SEMICONDUCTOR DEVICE

A semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on the active pattern; a bit line structure disposed on the active pattern, and including a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other, a lower spacer structure disposed on a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0170205 filed on Dec. 8, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Example embodiments of the present inventive concept relate to a semiconductor device. More particularly, example embodiments of the present inventive concept relate to a DRAM device.

DISCUSSION OF RELATED ART

Generally, in a DRAM device, a bit line structure may include a first conductive pattern, a barrier pattern, a second conductive pattern, a mask, an etch stop pattern and a capping pattern, which are sequentially stacked on each other, and a spacer structure may be formed on a sidewall of the bit line structure to prevent electrical short between the bit line structure and an adjacent contact plug.

However, as a width of the bit line structure becomes smaller to increase an integration degree of the DRAM device, the bit line structure may be tilted or broken. Additionally, an electrical short between the bit line structure and the contact plug may occur because a distance between the bit line structure and the contact plug might not be sufficiently large.

SUMMARY

According to example embodiments of the present inventive concept, a semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on an upper portion of the active pattern; a bit line structure disposed on the active pattern, wherein the bit line structure includes a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a lower spacer structure disposed on a lower portion of a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure, and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.

According to example embodiments of the present inventive concept, a semiconductor device includes: an active pattern disposed on a substrate; an isolation pattern disposed on the substrate, wherein the isolation pattern covers a sidewall of the active pattern; a gate structure disposed on an upper portion of the active pattern and an upper portion of the isolation pattern, wherein the gate structure extends in a first direction substantially parallel to an upper surface of the substrate; an insulation pattern structure disposed on the active pattern, the isolation pattern and the gate structure; a bit line structure extending on the active pattern and the insulation pattern structure in a second direction, wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction, and wherein the bit line structure includes a first conductive pattern structure, a second conductive pattern and an insulation structure sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate; a lower spacer structure disposed on a lower portion of a sidewall of the bit line structure, and including a first spacer, a second spacer and a third spacer; an upper spacer structure disposed on the lower spacer structure and on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, and spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the first conductive pattern structure includes a lower portion, a middle portion and an upper portion sequentially stacked on each other in the vertical direction, and wherein a first width, in the first direction, of the lower portion of the first conductive pattern structure is greater than a second width, in the first direction, of the middle portion of the first conductive pattern structure.

According to example embodiments of the present inventive concept, a semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on an upper portion of the active pattern, a bit line structure disposed on the active pattern, wherein the bit line structure includes a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a lower spacer structure disposed on a lower portion of a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, and disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the first conductive pattern includes: a lower portion contacting an upper surface of the active pattern; a middle portion disposed on the lower portion; and an upper portion disposed on the middle portion, wherein the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices, and wherein the lower spacer structure covers sidewalls of the lower portion and the middle portion of the first conductive pattern, and the upper spacer structure covers a sidewall of the upper portion of the first conductive pattern.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The above and other aspects and features of the semiconductor devices and the methods of manufacturing the same in accordance with example embodiments of the present inventive concept will become readily understood from detail descriptions that follow, with reference to the accompanying drawings. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structure and/or processes, these various materials, layers, regions, pads, electrodes, patterns, structure and/or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Thus, “first”, “second” and/or “third” may be used selectively or interchangeably for each material, layer, region, electrode, pad, pattern, structure or process respectively.

Hereinafter, two directions among horizontal directions that are substantially parallel to an upper surface of a substrate100, which may be substantially orthogonal to each other, may be referred as first and second directions D1and D2, respectively, and a direction among the horizontal directions, which may have an acute angle with respect to each of the first and second directions D1and D2, may be referred to as a third direction D3. Additionally, a direction substantially perpendicular to the upper surface of the substrate100may be referred to as a vertical direction.

FIG.1is a plan view illustrating a semiconductor device in accordance with example embodiments of the present inventive concept, andFIG.2is a cross-sectional view taken along line A-A′ ofFIG.1.

Referring toFIGS.1and2, the semiconductor device may include an active pattern105, an isolation pattern110, a gate structure160, a bit line structure395, a first lower spacer structure430, an upper spacer structure465, a seventh spacer485, a contact plug structure and a capacitor640on a substrate100.

The semiconductor device may further include first and second insulation pattern structures235and590, a second etch stop pattern600and a second capping pattern480.

The active pattern105may extend in the third direction D3, and a plurality of active patterns105may be spaced apart from each other in the first and second directions D1and D2. A sidewall of the active pattern105may be covered by the isolation pattern110. The active pattern105may include substantially the same material as that of the substrate100, and the isolation pattern110may include an oxide, e.g., silicon oxide.

Referring toFIGS.1and2together withFIG.4, the gate structure160may be formed in a second recess extending in the first direction D1through upper portions of the active pattern105and the isolation pattern110. The gate structure160may include a gate insulation pattern130, a gate electrode140, and a gate mask150. The gate insulation pattern130may be disposed on a bottom and a sidewall of the second recess, and the gate electrode140may be disposed on a portion of the gate insulation pattern130that is disposed on the bottom and a lower sidewall of the second recess. The gate mask150may be disposed on the gate electrode140and may fill an upper portion of the second recess.

The gate insulation pattern130may include an oxide, e.g., silicon oxide. The gate electrode140may include, e.g., a metal, a metal nitride, a metal silicide, etc., and the gate mask150may include an insulating nitride, e.g., silicon nitride.

In example embodiments of the present inventive concept, the gate structure160may extend in the first direction D1, and a plurality of gate structures160may be spaced apart from each other in the second direction D2.

Referring toFIGS.1and2together withFIGS.5and6, a first opening240extending through an insulating layer structure230and exposing upper surfaces of the active pattern105may be formed. In addition, the isolation pattern110and the gate mask150of the gate structure160may be formed, and an upper surface of a central portion in the third direction D3of the active pattern105may be exposed by the first opening240.

In example embodiments of the present inventive concept, an area of a bottom of the first opening240may be greater than an area of the upper surface of the active pattern105. Thus, the first opening240may also expose an upper surface of a portion of the isolation pattern110that is adjacent to the active pattern105. Additionally, the first opening240may extend through an upper portion of the active pattern105and the portion of the isolation pattern110adjacent thereto, and thus, the bottom of the first opening240may be lower than an upper surface of each of opposite edge portions in the third direction D3of the active pattern105.

In example embodiments of the present inventive concept, the first opening240may be spaced apart from each other in the first and second directions D1and D2.

In example embodiments of the present inventive concept, the bit line structure395may extend in the second direction D2on the substrate100, and a plurality of bit line structures395may be spaced apart from each other in the first direction D1. The bit line structure395may include a first conductive pattern255, a first barrier pattern265, a third conductive pattern275, a second mask285, a first etch stop pattern365and a first capping pattern385sequentially stacked in the vertical direction on the first opening240, and the bit line structure395may include a second conductive pattern259, the first barrier pattern265, the third conductive pattern275, the second mask285, the first etch stop pattern365and the first capping pattern385sequentially stacked in the vertical direction on the first insulation pattern structure235at an outside the first opening240.

The first conductive pattern255may have a lower portion255a, a middle portion255b, and an upper portion255c. The lower portion255amay be disposed at a lower portion of the first opening240and contacting an upper surface of a central portion of the active pattern105. The middle portion255bmay be disposed on the lower portion255a, and an upper portion255cmay be disposed on the middle portion255b. The lower portion255aand the middle portion255bof the first conductive pattern255may be disposed within the first opening240. The upper portion255cof the first conductive pattern255may protrude upwardly from the first opening240, and an upper surface of the middle portion255bof the first conductive pattern255may be substantially coplanar with an upper surface of the third insulating pattern225.

In example embodiments of the present inventive concept, each of the lower portion255aand the middle portion255bof the first conductive pattern255may have a shape of, for example, a circle, a square, or a square with rounded vertices in a plan view. Accordingly, each of the lower portion255aand the middle portion255bof the first conductive pattern255may have the shape of, for example, a cylinder, a square pillar, or a square pillar with rounded vertices.

In an example embodiment of the present inventive concept, as the lower portion255aand the middle portion255bof the first conductive pattern255, the upper portion255cof the first conductive pattern255may have a shape of, for example, a circle, a square or a square with rounded vertices in a plan view. Accordingly, the upper portion255cof the first conductive pattern255may have, for example, a shape of a cylinder, a square pillar, or a square pillar with rounded vertices.

In an example embodiment of the present inventive concept, the upper portion255cof the first conductive pattern255may have a shape of a rectangle of which a width in the second direction D2is larger than a width in the first direction D1, or a shape of a rectangle with rounded vertices. Accordingly, the upper portion255cof the first conductive pattern255may have a shape of, for example, a rectangular pillar or a rectangular pillar with rounded vertices.

The lower portion255aof the first conductive pattern255may have a first width W1in the first direction D1, and each of the middle portion255band the upper portion255cof the first conductive pattern255may have a second width W2in the first direction D1. In an example embodiment of the present inventive concept, the second width W2may be smaller than the first width W1. In an example embodiment of the present inventive concept, the second width W2may be substantially the same as the first width W1.

In example embodiments of the present inventive concept, a plurality of first conductive patterns255may be spaced apart from each other in the second direction D2, and the second conductive pattern259may be formed between and contact ones of the first conductive patterns255adjacent to each other in the second direction D2. In example embodiments of the present inventive concept, an upper surface of the second conductive pattern259and an upper surface of the first conductive pattern255may be substantially coplanar to each other.

In example embodiments of the present inventive concept, each of the first and second conductive patterns255and259may include polysilicon doped with n-type impurities, for example, phosphorus(P), arsenic(As), etc. In an example embodiment of the present inventive concept, the first and second conductive patterns255and259may include the same material as each other, that is, polysilicon doped with the same impurities, and accordingly, the first and second conductive patterns255and259may be merged with each other and not distinguished from each other. In an example embodiment of the present inventive concept, the first and second conductive patterns255and259may include different materials from each other, that is, polysilicon doped with different impurities, and thus, the first and second conductive patterns255and259may be distinguished from each other.

The first and second conductive patterns255and259may collectively form a conductive pattern structure, and the conductive pattern structure, the first barrier pattern265and the third conductive pattern275may collectively form a conductive structure. The second mask285, the first etch stop pattern365and the first capping pattern385may collectively form an insulation structure.

For example, the first barrier pattern265may include a metal nitride, e.g., titanium nitride, or a metal silicon nitride, e.g., titanium silicon nitride. For example, the third conductive pattern275may include a metal, e.g., tungsten, and each of the second mask285, the first etch stop pattern365and the first capping pattern385may include an insulating nitride, e.g., silicon nitride.

The first lower spacer structure430may be disposed in the first opening240, and may contact a sidewall of the first opening240and sidewalls of the lower portion255aand the middle portion255bof the first conductive pattern255. The first lower spacer structure430may include first to third spacers245,415and425.

The first spacer245may cover a lower sidewall of the first opening240and the sidewall of the lower portion255aof the first conductive pattern255. In example embodiments of the present inventive concept, the first spacer245may include air.

The second spacer415may cover the sidewall of the middle portion255bof the first conductive pattern255and an upper surface of the first spacer245, and the third spacer425may be disposed on the second spacer415, so that an inner sidewall and a bottom of the third spacer245may be covered by the second spacer415. The second spacer415may include, for example, silicon oxide, silicon carbonitride, or metal oxide, and the third spacer425may include, for example, an insulating nitride such as silicon nitride.

The first insulation pattern structure235may be formed on the active pattern105and the isolation pattern110under the bit line structure395, and may include first, second and third insulation patterns205,215and225sequentially stacked on each other in the vertical direction. The first and third insulation patterns205and225may include an oxide, e.g., silicon oxide, and the second insulation pattern215may include an insulating nitride, e.g., silicon nitride.

The contact plug structure may include a lower contact plug475, a metal silicide pattern490and an upper contact plug555sequentially stacked on each other in the vertical direction on the active pattern105and the isolation pattern110.

The lower contact plug475may contact the upper surface of each of opposite edge portions in the third direction D3of the active pattern105. In example embodiments of the present inventive concept, a plurality of lower contact plugs475may be spaced apart from each other in the second direction D2, and a second capping pattern480may be formed between neighboring ones of the lower contact plugs475in the second direction D2. For example, the second capping pattern480may include an insulating nitride, e.g., silicon nitride.

The upper contact plug555may include a second metal pattern545and a second barrier pattern535that covers a lower surface of the second metal pattern545. For example, the second metal pattern545may include a metal, e.g., tungsten, and the second barrier pattern535may include a metal nitride, e.g., titanium nitride.

In example embodiments of the present inventive concept, a plurality of upper contact plugs555may be spaced apart from each other in the first and second directions D1and D2, and may be arranged in a honeycomb pattern or a lattice pattern in a plan view. Each of the upper contact plugs555may have a shape of, e.g., a circle, an ellipse, or a polygon in a plan view.

The upper spacer structure465may include a fourth spacer445covering an upper sidewall of the bit line structure395, that is, a sidewall of the upper portion255cof the first conductive pattern255, an upper sidewall of the middle portion255bof the first conductive pattern255, sidewalls of the first barrier pattern265, the third conductive pattern275, the second mask285, the first etch stop pattern365and the first capping pattern385, a sidewall of the third insulation pattern225and an upper surface of the first lower spacer structure430. The upper spacer structure465may further include a fifth spacer455that may be disposed on a lower portion of an outer sidewall of the fourth spacer445. The upper spacer structure465may additionally include a sixth spacer460that may be disposed on an outer sidewall of the fifth spacer455, a sidewall of the first insulation structure235and a portion of an upper sidewall of the first lower spacer structure430.

In example embodiments of the present inventive concept, a cross-section in the first direction D1of the fourth spacer445may have an “L” shape.

For example, each of the fourth and sixth spacers445and460may include an insulating nitride, e.g., silicon nitride, and the fifth spacer455may include an oxide or air.

The seventh spacer485may cover an outer sidewall of a portion of the fourth spacer445, which is on the upper sidewall of the bit line structure395, an upper surface of the fifth spacer455and an upper surface and an upper portion of an outer sidewall of the sixth spacer465. For example, the seventh spacer485may include an insulating nitride, e.g., silicon nitride.

Referring toFIGS.1and2together withFIGS.27and28, the second insulation pattern structure590may include a fourth insulation pattern570and a fifth insulation pattern580. The fourth insulation pattern570may be disposed on an inner wall of a sixth opening560, which may extend through the upper contact plug555, a portion of the insulation structure of the bit line structure395and a portion of upper spacer structure465and may at least partially surround the upper contact plug555in a plan view. The fifth insulation pattern580may be disposed on the fourth insulation pattern570and may fill a remaining portion of the sixth opening560.

If the fifth spacer455includes air, a top end of the air spacer435may be closed by the fourth insulation pattern570.

For example, the fourth and fifth insulation patterns570and580may include an insulating nitride, e.g., silicon nitride.

The second etch stop pattern600may be disposed on the second insulation pattern structure590. For example, the second etch stop pattern600may include, an insulating nitride, e.g., silicon boronitride, silicon nitride, etc.

The capacitor640may be disposed on the upper contact plug555. The capacitor640may include a lower electrode610having a shape of a pillar or a cylinder, a dielectric layer620on a surface of the lower electrode610, and an upper electrode630on the dielectric layer620.

For example, the lower electrode610may include, e.g., a metal, a metal nitride, a metal silicide, polysilicon doped with impurities, etc. For example, the dielectric layer620may include, e.g., a metal oxide, and the upper electrode630may include, e.g., a metal, a metal nitride, a metal silicide, silicon-germanium (SiGe) doped with impurities, etc.

In the semiconductor device, the first spacer245and the first lower spacer structure may be disposed between the first conductive pattern255of the bit line structure395in the first opening240and the lower contact plug475, and accordingly, the first conductive pattern255and the lower contact plug475may be electrically insulated from each other. For example, as illustrated with reference toFIGS.3to28, the first conductive pattern255might not contact a sidewall of the first opening240due to the first spacer245, and thus an electrical short between the bit line structure395and the lower contact plug475may be prevented.

Additionally, the first spacer245may include air that has a low dielectric constant, so that parasitic capacitance between the bit line structure395and the lower contact plug475may be reduced.

FIGS.3to28are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments of the present inventive concept.

For example,FIGS.3,5,13,22and26are the plan views,FIG.4includes cross-sectional views taken along lines A-A′ and B-B′ ofFIG.3, andFIGS.6-12,14-21,23-25and27-28are cross-sectional views taken along lines A-A′, respectively, of corresponding plan views.

Referring toFIGS.3and4, an upper portion of a substrate100may be removed to form a first recess, and an isolation pattern110may be formed in the first recess.

As the isolation pattern110is formed on the substrate100, an active pattern105of which a sidewall is covered by the isolation pattern110may be defined.

The active pattern105and the isolation pattern110on the substrate100may be partially etched to form a second recess extending in the first direction D1, and a gate structure160may be formed in the second recess. In example embodiments of the present inventive concept, the gate structure160may extend in the first direction D1, and a plurality of gate structures160may be spaced apart from each other in the second direction D2.

Referring toFIGS.5and6, an insulating layer structure230may be formed on the active pattern105, the isolation pattern110, and the gate structure160. The insulating layer structure230may include first to third insulating layers200,210, and220sequentially stacked on each other.

The insulating layer structure230may be patterned, and the active pattern105, the isolation pattern110, and the gate mask150included in the gate structure160may be partially etched by using the patterned insulating layer structure230as an etching mask to form a first opening240. In example embodiments of the present inventive concept, the insulating layer structure230may have a circular shape or an elliptical shape in a plain view, and a plurality of insulating layer structures230may be spaced apart from each other in the first and second directions D1and D2. Each of the insulating layer structures230may overlap end portions of ones of the active patterns105neighboring in the third direction D3, which may face each other, in a vertical direction substantially orthogonal to the upper surface of the substrate100.

Referring toFIG.7, a sacrificial spacer layer241may be formed on the first insulating layer structure230, the active pattern105, the isolation pattern110and the gate structure160that are exposed by the first opening240.

The sacrificial spacer layer241may include a polymer that decomposes at a low temperature, for example, below about 300° C., and the sacrificial spacer layer241may include carbon(C).

Referring toFIG.8, an anisotropic etching process may be performed on the sacrificial spacer layer241, and a portion of the sacrificial spacer layer241, which is on an upper surface of the first insulating layer structure230and an upper surface of the active pattern105that is exposed by the first opening240, may be removed to form a sacrificial spacer243.

The sacrificial spacer243may be formed to cover a sidewall of the first opening240, and the upper surface of the active pattern105may be partially exposed again without being covered by the sacrificial spacer243.

Referring toFIG.9, a first conductive layer250may be formed on the first insulating layer structure230, the sacrificial spacer243and the partially exposed upper surface of the active pattern105to fill a remaining portion of the first opening240.

In example embodiments of the present inventive concept, a portion of the first conductive layer250in the first opening240, that is, a lower portion of the first conductive layer250may have a shape of, for example, a circle, a square or a square with rounded vertices in a plan view, and may have a first width W1in the first direction D1.

In example embodiments of the present inventive concept, the first conductive layer250may include polysilicon doped with n-type impurities, for example, phosphorus (P) or arsenic (As).

Referring toFIG.10, a first mask layer and a photoresist layer may be sequentially formed on the first conductive layer250. The photoresist layer may be patterned to form a photoresist pattern253, and the first mask layer may be etched by using the photoresist pattern253as an etching mask to form the first mask251.

In example embodiments of the present inventive concept, the first mask251may have the first width W1in the first direction D1, and may overlap, in the vertical direction, the first conductive layer250. In an example embodiment of the present inventive concept, the first mask251may have a shape of a circle, a square, or a square with rounded vertices in a plan view. In an example embodiment of the present inventive concept, the first mask251may have a shape of rectangle or a rectangle with rounded vertices having a length in the second direction D2greater than a length in the first direction D1in a plan view.

In example embodiments of the present inventive concept, the first mask251may have a multi-layer structure including a plurality of layers stacked in the vertical direction.

Referring toFIG.11, after removing the photoresist pattern253, the first conductive layer250may be patterned by performing a first etching process using the first mask251as an etching mask. Accordingly, the first conductive layer250may be transformed into a first preliminary conductive pattern253.

The first etching process may be performed by, for example, a dry etching process.

In example embodiments of the present inventive concept, the first preliminary conductive pattern253may include a lower portion, which is disposed in the first opening240, and an upper portion that is disposed on the lower portion and positioned higher than an upper surface of the sacrificial spacer243and the upper surface of the first insulating layer structure230. The first preliminary conductive pattern253may have the first width W1in the first direction D1.

In an example embodiment of the present inventive concept, the upper portion of the first preliminary conductive pattern253may have a shape of a circle, a square or a square with rounded vertices in a plan view. In this case, the upper portion of the first preliminary conductive pattern253may have substantially the same shape as the lower portion of the first preliminary conductive pattern253.

In another example embodiment of the present inventive concept, the upper portion of the first preliminary conductive pattern253may have a shape of a rectangle, or rectangle with rounded vertices having a length in the second direction D2greater than a length in the first direction D1in a plan view. In this case, the upper portion of the first preliminary conductive pattern253may have a different shape from the lower portion of the first preliminary conductive pattern253.

Referring toFIG.12, after forming a second conductive layer257on the first insulating layer structure230and the first preliminary conductive pattern253, an upper portion of the second conductive layer257may be planarized until an upper surface of the first preliminary conductive pattern253is exposed.

The second conductive layer257may include, for example, polysilicon doped with n-type impurities, for example, phosphorus(P) or arsenic(As). In an example embodiment of the present inventive concept, the second conductive layer257may include substantially the same material as the first preliminary conductive pattern253, and thus, the first preliminary conductive pattern253and the second conductive layer257may be merged with each other. In an example embodiment of the present inventive concept, the second conductive layer257may include a different material from the first preliminary conductive pattern253, and thus, the first preliminary conductive pattern253and the second conductive layer257may be distinguished from each other.

A first barrier layer260, a third conductive layer270and a second mask layer280may be sequentially formed on the first preliminary conductive pattern253and the second conductive layer257. The first preliminary conductive pattern253, the second conductive layer257, the first barrier layer260, the third conductive layer270and the second mask layer280may collectively form a conductive structure layer.

Referring toFIGS.13and14, a first etch stop layer and a first capping layer may be sequentially formed on the conductive structure layer. The first capping layer may be etched to form a first capping pattern385, and the first etch stop layer, the first mask layer280, the third conductive layer270, the first barrier layer260and the first conductive layer250may be sequentially etched by a second etching process using the first capping pattern385as an etching mask.

In example embodiments of the present inventive concept, the first capping pattern385may extend in the second direction D2, and a plurality of first capping patterns385may be spaced apart from each other in the first direction D1. The first capping pattern385may have a second width W2in the first direction D1. In an example embodiment of the present inventive concept, the second width W2may be smaller than the first width W1. In an example embodiment of the present inventive concept, the second width W2may be substantially the same as the first width W1.

During the second etching process, an upper portion of the sacrificial spacer243may be exposed, and the exposed upper portion of the sacrificial spacer243may also be removed. Accordingly, the sacrificial spacer243may remain at a lower portion of the first opening240.

If the second width W2of the first capping pattern385is smaller than the first width W1of the first preliminary conductive pattern253, the upper portion of the first preliminary conductive pattern253and an upper portion of the lower portion (e.g., a middle portion) of the first preliminary conductive pattern243may also be partially removed, and the first preliminary conductive pattern253may be transformed into a first conductive pattern255. Accordingly, the lower portion of the first preliminary conductive pattern243may be divided into a lower portion255aand a middle portion255bof the first conductive pattern255, and the upper portion of the first preliminary conductive pattern243may be transformed into an upper portion255cof the first conductive pattern255. The lower portion255aof the first conductive pattern255may have the first width W1in the first direction D1, and the middle portion255bof the first conductive pattern255may have the second width W2in the first direction D1. The upper portion255cof the first conductive pattern255may have the second width W2in the first direction D1.

However, if the second width W2of the first capping pattern385is substantially the same as the first width W1of the first preliminary conductive pattern253, the upper portion and the upper portion of the lower portion (e.g., the middle portion) the first preliminary conductive pattern253might not be partially removed during the second etching process, and accordingly, the lower portion255a, the middle portion255band the upper portion255cof the first conductive pattern255, which may be formed by the second etching process, may have a substantially same width in the first direction D1, that is, the first width W1or the second width W2as each other.

InFIG.14, after performing the second etching process, the upper surface of the sacrificial spacer243remaining in the first opening240may be substantially coplanar with an upper surface of the lower portion255aof the first conductive pattern255. However, the present inventive concept is not limited thereto, and the upper surface of the sacrificial spacer243may be formed to be higher or lower than the upper surface of the lower portion255aof the first conductive pattern255.

During the second etching process, the third insulating layer220under the second conductive layer257may also be partially etched and remain as a third insulation pattern225.

By the second etching process, the first conductive pattern255, a first barrier pattern265, a third conductive pattern275, a second mask285, a first etch stop pattern365and the first capping pattern385may be sequentially stacked on the first opening240, and the third insulation pattern225, the first conductive pattern255, the first barrier pattern265, the third conductive pattern275, the second mask285, the first etch stop pattern365and the first capping pattern385may be sequentially stacked on the second insulating layer210of the insulating layer structure230at an outside of the first opening240.

Hereinafter, the first and second conductive patterns255and259, the first barrier pattern265, the third conductive pattern275, the second mask285, the first etch stop pattern365and the first capping pattern385sequentially stacked on each other may be referred to as a bit line structure395. The first and second conductive patterns255and259, the first barrier pattern265and the third conductive pattern275may collectively form a conductive structure, and the second mask285, the first etch stop pattern365and the first capping pattern385may collectively form an insulation structure.

In example embodiments of the present inventive concept, the bit line structure395may extend in the second direction D2, and a plurality of bit line structures395may be spaced apart from each other in the first direction D1.

As described above, if the first and second conductive patterns255and259include substantially the same material as each other, the first and second conductive patterns255and259may be merged with each other, and if the first and second conductive patterns255and259include different materials from each other, the first and second conductive patterns255and259may be distinguished from each other.

Referring toFIG.15, a second spacer layer410may be formed on the substrate100and on the bit line structure395.

In example embodiments of the present inventive concept, the second spacer layer410may be formed by, for example, a deposition process such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma deposition process, etc. The second spacer layer410may formed on an upper surface and a sidewall of the bit line structure395, the upper surface of the sacrificial spacer243and sidewalls of the first and second insulating layers200and210and the third insulating pattern225.

The second spacer layer410may include, for example, silicon oxide, silicon carbonitride, or metal oxide.

Referring toFIG.16, a heat treatment process may be performed on the substrate100to remove the sacrificial spacer243that includes a polymer which decomposes at a low temperature, for example, equal to or less than about 300° C.

Accordingly, a first spacer245may be formed in a space from which the sacrificial spacer243is removed, that is, in a space surrounded or enclosed by a lower sidewall of the first opening240, a sidewall of the lower portion255aof the first conductive pattern255, and a lower surface of a portion of the first spacer layer410in the first opening240. The first spacer245may include air with a low dielectric constant.

Referring toFIG.17, a third spacer layer may be formed on the second spacer layer410, and an upper portion of the third spacer layer may be etched to form a third spacer425that fills a remaining portion of the first opening240.

The third spacer layer may be formed by, for example, a deposition process such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, etc., and may include a nitride, for example, silicon nitride.

Referring toFIG.18, a portion of the second spacer layer410, which is disposed on an upper surface of the second insulating layer210and an upper sidewall and the upper surface of the bit line structure395, may be partially removed by performing a wet etching process and/or a dry etching process.

Accordingly, the upper sidewall and the upper surface of the bit line structure395may be exposed, and the second spacer layer410may be transformed to a second spacer415that covers a lower surface of the third spacer425. The first to third spacers245,415and425may collectively form a first lower spacer structure430.

Referring toFIG.19, a fourth spacer layer440and a fifth spacer layer453may be sequentially formed on the exposed upper sidewall and the exposed upper surface of the bit line structure395, the sidewall of the third insulation pattern225, an upper surface of the first lower spacer structure430and the upper surface of the second insulating layer210.

Referring toFIG.20, the fourth and fifth spacer layers440and453may be anisotropically etched to form fourth and fifth spacers445and455, respectively, on the sidewall of the bit line structure395, the sidewall of the third insulation pattern225and the upper surface of the first lower spacer structure430.

A dry etching process may be performed using the first capping pattern385and the fourth and fifth spacers445and455as an etching mask to partially remove the first and second insulating layers200and210, and an upper portion of the active pattern105and upper portions of the isolation pattern110and the gate mask150adjacent thereto may also be removed by the dry etching process to form a second opening450.

By the dry etching process, the first and second insulating layers200and210may be partially removed to remain as first and second insulation patterns205and215, respectively, under the bit line structure395. The first to third insulation patterns205,215and225sequentially stacked on each other under the bit line structure395may form a first insulation pattern structure.

Referring toFIG.21, a sixth spacer layer may be formed on an upper surface of the first capping pattern385, an upper surface of the fourth spacer445, an upper surface and an outer sidewall of the fifth spacer455, a portion of the upper surface of the first lower spacer structure430, and upper surfaces of the active pattern105, the isolation pattern110and the gate mask150that are exposed by the second opening450. The sixth spacer layer may be anisotropically etched to form a sixth spacer460on the outer sidewall of the fifth spacer455and on the portion of the upper surface of the first lower spacer structure430.

The fourth to sixth spacers445,455and460, which are sequentially stacked on the sidewall of the bit line structure395in the horizontal direction, may be referred to as an upper spacer structure465.

A sacrificial layer may be formed to fill the second opening450on the substrate100to a sufficient height, and an upper portion of the sacrificial layer may be planarized until the upper surface of the first capping pattern385is exposed to form a sacrificial pattern470in the second opening450.

In example embodiments of the present inventive concept, the sacrificial pattern470may extend in the second direction D2, and a plurality of sacrificial patterns470may be spaced apart from each other in the first direction D1by the bit line structures395. The sacrificial pattern470may include, for example, an oxide such as silicon oxide.

Referring toFIGS.22and23, a third mask including a plurality of third openings, each of which may extend in the first direction D1and may be spaced apart from each other in the second direction D2may be formed on the first capping pattern385, the sacrificial pattern470and the upper spacer structure465, and the sacrificial pattern470may be etched by using the third mask as an etching mask.

In example embodiments of the present inventive concept, each of the third openings may overlap the gate structures160in the vertical direction. By the etching process, a fourth opening exposing upper surfaces of the gate structures160may be formed between the bit line structures395on the substrate100. The sacrificial pattern470extending in the second direction D2between the bit line structures395may be divided into a plurality of pieces in the second direction D2.

After removing the third mask, a second capping pattern480may be formed to fill the fourth opening.

The sacrificial pattern470may be removed to form a fifth opening exposing the upper surface of the active pattern105and an upper portion of the isolation pattern110adjacent thereto, and a lower contact plug layer may be formed on the first and second capping patterns385and480and the upper spacer structure465, and an upper portion of the lower contact plug475may be planarized until upper surfaces of the first and second capping patterns385and480and the upper spacer structure465are exposed.

Accordingly, the lower contact plug layer extending in the second direction D2between the bit line structures395may be divided into a plurality of lower contact plugs475spaced apart from each other in the second direction D2.

Referring toFIG.24, an upper portion of the lower contact plug475may be removed to expose an upper portion of the upper spacer structure465on the sidewall of the bit line structure395, and upper portions of the fifth and sixth spacers455and460of the exposed upper spacer structure465may be removed.

An upper portion of the lower contact plug475may be additionally removed. Thus, an upper surface of the lower contact plug475may be lower than upper surfaces of the fifth and sixth spacers455and460.

A seventh spacer layer may be formed on the bit line structure395, the upper spacer structure465, the second capping pattern480and the lower contact plug475, and may be anisotropically etched to form a seventh spacer485covering an upper portion of the upper spacer structure465on the sidewall of the bit line structure395, and the upper surface of the lower contact plug475may be exposed by the etching process.

A metal silicide pattern490may be formed on the exposed upper surface of the lower contact plug475. In example embodiments of the present inventive concept, the metal silicide pattern490may be formed by forming a first metal layer on the first and second capping patterns385and480, the seventh spacer485and the lower contact plug475, by performing a heat treatment thereon, and by removing an unreacted portion of the first metal layer.

Referring toFIG.25, a second barrier layer530may be formed on the first and second capping patterns385and480, the seventh spacer485, the metal silicide pattern490and the lower contact plug475, and a second metal layer540may be formed on the second barrier layer530to fill a space between adjacent bit line structures395.

A planarization process may be performed on an upper portion of the second metal layer540. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and/or an etch-back process.

Referring toFIGS.26and27, the second metal layer540and the second barrier layer530may be patterned to form an upper contact plug555. In example embodiments of the present inventive concept, a plurality of upper contact plugs555may be formed, and a sixth opening560may be formed between adjacent upper contact plugs555.

The sixth opening560may be formed by partially removing the first and second capping patterns385and480, the upper spacer structure465and the seventh spacer485as well as the second metal layer540and the second barrier layer530. In example embodiments of the present inventive concept, the upper contact plug555may be arranged, for example, in a honeycomb pattern or in a lattice pattern in the first and second directions D1and D2, in a plan view.

The lower contact plug475, the metal silicide pattern490and the upper contact plug555, which are sequentially stacked on each other on the substrate100, may collectively form a contact plug structure.

Referring toFIG.28, a fourth insulation pattern570may be formed on a bottom and a sidewall of the sixth opening560, and a fifth insulation pattern580may be formed to fill a remaining portion of the sixth opening560. The fifth insulation pattern580may be disposed on the fourth insulation pattern570.

Each of the fourth and fifth insulation patterns570and580may form a second insulation pattern structure590.

In an example embodiment of the present inventive concept, before forming the fourth insulating pattern570, the fifth spacer455included in the upper spacer structure465exposed by the sixth opening560may be removed to form an air gap. In this case, a top end of the air gap may be covered by the fourth insulation pattern570, and thus, an air spacer435may be formed.

Referring toFIGS.1and2again, a capacitor contacting an upper surface of the upper contact plug555may be formed.

For example, a second etch stop pattern600and a mold layer may be sequentially formed on the second insulating pattern structure590and the upper contact plug555. In addition, a seventh opening may be formed to expose an upper surface of the upper contact plug555.

The seventh openings respectively exposing the upper contact plugs555may be arranged, depending on the arrangement of the upper contact plugs555, in a honeycomb pattern or a lattice pattern in a plan view.

A lower electrode610having a shape of a pillar or cylinder may be formed in the seventh opening. The mold layer may be removed, and a dielectric layer620and an upper electrode630may be sequentially formed on the lower electrode610and the second etch stop pattern600. The lower electrode610, the dielectric layer620and the upper electrode630may collectively form the capacitor640.

In some embodiments of the present inventive concept, the lower electrode610may have a shape of a cylinder in the seventh opening.

Upper wirings may be additionally formed on the capacitor640, and the manufacturing of the semiconductor device may be completed.

As illustrated above, the sacrificial spacer243including a polymer that decomposes at a low temperature may be formed on the sidewall of the first opening240. In addition, the first conductive layer250filling the remaining portion of the first opening240may be formed, and the upper portion of the first conductive layer250may be etched to form the first preliminary conductive pattern253. Thereafter, the second conductive layer257, the first barrier layer260, the third conductive layer270and the second mask layer280may be formed on the sacrificial spacer243and the first preliminary conductive pattern253, and may be patterned to form the bit line structure395.

For example, instead of forming the sacrificial spacer243and the first preliminary conductive pattern253in the first opening240, a conductive layer may be formed in the first opening240, and other layers, that is, the second conductive layer257, the first barrier layer260, the third conductive layer270and the second mask layer280, may be formed on the conductive layer. In this case, during an etching process for forming the bit line structure, a total thickness of layers to be etched during the pattering process may be so large that the underlying conductive layer might not be easily etched. For example, if a width of the first opening240is small, a portion of the conductive layer in the lower portion of the first opening240might not be etched to remain on the sidewall of the first opening240. Thus, an electrical short may occur between the conductive layer and the lower contact plug475adjacent thereto.

However, in example embodiments of the present inventive concept, the sacrificial spacer243may be formed on the sidewall of the first opening240to secure an internal space that may be spaced apart from the sidewall of the first opening240. In addition, the first conductive layer250may be formed within the internal space, and the upper portion of the first conductive layer250may be patterned to form the first preliminary conductive pattern253. Thus, the first preliminary conductive pattern253might not contact the sidewall of the first opening240, and accordingly, an electrical short between the lower contact plug475and the bit line structure395including the first conductive pattern255, to which the first preliminary conductive pattern253is transformed, may be prevented.

In addition, the first conductive pattern255of the bit line structure395within the first opening240might not be etched simultaneously with the overlying layers, but may be etched before etching the overlying layers. Therefore, the process for forming the bit line structure395may be performed easily, and tilting of the bit line structure395may be reduced or prevented.

In addition, the sacrificial spacer243may include a polymer that is easily decomposed at low temperature, and thus, the sacrificial spacer243may be converted into the first spacer245including air by a subsequent heat treatment process. Accordingly, the first spacer245including air with a low dielectric constant may be formed between the bit line structure395and the lower contact plug475, so that parasitic capacitance between the bit line structure395and the lower contact plug475may be reduced.

FIG.29is a cross-sectional view illustrating a semiconductor device in accordance to example embodiments of the present inventive concept.

This semiconductor device is substantially the same as or similar to the semiconductor device illustrated with reference toFIGS.1and2, except for further including an eighth spacer247, and thus, repeated explanations may be omitted or briefly discussed herein.

Referring toFIG.29, the semiconductor device may further include the eighth spacer247covering a lower surface of the first spacer425, and the first, second, third and eighth spacers245,415,425and247may collectively form a second lower spacer structure249.

Unlike processes illustrated withFIG.16, the sacrificial spacer241might not be completely removed by the heat treatment process, but may partially remain, and the remaining portion of the sacrificial spacer241may be referred to as the eighth spacer247. Thus, the eighth spacer247may include a material substantially the same as that of the sacrificial spacer241.

FIG.30is a cross-sectional view illustrating a semiconductor device in accordance to example embodiments of the present inventive concept.

This semiconductor device is substantially the same as or similar to the semiconductor device illustrated with reference toFIGS.1and2except for some elements, and thus, repeated explanations may be omitted or briefly discussed herein.

Referring toFIG.30, instead of including the first lower spacer structure430and the upper spacer structure465, the semiconductor device may include a second spacer415on a top end of the first spacer245and covering the sidewall of the bit line structure395except for the sidewall of the lower portion255aof the first conductive pattern255. The semiconductor device may further include a third spacer425disposed on a lower portion of an outer sidewall of the second spacer415, and a fourth spacer445disposed on the third spacer425and covering an upper portion of the outer sidewall of the second spacer415. The semiconductor device may additionally include a fifth spacer455disposed on a lower portion of an outer sidewall of the fourth spacer445, and a sixth spacer460disposed on an outer sidewall of the fifth spacer455. The semiconductor device may also include a seventh spacer485contacting an upper portion of the outer sidewall of the fourth spacer445, an upper surface of the fifth spacer455and an upper surface and an upper portion of an outer sidewall of the sixth spacer460.

FIG.31is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance to example embodiments of the present inventive concept.

This method is substantially the same as or similar to those illustrated with reference toFIGS.3and28andFIGS.1and2, and thus, repeated explanations may be omitted or briefly discussed herein.

Processes substantially the same as or similar to those illustrated with reference toFIGS.2to17may be performed.

Referring toFIG.31, unlike the processes illustrated with reference toFIGS.18and19, an etching process is not performed on the second spacer layer410, and the third and fourth spacer layers440and453may be formed.

Accordingly, the first spacer415may cover the upper sidewall and the upper surface of the bit line structure395.

Thereafter, processes substantially the same as or similar to those illustrated with reference toFIGS.20to28andFIGS.1and2may be performed to complete manufacturing of the semiconductor device.