Charge coupled device

A charge coupled device and a manufacturing method therefor are provided. The charge coupled device has a transfer electrode portion having a first gate electrode, a second gate electrode having an end portion partially overlapping an end portion of the first gate electrode, and a third gate electrode having one end portion partially overlapping the other end portion of the first gate electrode and the other end portion thereof partially overlapping the other end portion of the second gate electrode. The charge coupled device also has a charge transfer portion located in a semiconductor substrate under the first, second and third gate electrodes, which includes a first potential area formed in the semiconductor substrate under the second gate electrode and a second potential area formed in the semiconductor substrate under the third gate electrode. The charge coupled device further has a clock portion which includes a first clock terminal connected to the first and third gate electrodes, and a second clock terminal connected to the second gate electrode. This charge coupled device may prevent unnecessary local potential barriers or wells produced by a misalignment, and thus may provide increased charge transfer efficiency.

BACKGROUND OF THE INVENTION 
The present invention relates to a semiconductor device and a manufacturing 
method therefor, and more particularly, to a charge coupled device which 
enables charge transfer and a manufacturing method therefor. 
A charge coupled device (CCD), as a kind of charge transfer device, is a 
dynamic device which transfers charge via a predetermined path according 
to clock pulses applied to a gate electrode. The CCD is constituted of 
metal oxide semiconductor (MOS) transistors of which the gates are 
connected to one another in series. 
The CCD having the characteristic of charge transfer via a predetermined 
path is widely used as an image device which is combined with a group of 
photo-diodes arranged in parallel to the CCD in order to sense an optical 
signal. The CCD also finds its use in various fields of analog and digital 
signal processing, using its ability of charge accumulation and transfer. 
The first CCD suggested by Bell and Smith in 1969 includes an insulation 
layer and gate electrodes arranged to constitute a MOS capacitor on a 
semiconductor substrate. This simple planar arrangement of gate electrodes 
makes it difficult to control the shapes of a potential well under the 
gate electrodes. Therefore, a structure has been suggested in which a gate 
electrodes are isolated from one another while being partially overlapped 
with each other. The structure which has been most widely used is composed 
of a plurality of gate electrodes formed on a semiconductor substrate 
having insulation layers formed therebetween, and charge transfer areas 
formed under the gate electrodes. 
Charge-coupled devices are divided into a pseudo 2-phase CCD, a 3-phase 
CCD, and a 4-phase CCD according to a driving method, and the structural 
configurations of the CCDs are modified in accordance with their driving 
methods. Especially, the pseudo 2-phase CCD uses simple driving pulses 
despite its low capacity of charge transfer as compared with other 
configurations, thus it is widely used as a horizontal charge transfer 
device of a CCD-type image device requiring high speed operation. 
FIG. 1 is a sectional view of a conventional charge coupled device. 
The conventional charge coupled device has first gate electrodes 16 spaced 
from one another by a predetermined distance, second gate electrodes 18 
positioned between each first gate electrode 16, and potential areas 14 
formed under the second gate electrodes 18. A first clock terminal .phi.1 
is connected to a first gate electrode 16 and a second gate electrode 18 
which form a unit transfer group, and a second clock terminal .phi.2 is 
connected to a first gate electrode 16 and a second gate electrode 18 
which form another unit transfer group. 
The potential areas 14 are formed by ion implantation using the first gate 
electrodes 16 as a mask, and thus are aligned with the first gate 
electrodes 16. In addition, the potential areas 14 form potential wells in 
a charge transferring direction. 
Mutually opposite clock signals are applied to the first and second clock 
terminals .phi.1 and .phi.2. 
In FIG. 1, reference numeral 10 denotes a semiconductor substrate, 
reference numeral 12 denotes a buried channel for a buried CCD, and 
reference numeral 20 denotes an interlayer insulation layer. 
FIG. 2 is a potential distribution diagram explaining the migration of 
charge of the charge coupled device of FIG. 1. 
Charge stored in a potential well in the left side of FIG. 2 migrates to 
the right when a clock pulse is applied to the first and second clock 
terminals .phi.1 and .phi.2. In FIG. 2, an arrow indicates the direction 
of charge transfer. 
The aforementioned pseudo 2-phase CCD of FIG. 1 has limits in reducing the 
length of charge transfer groups due to the application of a single clock 
pulse to two gate electrodes. That is, a reduction in the length of a unit 
gate electrode is limited due to resolution limitation during 
photolithography. 
When as many transfer groups as possible are needed in an area of a given 
unit length as in a horizontal charge coupled device of a CCD-type image 
device, the above limits emerge as a serious problem. To avoid this 
problem, a method has been suggested in which a single gate electrode is 
used as a unit transfer group by forming a potential area below only half 
the area of each gate electrode, as shown in FIG. 3. 
FIG. 3 is a sectional view for explaining another conventional charge 
coupled device. 
The charge coupled device of FIG. 3 is the same as that of FIG. 2 in terms 
of the arrangement of the first and second gate electrodes 16 and 18. 
However, a potential area 15 is formed under each of the first and second 
gate electrodes 16 and 18. Furthermore, a single gate electrode is 
connected to each of the clock terminals .phi.1 and .phi.2. 
Therefore, according to the charge coupled device of FIG. 3, the size of 
the area reserved for the charge coupled device can be reduced by at least 
half of the area of the charge coupled device of FIG. 1. That is, assuming 
that the sizes of horizontal charge transfer devices of a CCD-type image 
device are the same, the case of FIG. 3 can secure twice as many transfer 
groups as compared with the case of FIG. 1. 
Meanwhile, in the case of the charge coupled device of FIG. 3, in order to 
form the potential area 15, ion implantation should be performed after an 
ion implantation mask is formed using photolithography. In this case, it 
is impossible to align each potential area 15 with each of the gate 
electrodes 16 and 18. Thus, there is a likelihood that an unnecessary 
local potential barrier or well is formed due to the misalignment of a 
potential area and a gate electrode at a gate electrode boundary, thereby 
lowering charge transfer efficiency. 
SUMMARY OF THE INVENTION 
An object of the present invention is to provide a charge coupled device in 
which a potential area is formed to be aligned with a gate electrode and 
the area occupied by a unit transfer group is reduced. 
Another object of the present invention is to provide a method for 
manufacturing the above charge coupled device. 
To achieve the above object, there is provided a charge coupled device 
comprising: a transfer electrode portion having a first gate electrode, a 
second gate electrode having an end portion partially overlapping an end 
portion of the first gate electrode, and a third gate electrode having one 
end portion partially overlapping the other end portion of the first gate 
electrode and the other end portion thereof partially overlapping the 
other end portion of the second gate electrode; a charge transfer portion 
located in a semiconductor substrate under the first to third gate 
electrodes, and having a first potential area partially formed in the 
semiconductor substrate under the second gate electrode and a second 
potential area formed in the semiconductor substrate under the third gate 
electrode; and a clock portion having a first clock terminal 
simultaneously connected to the first and third gate electrodes, and a 
second clock terminal connected to the second gate electrode. 
It is preferable that the length of the second gate electrode is equal to 
the sum of the lengths of the first and third gate electrodes. 
It is preferable that the size of the first potential area is the same as 
that of the second potential area. 
It is preferable that an end portion of the first potential area is aligned 
with an end portion of the first gate electrode, and the end portions of 
the second potential area are aligned with end portions of the first and 
second gate electrodes. 
To achieve another object, there is provided a method for manufacturing a 
charge coupled device comprising the steps of: (a) forming a gate 
insulation layer on the overall surface of a semiconductor substrate; (b) 
forming a first gate electrode on the resultant structure having the gate 
insulation layer formed thereon; (c) coating the surface of the first gate 
electrode with a first insulation layer; (d) forming a photoresist pattern 
on the resultant structure including the first insulation layer, for 
exposing a portion of the first gate electrode and an area reserved for 
the formation of a second gate electrode; (e) forming a first potential 
area by implanting impurity ions, using the photoresist pattern as an ion 
implantation mask; (f) forming the second gate electrode on the area 
reserved for forming the second gate electrode so that an end portion 
thereof partially overlapping an end portion of the first gate electrode; 
(g) coating the surface of the second gate electrode with a second 
insulation layer; (h) forming a second potential area in the semiconductor 
substrate for forming the third gate electrode therein by implanting 
impurity ions, using the first and second gate electrodes as an ion 
implantation mask; (i) forming a third gate electrode on the area reserved 
for forming the third gate electrode so that an end portion thereof 
overlaps the other end portion of the first gate electrode and an end 
portion thereof partially overlaps the other end portion of the second 
gate electrode; and (j) connecting the first and third gate electrodes to 
a first clock terminal, and connecting the third gate electrode to a 
second clock terminal. 
It is preferable the size of the first potential area is the same as that 
of the second potential area. 
It is preferable that the second potential area is formed of impurity ions 
of the same type and concentration as that of impurity ions of the first 
potential area. 
It is preferable to add the step of forming a buried channel layer near the 
surface of the semiconductor substrate, before the step (a). 
Therefore, according to the charge coupled device and the manufacturing 
method therefor, the area occupied by a unit transfer group can be reduced 
and a potential area is formed to be aligned with a gate electrode.

DETAILED DESCRIPTION OF THE INVENTION 
A charge coupled device shown in FIG. 4 has a transfer electrode portion, a 
charge transfer portion, and a clock portion. 
Transfer Electrode Portion 
The transfer electrode portion has a plurality of first gate electrodes 36, 
a plurality of second gate electrodes 46 each having an end portion 
partially overlapping one end portion of each first gate electrode 36, and 
a plurality of third gate electrodes 54 having one end portion partially 
overlapping the other end portion of each first gate electrode 36 and the 
other end portion partially overlapping the other end portion of each 
second gate electrode 46. 
Charge Transfer Portion 
The charge transfer portion has a plurality of first potential areas 44 
formed in a semiconductor substrate under the second gate electrode 46, 
and a plurality of second potential areas 52 formed in the semiconductor 
substrate under the third gate electrode 54. 
Clock Portion 
The clock portion has a plurality of first clock terminals .phi.1 
simultaneously connected to each first and third gate electrode 36 and 54, 
and a plurality of second clock terminals .phi.2 connected to each second 
gate electrode 46. 
The length of each second gate electrode 46 is equal to the sum of the 
lengths of the first and third gate electrodes 36 and 54, and the 
configuration and size of each first potential area 44 is the same as that 
of each second potential area 52. 
In addition, an end portion of each first potential area 44 is aligned with 
an end portion of each first gate electrode 36, and the second potential 
area 52 are aligned with the first gate electrodes 36 and the second gate 
electrode 46. 
The first and second potential areas 44 and 52 form a potential well in a 
charge transferring direction, and mutually opposite clock signals are 
applied to the first and second clock terminals .phi.1 and .phi.2. 
According to the charge coupled device of the present invention, since the 
potential areas are aligned with the gate electrodes, reduction of charge 
efficiency due to the formation of an unnecessary local potential barrier 
or well is prevented. 
The portions of FIG. 4 which were not described will be described with 
reference to FIGS. 5A to 5G. 
FIG. 5A illustrates the step of forming a buried channel layer 32 in a 
semiconductor substrate 30. The buried channel layer 32 is formed by 
implanting N-type ions into the overall surface of a P-type semiconductor 
substrate 30. 
Here, the buried channel layer 32 is formed as a path for the migration of 
charge. A charge coupled device having the buried channel layer 32 near 
the surface of the semiconductor substrate 30 as shown in FIG. 5A is 
referred to as a buried CCD (BCCD), whereas a charge coupled device having 
no buried channel layer is referred to as a surface CCD (SCCD). 
Though a CCD having the buried channel layer 32 is described in this 
embodiment, the effects of the present invention can be achieved without 
it. 
FIG. 5B illustrates the step of forming the first gate electrodes 36 
wherein, a gate insulation layer 34 is formed by growing, for example, 
silicon dioxide, on the overall surface of the semiconductor substrate 30 
having the buried channel layer 32 formed therein. A first conductive 
material layer (not shown) of, for example, polysilicon, which will be the 
first gate electrodes 36, is formed on the overall surface of the gate 
insulation layer 34. Then, the first gate electrodes 36 are formed to be 
spaced from each other by a predetermined distance by performing a 
photolithography on the conductive material layer. 
FIG. 5C illustrates the step of forming the first gate insulation layers 38 
wherein, the first gate insulation layers 38 are formed of silicon dioxide 
by exposing the surfaces of the first gate electrodes 36 to oxygen 
atmosphere. Here, the first insulation layers 38 entirely cover the first 
gate electrodes 36. 
FIG. 5D illustrates the step of forming the first potential areas 44 
wherein, photoresist patterns 40 are formed to expose a portion of the 
first gate electrodes 36 and areas for forming second gate electrodes by 
coating and developing a photoresist film on the overall resultant 
structure. Then, the first potential areas 44 are formed in a portion of 
an area reserved for the second gate electrodes by implanting impurity 
ions 42, using the photoresist patterns 40 as an ion implantation mask. 
Here, the photoresist patterns 40 are formed to expose the right end 
portions of the first gate electrodes 36 and the left portions of the 
areas in which the second gate electrodes will be formed. Therefore, the 
first potential areas 44 are formed so that their left end portions are 
aligned with the first gate electrodes 36, and their right end portions 
are aligned with the photoresist patterns 40. 
In addition, the impurity ions 42 are P-type ions when the buried channel 
layer 32 is N-type. 
FIG. 5E illustrates the step of forming the second gate electrodes 46 
wherein the photoresist pattern 40 of FIG. 5D is removed, and a second 
conductive material layer (not shown) of, for example, polysilicon, which 
will be the second gate electrodes 46, is formed on the overall surface of 
the resultant structure. Then, the second gate electrodes 46 are formed by 
patterning the second conductive layer, and second insulation layers 48 
are formed on the surfaces of the second gate electrodes 46. 
The second gate electrodes 46 are formed so that their left end portions 
partially overlap the right end portions of the first gate electrodes 36, 
and their right end portions are positioned near the third gate electrode 
areas. 
Here, second insulation layers 48 are formed in the same manner as that for 
the first insulation layers 38. 
FIG. 5F illustrates the step of forming the second potential areas 52 
wherein, the second potential areas 52 are formed on the semiconductor 
substrate of an area reserved for the third gate electrodes by implanting, 
for example, P-type impurity ions 50 into the overall surface of the 
semiconductor substrate 30 having the first and second gate electrodes 36 
and 46 formed therein. 
Here, the second potential areas 52 should be identical to the first 
potential areas 44 in terms of shape and size, and formed to have the same 
impurity ions at the same concentration as that of the first potential 
area 44. 
In addition, the second potential areas 52 are formed so that their right 
end portions are aligned with the left end portions of the first gate 
electrodes 36, and their left end portions are aligned with the right end 
portions of the second gate electrodes 46. 
FIG. 5G illustrates the step of forming the third gate electrodes 54 
wherein, a third conductive material layer (not shown), which will be the 
third gate electrodes 54, is formed by depositing, for example, 
polysilicon on the overall surface of the resultant structure. Then, the 
third gate electrodes 54 are formed on the semiconductor substrate of an 
area reserved for the third gate electrodes by patterning the third 
conductive material layer. A third insulation layer (not shown) is formed 
on the surface of the third gate electrodes 54, and then an insulation 
layer 60 is formed on the overall surface of the resultant structure. 
The third gate electrodes 54 are formed so that their right end portions 
partially overlap the left end portions of the first gate electrodes 36, 
and their left end portions partially overlap the right end portions of 
the second gate electrode 46. 
Here, the third insulation layer (not shown) is formed in the same manner 
as that for the first and second insulation layers 38 and 48 of FIG. 5E. 
The first and third gate electrodes 36 and 54 are connected to the first 
clock terminal .phi.1, thus forming a unit transfer group, and the second 
gate electrode 46 is connected to the second clock terminal .phi.2, thus 
forming another unit transfer group. Charge accumulated in the buried 
channel layer 32 under the gate electrodes 36, 46, and 54 is transferred 
in a predetermined direction according to clock pulses applied to the 
first and second clock terminals .phi.1 and .phi.2. 
Though a preferred embodiment using electrons as a charge carrier has been 
described with reference to FIGS. 5A to 5G (for example, the first 
conductive type and the second conductive type were defined as P and N, 
respectively), anyone skilled in the art will know that impurity ions of 
the conductive type opposite to that described should be used when holes 
are used as a charge carrier. In addition, the gate insulation layer 
formation step and the impurity-ion implantation step for forming a 
potential area may be reversed, if necessary, with the same effects. 
Therefore, according to the charge coupled device and manufacturing method 
therefor, the area occupied by a unit transfer group can be reduced and a 
potential area can be accurately aligned with a gate electrode. 
Consequently, an unnecessary local potential barrier or well produced by a 
misalignment can be prevented, thereby increasing charge transfer 
efficiency. 
The present invention is not limited to the above embodiment, and it is 
clearly understood that many variations are possible within the scope and 
spirit of the present invention by anyone skilled in the art.