SEMICONDUCTOR DEVICE

According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. A fifth semiconductor region of the first conductivity type is in contact with an outside surface of the semiconductor laminated body opposite to an inside surface of the semiconductor laminated body, the inside surface is in contact with the fourth semiconductor region.

DETAILED DESCRIPTION

According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. The semiconductor laminated body includes an inside surface and an outside surface opposed to the inside surface. The first semiconductor region includes an upper surface and a lower surface. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. The fourth semiconductor region is in contact with the inside surface of the semiconductor laminated body, and includes an upper end and a lower end. A fifth semiconductor region of the first conductivity type is in contact with the outside surface of the semiconductor laminated body. A first electrode being in contact with the third semiconductor region, the fourth semiconductor region and the second semiconductor region via a first insulating film, and including a lower end. A second electrode provided between the fourth semiconductor region and the fifth semiconductor region, and includes a side surface and a lower surface. The side surface is in contact with the semiconductor laminated body via a second insulating film. A third electrode is electrically connected to the third semiconductor region. A fourth electrode is electrically connected to the fifth semiconductor region. The lower end of the second electrode is positioned between the lower surface of the first semiconductor region and the upper surface of the first semiconductor region. The upper surface of the first semiconductor region is positioned between the lower end of the third semiconductor region and the lower end of the fourth semiconductor region.

Hereinafter, embodiments will be described with reference to the drawings. In the drawings, same reference characters denote the same or similar portions.

First Embodiment

FIG. 1is a schematic perspective view of a semiconductor device in accordance with a first embodiment.FIGS. 2A and 2Bare schematic views of the semiconductor device in accordance with the first embodiment.FIG. 2Ais a schematic plan view andFIG. 2Bis a schematic cross-sectional view.

FIG. 1represents a state in which a portion of a surface of a semiconductor device1is eliminated in order to illustrate an inside structure of the semiconductor device1.

FIG. 2Ais a plane of the semiconductor device1when a space between an upper end of a base region and a lower end of a gate electrode50is cut taken along the X-Y plane inFIG. 1.FIG. 2Billustrates a cross section taken along the A-A′ line inFIG. 2A.

The semiconductor device1in accordance with the first embodiment is the MOSFET having a three-dimensional structure. The semiconductor device1includes a semiconductor laminated body10. The semiconductor laminated body10includes an n−-type low concentration region (a first semiconductor region)11and an n−-type drift region (a second semiconductor region)12provided on the low concentration region11. The concentration of impurities (dopant) included in the drift region12is higher than a concentration of impurities included in the low concentration region11. In addition, a specific resistance of the low concentration region11is higher than a specific resistance of the drift region12.

Further, the semiconductor device1includes an n+-type source region (a third semiconductor region)20, a p-type base region (a fourth semiconductor region)30and an n+-type drain region40a. The source region20includes a side surface20wand a lower end20d, and the side surface20wand the lower end20dof the source region20are surrounded by the semiconductor laminated body10. The base region30is provided between the semiconductor laminated body10and the source region20. The source region20and the base region30are extended in a Y direction. The drain region40ais in contact with an outside surface10wbof the semiconductor laminated body10opposite to an inside surface10waof the semiconductor laminated body10which is in contact with the base region30.

FIG. 1illustrates an n+-type drain region40bprovided below the semiconductor laminated body10, in addition to the drain region40awhich is in contact with the outside surface10wbof the semiconductor laminated body10. The drain region40ais adjacent to the drain region40bto integrate drain region (a fifth semiconductor region)40. That is, the semiconductor laminated body10is surrounded by the drain region40. In addition, in the first embodiment, a laminated body, which includes the drain region40b, the low concentration region11provided on the drain region40b, and the drift region12provided on the low concentration region11, may be referred to as the semiconductor laminated body10.

Further, the semiconductor device1includes a gate electrode (a first electrode)50and a field plate electrode60(a second electrode). The gate electrode50is in contact with the source region20, the base region30and drift region12through a gate insulating film (a first insulating film)51. The gate electrode50is connected to a gate wiring52. The field plate electrode60is provided between the base region30and the drain region40a. A side surface60wof the field plate electrode60is in contact with the semiconductor laminated body10through a field plate insulating film (a second insulating film)61. The field plate electrode60is connected to a field plate wiring62.

Further, in the semiconductor device1, a source electrode (a third electrode)70is electrically connected to the source region20and the base region30. A drain electrode (a fourth electrode)71is electrically connected to the drain region40. The field plate electrode60may be connected to the source electrode70through the field plate wiring62.

Further, interlayer insulating films80,81,82are provided on the drain region40a, the drift region12, the base region30, and the source region20. The interlayer insulating film80is provided between the field plate wiring62, the drain region40aand the drift region12. The interlayer insulating film81is provided between the field plate wire62and the gate wiring52. The interlayer insulating film82covers the gate wiring52.

In addition,FIGS. 1,2A and2B illustrate a state in which a lower end60dof the field plate electrode60is positioned between a lower surface11dof the low concentration region11and an upper surface11uof the low concentration region11. In other words, the lower end60dof the field plate electrode60is positioned inside the low concentration region11. However, a state of the semiconductor device1in accordance with the first embodiment is not limited to the state described above.

For example, the lower end60dof the field plate electrode60may be positioned above the upper surface11uof the low concentration region11. In this case, the lower end60dof the field plate electrode60is positioned inside the drift region12. Further, the lower end60dof the field plate electrode60may be positioned below the lower surface11dof the low concentration region11. In this case, the lower end60dof the field plate electrode60is positioned inside the drain region40a.

Further,FIGS. 1,2A and2B show a state in which the upper surface11uof the low concentration region11is positioned between the lower end20dof the source region20and the lower end30dof the base region30. However, the state of the semiconductor device1in accordance with the first embodiment is not limited to the state described above. For example, the upper surface11uof the low concentration region11may be positioned above the lower end20dof the source region20.

Further,FIGS. 1,2A and2B show a state in which the lower end50dof the gate electrode50is positioned above the lower end60dof the field plate electrode60. Further,FIGS. 1,2A and2B illustrate a state in which the lower end50dof the gate electrode50is positioned above the lower end20dof the source region20. However, the state of the semiconductor device1in accordance with the first embodiment is not limited to the state described above. For example, the lower end50dof the gate electrode50may be positioned between the lower end20dof the source region20and the lower end30dof the base region30. In addition, the lower end50dof the gate electrode50may be positioned below the lower end30dof the base region30.

In addition, for reducing a parasitic capacitance between the gate electrode50and the source region20, it is preferable that the gate wiring52and the source region20(or the source electrode70) overlap with each other as little as possible when the semiconductor device1is seen from a Z direction. Alternatively, it is preferable that a thickness of the insulating film (interlayer insulating films80,81) provided between the gate wiring52and the source region20be as thick as possible.

A main component of the low concentration region11, the drift region12, the source region20, the base region30and the drain region40is silicon (Si), for example. A material of the gate electrode50and the field plate electrode60is a polysilicon doped with impurities or amorphous silicon doped with impurities, for example. A material of the gate insulating film51and the field plate insulating film61is oxide silicon (SiO2), for example. A material of the source electrode70and the drain region40is metal.

Among a notation of an n−-type, an n−-type, and an n+-type, the n−-type means the lowest concentration of impurities, and the n+-type means the highest concentration of impurities. The n−-type, the n−-type, and the n+-type may be referred to as a first conductivity type. Further, a p-type and a p+-type may be referred to as a second conductivity type. The p+-type means a higher concentration of impurities than that of the p-type. As an element of impurities in the first conductivity type, arsenic (As), phosphorus (P) or the like is exemplified. As an element of impurities in the second conductivity type, boron (B) is exemplified.

A manufacturing step of the semiconductor device1will be described.FIGS. 3A to 7Brepresent schematic perspective views illustrating steps of manufacturing the semiconductor device in accordance with the first embodiment.

Firstly, as illustrated inFIG. 3A, the semiconductor laminated body10, which includes the drain region40b, the low concentration region11and the drift region12, is prepared. The low concentration region11is a semiconductor crystalline layer formed in advance on the drain region40bby using epitaxial growth techniques. The drift region12is a semiconductor crystalline layer formed in advance on the low concentration region11by using epitaxial growth techniques. The semiconductor laminated body10illustrated inFIG. 3Ais a semiconductor wafer including a three-layered semiconductor region.

In the first embodiment, a process treatment is carried out on the semiconductor laminated body10in which the low concentration region11and the drift region12are provided on the drain region40bin advance.

As illustrated inFIG. 3B, a trench10tais formed in the semiconductor laminated body10. For example, after patterning of a mask90on the semiconductor laminated body10, an etching treatment is performed with respect to the semiconductor laminated body10opened by the mask90. The etching treatment is an RIE (Reactive Ion Etching), for example. In this stage, a bottom surface10bof the trench10tais adjusted so as to be positioned between the upper surface11uand the lower surface11dof the low concentration region11. The bottom surface10bis adjacent to the exposed inside surface10waof the semiconductor laminated body10.

As illustrated inFIG. 4A, the base region30and the source region20are formed in the order, on the bottom surface10band the inside surface10waof the trench10ta. The base region30and the source region20are formed by using epitaxial growth techniques. The base region30and the source region20are also formed on the mask90. In the stage, a state in which the base region30is in contact with the inside surface10waof the semiconductor laminated body10is obtained.

As illustrated inFIG. 4B, a surplus portion of each of the mask90, and the base region30and the source region20formed on the mask90is removed by a CMP (Chemical Mechanical Polishing). As a result, the upper surfaces of each of the drift region12, the base region30, and the source region20are flush with each other.

As illustrated inFIG. 5A, a trench10tbis formed in the semiconductor laminated body10. For example, after patterning of a mask91on the semiconductor laminated body10, the etching treatment is performed to the semiconductor laminated body10opened from the mask91. The etching treatment is RIE, for example. In the stage, a depth of the trench10tbis adjusted such that the drain region40bis exposed from a bottom portion of the trench10tb. In addition, the outside surface10wbof the semiconductor laminated body10is exposed by providing the trench10tb. The outside surface10wbis positioned at a position opposite to the inside surface10wadescribed above.

The drain region40ais formed inside the trench10tb. Further, a surplus portion of the mask91and the drain region40ais removed by the CMP.FIG. 5Billustrates the state.

As illustrated inFIG. 5B, in the stage, the drain region40in which the drain region40ais integrated with the drain region40bis formed. The drain region40ais formed by using epitaxial growth techniques, a CVD (Chemical Vapor Deposition) method or the like, for example. The drain region40ais in contact with the outside surface10wbof the semiconductor laminated body10.

As illustrated inFIG. 6A, the interlayer insulating film80is patterned on the drain region40a, the drift region12, the base region30, and the source region20. Further, the etching treatment is carried out in the semiconductor laminated body10opened from the interlayer insulating film80, and the trench60tis formed in the semiconductor laminated body10. Subsequently, the field plate insulating film61is formed in an inside wall of the trench60tby using a thermal oxidation method.

In the stage, the interlayer insulating film80functions as the mask in the etching treatment. The trench60tis formed between the base region30and the drain region40a. Further, the bottom surface60bof the trench60tis adjusted so as to be positioned between the lower surface11dof the low concentration region11and the upper surface11uof the low concentration region11.

As illustrated inFIG. 6B, the field plate electrode60is formed inside the trench60t. In order to accelerate crystallinity of the field plate electrode60, a heat treatment may be carried out to the field plate electrode60as necessary. Further, the field plate wiring62connected to the field plate electrode60is patterned on the interlayer insulating film80. The field plate electrode60is formed by using the CVD method or the like, for example. The field plate electrode60is formed between the base region30and the drain region40a.

As a result, a state in which the side surface60wof the field plate electrode60is in contact with the semiconductor laminated body10through the field plate insulating film61may be obtained. Further, the lower end60dof the field plate electrode60is positioned between the lower surface11dof the low concentration region11and the upper surface11uof the low concentration region11.

As illustrated inFIG. 7A, the interlayer insulating film81is patterned on the interlayer insulating film80and the field plate wiring62. Thereafter, the etching treatment is carried out in the semiconductor laminated body10opened from the interlayer insulating film80, and a trench50tis formed in the semiconductor laminated body10. Subsequently, the gate insulating film51is formed in the inside wall of the trench50tby using the thermal oxidation method.

In the stage, the interlayer insulating film81functions as the mask in the etching treatment. Further, the gate insulating film51provided inside the trench50tis in contact with the source region20, the base region30, and the drift region12, respectively. In addition, the bottom surface50bof the trench50tis adjusted so as to be positioned above the lower end20dof the source region20.

As illustrated inFIG. 7B, the gate electrode50is formed inside the trench50t. In order to accelerate the crystallinity of the gate electrode50, the heat treatment may be carried out, in the gate electrode50, as necessary. Further, a patterning of the gate wiring52connected to the gate electrode50is performed on the interlayer insulating film81. The gate electrode50is formed by using the CVD method or the like, for example. In the stage, a state in which the gate electrodes50is in contact with each of the source region20, the base region30and the drift region12through the gate insulating film51, may be obtained. In addition, the lower end50dof the gate electrode50is positioned above the lower end20dof the source region20.

Subsequently, as illustrated inFIGS. 1,2A and2B, the interlayer insulating film82, the source electrode70electrically connected to the source region20, and the drain electrode71electrically connected to the drain region40are formed.

Before an advantage of the first embodiment is described, a first reference example and a second reference example will be described.FIGS. 8A and 8Billustrate schematic perspective views of the semiconductor device in accordance with the first reference example.

The above-described low concentration region11and the field plate electrode60are not provided in a semiconductor device100naccordance with the first reference example. Further, the field plate insulating film61and the field plate wire62are not provided in the semiconductor device100. However, the drift region12described above is provided, instead of a portion in the low concentration region11of the semiconductor device1, in the semiconductor device100. The other configurations of the semiconductor device100are in the same manner as those of the semiconductor device1. The semiconductor device100is formed through the manufacturing process described below.

First, the first reference example will be described.FIGS. 9A to 10Billustrate schematic perspective views of the steps of manufacturing the semiconductor device in accordance with the first reference example.

In the first reference example, after preparing the semiconductor wafer configured by the drain region40, a patterning of a mask92on the drain region40is performed. Further, an RIE processing is carried out in the drain region40opened from the mask92.FIG. 9Aillustrates the state.

As illustrated inFIG. 9A, the drain region40in which a trench40tis provided is formed. A width of the trench40tin the X direction is wider than that of the trench10tain the X direction. In addition, a depth of the trench40tin the Z direction is deeper than that of the trench10tain the Z direction.

As illustrated inFIG. 9B, the drift region12, the base region30and the source region20are formed, in the sequence, on a bottom surface41and an inside surface40waof the trench40t. The drift region12, the base region30and the source region20are formed by using epitaxial growth techniques.

Subsequently, as illustrated inFIG. 9C, the interlayer insulating films80,81are formed on the drain region40, the drift region12, the base region30and the source region20. Further, after the etching treatment is carried out in a semiconductor layer opened from the interlayer insulating films80,81to form the trench, the gate insulating film51and the gate electrode50are formed inside the trench. In addition, the gate wiring52is patterned on the interlayer insulating film81. The semiconductor device100in accordance with the first reference example is formed through the manufacturing step.

In the first reference example, a method in which three layers of epitaxial layers (the drift region12, the base region30, and the source region20) are buried in the trench40tis adopted. Further, a thickness of the drift region12initially formed inside the trench40tis thicker than that of the other epitaxial layers (the base region30and the source region20). Accordingly, a buried state of the drift region12greatly affects a buried state of the base region30and the source region20.

For example, there are cases where, in a growth rate of the epitaxial layer, a rate in the vicinity of an opening40uof the trench40tis faster than that in the bottom surface41of the trench40t. In the case, the trench12twhich is provided in the drift region12is easy to become a so-called reverse tapered state, as illustrated inFIG. 10A. Further, when the base region30and the source region20are buried in the trench12t, as illustrated inFIG. 10B, a seam20sis generated inside the source region20in some cases.

In order not to generate the seam20s, there is a method in which the upper portion of the trench12thaving the reverse tapered state is expanded by etching treatment. For example, the drift region12in the state ofFIG. 10Ais exposed under an atmosphere of hydrogen chloride (HCI) to remove the vicinity of opening of the trench12t. However, when the method is used, the etching treatment step becomes essential and the manufacturing step is not shortened.

Next, the second reference example will be described. The low concentration region which has a lower concentration of impurities than the drift region12may be formed through the manufacturing step described below.

FIGS. 11A to 11Care schematic perspective views illustrating steps of manufacturing a semiconductor device in accordance with the second reference example.

For example, in the same manner as in the first reference example, after the drain region40in which the trench40tis provided is prepared, the drift region12is formed on the bottom surface41and the inside surface40waof the trench40t.FIG. 11Aillustrates the state. The drift region12in which the trench12tis provided is formed without completely burying the drift region12into the trench40t. The drift region12is formed by using epitaxial growth techniques.

As illustrated inFIG. 11B, a p-type impurity (boron, for example) are implanted into the bottom surface12bof the trench12tand the inside surface12waof the drift region12adjacent to the bottom surface12b. The p-type impurity is injected, so that the n-type impurity included in the drift region12cancels out by the p-type impurity (counter-ion implantation method), thereby forming an n−-type low concentration region110having a lower concentration than the drift region12. The low concentration region110covers the bottom surface12bof the trench12tand the inside surface12waadjacent to the bottom surface12b.

As illustrated inFIG. 11C, the base region30and the source region20are formed inside the trench12tin the sequence. The base region30and the source region20are formed by using epitaxial growth techniques.

In the second reference example, in order to activate the p-type impurity which is ion-implanted, after the p-type impurity is implanted, it is necessary to carry out the annealing treatment at a high temperature over a long period of time. This is because it is necessary to activate the p-type impurity which is implanted without any limit, to accelerate a counter-ion implantation. Therefore, the annealing treatment is necessary at a high temperature over a long period of time. However, when the annealing treatment is carried out, there is possibility that the n-type impurity in the n+-type drain region40is easily diffused in the base region30through the drift region12, and the desired concentration profile of impurities may not be obtained in the drift region12or the base region30.

Further, in the second reference example, since the diffusion length of impurities in the annealing treatment is importantly considered, it is not possible to design a pitch of two or more trenches equal to or below the diffusion length. For example, this is because, when the distance between the adjacent trenches12tbecomes equal to or below the diffusion length of impurities, the adjacent low concentration regions overlap each other. For this reason, in the second reference example, a limit is posed in miniaturization of a device. In addition, in an ion-implantation, the concentration of the p-type impurity inside the low concentration region110becomes non-uniform in some cases. Thereby, there is possibility that a portion of the low concentration region110may be the p-type semiconductor.

On the other hand, the semiconductor device1includes the field plate electrode60and the low concentration region11.

In the semiconductor device1, the parasitic capacitance is further reduced between the gate electrode50and the drain region40, by providing the field plate electrode60. Therefore, a fast switching is possible in the semiconductor device1. Further, depletion of the drift region12is accelerated during switching off, by providing the field plate electrode60. Accordingly, compared with a case where the field plate electrode60is not provided, the concentration of impurities of the drift region12may be set to be high. As a result, compared with the semiconductor device100, on-resistance of the semiconductor device1is decreased.

Further, in the semiconductor device1, the low concentration region11which has a lower concentration of impurities than the drift region12is provided in the lower side of the drift region12(seeFIGS. 1,2A and2B). In addition, the low concentration region11covers the lower end30dof the base region30and a portion of the side surface30wof the base region30adjacent to the lower end30d.

As a result, compared with the semiconductor device100, a depletion layer is easily expanded from the lower end30dof the base region30in the semiconductor device1. As a result, electric field strength in the vicinity of the lower end of the base region30is alleviated compared with the semiconductor device100. Accordingly, withstand voltage of the semiconductor device1is higher than withstand voltage of the semiconductor device100.

Further, the low concentration region11covers the lower end30dof the base region30and a part of the side surface30wof the base region30adjacent to the lower end30d, and is provided in all the lower side of the drift region12. The low concentration region11is a part of the semiconductor wafer, and the thickness of the low concentration region11in the Z direction is uniform. In addition, in the first embodiment, since the annealing treatment at the high temperature over the long period of time after ion-implanted is not necessary, the concentration of impurities of the low concentration region11is even compared with the low concentration region110. Therefore, compared with the low concentration region110in accordance with the second reference, the distance of the depletion layer expanded from the base region30becomes longer in the low concentration region11in accordance with the first embodiment. As a result, withstand voltage of the semiconductor device is further improved.

Further, in the first embodiment, the semiconductor wafer including the three-layered semiconductor region is used and the trench is formed in the semiconductor wafer to epitaxially grow the base region30and the source region20inside the trench. That is to say, in the first embodiment, it is not necessary to form the drift region12as in the first reference example. As a result, in the first embodiment, the seam20sis hard to generate inside the source region20. In addition, the manufacturing step is simplified as long as the drift region12is not epitaxially grown inside the trench.

Further, in the first embodiment, it is not necessary to form the low concentration region by ion-implanting as in the second reference example. In addition, the annealing treatment after the ion-implantation is also not necessary. Accordingly, the manufacturing step is simplified in the first embodiment, and the low concentration region11which has the desired concentration profile of impurities, the drift region12, and the base region30may be formed.

Further, in the first embodiment, without considering the diffusion length of impurities during annealing treatment, the device may be further designed minutely compared with the second reference example. In addition, a portion of the low concentration region11is not modified into a p-type semiconductor.

Further, in the first embodiment, a state in which the upper surface11uof the low concentration region11is positioned between the lower end20dof the source region20and the lower end30dof the base region30(referred to asFIGS. 1,2A and2B), and a state in which the upper surface11uof the low concentration region11is positioned above the lower end20dof the source region20are included. For further reducing the on-resistance, the former state in which a volume of the drift region12may be designed to be larger is more preferable. For further increasing withstand voltage of the semiconductor device, the latter state in which electric field strength in the vicinity of the lower end of the base region30is further alleviated is more preferable. Depending on a proper use of the semiconductor device, the depth of the trench10tais sufficiently adjusted in the manufacturing step.

Further, in the first embodiment, the state in which the lower end60dof the field plate electrode60is positioned above the upper surface11uof the low concentration region11is more preferable than the state in which the lower end60dof the field plate electrode60is positioned below the lower surface11dof the low concentration region11. In addition, the state in which the lower end60dof the field plate electrode60is positioned between the lower surface11dof the low concentration region11and the upper surface11uof the low concentration region11is more preferable than the state in which the lower end60dof the field plate electrode60is positioned above the upper surface11uof the low concentration region11.

In the state in which the lower end60dof the field plate electrode60is positioned below the lower surface11dof the low concentration region11, the lower end60dof the field plate electrode60is positioned inside the drain region40b. Therefore, the electric field is concentrated in the lower end60dof the field plate electrode60, or the electric field is concentrated in the vicinity of the interface between the drain region40band the low concentration region11. As a result, there is possibility that a limit is posed in an improvement of withstand voltage. As described above, the state in which the lower end60dof the field plate electrode60is positioned above the upper surface11uof the low concentration region11is more preferable than the state in which the lower end60dof the field plate electrode60is positioned below the lower surface11dof the low concentration region11.

Further, in a case where the state in which the lower end60dof the field plate electrode60is positioned between the lower surface11dof the low concentration region11and the upper surface11uof the low concentration region11is more preferable than the state in which the lower end60dof the field plate electrode60is positioned above the upper surface11uof the low concentration region11, the electric field in the vicinity of the lower end of the field plate electrode60is more alleviated. Therefore, the state in which the lower end60dof the field plate electrode60is positioned between the lower surface11dof the low concentration region11and the upper surface11uof the low concentration region11is more preferable than the state in which the lower end60dof the field plate electrode60is positioned above the upper surface11uof the low concentration region11.

Further, in the first embodiment, since the lower end50dof the gate electrode50is positioned above the lower end60dof the field plate electrode60, electric field concentration to the lower end50dof the gate electrode50is alleviated by the field plate electrode60. As a result, the reduction in withstand voltage of the field plate insulating film61is hard to occur.

Further, the state in which the lower end50dof the gate electrode50is positioned above the lower end20dof the source region20or the state in which the lower end50dof the gate electrode50is positioned below the lower end30dof the base region30is more preferable than the state in which the lower end50dof the gate electrode50is positioned between the lower end20dof the source region20and the lower end30dof the base region30. This is because that when the lower end50dof the gate electrode50is positioned between the lower end20dof the source region20and the lower end30dof the base region30, the depletion layer expanded inside the base region30is blocked by the lower end50dof the gate electrode50. When the depletion layer is blocked by the lower end50dof the gate electrode50, there is a possibility that the depletion layer is insufficiently expanded inside the base region30to cause the reduction in withstand voltage.

In accordance with the first embodiment, the semiconductor device capable of increasing withstand voltage and reducing cost is realized.

Second Embodiment

FIGS. 12A and 12Bis schematic perspective views illustrating a semiconductor device in accordance with a second embodiment.

A basic structure of a semiconductor device2in accordance with the second embodiment is the same as that of the semiconductor device1in accordance with the first embodiment. However, the base region30of the semiconductor device2includes a protrusion30awhich protrudes from the upper end of the base region30to the drain region40aside. The protrusion30ais the p+-type silicon layer. The protrusion30ais formed by using the ion-implantation, epitaxial growth techniques, or the like, for example.

A pn diode is provided between the protrusion30aand the drift region12by providing the protrusion30a. As a result, in the semiconductor device2, surge absorption is accelerated, and thus withstand voltage of the semiconductor device2is further improved.

Hereinbefore, the embodiments have been with reference to specific embodiments, but the embodiments are not limited to specific embodiments. That is to say, appropriate variation of the design added to these specific embodiments by the inventors is made within a range of the embodiment as long as characteristics of the embodiment are included. The respective elements, an arrangement of the elements, a material, a condition, a state, and a size included in the respective specific embodiments described above are not limited to those exemplified, but may be appropriately changed.

Further, the respective elements included in the respective embodiments described above may be combined as long as it is technically changeable. The combination of these elements is made within a range of the embodiment as long as characteristics of the embodiment are included. Apart from that, it is understood that, within a range of the gist of the embodiment, those skilled in the art may conceive modifications and variations, and the modifications and variations of the embodiment may be made within a range of the embodiment.