Semiconductor memory device

A semiconductor memory device is provided in which erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports. The first write driver applies voltage corresponding to the first write data to the first bit line, when activated. The first write assist driver applies voltage corresponding to the first write data to the second bit line, when activated. A row of the memory cell array for the first access through the first port is specified by the first row address, and a row of the memory cell array for the second access through the second port is specified by the second row address. The first write assist driver is activated at least on condition that the first write driver is activated and that the first row address and the second row address coincide.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-132109 filed on Jun. 9, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor memory device, especially to a semiconductor memory device which comprises a dual port memory cell.

In a semiconductor memory device which comprises a dual port memory cell, when a read or a write is performed from one port of a certain memory cell and subsequently a write is performed from the other port of the memory cell at the same address or in the same row of the layout, the subsequent write is affected by the previous read or the previous write; accordingly, the subsequent write may result in error.

Patent Document 1 (Japanese Patent Laid-open No. Hei 5 (1993)-109279) discloses the following technology to cope with such a problem. That is, Patent Document 1 discloses the technology in which, when plural word lines belonging to the same row are selected from plural ports for a read or a write, a short circuit is employed to short substantially a bit line corresponding to a port selected for the write among bit lines corresponding to the plural selected ports and another arbitrary selected bit line. Patent Document 1 describes that, by adopting such a configuration, the problem of an erroneous writing to a cell at the time of selecting the same row from plural ports is solved.(Patent Document 1) Japanese Patent Laid-open No. Hei 5 (1993)-109279

SUMMARY

However, in the device disclosed by Patent Document 1, bit line capacity seen from a write driver will differ when accessing the same row and when accessing a different row. Since both ports operate asynchronously, bit line capacity seen from the write driver changes depending on skew conditions of a clock. In order to keep pace with such changes of bit line capacity, it is difficult to avoid the complicated circuit design.

Since a bit line of the other side is driven through another stage of a transistor when seen from the write driver, low voltage characteristics get worse.

An address comparison circuit of the device concerned is used by a clock-asynchronous dual-port SRAM (Static Random Access Memory) and cannot be applied directly to a clock-synchronous dual-port SRAM which is a mainstream currently.

The present invention has been made in view of the above circumstances and provides a semiconductor memory device which can prevent an erroneous writing, without short-circuiting two bit lines coupled to two ports of a dual port memory cell.

A semiconductor memory device according to one embodiment of the present invention comprises: a memory cell array with plural memory cells arranged in a matrix and each having a first port and a second port; a first bit line coupled to the first port; a second bit line coupled to the second port; a first write driver which is able to apply voltage corresponding to a first write data to the first bit line when activated; and a first write assist driver which is able to apply voltage corresponding to the first write data to the second bit line when activated. A row of the memory cell array for first access is specified by a first row address through the first port. A row of the memory cell array for second access is specified by a second row address through the second port. The first write assist driver is activated at least on condition that the first write driver is activated and that the first row address is coincident with the second row address.

According to one embodiment of the present invention, erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports.

DETAILED DESCRIPTION

Hereinafter, with reference to the accompanying drawings, the embodiment of the present invention is explained.

(Configuration of a Semiconductor Memory Device)

FIG. 1illustrates a configuration of a semiconductor memory device according to an embodiment of the present invention.

As illustrated inFIG. 1, the semiconductor memory device1comprises a memory cell array4, a port-A control circuit2A, a port-A input/output circuit3A, a port-B control circuit2B, and a port-B input/output circuit3B.

In the memory cell array4, plural SRAM cells each having dual ports are arranged in a matrix.

The port-A control circuit2A and the port-A input/output circuit3A control access through the port A of an SRAM of the memory cell array4.

The port-A control circuit2A receives a row address signal XAA, a column address signal YAA, a read/write specification signal WENA, and a clock signal CLKA, from the exterior.

The row address signal XAA specifies a row in the memory cell array4as a target of the access through the port A. The column address signal YAA specifies a column in the memory cell array4as a target of the access through the port A.

The read/write specification signal WENA specifies whether access through the port A is a read or a write.

The clock signal CLKA controls timing of access through the port A.

The port-A input/output circuit3A receives write data DINA and a bit write mask signal BWNA from the exterior and outputs read data DOUTA to the exterior.

The write data DINA is written in a corresponding memory cell when access through the port A is a write.

The read data DOUTA is read from a corresponding memory cell when access through the port A is a read.

The bit write mask signal BWNA specifies existence or nonexistence of a write mask for every column in access through the port A.

The port-B control circuit2B and the port-B input/output circuit3B control access through the port B of an SRAM of the memory cell array4.

The port-B control circuit2B receives a row address signal XAB, a column address signal YAB, a read/write specification signal WENB, and a clock signal CLKB, from the exterior.

The row address signal XAB specifies a row in the memory cell array4as a target of the access through the port B. The column address signal YAB specifies a column in the memory cell array4as a target of the access through the port B.

The read/write specification signal WENB specifies whether access through the port B is a read or a write.

The clock signal CLKB controls timing of access through the port B.

The port-B input/output circuit3B receives write data DINB and a bit write mask signal BWNB from the exterior and outputs read data DOUTB to the exterior.

The write data DINB is written in a corresponding memory cell when access through the port B is a write.

The read data DOUTB is read from a corresponding memory cell when access through the port B is a read.

The bit write mask signal BWNB specifies existence or nonexistence of a write mask for every column in access through the port B.

(Configuration of a Memory Cell)

FIG. 2illustrates a configuration of an SRAM cell included in a memory cell array illustrated inFIG. 1.

The P-channel MOS transistor P1is coupled between a power node VDD and a memory node NA, and its gate is coupled to a memory node NB. The N-channel MOS transistor N5is coupled between the memory node NA and a ground node VSS, and its gate is coupled to the memory node NB. The P-channel MOS transistor P1and the N-channel MOS transistor N5configure a first CMOS inverter.

The P-channel MOS transistor P2is coupled between the power node VDD and the memory node NB, and its gate is coupled to the memory node NA. The N-channel MOS transistor N6is coupled between the memory node NB and the ground node VSS, and its gate is coupled to the memory node NA. The P-channel MOS transistor P2and the N-channel MOS transistor N6configure a second CMOS inverter.

The memory node NB which serves as an input of the first CMOS inverter and an output of the second CMOS inverter are coupled with each other. The memory node NA which serves as an input of the second CMOS inverter and an output of the first CMOS inverter are coupled with each other.

The N-channel MOS transistor N2is coupled between the memory node NA and a port A1, and its gate is coupled to a word line WLA. The port A1is coupled to a bit line /BLA.

The N-channel MOS transistor N1is coupled between the memory node NA and a port B1, and its gate is coupled to a word line WLB. The port B1is coupled to a bit line /BLB.

The N-channel MOS transistor N4is coupled between the memory node NB and a port A2, and its gate is coupled to the word line WLA. The port A2is coupled to a bit line BLA.

The N-channel MOS transistor N3is coupled between the memory node NB and a port B2, and its gate is coupled to the word line WLB. The port B2is coupled to a bit line BLB.

(The Port-A Control Circuit and the Port a Input/Output Circuit)

FIG. 3illustrates details of the port-A control circuit and the port-A input/output circuit illustrated inFIG. 1.

As illustrated inFIG. 3, the port-A control circuit2A comprises an X address latch8a, a Y address latch9a, a WEN latch11a, an internal clock generator12a, an X address coincidence detection circuit6a, a Y address coincidence detection circuit7a, a write assist control circuit23a, a write controller13a, a predecoder10a, an equalizer & sense amplifier control circuit26a, and a word line-A driver93a.

The internal clock generator12areceives a clock signal CLKA for access through the port A from the exterior, and generates an internal clock signal INCLKA which is activated for a predetermined period.

The X address latch8alatches, based on the internal clock signal INCLKA, a row address signal XAA for specifying a row address inputted from the exterior and generates an internal row address signal LXAA.

The Y address latch9alatches, based on the internal clock signal INCLKA, a column address signal YAA for specifying a column address inputted from the exterior and generates an internal column address signal LYAA.

The WEN latch11alatches, based on the internal clock signal INCLKA, a read/write specification signal WENA for specifying whether access through the port A inputted from the exterior is a read or a write to the memory cell, and generates an internal read/write specification signal LWENA. The read/write specification signal WENA and the internal read/write specification signal LWENA are set to an “H” level when a write is specified, and set to an “L” level when a read is specified.

The write controller13agenerates a write enable signal WEA indicating a logical product of the internal read/write specification signal LWENA and the internal clock signal INCLKA. When a write is specified, the write enable signal WEA is set to an “H” level during a period when the internal clock signal INCLKA is at an “H” level.

The X address coincidence detection circuit6adetects whether a row address specified by the internal row address signal LXAA coincides with a row address specified by the internal row address signal LXAB sent from the port-B control circuit2B, and outputs a detection signal XDA indicating the detection result. When the detection result indicates a coincidence, the detection signal XDA is set to an “H” level, and when the detection result indicates a non-coincidence, the detection signal XDA is set to an “L” level.

In this way, the X address coincidence detection circuit6acompares the internal row address signals LXAA and LXAB which have been latched based on the internal clock signals INCLKA and INCLKB, respectively. The internal row address signals do not change throughout the activated period (when the internal clock signal is at an “H” level). Therefore, the detection signal XDA is fixed during the period when both ports are activated (that is, the internal clock signals INCLKA and INCLKB are both at an “H” level); accordingly, even if both ports operate asynchronously, malfunction does not occur.

The Y address coincidence detection circuit7adetects whether a column address specified by the internal column address signal LYAA coincides with a column address specified by the internal column address signal LYAB sent from the port-B control circuit2B, and outputs a detection signal YDA indicating the detection result. When the detection result indicates a coincidence, the detection signal YDA is set to an “H” level, and when the detection result indicates a non-coincidence, the detection signal YDA is set to an “L” level.

In this way, the Y address coincidence detection circuit7acompares the internal column address signals LYAA and LYAB which have been latched based on the internal clock signals INCLKA and INCLKB, respectively. The internal column address signals do not change throughout the activated period (when the internal clock signal is at an “H” level). Therefore, the detection signal YDA is fixed during the period when both ports are activated (that is, the internal clock signals INCLKA and INCLKB are both at an “H” level); accordingly, even if both ports operate asynchronously, malfunction does not occur.

The predecoder10apredecodes the internal row address signal LXAA, and outputs a signal PXA indicating the predecoded result to the word line-A driver93a. The predecoder10adecodes the internal column address signal LYAA, and outputs a signal PYA indicating the column decoded result to the write driver control circuit24aand the sense amplifier15a.

In response to the signal PXA indicating the predecoded result from the predecoder10a, the word line-A driver93aactivates a word line WLA corresponding to the decoded result among plural rows in the memory cell.

The equalizer & sense amplifier control circuit26acontrols equalizing timing of the equalizer14aaccording to the internal clock signal INCLKA. The equalizer & sense amplifier control circuit26aalso controls timing of amplification of the sense amplifier15aaccording to the internal clock signal INCLKA.

The write assist control circuit23acomprises an NAND circuit51a, a first AND circuit52a, and a second AND circuit53a.

The NAND circuit51areceives the detection signal YDA from the Y address coincidence detection circuit7a, and receives the internal read/write specification signal LWENB from the port-B control circuit2B. The NAND circuit51asets a control signal S1ato an “L” level, only when the detection signal YDA is at an “H” level which indicates a coincidence of the column address and the internal read/write specification signal LWENB is at an “H” level which indicates a write, otherwise, the NAND circuit51asets the control signal S1ato an “H” level.

The first AND circuit52areceives the control signal S1aand the detection signal XDA from the X address coincidence detection circuit6a. The first AND circuit52asets a control signal S2ato an “H” level, only when the control signal S1ais at an “H” level and the detection signal XDA is at an “H” level which indicates a coincidence of the row address, otherwise, the first AND circuit52asets the control signal S2ato an “L” level.

The second AND circuit53areceives the control signal S2a, the write enable signal WEA, and the internal clock signal INCLKB from the port-B control circuit2B. The second AND circuit53asets a write assist control signal DEA to an “H” level, only when the control signal S2ais at an “H” level and the write enable signal WEA is at an “H” level and the internal clock signal INCLKB is at an “H” level, otherwise, the second AND circuit53asets the write assist control signal DEA to an “L” level.

Eventually, the write assist control circuit23aactivates the write assist control signal DEA to an “H” level, when the write enable signal WEA is at an “H” level, the internal clock signal INCLKB is at an “H” level, and the detection signal XDA is at an “H” level indicating a coincidence of the row address, and when the detection signal YDA is at an “L” level indicating a non-coincidence of the column address or the internal read/write specification signal LWENB is at an “L” level indicating a read.

The restriction to the condition that the write enable signal WEA is at an “H” level, the internal clock signal INCLKB is at an “H” level, and the detection signal XDA is at an “H” level indicating a coincidence of the row address is for avoiding a possible problem posed by erroneous writing which may occur in the case where writing is executed through the port A, when accesses are made to the same row in the port A and the port B and the access through the port B is activated.

The restriction to the condition that the detection signal YDA is at an “L” level indicating a non-coincidence of the column address or that the internal read/write specification signal LWENB is at an “L” level indicating a read is for preventing that writing is executed through both of the port A and the port B to the same memory cell (with the same column address and the same row address).

The port-A input/output circuit3A comprises, for every column, an equalizer14a, a sense amplifier15a, a write driver control circuit24a, write drivers19aand20a, a write assist driver control circuit25a, write assist drivers21aand22a, inverters56a,57a, and58a, a BWN latch17a, a DIN latch18a, and a DOUT latch16a.

The DIN latch18alatches the write data DINA in access through the port A inputted from the exterior, based on the internal clock signal INCLKA, and generates internal write data LDINA. The DIN latch18asupplies the internal write data LDINA to the write driver19a, the write assist driver21a, and the inverter56a. Accordingly, the same data is written to the bit line /BLA and the bit line /BLB; therefore, the bit line /BLA and the bit line /BLB can be set to the same potential.

The inverter56ainverts the internal write data LDINA, and supplies it to the write driver20aand the write assist driver22a. Accordingly, the same data is written to the bit line BLA and the bit line BLB; therefore, the bit line BLA and the bit line BLB can be set to the same potential.

The BWN latch17alatches the bit write mask signal BWNA specifying existence or nonexistence of a write mask for every column in access through the port A inputted from the exterior, based on the internal clock signal INCLKA, and generates an internal bit write mask signal LBWNA. The bit write mask signal BWNA and the internal bit write mask signal LBWNA are set to an “L” level when a write mask is specified.

The equalizer14asets the potential of the bit line BLA and the bit line /BLA to the same potential (VDD) at the timing specified by the equalizer & sense amplifier control circuit26a(equalizing).

The sense amplifier15aperforms differential amplification of the potential of the bit line BLA and the bit line /BLA, when located in a column corresponding to the decoded result of a column of the predecoder10a, and the sense amplifier15aoutputs the internal read data LDOUTA obtained by the differential amplification, to the DOUT latch16a.

The DOUT latch16alatches the internal read data LDOUTA in access through the port A outputted from the sense amplifier15a, based on the internal clock signal INCLKA (latching is performed during the internal clock signal INCLKA is at an “L” level), and the DOUT latch16aoutputs the read data DOUTA.

The write driver control circuit24areceives an internal bit write mask signal LBWNA, a write enable signal WEA, and a signal PYA indicating the column decoded result. The write driver control circuit24aactivates a write driver control signal S6aof its own column to an “H” level, when the internal bit write mask signal LBWNA is activated to an “H” level (no mask), the write enable signal WEA is activated to an “H” level, and the signal PYA indicating the column decoded result indicates its own column (namely, when its own column coincides with the column address specified by the column address signal YAA). The inverter57ainverts write driver control signal S6a.

Activating the write driver control signal S6awhen the write enable signal WEA is activated to an “H” level and when its own column coincides with the column address specified by the column address signal YAA is because it is necessary to perform a write to the bit lines BLA and /BLA of the column specified by the exterior, when the write is instructed from the exterior.

Activating the write driver control signal S6awhen the internal bit write mask signal LBWNA indicates no mask is because prohibition of a write to the bit lines BLA and /BLA of the column is instructed from the exterior.

When activated, the write driver19aapplies voltage corresponding to the internal write data LDINA to the bit line /BLA. Specifically, the write driver19acomprises an N-channel MOS transistor60a, a P-channel MOS transistor61a, and an inverter59a. When the write driver control signal S6ais activated to an “H” level, the N-channel MOS transistor60aand the P-channel MOS transistor61aare set to ON, and the write driver19ais activated. In this active state, the inverter59ainverts the internal write data LDINA outputted from the DIN latch18a. The inverted internal write data LDINA is outputted to the bit line /BLA via the N-channel MOS transistor60aand the P-channel MOS transistor61a.

When activated, the write driver20aapplies voltage corresponding to the inverted data of the internal write data LDINA to the bit line BLA. Specifically, the write driver20acomprises an N-channel MOS transistor70a, a P-channel MOS transistor69a, and an inverter68a. When the write driver control signal S6ais activated to an “H” level, the N-channel MOS transistor70aand the P-channel MOS transistor69aare set to ON, and the write driver20ais activated. In this active state, the inverter68ainverts further the inverted data of the internal write data LDINA outputted from the inverter56a. Data after inverting twice the internal write data LDINA is outputted to the bit line BLA via the N-channel MOS transistor70aand the P-channel MOS transistor69a.

The write assist driver control circuit25aactivates the write assist driver control signal SA of its own column to an “L” level, when the write assist control signal DEA and the write driver control signal S6aof its own column are both activated to an “H” level. The inverter58ainverts the write assist driver control signal SA, and activates the inverted write assist driver control signal DA to an “H” level.

In this way, when the write assist control signal DEA and the write driver control signal S6aof its own column are both activated, the write assist driver control signal SA and the inverted write assist driver control signal DA of its own column are activated. The present scheme is adopted to indicate, by the activation of the write assist control signal DEA, that a write assist is necessary to one of columns of the memory cell array4, and to indicate, by the activation of the write driver control signal S6a, that a write is performed to one of the columns (that is, a write assist is necessary to the column).

When activated, the write assist driver21aapplies voltage corresponding to the internal write data LDINA to the bit line /BLB. Specifically, the write assist driver21acomprises a P-channel MOS transistor63a, an N-channel MOS transistor64a, and an inverter62a. When the write assist driver control signal SA is activated to an “L” level, the N-channel MOS transistor64aand the P-channel MOS transistor63aare set to ON, and the write assist driver21ais activated. In this active state, the inverter62ainverts the internal write data LDINA outputted from the DIN latch18a. The inverted internal write data LDINA is outputted to the bit line /BLB via the N-channel MOS transistor64aand the P-channel MOS transistor63a.

When activated, the write assist driver22aapplies voltage corresponding to the internal write data LDINA to the bit line BLB. Specifically, the write assist driver22acomprises a P-channel MOS transistor67a, an N-channel MOS transistor66a, and an inverter65a. When the write assist driver control signal SA is activated to an “L” level, the N-channel MOS transistor66aand the P-channel MOS transistor67aare set to ON, and the write assist driver22ais activated. In this active state, the inverter65ainverts further the inverted data of the internal write data LDINA outputted from the inverter56a. The data after inverting twice the internal write data LDINA is outputted to the bit line BLB via the N-channel MOS transistor66aand the P-channel MOS transistor67a.

FIG. 4illustrates details of the port-B control circuit and the port-B input/output circuit illustrated inFIG. 1.

As illustrated inFIG. 4, the port-B control circuit2B comprises an X address latch8b, a Y address latch9b, a WEN latch11b, an internal clock generator12b, an X address coincidence detection circuit6b, a Y address coincidence detection circuit7b, a write assist control circuit23b, a write controller13b, a predecoder10b, an equalizer & sense amplifier control circuit26b, and a word line-B driver93b.

The internal clock generator12bgenerates an internal clock signal INCLKB which is activated for a predetermined period, in response to the clock signal CLKB for access through the port B from the exterior.

The X address latch8blatches, based on the internal clock signal INCLKB, a row address signal XAB for specifying a row address inputted from the exterior, and generates an internal row address signal LXAB.

The Y address latch9blatches, based on the internal clock signal INCLKB, a column address signal YAB for specifying a column address inputted from the exterior, and generates an internal column address signal LYAB.

The WEN latch11blatches, based on the internal clock signal INCLKB, a read/write specification signal WENB for specifying whether access through the port B inputted from the exterior is a read or a write to the memory cell, and generates an internal read/write specification signal LWENB. The read/write specification signal WENB and the internal read/write specification signal LWENB are set to an “H” level when a write is specified, and set to an “L” level when a read is specified.

The write controller13bgenerates a write enable signal WEB indicating a logical product of the internal read/write specification signal LWENB and the internal clock signal INCLKB. When a write is specified, the write enable signal WEB is set to an “H” level during a period when the internal clock signal INCLKB is at an “H” level.

The X address coincidence detection circuit6bdetects whether a row address specified by the internal row address signal LXAB coincides with a row address specified by the internal row address signal LXAA sent from the port-A control circuit2A, and outputs a detection signal XDB indicating the detection result. When the detection result indicates a coincidence, the detection signal XDB is set to an “H” level, and when the detection result indicates a non-coincidence, the detection signal XDB is set to an “L” level.

In this way, the X address coincidence detection circuit6bcompares the internal row address signals LXAA and LXAB which have been latched based on the internal clock signals INCLKA and INCLKB, respectively. The internal row address signals do not change throughout the activated period (when the internal clock signal is at an “H” level). Therefore, the detection signal XDB is fixed during the period when both ports are activated (that is, the internal clock signals INCLKA and INCLKB are both at an “H” level); accordingly, even if both ports operate asynchronously, malfunction does not occur.

The Y address coincidence detection circuit7bdetects whether a column address specified by the internal column address signal LYAB coincides with a column address specified by the internal column address signal LYAA sent from the port-A control circuit2A, and outputs a detection signal YDB indicating the detection result. When the detection result indicates a coincidence, the detection signal YDB is set to an “H” level, and when the detection result indicates a non-coincidence, the detection signal YDB is set to an “L” level.

In this way, the Y address coincidence detection circuit7bcompares the internal column address signals LYAA and LYAB which have been latched based on the internal clock signals INCLKA and INCLKB, respectively. The internal column address signals do not change throughout the activated period (when the internal clock signal is at an “H” level). Therefore, the detection signal YDB is fixed during the period when both ports are activated (that is, the internal clock signals INCLKA and INCLKB are both at an “H” level); accordingly, even if both ports operate asynchronously, malfunction does not occur.

The predecoder10bpredecodes the internal row address signal LXAB, and outputs a signal PXB indicating the predecoded result to the word line-B driver93b. The predecoder10bdecodes the internal column address signal LYAB, and outputs a signal PYB indicating the column decoded result to the write driver control circuit24band the sense amplifier15b.

In response to the signal PXB indicating the predecoded result from the predecoder10b, the word line-B driver93bactivates a word line WLB corresponding to the decoded result among plural rows in the memory cell.

The equalizer & sense amplifier control circuit26bcontrols equalizing timing of the equalizer14baccording to the internal clock signal INCLKB. The equalizer & sense amplifier control circuit26balso controls timing of amplification of the sense amplifier15baccording to the internal clock signal INCLKB.

The write assist control circuit23bcomprises an NAND circuit51b, a first AND circuit52b, and a second AND circuit53b.

The NAND circuit51breceives the detection signal YDB from the Y address coincidence detection circuit7b, and receives the internal read/write specification signal LWENA from the port-A control circuit2A. The NAND circuit51bsets the control signal S1bto an “L” level, only when the detection signal YDB is at an “H” level which indicates a coincidence of the column address and the internal read/write specification signal LWENA is at an “H” level which indicates a write, otherwise, the NAND circuit51bsets the control signal S1bto an “H” level.

The first AND circuit52breceives the control signal S1band the detection signal XDB from the X address coincidence detection circuit6b. The first AND circuit52bsets the control signal S2bto an “H” level, only when the control signal S1bis at an “H” level and the detection signal XDB is at an “H” level which indicates a coincidence of the row address, otherwise, the first AND circuit52bsets the control signal S2bto an “L” level.

The second AND circuit53breceives a control signal S2b, a write enable signal WEB, and an internal clock signal INCLKA from the port-A control circuit2A. The second AND circuit53bsets a write assist control signal DEB to an “H” level, only when the control signal S2bis at an “H” level and the write enable signal WEB is at an “H” level and the internal clock signal INCLKA is at an “H” level, otherwise, the second AND circuit53bsets the write assist control signal DEB to an “L” level.

Eventually, the write assist control circuit23bactivates the write assist control signal DEB to an “H” level, when the write enable signal WEB is at an “H” level, the internal clock signal INCLKA is at an “H” level, and the detection signal XDB is at an “H” level indicating a coincidence of the row address, and when the detection signal YDB is at an “L” level indicating a non-coincidence of the column address or the internal read/write specification signal LWENA is at an “L” level indicating a read.

The restriction to the condition that the write enable signal WEB is at an “H” level, the internal clock signal INCLKA is at an “H” level, and the detection signal XDB is at an “H” level indicating a coincidence of the row address is for avoiding a possible problem posed by erroneous writing which may occur in the case where writing is executed through the port B, when accesses are made to the same row in the port A and the port B and the access through the port A is activated.

The restriction to the condition that the detection signal YDB is at an “L” level indicating a non-coincidence of the column address or that the internal read/write specification signal LWENA is at an “L” level indicating a read is for preventing that writing is executed through both of the port A and the port B to the same memory cell (with the same column address and the same row address).

The port-B input/output circuit3B comprises, for every column, an equalizer14b, a sense amplifier15b, a write driver control circuit24b, write drivers19band20b, a write assist driver control circuit25b, write assist drivers21band22b, inverters56b,57b, and58b, a BWN latch17b, a DIN latch18b, and a DOUT latch16b.

The DIN latch18blatches the write data DINB in access through the port B inputted from the exterior, based on the internal clock signal INCLKB, and generates internal write data LDINB. The DIN latch18bsupplies the internal write data LDINB to the write driver19b, the write assist driver21b, and the inverter56b. Accordingly, the same data is written to the bit line /BLA and the bit line /BLB; therefore, the bit line /BLA and the bit line /BLB can be set to the same potential.

The inverter56binverts the internal write data LDINB, and supplies it to the write driver20band the write assist driver22b. Accordingly, the same data is written to the bit line BLA and the bit line BLB; therefore, the bit line BLA and the bit line BLB can be set to the same potential.

The BWN latch17blatches the bit write mask signal BWNB specifying existence or nonexistence of a write mask for every column in access through the port B inputted from the exterior, based on the internal clock signal INCLKB, and generates an internal bit write mask signal LBWNB. The bit write mask signal BWNB and the internal bit write mask signal LBWNB are set to an “L” level when a write mask is specified.

The equalizer14bsets the potential of the bit line BLB and the bit line /BLB to the same potential (VDD) at the timing specified by the equalizer & sense amplifier control circuit26b(equalizing).

The sense amplifier15bperforms differential amplification of the potential of the bit line BLB and the bit line /BLB, when located in a column corresponding to the decoded result of a column of the predecoder10b, and the sense amplifier15boutputs the internal read data LDOUTB obtained by the differential amplification, to the DOUT latch16b.

The DOUT latch16blatches the internal read data LDOUTB in access through the port B outputted from the sense amplifier15b, based on the internal clock signal INCLKB (latching is performed during the internal clock signal INCLKB is at an “L” level), and the DOUT latch16boutputs the read data DOUTB.

The write driver control circuit24breceives an internal bit write mask signal LBWNB, a write enable signal WEB, and a signal PYB indicating the column decoded result. The write driver control circuit24bactivates a write driver control signal S6bof its own column to an “H” level, when the internal bit write mask signal LBWNB is activated to an “H” level (no mask), the write enable signal WEB is activated to an “H” level, and the signal PYB indicating the column decoded result indicates its own column (namely, when its own column coincides with the column address specified by the column address signal YAB). The inverter57binverts write driver control signal S6b.

Activating the write driver control signal S6bwhen the write enable signal WEB is activated to an “H” level and when its own column coincides with the column address specified by the column address signal YAB is because it is necessary to perform a write to the bit lines BLB and /BLB of the column specified by the exterior, when the write is instructed from the exterior.

Activating the write driver control signal S6bwhen the internal bit write mask signal LBWNB indicates no mask is because prohibition of a write to the bit lines BLB and /BLB of the column is instructed from the exterior.

When activated, the write driver19bapplies voltage corresponding to the internal write data LDINB to the bit line /BLB. Specifically, the write driver19bcomprises an N-channel MOS transistor60b, a P-channel MOS transistor61b, and an inverter59b. When the write driver control signal S6bis activated to an “H” level, the N-channel MOS transistor60band the P-channel MOS transistor61bare set to ON, and the write driver19bis activated. In this active state, the inverter59binverts the internal write data LDINB outputted from the DIN latch18b. The inverted internal write data LDINB is outputted to the bit line /BLB via the N-channel MOS transistor60band the P-channel MOS transistor61b.

When activated, the write driver20bapplies voltage corresponding to the inverted data of the internal write data LDINB to the bit line BLB. Specifically, the write driver20bcomprises an N-channel MOS transistor70b, a P-channel MOS transistor69b, and an inverter68b. When the write driver control signal S6bis activated to an “H” level, the N-channel MOS transistor70band the P-channel MOS transistor69bare set to ON, and the write driver20bis activated. In this active state, the inverter68binverts further the inverted data of the internal write data LDINB outputted from the inverter56b. Data after inverting twice the internal write data LDINB is outputted to the bit line BLB via the N-channel MOS transistor70band the P-channel MOS transistor69b.

The write assist driver control circuit25bactivates the write assist driver control signal SB of its own column to an “L” level, when the write assist control signal DEB and the write driver control signal S6bof its own column are both activated to an “H” level. The inverter58binverts the write assist driver control signal SB, and activates the inverted write assist driver control signal DB to an “H” level.

In this way, when the write assist control signal DEB and the write driver control signal S6bof its own column are both activated, the write assist driver control signal SB and the inverted write assist driver control signal DB of its own column are activated. The present scheme is adopted to indicate, by the activation of the write assist control signal DEB, that a write assist is necessary to one of columns of the memory cell array4, and to indicate, by the activation of the write driver control signal S6b, that a write is performed to one of the columns (that is, a write assist is necessary to the column).

When activated, the write assist driver21bapplies voltage corresponding to the internal write data LDINB to the bit line /BLA. Specifically, the write assist driver21bcomprises a P-channel MOS transistor63b, an N-channel MOS transistor64b, and an inverter62b. When the write assist driver control signal SB is activated to an “L” level, the N-channel MOS transistor64band the P-channel MOS transistor63bare set to ON, and the write assist driver21bis activated. In this active state, the inverter62binverts the internal write data LDINB outputted from the DIN latch18b. The inverted internal write data LDINB is outputted to the bit line /BLA via the N-channel MOS transistor64band the P-channel MOS transistor63b.

When activated, the write assist driver22bapplies voltage corresponding to the internal write data LDINB to the bit line BLA. Specifically, the write assist driver22bcomprises a P-channel MOS transistor67b, an N-channel MOS transistor66b, and an inverter65b. When the write assist driver control signal SB is activated to an “L” level, the N-channel MOS transistor66band the P-channel MOS transistor67bare set to ON, and the write assist driver22bis activated. In this active state, the inverter65binverts further the inverted data of the internal write data LDINB outputted from the inverter56b. The data after inverting twice the internal write data LDINB is outputted to the bit line BLA via the N-channel MOS transistor66band the P-channel MOS transistor67b.

FIG. 5is a timing chart of the semiconductor memory device according to the embodiment of the present invention.

The timing chart ofFIG. 5illustrates operation at the time of a read/write to the same memory cell (a write through the port A and a read through the port B).

The following explains, first, operation in the case of performing a read through the port B (B1and B2) and performing a write through the port A (A1and A2) after some delay. It is assumed that data “1” (the memory node NA is at an “L” level and the memory node NB is at an “H” level) is stored in a memory cell of the accessing target.

First, a row address signal XAB (address A0) is inputted into the X address latch8bof the port-B control circuit2B (as shown in (1)).

Next, the X address latch8bof the port-B control circuit2B latches the row address signal XAB (address A0), and outputs an internal row address signal LXAB (as shown in (2)).

Next, the clock signal CLKB, which is inputted into the internal clock generator12bof the port-B control circuit2B, rises to an “H” level (as shown in (3)).

Next, the internal clock generator12bof the port-B control circuit2B detects a rising edge of the clock signal CLKB, and activates the internal clock signal INCLKB to an “H” level only for a predetermined period (as shown in (4)).

Next, the predecoder10band the word line-B driver93bof the port-B control circuit2B rise to an “H” level the word line WLB coupled to the ports B1and B2in the row corresponding to the internal row address signal LXAB (address A0) (as shown in (5)). The internal clock signal INCLKB is sent also to the write assist control circuit23aof the port-A control circuit2A. Accordingly, the write assist control circuit23aof the port-A control circuit2A can monitor the fact that the word line WLB coupled to the port B has risen to an “H” level.

Next, data “1” (the memory node NA is at an “L” level and the memory node NB is at an “H” level) stored in the memory cell coupled to the word line WLB is outputted to the bit-line pairs BLB and /BLB of the port B (B1and B2). Accordingly, the bit line BLB is driven to an “H” level, and the bit line /BLB is driven to an “L” level (as shown in (6)).

Next, a row address signal XAA (address A0) is inputted into the X address latch8aof the port-A control circuit2A (as shown in (7)).

Next, the X address latch8aof the port-A control circuit2A latches the row address signal XAA (address A0), and outputs an internal row address signal LXAA (as shown in (8)).

Next, the clock signal CLKA, which is inputted into the internal clock generator12aof the port-A control circuit2A, rises to an “H” level (as shown in (9)).

Next, the internal clock generator12aof the port-A control circuit2A detects a rising edge of the clock signal CLKA, and activates the internal clock signal INCLKA to an “H” level only for a predetermined period (as shown in (10)).

Next, the predecoder10aand the word line-A driver93aof the port-A control circuit2A rise to an “H” level the word line WLA coupled to the ports A1and A2in the row corresponding to the internal row address signal LXAA (address A0) (as shown in (11)).

Next, the read/write specification signal WENA (“H” level) which specifies a write is inputted into the WEN latch11afrom the exterior. The WEN latch11alatches the read/write specification signal WENA based on the internal clock signal INCLKA, and generates an internal read/write specification signal LWENA (“H” level).

The write controller13aof the port-A control circuit2A generates a write enable signal WEA (“H” level) indicating a logical product of the internal read/write specification signal LWENA (“H” level) and the internal clock signal INCLKA (as shown in (12)).

Although not shown, the Y address latch9aof the port-A control circuit2A latches a column address signal YAA inputted at the same timing as the row address signal XAA, and outputs an internal column address signal LYAA. The predecoder10aof the port-A control circuit2A decodes the internal column address signal LYAA, and outputs a signal PYB (“H” level) indicating the column decoded result to the write driver control circuit24aof the column specified by the decoded column address.

Although not shown, a bit write mask signal BWNA (“H” level: no mask) corresponding to the column specified by the decoded column address is inputted into the BWN latch17aof the port-A input/output circuit3A. The BWN latch17alatches the bit write mask signal BWNA based on the internal clock signal INCLKA, and generates an internal bit write mask signal LBWNA (“H” level).

Next, the write driver control circuit24acorresponding to the column specified by the column address decoded by the port-A input/output circuit3A activates the write driver control signal S6ato an “H” level, upon receiving the signal PYB (“H” level), the write enable signal WEA (“H” level), and the internal bit write mask signal LBWNA (“H” level).

The DIN latch18alatches, based on the internal clock signal INCLKA, the write data DINA (“L” level) inputted from the exterior, and generates an internal write data LDINA (“L” level). The DIN latch18asupplies the internal write data LDINA to the write driver19a, the write assist driver21a, and the inverter56a. The inverter56ainverts the internal write data LDINA (“L” level), and supplies it to the write driver20aand the write assist driver22a.

Next, the write driver19acorresponding to a column specified by the decoded column address in the port-A input/output circuit3A is activated in response to the fact that the write driver control signal S6ahas been activated to an “H” level, and outputs an “H” level to the bit line /BLA by inverting the logic of the internal write data LDINA (“L” level). The write driver20acorresponding to a column specified by the decoded column address in the port-A input/output circuit3A is activated in response to the fact that the write driver control signal S6ahas been activated to an “H” level, and outputs an “L” level to the bit line BLA by further inverting the logic of the inverted data of the internal write data LDINA (“L” level) (as shown in (13)).

On the other hand, the X address coincidence detection circuit6aof the port-A control circuit2A activates the detection signal XDA to an “H” level, according to the fact that the row address indicated by the internal row address signal LXAA received from the X address latch8aand the row address indicated by the internal row address signal LXAB received from the X address latch8bin the port-B control circuit2B coincide with each other (as shown in (14)).

The Y address coincidence detection circuit7aof the port-A control circuit2A activates the detection signal YDA to an “H” level, according to the fact that the column address indicated by the internal column address signal LYAA received from the Y address latch9aand the column address indicated by the internal column address signal LYAB received from the Y address latch9bin the port-B control circuit2B coincide with each other.

The read/write specification signal WENB (“L” level) specifying a read is inputted into the WEN latch11bof the port-B control circuit2B, and the WEN latch11blatches the read/write specification signal WENB based on the internal clock signal INCLKB and generates an internal read/write specification signal LWENB (“L” level).

The write assist control circuit23aactivates the write assist control signal DEA to an “H” level, upon receiving the internal clock signal INCLKB (“H” level), the write enable signal WEA (“H” level), the detection signal XDA (“H” level), the detection signal YDA (“H” level), and the internal read/write specification signal LWENB (“L” level) (as shown in (15)).

Next, the write assist driver control circuit25acorresponding to the column specified by the decoded column address in the port-A input/output circuit3A activates the write assist driver control signal SA to an “L” level, upon receiving the write driver control signal S6a(“H” level) from the write driver control circuit24aand the write assist control signal DEA (“H” level) from the write assist control circuit23a. The inverter58A outputs an inverted write assist driver control signal DA (“H” level) obtained by inverting the write assist driver control signal SA (as shown in (16)).

Next, the write assist driver21acorresponding to a column specified by the decoded column address in the port-A input/output circuit3A is activated in response to the fact that the write assist driver control signal SA has been activated to an “H” level, and outputs an “H” level to the bit line /BLB by inverting the logic of the internal write data LDINA (“L” level).

Next, the write assist driver22acorresponding to the column specified by the decoded column address in the port-A input/output circuit3A is activated in response to the fact that the write assist driver control signal SA has been activated to an “H” level, and outputs an “L” level to the bit line BLB by further inverting the logic of the inverted data of the internal write data LDINA (“L” level) (as shown in (17)).

The operation exemplified above is a read and write operation in the completely same address (the same memory cell). However, even a read and write operation or a write and write operation in the case of the same row address but different column address, are essentially the same as described above, except that the operation of the port B changes from a read to a dummy read (the bit line is driven by the memory cell, however, the sense amplifier is not activated).

As described above, according to the embodiment of the present invention, when a write or a read is performed concurrently in the same address or the same row of the layout, interference from the port of the read side can be eliminated and an erroneous writing can be prevented, by making the bit line potential of a port of the read side the same as the bit line potential of a port of the write side. Consequently, it is possible to employ a memory cell with a small area although variation of transistors is large; accordingly it is possible to realize reduction of the chip area.

FIG. 3andFIG. 4illustrate the block diagrams in the case that the column address is expressed by one bit (that is, the degree of multiplexing is two). However, it is possible to easily realize a configuration with the degree of multiplexing greater than two, by changing the Y address coincidence detection circuit. It is also possible to easily realize a configuration with the degree of multiplexing of one. In this case, YDA and YDB will be fixed to an “H” level.

It should be understood by those skilled in the art that the embodiment disclosed in the present application is illustrative and not restrictive, with all the points of view. The scope of the present invention is illustrated not by the explanatory description given above but by the scope of the appended claims, and it is meant that various modifications, combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.