INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides a semiconductor structure including a vertical inductor. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment. The semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. As the semiconductor industry has progressed into advanced technology process nodes in pursuit of greater device density, a bottleneck in reduction of chip size without reduction of numbers of electrical elements formed on the chips has been encountered.

DETAILED DESCRIPTION

As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. In addition, the term “source/drain region” or “source/drain regions” mayrefer to a source or a drain, individually or collectively dependent upon the context.

A conventional inductor is formed over a semiconductor wafer, which includes a circuit formed therewithin. The conventional inductor is formed over an interconnect structure of the semiconductor wafer. The conventional inductor includes metal lines horizontally arranged and disposed along a surface of the semiconductor wafer. For instance, the metal lines of the conventional inductor are formed by a deposition over the surface of the semiconductor wafer and a patterning operation to define the metal lines arranged in a horizontal direction. In addition, the conventional inductor includes a polymeric material surrounding and separating the metal lines. Due to limitations of manufacturing process and dimensions and distances of different elements of an inductor for proper functioning, a size of the conventional inductor over the semiconductor wafer cannot be further reduced.

The present disclosure provides an inductor including conductive materials in a vertical arrangement so as to reduce a size of the inductor over a substrate. A semiconductor structure including the inductor and a method for manufacturing the same are also provided.FIGS.1to34are schematic cross-sectional diagrams of semiconductor structures at different stages of the method according to different embodiments or different perspectives. For a purpose of clarity and simplicity, reference numbers of elements with same or similar functions are repeated in different embodiments. However, such usage is not intended to limit the present disclosure to specific embodiments or specific elements. In addition, conditions or parameters illustrated in different embodiments can be combined or modified to form different combinations of embodiments as long as the parameters or conditions used are not in conflict.

Referring toFIG.1, a substrate11is provided, formed or received. In some embodiments, the substrate11includes a bulk semiconductor material, such as silicon. In some embodiments, the substrate11is a raw wafer. The substrate11mayinclude another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof. The substrate11may include a first surface115(e.g., a top surface) and a second surface116(e.g., a bottom surface) opposite to the first surface115.

Referring toFIG.2, a portion of the substrate11is removed, and an opening41is formed in the substrate11. The opening41may be formed on the first surface115of the substrate11. In some embodiments, the formation of the opening41includes formation of a photoresist layer over the first surface115of the substrate11followed by an etching operation. In some embodiments, the etching operation includes a dry etching operation, a wet etching operation or a combination thereof. In some embodiments, the dry etching operation includes an ion beam etching, a reactive ion etching, or a combination thereof. In some embodiments, a depth51of the opening41is in a range of 50 to 130 microns (μm).

Referring toFIG.3, a dielectric layer121is formed over the substrate11. In some embodiments, the dielectric layer121is formed by a deposition. The dielectric layer121may be conformal to the substrate11over the first surface115of the substrate11. In some embodiments, a thickness of the dielectric layer121is consistent across the substrate11. The dielectric layer121lines the opening41over the substrate11. A thickness of the dielectric layer121is not limited as long as a magnetic layer13(formed in subsequent processing) can be isolated from the substrate11. In some embodiments, the thickness of the dielectric layer121is in a range of 1 to 20 μm. The dielectric layer121can include a suitable dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), other low-k dielectric materials, high-k dielectric materials, or a combination thereof.

Referring toFIG.4, the magnetic layer13is formed over the dielectric layer121in the opening41. In some embodiments, the magnetic layer13is formed by a deposition. In some embodiments, the deposition includes a plating operation. The magnetic layer13may be conformal to the dielectric layer121over the first surface115of the substrate11. In some embodiments, a thickness of the magnetic layer13is consistent across the substrate11. The magnetic layer13mayline the opening41over the substrate11. A thickness of the magnetic layer13can be adjusted according to a designed electrical property of a device. In some embodiments, the thickness of the magnetic layer13is in a range of 1 to 10 μm. In some embodiments, the thickness of the magnetic layer13is less than the thickness of the dielectric layer121. The magnetic layer13can include a suitable magnetically conductive material. In some embodiments, the magnetically conductive material includes iron, cobalt, nickel, samarium, neodymium, stainless steel, or a combination thereof.

Referring toFIGS.5and6, the magnetic layer13is patterned. In some embodiments,FIG.6is a cross section of the intermediate structure ofFIG.5along a line A-A′ inFIG.5. In some embodiments, a portion of the magnetic layer13outside the opening41or above the first surface115of the substrate is removed. In some embodiments, the magnetic layer13extends along the dielectric layer121above the opening41by a distance greater than zero to ensure vertical portions121aof the dielectric layer121on sidewalls of the opening41are covered by the magnetic layer13as shown in the cross section ofFIG.5. A portion of the magnetic layer13in the opening41may be also removed. In some embodiments, the magnetic layer13lines only a portion of the opening41as shown in the cross section inFIG.6. In some embodiments, the magnetic layer13lines a central portion of the opening41. In some embodiments, the magnetic layer13exposes portions of the dielectric layer121lining the opening41as shown inFIG.6.

Referring toFIG.7, a dielectric layer122is formed over the substrate11. The dielectric layer122covers the magnetic layer13and the dielectric layer121. In some embodiments, the dielectric layer122is formed by a deposition. The dielectric layer122may be conformal to a profile of the magnetic layer13and the dielectric layer121. In some embodiments, the dielectric layer122covers an entirety of the magnetic layer13. In some embodiments, a thickness of the dielectric layer122is consistent across the substrate11. The dielectric layer122lines the magnetic layer13in the opening41. A thickness of the dielectric layer122can be adjusted according to a designed electrical property of a device. In some embodiments, the thickness of the dielectric layer122is less than 10 μm. The dielectric layer122can include a suitable dielectric material, such as one of the dielectric materials listed for the dielectric layer122. In some embodiments, the dielectric layers121and122include a same dielectric material.

Referring toFIGS.8and9, a conductive layer14is formed over the substrate11in the opening41, whereinFIG.9is a cross section of the intermediate structure ofFIG.8along the line A-A′ inFIG.8. In some embodiments, the conductive layer14is formed by a deposition. In some embodiments, the deposition includes a plating operation. A planarization can be performed after the deposition, and a top surface of the conductive layer14can be substantially aligned or coplanar with a top surface of the dielectric layer122. In some embodiments, the planarization includes an etching operation. The etching operation can include a dry etch (such as ion beam etch, plasma etch and reactive ion etch), a wet etch, or a combination thereof. In some embodiments, the planarization includes a polishing operation (e.g., a chemical-mechanical polishing operation, or CMP) followed by the etching operation. The planarization may stop on an exposure of the dielectric layer122.

In some embodiments, a depth521of the conductive layer14shown inFIG.8is in a range of 20 to 80 μm. In some embodiments, a width522of the conductive layer14shown inFIG.8is in a range of 10 to 40 μm. In some embodiments, a length523of the conductive layer14shown inFIG.9is in a range of 100 to 2000 μm. It should be noted that the depth521, the width522, and the length523can be adjusted according to the opening41depending on different applications. In addition, depths of the conductive layer14in a peripheral region and in a central region may have a difference524due to the magnetic layer13. However, the difference524can be small and is omitted in the following description for a purpose of ease of illustration. In some embodiments, the top surface of the conductive layer14is exposed, and the rest of the conductive layer14is entirely surrounded by the dielectric layer122. In some embodiments, the conductive layer14is partially surrounded by the magnetic layer13.

Referring toFIG.10, a dielectric layer123is formed over the dielectric layer122and the conductive layer14. The dielectric layer123may include a dielectric material same as or different from those of the dielectric layers122or121. In some embodiments, the dielectric layer123is formed by a deposition. A planarization can be performed after the deposition, and a bonding surface165is thereby formed. In some embodiments, the bonding surface165is a planar surface. In some embodiments, the planarization includes an etching operation. The etching operation can include a dry etch (such as ion beam etch, plasma etch or reactive ion etch), a wet etch, or a combination thereof. In some embodiments, the planarization includes a polishing operation (e.g., a chemical-mechanical polishing (CMP) operation) followed by the etching operation. The planarization may include a time-mode CMP operation and/or a time-mode etching operation, and a thickness of the dielectric layer123over the conductive layer14can be controlled by a duration of the CMP operation or the etching operation. A thickness53of the dielectric layer123over the conductive layer14may be adjusted according to a designed electrical property of a device, and is not limited herein. In some embodiments, the thickness53is greater than 0.5 μm.

Referring toFIG.11, a dielectric layer16is formed over the dielectric layer123, and a structure101is thereby formed. The dielectric layer16may be for a purpose of a bonding operation performed in subsequent processing. In some embodiments, the dielectric layer16is formed over the dielectric layer123when the dielectric layer123is not suitable for a bonding operation. In some embodiments, the dielectric layer16is referred to as a bonding layer16. In some embodiments, a top surface of the dielectric layer16is a planar surface and defines a bonding surface165. In some embodiments, the dielectric layer16includes oxide. In some embodiments, the dielectric layer16mayinclude a dielectric material different from that of the dielectric layer123. In some embodiments, the dielectric layer16is formed by a deposition. In some embodiments, a thickness of the dielectric layer16is in a range of 0.1 to 2 μm.

Referring toFIG.12, the dielectric layer123of the intermediate structure shown inFIG.10is replaced by a dielectric layer16, and a structure102is thereby formed. The formation of the dielectric layer16of the structure102is similar to the formation of the dielectric layer123of the structure101, and repeated description is omitted herein. In some embodiments, when a material of the dielectric layer123is not suitable for the bonding operation, the dielectric layer16is formed and covers the dielectric layer122as shown inFIG.12. In some embodiments, a top surface of the dielectric layer16defines a bonding interface165. In some embodiments, the bonding surface165includes only the material of the dielectric layer16. In some embodiments, a thickness of the dielectric layer16over the top surface of the conductive layer14is in a range of 0.1 to 2 μm. In some embodiments, the dielectric layer16covers an entirety of the dielectric layer122as shown inFIG.12.

In other embodiments, when a material of the dielectric layer122is suitable for the bonding operation, the dielectric layer16mayexpose the dielectric layer122.

Referring toFIG.13, a planarization of the dielectric layer16maystop at an exposure of the dielectric layer122, and a structure103is thereby formed. In some embodiments, a top surface of the dielectric layer16is substantially aligned or coplanar with the top surface of the conductive layer14or a top surface of the dielectric layer122. In some embodiments, the bonding surface165includes dielectric materials of the dielectric layers122and16and a conductive material of the conductive layer14. In some embodiments, the bonding operation includes a hybrid-bonding operation.

Referring toFIG.14, a magnetic layer15is formed over the intermediate structure shown inFIG.10. A material and formation of the magnetic layer15can be similar to or same as those of the magnetic layer13, and repeated description is omitted herein. In some embodiments, a thickness of the magnetic layer15is in a range of 1 to 10 μm. The magnetic layer15is separated from the magnetic layer13by the dielectric layers122and123, and the magnetic layer15is separated from the conductive layer14by the dielectric layer123. In the embodiments with the presence of the magnetic layer15, the thickness53of the dielectric layer123over the conductive layer14is less than 10 μm.

Referring toFIGS.15and16, the magnetic layer15is patterned, whereinFIG.16is a schematic cross-sectional diagram of the intermediate structure ofFIG.15along the line A-A′ inFIG.15. The magnetic layer15is over at least a portion of the conductive layer14. In some embodiments, the magnetic layer15is over an entirety of the conductive layer14as shown in the cross section ofFIG.15. In some embodiments, a width542of the magnetic layer15is substantially equal to a width541of the magnetic layer13as shown inFIG.15. In some embodiments, edges of the magnetic layer15are substantially aligned with edges of the magnetic layer13as shown inFIG.15.

In some embodiments as shown inFIG.16, a length544of the magnetic layer15is less than the length523of the conductive layer14. In some embodiments, the magnetic layer15is over a central portion of the conductive layer14as shown in the cross section ofFIG.16. In some embodiments, the length544of the magnetic layer15is substantially equal to a length543of the magnetic layer13as shown inFIG.16. In some embodiments, edges of the magnetic layer15are substantially aligned with edges of the magnetic layer13as shown in the cross section ofFIG.16.

Referring toFIG.17, a dielectric layer16is formed over the dielectric layer123and the magnetic layer15, and a structure104is thereby formed. The dielectric layer16may be for a purpose of a bonding operation performed in subsequent processing. In some embodiments, the dielectric layer16is referred to as a bonding layer16. Formation of the dielectric layer16of the structure104can be similar to formation of the dielectric layer16as illustrated above in other embodiments, and repeated description is omitted herein. A bonding surface165of the dielectric layer16can be above (or over) or substantially aligned with a top surface of the magnetic layer15.

Referring toFIG.18, an opening42is formed in the magnetic layer15in the patterning operation as depicted inFIG.15in accordance with some embodiments of the present disclosure. In some embodiments, the magnetic layer15includes a first portion151and a second portion152separated from the first portion151by the opening42. A purpose of the opening42is to adjust a magnetic property of an inductor of a device, and a width of the opening (or a distance between the first portion151and the second portion152) can be adjusted according to different applications. In some embodiments, the opening42is over a central portion of the conductive layer14. In some embodiments, the conductive layer14is overlapped by an entirety of the opening42from a top view.

Referring toFIG.19, a dielectric layer16is formed over the intermediate structure ofFIG.18, and a structure105is thereby formed. The dielectric layer16may be for a purpose of a bonding operation performed in subsequent processing. In some embodiments, the dielectric layer16is referred to as a bonding layer16. Formation of the dielectric layer16of the structure105can be similar to that of the dielectric layer16as illustrated above, and repeated description is omitted herein. In some embodiments, the dielectric layer16covers an entirety of the first portion151and an entirety of the second portion152of the magnetic layer15. In some embodiments, the dielectric layer16fills the opening42. In some embodiments, a bonding surface165of the dielectric layer16is substantially aligned or coplanar with a top surface of the first portion151or the second portion152(not shown).

Referring toFIG.20, a planarization is performed on the intermediate structure shown inFIG.19, and a structure106is thereby formed in accordance with some embodiments of the present disclosure. In some embodiments, the planarization includes a patterning operation, and portions of the dielectric layer122above the magnetic layer13are removed. In some embodiments, the patterning operation includes an etching operation. The etching operation can include a dry etch (such as ion beam etch, plasma etch or reactive ion etch), a wet etch, or a combination thereof. In some embodiments, the planarization includes a polishing operation (e.g., a chemical-mechanical polishing operation, or CMP) and is optionally followed by an etching operation. The planarization may stop on an exposure of the dielectric layer122. In some embodiments, the dielectric layer122includes a material suitable for a bonding operation, and the dielectric layer122can function as a bonding layer. In some embodiments, the dielectric layer122can be replaced by a dielectric layer16as illustrated above, wherein the dielectric layer16provides a bonding surface165. Another dielectric layer16(similar to the dielectric layer16inFIG.11) can be optionally formed if the dielectric layer122cannot be applied in the bonding operation.

Referring toFIG.21, the structure106is further processed in accordance with some embodiments of the present disclosure, and an etch-back operation is performed on the conductive layer14. A depth of the conductive layer14is reduced from the depth521shown inFIG.8to a depth525shown inFIG.21. In some embodiments, a difference between the depth525and the depth521is in a range of 1 to 10 μm. In some embodiments, a top surface of the conductive layer14is below a top surface of the dielectric layer16by a distance of 1 to 10 μm.

Referring toFIG.22, a dielectric layer16is formed over the conductive layer14and fills the space defined by the dielectric layer122and the conductive layer14. A structure107is thereby formed. In some embodiments, a thickness of the dielectric layer16is in a range of 1 to 10 μm. In some embodiments, a top surface of the dielectric layer16is substantially aligned or coplanar with a top surface of the magnetic layer13or the top surface of the dielectric layer122.

Referring toFIG.23, the structure107is further processed in accordance with some embodiments of the present disclosure, and a magnetic layer15and a dielectric layer17are formed over the top surfaces of the magnetic layer13and the dielectric layer122. The dielectric layer17can be similar to the dielectric layer16as described above, and the operations depicted inFIGS.14to17are performed on the structure107to form a structure108as shown inFIG.23. In some embodiments, the magnetic layer15contacts the magnetic layer13. In some embodiments, sidewalls of the magnetic layer15are aligned with sidewalls of the magnetic layer13. The magnetic layer15is separated from the conductive layer14by the dielectric layer16, and therefore a distance between the magnetic layer15and the conductive layer14is substantially equal to the thickness of the dielectric layer16. In these embodiments, the dielectric layer16can be replaced by a dielectric layer123since the dielectric layer16does not function as a bonding layer.

Referring toFIG.24, the dielectric layer17is etched and the magnetic layer15is exposed. A structure109is thereby formed. In some embodiments, a top surface of the dielectric layer17is substantially aligned with the top surface of the magnetic layer15. In some embodiments, a bonding surface165includes dielectric materials of the dielectric layers16and17and a magnetic material of the magnetic layer15.

Referring toFIG.25, two structures similar to the structures101to109are faced toward one another. In some embodiments as shown inFIG.25, a structure101is flipped over and disposed over another structure101, and bonding surfaces165of the two structures101are faced toward each other. In some embodiments, an upper structure101is moved toward a lower structure101.

Referring toFIG.26, a bonding operation is performed, and the upper and lower structures101are bonded to form an inductor structure201. It should be noted that any two structures similar to the structures101to109can be bonded to form an inductor structure as long as conductive layers are separated from each other and from magnetic layers so as to ensure proper functioning of the inductor structure. A distance between the conductive layers14of the lower and upper structures101can be adjusted to achieve a desired electrical property (e.g., an inductance or a coupling factor) of the inductor structure201. A bonding interface166is defined by the two structures101. In some embodiments, the distance between the conductive layers14is in a range of 1 to 10 μm.

In following paragraphs, different embodiments of inductor structures are provided for a purpose of illustration. However, the present disclosure is not limited thereto. For a purpose of clarity, reference numbers of elements with same or similar functions are repeated in different embodiments. However, such usage is not intended to limit the present disclosure to specific embodiments or specific elements. In addition, for a purpose of simplicity, only differences between the embodiments are illustrated in the following description, and similar or same functions, properties, positions and formations of elements are omitted.

Referring toFIG.27, a structure103is bonded to a structure101, and an inductor structure202is thereby formed. In some embodiments, a distance between conductive layers14of the inductor structure202is less than the distance between the conductive layers14of the inductor structure201. In some embodiments, an inductance of the inductor structure202substantially greater than the inductance of the inductor structure201. In some embodiments, a coupling factor of the inductor structure202is substantially greater than the coupling factor of the inductor structure201.

Referring toFIG.28, a structure104is bonded to a structure101, and an inductor structure203is thereby formed. In some embodiments, a distance between conductive layers14of the inductor structure203is greater than the distance between the conductive layers14of the inductor structure202. In some embodiments, the distance between the conductive layers14of the inductor structure203is substantially equal to or greater than the distance between the conductive layers14of the inductor structure201. In some embodiments, an inductance of the inductor structure203is substantially greater than the inductance of the inductor structure201or202. In some embodiments, a coupling factor of the inductor structure203is substantially less than the coupling factor of the inductor structure201or202.

Referring toFIG.29, a structure105is bonded to a structure101, and an inductor structure204is thereby formed. In some embodiments, a distance between conductive layers14of the inductor structure204is substantially equal to the distance between the conductive layers14of the inductor structure203. In some embodiments, a thickness of a magnetic layer15of the inductor structure204is substantially equal to a thickness of a magnetic layer15of the inductor structure203. In some embodiments, an inductance of the inductor structure204is substantially less than the inductance of the inductor structure203. In some embodiments, a coupling factor of the inductor structure204is greater than the coupling factor of the inductor structure203.

Referring toFIG.30, a structure107is bonded to a structure106, and an inductor structure205is thereby formed. In some embodiments, magnetic layers13of the structures106and107are in contact at a bonding interface166of the inductor structure205. In some embodiments, a depth521of a conductive layer14of the structure106is different from a depth525of a conductive layer14of the structure107. In some embodiments, the depth525is substantially less than the depth521. In some embodiments, a distance between the conductive layers14is defined by a thickness of a dielectric layer16.

Referring toFIG.31, a structure108is bonded to a structure106, and an inductor structure206is thereby formed. A magnetic layer15of the structure108contacts a magnetic layer13of the structure108and is separated from a magnetic layer13of the structure106by a dielectric layer16at a bonding interface166. In some embodiments, the depth521of the conductive layer14of the structure106is different from a depth525of a conductive layer14of the structure108. In some embodiments, the depth525is substantially less than the depth521.

Referring toFIG.32, a structure109is bonded to a structure107, and an inductor structure207is thereby formed. In some embodiments, depths of magnetic layers13of the structures109and107are substantially identical. In some embodiments, the magnetic layer13of the structure109contacts a magnetic layer15of the structure109, and the magnetic layer15of the structure109contacts a magnetic layer13of the structure107at a bonding interface166of the inductor structure207. In some embodiments, depths (or heights) of conductive layers14of the structures107and109are substantially equal.

Referring toFIG.33, a schematic cross-sectional diagram of the inductor structure204along a line B-B′ inFIG.29is provided. The structure101may further include a conductive plug21electrically connected to the conductive layer14of the structure101, and the structure105may further include a conductive plug22electrically connected to the conductive layer14of the structure105. The conductive plugs21and22are for a purpose of providing electrical connection to the conductive layers14respectively. In some embodiments, the conductive plug21or22is formed from a second surface116of the structure101or105. In some embodiments, the conductive plug21or22is formed after formation of the dielectric layer16shown inFIG.11or19. In some embodiments, the structure101or105shown inFIG.11or19is flipped over prior to the formation of the conductive plug21or22and after the formation of the dielectric layer16shown inFIG.11or19. In some embodiments, a substrate11of the structure101or105is thinned down prior to the formation of the conductive plug21or22.

Referring toFIG.34, a schematic cross-sectional diagram of a semiconductor structure400is provided in accordance with some embodiments of the present disclosure. In some embodiments, the inductor structure204shown inFIG.33is applied in the semiconductor structure400. A semiconductor substrate301may be bonded to the inductor structure204on a side of the structure101opposite to the structure105. The semiconductor substrate301may include an interconnection structure32disposed or formed over a substrate31. In some embodiments, the substrate31includes a semiconductive material layer, a plurality of electrical components formed there over, and an insulating layer covering the electrical components thereon. The plurality of electrical components may be formed on the semiconductive material layer following conventional methods of manufacturing semiconductors. The electrical components can be active components or devices, and may include different types or generations of devices. The electrical components can include a planar transistor, a multi-gate transistor, a gate-all-around field-effect transistor (GAAFET), a fin field-effect transistor (FinFET), a vertical transistor, a nanosheet transistor, a nanowire transistor, a passive device, a capacitor, a plurality thereof, or a combination thereof. The interconnection structure32mayinclude multiple conductive vias321alternately arranged between multiple conductive lines322. The interconnection structure32mayfurther include an intermetal dielectric (IMD) structure surrounding the conductive vias321and the conductive lines322.

The structure101and the semiconductor substrate301may be bonded through a bonding region33disposed therebetween. In some embodiments, the bonding region33includes a dielectric layer331formed over the interconnection structure32of the semiconductor substrate301and a plurality of conductive patterns332surrounded by the dielectric layer331. In some embodiments, the bonding region33includes a dielectric layer333formed over the second surface116of the structure101and a plurality of conductive patterns334surrounded by the dielectric layer333. In some embodiments, a hybrid bonding operation is performed to bond the structure101to the semiconductor substrate301. The conductive layer14of the structure101can electrically connect to the electrical components in the substrate layer31of the semiconductor substrate301through the conductive plug21, the conductive patterns334and332in the bonding region33and the interconnection structure32. A bonding interface167is defined between the dielectric layers331and333. In some embodiments, the conductive patterns334are aligned with the conductive patterns332.

The semiconductor structure400may further include a passivation layer26formed over the structure105on a side opposite to the structure101. The passivation layer26can be a single-layer or a multilayer structure, and is not limited herein. The conductive layer14of the structure105may be electrically connected to another device, chip, or die through a connector23. In some embodiments, the connector23includes a via portion231connected to the conductive plug22, a pad portion (e.g., an aluminum pad)232over the via portion231, a plug portion233over the pad portion232, and a bump portion234(e.g., a solder bump) over the plug portion233. In some embodiments, the via portion231and the pad portion232are surrounded by the passivation layer26. In some embodiments, at least a portion of the plug portion233is exposed from or above the passivation layer26.

Referring toFIG.35, a schematic cross-sectional diagram of a semiconductor structure401is provided in accordance with some embodiments of the present disclosure. The semiconductor structure401can be similar to the semiconductor structure400but the structure105further includes a conductive layer141horizontally adjacent to the conductive layer14and electrically connected to the conductive layer14of the structure101.FIG.34shows an embodiment that the conductive layer14of the structure105electrically connects to a power source or another electrical component thorough the conductive plug22and the connector23at a side of the structure105opposite to the structure101(i.e., a front side of the semiconductor structure401). The conductive layer14of the structure101can electrically connect to the power source or other electrical components through the conductive plug22and the connector23by the presence of the conductive layer141.

In some embodiments, the conductive layer141is formed concurrently with the conductive layer14in the operation shown inFIGS.8and9. In some embodiments, the conductive layer141is electrically isolated from the conductive layer14of the structure105. In some embodiments, the conductive layer141is physically separated from the conductive layer14of the structure105. In some embodiments, the conductive layer141is for a purpose of electrical connection to the conductive layer14of the structure101disposed below the structure105. In some embodiments, the structure105includes a plurality of conductive vias341penetrating the dielectric layer123of the structure105and electrically connecting the conductive layer141. In some embodiments, the conductive vias341are formed prior to or after the operations depicted inFIG.18. In some embodiments, the structure101includes a plurality of conductive vias342penetrating the dielectric layer123of the structure101. In some embodiments, the conductive vias341are formed prior to or after the operations depicted inFIG.10.

The structure101and the structure105may be bonded through a bonding region34disposed therebetween, wherein the bonding region33includes the dielectric layers16of the structures101and105. In some embodiments, the bonding region34includes a plurality of conductive patterns341surrounded by the dielectric layer16of the structure105and a plurality of conductive patterns342surrounded by the dielectric layer16of the structure101. The conductive patterns341are aligned to and electrically connect to the conductive patterns342. In some embodiments, the conductive layer14of the structure101is electrically connected to the conductive layer141through the conductive vias241and242and the conductive patterns341and342. In some embodiments, a hybrid bonding operation is performed to bond the structure101and the structure105. The conductive layer14of the structure101can thereby electrically connect to other electrical components or the power source through the connector23. It should be noted thatFIG.35provides an exemplary embodiment showing how electrical connection to the conductive layer14of the structure101from the front side of the semiconductor structure401. In some embodiments, the conductive layer14electrically connects to the power source or other electrical components through another connector (not shown) from the front side of the semiconductor structure401(similar to that shown inFIG.34).

To summarize the operations as illustrated inFIGS.1to32above, a method600within a same concept of the present disclosure is provided.

FIG.36is a flow diagram of the method600for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. The method600includes a number of operations (601,602,603,604,605and606) and the description and illustration are not deemed as a limitation to the sequence of the operations. In the operation601, a first substrate is provided, wherein the first substrate includes a first recess on a first surface of the first substrate. In the operation602, a first magnetic layer is deposited in the first recess. In the operation603, a first conductive layer is deposited in the first recess, wherein the first conductive layer is surrounded by the first magnetic layer. In the operation604, a second substrate is provided, wherein the second substrate includes a second recess on a second surface of the second substrate. In the operation605, a second magnetic layer and a second conductive layer are deposited in the second recess, wherein the second conductive layer is surrounded by the second magnetic layer in the second recess. In the operation606, the first substrate and the second substrate are bonded, wherein the first surface faces the second surface. It should be noted that the operations of the method600may be rearranged or otherwise modified within the scope of the various aspects. Additional processes may be provided before, during, and after the method600, and some other processes may be only briefly described herein. Thus, other implementations are possible within the scope of the various aspects described herein.

In a conventional inductor, horizontally arranged metal lines extend along a surface of a semiconductor wafer in a horizontal direction in order to achieve a lower manufacturing cost and ease of control, and thus a size or a coverage area of the conventional inductor is limited and cannot be further reduced. The present disclosure provides an inductor structure having vertically arranged conductive materials. The vertical arrangement of the conductive materials can reduce a coverage area of the inductor structure over a semiconductor substrate (including a circuit formed therewithin). In addition, compared to the conventional inductor, the conductive material of the inductor structure of the present disclosure extends along a vertical direction instead, and the coverage area of the inductor structure is further reduced. In some embodiments, a coverage area of the inductor structure is reduced by 75% compared to a conventional inductor.

It should be noted that an annealing operation is commonly used to adjust a magnetic property of a magnetic material. For instance, an annealing operation can be performed on the structures101to109prior to the bonding operation for a purpose of magnetic phase transformation (e.g., transformation to a paramagnetic phase). In some embodiments, a temperature of the annealing operation is greater than 300 degrees Celsius (° C.). The high temperature of the annealing operation may affect an electrical property of the circuit or electrical elements of the semiconductor wafer as in the conventional inductor. The inductor structure of the present disclosure includes an upper conductive material and a lower conductive material formed individually in different wafers and then bonded together. The annealing operation can be performed on individual structures101to109prior to bonding with a semiconductor substrate (e.g.,301inFIG.34), and thus an electrical property of the circuit or electrical elements of the semiconductor substrate are not affected. A product yield can be thereby improved.

In accordance with some embodiments of the disclosure, a semiconductor structure is provided. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.

In accordance with some embodiments of the disclosure, a semiconductor structure is provided. The semiconductor structure includes a first inductor, a second inductor, and a dielectric layer. The first inductor is vertically inserted in a first semiconductor layer, wherein the first inductor includes a first conductive layer and a first magnetic layer surrounding the first conductive layer. The second inductor is disposed in a second semiconductor layer, wherein the second semiconductor layer is disposed over the first semiconductor layer, and the second inductor includes a second conductive layer and a second magnetic layer surrounding the second conductive layer, wherein the first inductor and the second inductor are vertically aligned. The dielectric layer is disposed between the first conductive layer and the second conductive layer and separates the first inductor from the second inductor.

In accordance with some embodiments of the disclosure, a method for manufacturing a semiconductor structure is provided. The method may include several operations. A first substrate is provided, wherein the first substrate includes a first recess on a first surface of the first substrate. A first magnetic layer is deposited in the first recess. A first conductive layer is deposited in the first recess and surrounded by the first magnetic layer. A second substrate is provided, wherein the second substrate includes a second recess on a second surface of the second substrate. A second magnetic layer and a second conductive layer are deposited in the second recess, wherein the second conductive layer is surrounded by the second magnetic layer in the second recess. The first substrate and the second substrate are bonded, wherein the first surface faces the second surface.