Methods of forming circuit traces and contact pads for interposers utilized in semiconductor packages

The invention encompasses methods of preparing interposers for utilization in semiconductor packages. The invention includes a method in which an interposer substrate having a surface and a conductive layer extending over the surface is provided. Pads are formed on the conductive layer by plating a conductive material on the conductive layer while using the conductive layer as an electrical connection to a power source and without utilizing conductive busses, other than the conductive layer. Subsequent to the formation of the pads, the conductive layer is patterned into circuit traces. Methodology of the present invention can be utilized for, for example, forming board-on-chip constructions.

TECHNICAL FIELD

The present invention pertains to methods of fabricating circuit traces and contact pads for interposers utilized in semiconductor packages.

BACKGROUND OF THE INVENTION

Semiconductor devices, for example, dynamic random access memory (DRAM) devices, are shrinking in the sense that smaller devices are being manufactured that are able to handle larger volumes of data at faster data transfer rates. As a result, semiconductor manufacturers are moving toward chip-scale packages (CSP) for semiconductor components which have a small size and fine pitch wiring.

Exemplary CSPs are shown inFIGS. 1 and 2as a flip-chip-in-package-board-on-chip (FCIP-BOC) package10and a board-on-chip BOC package50, respectively. Each of the packages comprises a semiconductor component12(such as, for example, an integrated circuit (IC) chip), and can thus be referred to as semiconductor packages.

The packages10and50also comprise an interposer14utilized to support the semiconductor component12. The shown interposer is a board, and such board would typically be a glass weave material. In the case of BOC construction50, chip12is attached to board14through an adhesive16. In the case of FCIP-BOC construction10, the attachment between the chip12and board14is through a series of electrical contacts18and/or36. Each of the illustrated contacts18comprises an electrically conductive interconnect material20(shown as a small ball) between a pair of contact pads22and24. The contact pad22is associated with chip12, and the contact pad24is associated with board14. Contact pad24will typically comprise a stack of a copper layer, nickel layer and gold layer; with the copper layer being adjacent board14and the gold layer being adjacent ball20of interconnect18. Contact pads22can comprise constructions analogous to those of contact pads24.

Constructions10and50are shown comprising contact pads30on an underside of the board14(i.e., on a side of board14in opposing relation relative to the side proximate chip12), and comprising electrically conductive interconnect material (shown as solder balls32) on the contact pads30. Contact pads30can comprise constructions analogous to those described above with reference to pads24, and accordingly can comprise stacks of copper, nickel and gold. Solder balls32are utilized to form electrical interconnections between contact pads30and other circuitry (not shown) external of the chip package (i.e., the package10or the package50).

The boards14have orifices34extending therethrough. Wire bonds36extend from contact pads38associated with chips12to contact pads40associated with an underside of board14. The contact pads40can be connected with pads30through circuit traces (not shown in the views of FIGS.1and2). The FCIP-BOC construction10also comprises conductive vias42extending through board14to connect selected contact pads24above the board with selected contact pads30beneath the board.

Suitable encapsulant44can be provided over the chip12, around the wire bonds36, and within orifice34as shown.

From the discussion above it can be recognized that FCIP-BOC construction10is similar to BOC construction50, with the primary differences being that FCIP-BOC construction10comprises contacts formed both above and below board14(i.e., on opposing surfaces of board14), whereas BOC construction50has contacts formed only beneath board14.

The invention described herein includes methods of forming boards and other interposers utilized in semiconductor packages. The methods can be utilized in, for example, forming either FCIP-BOC constructions or BOC constructions. Before discussing the methods of the present invention, a problem associated with prior art fabrication of boards is described with reference toFIGS. 3-9. The figures show an exemplary process for forming a board of a BOC construction, but it is to be understood that similar methodology is utilized for forming boards utilized in FCIP-BOC constructions, and accordingly problems similar to those described with reference toFIGS. 3-9also occur in forming boards associated with FCIP-BOC constructions.

Referring toFIGS. 3 and 4, a construction51is shown at a preliminary stage of a prior art process of fabricating the board for utilization in a BOC construction. The construction is shown in a cross-sectional view inFIG. 3, and in a top view in FIG.4.

Construction51includes a board14. Board14comprises a first surface15and a second surface17in opposing relation to first surface15. A conductive layer52is provided over first surface15. Conductive layer52will typically comprise, for example, copper, and can have an initial thickness of greater than 10 microns, with a typical thickness being about 12 microns. Since the shown board is to be utilized for forming a BOC construction, conductive layer52is only along one of the surfaces15and17. However, if board14were to be utilized in forming a FCIP-BOC construction, the conductive material would be formed along both of surfaces15and17.

FIGS. 5 and 6show construction51at a processing stage subsequent to that ofFIGS. 3 and 4along cross-sectional and top views, respectively. Layer52is patterned into a series of circuit traces54. It is noted that an alternative route to obtain the construction ofFIGS. 5 and 6, other than that shown inFIGS. 3-6, is to start with a construction having conductive material52over both of opposing sides15and17at the processing stage ofFIG. 3, and to etch the conductive material from over side17while forming the traces54ofFIGS. 5 and 6.

FIGS. 7 and 8show construction51at a processing stage subsequent to that ofFIGS. 5 and 6, along cross-sectional and top views, respectively. A series of conductive busses56(shown inFIG. 8) are formed across upper surface15of board14, and utilized to form electrical connections to traces54. Subsequently, a patterned mask (not shown) is formed over portions of traces54while leaving portions62exposed for formation of contact pads30. Contact pads are formed electrolytically. Specifically, busses56are connected to a power source (not shown), and subsequently conductive layers58and60are plated onto the contact pad locations of traces54to form the contact pads30. Layers58and60can comprise, consist essentially of, or consist of, for example, nickel and gold, respectively; and can be referred to as a nickel-containing layer and a gold-containing layer, respectively.

FIG. 9shows a top view of construction51in a processing stage subsequent to that of FIG.8. Specifically, orifice34has been formed to extend through board14. Orifice34can be formed utilizing, for example, a router. The forming of orifice34removes the majority of busses56from board14. However, remaining portions of busses56can problematically leave burrs70along edges of orifice34. Also, the busses can have a so-called “antenna effect” on high speed traces, which can impair high frequency electrical performance.

Other problems of prior art processes of forming conductive traces and contact pads for board substrates can include utilization of unstable plating solutions, poor wirebondability, slow plating processes, difficulty in achieving thick platings, and high cost due to, among other things, complexities of incorporating busses into design space.

In light of the above-discussed problems, it is desirable to develop new methods of forming interposers suitable for incorporation into semiconductor packages.

SUMMARY OF THE INVENTION

In one aspect, the invention encompasses a method of forming circuit traces and contact pads for an interposer utilized in a semiconductor package. An interposer substrate having a pair of opposing surfaces is provided. The opposing surfaces are defined as a first surface and a second surface, and the substrate has a first conductive material extending at least over the first surface. Pads are formed over the first conductive material by plating a second conductive material over the first conductive material while using the first conductive material as an electrical connection to a power source. After the plating, the first conductive material is patterned into electrical traces. The semiconductor package can be, for example, either a FCIP-BOC construction or a BOC construction.

In one aspect, the invention encompasses a method for forming a BOC package. An interposer substrate (in this case a board substrate), is provided. The substrate has a surface, and a first conductive layer over such surface. A first patterned mask is formed over the first conductive layer. The first patterned mask has openings extending therethrough to the first conductive layer, with the openings defining circuit trace locations. A second conductive layer is formed over and in physical contact with portions of the first conductive layer exposed through the openings. The second conductive layer is thus formed at the circuit trace locations, and is formed in a circuit trace pattern. A second patterned mask is formed to cover regions of the first conductive layer while leaving other regions exposed. The exposed regions define contact pad locations. Conductive materials are plated over the contact pad locations, and the first and second patterned masks are then removed. The circuit trace pattern is then transferred to the first conductive layer with a suitable etch.

In one aspect, the invention encompasses a method of forming a board for utilization in a FCIP-BOC package. A board substrate is provided. The substrate has a pair of opposing surfaces, with the opposing surfaces being defined as a first surface and a second surface. A first conductive layer is formed over the first surface, and a second conductive layer is formed over the second surface. A first patterned mask is formed over the first and second conductive layers. The first patterned mask has openings extending therethrough to the first and second conductive layers. The openings define contact pad locations. A third conductive layer is formed over and in physical contact with portions of the first and second conductive layers exposed through the openings. The third conductive layer is thus formed at the contact pad locations. The first patterned mask is removed. A second patterned mask is then formed over the first and second conductive layers. The second patterned mask protects regions of the first and second conductive layers while exposing other regions. The protected regions define circuit traces to at least some of the contact pad locations. Unprotected regions of the first and second conductive layers are removed to form the circuit traces from the first and second conductive layers. Subsequently, the second patterned mask is removed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention includes methods for forming interposer substrates (e.g., board substrates) suitable for utilization in semiconductor packages. The methods eliminate the bus lines traditionally used during the plating of conductive materials at contact pad locations. The elimination of the bus lines can simplify fabrication relative to prior art processes, in that it eliminates the processing steps utilized for forming the bus lines. Also, it can eliminate problems associated with residual bus lines in conventional processing, such as, for example, the burrs described with reference to prior artFIG. 9, and the antenna effect described in the “Background” section of this disclosure.

Methodologies of the present invention are suitable for forming interposers (for example, boards, lead-frames, etc.) suitable for utilization in a diverse array of semiconductor packages. Exemplary packages include FCIP-BOC constructions, BOC constructions and chip-on-board (COB) constructions. The exemplary applications which follow utilize board substrates for fabrication of exemplary BOC and FCIP-BOC constructions, but it is to be understood that the invention can be utilized for forming packages other than BOC and FCIP-BOC constructions, and that the methodology described herein can be utilized with other interposer substrates besides board substrates.

FIGS. 10-24pertain to a first embodiment of the invention, andFIGS. 26-46pertain to a second embodiment of the invention. The first embodiment is described with reference to a board suitable for utilization in a BOC construction, and the second embodiment is described with reference to a board suitable for utilization in a FCIP-BOC construction. In referring to the embodiments that follow, similar numbering will be used as was utilized in describing the prior art ofFIGS. 1-9, where appropriate.

Referring initially toFIG. 10, a board construction51is illustrated at a preliminary processing stage of a method of the present invention. Construction51ofFIG. 10is similar to the construction described previously with reference toFIG. 3, and accordingly comprises a layer52of conductive material over a surface15of a substrate14. Layer52can comprise, consist essentially of, or consist of copper. In particular aspects, layer52can predominately comprise copper, with the term “predominately comprise” indicating that the layer comprises more than 50 atomic % copper.

Layer52can be initially provided to a thickness of at least about 10 microns, with a typical thickness being about 12 microns. Layer52can be referred to as a first conductive layer in the discussion that follows to distinguish layer52from subsequent conductive layers formed thereover.

Referring toFIGS. 11 and 12, layer52is thinned. The thickness of layer52can be reduced to less than or equal to about 5 microns, and typically will be reduced to about 3 microns.FIG. 12shows that the conductive layer can extend across an entirety of a surface of substrate14(the substrate is visible in the cross-sectional view of FIG.11).

Referring toFIGS. 13 and 14, a patterned mask100is formed over conductive layer52. Patterned mask100can be formed from, for example, a dry film provided over layer52and subsequently photolithographically patterned. Openings102extend through patterned mask100to conductive layer52. The openings102define a circuit pattern.

Referring toFIGS. 15 and 16, a second conductive layer104is grown over first conductive layer52within openings102. Second conductive layer104can be formed by, for example, electrolytic processing, and accordingly can be plated over first conductive layer52. In particular aspects, second conductive layer104will comprise, predominately comprise, consist essentially of, or consist of, copper. Accordingly, second conductive layer104can be substantially identical in composition to first conductor layer52, and specifically, layers52and104can both predominately comprise, consist essentially of, or consist of copper.

Second conductive layer104can be formed to a thickness of at least about 10 microns, and in particular aspects will be formed to a thickness of at least about 12 microns. In some aspects, a combined thickness of layers52and104can be greater than about 10 microns, and in particular aspects the combined thickness can be about 12 microns. Second conductive layer104is formed in physical contact with first conductive layer52, and is formed in the circuit pattern defined by openings102.

Referring toFIGS. 17 and 18, a second patterned mask106is formed over first patterned mask100and over portions of the circuit pattern defined by first patterned mask100, while leaving some portions of the circuit pattern exposed. The covered portions are labeled108inFIG. 18, and the openings extending through second mask106are labeled110. The covered portions of the circuit pattern are shown in dashed line in the top view ofFIG. 18to indicate that such portions are under mask106, while the exposed portions are shown surrounded by a solid-line periphery. Although second mask106is shown formed over first mask100, it is to be understood that the invention includes other aspects (not shown) in which mask100is removed prior to forming mask106.

The openings110extending through mask106can be considered to define contact pad locations, and the portions of second conductive layer104exposed through openings110can be considered to correspond to the contact pad locations.

Materials58and60are formed over the portions of second conductive layer104exposed within openings110of second patterned mask106(i.e., are plated over the contact pad locations), and form contact pads30. Materials58and60can be referred to as a third conductive layer and a fourth conductive layer, respectively, in the discussion and claims that follow. Materials58and60can correspond to the same materials traditionally utilized in contact pads. Accordingly, material58can comprise, consist essentially of, or consist of nickel; and material60can comprise, consist essentially of, or consist of gold. In some applications, layer60can be omitted; and in some applications, one or both of layers58and60can predominately comprise an element selected from the group consisting of palladium, nickel and gold.

Layers58and60can be formed electrolytically over conductive material104. Specifically, materials58and60can be plated over conductive material104while providing electrical power to the conductive material104. Electrical power can be provided from a source112connected to conductive layer52. In particular aspects of the present invention, conductive layer52will be the only conductive interconnect (i.e., bus) extending across substrate14between layer104and power source112. In other words, the bus lines56described above with reference toFIGS. 8 and 9are eliminated. The plating solutions utilized during plating of materials58and60can be chosen for appropriate chemical stability.

Referring toFIGS. 19 and 20, first and second patterned masks100and106(FIGS. 17 and 18) are removed.

Referring next toFIGS. 21 and 22, layers104,58and60are utilized as a patterned mask during an etch of first conductive layer52. Such patterns first conductive layer52into electrical traces aligned with the materials of layers104,58and60thereover. In the shown aspect of the invention, the traces have the rectangular shapes visible in the top view ofFIG. 22as combinations of materials104and60, with the individual discrete traces being labeled as118in FIG.22.

Referring toFIG. 23, a patterned mask120is formed over construction51to cover portions122of traces118(the covered portions are shown in phantom, dashed-line view in FIG.23), while leaving contact pads30exposed. Mask120can be referred to as a solder mask, and is utilized to define locations where solder balls are to be provided in a ball grid array. Such locations correspond to the locations of contact pads30. As will be understood by persons of ordinary skill in the art, the openings extending to contact pads30can expose the entire area of the contact pads, or can expose only a portion of the area of the contact pads, depending on whether the pads are to be utilized in solder mask defined (SMD) applications or non-solder mask defined (NSMD) applications.

Referring toFIG. 24, orifice34is formed to extend entirely through substrate14(visible in the cross-sectional view ofFIG. 21) of construction51. Mask120preferably remains in place during formation of orifice34. Subsequent to the formation of orifice34, construction51can be incorporated into a semiconductor package, such as, for example, the package50shown in FIG.2.

An advantage of the processing ofFIGS. 10-24relative to the prior art processing ofFIGS. 2-9, is that the bus lines56(FIGS. 8 and 9) have been eliminated from the processing of the present invention. Accordingly, orifice34can be formed without formation of the burrs70described above with reference to FIG.9. Other difficulties associated with busses (such as, for example, the antenna effect of the busses) can also be eliminated.

The construction ofFIG. 24can be considered to comprise a central region within which orifice34is formed, and a peripheral region surrounding the central region. The circuit traces118can be considered to be formed in the peripheral region in the shown embodiment. A dashed line130is shown inFIG. 24as an exemplary demarcation between the central region and the peripheral region. One aspect of the invention is that layers58and60(shown for example inFIG. 22) have been plated over contact locations30by using conductive layer52(shown inFIG. 17) as an electrical connection to a power source (112inFIG. 17) and without utilizing conductive busses, other than the conductive layer52, extending over any part of the central region of the substrate.

Although the processing ofFIGS. 10-24is described with reference to formation of an individual board construction, it is to be understood that methodology of the present invention can be utilized to form multiple board constructions simultaneously.FIG. 25shows an exemplary panel150at a processing step comparable to that ofFIGS. 11 and 12. Panel150comprises a base14(not visible in the top view ofFIG. 25) and a conductive layer52over the base. A plurality of board locations51are defined across panel150, and each of the board locations51can correspond to an individual board construction of the type described inFIGS. 10-24. All of the boards associated with the panel can be simultaneously subjected to the processing ofFIGS. 10-24. During the processing ofFIG. 17, electrical power can be provided to layer52by providing an electrical contact to the layer at, for example, one or more of the edges of panel150.

Although the individual board constructions51associated with panel150are shown separated from one another in the illustration, it is to be understood that the board constructions can be packed tightly together without intervening spaces between adjacent board constructions in other applications (not shown) to increase the number of board constructions formed from an individual panel.

The next embodiment of the invention is described initially with reference toFIGS. 26-28. Such show a construction200comprising the substrate14having opposing surfaces15and17. Surfaces15and17can be referred to as first and second surfaces, respectively. A first conductive layer202is provided over first surface15, and a second conductive layer204is provided over second conductive surface17. Conductive layers202and204can comprise, consist essentially of, or consist of copper. In particular aspects, layers202and204will predominately comprise copper. Layers202and204can thus have compositions identical to the composition of the layer52described above with reference to FIG.10. Layers202and204can each have thicknesses greater than about 10 microns, and in particular aspects will have thicknesses of about 12 microns. As discussed in the brief description of the drawings,FIGS. 27 and 28correspond to a top view and a bottom view, respectively, of a construction comprising the cross-section of FIG.26.

Referring next toFIGS. 29-31, openings206are formed through substrate14together with layers202and204, and subsequently a conductive material208is formed within the openings. Openings206can be formed by, for example, drilling. Although the openings206are shown formed entirely through substrate14and layers202and204, it is to be understood that the invention encompasses other aspects (not shown) in which one or more of the openings extend only partially through one or more of substrate14and layers202and204. Conductive material208can comprise, consist essentially of, or consist of, for example, copper. The openings206can ultimately be utilized to form vias, such as, for example, the vias42described with reference to prior art FIG.1. It is to be understood that the vias are optional relative to processing of the present invention, and accordingly can be eliminated in other aspects (not shown).

Referring next toFIGS. 32-34, patterned masks210and212are formed over exposed surfaces of conductive layers202and204, respectively. Mask210has openings214,215,216and217formed therethrough; and mask212has openings218,219,220and221formed therethrough. Masks210and212can correspond to, for example, dry films patterned by photolithography. Openings218,219,220and221are extended into layer204(shown in the cross-sectional view ofFIG. 32, and specifically shown relative to openings218and220), and openings214,215,216and217are not extended into layer202. The extension of openings218,219,220and221into layer204can be accomplished with a suitable timed etch of the material of layer204.

Referring next toFIGS. 35-37, conductive materials58and60are formed within openings214,215,216,217,218,219,220and221. Conductive materials58and60can comprise the same materials described previously with reference to FIG.17. Accordingly, conductive material58can comprise, consist essentially of, or consist of nickel; and conductive material60can comprise, consist essentially of, or consist of gold. Conductive materials58and60form contact pads, and openings214,215,216,217,218,219,220and221therefore correspond to contact pad locations.

Conductive materials58and60can be formed over conductive layers202and204utilizing an electrolytic process. Specifically, a power source222is connected to layers202and204. The power source is then utilized to provide electrical power to layers202and204while conductive materials of layers58and60are electrolytically formed (i.e., plated) within openings214,215,216,217,218,219,220and221. The plating solutions utilized during plating of materials58and60can be chosen for appropriate chemical stability.

It is noted that layer58is shown inset within layer204in openings218and220, and is shown on an upper surface of layer202within openings214and216. Layer58can be inset within an underlying conductive layer if a suitable etch is performed to form an opening extending into such layer (described above with reference to FIGS.32-34). Alternatively if no such suitable etch is performed, layer58will be formed over an exposed upper surface of the conductive layer. In the shown aspect of the invention, layer204has been subjected to a suitable etch to allow layer58to be inset within layer204, and layer202has not been subjected to such etch. It is to be understood that the invention encompasses other applications (not shown) wherein both of layers202and204are subjected to the suitable etch to form the inset, as well as other applications in which neither of layers202and204is subjected to the inset-forming etch. Also, the invention encompasses applications in which layer202is subjected to the inset-forming etch and layer204is not.

Referring next toFIGS. 41-43, patterned masks250and252are formed over layers202and204, respectively, and over contact pads234,235,236,237,238,239,240and241. Masks250and252can comprise, for example, dry films patterned using photolithographic processing. Masks250and252define circuit traces. Specifically, masks250and252cover portions of underlying layers202and204which are to be incorporated into circuit traces, and leave other portions of layers202and204exposed.

Referring next toFIGS. 44-46, the exposed portions of layers202and204are removed, and subsequently patterned masks250and252(FIGS. 41-43) are removed to leave the patterned circuit traces260and262remaining over substrate14. The circuit traces extend to and between conductive pads234,235,236,237,238,239,240and241. The circuit traces also extend between the conductive pads and the vias206.

In subsequent processing, not shown, an orifice (or opening)34analogous to the orifice described previously with reference toFIG. 24can be formed across a middle section of substrate200, and the substrate can then be incorporated into a semiconductor chip package, such as, for example, the package10described with reference toFIG. 1. Acentral region for formation of the orifice is illustrated diagrammatically inFIGS. 45 and 46utilizing the dashed line290to demarcate a central region (the region within the dashed line) from a peripheral region (the region outward of the dashed line).

The various contact pads formed relative to substrate200can be utilized in NSMD constructions, and/or SMD constructions. The SMD approach can be more preferred in particular aspects of the invention.

The processing ofFIGS. 26-46has, like the above-described processing ofFIGS. 10-24, plated contact pads without utilization of prior art busses (such as, for example, the busses56described with reference to FIGS.8and9). Such can lead to various of the advantages described previously in this disclosure. Among the advantages for eliminating bus lines is that such can eliminate slot burr, and can ease design while saving space and thus allowing a smaller footprint. Additionally, the removal of bus lines from designs of the present products can allow open/short tests to be achieved with the products, and can improve electrical performance at high frequencies due to elimination of an antenna effect caused by bus lines. Wirebondability of bond pads produced in accordance with methodology of the present invention should be similar regardless of whether electrolytic plating or electroless plating is used. Methodology of the present invention can achieve good plating thickness in relatively short plating time, utilizing electrolytic processes. Etching processes of the present invention can be conducted, in particular aspects, without tail traces left on the pattern.

FIG. 47illustrates an exemplary processor system that may include semiconductor components produced using packaging methodology of the present invention, such as, for example, FCIP-BOC, BOC and/or COB packaging. Specifically, a processor system500is illustrated which can be, for example, a computer system. The processor system generally comprises a central processing unit (CPU)502, for example, a microprocessor, that communicates with one or more input/output (I/O) devices512,514, and516over a system bus522. System500also includes random access memory (RAM)518, a read-only memory (ROM)520and may also include peripheral devices such as a floppy disk drive504, a hard drive506, a display508and a compact disk (CD) ROM drive510which also communicate with the processor502over the bus522. Any or all of the elements of the processor system500, for example, processor502, RAM518, ROM520or controller or other IC chips contained within the components shown inFIG. 47may include semiconductor packages formed using methodology described with reference toFIGS. 10-46. It should be noted thatFIG. 47is representative of many different types of architectures of a processor system500which may employ the invention. It may also be desirable to integrate the CPU502and the RAM518on a single chip.