Method for passivating the sidewalls of a tungsten word line

This invention embodies a process for passivating the edges of a tungsten metal layer within a word line stack. After the word line stack is patterned (i.e., formed by masking and etching the stack of globally-deposited layers) as shown in FIG. 1, a conformal silicon film is blanket deposited. Deposition of the silicon film may be accomplished by any available technique, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. The wafer is then heated so that the tungsten in contact with the silicon film is converted to tungsten silicide. In a preferred embodiment of the invention, only a portion of the silicon film is allowed to react with the edge of the tungsten layer. The remainder of the silicon film is converted to silicon dioxide by subjecting the wafer O.sub.2 in a furnace or rapid thermal processing chamber. Alternatively, the remainder of the silicon film may be converted to silicon dioxide by subjecting the wafer to O.sub.2 or O.sub.3 in a plasma reactor. In an alternative but equivalent embodiment of the process, the tungsten metal is converted to tungsten silicide and the remainder of the silicon film is converted to silicon dioxide using a single piece of equipment. This is done by first heating the wafer in a nitrogen-containing ambiance, and then ramping the temperature upward and replacing the nitrogen-containing ambiance with an oxidizing ambiance.

This application is related to U.S. application Ser. No. 08/572,164, 
entitled "METHOD FOR DEPOSITING A TUNGSTEN LAYER ON SILICON", which was 
filed simultaneously with the present application. 
FIELD OF THE INVENTION 
This invention relates to the fabrication of integrated circuits and, more 
particularly, to the use of tungsten metal as the primary current carrier 
for a word line stack. 
BACKGROUND INFORMATION 
In the manufacture of integrated circuits, both field-effect transistor 
gate electrodes and gate electrode interconnects are typically etched from 
a uniformly-thick conductive layer that blankets the in-process circuitry. 
In semiconductor memory circuits, word lines which are formed from a 
uniformly-thick conductive layer which blankets the circuitry form both 
gate electrodes and gate interconnects. Wherever a word line passes over a 
field oxide region, it functions as a gate electrode interconnect; 
wherever it passes over a gate dielectric layer that overlies an active 
area, it functions as a gate electrode. In typical circuits, whether they 
be memory circuits, processor circuits or logic circuits, multiple gate 
electrodes are series coupled by intervening gate interconnects. In other 
words, the gate electrode/gate interconnect structures seen in memory 
circuits closely resemble those found in other types of integrated 
circuits. 
For early generations of integrated circuits, gate electrodes and 
electrodes interconnects were typically etched from a heavily-doped 
polycrystalline silicon ("polysilicon") layer. However, in order to 
achieve increased operational speeds and lower stack heights in subsequent 
generations of circuits, it became necessary to decrease the sheet 
resistance of the conductive layer from which the gates and gates and 
interconnects were formed. 
A significant improvement in the conductivity of gate electrodes and gate 
interconnects was realized by forming a low-resistance metal silicide 
layer on top of the electrode/interconnect layer. A silicide is a binary 
compound formed by the reaction of a metal and silicon at elevated 
temperature. As integrated circuit processing generally requires a series 
of elevated temperature steps, metals having high melting points are 
preferred for structures, such as gates, which are created early in the 
fabrication process. A metal layer applied at the end of the fabrication 
process need not possess a particularly high melting point. Thus, 
aluminum, which has a melting point of only 660.degree. C., is typically 
used only for upper level interconnect lines, and is applied to the 
circuitry only after no further processing of the wafer in excess of about 
600.degree. C. is required. The group of refractory metals is generally 
considered to include tungsten (melting point 3410.degree. C.), titanium 
(m.p. 1675.degree. C.), platinum (m.p. 1774.degree. C.), palladium (m.p. 
1549.degree. C.), cobalt (m.p. 1495.degree. C.), molybdenum (m.p. 
2620.degree. C.), nickel (m.p. 1455.degree. C.), rhodium 1966.degree. C.) 
and iridium (m.p. 2454.degree. C.). Because of considerations related to 
cost and ease of deposition, silicides of tungsten and titanium are the 
most widely used for integrated circuit applications. Generally, a metal 
silicide conductor within an integrated circuit is formed by one of two 
methods. The first method involves depositing (usually by reactive 
sputtering) a metal silicide layer on top of a previously deposited 
polysilicon layer and annealing the resulting stack to break up the native 
oxide layer on the surface of the polysilicon layer (which enhances 
adhesion of the silicide layer to the polysilicon layer and also ensures 
adequate electrical interconnection between the two layers). The second 
method, on the other hand, involves depositing a metal layer (by either 
reactive sputtering or by chemical vapor deposition) on top of a 
previously deposited polysilicon layer and annealing the resulting stack 
to react the metal layer with a portion of the polysilicon layer (which, 
of course, also eliminates the native oxide layer on the polysilicon). 
Although metal silicides have significantly higher conductivity than 
heavily-doped silicon, a silicide is about an order of magnitude more 
resistive than the pure metal from which it is formed. 
In the quest of faster operational speeds (required for high-speed 
processor and memory circuits) and reduced stack heights (in the interest 
of enhanced planarity and, thus, better photolithographic resolution over 
the entire circuit), integrated circuit manufacturers are investigating 
the use of pure metal layers to enhance the conductivity of polysilicon 
transistor gates and gate interconnects. Tungsten is of particular 
interest because it is relatively inexpensive, has a very high melting 
point, and is known to be compatible with current circuit manufacturing 
processes. However, the deposition of tungsten metal directly on silicon 
results in tungsten layers having extremely poor thickness uniformity. 
Such non-uniformity most likely results from the formation of tungsten 
silicide islands as silicon diffuses into the tungsten layer at the 
polysilicon/tungsten interface. The referenced patent application entitled 
"METHOD FOR DEPOSITING A TUNGSTEN LAYER ON SILICON" discloses a method for 
depositing tungsten metal on silicon which ameliorates the poor uniformity 
characteristics of a tungsten metal layer deposited directly on silicon. 
FIG. 1 depicts a word line stack 10 comprising a polysilicon layer 11, a 
conductive barrier layer 12 such as tungsten nitride or titanium nitride, 
a tungsten metal layer 13, and a silicon dioxide capping layer 14. The 
word line stack 10 overlies a silicon substrate 15 which is a small 
portion of a silicon wafer. Polysilicon layer 11 of word line stack 10 is 
insulated from the substrate 15 by a gate dielectric layer 16. The use of 
unreacted tungsten metal as a word line conductive layer creates 
additional problems during the fabrication process. The word line 
materials must be able to withstand high temperature processing in an 
oxidizing environment. For example, shortly after the word line stack 10 
of FIG. 1 is patterned, a source/drain reoxidation step is performed 
which. The source/drain reoxidation step reduces the electric field 
strength at the gate edge by upwardly chamfering the edge, thereby 
reducing the "hot electron" effect that is responsible for threshold 
voltage shifts. Unfortunately, tungsten at the exposed edges of layer 13 
is rapidly converted to tungsten trioxide gas at high temperature in the 
presence of oxygen. As tungsten trioxide undergoes sublimation as it is 
formed at high temperatures, the oxidation of a tungsten surface is not 
self limiting. Therefore, a primary objective of the present invention is 
the development of a process which passivates the edges of the tungsten 
metal layer within such a word line stack. 
SUMMARY OF THE INVENTION 
This invention embodies a process for passivating the edges of a tungsten 
metal layer within a word line stack. After the word line stack is 
patterned (i.e., formed by masking and etching the stack of 
globally-deposited layers) as shown in FIG. 1, a conformal silicon film is 
blanket deposited. Deposition of the silicon film may be accomplished by 
any available technique, such as chemical vapor deposition or 
plasma-enhanced chemical vapor deposition. The wafer is then heated so 
that the tungsten in contact with the silicon film is converted to 
tungsten silicide. In a preferred embodiment of the invention, only a 
portion of the silicon film is allowed to react with the edge of the 
tungsten layer. The remainder of the silicon film is converted to silicon 
dioxide by subjecting the wafer to O.sub.2, H.sub.2 O vapor, or a wet 
forming gas (10% H.sub.2 in N.sub.2 with a trace of H.sub.2 O vapor) in a 
furnace or in a rapid thermal processing chamber. Alternatively, the 
remainder of the silicon film may be converted to silicon dioxide by 
subjecting the wafer to O.sub.2 or O.sub.3 in a plasma reactor. In an 
alternative but equivalent embodiment of the process, the tungsten metal 
is converted to tungsten silicide and the remainder of the silicon film is 
converted to silicon dioxide using a single piece of equipment. This is 
done by first heating the wafer in a nitrogen-containing ambiance, and 
then ramping the temperature upward and replacing the nitrogen-containing 
ambiance with an oxidizing ambiance.

PREFERRED EMBODIMENT OF THE INVENTION 
FIG. 1 has been heretofore described as a word line stack 10 fabricated on 
a silicon substrate 15 and having an unpassivated tungsten metal layer 13. 
The structure of FIG. 1 is the starting point for various embodiments of a 
process for passivating the exposed edges of the tungsten metal layer 13 
so that the word line stack may be further processed in an oxidizing 
ambiance without undergoing the conversion of the tungsten metal layer 13 
to the non-conductive compound, tungsten oxide. The various embodiments of 
the process proceed stepwise through FIG. 5. 
Referring now to FIG. 2, a conformal polycrystalline silicon or amorphous 
silicon film 21 having a thickness of about 50 .ANG. is blanket deposited, 
covering the upper surface and sidewalls of the word line stack and the 
substrate 15 as well. Deposition of the silicon film 21 may be 
accomplished by any available technique, such as chemical vapor deposition 
or plasma-enhanced chemical vapor deposition. 
Referring now to FIG. 3, the wafer is heated so that the tungsten at both 
edges of tungsten layer 13 that is in contact with the silicon film 21 is 
converted to tungsten silicide by subjecting the wafer to elevated 
temperature in the presence of a gas which does not react with silicon at 
the silicidation reaction temperature. Gases such as diatomic nitrogen, 
helium and argon are examples. In a preferred embodiment of the invention, 
the silicidation reaction is terminated before the entire thickness of the 
silicon film 21 that is adjacent each edge of tungsten layer 13 is 
consumed. In any case, tungsten silicide strips 31 are formed along each 
of the two formerly exposed edges of the tungsten layer 13. 
Referring now to FIG. 4, the remainder of the silicon film 21, both those 
portions which are immediately adjacent the newly formed tungsten silicide 
strips 21 as well as those portions which coat the remainder of the word 
line stack and the substrate 15 are converted to a silicon dioxide layer 
41 by subjecting the wafer to elevated temperature in an oxidizing 
ambiance. This step may be performed in a furnace or rapid thermal 
processing chamber in the presence of diatomic oxygen or ozone. 
Alternatively, the step may be performed by heating the wafer in a plasma 
reactor in the presence of plasma generated from diatomic oxygen or ozone 
gases. In an alternative equivalent embodiment of the process, the 
tungsten silicide strips 31 and silicon dioxide layer 41 are formed in a 
single piece of equipment. This is done by first heating the wafer in a 
nitrogen-containing ambiance, and then ramping the temperature upwardly 
and replacing the nitrogen-containing ambiance with an oxidizing ambiance. 
Referring now to FIG. 5, the process is completed by removing the silicon 
dioxide film 41 with a wet etch. A wet etch is preferred over a plasma 
etch because wet etches typically have greater selectivity and also 
because wet etches tend to effect less substrate damage. 
Although only several embodiments of the improved anneal process are 
disclosed herein, it will be obvious to those having ordinary skill in the 
art of integrated circuit manufacture, that changes and modifications may 
be made thereto without departing from the scope and the spirit of the 
invention as hereinafter claimed.