Systems and methods for data write loopback based timing control

Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for writing data to a storage medium.

In conventional recording systems there is a tradeoff between the longevity of data stored to a storage medium and the writeability of the storage medium. Small grain size is required for high-density recording. Such small grain size renders the stored data more susceptible to thermal agitation resulting in destruction of the magnetization representing the stored data. In some cases, medium coercivity is increased to mitigate the aforementioned effect of thermal agitation, but such an increase in coercivity has not proven able to surpass values magnetizable by about two Tesla flux densities, a limit imposed by the saturation magnetization of the soft magnetic materials of which the write head is fabricated.

Use of heat-assisted magnetic recording addresses the writeability versus longevity dilemma by locally heating the storage medium during writing to near its Curie temperature allowing magnetization by existing write head designs relying on achievable flux densities. In some cases, the heating is done using a concentrated laser beam typically of 800 nm-1000 nm wavelength; beam concentration below the diffraction limit is typically achieved using near-field techniques based on plasmon resonance. Such an approach is more fully described in D. Weller et al., “Thermal Limits in Ultrahigh-Density magnetic Recording”, IEEE Trans. Magn., Vol. 35, No. 6, p. 4423, Nov. 1999. The entirety of the aforementioned reference is incorporated herein by reference for all purposes. While such an approach offers promise of improved data storage devices and systems, current control of the laser in relation to other write circuitry has been insufficient to yield commercially viable systems.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for control of the laser relative to other write circuitry.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for writing data to a storage medium.

Some embodiments of the present invention provide methods for performing phase alignment in a recording channel. Such methods include: coupling a write output to a read data; determining a first delay from the write output to the read data; coupling a heat output to the read data; determining a second delay from the heat output to the read data; calculating a phase delay value corresponding to a difference between the first delay and the second delay; and modifying a heat data path providing the heat output to delay the heat output by an amount corresponding to the phase delay value. In some instances of the aforementioned embodiments, the methods further include: providing a write head operable to magnetize a storage medium, and providing a heat source operable to heat the storage medium. In such instances, a derivative of the write output is operable to excite the write head, and a derivative of the heat output is operable to excite the heat source.

In one or more instances of the aforementioned embodiments, determining the first delay from the write output to the read data includes: writing a pattern via a write data input; detecting the pattern in the read data; and determining a delay between a first time corresponding to when the pattern is written via the write data input and a second time corresponding to when the pattern is detected in the read data. In some cases, the pattern is a 2T pattern. In some such instances, determining the second delay from the heat output to the read data includes: writing a pattern via a write data input; detecting the pattern in the read data; and determining a delay between a first time corresponding to when the pattern is written via the write data input and a second time corresponding to when the pattern is detected in the read data.

Various embodiments of the present invention provide heat assisted loopback circuits. Such heat assisted loopback circuits include: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

In some instances of the aforementioned embodiments, the loopback circuit includes a variable gain element that is operable to provide a variable current output to an output buffer. In some cases, the variable current output varies based at least in part on the write output when the derivative of the write output is selectively coupled to the read output by the loopback circuit. In such cases, the derivative of the write output is the variable current output. In other cases, the variable current output varies based at least in part on the heat output when the derivative of the heat output is selectively coupled to the read output by the loopback circuit. In such cases, the derivative of the heat output is the variable current output. In one or more instances of the aforementioned embodiments, the loopback circuit includes: a variable gain element operable to provide a variable current output to an output buffer; and a selector circuit operable to connect at least one of the heat output and the write output to the variable gain element. In particular instances of the aforementioned embodiments, the variable gain element includes a current routing long tailed pair.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for writing data to a storage medium.

Heat-assisted magnetic recording and bit-patterned magnetic recording are two techniques offering promise of raising raise magnetic recording areal densities to approximately four terabytes per square inch, and together the promise of approximately ten terabytes per square inch. Both of the aforementioned recording methods demand a close timing match between disparate signal channels (e.g., a magnetic write path and a laser write path).

In heat-assisted magnetic recording, a heat source is pulsed in a controlled phase relationship with a write current provided to a magnetic recording head. In some cases, the heat source is a diode laser that illuminates the surface of a storage medium local to the write head. In bit-patterned magnetic recording, write current transitions must be aligned closely with lithographically deposited single-domain islands on the record medium. The write current is produced by a magnetic data write path and the heat source pulse is produced by a laser data write path. Both the magnetic data write path and the laser data write path may be part of a write portion of a recording channel. The write current and the heat source pulse are provided to a read/write head assembly disposed near the surface of a storage medium. The read/write head assembly includes a write head that is excited by the write current, and a heat source excited by the heat source pulse. In some cases, the write current and the heat source pulse are provided to the read/write head assembly through flexible transmission lines, receiving circuits, and high-power driver amplifier circuits. Transport delay and skew through the magnetic data write path and the laser data write path is affected by temperature and humidity and by the dissimilar driver and encoding circuitry.

In bit-patterned magnetic recording, propagation delay shifts through both a read head and the write head affect transition alignment to bit lands unless the shifts are calibrated out. Some embodiments of the present invention provide the means to establish a specified time relationship between the write current produced by the magnetic data write path and the heat source pulse produced by the laser data write path for heat-assisted magnetic recording or for a combined heat-assisted magnetic recording and bit-patterned magnetic recording system. Various embodiments of the present invention may be used in relation to circuitry described in U.S. patent application Ser. No. 12/838,601 entitled “Disk File Preamplifier Frequency-Response and Time Delay Compensation”, and filed by Ross Jul. 19, 2010. The entirety of the aforementioned reference is incorporated herein by reference for all purposes.

Turning toFIG. 1, a data storage system100is shown that may be, for example, a hard disk drive. Data storage system100includes a read channel circuit110having a heat write and magnetic write loopback based timing alignment circuit in accordance with various embodiments of the present invention. The heat write and magnetic write loopback based timing alignment circuit includes an ability to control the phase alignment of a heat source and a magnetic source in a read/write head assembly176. In some embodiments, the heat source is a laser. In one particular embodiment of the present invention, the laser is a JDS Uniphase 50 mW 830 nm diode. Such loopback based timing alignment control enhances the write effectiveness of read/write head assembly as it writes information to a disk platter178. Disc platter178may be fabricated with a continuous magnetic-recording layer, or in the case of BPMR (Bit Patterned Media Recording), with a layer having discrete magnetic islands each corresponding to a single bit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of constructions that may be used for disk platter178. It should be noted that data storage system100may include many disk platters with one or more read/write head assemblies associated with each disk platter. As just one example, data storage system100may include four disk platters and eight read/write head assemblies respectively associated with each of the eight storage surfaces of the four disk platters. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of number of disk platters and read/writer head assemblies, and configurations thereof that may be used in relation to different embodiments of the present invention.

Data storage system100also includes a preamplifier170, an interface controller120, a hard disk controller166, a motor controller168, and a spindle motor172. Interface controller120controls addressing and timing of data to/from disk platter178. The data on disk platter178consists of groups of magnetic signals that may be detected by read/write head assembly176when the assembly is properly positioned over disk platter178. In one embodiment, disk platter178includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical write operation, read/write head assembly176is accurately positioned by motor controller168over a desired data track on disk platter178. Motor controller168both positions read/write head assembly176in relation to disk platter178and drives spindle motor172by moving read/write head assembly178to the proper data track on disk platter178under the direction of hard disk controller166. Spindle motor172spins disk platter178at a determined spin rate (RPMs). Once read/write head assembly178is positioned adjacent the proper data track, a magnetic field is generated in read/write head assembly causing the surface of disk platter to be magnetized with a field corresponding to a write data101input (after encoding and processing by read channel circuit110). At the same time, the area on disk platter178where the data is to be written is heated using a heat source to allow for enhanced writeability. In a read process, magnetic signals representing data on disk platter178are sensed by read/write head assembly176as disk platter178is rotated by spindle motor172. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter178. This minute analog signal is transferred from read/write head assembly176to read channel circuit110via preamplifier170. Preamplifier170is operable to amplify the minute analog signals accessed from disk platter178. In turn, read channel circuit110decodes and digitizes the received analog signal to recreate the information originally written to disk platter178. This data is provided as read data103to a receiving circuit. The heat source and magnetic source may be phase aligned or phase offset in a controlled manner using write circuitry similar to that discussed below in relation toFIGS. 2-5, and/or methods consistent with that discussed below in relation toFIG. 6.

It should be noted that storage system100may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. It should also be noted that various functions or blocks of storage system100may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.

Turning toFIG. 2, a circuit portion200is shown in accordance with some embodiments of the present invention that includes elements of a read channel circuit210, preamplifier circuit250, a heat source280, a write head290and a read head295. In some implementations, heat source280, write head290and read head295are included in a common read/write head assembly that may be disposed in close proximity to a storage medium (not shown). Write head290may be any circuit or device known in the art that is capable of generating a magnetic field sufficiently large to magnetize a defined region of the storage medium. As just one example, write head290may be a magneto-resistive (MR) write head as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of write heads that may be used in relation to different embodiments of the present invention. In some embodiments of the present invention, heat source280is a laser as is known in the art. When excited, the laser generates heat at the defined location where a write is occurring. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of heat sources including, but not limited to, specific types of lasers that may be used in relation to different embodiments of the present invention. Read head295may be any circuit or device known in the art that is capable of sensing a magnetic field from information previously stored to a storage medium.

A controller circuit270is included that provides control signals274to read channel circuit210and control signals272to a loopback controller circuit271of preamplifier circuit250. Control circuit270may be any circuit capable of providing control to the operations of circuit portion200, and for determining a phase offset between read data203and write data201. In some embodiments of the present invention, control circuit270includes a microcontroller that executes firmware as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of control circuits that may be used in relation to different embodiments of the present invention.

Read channel circuit210includes a master clock circuit215that generates a clock signal217to which write operations are synchronized. In some cases, the phase and frequency of clock signal217are adjusted by master clock circuit215based upon timing recovery data202from a timing recovery circuit267. Timing recovery circuit267receives read data derived from read head295. In particular, read head295senses magnetic information from a storage medium and provides a read signal297to a receiver/amplifier circuit257within preamplifier circuit250. Receiver/amplifier circuit257amplifies the received read data and provides a corresponding amplified read signal258to read channel circuit210. Amplified read signal258is amplified by a variable gain amplifier circuit259, and a variable gain amplified signal262is provided to a filter circuit263. Variable gain amplifier circuit263may be any circuit known in the art that is capable of applying a variable gain to a received analog signal. Filter circuit263filters the received input and provides a corresponding filtered output264. Filter circuit263may be any circuit known in the art that is capable of filtering a received analog signal. Timing recovery circuit267uses filtered output264to recover timing information related to the data read from the storage medium. Timing recovery circuit267may be any circuit known in the art that is capable of recovering timing from a received data set. The recovered timing information is then provided to master clock circuit215as timing recovery data202. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of clock circuits and timing recovery circuits that may be used in relation to different embodiments of the present invention.

Filtered output264is also provided to a data decoder/detection circuit268. Data decoder/detection circuit268may be any circuit known in the art that is capable of receiving an encoded analog stream in digital format and recovering the originally written data set. In some embodiments of the present invention, data decoder/detection circuit268includes one or more pairs of data detector and data decoders. Upon processing filtered output264, data decoder/detection circuit268and timing recovery circuit267may share certain elements, for example, analog to digital conversion and adaptive equalization. Data decoder/detection circuit268yields the original data set which is provided as read data203. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data processing circuits that may be used in place of data decoder/detection circuit in accordance with the various embodiments of the present invention.

Write data201destined for storage to the storage medium may be received from an upstream source (not shown). Such write data may be received as a series of WORDS which each contain a number of individual bits. Such WORDS may be, for example, thirty-two bit words, sixty-four bit words, or one hundred, twenty-eight bit words. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources from which write data201may be received, and a number of formats that write data201may exhibit. Write data201is received by a magnetic write encoder circuit230and encoded in preparation for writing as magnetic information on a storage medium. The resulting data is provided as encoded data232to a data serializer circuit235. Magnetic write encoder circuit230may be any circuit known in the art that receives data and encodes that data in preparation for writing as magnetic information to a storage medium. Data serializer circuit235accepts parallel encoded data232at an input clock rate, and provides a serial data stream237at an output clock rate. As an example, where encoded data is received eight bits at a time, serial data stream237may be provided at eight times the rate of the input clock.

A clock218used by data serializer circuit235to synchronize the serialization process is provided by a variable phase shift circuit219. Variable phase shift circuit219delays clock signal217by an amount corresponding to a phase delay value226from a programmable phase shift register224. Of note, variable phase shift circuit219us used to support BPMR, but is not used for HAMR (Heat Activated Magnetic Recording). Variable phase shift circuit219may be implemented as a programmable phase interpolator. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of implementations of delay circuits that may be used in relation to different embodiments of the present invention. Programmable phase shift register224is written by controller circuit270using control signals274.

Serial data stream237is provided to a magnetic write pre-compensation circuit240that pre-compensates the received data and provides a pre-compensated write signal247to preamplifier circuit250. It is customary to pre-compensate the magnetic write data signal to counteract the bit-shift effect of adjacent transition patterns, and magnetic write pre-compensation circuit240may be any circuit known in the art that is capable of pre-compensating a data input in preparation for writing to a storage medium. Of note, in some embodiments read channel circuit210and preamplifier circuit250are implemented in separate physical packages. In some such cases, pre-compensated write signal247is provided to preamplifier circuit250via a flexible connector. While it is not shown, in some embodiments of the present invention, heat data may also be pre-compensated. In such cases, read channel circuit210would additionally include a heat data pre compensation circuit.

In addition, phase shifted clock218from variable phase shift circuit219is applied also to a second variable phase shift circuit220that operates to deliver variably-phase-shifted heat control clock245to the preamplifier. This applied phase delay operates to modify the relative alignment of heat write signal245and pre-compensated write signal247in accordance with the following equation:
Phase Offset=φHeat Write Signal−φPre-Compensate d Write Signal,
where φHeat Write Signalis the phase of heat write signal245and φPre-Compensate d Write Signalis the phase of pre-compensated write signal247. Of note, as depicted only a positive phase shift is possible as variable phase shift circuit220only applies a phase delay to serial data stream237. However, in some embodiments of the present invention, magnetic write pre-compensation circuit240applies a fixed delay to serial data stream237as part of generating pre-compensated write signal247. As such, where variable phase shift circuit220applies a phase delay less than the fixed delay applied by magnetic write pre-compensation circuit240, an effective negative delay can be applied to heat write signal245in accordance with the following equation:
Phase Offset=φHeat Write Signal−φPre-Compensate d Write Signal+φFixed,
where φFixedis the fixed delay applied by magnetic write pre-compensation circuit240. Phase delay value227is written to a programmable phase shift value register225by controller circuit270as part of a calibration process that is more fully described below.

Variable phase shift circuit220may be implemented as a programmable phase interpolator. It should also be noted that the variable delay implemented by variable phase shift circuit220may instead be implemented as delay cells within preamplifier circuit250. In some cases, the delay cells are programmably variable. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of implementations of delay circuits that may be used in relation to different embodiments of the present invention.

AlthoughFIG. 2shows distinct heat and magnetic write data signals, one or both may be multiplexed onto other preamplifier pins, to conserve flex and die area. Preamplifier circuit250includes a loopback control circuit271that is operable to control the aforementioned calibration process. An output driver260receives heat write signal245and provides a corresponding differential excitation signal282(of note, the excitation signal may be single ended) to heat source280; and an output driver255receives pre-compensated write signal247and provides a corresponding differential excitation signal292to write head290. To assure accommodation of as many potential path differences between exciting heat source280and exciting write head290, it is beneficial to determine the phase difference between differential excitation signal292and differential excitation signal282close to heat source280and write head290. Thus, in some embodiments of the present invention, a series of output drivers may be used in place of output driver255and output driver260with a final stage output driver driving the respective differential excitation signal292and differential excitation signal282(again, the excitation signal may be single ended) and a prior output driver providing the respective interim signal256and interim signal261to detect the phase offset by phase control circuit271.

Where heat source280is a laser and heat write signal245is used to stimulate the laser, properly phased laser illumination of the medium relative to the transitions of a magnetic field generated by write head280enhances storage capability. The transition gradient is a function of rates-of-change both of a differential excitation signal292to write head290and the temperature (T) of the storage medium local to the write area in accordance with the following equation:

ⅆHTotalⅆx=ⅆHWriteⅆx+ⅆHcⅆT×ⅆTⅆx.
Multiplying through by velocity

(ⅆxⅆt)
yields a time-dependent equation describing the effect of temporal shift between magnetic excitations (corresponding to differential excitation signal292) and thermal excitations (corresponding to differential excitation signal282). Independent of the areal-density benefits secured by precise phasing of the heat and magnetic signals, pulsing the heat source results in lower slider temperature hence improved reliability.

It should be noted that while the magnetic data path (i.e., the path from write data201to serial data stream237may be bifurcated to include a separate path from write data201to variable phase shift circuit220and from write data201to magnetic write pre-compensation circuit240. For example, the data provided as heat write signal245may be encoded and serialized, possibly using a code different from that used in the magnetic channel such as, by controlling the heat source by a variable-duty-cycle clock of bit rate frequency.

The support provided in circuit portion200for bit-patterned magnetic recording include the read data path yielding timing recovery data202and master clock circuit215that closely locks a write clock to read servo data and/or special island-timing information pre-recorded on the medium. Additionally, the support includes variable phase shift circuit219and programmable phase shift value register224that together operate to phase the written transitions properly relative to the bit patterned magnetic recording lands on the storage medium. In contrast, where heat assisted magnetic recording is used alone the clock from master clock circuit may be free running or a clock only loosely referenced to servo data retrieved using read head295.

Turning toFIG. 3, a preamplifier circuit300is shown that relies on a loopback cell operable to control phase alignment of the various signals involved in writing a storage medium. Preamplifier circuit300includes an input receiver320receiving a heat input305and providing a corresponding output327to an output driver350. Output driver350provides a corresponding differential excitation signal387to a heat source380. In some cases, heat source380is a pulsed laser. An input receiver circuit330receives a magnetic input310and provides a corresponding output337to an output driver355. Output driver355provides a corresponding differential excitation signal392to a write head390. Receiver330includes an internal receiver331providing an interim drive signal338that closely mimics output337. In some embodiments of the present invention, internal receiver331is implemented using positive emitter coupled logic (PECL). In addition, preamplifier circuit300includes a read data receiver357operable to receive a read signal397from a read head395. Receiver357drives read signal397as an output347to an output driver340that in turn provides a read output315.

Interim drive signal338, an output corresponding to excitation signal392(via an input buffer383), and an output corresponding to excitation signal387(via an input buffer384) are provided to a loopback circuit360that is operable to provide an injection signal376that is added to the read path. Loopback circuit360includes a loopback control circuit380that selects which of interim drive signal338, the output corresponding to excitation signal392or the output corresponding to excitation signal387drives a variable gain element374. More particularly, loopback control circuit380asserts a selector signal382causing one of the aforementioned signals to be applied to variable gain element374. In some embodiments of the present invention, selection between the three sources is done using a selector circuit as are known in the art. In one particular embodiment of the present invention, variable gain element374may be implemented as a current switch that provides a variable amplitude current mode differential signal372to drive an output buffer370. The amount of gain may be programmably varied to assure that read output315remains in a linear regime over all of its gain settings. In one example, variable gain element374may be implemented using conventional techniques, such as, for example, using a current-routing long-tailed pair having a programmable variable tail current source. Output buffer370provides injection signal376to output347. This augmentation of injection signal376with output347may be done simply by tying two signal lines together and enabling the corresponding source (block357or370), or may be done by using a driver circuit (not shown) internal to output driver340. In some embodiments of the present invention, output buffer370is added effectively in parallel to read data receiver357, and configured such that injection signal376may be selected under user control in lieu of output347from read data receiver357. In similar fashion, input buffer383is effectively in parallel with output driver350, and input buffer384is effectively in parallel with output driver355.

In operation, interim drive signal338may be chosen by loopback control circuit380when loopback correction is performed for fly-height measurement. One example of such fly-height measurement is disclosed in U.S. patent application Ser. No. 12/838,601 entitled “Disk File Preamplifier Frequency-Response and Time Delay Compensation”, and filed by Ross Jul. 19, 2010. The entirety of the aforementioned reference was previously incorporated herein by reference for all purposes. Alternatively, when loopback correction is provided for time delay compensation in bit patterned magnetic recording to change the phase offset applied by variable phase shift circuit219ofFIG. 2, the output corresponding to excitation signal392is selected by loopback control circuit380. As yet another alternative, when loopback correction is provided for time delay compensation in heat assisted magnetic recording to change the phase offset applied by variable phase shift circuit220ofFIG. 2, the output corresponding to excitation signal387is selected by loopback control circuit380. The frequency response of the selector circuit controlled by loopback control circuit380should be flat to beyond the desired test frequencies.

In general, including the write loopback driver166in the loopback excitation path is undesirable during fly-height loopback compensation calibration, as pulse asymmetries may affect the extracted loopback harmonic amplitudes. For bit patterned magnetic recording, the additional input buffer383is included in the loopback excitation path. Input buffer383generally mimics the operation of the normal output driver355, albeit at lower internal swings, while preserving the time-delay versus temperature properties of the normal output driver355. In this way, a bit patterned magnetic loopback operation may measure delay from the write data path from magnetic input310to read output315. Whenever fly-height correction loopback is active, output driver355may be disabled to prevent inadvertent writing on the storage medium (not shown). In some cases during bit patterned magnetic loopback, output driver355may be disabled, while in other cases output driver355may remain active to allow dynamic correction of write clock phasing during a write operation. For heat assisted magnetic recording, the additional input buffer384is included in the loopback excitation path. Buffer384generally mimics the operation of the normal output driver350, albeit at lower internal swings, while preserving the time-delay versus temperature properties of the normal output driver350. In some cases, the signals of output driver350and output driver355are tapped off as near as possible to heat source385and write head390, respectively. In this way, a heat assisted magnetic loopback operation may measure delay from the write data path from magnetic input310to excitation signal387. Whenever fly-height correction loopback is active, output driver355and output driver350may be disabled to prevent inadvertent writing on the storage medium (not shown). In some cases during bit patterned magnetic loopback, output driver355and output driver350may be disabled, while in other cases output driver355and output driver350may remain active to allow dynamic correction of write clock phasing during a write operation. It should be noted that preamplifier circuit300may service a number of read/write head assemblies (i.e., more than one of each of heat source385, write head390and read head395).

Turning toFIG. 4, an alternative implementation of a preamplifier circuit400that may be used in relation to various embodiments of the present invention is depicted. Preamplifier circuit400includes an input receiver420receiving a heat input405and providing a corresponding output427to an output driver450via a heat data write path425. Heat data write path425includes the various connections and/or circuitry through which heat input405passes in transit to output driver450. Output driver450provides a corresponding differential excitation signal487to a heat source485. In some cases, heat source485is a pulsed laser.

An input receiver circuit430receives a magnetic input410and provides an interim write output432that is in turn provided as an output437to an output driver455via a magnetic data write path435. Magnetic data write path435includes the various connections and/or circuitry through which magnetic input410passes in transit to output driver455. Output driver455provides a corresponding differential excitation signal492to a write head490. In some cases, write head490is an MR head as are known in the art.

Interim write output432, output437, and output427are provided to a loopback circuit460that is operable to provide a selected loopback signal as a read data output415. More particularly, Interim write signal432is provided to a loopback injection and gain control circuit474. Output437is provided to a dummy load483that is used for bit patterned magnetic recording feedback. Dummy load483mimics the operation of output driver455such that an output487from dummy load483reasonably closely approximates the timing of excitation signal492. Output427is provided to a dummy load484that is used for heat assisted magnetic recording feedback. Dummy load484mimics the operation of output driver450such that an output486from dummy load484reasonably closely approximates the timing of excitation signal487.

A read head495is operable to sense information from a storage medium (not shown) and to provide a corresponding read signal497to an input receiver457. Input receiver457provides an output447via a read data path454. Read data write path454includes the various connections and/or circuitry through which read data passes in transit to output447. A dummy loopback cell including common mode and null431operates to mimic a load expected by input receiver457as an output driver of the read data. Dummy loopback cell431provides a read output488to a dummy read cell470that drives read data output415. Dummy read cell470drives read data output415in accordance with an injection input472received from loopback injection and gain control circuit474. It should be noted that preamplifier circuit400may service a number of read/write head assemblies (i.e., more than one of each of heat source485, write head490and read head495).

In operation, a loopback control circuit480is programmed to select which of the various available signals are to be looped back as read data output415. The selection of the particular loopback scheme is controlled by a control output482driven by loopback control circuit480. Such programming may be done using a programmable interface499from a system controller (not shown). Loopback control circuit480may be, for example, a microcontroller. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuits that may be used to implement loopback control circuit480in accordance with different embodiments of the present invention. Further, loopback control circuit480may be programmed to assure that read data output415remains in a linear regime over all of its gain settings.

In particular, when loopback correction is to be performed for fly-height calibration, interim write output432is selected and operated on by loopback injection and gain control circuit474. In particular, loopback injection and gain control circuit474amplifies interim write signal432and a corresponding variable amplitude current mode signal is provided as injection signal472to drive dummy read cell470. In turn, dummy read cell470drives read data output415with a signal corresponding to injection signal472. In some cases, the variable gain element of loopback injection and gain control circuit474may be implemented using conventional techniques, such as, for example, using a current-routing long-tailed pair having a programmable variable tail current source.

Alternatively, when loopback correction is provided for time delay compensation in bit patterned magnetic recording to change the phase offset applied by variable phase shift circuit219ofFIG. 2, output487is selected and operated on by loopback injection and gain control circuit474. In particular, loopback injection and gain control circuit474amplifies output487and a corresponding variable amplitude current mode signal is provided as injection signal472to drive dummy read cell470. In turn, dummy read cell470drives read data output415with a signal corresponding to injection signal472. As a third alternative, when loopback correction is provided for time delay compensation in heat assisted magnetic recording to change the phase offset applied by variable phase shift circuit220ofFIG. 2, output486is selected and operated on by loopback injection and gain control circuit474. In particular, loopback injection and gain control circuit474amplifies output486and a corresponding variable amplitude current mode signal is provided as injection signal472to drive dummy read cell470. In turn, dummy read cell470drives read data output415with a signal corresponding to injection signal472.

FIGS. 5a-5cshow a more detailed diagram of one implementation of the preamplifier circuit400in accordance with some embodiments of the present invention. Turning toFIG. 5a, an overall circuit500includes output driver450that receives output437and drives excitation signal487to heat source485. Of note, output437is shown as a differential signal as are other signals within output driver450. Such a differential implementation provides an advantage of reducing propagation delays and permit polarity switching through use of differential clocking. Other implementations may use single ended technology. Output driver450includes a load driver502and an output driver504. Load driver502serves a similar purpose to dummy load484. Interim signals506,508between load driver502and output driver504are provided to an edge selector circuit568that is controlled by an edge select input. In some embodiments, interim signals506,508are tapped as near to excitation signal487as possible to allow for more accurate representation of the timing of excitation signal487. Portions of output driver450to the right of the tap point of interim signals506,508are assumed to exhibit substantially stable delays, or at least slow changing delays which can be calibrated out using multiple loopback sequences.

Edge selector circuit568is operable to select a polarity of heat data input437to use. In some cases, edge selector circuit568is implemented as an exclusive-or gate that allows examination of either positive or negative going edges of interim signals506,508depending upon the assertion level of the edge select input. By making both positive and negative edge phase measurements in succession, the width of a laser control pulse used to drive heat source485(where heat source485is a laser) the laser control pulse can be determined if necessary. In some embodiments of the present invention, edge selector circuit568is implemented using differential current mode logic to reduce propagation delay and permit polarity switching through use of differential clocking.

Since heat data input437undergoes a complete on/off cycle in each data bit time T, were the pulse signal looped back directly it may fall outside the passband of the read data path which is customarily about ½T. Accordingly, a flip-flop566is configured as a divide by two counter, with the output of flip-flop566driving a differential AND gate564. By performing the divide by two operation, the maximum frequency of the loopback signal corresponding to heat data input437is half the data rate (i.e., ½ cycle per bit time). In some embodiments of the present invention, a flip-flop566is implemented using differential current mode logic to reduce propagation delay and permit polarity switching through use of differential clocking.

Overall circuit500also includes output driver455that receives output432and drives excitation signal492to write head490. Of note, output432is shown as a differential signal as are other signals within output driver455. Such a differential implementation provides an advantage of reducing propagation delays and permit polarity switching through use of differential clocking. Other implementations may use single ended technology. Output driver455includes a load driver512and an output driver514. Load driver512serves a similar purpose to dummy load483. Interim signals516,518between load driver512and output driver514are provided to an differential AND gate560. In some embodiments, interim signals516,518are tapped as near to excitation signal492as possible. Portions of output driver455to the right of the tap point of interim signals516,518are assumed to exhibit substantially stable delays, or at least slow changing delays which can be calibrated out using multiple loopback sequences.

The fly height input447from the read data path is provide to a differential AND gate562. An output574from AND gate564, an output572from AND gate562, and an output570from AND gate560are all provided to a selector circuit583. Selector circuit583selects between the received inputs based upon a select bit482from loopback control circuit480. Select bit482operates to select either patterned magnetic data (i.e., output570), heat-assisted magnetic data (i.e., output574), or fly height data (i.e., output572) to be provided as an output to a loopback injection and gain control circuit584. Ultimately, injection output472from loopback injection and gain control circuit584is provided to a dummy loopback read cell470that drives read data output415.

Turning toFIG. 5b, a loopback injection circuit535is depicted that may be used in place of loopback injection and gain control circuit584. Loopback injection circuit535is implemented as a high-speed current-switched long-tailed pair having an adjustable tail current source536. Current source536may be made variable in order to maintain linear read circuit operation over the full range of read gain selections. A resistive divider composed of resistors R1and R2attenuates the output of the current-switch pair, allowing the pair to operate at a collector current near that required to achieve maximum Ft. Further, the resistive divider also performs voltage-to-current conversion working into the source of the common-gate loopback output stage. Of note, switches537are used to disable the input from the read head allowing for the loopback mode where the read data output is driven by one of the selected loopback sources. Variants such as omitting switches537and requiring that the read head not be reading (i.e., be at zero MR bias, or be positioned over an erased region of the medium) will be apparent to one skilled in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other gain and injection stages that may be used in relation to different embodiments of the present invention.

Turning toFIG. 5c, a low-noise input stage545is depicted that may be used in place of receiver457to receive reader data derived from the storage medium. Of note, the circuit would include one input stage545for each reader head that is deployed. Where more than one read head is deployed, only one reader head and the corresponding input stage545would typically be activated by a programmable port (not shown). Of note, switches546are used to disable the input from the read head allowing for the loopback mode where the read data output is driven by one of the selected loopback sources. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other input stages that may be used in relation to different embodiments of the present invention. For example, while input stage545is depicted as using a common-gate topology, other approaches are possible including, but not limited to, shunt feedback and common source/emitter.

Turning toFIG. 6, a flow diagram600shows a method in accordance with some embodiments of the present invention for performing phase alignment in a recording channel. Following flow diagram600, it is determined whether one of the supported loopback modes has been selected (block605). A loopback may be selected, for example, by controller circuit270writing control signals272to loopback controller circuit271. It is then determined what type of a loopback control has been selected. In particular, it is determined whether heat assisted magnetic recording loopback has been selected (block610). Where the selected loopback is other than heat assisted magnetic recording loopback or bit patterned magnetic recording loopback (block610), a fly height calibration loopback is performed (block615). Such a loopback may be performed similar to that described in relation to FIGS. 15-16 of U.S. patent application Ser. No. 12/838,601 entitled “Disk File Preamplifier Frequency-Response and Time Delay Compensation”, and filed by Ross Jul. 19, 2010. The entirety of the aforementioned reference was previously incorporated herein by reference for all purposes.

Alternatively, where the selected loopback is heat assisted magnetic recording loopback (block610), a phase delay value and an integral value are initialized to zero (block620), and the phase delay value is written to the register corresponding to heat assisted magnetic recording (block625). As an example, this may include controller circuit270writing a zero value to programmable phase shift value register225. The value written to programmable phase shift value register225is provided as phase shift value227to variable phase shift circuit220that imposes a phase delay on the heat write data provided to the preamplifier.

The bit patterned magnetic recording loopback configuration is selected (block630). This selection may include, for example, selecting magnetic input310to be fed back as read output315. A predefined write pattern is then written as magnetic input (block635). In some cases, the write pattern is a repeating 2T pattern (i.e., 11001100 . . . ). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of patterns that may be written in accordance with different embodiments of the present invention. Writing the pattern may include, for example, writing the pattern as write data201to magnetic write encoder circuit. A time delay between the write data and the looped back read data is calculated (i.e., Tm) (block640).

The heat assisted magnetic recording loopback mode is selected (block645). This selection may include, for example, selecting heat input305to be fed back as read output315. A predefined write pattern is then written as heat input (block650). In some cases, the write pattern is a repeating 2T pattern (i.e., 11001100 . . . ). Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of patterns that may be written in accordance with different embodiments of the present invention. Writing the pattern may include, for example, writing the pattern as write data201to magnetic write encoder circuit. A time delay between the write data and the looped back read data is calculated (i.e., Th) (block655).

A difference between the calculated loopback delays is calculated (block655) in accordance with the following equation:
Δ=Tm−Th.
It is then determined whether an absolute value of the calculated difference value is greater than a threshold value (block660). Where the absolute value of the calculated difference value is not greater than the threshold value (block660), the process ends as the delay imposed by the phase delay value is sufficient to align the excitation of the write head with the excitation of the heat source.

Alternatively, where the calculated difference value is greater than the threshold value (block660), an updated phase delay value is calculated (block670) in accordance with the following equation:
Phase Delay Value=−(Kp·Δ+K1·α),
where Kp is an integral compensation coefficient and K1is a proportional compensation coefficient. In addition, an updated integral value is calculated in accordance with the following equation:
α=α+Δ.
The updated phase delay value is then written to the register corresponding to heat assisted magnetic recording (block675). As an example, this may include controller circuit270writing a the updated phase delay value to programmable phase shift value register225. The value written to programmable phase shift value register225is provided as phase shift value227to variable phase shift circuit220that imposes a phase delay on the heat write data provided to the preamplifier. With this updated phase delay value thus programmed, the processes of blocks630-675are repeated.