Phase divider for complex signals

In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

BACKGROUND OF THE INVENTION 
The present invention relates generally to phase dividers, and more 
particularly to a frequency divider for quadrature signals. 
In synchronous detectors for M-ary phase shift keyed signals, a series of 
an M-th power multiplier, a low-pass filter and a 1/M frequency divider is 
connected to the output of an A/D converter to recover the transmitted 
carrier for synchronously detecting the original signal. The 1/M frequency 
divider comprises an xy-to-8 (phase) conversion table which detects the 
phase angle of quadrature (complex) signals from the A/D converter and 
supplies it to a phase divider that divides the detected phase angle with 
a ratio 1/N. The output of the phase divider is coupled to a sine 
translation table and a cosine translation table to generate cosine (real 
part) and sine (imaginary part) wave signals. The phase .theta..sub.i of 
the input signal to the 1/M frequency divider is defined within the range 
between -.pi. and +.pi.. If there is a phase change of 2.pi., the input 
phase can be represented as .theta.'.sub.i =.theta..sub.i +2.pi.. However, 
the phase conversion table cannot discriminate between .theta.'.sub.i and 
.theta.".sub.i and treats the input phase equivalently as .theta.".sub.i 
=.theta..sub.i (mod 2.pi.). Under such circumstances, the division by the 
phase divider results in a phase angle .theta.".sub.i /M=.theta..sub.i /M. 
Since it must be .theta.'.sub.i /M=.theta..sub.i /M+2.pi./M, a phase error 
of 2.pi./M results. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide a phase 
divider capable of phase division without introducing quantum variations 
of phase. 
The phase divider of the present invention comprises a first complex 
limiter for receiving a variable amplitude input complex signal formed by 
a sequence of samples of real and imaginary values for limiting the 
amplitude of the complex signal to a constant amplitude of unit value. A 
first complex multiplier multiplies the complex signal from the first 
complex limiter with a first feedback complex signal and applies its 
output through a loop filter to a second complex multiplier where the 
input signal is multiplied with a second feedback complex signal. A second 
complex limiter is provided for limiting the amplitude of the signal from 
the second complex multiplier to a constant amplitude of unit value. The 
output of the second complex limiter is delayed by a sample interval and 
applied to the second complex multiplier as the second feedback complex 
signal. A complex multiplier of M-th power raises the delayed complex 
signal to an M-th power and applies it to the first complex multiplier as 
the first feedback complex signal. 
Each of the complex limiters comprises first and second squaring circuits 
for respectively squaring the real and imaginary components of an input 
signal applied to the limiter, an adder for summing outputs of the first 
and second squaring circuits, a root-and-divide-one circuit for detecting 
a square root of an output signal of the adder and dividing a unit value 
by the detected square root, and first and second multipliers for 
multiplying the real and imaginary components of the input signal with an 
output signal of the root-and-divide-one circuit.

DETAILED DESCRIPTION 
In FIG. 1, a phase divider of the present invention comprises a first 
complex limiter 1 for receiving through input terminals A.sub.1, A.sub.2 a 
variable amplitude input complex signal which is a sequence of digital 
samples of real and imaginary values for limiting the amplitude of the 
input complex signal to a constant amplitude of unit value. A first 
complex multiplier 2 is connected to the outputs of the first complex 
limiter 1 for multiplying the complex signal from the first complex 
limiter 1 with a first feedback complex signal supplied from a complex 
multiplier 8 of M-th power which is connected to the outputs of one-sample 
delay circuits 6, 7. The M-th power complex multiplier 8 is a series of 
are complex multipliers 8.sub.1, 8.sub.2, . . . 8.sub.(M-1), each 
multiplying the input complex signal from one-sample delay circuits 6, 7 
with the output of the preceding stage. 
A complex low-pass (loop) filter 3 is connected between the first complex 
multiplier 2 and a second complex multiplier 4 having identical 
configuration to multiplier 2 to remove high frequency components. The 
second complex multiplier 4 multiplies the outputs of low-pass filter 3 
with a second complex feedback signal from the output terminals B.sub.1, 
B.sub.2. A second complex limiter 5, identical to limiter 1, is connected 
to the outputs of multiplier 4 for limiting the amplitude of the input 
complex signal therefrom to a constant amplitude of unit value. One-sample 
delay circuits 6 and 7 are provided for introducing a one-sample interval 
to the outputs of limiter 5 for application to output terminals B.sub.1, 
B.sub.2, on the one hand, and to the second complex multiplier 4 as the 
second feedback complex signal, on the other. 
As illustrated, complex limiter 1 is made up of squaring circuits 11 and 12 
connected to input terminals A.sub.1 and A.sub.2, respectively, the 
outputs of squaring circuits 11, 12 being summed by an adder 13 and fed to 
a root-and-divide-one circuit 14. Multipliers 15 and 16 are respectively 
connected to input terminals A.sub.1 and A.sub.2 to multiply the real and 
imaginary components of the input complex signal with the output of 
root-and-divide-one circuit 14. If the input complex signal is represented 
as W.sub.1 =u.sub.1 +j.multidot.v.sub.1, where u.sub.1 and v.sub.1 are the 
real and imaginary parts of the signal, respectively, then the outputs of 
multipliers 15 and 16 form an output complex signal W.sub.2 which is given 
by: 
##EQU1## 
Since 
##EQU2## 
the amplitude of the input complex signal of limiter 1 is normalized to a 
constant amplitude of unit value. 
Complex multiplier 2 comprises a first pair of multipliers 21 and 22 and a 
second pair of multipliers 23 and 24. The first input of multipliers 21 
and 23 is connected to the output of multiplier 15 and the first input of 
multipliers 22 and 24 is connected to the output of multiplier 16. A 
subtractor 24 is connected between the outputs of the multipliers of the 
first pair to produce a signal which forms the real part of the complex 
output of multiplier 2. An adder 25 is connected between the outputs of 
the multipliers of the second pair to produce a signal which forms the 
imaginary part of the output. The second input of multipliers 21 and 24 is 
connected to one output of multiplier 8, the second input of multipliers 
22 and 23 being connected to the other output of multiplier 8. If the 
feedback complex signal from multiplier 8 is represented as W.sub.3 
=u.sub.3 +j v.sub.3 =r.sub.3 e.sup.j.theta.3 and the complex signal from 
the preceding stage is represented as W.sub.2 =u.sub.2 +j v.sub.2 =r.sub.2 
ej.theta.2, then the complex output of multiplier 2 is: 
##EQU3## 
Since W.sub.2 and W.sub.3 are both normalized to unit value, W.sub.2 
.times.W.sub.3 is equal to e.sup.j(.theta.2+.theta.3). 
It is seen that by normalizing the amplitude of complex signals to a unit 
value the multiplication of these signals is equivalent to a summation of 
their phase components. An equivalent circuit of the phase divider can be 
represented is shown in FIG. 2 as comprising a subtractor 30 corresponding 
to multiplier 2, loop filter 31 corresponding to filter 3, an adder 32 
corresponding to multiplier 4, delay operator 33, and a M-fold phase 
multiplier 34 corresponding to M-th power multiplier 8. In FIG. 2, the 
signals are represented by z-transform of input phase .theta..sub.i (t) 
and output phase .theta..sub.o (t), where z=e.sup.j.omega.T (T=sampling 
intervals) and the following relations hold: 
##EQU4## 
Since H.sub.o (z)=H(z).z.sup.-1 /(1-z.sup.-1){H.sub.i (z)-M.H.sub.o (z)}, 
the transfer function T(z) of the phase divider is given by the following 
relation: 
##EQU5## 
Since the M.multidot.H(z) terms of Equation (2) imply that the loop filter 
has a gain M, and so Equation (2), as a whole, indicates that the phase 
divider of the present invention has the effect of dividing an input phase 
with a ratio M without introducing undesirable quantum phase "jumps". 
If loop filter 3 is constructed as shown in FIG. 3 having the following 
z-transform function H(z): 
##EQU6## 
then, the transfer function T(z) is given by: 
##EQU7## 
By denoting M.alpha.=A, M.beta.=B, Equation (4) can be rewritten as: 
##EQU8## 
If z=e.sup.s/fs, (where fs is the sampling frequency), and if the sampling 
frequency is sufficiently high, z=e.sup.s/fs .apprxeq.H.multidot.s/fs, and 
z.apprxeq.1, and T(z) is represented as:. 
##EQU9## 
Equation (6) indicates that the phase divider operates in a manner similar 
to conventional phase locked loops. 
The phase divider of the present invention is incorporated in a synchronous 
detector for M-ary phase-shift keying signals as shown in FIG. 4. The 
synchronous detector comprises mixers 40, 41 for mixing an incoming IF 
(intermediate frequency) signal with an in-phase carrier from a local 
oscillator 42 and a quadrature-phase carrier supplied from a phase shifter 
43. The outputs of mixers 40, 41 are converted to digital signals of 
complex values by an A/D converter 44 in response to a sampling pulse from 
a pulse generator 45. The digital complex signal from A/D converter 44 is 
applied to a M-th power frequency multiplier 46 where the frequency is 
raised to M times the input frequency and fed through a low-pass filter 
47. The 1/M phase divider 48 of the present invention takes its input from 
the low-pass filter 47, where the phase angle .theta. is divided by a 
factor M as described above so that the frequency of the signal from 
multiplier 46 is reduced to the baseband frequency. The output of A/D 
converter 44 is coupled through an appropriate delay circuit 49 to a 
complex multiplier 50 where it is multiplied with the output of phase 
divider 48 to synchronously detect the original digital signal. 
It is seen the present invention eliminates the need for xy-to-.theta. 
conversion table and cosine and sin tables which are required with the 
prior art phase dividers.