Noise control for printed circuit board

In accordance with at least one aspect of this disclosure, a system can include, a printed circuit board (PCB), a controller on the PCB configured to output a gate drive signal to one or more gate drivers 106 to drive a gate 108 of a switch (e.g., a transistor), and an isolation domain. The isolation domain can be defined in the PCB between the controller and the one or more gate drivers. More specifically, the isolation domain can begin at a first moat and end at a second moat, defined between the controller and the one or more gate drivers. The isolation domain can be configured to prevent common mode noise in the gate drive signal.

TECHNICAL FIELD

The present disclosure relates to noise control, and more particularly to noise control in printed circuit boards.

BACKGROUND

Typical switching power converters can have large high speed voltage and current transitions that generate significant levels of electromagnetic noise and interference. At the same time, the control circuits that perform the regulation and management of the converter are traditionally very low voltage that can be easily upset and interfered with. In order to keep the control functions operating the properly, system controllers are traditionally physically separated from the power switching portion of the converter on the board to prevent such interference.

However, this distance can cause problems for signal transfer between controllers and gate drivers because there is still the opportunity for noise to affect the signal when coupling onto gate control lines. There remains a need in the art for improved noise prevention in signals between the controller and gate driver without relying on physical placement of components on the board. This disclosure provides a solution for this need.

SUMMARY

In accordance with at least one aspect of this disclosure, a system includes, a printed circuit board (PCB), a controller on the PCB configured to output a gate drive signal to one or more gate drivers to drive a gate of a switch, and an isolation domain, including a first and second moat defined in the PCB, disposed between the controller and the one or more gate drivers, configured to prevent common mode or differential noise in the gate drive signal.

In embodiments, the controller can be disposed at a first location on the printed circuit board and the one or more gate drivers are disposed at a second location on the printed circuit board, the second location being remote from the first location. A power source can be disposed at the first location configured to provide a power signal to the isolation domain at the first moat.

The isolation domain can include a first isolation coupling at the first moat, configured to receive the gate drive signal from the controller and split the gate drive signal into a positive differential gate drive signal and a negative differential gate drive signal, forming a first differential pair, and receive the power signal from the power source and split the power signal into an isolated ground reference power signal and an isolated power signal, forming a second differential pair. In certain embodiments, the power source at the first location can be integrated with the first isolation coupling as an integrated circuit.

A first trace pair can be defined in the printed circuit board between the first moat and the second moat, configured to carry at least the differential gate drive signal from the controller to the gate driver, and a second trace pair can be defined in the printed circuit board between the first moat and the second moat, configured to carry at least the isolated ground reference power signal and the isolated power signals across the isolation domain.

In certain embodiments, the first and second trace pairs can include stacked traces. In embodiments, each of the positive differential gate drive signal, the negative differential gate drive signal, the isolated ground reference power signal, and the isolated power signal form the stacked traces. The isolated ground reference power signal can be at a bottom of the stacked trace, the negative differential gate drive signal can be atop the isolated ground reference power signal, the positive differential gate drive signal can be atop the negative differential gate drive signal, and the isolated power signal can be at a top of the stack.

A second isolation coupling can be included at the second moat, operatively connected to the first isolation coupling, across the isolation domain. The second isolation coupling can be configured to receive the first and second differential pairs, combine the first differential pair back into a single gate drive signal, and return the reference power signal to the first isolation coupling.

A switching domain can be included at the second location, the switching domain including the one or more gate drivers. One of the one or more gate drivers can be operatively connected to the second isolation coupling configured to receive the combined gate drive signal to drive the gate of the switch. A power source can be included at the second location configured to power the one of the one or more gate drivers locally.

In embodiments, the first isolation coupling can be physically closer on the printed circuit board to the first location than to the second location. In embodiments, the second isolation coupling can be physically closer on the printed circuit board to the second location than to the first location. In certain embodiments, the isolation domain is a floating isolation domain. In certain such embodiments, common mode noise is prevented from coupling between the switching domain and the controller.

In certain embodiments, a set of traces can be defined in the printed circuit board spanning the isolation domain, from a first isolation coupling at the first moat to a second isolation coupling at the second moat, the trace set carrying a gate drive signal from the controller the one or more gate drivers. The trace can include at least a four layer stacked trace such that the gate drive signal is sandwiched within the four layer stacked trace.

DETAILED DESCRIPTION

In accordance with at least one aspect of this disclosure, a system100can include, a printed circuit board (PCB)102, a low voltage controller104on the PCB102configured to output a gate drive signal105to one or more gate drivers106to drive a gate108of a switch110(e.g., a transistor), and an isolation domain112. The isolation domain112can be defined on the PCB102between the controller104and the one or more gate drivers106. More specifically, the isolation domain112can begin at a first moat114and end at a second moat116, defined between the controller104and the one or more gate drivers106. The isolation domain112can be configured to prevent common mode noise in the gate drive signal105. In embodiments, the isolation domain112can be floating.

In certain such embodiments, having all of the isolated circuits and paths floating together as a group, there can be no common mode coupling of any signal to any trace routed through the floating isolation domain112as there is no return path. This ensures that any noise from the gate drive (for example the high side driver that is riding up and down) does not couple back into the isolated lines and any noise that may try to be coupled onto those lines while they are in route cannot couple well to any of the isolated traces. Finally, the isolation back at the source ensures that there is still no return path for noise and no high voltage noise coupled back into the source control circuit and using that circuit as a return path resulting in a large noise loop.

As shown inFIG.1, in embodiments, the controller104can be disposed at a first location118on the printed circuit board102and the one or more gate drivers106can be disposed at a second location120on the printed circuit board102, where the second location120is remote from the first location118(e.g., the first and second locations118,120are physically distant from one another across the PCB102).

A power source122can be included at the first location118configured to provide a power signal123to the isolation domain112at the first moat114. The power signal can be any suitable voltage, such as 3.3V or 5V, for example, depending on part requirements. In embodiments, the isolation domain112can further include a first isolation coupling124at the first moat114, and powered by the power source122. In certain embodiments, the power source122at the first location118can be integrated with the first isolation coupling124, for example as an integrated circuit (e.g., as shown), however it is contemplated that the power source122at the first location118and the isolation coupling124may be discrete components.

The first isolation coupling124can be configured to receive the gate drive signal105from the controller104and split the gate drive signal105into a positive differential gate drive signal125aand a negative differential gate drive signal125b, forming a first differential pair126. The first isolation coupling124can also be configured to receive the power signal123from the power source122and split the power signal123into an isolated ground reference power signal127aand an isolated power signal127b, forming a second differential pair128.

A trace130(e.g., as schematically shown inFIG.1) is defined in the PCB102between the first moat114and the second moat116. The trace130can include a first stacked trace (e.g., pair126) configured to carry at least the gate drive signal105from the controller104to the gate driver106. The trace130can also include a second stacked trace (e.g., pair128) configured to carry at least the isolated ground reference power signal127aand the isolated power signal127bacross the isolation domain112. In embodiments, the trace130can span the isolation domain112(e.g., an entirety of the isolation domain112), from the first isolation coupling124at the first moat114to a second isolation coupling132at the second moat116. In certain embodiments, the trace130can include at least a four layer stacked trace (e.g., as a stackup131shown inFIG.2) such that the gate drive signal105(e.g., as the first differential pair126) is sandwiched within the four layer stackup131as shown inFIG.2. In embodiments, the stackup131as shown inFIG.2can be bound by a normal ground or power plane.

As shown, each of the positive differential gate drive signal125a, the negative differential gate drive signal125b, the isolated ground reference power signal127a, and the isolated power signal127bcan form the stacked trace130, such that that the isolated ground reference power signal127ais at a bottom of the stackup131, the negative differential gate drive signal125bis atop the isolated ground reference power signal127a, the positive differential gate drive signal125ais atop the negative differential gate drive signal125b, and the isolated power signal127bis at a top of the stack. In certain embodiments, such as shown inFIG.3, the stackup231can be similar to stack up131, however in stackup231, the signals125aand125bcan be positioned side-by-side between signals127aand127b, forming pair226. As shown in both stackups131,231, the power signal traces127a,127bcan be wider than the gate drive signal traces125a,125bto provide fringe protection.

The second isolation coupling132can be disposed at the second moat116, operatively connected to the first isolation coupling124across the isolation domain112(e.g., via the trace130). In embodiments, the second isolation coupling132can be configured to receive the first and second differential pairs126,128. The second isolation coupling132can be configured to combine the first differential pair126back into a single gate drive signal105and provide the gate drive signal105to the gate driver106, and can be powered by reference power signal.

A high voltage switching domain134can be disposed at the second location120, the switching domain134including the one or more gate drivers. The gate driver106is operatively connected to the second isolation coupling132being operative to receive the combined gate drive signal105to drive the gate108of the switch110. While one or more gate drivers can be included in the switching domain134, and driven by the main controller104and gate drive signal105, it should be understood that each gate driver106in the switching domain134includes its own isolation domain112and noise control system200,300,400,500. The second isolation coupling132cancels out any noised picked up in the gate drive signal105as pair126. This is because the differential trace pair126places signals125a,125bso close together that any voltage coupled to them will be common mode and differentially subtract out. This remains true even though there may be no significant common mode coupling current.

Another power source136(e.g., separate from power source122) can be disposed at the second location120configured to power the one or more gate drivers106locally and independent from the power source122at the first location118, such that common mode noise is prevented from coupling between the switching domain134and the controller104.

In embodiments, the first isolation coupling124can be physically closer on the PCB102to the first location118than to the second location120and the second isolation coupling132can be physically closer on the PCB102to the second location120than to the first location118. While shown relatively close together inFIG.1for clarity, it should be understood that the stacked trace130spanning the isolation domain112can be configured to traverse any distance and follow any suitable path along the PCB102between the controller104and the gate driver106as needed or desired for a given application. Moreover, in embodiments, it is possible to locate the first isolation coupling124in close proximity to the controller104, and the second isolation coupling132in close proximity to the one or more gate drivers106, without regard to the physical distance between the two isolation couplings124,132, or any intervening components therein.

In embodiments, the first moat114is at the same point on the PCB102where the power supply124and return for the main controller104ends, for example as shown inFIG.1. The supply for the main controller104, the return, and the first moat114all stack up exactly on top of each other so there is no parasitic capacitance bridging any moat114,116and the main controller104is powered only from power in it's own reference domain (e.g., by a local power source122) and only has signals routed from/to it in it's own reference domain. Additionally, in the switching domain134, at the second moat116should end at the exact location where the gate power supply136and it's return meet the area where the high voltage and return start and right under the middle of first isolation coupling124. Such an arrangement allows the gate driver106and the gate to all referenced to the source108of the transistor110.

In traditional systems, an isolated moat may be included, however, it may be located in an inconvenient location for the given application, which may require extensive routing of the trace across the PCB, which can make the signal more susceptible to picking up common and differential noise. Previously, in order to prevent switching noise from coupling back into the gate control signals and upsetting the converter operation, the signals could be placed between shielding signals with single isolation, however, this solution did not address the mechanical and electrical constraints on the converter, making such an approach difficult to implement, or in some cases, still result in some noise coupling onto the gate lines because the single ended signals were still crossing through noisy areas of the PCB through asymmetrical noise fields.

Embodiments as described herein provide an enhanced solution that addresses the noted constraints of the traditional systems. Embodiments includes two isolation couplings at individual isolation moats, to run the isolated signals differentially, and as a pair, over the two moats. The differential pairs of signals can include—in the stackup from bottom to top—an isolated signal that is referenced to ground, a negative gate drive signal, a positive gate drive signal, and an isolated ground signal, to form a stripline setup. In this way, the gate drive signals are shielded top and bottom, and any common mode noise will be cancelled out by the differential pairing of the signals. Additionally, in embodiments, the second isolation coupling can be very close (e.g., physically close) to the gate driver and the switch on the PCB.

Embodiments disclosed herein provide a system and method to better protect the gate drive control signals from picking up noise as the signals cross through the main power switching area of the converter. It should be understood that the return side of the gate drive control signals is every bit as critical for noise immunity as the gate drive signal itself. To further reduce noise pickup in the signals, embodiments utilize a double isolation coupling configuration with floating differential drive signals (e.g., as shown). By having the double split reference domains the signals and their reference at the controller never leave the area of the POS3R3V power and ground and equivalently any voltage noise the isolated lines see never leaves or enters the isolated area of the Gate/Source reference.

The isolated floating differential section (e.g., isolation domain112) can be used from the edge of the POS3R3V domain across and through the switching array where the signals are more susceptible to noise. For example, in certain application, the switching domain can be at a very high voltage, such as 270V or more, which can produce high dv/dt transients, leading to strong, high frequency fields and resulting in oscillations in the gate drive signals as they pass through the switching array. These oscillations then create even worse noise that lasts much longer and can couple through any capacitive path back to the controller and all over the module. But by floating the isolation domain and differentially pairing the signals (e.g., in embodiments described herein), there is nothing to create a noisy imbalance between the differential pair since the reference is floating at the same potential as the common mode voltage of the differential pair, and because the routing is arranged so that the four signals are stacked (e.g., in trace130). As described, the floating reference domain can be on the bottom range of the stackup, then the negative differential signal above that, then the positive differential signal above that, and finally with the floating POSV on top of the stack.

This makes a four layer stackup section that is set either to the top layers of the board or the bottom ones, but in either case completely separate vertically from the switching layers. By having the first isolation coupling also include a floating isolated power converter, then the floating isolation domain has no physical connection to either the controller side domain or the switching domain.

Finally, the differential receiver and isolation to the gate driver allows the transition to the switch source voltage level including the high side gate that is at a high voltage without coupling any of that voltage or noise back into the differential pair area. In embodiments, this can be done right at the entrance to a small floating switch source reference plane that is flowed with a copper pour area under the gate driver section.

With these two isolation couplings (e.g., couplings124,132) as described in place, there is no opportunity for noise to couple from the high voltage switching section back to the low voltage controller, even on the return side. Embodiments, therefore allow for more convenient routing without picking up the noise from the high power switching, and without having to tweak each component and location and route on the board to otherwise cancel or prevent such noise. Accordingly, embodiments allow for a much more complex board design with longer distances between the controller and switching sections surrounding the described system and its stacked trace.

Embodiments disclosed herein (e.g., as shown) can be suitable for a half bridge rectifier design, however, certain embodiments can be suitable a full bridge rectifier design, wherein additional isolation couplings and differential pairs, and gate drivers could be included for each side of each additional switch. For example, embodiments for a full bridge rectifier can include four gate drivers, and two isolation couplings for each side of each transistor, where each gate of each transistor includes its own isolation domain and noise control system200,300,400,500as shown. For example, as shown schematically inFIG.1, the novel noise control system indicated as block200, can be repeated throughout the board as needed for the given board and converter design, as shown by blocks300,400,500. Any suitable number of noise control system blocks,200,300,400,500and so on, and accompanying transistors may be included as needed or desired.

In certain applications, such as for use with a three phase AC motor, could include 12-16 gate drivers, and complimentary isolation couplings as described, as the number of switches increases. As more gate drivers and components are added, the board can become more complex, providing for more opportunity for noise, however, using the systems and methods as described herein, the gate drive signals even on the more complex boards should be immune to noise and signal oscillation, easing the design constraints while designing complex boards.

Embodiments can provide a complete barrier to any noise that would normally couple from the switching power section back to the low voltage controller. The double isolation of the described embodiments can be much better suited to be able to support much higher switching voltages and currents, while still controlling for noise in the system. Traditional single isolation systems may fail to block noise as the magnitudes of the voltages and currents increase and as a single isolation system results in one end of the other of the connecting traces between the controller and gate being referenced to either the gate return which may be riding on top of a high voltage square wave or to the controller end which is low voltage and sensitive to any capacitive pickup of noise along path to the controller, for example as present trends indicate aircraft power will require much higher voltages as the technology develops.

The embodiments of the present disclosure, as described above and shown in the drawings, provide for improvement in the art to which they pertain. While the apparatus and methods of the subject disclosure have been shown and described, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.