CONTROL CIRCUIT

A method, control circuit and printing system to control data communications with a plurality of integrated circuits. The method comprises receiving a control signal indicating that a first integrated circuit in the plurality of integrated circuits has been connected to an interface; pausing data communication between a processor and a second integrated circuit in the plurality of circuits over a data bus; and sending an enable signal to transition a switch from an open state to a closed state to connect a power supply to the interface while data communication with the plurality of integrated circuits over the data bus is paused.

BACKGROUND

Some printing systems utilize one or more removable consumable units, such as printing liquid or printing agent reservoirs for use in 2D and/or 3D printing systems, or build material reservoirs for use in 3D printing systems. A removable consumable unit may include an integrated circuit comprising an internal memory to store data associated with the removable consumable and its usage. This stored data may be readable by a printer to ensure that the consumable unit is used in an intended manner.

DESCRIPTION

FIG. 1is a schematic diagram showing an example of a printing system100comprising a printer110and a plurality consumable units150-N, where N is a numeral which refers to the particular consumable unit. Each consumable unit150-N comprises an integrated circuit152-N, which in turn comprises a memory device154-N for storing data associated with the respective consumable unit150-N. In some examples the data stored in the memory device154-N may be stored in an encrypted format and/or utilize a secure interface to prevent access to the data from unauthorized parties.

At least one of the plurality of consumable units150-N may be removably connectable to the printer110, to enable convenient replacement in the event that the consumable is exhausted or is desired to be changed. In the particular example shown inFIG. 1, a first consumable unit150-1is removably connectable to the printer110and is shown in an initially disconnected position, whereas a second consumable unit150-2and a third consumable unit150-3are shown in initially connected positions. The printer110is provided with a plurality of interfaces120-N which facilitate power and data connectivity between the printer110and the respective consumable units150-N. In further examples, the functionality provided by the interfaces120-N may be provided by a plurality of separate interfaces which respectively provide power and data connectivity between the printer110and the consumable units150-N.

The printer110comprises a processor112which communicates with the integrated circuits152-N of the consumable units150-N over a data bus114(shown as a double compound solid line inFIG. 1). For example, the processor112may communicate periodically with the plurality of integrated circuits152-N to store and update data relating to usage of the consumable units150-N in their respective memory devices154-N. In some examples, the data bus114may be a serial data bus which is implemented according to the I2C™ (Inter-Integrated Circuit) specification, as originally developed by Philips Semiconductors™ and presently maintained by NXP Semiconductors™. In this context, the processor112ofFIG. 1functions as a “master” device and each of the integrated circuits152-N function as “slave” devices.

The printer110comprises a power supply116which provides power to the first consumable unit150-1over a power line117-1(shown as a single compound solid line inFIG. 1) and interface120-1. The power supplied to the first consumable unit is used to power the respective integrated circuit152-1and memory device154-1, in addition to any other power consuming functionality provided by the first consumable unit150-1. According to some examples, the power supply may also provide power to the second consumable unit150-2and third consumable unit150-3(not shown inFIG. 1).

Control of the power supply to the first consumable unit150-1is provided by a control circuit118-1, shown schematically as a switch inFIG. 1, which is configured to control power supply to the first consumable unit150-1under the control of the processor112. In particular, the control circuit118-1is configured to operate the first consumable unit150-1according to two states: a “powered state” wherein the power supply is connected to the interface120-1(and thus the first consumable unit150-1), and an “isolated state” wherein the power supply is disconnected or isolated from the interface120-1(and thus the first consumable unit150-1). The processor112is configured to control the control circuit118-1to switch between the powered state and the isolated state by means of a control line119-1(shown as a single compound dashed line inFIG. 1) between the processor112and the control circuit118-1.

In some examples, the data bus114may be sensitive to noise induced by voltage changes in the power line117-1associated with the first consumable unit150-1. For example, voltage changes in the power line117-1may be caused by connection and disconnection of the first consumable unit150-1to its respective interface120-1. This induced noise on the data bus114has the potential to generate one or more spurious data values, which may in turn affect the correct operation of the integrated circuits152-2&152-3associated with the second and third consumable units150-2&150-3. For example, the one or more spurious data values induced on the data bus114may be detected by one or both of the integrated circuits152-2&152-3as a malicious attempt to circumvent the encryption employed to secure data stored in the respective memory devices154-2&154-3. As a result of this detection, the integrated circuits152-2&152-3may initiate one or more countermeasures to prevent unauthorized access, such as activating a locking mechanism to prevent further access to data stored in the respective memory devices154-2&154-3. In some cases, these countermeasures may prevent further use of the consumable units150-2&150-3, thereby causing inconvenience and additional expense for users of the printing system100.

In order to reduce the instances of spurious data values being induced on the data bus114, the processor112is configured to maintain the control circuit118-1associated with the first consumable unit150-1in the isolated state, such that the interface120-1is isolated from the power supply116upon connection or insertion of the first consumable unit150-1. Upon detection of insertion or connection of the first consumable unit150-1, the processor112pauses or stops data communication over the data bus114(i.e. data communication with the second and third integrated circuits152-2&152-3), before switching the control circuit to the “powered state” to provide power to the interface120-1and the first consumable unit150-1. After switching the control circuit118-1to the powered state, the processor112resumes data communication over the data bus (i.e. data communication with the first, second and third consumable units150-1to150-3). In this manner, incidents of spurious data values being induced on the data bus114due to insertion or connection of the first consumable unit150-1can be reduced or eliminated.

FIG. 2is a schematic diagram showing an example of the control circuit118-1for use in the printer110ofFIG. 1. In this example, the control circuit118-1comprises a switch122-1located between the power supply116and the power line117-1to the interface120-1associated with the first consumable unit150-1. The switch122-1comprises an open configuration in which the power supply116is disconnected from the interface120-1(i.e. providing the “isolated state” discussed above) and a closed configuration in which the power supply116is connected to the interface120-1(i.e. providing the “powered state” discussed above). The switch122-1may operate in the open configuration by default and transition to the closed state in response to an enable signal received on the control line119-1from the processor112. Thus, in the absence of the enable signal, the switch122-1remains in the open configuration and the interface120-1remains isolated from the power supply116.

In the particular example shown inFIG. 2, the switch122-1is a field effect transistor (FET), such as a p-channel metal-oxide-semiconductor field effect transistor (MOSFET), comprising a source terminal “s”, a drain terminal “d” and a gate terminal “g”. An example of a suitable MOSFET for use in the control circuit118-1is the IRLM5202 HEXFET™ Power MOSFET manufactured by International Rectifier™ of El Segundo, Calif., United States of America. In this example, the power supply116is be connected to the source terminal of the FET, the power line117-1to the interface120-1is connected to the drain terminal of the FET and the control line119-1from the processor is connected to the gate terminal of the FET. In further examples, the switch may be a bipolar junction transistor (BJT).

The control circuit118-1ofFIG. 2comprises a pull-up transistor122which is connected to the power line117-1to bias the voltage at the interface120-1to a first voltage Vswhen the switch122-1is in the open configuration (i.e. the power supply116is isolated from the interface120-1) and the integrated circuit152-1of the consumable unit150-1is disconnected from the interface120-1. For example, the first voltage Vsmay be set to 5V and asserted through a pull-up resistor123with a resistance of 1 MΩ.

The control circuit118-1further comprises a comparator124, such as a voltage comparator, to detect a voltage drop at the interface120-1from the first voltage Vsto a second voltage VREF, caused by connection of the first the consumable unit150to the interface120-1. This voltage drop is caused by the current drawn down by the integrated circuit152-1of the first consumable unit150-1, through the pull-up resistor123of the control circuit118-1. The voltage comparator124comprises a first input “a” connected to the powerline117-1(and thus indirectly to the interface120-1) and a second input “b” connected to a voltage source with voltage VREF. The second voltage VREFserves as a threshold voltage, indicative of the integrated circuit152-1of the first consumable unit150-1being connected to the interface120-1. In examples where the first voltage (i.e. the bias voltage) is set at 5 V, the second voltage (i.e. the reference voltage) may be set to approximately 3.5 V. An example of a suitable voltage comparator for use in the control circuit118-1is the LMC6762 Dual MicroPower Rail-To-Rail Input CMOS Comparator manufactured by Texas Instruments™ of Dallas, Tex., United States of America.

The voltage comparator124further includes an output “c” which is connected to the processor112as an input. In response to detecting a drop in voltage at the interface from the first voltage Vsto the second voltage VREF(or below), the voltage comparator124outputs a control signal to the processor112. The processor112interprets the control signal as an indicator that the first consumable unit150-1has been connected to the interface120-1of the printer110and proceeds to pause or stop data communication with any integrated circuits152-N which are connected to the data bus114(i.e. the integrated circuits152-2&152-3associated with the second and third consumable units150-2&150-3respectively). After pausing or stopping data communication, the processor112sends send an enable signal to the switch122on control line119-1to transition the switch122from the open state to the closed state, thereby connecting the power supply116to the interface120-1and the integrated circuit152-1associated with the first consumable unit150-1. In this respect, it will be noted that transition of the first consumable unit150-1from the isolated state to the powered state occurs while data communications over the data bus114are paused, thereby reducing the likelihood of spurious data values being induced on the data bus114during this connection process. In turn, this ensures that the integrated circuits152-2&152-3do not initiate countermeasures which may result in the locking or disabling of data stored in the associated memory devices154-2&154-3.

FIG. 3is a schematic diagram showing a further example of a control circuit118-1A for use in the printer110ofFIG. 1. In this example, the control circuit118-1A is substantively the same as that shown inFIG. 2and the same reference numerals have been used to denote common components. In this example, the interface120-1associated with the first consumable unit150-1is connected to ground through a capacitor126which functions as a decoupling capacitor to filter out relatively high frequency noise on the control circuit118. For example, the interface120-1may be connected to ground through a decoupling capacitor126with a capacitance in the range 1 to 110 nF. In one example a capacitance of approximately 10 nF may be chosen.

In further examples, the processor112may be configured to temporarily isolate (i.e. disconnect) the power supply116from the second consumable unit150-2and the third consumable unit150-3in response to detecting insertion of the first consumable unit150-1, in addition to pausing data communications on the data bus114.FIG. 4shown an example of a printer110A configured in this matter, including additional second and third control circuits118-2&118-3corresponding respectively to the second and third consumable units150-2&150-3. In this example, the second and third control circuits118-2&118-3are located between the power supply and power lines117-2&117-3to the respective interfaces120-2&120-3. The second and third control circuits118-2&118-3are controlled by the processor112via an enable signal transmitted over respective control lines119-2&119-3. In the configuration shown inFIG. 4, the first consumable unit150-1is disconnected from the printer110A, the first interface120-1is isolated from the power supply116by first control circuit118-1, and the second and third interfaces120-2&120-3are connected to the power supply by second and third control circuits118-2&118-3. In response to detecting insertion of the first consumable unit150-1(and thus the first integrated circuit152-1), the processor112pauses data communication on the data bus114and controls the second and third control circuits118-2&118-3to transition the second and third consumable units150-2&150-3to the isolated state. Once this transition has completed, the processor112controls the first, second and third control circuits118-1to118-3to transition each to the respective consumable units150-1to150-3to the powered state and resumes data communications on the data bus114. By isolating the second and third consumable units150-2&150-3from the power supply116in this manner, the processor112can further reduce the possibility that the second and third integrated circuits152-2&152-3respond to the insertion event by initiating countermeasures, such as locking their respective memory devices154-2&154-3.

FIG. 5is a flow chart showing an example of a method500performed by the processor112to control the plurality of integrated circuits152-N as shown inFIGS. 1 to 4. First, the processor112detects the control signal (e.g. received from the voltage comparator124) indicating that the integrated circuit152-1has been connected to the interface (S502). After receiving the control signal, the processor112pauses or stops data communications over the data bus114and/or isolates the power supply116from integrated circuits152-2and152-3(S504). Next, the processor112sends or asserts an enable signal to the control circuit118-1,118-1A to transition the first consumable unit150-1from the isolated state to the connected state by connecting the power supply116to the interface120-1and the first integrated circuit152-1(S506). After the first consumable unit150-1has transitioned to the connected state, the processor112resumes or restarts data communications over the data bus114with each of the connected integrated circuits152-N and reconnects the power supply116to integrated circuits152-2and152-3(S508).

In some examples, one of more of the integrated circuits152-N may be an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Further one of more of the memory devices154-N associated with the integrated circuits152-N may comprise volatile memory, non-volatile memory or a combination of both. For example, at least one of the memory devices154-N may comprise solid state flash memory for storage of data associated with the consumable unit.

In the examples described above with reference toFIGS. 1 to 5, the second consumable unit150-2and the third consumable unit150-3are shown as connected to the printer110. However, it will be appreciated that the second consumable unit150-2and/or third consumable unit150-3may also be removably connectable to the printer110in the same manner as the first consumable unit150-1. Indeed, the printer system100may comprise any number of consumable units150-N, one or more of which may be removal connectable to the printer110. In this respect, a separate control circuit118-N and interface120-N may be provided for each removably connectable consumable unit150-N, such that the processor can detect insertion or connection for each interface120-N and control data communications to the associated integrated circuits in the manner described above with reference toFIG. 4.

In further examples, the interface120-1associated with the first consumable unit may be located remote from the printer110and connected to the printer110by a cable or other appropriate means to provide power and data communications to the interface120. Such arrangement may, for example, be employed where the associated consumable unit150-1is particularly bulky, as may be the case with a 3D printing system.

In some examples, the data stored in the memory device154-N associated with each integrated circuit152-N may include usage data, identification data, calibration data, printing parameters, manufacturing information, servicing information, and other information pertinent to the associated consumable unit. In some examples, the data may be encrypted by the processor112prior to storage on the memory devices154using, for example, a symmetric encryption algorithm.

In some examples, the consumable unit may comprise a reservoir to store printing liquid or printing agent for 2D or 3D printing systems. In other examples, the consumable unit may comprises build material (e.g. a powder, paste, slurry or liquid material) for using in a 3D printing system.

Further, it will be appreciated that in some examples one or more of the integrated circuits152-N need not be associated with a consumable unit. For example, one of more of the integrated circuits152-N may be embedded in the printer110itself, or an external peripheral device which is removably connectable to the printer110.

Certain system components and methods described herein may be implemented by way of computer program code that is storable on a non-transitory storage medium. The computer program code may be implemented by a control system comprising at least one processor that is arranged to retrieve data from a computer-readable storage medium. The control system may comprise part of an object production system such as an additive manufacturing system. The computer-readable storage medium may comprise a set of computer-readable instructions stored thereon. The at least one processor may be configured to load the instructions into memory for processing. The instructions are arranged to cause the at least one processor to perform a series of actions. The instructions may instruct the method300ofFIG. 3and/or any other of the methods or processes described hereinbefore. The non-transitory storage medium can be any media that can contain, store, or maintain programs and data for use by or in connection with an instruction execution system. Machine-readable media can comprise any one of many physical media such as, for example, electronic, magnetic, optical, electromagnetic, or semiconductor media. More specific examples of suitable machine-readable media include, but are not limited to, a hard drive, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory, or a portable disc. The preceding description has been presented to illustrate and describe examples of the principles described.

This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.