Method of making high coupling ratio NAND type flash memory

A new method of fabricating a high coupling ratio Flash EEPROM memory cell is described. A layer of silicon dioxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. The silicon dioxide layer not covered by the patterned silicon nitride layer and the silicon nitride spacers is removed thereby exposing portions of the semiconductor substrate as tunneling windows. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer which is patterned to form a control gate. Passivation and metallization complete the fabrication of the NAND type memory cell with improved coupling ratio.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The invention relates to a method of fabricating semiconductor memory 
devices employing floating gates, and more particularly, to a method of 
fabricating NAND type memory devices employing floating gates having 
improved coupling ratio. 
2. Description of the Prior Art 
One class of semiconductor memory devices employ floating gates; that is, 
gates which are completely surrounded by an insulating layer, such as a 
silicon oxide. The presence or absence of charge in the floating gates 
represents binary information. These are called electrically programmable 
read only memories (EPROM). EEPROMs are erasable electrically programmable 
read only memories. "Flash" memory devices are those in which all of the 
cells can be erased in a single operation. As noted in the paper, "A 4-Mb 
NAND EEPROM with Tight Programmed V.sub.t Distribution," by M. Momodomi et 
al, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 
492-496, flash EEPROMs are NOR-structured cells in which memory cells are 
connected to a bit line in a parallel manner. A NAND-structured cell in 
which memory cells are arranged in series dramatically reduces the number 
of cell components as well as the cell size. 
The two papers, "Technology Trend of Flash-EEPROM-Can Flash-EEPROM overcome 
DRAM?," by Fujio Masuoka, 1992 Symposium on VLSI Technology Digest of 
Technical Papers, pp. 6-9 and "A 1.13 um.sup.2 Memory Cell Technology for 
Reliable 3.3 V 64M NAND EEPROMs," by S. Aritome et al, Extended Abstracts 
of the 1993 International Conference on Solid State Devices and Materials, 
pp. 446-448 discuss the future of NAND type EEPROMs. The coupling ratio of 
the NAND type EEPROM is limited, so the floating gate must overlap the 
field oxide area to improve the coupling ratio or the cell size must be 
increased or a higher program voltage used. 
A number of workers in the art have described improved designs for NAND 
type EEPROMs. U.S. Pat. No. 5,094,971 to Kanebako teaches miniaturizing 
NAND type ROMs by self-aligned ion implantation. U.S. Pat. No. 5,273,923 
to Chang et al teaches forming a tunneling window which overlaps both the 
active region and the field isolation region of the memory circuit. U.S. 
Pat. No. 4,945,068 to Sugaya teaches forming the thin tunnel oxide and the 
thick gate oxide in a single oxidation step using implanted nitrogen ions 
to slow the oxidation in the planned tunnel oxide region. U.S. Pat. No. 
5,284,786 to Sethi teaches another method of forming a tunnel window. 
SUMMARY OF THE INVENTION 
A principal object of the present invention is to provide an effective and 
very manufacturable method of fabricating a NAND type flash EEPROM memory 
cell. 
Another object of the present invention is to provide an effective and very 
manufacturable method of fabricating a high coupling ratio NAND type flash 
EEPROM memory cell. 
In accordance with the objects of this invention a new method of 
fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A 
layer of silicon dioxide is grown over the surface of a semiconductor 
substrate. A layer of silicon nitride is deposited over the silicon 
dioxide layer and patterned. Silicon nitride spacers are formed on the 
sidewalls of the patterned silicon nitride layer. The silicon dioxide 
layer not covered by the patterned silicon nitride layer and the silicon 
nitride spacers is removed thereby exposing portions of the semiconductor 
substrate as tunneling windows. A tunnel oxide layer is grown on the 
exposed portions of the semiconductor substrate. The silicon nitride layer 
and spacers are removed. A first polysilicon layer is deposited over the 
surface of the silicon dioxide and tunnel oxide layers and patterned to 
form a floating gate. An interpoly dielectric layer is deposited over the 
patterned first polysilicon layer followed by a second polysilicon layer 
which is patterned to form a control gate. Passivation and metallization 
complete the fabrication of the NAND type memory cell with improved 
coupling ratio.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now more particularly to FIG. 1, the process of the present 
invention will be described. A portion of a partially completed NAND type 
EEPROM is illustrated in FIG. 1 consisting of a semiconductor substrate 
10, preferably composed of monocrystalline silicon. 
A layer of silicon dioxide 14 is grown over the surfaces of the 
semiconductor substrate to a thickness of between about 200 to 400 
Angstroms. A layer of silicon nitride 16 is deposited over the silicon 
dioxide layer to a thickness of between about 1000 to 2000 Angstroms and 
is patterned to provide openings to the underlying silicon dioxide layer 
14. 
Referring now to FIG. 2, a second layer of silicon nitride is deposited 
over the surfaces of the substrate and anisotropically etched away leaving 
silicon nitride spacers 18 on the sidewalls of the patterned silicon 
nitride layer 16. The spacers are between about 500 to 3000 Angstroms in 
width. The portions of the silicon dioxide layer not covered by the 
silicon nitride layer 16 and spacers 18 are removed, exposing portions of 
the silicon substrate as tunneling windows. 
Two preferred embodiments of the present invention are illustrated here. 
The top plan view of the NAND cell after the spacers has been formed and 
portions of the silicon dioxide have been removed in the first embodiment 
is shown in FIG. 3. Here, the tunneling window to be formed is a strip, 
with an elongated shape in which two opposing sides are relatively longer 
than the other two opposing sides. In the second embodiment, shown in top 
plan view in FIG. 4, a window with a shape having approximately equal 
sides rather than an elongated strip is to be formed. The coupling ratio 
in the second embodiment will be higher than in the first embodiment. The 
cross section in FIG. 2 is the same for both embodiments. View 5--5 of the 
second embodiment of FIG. 4 is illustrated in FIG. 5. The opening 19, 
having four approximately equal sides, is shown in FIG. 5. In the first 
embodiment, this cross-section would show an elongated strip rather than 
smaller opening 19. 
Referring again to FIG. 2, the thin tunneling oxide 20 is grown on the 
exposed portions of the silicon substrate to a thickness of between about 
60 to 100 Angstroms, and preferably about 90 Angstroms. 
Referring now to FIG. 6, the silicon nitride layer 16 and spacers 18 are 
removed, typically by hot phosphoric acid. The thin tunneling oxide may be 
grown after the silicon nitride is removed, rather than before it is 
removed. In fact, it is best if the tunneling oxide is grown after removal 
of the silicon nitride. 
A layer of polysilicon 22 is deposited over the surface of the substrate to 
a thickness of between about 1000 to 3000 Angstroms and doped. An 
interpoly dielectric 24, such as ONO (silicon oxide-silicon 
nitride-silicon oxide) is deposited over the polysilicon layer 22. A 
second polysilicon layer 26 is deposited over the dielectric 24 to a 
thickness of between about 2000 to 5000 Angstroms and doped. The first and 
second polysilicon and ONO layers are etched to form the floating gates 22 
and control gates 26 of the memory cell, as illustrated in FIG. 7. 
Alternatively, the control gate could be formed of a polycide layer. 
Arsenic ions are implanted with a dosage of between about 2 E 15 to 8 E 15 
atoms/cm.sup.2 at a energy of between about 40 to 100 KeV to form N+ 
source and drain regions 28. 
FIG. 8 illustrates a top plan view of FIG. 7 showing the elongated strip 
tunneling window 20 under the floating gate 22. This tunneling window 
could be, for example, about 0.15 by 0.6 microns in size. FIG. 9 
illustrates a top plan view of FIG. 7 showing the tunneling window 20 
under the floating gate 22, as in the second embodiment. This tunneling 
window may be, for example, about 0.15 by 0.15 microns in size, depending 
upon the active width of the memory cell. The coupling ratio of the second 
embodiment may be as much as four times as high as the coupling ratio of 
the first embodiment. 
FIG. 10 illustrates a completed integrated circuit of the present invention 
in which passivation layer 30 has been blanket deposited over the gates. A 
contact opening has been made through the passivation layer 30 to the 
source/drain region 28. Metallization 32 completes the contact to N+ 
region 28. 
FIG. 11 is a circuit diagram of the completed NAND-type Flash EEPROM memory 
cell, showing word lines 44 and bit line 46. Cell 48 is selected, or on. 
The advantage of the present invention is an improved coupling ratio 
afforded by the small window for the tunneling oxide and thicker oxide 
used in other areas. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.