SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD THEREOF

Provided is a solid-state imaging element capable of reducing random noise in a pixel and suppressing crosstalk between adjacent pixels. A solid-state imaging element according to the present disclosure includes: a substrate; a plurality of photoelectric conversion units that is provided in the substrate; a first insulation film that is provided between the plurality of photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units, and has a fixed charge provided on an inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface; a second insulation film that is provided on an inner side of the first insulation film in the trench; at least one transistor that is provided on the first surface of the substrate; and a third insulation film that is provided on both sides of the trench or along the trench when viewed from the first surface.

TECHNICAL FIELD

The present disclosure relates to a solid-state imaging element and a manufacturing method thereof.

BACKGROUND ART

In a solid-state imaging element, a plurality of adjacent pixels may be physically isolated by a through trench. A fixed charge film is formed on a sidewall of such a through trench, and the fixed charge film induces a charge accumulation region around the sidewall of the through trench.

However, when the charge accumulation region comes into contact with a source diffusion layer or drain diffusion layer of a transistor of the pixel, a high-concentration PN junction is formed, and the PN junction generates a strong electric field. This strong electric field generates a dark current and causes random noise.

Furthermore, in a case where the through trench is formed before the formation of a pixel transistor, a material for filling the through trench needs to be a heat-resistant material that can withstand high-temperature processing in a step of forming the pixel transistor. For this reason, a metal material having low heat resistance cannot be used, and it is necessary to use polysilicon, a silicon nitride film, a silicon oxide film, or the like, which has high heat resistance. However, since the polysilicon, the silicon nitride film, the silicon oxide film, and the like have low light shielding properties, light leaks between adjacent pixels and crosstalk is caused.

CITATION LIST

Patent Document

Patent Document 1: WO 2019/093150 A

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

Provided is a solid-state imaging element capable of reducing random noise in a pixel and suppressing leakage of light between adjacent pixels.

Solutions to Problems

According to an aspect of the present disclosure, there is a solid-state imaging element including: a substrate; a plurality of photoelectric conversion units that is provided in the substrate; a first insulation film that is provided between the plurality of photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units, and has a fixed charge provided on an inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface; a second insulation film that is provided on an inner side of the first insulation film in the trench; at least one transistor that is provided on the first surface of the substrate; and a third insulation film that is provided on both sides of the trench or along the trench when viewed from the first surface.

The third insulation film is interposed between a charge induction layer formed on a surface of the substrate adjacent to the first charge film and a source or drain of the transistor.

The charge induction layer is a high-concentration charge layer of a first conductivity type, and the source or drain of the transistor is a high-concentration impurity diffusion layer of a second conductivity type.

The charge induction layer is an impurity diffusion layer of a first conductivity type.

The third insulation film covers ends of the first and second insulation films on the first surface side.

The ends of the first and second insulation films on the first surface side penetrate the third insulation film.

There are further provided: a wiring layer that is provided on the first surface of the substrate and electrically connected to the transistor; and a lens that is provided on the second surface of the substrate.

There is further provided a light shielding film that is provided on an inner side of the second insulation film in the trench.

The third insulation film overlaps the first and second insulation films when the substrate is viewed from a direction perpendicular to the first surface.

A width of the third insulation film is greater than a width of the trench when the substrate is viewed from a direction substantially perpendicular to the first surface.

A width of the third insulation film is greater than a width of the charge induction layer provided on both sides of the trench when the substrate is viewed from a direction substantially perpendicular to the first surface.

A depth of the third insulation film from the first surface is deeper than a depth of a diffusion layer of the transistor adjacent to the third insulation film.

According to another aspect of the present disclosure, there is provided a manufacturing method of a solid-state imaging element, the method including: forming a plurality of photoelectric conversion units in a substrate; forming, on a first surface of the substrate, a third insulation film between the photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units; forming, between the plurality of adjacent photoelectric conversion units, a trench penetrating between the first surface of the substrate and a second surface opposite to the first surface; forming, on an inner wall of the trench, a first insulation film having a fixed charge; forming, in the trench, a second insulation film on an inner side of the first insulation film; and forming at least one transistor on the first surface of the substrate.

The method further includes introducing an impurity of a first conductivity type into the inner wall of the trench to form a charge induction layer on the inner wall of the trench.

The trench penetrates the third insulation film.

According to still another aspect of the present disclosure, there is a solid-state imaging element including: a substrate; a plurality of photoelectric conversion units that is provided in the substrate; a second insulation film that is provided between the plurality of photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units and provided in a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface; a third insulation film that is provided on the first surface of the substrate and provided on both sides of the trench or along the trench when viewed from the first surface, the third insulation film being wider than the second insulation film; and an impurity diffusion layer that is provided on the first surface of the substrate and in contact with a side surface of the third insulation film, in which the second insulation film is not exposed from the side surface of the third insulation film.

An interface between the second insulation film and the third insulation film is in the third insulation film.

An interface between the second insulation film and the third insulation film is in the trench.

The second insulation film is a stacked film including a plurality of partial films.

The plurality of partial films is any of a fixed charge film, a low refractive index film, an oxide film, and a metal film.

There is a cavity in the second insulation film.

The solid-state imaging element further includes: a wiring layer that is provided on the first surface of the substrate and electrically connected to the impurity diffusion layer; and a lens that is provided on the second surface of the substrate.

According to still another aspect of the present disclosure, there is a manufacturing method of a solid-state imaging element, the method including: forming a plurality of photoelectric conversion units in a substrate; forming, between the photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units, a trench extending from a first surface of the substrate to a second surface opposite to the first surface; forming a sacrificial film in the trench; forming a third insulation film on the first surface of the substrate, the third insulation film being wider than the trench on both sides of the trench or along the trench when viewed from the first surface; removing the sacrificial film in the trench from the second surface side of the substrate; and forming a second insulation film in the trench from the second surface side of the substrate.

The method further includes removing an upper portion of the third insulation film such that the trench does not extend to a side surface of the third insulation film when the sacrificial film is removed, in which the second insulation film is formed so as not to be exposed from the side surface of the third insulation film when the second insulation film is formed.

The method further includes: partially removing the sacrificial film from the first surface side of the substrate to lower an upper surface of the sacrificial film below the first surface after the sacrificial film is formed; lowering the upper surface of the sacrificial film into the trench below a bottom surface of the third insulation film when the third insulation film is formed; and removing the sacrificial film from the second surface side of the substrate to form a second insulation film from a second surface side of the substrate into the trench.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the ratio of each portion are not necessarily the same as actual ones. In the specification and the drawings, the elements similar to those described above with respect to the previously described drawings are denoted by the same reference numerals, and the detailed description thereof will be appropriately omitted.

First Embodiment

FIG.1is a block diagram illustrating a configuration example of an imaging apparatus which is an example of an electronic apparatus of the present disclosure. As illustrated inFIG.1, an imaging apparatus10includes an optical system including a lens group11, an imaging element12, a DSP circuit13which is a camera signal processing unit, a frame memory14, a display unit15, a recording unit16, an operation system17, and a power supply system18. The DSP circuit13, the frame memory14, the display unit15, the recording unit16, the operation system17, and the power supply system18are connected to each other via a bus line19. A CPU20controls each unit in the imaging apparatus10.

The lens group11receives incident light (image light) from a subject and forms an image on an imaging surface of the imaging element12. The imaging element12converts the light amount of the incident light captured on the imaging surface by the lens group11into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. As the imaging element12, an imaging element (image sensor) including pixels to be described below can be used.

An example of the display unit15includes a panel-type display unit such as a liquid crystal display unit or an organic electro luminescence (EL) display unit, and the display unit15displays a moving image or a still image, which is captured by the imaging element12. The recording unit16records the moving image or the still image, which is captured by the imaging element12, on a recording medium such as a hard disk drive (HDD) or a solid state drive (SSD).

The operation system17issues operation commands for various functions of the imaging apparatus through the user's operation. The power supply system18appropriately supplies various power sources serving as operational power sources for the DSP circuit13, the frame memory14, the display unit15, the recording unit16, and the operation system17to these supply targets.

FIG.2is a block diagram illustrating a configuration example of the imaging element12. Here, the imaging element12may be a complementary metal oxide semiconductor (CMOS) image sensor which images a subject to obtain a captured image as an electrical signal. The imaging element12includes a pixel array unit41, a vertical drive unit42, a column processing unit43, a horizontal drive unit44, and a system control unit45. The pixel array unit41, the vertical drive unit42, the column processing unit43, the horizontal drive unit44, and the system control unit45are formed on a semiconductor substrate (chip) (not illustrated).

In the pixel array unit41, unit pixels each having a photoelectric conversion element that generates a photoelectric charge having a charge amount according to an incident light amount and accumulates the photoelectric charge therein are two-dimensionally arranged in a matrix form. Note that, in the following description, the photoelectric charge having a charge amount according to an incident light amount may be simply described as “charge”, and a unit pixel may be simply described as “pixel”.

In the pixel array unit41, a pixel drive line46is further formed for each row in a horizontal direction (array direction of the pixels in a pixel row) in the drawing with respect to the pixel array in the matrix form, and a vertical signal line VSL as a first signal line is formed for each column in a vertical direction (array direction of the pixels in the pixel column) in the drawing. One end of the pixel drive line46is connected to an output terminal corresponding to each row of the vertical drive unit42.

The imaging element12further includes a signal processing unit48and a data storage unit49. The signal processing unit48and the data storage unit49may be an external signal processing unit provided on a substrate separate from the imaging element12, for example, a digital signal processor (DSP) or processing with software, or may be mounted on the same substrate as that of the imaging element12.

The vertical drive unit42includes a shift register and an address decoder, and is a pixel drive unit that drives pixels of the pixel array unit41at the same time for all pixels or in units of rows. Although a specific configuration of the vertical drive unit42is not illustrated, the vertical drive unit42includes a read scanning system and a sweep scanning system, or performs batch sweeping and batch transfer.

In order to read a pixel signal from the unit pixel, the read scanning system sequentially selectively scans the unit pixels of the pixel array unit41row by row. In the case of row driving (rolling shutter operation), with respect to the sweeping, the sweep scanning is performed on a row on which read scanning is performed by the read scanning system earlier than the read scanning by a time corresponding to a shutter speed. Furthermore, in the case of global exposure (global shutter operation), the batch sweeping is performed earlier than the batch transfer by a time corresponding to the shutter speed.

When this sweeping is performed, unnecessary charges are swept (reset) from the photoelectric conversion elements of the unit pixels in the read row. When the unnecessary charges are swept (reset), a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of sweeping the photoelectric charge of the photoelectric conversion element and newly starting exposure (starting accumulation of the photoelectric charge).

The signal read by the read operation of the read scanning system corresponds to the amount of light incident after the immediately preceding read operation or electronic shutter operation. In the case of the row driving, a period from the read timing of the immediately preceding read operation or the sweep timing of the electronic shutter operation to the read timing of the current read operation is an accumulation period (exposure period) of the photoelectric charge in the unit pixel. In the case of the global exposure, a period from the batch sweeping to the batch transfer is an accumulation period (exposure period).

The pixel signal output from each unit pixel of the pixel row selectively scanned by the vertical drive unit42is supplied to the column processing unit43through each of the vertical signal lines VSL. The column processing unit43performs predetermined signal processing on the pixel signal output from each unit pixel of the selected row through the vertical signal line VSL for each pixel column of the pixel array unit41, and temporarily holds the pixel signal after the signal processing.

Specifically, the column processing unit43or the signal processing unit48performs at least noise removal processing, for example, correlated double sampling (CDS) processing as signal processing. When the correlated double sampling is performed by the column processing unit43, fixed pattern noise unique to the pixel, such as reset noise and threshold variation of the amplification transistor, is removed. Note that the column processing unit43can have, for example, an analog-digital (AD) conversion function in addition to the noise removal processing, and can output a signal level as a digital signal.

The horizontal drive unit44includes a shift register and an address decoder, and sequentially selects unit circuits corresponding to pixel columns of the column processing unit43. When the selective scanning is performed by the horizontal drive unit44, the pixel signals subjected to the signal processing by the column processing unit43are sequentially output to the signal processing unit48.

The system control unit45includes a timing generator that generates various timing signals, and performs drive control for the vertical drive unit42, the column processing unit43, the horizontal drive unit44, and the like on the basis of the various timing signals generated by the timing generator.

The signal processing unit48has at least an addition processing function, and performs various signal processing such as addition processing on the pixel signal output from the column processing unit43. The data storage unit49temporarily stores data necessary for signal processing when the signal processing is performed by the signal processing unit48.

FIG.3is a plan view illustrating a configuration example of one pixel100among a plurality of pixels constituting the pixel array unit41.FIG.4is an equivalent circuit diagram illustrating a configuration example of the pixel100. The pixel array unit41includes, for example, a plurality of the pixels100arranged in a two-dimensional array form. Each of the pixels100photoelectrically converts incident light and outputs a pixel signal of a captured image.

The pixel100includes a photodiode (PD)219, a transfer transistor (TG)112, a reset transistor (RST)113, an amplification transistor (AMP)114, and a selection transistor (SEL)115. Note that, in a region other than the transistor and the photodiode219, for example, an element isolation region is provided to be electrically isolated from other pixels. The element isolation region includes an insulation film. In the case of electronic reading, the element isolation region may be formed by a p-type region. The transistors112to115may be n-type transistors or p-type transistors. Here, the transistors112to115will be described as an n-type transistor.

The photodiode219photoelectrically converts received light into a charge (here, an electron) corresponding to the received light amount, and accumulates the charge. An anode of the photodiode219is connected to a ground of the pixel region, and a cathode is connected to a floating diffusion FD as a floating diffusion region via the transfer transistor112. Note that the cathode of the photodiode219may be connected to a power supply (pixel power supply) of the pixel region, and the anode may be connected to the floating diffusion FD via the transfer transistor112. In this case, the pixel100reads the charge as a hole.

The transfer transistor112controls reading for the photoelectric charge from the photodiode219. A source as one end of the transfer transistor112is connected to the cathode of the photodiode219. A drain as the other end of the transfer transistor112is connected to the floating diffusion FD. Furthermore, a transfer control signal is supplied to a gate of the transfer transistor112. The reading for the charge from the photodiode219is controlled with this transfer control signal. For example, in a case where the transfer control signal (that is, the gate potential of the transfer transistor112) is at a low level, the transfer transistor112is turned off (in a non-conductive state), and no charge is transferred from the photodiode219. In a case where the transfer control signal (that is, the gate potential of the transfer transistor112) is at a high level, the transfer transistor112is turned on (in a conductive state), and transfers the charge accumulated in the photodiode219to the floating diffusion FD. The floating diffusion FD is a diffusion layer capable of temporarily accumulating the charge, and is provided in a surface region of the semiconductor substrate218.

The reset transistor113resets the charge in the pixel100. The reset operation is, for example, an operation of expelling the charges (for example, electrons) of the photodiode219and floating diffusion FD to a power supply VDD, or an operation of expelling holes to the ground. A drain of the reset transistor113is connected to the power supply VDD, and a source of the reset transistor113is connected to the floating diffusion FD and is connected to a drain of the transfer transistor112via the floating diffusion FD. That is, the reset transistor113is connected between the drain of the transfer transistor112and the power supply VDD. Furthermore, a reset control signal is supplied to a gate of the reset transistor113. The resetting of the charge in the pixel100is controlled with this reset control signal. For example, in a case where the reset control signal (that is, the gate potential of the reset transistor113) is at a low level, the reset transistor113is turned off and the resetting is not performed. In a case where the reset control signal (that is, the gate potential of the reset transistor113) is at a high level, the reset transistor113is turned on, expels the charge in the pixel100to the power supply VDD, and resets the floating diffusion FD and the photodiode219.

The amplification transistor114is in a conductive state according to the voltage of the floating diffusion FD. The amplification transistor114amplifies voltage change in the floating diffusion FD and outputs the voltage change as an electrical signal (analog signal) to the vertical signal line VSL via the selection transistor115. That is, the amplification transistor114functions as a read circuit that reads the voltage of the floating diffusion FD. A gate of the amplification transistor114is connected to the floating diffusion FD. A drain of the amplification transistor114is connected to a source-follower power supply voltage (VDD), and a source of the amplification transistor114is connected to a drain of the selection transistor115. That is, the amplification transistor114is connected between the power supply (VDD) and the vertical signal line VSL. For example, the amplification transistor114outputs, to the selection transistor115, a voltage at a reset level (P-phase) corresponding to the potential of the floating diffusion FD in the reset state. Furthermore, the amplification transistor114outputs, to the selection transistor115, a voltage at a data level (D-phase) corresponding to the potential of the floating diffusion FD in which the signal charge from the photodiode219is accumulated.

The selection transistor115controls output of the electrical signal from the amplification transistor114to the vertical signal line VSL. A gate of the selection transistor115is connected to the pixel drive line46inFIG.2, and receives a selection control signal. The drain of the selection transistor115is connected to a source of the amplification transistor114, and a source of the selection transistor115is connected to the vertical signal line VSL as the first signal line. That is, the selection transistor115is connected between the amplification transistor114and the vertical signal line VSL. The amplification transistor114and the selection transistor115are connected in series between the power supply VDD and the vertical signal line VSL. Furthermore, the selection transistor115controls the output of the electrical signal from the amplification transistor114to the vertical signal line VSL on the basis of the selection control signal. For example, in a case where the pixel100is not selected, the selection control signal (that is, the gate potential of the selection transistor115) is at a low level. In this case, the selection transistor115is turned off, and does not output the electrical signal at the reset level or at the data level from the amplification transistor114to the vertical signal line VSL. In a case where the pixel100is selected, the selection control signal (that is, the gate potential of the selection transistor115) is at a high level. In this case, the selection transistor115is turned on, electrically connects the amplification transistor114to the vertical signal line VSL, and outputs the electrical signal corresponding to the voltage of the floating diffusion FD to the vertical signal line VSL. The vertical signal line VSL is connected to an A/D conversion circuit outside the pixel100, and transfers the electrical signal to the A/D conversion circuit. The A/D conversion circuit performs AD conversion on the electrical signal at the reset level and the electrical signal at the data level. The column processing unit43or the signal processing unit performs CDS processing on the electrical signal converted into the digital signal.

As described above, each pixel100can output, to the vertical signal line VSL, the electrical signal corresponding to incident light.

Next, the structure of the pixel100will be described.

FIG.5is a cross-sectional view illustrating a configuration example of the pixel100according to the present embodiment.FIG.6is a plan view illustrating an example of a layout of the pixels100as viewed from a second surface F2.FIG.5corresponds to a cross section taken along line A-A ofFIG.6.

As illustrated inFIG.5, the pixel100includes a semiconductor substrate218, a photodiode (PD)219, a charge induction layer220, a fixed charge film232, a pixel isolation film233, an element isolation film234, a light shielding film214, a planarization film213, a color filter212, an on-chip lens (OCL)211, a transistor250, a wiring261, and an interlayer insulation film262. Note that the pixel100may not include the color filter212and the on-chip lens (OCL)211.

The semiconductor substrate218is, for example, a silicon substrate. The semiconductor substrate218has a first surface F1and a second surface F2opposite to the first surface F1. The semiconductor substrate218is provided with, for example, the photodiode219including an n-type semiconductor region and a p-type semiconductor region. The photodiode219is a photoelectric conversion unit that converts incident light having passed through the on-chip lens211or the like on the second surface F2into a charge (for example, an electron). The photodiode219also functions as a charge accumulation region that accumulates photoelectrically converted charge in the n-type semiconductor region. The photodiode219is isolated for each pixel100by using the fixed charge film232and the pixel isolation film233, and performs photoelectric conversion for each pixel100. The photodiode219includes the p-type semiconductor region on the second surface F2side of the semiconductor substrate218.

As illustrated inFIG.6, the fixed charge film232and the pixel isolation film233are interposed between a plurality of adjacent pixels100and are provided in a lattice shape when viewed from a direction (Z direction) substantially perpendicular to the first surface F1or the second surface F2. The fixed charge film232and the pixel isolation film233are provided between a plurality of photoelectric conversion units adjacent to each other. The fixed charge film232and the pixel isolation film233partition the photodiode219for each pixel100, and electrically and optically isolate the photodiode219of each pixel100. Note that the pixel array unit41inFIG.2is configured by repeatedly arranging the pixels100inFIG.6in four directions.

The fixed charge film232as a first insulation film is provided in a trench TR penetrating between the first surface F1and second surface of the semiconductor substrate218, and covers the inner wall of the trench TR. The trench TR are provided between a plurality of adjacent pixels100and partitions the pixel100in a lattice shape when viewed in a direction substantially perpendicular to the first surface F1or the second surface F2(refer toFIG.6). Accordingly, the fixed charge film232is provided along the trench TR, and is provided between the adjacent pixels100similarly to the trench TR.

The fixed charge film232is an insulation film having a fixed charge, and has, for example, a negative charge. As the fixed charge film232, a material, which is deposited on the semiconductor substrate218and capable of generating the fixed charge and enhancing pinning, is preferable. Since the fixed charge film232is provided on the inner wall of the trench TR, the charge (for example, positive charge) is induced in the charge induction layer220on the surface of the semiconductor substrate218adjacent to the fixed charge film232.

For the fixed charge film232, for example, a high refractive index material film or a high dielectric film, which has a negative charge, may be used. For example, a metal oxide or metal nitride containing at least one element of hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), or titanium (Ti) may be used for the fixed charge film232. Furthermore, for the fixed charge film232, an oxide or nitride containing at least one element of lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), or yttrium (Y) may be used. Moreover, a hafnium oxynitride film or an aluminum oxynitride film may be used for the fixed charge film232.

As the material of the fixed charge film232, silicon (Si) or nitrogen (N) may be added to the film as long as insulation properties are not impaired. The concentration thereof is appropriately determined within a range in which the insulation properties of the film are not impaired. As described above, the addition of silicon (Si) or nitrogen (N) makes it possible to increase the heat resistance of the film and the ability to prevent ion implantation in the process.

The fixed charge film232having a negative charge is provided on the inner wall of the trench TR and the second surface F2of the semiconductor substrate218. Therefore, an inversion layer (p-type charge induction layer) is formed on the inner wall of the trench TR in contact with the fixed charge film232and the second surface F2of the semiconductor substrate218. Since a silicon interface is pinned by the charge induction layer, generation of a dark current is suppressed. Furthermore, when the trench TR is formed, physical damage may occur on the inner wall of the trench TR, and pinning deviation may occur in a peripheral portion of the trench TR. On the other hand, in the present embodiment, the fixed charge film232having a fixed charge is provided on the inner wall of the trench TR, and thus the pinning deviation can be suppressed.

Note that, as a forming method of the fixed charge film232, for example, a chemical vapor deposition (CVD) method, a sputtering method, an atomic layer deposition (ALD) method, or the like may be used.

In the trench TR, the pixel isolation film233as a second insulation film is provided so as to fill the trench TR on an inner side of the fixed charge film232. The pixel isolation film233is provided along the trench TR, and is provided between the adjacent pixels100similarly to the trench TR. The pixel isolation film233fills the trench TR to electrically and optically isolate the adjacent pixels100from each other. For the pixel isolation film233, for example, a material having a refractive index different from that of the fixed charge film232is preferably used, and for example, silicon oxide, silicon nitride, silicon oxynitride, resin, or the like can be used. Furthermore, for the pixel isolation film233, for example, a material that does not have a positive fixed charge or has a small amount of the positive fixed charge may be used.

Since a material having high insulation properties and high light shielding properties for the pixel isolation film233is used, incident light and a signal charge hardly leak into adjacent pixels. Therefore, the leakage (crosstalk) of incident light between the pixels100can be suppressed. Furthermore, even when the signal charge exceeding the saturation charge amount (Qs) is generated, it is possible to prevent the signal charge from leaking to adjacent pixels.

The charge induction layer220is, for example, a p-type high-concentration charge layer, and is a positive charge layer induced by a fixed charge (for example, negative charge) of the fixed charge film232. The charge induction layer220may be a p-type impurity diffusion layer formed by introducing a p-type impurity. Alternatively, the charge induction layer220may be induced by the fixed charge film232, and the p-type impurity may not necessarily be introduced (refer to a second embodiment).

The element isolation film234as a third insulation film covers the end of the fixed charge film232and the end of the pixel isolation film233on the first surface F1side. The element isolation film234is provided on the first surface F1of the semiconductor substrate218to define an active area A-A for forming the transistor250as illustrated inFIG.6, and electrically isolates the active areas A-A from each other. When viewed in a direction substantially perpendicular to the first surface F1(in a Z direction), as illustrated inFIG.6, the element isolation film234is provided between the adjacent pixels100, and overlaps the fixed charge film232and the pixel isolation film233. Accordingly, as illustrated inFIG.6, the element isolation film234appears on the first surface F1, and the fixed charge film232and the pixel isolation film233are under the element isolation film234and do not appear on the first surface F1. According to the present embodiment, since the element isolation film234covers the end of the fixed charge film232and the end of the pixel isolation film233, the element isolation film234isolates the charge induction layer220from the source or drain of the transistor250by being interposed between the charge induction layer220and the source or drain of the transistor250. Therefore, it is possible to suppress formation of a pn junction between the charge induction layer220having a high concentration of P+charge and the source or drain diffusion layer252having a high concentration of N+charge in the pixel100.

The transistor250is provided on the first surface F1of the semiconductor substrate218, and includes a gate251, and the source and drain diffusion layers (hereinafter, also simply referred to as a diffusion layer)252. The diffusion layer252is a high-concentration impurity diffusion layer having an n+-type impurity of a conductivity type opposite to that of the charge induction layer220.

The transistor250is at least one of the transistors constituting the pixel100illustrated inFIG.3, and may be any of the transfer transistor112, the reset transistor113, the amplification transistor114, and the selection transistor115.

The interlayer insulation film262and the wiring261are provided on the first surface F1. The transistor250is covered by the interlayer insulation film262. The wiring261is electrically connected to any one of the transfer transistor112, the reset transistor113, the amplification transistor114, and the selection transistor115, and reads a signal voltage corresponding to the signal charge from the selection transistor115to the vertical signal line VSL.

On the other hand, the fixed charge film232and the pixel isolation film233are provided on the second surface F2of the semiconductor substrate218, and the light shielding film214is further provided on the fixed charge film232and the pixel isolation film233. The light shielding film214is provided along the trench TR so as to overlap the trench TR when viewed from above the second surface F2(that is, Z direction). The light shielding film214includes a metal material having high light shielding properties. For example, a single metal material such as tungsten or aluminum, a stacked film of aluminum and a barrier metal (for example, titanium, cobalt, and the like), a stacked film of tungsten and a barrier metal (for example, titanium, cobalt, and the like), a stacked film of aluminum and cobalt, or the like can be used for the light shielding film214. The light shielding film214can prevent incident light from entering the through trench TR and reduce random noise in the pixel100.

The planarization film213is provided on the second surface F2and covers the light shielding film214. The surface of the planarization film213is planarized to provide a flat surface for the color filter212. As the planarization film213, for example, an insulation film such as a silicon oxide film is used. The planarization film213and the color filter212include a light transmitting material.

The color filter212is provided on the planarization film213. For example, a resin or the like that transmits light of a specific color such as RGB is used as the color filter212.

The on-chip lens211is provided on the color filter212and condenses incident light on the photodiode219of the pixel100.

The incident light is incident on the photodiode219of the pixel100from the second surface F2. The solid-state imaging element according to the present embodiment is a back-side illumination complementary metal oxide semiconductor (CMOS) image sensor (CIS) for capturing light from the second surface (back surface) F2side opposite to the first surface (front surface) F1on which the transistor250and the wiring261are provided. However, the present technology may be applied to a front-side illumination CIS.

The incident light enters the photodiode219via the on-chip lens211, the color filter212, and the planarization film213, and is photoelectrically converted in the photodiode219.

The anode of the photodiode219is grounded, the positive charge (hole) is expelled to the ground, and the negative charge (electron) is accumulated in the photodiode219. The electron accumulated in the photodiode219is read via the transfer transistor or the like and output to the vertical signal line VSL ofFIG.3as an electrical signal.

As described above, according to the present embodiment, the element isolation film234is provided along both sides of the trench TR when viewed in a direction substantially perpendicular to the first surface F1. Furthermore, the element isolation film234is provided on the trench TR so as to overlap the trench TR when viewed in a direction substantially perpendicular to the first surface F1. Therefore, it is possible to suppress formation of a pn junction between the charge induction layer220having a high concentration of P+charge and the diffusion layer252having a high concentration of N+charge in the pixel100.

In a case where the element isolation film234does not cover the end of the trench TR, the end of the fixed charge film232, and the end of the pixel isolation film233, the charge induction layer220inFIG.5is formed up to the first surface F1. In this case, the charge induction layer220and the diffusion layer252form a high-concentration pn junction formed by a high-concentration p+charge layer and a high-concentration n+diffusion layer. In a case where there is a high concentration pn junction, a high electric field is generated in the high concentration pn junction, which causes a dark current. The dark current causes random noise of the pixel100, and the effect of suppressing the dark current with pinning of the fixed charge film232is weakened.

On the other hand, in the present embodiment, the element isolation film234covers the end of the fixed charge film232and the end of the pixel isolation film233along the through trench TR. The element isolation film234insulates and isolates the charge induction layer220from the source and drain diffusion layers252of the transistor250. This suppresses formation of the high-concentration pn junction and suppresses generation of the high electric field. As a result, the dark current is suppressed, and the random noise in the pixel100can be reduced.

Next, the size of the element isolation film234will be described in more detail with reference toFIG.5.

The element isolation film234is provided so as to overlap the trench TR on both sides of the trench TR and along the trench TR when the semiconductor substrate218is viewed in a direction perpendicular to the first surface F1(that is, in a Z direction). Furthermore, a width W234of the element isolation film234is greater than a width Wtr of the trench TR. The width Wtr of the trench TR is equal to or greater than the width of the fixed charge film232or the width of the pixel isolation film233. Accordingly, the width W234is greater than any of the width of the trench TR, the width of the fixed charge film232, and the width of the pixel isolation film233. Note that, as illustrated inFIG.5, the width W234and the width Wtr are widths in a cross section in a direction substantially perpendicular to an extending direction (that is, X direction) of the trench TR, fixed charge film232, and pixel isolation film233on the first surface F1. Moreover, as illustrated inFIG.5, the element isolation film234protrudes toward the photodiode219side (that is, ±X direction) as compared with the charge induction layer220. Accordingly, the width W234of the element isolation film234is greater than a width W220formed by one trench TR and two charge induction layers220on both sides of the trench TR. Therefore, the charge induction layer220is prevented from being formed (induced) on the side surfaces of the element isolation film234, and the element isolation film234can more reliably isolate the charge induction layer220from the diffusion layer252.

Furthermore, a depth (thickness) D234of the element isolation film234in a Z direction is deeper (thicker) than a depth (thickness) D252of the diffusion layer252. Therefore, the element isolation film234can more reliably isolate the charge induction layer220from the diffusion layer252.

Next, a manufacturing method of the solid-state imaging element of the present embodiment will be described.

FIGS.7to13are cross-sectional views illustrating an example of the manufacturing method of the solid-state imaging element according to the first embodiment.

A processing step from the first surface F1of the semiconductor substrate218is performed.

First, the element isolation film234is formed on the first surface F1side of the semiconductor substrate218. The element isolation film234is formed to define the active area A-A as shallow trench isolation (STI). Furthermore, in the present embodiment, the element isolation film234is formed in a formation region of the trench TR between the adjacent pixels100. The element isolation film234removes the upper portion of the semiconductor substrate218in the element isolation region by using a lithography technology and an etching technology. Thereafter, an insulation film such as a silicon oxide film is embedded in the element isolation region to form the element isolation film234. The element isolation film234is formed to be wider than the trench TR and charge induction layer220described above.

Next, a trench TR is formed between the adjacent pixels100by using the lithography technology and an etching technology. The trench TR is formed in the semiconductor substrate218from the first surface F1toward the second surface F2of the semiconductor substrate218. At this time, the trench TR may penetrate the semiconductor substrate218, but may not penetrate the semiconductor substrate218at this stage. In this case, the second surface F2of the semiconductor substrate218may be polished in a rear end step, and the trench TR may penetrate the semiconductor substrate218.

Next, a p-type impurity is ion-implanted in an inclined direction toward the inner wall of the trench TR. Alternatively, the p-type impurity may be introduced into the inner wall of the trench TR by using a plasma doping method. Moreover, a p-type impurity may be introduced into the inner wall of the trench TR by using a solid-phase diffusion method. Accordingly, a p-type diffusion layer is formed as the charge induction layer220on the side wall of the trench TR.

Next, an insulation film301such as a silicon oxide film is deposited on the inner wall of the trench TR, and then the inside of the trench TR is filled with a sacrificial film302such as polysilicon. The sacrificial film302is a material that can be selectively etched with respect to the insulation film301. The trench TR also penetrates the central portion of the element isolation film234. Therefore, after the formation of the trench TR, the insulation film301, and the sacrificial film302, the trench TR portion of the element isolation film234is backfilled with the silicon oxide film. Accordingly, the structure illustrated inFIG.7is obtained. Note that the element isolation film234may be formed after the formation of the trench TR, the insulation film301, and the sacrificial film302. In this case, it is not necessary to backfill the trench TR portion of the element isolation film234with the silicon oxide film.

Next, the photodiode219and the transistor250are formed on the first surface F1. Moreover, the interlayer insulation film262and the wiring261are formed on the transistor250. Accordingly, the structure illustrated inFIG.8is obtained. When the transistor250is formed, the source and drain diffusion layers252are also formed. The depth of the diffusion layer252is formed to be shallower than the depth of the element isolation film234.

Next, a processing step from the second surface F2of the semiconductor substrate218is performed.

The semiconductor substrate218is polished from the second surface F2side by using a chemical mechanical polishing (CMP) method or the like to thin the semiconductor substrate218to a desired thickness. Accordingly, the structure illustrated inFIG.9is obtained.

Next, as illustrated inFIG.10, a material (for example, a silicon oxide film) of a hard mask303is deposited on the second surface F2. Next, the material of the hard mask303is processed so as to open the region of the trench TR by using the lithography technology and the etching technology.

Next, as illustrated inFIG.11, by using the hard mask303as a mask, the sacrificial film302is isotropically etched and removed by using a chemical dry etching (CDE) method or the like. At this time, since the sidewall of the trench TR is covered by the insulation film301, etching is not performed.

Next, as illustrated inFIG.12, the insulation film301is removed by using the CDE method or the like, and the hard mask303on the second surface F2is also removed.

Next, as illustrated inFIG.13, the fixed charge film232is deposited on the inner wall of the trench TR. At this time, the fixed charge film232is thinly deposited on the inner wall of the trench TR so as not to fill the trench TR. By forming the fixed charge film232on the inner wall of the trench TR, the charge (positive charge) is induced in the semiconductor substrate218in the vicinity of the inner wall of the trench TR.

Next, the trench TR is filled with the pixel isolation film233. Accordingly, the structure illustrated inFIG.13is obtained.

Thereafter, the light shielding film214, the planarization film213, and the color filter212are formed, and the on-chip lens211is further formed on the color filter212. As a result, the solid-state imaging element according to the first embodiment is made.

According to the present embodiment, the element isolation film234covers the end of the fixed charge film232and the end of the pixel isolation film233along the through trench TR. Therefore, the charge induction layer220and the diffusion layer252can be insulated and isolated, and a dark current of the pixel100can be suppressed.

Furthermore, according to the present embodiment, in the front end step, the trench TR is filled with the insulation film301and the sacrificial film302. The insulation film301and the sacrificial film302include, for example, a material having high heat resistance, such as a silicon oxide film or polysilicon. Therefore, a high-temperature process can be used in the front end step of forming the transistor250, the wiring261, and the like on the first surface F1.

When the trench TR is filled with a material having low heat resistance, such as a metal material in the front end step, a high temperature process required in the front end step cannot be used.

On the other hand, according to the present embodiment, in the front end step, the trench TR is filled with the insulation film301and the sacrificial film302, which have a heat resistance higher than that of the metal material. Therefore, the high temperature process can be used in the front end step.

On the other hand, in the rear end step, the fixed charge film232can be formed on the inner wall of the trench TR. The fixed charge film232induces a charge in the charge induction layer220in the vicinity of the inner wall of the trench TR. Therefore, the dark current is suppressed, and the random noise in the pixel100can be reduced.

Second Embodiment

FIG.14is a cross-sectional view illustrating a configuration example of a pixel100according to the second embodiment. The plan view of the pixel100according to the second embodiment may be basically the same as that inFIG.6.

In the second embodiment, a light shielding film235is provided on an inner side of the pixel isolation film233in the trench TR. The light shielding film235is provided along the trench TR when viewed from above the first surface F1, and extends in a Z direction between the first surface F1and the second surface F2. Accordingly, the light shielding film235is provided between a plurality of adjacent pixels100, and optically isolates the pixels100from each other. Therefore, crosstalk between a plurality of the pixels100can be further suppressed.

The light shielding film235includes a metal material having high light shielding properties. For example, a single metal material such as tungsten or aluminum, a stacked film of aluminum and a barrier metal (for example, titanium, cobalt, and the like), a stacked film of tungsten and a barrier metal (for example, titanium, cobalt, and the like), a stacked film of aluminum and cobalt, or the like can be used for the light shielding film235. Other configurations of the second embodiment may be similar to those of the first embodiment.

In the manufacturing method of the pixel100according to the second embodiment, after the fixed charge film232is formed in the trench TR, the pixel isolation film233is formed on the fixed charge film232in the trench TR. At this time, the material of the pixel isolation film233is thinly formed on the fixed charge film232without completely filling the inside of the trench TR.

Next, the material of the light shielding film235fills the inside of the trench TR. Accordingly, the light shielding film235covered with the pixel isolation film233is formed at the center portion of the trench TR.

Other manufacturing methods of the second embodiment may be the same as the corresponding manufacturing method of the first embodiment. As a result, the solid-state imaging element according to the second embodiment is made.

According to the second embodiment, the light shielding film235is formed in the trench TR in the rear end step. Thus, even when a metal material having low heat resistance is used for the light shielding film235, a high-temperature process can be executed in the front end step. Furthermore, the second embodiment can obtain the effects similar to those of the first embodiment.

Third Embodiment

FIG.15is a cross-sectional view illustrating a configuration example of a pixel100according to the third embodiment. The plan view of the pixel100according to the third embodiment may be basically the same as that inFIG.6.

In the third embodiment, the charge induction layer220is a p-type charge layer induced by the fixed charge film232, and no impurity is introduced into the inner wall of the trench TR. When the p-type charge layer is sufficiently induced on the inner wall of the trench TR by the fixed charge film232, the charge induction layer220is formed without introducing the impurity into the region of the charge induction layer220. Therefore, the dark current can be suppressed. In this case, a step of introducing an impurity into the inner wall of the trench TR can be omitted. Other configurations and the manufacturing method of the third embodiment may be similar to those of the first embodiment.

Thus, the third embodiment can obtain the same effects as those of the first embodiment. Furthermore, according to the third embodiment, the manufacturing process can be shortened as compared with the first embodiment.

Fourth Embodiment

FIG.16is a cross-sectional view illustrating a configuration example of a pixel100according to the fourth embodiment. The fourth embodiment is a combination of the second and third embodiments. Accordingly, the pixel100according to the fourth embodiment further includes a light shielding film235in the trench TR, and the p-type impurity is not introduced into the charge induction layer220. Other configurations and the manufacturing method of the fourth embodiment may be similar to those of the second embodiment or third embodiment. Therefore, the fourth embodiment can obtain the same effects as those of the second and third embodiments.

Fifth Embodiment

FIG.17is a cross-sectional view illustrating a configuration example of a pixel100according to the fifth embodiment. In the pixel100according to the fifth embodiment, the trench TR penetrates the element isolation film234from the first surface F1and protrudes toward the interlayer insulation film262. Accordingly, the end of the fixed charge film232and the end of the pixel isolation film233on the first surface F1side penetrate the element isolation film234from the first surface F1and protrude toward the interlayer insulation film262.

As described above, even when the fixed charge film232and the pixel isolation film233penetrate the element isolation film234, the element isolation film234is still provided on both sides of the fixed charge film232and pixel isolation film233, and is provided along the trench TR on the first surface F1. Other configurations of the fifth embodiment may be similar to those of the first embodiment. Therefore, in the solid-state imaging element according to the fifth embodiment, the effects similar to those of the first embodiment can be obtained.

In the manufacturing method of the solid-state imaging element according to the fifth embodiment, after the steps illustrated inFIGS.7to11, in the step illustrated inFIG.12, the insulation film301is removed, and a part of the element isolation film234and a part of the interlayer insulation film262are etched at the bottom of the trench TR. Accordingly, the trench TR is formed so as to penetrate the element isolation film234and reach the interlayer insulation film262. Thereafter, the solid-state imaging element according to the fifth embodiment is made through the step described with reference toFIG.13.

Sixth Embodiment

FIG.18is a cross-sectional view illustrating a configuration example of a pixel100according to the sixth embodiment. In the pixel100according to the sixth embodiment, the trench TR penetrates the element isolation film234from the first surface F1and protrudes toward the interlayer insulation film262. Accordingly, the fixed charge film232, the pixel isolation film233, and the light shielding film235penetrate the element isolation film234from the first surface F1and protrude toward the interlayer insulation film262.

As described above, even when the fixed charge film232, the pixel isolation film233, the light shielding film235penetrate the element isolation film234, the element isolation film234is provided on both sides of the fixed charge film232and pixel isolation film233, and is provided along the trench TR on the first surface F1. Other configurations of the sixth embodiment may be similar to those of the second embodiment. Therefore, in the solid-state imaging element according to the sixth embodiment, the effects similar to those of the second embodiment can be obtained.

Since the manufacturing method of the solid-state imaging element according to the sixth embodiment can be easily analogized from the manufacturing methods of the second and fifth embodiments, the description thereof will be omitted.

According to the sixth embodiment, since the light shielding film235also penetrates the element isolation film234and protrudes toward the interlayer insulation film262, light shielding properties between adjacent pixels100can be improved, and crosstalk can be further suppressed.

The technology (present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, or a robot.

FIG.19is a block diagram illustrating a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The imaging section12031is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like. The solid-state imaging element1according to the present disclosure may be the imaging section12031, or may be provided separately from the imaging section12031.

FIG.20is a diagram illustrating an example of an installation position of the imaging section12031.

InFIG.20, a vehicle12100includes, as the imaging section12031, imaging sections12101,12102,12103,12104, and12105.

The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided to the sideview mirrors mainly obtain images of the sideward sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The forward side images obtained by the imaging sections12101and12105are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

At least one of the imaging sections12101to12104may be an infrared camera that detects infrared rays. The microcomputer12051can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections12101to12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections12101to12104as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer12051determines that there is a pedestrian in the imaged images of the imaging sections12101to12104, and thus recognizes the pedestrian, the sound/image output section12052controls the display section12062so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section12052may also control the display section12062so that an icon or the like representing the pedestrian is displayed at a desired position. An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The solid-state imaging element according to the present disclosure can be applied to, for example, the imaging section12031among the above-described configurations. Therefore, the imaging section12031can obtain the effects of the above-described embodiment.

Seventh Embodiment

FIG.21is a cross-sectional view illustrating a partial configuration example of a pixel100according to the seventh embodiment.FIG.21illustrates a cross section of the end portion of the trench TR on the first surface F1side. The seventh embodiment may also be applied to a back-side illumination CIS or a front-side illumination CIS. The plan view of the seventh embodiment may be basically similar to the plan view ofFIG.6. Therefore, the element isolation film234is provided on the first surface F1of the substrate218, and is provided on both sides of the trench TR or along the trench TR when viewed from the first surface F1. Furthermore, when viewed from the first surface F1, the element isolation film234is formed to be wider than the pixel isolation film233. Note that the pixel isolation film233is a so-called full trench isolation (FTI) penetrating the substrate218between the first surface F1and the second surface F2, and the element isolation film234is a so-called shallow trench isolation (STI) formed in a surface region of the first surface F1shallower than the pixel isolation film233.

Moreover, in the seventh embodiment, the diffusion layer252is in contact with the side surface S234of the element isolation film234. The diffusion layer252is a high-concentration impurity diffusion layer having an n+-type impurity of a conductivity type opposite to that of the charge induction layer220. Therefore, a depletion layer300spreads in the substrate218around the diffusion layer252. The diffusion layer252may be a diffusion layer of a source and drain of the transistor250, or may be another diffusion layer such as a floating diffusion region. On the other hand, the end of the pixel isolation film233on the first surface F1side is not exposed from the side surface S234of the element isolation film234. Therefore, the pixel isolation film233is separated from the depletion layer300and is configured not to be in contact with the depletion layer300. That is, the interface between the pixel isolation film233and the element isolation film234is inside the element isolation film234, and is not exposed to (does not face) the side surface S234of the element isolation film234. Accordingly, the pixel isolation film233is configured not to be in contact with the depletion layer300.

The pixel isolation film233may be formed by forming the element isolation film234and the trench TR and then embedding a filling material from the second surface F2side. In this case, the sacrificial film previously embedded in the trench TR is removed from the second surface F2side of the substrate218, and then the filling material (for example, a silicon oxide film) of the pixel isolation film233fills the trench TR. Here, in a series of steps of removing the sacrificial film, a part of the filling material (for example, a silicon oxide film) of the element isolation film234may be simultaneously removed, and a cavity may be formed in the element isolation film234via the trench TR. When this cavity reaches the side surface S234of the element isolation film234, the substrate218(for example, a silicon substrate) having relatively high interface state density is exposed in the cavity on the side surface S234of the element isolation film234. In this case, when the filling material of the pixel isolation film233is embedded in the trench TR and the cavity, the pixel isolation film233is also formed on the side surface S234of the element isolation film234, and the interface state density between the pixel isolation film233and the substrate218exposed on the side surface S234of the element isolation film234increases. When the pixel isolation film233reaching the side surface S234of the element isolation film234is in contact with the depletion layer300extending from the diffusion layer252, junction leakage occurs due to a noise charge generated at the interface between the pixel isolation film233and the depletion layer300, and image quality deterioration, for example, a dark current is generated. Furthermore, in a case where the pixel isolation film233includes a negative fixed charge, the positive charge induction layer220is generated at the interface between the pixel isolation film233and the depletion layer300, and the electric field of the portion thereof is increased. Therefore, the junction leakage further occurs, and deterioration of the image quality is caused.

On the other hand, in the seventh embodiment, the end of the pixel isolation film233on the first surface F1side is not exposed from the side surface S234of the element isolation film234, and the pixel isolation film233is separated from the depletion layer300. Thus, the surface of the substrate218having the high interface state density is not exposed on the side surface S234of the element isolation film234, and the pixel isolation film233is not in contact with the depletion layer300. Therefore, the junction leakage can be suppressed, and deterioration of the image quality due to the dark current or the like can be suppressed.

Other configurations of the seventh embodiment may be the same as any of the first to sixth embodiments. Therefore, the seventh embodiment can obtain the effects similar to those of the first to sixth embodiments.

FIGS.22to26are cross-sectional views illustrating an example of the manufacturing method of the solid-state imaging element according to the seventh embodiment.

A processing step from the first surface F1of the semiconductor substrate218is performed.

First, a hard mask HM is formed on the first surface F1, and the hard mask HM is processed using a lithography technology and an etching technology. The hard mask HM is, for example, an insulation film such as a silicon oxide film or a silicon nitride film. Next, the hard mask HM is used as a mask, and the trench TR is formed between adjacent pixels100by using the etching technology. The trench TR is formed in the substrate218from the first surface F1toward the second surface F2of the semiconductor substrate218. At this time, the trench TR may penetrate the semiconductor substrate218, but may not penetrate the semiconductor substrate218at this stage. In this case, the second surface F2of the semiconductor substrate218may be polished in a rear end step, and the trench TR may penetrate the semiconductor substrate218. Note that, in the seventh embodiment, the trench TR is formed before the formation of the element isolation film234, but the element isolation film234may be formed before the formation of the trench TR as in the first embodiment.

Next, as necessary, a p-type diffusion layer is formed as the charge induction layer (not illustrated inFIG.22) on the sidewall of the trench TR.

Next, an insulation film (liner layer)301such as a silicon oxide film is formed on the inner wall of the trench TR, and then the inside of the trench TR is filled with the sacrificial film302such as polysilicon. The sacrificial film302is a material that can be selectively etched with respect to the insulation film301. The sacrificial film302includes, for example, a material that can be selectively etched with respect to the insulation film301including polysilicon or amorphous silicon. Next, the material of the sacrificial film302on the hard mask HM is removed by using CMP or wet etching, and the height of the sacrificial film302in the trench TR is adjusted. Accordingly, the structure illustrated inFIG.22is obtained.

Next, a trench TR2is formed on the first surface F1side of the semiconductor substrate218. The trench TR2is formed in a formation region of the element isolation film234between the adjacent pixels100. The trench TR2removes the upper portion of the semiconductor substrate218in the element isolation region by using a lithography technology and an etching technology. Accordingly, the trench TR2shallower than the trench TR is formed in the element isolation region. Thereafter, a thermal oxide film311of the substrate218is formed on the inner wall of the trench TR2, and an insulation film312such as a silicon oxide film the inside of the thermal oxide film311.

Accordingly, the element isolation film234is formed. Here, the element isolation film234(that is, the trench TR2) is formed to be wider than the trench TR and the charge induction layer220. Moreover, in a plan view seen from above the first surface F1(Z direction), the element isolation film234is formed to be wider than the pixel isolation film233to be formed later in the element isolation film234. Accordingly, the pixel isolation film233is prevented from being exposed from the side surface S234of the element isolation film234.

Other steps in the front end step of the seventh embodiment may be similar to the corresponding steps in the front end step of the first embodiment. For example, various ion implantation, formation of a gate electrode, activation annealing, formation of a wiring layer, and the like are performed. Moreover, another semiconductor chip having a logic circuit is connected to the first surface F1. Note that, inFIG.22and subsequent drawings, the photodiode219, the transistor250, the wiring261, other joined semiconductor chips, and the like are omitted.

Next, a processing step from the second surface F2of the semiconductor substrate218is performed.

The semiconductor substrate218is polished from the second surface F2side by using a CMP method or the like to thin the semiconductor substrate218to a desired thickness. Accordingly, the trench TR penetrates the substrate218, and one end of the sacrificial film302is exposed from the second surface F2.

Next, as illustrated inFIG.24, a material (for example, a silicon oxide film) of the hard mask303is deposited on the second surface F2. Next, the material of the hard mask303is processed so as to open the region of the trench TR by using the lithography technology and the etching technology.

Next, the hard mask303is used as a mask, and the sacrificial film302is isotropically etched and removed using the CDE or the like. Next, the hard mask303is removed. At this time, since the hard mask303includes a silicon oxide film, as illustrated inFIG.25, the insulation film301on the sidewall of the trench TR, and the thermal oxide film311and insulation film312formed in the trench TR2are also partially removed together with the hard mask303. In this case, a cavity320of the trench TR extends into the element isolation film234, and the thermal oxide film311is also partially removed. However, the cavity320is formed so as not to reach the side surface S234of the element isolation film234. That is, only the upper portion of the element isolation film234is removed such that the trench TR does not extend to the side surface S234of the element isolation film234. The width W233of the cavity320is smaller than the width W234of the element isolation film234. Accordingly, the cavity320of the trench TR exposes the substrate218on a part of the upper surface of the element isolation film234and is in contact with the substrate218, but does not expose the substrate218and is not in contact with the substrate218on the side surface S234of the element isolation film234.

Next, as necessary, the fixed charge film (not illustrated) is deposited on the inner wall of the trench TR.

Next, as illustrated inFIG.26, the trench TR is filled with the pixel isolation film233. At this time, the pixel isolation film233also fills the cavity320. Therefore, the width W233of the cavity320is the width of the pixel isolation film233. The width W233of the pixel isolation film233is smaller than the width W234of the element isolation film234. Accordingly, the pixel isolation film233in the element isolation film234is exposed on a part of the element isolation film234and is in contact with the substrate218, but is not exposed from the side surface S234of the element isolation film234and is not in contact with the substrate218. That is, on the side surface S234of the element isolation film234, the pixel isolation film233does not have an interface with the substrate218. The interface between the pixel isolation film233and the element isolation film234is in the element isolation film234, but is not exposed on the side surface S234. Note that the pixel isolation film233may include a single insulation material. However, the pixel isolation film233may have a stacked structure of a plurality of kinds of material films.

Thereafter, as in the other embodiments, the light shielding film, the planarization film, and the color filter are formed, and the on-chip lens is further formed on the color filter. As a result, the solid-state imaging element according to the seventh embodiment is made.

According to the seventh embodiment, the surface of the substrate218having high interface state density generated by removing the thermal oxide film311on the inner wall of the trench TR2is not exposed on the side surface S234of the element isolation film, and the pixel isolation film233formed in a back surface step is separated from the depletion layer300. Therefore, it is possible to suppress junction leakage caused by a noise charge generated in the depletion layer300in a case where the pixel isolation film233and the depletion layer300are in contact with each other. It is possible to suppress the occurrence of junction leakage due to a high electric field caused when the charge induction layer220is present in the depletion layer300, which occurs in a case where the fixed charge is included in the pixel isolation film233. Furthermore, from the viewpoint of image quality, generation of the dark current and inflow of a charge to the floating diffusion FD formed by the diffusion layer252can be suppressed.

Eighth Embodiment

FIG.27is a cross-sectional view illustrating a partial configuration example of a pixel100according to the eighth embodiment.FIG.27illustrates a cross section of the end portion of the trench TR on the first surface F1side. The eighth embodiment may also be applied to a back-side illumination CIS or a front-side illumination CIS. The plan view of the eighth embodiment may be basically similar to the plan view ofFIG.6. Therefore, the element isolation film234is provided on the first surface F1of the substrate218, and is provided on both sides of the trench TR or along the trench TR when viewed from the first surface F1. Furthermore, when viewed from the first surface F1, the element isolation film234is formed to be wider than the pixel isolation film233.

In the eighth embodiment, as in the seventh embodiment, the pixel isolation film233is not exposed from the side surface S234of the element isolation film234. Moreover, in the eighth embodiment, the interface between the pixel isolation film233and the element isolation film234is in the trench TR. That is, a distance from the second surface F2to the interface between the pixel isolation film233and the element isolation film234is shorter than the distance from the second surface F2to the lower end of the trench TR. In the eighth embodiment, the interface between the pixel isolation film233and the element isolation film234is provided closer to the second surface F2side as compared with the seventh embodiment. In this case, the pixel isolation film233does not reach the element isolation region.

In the eighth embodiment, as in the seventh embodiment, the end of the pixel isolation film233on the first surface F1side is not exposed from the side surface S234of the element isolation film234, and the pixel isolation film233is separated from the depletion layer300. Furthermore, in the eighth embodiment, the thermal oxide film311of the trench TR2is not removed. Thus, the surface of the substrate218having high interface state density generated by removing the thermal oxide film311is not exposed on the side surface S234of the element isolation film234. Furthermore, the pixel isolation film233is not in contact with the depletion layer300. Therefore, the junction leakage can be suppressed, and the dark current and the inflow of the charge to the floating diffusion FD can be suppressed.

Other configurations of the eighth embodiment may be the same as any of the first to seventh embodiments. Therefore, the eighth embodiment can obtain the effects similar to those of the first to seventh embodiments.

FIGS.28to33are cross-sectional views illustrating an example of the manufacturing method of the solid-state imaging element according to the eighth embodiment.

A processing step from the first surface F1of the semiconductor substrate218is performed.

First, the structure illustrated inFIG.22is formed through steps similar to those in the seventh embodiment. Next, the sacrificial film302is partially removed from the first surface F1side by using a wet etching method, and thus the upper surface of the sacrificial film302is lowered below the first surface F1. The upper surface of the sacrificial film302is recessed into the trench TR. The recessed amount of the upper surface of the sacrificial film302is adjusted such that the cavity320does not reach the element isolation region (trench TR2) in consideration of the amount that the material of the element isolation film234is etched in the rear end step to be described later. Accordingly, the structure illustrated inFIG.28is obtained. Note that the inner wall of the trench TR is protected by the insulation film (liner layer)301.

Next, a trench TR2is formed on the first surface F1side of the semiconductor substrate218. The trench TR2is formed in a formation region of the element isolation film234between the adjacent pixels100. The trench TR2removes the upper portion of the semiconductor substrate218in the element isolation region by using a lithography technology and an etching technology. Accordingly, the trench TR2shallower than the trench TR is formed in the element isolation region. Furthermore, when the trench TR2is formed, the upper surface of the sacrificial film302is etched together with the processing for the semiconductor substrate218. The sacrificial film302includes, for example, polysilicon or amorphous silicon, and thus can be etched together with the etching for the substrate218. Therefore, the upper surface of the sacrificial film302can be lowered to the inside of the trench TR below the bottom surface of the trench TR2. Accordingly, the structure illustrated inFIG.29is obtained. Note that the inner wall of the trench TR is protected by the insulation film301.

Thereafter, as illustrated inFIG.30, a thermal oxide film311of the substrate218is formed on the inner wall of the trench TR2, and an insulation film312such as a silicon oxide film the inside of the thermal oxide film311. Accordingly, the element isolation film234is formed. Here, the material of the element isolation film234is embedded up to the upper surface of the sacrificial film302in the trench TR. Thus, the interface between the element isolation film234and the sacrificial film302is formed in the trench TR.

Other steps in the front end step of the eighth embodiment may be similar to the corresponding steps in the front end step of the first embodiment. For example, various ion implantation, formation of a gate electrode, activation annealing, formation of a wiring layer, and the like are performed. Moreover, another semiconductor chip having a logic circuit is connected to the first surface F1.

Next, a processing step from the second surface F2of the semiconductor substrate218is performed.

The semiconductor substrate218is polished from the second surface F2side by using a CMP method or the like to thin the semiconductor substrate218to a desired thickness. Accordingly, the trench TR penetrates the substrate218, and one end of the sacrificial film302is exposed from the second surface F2.

Next, as illustrated inFIG.31, a material (for example, a silicon oxide film) of the hard mask303is deposited on the second surface F2. Next, the material of the hard mask303is processed so as to open the region of the trench TR by using the lithography technology and the etching technology.

Next, the hard mask303is used as a mask, and the sacrificial film302is isotropically etched and removed using the CDE or the like. Here, the interface between the sacrificial film302and the element isolation film234is in the trench TR. Thus, since the sacrificial film302is removed, the upper surface of the element isolation film234remains in the trench TR, and the cavity320does not reach the element isolation region (trench TR2). Next, the hard mask303is removed. At this time, since the hard mask303includes a silicon oxide film, as illustrated inFIG.32, the insulation film301on the sidewall of the trench TR, and the insulation film312in the trench TR are also partially removed together with the hard mask303. However, in the eighth embodiment, the cavity320does not reach the element isolation region (trench TR2). Accordingly, the cavity320of the trench TR does not reach the side surface S234of the element isolation film234. Therefore, the thermal oxide film311on the side surface S234of the element isolation film234is maintained.

Next, as necessary, the fixed charge film (not illustrated) is deposited on the inner wall of the trench TR.

Next, as illustrated inFIG.33, the trench TR is filled with the pixel isolation film233. At this time, the pixel isolation film233also fills the cavity320. The interface between the pixel isolation film233and the element isolation film234is formed in the trench TR. Therefore, the pixel isolation film233remains in the trench TR and is not formed in the element isolation region (trench TR2). The pixel isolation film233is not exposed from the side surface S234of the element isolation film234and is not in contact with the substrate218. That is, on the side surface S234of the element isolation film234, the pixel isolation film233does not have an interface with the substrate218. The interface between the pixel isolation film233and the element isolation film234is in the trench TR, and is not exposed on the side surface S234of the element isolation film234.

Thereafter, as in the other embodiments, the light shielding film, the planarization film, and the color filter are formed, and the on-chip lens is further formed on the color filter. As a result, the solid-state imaging element according to the eighth embodiment is made.

According to the eighth embodiment, the end of the pixel isolation film233on the first surface F1side is not exposed from the side surface S234of the element isolation film234, and the pixel isolation film233is separated from the depletion layer300. Therefore, the eighth embodiment can obtain the effects similar to those of the seventh embodiment.

Ninth Embodiment

FIG.34is a cross-sectional view illustrating a partial configuration example of a pixel100according to the ninth embodiment. In the ninth embodiment, the pixel isolation film233is formed by a stacked film. Other configurations of the ninth embodiment may be similar to those corresponding to the seventh and eighth embodiments.

The pixel isolation film233is a stacked film including a plurality of partial films233ato233d. The partial film233dcovers the inner wall of the trench TR. The partial film233ccovers the inner wall of the trench TR via the partial film233d. The partial film233bcovers the inner wall of the trench TR via the partial films233dand233c. Moreover, the partial film233afills the inner wall of the trench TR via the partial films233bto233d. The partial film233ais, for example, an insulation film such as a silicon oxide film, the partial films233band233care, for example, metal films (for example, copper, tungsten, and the like) having high light shielding properties, and the partial film233dis, for example, an insulation film such as a silicon oxide film and electrically isolates the partial films233band233cfrom the substrate218. Furthermore, the partial film233dmay be a fixed charge film or a low refractive index film.

Other configurations of the ninth embodiment may be similar to those of the seventh embodiment. Therefore, the ninth embodiment can obtain the effects similar to those of the seventh embodiment.

Tenth Embodiment

FIG.35is a cross-sectional view illustrating a partial configuration example of a pixel100according to a modification example of the tenth embodiment. The tenth embodiment is a combination of the eighth and ninth embodiments. Thus, in the tenth embodiment, the pixel isolation film233is formed by a stacked film, and the interface between the pixel isolation film233and the element isolation film234is in the trench TR. The configuration of the pixel isolation film233may be the same as those in the ninth embodiment. Other configurations of the tenth embodiment may be similar to those of the eighth embodiment. Therefore, the tenth embodiment can obtain the effects similar to those of the eighth and ninth embodiments.

Eleventh Embodiment

FIGS.36to39are cross-sectional views illustrating a partial configuration example of a pixel100according to the eleventh embodiment. In the eleventh embodiment, a cavity (air gap, void, or seam)350is formed in the pixel isolation film233.FIGS.36to39correspond to the seventh to tenth embodiments, respectively, and a cavity350is provided in each pixel isolation film233. As described above, even when the cavity350is provided in the pixel isolation film233, the effect of each embodiment is not changed.

A solid-state imaging element including:a substrate;a plurality of photoelectric conversion units that is provided in the substrate;a first insulation film that is provided between the plurality of photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units, and has a fixed charge provided on an inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface;a second insulation film that is provided on an inner side of the first insulation film in the trench;at least one transistor that is provided on the first surface of the substrate; anda third insulation film that is provided on both sides of the trench or along the trench when viewed from the first surface.

The solid-state imaging element according to (1), in which the third insulation film is interposed between a charge induction layer formed on a surface of the substrate adjacent to the first insulation film and a source or drain of the transistor.

The solid-state imaging element according to (2), in which the charge induction layer is a high-concentration charge layer of a first conductivity type, andthe source or drain of the transistor is a high-concentration impurity diffusion layer of a second conductivity type.

The solid-state imaging element according to (2) or (3), in which the charge induction layer is an impurity diffusion layer of a first conductivity type.

The solid-state imaging element according to any one of (1) to (4), in which the third insulation film covers ends of the first and second insulation films on the first surface side.

The solid-state imaging element according to any one of (1) to (4), in which the ends of the first and second insulation films on the first surface side penetrate the third insulation film.

The solid-state imaging element according to any one of (1) to (6), further including:a wiring layer that is provided on the first surface of the substrate and electrically connected to the transistor; anda lens that is provided on the second surface of the substrate.

The solid-state imaging element according to any one of (1) to (7), further including a light shielding film that is provided on an inner side of the second insulation film in the trench.

The solid-state imaging element according to any one of (1) to (8), in which the third insulation film overlaps the first and second insulation films when the substrate is viewed from a direction perpendicular to the first surface.

The solid-state imaging element according to any one of (1) to (8), in which a width of the third insulation film is greater than a width of the trench when the substrate is viewed from a direction substantially perpendicular to the first surface.

The solid-state imaging element according to any one of (2) to (4), in which a width of the third insulation film is greater than a width of the charge induction layer provided on both sides of the trench when the substrate is viewed from a direction substantially perpendicular to the first surface.

The solid-state imaging element according to any one of (1) to (11), in which a depth of the third insulation film from the first surface is deeper than a depth of a diffusion layer of the transistor adjacent to the third insulation film.

A manufacturing method of a solid-state imaging element, the method including:forming a plurality of photoelectric conversion units in a substrate;forming, on a first surface of the substrate, a third insulation film between the photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units;forming, between the plurality of adjacent photoelectric conversion units, a trench penetrating between the first surface of the substrate and a second surface opposite to the first surface;forming, on an inner wall of the trench, a first insulation film having a fixed charge;forming, in the trench, a second insulation film on an inner side of the first insulation film; andforming at least one transistor on the first surface of the substrate.

The method according to (13), further including introducing an impurity of a first conductivity type into the inner wall of the trench to form a charge induction layer on the inner wall of the trench.

The method according to (13) or (14), in which the trench penetrates the third insulation film.

A solid-state imaging element including:a substrate;a plurality of photoelectric conversion units that is provided in the substrate;a second insulation film that is provided between the plurality of photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units and provided in a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface;a third insulation film that is provided on the first surface of the substrate and provided on both sides of the trench or along the trench when viewed from the first surface, the third insulation film being wider than the second insulation film; andan impurity diffusion layer that is provided on the first surface of the substrate and in contact with a side surface of the third insulation film,in which the second insulation film is not exposed from the side surface of the third insulation film.

The solid-state imaging element according to (16), in which an interface between the second insulation film and the third insulation film is in the third insulation film.

The solid-state imaging element according to (16), in which an interface between the second insulation film and the third insulation film is in the trench.

The solid-state imaging element according to any one of (16) to (18), in which the second insulation film is a stacked film including a plurality of partial films.

The solid-state imaging element according to (16)19, in which the plurality of partial films is any of a fixed charge film, a low refractive index film, an oxide film, and a metal film.

The solid-state imaging element according to any one of (16) to (20), in which a cavity is provided in the second insulation film.

The solid-state imaging element according to any one of (16) to (21), further including:a wiring layer that is provided on the first surface of the substrate and electrically connected to the impurity diffusion layer; anda lens that is provided on the second surface of the substrate.

A manufacturing method of a solid-state imaging element, the method including:forming a plurality of photoelectric conversion units in a substrate;forming, between the photoelectric conversion units adjacent to each other among the plurality of photoelectric conversion units, a trench extending from a first surface of the substrate to a second surface opposite to the first surface;forming a sacrificial film in the trench;forming a third insulation film on the first surface of the substrate, the third insulation film being wider than the trench on both sides of the trench or along the trench when viewed from the first surface;removing the sacrificial film in the trench from the second surface side of the substrate; andforming a second insulation film in the trench from the second surface side of the substrate.

The method according to (23), further including removing an upper portion of the third insulation film such that the trench does not extend to a side surface of the third insulation film when the sacrificial film is removed,in which the second insulation film is formed so as not to be exposed from the side surface of the third insulation film when the second insulation film is formed.

The method according to (23), further including:partially removing the sacrificial film from the first surface side of the substrate to lower an upper surface of the sacrificial film below the first surface after the sacrificial film is formed;lowering the upper surface of the sacrificial film into the trench below a bottom surface of the third insulation film when the third insulation film is formed; andremoving the sacrificial film from the second surface side of the substrate to form a second insulation film from the second surface side of the substrate into the trench.

Note that the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure. Furthermore, the effects described in the present specification are merely examples and are not limited, and other effects may be provided.

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