Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries

A microprocessor includes a physically-indexed-and-tagged second-level set-associative cache. Each cache entry is uniquely identified by a set index and way number. Each store queue (SQ) entry holds store data for writing to a store physical address and a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and way number of the cache entry allocated to the store physical line address. A load unit obtains a load PAP for a load physical line address that specifies the set index and way number of the cache entry allocated to the load physical line address. The SQ compares the load PAP with each valid store PAP for use in identifying a candidate set of SQ entries whose store data overlaps requested load data and selects an entry from the candidate set from which to forward the store data to the load instruction.

BACKGROUND

Cache memories in microprocessors may have a significant impact on their performance. A cache memory is a memory within a processor that is small and fast relative to system memory, also referred to as main memory. The cache memory holds a copy of a small subset of the contents of system memory so that the processor can access the subset faster than the processor can access system memory. Generally, the cache tends to hold most recently used data by evicting least recently used data when allocating space for newly used data. In this manner, a cache memory reduces the execution time of load/store instructions by alleviating the need to read system memory to access the data specified by a load instruction and enabling a store instruction to immediately write its data to the cache memory without having to wait to write the data to system memory, for example. Generally, a cache memory stores a copy of system memory data in a quantum of a cache line, or cache block, e.g., 64 bytes. That is, when a cache memory allocates an entry for a memory address, the cache memory brings in an entire cache line implicated by the memory address, and when the cache memory has modified a copy of system memory, the cache memory writes back to system memory the entire modified cache line rather than merely the modified data.

The cache memories may significantly improve processor performance since a system memory access may require an order of magnitude more clock cycles than a cache memory access. Importantly, a load instruction, for example, may be stalled in its execution waiting for the data to be read from memory. To further exacerbate the situation, instructions dependent upon the load data may be prevented from being issued for execution, and instructions dependent upon the dependent instructions may also be prevented from being issued for execution, and so forth. If enough dependent instructions are stalled or waiting to issue and sufficient independent instructions are not within the execution window, execution units of the processor may sit idle, significantly reducing the instruction execution rate of the processor.

Even though a cache memory may improve load/store execution time by mitigating the need for memory accesses, nevertheless the time required to access the cache memory also affects the performance of the processor. This is particularly true for the cache memory that is directly accessed by load/store units of the processor, i.e., the cache memory at the lowest level in a processor that includes a cache hierarchy of multiple cache memories. That is, the performance of the processor may be significantly improved by reducing even a single clock cycle from the access time to the first level cache memory and/or enabling the cycle time of the processor to be made shorter by reducing the first level cache memory access time.

Finally, the performance of the processor is also significantly affected by the hit rate of the cache memory, which is affected by the capacity of the cache memory in terms of the number of bytes the cache memory is designed to hold. Cache memories hold other information besides the actual cache line data such as tags, status, and replacement policy information. Reducing the amount of other information held by the cache may enable the capacity of the cache to be bigger, i.e., to store more bytes of copies of memory data, thereby improving its hit rate. Furthermore, reducing the amount of other information held by the cache may enable the physical size of the cache—i.e., the area on the integrated circuit—to be smaller and to reduce the physical size of accompanying logic, e.g., comparators, again potentially enabling the capacity of the cache to be bigger, thereby improving its hit rate and improving the performance of the processor.

Another issue arises in the context of a system that includes multiple processors that share system memory and that each include a cache memory. In such systems, the processors must cooperate to ensure that when a processor reads from a memory address it receives the value most recently written to the address by any of the processors. For example, assume processors A and B each have a copy of a cache line at a memory address in their respective caches, and assume processor A modifies its copy of the cache line. The system needs to ensure that processor B receives the modified value when it subsequently reads from the address. This is commonly referred to as cache coherency.

A frequently employed protocol for attaining cache coherency is commonly referred to as a write-invalidate protocol that involves each processor snooping a shared bus used to access system memory. Using the example above, processor A broadcasts on the bus an invalidate transaction to announce that it intends to modify its copy of the cache line at the memory address. Processor B snoops the bus and sees the invalidate transaction. In response, processor B invalidates its copy of the cache line. When processor B later reads from the memory address, it broadcasts a read transaction on the bus. Processor A snoops the bus and sees the read transaction. In response, processor A provides the modified cache line to processor B and cancels the read transaction to the system memory. Processor A may also write back the modified cache line to system memory at this time.

As described above, cache memories hold and process other information besides the actual cache line data, some of which involves information for handling snooping the shared bus to attain cache coherency. By reducing the amount of cache coherence-related information held and processed by the cache, performance of the processor may be improved by increasing the speed of the cache and reducing its physical size.

SUMMARY

In one embodiment, the present disclosure provides a microprocessor that includes a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries. Each entry in the store queue holds information for a store instruction including store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The microprocessor also includes a load unit configured to, during execution of a load instruction that specifies a load virtual address, obtain a load PAP for a load physical line address that is a translation of a load virtual line address. The load PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the load physical line address is allocated. The load virtual line address is a portion of the load virtual address. The store queue is configured to compare the load PAP with the store PAP held in each valid entry of the store queue for use in identifying a candidate set of entries of the store queue whose store data overlaps load data requested by the load instruction. The store queue is also configured to select an entry from the candidate set from which to forward the store data of the selected entry to the load instruction.

In another embodiment, the present disclosure provides a method performed by a microprocessor having a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries and a load unit. The method includes holding, in each entry in the store queue, information for a store instruction. The information includes store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The method also includes obtaining, by the load unit during execution of a load instruction that specifies a load virtual address, a load PAP for a load physical line address that is a translation of a load virtual line address. The load PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the load physical line address is allocated. The load virtual line address is a portion of the load virtual address. The method also includes comparing, by the store queue, the load PAP with the store PAP held in each valid entry of the store queue for use in identifying a candidate set of entries of the store queue whose store data overlaps load data requested by the load instruction. The method also includes selecting, by the store queue, an entry from the candidate set from which to forward the store data of the selected entry to the load instruction.

In yet another embodiment, the present disclosure provides a non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor. The microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. Each entry in the second-level cache is uniquely identified by a set index and a way number of the second-level cache. The microprocessor also includes a store queue of entries. Each entry in the store queue holds information for a store instruction including store data to be written to a store physical address. A portion of the store physical address is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the store physical line address is allocated. The microprocessor also includes a load unit configured to, during execution of a load instruction that specifies a load virtual address, obtain a load PAP for a load physical line address that is a translation of a load virtual line address. The load PAP specifies the set index and the way number of the entry in the second-level cache into which a cache line specified by the load physical line address is allocated. The load virtual line address is a portion of the load virtual address. The store queue is configured to compare the load PAP with the store PAP held in each valid entry of the store queue for use in identifying a candidate set of entries of the store queue whose store data overlaps load data requested by the load instruction. The store queue is also configured to select an entry from the candidate set from which to forward the store data of the selected entry to the load instruction.

DETAILED DESCRIPTION

FIG. 1is an example block diagram of a pipelined super-scalar, out-of-order execution microprocessor core100that performs speculative execution of instructions in accordance with embodiments of the present disclosure. Speculative execution of an instruction means execution of the instruction during a time when at least one instruction older in program order than the instruction has not completed execution such that a possibility exists that execution of the older instruction will result in an abort, i.e., flush, of the instruction. The core100includes a cache memory subsystem that employs physical address proxies (PAP) to attain cache coherence as described herein. Although a single core100is shown, the PAP cache coherence techniques described herein are not limited to a particular number of cores. Generally, the PAP cache coherence embodiments may be employed in a processor conforming to various instruction set architectures (ISA), including but not limited to, x86, ARM, PowerPC, SPARC, MIPS. Nevertheless, some aspects of embodiments are described with respect to the microprocessor100conforming to the RISC-V ISA, as described in specifications set forth in Volumes I and II of “The RISC-V Instruction Set Manual,” Document Version 20191213, promulgated by the RISC-V Foundation. These two volumes are herein incorporated by reference for all purposes. However, the embodiments of the PAP cache coherence techniques are not generally limited to RISC-V.

The core100has an instruction pipeline140that includes a front-end110, mid-end120, and back-end130. The front-end110includes an instruction cache101, a predict unit (PRU)102, a fetch block descriptor (FBD) FIFO104, an instruction fetch unit (IFU)106, and a fetch block (FBlk) FIFO108. The mid-end120include a decode unit (DEC)112.

The back-end130includes a level-1 (L1) data cache103, a level-2 (L2) cache107, a register files105, a plurality of execution units (EU)114, and load and store queues (LSQ)125. In one embodiment, the register files105include an integer register file, a floating-point register file and a vector register file. In one embodiment, the register files105include both architectural registers as well as microarchitectural registers. In one embodiment, the EUs114include integer execution units (IXU)115, floating point units (FXU)119, and a load-store unit (LSU)117. The LSQ125hold speculatively executed load/store micro-operations, or load/store Ops, until the Op is committed. More specifically, the load queue125holds a load operation until it is committed, and the store queue125holds a store operation until it is committed. The store queue125may also forward store data that it holds to other dependent load Ops. When a load/store Op is committed, the load queue125and store queue125may be used to check for store forwarding violations. When a store Op is committed, the store data held in the associated store queue125entry is written into the L1 data cache103at the store address held in the store queue125entry. In one embodiment, the load and store queues125are combined into a single memory queue structure rather than separate queues. The DEC112allocates an entry of the LSQ125in response to decode of a load/store instruction.

The core100also includes a memory management unit (MMU)147coupled to the IFU106and LSU117. The MMU147includes a data translation lookaside buffer (DTLB)141, an instruction translation lookaside buffer (ITLB)143, and a table walk engine (TWE)145. In one embodiment, the core100also includes a memory dependence predictor (MDP)111coupled to the DEC112and LSU117. The MDP111makes store dependence predictions that indicate whether store-to-load forwarding should be performed.

The LSU117includes a write combining buffer (WCB)109that buffers write requests sent by the LSU117to the DTLB141and to the L2 cache107. In one embodiment, the L1 data cache103is a virtually-indexed virtually-tagged write-through cache. In the case of a store operation, when there are no older operations that could cause the store operation to be aborted, the store operation is ready to be committed, and the store data is written into the L1 data cache103. The LSU117also generates a write request to “write-through” the store data to the L2 cache107and update the DTLB141, e.g., to set a page dirty, or page modified, bit. The write request is buffered in the WCB109. Eventually, at a relatively low priority, the store data associated with the write request will be written to the L2 cache107. However, entries of the write combining buffer109are larger (e.g., 32 bytes) than the largest load and store operations (e.g., eight bytes). When possible, the WCB109merges, or combines, multiple write requests into a single entry of the WCB109such that the WCB109may make a potentially larger single write request to the L2 cache107that encompasses the store data of multiple store operations that have spatially-locality. The merging, or combining, is possible when the starting physical memory address and size of two or more store operations align and fall within a single entry of the WCB109. For example, assume a first 8-byte store operation to 32-byte aligned physical address A, a second 4-byte store operation to physical address A+8, a third 2-byte store operation to physical address A+12, and a fourth 1-byte store operation to physical address A+14. The WCB109may combine the four store operations into a single entry and perform a single write request to the L2 cache107of the fifteen bytes at address A. By combining write requests, the WCB109may free up bandwidth of the L2 cache107for other requests, such as cache line fill requests from the L1 data cache103to the L2 cache107or snoop requests.

The microprocessor110may also include other blocks not shown, such as a load buffer, a bus interface unit, and various levels of cache memory above the instruction cache101and L1 data cache103and L2 cache107, some of which may be shared by other cores of the processor. Furthermore, the core100may be multi-threaded in the sense that it includes the ability to hold architectural state (e.g., program counter, architectural registers) for multiple threads that share the back-end130, and in some embodiments the mid-end120and front-end110, to perform simultaneous multithreading (SMT).

The core100provides virtual memory support. Each process, or thread, running on the core100may have its own address space identified by an address space identifier (ASID). The core100may use the ASID to perform address translation. For example, the ASID may be associated with the page tables, or translation tables, of a process. The TLBs (e.g., DTLB141and ITLB143) may include the ASID in their tags to distinguish entries for different processes. In the x86 ISA, for example, an ASID may correspond to a processor context identifier (PCID). The core100also provides machine virtualization support. Each virtual machine running on the core100may have its own virtual machine identifier (VMID). The TLBs may include the VMID in their tags to distinguish entries for different virtual machines. Finally, the core100provides different privilege modes (PM), or privilege levels. The PM of the core100determines, among other things, whether or not privileged instructions may be executed. For example, in the x86 ISA there are four PMs, commonly referred to as Ring0through Ring3. Ring0is also referred to as Supervisor level and Ring3is also referred to as User level, which are the two most commonly used PMs. For another example, in the RISC-V ISA, PMs may include Machine (M), User (U), Supervisor (S) or Hypervisor Supervisor (HS), Virtual User (VU), and Virtual Supervisor (VS). In the RISC-V ISA, the S PM exists only in a core without virtualization supported or enabled, whereas the HS PM exists when virtualization is enabled, such that S and HS are essentially non-distinct PMs. For yet another example, the ARM ISA includes exception levels (EL0, EL1, EL2 and EL3).

As used herein and as shown inFIG. 1, a translation context (TC) of the core100(or of a hardware thread in the case of a multi-threaded core) is a function of the ASID, VMID, and/or PM or a translation regime (TR), which is based on the PM. In one embodiment, the TR indicates whether address translation is off (e.g., M mode) or on, whether one level of address translation is needed (e.g., U mode, S mode and HS mode) or two levels of address translation is needed (VU mode and VS mode), and what form of translation table scheme is involved. For example, in a RISC-V embodiment, the U and S privilege modes (or U and HS, when the hypervisor extension is active) may share a first TR in which one level of translation is required based on the ASID, VU and VS share a second TR in which two levels of translation are required based on the ASID and VMID, and M privilege level constitutes a third TR in which no translation is performed, i.e., all addresses are physical addresses.

Pipeline control logic (PCL)132is coupled to and controls various aspects of the pipeline140which are described in detail herein. The PCL132includes a ReOrder Buffer (ROB)122, interrupt handling logic149, abort and exception-handling logic134, and control and status registers (CSR) 123. The CSRs123hold, among other things, the PM199, VMID197, and ASID195of the core100, or one or more functional dependencies thereof (such as the TR and/or TC). In one embodiment (e.g., in the RISC-V ISA), the current PM199does not reside in a software-visible CSR123; rather, the PM199resides in a microarchitectural register. However, the previous PM199is readable by a software read of a CSR123in certain circumstances, such as upon taking of an exception. In one embodiment, the CSRs123may hold a VMID197and ASID195for each TR or PM.

The pipeline units may signal a need for an abort, as described in more detail below, e.g., in response to detection of a mis-prediction (e.g., by a branch predictor of a direction or target address of a branch instruction, or of a mis-prediction that store data should be forwarded to a load Op in response to a store dependence prediction, e.g., by the MDP111) or other microarchitectural exception, architectural exception, or interrupt. Examples of architectural exceptions include an invalid opcode fault, debug breakpoint, or illegal instruction fault (e.g., insufficient privilege mode) that may be detected by the DEC112, a page fault, permission violation or access fault that may be detected by the LSU117, and an attempt to fetch an instruction from a non-executable page or a page the current process does not have permission to access that may be detected by the IFU106. In response, the PCL132may assert flush signals to selectively flush instructions/Ops from the various units of the pipeline140. Conventionally, exceptions are categorized as either faults, traps, or aborts. The term “abort” as used herein is not limited by the conventional categorization of exceptions. As used herein, “abort” is a microarchitectural mechanism used to flush instructions from the pipeline140for many purposes, which encompasses interrupts, faults and traps. Purposes of aborts include recovering from microarchitectural hazards such as a branch mis-prediction or a store-to-load forwarding violation. The microarchitectural abort mechanism may also be used to handle architectural exceptions and for architecturally defined cases where changing the privilege mode requires strong in-order synchronization. In one embodiment, the back-end130of the processor100operates under a single PM, while the PM for the front-end110and mid-end120may change (e.g., in response to a PM-changing instruction) while older instructions under an older PM continue to drain out of the back-end130. Other blocks of the core100, e.g., DEC112, may maintain shadow copies of various CSRs123to perform their operations.

The PRU102maintains the program counter (PC) and includes predictors that predict program flow that may be altered by control flow instructions, such as branch instructions. In one embodiment, the PRU102includes a next index predictor (NIP), a branch target buffer (BTB), a main conditional branch predictor (CBP), a secondary conditional branch predictor (BMP), an indirect branch predictor (IBP), and a return address predictor (RAP). As a result of predictions made by the predictors, the core100may speculatively execute instructions in the instruction stream of the predicted path.

The PRU102generates fetch block descriptors (FBD) that are provided to the FBD FIFO104in a first-in-first-out manner. Each FBD describes a fetch block (FBlk or FB). An FBlk is a sequential set of instructions. In one embodiment, an FBlk is up to sixty-four bytes long and may contain as many as thirty-two instructions. An FBlk ends with either a branch instruction to be predicted, an instruction that causes a PM change or that requires heavy abort-based synchronization (aka “stop” instruction), or an indication that the run of instructions continues sequentially into the next FBlk. An FBD is essentially a request to fetch instructions. An FBD may include the address and length of an FBlk and an indication of the type of the last instruction. The IFU106uses the FBDs to fetch FBlks into the FBlk FIFO108, which feeds fetched instructions to the DEC112. The FBD FIFO104enables the PRU102to continue predicting FBDs to reduce the likelihood of starvation of the IFU106. Likewise, the FBlk FIFO108enables the IFU106to continue fetching FBlks to reduce the likelihood of starvation of the DEC112. The core100processes FBlks one at a time, i.e., FBlks are not merged or concatenated. By design, the last instruction of an FBlk can be a branch instruction, a privilege-mode-changing instruction, or a stop instruction. Instructions may travel through the pipeline140from the IFU106to the DEC112as FBlks, where they are decoded in parallel.

The DEC112decodes architectural instructions of the FBlks into micro-operations, referred to herein as Ops. The DEC112dispatches Ops to the schedulers121of the EUs114. The schedulers121schedule and issue the Ops for execution to the execution pipelines of the EUs, e.g., IXU115, FXU119, LSU117. The EUs114receive operands for the Ops from multiple sources including: results produced by the EUs114that are directly forwarded on forwarding busses—also referred to as result busses or bypass busses—back to the EUs114and operands from the register files105that store the state of architectural registers as well as microarchitectural registers, e.g., renamed registers. In one embodiment, the EUs114include four IXU115for executing up to four Ops in parallel, two FXU119, and an LSU117that is capable of executing up to four load/store Ops in parallel. The instructions are received by the DEC112in program order, and entries in the ROB122are allocated for the associated Ops of the instructions in program order. However, once dispatched by the DEC112to the EUs114, the schedulers121may issue the Ops to the individual EU114pipelines for execution out of program order.

The PRU102, IFU106, DEC112, and EUs114, along with the intervening FIFOs104and108, form a concatenated pipeline140in which instructions and Ops are processed in mostly sequential stages, advancing each clock cycle from one stage to the next. Each stage works on different instructions in parallel. The ROB122and the schedulers121together enable the sequence of Ops and associated instructions to be rearranged into a data-flow order and to be executed in that order rather than program order, which may minimize idling of EUs114while waiting for an instruction requiring multiple clock cycles to complete, e.g., a floating-point Op or cache-missing load Op.

Many structures within the core100address, buffer, or store information for an instruction or Op by reference to an FBlk identifier. In one embodiment, checkpoints for abort recovery are generated for and allocated to FBlks, and the abort recovery process may begin at the first instruction of the FBlk containing the abort-causing instruction.

In one embodiment, the DEC112converts each FBlk into a series of up to eight OpGroups. Each OpGroup consists of either four sequential Ops or, if there are fewer than four Ops in the FBlk after all possible four-op OpGroups for an FBlk have been formed, the remaining Ops of the FBlk. Ops from different FBlks are not concatenated together into the same OpGroup. Because some Ops can be fused from two instructions, an OpGroup may correspond to up to eight instructions. The Ops of the OpGroup may be processed in simultaneous clock cycles through later DEC112pipe stages, including rename and dispatch to the EU114pipelines. In one embodiment, the MDP111provides up to four predictions per cycle, each corresponding to the Ops of a single OpGroup. Instructions of an OpGroup are also allocated into the ROB122in simultaneous clock cycles and in program order. The instructions of an OpGroup are not, however, necessarily scheduled for execution together.

In one embodiment, each of the EUs114includes a dedicated scheduler121. In an alternate embodiment, a scheduler121common to all the EUs114(and integrated with the ROB122according to one embodiment) serves all the EUs114. In one embodiment, each scheduler121includes an associated buffer (not shown) that receives Ops dispatched by the DEC112until the scheduler121issues the Op to the relevant EU114pipeline for execution, namely when all source operands upon which the Op depends are available for execution and an EU114pipeline of the appropriate type to execute the Op is available.

The PRU102, IFU106, DEC112, each of the execution units114, and PCL132, as well as other structures of the core100, may each have their own pipeline stages in which different operations are performed. For example, in one embodiment, the DEC112has a pre-decode stage, an extract stage, a rename stage, and a dispatch stage.

The PCL132tracks instructions and the Ops into which they are decoded throughout their lifetime. The ROB122supports out-of-order instruction execution by tracking Ops from the time they are dispatched from DEC112to the time they retire. In one embodiment, the ROB122has entries managed as a FIFO, and the ROB122may allocate up to four new entries per cycle at the dispatch stage of the DEC112and may deallocate up to four oldest entries per cycle at Op retire. In one embodiment, each ROB entry includes an indicator that indicates whether the Op has completed its execution and another indicator that indicates whether the result of the Op has been committed to architectural state. More specifically, load and store Ops may be committed subsequent to completion of their execution. Still further, an Op may be committed before it is retired.

Embodiments of a cache subsystem are described herein that advantageously enable cache coherency attainment with higher performance and/or reduced size using PAPs.

FIG. 2is an example block diagram of a cache entry201of L1 data cache103ofFIG. 1that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The L1 data cache entry201is used in the L1 data cache103embodiment ofFIG. 3described in more detail below. The L1 data cache entry201includes cache line data202, a virtual address tag204, a status field206, a hashed tag field208, and a diminutive physical address proxy (dPAP) field209. The cache line data202is the copy of the data brought into the L1 data cache103from system memory indirectly through a higher level of the cache memory hierarchy, namely the L2 cache107.

The tag204is upper bits (e.g., tag bits322ofFIG. 3) of the virtual memory address (e.g., virtual load/store address321ofFIG. 3) specified by the operation that brought the cache line into the L1 data cache103, e.g., the virtual memory address specified by a load/store operation. That is, when an entry201in the L1 data cache103is allocated, the tag bits322of the virtual memory address321are written to the virtual address tag204of the entry201. When the L1 data cache103is subsequently accessed (e.g., by a subsequent load/store operation), the virtual address tag204is used to determine whether the access hits in the L1 data cache103. Generally speaking, the L1 data cache103uses lower bits (e.g., set index bits326ofFIG. 3) of the virtual memory address to index into the L1 data cache103and uses the remaining bits of the virtual address321above the set index bits326as the tag bits. To illustrate by way of example, assume a 64 kilobyte (KB) L1 data cache103arranged as a 4-way set associative cache having 64-byte cache lines; address bits [5:0] are an offset into the cache line, virtual address bits [13:6] (set index bits) are used as the set index, and virtual address bits [N−1:14] (tag bits) are used as the tag, where N is the number of bits of the virtual memory address, where N is 63 in the embodiment ofFIG. 3.

The status206indicates the state of the cache line. More specifically, the status206indicates whether the cache line data is valid or invalid. Typically, the status206also indicates whether the cache line has been modified since it was brought into the L1 data cache103. The status206may also indicate whether the cache line is exclusively held by the L1 data cache103or whether the cache line is shared by other cache memories in the system. An example protocol used to maintain cache coherency defines four possible states for a cache line: Modified, Exclusive, Shared, Invalid (MESI).

The hashed tag208may be a hash of the tag bits322ofFIG. 3of the virtual memory address321, as described in more detail below. Advantageously, the hashed tag208may be used to generate a predicted early miss indication, e.g., miss328ofFIG. 3, and may be used to generate a predicted early way select signal, e.g., way select342ofFIG. 3, as described in more detail with respect toFIG. 3.

The dPAP209is all or a portion of a physical address proxy (PAP), e.g., PAP699ofFIG. 6. As described herein, the L2 cache107is inclusive of the L1 data cache103. That is, each cache line of memory allocated into the L1 data cache103is also allocated into the L2 cache107, and when the L2 cache107evicts the cache line, the L2 cache107also causes the L1 data cache103to evict the cache line. A PAP is a forward pointer to the unique entry in the L2 cache107(e.g., L2 entry401ofFIG. 4) that holds a copy of the cache line held in the entry201of the L1 data cache103. For example, in the embodiments ofFIGS. 6 and 9, the dPAP209is the PAP less the untranslated physical address PA[11:6] bits that are used in the L1 set index. That is, the dPAP is the L2 way and the translated physical address bits PA[16:12] of the set index of the L2 cache107set containing the entry401that holds the copy of the L1 data cache103cache line. For another example, in the embodiment ofFIG. 11, the dPAP is the entire PAP, e.g., all the bits of the L2 way and L2 set index that point to the entry401in the L2 cache107that holds the copy of the L1 data cache103cache line. Uses of the dPAP209and PAP are described in more detail herein.

FIG. 3is an example block diagram illustrating the L1 data cache103ofFIG. 1that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. In the embodiment ofFIG. 3, the L1 data cache103is a virtual cache, i.e., it is virtually-indexed and virtually-tagged. In the embodiment ofFIG. 3, the DTLB141ofFIG. 1is a second-level TLB, and the processor100includes no first-level TLB. The L1 data cache103includes a tag array332, a data array336, a hashed tag array334, a multiplexer342, a comparator344, a multiplexer346, and tag hash logic312. The LSU117generates a virtual load/store address VA[63:0] and provides to the L1 data cache103a portion thereof VA[63:6]321used to specify a line of memory that may be stored in the L1 data cache103. The virtual address321includes a tag322portion (e.g., bits [63:14]) and a set index326portion (e.g., bits [13:6]). The L1 data cache103also includes an allocate way input308for allocating an entry into the L1 data cache103. The L1 data cache103also includes a data in input325for writing data into the L1 data cache103, e.g., during a store operation and during a cache line allocation.

The L1 data cache103also includes a hit output352, early miss prediction328, and a data out output227. The tag array332and data array336are random access memory arrays. In the embodiment ofFIG. 3, the L1 data cache103is arranged as a 4-way set associative cache; hence, the tag array332and data array336are arranged as 4-way set associative memory arrays. However, other embodiments are contemplated in which the associativity has a different number of ways than four, including direct-mapped and fully associative embodiments. The set index326selects the set of entries on each allocation or access, e.g., load/store operation.

In the embodiment ofFIG. 3, each entry of the L1 data cache103is structured as the entry201ofFIG. 2, having cache line data202, a tag204, a status206, a hashed tag208, and a dPAP209. The data array336holds the cache line data202associated with each of the entries201of the L1 data cache103. The tag array332holds the tag204associated with each of the entries201of the L1 data cache103. The hashed tag array334, also referred to as a hashed address directory334, holds the hashed tag208and dPAP209associated with each of the entries201of the L1 data cache103. In one embodiment, the status206of each entry is also stored in the tag array332, whereas in another embodiment the L1 data cache103includes a separate memory array for storing the status206of the entries. Although in the embodiment ofFIG. 3the data array336and tag array332are separate, other embodiments are contemplated in which the data and tag (and status) reside in the same memory array.

The tag hash logic312hashes the tag322portion of the virtual load/store address321to generate the hashed tag324. That is, the tag322is an input to a hash function performed by tag hash logic312that outputs the hashed tag324. The hash function performs a logical and/or arithmetic operation on its input bits to generate output bits. For example, in one embodiment, the hash function is a logical exclusive-OR on at least a portion of the tag322bits. The number of output bits of the hash function is the size of the hashed tag324and the hashed tag field208of the data cache entry201. The hashed tag324is provided as an input to the hashed tag array334for writing into the hashed tag208of the selected entry201of the hashed tag array334, e.g., during an allocation. Similarly, a dPAP323obtained from the L2 cache107during an allocation (as described with respect toFIG. 7) are written into the dPAP209of the selected entry201of the hashed tag array334during an allocation. The set index326selects the set of entries of the hashed tag array334. In the case of an allocation, the hashed tag324and dPAP323are written into the hashed tag208and dPAP209of the entry201of the way selected by an allocate way input308of the selected set. In the case of an access, comparator348compares the hashed tag324with each of the hashed tags208of the selected set. If there is a valid match, the early miss signal328is false and the way select341indicates the matching way; otherwise, the early miss signal328is true. Although it may not be used to execute a load/store operation, the dPAP323stored in the dPAP field202of the L1 entry201is used to process a snoop request to attain cache coherency, as described in more detail with respect toFIGS. 6 through 12.

Because the hashed tag324and the hashed tags208are small (e.g., 16 bits as an illustrative example) relative to the tag322and tags204(e.g., 54 bits as an illustrative example), the comparison performed by comparator348may be faster than the comparison performed by comparator344(described more below), for example. Therefore, the way select341may be signaled by an earlier stage in the L1 data cache103pipeline than an embodiment that relies on a comparison of the tags204of the tag array332to generate a way select. This may be advantageous because it may shorten the time to data out227.

Additionally, the early miss prediction328may be signaled by an earlier stage than the stage that signals the hit indicator352. This may be advantageous because it may enable a cache line fill requestor (not shown) to generate a cache line fill request to fill a missing cache line earlier than an embodiment that would rely on a comparison of the tags204in the tag array332to detect a miss. Thus, the hashed tag array334may enable a high performance, high frequency design of the processor100.

It is noted that due to the nature of the hashed tag324, if the early miss indicator328indicates a false value, i.e., indicates a hit, the hit indication may be incorrect, i.e., the hit indicator352may subsequently indicate a false value, i.e., a miss. Thus, the early miss indicator328is a prediction, not necessarily a correct miss indicator. This is because differing tag322values may hash to the same value. However, if the early miss indicator328indicates a true value, i.e., indicates a miss, the miss indication is correct, i.e., the hit indicator352will also indicate a miss, i.e., will indicate a false value. This is because if two hash results are not equal (assuming they were hashed using the same hash algorithm), then they could not have been generated from equal inputs, i.e., matching inputs.

The tag322is provided as an input to the tag array332for writing into the tag204field of the selected entry of the tag array332, e.g., during an allocation. The set index326selects the set of entries of the tag array332. In the case of an allocation, the tag322is written into the tag204of the entry of the way selected by the allocate way input308of the selected set. In the case of an access (e.g., a load/store operation), the mux342selects the tag204of the way selected by the early way select341, and the comparator344compares the tag322with the tag204of the selected set. If there is a valid match, the hit signal352is true; otherwise, the hit signal352is false. In one embodiment, the cache line fill requestor advantageously uses the early miss prediction328provided by the hashed tag array334in order to generate a fill request as soon as possible, rather than waiting for the hit signal352. However, in embodiments of the LSU117that employ the L1 data cache103ofFIG. 3, the cache line fill requestor is also configured to examine both the early miss prediction328and the hit indicator352, detect an instance in which the early miss prediction328predicted a false hit, and generate a fill request accordingly.

The data array336receives the data in input325for writing into the cache line data202field of the selected entry of the data array336, e.g., during a cache line allocation or a store operation. The set index326selects the set of entries of the data array336. In the case of an allocation, the way of the selected set is selected by the allocate way input308, and in the case of a memory access operation (e.g., load/store operation) the way is selected by the way select signal341. In the case of a read operation (e.g., load operation), the mux346receives the cache line data202of all four ways and selects one of the ways based on the way select signal341, and the cache line data202selected by the mux346is provided on the data out output227.

FIG. 4is an example block diagram of a cache entry401of L2 cache107ofFIG. 1that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The L2 cache entry401is used in the physically-indexed physically-tagged L2 cache107embodiment ofFIG. 5described in more detail below. That is, the tag field404holds a physical address tag, rather than a virtual address tag. Also, the cache entry401ofFIG. 4does not include a hashed tag field208nor a dPAP field209as inFIG. 2. Otherwise, the cache entry401ofFIG. 4is similar in many respects to the cache entry201ofFIG. 2, e.g., the status field406is similar to the status field206ofFIG. 2.

FIG. 5is an example block diagram illustrating the L2 cache107ofFIG. 1that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The DTLB141ofFIG. 1receives the virtual load/store address321ofFIG. 2and provides to the L2 cache107a physical memory line address PA[51:6]521that is the translation of the virtual load/store address321. More specifically, physical memory line address521bits PA[51:12] are translated from the virtual load/store address321bits [63:12]. The physical memory line address521comprises a tag522portion and a set index526portion. In some respects, the L2 cache107ofFIG. 5is similar and operates similarly to the L1 data cache103ofFIG. 3in that it analogously includes a tag array532, a data array536, a comparator544, a multiplexer546, an allocate way input508for allocating an entry into the L2 cache107, and a data in input525for writing data into the L2 cache107. However, the L2 cache107does not analogously include the tag hash logic312, hashed tag array334, comparator348, nor multiplexer342ofFIG. 3. The L2 cache107is physically-indexed and physically-tagged. That is, tag522is the tag portion (e.g., bits [51:17]) of the physical memory line address521, and the set index526is the index portion (e.g., bits [16:6]) of the physical memory line address521. Finally, the comparator544compares the tag522with the tag404of all ways of the selected set. If there is a valid match, the hit signal552is true and a way select signal542, which indicates the matching way, is provided to mux546; otherwise, the hit signal552is false. As described herein, a cache line of memory associated with a physical memory line address can only reside in one entry401of the L2 cache107, and a PAP points to the one entry401of the L2 cache107that holds the copy of the cache line associated with the physical memory line address for the which the PAP is a proxy.

FIG. 6is an example block diagram of a cache subsystem600that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The cache subsystem600includes the L2 cache107ofFIG. 5that includes entries401ofFIG. 4and the L1 data cache103ofFIG. 3that includes entries201ofFIG. 2. The cache subsystem600has an inclusive allocation policy such that each cache line of memory allocated into the L1 data cache103is also allocated into the L2 cache107, and when the L2 cache107evicts the cache line, the L2 cache107also causes the L1 data cache103to evict the cache line. Because the L2 cache107is a physically-indexed physically-tagged cache, a cache line of memory may reside only in a single entry of the L2 cache107. As described herein, each valid L1 entry201of the L1 data cache103includes a field, referred to as the dPAP209ofFIG. 2. The dPAP209, along with relevant bits of the L1 set index used to select the set of the L1 data cache103that includes the L1 entry201, points to the entry401of the L2 cache107that holds a copy of the cache line of memory allocated into the L1entry201. The dPAP209along with the relevant bits of the L1 set index are referred to herein as the physical address proxy (PAP)699ofFIG. 6, which may be considered a forward pointer to the L2 cache107that holds a copy of the cache line of memory allocated into the L1 entry201. The PAP699is used to accomplish cache coherency in a more efficient manner, both in terms of timing and storage space, than using a full physical memory line address to accomplish cache coherency, as described herein. The inclusive allocation policy is further described with respect toFIG. 7.

In the embodiment ofFIG. 6, the L2 cache107is a 512 KB 4-way set associative cache memory whose entries each store a 64-byte cache line. Thus, the L2 cache107includes an 11-bit L2 set index602that receives physical address bits PA[16:6] to select one of 2048 sets. However, other embodiments are contemplated in which the L2 cache107has a different cache line size, different set associativity, and different size. In the embodiment ofFIG. 6, the L1 data cache103is a 64 KB 4-way set associative cache memory whose entries each store a 64-byte cache line. Thus, the L1 data cache103includes an 8-bit L1 set index612to select one of 256 sets. However, other embodiments are contemplated in which the L1 data cache103has a different cache line size, different set associativity, and different size. In the embodiment ofFIG. 6, the lower six bits [5:0] of the L1 set index612receive physical address bits PA[11:6]. The upper two bits [7:6] are described in more detail below. In particular, in the example ofFIG. 6, the lower six bits [5:0] of the L1 set index612correspond to untranslated virtual address bits VA[11:6] that are mathematically equivalent to untranslated physical address bits PA[11:6] which correspond to the lower six bits [5:0] of the L2 set index602.

FIG. 6illustrates aspects of processing of a snoop request601by the cache subsystem600, which is also described inFIG. 8, to ensure cache coherency between the L2 cache107, L1 data cache103and other caches of a system that includes the core100ofFIG. 1, such as a multi-processor or multi-core system. The snoop request601specifies a physical memory line address PA[51:6], of which PA[16:6] correspond to the L2 set index602to select a set of the L2 cache107. Comparators604compare a tag portion603of the snoop request601against the four tags605of the selected set. The tag portion603corresponds to physical address bits PA[51:17]. Each of the four tags605is tag404ofFIG. 4, which is the physical address bits PA[51:17] stored during an allocation into the L2 cache107. If there is a tag match of a valid entry401, the hit entry401is indicated on an L2way number606, which is preferably a two-bit value encoded to indicate one of four ways, which is provided to snoop forwarding logic607. The snoop forwarding logic607forwards the snoop request601to the L1 data cache103as forwarded snoop request611.

The forwarded snoop request611is similar to the snoop request601except that the physical memory line address PA[51:6] is replaced with the PAP699. The PAP699points to the snoop request601hit entry401in the L2 cache107. That is, the PAP699is the physical address bits PA[16:6] that select the set of the L2 cache107that contains the hit entry401combined with the L2way number606of the hit entry401. The PAP699is significantly fewer bits than the physical memory line address PA[51:6], which may provide significant advantages such as improved timing and reduced storage requirements, as described in more detail below. In the embodiment ofFIG. 6, the PAP699is thirteen bits, whereas the physical memory line address is 46 bits, for a saving of 33 bits per entry of the L1 data cache103, although other embodiments are contemplated in which the different bit savings are enjoyed.

In the embodiment ofFIG. 6, the untranslated address bits PA[11:6] are used as the lower six bits [5:0] of the L1 set index612. During a snoop request, the upper two bits [7:6] of the L1 set index612are generated by the L1 data cache103. More specifically, for the upper two bits [7:6] of the L1 set index612, the L1 data cache103generates all four possible combinations of the two bits. Thus, four sets of the L1 data cache103are selected in the embodiment ofFIG. 6. The upper two bits [7:6] of the L1 set index612for processing of the forwarded snoop request611correspond to virtual address bits VA[13:12] of a load/store address during an allocation or lookup operation. Comparators614compare a dPAP613portion of the PAP699of the forwarded snoop request611against the dPAPs209of each entry201of each way of each of the four selected sets of the L1 data cache103. In the embodiment ofFIG. 6, sixteen dPAPs209are compared. The dPAP613portion of the PAP699is physical address bits PA[16:12] used to select the set of the L2 cache107that contains the hit entry401combined with the L2way number606of the hit entry401. The sixteen dPAPs209are the dPAPs209of the sixteen selected entries201. If there is a dPAP match of one or more valid entries201, the hit entries201are indicated on an L1 hit indicator616, received by control logic617, that specifies each way of each set having a hit entry201. Because the L1 data cache103is a virtually-indexed virtually-tagged cache, it may be holding multiple copies of the cache line being snooped and may therefore detect multiple snoop hits. In one embodiment, the L1 hit indicator616comprises a 16-bit vector. The control logic617uses the L1 hit indicator616to reply to the L2 cache107, e.g., to indicate a miss or to perform an invalidation of each hit entry201, as well as a write back of any modified cache lines to memory.

In one embodiment, the multiple sets (e.g., four sets in the embodiment ofFIG. 6) are selected in a time sequential fashion as are the tag comparisons performed by the comparators614. For example, rather than having four set index inputs612as shown inFIG. 6, the L1 data cache103may have a single set index input612, and each of the four L1 set index values corresponding to the four different possible values of the two VA[13:12] bits are used to access the L1 data cache103in a sequential fashion, e.g., over four different clock cycles, e.g., in a pipelined fashion. Such an embodiment may have the advantage of less complex hardware in exchange for potentially reduced performance.

The smaller PAP (i.e., smaller than the physical memory line address PA[51:6]), as well as even smaller dPAPs, may improve timing because the comparisons that need to be performed (e.g., by comparators614) are considerably smaller than conventional comparisons. To illustrate, assume a conventional processor whose first-level data cache stores and compares physical address tags, e.g., approximately forty bits. In contrast, the comparisons of dPAPs may be much smaller, e.g., seven bits in the embodiment ofFIG. 6. Thus, the comparisons made by the comparators614of the embodiment ofFIG. 6may be approximately an order of magnitude smaller and therefore much faster than a conventional processor, which may improve the cycle time for a processor that compares dPAPs rather than full physical addresses. Second, there may be a significant area savings due to less logic, e.g., smaller comparators, and less storage elements, e.g., seven bits to store a dPAP in an L1 cache entry201rather than a large physical address tag. Still further, the much smaller dPAP comparisons may be sufficiently faster and smaller to make feasible an embodiment in which the comparisons of the ways of multiple selected sets are performed in parallel (e.g., sixteen parallel comparisons in the embodiment ofFIG. 6). Finally, the smaller PAPs may further improve timing and area savings in other portions of the core100in which PAPs may be used in place of physical memory line addresses for other purposes, such as in entries of the load/store queue125for making decisions whether to perform a speculative store-to-load forward operation and for performing store-to-load forwarding violation checking at load/store commit time, or in entries of the write combine buffer109to determine whether store data of multiple store operations may be combined in an entry of the write combine buffer109.

FIG. 7is an example flowchart illustrating operation of the cache subsystem600ofFIG. 6to process a miss in the L1 data cache103in furtherance of an inclusive cache policy in accordance with embodiments of the present disclosure. Operation begins at block702.

At block702, a virtual address (e.g., VA321ofFIG. 2of a load/store operation) misses in the L1 data cache103. In response, the cache subsystem600generates a cache line fill request to the L2 cache107. The fill request specifies a physical address that is a translation of the missing virtual address obtained from the DTLB141ofFIG. 1, which obtains the physical address from the TWE145ofFIG. 1if the physical address is missing in the DTLB141. Operation proceeds to block704.

At block704, the L2 cache107looks up the physical address to obtain the requested cache line that has been allocated into the L2 cache107. (If the physical address is missing, the L2 cache107fetches the cache line at the physical address from memory (or from another cache memory higher in the cache hierarchy) and allocates the physical address into an entry401of the L2 cache107.) The L2 cache107then returns a copy of the cache line to the L1 data cache103as well as the dPAP (e.g., dPAP323ofFIG. 3) of the entry401of the L2 cache107into which the cache line is allocated. The L1 data cache103writes the returned cache line and dPAP into the respective cache line data202and dPAP209ofFIG. 2of the allocated entry201. Operation proceeds to block706.

At block706, at some time later, when the L2 cache107subsequently evicts its copy of the cache line (e.g., in response to a snoop request or when the L2 cache107decides to replace the entry401and allocate it to a different physical address), the L2 cache107also causes the L1 data cache103to evict its copy of the cache line. Thus, in the manner ofFIG. 7, the L2 cache107is inclusive of the L1 data cache103. Stated alternatively, as long as the cache line remains in the L1 data cache103, the L2 cache107also keeps its copy of the cache line.

FIG. 8is an example flowchart illustrating operation of the cache subsystem600ofFIG. 6to process a snoop request in accordance with embodiments of the present disclosure. Operation begins at block802.

At block802, a physically-indexed physically-tagged set associative L2 cache (e.g., L2 cache107ofFIG. 6) that is inclusive of a lower-level data cache (e.g., L1 data cache103ofFIG. 6) receives a snoop request (e.g., snoop request601) that specifies a physical memory line address. Operation proceeds to block804.

At block804, the L2 cache107determines whether the physical memory line address hits in any of its entries401. If so, operation proceeds to block806; otherwise, operation proceeds to block805at which the L2 cache107does not forward the snoop request to the L1 data cache103.

At block806, the snoop request is forwarded to the L1 data cache103, e.g., as a forwarded snoop request (e.g., forwarded snoop request611). The forwarded snoop request replaces the physical memory line address of the original snoop request (e.g., PA[51:6] ofFIG. 6) with the PAP (e.g., PAP699ofFIG. 6) of the entry401of the L2 cache107that was hit, i.e., the way number (e.g., L2way606ofFIG. 6) and the set index (e.g., L2 set index602ofFIG. 6) that together point to the hit entry401of the L2 cache107. Operation proceeds to block808.

At block808, the L1 data cache103uses N bits of the PAP (e.g., N=6 untranslated address bits such as PA[11:6] ofFIG. 6) as lower set index bits to select one or more (S) sets of the L1 data cache103. As described above with respect toFIG. 6, for the upper bits of the set index (e.g., two upper bits inFIG. 6), the L1 data cache103generates all possible combinations of the upper bits. The upper bits correspond to translated virtual address bits that are used to allocate into the L1 data cache103, e.g., during a load/store operation (e.g., VA [13:12]321ofFIG. 3). The L1 data cache103also uses the remaining bits of the PAP (i.e., not used in the L1 set index), which is the dPAP613portion of the PAP699ofFIG. 6, to compare against the dPAPs209stored in each valid entry201of the selected sets to determine whether any snoop hits occurred in the L1 data cache103in response to the forwarded snoop request (e.g., as indicated on Llhit indicator616ofFIG. 6). To process the forwarded snoop request, the L1 data cache103also performs an invalidation of each hit entry201as well as a write back of any modified cache lines to memory.

FIG. 9is an example block diagram of a cache subsystem900that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The cache subsystem900ofFIG. 9is similar in many respects to the cache subsystem600ofFIG. 6. However, in the cache subsystem900ofFIG. 9, to process the forwarded snoop request611, a single set of the L1 data cache103is selected rather than multiple sets. More specifically, the L1 data cache103uses untranslated bits (e.g., PA[11:6]) of the PAP699of the forwarded snoop request611that correspond to all bits of the L1 set index912to select a single set; the dPAP613is then used by comparators614to compare with the dPAPs209stored in each of the four ways of the single selected set to determine whether any snoop hits occurred in entries201of the L1 data cache103in response to the forwarded snoop request as indicated on L1hit indicator916, as described in block1008ofFIG. 10in which operation flows to block1008from block806ofFIG. 8(rather than to block808). In one embodiment, the L1 hit indicator616comprises a 4-bit vector. The embodiment ofFIG. 9may be employed when the L1 data cache103is sufficiently small and its cache lines size and set associative arrangement are such that the number of set index bits912are less than or equal to the number of untranslated address bits (excluding the cache line offset bits) such that corresponding bits of the L1 and L2 set indices correspond to untranslated address bits of the L1 data cache103virtual address321and the L2 cache107physical memory line address521such that a single set of the L1 data cache103may be selected to process a snoop request. For example, in the embodiment ofFIG. 9, the L1 data cache103is a 16 KB cache memory having 4 ways that each store a 64-byte cache line; therefore, the L1 data cache103has 64 sets requiring a set index912of 6 bits that correspond to untranslated virtual address bits VA[11:6] that are mathematically equivalent to untranslated physical address bits PA[11:6] that correspond to the lower 6 bits of the L2 set index602.

FIG. 11is an example block diagram of a cache subsystem1100that employs PAPs to accomplish cache coherence in accordance with embodiments of the present disclosure. The cache subsystem1100ofFIG. 11is similar in many respects to the cache subsystem600ofFIG. 6. However, in the cache subsystem1100ofFIG. 11, all bits of the PAP699are used as the dPAP1113for processing snoop requests. More specifically, the dPAP209stored in an allocated entry of the L1 data cache103(e.g., at block704ofFIG. 7) is the full PAP, no bits of the PAP699are used in the L1 set index1112to select sets to process a forwarded snoop request611, and all bits of the PAP699provided by the forwarded snoop request611, i.e., the dPAP1113, are used by comparators614to compare with the dPAP209stored in the entries201of the L1 data cache103. That is, in the embodiment ofFIG. 11, the dPAP and the PAP are equivalent. Furthermore, in the embodiment ofFIG. 11, all bits of the PAP stored in the dPAP field209ofFIG. 2of all sets of the L1 data cache103are compared by comparators614with the dPAP1113, which is the PAP699of the forwarded snoop request611, and the L1hit indicator1116specifies the hit entries201, as described in block1208ofFIG. 12in which operation flows to block1208from block806ofFIG. 8(rather than to block808). In one embodiment, the L1 hit indicator1116comprises a 1024-bit vector.

The embodiment ofFIG. 11may be employed when the address bits that correspond to the set index326used to access the L1 data cache103during an allocation operation (e.g., load/store operation) are not mathematically equivalent to the address bits that correspond to the set index526used to access the L2 cache107. For example, the address bits that correspond to the set index326used to access the L1 data cache103during an allocation operation may be virtual address bits and/or a hash of virtual address bits or other bits such as a translation context of the load/store operation.

The embodiments described herein may enjoy the following advantages. First, the use of PAPs may improve timing because the comparisons that need to be performed are considerably smaller than conventional comparisons. To illustrate, assume a conventional processor that compares physical memory line address tags, e.g., on the order of forty bits. In contrast, the comparisons of PAPs or diminutive PAPs may be much smaller, e.g., single-digit number of bits. Thus, the comparisons may be much smaller and therefore much faster, which may improve the cycle time for a processor that compares PAPs or diminutive PAPs rather than physical cache line address tags. Second, there may be a significant area savings due to less logic, e.g., smaller comparators, and less storage elements, e.g., fewer bits to store a PAP or diminutive PAP rather than a physical memory line address in a cache entry, load/store queue entry, write combine buffer, etc.

Embodiments are now described in which PAPs are used to make determinations related to store-to-load forwarding. Store-to-load forwarding refers to an operation performed by processors to increase performance and generally may be described as follows. Typically, when a load instruction is executed, the load unit looks up the load address in the cache, and if a hit occurs the cache data is provided to the load instruction. However, there may be an outstanding store instruction that is older than the load instruction and that has not yet written the store data to the cache for the same memory address as the load address. In this situation, if the cache data is provided to the load instruction it would be stale data. That is, the load instruction would be receiving the wrong data. One solution to solving this problem is to wait to execute the load instruction until all older store instructions have written their data to the cache. However, a higher performance solution is to hold the store data of outstanding store instructions (i.e., that have not yet written their store data into the cache) in a separate structure, typically referred to as a store queue. During execution of the load instruction the store queue is checked to see if the load data requested by the load instruction is present in the store queue. If so, the store data in the store queue is “forwarded” to the load instruction rather than the stale cache data.

Load and store instructions specify virtual load and store addresses. If forwarding is performed without comparing physical load and store addresses, i.e., forwarding based solely on virtual address comparisons, the forwarded store data may not be the correct requested load data since two different virtual addresses may be aliases of the same physical address. However, there are reasons to avoid comparing physical addresses for store-to-load forwarding purposes. First, the physical addresses are large and would require a significant amount of additional storage space per entry of the store queue. Second, timing is critical in high performance processors, and the logic to compare a large physical address is relatively slow. Historically, high performance processors speculatively perform store-to-load forwarding based on virtual address comparisons and use much fewer than the entire virtual addresses for fast comparisons, e.g., using only untranslated address bits of the virtual addresses. These high performance processors then perform checks later, either late in the execution pipeline or when the load instruction is ready to retire, to determine whether the incorrect data was forwarded to it. Third, even if the store physical addresses were held in the store queue, the load physical address is typically not available early in the load unit pipeline for use in comparing with the store physical addresses in the store queue thus resulting in a longer execution time of the load instruction, more specifically resulting in a longer load-to-use latency of the processor, which is highly undesirable with respect to processor performance.

FIG. 13is an example block diagram of a store queue (SQ) entry1301of the SQ125ofFIG. 1that holds PAPs to accomplish store-to-load forwarding in accordance with embodiments of the present disclosure. The SQ entry1301includes store data1302, a store PAP1304, lower physical address bits PA[5:3]1306, a byte mask1308, and a valid bit1309. The valid bit1309is true if the SQ entry1301is valid, i.e., the SQ entry1301has been allocated to a store instruction and its fields are populated with valid information associated with the store instruction. The store data1302is the data that is specified by the store instruction to be stored to memory. The store data is obtained from the register file105specified by the store instruction. The population of the SQ entry1301is described in more detail below with respect toFIG. 15.

The store PAP1304is a physical address proxy for a store physical line address to which the store data1302is to be written. The store instruction specifies a store virtual address. The store physical line address is a translation of a portion of the store virtual address, namely upper address bits (e.g., bits12and above in the case of a 4 KB page size). As described above, when a cache line is brought into the L2 cache107from a physical line address, e.g., by a load or store instruction, the upper address bits of the load/store virtual address specified by the load/store instruction are translated into a load/store physical line address, e.g., by the MMU147ofFIG. 1. The cache line is brought into, i.e., allocated into, an entry of the L2 cache107, which has a unique set index and way number, as described above.

The store PAP1304specifies the set index and the way number of the entry in the L2 cache107into which the cache line was allocated, i.e., the cache line specified by the physical line address of the load/store instruction that brought the cache line into the L2 cache107, which physical line address corresponds to the store physical line address that is a translation of the upper bits of the store virtual address. The lower bits of the store virtual address (e.g., bits [11:0] in the case of a 4 KB page size) are untranslated address bits, i.e., the untranslated bits of the virtual and physical addresses are identical, as described above. The store physical address bits PA[5:3]1306correspond to the untranslated address bits [5:3] of the store virtual address. The store instruction also specifies a size of the store data to be written. In the example embodiment, the largest size of store data (and load data) is eight bytes. Hence, in the embodiment ofFIG. 13, the size of the store data1302is up to eight bytes, and the store physical address bits PA[5:3]1306narrows down the location of the store data1302within a 64-byte cache line, for example. The store size and bits [2:0] of the store address may be used to generate the store byte mask1308that specifies, or encodes, which of the eight bytes are being written by the store instruction. Other embodiments are contemplated in which the bytes written by the store instruction are specified in a different manner, e.g., the size itself and bits [2:0] of the store address may be held in the SQ entry1301rather than the byte mask1308.

Advantageously, each entry of the SQ125holds the store PAP1304rather than the full store physical line address, as described in more detail below. In the embodiment ofFIG. 13, because in the example embodiment the L2 cache107is 4-way set associative, the store PAP1304specifies the 2 bits of the way number of the entry in the L2 cache107into which the cache line specified by the physical line address is allocated. Furthermore, in the embodiment ofFIG. 13, because in the example embodiment the L2 cache107has 2048 sets, the store PAP1304specifies the eleven bits of the set index of the set of the entry in the L2 cache107into which the cache line specified by the physical line address is allocated, which corresponds to physical line address bits PA[16:6] in the embodiment. Thus, in the embodiment ofFIG. 13, the store PAP1304is thirteen bits, in contrast to a full store physical line address, which may be approximately forty-six bits in some implementations, as described above, and in other implementations there may be more. Advantageously, a significant savings may be enjoyed both in terms of storage space within the SQ125and in terms of timing by providing the ability to compare PAPs rather than full physical line addresses when making store-to-load forwarding determinations, as described in more detail below.

FIG. 14is an example block diagram of portions of the processor100ofFIG. 1used to perform store-to-load forwarding using PAPs in accordance with embodiments of the present disclosure. In the embodiment ofFIG. 14, shown are the SQ125, portions of the L1 data cache103(hashed tag array334, tag hash logic312, and comparator348(and mux, not shown, that is controlled based on the result of the comparator348), e.g., ofFIG. 3), byte mask logic1491, a mux1446, and forwarding decision logic1499. The byte mask logic1491, mux1446, and forwarding decision logic1499may be considered part of the LSU117ofFIG. 1.FIG. 14illustrates the processing of a load instruction to which store data may be forwarded from an entry of the SQ125. The load instruction specifies a load virtual address VA[63:0]321(e.g., ofFIG. 3) and a load size1489. The byte mask logic1491uses the load VA321and load size1489to generate a load byte mask1493that specifies the eight or less bytes of load data to be read from within an eight-byte aligned memory address range. The load byte mask1493is provided to the forwarding decision logic1499. The load virtual address bits VA[5:3], which are untranslated and identical to the load physical address bits PA[5:3], are also provided to the forwarding decision logic1499. The load virtual address bits VA[11:6], which are untranslated and identical to the load physical address bits PA[11:6], are also provided to the forwarding decision logic1499.

As described above, the set index326portion of the load VA321selects a set of the hashed tag array334, each way of the selected set is provided to comparator348, and the tag hash logic312uses the load VA321to generate a hashed tag324provided to comparator348for comparison with each of the selected hashed tags208(ofFIG. 2). Assuming a valid match, the comparator348provides the dPAP209(ofFIG. 2) of the valid matching entry201of the L1 data cache103, as described above. The dPAP209in conjunction with the load PA[11:6] bits form a load PAP1495. In the embodiment ofFIG. 13, the load PAP1495specifies the set index and the way number of the entry in the L2 cache107into which the cache line was allocated, i.e., the cache line specified by the physical line address of the load/store instruction that brought the cache line into the L2 cache107, which physical line address corresponds to the load physical line address that is a translation of the upper bits of the load VA321. The load PAP1495is provided to the forwarding decision logic1499. If there is no valid match, then there is no load PAP available for comparison with the store PAP1304and therefore no store-to-load forwarding may be performed, and there is no valid L1 data out327; hence, a cache line fill request is generated, and the load instruction is replayed when the requested cache line and dPAP are returned by the L2 cache107and written into the L1 data cache103.

The SQ125provides a selected SQ entry1399. The selected SQ entry1399may be selected in different manners according to different embodiments, e.g., according to the embodiments ofFIGS. 18 and 19. The store data1302of the selected SQ entry1399is provided to mux1446, which also receives the output data of the hitting entry of the L1 data cache103, i.e., L1 data out327, e.g., ofFIG. 3. In the case of a hit in the L1 data cache103, a control signal forward1497generated by the forwarding decision logic1499controls mux1446to select either the store data1302from the selected SQ entry1399or the L1 data out327. The store PAP1304, store PA[5:3] bits1306, store byte mask1308and store valid bit1309of the selected SQ entry1399are provided to the forwarding decision logic1499.

The forwarding decision logic1499determines whether the store data1302of the selected SQ entry1399overlaps the load data requested by the load instruction. More specifically, the SQ entry selection and forwarding decision logic1499generates a true value on the forward signal1497to control the mux1446to select the store data1302if the store valid bit1309is true, the load PAP1495matches the store PAP1304, the load PA[5:3] matches the store PA[5:3]1306, and the load byte mask1493and the store byte mask1308indicate the store data overlaps the requested load data, i.e., the requested load data is included in the valid bytes of the store data1302of the selected SQ entry1399; otherwise, the forwarding decision logic1499generates a false value on the forward signal1497to control the mux1446to select the L1 data out327. Stated alternatively, the store data overlaps the requested load data and may be forwarded if the following conditions are met: (1) the selected SQ entry1399is valid; (2) the load physical address and the store physical address specify the same N-byte-aligned quantum of memory, where N is the width of the store data field1302in a SQ entry1301(e.g., N=8 bytes wide), e.g., the load PAP1495matches the store PAP1304and the load PA[5:3] matches the store PA[5:3] 1306; and (3) the valid bytes of the store data1302of the selected SQ entry1399as indicated by the store byte mask1308overlap the load data bytes requested by the load instruction as indicated by the load byte mask1493. To illustrate by example, assuming a valid selected SQ entry1399, a PAP match and a PA[5:3] match, assume the store byte mask1308is a binary value 00111100 and the load byte mask1493is a binary value 00110000; then the store data overlaps the requested load data and the store data will be forwarded. However, assume the load byte mask1493is a binary value 00000011; then the store data does not overlap the requested load data and the store data will be forwarded, and instead the L1 data out327will be selected. An example of logic that may perform the byte mask comparison is logic that performs a Boolean AND of the load and store byte masks and then indicates overlap if the Boolean result equals the load byte mask. Other embodiments are contemplated in which the entry201of the L1 data cache103also holds other information such as permissions associated with the specified memory location so that the forwarding decision logic1499may also determine whether it is permissible to forward the store data to the load instruction. Although an embodiment is described in which the width of the store queue data field1302equals the largest possible size specified by a store instruction, other embodiments are contemplated in which the width of the store queue data field1302is greater than the largest possible size specified by a store instruction.

Advantageously, the forwarding decision logic1499may compare load PAP1495against the store PAP1304since they are proxies for the respective load physical line address and store physical line address, which alleviates the need for the forwarding decision logic1499to compare the load physical line address and store physical line address themselves. Comparing the PAPs may result in a significantly faster determination (reflected in the value of the forward control signal1497) of whether to forward the store data1302and may even improve the load-to-use latency of the processor100. Additionally, each SQ entry1301holds the store PAP1304rather than the store physical line address, and each L1 data cache103entry201holds the load PAP1495(or at least a portion of it, i.e., the dPAP209) rather than the load physical line address, which may result in a significant savings in terms of storage space in the processor100. Finally, unlike conventional approaches that, for example, make forwarding decisions based merely on partial address comparisons (e.g., of untranslated address bits and/or virtual address bits), the embodiments described herein effectively make a full physical address comparison using the PAPs.

Further advantageously, the provision of the load PAP by the virtually-indexed virtually-tagged L1 data cache103may result in a faster determination of whether to forward the store data because the load PAP is available for comparison with the store PAP sooner than in a physically-accessed cache design in which the virtual load address is first looked up in a translation lookaside buffer. Still further, using the hashed tag array334to hold and provide the PAP for the load instruction may result in the load PAP being available for comparison with the store PAP sooner than if a full tag comparison is performed, again which may result in a faster determination of whether to forward the store data. Finally, a faster determination of whether to forward the store data may be obtained because the SQ125provides a single selected SQ entry1399which enables the load PAP to be compared against a single store PAP rather than having to perform a comparison of the load PAP with multiple store PAPs. These various speedups in the store forwarding determination may, either separately or in combination, improve the load-to-use latency of the processor100, which is an important parameter for processor performance.

FIG. 15is an example flowchart illustrating processing of a store instruction, e.g., by the processor100ofFIG. 14, that includes writing a store PAP into a store queue entry in accordance with embodiments of the present disclosure. As described above, the L2 cache107is inclusive of the L1 data cache103such that when a cache line is brought into an entry of the L1 data cache103, the cache line is also brought into an entry of the L2 cache107(unless the cache line already resides in the L2 cache107). As described above, e.g., with respect toFIG. 7, when the cache line is brought into the entry401of the L2 cache107, the dPAP209used to specify the allocated L2 entry401is written into the entry201allocated into the L1 data cache103. As described above, the dPAP209is the PAP that specifies the L2 entry401less any bits of the L2 set index of the PAP used in the set index of the L1 data cache103. Stated alternatively, the dPAP is the L2 way number of the L2 entry401along with any bits of the L2 set index of the entry401not used in the set index of the L1 data cache103. Operation begins at block1502.

At block1502, the decode unit112ofFIG. 1encounters a store instruction and allocates a SQ entry1301for the store instruction and dispatches the store instruction to the instruction schedulers121ofFIG. 1. The store instruction specifies a register of the register file105ofFIG. 1that holds the store data to be written to memory. The store instruction also specifies a store virtual address, e.g., store VA321ofFIG. 3(the store VA321may include all 64 bits, i.e., including bits [5:0], even thoughFIG. 3only indicates bits [63:6]) and a size of the data, e.g., one, two, four, or eight bytes. Operation proceeds to block1504.

At block1504, the LSU117executes the store instruction. The store virtual address321hits in the L1 data cache103, at least eventually. If the store virtual address321initially misses in the L1 data cache103(e.g., at block702ofFIG. 7), a cache line fill request will be generated to the L2 cache107, which involves the DTLB141translating the store virtual address321into a store physical address. A portion of the store physical address is the store physical line address, e.g., store PA[51:6] that is used in the lookup of the L2 cache107to obtain the requested cache line and, if missing in the L2 cache107(and missing in any other higher levels of the cache hierarchy, if present), used to access memory to obtain the cache line. The L2 cache107returns the cache line and the PAP that is a proxy for the store physical line address. More specifically, the PAP specifies the way number and set index that identifies the entry401of the L2 cache107that is inclusively holding the requested cache line. The dPAP portion of the PAP is written along with the cache line to the entry of the L1 data cache103allocated to the store instruction (e.g., at block704ofFIG. 7). The store instruction is replayed when the requested cache line and dPAP are returned by the L2 cache107and written into the L1 data cache103. Upon replay, the store virtual address321hits in the L1 data cache103. The hitting entry201of the L1 data cache103provides the store dPAP209that is used along with untranslated bits of the store virtual address321(e.g., VA[11:6], which are identical to store physical address bits PA[11:6]) to form a store PAP that is a physical address proxy of the store physical line address, i.e., the store PAP points to the entry401of the L2 cache107that holds the copy of the cache line held in the entry201of the L1 data cache103hit by the store virtual address321. The store physical line address is the upper bits (e.g., [51:6]) of the store physical address. Operation proceeds to block1506.

At block1506, the LSU117obtains the store data from the register file105and writes it into the store data field1302of the SQ entry1301allocated at block1502. The LSU117also forms the store PAP using the store dPAP209obtained from the L1 data cache103at block1504and lower untranslated address bits of the store virtual address321(e.g., store VA[11:6]). The LSU117then writes the store PAP into the store PAP field1304of the allocated SQ entry1301. Finally, the LSU117writes into the allocated SQ entry1301additional information that determines the store physical address and store data size, which in the embodiment ofFIGS. 13 and 14includes writing store address bits [5:3] into the PA[5:3] field1306and writing a store byte mask into the byte mask field1308. The store byte mask indicates which bytes within an eight-byte-aligned quantum of memory the store data are to be written in an embodiment in which the store byte mask if eight bits. As described above, the SQ entry1301is configured to hold the store PAP1304rather than the full store physical line address, which advantageously may reduce the amount of storage needed in the SQ125.

FIG. 16is an example flowchart illustrating processing of a load instruction, e.g., by the processor100ofFIG. 14, that includes using a load PAP and a store PAP from a store queue entry to decide whether to forward store data to the load instruction from the store queue entry in accordance with embodiments of the present disclosure. Operation begins at block1602.

At block1602, a load instruction is issued to the LSU (e.g.,117). The LSU looks up the load virtual address (e.g.,321) in the L1 data cache (e.g.,103). In the embodiment ofFIG. 14(andFIGS. 18 and 19), the lookup includes looking up the load virtual address in the hashed tag array (e.g.,334). In the embodiment ofFIG. 20, the lookup includes looking up the load virtual address in the tag array. Similar to the manner described above with respect to block1504, the load virtual address eventually hits in the L1 data cache. The hit entry (e.g.,201) provides the dPAP (e.g.,209) for the load instruction. The load dPAP along with untranslated bits of the load virtual address (e.g., VA[11:6], which are identical to the load physical address PA[11:6]) are used to form the load PAP (e.g.,1495), e.g., as shown inFIG. 14. Additionally, a load byte mask (e.g.,1493ofFIG. 14) is generated (e.g., by byte mask logic1491ofFIG. 14) from the load data size (e.g.,1489ofFIG. 14) and the lowest address bits (e.g., VA[2:0], which are identical to the load physical address PA[2:0]), e.g., as shown inFIG. 14. Operation proceeds to block1604.

At block1604, the SQ125provides a selected SQ entry (e.g.,1399), which includes the store data (e.g.,1302), store PAP (e.g.,1304), store lower physical address bits (e.g., PA[5:3]), store byte mask (e.g.,1308), and store valid bit (e.g.,1309), e.g., as shown inFIG. 14. As described with respect toFIG. 14, the SQ entry may be selected in different manners according to different embodiments, e.g., according to the embodiments ofFIGS. 18 and 19. Operation proceeds to block1606.

At block1606, the store PAP and load PAP are used (e.g., by forwarding logic1499ofFIG. 14)—along with additional information, e.g., the store lower address bits1306and load lower address bits (e.g., PA[5:3]) and store byte mask1308and load byte mask1493ofFIG. 14—to determine whether to forward the store data (e.g.,1302) from the selected SQ entry to the load instruction or whether instead the cache data (e.g., L1 data out327) is provided to the load instruction. That is, the store PAP and load PAP and the additional information are used to determine whether the store data of the selected SQ entry overlaps the load data requested by the load instruction. If the store data of the selected SQ entry overlaps the requested load data, then the store data is forwarded; otherwise, the data out of the L1 data cache is provided for the load instruction. Embodiments described herein use the load and store PAPs as proxies for the load and store physical line addresses to determine that the load and store have the same physical line address, which is required for the store data to overlap the requested load data. In contrast, conventional designs may forego a full physical line address comparison because of timing delays (e.g., instead making forwarding decisions based merely on partial address comparisons, e.g., of untranslated address bits and/or virtual address bits), whereas the embodiments described herein effectively make a full physical address comparison using the PAPs, but at a smaller timing cost because of the smaller PAP comparisons.

FIG. 17is an example block diagram of a SQ entry1701of the SQ125ofFIG. 1that holds PAPs to accomplish store-to-load forwarding in accordance with embodiments of the present disclosure. The SQ entry1701ofFIG. 17is similar in many respects to the SQ entry1301ofFIG. 13. However, the SQ entry1701ofFIG. 17further includes a subset of virtual address bits1711. In the embodiment ofFIG. 18, the subset of virtual address bits1711is written, along with the other information of the SQ entry1701according to the operation ofFIG. 15. That is, during execution of the store instruction the LSU117writes a corresponding subset of bits of the store virtual address321to the subset of virtual address bits field1711of the allocated SQ entry1701, e.g., at block1506, for subsequent use as described below with respect toFIG. 18.

FIG. 18is an example block diagram of portions of the processor100ofFIG. 1used to perform store-to-load forwarding using PAPs in accordance with embodiments of the present disclosure. The embodiment ofFIG. 18is similar in many respects to the embodiment ofFIG. 14, except that each entry1701of the SQ125also includes the subset of virtual address bits1711ofFIG. 17. Additionally, in the embodiment ofFIG. 18, the selected SQ entry1399(described with respect toFIG. 14) is selected using a subset of virtual address bits1801of the load virtual address321, as shown. That is, the subset of the load virtual address bits1801are compared with the subset of virtual address bits1711of each valid entry of the SQ125for matches. If no matches are found, then no store-to-load forwarding is performed. The SQ125receives an indicator that indicates which entries1701of the SQ125are associated with store instructions that are older than the load instruction. Using the indicator, if one or more matches are found that are older in program order than the load instruction, logic within the SQ125selects as the selected SQ entry1399the youngest in program order from among the older matching SQ entries1701. In one embodiment, the decode unit112, which dispatches instructions—including all load and store instructions—to the execution units114in program order, generates and provides to the SQ125, as the indicator, a SQ index1879for each load instruction which is the index into the SQ125of the SQ entry1701associated with the youngest store instruction that is older in program order than the load instruction. In an alternate embodiment, the index of the store instruction within the ROB122is held in each entry1701of the SQ125, and the index of the load instruction within the ROB122(rather than the SQ index1879) is provided to the SQ125, as the indicator, for use, in conjunction with the ROB indices of the SQ entries1701, in selecting the SQ entry1701associated with the matching youngest store instruction older in program order than the load instruction, i.e., selected SQ entry1399. The SQ125provides the selected SQ entry1399to the forwarding decision logic1499and to the mux1446, e.g., according to block1604ofFIG. 16. That is,FIG. 18describes an embodiment for selecting the selected SQ entry1399, i.e., using virtual address bits and the indicator, and otherwise operation proceeds according to the manner described with respect toFIGS. 14 and 16, advantageously that the load and store PAPs, rather than full load and store physical line addresses, are used to determine whether the store data of the selected SQ entry1399overlaps the requested load data and may thus be forwarded. In an alternate embodiment, the load byte mask1493is provided to the SQ125(rather than to the forwarding decision logic1499), and the logic within the SQ125compares the load byte mask1493against the store byte mask1308of each valid SQ entry1701to determine whether there is overlap of the requested load data by the store data1302of SQ entries1701whose subsets of virtual address bits1711match the load subset of virtual address bits1801. That is, the logic within the SQ125additionally uses the byte mask compares to select the selected SQ entry1399. In one embodiment, the subset of virtual address bits1711may be a hash of bits of the store virtual address321of the store instruction to which the SQ entry1701is allocated, and the subset of load virtual address bits1801used to compare with each valid entry1701of the SQ125may be a hash of bits of the load virtual address321.

FIG. 19is an example block diagram of portions of the processor100ofFIG. 1used to perform store-to-load forwarding using PAPs in accordance with embodiments of the present disclosure. The embodiment ofFIG. 19is similar in many respects to the embodiment ofFIG. 14, except that the embodiment ofFIG. 19uses the memory dependence predictor (MDP)111ofFIG. 1to provide a prediction of a store instruction from which to forward store data to the load instruction. In one embodiment, the MDP111receives an instruction pointer (IP)1901value of the load instruction, i.e., the address in memory from which the load instruction is fetched. In another embodiment, the MDP111receives information specifying other characteristics1901of the load instruction, such as a destination register of the store instruction or an addressing mode of the store instruction, i.e., a characteristic of the store instruction that may be used to distinguish the store instruction from other store instructions. The MDP111uses the received load instruction-specific information1901to generate a prediction of the store instruction from which store data should be forwarded to the load instruction. In the embodiment ofFIG. 19, the prediction may be an index1903into the SQ125of the entry1301allocated to the predicted store instruction. The predicted SQ entry index1903is provided to the SQ125to select the selected SQ entry1399. The SQ125provides the selected SQ entry1399to the forwarding decision logic1499and to the mux1446, e.g., according to block1604ofFIG. 16. That is,FIG. 19describes an embodiment for selecting the selected SQ entry1399, i.e., using the MDP111, and otherwise operation proceeds according to the manner described with respect toFIGS. 14 and 16, advantageously that the load and store PAPs, rather than full load and store physical line addresses, are used to determine whether the store data of the selected SQ entry1399overlaps the requested load data and may thus be forwarded.

FIG. 20is an example block diagram of portions of the processor100ofFIG. 1used to perform store-to-load forwarding using PAPs in accordance with embodiments of the present disclosure. The embodiment ofFIG. 20is similar in many respects to the embodiment ofFIG. 14. However, the embodiment is absent a hashed tag array334. Instead, in the embodiment ofFIG. 20, the tag array332holds the dPAPs209, and the tag322of the load VA321is compared with each of the selected tags204(ofFIG. 2) to determine which dPAP209to provide for formation into the load PAP1495. Otherwise, operation proceeds according to the manner described with respect toFIGS. 14 and 16, advantageously that the load and store PAPs, rather than full load and store physical line addresses, are used to determine whether the store data of the selected SQ entry1399overlaps the requested load data and may thus be forwarded.

FIG. 21is an example block diagram of portions of the processor100ofFIG. 1used to perform store-to-load forwarding using PAPs in accordance with embodiments of the present disclosure. The embodiment ofFIG. 21is similar in many respects to the embodiment ofFIG. 14, except that rather than using the load PAP to compare with a store PAP of a single selected SQ entry1399to determine whether the store data of the single selected SQ entry1399overlaps with the requested load data as inFIGS. 14 through 20, instead the load PAP is used to compare with the store PAP of all valid entries1301of the SQ125to select a SQ entry1301from which to forward store data to the load instruction.

The embodiment ofFIG. 21includes similar elements toFIG. 14and additionally includes a SQ head/tail2177(i.e., the head and tail pointers that identify the set of valid SQ entries1301), candidate set identification logic2197, SQ entry selection logic2193, and a mux2189. The storage that stores all the SQ entries1301is also shown, the number of entries1301being denoted N inFIG. 21. The mux2189receives the stores data1302of all N of the SQ entries1301and selects the store data indicated by a control signal2191generated by the SQ entry selection logic2193as described in more detail below. The candidate set identification logic2197receives all N SQ entries1301of the SQ125. The candidate set identification logic2197also receives the load PAP1495, the load lower address bits PA[5:3], and the load byte mask1493. The candidate set identification logic2197compares the load PAP1495and load lower address bits PA[5:3] and load byte mask1493with the respective store PAP1304and store lower address bits PA[5:3]1306and store byte mask1308of each of the N entries1301of the SQ125to generate a candidate set bit vector2195. The candidate set bit vector2195includes a bit for each of the N SQ entries1301. A bit of the bit vector2195associated with a SQ entry1301is true if its store PAP1304and store lower address bits PA[5:3]1306match the load PAP1495and load lower address bits PA[5:3] and the store byte mask1308overlaps the load byte mask1493.

The SQ entry selection logic2193receives the candidate set bit vector2195, head and tail pointers2177of the SQ125, and the SQ index of the most recent store older than the load1879. Using the head and tail pointers2177of the SQ125and the SQ index of the most recent store older than the load1879, the SQ entry selection logic2193selects, and specifies on mux2189control signal2191, the SQ entry1301associated with the youngest store instruction in program order from among the SQ entries1301whose associated bit of the candidate set bit vector2195is true that is older in program order than the load instruction, if such a SQ entry1301exists. If such a SQ entry1301exists, the SQ entry selection logic2193generates the forward control signal1497to select the selected store data2102out of the mux1446; otherwise, the mux1446selects the L1 data out327.

In an alternate embodiment, the index of the load instruction within the ROB122(rather than the SQ index1879) is provided, similar to the description with respect toFIG. 18, for use by the SQ entry selection logic2193in generating the mux2189control signal2191to select the store data1302from the SQ entry1301associated with the youngest store instruction older in program order than the load instruction from among the SQ entries1301whose associated bit of the candidate set bit vector2195is true.

FIG. 22is an example flowchart illustrating processing of a load instruction by the processor100ofFIG. 21that includes using a load PAP and a store PAP of each entry of the store queue to decide whether to forward store data to the load instruction from a store queue entry in accordance with embodiments of the present disclosure. Operation begins at block2202.

At block2202, operation is similar to the operation described at block1602ofFIG. 16. Operation proceeds to block2204.

At block2204, the load PAP (e.g.,1495) and load lower address bits (e.g., PA[5:3]) along with the load byte mask (e.g.,1493) are compared (e.g., by candidate set identification logic2197ofFIG. 21) with the store PAP (e.g.,1304) and store lower physical address bits (e.g., PA[5:3]) along with the store byte mask (e.g.,1308) of each valid SQ entry (e.g.,1301) to identify a candidate set of SQ entries whose store data (e.g.,1302) overlaps the load data requested by the load instruction (e.g., indicated by candidate set bit vector2195). Operation proceeds to block2206.

At block2206, from among the set of candidate SQ entries is selected (e.g., by mux2189controlled by SQ entry selection logic2193) the store data from the SQ entry associated with youngest store instruction that is older in program order than the load instruction. Assuming such a SQ entry is found, the selected store data is forwarded to the load instruction; otherwise, the cache data (e.g., L1 data out327) is provided to the load instruction. That is, the store PAP and load PAP and additional information (e.g., load and store lower address bits [5:3] and byte masks) are used to determine whether the store data of any of the SQ entries overlaps the load data requested by the load instruction. If the store data of the store instruction associated with one or more SQ entries overlaps the requested load data, and at least one of the overlapping store instructions is older than the load instruction, then the store data from the youngest of the older store instructions is forwarded; otherwise, the data out of the L1 data cache is provided for the load instruction. Embodiments described herein use the load and store PAPs as proxies for the load and store physical line addresses to determine that the load and candidate stores have the same physical line address, which is required for the store data to overlap the requested load data. In contrast, conventional designs may forego a full physical line address comparison because of timing delays (e.g., instead making forwarding decisions based merely on partial address comparisons, e.g., of untranslated address bits and/or virtual address bits), whereas the embodiments described herein effectively make a full physical address comparison using the PAPs, but at a smaller timing cost because of the smaller PAP comparisons.

It should be understood—especially by those having ordinary skill in the art with the benefit of this disclosure—that the various operations described herein, particularly in connection with the figures, may be implemented by other circuitry or other hardware components. The order in which each operation of a given method is performed may be changed, unless otherwise indicated, and various elements of the systems illustrated herein may be added, reordered, combined, omitted, modified, etc. It is intended that this disclosure embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense.

Similarly, although this disclosure refers to specific embodiments, certain modifications and changes can be made to those embodiments without departing from the scope and coverage of this disclosure. Moreover, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element.

Further embodiments, likewise, with the benefit of this disclosure, will be apparent to those having ordinary skill in the art, and such embodiments should be deemed as being encompassed herein. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art and are construed as being without limitation to such specifically recited examples and conditions.

Finally, software can cause or configure the function, fabrication and/or description of the apparatus and methods described herein. This can be accomplished using general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known non-transitory computer-readable medium, such as magnetic tape, semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.), a network, wire line or another communications medium, having instructions stored thereon that are capable of causing or configuring the apparatus and methods described herein.