Vertical cavity surface emitting laser array

A VCSEL array includes a base substrate, VCSEL element columns arranged in a row direction (y direction) on a front-surface side of the base substrate and parallel wiring lines that connect the VCSEL element columns in parallel with each other. Each of the VCSEL element columns includes a plurality of VCSEL elements arranged in a column direction (x direction) and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two VCSEL elements that are adjacent to each other in the column direction among the plurality of VCSEL elements in such an orientation that the forward directions of the two VCSEL elements match. Insulating grooves are formed on the base substrate. The insulating grooves electrically insulate the VCSEL element columns from each other. The insulating grooves electrically insulate the VCSEL elements from each other.

TECHNICAL FIELD

The present disclosure relates to a vertical cavity surface emitting laser array.

BACKGROUND

Generally, in the process of manufacturing a semiconductor element, an acceleration test is performed in which a temperature or voltage load is applied, that is, a burn-in test is performed. As a result of the burn-in test, when the value of a characteristic of a certain semiconductor element fails to satisfy a prescribed reference value, that semiconductor element is removed from a group of non-defective components as an initial-stage defective component.

In a vertical cavity surface emitting laser element, light is emitted in a direction orthogonal to a semiconductor substrate. Consequently, a burn-in test can be performed in a wafer state where a plurality of vertical cavity surface emitting laser elements are formed in an array pattern. This type of burn-in test is called wafer level burn-in (WLBI).

There is a demand for techniques for performing WLBI on a vertical cavity surface emitting laser array with accuracy and at low cost. In a surface emission wafer disclosed in Japanese Unexamined Patent Application Publication No. 2006-66845 for example, a plurality of surface emission elements are connected in series in such an orientation that the forward directions of light-emitting element units match.

SUMMARY

Technical Problem

In order to accurately carry out a burn-in test, it is necessary that load conditions be the same for all the vertical cavity surface emitting laser elements within a wafer. The value of a load current is one of the most important parameters in the burn-in test of vertical cavity surface emitting laser elements. Therefore, it is demanded that the values of the load currents of the vertical cavity surface emitting laser elements be made the same as one another.

However, there is a conductive semiconductor layer inside a semiconductor substrate in the surface emission wafer disclosed in Japanese Unexamined Patent Application Publication No. 2006-66845. Consequently, when a load current flows between serially connected surface emission elements, there is a possibility that part of the load current will leak out through the inside of the conductive semiconductor layer. As a result, it may not be possible to make the load currents of serially connected surface emission elements be the same as one another.

An object of the present disclosure is to provide a vertical cavity surface emitting laser array configured so that a burn-in test can be performed with accuracy and at low cost.

Solution to Problem

A vertical cavity surface emitting laser array according to a certain aspect of the present disclosure includes a semiconductor substrate, a plurality of vertical cavity surface emitting laser element columns and parallel wiring lines. The plurality of vertical cavity surface emitting laser element columns are arranged in a row direction on a front-surface side of the semiconductor substrate. The parallel wiring lines connect the plurality of vertical cavity surface emitting laser element columns in parallel with each other. The plurality of vertical cavity surface emitting laser element columns each include a plurality of vertical cavity surface emitting laser elements arranged in a column direction and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two of the vertical cavity surface emitting laser elements that are adjacent to each other in the column direction among the plurality of vertical cavity surface emitting laser elements in such an orientation that forward directions of the two vertical cavity surface emitting laser elements match. A first insulating region that electrically insulates the plurality of vertical cavity surface emitting laser element columns from each other and a second insulating region that electrically insulates the plurality of vertical cavity surface emitting laser elements from each other are formed in the semiconductor substrate.

It is preferable that the vertical cavity surface emitting laser array further include at least one pair of dummy pads. The at least one pair of dummy pads are electrically connected to the parallel wiring lines in order to supply a load current from burn-in test probes to the plurality of vertical cavity surface emitting laser element columns.

It is preferable that the plurality of vertical cavity surface emitting laser elements be arranged inside a quadrangular region on the front-surface side of the semiconductor substrate. The pair of dummy pads are arranged near a first corner and a second corner positioned on a diagonal line among first to fourth corners corresponding to the four corners of the quadrangular region.

It is preferable that the parallel wiring lines each include a plurality of wiring line portions. The plurality of wiring line portions each connect in parallel two vertical cavity surface emitting laser element columns that are adjacent to each other in the row direction. A resistance value of each of the plurality of wiring line portions is set so as to be inversely proportional to a value of the load current that will flow through the wiring line portion in a state where the load current is supplied to the plurality of vertical cavity surface emitting laser element columns.

It is preferable that each of the plurality of wiring line portions be configured so as to have a wiring line width that corresponds to a value of the load current that will flow through the wiring line portion in a state where the load current is supplied to the plurality of vertical cavity surface emitting laser element columns.

It is preferable that the plurality of vertical cavity surface emitting laser element columns includes a first vertical cavity surface emitting laser element column including m (m is natural number of 2 or more) vertical cavity surface emitting laser elements and a second vertical cavity surface emitting laser element column including n (n is a natural number that is smaller than m) vertical cavity surface emitting laser elements. At least one of the pair of dummy pads is arranged in a region corresponding to the area of (m−n) vertical cavity surface emitting laser elements in the vicinity of the second vertical cavity surface emitting laser element column on the front-surface side of the semiconductor substrate.

It is preferable that the second vertical cavity surface emitting laser element column further include a dummy element. The dummy element causes a voltage drop to be generated that corresponds to the size of a voltage drop that would be caused by the (m−n) vertical cavity surface emitting laser elements.

It is preferable that the plurality of vertical cavity surface emitting laser elements each have an anode electrode, a cathode electrode, an anode electrode pad electrically connected to the anode electrode and a cathode electrode pad electrically connected to the cathode electrode. The parallel wiring lines each include a plurality of wiring line portions. The plurality of wiring line portions each connect in parallel two vertical cavity surface emitting laser element columns that are adjacent to each other in the row direction. The plurality of wiring line portions are each arranged between one cathode electrode pad and another cathode electrode pad of two vertical cavity surface emitting laser elements that are adjacent to each other in the row direction.

It is preferable that the semiconductor substrate have a semi-insulating property. The first and second insulating regions are each an insulating groove. The insulating grooves each have a shape that is recessed from the front-surface-side of the semiconductor substrate toward the inside of the semiconductor substrate. The parallel wiring lines each include a wiring line portion formed on the insulating groove of the second insulating region.

It is preferable that the semiconductor substrate have a semi-insulating property. The first and second insulating regions are each a high-resistance region that has a higher electrical resistivity than the semiconductor substrate.

Advantageous Effects of Disclosure

According to the present disclosure, a vertical cavity surface emitting laser array can be provided that is configured so that a burn-in test can be performed with accuracy and at low cost.

DETAILED DESCRIPTION

Hereafter, embodiments of the present disclosure will be described in detail while referring to the drawings. In the figures, the same symbols denote identical or corresponding portions and repeated description thereof is omitted. In addition, the sizes of parts illustrated in the drawings are schematically represented and the sizes of the parts are not limited to the sizes illustrated in the drawings.

First EmbodimentFIG. 1Ais a plan view of a vertical cavity surface emitting laser (VCSEL) array according to a first embodiment of the present disclosure.FIG. 1Bis an equivalent circuit diagram of the VCSEL array according to the first embodiment of the present disclosure.

Referring toFIGS. 1A and 1B, a VCSEL array901includes VCSEL element columns101to105arranged in a row direction (y direction), parallel wiring lines73and74, a pair of dummy pads71and72and insulating grooves91and92. Each of the VCSEL element columns101to105includes five VCSEL elements arranged in a column direction (x direction) and series wiring lines61.

The parallel wiring lines73and74are for connecting in parallel every two VCSEL element columns that are adjacent to each other in the row direction (y direction) among the VCSEL element columns101to105. The series wiring lines61electrically connect every two VCSEL elements that are adjacent to each other in the column direction in such an orientation that the forward directions of the elements match.

The dummy pads71and72are respectively electrically connected to the parallel wiring lines73and74. The pair of dummy pads71and72are formed in order to supply a load current I (refer toFIG. 5for all) from probes63to the VCSEL element columns101to105. The load current I flows in a direction from the dummy pad71to the dummy pad72.

The parallel wiring line73includes wiring line portions731to734. The parallel wiring line74includes wiring line portions741to744. The wiring line portions731and741connect the VCSEL element columns101and102in parallel with each other. The wiring line portions732and742connect the VCSEL element columns102and103in parallel with each other. The wiring line portions733and743connect the VCSEL element columns103and104in parallel with each other. The wiring line portions734and744connect the VCSEL element columns104and105in parallel with each other.

Resistances R31to R34and R41to R44are resistance components of the wiring line portions731to734and741to744, respectively. In this embodiment, the resistance values of the resistances R31to R34and R41to R44are the same as one another.

The insulating grooves91electrically insulate the VCSEL element columns101to105from one another in a state where the parallel wiring lines73and74are not formed. The insulating grooves92electrically insulate the VCSEL elements from one another in a state where the series wiring lines61are not formed.

Since the structures of the individual VCSEL element columns are the same and the structures of the individual VCSEL elements are the same, hereafter, the structure of the VCSEL element column101and a VCSEL element2will be described as representative examples.

FIG. 2is an enlarged view of part of the VCSEL element column101illustrated inFIG. 1A.FIG. 3is a sectional view of the VCSEL element column101taken along line III-III inFIG. 2.FIG. 4is an enlarged view of the cross section of the VCSEL element2illustrated inFIG. 3.

The VCSEL element2includes a base substrate11, an n-type semiconductor contact layer (n-type contact layer)12, an n-type semiconductor multilayer-film reflecting layer (n-type distributed Bragg reflector (DBR) layer)13, an n-type semiconductor cladding layer (n-type cladding layer)14, an active layer15, a p-type semiconductor cladding layer (p-type cladding layer)16, a p-type semiconductor multilayer-film reflecting layer (p-type DBR layer)17, a p-type semiconductor contact layer (p-type contact layer)18, a current constriction layer19, an anode electrode pad41, an anode ohmic electrode42, an anode routing wiring line43, cathode electrode pads51, a cathode ohmic electrode52and cathode routing wiring lines53.

The insulating groove91is formed between the VCSEL element column101and the VCSEL element column102(refer toFIG. 1A). The insulating grooves92are formed between the VCSEL elements1to3. A direction from the rear surface side toward the front surface side of the base substrate11is represented by a z direction and a positive z direction is upward.

The material of the base substrate11is an n-type compound semiconductor that exhibits a semi-insulating property for example. An n-type gallium arsenide (GaAs) substrate having an electrical resistivity of 1.0×107Ω·cm or more is used as the base substrate11for example. The base substrate11corresponds to a “semiconductor substrate” in the present disclosure.

The n-type contact layer12is formed on the base substrate11. The material of the n-type contact layer12is a compound semiconductor that exhibits n-type conductivity. The n-type contact layer12is formed in order to realize with certainty ohmic contact between the n-type DBR layer13and the cathode ohmic electrode52.

The n-type DBR layer13is formed on the n-type contact layer12. The material of the n-type DBR layer13is a compound semiconductor that exhibits n-type conductivity and is aluminum gallium arsenide, for example. As an impurity for obtaining n-type conductivity, around 2×1018cm−3of silicon (Si) is introduced for example.

In the n-type DBR layer13, a high-refractive-index layer and a low-refractive-index layer (neither is illustrated) are alternately stacked. The thickness of each layer is λ/4 (λ: wavelength inside medium). The high-refractive-index layers and the low-refractive-index layers have different composition ratios of Al to Ga. The compositions of the high-refractive-index layers and the low-refractive-index layers are for example respectively expressed as n−Al0.9Ga0.1As and n−Al0.12Ga0.88As. One high-refractive-index layer and one low-refractive-index layer form a pair and for example 30 to 40 pairs of these layers are formed.

The n-type cladding layer14is formed on the n-type DBR layer13. The material of the n-type cladding layer14is a compound semiconductor that exhibits n-type conductivity.

The active layer15is formed on the n-type cladding layer14. The active layer15is a non-doped region into which an impurity has not been introduced. As one example, the active layer15has a multi quantum well (MQW) structure in which a quantum well layer and a barrier layer (neither is illustrated) are alternately stacked.

The p-type cladding layer16is formed on the active layer15. The material of the p-type cladding layer16is a compound semiconductor that exhibits p-type conductivity.

In this embodiment, the n-type cladding layer14, the active layer15and the p-type cladding layer16form an active region150that causes light to be generated. The thicknesses and the materials of the layers included in the active region150are appropriately set in accordance with the emission wavelength (for example, 850 nm). For example, GaAs and AlGaAs are respectively used in the quantum well layers and the barrier layers of the active layer15. In addition, AlGaAs is used in the n-type DBR layer13and the p-type cladding layer16.

However, the configuration of the active region is not limited to this configuration and for example a cladding layer need not be formed. Alternatively, a cladding layer may be formed on just one side of the active layer. In other words, the n-type cladding layer14and the p-type cladding layer16are not essential constituent elements.

The p-type DBR layer17is formed on the p-type cladding layer16. The material of the p-type DBR layer17is a compound semiconductor that exhibits p-type conductivity and is AlGaAs for example. As an impurity for obtaining p-type conductivity, around 2×1018cm−3of carbon (C) is introduced for example.

The structure of the p-type DBR layer17is different from the structure of the n-type DBR layer13in that the number of pairs of a high-refractive-index layer and a low-refractive-index layer is smaller than in the n-type DBR layer13. The number of pairs included in the n-type DBR layer13is 30 to 40, whereas the number of pairs included in the p-type DBR layer17is 20 for example. Thus, the p-type DBR layer17is formed such that the reflectivity of the p-type DBR layer17is somewhat lower than the reflectivity of the n-type DBR layer13. The rest of the structure of the p-type DBR layer17is the same as that of the n-type DBR layer13and detailed description thereof will not be repeated.

The p-type contact layer18is formed on the p-type DBR layer17. The material of the p-type contact layer18is a compound semiconductor that exhibits p-type conductivity. The p-type contact layer18is formed in order to realize with certainty ohmic contact between the p-type DBR layer17and the anode ohmic electrode42.

The p-type DBR layer17may also serve as the p-type contact layer18. In addition, the n-type DBR layer13may also serve as the n-type contact layer12. In other words, the p-type contact layer18and the n-type contact layer12are not essential constituent components.

The current constriction layer19is formed at the interface between the p-type cladding layer16and the p-type DBR layer17. The current constriction layer19includes an oxidized region191and a non-oxidized region192. The oxidized region191is formed by oxidizing the current constriction layer19from the side surfaces of the current constriction layer19toward the center. The non-oxidized region192is a region substantially in the center of the current constriction layer19that remains without being oxidized. The material of the oxidized region191is AlGaAs for example. In the composition of the oxidized region191, the composition ratio of Al to Ga is set so as to be high compared to the other layers and is Al0.95Ga0.05As for example.

As a result of forming the current constriction layer19, a current flowing from the p-type DBR layer17to the n-type DBR layer13can be locally concentrated and injected into the active region150. Thus, oscillations are generated with even a low current and therefore high light emission efficiency can be realized. Therefore, the power consumption of the VCSEL element can be reduced.

The anode ohmic electrode42is formed on the p-type contact layer18so as to be in conductive contact with the p-type contact layer18. The anode ohmic electrode42is for example an annular-shaped electrode when the xy plane is viewed in plan along the z direction (refer toFIG. 2). Light generated in the active region150is emitted through an emission aperture421in the center of the anode ohmic electrode42to the outside. The shape of the anode ohmic electrode42does not necessarily have to be an annular shape and for example may be a rectangular shape or a C shape formed by removing part of an annular shape.

A region in which the n-type DBR layer13is not formed is in the vicinity of the region in which the n-type cladding layer14is formed on the n-type contact layer12. The cathode ohmic electrode52is formed in this region so as to be in conductive contact with the n-type contact layer12. The cathode ohmic electrode52is for example an arc-shaped electrode when the xy plane is viewed along the z direction. The anode ohmic electrode42and the cathode ohmic electrode52respectively correspond to an “anode electrode” and a “cathode electrode” in the present disclosure.

The insulating grooves91and92each have a shape that is recessed from a front surface side of the base substrate11toward the inside of the base substrate11. The insulating grooves91and92isolate layers of the VCSEL elements formed on the base substrate11. The layers that are isolated by the insulating grooves91and92are conductive or semi-conductive semiconductor layers formed on the base substrate11and correspond to the n-type contact layer12and the n-type DBR layer13in this embodiment. The insulating grooves91and92respectively correspond to a “first insulating region insulating groove” and a “second insulating region insulating groove” in the present disclosure. In addition, it is preferable that the insulating grooves91and92be formed together in an integrated manner in order to reduce the number of steps.

By using a semiconductor substrate having a semi-insulating property as the base substrate11, all of the VCSEL elements are electrically insulated from each other. In addition, by forming the insulating grooves91and92, an electrical insulation property (isolation) between VCSEL elements that are adjacent to each other with the insulating grooves91and92therebetween can be further strengthened.

The parallel wiring lines73and74can be formed on the insulating grooves91. The series wiring lines61can be formed on the insulating grooves92. Thus, compared with the case where the series wiring lines61and the parallel wiring lines73and74are formed in different regions to the insulating grooves91and92, the area occupied by the series wiring lines61and the parallel wiring lines73and74can be reduced. Therefore, the number of VCSEL elements obtained per wafer is increased. Therefore, the cost per VCSEL element can be reduced.

An insulating protective film31is formed so as to cover the surface of each of the above-described structures except for the anode ohmic electrode42and the cathode ohmic electrode52. The insulating protective film31is composed of silicon nitride (SiN) for example. When silicon nitride is selected for the insulating protective film31, the film stress of the insulating protective film31can be adjusted. In addition, a film composed of silicon nitride has excellent resistance to moisture.

An insulating layer32is formed on the insulating protective film31so as to surround each of the layers between the p-type contact layer18and the n-type cladding layer14. The material of the insulating layer32is an insulating resin such as polyimide.

The anode electrode pad41is formed so as to be interposed between two cathode electrode pads51on the surface of the insulating layer32. The electrode pads (anode electrode pad41and cathode electrode pads51) are formed for the purpose of wire bonding. The anode electrode pad41is electrically connected to the anode ohmic electrode42via the anode routing wiring line43. The cathode electrode pads51are electrically connected to the cathode ohmic electrode52via the cathode routing wiring lines53.

By forming the electrode pads on the insulating layer32, which has a certain thickness, parasitic capacitances generated between the electrode pads and the n-type DBR layer13are reduced. Thus, distortion of the waveform of a driving signal can be reduced when a driving signal (not illustrated) is input to the electrode pads of the VCSEL elements1to3. However, the insulating layer32can be omitted.

FIG. 5is a circuit diagram that schematically illustrates the configuration of the VCSEL array901illustrated inFIG. 1Aat the time of a burn-in test. Referring toFIG. 5, a burn-in apparatus65includes a current source64and a pair of probes63. The current source64supplies a load current with a magnitude of 5I between the probes63in order to supply a load current I to each VCSEL column. The probes63are electrically connected to the dummy pads71and72.

As a result of forming the dummy pads71and72, there is no need for the probes63to physically contact the electrode pads (refer toFIG. 2). Consequently, the electrode pads can be prevented from being damaged. In order to make contact with the probes63easy, it is preferable that the size of the dummy pads71and72be larger than the size of the electrode pads (typically less than 100 μm×100 μm) and for example is 200 μm×200 μm or more.

By applying a load voltage between the dummy pads71and72, a load current I can be supplied to all of the VCSEL element columns101to105. Consequently, the number of probes can be reduced compared with the case where a load current is supplied to each VCSEL element. Therefore, the cost of the burn-in apparatus can be reduced.

InFIGS. 1A to 5, a VCSEL array is illustrated in which VCSEL elements are arranged in a 5×5 matrix in a quadrangular region. However, the configuration of the VCSEL array is not limited to this configuration and it is sufficient that a matrix larger than a 2×2 matrix be adopted. The number of VCSEL elements is appropriately decided upon in accordance with the specifications of the burn-in apparatus65, for example, the number of probes63or the value of the load current or load voltage that can be supplied by the current source64.

FIG. 6Aillustrates the path (represented by a solid line) of a load current If in a VCSEL array for comparison.FIG. 6Billustrates the path of a load current If in the VCSEL element column101illustrated inFIG. 3.

The structure of the VCSEL element column illustrated inFIG. 6Adiffers from the structure of the VCSEL element column101in that a base substrate111is formed instead of the base substrate11, an n-type-conductivity semiconductor layer112is formed instead of the n-type contact layer12and the insulating grooves91and92are not formed. The base substrate111is not particularly limited to having a semi-insulating property. The structures of other parts of the VCSEL element column illustrated inFIG. 6Aare the same as the structures of the corresponding parts of the VCSEL element column101and therefore a detailed description thereof will not be repeated.

Referring toFIGS. 2 to 4 and 6A, the load current I is supplied to the anode electrode pad41of the VCSEL element2via the series wiring line61. Inside the VCSEL element2, the load current I reaches the n-type conductive semiconductor layer112along a path of anode electrode pad41-anode routing wiring line43-anode ohmic electrode42-p-type contact layer18-p-type DBR layer17-current constriction layer19-p-type cladding layer16-active layer15-n-type cladding layer-n-type DBR layer13. The load current I is additionally supplied to the VCSEL element1along a path of n-type conductive semiconductor layer112-cathode ohmic electrode52-series wiring line61.

In the structure illustrated inFIG. 6A, the VCSEL elements are connected to each other by the n-type-conductivity semiconductor layer112formed on the base substrate111. Therefore, not all of the load current I that reaches the n-type conductive semiconductor layer112flows to the cathode ohmic electrode52. Part of the load current I leaks to the VCSEL element1via the n-type-conductivity semiconductor layer112as a leakage current (indicated by broken line). As a result, the load currents I of the individual VCSEL elements are not uniform.

On the other hand, referring toFIGS. 2 to 4 and 6B, according to the first embodiment, the electrical insulation property between adjacent VCSEL elements is strengthened by the semi-insulating base substrate11and the insulating grooves91and92. Consequently, it is difficult for a leakage current to flow via a conductive or semi-conductive semiconductor layer on the base substrate11. Therefore, a uniform load current I can be simultaneously supplied to a plurality of VCSEL elements in the same VCSEL element column. Thus, a burn-in test can be accurately performed under the same load conditions (load current conditions).

Second Embodiment

In the first embodiment, the load conditions are the same for a plurality of VCSEL elements in the same VCSEL element column. According to a second embodiment, the load conditions can be made to be the same for different VCSEL element columns.

FIG. 7is a plan view of a VCSEL array according to the second embodiment of the present disclosure.FIG. 7is to be contrasted withFIG. 1A.

Referring toFIG. 7, the configuration of a VCSEL array902differs from the configuration of the VCSEL array901(refer toFIG. 1A) in that the dummy pads71and72are arranged on a diagonal line L1extending through the VCSEL element columns101to105. In other words, the dummy pads71and72are arranged in the vicinities of corners C1and C2located on the diagonal line L1among corners C1to C4(first to fourth corners) corresponding to the four corners of a quadrangular region in which the VCSEL elements are arranged. The configurations of other parts of the VCSEL array902are the same as the configurations of the corresponding parts of the VCSEL array901and therefore a detailed description thereof will not be repeated. InFIG. 7, in order to prevent the drawing from becoming complicated, the insulating grooves91and92are not illustrated.

FIG. 8Ais an equivalent circuit diagram that illustrates the path of a load current in the VCSEL array901illustrated inFIG. 1A.FIG. 8Bis an equivalent circuit diagram that illustrates the path of a load current in the VCSEL array902illustrated inFIG. 7.

Referring toFIGS. 1A and 8A, the dummy pads71and72of the VCSEL array901are arranged in the column direction (x direction). Accordingly, the load current that flows through the VCSEL element column101flows along a path P1(represented by a solid line) of dummy pad71-VCSEL element column101-dummy pad72. That is, since there are no resistances included in the path P1, voltage drops at resistances do not occur when the load current flows along the path P1. Therefore, if the potentials of the dummy pads71and72are respectively represented by V1 and V2, the potential difference between the dummy pads71and72on the path P1is expressed by (V1−V2).

On the other hand, a load current that flows through the VCSEL element column105flows along a path P5(represented by a dotted line) of dummy pad71-resistance R31-resistance R32-resistance R33-resistance R34-VCSEL element column105-resistance R44-resistance R43-resistance R42-resistance R41-dummy pad72. That is, since there are eight resistances included along the path P5, voltage drops corresponding to the eight resistance components occur when the load current flows along the path P5. The resistance values of all the resistances are the same. Therefore, if the sum of voltage drops at the resistances R31to R34is denoted by α, the sum of the voltage drops at the resistances R41to R44is also α. Therefore, the potential difference between the dummy pads71and72along the path P5is expressed by (V1−V2−2α).

Thus, the load current flows through different numbers of resistances along the path P1and along the path P5in the arrangement of the dummy pads71and72in the first embodiment. Consequently, there are different load voltages in the VCSEL element columns101and105.

In contrast to this, referring toFIGS. 7 and 8B, in the VCSEL array902, the dummy pads71and72are arranged on the diagonal line L1. Consequently, the load current that flows through the VCSEL element column101flows along a path P1(represented by a solid line) of dummy pad71-VCSEL element column101-resistance R41-resistance R42-resistance R43-resistance R44-dummy pad72. That is, four resistances are included along the path P1.

In addition, the load current that flows through the VCSEL element column105flows along a path P5(represented by a dotted line) of the dummy pad71-resistance R31-resistance R32-resistance R33-resistance R34-VCSEL element column105-dummy pad72. That is, four resistances are included along the path P5.

The sum of the voltage drops at the resistances R41to R44on the path P1and the sum of the voltage drops at the resistances R31to R34on the path P5are a and are equal to each other. Therefore, the potential difference between the dummy pads71and72along the path P1and the potential difference between the dummy pads71and72along the path P5are the same and are expressed by (V1−V2−α).

As described above, according to the second embodiment, the dummy pads71and72are arranged on the diagonal line L1. In addition, the VCSEL element columns101and105and the parallel wiring lines73and74are symmetrically arranged about an axis of symmetry L2that passes through a center point O of the quadrangular shape in the column direction (x direction). Accordingly, the sizes of the voltage drops at the resistances are the same along the paths P1and P5. Therefore, the load conditions can be made the same for the VCSEL element columns101and105. Furthermore, the VCSEL element columns102to104are also similarly symmetrically arranged about the axis of symmetry L2. Consequently, although the description will not be repeated, the load conditions are also the same for the VCSEL element columns102to104.

Third Embodiment

In the second embodiment, the load conditions are the same for VCSEL element columns symmetrically positioned about the axis of symmetry L2. According to a third embodiment, the load conditions can be made to be the same for all of the VCSEL element columns.

FIG. 9is a plan view of a VCSEL array according to the third embodiment of the present disclosure. Referring toFIG. 9, the wiring line width of the parallel wiring line73is set so as to become smaller in order of the wiring line portions731to734. Thus, the resistance value of the parallel wiring line73becomes larger in this order. On the other hand, the wiring line width of the parallel wiring line74is set so as to become larger in the order of the wiring line portions741to744. Thus, the resistance value of the parallel wiring line74becomes smaller in this order. The configurations of other parts of a VCSEL array903are the same as the configurations of the corresponding parts of the VCSEL array902(refer toFIG. 7) and therefore detailed description thereof will not be repeated.

FIG. 10Ais an equivalent circuit diagram of the VCSEL array902illustrated inFIG. 7.FIG. 10Bis an equivalent circuit diagram of the VCSEL array903illustrated inFIG. 9.

Referring toFIG. 10A, a load current with a magnitude of 5I is supplied to the VCSEL array902via the dummy pad71. A load current I is equally distributed to each of the VCSEL element columns101to105. Accordingly, load currents of 4I, 3I, and I respectively flow through the resistances R31to R34(refer toFIG. 8B). The resistance values of the resistances are the same, namely, R. Therefore, the sizes of the voltage drops at the resistances R31to R34are 4RI, 3RI, 2RI and RI, respectively.

On the other hand, load currents of I, 2I, 3I and 4I respectively flow through the resistances R41to R44(refer toFIG. 8B). Therefore, the sizes of the voltage drops at the resistances R41to R44are RI, 2RI, 3RI and 4RI, respectively. Thus, in the VCSEL array902, there is a voltage drop of a different size at every resistance. The potentials at the intersection points are noted in the vicinities of the intersection points between the VCSEL element columns101to105and the resistances in the figure.

The potential difference of the VCSEL element column101(potential difference between the VCSEL elements at the two ends of the VCSEL element column101) and the potential difference of the VCSEL element column105are both calculated as (V1−V2−10RI). However, the potential difference of the VCSEL element column102and the potential difference of the VCSEL element column104are calculated as (V1−V2−13RI). In addition, the potential difference of the VCSEL element column103is calculated as (V1−V2−14RI). Thus, in the second embodiment, the potential differences of the VCSEL element columns are different from one another.

In contrast to this, referring toFIG. 10B, the resistance values of the resistances in the VCSEL array903are each set by adjusting the wiring line width on the basis of a simulation for example so as to be inversely proportional to the value of the load current that will flow through the resistance. That is, the resistance value of the resistances R34and R41is 4R. The resistance value of the resistances R33and R42is 2R. The resistance value of the resistances R32and R43is (4/3)R. The resistance value of the resistances R31and R44is R. By setting the resistance values in this way, the sizes of voltage drops at the resistances become equal to one another, namely, 4RI. As a result, the potential differences of all of the VCSEL element columns become equal to one another, namely, (V1−V2−16RI).

As described above, according to the third embodiment, the resistance values of the wiring line portions of the parallel wiring lines are each set so as to be inversely proportional to the value of the load current that will flow through the wiring line portion. Thus, the sizes of the voltage drops at the resistance components of the wiring line portions become equal to one another. Therefore, the load conditions of all the VCSEL element columns can be made to be the same as one another.

The method of adjusting the resistance values of the wiring line portions is not limited to adjusting the wiring line width. The resistance values of the wiring line portions can also be adjusted by changing the thicknesses or the materials of the wiring line portions for example. However, if the wiring line width is adjusted, a plurality of wiring line portions of different wiring line widths can be formed in a single electrode forming process and therefore the manufacturing process can be simplified.

Fourth Embodiment

FIG. 11Ais an enlarged view of the VCSEL array902illustrated inFIG. 7.FIG. 11Bis an enlarged view of a VCSEL array according to a fourth embodiment of the present disclosure. The configurations of parts of a VCSEL array904that are not illustrated are the same as the configurations of the corresponding parts of the VCSEL array902.

Referring toFIG. 11A, the parallel wiring line74is connected to the cathode ohmic electrodes52of the VCSEL elements. With this connection configuration, it is necessary that a region in which to arrange the parallel wiring line74be secured between the VCSEL element columns101to105and the dummy pad72in the column direction (x direction).

In contrast to this, referring toFIG. 11B, a VCSEL array904is provided with a parallel wiring line75instead of the parallel wiring line74. The parallel wiring line75includes wiring line portions751to754. Each of the wiring line portions751to754is arranged between one cathode electrode pad51and another cathode electrode pad51of two VCSEL elements that are adjacent to each other in the row direction (y direction).

According to the fourth embodiment, it is not necessary to secure a region in which to arrange the parallel wiring line outside of the quadrangular region in which the VCSEL elements are arranged. Therefore, the area of the VCSEL array can be reduced. Consequently, with the VCSEL array904, a greater number of VCSEL elements can be arranged within a fixed area compared with the VCSEL array902. Therefore, the number of VCSEL elements obtained per wafer is increased. Therefore, the cost per unit VCSEL element can be reduced.

Fifth Embodiment

FIG. 12illustrates a state in which six of the VCSEL arrays902illustrated inFIG. 7are arranged. Referring toFIG. 12, dead spaces76are generated between every two of the VCSEL arrays902arranged in the column direction (x direction). No VCSEL elements or any type of wiring line is arranged in the dead spaces76. Therefore, the number of VCSEL elements obtained per wafer is reduced by an amount corresponding to the area of the dead spaces76.

FIG. 13Ais a plan view of a VCSEL array according to a fifth embodiment of the present disclosure.FIG. 13Bis an equivalent circuit diagram of the VCSEL array according to the fifth embodiment of the present disclosure.FIG. 13Ais to be contrasted withFIG. 11B.

Referring toFIG. 13A, the configuration of the VCSEL array905differs from the configuration of the VCSEL array904(refer toFIG. 11B) in that VCSEL element columns114and115are provided instead of the VCSEL element columns104and105.

The number n of VCSEL elements included in each of the VCSEL element column114and115(n=4) is smaller than the number m of VCSEL elements included in each of the VCSEL element columns101to103(m=5). The dummy pad72is arranged in place of one VCSEL element that would have otherwise been included in the VCSEL element column114and one VCSEL element that would have otherwise been included in the VCSEL element column115. In other words, the dummy pad72is arranged in a region corresponding to the areas of VCSEL elements in the vicinity of the VCSEL element columns114and115. The rest of the configuration of the VCSEL array905is the same as that of the VCSEL array904and a detailed description thereof will not be repeated.

The VCSEL element columns101to103correspond to a “first vertical cavity surface emitting laser element column” in the present disclosure. The VCSEL element columns114and115correspond to a “second vertical cavity surface emitting laser element column” in the present disclosure. In addition, although a case in which the dummy pad72is arranged has been described, the dummy pad71could also be similarly arranged.

FIG. 14illustrates a state in which six of the VCSEL arrays905illustrated inFIG. 13Aare arranged.FIG. 14is to be contrasted withFIG. 12.

Referring toFIG. 14, as a result of arranging the dummy pads72in regions corresponding to the areas of VCSEL elements as described above, a dead space is no longer generated between two VCSEL arrays905arranged in the column direction (x direction). In addition, arranging the dummy pads71in spaces adjacent to the dummy pads72in the row direction (y direction) also contributes to the reduction of dead spaces. Therefore, with the VCSEL array905, a greater number of VCSEL arrays can be arranged on the base substrate11(wafer) compared with the VCSEL array902(refer toFIG. 11A). As a result, the cost per unit VCSEL element can be reduced.

Sixth Embodiment

Returning toFIG. 13B, the number of VCSEL elements included in each of the VCSEL element columns114and115is smaller than the number of VCSEL elements included in each of the VCSEL element columns101to103. Accordingly, the load voltage applied to each VCSEL element is higher in the VCSEL element columns114and115than in the VCSEL element columns101to103. Therefore, the load conditions are different in the VCSEL element columns101to103and in the VCSEL element columns114and115.

FIG. 15Ais a plan view of a VCSEL array according to a sixth embodiment of the present disclosure.FIG. 15Bis an equivalent circuit diagram of the VCSEL array according to the sixth embodiment of the present disclosure.FIGS. 15A and 15Bare to be contrasted withFIGS. 13A and 13B.

Referring toFIG. 15A, VCSEL element columns124and125are different to the VCSEL element columns114and115(refer toFIG. 13A) in that the VCSEL element columns124and125each include a dummy element77. The dummy element77included in the VCSEL element column124is electrically connected between the dummy pad72and the VCSEL elements inside the VCSEL element column124. The dummy element77included in the VCSEL element column125is electrically connected between the dummy pad72and the VCSEL elements inside the VCSEL element column125.

The dummy elements77are elements that are formed in order to generate a voltage drop and are for example diodes. The sizes of the voltage drops at the dummy elements77correspond to the sizes of voltage drops of VCSEL elements corresponding to the region in which the dummy pad72is arranged.

According to the sixth embodiment, the load voltage applied to each VCSEL element is the same in the VCSEL element columns101to103and in the VCSEL element column124and125. Therefore, along with it being possible to arrange a plurality of VCSEL arrays without the generation of dead spaces, the load conditions can be made the same for all the VCSEL element columns.

Method of Manufacturing VCSEL Array

Hereafter, a method of manufacturing the VCSEL arrays901to906according to the first to sixth embodiments will be described. The methods of manufacturing the VCSEL arrays901to906are the same and therefore a method of manufacturing the VCSEL array901will be described as a representative example.

FIG. 16is a flowchart for explaining the method of manufacturing the VCSEL array901illustrated inFIG. 1A.FIGS. 17 to 27are schematic step diagrams for the method of manufacturing the VCSEL array901illustrated inFIG. 1A. In the following description, the corresponding steps of the flowchart illustrated inFIG. 16are given in brackets.

Referring toFIG. 17, first, the n-type contact layer12, the n-type DBR layer13, the n-type cladding layer14, the active layer15, the p-type cladding layer16, the current constriction layer19, the p-type DBR layer17and the p-type contact layer18are formed in order from the surface of the base substrate11by epitaxial growth (step S101).

For example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy may be employed as the method of epitaxial growth. The temperature and duration of the epitaxial growth are decided upon in accordance with the growth method, the type of the base substrate11, or the type and thickness of each layer, or the carrier density and so forth.

Referring toFIG. 18, the pattern of each layer between the p-type contact layer18and the n-type cladding layer14is formed using photolithography for example. In the region outside the region where this pattern is formed, the layers from the p-type contact layer18up to the n-type cladding layer14are removed sequentially by using dry etching for example such that the n-type DBR layer13is exposed. In this way, a mesa structure81is formed (step S102).

Referring toFIG. 19, oxidation is made to selectively proceed from the outer periphery of the current constriction layer19by performing heating at 400° C. or more in a steam atmosphere. In this way, the oxidized region191and the non-oxidized region192are formed (step S103).

Referring toFIG. 20, the anode ohmic electrode42is formed on the p-type contact layer18(step S104).

Referring toFIG. 21, in this embodiment, the n-type contact layer12is formed closer toward the rear surface side of the base substrate11than the n-type DBR layer13is. Therefore, a recessed pattern82is formed by photolithography and etching. As a result, the n-type contact layer12is exposed (step S105).

Referring toFIG. 22, the cathode ohmic electrode52is formed on the exposed part of the n-type contact layer12(step S106).

Referring toFIG. 24, the insulating protective film31is formed on the surface of each of the structures formed in the above-described steps except for the anode ohmic electrode42and the cathode ohmic electrode52(step S108). More specifically, SiN can be deposited by using chemical vapor deposition (CVD) for example.

If the insulating protective film31is not formed, there is a possibility that a very small leakage current (refer toFIG. 5) will flow along the exposed surfaces of the insulating grooves91and92. By carrying out a passivation treatment (treatment of step S108), a leakage current that flows along the surfaces of the insulating grooves91can be suppressed and therefore the isolation between VCSEL elements that are adjacent to each other with the insulating grooves91and92therebetween can be strengthened even more.

It is preferable that the cross-sectional shape of the insulating grooves92be a normal tapered shape. In other words, it is preferable that the cross-sectional area of the insulating grooves92become smaller in a direction from the front surface side toward the rear surface side of the base substrate11(negative z direction inFIG. 4). In this way, the coverage of the insulating protective film31on side walls921of the insulating grooves92can be improved. Although the description will not be repeated, the same is true for the insulating grooves91.

Referring toFIG. 25, the insulating layer32is formed in a region that is on the insulating protective film31and is close to the mesa structure81(step S109). In order to form the insulating layer32, for example polyimide, which is a photosensitive resin, can be applied to the insulating protective film31by using spin coating. After that, photolithography and curing are performed.

Referring toFIG. 26, electrode pads and routing wiring lines for wire bonding (anode routing wiring line43and cathode routing wiring lines53, refer toFIG. 2for both) are formed (step S110). In addition, in this embodiment, in order to reduce the workload, the series wiring lines61and the parallel wiring lines73and74are formed together with the electrode pads and routing wiring lines.

In order to secure coverage on the side walls921of the insulating grooves92, it is preferable that the series wiring lines61be formed using sputtering deposition, plating or a combination of these techniques. For example, titanium (Ti) and gold (Au) can be used as the material of the series wiring lines61.

Next, a burn-in test is carried out by supplying a load current I from the external current source64(refer toFIG. 5). Tests other than the burn-in test may be carried out as needed (step S111).

Referring toFIG. 27, after the tests are finished, the series wiring lines61and the parallel wiring lines73and74are removed by photolithography and etching (step S112). At the time of etching, it is preferable that only the series wiring lines61and the parallel wiring lines73and74be removed without affecting the insulating protective film31. As an example, a potassium iodide (KI) solution and a fluoro-nitric acid (HF+HNO3) solution selectively remove parts formed of Au and parts formed of Ti respectively of the series wiring lines and the parallel wiring lines73and74. Therefore, by forming the insulating protective film31using SiN, it is possible to remove only the series wiring lines61and the parallel wiring lines73and74without affecting the insulating protective film31.

Finally, the VCSEL array901is divided into individual VCSEL elements by being cut with a dicing machine for example (step S113). In order to make efficient use of the area of the wafer on which the VCSEL array901is formed (that is, the area of the base substrate11), the regions to be cut with the dicing machine can also serve as the regions in which the insulating grooves91and92are formed. At this time, it is preferable that the insulating protective film31formed on the insulating grooves91and92be removed. The insulating protective film31can be removed by performing photolithography and then performing etching for example. In this way, wearing down of the blade of the dicing machine can be suppressed, and the impact of the dicing machine transmitted to the VCSEL elements can be softened. Once the processing of step S113is complete, the series of processing steps is complete.

The wafer may be divided into individual VCSEL elements by being cut using a dicing machine (step S113) in a state where the processing for removing the series wiring lines61and the parallel wiring lines73and74(processing of step S112) has not been performed and the series wiring lines61and the parallel wiring lines73and74remain. Thus, traces of the series wiring lines61and the parallel wiring lines73and74cut by the dicing machine can be confirmed in the individual VCSEL elements. For example, parts of the wiring lines61between the elements illustrated inFIG. 2remain in the individual VCSEL elements.

In addition, before the processing of dividing the wafer into individual VCSEL elements (processing of step S113), a sticker, tape or the like can be stuck to the entire back surface of the wafer. Despite the wafer being cut with the dicing machine, the sticker or the tape will remain on the rear surface of the wafer without being cut. Thus, the VCSEL elements obtained by the wafer being divided into individual elements can be collectively handled in a state in which they are arranged in an array pattern. Therefore, it is easy to handle the VCSEL elements when for example shipping, transporting or mounting the VCSEL elements.

Modification 1 of First to Sixth Embodiments

In the first to sixth embodiments, a case is described in which the VCSEL array is provided with insulating grooves. However, a structure for electrically insulating the VCSEL elements from one another is not limited to this structure.

FIG. 28is an enlarged view of the cross section of a VCSEL element column having a different structure to the VCSEL element column101illustrated inFIG. 3. Referring toFIG. 28, a VCSEL element column201differs from the VCSEL element column101in that high-resistance regions93are provided instead of the insulating grooves91and92. The high-resistance regions93correspond to an “insulating region” in the present disclosure.

The high-resistance regions93are formed using ion implantation. Thus, the electrical resistivity of the high-resistance regions93is higher than the electrical resistivity of the base substrate11(for example, 1.0×107Ω·cm or higher). The structures of other parts of the VCSEL element column201are the same as the structures of the corresponding parts of the VCSEL element column101and therefore a detailed description thereof will not be repeated. The high-resistance regions also have the characteristics of the dummy pads or the wiring line portions of the parallel wiring lines described in the first to sixth embodiments, and therefore the same effect as in the first to sixth embodiments can be obtained.

Modification 2 of First to Sixth Embodiments

In the first to sixth embodiments, a semi-insulating semiconductor substrate is used as the base substrate. However, the type of base substrate is not limited to a semi-insulating semiconductor substrate. A conductive or semi-conductive semiconductor substrate can also be used as the base substrate.

FIG. 29is an enlarged view of the cross section of a VCSEL element column having a further different structure to the VCSEL element column101illustrated inFIG. 3. Referring toFIG. 29, a VCSEL element column202differs from the VCSEL element column101in that a conductive or semi-conductive base substrate113is provided instead of the semi-insulating base substrate11and in that a p-type-conductivity semiconductor layer116is provided between the base substrate113and the n-type contact layer12.

The p-type-conductivity semiconductor layer116and the n-type contact layer12form a pn junction. The forward direction of the pn junction is opposite to the direction of the load current I (negative z direction, refer toFIG. 5). Accordingly, it is difficult for the load current I to reach the base substrate113. Therefore, it is difficult for a leakage current to flow between the VCSEL elements. The structures of other parts of the VCSEL element column202are the same as the structures of the corresponding parts of the VCSEL element column101and therefore a detailed description thereof will not be repeated.

Modification 1 and modification 2 of the first to sixth embodiments may be combined. That is, the high-resistance regions93(refer toFIG. 28) can also be formed in the structure in which the p-type-conductivity semiconductor layer116is formed on the conductive or semi-conductive base substrate113.

In the first to sixth embodiments, an AlGaAs-based semiconductor material has been described. However, a semiconductor material that can be used in the present disclosure is not limited to this semiconductor material, and other materials such as a GaInP-based, a ZnSSe-based, an InGaN-based, an AlGaN-based, an InGaAs-based, a GaInNAs-based or a GaAsSb-based semiconductor material can also be used in accordance with the emission wavelength.

The presently disclosed embodiments are illustrative in all points and should not be thought of as being limiting. The scope of the present disclosure is defined by the scope of the claims and it is intended that equivalents to the scope of the claims and all modifications within the scope of the claims be included within the scope of the present disclosure.