Foreign objection detection sensing circuit for wireless power transmission systems

A wireless-power-circuit is operable in transceiver-mode and Q-factor-measurement-mode, and includes a bridge coupled to a coil, and having an output coupled to a rectified-voltage node. An excitation circuit, when in Q-factor-measurement-mode, drives the coil with a pulsed signal. A protection circuit couples the coil to a first node when in Q-factor-measurement-mode and decouples the coil from the first node when in transceiver-mode. A Q-factor sensing circuit includes an amplifier having inputs coupled to the first node and a common mode voltage (Vcm), and generating an output signal having an output voltage. A comparator generates a comparison output indicating Vcm crossing of a voltage at the first terminal of the coil, a processing circuit generating an enable signal based upon the comparison output, and an analog-to-digital-converter, when enabled, digitizing the output voltage for use in calculating a Q-factor of the coil.

TECHNICAL FIELD

This disclosure is related to the field of wireless power transmission and, in particular, to a foreign objection detection sensing circuit for wireless power transmission systems.

BACKGROUND

Portable electronic devices, such as smartphones, smartwatches, audio output devices (earbuds, headphones), and wearables operate on battery power, not from wired power transmitted thereto over wired transmission lines and distribution systems. The batteries used for such devices are typically rechargeable and, therefore, a way to recharge the power of such batteries is necessary.

Most portable electronic devices include a charging port, typically conforming to the Micro USB or USB-C standards, into which a power cord connected to a power source can be inserted to provide for recharging of their batteries. However, such charging ports may make it difficult to enhance the water resistance of the electronic device, and are subject to damage from repeated use. In addition, some smaller portable electronic devices (for example, earbuds and smartwatches) may lack the available space to provide for a charging port. Still further, some users may find it cumbersome to plug a power cord into the charging port of an electronic device to charge the battery of that device.

Therefore, to address these issues, wireless power transmission has been developed. As shown inFIG. 1, a wireless power transmission system10may be comprised of a first device11and a second device15. The first device11may be a device capable of wireless power transmission (for example, a smartphone) and/or wireless power reception (for example, a device to be wirelessly charged, such as a charging case for a pair of wireless earbuds or an active stylus), and the second device15may be a device capable of both wireless power transmission and wireless power reception, such as a smartphone.

The first device11includes a coil Ls (considered to be a secondary when receiving power; the capacitance Cs represents a tuning capacitance for the coil Ls) in which a time-varying current is induced by a time-varying electric field when receiving power, and hardware12that rectifies, regulates, and makes use of the time-varying current induced in the coil Ls to provide power to the device11, for example to charge its battery.

The second device15includes a controlled switching bridge circuit (operable as either a bridge rectifier or a DC-AC inverter)16coupled to a transceiver coil Lxcvr at nodes Ac1and Ac2, with a discrete capacitor Cxcvr being used to tune the second device15. The controlled switching bridge circuit16is comprised of transistors T1-T4controlled by gate voltages G1-G4.

A tank capacitor Ctank is coupled between node Nin and node N. A voltage regulator17has an input coupled to node Nin and an output coupled to node Nout. A battery18is selectively coupled between node Nout and node N by a switch SW1, and is selectively coupled between the node N and node Nin by a switch SW2. The switches SW1and SW2operate out of phase with one another; switch SW1is closed while switch SW2is opened when the second device15operates as a receiver in a power reception mode with the circuit16functioning as an AC-DC rectifier and the regulator functioning to generate the regulated voltage Vreg for charging the battery of the second device15, and switch SW1is opened while switch SW2is closed when the second device15operates as a transmitter in a power transmission mode with the circuit16functioning as a DC-AC inverter powered by the battery18in a mode to transfer power supplied by battery18to the first device11. A controller19generates the gate voltages G1-G4for controlling the bridge16to operate in the desired rectifier/inverter mode.

When the second device15operates as a receiver, the controlled switching bridge circuit16rectifies the AC current flowing in transceiver coil Lxcvr to produce a DC current that charges the tank capacitor Ctank connected to the node Nin, and a rectified voltage Vrect is formed across the tank capacitor Ctank. The voltage regulator17produces a regulated output voltage Vreg at its output node Nout from that rectified voltage Vrect, which is provided to the battery18to thereby charge the battery18.

When the second device15operates as a transmitter, the voltage of the battery18is applied to the node Nin by switch SW2and becomes the voltage Vrect. Then, the gate voltages G1-G4are driven by the controller19so as to generate a time-varying current flowing through the transceiver coil Lxcvr.

During wireless power transmission, a danger arises in that a conductive foreign object20may inadvertently be physically present between the first device11and second device15, such as shown inFIG. 2. This is a concern because a conductive foreign object may have eddy currents induced therein by the device acting as a transmitter, which are dissipated as heat that can damage the devices. Therefore, it is desired for there to be a way to detect the presence of a conductive foreign object so that the wireless power transfer can be aborted or the amount of power transferred can be moderated. In the context of wireless power transmission system, foreign objects are electrically-conductive materials that are placed in the field, such as coins, keys, paperclips, etc., and that are not part of the wireless charging system and are not protected by the shielding in either the transmitting or receiving device. The alternating magnetic field between a transmitter and a receiver can induce eddy currents in these electrically conductive materials that are exposed to the field, the eddy currents cause those materials to heat up. Therefore, it is desired for these objects to be detected and removed from a wireless power transmission system for efficient power deliver and safety of operation.

The quality factor (Q-factor) of the second device15, an indication of the efficiency of the power transferred thereto or thereby, may be measured by exciting with the time-varying electric field generated by the transceiver15while measuring the peak voltage developed at the node AC1, and then next damped peak voltage at same node AC1. To accommodate this, a Q-factor sensing block9is coupled to the coil Lxcvr. Q-factor measurement cycles may be interleaved with power transmission/reception cycles, but do not occur simultaneously.

Since the mutual induction between the coils Ls and Lxcvr will change dependent upon the condition of the system10, the Q-factor of Lxcvr will change dependent upon the condition of the system10. Therefore, from the Q-factor of Lxcvr, the second device15can infer the condition of the system10. Possible relevant conditions of the system10, when the second device15is acting as a transmitter, include: (i) both the first device11and the second device15being in proximity to one another, but not a foreign object20, (ii) the second device15being in proximity to the foreign object20but not the first device11, (iii) the second device15being in proximity to neither the first device11nor the foreign object20, and (iv) both the first device11and the second device15being in proximity to one another as well as to the foreign object20.

By modeling the wireless power transmission system10as a transformer, Q-factor curves for these different system conditions can be inferred. For example, with additional reference toFIG. 3, in case (i), the resonance amplitude of the coil Lxcvr will be higher than in other conditions and the resonance frequency of the system10will be lower than in other conditions, as illustrated in the Q-factor curve labeled as Fr_tx+rx. Similarly, in case (ii), the resonance amplitude of the coil Lxcvr is lower than in other conditions, and the resonance frequency of the system10is higher than in other conditions, as illustrated in the Q-factor curve labeled as Fr_tx+fo. For case (iii), the resonance amplitude of the coil Lxcvr is less than in case (i) but greater than in case (iii) while the resonance frequency of the coil Lxcvr is greater than in case (i) but less than in case (iii), as illustrated in the Q-factor curve labeled as Fr_tx. Case (iv) yields a similar resonance frequency as case (iii), but a slightly lesser resonance amplitude, as illustrated in the Q-factor curve labeled as Fr_tx+rx+fo. Therefore, by measuring the Q-factor of the coil Lxcvr, the second device15may determine the current condition of the system10and may take appropriate action (e.g., transmit at full power, transmit at a lesser power, cease transmission, etc).

Existing techniques for Q-factor measurement have proven to have insufficient accuracy to be able to use the results to properly discern case (ii) from case (iii), and to be able to discern case (i) from case (iv), since in case (ii) a foreign object is present but in case (iii) the foreign object is not present and since in case (iv) the foreign object is present but in case (i) the foreign object is not present. Therefore, further development is needed.

SUMMARY

Disclosed herein is a wireless power circuit operable in a transceiver mode and in a Q-factor measurement mode. The wireless power circuit includes: a coil having first and second terminals; a bridge rectifier having a first input and a second input coupled to the first terminal and second terminal of the coil, respectively, and having an output coupled to a rectified voltage node; an excitation circuit coupled to the first terminal of the coil and configured to, when in the Q-factor measurement mode, drive the coil with a pulsed signal; and a protection circuit coupling the first terminal of the coil to a first node when in the Q-factor measurement mode and decoupling the first terminal of the coil from the first node when in the transceiver mode. In addition, the wireless power circuit includes a Q-factor sensing circuit with: an amplifier having inputs coupled to the first node and a common mode voltage, and generating an output signal having an output voltage; a comparator having inputs coupled to a second node and the common mode voltage, and generating a comparison output indicating a VCM crossing of a voltage at the first terminal of the coil; a processing circuit configured to receive the comparison output and generate an enable signal based thereupon; and an analog to digital converter configured to, when enabled by the enable signal from the processing circuit, digitize the output voltage and provide the digitized output voltage to the processing circuit for use in calculating a Q-factor of the coil.

The comparator may be configured to have a rising threshold equal to a common mode voltage, a falling threshold equal to the common mode voltage, and hysteresis, such that when voltage at the second node is falling, an effective rising threshold is equal to the rising threshold plus the hysteresis and an effective falling threshold is equal to the falling threshold, and such that when voltage at the second node is rising, the effective falling threshold is equal to the falling threshold less the hysteresis and the effective rising threshold is equal to the rising threshold.

The processing circuit may calculate the Q-factor of the coil based upon an amplitude of a first sample of the output voltage taken at a first peak of the output voltage, and an amplitude of at least one other sample of the output voltage taken at at least one other peak of the output voltage.

The processing circuit may calculate the Q-factor as:

Q=Π⁡(N-1)ln⁢(A⁢1⁢/A⁢N)
where A1 is the first sample of the output voltage taken at the first peak of the output voltage, and AN is the Nth sample of the output voltage taken at an Nth peak of the output voltage. The processing circuit may calculate the Q-factor of the coil based upon a difference between a first sample of the output voltage taken at a first peak of the output voltage and a second sample of the output voltage taken at a first trough of the output voltage, and a difference between a third sample of the output voltage taken at another peak of the output voltage and a fourth sample of the output voltage taken at another trough of the output voltage.

The processing circuit may calculate the Q-factor as:

Q=Π⁡(N-1)ln⁡(A⁢1⁢a-A⁢1⁢bA⁢N⁢a-A⁢N⁢b)
where A1s is the first sample, A1b is the second sample, ANa is the third sample, and ANb is the fourth sample.

The excitation circuit may include: a driver configured to receive a driving signal and to generate an excitation signal based thereupon; and a p-channel transistor having a source couples to a supply voltage, a drain coupled to an anode of a diode through a resistance, and a gate coupled to receive the excitation signal; with the diode having a cathode coupled to the first terminal of the coil.

The amplifier may have a non-inverting terminal coupled to the common mode voltage, an inverting terminal capacitively coupled to the first node by a first capacitor, and an output coupled to the non-inverting terminal by a second capacitor, the output also coupled to the analog to digital converter.

The comparator may have a non-inverting terminal coupled to the first node, an inverting terminal coupled to the common mode voltage, and an output at which the comparison output is generated.

A first resistance may be coupled between a supply voltage and the first node, and a second resistance may be coupled between the first node and ground.

A third resistance may be coupled between a supply voltage and a second node at which the common mode voltage is produced, and a fourth resistance may be coupled between the second node and ground.

The protection circuit may include a pair of series coupled transistors coupled between the first terminal of the coil and a first node, and having their gates coupled to a Q-factor sensing enable signal that is asserted when in Q-factor sensing mode and otherwise deasserted.

In the Q-factor measurement mode, the processing circuit may be configured to determine that a second wireless power circuit is in proximity to the wireless power circuit but that a foreign object is not present in between the second wireless power circuit and the wireless power circuit, by determining that a frequency of the output signal is less than a known frequency of the output signal in absence of the second wireless power circuit and the foreign object less a margin value. In response, the processing circuit may cause the wireless power circuit to wirelessly transmit power at a full power level.

In the Q-factor measurement mode, the processing circuit may be configured to determine that a second wireless power circuit is in proximity to the wireless power circuit but that a foreign object is present in between the second wireless power circuit and the wireless power circuit, by: determining that a frequency of the output signal is greater than a known frequency of the output signal in absence of a second wireless power circuit and a foreign object plus a margin value; determining that the frequency of the output signal is less than the known frequency of the output signal in the absence of the second wireless power circuit and the foreign object less the margin value; determining whether the Q-factor is less than a Q-factor margin value; determining whether a first sample of the output voltage is less than an amplitude margin value; and determining whether another sample of the output voltage is less than the amplitude margin value. If the Q-factor is less than the Q-factor margin value, the first sample is less than the amplitude margin value, and the other sample is less than the amplitude margin value, the processing circuit causes the wireless power circuit to not wirelessly transmit power. If the Q-factor is not less than the Q-factor margin value, or if the first sample is not less than the amplitude margin value, or if the other sample is not less than the amplitude margin value, the processing circuit causes the wireless power circuit to wirelessly transmit a limited amount of power, the limited amount of power being less than an amount of power that the wireless power circuit would otherwise transmit.

In the Q-factor measurement mode, the processing circuit may be configured to determine that a second wireless power circuit is not in proximity to the wireless power circuit and a foreign object is in proximity to the wireless power circuit, by determining that a frequency of the output signal is greater than a known frequency of the output signal in absence of the second wireless power circuit and the foreign object plus a margin value. In response thereto, the processing circuit may cause the wireless power circuit to not wirelessly transmit power.

In the Q-factor measurement mode, the processing circuit may be configured to determine that a second wireless power circuit is not in proximity to the wireless power circuit and a foreign object is also not in proximity to the wireless power circuit, by determining that a frequency of the output signal is equal to a known frequency of the output signal in absence of the second wireless power circuit and the foreign object.

DETAILED DESCRIPTION

The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

Described herein with reference toFIG. 4is a transceiver device15′, such as may be used with the wireless power transmission system10ofFIG. 1, that incorporates a Q-factor sensor30and an excitation circuit21described herein.

The transceiver device15′ includes a controlled switching bridge circuit (operable as either a bridge rectifier or a DC-AC inverter)16coupled to a transceiver coil Lxcvr at nodes Ac1and Ac2, with the capacitor Cxcvr representing the tuning capacitor to align the impedance matching, and the capacitor Cpar representing the parasitic capacitance purposefully added between nodes Ac1and Ac2to tune the impedance of the system

The controlled switching bridge circuit16is comprised of transistors T1-T4controlled by gate voltages G1-G4. In greater detail: the transistor T1has a drain coupled to node Nin, a source coupled to node Ac1, and a gate coupled to gate voltage G1; the transistor T3has a drain coupled to node Ac1, a source coupled to node N (which may be ground or another reference voltage), and a gate coupled to gate voltage G3; the transistor T2has a drain coupled to node Nin, a source coupled to node Ac2, and a gate coupled to gate voltage G2; and the transistor T4has a drain coupled to node Ac2, a source coupled to node N, and a gate coupled to gate voltage G4.

A tank capacitor Ctank is coupled between node Nin and ground. A voltage regulator17has an input coupled to node Nin and an output coupled to node Nout. A battery18is selectively coupled between node Nout and ground by a switch SW1, and is selectively coupled between node Nin and node Nout by a switch SW2. The switches SW1and SW2operate out of phase with one another; switch SW1is closed while switch SW2is opened when the transceiver device15′ operates as a receiver in a power reception mode with the circuit16functioning as an AC-DC rectifier and the regulator functioning to generate the regulated voltage Vreg for charging the battery18, and switch SW1is opened while switch SW2is closed when the device15′ operates as a transmitter in a power transmission mode with the circuit16functioning as a DC-AC inverter powered by the battery18.

A controller19′ generates the gate voltages G1-G4for controlling the bridge16to operate in the desired rectifier/inverter mode. The controller19′ includes a logic core23generating control signals Gate_G1, Gate_G2, Gate_G3, and Gate_G4, as well as the Q-factor measurement enable signal Q_en, which is inverted to produce signal Q_En_B. A first AND gate31performs a logical-AND operation on the signals Gate_G1and Q_En_B to produce the gate voltage G1. A second AND gate32performs a logical-AND operation on signals Gate_G2and Q_En_B to produce the gate voltage G2. An OR gate33performs a logical-OR on signals Gate_G3and Q_E to produce the gate voltage G3. An OR gate34performs a logical-OR on signals Gate_G4and Q_En to produce the gate voltage G4.

When the transceiver device15′ operates as a receiver, the controlled switching bridge circuit16rectifies the AC current to produce a DC current that charges the tank capacitor Ctank connected to the node Nin, and a rectified voltage Vrect is formed across the tank capacitor Ctank. The voltage regulator17produces a regulated output voltage Vreg at its output node Nout, which is provided to the battery18to thereby charge the battery18.

When the transceiver device15′ operates as a transmitter, the voltage of the battery18is applied to the node Nin by switch SW2and becomes the voltage Vrect. Then, the gate voltages G1-G4are driven by the controller19so as to generate a time-varying current flowing through the transceiver coil Lxcvr. Details of this control scheme may be found in U.S. patent application Ser. No. 16/669,068, filed Oct. 30, 2019, the contents of which are incorporated by reference in its entirety.

An excitation circuit21is coupled to the transceiver coil Lxcvr at node Ac1. The excitation circuit21is comprised of a p-channel transistor MP1having a source coupled to a supply voltage Vdd, a drain coupled to a first terminal of resistor Re, and a gate coupled to a pad Qe to receive the signal Vin_exc as driven by a driver22. The excitation circuit21also includes a diode D1having an anode coupled to a second terminal of the resistor Re and a cathode coupled to the transceiver coil Lxcvr at node Ac1. Note here that the excitation circuit21is off-chip, as well as is the capacitor Cq described below, compared to the other components of the transceiver device15′.

A Q-factor sensing circuit30includes a capacitor Cq coupled between the cathode of diode D and a pad Qs. An n-channel transistor MN1has a drain coupled to the pad Qs, a source coupled to the source of an n-channel transistor MN2, and a gate coupled to the Q-factor measurement enable signal Q_en. The transistor MN2has its source coupled to the source of the transistor MN1, its drain coupled to a tap node N1between resistors R1and R2(which are series coupled between Vdd and ground), and its gate coupled to receive the Q-factor measurement enable signal Q_En. An amplifier26has an inverting input terminal coupled to node N1through a capacitor Cg and has the inverting input terminal further coupled to an output of the amplifier through a capacitor Cf and further has an inverting terminal coupled to receive a common mode voltage Vcm. The capacitors Cg and Cf may be adjustable in some cases, allowing for adjustment of the gain of the amplifier26. An output voltage Vout is produced at the output of the amplifier26. This output voltage Vout is applied to the input of an analog to digital converter (ADC)24which converts the analog output voltage to a digital signal ADCout.

The Q-factor sensing circuit30also includes a comparator27having a non-inverting input terminal coupled to node N1, an inverting input terminal coupled to a tap node N2between resistors R3and R4coupled in series between the supply voltage Vdd and ground as a voltage divider circuit to produce the common mode voltage Vcm at node N2, and an output at which a comparison output signal Comp_Out is generated. A finite state machine (FSM)25has inputs at which the comparison output signal Comp_Out and the digital signal ADCout are received, and outputs a control signal Ctrl to the ADC24as well as the Vin_exc signal. Note that since the capacitance of the capacitors Cg and Cf may be adjustable, permitting programming of the gain of the amplifier26, the resolution of the samples produced by the ADC24may be adjusted as a result.

Also note that the comparator27has rising and falling threshold values dynamically set by hysteresis dependent upon whether the voltage at its input are rising or falling. The comparator has both the comparator rising threshold Vtr and comparator falling threshold Vtl set to Vcm, but with the hysteresis maintained making the actual threshold voltages Vtr and Vtl dynamic, as shown in the graph of the voltage at pad Qs (which will be VLC) inFIG. 5. Therefore, when the voltage VLC is falling, the rising threshold Vtr is set to Vcm+hyseresis (2V+0.05V=2.05V in this example) and the falling threshold Vtl is set to Vcm (2V in this example); conversely, when the voltage VLC is rising, the falling threshold Vtr is set to Vcm-hysteresis (2V−0.05V=1.95V in this example) and the rising threshold Vtl is set to Vcm (2V in this example). Thus, the comparator27permits accurate zero cross (Vcm cross) detection, without compromising the ability of the comparator27to utilize hysteresis to reject noise during that zero cross detection.

The second device15′ may be operated in either transceiver mode (Rx or Tx) or Q-factor measurement mode.

During transceiver mode, the controller19generates the control signals G1-G4so as to cause the circuit16to act as either a receiver or inverter, as described above. Additionally, during transceiver mode, the Q-factor measurement enable signal Q_en is deasserted, turning off transistors MN1and MN2to effectively isolate node Qs from Vcm while the diode D effectively blocks the transceiver signal from the circuit21, and the switching action of the circuit16results in the voltage VLC across the coil Lxcvr switching between positive and negative maximum magnitudes, such as −50V and 50V.

In Q-factor measurement mode, the Q-factor measurement enable signal Q_en is asserted by the controller19to turn on transistors MN1and MN2to thereby establish a connection from the Qs pad to the center tap of the series connected resistors R1and R2. In addition, the transistors T3and T4are simultaneously turned on by the controller19asserting the gate voltages G3and G4, thereby shorting the nodes Ac1and Ac2to ground.

Then, the driver22drives the p-channel transistor MP1through pad Qe with a pulse wave Vin_exc during an excitation period to produce an excitation signal, with the duty cycle, frequency, and number of cycles of the pulse wave Vin_exc being set by the firmware of the FSM25. A graph of Vin_exc at pad Qe during the excitation period can be seen inFIG. 6. When Vin_exc is low during the excitation period, turning on the p-channel transistor MP1, the coil Lp sinks power from VDD; conversely, when Vin_exc is high turning the excitation period, the p-channel transistor MP1is turned off.

Through this, the coil Lp is excited with a frequency and duty cycle set by Vin_exc. The pulse width and frequency of the excitation signal sets the excitation amplitude of the coil Lp. The excitation period continues until the coil Lxcvr reaches a steady state. The sensing circuit30is protected during the excitation phase by the diode D, resistor Re, and p-channel transistor MP1having a voltage rating sufficient to withstand the voltage VLC at node Nf.

Once the excitation period is over, the response of the voltage VLC at node Qs (which will be a decaying sine wave oscillating about a common mode voltage Vcm set at the tap between the resistors R1and R2, as shown inFIG. 6) is sensed by the sensing circuitry23through the capacitor Cq during a sensing period.

In particular, the comparator27asserts the Comp_Out signal when the voltage VLC undergoes a rising zero-cross (meaning that VLC rises above the Vtr threshold, with “zero” here being Vcm as modified by hysteresis, explained above), and deasserts the Comp_Out signal when the voltage VLC undergoes a falling zero-cross (meaning that VLC falls below the Vtl threshold, with “zero” being Vcm as modified by hysteresis as explained above). When the Comp_Out signal is asserted, and the FSM25in turn asserts the control signal Ctrl to thereby enable or trigger the ADC24to take a single sample, the sample being the digitized amplitude of the output voltage Vout as output by the amplifier26at the time delay td after the control signal Ctrl was asserted to produce an ADC output signal ADCout, which is received by FSM25.

A first way that the processing circuitry31can calculate the Q-factor from the samples is from two peak samples, for example referring toFIG. 7, as:

where A1 is the amplitude of the first measured peak of Vout during the sensing period, and AN is the amplitude of the Nth measured peak during the sensing period.

When calculating the Q-factor using this first way, the FSM25stores the value of amplitude A1 and continues to compare the value of amplitude A1 to the current value of amplitude AN. When the value of amplitude AN is below half that of amplitude A1, the FSM25saves that value of amplitude AN, thereby reducing the number of values of amplitude AN stored for calculating the Q-factor, and reducing the size of a lookup table used for the natural logarithm function.

The above described calculation is also effective if amplitude A1 is measured not only at the peak but also if amplitude A1 is measured at any point that is the time delay period td away from a zero crossing on the curve within the first oscillation cycle during the sensing period. For example, referring toFIG. 8, amplitude A1 could be measured at any point between t1a and t1b, provided that amplitude AN is also measured at the same time delay td away from a zero crossing on the curve within the Nth oscillation cycle, with the exception to both being where td=0, td=one half the period of the first oscillation, or where td=the period of the first oscillation.

In order to remove error introduced by DC offset and/or flicker noise of the amplifier26, the peak and valley of the oscillation cycle may be utilized. For example, referring toFIG. 8, amplitude A1a and A1b samples may be taken, and amplitude ANa and ANb samples may be taken, and the calculation of the Q-factor may be performed as:

When calculating the Q-factor using this second way, the FSM25stores the value of A1a-A1b and continues to compare the value of A1a-A1b to the current value of ANa-ANb. When the value of ANa-ANb is below half that of A1a-A1b, the FSM25saves those values of amplitude ANa and amplitude ANb, thereby reducing the number of values of ANa-ANb stored for calculating the Q-factor, and reducing the size of a lookup table used for the natural algorithm function.

Now that Q-factor calculation using the second device15′ has been described, an operating technique for foreign object detection utilizing the calculated Q-factor is now described with additional reference to the flowchart50ofFIG. 9. This technique begins with a calibration. During the calibration, it is known that the first device11and the foreign object are not in proximity to the second device15′, and the second device15′ is set in Q-factor measurement mode. Then, the excitation period as described above occurs (e.g., the second device15′ is excited without the presence of the second device11), and its output voltage Vout is sampled during the sensing period. From the samples of Vout, the frequency of Vout during the sensing period, which is the resonance frequency of the second device15′, is determined, and saved as Fr_tx, completing the step of Block51.

Now, the operation of the second device15′ and its FSM25for performing foreign object detection is described. Beginning with the step at Block52, when it is not known whether the first device11and/or the foreign object are in proximity to the second device15′, the Q-factor measurement mode is engaged, the excitation period as described above occurs, and the output voltage Vout is sampled during the sensing period. From the samples of Vout, the frequency of Vout during the sensing period, which is the resonance frequency of the system (second device15′, first device11if present, and foreign object if present), is determined by the FSM25and saved as Fr_sys. The first sample of Vout, amplitude A1 is also saved by the FSM25, as is the amplitude AN sample used together with the amplitude A1 sample to determine the Q-factor, completing the step of Block52.

If Fr_tx less a margin Fr_margin is greater than Fr_sys at the step of Block53, then it can be inferred by the FSM25that the first device11is present but a foreign object is not present at the step of Block54, so the second device15′ can proceed with transmitting full power wirelessly at the step of Block55, and this is effectuated by the FSM25instructing the logic core23accordingly. Regarding the margin Fr_margin, this is a set tolerance threshold either estimated or profiled.

If Fr_sys is less than Fr_tx plus Fr_margin, but greater than Fr_tx-Fr_margin at the step of Block56, then it can be inferred by the FSM25that both the first device11and a foreign object are present at the step of Block57. So as to provide for enhanced accuracy at this step, here, the Q-factor calculated during the Q-factor measurement mode (shown here as Qsys) is compared a Q-factor margin value (shown here as Qmargin) and the amplitude A1 or AN samples are compared to an amplitude margin value (shown here as Amargin). In particular, if Qsys is less than Qmargin, amplitude A1 is less than Amargin, or amplitude AN is less than Amargin at the step of Block58, then it can be inferred by the FSM25that the foreign object is positioned between the first device11and second device15′ or sufficiently conductive that it would be preferable for the second device15′ to not wireless transmit power at this point at the step of Block59, and the FSM25instructs the logic core23accordingly. On the other hand, if Qsys is greater than Qmargin, or if amplitude A1 is greater than Amargin, or if amplitude AN is greater than Amargin, then it can be inferred by the FSM25that the foreign object is either not positioned sufficiently between the first device11and second device15′ or is not sufficiently conductive such that the second device15′ can wireless transmit limited power at the step of Block60, and the FSM25instructs the logic core23accordingly.

If Fr_sys is equal to Fr_tx at the step of Block64, then it can be inferred by the FSM25that neither the first device11nor a foreign object are present, so periodic pinging can be performed (e.g., every few seconds to check for presence of the first device11) at the step of Block65, and the FSM25instructs the logic core23accordingly.

Note here that sufficiently non-conductive objects, such as a plastic case for a smartphone, may have no appreciable effect on the output voltage Vout.

As stated above, the comparator27utilized by the transceiver device15′ has rising and falling threshold values dynamically set by hysteresis dependent upon whether the voltage at its inputs are rising or falling. The comparator has both the comparator rising threshold Vtr and comparator falling threshold Vtl set to Vcm, but with the hysteresis maintained making the actual threshold voltages Vtr and Vtl dynamic.

The advantages provided by this comparator27are perhaps best first described with reference to a more generic example of an electronic device90including transmitter hardware91and receiver or transceiver hardware92, shown inFIG. 10A. The transmitter hardware91has a transmitter coil Lxmit coupled thereto, with a capacitor Cxmit being a tuning capacitor. The receiver hardware92includes a receiver coil Lxcvr, with a capacitor Cxcvr being a tuning capacitor. A bridge rectifier99has a first input node Ac1coupled to the first terminal of the receiver coil Lxcvr and a second input node Ac2coupled to the second terminal of the receiver coil Lxcvr. The bridge rectifier99has an output node Nin coupled to a voltage regulator97, with a tank capacitor Ctank being coupled between the output node Nin and ground. A rectified voltage Vrect forms across the tank capacitor Ctank. A voltage regulator97receives the rectified voltage Vrect at its input, and outputs a regulated voltage Vreg at its output to a load98.

The bridge rectifier99is comprised of a first n-channel transistor T1having a drain coupled to the output node Nin, a source coupled to the input node Ac1, and a gate coupled to receive the high side on signal HS1_ON generated by driver93based upon the low side on signal LS2_ON; a second n-channel transistor T2having a drain coupled to the output node Nin, a source coupled to the input node Ac2, and a gate coupled to receive the high side on signal HS2_ON generated by the driver95based upon the low side on signal LS1_ON; a third n-channel transistor T3having a drain coupled to the input node Ac1, a source coupled to ground, and a gate coupled to receive the low side on signal LS1_ON, generated by a comparator94having its inverting terminal coupled to the input node Ac1and its non-inverting terminal coupled to ground; and a fourth n-channel transistor T4having a drain coupled to the input node Ac2, a source coupled to ground, and a gate coupled to receive the low side on signal LS2_ON, generated by a comparator96having its inverting terminal coupled to the input node Ac2and its non-inverting terminal coupled to ground.

In operation, the transmitter91drives the transmitter coil Lxmit with a time varying current, resulting in a time varying current being induced in the receiver coil Lxcvr, which is in turn rectified by the rectifier99. Operation of the rectifier99is as follows, with additional reference toFIG. 10B.

When the voltage at node Ac1crosses zero and the voltage at node Ac2goes high, the comparator94outputs the LS1_ON signal at a logic high, turning on the transistors T2and T3. This has the effect of current flowing from the node Ac2to the output node Nin through the transistor T2, and current flowing from node Ac2to node Ac1through the receiver coil Lxcvr, and from ground to node Ac1through the transistor T3.

When the voltage at node Ac2crosses zero and the voltage at node Ac1goes high, the comparator96outputs the LS2_ON signal at a logic high, turning on the transistors T1and T4. This has the effect of current flowing from the node Ac1to the output node Nin through the transistor T1, from the node Ac1to node Ac2through the receiver coil Lxcvr, and from ground to the node Ac2through the transistor T4.

The comparators94and96are hysteresis comparators having a rising threshold Vtr at, for example, 0V and falling threshold Vtl at, for example, −80 mV. This response characteristic can be seen inFIG. 10C. This lower threshold Vtl is utilized to help ensure that the direction of current flow in the receiver coil Lxcvr has full reversed before the comparator changes state, avoiding incorrect direction which could lead to oscillation of the output of the comparator.

The novel design of the comparators94and96is shown inFIG. 11. Here, it can be seen that each comparator94,96is comprised of: a first p-channel transistor MH1having a source coupled to a tail current source101, a drain coupled to ground through a transistor Rh1, and a gate forming the first comparator input (shown as IN1); a second p-channel transistor MH2having a source coupled to the tail current source101, a drain coupled to ground through a transistor Rh2, and a gate forming the second comparator input (shown as IN2). A resistor Rh3is selectively connected in parallel with resistor Rh2by a switch SW. A gain stage102(shown as an amplifier) has inputs coupled to the drains of the p-channel transistors MH1and MH2respectively at nodes No1and No2, and its output OUT forming the output of the comparator94,96. The switch SW is operated as a function of the output OUT of the comparator94,96.

The comparator94,96design shown inFIG. 11operates as follows. When OUT is at a logic low, the switch SW is open and the output load of each side of the comparator is equal, because the resistances of Rh1and Rh2are equal. The triggering point of the comparator output OUT (to logic high) is at the point where the voltage Vo1across Rh1is equal to the voltage Vo2across Rh2. Thus, the output current I1output from the drain of the transistor MH1is equal to the current I2output from the drain of the transistor MH2at the triggering point of the comparator since Von=In*Rhn, where n is either 1 or 2 depending on which side of the comparator structure is being referred to. Since the output current is proportional to the square of the input voltage, the output OUT of the comparator is asserted when IN1is equal to IN2.

Now, when the output OUT is at a logic high, the switch SW closes. This results in the output load being imbalanced because resistors Rh2and Rh3are connected in parallel, so the voltage Vo2becomes less than the voltage Vo1. As a result, the current I2is increased to ensure that the voltage Vo1is nevertheless equal to Vo2to reach the triggering point. Hence, the comparator output does not trigger when IN1=IN2, and the trigger point (from the output OUT transitioning from high to low) is shifted depending on the value of the resistor Rh3.

This design hysteresis comparator is quite useful where the comparator, as shown, has a resistive load, and works well in the electronic device90described above.

However, PVT variations can cause offset, leading to the zero-crossing detection performed by the comparators94,96being inaccurate, leading to this comparator design not being optimal for some applications. For example, this comparator design could be used as the comparator27in the transceiver device15′ described above, although functionality could be improved if the comparator27were to include an auto-zeroing offset cancellation component. The auto-zeroing offset cancellation component, however, cannot function with a resistive load, and therefore the auto-zeroing offset cancellation component is to have an active load.

Such a design is shown inFIG. 12, and this design comparator27may also be used in the transceiver device15′ described above. The comparator27is comprised of a hysteresis stage27a, an auto-zeroing stage27b, and a gain stage27c.

The hysteresis stage27ais comprised of p-channel transistors MH1and MH2having their sources coupled to a current source101and their drains respectively coupled to nodes No1and No2. A resistor Rh1is coupled between node No1and ground, and a resistor Rh2is coupled between node No2and ground. The resistors Rh2and Rh3may be equal in resistance. A switch S5, responsive to the output OUT of the comparator27, selectively couples the resistor Rh2in parallel with the resistor Rh3.

The gate of the p-channel transistor MH1is selectively coupled to the input IN1by switch51, and switch51operates responsive to deassertion of an auto-zeroing signal AZ. The gate of the p-channel transistor MH1is also selectively coupled to ground by the switch S3, responsive to assertion of the auto-zeroing signal. The gate of the p-channel transistor MH2is selectively coupled to the input IN2by switch S2, and switch S2operates responsive to deassertion of the auto-zeroing signal AZ. The gate of the p-channel transistor MH2is also selectively coupled to ground by the switch S4, responsive to assertion of the auto-zeroing signal.

The auto-zeroing stage27bis comprised of p-channel transistors MH3and MH4having their sources coupled to a tail current source103and their drains respectively coupled to nodes No3and No4. The gate of p-channel transistor MH3is coupled to node No1, and the gate of p-channel transistor MH4is coupled to node No2. An n-channel transistor MH5has its drain coupled to node No3and its source coupled to ground, while an n-channel transistor MH6has its drain coupled to node No4and its source coupled to ground. A switch S6, responsive to assertion of the auto-zeroing signal AZ, couples the gate of the n-channel transistor MH5to the drain of the n-channel transistor MH5, as well as to the top plate of capacitor Ch1, the bottom plate of which is coupled to ground. A switch S7, responsive to assertion of the auto-zeroing signal AZ, couples the gate of the n-channel transistor MH6to the drain of the n-channel transistor MH6, as well as to the top plate of capacitor Ch2, the bottom plate of which is coupled to ground.

The gain stage27cis comprised of an amplifier having inputs coupled to nodes No3and No4, and providing the comparator output OUT.

Operation of the comparator27shown inFIG. 12is as follows. In auto-zeroing mode, the auto-zeroing signal AZ is asserted, opening the switches51and S2, while closing the switches S3, S4, S6, and S7. Any offset present resulting from resistance variation between the resistors Rh1and Rh2is amplified by the transistors MH3and MH4and sampled across capacitors Ch1and Ch2.

When the auto-zeroing mode is when complete, the auto-zeroing signal AZ is deasserted, opening the switches S3, S4, S6, and S7. Note that the offset is still stored across capacitors Ch1and Ch2. The deassertion of the auto-zeroing signal also serves to close switches51and S2so as to receive input.

When OUT is at a logic low, the switch S5is open and the output load of each side of the hysteresis stage27ais equal, because the resistances of Rh1and Rh2are equal. The triggering point of the comparator output OUT (to logic high) is at the point where the voltage Vo1across Rh1is equal to the voltage Vo2across Rh2. Thus, the output current I1output from the drain of the transistor MH1is equal to the current I2output from the drain of the transistor MH2at the triggering point of the comparator since Von=In*Rhn, where n is either 1 or 2 depending on which side of the hysteresis stage27ais being referred to. Since the output current is proportional to the square of the input voltage, the output OUT of the comparator is asserted when IN1is equal to IN2. Note that any imbalance in resistance between resistors Rh1and Rh2is compensated by n-channel transistors MH5and MH6as biased by the offset that was stored across capacitors Ch1and Ch2during auto-zeroing mode.

Now, when the output OUT is at a logic high, the switch S5closes. This results in the output load being imbalanced because resistors Rh2and Rh3are connected in parallel, so the voltage Vo2becomes less than the voltage Vo1. As a result, the current I2is increased to ensure that the voltage Vo1is nevertheless equal to Vo2to reach the triggering point. Hence, the comparator output does not trigger when IN1=IN2, and the trigger point (from the output OUT transitioning from high to low) is shifted depending on the value of the resistor Rh3. Once again, as stated, any imbalance in resistance between resistors Rh1and Rh2is compensated by n-channel transistors MH5and MH6as biased by the offset that was stored across capacitors Ch1and Ch2during auto-zeroing mode.

Shown inFIGS. 13A-13Care graphs of operating characteristics of the comparator27with and without the auto-zeroing function. Note that the hysteresis sets Vtr to be 0 V, and Vtl to be −75 mV. The offset without auto-zeroing at Vtr can be 15.3 mV and at Vtl can be 13.1; with auto-zeroing, the offset is reduced to 0.3 mV at Vtr and 5.7 mV at Vtl.