Programmable level shifter

In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.

TECHNICAL FIELD

The present invention relates to electronics, and, in particular, to level shifters for programmable logic devices, such as field-programmable gate arrays (FPGAs), and other integrated circuits that use multiple power supplies.

BACKGROUND

In integrated circuits having multiple power supplies, as signals cross from one power-supply domain to another, the signals need to be level-shifted. Level shifters can be categorized into two types: high-speed and low-power. Depending on the application of the signal being level-shifted, the application may need a fast data path signal or a slower control signal with lower performance requirements. High-speed level shifters typically require more power and/or greater area than low-power level shifters. Some conventional high-speed level shifters consume both static DC power and transient power associated with switching, while low-power level shifters do not consume static DC power. The transient switching power of both level-shifter types is associated with charging and discharging, as signal potentials change from high to low or low to high.

A low-power level shifter transiently flows current while turning some devices on and other devices off. The transient current is used for the charging and discharging of signal potentials from one rail to another. Low-power level shifter nodes fully swing. The advantage of low-power level shifters is the absence of a static power component; the disadvantage is the relatively low speed. The NFETs of a low-power level shifter are used to over drive the current state of the latch. The larger the NFETs, the faster the transition and the faster the level shifter.

A high-speed level shifter may have nodes that do not swing from rail to rail. In this case, there is DC power for as long as one or more signals are not at a rail voltage. This power is due to a static current passing through an impedance. When current flows, the device is on. As long as current stays flowing, the device stays on. Therefore, the high-speed level shifter has states where some devices flow static current. The advantage is relatively high speed; the disadvantage is relatively high power (both static and transient power components). A high-speed level shifter can be thought of as a current source with an enable/disable.

FIG. 1shows a schematic diagram of a conventional high-speed level shifter100of the prior art. High-speed level shifter100converts input signal102in the domain of power supply Pwr1into output signal104in the domain of power supply Pwr2. As shown inFIG. 1, p-type field effect transistor (PFET) HP1is diode-connected, and PFETs HP1and HP2are configured to provide a current-mirror scheme. Turning on n-type FET (NFET) HN1creates a current source between Pwr2and ground, through HP1and HN1. This current is mirrored to device HP2.

If input signal102is driven towards ground (i.e., low), then inverter106drives inverted input signal108towards power supply Pwr1. These two signals turn NFET HN1off and NFET HN2on, respectively. Turning off HN1disables the current source, and turning on HN2drives output signal104towards ground. With HN1off, node110will be driven high through the PFET HP1diode. The HP1diode will pull node110all the way to Pwr2.

If input signal102is driven towards power supply Pwr1(i.e., high in the Pwr1domain), then HN1turns on and HN2turns off, due to inverter106. Turning on HN1turns on the current source through HP1/HN1and drives node110low. But node110does not go all the way to ground, because of the IR drop across HN1. HN1has an intrinsic impedance. As the current flows through HN1/HN2, there is a voltage potential created across HN1. This potential is a function of ohms law (V=IR). The current through the HP1and HN1devices is mirrored to HP2. With the gate-source voltage being the same across both HP1and HP2, HP2turns on. Turning on HP2drives output signal104towards power supply Pwr2(i.e., high in the Pwr2domain), thereby converting input signal102at Pwr1into output signal104at Pwr2.

Since, as described above, diode-connected HP1prevents node110from swinging from rail to rail (i.e., from ground to Pwr2, and vice versa), level shifter100can react quicker to changes in input signal102than if node110did swing rail to rail.

As described, if input signal102is low, then HN1is off, HN2is on, and HP1and HP2are off. As such, with input signal102low, there are no DC paths from power supply Pwr2to ground. However, if input signal102is high, then both HN1and HP1are on, and DC current flows through those two transistors from power supply Pwr2to ground, as represented inFIG. 1. As a result, there is a DC current flowing through high-speed level shifter100if input signal102is high.

FIG. 2shows a schematic diagram of a conventional low-power level shifter200of the prior art. Like high-speed level shifter100ofFIG. 1, low-power level shifter200converts input signal202in the domain of power supply Pwr1into output signal204in the domain of power supply Pwr2. Unlike high-speed level shifter100ofFIG. 1, which has diode-connected HP1, low-power level shifter200has PFETs LP1and LP2cross-coupled to provide a latching scheme.

If input signal202is driven towards power supply Pwr1(i.e., high in the Pwr1domain), then LN1turns on and LN2turns off, due to inverter206. Turning on LN1drives node210low, which turns on LP2. Turning on LP2drives output signal204towards power supply Pwr2(i.e., high in the Pwr2domain), thereby converting input signal202at Pwr1into output signal204at Pwr2. Driving output signal204high also turns PFET LP1off.

As described, if input signal202is low, then LN1is off, LN2is on, LP1is on, and LP2is off. As such, with input signal202low, there are no DC paths from power supply Pwr2to ground. Similarly, if input signal202is high, then LN1is on, LN2is off, LP1is off, and LP2is on. As such, with input signal202low, there are also no DC paths from power supply Pwr2to ground. As a result, there is never a DC current flowing through low-power level shifter200. On the other hand, low-power level shifter200is slower than a comparable implementation of high-speed level shifter100due to the time required to flip the latch formed by the cross-coupled PFETs. Typical implementations of low-power level shifter200use relatively large NFETs to over-drive the cross-coupled PFETs.

SUMMARY

In one embodiment, the present invention is an integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain. Switching speed of the level shifter is higher in the high-speed mode than in the low-power mode, while power consumption of the level shifter is lower in the low-power mode than in the high-speed mode.

In another embodiment, the present invention is an integrated circuit comprising first means for converting, in a high-speed mode, an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain. The integrated circuit further comprises second means for converting, in a low-power mode, the input signal in the first power supply domain into the output signal in the second power supply domain. The switching speed of the first means is higher than the switching speed of the second means, and the power consumption of the first means is lower than the power consumption of the second means. The first and second means share at least one circuit element.

DETAILED DESCRIPTION

FIG. 3shows a high-level block diagram of a programmable level shifter300, according to one embodiment of the present invention. In general, level shifter300converts input signal302in the domain of power supply Pwr1into output signal304in the domain of power supply Pwr2. Level shifter300supports two different modes of operation: high-speed and low-power, as determined by mode-control signal320. For example, if mode-control signal320is high (e.g., logic one), then level shifter300operates in high-speed mode, and if mode-control signal320is low (e.g., logic zero), then level shifter300operates in low-power mode. As their names suggest, if operated in high-speed mode, the switching speed and power consumption of level shifter300are both greater than if operated in low-power mode. Depending on the particular implementation, mode-control signal320can be bit-programmable, user-controlled, metal-programmable, and/or fuse-programmable.

In low-power mode, inverted mode-control signal324is high, which causes input signal302to be applied to the gate of N3and inverted input signal308to be applied to the gate of N4. Thus, if input signal302is high and inverted input signal308from inverter306is low, then both NFETs N1and N3are on, and both NFETs N2and N4are off. Similarly, if input signal302is low and inverted input signal308is high, then N1and N3are both off, and N2and N4are both on. As such, in low-power mode, programmable level shifter300operates in a manner analogous to that of low-power level shifter200ofFIG. 2, with PFET P1of level shifter300analogous to PFET LP1of level shifter200, PFET P2of level shifter300analogous to PFET LP2of level shifter200, the combination of NFETs N1and N3of level shifter300analogous to NFET LN1of level shifter200, and the combination of NFETs N2and N4of level shifter300analogous to NFET LN2of level shifter200. Note that, in combination with NFETs N1and N2, respectively, selectively enabled NFETs N3and N4provide larger effective n-type devices to enable the NFETs to overcome the latch formed by cross-coupled P1and P2in the low-power mode. Note that, for applications that do not require such larger effective n-type devices, transistors N3and N4and muxes326and328may be omitted.

In this way, programmable level shifter300provides an area-efficient implementation of a level shifter that can be programmed to operate either in high-speed mode to support high-speed applications or in low-power mode to support low-power applications in which high speed is not required. Area efficiency is provided by the fact that transistors P1, P2, N1, and N2are enabled for both the high-speed mode and the low-power mode and are therefore shared by the two operating modes.

The present invention can be implemented in the context of any suitable type of integrated circuit device, such as, without limitation, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), mask-programmable gate arrays (MPGAs), simple programmable logic devices (SPLDs), and complex programmable logic devices (CPLDs).

The present invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes.

Also, for purposes of this description, it is understood that all gates are powered from a fixed-voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.

Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.

Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.

Although the present invention has been described in the context of implementations based on FETs, such as metal-oxide semiconductor FETs (also referred to as MOSFET), the present invention can be implemented using other transistor technologies, such as bi-polar transistor technology.