Power semiconductor device

The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

CROSS-REFERENCE TO RELATED APPLICATION(S)

BACKGROUND

The following description relates to a power semiconductor device. The following description also relates to a power semiconductor device that maintains a breakdown voltage and reduces gate capacitance through strength reduction of an electric field, as compared to related alternative technologies, by improving the structure of an Injection Enhanced Gate Transistor (IEGT). Thereby, a power semiconductor device with reduced energy consumption and improved switching functionality is provided.

2. Description of Related Art

Minimization and high functionality of power devices are useful in the field of power electronics. Corresponding to these requirements, an improvement in not only high breakdown voltage and high current but also low loss and low noise in a power semiconductor device are being accomplished. In this circumstance, an IEGT, which is an improved version of an Insulated Gate Bipolar Transistor (IGBT) has gathered attention as a device with low ON voltage features and possible of reduction in turn-off losses.

Particularly, recently available alternative technologies disclose technical features of obtaining a Breakdown Voltage Collector-Emitter, specified with zero gate emitter voltage, BVCES, of an IEGT by minimizing a floating space of an IEGT or increasing resistivity value of an epi layer.

However, the aforementioned related alternatives incur a decrease in a floating effect, that increases Vce (sat), or Collector-Emitter Saturation voltage or epi layer thickness, and thereby reduces a switching function.

SUMMARY

Examples overcome the above disadvantages and other disadvantages not described above. Also, the examples are not required to overcome the disadvantages described above, and an example potentially does not overcome any of the problems described above.

The present description relates to a power semiconductor device that can maintain BVCESwhile solving problems of related technologies and reduces gate capacitance. As a result, power energy consumption is small and is able to provide improved switching functionality.

In one general aspect, a power semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface, a drift region located on the substrate having a first conductivity type, an emitter electrode located on the first surface of the substrate, a drain electrode located on the second surface of the substrate, an emitter contact region in contact with the emitter electrode, a trench gate structure that surrounds four sides of the emitter contact region, a base region located under the emitter contact region having a second conductivity type, and a floating region located on an exterior region of the trench gate structure that surrounds the trench gate structure and is deeper than the trench gate structure, wherein the floating region is electrically floating and surrounds a bottom surface of the trench gate structure and is separate from the base region, and wherein an impurity concentration of the floating region is lower than an impurity concentration of the base region.

The trench gate structure may include a pair of trench gates extending from the substrate surface to the drift region, the emitter contact region may include a first conductivity type source region and a second conductivity type contact region, and the power semiconductor device may further include a first well region with a first conductivity type configured between the base region and drift region that has a higher impurity concentration than the drift region, and the floating region and the base region may be separated by the first well region.

The power semiconductor device may further include a second conductivity type deep-well region having a greater depth than the floating region, and a pair of dummy trench gates configured not to contact the source region and having a smaller depth than the deep-well region, wherein the floating region and the deep-well region are separated by the pair of dummy trench gates.

The power semiconductor device may further include a termination region located in the substrate and surrounding a cell region, wherein the cell region includes the trench gate structure and the floating region, and the termination region includes a termination ring region and a gate bus line.

The power semiconductor device may further include a termination ring region located in the substrate, a dummy trench gate located between the floating region and the termination ring region, and a second conductivity type deep-well region located between the dummy trench gate and the termination ring region and having a deeper depth than the dummy trench gate, wherein the deep-well region is electrically connected to the emitter electrode.

The power semiconductor device may further include a second conductivity type edge base region located between the dummy trench gate and the deep-well region, with a smaller depth than the dummy trench gate.

In another general aspect, a power semiconductor substrate includes a substrate including a first conductivity type drift region, an emitter electrode located on an upper region of the substrate, a drain electrode located on a lower region of the substrate, a trench emitter structure that is electrically connected to the emitter electrode, a second conductivity type floating region located in the trench emitter structure with a greater depth than the depth of the trench emitter structure, a trench gate structure arranged in an exterior region of the trench emitter structure and surrounding the trench emitter structure, an emitter contact region formed between the trench gate structure and the trench emitter structure and in contact with the emitter electrode, and a second conductivity type base region formed below the emitter contact region, wherein the floating region is electrically floating, and wherein the trench gate structure has a network structure having a net shape whose portions connect with each other, with a planar structure.

The floating region may be in contact with the drift region and may surround a bottom corner of the trench emitter structure.

The width of the floating region may be greater than the width of the base region.

The trench gate structure may include trench regions, the trench regions may include a pair of trench gates configured to extend from the substrate surface to the drift region, and the emitter contact region may include a first conductivity type source region and a second conductivity type contact region.

The trench emitter structure may be formed between the pair of trench gates and the trench emitter structure may be configured not to contact with the source region.

The power semiconductor substrate may further include a second conductivity type termination ring region formed in the inner substrate, and a dummy trench gate with a deeper depth than the base region, wherein the dummy trench gate is formed between the base region and the termination ring region and is configured not to contact with the source region.

The substrate may be divided into a first region and a second region and the first region and the second region are formed alternately on the substrate, the first region including the floating region surrounding the trench emitter structure, and the second region including the emitter contact region surrounding the trench gate structure.

The termination ring region may be overextended on the lower side of the dummy trench gate.

In another general aspect a power semiconductor device includes a drift region located on a substrate having a first conductivity type, an emitter electrode located on a first surface of the substrate, including an emitter contact region in contact with the emitter electrode, a drain electrode located on a second surface of the substrate, wherein the second surface is opposite to the first surface, a trench gate structure that surrounds the emitter contact region, a base region located under the emitter contact region, having a second conductivity type, and an floating region located on an exterior region, surrounding a bottom surface of, separate from, and deeper than the trench gate structure, wherein the floating region is electrically floating, wherein an impurity concentration of the floating region is lower than an impurity concentration of the base region.

The trench gate structure may include a pair of trench gates extending from the substrate surface to the drift region, the emitter contact region may include a first conductivity type source region and a second conductivity type contact region, the power semiconductor device may further include a first well region with a first conductivity type configured between the base region and drift region that has a higher impurity concentration than the drift region, and the floating region and the base region may be separated by the first well region.

The power semiconductor device may further include a second conductivity type deep-well region having a greater depth than the floating region, and a pair of dummy trench gates configured not to contact the source region and having a smaller depth than the deep-well region, wherein the floating region and the deep-well region are separated by the pair of dummy trench gates.

The power semiconductor device may further include a termination region located in the substrate and surrounding a cell region, wherein the cell region includes the trench gate structure and the floating region, and the termination region includes a termination ring region and a gate bus line.

The power semiconductor device may further include a termination ring region located in the substrate, a dummy trench gate located between the floating region and the termination ring region, and a second conductivity type deep-well region located between the dummy trench gate and the termination ring region and having a deeper depth than the dummy trench gate, wherein the deep-well region is electrically connected to the emitter electrode.

The power semiconductor device may further include a second conductivity type edge base region located between the dummy trench gate and the deep-well region, with a smaller depth than the dummy trench gate.

DETAILED DESCRIPTION

Certain examples are now described in greater detail with reference to the accompanying drawings.

In the following description, the same drawing reference numerals are used for the same elements, even in different drawings. The matters defined in the description, such as detailed constructions of terms and elements, are provided to assist in a comprehensive understanding of the present examples. Accordingly, it is apparent that it is possible for the examples to be carried out without those specifically defined matters. Also, well-known functions or constructions are not described in detail to avoid obscuring the examples with unnecessary detail.

While the expressions such as “first” or “second” are potentially used to refer to various elements, the elements are not intended to be limited by the expressions. Such expressions are used only for the purpose of distinguishing one element from the other when referring to such elements.

The expressions presented are used herein only for the purpose of explaining specific examples and are not intended to place limits on the present examples. An expression in singular form also encompasses plural meaning, unless otherwise specified. Throughout the description, the expression “comprise” or “have” is used only to designate the existence of a characteristic, number, step, operation, element, component or a combination thereof which is described herein, but not to preclude possibility of existence of one or more of the other characteristics, numbers, steps, operations, elements, components or combinations of these or other appropriate additions.

Spatial words, such as below, beneath, lower, above and upper are used to conveniently recite a correlation between one element or features with respect to other elements or features, as illustrated in the drawings. When spatial terminology is used with a direction as illustrated in the drawing, if the illustrated element is upside down, the element that was recited as below and beneath is also potentially considered to be above or upper of another element. Thus, examples presented below include all such instances related to the directions of below and above. An element is also potentially aligned in another direction, and thereby spatial words are interpreted according to the alignment.

Moreover, words such as a first conductivity type and a second conductivity type indicate opposite conductivity types like N-type or P-type. An example that is each recited and illustrated herein includes complementary examples thereof, in which N-type dopants are replaced by P-type dopants and vice versa. For example, in an example, a first conductivity type is an N-type and a second conductivity type is a P-type, but these types are potentially switched in another example.

Hereinafter, examples are illustrated with reference to the attached drawings.

FIG. 1is a top view of a semiconductor chip comprising a power semiconductor device.

As illustrated in the example ofFIG. 1, a semiconductor chip including a power semiconductor device according to a first example includes an active region or a cell region1000, a semiconductor device operating thereon, and a high voltage (HV) region in the active region1000is formed disposed therein. However, the periphery region of a semiconductor chip includes Junction Termination Extension (JTE), which includes an edge termination region at edge region2000. Herein, the edge termination region2000is also referred to as a junction termination region.

Particularly, in the example ofFIG. 1, the edge termination region2000electrically isolates the active region1000. To achieve this effect, the termination region2000stops a high electric field applied onto the active region1000. The electric field of the active region gradually decreases towards the edge of the semiconductor chip. Thus, the electric field value becomes closer to zero (0) by using the edge termination region, as the electric field becomes farther from the active region.

FIG. 1is an example of the power semiconductor device of the present examples disclosing a technical feature of a gate pad3000of an IGBT device with a breakdown voltage of a 1200V range configured in the center of the active cell region1000, and a first gate bus line1500that is electrically connected with the gate pad3000. Accordingly, when a signal is applied to the gate pad3000, the signal is also applied to the trench gate through a first gate bus line1500. In this example, the first gate bus line1500is configured as an option in order to prevent a delay of a gate signal propagation route that is proper for a mass storage power semiconductor device with a large current of approximately 100 A. In another example, the first gate bus line1500is not be used in a small storage power semiconductor device with a lower current, with reference toFIG. 6. Further, the first gate bus line1500is formed with a metal layer of Al or Cu in order to lower its resistance. Further, in this example, a second gate bus line1600is included to surround a periphery region of an active region1000. The first gate bus line1500and the second gate bus line1600are physically separated, but electrically connected through gate polysilicon. An emitter electrode passes between the first gate bus line1500and the second gate bus line1600. Accordingly, a signal is able to be input to the trench gate electrode through the second gate bus line1600. The second gate bus line1600is also formed with a metal layer such as Al or Cu to lower its resistance.

In the example ofFIG. 1, a power semiconductor device according to an example discloses a technical feature of semiconductor devices having an active cell region1. Thus a feature, for example, a trench gate, structure, shape and arrangement of a gate electrode as illustrated inFIG. 1and so on, for applying a gate voltage to a gate electrode or gate poly in a semiconductor chip comprising the aforementioned features potentially varies.

FIG. 2is an enlarged top view of the active cell region1as shown inFIG. 1in a power semiconductor device according to an example. The trench gate structure10includes a trench gate electrode15A and a gate insulating layer16formed in deep trenches11,12,13and14. The emitter contact region Ec defines an active region that contacts the emitter electrode80. The emitter electrode80contacts the P-type contact region35and the source region30, as shown inFIG. 3. Therefore, the emitter contact region Ec includes the P-type contact region35and the source region30.

FIG. 2shows that a trench gate structure10surrounds the emitter contact regions Ec in a top view. For example, the trench gate structure10has a rectangular shape or circular shape. A P-type floating region DF20is formed adjacent to the trench gate structure10and surrounds all of the sides of the trench gate structure10. These compact structures, including Ec and DF and trench gate structure, result in a high density chip area. In the example ofFIG. 2, the emitter contact region Ec is referred to as Ec and the floating region20is referred to as DF. Subsequently, the second and third examples use the same reference annotations.

FIG. 3is a diagram shown according to a cross section A-A′ ofFIG. 2. As illustrated inFIG. 3, an active cell region1of a power semiconductor device according to a first example includes an emitter contact region Ec including a P-type contact region35with a high doping concentration and an N-type source region30with a high doping concentration. Further, a plurality of trench gate structures10configured is formed to surround the emitter contact region Ec. The trench gate structure also includes a trench gate electrode15A and a gate insulating layer16that are formed in a trench. The trench gate electrode15A is formed of a polysilicon doped with an N-type dopant, according to an example. In this example, the emitter contact region Ec and the gate electrodes15A,15B are electrically insulated. Also, a trench gate electrode15A is connected to the gate bus line1500through the conductive material15B over a floating region20. Here, the trench gate electrode15A and the transfer gate electrode15B are formed of the same material. The conductive material15B has a role of a bridge connecting a plurality of trench gate electrodes15A with each other.

A P-type floating region DF20is formed to be adjacent to the trench gate structure10. The P-type floating region20has a lower impurity concentration than a high impurity concentration P-type contact region35and a high impurity concentration N-type source region30. The floating region20is not electrically connected with either an emitter electrode80or gate electrodes15A,15B and as a result the floating region20is completely floating. The floating region20is formed below the emitter electrode80, but is surrounded by an insulation layer60. Thus, the floating region20blocks a hole carrier from entering into the emitter electrode80. Thus, a hole carrier concentration increases in an N-drift region50. Electron concentration in the N-drift region increases accordingly due to conduction modulation. Accordingly, in a switched ON state, a resistance of the N-drift region50decreases. Then, the voltage, that is, Vce, between a collector and emitter electrode is reduced. When Vce decreases, power loss is reduced accordingly in a switching ON state. On the contrary, a switched OFF state is disadvantageous because electrons or hole-carriers are difficult to move out due to the floating region. As a result, the floating region20is unable to be used as a passage or channel. Thus, a switched OFF period is potentially longer.

The power semiconductor device, which is an IGBT, is formed based on the semiconductor substrate. The substrate includes two epi-layers with different concentrations. In this example, an epi-layer with a high impurity concentration operates with a field stop layer, or buffer layer,55and the epi-layer with a lower impurity concentration than the field stop layer55and configured on the field stop layer55is operated with a drift region50. In an example, the drift region50has a thickness of 90˜100 μm. On the other hand, in such an example, the field stop layer has a thickness of 15˜30 μm. The field stop layer55prevents an electric field formed by the emitter electrode from extending into a P+ collector layer57. When a field stop layer55is not formed, a thickness of a drift region50is correspondingly thicker. Thus, there is a potential issue that arises that resistance increase due to the drift region50being doped with a low concentration.

A power semiconductor according to an example is potentially applied with an epi-wafer of different concentrations, but examples are not limited to the aforementioned example. For example, the field stop layer55is potentially formed by ion-injection of an impurity with a different concentration regarding the semiconductor substrate.

Hereinafter, various features and aspects of a power semiconductor device according to an example are illustrated in the following.

First, a plurality of trench gate structures10are formed with a predetermined depth from the upper semiconductor substrate. However, for the convenience of explanation, is the trenches are referred to as a first trench11, a second trench12, a third trench13, and a fourth trench14from left to right inFIG. 3.

In the example ofFIG. 3, the first to fourth trenches11,12,13and14are formed through an etching process with regard to the semiconductor substrate and respective gates are formed with a similar or identical depth through a similar or identical process.

Respective trenches11,12,13and14potentially each include gate insulation layer16and trench gate electrode15A, respectively. The trench gate electrodes15A are formed in respective deep trenches11,12,13and14and a gate insulation layer16surrounding the trench gate electrodes15A is formed as well.

The P-type floating region20is formed surrounding bottom corners of the second and third trenches12,13. For example, the P-type floating region20is be formed through ion-injection of P-type impurity such as boron (B) or BF2and so on, with a predetermined concentration. However, these are merely example impurities, and other appropriate alternatives are used in other examples. Here, the P-type floating region20has a smaller concentration than a P-type base region40. This difference is present to increase a resistance of the P-type floating region20, thereby allowing a further increase or maintenance of a breakdown voltage.

Herein, the floating region20is configured to surround the bottom corners of the second and third trench12,13. Thus, each bottom surface of the second and third trench12,13is accordingly configured to be in contact with the P-type floating region20.

When a power semiconductor device operates, an electric field is increased in bottom corners of all of the trench gates. However, as the P-type floating region20is configured to surround the bottom corners of respective trench gates, the concentration of electric field is relieved; and thereby the breakdown voltage of a power semiconductor device is improved. A reason why the electric field is increased in the bottom corner of the trench gate is because the corner shape of the trench is sharply changed, in the examples. Thus, the electric field is increased in the corner of the trench. However, the electric field is relieved elsewhere because the P-type floating region20completely surrounds one corner of the trench. Hence, such a floating region formed at a lower depth of the bottom surface of trench region is more advantageous in terms of a breakdown voltage.

Preferably, the P-type floating region20is configured to surround the bottom corners of the trenches12,13as illustrated inFIG. 3, and thereby improves operation of the power semiconductor device.

Herein, the power semiconductor device according to a first example includes the features illustrated inFIG. 3. Accordingly, the floating region20is formed on a left region of the first trench11and a right region of the fourth trench14as illustrated inFIG. 3. Likewise, the floating region20is configured to completely surround the bottom corners of the first to fourth trenches11,12,13and14.

An emitter contact region Ec including a P-type contact region with a high impurity concentration35is formed between regions of the first and second trenches11,12and the third and fourth trenches13,14, and a P-type base region40are formed below the emitter contact region Ec.

First, the N-type source region30is formed with a high doping concentration of an N-type impurity concentration and in contact with a trench. For example, the N-type source region is formed using an ion-injection with a high doping concentration of phosphorus (P), arsenic (As) and so on. However, these are merely examples and other appropriate alternative dopants are used in different examples. The N-type source region30is formed on the upper region of a semiconductor substrate respectively in contact with the first to fourth trenches11,12,13and14.

A P-type contact region35is formed with a high doping concentration of a P-type impurity, and is appropriately configured between regions of the source region30. Herein, the P-type contact region with a high doping concentration35is formed in contact with the source region30. A P-type base region40is formed under the source region30and the P-type contact region35, and is also formed at a predetermined depth from the upper semiconductor substrate. In an example, the base region40is formed with a lower impurity concentration than the P-type contact region35. Thus, the base region40becomes a channel region.

According to an example, an N-type well region45is formed under the P-type base region40. The N-type well region45restricts hole carrier movement from a drain electrode59to a source region30. For this effect to occur, the N-type well region45is formed with a higher impurity concentration than that of an N-type drift region40. Accordingly, when a hole carrier is accumulated on the drift region40, electrons crowd into the drift region, and thereby more conductivity modulation is generated, and thus resistance decreases. Accordingly, electron carriers are able to easily move to the drain region even with a small voltage, thereby obtaining a low Vce (sat) feature.

In one example, the depth of the base region40formed from the upper semiconductor substrate is formed to be smaller than the depth of respective trenches11,12,13and14. Alternatively, in another example, the N-type well region45that is a charge storage layer is formed to be deeper than the depth of respective trench gates. Further, there is a trade-off feature of a Vce (sat) reduction effect and a breakdown voltage between collector and emitter BVces reduction due to the depth value and impurity concentrations. Thus, the depth value is appropriately adjusted to manage these effects.

Further, according to an example, the width of the base region40or the N-type well region45is potentially formed to be smaller than the width of the floating region20. However, if the width of the base region40or the N-type well region45becomes smaller, a diffusion rate of electron or hole carrier is accordingly lowered. Thus, a determination of an appropriate width for these elements according to a desired functionality of a semiconductor device is desirable.

Also, an N-type drift region50is formed under the base region40or N-type well region45and the floating region20. Furthermore, the drift region50surrounds a bottom surface of the floating region20as illustrated inFIG. 3and is also formed to have a larger depth than the floating region20.

Additionally, an N-type field stop layer55is formed under the drift region50. The field stop layer55is formed with a higher impurity concentration than that of the drift region50, as aforementioned. Additionally, in such an example, a drain electrode59is formed by deposing a back metal layer on a lower semiconductor substrate that is formed on the field stop layer55and the collector layer57.

As illustrated inFIG. 3, trench gate electrodes15A formed in the second and third trench12,13are electrically and physically connected through a conductive material15B. The trench gate electrodes15A are formed of a polysilicon material that is the same material as the material of the conductive material15B. Further, the insulated layer60is formed on the floating region20. Likewise, the insulation layer60is configured between the conductive material15B and the floating region20. Furthermore, an insulation layer70covers the conductive material15B and a portion of the source region30.

As aforementioned, the emitter electrode80is formed on the insulated layer70and the emitter electrode80electrically connects with the P-type contact region35and N-type source region30. Thus, the emitter electrode80is able to form Ohmic contact not only with the P-type contact region35, but also with the source region30.

FIG. 4is a cross-sectional view of B-B′ inFIG. 1according to an example. The B-B′ line passes through the gate pad3000. Thus,FIG. 4shows a cell region around the gate pad3000. As illustrated inFIG. 4, a pair of active trenches21,22and a pair of dummy trenches23,24are formed. The trench gate electrode15A is formed in a respective trench and is electrically connected with a gate pad3000through the conductive material15B.

The P-type base region40is not formed between two dummy trench gates23,24adjacent to the trench gate, in the B′ direction. The floating region20is unable to contact a first P-type well region90, because the N-drift region exists between these elements. However, the P-type well region90is electrically connected with the emitter electrode80. When such a deep well region90formed below a gate pad3000is overly diffused and is in contact with a deep floating region DF20, the deep floating region20and the emitter contact region Ec potentially causes an electrical short circuit. This situation potentially causes a problem issue of an increase in capacitance and other related issues. Accordingly, the deep well region and deep floating region are separated formed using two trenches to prevent contact between these regions.

In this example, a source region30is not formed on the pair of dummy trench gates23,24. Hence, in the example, there is no channel region. By contrast, an N+ source region30is formed on a pair of active trench gates21,22and the channel region is formed on the P-type base region40, as hence the channel region is referred as an active region.

Thus, in such an example, a P-type deep-well region90is connected with an emitter electrode80, and thus has an identical potential as the emitter contact region Ec of a cell region by connection with the emitter electrode80. If the P-type deep-well region90is not connected with the emitter electrode, a breakdown voltage BV potentially drops. That is, the P-type deep-well region90is electrically connected with the emitter electrode80through high doping concentration contact layer36to have equivalent potential of the emitter contact region Ec of the cell region. As a result, a high voltage of about 1200V generated in the cell region is continuously maintained. In this example, the P-type deep well regions90are formed deeper than the pair of dummy trench gates23,24. Thus, a doping concentration of the P-type deep-well region90is formed to be identical or smaller than a doping concentration of a P-type floating region20.

FIG. 5is a cross-section of a power semiconductor of an edge cell region C-C′, as shown in the example ofFIG. 1. As illustrated, a cell region in an active region is formed to be identical with the example ofFIG. 3. Three trenches, that is, a pair of active trenches26and27and a dummy trench28, are formed. The first P-type base region40is formed between the active trenches26and27. Another P-type base region41is formed on one side of the dummy trench28. In such an example, the second P-type base region41is located near edge region. Furthermore the second P-type base region41has similar features to those of the first P-type base region40. An N+ source region30is formed to be adjacent to the active trenches26and27. Thereby, a channel region is formed on the P-type base region40. However, the channel region is not formed in the second P-type base region41, because there is no source region30in the second P-type base region41. Furthermore, a P-type floating region20is formed between the dummy trench28and the active trench27.

In this example, a bottom portion of the P-type floating region20is completely surrounded by an N-type semiconductor region that includes an N-type drift region50and an N-type well region45. Furthermore, the top portion and sidewall portion of the P-type floating region20are surrounded by an insulation layer60and the gate insulation layer16. As a result, the P-type floating region20is a completely floating region. Hence, there is an effect of reducing gate capacitance through the floating region. Thus, the Vce value decreases. However, one factor which is to be considered to achieve this effect is that a floating region20is to be spaced apart from the second P-type base region41or the P-type deep-well region90. It is required that there is enough space between the second P-type base region41and the floating region20.

Further, the second P-type base region41and the P-type deep well region90are configured to be in contact with each other in a termination region direction, along the C′ direction. Herein, in an example, the P-type deep well region90is formed to have a greater depth than the second P-type base region41. Also, the P-type contact region36is potentially formed on the upper P-type deep-well region90. In this example, the P-type contact region36is electrically connected with an emitter electrode80that is formed on the upper surface of the substrate. Accordingly, the P-type deep-well region90is electrically connected with the emitter electrode80. As a result, the P-type deep well region90has an identical potential that is the same as that of a cell region. This approach allows the maintenance of high voltage potential near a termination region2000.

Furthermore, in order to apply a gate voltage to a trench gate electrode15A formed in one of the trenches26,27,28in an active cell region, the trench gate electrode15A is connected with the gate pad3000through the gate bus line1600. Between the gate bus line1600and the trench gate electrode15A, there is a conductive material15B. In this example, the conductive material15B is formed over the second P-type base region41and the P-type deep-well region90. Thus, therefore an insulation layer72formed between these regions that are separated by the insulation layer72. Through such a use of the insulation layer72, the second P-type base region41and the P-type deep-well region90are electrically isolated from the gate electrode15A.

In this example, the conductive material15B extends into a termination region. One region of the gate electrode15A is electrically connected with a second gate bus line1600. When the trench gate electrode15A is formed on the termination region and is electrically connected with the second gate bus line1600, the trench gate electrode15A assumes an identical potential with that of the second gate bus line1600. Thus, a gate signal is well transmitted in this manner.

A doping region having ring shape95doped with a P-type dopant, that is, the junction field ring95is formed on a termination region2000. In an example, a depth of the junction field ring95is almost identical to a depth of a P-type deep well region90, and is formed to be deeper than the P-type floating region20.

According to an example, the junction field ring95is formed appropriately according to characteristics of a semiconductor device, and the depth is adjusted appropriately by a designer.

For example, an insulation layer60is formed on a region between the junction field ring95and a conductive material15B to prevent electric conduction between the junction field ring95and the conductive material15B.

Subsequently, with references toFIGS. 6-12, a power semiconductor device according to a second example and a third example is illustrated.

FIG. 6is a top view of a power semiconductor device according to a second example.FIG. 7is a top view of a power semiconductor device according to a second example.FIG. 8is a diagram shown according to a cross section D-D′ of the example ofFIG. 7.

InFIG. 6, a second gate bus line1600is formed to surround the edge of the active region1000. The gate bus line1500illustrated in the example ofFIG. 1is not formed in this example. The second gate bus line1600is electrically connected to a trench gate electrode formed on a cell region1000. Thus, a signal is input on the trench gate electrode215through the second gate bus line1600. Also, the second gate bus line1600is formed with a metal layer of Al or Cu to reduce resistance.

FIG. 7illustrates a plane view of a power semiconductor device of the present examples. Referring to the example ofFIG. 7, a trench gate structure210that divides the active region of a semiconductor chip is formed in a network shape that is connected in a net shape. The emitter contact region Ec is formed in a region that is divided by the trench gate structure210. The emitter contact region Ec includes an N+ source region230and P+ contact region235that electrically contact an emitter electrode. Further, a floating region DF220is formed to be isolated from a trench emitter structure290. The floating region DF220is a P-type doping region that is completely surrounded by a trench emitter structure290, and therefore the floating region is a completely isolated structure.FIG. 7illustrates a trench gate structure210surrounding the floating region that is an opposite approach to the approach ofFIG. 2. InFIG. 2, the floating region DF20surrounds the trench gate structure10, and hence is an opposite structure to that ofFIG. 7. The feature is desirable in terms of managing Miller capacitance effects. These issues are discussed further with respect toFIG. 9.

A power semiconductor device of the present examples is illustrated inFIG. 8. A plurality of deep trenches211,212,213and214is formed, each having a predetermined depth from the upper semiconductor substrate. However, trench emitter electrode217is formed in two of the trenches212and213, which are electrically connected using a top emitter electrode280. The deep trenches212and213form a trench emitter structure290as shown in the example ofFIG. 7. Trench gate electrodes215are formed in the trenches211,214that are disposed outside the trenches212,213. Trench gate electrodes215are electrically connected with a gate bus line1600or a gate pad3000, in examples. Hereinafter, for the convenience of explanation, is the deep trenches211,212,213, and214are referred to as a first trench211, a second trench212, a third trench213, and a third trench213and a fourth trench214.

In an example, the first to fourth trenches211,212,213and214are formed through an etching of the substrate, and then the trench gate electrode or trench emitter electrode are selectively formed in the trench. Herein, the trench gate electrode215and the trench emitter electrode217are formed by using the same process and the same material. If the electrode in the trench is electrically connected with the emitter electrode280, it is called a trench emitter electrode217. If the electrode in the trench is electrically connected with the gate pad3000or gate bus lines1500and1600, it is called a trench gate electrode215. Thus, the trench gate electrode215and the trench emitter electrode217are electrically connected with the gate pad3000and emitter electrode280, respectively.

All of the deep trenches211,212,213and214are filled with an insulation layer and a conductive material. For example, the conductive material is polysilicon in certain examples. However, appropriate alternative materials are used in other examples. In particular, the deep trenches211and214comprise gate insulation layers216and218and electrode materials215and217. The insulation layers216,218are formed along the sidewalls of the deep trenches211,212,213and214. In an example, the gate insulation layer216and the gate insulation layer218are formed through the same process as one another, such as with a silicon oxide layer or silicon oxide layer and a silicon oxynitride layer. However, as noted above, other appropriate materials are used in other examples.

Thus, in this example, the two trench emitter electrodes217are connected with conductive material217B and the trench emitter electrodes217are formed in the second trench212and third trench213, respectively. The conductive material217B is formed of the same material as the trench emitter electrode217, which is formed over the floating region220. The conductive material217B has a bridge shape that connects the plurality of trench emitter electrodes217. In the example, an upper side of the conductive material217B is partially exposed. Accordingly, one side of exposed the conductive material217B can electrically connect with the emitter electrode280. Thus, the trench emitter electrode217is electrically connected with the emitter electrode280. That is, in the example, the two trench emitter electrodes217are not used to open a channel region. Because a source region230is not formed in the periphery region of the trench emitter electrodes217, that aspect of the design also supports this approach.

The floating region220doped with a P-type dopant is similar in form to the corresponding floating region previously discussed. The P-type floating region220is formed between the second trench212and the third trench213. The floating region220is surrounded by the second trench212and the third trench213. In addition, the floating region220has a greater depth than those of the second trench212and the third trench213. Furthermore, the floating region220is configured to surround the bottom corners of the first and second trench emitters212,213, which means that the bottom surfaces of the second trench212and the third trench213are configured to be in contact with the P-type floating region220.

In addition, the P-type floating region DF220contacts the n-drift region250, which results in the formation of a PN junction region. The P-type floating region220is not electrically connected to any P-type semiconductor region, such as, for example, P-type base region240. Thus, the P-type floating region220is not connected to any ground potential. Thus, the P-type floating region220assumes a completely electrically floating state. Also, the P-type floating region220has a lower doping concentration than that of the P-type base region240. When a doping concentration of the P-type floating region increases more than that of the P-type base region240, an unwanted parasitic capacitance value is possibly induced. Hence, an N-type well region245is formed between the P-type floating region220and P-type base region240. Thus, the P-type floating region220does not contact P-type base region240, avoiding the issue discussed above. Such an N-type well region245is in contact with both the P-type floating region220and the P-type base region240. Here, the N-type well region245has a higher doping concentration than that of the n-drift region250. However, the formation of N-type well region245is an optional process. If no N-type well region245is present, the depth of the P-type base region240is to be adjusted so that it does not contact the P-type floating region220. If the P-type base region240contacts the P-type floating region220, the floating state of P-type floating region is not maintained. In addition, the N-type well region245plays a role of a barrier for moving the hole carrier toward the source region from the drain region.

An occupied area of P-type base region240decreases in size in a whole cell region, because the floating region220is formed between the second trench212and the third trench213. Thus, in the presence of a P-type floating region, this approach makes hole carriers slowly discharge toward source region230from a collector layer257during a turned-off state. In the presence of a P-type floating region220, the hole carriers stay for a longer time in the n-drift region250than in an approach without the formation of a P-type floating region. Thus, an amount of hole carriers increases in the n-drift region250and electron carriers move to the n-drift region250in order to compensate the hole carriers, and electron carriers are able to sufficiently accumulate in the n-drift region250. Thus, conductivity modulation is further efficiently executed. Here, Vce decreases between a collector and an emitter electrode as carrier density increases. Both holes and electrons accumulate below the floating region220, and therefore it requires more time for the extra carriers to move out. This phenomenon potentially generates a switching loss issue.

Further, it is appropriate to optimize a thickness of an n-drift region250. If the n-drift region250becomes too thin, the breakdown voltage of the semiconductor device is potentially degraded. A sufficient depth of the depletion region is obtained from a thicker n-drift region250. Accordingly, an n-drift thickness is recommended to have a thickness of around 100 μm between the floating region and the N+ buffer region255. The floating region has a thickness around 8˜9 μm. The thickness of the floating region220is preferably 8˜10% of the n-drift region250with respect to obtaining a reasonable breakdown voltage and a sufficient depletion region.

Further, the power semiconductor device is potentially formed as being based on various semiconductor substrates. For example, the substrate is potentially applied as an epi-wafer doped with an N-type or P-type impurity. For example, a Cz wafer made by a Czochralski method, which is favorable for large caliber wafer manufacture, or a wafer with an epi-layer grown on a substrate, are examples of possible approaches to forming an epi-wafer. However, these are merely examples and are not intended to be limiting. Further, a wafer with an N-type epi-layer that is lightly doped is optionally used in another example. Further, in certain examples, the semiconductor substrate optionally includes two epi-layers with different doping concentrations. In such an example, an epi-layer with a high impurity concentration operates with a field stop layer, such as buffer layer255and the epi-layer with lower impurity concentration than the field stop layer255and configured on the field stop layer255is operated with a drift region250. A power semiconductor according to an example is also optionally applied with an epi-wafer of a different concentration but examples are not limited to the aforementioned examples. For example, the field stop layer and drift region are formed through ion-injection of impurities with different concentrations with respect to the semiconductor substrate.

Hereinafter, an explanation of identical technical feature is omitted and differences from a first example are compared when illustrating features of a power semiconductor device according to a second example.

As shown inFIG. 8, a highly doped N-type source region230, a highly doped P-type contact region235and a lowly doped P-type base region240are formed on the both sides of the first trench211and the fourth trench214. However, no N-type source region230is formed on both sides of the second trench212and the third trench213, which results in no channel region being formed. If there is no channel region, an amount of current from an emitter electrode280to a collector layer257is decreased. However, in such an approach, short-circuit characteristics improve. The lowly doped P-type base region240is formed over an N-type drift region250and it surrounds a bottom corner of the N-type source region230and the P-type contact region235.

The base region240has a shallower depth than that of the trenches211,212,213and214from the top surface of the semiconductor substrate. Furthermore, the base region240has a smaller width than that of the floating region220, which correspondingly increases cell density. An N-type drift region250is formed over the N+ buffer255and it contacts both the N-type well region245and a floating region220. The drift region250surrounds the bottom corner of the floating region220and is formed to have a deeper depth than that of the floating region220, as illustrated inFIG. 8. The N-type field stop layer or N+ buffer255is formed on the P+ collector layer257. Also, the field stop layer255is formed to have a higher impurity concentration than the drift region250as aforementioned.

In this example, a drain electrode259is formed on a lower side of a semiconductor substrate formed with the field stop layer255and a P-type collector layer257through deposition of a back metal layer. Further, an insulation layer260is formed over the floating region220.

Here, according to an example, the insulation layer270is formed over the conductive material217B, however, a portion of the insulation layer270is removed to expose the upper side of the conductive material217B. In this manner, the trench emitter electrode217is electrically connected with the emitter electrode280.

The aforementioned first embodiment has a large Miller capacitance that is discussed further with respect toFIGS. 9A-9B. As illustrated inFIG. 9A, when there is only a trench gate structure, a capacitance value has CM=CGC+CGF+CFCdue to a floating region, wherein the CMdenotes total miller capacitance, CGCdenotes the gate-collector capacitance between gate electrode215and P+ collector layer257, CGFdenotes the gate-floating capacitance between the gate electrode215and the floating region220, CFCdenote the floating-collector capacitance between the floating region220and the P+ collector layer257. CGFand CFCare generated because there is a channel region in the floating region.

By contrast to the example ofFIG. 9A, as illustrated inFIG. 9B, if some of the trench gate electrodes are connected to emitter electrodes, the total Miller capacitance CMsignificantly decreases. As shown inFIG. 9B, if both the trench gate electrode and the trench emitter electrode are formed as provided in the discussion above, the capacitance value becomes CM=CGC. Only the gate-collector capacitance CGCremains. That is, the CGF+CFCvalues disappear because there is no channel region. If the trench gate electrode is connected to an emitter electrode280, as a result the trench gate electrode is no longer a gate electrode playing a role of opening and closing the channel. Likewise, a switching delay reduces when Miller capacitance value decreases and power loss decreases accordingly. That is, switching loss also decreases substantially. Further, a Miller period time decreases, and thus energy loss decreases accordingly, and energy loss required for turning-on also decreases. These effects occur because current is able to flow out immediately into the emitter electrode. This effect is advantageous in achieving a low switching power loss and a small gate driving force.

FIG. 10is a cross section of a periphery termination region according to a second example. A plurality of deep trenches226,227,228is formed. The P-type base region240is formed between the deep trenches226,227,228. The trench emitter electrode217that is electrically connected with an emitter electrode280is formed in a deep trench226. Furthermore, a gate insulation layer218is formed on the sidewall of the deep trench226.

A trench gate electrode215is formed in the deep trench227and the dummy trench228. An N+ source region230is arranged on both sides of the deep trench227. The dummy trench228is formed between the deep trench227and a JTE ring region295. The N+ source region230is not formed on both sides of the dummy trench228. That is, in this portion of this example, a channel region does not exist.

Further, a JTE ring region295is formed near the dummy trench228. The JTE ring region295optionally includes a plurality of field rings, but is illustrated as only forming one JTE ring region295in the drawing, but the present examples is not limited to only one JTE ring region295. However, in examples there is potentially actually a plurality of the field rings in a termination region2000. Thus, in this example, when the JTE ring region295extends to a bottom surface of the dummy trench228, there is no problem with respect to device features because there is no channel region in the JTE ring region. Rather, when the JTE ring region is in contact with the bottom surface of the dummy trench228, it is advantageous for a breakdown voltage feature because there is an effect of relieving an electric field.

The second gate bus line1600is formed to overlap with the JTE ring region295on the termination region2000. Furthermore, the second gate bus line1600is electrically connected through the trench gate electrode215and the conductive material215B. The trench emitter electrode217is electrically connected to the emitter electrode280. Other regions of this example are similar to those presented with respect to the aforementioned regions.

A power semiconductor device according to a third example is formed as having a hybrid structure of a power semiconductor device according to a first example and a power semiconductor structure according to a second example, with reference toFIG. 11andFIG. 12.

FIG. 11is a top view of a power semiconductor device according to a third example.FIG. 12is a diagram shown according to a cross-section F-F′ of the example ofFIG. 11.

As illustrated in the example ofFIG. 11, a power semiconductor device according to a third example includes an active region of a semiconductor chip divided with a trench gate structure310that is similar with that of a second example. Herein, a floating region320is surrounded by the trench emitter structure390. Furthermore, the emitter contact region Ec is surrounded by the trench gate structure310. Herein,FIG. 11divides the power semiconductor device into a first region and a second region for convenience of explanation. The first region is the floating region320that is surrounded by the trench emitter structure390. Further, the second region is the emitter contact region Ec surrounded by the trench gate structure310. Thus, the first region and the second region are formed alternately. Herein, the third region is identical with the first region, located in a different area of the power semiconductor device. The network trench gate structure310N has a form that is connected in a network, having a net shape, connecting portions of the network trench gate structure with each other. The network trench gate structure310N is formed across the region between the first region and the second region. That is, the network trench gate structure310N divides the elements of the first region and the second region. Further, the first region and the second region have an X-type structure and a Y-type structure, respectively.

Referring toFIG. 11, a chip structure of a power semiconductor device according to a third example is divided into six regions by a trench gate structure310. Herein, the six regions are divided into inner and outer regions by an electrode that is formed in each of the trench structures. Further, the inner and outer regions are potentially formed with combinations of a floating region DF and an emitter contact region Ec, or alternatively an emitter contact region Ec and a floating region DF. Thus, each region is divided with a DF structure or an Ec structure in reference to a name of the region formed in the middle of each of the six regions, for convenience of explanation.

That is, six regions that are divided by the network trench gate structure310N are divided according to the following table, referring toFIG. 11.

That is, X-type and Y-type regions are formed alternately. Only Y-type exists around X-type and by contrast, only X-type exists around Y-type. That is, each region is formed to be different with the adjacent region. The X-type structure includes the trench emitter structure390, and thereby divides inner and outer regions and the floating region DF320is formed in the trench emitter structure390. The emitter contact region Ec is formed in the outer region. The trench emitter structure390is all electrically connected with an emitter electrode380, as seen with respect toFIG. 12.

By contrast, a Y-type structure includes the first trench gate structure310that divides inner and outer regions, and the emitter contact region Ec is formed in the trench gate structure310and a floating region DF320is formed in an outer region. Furthermore, a network trench gate structure310N that surrounds the emitter contact region Ec is formed. The network trench gate structure310N electrically connects these regions with each other. All of them are connected with a gate electrode315, as seen with reference toFIG. 12.

The particular features of the power semiconductor device with the above structure refers to the example ofFIG. 12and the particulars are illustrated and discussed further in the following description.

Hereinafter, in illustrating the features of a power semiconductor device according to a third example, illustration regarding identical features is omitted and differences are presented illustrating changes with respect to a first example and a second example.

First, as illustrated inFIG. 12, six deep trenches321,322,323,324,325, and326are formed having a predetermined depth from the upper semiconductor substrate. Additionally,FIG. 12illustrates a feature that six deep trenches are formed, unlikeFIG. 3andFIG. 8.

InFIG. 12, a trench emitter electrode317is formed in the deep trench323,324, which contacts an emitter electrode380. A plurality of trench gate electrodes are formed in the trench321,322,325,326, which are electrically connected with a gate pad, not shown, or a gate bus line, not shown.

The deep trench is also potentially formed by an etching process with regard to the semiconductor substrate and respective trenches are formed with a similar or identical depth through a similar or identical process.

Each trench includes an insulation layer and an electrode. In particular, the trenches323,324include thin insulation layers318and the trench emitter electrode317. Trenches321,322,325,326include the gate insulation layer316and a gate electrode315. In this example, an electrode is formed in each trench and the insulation layers316,318are formed between the electrodes315,317and the trench.

The P-type floating region320is formed on the region between the trenches321,322, the region between the trenches323,324, and the region between the trenches325,326so as to surround a bottom region of the trenches321,322,323,324,325,326. Herein, the floating region320is configured to surround the bottom region of each of the trench structures321,322,323,324,325,326. Thus, the bottom surfaces of the trenches contact the P-type floating region320.

An N-type source region330is formed on sides of trenches321,322,325,326. However, no N-type source region330is formed on sides of trenches323,324.

The features are presented according to the disclosed structures of a P-type contact region335, P-type base region340, an N-type well region345, an N-type drift region350, an N-type field stop layer355, a P-type collector layer357, a drain electrode359, and insulation layers360,370. Further, in an example, the base region340width is formed to be smaller than the floating region320width. However, as the width of the base region340becomes smaller, the effect on channel diffusion of an active cell due to side diffusion of the floating region320increases, a hence proper determination of the width according to a desired feature of the semiconductor device is advisable.

A plurality of trench gate electrodes315are electrically connected with a gate pad for supporting features and functionality of the power semiconductor operation discussed further above. By contrast, the trench emitter electrodes317are electrically connected with an emitter electrode380.

A power semiconductor device according to examples provides a power semiconductor device with low Vce (sat) without reduction of BVCES compared to alternative technologies and an improved switching function through the aforementioned features and approaches.