Electrically reconfigurable interposer with built-in resistive memory

An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

BACKGROUND

Field

The present disclosure generally relates to integrated circuits (ICs). More specifically, one aspect of the present disclosure relates to an electrically reconfigurable interposer with built-in resistive memory.

Background

The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle of line (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate contact formation. Middle of line layers may include, but are not limited to, MOL contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.

An interposer is a die-mounting technology in which the interposer serves as a base upon which the semiconductor dies of a system on chip (SoC) are mounted. An interposer may include wiring layers of conductive traces and conductive vias for routing electrical connections between the semiconductor dies (e.g., memory modules and processors). In most applications, the interposer does not include active devices such as diodes and transistors.

SUMMARY

An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

A system on chip (SOC) may include an interposer. The system on chip may also include a resistive-type non-volatile memory (NVM) array(s). The resistive-type NVM array(s) may be partially embedded within the interposer. The system on chip may include interconnections configured to couple the resistive-type NVM array(s) to a die(s).

An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include means for interconnecting the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the interconnecting means. The substrate may support the interconnecting means.

A method of fabricating an integrated interposer may including fabricating a resistive-type non-volatile memory (NVM) array(s) within a dielectric layer on a first surface of an interposer substrate. The method may also include plating a conductive material within the dielectric layer. The method may further include etching the conductive material within the dielectric layer to form a contact layer on the first surface of the interposer substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

DETAILED DESCRIPTION

Resistive memory technologies, such as magnetic random access memory (MRAM), resistive RAM (RRAM), and phase change memory (PCM), are maturing at a rapid pace. These resistive memory technologies can potentially provide non-volatile memory (NVM) solutions for a wide range of density and performance design points. In particular, many applications specify a small amount of NVM. For example, current techniques for providing NVM include embedded NVM, such as eFLASH or other like resistive memory. Unfortunately, the additional process steps for creating FLASH or a resistive memory macro often is not justified if only a small amount of memory is specified. Another option is a separate FLASH chip or resistive memory. Unfortunately, this solution provides limited bandwidth and consumes additional power due to off-chip input/output (I/O). A further option is battery-backed dynamic RAM (DRAM).

Because resistive memory devices do not involve semiconducting devices, resistive memory devices can be fabricated (e.g., embedded) within the interconnect levels of a device. Accessing these embedded resistive memory devices (read, write, and bit selection), however, involves active semiconductor devices. For example, embedded resistive memories like spin-transfer-torque (STT) MRAM (STT-MRAM), RRAM, or PCM, when integrated within logic interconnect levels, could affect the resistive capacitive (RC) or reliability characteristics of the interconnect level. Some resistive memory technology might also impose process limitations that are incompatible with logic-optimized interconnect fabrication.

Embedded resistive memories like STT-MRAM, RRAM, or PCM, when coupled with an active semiconductor selection transistor to form a one-transistor one-resistor (1T1R) bitcell, involve a stacked-conductive structure to electrically connect the bottom side of the resistive memory device to the transistor. In a typical logic-interconnect process, however, patterning specifications from synchronous RAM (SRAM) and signal routing generally dictate layout rules. As a result, the minimum area of the stacked-metal connection is large, as compared with a typical resistive memory size. This creates a severe bitcell size limitation when implementing embedded resistive memories.

Some described implementations relate to interposer technology. An interposer generally serves as an intermediate layer that can be used for direct electrical interconnection between one component or substrate and a second component or substrate with the interposer positioned in between. For example, an interposer may have a pad configuration on one side that can be aligned with corresponding pads on a first component (e.g., a die), and a different pad configuration on a second side that corresponds to pads on a second component (e.g., a package substrate, system board, etc.) Interposers are widely used for integrating multiple chips on a single package. In addition, interposer substrates can be composed of glass and quartz, organic, or other like material and normally contain a few interconnect layers.

Various aspects of the disclosure provide techniques for embedding resistive memory within an integrated interposer. The process flow for semiconductor fabrication of an integrated interposer may include front-end-of-line (FEOL) processes, middle of line (MOL) processes, and back-end-of-line (BEOL) processes. It will be understood that the term “layer” includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described herein, the term “substrate” or “interposer substrate” may refer to a substrate of a diced wafer or may refer to the substrate of a wafer that is not diced. Similarly, the terms wafer and die may be used interchangeably unless such interchanging would tax credulity.

In one aspect of the present disclosure, at least one resistive-type non-volatile memory (NVM) array is embedded within an integrated interposer. In some configurations, a contact layer on a surface of the interposer substrate includes interconnections. These interconnections may be configured to couple the resistive-type NVM array(s) to at least one die. In this arrangement, the resistive-type NVM array(s) is at least partially embedded within the contact layer of the integrated interposer. In another configuration, the resistive-type NVM array(s) is field reconfigurable to selectively couple at least a first die and a second die to a bus within the contact layer of the integrated interposer.

According to one aspect of the disclosure, an integrated interposer with a glass, quartz or organic substrate includes embedded resistive memory. Active selection devices for the resistive memory may be fabricated based on low cost thin film technology (e.g., thin film active devices). These thin film active devices can be organic. The resistive memory may be field reconfigurable to selectively couple at least a first die and a second die to a bus within a contact layer of the integrated interposer. This configuration enables the combination of an active die for targeted (e.g., high performance) technologies for each system functionality (processor, modem, memory, etc.), while the integrated interposer provides other functionality (e.g., reconfigurable die interconnection, embedded resistive memory, embedded active selection devices) and interconnection to a system board.

FIG. 1show a cross-sectional view illustrating a system on chip (SoC)100having an integrated interposer110including an interposer substrate120and a contact layer130on a surface of the interposer substrate120. The interposer substrate120may be a semiconductor substrate (e.g., a silicon wafer) or an organic substrate (e.g., glass, quartz, sapphire, or other like organic material). The contact layer130is disposed on the interposer substrate120including interconnections140. In addition, active die180(180-1,180-2) are coupled to the contact layer130of the integrated interposer110through a second set of interconnects104.

A first set of interconnects102may couple a system board190to the integrated interposer110through, for example, a redistribution layer (not shown). Although shown with reference to the system board190, it should be recognized that the first set of interconnects102may be coupled to a printed circuit board (PCB), a package substrate or other like carrier substrate to the integrated interposer110. In some configurations, one or more devices may be attached to each side of the integrated interposer110.

FIG. 2shows a cross-sectional view illustrating a system on chip (SoC)200including a resistive memory250at least partially embedded within an integrated interposer210according to one aspect of the present disclosure. In this configuration, the resistive memory250is disposed on a surface of the interposer substrate220and embedded within a contact layer230on the surface of the interposer substrate220. Representatively, the contact layer230includes interconnections240(e.g., electrical traces) coupling the resistive memory250to the active die180.

In this configuration, the resistive memory250stores device configuration data (e.g., redundancy data, configuration settings, boot code, etc.) The resistive memory250may be configured as an embedded resistive memory including, but not limited to, spin-transfer-torque (STT) MRAM (STT-MRAM), RRAM, or PCM, integrated within the logic interconnect levels (e.g., interconnections240) of the contact layer230without negatively affecting the resistive capacitive (RC) or reliability characteristics of the contact layer230. In one aspect of the disclosure, the resistive memory250is arranged to provide off-chip cache memory (e.g., level four (L4) cache memory) for the active die180.

In one aspect of the present disclosure, the resistive memory250is fabricated between two interconnect levels of the integrated interposer210, without active selection devices being created on the integrated interposer210. In another aspect of the present disclosure, the resistive memory250is fabricated along with the active selection devices within the integrated interposer210. In this arrangement, the active selection devices may be implemented using thin film devices (e.g., thin film diodes, thin film transistors, etc.) built on one of the interconnect levels within the integrated interposer210. In a further aspect of the present disclosure, the resistive memory250is fabricated along with the active selection devices on a semiconductor (e.g., silicon) interposer in which the active selection devices within the integrated interposer are fabricated on a semiconductor interposer substrate.

In these arrangements, peripheral circuits, including decoders, sense-amps, and some control logic, is fabricated using the same thin-film-transistor devices or bulk devices on a silicon interposer substrate. Alternatively, at least a portion of the control logic is built on the active die (e.g.,180) instead of on the integrated interposer210. The noted thin film diode or thin film transistor selection devices could be stacked to increase an efficiency of a resistive memory array. For example, the decoder circuit and the sense-amp circuit could be fabricated on a first layer of thin film transistors or a silicon interposer substrate, while the resistive memory array with thin film diode or thin film selection devices is fabricated in the same physical area, as described in further detail below.

FIGS. 3A and 3Bare block diagrams illustrating resistive memory cells according to one aspect of the disclosure.FIG. 3Afurther illustrates the resistive memory250ofFIG. 2. In this arrangement, each resistive memory350is coupled to an interconnect (e.g.,342,344,346) within a contact layer330of an integrated interposer310. The resistive memory cells300(e.g., bit cells) also include active selection devices360within an active layer332(e.g., an oxide layer, a dielectric layer, etc.) of the contact layer330. Alternatively, the active layer332may be a silicon substrate or other like layer to enable fabrication of the active selection devices360. The active selection devices360may be implemented using thin film devices (e.g., thin film diodes, thin film transistors, etc.) built on one of the interconnect levels (e.g., contact layer330) within the integrated interposer310.

FIG. 3Bfurther illustrates one of the resistive memory cells300ofFIG. 3Afor a memory device including the resistive memory350(e.g., magnetic tunnel junction (MTJ)) coupled to one of the active selection devices360(e.g., an access transistor). The memory device may be a magnetic random access memory (MRAM) device that is built from an array of individually addressable MTJs. An MTJ stack may include a free layer, a fixed layer and a tunnel barrier layer there between as well as one or more ferromagnetic layers. Representatively, a free layer352of the resistive memory350is coupled to a bit line358. One of the active selection devices360is coupled between a fixed layer356of the resistive memory350and a fixed potential node368. A tunnel barrier layer354is coupled between the fixed layer356and the free layer352. The active selection devices360include a gate364coupled to a word line366.

Synthetic anti-ferromagnetic materials may form the fixed layer356and the free layer352. For example, the fixed layer356may comprise multiple material layers including a cobalt-iron-boron (CoFeB) layer, a ruthenium (Ru) layer and a cobalt-iron (CoFe) layer. In addition, the free layer352may also include multiple material layers including a cobalt-iron-boron (CoFeB) layer, a ruthenium (Ru) layer and a cobalt-iron (CoFe) layer. Further, the tunnel barrier layer354may be magnesium oxide (MgO).

The resistive memory cell ofFIG. 3Bmay be implemented using an STT-MRAM bit cell. The STT-MRAM bit cell may include a magnetic tunnel junction (MTJ) storage element. The MTJ storage element is formed, for example, from at least two anti-ferromagnetic layers (a pinned layer and a free layer), each of which can hold a magnetic field or polarization, separated by a thin non-magnetic insulating layer (tunneling barrier). Electrons from the two ferromagnetic layers can penetrate through the tunneling barrier due to a tunneling effect under a bias voltage applied to the ferromagnetic layers. The magnetic polarization of the free layer can be reversed so that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variance in resistance may program and read one of the resistive memory cells300.

FIG. 4is a block diagram illustrating an integrated interposer410including embedded resistive memory cells400composed of a resistive memory device450and a thin film diode as an active selection device460, according to one aspect of the disclosure. In this arrangement, the embedded resistive memory cells400are fabricated between a first interconnect level440(e.g., a conductive (Cu) trace) and a second interconnect level442of a contact layer430supported by an interposer substrate420(e.g., a glass substrate). In this arrangement, a thin film is deposited on the first interconnect level440to form a thin film diode as an active selection device460. The thin film may be a low-temperature polycrystalline silicon (LTPS) material, an indium gallium zinc oxide (IGZO) material, or other like thin film material.

FIG. 5shows a cross-sectional view500of an integrated interposer510including peripheral circuitry570fabricated within, for example, a contact layer of the integrated interposer510according to one aspect of the disclosure. The peripheral circuitry570may include thin film transistors574having a gate on a surface of an interposer substrate520(e.g., a glass substrate). The gate may be fabricated first and the channel material deposited later. In this arrangement, a thin film572(e.g., low-temperature polycrystalline silicon) is deposited on the surface of the interposer substrate520and on the thin film transistors574. The peripheral circuitry570also includes a source line (SL)576and bit lines578for accessing the resistive memory550.

In this aspect of the present disclosure, thin film active devices are embedded within an integrated interposer510to enable formation of the peripheral circuitry570. These thin film active devices can be organic. A further arrangement of these thin film active devices for forming the peripheral circuitry570to control access to/from the resistive memory550is shown, for example, inFIG. 6.

FIG. 6is a block diagram illustrating an integrated interposer610in which the peripheral circuitry670and the resistive memory cells600(650,660) are arranged within the interconnect levels of a contact layer630, according to one aspect of the disclosure. In this arrangement, the peripheral circuitry670is fabricated between a first interconnect level640(e.g., a conductive (Cu) trace) and a second interconnect level642of a contact layer630supported by an interposer substrate620(e.g., a glass substrate). In addition, the resistive memory cells600are fabricated between the second interconnect level642and a third interconnect level644of the contact layer630. In this arrangement, a thin film is deposited on the second interconnect level642to form a thin film diode as an active selection device660.

In this arrangement, a decoder circuit and a sense-amp circuit of the peripheral circuitry670are fabricated on a first layer of thin film transistors674, while the resistive memory650with thin film diode or thin film selection devices (e.g.,660) is fabricated in the same physical area. Alternatively, the peripheral circuitry670may be fabricated on a silicon interposer substrate or on the active die. In one configuration, the peripheral circuitry670may be fabricated with a cross-bar architecture to control access to/from the resistive memory650.

The various interposers described above allow integration of heterogeneous chips (logic, memory, etc.) into a single package. The interposers may be configured as low-cost, passive interposers. Unfortunately, the interconnections between chips or between any functional devices (passive, memory protection unit (MPU), memory, analog, etc.) on the interposer are fixed. In an example case where an MPU and a DRAM are placed on an interposer, a bump pattern from the different DRAM vendors should match each other for the same interposer to be used. In another scenario, where a high-speed data bus on the interposer transfers data between dies, it is desirable to be able to trim the impedance of the lines to optimize data rate.

FIG. 7shows a cross-sectional view illustrating a system on chip (SoC)700including a re-configurable interposer710having an embedded memory750according to one aspect of the present disclosure. The embedded memory750may be configured as multi-time programmable (MTP) memory, including pseudo-MTP. Alternatively, the embedded memory750may be configured to provide a small amount of NVM (e.g., RRAM, MRAM, PCM, etc.) In this configuration, the embedded memory750enables field reconfiguration of a high-speed die-to-die bus740within a contact layer730of the re-configurable interposer710. Field reconfiguration of a high-speed die-to-die bus740may include selectively coupling a first die780and a second die782to the high-speed die-to-die bus740.

Re-configuration of the re-configurable interposer710enables an active die for targeted (e.g., high performance) technologies for each system functionality (processor, modem, memory, etc.). Furthermore, the re-configurable interposer710provides other functionality (e.g., reconfigurable die interconnection, embedded resistive memory, embedded active selection devices) and interconnection to the system board190. The re-configurable interposer710enables re-routing of the high-speed die-to-die bus740. In addition, re-configuration of the re-configurable interposer710enable tuning of the high-speed die-to-die bus740for improved transmission as well as improved access to internal nodes during testing.

As noted, the embedded memory750may be pseudo-MTP when implemented as an e-fuse or anti-fuse. Alternatively, the embedded memory750may be configured as resistive memory that is built on an interposer substrate720(e.g., silicon or glass) using thin-film devices. Whether configured as either MTP or NVM, the embedded memory750enables configuration of the interconnects within the contact layer730to accommodate dies with a heterogeneous bump out. The interconnects within the contact layer730can be fine-tuned to match the input/output (I/O) of the dies post packaging. Furthermore, field reconfiguration of the re-configurable interposer710allows switching of package contacts during testing.

In the configuration described above, a glass interposer substrate can be thinned by etching the glass to a desired thickness. The desired thickness of the glass may vary according to the targeted thickness for fabrication of, for example, thin film transistors (TFTs) (e.g., five-hundred (500) micron thickness). The interposer application, however, may target a fifty (50) to two-hundred fifty (250) microns thickness. In this arrangement, the glass interposer substrate is thinned, for example, through wet etching with etchants (e.g., hydrofluoric acid (HF)). Etch protect layers shield the devices during the glass thinning and any cleaning processes of any via formation.

FIG. 8is a flow diagram illustrating a method800for fabricating an integrated interposer according to one aspect of the disclosure. At block802, at least one resistive-type non-volatile memory (NVM) array is fabricated within a dielectric layer on a first surface of an interposer substrate, for example, as shown inFIGS. 3A and 3B. Although the present description has mentioned silicon and glass interposer substrates, other substrate materials including sapphire or other like materials are also contemplated.

At block804, the dielectric layer is masked and etched to define interconnections within the dielectric layer. At block806a conductive material is plated within the dielectric layer. The patterned conductive material within the dielectric layer forms a contact layer on the first surface of the substrate. For example, as shown inFIG. 2, a contact layer230includes interconnections240configured to couple the resistive memory250to an active die180. In this configuration, the resistive memory is at least partially embedded within the contact layer230of the integrated interposer210.

In one configuration, an integrated interposer includes at least one resistive-type non-volatile memory (NVM) array on a first surface of an interposer substrate. The integrated interposer also includes means for interconnecting the at least one resistive-type NVM array to at least one die. The at least one resistive-type NVM array may be partially embedded within the interconnecting means. In one aspect of the disclosure, the interconnecting means is the contact layer230/330/430/630/730ofFIGS. 1, 2, 3A, 6 and/or 7, configured to perform the functions recited by the interconnecting means. In another aspect, the aforementioned means may be a device or any layer configured to perform the functions recited by the aforementioned means.

FIG. 9is a block diagram showing an exemplary wireless communication system900in which a configuration of the disclosure may be advantageously employed. For purposes of illustration,FIG. 9shows three remote units920,930, and950and two base stations940. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units920,930, and950include IC devices925A,925B, and925C, which include the disclosed integrated interposer. It will be recognized that any device containing an IC may also include the disclosed integrated interposer, including the base stations, switching devices, and network equipment.FIG. 9shows forward link signals980from the base station940to the remote units920,930, and950and reverse link signals990from the remote units920,930, and950to base stations940.

InFIG. 9, remote unit920is shown as a mobile telephone, remote unit930is shown as a portable computer, and remote unit950is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 9illustrates IC devices925A,925B, and925C, which include the disclosed integrated interposer, the disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in any device, which includes an interposer.