Semiconductor device

A semiconductor device in which the electrical connection is established using conductive pins and a printed wiring board, wherein the printed wiring board is mounted parallel to an insulated circuit board to prevent poor bonding of the conductive pins. A third-type conductive pin is arranged in such a manner as to be connected to a first metal layer at a position farther than a first-type conductive pin arranged at a position farthest from a side that is in contact with a gap between island regions. Similarly, another third-type conductive pin is arranged in such a manner as to be connected to another first metal layer at a position farther than another first-type conductive pin arranged at a position farthest from another side that is in contact with the gap between the island regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on, and claims foreign priority to, Japanese Patent Application No. 2015-117171, filed Jun. 10, 2015, the content of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor device such as a power device or a switching IC for high frequency applications, and more particularly to a semiconductor device equipped with a power semiconductor element.

2. Related Art

Power semiconductor devices often use bonding wires or lead frames for the electrical connection between the semiconductor elements thereof. Power semiconductor devices, such as the ones disclosed in Japanese Unexamined Patent Application Publication No. 2013-125804 and WO 2014/185050, which provide excellent heat dissipation with conductive pins and a printed wiring board, have started to be used as well.

However, according to the mounting methods described in Japanese Unexamined Patent Application Publication No. 2013-125804 and WO 2014/185050, the printed wiring board is tilted, lifting the conductive pins, and consequently causing poor electrical connection. The causes thereof were unknown.

SUMMARY

An aspect of the present disclosure is to provide a semiconductor device in which the electrical connection is established using conductive pins and a printed wiring board, wherein the printed wiring board is mounted parallel to an insulated circuit board to prevent poor bonding of the conductive pins.

In order to achieve the foregoing aspect, a semiconductor device of the present disclosure has: an insulated circuit board having an insulating substrate, a first metal layer disposed on one of principal surfaces of the insulating substrate and divided into a plurality of island regions, and a second metal layer disposed on the other principal surface of the insulating substrate; a semiconductor element that is bonded to the first metal layer; a printed wiring board that is disposed to face the first metal layer and extends over the plurality of island regions; first-type conductive pins each having one end fixed to the printed wiring board and the other end soldered to a surface electrode of the semiconductor element; second-type conductive pins each having one end fixed to the printed wiring board and the other end soldered to the first metal layer; and third-type conductive pins each having one end fixed to the printed wiring board and the other end soldered to the first metal layer, the third-type conductive pins being provided independently from an electric circuit, wherein each of the third-type conductive pins is arranged in each of the island regions adjacent to each other in the printed wiring board in such a manner as to be connected to the first metal layer at the same position as, or a position farther than, the first-type conductive pin or the second-type conductive pin that is arranged at a position farthest from a side that is in contact with a gap between the island regions.

In the semiconductor device of the present disclosure, of the island regions in which the third-type conductive pins are to be arranged, it is preferred that more of the third-type conductive pins be arranged in an island region that has a lower total number of the connected first-type conductive pins and a lower total number of the connected second-type conductive pins.

According to embodiments of the present disclosure, each of the third-type conductive pins, provided independently from an electric circuit, is arranged at the same position as, or a position farther than, the first-type conductive pin or the second-type conductive pin that is arranged at a position farthest from the side that is in contact with the gap between the island regions. Therefore, the printed wiring board can be prevented from tilting, preventing poor bonding of the conductive pins and consequently improving the non-defective product ratio of the semiconductor device.

DESCRIPTION OF EMBODIMENTS

A comparative example of the semiconductor device according to the present disclosure is described first for the purpose of enabling easy understanding of the characteristics of the semiconductor device.

Comparative Example

For example, a chopper control semiconductor device200can be configured by a MOS transistor1aand a diode1bthat are connected in series, as shown by an equivalent circuit inFIG. 5. When the MOS transistor1ais turned on by a control signal input to an external terminal55, a current flows from an external terminal51to an external terminal52, as shown by the solid arrow. When the MOS transistor1ais turned off, the current flows from the external terminal51to an external terminal53, as shown by the dashed arrow. The semiconductor device200is configured to be able to change the direction of the current alternately in this manner, and therefore can be used in, for example, an electric circuit for driving a motor.

As shown in the plan view ofFIG. 6Aand the cross-sectional diagramFIG. 6B, the semiconductor device200has an insulated circuit board10ato which are bonded six MOS transistors1athat are connected in parallel for the purpose of increasing the current capacity, an insulated circuit board10bto which are bonded three diodes1bthat are connected in parallel for the purpose of increasing the current capacity, a printed wiring board20(not shown in the plan view), conductive pins31athat are fixed to the printed wiring board20and bonded to surface electrodes of the MOS transistors1a, conductive pins32athat are fixed to the printed wiring board20and bonded to surface metal layers12a1,12a2of the insulated circuit board10a, conductive pins31bthat are fixed to the printed wiring board20and bonded to surface electrodes of the diodes1b, conductive pins32bthat are fixed to the printed wiring board20and bonded to surface metal layers12b2,12b3of the insulated circuit board10b, external terminals51through55, and thermosetting sealing resin70such as epoxy resin.

The insulated circuit board10ahas an insulation board11a, the metal layer12a1, which is disposed on one of the principal surfaces of the insulation board11aand to which the MOS transistors1aare bonded with solder4a1therebetween, metal layers12a2(two) to each of which the external terminal52is soldered, and a metal layer13athat is disposed on the other principal surface of the insulation board11aand can be connected to a cooler that is not shown.

The insulated circuit board10bhas an insulation board11b, a metal layer12b1, which is disposed on one of the principal surfaces of the insulation board11band to which the diodes1bare bonded with solder4b1therebetween, metal layers12b2(two) to each of which the external terminal54is soldered, metal layers12b3(two) to each of which the external terminal55is soldered, and a metal layer13bthat is disposed on the other principal surface of the insulation board11band can be connected to the cooler that is not shown.

The printed wiring board20is configured by an insulation board21, a metal layer22that is positioned on one of the principal surfaces of the insulation board21, faces the insulated circuit boards10aand10band is wired into an electric circuit, and a metal layer23that is positioned on the other principal surface of the insulation board21and wired into an electric circuit, wherein the metal layers22and23are electrically connected to each other by via holes that pass through the printed wiring board20and have inner circumferential surfaces thereof conductively plated.

The conductive pins31a,31b,32aare in a cylindrical or prismatic shape. The ends thereof at one side are press-fitted to the via holes provided in the printed wiring board20, and fixed to the printed wiring board20using a bonding member so as to be unremovable, and the ends thereof at the other side are soldered to the MOS transistors1a, the diodes1b, and the metal layers12a1,12b1,12a2,12b2,12b3of the insulated circuit boards.

The external terminals51through55extend to the outside of the sealing resin70through through-holes or cutouts provided in the printed wiring board20, in such a manner as to not come into contact with the printed wiring board20.

In the semiconductor device200, when the MOS transistors1aare on, the current flows from the external terminal51to the external terminal52through the metal layer12a1, solder4a1, MOS transistors1a, solder3a1, and conductive pins31aof the insulated circuit board10a, the metal layers22and23of the printed wiring board20, and the conductive pins32aof the metal layers12a2, as shown by the solid arrows. When the MOS transistors1aare off, the current flows from the external terminal51to the external terminal53through the metal layer12a1, solder4a2and conductive pins32aof the insulated circuit board10a, the metal layers22and23of the printed wiring board20, the conductive pins31b, solder3b1, diode1b, solder4b1, and the metal layer12b1of the insulated circuit board10b, as shown by the dashed arrows.

The semiconductor device200has a problem where the printed wiring board20tilts about a point P as a fulcrum and consequently the conductive pins31blift up, causing poor bonding F, as shown inFIG. 7.

The reasons are as follows. However, for illustrative purposes, the conductive pins soldered to the semiconductor element are referred to as “first-type conductive pins,” and the conductive pins soldered to the metal layers on the insulated circuit boards are referred to as “second-type conductive pins.”

First of all, the number of conductive pins arranged on the insulated circuit board10ais counted. The metal layer12a1of the insulated circuit board10ahas six MOS transistors1a, wherein each MOS transistor has two first-type conductive pins31aas source electrodes and one first-type conductive pin31aas a gate electrode. Therefore, a total of eighteen first-type conductive pins31aare arranged on the metal layer12a1of the insulated circuit board10a. The metal layer12a1also has eight second-type conductive pins32aarranged along the gap between the metal layer12a1and the metal layer12b1. There are two metal layers12a2to each of which the external terminal52is soldered, and four second-type conductive pins32aare bonded to each of these metal layers12a2. Therefore, a total of eight second-type conductive pins32aare arranged on these metal layers. Thus, a total of thirty-four conductive pins are arranged on the insulated circuit board10a.

Next, the number of conductive pins arranged on the insulated circuit board10bis counted. The metal layer12b1of the insulated circuit board10bhas three diodes1b, wherein each diode has two first-type conductive pins31bbonded thereto as anode electrodes. Therefore, a total of six first-type conductive pins31bare arranged on the metal layer12b1. There are two metal layers12b2to each of which the external terminal54is soldered, and one second-type conductive pin32ais bonded to each of these metal layers12b2. Therefore, a total of two second-type conductive pins32aare arranged on these metal layers. In addition, there are two metal layers12b3to each of which the external terminal55is soldered, and one second-type conductive pin32ais bonded to each of these metal layers12b3. Therefore, a total of two second-type conductive pins32aare arranged on these metal layers. Thus, a total of ten conductive pins are arranged on the insulated circuit board10b.

As described above, the insulated circuit board10ahas thirty-four conductive pins and the insulated circuit board10bhas ten, and the numbers of conductive pins are not balanced at all between these insulated circuit boards. Moreover, in order to lower the wiring resistance by connecting the insulated circuit board10aand the insulated circuit board10bat the shortest distance, the second-type conductive pins32aare grouped together at a side of the insulated circuit board10athat is close to the insulated circuit board10b, whereby the printed wiring board tilts easily about this side as in a seesaw.

A cause of the poor bonding F is as follows: when a solder paste for bonding the conductive pins is caused to reflow in order to mount the printed wiring board20having the conductive pins fixed thereto, the surface tension of the melted solder strongly pulls the printed wiring board20down at the insulated circuit board10ahaving more conductive pins and lifts the printed wiring board20at the insulated circuit board10bhaving less conductive pins.

First Embodiment

The present disclosure solves the foregoing problem by configuring the semiconductor device thereof as follows.

FIG. 1Ais a plan view of a chopper control semiconductor device100according to the present disclosure, andFIG. 1Bis a cross-sectional diagram thereof.FIG. 5shows an equivalent circuit of the semiconductor device100.

The semiconductor device100of the present disclosure has third-type conductive pins33a,33bthat are fixed to the printed wiring board20and bonded to the surface metal layers12a1,12b1of the insulated circuit board to prevent the printed wiring board20from tilting, wherein in the printed wiring board the third-type conductive pins33a,33bare electrically isolated from the wiring and independent of the electric circuits. The third-type conductive pins33a,33bare arranged according to the rules described hereinafter.

The semiconductor device100, therefore, has an insulated circuit board10ato which are bonded six MOS transistors1athat are connected in parallel for the purpose of increasing the current capacity, an insulated circuit board10bto which are bonded three diodes1bthat are connected in parallel for the purpose of increasing the current capacity, the printed wiring board20(not shown in the plan view), first-type conductive pins31athat are fixed to the printed wiring board20and bonded to surface electrodes of the MOS transistors1a, second-type conductive pins32athat are fixed to the printed wiring board20and bonded to surface metal layers12a1,12a2of the insulated circuit board10a, the third-type conductive pins33athat are fixed to the printed wiring board20and bonded to the surface metal layer12a1of the insulated circuit board10a, first-type conductive pins31bthat are fixed to the printed wiring board20and bonded to surface electrodes of the diodes1b, second-type conductive pins32bthat are fixed to the printed wiring board20and bonded to surface metal layers12b2,12b3of the insulated circuit board10b, the third-type conductive pins33bthat are fixed to the printed wiring board20and bonded to the surface metal layer12b1of the insulated circuit board10b, external terminals51to55, and thermosetting sealing resin70such as epoxy resin. It should be noted that the use of the thermosetting sealing resin70is not the only way to seal the semiconductor device; thus, a combination of a case and silicone resin can be selected as well.

The MOS transistors1aare each a vertical N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source electrode and a gate electrode on its front surface and a drain electrode on its rear surface. On the other hand, the diodes1bare each a vertical Schottky barrier diode having an anode electrode on its front surface and a cathode electrode on its rear surface. The MOS transistors1aand diodes1bmay be not the only semiconductor elements formed on a silicon substrate but also the semiconductor elements formed on a silicon carbide substrate.

The insulated circuit board10ahas an insulation board11a, the metal layer12a1, which is disposed on one of the principal surfaces of the insulation board11aand to which the MOS transistors1aare bonded with a bonding member4a1therebetween, metal layers12a2(two) to each of which the external terminal52is bonded, and a metal layer13athat is disposed on the other principal surface of the insulation board11aand can be connected to a cooler that is not shown.

The insulated circuit board10bhas an insulation board11b, the metal layer12b1, which is disposed on one of the principal surfaces of the insulation board11band to which the diodes1bare bonded with a bonding member4b1therebetween, metal layers12b2(two) to each of which the external terminal54is bonded, metal layers12b3(two) to each of which the external terminal55is bonded, and a metal layer13bthat is disposed on the other principal surface of the insulation board11band can be connected to the cooler that is not shown.

As described above, the insulated circuit boards10a,10bare the circuit boards in each of which the metal layers are arranged on either side of the insulation board, wherein the metal layers disposed on the principal surfaces to which the semiconductor elements are bonded are divided into island regions in specific shapes that are electrically insulated, to configure the electric circuits, and wherein the other principal surfaces each configure a cooling surface to be connected to the cooler. The materials of the insulation boards are not particularly limited, and materials that are excellent in thermal conductivity and have low dielectric loss are favorably used. The materials of the metal layers, too, are not particularly limited and metals having low electrical resistance are favorably used. Specific examples include a direct bonding copper substrate created by bonding a copper sheet directly to ceramics such as alumina, aluminum nitride or silicon nitride, and an active metal brazed copper substrate created by bonding a copper sheet to the ceramics with a brazing filler metal.

The materials of the bonding members4a1,4b1are not particularly limited, and for example, lead-free solder, a nano-silver paste (paste containing silver nanoparticles) or the like can be used.

The printed wiring board20is configured by an insulation board21, a metal layer22that is disposed on one of the principal surfaces of the insulation board21, faces the insulated circuit boards10aand10band is wired into an electric circuit, and a metal layer23that is disposed on the other principal surface of the insulation board21and wired into an electric circuit, wherein the metal layers22and23are electrically connected to each other by via holes that pass through the printed wiring board20and have inner circumferential surfaces thereof conductively plated. Here, the insulation board21may be made of ceramics such as alumina, aluminum nitride or silicon nitride or may be a resin product made of epoxy resin or the like containing fiberglass.

The conductive pins31a,31b,32a,33a,33bare in a cylindrical or prismatic shape. The ends thereof at one side are press-fitted to the via holes provided in the printed wiring board20, and fixed to the printed wiring board20using a bonding member so as to be unremovable. For instance, the inner circumferential surfaces of the via holes of the printed wiring board20or the surfaces of the press-fitted portions of the conductive pins can be plated with Sn, SnAg-based solder, SnBi-based solder, SnSb-based solder, SnCu-based solder, SnIn-based solder or the like, and then the conductive pins can be press-fitted and thereafter heated to the melting temperature, to perform fused bonding of the conductive pins.

The external terminals51through55have ends at one side fixed to the insulated circuit board10aor10b, and extend to the outside of the sealing resin70through through-holes or cutouts provided in the printed wiring board20, in such a manner as to not come into contact with the printed wiring board20. Therefore, the external terminals51through55are configured to not affect the posture of the printed wiring board20.

According to a first arrangement rule for the third-type conductive pins in the semiconductor device of the present disclosure, in each of adjacent island regions the third-type conductive pins are arranged at the same positions as, or positions farther than, the first-type conductive pins or second-type conductive pins that are arranged at the positions farthest from the sides that are in contact with the gap between the island regions.

According to this rule, the third-type conductive pins are arranged far away from the rotation fulcrum of the printed wiring board so as to be able to apply large moment of force to the printed wiring board. Therefore, even when the number of third-type conductive pins is low, the printed wiring board can easily be prevented from tilting. In addition, in the printed wiring board, the third-type conductive pins are electrically isolated from the wiring and independent of the electric circuits. For this reason, although the third-type conductive pins can be arranged on the insulated circuit boards in a less restrictive manner, the first arrangement rule has the advantage that the third-type conductive pins can be arranged more freely in the outer edge regions located away from the gap between the metal layers.

According to a second arrangement rule for the third-type conductive pins, of the island regions in which the third-type conductive pins are to be arranged, more of the third-type conductive pins are arranged in the island region that has a lower total number of the connected first-type conductive pins and a lower total number of the connected second-type conductive pins.

This rule can even out the moment of the force acting on the printed wiring board, easily preventing the printed wiring board from tilting.

The arrangement rules for arranging the third-type conductive pins on the metal layer12a1and the metal layer12b1drawn with solid lines are described hereinafter specifically with reference toFIG. 2. In this example, note that the metal layers12a2,12b2,12b3drawn with broken lines have small areas and no extra space and therefore do not have the third-type conductive pins arranged thereon.

The “sides that are in contact with the gap between the island regions” described in the first arrangement rule indicate sides La, Lb that are closest to each other among the sides configuring the gap between the metal layer12a1forming an island region and the metal layer12b1forming another island region.

The metal layer12a1has a total of twenty-six conductive pins arranged thereon, i.e., eighteen first-type conductive pins31aand eight second-type conductive pins32a. Of these twenty-six conductive pins, four first-type conductive pins31a1are arranged at positions farthest from the side La by a distance x1. Then, according to the first arrangement rule, three third-type conductive pins33aare arranged at positions away from the side La by a distance y1longer than the distance x1.

In the metal layer12b1, six first-type conductive pins31bare arranged at positions farthest from the side Lb by a distance x2. Then, according to the first arrangement rule, a total of eight third-type conductive pins33bare arranged, i.e., four at positions away from the side Lb by a distance y2longer than the distance x2, and four at positions away from the side Lb by a distance z2.

Prior to arranging the third-type conductive pins as described above, a total of twenty-six conductive pins are arranged on the metal layer12a1and a total of six conductive pins are arranged on the metal layer12b1. The difference between the total numbers is twenty. After the third-type conductive pins are arranged, a total of twenty-nine conductive pins are arranged on the metal layer12a1and a total of fourteen conductive pins are arranged on the metal layer12b1. The difference between the total numbers is then fifteen.

The positions of the eight second-type conductive pins32a1arranged adjacent to the side La correspond to the rotation fulcrum about which the printed wiring board20tilts. Therefore, these second-type conductive pins32a1do not contribute to the application of the moment of force and thus can be eliminated from the twenty-nine conductive pins arranged on the metal layer12a1, resulting in practically a configuration equivalent to the one in which twenty-one conductive pins are arranged on the metal layer12a1and a total of fourteen conductive pins are arranged on the metal layer12b1, with the difference between these numbers being reduced to seven.

Given that the total of eight second-type conductive pins on the two metal layers12a2are positioned in the vicinity of the fulcrum and are therefore eliminated and that the total of two second-type conductive pins on the two metal layers12b2and the total of two second-type conductive pins on the two metal layers12b3apply the moment of force, the difference in the number of conductive pins between the metal layer12a1and the metal layer12b1is practically three.

Arranging the third-type conductive pins in this manner can reduce the difference in the imbalance of the moment of force, reducing the tilt of the printed wiring board to the extent that does not affect the non-defective product ratio.

Note that the insulated circuit boards10aand10bdo not have to be divided into two, and the insulation boards11aand11bmay be integrated, in which the metal layers12a1,12a2,12b1,12b2and12b3may be formed on one of the surfaces and the metal layers13aand13bon the other surface.

The MOS transistors1aof the chopper control semiconductor device100may each be an IGBT (Insulated Gate Bipolar Transistor).

In addition, the semiconductor of the present disclosure does not have to be a chopper control semiconductor device and may be, for example, a bridge circuit in which an IGBT (switching element) and SBD (freewheeling diode) are mounted on the metal layer12a1as the semiconductor elements and an IGBT and SBD are mounted on the metal layer12b1as the semiconductor elements, an inverter control semiconductor device, or the like.

Second Embodiment

Another embodiment of the semiconductor device according to the present disclosure is now described.FIG. 3shows a plan view of a semiconductor device101. For the purpose of clear illustration, the diagram does not show any of the insulation boards, printed wiring board, external terminals, and sealing resin of the insulated circuit boards, but only shows semiconductor elements1c,1d, metal layers12c,12dof the insulated circuit boards, first-type conductive pins31c,31d, second-type conductive pins32c1,32d1, and third-type conductive pins33c1,33d1, which are all necessary for explaining the arrangement of the conductive pins. The metal layer12cand the metal layer12deach configure a rectangular island region and are adjacent to each other, wherein the sides thereof that are in contact with the gap between these two island regions are taken as a side Lc and a side Ld respectively.

The metal layer12chas a total of eleven conductive pins arranged thereon, i.e., six first-type conductive pins31cand five second-type conductive pins32c1. Of these eleven conductive pins, the conductive pin located farthest from the side Lc is one second-type conductive pin32c1which is arranged away from the side Lc by a distance x3. Then, according to the first arrangement rule, a total of three third-type conductive pins33care arranged, i.e., one at a position that is away from the side Lc by a distance y3longer than the distance x3, and two at positions away from the side Lc by a distance z3longer than the distance y3.

The metal layer12dhas a total of eight conductive pins arranged thereon, i.e., four first-type conductive pins31dand four second-type conductive pins32d1. Of these first-type and second-type conductive pins on the metal layer12d, the conductive pins located farthest from the side Ld are two second-type conductive pins32d1which are arranged away from the side Ld by a distance x4. Then, according to the first arrangement rule, a total of six third-type conductive pins33dare arranged, i.e., two at positions away from the side Ld by a distance y4equivalent to the distance x4, and four at positions away from the side Ld by a distance z4longer than the distance x4.

Prior to arranging the third-type conductive pins as described above, a total of eleven conductive pins are arranged on the metal layer12cand a total of eight conductive pins are arranged on the metal layer12d. The difference between the total numbers is three. After the third-type conductive pins are arranged, a total of fourteen conductive pins are arranged on the metal layer12cand a total of fourteen conductive pins are arranged on the metal layer12d, i.e., the same number of conductive pins are arranged on the metal layers. Consequently, the moments of force applied become balanced so that the printed wiring board does not tilt, improving the non-defective product ratio.

Third Embodiment

Another embodiment of the semiconductor device according to the present disclosure is now described.FIG. 4shows a plan view of a semiconductor device102. For the purpose of clear illustration, the diagram does not show any of the insulation boards, printed wiring board, external terminals, sealing resin, and case of the insulated circuit boards, but only shows semiconductor elements1e,1f,1g, metal layers12e,12f,12gof the insulated circuit boards, first-type conductive pins31e,31f,31g, second-type conductive pins32e,32f,32g, and third-type conductive pins33e,33f, which are all necessary for explaining the arrangement of the conductive pins. The metal layers12e,12f,12geach configure a rectangular island region and are arranged horizontally. Because the first-type conductive pins31gand second-type conductive pins32gon the metal layer12glocated in the middle are the pins acting as or adjacent to the fulcrum about which a printed wiring board, not shown, tilts, these conductive pins hardly contribute to the application of the moment of force. Therefore, without taking these conductive pins into consideration, the third-type conductive pins may be arranged in such a manner that the moment of force applied by the conductive pins arranged on the metal layer12eand the moment of force applied by the conductive pins arranged on the metal layer12fare balanced.

The side of the metal layer12ethat is in contact with the gap between the metal layer12eand the metal layer12gis taken as a side Le, and the side of the metal layer12fthat is in contact with the gap between the metal layer12fand the metal layer12gis taken as a side Lf.

The metal layer12ehas a total of twelve conductive pins arranged thereon, i.e., six first-type conductive pins31eand six second-type conductive pins32e. Of these twelve conductive pins, the conductive pin located farthest from the side Le is one second-type conductive pin32e1which is arranged away from the side Le by a distance x5. Then, according to the first arrangement rule, a total of three third-type conductive pins33eare arranged, i.e., one at a position that is away from the side Le by a distance y5longer than the distance x5, and two at positions away from the side Le by a distance z5longer than the distance y5.

The metal layer12fhas a total of nine conductive pins arranged thereon, i.e., four first-type conductive pins31fand five second-type conductive pins32f. Of these first-type and second-type conductive pins on the metal layer12f, the conductive pins located farthest from the side Lf are two second-type conductive pins32f1which are arranged away from the side Lf by a distance x6. Then, according to the first arrangement rule, a total of six third-type conductive pins33fare arranged, i.e., two at positions away from the side Lf by a distance y6equivalent to the distance x6, and four at positions away from the side Lf by a distance z6longer than the distance x6.

Prior to arranging the third-type conductive pins as described above, a total of twelve conductive pins are arranged on the metal layer12eand a total of nine conductive pins are arranged on the metal layer12f. The difference between the total numbers is three. After the third-type conductive pins are arranged, a total of fifteen conductive pins are arranged on the metal layer12eand a total of fifteen conductive pins are arranged on the metal layer12f, i.e., the same number of conductive pins are arranged on the metal layers. Consequently, the moments of force applied become balanced so that the printed wiring board does not tilt, improving the non-defective product ratio.

Any identification in this disclosure of problems, deficiencies, or other characterizations of any product or method of the related art does not imply or admit that such problems, deficiencies, or other characterizations were known in the prior art even if the product or method itself was known in the prior art.

Reference signs and numerals are as follows:1aMOS transistor (semiconductor element)1bDiode (semiconductor element)1c,1d,1e,1f,1gSemiconductor element3a1,3b1,4a1,4a2,4b1Bonding member10a,10bInsulated circuit board11a,11bInsulation board12a,12a1,12a2,12b,12b1,12b2,12b3,12c,12d,12e,12f,12gMetal layer to which semiconductor element is bonded13a,13bMetal layer bonded to cooler20Printed wiring board21Insulation board of printed wiring board22,23Metal layer of printed wiring board31a,31bFirst-type conductive pin32a,32bSecond-type conductive pin33a,33bThird-type conductive pin51,52,53,54,55External terminal70Sealing resin100,101,102,200Semiconductor deviceF Poor bondingP FulcrumLa, Lb, Lc, Ld, Le, Lf Side in contact with gap between island regions