Interconnect capacitive effects estimation

An non-iterative approach for estimating interconnect capacitive effects. The non-iterative approach includes a method for estimating the interconnect capacitive effects. The method includes modeling the gate and estimating an effective capacitance for the interconnect capacitive effects. The effective capacitance estimation includes modeling the gate load at an output of the gate. The gate load modeling includes approximating an admittance of the gate load to a single capacitance model in addition to approximating the admittance of the gate load to a .PI. model. The gate load modeling also includes matching a gate response for the .PI. model with the gate response for the single capacitance model to determine the effective capacitance. Another aspect of the method for estimating the interconnect capacitive effects includes modeling the gate using an equivalent circuit, and modeling the load at an output of the gate. The gate load modeling includes determining .PI. model parameters that represent the load at the output of the gate. The parameters are associated with a response at the gate output. The effective capacitance estimation method further includes modeling a single capacitive load at the output of the gate. The single capacitive load modeling includes determining a gate delay for a threshold time at a threshold voltage. This delay determination accounts for the input voltage waveform, the voltage response at the gate output and the .PI. model parameters. The single capacitance modeling the capacitive load is determined using the threshold time. The effective capacitance is then derived taking into account the single capacitance, a total capacitance of the gate load, an intrinsic gate delay and a gate load delay for the total capacitance as a load.

FIELD OF THE INVENTION
 This application relates to integrated circuit design automation and,
 specifically, to gate interconnect load estimation.
 BACKGROUND OF THE INVENTION
 Integrated circuit design includes selection and layout of gates also known
 as cells. The interconnections between the multiplicity of gates in an
 integrated circuit form signal paths. In most cases, the interconnections
 between gates form an interconnect tree (as shown in FIG. 1). The
 resistive, capacitive and inductive attributes of interconnect lines form
 gate loads at the respective gate outputs and contribute to signal time
 delays.
 With interconnect delays dominating overall path delays for deep-submicron
 integrated circuits, heuristics for logic synthesis and layout
 optimization need to accurately model interconnect effects. Accurate
 estimations of gate delay and slew time are required for a number of
 signal integrity and reliability checks. In synthesis and floorplanning,
 pre-layout gate delay estimation capability is needed. In post-layout
 timing analysis, existing accurate gate delay estimates are not efficient
 enough to be used in the typical incremental synthesis, layout or in-place
 optimization loop or during performance-driven area routing. In either
 context, accurate estimations of gate delay and slew time at the gate
 output, depend closely on an accurate model for the admittance of an
 interconnect tree load at the gate output. The present invention addresses
 these and related issues.
 SUMMARY OF THE INVENTION
 The present invention provides a new non-iterative approach for estimating
 interconnect capacitive effects. This approach includes determining an
 effective capacitance that represents the interconnect capacitive effects
 at an output of a driving gate (hereafter "gate"). The effective
 capacitance estimation is preceded by a gate modeling.
 The gate is modeled using, for example, a Thevenin equivalent circuit to
 solve a closed-form equation for the voltage response at the gate output.
 A closed-form equation is a single equation requiring only one iteration
 for deriving a solution.
 Effective capacitance determination in accordance with this non-iterative
 approach involves modeling of an interconnect tree load at the gate output
 (i.e., the gate load). The gate load modeling uses an accurate RC .PI.
 model or open-ended (heuristic) RC .PI. model (hereafter collectively
 referred to as the "RC .PI. model"). The use of an open-ended RC .PI.
 model eliminates the need for moment computations at the gate output. The
 use of an accurate RC .PI. model requires a determination of the first
 three moments of the gate load admittance. The gate load modeling uses, in
 addition, a single capacitance model. Then the effective capacitance value
 is closely estimated by matching the RC .PI. model response with that of
 the single capacitance model.
 The non-iterative approach includes a method for estimating the
 interconnect capacitive effects. The method includes modeling the gate and
 estimating an effective capacitance for the interconnect capacitive
 effects. The effective capacitance estimation includes modeling the gate
 load at an output of the gate. The gate load modeling includes
 approximating an admittance of the gate load to a single capacitance model
 in addition to approximating the admittance of the gate load to a .PI.
 model. The gate load modeling also includes matching a gate response for
 the .PI. model with the gate response for the single capacitance model to
 determine the effective capacitance.
 Another aspect of the method for estimating the interconnect capacitive
 effects includes modeling the gate using an equivalent circuit, and
 modeling the load at an output of the gate. The gate load modeling
 includes determining .PI. model parameters that represent the load at the
 output of the gate. The parameters are associated with a response at the
 gate output. The effective capacitance estimation method further includes
 modeling a single capacitive load at the output of the gate. The single
 capacitive load modeling includes determining a gate delay for a threshold
 time at a threshold voltage. This delay determination accounts for the
 input voltage waveform, the voltage response at the gate output and the
 .PI. model parameters. The single capacitance modeling the capacitive load
 is determined using the threshold time. The effective capacitance is then
 derived taking into account the single capacitance, a total capacitance of
 the gate load, an intrinsic gate delay and a gate load delay for the total
 capacitance as a load.
 For logic synthesis and layout optimization, this non-iterative approach
 models interconnect capacitive effects faster and with little or no loss
 of accuracy. Hence, this non-iterative approach is suitable as a step
 within the analysis loop for performance driven iterative layout
 optimization.
 The non-iterative approach can, for example, be suitably implemented in
 timing analysis tools. Such tools are used for analysis and optimization
 of critical paths in integrated circuits design, including microprocessors
 design. Moreover, a computer system can be used in which an embodiment of
 the present invention is implemented
 Advantages of the invention will be set forth, in part, in the description
 that follows and, in part, will be understood by those skilled in the art
 from the description herein. The advantages of the invention will be
 realized and attained by means of the elements and combinations
 particularly pointed out in the appended claims and equivalents.

DETAILED DESCRIPTION OF THE INVENTION
 The present invention provides a new non-iterative approach for estimating
 interconnect capacitive effects on gate output response. This
 non-iterative approach is considerably faster than conventional methods
 for computing effective capacitance, with little or no loss of accuracy.
 Hence, this non-iterative approach is suitable for logic synthesis and
 performance-driven layout optimization analysis. Moreover, this approach
 can be implemented in a computer system as a separate tool or as part of
 other design automation tools.
 The non-iterative approach for estimating interconnect capacitive effects
 includes modeling both the gate and an interconnect tree load (also
 referred to as the "gate load") at the output of the gate. Modeling the
 gate load involves estimating an effective capacitance.
 Modeling the gate load can be done by approximating an admittance of the
 gate load to a single capacitance model, in addition to approximating the
 admittance of the gate load to a .PI. model. After the admittance
 approximations, a gate response for the .PI. model is matched with the
 gate response for the single capacitance model to determine the effective
 capacitance.
 Reference will hereafter be made in detail to embodiments of the invention,
 examples of which are illustrated in the accompanying drawings. Wherever
 convenient, the same reference numbers will be used throughout the
 drawings to refer to the same of like parts. The following discussion
 describes the issues in modeling the interconnect effects and the approach
 of the invention to solving them. The discussion first examines both the
 gate and gate load models. The discussion then describes how, in
 accordance with this invention, the gate and gate load models are used to
 estimate the interconnect capacitive effects.
 I. The Gate Model
 As mentioned, the modeling of interconnect capacitance effects on the gate
 output response includes modeling of the gate itself. The modeling of the
 gate can be accomplished in one of several ways, including: modeling the
 gate as a Thevenin equivalent circuit with an effective linear resistor
 driven by a voltage source; modeling the behavior of the gate using
 relevant parameters such as input slew time(s) and output load
 capacitance; and modeling the nonlinear gate characteristics using
 piece-wise linear device models.
 FIG. 2a illustrates a Thevenin model of the gate. In the Thevenin model,
 the gate 102 is replaced by a voltage source (V.sub.A) 102a in series with
 the gate output impedance (Z) 102b (as seen from the load 104). The
 voltage source 102a represents the open-circuit voltage between the
 terminals (A and ground). In the Thevenin model of the gate, the effective
 gate impedance value is obtained such that the non-linear characteristics
 of the gate are approximated as a piece-wise linear resistor. A resistor
 of fixed value (R) can be used to model the gate by selecting an
 appropriate load capacitance to match, for example, the delay for a 50%
 threshold voltage (V.sub.thd).
 A more accurate model, called the slope model, uses a one-dimensional table
 to determine the effective gate impedance based on the ratio of input slew
 time and output slew time. Alternatively, pre-determined total gate delay
 for various load values is stored in a table format for each gate in a
 cell library.
 FIG. 2b illustrates a total gate delay for a threshold voltage at the gate
 output. The total gate delay D.sub.AB is expressed as the sum of an
 intrinsic gate delay of gate 102 and a gate load delay produced by load
 104. The intrinsic gate delay is a delay attributed to the physical
 devices (e.g., transistors) in the gate. Intrinsic gate delay can be
 thought of as the total gate delay with an infinite load at the output.
 The intrinsic gate delay is known for each gate in the cell library. Data
 such as the cell library and delay tables may be stored in a computer
 readable medium including a computer memory.
 For each gate in the cell library, at least two gate delay tables exist,
 one for delays and one for slew rates. To form the delay tables, delay and
 slew rates may be obtained (e.g., during modeling using a circuit
 simulator) by loading a given gate with a discrete load capacitor and then
 varying the load capacitance and input slew time. The format of delay
 tables is equivalent to the so-called empirical "K-factor" formula for
 delay and output rise time.
 The delay table approach raises some methodology issues. For example, in
 actual layouts the gate output is connected via interconnects to other
 gate inputs. Modeling the load at the gate as a single load capacitor may
 work well for integrated circuit technologies where the area of
 interconnect at the gate output is small or the interconnect parameters
 are not dominant compared to gate parameters. However, with submicron
 technologies the interconnect resistance, capacitance, and inductance need
 to be considered in the delay table determination (the effects of
 inductance are increasingly important as integrated circuits geometry
 becomes smaller).
 II. The Gate Load Model
 As stated above, estimating the interconnect capacitive effects includes
 modeling the gate load in addition to modeling the gate. It may be
 recalled that the gate load is the load at the driving gate output. (The
 driving gate is hereafter referred to as the "gate.") An interconnection
 at a gate output produces the gate load. An interconnection may be an
 interconnect line or an interconnect tree with a number of interconnect
 lines. It is noted that the term "interconnect tree" is used as a
 collective term to describe an interconnect tree with any number of
 branches, i.e., single or multiple interconnect lines.
 Typically, interconnections are metal lines that carry the signals between
 gates in the integrated circuit. Interconnect lines can be analyzed in
 terms of their resistive and capacitive components. More detailed models
 also include inductive components. In the illustrated models, the gate
 load produced by interconnections is a function of the resistive and
 capacitive components of the interconnections.
 With narrower deep-submicron interconnect geometries, the resistive
 component of the gate load is comparable to or larger than the gate output
 resistance. The resistance of interconnect lines "shields" some load
 capacitance in that the load capacitance appears smaller with increases in
 the resistance.
 FIG. 3 illustrates an RC gate load 104 shielding effect at the output of a
 gate 102 in an integrated circuit designed in accordance with an
 embodiment of the invention. The admittance Y(s) of the gate load is
 expressed as an inverse of the impedance Z(s):
EQU Y.sub.L (s)=sC(1+RsC).sup.-1
 where Y(s) decreases in inverse proportion to an increase in R. This
 decrease produces the shielding effect.
 The resistance shielding effect is very significant for deep-submicron
 technologies because it effects the total gate delay. Namely, the total
 gate delay at the gate output decreases as a result of the interconnect
 resistance tending to shield some of the load capacitance. For example,
 the total gate delay at the output decreases when the gate output
 resistance is kept constant and the interconnect resistance of the load is
 increased. However, while the total gate delay decreases, the interconnect
 propagation delay increases as a result of the increase in interconnect
 resistance.
 A primary approach to estimating gate delays is the modeling of admittance
 at the gate output. Gate delays are estimated using these models either
 through a delay table methodology or through an explicit simulation of the
 gate with the given load model.
 In accordance with an embodiment of the invention, modeling the gate load
 can be done by approximating an admittance of the gate load to a single
 capacitance model, in addition to approximating the admittance of the gate
 load to a .PI. model. After the admittance approximations, a gate response
 for the .PI. model is matched with the gate response for the single
 capacitance model to determine the effective capacitance. Accordingly, the
 .PI. models and single capacitance model are described in detail below.
 A. The .PI. Model
 The .PI. model is an equivalent circuit in the form of a single .PI.
 network segment approximating the characteristics of the gate load at the
 respective gate output. The circuit may include resistive and capacitive
 or resistive, capacitive and inductive components. Although an
 interconnect line can be approximated to a distributed network, the
 following exemplary analysis presents a single network segment.
 The .PI. models examined here, include the O'Brien/Savarino (accurate RC)
 .PI. model and the open-ended (heuristic) RC .PI. model. As exemplified,
 the .PI. models include a resistor and two capacitors. The .PI. models can
 also include an inductor. However, to simplify this discussion the
 inductor is omitted.
 In the O'Brien/Savarino (accurate RC) .PI. model, the interconnect load
 tree is approximated by an RC .PI. model with a resistance and capacitance
 equaling the total interconnect resistance (R.sub.tot) and capacitance
 (C.sub.tot), respectively. For deep-submicron technologies, the total
 interconnect resistance is large and comparable to the gate output
 resistance. Thus, the actual delay is much smaller than the delay derived
 from an alternative total capacitance model because the interconnect
 resistance shields the load capacitance seen by the gate. With this
 approximation, the total interconnect load tree resistance shields the
 total capacitance.
 FIG. 4 illustrates the O'Brien/Savarino .PI. model. The O'Brien/Savarino
 .PI. model approximates the interconnect load at the gate output by
 matching the first three moments of the interconnect load admittance at
 the gate output (i.e., as seen from the gate output).
 In accordance with O'Brien/Savarino .PI. model, the admittance, Y.sub.L, of
 the interconnect tree load 104 at the gate output (B) is represented by:
EQU Y.sub.L (s)=.SIGMA..sub.i=1.sup..infin. A.sub.i s.sup.i =sA.sub.1 +s.sup.2
 A.sub.2 +s.sup.3 A.sub.3 +
 The parameters of the equivalent circuit are obtained by matching the first
 three moments of the admittance with corresponding moments of the
 interconnect tree load admittance of the .PI. load model in FIG. 4. That
 is:
 ##EQU1##
 In accordance with the O'Brien/Savarino .PI. model, the delay tables need
 to be expanded from two-dimensional to space consuming four-dimensional
 tables. One dimension is the slew time of the input voltage. The other
 three dimensions are the three .PI. model parameters R.sub.1, C.sub.1,
 C.sub.2 104a, 104b and 104c, respectively.
 A second .PI. model approach, the open-ended RC .PI. model, offers an
 alternative to the O'Brien/Savarino .PI. model for estimating the
 interconnect tree load admittance. The open-ended H model provides a
 linear-time estimation.
 FIGS. 5a an 5b illustrate the open-ended model of an interconnect tree load
 104 at a gate 102 output. The open-ended RC .PI. model approximates the
 entire interconnect tree 104 by an equivalent open-ended RC line whose
 resistance (R.sub.tot) and capacitance (C.sub.tot) 104d are equal to the
 total interconnect resistance and capacitance, as shown in FIG. 5(a). By
 using an open-ended RC line to approximate the entire tree, the
 distributed nature of the interconnect tree load is still considered in
 determining the model parameters. That is, the resistance of the
 open-ended RC line shields part of the load capacitance from the gate.
 The one-segment RC .PI. model is open-ended in the sense that parameter
 values can be set to any value not exceeding the range determined by the
 total resistance (R.sub.tot) and capacitance (C.sub.tot) 104. In other
 words, the open-ended RC .PI. model is a one-segment RC .PI. model with
 predetermined parameter values that depend only on the total resistance
 (R.sub.tot) and capacitance (C.sub.tot) 104.
 In accordance with this modeling approach, as illustrated in FIG. 5b, the
 admittance Y(s) of an open-ended RC line is approximated to:
 ##EQU2##
 where the propagation constant .theta.=R.sub.tot +L sC.sub.tot +L and the
 characteristic impedance
 ##EQU3##
 Therefore, the first three moments of the gate load admittance
 approximating the open-ended RC line are
 ##EQU4##
 Using these values for A.sub.1, A.sub.2 and A.sub.3, in equation (1) above
 yields .PI. model parameters as shown in FIG. 5(b):
 ##EQU5##
 The open-ended .PI. model can be extended to RLC networks as shown in FIGS.
 6a and 6b. Using this modeling approach to obtain the moments of the gate
 load admittance increases modeling efficiency because it avoids recursive
 interconnect tree traversal. Still, if the designer must account for all
 the possible combinations of C.sub.1, C.sub.2, R.sub.1 in the .PI. model,
 a very large look-up table or highly complex K-factor formulas (along with
 a complex, resource consuming modeling process) would be required.
 It may be recalled that estimating the interconnect capacitive effects can
 be done by approximating an admittance of the gate load to a single
 capacitance model, in addition to approximating the admittance of the gate
 load to a .PI. model. After the admittance approximations, a gate response
 for the .PI. model is matched with the gate response for the single
 capacitance model to determine the effective capacitance that represents
 the interconnect capacitive effects. Having first considered the .PI.
 model, attention is now turned to approximating the admittance of the gate
 load to the single capacitance model.
 B. The Single Capacitance Model
 The gate load can be modeled using a delay table lookup approach with a
 single load capacitance to approximates the gate load. FIGS. 7a and 7b
 illustrate a single capacitance model of the load. Specifically, in
 response to the gate 102 input being excited with, for example, a step or
 ramp voltage waveform (V.sub.in (t)), the voltage waveform (V.sub.s (t))
 at the gate output rises (or falls) to a particular level within the
 output voltage range. The time-domain response v.sub.out (t) at the gate
 output can be obtained as a function of the single capacitance, C, 104e.
 As the output voltage changes, it passes through voltage threshold points,
 one being the t=t.sub.0 (or 0%) point 190 and the other being the
 t=t.sub.thd (or 50% or 75%, etc. ) point 192. It is for these endpoints
 that the capacitance, C, 104e is determined.
 It is noted that the term "single capacitance model" means a model using a
 single capacitor to represent one capacitor or multiple capacitors
 arranged in series or parallel. In the case of the multiple capacitors in
 series or in parallel, the single capacitor is an equivalent of the
 multiple capacitors as is readily known.
 III. The Effective Capacitance Estimation
 As part of the interconnect capacitive effects estimation a non-iterative
 effective capacitance estimation technique is provided by the present
 invention. This approach is very useful with respect to each gate for
 providing an accurate estimation of gate load delays. This approach is
 less useful for accurate estimation with respect to downstream gates.
 As stated before, the gate model and the gate load models (the .PI. model
 and the single capacitance model) are used in the interconnect capacitive
 effects estimation. Namely, once the gate and gate load modeling is done,
 the interconnect capacitive effects can be approximated to an effective
 capacitance. The effective capacitance can be determined from the gate and
 gate load models as hereafter described.
 More particularly, in accordance with an embodiment of the invention,
 modeling of the interconnect tree load at the gate output (i.e., the gate
 load) uses the accurate RC .PI. model or open-ended (heuristic) RC .PI.
 model (hereafter collectively referred to as the "RC .PI. model"). The use
 of an open-ended RC .PI. model eliminates the need for moment computations
 at the gate output. The use of an accurate RC .PI. model requires a
 determination of the first three moments of the gate load admittance.
 Additionally, the gate is modeled using, for example, a Thevenin
 equivalent circuit to determine the voltage response at the gate output
 using the closed-form equation. As noted before, the closed-form equation
 is a single equation requiring only one iteration to derive a solution.
 The effective capacitance value is closely estimated by matching the RC
 .PI. model response with that of the single capacitance model. A more
 detailed explanation of the non-iterative approach to estimating effective
 capacitance is now provided.
 FIGS. 8( a)-8(e) illustrate the effective capacitance estimation in
 accordance with the non-iterative approach. In one embodiment, the
 effective capacitance estimation is performed using as an input a step
 voltage waveform, as shown in FIG. 8a. In a second embodiment, the
 effective capacitance estimation is performed using a ramp voltage
 waveform at the gate input, as is further shown in FIG. 8a.
 As shown in FIGS. 8b and 8c, the Thevenin equivalent circuit models the
 gate 102 by replacing it with a voltage source (v.sub.s (t)) 102a and a
 linear source resistance (R.sub.s) 102b. As indicated, in one embodiment
 the voltage source 102a provides a step voltage waveform. In the the
 second embodiment the voltage source 102a provides a ramp voltage
 waveform.
 Initially, as shown in FIG. 8b, the interconnect tree load (the gate load)
 104 at the gate output is modeled using an open-ended (heuristic) RC .PI.
 model. This RC .PI. model is used for determining the gate load
 admittance. The open-ended RC .PI. model includes a resistor (R.sub.1)
 104a and two capacitors (C.sub.1 and C.sub.2) 104b and 104c. An inductor
 (L) can be included as well to form an RLC .PI. model. However, for a
 simpler analysis the inductor is omitted. The open-ended RC .PI. model
 components, R.sub.1, C.sub.1 and C.sub.2, are expressed as a function of
 the total interconnect capacitance (C.sub.tot) and resistance (R.sub.tot)
 The components R.sub.1, C.sub.1, and C.sub.2, are determined n accordance
 with the relationships as indicated in equation (2).
 Instead of the open-ended RC .PI. model as shown in FIG. 8b, the gate load
 modeling can use an accurate RC .PI. model as shown in FIG. 8c. In this
 instance, the accurate RC .PI. model components, R.sub.1, C.sub.1 and
 C.sub.2, are determined by the relationships as indicated in equation (1).
 As a next step in estimating the interconnect capacitive effects, the gate
 load 104 is modeled using the single capacitance model, as shown in FIG.
 8d. As previously explained, the value of the effective capacitance,
 C.sub.eff, 104' (FIG. 8e) is closely estimated by matching the RC .PI.
 model response (FIGS. 8b or 8c) with that of the single capacitance model
 (FIG. 8d).
 A. Effective Capacitance Estimation With Step Input
 Starting with the step voltage waveform as an input (V.sub.in) to the gate
 102 (FIG. 8a). The gate output response (V.sub.B (s)) produced thereby is
 analytically computed using the source resistance R.sub.S and the load
 which is modeled as the RC .PI. model as previously described.
 Under these conditions, the response at the gate output (B) in the Laplace
 transform domain is given by the following transfer function:
 ##EQU6##
 where
 ##EQU7##
 where R.sub.1 104a, C.sub.1, 104b and C.sub.2 104c, are the components of
 the .PI. model, and V.sub.0 is the output voltage that approximates the
 maximum V.sub.S.
 Depending on the sign of b.sub.1.sup.2 -4b.sub.2, the poles of the transfer
 function can be either real or complex. V.sub.B (t) is the reverse Laplace
 transform of the transfer function expressing the time domain gate output
 response. The time domain response, V.sub.B (t), is determined separately
 for each case, real and complex. Substituting the moments, b.sub.1 and
 b.sub.2, for the parameters in the above equation, produces:
EQU b.sub.1.sup.2 -4b.sub.2 =R.sub.S.sup.2 (C.sub.1 +C.sub.2).sup.2
 +R.sub.1.sup.2 C.sub.2.sup.2 +2R.sub.S R.sub.1 C.sub.2 (C.sub.2 -C.sub.1)
 (4)
 For the most part, especially in the case of open-ended RC .PI. models, the
 value of C.sub.2 104b is greater than C.sub.1 104b. Hence, the time domain
 response, V.sub.B (t), with a load at gate output (B) being represented by
 an RC .PI. model, is determined for real poles as follows:
 ##EQU8##
 This response is then used to determine the slew time (or delay with
 respect to input signal) at a specified threshold voltage by matching the
 results for a single capacitor as a gate load. Assuming that (in the step
 voltage waveform input case) the load is modeled as a single, step input
 capacitance, C.sub.step. In other words:
EQU V.sub.B (t)=V.sub.s (1-e.sup.-t/RsCstep)
 where V.sub.s approximates 100% of the gate output voltage represented by
 the voltage source 102a. C.sub.step, the step input capacitance 104e, is
 the capacitor component of a single capacitance model that is excited by a
 step input waveform (FIG. 8d). It may be recalled that as the V.sub.B (t)
 changes it passes through threshold points t=t.sub.0 and t=t.sub.thd set
 for determining the gate response delay (slew rate). Hence, also assuming,
 for V.sub.B (t), a threshold voltage, V.sub.thd, that is greater than 0%
 and lower than 100% (e.g., 50%, 90% etc.). Then:
EQU V.sub.B (t).sub.thd =V.sub.thd,
 and:
 ##EQU9##
 where k.sub.1 is a constant associated with the particular threshold
 voltage, V.sub.thd, so that:
 ##EQU10##
 where T.sub.out.sup..PI. is the slew time for a .PI. model at the gate
 output for the particular V.sub.thd.
 Finally, the effective capacitance is determined in the range between the
 step input capacitance C.sub.step and the total load capacitance C.sub.tot
 under full load conditions. It may be recalled, that under no load
 condition the gate response is fast since the gate will not see the
 interconnect load capacitance. Under full load conditions the gate
 response is slow because it needs to charge a full capacitive load. The
 range between C.sub.step and C.sub.tot is set by obtaining the intrinsic
 gate delay D.sub.NL and the gate load delay D.sub.LD. The intrinsic gate
 delay, D.sub.NL, is a gate response delay with no load at the gate output,
 and the gate load delay, D.sub.LD, is a gate response delay with C.sub.tot
 as a load. Intrinsic and gate load delays for specific loads are
 predetermined and can be obtained from K-factor formulas or look-up tables
 available for each gate in the cell library. Accordingly, C.sub.eff can be
 expressed as follows:
 ##EQU11##
 This implies that
 C.sub.eff.apprxeq.C.sub.step if D.sub.LD /D.sub.NL &gt;&gt;1,
 and
EQU C.sub.eff.apprxeq.C.sub.tot if D.sub.LD /D.sub.NL &lt;&lt;1.
 Given the .PI. model parameters (R.sub.1,C.sub.1,C.sub.2) and the
 predetermined output delay table for the gate, the above-described
 embodiment provides a non-iterative method for estimating the effective
 capacitance. The method for estimating the effective capacitance of an
 interconnect load when the gate is excited with a step voltage waveform
 includes steps as hereafter outlined. First, determine .PI. model
 parameters in accordance with the relationship as expressed in either
 equation (1) or equation (2). Second, determine the threshold time,
 t.sub.thd, using a transfer function as demonstrated by equation (5) for
 the voltage response at the gate output. Third, determine the single
 capacitor, C.sub.step, from t.sub.thd and R.sub.S using the relationship
 of equation (6). Fourth, obtain from the gate delay table the gate load
 delay D.sub.LD for the total capacitance, C.sub.tot, as a load and the
 intrinsic gate delay D.sub.NL for the no load condition. Fifth, determine
 C.sub.eff using the relationship expressed in equation (7).
 B. Effective Capacitance Estimation With Ramp Input
 For a ramp voltage waveform as an input to the gate, the following
 effective capacitance estimation process is presented. In this case, the
 gate is modeled with a Thevenin equivalent circuit that replaces the gate
 with a ramp voltage source V.sub.S and a series source resistance R.sub.S.
 The ramp voltage is characterized by rise time T.sub.R. To approximate the
 entire interconnect load tree at the gate output, the RC .PI. model is
 used (as before). The voltage V.sub.B at the gate output (B) in the
 Laplace transform domain is:
 ##EQU12##
 where:
 b.sub.1 =R.sub.S (C.sub.1 +C.sub.2)+R.sub.1 C.sub.2,
 b.sub.2 =R.sub.S R.sub.1 C.sub.1 C.sub.2, and:
 ##EQU13##
 The time-domain response is:
 ##EQU14##
 for t.ltoreq.T.sub.R, and:
 ##EQU15##
 for t&gt;T.sub.R.
 Depending on the sign of b.sub.1.sup.2 -4b.sub.2, the poles will be either
 real or complex. As before (equation (4)), the quantity b.sub.1.sup.2
 -4b.sub.2 is positive. Accordingly, the case of real poles is analyzed
 here.
 From the output response, V.sub.B (t), the threshold time, t.sub.thd, is
 determined for a user-specified threshold voltage (e.g. 50%, 90% etc.).
 The ramp input capacitance, C.sub.ramp, 104e is the capacitive component
 of the single capacitance model, excited by a ramp voltage waveform, as
 shown in FIG. 8d. The ramp input capacitance, C.sub.ramp, is then
 determined for the given threshold time, t.sub.thd (T.sub.out.sup..PI. for
 .PI. model) as follow:
 ##EQU16##
 where the constant k.sub.2 is an absolute value expressed as:
 ##EQU17##
 and:
 ##EQU18##
 Finally, the effective capacitance, C.sub.eff, is determined in the range
 between the ramp input capacitance C.sub.ramp and total load capacitance
 C.sub.tot, as in the previous case. The intrinsic gate load, D.sub.NL, and
 the gate load, D.sub.LD, with C.sub.tot as the load, are then obtained
 from the k-factor formulas or delay tables for the gate. From the above,
 the the effective capacitance, C.sub.eff, is determined as follows:
 ##EQU19##
 This again implies that:
EQU C.sub.eff.apprxeq.C.sub.step if D.sub.LD /D.sub.NL &gt;&gt;1,
 and
EQU C.sub.eff.apprxeq.C.sub.tot if D.sub.LD /D.sub.NL &lt;&lt;1.
 Given the .PI. model parameters (R.sub.1,C.sub.1,C.sub.2) and the
 predetermined output delay table for the gate, this embodiment provides a
 non-iterative method for estimating the effective capacitance. The
 following method for estimating the effective capacitance of an
 interconnect load is suitable when the gate is excited with a ramp voltage
 waveform. First, determine .PI. model parameters using the relationships
 expressed in either equation (1) or equation (2). Second, determine the
 threshold time, t.sub.thd, by determining the voltage response at the gate
 output based on a transfer function as expressed in equation (8). Third,
 determine the single capacitance, the ramp input capacitance C.sub.ramp,
 from t.sub.thd and R.sub.S in accordance with the relationships as
 expressed in equations (9) and (10). Fourth, obtain from the gate delay
 table the gate load delay D.sub.LD for C.sub.tot as a load and the
 intrinsic gate delay D.sub.NL for the no load condition. Fifth, determine
 C.sub.eff using the relationship expressed in equation (11).
 In summary, the present invention provides a new non-iterative approach for
 estimating the interconnect capacitive effects on the gate output
 response. This approach includes estimating the effective capacitance of
 an interconnect load at the gate output. For logic synthesis and layout
 optimization, this approach models interconnect effects more accurately.
 This non-iterative approach is considerably faster than conventional
 methods for computing effective capacitance, with little or no loss of
 accuracy. This approach for estimating effective capacitance works
 especially well for threshold voltages between 30% to 60%.
 Accordingly this non-iterative approach is advantageous in providing
 accurate delay analysis within a tight synthesis-analysis loop. For
 instance, in performance-driven layout optimization, this non-iterative
 approach is suitable as a step within the analysis loop.
 Other embodiments will be apparent to those skilled in the art from
 consideration of the specification and practice of the invention disclosed
 herein. It is intended that the specification and examples be considered
 as exemplary only, with a true scope of the invention being indicated by
 the following claims and equivalents.