Light-emitting element and method of manufacturing same

A method of manufacturing a light-emitting element includes: forming a plurality of masks on a surface of a first conductive semiconductor layer; forming a plurality of rods comprising a first conductive semiconductor by partially removing, in a depth direction, a portion of the first conductive semiconductor layer exposed from the masks by etching; forming an insulating film on the rods and a surface of a the remaining first conductive semiconductor layer; performing wet etching, in a state in which a mask covering the insulating film is not formed, to remove a first portion of the insulating film on lateral surfaces of the rods but retaining a second portion of the insulating film on a surface of the first conductive semiconductor layer; forming a plurality of light-emitting layers covering the lateral surfaces of the rods; and forming a plurality of second conductive semiconductor layers covering outer peripheries of the light-emitting layers.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U. S. C. § 119 to Japanese Patent Application No. 2018-244450, filed Dec. 27, 2018, the contents of which are hereby incorporated by reference in their entirety.

BACKGROUND

The present disclosure relates to a light-emitting element and a method of manufacturing the light-emitting element.

Background art of the present technical field includes Japanese Patent Publication No. 2015-126048. Japanese Patent Publication No. 2015-126048 (“JP '048”) discloses a method of manufacturing a rod-type light-emitting element as shown in FIG. 7 thereof. An n-type GaN layer 72 is formed on a principal surface of a sapphire substrate 70, and a mask 74 is formed on the n-type GaN layer 72. Subsequently, a plurality of rod-shaped (rod-type) n-type GaN members 72A are formed by etching. A plurality of rod-type light-emitting elements can be created by using the rod-shaped n-type GaN members 72A as a semiconductor core 12 to form a light-emitting layer 14 and a p-type semiconductor layer 16 on a lateral surface thereof and further forming a transparent conductive film 30 (refer to paragraphs [0057] to in JP '048).

SUMMARY

In JP '048, the plurality of formed rod-type light-emitting elements are ultimately separated from the sapphire substrate 70 (refer to FIG. 7H of JP '048). However, minute rod-type light-emitting elements separated from a substrate in this manner are difficult to handle. On the other hand, leaving the plurality of rod-type light-emitting elements formed by the method described in JP '048 on the substrate instead of separating the plurality of rod-type light-emitting elements from the substrate (refer to FIG. 7G of JP '048) reduces the difficulty of handling. However, in this case, the transparent conductive film 30 forming a p-electrode is directly formed on a surface of the substrate 70. In addition, the substrate 70 is a sapphire substrate with an insulating property, and the semiconductor cores 12 that are n-type semiconductors of the light-emitting elements are not electrically connected to each other. Such a configuration requires that, in order to energize the semiconductor cores 12, n-electrodes be formed with high accuracy so as to prevent the n-electrodes from coming into contact with the transparent conductive film 30 forming a p-electrode.

The present disclosure provides a light-emitting element having a plurality of rod-type light-emitting sections and a method of readily manufacturing such a light-emitting element.

According to one embodiment, a method of manufacturing a light-emitting element includes: forming a plurality of masks in forms of islands on a surface of a first conductive semiconductor layer; forming a plurality of rods of a first conductive semiconductor by partially removing, in a depth direction, the first conductive semiconductor layer in a portion exposed from the masks by etching; forming an insulating film on the rods and a surface of the remaining first conductive semiconductor layer; performing wet etching, in a state in which a mask covering the insulating film is not formed, to remove a first portion of the insulating film on lateral surfaces of the rods but retaining a second portion of the insulating film on a surface of the first conductive semiconductor layer; forming a plurality of light-emitting layers covering the lateral surfaces of the rods; and forming a plurality of second conductive semiconductor layers covering outer peripheries of the light-emitting layers.

According to another embodiment, a light-emitting element includes: a first conductive semiconductor layer; a plurality of rods of a first conductive semiconductor disposed on the first conductive semiconductor layer; a first insulating film disposed on a surface of the first conductive semiconductor layer while being absent under the rods; a plurality of light-emitting layers disposed on lateral surfaces of the rods; a plurality of second conductive semiconductor layers disposed on outer sides of the light-emitting layers; and a plurality of second insulating films disposed at upper ends of the rods.

According to certain embodiments of the present disclosure, a light-emitting element having a plurality of rod-type light-emitting sections can be obtained and such a light-emitting element can be readily manufactured.

DETAILED DESCRIPTION

First Embodiment

FIG. 1is a flow chart schematically showing a method of manufacturing a light-emitting element according to a first embodiment of the present invention. The manufacturing method according to the first embodiment includes: a step S102of forming an n-type semiconductor layer; a step S104of forming masks in forms of islands; a step S106of forming rods; a step S108of forming an insulating film; an etching step S110; a step S112of forming a light-emitting layer; and a step S114of forming a p-type semiconductor layer. It should be noted that, in the present embodiment, an “n-type” will be referred to as a “first conductive type” and a “p-type” will be referred to as a “second conductive type”.

FIG. 2is a sectional view schematically showing a state in which masks in forms of islands are formed on a surface of an n-type semiconductor layer in the first embodiment. In order to form a structure shown inFIG. 2, first, in step S102, with one principal surface102aof a substrate102as a growth surface, a buffer layer104is formed on the principal surface102aand, subsequently, an n-type semiconductor layer106is formed on the buffer layer104. As the substrate102, for example, a sapphire (Al2O3) substrate, a SiC substrate, or a nitride semiconductor substrate can be used. As the buffer layer104, for example, nitride semiconductors such as GaN and AlN can be used. As the n-type semiconductor layer106, for example, nitride semiconductors such as n-type GaN-based semiconductors can be used. In the present embodiment, an example will be described in which a sapphire substrate is used as the substrate102, a GaN layer is used as the buffer layer104, and an n-type GaN layer is used as the n-type semiconductor layer106. As a reaction apparatus for forming the buffer layer104and the n-type semiconductor layer106, for example, a MOCVD apparatus can be used. The buffer layer104may be omitted. It should be noted thatFIG. 2is a schematic view, and a magnitude relationship among thicknesses of the respective parts is not necessarily consistent with an actual magnitude relationship. For example, the substrate102is around several hundreds of μm, the buffer layer104is around several tens of nm, and the n-type semiconductor layer106ranges from several hundreds of nm to several μm.

A crystal plane of the sapphire substrate with Miller indices of (0001) is preferably used as the principal surface102athat is the growth surface. A “(0001) plane” as referred to herein also includes planes that are slightly inclined with respect to the (0001) plane. Specifically, more preferably, a plane with an off angle of 2.0 degrees or less with respect to the (0001) plane is adopted as the growth surface. For example, an upper surface of a nitride semiconductor (an upper surface of the n-type semiconductor layer106) formed on the (0001) plane of the substrate102is assumed to be (0001).

For example, the buffer layer104made of GaN can be formed on the substrate102by setting a temperature of the substrate to be in a range of 102° C. to 550° C. and supplying raw material gas. In this case, trimethyl gallium (TMG) or triethyl gallium (TEG) can be used as a raw material gas of gallium and NH3can be used as a raw material gas of nitrogen. The thickness of the buffer layer104is set to, for example, approximately 20 nm. Amorphous GaN may be formed as the buffer layer104and a heat treatment may be subsequently performed.

An n-type GaN layer is formed as the n-type semiconductor layer106on the buffer layer104. As the n-type GaN layer, for example, a Si-added GaN layer can be formed. A Si-added GaN layer can be formed by adding silane gas to the raw material gas described above.

Next, in step S104of forming masks in forms of islands, a plurality of masks108are formed on a surface of the n-type semiconductor layer106. For the masks108, a material with an etching rate with respect to etching to be performed in step S106of forming rods (to be described later) that is lower than that of the n-type semiconductor layer106can be used. Examples of materials that can be used in the masks108include SiO2and SiN. For example, after forming a SiO2film on an entire surface of the n-type semiconductor layer106, the masks108can be formed using a lithographic technique such as nanoimprint lithography, photolithography, or electron beam lithography and by etching. Examples of methods for forming the SiO2layer include a CVD method. A pattern of the masks108may have various shapes such as a circular shape and a polygonal shape. A circular shape is suitable as a fine pattern.FIG. 2schematically shows a state in which the buffer layer104and the n-type semiconductor layer106have been sequentially stacked on the substrate102and the masks108have been formed.

FIG. 3is a sectional view schematically showing a state in which rods are formed by etching the n-type semiconductor layer shown inFIG. 2. In step S106of forming rods, the n-type semiconductor layer106in a portion exposed from the masks108is partially removed in a depth direction by dry etching and a plurality of rods106aof an n-type semiconductor are formed as shown inFIG. 3. As an etching gas, for example a mixed gas of Cl2gas and SiCl4gas can be used. In the present step, because the n-type semiconductor layer106is partially removed in the depth direction, the n-type semiconductor layer106still remains under the plurality of formed rods106a. Therefore, because the plurality of rods106aare electrically connected through the n-type semiconductor layer106that is present under the rods106a, energization can be readily performed. In other words, by energizing the n-type semiconductor layer106, all of the plurality of rods106acan be energized. For this reason, there is no need to form an n-electrode on each of the rods106a, and forming only one n-electrode that is electrically connected to the n-type semiconductor layer106may suffice. It should be noted that there may not be only one n-electrode. For example, a plurality of n-electrodes that are fewer than the rods106amay be provided. In addition, not all rods106aneed be simultaneously driven. For example, even when there is only one n-electrode, providing a plurality of mutually independent p-electrodes enables rods106awith different p-electrodes to be individually driven.

A GaN-based crystal has a wurtzite (hexagonal system) crystal structure. When the rod106ais formed by etching the n-type semiconductor layer106of which an upper surface is (0001) plane in a depth direction (a [000-1] direction of the crystal), the rod106afirst assumes a shape corresponding to a shape of the mask108. Subsequently, when the light-emitting layer (to be described later) and the like are grown, an outer shape of the light-emitting layer and the like may assume a hexagonal column shape. At this point, a lateral surface of the hexagonal column-shaped rod-like stack becomes an m-surface of a GaN-based crystal. When a diameter of the mask108is large, a thickness of the rod106aincreases accordingly. Therefore, the thickness of the rod106acan be controlled by the diameter of the mask108.

As a method of forming a semiconductor rod, for example, a mask of an insulating film having a plurality of through-holes can be formed on the upper surface of the n-type semiconductor layer106, and the semiconductor rod can be formed by selectively growing from the upper surface of the n-type semiconductor layer106that is exposed from the through-holes in a direction perpendicular to the upper surface of the n-type semiconductor layer106. Compared to such a selective growth method, a method of forming a rod by etching as in the present embodiment is advantageous in that a variation in lateral sizes (diameters or the like) of the rods can be reduced, a variation in heights of the rod portions can be reduced, and the like. The closer the heights of the rods are to being uniform, the smaller a vertical difference among the rods, which enables more advantages to be gained, such as making p-electrodes and the like more readily formable and making junction-down mounting more readily achievable.

FIG. 4is a sectional view schematically showing a state in which an insulating film is formed on surfaces of the rods and the like shown inFIG. 3. In step S108of forming an insulating film112, the insulating film112is formed on surfaces of the rods106aand the remaining n-type semiconductor layer106. While SiO2, SiN, and the like can be exemplified as the insulating film112, in the present embodiment, an example using SiO2will be described. The insulating film112is preferably formed by a sputtering method. Forming the insulating film112by a sputtering method causes an etching rate of the insulating film112formed on lateral surfaces of the rods106ain a next etching step to be higher than an etching rate of the insulating film112formed in other portions. This is conceivably due to density of the insulating film112formed on the lateral surfaces of the rods106abeing lower than that of the insulating film112formed in other portions. Because the formation of such films in which density differs according to a formation position is conceivably dependent on anisotropy of sputter, for example, the difference in density can conceivably be made more apparent by increasing a distance between a target and a sample, increasing a degree of vacuum, or the like. It should be noted that the rods106aare preferably subjected to wet etching prior to forming the insulating film112. Accordingly, portions damaged by dry etching can be removed and, at the same time, lateral surfaces of the rods106acan be brought closer to vertical with respect to the principal surface of the substrate102.

FIG. 5is a sectional view schematically showing a state in which the insulating film on the lateral surfaces of rods have been removed by etching. In etching step S110, wet etching is performed in a state in which a mask covering the insulating film112is not formed. Accordingly, the insulating film112on the lateral surfaces of the rods106acan be removed but the insulating film112on the surface of the n-type semiconductor layer106can be retained. When the insulating film112is SiO2, buffered hydrofluoric acid (BHF) can be used as an etching solution.

As described above, the insulating film112formed on the lateral surfaces of the rods106ahas a higher etching rate than the insulating film112formed in other portions. Therefore, when wet etching is performed without forming a mask for covering the insulating film112, the insulating film112formed on the lateral surfaces of the rods106ais completely removed before the insulating film112formed in other portions. Etching time is controlled so as to stop etching in a state in which the insulating film112of the lateral surfaces of the rods106ais removed and the lateral surfaces of the rods106aare exposed but the insulating film112on the surface of the n-type semiconductor layer106still remains. Accordingly, a state in which the insulating film112is present on the surface of the n-type semiconductor layer106but the insulating film112is absent from the lateral surfaces of the rods106acan be created.FIG. 5schematically shows a state in which such etching has been completed. As shown inFIG. 5, for the sake of brevity, the insulating film112remaining on the surface of the n-type semiconductor layer106will be referred to as a first insulating film112a, and the insulating film112remaining on upper ends of the rods106awill be referred to as a second insulating film112b. In this manner, the second insulating film112bmay be retained on the upper ends of the rods106a.

FIG. 6is a sectional view schematically showing a state in which a light-emitting layer and a second conductive semiconductor layer are formed on lateral surfaces of rods. In step S112of forming a light-emitting layer, a light-emitting layer114covering the lateral surfaces of the rods106ais formed. An n-type semiconductor layer is preferably formed on the lateral surfaces of the rods106aprior to forming the light-emitting layer114. Although regrowth is to be performed on the surface of the rods106awhen forming the rods106aby etching, growing an undoped layer on the surface of the n-type rods106amay cause a voltage rise depending on an impurity level on a regrowth interface. Therefore, preferably, as shown inFIG. 14, an n-type semiconductor layer106bis first formed on a surface of the n-type rods106aand, subsequently, the light-emitting layer114is grown. Accordingly, a voltage rise can be suppressed. The light-emitting layer114may have a multi-quantum well (MQW) structure. For example, the light-emitting layer114may be constructed by alternately stacking a GaN barrier layer and an InGaN well layer a plurality of times. By adjusting formation conditions of the light-emitting layer114, the light-emitting layer114that emits light of various wavelengths can be formed. For example, the light-emitting layer114that emits blue light can be formed by setting the temperature of the substrate102to around 800° C. to 900° C. and supplying raw material gas. As raw materials, for example, TMG or TEG can be used as a gallium source, NH3can be used as a nitrogen source, and trimethyl indium (TMI) can be used as an indium source.

In next step S114of forming a p-type semiconductor layer, a p-type semiconductor layer116is formed so as to cover an outer periphery of the light-emitting layer114. The p-type semiconductor layer116may be a p-type GaN-based semiconductor. The p-type semiconductor layer116may be formed by stacking a p-type GaN layer or a p-type AlGaN layer a plurality of times while varying a p-type impurity concentration thereof. For example, the p-type semiconductor layer116can be formed by setting the temperature of the substrate102to be in a range of about 800° C. to 900° C. and supplying raw material. TMG or TEG can be used as a raw material to be a gallium source and NH3can be used as a raw material to be a nitrogen source. When adding Mg as a p-type impurity, for example, Cp2Mg (bis(cyclopentadienyl) magnesium) can be used as a raw material.FIG. 6shows a state in which the light-emitting layer114and the p-type semiconductor layer116have been formed on lateral surfaces of the rods106a. It should be noted that further layers other than those described above may be provided. For example, an undoped layer may be provided between the light-emitting layer114and the p-type semiconductor layer116.

As shown inFIG. 6, by forming the p-type semiconductor layer116, a rod-like stack110including the rod106a, the light-emitting layer114, and the p-type semiconductor layer116is completed. The rod-like stack110constitutes a light-emitting section of the light-emitting element according to the present embodiment. When growing the light-emitting layer114and the p-type semiconductor layer116on the lateral surface of the rods106a, an interval between rods106athat are adjacent to each other may affect a growth rate and a composition of the light-emitting layer114and the p-type semiconductor layer116. The “interval between rods106a” as referred to herein may be paraphrased as an interval between centers of masks108when the masks108shown inFIG. 2are viewed from above. This is because a position of the rod106ato be formed is determined by a position of the center of the mask108. It should be noted that an “interval between rod-like stacks110” refers to the same interval. Arranging the plurality of rods106aat substantially constant intervals enables growth rates of the light-emitting layer114and the p-type semiconductor layer116formed on the lateral surfaces of the rods106ato be made substantially constant. When sizes of the plurality of masks108are not constant, the “interval between rods106a” will refer to a shortest distance between the masks108.

For example, in a top view of the masks108formed in step S104, by arranging the masks108in forms of islands in an equilateral-triangular lattice, the intervals of the rods106aformed in step S106can be made substantially constant. Furthermore, preferably, a direction connecting the centers of the masks108in a top view is an m-axis direction of a GaN-based crystal constituting the rods106aor, in other words, an a-axis direction of sapphire constituting the substrate102. Accordingly, in hexagonal rods106aarranged in an equilateral-triangular lattice, lateral surfaces of adjacent rods106acan substantially each other so as to be substantially parallel. In this case, growth rates of the light-emitting layer114and the p-type semiconductor layer116formed on each lateral surface of each rod106acan be made substantially constant and film thicknesses of the light-emitting layer114and the p-type semiconductor layer116formed on each rod106aare allowed to have uniform film thicknesses.

As shown inFIG. 6, according to the first embodiment described above, a light-emitting element is formed that includes: an n-type semiconductor layer106; a plurality of rods106aof an n-type semiconductor formed on the n-type semiconductor layer106; a first insulating film112athat is formed on a surface of the n-type semiconductor layer106while being absent under the rods106a; a light-emitting layer114stacked on lateral surface of the rods106a; a p-type semiconductor layer116stacked on an outer side of the light-emitting layer114; and a second insulating film112bformed at upper ends of the rods106a.

The first insulating film112aformed on the surface of the n-type semiconductor layer106is capable of preventing leakage due to the p-type semiconductor layer116and the n-type semiconductor layer106coming into contact with each other. As is conventional, providing a mask so that the insulating film112is not formed on the lateral surfaces of the rods106aand attempting to form the insulating film112only on the surface of the n-type semiconductor layer106necessitates adding many steps to a manufacturing process. In particular, when the sizes of the rods106aare small or the intervals between adjacent rods106aare narrow, requirements for mask precision is extremely high. A photolithographic process of forming such a resist mask requires complicated steps such as positioning a photomask with high precision requirement, which in turn prolongs manufacturing cycles and raises manufacturing cost. In the present embodiment, in step S108, by simply forming the insulating film112on entire surfaces of the rods106aand the n-type semiconductor layer106and performing wet etching without forming a mask, the insulating film112on the lateral surfaces of the rods106acan be removed while retaining the first insulating film112aon the surface of the n-type semiconductor layer106. Accordingly, because a formation process of the first insulating film112ais simplified, manufacturing throughput can be improved and, furthermore, manufacturing cost can be reduced.

Next, by forming a p-electrode to be connected to the p-type semiconductor layer116and an n-electrode to be connected to the n-type semiconductor layer106, the light-emitting element can be driven through the p-electrode and the n-electrode to perform light emission. Alternatively, before forming the p-electrode, an electrode film that covers the plurality of rod-like stacks110may be formed and the p-electrode may be formed on the electrode film. Accordingly, the plurality of rod-like stacks110can be simultaneously driven by one p-electrode.

As the electrode film, for example, a conductive oxide film such as indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, or InGaZnO4or an Ag film can be used. The electrode film is preferably a monolayer film. Because a monolayer film enables a process of forming the electrode film and a subsequent wet etching process to be simplified as compared to using a multilayer film, manufacturing throughput can be improved and cost can be reduced. Forming a transparent film such as an ITO film as the electrode film has an advantage of making it easier to extract light emitted by the light-emitting layer114. The electrode film can be formed by a sputtering method without providing a resist mask.

In the present specification, expressions including “up”, “down”, “left”, and “right” that are used when expressing an orientation, a position, or the like of a component, such as “upper” in “upper surface” described above, represent a relative orientation, position, or the like among components in the drawings and are not intended to indicate an absolute position unless explicitly stated. For example, while the “upper surface” of the n-type semiconductor layer106described above represents a principal surface of the n-type semiconductor layer106that is not in contact with the buffer layer104, because the “upper surface” of the n-type semiconductor layer106faces upward inFIG. 2, the term “upper surface” is used for the sake of convenience.

Second Embodiment

FIG. 7is a sectional view schematically showing a light-emitting element formed according to a second embodiment. The present embodiment is a modification of the first embodiment. In the present embodiment, parts, members, portions, and elements having same functions as those in the first embodiment will be denoted by same reference characters as used in the first embodiment and descriptions thereof may be omitted. The present embodiment differs from the first embodiment in step S104of forming masks in forms of islands. In step S104according to the present embodiment, the plurality of masks108are formed so that the plurality of rods106aformed in step S106of forming rods include a first rod group A having a first interval d1and a second rod group B having a second interval d2that is wider than the first interval d1.

As described above, the positions of the rods106ato be formed are determined by the positions of the masks108. Therefore, setting intervals between the centers of adjacent masks108to the first interval d1also causes the intervals between the formed rods106ato be set to the first interval d1. Setting intervals between the centers of adjacent masks108to the second interval d2also causes the intervals between the formed rods106ato be set to the second interval d2. The plurality of rods106ahaving the first interval d1form the first rod group A and the plurality of rods106ahaving the second interval d2form the second rod group B.

As shown inFIG. 7, according to the present embodiment, a light-emitting element can be formed that includes, on a same substrate, the first rod group A having the first interval d1and the second rod group B having the second interval d2that is wider than the first interval d1. As a modification of the present embodiment, a third rod group having a third interval, a fourth rod group having a fourth interval, and the like may be further formed on the same substrate. It should be noted that rods positioned at boundaries between the respective rod groups tend to assume shapes that represent a mixture of characteristics of both rod groups. Therefore, the rods positioned at boundaries between the respective rod groups are preferably removed after formation.

The intervals between adjacent rods106aalso affect an amount of incorporation of In by an InGaN well layer in the light-emitting layer114. When the intervals between the rods106adiffer although a flow rate of In raw material gas is the same, the wider the intervals between the rods106a, the larger the amount of In incorporated into the InGaN well layer. The higher the ratio of In in the InGaN well layer, the greater the shift of a wavelength of light emitted by the InGaN well layer to a long wavelength side. Therefore, by adjusting the intervals between the rods106a, rod-like stacks110that emit light with different wavelengths can be formed. For example, rod-like stacks110of the three RGB colors can be formed on the same substrate102. Because the second interval d2between the rods106ain the second rod group B is wider than the first interval d1between the rods106ain the first rod group A, an emission wavelength of the second rod group B is longer than an emission wavelength of the first rod group A.

When forming the rods106aby a selective growth method, changing the intervals between the rods106amakes the diameter of the rods106asusceptible to change. With a method of forming the rods106aby etching as in the present embodiment, a uniform diameter of the rods106acan be more readily realized even when a plurality of rod groups with different intervals are formed on the same substrate. A “diameter” as described herein refers to a dimension of a maximum width of a cross section of the rod106a.

When the upper surface of the rod106ais (0001) plane, increasing the intervals between the rods106aas in the second rod group B shown inFIG. 7enables the light-emitting layer114and the p-type semiconductor layer116formed on the rods106ato be made in a tapered shape. The interval between the rods106afor obtaining such a shape is, for example, around 2.5 μm. When the light-emitting layer114and the p-type semiconductor layer116have a tapered shape, the wavelength of light emitted by the light-emitting element more readily shifts to the long wavelength side as compared to a case where the light-emitting layer114and the p-type semiconductor layer116do not have a tapered shape. This is conceivably due to the fact that, when the light-emitting layer114has a tapered shape, the amount of In incorporated into the well layer of the light-emitting layer114increases. When the upper surface of the rod106ais not flat, the upper surface of the rod106abeing (0001) plane may be paraphrased as the height direction of the rod106abeing a [0001] direction.

Third Embodiment

The present embodiment is a modification of the second embodiment and the first embodiment. In the present embodiment, parts, members, portions, devices, and elements having same functions as those in the second embodiment will be denoted by same reference characters as used in the second embodiment, and descriptions thereof may be omitted.

FIG. 8is a flow chart schematically showing the third embodiment. The present embodiment mainly differs from the second embodiment in that the present embodiment includes step S800of removing the masks108of a first mask group corresponding to the first rod group A but retaining the masks108of a second mask group corresponding to the second rod group B between step S106of forming rods and step S108of forming an insulating film. Step S800is further divided into step S802of forming a resist mask and step S804of removing the masks in forms of islands of the first mask group. The respective steps prior to step S800are the same as those in the first embodiment and a description thereof will be omitted.

FIG. 9Ais a sectional view schematically showing a state in which masks in forms of islands are formed on a surface of a first conductive semiconductor layer in the third embodiment.FIG. 9Bis a sectional view schematically showing a state in which a resist mask is formed after forming rods in the third embodiment. InFIG. 9A, a mask108on a left side belongs to a first mask group A having the first interval and a mask108on a right side belongs to a second mask group B having the second interval. InFIG. 9B, a rod106aon a left side belongs to the first rod group A having the first interval d1and a rod106aon a right side belongs to the second rod group B having the second interval d2. The first rod group corresponds to the first mask group, and the second rod group corresponds to the second mask group. In step S802, a resist mask202that covers the second rod group B but does not cover the first rod group A is formed.

FIG. 10is a sectional view schematically showing a state in which masks108in forms of islands of the first mask group corresponding to the first rod group A shown inFIG. 9Bhave been removed. In step S804, the masks108on an upper end of the rods106aof the first rod group A are removed by wet etching. BHF can be used as an etching solution. Subsequently, the resist mask202is removed.

FIG. 11is a sectional view schematically showing a state in which an insulating film is formed on surfaces of the rods and the like shown inFIG. 10. In step S108of forming an insulating film, the insulating film112is formed on surfaces of the rods106aand the remaining n-type semiconductor layer106. The insulating film112and the masks108have different etching rates with respect to an etching solution used in subsequent etching step S110, with the etching rate of the masks108being higher. In the present embodiment, for example, in step S104of forming masks in forms of islands, SiO2masks108in forms of islands are formed by a CVD method, and in step S108of forming an insulating film, a SiO2insulating film112is formed by a sputtering method. By using such methods, the etching rate of the masks108is made higher than the etching rate of the insulating film112with respect to the etching solution used in subsequent etching step S110.

FIG. 12is a sectional view schematically showing a state in which the insulating film on the lateral surfaces of rods have been removed by etching. In etching step S110, the insulating film112on the lateral surfaces of the rods106ais removed by wet etching. BHF can be used as an etching solution. In this case, because the etching rate of the masks108is higher, the masks108at the upper ends of the rods106ain the second rod group B are removed and, accordingly, the second insulating film112on the masks108is also removed. Because the upper surface of the rods106ain the first rod group A is a flat surface similar to the upper surface of the n-type semiconductor layer106, the second insulating film112bprovided on the upper surface of the rods106ais retained in a similar manner to the first insulating film112aon the n-type semiconductor layer106.

FIG. 13is a sectional view schematically showing a state in which a light-emitting layer and a second conductive semiconductor layer are formed on an outer periphery of rods. In step S112, the light-emitting layer114is formed, and in step S114, the p-type semiconductor layer116is formed. In this case, because the second insulating film112bis present at the upper end of the rods106ain the first rod group A, the light-emitting layer114and the p-type semiconductor layer116are only formed on the lateral surfaces of the rods106a. On the other hand, because neither the second insulating film112bnor the mask108is present at the upper end of the rods106ain the second rod group B, the light-emitting layer114and the p-type semiconductor layer116are not only formed on the lateral surfaces of the rods106abut also formed on the upper ends of the rods106a.

A growth rate of semiconductor layers on the lateral surfaces of the rods106ais low. In particular, when the light-emitting layer114and the p-type semiconductor layer116are given tapered shapes as in the rod-like stacks110in the second rod group B, the growth rate further decreases. However, if the light-emitting layer114and the p-type semiconductor layer116also grow on the upper surface of the rods106ain the second rod group B, the growth rates of the light-emitting layer114and the p-type semiconductor layer116on the lateral surfaces can be increased.

In each embodiment of the present invention, a light-emitting element having a plurality of rod-type light-emitting sections can be obtained. Moreover, the first insulating film112athat prevents leakage between the p-type semiconductor layer116and the n-type semiconductor layer106can be readily formed on the surface of the n-type semiconductor layer106. Accordingly, manufacturing throughput can be improved and manufacturing cost can be reduced.

Furthermore, according to the second embodiment and the third embodiment, the rod-like stacks110that emit light with different wavelengths can be formed on a same substrate. In addition, a structure of a light-emitting element that enables an In content of a well layer in the light-emitting layer114to be readily increased can be provided.

The present invention is not limited to the embodiments described above, and encompasses various modifications. For example, while an “n-type” is referred to as a “first conductive type” and a “p-type” is referred to as a “second conductive type” in the embodiments described above, conversely, a “p-type” may be referred to as the “first conductive type” and an “n-type” may be referred to as a “second conductive type”. In addition, while the above embodiments have been described in detail in order to explain the present invention in an easily understood manner, the present invention is not necessarily limited to modes that include all of the components or steps described above. For example, while the buffer layer104is formed on the principal surface102aof the substrate102and, subsequently, the n-type semiconductor layer106is formed on the buffer layer104in step S102in the embodiments described above, the n-type semiconductor layer106may be directly formed on the principal surface102aof the substrate102. If the substrate102is constituted by an n-type semiconductor (for example, an n-type GaN-based semiconductor), step S102of forming the n-type semiconductor layer106may be omitted and n-type rods106amay be formed by directly forming the masks108on the principal surface102aof the substrate102.

It should be noted that some of the components of a given embodiment may be replaced with components of another embodiment, and components of the other embodiment may be added to components of the given embodiment. In addition, with respect to a part of the components of each embodiment, others component may be added thereto or the part of the components may be replaced with other components.