HIGH EFFICIENCY POWER AMPLIFIER

In some embodiments, a power amplifier circuit can include a power amplifier having an input node and an output node, and a load modulation circuit coupled to the output node of the power amplifier. The power amplifier circuit can further include a control profile configured to provide information for generating a control signal for the load modulation circuit, and a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile. In some embodiments, the control profile can be further configured to provide information for generating a control signal for a phase compensation circuit.

BACKGROUND

Field

The present disclosure relates to amplifiers for radio-frequency (RF) applications.

Description of the Related Art

In electronic applications such as radio-frequency (RF) applications, signals can be amplified for a number of reasons. For example, an RF signal to be transmitted can be amplified by a power amplifier, and such an amplified signal can be routed to an antenna for transmission.

SUMMARY

In accordance with a number of implementations, the present disclosure relates to a power amplifier circuit that includes a power amplifier having an input node and an output node, a load modulation circuit coupled to the output node of the power amplifier, and a control profile configured to provide information for generating a control signal for the load modulation circuit. The power amplifier circuit further includes a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile.

In some embodiments, the control signal can be generated based on a first current representative of a tunable reference current and a second current representative of a saturation detection current. The first current can include an AMAM current.

In some embodiments, the power amplifier circuit can further include a phase compensation circuit implemented in the input node side of the power amplifier. The control profile can be further configured to provide information for generating a control signal for the phase compensation circuit. The control signal for the phase compensation circuit can be based on a third current representative of a tunable reference current and the second current. The third current can include an AMPM current.

In some embodiments, the load modulation circuit can be configured to provide variable capacitance that depends on a control voltage representative of the control signal.

The information provided by the control profile can include an optimized load at a minimum capacitance of the variable capacitance and an optimized load at a maximum capacitance of the variable capacitance.

The information provided by the control profile can further include an optimized bias configuration for the power amplifier.

The information provided by the control profile can further include an AMAM control profile for the generation of the control signal.

The information provided by the control profile can further include a phase compensation profile for generation of a control signal for a phase compensation circuit.

The information provided by the control profile can further include average power tracking performance information based on implementation of the control signal for the phase compensation circuit.

In some embodiments, the power amplifier can include an input stage and an output stage. The input stage can be implemented as a driver stage, and the output stage can be implemented as a final stage. The driver stage can be implemented as a cascode driver stage. The cascode driver stage can be configured to operate with a Class AB bias.

In some embodiments, the final stage can be implemented as a push-pull amplifier. The push-pull amplifier can include a splitter having an input and a pair of outputs, with each output being coupled to an input of a respective amplifier. The push-pull amplifier can further include a combining circuit that combines outputs of the pair of amplifiers. Each of the pair of amplifiers can be configured to operate with a Class AB bias. The combining circuit can include a transformer circuit having a primary with first and second nodes coupled to the outputs of the pair of amplifiers, and a secondary with first and second nodes, with the first node being coupled to an output node and the second node being coupled to ground through the load modulator.

In some implementations, the present disclosure relates to a method for operating a power amplifier. The method includes receiving a signal at an input node, amplifying the signal, and providing load modulation for the amplified signal by generating a control signal based on a control profile having information for the generation of the control signal.

In some embodiments, the load modulation can include a variable capacitance that depends on a control voltage representative of the control signal.

The information provided by the control profile can include an optimized load at a minimum capacitance of the variable capacitance and an optimized load at a maximum capacitance of the variable capacitance.

The information provided by the control profile can further include an optimized bias configuration for the power amplifier.

The information provided by the control profile can further include an AMAM control profile for the generation of the control signal.

The information provided by the control profile can further include a phase compensation profile for generation of a control signal for a phase compensation circuit.

The information provided by the control profile can further include average power tracking performance information based on implementation of the control signal for the phase compensation circuit.

In some implementations, the present disclosure relates to a semiconductor die that includes a substrate and a power amplifier circuit implemented on the substrate. The power amplifier circuit includes a power amplifier having an input node and an output node, a load modulation circuit coupled to the output node of the power amplifier, and a control profile configured to provide information for generating a control signal for the load modulation circuit. The power amplifier circuit further includes a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile.

In some embodiments, the control profile can be further configured to provide information for generating a control signal for a phase compensation circuit.

In some embodiments, the substrate can be configured to support heterojunction bipolar transistors.

In some implementations, the present disclosure relates to a packaged module that includes a packaging substrate and a power amplifier circuit implemented on the packaging substrate. The power amplifier circuit includes a power amplifier having an input node and an output node, a load modulation circuit coupled to the output node of the power amplifier, and a control profile configured to provide information for generating a control signal for the load modulation circuit. The power amplifier circuit further includes a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile.

In some embodiments, the control profile can be further configured to provide information for generating a control signal for a phase compensation circuit.

In some embodiments, the power amplifier circuit can be implemented on a single semiconductor die. In some embodiments, the packaged module can be implemented as a power amplifier module.

In some implementations, the present disclosure relates to a wireless device that includes an antenna and an amplifier circuit configured to amplify a radio-frequency signal associated with the antenna. The amplifier circuit includes an amplifier, a load modulation circuit coupled to an output node of the amplifier, and a control profile configured to provide information for generating a control signal for the load modulation circuit. The amplifier circuit further includes a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile.

In some embodiments, the control profile can be further configured to provide information for generating a control signal for a phase compensation circuit.

In some embodiments, the amplifier circuit can be implemented as a power amplifier circuit. The antenna can be configured to support a transmit operation of the amplified radio-frequency signal provided by the power amplifier.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Described herein are examples related to high efficiency power amplifiers.FIG.1shows a power amplifier system400configured to receive a signal as an input (RF_IN) and amplify the signal with a power amplifier404. The amplified signal can then be provided as an output (RF_OUT). As described herein, the power amplifier system400may also be referred to as a power amplifier circuit, or simply as a power amplifier.

FIG.1shows that in some embodiments, the power amplifier system400can include a load modulation (LM) circuit414. Such a load modulation circuit (also referred to herein as a load modulator) can be coupled to an output side of the power amplifier404.

Although various examples are described herein in the context of power amplifiers, it will be understood that in some embodiments, one or more features of the present disclosure can also be utilized for other types of amplifiers.

FIG.1shows that in some embodiments, the power amplifier system400can also include a phase compensation circuit402implemented on the input side of the power amplifier404. For example, the phase compensation circuit402can be implemented between the input RF_IN and a DC-blocking capacitance on the input side of the power amplifier404.

Referring toFIG.1, the power amplifier system400can include a control circuit410configured to control the load modulator414and the phase compensation circuit402. In some embodiments, the control circuit410can include or have access to one or more control profiles412for operation of either or both of the load modulator414and the phase compensation circuit402.

FIG.2shows that in some embodiments, the power amplifier404ofFIG.1can be implemented as a power amplifier having a push-pull architecture. In the example ofFIG.2, the power amplifier404is shown to include a cascode driver stage and an inverse F push-pull final stage. In some embodiments, a load modulator (LM)414is shown to be coupled to a secondary of an output combining/matching balun circuit415combines the outputs of two amplifiers (each indicated as A/2 inFIG.2) of the push-pull final stage.

In the example ofFIG.2, the load modulator414is shown to be controlled by the control circuit410. In some embodiments, the control circuit410ofFIGS.1and2can be based on the control profile(s)412as described herein to control the load modulator414.

In the example ofFIG.2, each of the cascode driver stage and the push-pull final stage is depicted as being provided with Class AB bias. However, it will be understood that one or more features of the present disclosure can also be implemented in power amplifiers having different bias configurations.

FIG.2shows that in some embodiments, a phase compensation circuit404having one or more features as described herein can be implemented between on the input side of the cascode driver stage, and be controlled by the control circuit410. In some embodiments, the control circuit410ofFIGS.1and2can be based on the control profile(s)412as described herein to control the phase compensation circuit402.

Additional details and examples of the load modulator414ofFIGS.1and2are provided in the herein-referenced U.S. Provisional Application No. 63/337,160 which is hereby expressly incorporated by reference herein in its entirety. Additional details and examples of the phase compensation circuit402ofFIGS.1and2are provided in the herein-referenced U.S. Provisional Application No. 63/337,161 which is hereby expressly incorporated by reference herein in its entirety.

FIG.3shows an example where the power amplifier system400ofFIG.2includes a control circuit410that generates a control voltage for the load modulator414based on a current IAMAM and saturation detection, and a control voltage for the phase compensation circuit402based on a current IAMPM and the saturation detection. Additional details and examples of such generation of control voltages based on respective currents and the saturation detection are provided in the herein-referenced U.S. Provisional Application No. 63/337,162 which is hereby expressly incorporated by reference herein in its entirety, where the control circuit410may be referenced as300, the load modulator414may be referenced as100, and the phase compensation circuit402may be referenced as200.

In the example ofFIG.3, the driver stage that includes the cascode amplifier is also shown to include a low-power mode (LPM) amplifier in parallel with the cascode amplifier. Such a low-power mode amplifier can be enabled (and the cascode amplifier disabled) when the input power is below some level. It will be understood that a power amplifier having one or more features as described herein may or may not include such a low-power mode amplifier.

Described herein are examples of steps that can be utilized to design a high efficiency power amplifier. Referring toFIG.4, such steps can include a step (Step1) where loads at minimum and maximum load modulation (LM) capacitances are optimized.

For example, and as described in U.S. Provisional Application No. 63/337,160, suppose that the load modulator provides a linear relationship between the capacitance C of the load modulator and the control voltage VCTRL range of 1.0V to 2.5V. Then, the minimum capacitance CMINcan be selected to be the capacitance C when the load modulator is provided with VCTRL=1.0V, and the maximum capacitance CMAXcan be selected to be the capacitance C when the load modulator is provided with VCTRL=2.5V.

Referring toFIG.4where 5V is provided to the combiner415, UHB PSAT at CMAXcan be calculated to be 28.7 dBm+2 dB+4.5 dB=35.2 dBm, and UHB PSAT at CMINcan be calculated to be less than or equal to 35.2 dBm−4 dB=31.2 dBm.

Referring toFIG.4, Step2can include optimization of bias at CMIN(e.g., by setting VCTRL to 1.0V). Such an optimization can include a landing zone that is linear or approximately linear, and an ACLR plateau below −40 dBc can be targeted. Such a step effectively sets an ACLR plateau of the entire load modulated push-pull amplifier ofFIG.4.

Referring toFIG.4, Step3can include obtaining of a desired AMAM control profile for controlling of the load modulator414. Such an AMAM control profile can be obtained by running waterfalls with bias and load configurations of Steps1and2. For example, VCTRL can be varied in 50 mV steps between the example range of 1.0V to 2.5V. In some embodiments, a control circuit can be designed or configured to provide AMAM control based on ISOGAIN VCTRL vs VB2 profile, similar to the example described in U.S. Provisional Application No. 63/337,162.

FIG.5shows various plots related to the ISOGAIN characteristic in the foregoing Step3.

FIG.6depicts an example of how AMAM control with the control circuit410,300ofFIG.3can be implemented, as described in U.S. Provisional Application No. 63/337,162.

FIG.7shows an example of how the control signal VCTRL can be generated by the control circuit410,300ofFIG.3, as described in U.S. Provisional Application No. 63/337,162.

FIG.8shows gain, phase and PAE plots of the power amplifier ofFIG.4with AMAM control provided as described herein. As shown in the gain vs output power plot in the upper right panel, nearly ideal AMAM characteristic is displayed. However, and as shown in the phase vs output power in the lower right panel, AMPM correction above 30 dBm is desirable.

FIG.9shows that Step4can include obtaining of a phase compensation control profile. Such a step can include running an input power sweep with AMAM control driving the load modulator. Results from such a sweep should match or be similar to the above-described ISOGAIN profile. Step4can further include designing or configuring a phase compensation to match AMPM vs VB2 characteristic, similar to the example described in U.S. Provisional Application No. 63/337,162.

FIG.10shows an example of a desired AMPM vs VB2 that can be obtained from Step4.

FIG.11depicts an example of how AMPM control with the control circuit410,300ofFIG.3can be implemented, as described in U.S. Provisional Application No. 63/337,162.

FIG.12shows an example of how the control signal VCTRL can be generated by the control circuit410,300ofFIG.3to provide AMPM control, as described in U.S. Provisional Application No. 63/337,162.

FIG.13Ashows the power amplifier system400ofFIG.9in a simplified manner with selected parameters emphasized.FIG.13Bshows various simulation results as operating temperature is varied from −30 deg. C. to 85 deg. C. One can see in the top panel that output current is very consistent over the range of temperature.

FIG.14Ashows the power amplifier system400ofFIG.9in a simplified manner with selected parameters emphasized.FIG.14Bshows VCTRL_AMPM curves as operating temperature is varied from −30 deg. C. to 85 deg. C.

FIG.15shows a loop portion emphasized, similar to the example in U.S. Provisional Application No. 63/337,162.FIG.15Bshows loop gain, loop phase and phase margin plots for different temperatures in a range of −30 deg. C. to 85 deg. C. As shown in the bottom panel, a minimum phase margin of 62.5 degrees is present.

FIG.16shows the power amplifier system400ofFIG.9in a simplified manner with selected parameters emphasized.FIG.16also shows AMPM profiles as a function of VB2 as IAMPM is swept.

FIG.17show example plots obtained with phase compensation as described herein. In the gain plots with and without AMPM compensation, one can see that the AMAM profile does not change significantly. Plots of AMPM vs output power show that there is a desired sweet spot that could be obtained and implemented as described herein. Similarly, plots of ACLR vs output power show that there is a desired sweet spot that could be obtained and implemented as described herein.

FIG.18shows that Step5can include implementing phase compensation and verifying APT performance. In some embodiments, such phase compensation can be implemented with a phase compensation circuit described in U.S. Provisional Application No. 63/337,161.

FIG.19shows plots of gain, AMPM and ACLR with the implementation of phase compensation according to Step5.

FIG.20shows various Smith charts associated with the power amplifier circuit400ofFIG.18.

FIG.21shows various harmonics associated with the power amplifier circuit400ofFIG.18.

FIG.22shows various currents associated with the power amplifier circuit400ofFIG.18.

FIG.23shows AMAM and AMPM control loop gains associated with the power amplifier circuit400ofFIG.18. It is noted that AMAM control behaves in a feed forward manner. It is also noted that input phase and base amplitude do not appear to be correlated.

FIG.24shows gain, AMPM and ACLR plots over a range of temperature.

FIG.25shows gain, AMPM and ACLR plots over process variation associated with capacitances of the phase compensation circuit.

FIG.26shows plots of gain, AMPM and ACLR with the implementation of phase compensation as described herein.

FIG.27shows another example of gain, AMPM and ACLR plots over process variation associated with capacitances of the phase compensation circuit.

FIG.28shows plots of gain, AMPM and ACLR with the implementation of phase compensation as described herein, and with load VSWR of 1.5:1.

FIG.29shows plots of gain, AMPM and ACLR with the implementation of phase compensation as described herein, and with load VSWR of 2:1. In some applications, there is too much expansion at low collector Z angles.

FIG.30shows plots of gain, AMPM and ACLR with the implementation of phase compensation as described herein, and with source VSWR of 2:1. One can see that there is very little ACLR variation from AMAM, and about +/−3 dB variation from AMPM.

FIG.31shows a plot of R×BN as a function of noise frequency, when a transmission operation is in progress at 3,750 MHz. One can see that there is approximately −133 dBm/Hz at 600 MHz below the Tx carrier frequency.

As described herein, a high linearity and wide bandwidth variable capacitance being connected to the secondary of an output combining/matching balun can provide a number of desirable features. Such features can allow the load presented to the power amplifier to be modulated as a function of a control voltage.

As also described herein, a desired amplitude control voltage profile can be obtained to optimize AMAM across the entire dynamic range. A saturation detection and amplitude processing circuit as described herein can provide such a voltage profile to the variable capacitance of the load modulator.

The foregoing AMAM control results in a very highly efficient power amplifier with flat AMAM across the dynamic range. A tradeoff for such a property can include a poor AMPM created with an active load network. However, a wide bandwidth active phase compensation circuit can be implemented at the input of the power amplifier to compensate for the poor AMPM.

As described herein, saturation detection and phase processing circuit can provide a voltage profile for the active phase compensation circuit. Such a phase compensation circuit is shown to have very little AMAM distortion, thereby resulting in a desirable solution with a flat AMAM, a flat AMPM, and high PAE.

FIG.32shows that in some embodiments, a semiconductor die700can include a power amplifier system400having one or more features as described herein. Such a power amplifier system can be implemented on a semiconductor substrate702.

FIG.33shows that in some embodiments, one or more features as described herein can be implemented in a packaged module800. Such a packaged module can include a packaging substrate802configured to receive a plurality of components. At least some of the components mounted on the packaging substrate802can include a die such as the die700ofFIG.32.

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.

FIG.34depicts an example wireless device900having one or more advantageous features described herein. In some embodiments, one or more power amplifier circuits400can be configured as described herein. In some embodiments, such one or more power amplifier circuits can be implemented on a power amplifier module916.

In the example wireless device900, the power amplifier (PA) module916having a plurality of PAs can provide one or more amplified RF signals to the switch920(via an assembly of one or more duplexers918), and the switch920can route the amplified RF signal(s) to one or more antennas. In some embodiments, the PAs in the module916can receive corresponding unamplified RF signal(s) from a transceiver914that can be configured and operated in known manners. The transceiver914can also be configured to process received signals. The transceiver914is shown to interact with a baseband sub-system910that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver914. The transceiver914is also shown to be connected to a power management component906that is configured to manage power for the operation of the wireless device900.

The baseband sub-system910is shown to be connected to a user interface902to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system910can also be connected to a memory904that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In some embodiments, the duplexers918can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,924). InFIG.34, received signals are shown to be routed to “Rx” paths that can include, for example, one or more low-noise amplifiers (LNAs).

A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.