Planarization of metal container structures

A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.

FIELD OF THE INVENTION

The present invention relates generally to the fabrication of semiconductive devices, and more particularly; to a method of forming conductive material in an opening in a semiconductive device. The invention also relates to the structures formed according to the various embodiments of the method herein set forth.

BACKGROUND OF THE INVENTION

In the fabrication of integrated circuits, various layers, e.g. conductive layers and insulative layers, are formed. For example, during the formation of semiconductive devices, such as dynamic random access memories (DRAMs), insulating layers are used to electrically separate conductive layers such as doped polycrystalline silicon, aluminum, metal silicides, etc. It is often required that the conductive layers be interconnected through holes or openings in the insulating layers. Such openings are commonly referred to as contact holes, e.g. when the opening extends through an insulating layer to an active area, or vias, e.g. when the opening extends through an insulating layer between two conductive layers. The profile of an opening is of particular importance such that specific characteristics can be achieved when a contact hole or via is provided and then filled with one or more conductive materials.

Conductive materials are also formed in openings when providing certain storage cell capacitors for use in semiconductive devices, e.g. DRAMs. Storage capacity and size are important characteristics of a storage cell. Generally, a storage cell is formed with a dielectric constant material interposed between two conductive electrodes. One or more layers of various conductive materials may be used as the electrode material.

Container-type cell capacitor structures generally include the formation of an insulative layer over existing topography which has been formed over a substrate, and then openings are etched into the insulative layer. These openings allow access to the underlying topography, e.g. for a cell capacitor, which may include conductive regions, e.g. conductive plugs, active substrate regions, etc. Thereafter, a conductive layer to be used for forming the bottom electrode of the cell capacitor is formed within the openings, and may also be formed on the upper surface of the insulative layer as well. A layer of oxide material may then be used to fill the opening over the conductive material. Thereafter, this oxide material is removed to expose the layer of conductive material. The exposed layers of conductive material which are outside of the opening, e.g. which are over the top surface of the insulative layer, are then removed to separate neighboring conductive openings, thereby forming individual containers with exposed insulative material between them. Next, the oxide material still filing the conductive opening is removed, leaving the opening lined with a bottom electrode for use in forming the container-type cell capacitor.

Storage capacity and size are important characteristics in a storage cell. One way to retain the storage capacity of a device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, preferably a high dielectric constant material is utilized in applications interposed between two electrodes. Many conductive metals such as platinum, rhodium, iridium, osmium, as well as other Group VIII metals, and other transition element metals, e.g. copper, silver and gold, and Group IIIa and IVa metals, e.g. aluminum, and their alloys are desirable electrode materials for such high dielectric constant capacitors.

However, many of the foregoing metals, e.g. Group VIII metals such as platinum or platinum alloys such as platinum-rhodium, are not easily planarized. An illustrative planarization problem is shown inFIG. 1A.FIG. 1Ashows a cross-sectional portion of a semiconductive device10. An insulative layer12is formed over a substrate11. An opening15is formed in the insulative layer12which stops on the surface of the substrate11. To form a lower electrode or bottom electrode of a capacitor-type structure, a metal layer20is formed over the insulative layer and as a lining in opening15. Thereafter, a photoresist layer25is formed over the metal layer20to completely fill the opening15. Upon plananzation, the upper portion of layer25is removed along with the metal portion20which is outside of the opening15, resulting in the non-dashed lining portion30. However, as shown inFIG. 1A, the metal is often deformed or smeared at the upper region or edge of the opening15. The metal material is pushed into the center of the container opening15as represented by projection35during the planarization process. Such deformation of the metal in the container opening15produces an undesirable profile and is further problematic in removing the resist material25from within the opening15.

As shown inFIG. 1B, a further problem associated with the use of a metal is shown wherein the metal layer20is not planarized, but instead is etched. However, upon wet etching the metal layer20back to the insulative layer12, the photoresist layer25is pulled back away from the metal layer, thereby allowing for undesirable removal of portions of the metal layer as shown by the undesirably etched regions40inFIG. 1B.

Thus, there exists a need in the art for a new method of forming conductive material in openings in semiconductive devices. There is also a need for better structures containing conductive material formed therein.

SUMMARY OF THE INVENTION

In accordance with the invention, there is set forth a method of providing a conductive material in an opening. The process involves first forming a conductive material in the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material such that at least some of the metal-containing material is located in the opening. At least a portion of the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.

The invention further provides a method of forming a bottom electrode of a capacitor. A second conductive material is provided within an opening in contact the first conductive material. The second conductive material is also provided over at least a portion of an insulative material which is outside of the opening. Next, a metal-containing fill material is provided over at least a portion of the conductive material which is inside the opening and which is over the insulative layer as well. At least a portion of the metal-containing fill material which is inside the opening is next removed and the second conductive material thereby forms the bottom electrode of a capacitor.

Also included is a method of providing a conductive material in an opening which has been provided in an insulative material over a substrate, wherein the opening contacts a surface portion of the substrate. First, a conductive material is deposited over at least a portion of the inside of the opening and over at least a portion of the surface of the insulative material which is outside the opening. Next, a tungsten-containing fill material is deposited over at least a portion of the conductive material which is over the surface portion of the substrate and which is over the insulative material outside of the opening. At that point, the tungsten material at least partially fills the opening. At least a portion of the tungsten-containing fill material and the conductive material which is over the insulative material outside the opening is then removed. The removal is effected by planarization. Next, at least a portion of the tungsten-containing fill material is removed from the opening.

According to another aspect of the invention, a structure comprises a substrate with an insulative material over the substrate. There is also a conductive material formed over at least a portion of the surface of the opening and over at least a portion of the insulative material which is outside the opening. A tungsten-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is over the insulative material outside the opening, such that the tungsten-containing fill material at least partially fills the opening.

Another structure of the invention also contains a substrate and an insulative material over the substrate. A conductive material is formed over substantially all of the inside surface of the opening. A tungsten-containing fill material is formed over the conductive material and substantially fills the opening. The conductive material and the tungsten containing material are substantially co-planar at the top of the opening.

A further method of the invention is useful in forming a bottom electrode of a capacitor and a bit line conductive plug in a semiconductive device. A first opening is provided through the surface of an insulative material provided over a substrate in the device, such that at least a portion of the opening contacts a first conductive material. A second conductive material is then provided over at least a portion of the surface of the opening which is in contact with the first conductive material, as well as over at least a portion of the surface of the insulative material which is outside the opening. A protective layer is next provided over the second conductive material. A second opening is then provided through the protective layer and through the second conductive material which is over the insulative material, as well as through the insulative material. At least a portion of the second opening contacts a third conductive material. The protective layer is then removed. A metal-containing fill material is next provided over the second conductive material which is inside the first opening and which is over the insulative material outside of the opening.

The metal-containing fill material is further provided over the second opening such that the metal-containing fill material at least partially fills both the first and second openings. A bit line conductive plug is thereby formed in the second opening. Next, at least a portion of the metal-containing fill material and the conductive material which is over the insulative material outside of both openings is removed. Thereafter, at least a portion of the metal-containing fill material from the first opening is removed so as to form the bottom electrode of the capacitor.

The invention also provides a method of planarizing a conductive material formed over an opening without substantially deforming the material. The conductive material is contacted with a metal-containing fill material such that the fill material is over the conductive material and at least partially fills the opening. The conductive material and the metal-containing fill material are then planarized such that a top portion of the conductive material and the fill material are substantially co-planar with a top portion of the opening.

Additional advantages and features of the present invention will become more readily apparent from the following detailed description and drawings which illustrate various exemplary embodiments of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The invention in its broadest embodiment is directed to a method of providing a conductive material in an opening in a semiconductive device, and to the structures formed therefrom.

Reference herein shall be made to the terms “substrate” and “wafer”, which are to be understood as including silicon, a silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) structures, doped and undoped semiconductives, epitaxial layers of silicon supported by a base semiconductive foundation, and other semiconductive structures. In addition, when reference is made to a “substrate” or “wafer” in the following description, previous process steps may have been utilized to form arrays, regions or junctions in or over the base semiconductive structure or foundation. In addition, the semiconductive material need not be silicon-based, but could be based on silicon-germanium, germanium, indium phosphide, or gallium arsenide. The term “substrate” as used herein may also refer to any type of generic base or foundation structure.

Referring again to the drawings,FIG. 2Aillustrates a semiconductive device200in an intermediate stage of fabrication. Shown is a substrate212and a layer214of material, preferably insulative material such as, for example, silicon dioxide or Boro-Phospho-Silicate Glass (BPSG), formed over the substrate212. The layer214has a top surface215. An opening216is formed in the layer214using methods known in the art, for example, wet and/or dry etching. The opening216can represent a contact opening or via, or even a trench or recess, and may or may not extend to the substrate surface (as represented by the dotted lines217). The opening216includes a bottom surface218and side walls220. Preferably, the bottom surface218is a generally horizontal surface from which the side walls220extend. The side walls220may be substantially orthogonal to the bottom surface218, as shown inFIG. 2A, or they may be of another desired angle or shape, depending upon the particular environment of use for the opening. Moreover, the opening216defined by bottom surface218and side walls220can be any shape suitable to the needs of the skilled artisan, including a generally cylindrical shape.

Referring now toFIG. 2B, one illustrative method of forming a conductive material in the opening216is described. A conductive material222is formed over the surfaces218,220which define the opening216. The conductive material is formed over at least a portion of the surfaces218,220, and more desirably is formed over a majority or even substantially all of the inside surfaces218,220. The conductive material222is shown as a substantially conformal, single layer of material inFIG. 2B, but those skilled in the art will recognize that the conductive material222may or may not be conformal, and may also be comprised of two or more layers. The conductive material222is desirably made up of one or more Group VIII metals, together with their alloys and composites, and thus can include platinum, palladium, ruthenium, iridium, osmium and rhodium, and such alloys as platinum-rhodium. Platinum is the preferred conductive material222for use in the method of the invention. Other suitable conductive materials include other transition element metals, e.g. gold, copper and silver, as well as the Group IIIa and IVa metals, e.g. aluminum, together with their alloys and composites.

The conductive material222may be formed in the opening216using any suitable method, such as sputtering, chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), electroplating and electroless plating. Preferably, the conductive material222is formed to a thickness within the range of a few Angstroms to several hundred Angstroms, which can vary according to the needs of the skilled artisan.

As further shown inFIG. 2B, the conductive material222preferably extends outside of the contact opening216and over the top surface215of the layer214. The conductive material222is preferably formed over substantially the entire surface of the layer214as shown inFIG. 2B, or may be formed over any fraction thereof and subsequently etched back. Also shown inFIG. 2Bare upper edges223aand223bof the conductive material222. The upper edges223a,223bextend above the plane formed by the upper surface215of the layer214, and they are bounded by the respective planes of the vertical lines extending upwards from the sidewalls220of the opening216.

Referring now toFIGS. 2C and 2D, after forming the conductive material222, a fill material224is next deposited over the conductive material222. The fill material224may be any suitable material which will protect the conductive material222from substantially deforming or smearing during a planarization step, hereinafter described. The fill material224should also be one which is itself capable of ultimate removal and/or planarization. The fill material224should also be substantially harder than the conductive material222, and even more preferably, should be substantially harder than typical photoresist materials used in the semiconductive industry. Preferably, the fill material224is comprised substantially of a hard metal, and more desirably, a tungsten-containing metal, which can therefore include tungsten, tungsten alloys, tungsten composites as well as tungsten compounds. For example, tungsten nitride (WNx) is one tungsten compound highly suitable as a fill material224. The fill material224may be deposited using suitable deposition techniques such as CVD or LPCVD, using WF6and silane (SiH4), for examples, as reactants. Other suitable fill material can include titanium-containing metals, which can include titanium, titanium alloys, titanium composites as well as titanium compounds such as, for example, titanium nitride (TiN).

Preferably, the fill material224extends into at least a portion of the opening216as shown inFIG. 2D, or substantially fills the opening216as illustrated inFIG. 2C. More preferably, the fill material224will substantially cover, or be substantially co-extensive with, the upper edges223a,223bof the conductive material222. This particular embodiment is illustrated in bothFIGS. 2C and 2D. Even more desirably, the fill material224will be substantially co-extensive with the conductive material222over the top surface215of the insulative layer214. The fill material224will be distributed to have a thickness that is typically within the range of a few hundred Angstroms to several thousand Angstroms.

Referring now toFIG. 2E, the portions of the conductive material222and the fill material224which are outside of the opening216and which are over the top surface215of the layer214are next removed from the device210. Preferably, removal is effected using a planarization technique which in general refers to the mechanical removal of material at a surface, and typically involves a flattening and polishing process used during semiconductive wafer fabrication. For example, such planarization may include chemical mechanical planarization (CMP), chemical mechanical polishing, planarization using pads and abrasive slurries, planarization using fixed abrasive pads either alone or in combination with slurries or other fluid compositions. Planarization is used to remove surface material for providing a flattening of surfaces of a wafer during the wafer fabrication process. The preferred method of removal is CMP. The removal or planarization process may also involve any number of actual process steps, e.g. repeated planarization for several periods of time, alternated by cleaning steps, etc.

As shown inFIG. 2E, the fill material224functions to support and protect the underlying conductive material222during the removal/planarization step so that the conductive material222is substantially prevented from being smeared, scratched and pushed out of shape, e.g. caused to form the undesirable overhang into the opening216, as was illustrated inFIG. 1A. Thus, the conductive material222remains substantially undeformed. After planarization is completed, the segments of the conductive material222and the overlying fill material224which were above the top surface215of the layer214are substantially all removed. Thus, in a preferred embodiment, the conductive material222at the top of the respective sidewalls220is substantially coplanar with the top surface215of the layer214. In another preferred embodiment, the fill material left inside the opening216is also substantially co-planar with the top surface215of the layer214.

Thereafter, as shown inFIG. 2F, substantially all of the remaining portion of the fill material224which is inside the opening216is removed from the device. Any method of removing the fill material may be utilized in the present invention. Preferably, a wet etch or dry etch process, or a combination thereof may be utilized to remove the fill material. If the fill material224is made up of the preferred tungsten or tungsten-containing material, e.g. tungsten nitride, then stripping in piranha can be used to remove this tungsten material from inside the opening216. As a result of the removal step inFIG. 2F, the conductive material222is left intact inside the opening216, substantially without being smeared or overhanging into the opening216. Preferably, a conformal layer of conductive material222is left over the sidewalls220and the bottom surface218of the opening216as shown inFIG. 2F. The top surfaces of the side walls are still desirably substantially co-planar with the top surface215of the layer214. The device200is now ready for further processing as desired by the person skilled in the art.

Referring now toFIG. 3A, there is shown an additional embodiment of the invention in another environment. A portion of a semiconductive device structure300is fabricated in accordance with conventional processing techniques through the formation of a contact opening302prior to metallization of the exposed contact area304of the surface portion305of the substrate307. The contact opening302may be formed through layer308, which is preferably a layer of insulative material such as BPSG or other suitable material, using suitable etching techniques, such as wet etching with hydrogen fluoride (HF) for example. Layer308has a top surface portion309. Also shown are gate stack transistors321and322which each may alternately function as a word line or field effect transistor. The sides of the gate stack321,322may be used to align the opening302to the substrate307, and therefore the opening may be described as a self-aligned contact (SAC) opening. The device300further includes a field oxide region325formed in the substrate. Suitably doped source/drain regions330and335are formed in the substrate307between the gate stack transistors according to processes available to the skilled artisan. The opening302inFIG. 3Ais further shown with side walls340.

With reference now toFIG. 3B, a conductive material350is deposited inside the opening302in the manner as heretofore described. As previously set forth, the conductive material is preferably a transition element metal, e.g. a Group VIII material, and more desirably is platinum, a platinum compound or a platinum alloy, but other conductive material metals as previously mentioned may also be utilized. The conductive material is formed over the sidewalls340of the layer308, as well as over the sides of the gate stacks321and322, and over the exposed portion304of the top surface305of the substrate307. Preferably, the conductive material substantially covers the top surface portion309of the insulative layer308. Further shown inFIG. 3Bis a fill material360which is next deposited over the conductive material350, again as previously described. The fill material360is desirably tungsten or a tungsten compound such as tungsten nitride, or any other suitable material which is harder than the underlying conductive material350, and can thus include titanium and titanium compounds such as titanium nitride. As shown inFIG. 3B, the fill material preferably substantially covers the top edge portions375of the conductive material350. Even more preferably, the fill material360is substantially co-extensive with the conductive material350over the top surface309of the layer308.

As now shown inFIG. 3C, the portions of the conductive material350and the overlying fill material360outside of the contact opening302are then removed, preferably by one or more planarization techniques as described above. As a result, the top portions of the conductive material350are desirably substantially coplanar with the top surface309of the layer308.

InFIG. 3Dthe fill material360is now removed from the inside of the contact opening302. It is desirable that substantially all of the fill material360be removed from the device300using a technique such as etching, etc., as heretofore described. The device shown inFIG. 3Dis now ready for further fabrication according to the needs of the skilled artisan, including further metallization or additional deposition of other conductive materials inside contact opening302over conductive material350. As shown inFIG. 3D, the top portions of the conductive material350are still preferably substantially coplanar with the top surface309of the layer308, and are not substantially deformed, bent or overhanging into the opening302.

Referring now toFIG. 4A, there is set forth a further embodiment of the invention. A semiconductive device400is shown fabricated using conventional processing techniques through the formation of an opening402. Such processing is performed prior to depositing a bottom electrode structure on the surfaces defining the opening402using one of the methods described in accordance with the present invention. The device400includes field oxide region425formed in substrate407, as well as source and drain regions430,435which may be suitably doped. Also shown are gate stack transistors421and422, which each may alternately function as a word line or field effect transistor. A first layer440of an insulative material, e.g. BPSG, has been formed over the substrate407of the structure400. A plug445of electrically conductive material, e.g. polysilicon, has been formed in an opening447provided in layer440to provide electrical communication between a top surface448of the active source/drain region430of the substrate407and a storage cell capacitor to be later formed thereover. One or more barrier layers may be formed over the polysilicon plug445, including layers449aand449bas shown inFIG. 4A. For example, one or more of the barrier layers may be comprised of such compounds as titanium nitride, tungsten nitride, titanium silicide, or any other metal nitride or metal silicide layer which can function as a barrier layer. A second insulative layer443is formed over the first insulative layer440. The opening402is defined in the second layer443using available methods such as etching.

With reference now toFIG. 4B, a conductive material450is deposited inside the opening402in the manner as heretofore described. As previously set forth, the conductive material is preferably a transition element metal or a Group IIIa or IVa metal, and more desirably is a Group VIII material, including platinum, platinum compounds and platinum alloys. The conductive material is formed over the sidewalls457of the layer443, and over the bottom portion458of the opening402. Even more preferably the conductive material450extends over the top surface459of the insulative layer443.

Further shown inFIG. 4Bis a fill material465which is next deposited over the conductive material450, again as previously described. The fill material465is desirably tungsten or a tungsten compound such as tungsten nitride, or any other suitable material which is harder than the underlying conductive material450. Desirably, the fill material465substantially covers, e.g. is co-extensive with the top corner segments475of the conductive material. More desirably, the fill material is substantially co-extensive with the conductive material which is formed on the top surface459of the layer443.

As shown inFIG. 4C, the portions of the conductive material450and the overlying fill material465outside of the contact opening402are now removed, preferably by one or more planarization techniques as described above. As a result, the top portions of the conductive material450are desirably substantially coplanar with the top surface459of the layer443.

InFIG. 4Dthe fill material465is removed from the inside of the contact opening402. It is desirable that substantially all of the fill material465be removed from the device400using a technique such as etching, etc., as heretofore described. The conductive material450thus functions as a capacitor bottom electrode as shown inFIG. 4D. A dielectric material layer470is formed over the bottom electrode450using a process known in the art. For example, the dielectric layer may be any material having a suitable dielectric constant such as BaxSr(1-x)TiO3[BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3[PZT], (Pb,La)(Zr,Ti)O3[PLZT], (Pb,La)TiO3[PLT], KNO3, Al2O3, Si3N4, SiO2, Ta2O5, TiO2, ZrO2, HfO2and LiNbO3, among others. Thereafter, a second or top electrode475is formed over the dielectric material470. In one embodiment of the invention, the second electrode475may also be formed of a Group VIII metal, preferably platinum or a platinum alloy, as well as other conductive material metals as heretofore described. It will be recognized by one skilled in the art, however, that either one or both of the electrodes may be formed of any conductive material generally used for capacitor electrode structures. It is also within the scope of the invention that each electrode be one of several layers forming an electrode stack. The structure inFIG. 4Dcan thus function as a typical storage capacitor.

Referring now toFIG. 5A, there is shown another embodiment of the present invention. According to this embodiment, it is possible to fabricate a bit line conductive plug. A semiconductive device500is shown fabricated using conventional processing techniques through the formation of openings502and504over the substrate507. The device500includes field oxide regions508. Also shown are gate stack transistors509, which each may alternately function as a word line or field effect transistor. The device500further includes suitably doped source/drain regions510which are formed in the substrate507according to processes available to the skilled artisan. A first layer512of an insulative material, e.g. BPSG, has been formed over the substrate507. A first conductive plug514has been formed in an opening provided in layer512to provide electrical communication between the source/drain region510in the substrate507and a bit line conductive plug to be later formed thereover.

The first conductive plug514may be formed of a suitably conductive material, such as polysilicon for example. Second and third conductive plugs516,518have also been formed in openings provided in layer512to provide electrical communication between the source/drain regions510and a storage cell capacitor which may formed thereover. The second and third conductive plugs are also formed of suitably conductive material which may be the same or different, but is preferably polysilicon. One or more barrier layers520,522have been formed over the second and third conductive plugs516,518. As set forth above, the barrier layer(s) may be formed from such compounds as titanium nitride, tungsten nitride, titanium silicide, or any other metal nitride or metal silicide layer. Thereafter, a second insulative layer525is formed with openings502,504defined therein according to methods known in the art. Openings502,504are preferably contact openings which are formed using available etching, e.g. wet or dry etching, techniques.

With reference now toFIG. 5B, a conductive material530is deposited inside the openings502,504in the manner as heretofore described. As previously set forth, the conductive material is preferably a Group VIII material, and more desirably is platinum or a platinum alloy, but other transition element metals (e.g., copper, silver and gold), as well as Group IlIa and IVa metals, e.g. aluminum, may also be utilized. The conductive material is formed over the sidewalls532inside of the openings502,504in the insulative layer525, and over the bottom portions534of the openings. The conductive material is also preferably formed over the top surface536of the layer525.

Further shown inFIG. 5Cis a protective layer540which is next deposited over the structure500, including the conductive material530, using available techniques. Preferably, the protective layer540is a photoresist layer. The protective layer540is used to pattern an opening in the insulative layer525which will serve as the contact opening542with the polysilicon plug514for the bit line conductive plug to be subsequently formed. The contact opening542is then etched using suitable etching techniques, for example, a dry etch using CF4, CHF3and argon gases. InFIG. 5B, the etch stop is the top surface of the polysilicon plug514.

Thereafter, as shown inFIG. 5D, the protective layer540, e.g. the photoresist layer, is removed. Next, fill material545is deposited over the structure500as heretofore described. The fill material is desirably a hard metal, metal alloy or metal compound, such as tungsten or a tungsten compound like tungsten nitride, or any other suitable material which is harder than the underlying conductive material530. If desired, the fill material deposition step may be preceded by a titanium or titanium nitride deposition step in the contact opening542. The titanium material will coat the inside of the contact opening542to improve the adhesion of metal within the insulative layer525. The titanium material may be deposited using a CVD process, for example.

As next shown inFIG. 5E, the portions of the conductive material530and the overlying fill material545outside of the contact openings502,504,542are then removed, preferably by one or more planarization techniques, e.g. CMP, as described above. The metal-containing fill material545functions to protect the conductive material from spreading or smearing into the contact openings502,504. As a result of planarization, the top portions of the conductive material530are desirably substantially coplanar with the top surface536of the insulative layer525. In addition, the top portion of the fill material545inside the contact openings502,504, and542is also preferably substantially co-planar with the top surface536of the layer525.

Referring now toFIGS. 5F and 5G, the fill material inside contact opening542now forms a bit line conductive plug545ain contact with the conductive polysilicon plug514. Next, a protective cap555is deposited over the bit line conductive plug545a. The protective cap is desirably formed from a substantially non-conductive material such as an oxide. Thereafter as shown inFIG. 5G, the fill material545is removed from the inside of the contact openings502,504. It is desirable that substantially all of the fill material545be removed from the contact openings502,504using a technique such as etching, etc., as heretofore described. The conductive material530can thus function as a capacitor bottom electrode as was illustrated inFIGS. 4A through 4D.

Due at least in part to their improved electrical characteristics, the structures herein described have wide applicability in the semiconductor industry. A typical processor system which includes integrated circuits that utilize one or more of the structures formed in accordance with the present invention is illustrated generally at600inFIG. 6. A processor system, such as a computer system, for example, generally comprises a central processing unit (CPU)610, for example, a microprocessor, that communicates with one or more input/output (I/O) devices640, and a hard drive650over a bus system670which may include one or more busses and/or bus bridges. The computer system600also includes a hard disk drive620, a floppy disk drive630, a random access memory (RAM)660, a read only memory (ROM)680and, in the case of a computer system may include other peripheral devices such as a compact disk (CD) ROM drive630which also communicate with CPU610over the bus670. The invention may be used in one or more of the processor, RAM and ROM, or a chip containing a processor and on board memory. WhileFIG. 6shows one exemplary computer system architecture, many others are also possible.

The foregoing description is illustrative of exemplary embodiments which achieve the objects, features and advantages of the present invention. It should be apparent that many changes, modifications, substitutions may be made to the described embodiments without departing from the spirit or scope of the invention. The invention is not to be considered as limited by the foregoing description or embodiments, but is only limited by the scope of the appended claims.