Data processing system having multiple register contexts and method therefor

A data processing system having multiple register contexts is described. One embodiment of the present invention uses a user programmable context control register for each of the multiple register contexts to allow for the mapping of portions of an alternate register context into a current register context. The context control register may also be used to provide for the sharing of common stack pointers among multiple register contexts. Therefore, when operating in a current register context, the context control register may be used to access portions of an alternate register context in place of accessing corresponding portions of the current register context.

FIELD OF THE INVENTION

The present invention relates generally to a data processing system, and more specifically, to a data processing system having multiple register contexts.

RELATED ART

In data processing systems, such as microprocessors, a processor is utilized to control execution and processing of operations. The processor includes registers which store a register context which is utilized by the processor during normal operation and exception processing. When an interrupt or process switch occurs, the register context information may be corrupted because the interrupt processing program or the new process will use the same registers and may change some of the values therein.

One solution to the above mentioned problem is to save the current values of the register context in a memory prior to beginning the processing of the interrupt or the new process, and reading the saved register context values back into the registers from the memory when the interrupt processing is complete or when returning back to the current process. However, the overhead of saving the register context, and loading a new context is undesirable in a real-time or high-performance environment. Therefore, a need exists for a register context selection scheme in a data processing system which is flexible and reduces overhead.

DETAILED DESCRIPTION OF THE DRAWINGS

As used herein, the term “bus” is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. The terms “assert” and “negate” (or “deassert”) are used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one. The symbol “$” preceding a number indicates that the number is represented in its hexadecimal or base sixteen form. The symbol “%” preceding a number indicates that the number is represented in its binary or base two form.

FIG. 1illustrates a data processing system10coupled to an external device2via a data bus4and an address bus6. Data processing system10includes a processor12. In one embodiment, data processing system10and external device2are each implemented as separate integrated circuits. In alternate embodiments, data processing system10and external device2can be implemented on a single integrated circuit. Within data processing system10, processor12is coupled to system integration circuit22by an internal data bus13and internal address bus14.

Note that in some embodiments of the present invention, data processing system10is formed on a single integrated circuit. Additionally, in some embodiments, data processing system10may be a single chip microcontroller, a microprocessor, a digital signal processor, or any other type of data processing system. Furthermore, data processing system10may be implemented using any type of electrical circuitry. External device2may be any type of electrical circuit, including a memory or any type of peripheral device. Alternate embodiments may include more, fewer, or different external integrated circuits. In addition buses4and6can be implemented using any number of bits.

In operation, system integration22is used to allow communication between processor12and external device2. That is, processor12passes data and address information via internal buses14and13to system integration22which then passes the data and address information via buses4and6in a method and format appropriate for external device2. Processor12will be discussed in more detail below in reference toFIG. 2.

FIG. 2illustrates a portion of processor12in accordance with one embodiment of the present invention. Processor12includes an arithmetic logic unit (ALU)24, an address generator26, an instruction pipeline28, an instruction decode circuit30, a register file set32, and a vector offset generator39. Register file32includes multiple register contexts, such as context034, context135and context N36. Therefore, register file32includes N+1 registers contexts, and although only 3 are illustrated inFIG. 2, processor12may include any number of register contexts, depending on how many register contexts the hardware can support. Register file32also includes a control register file38. Internal address bus14is coupled to address generator26, and address generator26is coupled to register file32via a register source bus40and is also coupled to internal data bus13. Vector offset generator39is coupled to address generator26via a vector offset bus27. Internal data bus13is coupled to instruction pipeline28, ALU24, and register file32. Instruction decode circuit30is bi-directionally coupled to instruction pipeline28via an instruction bus29. Register file32is coupled to ALU24via a filed information bus42.

FIG. 3illustrates a register context51according to one embodiment of the present invention. Register context51ofFIG. 3may represent any one of contexts0through N ofFIG. 2. In the embodiment ofFIG. 3, register context51includes32general purpose registers (GPR)50, a link register54, a count register56, a condition register58, an integer exception register60, a machine state register62, and a context control register64. Link register54is used to hold subroutine linkage information when calling and returning from a subroutine. Count register56is used to hold count information for processing counted loops of instructions. Condition register58is used to hold the results of condition code calculations. Integer exception register60is used to provide various exception status. Machine state register62is used to control and provide status of various functions within processor12. Context control register64, as will be discussed in more detail below, is used to provide for context switching in accordance with one embodiment of the present invention. Note also that one of the GPR50is a stack pointer register52which is reserved for storing the current stack pointer.

Therefore, a register context refers to the contents of the registers described above (the registers of context51). Alternate embodiments may define a register context as having all or some of the same registers of register context51, or may include a different set of registers from those of register context51. Therefore, as used herein, a register context can be defined to have any number and any type of registers. Typically, a register context contains register resources that form all or a portion of a programmers' register model for a processor. During normal operation or upon power up or reset, data processing system10may default to utilizing context034. (Note that in alternate embodiments, normal operation may default to a different context.) However, when an interrupt or process switch occurs, so as not to corrupt the values in context034, data processing system10selects a new context (from context1to N) for processing the interrupt or executing the new process or thread. Therefore, interrupt handling and process switching (e.g. multithreading) may result in a need for register context switching within data processing system10. Also, in some embodiments, it may be desirable to share a portion of the registers within a register context with another register context. Therefore, as will be described below, portions of a register context may be mapped into another register context to help reduce overhead and increase the speed during a context switch.

In data processing system10, exceptions and interrupts are recognized at a decode stage or an execution stage of instruction pipeline28. Thus, when an instruction is provided to instruction decode circuit30and decoded, an interrupt may be recognized and processed, in lieu of normal instruction processing. In one embodiment described herein, there are multiple interrupt levels which determine whether a given interrupt has priority over any other interrupt. Thus, and interrupt with a high priority will get processed more quickly than an interrupt with a lower priority, which must wait for processing. Each interrupt or type of interrupt or interrupt having a same priority may therefore share a same register context if desired.

When an interrupt is received, data processing system10begins to execute an exception processing sequence. During this sequence, vector offset generator39provides a vector offset value via vector offset bus27to address generator26. Address generator26uses the vector offset value to form an instruction address at which execution is to begin for processing the interrupt. In one embodiment, in addition to the vector offset value, vector offset generator also provides a context selector indicating the register context to be used for the interrupt processing. In one embodiment, the context selector is a part of the vector offset value, or may be a separate value provided by vector offset generator39. Also, the context selector can be provided directly to register file32. In alternate embodiments, the context selector can be a value read from a memory (not illustrated) or may be received via an instruction. In the case of data processing system10having 8 register contexts in register file32, the context selector may be a 3-bit value used to identify one of the register contexts.

Also, data processing system10may be capable of process switching where processor12is capable of switching from one process to another, where each process may operate in a different register context. For example, in a multi-threading application, processor12may continually switch among various processing threads, where different processing threads (or groups of processing threads) use a different register context. In the case of process switching, an interrupt may be used to indicate a process switch to data processing system10(where the interrupt handling includes switching processes). Alternatively, other methods may be used to indicate to address generator26that a process switch is necessary such that address generator26can generate a starting address for the new process. Also, upon a process switch, a context selector is also provided to indicate which register context is needed for the new process. As described above, the context selector can be provided in a variety of different ways (i.e. from vector offset generator39, from a memory, from a user instruction, etc.) and can be provided directly or indirectly (e.g. via address generator26) to register file32such that the correct register context can be selected.

Once a register context has been established, instructions executed by processor12will reference the appropriate general purpose registers (GPRs50) or special purpose registers (e.g. LR54, CTR56, CR58, XER60, MSR62, or CTXCR64) corresponding to the currently established context. Registers within other contexts will not be affected (unless a mapping has been established as will be described below), thus no saving or restoring of alternate contexts to memory need be performed prior to execution of instructions for the currently established context. This provides for a savings in overhead.

FIGS. 4 and 5illustrate example mappings within register contexts that may be used within data processing system10.FIG. 4illustrates three register contexts: context070, context172, and context274. These register contexts may represent three of the contexts within contexts0through N ofFIG. 2. Assume that in the example ofFIG. 4, context070corresponds to normal operation of data processing system10, context172corresponds to a critical interrupt (highest priority), and context2corresponds to an external interrupt (lower priority). As mentioned above, in some cases it is desirable for multiple register contexts to “share” a portion of the registers. Therefore, in the example ofFIG. 4, as indicated by arrow82, stack pointer register80of register context274is mapped to stack pointer78of register context172indicating that register context172and register context274are able to share a same stack pointer such that the same stack pointer value is used in both register contexts. This mapping reduces overhead and helps maintain coherency of the stack pointer. Therefore, upon processing an external interrupt, context274is selected by data processing system10. However, since stack pointer register80is mapped to stack pointer register78, stack pointer register78in register context172is accessed during operation in register context274in order to access the stack pointer. In other words, while operating with a current context value selecting register context274, instructions and other operations which attempt to access stack pointer register80are redirected to access stack pointer register78within register context172. This allows a single consistent stack and stack pointer value to be shared between context1and context2, without the overhead of synchronizing separate stack pointer registers80and78.

Note that stack pointer register76(of context070) and stack pointer register78(of context172) are not mapped; therefore, when operating in these register contexts, no other register contexts need to be accessed when accessing the stack pointer. Context control registers77,79, and75within each of register contexts70,72, and74, respectively, indicate whether the stack pointer of the corresponding register context is mapped, and if so, to which other register context it is mapped to. The details of the context control register will be discussed in more detail below in reference toFIG. 6.

FIG. 5illustrates three register contexts in accordance with another example: register context190, register context292, and register context394. As withFIG. 4, the register contexts ofFIG. 5may represent three of the register contexts of register contexts0through N ofFIG. 2. In the example ofFIG. 5, register context190corresponds to Process A, register context292corresponds to Process B, and register context394corresponds to Process C. Therefore, when data processing system10is executing Process A, data processing system10operates in register context190. Upon a process switch (such as from Process A to Process B), the context selector selects register context292for use when executing Process B. As described above in reference toFIG. 4, each of the stack pointer registers have the capability of being mapped to a different register context. For example, inFIG. 5, stack pointer register96of register context190is mapped to stack pointer register98of register context292as indicated by arrow124. Therefore, when executing Process A (using register context190), an access to the stack pointer actually results in an access to stack pointer register98within a different register context (i.e. register context292). Note that stack pointer register100of register context394, though, is not mapped. Also, in one embodiment, it is possible to have layered mappings. For example, just as stack pointer register96is mapped to stack pointer register98, stack pointer register98can also be mapped to, for example, stack pointer register100. Also, a particular stack pointer register can have multiple stack pointer registers mapped to it. For example, both stack pointer registers100and96could be mapped to stack pointer register98. Other mappings are possible as well.

The register contexts ofFIG. 5also include groupings of registers. For example, the general purpose registers are grouped into groups of four registers. In register context190, GPR4–7are grouped together into register group102, GPR8–11are grouped together into register group104, and GPR28–31are grouped into register group106. Therefore, register context190, in the example ofFIG. 5, includes three groups (groups102,104, and106) of four registers each, where each of these groups can be mapped (as a group) to a different register context. In alternate embodiments, any number and type of registers may be grouped. Alternatively, each individual register may be considered a separate group, depending on the granularity desired. Similarly, register context292includes three groups of four registers: group114having GPR4–7, group116having GPR8–11, and group118, having GPR28–31). Also, register context394includes three groups of four registers: group108having GPR4–7, group110having GPR8–11, and group112, having GPR28–31). These groupings allow for groups of registers to be mapped among different register contexts.

For example, as illustrated by arrow120, group118of register context292is mapped to group106of register context190. As shown by arrow126, group112of register context394is also mapped to group106of register context190. That is, the registers of group106are shared by all three register contexts: register context190, register context292, and register context394. Therefore, when executing either Process B or Process C, an access to GPR28–31of the current register context (register context292or register context394, respectively) actually results in an access to GPR28–31of register context190. Also illustrated inFIG. 5, as shown by arrow122, group104of register context190is mapped to group116of register context292. That is, the registers of group116are shared by both register context190and register context292. Therefore, when executing Process A, an access to GPR8–11of the current register context actually results in an access to GPR8–11of register context292. Therefore, any number of mappings may exist, whether it be of a single register (such as stack pointer register96,98, or100) or groups of registers. Also, each register context may have some registers mapped to one register context and other registers mapped to another register contexts. Also, a register or group of registers may have registers of multiple register contexts mapped to it.

The mappings of each register context is defined in the context control register of each register context (for example, context control registers128,130, and132ofFIG. 5). Therefore, each register context0–N ofFIG. 2has a corresponding context control register which may be included in each register context (as inFIGS. 4 and 5) or may be stored separately (such as in control register file38ofFIG. 2).FIG. 6illustrates the contents of a context control register140in accordance with one embodiment of the present invention. Context control register140may refer to context control registers77,79,75ofFIG. 4, or context control registers128,130, and132ofFIG. 5. In one embodiment, context control register140is a special purpose 32 bit register that has various different fields which controls the mappings of registers, and holds current, alternate, and saved context information.

Bit0of context control register140corresponds to a context enable field142which enables the use of multiple register contexts. For example, if context enable field142is negated, only a single context is enabled, all other control fields in context control140are ignored, and the current context is set to the default register context (which, in the embodiment illustrated inFIG. 2, is register context034). If the context enable field142is asserted, then multiple contexts are enabled. Bits3–5correspond to a number of contexts field144which is a read only field that indicates the highest context number supported by the hardware. In the example ofFIG. 6, a value of 000 indicates one context is support while a value of 111 indicates that eight register contexts are supported by the hardware. If data processing system10can support more than 8 register contexts, then additional bits can be used for the number of contexts field144. However, in the embodiment ofFIG. 6, it will be assumed that a maximum of 8 register contexts is supported.

Bits6–8correspond to a current context field146which defines the currently enabled register context. In one embodiment, this field is cleared to 0 upon reset to indicate that the default register context is register context0. The current context field146corresponds to the context selector discussed above which may be provided in a variety of different ways, such as by vector offset generator39ofFIG. 2. Therefore, upon a context switch (caused by an interrupt or process switch), the current context field146is set to the new register context as indicated by the context selector. For example, referring toFIG. 5, if data processing system10is currently executing in Process A, then, upon a context switch to Process B, the context selector indicates register context2, and a value of 2 gets written into the current context field of the context control register of register context292.

Note that while each register context has its own context control register, some of the fields may be shared among the different context control registers. For example, a single context enable bit, a single number of contexts field, and a single current context field may be implemented which is used by all the context control registers since the value is always the same among the different context control registers. Alternate embodiments may use a context enable or a number of contexts field or a current context field for each context control register, but by using a single shared field for each reduces hardware requirements.

Bits9–11correspond to a saved context field148which defines the previously enabled context. Note that this field can also be cleared to 0 upon reset. Therefore, in the above example of switching from Process A to Process B (referring toFIG. 5), the current context field is set to 2 (representing register context292) and the saved context field gets set to 1 (representing the previous context, register context190).

Bits12–14correspond to the alternate context field150which defines an alternately enabled context which is used to define a context mapping for register groups. Bits15–18correspond to mapping fields151. Bit15corresponds to a register group A (defined as GPR4–7), bit16to corresponds to register group B (defined as GPR8–11), bit17to register group C (defined as GPR16–23), and bit18to register group D (defined as GPR27–31). Each of the register groups A–D can be independently enabled by asserting the corresponding bit. For example, if bit15is asserted, group A is enabled such that group A is mapped to the register context defined by the alternate context field. If bit15is negated, group A is not mapped. Similarly, if bits16,17, or18are asserted, then the corresponding group of registers (B, C, or D, respectively) is mapped to the register context defined by the alternate context field. If bits16,17, or18are negated, then the corresponding group of registers (B, C, or D, respectively), are not mapped. Therefore, referring toFIG. 5, the context control register of register context190includes a 2 in its alternate context field indicating that the selected group or groups of registers are mapped to register context292. Also, bit16(corresponding to group B having GPR8–11) is asserted such that group104of register context190is mapped to group116of register context292.

In the example context control register, context control register140, ofFIG. 6, a single alternate context field is available and each group (A–D) can be enabled to be mapped to a same alternate register context. That is, if group A is mapped to a particular register context, then groups C–D can only be mapped to the same context. However, in alternate embodiments, each separate grouping of registers (such as groups A–D) can have a corresponding alternate context field such that they can be mapped to different alternate register contexts. Alternatively, a separate alternate context field can be used for groups of groups (e.g. one alternate context field for groups A and B and another for groups C and D). Also, the groups can be defined in any way. For example, each group can have more than or less than four registers, each group can be a single register, or each group can have a different number of registers. Also, in alternate embodiments, more or less groups may be used with more or less alternate context fields. Therefore context control register140ofFIG. 6is only one example. Also, each field may use more or less bits, as needed, to represent the values of the fields. Context control140includes unused bits1,2,19–23, and28–31; however, alternate embodiments may not include any unused bits or may require multiple registers for storing the context control information.

Bit24of context control register140corresponds to a stack pointer context enable field152which enables mapping of the stack pointer, as discussed in reference to bothFIGS. 4 and 5. Bits25–27correspond to a stack pointer context select field154which selects an alternate register context for the stack pointer. Therefore, if bit24is asserted, the stack pointer is mapped to the register context indicated by the stack pointer context select field154; however, if negated, then the stack pointer is not mapped (i.e. it remains from the current context defined by the current context field146). The stack pointer context select field154is a 3 bit value which can indicate which of the 8 register contexts in data processing system10is to be used as the alternate context for the stack pointer. For example, a value of 000 may correspond to register context0and 111 to register context7. Therefore, if the stack pointer context select field154is set to 001, (and stack pointer context enable field152is asserted) then the stack pointer of the current context is mapped to register context1. For example, referring back toFIG. 4, the stack pointer context enable field of the context control register of register context274is asserted and the stack pointer context select field is set to 001 to indicate that the stack pointer register80is mapped to stack pointer register78of register context172. Note also that alternate embodiments may include fields which allow the mapping of other individual registers other than just allowing the sharing of the stack pointer.

The context control register can be programmed in a variety of different ways. For example, in one embodiment, each context control register can be user programmed directly. Alternatively, the context control registers can be mapped indirectly using the alternate context field of the current context control register. For example, in one embodiment, upon power up or reset, data processing system defaults to register context0. The alternate context field can then be set to a value indicating which register context's context control register is to be programmed. For example, while in register context0, a writing of a value of 2 to the alternate context field of the context control register of register context0allows access to the programming of the context control register of register context2via a special purpose register. After all of the context control fields have been programmed, they can all be enabled simultaneously (which, in the case of having a single shared context enable field is done by asserting this bit). Also, in one embodiment, interrupt processing may be turned off during the programming of context control registers.

Note that context control register140has been described in reference to particular fields and bit locations. Note that alternate embodiments may include more or less fields, as needed, and each field may include more or less bits, as needed. Also, in alternate embodiments, context control registers may be located anywhere within data processing system10, or may be located external to data processing system10.

Therefore, it can be appreciated how the context control register can be used to provide for flexible context selection with reduced overhead. Upon a context switch within data processing system10, the context control register of the new register context is updated. For example, the new register context is written to the current context field, the previous context gets written to the saved context field, and the register mappings provided within the mapping fields are used when operating within the new register context. The register mappings allow for different register contexts to share register values. Also, the register mappings allow for access of other register contexts outside the current register context, as defined by the context control register of the current register context. Also, the user programmable context control registers allow for flexibility in how the mappings are defined. Therefore, one aspect of the present invention described herein provides a flexible mechanism to map portions of an alternate register context onto a current register context (and vice versa) and provides for flexible sharing of common stack pointers among multiple contexts, thus resulting in improved real-time performance. By mapping portions of the current context onto an alternate context, the overhead of transferring information values between operating contexts can be removed or eliminated, resulting in improved performance and flexibility.