Power semiconductor device

A power semiconductor having a first, second, third, and fourth semiconductor layer on top of each other, two trench gates parallel and adjacent to each other, each having a trench in the fourth semiconductor layer with the a trench bottom portion reaching into the third semiconductor layer, a gate insulation film lining the trench, and a gate electrode filling the trench being lined with the gate insulation film, two first semiconductor region regions provided contiguously bordering on one side of each of the two trench gates, located at the outer sides of each of the two adjacent trench gates, and located in the top side of the fourth semiconductor layer, a first main electrode on the fourth semiconductor layer, and a second main electrode provided on a bottom of the first semiconductor layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power semiconductor devices having a MOS-gate-metal-oxide semiconductor gate-structure, especially to an insulated gate bipolar transistor used in devices such as invertors that transform or control electric power.

2. Description of the Related Art

In recent years, insulated gate bipolar transistors (hereinafter referred as IGBTs) are utilized, in many cases, as power semiconductor devices including invertors that transform or control electric power. Also, IGBTs are required to obtain larger current capacity (higher withstand voltage) and higher reliability.

FIG. 7is a plane view of an IGBT-chip that is illustrated in Patent Document 1, for example. In the IGBT-chip50illustrated inFIG. 7, a numeral ‘51’ represents an emitter electrode (a first main electrode); ‘52’, a gate pad formed at a concave portion that is provided on a peripheral portion of the emitter electrode51; ‘53’, gate wiring that extends from the gate pad52and is provided on peripheral surface of the emitter electrode51and on the inner surface; thereof so as to divide the emitter electrode51into strips. IGBT cells54having a cellular structure are formed in spaces divided by the gate wire53.

For example,FIG. 8is a partially sectional view along Line A-A of one of the IGBT cells54inFIG. 7, and shows a cellar structure of a general planar-gate-type IGBT illustrated in Non-Patent Document 1. InFIG. 8, a numeral ‘55’ represents a p+collector layer (a first semiconductor layer of a first conductivity type) made of a semiconductor substrate; ‘56’, an n+buffer layer (a second semiconductor layer of a second conductivity type) provided on the top side of the p+collector layer55; ‘57’, an n−layer (a third semiconductor layer of the second conductivity type) provided on the n+buffer layer56; ‘58’, a p base region (a first semiconductor region of the first conductivity type) provided selectively in the top side of the n−layer57; ‘59’, an n+emitter region (a second semiconductor region of the second conductivity type) provided selectively in the top side of the p base region58; ‘60’, a gate insulation film that is made of a dielectric material such as an oxide film and is provided on the n−layer57, partially on the n+emitter region59and on the p base region58therebetween; ‘61’, a gate electrode that is provided on the gate insulation film60and made of a conductive material such as a polysilicon film; ‘62’, an interlayer insulation film that covers the gate electrode61, the gate insulation film60and a portion of the n+emitter region59, and is made of a dielectric material such as a silicate glass (hereinafter, referred as a BPSG); ‘51’, an emitter electrode, shown inFIG. 7, that is made of a conductive material such as aluminum and is provided so as to cover on the interlayer insulation film62, the p base region58and a portion of the n+emitter region59. A numeral ‘63’ represents a collector electrode (a second main electrode) that is provided on the bottom surface of the p+collector layer55and is made of a conductive material such as aluminum. In addition, the gate electrode61is connected to the gate wiring53at the electrode ends provided in its extension orientation (in the front-back orientation with respect to the document face inFIG. 8).

Moreover,FIG. 9is a partially sectional view along Line A-A of the one of IGBT cells54inFIG. 7; the figure shows a cellular structure of a planar-gate-type IGBT that has a terrace gate structure shown in Patent Document 2. A terrace gate portion65is provided on the n−layer57inFIG. 9, which differs fromFIG. 8; whose feature is that the IGBT has a thicker gate insulation film60than that of the average planar-gate-type IGBT. Herewith, the capacity of the gate insulation film becomes smaller, reducing its feedback capacity. In addition, inFIG. 9, the portions that are identical or equivalent to those inFIG. 8are represented by the same numerals as those inFIG. 8so as to omit their explanations.

FIG. 10AandFIG. 10Bare a plane view and a partially sectional view along Line A-A of one of the IGBT cells54inFIG. 7, respectively; the views illustrate a cellular structure of a trench-gate-type IGBT including a trench that does not work as gate (hereinafter, referred as a dummy trench); the views illustrate, for example, the equivalent IGBT described in Patent Document 2.FIG. 10Ashows the IGBT structure, in which the emitter electrode51is removed for easy understanding. InFIG. 10, the p+collector layer55, the n+buffer layer56, the n−layer57, the emitter electrode51and the collector electrode63are the portions that are identical or equivalent to those shown inFIG. 8, so that they will be represented by the same numerals as those inFIG. 8so as to omit their explanations. A numeral ‘66’ represents a p base layer (a fourth semiconductor layer of the first conductivity type) provided on the n−layer57; a numeral ‘67’ represents a trench gate that extends from the top of the p base layer66and reaches the n−layer57; the trench gate67includes a trench67a, a gate insulation film67bthat lines the trench67aand is made of a dielectric material such as an oxide film, and a gate electrode67cthat is provided to fill the trench67abeing lined with the gate insulation film67band is made of a conductive material such as polysilicon. A numeral ‘68’ represents a dummy trench that extends from the top of the p base layer66and reaches the n−layer57; the dummy trench68includes a trench68a, a gate insulation film68bthat lines the trench68aand is made of a dielectric material such as an oxide film, and a dummy electrode68cthat is provided to fill the trench68abeing lined with the gate insulation film68band is made of a conductive material such as polysilicon so as to be electrically connected to the emitter electrode51. A numeral ‘69’ represents an n+emitter region provided in the top of the p base layer66, contiguously bordering on both sides of the trench gate67; a numeral ‘70’, an interlayer insulation film that covers a portion of the n+emitter region69and the trench gate67; the numeral ‘51’, the emitter electrode shown inFIG. 7that covers uncovered portions of the interlayer insulation film70, the p base layer66, the dummy trench68and the n+emitter region69. With the dummy trenches being provided, current flowing into the IGBT chip50due to short circuits can be curbed, which enables the device to secure a short circuit safe operation area (hereinafter, referred as SCSOA) and is effective for increasing current capacity of the device. Here, the end of the gate electrode67cis connected to the gate wiring53.

Patent Documentation 1

Patent Documentation 2

An IGBT that is a conventional power semiconductor device has been configured as described above; recently, it is required that IGBTs obtain larger current capacity (higher withstand voltage) and higher reliability; the following problems have now drawn attention in order to meet those requirements.

In the IGBT chip50, in order to reduce each gate resistance (represented as ‘R’ inFIG. 7) of the gate electrodes61and67cformed of a conductive material such as polysilicon, the gate wiring53formed of a conductive material such as aluminum is provided as shown inFIG. 7, so as to divide the emitter electrode51into strips. In order to cope with larger current capacity and higher reliability, the number of wires that are made of a conductive material such as aluminum and bonded to the emitter electrode51tends to increase in an IGBT package where the IGBT chip50is mounted. Therefore, in order to enhance the reliability of the wire-bonding, it is necessary to enlarge areas for each strip of the emitter electrode51by giving more spaces between the gate wiring53; however, enlarging the areas meanwhile causes big difference between the gate resistances of the gate electrodes61and67c, as have been described above. More specifically, in the IGBT cells54, when a cell is located near to the gate wiring53, the gate resistance thereof becomes small; when it is located apart from the gate wiring53(for example, located at the intermediary point between the gate wiring), the gate resistance thereof becomes large. Therefore, when the IGBT chip turns off, a current supplied to one of the IGBT cells54close to the gate wiring53and a current supplied to another one of the IGBT cells54apart from the gate wiring are not balanced (hereinafter, referred as imbalance among current diversions); then, currents are concentrated on such IGBT cells54that are located apart from the gate wiring53and whose turning off speed becomes slow, so that the IGBT cells generate heat; therefore, turn-off withstand ability, that is, a reverse-biased safe operating area (hereinafter, referred as RBSOA), becomes reduced.

As a means for reducing the gate resistance of the gate electrodes61and67c, it is considered to use doped polysilicon that is a polysilicon—the material of the gate electrodes61and67c—doped with impurities in order to reduce their resistance. However, when doped silicon is used for the gate electrode61of the planar-gate-type IGBT shown inFIG. 8andFIG. 9, auto-doping of impurities, with which a polysilicon has been doped, into the gate insulation film60and the n−layer57occurs, adversely affecting the gate-emitter leakage current and the primary-voltage-to-leakage-current characteristics. Also, when doped silicon is used for the gate electrode67cof the trench-gate-type IGBT shown inFIG. 10, because the width of the trench gate is formed very narrow, the cross-sectional area of the gate electrode67cbecomes small. Therefore, in the above-described case where the spaces between the gate wiring53become wider, the gate resistances increase, causing the imbalance among current diversions to occur, so that its turn-off withstand ability will be reduced.

SUMMARY OF THE INVENTION

The present invention is aimed to solve the problems above-described; an object thereof is, even when the spaces between the gate wiring53become wide, to provide a power semiconductor device that can meet requirements for larger current capacity and higher reliability while improving imbalance among current diversions.

A power semiconductor device according to the present invention includes a second semiconductor layer of a second conductive type, provided on a top side of a first semiconductor layer of a first conductivity type; a third semiconductor layer of the second conductivity type, provided on the second semiconductor layer; a first semiconductor region of the first conductivity type, provided selectively in a top side of the third semiconductor layer; a second semiconductor region of the second conductivity type, provided selectively in a top side of the first semiconductor region; a gate insulation film provided on the third semiconductor layer, on the first semiconductor region, and partially on the second semiconductor region; a gate electrode provided on the gate insulation film; a first main electrode that is provided on the first semiconductor region and is electrically connected with the second semiconductor region; and a second main electrode provided on a bottom side of the first semiconductor layer. Also, the gate electrode includes a polysilicon film provided on the gate insulation film, and a doped polysilicon film doped with impurities that is provided on the polysilicon film.

According to the present invention, because a power semiconductor device is configured so as to have a gate electrode including a polysilicon film provided on a gate insulation film, and a doped polysilicon film—a polysilicon doped with impurities to reduce its resistance—that is provided on the polysilicon film; the gate resistance of the gate electrode can be reduced in comparison to conventional ones. Therefore, the imbalance among current diversions at turn-off is improved so as not to reduce turn-off withstand ability of the device. In addition, because a polysilicon film not doped with impurities is provided between a doped polysilicon film and a gate insulation film, it is possible to preclude auto-doping of impurities, which might be feared by providing with the doped polysilicon film, into the gate insulation film and an n−layer from adversely affecting gate-emitter leakage current and collector-emitter leakage current. Therefore, a power semiconductor device that meets requirements for increased current capacity and higher reliability can be obtained.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiment 1 according to the present invention will be explained below.FIG. 1is a partial cross-sectional view illustrating a planar-gate-type IGBT that is a power semiconductor device according to Embodiment 1 of the present invention; the figure illustrates, taking along the line A-A, a cross-sectional cellar structure of the IGBT cells54shown inFIG. 7.FIG. 1differs fromFIG. 8that represents prior art as follows; a gate electrode includes a polysilicon film1aprovided on the gate insulation film60, and a doped polysilicon film1bthat is doped with impurities and provided on the polysilicon film1a; the gate electrode1is connected to the gate wiring53at the electrode ends provided in its extension orientation (in the front-back orientation with respect to the document face inFIG. 1). Because the other components are identical or equivalent to those inFIG. 8, the same numerals will be used so as to omit their explanations.

According to the structure shown inFIG. 1, because the gate electrode includes the polysilicon film1aprovided on the gate insulation film60, and the doped polysilicon film1bthat is doped with impurities to reduce its resistance and is provided on the polysilicon film1a, the gate resistance of the gate electrode1can be reduced in comparison to conventional ones. Therefore, the difference between the gate resistance of a first one of the IGBT cells54close to the gate wiring53and that of a second one of the IGBT cells54apart from the gate wiring (for example, being located at the intermediary point between the gate wiring) becomes small. Therefore, when the IGBT cells54turn off, the imbalance between a current supplied to the first one of the IGBT cells54close to the gate wiring53and a current supplied to the second one of the IGBT cells54apart from the gate wiring53is improved; because currents are not concentrated at the second one of the IGBT cells54apart from the gate wiring53, the IGBT cell does not generate heat, so as to prevent its turn-off withstand ability from reducing.

In addition, because the polysilicon film1anot doped with impurities is provided between the doped polysilicon film1band the gate insulation film60, the impurities contained in the doped polysilicon film1bare prevented from naturally diffusing, namely, auto-doping into the gate insulation film60and the n−layer57. Therefore, it is possible to preclude expected influence of auto-doping on gate-emitter leakage current and collector-emitter leakage current.

Even when the spaces between the gate wiring53become wide, because improvement in imbalance among current diversions prevents the turn-off withstand ability from reducing and, in addition, because it is possible to preclude, by curbing auto-doping of the impurities, expected influence on gate-emitter leakage current and collector-emitter leakage current, a planar type IGBT that meets requirements for increased current capacity (higher withstand voltage) and higher reliability can be obtained.

In Embodiment 1, a gate electrode1has been explained, in which the gate electrode1is configured with the polysilicon film1aprovided on the gate insulation film60, and the doped polysilicon film1bthat is doped with impurities to reduce its resistance and is provided on the polysilicon film1a. One ofFIG. 2is a partially enlarged view for explaining Embodiment 2; the figure corresponds to a view in which the gate electrode1inFIG. 1is partially enlarged. Embodiment 2 differs from Embodiment 1 in that gradient of concentration with respect to impurities is provided in the doped polysilicon film1b. More specifically, as distribution of its impurity concentration shown in the middle view ofFIG. 2, the impurity concentration is made to vary in a thickness direction of the doped polysilicon film1b; at the top portion of the doped polysilicon1b, the value of impurity concentration takes its maximum value; the value becomes smaller heading thickness-wise toward the polysilicon film1a; at the bottom portion of the doped polysilicon film1b, which is contiguous with the polysilicon, the value takes its lowest value or zero. In addition, in the figure, the portions that are identical or equivalent to those inFIG. 8are represented by the same numerals as those inFIG. 8so as to omit their explanations.

Using the structure shown inFIG. 2, the resistance of the gate electrode1becomes distributed as shown in the right view ofFIG. 2; the doped silicon film1bhas at its top area a portion in which its resistance is reduced, which prevents the turn-off withstand ability from reducing as in the case of Embodiment 1.

In addition, because at the bottom portion of the doped polysilicon film1b, which is contiguous with the polysilicon1a, the value takes its lowest value or zero, the impurities contained in the doped polysilicon film1bare prevented much more than Embodiment 1, from diffusing naturally, namely, auto-doping into the gate insulation film60and the n−layer57. Therefore, it is possible to further preclude expected influence of auto-doping on gate-emitter leakage current and collector-emitter leakage current.

Therefore, even when the spaces between the gate wiring53become wide, because improvement in imbalance among current diversions prevents the turn-off withstand ability from reducing and it is possible to preclude expected influence on gate-emitter leakage current and collector-emitter leakage current by curbing auto-doping of the impurities, a planar type IGBT that meets requirements for increased current capacity (higher withstand voltage) and higher reliability, can be obtained.

The gate electrode1configured with a polysilicon film1aand a doped polysilicon1bthat have been explained in Embodiment 1, is also applicable to a planar-gate-type IGBT that has a terrace gate structure shown inFIG. 9.FIG. 3is a partial cross-sectional view illustrating a planar-gate-type IGBT that is a power semiconductor device having the terrace gate structure, according to Embodiment 3 of the present invention; the figure illustrates, taking along the line A-A, a cellar structure of the IGBT cells54shown inFIG. 7.FIG. 3differs fromFIG. 9explaining a conventional device, as follows; a terrace gate portion65of a gate electrode2is configured with a polysilicon film2aprovided on a gate insulation film60, and with the doped polysilicon film2bthat is provided on the polysilicon film2aand is doped with impurities to reduce its resistance. In addition, the gate electrode2is connected to the gate wiring53at the electrode ends provided in its extension orientation (in the front-back orientation with respect to the document face inFIG. 3). Because the other components are identical or equivalent to those inFIG. 8andFIG. 9, the same numerals will be used so as to omit their explanations.

According to the structure shown inFIG. 3, because the terrace gate portion65of the gate electrode2is configured with the polysilicon film2aprovided on the gate insulation film60, and with the doped polysilicon film2bthat is provided on the polysilicon film2aand is doped with impurities to reduce its resistance, the gate resistance of the gate electrode2can be reduced in comparison to that of conventional devices. Therefore, as is the case with Embodiment 1, the turn-off withstand ability of the device can be prevented from reducing.

Also, as is the case with Embodiment 1, the impurities contained in the doped polysilicon film2bare prevented from diffusing naturally, namely, auto-doping into the gate insulation film60and the n−layer57. Therefore, it is possible to preclude expected influence of auto-doping on gate-emitter leakage current and collector-emitter leakage current.

Therefore, even when the spaces between the gate wiring53become wide, because improvement in imbalance among current diversions prevents the turn-off withstand ability from reducing and, in addition, because it is possible to further preclude expected influence on gate-emitter leakage current and collector-emitter leakage current by curbing auto-doping of the impurities, a planar type IGBT that meets requirements for increased current capacity (higher withstand voltage) and higher reliability, can be obtained.

In Embodiment 3, a terrace gate has been explained, as follows; the terrace gate portion65of the gate electrode2is configured with the polysilicon film2aprovided on the gate insulation film60, and with the doped polysilicon film2bthat is provided on the polysilicon film2aand is doped with impurities to reduce its resistance. In the doped polysilicon film2b, the value of impurity concentration may vary in a similar fashion to that of Embodiment 2. In this case, as is the case with Embodiment 2, because the turn-off withstand ability is prevented from reducing and the impurities contained in the doped polysilicon film2bare prevented from diffusing naturally, namely, auto-doping into the gate insulation film60and the n−layer57, it is possible to preclude expected influence of auto-doping on gate-emitter leakage current and collector-emitter leakage current. Therefore, a planar-gate-type IGBT can be obtained that meets requirements for increased current capacity and higher reliability.

Embodiment 5 according to the present invention will be explained below.FIG. 4AandFIG. 4Bare a plane view and a partially sectional view along Line A-A of one of the IGBT cells54inFIG. 7, in which the figures illustrate a cellular structure of a trench-gate-type IGBT that is a power semiconductor device including a dummy trench, according to Embodiment5of the present invention.FIG. 4Ashows the trench-gate-type IGBT structure, in which the emitter electrode51is removed for easy understanding. InFIG. 4, components, such as the p+collector layer55(a first semiconductor layer of a first conductivity type), the n+buffer layer56(a second semiconductor layer of a second conductivity type), the n−layer.57(a third semiconductor layer of the second conductivity type), the emitter electrode51(a first main electrode), the collector electrode63(a second main electrode), the p base layer66(a fourth semiconductor layer of the first conductivity type), and the dummy trench68(the trench68a, the insulation film68b, and the dummy electrode68c), are identical or equivalent to those inFIG. 10, the same numerals will be used for the components so as to omit their explanation. Numerals ‘3’ and ‘4’ represent two trench gates that are provided in parallel and adjacent to each other and extend from the top of the p base layer66with the trench bottom portion reaching the n−layer57. The two trench gates3and4include trenches3aand4a; gate insulation films3band4bthat line the trenches3aand4aand are made of a dielectric material such as an oxide film; and gate electrodes3cand4cthat are provided to fill the trenches3aand4abeing lined with the gate insulation films3band4band are made of a conductive material such as polysilicon. A numeral ‘6’ represents n+emitter regions (first semiconductor regions of the second conductivity type) each of which is provided in the top of the p base layer66, contiguously bordering on only one side of each of the two trench gates3and4. InFIG. 4, in order to dispose the two trench gates3and4close to each other, the n+emitter regions6are provided on both outer sides of the two trench gates3and4. A numeral ‘7’ represents an interlayer insulation film that covers a portion of the n+emitter regions6and the two trench gates3and4; the numeral ‘51’, the emitter electrode shown inFIG. 7that covers uncovered portions of the interlayer insulation film7, the p base layer66, the dummy trench68and the n+emitter regions6. In addition, the gate electrodes3cand4care connected to the gate wiring53at the electrode ends provided in their extension orientation (in the top-bottom orientation of the document inFIG. 4A, or in the front-back orientation with respect to the document face inFIG. 4B).

According to the structure shown inFIG. 4, the n−layer6is provided, contiguously bordering on only one side of each of the two trench gates3and4that are provided in parallel and adjacent to each other, and in the top of the p base layer66; the two trench gates3and4come into operation as if they were one trench gate so as to substantially increase the cross-sectional area of the gate electrode; more specifically, the cross-sectional area of the gate electrode is increased to be the sum of the areas of the gate electrode3cof the trench gate3and the gate electrode4cof the trench gate4; the gate resistance can be resultantly reduced in comparison to a conventional one. Therefore, the difference between the gate resistance of the first one of the IGBT cells54close to the gate wiring53and that of the second one of the IGBT cells54apart from the gate wiring53(for example, being located at the intermediary point between the gate wiring) becomes small. Therefore, when the IGBT cells turn off, the imbalance between the first one of the IGBT cells54close to the gate wiring53and the second one of the IGBT cells54apart from the gate wiring53is improved; because currents are not concentrated at the second one of the IGBT cells54apart from the gate wiring53, the IGBT cell does not generate heat, so as to prevent its turn-off withstand ability from reducing.

In addition, because the n+emitter regions6are provided on one side of the two trench gates3and4each, n channel regions emerge only on the one side of each of the gates at turning-off. Therefore, because current loss can be kept low at short circuit, the short circuit safe operation area can be secured even in a case without the dummy trench68. Furthermore, provision of the dummy trench68further secures the short circuit safe operation area.

Therefore, even when the spaces between the gate wiring53become wide, because improvement in imbalance among current diversions prevents the turn-off withstand ability from reducing, a trench-gate-type IGBT to meet requirements for increased current capacity and higher reliability can be obtained. Furthermore, provision of the dummy trenches can further secure the short circuit safe operation area; a trench-gate-type IGBT that meets requirements for more increased current capacity and higher reliability can be obtained.

Embodiment 6 according to the present invention will be explained below.FIG. 5AandFIG. 5Bare a plane view and a partially sectional view along Line A-A of one of the IGBT cells54shown inFIG. 7, in which the figures illustrate a cellular structure of a trench-gate-type IGBT that is a power semiconductor device according to Embodiment 6 of the present invention.FIG. 5Ashows the trench-gate-type IGBT structure, in which the emitter electrode51is removed for easy understanding. InFIG. 5, components such as the p+collector layer55(the first semiconductor layer of the first conductivity type), the n+buffer layer56(the second semiconductor layer of the second conductivity type), the n−layer57(the third semiconductor layer of the second conductivity type), the emitter electrode51(the first main electrode), the collector electrode63(the second main electrode), and the p base layer66(the fourth semiconductor layer of the first conductivity type) are identical or equivalent to those inFIG. 10, the same numerals will be used for the components so as to omit their explanation. A numeral ‘8’ represents a trench gate that extends from the top of the p base layer66and reaches the n−layer57; the trench gate8includes a trench8a, a gate insulation film8bthat lines the trench8aand is made of a dielectric material such as an oxide film, and a gate electrode8cthat is provided to fill the trench8abeing lined with the gate insulation film8band made of a conductive material such as polysilicon. A numeral ‘9’ represents an n+emitter region (the first semiconductor region of the second conductivity type) which is provided in the top of the p base layer66, contiguously bordering on only one side of the trench gate8; a numeral ‘10’, an interlayer insulation film that covers a portion of the n+emitter region9and the trench gate8; a numeral ‘51’, the emitter electrode shown inFIG. 7that covers uncovered portions of the interlayer insulation films10, the p base layer66, and the n+emitter regions9. In addition, the gate electrodes8cis connected to the gate wiring53at the electrode ends provided in its extension orientation (in the top-bottom orientation of the document inFIG. 5A, or in the front-back orientation with respect to the document face inFIG. 5B).

According to the structure shown inFIG. 5, the n+emitter region9is provided in the top of the p base layer66, contiguously bordering on only one side of the trench gate8; therefore, a current supplied to the gate electrode8can be reduced in comparison to that of conventional devices, the cross-sectional area of the gate electrode8cof the trench gate8becomes substantially increased, so that the gate resistance of the trench gate8can be reduced in comparison to conventional ones. Therefore, the difference between the gate resistance of the first one of the IGBT cells54close to the gate wiring53and that of the second one of the IGBT cells54apart from the gate wiring53(for example, being located at the intermediary point between the gate wiring) becomes small. Therefore, when the IGBT cells turn off, imbalance between the first one of the IGBT cells54close to the gate wiring53and the second one of the IGBT cells54apart from the gate wiring53is improved; because currents are not concentrated at the second one of the IGBT cells54apart from the gate wiring53, the IGBT cell does not generate heat, so as to prevent its turn-off withstand ability from reducing.

In addition, because the n+emitter region9is provided on one side of the trench gate8, an n channel region emerges only on the one side of the trench at turning-off. Therefore, because current loss to short circuit can be curbed to be low, the short circuit safe operation area can be secured. Provision of the dummy trench68described in Embodiment 5 can further secure the short circuit safe operation area.

Therefore, even when the spaces between the gate wiring53become wide, because improvement in imbalance among current diversions prevents the turn-off withstand ability from reducing, a trench-gate-type IGBT to meet requirements for increased current capacity and higher reliability can be obtained. Provision of the dummy trenches can secure the short circuit safe operation area, so that a trench-gate-type IGBT that meets requirements for more increased current capacity and higher reliability can be obtained.

In Embodiment 6, the n+emitter region9is provided in the top of the p base layer66, contiguously bordering on only one side of the trench gate8; the same effects as those in Embodiment 6 can be obtained as long as the n+emitter region9is provided contiguously bordering on only one side of the trench gate8. As is shown inFIG. 6, for example, the n+emitter region9may be provided such that a first n+emitter region9aand a second n+emitter region9b, each having a predetermined length, are provided in the top of the p base layer66, contiguously bordering on the trench gate8, paralleling the trench gate extension orientation, and being staggered on either side of the trench gate(inFIG. 6A, in the top-bottom orientation of the document, or inFIG. 6B and 6C, in the front-back orientation with respect to the document face).FIG. 6Ais a plane view of one of the IGBT cells54shown inFIG. 7, andFIG. 6BandFIG. 6care partially sectional views along Line B-B and Line C-C inFIG. 6A, respectively. In addition, inFIG. 6, the portions that are identical or equivalent to those inFIG. 5explained in Embodiment6are represented by the same numerals so as to omit their explanations.