Method and apparatus for partial word read through ECC block

A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits. The undriven check bits and undriven data bits are preferably forced to the predefined state using a plurality of respective pull-up resistors.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention generally relates to computer systems, particularly 
to a method of transmitting information between different components in a 
computer system, such as between a system memory device and a central 
processing unit, and more specifically to a method and apparatus for 
reading a partial word through an error-correcting code (ECC) circuit. 
2. Description of Related Art 
A typical structure for a conventional computer system includes one or more 
processing units connected to a system memory device (random access memory 
or RAM) and to various peripheral, or input/output (I/O), devices such as 
a display monitor, a keyboard, a graphical pointer (mouse), and a 
permanent storage device (hard disk). The system memory device is used by 
a processing unit in carrying out program instructions, and stores those 
instructions as well as data values that are used or generated by the 
programs. A read-only memory device (ROM) is used to provide firmware 
whose primary purpose is to seek out and load an operating system from one 
of the peripherals (usually the permanent storage device) whenever the 
computer is first turned on. A processing unit communicates with the other 
components by various means, including one or more interconnects (buses), 
or direct memory-access channels. A computer system may have many 
additional components, such as serial and parallel ports for connection 
to, e.g., printers, and network adapters. Other components might further 
be used in conjunction with the foregoing; for example, a display adapter 
might be used to control a video display monitor, a memory controller can 
be used to access the system memory, etc. 
An exemplary computer system 10 is illustrated in FIG. 1. System 10 
includes a central processing unit (CPU) 12, firmware or read-only memory 
(ROM) 14, and a dynamic random access memory (DRAM) 16 which are all 
connected to a system bus 18. CPU 12, ROM 14 and DRAM 16 are also coupled 
to a peripheral component interconnect (PCI) local bus 20 using a PCI host 
bridge 22. PCI host bridge 22 provides a low latency path through which 
processor 12 may access PCI devices mapped anywhere within bus memory or 
I/O address spaces. PCI host bridge 22 also provides a high bandwidth path 
to allow the PCI devices to access DRAM 16. 
Attached to PCI local bus 20 are a local area network (LAN) adapter 24, a 
small computer system interface (SCSI) adapter 26, an expansion bus bridge 
28, an audio adapter 30, and a graphics adapter 32. Lan adapter 24 is used 
to connected computer system 10 to an external computer network 34. SCSI 
adapter 26 is used to control high-speed SCSI disk drive 36. Expansion bus 
bridge 28 is used to couple an ISA (Industry Standard Architecture) 
expansion bus 38 to PCI local bus 20. As shown, several user input devices 
are connected to ISA bus 38, including a keyboard 40, a microphone 42, and 
a graphical pointing device (mouse) 44. Other devices may also be attached 
to ISA bus 38, such as a CD-ROM drive 46. Audio adapter 30 controls audio 
output to a speaker 48, and graphics adapter 32 controls visual output to 
a display monitor 50. 
Parity checks and error-correction codes (ECC's) are commonly used to 
ensure that data is properly transferred between system components. For 
example, a magnetic disk (permanent memory device) typically records not 
only information that comprises data to be retrieved for processing (the 
memory word), but also records an error-correction code for each file, 
which allows the processor, or a controller, to determine whether the data 
retrieved is valid. ECC's are also used with temporary memory devices, 
e.g., DRAM or cache memory devices, and the ECC for files stored in DRAM 
can be analyzed by a memory controller which provides an interface between 
the processor and the DRAM array. If a memory cell fails during reading of 
a particular memory word (due to, e.g., stray radiation, electrostatic 
discharge, or a defective cell), then the failure can at least be detected 
so that further action can be taken. ECC's can further be used to 
reconstruct the proper data stream. 
Some error correction codes can only be used to detect single-bit errors; 
if two or more bits in a particular memory word are invalid, then the ECC 
might not be able to determine what the proper data stream should actually 
be. Other ECC's are more sophisticated and allow detection or correction 
of double errors, and some ECC's further allow the memory word to be 
broken up into clusters of bits, or "symbols," which can then be analyzed 
for errors in even more detail. 
One limitation of ECC circuits relates to the fact that they are always 
designed to receive and analyze a memory word of a fixed width. In a 
computer system such as that shown in FIG. 1, DRAM 16 might provide a 
64-bit data word (eight 8-bit bytes), with an additional 8-bit check word 
used for error correction (i.e., a total of 72 bits). Therefore, if an ECC 
circuit were implemented in an interconnection between the DRAM and some 
other component (such as CPU 12), then the ECC circuit would necessarily 
be constructed to specifically conform to the 72-bit format. The presence 
of an ECC circuit in this communications path, however, prevents other 
devices from using the path if they do not utilize the same word format. 
In other words, a problem exists where a memory word having a width less 
than the fixed width is to be read through the ECC block. 
For example, in the system of FIG. 1, ROM 14 transmits single-byte data (8 
bits). If ROM data were to pass through an ECC block adapted for DRAM 16, 
then the check word and the remaining data bits expected by the ECC block 
would be undefined. In this situation, one of three results can occur 
within the ECC block (depending upon the ROM value): no error is detected; 
a single-bit error is detected; or a multiple-bit error is detected. The 
case of "no error detected" is possible where the undefined signals input 
into the ECC block, along with the ROM byte, exactly match a "no error" 
pattern. This result will leave the ROM data bits unaffected, and 
therefore does not present a problem. In the case of "multiple-bit error 
detected," the undefined signals do not match the "no error" pattern, but 
the data is passed through unmodified anyway (including the ROM data), 
since the ECC block cannot determine which bits require correction, so 
this case also does not present a problem. However, in the case of 
"single-bit error detected," while the undefined signals do not match the 
"no error" pattern, the error-correction code presumes that the memory 
word has a single-bit error which can be corrected and, as a consequence, 
the ECC circuitry will modify the imagined 64-bit memory word, by 
complementing one of these 64 bits. If the modified bit is within the ROM 
data bits, a ROM corruption will appear to the reading device (e.g., CPU 
12), which could lead to catastrophic failure of the system. 
One solution to the foregoing problem is to simply make all devices which 
use a common ECC block operate at the same granularity, that is, with the 
same memory word size. This solution is not, however, always feasible. For 
example, considering again the use of an ECC block which passes data from 
both a DRAM device and a ROM device, this approach would require the use 
of a 72-bit ROM, which is quite expensive compared to 8-bit ROMs. In light 
of the foregoing, it would be desirable to devise a method of passing 
different sizes of memory words through a common ECC block. It would be 
further advantageous if the method could be implemented at a relatively 
low cost and with less load on the CPU bus. 
SUMMARY OF THE INVENTION 
It is therefore one object of the present invention to provide an improved 
computer system having error-correction and detection in transmission of 
data between system components. 
It is another object of the present invention to provide such a computer 
system wherein error-correction code (ECC) circuitry can be established in 
a single communications path used by devices having different memory word 
sizes, such as an 8-bit ROM and a 72-bit RAM. 
It is yet another object of the present invention to provide a simple and 
inexpensive method of constructing such a compliant ECC block. 
The foregoing objects are achieved in a method of communicating between 
components in a computer system, generally comprising the steps of 
providing a communications path between a first component of the computer 
system (such as a random-access memory (RAM) device) and a second 
component of the computer system (such as a central processing unit 
(CPU)), wherein the first component transmits data to the second component 
using a first granularity, and wherein the communications path includes an 
error-correction code (ECC) circuit adapted to detect and correct parity 
errors transmitted from the first component to the second component, 
interconnecting a third component to the communications path (such as a 
read-only memory (ROM) device) such that the third component may transmit 
data to the second component using a second granularity which is smaller 
than the first granularity, and merging data from the third component with 
predefined data to present a merged data word to the ECC circuit, the 
merged data word having the first granularity. The first granularity may 
be, e.g., 72 bits, while the second granularity is 8 bits. The data is 
merged by forcing undriven check bits and undriven data bits in the ECC 
block to a predefined state such that error correction of the merged data 
word by the ECC circuit results in modification of the predefined data and 
not in modification of the data from the third component. The undriven 
check bits and undriven data bits are preferably forced to the predefined 
state using a plurality of respective pull-up resistors. 
The above as well as additional objectives, features, and advantages of the 
present invention will become apparent in the following detailed written 
description.