Method and apparatus for reduced power cell

The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input to the cell. The reduced voltage reduces the current leakage of the electronic components within the cell. Some embodiments provide a memory circuit that has a level converter. The level converter receives a reduced voltage and converts the reduced voltage into values that can be used to store and retrieve data with stability in the cell. Some embodiments provide a method for storing data in a memory circuit that has a storage cell. The method applies a reduced voltage to the input of the cell. The method level converts the reduced voltage. The reduced voltage is converted to a value that can be used to store and retrieve data with stability in the cell. The reduced voltage reduces a current leakage of electronic components within the cell.

CROSS REFERENCE TO RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 11/081,870, filed Mar. 15, 2005.

FIELD OF THE INVENTION

The present invention relates to reduced power cells.

BACKGROUND OF THE INVENTION

Volatile memory circuits are quite common today. Such memory circuits can be contained in an individual integrated circuit (IC) chip or can be part of other IC's. These IC's include a configurable IC that uses a memory circuit to store configuration data. The configurable IC can be configured to perform a set of operations based on the stored configuration data.

The use of configurable IC's has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (FPGA). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects) and that are surrounded by input/output blocks. Like some other configurable IC's, the logic circuits and the interconnect circuits of an FPGA are configurable. In other words, each of these circuits receives configuration data that configures the circuit to perform an operation in a set of operations that it can perform. One benefit of configurable IC's is that they can be uniformly mass produced and then subsequently configured to perform different operations.

As mentioned above, configurable IC's typically store their configuration data in memory cells.FIG. 1illustrates a memory circuit100of a configurable IC. As shown in this figure, the memory circuit100includes: (1) a storage cell128for storing a configuration data value; (2) a VDDcell line106for supplying power to the storage cell128; (3) true and complement bit lines110and115for reading and/or writing the contents of the storage cell128; (4) pass gates120and125for connecting the bit lines110and115to the storage cell128; and (5) output lines160and165for outputting, through configuration buffers140and145, the contents of the storage cell128without the need for a read operation.

The typical storage cell128in the art requires that the voltage within the cell128and through the buffers140and145be driven to the rails in order for the cell128to retain stable values and output a useable configuration value (i.e., VDDcell106is typically VDD). If the voltage within the storage cell128is less than the voltage on a word line used to read the cell, then a read operation could cause instability in the value stored by the storage cell128by undesirably altering the value stored in the storage cell128. This condition is also known as “read upset.”

However, requiring the voltage within the cell128and through the buffers140and145to be driven to the rails exasperates current leakage from the cell, since current leakage from the memory cell is non linearly (e.g., exponentially) proportional to the voltages that are used to store data in the memory cell. Specifically, in the memory cell100there are two kinds of leakage that are problematic: sub threshold leakage and gate leakage.

FIG. 2illustrates an example of sub threshold leakage through an NMOS transistor200that is commonly used in memory circuits. InFIG. 2, the gate and source leads of the NMOS transistor200are short circuited to represent that their voltage difference is zero (i.e., Vg−s=0). Even though the transistor is “off” in this sub threshold condition, there is still undesirable leakage current through the transistor200, as shown inFIG. 2.

FIG. 3illustrates an example of gate leakage through an NMOS transistor305. Electron tunneling through the gate oxide of a transistor causes gate leakage current. For a 90 nm electronic component (e.g., a transistor), gate oxide can be about fourteen angstroms or approximately seven silicon dioxide atoms thick. This distance is sufficiently short to allow tunneling current to flow through the gate oxide even at voltage levels as low as one volt. Gate leakage in N-channel devices is significantly worse than in P-channel devices.

With the size of electronic components continually becoming smaller due to improvements in semiconductor technology, leakage current is a continually growing problem. Leakage current in a standard (six transistor) memory cell is exponentially proportionate to voltage. So if the voltage in the cell can be reduced, then the amount of leakage (i.e., both gate and sub threshold leakage) in the cell can be exponentially reduced. However, a typical memory cell has particular voltage requirements in order for the cell to function properly. Thus, if the voltage within the cell is reduced too much, then the cell becomes unstable and unable to store and output data reliably, as seen in the case of the read upset condition. Thus, there is a need in the art for a useable reduced power configuration storage cell, such that the leakage from electronic components within the cell is reduced, while retaining useable output configuration signals.

SUMMARY OF THE INVENTION

The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input to the cell. The reduced voltage reduces the current leakage of the electronic components within the cell. Some embodiments provide a memory circuit that has a level converter. The level converter receives a reduced voltage and converts the reduced voltage into values that can be used to store and retrieve data with stability in the cell. Some embodiments provide a method for storing data in a memory circuit that has a storage cell. The method applies a reduced voltage to the input of the cell. The method level converts the reduced voltage. The reduced voltage is converted to a value that can be used to store and retrieve data with stability in the cell. The reduced voltage reduces a current leakage of electronic components within the cell.

DETAILED DESCRIPTION OF THE INVENTION

The invention is directed towards reduced power static random access memory (SRAM) cells. In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. For instance, the invention has primarily been described with reference to the storage cells for volatile memory (e.g., SRAM) in a configurable IC. However, the same techniques can easily be applied for other types of memory and electronic circuits. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.

I. Reduced Power Memory Cell

To address the problems of current leakage present in memory cells, some embodiments provide a memory circuit400illustrated inFIG. 4that includes a reduced power storage cell428. During normal operation, the reduced power storage cell428is supplied with a lower voltage so that it will leak less current, and therefore consume less power than the storage cells known in the art. Moreover, the reduced power storage cell428outputs through an amplifier circuit438, which also leaks less current than the buffers in the art.

As shown inFIG. 4, the memory circuit400includes a word line405, a VDDcell line406, a bit line410, a complement bit line415, pass gates420and425, a reduced power storage cell428, and an amplifier stage438. In some embodiments, the pass gates420and425are NMOS transistors that connect the bit line410and the complement bit line415to the storage cell428when the signal on the word line405is high.

The pass gates420and425enable writes to, and reads from, the storage cell428. During a read operation, the value in the storage cell428is “read” out onto the bit line410and the complement bit line415(hereinafter also referred to as the bit lines). Specifically, for the read operation of some embodiments, the voltages stored at the nodes426and427pass through the pass gates420and425to affect the voltages on the bit lines410and415. In some embodiments, the bit lines410and415are precharged and then allowed to float high in anticipation of a read operation. Also during a read operation, a sense amplifier (not shown inFIG. 4) monitors the bit lines410and415to sense or “read” the value stored in the storage cell428through the bit lines410and415.

During a write operation, the values on the bit lines410and415are “written” into the storage cell428. Specifically, for the write operation of some embodiments, voltages on the bit lines410and415pass through the pass gates420and425to alter the voltages stored at the nodes426and427. As shown inFIG. 4, some memory cells require a true configuration signal and its complement signal (provided by the bit lines410and415) for the memory circuit400to execute reliable read and write operations. In these embodiments, the bit lines410and415are precharged, then one is pulled low to effect differential signals for the write operation.

FIG. 4illustrates that the reduced power storage cell428of some embodiments is formed by cross coupling a pair of standard complementary metal oxide semiconductor (CMOS) inverters. These CMOS inverters are cross-coupled in that the output of the first inverter is coupled to the input of the second inverter and the output of the second inverter is coupled to the input of the first inverter.

The cut-out inFIG. 4illustrates the cross coupled transistors of two standard CMOS inverters. This cut-out includes PMOS transistors431and436and NMOS transistors432and437. To form a first inverter, the drains of the transistors431and432are connected, and the gates of these transistors are also connected. To form a second inverter, the drains of the transistors436and437are connected, and the gates of these transistors are also connected. Cross-coupling of the two inverters is achieved by connecting the drains of the first inverter's transistors to the gates of the second inverter's transistors, and by connecting the drains of the second inverter's transistors to the gates of the first inverter's transistors. The sources of the transistors432and437are connected to ground.

The source leads of the PMOS transistors431and436are connected to the VDDcell line406. When the VDDcell line406supplies power to the storage cell428, a value that represents a bit can be stored at the output (the transistor drains) of the first inverter (i.e., at node426) and a value that represents the complement of the bit can be stored at the output (the transistor drains) of the second inverter (i.e., at node427). In certain conditions (i.e., during the normal operation of the cell428), the VDDcell line406supplies reduced power by using a reduced voltage. Thus, the storage cell428stores reduced voltages at the nodes426and427to represent the stored bit and its complement.

When operating based on a reduced voltage (e.g., VDDcell less than VDD), the storage cell428consumes less power, since the power consumed by a circuit is non linearly proportional to the voltage within the circuit. In some embodiments, the voltage supplied by the VDDcell line406is less than the voltage provided by the VDD line407by one NMOS threshold. In other embodiments, the voltage from the VDDcell line406is less than the voltage from the VDD line407by more than one NMOS threshold. At the reduced voltage, the current leakage from the electronic components of the storage cell428is exponentially lower at the lower voltage.

As mentioned above, the storage cell428normally provides continuous output of its stored value. While the storage cell428stores values at a voltage less than VDD, a typical useable configuration output has a voltage approximately equal to the full supply voltage VDD. Some embodiments compensate for the reduced voltage within the cell428by replacing the pair of configuration buffers140and145shown inFIG. 1, with the amplifier stage438ofFIG. 4. In these embodiments, though reduced voltage is supplied to the storage cell428, the storage cell428outputs the value representing the stored bit through the amplifier stage438at the full supply voltage (VDD). Moreover, the amplifier stage438buffers the storage cell428from the configuration outputs460and465, to prevent an undesirable change in the stored data when these outputs460and465are accessed by external circuitry (not shown).

As shown inFIG. 4, the amplifier stage438can be implemented by using the PMOS transistors441and446, and the NMOS transistors442and447. In these embodiments, the sources of the PMOS transistors441and446are coupled to the VDD line407(VDD≧VDDcell). The PMOS transistors441and446are cross-coupled, meaning that the gate of the PMOS441is coupled to the drain of the PMOS446, and the gate of the PMOS446is coupled to the drain of the PMOS441. As further shown inFIG. 4, the drain of the PMOS441is coupled to the drain of the NMOS442and the drain of the PMOS446is coupled to the drain of the NMOS447. The sources of the NMOS transistors442and447are grounded.

Also shown inFIG. 4, the gate of the NMOS transistor442is coupled to the storage cell428and the pass gate420at the node426. Similarly, the gate of the NMOS transistor447is coupled to the storage cell428and the pass gate425at the node427.

In some embodiments, the four transistors441,442,446and447described above form the amplifier stage438by implementing a static level converter. In these embodiments, the level converter does not directly drive the PMOS transistors441and446. Rather, the cross-coupled PMOS transistors441and446provide differential level conversion. Thus, the voltage VDD supplied by the VDD line407from the level converter (the four transistors) of the amplifier stage438drives the configuration outputs460and465, instead of the reduced voltage from the VDDcell line406.

The advantage of the level converter is that the voltage swing on the NMOS transistors442and447from the storage cell428is not required to go all the way to the rails (all the way to the full supply voltage VDD) for the value in the storage cell428to be correctly outputted. This allows the storage cell428to operate at reduced voltages. The reduced operating voltage reduces both the sub threshold leakage and the gate leakage of the cell428. The storage cell428in the memory circuit400consumes less power at the reduced voltage (supplied by the VDDcell line406). Despite operating at the reduced voltage, the cell428properly outputs its configuration value.

Moreover, since the supply voltage VDD (from VDD line407) passes only through the PMOS transistors441and446before reaching the outputs460and465, the amplifier stage438leaks significantly less current than the configuration buffers140and145of the prior art memory cell100illustrated inFIG. 1. This is partly because the configuration buffers140and145are typically implemented with a greater number of transistors, each of which leaks current, and partly because these transistors include NMOS transistors, each of which leaks more current than PMOS transistors.

II. Operation and Control of the Reduced Power Cell

The operation of the reduced power storage cell428will now be described in relation toFIGS. 4 and 5. As previously described,FIG. 4illustrates a memory circuit400that includes the reduced power cell428.FIG. 5illustrates a control circuit501that provides control signals for the memory circuit400. The memory circuit400is represented inFIG. 5as the simplified memory circuit500.

More specifically,FIG. 5illustrates the control circuit501having two control inputs, Not_Enable (EN-bar520) and Word_Line_Enable (WL_EN530), that provide three states: 1) Disabled; 2) Read/Write; and 3) Normal states for the memory circuit500. The input Not_Enable520is coupled to the input of the inverter525. The output of the inverter525is coupled to the NMOS transistor540. The NMOS transistor540connects the VDD line507to the VDDcell line506. The input Word_Line_Enable530is coupled to the input of the inverter535. An output of the inverter535is coupled to the transistors545,550, and555.

As further shown inFIG. 5, the PMOS transistor545connects the VDD line507to the VDDcell line506. The PMOS transistor555connects the VDDcell line506to the word line505. The PMOS transistor545is “stacked” above the PMOS transistor555such that the voltage on the word line505may never exceed the voltage on the VDDcell line506. Likewise, the voltage on the VDDcell line506may never exceed the voltage on the VDD line507. Since these voltages are tiered or “stacked” above and below the PMOS transistors545and555(i.e., the voltage on the VDD line507≧VDDcell line506≧word line505), a read operation will not upset a value stored in the storage cell528. In other words, because the voltage on the word line505may equal, but may never exceed, the voltage on the VDDcell line506, a “read upset” condition is avoided by the control circuit501.

The three states for the memory circuit500will now be described by reference to the control circuit501. As previously discussed, the three states for the memory circuit500include a Disabled State, a Read/Write State, and a Normal State.

When the input signal at the input Not_Enable520has a logical “1” and the signal at the input Word_Line_Enable530has a logical “0,” both the NMOS540and the PMOS545transistors are turned off and no power is supplied to the VDDcell line506. Thus, no power is supplied to the storage cell528that is coupled to the VDDcell line506. In this Disabled State, the memory circuit500that is controlled by the control circuit501is not used at all in the current arrangement.

As is more specifically shown by reference toFIG. 4, during the Disabled State, the word line405and the VDDcell line406have a logical “0.” When the VDDcell line406has a logical “0,” no power is provided to the storage cell428. Further, since the storage cell428outputs no value to the NMOS transistors442and447, the output of the amplifier stage438floats (e.g., at one P-channel threshold below the rail). Thus, the memory circuit400stores and outputs no value in the Disabled State.

The Disabled State is useful, for example, in the case of a configurable circuit where it is desirable to power off parts of the circuit (e.g., an array or parts of an array of memory cells). Powering off cells in this manner can additionally conserve power.

For the Read/Write State, the control circuit501: (1) provides the full supply voltage VDD to the storage cell528, so that it can store and output a value, and so that the memory circuit500can access the cell528through a read/write operation; (2) enables the word line505to select the cell528for the read/write operation; and (3) prevents the voltage on the word line505from exceeding the voltage on the VDDcell line506, such that a read upset condition is avoided.

More specifically, when an input signal at the input Not_Enable520has a logical “0” and the input Word_Line_Enable530has a logical “1,” then current flows from the VDD line507through the VDDcell line506(via the PMOS transistor545), and from the VDDcell line506through the word line505(via the PMOS transistor555). In other words, the PMOS transistors545and555switch to low impedance which pulls the voltages on these lines (VDD cell line506and word line505) up to the level of approximately VDD. In this state, the memory circuit500performs a read and/or write operation by using the full supply voltage VDD, in the manner of a typical memory cell in the art.

As more specifically shown inFIG. 4, during a read or a write operation, both the VDDcell line406and the word line405are activated (have a logical “1”). As previously described, the VDDcell line406provides a voltage at approximately VDD to the storage cell428to allow for a typical read or write operation by using the full supply voltage VDD. Since the word line405is activated, the pass gates420and425are turned on, and voltage signals are allowed to pass between the bit lines410and415, and the storage cell428. During a write operation, the voltage signals on the bit lines410and415modify the voltages (which represent the stored value) at the nodes426and427. For instance, the value on the bit line410passes through the pass gate420and is stored in the storage cell428at node426during a write operation. Conversely, the value stored in the storage cell428at node426passes through the pass gate420to modify the voltage on the bit line410, during a read operation. Write and read operations occur in the same manner through the pass gate425between the node427and the complement bit line415in the Read/Write State. Moreover, the nodes426and427(representing the stored bit and its complement) each may have a value approximately equal to VDD that is applied to the amplifier stage438. As previously mentioned, the amplifier stage438produces an output with a voltage of approximately VDD.

Specifically, as shown inFIG. 4, the storage cell428is coupled to the amplifier stage438at the gate-inputs of the NMOS transistors442and447. Thus, if a logical “1” is at the node426, then the NMOS transistor442will be activated and the PMOS transistor446will also be activated. Accordingly, current will flow from the VDD line407through the PMOS transistor446to the configuration output465. Conversely, the cross-coupled PMOS transistor441will ensure that the output460will be pulled low (i.e., grounded through the NMOS transistor442.

As previously mentioned, the amplifier stage438leaks less current than its counterpart in the prior art (buffers140and145) because the output voltage only passes through a low impedance PMOS transistor. However, the Normal State has even lower current leakage.

As shown inFIG. 5, when the input signal at the input Not_Enable520has a logical “0” and the signal at the input Word_Line_Enable530has a logical “0,” the NMOS transistor540is turned on and current flows from the VDD line507through the VDDcell line506. Because the signal at the output of the inverter535is a logical “1,” both the PMOS transistors545and555are turned off and the word line505has a logical “0.” When the PMOS transistors545and555are off, the word line505is not enabled for reading or writing the contents of the storage cell528in the memory circuit500. Moreover, because the NMOS transistor540connects the VDDcell line506to the VDD line507, the VDDcell line506has a reduced voltage of approximately one NMOS threshold below the full supply voltage VDD.

Therefore, the memory circuit500is used in the current arrangement (of a configurable IC, for instance) but the memory circuit500is not currently being accessed by a read or write operation through the word line505. However, the memory circuit500is outputting a value stored in the storage cell528to the configuration outputs560and565. This is the normal active state of the memory circuit500.

As more specifically shown inFIG. 4, during the Normal State, the VDDcell line406is activated but the word line405is de-activated. Since the word line405is de-activated, the pass gates420and425are turned off. When the pass gates420and425are turned off, the bit lines410and415are not used to write to, and are not used to read from, the storage cell428. However, since the VDDcell line406is activated, (a reduced) power is supplied to the storage cell428to maintain a value stored in the storage cell428. Since the cell operates at the reduced voltage (which in some embodiments is less than VDD by an NMOS threshold), the electronic components of the cell428leak exponentially less current than the prior art cell. Further, the value stored in the storage cell428is applied to the amplifier stage438through the NMOS transistors442and447.

Accordingly, the amplifier stage438outputs the value stored in the storage cell428at a voltage approximately equal to VDD (from the VDD line407). As mentioned above, the voltage signal from the VDD line407through the PMOS transistors441and446to the configuration outputs460and465is roughly equal to the full supply voltage VDD. In this manner, the voltage signal from the storage cell428that is approximately equal to VDDcell is amplified (level-converted) for output at the amplifier stage438to a value that is approximately equal to VDD. As previously mentioned, the voltage on the VDDcell line406can be less than the voltage on the VDD line407by one or more NMOS thresholds because the NMOS transistors442and447of the amplifier stage438do not require full swing. Thus, the amplifier stage438converts (amplifies) the voltage level from the storage cell428before outputting the voltage signal at the configuration outputs460and465. Therefore, in the Normal State, the storage cell428can operate at a reduced voltage to minimize leakage while maintaining and outputting a stable configuration output value at approximately the full supply voltage VDD.

4. Table Showing Inputs, Outputs, and States

Table 1 summarizes the three states for the memory circuit500in relation to the input values for the control circuit501. Table 1 also shows the values of the VDDcell line506and the word line505for the three states according to one embodiment of the present invention. For instance, the VDDcell line506is approximately equal to VDD (the full supply voltage) which allows typical reading and/or writing operations during the Read/Write State. During the Read/Write State the word line505is also approximately equal to VDD. During the Normal State, however, the word line505is de-activated and the VDDcell line506is about one NMOS threshold below VDD. As described above, reducing the VDDcell voltage by only one NMOS threshold is sufficient to result in a significant reduction in current leakage.

III. Performance and Advantages

As mentioned in relation toFIG. 4, the voltage within the cell (VDDcell) can be reduced from about 1.0V to about 0.8V or approximately one NMOS threshold, in some embodiments. In other embodiments VDDcell may be reduced by a plurality of NMOS thresholds to further reduce current leakage through the electronic components (e.g., the MOS transistors) of the memory circuit storage cell.

Some embodiments use 90 nm electronic components. At 90 nm the sub threshold leakage and the gate leakage are roughly equal. Since gate leakage is more sensitive to voltage reductions, some embodiments provide greater reduction in the gate leakage for 90 nm components. For 65 nm components, gate leakage is often worse than sub threshold leakage. Thus, a greater improvement in overall leakage reduction may occur for electronic components using 65 nm technologies.

Some embodiments allow the reduced voltage to be used for a set of cells that are similar to the cell428inFIG. 4, to reduce the power consumed and leaked by the entire set of memory cells. For instance, the invention also allows an entire row of cells to be powered down at a time. This feature can be useful, for instance, in an FPGA where the whole array may not be needed for some arrangements of the FPGA. Thus, the present invention allows for additional power savings by allowing unused parts of the array to be powered off. The invention has been described in relation to FPGA's and configuration cells. However, one of ordinary skill in the art will recognize that the invention would be useful in a variety of memory and other applications where reduced power consumption and lower leakage are desirable.

The foregoing has described a reduced power cell. One of ordinary skill will also recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention, even though the invention has been described with reference to numerous specific details. In view of the foregoing, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.