Electrostatic discharge power clamp with a JFET based RC trigger circuit

An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

FIELD OF THE INVENTION

The present invention relates to the field of integrated circuits; more specifically, it relates to an electrostatic discharge power clamp with a junction field effect transistor based resistive/capacitive network.

BACKGROUND

To protect integrated circuits from damage due to electrostatic discharge events, electrostatic discharge power clamp circuits are used. Traditional electrostatic discharge power clamp circuits require relatively long amounts of time to reset putting the circuits being protected at risk during consecutive electrostatic discharge events. Schemes to reduce this reset time result in the trigger portion of the electrostatic discharge power clamp circuits being overly sensitive to noise causing false triggers. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.

SUMMARY

A first aspect of the present invention is an electrostatic discharge power clamp circuit, comprising: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

A second aspect of the present invention is a method, comprising: providing an electrostatic discharge power clamp circuit, comprising: a trigger circuit comprising at least one junction field effect transistor connected between a power pad and a first plate of a capacitor and connected to an input of a buffer circuit, the input of the buffer circuit connected to the first plate of the capacitor; and a current by-pass device connected between the power pad and ground, to an output of the buffer circuit and to a second plate of the capacitor; charging the capacitor during an electrostatic discharge event, the charged capacitor turning on the current by-pass device to discharge current from the power pad to ground during the electrostatic discharge event; and discharging the capacitor through internal diodes of the one or more junction field effect transistors to the power pad when the electrostatic discharge event ends.

These and other aspects of the invention are described below.

DETAILED DESCRIPTION

There are three general types of electrostatic discharge (ESD) events that have been commonly modeled: the human body model (HBM), the machine model (MM) and the charged device model (CDM). The HBM and MM represent discharge current between any two pins (e.g., pads) on an integrated circuit (IC) as a result of (respectively) a human body discharging through the IC and an electrically conductive tool discharging through the IC. Whereas a human body discharge is relatively slow in terms of rise time and has, for example, a unidirectional current of about 1-3 amps. A tool discharge is a relatively rapid event compared with HBM that, in one example, produces a bi-directional current into and out of the pins of about 3-5 amps. In the CDM, the ESD event does not originate from outside the IC, but instead represents a discharge of a device within the IC to ground (e.g., VSS). The IC is charged through the triboelectric effect (friction charging) or by external electrical fields. The CDM is a very rapid event compared with HBM. ESD events cause high currents to flow through devices of ICs that damage the devices. For example, with field effect transistors, the PN junctions and gate dielectrics can be damaged and interconnects between devices can be damaged.

A problem with traditional resistive/capacitive (RC) triggered ESD power clamp circuits that use a metal-oxide-silicon field effect transistor (MOSFET) as the resistive element of the RC trigger is once the ESD power clamp circuit is triggered by an ESD event, the ESD power clamp circuit is not useable until the RC trigger resets after the time delay required to discharge the RC timing capacitor through the RC resistor or MOSFET. HBM and CDM studies show that when the traditional ESD power clamp circuits undergo quick consecutive ESD events, less than full ESD protection is provided. The delay is severe enough that complex MOSFET networks are often used to reduce the delay. Another problem with traditional resistive/capacitive (RC) triggered ESD power clamp circuits that use polysilicon or metal resistor is the large chip area needed to achieve the high resistance required for the necessary on-time. The embodiments of the present invention utilize junction-field effect transistors (JFETs) as a unique automatically variable resistive element in the RC trigger circuit of an electrostatic discharge (ESD) power clamp circuit which reduce the reset time, use less chip area and provide additional benefits that can not be provided by ESD power clamp circuits which use polysilicon/metal resistors or MOSFET based resistors.

When used in the power clamp circuits according to embodiments of the present invention, the drain of the JFET is connected to VDD, and the gate and source of the FET are connected to the timing capacitor. The following discussion should be understood in this context. The drain-to-source resistance of JFET is a function of the drain-to-gate voltage.

During an ESD event, a positive pulse is applied to the power terminal and the JFETs gate-to-drain PN junction is maximally reverse biased initially. This reverse bias pinches off the channel and the JFET acts as a high impedance resistor similar to the case of a regular RC power clamp. The high resistance is desired in this situation as it keeps the ESD power clamp on long enough to dissipate incoming ESD energy. The advantages of using the JFET as compared to other resistive elements are small area compared to traditional back-end-of-line metal resistor and the fact JFETs do not suffer delayed turn-on compared to MOSFETs. Another advantage of the JFET as a resistive element in the RC network stems from the fact that a JFET can quickly discharge the timing capacitor to VDD through the internal gate-to-drain diodes to restore the timing capacitor to its pre-triggered initial state.

During normal circuit operation the clamp is not triggered and the timing capacitor voltage reaches the input voltage level. In this case the JFET is operated in the linear region with its channel open and acts as a low impedance resistor. The low resistance is also desired during normal operation mode as it reduces the susceptibility of the ESD power clamp to noise and therefore false triggering.

Because the JFET is automatically functioning at the optimal resistance during both normal operation and during ESD events improved overall ESD power clamp circuit performance is provided compared to ESD power clamp circuit using other resistive elements (e.g., MOSFET based resistors, polysilicon resistors and metal resistors and other resistive elements).

A direct current (DC) power supply has two terminals. The more positive terminal may be designated VDD and the other terminal may be designated VSS. Thus, VDD is more positive than VSS and VDD may be considered power and VSS may be considered ground. VSS/ground may be a positive, zero or negative potential so long as VDD is more positive than VSS. A positive voltage is a voltage having a potential greater than zero and a negative voltage is a voltage having a potential less than zero. Integrated circuit power supply pads and power supply lines (commonly called power rails) use the same terminology as that of the power supply terminal they are connected to or intended to be connected to. While the terms VDD and VSS will be used in describing the embodiments of the present invention, it should be understood that the terms “positive” or “power” may be substituted for VDD and the terms “negative” or “ground” may be substituted for VSS.

FIG. 1is a circuit diagram of a first electrostatic discharge power clamp circuit according to embodiments of the present invention. InFIG. 1, an ESD power clamp circuit100is connected between a power pad (VDD) and ground (VSS). ESD power clamp circuit100includes a current by pass device embodied as an n-channel MOSFET T1(NFET), a buffer circuit embodied as inverters I1, I2and I3, and a trigger circuit embodied as a n-channel JFET T2(nJFET) and a capacitor C1. JFET T2includes an internal diode D1shown connected by dashed lines. nJFET T2is the resistive element of an RC trigger circuit that includes capacitor C1.

InFIG. 1, the drain of NFET T1is connected to VDD and the source and body of NFET T1are connected to VSS. The drain of nJFET T2is connected to VDD and the gate and source of nJFET T2is connected to a first plate of capacitor C1. The second plate of capacitor C1is connected to VSS. The input of inverter I1is connected to the source of nJFET T2, the output of inverter I1is connected to the input of I2, the output of inverter I2is connected to the input of inverter I3, and the output of inverter I3is connected to the gate of NFET T1. Internal diode D1is the PN junction between the P-doped gate region and N-doped drain region of nJFET T2(seeFIG. 2). Circuit wise the cathode of diode D1is connected to VDD and the anode of diode D1is connected to the first plate of capacitor C1and the input of inverter I1. While three inverters are illustrated inFIG. 1, there may be more or less invertors connected in series. Inventors I1, I2and I3comprise an exemplary buffer circuit and other types of buffer circuits may be used (e.g., voltage buffers, current buffers, impedance matching or transforming buffers.”

During normal operation (power on/VDD high, no ESD event) the resistance of nJFET T2is low because the drain, gate and source of the JFET are near the same potential reducing drain-to-source impedance. The resistance of the JFET during normal operation can be calculated using the basic resistance equation where the resistance is a function of the channel resistivity and the geometrical dimensions of the channel. During an ESD event on the VDD supply the resistance of nJFET T2is higher because the gate-to-drain PN junction is maximally reverse biased, reducing the effective channel width and pinching off the current passing through nJFET T2. The resistance of a reverse biased JFET is determined by the saturation current and the applied pulse voltage. When the ESD event is over capacitor C1discharges through diode D1to VDD. It is the automatic switching between high and low resistance of nJFET T2that distinguishes the nJFET/capacitor RC trigger circuit from other RC trigger circuit designs.

The resistance of nJFET T2is a function of the length of the channel region of nJFET T2. Increasing the channel length of nJFET T2will increase the channel resistance of nJFET T2and the RC time constant of ESD power clamp circuit100. Decreasing the channel length of nJFET T2, on the other hand, will decrease the channel resistance of nJFET T2. Therefore the RC time constant of ESD power clamp circuit100can thus be selected by selection of the channel length of nJFET T2.

FIG. 2is a diagram depicting the structure and features of a junction field effect transistor according to embodiments of the present invention. InFIG. 2, a typical nJFET105includes an N-type body110. Formed in N-type body110is an N-type drain115, an N-type source120and P-type gates125. The channel of nJFET105is the region of body110between source115, drain120and gates125. The internal diode is the PN junction between gate125(which is the cathode) and drain120(which is the anode).

FIG. 3is a diagram depicting the structure and features of a metal oxide field effect transistor according to embodiments of the present invention. InFIG. 3, a typical NFET130includes a body135. Formed in body135are source/drains140on opposite sides of a channel region145of body135. A gate electrode150(e.g., metal or polysilicon) is formed over channel region145and separated from channel region145by a gate dielectric layer155. It should be noted that when the source and drain are tied together, an FET acts as a capacitor.

FIG. 4is a circuit diagram of a second electrostatic discharge power clamp circuit according to a further embodiment of the present invention. InFIG. 4, an ESD power clamp circuit200is similar to ESD power clamp circuit100ofFIG. 1except the trigger circuit is embodied with an additional JFET, nJFET T3and the connections of nJFET T2are slightly modified. The drain of nJFET T2is now connected to the source and gate of nJFET T3instead of directly to VDD. nJFET T3includes its own internal diode D2. The drain of nJFET T3is connected to VDD. Circuit wise the cathode of diode D1is connected to the gate and source of nJFET T3instead of directly to VDD, the anode of diode D2is connected to the cathode of diode D1and the cathode of diode D3is connected to VDD. The addition of nJFET T3increases the resistance of the RC trigger circuit200over the ESD power clamp circuit100ofFIG. 1. The operation of ESD power clamp circuit200is similar to that of ESD power clamp circuit100ofFIG. 1. While two nJFETs are illustrated more than two nJFETs may be connected in series.FIG. 4illustrates a method of designing the resistance of the RC trigger circuit at the circuit level rather than the device level which allows increased range of control of the nJFET channel resistance and thus the RC time constant of the RC network of the ESD power clamp circuit.

FIG. 5is a circuit diagram of a third electrostatic discharge power clamp circuit according to a further embodiment of the present invention. InFIG. 5, an ESD power clamp circuit300is similar to ESD power clamp circuit200ofFIG. 2except instead of connecting the gate of nJFET T3to the source of nJFET T3, the gate of nJFET T3is connected to the first plate of capacitor C1. This increases the resistance of the RC trigger circuit300over the ESD power clamp circuit200ofFIG. 4because in this configuration the gate of nJFET T3is more negatively biased than the source of nJFET T3and thus the conductivity of the channel of nJFET T3is lowered. The operation of ESD power clamp circuit200is similar to that of ESD power clamp circuit100ofFIG. 1. Again, while two nJFETs are illustrated more than two nJFETs may be connected in series with the gate of each nJFET of the series connected to the first plate of capacitor C1.FIG. 5illustrates another method of designing the resistance of the RC trigger circuit at the circuit level rather than the device level which allows increased range of control of the nJFET channel resistance and thus the RC time constant of the RC network of the ESD power clamp circuit.

FIG. 6is a circuit diagram of the electrostatic discharge power clamp circuit according ofFIG. 1including a false-trigger suppression circuit. InFIG. 6, an ESD power clamp circuit400is similar to ESD power clamp circuit100ofFIG. 1except a first input (pin A) of false-trigger suppression circuit405is connected to the drain of nJFET T2and a first output (pin B) of false-trigger suppression circuit405is connected to the gate and source of nJFET T2. A second input (pin C) of false-trigger suppression circuit405is connected to a power-on signal. False-trigger suppression circuit405shorts out nJFET T2by providing an additional low resistance path when power is applied to the VDD pad and the power-on signal is asserted (i.e., during normal operation). With nJFET T2bypassed, capacitor C1maintains at the same voltage as VDD and NFET T1will not turn on. Any other combination of VDD and power-on signal allows NFET T1to turn on.

FIG. 7is a circuit diagram of an exemplary false-trigger suppression circuit according to embodiments of the present invention. InFIG. 7, false-trigger suppression circuit405comprises a NAND gate N1and a p-channel FET (PFET) T4. A first input (A) of false-trigger suppression circuit405is connected to the source of PFET T4and a first input of NAND gate N1. A second input (C) of false-trigger suppression circuit405is connected to a second input of NAND gate N1. The output of NAND gate N1is connected to the gate of PFET T4. The drain and body of PFET T4are connected to the output (B) of false-trigger suppression circuit405. Resistance between input (A) and output (B) will be low only when both inputs (A) and (C) are asserted high.

Returning toFIG. 4, it should be apparent that buffer circuit405ofFIG. 6may be connected to ESD power clamp circuit200. Pin A would be connected the drain of nJFET T3and the VDD pad and pin B would be connected to the gate and source of nJFET T2.

Returning toFIG. 6, it should be apparent that buffer circuit405ofFIG. 6may be connected to ESD power clamp circuit300. Pin A would be connected to the drain of nJFET T3and the VDD pad and pin B would be connected to the gate and source of nJFET T2.

Thus, the ESD power clamp circuits of the embodiments of the present invention provide ESD protection with a minimal time to reset that are less sensitive to noise causing false triggers than conventional ESD power clamp circuits.