Method for testing analog-to-digital converter and system therefor

A data processing system having an analog-to-digital converter (ADC) and method for testing the ADC are provided. The data processing system also comprises a digital-to-analog converter (DAC) and test logic. The DAC has a first voltage range, an input for receiving a test code, and an output. The ADC has a second voltage range larger than the first voltage range, an input coupled to the output of the DAC, and an output for providing a series of output codes over the second voltage range. The test logic is coupled to the ADC and is for controlling testing of the ADC using the DAC. A plurality of series of test codes are provided to the DAC for testing portions of the second voltage range output from the ADC. A beginning series of test codes is for testing a beginning portion of the second voltage range and subsequent series of test codes are for testing subsequent portions of the second voltage range. Subsequent portions of the second voltage range are tested until a maximum voltage of the second voltage range of the ADC is reached.

BACKGROUND

This disclosure relates generally to test methods and systems, and more specifically, to methods and systems for testing analog-to-digital converters.

2. Related Art

Many of today's system on chip (SoC) devices include converters such as an analog-to-digital converter (ADC). An ADC generally samples received analog voltages and converts the sampled voltages into digital values. The resolution or precision of an ADC is typically dependent upon the application of SoCs. For example, if the ADC was used to determine a temperature in a consumer temperature sensing application, then a typical resolution might be 8 bits. Higher resolution ADCs require higher precision and are generally more sensitive to environmental conditions such as circuit noise, temperature, operating voltages, and so on.

Traditionally, ADCs are tested by providing test input voltages representing each of the conversion result values. To account for noise and to precisely calculate the error, the test input voltage is varied in multiple steps in the range of each conversion result value. Because this test technique is time consuming, which leads to prolonged test times and requires expensive test equipment, it is desirable to perform ADC testing within a system or application to assist in system debug efforts, for example.

DETAILED DESCRIPTION

The present disclosure includes a method and system which accommodates testing of an analog-to-digital converter (ADC) using a digital-to-analog converter (DAC) which has a smaller output voltage range than the ADC input voltage range. For example, the ADC may have a 3 volt input voltage range and the DAC may have a 1.5 volt output voltage range. Because the DAC has an output voltage range less than an input voltage range of the ADC, a portion of the ADC voltage range may be tested by selectively coupling capacitors in the capacitor array of the ADC to a reference voltage VREF. Capacitors selectively coupled to VREF during a sampling phase of the ADC operation allow an offset voltage to be added to the DAC output voltages.

FIG. 1is a simplified block diagram illustrating a data processing system100according to an embodiment of the present disclosure. In some embodiments, data processing system100may be implemented as a single integrated circuit. In some embodiments, data processing system100may be implemented as a plurality of integrated circuits, or may be implemented as a combination of integrated circuits and discrete components. Alternate embodiments may implement system100in any manner.

In the embodiment illustrated inFIG. 1, data processing system100includes a central processing unit (CPU)102, memory104, other modules106, a digital-to-analog converter (DAC)108, and analog-to-digital converter (ADC)110, which are all bi-directionally coupled to each other by way of a system bus112. The DAC108and the ADC110are also coupled to each other via bus114. In some embodiments, system100may include fewer, more, or different blocks of circuitry than those illustrated inFIG. 1.

FIG. 2is a simplified schematic diagram illustrating an exemplary successive approximation register (SAR) ADC200according to an embodiment of the present disclosure. SAR ADC200depicts representative circuitry of ADC110inFIG. 1and includes a capacitor array202, a comparator204, an SAR control unit206, test logic208, a multiplexer210, and switches212-228.

Capacitor array202includes a plurality of binary-weighted capacitors C1-CN, where N is the number of bits of resolution of the ADC. For example, capacitor array202may include binary-weighted capacitors C1-C12for a 12-bit resolution ADC. In some embodiments, the capacitor array may be a two-stage weighted capacitor array, a C-2C ladder capacitor array, or any suitable form of a capacitor array sufficient for an SAR ADC.

In this embodiment, C1is characterized as the least significant bit (LSB) capacitor and CN is characterized as the most significant bit (MSB) capacitor. A dummy capacitor (not shown) is included in the capacitor array and has equal value as the LSB capacitor. Each capacitor C1-CN has a first terminal and a second terminal whereby capacitors C1-CN are coupled between switches212-228and a first input of comparator204. Switches212,218, and224selectively couple the first terminal of each capacitor C1-CN of the capacitor array202to a voltage VIN provided at an output of the multiplexer210. Switches214,220, and226selectively couple the first terminal of each capacitor C1-CN of the capacitor array202to first voltage reference node VREFH. Switches216,222, and228selectively couple the first terminal of each capacitor C1-CN of the capacitor array202to second voltage reference node VREFL. The second terminal of each capacitor C1-CN is coupled to the first input of comparator204(node VP).

Comparator204includes the first input coupled to receive a voltage VP at node VP coupled to the second terminal of the capacitors C1-CN, a second input coupled to receive a reference voltage VBIAS at a VBIAS supply terminal, and an output for providing a digital indication of whether the voltage at the first input is higher or lower than the voltage at the second input. In this embodiment, comparator204is characterized as a differential comparator and compares the voltage VP with the reference voltage VBIAS. For example, when VP is lower than VBIAS, the output of comparator204can be at a logic low level, and when VP is higher than VBIAS, the output of comparator204can be at a logic high level.

SAR control unit206is coupled to receive the digital indication from comparator204of whether VP is at a higher voltage or lower voltage than VBIAS. SAR control unit206sequentially determines the value of bits based on the indication from comparator204and stores the results in a register, memory, or the like. For example, in an 8-bit resolution ADC, a first bit value may be determined in a first clock cycle and stored, and a second bit value may be determined in a second clock cycle and stored, and so on until all eight bit values have been determined and stored. The SAR control unit206is coupled to provide signals via bus230for controlling switches212-228and is coupled to test logic block208via bus232whereby a pass or fail can be determined based on the stored results.

Test logic block208of SAR ADC200communicates with the DAC108inFIG. 1via bus114. For example, test logic block208may provide a series of test codes to the DAC108and the DAC108, in turn, outputs voltages for testing a portion of the voltage range of the ADC200. The test logic block208may be used to determine a pass/fail result from an ADC conversion corresponding to a test code sent to the DAC108.

Multiplexer210couples an output of DAC108inFIG. 1to capacitor array202during a test mode. Multiplexer210includes a first input IN for receiving an analog voltage during normal operation of the SAR ADC200, a second input for receiving an analog voltage from DAC108during a test mode, and an output for providing an input voltage VIN to the capacitor array202via switches212,218, and224. Multiplexer210receives a control signal (not shown) to select one of the first input or the second input to be coupled to the output.

During a sample phase of the ADC110, voltage at node VIN is sampled on binary-weighted capacitors C1-CN in the capacitor array202via switches212,218, and224. After the voltage at node VIN is sampled on binary-weighted capacitors C1-CN in the capacitor array202, switches212,218, and224are opened in a hold phase. In a conversion phase, charge on each binary-weighted capacitor is successively redistributed and compared with a reference voltage VBIAS at comparator204, converting the sampled voltage to a digital value.

FIG. 3is a simplified flow chart illustrating an exemplary method for testing an ADC using a DAC according to an embodiment of the present disclosure. In this embodiment, DAC108has a voltage range which is less than a voltage range of ADC110and is coupled to provide a range of voltages to an input of ADC110via bus114during a test mode. The DAC108receives input codes such as test codes, commands, or the like, and in turn outputs corresponding analog voltages. The DAC108output voltages are provided to the ADC110during the test mode. The ADC110samples the provided voltages and through a conversion process, generates digital output codes. The ADC110may store the output codes in memory, registers, or the like, and may provide the output codes to functional blocks such as test logic unit208, for example.

At step302, an ADC test mode is enabled. In some embodiments, variables may be set or reset to initial values for a test procedure. For example, a procedure to test an ADC using a DAC may include initial settings of variables such as an iteration number I set to I=1, a DAC resolution set to 12 bits, a DAC step size set to 1, an ADC resolution set to 12 bits, an ADC maximum output code D set to 1, and so on.

At step304, a DAC output is coupled to a capacitor array of the ADC. In this embodiment, capacitor array202includes a plurality of binary-weighted capacitors C1-CN, where N is the number of bits of resolution of the ADC110. In some embodiments, the capacitor array202may be a two-stage weighted capacitor array, a C-2C ladder capacitor array, or any suitable form of a capacitor array sufficient for an SAR ADC. In this embodiment, DAC108is coupled to provide voltages to an input of ADC110via bus114during the ADC test mode. Switches212,218, and224selectively couple the first terminal of each capacitor C1-CN of the capacitor array202to the input of ADC110. A series of test codes are provided to the DAC108. The DAC108in turn outputs a test voltage corresponding to each test code.

In this embodiment, the DAC108output voltage is ramped or increased sequentially to test the ADC110. For example using an M-bit DAC108, input test codes may be increased sequentially from 0 to 2^M−1. In this example, a 12-bit DAC108having a 1.5 volt range may be considered. When a first test code of 0000 (decimal) is provided to the DAC108, a corresponding voltage of 0 volts (0000*(1.5 volts/2^12 codes)) may be output from the DAC108. When a second test code of 0001 (decimal) is provided to the DAC108, a corresponding voltage of 0.366 millivolts (0001*(1.5 volts/2^12 codes)) may be output. When a third test code of 0002 (decimal) is provided to the DAC108, a corresponding voltage of 0.732 millivolts (0002*(1.5 volts/2^12 codes)) may be output, and so on until a last test code of 4095 (decimal) is provided to the DAC108whereby a corresponding voltage of 1.50 volts (4095*(1.5 volts/2^12 codes)) may be output. In some embodiments, the DAC108output voltage may be decreased sequentially to test the ADC110. In some embodiments, portions of the DAC108output voltage range may be used to test the ADC110.

At step306, one or more capacitors in the capacitor array of the ADC110are selectively coupled to a reference voltage (VREF) supply. In some embodiments, the reference voltage VREF may include VREFH or VREFL shown inFIG. 2. Because the DAC108has a voltage range less than a voltage range of the ADC110, a portion of the ADC110voltage range may be tested by selectively coupling capacitors in the capacitor array202to the reference voltage VREF. For example, when an M-bit DAC having 1.5 volt range is used to test an N-bit ADC having a 3.0 volt range, the DAC input code may be increased sequentially from 0 to 2^M−1 in a first iteration outputting a voltage that increases substantially linearly. In this example, about a one-half portion of the ADC110voltage range may be tested. The series of DAC input codes may be representative of a linear signal having a slope determined to test about one-half of the voltage range of the ADC. To test one or more next portions of the ADC110voltage range, capacitors are selectively coupled to VREF in subsequent iterations such that an offset voltage is added to the DAC108output voltages. For example, the last DAC108voltage of the tested one-half portion may correspond to the last converted ADC110output code D=2048. To test the next one-fourth portion of the ADC110voltage range, capacitors C1(LSB) and CN (MSB) may be coupled to VREF in a second iteration causing the DAC108to output voltages corresponding to ADC110output codes2049-3072. To test the next one-eighth portion of the ADC110voltage range, capacitors C1(LSB), CN-1, and CN (MSB) may be coupled to VREF in a third iteration causing the DAC108to output voltages corresponding to ADC110output codes3073-3584, and so on.

At step308, the DAC108output voltage is provided, during a sampling phase of the ADC110, to the plurality of binary weighted capacitors of the capacitor array202excluding capacitors coupled to the VREF supply. The DAC108output test voltage corresponds to the test codes provided to the DAC108. Referring back toFIG. 2, in the test mode, multiplexer is configured to allow output voltage from DAC108to be coupled to VIN, and switches212,218, and224selectively couple VIN to capacitors of the capacitor array. For example, the DAC108output voltage may not be provided to capacitors C1and CN in the ADC110D+1 output code example above because C1and CN may be coupled to VREF.

At step310, ADC110conversion is performed on a sampled voltage. For example, during an ADC conversion phase, charge on each binary-weighted capacitor is successively redistributed and compared with a reference voltage VBIAS at comparator204, converting the sampled voltage to a digital value or ADC output code.

At step312, determine if the ADC110output code D has reached a maximum. If the ADC110output code D has reached a maximum (yes), then the test is complete at step314. If the ADC110output code D has not reached a maximum (no), then determine if a maximum DAC108input value has been reached at step316. In some embodiments, a maximum ADC110output code for a portion of the ADC110output codes may be determined such as when testing a portion of the ADC110voltage range, for example. In some embodiments, a minimum ADC110output code may be determined at step312, for example, when testing the ADC110using the DAC108having a ramp voltage that is characterized as a decreasing ramp voltage.

At step316, determine if the DAC108input code has reached a maximum. The DAC108output voltages correspond to the input codes provided to the DAC108. When a maximum input code is provided to the DAC108, the DAC108may output a corresponding maximum voltage. For example, considering a 12-bit DAC having 1.5 volt range, the maximum input code may be 4095 (decimal) and may correspond to an output voltage of 1.5 volts. If the DAC108input code has not reached a maximum (no), then increment DAC108input value by step size at step318. If the DAC108input code has reached a maximum (yes), then determine if the increment value I equals the ADC resolution bits (I=N) at step320. In some embodiments, a maximum DAC input code for a portion of the possible DAC input codes may be determined such as when testing a portion of the ADC110voltage range, for example. In some embodiments, a minimum DAC108input code may be determined at step316, for example, when testing the ADC110using the DAC108having a ramp voltage that is characterized as a decreasing ramp voltage.

At step318, the DAC108input code is incremented by a step size. If the DAC108input code has not reached a maximum input code at step316, then increment DAC108input code according to the step size and return at step308. For example, an input code of 0010 (decimal) may be provided to the DAC108, and after incrementing, the input code may be at 0012 (decimal) according to a step size of 2.

At step320, determine if the iteration number I equals the number of ADC bits of resolution N. If the DAC108input code has reached a maximum at step316, then determine if the iteration number I has reached the number of ADC bits of resolution N. An iteration generally refers to the process of providing a set of input codes to the DAC whereby corresponding output voltages are provided to test a portion of the voltage range of the ADC. For example, a first iteration may correspond to input codes provided to the DAC which begin at a minimum code and end at a maximum code. Considering a 12-bit DAC having 1.5 volt range, the minimum input code may be 0000 (decimal) and may correspond to an output voltage of 0 volts, and the maximum input code may be 4095 (decimal) and may correspond to an output voltage of 1.5 volts. In some embodiments, the size of the portion of the voltage range of the ADC may be determined by the selected coupling of one or more capacitors of the plurality of binary-weighted capacitors. In some embodiments, the slope of a ramped signal resulting from a series of test codes may be determined by a step size between DAC input codes of the series of test codes.

Because the DAC108has a voltage range less than a voltage range of the ADC110, more than one iteration of the DAC input code may be required to test the voltage range of the ADC110. The first iteration (1=1) may allow the DAC to be used to test a first portion of the ADC110voltage range. For example, the first iteration may include a series of test codes provided to the DAC which in turn outputs corresponding output voltages from 0 volts through 1.5 volts representative of a linear signal having a slope determined to test about a one-half portion of a 12-bit ADC having a 3.0 volt input voltage range. To test a second and subsequent portions of the ADC110voltage range, capacitors may be selectively coupled to VREF in the second and subsequent iterations such that an offset voltage is added to the DAC108output voltages. For example, the second iteration (1=2) may include a series of test codes provided to the DAC108which in turn outputs corresponding output voltages from approximately 1.5 volts through 2.25 volts and may be representative of a linear signal having a slope determined to test about a one-fourth additional portion of the 12-bit ADC110having a 3.0 volt input voltage range. A third iteration (1=3) may include a series of test codes provided to the DAC108which in turn outputs corresponding output voltages from approximately 2.25 volts through 2.375 volts and may be representative of a linear signal having a slope determined to test about a one-eighth additional portion of the ADC110input voltage range. A fourth iteration (1=4) may include DAC108output voltages to test about a one-sixteenth additional portion of the ADC110, a fifth iteration (1=5) may include DAC108output voltages to test about a one-thirty-second additional portion of the ADC110, and so on through a twelfth iteration (I=N=12) beyond which no further binary-weighted capacitors can be selectively coupled to VREF. The accumulative range of the DAC108output voltages over iterations 1 through 12 can be used to test the entire input voltage range of ADC110by testing 4096 out of a possible 4096 ADC output codes in the foregoing example.

If the iteration number I does not equal the number of ADC bits of resolution N (no), then increment the iteration number I at step322and continue at step324. If the iteration number I equals the number of ADC bits of resolution N (yes), then change the DAC step size according to 2^(M−N+1) at step324.

At step322, the DAC108input code step size is incremented. If the DAC108input code has not reached a maximum input code at step316, then increment DAC108input code step size and return at step308. For example, the DAC108input code step size may initially be at 1 whereby each input code may be increased by 1. After incrementing the input code step size to 2, each input code may be increased by 2, effectively skipping every other input code.

At step324, change the DAC step size by 2^(M−N+1). If the iteration number I equals the number of ADC bits of resolution N at step320or if the iteration number was incremented at step322, then the DAC step size may be changed according to 2^(M-N+1). For example, the DAC108step size may initially be at 1 whereby each input code may be increased by 1. After incrementing the step size to 2, each input code may be increased by 2, effectively skipping every other input code. After the DAC108step size is changed according to 2^(M−N+1), then continue at step306.

Generally, there is provided, a method of testing an analog-to-digital converter (ADC) having a plurality of binary-weighted capacitors including: coupling an output of a digital-to-analog converter (DAC) to the plurality of binary-weighted capacitors, the DAC having a voltage range that is less than a voltage range of the ADC; providing a series of test codes to the DAC, the series of test codes for testing a portion of the voltage range of the ADC; outputting a test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors during a sampling phase of the ADC; determining an output code from the test voltage during an ADC conversion phase; selectively coupling one or more capacitors of the plurality of binary-weighted capacitors, corresponding to a next portion of the ADC to be tested, to a reference voltage; and iteratively performing the steps of providing, outputting, determining, and selectively coupling until testing of the voltage range of the ADC is complete. Providing a series of test codes may further include providing a series of test codes during a first iteration, the series of test codes representative of a linear signal having a slope determined to test about one-half of the voltage range of the ADC. Providing a series of test codes may further include providing a series of test codes during a second iteration, the series of test codes representative of a linear signal having a slope determined to test an additional one-quarter of the voltage range of the ADC. Outputting a test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors during a sampling phase of the ADC may further include outputting the test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors excluding the one or more capacitors of the plurality of binary-weighted capacitors corresponding to a beginning test code of the next portion of the ADC to be tested. The ADC may be characterized as being a successive approximation register (SAR) ADC. Providing a series of test codes to the DAC, the series of test codes for testing a portion of the voltage range of the ADC, may further include providing a series of test codes for testing a portion of the voltage range of the ADC, a size of the portion determined by the selected coupling of one or more capacitors of the plurality of binary-weighted capacitors. Outputting a test voltage corresponding to the test codes from the DAC may further include outputting a voltage that increases substantially linearly. Testing of the voltage range of the ADC may be complete when a maximum voltage of an ADC input range is reached. Determining an output code from the test voltage during an ADC conversion phase may further include comparing a voltage from the plurality of binary-weighted capacitors with a reference voltage.

In another embodiment, there is provided, a method of testing a successive approximation register analog-to-digital converter (SAR ADC) having a plurality of binary-weighted capacitors including: coupling an output of a digital-to-analog converter (DAC) to the plurality of binary-weighted capacitors, the DAC having a voltage range that is less than a voltage range of the SAR ADC; providing a series of test codes to the DAC, the series of test codes representing a substantially linear voltage change over time, the series of test codes for testing a portion of the voltage range of the SAR ADC; outputting a test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors during a sampling phase of the SAR ADC; determining an output code from the test voltage during a SAR ADC conversion phase; selectively coupling one or more capacitors of the plurality of binary-weighted capacitors, corresponding to a next portion of the SAR ADC to be tested, to a reference voltage; and iteratively performing the steps of providing, outputting, determining, and selectively coupling until testing of the voltage range of the SAR ADC is complete. The voltage range of the DAC may be further characterized as being an output voltage range and the voltage range of the ADC may be further characterized as being an input voltage range. Outputting a test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors during a sampling phase of the SAR ADC may further include outputting the test voltage corresponding to the test codes from the DAC to the plurality of binary-weighted capacitors excluding the one or more capacitors of the plurality of binary-weighted capacitors corresponding to a beginning test code of the next portion of the SAR ADC to be tested. Determining an output code from the test voltage during an SAR ADC conversion phase may further include comparing a voltage from the plurality of binary-weighted capacitors with a reference voltage. Providing a series of test codes to the DAC, the series of test codes representing a substantially linear voltage changing over time may further include the substantially linear voltage increasing over time. Testing of the voltage range of the SAR ADC may be complete when a maximum voltage of an SAR ADC output voltage is reached. Providing a series of test codes may further include providing a series of test codes during a first iteration, the series of test codes may have a slope determined to test about one-half of the voltage range of the SAR ADC, and during a second iteration, the series of test codes may have a slope determined to test an additional one-quarter of the voltage range of the SAR ADC.

In yet another embodiment, there is provided, a data processing system including: a digital-to-analog converter (DAC) having a first voltage range, the DAC having an input for receiving a test code, and an output; an analog-to-digital converter (ADC) having a second voltage range larger than the first voltage range, the ADC having an input coupled to the output of the DAC, and an output for providing a plurality of output codes representative of the second voltage range; and test logic coupled to the ADC, the test logic for controlling testing of the ADC using the DAC for testing portions of the second voltage range of the ADC, wherein a beginning portion of a series of test codes provided to the DAC is for testing a beginning portion of the second voltage range and subsequent portions of the series of test codes is for testing subsequent portions of the second voltage range, and wherein the subsequent portions of the second voltage range are tested until testing of all of the second voltage range of the ADC is complete. The ADC may be characterized as being a successive approximation register ADC. The series of test codes may be representative of a ramped signal having a slope determined by a step size between test codes of the series of test codes. The data processing system may be implemented on a single integrated circuit.

By now it should be appreciated that there has been provided a method and system which accommodates testing of an analog-to-digital converter (ADC) using a digital-to-analog converter (DAC) which has a smaller output voltage range than the ADC input voltage range. Because the DAC has an output voltage range less than an input voltage range of the ADC, a portion of the ADC voltage range may be tested by selectively coupling capacitors in the capacitor array to a reference voltage VREF. Capacitors selectively coupled to VREF during a sampling phase of the ADC operation allow an offset voltage to be added to the DAC output voltages.

Some of the above embodiments, as applicable, may be implemented using a variety of different data processing systems. For example, althoughFIG. 1and the discussion thereof describe an exemplary data processing system, this exemplary system is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the system has been simplified for purposes of discussion, and it is just one of many different types of appropriate system that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.