Hybrid-integrated photonic chip package

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

CROSS-REFERENCE TO RELATED APPLICATIONS

BACKGROUND

The present disclosure generally relates to a chip package that accommodates semiconductor chips. More specifically, the present disclosure relates to a hybrid-integrated chip package that includes a substrate with adjacent payload and photonic chips.

2. Related Art

As integrated-circuit (IC) technology continues to scale to smaller critical dimensions, it is increasingly difficult for existing interconnection technologies to provide suitable communication characteristics, such as: high bandwidth, low power, reliability and low cost. Engineers and researchers are investigating a variety of interconnect technologies to address these problems, and to enable future high-density, high-performance systems.

One interconnect technology to address these challenges, which is the subject of ongoing research, is optical communication. In principle, optical communication can be used to communicate large amounts of data. However, while photonic technologies based on vertical cavity surface-emitting lasers (VCSELs) and optical fibers are typically a convenient and cost-effective solution to communicate modest amounts of data in certain parts of systems (such as between racks and, in certain cases, between boards within a rack), it is often difficult to scale these photonic components to meet the bandwidth, size, and power requirements of input/output (I/O) interfaces for future chips.

Alternatively, optical interconnects or links based on silicon photonics are attractive candidates for interconnect technology because they can be readily scaled on optical integrated circuits. However, it can be difficult to integrate optical integrated circuits with conventional integrated circuits in existing chip packages.

Hence, what is needed is a chip package that does not suffer from the above-described problems.

SUMMARY

One embodiment of the present disclosure provides a chip package that includes: an integrated circuit having a front surface with integrated-circuit connector pads; integrated-circuit electrical connectors electrically coupled to the integrated-circuit connector pads; a substrate having a top surface, facing the front surface, with first substrate connector pads electrically coupled to the integrated-circuit electrical connectors, and second substrate connector pads; and optical-integrated-circuit electrical connectors electrically coupled to the second substrate connector pads. Moreover, the chip package includes an optical integrated circuit having a front surface, facing the top surface, with optical-integrated-circuit connector pads electrically coupled to the optical-integrated-circuit electrical connectors, where the optical integrated circuit is proximate to the integrated circuit on a same side of the substrate, and the optical integrated circuit communicates optical signals. Furthermore, the chip package includes an input/output (I/O) integrated circuit between the front surface of the optical integrated circuit and the top surface of the substrate, where the I/O integrated circuit is coupled to the optical integrated circuit, and the I/O integrated circuit contains high-speed I/O circuits as well as energy-efficient driver and receiver circuits to communicate with the optical devices on the optical integrated circuit. It may also serialize/deserialize data

Note that the integrated circuit may be adjacent to the optical integrated circuit.

Additionally, the substrate includes: third substrate connector pads disposed on a bottom surface on an opposite side of the substrate from the top surface; and through-substrate vias (TSVs) electrically coupling the first substrate connector pads to the third substrate connector pads, and the second substrate connector pads to the third substrate connector pads. The TSVs may convey power and ground to the integrated circuit and the optical integrated circuit.

In some embodiments, the chip package includes a ramp-stack chip package electrically coupled to the third substrate connector pads, where the ramp-stack chip package includes multiple parallel substrates arranged at an oblique angle relative to the bottom surface. Moreover, the third substrate connector pads may have a lower pitch than a pitch of the first substrate connector pads and a pitch of the second substrate connector pads.

Moreover, the optical integrated circuit may include: ramp-stack connector pads disposed on a back surface on an opposite side of the optical integrated circuit from the front surface; TSVs electrically coupling the optical-integrated-circuit connector pads to the ramp-stack connector pads; ramp-stack electrical connectors electrically coupled to the ramp-stack connector pads; and the ramp-stack chip package electrically coupled to the ramp-stack electrical connectors, where the ramp-stack chip package includes the multiple parallel substrates arranged at the oblique angle relative to the back surface.

Furthermore, the I/O integrated circuit may communicate with the integrated circuit via the substrate.

Additionally, the chip package may include an optical fiber edge coupled to the optical integrated circuit. Alternatively, the chip package may include an optical fiber vertically coupled to the optical integrated circuit. For example, the optical fiber may be coupled to the front surface of the optical integrated circuit and/or the optical fiber may be coupled to the back surface of the optical integrated circuit on the opposite side of the optical integrated circuit from the front surface of the optical integrated circuit.

In some embodiments, the chip package includes an optical source between the optical integrated circuit and the substrate, where the optical source is optically coupled to the front surface of the optical integrated circuit.

Note that the substrate may include: a ceramic, an organic material, a glass, and/or a semiconductor.

Moreover, the chip package may include a thermal-cooling mechanism on a back surface of the integrated circuit on an opposite side of the integrated circuit from the front surface of the integrated circuit.

Furthermore, the chip package may include an interposer between the front surface of the integrated circuit and the top surface of the substrate.

Another embodiment provides a system that includes a processor, a memory coupled to the processor and the chip package.

Another embodiment provides a method for communicating electrical signals between the integrated circuit and the optical integrated circuit. During the method, the electrical signals are conveyed from the integrated-circuit connector pads on the front surface of the integrated circuit to the first substrate connector pads on the top surface of the substrate via the integrated-circuit electrical connectors, where the front surface faces the top surface. Then, the electrical signals are conveyed via traces disposed on the substrate, where the traces electrically couple the first substrate connector pads and the second substrate connector pads on the top surface. Moreover, the electrical signals are conveyed from the second substrate connector pads to the optical-integrated-circuit connector pads on the front surface of the optical integrated circuit via the optical-integrated-circuit electrical connectors, where the front surface of the optical integrated circuit faces the top surface, and the optical integrated circuit is proximate to the integrated circuit on the same side of the substrate. Next, the electrical signals are communicated from the front surface of the optical integrated circuit to the I/O integrated circuit between the front surface of the optical integrated circuit and the substrate. Furthermore, the electrical signals and/or optical signals are communicated with optical devices of the optical integrated circuit using the I/O integrated circuit.

DETAILED DESCRIPTION

Embodiments of a chip package, a system that includes the chip package, and a technique for communicating electrical signals between an integrated circuit and an optical integrated circuit in the chip package are described. This chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit, which are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit serializes and deserializes data in the electrical signals communicated between the integrated circuit and the optical integrated circuit.

By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects. In particular, the chip package may provide multi-terabit per second optical communication in conjunction with high-performance electrical circuits. In this way, the chip package may meet the escalating demands of off-chip bandwidth, while providing higher bandwidth density and improved energy efficiency compared to electrical interconnects.

We now describe the chip package. Hybrid integration is a pragmatic approach that allows silicon photonic devices and VLSI circuits to be combined. The chip package described here contains hybrid-integrated electronic-photonic elements, where the electronics and photonics have been built on individually optimized technology platforms and then bonded together using a low-parasitic flip-chip-assembly technique, such as thermocompression or reflow bonding.

FIG. 1presents a block diagram illustrating a side view of a chip package100, such as a wavelength-division-multiplexing photonic input/output (I/O)-enabled hybrid-integrated chip package. In chip package100, integrated circuit110(such as a switch chip or a high-performance processor that requires ultrahigh off-chip bandwidth, and which is sometimes referred to as a ‘payload IC’) may be flip-chip bonded to substrate118. In particular, chip package100includes: integrated circuit110having a surface112with integrated-circuit connector pads114; integrated-circuit electrical connectors116electrically coupled to integrated-circuit connector pads114; a substrate118having a surface120, facing surface112, with substrate connector pads122electrically coupled to integrated-circuit electrical connectors116, and substrate connector pads124; and optical-integrated-circuit electrical connectors126electrically coupled to substrate connector pads124. For example, substrate118may include: a ceramic, an organic material, a glass, and/or a semiconductor.

Moreover, chip package100includes an optical integrated circuit128-1(which is sometimes referred to as a ‘photonic bridge chip’ or a ‘photonic IC’) having a surface130, facing surface120, with optical-integrated-circuit connector pads132electrically coupled to optical-integrated-circuit electrical connectors126, where optical integrated circuit128-1is proximate to integrated circuit110on a same side of substrate118, and optical integrated circuit128-1communicates optical signals. As shown inFIG. 1, optical integrated circuit128-1is adjacent to integrated circuit110. In an exemplary embodiment, optical integrated circuit128-1is fabricated on a silicon-on-insulator substrate and includes optical components, such as optical waveguides, modulators, photodetectors, etc.

Furthermore, chip package100includes an I/O integrated circuit134between surfaces120and130, where I/O integrated circuit134is coupled to optical integrated circuit128-1, and I/O integrated circuit134serializes/deserializes data in the electrical signals. For example, VLSI I/O integrated circuit134may be hybrid integrated onto a physically larger optical integrated circuit128-1and, in addition to interfacing optical integrated circuit128-1with energy-efficient photonic driver and receiver circuits, I/O integrated circuit134may serialize/deserialize data. Thus, I/O integrated circuit134may accept parallel data from integrated circuit110, serialize the data and encode the data onto a photonic-modulator driver signal. Conversely, I/O integrated circuit134may accept serial electrical data from the photodetectors on optical integrated circuit128-1, and may convert the electrical data into parallel inputs to transmit electrically to integrated circuit110. However, other combinations of serial or parallel data transmission may also be used. In some embodiments, the integrated circuit-I/O integrated circuit interface consists of a multiple moderate-speed electrical links (e.g., 1-5 Gbps per channel), whereas the I/O integrated circuit-optical integrated circuit interface may include a smaller number of high-speed serial links (e.g., greater than 14 Gbps per channel).

Note that the hybrid integration may be achieved using a flip-chip attachment technique using thermocompression or reflow-bonded microbump technology. The bump and hybrid bond-pad sizes may be designed to minimize parasitic capacitance. The hybrid-integrated VLSI I/O integrated circuit134may be surrounded by a field of C4-type solder interconnects (e.g., C4 bumps, lead-free bumps, copper-pillar bumps, etc.). Consequently, I/O integrated circuit134may need to be thinned down to be shorter than the height of the collapsed C4 bumps to prevent interference with subsequent assembly of the hybrid component to substrate118. Alternatively, compliant, rematable interconnects may be used instead of C4-type interconnects.

Moreover, hybrid-integrated optical integrated circuit128-1may be flip-chip attached adjacent to integrated circuit110with a small or minimal gap between the two to minimize the electrical chip-to-chip interconnect wire length. Integrated circuit110may also be flip-chip attached to substrate118. In general, the density of flip-chip interconnects may ultimately be constrained by physical limitations in the package-substrate manufacturing process.

As described further below with reference toFIG. 11, I/O integrated circuit134may communicate with integrated circuit110via substrate118. In particular, substrate118may include: substrate connector pads136disposed on a surface138on an opposite side of substrate118from surface120; and through-substrate vias (TSVs)140electrically coupling substrate connector pads122to substrate connector pads136, and substrate connector pads124to substrate connector pads136. In addition, substrate118may include multiple layers of wiring on surfaces120and138for signal and power ground routing, as well as redistribution. Therefore, TSVs140may convey power and ground to integrated circuit110and optical integrated circuit128-1, and optical integrated circuit128-1may convey power and ground to I/O integrated circuit134.

During operation, integrated circuit110may communicate with I/O integrated circuit134via wiring on substrate118, and on-chip wiring on optical integrated circuit128-1. These electrical signals may also traverse two off-chip interconnects and microbump. Thus, the electrical signals may go from: integrated circuit110to substrate118via integrated-circuit electrical connectors116; substrate118to optical integrated circuit128-1via optical-integrated-circuit electrical connectors126; and optical integrated circuit128-1to I/O integrated circuit134via the microbumps. While this communication may involve a large number of moderate-speed rated off-chip interconnects on integrated circuit110and optical integrated circuit128-1, this configuration minimizes the wire-length of ultrahigh speed electrical signals between the I/O integrated circuit134and optical integrated circuit128-1.

A portion of optical integrated circuit128-1may extend beyond an edge of substrate118. As shown inFIG. 1, and described further below with reference toFIGS. 2-4, this configuration may provide physical space for attachment of at least one optical fiber142to optical integrated circuit128-1(more may be used depending on the bandwidth requirements). This optical fiber may carry high-speed optical signals to and from chip package100.

In particular, optical fiber142may be vertically coupled to surface130of optical integrated circuit128-1. Alternatively, as shown inFIG. 2, which presents a block diagram illustrating a side view of a chip package200, optical fiber142may be vertically coupled to surface144of optical integrated circuit128-1on the opposite side of optical integrated circuit128-1from surface130.

Alternatively, optical fiber142may be edge coupled to optical integrated circuit128-1. For example, as shown inFIG. 3, which presents a block diagram illustrating a side view of a chip package300, optical fiber142may be edge coupled to surface130of optical integrated circuit128-1and/or optical fiber142may be edge coupled to surface144. This latter configuration is shown inFIG. 4, which presents a block diagram illustrating a side view of a chip package400.

When optical fiber142is coupled to surface144, optical integrated circuit128-1may include additional elements, such as minors, lenses and/or through optical vias (with or without an optically transmissive material). This configuration may leave surface130clear for attachment to substrate118and underfill. In addition, optical integrated circuit128-1and optical fiber142may not have to be pre-assembled.

Optical fiber142(or another dedicated optical fiber) may be used to bring in light from an off-package optical source (e.g., one or more lasers). Alternatively, as shown inFIG. 5, which presents a block diagram illustrating a side view of a chip package500, an optional optical source or gain material510may be included between optical integrated circuit128-1and substrate118. For example, optional optical source510may be optically coupled to surface130of optical integrated circuit128-1. In this case, optional optical source510may be thinner than the surrounding C4-type bumps.

In some embodiments, chip package500includes an optional thermal-cooling mechanism512on a surface514of integrated circuit110on an opposite side of integrated circuit110from surface112. This optional thermal-cooling mechanism may include a heat sink. Moreover, optional thermal-cooling mechanism512may also extend to (back-side) surface144of optical integrated circuit128-1. Furthermore, the heat sink may have some topology if the chips have different heights. If optical fiber142interfaces with surface144, it may share space with optional thermal-cooling mechanism512. In addition, in embodiments with optional optical source510, chip package500may include an appropriate thermal-management technique for optional optical source510.

In order to maximize the number of off-chip data channels, and therefore the bandwidth, multiple optical integrated circuits128may be placed adjacent to each edge of integrated circuit110. This is illustrated inFIG. 6, which presents a block diagram illustrating a top view of a multi-chip module (MCM)600.

In an exemplary embodiment, MCM600is assembled by attaching the optional optical source using hybrid bonding or a fusion process. Then, the I/O integrated circuit may be hybrid integrated with optical integrated circuits128using fine-pitch microbumps. Moreover, integrated circuit110and optical integrated circuits128may be coupled to substrate118using C4-type interconnects. Furthermore, ball-grid-array interconnects may be coupled to surface138(FIG. 1) so substrate118can be attached to a printed-circuit board. Additionally, the optical fibers may be optically coupled to optical integrated circuits128.

In some embodiments, the chip package includes low-latency, high-bandwidth interconnections to banks of high-density memory. This is shown inFIG. 7, which presents a block diagram illustrating a side view of a chip package700that includes a ramp-stack chip package710electrically coupled to substrate connector pads136, where ramp-stack chip package710includes multiple parallel substrates arranged at an oblique angle712relative to surface138. (For example, there may be as many as 80 substrates in ramp-stack chip package710.) Moreover, substrate connector pads136may have a lower pitch than a pitch of substrate connector pads122and/or a pitch of substrate connector pads124inFIG. 1). Furthermore, integrated circuit110may be coupled to ramp-stack chip package710by TSVs140and flip-chip interconnects.

Note that ramp-stack chip package710may increase memory and interconnect capacity in chip package700. While ramp-stack chip package710is used as an illustration inFIG. 7, in other embodiments memory stacks fabricated using other techniques, such as stacked with TSVs or assembled as vertical chips, are used.

In contrast with chip package100inFIG. 1, integrated circuit110is coupled to substrate118in chip package700, and optical integrated circuit128-1is hybrid integrated onto integrated circuit110. Note that optical integrated circuit128-1may include wavelength-division-multiplexing optical devices, and integrated circuit110may include optical-device driver and receiver circuits, as well as memory-controller circuitry. Moreover, chip package700may be constructed such that there is a point-to-point relationship between memory-control I/Os on integrated circuit110and I/Os of memory chips in ramp-stack chip package710.

While not shown inFIG. 7, surface120may include interconnects (such as a ball-grid array) for assembling chip package700onto a printed-circuit board. Therefore, chips mounted on these interconnects may need to be thinner than the height of these interconnects.

In some embodiments, ramp-stack chip package710and optical integrated circuit128-1are thermally managed from the top-side of chip package700. For example, a thermal-interface material may contact a heat-spreading feature on the mating printed-circuit board.

In another configuration, hybrid integration is used to bring photonic I/Os directly to a memory stack. This is shown inFIG. 8, which presents a block diagram illustrating a side view of a chip package800that includes: ramp-stack connector pads810disposed on surface144; TSVs812electrically coupling optical-integrated-circuit connector pads132to ramp-stack connector pads810; ramp-stack electrical connectors814electrically coupled to ramp-stack connector pads810; and ramp-stack chip package710electrically coupled to ramp-stack electrical connectors814, where ramp-stack chip package710includes the multiple parallel substrates arranged at an oblique angle712relative to surface144.

InFIG. 8, surface112of integrated circuit110is coupled to surface130of optical integrated circuit128-1. For example, integrated circuit110may be flip-chip bonded to optical integrated circuit128-1and integrated circuit110may be thinned down to a height that is less than the height or thickness of the flip-chip interconnects between optical integrated circuit128-1an substrate118. In some embodiments, chip package800includes one or more additional instances of the integrated circuit, such as optional integrated circuit816. These additional instances may increase the memory density and access in chip package800.

FIG. 9presents a block diagram illustrating a side view of a chip package900. In this chip package, ramp-stack chip package710is electrically coupled to one side of interposer910, and integrated circuit110is coupled to the other side of interposer910. Note that integrated circuit110is coupled to ramp-stack chip package710by TSVs912in interposer910(or through-glass vias if interposer910includes glass). These TSVs may have widths of 50-200 μm. Moreover, surface112of integrated circuit110is coupled to surface130of optical integrated circuit128-1. However, multiple memory stacks and/or optical integrated circuits may be coupled to interposer910to increase memory and interconnect capacity.

Interposer910may support dense redistribution wiring layers on one or both sides to allow for physical transformation of pad/bump pitch between the two sides of interposer910. In general, the integrated-circuit side of interposer910may have a much tighter pad pitch than the chip-package side. Furthermore, interposer910may be made of silicon, a glass, a ceramic and/or an organic material having a coefficient of thermal expansion that is very close to that of silicon. This feature may provide the thermo-mechanical latitude to use shorter and higher-density bumps on chips, but also to allow the chips to be bonded very close together.

Interposer910may also include flip-chip interconnects to assemble the entire subcomponent onto a package substrate or printed-circuit board. Therefore, chips mounted on the same side as the flip-chip interconnects (C4, copper pillars, etc.) may need to be thinner than the height of these interconnects.

In some embodiments, ramp-stack chip package710and optical integrated circuit128-1are thermally managed from the top-side of chip package900. For example, a thermal-interface material may contact a heat-spreading feature on the mating printed-circuit board.

Embodiments of the chip package may be used in a wide variety of applications.FIG. 10presents a block diagram illustrating a system1000that includes a chip package1010, such as one of the preceding embodiments of the chip package. This system may include an optional processor1012and/or an optional memory1014, which may be coupled to each other and chip package1010by a bus (not shown). Note that optional processor (or processor core)1012may support parallel processing and/or multi-threaded operation.

Optional memory1014in system1000may include volatile memory and/or non-volatile memory. More specifically, optional memory1014may include: ROM, RAM, EPROM, EEPROM, flash, one or more smart cards, one or more magnetic disc storage devices, and/or one or more optical storage devices. Moreover, optional memory1014may store an operating system that includes procedures (or a set of instructions) for handling various basic system services for performing hardware-dependent tasks. Moreover, optional memory1014may also store communications procedures (or a set of instructions) in a communication module. These communication procedures may be used for communicating with one or more computers, devices and/or servers, including computers, devices and/or servers that are remotely located with respect to the system1000.

Furthermore, optional memory1014may also include one or more program modules (or sets of instructions). Note that the one or more program modules may constitute a computer-program mechanism. Instructions in the various modules in optional memory1014may be implemented in: a high-level procedural language, an object-oriented programming language, and/or in an assembly or machine language. The programming language may be compiled or interpreted, i.e., configurable or configured, to be executed by optional processor (or processor core)1012.

System1000may include, but is not limited to: a server, a laptop computer, a communication device or system, a personal computer, a work station, a mainframe computer, a blade, an enterprise computer, a data center, a portable-computing device, a tablet computer, a cellular telephone, a supercomputer, a network-attached-storage (NAS) system, a storage-area-network (SAN) system, an electronic device, and/or another electronic computing device.

Note that embodiments of the chip package may be used in a variety of applications, including: VLSI circuits, communication systems (such as in wavelength division multiplexing), storage area networks, data centers, networks (such as local area networks), memory systems and/or computer systems (such as multiple-core processor computer systems). For example, the chip package may be included in a backplane that is coupled to multiple processor blades, or the chip package may couple different types of components (such as processors, memory, input/output devices, and/or peripheral devices). Thus, the chip package may perform the functions of: a switch, a hub, a bridge, and/or a router.

In general, system1000may be at one location or may be distributed over multiple, geographically dispersed locations. Moreover, some or all of the functionality of system1000may be implemented in one or more application-specific integrated circuits (ASICs) and/or one or more digital signal processors (DSPs). Furthermore, functionality in the preceding embodiments may be implemented more in hardware and less in software, or less in hardware and more in software, as is known in the art.

The preceding embodiments may include fewer components or additional components. For example, components in the chip package may be electrically coupled to each other using proximity-communication (P×C) connectors on surfaces of the components, such as: capacitive P×C connectors, inductive P×C connectors, conductive P×C connectors, and/or optical P×C connectors. Alternatively or additionally, the connectors may include compression-compliant microspring connectors. Moreover, components or features in one in embodiment may be used in another of the embodiments.

The chip package may also include additional features that facilitate assembly and that may help maintain in-plane (XY) alignment of components. In particular, components (such as integrated circuit110and/or optical integrated circuit128-1inFIG. 1) may be mechanically coupled to substrate118inFIG. 1by pairs of negative features on surfaces and positive features that mate with the corresponding pairs of negative features. For example, the negative features may include pits that are recessed below surfaces112,120and130inFIG. 1, and the positive features may include spherical balls that mate with the negative features (such as a ball-and-etch-pit structure), thereby aligning the components. (Alternatively or additionally, alignment in the chip package may be facilitated using positive features on surfaces112,120and130inFIG. 1, where these positive features protrude above these surfaces). In some embodiments, the pairs of negative features are proximate to corners of the components.

As noted above, mating the negative features and the positive features can provide highly accurate self-alignment in the XY plane of the components, as well as coplanarity control during assembly. For example, the alignment over surfaces112,120and/or130inFIG. 1may be within ±1 μm in the XY plane.

In some embodiments, components in the chip package are permanently attached after remateable alignment, for example, by using a post-alignment technique to permanently fix the chip-to-chip alignment. In particular, solder may be partially melted or reflowed at an elevated temperature to fuse components in the chip package to create a more permanent bond. However, in other embodiments, components in the chip package are remateably coupled, thereby facilitating rework of the chip package.

Moreover, although the chip package and the system are illustrated as having a number of discrete items, these embodiments are intended to be functional descriptions of the various features that may be present rather than structural schematics of the embodiments described herein. Consequently, in these embodiments, two or more components may be combined into a single component and/or a position of one or more components may be changed. Furthermore, features in two or more of the preceding embodiments may be combined with one another.

Note that surfaces on components should be understood to include surfaces of substrates or surfaces of layers deposited on these substrates (such as a dielectric layer deposited on a substrate). Additionally, note that components in the chip package may be fabricated, and the chip package may be assembled, using a wide variety of techniques, as is known to one of skill in the art.

We now describe the method.FIG. 11presents a flow diagram illustrating a method1100for communicating electrical signals between an integrated circuit and an optical integrated circuit, such as an integrated circuit and an optical integrated circuit in one of the preceding embodiments of the chip package. During the method, the electrical signals are conveyed from integrated-circuit connector pads on a front surface of the integrated circuit to first substrate connector pads on a surface of a substrate via the integrated-circuit electrical connectors (operation1110), where the front surface faces the top surface. Then, the electrical signals are conveyed via traces disposed on the substrate (operation1112), where the traces electrically couple the first substrate connector pads and second substrate connector pads on the top surface. Moreover, the electrical signals are conveyed from the second substrate connector pads on the surface to optical-integrated-circuit connector pads on a front surface of the optical integrated circuit via the optical-integrated-circuit electrical connectors (operation1114), where the front surface of the optical integrated circuit faces the top surface, and the optical integrated circuit is proximate to the integrated circuit on the same side of the substrate. Next, the electrical signals are communicated from the front surface of the optical integrated circuit to I/O integrated circuit (operation1116) between the front surface of the optical integrated circuit and the substrate. Furthermore, the electrical signals and/or optical signals are communicated with optical devices of the optical integrated circuit (operation1118) using the I/O integrated circuit.

In some embodiments, method1100includes additional or fewer operations. Moreover, the order of the operations may be changed, and/or two or more operations may be combined into a single operation.