A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.

BACKGROUND OF THE INVENTION

The subject matter of the present application relates to microelectronic packages and assemblies incorporating microelectronic packages.

Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is contained in a package having external terminals which, in turn, are electrically connected to a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face.

Microelectronic packages may be fabricated at the wafer level; that is, the enclosure, terminations and other features that constitute the package, are fabricated while the chips, or die, are still in a wafer form. After the die have been formed, the wafer is subject to a number of additional process steps to form the package structure on the wafer, and the wafer is then diced to free the individually packaged die. Wafer level processing may be a preferred fabrication method because it may provide a cost savings advantage, and because the footprint of each die package may be made identical, or nearly identical, to the size of the die itself, resulting in very efficient utilization of area on the printed circuit board to which the packaged die is attached. A die packaged in this manner is commonly referred to as wafer-level chip scale package or wafer-level chip sized package (WLCSP).

In order to save additional space on the substrate to which a packaged die is mounted, multiple chips may be combined in a single package by vertically stacking them. Each die in the stack must typically provide an electrical connection mechanism to either one or more other die in the stack, or to the substrate on which the stack is mounted, or to both. This allows the vertically stacked multiple die package to occupy a surface area on a substrate that is less than the total surface area of all the chips in the package added together. Such arrangements have, however, required the chips to be offset at least somewhat to provide access to the contacts of the upper chips for electrical connection thereto, as the routing for all of the multiple chips is done along the same surface of the package. This can also lead to complicated routing and for different paths to externally-connected logic between chips of the same package.

In light of the foregoing, certain improvements in multi-chip microelectronic packages can be made in order to improve electrical performance, particularly in assemblies which include such packages interconnected with one another or other packages.

SUMMARY OF THE INVENTION

An aspect of the present disclosure relates to a microelectronic package. The microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces. An encapsulant contacts at least the edge surface of the semiconductor die and extends in at least one of the lateral directions from the edge surface. Electrically conductive elements extend from the contacts of the semiconductor die and over the front face in at least one of the lateral directions to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies. The encapsulants of the first and second microelectronic elements define respective outwardly opposite surfaces. The package further includes a plurality of electrically conductive interconnects extending through the encapsulants of the first and second microelectronic elements. At least some of the conductive interconnects are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. The conductive interconnects are exposed at the outwardly opposite surfaces.

In an example, the first and second microelectronic elements can be affixed to one another such that the front faces of the first and second semiconductor dies confront one another. In another arrangement, the first and second microelectronic elements can be affixed to one another such that the front face of the second semiconductor die confronts the back face of the first semiconductor die. In yet another example, the first and second microelectronic elements can be affixed to one another such that the back faces of the first and second semiconductor dies confront one another.

At least one of the microelectronic elements can be configured such that the major surface of the encapsulant is co-planar with the front face of the respective semiconductor die. Similarly, at least one of the microelectronic elements can be configured such that the second major surface of the encapsulant is co-planar with the back face of the corresponding semiconductor die.

The conductive interconnects can include laser-etched openings extending between the outwardly opposite surfaces of the encapsulants and intersecting respective conductive elements, the openings being at least partially filled with a conductive metal. First ones of the conductive interconnects can be electrically connected with the first semiconductor die by respective conductive elements, and second ones of the conductive interconnects can be electrically connected with the second semiconductor die by respective conductive elements. In a particular example, a quantity of the first conductive interconnects can be equal to a quantity of the second conductive interconnects. Further, all of the conductive interconnects can be either first conductive interconnects or second conductive interconnects.

In an example, the first and second semiconductor dies can be memory chips having a greater number of active devices configured to provide memory storage array function than any other function. Each of the memory chips can include a dynamic random access memory (DRAM) storage array.

A microelectronic assembly can include a first microelectronic package according to the above description and a second microelectronic package. The second microelectronic package can define a first surface having terminals exposed thereon and a second surface having package contacts exposed thereon. The second microelectronic package can further include a microelectronic element disposed between the first and second surface and electrically connected with terminals and the package contacts. A plurality of conductive joining elements can be joined between confronting ends of the conductive interconnects of the first microelectronic package and the terminals of the second microelectronic package.

The microelectronic element of the second package can be a logic chip having a greater number of active devices configured to provide logic function than any other function. The second microelectronic package can further include a substrate on which the microelectronic element is mounted. The substrate can include conductive elements electrically connected between the microelectronic element and the terminals.

The terminals of the second package can be ends of wire bonds having bases joined to respective ones of the conductive elements. In such an example, the second microelectronic package can further include an encapsulation layer formed over a surface of the substrate and over at least a portion of the microelectronic element. The encapsulation layer can further extend along edge surfaces of the wire bonds and can separate the wire bonds. The encapsulation layer can define the first surface of the second package, and the end surfaces of the wire bonds can be uncovered by the encapsulation layer on the second surface thereof.

In an example, first ones of the conductive interconnects can be electrically connected with the first microelectronic element by respective conductive elements, second ones of the conductive interconnects that can be electrically connected with the second microelectronic element by respective conductive elements, and third ones of the conductive interconnects that can be connected with neither of the first or second microelectronic elements. The first microelectronic package can further include a third microelectronic package overlying the first microelectronic package and having package contacts joined with the ends of the third conductive elements that are exposed on the first surface of the encapsulants.

In an exemplary configuration the second microelectronic package can include a substrate defining the first surface of the second package and having third surface opposite the first surface, the microelectronic element being mounted on the third surface.

A system can include comprising the microelectronic assembly described above and one or more electronic components.

Another aspect of the present disclosure relates to a microelectronic package including first and second encapsulated microelectronic elements. Each microelectronic element includes a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces. Each microelectronic element further has an encapsulant contacting at least the edge surface of the respective semiconductor die and extending in at least one of the lateral directions from the edge surface so as to define a major surface coplanar with or parallel to the front face of the semiconductor die, and electrically conductive elements including metallized vias extending from the contacts of the semiconductor die and along the front face. At least some of the conductive elements extend beyond the edge surface to locations overlying the major surface of the encapsulant. The first and second microelectronic elements are affixed to one another such that the front faces confront one another and the major surfaces confront one another. The package further includes a plurality of electrically conductive interconnects extending through the encapsulants of the first and second microelectronic elements in a direction away from the major surfaces. At least some of the conductive interconnects are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. The conductive interconnects are exposed at first and second opposed surfaces of the encapsulants which are opposite the major surfaces.

Another aspect of the present disclosure relates to a method for making a microelectronic package. The method includes forming a plurality of electrically conductive interconnects through first and second encapsulated microelectronic elements. Each of the microelectronic elements includes a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces. An encapsulant contacts at least the edge surface of the respective semiconductor die and extends in at least one of the lateral directions from the edge surface. Electrically conductive elements extend from the contacts of the semiconductor die in at least one of the lateral directions to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies. The encapsulants of the first and second microelectronic elements define respective outwardly opposite surfaces. The conductive interconnects are formed through the encapsulants of the first and second microelectronic elements such that at least some of the conductive interconnects are electrically connected with at least one semiconductor die of the first and second microelectronic by the conductive elements. The conductive interconnects are exposed at the outwardly opposite surfaces.

The conductive interconnects can be formed by laser etching openings through the encapsulants of the first and second microelectronic elements and through respective ones of the conductive elements and by at least partially filling the openings with a conductive metal.

In an example, method can further including affixing the first and second microelectronic elements to one another such that the front faces confront one another. In another example, the method can further include affixing the first and second microelectronic elements to one another such that the front face of the second microelectronic element confronts the back face of the first microelectronic element. In yet another example, the method can further include affixing the first and second microelectronic elements to one another such that the back faces confront one another.

The conductive interconnects can be formed to include first conductive interconnects that are connected by respective conductive elements to the first microelectronic element and second conductive interconnects that are connected by respective conductive elements to the second microelectronic element. A quantity of first conductive interconnects formed in the package can be equal to a quantity of second conductive vias formed in the package. The conductive interconnects can be further formed to include third conductive interconnects that are free from other electrical connections within the package.

The method can further include forming the electrically conductive elements that extend along a dielectric region overlying the respective front faces of the semiconductor dies and the first major surfaces of the encapsulants. Forming the electrically conductive elements can include forming the conductive elements on at least one of the first or second microelectronic elements prior affixing the microelectronic elements together. Additionally or alternatively, forming the electrically conductive elements can include forming the conductive elements on a dielectric region overlying at least one of the first or second microelectronic elements before affixing the microelectronic elements together.

Another aspect of the present disclosure relates to a method for making a microelectronic assembly. The method includes making a first microelectronic package by a steps including forming a plurality of electrically conductive interconnects through first and second encapsulated microelectronic elements. Each of the microelectronic elements includes a semiconductor die having a front face extending in first and second lateral directions, a plurality of contacts on the front face, a back face opposite the front face, and an edge surface extending between the front and back faces. An encapsulant contacts at least the edge surface of the respective semiconductor die and extends in at least one of the lateral directions from the edge surface. Electrically conductive elements including metalized vias extend from the contacts of the semiconductor die in at least one of the lateral directions to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards and adjacent to one of the front or back surfaces of the other of the first and second semiconductor dies. The encapsulants of the first and second microelectronic elements define respective outwardly opposite surfaces. The conductive interconnects are formed through the encapsulants of the first and second microelectronic elements such that at least some of the conductive interconnects are electrically connected with at least one semiconductor die of the first and second microelectronic by the conductive elements. The conductive interconnects are exposed at the outwardly opposite surfaces. The method further includes positioning the first microelectronic package over a second microelectronic package including a logic chip electrically connected with terminals exposed on a first surface of the second package and package contacts exposed on a second surface of the second microelectronic package. The method further includes joining ends of the conductive interconnects of the first microelectronic package that face the second microelectronic package with the terminals of the second microelectronic package using a plurality of conductive joining elements.

The method can further include positioning a third microelectronic package over the first microelectronic package, the third microelectronic package including terminals exposed on a surface thereof that is positioned to confront the first package. In such an example, the method can further include joining terminals of the third microelectronic package with ends of the conductive interconnects that are disposed toward the third microelectronic package.

The conductive interconnects can be formed to include first conductive interconnects connected by respective conductive elements to the first microelectronic element, second conductive interconnects connected by respective conductive elements to the second microelectronic element, and third conductive interconnects that are free from other electrical connections within the package. The terminals of the third microelectronic package can be joined with ends of the third conductive interconnects, the third conductive interconnects electrically connecting the third package to the second package.

DETAILED DESCRIPTION

Turning now to the figures, where similar numeric references are used to indicate similar features, there is shown inFIG. 1a microelectronic assembly10in the form a first microelectronic package12stacked over a second microelectronic package50. In an example, assembly10can be in the form of a memory-on-logic assembly in which first package12is a memory package and second package50is a logic package, although the arrangements described herein can be used in arrangements with packages of different types or combinations of different types. Both first12and second50packages include one or more respective semiconductor dies18and26that themselves include a plurality of active devices. A memory package can be a package with semiconductor dies that have a majority of active devices configured for a memory storage array function. Similarly, a logic package can be one in which a majority of the active devices therein are configured to execute processor functions.

First microelectronic package12can include first and second encapsulated microelectronic elements14and16. Each of the encapsulated microelectronic elements14,16includes a semiconductor die18. As mentioned above, these semiconductor dies18can be in the form of memory chips such as DRAM chips or the like. In other examples, the semiconductor dies18can be in the form of application-specific integrated circuit (ASIC) chips. Various combinations of ASIC and memory chips are also possible within package12. Semiconductor die18further includes a front face20that extends in lateral directions and has element contacts26exposed thereon. A back face22is positioned opposite front face20and is generally parallel thereto. Edge surfaces24extend between front face20and back face22defining an outer periphery of die18.

An encapsulant28at least partially surrounds semiconductor die18. Encapsulant can be made from a dielectric material and can be molded or otherwise formed at least partially around die18. Encapsulant28can contact one or more edge surfaces24of die18and can extend away therefrom in one or more lateral directions normal to the edge surfaces24. In an example, front face20and back face22can be rectangular or square and four corresponding edge surfaces24can extend between respective sides of front and back faces20,22. Encapsulant28can surround all four edge surfaces24and can extend away therefrom to give the microelectronic element14or16a rectangular shape. Encapsulant18includes first and second major surfaces30and32that are respectively associated with and parallel to front and back faces20and22of the semiconductor die18. In some examples, encapsulant28can further contact back face22and extend away therefrom such that second major surface32overlies back face32. In other embodiments, such as that shown inFIG. 1, front and back faces and22can be uncovered by encapsulant28such that first major surface30extends substantially co-planar with front face20and/or second major surface32extends substantially co-planar with back face22.

Each microelectronic element14and16can further include a dielectric region48overlying at least the front faces of the semiconductor dies18. As seen inFIG. 1A, the dielectric region48may extend beyond the edge surface24of the semiconductor die18to overlie first major surface30of the encapsulant28. The dielectric region48may be partly or entirely made of any suitable dielectric material. For example, the dielectric region48may comprise a layer of flexible material, such as a layer of polyimide, BT resin or other dielectric material of the commonly used for making tape automated bonding (“TAB”) tapes. Alternatively, the dielectric region48may comprise a relatively rigid, board like material such as a thick layer of fiber-reinforced epoxy, such as, Fr-4 or Fr-5 board. Regardless of the material employed, the dielectric region30may include a single layer or multiple layers of dielectric material.

As shown in the detail view ofFIG. 1A, conductive elements can be connected with the contacts26of the semiconductor dies18. Specifically, conductive vias38can extend through dielectric region48to connect with contacts26of semiconductor die18. Additional conductive features such as traces36can connect with the conductive vias38and can extend away therefrom in one or more lateral directions along dielectric region48over face20and can further over first major surface30of encapsulant28to connect with one or more contacts26that can be positioned at various locations along first major surface30. Such conductive element can be made from a conductive metal such as copper, gold, silver, nickel, aluminum, or various alloys thereof.

As further shown inFIG. 1A, first microelectronic element14and second microelectronic element16can be assembled together such that the front faces20of the respective semiconductor dies18confront one another. In such an arrangement the first major surfaces30of the respective encapsulants28can confront each other as well. Microelectronic elements can be joined together by a bonding layer44that can be an adhesive, a molded dielectric, or the like that can be bonded between the dielectric regions48of the microelectronic elements and40. Bonding layer44can be further configured to surround and insulate conductive elements, such as traces36and contacts26. In the example shown, bonding layer44spaces apart microelectronic element14and16such that the routing patterns of the traces18do not interfere with one another. In other examples, the routing patterns of the respective first and second microelectronic elements14,16can be structured to be laterally spaced apart from each other such that the microelectronic elements14and16can be spaced closer together.

Conductive interconnects40can extend through the encapsulants28of both first and second microelectronic element14and16such that end surfaces46A thereof are exposed on the second major surfaces32of the encapsulant28of first microelectronic element14and opposite end surfaces46B are exposed on the second major surface32of the encapsulant28of second microelectronic element16. Conductive interconnects40can also extend through and connect with respective ones of the conductive elements associated with either of the microelectronic elements14and16. In the example ofFIG. 1A, conductive element40A connects with a pad34at the end of a trace36that extends along major surface30and front face20of microelectronic element14and connects to a respective contact of the semiconductor die18of microelectronic element14. Similarly, conductive element40B connects with a pad34at the end of another trace36that extends along major surface30and front face20of microelectronic element16and connects to a respective contact26of the semiconductor die18of microelectronic element16. By this arrangement a number of connections can be made between the second major surfaces32of the microelectronic elements14and16and either semiconductor die18. This can allow, for example, connection to the semiconductor dies18of both microelectronic elements14and16by ends46B of the conductive interconnections40that are exposed at second major surface32of microelectronic element16or vice versa. Conductive interconnects can be metalized vias that are formed by plating a conductive metal into an opening that can be formed through the encapsulants and through portions of conductive elements disposed therebetween by etching, drilling or the like, as will be described in further detail below. Conductive metals for interconnects40can include copper, gold, silver, nickel, aluminum or various alloys thereof.

Conductive interconnects40can be arranged in any configuration or pattern within encapsulants28. In the example shown inFIG. 2, conductive interconnects40are arranged in an area array pattern in which interconnects40are laid out in a grid pattern of various rows and columns of interconnects40within encapsulants18and surrounding semiconductor dies18. The interconnects40within such an array can be spaced apart from one another according to a pitch of the array that can be less than, for example 500 microns and in another examples between about 250 and 300 microns. The array can be configured to align with an array of terminals58in second package50, for example, to facilitate a particular electrical connection between packages by joining terminals58with, for example, ends46B of conductive interconnects40. This can allow for connection between, for example microelectronic element52and the semiconductor dies18of both microelectronic elements14and16in first package12.

The conductive elements of the respective microelectronic elements14and16can be arranged such that only a single contact26on one of the semiconductor dies18is connected with a corresponding conductive interconnect40. For example, the pads34of the respective microelectronic elements14and16can be arranged in different arrays or other pattern that each partially corresponds to the array of conductive interconnects40. Such partially corresponding patterns can be different as between microelectronic elements14and16such that none of the pads34associated with microelectronic element14occupy a position of a pad34associated with microelectronic element16, and vice versa. Numerous configurations are possible for such different patterns. In one example, all of the pads34of microelectronic element16can be positioned inside the array of pads34of microelectronic element14. In another example, the pads34of microelectronic element14can alternate in an array with the pads34of microelectronic element16, with further arrangements being possible. Traces36can be routed such that they do not contact any features within package12other than a single pad34and a single contact26on a corresponding semiconductor die18.

As mentioned previously, conductive interconnects40can be positioned to connect with terminals29of second package50, which in an example can be a logic package. As shown inFIG. 1, second package50can be in the form of a microelectronic element52carried on a substrate54with terminals58on a surface of an encapsulant that overlies substrate. Terminals58can be end surfaces of interconnects56that extend from conductive elements that extend along a surface of the substrate54to connect with microelectronic element52by, for example, conductive masses70. Interconnects can be in any of a number of configurations and can include conductive pins or posts. In another example, interconnects56can be in the form of wire bonds, as described in U.S. Pat. No. 7,391,121 to Otremba, in U.S. Pat. App. Pub. No. 2005/0095835 (describing a wedge-bonding procedure that can be considered a form of wire bonding), and in commonly-assigned U.S. patent application Ser. Nos. 13/462,158; 13/404,408; 13/405,108; 13/405,125; and 13/404,458, the disclosures of which are incorporated herein by reference in their entireties. Substrate54can include redistribution to connect package contacts exposed on the substrate54opposite terminals58with microelectronic element52to facilitate connection between assembly10and other microelectronic devices in a microelectronic system. In an embodiment, package contacts60can connect with terminals on a circuit panel or the like (not shown) by conductive joining masses. Such package contacts60can be arranged in a pattern or array as shown inFIG. 3and can be input and output connections for assembly10.

As shown inFIG. 4an additional package12B can be stacked on top of package12A. Package12B can be of a similar configuration as package12A, which itself is similar to package described above with respect toFIGS. 1-3. In such an example, package12A can be adapted to facilitate an electrical connection between package12B and package50. To accomplish this, some of the conductive interconnects40within package12A can be unconnected with either of the semiconductor dies18within package12A. Such interconnects40can further be unconnected with any conductive elements, such as pads34or traces36within package12A. These unconnected interconnects40within package12A can connect with conductive interconnects40within package12B, which themselves can be connected with either of the semiconductor dies18therein in a manner similar to that discussed above with respect to package12inFIG. 1A. In a further example, some of the conductive interconnects40within package12B can themselves be unconnected with either of the semiconductor dies18in package12B and can, along with unconnected interconnects40within package12A can facilitate an electrical connection between package50and a still further package (not shown) stacked on top of package12B. The uppermost package in such a stacked arrangement can be similar to package12A or12B, as shown inFIG. 4or can be another form of a packaged microelectronic element (or microelectronic elements) with contacts exposed at least on a surface that faces the conductive interconnects40of a package beneath it.

FIG. 5shows an assembly110that is a variation of the assembly ofFIG. 1. In particular, assembly110includes a first package112that is similar in construction to that of package12inFIGS. 1-3. Assembly110further includes a second package150that is similar to package50inFIGS. 1-4but is configured such that the ends158of the interconnects56are disposed away from package112and act as contacts for connection of assembly110with external components, such as a circuit panel or the like. Accordingly, the contacts on substrate154opposite the microelectronic element152act as terminals160to which the ends146B of the conductive interconnects146of package112are connected using conductive joining masses70or the like. In such an arrangement, interconnects156can be in the form of encapsulated wire bonds, as described above to achieve a fine-pitch for the contacts160that are the ends of the interconnects156. Redistribution through substrate154(or layers thereof) can provide for the desired configuration of terminals158to connect with conductive interconnects140. Further packages (not shown) can be included in the assembly110in a similar way to that described above with respect toFIG. 4.

FIGS. 6-10show the various components of assembly10during steps of fabrication thereof in a method according to an embodiment of the present disclosure. In particular,FIG. 6shows first microelectronic element14and second microelectronic element16prior to assembly together. Microelectronic elements14and16can be formed as reconstituted wafer-level packages. That is, they can be formed in a wafer with a plurality of semiconductor dies that are embedded in an encapsulant layer. The wafer can then be diced or segmented into individual microelectronic elements including, for example, a single semiconductor die with a portion of the encapsulant surrounding at least a portion thereof. Other process steps can be used to create the particular package, including grinding one or more surfaces of the encapsulant to create major surfaces30and32that are flush with the front20and back22faces of the semiconductor die18, which themselves can be thinned by such a grinding process. Before or after segmentation, the conductive elements, including the pads34, traces36and conductive vias38can be formed along front face20of the semiconductor die18and the first major surface30of the encapsulant28according to the principles discussed above. An additional dielectric layer can optionally be formed over the portions of first major surface30and front face20not covered by conductive elements.

As shown inFIG. 6, the microelectronic elements14and16can then be positioned such that front faces20and first major surfaces30confront one another with their respective conductive elements appropriately positioned with respect to each other as described above. The microelectronic elements14and16can then be bonded together by an adhesive layer or a curable dielectric material layer disposed between microelectronic elements14and16. In some embodiments such a layer can intersperse between conductive elements when microelectronic elements14and16are moved together. Such bonding can result in the in-process unit12′ shown inFIG. 7.

The in-process unit ofFIG. 7can then be processed to form openings through the encapsulants28of the first and second microelectronic elements14and16and through desired portions of the conductive elements associated therewith. In an example, wherein the pads34associated with microelectronic elements14and16are arranged in an array when microelectronic elements14and16are assembled together, the openings42can be made through the pads34and the portions of the areas of the encapsulants28that overlie the pads34. In the example shown, openings42can extend completely through in-process unit12such that they are open to second major surfaces32of both microelectronic elements14and16. In other embodiments, such as when the package being made is intended as a topmost package in a stack the openings can extend from a single one of the second major surfaces32to a depth adequate to extend through the pads34. Openings42can be made by drilling, etching or the like. Etching can be done using a chemical etchant or the like with a mask layer being at least temporarily over second major surfaces32. In another example, openings42can be formed by laser etching. Laser etching can be advantageous because it can use specially-configured equipment that can locate and target the portions of in-process unit12′ for formation of holes42based on detection of pads34.

Openings42can then be filled with a conductive metal, such as copper or other metals discussed above, to form conductive interconnects40. This can be done by plating the conductive metal into the holes. Such plating can be done by electroplating or electroless plating and can be done after depositing a seed layer or the like within openings42. When used such a seed layer can be conductive to allow for electrical connection between conductive interconnects40and pads34or other conductive elements. In some embodiments, the ends46of the conductive interconnects40can be planarized by grinding or the like so that they become substantially flush with second major surfaces32. In other examples, contacts can be formed over the ends46of the interconnects40to provide additional area for connection to other components.

As shown inFIG. 10, package12is then aligned with package50such that the conductive interconnects40, in particular the faces46B thereof, align with the desired terminals58of package50. In one example, package50can be formed as a package including encapsulated wire bond interconnects by any of the methods described in above-referenced commonly-assigned U.S. patent application Ser. Nos. 13/462,158; 13/404,408; 13/405,108; 13/405,125; and 13/404,458. Faces46B of interconnects40are then joined with respective terminals58using conductive joining masses70such as solder balls or the like to form a package such as that shown inFIG. 1. Additional steps can be performed, including the formation of additional packages that are similar to package12that can be further assembled over package12with the conductive interconnects of such an additional package connected with certain ones of the conductive interconnects40of package12, as described above with respect toFIG. 4.

FIG. 11shows a microelectronic assembly210that includes a package212assembled with another microelectronic package250, wherein package250can be similar to package50discussed with respect toFIG. 1. Package212can be a variation of package12shown inFIG. 1with many common characteristics. In particular, package212can include first and second microelectronic elements214and216that include semiconductor dies218with encapsulants228at least partially surrounding the semiconductor dies218. Each microelectronic element214and216can include respective conductive elements including conductive vias238connected with contacts226of the respective semiconductor dies218and traces36extending along the front faces20and the first major surfaces30to pads34. The first and second microelectronic elements214and216in the embodiment shown inFIG. 11can be assembled together such that the first major surface230of microelectronic element214confronts the second major surface232of microelectronic element216. Further, in such an arrangement front face220of the semiconductor die218of first microelectronic element214confronts the back surface222of the semiconductor die218of the second microelectronic element216.

In the arrangement ofFIG. 11, the locations of the conductive elements, in particular the pads234of the respective microelectronic packages214and216can be determined in a similar way to those of microelectronic package12ofFIGS. 1-4. In particular, pads234can be positioned such that each conductive interconnect240passes through only one pad234of only one of the microelectronic elements214or216. Also, as in package12ofFIGS. 1-4some of the conductive interconnects240can be free from electrical connections with either of the semiconductor dies218within package212and can be used to connect another package (not shown) stacked on top of package212with terminals258of package250.

The method of fabricating assembly210can also be similar to the fabrication method of assembly10as described inFIGS. 6-10but with microelectronic elements214and216being positioned in the back-to-front arrangement described above when being assembled together. Further, the conductive elements of second microelectronic element216can be formed after assembly thereof with first microelectronic element214.

FIG. 12shows another variation of a microelectronic assembly310that includes a package312assembled with another microelectronic package350, wherein package350can be similar to package50discussed with respect toFIG. 1. Package312can be a variation of package12shown inFIG. 1with many common characteristics. In particular, package312can include first and second microelectronic elements314and316that include semiconductor dies318with encapsulants328at least partially surrounding the semiconductor dies318. Each microelectronic element314and316can include respective conductive elements including conductive vias338connected with contacts326of the respective semiconductor dies318and traces336extending along the front faces320and the first major surfaces330to pads334. The first and second microelectronic elements314and316in the embodiment shown inFIG. 12can be assembled together such that the second major surfaces330of the microelectronic elements214and216confront each other. Further, in such an arrangement the back faces322of the semiconductor dies218of the first and second microelectronic elements214and216can confront each other.

In the arrangement ofFIG. 12, the locations of the conductive elements, in particular the pads334of the respective microelectronic packages314and316can be determined in a similar way to those of microelectronic package12ofFIGS. 1-4. In particular, pads334can be positioned such that each conductive interconnect340passes through only one pad334of only one of the microelectronic elements314or316. Also, as in package12ofFIGS. 1-4some of the conductive interconnects340can be free from electrical connections with either of the semiconductor dies318within package312and can be used to connect another package (not shown) stacked on top of package312with terminals358of package350. In some variations of package312ofFIG. 12, conductive pads334of second microelectronic element316are exposed on package312and confront terminals358of package35and, thus, can be directly connected therewith by solder balls370or the like. Accordingly, such pads334may not require any conductive interconnects340to be associated therewith. In such an example, conductive interconnects340can connect with pads of first microelectronic element314and can also be unconnected within package312for connection with additional packages (not shown) assembled above package312.

The method of fabricating assembly310can also be similar to the fabrication method of assembly10as described inFIGS. 6-10but with microelectronic elements314and316being positioned in the back-to-back arrangement described above when being assembled together. Further, the conductive elements of first and second microelectronic element314and316can be formed after being assembled together.

The structures discussed above can be utilized in construction of diverse electronic systems. For example, a system1in accordance with a further embodiment of the invention includes microelectronic package10, as described above with respect toFIGS. 1-4, in conjunction with other electronic components2and3. In the example depicted, component2is a semiconductor chip whereas component3is a display screen, but any other components can be used. Of course, although only two additional components are depicted inFIG. 13for clarity of illustration, the system may include any number of such components. The microelectronic package10as described above may be, for example, a microelectronic package as discussed above in connection withFIG. 1, or a structure incorporating plural microelectronic packages as discussed with reference toFIG. 4. Package10can further include any one of the embodiments described inFIG. 11 or 12. In a further variant, multiple variations may be provided, and any number of such structures may be used.

Microelectronic package10and components2and3are mounted in a common housing4, schematically depicted in broken lines, and are electrically interconnected with one another as necessary to form the desired circuit. In the exemplary system shown, the system includes a circuit panel5such as a flexible printed circuit board, and the circuit panel includes numerous conductors6, of which only one is depicted inFIG. 13, interconnecting the components with one another. However, this is merely exemplary; any suitable structure for making electrical connections can be used.

The housing4is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen3is exposed at the surface of the housing. Where microelectronic package10includes a light-sensitive element such as an imaging chip, a lens7or other optical device also may be provided for routing light to the structure. Again, the simplified system shown inFIG. 13is merely exemplary; other systems, including systems commonly regarded as fixed structures, such as desktop computers, routers and the like can be made using the structures discussed above.