C2C YIELD AND PERFORMANCE OPTIMIZATION IN A DIE STACKING PLATFORM

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

TECHNICAL FIELD

At least one embodiment pertains to a chip-to-chip (C2C) serializer and deserializer (SERDES) apparatus. For example, at least one embodiment pertains to C2C yield and performance optimization in a die stacking platform.

BACKGROUND

In the data processing field, integrated circuits (dies) are fabricated on a semiconductor material such as electronic-grade silicon. The dies are manufactured with functional circuitry that can function as microcontrollers, microprocessors, logic gates, computer memory, and the like. The dies are placed within a package on top of a printed circuit board (PCB) and can communicate with each other via electrical connections within the substrate. As semiconductor manufacturing technologies continue to improve, the size of the dies continues to decrease.

One technology that has been developed to maximize the available die capabilities, while keeping up with the decreasing die size is called die stacking. Die stacking refers to the process of stacking two or more dies on top of each other within a single semiconductor package. In stacked die platforms, a first die (or primary die) is connected to a substrate within the semiconductor package, and subsequent dies are stacked on top. The first die is connected is connected via solder bumps or other forms of connection to the substrate. The solder bumps can also be connected to peripheral devices to allow for communication between the stacked dies and the peripheral devices. The communication between the stacked dies and the peripheral devices is done via a C2C (chip to chip) serializer and deserializer (SERDES). Die stacking can significantly increase the number of dies used within a single package while conserving the available area on the substrates. When dies are stacked, rather than placed side by side, the electrical connections between dies and other circuitry can be shortened, which can result in faster signal propagation and noise and cross-talk reduction, therefore resulting in better electrical performance of the device.

Large platforms implementing die stacking technologies may use thousands of C2C links between the different dies. As such, platform failure or limited performance due to a single C2C input/output (C2C I/O) is common. This can be due to mechanical or assembly failure (e.g., soldering disconnections), electrical failure (e.g., silicon defects), or the like. Thus, C2C yield and optimization improvements to address platform failure are desired.

DETAILED DESCRIPTION

Technologies for C2C yield and performance optimization in a die stacking platform are described. As described above, large platforms implementing die stacking technologies may use thousands of C2C links between the different dies, making platform failure or limited performance due to a single C2C I/O common. Conventionally, there are two types of solutions to overcome C2C I/O failure or limited performance. The first solution is used by incorporating redundant C2C I/Os into the silicon of each die (also known as lane repair). Using this method, failing C2C I/Os are disabled and redundant C2C I/Os are activated within the dies to take the place of the failing C2C I/Os. The second solution is used by periodically calibrating and optimizing the C2C I/O performance (e.g., calibrating C2C I/Os in order to overcome aging or slow temperature variations that might lead to high bit error ratios (BERs)). In using the first solution, adding redundant C2C I/Os to the silicon of each die may lower the overall throughput of the C2C interconnect solution. Therefore, there is a tradeoff between the throughput and yield, constraining the platform yield. In using the second solution, the calibration has to be performed in either a very short time or in the background, since there are C2C standards (such as high bandwidth interconnect (HBI) standards) that operate continuously and prevent link stoppage for calibration.

Aspects and embodiments of the present disclosure address these and other challenges by providing a die configuration on a substrate to optimize C2C yield and performance. Aspects and embodiments of the present disclosure can provide integrated circuits disposed on a substrate. A first integrated circuit can be disposed on the substrate at a first location. A second integrated circuit can be disposed on the substrate at a second location. A third integrated circuit can be disposed on the second integrated circuit. The second and third integrated circuits can each comprise a C2C interface. The C2C interfaces of the second and third integrated circuits can be coupled to the first integrated circuit via a physical terminal. Only one of the C2C interfaces of the second and third integrated circuits can be active at a time. The configuration of the integrated circuits and the C2C interfaces can enable high platform yield and performance compared to conventional systems.

FIG.1Aillustrates an example communication system100with a stacked die platform140, in accordance with at least some embodiments. The system100includes a device110, a communication network108including a communication channel109, and a device112. In at least one example embodiment, devices110and112correspond to one or more of a Personal Computer (PC), a laptop, a tablet, a smartphone, a server, a collection of servers, or the like. In some embodiments, the devices110and112may correspond to any appropriate type of device that communicates with other devices also connected to a common type of communication network108. According to embodiments, the receiver104A,104B of devices110or112may correspond to a graphics processing unit (GPU), a switch (e.g., a high-speed network switch), a network adapter, a central processing unit (CPU), a data processing unit (DPU), etc. As another specific but non-limiting example, the devices110and112may correspond to servers offering information resources, services, and/or applications to user devices, client devices, or other hosts in the system100.

Examples of the communication network108that may be used to connect the devices110and112include an Internet Protocol (IP) network, an Ethernet network, an InfiniBand (IB) network, a Fibre Channel network, the Internet, a cellular communication network, a wireless communication network, combinations thereof (e.g., Fibre Channel over Ethernet), variants thereof, and/or the like. In one specific, but non-limiting example, the communication network108is a network that enables data transmission between the devices110and112using data signals (e.g., digital, optical, wireless signals).

The device110includes a transceiver116for sending and receiving signals, for example, data signals. The data signals may be digital or optical signals modulated with data or other suitable signals for carrying data.

The transceiver116may include a digital data source120, a transmitter102, a receiver104A, and processing circuitry132that controls the transceiver116. The digital data source120may include suitable hardware and/or software for outputting data in a digital format (e.g., in binary code and/or thermometer code). The digital data output by the digital data source120may be retrieved from memory (not illustrated) or generated according to input (e.g., user input).

The transmitter102includes suitable software and/or hardware for receiving digital data from the digital data source120and outputting data signals according to the digital data for transmission over the communication network108to a receiver104B of device112.

The receiver104A,104B of device110and device112may include suitable hardware and/or software for receiving signals, for example, data signals from the communication network108. For example, the receivers104A,104B may include components for receiving processing signals to extract the data for storing in a memory.

The processing circuitry132may comprise software, hardware, or a combination thereof. In at least one embodiment, the processing circuitry132includes the stacked die platform140. The stacked die platform140includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the first integrated circuit, and peripheral integrated circuits disposed at various locations on the substrate. The first integrated circuit is coupled to one or more of the peripheral integrated circuits using at least a first chip-to-chip (C2C) interface via a physical terminal. Second integrated circuit is to one or more of the peripheral integrated circuits using at least a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time. For example, the first integrated circuit and the second integrated circuit may make up one or more of an Integrated Circuit (IC) chip, a CPU, a GPU, a DPU, a microprocessor, a Field Programmable Gate Array (FPGA), or the like. The peripheral integrated circuits may make up one or more peripheral devices including serial interfaces, parallel input-output devices, hardware controllers, or the like. Additional details of the stacked die platform140are discussed in more detail below with reference to the figures. For example, the processing circuitry132may include a memory including executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include Flash memory, Random Access Memory (RAM), Read Only Memory (ROM), variants thereof, combinations thereof, or the like. In some embodiments, the memory and processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally, or alternatively, the processing circuitry132may comprise hardware, such as an application-specific integrated circuit (ASIC). Other non-limiting examples of the processing circuitry132include an Integrated Circuit (IC) chip, a CPU, A GPU, a DPU, a microprocessor, a Field Programmable Gate Array (FPGA), a collection of logic gates or transistors, resistors, capacitors, inductors, diodes, or the like. Some or all of the processing circuitry132may be provided on a Printed Circuit Board (PCB) or collection of PCBs. Additionally, it should be appreciated that any other appropriate type of electrical component or collection of electrical components may be suitable for inclusion in the processing circuitry132. The processing circuitry132may send and/or receive signals to and/or from other elements of the transceiver116to control the overall operation of the transceiver116.

The transceiver116or selected elements of the transceiver116may take the form of a pluggable card or controller for the device110. For example, the transceiver116or selected elements of the transceiver116may be implemented on a network interface card (NIC).

The device112may include a transceiver136for sending and receiving signals, for example, data signals over a channel109of the communication network108. The same or similar structure of the transceiver116may be applied to transceiver136, and thus, the structure of transceiver136is not described separately.

Although not explicitly shown, it should be appreciated that devices110and112and the transceivers116and136may include other processing devices, storage devices, and/or communication interfaces generally associated with computing tasks, such as sending and receiving data.

FIG.1Billustrates a block diagram of an example communication system150employing stacked die platforms140a-bin a transmitter102and a receiver104, according to at least one embodiment. In the example shown inFIG.1B, a PAM level-4 (PAM4) modulation scheme is employed with respect to the transmission of a signal (e.g., digitally encoded data) from the transmitter (TX)102to a receiver (RX)104via a communication channel106(e.g., a transmission medium). In this example, the transmitter102receives101an input data (i.e., the input data at time n is represented as “a(n)”), which is modulated in accordance with a modulation scheme (e.g., PAM4) and sends the signal103a(n) including a set of data symbols (e.g., symbols −3, −1, 1, 3, wherein the symbols represent coded binary data). It is noted that while the use of the PAM4 modulation scheme is described herein by way of example, other data modulation schemes can be used in accordance with embodiments of the present disclosure, including, for example, a non-return-to-zero (NRZ) modulation scheme, PAM7, PAM8, PAM16, etc. For example, for an NRZ-based system, the transmitted data symbols consist of symbols −1 and 1, with each symbol value representing a binary bit. This is also known as a PAM level-2 or PAM2 system as there are two unique values of transmitted symbols. Typically, a binary bit 0 is encoded as −1, and a bit 1 is encoded as 1, as the PAM2 values.

In the example shown, the PAM4 modulation scheme uses four (4) unique values of transmitted symbols to achieve higher efficiency and performance. The four levels are denoted by symbol values −3, −1, 1, 3, with each symbol representing a corresponding unique combination of binary bits (e.g., 00, 01, 10, 11).

The communication channel106is a destructive medium in that the channel acts as a low pass filter which attenuates higher frequencies more than it attenuates lower frequencies, introduces inter-symbol interference (ISI) and noise from cross talk, power supplies, Electromagnetic Interference (EMI), or other sources. The communication channel106can be over serial links (e.g., a cable, printed circuit boards (PCBs) traces, copper cables, optical fibers, or the like), read channels for data storage (e.g., hard disk, flash solid-state drives (SSDs), high-speed serial links, deep space satellite communication channels, applications, or the like.

As described above, in some communication systems, the transmitter102sends the signal103as a data signal without a transmitter clock used to generate the data signal. The receiver (RX)104receives an incoming signal105over the channel106. The stacked die platforms140a-bcan be used to make up the electrical circuitry in the transmitter102and the receiver104as described herein. For example, the stacked die platforms140a-bmay replace conventional circuitry that would conventionally make up the electrical circuitry in the transmitter102and the receiver104as described herein.

FIG.2illustrates an example of an apparatus including a stacked die platform comprising multiple integrated circuits mounted on a substrate, according to at least one embodiment. The apparatus includes a stacked die platform200, which includes a substrate202, a first integrated circuit204disposed on the substrate202at a first location, a second integrated circuit206disposed on the first integrated circuit204, and peripheral integrated circuits208a-1disposed in various locations on the substrate202. In at least one embodiment, the substrate202may be a common substrate. In at least one embodiment, the stacked die platform200may correspond to any appropriate type of device that comprises an integrated circuit. In some embodiments, the stacked die platform200may correspond to one or more of a personal computer (PC), a laptop, a tablet, a video processor, a memory chip, a microcontroller, a server, or the like. For example, the first integrated circuit204and the second integrated circuit206may correspond to a central processing unit (CPU), and the peripheral integrated circuits208a-1may correspond to various peripheral devices (e.g., serial interfaces, parallel input-output devices, hardware controllers, etc.).

The first integrated circuit204is coupled to one or more of the peripheral integrated circuits208a-1using a first chip-to-chip (C2C) interface via a first physical terminal. The second integrated circuit206is coupled to the first integrated circuit204using a second C2C interface via the first physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

In at least one embodiment, one or more peripheral integrated circuits208a-1may be coupled to the first integrated circuit204and the second integrated circuit206using a third C2C interface via the physical terminal. In other embodiments, the one or more of the peripheral integrated circuits208a-1may additionally be coupled to the first integrated circuit204and the second integrated circuit206using a third C2C interface via the physical terminal and a fourth C2C interface via the physical terminal. The fourth C2C interface is a redundant C2C interface.

In at least one embodiment, the first integrated circuit204may be coupled to the same or other peripheral integrated circuits208a-1using one or more additional C2C interfaces via one or more additional physical terminals. Additionally, the second integrated circuit206may be coupled to the first integrated circuit204using one or more additional C2C interfaces via the one or more additional physical terminals. For example, the first integrated circuit204may be coupled to one or more of the peripheral integrated circuits208a-1using the first C2C interface via the first physical terminal and a third C2C interface via a second physical terminal. The second integrated circuit206may be coupled to the first integrated circuit204using the second C2C interface via the first physical terminal and a fourth C2C interface via the second physical terminal.

In at least one embodiment, the C2C interfaces of the second integrated circuit206may be connected to the physical terminals via one or more through-silicon vias (TSVs). For example,FIG.4illustrates an exemplary embodiment that includes TSVs and will be described in more detail below.

In at least one embodiment, the first integrated circuit204and the second integrated circuit206may be manufactured to be substantially the same or with only minor differences. For example, the top of the first integrated circuit204or the bottom of the second integrated circuit206may comprise one or more metal plates to facilitate the connection of the C2C interfaces of the second integrated circuit206to one or more physical terminals. In some embodiments, one or more metal plates can be used to facilitate the connection of the C2C interfaces of the second integrated circuit206to the one or more physical terminals via one or more TSVs (described below).

In at least one embodiment, the substrate202may be a silicon interposer. The silicon interposer may include physical terminals to electrically connect to integrated circuits or other electronic elements. Multiple physical terminals may be electrically connected to each other to enable the connection between different integrated circuits or other electronic elements. In embodiments, the physical terminals may be made up of solder bumps located on a first side of the first integrated circuit204.

In at least one embodiment, the first integrated circuit204and the second integrated circuit206are stacked integrated circuits, and the peripheral integrated circuits208a-1are single dies or tile dies disposed on the silicon interposer corresponding to one or more peripheral devices. One or more additional integrated circuits (not illustrated) may be disposed on top of one or more of the peripheral integrated circuits208a-l. The second integrated circuit206and the one or more additional integrated circuits may be stacked integrated circuits on the silicon interposer.

In at least one embodiment, one or more additional integrated circuits (not illustrated) may be disposed on top of the second integrated circuit206. The one or more additional integrated circuits may be coupled to each other using one or more additional C2C interfaces via physical terminals. The one or more additional C2C interfaces may be coupled to the physical terminals via one or more TSVs (described below).

In at least one embodiment, one or more additional integrated circuits (not illustrated) may be disposed on top of one or more of the peripheral integrated circuits208a-1. The one or more additional integrated circuits may be coupled to each other using one or more additional C2C interfaces via physical terminals. The one or more additional C2C interfaces may be coupled to the physical terminals via one or more TSVs (described below).

In at least one embodiment, one or more additional integrated circuits may be disposed on a different location on the substrate202. For example, a first additional integrated circuit may be disposed on a different location on the substrate202, and a second additional integrated circuit may be disposed on top of the first additional integrated circuit. The additional integrated circuits may be connected to the first integrated circuit204and the second integrated circuit206via the physical terminal.

FIG.3Ais a block diagram illustrating the operations of an apparatus including a stacked die platform with redundancy only in the main dies, according to at least one embodiment. The block diagram illustrates an apparatus including a stacked die platform300A, which includes a substrate302that comprises a first integrated circuit304and a second integrated circuit306. In at least one embodiment, the substrate302may be a common substrate. The substrate302also comprises a peripheral integrated circuit308and a physical terminal316. The first integrated circuit304is coupled to a peripheral integrated circuit308using a first C2C interface via a physical terminal316. The first C2C interface includes a first C2C I/O318and a first switch330. The first switch330is coupled to the physical terminal316. The second integrated circuit306is coupled to the first integrated circuit304using a second C2C interface via the physical terminal316. The second C2C interface includes a second C2C I/O320and a second switch332. The second switch332is coupled to the physical terminal316. Only one of the first C2C I/O318of the first C2C interface and the second C2C I/O320of the second C2C interface is active at a time.

In at least one embodiment, the first switch330may couple the first C2C I/O318to the physical terminal316when the first C2C I/O318is active. The second switch332may couple the second C2C I/O320to the physical terminal316when the second C2C I/O320is active. The first integrated circuit304may further include a first C2C link monitoring logic324coupled to the first switch330and the first C2C I/O318. The first C2C link monitoring logic324may control the first switch330when the first C2C I/O318is to be made active or inactive. The second integrated circuit306may further include a second C2C link monitoring logic326coupled to the second switch332and the second C2C I/O320. The second C2C link monitoring logic326may control the second switch332when the second C2C I/O320is to be made active or inactive. In at least one embodiment, the peripheral integrated circuit308may couple to the first integrated circuit304and the second integrated circuit306via the physical terminal316via a third C2C interface. The third C2C interface may include a third C2C I/O322. The peripheral integrated circuit308may include a third C2C link monitoring logic328to monitor input and output via the third C2C I/O322. In at least one embodiment, the first integrated circuit304may include first digital blocks310coupled to the first C2C I/O318, the second integrated circuit306may include second digital blocks312coupled to the second C2C I/O320, and the peripheral integrated circuit308may include third digital blocks314coupled to the third C2C I/O322. The first digital blocks310, the second digital blocks312, and the third digital blocks314may be capable of performing various computing operations (e.g., logic gates, memory functions, etc.).

In an exemplary embodiment, the first C2C I/O318may be active initially, and the second C2C I/O320may be inactive initially. The first C2C I/O318may communicate signals from the first digital blocks310, through the first C2C I/O318and the third C2C I/O322, and into the third digital blocks314. During operation, the first C2C link monitoring logic324and/or the second C2C link monitoring logic326may observe failed communication through the first C2C I/O318. In response to the failed communication, the first C2C link monitoring logic324may cause the first switch330to be turned off, and the second C2C link monitoring logic326may cause the second switch332to be turned on. This may disable any communication from the first C2C I/O318and enable communication from the second C2C I/O320. Once the first switch330is turned off and the second switch332is turned on, communication from the second digital blocks312through the second C2C I/O320and the third C2C I/O322and into the third digital blocks314is enabled. This provides redundancy between the first integrated circuit304and the second integrated circuit306.

In at least one embodiment, the substrate302may be a silicon interposer. The silicon interposer may include physical terminals, including physical terminal316, to connect to integrated circuits or other electronic elements. The physical terminals may be made up of solder bumps. Multiple physical terminals may be electrically connected to each other to enable the connection between the same or different integrated circuits or other electronic elements.

In at least one embodiment, the first integrated circuit304and the second integrated circuit306are stacked integrated circuits, and peripheral integrated circuit308is a single die, or a tile die corresponding to one or more peripheral devices.

In at least one embodiment, the first integrated circuit304may be coupled to the peripheral integrated circuit308or other peripheral integrated circuits (not illustrated) via one or more additional physical terminals. The second integrated circuit306may be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. The peripheral integrated circuit308may also be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. For example, the first integrated circuit304may be coupled to the peripheral integrated circuit308using the first C2C interface via the physical terminal316and an additional C2C interface via an additional physical terminal. The second integrated circuit306may be coupled to the first integrated circuit304using the second C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal. The peripheral integrated circuit308may also be coupled to the first integrated circuit304using the third C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal.

FIG.3Bis a block diagram illustrating the operations of an apparatus including a stacked die platform with redundancy in both the main dies and the tile die, according to at least one embodiment. As similarly described above inFIG.3A, the block diagram illustrates an apparatus including a stacked die platform300B, which includes a substrate302that comprises a first integrated circuit304and a second integrated circuit306. In some embodiments, the substrate302may be a common substrate. The substrate302also comprises a peripheral integrated circuit308and a physical terminal316. The first integrated circuit304is coupled to a peripheral integrated circuit308using a first C2C interface via the physical terminal316. The first C2C interface includes a first C2C I/O318and a first switch330. The first switch330is coupled to the physical terminal316. The second integrated circuit306is coupled to the first integrated circuit304using a second C2C interface via the physical terminal316. The second C2C interface includes a second C2C I/O320and a second switch332. The second switch332is coupled to the physical terminal316. Only one of the first C2C I/O318of the first C2C interface and the second C2C I/O320of the second C2C interface is active at a time.

In at least one embodiment, the first switch330may couple the first C2C I/O318to the physical terminal316when the first C2C I/O318is active. The second switch332may couple the second C2C I/O320to the physical terminal316when the second C2C I/O320is active. The first integrated circuit304may further include a first C2C link monitoring logic324coupled to the first switch330and the first C2C I/O318. The first C2C link monitoring logic324may control the first switch330when the first C2C I/O318is to be made active or inactive. The second integrated circuit306may further include a second C2C link monitoring logic326coupled to the second switch332and the second C2C I/O320. The second C2C link monitoring logic326may control the second switch332when the second C2C I/O320is to be made active or inactive. In some embodiments, the peripheral integrated circuit308may couple to the first integrated circuit304and the second integrated circuit306via the physical terminal316via a third C2C interface.

According to at least one embodiment, the third C2C interface may include a third C2C I/O322, a fourth C2C I/O338, a third switch334, a fourth switch340, and a third C2C link monitoring logic328. The third switch334may be coupled to the physical terminal316, the third C2C I/O322, and the third C2C link monitoring logic328. The fourth switch340may be coupled to the physical terminal316, the fourth C2C I/O338, and the third C2C link monitoring logic328. The third switch334may couple the third C2C I/O322to the physical terminal316when the third C2C I/O322is active. The fourth switch340may couple the fourth C2C I/O338to the physical terminal316when the fourth C2C I/O338is active. The third C2C link monitoring logic328may control the third switch334based on whether the third C2C I/O322is to be active or inactive. The third C2C link monitoring logic328may also control the fourth switch340based on whether the fourth C2C I/O338is active or inactive.

In at least one embodiment, the first integrated circuit304may include first digital blocks310coupled to the first C2C I/O318, the second integrated circuit306may include second digital blocks312coupled to the second C2C I/O320, and the peripheral integrated circuit308may include third digital blocks314coupled to the third C2C I/O322and the fourth C2C I/O338. The first digital blocks310, the second digital blocks312, and the third digital blocks314may be capable of performing various computing operations (e.g., logic gates, memory functions, etc.).

In an exemplary embodiment, the first C2C I/O318and the third C2C I/O322may initially be active. The second C2C I/O320and the fourth C2C I/O338may initially be inactive. The first C2C I/O318may communicate signals from the first digital blocks310, through the first C2C I/O318and the third C2C I/O322, and into the third digital blocks314. During operation, the first C2C link monitoring logic324, the second C2C link monitoring logic326, and/or the third C2C link monitoring logic328may observe failed communication through the first C2C I/O318and the third C2C I/O322. In response to the failed communication, the first C2C link monitoring logic324may cause the first switch330to be turned off, the second C2C link monitoring logic326may cause the second switch332to be turned on, and the third C2C link monitoring logic328may cause the third switch334to be turned off and the fourth switch340to be turned on. This provides redundancy between the first integrated circuit304and the second integrated circuit306, along with redundancy within the peripheral integrated circuit308.

In at least one embodiment, as described above, the substrate302may be a silicon interposer. The silicon interposer may include physical terminals, including the physical terminal316, to connect to integrated circuits or other electronic elements. The physical terminals may be made up of solder bumps. Multiple physical terminals may be electrically connected to each other to enable the connection between different integrated circuits or other electronic elements.

In at least one embodiment, as described above, the first integrated circuit304and the second integrated circuit306are stacked integrated circuits, and the peripheral integrated circuit308is a single die or a tile die corresponding to one or more peripheral devices.

In at least one embodiment, as described above, the first integrated circuit304may be coupled to the peripheral integrated circuit308or other peripheral integrated circuits (not illustrated) via one or more additional physical terminals. The second integrated circuit306may be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. The peripheral integrated circuit308may also be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. For example, the first integrated circuit304may be coupled to the peripheral integrated circuit308using the first C2C interface via the physical terminal316and an additional C2C interface via an additional physical terminal. The second integrated circuit306may be coupled to the first integrated circuit304using the second C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal. The peripheral integrated circuit308may also be coupled to the first integrated circuit304using the third C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal.

FIG.3Cis a block diagram illustrating the operations of an apparatus including two stacked die platforms connected to the same physical interface, according to at least one embodiment. As similarly described above inFIG.3A, the block diagram illustrates an apparatus including a stacked die platform300C, which includes a substrate302that comprises a first integrated circuit304, a second integrated circuit306, and a physical terminal316. In at least one embodiment, the substrate302may be a common substrate. In at least one embodiment, the substrate302also comprises a third integrated circuit346and a fourth integrated circuit336. The first integrated circuit304is coupled to the third integrated circuit346and a physical terminal316. The first integrated circuit304is coupled to the third integrated circuit346using a first C2C interface via the physical terminal316. The first C2C interface includes a first C2C I/O318and a first switch330. The first switch330is coupled to the physical terminal316. The second integrated circuit306is coupled to the first integrated circuit304using a second C2C interface via the physical terminal316. The second C2C interface includes a second C2C I/O320and a second switch332. The second switch332is coupled to physical terminal316. Only one of the first C2C I/O318of the first C2C interface and the second C2C I/O320of the second C2C interface is active at a time.

In at least one embodiment, the third integrated circuit346is coupled to the first integrated circuit304using a third C2C interface via the physical terminal316. The third C2C interface includes a third C2C I/O322and a third switch334. The third switch334is coupled to the physical terminal316. The fourth integrated circuit336is coupled to the third integrated circuit346using a fourth C2C interface via the physical terminal316. The fourth C2C interface includes a fourth C2C I/O338and a fourth switch340. The fourth switch340is coupled to the physical terminal316. Only one of the third C2C I/O322of the third C2C interface and the fourth C2C I/O338of the fourth C2C interface is active at a time.

In at least one embodiment, the first switch330may couple the first C2C I/O318to physical terminal316when the first C2C I/O318is active. The second switch332may couple the second C2C I/O320to the physical terminal316when the second C2C I/O320is active. The third switch334may couple the third C2C I/O322to the physical terminal316when the third C2C I/O322is active. The fourth switch340may couple the fourth C2C I/O338to the physical terminal316when the fourth C2C I/O338is active.

In at least one embodiment, the first integrated circuit304may further include the first C2C link monitoring logic324coupled to the first switch330and the first C2C I/O318. The first C2C link monitoring logic324may control the first switch330when the first C2C I/O318is to be made active or inactive. The second integrated circuit306may further include a second C2C link monitoring logic326coupled to the second switch332and the second C2C I/O320. The second C2C link monitoring logic326may control the second switch332when the second C2C I/O320is to be made active or inactive.

In at least one embodiment, the third integrated circuit346may further include a third C2C link monitoring logic328coupled to the third switch334and the third C2C I/O322. The third C2C link monitoring logic328may control the third switch334when the third C2C I/O322is to be made active or inactive. The fourth integrated circuit336may further include a fourth C2C link monitoring logic342coupled to the fourth switch340and the fourth C2C I/O338. The fourth C2C link monitoring logic342may control the fourth switch340when the fourth C2C I/O338is to be made active or inactive.

In at least one embodiment, the first integrated circuit304may include first digital blocks310coupled to the first C2C I/O318, the second integrated circuit306may include second digital blocks312coupled to the second C2C I/O320, the third integrated circuit346may include third digital blocks314coupled to the third C2C I/O322, and the fourth integrated circuit336may include fourth digital blocks344coupled to the fourth C2C I/O338. The first digital blocks310, the second digital blocks312, the third digital blocks314, and the fourth digital blocks344may be capable of performing various computing operations (e.g., logic gates, memory functions, etc.).

In an exemplary embodiment, the first C2C I/O318and the third C2C I/O322may initially be active. The second C2C I/O320and the fourth C2C I/O338may initially be inactive. The first C2C I/O318may communicate signals from the first digital blocks310, through the first C2C I/O318and the third C2C I/O322, and into the third digital blocks314or vice versa. During operation, the first C2C link monitoring logic324, the second C2C link monitoring logic326, the third C2C link monitoring logic328, and/or the fourth C2C link monitoring logic342may observe failed communication through the first C2C I/O318and the third C2C I/O322. In response to the failed communication, the first C2C link monitoring logic324may cause the first switch330to be turned off, the second C2C link monitoring logic326may cause the second switch332to be turned on, the third C2C link monitoring logic328may cause the third switch334to be turned off, and the fourth C2C link monitoring logic342may cause the fourth switch340to be turned on. This provides redundancy between the first integrated circuit304and the second integrated circuit306. This also provides redundancy within the third integrated circuit346and the fourth integrated circuit336.

In at least one embodiment, as described above, the substrate302may be a silicon interposer. The silicon interposer may include physical terminals, including the physical terminal316, to connect to integrated circuits or other electronic elements. The physical terminals may be made up of solder bumps. Multiple physical terminals may be electrically connected to each other to enable the connection between different integrated circuits or other electronic elements.

In at least one embodiment, the first integrated circuit304, the second integrated circuit306, the third integrated circuit346, and the fourth integrated circuit336are stacked integrated circuits.

In at least one embodiment, as described above, the first integrated circuit304may be coupled to the third integrated circuit346or additional peripheral integrated circuits (not illustrated) via one or more additional physical terminals. The second integrated circuit306may be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. The third integrated circuit346may also be coupled to the first integrated circuit304using one or more additional C2C interfaces via the one or more additional physical terminals. The fourth integrated circuit336may be coupled to the third integrated circuit346using one or more additional C2C interfaces via the one or more additional physical terminals. For example, the first integrated circuit304may be coupled to the third integrated circuit346using the first C2C interface via the physical terminal316and an additional C2C interface via an additional physical terminal. The second integrated circuit306may be coupled to the first integrated circuit304using the second C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal. The third integrated circuit346may be coupled to the first integrated circuit304using the third C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal. The fourth integrated circuit336may be coupled to the third integrated circuit346using the fourth C2C interface via the physical terminal316and an additional C2C interface via the additional physical terminal.

FIG.4illustrates an example of a stacked die platform with stacked dies connected to solder bumps using TSVs, according to at least one embodiment. In an exemplary embodiment, the stacked die platform400includes a first die402a, a second die402b, and a third die402c. The bottom of the first die402aincludes a first flip-chip bump408a, a second flip-chip bump408b, and a third flip-chip bump408c. The bottom of second die402bincludes a fourth micro-bump404d, a fifth micro-bump404e, and a sixth micro-bump404f. The bottom of the third die402cincludes a first micro-bump404a, a second micro-bump404b, and a third micro-bump404c. The stacked die platform400further includes a first TSV406a, a second TSV406b, and a third TSV406c. The first TSV406acouples the first micro-bump404a, the fourth micro-bump404d, and the first flip-chip bump408a. The second TSV406bcouples the second micro-bump404b, the fifth micro-bump404e, and the second flip-chip bump408b. The third TSV406ccouples the third micro-bump404c, the sixth micro-bump404f, and the third flip-chip bump408c. When the first TSV406a, the second TSV406b, and the third TSV406care each connected to their respective micro-bumps and flip-chip bumps, they extend from the third die402c, through the second die402b, and through the first die402a. The first flip-chip bump408ais coupled to the substrate410and a first electrical connection412a. The first electrical connection412aextends through the substrate410and couples to a first solder bump414a. The second flip-chip bump408bis coupled to the substrate410and a second electrical connection412b. The second electrical connection412bextends through the substrate410and couples to a second solder bump414b. The third flip-chip bump408cis coupled to the substrate410and a third electrical connection412c. The third electrical connection412cextends through the substrate410and couples to a third solder bump414c.

As described above, in at least one embodiment, the C2C interfaces of the integrated circuits (e.g., the second integrated circuit206, the second integrated circuit306) may be connected to the physical terminals (e.g., the physical terminal316) via one or more TSVs. For example, the first die402amay represent the first integrated circuit204, and the second die402bmay represent the second integrated circuit206. The substrate402may represent the substrate202, and the first solder bump414amay represent the physical terminal ofFIG.2. As described above inFIG.2, the first integrated circuit204may be connected to the substrate202via one or more physical terminals. The second integrated circuit206may be connected to the one or more physical terminals via one or more TSVs as currently described inFIG.4. In some embodiments, if one or more additional dies are added on top of the package (as described inFIGS.2and3A-C), the one or more TSVs can be extended through the stacked dies into the topmost die.

In an exemplary embodiment, the first die402a, the second die402b, and the third die402cmay include integrated circuitry similar to those described inFIGS.3A-C. The first die402a, the second die402b, and the third die402cmay each include one or more digital blocks, C2C I/Os, C2C link monitoring logic, and/or switches. For example, the first die402amay include one or more digital blocks, a C2C I/O, C2C link monitoring logic, and/or a switch coupled to the flip-chip bump408a. Similar circuitry may be connected to the flip-chip bump408band the flip-chip bump408c. The second die402band the third die402cmay also have similar circuitry connected to the micro-bumps404a-f. This arrangement may facilitate redundancy between the first die402a, the second die402b, and the third die402c.

In at least one embodiment, the stacked die platform400may include additional dies stacked on top of the third die402cor placed at a different location on the substrate410. The additional dies may be a single die, multiple dies, tile dies, stacked dies, or any other types of die. The first die402a, the second die402b, and the third die402cmay be coupled to additional micro-bumps, flip-chip bumps, and/or TSVs. The substrate410may include additional solder bumps and additional electrical connections to facilitate additional connections between the first die402a, the second die402b, the third die402c, or any additional die or device that needs an electrical connection to the substrate. For example, any arrangement, such as those described inFIGS.2and3A-C, may be implemented using the exemplary electrical connections as implemented in stacked die platform400.

Other variations are within the spirit of the present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to a specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in appended claims.

Although descriptions herein set forth exemplary embodiments of described techniques, other architectures may be used to implement described functionality, and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibilities may be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.