Clock driver for a capacitance clock input

A circuit that produces a clocking signal for a low to medium capacitance input of a device includes a drive gate connected to a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through one coupling capacitor and to an emitter of a PNP bi-polar transistor through another coupling capacitor. The transistors are connected in a common-base configuration with the collectors of the transistors connected together. One voltage is connected to the base of the PNP transistor. Another voltage is connected to the base of the NPN transistor. A diode is connected in parallel with the base-emitter of the PNP transistor. Another diode is connected in parallel with the base-emitter of the NPN transistor. A damping resistor is connected between the collectors of the transistors and the low to medium capacitance clock input of the device.

TECHNICAL FIELD

The present invention relates generally to a circuit for producing a clocking signal for a capacitance clock input of a device.

BACKGROUND

FIG. 1is a simplified top view of a charge-coupled device (CCD) image sensor according to the prior art. Image sensor100includes an array101of photosensitive areas102arranged in rows and columns. The photosensitive areas102collect charge carriers in response to light striking the array101. Image sensor100is illustrated as a full frame image sensor, where photosensitive areas102also operate as shift elements in CCD vertical shift registers104. Accumulated charge packets106are shifted one row at a time through the vertical shift registers104to the horizontal shift register108. The charge packets106are then serially shifted through the horizontal shift register108to an output circuit110.

Circuit112outputs a CCD clocking signal (VCCD) that is transmitted to output circuit110on signal line114. The CCD clocking signal (VCCD) is input into a low to medium capacitance clock input that is used to reset a charge storage element to a known potential or voltage level. For example, a reset transistor200(seeFIG. 2) can be included in output circuit110, and the CCD clocking signal (VCCD) is received on the gate202of the reset transistor. The low to medium capacitance clock input includes the gate of the reset transistor200. The charge storage element to be reset to a known potential (e.g., element204) can be implemented as the last shift element116in horizontal shift register108or as a floating diffusion that receives charge from shift element116.

FIG. 3is a schematic diagram of a first circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Drive gate300receives an input signal VIN, inverts the VINsignal, and outputs a clocking signal VCCD. Drive gate300is power efficient and very fast, but is limited in the voltage swing it can produce. Generally, the voltage swing of drive gate300is limited to six volts due to the maximum supply voltage (VCC) rating.

FIG. 4is a schematic diagram of a second circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Circuit400includes drive gate300connected to a common-emitter bipolar driver circuit402. Circuit400has good power efficiency and is capable of producing a larger voltage swing in VCCDthan drive gate300is able to produce by itself. For example, the voltage swing for circuit400can be ten volts. But circuit400suffers from waveform distortion and speed limitations due to the inverting character of circuit400.

FIG. 5is a schematic diagram of a third circuit for producing a clocking signal for a capacitance clock input in accordance with the prior art. Circuit500uses two metal oxide semiconductor field-effect transistors502,504(MOSFET) instead of NPN and PNP bi-polar transistors404,406shown inFIG. 4. Circuit500operates more quickly and can produce even larger voltage swings than circuit400. But circuit500suffers from waveform distortion, and due to the unavailability of small enough MOSFETS, requires too much gate drive power to use at frequencies above 25 MHz.

SUMMARY

A circuit that produces a clocking signal for a low to medium capacitance clock input of a device includes a drive gate and a common-base bi-polar driver circuit. The output of the drive gate is connected to an emitter of an NPN bi-polar transistor through a first coupling capacitor and to an emitter of a PNP bi-polar transistor through a second coupling capacitor. The NPN and PNP bi-polar transistors are connected in a common base configuration with the collectors of the transistors connected together. A first DC voltage is connected between a base of the PNP bi-polar transistor and ground, while a second DC voltage is connected between a base of the NPN bi-polar transistor and ground. The first DC voltage is larger than the second DC voltage. A first diode is connected in parallel with the base emitter of the PNP transistor, with an anode of the diode connected to the base of the PNP transistor. A second diode is connected in parallel with the base emitter of the NPN transistor, with a cathode of the diode connected to the base of the NPN transistor. A damping resistor is connected between the collectors of the NPN and PNP bi-polar transistors and the low to medium capacitance clock input of the device. The device can be any type of device, including, but not limited to, a charge-coupled device (CCD).

DETAILED DESCRIPTION

Throughout the specification and claims the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, or data signal.

Referring to the drawings, like numbers indicate like parts throughout the views.

The present invention is described herein in conjunction with a low to medium capacitance CCD clock input in an image sensor. Embodiments in accordance with the invention are not limited to this implementation. The present invention can be used to drive any device having a low to medium capacitance clock input, including, but not limited to, a capacitor.

FIG. 6is a schematic diagram of a circuit for producing a CCD clocking signal in an embodiment in accordance with the invention. Circuit600includes drive gate602and common-base bi-polar driver circuit604. Drive gate602is implemented as an inverter that receives an input signal VINfrom clock source606in an embodiment in accordance with the invention. Drive gate602can be configured differently in other embodiments in accordance with the invention. For example, drive gate602can be implemented as a non-inverting buffer.

Common-base bi-polar driver circuit604includes NPN bi-polar transistor608and PNP bi-polar transistor610. An output of drive gate602is connected to an emitter of an NPN bi-polar transistor608through coupling capacitor612. The output of drive gate602is also connected to an emitter of a PNP bi-polar transistor610through coupling capacitor614.

The NPN bi-polar transistor608and the PNP bi-polar transistor610are connected in a common-base configuration with the collectors of the transistors608,610connected together. In the common-base configuration, the emitters of the bi-polar transistors608,610serve as the input to the transistors608,610. The collectors of the transistors608,610serve as the outputs. DC voltage supply616is connected to the base of PNP bi-polar transistor610. DC voltage supply618is connected to the base of NPN bi-polar transistor608. In the illustrated embodiment, the output of DC voltage supply616is larger than the output DC voltage supply618.

Diode620is connected in parallel with the base-emitter of the PNP transistor610, with an anode of the diode620connected to the base of the PNP transistor610. Diode622is connected in parallel with the base-emitter of NPN transistor608, with a cathode of the diode622connected to the base of the NPN transistor608. Diodes620,622are implemented as Shottky diodes in an embodiment in accordance with the invention. Damping resistor624is connected between the collectors of the NPN bi-polar transistor608and the PNP bi-polar transistor610and the low to medium capacitance CCD clock input626.

As used herein, the term “clock input” refers to a capacitance input for a device. In the illustrated embodiment, the clock input is the low to medium capacitance CCD clock input626. By way of example only, a low capacitance CCD clock input can be the reset gate or last horizontal phase input, which typically have a capacitance in the order of 20 pF. A medium capacitance CCD clock input can be a H-register of a CCD image sensor, which typically has a capacitance up to approximately 300 pF. For comparison, an exemplary high capacitance CCD clock input can be the V-registers of a CCD image sensor, which typically has a capacitance in the order of 10,000 pF or more. Alternatively, the H-register of a larger CCD image sensor can be a high capacitance CCD clock input having a capacitance greater than 300 pF.

The operation of circuit600will now be described for the NPN transistor section of the common-base bi-polar drive circuit602. Since the NPN and PNP transistor sections of the common-base bi-polar drive circuit602are fully complementary, the description of the NPN transistor section applies to the PNP transistor section as well. At time T0(seeFIG. 7), the output node VBUF of drive gate600is in a high state, where the voltage is substantially greater than VBE+VSH. VSHrepresents the diode voltage for diode622. The output node VDRV is in a high state, where the voltage is essentially the voltage of node VEH. The emitter of NPN bi-polar transistor608is one diode drop VSHabove ground.

From time T0to T1(FIG. 7), the output node VBUF of drive gate602rapidly falls from the high state to ground. The output of drive gate602is connected to the emitter of NPN bi-polar transistor608by coupling capacitor612, so the transition in VBUF causes the voltage at the emitter (VEL) of NPN bi-polar transistor608to fall rapidly. The transition in VEL is coupled across NPN bi-polar transistor608to the output node VDRV by the parasitic collector-emitter capacitance628plus the series connection of the parasitic collector-base capacitance630and the parasitic base-emitter capacitance632. The parasitic base-emitter capacitance632is shunted to AC ground by parasitic base resistance634.

Although NPN bi-polar transistor608does not turn on until the voltage at the emitter of NPN bi-polar transistor608falls to 1 VBEbelow ground, the signal capacitively coupled to the output node VDRV is in phase with the direction the output will move when NPN bi-polar transistor608does turns on. This is in contrast to the prior art common-emitter bipolar circuit shown inFIG. 2, where the capacitive feed through to the output is out of phase with the direction the output will move. Thus, the common-base bi-polar drive circuit602in circuit600does not have the signal distortion that is produced by the prior art circuits depicted inFIGS. 2 and 3.

Once the voltage at the emitter of NPN bi-polar transistor608falls to 1 VBEbelow ground, the emitter voltage clamps as NPN bi-polar transistor608turns on. At this point, the current in coupling capacitor612rises abruptly and begins to flow from the emitter of NPN bi-polar transistor608. A fraction of the emitter current transfers to the collector, depending on the common-base current gain α. While at low frequencies α is very close to 1, at the high edge rates typically found in these drivers, a will be closer to 0.5. The falloff in α is the major loss in power efficiency of circuit600.

Another parasitic effect occurs when NPN bi-polar transistor608turns on and the voltage at the collector of NPN bi-polar transistor608continues to fall. The other parasitic effect is the well-known Miller effect that results from the parasitic collector-base capacitance630and parasitic base resistance634. These parasitic components increase the fall time of the collector of NPN bi-polar transistor608. The severity of the effect is proportional to their product.

Those skilled in the art will recognize the Miller effect is also present in the prior art common-emitter bipolar circuit ofFIG. 2. But in the prior art circuit, the resistance is the sum of the parasitic base resistance (e.g. resistance634inFIG. 6) and the parasitic drive gate output resistance (e.g., resistance636inFIG. 6). Since the parasitic drive gate output resistance is typically several times larger than the parasitic base resistance, the Miller effect is much smaller in the prior art common-base configuration.

When the voltage at the output node VDRV falls to the emitter voltage of NPN bi-polar transistor608, NPN bi-polar transistor608enters saturation and the collector voltage ceases to fall. Coupling capacitor612continues to charge for a short amount of time until its current falls to zero. The voltage at node VDRV is then maintained by the node capacitance.

The value of coupling capacitor612is large enough to supply sufficient charge to load capacitor638, to account for the charge lost to the current gain α of NPN bi-polar transistor608, and to account for circuit tolerances. Load capacitor638represents the capacitance of CCD clock input626. Coupling capacitor612preferably does not allow current to flow for much longer than the time required to bring node VDRV to the emitter voltage of NPN bi-polar transistor608, as this represents wasted power. The first order design equation for the value of coupling capacitor612(Ccoupling) is:
Ccoupling=(Cvccd)(ΔVccd)/[(α)(ΔVBUF−(VBE+VSH))]  (Equation 1)
Examining Equation 1, it can be seen that the required value of coupling capacitor612increases as load capacitor638and load voltage swing increase, and as α and the gate output swing decrease. The (VBE+VSH) term is due to the coupling capacitor current being zero on a first order basis while the emitter voltage transitions between −1 VBEand one Shottky diode drop VSHin an embodiment in accordance with the invention.

Damping resistor624is provided to eliminate any ringing in circuit600due to parasitic inductances. Damping resistor624also rolls off the waveform at node VCCD, increasing the settling time of node VCCD to T2(seeFIG. 7).

The rising transition of node VDRV begins at time T3(FIG. 7). Since coupling capacitor612is sized so that the emitter current of NPN bi-polar transistor608has substantially reached zero, there is little or no stored charge in the base region of NPN bi-polar transistor608to cause a turn-off delay. From time T3to time T4, the output voltage VBUF of drive gate602rapidly rises from ground to a high state. This transition in VBUF is coupled to the emitter of NPN bi-polar transistor608by coupling capacitor612, so that the voltage at the emitter (VEL) of NPN bi-polar transistor608rises rapidly. This transition in VEL is coupled across NPN bi-polar transistor608to the output node VDRV by the parasitic collector-emitter capacitance628plus the series connection of the parasitic collector-base capacitance630and the parasitic base-emitter capacitance632. Similar to the negative transition, the coupling to output node VDRV is in phase with the direction the output will move when PNP bi-polar transistor610turns on.

Once the voltage VEL at the emitter of NPN bi-polar transistor608rises to 1 VSBabove ground, the emitter voltage clamps as Shottky diode622turns on. At this point, the current in coupling capacitor612rises abruptly, flows into diode612, and then falls to zero as coupling capacitor612is recharged to be ready for the next falling edge. NPN bi-polar transistor608will again turn on at the next falling edge.

Node VDRV is pulled up by PNP bi-polar transistor610operating in complementary fashion to NPN bi-polar transistor608turn-on transient. It is possible that NPN bi-polar transistor608may experience the Miller effect while the voltage at the collector of NPN bi-polar transistor608rises, but the external reverse bias of the emitter of NPN bi-polar transistor608will prevent or minimize the Miller effect. The voltage at node VDRV is maintained by its node capacitance after PNP bi-polar transistor610turns off.

In one embodiment in accordance with the invention, the low state of node VDRV is one (1) VBEbelow the value of the bias supply VDCL. In another embodiment in accordance with the invention, a reference generator is designed and used with DC voltage supply618so that the low state of node VDRV is VDC+VBEto compensate for the base-emitter drop of NPN bi-polar transistor608. A similar reference generator can be designed for use with PNP bi-polar transistor610.

FIG. 8is a schematic diagram of exemplary temperature compensated reference generators suitable for use in circuit600shown inFIG. 6in an embodiment in accordance with the invention. As previously described, the output of the circuit shown inFIG. 6has a high level output of VDCH+1VBE and a low output of VDCL−1VBE in an embodiment in accordance with the invention. The DC voltage supplies618and616have levels that are a DC voltage+/−1VBE, respectively. If these voltage levels are used, the low level output of the circuit shown inFIG. 6is VL+1VBE−1VBE=VL, and the high level output of the circuit is VH−1VBE+1VBE=VH. Since there is no term in levels VL and VH involving VBE, the output of the circuit is independent of both the absolute and temperature change in the value of VBE.

Reference generator800can be used in place of DC voltage supply618inFIG. 6while reference generator802can be used in place of DC voltage supply616. A description of the operation of reference generator800explains the operation of reference generator802because the two bi-polar transistors608,610are complementary. Operational amplifier804is configured as a unity gain follower where the output equals VL (here shown <0V) plus the forward drop of diode806. Diode806can be either a true PN junction diode or a diode-connected transistor where the transistor is of the same type as transistor608inFIG. 6. In a diode-connected transistor, the collector is connected to the base, and the diode forward voltage appears between the base/collector and emitter terminals. If a diode-connected transistor is used, the diode-connected transistor may better match the characteristics of transistor608than a PN junction diode.

Current sink808provides the forward current that generates the forward drop. Capacitor810provides a low impedance path to ground at high frequencies, and operational amplifier804provides the required load current and accurate voltage.

The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. And even though specific embodiments of the invention have been described herein, it should be noted that the application is not limited to these embodiments. In particular, any features described with respect to one embodiment may also be used in other embodiments, where compatible. And the features of the different embodiments may be exchanged, where compatible.

PARTS LIST