Graphene-inserted phase change memory device and method of fabricating the same

Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.

BACKGROUND

The present disclosure relates to a graphene-inserted phase change memory device and a method of fabricating the same.

2. Description of the Related Art

As semiconductor products gradually have small volumes, they demand higher capacity data processing. An operation speed and/or an integration of a nonvolatile memory device used in such a semiconductor product are to be increased.

A technology that uses a phase change material as a nonvolatile memory device has been developed. Examples of the nonvolatile memory device include a phase change memory (PCM) device that uses a phase change material as a memory device. The memory device that uses the phase change material is a memory device that uses changes in a resistance caused by a phase change of a material, e.g., uses reversible changes in the phase of the material depending on an amplitude and a duration time of an applied voltage.

The PCM device may be scaled to an area having a several nanometer size and exhibit fast switching. Therefore, the PCM device takes center stage as a next generation memory. The PCM device has a faster speed and a more stable characteristic than a NOR device having a large size.

However, a speed of the PCM device may be improved so as to be used as a next generation memory that replaces a place of an NAND flash device regarded as a mainstream memory device. For this, consumption of driving power of a PCM is to be reduced. This is related to a driving speed, and thus crystallization and amorphousness of a phase change material may be fast performed according to a current input in terms of a structure of the PCM so as to increase the driving speed. Therefore, the PCM may be driven at a low current to increase the driving speed.

SUMMARY

Provided are a phase change memory device into which a graphene layer is inserted so as to have high heat transfer efficiency and a low driving current, and a method of fabricating the same.

Provided are a phase change memory device that controls a width of an inserted graphene layer to control a heat transfer amount, and a method of fabricating the same.

According to an aspect of an example embodiment, a phase change memory device includes: a lower electrode; an insulating layer configured to be formed so as to enclose the lower electrode; a graphene layer configured to be formed on the lower electrode; a phase change material layer configured to be formed on the graphene layer and the insulating layer; and an upper electrode configured to be formed on the phase change material layer.

The graphene layer may be formed only on the lower electrode and may not be formed on the insulating layer.

A width of the graphene layer may be equal to a width of the lower electrode.

The phase change material layer may include a germanium antimony tellurium (GST) material.

According to an aspect of another example embodiment, a phase change memory device includes: a lower electrode; an insulating layer configured to be formed so as to enclose the lower electrode; a graphene layer configured to be formed on the lower electrode and the insulating layer; a phase change material layer configured to be formed on the graphene layer; and an upper electrode configured to be formed on the phase change material layer.

The graphene layer may be formed to cover the lower electrode and parts of the insulating layer.

The graphene layer may be formed to cover the lower electrode and all of the insulating layer.

The phase change material layer may include a GST material.

According to an aspect of another example embodiment, a method of fabricating a phase change memory device, includes: sequentially forming an electrode layer and an insulating layer on a substrate; removing a part of the insulating layer to expose the electrode layer to an outside; forming a lower electrode in the removed part of the insulating layer and then planarizing an uppermost layer; forming a graphene layer on the lower electrode and the insulating layer; removing the graphene layer formed on the insulating layer; and sequentially forming a phase change material layer and an upper electrode on the graphene layer and the insulating layer.

The graphene layer may be formed by using a transfer method or a direct growth method.

The electrode layer and the lower electrode may be formed of a same material.

All of the graphene layer formed on the insulating layer may be removed.

A part of the graphene layer formed on the insulating layer may be removed.

According to an aspect of another example embodiment, a method of fabricating a phase change memory device, includes: sequentially forming an electrode layer and an insulating layer on a substrate; removing a part of the insulating layer to expose the electrode layer to an outside; forming a lower electrode in the removed part of the insulating layer and then planarizing an uppermost layer; forming a graphene layer on the lower electrode and the insulating layer; and sequentially forming a phase change material layer and an upper electrode on the graphene layer.

The graphene layer may be formed by using a transfer method or a direct growth method.

The electrode layer and the lower electrode may be formed of a same material.

The graphene layer may be formed to cover all of the lower electrode and the insulating layer.

DETAILED DESCRIPTION

It will be understood that when any part is referred to as being “connected to” or “coupled to” another part, it may be directly connected or coupled to the other part or intervening elements may be present. In contrast, when any part is referred to as including any element, it may further include other elements without excluding other elements.

The inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concepts are shown. The advantages and features of the inventive concepts and methods of achieving them will be apparent from the following example embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concepts are not limited to the following example embodiments, and may be implemented in various forms. Accordingly, the example embodiments are provided only to disclose the inventive concepts and let those skilled in the art know the category of the inventive concepts. In the drawings, embodiments of the inventive concepts are not limited to the specific examples provided herein and are exaggerated for clarity.

Additionally, the embodiment in the detailed description will be described with sectional views as ideal example views of the inventive concepts. Accordingly, shapes of the example views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concepts are not limited to the specific shape illustrated in the example views, but may include other shapes that may be created according to manufacturing processes. Areas exemplified in the drawings have general properties, and are used to illustrate specific shapes of elements. Thus, this should not be construed as limited to the scope of the inventive concepts.

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

FIG. 1is a schematic cross-sectional view of a structure of a phase change memory device100according to an example embodiment.

Referring toFIG. 1, the phase change memory device100includes an insulating layer110, a lower electrode120, a graphene layer130, a phase change material layer140, and/or an upper electrode150.

The insulating layer110may be formed to enclose the lower electrode120(this is not visible in the provided view, but would be visible from a view above). The insulating layer110may, for example, include at least one selected from a silicon oxide, a silicon nitride, and a silicon oxynitride.

The lower electrode120may be enclosed by the insulating layer110. Since the drawing ofFIG. 1is a cross-sectional view, the insulating layer110is illustrated beside both sides of the lower electrode120. However, the insulating layer110may be positioned in front or back of the lower electrode120, e.g., in a vertical direction in the drawing. The insulating layer110encloses only sides of the lower electrode120and need not be formed on the lower electrode120.

The lower electrode120may include a metal such as aluminum (Al), copper (Cu), tungsten (W) titanium (Ti), or tantalum (Ta), an alloy such as titanium tungsten (TiW) or titanium aluminum (TiAl), or carbon (C). The lower electrode120may also include titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). Also, the lower electrode120may be a single layer including one single material of the above-mentioned materials, a single layer including a plurality of materials of the above-mentioned materials, a multilayer each including a single material of the above-mentioned materials, and/or a multilayer each including a plurality of materials of the above-mentioned materials.

The graphene layer130may be formed on the lower electrode120. The graphene layer130may be positioned between the lower electrode120and the phase change material layer140or may directly contact the lower electrode120and the phase change material layer140to transfer heat generated from the lower electrode120to the phase change material layer140. A width of the graphene layer130and a width of the lower electrode120may be equal to each other, and the graphene130need not be formed on the insulating layer110. The graphene layer130may be formed to have the same width as the lower electrode120so as to enable heat, which flows into the lower electrode120when driving the phase change memory device100, not to escape in a horizontal direction but enable the heat to transfer to the phase change material layer140.

Since the graphene layer130has a high electrical conductivity, the graphene layer130may transfer a current input into the lower electrode120to the phase change material layer140. Also, since the graphene layer130has a high heat conductivity, the graphene layer130may transfer the heat generated from the lower electrode120to the phase change layer material140.

The phase change material layer140may be formed on the graphene layer130and the insulating layer110. The phase change material layer140may directly contact the insulating layer110and the graphene layer130. The phase change material layer140is electrically connected to the lower electrode120. The graphene layer130is inserted between the phase change material layer140and the lower electrode120. However, since the graphene layer130has a very high electrical conductivity, the phase change material layer140and the lower electrode120may be electrically connected to each other.

The phase change material layer140may be formed by using sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or the like. The phase change material layer140may include a phase change material, such as chalcogenide, that may store data according to different crystalline states. The phase change material may be a binary, tertiary, or quaternary material and include, for example, Ge—Te, Ge—Sb—Te, Ge—Te—Se, Ge—Te—As, Ge—Te—Sn, Ge—Te—Ti, Ge—Bi—Te, Ge—Sn—Sb—Te, Ge—Sb—Se—Te, Ge—Sb—Te—S, Ge—Te—Sn—O, Ge—Te—Sn—Au, Ge—Te—Sn—Pd, Sb—Te, Se—Te—Sn, Sb—Se—Bi, In—Se, In—Sb—Te, Sb—Se, Ag—In—Sb—Te, or a combination thereof. Also, the phase change material layer140may include only a phase change material or a phase change material to which dopant is added. The dopant may include C, N, Si, O, bismuth (Bi), tin (Sn), or a combination thereof. The dopant may be doped on the phase change material layer140to reduce a driving current of the phase change memory device100. Also, the phase change material layer140may further include a metal material.

The upper electrode150may be formed on the phase change material layer140. The upper electrode150may directly contact the phase change material layer140. The upper electrode may also be electrically connected to the phase change material layer140. The upper electrode150may include a metal such Al, Cu, W, Ti, or Ta, an alloy such as TiW or TiAl, or C. The upper electrode150may also include, TiN, TiAlN, TaN, WN, MoN, NbN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, TiCN, or TaCN. Also, the upper electrode150may include a single layer including one single material of the above-mentioned materials, a single layer including a plurality of materials of the above-mentioned materials, a multilayer each including a single material of the above-mentioned materials, and/or a multilayer each including a plurality of materials of the above-mentioned materials. The lower electrode120and the upper electrode150may be formed of the same material or different materials

The phase change memory device100is basically driven by a current and has a structure in which heat generated by current driving is transferred to the lower electrode120of the phase change memory device100. The lower electrode120may perform a function of a heater that changes a material state of the phase change material layer140, e.g., changes a material state into a crystalline state or an amorphous state.

The phase change memory device100may store preset data according to a material state of the phase change material layer140formed between the lower electrode120and the upper electrode150. For example, if the phase change material layer140is heated at temperature between a crystallization temperature and a melting temperature and then cooled, the phase change material layer140is changed into a crystalline state. The crystalline state is referred to as a set state or may be a state in which data “0” is stored. If the phase change material layer140is heated at a temperature higher than or equal to the melting temperature and then cooled, the phase change material layer140is changed into an amorphous state. The amorphous state is referred to as a reset state or may be a state in which data “1” is stored. Therefore, a current may be supplied to the phase change memory device100to store data, and a resistance value of the phase change material layer140may be measured to read data. A heating temperature of a phase change material is proportional to an amount of a current, and an increase in the amount of the current makes an achievement of a high integration difficult. Also, the change into the amorphous state (the reset state) demands a larger amount of current than the change into the crystalline state (the set state), and thus power consumption of a memory device increases. Therefore, a phase change material may be heated at a small amount of current to be changed into a crystalline state or an amorphous state so as to reduce power consumption. In particular, a current (e.g., a reset current) for a change into the amorphous state may be reduced to achieve the high integration.

Heat flowing into the lower electrode120due to current driving may be transferred to the phase change material layer140through the graphene layer130. The graphene layer130has a higher heat conductivity in a thickness direction than in a width direction. Therefore, the heat flowing into the lower electrode120may not escape in a width direction of the graphene layer130, e.g., in a horizontal direction, but may be efficiently transferred to the phase change material layer140. Therefore, a driving current for driving the phase change memory device100may be lowered, and thus a driving speed of the phase change memory device100may also increase. Also, the phase change material layer140may be heated at a small amount of current to be changed into the amorphous state, and thus the high integration may be achieved.

FIG. 2is a cross-sectional view illustrating changes in a phase of the phase change material layer140caused by heat generated from the lower electrode120in the phase change memory device100, according to an example embodiment.

Referring toFIG. 2, a driving current may flow into the phase change memory device100to heat the lower electrode120. The lower electrode120that is heated may transfer the heat to the phase change material layer140through the graphene layer130. The graphene layer130has the higher heat conductivity in the thickness direction than in the width direction. Therefore, the heat flowing into the lower electrode120may not get out in the horizontal direction but may be transferred in a vertical direction so as to change a phase of the phase change material layer140. If the phase change material layer140is heated at a temperature higher than or equal to a preset temperature, the phase change material layer140may change the phase thereof to be changed into a phase change material layer145having an amorphous state. InFIG. 2, the phase change material layer140shows the crystalline state, and the phase change material layer145shows the amorphous state. The phase change material layer140having the crystalline state is in a set state, e.g., may be in a state in which data “0” is stored. The phase change material layer145having the amorphous state is in a reset state, i.e., may be in a state in which data “1” is stored.

The heat flowing into the lower electrode120may be quickly transferred in the width direction of the graphene layer130, e.g., in the vertical direction, through the graphene layer130. As a result, a loss of heat transferred to the phase change material layer140may be reduced or prevented. As the loss of the heat decreases, the phase change material layer140in the crystalline state may be changed into the phase change material layer145in the amorphous state only at a small amount of driving current. Therefore, a manual speed of the phase change memory device100may quicken and may be realized as a device having a high integration.

FIGS. 3A through 3Fare cross-sectional views illustrating a method of fabricating a phase change memory device according to an example embodiment.

Referring toFIG. 3A, an electrode layer125and an insulating layer110are sequentially formed on a substrate105.

The substrate105may include a semiconductor material, e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The substrate105may be provided as a bulk wafer or an epitaxial layer. Alternatively, the substrate105may be a substrate such as a Silicon On Insulator (SOI) substrate, a gallium (Ga)-arsenic (As) substrate, a Si—Ge substrate.

The electrode layer125may be formed on the substrate105and may include a metal such as Al, Cu, W, Ti, or Ta, an alloy such as TiW or TiAl, or C.

The insulating layer110may be formed on the electrode layer125and may include at least one selected from silicon oxide, silicon nitride, and a silicon oxynitride.

Referring toFIG. 3B, a part of the insulating layer110may be patterned to expose the electrode layer125. The insulating layer110may be patterned by using a normal photography method, an etch method, a chemical mechanical polishing (CMP) method, a dry etch method, or the like. The above-described process may form a hole in the insulating layer110and expose the electrode layer125to the outside.

The lower electrode120may be formed of the same material as that of which the electrode layer125is formed. However, the electrode layer120need not be formed of the same material as the electrode layer125and thus may be formed of a different material from the electrode layer125so as to be electrically connected to the electrode layer125.

The lower electrode120may be formed in the patterned part of the insulating layer110, and then uppermost layers of the lower electrode120and the insulating layer110may be planarized.

Referring toFIG. 3D, the graphene layer130may be formed on the lower electrode120and the insulating layer110that are planarized. A graphene may be fabricated by using CVD and then transferred onto the lower electrode120and the insulating layer110so as to form the graphene layer130. Also, the graphene layer130may be formed on the lower electrode120and the insulating layer110by using a direct growth method.

Referring toFIG. 3E, an other part of the graphene layer130except a part of the graphene layer130formed on the lower electrode120, e.g., a part of the graphene layer130formed on the insulating layer110, may be removed by a method such as an etch or the like. Therefore, a width of the graphene layer130and a width of the lower electrode120may become equal.

The part of the graphene layer130except the other part of the graphene layer130formed on the lower electrode120, e.g., only a part of the graphene layer130formed on the insulating layer110, may be etched and removed. In example embodiments, the width of the graphene layer130may be wider than the width of the lower electrode120. The graphene layer130that is formed wider than the lower electrode120may diffuse heat, which flows into the lower electrode120, through the graphene layer130in a width direction (a horizontal direction) of the graphene layer130. Therefore, a width of a part of the graphene layer130that is formed on the insulating layer110and removed by etching may be controlled to control an amount of heat transferred to the phase change material layer140.

Referring toFIG. 3F, the phase change material layer140and the upper electrode150may be sequentially formed on the graphene layer130and the insulating layer110. The phase change material layer140and the upper electrode150may be formed by using sputtering, CVD, PECVD, ALD, or the like.

FIG. 4is a schematic cross-sectional view of a structure of a phase change memory device200according to another example embodiment.

Referring toFIG. 4, the phase change memory device200includes an insulating layer210, a lower electrode220, a graphene layer230, a phase change material layer240, and an upper electrode250.

The insulating layer210may be formed to enclose the lower electrode220. The insulating layer210may, for example, include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

The lower electrode220may be enclosed by the insulating layer210. Since the drawing ofFIG. 4is a cross-sectional view, the insulating layer210is illustrated beside only both sides of the lower electrode220. However, inFIG. 4, the insulating layer210may be positioned in front or back of the lower electrode220, e.g., in a vertical direction of the drawing. The insulating layer210may enclose only a side part of the lower electrode220, and the insulating layer210may not be formed on the lower electrode220.

The lower electrode220may include a metal such as Al, Cu, W, Ti, or Ta, an alloy such as TiW or TiAl, or C. The lower electrode220may also include TiN, TiAlN, TaN, WN, MoN, NbN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, TiCN, or TaCN. Also, the lower electrode220may be a single layer including one single material of the above-mentioned materials, a single layer including a plurality of materials of the above-mentioned materials, a multilayer each including a single material of the above-mentioned materials, and/or a multilayer each including a plurality of materials of the above-mentioned materials.

The graphene layer230may be formed on the lower electrode220and the insulating layer210. The graphene layer230may be formed to cover all of the lower electrode220and the insulating layer210. The phase change memory device200may be basically driven by a current, and heat generated by current driving may be transferred to the lower electrode220. In the phase change memory device200ofFIG. 4, a width of the graphene layer230is wider than a width of the lower electrode220. Therefore, heat flowing into the lower electrode220may be diffused in a width direction (or a horizontal direction) of the graphene layer230through the graphene layer230. Therefore, an amount of the heat transferred to the phase change material layer140may be controlled.

The phase change material layer240may be formed on the graphene layer230. The phase change material layer240may directly contact the graphene layer230. The phase change material layer240is electrically connected to the lower electrode220. The graphene layer230is inserted between the phase change material layer240and the lower electrode220. However, since the graphene layer230has a very high electrical conductivity, the phase change material layer240and the lower electrode220may be electrically connected to each other.

The phase change material layer240may be formed by using sputtering, CVD, PECVD, ALD, or the like. The phase change material layer240may include a phase change material, such as chalcogenide, that may store data according to different crystalline states. The phase change material may be Ge—Te, Ge—Sb—Te, Ge—Te—Se, Ge—Te—As, Ge—Te—Sn, Ge—Te—Ti, Ge—Bi—Te, Ge—Sn—Sb—Te, Ge—Sb—Se—Te, Ge—Sb—Te—S, Ge—Te—Sn—O, Ge—Te—Sn—Au, Ge—Te—Sn—Pd, Sb—Te, Se—Te—Sn, Sb—Se—Bi, In—Se, In—Sb—Te, Sb—Se, Ag—In—Sb—Te, or a combination thereof. The phase change material layer240may also include only the phase change material or a phase change material to which dopant is added. The dopant may be C, N, Si, O, Bi, Sn, or a combination thereof. The phase change material layer240may further include a metal material.

The upper electrode250may be formed on the phase change material layer240. The upper electrode250may directly contact the phase change material layer240. The upper electrode250may be electrically connected to the phase change material layer240. The upper electrode250may include a metal such as Al, Cu, W, Ti, or Ta, an alloy such as TiW or TiAl, or C. The upper electrode250may also include TiN, TiAlN, TaN, WN, MoN, NbN, TiSiN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, TiCN, or TaCN. Also, the upper electrode250may be a single layer including one single material of the above-mentioned materials, a single layer include a plurality of materials of the above-mentioned materials, a multilayer each including a single material of the above-mentioned materials, and/or a multilayer each including a plurality of materials of the above-mentioned materials. The lower electrode220and the upper electrode250may be formed of the same material or different materials.

FIGS. 5A through 5Fare cross-sectional views illustrating a method of fabricating a phase change memory device according to another example embodiment.

Referring toFIG. 5A, an electrode layer225and the insulating layer210are sequentially formed on a substrate205.

The substrate205may include a semiconductor material, e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include Si, Ge, or Si—Ge. The substrate205may be provided as a bulk wafer or an epitaxial layer. Alternatively, the substrate205may be a substrate such as an SOI substrate, a Ga—As substrate, or a Si—Ge substrate.

The electrode layer225may be formed on the substrate205and may include a metal such as Al, Cu, W, Ti, or Ta, an alloy such as TiW or TiAl, or C.

The insulating layer210may be formed on the electrode layer225and may include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

Referring toFIG. 5B, a part of the insulating layer210may be patterned to expose the electrode layer225to an outside. The insulating layer210may be patterned by using a normal photolithography method, an etch method, CMP, a dry etch method, or the like. The above-described process may form a hole in the insulating layer210and expose the electrode layer225to the outside.

The lower electrode220may be formed of the same material as the electrode layer225. However, the lower electrode220may not be formed of the same material as the electrode layer225and thus may be formed of a different material from the electrode layer225to be electrically connected to the electrode layer225.

The lower electrode220may be formed in the patterned part of the insulating layer210, and then uppermost layers of the lower electrode220and the insulating layer210may be planarized.

Referring toFIG. 5D, the graphene layer230may be formed on the lower electrode220and the insulating layer210. A graphene may be fabricated by CVD and then transferred onto the lower electrode220and the insulating layer210to form the graphene layer230. Also, the graphene layer230may be formed on the lower electrode220and the insulating layer210by using a direct growth method.

Referring toFIGS. 5E and 5F, the phase change material layer240and the upper electrode250may be sequentially formed on the graphene layer230. The phase change material layer240and the upper electrode250may be formed by using sputtering, CVD, PECVD, ALD, or the like.

According to example embodiments as described, a graphene layer may be formed between a phase change material layer and a lower electrode to efficiently transfer heat energy formed from the lower electrode to the phase change material layer so as to lower a driving current of a phase change memory device. Therefore, a driving speed of the phase change memory device may also increase.

Also, a width of the graphene layer formed between the phase change material layer and the lower electrode may be controlled to control a transferred amount of heat flowing from the lower electrode into the phase change material layer.