Shift and detecting circuit and floating-point calculating circuit using the same

In a shift and shift-out detecting circuit, a plurality of partial shift circuits respectively have bit shift quantities which are different from each other, and are connected in series. Each of the plurality of partial shift circuits receives a shift result as a previous shift result from the partial shift circuit of a previous stage and a corresponding shift instruction, shifts the previous shift result by the corresponding bit shift quantity in response to the shift instruction to produce a current shift result, and outputs the current shift result to the partial shift circuit of a subsequent stage. A plurality of shift-out detecting circuits are respectively provided for the plurality of partial shift circuits. Each of the plurality of shift-out detecting circuits detects a shift-out of “1” bit from the current shift result and the corresponding shift instruction and generates a partial sticky signal when the shift-out is detected. A collecting circuit collects the partial sticky signals from the plurality of shift-out detecting circuits and generates a sticky signal to indicate generation of the shift-out.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the embodiments of the present invention will be described below in detail with reference to the attached drawings. The description will be given with reference to the embodiments. In the circuit structure of the present invention, one of partial rounding detection signals which is outputted from at least one of partial rounding detecting circuits other than the partial rounding detecting circuit of the last stage does not pass through another partial rounding detecting circuit. Therefore, a rounding detection signal which is outputted from the rounding detection signal output circuit is transferred to a rounding process circuit in which a rounding process is carried out at high speed. Thus, it is possible to contribute to improvement of the operation speed of a floating-point calculating circuit. Also, the size of an active element of the partial rounding detecting circuit corresponding to a partial shift circuit with a relatively large partial shift quantity is set to be larger than the size of an active element of the partial rounding detecting circuit corresponding to the partial shift circuit with a relatively small partial shift quantity. Therefore, the reduction in size of the whole rounding detecting circuit can be achieved, while attempting to shorten an average calculation time. &lsqb;The First Embodiment&rsqb; FIGS. 5 and 6 are block diagrams showing circuit structures of a shift circuit according to the first embodiment of the present invention and a shift-out detecting circuit. FIG. 7 is a circuit diagram showing the circuit structure of a multiplexer circuit of the shift circuit. FIG. 8 is a circuit diagram showing the circuit structure of a 1-bit detecting circuit of the shift-out detecting circuit. FIG. 9 is a circuit diagram showing the circuit structure of a 2-bit detecting circuit of the shift-out detecting circuit. FIG. 10 is a circuit diagram showing the circuit structure of a 4-bit detecting circuit of the shift-out detecting circuit. FIG. 11 is a circuit diagram showing the circuit structure of an 8-bit detecting circuit of the shift-out detecting circuit. FIG. 12 is a circuit diagram showing the circuit structure of a 16-bit detecting circuit of the shift-out detecting circuit. FIG. 13 is a circuit diagram showing the circuit structure of a 32-bit detecting circuit of the shift-out detecting circuit. FIGS. 14A to 14 C are diagrams showing the operation of the shift circuit and shift-out detecting circuit. Also, FIG. 15 is a block diagram showing the circuit structure of a floating-point adding and subtracting circuit in which the shift circuit and the shift-out detecting circuit are incorporated. As shown in FIG. 5 , the shift circuit 1 and the shift-out detecting circuit (rounding detecting circuit) 2 in this example are used for a digit adjustment shifting process and a normalization shifting process in the floating-point adding and subtracting circuit which outputs the addition result (summation) of two floating-point numbers. It should be noted that the shift circuit 1 and the shift-out detecting circuit 2 connected in parallel form a composite circuit. This shift circuit 1 is composed of a 1-bit shift circuit (partial shift circuit) 5 which is possible to shift data by 1 bit on either side in accordance with a shift quantity signal given from a comparing and subtracting circuit 3 , a 2-bit shift circuit 6 which is possible to shift data by 2 bits, a 4-bit shift circuit 7 which is possible to shift data by 4 bits, a 8-bit shift circuit 8 which it is possible to shift data by 8 bits, a 16-bit shift circuit 9 which is possible to shift data by 16 bits, and a 32-bit shift circuit 11 which is possible to shift data by 32 bits. As shown in FIG. 5 and 6 , the shift circuit 1 shifts 64-bit mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) by an optional shift bit quantity in a range from 1 bit to 64 bits, and outputs the shift result (b 63 b 62 . . . b 3 b 2 b 1 b 0 ) to the rounding process circuit 4 by the combination of the above bit shift circuits. As shown in FIGS. 5 and 6 , the shift-out detecting circuit 2 is composed of a 1-bit detecting circuit (partial rounding detecting circuit) 13 , a 2-bit detecting circuit 6 , a 4-bit detecting circuit 7 , a 8-bit detecting circuit 8 , a 16-bit detecting circuit 9 , and a 32-bit detecting circuit 11 for detecting the shifting-out operations of “1” in the 1-bit shift circuit 5 , the 2-bit shift circuit 6 , the 4-bit shift circuit 7 , the 8-bit shift circuit 8 , the 16-bit shift circuit 9 , and the 32-bit shift circuit 11 , respectively. Further, the shift-out detecting circuit 2 is composed of a relaying circuit 19 for relaying the output of 2-bit detecting circuit 14 and the 4-bit detecting circuit 15 , and a collecting circuit (rounding detection signal output circuit) 21 which collects the outputs of the respective bit detecting circuits, and outputs a sticky signal (rounding detection signal) STOUT to notify the shift-out of “1” as a result of the shifting process of the shift circuit 1 . The shift-out detecting circuit 2 checks the existence or non-existence of the shift-out of “1” based on the shift quantity signal given from the comparing and subtracting circuit 3 and a part of data during the shifting process outputted from the digit adjustment shift circuit 1 . In case of a digit adjustment shift, for example, the shift circuit 1 shifts (right shift) the inputted mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) of 64 bits as a shift object into the lower bit, based on the shift quantity necessary for the digit adjustment of the mantissa of the floating-point number with the smaller exponent which is outputted from the comparing and subtracting circuit 3 which determines the larger or smaller relation of the exponents of two floating-point numbers, and outputs the shifted result (b 63 b 62 . . . b 3 b 2 b 1 b 0 ). On the other hand, the shift-out detecting circuit 2 checks whether or not “1” is contained in any one of the data shift out as a result of the shifting process in parallel to the shifting process of the shift circuit 1 , and sets and outputs a sticky signal STOUT of “1” to promote a rounding process determining process for selecting an optimal rounding method in the rounding process circuit 4 of the post stage, when “1” is contained. The shift circuit 1 is a barrel shift circuit which can collectively shift a plurality of bits. As shown in FIGS. 5 and 6 , in the shift circuit 1 , the 1-bit shift circuit (partial shift circuit) 5 shifts the inputted mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) into a right direction by one bit, when receiving the right 1-bit shift signal RS 1 of “1” from the comparing and subtracting circuit 3 , for example. Also, the 1-bit shift circuit 5 shifts the inputted mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) into a left direction by one bit, when receiving the left 1-bit shift signal LS 1 of “1”. The 2-bit shift circuit 6 shifts the output data (p 63 P 62 . . . p 3 p 2 p 1 p 0 ) of the 1-bit shift circuit 5 into a right direction by two bits, when receiving the right 2-bit shift signal RS 2 of “1”. Also, the 2-bit shift circuit 6 shifts the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) of the 1-bit shift circuit 5 into a left direction by two bits, when receiving the left 2-bit shift signal LS 2 of “1”. The 4-bit shift circuit 7 shifts the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) of the 2-bit shift circuit 6 into a right direction by four bits, when receiving the right 4-bit shift signal RS 3 of “1”. Also, 4-bit shift circuit 7 shifts the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) of the 2-bit shift circuit 6 into a left direction by four bits, when receiving the left 4-bit shift signal LS 3 of “1”. The 8-bit shift circuit 8 shifts the output data (r 63 r 62 . . . r 3 r 2 r 1 r 0 ) of the 4-bit shift circuit 7 into a right direction by 8 bits, when receiving a right 8-bit shift signal RS 4 of “1”. Also, 8-bit shift circuit 8 shifts the output data (r 63 r 62 . . . r 3 r 2 r 1 r 0 ) of the 4-bit shift circuit 7 into a left direction by 8 bits, when receiving a left 8-bit shift signal LS 4 of The 16-bit shift circuit 9 shifts the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) of the 8-bit shift circuit 8 into a right direction by 16 bits, when receiving the right 16-bit shift signal RS 5 of “1”. Also, the 16-bit shift circuit 9 shifts the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) of the 8-bit shift circuit 8 into a left direction by 16 bits when receiving the left 16-bit shift signal LS 5 of “1”. The 32-bit shift circuit 11 shifts the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) of the 16-bit shift circuit 9 into a right direction by 32 bits, when receiving the right 32-bit shift signal RS 6 of “1”. Also, the 32-bit shift circuit 11 shifts the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) of the 16-bit shift circuit 9 into a left direction by 32 bits, when receiving the left 32-bit shift signal LS 6 of “1”. The shift circuit 1 is possible to shift data into the upper or lower bit direction by an optimal shift quantity from 1 bit to 64 bits by the combination of the above shift signals. As shown in FIG. 6 , the 1-bit shift circuit 5 inputs a mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ), Of the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) as 1-bit higher data obtained by shifting the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) into a right direction by one bit, and the left shifted data (aL 63 aL 62 . . . aL 3 aL 2 aL 1 aL 0 ) as 1-bit lower data obtained by shifting the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) into a left direction by one bit. When there is not the 1-bit higher data or the 1-bit lower data, data of “0” is inputted. As shown in FIG. 6 , the 1-bit shift circuit 5 inputs the above data and has 64 multiplexer circuits 5 0 , 5 1 , 5 2 , . . . , 5 62 , 5 63 corresponding to the number of bits of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ). As shown in FIG. 6 , the multiplexer circuits 5 0 ( 5 1 , 5 2 , . . . , 5 62 , 5 63 ) selects and outputs one of data of a corresponding bit of the inputted mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ), data of the corresponding bit of the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ), and data of the corresponding bit of the left shifted data (aL 63 aL 62 . . . . aL 3 aL 2 aL 1 aL 0 ) in accordance with the states of the right 1-bit shift signal RS 1 and the left 1-bit shift signal LS 1 which are inputted as a control signal. In the same way, the 2-bit shift circuit 6 , the 4-bit shift circuit 7 , the 8-bit shift circuit 8 , the 16-bit shift circuit 9 , and the 32-bit shift circuit 11 have 64 multiplexer circuits 6 0 , 6 1 , 6 2 , . . . 6 63 , multiplexer circuits 7 0 , 7 1 , 7 2 , . . . 7 63 , multiplexer circuits 8 0 , 8 1 , 8 2 . . . , 8 63 , multiplexer circuits 9 0 , 9 1 , 9 2 , . . . , 9 63 , and multiplexer circuits 11 0 , 11 1 , 11 2 , . . . , 11 63 , respectively. Here, as shown in FIG. 6 , the 2-bit shift circuit 6 inputs the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) of the 1-bit shift circuit 5 , the right shifted data (pR 63 pR 62 . . . pR 3 pR 2 pR 1 pR 0 ) as 2-bit higher data by shifting the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) into a right direction by two bits, and the left shifted data (pL 63 pL 62 . . . pL 3 pL 2 pL 1 pL 0 ) as 2-bit lower data obtained by shifting the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) into a left direction by two bit. When there is not the 2-bit higher or the 2-bit lower data, “0” is inputted. The above data is inputted to each of the multiplexer circuits 6 0 ( 6 1 , 6 2 , 6 3 , . . . , 6 62 , 6 63 ) Similarly, the 4-bit shift circuit 7 inputs the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) of the 2-bit shift circuit 6 , the right shifted data (qR 63 qR 62 . . . qR 3 qR 2 qR 1 qR 0 ) obtained by shifting the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) into a right direction by four bits, and the left shifted data (qL 63 qL 62 . . . qL 3 qL 2 qL 1 qL 0 ) obtained by shifting the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) into a left direction by four bit. Also, the 8-bit shift circuit 8 inputs the output data (r 63 r 62 . . . r 3 r 2 r 1 r 0 ) of the 4-bit shift circuit 7 , the right shifted data (rR 63 rR 62 . . . rR 3 rR 2 rR 1 rR 0 ) obtained by shifting the output data (r 63 r 62 . . . r 3 r 2 r 1 r 0 ) into a right direction by 8 bits, and the left shifted data (rL 63 rL 62 . . . rL 3 rL 2 rL 1 rL 0 ) obtained by shifting the output data (r 63 r 62 . . . r 3 r 2 r 1 r) into a left direction by 8 bits. Also, the 16-bit shift circuit 9 inputs the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) from the 8-bit shift circuit 8 , the right shifted data (sR 63 sR 62 . . . sR 3 sR 2 sR 1 sR 0 ) obtained by shifting the output data (s 63 s 62 . . . S 3 S 2 s 1 s 0 ) into a right direction by 16 bits, and the left shifted data (sL 63 sL 62 . . . sL 3 sL 2 sL 1 sL 0 ) obtained by shifting the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) into a left direction by 16 bits. Also, the 32-bit shift circuit 11 inputs the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) of the 16-bit shift circuit 9 , the right shifted data (tR 63 tR 62 . . . tR 3 tR 2 tR 1 tR 0 ) obtained by shifting the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) into a right direction by 32 bits, and the left shifted data (tL 63 tL 62 . . . tL 3 tL 2 tL 1 tL 0 ) obtained by shifting the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) into a left direction by 32 bits. As shown in FIG. 7 , the multiplexer circuit 5 0 is composed of clock inverter circuits 5 0 a , 5 0 b , and 5 0 c , inverter circuits 5 0 d , 5 0 e , 5 0 g , 5 0 h and a NOR circuit 5 0 f. According to the states (“1” or “0”) of the control signals inputted to two control terminals &phgr; 1 and &phgr; 2 , the clock inverter circuit 5 0 a , 5 0 b , and 5 0 c become a conductive state to invert and outputs an input signal, or becomes a high impedance state (blocking-off state) to prevent the passage of the input signal. The inverter circuit 5 0 d receives and inverts the right 1-bit shift signal RS 1 and gives the inverted signal to the control terminal &phgr; 2 of the clock inverter circuit 5 0 a . The Inverter circuit 5 0 e receives and inverts the left 1-bit shift signal LS 1 and gives the inverted signal to the control terminal &phgr; 2 of the clock inverter circuit 5 0 b. The NOR circuit 5 0 f receives the right 1-bit shift signal RS 1 and the left 1-bit shift signal LS 1 , and outputs a non-selection signal of “1” only when time both of right 1-bit shift signal RS 1 and left 1-bit shift signal LS 1 have the state of “0”. The inverter circuit 5 0 g receives and inverts the output signal of the NOR circuit 5 0 f and gives the inverted signal to the control terminal &phgr; 2 of the clock inverter circuit 5 0 c . The inverter circuit 5 0 h inverts and outputs the output signals from the clock inverter circuit 5 0 a , the clock inverter circuit 5 0 b or the clock inverter circuit 5 0 c. In the clock inverter circuit 5 0 a , 5 0 b , and 5 0 c , a control signal obtained by inverting the control signal inputted to the control terminal &phgr; 1 is supplied to the control terminal &phgr; 2 . For example, in the clock inverter circuit 5 0 a , the right 1-bit shift signal RS 1 of the “1” is supplied to the control terminal &phgr; 1 as the control signal. When the signal of “0” is supplied to the control terminal &phgr; 2 , the least significant bit data aR 0 of the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) is inverted and is outputted from the clock inverter circuit 5 0 a . At this time, the clock inverter circuits 5 0 b and 5 0 c are in the blocking-off state and the least significant bit data aR 0 is outputted from the multiplexer circuit 50 . In the same way, when the left 1-bit shift signal LS 1 of “1” is supplied to the control terminal of the clock inverter circuit 5 0 b , the least significant bit data aL 0 of the left shifted data (aL 63 aL 62 . . . aL 3 aL 2 aL 1 aL 0 ) is outputted from the multiplexer circuit 5 0 . Also, when the non-selection signal of “1” is inputted to the control terminal &phgr; 1 of the clock inverter circuit 5 0 c, the least significant bit a 0 of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a) is outputted from the multiplexer circuit 50 as it is. Also, the multiplexer circuits 5 1 , 52 1 , . . . , 5 63 have the same circuit structure as the multiplexer circuit 50 . In FIG. 7 , they are shown by adding subscripts 0 , 1 , 2 , . . . , 63 . Moreover the multiplexer circuits 6 , 7 , . . . , 11 have the same circuit structure as the multiplexer circuit 5 , except for the shift signal as the input data and the control signal. In FIG. 7 , the numbers 50 is changed to 6 0 , 6 1 , . . . , and 1163 , and also 6 0 a is shown in place of 5 0 a , of example. The multiplexer circuit 51 outputs the second bit data aR 1 of right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) when the right 1-bit shift signal RS 1 is “1”, outputs the second bit data aL 1 of the left shifted data (aL 63 aL 62 . . . aL 3 aL 2 aL 1 aL 0 ), when the left 1-bit shift signal LS 1 is “1”, and outputs the second bit data a 1 of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ), when both of right 1-bit shift signal RS 1 and left 1-bit shift signal LS 1 are “0”. Similarly, the multiplexer circuits 5 2 , . . . , 5 62 , and 5 63 operate in the same way. In this way, the 1-bit shift circuit 5 selects one of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ), the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) and the left shifted data (aL 63 aL 62 . . . aL 3 aL 2 aL 1 aL 0 ) in accordance with the right 1-bit shift signal RS 1 and the left 1-bit shift signal LS 1 . In the same way, the 2-bit shift circuit 6 selects one of the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) the right shifted data (pR 63 pR 62 . . . pR 3 pR 2 pR 1 pR 0 ) and the left shifted data (pL 63 pL 62 . . . pL 3 pL 2 pL 1 pL 0 ) in accordance with the right 2-bit shift signal RS 2 and the left 2-bit shift signal LS 2 . Hereinafter, the 1-bit shift circuit 5 , the 2-bit shift circuit 6 , the 4-bit shift circuit 7 , the 8-bit shift circuit 8 , the 16-bit shift circuit 9 , and the 32-bit shift circuit 11 operate in the same way. The shift circuit 1 shifts the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) by an optional shift quantity from 1 bit to 64 bits. As shown in FIGS. 5 and 6 , in the shift-out detecting circuit 2 , the 1-bit detecting circuit (partial rounding detecting circuit) 13 detects that “1” is shifted out as the result of the shifting process by the 1-bit shift circuit 5 . The 2-bit detecting circuit 14 detects that “1” is shifted out as the result of the shifting process by the 2-bit shift circuit 6 . The 4-bit detecting circuit 15 detects that “1” is shifted out as the result of the shifting process by the 4-bit shift circuit 7 . Also, the detection result by the 1-bit detecting circuit 13 is inputted and the signal which contains this detection result is outputted. The 8-bit detecting circuit 16 detects that “1” is shifted out as the result of the shifting process by the 8-bit shift circuit 8 . The 16-bit detecting circuit 17 detects that “1” is shifted out as the result of the shifting process by the 16-bit shift circuit 9 . The 32-bit detecting circuit 18 detects that “1” is shifted out as the result of the shifting process by the 32-bit shift circuit 11 . The relaying circuit 19 inputs the detection results of the 2-bit detecting circuit 14 and 4-bit detecting circuit 15 , and outputs the signal which contains the detection results of the 1-bit shift circuit 5 , 2-bit shift circuit 6 , and 4-bit shift circuit 7 . The collecting circuit (rounding detection signal outputting circuit) 21 inputs the detection results of the relaying circuit 19 , 8-bit detecting circuit 16 , 16-bit detecting circuit 17 and 32-bit detecting circuit 18 , and outputs a sticky signal STOUT of “1”, when “1” is shifted out in either of does either of 1-bit shift circuit 5 , 2-bit shift circuit 6 , 4-bit shift circuit 7 , 8-bit shift circuit 8 , 16-bit shift circuit 9 , and 32-bit shift circuit of circuit 11 . As shown in FIG. 8 , the 1-bit detecting circuit 13 is composed of a 2-input NAND circuit. The 1-bit detecting circuit 13 inputs the right 1-bit shift signal RS 1 and least significant bit data a 0 , and outputs a sticky signal ST 1 to notify to processing circuit 4 that “1” is contained in the shifted out data in case of both being “1”. That is, the 1-bit detecting circuit 13 outputs the sticky signal ST 1 of “0”, when the right 1-bit shift signal RS 1 is “1” and a 1-bit right shift is carried out by the 1-bit shift circuit 5 , and the least significant bit data a 0 of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) supplied to the 1-bit shift circuit As shown in FIG. 9 , the 2-bit detecting circuit 14 has a 2-input OR 2-input NAND circuit 23 for carrying out the NAND logical operation of the OR output of the least significant bit data p 0 and the data the second bit p 1 and right 2-bit shift signal RS 2 and an inverter circuit 24 which inverts the output of 2-input OR 2-input NAND circuit 23 . That is, the 2-bit detecting circuit 14 outputs the sticky signal ST 2 to notify that “1” is contained in the shifted-out data, when the right 2-bit shift signal RS 2 is “1”, and the 2-bit right shift is carried out by the 2-bit shift circuit 6 and either of the least significant bit data p 0 and the second bit p 1 of the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) supplied to the 2-bit shift circuit 6 . As shown in FIG. 10 , the 4-bit detecting circuit 15 is composed of a 4-input NOR circuit 25 which carries out the NOR logical operation of the data from the least significant bit data q 0 to the fourth bit q 3 , an inverter circuit 26 which inverts and outputs the right 4-bit shift signal RS 3 , and a 2-input OR 2-input NAND circuit 27 which carries out the NAND logical operation of the OR output of the output of inverter circuit 26 and the output of the 4-input NOR circuit 25 and the sticky signal ST 1 . That is, the 4-bit detecting circuit 15 outputs the sticky signal ST 13 of “1” to notify that “1” is contained in the shifted out data, when the right 4-bit shift signal RS 3 is “1”, and the 4-bit right shift is carried out by the 4-bit shift circuit 7 , and at least one bit of the data from the least significant bit data q 0 to the fourth bit q 3 of the in the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) supplied to the 4-bit shift circuit 7 is “1” or the sticky signal ST 1 is “0”. As shown in FIG. 11 , the 8-bit detecting circuit 16 is composed of a 4-input NOR circuit 28 which carries out the NOR logical operation of bits from the least significant bit r 0 to the fourth bit r 3 , a 4-input NOR circuit 29 which carries out the NOR logical operation of bits from the fifth bit r 4 to the eight bit r 7 , an inverter circuit 31 which inverts and outputs the right 8-bit shift signal RS 4 , a 2-input AND 2-input NOR circuit 32 which carries out and outputs the NOR logical operation of the AND output of the 4-input NOR circuit 28 and the 4-input NOR circuit 29 and the output of the inverter circuit 31 , and an inverter circuit 33 which inverts and outputs the 2-input NAND 2-input NOR circuit 32 . That is, the 8-bit detecting circuit 16 outputs the sticky signal ST 4 of “0” to notify that “l 1 is contained in the shifted-out data, when the right 8-bit shift signal RS 4 is “1”, and an 8-bit right shift is carried out by the 8-bit shift circuit 8 , at least one of bits from the least significant bit data r 0 to the eighth bit r 7 of the output data (r 63 r 62 . . . r 3 r 2 r 1 r 0 ) supplied to the 8-bit shift circuit 8 is “1”. As shown in FIG. 12 , the 16-bit detecting circuit 17 is composed of a 4-input NOR circuit 34 which carries out the NOR logical operation of the bits from the least significant bit data so to the fourth bit S 3 , a 4-input NOR circuit 35 which carries out the NOR logical operation bits from the fifth bit s 4 to the eighth bit s 7 , a 4-input NOR circuit 36 which carries out the NOR logical operation of the bits from the ninth bit s 8 to the twelfth bit s 11 , a 4-input NOR circuit 37 which carries out the NOR logical operation of bits from the thirteenth bit s 12 to the sixteenth bit s 15 , a 4-input NAND circuit 38 which carries out the NAND logical operation of the outputs of 4-input NOR circuits 34 , 35 , 36 , 37 , and a 4-input NAND circuit 39 which carries out the NAND logical operation of the outputs of right 16-bit shift signal RS 5 and the 4-input NAND circuit 38 . That is, the 16-bit detecting circuit 17 outputs the sticky signal ST 5 of “0” to notify that “1” is contained in the shifted-out data, when the right 16-bit shift signal RS 5 is “1”, and the 16-bit right shift is carried out by the 16-bit shift circuit 9 , and at least one of bits from the least significant bit data so the sixteenth bit s 15 of the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) supplied to 16-bit shift circuit 9 is “1”. As shown in FIG. 13 , the 32-bit detecting circuit 18 is composed of 4-input NOR circuits 41 , 42 , . . . , and 48 , 4-input NAND circuits 49 and 51 and a 2-input OR 2-input NAND circuit 52 . The 4-input NOR circuit 41 carries out the NOR logical operation of bits from the least significant bit data t 0 to the fourth bit t 3 . The 4-input NOR circuit 42 carries out the NOR logical operation of bits from the fifth bit t 4 to the eighth bit t 7 . The 4-input NOR circuit 43 carries out the NOR logical operation of bits from the ninth bit t 8 to the twelfth bit t 11 . The 4-input NOR circuit 44 carries out the NOR logical operation of bits from the thirteenth bit t 12 to the sixteenth bit t 15 . The 4-input NOR circuit 45 carries out the NOR logical operation of bits from the seventeenth bit t 16 to the twentieth bit t 19 . The 4-input NOR circuit 46 carries out the NOR logical operation of bits from the twenty-first bit t 20 to the twenty-fourth bit t 23 . The 4-input NOR circuit 47 carries out the NOR logical operation of bits from the twenty-fifth bit t 24 to the twenty-eighth bit t 27 . The 4-input NOR circuit 48 carries out the NOR logical operation of bits from the twenty-ninth bit t 28 to the thirty-second bit t 31 . The 4-input NAND circuit 49 carries out the NAND logical operation of the outputs of 4-input NOR circuits 41 , 42 , 43 , and 44 . The 4-input NAND circuit 51 carries out the NAND logical operation of the outputs of the 4-input NOR circuits 45 , 46 , 47 , and 48 . The 2-input OR 2-input NAND circuit 52 carries out the NAND logical operation of the OR logical operation of the output of the 4-input NAND circuit 49 and the output of the 4-input NAND circuit 51 and the right 32-bit shift signal RS 6 . That is, as shown in FIG. 13 , the 32-bit detecting circuit 18 outputs the sticky signal ST 6 of “0” to notify that “1” is contained in the shifted-out data, when the right 32-bit shift signal RS 6 is “1”, and the 32-bit right shift is carried out by the 32-bit shift circuit 11 , and at least one of bits from the least significant bit data to t 0 the thirty-second bit t 31 of the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) supplied to the 32-bit shift circuit 11 is “1”. As shown in FIG. 6 , the relaying circuit 19 is composed of a NOR circuit which carries out the NOR logical operation of the sticky signal ST 2 and the sticky signal ST 3 . The relaying circuit 19 outputs a signal ST 123 of “0”, when one of the sticky signal ST 2 and the sticky signal ST 13 is “1”. As shown in FIG. 6 , the collecting circuit 21 is composed of a 4-input NAND circuit which carries out the NAND logical operation of the output of the relaying circuit 19 , and the sticky signals ST 4 , ST 5 and ST 6 and outputs a sticky signal ST. When at least one of the output signal ST 123 of the relaying circuit 19 , and the sticky signals ST 4 , ST 5 and ST 6 is “0”, the collecting circuit 21 outputs the sticky signal STOUT of “1”. It should be noted that in this example, although a delay is added to the signal output from collecting circuit 21 rather than the detecting circuit in the front-stage is connected directly with the concentration output circuit 21 of the last stage, when “there is a shift-out of “1”” is detected in the previous stage (e.g., by the 1-bit detecting circuit 13 ), the output signal is passed through the relaying circuit. Also, because the determination of “not being in the shift-out of “1”” is accomplished after the output from the 32-bit detecting circuit 18 is determined, the sticky signal is outputted to match to the timing of the determination of the 32-bit detecting circuit 18 by passing through the relaying circuit 19 . Thus, in this example, the number of logic stages for each sticky signal to be outputted from the collecting circuit 21 is set to 4 , to equalize the time required for the shift-out detecting process regardless of the shift quantity. Further, the size of a transistor of the logic circuit of the detecting circuit at the previous stage (for example, 1-bit detecting circuit 13 ) is made small compared with that of a transistor of the detecting circuit at the post stage (for example, 32-bit detecting circuit 18 ) to reduce the whole size while the calculation time is adjusted to the calculation time in the detecting circuit at the post stage. Also, in case of a composite gate, the size of the transistor is made relatively larger to reduce the calculation time. Next, the operations of the shift circuit 1 and shift-out detecting circuit 2 in this example will be described. In case of the 3-bit right shift, for example, all of the operation will be described when the least significant bit a 0 , the second bit al and the third bit a 2 of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) are “1”. As shown in FIGS. 5, 6 and 14 A, first, the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) is supplied to the shift circuit 1 . The comparing and subtracting circuit 3 set only the right 1-bit shift signal RS 1 and right 2-bit shift signal RS 2 to “1”, and outputs to the digit adjustment shift circuit 1 and shift-out detecting circuit 2 . When the 1-bit shift circuit 5 receives the right 1-bit shift signal RS 1 of “1”, only the clock inverter circuit 5 0 a is set to the conductive state in the multiplexer circuit 50 , and the least significant bit data aR 0 of the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) is inverted and is outputted from the clock inverter circuit 5 0 a . Moreover, it is again inverted by the inverter circuit 5 0 h to be returned to the least significant bit aR 0 , and then is sent out to the multiplexer circuit 6 0 of the 2-bit shift circuit 6 . In the same way, in the multiplexer circuits 5 1 , 5 2 , . . . , 5 63 , the corresponding bits of the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) are selected, and the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) obtained by shifting the right shifted data (aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 ) (&equals;(0a 63 a 62 . . . a 3 a 2 a 1 a 0 )) in a right direction by one bit is sent out to the 2-bit shift circuit 6 , as shown in FIG. 14B . When the 2-bit shift circuit 6 receives the right 2-bit shift signal RS 2 of “1”, only the clock inverter circuit 6 0 a is set to the conductive state in the multiplexer circuit 60 . The least significant bit pR 0 of right shifted data (pR 63 pR 62 . . . pR 3 pR 2 pR 1 pR 0 ) is inverted and is outputted from the clock inverter circuit 6 0 a , and then it is again inverted by the inverter circuit 6 0 h to be returned to the least significant bit pR 0 . Thereafter, the bit pR 0 is sent out to the multiplexer circuit 70 of the 4-bit shift circuit 7 . In the same way, in the multiplexer circuits 6 1 , 6 2 , . . . , 6 63 , the corresponding bit of the right shifted data (pR 63 pR 62 . . . pR 3 pR 2 pR 1 pR 0 ) is selected and the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) by shifting the right shifted (pR 63 pR 62 . . . pR 3 pR 2 pR 1 pR 0 ) (&equals;(000(a 63 a 62 . . . a 3 a 2 a 1 a 0 )) in a right direction by 3 bits is sent out to 4-bit shift circuit 7 , as shown in FIG. 14C . In the 4-bit shift circuit 7 , only the clock inverter circuit 7 0 c is set to the conductive state in the multiplexer circuit 7 0 . The least significant bit q 0 of the output (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) is inverted and is outputted from the clock inverter circuit 7 0 a , and then it is again inverted by the inverter circuit 7 0 h to be returned to the least significant bit q 0 . Thereafter, it is sent out to the multiplexer circuit 80 of the 8-bit shift circuit 8 . In the same way in the multiplexer circuits 7 1 , 7 2 , . . ., 7 63 , the corresponding bit of the output (q 63 q 62 q 3 q 2 q 1 q 0 ) is selected, and the outputs data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) is sent out to the 8-bit shift circuit 8 as the output data (r 63 r 62 . . . r 3 r 2 rlr 0 ) In the 8-bit shift circuit 8 , 16-bit shift circuit 9 and 32-bit shift circuit 11 , only the clock inverter circuit 8 0 c ( 9 0 c , 11 0 c ) is set to the conductive state in the multiplexer circuit 8 0 ( 9 0 , 11 0 ), for example. Therefore, the relation ((r 63 r 62 . . . r 3 r 2 r 1 r 0 )&equals;(s 63 s 62 . . . s 3 s 2 s 1 s 0 )&equals;(t 63 t 62 . . . t 3 t 2 t 1 t 0 )) is satisfied. The output data (b 63 b 62 . . . b 3 b 2 b 1 b 0 ) from the 32-bit shift circuit 11 becomes equal to the data obtained by shifting the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) supplied to the digit adjustment shift circuit 1 in the right direction by 3 bits. On the other hand, in the shift-out detecting circuit 4 , the 1-bit detecting circuit 13 outputs the sticky signal ST 1 of “0”, when the right 1-bit shift signal RS 1 and the least significant bit a 0 of the mantissa (a 63 a 62 a 3 a 2 a 1 a 0 ) are all “1”, as shown in FIGS. 5 and 6 . In this example, the sticky signal ST 1 of “0” is sent out to the 4-bit detecting circuit 15 because (a 0 &equals;1). Also, the 2-bit detecting circuit 14 outputs the sticky signal ST 2 of “1”, when the right 2-bit shift signal RS 2 is “1”, and at least one of the second bit p 1 and the least significant bit p 0 of the output data (p 63 p 62 . . . p 3 p 2 p 1 p 0 ) is “1”. In this example, because ((p 63 p 62 . . . p 3 p 2 p 1 p 0 0)&equals;(aR 63 aR 62 . . . aR 3 aR 2 aR 1 aR 0 )&equals;(0a 63 a 62 . . . a 3 a 2 a 1 a 0 ), and (a 1 &equals;a 2 &equals;1), (p 1 &equals;p 0 &equals;1). Therefore, the 2-bit detecting circuit 14 sends out the sticky signal ST 2 of the “1” state to the relaying circuit 19 . The 4-bit detecting circuit 15 outputs the sticky signal ST 13 of “1”, when the right 4-bit shift signal RS 3 is “1”, and at least one of bits from the least significant bit q 0 to the fourth bit q 3 of the output data (q 63 q 62 . . . q 3 q 2 q 1 q 0 ) supplied to the 4-bit shift circuit 7 is “1” or the sticky signal ST 1 is “0”. In this example, the sticky signal ST 13 of “1” is outputted because the right 4-bit shift signal RS 3 is “0” but the sticky signal ST 1 is “0”. The relay output circuit 19 outputs the sticky signal ST 123 of “0”, when at least one of the sticky signal ST 2 and the sticky signal ST 3 is “1”. In this example, because the sticky signal ST 2 and the sticky signal ST 13 are both “1”, the output signal ST 123 of the “0” state is sent out to the output circuit 21 . The 8-bit detecting circuit 16 outputs the sticky signal ST 4 of “0”, when the right 8-bit shift signal RS 4 is “1” and at least one of bits from the least significant bit r 0 to the eighth bit r 7 of the output data (r 63 r 62 * r 3 r 2 r 1 r 0 ) is 1 ”. Because the right 8-bit shift signal RS 4 is “1” in this example, the sticky signal ST 4 of the “1” state is sent out to the collecting circuit 21 . The 16-bit detecting circuit 17 outputs the sticky signal ST 5 of “0”, when the right 16-bit shift signal RS 5 is “1” and at least one of bits from the least significant bit s 0 to the sixteenth bit s 15 of the output data (s 63 s 62 . . . s 3 s 2 s 1 s 0 ) is “1”. In this example, because the right 16-bit shift signal RS 5 is “0”, the sticky signal ST 5 of the “1” state is sent out to the output circuit 21 . The 32-bit detecting circuit 18 outputs the sticky signal ST 6 of “0”, when the right 32-bit shift signal RS 6 is “1” and at least one of bits from the least significant bit t 0 to the thirty-second bit t 31 of the output data (t 63 t 62 . . . t 3 t 2 t 1 t 0 ) is “1”. In this example, because the right 32-bit shift signal RS 6 is “0”, the sticky signal ST 6 of the “1” state is sent out to the collecting circuit 21 . The collecting circuit 21 outputs the sticky signal STOUT of “1”, when at least one of the output signal ST 123 from the relaying circuit 19 , the sticky signals ST 4 , ST 5 , ST 6 is “0” . In this example, because the output signal ST 123 from the relaying circuit 19 is “o”, the sticky signal STOUT of the “1” state is sent out to the rounding process circuit 4 to indicate that the shift-out of “1” is detected by the shift circuit 1 in the shifting process. It should be noted that the shifting process to the direction of the most significant bit (left shift) is carried out like the right shift mentioned above. The left shifting process is carried out in a case of the normalization shift when the integer part becomes “0” as the result of a subtracting process, and in case of the digit adjusting process in which data is left-shifted by a predetermined bit quantity and outputted from the once from shift circuit 1 , and then the outputted data is inputted again and right-shifted by a predetermined bit quantity. Next, a floating-point addition and subtraction calculating circuit 61 using the shift circuit 1 and shift-out detecting circuit 2 in this example will be described. As shown in FIG. 15 , the floating-point addition and subtraction calculating circuit (the floating-point calculating circuit) 61 is composed of a comparing and subtracting circuit 62 which determines a larger one of the exponents E 1 and E 2 , a digit adjustment shift circuit 63 , a shift-out detecting circuit 64 , a rounding process circuit 65 , a mantissa addition and subtraction calculating circuit 66 , a normalization shift circuit 67 , a shift-out detecting circuit 68 , a rounding process circuit 69 and an exponent increasing and decreasing circuit 71 . The comparing and subtracting circuit 62 inputs two floating-point numbers X 1 , X 2 , and outputs the addition result (summation) X 3 (&equals;X 1 &plus;X 2 ) of the floating-point number X 1 and the floating-point number X 2 . The comparing and subtracting circuit 62 inputs the floating-point number X 1 , X 2 and the exponent E 1 , E 2 and determines a larger one of the exponents E 1 , E 2 . The digit adjustment shift circuit 63 shifts the mantissa of the floating-point number with smaller exponent to the direction of the least significant bit to adjust the digit. The shift-out detecting circuit 64 checks whether or not “1” is contained in the shifted-out data. The rounding process circuit 65 shortens shifted data to the number of digits of the format in a predetermined rounding method. The mantissa addition and subtraction calculating circuit 66 carries out an addition and subtraction calculation of mantissas. The normalization shift circuit 67 normalizes an addition and subtraction calculation result. The shift-out detecting circuit 68 checks whether there is shifted-out as a result of the normalization and “1” is contained in the shifted-out data. The rounding process circuit 69 shortens the shifted data to the number of digits in the format in a predetermined rounding method. The exponent increasing and decreasing circuit 71 corrects the exponent based on the normalization shift quantity. Here, the above mentioned shift circuit 1 and shift-out detecting circuit 2 are used as the digit adjustment shift circuit 63 , the shift-out detecting circuit 64 , the normalization shift circuit 67 and the shift-out detecting circuit 68 . Next, the operation of the floating-point number addition and subtraction calculating circuit 61 of this example will be described. First, the comparing and subtracting circuit 62 inputs the exponent E 1 , E 2 of two floating-point numbers X 1 , X 2 and determines a larger one of the exponents E 1 , E 2 , and calculates the difference (E 1 −E 2 ) or (E 2 −E 1 ). Then, the comparing and subtracting circuit 62 outputs the comparing signal and a digit adjustment shift quantity signal. The digit adjustment shift circuit 63 inputs the mantissa F 1 , F 2 of the floating-point numbers X 1 , X 2 , the comparing signal and the digit adjustment shift quantity signal, makes the smaller one of the exponents E 1 , E 2 equal to the larger one based on the comparing signal and the digit adjustment shift quantity signal. Then, the digit adjustment shift circuit 63 shifts the mantissa for the smaller exponent to the direction of the least significant bit by the difference. The digit adjustment shift circuit 63 inputs the mantissa for the smaller exponent of mantissas Fl, F 2 . For example, in case of 64 bits, the digit adjustment shift circuit 63 inputs a 63 , a 62 , . . . , a 3 , a 2 , a 1 , a 0 of the respective digits of F 1 (F 2 )&equals;(a 63 a 62 . . . a 3 a 2 a 1 a 0 ). The shift-out detecting circuit 64 outputs the sticky signal STOUT of “1” to promote the rounding process determining process, when “1” is contained in the shifted-out data as the result of the shifting process by the digit adjustment shift circuit 63 . The sticky signal STOUT outputted from the shift-out detecting circuit 64 is used for the determination of whether data correction should be carried out in accordance with the digit adjustment in the floating-point calculation. The rounding process circuit 65 shortens the calculation result obtained from the digit adjustment shift circuit 63 to the number of digits ( 64 digits in this example) of the format in a predetermined rounding method based on the sticky signal STOUT outputted from the shift-out detecting circuit 64 and the shifted-out data. Here, the rounding process circuit 65 receives the shifting process result from the digit adjustment shift circuit 63 and carries out the predetermined rounding process, after receiving the sticky signal STOUT and starting the determining process of the rounding method. The rounding process circuit 65 selects and carries out a suitable one of the rounding processes to round a value to a near value to the value, to round the value for 0, to round the value for the positive infinity, and to round the value for the negative infinity, based on the sticky signal STOUT and the shifted-out data, for reduction an accumulated error. The mantissa addition and subtraction calculating circuit 66 carries out the addition and subtraction calculation of mantissa after the digit adjustment rounded by the rounding process circuit 65 . The normalization shift circuit 67 calculates the number of digits as a normalization shift quantity to the integer part from the digit of the most significant bit of “1” of the addition and subtraction calculation result obtained from the mantissa addition and subtraction calculating circuit 66 and carries out a shifting process by the normalization shift quantity. The shift-out detecting circuit 68 outputs the sticky signal STOUT to promote the rounding process determining process when “1” is contained in the shifted-out data at least as the result of the shifting process by the normalization shift circuit 67 . The sticky signal STOUT outputted from the shift-out detecting circuit 68 is used for the determination of whether data correction should be carried out as the result of the digit adjustment by the floating-point calculation. The rounding process circuit 69 shortens the calculation result obtained in the normalization shift circuit 67 to the number of digits of the format in a predetermined rounding method based on the sticky signal STOUT outputted from the shift-out detecting circuit 68 and the shifted-out data. The rounding process circuit 69 receives the sticky signal STOUT and then receives the shifting process result from the digit adjustment shift circuit 63 or the normalization shift circuit 67 after starting the rounding method determining process, and thereafter carries out the predetermined rounding method. The exponent increasing and decreasing circuit 71 corrects the exponent based on the normalization shift quantity obtained by the normalization shift circuit 67 and outputs the exponent E 3 of the calculation result X 3 (&equals;X 1 &plus;X 2 ). In this way, according to the circuit structure in this example, the sticky signals ST 1 , ST 2 , . . . , and ST 6 outputted from the 1-bit detecting circuit 13 , the 2-bit detecting circuit 14 , the 4-bit detecting circuit 15 , the 8-bit detecting circuit 16 , the 16-bit detecting circuit 17 , and the 32-bit detecting circuit 18 are collected by the collecting circuit 21 directly or via the relaying circuit 19 (the sticky signal ST 1 passes through the 4-bit detecting circuit 15 ). Then, finally, the sticky signal STOUT is outputted. For example, the number of logic stages through which the sticky signal ST 1 (ST 2 , ST 3 , . . . , ST 6 ) passes is as less as 4 regardless of the shift quantity, compared with a conventional example in which the number of stages is 13 . Therefore, as in the conventional example, the unnecessary delay in case of the output of the sticky signal S 1 of “1” via all the 2-input selectors 122 , 123 , . . . , 127 can be reduced. For this reason, the generation of the shift out (rounding) of “1” can be detected at high speed, and the sticky signal STOUT can be outputted to inform that the shift-out of “1” is generated to the rounding process circuit 65 ( 69 ), before the shifted data is outputted from the digit adjustment shift circuit 63 (the normalization shift circuit 67 ). Therefore, it is possible to contribute to the improvement in operation speed of the floating-point addition and subtraction calculating circuit 61 . Also, for example, because the 4-input NAND circuit is used, the collecting circuit 21 can rather reduce the calculation time, compared with the 6-input NAND circuit. Also, by reducing the size of a transistor of the logic circuit of the detecting circuit at the previous stage (e.g., the 1-bit shift circuit 13 ) compared with the size of a transistor of the side of the subsequent stage (e.g., the 32-bit detecting circuit 18 ), the size of the shift circuit and the size of the whole shift-out detecting circuit can be reduced, while attempting to shorten an average calculation time. &lsqb;The Second Embodiment&rsqb; FIG. 16 is the circuit diagram showing the circuit structure of the multiplexer circuit of the shift circuit according to the second embodiment of the present invention. This example is different from the above mentioned first embodiment in that the 1-bit shift circuit 1 and the 2-bit shift circuit 2 are collected into a variable shift circuit which can carry out 1-bit shift, 2-bit shift and 3-bit shift. Because the circuit structure except this is the same as that of the above mentioned first embodiment, the brief description is given. The variable shift circuit for 64 bits is composed of the multiplexer circuits 81 0 , 81 1 , . . . , 81 63 . For example, the multiplexer circuit 81 0 corresponding to the least significant bit is composed of clock inverter circuits 81 0 a , 81 0 b , 81 0 c , 81 0 d , 81 0 e , 81 0 f , and 81 0 g , 2-input NAND circuits 81 0 h , 81 0 j , 81 0 m , and 81 0 p , and inverter circuits 81 0 i , 81 0 k , 81 0 l , 81 0 n , 81 0 o , 81 0 q , 81 0 r , 81 0 s , 81 0 u , and 81 0 v , as shown in FIG. 16 . Each of the clock inverter circuits 81 0 a , 81 0 b , 81 0 c , 81 0 d , 81 0 e , 81 0 f , and 81 0 g is set to the conductive state to invert an input signal or to the blocking-off state to prevent the passage of the input signal, according to the state of the control signals supplied to two control terminals &phgr; 1 , &phgr; 2 . The 2-input NAND circuit 81 0 h receives the right 1-bit shift signal RS 1 and the right 2-bit shift signal RS 2 and outputs the NAND calculation result of both. The inverter circuit 81 0 i inverts the output of the 2-input NAND circuit 81 0 h. The 2-input NAND circuit 81 0 j receives the left 1-bit shift signal LS 1 and the left 2-bit shift signal LS 2 and outputs the NAND calculation result of both. The inverter circuit 81 0 k inverts the output of the 2-input NAND circuit 81 0 j . The inverter circuit 8101 inverts the right 1-bit shift signal RS 1 . The 2-input NAND circuit 81 0 m receives the output of the inverter circuit 81 0 l and the right 2-bit shift signal RS 2 and outputs the NAND calculation result of both. The inverter circuit 81 0 n inverts the output of the 2-input NAND circuit 81 0 m. The inverter circuit 81 0 O receives and inverts the left 1-bit shift signal LS 1 . The 2-input NAND circuit 81 0 p receives the output of the inverter circuit 81 0 O and the left 2-bit shift signal LS 2 , and outputs the NAND calculation result of both. The inverter circuit 81 0 q inverts the output of the 2-input NAND circuit 81 0 p. The inverter circuit 81 0 r receives and inverts the right 1-bit shift signal RS 1 to give to the control terminal &phgr; 2 of the clock inverter circuit 81 0 e. The inverter circuit 81 0 s receives and inverts the left 1-bit shift signal LS 1 to give to the control terminal &phgr; 2 of the clock inverter circuit 81 0 f. The NOR circuit 81 0 t receives the right 1-bit shift signal RS 1 , the left 1-bit shift signal LS 1 , the right 2-bit shift signal RS 2 and the left 2-bit shift signal LS 2 , and outputs the non-selection signal of the “1” state only when all 4 signals are in the “0” state. The inverter circuit 81 0 u receives and inverts the output signal of the NOR circuits 81 0 t to give to the control terminal &phgr; 2 of the clock inverter circuit 81 0 g. The inverter circuit 81 0 v inverts and outputs either of the output signals from the clock inverter circuits 81 0 a , 81 0 b , 81 0 c , 81 0 d , 81 0 e , 81 0 f , and 81 0 g. Here, the output signals from the inverter circuit 81 0 i and the 2-input NAND circuit 81 0 h are supplied to the control terminals &phgr; 1 , &phgr; 2 of 81 0 a of the clock inverter circuits, respectively. Also, the output signals from the inverter circuit 81 0 k and the 2-input NAND circuit 81 0 j are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 b , respectively. Also, the output signals from the inverter circuit 81 0 n and the 2-input NAND circuit 81 0 m are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 c , respectively. Also, the output signals from the inverter circuit 81 0 q and the 2-input NAND circuit 81 0 p are supplied to the control terminals &phgr; 1 , &phgr; 2 Of the clock inverter circuit 81 0 d , respectively. Also, the right 1-bit shift signal RS 1 and the output signal from the inverter circuit 81 0 r are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 e , respectively. Also, the left 1-bit shift signal LS 1 and the output signal from the inverter circuit 810 s are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 f , respectively. Also, the output signals from the NOR circuit 81 0 t and the inverter circuit 81 0 u are supplied to the control terminals &phgr; 1 , &phgr; 2 Of the clock inverter circuit 81 0 g , respectively. Next, the operation of the multiplexer circuit 810 will be described. First, when only the right 1-bit shift signal RS 1 and the right 2-bit shift signal RS 2 are received at the same time, the output of the 2-input NAND circuit 81 0 h becomes “0”. When “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 a , respectively, only the clock inverter circuit 81 0 a becomes a conductive state, and a bit data a 3 R 0 obtained by shifting the least significant bit a 0 of the mantissa in the right direction by 3 bits passes the clock inverter circuit 810 a and is outputted from the inverter circuit 810 v . Also, when only the left 1-bit shift signal LS 1 and the left 2-bit shift signal LS 2 are received at the same time, the output of the 2-input NAND circuit 81 0 j becomes “0”. Also, when “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 b , respectively, only the clock inverter circuit 81 0 b become the conductive state, and a bit data a 3 L 0 obtained by shifting the least significant bit a 0 of the mantissa in the left direction by 3 bits passes the clock inverter circuit 81 0 b and is outputted from the inverter circuit 81 0 v. Also, when only the right 2-bit shift signal RS 2 is received, the output of the 2-input NAND circuit 81 0 m becomes “0”. Also, when “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 c , respectively, only the clock inverter circuit 81 0 c of become conductive state a bit data a 2 R 0 obtained by shifting the least significant bit a 0 of the mantissa in the right direction by 2 bits passes the clock inverter circuit 81 0 c and is outputted from the inverter circuit 81 0 v. Also, when only the left 2-bit shift signal LS 2 is received, the output of the 2-input NAND circuit 81 0 p becomes “0”. Also, when “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 d , respectively, only the clock inverter circuit 81 0 d becomes the conductive state. As a result, a bit data a 2 L 0 obtained by shifting the least significant bit a 0 with mantissa in the left direction by 2 bits passes the clock inverter circuit 81 0 d and is outputted from the inverter circuit 81 0 v. Also, when only the right 1-bit shift signal RS 1 is received, “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 e , respectively. Only the clock inverter circuit 81 0 e becomes conductive state, and a bit data aR 0 obtained by shifting the least significant bit a 0 of the mantissa in the right direction by 1 bit passes the clock inverter circuit 81 0 e and is outputted from the inverter circuit 81 0 v. Also, when only the left 1-bit shift signal LS 1 is received, “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 f , respectively. Only the clock inverter circuit 81 0 f becomes conductive state, and a bit data aL 0 obtained by shifting the least significant bit a 0 of the mantissa in the left direction by 1 bit passes the clock inverter circuit 81 0 f and is outputted from the inverter circuit 81 0 v. Also, when neither of the right 1-bit shift signal RS 1 , the right 2-bit shift signal RS 2 , the left 1-bit shift signal LS 1 , the left 2-bit shift signal LS 2 is received, the non-selection signal of the “1” state is outputted from the NOR circuit 81 0 t. Also, “1” and “0” are supplied to the control terminals &phgr; 1 , &phgr; 2 of the clock inverter circuit 81 0 g , respectively, and only the clock inverter circuit 81 0 g become conductive state. As a result, the least significant bit a 0 of the mantissa passes through the clock inverter circuit 81 0 g as it is and is outputted from the inverter circuit 81 0 v. In the same way, even in case of second bit or subsequent bits, the shifting process of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) is carried out by shifting it by a predetermined shift quantity. According to the circuit structure in this example, the sticky signals outputted from the variable shift circuit, the 4-bit detecting circuit 15 , the 8-bit detecting circuit 16 , the 16-bit detecting circuit 17 , and the 32-bit detecting circuit 18 are collected by the collecting circuit 21 directly or via the relaying circuit 19 , and finally the sticky signal STOUT is outputted. Therefore, the sticky signal STOUT can be sent to the rounding process circuit 65 ( 69 ) at high speed and it is possible to contribute to the improvement in the operation speed of the floating-point addition and subtraction calculating circuit 61 . Also, the number of logic stages in the multiplexer circuit 81 0 can be reduced from 4 to 2 , compared with the case of using the multiplexer circuits 5 0 , 6 0 . Therefore, the shifting process can be sped up. &lsqb;The Third Embodiment&rsqb; FIG. 17 is a block diagram showing the circuit structure of the shift circuit and the shift-out detecting circuit according to the third embodiment of the present invention. Also, FIG. 18 is a circuit diagram showing the circuit structure of the 4-bit detecting circuit and the 2-bit detecting circuit of the same shift-out detecting circuit. This example is different from the abovementioned first embodiment in that the bit shift circuits are arranged from the 32-bit shift circuit such that the shift quantities of the respective bit shift circuits are arranged in a descending order. As shown in FIG. 17 , the shift circuit 32 is composed of a 32-bit shift circuit 83 to carry out 32 b it right shift of the mantissa (a 63 a 62 . . . a 3 a 2 a 1 a 0 ) when receiving the right 32-bit shift signal RS 6 of “1” from the comparing and subtracting circuit 3 , a 16-bit shift circuit 84 to carry out 16-bit right shift of the output data of the 32-bit shift circuit 83 when receiving the right 16-bit shift signal RS 6 of “1”, a 8-bit shift circuit 85 to carry out 8-bit right shift of the output data of the 16-bit shift circuit 84 when receiving the right 8-bit shift signal RS 4 of “1”, a 4-bit shift circuit 86 to carry out 4-bit right shift of the output data of the 8-bit shift circuit 85 when receiving the right 4-bit shift signal RS 3 of “1”, a 2-bit shift circuit 87 to carry out 2-bit right shift of the output data of the 4-bit shift circuit 86 when receiving the right 2-bit shift signal RS 2 of “1”, and a 1-bit shift circuit 88 to carry out 1-bit right shift of the output data of the 2-bit shift circuit 87 when receiving the right 1-bit shift signal RS 1 of “1”. As shown in FIG. 17 , the shift-out detecting circuit 89 is composed of a 32-bit detecting circuit which detects the shift-out of “1” as a result of the shifting process in the 32-bit shift circuit 83 , a 16-bit detecting circuit 91 which detects the shift-out of “1” as a result of the shifting process in the 16-bit shift circuit 84 , a 8-bit detecting circuit 92 which detects the shift-out of “1” as a result of the shifting process in the 8-bit shift circuit 85 , a 4-bit detecting circuit 93 which detects the shift-out of “1” as a result of the shifting process in the 4-bit shift circuit 86 , a 2-bit detecting circuit 94 which detects the shift-out of “1” as a result of the shifting process in the 2-bit shift circuit 87 , a 1-bit detecting circuit 95 which detects the shift-out of “1” as a result of the shifting process in the 1-bit shift circuit 88 , and a collecting circuit 96 which detects the shift-out of “1” in either of the 1-bit shift circuit 88 , the 2-bit shift circuit 87 , the 4-bit shift circuit 86 , the 8-bit shift circuit 85 , the 16-bit shift circuit 84 , and the 32-bit shift circuit 83 to output the sticky signal STOUT. It should be noted that as shown in FIGS. 17 and 18 , in this example, the sticky signal ST 3 outputted from the 4-bit detecting circuit 93 is once supplied to the 2-bit detecting circuit 94 . The 2-bit detecting circuit 94 outputs the sticky signal ST 23 of “0” when the sticky signal ST 3 is “1” or the shift-out of “1” is detected in the 2-bit shift circuit 87 . As shown in FIG. 18 , the 4-bit detecting circuit 93 is composed of a 4-input NOR circuit 93 a which carries out the NOR logical operation of bits from the least significant bit to fourth bit, a inverter circuit 93 b which inverts and output the right 4-bit shift signal RS 3 , and a NOR circuit 93 c which carries out the NOR logical operation of the output of the inverter circuit 93 b and the output of the 4-input NOR circuit 93 c and outputs the sticky signal ST 3 . Also, as shown in FIG. 18 , the 2-bit detecting circuit 94 is composed of a 2-input OR 2-input NAND circuit 94 a which carry out the NAND logical operation of the OR output between the least significant bit and the second bit and the right 2-bit shift signal RS 2 , an inverter circuit 94 b which invert the output of the 2-input OR 2-input NAND circuit 94 a , and a 2-input NOR circuit 94 c which carries out the NOR logical operation of the output of the inverter circuit 94 b and the sticky signal ST 3 and output the sticky signal ST 23 . The operations of the shift circuit 82 and the shift-out detecting circuit 89 in this example are almost the same as those of the first embodiment except that the order of the shift quantities to be shifted in one bit shift circuit is different, when the bit shift circuits are combined and operated. Therefore, the description is omitted. According to the circuit structure in this example, the sticky signals outputted from the 32-bit detecting circuit 90 , the 16-bit detecting circuit 91 , the 8-bit shift detecting circuit 92 , the 2-bit detecting circuit 94 , the 1-bit detecting circuit 95 are directly collected by the collecting circuit 96 and the sticky signal outputted from the 4-bit detecting circuit 93 is collected by the collecting circuit 96 via the 2-bit detecting circuit 94 . The collecting circuit outputs the sticky signal STOUT as the last output. Therefore, the sticky signal STOUT can be sent to the rounding process circuit 65 ( 69 ) at high speed and it is possible to contribute to the improvement in the operation speed of the floating-point addition and subtraction calculating circuit 61 . Also, the respective bit shift circuits are arranged in order of 32-bit shift circuit 83 , 7 , the 16-bit shift circuit 84 , the 8-bit shift circuit 85 , the 4-bit shift circuit 86 , the 2-bit shift circuit 87 and the 1-bit shift circuit 88 , that is, in order of larger shift quantity from the input side. Therefore, when the right 32-bit shift signal RS 6 is “1”, for example, the 32-bit detecting circuit 90 corresponding to 32-bit shift circuit 83 can output the calculation result at the timing earlier than in the first embodiment. As described above, the embodiments of the present invention are described in detail, with reference to the drawings. However, a specific circuit structure is not limited to these embodiments. Any modification which is not apart from the spirits of the present invention is contained in the present invention even if there is a change of the design. For example, in the above mentioned embodiments, the case where the multiplexer circuit 5 0 is composed of the clock inverter circuits 5 0 a , 5 0 b , 5 0 c is described. However, as shown in FIG. 19 , the NAND circuit may be used in places of the clock inverter circuit. Also, in place of the multiplexer circuit 5 0 , the multiplexer circuit 97 0 may be composed of a NAND circuit 97 0 a which carries out the NAND operation of the right 1-bit shift signal RS 1 and the right 1-bit shift data aR 0 and outputs the calculation result, a NAND circuit 97 0 b which carries out the NAND operation of the left 1-bit shift signal LS 1 and left 1-bit shift data aL 0 and outputs the calculation result, a NAND circuit 97 0 c which carries out the NAND operation of the operation result of a NOR circuit 97 0 d which carries out the NOR operation of the right 1-bit shift signal RS 1 and the left 1-bit shift signal LS 1 , and the least significant bit a 0 of the mantissa, and a NAND circuit 97 0 e which carries out the NAND operation of the outputs of the NAND circuit 97 0 a , 97 0 b and 97 0 c . By this, a circuit can be simplified and the number of parts can be reduced. Also, in the above mentioned embodiment, eight 4-input NOR circuits 41 , 42 , . 48 are used in the 32-bit detecting circuit 18 . However, in place of these circuits, the 32-bit detecting circuit 98 may be formed using four 8-input NOR circuits 98 a , 98 b , 98 c , and 98 d. This 32-bit detecting circuit 98 is composed of 8-input NOR circuits 98 a , 98 b , 98 c and 98 d , and the 4-input NAND 2-input NOR circuit 98 f which outputs the NOR calculation result of the AND calculation result of the outputs of the 8-input NOR circuits 98 a , 98 b , 98 c and 98 d , and the output of an inverter circuit 98 e which inverts the right 32-bit shift signal RS 6 . Thus, the number of logic stages can be reduced. Also, in the first embodiment, the case where the shift-out detecting circuit 2 outputs the sticky signals ST 1 , ST 2 , and ST 3 to the collecting circuit 21 via the relaying circuit 19 is described. However, the shift-out detecting circuit 99 may be formed using a 6-input collecting circuits 99 a such that the sticky signals ST 1 , ST 2 , and ST 3 are directly supplied to the collecting circuits 99 a. By this, when there is a shift-out of “1” is detected at the previous stage (e.g., the detecting circuit of 1 bit), it is possible to output the signal output from the collecting circuit 99 a of the last stage at an earlier timing and the calculation can be sped up. Also, the case where the digit adjustment shift circuit 1 and the shift-out detecting circuit 2 are provided separately for the digit adjustment shift and the normalization shift is described. However, the circuits may be shared. Also, the rounding process circuit may be shared by the digit adjustment shift and the normalization shift. By this, the floating-point addition and subtraction calculating circuit can be simplified. Also, the case where the present invention is applied to the rounding process in digit adjustment and the normalization process in the addition and subtraction calculation of the floating-point numbers is described. However, the present invention may be applied to the rounding process in case that a number is divided by a number with a power of 2. Also, the case that the mantissa of the shift object is 64 bits is described but the present invention is not limited to this. As described above, according to the present invention, a partial rounding detection signal outputted from at least one of partial rounding process circuit other than the partial rounding process circuit of a last stage does not pass through other partial rounding process circuits. The rounding detection signal outputted from the rounding detecting signal outputting circuit can be transferred to the rounding process circuit at high speed. Therefore, it is possible to contribute to the improvement in the operation speed of the floating-point calculating circuit. Also, the size of an active element of the partial rounding detecting circuit corresponding to the partial shift circuit with a relatively large partial shift quantity is set larger than the size of an active element of the partial rounding detecting circuit corresponding to the partial shift circuit with a relatively small partial shift quantity. Therefore, the whole rounding detecting circuit can be reduced in size while attempting to shorten the average calculation time.