METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concepts of the present disclosure relate to methods of manufacturing a semiconductor device.

With the recent size reduction in memory cell for high integration of information and communication devices, operating circuits and/or wiring structures in memory devices for operation and electrical connection of semiconductor devices have also been complicated. Accordingly, an extreme ultraviolet (EUV) lithography process has been increasingly applied in manufacture semiconductor devices. The EUV lithography, for example, is a lithography technology that uses light with a wavelength of about 4 nm to about 124 nm, preferably 13.5 nm, and enables ultra-fine dimensional processing of less than 20 nm (Sub-20 nm), which is difficult to implement with conventional ArF excimer laser. A feedback process including overlay measurement and analysis is one of the key factors for securing reliability of the EUV lithography process. Accordingly, various studies have been conducted for improving the accuracy and reliability of the overlay measurement.

SUMMARY

The inventive concepts of the present disclosure provide methods of manufacturing a semiconductor device.

According to an example embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first material layer and a first photoresist (PR) layer on a first substrate, forming a first PR pattern on the first material layer by a first exposing process on the first PR layer in a first exposing apparatus, the first exposing process including exposing plurality of first field areas of the first PR layer, forming a first pattern layer by an etching process on the first material layer using the first PR pattern as an etching mask, sequentially forming a second material layer and a second PR layer on the first pattern layer, forming a second PR pattern on the second material layer by a second exposing process on the second PR layer in a second exposing apparatus, the second exposing process including exposing a plurality of first top field areas and a plurality of first bottom field areas of the second PR layer, the first top field areas vertically overlapping first portions of corresponding ones of the first field areas, respectively, and the first bottom field areas vertically overlapping second portions of corresponding ones of the first field areas, respectively, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, determining a top intra-field correction parameter based on the first top intra-field overlay and a first top intra-field correction function, determining a bottom intra-field correction parameter based on the first bottom intra-field overlay and a first bottom intra-field correction function, feeding back the determined top intra-field correction parameter and the determined bottom intra-field correction parameter to the second exposing apparatus, inspecting the second PR pattern, selectively reworking the second PR pattern based on an inspection results, to form the semiconductor device.

According to an example embodiment, a method of manufacturing a semiconductor device includes forming a first layer on a first substrate, sequentially forming a second layer and a photoresist (PR) layer on the first layer, forming a PR pattern on the second layer by exposing top field areas and bottom field areas of the PR layer in a first exposing apparatus, the top field areas arranged in a first line in parallel with a first direction, the bottom field areas arranged in a second line in parallel with the first direction, the first line and the second line being spaced apart in a second direction perpendicular to the first direction, measuring a top intra-field overlay for the top field areas and a bottom intra-field overlay for the bottom field areas, determining a top intra-field correction parameter based on the top intra-field overlay and a bottom intra-field correction parameter based on the bottom intra-field overlay, feeding back the determined top intra-field correction parameter and the determined bottom intra-field correction parameter to the first exposing apparatus, inspecting the PR pattern, and selectively reworking the PR pattern based on an inspection result, to form the semiconductor device, wherein each of the top field areas has a first reduction ratio in the first direction and a second reduction ratio in the second direction with respect to a photomask of the first exposing apparatus, each of the bottom field areas has a first reduction ratio in the first direction and a second reduction ratio in the second direction with respect to the photomask of the first exposing apparatus, and the first reduction ratio and the second reduction ratio are different from each other.

According to an example embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first material layer and a first photoresist (PR) layer on a first substrate, forming a first PR pattern by a first exposing process on the first PR layer in a first exposing apparatus, the first exposing process including exposing first field areas of the first PR layer, forming a first pattern layer by a first etching process on the first material layer using the first PR pattern as an etching mask, sequentially forming a second material layer and a second PR layer on the first pattern layer, forming a second PR pattern by a second exposing process on the second PR layer in a second exposing apparatus, the second exposing process including exposing a plurality of first top field areas and a plurality of first bottom field areas of the second PR layer, each of the first top field areas vertically overlapping first portions of corresponding ones of the first field areas, and each of the first bottom field areas vertically overlapping second portions of corresponding ones of the first field areas, respectively, forming a second pattern layer by a second etching process on the second material layer using the second PR pattern as an etching mask, the second pattern layer including second top field areas vertically overlapping the first top field areas and second bottom field areas vertically overlapping the first bottom field areas, measuring a top intra-field overlay for the second top field areas and a bottom intra-field overlay for the second bottom field areas, determining a top intra-field correction parameter based on the top intra-field overlay and a top intra-field correction function, determining a bottom intra-field parameter based on the bottom intra-field overlay and a bottom intra-field correction function, feeding back the determined top intra-field correction parameter and the determined bottom intra-field correction parameter to the second exposing apparatus, inspecting the second PR pattern, and selectively reworking the second PR pattern based on an inspection result, to form the semiconductor device.

DETAILED DESCRIPTION

Hereinafter, some embodiments of the present inventive concepts will be described in detail with reference to the accompanying drawings. The same reference numerals denote the same elements in the drawings, and the descriptions on the same elements are omitted.

While the term “same,” “equal” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).

FIG.1is a flowchart showing a method of manufacturing a semiconductor device S10, according to an example embodiment.FIGS.2A to2Iare views illustrating a method of manufacturing a semiconductor device, according to an example embodiment.FIGS.2A,2D, and2H are plan views.FIGS.2B,2C,2E,2F,2G, and2Ieach show a cross-sectional view taken along line A1-A1′ inFIG.2Aand a cross-sectional view taken along line A2-A2′ inFIG.2A.

Hereinafter, a method of manufacturing a semiconductor device is described in detail with reference toFIGS.1and2A to2I.

Referring toFIGS.1and2A, a first semiconductor substrate W1may be prepared (S111). The first semiconductor substrate W1may include, for example, a wafer. The first semiconductor substrate W1may include a plurality of chip areas CHP. Each of the chip areas CHP may be an area of the first semiconductor substrate W1, in which a plurality of circuit layouts for a semiconductor device overlaps each other, to provide a semiconductor chip. The plurality of chip areas CHP may be separated by a scribe lane SL extending in X and Y directions. InFIG.2A, reference number M1represents an area corresponding to a first field area F1inFIG.2Dexposed by single-shot exposure in a first exposing process, which is described hereinafter. The X direction and the Y direction may be in parallel with an upper surface of the first semiconductor substrate W1, and more particularly, the X direction and the Y direction may be perpendicular to each other.

In some example embodiments, a memory device may be formed in each of the plurality of chip areas CHP and the memory device may include a nonvolatile memory device and a volatile memory device. For example, the nonvolatile memory device may include NAND flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the volatile memory device may include DRAM and SRAM.

In some example embodiments, any one of a logic device, a measuring device, a communication device, a digital signal processor (DSP), and a system-on-chip (SOC) may be formed in each chip area CHP.

Referring toFIGS.1and2B, a first material layer LY1and a first photoresist (PR) layer PR1may be sequentially formed on the first semiconductor substrate W1(S113).

In operation S113, the first material layer LY1may include, for example, a metal. The first material layer LY1may cover the first semiconductor substrate W1. For example, the first material layer LY1may be formed by a plating process. Another material layer may be further positioned between the first semiconductor substrate W1and the first material layer LY1.

In operation S113, the first PR layer PR1may be formed by an adhesion promoting process and a spin coating process. The adhesion promoting process may include a process for bonding the first PR layer PR1to the first semiconductor substrate W1or a material layer provided on the first semiconductor substrate W1. The PR material may have a low adhesion with regard to the surface of silicon or silicon-containing material. Therefore, the adhesion promoting process may be performed on a surface of the first semiconductor substrate W1(or the surface of the material layer provided on the first semiconductor substrate W1) before the first PR layer PR1is formed on the first semiconductor substrate W1. For example, the adhesion promoting process may include surface treatment to the surface of the first semiconductor substrate W1with hexamethyldisilazane (HMDS). The HMDS may make the surface of the first semiconductor substrate W1hydrophobic, and thus, the adhesion may be reinforced between the PR material and the first semiconductor substrate W1.

The spin coating process may include a process of coating the PR material on the first semiconductor substrate W1. The PR material may include an organic polymer. Liquid PR material may be supplied onto the first semiconductor substrate W1and the first semiconductor substrate W1may be rotated at high speed, so that the first semiconductor substrate W1is coated with the PR material. A thickness of the first PR layer PR1may be uniform by the spin rotation of the first semiconductor substrate W1.

Referring toFIGS.1,2B, and2C, after forming the first PR layer PR1, an exposing process and a developing process may be sequentially performed on the first PR layer PR1, to thereby form a first PR pattern PP1(S115).

In operation S115, the first exposing process may be performed on the first field areas F1of the first PR layer PR1in a first exposing apparatus1inFIG.3. Each first field area F1is an area on which an image of the entire circuit pattern of a first photomask R1inFIG.3is transferred in the first exposing apparatus1. In the first exposing process, each first field area F1of the first PR layer PR1may be exposed by single-shot exposure. Each first field area F1may have the same field size in view of a length in the X direction and a length in the Y direction. The first field areas F1may be arranged on the first semiconductor substrate W1in the X direction and the Y direction. The first photomask may also be referred to as first reticle.

The circuit pattern of the first photomask may be transferred onto the plurality of first field areas F1of the first PR layer in the first exposing process by using a deep ultraviolet (DUV) radiation beam and/or a low numerical aperture (NA) extreme UV (EUV) radiation beam. Herein, the low numerical aperture (low NA) may include a numerical aperture less than about 0.35, and a high numerical aperture (high NA) described below may include a numerical aperture more than or equal to about 0.35. For example, the low numerical aperture may be about 0.33, and the high numerical aperture may be about 0.55.

In the first exposing process, the circuit pattern of the first photomask R1may be reduced to 1:1 or a certain reduction ratio and transferred to the first field areas F1of the first PR layer PR1. In some example embodiments, in the first exposing process, the X-direction reduction ratio between the X-direction length of the first photomask R1and the X-direction length of the first field area F1may be the same as or substantially similar to the Y-direction reduction ratio between the Y-direction length of the first photomask R1and the Y-direction length of the first field area F1. In some example embodiments, in the first exposing process, the X-direction reduction ratio and the Y-direction reduction ratio may be 1/N (N is a natural number)y. In some example embodiments, in the first exposing process, the X-direction reduction ratio and the Y-direction reduction ratio may be about 1/4.

In operation S115, after performing the first exposing process on the first PR layer PR1, the developing process may be performed on the first PR layer PR1. At least an exposed area of the first PR layer PR1may be removed by the developing process to the first PR layer PR1. The first PR pattern PP1may be formed from the first PR layer PR1by the developing process to the first PR layer PR1. The first PR pattern PP1may have a first overlay mark OM1.

Referring toFIGS.1,2C, and2D, after forming the first PR pattern PP1, an overlay may be measured, and an overlay correction model may be generated (S117).

The overlay measurement may include an operation of measuring an overlay error that indicates a deviation between a current layer, which is formed in the current operation, and a lower layer, which is formed in the previous operation, by using a measuring apparatus. Hereinafter, the overlay error is collectively referred to as overlay.

In some example embodiments, the first overlay mark OM1of the first PR pattern PP1may include an image-based overlay (IBO) mark. For example, the first overlay mark OM1of the first PR pattern PP1may have a box-in-box structure. The measuring apparatus may obtain images of the first semiconductor substrate W1by using an optical device or a camera and may measure the overlay by performing a signal processing for extracting the IBO marks from the obtained images.

In some example embodiments, the first overlay mark OM1of the first PR pattern PP1may include a diffraction-based overlay (DBO) mark. Incident light incident onto the DBO mark is diffracted from the DBO mark and the diffracted light may be detected, and then the overlay may be measured by performing a signal processing to the diffracted light.

The second to fourth overlay marks OM2, OM3, and OM4may include an IBO mark or a DBO mark, as described in detail hereinafter.

The overlay measurement for the first PR pattern PP1may be performed by using the first overlay mark OM1of the first PR pattern PP1. In some example embodiments, the overlay measurement for the first PR pattern PP1may include an operation of detecting the first overlay mark OM1of the first PR pattern PP1and another overlay mark of the lower layer under the first PR pattern PP1, and an operation of calculating the relative position between the first overlay mark OM1and the overlay mark of the lower layer. In some example embodiments, when the first PR pattern PP1is a lowermost layer, the overlay measurement for the first PR pattern PP1may include an operation of detecting the first overlay mark OM1of the first PR pattern PP1and a reference mark, and an operation of calculating the relative position between the first overlay mark OM1and the reference mark. The reference mark may be positioned on the first semiconductor substrate W1or positioned on a substrate stage on which the first semiconductor substrate W1is mounted.

The overlay measurement may include an operation of measuring an intra-field overlay for each of the first field areas F1of the first PR pattern PP1and an operation of measuring an inter-field overlay between the first field areas F1of the first PR pattern PP1.

In performing the overlay measurement, a field coordinate of each first field area F1may be defined as a distance between a reference point RP on the first semiconductor substrate W1and a center of the first field area F1. For example, the reference point RP may be set as a center of the first semiconductor substrate W1and may be indicated by (0,0). Thus, the field coordinate of the first field area F1may be indicated by (X, Y). In addition, the intra-field coordinate of each first field area F1may be defined as a distance from a center of the corresponding first field area F1. The intra-field coordinates for a specific point of each first field area F1may be expressed as (x, y). In addition, the inter-field overlay may indicate a deviation between the first field areas F1on the first semiconductor substrate W1, and the intra-field overlay may indicate a deviation within each first field area F1.

The intra-field overlay may be expressed as the intra-field coordinates of the first field area F1. The intra-field overlay may include a zero-degree component, a first-degree linear component, and a second or more degree non-linear component.

For example, the zero-degree component may include K1 and K2 components. The K1 component may include a parallel transition parameter in the X direction, and the K2 component may include a parallel transition parameter in the Y direction. The K1 component may be represented in the form of dx=K1 and the K2 component may be represented in the form of dy=K2. The zero-degree component may be included in a linear component.

The first-degree linear component may include K3 to K6 components. The K3 component may include an isotropic expansion parameter in the X direction, the K4 component may include an isotropic expansion parameter in the Y direction, the K5 component may include a rotation parameter with respect to the X direction, and the K6 component may include a rotation parameter with respect to the Y direction. The K3 component may be represented in the form of dx=K3*x, and the K4 component may be represented in the form of dy=K4*y. In addition, the K5 component may be represented as dx=K5*y, and the K6 component may be represented as dy=K6*x.

The second-degree nonlinear component may include K7 to K12 components. The K7 to K12 components may include parameters proportional to the square of the position. The K7 component may be represented in the form of dx=K7*x2, and the K8 component may be represented in the form of dy=K8*y2. In addition, the K9 component may be represented as dx=K9*x*y, the K10 component may be represented as dy=K10*y*x, the K11 component may be represented as dx=K11*y2, and the K12 component may be represented in the form of dy=K12*x2.

The third-degree nonlinear component may include K13 to K20 components. The K13 to K20 components may include parameters proportional to a cube of the position. The K13 component may be represented in the form of dx=K13*x3, and the K14 component may be represented in the form of dy=K14*y3. In addition, the K15 component may be represented as dx=K15*x2*y, the K16 component may be represented as dy=K16*y2*x, the K17 component may be represented as dx=K17*x*y2, the K18 component may be represented as dy=K18*y*x2, the K19 component may be represented as dx=K19*y3, and the K20 component may be represented as dy=K20*x3.

In operation S117, the overlay correction model may be generated based on the overlay measurement results. The generating of the overlay correction model may include an operation of generating an overlay correction function and an operation of determining a correction parameter based on a value of the overlay measurement and the overlay correction function (e.g., by comparing a value of the overlay measurement with the overlay correction function).

The overlay correction function may be generated by fitting a polynomial function based on the parameters of the intra-field overlay (e.g., K1 to K20). The overlay correction function may include an intra-field correction function FX related to X-axis components of the overlay and an intra-field correction function FY related to Y-axis components of the overlay. Each of the intra-field correction functions FX and FY may be represented as a polynomial function of which the highest degree is a third degree.

Based on the value of the overlay measurement and the overlay correction function (e.g., by comparing the value of the overlay measurement with the overlay correction function), contributions of the intra-field overlay parameters (e.g., K1 to K20) for the entire overlay may be detected. The value of the overlay measurement may include an average overlay, which is an average value of overlay values obtained from the first field areas F1of the first PR pattern PP1. The average overlay value at a specific coordinate may be an average of the overlay values measured at a specific coordinate of the first field areas F1. The comparing of the value of the overlay measurement with the overlay correction function (e.g., the detecting contributions of the intra-field overlay parameters (e.g., K1 to K20) for the entire overlay Based on the value of the overlay measurement and the overlay correction function) may include an operation of determining a residual, which is the difference between the value of the overlay measurement (or the average overlay value) and the overlay correction function, and operation of determining regression coefficients (e.g., intra-field overlay parameters), which minimize the sum of the squares of the above residuals or the sum of the above residuals, by using a regression analysis technique. The intra-field overlay parameters, which are determined in the previous process, may be fed back to the first exposing apparatus, to thereby correct the first exposing process. The operation S117may be performed by an advanced process controller or an advanced process controlling system. The advanced controller or an advanced process controlling system may perform various functions including functions not discussed herein and may include processing circuitry to implement the various functions. The advanced controller or an advanced process controlling system may operate based on instructions stored in a memory or may operate based on preprogrammed functions.

Referring toFIGS.1and2E, the first material layer LY1may be patterned by using the first PR pattern PP1inFIG.2Cas a mask, to form a first pattern layer LY1a, and the first PR pattern PP1may be removed from the first pattern layer LY1a(S119). In operation S119, an etching process may be performed on the first material layer LY1by using the first PR pattern PP1as an etching mask, to thereby form the first pattern layer LY1afrom the first material layer LY1. The first pattern layer LY1amay include a second overlay mark OM2. In addition, the first PR pattern PP1may be removed by a strip process.

Referring toFIGS.1and2F, after forming the first pattern layer LY1a, a first insulating layer IL1may be formed on the first pattern layer LY1ain such way that the first pattern layer LY1ais covered with the first insulating layer IL1, and then, a second material layer LY2may be formed on the first insulating layer (S121). The second material layer LY2may include, for example, metal. The second material layer LY2may be formed by, for example, a plating process. After forming the second material layer LY2, a second PR layer PR2may be formed on the second material layer LY2(S123). The operation of forming the second PR layer PR2may include an adhesion promoting process and a spin coating process.

Referring toFIGS.1,2F, and2G, after forming the second PR layer PR2, an exposing process and a developing process may be sequentially performed on the second PR layer PR2, to thereby form a second PR pattern PP2(S125).

In operation S125, a second exposing process may be performed on the second PR layer PR2in a second exposing apparatus2inFIG.4, and thus, first top field areas TF and first bottom field areas BF of the second PR layer PR2may be exposed by the second exposing apparatus2. The second exposing apparatus may be different from the first exposing apparatus1inFIG.3, which is used to perform the first exposing process on the first PR layer PR1. The first top field areas TF and the first bottom field areas BF may be exposed in different exposing steps in the second exposing apparatus. In the second exposing process, the first top field areas TF of the second PR layer PR2may be exposed by top single-shot exposure, and the first bottom field areas BF of the second PR layer PR2may be exposed by bottom single-shot exposure. Each first top field area TF is an area on which an image of the entire circuit pattern of a second photomask R2inFIG.4is transferred in the second exposing apparatus, and each first bottom field area BF is an area on which an image of the entire circuit pattern of a second photomask R2inFIG.4is transferred in the second exposing apparatus. The second photomask R2may be referred to as second reticle.

The first top field areas TF may be arranged in the X direction, the first bottom field areas BF may be arranged in the X direction, and each first top field area TF and a corresponding first bottom field area BF may be adjacent to each other in the Y direction. The first top field areas TF may be arranged along a first line in parallel with the X direction, the first bottom field areas BF may be arranged along a second line in parallel with the X direction, and the first line and the second line may be spaced apart in the Y direction.

Each of the first top field areas TF may vertically overlap a first portion of a corresponding first field area (F1ofFIG.2D), and each of the first bottom field areas BF may vertically overlap a second portion of the corresponding first field area F1. In each first field area F1, the first portion and the second portion may not overlap each other. The field size of each first top field area TF may be the same as that of each first bottom field area BF. That is, a length of each first top field area TF in the X direction may be the same as that of each first bottom field area BF in the X direction, and the length of each first top field area TF in the Y direction may be the same as that of each first bottom field area BF.

The second exposing process may include an EUV exposing process using an EUV radiation beam. The wavelength of light provided to the second photomask R2in the second exposing process may be smaller than that of light provided to the first photomask R1in the first exposing process. In some example embodiments, the first exposing process may be a process in which a low numerical aperture EUV radiation beam or a DUV radiation beam is used, and the second exposing process may be a process in which a high numerical aperture EUV radiation beam is used.

The EUV exposing process may be performed by a scanning method. The EUV exposing process may be performed by using a slit for limiting an irradiation area of the EUV radiation beam to a partial area of the second photomask R2. While the EUV radiation beam is irradiated to the limited partial area of the second photomask R2through the slit, the second photomask R2may move in a direction perpendicular to a longitudinal direction of the slit, so that the EUV radiation beam is continuously irradiated or scanned to the second photomask R2in the direction along which the second photomask R2moves. The longitudinal direction of the slit may be the X direction, and the scanning direction of the second photomask R2may be the Y direction.

In the second exposing process, the X-direction reduction ratio between the X-direction length of the second photomask R2and the X-direction length of the field area (e.g., the first top field area TF or the first bottom field area BF) may be different from the Y-direction reduction ratio between the Y-direction length of the second photomask R2and the Y-direction length of the field area (e.g., the first top field area TF or the first bottom field area BF). In some example embodiments, the Y-direction reduction ratio may be greater than the X-direction reduction ratio in the second exposing process. In some example embodiments, when the X-direction reduction ratio is 1/N (N is a natural number) and the Y-direction reduction ratio is 1/M (M is a natural number), M may be greater than N in the second exposing process. In some example embodiments, the X-direction reduction ratio may be 1/4 and the Y-direction reduction ratio may be 1/8 in the second exposing process. In some example embodiments, the second exposing process may be an anamorphic reduction projection in which the X-direction reduction ratio and the Y-direction reduction ratio are different.

In operation S125, after performing the second exposing process on the second PR layer PR2, the developing process may be performed on the second PR layer PR2. At least an exposed area of the second PR layer PR2may be removed by the developing process. The second PR layer PR2may be formed into the second PR pattern PP2by the developing process. The second PR pattern PP2may include a third overlay mark OM3.

Referring toFIGS.1,2G, and2H, after forming the second PR pattern PP2, an overlay may be measured, and an overlay correction model may be generated (S127).

In operation S127, the overlay measurement for the second PR pattern PP2may include an operation of detecting the third overlay mark OM3of the second PR pattern PP2and the second overlay mark OM2of the first pattern layer LY1aand an operation of calculating the relative position between the third overlay mark OM3of the second PR pattern PP2and the second overlay mark OM2of the first pattern layer LY1a.

The overlay measurement may include an operation of measuring a top intra-field overlay for each of the first top field areas TF of the second PR pattern PP2, an operation of measuring a bottom intra-field overlay for each of the first bottom field areas BF of the second PR pattern PP2, and an operation of measuring an inter-field overlay between the field areas of the second PR pattern PP2(e.g., the first top field areas TF and the first bottom field areas BF).

In performing the overlay measurement, the field coordinates of each first top field area TF may be represented as (TX, TY), and the field coordinates of each first bottom field area BF may be represented as (BX, BY). The intra-field coordinates of the first top field areas TF may be represented as (Tx, Ty) and the intra-field coordinates of the first bottom field areas BF may be represented as (Bx, By).

The top intra-field overlay may be expressed as the intra-field coordinates in the first top field area TF, and the bottom intra-field overlay may be expressed as the intra-field coordinates in the first bottom field area BF. Each of the top intra-field overlay and the bottom intra-field overlay may include a zero-degree component, a first-degree linear component, and a second or more-degree non-linear component. The top intra-field overlay may include TK1 to TK20 components, and the TK1 to TK20 components may be the same kinds of parameters as the K1 to K20 described above, respectively. The bottom intra-field overlay may include BK1 to BK20 components, and each of the BK1 to BK20 components may be the same kinds of parameters as the K1 to K20 described above, respectively.

In operation S127, the overlay correction model may be generated based on the overlay measurement results. The generation the overlay correction model may include an operation of generating a top intra-field correction function, an operation of generating a bottom intra-field correction function, an operation of determining a top intra-field correction parameter based on the measured top intra-field overlay and the top intra-field correction function (e.g., by comparing the measured top intra-field overlay with the top intra-field correction function), and an operation of determining a bottom intra-field correction parameter based on the measured bottom intra-field overlay and the bottom intra-field correction function (by comparing the measured bottom intra-field overlay with the bottom intra-field correction function).

The top intra-field correction function may be generated by fitting a polynomial function using the top intra-field overlay parameters (e.g., TK1 to TK20). The top intra-field correction function may include a first top intra-field correction function TFX related to the X-axis components of the overlay and a second top intra-field correction function TFY related to the Y-axis components of the overlay. The first and second top intra-field correction functions TFX and TFY each may be represented as a polynomial function in which the highest degree is a third degree.

Based on the top intra-field overlay and the top intra-field correction function (e.g., by comparing the top intra-field overlay with the top intra-field correction function), the contribution of the top intra-field overlay parameters (e.g., TK1 to TK20) for the entire top intra-field overlay may be detected. The measured top intra-field overlay may include an average overlay value, which is an average value of the overlay values obtained from the first top field areas TF of the second PR pattern PP2. The average overlay value at a specific coordinate may be an average of the overlay values measured at a specific coordinate of the first top field areas TF. The overlay values obtained from the first bottom field areas BF of the second PR pattern PP2may not be considered in generating the top intra-field correction function. The comparing of the measured top intra-field overlay with the top intra-field correction function (e.g., the detection of the contribution of the top intra-field overlay parameters for the entire top intra-field overlay based on the top intra-field overlay and the top intra-field correction function) may include an operation of determining a residual, which is the difference between the top intra-field overlay and the top intra-field correction function, and an operation of determining regression coefficients (e.g., the top intra-field overlay parameters), which minimize the sum of the squares of the above residuals or the sum of the above residuals, by using a regression analysis technique. The regression coefficient(s), which is determined by the regression analysis for the top intra-field correction function, is the top intra-field correction parameter(s) that is fed back to the second exposing apparatus.

The bottom intra-field correction function may be generated by fitting a polynomial function using the bottom intra-field overlay parameters (e.g., BK1 to BK20). The bottom intra-field correction function may include a first bottom intra-field correction function BFX related to the X-axis components of the overlay and a second bottom intra-field correction function BFY related to the Y-axis components of the overlay. The first and second bottom intra-field correction functions BFX and BFY may be represented as a polynomial function in which the highest degree is a third degree, respectively.

Based on the bottom intra-field overlay and the bottom intra-field correction function (e.g., by comparing the bottom intra-field overlay with the bottom intra-field correction function), the contribution of the bottom intra-field overlay parameters (e.g., BK1 to BK20) for the entire bottom intra-field overlay may be detected. The measured bottom intra-field overlay may include an average overlay value, which is an average value of overlay values obtained from the first bottom field areas BF of the second PR pattern PP2The average overlay value at a specific coordinate may be an average of overlay values measured at a specific coordinate of the first bottom field areas BF. The overlay values obtained from the first top field areas TF of the second PR pattern PP2may not be considered in generating the bottom intra-field correction function. The comparing of the measured bottom intra-field overlay with the bottom intra-field correction function (e.g., the detection of the contribution of the bottom intra-field overlay parameters for the entire bottom intra-field overlay based on the bottom intra-field overlay and the bottom intra-field correction function) may include an operation of determining a residual, which is the difference between the bottom intra-field overlay and the bottom intra-field correction function, and an operation of determining regression coefficients (e.g., the bottom intra-field overlay parameters), which minimize the sum of the squares of the above residuals or the sum of the above residuals, by using a regression analysis technique. The regression coefficient(s), which is determined by the regression analysis for the bottom intra-field correction function, is the bottom intra-field correction parameter(s) that is fed back to the second exposing apparatus.

The operation S127may be performed by an advanced process controller or an advanced process controlling system. The advanced controller or an advanced process controlling system may perform various functions including functions not discussed herein and may include processing circuitry to implement the various functions. The advanced controller or an advanced process controlling system may operate based on instructions stored in a memory or may operate based on preprogrammed functions.

The top intra-field correction parameters and the bottom intra-field correction parameters, which are determined in operation S127, may be fed back to the second exposing apparatus (S129). The second exposing apparatus2may perform another exposing process on the first semiconductor substrate W1or another semiconductor substrate based on the top intra-field correction parameters and the bottom intra-field correction parameters.

Referring toFIGS.1and2G, the second PR pattern PP2may be inspected, and it is determined whether to rework the second PR pattern PP2based on the inspection results (S131). For example, the dimensions of the features in the second PR pattern PP2, the consistency between the second PR pattern PP2and the lower layer, and defects of the second PR pattern PP2may be inspected when inspecting the second PR pattern PP2.

In operation S131, when the rework of the second PR pattern PP2is not desired, the second material layer LY2inFIG.2Gmay be patterned into a second pattern layer LY2ainFIG.2I, and then, the second PR pattern PP2may be removed (S133). In operation S133, the second pattern layer LY2amay be formed from the second material layer LY2by an etching process using the second PR pattern PP2as an etching mask. Thereafter, the second PR pattern PP2may be removed by a strip process.

Otherwise, in operation131, when the rework of the second PR pattern PP2is desired, the second PR pattern PP2may be removed (S135).

After removing the second PR pattern PP2, a third PR pattern may be formed on the second material layer LY2(S140). The forming of the third PR pattern may include an operation of forming a third PR layer on the second material layer LY2the same as or substantially similar to operation S123, an operation of performing an exposing process and a developing process on the third PR layer the same as or substantially similar to operation S125, and an operation of performing overlay measurement the same as or substantially similar to operation S127.

A third exposing process for the third PR pattern may be performed by the second exposing apparatus. In the third exposing process, each of the second top field areas of the third PR layer may be exposed by top single-shot exposure, and each of the second bottom field areas of the third PR layer may be exposed by bottom single-shot exposure. Each second top field area of the third PR layer may overlap a corresponding first top field area TF among the first top field areas TF of the second PR layer PR2, and each second bottom field area overlap a corresponding first bottom field area BF among first bottom field areas BF of the second PR layer PR2.

In the third exposing process, the second exposing apparatus may perform the third exposing process on the third PR layer based on the top intra-field correction parameter and the bottom intra-field correction parameter that are determined in operation S127. The third exposing process may include checking the target positions of target exposing areas of the third PR layer and performing the top single-shot exposure or the bottom single-shot exposure according to the checked target positions. That is, when the checked position of the target exposing area of the third PR layer is in the second top field area of the third PR layer, the second exposing apparatus may perform the top single-shot exposure on the second top field area of the third PR layer based on the top intra-field correction parameter, which is determined in operation S127, in the second exposing apparatus. When the checked position of the target exposing area of the third PR layer is in the second bottom field area of the third PR layer, the second exposing apparatus may perform the bottom single-shot exposure on the second bottom field area of the third PR layer based on the bottom intra-field correction parameter, which is determined in operation S127, in the second exposing apparatus.

In some example embodiments, when the semiconductor device is manufactured on a second semiconductor substrate different from the first semiconductor substrate, an exposing process may be performed on a material layer on the second semiconductor substrate based on the top intra-field correction parameter and the bottom intra-field correction parameter, which are determined in operation S127, in the second exposing apparatus. The method of manufacturing a semiconductor device on the second semiconductor substrate may be the same as or substantially similar to the method of manufacturing a semiconductor device S10on the first semiconductor substrate W1. For example, the method of manufacturing a semiconductor device on the second semiconductor substrate may include an operation of sequentially forming a third material layer and a fourth PR layer on the second semiconductor substrate, an operation of forming a fourth PR pattern by performing an exposing process and a developing process on the fourth PR layer, an operation of forming a third pattern layer by patterning the third material layer using the fourth PR pattern as an etching mask, an operation of removing the fourth PR pattern, an operation of forming a fourth material layer and a fifth PR layer on the third pattern layer, an operation of forming a fifth PR pattern by performing an exposing process and a developing process on the fifth PR layer, and an operation of forming a fourth pattern layer by patterning the fourth material layer using the fifth PR pattern as an etching mask. The exposing process on the third PR layer may be performed by the first exposing apparatus, and the exposing process on the fourth PR layer may be performed by the second exposing apparatus.

In the fourth exposing process on the fourth PR layer, the fourth PR layer may be exposed based on the top intra-field correction parameter and the bottom intra-field correction parameter that are determined in operation S127in the second exposing apparatus. The fourth exposing process may include checking the target positions of target exposing areas of the fourth PR layer and performing the top single-shot exposure or the bottom single-shot exposure according to the checked target positions. That is, when the checked position of the target exposing area of the fourth PR layer is in a third top field area of the fourth PR layer, the second exposing apparatus may perform the top single-shot exposure on the third top field area of the fourth PR layer based on the top intra-field correction parameter, which is determined in operation S127, in the second exposing apparatus. When the checked position of the target exposing area of the fourth PR layer is in a third bottom field area of the fourth PR layer, the second exposing apparatus may perform the bottom single-shot exposure on the third bottom field area of the fourth PR layer based on the bottom intra-field correction parameter, which is determined in operation S127, in the second exposing apparatus.

FIG.3is a view illustrating a first exposing apparatus1, according to an example embodiment.

Referring toFIG.3, the first exposing apparatus1may include a light source110, a transmission optical system130, a projection optical system170, and a control unit (or alternatively, controller or processor)190. The light source110may include, for example, a laser source for generating a laser having a central wavelength of about 150 nm to 500 nm. The light source110may include an excimer laser source for generating a KrF laser or an ArF laser. For example, the light source110may generate an ArF laser having a central wavelength of about 193 nm.

The transmission optical system130may transmit a first light L1generated from the light source110to the first photomask R1. The transmission optical system130may include a plurality of optical elements131for guiding the first light L1to the first photomask R1and the optical elements131may include lenses and mirrors.

The first photomask R1may be provided on the mask stage150. The first photomask R1may include, for example, a transmissive mask. Although not shown inFIG.3, the first photomask R1may be supported on the mask stage150by, for example, three clamps, and the three clamps may be positioned at an edge portion of the first photomask R1. The mask stage150may include a material through which the first light L1generated from the light source110may transmit.

The projection optical system170may focus the first light L1, which passes through the mask stage150and the first photomask R1, on an area of the substrate W. The projection optical system170may include, for example, a plurality of focusing lenses. The focusing lenses of the projection optical system170may reduce the first light L1, which has passed through the first photomask R1, at a certain magnification ratio (e.g., 4 times, 6 times, or 8 times), and the reduced first light L1may be projected onto the substrate W.

A substrate W may be provided on the substrate stage180. The substrate W may include a wafer on which an integrated circuit is formed The substrate W may be a semiconductor wafer including at least one of silicon, germanium, or silicon-germanium or a compound semiconductor wafer. An upper surface of the substrate W may be coated with a PR material that is sensitive to the first light L1, so that the PR layer may be formed on the substrate W.

The PR layer may be exposed to the first light L1and a developing process may be performed on the exposed PR layer, to thereby form a PR pattern on the substrate W. A material layer under the PR pattern may be patterned by an etching process using the PR pattern as an etching mask, to thereby form a pattern layer from the material layer.

The control unit190may be connected to the light source110, the mask stage150, and the substrate stage180, and may control the light source110, the mask stage150, and the substrate stage180. For example, the control unit190may control driving motors coupled to the mask stage150and the substrate stage180, respectively. The mask stage150and the substrate stage180may move in the X direction and/or the Y direction by the driving motor. The X direction may include a direction in which a slit for defining a target exposing area extends, and the Y direction may include a scan direction. In addition, the mask stage150and the substrate stage180may be rotated clockwise or counterclockwise by the driving motor. The control unit190may perform various functions including functions not discussed herein and may include processing circuitry to implement the various functions. The control unit190may operate based on instructions stored in a memory or may operate based on preprogrammed functions.

FIG.4is a view illustrating a second exposing apparatus2, according to an example embodiment.

Referring toFIG.4, the second exposing apparatus2may include a light source210, a transmission optical system230, a projection optical system270and a control unit (or alternatively, controller or processor)290. The light source210may include, for example, a beam source for generating a beam having a central wavelength of about 4 nm to about 120 nm, and for example, of about 4 nm to about 20 nm. For example, the light source210may generate an extreme ultra-violet (EUV) beam having a central wavelength of about 13.5 nm. A second light L2generated from the light source210may have an energy of about 6.21 eV to about 124 eV, and more particularly, about 90 eV to about 95 eV.

The light source210of the second exposing apparatus2may include, for example, a plasma source using laser produced plasma (LPP). Although not shown inFIG.4, the light source210of the second exposing apparatus2may include a vacuum chamber having a seed laser for emitting a pulse laser, at least a power amplifier for amplifying the laser, a target generator for generating targets at regular intervals, and a target collector for collecting targets.

The target may include a material that emits extreme ultraviolet light when the material such as tin (Sn), lithium (Li), or xenon (Xe) is converted into plasma. When including tin (Sn), the targets may include pure tin (Sn), a tin compound (e.g., SnBr4, SnBr2, SnH4, etc.), and a tin alloy (e.g., a tin-gallium alloy, a tin-indium alloy, a tin-indium-gallium alloy, etc.). The targets may be in the form of, for example, droplets, streams, or clusters.

The pulse laser, which is emitted from the seed laser and passes through the power amplifier, may be irradiated to the targets moving from the target generator to the target collector, and thus, the targets may be converted into plasma by the pulse laser and the extreme ultraviolet light (e.g., second light L2) may be emitted from the targets.

The transmission optical system230may transmit the second light L2generated from the light source210to the second photomask R2. The transmission optical system230may include a plurality of optical elements231for guiding the second light L2to the second photomask R2, and the optical elements231may be lenses or mirrors. The optical elements231of the transmission optical system230may guide the second light L2to be obliquely incident on the second photomask R2.

The second photomask R2may be provided on the mask stage250. The second photomask R2may be, for example, a reflective mask. Although not shown inFIG.4, the second photomask R2may be supported on the mask stage250by, for example, a plurality of clamps, and the plurality of clamps may be positioned on an entire rear surface of the second photomask R2at regular intervals. The mask stage250may include a material reflecting the second light L2generated from the light source210.

The projection optical system270may transmit the second light L2, which is reflected from the mask stage250and the second photomask R2, to an area of the substrate W. The projection optical system270may include a plurality of optical elements271for guiding the second light L2to an area of the substrate W, and the optical elements271may be lenses or mirrors. The optical elements271of the projection optical system270may reduce the second light L2, which is reflected from the second photomask R2, to a certain magnification ratio (e.g., 4 times, 6 times, or 8 times) and the reduced second light L1may be projected onto the substrate W.

The substrate W may be provided on the substrate stage280. The substrate stage280may support the substrate W. An upper surface of the substrate W may be coated with a PR material that is sensitive to the second light L2, so that the PR layer may be formed on the substrate W.

The PR material, which is sensitive to the second light L2such as an EUV light having a central wavelength of about 13.5 nm, may include an organic PR material having an organic polymer such as polyhydroxystyrene. The organic PR material may further include a photosensitive compound reacting with the second light L2. The organic PR material may further include a material having a high absorption rate for the second light L2, such as an organometallic material, an iodine-containing material, and a fluorine-containing material. In another example embodiment, the PR material may include an inorganic PR material having an inorganic material such as tin oxide.

The PR material may be formed on the substrate W with a relatively thin thickness. A developing process may be performed on the PR layer exposed to the second light L2, to thereby form a PR pattern. From a plan view, the PR pattern may include a line shape extending in a direction, an island shape, a zigzag shape, a honeycomb shape, and/or a circle shape, but the present inventive concepts are not limited thereto.

A material layer under the PR pattern may be patterned by an etching process using the PR pattern as an etching mask, to thereby pattern the material layer. In contrast, the material layer under the mask pattern may also be patterned by an etching process using the mask pattern as an etching mask, to thereby form a pattern layer patterned from the material layer. For example, a minimal pitch of the pattern layer, which is formed by the second exposing apparatus2, may be about 45 nm or less.

The control unit290may be connected to the light source210, the mask stage250, and the substrate stage280, and may control the light source210, the mask stage250, and the substrate stage280. For example, the control unit290may control driving motors coupled to the mask stage250and the substrate stage280, respectively. The mask stage250and the substrate stage280may move in the X direction and/or the Y direction by the driving motor. In addition, the mask stage250and the substrate stage280may be rotated clockwise or counterclockwise by the driving motor. In some example embodiments, the control unit290may control the light source210, the mask stage250, and/or the substrate stage280based on the top intra-field correction parameter and the bottom intra-field correction parameter that are determined in operation S127inFIG.1. The control unit190may perform various functions including functions not discussed herein and may include processing circuitry to implement the various functions. The control unit190may operate based on instructions stored in a memory or may operate based on preprogrammed functions.

FIG.5is a flowchart showing a method of manufacturing a semiconductor device S20, according to an example embodiment. Hereinafter, the method of manufacturing a semiconductor device S20is described with reference toFIG.5focusing on differences from the method of semiconductor device S10described in detail with reference toFIGS.1to4, and the same descriptions as the method of manufacturing a semiconductor device S10are omitted.

Referring toFIG.5, operations S111to S125may be the same as or substantially similar to those described with reference toFIG.1.

Referring toFIG.5together withFIGS.2G and2I, after forming the second PR pattern PP2in operation S125, the second material layer LY2may be patterned by an etching process using the second PR pattern PP2as an etching mask, to thereby form the second pattern layer LY2a, and then, the second PR pattern PP2may be removed (S151).

After forming the second pattern layer LY2a, an overlay is measured, and an overlay correction model is generated (S153).

In operation S153, the overlay measurement may include an operation of detecting the fourth overlay mark OM4of the second pattern layer LY2aand the second overlay mark OM2of the first pattern layer LY1a, and an operation of calculating the relative position between the fourth overlay mark OM4of the second pattern layer LY2aand the second overlay mark OM2of the first pattern layer LY1a. The overlay measurement may include an operation of measuring the top intra-field overlay in the top field area of the second pattern layer LY2a, which is an area overlapping with the first top field area TF inFIG.2Hof the second PR layer PR2or overlapping with the first portion of the first field area F1inFIG.2Dof the first PR layer PR1, and an operation of measuring the bottom intra-field overlay in the bottom field area of the second pattern layer LY2a, which is an area overlapping with the first bottom field area BF inFIG.2Hof the second PR layer PR2or the second portion of the first field area F1inFIG.2Dof the first PR layer PR1. The overlay measurement for the second pattern layer LY2amay be the same as or substantially similar to the overlay measurement described in operation S127inFIG.1, except that the overlay measurement is performed by using the fourth overlay mark OM4of the second pattern layer LY2ainstead of the third overlay mark OM3of the second PR pattern PP2.

In operation S153, an overlay correction model may be determined based on the overlay measurement results. The generating of the overlay correction model may include an operation of generating a top intra-field correction function, an operation of generating a bottom intra-field correction function, an operation of determining a top intra-field correction parameter based on the measured top intra-field overlay and the top intra-field correction function that are measured in the top field areas of the second pattern layer (e.g., by comparing the measured top intra-field overlay with the top intra-field correction function, and an operation of determining a bottom intra-field correction parameter based on the measured bottom intra-field overlay and the bottom intra-field correction function that are measured in the bottom field areas of the second pattern layer (e.g., by comparing the measured bottom intra-field overlay with the bottom intra-field correction function).

The top intra-field correction function may be generated by fitting a polynomial function using the overlay parameters and may be the same as or substantially similar to the first and second top intra-field correction functions TFX and TFY described in detail in operation S127. The top intra-field correction parameter may be determined based on the top intra-field overlay and the top intra-field correction function (e.g., by comparing the top intra-field overlay with the top intra-field correction function). The bottom intra-field correction function may be generated by fitting a polynomial function using the overlay parameters and may be the same as or substantially similar to the first and second bottom intra-field correction function BFX and BFY described in detail in operation S127. The bottom intra-field correction parameter may be determined based on the bottom intra-field overlay and the bottom intra-field correction function (e.g., by comparing the bottom intra-field overlay with the bottom intra-field correction function). The determining of the overlay correction model in operation S153may be the same as or substantially similar to the determining of the overlay correction model in operation S127inFIG.1, so that any detailed descriptions on operation S153are omitted herein.

The top intra-field correction parameter and the bottom intra-field correction parameter, which are determined in operation S153, may be fed back to the second exposing apparatus (S129). Another exposing process may be performed on a material layer on another semiconductor substrate in the second exposing apparatus based on the fed-back top intra-field correction parameters and bottom intra-field correction parameters.

Next, an inspection process may be performed on the second pattern layer LY2ato determine whether the specifications of the second pattern layer LY2asatisfy target specifications based on the inspection results (S155). For example, the dimensions of the features in the second pattern layer LY2a, the consistency between the second pattern layer LY2aand the lower layer, and defects of the second pattern layer LY2amay be inspected when inspecting the second pattern layer LY2a. In operation S155, when the specifications of the second pattern layer LY2asatisfy the target specifications, a subsequent process may be performed on the first semiconductor substrate W1(S157). In contrast, in operation S155, when the specifications of the second pattern layer LY2ado not satisfy the target specifications, the first semiconductor substrate W1may be discarded (S159).

FIG.6is a view illustrating a process of processing overlay data in a method of manufacturing a semiconductor device, according to a comparative example.FIG.7is a view illustrating a process of processing overlay data in a method of manufacturing a semiconductor device, according to an example embodiment.

FIGS.6and7shows that the overlay measurement is performed in a structure including a lower layer, which is formed by the first exposing process in the first exposing apparatus, and an upper layer, which is formed by the second exposing process in the second exposing apparatus, and how the top intra-field correction parameter and the bottom intra-field correction parameter, which are fed back to the second exposing apparatus, are determined based on the overlay measurement results. The first exposing process for the lower layer may be performed by using, for example, a DUV radiation beam or a low numerical aperture EUV beam, and the field areas of the lower layer may be exposed by a single exposing step. The second exposing process for the upper layer may be performed by using a high numerical aperture EUV beam, and the top field areas and the bottom field areas of the upper layer may be exposed by a single exposing step, respectively. InFIGS.6and7, the starting point of the arrow may correspond to the coordinates of the corresponding field area, and the size and direction of the arrow may indicate the size and direction of the overlay, respectively. A case that a K5 type overlay occurs in each field area of the bottom layer is shown inFIGS.6and7.

Referring toFIG.6, reference number511denotes data for the top intra-field overlay that is measured in the top field areas of the upper layer, and reference number513denotes data for the bottom intra-field overlay that is measured in the bottom field areas of the upper layer. The data511for the top intra-field overlay may include an average overlay value, which is an average of the overlay values measured in the top field areas, and the data513for the bottom intra-field overlay may include an average overlay value, which is an average of the overlay values measured in the bottom field areas.

Reference number521denotes data for the intra-field correction parameters determined by the overlay correction model for the method of manufacturing a semiconductor device according to the comparative example. Reference number531denotes data for the difference between the top intra-field overlay and the intra-field correction parameter, and reference number533denotes data for the difference between the bottom intra-field overlay and the intra-field correction parameter.

In the method of manufacturing a semiconductor device according to a comparative example, the overlay correction model is generated without distinguishing the top field area and the bottom field area. In generating the overlay correction model, the top intra-field overlay and the bottom intra-field overlay may be integrated to an integrated overlay and the intra-field overlay, which is to be fed back to the exposing apparatus, may be determined based on the integrated overlay and the overlay correction function (e.g., by comparing the integrated overlay with the overlay correction function). As shown inFIG.6, when the intra-field correction parameter is determined based on the integrated overlay, the overlay is not sufficiently corrected in both of the top field area and the bottom field area, as is verified by the data531for the difference between the top intra-field overlay and the intra-field correction parameter and the data533for the difference between the bottom intra-field overlay and the intra-field correction parameter.

Referring toFIG.7, reference number511denotes data for the top intra-field overlay measured in the top field areas of the upper layer, and reference number513denotes data for the bottom intra-field overlay measured in the bottom field areas of the upper layer. The data511for the top intra-field overlay may include an average overlay value, which is the average of the overlay values measured in the top field areas, and the data513for the bottom intra-field overlay may include the average overlay value, which is the average overlay value measured in the bottom field areas. Reference number541denotes data for the top intra-field correction parameter determined by the overlay correction model according to an example embodiment, reference number543denotes data for the bottom intra-field correction parameter determined by the overlay correction model according to an example embodiment, reference number551represents the difference between the top intra-field overlay and the top intra-field correction parameter, and reference number553represents the difference between the bottom intra-field overlay and the bottom intra-field correction parameter.

According to an example embodiment, in generating the overlay correction model, the top intra-field overlay measured in the top field area and the bottom intra-field overlay measured in the bottom field area may be processed independently from each other. That is, the top intra-field correction parameter may be determined based on the top intra-field overlay, and the bottom intra-field correction parameter may be determined based on the bottom intra-field overlay. In this case, the overlay may be sufficiently corrected in both the top field area and the bottom field area, as is verified by the data551for the difference between the top intra-field overlay and the top intra-field correction parameter and the data553for the difference between the bottom intra-field overlay and the bottom intra-field correction parameter.

As described with reference toFIGS.6and7, the K5 type overlay may be sufficiently corrected as described in the example embodiments above. Furthermore, when K4, K5, K8, K9, K10, K11, K14, K15, K16, K17, K18 or K19 type overlay occurs on the lower layer, both of the overlay in the top field area and the overlay in the bottom field area may be sufficiently corrected methods of manufacturing a semiconductor device according some example embodiments, whereas both of the overlay in the top field area and the overlay in the bottom field area may not be sufficiently corrected according to the comparative example method of manufacturing a semiconductor device.

Recently, a circuit width of the semiconductor device has become fine and minute and the circuit width may be different in each layer of the semiconductor devices. Accordingly, various circuit patterns having different circuit widths may be formed in various layers of the semiconductor device by a combination of different exposing apparatuses, for example, a combination of a DUV exposing apparatus and an EUV exposing apparatus. However, the DUV exposing apparatus and the EUV exposing apparatus are generally different from the points of the substrate stage, the reticle, the slit, and the optical system as well as the wavelength of light. There have been difficulties in correcting the overlay due to the differences between the DUV exposing apparatus and the EUV exposing apparatus.

However, according to some example embodiments of the present inventive concepts, when the overlay correction is performed on the upper layer that is formed by a high numerical aperture EUV exposing process, the top intra-field overlay and the bottom intra-field overlay may be processed independently from each other, and a subsequent exposing process may be corrected by feeding back the top intra-field correction parameter, which is generated based on the top intra-field overlay, and the bottom intra-field correction parameter, which is generated based on the bottom intra-field overlay, to the exposing apparatus, to thereby improve reliability of the exposing process and reliability of the semiconductor device manufactured by the exposing process.