Semiconductor device, memory device, electronic device, and method for driving semiconductor device

A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

2. Description of the Related Art

Patent Document 1 describes a memory device that includes a transistor using an oxide semiconductor and a transistor using single crystal silicon. According to Patent Document 1, the transistor using an oxide semiconductor has an extremely low off-state current.

REFERENCE

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide a novel semiconductor device or a novel memory device. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device capable of storing multi-level data. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device or a memory device with a reduced area. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device or a highly reliable memory device.

One embodiment of the present invention does not necessarily achieve all the objects listed above and only needs to achieve at least one of the objects. The descriptions of the above objects do not disturb the existence of other objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

A semiconductor device according to one embodiment of the present invention includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring. The second wiring has a function of transmitting a first potential based on data to be written to the memory cell. The semiconductor device has a function of performing a first operation of supplying a predetermined potential to the one of the electrodes of the capacitor by turning on the first transistor and has a function of performing a second operation of setting the potential of the one of the electrodes of the capacitor to a third potential based on the first potential by turning off the first transistor after the first operation and by changing the potential of the second wiring from the first potential to a second potential.

In the semiconductor device according to one embodiment of the present invention, one of a source and a drain of the second transistor may be electrically connected to a third wiring, and the semiconductor device may have a function of performing a third operation of setting the potential of the first wiring to a fourth potential based on the third potential and setting the potential of the third wiring to a potential based on the fourth potential by turning on the first transistor.

In the semiconductor device according to one embodiment of the present invention, the data to be written to the memory cell may be two or more bits of data, and the semiconductor device may have a function of sequentially changing the potential of the second wiring in reading the data.

In the semiconductor device according to one embodiment of the present invention, the memory cell may be stacked over the second transistor.

In the semiconductor device according to one embodiment of the present invention, the capacitance of the capacitor may be larger than a parasitic capacitance added to the first wiring.

A memory device according to one embodiment of the present invention includes the above-described semiconductor device.

An electronic device according to one embodiment of the present invention includes the above-described semiconductor device or the above-described memory device and a display portion, a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a novel semiconductor device or a novel memory device can be provided. According to another embodiment of the present invention, a semiconductor device or a memory device capable of storing multi-level data can be provided. According to another embodiment of the present invention, a semiconductor device or a memory device with low power consumption can be provided. According to another embodiment of the present invention, a semiconductor device or a memory device with a reduced area can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device or a highly reliable memory device can be provided.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the description in the following embodiments, and it will be easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments.

One embodiment of the present invention includes, in its category, devices such as a semiconductor device, a memory device, a radio frequency (RF) tag, a display device, an imaging device, and an integrated circuit. In addition, the display device includes, in its category, display devices including integrated circuits, such as liquid crystal display devices, light-emitting devices in which a light-emitting element typified by an organic light-emitting element is provided in each pixel, electronic paper, digital micromirror devices (DMDs), plasma display panels (PDPs), and field emission displays (FEDs).

Note that, in the description of modes of the invention with reference to the drawings, the same components in different diagrams are commonly denoted by the same reference numeral.

In this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without limitation to a predetermined connection relation, for example, a connection relation shown in drawings or text, another connection relation is included in the drawings or the text. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

For example, in the case where X and Y are directly connected, X and Y are connected without an element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) interposed between X and Y.

Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit provided therebetween). That is, in this specification and the like, the explicit expression “X and Y are electrically connected” is the same as the explicit simple expression “X and Y are connected.”

In this embodiment, a configuration example of a semiconductor device of one embodiment of the present invention will be described.

FIG. 1illustrates a configuration example of a semiconductor device10of one embodiment of the present invention. The semiconductor device10includes a cell array20, a control circuit30, and a read circuit40.

The cell array20includes a plurality of memory cells21. InFIG. 1, the cell array20includes memory cells21(memory cells21[1,1] to21[n,m]) arranged in n rows and m columns (n and m are natural numbers). Since the cell array20includes the memory cells21, the semiconductor device10can be used as a memory device.

Each of the memory cells21is a circuit having a function of storing data. The memory cell21is preferably configured to be capable of storing two or more bits of data (multi-level data), in which case the area per bit of the semiconductor device10can be reduced.

Each of the memory cells21is connected to a wiring WL, a wiring BL, and a wiring CL. The wiring WL has a function of transmitting a signal for selecting memory cells21in a predetermined row (this signal is hereinafter also referred to as a selection signal). The wiring BL has a function of transmitting a potential to be supplied to the memory cell21during a write operation and also has a function of transmitting a potential corresponding to data stored in the memory cell21(this potential is hereinafter also referred to as a read potential) during a read operation. The wiring CL has a function of transmitting a signal for controlling data writing to the memory cell21(this signal is hereinafter also referred to as a write control signal) and a signal for controlling data reading from the memory cell21(this signal is hereinafter also referred to as a read control signal).

FIG. 2illustrates a specific configuration example of the memory cell21. The memory cell21includes a transistor101and a capacitor102. A gate of the transistor101is connected to the wiring WL, one of a source and a drain of the transistor101is connected to one of electrodes of the capacitor102, and the other of the source and the drain of the transistor101is connected to the wiring BL. The other of the electrodes of the capacitor102is connected to the wiring CL. Here, a node which is connected to the one of the source and the drain of the transistor101and the one of the electrodes of the capacitor102is referred to as a node SN.

A predetermined potential is supplied to the node SN from the wiring BL through the transistor101. When the transistor101is in an off state, the node SN is in a floating state and thus the potential of the node SN is retained. Thus, the memory cell21can store data. Note that whether the transistor101is turned on or off can be controlled by a potential supplied to the wiring WL.

A transistor containing an oxide semiconductor in a channel formation region (this transistor is hereinafter also referred to as an OS transistor) is preferably used as the transistor101. An oxide semiconductor has a wider band gap and a lower carrier density than other semiconductors such as silicon. Thus, the off-state current of the OS transistor is extremely low. Therefore, when the OS transistor is used as the transistor101, a potential can be retained at the node SN for a long period. Thus, operation in which another writing is performed at predetermined intervals (refresh operation) is unnecessary or the frequency of the refresh operation can be extremely low. Moreover, even in a period in which the power supply to the memory cell21is stopped, data can be retained for a long period. Thus, power consumption of the semiconductor device10can be reduced. A case where an n-channel OS transistor is used as the transistor101is specifically described here.

One of i potentials (i is a natural number of 2 or more) can be retained at the node SN. Note that the value i can be freely set. For example, the potential retained at the node SN may be one of two (high- and low-level) potentials (i=2) or one of three or more potentials (i≧3). In the case where i≧3, the memory cell21stores multi-level data. For example, in the case where i=4, the memory cell21can store 2-bit data.

In the case where one of three or more potentials is retained at the node SN, the differences between the potentials to be retained are narrower than in the case where one of two potentials is retained. Therefore, even slight leakage of charge from the node SN might cause a change in data stored in the memory cell21. However, since the off-state current of an OS transistor is extremely low, leakage of charge from the node SN can be significantly suppressed, and one of three or more potentials can be accurately retained at the node SN. Therefore, the transistor101is preferably an OS transistor particularly in the case where one of three or more potentials is to be retained at the node SN.

In addition, the OS transistor has a higher withstand voltage than a transistor whose channel formation region contains silicon (the transistor is hereinafter also referred to as a Si transistor). Therefore, when the transistor101is the OS transistor, the range of potentials to be retained at the node SN can be widened. Accordingly, the number of potentials to be retained at the node SN can be increased, and the amount of data to be stored in the memory cell21can be increased. Alternatively, the differences between potentials can be widened, and multi-level data can be accurately stored.

The control circuit30illustrated inFIG. 1has a function of controlling the potential of the wiring BL. Specifically, the control circuit30includes a plurality of circuits31(circuits31[1] to31[m]), each of which has a function of supplying a predetermined potential to the wiring BL and a function of keeping the wiring BL in a floating state. Each wiring BL is provided with one circuit31; accordingly, the potential of each wiring BL can be controlled individually.

The read circuit40has a function of reading data stored in the memory cells21. Specifically, the read circuit40includes a plurality of circuits41(circuits41[1] to41[m]), each of which has a function of outputting a predetermined potential to a wiring RL in accordance with the potential of the wiring BL. Each wiring BL is provided with one circuit41; accordingly, data can be read from the memory cells21row by row.

Although the configurations of the circuits31and41are not particularly limited, the circuits31and41can be formed with transistors or the like.FIG. 2illustrates a specific configuration example of the circuits31and41.

The circuit31includes a transistor110. A gate of the transistor110is connected to a wiring WEB. One of a source and a drain of the transistor110is connected to the wiring BL. The other of the source and the drain of the transistor110is connected to a wiring VL. The wiring WEB has a function of transmitting a signal for supplying a predetermined potential to the wiring BL. The wiring VL is supplied with a constant potential. Note that the transistor110is a p-channel transistor and the wiring VL is supplied with a high power supply potential VDDin the example described here; however, the configuration of the circuit31is not limited thereto. The circuits31may be provided with respective wirings VL or may share one wiring with each other.

When the wiring WEB is set at a low-level potential and the transistor110is turned on, the high power supply potential VDDis supplied to the wiring BL from the wiring VL through the transistor110and the wiring BL is set at a high-level potential. When the wiring WEB is set at a high-level potential and the transistor110is turned off, the wiring BL is brought into a floating state.

The circuit41includes a transistor120. A gate of the transistor120is connected to the wiring BL. One of a source and a drain of the transistor120is connected to the wiring RL. The other of the source and the drain of the transistor120is connected to a wiring RSL. The wiring RL has a function of transmitting a potential corresponding to data stored in the memory cell21. The wiring RSL is supplied with a constant potential. Note that the transistor120is an n-channel transistor and the wiring RSL is supplied with a low power supply potential Vss (e.g., a ground potential) in the example described here; however, the configuration of the circuit41is not limited thereto. The circuits41may be provided with respective wirings RSL or may share one wiring with each other.

A read potential is output to the wiring BL in a state where the wiring RL is precharged to a high-level potential. Then, whether the transistor120is turned on or off is controlled in accordance with the potential of the wiring BL, and the potential of the wiring RL is determined. Specifically, in the case where a voltage between the wiring BL and the wiring RSL is higher than or equal to the threshold voltage of the transistor120, the transistor120is turned on and the low power supply potential Vss is supplied to the wiring RL from the wiring RSL through the transistor120. Accordingly, the potential of the wiring RL is set to a low-level potential. On the other hand, in the case where the voltage between the wiring BL and the wiring RSL is lower than the threshold voltage of the transistor120, the transistor120is turned off and the potential of the wiring RL is kept at the high-level potential. Accordingly, a signal corresponding to the read potential output to the wiring BL from the memory cell21is output to the wiring RL.

When the circuit41is formed with the transistor120, the configuration of the read circuit40can be significantly simplified. Therefore, an increase in the area of the semiconductor device10can be suppressed, and the manufacturing process of the semiconductor device10can be simplified.

The structures of the transistors110and120are not particularly limited. For example, an OS transistor may be used as each of the transistors110and120as well as the transistor101, or a different transistor may be used. For example, a transistor whose channel formation region is formed in part of a substrate including a single crystal semiconductor (the transistor is hereinafter also referred to as a single crystal transistor) may be used as each of the transistors110and120. As the substrate including a single crystal semiconductor, a single crystal silicon substrate, a single crystal germanium substrate, or the like can be used.

As each of the transistors110and120, a transistor whose channel formation region is formed in a film including a semiconductor material other than an oxide semiconductor can also be used. For example, a transistor whose channel formation region is formed in a film including a non-single-crystal semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, amorphous germanium, microcrystalline germanium, or polycrystalline germanium can be used.

As the transistor101, the above-described single crystal transistor or the above-described transistor whose channel formation region is formed in a film including a semiconductor material other than an oxide semiconductor can also be used.

In the semiconductor device10illustrated inFIG. 1, the cell array20and the control and read circuits30and40are preferably stacked.FIG. 3Aillustrates a structural example of the semiconductor device10in which the cell array20is stacked over the control circuit30and the read circuit40and the cell array20overlaps with the control circuit30and the read circuit40. With such a structure, the control circuit30and the read circuit40can be provided in the semiconductor device10with no or a suppressed increase in the area of the semiconductor device10.

FIG. 3Billustrates a structure in which the memory cell21inFIG. 3Ais stacked over the circuit31and the circuit41. Here, the transistor101preferably overlaps with the transistor110or the transistor120. With such a structure, the area of the semiconductor device10can be reduced.

Note that the phrase “a transistor has a region where the transistor overlaps with another transistor” means, for example, that the transistor has a region where a channel formation region, a gate electrode, a source electrode, or a drain electrode of the transistor overlaps with a channel formation region, a gate electrode, a source electrode, or a drain electrode of the other transistor. In other words, the phrase includes a case where the transistor has a region where channel formation regions, gate electrodes, source electrodes, or drain electrodes of the transistor and the other transistor overlap with each other.

As illustrated inFIG. 1,FIG. 2, andFIGS. 3A and 3B, a capacitor50is added to the wiring BL owing to another wiring, electrode, or the like. The capacitor50corresponds to a parasitic capacitance added to the wiring BL. Here, Cs/Cb, the ratio of the capacitance Csof the capacitor102inFIG. 2to the capacitance Cbof the capacitor50, is a value which indicates the performance of the memory cell21. A greater value of Cs/Cbenables more high-speed and stable writing and reading to and from the memory cell21and is more advantageous for the memory cell21to be capable of storing multi-level data. A decrease in Cbcan increase the speed and stability of the memory cell21. Alternatively, a decrease in Cbcan decrease Cswith the value of Cs/Cbmaintained and can reduce the area of the capacitor102.

In order to decrease Cb, it is preferable that the number of memory cells21connected to one wiring BL be small and the wiring BL be short. For example, Cbcan be decreased by dividing the cell array20and halving the number of memory cells21connected to one wiring BL. However, the number of cell arrays20is doubled in that case. In addition, the numbers of control circuits30and read circuits40included in the semiconductor device10are also doubled because each cell array20needs one control circuit30and one read circuit40. Therefore, a decrease in the number of memory cells21connected to one wiring BL might result in an increase in the area of the semiconductor device10. In one embodiment of the present invention, there is no or a small increase in the area of the semiconductor device10due to the presence of the control circuit30and the read circuit40because the cell array20can be stacked over the control circuit30and the read circuit40as illustrated inFIG. 3A. Thus, an increase in the area of the semiconductor device10can be suppressed, and at the same time, the cell array20can be divided to decrease the number of memory cells21connected to one wiring BL and make the wiring BL short. Accordingly, the capacitance Cbof the capacitor50added to the wiring BL can be decreased. Note that the number of memory cells21connected to one wiring BL can be reduced to, for example, 2 to 8.

Next, operation of the semiconductor device10will be described. Specifically, an operation example of multi-level data writing and reading to and from the memory cell21illustrated inFIG. 2will be described below.

First, a potential corresponding to data to be written to the memory cell21(this potential is hereinafter also referred to as a write potential) is supplied to the wiring CL. For example, in the case where the memory cell21stores four-level data, any of four potentials V1, V2, V3, and V4(V1>V2>V3>V4) is selected and supplied to the wiring CL. The potential of the wiring WEB is set to a low-level potential, and a predetermined potential (here, a high-level potential) is supplied to the wiring BL. Note that the potential of the wiring BL is higher than or equal to V1in this example. A selection signal is supplied to the wiring WL to turn on the transistor101. Accordingly, the high-level potential is supplied from the wiring BL to the node SN.

Next, the potential of the wiring WL is set to a potential at which the transistor101is turned off, so that the transistor101is turned off. This makes the node SN floating, and the potential of the node SN is retained.

Next, the potential of the wiring CL is set to a low-level potential. Note that the potential of the wiring CL is lower than or equal to V4in this example. The amount of change in the potential of the wiring CL at that time varies depending on the write potential. For example, the amount of change in the potential from the potential V1to the low-level potential is larger than the amount of change in the potential from the potential V2to the low-level potential. Since the node SN at that time is in a floating state, the potential of the node SN changes in accordance with a change in the potential of the wiring CL by capacitive coupling due to the capacitor102. That is, the potential of the node SN becomes a potential based on the write potential supplied to the wiring CL. The potential of the node SN after the potential of the wiring CL is changed from V1, V2, V3, or V4to the low-level potential is denoted by V1′, V2′, V3′, or V4′ (V1′<V2′<V3′<V4′). Accordingly, the potential based on the write potential supplied to the wiring CL is retained at the node SN. Thus, multi-level data writing is performed.

As described above, multi-level data can be written to the memory cell21by supplying a write control signal to the wiring CL and controlling the potential of the node SN.

Next, the operation of reading data from the memory cell21will be described. First, the potential of the wiring WEB is set to a low-level potential and the potential of the wiring BL is precharged to a high-level potential. Then, the potential of the wiring WEB is set to a high-level potential and the wiring BL is brought into a floating state. After that, a selection signal is supplied to the wiring WL to turn on the transistor101. Accordingly, the wiring BL is electrically connected to the node SN.

When the wiring BL is electrically connected to the node SN, the capacitor102and the capacitor50are added to the wiring BL and charge accumulated in the capacitor102is distributed. As a result, the potential of the wiring BL varies depending on the potential retained at the node SN. The potential of the wiring BL and the node SN after charge distribution in the case where the potential retained at the node SN is V1′, V2′, V3′, or V4′ is denoted by V1″, V2″, V3″, or V4″ (V1″<V2″<V3″<V4″).

When the capacitance Csof the capacitor102is larger than the capacitance Cbof the capacitor50, the amount of change in potential due to charge distribution (a change from V1′, V2′, V3′, or V4′ to V1″, V2″, V3″, or V4″) can be small. Therefore, the area of electrodes of the capacitor102is preferably larger than the area of electrodes of the capacitor50. Alternatively, the thickness of a dielectric of the capacitor102is preferably smaller than the thickness of a dielectric of the capacitor50.

Next, with the wiring RSL set at a constant potential (here, a low-level potential), the wiring RL is precharged to a predetermined potential (here, a high-level potential). In the case where the voltage between the wiring BL and the wiring RSL is higher than or equal to the threshold voltage of the transistor120, the transistor120is turned on and the potential of the wiring RL is set to the low-level potential. On the other hand, in the case where the voltage between the wiring BL and the wiring RSL is lower than the threshold voltage of the transistor120, the transistor120remains off and the potential of the wiring RL is kept at the high-level potential. Therefore, the potential of the wiring BL after charge distribution can be determined by reading the potential of the wiring RL.

In the case where the memory cell21stores multi-level data, a read control signal is supplied to the wiring CL and the above-described operation is performed. Specifically, charge distribution is performed first, and then, the potential of the wiring CL is increased from the low-level potential to V4. At that time, the potential of the wiring BL is increased by capacitive coupling due to the capacitor102. Then, the potential of the wiring RL after the potential of the wiring BL is increased is read. Thus, data stored in the memory cell21is read. Note that there is no need to increase the potential of the wiring CL when the low-level potential is V4.

In the case where the wiring RL is at the low-level potential, the potential stored at the node SN can be determined to be V4′, and in the case where the wiring RL is kept at the high-level potential, the potential stored at the node SN can be determined to be V2′, or V3′. In the case where the wiring RL is at the low-level potential when the potential of the wiring CL is V4, the potential of the wiring CL is kept at V4in the subsequent reading operation.

In the case where the wiring RL is kept at the high-level potential, the potential of the wiring CL is increased from V4to V3. At that time, the potential of the wiring BL is increased by capacitive coupling due to the capacitor102. Then, the potential of the wiring RL after the potential of the wiring BL is increased is read. Thus, data stored in the memory cell21is read. Specifically, in the case where the wiring RL is at the low-level potential, the potential stored at the node SN can be determined to be V3′, and in the case where the wiring RL is kept at the high-level potential, the potential stored at the node SN can be determined to be V1′ or V2′. In the case where the wiring RL is at the low-level potential when the potential of the wiring CL is V3, the potential of the wiring CL is kept at V3in the subsequent reading operation.

In the case where the wiring RL is kept at the high-level potential, the potential of the wiring CL is increased from V3to V2. At that time, the potential of the wiring BL is increased by capacitive coupling due to the capacitor102. Then, the potential of the wiring RL after the potential of the wiring BL is increased is read. Thus, data stored in the memory cell21is read. Specifically, in the case where the wiring RL is at the low-level potential, the potential stored at the node SN can be determined to be V2′, and in the case where the wiring RL is kept at the high-level potential, the potential stored at the node SN can be determined to be V1′. In the case where the wiring RL is at the low-level potential when the potential of the wiring CL is V2, the potential of the wiring CL is kept at V2in the subsequent reading operation. On the other hand, in the case where the wiring RL remains at the high-level potential when the potential of the wiring CL is V2, the potential of the wiring CL is increased to V1.

As described above, multi-level data stored in the memory cell21can be read by supplying a read control signal to the wiring CL to sequentially change the potential and reading the potential of the wiring RL at that time. Although the operation example in which the potential of the wiring CL is sequentially increased is described above, the potential of the wiring CL may be sequentially decreased to perform reading.

Next, data write-back to the memory cell21will be described. Data reading from the memory cell21illustrated inFIG. 2is destructive reading in which charge accumulated in the node SN is released. Therefore, in the case where data is continuously retained after the read operation, an operation of writing read data to the memory cell21again (a write-back operation) is performed as described below.

First, after the read operation, the potential of the wiring WEB is set to the low-level potential and the potential of the wiring BL is set to the high-level potential. Note that the high-level potential is higher than or equal to V1in this example. Then, the potential of the wiring WL is set to a potential at which the transistor101is turned on, so that the transistor101is turned on. Accordingly, the high-level potential is supplied from the wiring BL to the node SN.

Next, the potential of the wiring WL is set to a potential at which the transistor101is turned off, so that the transistor101is turned off. This makes the node SN floating, and the potential of the node SN is retained.

The potential of the wiring CL after the read operation varies depending on the potential stored at the node SN. Specifically, in the case where the potential stored at the node SN is V1′, V2′, V3′, or V4′, the potential of the wiring CL is V1, V2, V3, or V4.

In this state, the potential of the wiring CL is changed to the low-level potential. Note that the low-level potential is lower than or equal to V4in this example. Thus, the potential of the node SN changes in accordance with a change in the potential of the wiring CL by capacitive coupling due to the capacitor102. The potential of the node SN after the potential of the wiring CL is changed from V1, V2, V3, or V4to the low-level potential is V1′, V2′, V3′, or V4′, as in the write operation. Accordingly, the same potential as that in the write operation is retained at the node SN. Thus, data write-back is performed.

As described above, multi-level data can be written back to the memory cell21by changing the potential of the wiring CL and controlling the potential of the node SN. There is no need of analog/digital conversion or digital/analog conversion in the above-described write-back operation. Therefore, the speed of the write-back operation can be increased, and the configuration of the semiconductor device10can be simplified.

Next, a specific operation example of the memory cell21, the circuit31, and the circuit41illustrated inFIG. 2will be described using a timing chart ofFIG. 4. Note that periods T11to T13are periods during which data is written to the memory cell21; periods T21to T26are periods during which data is read from the memory cell21; and periods T31to T33are periods during which data is written back to the memory cell21. As one example, an operation of four-level data writing and reading to and from the memory cell21will be described here.

First, in the period T11, the wiring CL is set at any of the potentials V1, V2, V3, and V4(V1>V2>V3>V4). The potential of the wiring WEB is set to a low-level potential, and the potential of the wiring BL is set to a high-level potential (here, the potential V1). The potential of the wiring WL is set to a high-level potential to turn on the transistor101. Accordingly, the potential V1of the wiring BL is supplied to the node SN. Note that the potential of the wiring CL in the period T11corresponds to the write potential.

Next, in the period T12, the potential of the wiring WL is set to a low-level potential to turn off the transistor101. This makes the node SN floating, and the potential of the node SN is retained.

Then, in the period T13, the potential of the wiring CL is set to a low-level potential (here, V4). At that time, the potential of the node SN changes to any of the potentials V1′, V2′, V3′, and V4′ (V1′<V2′<V3′<V4′), which correspond respectively to the potentials V1, V2, V3, and V4, by capacitive coupling due to the capacitor102. Accordingly, the potential based on the write potential supplied to the wiring CL is retained at the node SN. Thus, data writing to the memory cell21is performed.

Then, in the period T21, the potential of the wiring WEB is set to the low-level potential, and the potential of the wiring BL is precharged to the high-level potential (here, the potential V1). Note that the potential of the wiring CL is kept at V4.

Next, in the period T22, the potential of the wiring WEB is set to a high-level potential to make the wiring BL floating. The potential of the wiring WL is set to the high-level potential to turn on the transistor101. Accordingly, the wiring BL is electrically connected to the node SN, charge accumulated in the capacitor102is distributed, and the potentials of the wiring BL and the node SN are changed. The potential of the wiring BL and the node SN at that time is changed to any of the potentials V1″, V2″, V3″, and V4″ (V1″<V2″<V3″<V4″), which correspond respectively to the potentials V1′, V2′, V3′, and V4′ of the node SN in the period T13. In the example given here, the potential V1of the wiring BL which is precharged in the period T21and the potential V4′ of the node SN in the period T13are at the same level and V4′ is equal to V4″.

Next, in the period T23, the wiring RL is precharged to a high-level potential. At that time, the potential of the wiring RL changes depending on whether the transistor120is turned on or off. Specifically, assuming that the transistor120is turned on when the potential of the wiring RSL is constant (a low-level potential) and the potential of the gate of the transistor120is higher than or equal to Vr, the potential of the wiring RL changes from the high-level potential to a low-level potential when the potential of the wiring BL is higher than or equal to Vr. In the case where the potential of the wiring BL is lower than Vr, the potential of the wiring RL is kept at the high level.

In the period T23, the potential of the wiring RL is set to the low-level potential when the potential of the wiring BL is V4″ (≧Vr), and the potential of the wiring RL is kept at the high level when the potential of the wiring BL is V1″ (<Vr), V2″ (<Vr), or V3″ (<Vr). Thus, whether the potential retained in the memory cell21is V4′ or not can be determined by reading the potential of the wiring RL in the period T23. The potential of the wiring CL in the periods T24to T26is kept at V4in the case where the potential of the wiring RL becomes the low-level potential in the period T23.

In the case where the wiring RL is at the high-level potential in the period T23, the potential of the wiring CL is increased from V4to V3in the period T24. At that time, the potentials of the node SN and the wiring BL are increased by capacitive coupling due to the capacitor102. The potential of the wiring BL after an increase from V1″, V2″, or V3″ is denoted by V1′″, V2′″, or V3′″.

When the potential of the wiring BL in the period T22is V3″, the potential of the wiring BL in the period T24is V3′″(≧Vr) and the potential of the wiring RL is the low-level potential. When the potential of the wiring BL in the period T22is V1″ or V2″, the potential of the wiring BL in the period T24is V1′″ (<Vr) or V2′″ (<Vr) and the potential of the wiring RL is kept at the high level. Thus, whether the potential retained in the memory cell21is V3′ or not can be determined by reading the potential of the wiring RL in the period T24. The potential of the wiring CL in the periods T25and T26is kept at V3in the case where the potential of the wiring RL becomes the low-level potential in the period T24.

In the case where the wiring RL is at the high-level potential in the period T24, the potential of the wiring CL is increased from V3to V2in the period T25. At that time, the potentials of the node SN and the wiring BL are increased by capacitive coupling due to the capacitor102. The potential of the wiring BL after an increase from V1′″ or V2′″ is denoted by V1″″ or V2″″.

When the potential of the wiring BL in the period T22is V2″, the potential of the wiring BL in the period T25is V2″″ (≧Vr) and the potential of the wiring RL is the low-level potential. When the potential of the wiring BL in the period T22is V1″, the potential of the wiring BL in the period T25is V1″″ (<Vr) and the potential of the wiring RL is kept at the high level. Thus, whether the potential retained in the memory cell21is V1′ or V2′ can be determined by reading the potential of the wiring RL in the period T25. The potential of the wiring CL in the period T26is kept at V2in the case where the potential of the wiring RL becomes the low-level potential in the period T25. On the other hand, in the case where the wiring RL is at the high-level potential in the period T25, the potential of the wiring CL is increased from V2to V1in the period T26.

As described above, the potential retained at the node SN in the period T13can be determined to be V1′, V2′, V3′, or V4′ by sequentially changing the potential of the wiring CL and reading the potential of the wiring RL at that time. Accordingly, data reading from the memory cell21can be performed.

Next, in the period T31, the potential of the wiring WEB is set to the low-level potential, and the potential of the wiring BL is set to the high-level potential (here, the potential V1). Accordingly, the potential V1of the wiring BL is supplied to the node SN.

Next, in the period T32, the potential of the wiring WL is set to the low-level potential to turn off the transistor101. This makes the node SN floating, and the potential of the node SN is retained. Note that the potential of the wiring CL in the period T32varies depending on the operation in the periods T23to T26. Specifically, in the case where the potential stored at the node SN in the period T13is V1′, V2′, V3′, or V4′, the potential of the wiring CL is V1, V2, V3, or V4.

Then, in the period T33, the potential of the wiring CL is set to the low-level potential (here, V4). At that time, the potential of the node SN changes to any of the potentials V1′, V2′, V3′, and V4′, which correspond respectively to the potentials V1, V2, V3, and V4, by capacitive coupling due to the capacitor102. Accordingly, the same potential as that in the period T13is retained at the node SN. Thus, data write-back to the memory cell21is performed.

As described above, multi-level data writing, reading, and write-back can be controlled by supplying control signals to the wiring CL.

With the above-described configuration of one embodiment of the present invention, multi-level data writing to the memory cell21and multi-level data reading from the memory cell21can be performed.

In one embodiment of the present invention, the area of the semiconductor device10can be reduced by stacking the cell array20and the control and read circuits30and40. In addition, the capacitance added to the wiring BL can be reduced, and the operating speed of the semiconductor device10can be increased. Such a configuration is also effective when two-level data is stored in the memory cell21.

In one embodiment of the present invention, with the use of an OS transistor, data in the memory cell21can be retained for a long time, and the power consumption of the semiconductor device10can be reduced. With the use of the OS transistor, the range of potentials to be retained at the node SN can be widened. Accordingly, the amount of data to be stored in the memory cell21can be increased, and multi-level data can be accurately stored. Thus, a reduction in area and an improvement in reliability of the semiconductor device10can be achieved.

In this embodiment, modification examples of a semiconductor device of one embodiment of the present invention will be described.

<Modification Example of Memory Cell21>

FIGS. 5A and 5Billustrate modification examples of the memory cell21. Memory cells21illustrated inFIGS. 5A and 5Bdiffer from the memory cell21inFIG. 2in that the transistor101includes a pair of gates. That is, the transistors101inFIGS. 5A and 5Beach have a structure obtained by providing the transistor101inFIG. 2with a back gate.

InFIG. 5A, the back gate of the transistor101is connected to the gate of the transistor101. InFIG. 5B, the back gate of the transistor101is connected to a wiring BGL. Note that the wiring BGL may be a wiring to which a fixed potential is supplied or a wiring to which two or more different potentials are supplied.

When the transistor101has a pair of gates between which a semiconductor film is positioned as illustrated inFIG. 5B, one of the gates may be supplied with a signal A, and the other gate may be supplied with a fixed potential Vb.

The signal A is, for example, a signal for controlling the on/off state. The signal A may be a digital signal with two kinds of potentials, a potential V1and a potential V2(V1>V2). For example, the potential V1can be a high power supply potential, and the potential V2can be a low power supply potential (e.g., a ground potential). The signal A may be an analog signal.

The fixed potential Vbis, for example, a potential for controlling the threshold voltage VthAof the transistor101. The fixed potential Vbmay be the potential V1or the potential V2. In this case, no additional potential generation circuit is necessary to generate the fixed potential Vb, which is preferable. The fixed potential Vbmay be a potential different from the potential V1or the potential V2. When the fixed potential Vbis low, the threshold voltage VthAcan be high in some cases. As a result, the drain current flowing when the gate-source voltage Vgsis 0 V can be reduced, and leakage current in a circuit including the transistor101can be reduced in some cases. The fixed potential Vbmay be, for example, lower than the low power supply potential. When the fixed potential Vbis high, the threshold voltage VthAcan be low in some cases. As a result, the drain current flowing when the gate-source voltage Vgsis VDDand the operating speed of the circuit including the transistor101can be increased in some cases. The fixed potential Vbmay be, for example, higher than the low power supply potential.

Alternatively, one of the gates of the transistor101may be supplied with the signal A, and the other gate may be supplied with a signal B. The signal B is, for example, a signal for controlling the on/off state of the transistor101. The signal B may be a digital signal with two kinds of potentials, a potential V3and a potential V4(V3>V4). For example, the potential V3may be a high power supply potential, and the potential V4may be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may have the same digital value as the signal A. In this case, the on-state current of the transistor101and the operating speed of the circuit including the transistor101can be increased in some cases. Here, the potential V1of the signal A may be different from the potential V3of the signal B. Furthermore, the potential V2of the signal A may be different from the potential V4of the signal B. For example, if a gate insulating layer for the gate to which the signal B is input is thicker than a gate insulating layer for the gate to which the signal A is input, the potential amplitude of the signal B (V3−V4) may be larger than the potential amplitude of the signal A (V1−V2). In this manner, the influence of the signal A and that of the signal B on the on/off state of the transistor101can be substantially the same in some cases.

When both the signal A and the signal B are digital signals, the signal B may have a digital value different from that of the signal A. In this case, the signal A and the signal B can separately control the transistor101, and thus, higher performance can be achieved. The transistor101which is, for example, an n-channel transistor can function by itself as a NAND circuit, a NOR circuit, or the like in the following case: the transistor101is turned on only when the signal A has the potential V1and the signal B has the potential V3, or the transistor101is turned off only when the signal A has the potential V2and the signal B has the potential V4. The signal B may be a signal for controlling the threshold voltage VthA. For example, the potential of the signal B in a period where the circuit including the transistor101operates may be different from the potential of the signal B in a period where the circuit does not operate. The potential of the signal B may vary depending on the operation mode of the circuit. In this case, the potential of the signal B is not necessarily changed as frequently as the potential of the signal A.

When both the signal A and the signal B are analog signals, the signal B may be an analog signal having the same potential as the signal A, an analog signal whose potential is a constant times the potential of the signal A, an analog signal whose potential is higher or lower than the potential of the signal A by a constant, or the like. In this case, it may be possible to increase the on-state current of the transistor101and the operating speed of the circuit including the transistor101. The signal B may have an analog value different from that of the signal A. In this case, the signal A and the signal B can separately control the transistor101, and thus, higher performance can be achieved.

The signal A may be a digital signal, and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal, and the signal B may be a digital signal.

Alternatively, one of the gates of the transistor101may be supplied with a fixed potential Va, and the other gate may be supplied with the fixed potential Vb. When both of the gates of the transistor101are supplied with the fixed potentials, the transistor101can function as an element equivalent to a resistor in some cases. For example, when the transistor101is an n-channel transistor, the effective resistance of the transistor can be sometimes low (high) when the fixed potential Vaor the fixed potential Vbis high (low). When both the fixed potential Vaand the fixed potential Vbare high (low), the effective resistance can be lower (higher) than that of a transistor with only one gate in some cases.

Although the structure of the transistor101including a pair of gates is described here, the transistor110and the transistor120inFIG. 2may each similarly have a pair of gates.

<Modification Examples of Circuits31and41>

FIGS. 6A and 6Billustrate modification examples of the circuits31and41.

The circuit41inFIG. 6Adiffers from that inFIG. 2in that the transistor120is a p-channel transistor. InFIG. 6A, for example, with the potential of the wiring RSL set to a high-level potential, the wiring RL is precharged to a low-level potential during a read operation; thus, data stored in the memory cell21can be read. Other details of operations of the circuit41are similar to those in Embodiment 1.

The circuit31inFIG. 6Bdiffers from that inFIG. 2in that the transistor110is an n-channel transistor. InFIG. 6B, a low power supply potential VSS (e.g., a ground potential) can be supplied to the wiring VL. Then, data writing or write-back can be performed by supplying a low-level potential to the wiring BL. Data reading can be performed by precharging the wiring BL to a low-level potential. Other details of operations of the circuit31are similar to those in Embodiment 1.

When the transistor110and the transistor120have the same polarity as illustrated inFIG. 6A or 6B, the circuit31and the circuit41can be formed through the same process. Thus, the manufacturing process of the semiconductor device10can be simplified. When the transistor110or120and the transistor101are OS transistors and are formed in the same layer, the control circuit30or the read circuit40and the cell array20can be partly manufactured through a common process.

The semiconductor device10may have a structure in which the control circuit30and the read circuit40are formed in different layers and the memory cell21, the circuit31, and the circuit41are stacked.FIGS. 7A to 7Deach illustrate an example of a structure in which the memory cell21, the circuit31, and the circuit41are stacked.

FIG. 7Aillustrates a structure example of the semiconductor device10including the circuit41over the circuit31and the memory cell21over the circuit41. For example, the transistor110may be a single crystal transistor; the transistor101and the transistor120may be OS transistors; the transistor120may be provided over the transistor110; and the transistor101may be provided over the transistor120.

As illustrated inFIG. 7B, the transistor110may be an n-channel transistor, and all the transistors101,110, and120may be OS transistors. In that case, the semiconductor device10can be formed by stacking three layers each including the OS transistor.

When the transistor120is the OS transistor, the withstand voltage of the transistor120can be increased. Accordingly, the range of potentials to be supplied to the wiring BL connected to the gate of the transistor120can be widened, and an increase in the amount of data to be stored in the memory cell21and an improvement in reliability of multi-level data reading can be achieved.

Note that the order of stacking the memory cell21, the circuit31, and the circuit41is not limited to the above examples and can be freely changed. For example, the circuit31may be provided between the memory cell21and the circuit41as illustrated inFIG. 7C, or the memory cell21may be provided between the circuit31and the circuit41as illustrated inFIG. 7D.

InFIGS. 7A to 7D, at least one of the transistors101,110, and120preferably has a region where it overlaps with another transistor, in which case the area of the semiconductor device10can be reduced. Alternatively, each of the transistors101,110, and120preferably has a region where it overlaps with the other two transistors, in which case the area of the semiconductor device10can be further reduced.

As illustrated inFIG. 8, a plurality of memory cells21can be stacked. Thus, the area of the cell array20can be reduced. In that case, the transistor101of the memory cell21provided in one layer preferably has a region where it overlaps with the transistor101of the memory cell21provided in another layer.

As described above, the area of the semiconductor device10can be reduced by stacking circuits of the semiconductor device10.

In this embodiment, a memory device and a computer including the semiconductor device of one embodiment of the present invention will be described.

<Configuration Example of Memory Device>

FIG. 9is a block diagram illustrating a configuration example of a memory device including the semiconductor device10described in the above embodiment.

A memory device300illustrated inFIG. 9includes a row selection driver310and a column selection driver320in addition to the semiconductor device10described in the above embodiment.

The row selection driver310is a driver circuit having a function of selecting memory cells21in a predetermined row by supplying a selection signal to the wiring WL. The row selection driver310in the memory device300allows the memory cells21to be selected row by row and data to be written to and read from the selected memory cells21. The row selection driver310also has a function of controlling the potential of the wiring BL by supplying a predetermined signal to the wiring WEB.

The column selection driver320is a driver circuit having a function of controlling data writing to the memory cells21or data reading from the memory cells21by supplying a write control signal or a read control signal to the wiring CL. The column selection driver320may have a function of precharging the potential of the wiring CL, a function of initializing the potential of the wiring CL, a function of making the wiring CL floating, and the like. Specifically, the column selection driver320is a circuit having a function of supplying a write potential corresponding to multi-level data, a precharge voltage Vprecharge, an initialization voltage Vinitial, and the like to the wiring CL through a switch. The column selection driver320in the memory device300allows the memory cells21to be selected column by column and data to be written to and read from the selected memory cells21. Note that the column selection driver320does not need to have all the above-mentioned functions and may lack some of the functions as appropriate depending on the operation of the memory cells21.

The column selection driver320also has a function of reading data stored in the memory cell21from the potential of the wiring RL. Data read by the column selection driver320may be used to generate a signal to be supplied to the wiring CL or may be output from the column selection driver320to the outside. Note that the wiring RL may be connected to a read circuit different from that connected to the column selection driver320. In this case, the read circuit performs reading, outputting, or the like of data stored in the memory cell21.

[Configuration Example of Row Selection Driver]

FIG. 10is a block diagram illustrating a configuration example of the row selection driver310inFIG. 9.

The row selection driver310inFIG. 10includes a decoder311, control circuits312, and a control circuit313. The wiring WL in every row is provided with one control circuit312, and each control circuit312is connected to one of the wirings WL[1] to WL[n].

The decoder311is a circuit having a function of outputting a signal for selecting a specific wiring WL. Specifically, the decoder311receives an address signal Address and selects the control circuit312in a predetermined row in accordance with the address signal Address. With the decoder311, the row selection driver310can select a given row to write or read data. Note that the decoder311may have a function of selecting one of the control circuits312or may have a function of selecting two or more of the control circuits312.

The control circuits312are circuits having a function of selectively outputting a selection signal to the wiring WL in a specific row selected by the decoder311. Specifically, the control circuits312receive a write control signal Write_CONT and a read control signal Read_CONT and selectively output selection signals in accordance with these input signals. With the control circuits312, the row selection driver310can selectively output the selection signal to the row selected by the decoder311.

The control circuit313is a circuit having a function of supplying a signal for selecting the control circuit30to the wiring WEB. With the control circuit313, the row selection driver310can control the timing of supplying a predetermined potential to the wiring BL.

[Configuration Example of Column Selection Driver]

FIG. 11is a block diagram illustrating a configuration example of a mechanism which controls a signal to be supplied to the wiring CL in the column selection driver320illustrated inFIG. 9.

The column selection driver320illustrated inFIG. 11includes a decoder321, latch circuits322, D/A converters323, switch circuits324, transistors325, and transistors326. Each column is provided with one latch circuit322, one D/A converter323, one switch circuit324, one transistor325, and one transistor326. Furthermore, the switch circuit324, the transistor325, and the transistor326of each column are connected to the wiring CL.

The decoder321is a circuit having a function of selecting a column in which the wiring CL is provided and distributing input data to output the data. Specifically, the decoder321receives an address signal Address and data Data and outputs the data Data to the latch circuit322of any of columns in accordance with the address signal Address. The decoder321allows the column selection driver320to select a given column and write data.

Note that the data Data input to the decoder321is a-bit digital data. The a-bit digital data is a signal represented by binary data of ‘1’ or ‘0’ for each bit. For example, 2-bit digital data is data represented by ‘00’, ‘01’, ‘10’, or ‘11’.

The latch circuit322has a function of temporarily storing the input data Data. Specifically, the latch circuit322is a flip-flop circuit that receives a latch signal W_LAT, stores the data Data, and outputs the data Data to the D/A converter323in accordance with the latch signal W_LAT. The latch circuit322enables the column selection driver320to write data at an opportune time.

The D/A converter323is a circuit having a function of converting input digital data Data into analog data Vdata. For example, the D/A converter323converts 2-bit data Data into one of four potentials (V0to V3) and outputs the potential to the switch circuit324. The D/A converter323allows the column selection driver320to convert data to be written to the memory cell21into a potential corresponding to multi-level data.

Note that the data Vdataoutput from the D/A converter323can be represented by different voltage levels. For example, 2-bit data Vdatais represented by any of the four voltage levels (0.0 V, 0.4 V, 0.8 V, or 1.2 V).

The switch circuit324has a function of supplying input data Vdatato the wiring CL and a function of bringing the wiring CL into an electrically floating state. Specifically, the switch circuit324includes an analog switch and an inverter. The switch circuit324supplies the data Vdatato the wiring CL in accordance with a switch control signal Write_SW, and then makes the wiring CL electrically floating by turning off the analog switch. The switch circuit324enables the column selection driver320to keep the wiring CL in an electrically floating state after the data Vdatais supplied to the wiring CL.

The transistor325has a function of supplying an initialization voltage Vinitialto the wiring CL and a function of bringing the wiring CL into an electrically floating state. Specifically, the transistor325is a switch that supplies an initialization voltage Vinitialto the wiring CL in accordance with an initialization control signal Init_EN, and then brings the wiring CL into an electrically floating state. The transistor325enables the column selection driver320to keep the wiring CL in an electrically floating state after the initialization voltage Vinitialis supplied to the wiring CL. Note that the initialization voltage Vinitialcan be used as, for example, a potential supplied to the wiring CL in the period T13or the period T33inFIG. 4.

The transistor326has a function of supplying a precharge voltage Vprechargeto the wiring CL and a function of bringing the wiring CL into a floating state. Specifically, the transistor326is a switch that supplies a precharge voltage Vprechargeto the wiring CL in accordance with a precharge control signal Pre_EN, and then brings the wiring CL into an electrically floating state. The transistor326enables the column selection driver320to keep the wiring CL in an electrically floating state after the precharge voltage Vprechargeis supplied to the wiring CL. Note that the transistor326can be omitted.

<Configuration Example of Computer>

FIG. 12is a block diagram illustrating a configuration example of a computer including the above-described memory device.

A computer400includes an input device410, an output device420, a central processing unit430, and a main memory device440.

The central processing unit430includes a control circuit431, an arithmetic circuit432, a memory device433, and a memory device434.

The input device410has a function of inputting data from the outside to the computer400.

The output device420has a function of outputting data from the computer400to the outside.

The control circuit431has a function of outputting control signals to the input device410, the output device420, and the main memory device440for controlling these devices.

The arithmetic circuit432has a function of performing a calculation using input data.

The memory device433retains data used for calculations or the like by the arithmetic circuit432. The memory device433has a function of a register.

The memory device434is used to store a copy of frequently used information of the main memory device440. The memory device434has a function of a cache memory.

The memory device434can be accessed at a higher speed than the main memory device440, which increases the processing speed of the central processing unit430. Note that the main memory device has a larger capacity than the cache memory, and the cache memory has a larger capacity than the register. The cache memory and the register operate at a higher speed than the main memory device. The memory device300inFIG. 9can be used as the memory device433, the memory device434, or the main memory device440.

Described in this embodiment are transistors of one embodiment of the disclosed invention.

Note that the transistors of one embodiment of the present invention preferably include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film or a nanocrystalline oxide semiconductor (nc-OS) film described in Embodiment 6.

FIGS. 13A to 13Care a top view and cross-sectional views of a transistor1400a.FIG. 13Ais a top view.FIG. 13Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 13A, andFIG. 13Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 13A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG. 13A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction of the transistor1400aand a channel width direction of the transistor1400a, respectively.

The transistor1400aincludes a substrate1450, an insulating film1401over the substrate1450, a conductive film1414over the insulating film1401, an insulating film1402covering the conductive film1414, an insulating film1403over the insulating film1402, an insulating film1404over the insulating film1403, a metal oxide1431and a metal oxide1432which are stacked in this order over the insulating film1404, a conductive film1421in contact with top and side surfaces of the metal oxide1432, a conductive film1423also in contact with the top and side surfaces of the metal oxide1432, a conductive film1422over the conductive film1421, a conductive film1424over the conductive film1423, an insulating film1405over the conductive films1422and1424, a metal oxide1433in contact with the metal oxides1431and1432, the conductive films1421to1424, and the insulating film1405, an insulating film1406over the metal oxide1433, a conductive film1411over the insulating film1406, a conductive film1412over the conductive film1411, a conductive film1413over the conductive film1412, an insulating film1407covering the conductive film1413, and an insulating film1408over the insulating film1407. Note that the metal oxides1431to1433are collectively referred to as a metal oxide1430.

The metal oxide1432is a semiconductor and serves as a channel of the transistor1400a.

Furthermore, the metal oxides1431and1432include a region1441and a region1442. The region1441is formed in the vicinity of a region where the conductive film1421is in contact with the metal oxides1431and1432. The region1442is formed in the vicinity of a region where the conductive film1423is in contact with the metal oxides1431and1432.

The regions1441and1442serve as low-resistance regions. The region1441contributes to a decrease in the contact resistance between the conductive film1421and the metal oxides1431and1432. The region1442also contributes to a decrease in the contact resistance between the conductive film1423and the metal oxides1431and1432.

The conductive films1421and1422serve as one of source and drain electrodes of the transistor1400a. The conductive films1423and1424serve as the other of the source and drain electrodes of the transistor1400a.

The conductive film1422is configured to allow less oxygen to pass therethrough than the conductive film1421. It is thus possible to prevent a decrease in the conductivity of the conductive film1421due to oxidation.

The conductive film1424is also configured to allow less oxygen to pass therethrough than the conductive film1423. It is thus possible to prevent a decrease in the conductivity of the conductive film1423due to oxidation.

The conductive films1411to1413serve as a first gate electrode of the transistor1400a.

The conductive films1411and1413are configured to allow less oxygen to pass therethrough than the conductive film1412. It is thus possible to prevent a decrease in the conductivity of the conductive film1412due to oxidation.

The insulating film1406serves as a first gate insulating film of the transistor1400a.

The conductive film1414serves as a second gate electrode of the transistor1400a.

The potential applied to the conductive films1411to1413may be the same as or different from that applied to the conductive film1414. The conductive film1414may be omitted in some cases.

The insulating films1401to1404serve as a base insulating film of the transistor1400a. The insulating films1402to1404also serve as a second gate insulating film of the transistor1400a.

The insulating films1405,1407, and1408serve as a protective insulating film or an interlayer insulating film of the transistor1400a.

As illustrated inFIG. 13C, the side surface of the metal oxide1432is surrounded by the conductive film1411. With this structure, the metal oxide1432can be electrically surrounded by an electric field of the conductive films1411and1412. Such a structure of a transistor in which a semiconductor is electrically surrounded by an electric field of a gate electrode is referred to as a surrounded channel (s-channel) structure. Since a channel is formed in the entire metal oxide1432(bulk) in the s-channel structure, a large amount of current can flow between a source and a drain of a transistor, increasing the on-state current of the transistor.

The s-channel structure, because of its high on-state current, is suitable for a semiconductor device which requires a miniaturized transistor, such as a large-scale integrated (LSI) circuit. A semiconductor device including the miniaturized transistor can have a high integration degree and high density.

In the transistor1400a, a region serving as a gate electrode is formed so as to fill an opening1415formed in the insulating film1405or the like, that is, in a self-aligned manner.

As illustrated inFIG. 13B, the conductive films1411and1422have a region where they overlap with each other with the insulating film positioned therebetween. The conductive films1411and1424also have a region where they overlap with each other with the insulating film positioned therebetween. These regions serve as the parasitic capacitance caused between the gate electrode and the source or drain electrode and might decrease the operating speed of the transistor1400a. This parasitic capacitance can be reduced by providing the insulating film1405in the transistor1400a. The insulating film1405preferably contains a material with a low relative dielectric constant.

FIG. 14Ais an enlarged view of the center of the transistor1400a. InFIG. 14A, a width LGdenotes the length of the bottom surface of the conductive film1411, which faces and lies parallel to the top surface of the metal oxide1432with the insulating film1406and the metal oxide1433positioned therebetween. The width LGis the line width of the gate electrode. InFIG. 14A, a width LSDdenotes the length between the conductive films1421and1423, i.e., the length between the source electrode and the drain electrode.

The width LSDis generally determined by the minimum feature size. As illustrated inFIG. 14A, the width LGis narrower than the width LSD. This means that in the transistor1400a, the line width of the gate electrode can be made narrower than the minimum feature size; specifically, the width LGcan be greater than or equal to 5 nm and less than or equal to 60 nm, preferably greater than or equal to 5 nm and less than or equal to 30 nm.

InFIG. 14A, a height HSDdenotes the total thickness of the conductive films1421and1422, or the total thickness of the conductive films1423and1424.

The thickness of the insulating film1406is preferably less than or equal to the height HSD, in which case the electric field of the gate electrode can be applied to the entire channel formation region. The thickness of the insulating film1406is less than or equal to 30 nm, preferably less than or equal to 10 nm.

The parasitic capacitance between the conductive films1422and1411and the parasitic capacitance between the conductive films1424and1411are inversely proportional to the thickness of the insulating film1405. For example, the thickness of the insulating film1405is preferably three or more times, and further preferably five or more times the thickness of the insulating film1406, in which case the parasitic capacitance is negligibly small. As a result, the transistor1400acan operate at high frequencies.

Components of the transistor1400awill be described below.

First, a metal oxide that can be used as the metal oxides1431to1433will be described.

In the transistor1400a, it is preferable that current flowing between a source and a drain in an off state (off-state current) be low. Examples of the transistor with a low off-state current include a transistor including an oxide semiconductor in a channel formation region.

The metal oxide1432is an oxide semiconductor containing indium (In), for example. The metal oxide1432can have high carrier mobility (electron mobility) by containing indium, for example. The metal oxide1432preferably contains an element M. The element M is preferably aluminum (A1), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements that can be used as the element M are boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), and the like. Note that two or more of these elements may be used in combination as the element M. The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium, for example. The element M is an element that can increase the energy gap of the metal oxide, for example. Furthermore, the metal oxide1432preferably contains zinc (Zn). When containing zinc, the metal oxide is easily crystallized in some cases.

Note that the metal oxide1432is not limited to the oxide semiconductor containing indium. The metal oxide1432may be an oxide semiconductor that does not contain indium and contains at least one of zinc, gallium, and tin (e.g., a zinc tin oxide or a gallium tin oxide).

For the metal oxide1432, an oxide semiconductor with a wide energy gap is used, for example. The energy gap of the metal oxide1432is, for example, greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, more preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.

The metal oxide1432is preferably a CAAC-OS film which is described later.

The metal oxides1431and1433include, for example, one or more, or two or more, elements other than oxygen included in the metal oxide1432. Since the metal oxides1431and1433include one or more, or two or more, elements other than oxygen included in the metal oxide1432, an interface state is less likely to be formed at an interface between the metal oxides1431and1432and an interface between the metal oxides1432and1433.

In the case of using an In-M-Zn oxide as the metal oxide1431, when the total proportion of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be lower than 50 atomic % and higher than 50 atomic %, respectively, more preferably lower than 25 atomic % and higher than 75 atomic %, respectively. When the metal oxide1431is formed by a sputtering method, a sputtering target with the above composition is preferably used. For example, In:M:Zn is preferably 1:3:2 or 1:3:4.

In the case of using an In-M-Zn oxide as the metal oxide1432, when the total proportion of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be higher than 25 atomic % and lower than 75 atomic %, respectively, more preferably higher than 34 atomic % and lower than 66 atomic %, respectively. When the metal oxide1432is formed by a sputtering method, a sputtering target with the above composition is preferably used. For example, In:M:Zn is preferably 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, or 4:2:4.1. In particular, when a sputtering target with an atomic ratio of In to Ga and Zn of 4:2:4.1 is used, the atomic ratio of In to Ga and Zn in the metal oxide1432may be 4:2:3 or in the neighborhood of 4:2:3.

In the case of using an In-M-Zn oxide as the metal oxide1433, when the total proportion of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be lower than 50 atomic % and higher than 50 atomic %, respectively, more preferably lower than 25 atomic % and higher than 75 atomic %, respectively. For example, In:M:Zn is preferably 1:3:2 or 1:3:4. The metal oxide1433may be a metal oxide that is the same type as that of the metal oxide1431.

The metal oxide1431or the metal oxide1433does not necessarily contain indium in some cases. For example, the metal oxide1431or the metal oxide1433may be gallium oxide.

The function and effect of the metal oxide1430, which includes a stack of the metal oxides1431to1433, are described with reference to the energy band diagram ofFIG. 14B.FIG. 14Bshows an energy band structure of a portion taken along dashed line Y1-Y2inFIG. 14A, that is, the energy band structure of a channel formation region of the transistor1400aand the vicinity thereof.

InFIG. 14B, Ec1404, Ec1431, Ec1432, Ec1433, and Ec1406indicate the energies at the bottoms of the conduction bands of the insulating film1404, the metal oxide1431, the metal oxide1432, the metal oxide1433, and the insulating film1406, respectively.

Here, a difference in energy between the vacuum level and the bottom of the conduction band (the difference is also referred to as electron affinity) corresponds to a value obtained by subtracting an energy gap from a difference in energy between the vacuum level and the top of the valence band (the difference is also referred to as an ionization potential). Note that the energy gap can be measured using a spectroscopic ellipsometer. The energy difference between the vacuum level and the top of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) device.

Since the insulating films1404and1406are insulators, Ec1406and Ec1404are closer to the vacuum level (i.e., have a lower electron affinity) than Ec1431, Ec1432, and Ec1433.

The metal oxide1432is a metal oxide having an electron affinity higher than those of the metal oxides1431and1433. For example, as the metal oxide1432, a metal oxide having an electron affinity higher than those of the metal oxides1431and1433by greater than or equal to 0.07 eV and less than or equal to 1.3 eV, preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV is used. Note that the electron affinity refers to an energy difference between the vacuum level and the bottom of the conduction band.

An indium gallium oxide has a small electron affinity and a high oxygen-blocking property. Therefore, the metal oxide1433preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, more preferably higher than or equal to 90%.

At this time, when gate voltage is applied, a channel is formed in the metal oxide1432having the highest electron affinity among the metal oxides1431to1433.

At this time, electrons move mainly in the metal oxide1432, not in the metal oxides1431and1433. Hence, the on-state current of the transistor hardly varies even when the density of interface states, which inhibit electron movement, is high at the interface between the metal oxide1431and the insulating film1404or at the interface between the metal oxide1433and the insulating film1406. The metal oxides1431and1433function as an insulating film.

In some cases, there is a mixed region of the metal oxides1431and1432between the metal oxides1431and1432. In some cases, there is a mixed region of the metal oxides1432and1433between the metal oxides1432and1433. Because the mixed region has a low interface state density, a stack of the metal oxides1431to1433has a band structure where energy at each interface and in the vicinity of the interface is changed continuously (continuous junction).

As described above, the interface between the metal oxides1431and1432or the interface between the metal oxides1432and1433has a low interface state density. Hence, electron movement in the metal oxide1432is less likely to be inhibited and the on-state current of the transistor can be increased.

Electron movement in the transistor is inhibited, for example, in the case where physical surface unevenness in a channel formation region is large. To increase the on-state current of the transistor, for example, the root mean square (RMS) roughness in a measurement area of 1 μm×1 μm of a top surface or a bottom surface of the metal oxide1432(a formation surface; here, the top surface of the metal oxide1431) is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, still more preferably less than 0.4 nm. The average surface roughness (Ra) in the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, still more preferably less than 0.4 nm. The maximum peak-to-valley height (P-V) in the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, still more preferably less than 7 nm. The RMS roughness, Ra, and P-V can be measured with, for example, a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc.

The electron movement is also inhibited in the case where the density of defect states is high in the channel formation region. For example, in the case where the metal oxide1432contains oxygen vacancies (also denoted by VO), donor levels are formed by entry of hydrogen into sites of oxygen vacancies in some cases. A state in which hydrogen enters sites of oxygen vacancies is denoted by VOH in the following description in some cases. VOH is a factor of decreasing the on-state current of the transistor because VOH scatters electrons. Note that sites of oxygen vacancies become more stable by entry of oxygen than by entry of hydrogen. Thus, by decreasing oxygen vacancies in the metal oxide1432, the on-state current of the transistor can be increased in some cases.

For example, at a certain depth in the metal oxide1432or in a certain region of the metal oxide1432, the concentration of hydrogen measured by secondary ion mass spectrometry (SIMS) is set to be higher than or equal to 1×1016atoms/cm3and lower than or equal to 2×1020atoms/cm3, preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1019atoms/cm3, more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 1×1019atoms/cm3, still more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1018atoms/cm3.

To decrease oxygen vacancies in the metal oxide1432, for example, there is a method in which excess oxygen contained in the insulating film1404is moved to the metal oxide1432through the metal oxide1431. In that case, the metal oxide1431is preferably a layer having oxygen permeability (a layer through which oxygen can pass or permeate).

Note that in the case where the transistor has an s-channel structure, a channel is formed in the entire metal oxide1432. Therefore, as the metal oxide1432has a larger thickness, a channel region becomes larger. In other words, the thicker the metal oxide1432is, the larger the on-state current of the transistor is.

Moreover, the thickness of the metal oxide1433is preferably as small as possible to increase the on-state current of the transistor. For example, the metal oxide1433has a region with a thickness of less than 10 nm, preferably less than or equal to 5 nm, more preferably less than or equal to 3 nm. Meanwhile, the metal oxide1433has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the metal oxide1432where a channel is formed. Thus, the metal oxide1433preferably has a certain thickness. For example, the metal oxide1433may have a region with a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm and further preferably greater than or equal to 2 nm. The metal oxide1433preferably has an oxygen blocking property to inhibit outward diffusion of oxygen released from the insulating film1404and the like.

To improve reliability, preferably, the thickness of the metal oxide1431is large and the thickness of the metal oxide1433is small. For example, the metal oxide1431has a region with a thickness of greater than or equal to 10 nm, preferably greater than or equal to 20 nm, more preferably greater than or equal to 40 nm, still more preferably greater than or equal to 60 nm. An increase in the thickness of the metal oxide1431can increase the distance from the interface between the adjacent insulator and the metal oxide1431to the metal oxide1432where a channel is formed. Note that the metal oxide1431has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, more preferably less than or equal to 80 nm, otherwise the productivity of the semiconductor device might be decreased.

For example, a region in which the concentration of silicon is higher than or equal to 1×1016atoms/cm3and lower than 1×1019atoms/cm3is provided between the metal oxides1432and1431. The concentration of silicon is preferably higher than or equal to 1×1016atoms/cm3and lower than 5×1018atoms/cm3, more preferably higher than or equal to 1×1016atoms/cm3and lower than 2×1018atoms/cm3. A region in which the concentration of silicon is higher than or equal to 1×1016atoms/cm3and lower than 1×1019atoms/cm3is provided between the metal oxides1432and1433. The concentration of silicon is preferably higher than or equal to 1×1016atoms/cm3and lower than 5×1018atoms/cm3, more preferably higher than or equal to 1×1016atoms/cm3and lower than 2×1018atoms/cm3. The concentration of silicon can be measured by SIMS.

It is preferable to reduce the concentration of hydrogen in the metal oxides1431and1433in order to reduce the concentration of hydrogen in the metal oxide1432. The metal oxides1431and1433each have a region in which the concentration of hydrogen is higher than or equal to 1×1016atoms/cm3and lower than or equal to 2×1020atoms/cm3. The concentration of hydrogen is preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1019atoms/cm3, more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 1×1019atoms/cm3, still more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1018atoms/cm3. The concentration of hydrogen can be measured by SIMS. It is also preferable to reduce the concentration of nitrogen in the metal oxides1431and1433in order to reduce the concentration of nitrogen in the metal oxide1432. The metal oxides1431and1433each have a region in which the concentration of nitrogen is higher than or equal to 1×1016atoms/cm3and lower than 5×1019atoms/cm3. The concentration of nitrogen is preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1018atoms/cm3, more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 1×1018atoms/cm3, still more preferably higher than or equal to 1×1016atoms/cm3and lower than or equal to 5×1017atoms/cm3. The concentration of nitrogen can be measured by SIMS.

The metal oxides1431to1433may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

After the metal oxides1431and1432are formed, first heat treatment is preferably performed. The first heat treatment can be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C., further preferably higher than or equal to 520° C. and lower than or equal to 570° C. The first heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under a reduced pressure. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for desorbed oxygen. The crystallinity of the metal oxides1431and1432can be increased by the first heat treatment. Furthermore, impurities such as hydrogen and water can be removed by the first heat treatment.

The above three-layer structure is an example. For example, a two-layer structure without the metal oxide1431or1433may be employed. Alternatively, the metal oxide given as an example of the metal oxides1431to1433may be provided over or under the metal oxide1431or over or under the metal oxide1433, i.e., a four-layer structure may be employed. Further alternatively, an n-layer structure (n is an integer of 5 or more) in which the metal oxide given as an example of the metal oxides1431to1433is provided at two or more of the following positions may be employed: over the metal oxide1431, under the metal oxide1431, over the metal oxide1433, and under the metal oxide1433.

As the substrate1450, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like, and a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a silicon on insulator (SOI) substrate in which an insulating region is provided in the above semiconductor substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. A substrate including a metal nitride, a substrate including a metal oxide, or the like can also be used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be used. Alternatively, any of these substrates over which an element is provided may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

A flexible substrate may be used as the substrate1450. As a method for providing a transistor over a flexible substrate, there is a method in which a transistor is formed over a non-flexible substrate, and then the transistor is separated and transferred to the substrate1450that is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate1450, a sheet, a film, or foil containing a fiber may be used. The substrate1450may have elasticity. The substrate1450may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate1450may have a property of not returning to its original shape. The thickness of the substrate1450is, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, more preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate1450has small thickness, the weight of the semiconductor device can be reduced. When the substrate1450has small thickness, even in the case of using glass or the like, the substrate1450may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate1450, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.

For the flexible substrate1450, a metal, an alloy, a resin, glass, or fiber thereof can be used, for example. The flexible substrate1450preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate1450is preferably formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10−3/K, lower than or equal to 5×10−5/K, or lower than or equal to 1×10−5/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, aramid is preferably used as the material of the flexible substrate1450because of its low coefficient of linear expansion.

The insulating film1401has a function of electrically isolating the substrate1450from the conductive film1414.

The insulating film1401or1402is formed using an insulating film having a single-layer structure or a layered structure. Examples of the material of the insulating film include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Note that in this specification, an oxynitride refers to a compound that contains more oxygen than nitrogen, and a nitride oxide refers to a compound that contains more nitrogen than oxygen.

The insulating film1402may be formed using silicon oxide with high step coverage which is formed by reacting tetraethyl orthosilicate (TEOS), silane, or the like with oxygen, nitrous oxide, or the like.

After the insulating film1402is formed, the insulating film1402may be subjected to planarization treatment using a CMP method or the like to improve the planarity of the top surface thereof.

The insulating film1404preferably contains an oxide. In particular, the insulating film1404preferably contains an oxide material from which part of oxygen is released by heating. The insulating film1404preferably contains an oxide containing oxygen more than that in the stoichiometric composition. Part of oxygen is released by heating from an oxide film containing oxygen more than that in the stoichiometric composition. Oxygen released from the insulating film1404is supplied to the metal oxide1430, so that oxygen vacancies in the metal oxide1430can be reduced. Consequently, changes in the electrical characteristics of the transistor can be reduced and the reliability of the transistor can be improved.

The oxide film containing oxygen more than that in the stoichiometric composition is an oxide film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 3.0×1020atoms/cm3in thermal desorption spectroscopy (TDS) analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C.

The insulating film1404preferably contains an oxide that can supply oxygen to the metal oxide1430. For example, a material containing silicon oxide or silicon oxynitride is preferably used.

Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride may be used for the insulating film1404.

To make the insulating film1404contain excess oxygen, the insulating film1404is formed in an oxygen atmosphere, for example. Alternatively, a region containing excess oxygen may be formed by introducing oxygen into the insulating film1404that has been formed. Both the methods may be combined.

For example, oxygen (at least including any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the insulating film1404that has been formed, so that a region containing excess oxygen is formed. Oxygen can be introduced by, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like.

A gas containing oxygen can be used for oxygen introducing treatment. Examples of the gas containing oxygen include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and carbon monoxide. Furthermore, a rare gas may be included in the gas containing oxygen for the oxygen introducing treatment. Moreover, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

After the insulating film1404is formed, the insulating film1404may be subjected to planarization treatment using a CMP method or the like to improve the planarity of the top surface thereof.

The insulating film1403has a passivation function of preventing oxygen contained in the insulating film1404from decreasing by bonding to metal contained in the conductive film1414.

The insulating film1403has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. Providing the insulating film1403can prevent outward diffusion of oxygen from the metal oxide1430and entry of hydrogen, water, or the like into the metal oxide1430from the outside.

The insulating film1403can be, for example, a nitride insulating film. The nitride insulating film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. Note that instead of the nitride insulating film, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film.

The threshold voltage of the transistor1400acan be controlled by injecting electrons into a charge trap layer. The charge trap layer is preferably provided in the insulating film1402or the insulating film1403. For example, when the insulating film1403is formed using hafnium oxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like, the insulating film1403can function as a charge trap layer.

The conductive films1411to1414each preferably have a single-layer structure or a layered structure of a conductive film containing a low-resistance material selected from copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), and strontium (Sr), an alloy of such a low-resistance material, or a compound containing such a material as its main component. It is particularly preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum. In addition, the conductive film is preferably formed using a low-resistance conductive material such as aluminum or copper. The conductive film is more preferably formed using a Cu—Mn alloy, in which case manganese oxide formed at the interface with an insulator containing oxygen has a function of preventing Cu diffusion.

[Source Electrode and Drain Electrode]

The conductive films1421to1424each preferably have a single-layer structure or a layered structure of a conductive film containing a low-resistance material selected from copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), and strontium (Sr), an alloy of such a low-resistance material, or a compound containing such a material as its main component. It is particularly preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum. In addition, the conductive film is preferably formed using a low-resistance conductive material such as aluminum or copper. The conductive film is more preferably formed using a Cu—Mn alloy, in which case manganese oxide formed at the interface with an insulator containing oxygen has a function of preventing Cu diffusion.

The conductive films1421to1424are preferably formed using a conductive oxide including noble metal, such as iridium oxide, ruthenium oxide, or strontium ruthenate. Such a conductive oxide hardly takes oxygen from an oxide semiconductor even when it is in contact with the oxide semiconductor and hardly generates oxygen vacancies in the oxide semiconductor.

The regions1441and1442are formed when, for example, the conductive films1421and1423extract oxygen from the metal oxides1431and1432. Oxygen is more likely to be extracted at higher temperatures. Oxygen vacancies are formed in the regions1441and1442through several heating steps in the manufacturing process of the transistor. In addition, hydrogen enters sites of the oxygen vacancies by heating, increasing the carrier density in the regions1441and1442. As a result, the resistance of the regions1441and1442is reduced.

The insulating film1406preferably contains an insulator with a high relative dielectric constant. For example, the insulating film1406preferably contains gallium oxide, hafnium oxide, an oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, or oxynitride containing silicon and hafnium.

The insulating film1406preferably has a layered structure containing silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Because silicon oxide and silicon oxynitride have thermal stability, a combination of silicon oxide or silicon oxynitride with an insulator with a high relative dielectric constant allows the layered structure to be thermally stable and have a high relative dielectric constant. For example, when aluminum oxide, gallium oxide, or hafnium oxide is on the metal oxide1433side, entry of silicon from silicon oxide or silicon oxynitride into the metal oxide1432can be suppressed.

When silicon oxide or silicon oxynitride is on the metal oxide1433side, for example, trap centers might be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap centers can shift the threshold voltage of the transistor in the positive direction by trapping electrons in some cases.

[Interlayer Insulating Film and Protective Insulating Film]

The insulating film1405preferably contains an insulator with a low relative dielectric constant. For example, the insulating film1405preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or a resin. Alternatively, the insulating film1405preferably has a layered structure containing silicon oxide or silicon oxynitride and a resin. Because silicon oxide and silicon oxynitride have thermal stability, combination of silicon oxide or silicon oxynitride with a resin allows the layered structure to be thermally stable and have a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

The insulating film1407has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. Providing the insulating film1407can prevent outward diffusion of oxygen from the metal oxide1430and entry of hydrogen, water, or the like into the metal oxide1430from the outside.

The insulating film1407can be, for example, a nitride insulating film. The nitride insulating film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. Note that instead of the nitride insulating film, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of the oxide insulating film include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film.

An aluminum oxide film is preferably used as the insulating film1407because it is highly effective in preventing permeation of both oxygen and impurities such as hydrogen and moisture.

When the insulating film1407is formed using plasma containing oxygen by a sputtering method, a CVD method, or the like, oxygen can be added to side and top surfaces of the insulating films1405and1406. It is preferable to perform second heat treatment at any time after the formation of the insulating film1407. Through the second heat treatment, oxygen added to the insulating films1405and1406is diffused through the insulating films to reach the metal oxide1430, whereby oxygen vacancies in the metal oxide1430can be reduced.

In schematic views ofFIGS. 15A and 15B, oxygen added to the insulating films1405and1406in the formation of the insulating film1407is diffused through the insulating films by the second heat treatment and reaches the metal oxide1430. InFIG. 15A, oxygen diffusion in the cross-sectional view ofFIG. 13Bis indicated by arrows. InFIG. 15B, oxygen diffusion in the cross-sectional view ofFIG. 13Cis indicated by arrows.

As illustrated inFIGS. 15A and 15B, oxygen added to the side surface of the insulating film1406is diffused in the insulating film1406and reaches the metal oxide1430. In addition, a region1461, a region1462, and a region1463each containing excess oxygen are sometimes formed in the vicinity of the interface between the insulating films1407and1405. Oxygen contained in the regions1461to1463reaches the metal oxide1430through the insulating films1405and1404. In the case where the insulating film1405includes silicon oxide and the insulating film1407includes aluminum oxide, a mixed layer of silicon, aluminum, and oxygen is formed in the regions1461to1463in some cases.

The insulating film1407has a function of blocking oxygen and prevents oxygen from being diffused upward across the insulating film1407. The insulating film1403also has a function of blocking oxygen and prevents oxygen from being diffused downward across the insulating film1403.

Note that the second heat treatment may be performed at a temperature that allows oxygen added to the insulating films1405and1406to be diffused to the metal oxide1430. For example, the description of the first heat treatment may be referred to for the second heat treatment. Alternatively, the temperature of the second heat treatment is preferably lower than that of the first heat treatment. The second heat treatment is preferably performed at a temperature lower than that of the first heat treatment by higher than or equal to 20° C. and lower than or equal to 150° C., preferably higher than or equal to 40° C. and lower than or equal to 100° C. Accordingly, superfluous release of oxygen from the insulating film1404can be inhibited. Note that the second heat treatment is not necessarily performed when heating during formation of the films can work as heat treatment comparable to the second heat treatment.

As described above, oxygen can be supplied to the metal oxide1430from above and below by the formation of the insulating film1407and the second heat treatment.

Alternatively, oxygen can be added to the insulating films1405and1406by forming a film containing indium oxide, e.g., an In-M-Zn oxide, as the insulating film1407.

The insulating film1408can be formed using an insulator including one or more kinds of materials selected from aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Alternatively, for the insulating film1408, a resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used. The insulating film1408may be a stack including any of the above materials.

The conductive film1414and the insulating films1402and1403can be omitted in the transistor1400aillustrated inFIGS. 13A to 13C. An example of such a structure is illustrated inFIGS. 16A to 16C.

FIGS. 16A to 16Care a top view and cross-sectional views of a transistor1400b.FIG. 16Ais a top view.FIG. 16Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 16A, andFIG. 16Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 16A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG. 16A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction of the transistor1400band a channel width direction of the transistor1400b, respectively.

In the transistor1400aillustrated inFIGS. 13A to 13C, parts of the conductive films1421and1423that overlap with the gate electrode (the conductive films1411to1413) can be reduced in thickness. An example of such a structure is illustrated inFIGS. 17A to 17C.

FIGS. 17A to 17Care a top view and cross-sectional views of a transistor1400c.FIG. 17Ais a top view.FIG. 17Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 17A, andFIG. 17Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 17A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG. 17A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction of the transistor1400cand a channel width direction of the transistor1400c, respectively.

In the transistor1400cillustrated inFIG. 17B, part of the conductive film1421that overlaps with the gate electrode is reduced in thickness, and the conductive film1422covers the conductive film1421. Part of the conductive film1423that overlaps with the gate electrode is also reduced in thickness, and the conductive film1424covers the conductive film1423.

The transistor1400c, which has the structure illustrated inFIG. 17B, can have an increased distance between the gate and source electrodes or between the gate and drain electrodes. This results in a reduction in the parasitic capacitance formed between the gate electrode and the source and drain electrodes. As a result, a transistor capable of high-speed operation can be obtained.

In the transistor1400cillustrated inFIGS. 17A to 17C, the width of the metal oxides1431and1432can be increased in the A3-A4direction. An example of such a structure is illustrated inFIGS. 18A to 18C.

FIGS. 18A to 18Care a top view and cross-sectional views of a transistor1400d.FIG. 18Ais a top view.FIG. 18Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 18A, andFIG. 18Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 18A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG. 18A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction of the transistor1400dand a channel width direction of the transistor1400d, respectively.

The transistor1400d, which has the structure illustrated inFIGS. 18A to 18C, can have an increased on-state current.

In the transistor1400cillustrated inFIGS. 17A to 17C, a plurality of regions (hereinafter referred to as fins) consisting of the metal oxides1431and1432may be provided in the A3-A4direction. An example of such a structure is illustrated inFIGS. 19A to 19C.

FIGS. 19A to 19Care a top view and cross-sectional views of a transistor1400e.FIG. 19Ais a top view.FIG. 19Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 19A, andFIG. 19Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 19A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG. 19A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction of the transistor1400eand a channel width direction of the transistor1400e, respectively.

The transistor1400eincludes a first fin consisting of metal oxides1431aand1432a, a second fin consisting of metal oxides1431band1432b, and a third fin consisting of metal oxides1431cand1432c.

In the transistor1400e, the metal oxides1432ato1432cwhere a channel is formed are surrounded by the gate electrode. Hence, a gate electric field can be applied to the entire channel, so that a transistor with a high on-state current can be obtained.

FIGS. 20A to 20Dare a top view and cross-sectional views of a transistor1400fFIG. 20Ais a top view of the transistor1400fFIG. 20Bis a cross-sectional view taken along dashed-dotted line A1-A2inFIG. 20A, andFIG. 20Cis a cross-sectional view taken along dashed-dotted line A3-A4inFIG. 20A. Note that the dashed-dotted line A1-A2and the dashed-dotted line A3-A4are sometimes referred to as a channel length direction and a channel width direction, respectively. The transistor1400fhas the s-channel structure like the transistor1400aand the like. In the transistor1400f, an insulating film1409is provided in contact with the side surface of the conductive film1412used as a gate electrode. The insulating film1409and the conductive film1412are covered with the insulating film1407. The insulating film1409serves as a sidewall insulator of the transistor1400fAs in the transistor1400a, the gate electrode may be a stack of the conductive films1411to1413.

The insulating film1406and the conductive film1412overlap with the conductive film1414and the metal oxide1432at least partly. The side edge of the conductive film1412in the channel length direction is preferably approximately aligned with the side edge of the insulating film1406in the channel length direction. Here, the insulating film1406serves as a gate insulating film of the transistor1400f, the conductive film1412serves as a gate electrode of the transistor1400f, and the insulating film1409serves as a sidewall insulating film of the transistor1400f.

The metal oxide1432has a region where it overlaps with the conductive film1412with the metal oxide1433and the insulating film1406positioned therebetween. Preferably, the outer edge of the metal oxide1431is approximately aligned with the outer edge of the metal oxide1432, and the outer edge of the metal oxide1433is outside of the outer edges of the metal oxides1431and1432. However, the shape of the transistor in this example is not limited to the one in which the outer edge of the metal oxide1433is outside of the outer edge of the metal oxide1431. For example, the outer edge of the metal oxide1431may be outside of the outer edge of the metal oxide1433, or the side edge of the metal oxide1431may be approximately aligned with the side edge of the metal oxide1433.

FIG. 20Dis an enlarged view of part ofFIG. 20B. As illustrated inFIG. 20D, regions1461ato1461eare formed in the metal oxide1430. The regions1461bto1461ehave a higher concentration of dopant and therefore have a lower resistance than the region1461a. Furthermore, the regions1461band1461chave a higher concentration of hydrogen and therefore have a much lower resistance than the regions1461dand1461e. The concentration of a dopant in the region1461ais, for example, less than or equal to 5%, less than or equal to 2%, or less than or equal to 1% of the maximum concentration of a dopant in the region1461bor1461c. Instead of the term “dopant,” the term “donor,” “acceptor,” “impurity,” or “element” may be used.

As illustrated inFIG. 20D, the region1461ais a region substantially overlapping with the conductive film1412, and the region1461b, the region1461c, the region1461d, and the region1461eare regions except the region1461ain the metal oxide1430. In the regions1461band1461c, the top surface of the metal oxide1433is in contact with the insulating film1407. In the regions1461dand1461e, the top surface of the metal oxide1433is in contact with the insulating film1409or the insulating film1406. Thus, as illustrated inFIG. 20D, the boundary between the region1461band the region1461doverlaps with the boundary between the insulating film1407and the side edge of the insulating film1409. The same applies to the boundary between the regions1461cand1461e. It is preferable that the region1461dand the region1461epartly overlap with a region (channel formation region) in which the metal oxide1432overlaps with the conductive film1412. For example, the side edges of the region1461dand the region1461ein the channel length direction are preferably positioned inward from the side edge of the conductive film1412by a distance d. In that case, the thickness t406of the insulating film1406and the distance d preferably satisfy 0.25t406<d<t406.

As described above, the region1461dand the region1461eare partly formed in a region in which the metal oxide1430overlaps with the conductive film1412. Accordingly, the channel formation region of the transistor1400fis in contact with the regions1461dand1461ehaving low resistance, and thus, high-resistance offset regions are not formed between the region1461aand the regions1461dand1461e. As a result, the on-state current of the transistor1400fcan be increased. Furthermore, since the side edges of the regions1461dand1461ein the channel length direction are formed so as to satisfy the above range, the regions1461dand1461ecan be prevented from being formed too deeply in the channel formation region and always conductive.

The region1461b, the region1461c, the region1461d, and the region1461eare formed by ion doping treatment such as an ion implantation method. Therefore, as illustrated inFIG. 20D, the positions of the side edges of the regions1461dand1461ein the channel length direction are sometimes shifted to the side edge of the metal oxide1430in the channel length direction in a deeper area from the top surface of the metal oxide1433. The distance d in that case is the distance between the side edge of the conductive film1412in the channel length direction and each of the side edges of the regions1461dand1461ethat are closest to the inner part of the conductive film1412.

In some cases, for example, the regions1461dand1461ein the metal oxide1431do not overlap with the conductive film1412. In that case, at least part of the regions1461dand1461ein the metal oxide1431or1432is preferably formed in a region overlapping with the conductive film1412.

In addition, low-resistance regions1451and1452are preferably formed in the metal oxide1431, the metal oxide1432, and the metal oxide1433in the vicinity of the interface with the insulating film1407. The low-resistance regions1451and1452contain at least one of elements included in the insulating film1407. It is preferable that the low-resistance region1451and the low-resistance region1452be partly and substantially in contact with a region (channel formation region) of the metal oxide1432overlapping with the conductive film1412or partly overlap with the region.

Since a large region of the metal oxide1433is in contact with the insulating film1407, the low-resistance region1451and the low-resistance region1452are likely to be formed in the metal oxide1433. The concentration of the element contained in the insulating film1407is higher in the low-resistance region1451and the low-resistance region1452included in the metal oxide1433than in a region of the metal oxide1433other than the low-resistance region1451and the low-resistance region1452(e.g., a region of the metal oxide1433overlapping with the conductive film1412).

The low-resistance region1451is formed in the region1461b, and the low-resistance region1452is formed in the region1461c. Ideally, the metal oxide1430has a structure in which the concentration of an added element is the highest in the low-resistance regions1451and1452, the second highest in the regions1461band1461cto1461eother than the low-resistance regions1451and1452, and the lowest in the region1461a. The added element refers to a dopant for forming the regions1461band1461cand an element added from the insulating film1407to the low-resistance regions1451and1452.

Although the low-resistance regions1451and1452are formed in the transistor1400f, the semiconductor device shown in this embodiment is not limited to this structure. For example, the low-resistance regions1451and1452are not necessarily formed in the case where the regions1461band1461chave a sufficiently low resistance.

FIGS. 21A and 21Bare a top view and a cross-sectional view of a transistor1680.FIG. 21Ais a top view, andFIG. 21Bis a cross-sectional view taken along dashed-dotted line A-B inFIG. 21A. Note that for simplification of the drawings, some components are increased or reduced in size, or omitted inFIGS. 21A and 21B. Note that the direction of the dashed-dotted line A-B is sometimes referred to as a channel length direction.

The transistor1680illustrated inFIG. 21Bincludes a conductive film1689serving as a first gate, a conductive film1688serving as a second gate, a semiconductor1682, a conductive film1683and a conductive film1684serving as a source and a drain, an insulating film1681, an insulating film1685, an insulating film1686, and an insulating film1687.

The conductive film1689is on an insulating surface. The conductive film1689overlaps with the semiconductor1682with the insulating film1681provided therebetween. The conductive film1688overlaps with the semiconductor1682with the insulating films1685,1686, and1687provided therebetween. The conductive films1683and1684are connected to the semiconductor1682.

The description of the conductive films1411to1414inFIGS. 13A to 13Ccan be referred to for the details of the conductive films1689and1688.

The conductive films1689and1688may be supplied with different potentials, or may be supplied with the same potential at the same time. The conductive film1688serving as a second gate electrode in the transistor1680leads to stabilization of threshold voltage. Note that the conductive film1688is unnecessary in some cases.

The description of the metal oxide1432inFIGS. 13A to 13Ccan be referred to for the details of the semiconductor1682. The semiconductor1682may be a single layer or a stack including a plurality of semiconductor layers.

The description of the conductive films1421to1424inFIGS. 13A to 13Ccan be referred to for the details of the conductive films1683and1684.

The description of the insulating film1406inFIGS. 13A to 13Ccan be referred to for the details of the insulating film1681.

The insulating films1685to1687are sequentially stacked over the semiconductor1682and the conductive films1683and1684inFIG. 21B; however, an insulating film provided over the semiconductor1682and the conductive films1683and1684may be a single layer or a stack including a plurality of insulating films.

In the case of using an oxide semiconductor as the semiconductor1682, the insulating film1686preferably contains oxygen at a proportion higher than or equal to that in the stoichiometric composition and has a function of supplying part of oxygen to the semiconductor1682by heating. Note that in the case where the provision of the insulating film1686directly on the semiconductor1682causes damage to the semiconductor1682at the time of formation of the insulating film1686, the insulating film1685is preferably provided between the semiconductor1682and the insulating film1686, as illustrated inFIG. 21B. The insulating film1685preferably allows oxygen to pass therethrough, and causes little damage to the semiconductor1682when the insulating film1685is formed compared with the case of the insulating film1686. If damage to the semiconductor1682can be reduced and the insulating film1686can be formed directly on the semiconductor1682, the insulating film1685is not necessarily provided.

For the insulating films1685and1686, a material containing silicon oxide or silicon oxynitride is preferably used, for example. Alternatively, a metal oxide such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used.

The insulating film1687preferably has a blocking effect of preventing diffusion of oxygen, hydrogen, and water. Alternatively, the insulating film1687preferably has a blocking effect of preventing diffusion of hydrogen and water.

As an insulating film has higher density and becomes denser or has a fewer dangling bonds and becomes more chemically stable, the insulating film has a more excellent blocking effect. An insulating film that has a blocking effect of preventing diffusion of oxygen, hydrogen, and water can be formed using, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride. An insulating film that has a blocking effect of preventing diffusion of hydrogen and water can be formed using, for example, silicon nitride or silicon nitride oxide.

In the case where the insulating film1687has a blocking effect of preventing diffusion of water, hydrogen, and the like, impurities such as water and hydrogen that exist in a resin in a panel or exist outside the panel can be prevented from entering the semiconductor1682. In the case where an oxide semiconductor is used as the semiconductor1682, part of water or hydrogen that enters the oxide semiconductor serves as an electron donor (donor). Thus, the use of the insulating film1687having the blocking effect can prevent a shift in the threshold voltage of the transistor1680due to generation of donors.

In addition, in the case where an oxide semiconductor is used as the semiconductor1682, the insulating film1687has a blocking effect of preventing diffusion of oxygen, so that diffusion of oxygen from the oxide semiconductor to the outside can be prevented. Accordingly, oxygen vacancies in the oxide semiconductor that serve as donors are reduced, so that a shift in the threshold voltage of the transistor1680due to generation of donors can be prevented.

In this embodiment, configuration examples of a device that can be applied to the semiconductor device10described in the above embodiment will be described with reference toFIGS. 22A and 22B,FIGS. 23A and 23B,FIGS. 24A and 24B, andFIGS. 25A and 25B.

FIGS. 22A and 22Bare partial cross-sectional views of the semiconductor device10.FIG. 22Aillustrates a cross section in a channel length direction of the transistor included in the memory cell21of the semiconductor device10.FIG. 22Billustrates a cross section in a channel width direction of the transistor included in the memory cell21of the semiconductor device10.

The layer L1includes a substrate1700, a transistor TrA formed using the substrate1700, an element isolation layer1701, and a plurality of conductors such as a conductor1710and a conductor1711.

The layer L2includes a plurality of wirings such as a wiring1730and a wiring1731.

The layer L3includes a plurality of conductors such as a conductor1712and a conductor1713and a plurality of wirings (not illustrated).

The layer L4includes an insulator1706, a transistor TrB, an insulator1702, an insulator1703, and a plurality of conductors such as a conductor1714and a conductor1715.

The layer L5includes a plurality of wirings such as a wiring1732and a wiring1733.

The layer L6includes a plurality of conductors such as a conductor1716.

The layer L7includes a transistor TrC, an insulator1704, an insulator1705, and a plurality of conductors such as a conductor1717.

The layer L8includes a plurality of wirings such as a wiring1734and a wiring1735.

The layer L9includes a plurality of conductors such as a conductor1718and a plurality of wirings (not illustrated).

The layer L10includes a plurality of wirings such as a wiring1736.

The layer L11includes a capacitor C1and a plurality of conductors such as a conductor1719. The capacitor C1includes a first electrode1751, a second electrode1752, and an insulator1753.

The layer L12includes a plurality of wirings such as a wiring1737.

The OS transistor described in Embodiment 4 is preferably used as the transistors TrB and TrC. InFIGS. 22A and 22B, the transistor1400cillustrated inFIGS. 17A to 17Cis used as the transistors TrB and TrC.

The transistor TrA is preferably formed using a semiconductor material different from that for the transistors TrB and TrC. InFIGS. 22A and 22B, a Si transistor is used as the transistor TrA.

The control circuit30and the read circuit40are preferably in the layer L1and the layer L2. The cell array20is preferably in the layers L4to L11. Note that the capacitor102included in the memory cell21may be provided in the layer L11, not in the layers L1and L2. In the case where the transistor110of the circuit31and the transistor120of the circuit41are OS transistors, these OS transistors may be provided in the layers L4to L7.

As the substrate1700, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, an SOI substrate, or the like can be used.

For example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, an attachment film, paper including a fibrous material, or a base film may be used as the substrate1700. Alternatively, a semiconductor element may be formed using one substrate, and then transferred to another substrate. InFIGS. 22A and 22B, as an example, a single crystal silicon wafer is used as the substrate1700.

The transistor TrA is described in detail with reference toFIGS. 24A and 24B.FIG. 24Ais a cross-sectional view of the transistor TrA in the channel length direction, andFIG. 24Bis a cross-sectional view of the transistor TrA in the channel width direction. The transistor TrA includes a channel formation region1793formed in a well1792, low-concentration impurity regions1794and high-concentration impurity regions1795(also collectively referred to as an impurity region simply), conductive regions1796provided in contact with the impurity region, a gate insulating film1797provided over the channel formation region1793, a gate electrode1790provided over the gate insulating film1797, and sidewall insulating layers1798and1799provided on side surfaces of the gate electrode1790. Note that the conductive regions1796can be formed using metal silicide or the like.

In the transistor TrA inFIG. 24B, the channel formation region1793has a projecting portion, and the gate insulating film1797and the gate electrode1790are provided along side and top surfaces of the channel formation region1793. The transistor with such a shape is referred to as a FIN-type transistor. Although the projecting portion is formed by processing part of the semiconductor substrate in this embodiment, a semiconductor layer with a projecting portion may be formed by processing an SOI substrate.

Note that the transistor TrA is not limited to the FIN-type transistor, and may be a planar-type transistor illustrated inFIGS. 25A and 25B.FIG. 25Ais a cross-sectional view of the transistor TrA in the channel length direction, andFIG. 25Bis a cross-sectional view of the transistor TrA in the channel width direction. The reference numerals inFIGS. 25A and 25Bare the same as those shown inFIGS. 24A and 24B.

InFIGS. 22A and 22B, the insulators1702to1706preferably have a blocking effect against hydrogen, water, and the like. Water, hydrogen, and the like are factors that generate carriers in an oxide semiconductor; thus, providing such a blocking layer against hydrogen, water, and the like can improve the reliability of the transistors TrB and TrC. Examples of insulators having a blocking effect against hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and yttria-stabilized zirconia (YSZ).

The wirings1730to1737and the conductors1710to1719each preferably have a single-layer structure or a layered structure of a conductive film containing a low-resistance material selected from copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), and cobalt (Co), an alloy of such a low-resistance material, or a compound containing such a material as its main component. It is particularly preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum. In addition, the conductive film is preferably formed using a low-resistance conductive material such as aluminum or copper. The conductive film is more preferably formed using a Cu—Mn alloy, in which case manganese oxide formed at the interface with an insulator containing oxygen has a function of preventing Cu diffusion.

InFIGS. 22A and 22B, regions without reference numerals and hatch patterns represent regions formed of an insulator. As the insulator, an insulator containing at least one of aluminum oxide, aluminum nitride oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and the like can be used. Alternatively, in the regions, an organic resin such as a polyimide resin, a polyamide resin, an acrylic resin, a siloxane resin, an epoxy resin, or a phenol resin can be used.

In the case where an OS transistor is used as the transistor101shown in the above embodiment, the transistor101is preferably formed in the layer L4or L7. In the case where memory cells21are stacked as illustrated inFIG. 8, the transistor101of one memory cell21may be formed in the layer L4and the transistor101of another memory cell21may be formed in the layer L7.

In the case where a Si transistor is used as the transistor110or120shown in the above embodiment, the transistor is preferably formed in the layer L1.

In the case where an OS transistor is used as the transistor110or120shown in the above embodiment, the transistor is preferably formed in the layer L4or L7.

The capacitor102shown in the above embodiment is preferably formed in the layer L11.

In the case where an OS transistor is used in a driver circuit in the periphery of the semiconductor device10, the OS transistor may be formed in the layer L4or L7.

In the case where a Si transistor is used in a driver circuit in the periphery of the semiconductor device10, the Si transistor may be formed in the layer L1.

With the structure illustrated inFIGS. 22A and 22B, the area occupied by the semiconductor device10can be reduced, leading to a higher level of integration of the memory cells.

In the case where the semiconductor device10described in the above embodiment has the structure ofFIGS. 22A and 22B, the numbers of the transistors (TrA, TrB, and TrC) and the capacitors (C1) are sometimes different from those shown inFIGS. 22A and 22B. In that case, the structure ofFIGS. 22A and 22Bcan be changed as appropriate; for example, the numbers of the layers L4, L7, and L11are increased or decreased, or an element is additionally provided in a layer.

All the OS transistors in the semiconductor device10may be formed in the same layer. An example of such a structure is illustrated inFIGS. 23A and 23B. LikeFIGS. 22A and 22B,FIG. 23Aillustrates a cross section in a channel length direction of the transistor included in the memory cell21of the semiconductor device10, andFIG. 23Billustrates a cross section in a channel width direction of the transistor included in the memory cell21of the semiconductor device10.

The cross-sectional views ofFIGS. 23A and 23Bare different from those ofFIGS. 22A and 22Bin that the layers L6to L8are omitted and the layer L9is formed on the layer L5. For the other details inFIGS. 23A and 23B, the description ofFIGS. 22A and 22Bis referred to.

The transistor101shown in the above embodiment is preferably formed in the layer L4.

In the case where a Si transistor is used as the transistor110or120shown in the above embodiment, the transistor is preferably formed in the layer L1.

In the case where an OS transistor is used as the transistor110or120described in the above embodiment, the transistor is preferably formed in the layer L4.

The capacitor102shown in the above embodiment is preferably formed in the layer L11.

In the case where a driver circuit in the periphery of the semiconductor device10is formed using an OS transistor, the OS transistor may be formed in the layer L4.

In the case where a driver circuit in the periphery of the semiconductor device10is formed using a Si transistor, the Si transistor may be formed in the layer L1.

With the structure illustrated inFIGS. 23A and 23B, the production process of the semiconductor device10can be simplified.

In the case where the semiconductor device10described in the above embodiment has the structure ofFIGS. 23A and 23B, the numbers of the transistors (TrA, TrB, and TrC) and the capacitors (C1) are sometimes different from those shown inFIGS. 23A and 23B. In that case, the structure ofFIGS. 23A and 23Bcan be changed as appropriate; for example, the numbers of the layers L4and L11are increased or decreased, or an element is additionally provided in a layer.

In this embodiment, the structure of an oxide semiconductor film that can be used for the OS transistor described in the above embodiment will be described.

An oxide semiconductor film is classified roughly into a non-single-crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of a CAAC-OS film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS film, which is obtained using a transmission electron microscope (TEM), a plurality of crystal parts can be observed. However, in the high-resolution TEM image, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the high-resolution cross-sectional TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface, metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflecting unevenness of a surface where the CAAC-OS film is formed (hereinafter, the surface where the CAAC-OS film is formed is also referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged parallel to the formation surface or the top surface of the CAAC-OS film.

When the CAAC-OS film with an InGaZnO4crystal is analyzed by an out-of-plane method, a peak may also be observed when 20 is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferable that in the CAAC-OS film, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.

The CAAC-OS film is an oxide semiconductor film having low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element that has higher bonding strength to oxygen than a metal element included in the oxide semiconductor film, such as silicon, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and causes a decrease in crystallinity. Furthermore, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film having a low density of defect states. In some cases, oxygen vacancies in the oxide semiconductor film serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.

The state in which the impurity concentration is low and the density of defect states is low (the number of oxygen vacancies is small) is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has little variation in electrical characteristics and high reliability. Electric charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released and might behave like fixed electric charge. Thus, the transistor including the oxide semiconductor film having high impurity concentration and a high density of defect states has unstable electrical characteristics in some cases.

With the use of the CAAC-OS film in an OS transistor, variation in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light is small.

Note that in this specification and the like, the expression “an oxide semiconductor is substantially highly purified intrinsic” refers to a state where an oxide semiconductor has a carrier density lower than 8×1011/cm3, preferably lower than 1×1011/cm3, and further preferably lower than 1×1010/cm3and higher than or equal to 1×10−9/cm3. A transistor in which a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is used for a channel formation region exhibits an extremely low off-state current. When a source-drain voltage is, for example, about 0.1 V, 5 V, or 10 V, the off-state current normalized by the channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.

A microcrystalline oxide semiconductor film has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. A microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm, is specifically referred to as nanocrystal (nc). An oxide semiconductor film including nanocrystal is referred to as an nc-OS film. In a high-resolution TEM image of the nc-OS film, for example, a grain boundary is not clearly observed in some cases.

In the nc-OS film, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different crystal parts in the nc-OS film. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than the size of a crystal part, a peak indicating a crystal plane does not appear. Further, a diffraction pattern like a halo pattern appears in a selected-area electron diffraction pattern of the nc-OS film which is obtained by using an electron beam having a probe diameter (e.g., larger than or equal to 50 nm) larger than the diameter of a crystal part. Meanwhile, spots are shown in a nanobeam electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter close to or smaller than the size of a crystal part. Furthermore, in a nanobeam electron diffraction pattern of the nc-OS film, regions with high luminance in a circular (ring) pattern are shown in some cases. Moreover, in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are shown in a ring-like region in some cases.

The nc-OS film is an oxide semiconductor film that has high regularity as compared with an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

The amorphous oxide semiconductor film has disordered atomic arrangement and no crystal part. For example, the amorphous oxide semiconductor film does not have a specific state as in quartz.

In a high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found. When the amorphous oxide semiconductor film is subjected to structural analysis by an out-of-plane method with an XRD apparatus, a peak which shows a crystal plane does not appear. A halo pattern is observed when the amorphous oxide semiconductor film is subjected to electron diffraction. Furthermore, a spot is not observed and a halo pattern appears when the amorphous oxide semiconductor film is subjected to nanobeam electron diffraction.

An oxide semiconductor film may have a structure having physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. The oxide semiconductor film having such a structure is specifically referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In a high-resolution TEM image of the a-like OS film, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. In some cases, growth of the crystal part occurs due to the crystallization of the a-like OS film, which is induced by a slight amount of electron beam employed in the TEM observation. In contrast, in the nc-OS film that has good quality, crystallization hardly occurs by a slight amount of electron beam used for TEM observation.

The crystal part size in the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, an InGaZnO4crystal has a layered structure in which two Ga—Zn—O layers are included between In—O layers. A unit cell of the InGaZnO4crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Accordingly, the distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Thus, focusing on lattice fringes in the high-resolution TEM image, each of lattice fringes in which the lattice spacing therebetween is greater than or equal to 0.28 nm and less than or equal to 0.30 nm corresponds to the a-b plane of the InGaZnO4crystal.

The density of an oxide semiconductor film varies depending on the structure in some cases. For example, when the composition of an oxide semiconductor film is determined, the structure of the oxide semiconductor film can be expected by comparing the density of the oxide semiconductor film with the density of a single crystal oxide semiconductor film having the same composition as the oxide semiconductor film. For example, the density of the a-like OS film is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor film having the same composition. For example, the density of each of the nc-OS film and the CAAC-OS film is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor film having the same composition. Note that it is difficult to deposit an oxide semiconductor film having a density of lower than 78% of the density of a single crystal oxide semiconductor film having the same composition.

Specific examples of the above description are given. For example, in the case of an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of a single crystal InGaZnO4film with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS film is higher than or equal to 5.0 g/cm3and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS film and the CAAC-OS film is higher than or equal to 5.9 g/cm3and lower than 6.3 g/cm3.

Note that there might be no single crystal oxide semiconductor film having the same composition as the oxide semiconductor film. In that case, single crystal oxide semiconductor films with different compositions are combined at an adequate ratio, which makes it possible to calculate a density equivalent to that of a single crystal oxide semiconductor film with the desired composition. The density of a single crystal oxide semiconductor film having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductor films with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductor films as possible to calculate the density.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

In this embodiment, methods of forming the insulating layers, the conductive layers, the semiconductor layers, and the like included in the semiconductor device10described in the above embodiment will be described.

A sputtering method and a plasma CVD method are typical examples of a method of forming an insulating layer, a conductive layer, a semiconductor layer, and the like included in a semiconductor device. These layers can be formed by another method, for example, a thermal CVD method. A metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method can be employed as a thermal CVD method, for example.

A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film. Deposition by a thermal CVD method may be performed in the following manner: the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and a source gas and an oxidizer are supplied to the chamber at the same time, react with each other in the vicinity of the substrate or over the substrate, and are deposited on the substrate.

Deposition by an ALD method may be performed in the following manner: the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then, the sequence of the gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). In this case, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as the first source gas or after the first source gas is introduced so that the source gases are not mixed, and then, a second source gas is introduced. In the case where the first source gas and the inert gas are introduced at the same time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the second source gas. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then, the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first single-atomic layer; then, the second source gas is introduced to react with the first single-atomic layer; as a result, a second single-atomic layer is stacked over the first single-atomic layer, so that a thin film is formed. The sequence of the gas introduction is repeated a plurality of times until a desired thickness is obtained, so that a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of times the sequence of the gas introduction is repeated; therefore, an ALD method makes it possible to accurately adjust thickness and thus is suitable for manufacturing a minute FET.

The conductive films and the semiconductor films which are described in the above embodiments can be formed by a thermal CVD method such as an MOCVD method or an ALD method. For example, in the case where an InGaZnOX(X>0) film is formed, trimethylindium, trimethylgallium, and dimethylzinc can be used. Note that the chemical formula of trimethylindium is (CH3)3In. The chemical formula of trimethylgallium is (CH3)3Ga. The chemical formula of dimethylzinc is (CH3)2Zn. Without limitation to the above combination, triethylgallium (chemical formula: (C2H5)3Ga) can be used instead of trimethylgallium, and diethylzinc (chemical formula: (C2H5)2Zn) can be used instead of dimethylzinc.

For example, in the case where a tungsten film is formed using a deposition apparatus employing ALD, a WF6gas and a B2H6gas are sequentially introduced a plurality of times to form an initial tungsten film, and then, a WF6gas and an H2gas are used to form a tungsten film. Note that an SiH4gas may be used instead of a B2H6gas.

For example, in the case where an oxide semiconductor film, e.g., an InGaZnOX(X>0) film is formed using a deposition apparatus employing ALD, an In(CH3)3gas and an O3gas are sequentially introduced a plurality of times to form an InO2layer, a Ga(CH3)3gas and an O3gas are used to form a GaO layer, and then, a Zn(CH3)2gas and an O3gas are used to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an InGaO2layer, an InZnO2layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Although an H2O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O3gas, it is preferable to use an O3gas, which does not contain H. Instead of an In(CH3)3gas, an In(C2H5)3gas may be used. Instead of a Ga(CH3)3gas, a Ga(C2H5)3gas may be used. Furthermore, a Zn(CH3)2gas may be used.

In this embodiment, application examples of the semiconductor device or memory device described in the foregoing embodiment to an electronic component and to an electronic device including the electronic component will be described with reference toFIGS. 26A and 26BandFIGS. 27A to 27F.

FIG. 26Ashows an example where the semiconductor device described in the foregoing embodiment is used to make an electronic component. Note that an electronic component is also referred to as semiconductor package or IC package. This electronic component has various standards and names depending on the direction and the shape of terminals. Therefore, an example of the electronic component will be described in this embodiment.

A semiconductor device including the transistors in the foregoing embodiment is completed by integrating detachable components on a printed circuit board through an assembly process (post-process).

The post-process can be completed through steps shown inFIG. 26A. Specifically, after an element substrate obtained in the preceding process is completed (Step S1), a back surface of the substrate is ground (Step S2). The substrate is thinned in this step to reduce warpage or the like of the substrate in the preceding process and to reduce the size of the component itself.

A dicing step of grinding the back surface of the substrate and separating the substrate into a plurality of chips is performed. Then, a die bonding step of individually picking up separate chips to be mounted on and bonded to a lead frame is performed (Step S3). In this die bonding step, the chip is bonded to the lead frame by an appropriate method depending on a product, for example, bonding with a resin or a tape. Note that in the die bonding step, the chip may be mounted on and bonded to an interposer.

Note that in this embodiment, when an element is formed on one surface of a substrate, the other surface is referred to as a back surface (a surface on which the element is not formed).

Next, wire bonding for electrically connecting a lead of the lead frame and an electrode on the chip through a metal wire is performed (Step S4). As the metal wire, a silver wire or a gold wire can be used. For wire bonding, ball bonding or wedge bonding can be employed.

A molding step is performed to seal the wire-bonded chip with an epoxy resin or the like (Step S5). With the molding step, the inside of the electronic component is filled with a resin, thereby reducing damage to the circuit portion and the wire embedded in the component caused by external mechanical force as well as reducing deterioration of characteristics due to moisture or dust.

After being plated, the lead of the lead frame is cut and processed into a predetermined shape (Step S6). The plating process prevents rust of the lead and facilitates soldering at the time of mounting on a printed circuit board in a later step.

Printing (marking) is performed on the package surface (Step S7). After a final testing step (Step S8), the electronic component is completed (Step S9).

Since the electronic component described above includes the semiconductor device of the foregoing embodiment, it is possible to improve the reliability of the electronic component.

FIG. 26Bis a perspective schematic diagram of a completed electronic component.FIG. 26Bshows a perspective schematic diagram of a quad flat package (QFP) as an example of the electronic component. An electronic component4700inFIG. 26Bincludes a lead4701and a circuit portion4703. The electronic component4700inFIG. 26Bis, for example, mounted on a printed circuit board4702. A plurality of electronic components4700which are combined and electrically connected to each other over the printed circuit board4702can be mounted on an electronic device. A completed circuit board4704is provided in an electronic device or the like.

Described next are electronic devices including the aforementioned electronic component.

The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are cellular phones, game machines including portable game machines, portable information terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), vending machines, and medical devices.FIGS. 27A to 27Fillustrate specific examples of these electronic devices.

FIG. 27Aillustrates a portable game machine, which includes a housing5201, a housing5202, a display portion5203, a display portion5204, a microphone5205, a speaker5206, an operation key5207, a stylus5208, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in portable game machines. Although the portable game machine inFIG. 27Ahas the two display portions5203and5204, the number of display portions included in a portable game machine is not limited to this.

FIG. 27Billustrates a portable information terminal, which includes a first housing5601, a second housing5602, a first display portion5603, a second display portion5604, a joint5605, an operation key5606, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in portable information terminals. The first display portion5603is provided in the first housing5601, and the second display portion5604is provided in the second housing5602. The first housing5601and the second housing5602are connected to each other with the joint5605, and the angle between the first housing5601and the second housing5602can be changed with the joint5605. Images displayed on the first display portion5603may be switched in accordance with the angle at the joint5605between the first housing5601and the second housing5602. A display device with a position input function may be used as at least one of the first display portion5603and the second display portion5604. Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by provision of a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 27Cillustrates a notebook type personal computer, which includes a housing5401, a display portion5402, a keyboard5403, a pointing device5404, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in notebook type personal computers.

FIG. 27Dillustrates an electric refrigerator-freezer, which includes a housing5301, a refrigerator door5302, a freezer door5303, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in electric refrigerator-freezers.

FIG. 27Eillustrates a video camera, which includes a first housing5801, a second housing5802, a display portion5803, operation keys5804, a lens5805, a joint5806, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in video cameras. The operation keys5804and the lens5805are provided in the first housing5801, and the display portion5803is provided in the second housing5802. The first housing5801and the second housing5802are connected to each other with the joint5806, and the angle between the first housing5801and the second housing5802can be changed with the joint5806. Images displayed on the display portion5803may be switched in accordance with the angle at the joint5806between the first housing5801and the second housing5802.

FIG. 27Fillustrates a passenger car, which includes a car body5701, wheels5702, a dashboard5703, lights5704, and the like. The semiconductor device of one embodiment of the present invention can be used for a variety of integrated circuits included in passenger cars.

In this embodiment, application examples of an RF tag which can include the semiconductor device or memory device of one embodiment of the present invention will be described with reference toFIGS. 28A to 28F. The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident cards, seeFIG. 28A), recording media (e.g., DVDs or video tapes, seeFIG. 28B), packaging containers (e.g., wrapping paper or bottles, seeFIG. 28C), vehicles (e.g., bicycles, seeFIG. 28D), personal belongings (e.g., bags or glasses), foods, plants, animals, human bodies, clothes, household goods, medical supplies such as medicine and chemicals, and electronic devices (e.g., liquid crystal display devices, EL display devices, television devices, or cellular phones), or tags on products (seeFIGS. 28E and 28F).

An RF tag4000of one embodiment of the present invention is fixed to products by being attached to a surface thereof or embedded therein. For example, the RF tag4000is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag4000of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag4000of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have higher security against theft or the like by being provided with the RF tag of one embodiment of the present invention.

As described above, by using the RF tag of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read.

Example

In this example, measurement results of characteristics of OS transistors which can be used in the above embodiment will be described.

First, temperature characteristics of OS and Si transistors were measured.FIG. 29Ashows measurement results of temperature dependences of gate voltage vs. drain current (VG−ID) characteristics and gate voltage vs. field-effect mobility (VG−μFE) characteristics of an OS transistor.FIG. 29Bshows measurement results of temperature dependences of gate voltage vs. drain current (VG−ID) characteristics and gate voltage vs. field-effect mobility (VG−μFE) characteristics of a Si transistor.FIGS. 29A and 29Bshow measurement results of these electrical characteristics at temperatures of −25° C., 50° C., and 150° C. The drain voltage VDis 1 V.

FIG. 29Ashows electrical characteristics of the OS transistor that has a channel length L of 0.45 μm, a channel width W of 10 μm, and a gate insulating layer of an oxide film with a thickness Toxof 20 nm.FIG. 29Bshows electrical characteristics of the Si transistor that has an L of 0.35 μm, a W of 10 μm, and a Toxof 20 nm.

An oxide semiconductor layer in the OS transistor is made of an In—Ga—Zn-based oxide. The Si transistor is formed using a silicon wafer.

FIGS. 29A and 29Bshow that the OS transistor has low temperature dependence of rising gate voltage. The off-state current of the OS transistor is lower than or equal to the lower measurement limit (I0) independently of temperature. On the contrary, the off-state current of the Si transistor largely depends on the temperature. According to the measurement results ofFIG. 29B, at 150° C., the off-state current of the Si transistor rises, and a sufficiently high current on/off ratio cannot be obtained.

According to the graphs inFIGS. 29A and 29B, when including the OS transistor, the semiconductor device of one embodiment of the present invention can operate even at 150° C. or higher. Thus, the semiconductor device has excellent heat resistance.

Next, withstand voltages of OS and Si transistors were measured.FIG. 30shows measurement results of VD−IDcharacteristics of Si and OS transistors. InFIG. 30, to compare withstand voltages of the Si and OS transistors under the same conditions, both of the transistors have a channel length of 0.9 μm, a channel width of 10 μm, and a gate insulating film using silicon oxide with a thickness of 20 nm. Note that the gate voltage is 2 V.

As shown inFIG. 30, avalanche breakdown occurs in the Si transistor at a drain voltage of approximately 4 V, whereas in the OS transistor, a constant current can flow until a drain voltage of approximately 26 V causes avalanche breakdown.

FIG. 31Ashows measurement results of VD−IDcharacteristics of an OS transistor with varying gate voltage.FIG. 31Bshows measurement results of VD−IDcharacteristics of a Si transistor with varying gate voltage. Note that to compare withstand voltages of the Si and OS transistors under the same conditions, both of the transistors have a channel length of 0.9 μm, a channel width of 10 μm, and a gate insulating film using silicon oxide with a thickness of 20 nm. The measurement results of the characteristics of the OS transistor inFIG. 31Awere obtained at different gate voltages of 0.1 V, 2.06 V, 4.02 V, 5.98 V, and 7.94 V. The measurement results of the characteristics of the Si transistor inFIG. 31Bwere obtained at different gate voltages of 0.1 V, 1.28 V, 2.46 V, 3.64 V, and 4.82 V.

As shown inFIGS. 31A and 31B, avalanche breakdown occurs in the Si transistor at a drain voltage of approximately 4 V to 5 V, whereas in the OS transistor, a constant current can flow until a drain voltage of approximately 9 V causes avalanche breakdown.

FIG. 30andFIGS. 31A and 31Bshow that the OS transistor has a higher withstand voltage than the Si transistor. Therefore, with the use of the OS transistor in the memory cell21of one embodiment of the present invention, the range of possible voltages at the node SN can be widened.

This application is based on Japanese Patent Application serial no. 2015-098701 filed with Japan Patent Office on May 14, 2015, the entire contents of which are hereby incorporated by reference.