Precision bandgap circuit using high temperature coefficient diffusion resistor in a CMOS process

Disclosed are bandgap circuits that use a resistive divider circuit to modulate the gate voltage of a reference source transistor. The reference voltage transistor is modulated at the base by a voltage that varies inversely with temperature. In this fashion, high sheet resistance poly resistors and diffusion resistors can be used that have very low process variation and minimize the use of die space.

BACKGROUND OF THE INVENTION

a. Field of the Invention

The present invention pertains generally to electrical devices and more specifically to bandgap current and voltage reference circuits.

b. Description of the Background

Reference circuits are needed to bias electronic circuits. Reference sources of electronic circuits use the conduction and valence band difference of the intrinsic substrate material (silicon) to generate a reference voltage or current which may vary as a result of process variations or variations in environmental temperatures. The negative temperature coefficient of the silicon bandgap voltage is cancelled in prior art circuits by using the positive temperature coefficient of thermal voltage to generate the reference source. Typically, low temperature coefficient poly resistors, i.e., on the order of 6×10−4, are used to generate a reference source. However, these poly resistors have low sheet resistance, i.e., on the order of 30-40 ohms per square, and as such, consume a large amount of space on the die. In many cases, the poly resistors may consume up to 50 percent of the die space. In addition, poly resistors have large process variations, and many times require expensive laser trimming to provide the needed accuracy that is not available because of process variations.

SUMMARY OF THE INVENTION

An embodiment of the present invention comprises a bandgap reference circuit comprising: first and second transistors that have gates that are connected and are driven by a common gate voltage, the first and second transistors having sizes that are proportional to the current flowing through the first and second transistors so that the voltages at the sources of the first and second transistors are substantially equal; a reference resistor connected to the source of the first transistor; a first reference transistor having an emitter that is connected to the resistor and a collector connected to ground; a second reference transistor having an emitter connected to the second transistor and a collector connected to ground; a resistor divider circuit connected to the base of the first reference transistor; a modulating transistor connected to the resistor divider circuit that modulates the base of the first reference transistor with a fraction of voltage difference between the base and emitter of the modulating transistor to substantially cancel the temperature coefficient of current flowing through the reference resistor.

Another embodiment of the present invention comprises a method of generating a reference voltage in a bandgap circuit comprising: generating a first voltage at the source of a first transistor that is substantially equal to a second voltage at the source of a second transistor by connecting the gates of the first and second transistors to a common driver, and matching the component sizes of the first and second transistors with the amount of current passing through the first and second transistors; connecting the source of the first transistor to a reference resistor; connecting the reference resistor to a first reference transistor; connecting the source of second transistor to a second reference transistor; connecting the base of the first reference transistor to a resistor divider circuit; connecting the resistor divider circuit to a modulating transistor that modulates the base of the first reference transistor with a fraction of the voltage difference between the base and emitter of the modulating transistor so as to substantially cancel the temperature coefficient of current through the reference resistor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1discloses a classical bandgap reference circuit that uses a substrate vertical PNP transistor of a standard CMOS process to generate a reference current and/or reference voltage source. By setting the device ratio of M0and M1the same as the current ratio for the current that flows through M0and M1, a temperature independent source can be achieved as long as the temperature coefficient of the resistance used for R0and R1is sufficiently low, such as that provided by poly resistors, which is on the order of e−06. The gates of both M1and M0are held at the same potential in the circuit ofFIG. 1by M2. Because the device size ratio of M0and M1is the same as the current ratio of the current passing through M0and M1, the sources of M1and M0are the same potential. A0is the device area of Q0, and A1is the device area of Q1.

As also shown inFIG. 1, Q0and Q1have an area ratio of A0/A1which is typically 8 to 1. The voltage drop across R0(VR0) can be determined using Kirchoff's Voltage Law around the loop Q0, Q1, M1, M0and R0.

VR0=VGS1-VGS0-VBE0+VBE1=VT⁢ln⁡(A0⁢I1A1⁢I0)Eq.⁢1
VTis the thermal voltage and is equal to κT/q. The gate to source voltage of M1(VGS1) and the gate to source voltage of M0(VGS0), as pointed out above, are equal since the device ratio size of M1and M0are the same as the ratio of the current flowing through them.

As Eq. 1 shows, the voltage drop across R0is proportional to the thermal voltage (VT). The current I0flowing through R0can be determined from the super position theorem as follows:

I0=VBE1-VBE0R0=κ⁢⁢Tq⁢⁢R0⁡[ln⁡(A0⁢MA1)+ln⁡(1+VBE0IQ0⁢R1)]Eq.⁢2
where κ is the Boltzman Constant, ‘M’ is current ratio between M0and M1, ‘A’ is the area ratio of transistor Q0and Q1, ‘T’ is absolute temperature, ‘q’ is the single electron charge and IQ0is the current in the Q0device.

By taking the derivative of the current I0through R0with respect to temperature, the change in the current I0can be determined as a function of the change in absolute temperature. The first order temperature derivative of I0is given in Eq. 3.

∂I0∂T=κq⁢⁢R⁢ln⁡(A0⁢I1A1⁢I0)⁢1-α2⁢T2(1+α1⁢T+α2⁢T2)Eq.⁢5
Eq. 5 suggests that at a temperature equal to 1/√{square root over (a2)}, the temperature coefficient of a current reverses its sign. Thus, above the coefficient inversion temperature (T0), the device has a negative temperature coefficient instead of a positive temperature coefficient.

Referring toFIG. 2, the coefficient inversion temperature for a poly resistor is 1090° C., whereas the coefficient inversion temperature for a well resistor is 17° C. Hence, poly resistors having low sheet resistance work well in the circuitFIG. 1since the coefficient inversion temperature of the poly resistors is well above the environmental temperatures to which the circuit ofFIG. 1is subjected. The problem, again, is poly resistors require a large die area and process variations are large. Laser trimming is frequently required to provide the necessary accuracy. Well resistors and high sheet resistance poly resistors, however, have coefficient inversion temperatures that are within the temperature of interest and as such, provide a negative temperature coefficient that does not cancel out the negative temperature coefficient of the silicon.

FIG. 3is a schematic circuit diagram of one embodiment that is capable of using well resistors or high poly resistors that use a much smaller die space and provide the compensation necessary to offset the negative temperature coefficient of the silicon. Well resistors (diffusion resistors) have 16 times higher sheet resistance and 4 times tighter process variation than low sheet resistance poly resistors. As indicated above, however, well resistors suffer from in order of magnitude higher temperature coefficient, which causes the resistor R0to have a negative temperature coefficient above the coefficient inversion temperature, which for the well resistor is about 17° C. The base to emitter voltage in silicon, as pointed out above, also has a negative temperature coefficient. Hence, the resistor R1inFIG. 1does not compensate the negative temperature coefficient of Q0, but actually adds to the problem, if a well resistor or high poly resistor is used. In other words, it can be said that above the inversion temperature of resistor R0, the current becomes CTAT, instead of PTAT.

FIG. 3provides a circuit layout in which the base of transistor Q1is modulated with a voltage(VB) which has positive temperature coefficient below the coefficient inversion temperature(T0) and negative temperature coefficient above T0.

∂VB∂T>0;for⁢⁢T<T0Eq.⁢5⁢A∂VB∂T<0;for⁢⁢T>T0
The positive temperature coefficient of VBis generated using a constant current through a well resistor R1. The negative coefficient is generated by an appropriate fraction of VBEof Q2. Thus, base voltage modulation of the Q1 transistor is used to cancel the PTAT and CTAT nature of I0in the resistor R0over entire operating temperature range. Resistors R1and R2and current through them in the circuit ofFIG. 3are selected such that at temperature T0the voltage drop across R1and R2is equal to the required voltage to put the diode connected device Q2in saturation. Since Vbe of Q2has a negative temperature coefficient and the well resistors have a positive temperature coefficient, for temperatures below T0, resistors R1and R2will develop a lower voltage drop than required voltage to put the transistor Q2in saturation. Thus, the voltage VBat the junction of R1and R2is controlled by the voltage drop across resistor R1, which gives the required positive temperature coefficient to VBbelow temperature T0. Above temperature T0, R1and R2require higher and higher voltages, whereas the VBEof transistor Q2keeps on falling. The current chooses the least resistance path through Q2over R1in series with R2. At these high temperatures, R1and R2behaves as a resistive divider of voltage VBEof Q2transistor. Thus again, the temperature coefficient of VBabove T0is controlled by Vbe and a fraction of it provides the necessary negative temperature to VB. Voltage VBis used to modulate the base of Q0and subtract a desired fractional value of the positive and negative temperature coefficient from VR0to cancel the temperature coefficient of the current flowing in R0. To prove the concept, the analysis of the temperature coefficient of the current above T0is given below. The current I0flowing through R0ofFIG. 3is given by the Eq. 6.

∂I0∂T=κ⁢⁢ln⁢⁢Aq⁢⁢R0⁡(1+ɛ⁢⁢R1/R0)⁢1-α2⁢T2(1+α1⁢T+α2⁢T2)2Eq.⁢7
If ratio of R1/R0>>1, then ∂I0/∂T is negligible.
Taking the derivative of the current I0with respect to temperature for T>T0gives

∂I0∂T={κ⁢⁢ln⁢⁢Aq⁢⁢R0-⁢ηR0⁢(∂VBE2∂T-⁢α1⁢VBE2)}-⁢ηR0⁢⁢(α1⁢∂VBE2∂T-2⁢α2⁢VBE2)⁢T(1+α1⁢T+α2⁢T2)2-α2R0⁢(κ⁢⁢ln⁢⁢Aq+η⁢∂VBE2∂T)⁢T2(1+α1⁢T+α2⁢T2)2Eq.⁢8
where η is R1/(R1+R2). The last factor in parentheses in Eq. 8 is the third order coefficient (second order curvature compensated reference current). The second to the last factor in parentheses is the second order coefficient. The factor on the far left of Eq. 8 is the first order coefficient.

Equating the first factor of Eq. 8 to zero gives a first order temperature compensated reference current that is provided in Eq. 9.

Eq. 9 involves two unknown terms, i.e., η and VBE2. Hence, another factor of r.h.s of Eq. 8 must be equated to zero. Equating the last factor of Eq.8 to zero gives the value of design variable η as shown in Eq. 11. It is also known that
∂VBE/∂T≈−2 mV/°C.

Substituting the of value of η from Eq. 11 in Eq.9 to solve for the second design variable VBEof Q2 transistor gives

Substituting the value of VBE2and η in Eq.8 gives the remainder of second order temperature coefficient (TC2).

The second order temperature coefficient (TC2) is mostly dominated by the cross over distortion at coefficient inversion temperature (T0). At temperature T0, feedback of Eq. 7 is also present, therefore with some iteration in design it can be cancelled out.

The above derivation assumes that each higher order temperature coefficient VBEis smaller than the previous one. The current and device area for Q2is designed such that it can generate the voltage drop VBE2at temperature T0. Thus, depending upon the current ratio of Q0and Q1, the resistor ratio η can be calculated from Eq. 11. Since ∂VBE/∂T is a negative quantity, the negative sign on the right hand side of Eq. 11 and Eq. 12 renders these quantities positive. Referring again toFIG. 3, the gate of M0and the gate of M1constitute the differential inputs to a differential amplifier formed by M0and M1. As such, the voltages at node24and node26are equal. Again, Q0and Q1have a device area ratio of A0/A1and a current ratio of I0/I1. Assuming temperature independent current flows through R0in this circuit, a fraction of this current is mirrored back to Q2. Hence, the base of Q0is modulated by a voltage VB, which is generated using R1, R2and Q2. For temperature T<T0, VBE2will be higher than εI0(R1+R2). Therefore, VBis defined by the drop across the resistor R1and, consequently, has a positive temperature coefficient. For temperature T>T0, VBE2is smaller than εI0(R1+R2) Therefore, VBis defined by the resistive ratio (η) of the voltage drop VBE2, and in return has a negative temperature coefficient. The voltage VBgenerated by R1, R2and Q2is subtracted from the PTAT voltage across R0by modulating the base of transistor Q0. Hence the circuit shown inFIG. 3, using R0, R1, R2, Q0, Q1and Q2, is one form of circuit implementation of Eq. 6.

The positive feedback loop, consisting of M0, M2, M4, M6, M7, M12and M13, boosts the startup current from M21to the desired value. The negative feedback loop consisting of M1, M3, M5, M10and M11stabilizes the loop from a runaway condition. The components M1, M3, M5, M14, M15, R2, Q0and R0form another feedback loop which stabilizes the temperature coefficient of the current. The device M21is a startup device that ensures that there is always a current for the differential amplifier formed by M0and M1. Components M19and M20mirror a small portion of the differential amplifier current to establish a cascade voltage for the current sources in the circuit. The current flowing through M19and M20are summed together so that there is always current available for M18to avoid startup problems. The gain of the negative feedback loop is higher than the positive feedback loop to avoid a current runaway. The impedance at the drain of M13is 1/gm1. The impedance at the drain of M11is R0+1/gm0+(R1/β), which is greater than 1/gm1. The load at the drain of M11defines the negative loop gain, and M13defines the positive loop gain.

FIG. 4illustrates a layout of the circuit illustrated inFIG. 3. It can be observed that the resistors R0, R1and R2take less than 10 percent of the die area. Low sheet resistance poly resistors, along with trim, consume more than 50 percent of the die area, as disclosed in Rasoul Deghani, S. M. Atarodi, A New Low Voltage Precision CMOS Current Reference with No External Components,IEEE Transactions on Circuits and Systems-II, pp. 928-931, IEEE, December 2003.

FIG. 4was simulated in a 0.5 μm CMOS process. The simulation results of the reference current and first and second order derivatives are shown inFIG. 5. The simulated reference current has two zero crossing points. Hence, the reference current has a third order temperature cancellation or second order curvature compensation. The first and second order derivatives are also plotted along with the current inFIG. 5. The second order derivative has a second order effect.

The reference current has a variation of ±0.8% across the temperature range of −40° C. to 125° C. The power supply rejection ratio (PSRR) of the current is plotted against frequency inFIG. 6for the current shown inFIG. 4. The current has a PSRR of −125 dB at 100 KHz.

The above mathematical derivation can have many other implementations, which can be identified by an expert in the area of circuit design. For example,FIG. 7illustrates another embodiment. M2, M1and M0have good current sources. M2is laid out in the same configuration inFIG. 7as M2inFIG. 1. Transistors M4, M5and M6cascode the current sources M8, M9and M10. By cascoding the current sources, the output resistance of the current sources is increased. Hence, transistors M8, M9and M10constitute a new layer of current sources. M12provides a bias potential for the gates of M8, M9and M10. M3constitutes another current source for M2, M1and M0. It is desirable to have the same gate to source voltage on M3as M2so that a current mirror is created. So, another transistor, Q3is added which is the same size as Q2.

Eq. 12 is the voltage from which the current in M7and M11can be calculated. The current provided by M7and M11are used to modulate the base of transistor Q0using transistor Q4. In this fashion, a portion of the negative coefficient of temperature is subtracted from Q0for T>T0, as explained above with respect toFIG. 3.

Both positive and negative feedback loops are provided in the circuit ofFIG. 7. The positive feedback loop starts at node12and proceeds to node14which changes the sign to a minus. From node14the loop proceeds from the base of M4to node16, and the sign changes to plus. The feedback loop then proceeds from M8to node18, and the sign remains the same, i.e., plus. The feedback loop then proceeds from node18to node12, and the sign changes to a negative. Hence, the feedback loop of M1, M4, M8and M0is a negative feedback loop and keeps the circuit from runaway conditions.

The positive feedback loop starts at node12and proceeds from the base of M0to node18where the sign changes to minus. The positive feedback loop then proceeds from the base of M6to node20where the sign changes to plus. The positive feedback loop then proceeds from node20to node22(node12) and the sign remains the same, i.e., plus. A positive feedback loop is therefore provided by M0, M6and M10.

Hence, various embodiments disclosed herein ameliorate the problems of the negative temperature coefficient of the Q0transistor by modulating the base of the Q0transistor with a CPTAT voltage that is inversely proportional to temperature. In other words, a fraction of the VBEof Q2(FIG. 3) or Q4(FIG. 7) is used to modulate the base of the transistor Q0. By using the resistor divider circuit R1and R2, a fraction of the VBEof Q2(FIG. 3) or Q4(FIG. 7) is subtracted from the PTAT voltage across resistor R0(VRO) and thereby cancels the negative temperature coefficient of current that is above the coefficient inversion temperature of R0, above temperature T0. In this manner, well resistors such as diffusion resistors or high sheet resistance poly resistors can be used that do not occupy a large space on the semiconductor die and that have much better process variation control so that a more accurate system is provided.