Method for reading memory cell

Methods for reading a memory cell are provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for reading a memory cell, and more particularly to a method for stably reading a memory cell.

2. Description of the Related Art

Demand for semiconductor memory devices (or memory devices) have increased because of their advantages. Of the different types of memory devices, magnetic random access memory (MRAM), resistive random-access memory (RRAM), and phase change memory (PCM) have random accessibility, higher integration and greater capacity storage when compared to other memory devices.

A phase change memory (PCM) or phase-change random access memory (PRAM) is based on a volume of chalcogenide alloy, which, after being heated and cooled, adopts one of two stable, but programmable, phases: a crystalline state or an amorphous state. The key to the phase-change memory is the chalcogenide material. The device historically includes an alloy of germanium (Ge), antimony (Sb) and tellurium (Te), which is referred to commonly as a GST alloy. The material is particularly useful for incorporation in a memory device because of its ability to switch rapidly, when heated and cooled, between the stable amorphous and crystalline phases.

For materials used in PCMs or PRAMs, resistance of a first phase, i.e., a crystalline phase, is relatively low, and the resistance of a second phase, i.e., the amorphous phase, is relatively high. The state of the cell is programmed to a logical one (1) or zero (0), depending upon the phase of the programmable volume, and measured resistance. The crystalline state is commonly referred to as the “set”, or “0”, state and the amorphous state is commonly referred to as the “reset”, or “1”, state.

Recently, a technique for storing more than 2-bit data in one memory cell has been disclosed. This type of memory cell is generally referred to as a multi-level cell (MLC). A multi-level phase change memory device is a low-cost non-volatile memory device having high memory capacity. In a multi-level phase change memory device, there are intermediate states between a reset state and a set state.

However, for multi-level phase change memory devices including chalcogenide containing amorphous material, the resistance of the chalcogenide containing amorphous material drifts upward over time (e.g., following the power law (t/t0)r, with r˜0.1), as much as a factor of 4, within 106seconds, as shown inFIG. 1and disclosed in Karpov et al., J. Appl. Phys. 102, 124503 (2007). This poses a problem for operation of the multi-level phase change memory device, where two adjacent resistance states may need to be separated by a factor of 1.5-2.

FIG. 2is a graph illustrating time against resistance of a multi-level phase change memory cell in which data are programmed into a state 11, a state 10, a state 01 and a state 00. The freshly programmed resistance state 11 of a resistance R0at time t1would be confused with the resistance state 10 that was programmed at time t2. For this reason, the operation of multilevel phase change memory as high bit density technology is prohibited unless a different method of operation avoiding the drift consequence is used. It should also be noted that other non-volatile resistance-based memories based on materials such as TiO2, are also vulnerable to resistance drift (e.g., B. J. Choi et al., J. Appl. Phys. 98, 033715 (2005)).

U.S. Pat. Pub. 2009/0016100 discloses a phase change memory device and a reading method thereof. The method programs a reference array along with a read/write block. However, the read/write operation and required structure result in excess time and power consumption as well as extra chip area, leading to higher manufacturing cost.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a method for reading a memory cell is provided. The method for reading a memory cell includes applying at least two successive read pulses to a memory cell, obtaining at least two read data; and subsequently determining the activation energy via the at least two read data.

Another exemplary embodiment of a method for reading a memory cell is provided. The method for reading a memory cell includes applying a first read pulse to a memory cell, heating the memory cell to a first temperature and obtaining a first read data. The first read data is converted to a first digital data. The first digital data is stored in a shift register. A second read pulse is applied to the memory cell, heating the memory cell to a second temperature and obtaining a second read data. The second read data is converted to a second digital data. The second digital data is stored in the shift register. A ratio of the first digital data and the second digital data is calculated, obtaining a quotient. The quotient is converted to an analog value. A log amplifier circuit takes the log of the analog value, representing an activation energy state.

DETAILED DESCRIPTION OF THE INVENTION

A memory cell such as a phase change memory cell stores information as a state. This state is characterized not only by electrical resistance but also by activation energy (Ea). An embodiment of the invention provides a method for reading state information by determining the activation energy thereof, reducing read errors causing from resistance time drift during a read operation.

The invention avoids the above-mentioned resistance drift by relying on determining activation energy (Ea) as the method of reading information. The activation energy and the memory cell state resistance can be determined according to the following equation:
R=Aexp(Ea/kT),  Equation (I)

wherein, A is a normalizing factor, Ea is the activation energy, k is the Boltzmann constant and T is the absolute Kelvin temperature. The activation energy is an indicator of the mixture of amorphous and crystalline composition in the phase change material. Further, the memory cell state resistance can be also determined by the following equation:
R=Aexp([E0+kTvln(t/t0)]/kT),  Equation (II)

wherein, A is a normalizing factor, E0is the activation energy in crystalline state, k is the Boltzmann constant, T is the absolute Kelvin temperature, t and t0are time, and v is drift coefficient. Therefore, the activation energy of the amorphous/crystalline mixture state can be identified according to the following equation:
Ea=E0+kTvln(t/t0).  Equation (III)

In a typical phase change memory cell operation at room temperature, kT is approximated as 0.026 eV, v is approximated as 0.1, E0is approximated as 0.2 Ev, and to is 1 second. Accordingly, the activation energy of the crystalline state and amorphous/crystalline mixture state is determined according to the following equation:
Ea≈0.2 eV+0.0026 eV×ln(t/1).  Equation (IV)

For a typical phase change memory based on Ge2Sb2Te5 (GST), the activation energy of the crystalline state is approximated as 0.02 eV and the activation energy of the amorphous state is approximated as 0.2 eV. The activation energy between an amorphous/crystalline mixture state is illustrated inFIG. 3. As shown inFIG. 3, each amorphous/crystalline mixture state (with different amorphous/crystalline (a/c) ratio) has corresponding and no overlapped activation energy.

Operation of activation energy inherently results in less time drift than resistance due to the following. From the Equation (I): R=A exp (Ea/kT), the following equation can be derived:
1/Ea×dEa/dt=(kT/Ea)×1/R×dR/dt,Equation (V)

wherein, t is time, and R is resistance,

Thus, the logarithmic rate of change of Ea is a factor of kT/Ea smaller than that of R. In embodiments of the invention, the method to determine activation energy requires two successive resistance readings (obtaining resistances R1and R2), one after the other, but at two different temperatures (first temperature T1and second temperature T2) resulting from two different read power inputs. According to the above description and the Equation (V), the relationship between R1and R2can be represented by the following equation:
R1/R2=exp[Ea/k×(1/T1−1/T2)],  Equation (VI)
i.e. ln(R1/R2)=Ea/k×(1/T1−1/T2).  Equation (VII)

Regarding Equation (VII), the log ratio (ln(R1/R2)) is in direct proportion to the activation energy (Ea), represented by the following equation:
ln(R1/R2)∝Ea.Equation (VIII)

For the crystalline state, the log ratio (ln(R1/R2)) is approximated as 0. For the amorphous state, in a worst case, the log ratio (ln(R1/R2)) ranges from 0.3 to 0.4 (wherein Ea is approximated as 0.2 Ev, and T1is 380K and T2is 400K), as shown inFIG. 4. As result, the activation energy drift factor (≦30%) is much less than the resistance drift factor (˜4).

As shown inFIG. 2, if the resistance of state 10 at time t2(R10(t2) is equal to the resistance of state 11 at time t1, reading errors occur. Accordingly, if the activation energy of state 10 at time t2Ea10(t2) is not equal to or exceeds the activation energy of state 11 at time t1Ea11(t1), reading errors would not occur. In an embodiment of the invention, a multi-level phase change memory cell, in which data are programmed into a state 11, a state 10, a state 01 and a state 00, is provided. The resistance of state 10 at time t2(R10(t2)) and the resistance of state 11 (R11(t1)) at time t1can be determined according to the following equations:
R11(t1)=A11exp(Ea11(t1)/kT),  Equation (IX)
R10(t2)=A10exp(Ea10(t2)/kT).  Equation (X)

When the resistance of state 10 at time t2(R10(t2)) is equal to the resistance of state 11 at time t1(R11(t1)), the relationship between the activation energy of state 10 at time t2Ea10(t2) and the activation energy of state 11 at time t1Ea11(t1) can be determined according to the following equation:
A11exp(Ea11(t1)/kT)=A10exp(Ea10(t2)/kT).  Equation (XI)

After taking log of both sides, Equation (XI) can be expressed according to the following equation:
lnA11+Ea11(t1)/kT=lnA10+Ea10(t2)/kT,Equation (XII)
i.e.kT[lnA11−lnA10]=Ea10(t2)−Ea11(t1).  Equation (XIII)

At the melting point (˜900 K for GST), the resistivities should converge. As a result, A00should be greater than A11to make up for the activation energy. Since A11<A10, the Equation (XIII): kT[ln A11−ln A10]=Ea10(t2)−Ea11(t1)<0.

The negative difference means Ea10(t2) has not yet crossed over to match Ea11(t1). The result is shown inFIG. 5.

FIG. 6shows a block diagram of a multi-level phase change memory device100according to an example embodiment. As shown inFIG. 6, the array10may include a plurality of memory cells storing multi-bit data in a sense amplifier circuit (as shown as SA)20. Although not illustrated in the drawings, a plurality of memory cells may be arranged in rows (i.e., along word lines) and columns (i.e., along bit lines). The sense amplifier circuit20may sense data of selected memory cells during a read operation. The sense amplifier circuit20provides an analog output signal to an analog-to-digital converter (shown as DAC)30to enable it to produce a digital output signal stored in a shift register40. The shift register40is reset with the first signal, and sequentially shifts the m-bit data from stage to stage in response to the second signal. An arithmetic unit70is used to calculate a ratio of the digital data provided by the shift register40, obtaining a quotient (digital data). A digital-to-analog converter80converts the quotient to an analog value. A log amplifier circuit90(shown as Log Amp) takes the log of the analog value, representing an activation energy state into a data unit120via a sense amplifier circuit (shown as SA)110. The log amplifier can be, for example, an operational amplifier in parallel with a diode and in series with a resistor. An address decoder50may decode an externally provided address and provide the decoded address to a selection circuit (not shown) to select a word line and bit line of at least one memory cell during a write or read operation. Further, the address decoder50and the arithmetic unit70may be controlled by a control logic60.

In embodiments of the invention, the state information is characterized by the activation energy (Ea), which is determined by the ratio of two resistances, and read by two successive pulses, wherein each pulse designed to heat the cell to one of two different temperatures. The results of the two readings may be stored after analog-digital conversion in a shift register, and before a final readout/comparison of the results is performed. The comparison is the binary ratio of the digital data representing the two readings. For a given activation energy, the ratio will be unique, referenced to the ambient temperature. As shown inFIG. 7, the method for reading a memory cell of the invention includes applying a first read pulse to a memory cell to heat the memory cell to a first temperature T1, thus obtaining a first data R1(as shown in step210). Next, the first read data is converted to a first digital data via an analog-to-digital converter30(as shown in step220). Next, the first digital data is stored in a shift register40(as shown in step230). Next, a second read pulse is applied to the memory cell to heat the memory cell to a second temperature T2, thus obtaining a second data R2(as shown in step240). Particularly, the first temperature T1and second temperature T2are different. Next, the second read data is converted to a second digital data via an analog-to-digital converter30(as shown in step250). Next, the second digital data is stored in the shift register40(as shown in step260). Next, the first digital data and the second digital data stored in the shift register40are provided to the arithmetic unit70, calculating a ratio of the first digital data and the second digital data and obtaining a quotient (as shown in step270). Next, the quotient is converted to an analog value via the digital-to-analog converter80(as shown in step280). Finally, the log amplifier circuit90takes the log of the analog value, representing an activation energy state into a data unit120via a sense amplifier circuit110(as shown in step290). The obtained activation energy state can be further calibrated with a thermal reference.

The memory cell read by the method of the invention can be a phase change memory cell, magnetic random access memory cell, or a resistive random access memory cell. The memory cell may include a switching device and a resistance device. The switching device may be realized with a MOS transistor or a diode, for example. The resistance device can include a phase change layer or an oxide resistance layer.

The particular structure of the phase change memory cell is not necessarily constrained, but it is preferably to have a cell that is relatively simple to fabricate and be programmed so that the amorphous and crystalline portions can be mixed in different proportions. For example, the structure may simply consist of a bottom electrode serving as a heater, with a layer of GST on top. The cell may be programmed by first applying a RESET pulse to melt a small portion of the GST, wherein some cooling time is allowed before a second pulse is applied for annealing some portions of the melted region back to a crystalline phase. Thus, a spectrum of different ratios of amorphous to crystalline material may be formed. Each ratio has a corresponding activation energy. In turn, the combination of different ratio regions present an overall effective activation energy. The activation energy can be read by the previously described algorithm.

A resistive random access memory cell has two main states i.e. high resistance state (HRS) and low resistance state (LRS). As shown inFIG. 8, the resistance state of the oxide resistance layer (here consisting of NiO) in the resistive random access memory cell according to an embodiment of the invention exhibit temperature dependences. As shown inFIG. 9, the ln(R1/R2) values (proportional to the activation energies) of the NiO resistive random access memory cell in the high resistance state is stable against time. Accordingly, the method for reading a memory cell of the invention can also be used for resistive random access memory cells.