Display device and method of manufacturing the display device

A wiring layer includes a signal line and covers a predetermined portion on a source region and a drain region of a crystalline silicon layer. A gate insulating layer is on the crystalline silicon layer and the wiring layer. A gate electrode layer above the gate insulating layer includes a scanning line, a gate electrode corresponding to a channel region of the crystalline silicon layer, and a capacitor electrode corresponding to a predetermined portion of the wiring layer. The capacitor electrode is formed separately from the scanning line and the gate electrode and is configured to form a capacitor with the wiring layer. An interlayer insulating film is on the gate electrode layer and the gate insulating layer. A pixel electrode layer on the interlayer insulating film includes a pixel electrode connected to the wiring layer through a contact hole in the gate insulating layer and the interlayer insulating film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device and a method of manufacturing the display device. In particular, the invention relates to a display device including a thin film transistor having a crystalline silicon layer as a channel active layer.

2. Description of Related Art

In recent years, there have been developed active matrix display devices where plural signal lines and plural scanning lines are arranged in matrix, and a thin film transistor (TFT) as a switching element is formed in a pixel area surrounded by the signal lines and the scanning lines. The active matrix display devices excel passive matrix display devices in image quality and thus prevail over other organic EL display devices and liquid crystal display devices. A LTPS TFT including a channel active layer made of low temperature polysilicon (LTPS) has high electron mobility. Performances of the active matrix display devices have been dramatically improved using the LTPS TFT.

For example, the LTPS TFT is applied to a peripheral circuit portion for driving a switching element. If the LTPS TFT is used for peripheral circuits of the display device, it is possible to reduce the number of ICs and IC-equipped substrates for use in devices. As a result, the display device configuration can be simplified and a high-reliability display device with a narrow frame is realized.

Further, in the liquid crystal display devices, if the LTPS TFT is used as a switching element for each pixel, it is possible to reduce not only a capacitance thereof but an area of a storage capacitor connected to the drain side. Therefore, a liquid crystal display device (LCD) of high resolution and high aperture ratio can be attained. Thus, the LTPS TFT plays a leading role in displaying high-resolution images such as QVGA (240×320 pixels) or VGA (480×640 pixels) with a liquid crystal display device with a small panel like a cell phone display panel. In this way, the LTPS TFT is more advantageous than an amorphous silicon (a-Si) TFT in terms of performance.

However, existing LTPS TFTs have problems of many manufacturing steps and low productivity compared with the a-Si TFT. Here, a difference in manufacturing process between the a-Si TFT and the LTPS TFT is described in detail based on the LCD.

As a result of comparing a manufacturing process for an a-Si TFT LCD with that for an LTPS TFT LCD array, the number of patterning steps is 5 for the a-Si TFT LCD but is 8 for the LTPS TFT. A breakdown of the additional three patterning steps necessary for the LTPS TFT is as follows:(1) a selective doping step for forming a C/MOS structure (unnecessary if the TFT structure is one-conductivity type: N type or P type)(2) a doping step for reducing a resistance of a lower-electrode-formation polysilicon layer of a storage capacitor(3) a step of forming contact holes for source/drain lines inclusive of a signal line.

The difference of 3 patterning steps largely influences productivity, and a production cost exceeds a low component cost for ICs and IC-equipped substrates, which is an advantage of the LTPS TFT LCD. As a result, the display device using the LTPS TFT is inferior in product competitiveness to the a-Si TFT. This problem is applicable to active matrix display devices other than the LCD, such as an active matrix organic EL display device (AMOLED).

To that end, Japanese Unexamined Patent Application Publication Nos. 6-194689 and 2003-131260 (Miyasaka) disclose a technique of forming a source/drain line below a gate insulating layer to directly contact a source/drain region in a silicon layer with the source/drain line to use the line as a lower electrode of a storage capacitor. As a result, it is possible to skip the aforementioned two steps: (2) doping step for reducing a resistance of a lower-electrode-formation polysilicon layer of a storage capacitor and (3) step of forming contact holes for source/drain lines. For example, the technique of Miyasaka directly connects the source/drain line with the silicon layer to reduce the number of steps.

The TFT structure of Miyasaka has a silicon layer formed on a metal line, and many defects occur in the LTPS TFT. The LTPS is generally obtained by forming an a-Si layer and locally-heating the a-Si layer surface with a laser to fuse and crystallize the a-Si layer. Under heating at high temperature, metal contamination proceeds from the base metal line to a silicon layer. Hence, a TFT junction in the silicon layer is deteriorated to increase a leak current.

Further, in general, an a-Si layer is heated by moving a laser beam which has linear spot in a laser annealing step. A crystal structure of a silicon layer differs between a case where a direction in which a region is heated with the linear spot of laser beam is vertical to a direction of a source/drain region having a metal line at the end portion and the case where the two directions are parallel to each other. A difference of the crystal structure causes a difference in TFT characteristics. If the TFT structure of Miyasaka is applied to the LTPS TFT, the TFT characteristics vary, and a current leaks and its reliability lowers due to the defects.

SUMMARY OF THE INVENTION

The present invention has been accomplished in view of the above circumstances, and it is an object of the present invention to provide a display device capable of suppressing variations in characteristics of a thin film transistor including a crystalline silicon layer as a channel active layer with a simple structure and a method of manufacturing the display device.

A display device according to an aspect of the present invention includes: a crystalline silicon layer formed on a substrate and including a source region, a drain region, and a channel region; a wiring layer including a signal line and formed to cover at least a predetermined portion on the source region and the drain region; a gate insulating layer formed on the crystalline silicon layer and the wiring layer; a gate electrode layer formed above the gate insulating layer and including a scanning line, a gate electrode corresponding to the channel region, and a capacitor electrode corresponding to a predetermined portion of the wiring layer; an interlayer insulating film formed on the gate electrode layer; and a pixel electrode layer formed on the interlayer insulating film, and including a pixel electrode connected to the drain region or the source region through a contact hole formed in the gate insulating layer and the interlayer insulating film.

A display device according to another aspect of the present invention includes: a crystalline silicon layer formed on a substrate and including a source region, a drain region, and a channel region; a wiring layer including a signal line and formed away from the crystalline silicon layer; a gate insulating layer formed on the crystalline silicon layer and the wiring layer; a gate electrode layer formed above the gate insulating layer and including a scanning line, a gate electrode corresponding to the channel region, and a capacitor electrode corresponding to a predetermined portion of the wiring layer; an interlayer insulating film formed on the gate electrode layer; and a pixel electrode layer formed on the interlayer insulating film, and including a pixel electrode connected to the drain region or the source region through a contact hole formed in the gate insulating layer and the interlayer insulating film.

A method of manufacturing a display device according to another aspect of the present invention includes: forming a crystalline silicon layer on a substrate; covering at least a predetermined portion on the crystalline silicon layer to form a wiring layer including a signal line; forming a gate insulating layer on the crystalline silicon layer and the wiring layer; forming a gate electrode layer including a scanning line, a gate electrode, and a capacitor electrode above the gate insulating layer; forming an interlayer insulating film on the gate electrode layer and the gate insulating layer; and forming a pixel electrode layer on the interlayer insulating film, and electrically connecting the pixel electrode layer and the wiring layer through a contact hole formed in the interlayer insulating film and the gate insulating layer.

A method of manufacturing a display device according to another aspect of the present invention includes: forming a crystalline silicon layer on a substrate; forming a wiring layer including the signal lines away from the crystalline silicon layer; forming a gate insulating layer on the crystalline silicon layer and the wiring layer; forming a gate electrode layer including a gate electrode, the scanning lines, and a capacitor electrode on the gate insulating layer; forming an interlayer insulating film on the gate electrode layer and the gate insulating layer; and forming a pixel electrode layer on the interlayer insulating film and electrically connecting the pixel electrode with the wiring layer and the crystalline silicon layer through a contact hole formed in the interlayer insulating film and the gate insulating layer.

According to the present invention, it is possible to provide a display device capable of suppressing variations in characteristics of a thin film transistor including a crystalline silicon layer as a channel active layer with a simple structure and a method of manufacturing the display device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described. The following description about the embodiment of the present invention is given for illustrative purposes, and the present invention should not be construes as being limited to the following embodiments.

First Embodiment

Referring toFIGS. 1 and 2, a display device according to a first embodiment of the present invention is described below. The display device of the present invention is an active matrix display device including a thin film transistor as a switching element. Here, a transmissive type active matrix liquid crystal display device is described as an example of the display device.FIG. 1is a plan view of the structure of a liquid crystal display device100of this embodiment.FIG. 2is a sectional view of the structure of the liquid crystal display device100of this embodiment. Incidentally, an opposing substrate or the like is omitted fromFIG. 1for ease of illustration.

As shown inFIGS. 1 and 2, the liquid crystal display device100includes a liquid crystal display panel101and a backlight102. The liquid crystal display panel101displays an image based on an input display signal. The backlight102is placed on the opposite side to a display side of the liquid crystal display panel101, and applies light from the rear side of the liquid crystal display panel101. The liquid crystal display panel101includes a thin film transistor array substrate (TFT array substrate)103, an opposing substrate104, a seal member105, a liquid crystal106, a spacer107, a gate line (scanning line)108, a source line (signal line)109, an orientation film110, an opposing electrode111, a polarizing plate112, a gate driver IC113, and a source driver IC114. A feature of the present invention resides in the TFT array substrate103as described in detail later.

As shown inFIG. 1, the liquid crystal display device100of this embodiment includes the TFT array substrate103. In the TFT array substrate103, a display region115and a peripheral region116are formed. The peripheral region116is formed to surround the display region115. In the display region115, plural gate lines108and plural source lines109are formed. The plural gate lines108extend in parallel. Likewise, the plural source lines109extend in parallel. The gate lines108and the source lines109cross each other.

Further, thin film transistors (TFTs)118are formed at intersections between the gate lines108and the source lines109. In the region surrounded by adjacent gate line108and source line109, a pixel electrode (not shown) is formed. Hence, the region surrounded by the adjacent gate line108and source line109corresponds to a pixel117. Thus, the pixels117are arranged in matrix on the TFT array substrate103. The TFT118has a gate connected to the gate line108, a source connected to the source line109, and a drain connected to the pixel electrode. The pixel electrode is made up of a transparent conductive thin film, for example, an ITO (Indium Tin Oxide) film. The region having the plural pixels117corresponds to the display region115.

As shown inFIG. 2, the liquid crystal display panel101is structured such that the liquid crystal106is filled in between the TFT array substrate103, the opposing substrate104opposite to the TFT array substrate103, and the seal member105bonding the two substrates. The two substrates are kept at a predetermined gap with the spacer107. As the TFT array substrate103and the opposing substrate104, for example, an insulating substrate made of glass transmissive of light, polycarbonate, or an acrylic resin can be used.

In the TFT array substrate103, the orientation film110is formed on the above electrode and line. On the other hand, a color filter (not shown), a BM (Black Matrix) (not shown), the opposing electrode111, and the orientation film110are formed on one surface of the opposing substrate104, which opposes the TFT array substrate103. Incidentally, the opposing electrode may be provided on the TFT array substrate103. Further, the polarizing plate112is bonded to the outer surfaces of the TFT array substrate103and the opposing substrate104.

As shown inFIG. 1, in the peripheral region116of the TFT array substrate103, the gate driver IC113and the source driver IC114are provided. The gate line108extends from the display region115up to the peripheral region116. Then, the gate line108is connected to the gate driver IC113at the end of the TFT array substrate103. Likewise, the source line109extends from the display region115up to the peripheral region116. Then, the source line109is connected to the source driver IC114at the end of the TFT array substrate103. The external line119is connected near the gate driver IC113. Further, the external line120is connected near the source driver IC114. The external lines119and120constitute, for example, a wiring board such as an FPC (Flexible Printed Circuit).

Various signals are supplied from the outside to the gate driver IC113and the source driver IC114through the external lines119and120. The gate driver IC113supplies a gate signal (scanning signal) from the outside to the gate line108based on an external control signal. In accordance with the gate signal, the gate lines108are successively selected. The source driver IC114supplies a display signal to the source line109based on an external control signal and display data. Hence, a display voltage corresponding to the display data can be supplied to each pixel electrode.

Incidentally, in this example, the gate driver IC113and the source driver IC114are directly mounted onto the TFT array substrate103with a COG (Chip On Glass) technique, but the present invention is not limited to this structure. For example, the driver IC may be connected to the TFT array substrate103with the TCP (Tape Carrier Package).

On the rear side of the liquid crystal display panel101, the backlight102is provided. The backlight102applies light to the liquid crystal display panel101from the opposite side to the display side of the liquid crystal display panel101. As the backlight102, for example, a general backlight including a light source, a light guide plate, a reflection sheet, a diffusing sheet, a prism sheet, reflection polarizing sheet, and the like can be used.

Here, a method of driving the liquid crystal display device100is described. In each gate line108, the gate driver IC113supplies scanning signals. All TFTs118connected to one gate line108are turned on in accordance with each scanning signal. Then, the source driver IC114supplies a display signal to each source line109, and charges corresponding to the display signal are accumulated in the pixel electrode. A liquid crystal alignment direction is changed between the pixel electrode and the opposing electrode111in accordance with a potential difference between the pixel electrode to which the display signal is written and the opposing electrode111. As a result, an amount of light transmitted through the liquid crystal display panel101is changed. A display voltage is made to vary from one pixel117to another to thereby display a desired image.

Referring now toFIGS. 3 and 4, the TFT array substrate103used in the liquid crystal display device100of this embodiment is described in detail.FIG. 3is a plan view of the structure of the top-gate type TFT118formed on the TFT array substrate103of this embodiment and its vicinities.FIG. 4is a sectional view taken along the line IV-IV ofFIG. 3. In this embodiment, low temperature polysilicon (LTPS) as crystalline silicon is used for a channel active layer of the TFT118formed on the TFT array substrate103.

As shown inFIGS. 3 and 4, the TFT array substrate103includes an insulating substrate1, a polysilicon layer2, a wiring layer3, a gate insulating layer4, a gate electrode5, a capacitor electrode6, an interlayer insulating film7, a pixel electrode layer8, a contact hole9, and a connection pad10. Here, the wiring layer3includes a source line (signal line)109and a connection pad10. Further, the gate electrode layer11includes the gate line (scanning line)108, the gate electrode5, and the capacitor electrode6. Further, the pixel electrode layer8may include a pixel electrode and function as a line.

As the insulating substrate1, a glass substrate or conductive substrate having a protective insulating film formed thereof may be used. On the insulating substrate1, the polysilicon layer2is formed. The polysilicon layer2includes a source region2a, a channel region2b, and a drain region2c. Further, on the insulating substrate1, the wiring layer3is formed on a part of the source region2aand drain region2cof the polysilicon layer2. That is, the wiring layer3extends from the polysilicon layer2to the insulating substrate1. A portion of the wiring layer3corresponding to the source region2ais the source line109. Further, a portion of the wiring layer3corresponding to the drain region2cis the connection pad10. Therefore, the wiring layer3functions as the source line109and functions to constitute a predetermined circuit between the TFT118, the storage capacitor, and the pixel electrode layer8.

As shown inFIG. 4, the wiring layer3has a three-layer structure including an underlying silicon layer3a, a conductive layer3b, and an interfacial conductive layer3c. At an interface with the polysilicon layer2of the wiring layer3, the underlying silicon layer3ais formed. As the underlying silicon layer3a, an amorphous or microcrystal silicon containing a conductive impurity of the same conductivity type as the source region2aand drain region2cof the polysilicon layer2can be used. That is, the wiring layer3is composed of at least the underlying silicon layer3a, and the conductive layer3band interfacial conductive layer3cformed thereon. The underlying silicon layer3anext to the source region2aand drain region2cis a silicon film containing a conductive impurity. Further, the conductive layer3band interfacial conductive layer3cformed on the underlying silicon layer3aare metal films.

As a material for the conductive layer3b, a material resistant to subsequent heat treatment is preferred, and a refractory and conductive material can be used. For example, the conductive layer3bpreferably contains at least one of Ti, Cr, Zr, Ta, W, Mo, TiN, ZrN, TaN, WN, and VN. Incidentally, a line resistance largely contributes to a circuit performance. Thus, if it is necessary to reduce a line resistance, the wiring layer3may mainly contain Al or Cu. At this time, the interfacial conductive layer3cis formed on the conductive layer3b. As the interfacial conductive layer3c, the layer preferably contains at least one of Ti, Cr, Zr, Ta, W, Mo, TiN, ZrN, TaN, WN, and VN. That is, refractory metal or metal compounds are used at the interface with the pixel electrode layer8of the wiring layer3as described later.

Incidentally, in this embodiment, the wiring layer3has a three-layer structure composed of the underlying silicon layer3a, the conductive layer3b, and the interfacial conductive layer3c, but the present invention is not limited thereto. For example, the wiring layer3may have a single-layer structure made of a refractory and conductive material. Further, the layer may be a two-layer structure composed of the underlying silicon layer3aand the conductive layer3bmade of a refractory and conductive material.

Further, in the case of using Cu as a material for the conductive layer3bwithout forming the underlying silicon layer3a, contamination of the polysilicon layer2becomes a problem. In this case, it is preferred to form the interfacial conductive layer3cabove and below the conductive layer3b. That is, the conductive layer3bis sandwiched between the interfacial conductive layers3c. That is, refractory metal such as Ti or metal compounds are used at an interface between the polysilicon layer2of the wiring layer3and the pixel electrode layer8.

As described above, the polysilicon layer2is formed below the wiring layer3, and the underlying silicon layer3aor refractory metal is formed at the interface with the polysilicon layer2of the wiring layer3. Hence, there is a fear that metal contamination proceeds from the wiring layer3to the polysilicon layer2with heat of a laser used for forming the polysilicon layer2. Hence, it is possible to prevent such a situation that a junction of the TFT formed in the silicon layer is deteriorated to increase a leak current.

The gate insulating layer4is formed on the polysilicon layer2and wiring layer3. As the gate insulating layer4, it is important to form a trap level of an electron or hole at the interface with the polysilicon layer2. As the gate insulating layer4, a silicon oxide film or the like can be used. Further, on the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2. Further, on the gate insulating layer4, the capacitor electrode6is formed in accordance with the connection pad10as apart of the wiring layer3. The gate electrode5and capacitor electrode6are formed in the same layer. As shown inFIG. 3, the gate electrode5is used as the gate line108as well. Further, the capacitor electrode6is also used as the common potential line for supplying a common potential to the opposing electrode111. The gate electrode5, the capacitor electrode6, and the gate line108constitute the gate electrode layer11.

To self-align the gate electrode5and the channel region2b, it is preferred to form the gate electrode5and then form the source region2aand drain region2cthrough selective ion implantation with the gate electrode5used as a mask. Thus, a parasitic capacitance of the TFT can be reduced. Incidentally, in the polysilicon layer2below the wiring layer3, an amount of implanted ions is small, but the underlying silicon layer3acan reduce an electrical-connection resistance of the wiring layer3, and the source region2aand drain region2c. Further, the underlying silicon layer3ahas the same conductivity type as the source region2aand drain region2c, and a leak current supplied when the TFT118is turned off can be suppressed.

Further, the capacitor electrode6is formed on the connection pad10as a part of the wiring layer3through the gate insulating layer4to thereby use the connection pad10as a lower electrode of the capacitor. That is, a capacitor can be formed with the capacitor electrode6used as an upper electrode, the gate insulating layer4used as the capacitor insulating film, and the connection pad10used as the lower electrode. As a result, a doping step for forming the lower electrode of the capacitor can be skipped as in the related art. Incidentally, as a capacitor insulating film, a material other than the material of the gate insulating layer4can be used, or the film thickness of the capacitor insulating film is changed to change the capacitor capacitance.

As shown inFIG. 4, on the gate electrode layer11, the interlayer insulating film7is formed. The interlayer insulating film7is formed to prevent hydrogen from spreading from the lower layer of the interlayer insulating film7. If hydrogen is spread from the lower layer of the interlayer insulating film7, dangling bonds of silicon atoms increase to considerably deteriorate TFT characteristics (threshold voltage Vth, electron mobility, etc.). However, the interlayer insulating film7formed on the gate electrode layer11can suppress an increase in dangling bonds of silicon atoms in the polysilicon layer2and at the interface between the polysilicon layer2and the gate insulating layer4due to hydrogen distortion. The interlayer insulating film7preferably includes at least a silicon nitride film. Further, hydrogen is diffused through heat treatment after the formation of the interlayer insulating film7to further reduce dangling bonds of silicon atoms.

On the interlayer insulating film7, the pixel electrode layer8is formed. The pixel electrode layer8is electrically connected to the gate electrode layer11and wiring layer3through the contact hole9passed through the interlayer insulating film7and gate insulating layer4. In this embodiment, since the transmissive type liquid crystal display device100is used, as the pixel electrode layer8, a transparent electrode made of ITO, IZO, or ITZO is used.

Incidentally, if a bottom-emission type organic EL display device is used, a transparent electrode made of ITO, IZO, or ITZO as the pixel electrode layer8similar to the transmissive type liquid crystal display device. Further, if a reflective type liquid crystal display device is used, a reflection electrode made of Al or Ag is used as the pixel electrode layer8. Further, if the top-emission type organic EL display device is used, as the pixel electrode layer8, a laminate of a transparent electrode made of ITO, IZO, or ITZO, and a reflection electrode made of a high-reflection material such as Al or Ag is used.

In order that the pixel electrode layer8is securely electrically connected to the gate electrode layer11and wiring layer3, an interfacial conductive layer is preferably formed on the gate electrode layer11and wiring layer3. Therefore, in this embodiment, the interfacial conductive layer3cis formed on the wiring layer3, the interfacial conductive layer5ais formed on the gate electrode5, and the interfacial conductive layer6ais formed on the capacitor electrode6. The interfacial conductive layer preferably contains at least one of Ti, Cr, Zr, Ta, W, Mo, TiN, ZrN, TaN, WN, and VN as described above.

Referring now toFIGS. 5A to 5E, a method of manufacturing the liquid crystal display device100is described.FIGS. 5A to 5Eare manufacturing process diagrams for explaining the method of manufacturing the liquid crystal display device100of this embodiment. As shown inFIG. 5A, the polysilicon layer2is formed first on the insulating substrate1. To be specific, an amorphous silicon film is formed on the insulating substrate1through plasma CVD (PECVD: Plasma Enhanced Chemical Vapor Deposition), and XeCl excimer laser light (wavelength: 308 nm) or YAG2ω laser light (wavelength: 532 nm) is applied to transform the amorphous silicon film into a polysilicon film. The polysilicon film is photoetched into a predetermined shape to thereby form the polysilicon layer2.

As shown inFIG. 5B, on the insulating substrate1having the polysilicon layer2formed thereon, the wiring layer3is formed next. To be specific, an amorphous silicon film or microcrystal silicon film containing conductive impurities is deposited through PECVD. The underlying silicon layer3ais formed. The conductive impurities are injected as follows: diborane (B2H6) is doped in the case of injecting a p-type impurity or phosphine (PH3) is mixed with silane (SiH4) and doped in the case of injecting an n-type impurity under PECVD. The concentration of the conductive impurity is determined based on concentrations of mixed gases, and diborane and phosphine is preferably diluted with hydrogen etc. beforehand. The microcrystal silicon film is formed by a combination between optimization of an amount of hydrogen diluents upon PECVD and hydrogen plasma treatment. The microcrystal silicon film may be formed through ICP (Inductive Coupled Plasma) CVD as well. Further, a silicon tetrafluoride (SiF4) may be used in place of the silane.

After that, a material for the wiring layer3including the source line109is deposited on the underlying silicon layer3athrough sputtering. As described above, as the wiring layer3, a material resistant to subsequent heat treatment with high property of electrical connection with the pixel electrode layer8is used. Alternatively, as described above, Al, Cu, or the like may be used for the conductive layer3bto reduce the line resistance and covered with the interfacial conductive layer3c.

In this way, after depositing a material for the wiring layer3composed of the underlying silicon layer3a, the conductive layer3b, and the interfacial conductive layer3con the insulating substrate1, a predetermined pattern is formed through photoetching. The wiring layer3can be formed into a predetermined pattern through dry etching with varying etching gases and conditions, but the conductive layer3band interfacial conductive layer3cof the wiring layer3can be formed through wet etching. Further, it is necessary to appropriately determine the kind of the underlying silicon layer3aso as to execute selective etching by utilizing a difference in etching rate from the lower polysilicon layer2. At this time, the wiring layer3is partially formed on a part of the polysilicon layer2. Then, the wiring layer3extends from the polysilicon layer2to the insulating substrate1.

After that, as shown inFIG. 5C, the gate insulating layer4is formed to cover the polysilicon layer2and wiring layer3. As the gate insulating layer4, an SiO2film is preferably formed through PECVD using TEOS (Tetra Ethyl Ortho Silicate). Then, the gate electrode layer11including the gate electrode5, the capacitor electrode6, and the gate line108is formed on the gate insulating layer4. The gate electrode layer11needs to have high property of electrical connection with the pixel electrode layer8. For example, if the pixel electrode layer8is ITO, an Mo alloy or Al alloy having high property of electrical connection with ITO can be selected. Further, the interfacial conductive layers5aand6amade of, for example, TiN having high property of electrical connection with ITO may be formed on the gate electrode layer11.

After the completion of depositing the gate electrode layer11, the gate electrode5and capacitor electrode6are patterned into a predetermined shape through photoetching. As the etching, wet etching or dry etching may be performed. As a result, the gate electrode5and the polysilicon layer2are formed face to face through the gate insulating layer4. Further, the capacitor electrode6and the connection pad10as a part of the wiring layer3are formed face to face through the gate insulating layer4. That is, the capacitor electrode6overlaps with a part of the connection pad10.

After the formation of the gate electrode5, ions are selectively implanted to the source region2aand drain region2cwith the gate electrode5used as a mask to self-align the gate electrode5and the channel region2bof the polysilicon layer2. As a result, the source region2aand drain region2care formed in the polysilicon layer2. Incidentally, an amount of implanted ions is small in the polysilicon layer2below the wiring layer3, but the underlying silicon layer3acan reduce an electrical-connection resistance of the wiring layer3, and the source region2aand drain region2c.

Further, the capacitor electrode6is formed in accordance with the connection pad10as a part of the wiring layer3on the gate insulating layer4to thereby form a capacitor having the capacitor electrode6as the upper electrode and the connection pad10as the lower electrode. At this time, the gate insulating layer4formed between the capacitor electrode6and the connection pad10is a capacitor insulating layer. Incidentally, as the capacitor insulating layer, materials other than the material for the gate insulating layer4can be used. Further, the film thickness of the capacitor insulating film is set different from the film thickness of the gate insulating layer4to thereby change the capacitor capacitance.

As shown inFIG. 5D, the interlayer insulating film7is formed to cover the gate insulating layer4and the gate electrode layer11. As the interlayer insulating film7, as described above, a film for preventing hydrogen from diffusing, that is, a film including a silicon nitride film formed through PECVD can be used. Further, as the interlayer insulating film7, a two-layer structure having a silicon oxide film formed through PECVD with TEOS as a lower layer and a silicon nitride film formed through PECVD as an upper layer is further preferred.

Then, the contact hole9is formed in a predetermined position of the interlayer insulating film7and gate insulating layer4. Thus, the connection pad10is partially exposed. The contact hole9can be formed through dry etching. In general, in the case of the interlayer insulating film7including the silicon oxide film or silicon nitride film, a dry etching selectivity between the interlayer insulating film7and the polysilicon layer2is low. Thus, if the contact hole is directly formed on the polysilicon layer2as in the related art, up to the polysilicon layer2is etched. However, according to this embodiment, the contact hole9is not directly formed on the polysilicon layer2but on the wiring layer3connected to the polysilicon layer2. Therefore, the contact hole9of a stable shape can be formed.

After that, as shown inFIG. 5E, the pixel electrode layer8including the pixel electrode is formed on the interlayer insulating film7. As a result, the pixel electrode of the pixel electrode layer8is electrically connected to the connection pad10as a part of the wiring layer3through the contact hole9passed through the interlayer insulating film7and gate insulating layer4. Further, although not shown, a part of the pixel electrode layer8is electrically connected to a terminal formed at the end of the insulating substrate1. As the pixel electrode layer8, as described above, a transparent electrode made of ITO or the like can be used. Then, a pixel electrode material deposited on the interlayer insulating film7is photoetched into a predetermined shaped to form the pixel electrode and the like.

In this way, the TFT array substrate103is completed. After that, the thus-formed TFT array substrate is used to form the liquid crystal panel101, and the backlight102, the gate driver IC113, the source driver IC114, and the like are mounted to obtain the liquid crystal display device100of this embodiment.

As described above, in the method of manufacturing a liquid crystal display device according to the present invention, the wiring layer3can be partially used as the lower electrode of the storage capacitor. Thus, it is unnecessary to execute a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor unlike the related art. Further, the wiring layer3is directly formed above the source region2aand drain region2cof the polysilicon layer2, so a step of forming the contact hole for the source/drain line can be omitted. As described above, a manufacturing step can be skipped and productivity can be improved.

Second Embodiment

Referring toFIG. 6, a display device according to a second embodiment of the present invention is described next.FIG. 6is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the first embodiment in that the pixel electrode layer8partially comes into contact with the insulating substrate1, and the pixel electrode layer8is connected with the wiring layer3near a region where the pixel electrode layer8comes into contact with the insulating substrate1. Further, the liquid crystal display device100of this embodiment is suitable for a transflective type liquid crystal display device with the wiring layer3used as a reflection electrode and the pixel electrode layer8used as a transparent electrode. Thus, this embodiment describes the transflective type liquid crystal display device100. InFIG. 6, the same components as those ofFIG. 4are denoted by identical reference numerals and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103as shown inFIG. 6is described.

As shown inFIG. 6, the TFT array substrate103of this embodiment includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, the interlayer insulating film7, the pixel electrode layer8, the connection pad10, the gate electrode layer11, and the like. The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1. The wiring layer3is formed on a part of the polysilicon layer2. The source line109as a part of the wiring layer3extends from the source region2aof the polysilicon layer2to the insulating substrate1. Further, the connection pad10as a part of the wiring layer3extends from the drain region2cof the polysilicon layer2to the insulating substrate1. Incidentally, the pixel electrode layer8is formed on the insulating substrate1as described below. Further, the pixel electrode layer8is formed on the interlayer insulating film7and the wiring layer3. That is, the pixel electrode layer8extends from the interlayer insulating film7to the wiring layer3and the insulating substrate1.

In this embodiment, the wiring layer3is made of a material having reflection characteristics. For example, the conductive layer3bof the wiring layer3may be formed of Al, Ag, or the like. Then, the wiring layer3has a three-layer structure including the underlying silicon layer3a, the conductive layer3b, and the interfacial conductive layer3cas described in the first embodiment. Hence, a part of the connection pad10in the wiring layer3can be used as a reflection electrode.

The gate insulating layer4is formed on the polysilicon layer2and the wiring layer3. Further, the gate insulating layer4is formed on a part of the connection pad10. In the region of the connection pad10having no gate insulating layer4, the pixel electrode layer8is directly formed. That is, the connection pad10and the pixel electrode layer8are directly connected. As described above, in this embodiment, a relatively large area can be set aside for connecting the wiring layer3for supplying an image signal to the pixel electrode layer8and the pixel electrode layer8. Further, it is unnecessary to form a contact hole for connecting the pixel electrode layer8and the connection pad10. However, in place of the contact hole for connecting the wiring layer3and the pixel electrode layer8, although not shown inFIG. 6, a contact hole should be formed in the interlayer insulating film7as described below to connect the wiring layer3and the gate electrode5. The contact hole can be formed through the same number of manufacturing steps as that of the first embodiment as shown in ofFIG. 4.

On the gate insulating layer4, the gate electrode layer11including the gate electrode5and capacitor electrode6are formed. On the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2, and the capacitor electrode6is formed in accordance with the connection pad10of the wiring layer3. Thus, in this embodiment, the connection pad10as a part of the wiring layer can be used as a lower electrode of the capacitor. Hence, two steps of a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor and the step of forming the contact hole for the source/drain line can be skipped.

On the gate electrode layer11, the interlayer insulating film7is formed. Then, the pixel electrode layer8is formed on the interlayer insulating film7. Hence, as described above, the pixel electrode layer8extends from the interlayer insulating film7to the connection pad10and the insulating substrate1. As the pixel electrode layer8, a transparent conductive material made of ITO or the like is used. A region having the connection pad10and pixel electrode8aas the reflection electrode out of the pixels117surrounded by the gate line108and the source line109is a reflection region117a. Further, a region having the pixel electrode8aas the transparent electrode out of the pixels117where no connection pad10is formed is a transmissive region117b.

At this time, the pixel electrode layer8on the connection pad10as the reflection electrode is preferably removed as much as possible. As a result, reflectivity of the connection pad10as the reflection electrode can be increased, and brightness in a reflection mode can be improved. Further, the interfacial conductive layer3con the connection pad10as the reflection electrode is removed to further increase the reflectivity.

Third Embodiment

Referring toFIG. 7, a display device according to a third embodiment of the present invention is described.FIG. 7is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the first embodiment in that an interfacial conductive layer3cis formed in place of the underlying silicon layer3aformed at the interface with the polysilicon layer2of the wiring layer3. InFIG. 7, the same components as those ofFIG. 4are denoted by identical reference numerals and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103ofFIG. 7is described below.

As shown inFIG. 7, the TFT array substrate103of this embodiment includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, the interlayer insulating film7, the pixel electrode layer8, the connection pad10, the gate electrode layer11, and the like. The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1. The wiring layer3is formed on a part of the polysilicon layer2. The source line109as a part of the wiring layer3extends from the source region2aof the polysilicon layer2to the insulating substrate1. Further, the connection pad10as a part of the wiring layer3extends from the drain region2cof the polysilicon layer2to the insulating substrate1. In this embodiment, at the interface with the polysilicon layer2of the wiring layer3, no underlying silicon layer3ais formed. That is, the wiring layer3may have a three-layer structure where the conductive layer3bis sandwiched between the interfacial conductive layers3cas shown inFIG. 7.

Further, the gate insulating layer4is formed on the polysilicon layer2and wiring layer3. Then, on the gate insulating layer4, the gate electrode layer11including the gate electrode5and capacitor electrode6are formed. On the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2, and the capacitor electrode6is formed in accordance with, the connection pad10of the wiring layer3. Thus, in this embodiment, the connection pad10as a part of the wiring layer3can be used as a lower electrode of the capacitor. Hence, two steps of a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor and the step of forming the contact hole for the source/drain line can be skipped. Incidentally, as the capacitor insulating film, materials other than the material for the gate insulating layer4are used to change the capacitor capacitance.

As described in the first embodiment, to self-align the gate electrode5and the channel region2b, after the formation of the gate electrode5, the drain region2cis formed through selective ion implantation with the gate electrode5used as a mask, the source region2a. At this time, the wiring layer3formed on the source region2aand drain region2cof the polysilicon layer2hinders the ion implantation. Hence, it is necessary to take a measure such as recuing a film thickness of the gate insulating layer4or a film thickness of the wiring layer3upon the ion implantation.

Further, as the conductive layer3band interfacial conductive layer3cof the wiring layer3, a material having a relatively small ion stopping power is preferred. According to the SRIM (the Stopping and Range of Ions in Matter; James F. Ziegler), materials are ranked in terms of the ion stopping power at an ion energy of 100 to 200 KeV as follows:Ranking of ion stopping power of phosphorous ions: Si<AL<Ti<Zr<Sn<CuRanking of ion stopping power of boron ions: Si<Al<Ti<Zr<Sn<Cu

As understood from the ranking of ion stopping power, Al can be used as the conductive layer3bof the wiring layer3, and as the interfacial conductive layer3c, Ti, Zr and conductive Ti or Zr compounds can be used. Alternatively, as the wiring layer3, a single layer made of Ti, Zr and conductive Ti or Zr compounds may be used. Here, from the viewpoint of wiring resistance, a combination of the Al-made conductive layer3band the interfacial conductive layer3cis preferred.

Further, the injection depth of phosphorous ions for forming an n-type region is about ⅓ of the injection depth of boron ions for forming a p-type region at the same injection energy. Hence, ion implantation for the n-type region is more difficult than that for the p-type region. Hence, in the case of injecting phosphorous ions, if the film thickness of the gate insulating layer4is set to 30 nm, the film thickness of Al of the conductive layer3bof the wiring layer3is set to 65 nm, and the film thickness of Ti of the interfacial conductive layer3cis set to 20 nm in a target region, according to the above SRIM, an injection energy of 100 KeV or more is necessary for injecting phosphorous ions to the polysilicon layer2. If the film thickness of Al of the conductive layer3bof the wiring layer3is set to 160 nm, and the film thickness of Ti of the interfacial conductive layer3cis set to 200 nm, an injection energy of 200 KeV is necessary for injecting phosphorous ions to the polysilicon layer2.

On the other hand, in the case of injecting boron ion, if the film thickness of the gate insulating layer4is set to 30 nm, the film thickness of Al of the conductive layer3bof the wiring layer3is set to 210 nm, and the film thickness of Ti of the interfacial conductive layer3cis set to 20 nm, according to the above SRIM, an injection energy of 100 KeV or more is necessary for injecting boron ions to the polysilicon layer2, the p-type region can be formed more easily that the n-type region.

Then, as shown inFIG. 7, on the gate electrode layer11, the interlayer insulating film7is formed. Further, the contact hole9is formed in the predetermined position of the interlayer insulating film7and gate insulating layer4. On the interlayer insulating film7, the pixel electrode layer8is formed. The pixel electrode layer8is electrically connected to the gate electrode layer11and wiring layer3through the contact hole9passed through the interlayer insulating film7and the gate insulating layer4. Further, the pixel electrode layer8extends from the interlayer insulating film7to the connection pad10and the insulating substrate1.

As described above, the film thickness of the wiring layer3, the gate insulating layer4, or the like is adjusted to thereby appropriately doped ions to the polysilicon layer without forming the underlying silicon layer3aat the interface with the polysilicon layer2of the wiring layer3.

Fourth Embodiment

Referring toFIG. 8, a display device according to a fourth embodiment of the present invention is described.FIG. 8is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the first embodiment in that the wiring layer3on the source region2acomes into contact with the channel region2b. That is, the wiring layer3is formed up to above the channel region2b. InFIG. 8, the same components as those ofFIG. 4are denoted by identical reference numerals, and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103as shows inFIG. 8is described below.

As shown inFIG. 8, the TFT array substrate103of this embodiment includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, the interlayer insulating film7, the pixel electrode layer8, the connection pad10, the gate electrode layer11, and the like. The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1.

The wiring layer3is formed on a part of the polysilicon layer2. The source line109as a part of the wiring layer3extends from the source region2aof the polysilicon layer2to the insulating substrate1. In this embodiment, the source line109comes into contact with the channel region2b. That is, the source line109extends up to below the gate electrode5as described later. In other words, the source line109extends up to above the channel region2b. Incidentally, at the interface with the polysilicon layer2of the wiring layer3, the underlying silicon layer3ais formed. Hence, the conductive layer3bof the wiring layer3is not short-circuited with the channel region2b. Further, the connection pad10as a part of the wiring layer3extends from the drain region2cof the polysilicon layer2to the insulating substrate1.

Further, the gate insulating layer4is formed on the polysilicon layer2and wiring layer3. Then, on the gate insulating layer4, the gate electrode layer11including the gate electrode5and capacitor electrode6are formed. On the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2, and the capacitor electrode6is formed in accordance with, the connection pad10of the wiring layer3. Thus, in this embodiment, the connection pad10as a part of the wiring layer can be used as a lower electrode of the capacitor. Hence, two steps of a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor and the step of forming the contact hole for the source/drain line can be skipped. Incidentally, as the capacitor insulating film, materials other than the material for the gate insulating layer4are used to change a capacitor capacitance. Further, in this embodiment, the gate electrode5is also formed in a position corresponding to an upper portion of the source line109.

Owing to such structure, a source resistance as an important element of the parasitic resistance of the TFT118can be reduced. In particular, in a LDD (Lightly Doped Drain) structure or a GOLD (Gate Overlapped LDD) structure where a conductive impurity concentration in interface regions between the source region2aand the channel region2b/the drain region2cand the channel region2bis reduced, if the source region has the same structure in view of the manufacturing process, the resistance on the source side can be prevented from increasing and the parasitic resistance of the TFT can be reduced.

Fifth Embodiment

Referring toFIG. 9, a display device according to a fifth embodiment of the present invention is described.FIG. 9is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the first embodiment in that the wiring layer3on the source region2aand the wiring layer3on the drain region2ccome into contact with the channel region2b. That is, the wiring layer3extends up to above the channel region2b. InFIG. 9, the same components as those ofFIG. 4are denoted by identical reference numerals, and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. In this example, the structure of the TFT array substrate103as shown inFIG. 9is described below.

As shown inFIG. 9, the TFT array substrate103of this embodiment includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, the interlayer insulating film7, the pixel electrode layer8, the connection pad10, the gate electrode layer11, and the like. The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1.

The wiring layer3is formed on a part of the polysilicon layer2. The source line109as a part of the wiring layer3extends from the source region2aof the polysilicon layer2to the insulating substrate1. In this embodiment, the source line109comes into contact with the channel region2b. That is, the source line109extends up to below the gate electrode5as described later. In other words, the source line109extends up to above the channel region2b. Further, the connection pad10as a part of the wiring layer3extends from the drain region2cof the polysilicon layer2to the insulating substrate1. The connection pad10comes into contact with the channel region2b. That is, the connection pad10extends up to below the gate electrode5as described below. In other words, the connection pad10extends up to above the channel region2b. Incidentally, at the interface with the polysilicon layer2of the wiring layer3, the underlying silicon layer3ais formed. Hence, the conductive layer3bof the wiring layer3is not short-circuited with the channel region2b.

Further, the gate insulating layer4is formed on the polysilicon layer2and wiring layer3. Then, on the gate insulating layer4, the gate electrode layer11including the gate electrode5and capacitor electrode6are formed. On the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2, and the capacitor electrode6is formed in accordance with, the connection pad10of the wiring layer3. Thus, in this embodiment, the connection pad10as a part of the wiring layer3can be used as a lower electrode of the capacitor. Hence, two steps of a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor and the step of forming the contact hole for the source/drain line can be skipped. Incidentally, as the capacitor insulating film, materials other than the material for the gate insulating layer4are used to change the capacitor capacitance. Further, in this embodiment, the gate electrode5is also formed in a position corresponding to an upper portion of the source line109.

Owing to such structure, a source/drain resistance as an important element of a parasitic resistance of the TFT118can be reduced. Further, since the source region2aand drain region2cis covered with the wiring layer3, an ion implantation step for injecting conductive impurities necessary for forming the source region2aand drain region2ccan be skipped. Further, an impurity concentration of the underlying silicon layer3ais controlled to reduce a field intensity at an interface between the drain region2cand the channel region2bto realize the same effects as those of the LDD.

Sixth Embodiment

Referring toFIGS. 10 and 11, a display device according to a sixth embodiment of the present invention is described.FIG. 10is a plan view of the structure of the liquid crystal display device100of this embodiment.FIG. 11is a sectional view taken along the line IX-IX ofFIG. 10. In this embodiment, unlike the first to fifth embodiments, the wiring layer3is not directly connected onto the polysilicon layer2. Incidentally, inFIGS. 10 and 11, the same components as those ofFIGS. 3 and 4are denoted by identical reference numerals, and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103as shown inFIGS. 10 and 11is described below.

As shown inFIGS. 10 and 11, the TFT array substrate103includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, interlayer insulating film7, the pixel electrode layer8, the contact hole9, and the connection pad10. Here, the wiring layer3includes the source line (signal line)109and the connection pad10. Further, the gate electrode layer11includes the gate line (scanning line)108, the gate electrode5, and the capacitor electrode6. Further, the pixel electrode layer8may include the pixel electrode and function as a line.

On the insulating substrate1, the polysilicon layer2is formed. The polysilicon layer2includes the source region2a, the channel region2b, and the drain region2c. Further, on the insulating substrate1, the wiring layer3is formed independently of the polysilicon layer2. That is, the wiring layer3is formed not to contact the polysilicon layer2. In other words, the wiring layer3is formed away from the polysilicon layer2. The wiring layer3functions as the source line109and in addition, forms a predetermined circuit between the TFT118, the storage capacitor, and the pixel electrode layer8. As shown inFIG. 11, in this embodiment, a two-layer structure including the conductive layer3band the interfacial conductive layer3cis employed. On the insulating substrate1, the conductive layer3bis formed. Then, on the conductive layer3b, the interfacial conductive layer3cthat comes into contact with the pixel electrode layer8is formed. That is, the wiring layer3has a structure where the conductive layer3band the interfacial conductive layer3care formed in order on the insulating substrate1. Incidentally, as described above, as the wiring layer3, a single layer made of a refractory conductive material such as Ti may be used. Alternatively, the conductive layer3bmade of Al may be covered with the interfacial conductive layer3cmade of a refractory conductive material and used. Thus, refractory metal or metal compounds are used at the interface of the wiring layer3with the pixel electrode layer8.

On the polysilicon layer2and wiring layer3, the gate insulating layer4is formed. Further, on the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2. Further, on the gate insulating layer4, the capacitor electrode6is formed in accordance with the connection pad10as a part of the wiring layer3. The gate electrode5and capacitor electrode6are formed with the same layer. As shown inFIG. 10, the gate electrode5can be also used as the gate line108. Further, the capacitor electrode6is also used as a common potential line for supplying a common potential to the above opposing electrode111. The gate electrode5, the capacitor electrode6, and the gate line108are formed in the gate electrode layer11.

Further, the interfacial conductive layer3cis preferably formed on the gate electrode layer11and wiring layer3such that the pixel electrode layer8can be well connected with the gate electrode layer11and wiring layer3. Thus, in this embodiment, the interfacial conductive layer3cis formed on the wiring layer3, the interfacial conductive layer5ais formed on the gate electrode5, and the interfacial conductive layer6ais formed on the capacitor electrode6. The interfacial conductive layer preferably contains at least one of Ti, Cr, Zr, Ta, W, Mo, TiN, ZrN, TaN, WN, and VN as described above.

Further, the capacitor electrode6is formed on the connection pad10as a part of the wiring layer3through the gate insulating layer4to use a part of the connection pad10as a lower electrode of the capacitor. That is, a capacitor with the capacitor electrode6used as an upper electrode, the gate insulating layer4used as a capacitor insulating film, and the connection pad10used as a lower electrode can be obtained. As a result, a doping step for forming a lower electrode of the capacitor can be skipped. Incidentally, as the capacitor insulating film, materials other than the material for the gate insulating layer4are used or film thickness of the capacitor insulating film is changed to change the capacitor capacitance.

As shown inFIG. 11, on the gate electrode layer11, the interlayer insulating film7is formed. The interlayer insulating film7is formed to prevent hydrogen from diffusing from a lower layer of the interlayer insulating film7. As described above, if a film including at least a silicon nitride film is used as the interlayer insulating film7, dangling bonds of silicon atoms can be reduced in the polysilicon layer2and at the interface between the polysilicon layer2and the gate insulating layer4due to hydrogen distortion. Further, hydrogen is diffused through heat treatment after the formation of the interlayer insulating film7to further reduce dangling bonds of silicon atoms. The contact hole9is formed in a predetermined position of the interlayer insulating film7. Here, the contact hole9ais formed to connect the connection pad10with the pixel electrode8aof the pixel electrode layer8, and the contact hole9bis formed to connect the pixel electrode8awith the drain region2cof the polysilicon layer2. Further, the contact hole9cis formed to connect the pixel electrode lay electrode8bwith the source region2aof the polysilicon layer2, the contact hole9dis formed to connect the connection electrode8bwith the source line109as a part of the wiring layer3.

On the interlayer insulating film7, the pixel electrode layer8is formed. The pixel electrode layer8is composed of the pixel electrode8aand the connection electrode8b. The pixel electrode8ais connected to the connection pad10and the drain region2cthrough the contact holes9aand9bpassed through the interlayer insulating film7and gate insulating layer4. Further, the connection electrode8bis connected to the source region2aand the source line109through the contact holes9cand9dpassed through the interlayer insulating film7and gate insulating layer4. In this embodiment, since the liquid crystal display device100is a transmissive type, a transparent electrode made of ITO, IZO, or ITZO is used as the pixel electrode layer8. Incidentally, as described above, if a reflective type liquid crystal display device, a bottom-emission type organic EL display device, or a top-emission type organic EL display device is used, an appropriate material is selected for the pixel electrode layer8.

If the pixel electrode layer8is a metal oxide film made of made of ITO, IZO, ITZO, or the like, the source region2ais hardly electrically connected with the drain region2cof the polysilicon layer2because a silicon oxide film grows at the interface of the polysilicon layer2. Thus, in this embodiment, prior to the formation of the pixel electrode layer8, a silicide layer2dis formed at the interface between the polysilicon layer2and the pixel electrode layer8. That is, the polysilicon layer2has the silicide layer2dat the interface with the pixel electrode layer8. As a result, electrical connection between the polysilicon layer2and the pixel electrode layer8can be improved.

To form the silicide layer2d, it is necessary to use metal which silicifies with polysilicon at relatively low temperature and a metal oxide film of which has conductivity. In view of this, as metal to silicify, Co, Ni, Mo, W, or Cr is preferably used. In particular, Co can be readily silicified with the polysilicon layer2under heat treatment at about 400° C. and thus is preferred. If high-temperature treatment at 600° C. or higher is required, it is preferred to form a silicide while thermal strain of the insulating substrate1is suppressed with RTA (Rapid Thermal Annealing) such as lamp annealing. The degree to which the metal is silicified can be adjusted in accordance with an electrical-connection resistance.

Referring now toFIGS. 12A to 12F, the method of manufacturing the liquid crystal display device100of this embodiment is described below.FIGS. 12A to 12Fare a manufacturing process diagram for explaining the manufacturing process of the liquid crystal display device100of this embodiment. Incidentally, in this embodiment, description about the same steps as those of the manufacturing method of the first embodiment is omitted.

As shown inFIG. 12A, the polysilicon layer2is first formed on the insulating substrate1. As described above, the a-Si film is formed, followed by laser annealing to thereby form the polysilicon layer2. As shown inFIG. 12B, on the insulating substrate1having the polysilicon layer2formed thereon, the wiring layer3is formed not to contact the polysilicon layer2. To be specific, materials for the conductive layer3band interfacial conductive layer3care deposited through sputtering on the insulating substrate, and then a predetermined pattern is formed through photoetching. As a result, the wiring layer3is formed away from the polysilicon layer2on the insulating substrate1.

After that, as shown inFIG. 12C, the gate insulating layer4is formed to cover the polysilicon layer2and wiring layer3. The gate insulating layer4is preferably an SiO2film formed through PECVD with TEOS (Tetra Ethyl Ortho Silicate) as described above. Then, the gate electrode layer11including the gate electrode5, the capacitor electrode6and the gate line108is formed on the gate insulating layer4. Further, the interfacial conductive layers5aand6amade of TiN having high property of electrical connection with ITO is formed on the gate electrode layer11. Then, after the deposition of the gate electrode layer11, the gate electrode5and capacitor electrode6are patterned into a predetermined shape through photoetching. As a result, the gate electrode5and the polysilicon layer2are formed face to face through the gate insulating layer4. Further, the capacitor electrode6and the connection pad10as a part of the wiring layer3are formed face to face through the gate insulating layer4.

After the formation of the gate electrode5, ions are selectively doped for forming the source region2aand drain region2cwith the gate electrode5used as a mask to self-align the gate electrode5and the channel region2bof the polysilicon layer2. As a result, the source region2aand drain region2care formed in the polysilicon layer2.

Further, on the gate insulating layer4, the capacitor electrode6is formed in accordance with the connection pad10as a part of the wiring layer3to thereby obtain a capacitor having the capacitor electrode6as the upper electrode and the connection pad10as the lower electrode. At this time, the gate insulating layer4formed between the capacitor electrode6and the connection pad10is a capacitor insulating layer. Incidentally, as the capacitor insulating layer, materials other than the material for the gate insulating layer4may be used, or the film thickness of the capacitor insulating film is made different from the film thickness of the gate insulating layer4to thereby change the capacitor capacitance.

As shown inFIG. 12D, the interlayer insulating film7is formed to cover the gate insulating layer4and the gate electrode layer11. As the interlayer insulating film7, as described above, a film capable of preventing hydrogen diffusion, in other words, a film including a silicon nitride film formed through PECVD may be used. Further, as the interlayer insulating film7, a two-layer structure including a silicon oxide film formed through PECVD with a TEOS as a lower layer and a silicon nitride film formed through PECVD as an upper layer is particularly preferable.

Then, the contact hole9is formed in a predetermined position of the interlayer insulating film7and gate insulating layer4. As a result, the connection pad10of the wiring layer3and the source line109, and the source region2aand drain region2cof the polysilicon layer2are partially exposed. The contact hole9can be formed through dry etching.

After that, the silicide layer2dis formed at the bottom of the contact holes9band9c. To be specific, a metal film for forming the silicide layer2don the interlayer insulating film7and inside the contact hole9is deposited through sputtering. That is, a metal film for forming the silicide layer2dis formed above the polysilicon layer2at the bottom of the contact holes9band9c. Then, the polysilicon layer2and the metal film are annealed at high temperature to thereby form the silicide layer. For example, Co is deposited through sputtering, followed by heat treatment at 400° C. to thereby silicify Co with the polysilicon layer2. As a result, electrical connection between the pixel electrode layer8and the polysilicon layer2can be improved. Incidentally, if high temperature of 600° C. or higher is necessary, it is preferred to form a silicide while suppressing thermal strain of a glass substrate with RTA (Rapid Thermal Annealing) such as lamp annealing. Then, heat treatment is performed to form the silicide layer2don the surface of the polysilicon layer2, after which the remaining metal film for forming the silicide layer is removed through wet etching. As a result, as shown inFIG. 12E, the silicide layer2dcan be formed at the bottom of the contact hole9cformed above the source region2aof the polysilicon layer2and the contact hole9bformed above the drain region2c. Incidentally, the residual on the interlayer insulating film7is removed by slightly etching off the surface. As a result of silicification, it is possible to prevent the pixel electrode layer8from contaminating the polysilicon layer2.

After that, as shown inFIG. 12F, the pixel electrode layer8including the pixel electrode8aand connection electrode8bis formed on the interlayer insulating film7. As a result, the pixel electrode8ais electrically connected to the connection pad10as a part of the wiring layer3through the contact hole9apassed through the interlayer insulating film7and gate insulating layer4. Further, the pixel electrode8ais electrically connected to the drain region2cof the polysilicon layer2through the contact hole9bpassed through the interlayer insulating film7and gate insulating layer4. On the other hand, the connection electrode8bis electrically connected to the source region2aof the polysilicon layer2through the contact hole9cpassed through the interlayer insulating film7and gate insulating layer4. Further, the connection electrode8bis electrically connected to the source line109as a part of the wiring layer3through the contact hole9dpassed through the interlayer insulating film7and gate insulating layer4. Incidentally, although not shown, a part of the pixel electrode layer8is electrically connected to a terminal formed at the end of the insulating substrate1. As the pixel electrode layer8, as described above, a transparent electrode made of ITO or the like can be used. As the pixel electrode layer8, as described above, a transparent electrode made of ITO or the like may be used. Then, a pixel electrode material deposited on the interlayer insulating film7is photoetched into a predetermined shaped to form the pixel electrode and the like.

In this way, the TFT array substrate103is formed. After that, the thus-formed TFT array substrate is used to form the liquid crystal panel101, and the backlight102, the gate driver IC113, the source driver IC114, and the like are mounted to obtain the liquid crystal display device100of this embodiment.

As described above, in the method of manufacturing the liquid crystal display device100according to the present invention, the wiring layer3can be partially used as the lower electrode of the storage capacitor. Hence, a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor can be skipped unlike the related art. Further, since the wiring layer3is directly formed on the insulating substrate1, a contact hole for source/drain lines can be formed through the same step for forming the contact hole for connecting the pixel electrode layer8and the connection pad10. As described above, the number of manufacturing steps can be reduced and productivity can be increased.

Seventh Embodiment

Referring toFIG. 13, a display device according to a seventh embodiment of the present invention is described.FIG. 13is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the sixth embodiment in that the pixel electrode layer8partially comes into contact with the insulating substrate1, and the pixel electrode layer8is connected with the wiring layer3near a region where the pixel electrode layer8comes into contact with the insulating substrate1. Further, the liquid crystal display device100of this embodiment is suitable for a transflective type TFT LCD with the wiring layer3used as a reflection electrode and the pixel electrode layer8used as a transparent electrode. Hence, in this embodiment, the transflective type liquid crystal display device100is described below. InFIG. 13, the same components as those ofFIG. 4are denoted by identical reference numerals and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103ofFIG. 13is described below.

As shown inFIG. 13, the TFT array substrate103of this embodiment includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, the interlayer insulating film7, the pixel electrode layer8, the connection pad10, the gate electrode layer11, and the like. The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1. Further, on the insulating substrate1, the wiring layer3is formed not to contact the polysilicon layer2. Incidentally, the pixel electrode layer8is formed on the insulating substrate1as described below. Further, the pixel electrode layer8is formed on the interlayer insulating film7and the wiring layer3. That is, the pixel electrode layer8extends from the interlayer insulating film7to the wiring layer3and the insulating substrate1.

In this embodiment, the wiring layer3is made of a material having reflection characteristics. For example, the conductive layer3bof the wiring layer3may be formed of Al, Ag, or the like. Then, the wiring layer3has a two-layer structure including the conductive layer3band the interfacial conductive layer3cas described in the sixth embodiment. Hence, a part of the connection pad10in the wiring layer3can be used as a reflection electrode. A region having the connection pad10as the reflection electrode out of the pixels surrounded by the gate line108and the source line109is the reflection region117a. Further, a region having the pixel electrode8aas the transparent electrode out of the pixels117where the connection pad10is formed is the transmissive region117b.

The gate insulating layer4is formed on the polysilicon layer2and wiring layer3. Further, the gate insulating layer4is formed on a part of the connection pad10. In the region of the connection pad10having no gate insulating layer4, the pixel electrode layer8is directly formed. That is, the connection pad10and the pixel electrode layer8are directly electrically connected. As described above, in this embodiment, a relatively large area can be set aside for connecting the wiring layer3for supplying an image signal to the pixel electrode layer8and the pixel electrode layer8. Further, it is unnecessary to form a contact hole for connecting the pixel electrode layer8and the connection pad10. However, in place of the contact hole for connecting the wiring layer3and the pixel electrode layer8, Although not shown inFIG. 13, a contact hole should be formed in the interlayer insulating film7as described below to connect the wiring layer3and the gate electrode5. Hence, there is no large difference in the number of manufacturing steps between this embodiment and the sixth embodiment ofFIG. 11.

On the gate insulating layer4, the gate electrode layer11including the gate electrode5and capacitor electrode6are formed. On the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2, and the capacitor electrode6is formed in accordance with, the connection pad10of the wiring layer3. Thus, in this embodiment, the connection pad10as a part of the wiring layer can be used as a lower electrode of the capacitor. Hence, two steps of a doping step for reducing a resistance of a polysilicon layer for the lower electrode of the storage capacitor and the step of forming the contact hole for the source/drain line can be skipped.

On the gate electrode layer11, the interlayer insulating film7is formed. Further, in the predetermined position of the interlayer insulating film7, the contact hole9is formed. Here, the contact hole9ais formed to connect the connection pad10with the pixel electrode8aof the pixel electrode layer8, and the contact hole9bis formed to connect the pixel electrode8awith the drain region2cof the polysilicon layer2. Further, the contact hole9cis formed to connect the pixel electrode8bwith the source region2aof the polysilicon layer2, the contact hole9dis formed to connect the connection electrode8bwith the source line109as a part of the wiring layer3.

Then, the pixel electrode layer8is formed on the interlayer insulating film7. Hence, as described above, the pixel electrode layer8extends from the interlayer insulating film7to the connection pad10and the insulating substrate1. As the pixel electrode layer8, a conductive material made of ITO or the like can be used. The pixel electrode layer8is composed of the pixel electrode8aand the connection electrode8b. The pixel electrode8ais connected to the connection pad10and the drain region2cthrough the contact holes9aand9bpassed through the interlayer insulating film7and gate insulating layer4. Further, the connection electrode8bis connected to the source region2aand the source line109through the contact holes9cand9dpassed through the interlayer insulating film7and gate insulating layer4.

Further, as described in the sixth embodiment, the silicide layer2dis formed at the interface between the polysilicon layer2and the pixel electrode layer8to improve connection between the polysilicon layer2and the pixel electrode layer8. Incidentally, the pixel electrode layer8on the connection pad10as the reflection electrode is preferably removed as much as possible. As a result, reflectivity of the connection pad10as the reflection electrode can be increased, and brightness in a reflection mode can be improved. Further, the interfacial conductive layer3con the connection pad10as the reflection electrode is removed to further increase the reflectivity.

Eighth Embodiment

Referring toFIG. 14, a display device according to an eight embodiment of the present invention is described.FIG. 14is a sectional view of the structure of the TFT array substrate103used in the liquid crystal display device100of this embodiment. This embodiment differs from the sixth embodiment in that the interfacial conductive layer8cis formed below the pixel electrode layer8. InFIG. 14, the same components as those ofFIG. 4are denoted by identical reference numerals and description thereof is omitted. Further, in this embodiment, as for components other than the TFT array substrate103, the components ofFIGS. 1 and 2can be used. Thus, in this example, the structure of the TFT array substrate103as shown inFIG. 14is described below.

As shown inFIG. 14, the TFT array substrate103includes the insulating substrate1, the polysilicon layer2, the wiring layer3, the gate insulating layer4, the gate electrode5, the capacitor electrode6, interlayer insulating film7, the pixel electrode layer8, the contact hole9, and the connection pad10. Here, the wiring layer3includes the source line (signal line)109and the connection pad10. Further, the gate electrode layer11includes the gate line (scanning line)108, the gate electrode5, and the capacitor electrode6. Further, the pixel electrode layer8may include the pixel electrode and function as a line.

The polysilicon layer2including the source region2a, the channel region2b, and the drain region2cis formed on the insulating substrate1. Further, on the insulating substrate1, the wiring layer3is formed independently of the polysilicon layer2. As shown inFIG. 14, in this embodiment, a two-layer structure including the conductive layer3band the interfacial conductive layer3cis employed. On the polysilicon layer2and wiring layer3, the gate insulating layer4is formed. Further, on the gate insulating layer4, the gate electrode5is formed in accordance with the channel region2bof the polysilicon layer2. Further, on the gate insulating layer4, the capacitor electrode6is formed in accordance with the connection pad10as apart of the wiring layer3. The gate electrode5and capacitor electrode6are formed with the same gate electrode layer11. Further, the interfacial conductive layer5ais formed on the gate electrode5, and the interfacial conductive layer6ais formed on the capacitor electrode6such that the pixel electrode layer8can be well connected with the gate electrode layer11and wiring layer3. Incidentally, in this embodiment, no interfacial conductive layer3ais formed on the wiring layer3.

Further, the capacitor electrode6is formed on the connection pad10as a part of the wiring layer3through the gate insulating layer4, and thus the part of the connection pad10can be used as a lower electrode of the capacitor. That is, the capacitor with the capacitor electrode6used as an upper electrode, the gate insulating layer4used as a capacitor insulating film, and the connection pad10used as a lower electrode can be obtained. As a result, a doping step for forming a lower electrode of the capacitor can be skipped. Incidentally, as the capacitor insulating film, materials other than the material for the gate insulating layer4are used or film thickness of the capacitor insulating film is changed to change the capacitor capacitance.

As shown inFIG. 14, on the gate electrode layer11, the interlayer insulating film7is formed. As described above, as the interlayer insulating film7, a film including at least a silicon nitride film is used and thus dangling bonds of silicon atoms can be reduced in the polysilicon layer2and at the interface between the polysilicon layer2and the gate insulating layer4due to hydrogen distortion. Further, the contact hole9is formed in a predetermined position of the interlayer insulating film7.

On the interlayer insulating film7, the pixel electrode layer8is formed. The pixel electrode layer8is composed of the pixel electrode8aand the connection electrode8b. The pixel electrode8ais connected to the connection pad10and the drain region2cthrough the contact holes9aand9bpassed through the interlayer insulating film7and gate insulating layer4. Further, the connection electrode8bis connected to the source region2aand the source line109through the contact holes9cand9dpassed through the interlayer insulating film7and gate insulating layer4.

Further, at an interface of the pixel electrode layer8with the interlayer insulating film7, the interfacial conductive layer8cis formed. Further, the interfacial conductive layer8cis formed up to inside the contact hole9. That is, at the interface of the pixel electrode layer8with the polysilicon layer2and with the wiring layer3, the interfacial conductive layer8cis formed. As a result, electrical connection between the polysilicon layer2and the pixel electrode layer8, and between the wiring layer3and gate electrode layer11can be easily improved. As a result, an electrical connection property can be easily improved with fewer steps than the manufacturing steps of the above sixth embodiment. Incidentally, in this embodiment, if the pixel electrode layer8is made of a transparent conductive material, the transparency may be deteriorated. Hence, it is preferably used for a light emitting display device such as top-emission type organic EL or reflection-type liquid crystal display device.

As described above, the wiring layer3including the source line109is formed below the gate insulating layer4to be the same layer as the polysilicon layer2for forming the source region2a/drain region2cor overlap with the polysilicon layer2to thereby use the wiring layer3as a lower electrode of the storage capacitor. Further, the wiring layer3can be directly connected to the source region2a/drain region2c, so the step of forming a contact hole for source/drain lines can be skipped. Further, the wiring layer3can be used as the lower electrode of the storage capacitor, so it is unnecessary to perform the doping step for forming a lower electrode of the storage capacitor and a doping step for reducing a resistance of a polysilicon layer unlike the related art.

As described above, according to the present invention, the 8 patterning steps necessary for the LTPS TFT LCD of the related art can be reduce to 6 steps. Further, is a single channel structure similar to the a-Si TFT LCD structure is used in place of the above complementary-type MOS (CMOS) structure, according to the present invention, the LTPS TFT can be formed through as many patterning steps as those necessary for the a-Si TFT LCD. Thus, the number of patterning steps for the LTPS TFT is reduced, and productivity can be improved.

Further, in the transflective type TFT LCD, the wiring layer is used as the reflection electrode to thereby omit the step for forming a reflection electrode. Thus, the reflection-type LCD can be manufactured through as many patterning steps as those necessary for the transmissive type LCD.

Incidentally, the above embodiments describe the SA (Self Aligned) TFT, but the present invention is not limited thereto. For example, the same effects can be attained with an LDD (Lightly Doped Drain) TFT and GOLD (Gate-Overlapped LDD) TFT. Further, the present invention produces similar effects if applied to an active matrix display device using, for example, a microcrystal silicon TFT made of crystalline silicon formed by various methods as well as existing LTPS TFTs made of polysilicon formed through the above laser annealing. Further, the present invention is applicable to not only the LCD but also the other active matrix display device such as an active matrix organic EL display device.