Virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus

Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to ways and techniques to send general purpose input/output (GPIO) signals through a virtual channel.

Computing devices have become increasingly common in current society. Computing devices have evolved from large cumbersome devices with limited functionality into small, portable multi-function, multimedia devices. These myriad functions are enabled by integrated circuits (ICs) within the computing devices. In general, there has been substantial pressure to make the ICs smaller and faster.

Typically, a computing device may incorporate multiple ICs that communicate with one another to effectuate various functions. Various protocols and communication buses have evolved to allow the ICs to communicate with one another. In many instances these protocols and communication buses are tailored to particular functions that are being enabled by the protocols or buses. In other instances, such communication may fall outside a protocol, but still need to be conveyed between ICs. One technique to allow such communication to pass is referred to as general purpose input/output (GPIO). GPIO signals typically require a pin or bump to be present on the IC to couple to a conductive trace to carry the signal between ICs. Such pins or bumps are, in relative terms, expensive both from a material cost as well as consuming area on the ICs. Such pins may also require additional circuitry (with its own added expense and area penalty) within the ICs to send and receive signals through the pin or bump.

In general, such added expense and added area consumption are considered undesirable for most ICs. Accordingly, various efforts have been made to send GPIO signals over pre-existing pins. Such efforts are sometimes referred to as Virtual GPIO (VGI). At the time of this writing, such efforts have been directed to protocols and communication schemes such as system power management interface (SPMI) and Improved Inter Integrated Circuit (I3C). While effective at reducing pin requirements and consolidating circuitry, such efforts require overhead to package the messages in a format acceptable to such buses and the corresponding routing within the ICs. Accordingly, there is a need to find better ways to effectuate VGI.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

In this regard in one aspect, an integrated circuit (IC) is disclosed. The IC includes a bus interface configured to couple to a TDM bus. The IC also includes a transceiver coupled to the bus interface and configured to send signals and receive signals over the TDM bus through the bus interface. The IC also includes a logic element coupled to the transceiver and providing to the transceiver at least one GPIO signal. The IC also includes a control system. The control system is configured to cause the transceiver to send the at least one GPIO signal in a first TDM slot over the TDM bus.

In another aspect, an IC is disclosed. The IC includes a bus interface configured to couple to a TDM bus. The IC also includes a transceiver coupled to the bus interface and configured to send signals and receive signals over the TDM bus through the bus interface. The IC also includes a logic element coupled to the transceiver and receiving from the transceiver at least one GPIO signal. The IC also includes a control system. The control system is configured to cause the transceiver to receive the at least one GPIO signal in a first TDM slot over the TDM bus.

In another aspect, a method of sending a GPIO signal over a bus is disclosed. The method includes placing a raw GPIO signal within a TDM slot in a TDM frame. The method also includes sending from a first IC the TDM frame over a TDM bus to a second IC.

In another aspect, a method of sending a GPIO signal over a bus is disclosed. The method includes receiving at a first IC a TDM signal including one or more TDM slots. The method also includes extracting from one of the one or more TDM slots a raw GPIO signal.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

Before addressing exemplary aspects of the present disclosure, a brief overview of a conventional GPIO communication system is provided with reference toFIG. 1. A discussion of exemplary aspects of the present disclosure begins below with reference toFIG. 2.

In this regard,FIG. 1is a block diagram of a computing system100having a first integrated circuit (IC)102and a second IC104. The first IC102includes a control system106(referred to in the drawings as CS) that generates information and/or uses information that is received. The first IC102further includes a physical layer (PHY)108coupled to a first input pin110and a first output pin112. While not explicitly illustrated, the PHY108includes necessary and sufficient structure to act as a transceiver to send and receive signals through the first input pin110and the first output pin112. In this regard, the PHY108may sometimes be referred to as a bus interface. The first input pin110is coupled to a first conductive trace114that may be on a printed circuit board or other support structure. Similarly, the first output pin112is coupled to a second conductive trace116that may also be on a printed circuit board or the like. The first conductive trace114is also coupled to a second output pin118on the second IC104while the second conductive trace116is coupled to a second input pin120on the second IC104. The second IC104further includes a PHY122similar to the PHY108. The second IC104further includes a second control system124. The second control system124likewise generates information and/or uses information that is received. In use, the control systems106and124communicate through the PHYs108and122using a GPIO protocol. This use makes the pins110,112,118, and120GPIO pins. Thus, to achieve bidirectional communication, four pins are required along with the associated conductive traces114and116. The presence of the pins110,112,118, and120add to the expense of the first IC102and the second IC104as well as make the first IC102and the second IC104larger and more complex by virtue of the presence of the PHYs108and122.

Exemplary aspects of the present disclosure allow for VGI, which helps reduce the need for dedicated GPIO pins. Further, by placing the VGI in a TDM bus using a TDM protocol, the information that would normally be sent through a GPIO pin is concurrently available to multiple ICs with minimal latency and no additional overhead.

In this regard,FIG. 2provides a block diagram of a computing system200having a first IC202and a second IC204. The first IC202includes a control system206and a logic element208that sends and/or receives GPIO signals from a TDM bus PHY210. The TDM bus PHY210converts GPIO OUT signals by placing them into channels within a TDM stream for transmission over a TDM bus212. The TDM bus PHY210also extracts GPIO IN signals that are within channels on the TDM bus212. The GPIO IN signals are passed to the logic element208. Again, while not explicitly illustrated, the TDM bus PHY210includes necessary and sufficient structure to act as a transceiver to send and receive signals over the TDM bus212. Thus, the TDM bus PHY210may likewise sometimes be referred to as a bus interface. The second IC204is also coupled to the TDM bus212, through a second PHY214that handles TDM slots in similar fashion. The second PHY214receives GPIO OUT signals from a logic element216and sends GPIO IN signals to the logic element216. Likewise a control system218may further control the operation of the second IC204.

With continued reference toFIG. 2, as illustrated, the first IC202may be a master relative to the TDM bus212and the second IC204may be a slave relative to the TDM bus212. In a master/slave arrangement, the control system206of the first IC202may designate into which TDM slots which channels are assigned and provide a clock signal (not illustrated) to the TDM bus212to allow the second IC204to synchronize to the TDM bus212. Where there is not a master/slave arrangement between the first IC202and the second IC204, there may be other rules that allow the TDM slots to be assigned.

By placing the GPIO signals into TDM slots, there is no need for additional overhead and there is no need for dedicated GPIO pins and the GPIO PHYs. Further, signals sent across the TDM bus212arrive with relatively little latency. As used herein, “little latency” may also be referred to within the industry as “short latency.” The latency benefits are more pronounced in a multi-drop bus, as explained in greater detail below with reference toFIGS. 3 and 4.

FIG. 3illustrates a computing system300having a multi-drop TDM bus coupling multiple ICs. In particular, the computing system300includes a first IC302coupled to multiple slave ICs304(1)-304(N), where as illustrated N=3. The first IC302is substantially similar to the first IC202ofFIG. 2and operates as a master for a TDM bus306. Likewise, the slave ICs304(1)-304(N) are similar to the second IC204. Thus, the first IC302includes a control system308and a logic element310that sends and/or receives GPIO signals from a TDM bus PHY312. The TDM bus PHY312converts GPIO OUT by placing them into channels within a TDM stream for transmission over the TDM bus306. The TDM bus PHY312also extracts GPIO IN signals that are within channels on the TDM bus306. The GPIO IN signals are passed to the logic element310. Again, while not explicitly illustrated, the TDM bus PHY312includes necessary and sufficient structure to act as a transceiver to send and receive signals over the TDM bus306and may be referred to as a bus interface.

With continued reference toFIG. 3, a slave IC304(N) includes a control system314and a logic element316that sends and/or receives GPIO signals from a TDM bus PHY318. The TDM bus PHY318converts GPIO OUT signals by placing them into channels within a TDM stream for transmission over the TDM bus306. The TDM bus PHY318also extracts GPIO IN signals that are within channels on the TDM bus306. The GPIO IN signals are passed to the logic element316. The other slave ICs304(1)-304(N−1) have similar elements and further discussion is omitted.

While the TDM bus306may be any multi-drop TDM bus, it should be appreciated that sometimes audio buses are underutilized and have ready bandwidth with which to accommodate GPIO signals without affecting audio quality or other performance metrics. While audio buses are specifically contemplated as being suitable for carrying the VGI signals described herein, it should be appreciated that the SOUNDWIRE protocol and the SLIMbus protocol, both promulgated by the MIPI Alliance, are specific examples of appropriate multi-drop audio TDM buses suitable for use with the present disclosure.

In this regard,FIG. 4illustrates a computing system400having a first master IC402coupled to a plurality of slave ICs404(1)-404(N) through a SOUNDWIRE bus406. As illustrated, the first master IC402has a logic element408that generates GPIO output signals GPx0-GPx7and a logic element410that receives GPIO input signals GPy0-GPy3and GPz0-GPz3. Note that the logic elements408and410may be the same logic element. In operation, the logic element408passes the GPIO signals GPx0-GPx7to a PHY412that places them in an appropriate TDM slot for transmission on the SOUNDWIRE bus406. Likewise, slave IC404(1) has a logic element414that generates the GPIO signals GPy0-GPy3and a logic element416that receives the GPIO signals GPx0-GPx7and GPz0-GPz3. Note that the logic elements414and416may be the same logic element. Similarly, slave IC404(N) has a logic element418that generates the GPIO signals GPz0-GPz3and a logic element420that receives the GPIO signals GPx0-GPx7and GPy0-GPy3. Note that the logic elements418and420may be the same logic element. The slave IC404(1) has a PHY422that sends the GPIO signals GPy0-GPy3in slots over the SOUNDWIRE bus406and extracts the GPIO signals GPx0-GPx7and GPz0-GPz3from slots in the SOUNDWIRE bus406. Similarly, the slave IC404(N) has a PHY424that sends the GPIO signals GPz0-GPz3in slots over the SOUNDWIRE bus406and extracts the GPIO signals GPx0-GPx7and GPy0-GPy3from slots in the SOUNDWIRE bus406. Note that the logic elements408,410,414,416,418, and420may include registers426,428,430,432,434,436,438,440, and442that hold the GPIO signals as needed or desired.

WhileFIG. 4illustrates a comprehensive GPIO transport solution that allows all devices to see all GPIO signals, the present disclosure is not so limited. In an alternate aspect, only a subset of devices may receive specific GPIO signals. For example, GPx0-GPx7driven from the first master IC402may be addressed to the slave IC404(1) but not the slave IC404(N) and thus are not read from the SOUNDWIRE bus406by the slave IC404(N). Likewise, it is possible that only a portion of a specific set of GPIO signals is received at a destination. For example, GPx0-GPx3(but not GPx4-GPx7) may be received by the slave IC404(N) and GPx4-GPx7are received by the slave IC404(1) (but not GPx0-GPx3).

FIG. 5provides a flowchart of the computing system400in operation. As such, the process assumes that the bus406is a SOUNDWIRE bus and that SOUNDWIRE protocols are used to send and receive frames as set forth in the process. In this regard, a process500begins with the start of the TDM bus (e.g., the TDM bus306ofFIG. 3or the SOUNDWIRE bus406ofFIG. 4) (block502). The “start” may be on power up or other event after manufacture. The master enumerates the drops on the bus (block504). The master defines a frame size and allocates slots within the frame to GPIO information (block506). Note, as better explained below, the allocation of slots may try to optimize placement of the slots within the frame in slots that are unsuitable for use as an audio channel. Note further that the slot assignments may define the data width, reflecting a number of GPIO slots per channel, any data offset, reflecting a position in the frame, and a data sample interval, reflecting a maximum latency for real time updates. After enumeration and slot assignment, a device may generate GPIO information (block508) and pass this GPIO information to an associated register (block510). The PHY reads the register and puts the raw GPIO information into the appropriate slot in the frame (block512). As used herein, raw GPIO is defined to be without any additional overhead. Thus, the original GPIO interface bus will appear after short latency on all the corresponding GPIO internal signals. Where relevant, the present disclosure uses “GPIO” for all signals while VGIO is used for internal signals received and delivered from inside the core versus the legacy GPIO interface.

With continued reference toFIG. 5, the PHY then transmits the GPIO information in the assigned slots (block514). All other devices on the bus receive the GPIO information essentially concurrently and essentially in real time (block516). Essentially in this case means that minor variations caused by different travel times (e.g., device A is further from device B than device C, so device C receives the information before device B, but both receive the GPIO information essentially concurrently (within picoseconds of each other). In practice, the devices may accumulate data being received on each of the GPIO channels and hold the data until the end of a frame. At the end of the frame, the accumulated data is released to logic within the device. This release also occurs at essentially the same time. As used herein, the delay of a single frame, such as through this accumulation and release, is considered to be short enough to be essentially real time. The receiving device reads the slot with the GPIO information (block518) and extracts the raw GPIO information. The receiver PHY then passes the raw GPIO information to a destination logic element (block520).

The ability for the GPIO information to be shared amongst multiple devices in essentially real time as if a physical GPIO link was connecting them but without incurring the extra GPIO pin penalty improves performance and allows for continued size reduction of ICs. Likewise, this arrangement allows slave-to-slave communication, master-to-slave communication, slave-to-master communication, point-to-point, and point-to-many options. Likewise, by using the TDM slots assigned by the master, there is no need to add source or addressing information or add overhead with routing instructions.

As noted above, aspects of the present disclosure are well suited for use with a SOUNDWIRE bus such as the SOUNDWIRE bus406ofFIG. 4. SOUNDWIRE provides for a number of different frame sizes, and while any frame size can accommodate the TDM slots containing GPIO signals, a few frames are illustrated inFIG. 6showing how the VGI TDM slots may be optimized. In this regard,FIG. 6illustrates frames600A-600D. Frame600A is forty-eight rows by two columns602A and604A. In the SOUNDWIRE specification, control information occupies the first forty-eight rows of the first column602A and the data channels (i.e., payload) go in the remaining rows of the second column604A. Given that all channels are in a single column, there is little that can be done to optimize the frame600A by placing a TDM slot having VGI data in a particular spot. Somewhat similarly, frame600B is forty-eight rows by four columns. The first column602B is again taken up by control information, leaving the columns604B available for payload. Again, there is no specific placement of the TDM slots having the VGI channel in the frame600B that provides an advantage over another location. In contrast, frame600C is sixty-four rows by four columns. The first column602C has a first segment606C of forty-eight rows occupied by control information and a second segment608C of sixteen rows that are not occupied by control information, but may be too few rows to accommodate audio data. Accordingly, the second segment608C of sixteen rows in the first column602C is well suited for placement of the TDM slots having the VGI channel, leaving the columns604C free for audio channel TDM slots. Likewise, frame600D has fifty rows by sixteen columns. The first column602D has a first segment606D of forty-eight rows taken by control information, leaving a second segment608D of just two rows. These two rows of the second segment608D are too few to handle an audio channel TDM slot, but may advantageously be used for the TDM slots having the VGI channel, leaving the columns604D free for audio channel TDM slots.

FIG. 7provides a more granular view of the frame600C. Specifically, continuing the example fromFIG. 4, a channel700is formed of eight slots that hold the GPIO signals GPx0-GPx7, a second channel702is formed of four slots that hold the GPIO signals GPy0-GPy3, and a third channel704is formed of four slots that hold the GPIO signals GPz0-GPz3. All three channels700,702, and704are advantageously placed in the same column602C that holds a control channel706.

The systems and methods for providing VGI over a TDM bus according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard,FIG. 8is a system-level block diagram of an exemplary mobile terminal800such as a smart phone, mobile computing device tablet, or the like. While a mobile terminal having a SOUNDWIRE bus is particularly contemplated as being capable of benefiting from exemplary aspects of the present disclosure, it should be appreciated that the present disclosure is not so limited and may be useful in any system having a TDM bus.

With continued reference toFIG. 8, the mobile terminal800includes an application processor804(sometimes referred to as a host) that communicates with a mass storage element806through a universal flash storage (UFS) bus808. The application processor804may further be connected to a display810through a display serial interface (DSI) bus812and a camera814through a camera serial interface (CSI) bus816. Various audio elements such as a microphone818, a speaker820, and an audio codec822may be coupled to the application processor804through a serial low power interchip multimedia bus (SLIMbus)824. Additionally, the audio elements may communicate with each other through a SOUNDWIRE™ bus826. A modem828may also be coupled to the SLIMbus824and/or the SOUNDWIRE bus826. The modem828may further be connected to the application processor804through a peripheral component interconnect (PCI) or PCI express (PCIe) bus830and/or a system power management interface (SPMI) bus832.

With continued reference toFIG. 8, the SPMI bus832may also be coupled to a local area network (WLAN) IC (WLAN IC)834, a power management integrated circuit (PMIC)836, a companion IC (sometimes referred to as a bridge chip)838, and a radio frequency IC (RFIC)840. It should be appreciated that separate PCI buses842and844may also couple the application processor804to the companion IC838and the WLAN IC834. The application processor804may further be connected to sensors846through a sensor bus848. The modem828and the RFIC840may communicate using a bus850.

With continued reference toFIG. 8, the RFIC840may couple to one or more RFFE elements, such as an antenna tuner852, a switch854, and a power amplifier856through a radio frequency front end (RFFE) bus857. Additionally, the RFIC840may couple to an envelope tracking power supply (ETPS)858through a bus860, and the ETPS858may communicate with the power amplifier856. Collectively, the RFFE elements, including the RFIC840, may be considered an RFFE system862. It should be appreciated that the RFFE bus857may be formed from a clock line and a data line (not illustrated).