Multilevel power supply

According to an embodiment there is provided a multilevel power supply comprising two power sources that share a common node, a switching arrangement, a charge storage device and an output terminal. The two power sources are configured to provide a first potential V1, a second potential V2 and a third potential V3, wherein V1>V2>V3. The switching arrangement is configured to charge the charge storage device between potentials V1 and V3 in a first switching state and to connect the charge storage device between potential V2 and the output in a second switching state.

FIELD

Embodiments described herein generally relate to the field of multilevel power supplies and to methods of generating multiple power output levels.

BACKGROUND

Known multilevel power supplies suffer from a number of disadvantages including a need for complex driving signals and/or isolation networks and a need to use separate input power supplies from each other.

DETAILED DESCRIPTION

According to an embodiment there is provided a multilevel power supply comprising two power sources that share a common node, a switching arrangement, a charge storage device and an output terminal. The two power sources are configured to provide a first potential V1, a second potential V2and a third potential V3, wherein V1>V2>V3. The switching arrangement is configured to charge the charge storage device between potentials V1and V3in a first switching state and to connect the charge storage device between potential V2and the output in a second switching state.

The switching arrangement may be configured to connect the output to potential V2in a third switching state and/or to potential V1or V3in a fourth switching state.

The output may be a first stage output. The multilevel power supply may further comprise a second charge storage device with a second stage output. The switching arrangement can be configured to, in a fifth switching state, connect the second charge storage device between the first and second stage outputs when the first charge storage device is connected between potential V2and the first stage output node.

The output may be a first stage output. The multilevel power supply may further comprise a second charge storage device with a second stage output. The switching arrangement is configured to, in a fifth switching state, connect the second charge storage device for charging between the first stage output node and potential V1or potential V3when the first charge storage device is connected between potential V2and the first stage output node.

A variable attenuator may further be provided in series with the output. The attenuator may provide for an adjustable attenuation of the output voltage. An example of such a variable attenuator, to be explained below, is the element Q22ofFIG. 11. In another example, to be explained below with reference toFIG. 12, a variable attenuator such as the element Q66is provided, and a further variable attenuator such as the element Q68is provided between the output and a further power source V15. A driver circuit such as the driver circuit102ofFIG. 12can be provided to supply a driving signal to the attenuator and/or to the further attenuator for adjusting the amount of attenuation provided by the attenuator.

According to another embodiment there is provided a bipolar multilevel power supply that comprising a first multilevel power supply as described above and a second multilevel power supply as described above. The architecture of the second multilevel power supply is symmetric with the architecture of the first multilevel power supply. The potential V3of the first multilevel power supply and the potential V1of the second multilevel power supply are the same. Both these potentials may be the ground potential. The switching devices in the first and second multilevel power supplies may have opposite polarities.

According to another embodiment there is provided a bipolar multilevel power supply comprising a positive and a negative stage. Each of the positive and the negative stage comprising a multilevel power supply as described above. The bipolar multilevel power supply may further comprise a transformer with a secondary side connectable to a load. The transformer has a first, a second and a common terminal. The first terminal is connected or connectable to the output of the positive stage and the second terminal is connected or connectable to the output of the negative stage. The common terminal is connected to potential V1or V3.

The switching arrangements of any of the above described multilevel power supplies can comprise MOSFETs.

The multilevel power supply may comprise a signal source configured to supply binary signals to switches within the switching device.

According to an embodiment there is provided a base station or transmitter, such as the base station or transmitter100ofFIG. 2, comprising a multilevel power supply as described above.

According to an embodiment there is provided a method of generating multiple power output levels comprising charging a first charge storage device by connecting it between a first potential V1of a first power supply and a second potential V3of a second power supply and subsequently connecting the first charge storage device between a third potential V2shared by the first and second power supply and an output, wherein V1>V2>V3.

The output may be a first stage output and the method may further comprise charging, in one switching state, a second charge storage device between V1and V3and/or, in another switching state, between a potential generated at a terminal of the first charge storage device connected to the output when another terminal of the first charge storage device is connected to V2and either of V1and V3and connecting the second charge storage device in series with the first charge storage device between V2and a second stage output.

The above described embodiments are suitable for use with amplifiers intended for high PAPR modulation scheme like OFDM, for example the LTE or DVB standards, using envelope tracking and modulation. Embodiments extend to amplifiers for use in such high PAPR modulation schemes and that comprise a multilevel power supply as described above.

FIG. 1shows a known charge pump voltage doubler. As is know, the voltages applied to the gates of transistors Q55and Q58are out of phase with each other, so that, at any given point in time, only one of the two transistors Q55and Q58is conducting.

In a switching state where transistor Q58is conducting and transistor Q55is not conducting both of the capacitors C16and C17are in parallel to the voltage source V21. Capacitor C16is therefore charged to the output voltage of voltage source V21in this switching state.

In a switching state where transistor Q55is conducting and transistor Q58is not conducting the capacitors of C16and C17are switched in series. This means that the terminal capacitor C17shares with a diode D50is at a potential that is the sum of the voltage provided by the voltage source V21and the voltage stored in capacitor C16. Consequently capacitor C17is charged to twice the output voltage of voltage source V21in this switching state after a number of initial switching cycles until sufficient charge has been passed to capacitor C17. The presence of the diode D50prevents leakage of charges stored in capacitor C17into capacitor C16in the switching state where transistor Q58is conducting and transistor Q55is not conducting. Diode D49disconnects the upper terminal of the capacitor C16from the power supply when the potential of the node shared by diodes D49and D50exceeds the supply voltage.

FIG. 2shows a multilevel power supply that is controlled by two binary inputs according to one embodiment.FIG. 3illustrates the various voltage states that can be present on nodes V3, V4and on the output node V5depending on the input signals IN_1and IN_2as well as the switching state of transistors Q1, Q2and Q3. It will of course be appreciated that the aim of the circuit shown inFIG. 2is to generate the various output voltages indicated inFIG. 3as being present on node V5. Generating these voltages includes charging and discharging capacitor C1. The charging and discharging states of this capacitor are shown in the last line ofFIG. 3. It will moreover be appreciated that, while transistors Q1and Q2have different polarities and can consequently be switched using a single input signal, signal IN_1, two separate transistors with the same (or different) polarity and switched with two separate input signals may instead be used if the separate input signals are out of phase (for transistors having the same polarity; in a manner discussed above with reference to the charge pump ofFIG. 1) or in phase (for transistors having opposing polarities).

Transistor Q1is a n-channel MOSFET that conducts when input signal IN_1is high and that does not conduct when input signal IN_1is low. Transistor Q2is a p-channel MOSFET that exhibits a switching behaviour opposite to that of transistor Q1. When input signal IN_1is low transistor Q2is conducting and transistor Q1is not conducting. Capacitor C1is therefore connected between the positive terminal of voltage source V1and the negative terminal of voltage source V2and is charged to a voltage corresponding to the sum of voltages V1and V2(which in the embodiment corresponds to 2*V1, given that in the embodiment V2=V1). This indicated in the last line (labelled “C1”) inFIG. 3.

The output voltage achieved at node V5during charging cycles (that is when input signal IN_1is low) is dependent on the switching state of the second input signal, input signal IN_2. The output voltage generated for the different combination of switching states for IN_1and IN_2are discussed in the following.

If IN_2=High Q3is conducting. In this case node V5is connected to the negative terminal of voltage source V2. The output voltage at node V5therefore corresponds to the output voltage at the negative terminal of voltage source V2. This output voltage is, in the embodiments shown, −V1. Diode D1decouples nodes V3and V5from each other in this case. The voltage difference across the load resistor RL in the switching state is therefore 2*V1

If Q3is not conducting (IN_2=Low) output node V5is connected to the positive terminal of voltage source V1(via diode D1), so that the output voltage provided at node V5corresponds to the voltage at the positive terminal of voltage source V1. As a consequence a zero voltage difference is applied across the load resistor RL.

When the input signal IN_1is High transistor Q2is non-conducting and the transistor Q1is conducting. In this state the positive terminal of voltage source V1is only connected to the positive output terminal, while node V3is connected to ground. The voltage present at output node V5is dependent on the switching state of the transistor Q3.

When transistor Q3is conducting (IN_2=High) then node V5is connected to the negative terminal of capacitor C1. Given that capacitor C1has previously been charged to 2*V1and as the positive terminal of capacitor C1is at ground potential the output voltage at node V5is −2*V1. The presence of diode D2interrupts current flow to voltage source V2. In this switching state the voltage across the output load RL is 3*V1and capacitor C1discharges to node V5via transistor Q3.

When transistor Q3is not conducting (IN_2=Low) then node V5is connected to node V3via diode D1, so that V5is at ground potential. Given that capacitor C1has previously been charged to 2*V1and as the positive terminal of capacitor C1is at ground the potential at node V4is more negative (at −2*V1) than the potential at the negative terminal of voltage source V2. Diode D2consequently prevents a discharging of the capacitor C1in this switching state. In the switching state the voltage across the output load RL is V1.

FIG. 4provides a simplified illustration of the way the three input terminals (labelled V1, 0V and −V2in correspondence with the respective potentials found at the respective terminals of the voltage sources shown inFIG. 2) can be connected to the two output terminals of the circuit ofFIG. 2, depending on the state of the input signals IN_1and IN_2. It will be appreciated that whileFIGS. 4A), B) and C) provide at the output terminals the voltage differences that would normally be available from two series connected power supplies, the switching state shown inFIG. 4D) provides another voltage difference (3*V1) at the output that would not normally be available from a series of two voltage sources. This additional voltage output level is created because of the presence of the charge storage device (in theFIG. 2embodiment specifically a capacitor C1, although the present disclosure should not be read as being limited to capacitive charge storage). Generating this additional output voltage level is possible because the charge storage device has been charged between V1an −V2before the switching state shown inFIG. 4D) is created. The charge storage device thus acts as a floating power supply.

For completeness it is pointed out that the zero Volt potential difference at the output terminals shown inFIG. 4A) could of course alternatively be achieved by connecting both output terminals to the ground potential or to the −V2potential. The V1potential difference shown inFIG. 4C) could equally be achieved by connecting the two output terminals to the ground potential and the −V2potential respectively.

It will equally be appreciated that further output voltage levels other than those illustrated inFIGS. 2 to 4can be generated by switching the charge storage device in series with a potential other than the ground potential. For example, if the charge storage device was provided in series with the positive terminal of the voltage source V1, then the potential at the positive output terminal could be boosted to 3*V1(It will be appreciated that, in order to achieve this the lower terminal of the charge storage device ofFIG. 2would need to be connected to potential V1. Switching devices in addition to those shown inFIG. 2would be required for this purpose). If output terminal V5was at the same time connected to the potential −V2, then (for V2=V1) the potential difference between the two output terminals could be 4*V1).

It will moreover be appreciated that, although the circuit shown inFIG. 2uses two voltage sources with the same voltage output (V1) this is not essential and that voltage sources with two different voltage outputs can be used instead depending the desired voltage output levels at node V5.

The use of capacitor C1inFIG. 2allows common power supplies to be used. This is a significant advantage compared to known cascaded power supply solutions that require separate floating power supplies. Such floating power supply sections of cascaded power supplies often require control through optic isolators. The use of optic isolators can introduce significant delay and increase power consumption. The control of theFIG. 2power supply is, in contrast, simpler due to the use of common power supplies.

The above discussed architecture, as well as the further embodiments described in the following provide a wide bandwidth multilevel power supply that is both efficient in power consumption and the number of power supplies required.

While inFIG. 2power is returned to the positive supply rail via RL, power could equally be returned to the negative supply rail if P-channel MOSFETs were used. A thus modified equivalent of the circuit shown in FIG.2forms the basis of the circuit shown inFIG. 5.FIG. 5shows a version of this circuit that further comprises a cascaded further switching stages between the charge storage device (capacitor C1inFIG. 2and capacitor C4inFIG. 5) and the output switching device (transistor Q3inFIG. 2and transistor Q59inFIG. 5). A further switching device Q60is provided in the circuits shown inFIG. 5to ensure that the intermediate output voltages V6/V7and 2*V7that can be applied to the node shared by diodes D7and D8, capacitor C4and transistor Q60can be applied to the load RL as well as the to the input node of the second switching stage, namely the node shared by the diodes D9and D10and the transistor Q10.FIG. 6shows a voltage level diagram illustrating the potentials generated in theFIG. 5circuit by various combinations of the input signals IN_3to IN_5and IN_10. In the circuit ofFIG. 5V6=V7and the node connecting the two voltage sources is at ground potential. It will, however, be appreciated that the outputs of the two voltage sources do not have to be the same and/or that the shared node between the voltage sources does not have to be at ground potential.

The conductivity state of transistors Q12and Q13switch depends on the same input signal, IN_3. As these two transistors are of opposite polarity one transistor will be non-conductive when the other transistor is conducting. When transistor Q13is conducting capacitor C4is connected between the voltage +V6/+V7and −V7and will therefore charge to a voltage 2*V7. When transistor Q13is switched to the non-conducing state and transistor Q12to the conducting state the node shared by the two transistors is moved to ground potential. The voltage (2*V7) stored in capacitor V4boosts the potential on the node shared by diode D8and capacitor C4to 2*V7above ground. D8is rendered non-conductive and prevents leakage of charges from the capacitor C4into the voltage source V6. This operation of the circuit ofFIG. 5is analogous to the operation of theFIG. 2circuit.

The above discussed first stage of theFIG. 5circuit (comprising diode D8, transistors Q12and Q13and capacitor C4) provides four different voltages on the nodes connecting to the cascaded further switching stage (in the area outlined by dashed lines). These are V7and 2*V7(depending on the switching states of transistors Q12and Q13) at the node shared by capacitor C4and diode D8and ground potential or −V7(again depending on the switching states of transistors Q12and Q13) at the node shared by transistors Q12and Q13and capacitor C4. A voltage of −V7is also provided at the negative power rail.

Similar to the charging operation employed by the first stage of theFIG. 5circuit the transistors Q10and Q11again charge the capacitor C5, albeit to 3*V7when transistor Q11is conducting but Q10is non-conductive and if the voltage provided at the node shared by diode D8and capacitor C4is 2*V7.

Cascading the four power sources V6, V7, C4and C5allows to achieve the output voltages V_RL across the load RL indicated in the diagram ofFIG. 6.

A load voltage V_RL of 0 Volt is generated if transistors Q11and Q13are conducting and transistors Q59and Q60are non-conductive (switching state1inFIG. 6). The node shared by capacitor C4and diode D9is then at a potential of −V7, as is the node shared by transistors Q10, Q11and capacitor C5. The voltage at the upper terminal of RL is therefore −V7, giving rise to a zero voltage potential difference. In this switching state capacitor C4is charged to a voltage difference of 2*V7.

A load voltage V_RL of V7is generated if transistor Q12is conducting and transistors Q59and Q60are non-conductive (switching state2inFIG. 6). In this switching state the node shared by transistors Q12and Q13, capacitor C4and diode D9is at ground potential, while the node shared by transistors Q10, Q11and capacitor C5is at potential −V7. Diodes D9and D10are conductive, passing the ground potential to the upper terminal of RL. The potential difference across the load RL is therefore V7. In this switching state diodes D8is non-conductive, as the voltage stored in capacitor C4boosts the voltage on the node shared by diodes D7and D8, capacitor C4and transistor Q60to 2*V7.

A load voltage V_RL of 2*V7is generated if transistors Q11, Q13and Q60are conducting and transistor Q59is non-conductive (switching state3inFIG. 6). Potential V7is applied to the upper terminal of the load RL via transistor Q60. As the anode of diode D9is at a potential of −V7diode D9is non-conductive. The potential across the load RL is therefore 2*V7.

A load voltage V_RL of 3*V7can be achieved by two different switching states, shown as states4and5inFIG. 6. In the first switching state (switching state4inFIG. 6) transistors Q11, Q12and Q60are conducting while transistor Q59is non-conductive. The ground potential shared by the voltage sources is applied, through transistor Q12, to the node shared by the transistors Q12and Q13and by capacitor C4and diode D9. The potential on the node shared by diodes D7and D8, capacitor C4and transistor Q60is boosted to 2*V7by the charges stored in capacitor C4, therefore rendering diode D8non-conductive. This potential is passed through transistor Q60and diode D10to the upper terminal of the load RL, rendering diode D9non-conductive. The potential difference V_RL across the load RL is therefore 3*V7. In this switching state the capacitor C4is discharged. The capacitor C5connected between the boosted voltage 2*V7(through diode D7) and −V7(through transistor Q11) and is therefore charged to 3*V7by capacitor C4.

In the second switching state (switching state5shown inFIG. 6) transistors Q10, Q13and Q59are conducting, while transistor Q60is non-conductive. In this switching state capacitor C4is charged between voltages V7and −V7(through transistor Q13). The node shared by transistors Q10and Q60and diodes D9and D10is at a potential of −V7. Capacitor C5holds a voltage of 3*V7, thus boosting the node shared between diode D7, capacitor C5and transistor Q59to a potential of 2*V7, rendering diode D7non-conductive. This potential is also applied to the upper output terminal connecting to RL, rendering diode D10non-conductive. In this switching state capacitor C4is charged while capacitor C5is discharged.

A load voltage V_RL of 4*V7is achieved if transistors Q10, Q12and Q59are conducting and when transistor Q60is non-conductive (switching state6inFIG. 6). Ground potential is applied to the node shared by capacitor C5and transistors Q10and Q11through transistors Q10and Q12and diode D9. Capacitor C5stores a voltage of 3*V7, thus boosting the potential at the node shared by diode D7, capacitor C5and transistor Q59to 3*V7. This potential is applied to the upper terminal of load RL through transistor Q59. It will be appreciated that the potential at the node shared by transistors Q12and Q13, capacitor C4and diode D9is also at ground. This means that the charges stored in capacitor C4(amounting to 2*V7in a steady-state fully charged mode) boost the potential at the node shared by diodes D7and D8, capacitor C4and transistor Q10to 2*V7, thus rendering diode D8non-conductive. The potential 3*V7at the node shared between diode D7, capacitor C5and transistor Q59renders diode D7non-conductive in light of the 2*V7potential at the anode of diode D7. Capacitor C4thus can hold the stored charge, while capacitor C5discharges in this switching state.

Load voltages of V_RL of 5*V7and6*V7are generated in switching states7and8shown inFIG. 6respectively. In both switching states transistors Q10, Q59and Q60are conducting. The two switching states differ from each other in that, in switching state7transistor Q13is conducting while transistor Q12is non-conductive, while in switching state8transistor Q12is conducting while transistor Q13is non-conductive.

In both switching states the potential applied to the lower terminal of capacitor C5/to the node shared by diodes D9and D10and transistors Q10and Q60is boosted by the voltage stored in capacitor C5, namely by 3*V7. The two switching states differ in the potential that is applied (via transistor Q60) to the node shared by diodes D9and D10and transistors Q10and Q60. Both of the different potentials applied to this node in the two switching states result from a boosting of the potential at the node shared by transistors Q12and Q13, capacitor C4and diode D9. The potential at this node is boosted by the voltage stored in C4, 2*V7. In switching state7transistor Q13is conducting, so that a voltage of −V7is boosted to a voltage of V7by capacitor C4. This voltage is in turn boosted to 4*V7by capacitor C5, giving rise to an output potential difference of 5*V7. In switching state8transistor Q12is conducting, so that the ground potential is boosted to a voltage of 2*V7by capacitor C4. This voltage is in turn boosted to 5*V7by capacitor C5, giving rise to an output potential difference of 6*V7.

The above description of the circuit shown inFIG. 5charges capacitor C5to a voltage of 3*V7. It will, however, also be appreciated that it would be possible to charge capacitor C5to a voltage of 2*V7. In this some of the above discussed output voltages can be generated in a different manner that would be readily apparent to the person skilled in the art in view of the above discussion.

Turning now to the circuit shown inFIG. 7, this circuit is similar to the first stage of the circuit shown inFIG. 5(comprising transistors Q12and Q13, diode D8and capacitor C4) in combination with transistor Q59but comprises an additional transistor Q17in series with the load RL. It will be appreciated that the circuit shown inFIG. 7is also similar to a version of the circuit shown inFIG. 2but modified so that power is returned to the negative supply rail and further comprising the transistor Q17.

It will be appreciated that in the example circuits shown inFIGS. 2 and 5only the discrete voltage levels shown inFIGS. 3 and 6respectively can be applied at the output.FIG. 7improves upon this by varying the gate voltage applied to transistor Q17so that the voltage drop across transistor Q17causes the voltage output across the load RL to vary smoothly. It will be appreciated that the input signal applied to the gate of transistor Q17is not a binary signal (as is the case for IN_1to IN_5discussed above) but a linear analogue signal that has a signal levels arranged to cause a voltage drop across the channel of transistor Q17that reduces a voltage applied to the node transistor Q17shares with transistor Q14and diode D12to a desired output voltage V_RL.

A further difference between the circuit ofFIG. 7and both of the circuits ofFIGS. 2 and 5is that it is the negative terminal of the voltage source V9(rather than the terminal shared by the two voltage sources) that is connected to ground. This modification is independent from the use of transistor Q17and could equally be made in the circuits shown inFIGS. 2 and 5.

Turning now to the circuit ofFIG. 8, this circuit expands the circuit shown inFIG. 7by adding a mirrored version of theFIG. 7circuit, wherein the polarities of the transistors are also inverted. As can be seen, the regulating transistor Q17used inFIG. 7has not been included in either of the two halves of the circuit shown inFIG. 8. Omission of this transistor from either half of theFIG. 8circuit is, however, not essential if a linear signal is to be produced.

The operation of each half of theFIG. 8circuit is the same as the operation of the circuit shown inFIG. 2or of the equivalent parts of the circuit shown inFIG. 7. The circuit shown inFIG. 8enables applying positive and negative voltages across the load RL. Table 1 details a range of voltages that can be applied to the load RL, alongside the required switching states of the relevant transistors.

TABLE 1Switching states of relevant transistors for applying the output loadvoltages discussed in the left-hand columnVoltage at RLSwitching Mechanism3*V16Connect the lower terminal of C9 to the node between V13and V14 through transistor Q26, thereby boosting thepotential at the upper terminal of C9 to 3*V16 (as C9 storesa voltage of 2*V16)Connect this potential to RL through transistor Q252*V16Connect the potential 2*V16 provided by V13 and V14 toRL through transistor Q25V16Connect the potential V16 at the node shared by V13 andV14 to RL through Q26 and D17. Transistors Q25 and Q30are non-conductive.0Connect ground potential from the node shared by V14 andV15 to RL through Q27 and D17. Q25 and Q30 are non-conductive−V16Connect the potential −V16 at the node shared by V15 andV16 to RL through Q29 and D18. Transistors Q25 and Q30is non-conductive.−2*V16Connect the potential −2*V16 provided by V15 and V16 toRL through Q30−3*V16Connect the upper terminal of C10 to potential −V16through transistor Q29, thereby boosting the potential atthe lower terminal of C10 to −3*V16 (as C10 stores avoltage of 2*V16)Connect this potential to RL through transistor Q30

The circuit ofFIG. 8relies on four binary signal inputs, two for each half circuit. It will be appreciated that not all combinations of signal inputs can be used in this circuit. The switching of the transistors does, for example, have to be performed such that only a single potential is applied to the load RL in one of the above summarised manners. Transistors required for blocking other potentials from being applied to the load RL are switched accordingly. Other transistors may be switched to enable the charging of one or both of the capacitors when the capacitors are not used for voltage boosting.

Combining P-channel and N-channel structures as shown inFIG. 8results in a bipolar output so that both positive and negative transitions can be achieved around the ground reference. It is possible to integrate respective P-channel and N-channel series pass elements intoFIG. 8to achieve a linear output signal as detailed inFIG. 7.

It will be appreciated that the advantage of being able to provide positive and negative voltage levels is achieved in the circuit shown inFIG. 8at the cost of having to provide four voltage sources. A further embodiment capable of applying positive as well as negative voltages to the load RL without, however, having to use four voltage sources is shown inFIG. 9. The circuit ofFIG. 9uses a transformer with two primary windings. The centre/common terminal of the primary side of this transformer is permanently connected to the potential +V3. Positive and negative voltages are induced in the secondary side of the transformer by applying either a negative potential at the upper terminal (the terminal sharing a node with diode D3and transistor Q6) of the primary side of the transformer or a positive potential at the lower terminal (the terminal sharing a node with diode D5and transistor Q9) of the primary side of the transformer. Only one half of the primary side of the transformer is in use at any one time.

In the illustrated embodiment the transformer is configured such that the two halves of the primary winding have an equal number of turns. In an embodiment each half of the primary side provides 1:1 transformation of an applied voltage to the secondary side. It will be appreciated that 1:1 transformation is, however, not essential and other ratios may be chosen, depending on the desired output voltages. If the transformer is configured so that 1:1 transformation between the primary and secondary sides is achieved, then the voltage V_RL applied to the load is the same voltage as the voltage difference applied across the half of the primary side of the transformer currently in use. The input signals applied for generating the various load voltages V_RL are shown inFIG. 10. Table 2 lists the switching states required to achieve various load voltages V_RL.

TABLE 2Switching states of relevant transistors for applying the output loadvoltages discussed in the left-hand columnVoltage at RLSwitching Mechanism3*V3Connect the node shared by capacitor C3, diode D5,transistors Q7 and Q8 to ground via transistor Q8, therebyboosting the potential at the node shared by capacitor C3,diode D6 and transistor Q9 to −2*V3 (as capacitor C3stores −2*V3)Connect this potential to the lower terminal of thetransformer through Q92*V3Connect the lower terminal of the transformer to −V3through transistor Q9 and diode D6V3Connect the lower terminal of the transformer to groundthrough transistor Q8 and D50Connect the upper and the lower terminal of thetransformer to +V3 through transistor Q4 and diodeD3, and Q7 and D5 respectively−V3Connect ground potential to the upper terminal of thetransformer through transistor Q5 and diode D3−2*V3Connect potential −V3 to the upper terminal of thetransformer through transistor Q6 and diode D4−3*V3Connect the node shared by capacitor C2, diode D3 andtransistors Q4 and Q5 to ground through transistor Q5,thereby boosting the potential at the node shared bycapacitor C2, diode D4 and transistor Q6 to −2*V3 (ascapacitor C2 stores −2*V3)Connect this potential to the upper terminal of thetransformer through transistor Q6Diodes D3 and D4 are non-conductive in this switchingstate

FIG. 11shows the circuit ofFIG. 9, albeit including a series pass element Q22to provide a smooth output signal in the same manner as the series pass element described above with reference toFIG. 7. It will be appreciated that transistor Q22shown inFIG. 11operates in class A mode. This leads to inefficiencies that may be avoided if a second transistor connected to draw current from a power supply with a lower supply voltage than the supply voltage of the two power supplies V11and V12was included in the circuit so as to form a class G amplifier. An example of such a circuit is shown inFIG. 12.

The potential across either of the two primary windings of the transformer shown inFIGS. 9, 11 and 12is the difference between the voltage applied to the central terminal (this potential is V3in the circuit shown inFIG. 9and (due to the modifying effects of the linear series pass element Q22used inFIG. 11) between ground and V3in the circuit shown inFIG. 11) and the potential applied to the upper or lower terminals of the primary windings (as discussed above, these potentials are the ground potential, −V3, −2*V3and −3*V3. The potential applied across the primary windings of the transformer of the circuit shown inFIG. 9can therefore be expressed as Vprimary=V3+n*V3, wherein n is an integer that can take the values 0, 1, 2 or 3.

The series pass element can induce a voltage drop that reduces the potential V3applied to the central terminal of the primary winding to any potential value between the ground potential and V3. The potential applied across the primary windings of the transformer of the circuit shown inFIG. 11can therefore be expressed as Vprimary=cV3*V3+n*V3, wherein n is an integer that can take the values 0, 1, 2 or 3 and wherein cV3is a scaling factor smaller than 1 that reflects the attenuation of the potential applied to the common terminal of the primary winding of the transformer by Q22.

It will be appreciated that the efficiency of the circuit ofFIG. 11is reduced as the potential drop across Q22increases. The circuit shown inFIG. 12alleviates this problem by providing a further power supply, V15. The voltage supplied by V15is lower than the supply voltage V13. This means that, if a voltage Vprimarywas desired that would require cV3*V3to be smaller than V15the circuit shown inFIG. 12allows disconnecting the node shared by transistors Q66, Q68and the transformer from V3by applying an appropriate input signal to the gate of transistor Q66. The voltage source V15can then be connected to the node shared by transistors Q66, Q68and the transformer by applying an appropriate input signal to transistor Q68. In this case that output signal Vprimarycan be expressed as Vprimary=cV15*V15+n*V13, wherein n is an integer that can take the values 0, 1, 2 or 3 and wherein cV15is a scaling factor smaller than 1 that reflects the attenuation of the potential applied to the common terminal of the primary winding of the transformer by Q68.

This arrangement compares favourable in terms of efficiency with the circuit shown inFIG. 11as, in theFIG. 12circuit output voltages requiring an attenuation of V13(V3inFIG. 11) to below V15can be generated by replacing a heavily attenuated voltage supply from V13with a less heavily attenuated voltage supply from voltage source V15.

It will be appreciated that the class G arrangement is not only useful in the transformer embodiments ofFIGS. 9, 11 and 12. More generally the class G network shown inFIG. 12is useful in any arrangement where a supply potential other than the ground potential is applied to one load terminal and a switched potential is applied to the other load terminal. This is, for example, the case in the circuit shownFIG. 2.

In a further embodiment shown inFIG. 13a series pass element QAis provided in series with the unswitched supply potential VAand the load terminal (as opposed to the series pass element being provided in series between the switched output potential and the load as is the case in the circuit shown inFIG. 7). It will be appreciated that, in this embodiment the voltage applied across the load V_RL is c*VA−Vswitched, wherein c is a constant representing the attenuation of the supply voltage VA, wherein VA≠0 V and wherein Vswitchedis the voltage supplied by the switching network indicated in dashed lines inFIG. 13. It will be appreciated that the switching network used inFIG. 13can be any of the networks discussed above, wherein a direct connection between a power supply and the load is provided by the connections shown inFIG. 13.

As is the case for the circuit ofFIG. 11, the circuit shown inFIG. 13suffers from reduced efficiency as the value of c decreases. This problem is alleviated by the provision of the voltage source VBand the series pass element QBand the same manner as discussed above with regard toFIG. 12. and similar efficiency gains as those discussed above with reference toFIG. 12can be achieved.

It will be appreciated that the voltages supplied by the two power sources connected to the switching network (V13and V14ofFIG. 12, for example) determines the voltages that can be stored in the capacitors in the switching networks. The stored voltage in turn determines the amount by which one of the supply voltages of the commonly connected power sources can be boosted. The voltages supplied by the two commonly connected power sources thus determine the difference between the potentials applied to one terminal of the load. In all of the above described embodiments with the exception of the embodiments shown inFIGS. 12 and 13one of the supply voltages provided by the commonly connected power supplies is also (directly or via a series pass element) applied to another load terminal, withFIGS. 12 and 13using a different power supply (V15and VBrespectively) at times. This supply voltage thus provides a reference voltage to the load against which the voltage drop across the load is formed.

As the above discussion relating toFIGS. 12 and 13shows, situations exist where it is advantageous to replace the supply voltage provided to the load terminal from the commonly connected power supplies with a lower supply voltage (which may in turn be subject to attenuation by a series pass element), for example from voltage sources V15and QBinFIGS. 12 and 13respectively. Thus far the description of embodiments has focused on supplementary power supplies V15/VBthat provide a supplementary supply voltage that is lower than the supply voltage V13/VAsupplied to the switching network. As will be appreciated from the above discussion, the supply voltage provided to the switching network determines the step width between the voltages applied to one of the load terminals. It is, however, not necessary for the voltage VBto be lower than the voltage VAand situations can be imagined where VB>VAand where VBis connected to a load terminal and attenuated by QBuntil the attenuated supplied voltage is as low as VA. At this point QBcan be switched to disconnect VBfrom the load terminal and QAcan be enabled to connect VAto the load terminal

The multilevel power supply architectures of the embodiments have been shown to provide increased efficiency. A standard class B amplifier with a sinusoidal input, for example, has an efficiency of 78.5%, whereas the efficiency of the circuit shown inFIG. 11is 89%. It will be appreciated that the improvement relative to the class B amplifier is the greatest if signals with his PAPR are to be operated upon.

In embodiments a number of different voltages can be produced across a resistive load in a binary controlled fashion. The binary weighted switching reduces the number of power supplies required when compared to known multilevel power supplies without dramatically increasing the number of components.

It will be appreciated that, although MOSFETs are used in the above described embodiments, the use of such transistors is not essential and other transistor types or species (such as bipolar junction transistors or insulated gate bipolar transistors) or other form of switching devices can be used in practising the embodiments as long as the switching behaviour of the transistors described above with respect to the preferred embodiments is replicated.

If low power MOSFET switches are used fast switching speeds are achievable. This makes the architectures of the embodiments suitable for replacing class B or class G amplifiers in wideband split frequency envelope modulated amplifier architectures.