A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

BACKGROUND

Description of the Related Art

In general, a three-dimensional integrated circuit product includes integrated circuit die that are stacked and interconnected vertically to behave as a single integrated circuit. Three-dimensional integrated circuits achieve performance improvements at reduced power and smaller footprints than conventional two-dimensional integrated circuit products. In operation, heat accumulates within the stack of the integrated circuit die. That heat must be dissipated to reduce or eliminate thermal failure of the three-dimensional integrated circuit product. Traditional heat extraction techniques that extract heat from the top of a stack are insufficient to dissipate enough heat from increasingly dense stacks of integrated circuit die to prevent failure of three-dimensional integrated circuit products. Accordingly, improved techniques for thermal management in three-dimensional integrated circuit products are desired.

SUMMARY OF EMBODIMENTS OF THE INVENTION

In at least one embodiment, a three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts. The three-dimensional integrated circuit may include at least one additional die having the second geometry. The at least one additional die may include additional electrical contacts disposed on a first side of the at least one additional die. Each additional die of the at least one additional die is stacked on the first die and disposed laterally across the first die from others of the at least one additional die. Each additional die of the at least one additional die may have a corresponding stacked portion stacked within the periphery of the first die and a corresponding overhang portion that extends beyond the periphery of the first side of the first die, the additional electrical contacts being aligned with and coupled to the first electrical contacts.

In at least one embodiment, a method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit. The method may include removing the second carrier wafer before attaching the first side of the second die to the second side of the transitional three-dimensional integrated circuit. The method may include preparing the first side of the transitional three-dimensional integrated circuit to generate a prepared first side of the first die before attaching the third carrier wafer. The third carrier wafer may be attached to the prepared first side of the first die. The method may include removing the third carrier wafer from the transitional three-dimensional integrated circuit after attaching the first side of the second die to the second side of the transitional three-dimensional integrated circuit.

In at least one embodiment, a three-dimensional integrated circuit includes a processor die. The processor die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The processor die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a plurality of high bandwidth memory die. Each high bandwidth memory die of the plurality of high bandwidth memory die includes second electrical contacts disposed on a first side of the high bandwidth memory die. The second electrical contacts are coupled to the first electrical contacts. Each high bandwidth memory die of the plurality of high bandwidth memory die is stacked with the first die and disposed laterally across the first die from other high bandwidth memory die of the plurality of high bandwidth memory die, at the periphery of the processor die, and extends beyond the periphery of the first die.

In at least one embodiment, a three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry. If the additional die structure has the first geometry, the additional die structure includes a third region that operates with a third power density and a fourth region that operates with a fourth power density, the third power density is less than the fourth power density, the second die structure is interleaved between the first die structure and the additional die structure, the stacked portion of the second die structure is aligned with the third region, and an overhang portion of the additional die structure extends beyond a periphery of the second die structure. If the additional die structure has the second geometry, the first die structure is interleaved between the second die structure and the additional die structure, a stacked portion of the additional die structure is aligned with the first region, and the overhang portion of the first die structure extends beyond a periphery of the additional die structure. The overhang portion of the first die structure extends beyond the periphery of the second die structure.

DETAILED DESCRIPTION

Referring toFIG. 1, processor die100(e.g., graphics processing unit, central processing unit, digital signal processing unit, or other processing unit) includes regions that operate with different power densities. For example, region104and region106of processor die100operate with a first power density and region108, region110, region112, region114, region116and other similarly shaded regions of processor die100operate with second power densities, which are lower than the first power density. Processor die100has a first geometry that has substantially larger area than the geometry of each of a plurality of memory modules that will be coupled to processor die100. Referring toFIGS. 1 and 2, memory module200is a stacked memory module (e.g., high-bandwidth memory, which includes multiple stacked memory die coupled to each other and at least partially encapsulated by a mold compound) having an area of d1×d2, which in some embodiments is less than 25% of the area of processor die100. Memory module200includes electrical contacts202(e.g., a region including conductive pillars, conductive bumps, or other interconnects of copper, gold, aluminum, other conductive material, or combination thereof) in an area d3×d4. A perimeter zone without electrical contacts located outside region202provides a high thermal resistance path to processor die100when memory module200is stacked on processor die100.

Referring toFIG. 3, in an exemplary three-dimensional integrated circuit, memory modules200are stacked on processor die100in a conventional configuration, which causes the power dense regions toward the center of processor die100to be disposed directly under memory modules200, resulting in high thermal resistance paths for dissipating the heat generated by processor die100. That high thermal resistance of memory modules200is exacerbated by embodiments of memory modules200having limited footprints (e.g., limited electrical contact footprints of approximately 21% of area of memory modules200), reducing the metal-volume fraction, and thus, further increasing thermal resistance of memory module200. For example, one or more (e.g., four) memory modules200are stacked on processor die100laterally with respect to each other memory module200. Each memory module200is coupled to processor die100using electrical contacts202. Underfill material (e.g., epoxy, which is a poor thermal conductor) fills in gaps between memory modules200and processor die100. Mold material encapsulates portions of the stack. The center-alignment of memory modules200on processor die100may result in a high percentage (e.g., approximately 86%) of dense power blocks of processor die100in contact with a high thermal resistance path.

Referring toFIG. 4, an alternate arrangement of a three-dimensional integrated circuit includes memory modules200aligned with the perimeter of processor die100. Accordingly, lanes402and lanes404between memory modules200have increased width, as compared to the center-aligned configuration ofFIG. 3. Referring toFIG. 4, underfill material fills in gaps between adjacent memory modules200and between memory modules200and processor die100. Mold material encapsulates portions of the stack. The perimeter-aligned arrangement slightly reduces the percentage (e.g., by approximately 4-5%, to approximately 82%) of dense power blocks of processor die100in contact with a high thermal resistance path.

Referring toFIG. 5, at least one embodiment, a three-dimensional integrated circuit obtains a substantial reduction in the percentage (e.g., a reduction of 65%) of high power density regions of processor die100that are in contact with a high thermal resistance path. That reduction is obtained at the expense of increased lateral area of the three-dimensional integrated circuit, additional manufacturing steps, and thus, an increased cost of the three-dimensional integrated circuit. Electrical contacts202of memory modules200and corresponding contacts of processor die100are aligned with the perimeter of processor die100. As a result, portions of memory modules200overhang processor die100, i.e., portions of memory module200extend beyond the periphery of processor die100, and portions of memory module200are stacked within the periphery of processor die100. Thus, the area of three-dimensional integrated circuit500is greater than (e.g., approximately 50% greater than) the area of three-dimensional integrated circuit300and three-dimensional integrated circuit400ofFIG. 3andFIG. 4, respectively. Like three-dimensional integrated circuit300and three-dimensional integrated circuit400, three-dimensional integrated circuit500ofFIG. 5includes underfill material that fills in gaps between adjacent memory modules200and between memory modules200and processor die100. Mold material encapsulates portions of the stack. The sizes of the overhang portions are limited by the size and location of electrical contacts202, which may be coupled to through-silicon vias of processor die100.

Referring toFIG. 6, as discussed above, the high power density regions of processor die100reside in particular portions of processor die100(e.g., toward the center of processor die100). Memory module200has a higher thermal resistance than a single silicon filler die or other filler material. Accordingly, offsetting memory module200with respect to processor die100in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of processor die100having a higher power density. In at least one embodiment of a three-dimensional integrated circuit having perimeter-aligned contacts and an offset-perimeter-aligned stacked die configuration, lanes between memory modules200are filled with a homogeneous inorganic material (e.g., silicon crystal). For example, filler silicon portion602and filler silicon portion604are attached in the lanes between memory modules200. Filler silicon portion602and filler silicon portion604may extend between multiple memory modules200, extend across a wafer including multiple processor die100, and may be shared with other processor die on a wafer adjacent to processor die100on the wafer.

Referring toFIGS. 6 and 7, in an exemplary embodiment of a three-dimensional integrated circuit having perimeter-aligned contacts and offset-perimeter-aligned stacked die configuration, memory modules200are stacked on a backside of processor die100and disposed laterally with respect to each other, to form overhang portions720. Overhang portions720of the memory modules extend beyond the periphery of processor die100and portions of the memory modules are stacked within the periphery of processor die100. Electrical contacts202are electrically and mechanically coupled to through-silicon vias708, which are coupled to frontside conductors702(e.g., conductive pads, conductive bumps, or conductive pillars) of processor die100. Mold material704encapsulates portions of the stacked die. Material710is an encapsulant (e.g., silicon oxide or organic mold) that fills in gaps that extend from the periphery of processor die100underneath the overhanging portions of the memory modules. In an embodiment including four memory modules, each memory module200is stacked on processor die100at a corresponding corner of processor die100. In embodiment of a three-dimensional integrated circuit including other numbers of memory modules, and each memory module200is stacked on processor die100and disposed laterally from any other memory module200with respect to the surface of processor die100.

Referring toFIGS. 7 and 8, in at least one embodiment, a three-dimensional integrated circuit with perimeter-aligned contacts and offset-perimeter-aligned stacked die configuration is formed using manufacturing process800. Processor die100may be manufactured using conventional semiconductor wafer processing, diced, and reconstituted on another wafer to widen scribe lanes between processor die100to accommodate the larger area of three-dimensional integrated circuit700. Reconstitution may be preceded by testing of processor die100and only qualified die are reconstituted on the other wafer for further processing. In other embodiments, processor die100are manufactured using conventional semiconductor wafer manufacturing processes on a wafer with scribe lanes wide enough to accommodate the larger area of three-dimensional integrated circuit700, thus eliminating the need to dice and reconstitute on another wafer.

Manufacturing process800includes preparing processor die100to have through-silicon vias in a region where a redistribution layer will be present between processor die100and a memory module or in a region that corresponds to electrical contacts of a memory module (802). Through-silicon vias708are vertical interconnect structures that pass completely thorough processor die100. For example, through-silicon vias708are formed using wafer backside lithography, deep silicon etching, silicon dioxide etching (e.g., reactive ion etch (RIE)) with a photoresist mask, side wall insulation deposition (e.g., low-temperature plasma-enhanced chemical vapor deposition (PECVD), silicon dioxide deposition, and subsequent silicon dioxide RIE), and conductive material processing. Manufacturing process800includes preparing a first carrier wafer (e.g., preparing a native oxide layer surface, pre-bonding at room temperature, and annealing at elevated temperature) (803). In general, carrier wafers (e.g., glass wafer or silica wafer) provide structural support and permit safe handling of delicate semiconductor wafers during manufacturing. Manufacturing process800attaches the frontside of processor die100to the first carrier wafer using direct bonding or using a temporary bonding adhesive (e.g., a material including low temperature wax, hydrocarbon oligomers or polymers, acrylate, epoxy, silicone, or high temperature thermoplastic). The attachment of the first carrier wafer may be followed by planarization (e.g., using a silicon oxide material or mold compound) and wafer thinning (e.g., by back grinding and polishing techniques) to reveal through-silicon vias on the backside of processor die100(804).

Next, manufacturing process800prepares backside pads, or other electrical connectors on processor die100by forming one or more conductive layers (e.g., redistribution layers) and photoresist masking techniques. For example, a photoresist is applied, a reticle including a backside pad pattern is used to selectively expose the photoresist material, and unwanted material is removed (e.g., etched away). Instead of a subtractive patterning process, an additive patterning process may be used to form conductive structures only in regions that need the material (806). A second carrier wafer is attached to the backside of processor die100using direct bonding or a temporary bonding adhesive (808) and the first carrier wafer is removed using a mechanism associated with the corresponding bonding technique, e.g., mechanical separation, ultra-violet curing and release, heat curing and release, thermal sliding, chemical activation, laser activation, or other debonding technique associated with the material of the temporary bonding adhesive (810). Following the removal of the first carrier wafer, electrical contacts are formed on the frontside of processor die100by applying a conductive layer and using photoresist masking techniques (812).

After the formation of frontside electrical contacts, a third carrier wafer is attached to the frontside of processor100using direct bonding or a temporary bonding adhesive (814) and the second carrier wafer is removed using a mechanism associated with the corresponding bonding technique (816). Electrical contacts202of memory module200are aligned and attached to electrical contacts on the backside of processor die100(818). At this time, filler silicon portion602and filler silicon portion604are attached to the backside of processor die100and wafer-level molding and molded wafer back grind are performed. The third carrier wafer is removed using a debonding mechanism associated with the corresponding bonding technique (820). A wafer including the resulting three-dimensional integrated circuit is then diced to form three-dimensional integrated circuit700(822).

Note that manufacturing process800is exemplary only and other sequences and types of manufacturing steps may be used to generate a three-dimensional integrated circuit having perimeter-aligned contacts and offset-perimeter-aligned stacked die configuration. For example, rather than start with backside processing and carrier wafer attach to the frontside of processor die100of manufacturing process800, processing may begin with frontside processing of processor die100before preparing the through-silicon vias (802). The resulting manufacturing process is a simplified version of manufacturing process800that uses fewer carriers and fewer steps (e.g., steps808-816and820are excluded). For example, after preparing processor die backside pads (806), electrical contacts202of memory module200are aligned and attached to electrical contacts on the backside of processor die100(818). At this time, filler silicon portion602and filler silicon portion604are attached to the backside of processor die100and wafer-level molding and molded wafer back grind are performed. The first carrier wafer is removed using a debonding mechanism associated with the corresponding bonding technique and a wafer including the resulting three-dimensional integrated circuit is then diced to form three-dimensional integrated circuit700(822). However, this simplification of manufacturing process800trades off reduced complexity and cost of manufacture with increased challenges to reconstitution of singulated die and control of the through-silicon via reveal process.

In other embodiments, a three-dimensional integrated circuit includes vertical stacks of die having different geometries (e.g., different rectangular proportions or different square proportions). Those die of different geometries may be interleaved in a stack to create or increase cavities in the three-dimensional integrated circuit, which may improve conditions for thermal management. For example, referring toFIG. 9, square die structure1004may be a smaller-scaled version of square die structure1002(e.g., the smaller die has fewer memory circuits or core circuits than the larger die) or square die structure1002and square die structure1004may be different types of die (e.g., a memory die and a controller die). The entirety of square die structure1004may be stacked on square die structure1002within the periphery of square die structure1002, and no portions of square die structure1004overhang square die structure1002. Interleaving those different die creates cavities in the die stack. In other embodiments, square die structure1004may be offset-perimeter aligned to square die structure1002to create cavities that are asymmetrically positioned in the stack of die. Although square die structure1002may be a single die and square die structure1004may be a single die, in other embodiments of a three-dimensional integrated circuit, square die structure1002includes a plurality of die having the same, first geometry aligned in a stack. That stacked die structure increases the size of a cavity formed by stacking square die structure1002and square die structure1004. Similarly, square die structure1004may include a plurality of die having the same, second geometry aligned in a stack, thus increasing the size of a cavity formed by stacking square die structure1002and square die structure1004. Stacking of individual die to form square die structure1002may occur prior to stacking with square die structure1004. In another embodiment, square die structure1002may be formed by stacking a first square die with the first geometry in a stack with square die structure1004and then stacking at least one additional square die with the first geometry aligned with the first square die.

Referring toFIG. 10, in some embodiments of a three-dimensional integrate circuit, each individual integrated circuit die has a rectangular geometry that may be used to create or increase the size of cavities in the three-dimensional integrated circuit. Rather than align the length and width of rectangular die structure1102and rectangular die structure1104, rectangular die structure1102and rectangular die structure1104are positioned in a stack with their length dimensions L1and L2, respectively, orthogonal to each other. Offsetting the alignment of the length dimensions of those die at an angle A greater than zero (e.g., 0<∠A≤90 degrees) creates cavities that may improve conditions for thermal management at the expense of increased size and manufacturing process steps of the three-dimensional integrated circuit. Although rectangular die structure1102may be a single die and rectangular die structure1104may be a single die, in other embodiments of a three-dimensional integrated circuit, rectangular die structure1102includes a plurality of die having the same, first geometry aligned in a stack. That stacked structure increases the size of a cavity formed by stacking rectangular die structure1102and rectangular die structure1104. Similarly, rectangular die structure1104may include a plurality of die having the same, second geometry aligned in a stack, thus increasing the size of a cavity formed by stacking rectangular die structure1102and rectangular die structure1104. Stacking of individual die to form rectangular die structure1102may occur prior to stacking with rectangular die structure1104. In another embodiment, rectangular die structure1102may be formed by stacking a first rectangular die with the first geometry in a stack with rectangular die structure1104and then stacking at least one additional rectangular die with the first geometry aligned with the first rectangular die.

Referring toFIG. 11, in some embodiments of a three-dimensional integrated circuit in which an unsupported die portion does not introduce mechanical issues, rather than use filler material, cavities in the three-dimensional structure may be used to dissipate heat, and die are placed in mechanical contact with regions of lower operational power density (e.g., unshaded regions of die1204, die1208, die1212, and die1216). Three-dimensional integrated circuit1200includes cavities between adjacent die of the same geometry and alignment, thereby improving conditions for thermal management. Die1204, die1208, die1212, and die1216may be larger square die interleaved with die1206, die1210, and die1214, which are smaller square die as illustrated inFIG. 9. In other embodiments of three-dimensional integrated circuit1200, die1204, die1208, die1212, and die1216are rectangular die having lengths oriented orthogonally to lengths of die1206, die1210, and die1214, which are other rectangular die, as illustrated inFIG. 10. Note that although adjacent die of the same geometry and alignment (e.g., die1204, die1208, die1212, and die1216, which have a first geometry and alignment, or die1206, die1210, and die1214, which have a second geometry and alignment) may be identical to each other, in other embodiments of a three-dimensional integrated circuit, adjacent die of the same geometry and alignment may vary from each other in other aspects.

Referring toFIG. 11, by placing power-hungry logic (shaded regions of die1204, die1208, die1212, and die1216), towards periphery of the die, near cavities of three-dimensional integrated circuit1200, improves heat radiation towards the cavities, where the heat is dissipated. Die1204, die1206, die1208, die1210, die1212, die1214, and die1216may be homogenous die (e.g., memory die) or heterogeneous die (e.g., die having circuits of different functions) coupled to a controller die1202using through-silicon vias1222. In other embodiments of three-dimensional integrated circuit1200, through-silicon vias1222are perimeter-aligned, and die are offset-perimeter-aligned, creating a three-dimensional integrated circuit having asymmetrically disposed cavities.

In at least one embodiment of a three-dimensional integrated circuit, changing the surface texture of die overhang portions that extend into the cavities increases contact area with air or other heat dissipating material in the cavity. For example, deposition of structures or outgrowth of structures1224, which may be thermally conductive carbon nano-tubes (e.g., carbon nanotubes having thermal conductivity of at least approximately 6000 Watts (W) per milli-Kelvin (m K)) having micron feature size, may be used. Referring toFIG. 12, in at least one embodiment of a packaged three-dimensional integrated circuit, structures1308may also be deposited on package lid1302and on a surface of three-dimensional integrated circuit1302to increase heat conductivity and to reduce the thermal resistance of the interface between three-dimensional integrated circuit1302, thermal interface material1304(e.g., silicone rubber or thermal grease mixed with aluminum particles and zinc oxide, gold, platinum, silver, nanofoils composed of layers of aluminum and nickel, or other base material and thermally conductive particles), and lid1306.

Techniques for changing the surface texture of the three-dimensional integrated circuit and/or package may be incorporated with heat extraction techniques, such as thermal interface material interfaces that are deposited on die before stacking or injected into cavities after stacking. After stacking die, thermal interface material sidewalls may be formed and bonded to sides of the package. The three-dimensional integrated circuit may have an interface with a heat spreader, which may be air-cooled or liquid-cooled. An exemplary thermal interface material has a higher thermal conductivity as compared to silicon (e.g., 149 W/mk). For example, copper has a thermal conductivity of 385 W/(mK) and graphene films have a thermal conductivity of 1219 W/(mK). Other heat dissipating techniques may be used (e.g., pumping liquid coolant in and out of the package, microfluidic-based closed loop in-package cooling, electro-hydrodynamic ionic wind solutions).

Referring toFIGS. 11 and 13, the three-dimensional integrated circuit may include support structures to reduce the likelihood of damage to overhang portions of integrated circuit die structures from mechanical issues. For example, support structures disposed at or near the corners (e.g., support structure1408, support structure1410, and support structure1412) are formed on integrated circuit die structure1204before attaching integrated circuit die structure1208to integrated circuit die structure1206. The support structures do not substantially reduce the cavity. Exemplary support structures are formed from silicon or thermal interface material (TIM).

Thus, techniques for improving conditions for thermal management of a three-dimensional integrated circuit have been disclosed. The techniques include offset alignment and placement of die a stack to increase power dissipation. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which a processor die is positioned on the bottom of a three-dimensional integrated circuit structure with four memory modules positioned laterally on the backside of a processer die, each memory module including multiple stacked memory die, one of skill in the art will appreciate that the teachings herein can be utilized with any number of integrated circuit die, heterogenous mixing of integrated circuit die, die of varying geometry, and various other stacking configurations. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.