Circuit for testing internal voltage of semiconductor memory apparatus

An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2007-0101568, filed on Oct. 9, 2007, which is incorporated herein by reference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

The embodiments described herein relate to a semiconductor memory apparatus. More particularly, the embodiments described herein relate to an internal voltage testing circuit.

2. Related Art

A Conventional semiconductor memory apparatus receives external voltage to generate desired voltage having a predetermined level. At this time, the voltage generated in the semiconductor memory apparatus is referred to as internal voltage.

During a test mode, an internal voltage generation circuit generates the internal voltage according to a level of external reference voltage. If the test mode is completed, the internal voltage generation circuit generates the internal voltage according to a level of internal reference voltage.

In a semiconductor memory apparatus having the internal voltage generation circuit as described above, it is possible to monitor a level of the internal voltage, which is generated according to the level of the external reference voltage, in a test step prior to a packaging step. After the test step, the internal voltage generation circuit detects a level of external reference voltage, which allows the internal voltage to have a target level, and fixes the detected external reference voltage level as a level of internal reference voltage.

After packaging the semiconductor memory apparatus, it is impossible to monitor levels of the internal voltage and the internal reference voltage generated in the semiconductor memory apparatus. Thus, if the semiconductor memory apparatus has been packaged, it is difficult to analyze and solve the problems caused by the failure of the internal voltage.

SUMMARY

An internal voltage test circuit of a semiconductor memory apparatus, in which it is possible to monitor the level of voltage generated in the semiconductor memory apparatus after packaging the semiconductor memory apparatus, is described herein.

In one aspect, an internal voltage test circuit of the semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during normal operation mode.

DETAILED DESCRIPTION

As illustrated inFIG. 1, an internal voltage test circuit of a semiconductor memory apparatus according to one embodiment can be configured to include a comparing unit100and an output selecting unit200.

The comparing unit100can be activated when a test signal ‘TM’ is enabled. The activated comparing unit100can generate an output signal ‘OUT’ by comparing the level of internal voltage V_int with the level of external reference voltage Ex_Vref. The internal voltage V_int can be generated in the semiconductor memory apparatus, and the external reference voltage Ex_Vref can be applied to the semiconductor memory apparatus from an exterior thereof.

As illustrated inFIG. 2, the comparing unit100can be configured to include first to fifth transistors N11, N12, N13, P11and P12. The first transistor N11can have a gate terminal, which receives the test signal ‘TM,’ and a source terminal connected with the ground VSS. The second transistor N12can have a gate terminal, which receives the internal voltage V_int, and a source terminal connected with a drain terminal of the first transistor N11. The third transistor N13can have a gate terminal, which receives the external reference voltage Ex_Vref, and a source terminal connected with the drain terminal of the first transistor N11. The fourth transistor P11can have gate and drain terminals, which are connected with a drain terminal of the second transistor N12, and a source terminal that receives external voltage VDD. The fifth transistor P12can have a gate terminal connected with a gate terminal of the fourth transistor P11, a drain terminal connected with a drain terminal of the third transistor N13, and a source terminal that receives the external voltage VDD. At this time, the output signal ‘OUT’ can be output from a node connected with the third and fifth transistors N13and P12.

When the test signal ‘TM’ is enabled, the output selecting unit200can be configured to output the output signal ‘OUT’ to a data output pad DQ. When the test signal ‘TM’ is disabled, the output selecting unit200can output a data signal ‘DATA’ to the data output pad DQ.

As illustrated inFIG. 2, the output selecting unit200can be configured to include first and second inverters IV11and IV12, and first and second pass gates PG11and PG12. The first inverter IV11can be configured to receive the test signal ‘TM.’ The first pass gate PG11can have an input terminal, which receives the output signal ‘OUT’, a first control terminal, which receives output of the first inverter IV11, a second control terminal, which receives the test signal ‘TM,’ and an output terminal connected with the data output pad DQ. The second inverter IV12can be configured to receive the test signal ‘TM.’ The second pass gate PG12can have an input terminal, which receives the data signal ‘DATA,’ a first control terminal, which receives the test signal ‘TM,’ a second control terminal, which receives output of the second inverter IV12, and an output terminal connected with the data output pad DQ.

Hereinafter, an operation of the internal voltage test circuit of the semiconductor memory apparatus according to one embodiment will be described.

During a test mode, when the test signal ‘TM’ is enabled at a high level, the first transistor N11can be turned on so that the comparing unit100is activated. Further, when the test signal ‘TM’ is enabled at a high level, the first pass gate PG11can be turned on, so that the output signal ‘OUT’ of the comparing unit100can be output to the data output pad DQ. The comparing unit100can compare the level of the external reference voltage Ex_Vref with the level of the internal voltage V_int, thereby outputting a comparison result as the output signal ‘OUT.’

The external reference voltage Ex_Vref can be applied to the semiconductor memory apparatus through an input pin and has various levels. The internal voltage V_int can be generated in the semiconductor memory apparatus. The internal voltage test circuit can compare a voltage level of the internal voltage V_int and a voltage level of the external reference voltage Ex_Vref while changing the external reference voltage Ex_Vref from high voltage to low voltage. Further, the external reference voltage Ex_Vref can, depending on the embodiment, vary from low voltage to high voltage.

If the internal voltage V_int has a level lower than that of the external reference voltage Ex_Vref, the output signal ‘OUT’ becomes a low level. However, if the internal voltage V_int has a level higher than that of the external reference voltage Ex_Vref, the output signal ‘OUT’ becomes a high level.

During a normal operation mode, other than the test mode, when the test signal ‘TM’ becomes a low level, the first transistor N11can be turned off, so that the comparing unit100is deactivated. Further, the second pass gate PG12of the output selecting unit200can be turned on by the test signal ‘TM’ at a low level, thereby outputting the data signal ‘DATA’ to the data output pad DQ. The data signal ‘DATA’ can be outputted through a general read operation of the semiconductor memory apparatus during the normal operation mode.

During the test mode, the internal voltage test circuit of one embodiment can be configured to detect the time point, at which the voltage level of the output signal ‘OUT’ is shifted from a low level to a high level, by changing the level of the external reference voltage Ex_Vref. At this time, the time point, at which the voltage level of the output signal ‘OUT’ is shifted from the low level to the high level or from the high level to the low level, corresponds to the time point at which the internal voltage V_int has a level identical to that of the external reference voltage Ex_Vref. Thus, after packaging the semiconductor memory apparatus, it is possible to exactly measure the level of the internal voltage V_int based on the time point at which the level of the output signal ‘OUT’ is shifted.

As illustrated inFIG. 3, an internal voltage test circuit of a semiconductor memory apparatus according to another embodiment can be configured to include a comparing unit100, an output selecting unit200and a voltage divider300. When internal voltage V_int to be tested has a high level of similarly to pumping voltage VPP, the internal voltage test circuit can be provided according to another embodiment. Hereinafter, the following description will be given on an assumption that the internal voltage V_int is the pumping voltage VPP.

The voltage divider300can be configured to generate divided voltage V_dv by dividing the internal voltage V_int. The voltage divider300can be a used circuit, and includes a plurality of resistors serially interconnected. The voltage divider300has one end, to which the internal voltage V_int can be applied, and the other end connected with the ground. Further, the divided voltage V_dv can be outputted from one node among the resistors.

The comparing unit100can be activated when the test signal ‘TM’ is enabled. The activated comparing unit100generates an output signal ‘OUT’ by comparing a level of the divided voltage V_dv with a level of external reference voltage Ex_Vref applied from the exterior. At this time, when the divided voltage V_dv has a level lower than that of the external reference voltage Ex_Vref, the comparing unit100outputs an output signal ‘OUT’ at a low level. However, when the divided voltage V_dv has a level higher than that of the external reference voltage Ex_Vref, the comparing unit100outputs an output signal ‘OUT’ at a high level.

When the test signal ‘TM’ is enabled, the output selecting unit200outputs the output signal ‘OUT’ to a data output pad DQ. However, when the test signal ‘TM’ is disabled, the output selecting unit200outputs a data signal ‘DATA’ to the data output pad DQ. Further, the comparing unit100and the output selecting unit200may have the same construction as those of the comparing unit100and the output selecting unit200shown inFIG. 2.

The internal voltage test circuit of the semiconductor memory apparatus according to another embodiment operates as follows:

A description will be given on the assumption that the voltage divider300outputs the divided voltage V_dv having a level corresponding to ½ of that of the internal voltage V_int.

During a test mode, when the divided voltage V_dv has a level lower than that of the external reference voltage Ex_Vref, the comparing unit100outputs the output signal ‘OUT’ at a low level. However, when the divided voltage V_dv has a level higher than that of the external reference voltage Ex_Vref, the comparing unit100outputs the output signal ‘OUT’ at a high level.

During the test mode, the output selecting unit200outputs the output signal ‘OUT’ to the data output pad DQ. Thus, the packaged semiconductor memory apparatus outputs the output signal ‘OUT’ to the exterior.

Further, during the test mode, it is possible to monitor change in the level of the output signal ‘OUT’ while varying the level of the external reference voltage Ex_Vref. During test mode, if the level of the output signal ‘OUT’ is changed from high to low or from low to high, the level of the external reference voltage Ex_Vref is checked at the time point at which the voltage level of the output signal ‘OUT’ is shifted. If the external reference voltage Ex_Vref has a level of 0.8V at the time point at which the voltage level of the output signal ‘OUT’ is shifted, it can be estimated that the internal voltage V_int to be tested has a level of 1.6V.

As illustrated inFIG. 4, the semiconductor memory apparatus using the internal voltage test circuit according to one embodiment can be configured to include the internal voltage test circuit400and a detection unit500.

The internal voltage test circuit400can be activated when the test signal ‘TM’ is enabled. The activated internal voltage test circuit400generates the output signal ‘OUT’ by comparing the level of the internal voltage V_int with the level of external reference voltage Ex_Vref. For example, when the internal voltage V_int has a level lower than that of the external reference voltage Ex_Vref, the internal voltage test circuit400outputs the output signal ‘OUT’ at a low level. However, when the internal voltage V_int has a level higher than that of the external reference voltage Ex_Vref, the internal voltage test circuit400outputs the output signal ‘OUT’ at a high level.

The detection unit500outputs the external reference voltage Ex_Vref as output voltage V_out at the timing at which the level of the output signal ‘OUT’ is shifted.

The semiconductor memory apparatus using the internal voltage test circuit of one embodiment operates as follows.

The external reference voltage Ex_Vref can be applied to the semiconductor memory apparatus from the exterior thereof and has various levels. Thus, during the test mode, the level of the external reference voltage Ex_Vref can be increased from low voltage.

When the external reference voltage Ex_Vref, a level of which increases, has a level lower than that of the internal voltage V_int, the internal voltage test circuit400outputs the output signal ‘OUT’ at a low level. However, when the external reference voltage Ex_Vref has a level higher than that of the internal voltage V_int, the internal voltage test circuit400outputs the output signal ‘OUT’ at a high level.

The detection unit500can be configured to output the external reference voltage Ex_Vref as the output voltage V_out at the timing at which the output signal ‘OUT’ is shifted from a low level to a high level. The timing, at which the output signal ‘OUT’ is shifted from a low level to a high level, represents the time point at which the external reference voltage Ex_Vref has a level identical to that of the internal voltage V_int. Accordingly, the output voltage V_out has a level identical to that of the internal voltage V_int.

As described above, the internal voltage test circuit of the semiconductor memory apparatus according to one embodiment can be configured to monitor a level of voltage generated after packaging the semiconductor memory apparatus, thereby reducing time required for testing the semiconductor memory apparatus.