Circuit and method for adaptively eliminating ringing in signals driving capacitive loads

A control signal may be produced in response to an assertion of a switch signal by asserting the control signal, waiting an adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the adaptive delay, and re-asserting the control signal in response to a current generated according to the control signal becoming zero. The adaptive delay may be adjusted according to a voltage generated using the current. A circuit may include an XOR gate producing the control signal from a switch signal and an output of a Set-Reset Flip-Flop (SRFF), a zero-detect circuit that resets the SRFF when a current generated using the control circuit becomes zero, and a delay circuit to set the SRFF an adaptive delay after assertion of the switch signal and to adjust the adaptive delay according to a voltage generated by the current.

BACKGROUND

Many devices present primarily capacitive loads on their control inputs. Examples include the gates of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), including devices ranging from MOSFETs of digital logic circuits to power MOSFETs. For simplicity of explanation, the description below will be made in terms of MOSFETs, where the control input is a gate, and the capacitive load includes a gate capacitance.

When MOSFETs are operated in a switched mode having an on state and an off state, the highest performance in terms of both frequency and energy efficiency may be achieved by minimizing the time required to transition between the on state and off state and between the off state and on state. Whether a MOSFET is on or off is determined by a gate voltage present across the gate capacitance. Therefore, minimizing the time required for the off/on and on/off transition of the MOSFET may be achieved by minimizing a rise time trand a fall time tfof the gate voltage.

However, circuit inductances associated with the gate may lead to ringing of a control signal provided to the gate capacitance when the control signal is underdamped, may result in damage the MOSFET. On the other hand, when the control signal is overdamped, the rise time trand fall time tfof the control signal are increased. A circuit that is neither overdamped or underdamped is called a critically damped circuit.

Critical damping may be achieved by incorporating an output resistance in the path of the control signal. However, the value of the output resistor needed to achieve critical damping depends on the load capacitance and the inductance in the circuit, among other factors, which can both vary based on manufacturing variations and operational environmental conditions.

Accordingly, a need exists for circuits and methods for minimizing the time to switch a capacitive load having an associated inductance while preventing ringing in the control signal switching the capacitive load, where the circuits automatically adapt to variations in circuit parameters and changing operational environmental conditions.

SUMMARY OF THE INVENTION

Embodiments relate to switching of a capacitive load; for example, switching a gate of a power MOSFET. Specifically, embodiments relate to minimizing ringing by controlling the rise and fall of a control signal provided to the capacitive load.

In an embodiment, a circuit for driving a control signal comprises a zero detect circuit, a first adaptive delay circuit, and an output circuit. The zero detect circuit produces a zero detect signal indicating a current generated according to the control signal becoming zero. The first adaptive delay circuit receives a switch signal, produces a first delay signal indicating that a first adaptive delay has elapsed since an assertion of the switch signal, and adjusts the first adaptive delay according to a first target voltage and an output voltage generated using the current. The output circuit, when the switch signal is asserted, asserts the control signal in response to the assertion of the switch signal, de-assert the control signal in response to the first delay signal indicating that the first adaptive delay has elapsed since the assertion of the switch signal, and re-assert the control signal in response to the zero detect signal indicating the current becoming zero.

In an embodiment, a method of producing an output signal comprises in response to an assertion of a switch signal: asserting the control signal, waiting a first adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the first adaptive delay, and asserting the control signal in response to a current generated according to the control signal becoming zero. The method further comprises adjusting the first adaptive delay according to a first voltage generated using the current.

In an embodiment, a circuit for driving a control signal comprises an Exclusive-OR (XOR) circuit, a Set-Reset Flip-Flop (SRFF), a zero-detect circuit, and a delay circuit. The XOR gate has a first input coupled to a switch signal, a second input coupled to an output of the SRFF, and an output coupled to the control signal. The zero-detect circuit provides a pulse to a Reset input of the SRFF in response to a current generated according to the control circuit becoming zero. The delay circuit provides a first pulse to a Set input of the SRFF a first adaptive delay after an assertion of the switch signal and adjusts the first adaptive delay according to a voltage generated by the current.

DETAILED DESCRIPTION

Embodiments of the present application relate to enabling robust switching of capacitive loads without overshoot or undershoot. Specifically, embodiments may automatically adapt to changes in device parameters so as to prevent ringing in a control signal while providing fast rise times trand fall times tfof the control signal.

The present disclosure may relate to power semiconductor devices such as power MOSFETs.

A detailed description of embodiments is provided below along with accompanying figures. The scope of this disclosure is limited only by the claims and encompasses numerous alternatives, modifications and equivalents. Although steps of various processes are presented in a given order, embodiments are not necessarily limited to being performed in the listed order. In some embodiments, certain operations may be performed simultaneously, in an order other than the described order, or not performed at all.

Numerous specific details are set forth in the following description. These details are provided to promote a thorough understanding of the scope of this disclosure by way of specific examples, and embodiments may be practiced according to the claims without some of these specific details. Accordingly, the specific embodiments of this disclosure are illustrative, and are not intended to be exclusive or limiting. For the purpose of clarity, technical material that is known in the technical fields related to this disclosure has not been described in detail so that the disclosure is not unnecessarily obscured.

As used herein, a signal is asserted when it has a value corresponding to logical-true or to an active or on state of the device or circuit being controlled by the signal, and is de-asserted when it has a value corresponding to logical-false or to an inactive or off state of the device or circuit being controlled by the signal. Assertion of a signal refers to the act of driving the signal from the de-asserted to the asserted state, and de-assertion of the signal refers to the act of driving the signal from the asserted to the de-asserted state. The example embodiments presented herein use active-high signals where assertion of a signal corresponds to driving the signal to a high value which may correspond to 1 or logical-true (i.e., to a rising edge) and de-assertion of the a signal corresponds to falling edge that driving the signal to a low value which may correspond to 0 or logical-false (i.e., to a falling edge), but embodiments are not limited thereto, and in other embodiments, some or all of the signals may be active-low signals instead.

FIG. 1illustrates a circuit100according to an embodiment. The circuit100includes a Q-Cell logic circuit102, a driver circuit104, a resistor106, and an n-channel MOSFET108. Also shown inFIG. 1is an interconnect inductance LPcorresponding to a parasitic inductance of the connection between the driver104and the MOSFET108, and a gate capacitance CGcorresponding to the gate capacitance between the gate and the source of the MOSFET108.

The Q-Cell logic circuit102receives a switching signal SW. The Q-cell circuit may also receive a positive and negative current sense signals ICSPand ICSNand a gate capacitance voltage VC. The Q-cell circuit produces a Q-cell signal VQCaccording to the switch signal SW, a current to the gate of the MOSFET108determined using current sense signals ICSPand ICSN, and timing parameters determined using the capacitance voltage VC, as explained below.

The driver circuit104generates the gate driver output VGDaccording to the Q-cell signal VQC. In embodiments, the gate driver circuit104may provide current buffering, output impedance matching, voltage translation, or the like.

Although the circuit100ofFIG. 1includes a driver circuit104, embodiments are not limited thereto, and in other embodiments the driver circuit104is absent and the Q-Cell logic circuit102drives the gate of the MOSFET108. Furthermore, embodiments are not limited to driving devices like the n-channel MOSFET108ofFIG. 1, and may instead drive p-channel MOSFETS, Insulated-Gate Bipolar Transistors (IGBT), or the like.

The resistor106operates to provide damping of the gate driver output VGD. In an embodiment, the resistor106is not a separate component, but instead represents the output resistance of the driver circuit104.

The parameters used to determine the value of the resistor106may include an output impedance of the driver circuit104, the interconnect inductance LPof the connection coupling the driver circuit104to the MOSFET108through the resistor106, and the gate capacitance CGof the MOSFET108. The parameters may be estimated for an anticipated operating environment, such as an anticipated operating temperature.

In an embodiment, the resistor106has a value chosen according to the estimated circuit parameters and operating conditions to critically damp the gate driver output VGD; for example, the resistance R of resistor106may be equal to

R=2·LPLP·CGEquation⁢⁢1
where LPis an estimated inductance of the interconnect inductance LPand CGis an estimated capacitance of a gate capacitance CG; for example, when C is 400 picofarads and L is 1 nanohenry, R may be 3.1 ohms. In another embodiment wherein the Q-cell circuit102is relied on to prevent ringing, the resistor106has a value chosen to underdamp the gate driver output VGD; that is, the resistance R of resistor106may be substantially less than the resistance indicated by Equation 1; for example, given the capacitance and inductance values above, the resistance of resistor106may be 2 ohms. However, embodiments are not limited to the resistor values used in the examples above.

Furthermore, although the circuit100ofFIG. 1drives only a single capacitive load (the single MOSFET108), embodiments are not limited thereto, and in embodiments, a plurality of capacitive loads connected in parallel may be driven.

FIG. 2Aillustrates operation of a circuit such as shown inFIG. 1in the absence of the Q-cell circuit102, that is, if the switch signal SW were directly coupled to the input of the driver circuit104.FIG. 2Ais provided to show advantages of embodiments of the present disclosure by providing a contrast toFIG. 2B.FIG. 2Aillustrates an output voltage VGDof a driver circuit such as driver circuit104, a capacitance voltage VCacross a load capacitance such as the gate capacitance CGof MOSFET108, a capacitance current ICflowing to the load capacitance, and a voltage drop VRacross an output resistance such as the resistor106.

InFIG. 2A, the circuit comprising the resistor106, interconnect inductance LP, and gate capacitance CGis assumed to be underdamped. As a result, when the gate driver output VGDtransitions from low to high, ringing occurs with a frequency f of ω/2π, equal to:

f=12⁢π·1L⁢C+(R2⁢L)2Equation⁢⁢2
The amplitude of the ringing decays at an exponential rate e−t/α, where α=R/2 L.

As can be seen inFIG. 2A, the ringing that occurs in response to the low to high transition of the gate driver output VGDcauses the gate capacitance voltage VCto rise above the maximum voltage value VDDof the gate driver output VGD. Furthermore, the ringing causes the voltage drop VRacross the resistor106to experience additional periods of time when it is non-zero; during these periods, power is dissipated as heat in the resistor106.

Similar effects occur in response to the high to low transition of the gate driver output VGD. The ringing that occurs in response to the high to low transition of the gate driver output VGDcauses the gate capacitance voltage VCto drop below zero; that is, to go negative. Furthermore, the ringing causes the voltage drop VRacross the resistor106to experience additional periods of time when it is non-zero; during these periods, power is dissipated as heat in the resistor106.

The excursions of the gate capacitance voltage VCabove the maximum voltage value VDDand below zero may have detrimental effects on the circuit100. Furthermore, the power dissipated as heat in the resistor106not only wastes energy but also may require additional measures to be taken to remove heat from the circuit100, increasing the cost, complexity, size, or a combination thereof of a device employing the circuit100.

FIG. 2Billustrates operation of the circuit100shown inFIG. 1.FIG. 2Billustrates the switch signal SW, the Q-cell signal VQCoutput by the Q-Cell logic circuit102, the capacitance voltage VCacross the gate capacitance CGof MOSFET108, a capacitance current ICflowing to the gate capacitance CG, and a voltage drop VRacross the resistor106.

InFIG. 2B, the switch signal SW is a binary signal with a clock period Tclkand an asserted (high) duration Tclkhwithin each clock cycle.

At a zeroth time t0, at the beginning of a first clock period, the switch signal SW transitions from low to high. In response, the Q-Cell logic circuit102asserts the Q-cell signal VQC, which causes the driver circuit104to assert the gate driver output VGDafter a propagation delay time. This causes the capacitance current ICto be sourced through the resistor106, which causes the capacitance voltage VCto rise, energy to be stored in a magnetic field of the interconnect inductance LP, and a voltage drop VRacross the resistor106.

At a first time t1occurring a first adaptive delay after the zeroth time t0, the Q-Cell logic circuit102de-asserts the Q-cell signal VQC. This causes the driver circuit104to de-assert the gate driver output VGDafter the propagation delay time. In response to the de-assertion of the gate driver output VGD, the energy stored in the magnetic field of the interconnect inductance LPdischarges, thereby continuing to source the capacitance current ICinto the gate capacitance CG, causing the capacitance voltage VCto continue to rise and a voltage drop VRacross the resistor106.

A second time t2corresponds to the energy stored in the magnetic field of the interconnect inductance LPbeing completely discharged, which causes the capacitance current ICto be zero. The Q-Cell logic circuit102detects the capacitance current ICbecoming zero (such as by detecting that the voltage drop VRacross resistor106is zero) and in response re-asserts the Q-cell signal VQC, which causes the driver circuit104to re-assert the gate driver output VGDafter a propagation delay time. In an embodiment, detecting the capacitance current ICbecoming zero may be performed by detecting a zero-crossing of the capacitance current IC. In another embodiment, detecting the capacitance current ICbecoming zero may be performed by detecting that a magnitude of the capacitance current ICis less than a zero detect threshold value.

If at the second time t2the capacitance voltage VCis equal to the maximum voltage value VDDof the gate driver output VGD, the capacitance current ICwill remain at zero when the gate driver output VGDis asserted. However, when the capacitance voltage VCis less than or greater than the maximum voltage value VDDat the second time t2, the Q-Cell logic circuit102will adjust the first adaptive delay that determines how soon the first time t1follows after the zeroth time to (that is, how long the Q-Cell logic circuit102first asserts the Q-cell signal VQCin response to the assertion of the switch signal SW).

In an embodiment, the Q-Cell logic circuit102may reduce the first adaptive delay time when the capacitance voltage VCis greater than the maximum voltage value VDDat the second time t2, and may increase the first adaptive delay time when the capacitance voltage VCis less than the maximum voltage value VDDat the second time t2. As a result, the first adaptive delay time may converge to a value that causes the capacitance voltage VCto reach the maximum voltage value VDDat the second time t2that corresponds to the capacitance current ICbecoming zero.

At a third time t3, within the first clock period, the switch signal SW transitions from high to low. In response, the Q-Cell logic circuit102de-asserts the Q-cell signal VQC, which causes the driver circuit104to de-assert the gate driver output VGDafter a propagation delay time. This causes the capacitance current ICto be sunk through the resistor106, which causes the capacitance voltage VCto decrease, energy to be stored in a magnetic field of the interconnect inductance LP, and a voltage drop VRacross the resistor106.

At a fourth time t4occurring a second adaptive delay after the third time t3, the Q-Cell logic circuit102asserts the Q-cell signal VQC. This causes the driver circuit104to assert the gate driver output VGDafter the propagation delay time. In response to the assertion of the gate driver output VGD, the energy stored in the magnetic field of the interconnect inductance LPdischarges, thereby continuing to sink the capacitance current ICout of the gate capacitance CG, causing the capacitance voltage VCto continue to decrease and a voltage drop VRacross the resistor106.

A fifth time t5corresponds to the energy stored in the magnetic field of the interconnect inductance LPbeing completely discharged, which causes the capacitance current ICto be zero. The Q-Cell logic circuit102detects the capacitance current ICbecoming zero (such as by detecting that the voltage drop VRacross resistor106is zero) and in response de-asserts the Q-cell signal VQCagain, which causes the driver circuit104to again de-assert the gate driver output VGDafter a propagation delay time.

If at the fifth time t5the capacitance voltage VCis equal to zero, the capacitance current ICwill remain at zero when the gate driver output VGDis again de-asserted. However, when the capacitance voltage VCis less than or greater than zero at the fifth time t5, the Q-Cell logic circuit102will adjust the second adaptive delay that determines how soon the fourth time t4follows after the third time t3(that is, how long the Q-Cell logic circuit102first de-asserts the Q-cell signal VQCin response to the de-assertion of the switch signal SW).

In an embodiment, the Q-Cell logic circuit102may increase the second adaptive delay time when the capacitance voltage VCis greater than zero at the fifth time t5, and may decrease the second adaptive delay time when the capacitance voltage VCis less than zero at the fifth time t5. As a result, the second adaptive delay time may converge to a value that causes the capacitance voltage VCto reach zero at the fifth time t5that corresponds to the capacitance current ICbecoming zero.

When the first and second adaptive delay times have converged as described above, there is no energy in the interconnect inductance LPafter the second time t2or after the fifth time t5; as a result, because the capacitance voltage VCis, at the time, equal to the gate driver output VGD, there is nothing to generate current in the circuit comprising the resistor106, interconnect inductance LP, and gate capacitance CG, and therefore no ringing occurs. When no ringing occurs, the detrimental effects of ringing (such as wasted energy or increased signal noise) are eliminated.

FIG. 3illustrates a circuit300including a Q-Cell logic circuit302according to an embodiment. The circuit300also includes a driver circuit304, a resistor306, an interconnect inductance LP, and a gate capacitance CG. The driver circuit304, resistor306, interconnect inductance LP, and load capacitance CGofFIG. 3correspond to the driver circuit104, resistor106, interconnect inductance LP, and gate capacitance CGofFIG. 1, and accordingly description thereof are omitted in the interest of brevity. In embodiments, the driver circuit304and resistor306may be absent, and the Q-Cell logic circuit302may drive the gate capacitance CGthrough the interconnect inductance LP, but embodiments are not limited thereto.

The Q-Cell logic circuit302includes a positive adaptive delay circuit310, a negative adaptive delay circuit312, an OR gate314, a pulse generator316, a Set-Reset Flip-Flop (SRFF)318, an Exclusive-OR (XOR) gate320, a zero detect circuit322, a sample-and hold (S/H) circuit324, a positive-level comparator326, and a negative-level comparator328.

The Q-Cell logic circuit302receives a switch signal SW for controlling the a capacitance voltage VCof a gate capacitance CG, a positive current sense signal ICSPand a negative current sense signal ICSNthat may be used to measure a capacitance current ICflowing into the gate capacitance CG, and a capacitance voltage VCcorresponding to the voltage on the gate capacitance CG. The Q-Cell logic circuit302produces a Q-cell signal VQCthat may be used to drive the gate capacitance CGwithout generating undesired ringing.

The positive adaptive delay circuit310generates a positive delay signal Pt+ in response to a positive transition (i.e., an assertion of) the switch signal SW. The positive delay signal Pt+ has an asserted duration equal to a positive delay τ+, which may correspond to the first adaptive delay described with respect toFIGS. 1, 2A, and 2B. The positive adaptive delay circuit310adjusts the value of the positive delay τ+ according to a positive feedback signal FB+.

An initial value of the positive delay τ+ may be determined according to

τ+=π2⁢LE⁢CEEquation⁢⁢3
where LEis the estimated inductance of the interconnect inductance LPand CEis the estimated capacitance of the gate capacitance CGat the expected operating conditions. For example, when the estimated capacitance CEis 400 picofarads and the estimated inductance LEis 400 picohenries, the initial value for the positive delay τ+ may be 620 picoseconds. The value of the positive delay τ+ may be adjusted cycle by cycle to accommodate for differences between actual and estimated values for L, C, and the resistance R of resistor106, and for value differences in these parameters that may arise due to, for example, age, temperature, offsets, delays, or package stress. In an embodiment, the value of the positive delay τ+ may vary within a range from 100 picoseconds to 100 nanoseconds, but embodiments are not limited thereto.

The negative adaptive delay circuit312generates a negative delay signal Pt− in response to a negative transition (i.e., a de-assertion of) the switch signal SW. The negative delay signal Pt− has an asserted duration equal to a negative delay τ−, which may correspond to the second adaptive delay described with respect toFIGS. 1, 2A, and 2B. The negative adaptive delay circuit312adjusts the value of the negative delay τ− according to a negative feedback signal FB−.

An initial value of the negative delay τ− may be determined according to

τ-=π2⁢LE⁢CEEquation⁢⁢4
The value of the negative delay τ− may be adjusted cycle by cycle to accommodate for differences between actual and estimated values for L, C, and the resistance R of resistor106, and for value differences in these parameters that may arise due to, for example, age, temperature, offsets, delays, or package stress. In an embodiment, the value of the negative delay τ− may vary within a range from 100 picoseconds to 100 nanoseconds, but embodiments are not limited thereto.

In an embodiment, because the positive delay signal Pt+ is asserted in response to an assertion (a rising edge) of the switch signal SW and the negative delay signal Pt− is asserted in response to a de-assertion (a falling edge) of the switch signal SW, and the positive delay τ+ and the negative delay τ− are substantially smaller than half a clock cycle of the switch signal SW, the positive delay signal Pt+ and the negative delay signal Pt− are each only asserted when the other is in a de-asserted state.

The OR gate314operates to produce a signal that is asserted whenever the positive delay signal Pt+, the negative delay signal Pt−, or both are asserted, and is de-asserted otherwise. The pulse generator316generates a short pulse in response to the de-assertion of the signal produced by the OR gate314. As a result, the pulse generator316generates a short pulse in response to either the positive delay signal Pt+ or the negative delay signal Pt− being de-asserted. The duration of the short pulse is selected to guarantee that it is long enough to set the SRFF318.

The SRFF318receives the output of the pulse generator316on its Set input and receives a zero detect signal ZD on its Reset input. As a result, the output Q of the SRFF318is asserted in response to the positive delay signal Pt+ or the negative delay signal Pt− being de-asserted, and the output Q of the SRFF318is de-asserted in response to the zero detect signal ZD being asserted.

The XOR gate320produces the Q-cell signal VQCby outputting the switch signal SW when the output Q of the SRFF318is de-asserted and inverting the switch signal SW when the output Q of the SRFF318is asserted.

The zero detect circuit322produces a pulse on the zero detect signal ZD whenever the capacitance current ICsourced to or sunk from the gate capacitance CGbecomes or passes through zero. In the embodiment ofFIG. 3, the zero detect circuit322determines that the capacitance current ICis equal to or has passed through zero when the voltage drop VRacross the resistor306, measured using the positive current sense signal ICSPand the negative current sense signal ICSN, is equal to or has passed through zero volts, but embodiments are not limited thereto. The pulses produced on the zero detect signal ZD are sufficiently long to reset the SRFF318and to allow the S/H circuit324to accurately sample the capacitance voltage VC.

The S/H circuit324samples the capacitance voltage VCat a time immediately after the zero detect signal ZD indicates that the capacitance current ICsourced to or sunk from the gate capacitance CGhas become or passed through zero, and holds the sampled voltage value until the next time the zero detect signal ZD indicates that the capacitance current ICsourced to or sunk from the gate capacitance CGhas become or passed through zero.

The positive-level comparator326compares the sampled capacitance voltage VCoutput by the S/H circuit324to the maximum voltage value VDDof the gate driver output VGD. The positive-level comparator326asserts the positive feedback signal FB+ when the sampled capacitance voltage VCis greater than the maximum voltage value VDD.

The positive adaptive delay circuit310may decrease the positive delay τ+ in response to the positive feedback signal FB+ being asserted at a positive feedback sampling time during a clock cycle of the switch signal SW, and may increase the positive delay τ+ in response to the positive feedback signal FB+ being de-asserted at the positive feedback sampling time. In an embodiment, the positive feedback sampling time may correspond to the time of de-assertion (that is, the falling edge) of the switch signal SW. In another embodiment, the positive feedback sampling time may correspond to a predetermined delay after the pulse on the zero detect signal ZD.

The negative-level comparator328compares the sampled capacitance voltage VCoutput by the S/H circuit324to 0V. The negative-level comparator328asserts the negative feedback signal FB− when the sampled capacitance voltage VCis greater than 0V.

The negative adaptive delay circuit312may increase the negative delay τ− in response to the negative feedback signal FB− being asserted at a negative feedback sampling time during a clock cycle of the switch signal SW, and may decrease the negative delay τ− in response to the negative feedback signal FB− being de-asserted at the negative feedback sampling time. In an embodiment, the negative feedback sampling time may correspond to the time of assertion (that is, the rising edge) of the switch signal SW. In another embodiment, the negative feedback sampling time may correspond to a predetermined delay after the pulse on the zero detect signal ZD.

FIG. 4illustrates operation of the circuit300ofFIG. 3according to an embodiment. Shown inFIG. 4are the switch signal SW, the Q-cell signal VQC, the capacitance voltage VC, the capacitance current IC, an inductor voltage VLacross the interconnect inductance LP, a voltage drop VRacross the resistor306, the positive delay signal Pt+, the negative delay signal Pt−, the zero detect signal ZD, and the output Q of the SRFF318.

At a zeroth time to, the switch signal SW is asserted. Because the output Q of the SRFF318is de-asserted, the Q-Cell logic circuit302asserts the Q-cell signal VQCin response to the switch signal SW being asserted, the output of the driver circuit304is driven to maximum voltage value VDD, and the capacitance current ICflows into the gate capacitance CG, causing the capacitance voltage VCto rise. The capacitance current ICflowing from the driver circuit304to the gate capacitance CGcauses the inductor voltage VLand the voltage drop VRto develop. The voltage drop VRis proportional to the capacitance current IC. The inductor voltage VLis initially equal to the output voltage of the driver circuit304but decreases as the magnetic field of the interconnect inductance LPincreases increase in strength.

Also in response to the switch signal SW being asserted at the zeroth time t0, the positive adaptive delay circuit310produces a pulse having a duration corresponding to the current value of the positive delay τ+ on the positive delay signal Pt+.

At the first time t1, the pulse on the positive delay signal Pt+ ends, and in response the output Q of the SRFF318goes high, which causes the Q-cell signal VQCto go low, and the driver circuit304to drive its output low.

The output of the driver circuit304being driven low causes the interconnect inductance LPto release the energy stored in its magnetic field, causing the inductance voltage VLto go negative as the capacitance current ICcontinues to flow and the capacitance voltage VCcontinues to rise. As the magnetic field of the interconnect inductance LPdecreases, the capacitance current ICalso decreases.

At a second time t2, the magnetic field of the interconnect inductance LPgoes to zero and as a result the capacitance current ICgoes to zero. Because the capacitance current ICis zero, the voltage drop VRacross the resistor306is also zero. This causes the zero detect circuit322to output a pulse on the zero detect signal ZD.

In response to the pulse on the zero detect signal ZD, the output Q of the SRFF318is de-asserted, causing the Q-cell signal VQCto be asserted, which causes the output of the driver circuit304to be driven to the maximum voltage value VDD.

If the capacitance voltage VCis at the maximum voltage value VDDat this time, no current flows from the driver circuit403to the gate capacitance CG, so the capacitance current IC, voltage drop VR, and inductor voltage VLall remain at zero. If the capacitance voltage VCis not equal to the maximum voltage value VDDat this time, current will flow to or from the gate capacitance CGuntil the capacitance voltage VCis equal to the maximum voltage value VDD. The Q-Cell logic circuit302operates to adjust the positive delay τ+ so that the capacitance voltage VCis at the maximum voltage value VDDwhen the magnetic field of the interconnect inductance LPgoes to zero while the switch signal SW is asserted.

Also in response to the pulse on the zero detect signal ZD, the S/H circuit324samples and holds the value of the capacitance voltage VC. The positive-level comparator326produces the positive feedback signal FB+ by asserting the positive feedback signal FB+ when the capacitance voltage VCis greater than the maximum voltage value VDD, and de-asserting the positive feedback signal FB+ otherwise. Accordingly, during the time starting at the end of the pulse on the zero detect signal ZD following the second time t2and ending at the next pulse on the zero detect signal ZD at a fifth time t5, the output of the S/H circuit324corresponds to the value of the capacitance voltage VCat the second time t2, and the positive feedback signal FB+ is asserted if the capacitance voltage VCwas higher at the second time t2than the maximum voltage value VDD.

At a time t3, the switch signal SW is de-asserted. Because the output Q is de-asserted, the Q-Cell logic circuit302de-asserts the Q-cell signal VQCin response to the switch signal SW being de-asserted, the output of the driver circuit304is driven to zero volts, and the capacitance current ICflows from the gate capacitance CG, causing the capacitance voltage VCto decrease. The capacitance current ICflowing to the driver circuit304from the gate capacitance CGcauses the inductor voltage VLand the voltage drop VRto develop. The voltage drop VRis proportional to the capacitance current IC. The inductor voltage VLis initially equal to the negative of the capacitance voltage VC, but the magnitude of the inductor voltage VLdecreases as the magnetic field of the interconnect inductance LPincreases in strength.

Also in response to the switch signal SW being de-asserted at the third time t3, the negative adaptive delay circuit312produces a pulse having a duration corresponding to the current value of the negative delay τ− on the negative delay signal Pt−.

In an embodiment, also in response to switch signal SW being de-asserted at the third time t3, the positive adaptive delay circuit310may adjust the value of the positive delay τ+ according to the positive feedback signal FB+. When the positive feedback signal FB+ is asserted, indicating that the capacitance voltage VCmay have had a higher than desired value at the time when the magnetic field of the interconnect inductance LPwent to zero, the positive adaptive delay circuit310may decrease the value of the positive delay τ+. When the positive feedback signal FB+ is de-asserted, indicating that the capacitance voltage VCmay have had a lower than desired value at the time when the magnetic field of the interconnect inductance LPwent to zero, the positive adaptive delay circuit310may increase the value of the positive delay τ+. The new value of the positive delay τ+ is indicated as τ+′ inFIG. 4.

At the fourth time t4, the pulse on the negative delay signal Pt− ends, and in response the output Q of the SRFF318goes high, which causes the Q-cell signal VQCto go high, and the driver circuit304to drive its output to the maximum voltage value VDD.

The output of the driver circuit304being driven to the maximum voltage value VDDcauses the interconnect inductance LPto release the energy stored in its magnetic field, causing the inductance voltage VLto go positive as the capacitance current ICcontinues to flow from the gate capacitance CGand the capacitance voltage VCcontinues to decrease. As the magnitude of the magnetic field of the interconnect inductance LPdecreases, the magnitude of the capacitance current ICalso decreases.

At a fifth time t5, the magnetic field of the interconnect inductance LPgoes to zero and as a result the capacitance current ICgoes to zero. Because the capacitance current ICis zero, the voltage drop VRacross the resistor306is also zero. This causes the zero detect circuit322to output a pulse on the zero detect signal ZD.

In response to the pulse on the zero detect signal ZD, the output Q of the SRFF318is de-asserted, causing the Q-cell signal VQCto be de-asserted, which causes the output of the driver circuit304to be driven to zero volts.

If the capacitance voltage VCis zero at this time, no current flows between the driver circuit403to the gate capacitance CG, so the capacitance current IC, voltage drop VR, and inductor voltage VLall remain at zero. If the capacitance voltage VCis not equal to the maximum voltage value VDDat this time, current will flow to or from the gate capacitance CGuntil the capacitance voltage VCis equal to zero. The Q-Cell logic circuit302operates to adjust the negative delay τ− so that the capacitance voltage VCis at zero when the magnetic field of the interconnect inductance LPgoes to zero while the switch signal SW is de-asserted.

Also in response to the pulse on the zero detect signal ZD, the S/H circuit324samples and holds the value of the capacitance voltage VC. The negative-level comparator328produces the negative feedback signal FB− by asserting the negative feedback signal FB− when the capacitance voltage VCis greater than zero, and de-asserting the negative feedback signal FB− otherwise. Accordingly, during the time starting at the end of the pulse on the zero detect signal ZD following the fifth time t5and ending at the next pulse on the zero detect signal ZD (which occurs in the next cycle of the switch signal SW), the output of the S/H circuit324corresponds to the value of the capacitance voltage VCat the second time t2, and the negative feedback signal FB− is asserted if the capacitance voltage VCwas greater than zero at the fifth time t5.

In an embodiment, in response to switch signal SW being asserted at the second zeroth time t0′ (i.e., at the beginning of the second cycle of the switch signal SW), the negative adaptive delay circuit312may adjust the value of the negative delay τ− according to the negative feedback signal FB−. When the negative feedback signal FB− is asserted, indicating that the capacitance voltage VCmay have had a higher than desired value at the last time at which the magnetic field of the interconnect inductance LPwent to zero, the negative adaptive delay circuit312may increase the value of the negative delay τ−. When the positive feedback signal FB− is de-asserted, indicating that the capacitance voltage VCmay have had a lower than desired value at the last time at which the magnetic field of the interconnect inductance LPwent to zero, the negative adaptive delay circuit312may decrease the value of the negative delay τ−.

Accordingly, the Q-Cell logic circuit302continuously adjusts the positive delay τ+ so that after a rising edge of the switch signal SW, the capacitance voltage VCreaches a desired high level at a time when the energy stored in the interconnect inductance LPgoes to zero, and adjusts the negative delay τ− so after a falling edge of the switch signal SW, the capacitance voltage VCreaches a desired low level at a time when the energy stored in the interconnect inductance LPgoes to zero. The lack of stored energy in the interconnect inductance LPprevents ringing of the capacitance voltage VC.

FIG. 5illustrates a zero detect circuit522which in an embodiment may be used in the zero detect circuit332ofFIG. 3. The zero detect circuit522includes a comparator502, a buffer504having a propagation delay, and an XOR gate506. In the embodiment shown, the comparator502incorporates hysteresis, but embodiments are not limited thereto.

The comparator502receives a positive current sense signal ICSPand a negative current sense signal ICSN. The positive current sense signal ICSPand the negative current sense signal ICSNmay have a voltage difference corresponding to the capacitance current IC. The output of the comparator502is asserted when a voltage of the positive current sense signal ICSPis greater than a voltage of the negative current sense signal ICSN, and de-asserted otherwise.

The buffer504and XOR gate506operate to produce a short pulse (having a duration corresponding to the propagation delay of the buffer504) in response to each high-to-low or low-to-high transition of the output of the comparator502. As a result, the zero detect circuit522produces a pulse each time the capacitance current ICpasses through zero.

FIG. 6Aillustrates a positive adaptive delay circuit610which in an embodiment may be used in the positive adaptive delay circuit310ofFIG. 3. The positive adaptive delay circuit610includes a programmable pulse generator620, an up/down (U/D) counter622, and an inverter628. The positive adaptive delay circuit610receives the switch signal SW and the positive feedback signal FB+, and produces the positive delay signal Pt+.

The inverter628receives the positive feedback signal FB+ and provides an inverted version of it to the U/D input of the U/D counter622. Accordingly, the U/D counter622will, when clocked, count up when the positive feedback signal FB+ is de-asserted and count down when the positive feedback signal FB+ is asserted.

The U/D counter622counts in response to a falling edge of the switch signal SW, counting up when the positive feedback signal FB+ is de-asserted and counting down when the positive feedback signal FB+ is asserted to produce an n-bit positive delay count QP[n:1]. In an embodiment, n may be 6 or more, but embodiments are not limited thereto. In an embodiment, the U/D counter622may include circuits to receive and load an initial positive count value into the positive delay count QP.

The programmable pulse generator620asserts the positive delay signal Pt+ for a duration corresponding to the positive delay count QP in response to a rising edge of the switch signal SW, and de-asserts the positive delay signal Pt+ in response to that duration elapsing.

FIG. 6Billustrates a negative adaptive delay circuit612which in an embodiment may be used in the negative adaptive delay circuit312ofFIG. 3. The negative adaptive delay circuit612includes a programmable pulse generator630, an up/down (U/D) counter632, and an inverter638. The negative adaptive delay circuit612receives the switch signal SW and the negative feedback signal FB−, and produces the negative delay signal Pt−.

The inverter638receives the switch signal SW and provides an inverted version of it to the trigger input of the programmable pulse generator630and to the clock input of the U/D counter632. Accordingly, programmable pulse generator630will generate a pulse in response to a falling edge of the switch signal SW, and the U/D counter622will count in response to a rising edge of the switch signal SW.

The U/D counter632counts in response to a rising edge of the switch signal SW, counting up when the negative feedback signal FB− is asserted and counting down when the negative feedback signal FB− is de-asserted to produce an n-bit negative delay count QN[n:1]. In an embodiment, n may be 6 or more, but embodiments are not limited thereto. In an embodiment, the U/D counter632may include circuits to receive and load an initial negative count value into the negative delay count QN.

The programmable pulse generator630asserts the negative delay signal Pt− for a duration corresponding to the negative delay count QN in response to a falling edge of the switch signal SW, and de-asserts the negative delay signal Pt− in response to that duration elapsing.

FIG. 7Aillustrates a positive adaptive delay circuit710which in an embodiment may be used in the positive adaptive delay circuit310ofFIG. 3. The positive adaptive delay circuit710includes a programmable pulse generator720, and an up/down (U/D) counter722, an AND gate724, a fixed pulse generator726, and an inverter728. The positive adaptive delay circuit710receives the switch signal SW, the zero detect signal ZD, and the positive feedback signal FB+, and produces the positive delay signal Pt+.

The inverter728receives the positive feedback signal FB+ and provides an inverted version of it to the U/D input of the U/D counter722. Accordingly, the U/D counter722will, when clocked, count up when the positive feedback signal FB+ is de-asserted and count down when the positive feedback signal FB+ is asserted.

The fixed pulse generator726produces a pulse having a predetermined duration in response to a falling edge of the zero detect signal ZD. The predetermined duration may correspond to the sum of a settling time of S/H circuit324ofFIG. 3and a propagation time of the positive-level comparator326ofFIG. 3.

When the switch signal SW is asserted, the AND gate724outputs a pulse according to the output of the fixed pulse generator726; the output of the AND gate therefore has a falling edge only when the fixed pulse generator726has a falling edge while the switch signal SW is asserted.

The U/D counter722counts in response to a falling edge of the output of the AND gate724, counting up when the positive feedback signal FB+ is de-asserted and counting down when the positive feedback signal FB+ is asserted to produce an n-bit positive delay count QP[n:1]. Accordingly, the U/D counter722updates the value of the positive delay count QP a predetermined time after the sampling of the capacitance voltage VCduring a period when the switch signal SW is asserted. In an embodiment, the U/D counter722may include circuits to receive and load an initial positive count value into the positive delay count QP.

The programmable pulse generator720asserts the positive delay signal Pt+ for a duration corresponding to the positive delay count QP in response to a rising edge of the switch signal SW, and de-asserts the positive delay signal Pt+ in response to that duration elapsing.

FIG. 7Billustrates a negative adaptive delay circuit712which in an embodiment may be used in the negative adaptive delay circuit312ofFIG. 3. The negative adaptive delay circuit712includes a programmable pulse generator730, an up/down (U/D) counter732, an AND gate734, a fixed pulse generator736, and an inverter738. The negative adaptive delay circuit712receives the switch signal SW, the zero detect signal ZD, and the negative feedback signal FB−, and produces the negative delay signal Pt−.

The inverter738receives the switch signal SW and provides an inverted version of it to the trigger input of the programmable pulse generator730and to an input of the AND gate734. Accordingly, the programmable pulse generator730will generate a pulse in response to a falling edge of the switch signal SW.

The fixed pulse generator736produces a pulse having a predetermined duration in response to a falling edge of the zero detect signal ZD. The predetermined duration may correspond to the sum of a settling time of S/H circuit324ofFIG. 3and a propagation time of the negative-level comparator328ofFIG. 3.

When the switch signal SW is de-asserted, the AND gate734outputs a pulse according to the output of the fixed pulse generator736; the output of the AND gate therefore has a falling edge when the fixed pulse generator736has a falling edge while the switch signal SW is de-asserted.

The U/D counter732counts in response to the falling edge of the output of the AND gate734, counting up when the negative feedback signal FB− is asserted and counting down when the negative feedback signal FB− is de-asserted to produce an n-bit negative delay count QN[n:1]. Accordingly, the U/D counter732updates the value of the negative delay count QN a predetermined time after the sampling of the capacitance voltage VCduring a period when the switch signal SW is de-asserted. In an embodiment, the U/D counter732may include circuits to receive and load an initial negative count value into the negative delay count QN.

The programmable pulse generator730asserts the negative delay signal Pt− for a duration corresponding to the negative delay count QN in response to a falling edge of the switch signal SW, and de-asserts the negative delay signal Pt− in response to that duration elapsing.

FIG. 8illustrates a process800for generating a drive signal according to an embodiment. The process800may be performed using a circuit such as the Q-Cell logic circuit302ofFIG. 3, but embodiments are not limited thereto.

At S802, the process800waits for a switch signal SW to be asserted (for example, by waiting for the rising edge of an active-high signal). In response to the switch signal SW being asserted, the process800proceeds to S804.

At S804, the process800asserts a Q-Cell output VQCand then waits a positive delay τ+. In response to the positive delay τ+ elapsing, the process800proceeds to S806.

At S806, the process800de-asserts the Q-Cell output VQCand then waits for a zero crossing of a current being controlled by the Q-Cell output VQC, here, a capacitance current ICof a capacitive load being driven according to the Q-Cell output VQC. In response to the zero crossing of the capacitance current IC, the process800proceeds to S808.

At S808, the process800asserts the Q-Cell output VQCand measures a voltage produced according to the current of S806; in this example the voltage that is measured is a capacitance voltage VCgenerated according to the capacitance current IC.

At S810, the process800compares the measured voltage (the capacitance voltage VC) against a positive target voltage. Here, the positive target voltage is the maximum voltage value VDDthat can be output by the circuit that is the source of the capacitance current IC, but embodiments are not limited thereto. When the measured voltage is greater than the positive target voltage, at S810the process800proceeds to S814; otherwise the process800proceeds to S812.

At S812, the process800increases the positive delay τ+ and then proceeds to S822.

At S814, the process800decreases the positive delay τ+ and then proceeds to S822.

At S822, the process800waits for the switch signal SW to be de-asserted (for example, by waiting for the falling edge of an active-high signal). In response to the switch signal SW being de-asserted, the process800proceeds to S824.

At S824, the process800de-asserts the Q-Cell output VQCand then waits a negative delay τ−. In response to the negative delay τ− elapsing, the process800proceeds to S826.

At S826, the process800asserts the Q-Cell output VQCand then waits for a zero crossing of the current being controlled by the Q-Cell output VQC; here, the capacitance current IC. In response to the zero crossing of the capacitance current IC, the process800proceeds to S828.

At S828, the process800de-asserts the Q-Cell output VQCand measures a voltage produced according to the current of S826; in this example the capacitance voltage VCgenerated according to the capacitance current IC.

At S830, the process800compares the measured voltage (the capacitance voltage VC) against a negative target voltage. Here, the negative target voltage may be zero volts, but embodiments are not limited thereto. When the measured voltage is greater than the negative target voltage, at S830the process800proceeds to S834; otherwise the process800proceeds to S832.

At S832, the process800decreases the negative delay τ− and then proceeds to S802

At S834, the process800increases the negative delay τ− and then proceeds to S802.

Aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples. Numerous alternatives, modifications, and variations to the embodiments as set forth herein may be made without departing from the scope of the claims set forth below. For example, a power device may have a metal pattern with different thicknesses on the front side and another metal pattern with different thicknesses on the backside to enable lifetime control treatment to be performed from the both sides. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting.