SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device may include: a first conductive line; a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line; a variable resistance layer disposed over the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer; at least one of a first contact or a second contact; and at least one of a first doped selector layer or a second doped selector layer.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims the priority and benefits of Korean Patent Application No. 10-2021-0145463 filed on Oct. 28, 2021, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

The recent trend toward miniaturization, low power consumption, high performance, and multi-functionality in the electrical and electronics industry has compelled the semiconductor manufacturers to focus on high-performance, high capacity semiconductor devices. Examples of such high-performance, high capacity semiconductor devices include memory devices that can store data by switching between different resistance states according to an applied voltage or current. The semiconductor devices may include an RRAM (resistive random access memory), a PRAM (phase change random access memory), an FRAM (ferroelectric random access memory), an MRAM (magnetic random access memory), and an electronic fuse (E-fuse).

SUMMARY

The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device, in which an electronic device includes a semiconductor device which can improve a hard mask margin during a patterning process and prevent etch damage during patterning a selector layer.

In one aspect, a semiconductor device may include: a first conductive line; a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line; a variable resistance layer disposed over the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer, the first dielectric layer includes a first through-hole disposed between the first conductive line and the variable resistance layer and the second dielectric layer includes a second through-hole disposed between the variable resistance layer and the second conductive lines; at least one of a first contact or a second contact, wherein the first contact is structured to include a conductive material filled with the first through-hole and includes a first contact portion and a second contact portion spaced apart from each other, and the second contact is structured to include a conductive material filled with the second through-hole, and includes a third contact portion and a fourth contact portion spaced apart from each other, and at least one of a first doped selector layer or a second doped selector layer, wherein the first doped selector layer includes a first selection element portion interposed between the first contact portion and the second contact portion and a second selection element portion disposed in the first dielectric layer to be spaced apart from an upper surface of the first dielectric layer and a lower surface of the first dielectric layer, and the second doped selector layer includes a third selection element portion interposed between the third contact portion and the fourth contact portion and a fourth selection element portion disposed in the second dielectric layer to be spaced apart from an upper surface of the second dielectric layer and a lower surface of the second dielectric layer.

In another aspect, a method for fabricating a semiconductor device may include: forming a first conductive line over a substrate; forming a variable resistance layer over the first conductive line; forming a second conductive line over the variable resistance layer; forming a first dielectric layer including a through-hole between the first line and the variable resistance layer, between the variable resistance layer and the second conductive line, or both between the first line and the variable resistance layer and between the variable resistance layer and the second conductive line; forming a contact in the through-hole; performing a first ion implantation process to form a first sub dielectric layer within the contact and a second sub dielectric layer within the first dielectric layer such that the first sub dielectric layer is spaced apart from an upper surface and a lower surface of the contact and the second sub dielectric layer is spaced apart from an upper surface and a lower surface of the first dielectric layer by converting a portion of the contact into the first sub dielectric layer and a portion of the first dielectric layer into the second sub dielectric layer; and performing a second ion implantation of a dopant into the first sub dielectric layer and the second sub dielectric layer to form a doped selector layer, wherein the doped selector layer includes a first portion including the first sub dielectric layer and the dopant and a second portion including the second sub dielectric layer and the dopant.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

FIGS.1A and1Billustrate a semiconductor device based on some implementations of the disclosed technology.FIG.1Ais a plan view, andFIG.1Bis a cross-sectional view taken along line A-A′ ofFIG.1A.

Referring toFIGS.1A and1B, the semiconductor device may include a cross-point structure including a substrate100, first conductive lines110formed over the substrate100and extending in a first direction, second conductive lines130formed over the first conductive lines110to be spaced apart from the first conductive lines110and extending in a second direction crossing the first direction, and memory cells120disposed at intersections of the first conductive lines110and the second conductive lines130between the first conductive lines110and the second conductive lines130.

The substrate100may include a semiconductor material such as silicon. A required lower structure (not shown) may be formed in the substrate100. For example, the substrate100may include a driving circuit (not shown) electrically connected to the first conductive lines110and/or the second conductive lines130to control operations of the memory cells120. In this patent document, the conductive lines can indicate conductive structures that electrically connect two or more circuit elements in the semiconductor device. In some implementations, the conductive lines include word lines that are used control access to memory cells in the memory device and bit lines that are used to read out information stored in the memory cells. In some implementations, the conductive lines include interconnects that carry signals between different circuit elements in the semiconductor device.

The first conductive line110and the second conductive line130may be connected to a lower end and an upper end of the memory cell120, respectively, and may transmit a voltage or a current to the memory cell120to drive the memory cell120. When the first conductive line110functions as a word line, the second conductive line130may function as a bit line. Conversely, when the first conductive line110functions as a bit line, the second conductive line130may function as a word line. The first conductive line110and the second conductive line130may include a single-layer or multilayer structure including one or more of various conductive materials. Examples of the conductive materials may include a metal, a metal nitride, or a conductive carbon material, or a combination thereof, but are not limited thereto. For example, the first conductive line110and the second conductive line130may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN), or a combination thereof.

The memory cell120may be arranged in a matrix having rows and columns along the first direction and the second direction so as to overlap the intersection regions between the first conductive lines110and the second conductive lines130. In an implementation, each of the memory cells120may have a size that is substantially equal to or smaller than that of the intersection region between each corresponding pair of the first conductive lines110and the second conductive lines130. In another implementation, each of the memory cells120may have a size that is larger than that of the intersection region between each corresponding pair of the first conductive lines110and the second conductive lines130.

Spaces between the first conductive line110, the second conductive line130and the memory cell120may be filled with dielectric layers101,102-1,102-2,103,104-1and104-2. Each of the dielectric layers101,102-1,102-2,103,104-1and104-2may include a dielectric material. Examples of the dielectric material may include an oxide, a nitride, or a combination thereof. The dielectric layers101,102-1,102-2,103,104-1and104-2may include the same material as each other or different materials from each other.

The memory cell120may include a stacked structure including a first lower electrode contact121-1, a first blanket-doped selector layer122, a second lower electrode contact121-2, a variable resistance layer123, a first upper electrode contact124-1, a second blanket-doped selector layer125and a second upper electrode contact124-2. Each blanket-doped layer at a region is doped uniformly within that region without using any mask or pattern within that doped region during the doping.

The first lower electrode contact121-1may be interposed between the first conductive lines110and the first blanket-doped selector layer122. The first lower electrode contact121-1may be disposed at a lowermost portion of the memory cells120and function as a circuit node that carries a voltage or a current between a corresponding one of the first conductive lines110and the remaining portion of each of the memory cells120. The second upper electrode contact124-2may be disposed at an uppermost portion of the memory cell120and function as a transmission path of a voltage or a current between the rest of the memory cell120and a corresponding one of the second conductive lines130. In this patent document, the electrode contact may include contacts, contact plugs, or any other structures with a small gap that is filled with a conductive material such as metal.

The first and the second lower electrode contacts121-1and121-2, and the first and the second upper electrode contacts124-1and124-2may include a material that can be used to form a dielectric material layer by using oxygen, nitrogen, or a combination of oxygen and nitrogen through, e.g., an ion implantation process. For example, the first and the second lower electrode contacts121-1and121-2, and the first and the second upper electrode contacts124-1and124-2may include tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN) or a combination thereof.

The first and the second lower electrode contacts121-1and121-2, and the first and the second upper electrode contacts124-1and124-2may include the same material as each other, or different materials from each other.

The first and the second lower electrode contacts121-1and121-2may have the same thickness as each other, or different thicknesses from each other.

The first and the second upper electrode contacts124-1and124-2may have the same thickness as each other, or different thicknesses from each other.

At least one of the first and the second lower electrode contacts121-1and121-2, and the first and the second upper electrode contacts124-1and124-2may be omitted.

The variable resistance layer123may be used to store data using the different resistance states of the variable resistance layer123(e.g., using high and low resistance states to represent digital level “1” and “0”) by setting the variable resistance layer123into a desired resistance state, and to change a stored data bit by switching between different resistance states, according to an applied voltage or current. The variable resistance layer123may have a single-layered structure or a multi-layered structure including at least one of materials used for an RRAM, a PRAM, an MRAM, an FRAM, and others. For example, the variable resistance layer123may include a metal oxide such as a transition metal oxide or a perovskite-based oxide, a phase change material such as a chalcogenide-based material, a ferromagnetic material, a ferroelectric material, or others. However, the implementations are not limited thereto, and the memory cell120may include other memory layers capable of storing data in various ways instead of the variable resistance layer123.

In some implementations, the variable resistance layer123may include a magnetic tunnel junction (MTJ) structure. This will be explained with reference toFIG.1C.

FIG.1Cillustrates an example of Magnetic Tunnel Junction (MTJ) structure included in the variable resistance layer123.

The variable resistance layer123may include an MTJ structure including a free layer13having a variable magnetization direction, a pinned layer15having a pinned magnetization direction and a tunnel barrier layer14interposed between the free layer13and the pinned layer15.

The free layer13may have one of different magnetization directions or one of different spin directions of electrons to switch the polarity of the free layer13in the MTJ structure, resulting in changes in resistance value. In some implementations, the polarity of the free layer13is changed or flipped upon application of a voltage or current signal (e.g., a driving current above a certain threshold) to the MTJ structure. With the polarity changes of the free layer13, the free layer13and the pinned layer15have different magnetization directions or different spin directions of electron, which allows the variable resistance layer123to store different data or represent different data bits. The free layer13may also be referred as a storage layer. The magnetization direction of the free layer13may be substantially perpendicular to a surface of the free layer13, the tunnel barrier layer14and the pinned layer15. In other words, the magnetization direction of the free layer13may be substantially parallel to stacking directions of the free layer13, the tunnel barrier layer14and the pinned layer15. Therefore, the magnetization direction of the free layer13may be changed between a downward direction and an upward direction. The change in the magnetization direction of the free layer13may be induced by a spin transfer torque generated by an applied current or voltage.

The free layer13may have a single-layer or multilayer structure including a ferromagnetic material. For example, the free layer13may include an alloy based on Fe, Ni or Co, for example, an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, a Co—Fe alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, or a Co—Fe—B alloy, or others, or may include a stack of metals, such as Co/Pt, or Co/Pd, or others.

The tunnel barrier layer14may allow the tunneling of electrons in both data reading and data writing operations. In a write operation for storing new data, a high write current may be directed through the tunnel barrier layer14to change the magnetization direction of the free layer13and thus to change the resistance state of the MTJ for writing a new data bit. In a reading operation, a low reading current may be directed through the tunnel barrier layer14without changing the magnetization direction of the free layer13to measure the existing resistance state of the MTJ under the existing magnetization direction of the free layer13to read the stored data bit in the MTJ. The tunnel barrier layer14may include a dielectric oxide such as MgO, CaO, SrO, TiO, VO, or NbO or others.

The pinned layer15may have a pinned magnetization direction, which remains unchanged while the magnetization direction of the free layer13changes. The pinned layer15may be referred to as a reference layer. In some implementations, the magnetization direction of the pinned layer15may be pinned in a downward direction. In some implementations, the magnetization direction of the pinned layer15may be pinned in an upward direction.

The pinned layer15may have a single-layer or multilayer structure including a ferromagnetic material. For example, the pinned layer15may include an alloy based on Fe, Ni or Co, for example, an Fe—Pt alloy, an Fe—Pd alloy, a Co—Pd alloy, a Co—Pt alloy, a Co—Fe alloy, an Fe—Ni—Pt alloy, a Co—Fe—Pt alloy, a Co—Ni—Pt alloy, or a Co—Fe—B alloy, or may include a stack of metals, such as Co/Pt, or Co/Pd or others.

If a voltage or current is applied to the variable resistance layer123, the magnetization direction of the free layer13may be changed by spin torque transfer. In some implementations, when the magnetization directions of the free layer13and the pinned layer15are parallel to each other, the variable resistance layer123may be in a low resistance state, and this may indicate digital data bit “0.” Conversely, when the magnetization directions of the free layer13and the pinned layer15are anti-parallel to each other, the variable resistance layer123may be in a high resistance state, and this may indicate a digital data bit “1.” In some implementations, the variable resistance layer123can be configured to store data bit ‘1’ when the magnetization directions of the free layer13and the pinned layer15are parallel to each other and to store data bit ‘0’ when the magnetization directions of the free layer13and the pinned layer15are anti-parallel to each other.

In some implementations, the variable resistance layer123may further include one or more layers performing various functions to improve a characteristic of the MTJ structure. For example, the variable resistance layer123may further include at least one of a buffer layer11, an under layer12, a spacer layer16, a magnetic correction layer17and a capping layer18.

The under layer12may be disposed under the free layer13and may be used to improve perpendicular magnetic crystalline anisotropy of the free layer13. The under layer12may have a single-layer or multilayer structure including a metal, a metal alloy, a metal nitride, or a metal oxide, or a combination thereof.

The buffer layer11may be disposed below the under layer12to facilitate crystal growth of the under layer12, thus improving perpendicular magnetic crystalline anisotropy of the free layer13. The buffer layer11may have a single-layer or multilayer structure including a metal, a metal alloy, a metal nitride, or a metal oxide, or a combination thereof. Moreover, the buffer layer11may be formed of or include a material having a good compatibility with a bottom electrode (not shown) in order to resolve the lattice constant mismatch between the bottom electrode and the under layer12. For example, the buffer layer11may include tantalum (Ta).

The spacer layer16may be interposed between the magnetic correction layer17and the pinned layer15and function as a buffer between the magnetic correction layer17and the pinned layer15. The spacer layer16may be used to improve characteristics of the magnetic correction layer17. The spacer layer16may include a noble metal such as ruthenium (Ru).

The magnetic correction layer17may be used to offset the effect of the stray magnetic field produced by the pinned layer15. In this case, the effect of the stray magnetic field of the pinned layer15can decrease, and thus a biased magnetic field in the free layer13can decrease. The magnetic correction layer17may have a magnetization direction anti-parallel to the magnetization direction of the pinned layer15. In the implementation, when the pinned layer15has a downward magnetization direction, the magnetic correction layer17may have an upward magnetization direction. Conversely, when the pinned layer15has an upward magnetization direction, the magnetic correction layer17may have a downward magnetization direction. The magnetic correction layer17may be exchange coupled with the pinned layer15via the spacer layer16to form a synthetic anti-ferromagnet (SAF) structure. The magnetic correction layer17may have a single-layer or multilayer structure including a ferromagnetic material.

In this implementation, the magnetic correction layer17is located above the pinned layer15, but the magnetic correction layer17may disposed at a different location. For example, the magnetic correction layer17may be located above, below, or next to the MTJ structure while the magnetic correction layer17is patterned separately from the MTJ structure.

The capping layer18may be used to protect the variable resistance layer123and/or function as a hard mask for patterning the variable resistance layer123. In some implementations, the capping layer18may include various conductive materials such as a metal. In some implementations, the capping layer18may include a metallic material having almost none or a small number of pin holes and high resistance to wet and/or dry etching. In some implementations, the capping layer18may include a metal, a nitride, or an oxide, or a combination thereof. For example, the capping layer18may include a noble metal such as ruthenium (Ru).

The capping layer18may have a single-layer or multilayer structure. In some implementations, the capping layer18may have a multilayer structure including an oxide, or a metal, or a combination thereof. For example, the capping layer18may have a multilayer structure of an oxide layer, a first metal layer and a second metal layer.

A material layer (not shown) for resolving the lattice structure differences and the lattice constant mismatch between the pinned layer15and the magnetic correction layer17may be interposed between the pinned layer15and the magnetic correction layer17. For example, this material layer may be amorphous and may include a metal a metal nitride, or metal oxide.

The first and the second blanket-doped selector layers122and125may be used to control access to the variable resistance layer123. To this end, the first and the second blanket-doped selector layers122and125may have a characteristic for adjusting the flow of a current according to the magnitude of the applied a voltage or a current, that is, for blocking or substantially limiting a current flowing through the memory cell120when a magnitude of an applied voltage is less than a predetermined threshold value and for allowing a current flowing through the memory cell120to abruptly increase when the magnitude of the applied voltage is equal to or greater than the threshold value. The first and the second blanket-doped selector layers122and125may include a Metal Insulator Transition (MIT) material such as NbO2, TiO2, VO2, WO2, or others, a Mixed Ion-Electron Conducting (MIEC) material such as ZrO2(Y2O3), Bi2O3—BaO, (La2O3)x(CeO2)1-x, or others, an Ovonic Threshold Switching (OTS) material including chalcogenide material such as Ge2Sb2Te5, As2Te3, As2, As2Se3, or others, or a tunneling insulating material such as silicon oxide, silicon nitride, a metal oxide, or others. A thickness of the tunneling insulating layer is sufficiently small to allow tunneling of electrons under a given voltage or a given current. The first and the second blanket-doped selector layers122and125may include a single-layer or multilayer structure.

In one implementation, the first and the second blanket-doped selector layers122and125may be configured to perform a threshold switching operation. In this patent document, the term “threshold switching operation” can be used to indicate turning on or off the first and the second blanket-doped selector layers122and125while an external voltage is applied to the first and the second blanket-doped selector layers122and125at a voltage value with respect to a threshold voltage. The absolute value of the external voltage may be controlled to gradually increase or decrease. When the absolute value of the external voltage applied to the first and the second blanket-doped selector layers122and125increases, the first and the second blanket-doped selector layers122and125may be turned on to be electrically conductive, when the absolute value of the external voltage is greater than a first threshold voltage, once turned on, the increase of this external voltage causes an operation current to increase nonlinearly. When the absolute value of the external voltage applied to the first and the second blanket-doped selector layers122and125decreases after the first and the second blanket-doped selector layers122and125are turned on, the operation current flowing through or between the first and the second blanket-doped selector layers122and125decreases nonlinearly until the applied voltage value reaches a second threshold voltage below which the first and the second blanket-doped selector layers122and125may be turned off (i.e., electrically non-conductive). As such, the first and the second blanket-doped selector layers122and125performing the threshold switching operation may have a non-memory operation characteristic.

In some implementations, the first and the second blanket-doped selector layers122and125may include a dielectric material having incorporated dopants. The first and the second blanket-doped selector layers122and125may include an oxide with dopants, a nitride with dopants, or an oxynitride with dopants, or a combination thereof such as silicon oxide, tungsten oxide, titanium oxide, vanadium oxide, chromium oxide, platinum oxide, aluminum oxide, copper oxide, zinc oxide, nickel oxide, cobalt oxide, lead oxide, manganese oxide, niobium oxide, hafnium oxide, silicon nitride, tungsten nitride, titanium nitride, vanadium nitride, chromium nitride, platinum nitride, aluminum nitride, copper nitride, zinc nitride, nickel nitride, cobalt nitride, lead nitride, manganese nitride, niobium nitride, hafnium nitride, silicon oxynitride, tungsten oxynitride, titanium oxynitride, vanadium oxynitride, chromium oxynitride, Platinum oxynitride, aluminum oxynitride, copper oxynitride, zinc oxynitride, nickel oxynitride, cobalt oxynitride, lead oxynitride, manganese oxynitride, niobium oxynitride, or hafnium oxynitride, or a combination thereof. The dopants doped into the first and the second blanket-doped selector layers122and125may include an n-type dopant or a p-type dopant and be combined or incorporated, for example, by an ion implantation process. Examples of the dopants may include one or more of boron (B), nitrogen (N), carbon (C), phosphorous (P), arsenic (As), aluminum (Al), silicon (Si) and germanium (Ge).

Conventionally, a doped selector may be formed by depositing a dielectric layer as a matrix for the selector, combining or incorporating a dopant into the dielectric layer by an ion implantation process and patterning the doped dielectric layer. In this case, the separate dielectric layer should be formed for forming the selector, thereby increasing the overall height of the memory, which may cause insufficient hard mask margin during the subsequent patterning process. As a result, etch damage to the doped selector may occur during the patterning process.

In order to overcome such problems, in implementations of the disclosed technology, the first and the second blanket-doped selector layers122and125including a doped dielectric material may be formed by introducing oxygen and/or nitrogen into a part of a lower electrode contact and/or a part of an upper electrode contact to convert the part of the lower electrode contact and/or the part of the upper electrode contact into dielectric layers, instead of forming a separate dielectric layer for the first and the second blanket-doped selector layers122and125, and then introducing or implanting a dopant into the dielectric layers by e.g., an ion implantation process.

The first and the second blanket-doped selector layers122and125may include the dielectric material and the dopant.

The first blanket-doped selector layer122may include a first portion122-1and a second portion122-2. The first portion122-1may be disposed between the first lower electrode contact121-1and the second lower electrode contact121-2, and the second portion122-2may be disposed between the dielectric layer102-1and the dielectric layer102-2.

In some implementations, the first portion122-1and the second portion122-2may have different dielectric materials from each other.

The second blanket-doped selector layer125may include a first portion125-1and a second portion125-2. The first portion125-1may be disposed between the first upper electrode contact124-1and the second upper electrode contact124-2, and the second portion125-2may be disposed between the dielectric layer104-1and the dielectric layer104-2.

In some implementations, the first portion125-1and the second portion125-2may have different dielectric materials from each other.

In some implementations, the first portion122-1of the first blanket-doped selector layer122and the first portion125-1of the second blanket-doped selector layer125may include the same dielectric material and dopant as each other.

In some implementations, the second portion122-2of the first blanket-doped selector layer122and the second portion125-2of the second blanket-doped selector layer125may include the same dielectric material and dopant as each other.

A distance from a lower surface of the first lower electrode contact121-1to a lower surface of the first portion122-1may be the same as or different from a distance from an upper surface of the second lower electrode contact121-2to an upper surface of the first portion122-1. A distance from a lower surface of the dielectric layer102-1to the lower surface of the second portion122-2may be the same as or different from a distance from an upper surface of the dielectric layer102-2to the upper surface of the second portion122-2.

A distance from a lower surface of the first upper electrode contact124-1to a lower surface of the first portion125-1may be the same as or different from a distance from an upper surface of the second upper electrode contact125-2to an upper surface of the second portion125-2. A distance from a lower surface of the dielectric layer104-1to the lower surface of the first portion125-1may be the same as or different from a distance from an upper surface of the dielectric layer104-2to the upper surface of the second portion125-2.

In some implementations, a separate dielectric layer for forming the first and the second blanket-doped selector layers122and125is not formed. Thus, the overall height of the memory cell120is not increased, thereby improving a hard mask margin and preventing etch damage during a patterning process of the first and the second blanket-doped selector layers122and125.

Forming the first and the second blanket-doped selector layers122and125will be described in detail with reference toFIGS.2A to2G,FIGS.3A to3D, andFIGS.4A to4D.

In some implementations, the first and the second blanket-doped selector layers122and125may perform a threshold switching operation through a doped region formed in a material layer for the first and the second blanket-doped selector layers122and125. Thus, a size of the threshold switching operation region may be controlled by a distribution area of the dopants. The dopants may form trap sites for charge carriers in the material layer for the first and the second blanket-doped selector layers122and125. The trap sites may capture the charge carriers moving in the first and the second blanket-doped selector layers122and125, based on an external voltage applied to the first and the second blanket-doped selector layers122and125. The trap sites thereby provide a threshold switching characteristic and are used to perform a threshold switching operation.

In some implementations, each of the memory cell120may include the first lower electrode contact121-1, the first blanket-doped selector layer122, the second lower electrode contact121-2, the variable resistance layer123, the first upper electrode contact124-1, the second blanket-doped selector layer125and the second upper electrode contact124-2which are sequentially stacked. However, the memory cells120may have different structures. In some implementations, at least one of the first blanket-doped selector layer122or the second blanket-doped selector layer125may be omitted. In some implementations, in addition to the layers121to125shown inFIG.1B, the memory cells120may further include one or more layers (not shown) for enhancing characteristics of the memory cells120or improving fabricating processes.

In some implementations, neighboring memory cells of the plurality of memory cells120may be spaced apart from each other at a predetermined interval, and trenches may be present between the plurality of memory cells120. A trench between neighboring memory cells120may have a height to width ratio (e.g., an aspect ratio) in a range from 1:1 to 40:1, from 10:1 to 40:1, from 10:1 to 20:1, from 5:1 to 10:1, from 10:1 to 15:1, from 1:1 to 25:1, from 1:1 to 30:1, from 1:1 to 35:1, or from 1:1 to 45:1.

In some implementations, the trench may have sidewalls that are substantially perpendicular to an upper surface of the substrate100. In some implementations, neighboring trenches may be spaced apart from each other by an equal or similar distance.

In some implementations, the semiconductor device may include further layers in addition to the first conductive line110, the memory cell120and the second conductive line130.

Although one cross-point structure has been described, two or more cross-point structures may be stacked in a vertical direction perpendicular to a top surface of the substrate100.

A method for fabricating a semiconductor device will be explained with reference toFIGS.2A to2G.

Referring toFIG.2A, first conductive lines210may be formed over a substrate200in which a predetermined structure is formed. The first conductive lines210may be formed by forming a first interlayer dielectric layer201having a trench for forming the first conductive lines210over the substrate200, forming a conductive layer for the first conductive lines210, and etching the conductive layer using a mask pattern in a line shape extending in a first direction.

A lower electrode contact221may be formed over the first conductive lines210. The lower electrode layer221may be formed by forming a second interlayer dielectric layer202having a hole over the structure in which the first conductive lines210are formed, forming a material layer for the lower electrode layer221in the hole, and performing a planarization process such as a chemical mechanical planarization (CMP).

The lower electrode contact221may include a material capable of forming a dielectric material by combining or incorporating oxygen, nitrogen, or a combination of oxygen and nitrogen through, e.g., an ion implantation process. For example, the lower electrode contact221may include tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or a combination thereof.

Referring toFIG.2B, a first ion implantation process may be performed on a portion of the lower electrode contact221and a portion of the second interlayer dielectric layer202to incorporate oxygen, nitrogen, or a combination thereof into the portion of the lower electrode contact221and the portion of the second interlayer dielectric layer202. The portion of the lower electrode contact221may be a portion spaced apart from an upper surface and a lower surface of the lower electrode contact221. Similarly, the portion of the second interlayer dielectric layer202may be a portion spaced apart from an upper surface and a lower surface of the second interlayer dielectric layer202. That is, the first ion implantation process may be performed by targeting the position spaced apart from the upper surface and the lower surface of the lower electrode contact221and the position spaced apart from the upper surface and the lower surface of the second interlayer dielectric layer202so as to incorporate oxygen, nitrogen, or a combination thereof into a given part of the lower electrode contact221and a given part of the second interlayer dielectric layer202in a direction perpendicular to the surfaces of the layers. The first ion implantation process may be a process to convert the portions of the lower electrode contact221and the second interlayer dielectric layer202into dielectric layers by oxidizing, nitriding, or oxynitriding. Since the second interlayer dielectric layer202is originally formed of a dielectric material, it may maintain dielectric characteristics even after oxygen and/or nitrogen is introduced by the first ion implantation process.

In the first ion implantation process, a projection range (Rp) may be adjusted in consideration of a position and a thickness of a first blanket-doped selector layer (see, reference numeral222ofFIG.2C) formed in a subsequent process.

By the first ion implantation process, a first material layer222A may be formed in the lower electrode contact221, and a second material layer222B may be formed in the second interlayer dielectric layer202. The lower electrode contact221below the first material layer222A and the lower electrode contact221over the first material layer222A may be referred to as a first lower electrode contact221-1and a second lower electrode contact221-2, respectively. The first lower electrode contact221-1and the second lower electrode contact221-2may have the same thickness as each other, or different thicknesses from each other. The second interlayer dielectric layer202below the second material layer222B and the second interlayer dielectric layer202over the second material layer222B may be referred to as a first portion202-1of the second interlayer dielectric layer202and a second portion202-2of the second interlayer dielectric layer202, respectively. The first portion202-1and the second portion202-2may have the same thickness as each other, or different thicknesses from each other.

Each of the first material layer222A and the second material layer2228may include a dielectric material. In some implementations, the first material layer222A and the second material layer2228may include different dielectric materials from each other.

Referring toFIG.2C, the first blanket-doped selector layer222may be formed by incorporating a dopant through performing a second ion implantation process on the first material layer222A and the second material layer2228.

The first blanket-doped selector layer222may include a first portion222-1interposed between the first lower electrode contact221-1and the second lower electrode contact221-2, and a second portion222-2interposed between the first portion202-1and the second portion202-2of the second interlayer dielectric layer202. That is, the first blanket-doped selector layer222may be interposed in a form of a blanket-doped between the first lower electrode contact221-1and the second lower electrode contact221-2, and between the first portion202-1and the second portion202-2of the second interlayer dielectric layer202

The dopant doped by the second ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorous (P), arsenic (As), aluminum (Al), silicon (Si) and germanium (Ge).

The first blanket-doped selector layer222may be interposed in a form of a blanket-doped between the first portion202-1and the second portion202-2of the second interlayer dielectric layer202, and between the first lower electrode contact221-1and the second lower electrode contact221-2.

Referring toFIG.2D, a variable resistance layer223and an upper electrode contact224may be formed over the second lower electrode contact221-2.

The variable resistance layer223may be formed by forming material layers for the variable resistance layer223on the structure ofFIG.2Cand patterning the material layers. Then, a third interlayer dielectric layer203may be formed.

The upper electrode contact224may be formed by forming a fourth interlayer dielectric layer204having a hole over the variable resistance layer223and the third interlayer dielectric layer203, forming a material layer for the upper electrode contact224in the hole and performing a planarization process such as a chemical mechanical planarization (CMP).

The upper electrode contact224may include a material capable of forming a dielectric material by incorporating oxygen, nitrogen, or a combination thereof through e.g., an ion implantation process. For example, the upper electrode contact224may include tungsten (W), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), platinum (Pt), aluminum (Al), copper (Cu), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), manganese (Mn), niobium (Nb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or tantalum aluminum nitride (TaAlN), or a combination thereof.

Referring toFIG.2E, a third ion implantation process may be performed on a portion of the upper electrode contact24and a portion of the fourth interlayer dielectric layer204to incorporate oxygen, nitrogen, or a combination thereof into the portion of the upper electrode contact224and the portion of the fourth interlayer dielectric layer204. The portion of the upper electrode contact224may be a portion spaced apart from an upper surface and a lower surface of the upper electrode contact224. Similarly, the portion of the fourth interlayer dielectric layer204may be a portion spaced apart from an upper surface and a lower surface of the fourth interlayer dielectric layer204. That is, the third ion implantation process may be performed by targeting the position spaced apart from the upper surface and the lower surface of the upper electrode contact224and the position spaced apart from the upper surface and the lower surface of the fourth interlayer dielectric layer204so as to incorporate oxygen, nitrogen, or a combination thereof into a given part of the lower electrode contact221and a given part of the fourth interlayer dielectric layer204in a direction perpendicular to the surfaces of the layers. The third ion implantation process may be a process to convert the portions of the upper electrode contact224and the fourth interlayer dielectric layer204into dielectric layers by oxidizing, nitriding, or oxynitriding. Since the fourth interlayer dielectric layer204is originally formed of a dielectric material, it may maintain dielectric characteristics even after oxygen and/or nitrogen is introduced by the third ion implantation process.

In the third ion implantation process, a projection range (Rp) may be adjusted in consideration of a position and a thickness of a second blanket-doped selector layer (e.g.,225ofFIG.2F).

By the third ion implantation process, a first material layer225A may be formed in the upper electrode contact224, and a second material layer225B may be formed in the fourth interlayer dielectric layer204. The upper electrode contact224below the first material layer225A and the upper electrode contact224over the first material layer225A may be referred to as a first upper electrode contact224-1and a second upper electrode contact224-2, respectively. The first upper electrode contact224-1and the second upper electrode contact224-2may have the same thickness as each other, or different thicknesses from each other. The fourth interlayer dielectric layer204below the second material layer225B and the fourth interlayer dielectric layer204over the second material layer225B may be referred to as a first portion204-1of the fourth interlayer dielectric layer204and a second portion204-2of the fourth interlayer dielectric layer204. The first portion204-1and the second portion204-2may have the same thickness as each other, or different thicknesses from each other.

Each of the first material layer225A and the second material layer225B may include a dielectric material. In some implementations, the first material layer225A and the second material layer225B may include different dielectric materials from each other.

Referring toFIG.2F, the second blanket-doped selector layer225may be formed by incorporating a dopant through performing a fourth ion implantation process on the first material layer225A and the second material layer225B.

The second blanket-doped selector layer225may include a first portion225-1interposed between the first upper electrode contact224-1and the second upper electrode contact224-2, and a second portion225-2interposed between the first position204-1and the second portion204-2of the fourth interlayer dielectric layer204.

The dopant doped by the fourth ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorous (P), arsenic (As), aluminum (Al), silicon (Si) and germanium (Ge).

The second blanket-doped selector layer225may be interposed in a form of a blanket-doped between the first portion204-1and the second portion204-2, and between the first upper electrode contact224-1and the second upper electrode contact224-2.

In some implementations, the first portion225-1of the second blanket-doped selector layer225, and the first portion222-1of the first blanket-doped selector layer222may be formed of the same material as each other. In some implementations, the second portion225-2of the second blanket-doped selector layer225, and the second portion222-2of the first blanket-doped selector layer222may be formed of the same material as each other. In this case, since the first blanket-doped selector layer222and the second blanket-doped selector layer225may have the same operation characteristic as each other, device operation conditions may be the same as each other.

Referring toFIG.2G, second conductive lines230may be formed over the second upper electrode contact224-2and the second portion204-2of the fourth interlayer dielectric layer204.

The second conductive lines230may be formed by forming a conductive layer for the second conductive lines230over the second upper electrode contact224-2and the second portion204-2and etching the conductive layer by using a mask pattern in a line shape extending in a second direction.

Through the processes as described above, the semiconductor device including the first conductive lines210, the memory cell220and the second conductive lines230may be formed. The memory cell220may include the first lower electrode contact221-1, the first blanket-doped selector layer222, the second lower electrode contact221-2, the variable resistance layer223, the first upper electrode contact224-1the second blanket-doped selector layer225and the second upper electrode contact224-2which are sequentially stacked.

The memory cell220may include the first blanket-doped selector layer222and the second blanket-doped selector layer225. In some implementations, the first blanket-doped selector layer222and the second blanket-doped selector layer225may be formed of the same material as each other so as to have the same operation characteristic and device operation conditions. In case of having two blanket-doped selector layers222and225, even if any one of the blanket-doped selector layers222and225is not operated, a bit cell operation at the corresponding address may be preserved.

According to the semiconductor device described above, the first and the second blanket-doped selector layers222and225may be formed by converting the portion of the lower electrode contact221and the portion of the upper electrode contact224into dielectric layers instead of forming an additional dielectric layer for the first and the second blanket-doped selector layers222and225, and then introducing the dopant into the portions. Therefore, a height of the memory cell220may not be increased, thereby improving a hard mask margin and preventing etch damage during a patterning process of the first and the second blanket-doped selector layers222and225.

The substrate200, the first conductive lines210, the first lower electrode contact221-1, the first blanket-doped selector layer222, the second lower electrode contact221-2, the variable resistance layer223, the first upper electrode contact224-1, the second blanket-doped selector layer225, the second upper electrode contact224-2and the second conductive lines230shown inFIG.2Gmay correspond to the substrate100, the first conductive lines110, the first lower electrode contact121-1, the first blanket-doped selector layer122, the second lower electrode contact121-2, the variable resistance layer123, the first upper electrode contact124-1, the second blanket-doped selector layer125, the second upper electrode contact124-2and the second conductive lines130.

In some implementations, the semiconductor device may include a first conductive line structured to electrically connect two or more circuit elements in the semiconductor device, a second conductive line structured to electrically connect two or more circuit elements in the semiconductor device and disposed over the first conductive line to be spaced apart from the first conductive line, a variable resistance layer disposed over the first conductive line and below the second conductive line, at least one of a first dielectric layer including a first through-hole disposed between the first conductive line and the variable resistance layer and a second dielectric layer including a second through-hole disposed between the variable resistance layer and the second conductive lines, at least one of a first contact structured to include a conductive material filled with the first through-hole and a second contact structured to include a conductive material filled with the second through-hole, the first contact including a first contact portion and a second contact portion spaced apart from each other and the second contact including a third contact portion and a fourth contact portion spaced apart from each other, and at least one of a first blanket-doped selector layer and a second blanket-doped selector layer. The first blanket-doped selector layer may include a first selection element portion interposed between the first contact portion and the second contact portion and a second selection element portion disposed in the first dielectric layer to be spaced apart from an upper surface of the first dielectric layer and a lower surface of the first dielectric layer, and the second blanket-doped selector layer may include a third selection element portion interposed between the third contact portion and the fourth contact portion and a fourth selection element portion disposed in the second dielectric layer to be spaced apart from an upper surface of the second dielectric layer and a lower surface of the second dielectric layer. Here, the first dielectric layer may include the second interlayer dielectric layer202, and the second dielectric layer may include the fourth interlayer dielectric layer204.

The semiconductor device described above may include both the first blanket-doped selector layer222and the second blanket-doped selector layer225. However, the semiconductor device may include any one of the first blanket-doped selector layer222and the second blanket-doped selector layer225. This will be described in detail with reference toFIGS.3A to3DandFIGS.4A to3D.

FIGS.3A to3Dare cross-sectional views illustrating another example method for fabricating a semiconductor device based on some implementations of the disclosed technology.

The semiconductor device illustrated inFIGS.3A to3Dis similar to the semiconductor device illustrated inFIGS.2A to2Gexcept for including only one blanket-doped selector layer (see, reference numeral322ofFIG.3C). The implementations illustrated inFIGS.3A to3Dwill be described focusing on differences from the above-described implementations illustrated inFIGS.2A to2G.

Referring toFIG.3A, first conductive lines310, a first interlayer dielectric layer301, a lower electrode contact321and a second interlayer dielectric layer302may be formed over a substrate300in which a predetermined structure is formed.

Referring toFIG.3B, a first ion implantation process may be performed on a portion spaced apart from an upper surface and a lower surface of the lower electrode contact321and a portion spaced apart from an upper surface and a lower surface of the second interlayer dielectric layer302to incorporate oxygen, nitrogen, or a combination thereof into the portion of the lower electrode contact321and the portion of the second interlayer dielectric layer302. The first ion implantation process may be a process to convert the portions of the lower electrode contact321and the second interlayer dielectric layer302into dielectric layers by oxidizing, nitriding, or oxynitriding. Since the second interlayer dielectric layer302is originally formed of a dielectric material, it may maintain dielectric characteristics even after oxygen and/or nitrogen is introduced by the first ion implantation process.

In the first ion implantation process, a projection range (Rp) may be adjusted in consideration of a position and a thickness of a blanket-doped selector layer (see, reference numeral322ofFIG.3C) formed in a subsequent process.

By the first ion implantation process, a first material layer322A may be formed in the lower electrode contact321, and a second material layer322B may be formed in the second interlayer dielectric layer302. The first material layer322A and the second material layer322B may include a dielectric material. In some implementations, the first material layer322A and the second material layer322B may include different dielectric materials from each other. The lower electrode contact321below the first material layer322A and the lower electrode contact321over the first material layer322A may be referred to as a first lower electrode contact321-1and a second lower electrode contact321-2, respectively. The first lower electrode contact321-1and the second lower electrode contact321-2may have the same thickness as each other, or different thicknesses from each other. The second interlayer dielectric layer302below the second material layer322B and the second interlayer dielectric layer302over the second material layer322B may be referred to as a first portion302-1of the second interlayer dielectric layer302and a second portion302-2of the second interlayer dielectric layer302, respectively. The first portion302-1and the second portion302-2may have the same thickness as each other, or different thicknesses from each other.

Referring toFIG.3C, the blanket-doped selector layer322may be formed by incorporating a dopant through performing a second ion implantation process on the first material layer322A and the second material layer322B through performing a second ion implantation process.

The blanket-doped selector layer322may include a first portion322-1interposed between the first lower electrode contact321-1and the second lower electrode contact321-2, and a second portion322-2interposed between the first portion302-1and the second portion302-2of the second interlayer dielectric layer302. That is, the blanket-doped selector layer322may be interposed in a form of a blanket-doped between the first lower electrode contact321-1and the second lower electrode contact321-2, and between the first portion302-1and the second portion302-2of the second interlayer dielectric layer302

Referring toFIG.3D, a variable resistance layer323may be formed over the second lower electrode contact321-2. The variable resistance layer323may be formed by forming material layers for the variable resistance layer323on the structure ofFIG.3Cand patterning the material layers. Consequently, a memory cell320including the first lower contact321-1, the blanket-doped selector layer322, the second lower contact321-2and the variable resistance layer323may be formed. Then, a third interlayer dielectric layer303may be formed.

Then, second conductive lines330may be formed over the variable resistance layer323and the third interlayer dielectric layer303.

The second conductive lines330may be formed by forming a conductive layer for the second conductive lines230over the variable resistance layer323and the third interlayer dielectric layer303and etching the conductive layer by using a mask pattern in a line shape extending in a second direction.

Through the processes as described above, the semiconductor device including the first conductive lines310, the memory cell320and the second conductive lines330may be formed. The memory cell320may include the first lower electrode contact321-1, the blanket-doped selector layer322, the second lower electrode contact321-2and the variable resistance layer323which are sequentially stacked.

The substrate300, the first conductive lines310, the first lower electrode contact321-1, the blanket-doped selector layer322, the second lower electrode contact321-2, the variable resistance layer323and the second conductive lines330shown inFIG.3Dmay correspond to the substrate100, the first conductive lines110, the first lower electrode contact121-1, the first blanket-doped selector layer122, the second lower electrode contact121-2, the variable resistance layer123and the second conductive lines130shown inFIG.1B, respectively, and the substrate200, the first conductive lines210, the first lower electrode contact221-1, the blanket-doped selector layer222, the second lower electrode contact221-2, the variable resistance layer223and the second conductive lines230shown inFIG.2G, respectively.

FIGS.4A to4Dare cross-sectional views illustrating further another example method for fabricating a semiconductor device based on some implementations of the disclosed technology.

The semiconductor device illustrated inFIGS.4A to4Dis similar to the semiconductor device illustrated inFIGS.2A to2Gexcept for including only one blanket-doped selector layer (see, reference numeral425ofFIG.4C). The implementations illustrated inFIGS.4A to4Dwill be described focusing on differences from the above-described implementations illustrated inFIGS.2A to2G.

Referring toFIG.4A, first conductive lines410, a first interlayer dielectric layer401, a variable resistance layer423, a second interlayer dielectric layer403, an upper electrode contact424and a third interlayer dielectric layer404may be formed over a substrate400in which a predetermined structure is formed.

Referring toFIG.4B, a first ion implantation process may be performed on a portion spaced apart from an upper surface and a lower surface of the upper electrode contact424and a portion spaced apart from an upper surface and a lower surface of the third interlayer dielectric layer404to incorporate oxygen, nitrogen, or a combination thereof into the portion of the upper electrode contact424and the portion of the third interlayer dielectric layer404. The first ion implantation process may be a process to convert the portions of the upper electrode contact424and the third interlayer dielectric layer404into dielectric layers by oxidizing, nitriding, or oxynitriding. Since the third interlayer dielectric layer404is originally formed of a dielectric material, it may maintain dielectric characteristics even after oxygen and/or nitrogen is introduced by the first ion implantation process.

In the first ion implantation process, a projection range (Rp) may be adjusted in consideration of a position and a thickness of a first blanket-doped selector layer (see, reference numeral425ofFIG.4C) formed in a subsequent process.

By the first ion implantation process, a first material layer425A may be formed in the upper electrode contact424and a second material layer425B may be formed in the third interlayer dielectric layer404. The upper electrode contact424below the first material layer425A and the upper electrode contact424over the upper electrode contact424may be referred to as a first upper electrode contact424-1and a second upper electrode contact424-2, respectively. The third interlayer dielectric layer404below the second material layer425B and the third interlayer dielectric layer404over the second material layer425B may be referred to as a first portion404-1of the third interlayer dielectric layer404and a second portion404-2of the third interlayer dielectric layer404, respectively. The first material layer425A and the second material layer425B may include a dielectric material. In some implementations, the first material layer425A and the second material layer425B may include different dielectric materials from each other.

Referring toFIG.4C, the blanket-doped selector layer425may be formed by incorporating a dopant through performing a second ion implantation process on the first material layer425A and the second material layer425B through performing a second ion implantation process.

The blanket-doped selector layer425may include a first portion425-1interposed between the first upper electrode contact424-1and the second upper electrode contact424-2and a second portion425-2interposed between the first portion404-1and the second portion404-2of the third interlayer dielectric layer404. That is, the blanket-doped selector layer425may be interposed in a form of a blanket-doped between the first upper electrode contact424-1and the second upper electrode contact424-2, and between the first portion404-1and the second portion404-2of the third interlayer dielectric layer404.

Consequently, a memory cell420including the variable resistance layer423, the first upper contact424-1, the blanket-doped selector layer422and the second upper contact424-2may be formed.

Referring toFIG.4D, second conductive lines330may be formed over the second upper electrode contact424-2and the second portion404-2of the third interlayer dielectric layer404.

Through the processes as described above, the semiconductor device including the first conductive lines410, the memory cell420and the second conductive lines430may be formed. The memory cell420may include the variable resistance layer423, the first upper contact424-1, the blanket-doped selector layer422and the second upper contact424-2which are sequentially stacked.

The substrate400, the first conductive lines410, the variable resistance layer423, the first upper electrode contact424-1, the blanket-doped selector layer425, the second upper electrode contact424-2and the second conductive lines430may correspond to the substrate100, the first conductive lines110, the first upper electrode contact124-1, the second blanket-doped selector layer125, second upper electrode contact124-2and the second conductive lines130shown inFIG.1B, respectively, and the substrate200, the first conductive lines210, the resistance layer223, the first upper electrode contact224-1, the second blanket-doped selector layer225, the second upper electrode contact224-2and the second conductive lines230shown inFIG.2G, respectively.

Only a few embodiments and examples are described. Enhancements and variations of the disclosed embodiments and other embodiments can be made based on what is described and illustrated in this patent document.