Data serializer, latch data device using the same and controlling method thereof

A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

TECHNICAL FIELD

The disclosure relates in general to an electronic component, an electric device using the same and a controlling method thereof, and more particularly to a data serializer, a latch data device using the same and a controlling method thereof.

BACKGROUND

Along with the development of the semiconductor technology, several kinds of electric components are invented. For example, data buffers are widely used in the latch data device. The data buffer outputs data of “0” or “1” when an enable port is inputted a controlling signal of “1.” The data buffer disables output (or output “Hi-Z”) when the enable port is inputted the controlling signal of “0.”

In the data buffer, an outputting signal is raised to be “1” or fallen to be “0.” When the outputting signal is being raised or fallen, the content is invalid. In case of the raising time is longer than the falling time, the time period of “1” will be shorter than the time period of “0” under the controlling signal having fixed cycle time. In case of the raising time is shorter than the falling time, the time period of “1” will be longer than the time period of “0” under the controlling signal having fixed cycle time.

To accurately read the content “0” or “1” of the outputting signal, a data valid window excluded the union of the raising time and the falling time is used. The content “0” or “1” read at the data valid window is accurate. The difference between the raising time and the falling time greatly affects the size of the data valid window.

SUMMARY

The disclosure is directed to a data serializer, a latch data device using the same and a controlling method thereof. A de-skew buffer is used to receive a complementary outputting signal to accelerate or slow down forming an outputting signal. Therefore, the raising time and the falling time of the outputting signal become substantially identical. Because the difference between the raising time and the falling time is greatly reduced, so the size of a data valid window can be greatly increased.

According to one embodiment, a data serializer is provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

According to another embodiment, a latch data device is provided. The latch data device includes a latch circuit and an output transmitter. The output transmitter is connected to the latch circuit. The output transmitter includes a data serializer. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

According to another embodiment, a controlling method of a data serializer is provided. The data serializer includes at least one data buffer and a de-skew buffer. The controlling method comprises the following steps. The data buffer receives an inputting data and a controlling signal. The data buffer forms an outputting signal and a complementary outputting signal, which is complementary to the outputting signal, when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

DETAILED DESCRIPTION

Referring toFIG.1, a data buffer TB1according to one embodiment is shown. The data buffer TB1is, for example, a tri-state buffer TB1. The data buffer TB1has an input port I, an enable port EN and an output port O. A controlling signal C is inputted to the enable port EN. An inputting data DA is inputted to the input port I. An outputting signal Dout is outputted from the output port O.

Please refer toFIG.2, which shows a logic table of the data buffer TB1. The controlling signal C inputted to the enable port EN is “1” when it is at a predetermined level; the controlling signal C inputted to the enable port EN is “0”, when it is lower than the predetermined level. The output port O of the data buffer TB1outputs the outputting signal Dout of “0” or “1” according to the inputting data DA inputted to the input port I when the controlling signal C inputted to the enable port EN is “1.” The data buffer TB1disables output (or output “Hi-Z”) when the controlling signal C inputted to the enable port EN is “0.”

Please refer toFIG.3, which shows a circuit diagram of the data buffer TB1according to one embodiment. The data buffer TB1includes a PMOS transistor PM11, a PMOS transistor PM12, a NMOS transistor NM11, a NMOS transistor NM12, an inverter IV11and an inverter IV12. The PMOS transistor PM11, the PMOS transistor PM12, the NMOS transistor NM11and the NMOS transistor NM12are connected in series. The drain (or the source) of the PMOS transistor PM11is applied a first voltage V1. The first voltage V1is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM12is applied a second voltage V2. The inverter IV11is connected to the input port I. The gate of the PMOS transistor PM12and the gate of the NMOS transistor NM11are connected to the inverter IV11. The inverter IV12is connected between the enable port EN and the gate of the PMOS transistor PM11. The source (or the drain) of the PMOS transistor PM12and the drain of the NMOS transistor NM11are connected to the output port O.

When the controlling signal C inputted to the enable port EN is “0”, the PMOS transistor PM11and the NMOS transistor NM12are turned off. So, the current Ip1or the current In1will not be formed, and the data buffer TB1disables output (or output “Hi-Z”).

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “1”, the PMOS transistor PM11and the PMOS transistor PM12are turned on, and the NMOS transistor NM11is turned off. So the current Ip1will be formed, and the outputting signal Dout outputted from the output port O is raised to “1” which is identical to the inputting data DA.

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “0”, the NMOS transistor NM11and the NMOS transistor NM12are turned on and the PMOS transistor PM12is turned off. So the current In1will be formed, and the outputting signal Dout outputted from the output port O is fallen to “0” which is identical to the inputting data DA.

Please refer toFIG.4A, which shows voltage curves of the controlling signal C, the inputting data DA and the outputting signal Dout of the data buffer TB1in the case that the PMOS transistors PM11, PM12work slower than the NMOS transistors NM11, NM12. As shown inFIG.4A, the raising time tR of the outputting signal Dout is longer than the falling time tF of the outputting signal Dout, so the time period t1of “1” is shorter than the time period t0of “0.”

To accurately read the content “0” or “1” of the outputting signal Dout, a data valid window tDV excluded the union of the raising time tR and the falling time tF is used. The content “0” or “1” read at the data valid window tDV is accurate. The difference between the raising time tR and the falling time tF greatly affects the size of the data valid window tDV.

Please refer toFIG.4B, which shows voltage curves of the controlling signal C, the inputting data DA and the outputting signal Dout of the data buffer TB1in the case that the PMOS transistors PM11, PM12work faster than the NMOS transistors NM11, NM12. As shown inFIG.4B, the raising time tR of the outputting signal Dout is shorter than the falling time tF of the outputting signal Dout, so the time period t1of “1” will be longer than the time period t0of “0.”

To accurately read the content “0” or “1” of the outputting signal Dout, the data valid window tDV excluded the union of the raising time tR and the falling time tF is used. The content “0” or “1” read at the data valid window tDV is accurate. The difference between the raising time tR and the falling time tF greatly affects the size of the data valid window tDV.

The data buffer TB1is widely used in electric devices and latch data devices. For example, one or more data buffers TB1may be used in a data serializer.

Please refer toFIG.5, which shows a data serializer DS2according to one embodiment. The data serializer DS2includes a data buffer TB2and a de-skew buffer DB2. The operation and the controlling method of the data serializer DS2are described as follows. The data buffer TB2at least receives the inputting data DA and the controlling signal C. The outputting signal Dout and a complementary outputting signal Doutb, which is complementary to the outputting signal Dout, are formed when the controlling signal C is at the predetermined level, i.e. “1.” The de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout.

Please refer toFIG.6, which shows a logic table of the data serializer DS2. The controlling signal C inputted to the enable port EN is “1” when it is at a predetermined level; the controlling signal C inputted to the enable port EN is “0”, when it is lower than the predetermined level. The output port O of the data buffer TB2outputs the outputting signal Dout of “0” or “1” according to the inputting data DA inputted to the input port I when the controlling signal C inputted to the enable port EN is “1.” The output port OB of the data buffer TB2outputs the complementary outputting signal Doutb of “1” or “0” according to complementary value of the inputting data DA inputted to the input port I when the controlling signal C inputted to the enable port EN is “1.” The data buffer TB2disables output (or output “Hi-Z”) when the controlling signal C inputted to the enable port EN is “0.”

Refer toFIG.7, which shows a circuit diagram of the data serializer DS2according to one embodiment. The data buffer TB2includes a PMOS transistor PM21, a PMOS transistor PM22, a NMOS transistor NM21, a NMOS transistor NM22, an inverter IV21, a pass gate (buffer gate) PG, an inverter IV22, a PMOS transistor PM23, a PMOS transistor PM24, a NMOS transistor NM23, a NMOS transistor NM24, an inverter IV23, an inverter IV24and an inverter IV25. The PMOS transistor PM21, the PMOS transistor PM22, the NMOS transistor NM21and the NMOS transistor NM22are connected in series. The drain (or the source) of the PMOS transistor PM21is applied the first voltage V1. The first voltage V1is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM22is applied the second voltage V2. The inverter IV21is connected to the input port I. The pass gate PG is connected to the inverter IV21and used for supplementing the delay of the inverter IV23. The function of the pass gate PG is to make the inputting data DA entering the gate of the PMOS transistor PM22/the NMOS transistor NM21and entering the gate of the PMOS transistor PM24/the NMOS transistor NM23at the same time. The gate of the PMOS transistor PM22and the gate of the NMOS transistor NM21are connected to the pass gate PG. The inverter IV22is connected between the enable port EN and the gate of the PMOS transistor PM21. The source (or the drain) of the PMOS transistor PM22and the drain of the NMOS transistor NM21are connected to the output port O.

The PMOS transistor PM23, the PMOS transistor PM24, the NMOS transistor NM23and the NMOS transistor NM24are connected in series. The drain (or the source) of the PMOS transistor PM23is applied the first voltage V1. The first voltage V1is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM24is applied the second voltage V2. The inverter IV25is connected to the input port I. The inverter IV23is connected to the inverter IV25. The gate of the PMOS transistor PM24and the gate of the NMOS transistor NM23are connected to the inverter IV23. The inverter IV24is connected between the enable port EN and the gate of the PMOS transistor PM23. The source (or the drain) of the PMOS transistor PM24and the drain of the NMOS transistor NM23are connected to the output port OB.

When the controlling signal C inputted to the enable port EN is “0”, the PMOS transistor PM21and the NMOS transistor NM22are turned off. So, the current Ip1or the current In1will not be formed.

When the controlling signal C inputted to the enable port EN is “0”, the PMOS transistor PM23and the NMOS transistor NM24are turned off. So, a current Ip2or a current In2will not be formed.

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “1”, the PMOS transistor PM21and the PMOS transistor PM22are turned on, and the NMOS transistor NM21is turned off. So the current Ip1will be formed, and the outputting signal Dout outputted from the output port O is raised to “1” which is identical to the inputting data DA.

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “1”, the NMOS transistor NM23and the NMOS transistor NM24are turned on, and the PMOS transistor PM24is turned off. So the current In2will be formed, and the complementary outputting signal Doutb outputted from the output port OB is fallen to “0” which is complementary to the inputting data DA.

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “0”, the NMOS transistor NM21and the NMOS transistor NM22are turned on, and the PMOS transistor PM22is turned off. So the current In1will be formed, and the outputting signal Dout outputted from the output port O is fallen to “0” which is identical to the inputting data DA.

When the controlling signal C inputted to the enable port EN is “1” and the inputting data DA inputted to the input port I is “0”, the PMOS transistor PM23and the PMOS transistor PM24are turned on, and the NMOS transistor NM23is turned off. So the current Ip2will be formed, and the complementary outputting signal Doutb outputted from the output port OB is raised to “1” which is complementary to the inputting data DA.

The de-skew buffer DB2includes a PMOS transistor PM25, a NMOS transistor NM25, a PMOS transistor PM26and a NMOS transistor NM26. The PMOS transistor PM25and the NMOS transistor NM25are connected in series. The drain (or source) of the PMOS transistor PM25is applied the first voltage V1. The first voltage V1is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM25is applied the second voltage V2. The gate of the PMOS transistor PM25and the gate of NMOS transistor NM25are connected to the output port OB. The source (or the drain) of the PMOS transistor PM25and the drain of the NMOS transistor NM25are connected to the output port O.

The PMOS transistor PM26and the NMOS transistor NM26are connected in series. The drain (or source) of the PMOS transistor PM26is applied the first voltage V1. The first voltage V1is, for example, a drain voltage or a source voltage. The source of the NMOS transistor NM26is applied the second voltage V2. The source (or the drain) of the PMOS transistor PM26and the drain of the NMOS transistor NM26are connected to the output port OB. The gate of the PMOS transistor PM26and the gate of NMOS transistor NM26are connected to the output port O.

Please refer toFIG.8A, which shows voltage curves of the controlling signal C, the inputting data DA, the outputting signal Dout and the complementary outputting signal Doutb of the data serializer DS2in the case that the PMOS transistors PM21, PM22, PM23, PM24, PM25, PM26work slower than the NMOS transistors NM21, NM22, NM23, NM24, NM25, NM26.

Referring to dotted lines L211, L215inFIG.8A, the raising of the outputting signal Dout is slower than the falling of the outputting signal Dout. When the outputting signal Dout is being slowly raised, the complementary outputting signal Doutb is being rapidly fallen. At time point T21, the complementary outputting signal Doutb first reach “0”, so the PMOS transistor PM25of the de-skew buffer DB2is turned on by the complementary outputting signal Doutb. Further, at the time point T21, the outputting signal Dout is still at “0”, so the PMOS transistor PM26of the de-skew buffer DB2is turned on by the outputting signal Dout. After the PMOS transistor PM25is turned on, a current Ip3is provided to pull the outputting signal Dout high; after the PMOS transistor PM26is turned on, a current Ip4is provided to inhibit the complementary outputting signal Doutb (to pull the complementary outputting signal Doutb high). Therefore, referring to solid lines L213, L214, forming the outputting signal Dout is accelerated and forming the complementary outputting signal Doutb is slowed down.

Referring to dotted lines L215, L216inFIG.8A, when the outputting signal Dout is being rapidly fallen, the complementary outputting signal Doutb is being slowly raised. At time point T22, the complementary outputting signal Doutb is still at “0”, so the PMOS transistor PM25of the de-skew buffer DB2is turned on by the complementary outputting signal Doutb. Further, at the time point T22, the outputting signal Dout first reaches “0”, so the PMOS transistor PM26of the de-skew buffer DB2is turned on by the outputting signal Dout. After the PMOS transistor PM25is turned on, the current Ip3is provided to pull the outputting signal Dout high; after the PMOS transistor PM26is turned on, the current Ip4is provided to inhibit the complementary outputting signal Doutb (to pull the complementary outputting signal Doutb high). Therefore, referring to solid lines L217, L218, forming the outputting signal Dout is slowed down and forming the complementary outputting signal Doutb is accelerated.

As such, the raising time tR1, the falling time tF1of the outputting signal Dout and the raising time tR2, the falling time tF2of the complementary outputting signal Doutb become substantially identical. Because the difference between the raising time tR1and the falling time tF1is greatly reduced, so the size of a data valid window tDV1can be greatly increased.

Please refer toFIG.8B, which shows voltage curves of the controlling signal C, the inputting data DA, the outputting signal Dout and the complementary outputting signal Doutb of the data serializer DS2in the case that the PMOS transistors PM21, PM22, PM23, PM24, PM25, PM26work faster than the NMOS transistors NM21, NM22, NM23, NM24, NM25, NM26.

Referring to dotted lines L221, L225inFIG.8B, the raising of the outputting signal Dout is faster than the falling of the outputting signal Dout. When the outputting signal Dout is being rapidly raised, the complementary outputting signal Doutb is being slowly fallen. At time point T23, the complementary outputting signal Doutb is still at “1”, so the NMOS transistor NM25of the de-skew buffer DB2is turned on by the complementary outputting signal Doutb. Further, at the time point T23, the outputting signal Dout first reaches “1”, so the NMOS transistor NM26of the de-skew buffer DB2is turned on by the outputting signal Dout. After the NMOS transistor NM25is turned on, a current In3is provided to pull the outputting signal Dout down; after the NMOS transistor NM26is turned on, a current In4is provided to inhibit the complementary outputting signal Doutb (to pull the complementary outputting signal Doutb down). Therefore, referring to solid lines L223,1224, forming the outputting signal Dout is slowed down and forming the complementary outputting signal Doutb is accelerated.

Referring to dotted lines1225, L226inFIG.8B, when the outputting signal Dout is being slowly fallen, the complementary outputting signal Doutb is being rapidly raised. At time point T24, the complementary outputting signal Doutb first reaches “1”, so the NMOS transistor NM25of the de-skew buffer DB2is turned on by the complementary outputting signal Doutb. Further, at the time point T24, the outputting signal Dout is still at “1”, so the NMOS transistor NM26of the de-skew buffer DB2is turned on by the outputting signal Dout. After the NMOS transistor NM25is turned on, the current In3is provided to pull the outputting signal Dout down; after the NMOS transistor NM26is turned on, the current In4is provided to inhibit the complementary outputting signal Doutb (to pull the complementary outputting signal Doutb down). Therefore, referring to solid lines L227, L228, forming the outputting signal Dout is accelerated and forming the complementary outputting signal Doutb is slowed down.

As such, the raising time tR3, the falling time tF3of the outputting signal Dout and the raising time tR4, the falling time tF4of the complementary outputting signal Doutb become substantially identical. Because the difference between the raising time tR3and the falling time tF3is greatly reduced, so the size of a data valid window tDV3can be greatly increased.

Please refer toFIG.9, which shows a data serializer DS3according to another embodiment. In this embodiment, the data serializer DS3includes a data buffer TB3and the de-skew buffer DB2. The structure of the data buffer TB3is similar to that of the data buffer TB2, so the similarities are not repeated here. Compared to the data buffer TB2, the data buffer TB3further has an input port IB. The inputting data DA is inputted to the input port I, and a complementary inputting data DAB is inputted to the input port IB. The complementary inputting data DAB is complementary to the inputting data DA.

Please refer toFIG.10, which shows a circuit diagram of the data serializer DS3according to another embodiment. In this embodiment, the complementary outputting signal Doutb can be provided without the inverter IV25ofFIG.7.

The data serializers DS2, DS3described above are widely used in electric devices and latch data devices. For example, please refer toFIG.11, which shows a latch data device100according to one embodiment. The latch data device100includes a latch circuit110and an output transmitter120. The output transmitter120is connected to the latch circuit110. The data stored in the latch circuit110is transmitted through the output transmitter120. The output transmitter120includes the data serializer DS2or the data serializer DS3.

In another embodiment, the data serializer may include two, four or more data buffers. Those embodiments are described as follows.

Please refer toFIG.12, which shows a data serializer DS4according to another embodiment. InFIG.12, the data serializer DS4includes two data buffers TB3, TB4and one de-skew buffer DB2. The structure of each of the data buffers TB3, TB4is similar to that of the data buffer TB2. Similarities are not repeated here. The data buffer TB3receives the inputting data DA and the controlling signal C. The data buffer TB4receives an inputting data DB and a complementary controlling signal C #. The complementary controlling signal C # is complementary to the controlling signal C.

The outputting signal Dout and the complementary outputting signal Doutb, which is complementary to the outputting signal Dout, are formed by the data buffer TB3when the controlling signal C is at the predetermined level, i.e. “1.” The outputting signal Dout and the complementary outputting signal Doutb, which is complementary to the outputting signal Dout, are formed by the data buffer TB4when the complementary controlling signal C # is at the predetermined level, i.e. “1.” The de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout.

Please refer toFIG.13, which illustrates the outputting signal Dout ofFIG.12. The content of the inputting data DA is “DA0”, “DA1”, “DA2”, etc. The content of the inputting data DB is “DB0”, “DB1”, etc. At first, the controlling signal C is “1” and the complementary controlling signal C # is “0”, so the content of the outputting signal Dout is “DA0”. Then, the controlling signal C is “0” and the complementary controlling signal C # is “1”, so the content of the outputting signal Dout is “DB0”. Next, the controlling signal C is “1” and the complementary controlling signal C # is “0”, so the content of the outputting signal Dout is “DA1”. If the de-skew buffer DB2is not used to accelerate or slow down forming the outputting signal Dout, the falling time tF of the outputting signal Dout is much shorter than the raising time tR, in case of that the PMOS transistors work slower than the NMOS transistors.

In this embodiment, the de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate raising the outputting signal Dout and to slow down falling the outputting signal Dout. Therefore, the raising time tR is shortened to the raising time tR1, and the falling time tF is stretched to the falling time tF1. As such, the size of the data valid window tDV1can be greatly increased.

Please refer toFIG.14, which shows a data serializer DS5according to another embodiment. InFIG.14, the data serializer DS5includes two data buffers TB5, TB6and one de-skew buffer DB2. The structure of each of the data buffers TB5, TB6is similar to that of the data buffer TB3. Similarities are not repeated here. The data buffer TB5receives the inputting data DA, the complementary inputting data DAB and the controlling signal C. The data buffer TB6receives the inputting data DB, a complementary inputting data DBB and the complementary controlling signal C #. The complementary controlling signal C # is complementary to the controlling signal C.

The outputting signal Dout and the complementary outputting signal Doutb, which is complementary to the outputting signal Dout, are formed by the data buffer TB5when the controlling signal C is at the predetermined level, i.e. “1.” The outputting signal Dout and the complementary outputting signal Doutb, which is complementary to the outputting signal Dout, are formed by the data buffer TB6when the complementary controlling signal C # is at the predetermined level, i.e. “1.” The de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout.

Please refer toFIG.15, which shows a data serializer DS6according to another embodiment. InFIG.15, the data serializer DS6includes four data buffers TB7, TB8, TB9, TB10and one de-skew buffer DB2. The structure of each of the data buffers TB7, TB8, TB9, TB10is similar to that of the data buffer TB2. Similarities are not repeated here. The data buffer TB7receives the inputting data DA and a controlling signal CA. The data buffer TB8receives the inputting data DB and a controlling signal CB. The data buffer TB9receives an inputting data DC and a controlling signal CC. The data buffer TB10receives an inputting data DD and a controlling signal CD. The controlling signals CA, CB, CC, CD are taken turns to be “1” in one cycle.

The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB7when the controlling signal CA is “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB8when the controlling signal CB is “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB9when the controlling signal CC is “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB10when the controlling signal CD is “1.” The de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout.

Please refer toFIG.16, which illustrates the outputting signal Dout ofFIG.15. The content of the inputting data DA is “DA0”, “DA1”, “DA2”, etc. The content of the inputting data DB is “DB0”, “DB1”, “DB2”, etc. The content of the inputting data DC is “DC0”, “DC1”, etc. The content of the inputting data DD is “DD0”, “DD1”, etc. At first, the controlling signal CA is “1” and the controlling signals CB, CC, CD are “0”, so the content of the outputting signal Dout is “DA0”. Then, the controlling signal CB is “1” and the controlling signals CA, CC, CD are “0”, so the content of the outputting signal Dout is “DB0”. Next, the controlling signal CC is “1” and the controlling signals CA, CB, CD are “0”, so the content of the outputting signal Dout is “DC0”. Afterwards, the controlling signal CD is “1” and the controlling signals CA, CB, CC are “0”, so the content of the outputting signal Dout is “DD0”. If the de-skew buffer DB2is not used to accelerate or slow down forming the outputting signal Dout, the falling time tF of the outputting signal Dout is much shorter than the raising time tR, in case of that the PMOS transistors work slower than the NMOS transistors.

In this embodiment, the de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate raising the outputting signal Dout and to slow down falling the outputting signal Dout. Therefore, the raising time tR is shortened to the raising time tR1, and the falling time tF is stretched to the falling time tF1. As such, the size of the data valid window tDV1can be greatly increased.

Please refer toFIG.17, which shows a data serializer DS7according to another embodiment. InFIG.17, the data serializer DS7includes four data buffers TB11, TB12, TB13, TB14and one de-skew buffer DB2. The structure of each of the data buffers TB11, TB12, TB13, TB14is similar to that of the data buffer TB3. Similarities are not repeated here. The data buffer TB11receives the inputting data DA, the complementary inputting data DAB and the controlling signal CA. The data buffer TB12receives the inputting data DB, a complementary inputting data DBB and the controlling signal CB. The data buffer TB13receives the inputting data DC, a complementary inputting data DCB and the controlling signal CC. The data buffer TB14receives the inputting data DD, a complementary inputting data DDB and the controlling signal CD.

The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB11when the controlling signal CA is “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB12when the controlling signal CB is at “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB13when the controlling signal CC is at “1.” The outputting signal Dout and the complementary outputting signal Doutb are formed by the data buffer TB14when the controlling signal CD is at “1.” The de-skew buffer DB2receives the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout.

Base on above, the de-skew buffer DB2is used to receive the complementary outputting signal Doutb to accelerate or slow down forming the outputting signal Dout. Therefore, the raising time tR1, the falling time tF1of the outputting signal Dout and the raising time tR2, the falling time tF2of the complementary outputting signal Doutb become substantially identical. Because the difference between the raising time tR1and the falling time tF1is greatly reduced, so the size of a data valid window tDV1can be greatly increased.