Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

FIELD OF THE INVENTION

The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include metal gate electrodes.

BACKGROUND OF THE INVENTION

MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. Because, however, such a dielectric may not be compatible with polysilicon, it may be desirable to use metal gate electrodes in devices that include high-k gate dielectrics.

When making a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a first trench between the spacers. A first workfunction metal is deposited within the trench. A second polysilicon layer is then removed to create a second trench, and replaced with a second workfunction metal that differs from the first workfunction metal.

When applying such a replacement gate process, it may be advantageous to fill only part of the trenches with the workfunction metals, then fill the remainder of the trenches with a fill metal. In the resulting structure, the high-k gate dielectric layer, upon which the metal layers are formed, may spill over onto an oxide layer that separates the trenches. Similarly, part of the workfunction and fill metals may form above that oxide layer. In current processes, a polishing operation, e.g., a chemical mechanical polishing (“CMP”) step, may be applied to remove the high-k gate dielectric layer, the workfunction metal, and the fill metal from above the oxide layer.

If the workfunction metals polish slowly, it may require a relatively long overpolish step to completely remove them. When such an overpolish step is not selective to the underlying high-k gate dielectric layer, significant lot to lot or wafer to wafer variation in the thickness of an underlying oxide layer may result. In some cases, severe reduction in oxide thickness may occur over parts of a wafer by the time the polishing operation is completed.

Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric layer and a metal gate electrode. There is a need for such a process that enables removal of fill and workfunction metals from above an underlying dielectric layer (e.g., an oxide layer) without removing significant portions of that underlying layer and without causing the dielectric layer to manifest significant variation in thickness. The method of the present invention provides such a process.

Features shown in these figures are not intended to be drawn to scale.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.

FIGS. 1a–1jillustrate structures that may be formed, when carrying out an embodiment of the method of the present invention.FIG. 1arepresents an intermediate structure that may be formed when making a CMOS device. That structure includes first part101and second part102of substrate100. Isolation region103separates first part101from second part102. First polysilicon layer104is formed on dielectric layer105, and second polysilicon layer106is formed on dielectric layer107. First polysilicon layer104is bracketed by sidewall spacers108and109, and second polysilicon layer106is bracketed by sidewall spacers110and111. Dielectric112separates layers104and106.

Substrate100may comprise a bulk silicon or silicon-on-insulator substructure. Alternatively, substrate100may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although a few examples of materials from which substrate100may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

Isolation region103may comprise silicon dioxide, or other materials that may separate the transistor's active regions. Dielectric layers105and107may each comprise silicon dioxide, or other materials that may insulate the substrate from other substances. First and second polysilicon layers104and106preferably are each between about 100 and about 2,000 angstroms thick, and more preferably between about 500 and about 1,600 angstroms thick. In one embodiment, one layer may be doped n-type (e.g., with arsenic, phosphorus or another n-type material), while the other is doped p-type (e.g., with boron or another p-type material). Spacers108,109,110, and111preferably comprise silicon nitride, while dielectric112may comprise silicon dioxide or a low-k material.

Conventional process steps, materials, and equipment may be used to generate theFIG. 1astructure, as will be apparent to those skilled in the art. As shown, dielectric112may be polished back, e.g., via a conventional CMP step, to expose first and second polysilicon layers104and106. Although not shown, theFIG. 1astructure may include many other features (e.g., a silicon nitride etch stop layer, source and drain regions, and one or more buffer layers) that may be formed using conventional processes.

When source and drain regions are formed using conventional ion implantation and anneal processes, it may be desirable to form a hard mask on polysilicon layers104and106—and an etch stop layer on the hard mask—to protect layers104and106when the source and drain regions are covered with a silicide. Such a hard mask may comprise silicon nitride. Such an etch stop layer may comprise silicon, an oxide (e.g., silicon dioxide or hafnium dioxide), or a carbide (e.g., silicon carbide).

Such an etch stop layer and silicon nitride hard mask may be polished from the surface of layers104and106, when dielectric layer112is polished—as those layers will have served their purpose by that stage in the process.FIG. 1arepresents a structure in which any hard mask or etch stop layer, which may have been previously formed on layers104and106, has already been removed from the surface of those layers. When ion implantation processes are used to form the source and drain regions, layers104and106may be doped at the same time the source and drain regions are implanted. In such a process, first polysilicon layer104may be doped n-type, while second polysilicon layer106is doped p-type—or vice versa.

After forming theFIG. 1astructure, first polysilicon layer104is removed. In a preferred embodiment, that layer is removed by applying a wet etch process. Such a wet etch process may comprise exposing layer104to an aqueous solution that comprises a source of hydroxide for a sufficient time at a sufficient temperature to remove substantially all of that layer without removing a significant amount of second polysilicon layer106. That source of hydroxide may comprise between about 2 and about 30 percent ammonium hydroxide or a tetraalkyl ammonium hydroxide, e.g., tetramethyl ammonium hydroxide (“TMAH”), by volume in deionized water.

An n-type polysilicon layer may be removed by exposing it to a solution, which is maintained at a temperature between about 15° C. and about 90° C. (and preferably below about 40° C.), that comprises between about 2 and about 30 percent ammonium hydroxide by volume in deionized water. During that exposure step, which preferably lasts at least one minute, it may be desirable to apply sonic energy at a frequency of between about 10 KHz and about 2,000 KHz, while dissipating at between about 1 and about 10 watts/cm2. For example, an n-type polysilicon layer that is about 1,350 angstroms thick may be removed by exposing it at about 25° C. for about 30 minutes to a solution that comprises about 15 percent ammonium hydroxide by volume in deionized water, while applying sonic energy at about 1,000 KHz—dissipating at about 5 watts/cm2.

As an alternative, an n-type polysilicon layer may be removed by exposing it for at least one minute to a solution, which is maintained at a temperature between about 60° C. and about 90° C., that comprises between about 20 and about 30 percent TMAH by volume in deionized water, while applying sonic energy. Substantially all of such an n-type polysilicon layer that is about 1,350 angstroms thick may be removed by exposing it at about 80° C. for about 2 minutes to a solution that comprises about 25 percent TMAH by volume in deionized water, while applying sonic energy at about 1,000 KHz—dissipating at about 5 watts/cm2.

After removing first polysilicon layer104, dielectric layer105is exposed. In this embodiment, layer105is removed. When dielectric layer105comprises silicon dioxide, it may be removed using an etch process that is selective for silicon dioxide. Such an etch process may comprise exposing layer105to a solution that includes about 1 percent HF in deionized water. The time layer105is exposed should be limited, as the etch process for removing that layer may also remove part of dielectric layer112. With that in mind, if a 1 percent HF based solution is used to remove layer105, the device preferably should be exposed to that solution for less than about 60 seconds, and more preferably for about 30 seconds or less. As shown inFIG. 1b, removal of dielectric layer105forms trench113within dielectric layer112positioned between sidewall spacers108and109.

After removing dielectric layer105, high-k gate dielectric layer115is formed within trench113and on substrate100. Some of the materials that may be used to make high-k gate dielectric layer115include: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, and aluminum oxide. Although a few examples of materials that may be used to form high-k gate dielectric layer115are described here, that layer may be made from other materials.

High-k gate dielectric layer115may be formed on substrate100using a conventional atomic layer chemical vapor deposition (“CVD”) process. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate100and high-k gate dielectric layer115. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, high-k gate dielectric layer115should be less than about 60 angstroms thick, and more preferably between about 5 angstroms and about 40 angstroms thick.

As shown inFIG. 1c, when an atomic layer CVD process is used to form high-k gate dielectric layer115, that layer will form on the sides of trench113in addition to forming on the bottom of that trench, and will form on dielectric layer112. If high-k gate dielectric layer115comprises an oxide, it may manifest oxygen vacancies at random surface sites and unacceptable impurity levels, depending upon the process used to make it. After layer115is deposited, it may be desirable to remove impurities from that layer, and to oxidize it to generate a layer with a nearly idealized metal:oxygen stoichiometry.

To remove impurities from that layer and to increase that layer's oxygen content, a wet chemical treatment may be applied to high-k gate dielectric layer115. Such a wet chemical treatment may comprise exposing high-k gate dielectric layer115to a solution that comprises hydrogen peroxide at a sufficient temperature for a sufficient time to remove impurities from high-k gate dielectric layer115and to increase the oxygen content of high-k gate dielectric layer115. The appropriate time and temperature at which high-k gate dielectric layer115is exposed may depend upon the desired thickness and other properties for high-k gate dielectric layer115.

When high-k gate dielectric layer115is exposed to a hydrogen peroxide based solution, an aqueous solution that contains between about 2% and about 30% hydrogen peroxide by volume may be used. That exposure step should take place at between about 15° C. and about 40° C. for at least about one minute. In a particularly preferred embodiment, high-k gate dielectric layer115is exposed to an aqueous solution that contains about 6.7% H2O2by volume for about 10 minutes at a temperature of about 25° C. During that exposure step, it may be desirable to apply sonic energy at a frequency of between about 10 KHz and about 2,000 KHz, while dissipating at between about 1 and about 10 watts/cm2. In a preferred embodiment, sonic energy may be applied at a frequency of about 1,000 KHz, while dissipating at about 5 watts/cm2.

Although not shown inFIG. 1c, it may be desirable to form a capping layer, which is no more than about five monolayers thick, on high-k gate dielectric layer115. Such a capping layer may be formed by sputtering one to five monolayers of silicon, or another material, onto the surface of high-k gate dielectric layer115. The capping layer may then be oxidized, e.g., by using a plasma enhanced chemical vapor deposition process or a solution that contains an oxidizing agent, to form a capping dielectric oxide.

Although in some embodiments it may be desirable to form a capping layer on layer115, in the illustrated embodiment, first metal layer116is formed directly on high-k gate dielectric layer115to generate theFIG. 1dstructure. First metal layer116may comprise any conductive material from which a metal gate electrode may be derived, and may be formed on high-k gate dielectric layer115using well known physical vapor deposition (“PVD”) or CVD processes. Like high-k gate dielectric layer115, in this embodiment part of first metal layer116lines trench113while part of that layer spills over onto dielectric layer112.

When first metal layer116will serve as an n-type workfunction metal, layer116preferably has a workfunction that is between about 3.9 eV and about 4.2 eV. N-type materials that may be used to form first metal layer116include hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides that include these elements, i.e., titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide and aluminum carbide. First metal layer116should be thick enough to ensure that any material formed on it will not significantly impact its workfunction. Preferably, first metal layer116is between about 25 angstroms and about 300 angstroms thick, and more preferably is between about 25 angstroms and about 200 angstroms thick.

In this embodiment, after forming first metal layer116on high-k gate dielectric layer115, second metal layer121is formed on first metal layer116. Second metal layer121fills the remainder of trench113and covers dielectric layer112, as illustrated inFIG. 1e. Second metal layer121preferably comprises a material that may be easily polished, and preferably is deposited over the entire device using a conventional metal deposition process. Such a fill metal may comprise titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, nickel, or any other metal that may be polished and that may satisfactorily fill trench113.

In a particularly preferred embodiment, fill metal121comprises titanium nitride. Titanium nitride may be deposited using an appropriate CVD or PVD process that does not significantly affect underlying first metal layer116or high-k gate dielectric layer115. In addition, when second polysilicon layer106is subsequently removed (as described below), titanium nitride may be more resistant than other metals to the etch chemistry used to remove that layer. When fill metal121comprises tungsten, a CVD process that employs a WF6precursor may be used to deposit a tungsten layer. Care should be taken to ensure that the process used to deposit such a tungsten layer does not adversely affect the underlying workfunction and high-k gate dielectric layers. In addition, when fill metal121comprises tungsten, it may be necessary to select an etch chemistry for removing second polysilicon layer106that does not remove significant portions of that fill metal.

As an alternative to using PVD, CVD, or atomic layer CVD processes to form second metal layer121on first metal layer116, second metal layer121may be formed on first metal layer116using an electroplating or electroless plating process. Plating technologies may be particularly suited for filling trenches with high aspect ratios. Various combinations of deposition and plating processes may be used to form second metal layer121.

Although in this embodiment, second metal layer121is formed directly on first metal layer116, in an alternative embodiment, a relatively thin sealant layer may be formed on first metal layer116prior to forming second metal layer121.FIGS. 2a–2brepresent cross-sections of structures that may be formed when carrying out such an alternate embodiment of the method of the present invention. As shown inFIG. 2a, sealant layer130is formed on first metal layer116. Sealant layer130may be about 100 angstroms thick, and may be formed using a conventional deposition process.

Sealant layer130should comprise a highly conformal conductive layer that protects workfunction metal116during subsequent process steps. In this regard, sealant layer130should comprise a material that prevents chemicals that are used in subsequent polishing steps (e.g., slurries and post polish cleaning solutions) from degrading the performance of workfunction metal116and/or high-k gate dielectric layer115. Suitable materials may include metal carbides, metal carbide alloys, metal nitrides, and metal nitride alloys. In a particularly preferred embodiment, sealant layer130comprises titanium carbide and is formed using a conventional atomic layer CVD process. Alternatively, sealant layer130may comprise a titanium nitride or tantalum nitride layer, which is formed using an atomic layer CVD or other CVD process.

In this alternative embodiment, second metal layer121is formed on sealant layer130, as shown inFIG. 2b—e.g., by using the materials and process steps that are identified above in connection withFIG. 1e.

After forming theFIG. 1estructure, at least part of second metal layer121is removed from above dielectric layer112using a polishing step. In a preferred embodiment, a CMP step is applied to remove substantially all of second metal layer121from above dielectric layer112to generate theFIG. 1fstructure—workfunction metal116acting as a polish stop. Although such a CMP step may be applied to remove all of fill layer121from above dielectric layer112, while stopping on first metal layer116, in alternative embodiments, a relatively thin portion of second metal layer121may remain above dielectric layer112following the CMP operation. Alternatively, the CMP step may remove part or all of workfunction metal116from above dielectric layer112in addition to removing fill metal121from above dielectric layer112.

After that CMP step, additional material is removed from above dielectric layer112using an etch step. In a preferred embodiment, substantially all of first metal layer116, which remains after the chemical mechanical polishing step, is removed from above dielectric layer112using a dry etch step. In a preferred embodiment, such a dry etch step is highly selective to high-k gate dielectric layer115, enabling layer115to act as an etch stop. The etch step may comprise a plasma dry etch process, e.g., one using a chlorine based plasma. The duration of such a plasma dry etch process may be controlled to prevent a significant part of underlying high-k gate dielectric layer115from being removed during that process. Alternatively, such a plasma dry etch process may remove substantially all of high-k gate dielectric layer115from above dielectric layer112, when removing the remainder of workfunction metal116.

If the fill metal polishing step previously removed all of workfunction metal116, then a subsequent dry etch process may be applied to remove substantially all of high-k gate dielectric layer115, which remained after the polishing step, from above dielectric layer112. Alternatively, any remaining portion of layer115may be removed using a wet etch process. Such a wet etch process may use a relatively strong acid, e.g., a halide based acid (such as hydrobromic or hydrochloric acid) or phosphoric acid. Similarly, if a previous dry etch process removed workfunction metal116from above dielectric layer112, without removing all of underlying layer115, then such a wet etch process may be employed to remove the remainder of layer115. Such a wet etch process may also be applied to clean the surface of the resulting structure, after high-k gate dielectric layer115is removed from above dielectric layer112.

After one or more etch processes are used to remove substantially all of workfunction metal116and/or high-k gate dielectric layer115from above dielectric layer112to generate theFIG. 1gstructure, second polysilicon layer106is removed. If layer106comprises a p-type polysilicon layer, then that layer may be removed selectively to second metal layer121by exposing layer106to a solution that comprises between about 20 and about 30 percent TMAH by volume in deionized water for a sufficient time at a sufficient temperature (e.g., between about 60° C. and about 90° C.), while applying sonic energy.

After removing second polysilicon layer106, dielectric layer107is removed, e.g., by using the same process that was used to remove dielectric layer105. Removing dielectric layer107generates trench114, asFIG. 1hillustrates. Following the removal of that dielectric layer, high-k gate dielectric layer117is formed within trench114and onto dielectric layer112. The same process steps and materials used to form high-k gate dielectric layer115may be used to form high-k gate dielectric layer117.

In this embodiment, third metal layer120is then deposited on high-k gate dielectric layer117. If first metal layer116comprises an n-type metal, then third metal layer120preferably comprises a p-type metal. Examples of p-type metals that may be used include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. Although a few examples of materials that may be used to form third metal layer120are described here, that layer may be made from many other materials.

Third metal layer120may comprise a second workfunction metal that is formed on high-k gate dielectric layer117using a conventional PVD or CVD process. Third metal layer120preferably is between about 25 angstroms and about 300 angstroms thick, and more preferably is between about 25 angstroms and about 200 angstroms thick. If third metal layer120comprises a p-type metal, layer120preferably has a workfunction that is between about 4.9 eV and about 5.2 eV.

After forming third metal layer120on high-k gate dielectric layer117, fourth metal layer118, e.g., a second fill metal, may be formed on third metal layer120to generate theFIG. 1istructure. The same process steps and materials used to form second metal layer121may be used to form fourth metal layer118. The portions of second fill metal118, second workfunction metal120and high-k gate dielectric layer117that cover dielectric layer112may then be removed to generate theFIG. 1jstructure. The same combination of polish and etch steps used to remove first fill metal121, first workfunction metal116and high-k gate dielectric layer115from above dielectric layer112may be used to remove second fill metal118, second workfunction metal120and high-k gate dielectric layer117from above dielectric layer112.

After removing second fill metal118, second workfunction metal120and high-k gate dielectric layer117from above dielectric layer112, a capping dielectric layer (not shown) may be deposited onto the resulting structure using a conventional deposition process. Process steps for completing the device that follow the deposition of such a capping dielectric layer, e.g., forming the device's contacts, metal interconnect, and passivation layer, are well known to those skilled in the art and will not be described here.

As illustrated above, the method of the present invention enables production of CMOS devices that include a high-k gate dielectric layer and metal gate electrodes. This method enables removal of fill and workfunction metals from above an underlying dielectric layer without removing significant portions of that underlying layer and without causing the dielectric layer to manifest significant variation in thickness. This method may facilitate such a result by applying a highly selective dry etch process to remove difficult to polish workfunction metals, rather than remove them using a polishing process. Although the embodiments described above provide examples of processes for forming CMOS devices with a high-k gate dielectric layer and metal gate electrodes, the present invention is not limited to these particular embodiments.

Although the foregoing description has specified certain steps and materials that may be used in the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, all such modifications, alterations, substitutions and additions fall within the spirit and scope of the invention as defined by the appended claims.