SEMICONDUCTOR DEVICE

An object is to provide a technique capable of reducing in the size of a semiconductor device. A semiconductor device includes a second semiconductor switching element having a rectangular shape with a long side facing a first semiconductor switching element in plan view, having an area smaller than that of the first semiconductor switching element in plan view, and composed of a wide bandgap semiconductor, and a plurality of first wires connecting the first semiconductor switching element and the second semiconductor switching element, being 40 μm or less in diameter, and composed of silver or gold.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a semiconductor device.

Description of the Background Art

In recent years, there has been proposed a technique of connecting an emitter terminal of an Insulated Gate Bipolar Transistor (IGBT) and a source terminal of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with a wire (for example, Japanese Patent Application Laid-Open No. 2014-130909). From the viewpoint of current density, in typical practice, power chips such as IGBTs and MOSFETs are connected by a thick wire being 200 to 400 μm in diameter and made of aluminum.

However, for example, in the commonly used wedge bonding method for wire bonding for thick wires, a bonding area on the order of millimeters is typically required. Accordingly, the bonding area for the thick wire is relatively large, which has remained a problem of the size of the semiconductor device not being reduced.

SUMMARY

The present disclosure has been made in view of the above problem and has an object to provide a technique capable of reducing the size of the semiconductor device.

According to the present disclosure, a semiconductor device includes a first semiconductor switching element composed of silicon, a second semiconductor switching element having a rectangular shape with a long side facing the first semiconductor switching element in plan view, having an area smaller than that of the first semiconductor switching element in plan view, and composed of a wide bandgap semiconductor, and a plurality of first wires connecting the first semiconductor switching element and the second semiconductor switching element, being 40 μm or less in diameter, and composed of silver or gold.

The reduction in size of the semiconductor device is enabled.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, Embodiments will be described with reference to the attached drawings. Features described in each of following Embodiments are examples, and not all features are necessarily essential. In addition, in the description given below, the same or similar components are given the same or similar reference numerals in a plurality of Embodiments, and components that are different will be mainly described. Also, in the following description, terms indicating specific positions or directions such as “upper”, “lower”, “left”, “right”, “front”, and “back” may not necessarily coincide with the positions or directions at the time of implementation.

FIG.1is a plan view illustrating a configuration of a semiconductor device according to Embodiment 1 andFIG.2is an enlarged plan view illustrating a part of the configuration ofFIG.1. The semiconductor device ofFIG.1includes a first semiconductor switching element1, a second semiconductor switching element2, a plurality of chip wires3, lead frames4a,4b,4c, a lead wire5, a gate wire6, a control chip7, and a scaling resin8.

The first semiconductor switching element1is composed of silicon. The second semiconductor switching element2has a smaller area than the first semiconductor switching element1in plan view, and is composed of a wide bandgap semiconductor. The wide bandgap semiconductor includes, for example, silicon carbide (SiC), gallium nitride (GaN), diamond, and the like. The second semiconductor switching element2composed of a wide bandgap semiconductor is capable of stable operation under higher temperature and higher voltage and faster switching speed than the first semiconductor switching element1composed of silicon.

Hereinafter, a configuration in which the first semiconductor switching element1is an Insulated Gate Bipolar Transistor (IGBT) and the second semiconductor switching element2is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) will be described as an example. However, the first semiconductor switching element1and the second semiconductor switching element2may also be, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), IGBTs, and Reverse Conducting-IGBTs (RC-IGBTs).

InFIG.2, a gate pad1aand an emitter terminal are provided on the front side of the first semiconductor switching element1, and a collector terminal is provided on the back side. InFIG.2, a gate pad2aand a source terminal are provided on the front side of the second semiconductor switching element2, and a drain terminal is provided on the back side.

A plurality of chip wires3, which area plurality of first wires, connect the emitter terminal of the first semiconductor switching element1and the source terminal of the second semiconductor switching element2. Each of the plurality of chip wires3is 40 μm or less in diameter, and each of the plurality of chip wires3is composed of silver or gold.

Such chip wires3are relatively thin; therefore, a ball bonding method is adopted instead of a wedge bonding method for the bonding of the chip wires3, for example. As a result, the bonding area of the chip wire3can be reduced to the order of micrometers, and design restrictions due to the bonding area can be relaxed.

In the following description, the chip wire3will be appropriately compared with a thick wire. The thick wire, which is thicker than the diameter of the chip wire3, is for example, 200 μm or more and 400 μm or less in diameter, and is composed of aluminum, for example.

Increasing the number of chip wires3enables bringing the total current density of a plurality of chip wires3to be equivalent to the current density of the thick wire. Meanwhile, even if the number of chip wires3is increased, the total bonding area of a plurality of chip wires3is made smaller than the bonding area of thick wires because of the minuscule bonding area of each chip wire3.

As described above, according to the configuration according to Embodiment 1, in which the first semiconductor switching element1and the second semiconductor switching element2are connected by the plurality of chip wires3, reduction in size of the semiconductor device is enabled.

Further, in Embodiment 1, as illustrated inFIGS.1and2, the second semiconductor switching element2has a rectangular shape with the long side facing the first semiconductor switching element1in plan view. The long side of the second semiconductor switching element2and the side of the first semiconductor switching element1facing the long side may be parallel or substantially parallel. According to such a configuration, a plurality of chip wires3can be arranged along the longitudinal direction of the second semiconductor switching element2. Consequently, the length of the plurality of chip wires3can be shortened, so the reduction in size of the semiconductor device is enabled.

Further, in Embodiment 1, the longitudinal direction of the second semiconductor switching element2is perpendicular to the extending direction of the plurality of chip wires3in plan view. According to such a configuration, the length of the plurality of chip wires3can be shortened further, so the further reduction in size of the semiconductor device is enabled. However, the longitudinal direction of the second semiconductor switching element2may not be perpendicular to the extending direction of the plurality of chip wires3, and may be substantially perpendicular, for example.

A first semiconductor switching element1and a second semiconductor switching element2are mounted on each of the lead frames4aand4b. In each of the lead frames4aand4b, a collector terminal of the mounted first semiconductor switching element1and a drain terminal of the mounted second semiconductor switching element2are electrically connected. The first semiconductor switching element1and the second semiconductor switching element2are not mounted on the lead frames4c.

The lead wires5connect the first semiconductor switching element1mounted on the lead frame4aand the lead frames4b. Also, the lead wires5connect the first semiconductor switching elements1mounted on the lead frames4band the lead frames4c. In Embodiment 1, the lead wires5are thick wires. The surface on the front side of the first semiconductor switching element1is relatively large and has a margin capable of accommodating the bonding area of the thick wire; therefore, there is no actual increase in the size of the semiconductor device even if the lead wires5are thick wires.

The gate wires6connect the gate pad1aof the first semiconductor switching element1to the control chip7, and the gate pad2aof the second semiconductor switching element2to the control chip7, respectively.

The control chip7controls the gate voltage of the first semiconductor switching element1and the gate voltage of the second semiconductor switching element2through the gate wires6to control the first semiconductor switching element1and the second semiconductor switching element2. In Embodiment 1, the control chip7is provided on the side opposite to the first semiconductor switching element1with respect to the second semiconductor switching element2in a plan view, that is, the second semiconductor switching element2is provided between the control chip7and the first semiconductor switching element1.

The control chip7on the right side inFIG.1is a High VoltAge IC (HVIC), and controls the gate voltages of three sets of first semiconductor switching element1and second semiconductor switching element2from the right side to control the current between the lead frame4aand the lead frames4b. The control chip7on the left side inFIG.1is a Low VoltAge IC (LVIC), and controls the gate voltages of three sets of first semiconductor switching element1and second semiconductor switching element2from the left side to control the current between the lead frames4band the lead frames4c.

Although the number of control chips7is two in the example ofFIG.1, providing one control chip7may also be adoptable. Also, although in the example ofFIG.1, the number of sets of the first semiconductor switching element1and the second semiconductor switching element2is six, the number is not limited thereto.

The sealing resin8covers the first semiconductor switching elements1, the second semiconductor switching elements2, and the control chips7. The sealing resin8is formed by injecting an uncured resin from the mold gate into the mold. AlthoughFIG.1illustrates that the sealing resin8has a resin gate trace8athat is a trace of the gate, the resin gate trace8ais not essential in Embodiment 1.

Summary of Embodiment 1

According to the above semiconductor device of Embodiment 1, the second semiconductor switching element2has a rectangular shape with the long side facing the first semiconductor switching element1in plan view. A plurality of chip wires3being 40 μm or less in diameter and composed of silver or gold connect the first semiconductor switching elements1and the second semiconductor switching elements2, respectively. According to such a configuration, the reduction in size of the semiconductor device is enabled.

In Embodiment 1, the control chip7is provided on the side opposite to the first semiconductor switching element1with respect to the second semiconductor switching element2in a plan view. According to such a configuration, the connecting portions between the lead frames4a,4b,4cand the lead wires5can be provided on the side opposite to the control chips7and the second semiconductor switching elements2with respect to the first semiconductor switching elements1. As a result, the main current flows through the first semiconductor switching elements1and the lead wires5; thereby reducing the current flowing through the second semiconductor switching elements2. Consequently, a reduction in the number of chip wires3is enabled, and a reduction in manufacturing cost can be expected.

As illustrated inFIG.3, the connection points of the plurality of chip wires3with the first semiconductor switching element1and the second semiconductor switching element2may be placed in an alternate manner along the arrangement direction of the plurality of chip wires3(that is, in a staggered pattern). According to such a configuration, the number of the plurality of chip wires3per unit area can be increased; therefore, increasing the total number of the plurality of chip wires3or reducing the total bonding area of the plurality of chip wires3is enabled. The same divided current flows through the plurality of chip wires3; therefore, no substantial problem arises even if the chip wires3come into contact with each other.

FIG.4is a side view illustrating a part of a configuration of a semiconductor device according to Modification 2, viewed from the resin gate trace8aside inFIG.1. As illustrated inFIG.4, the loop heights of the plurality of chip wires3may increase in order of increasing distance from the resin gate trace8a.

According to such a configuration, when the sealing resin8is formed, the flow of the resin injected from the mold gate can be suppressed while passing through the plurality of chip wires3. For this reason, providing a component with weak mechanical strength on the opposite side of the mold gate with respect to the plurality of chip wires3enables the suppression of defects in the component due to the flow of resin. In the example inFIG.4, the component is represented by a relatively long gate wire6connecting the first semiconductor switching element1and the control chip7, and according to the above configuration, disconnection of the gate wire6can be suppressed.

In the configuration ofFIG.1of Embodiment 1, the lead wires5are thick wires, however they are not limited thereto. As illustrated inFIG.5, the lead wires5, which are second wires, are 40 μm or less in diameter and may be wires composed of silver or gold as with the plurality of chip wires3.

In short, the lead wires5connecting the first semiconductor switching element1mounted on the lead frame4awhich is a first lead frame and the lead frame4bwhich are the second lead frame may be wires of 40 μm or less in diameter. Also, the lead wires5connecting the first semiconductor switching element1mounted on the lead frame4bwhich is the first lead frame and the lead frame4cwhich are the second lead frame may also be wires of 40 μm or less in diameter.

According to such a configuration, the bonding area of the lead wires5can be made small, thereby, ensuring the reduction in the size of the semiconductor device. Also, adopting the same wires for the chip wires3and the lead wires5improves manufacturability.

Further, as illustrated inFIGS.6to8, a thick wire9, which is a third wire having a diameter larger than that of the chip wires3, may further be included. As illustrated inFIG.6, the thick wire9may connect the first semiconductor switching elements1mounted on the lead frames4a,4band the lead frames4b,4c, respectively, in coordination with lead wires5inFIG.5. As illustrated inFIG.7, the thick wire9may connect the first semiconductor switching element1and the second semiconductor switching element2, in coordination with chip wires3inFIG.5. As illustrated inFIG.8, the thick wires9may connect the first semiconductor switching elements1mounted on the lead frames4a,4band the lead frames4b,4c, respectively, and may also connect the first semiconductor switching element1and the second semiconductor switching element2.

According to such a configuration, the thick wires9that are difficult to disconnect are adopted, thereby improving the reliability of the semiconductor device. Also, the current density of each path can be sufficiently secured.

As illustrated inFIG.9, fourth wires are the gate wires6, one of which connects the first semiconductor switching element1and the control chip7, and another of which connects the second semiconductor switching element2and the control chip7. The gate wires6may extend in a direction perpendicular to the direction in which the first semiconductor switching element1and the second semiconductor switching element2are arranged. With such a configuration, the length of the gate wire6can be shortened, so disconnection of the gate wire6during injection of the sealing resin8can be suppressed.

It should be noted that Embodiment can be appropriately modified or omitted.

Hereinafter, the aspects of the present disclosure will be collectively described as Appendices.

A semiconductor device comprising:a first semiconductor switching element composed of silicon;a second semiconductor switching element having a rectangular shape with a long side facing the first semiconductor switching element in plan view, having an area smaller than that of the first semiconductor switching element in plan view, and composed of a wide bandgap semiconductor; anda plurality of first wires connecting the first semiconductor switching element and the second semiconductor switching element, being 40 μm or less in diameter, and composed of silver or gold.

The semiconductor device according to Appendix 1, wherein in plan view, a longitudinal direction of the second semiconductor switching element is perpendicular to an extending direction of the plurality of first wires.

The semiconductor device according to Appendix 1 or 2, wherein connection points of the plurality of first wires with the first semiconductor switching element and the second semiconductor switching element are placed along an arrangement direction of the plurality of first wires in an alternate manner.

The semiconductor device according to any one of Appendices 1 to 3, further comprising:a control chip configured to control the first semiconductor switching element and the second semiconductor switching element; anda sealing resin having a resin gate trace and covering the first semiconductor switching element, the second semiconductor switching element, and the control chip, whereinloop heights of the plurality of first wires increase in order of increasing distance from the resin gate trace.

The semiconductor device according to any one of Appendices 1 to 3, further comprisinga control chip configured to control the first semiconductor switching element and the second semiconductor switching element, whereinin a plan view, the control chip is provided on a side opposite to the first semiconductor switching element with respect to the second semiconductor switching element.

The semiconductor device according to any one of Appendices 1 to 5, further comprising:a first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted;a second lead frame; anda plurality of second wires being 40 μm or less in diameter and connecting the first semiconductor switching element mounted on the first lead frame and the second lead frame.

The semiconductor device according to any one of Appendices 1 to 5, further comprising:a first lead frame on which the first semiconductor switching element and the second semiconductor switching element are mounted;a second lead frame; anda third wire connecting at least one of between the first semiconductor switching element mounted on the first lead frame and the second lead frame or between the first semiconductor switching element and the second semiconductor switching element and having a diameter larger than that of the first wires.

The semiconductor device according to any one of Appendices 1 to 3, further comprising:a control chip configured to control the first semiconductor switching element and the second semiconductor switching element; andfourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged.

While the invention has been illustrated and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.