Resistance change memory element and resistance change memory

According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.

FIELD

Embodiments described herein relate generally to a memory element.

BACKGROUND

Resistance change memories that store data based on the resistance state are researched and developed. The resistance change memory includes a memory layer of which the resistance can change between a low resistance state and a high resistance state. Data storing can be assigned data to the low resistance state and the high resistance state. Here, the memory layer can be switched between the low resistance state and the high resistance state by applying a voltage to electrodes formed at its both ends.

DETAILED DESCRIPTION

According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.

Hereinbelow, embodiments are described with reference to the drawings. In the following description, identical components are marked with the same reference numerals, and a description of components once described is omitted as appropriate.

First Embodiment

FIG. 1Cshows an example of a cross-point memory cell array using a memory element1. InFIG. 1C, two layers of memory cell arrays are shown as an example. A memory cell is provided at the intersection of each bit line80and each word line90. Memory cells are arranged in a matrix configuration in the X direction (a first direction) and the Y direction (a second direction).

Each bit line80and each word line90contain a material containing a metal, having a high heat resistance, and having a low resistance value. For example, each bit line and each word line contain tungsten (W), titanium (Ti), tantalum (Ta), a nitride of these, a stacked structure of these, or the like.

FIG. 1Ais an example of a schematic cross-sectional view showing a memory element according to a first embodiment,FIG. 1Bis an example of a schematic plan view showing the memory element according to the first embodiment, andFIG. 1Cshows an example of a cross-point memory cell array using the memory element according to the first embodiment.

FIG. 1Ashows a cross section in the position of line A-A′ ofFIG. 1B.

The memory element1is, for example, a resistance change element of an interface oxidation type. The memory element1includes an electrode layer10(a first electrode layer), an electrode layer20(a second electrode layer), and a memory layer30A. The memory layer30A is provided between the electrode layer10and the electrode layer20. The memory layer30A includes a plurality of oxide layers31(first oxide layers) and an oxide layer32(a second oxide layer) provided between the plurality of oxide layers31. The memory element may be referred to as a resistance change element. The memory layer may be referred to as a resistance change layer.

The plurality of oxide layers31are aligned in the Z direction (a first direction) from the electrode layer10toward the electrode layer20, and are aligned via the oxide layer32in a direction (a second direction) crossing the Z direction. The direction crossing the Z direction is, for example, the X direction or the Y direction. The resistivity of each of the plurality of oxide layers31is higher than the resistivity of the oxide layer32. That is, in the memory layer30A, the plurality of oxide layers31that are more resistive than the oxide layer32are scattered three-dimensionally in the oxide layer32. One of the plurality of oxide layers31is in contact with the electrode layer10. Another of the plurality of the oxide layers31is disposed apart from the electrode layer10.

Each of the oxide layers31and32is, for example, a metal oxide layer.

The oxide layer31or the oxide layer32contains an oxide of at least one element selected from the group consisting of hafnium (Hf), aluminum (Al), zirconium (Zr), titanium (Ti), silicon (Si), vanadium (V), tantalum (Ta), manganese (Mn), niobium (Nb), chromium (Cr), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), and copper (Cu).

Each of the electrode layer10and the electrode layer20contains at least one element selected from the group consisting of tungsten (W), molybdenum (Mo), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), ruthenium (Ru), iridium (Ir), silver (Ag), and platinum (Pt).

In the plurality of oxide layers31and the oxide layer32, the elements contained in the oxide layers31and32are selected so that the absolute value of the standard Gibbs free energy of formation of the oxide contained in each of the plurality of oxide layers31is larger than the absolute value of the standard Gibbs free energy of formation of the oxide contained in the oxide layer32.

Alternatively, in the plurality of oxide layers31and the oxide layer32, the elements contained in the oxide layers31and32are selected so that the absolute value of the standard Gibbs free energy of formation of the oxide contained in each of the plurality of oxide layers31is smaller than the absolute value of the standard Gibbs free energy of formation of the oxide contained in the oxide layer32.

Here, the standard Gibbs free energy of formation of an oxide contained in an oxide layer A is expressed as ΔGa(kJ/mol, 298.15 K). The standard Gibbs free energy of formation when a metal element contained in an oxide layer B changes to an oxide is expressed as ΔGb.

The oxide layer32has a composition deviated from the stoichiometric composition. The oxide layer32is a metal-rich oxide layer. The oxide layer32has a small electrical conductivity. In the memory element1, as a result of the plurality of oxide layers31being scattered in the oxide layer32, the oxide layer32is sandwiched by adjacent oxide layers31. The region of the sandwiched oxide layer32forms a current path30p. The current path30pextends in the Z direction. The current path30pis in contact with the electrode layers10and20. In the memory element1, a plurality of current paths30pare provided between the electrode layer10and the electrode layer20. The oxide layers31are not limited to the case of being arranged in a matrix configuration. The oxide layers31may be randomly arranged in the memory layer30A. It is sufficient that at least the current flowing through the oxide layer32be limited by the existence of the oxide layer31and a current path be formed in the oxide layer32between oxide layers31.

To suppress the oxidation of the electrode layers10and20, the elements contained in the oxide layers31and32or the electrode layers10and20are selected so that the absolute value of the standard Gibbs free energy of formation of the oxide contained in the oxide layers31and32is larger than the absolute value of the standard Gibbs free energy of formation when the metal element contained in the electrode layers10and20changes to an oxide.

FIG. 1Ashows a state where part of the plurality of oxide layers31are in contact with at least one of the electrode layer10and the electrode layer20. The embodiment includes also a state where part of the plurality of oxide layers31are not in contact with at least one of the electrode layer10and the electrode layer20.

FIG. 2is an example of a circuit diagram of a memory cell array of a memory device using the memory element according to the first embodiment. Here,FIG. 2shows a circuit diagram of a memory cell array100of only one stage in the Z direction. Actually the memory cell array100shown inFIG. 2is stacked vertically and horizontally.

A voltage can be applied to the electrode layer10via the bit line80, and a voltage can be applied to the electrode layer20via the word line90. Here, the memory layer30A can be given a potential difference of a polarity whereby the bit line80becomes a higher potential, and can be given a potential difference of a polarity whereby the word line90becomes a higher potential. That is, the memory element1can be used as a bipolar resistance change element.

In addition, the memory cell array100may include a selector40. The selector40is provided between the memory element1and the bit line80, for example. The selector includes a diode through which a current flows in one direction and a current does not flow in the opposite direction thereof and an element through which a current does not flow at or below a certain positive or negative threshold voltage and a current flows forward or backward upon exceeding the threshold voltage. For example, the selector40is a tunnel diode. The selector40may be also a field effect transistor, for example.

FIG. 3AandFIG. 3Bare examples of schematic cross-sectional views showing a method for manufacturing a memory element according to the first embodiment.

First, as shown inFIG. 3A, a stacked body30stin which an oxide layer31L and the oxide layer32are alternately stacked is formed between the electrode layer10and the electrode layer20. The components of the oxide layer31L are the same as the components of the oxide layer31.

The stacked body30stis provided between the electrode layer10and the electrode layer20in such a manner that the oxide layer31L that is high resistive is in contact with the electrode layer10or the electrode layer20.

Next, heating treatment is performed on the stacked body30st. When the stacked body30stis heated, the aggregation effect of a coating occurs, and the plurality of oxide layers31L are separated. Thereby, the oxide layer32is provided between a plurality of oxide layers31.

Thus, the oxide layer32is in contact with the electrode layer10or the electrode layer20so as to be sandwiched by oxide layers31. That is, the area with which the oxide layer32is in contact with the electrode layer10or the electrode layer20is smaller than the area with which the memory layer30A is in contact with the electrode layer10or the electrode layer20.

FIG. 4AandFIG. 4Bare examples of schematic cross-sectional views showing operations of the memory element according to the first embodiment.

FIG. 4Ashows a situation where the memory layer30A is in a high resistance state, andFIG. 4Bshows a situation where the memory layer30A is in a low resistance state. In the memory element1, by forming a high resistance region30hand by eliminating the high resistance region30h, the resistance can be changed to store information.

For example, as shown inFIG. 4A, a voltage is applied so that the electrode layer10becomes a higher potential. Due to the potential difference applied between the electrode layer10and the electrode layer20, oxygen ions (O2−) are generated in the oxide layer32. Here, the current flows through the narrow region of the oxide layer32sandwiched by oxide layers31. That is, Joule heat is efficiently generated in the oxide layer32, and oxygen ions are produced in a large amount from the oxide layer32.

The oxygen ions are minus ions, and therefore move to the side of the electrode layer10, which is an anode. A voltage, which is at a level necessary for the movement of oxygen ions, is applied between the electrode layer10and the electrode layer20.

Thereby, the reactivity between oxygen ions and the oxide layer32near the electrode layer10is enhanced, and the oxidation reaction of the oxide layer32near the electrode layer10is promoted. Here, near the electrode layer10, the area with which the electrode layer10and the oxide layer32are in contact is smaller than the area with which the memory layer30A is in contact with the electrode layer10. This is because the electrode layer10and the oxide layer31are in contact. Consequently, in the oxide layer32of the electrode layer10, a high resistance region30hhaving a high oxygen concentration and a high resistance is formed. The electrons possessed by the oxygen ions flow to the electrode layer10. The high resistance region30his an oxide layer of the stoichiometric composition or near the stoichiometric composition.

Here, when the high resistance region30his formed, it becomes difficult for a current to flow between the electrode layer10and the electrode layer20. That is, the memory layer30A is switched to a high resistance state.

As shown inFIG. 4B, a voltage is applied so that the electrode layer10becomes a lower potential. In this case, the electric field of the high resistance region30hbecomes strong in the memory layer30A. This is because the resistivity of the high resistance region30his relatively high in the memory layer30A. Therefore, oxygen ions are generated in a large amount in the high resistance region30h.

The oxygen ions are diffused to the side of the electrode layer20, which is an anode. Consequently, the oxygen concentration of the high resistance region30his reduced. The oxygen ions cause a reaction with the oxide layer32in an oxygen deficient state outside the high resistance region30h. The electrons possessed by the oxygen ions flow to the electrode layer20. That is, the high resistance region30hdisappears, and the memory layer30A returns to the low resistance state.

Thus, in the memory element1, bidirectional (bipolar) voltage control is used to form and eliminate the high resistance region30hnear the electrode layer20; thereby, information can be written and erased. For example, the state of the memory element1in the high resistance state is put as information “0”. The state of the memory element1in the low resistance state is put as information “1”.

Changing the memory element1from the high resistance state to the low resistance state is referred to as, for example, setting, and changing the memory element1from the low resistance state to the high resistance state is referred to as, for example, resetting. By repeating such a set operation and a reset operation, information can be written on the memory element1and information can be erased from the memory element1.

To enhance the oxidation degree of the oxide layer32near the electrode layer10, the movement of oxygen ions in the oxide layer32is necessary. In the memory element1, to make it easy for oxygen ions to move, an oxygen deficient film, which has a lower oxygen concentration than the stoichiometric composition, is used as the oxide layer32that forms a current path. Since the high resistive oxide layers31are scattered in the memory layer30A, it is easy for a current to be passed through the oxide layer32.

Consequently, the high resistance region30hcan be effectively formed in the oxide layer32near the electrode layer10. Thereby, in the memory element1, the power consumption in the write operation and the erase operation is reduced.

In the memory element1, part of the plurality of oxide layers31are in contact with at least one of the electrode layer10and the electrode layer20. Consequently, the contact area between the oxide layer32and the electrode layer10(or the electrode layer20) is reduced as compared to the case where the plurality of oxide layers31are not in contact with at least one of the electrode layer10and the electrode layer20.

Therefore, the current path flowing from the oxide layer32to the electrode layer10is narrowed, and it becomes easy for the high resistance region30hto be formed. Consequently, the power consumption in switching to a high resistance, that is, in forming the high resistance region30his reduced. Similarly, power consumption is reduced also in switching to a low resistance.

In the memory element1, the elements contained in the oxide layers are selected so that the absolute value of the standard Gibbs free energy of formation of the oxide contained in the high resistive oxide layer31is larger than the absolute value of the standard Gibbs free energy of formation of the oxide contained in the low resistive oxide layer32.

In the case of such a combination of materials, there is no case where the oxide layer32reduces the oxide layer31, so that the oxygen concentration of the oxide layer32is increased. Therefore, the oxygen deficient state of the oxide layer32can be maintained. Consequently, the operating voltage of the memory layer30A is stabilized, and the resistance value retention property is improved.

In the memory element1, the elements contained in the oxide layers may be selected so that the absolute value of the standard Gibbs free energy of formation of the oxide contained in the high resistive oxide layer31is smaller than the absolute value of the standard Gibbs free energy of formation of the oxide contained in the low resistive oxide layer32. In this case, it is easy for the low resistive oxide layer32to become high resistive. Therefore, also in this case, the operating voltage of the memory layer30A is stabilized, and the resistance value retention property is improved.

The plurality of oxide layers31are formed by self alignment in which the oxide layer31L is separated into a plurality of oxide layers31by heating treatment. That is, in the first embodiment, photolithography technology and etching process technology are not needed for the formation of the memory layer30A. In other words, the manufacturing process according to the first embodiment is simple, and an increase in manufacturing costs is not caused.

In a filament-type resistance change element, the forming operation for forming a filament in a memory layer is generally needed. On the other hand, the forming operation is not needed in the memory element1according to the first embodiment.

Second Embodiment

FIG. 5is an example of a schematic cross-sectional view showing a memory element according to a second embodiment.

A memory element2according to the second embodiment includes the electrode layers10and20and a memory layer30B. The memory layer30B includes a plurality of oxide layers33and an oxide layer34. Each of the plurality of oxide layers33includes a crystalline phase. The oxide layer34includes an amorphous phase. The crystallization temperature of the plurality of oxide layers33is lower than the crystallization temperature of the oxide layer34. That is, the oxide layer33crystallizes more easily than the oxide layer34.

FIG. 6AandFIG. 6Bexamples of are schematic cross-sectional views showing a method for manufacturing a memory element according to the second embodiment.

First, as shown inFIG. 6A, an oxide layer34L with a composition deviated from the stoichiometric composition is formed between the electrode layer10and the electrode layer20. The oxide layer34L contains an oxide having oxygen deficiency. The oxide layer34L is amorphous.

Next, as shown inFIG. 6B, heating treatment is performed on the oxide layer34L. Thereby, parts of the low crystallized material of the oxide layer34L are crystallized to form a plurality of oxide layers33. Thereby, the plurality of oxide layers33are formed as to be scattered in the oxide layer34.

Thus, by using a material with a lower crystallization temperature than the oxide layer34and performing heating treatment on the oxide layer34L at not less than the crystallization temperature of the oxide layer33and not more than the crystallization temperature of the oxide layer34, the oxide layer33of a high resistance layer can be formed selectively in the oxide layer34.

The oxide layer33or the oxide layer34contains an oxide of at least one element selected from the group consisting of hafnium (Hf), aluminum (Al), zirconium (Zr), titanium (Ti), silicon (Si), vanadium (V), tantalum (Ta), manganese (Mn), niobium (Nb), chromium (Cr), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), and copper (Cu).

The oxide layer33and the oxide layer34may contain oxides of the same element. For example, the oxide layer33contains niobium pentoxide (Nb2O5) and the oxide layer34contains niobium dioxide (NbO2).

In the memory element2, a current path30pis formed in the region of the oxide layer34sandwiched by adjacent oxide layers33. The oxide layer33is in a state of the stoichiometric composition or near the stoichiometric composition. Therefore, the oxide layer33is a high resistive metal oxide layer. On the other hand, the oxide layer34is in an oxygen deficient state, and is therefore a low resistive metal oxide layer. Since the oxygen in the oxide layer34L has been reduced by the crystallization of the oxide layer33, the oxygen concentration in the oxide layer34is lower than the oxygen concentration in the oxide layer34L. Therefore, the oxide layer34in an amorphous state maintains the low resistance state.

Also the memory element2can be given a potential difference of a polarity whereby the electrode layer10becomes a higher potential, and can be given a potential difference of a polarity whereby the electrode layer20becomes a higher potential. Also in the memory element2, the high resistance region30his formed on the anode side, and the high resistance region30his eliminated by the movement of oxygen ions and the Joule heat generated near the current path30p. In other words, also in the memory element2, the high resistance state and the low resistance state of the memory layer30B can be created with good efficiency. Thus, the memory element2exhibits similar operation and effect to the memory element1.

Third Embodiment

FIG. 7is an example of a schematic cross-sectional view showing a memory element according to a third embodiment.

The basic structure of a memory element3according to the third embodiment is the same as the basic structure of the memory element2. In addition, in the memory element3, each of the plurality of oxide layers33includes a crystalline phase that is grown by using an impurity piece33nas a nucleus.

FIG. 8AandFIG. 8Bare examples of schematic cross-sectional views showing a method for manufacturing a memory element according to the third embodiment.

First, as shown inFIG. 8A, the oxide layer34L with a composition deviated from the stoichiometric composition is formed between the electrode layer10and the electrode layer20. A plurality of impurity pieces33nare scattered in the oxide layer34L.

The oxide layer34L containing the plurality of impurity pieces33nis formed by the sputtering method using a metal oxide target containing an impurity, the two-dimensional sputtering method of a metal oxide target and an impurity target, a method of doping the oxide layer34L with an impurity, or the like.

Next, as shown inFIG. 8B, heating treatment is performed on the oxide layer34L. Thereby, parts of the oxide layer34L are crystallized, and the parts form a plurality of oxide layers33. Consequently, the plurality of oxide layers33each including a crystalline phase are scattered in the oxide layer34.

In the crystallization, the oxide layer33grows by using the impurity piece33nas a nucleus. That is, the oxide layer33grows from the nucleus. By the concentration of impurity pieces33nbeing adjusted almost uniformly in the oxide layer34L, the plurality of oxide layers33are arranged more uniformly in the oxide layer34. Since the nucleus serving as a starting point of crystallization is present, the heating treatment temperature can be further reduced. Also in the third embodiment, similar effects to the first or second embodiment are obtained.

Fourth Embodiment

FIG. 9Ais an example of a schematic cross-sectional view showing a memory element according to a first example of a fourth embodiment, andFIG. 9Bis an example of a schematic cross-sectional view showing a memory element according to a second example of the fourth embodiment.

The basic structure of a memory element4shown inFIG. 9Ais the same as the basic structure of the memory element1. In addition, the memory element4further includes an oxide layer50(a third oxide layer) surrounding the side surface of the memory layer30A.

The absolute value of the standard Gibbs free energy of formation of the oxide contained in the oxide layer50may be larger than the absolute value of the standard Gibbs free energy of formation of the oxide contained in each of the plurality of oxide layers31and the absolute value of the standard Gibbs free energy of formation of the oxide contained in the oxide layer32. That is, the oxide layer50includes an oxide layer more stable than the oxide layers31and32.

The memory cell array100includes a plurality of memory elements (FIG. 1CandFIG. 2). By the oxide layer50being provided in the memory element4, the interference between the operations of adjacent memory elements4is suppressed. For example, by the oxide layer50, the current flowing through the memory element4can be prevented from leaking to between memory elements. Thereby, the high resistance region30hcan be reliably formed in a selected memory element4, and a malfunction of another memory element4due to a leaking current can be prevented.

In addition to the structure in which a plurality of oxide layers31are three-dimensionally scattered in the oxide layer32, also a structure in which a plurality of oxide layers31are arranged two-dimensionally on the electrode layer10side is included in the embodiment. For example,FIG. 9Billustrates a memory element5in which a plurality of oxide layers31are arranged two-dimensionally on the electrode layer10side. The plurality of oxide layers31are two-dimensionally arranged in contact with the electrode layer10.

Also in such a structure, near the electrode layer10, Joule heat is concentrated in the narrow region of the oxide layer32sandwiched by oxide layers31. Oxygen ions move to the electrode layer10side due to an electric field, and obtain reaction energy from the Joule heat. Thereby, the reactivity between the oxygen ions and the oxide layer32near the electrode layer10is enhanced, and the oxidation reaction of the oxide layer32near the electrode layer10is promoted. Consequently, the high resistance region30hcan be formed near the electrode layer10.

The embodiments have been described above with reference to examples. However, the embodiments are not limited to these examples. More specifically, these examples can be appropriately modified in design by those skilled in the art. Such modifications are also encompassed within the scope of the embodiments as long as they include the features of the embodiments. The components included in the above examples and the layout, material, condition, shape, size and the like thereof are not limited to those illustrated, but can be appropriately modified.

The term “on” in “a portion A is provided on a portion B” refers to the case where the portion A is provided on the portion B such that the portion A is in contact with the portion B and the case where the portion A is provided above the portion B such that the portion A is not in contact with the portion B.

Furthermore, the components included in the above embodiments can be combined as long as technically feasible. Such combinations are also encompassed within the scope of the embodiments as long as they include the features of the embodiments. In addition, those skilled in the art could conceive various modifications and variations within the spirit of the embodiments. It is understood that such modifications and variations are also encompassed within the scope of the embodiments.