Series of parallel sensing operations for multi-level cells

Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

BACKGROUND

Developments in electronic devices, such as computers, portable devices, smart phones, internet of thing (IoT) devices, etc., have prompted increased demands for memory devices. In general, memory devices may be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data while power is provided, but may lose the stored data once the power is shut off. Unlike volatile memory devices, non-volatile memory devices may retain data even after the power is shut off, but may be slower than the volatile memory devices.

DETAILED DESCRIPTION

In accordance with some embodiments, data stored by a multi-level cell (MLC) is read through a series of parallel sensing operations. In one aspect, a first parallel sensing operation is performed through two or more sense amplifiers to determine a first bit of multiple bits of data stored by the MLC. For example, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits to determine one or more bits (e.g., most significant bits (MSBs)) of the multiple bits of data stored by the MLC. According to the determined one or more bits, a second parallel sensing operation can be performed through the two or more sense amplifiers. For example, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits (e.g., least significant bits (LSBs)) of the multiple bits of data stored by the multi-level cell can be determined.

Advantageously, the series of parallel sensing operations disclosed herein allows sensing multiple bits of data stored by an MLC in an area and time efficient manner. For example, serial sensing through a single sense amplifier allows reduction in an area of the integrated circuit but may take a long time. Meanwhile, parallel sensing through multiple sense amplifiers allows sensing in a time efficient manner, but multiple sense amplifiers may consume a large area of the integrated circuit. By determining one or more bits (e.g., MSBs) of multiple bits of data stored by the MLC through a first parallel sensing operation and one or more bits (e.g., LSBs) of the multiples bits of data stored by the MLC through a second parallel sensing operation based on the first parallel sensing operation, less number of comparators can be implemented compared to a number of comparators for performing a single parallel sensing operation. Moreover, a speed of comparison can be improved compared to a speed of comparison for performing a serial sensing operation. Hence, multiple bits of data stored by the MLC can be read in an area and time efficient manner.

FIG. 1is a diagram of a memory device100, in accordance with one embodiment. In some embodiments, the memory device100includes a memory controller105and a memory array120. The memory array120may include a plurality of storage units or storage circuits125arranged in two or three dimensional arrays. Each storage circuit may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller105may write data to or read data from the memory array120according to electrical signals through word lines WL and bit lines BL. In other embodiments, the memory device100includes more, fewer, or different components than shown inFIG. 1.

The memory array120is a hardware component that stores data. In one aspect, the memory array120is embodied as a semiconductor memory device. The memory array120includes a plurality of storage units or storage circuits125. The memory array120includes word lines WL0, WL1. . . WLJ, each extending in a first direction (e.g., X-direction) and bit lines BL0, BL1. . . BLK, each extending in a second direction (e.g., Y-direction). The word lines WL and the bit lines BL may be conductive metals or conductive rails. In one aspect, each storage circuit125is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to voltages or currents through the corresponding word line WL and the corresponding bit line BL. In one aspect, each storage circuit125includes a MLC. An MLC is a single memory cell capable of storing multiple bits of data. Examples of the storage circuit125include a volatile memory cell such as a phase change random access memory (PCRAM) cell, a resistive random access memory (RRAM) cell, or any memory cell that stores multiple bits of data. In some embodiments, the memory array120includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.). Detailed descriptions on configurations and operations of memory device100are provided below with respect toFIGS. 2 through 5.

The memory controller105is a hardware component that controls operations of the memory array120. In some embodiments, the memory array120includes a bit line controller112, a word line controller114, and a timing controller110. In one configuration, the word line controller114is a circuit that provides a voltage or a current through one or more word lines WL of the memory array120, and the bit line controller112is a circuit that provides or senses a voltage or current through one or more bit lines BL of the memory array120. In one configuration, the timing controller110is a circuit that provides control signals or clock signals to synchronize operations of the bit line controller112and the word line controller114. The bit line controller112may be coupled to bit lines BL of the memory array120, and the word line controller114may be coupled to word lines WL of the memory array120. In one example, to write data to a storage circuit125, the word line controller114provides a voltage or current to the storage circuit125through a word line WL coupled to the storage circuit125, and applies a bias voltage to the storage circuit125through a bit line BL coupled to the storage circuit125. In one example, to read data from a storage circuit125, the word line controller114provides a voltage or current to the storage circuit125through a word line WL coupled to the storage circuit125, and senses a voltage or current corresponding to data stored by the storage circuit125through a bit line BL coupled to the storage circuit125. In some embodiments, the memory controller105includes more, fewer, or different components than shown inFIG. 1.

FIG. 2is a diagram of a sensing device205that performs a series of parallel sensing operations, in accordance with some embodiments. In some embodiments, the sensing device205is part of the bit line controller112ofFIG. 1. In some embodiments, the sensing device205includes a sense controller210, sense amplifiers240A-240C, multiplexers220A-220C, and reference circuits250AA . . .250AE,250BA . . .250BE,250CA . . .250CE. In one aspect, these components operate together to perform a series of parallel sensing operations to read data from the storage circuit125(also referred to as “a MLC125” herein). In other embodiments, the sensing device205includes more, fewer, or different components than shown inFIG. 2. For example, in some embodiments, the sensing device205includes more or different number of sense amplifiers240, multiplexers220, and reference circuits250than shown inFIG. 2.

In some embodiments, each reference circuit250is a circuit that provides a corresponding reference characteristic. An example characteristic includes a discharge rate, a resistance, a voltage, etc. In some embodiments, the reference circuits250can be replaced by other components that perform similar functions of the reference circuits250. In one aspect, a characteristic (a discharge rate, a resistance, a voltage, etc.) of the MLC125can be set, programmed or configured, from a plurality of predetermined resistances, according to multiple bits of data stored. For example, a resistance of a memory cell between a reference resistance 0thRref(e.g., 400Ω) and a reference resistance 1thRref(e.g., 4 kΩ) represents [0001], a resistance of the memory cell between the reference resistance 1thRref(e.g., 4 kΩ) and a reference resistance 2ndRref(e.g., 40 kΩ) represents [0010], and a resistance of the memory cell between the reference resistance 2ndRref(e.g., 40 kΩ) and a reference resistance 3rdRref(e.g., 400 kΩ) represents [0011]. In some embodiments, the reference circuits250are set, designed or implemented with different values of reference characteristics that can be compared against the programmed characteristic of the MLC125to determine multiple bits of data stored by the MLC125. In one some embodiments, each of the reference circuits250AA . . .250AE,250BA . . .250BE,250CA . . .250CE has a corresponding one of reference resistances 0thRref. . . 14thRref, that can be used to identify or distinguish 16 values of 4 bit data. The reference resistances 0thRref. . . 14thRrefmay monotonically (linearly or non-linearly) increase in that sequence. In one aspect, the reference circuits250AA . . .250AE,250BA . . .250BE,250CA . . .250CE have non-monotonically assigned reference resistances to allow efficient parallel sensing. In one configuration, the reference circuits250AA . . .250AE have reference resistances 3rdRref, 0thRref, 4thRref, 8thRref, 12thRref, respectively; the reference circuits250BA . . .250BE have reference resistances 7thRref, 1stRref, 5thRref, 9thRref, 13thRref, respectively; and the reference circuits250CA . . .250CE have reference resistances 11thRref, 2ndRref, 6thRref, 10thRref, 14thRref, respectively. Such arrangement of resistances allows efficient parallel sensing operations, as described below with respect toFIG. 3.

In some embodiments, each multiplexer220is a circuit that electrically couples, from a corresponding subset of reference circuits250, a selected reference circuit to a corresponding sense amplifier240. In other embodiments, the multiplexers220can be replaced by other components that perform similar functions of the multiplexers220. In one configuration, the multiplexer220A includes input ports coupled to a subset of reference circuits250AA . . .250AE, and an output port coupled to an input port of the sense amplifier240A. In addition, the multiplexer220B includes input ports coupled to a subset of reference circuits250BA . . .250BE, and an output port coupled to an input port of the sense amplifier240B. In addition, the multiplexer220C includes input ports coupled to a subset of reference circuits250CA . . .250CE, and an output port coupled to an input port of the sense amplifier240C. Moreover, each of the multiplexers220A-220C includes a control port coupled to the sense controller210to receive a control signal from the sense controller210. In this configuration, each of the multiplexers220A-220C may electrically couple, from a corresponding subset of reference circuits250, a selected reference circuit to a corresponding sense amplifier240according to a control signal from the sense controller210. For example, the multiplexer220A electrically couples the reference circuit250AA to the sense amplifier240A, while the multiplexer220B electrically couples the reference circuit250BA to the sense amplifier240B and the multiplexer220C electrically couples the reference circuit250CA to the sense amplifier240C. When the multiplexer220electrically couples, from a subset of reference circuits, a selected reference circuit to a corresponding sense amplifier, the remaining reference circuits of the subset of the reference circuits may be electrically decoupled from the corresponding sense amplifier. Hence, a voltage, current, or resistance at the selected sense amplifier can be provided to the corresponding sense amplifier, while voltages, currents, or resistances at the remaining sense amplifiers may not be provided to the corresponding sense amplifier.

In some embodiments, each sense amplifier240is a circuit that compares a characteristic of the MLC125with a reference characteristic of a selected reference circuit250through a corresponding multiplexer220. In other embodiments, the sense amplifier240can be replaced by other components that perform similar functions of the sense amplifiers220. In one configuration, each sense amplifier includes a first input port (e.g., shown as “−”) coupled to the MLC125through the bit line BL, a second input port (e.g., shown as “+”) coupled to a corresponding multiplexer220, and an output port coupled to the sense controller210. In one configuration, a sense amplifier240compares a discharge rate of a MLC125with a discharge rate of the selected reference circuit250. In one aspect, the MLC125can be modeled as a resistor Rcellwith a capacitor CBLcorresponding to a capacitance of the bit line BL. In one example, a voltage of the MLC125at the bit line BL can decrease at a rate corresponding to the resistance Rcellset or programmed. Similarly, a voltage of the selected reference circuit250can decrease at a rate corresponding to a predetermined resistance of the selected reference circuit250. In one approach, the sense controller210may charge or set the MLC125and the selected reference circuit250to have the same voltage. After a predetermined time period (e.g., 10 ns), a voltage of the MLC125at the bit line BL and a voltage of the selected reference circuit250may differ, because the MLC125and the selected reference circuit250have different discharge rates. After the predetermined time period, the sense amplifier240may detect a difference in a voltage of the MLC125at the bit line BL and a voltage of the selected reference circuit250, and generate an output signal according to the detected difference. For example, in response to a voltage (e.g., 400 mV) of the MLC125being higher than a voltage (e.g., 300 mV) of the selected reference circuit250, the MLC125may generate an output signal having 0V or logic [0]. Conversely, in response to a voltage (e.g., 300 mV) of the MLC125being lower than a voltage (e.g., 400 mV) of the selected reference circuit250, the MLC125may generate an output signal having VDD or logic value [1].

In some embodiments, the sense controller210is a circuit that configures one or more components of the sensing device205to perform a series of parallel sensing operations to determine multiple bits of data stored by the MLC125according to outputs from the sense amplifiers240A-240C. The sense controller210may be embodied as a digital logic circuit or a state machine. In other embodiments, the sense controller210can be replaced by other components that perform similar functions of the sense controller210. In one configuration, the sense controller210includes input ports coupled to outputs ports OutA, OutB, OutC of the sense amplifiers240A-240C. In addition, the sense controller210includes one or more output ports coupled to control ports of the multiplexers220A-220C to provide control signals for one or more reference circuits250. In this configuration, the sense controller210can perform a first parallel sensing operation through the sense amplifiers240A-240C to determine a value (or values) of one or more bits (e.g., MSB) of multiple bits of data stored by the MLC125. In addition, the sense controller210can perform a second parallel sensing operation through the sense amplifiers240A-240C based at least in part on the one or more bits (e.g., MSB) of the multiple bits of data determined by the first parallel sensing operation to determine a value (or values) of one or more bits (e.g., LSB) of multiple bits of data stored by the MLC125. Assuming for an example that the MLC125can store 4 bit data [YYXX], the sense controller210may perform the first parallel sensing through the sense amplifier240A-240C to determine values of the two MSBs [YY]. Then, according to the MSBs [YY], the sense controller210may perform the second parallel sensing through the sense amplifier240A-240C to determine values of the two LSBs [XX].

In some embodiments, to perform a parallel sensing operation, the sense controller210may configure each of the multiplexers220A-220C to select a predetermined reference circuit from a corresponding subset of reference circuits250, and determine one or more bits (e.g., MSB) of data stored by the MLC125according to the selected reference circuits. In one approach, the sense controller210configures the multiplexer220A-220C to select the reference circuits250AA,250BA,250CA having predetermined or pre-assigned reference resistances (e.g., 3rdRref, 7thRref, 11thRref) for determining the one or more bits (e.g., MSBs). In one example, the reference resistances 3rdRref, 7thRref, 11thRrefare predetermined or assigned for determining first two bits of multiple bits (e.g., [YY] of [YYXX]). For example, the MLC125storing any of [0000], [0001], [0010], [0011] has a resistance lower than the reference resistance 3rdRref; the MLC125storing any of [0100], [0101], [0110], [0111] has a resistance between the reference resistance 3rdRrefand the reference resistance 7thRref; the MLC125storing any of [1000], [1001], [1010], [1011] has a resistance between the reference resistance 7rdRrefand the reference resistance 11thRref; and the MLC125storing any of [1100], [1101], [1110], [1111] has a resistance greater than the reference resistance 11rdRref. During the first time period, the sense amplifiers240A,240B,240C may compare characteristic (e.g., discharge rate) of the MLC125with characteristic (e.g., discharge rates) of the selected reference circuits (e.g.,250AA,250BA,250CA), and determine a value (or values) of one or more bits (e.g., MSB) of multiple bits of data stored by the MLC125according to the comparison.

In one example, a discharge rate less than a discharge rate of the reference circuit250AA corresponds to [00XX] of data stored by the MLC125; a discharge rate between i) the discharge rate of the reference circuit250AA having the reference resistance 3rdRrefand ii) a discharge rate of the reference circuit250BA having the reference resistance 7thRrefcorresponds to [01XX] of data stored by the MLC125; a discharge rate between i) the discharge rate of the reference circuit250BA and ii) a discharge rate of the reference circuit250CA having the reference resistance 11thRrefcorresponds to [10XX] of data stored by the MLC125; and a discharge rate higher than the discharge rate of the reference circuit250CA corresponds to [11XX] of data stored by the MLC125. In this example, the sense controller210can determine first two MSBs according to outputs OutA, OutB, OutC from the sense amplifiers240A-240C. For example, if the outputs OutA, OutB, OutC are [110] in a thermometer code (corresponding to ‘2’ in a decimal representation as indicated a number of ‘1’), the sense controller210may determine that a discharge rate of the MLC125is higher than discharge rates of the reference circuits250AA,250BA but less than the discharge rate of the reference circuit250CA. Accordingly, the sense controller210may determine that first two MSBs of the MLC125is [10] in a binary code (corresponding to ‘2’ in the decimal representation).

In some embodiments, to perform a subsequent parallel sensing, the sense controller210may select, from each of different sets of reference circuits, a reference circuit according to the determined one or more bits through the prior parallel sensing, and cause the multiplexers220A-220C to electrically couple the selected reference circuits to corresponding sense amplifiers240A-240C during a second time period. For example, in response to [00] of two bits determined during the prior sensing, the reference circuits250AB,250BB,250CB having resistances 0thRref, 1stRref, 2ndRref, respectively, are selected to determine values of subsequent two bits [XX] from [00XX]; in response to [01] of two bits determined during the prior sensing, the reference circuits250AC,250BC,250CC having resistances 4thRref, 5thRref, 6thRref, respectively, are selected to determine subsequent two bits [XX] from [01XX]; in response to [10] of two bits determined during the prior sensing, the reference circuits250AD,250BD,250CD having resistances 8thRref, 9thRref, 10thRref, respectively, are selected to determine subsequent two bits [XX] from [10XX]; and in response to [11] of two bits determined during the prior sensing, the reference circuits250AE,250BE,250CE having reference resistances 12thRref, 13thRref, 14thRref, respectively, are selected, to determine subsequent two bits [XX] from [11XX], Assuming for an example that two bits determined through the prior parallel sensing is [10], the sense controller210selects the reference circuits250AD,250BD,250CD having reference resistances 8thRref, 9thRref, 10thRref, associated with [10] for determining subsequent bits [XX] of [10XX], Then, the sense controller210generates one or more control signals to configure the multiplexers220A,220B,220C to electrically couple the selected reference circuits250AD,250BD,250CD to the sense amplifiers240A,240B,240C, respectively, during the second time period. The sense amplifiers240A-240C may compare characteristics of selected reference circuits with the characteristic of the MLC125during the second time period. The sense controller210may determine one or more bits (e.g., LSB) of multiple bits of data stored by the MLC125according to outputs from the sense amplifiers240A-240C during the second time period in a similar manner as determining the one or more bits (e.g., MSB) of the multiple bits of data.

Advantageously, the series of parallel sensing operations disclosed herein allows sensing multiple bits of data stored by a MLC125in an area and time efficient manner. For example, serial sensing through a single sense amplifier allows reduction in an area of the integrated circuit, but may take a long time. Meanwhile, parallel sensing through multiple sense amplifiers allows sensing in a time efficient manner, but multiple sense amplifiers may consume a large area of the integrated circuit. By determining a value (or values) of one or more bits (e.g., MSBs) of multiple bits (e.g., [YY] of [YYXX]) of data stored by the MLC125through a first parallel sensing operation and determining one or more bits (e.g., LSBs) of the multiples bits (e.g., [XX] of [YYXX]) of data stored by the MLC125through a second parallel sensing operation based on the first parallel sensing operation, less number of comparators can be implemented compared to a number of comparators for performing a single parallel sensing operation. Moreover, a speed of comparison can be improved compared to a speed of comparison for performing a serial sensing operation. Hence, multiple bits of data stored by the MLC can be read in an area and time efficient manner.

FIG. 3is an example timing diagram300of performing parallel sensing and serial sensing, in accordance with some embodiments. Assuming for an example that a MLC125can have one of 16 predetermined resistance states to represent 4 bit data. In one approach, to read stored data from the MLC125, the MLC125can perform a series of parallel sensing operations.

For the first parallel sensing operation, in one approach, the sense controller210configures the multiplexers220A,220B,220C to select predetermined reference circuits250AA,250BA,250CA having reference resistances 3rdRref, 7thRref, and 11thRref. In one example, the reference resistances 3rdRref, 7thRref, 11thRrefare predetermined or assigned for determining first two bits of multiple bits of data stored (e.g., [YY] of [YYXX]). During a first time period, the multiplexer220A can electrically couple the reference circuit250AA to the sense amplifier240A, the multiplexer220B can electrically couple the reference circuit250BA to the sense amplifier240B, and the multiplexer220C can electrically couple the reference circuit250CA to the sense amplifier240C simultaneously. The sense amplifiers240A,240B,240C can compare characteristic (e.g., voltage or discharge rate) of the MLC125with characteristics of the reference circuits250AA,250BA,250CA, and output the comparisons, for example, in a thermometer code. For example, if the discharge rate of the MLC125is higher than a discharge rate of the reference circuit250AA but less than discharge rates of the reference circuits250BA,250CA, the sense amplifiers240A,240B,240C can output [100], because the resistance of the MLC125is determined to be greater than the reference resistance 3rdRref, but less than the reference resistances 7thRref, 11thRref. The sense controller210can receive outputs from the sense amplifiers240A,240B,240C, and decode the outputs in the thermometer code into 2 bit binary representation, which may correspond to MSBs of data stored by the MLC125. For example, the thermometer code [100] having one ‘1’ can be converted into a binary representation [01].

For the second parallel sensing operation, in one approach, the sense controller210selects, for each multiplexer, a corresponding reference circuit according to the one or more determined bits in the first parallel sensing operation. Assuming for an example that [01] is determined from the first parallel sensing operation, the sense controller210configures the multiplexers220A,220B,220C to select reference circuits250AC,250BC,250CC corresponding to the determined bits [01], The reference circuits250AC,250BC,250CC may have reference resistances 4thRref, 5thRref, and 6thRref, respectively. The sense amplifiers240A,240B,240C can compare characteristic (e.g., voltage or discharge rate) of the MLC125with characteristics of the reference circuits250AC,250BC,250CC, and output the comparisons, for example, in a thermometer code. For example, if the discharge rate of the MLC125is higher than a discharge rate of the reference circuits250AC,250BC, but less than discharge rates of the reference circuit250CC, the sense amplifiers240A,240B,240C can output [110], The sense controller210can receive outputs from the sense amplifiers240A,240B,240C, and decode the outputs in the thermometer code into a 2 bit binary representation, which may correspond to LSBs of data stored by the MLC125. For example, the thermometer code [110] having two ‘1’ can be converted to binary representation [10],

FIG. 4is a flowchart of a method400of reading multiple bits of data stored by a multi-level cell, in accordance with some embodiments. The method400may be performed by the sensing device205ofFIG. 2. In some embodiments, the method400is performed by other entities. In some embodiments, the method400includes more, fewer, or different operations than shown inFIG. 4.

In an operation410, the sensing device205performs a first parallel sensing operation through sense amplifiers (e.g.,240A-240C) with reference circuits (e.g.,250AA,250BA,250CA) during a first time period. In one approach, the sense amplifiers (e.g.,240A-240C) simultaneously compares a characteristic (e.g., a resistance, a discharge rate, a voltage, etc.) of a memory cell (e.g., MLC125) with characteristics of the reference circuits (e.g.,250AA,250BA,250CA) during the first time period, and determine a value (or values) of one or more bits (e.g., MSBs) of multiple bits of data stored by the memory cell (e.g., MLC125).

In one approach, the operation410includes operations412,414. In the operation412, a sense controller (e.g.,210) selects reference circuits (e.g.,250AA,250BA,250CA) from a set of reference circuits (e.g.,250AA-250AE,250BA-250BE,250CA-250CE). In one aspect, each subset of the set of reference circuits250is associated with a corresponding one of multiplexers (e.g.,220A,220B,220C). For example, the reference circuits250AA-250AE are associated with the multiplexer220A, the reference circuits250BA-250BE are associated with the multiplexer220B, and the reference circuits250CA-250CE are associated with the multiplexer220C. In the operation412, the sense controller (e.g.,210) may select, from each of the subsets of the set of reference circuits250, predetermined reference circuits (e.g.,250AA,250BA,250CA). The sense controller (e.g.,210) may generate one or more control signals to configure the multiplexers220A-220C to electrically couple the selected reference circuits (e.g.,250AA,250BA,250CA) to the corresponding sense amplifiers240A-240C, respectively, during the first time period.

In an operation414, the sense controller (e.g.,210) determines a value (or values) of one or more bits (e.g., MSBs) of the multiple bits of data stored by the memory cell (e.g., MLC125) according to the reference circuits (e.g.,250AA,250BA,250CA). In one approach, the multiplexers220A-220C can electrically couple the selected reference circuits (e.g.,250AA,250BA,250CA) to the sense amplifiers (e.g.,240A-240C), respectively, according to the control signal from the sense controller (e.g.,210). The sense amplifiers (e.g.,240A-240C) can compare a characteristic (e.g., a resistance, a discharge rate, a voltage, etc.) of the memory cell (e.g., MLC125) with characteristics of the reference circuits (e.g.,250AA,250BA,250CA), and generate outputs according to the comparisons during the first time period. In one example, the outputs of the sense amplifiers (e.g.,240A-240C) are represented in a thermometer code. The sense controller (e.g.,210) may receive the outputs of the sense amplifiers (e.g.,240A-240C) in the thermometer code, and convert the received outputs into a binary representation. For example, if the outputs OutA, OutB, OutC are [110] in a thermometer code, the sense controller (e.g.,210) may determine that a discharge rate of the MLC125is higher than discharge rates of the reference circuits250AA,250BA but less than the discharge rate of the reference circuit250CA. Accordingly, the sense controller210may determine that first two MSBs of the MLC125is [10] in a binary code corresponding to the thermometer code [110] having two ‘1’.

In an operation430, the sensing device205performs a second parallel sensing operation though the sense amplifiers (e.g.,240A-240C) with different reference circuits (e.g.,250AD,250BD,250CD) during a second time period. In one approach, different reference circuits (e.g.,250) are selected according to the value (or the values) of the one or more bits determined in the operation410. The sense amplifiers (e.g.,240A-240C) can simultaneously compare the characteristic (e.g., a resistance, a discharge rate, a voltage, etc.) of the memory cell (e.g., MLC125) with characteristics of the different reference circuits (e.g.,250AA,250BA,250CA) during the second time period, and determine one or more bits (e.g., LSBs) of the multiple bits of data stored by the memory cell (e.g., MLC125).

In one approach, the operation430includes operations432,434. In the operation432, the sense controller (e.g.,210) selects different reference circuits (e.g.,250AD,250BD,250CD) from a set of reference circuits (e.g.,250AA-250AE,250BA-250BE,250CA-250CE), according to the determined one or more bits in the operation410. For example, the reference circuits250AB,250BB,250CB having resistances 0thRref, 1stRref, 2ndRref, respectively, correspond to [00] of two bits determined during the prior sensing; the reference circuits250AC,250BC,250CC having resistances 4thRref, 5thRref, 6thRref, respectively, correspond to [01] of two bits determined during the prior sensing; the reference circuits250AD,250BD,250CD having resistances 8thRref, 9thRref, 10thRref, respectively, correspond to [10] of two bits determined during the prior sensing; and the reference circuits250AE,250BE,250CE having resistances 12thRref, 13thRref, 14thRref, respectively, correspond to [11] of two bits determined during the prior sensing. Assuming for an example that two bits determined in the operation410is [10], the sense controller210selects the reference circuits250AD,250BD,250CD.

In the operation434, the sense controller (e.g.,210) determines additional one or more bits of the multiple bits of data stored by the memory cell according to the different reference circuits. In one approach, the multiplexers220A-220C can electrically couple the reference circuits (e.g.,250AD,250BD,250CD) selected in the operation432to the sense amplifiers (e.g.,240A-240C), respectively. The sense amplifiers (e.g.,240A-240C) can compare the characteristic (e.g., a resistance, a discharge rate, a voltage, etc.) of the memory cell (e.g., MLC125) with characteristics of the reference circuits (e.g.,250AD,250BD,250CD), and generate outputs according to the comparisons during the second time period. The sense controller (e.g.,210) may receive the outputs of the sense amplifiers (e.g.,240A-240C) in the thermometer code, and convert the received outputs into the binary representation. In one aspect, the one or more bits determined in the operation434corresponds to LSB of the multiple bits of data stored by the memory cell (e.g., MLC125).

Advantageously, the series of parallel sensing operations disclosed herein allows sensing multiple bits of data stored by a MLC125in an area and time efficient manner. For example, serial sensing through a single sense amplifier allows reduction in an area of the integrated circuit, but may take a long time. Meanwhile, parallel sensing through multiple sense amplifiers allows sensing in a time efficient manner, but multiple sense amplifiers may consume a large area of the integrated circuit. By determining one or more bits (e.g., MSBs) of multiple bits of data stored by the MLC through a first parallel sensing operation and one or more bits (e.g., LSBs) of the multiples bits of data stored by the MLC125through a second parallel sensing operation based on the first parallel sensing operation, less number of comparators can be implemented compared to a number of comparators for performing a single parallel sensing operation. Moreover, a speed of comparison can be improved compared to a speed of comparison for performing a serial sensing operation. Hence, multiple bits of data stored by the MLC can be read in an area and time efficient manner.

Referring now toFIG. 5, an example block diagram of a computing system500is shown, in accordance with some embodiments of the disclosure. The computing system500may be used by a circuit or layout designer for integrated circuit design. A “circuit” as used herein is an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured for implementing a desired functionality. The computing system500includes a host device505associated with a memory device510. The host device505may be configured to receive input from one or more input devices515and provide output to one or more output devices520. The host device505may be configured to communicate with the memory device510, the input devices515, and the output devices520via appropriate interfaces525A,525B, and525C, respectively. The computing system500may be implemented in a variety of computing devices such as computers (e.g., desktop, laptop, servers, data centers, etc.), tablets, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and/or layout design using the host device505.

The input devices515may include any of a variety of input technologies such as a keyboard, stylus, touch screen, mouse, track ball, keypad, microphone, voice recognition, motion recognition, remote controllers, input ports, one or more buttons, dials, joysticks, and any other input peripheral that is associated with the host device505and that allows an external source, such as a user (e.g., a circuit or layout designer), to enter information (e.g., data) into the host device and send instructions to the host device. Similarly, the output devices520may include a variety of output technologies such as external memories, printers, speakers, displays, microphones, light emitting diodes, headphones, video devices, and any other output peripherals that are configured to receive information (e.g., data) from the host device505. The “data” that is either input into the host device505and/or output from the host device may include any of a variety of textual data, circuit data, signal data, semiconductor device data, graphical data, combinations thereof, or other types of analog and/or digital data that is suitable for processing using the computing system500.

The host device505includes or is associated with one or more processing units/processors, such as Central Processing Unit (“CPU”) cores530A-530N. The CPU cores530A-530N may be implemented as an Application Specific Integrated Circuit (“ASIC”), Field Programmable Gate Array (“FPGA”), or any other type of processing unit. Each of the CPU cores530A-530N may be configured to execute instructions for running one or more applications of the host device505. In some embodiments, the instructions and data to run the one or more applications may be stored within the memory device510. The host device505may also be configured to store the results of running the one or more applications within the memory device510. Thus, the host device505may be configured to request the memory device510to perform a variety of operations. For example, the host device505may request the memory device510to read data, write data, update or delete data, and/or perform management or other operations. One such application that the host device505may be configured to run may be a standard cell application535. The standard cell application535may be part of a computer aided design or electronic design automation software suite that may be used by a user of the host device505to use, create, or modify a standard cell of a circuit. In some embodiments, the instructions to execute or run the standard cell application535may be stored within the memory device510. The standard cell application535may be executed by one or more of the CPU cores530A-530N using the instructions associated with the standard cell application from the memory device510. In one example, the standard cell application535allows a user to utilize pre-generated schematic and/or layout designs of the memory device100or a portion of the memory device100to aid integrated circuit design. After the layout design of the integrated circuit is complete, multiples of the integrated circuit, for example, including the memory device100or a portion of the memory device100can be fabricated according to the layout design by a fabrication facility.

Referring still toFIG. 5, the memory device510includes a memory controller540that is configured to read data from or write data to a memory array545. The memory array545may include a variety of volatile and/or non-volatile memories. For example, in some embodiments, the memory array545may include NAND flash memory cores. In other embodiments, the memory array545may include NOR flash memory cores, Static Random Access Memory (SRAM) cores, Dynamic Random Access Memory (DRAM) cores, Magnetoresistive Random Access Memory (MRAM) cores, Phase Change Memory (PCM) cores, Resistive Random Access Memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores that are suitable for use within the memory array. The memories within the memory array545may be individually and independently controlled by the memory controller540. In other words, the memory controller540may be configured to communicate with each memory within the memory array545individually and independently. By communicating with the memory array545, the memory controller540may be configured to read data from or write data to the memory array in response to instructions received from the host device505. Although shown as being part of the memory device510, in some embodiments, the memory controller540may be part of the host device505or part of another component of the computing system500and associated with the memory device. The memory controller540may be implemented as a logic circuit in either software, hardware, firmware, or combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller540may be configured to retrieve the instructions associated with the standard cell application535stored in the memory array545of the memory device510upon receiving a request from the host device505.

It is to be understood that only some components of the computing system500are shown and described inFIG. 5. However, the computing system500may include other components such as various batteries and power sources, networking interfaces, routers, switches, external memory systems, controllers, etc. Generally speaking, the computing system500may include any of a variety of hardware, software, and/or firmware components that are needed or considered desirable in performing the functions described herein. Similarly, the host device505, the input devices515, the output devices520, and the memory device510including the memory controller540and the memory array545may include other hardware, software, and/or firmware components that are considered necessary or desirable in performing the functions described herein.

One aspect of this description relates to a memory device. In some embodiments, the memory device includes a multi-level cell storing multiple bits of data. In some embodiments, the memory device includes a sensing device coupled to the multi-level cell. In some embodiments, the sensing device includes a first sense amplifier having a first input port coupled to the multi-level cell. In some embodiments, the sensing device includes a first multiplexer coupled to a second input port of the first sense amplifier. In some embodiments, the sensing device includes a second sense amplifier having a first input port coupled to the multi-level cell. In some embodiments, the method sensing device includes a second multiplexer coupled to a second input port of the second sense amplifier.

One aspect of this description relates to a memory device. In some embodiments, the memory device includes a multi-level cell storing multiple bits of data. In some embodiments, the memory device includes a sensing device coupled to the multi-level cell. In some embodiments, the sensing device includes a set of sense amplifiers, each of the set of sense amplifiers including a first input port and a second input port, the first input port coupled to the multi-level cell. In some embodiments, the sensing device includes a set of reference circuits, and a set of multiplexers. Each of the set of multiplexers may be coupled between the second input port of a corresponding one of the set of sense amplifiers and a corresponding subset of the set of reference circuits.

One aspect of this description relates to a method of reading data stored by a multi-level cell. In some embodiments, the method includes selecting, a first reference circuit from a first set of reference circuits. In some embodiments, the method includes selecting a second reference circuit from a second set of reference circuits. In some embodiments, the method includes determining one or more bits of multiple bits of data stored by a multi-level cell, based at least in part on the first reference circuit and the second reference circuit. In some embodiments, the method includes selecting a third reference circuit from the first set of reference circuits, according to the determined one or more bits. In some embodiments, the method includes selecting a fourth reference circuit from the second set of reference circuits, according to the determined one or more bits. In some embodiments, the method includes determining additional one or more bits of the multiple bits of data stored by the multi-level cell, based at least in part on the third reference circuit and the fourth reference circuit.