Methods and apparatus for reducing discrete power spectral density components of signals transmitted in wideband communications systems

Methods and apparatus for reducing discrete power spectral density (PSD) components of wideband signals transmitting blocks of data are disclosed. Discrete components are reduced by acquiring N symbols of pseudo-random data, each symbol having K bits; selecting one bit from each of the acquired symbols to generate N selected bits; selectively inverting a respective element in one of the data blocks responsive to the selected bits; acquiring one or more bits of pseudo-random data to replace a corresponding one or more respective bits of the acquired N symbols of pseudo-random data; and repeating for successive blocks of data.

FIELD OF THE INVENTION

The present invention relates to wideband communication systems and, more particularly, to methods and apparatus for reducing discrete power spectral density component of signals transmitted in wideband communication systems such as ultra wideband (UWB) communication systems.

BACKGROUND OF THE INVENTION

Ultra wideband (UWB) technology uses base-band pulses of very short duration to spread the energy of transmitted signals very thinly from near zero to several GHz. UWB technology is presently in use In military applications and techniques for generating UWB signals are well known. Commercial applications will soon become possible due to a recent decision announced by the Federal Communications Commission (FCC) that permits the marketing and operation of consumer products incorporating UWB technology.

The key motivation for the FCC's decision to allow commercial applications is that no new communication spectrum is required for UWB transmissions because, when they are properly configured, UWB signals can coexist with other application signals in the same spectrum with negligible mutual interference. The FCC has specified emission limits for UWB applications to prevent Interference with other communication systems.

The emission profile of a UWB signal can be determined by examining Its power spectral density (PSD). Characterization of the PSD of a “Time-Hopping Spread Spectrum” signaling scheme in the presence of random timing jitter using a stochastic approach is disclosed in an article by Moe et al. titled “On the Power Spectral Density of Digital Pulse Streams Generated by M-ary Cyclostationary Sequences In the Presence of Stationary Timing Jitter.” See IEEE Tran. on Comm., Vol. 46, no. 9, pp. 1135-1145, September 1998. According to this article, the power spectra of UWB signals consists of continuous and discrete components. Discrete components create peaks in the PSD that may exceed the FCC emission limits even when the continuous components are well below these limits.

There is an ever present desire to increase the communication distances of communication systems. One way to Increase communication distance is to increase the power used for transmissions. To increase transmission power while still conforming to the FCC emission limits for UWB signals, it is desirable to reduce the discrete components so that overall power can be increased while still conforming to the FCC emission limits for UWB signals. In traditional communication systems, scramblers are commonly used to reduce discrete components (i.e., data whitening). These scramblers, however, are insufficient for reducing discrete PSD components In UWB communication systems, e.g., due to their high pulse repetition frequency (PRF), i.e., about 100 Mbps to 500 Mbps, and their time division multiple access (TDMA) frame structure. Accordingly, improved methods and apparatus for reducing discrete PSD components of UWB signals are needed. The present invention fulfills this need among others.

SUMMARY OF THE INVENTION

The present Invention is embodied in methods and apparatus for reducing discrete power spectral density (PSD) components of wideband signals transmitting blocks of data. Discrete components are reduced by acquiring N symbols of pseudo-random data, each symbol having K bits; selecting one bit from each of the acquired symbols to generate N selected bits; selectively inverting a respective element In one of the data blocks responsive to the selected bits; acquiring one or more bits of pseudo-random data to replace a corresponding one or more respective bits of the acquired N symbols of pseudo-random data; and repeating for successive blocks of data.

In addition, the present invention is embodied In methods and apparatus for receiving these selectively inverted wideband signal and In pseudo-random number generators.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a conceptual representation of an exemplary wideband communication system100in accordance with the present invention. Functions of one or more blocks within the illustrated communication system100can be performed by the same piece of hardware or module of software. It should be understood that embodiments of the present Invention may be implemented in hardware, software, or a combination thereof. In such embodiments, the various component and steps described below may be implemented in hardware and/or software.

In general overview, a transmitting apparatus102for transmitting source data Inverts and, optionally, scrambles the source data prior to transmission to reduce the discrete power spectral density (PSD) components of the transmitted source data. The transmitting apparatus102employs improved inverting techniques that offer improved randomization of the source data utilizing relatively short pseudo-random sequences, thereby reducing the discrete PSD components and facilitating synchronization. A receiving apparatus104receives the transmitted source data and reverses the inversion and optional scrambling to recover the original source data. The source data Includes blocks of data made up of elements. As used herein, the term elements may be used to represent frames of data within the blocks, data symbols within the frames, and/or bits within the data symbols. Each data symbol may include one or more bits.

The components of the transmitting apparatus102and the receiving apparatus104are now described in detail. In an exemplary embodiment, the source data is applied to an optional scrambler106that is configured to scramble the source data. The scrambler106scrambles elements within the blocks of source data according to a predetermined scrambling function. The scrambler106may scramble all of the source data or may scramble a portion of the source data such as just frames within the source data containing repetitive data, e.g., synchronization words. In an alternative exemplary embodiment, the source data is not scrambled and the optional scrambler106can be omitted.

In an exemplary embodiment, the scrambler106scrambles at least a portion of the source data using scrambling words. A table of eight exemplary scrambling words (numbered 0-7) are depicted In Table 1.

TABLE 10:00001:00012:00103:00114:01005:01016:01107:0111
The exemplary scrambling words may be logically combined with portions of the source data, e.g., using an XOR logic circuit (not shown), to scramble the source data, which is described in further detail below.

In an alternative exemplary embodiment, a scrambler such as those described in proposals to the Institute of Electrical and Electronic Engineer's (IEEE) standard IEEE 802.15.3a is employed to scramble the source data. The proposed scrambler uses a 15-bit linear feedback shift register (LFSR) to generate a pseudo-random binary sequence (PRBS) for the scrambler. At the beginning of each frame, the LFSR is loaded with predefined values (seeds), which are referred to herein as initial settings. Four seeds indexed with a two bit identifier (b1, b0) are defined for selection as the initial setting, which is illustrated in Table 2.

TABLE 2Seed identifier (b1, b0)Seed value (x14. . . x0)0, 00011 1111 1111 1110, 10111 1111 1111 1111, 01011 1111 1111 1111, 11111 1111 1111 111
The seed values used for scrambling may be selected from the seed set using the two bit identifier. The selected seed is then logically combined with the source data, e.g., using an XOR logic circuit (not shown), to scramble the source data. The two bit identifier may be transmitted in a packet along with the source data for use in the receiver104to initialize the descrambler132.

As depicted in Table 2, the seed values are highly correlated (i.e., only the first two bits of each seed value are unique) and, thus, the pseudo random sequences generated are highly correlated, resulting in line spectra due to the lack of adequate randomness. The inventors have recognized that superior results in the suppression of discrete PSD components may be obtained through the use of uncorrelated seeds. Table 3 depicts an exemplary seed set for use with the scrambler106.

TABLE 3Seed identifier (b1, b0)Seed value (x27. . . x0)0, 00100 1100 0000 0101 0001 0000 11100, 11011 1000 0101 1011 1001 1101 10101, 00101 1111 1101 0010 1000 0001 10011, 10000 1111 0010 1111 0011 0111 1111
In Table 3, there are four seed values and each seed value includes 28 bits. The seed values are substantially uncorrelated and, therefore, pseudo random sequences generated using these seed values are substantially uncorrelated. The seed set shown in Table 3 is for illustration only and seed sets with seeds having different seed values, more or less seeds, and more or less bits per seed may be employed. Those of skill in the art will understand how to generate suitable uncorrelated seed values for use in a seed set from the description herein.

An inverter108inverts elements within the blocks of the source data according to a predetermined inverting function. In an exemplary embodiment, the inverter108is coupled to a pseudo-random number generator110that generates a number (N) of symbols having evenly distributed binary numbers where the evenly distributed binary numbers are periodically updated, e.g., prior to each frame of source data. The inverter108may be a multiplexer (not shown) that passes the source data or the inverse of the source data, e.g., as inverted by an inverter circuit (not shown), on an element by element basis responsive to the select bits. As described in further detail below, the inverter108is configured to receive one bit from each of the symbols of the pseudo-random number generator110to create select bits and to invert elements within the blocks of source data responsive to the select bits.

In an exemplary embodiment, each register within the shift register202is examined after each shift. A condition where all of the bits in the shift register202have a value of “0” Is illegal when an XOR gate is in the feedback loop203because the pseudo-random number generator200is not able to leave this state. Similarly a value of all “1”s is illegal if an NXOR gate is in the feedback loop203. If an illegal condition occurs, at least one bit within the shift register202is inverted.

The Illustrated shift register202can be divided into a predefined number (N) of designated symbol areas. For example, if a symbol is defined as 4 bits, the shift register202is effectively divided into 7 designated symbol areas, i.e., bit registers1-4,5-8,9-12,13-16,17-20,21-24, and25-28. One bit from each designated symbol area is coupled to the inverter, e.g., via another shift register (not shown), for use in inverting elements of the source data. For example, the inverter may invert a bit of the source data for each select bit from the N symbols generated by the pseudo-random number generator (seeFIG. 9, with select bits indicated by an up arrow extending from the bits), each bit within a symbol for each select bit (seeFIG. 10), or each bit within a frame for each select bit. The select bits may be in the same relative position in each symbol as shown inFIGS. 9 and 10or in different (random) positions as shown InFIG. 11. The designated symbol areas may each include a uniform number of bit registers or different numbers of bit registers. Various alternative embodiments will be readily apparent to those of skill in the art.

Prior to generating pseudo-random numbers, the shift register202within the LFSR is initialized with bit values (e.g., a bit stream of evenly distributed ones “1” and zeroes “0”). The shift register202may be reinitialized with new bit values at predefined intervals such as after each symbol, frame (e.g., prior to each synchronization word), or block of data. Suitable methods for initializing the shift register202are described below.

The operation on the shift register202within the pseudo-random number generator200for one update is shown inFIGS. 2A,2B, and2C. The shift register202includes a bit string (referred to herein as sign_ctl_array). First, individual elements in the source data are associated with one bit from a designated symbol area of the shift register202, as shown inFIG. 2A. Next, the sign_ctl_array in the shift register is shifted to the right (i.e. toward less significant bit positions) by L bits (wherein L is one or more bits), as shown inFIG. 2B. As a last step, L new random bits (e.g., 3 random bits) are generated and inserted into the first L bits of the shift register202, as shown inFIG. 2C.

Referring back toFIG. 1, in the illustrated embodiment, the inverter108is positioned after the scrambler104such that the inverter108inverts the source data after scrambling. In an alternative exemplary embodiments, the scrambler106may be positioned after the inverter108with the inverter108inverting portions of the source data prior to scrambling by the scrambler106.

The transmitter114is coupled to a pulse generator116that generates a wideband pulse signal made up of a series of signal pulses such as ultra wideband (UWB) signal pulses. The transmitter114modulates the source data in digital format onto the wideband pulse signal for transmission via an antenna108. The transmitter114may be a pulse modulator as shown or it may be a digital-to-analog converter (not shown) with a pulse shaping circuit (not shown), and may even be considered part of the antenna118.

FIG. 1Adepicts an alternative exemplary transmitting apparatus102a. The transmitting apparatus102ais similar to the transmitting apparatus102ofFIG. 1with the exception that the pulse generator116(FIG. 1) is replaced with a pulse generator116a(FIG. 1A) positioned between the scrambler106and an inverter108a. In this embodiment, the pulse generator116amodulates optionally scrambled digital source data onto wideband signal pulses to create an analog signal. The inverter108athen inverts the source data in the analog domain for transmission by the transmitter114a. The transmitter114amay be pulse shaping circuitry, a connector simply coupling the Inverter108ato the antenna118, or may even be considered part of the antenna118. A suitable inverter108afor inverting the source data in the analog domain will be understood by those of skill in the art from the description herein. Further, various alternative exemplary embodiments for a transmitting apparatus In accordance with the present invention will be understood by those of skill in the art from the description of the transmitting apparatus102and102aofFIGS. 1 and 1A, respectively.

Referring back toFIG. 1, a receiver120within the receiving apparatus104receives the inverted and, optionally, scrambled wideband pulse signal through another antenna122. A correlator124within the receiver120correlates the received data to the pulse shape used by the transmitting apparatus102to identify pulses and convert them to digital pulses. In an exemplary embodiment, the correlator124is a matched filter correlator configured to identify and correlate incoming wideband pulses such as UWB pulses.

An inverter−1126reverses the inversion introduced to the source data by the inverter108according to a predefined inverting function that is based on the inverting function of the inverter108. In an exemplary embodiment, the inverter−1126is coupled to a pseudo-random number generator128that is substantially identical to the pseudo-random number generator110described in detail above (and, thus, Is not described in further detail here). The inverter−1126may be a multiplexer (not shown) which passes the source data or the inverse of the source data, e.g., as inverted by an inverter logic circuit (not shown), responsive to select bits generated by the pseudo-random number generator128.

The two pseudo-random number generators110and128generate identical bit-strings. In an exemplary embodiment, for synchronization, the generators110and128are configured to start at a common point when the first bit of a sequence is transmitted or received. In an alternative exemplary embodiment, Instead of generating a set of random numbers at each frame, a set of random numbers can be generated in advance and stored into an array. The same array is kept in the pseudo-random number generators110,128in both the transmitting apparatus102and the receiving apparatus104. A random number is generated as an index to the stored array and is transmitted for use in establishing synchronization between the transmitting apparatus102and the receiving apparatus104.

A synchronizer130synchronizes the received data for descrambling by an optional descrambler132. In an exemplary embodiment, the descrambler132, after synchronization, reverses the scrambling introduced by the scrambler106to yield the original source data. The descrambler132reverses the scrambling according to a predefined descrambling function that is based on the scrambling function used by the scrambler106. In the illustrated embodiment, the synchronizer130receives feedback from the descrambler132in synchronizing the scrambled source data. Further details regarding the synchronization of the scrambled source data are described below. In an alternative exemplary embodiment, where the scrambler106is omitted, the descrambler132may be omitted.

FIG. 3depicts a synchronizer300in accordance with an exemplary embodiment of the present invention for use as the synchronizer130inFIG. 1. The Illustrated synchronizer300is a four pattern synchronizer that is based on four seeds I-IV, which were used to scramble the source data. The first pattern S1includes the four seeds in sequential order from I-IV. The second pattern52includes the four seeds starting with IV followed by I, II, and III. The third pattern S3is III, IV, I, II and the fourth pattern S4is II, III, IV, I. The received sequence, r, is exclusively ORed, XOR, with each of the four patterns S1-S4using XOR logic circuits302a-d. Absolute value components (ABS)304a-dfind the absolute value of the resultant values produced by the XOR logic circuits302a-d. A maximum value circuit306then determines which patterns S1-S4produces the maximum absolute value when combined with the received sequence, r, and controls a multiplexer308such that the determined pattern is passed by the multiplexer308for use in descrambling the received sequence. In embodiments where the sync word is all one value, e.g., all ones (1's), and the inverter108(FIG. 1) Inverts the entire sync word on a random basis, the use of absolute value components304a-din the synchronizer300enables the detection of a valid sync word in the receive data prior to inversion by the inverter−1126(FIG. 1), e.g., during an Initial system channel access. The detected sync word may then serve as the basis for initializing the pseudo-random number generator128(FIG. 1).

In an alternative exemplary embodiment, where the scrambler106scrambles the source data using a LFSR initialized using seeds selected from an indexed seed set, the synchronizer130(FIG. 1) may use an index value received In the transmitted data to synchronize the descrambler132. In accordance with this embodiment, the descrambler132may include an LFSR (not shown) and a seed set that correspond to the LFSR and seed set, respectively, in the scrambler106. The synchronizer130identifies the index value received in the transmitted data and passes it to the descrambler132, which selects the appropriate seed to initialize the descrambler132.

Referring back toFIG. 1, in the illustrated embodiment, the descrambler132is positioned after the inverter−1126such that the source data is inverted and then descrambled. In an alternative embodiment, the inverter−1126may be positioned after the descrambler132with the inversion and descrambling performed in the opposite order.

FIG. 4depicts a flow chart400of exemplary transmitting steps for reducing discrete PSD components in a wideband communication system such as a UWB communication system. The steps of flow chart400are described with reference to the components ofFIGS. 1 and 2.

At block402, the optional scrambler106scrambles the source data. The source data may include frames of data including payload data and non-payload data, e.g., synchronization data. In an exemplary embodiment, the source data is scrambled according to a predetermined scrambling function, e.g., using scrambling words, which are described in further detail below. The synchronization data may be all one symbol such as all positive (+) 1's. In an alternative exemplary embodiment, the source data is not scrambled and block402can be omitted.

At block404, the shift register202initially acquires N symbols of pseudo-random data (i.e., bit string sign_ctl_array) during an initialization. The N symbols of pseudo-random data received during initialization may be supplied from a register or from a pseudo-random number generator, which is described in further detail below.

At block406, the inverter108selects one bit from each of the acquired symbols of pseudo-random data to generate N select bits. The select bits may be selected by transferring select bits from cells within designated symbol areas of the shift register202into a register (not shown) associated with the inverter108.

At block408, the inverter108inverts respective elements in one of the data blocks responsive to the selected bits. In an exemplary embodiment, the inverter108inverts individual bits, each bit within a symbol, or each bit within a frame responsive to each bit of the selected bits. For example, if there are 7 select bits and the inverter108inverts each bit within a symbol responsive to each bit, the first select bit will determine whether each bit within a first symbol is inverted or not, the second select bit will determine whether each bit within a second symbol is inverted or not, etc. Likewise, if the inverter108inverts each bit within a frame, the first bit will determine whether each bit within a first frame is inverted or not, the second bit will determine whether each bit within a second frame is inverted or not, etc.

In the illustrated flow chart400, source data is first scrambled (block402) and then inverted (block408). It will be understood by those of skill in the art that in other embodiments the source data may first be inverted and then scrambled, in which case the step of block402occur after the steps of blocks404through412.

At block410, the inverted and, optionally, scrambled source data is prepared for transmission. The source data may be prepared for transmission by using it to modulate pulses provided by a pulse generator, such as pulse generator116. At block412, the transmitter114transmits the inverted and, optionally, scrambled source data from the antenna118.

At block414, a decision to repeat blocks406-412is made responsive to the presence of additional source data for transmission. If additional source data is present for transmission, processing proceeds to block416to acquire additional pseudo-random data and the steps in blocks406through412are repeated. If all source data for transmission has been selectively inverted, processing ends at block418.

At block416, the shift register202acquires one or more bits of pseudo-random data to replace a corresponding one or more respective bits of the acquired symbols of pseudo-random data. In an exemplary embodiment, the shift register202shifts out one or more bits (such as a single data bit, a symbol of data bits, or one data bit for each select bit) after each frame or block of source data has been inverted. A corresponding number of data bits are concurrently shifted into the shift register202to replace the shifted out bits. The new pseudo-random data may be supplied by the logic circuit204to the shift register202responsive to one or more bit values in intermediate registers within the shift register202.

FIG. 5depicts a flow chart500of exemplary receiving steps for receiving wideband signals that are inverted and, optionally, scrambled in accordance with the present invention. The steps of flow chart500are described with reference to the components ofFIGS. 1,2, and3.

At block502, the receiver120within the receiving apparatus104receives the inverted and, optionally, scrambled source data through the antenna122and, at block504, the correlator124within the receiver120correlates the source data to identify the wideband pulse signal carrying the source data. At block506, the synchronizer130synchronizes the received scrambled source data for reversal of the scrambling applied by the scrambler106. In an exemplary embodiment, the synchronizer130synchronizes the scrambled and inverted source data based on feedback from the descrambler132.

At block508, the inverter−1126reverses the inversion introduced by the inverter108responsive to a pseudo-random number sequence or stream generated by the pseudo-random number generator128. In an exemplary embodiment, the pseudo-random number generator128is configured to start when a designated bit is received, e.g., a first bit of a received sequence. At block510, the descrambler132reverses the scramble introduced by the scrambler106to derive the original source data. In embodiments where the source data is not scrambled the step in block510is omitted.

In the illustrated flow chart500, source data is first inverted (block508) by the inverter−1126and then descrambled (block510) by the descrambler132. It will be understood by those of skill in the art that in alternative exemplary embodiments, the source data may first be descrambled and then inverted, in which case the step of block508occurs after the step of block510.

Initialization schemes for the exemplary pseudo-random number generator200ofFIG. 2are now described.FIG. 6depicts the pseudo-random number generator200described above with reference toFIG. 2and a random numbers register600for supplying random numbers to the shift register202of the pseudo-random number generator200for initialization. The register600stores one or more sequences of pseudo-random numbers of use in initializing the pseudo-random number generator200. In an exemplary embodiment, the sequences of pseudo-random numbers are uncorrelated with respect to one another and each pseudo-random number includes one bit value for each cell of the shift register202within the pseudo-random number generator200. For example, if a 28 bit shift register202is employed, each seed value has 28 bits.

FIG. 7depicts the pseudo-random number generator200described above with reference toFIG. 2and a second pseudo-random number generator700such as a second LFSR (with the feedback loop and logic circuitry of the LFSR omitted to simplify illustration and facilitate discussion). The bit registers of the second pseudo-random number generator700is coupled to bit registers of the shift register202within the pseudo-random number generator200to provide random bits for Initialization. In an exemplary embodiment, the second pseudo-random number generator700and the pseudo-random number generator200may operate in a similar manner, but may use different bits or a different logic circuit in the feedback loop. In an alternative exemplary embodiment, the second pseudo-random number generator700may be a random or pseudo-random number generator that is different than the pseudo-random number generator200.

In an exemplary embodiment, at the beginning of each frame, a bit string sign_ctl_orig generated in the second pseudo-random number generator700is loaded as an initial setting for bit string sign_ctl_array in the first pseudo-random number generator200. The bit string sign_ctl_array is updated for every bit that is transmitted and the bit string sign_ctl_orig is updated every frame. This operation is described by the following sequence of four steps:1. At the beginning of each frame, right shift bit string sign_ctl_orig for n bits;2. Copy sign_ctl_orig to sign_ctl_array;3. Use sign_ctl_array to generate the sign control bits;4. Go to step 1 for next frame.

It can be seen that the original state of bit string sign_ctl_array at frame n+1 is an n-bit delay of bit string sign_ctl_array at frame n.

It is noted from the above operation that, because bit string sign_ctl_orig specifies the initial state of bit string sign_ctl_array at the beginning of each frame, only bit string sign_ctl_orig needs to be synchronized in order to synchronize a receiving apparatus104to its transmitting apparatus102.

FIG. 8depicts another exemplary architecture for initializing the pseudo-random number generator200that exhibits increased randomness. This architecture employs a second pseudo-random number generator800, a third pseudo-random number generator802, and logic circuits804. The second and third pseudo-random number generators may be LFSRs (with the feedback loop and logic circuitry of the LFSR omitted to simplify illustration and facilitate discussion) and the logic circuits may be XOR or XNOR gates. The logic circuits404combine respective bits of the second and third pseudo-random number generators800and802to generate the initializing values for the first pseudo-random number generator200.

In an exemplary embodiment, at the beginning of each frame, bit strings sign_ctl_orig1and sign_ctl_orig2generated, respectively, by the second and third pseudo-random number generators800and802are combined to form an initial setting of the bit string sign_ctl_array of the first pseudo-random number generator200. This operation is described by the following sequence of 5 steps.1. At the beginning of each frame, right shift sign_ctl_orig1n1bits and sign_ctl_orig2n2bits;2. Form, in the XOR gates804, the exclusive OR of the respective bits of sign_ctl_orig1and sign_ctl_orig2to form an input value, sign_ctl_orig, i.e., sign_ctl_orig=sign_ctl_orig1⊕sign_ctl_orig2;3. Copy sign_ctl_orig to sign_ctl_array;4. Use sign_ctl_array to generate select bits for inversion;5. Go to step 1 for next frame.

Synchronization of the pseudo-random number generator202with the above initialization schemes is now described. In an exemplary embodiment, there are two synchronization phases. The two synchronization phases include an initial system channel access phase and an Initial traffic channel access phase. During the Initial system channel access phase, the receiving apparatus102has no knowledge of the states of the pseudo-random number generator200in the transmitting apparatus102. Thereafter, during the initial traffic channel access phase, the receiving apparatus102has some knowledge of the states of the pseudo-random number generator200in the transmitting apparatus102, thereby allowing a sequence number to be used for synchronization.

For initial channel system access, different methods can be used for the different pseudo-random number generator with Initialization described above with reference toFIGS. 6-9.

Initial channel access for the method described with reference toFIG. 6is obtained using a set of random numbers that are generated in advance and stored in an array. Identical arrays are stored in the pseudo-random number generators110,128in both the transmitting apparatus102and the receiving apparatus104. A random number is generated as an index to the stored array and is transmitted for use in establishing synchronization between the transmitting apparatus102and the receiving apparatus104.

Initial channel access for the method described with reference toFIG. 7is obtained by sending the states of the bit registers of the second pseudo-random number generator700from the transmitting apparatus102to the receiving apparatus104. For registers with length of n, n bits of data are sent. If, however, fewer bits are reserved for register states to be transmitted (e.g., only 4 bits of data), the status of only registers1-4only may be sent with the data. In this example, after 7 frames (i.e., 28 bits), the entire bit string sign_ctl_array100can be obtained. After initial synchronization, data in this field may be used to check whether bit string sign_ctl_orig remains synchronized between respective transmitting apparatus102and receiving apparatus104.

Initial channel access for the method described with reference toFIG. 8is similar to that for the method ofFIG. 7except that twice as much data is sent because bits from two registers of two pseudo-random number generators800and802are transmitted (assuming each pseudo-random number generator800and802has a shift register with the same number of bits as the shift register of the pseudo-random number generator700).

Additional implementation details are now provided for the exemplary communication system100described above with reference toFIGS. 1,2,3,4, and5. In an exemplary embodiment, a scrambler array, SA, including M distinct symbols, each symbol consisting of n pulses is defined. The symbols may be, for example, binary representations of the numbers 0 to M−1. The complete procedure for a symbol-based operation is now described.1. Set the initial value of m (1≦m≦M) and set the initial value of sign_tx_array.2. Set m=m+1 modulo (mod) M.3. Use the m as an Index to the scrambler array SA to obtain one symbol;4. Go to 2 until N symbols have been obtained. These N symbols are used to construct a new scramble word SW shown in equation 1:
SW=[SA(m), SA(m+1 modM), SA(m+2 modM), . . . , SA(m+(N−1)modM)]  (1)5. Apply XOR operation on symbols of the source data for transmission and the generated SW to form a new block of data SSW1as shown in equation 2:
SSW1(n)=symbol(n)⊕SW(n) n=1, . . . , N  (2)6. Obtain N evenly distributed binary numbers cn⊂(1, −1) from the sign_tx_array and use these numbers to generate a new block of data SSW2, as shown in equation (3):
SSW2(n)=SSW1(n)⊕sign—tx—array(n*K) n=1, . . . , N(3)7. Use SSW2for transmission.8. Update sign_tx_array.9. Go to 2 for the next frame.

The starting index of the next symbols in SW may be calculated as shown In equation 4:
m=m+NmodM(4)

At the receiver, the following operation is performed on the received sequence SSW2to synchronize the receiver to the transmitter and to recover the original symbols in the symbol based operation:1. If this is the initial acquisition, initial value of m and random sequence generator are synchronized so that sign_tx_array(n)=sign rx_array(n).2. Obtain N evenly distributed binary number from sign_rx_array and use these numbers to produce data SSW1as shown in equation 5:
SSW1(n)=SSW2(n)⊕sign—rx—array(n*K)n=1, . . . , N  (5)3. Form SW and use it to de-scramble SSW1to get original data Sy{circumflex over (m)}bol(n) as shown in equations 6 and 7;
SW=[SA(m), SA(m+1 modM), SA(m+2modM), . . . , SA(m+(N−1)modM)]  (6)
Sy{circumflex over (m)}bol(n)=SSW1(n)⊕SW(n)  (7)4. Calculate the index of m for the next word, m=m+N mod M;5. Update sign_rx_array;6. Go to step 2 for the next frame.

If sign_tx_array and sign_rx_array are synchronized, then equations 8, 9, and 10 are valid.

Although the components of the present invention have been described in terms of specific components, it is contemplated that one or more of the components may be implemented in software running on a computer. In this embodiment, one or more of the functions of the various components may be implemented in software that controls the computer. This software may be embodied in a computer readable carrier, for example, a magnetic or optical disk, a memory-card or an audio frequency, radio-frequency or optical carrier wave.