LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

A light-emitting device includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. The first substrate edge region has a first uneven toothed surface or an even flat surface. The second substrate edge regions are formed with second uneven toothed surfaces which have a height greater than a height of the first even toothed surface, or the even flat surface.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Invention Patent Application No. 202211355566.7, filed on Nov. 1, 2022, and incorporated by reference herein in its entirety.

FIELD

The disclosure relates to a semiconductor device, and more particularly to a light-emitting device and a method for manufacturing the same.

BACKGROUND

Light-emitting diode is a solid light-emitting device that converts electrical energy into light energy. For the light-emitting diode, the light emitting area is an important factor affecting the luminous brightness. In general, each wafer is one substrate for epitaxial growth. Referring toFIGS.1ato2c, in a conventional method for manufacturing a light-emitting diode, an N-type semiconductor layer201, an active layer202, and a P-type semiconductor layer203are successively formed on a wafer substrate100in such order, followed by etching the P-type semiconductor layer203and the active layer202from a surface of the P-type semiconductor layer203so as to expose a part of the N-type semiconductor layer201, thereby forming a mesa structure. Subsequently, the wafer substrate100is ground to reduce the thickness thereof, and the exposed part of the N-type semiconductor layer201and a part of the wafer substrate100immediately beneath the exposed part of the N-type semiconductor layer201are diced to singulate LED chips. However, before dicing, the wafer substrate has a large surface area, and after the wafer substrate is thinned, the wafer substrate becomes thin; the N-type semiconductor layer201is a continuous layer which is thick. Therefore, the wafer substrate100can be subjected to a large stress and is prone to warpage and crack during dicing.

SUMMARY

Therefore, an object of the disclosure is to provide a light-emitting device and method for manufacturing the same that can alleviate at least one of the drawbacks of the prior art.

According to one aspect of the disclosure, the method includes the steps of:(a) providing a substrate having an upper surface which is patterned, and forming an epitaxial multilayer stack on the upper surface of the substrate, the epitaxial multilayer stack including a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order;(b) etching, from an upper surface of the second semiconductor layer, the second semiconductor layer and the active layer until the first semiconductor layer is exposed so as to form multiple mesa structures, each of which includes a mesa top defined by the upper surface of the second semiconductor layer, a mesa sidewall portion extending downwardly from the mesa top and formed by lateral edge portions of the second semiconductor layer and of the active layer, and a mesa bottom formed by an exposed part of the first semiconductor layer surrounding the mesa sidewall portion; and(c) etching boundary regions of the mesa structures until the substrate is exposed so as to form dicing line regions on the substrate, each of the boundary regions of the mesa structures including a first boundary region formed by the mesa bottom, and a second boundary region that extends from the mesa top to a bottom surface of the first semiconductor layer and that includes the mesa sidewall portion, and a portion of the first semiconductor layer located beneath the mesa sidewall portion and adjoining the mesa bottom, the dicing line regions being formed after the first and second boundary regions of the mesa structures are etched and removed from the substrate.

According to another aspect of the disclosure, the light-emitting device includes a substrate and an epitaxial structure formed on an upper surface of the substrate. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. The first substrate edge region has a first uneven toothed surface or an even flat surface. The second substrate edge regions are formed with second uneven toothed surfaces which have a height greater than a height of the first even toothed surface, or the even flat surface.

According to yet another aspect of the disclosure, the light-emitting device includes a substrate and an epitaxial structure formed on an upper surface of the substrate. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. A thickness of the substrate in the first substrate edge region is smaller than a thickness of the substrate in the second substrate edge region.

DETAILED DESCRIPTION

First Embodiment

Referring toFIGS.3ato3d, a method for manufacturing a light-emitting device according to the present disclosure is shown; the method includes following steps S101to S104.

In step S101, as shown inFIG.3a, a substrate100having an upper surface which is patterned is provided, and an epitaxial multilayer stack200′ is formed on the upper surface of the substrate100. The substrate100may be a sapphire substrate, and has an upper surface and a lower surface opposite to the upper surface. The pattern formed on the upper surface of the substrate may be made of aluminum oxide, has a height ranging from 1.5 μm to 3 μm, and has a width ranging from 2 μm to 4 μm. The epitaxial multilayer stack200′ includes a first semiconductor layer201, an active layer202, and a second semiconductor layer203which are disposed on the upper surface of the substrate100in such order. The first semiconductor layer201may be an n-type semiconductor layer, the active layer202may be a quantum well layer, and the second semiconductor layer203may be a p-type semiconductor layer. The first semiconductor layer201, the active layer202, and the second semiconductor layer203may be made of GaN-based materials, and may be formed by deposition.

In this embodiment, after the epitaxial multilayer stack200′ is formed on the substrate100, a conductive layer (not shown) is formed on a surface of the second semiconductor layer203. The conductive layer may be made of indium tin oxide, nickel gold, or the like, and may be etched in a subsequent step.

In step S102, as shown inFIG.3b, the second semiconductor layer203and the active layer202are etched from an upper surface of the second semiconductor layer203until the first semiconductor layer201is exposed so as to form multiple mesa structures (M). Each of the mesa structures (M) includes a mesa top (M1) which is defined by the upper surface of the second semiconductor layer203, a mesa sidewall portion (M2) which extends downwardly from the mesa top (M1) and is formed by lateral edge portions of the second semiconductor layer203and of the active layer202, and a mesa bottom (M3) which is formed by an exposed part of the first semiconductor layer201and which loops around the mesa sidewall portion (M2). The mesa bottom (M3) is flush with a lower surface of the active layer202or lower than the lower surface of the active layer202.

Referring toFIG.3b, in particular, after a part of the conductive layer (not shown) is etched to expose a part of the upper surface of the second semiconductor layer203, the second semiconductor layer203and the active layer202are successively etched from the exposed part of the upper surface of the second semiconductor layer203, until the upper surface of the first semiconductor layer201is exposed, thereby forming multiple mesa structures (M). The exposed upper surface of the first semiconductor layer201forms the mesa bottoms (M3) each of which is formed at a boundary region of each of the mesa structures (M). In some embodiments, besides the mesa bottoms (M3) located at the boundary region of each mesa structure (M), the exposed upper surface of the first semiconductor layer201also forms internal mesas (not shown) located within an area surrounded by the boundary region of each mesa structure (M). N type electrodes may be formed on the mesa bottom (M3). In an example, one or more N type electrodes are formed on a part of the mesa bottom (M3). In another example, one or more N type electrodes are formed at the internal mesas (not shown), and no electrode is formed at the mesa bottom (M3).

In step S103, as shown inFIGS.3bto3d, boundary regions of the mesa structures (M) are etched until the substrate100is exposed so as to form dicing line regions300(only one is shown) on the substrate100, each of which is formed between two adjacent ones of the mesa structures (M). Each of the boundary regions of the mesa structures (M) includes a first boundary region which is formed by the mesa bottom (M3), and a second boundary region which extends from the mesa top (M1) to a bottom surface of the first semiconductor layer201and which includes the mesa sidewall portion (M2) and a portion of the first semiconductor layer201located beneath the mesa sidewall portion (M2) and adjoining the mesa bottom (M3). The dicing line regions300are formed after the first and second boundary regions of the mesa structure (M) are etched and removed from the substrate100. Each of the dicing line regions300has a width greater than a width of the mesa bottom (M3).

In this embodiment, the etching in step S103is inductively coupled plasma (ICP) etching, where an ICP etching gas is used for etching the mesa structure (M).

Referring toFIGS.3bto3d, in this embodiments, the first and second boundary regions of the mesa structure (M) are simultaneously etched and removed until the substrate100is exposed, such that the dicing line region300has a width greater than a width of the mesa bottom (M3). Each of the dicing line regions300is situated between two adjacent ones of the mesa structures (M), and includes a first dicing line region301, and two second dicing line regions302on two opposite sides of the first dicing line region301. The first dicing line region301is formed on an exposed part of the substrate100from which the first boundary regions of two adjacent ones of the mesa structures (M) are removed, and the second dicing line regions302are respectively formed on other exposed parts of the substrate100from which the second boundary regions of two adjacent ones of the mesa structures (M) are removed. As shown inFIGS.3cand3d, the other exposed parts of the substrate100where the second dicing line regions302are formed has a thickness (d2) greater than a thickness (d1) of the exposed part of the substrate100where the first dicing line region301is formed. It is noticed that, since the substrate100may has uneven toothed surfaces103,104which will be described below, the above-stated thicknesses (D1, D2) of the substrate100are distances between the lower surface the substrate100and tops of the uneven toothed surfaces103,104, respectively. For each of the mesa structures (M), since the thickness of the first boundary region is lower than the thickness of each second boundary region, after etching of the first boundary region is completed, the ICP etching gas still continues its etching activity until the second boundary regions are cleared from the substrate100, and stops etching at the upper surface of the substrate100.

Referring toFIGS.3aand3b, in this embodiment, the substrate100is a patterned substrate, and includes a flat base layer101and an uneven toothed structure layer102which is formed on an even surface of the flat base layer101and which includes a plurality of protrusions spaced apart from each other. The mesa structures (M) are formed on a surface of the uneven toothed structure layer102of the substrate100.

Referring toFIG.3c, in an example of the embodiment, in step S103, the first and second boundary regions of the mesa structures (M) are simultaneously etched such that an exposed part of the substrate100from which the first boundary regions of two adjacent ones of the mesa structures (M) are removed is formed with a first uneven toothed surface103, and other exposed parts of the substrate100, from which the second boundary regions of two adjacent ones of the mesa structures (M) are removed, are respectively formed with second uneven toothed surfaces104. The first and second uneven toothed surfaces103,104are formed after etching is performed at the surface of the uneven toothed structure layer102. The exposed part of the substrate100where the first uneven toothed surface103is formed has the first dicing line region301thereon, and the other exposed parts of the substrate100where the second uneven toothed surfaces104are formed have the second dicing line regions302thereon. The first uneven toothed surface103has a height lower than a height of the second uneven toothed surfaces104. In particular, for each of the mesa structures (M), the first boundary region is etched from the mesa bottom (M3); the etching of the second boundary region starts from the mesa top (M1) and is conducted simultaneously with the etching of the first boundary region, so that the height of the first uneven toothed surface103formed in the first dicing line region301is lower than the height of the second uneven toothed surfaces104. In some embodiments, the second uneven toothed surfaces104of the substrate100may be formed to have a height lower than an original height of the uneven toothed structure layer102.

Referring toFIG.3d, in another example of the embodiment, in step S103, the first boundary region and the second boundary regions of the mesa structures (M) are simultaneously etched until the substrate100is exposed, and each of the dicing line regions300is situated between two adjacent ones of the mesa structures (M), and includes a first dicing line region301, and two second dicing line regions302on two opposite sides of the first dicing line region301. An exposed part of the substrate100, from which the first boundary regions of two adjacent ones of the mesa structures (M) are removed, has an even flat surface105on which the first dicing line region301is formed, and other exposed parts of the substrate100from which the second boundary regions of two adjacent ones of the mesa structures (M) are removed have uneven toothed surfaces104. Each of the other exposed parts of the substrate100having a second dicing line region302formed thereon. The even flat surface105of the substrate100may be the even surface of the flat base layer101of the substrate100, or may be a surface of the substrate100which is exposed as a result of etching the even surface of the flat base layer101of the substrate100in certain degree. The uneven toothed surfaces104of the substrate100may be formed to have a height equal to the original height of the uneven toothed structure layer102, or may be formed to have a height lower than the original height of the uneven toothed structure layer102.

In some embodiments, for each mesa structure (M), the width of the mesa bottom (M3) is in a range from 2 μm to 38 μm, and the width of the dicing line region300formed after removal of the mesa bottom (M3) is in a range from 4 μm to 40 μm.

In some embodiments, for each mesa structure (M), the width of the first dicing line region301is in a range from 2 μm to 38 μm, and the width of the second dicing line region302is in a range from 2 μm to 38 μm. The width of the first dicing line region301may be less than the width of the second dicing line region302. Alternatively, the width of the first dicing line region301may be equal to or greater than the width of the second dicing line region302.

In some embodiments, the height of the first uneven toothed surface103is not greater than 2 μm. Further, the height of the first uneven toothed surface103may be in a range from 1 μm to 2 μm or may be less than 1 μm. In some embodiments, the height of the second uneven toothed surface104is not greater than 2 μm. Further, the height of the second uneven toothed surface104may be in a range from 1 μm to 2 μm or may be less than 1 μm.

According to this embodiment, the part of the substrate where the first dicing line region301is formed has a relatively even surface in comparison with the other parts of the substrate100where the second dicing regions302are formed, and the other parts of the substrate100where the second dicing regions302are formed may have a relatively even surface in comparison with a part of the substrate100where the mesa structures (M) remain thereon. Therefore, when an insulation layer is formed on the second dicing line region302, the insulation layer can be bonded more tightly on the substrate100, so as to improve production yield of the light-emitting device.

According to this embodiment, since there is a difference between the thickness of the parts of the substrate100where the second dicing line regions302are formed and the thickness of the exposed part of the substrate100where the first dicing line region301is formed, a part of the first semiconductor layer201which corresponds in position to the first dicing line region301can be completely etched, so that a current leakage which may be caused due to incomplete etching of the part of the first semiconductor layer201can be prevented, thereby improving the luminous efficiency of the light-emitting device.

In step S104, parts of the substrate100each located immediately beneath the dicing line regions300are subjected to stealth dicing from the lower surface of the substrate100so as to form modified points inside the substrate100, and an external force is applied to the substrate100to cut the substrate100along the dicing line regions300, thereby obtaining singulated light-emitting devices each of which includes the substrate100and the mesa structure (M) formed on the substrate100.

Second Embodiment

Referring toFIG.4a, a light-emitting device according to the present disclosure is shown, which is manufactured by the method of First Embodiment.

The light-emitting device includes a substrate100and an epitaxial structure200formed on an upper surface of the substrate100. The epitaxial structure200includes a first semiconductor layer201, an active layer202, and a second semiconductor layer203which are disposed on the upper surface of the substrate100in such order. The substrate100has a substrate edge region3000surrounding and exposed from the epitaxial structure200. The substrate edge region3000includes a first substrate edge region3010and a second substrate edge region3020which is proximate to the epitaxial structure200than the first substrate edge region3010. The first substrate edge region3010has a first uneven toothed surface103, and the second substrate edge region3020has a second uneven toothed surface104which has a height greater than a height of the first uneven toothed surface103. Accordingly, the first substrate edge region3010(here, the edge region3010refers to an edge part or portion of the substrate100) has a thickness (d1) less than a thickness (d2) of the second substrate edge region3020.

Referring toFIG.4b, a variation of the second embodiment of the light-emitting device is shown. In this variation, unlike the first substrate edge region3010shown inFIG.4a, the first substrate edge region3010has an even flat surface105. Specifically, in this variation, the first substrate edge region3010has an even flat surface105, and the second substrate edge region3020has a second uneven toothed surface104. The flat even surface105is flat and has no protrusion. Accordingly, the first substrate edge region3010has a thickness (d1) less than a thickness (d2) of the second substrate edge region3020.

In some embodiments, each of the first and second uneven toothed surfaces103,104includes a plurality of protrusions which have a pointed cone-shape, and each of the protrusions of the first uneven toothed surface103or the second uneven toothed surface104has an arcuate side wall. The arcuate side wall may be concave or convex.

In some embodiments, the epitaxial structure200has a boundary sidewall (B) which extends downward continuously from the second semiconductor layer203and has a bottom end meeting an upper surface of the substrate edge region3000, and no step is formed on at least a portion of the boundary sidewall (B) of the epitaxial structure200.

In some embodiments, the epitaxial structure200has a boundary sidewall (B) which extends downward continuously from the second semiconductor layer203and has a bottom end meeting the substrate edge region3000, and no step is formed on all part of the boundary sidewall (B) of the epitaxial structure200. In such embodiments, the second substrate edge region3020surrounds the epitaxial structure200, and the first substrate edge region3010surrounds the second substrate edge region3020.

In some embodiments, the epitaxial structure200has a boundary side wall (B) which includes a portion extending downward continuously from the second semiconductor layer203and has a bottom end meeting the substrate edge region3000, and no step is formed on the portion of the boundary sidewall (B) of the epitaxial structure200while a step is formed on a remaining portion of the boundary sidewall (B) of the epitaxial structure200other than the portion of the boundary sidewall (B). The step is provided for forming an electrode.

In some embodiments, the substrate edge region3000of the substrate100has a width ranging from 2 μm to 20 μm, such as from 6 μm to 15 μm, or from 8 μm to 12 μm.

In some embodiments, the first substrate edge region3010has a width ranging from 1 μm to 19 μm, such as from 3 um to 10 μm, from 4 um to 8 μm, or 6 um, and the second substrate edge region3020has a width ranging from 1 μm to 19 μm, such as from 3 um to 10 μm, from 4 um to 8 μm, or 6 um.

The width of the first substrate edge region3010may be less than the width of the second substrate edge region3020. Alternatively, the width of the first substrate edge region3010may be equal to or greater than the width of the second substrate edge region3020.

The first substrate edge region3010may have an area which is as large as possible. For example, the width of the first substrate edge region3010is greater than the width of the second substrate edge region3020, so as to allow the pattern of the substrate edge region3000to have a relatively low height, which is beneficial to coverage of an insulation layer on the epitaxial structure200and the first and second substrate edge regions3010,3020.

Third Embodiment

FIGS.5aand5bshow a flip-chip type light-emitting device1which is also produced by the method of the first embodiment. The light-emitting device1includes an epitaxial structure12which may be the same structure as the epitaxial structure200shown inFIG.4a. The epitaxial structure12includes a first semiconductor layer123, an active layer124, and a second semiconductor layer125.

Specifically, as shown inFIG.5a, the epitaxial structure12has an upper surface121and a lower surface122opposite to the upper surface121. Further, the epitaxial structure12includes the first semiconductor layer123, the active layer124, and the second semiconductor layer125which are disposed on a substrate100in such order from the lower surface122to the upper surface121. That is to say, the active layer124is located between the first semiconductor layer123and the second semiconductor layer125. The first semiconductor layer123has an upper surface123awhere the active layer124is formed thereon, and a lower surface123b(i.e., the lower surface122of the epitaxial structure12) which faces toward the substrate100. The first semiconductor layer123may be an N-type semiconductor layer. The substrate100includes a substrate edge region3000which is the same as the substrate edge region3000of the second embodiment shown inFIG.4a.

As shown inFIG.5a, parts of the upper surface121of the epitaxial structure12are exposed from the active layer124, and the exposed parts of the first semiconductor layer123define multiple internal mesa bottoms (M3′) (only one is shown inFIG.5afor the sake of brevity). The internal mesa bottoms (M3′) are located within an internal area (E) of the epitaxial structure12, and a boundary sidewall (B) of the epitaxial structure12loops around the internal area (E); a plurality of through holes (h) (only one is shown inFIG.5a) are formed in the internal area (E) above the internal mesa bottoms (M3′), respectively. The substrate edge region3000of the substrate100loops around the boundary sidewall (B) of the epitaxial structure12and is exposed from the epitaxial structure12. The substrate edge region3000includes a first substrate edge region3010and a second substrate edge region3020which is more proximate to the boundary sidewall (B) of the epitaxial structure12than the first substrate edge region3010. The first substrate edge region3010has a thickness (d1) less than a thickness (d2) of the second substrate edge region3020. In addition, the light-emitting device1may further includes an insulation layer32which covers the epitaxial structure12and the first and second substrate edge regions3010,3020of the substrate edge region3000. Since the first substrate edge region3010is lower than the second substrate edge region3020, the insulation layer32can efficiently enclose the second substrate edge region3020, and a current leakage which may be caused due to incomplete etching of the first semiconductor layer123on the second substrate edge region3020can be prevented, thereby improving the manufacturing yield of the light-emitting device.

In this embodiment, the epitaxial structure12has the boundary sidewall (B) which extends downward continuously from the second semiconductor layer125and has a bottom end meeting the upper surface of the substrate edge region3000, and no step is formed on all part of the boundary sidewall (B) of the epitaxial structure12. The second substrate edge region3020surrounds the epitaxial structure12, and the first substrate edge region3010surrounds the second substrate edge region3020.

In this embodiment, the boundary sidewall (B) of the epitaxial structure12is not formed with any step; specifically, the boundary sidewall (B) has no mesa bottom formed by the first semiconductor layer123, which can affect the light emitting area of the light-emitting device1, thereby improving the light emitting efficiency of the light-emitting device1. Accordingly, since the light emitting area of the light-emitting device1is not affected, and since a metal reflection layer26is formed as described below, the brightness of the light-emitting device1can be significantly improved.

In this embodiment, the light-emitting device1further includes a first metal electrode21and a second metal electrode22. The first metal electrode21is located above the upper surface121of the epitaxial structure12, and is electrically connected to the first semiconductor layer123. In some embodiments, the first metal electrode21is directly formed on the mesa bottom formed by the first semiconductor layer123, so as to ensure a good ohmic contact between the first metal electrode21and the first semiconductor layer123.

The second metal electrode22is located above the upper surface121of the epitaxial structure12(i.e., the upper surface of the second semiconductor layer125), and is electrically connected to the second semiconductor layer125. The second metal electrode22may be made of the same material as that of the first metal electrode21.FIG.5bwhich is a top view shows a more detailed configuration of the internal area (E) of the light-emitting device1. As shown inFIG.5b, each of the first and second metal electrodes21,22has a circular or elliptical shape. Each of the first and second metal electrodes21,22may have a width ranging from 5 μm to 50 μm, such as 10 μm, 20 μm, 30 μm.

In this embodiment, the light-emitting device1further includes a first connection electrode41and a second connection electrode42. The insulation layer32partially covers the epitaxial structure12, the first metal electrodes21, and the second metal electrodes22. The insulation layer32includes a first insulation layer321and a second insulation layer322. The second insulation layer322is located above the first insulation layer321. The insulation layer32has first holes61and second holes62. Each of the first holes61is located above one of the first metal electrodes21, so that, through each of the first holes61, the first connection electrode41is electrically connected to the first metal electrode21. Each of the second holes62is located above one of the second metal electrodes22, so that, through each of the second holes62, the second connection electrode42is electrically connected to the second metal electrode22. Both of the first holes61and the second holes62extend through the first and second insulation layers321,322. The insulation layer32has different effects depending on the positions thereof. For example, when the insulation layer32covers the boundary sidewall (B) of the epitaxial structure12, it may prevent the first and second semiconductor layers123,125from being electrically connected to each other by leaked conductive materials, so as to prevent short circuit of the light-emitting device1. The insulation layer32includes a non-conductive material, such as silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, and a combination thereof; the combination may form a Bragg reflector (DBR).

In some embodiments, the first insulation layer321is an insulating reflective layer formed by repeatedly stacking two insulating materials. In an example where the first insulation layer321is a DBR layer, the optical thickness of each sub-layer of the DBR layer is about 137.5 nm, and the DBR layer has a thickness ranging from 2 μm to 6 μm, and includes 10 to 30 pairs of the sub-layers. In some embodiments, in order to ensure reflectance of the DBR layer, the DBR layer includes 20 to 30 pairs of the sub-layers, has a thickness ranging from 4 to 6 μm. In some embodiments, the DBR layer includes 22 pairs of the sub-layers, and has a thickness of 5 μm.

A part of or all of the insulation layer32covers all of the substrate edge region3000of the substrate100.

In this embodiment, the light-emitting device1further includes a metal reflection layer26formed between the first insulation layer321and the second insulation layer322of the insulation layer32. The metal reflection layer26is used to reflect light so that more light can be emitted from a light emitting surface of the light-emitting device1. In some embodiments, the metal reflection layer26includes Ag or Al.

The first connection electrode41is located above the insulation layer32, and is connected to the first metal electrodes21. The first connection electrode41is capable of spreading current, protects the first metal electrodes21located therebelow, and has functions of supporting and height adjustment. The material of the first connection electrode41may be selected from Cr, Pt, Au, Ni, Ti, Al, and combination thereof. In some embodiments, the first connection electrode41has a metal base layer which made of Ti or Cr, so as to facilitate adhesion between the first connection electrode41and the insulation layer32. The second connection electrode42is located above the insulation layer32, and is connected to the second metal electrodes22. The second connection electrode42is capable of spreading current. The material of the second connection electrode42may be selected from Cr, Pt, Au, Ni, Ti, Al, and combination thereof. In some embodiments, the second connection electrodes42has a metal surface layer which is made of Ti or Cr, so as to facilitate adhesion between the second connection electrode42and the adjacent structure layers.

In some embodiments, each of the first and second holes61,62of the insulation layer32has a bottom width and a top width, and the bottom width of each of the first and second holes61,62is smaller than the top width of each of the first and second holes61,62. This facilitates filling of the first and second connection electrodes41,42into the first and second holes61,62and allows the first and second connection electrodes41,42to be formed continuously in the first and second holes61,62. In some embodiments, the top width of each first hole61is greater than the width of the upper surface of the first metal electrode21, and the top width of each second hole62is greater than the width of the upper surface of the second metal electrode22.

The first connection electrode41may be formed as a stripe or multiple stripes, or may be formed into a comb-shape; the second connection electrode42may be formed as a block. As shown inFIG.5b, when the first and second connection electrodes41,42are projected perpendicularly onto a common horizontal plane and are viewed from above the epitaxial structure12, an area of the first connection electrode41is smaller than that of the second connection electrode42, and the second connection electrode42generally surrounds the first connection electrode(s)41.

The vertical projections of the first metal electrodes21and/or the second metal electrodes22on an imaginary common horizontal plane do not overlap with the vertical projection of the metal reflection layer26on the imaginary horizontal plane. That is to say, when viewing the epitaxial structure12from above of the light-emitting device1, the first metal electrodes21and/or the second metal electrodes22do not intersect with or overlap with the metal reflection layer26, such that none of the first and second metal electrodes21,22are located within the vertical projection area of the metal reflection layer26. If the vertical projections of the first metal electrodes21and/or the second metal electrodes22on the imaginary horizontal plane overlap with the vertical projection of the metal reflection layer26on the imaginary horizontal plane, the first holes61and/or the second holes62at the insulation layer32may be too small, and the metal reflection layer26may cover the first and second metal electrodes21,22. In such case, the insulation layer32located below the metal reflection layer26may cover the first and second metal electrodes21,22, so that steps may be formed. If the steps are formed, due to the brittleness of the insulation layer32, the insulation layer32may be prone to crack at locations where the steps are formed, and a moisture may get into the light-emitting device1through the cracks formed in the insulation layer32. Thus, the metal reflection layer26tends to migrate, so that the stability of reflectivity of the metal reflection layer26may be affected, and the metal reflection layer26may contact with a contact electrode disposed therebelow. This may cause a melt blending of the materials of the metal reflection layer26, which may affect the stability of the metal reflection layer26, and may cause the metal reflection layer26to be easily damaged in a subsequent process such as an etching process.

In some embodiments, the vertical projection of the lower surface of the first metal electrode21and/or the lower surface of the second metal electrode22on the imaginary horizontal plane do not overlap with the vertical projection of a lower surface of the metal reflection layer26on the imaginary horizontal plane. In some embodiments, the imaginary horizontal plane is a plane on which the lower surface122of the first semiconductor layer123of the epitaxial structure12shown inFIG.5ais located.

In some embodiments, the metal reflection layer26has a thickness ranging from 200 nm to 1000 nm, such as from 300 nm to 600 nm. For example, the thickness of the metal reflection layer26may be 400 nm or 500 nm. The second insulation layer322has a thickness ranging from 200 nm to 1000 nm, such as from 200 nm to 400 nm, or from 400 nm to 600 nm.

In some embodiments, the metal reflection layer26is disposed above the upper surface121of the epitaxial structure12, and is not disposed above the exposed part of the substrate100which is exposed from the epitaxial structure12, so that the metal reflection layer26can be as flat as possible. In some embodiments, the metal reflection layer26is only disposed immediately above an upper surface of the second semiconductor layer125, so that the metal reflection layer26thus formed can be as flat as possible and is prevented from being formed with a step or a height difference, thereby avoiding moisture erosion or metal migration problems and ensuring the stability of the metal reflection layer26.

In some embodiments, the vertical projection of the metal reflection layer26on the upper surface of the second semiconductor layer125overlaps with the vertical projections of the first connection electrode41and the second connection electrode42on the upper surface of the second semiconductor layer125. The vertical projection of the metal reflection layer26on the imaginary horizontal plane overlaps with the vertical projections of the first connection electrode41and the second connection electrode42on the imaginary horizontal plane.

In some embodiments, the area of the vertical projection of the metal reflection layer26on the upper surface of the second semiconductor layer125occupies at least 80% of the total area of the upper surface of the second semiconductor layer125; the total area of the vertical projections of the second metal electrodes22on the upper surface of the second semiconductor layer125occupies less than 20% of the total area of the upper surface of the second semiconductor layer125. In some embodiments, the light-emitting device1further includes a current blocking layer67which is disposed below the second metal electrode22, and the area of the vertical projection of the current blocking layer67on the upper surface of the second semiconductor layer125occupies less than 20% of the total area of the upper surface of the second semiconductor layer125.

In some embodiments, the second insulation layer322covers an upper surface and a sidewall of the metal reflection layer26. Moreover, a part of the first insulation layer321and a part of the second insulation layer322which are located around the metal reflection layer26are in direct contact, so that the first insulation layer321and the second insulation layer322tightly sandwich the metal reflection layer26, thereby improving the overall structural stability.

In some embodiments, as shown inFIG.5a, the metal reflection layer26has a third hole63which is located above and communicates with the second hole62, and a dimension L1of the third hole63which is measured at a bottom part thereof is greater than a dimension L2of the second hole62which is measured at a top part thereof (i.e., at a point where the first insulation layer321and the second insulation layer322are in contact with each other). Therefore, the metal reflection layer26thus formed can be as flat as possible, so that moisture erosion and metal migration which may be caused when a step or a height difference is formed on the metal reflection layer26can be avoided.

In some embodiments, as shown inFIG.5a, the metal reflection layer26further has a fourth hole64which is located above and communicates with the first hole61, and a dimension L3of the fourth hole64which is measured at a bottom part thereof is greater than a dimension L4of the first hole61which is measured at a top part thereof (i.e., at the point where the first insulation layer321and the second insulation layer322are in contact with each other.

In some embodiments, the dimension L1of the third hole63is greater than a dimension L5of the second hole62which is measured at a top part thereof, so as to ensure that the metal reflection layer26can be protected, thereby preventing the metal reflection layer26from being exposed or etched and damaged. The difference between the dimensions L1and L5may be at least 6 μm.

Each of the dimensions L1to L5may be a diameter or a width of each of the holes.

In one embodiment, as shown inFIG.5a, the top part of the first hole61is higher than the upper surface of the first metal electrode21, and the top part of the second hole62is higher than the upper surface of the second metal electrode22. The heights of the first and second holes61,62are determined based on the lower surface122of the first semiconductor layer121(i.e., the lower surface of the epitaxial structure12) as a reference surface.

In the embodiment, the metal reflection layer26is formed flatly on the first insulation layer321. Furthermore, the metal reflection layer26has edge parts with inclined edge faces which interconnect between upper and lower surfaces of the metal reflection layer26. In such example, the second insulation layer322may have a thickness ranging from 200 nm to 1000 nm, and the inclined edge faces of the metal reflection layer26may have an inclination angle not greater than 40°, such as not greater than 30°, or not greater than 20°.

In some embodiments, as shown inFIG.5a, the light-emitting device1further include an insulating structure34, a first pad electrode51, and a second pad electrode52. The insulating structure34partially covers the insulation layer32, the first connection electrode41, and the second connection electrode42, for mainly providing insulating protection function. The first pad electrode51is located above the insulating structure34, and is connected to the first connection electrode41. The second pad electrode52is located above the insulating structure34, and is connected to the second connection electrode42. The first and second pad electrodes51,52may be metal pads.

In some embodiments, in addition to the current blocking layer67, the light-emitting device1further include a transparent current spreading layer66. The current blocking layer67is disposed between the second semiconductor layer125and the second metal electrode22, and is capable of blocking a current. The transparent current spreading layer66is disposed between the current blocking layer64and the second metal electrode22, covers the current blocking layer67, and is capable of spreading a current. In some embodiments, the vertical projection of the metal reflection layer26on the imaginary horizontal plane does not overlap with the vertical projection of the current blocking layer67on the imaginary horizontal plane. The current blocking layer67may include silicon oxide, and has a width greater than that of the second metal electrode22. Particularly, the bottom width of the current blocking layer67is greater than the bottom width of the second metal electrode22, and the difference therebetween may be 2 μm to 6 μm. In some embodiments, in order to keep the metal reflection layer26away from the current blocking layer67, the difference between the dimension L1and the dimension L5is at least 15 μm.

The transparent current spreading layer66is made of a transparent conductive material, such as, but not limited to, indium tin oxide (ITO).

In some specific embodiments, the metal reflection layer26is formed such that the vertical projection thereof on the imaginary horizontal plane falls within the vertical projection of the second semiconductor layer125on the imaginary horizontal plane. In other words, the metal reflection layer26is only disposed immediately above the second semiconductor layer125, so that the metal reflection layer26thus formed can be as flat as possible. Accordingly, when the metal reflection layer26is formed on the first insulation layer321, and the second insulation layer322is formed on the first insulation layer321and covers the metal reflection layer26, formation of a height difference or a step between the first and second insulation layers321,322can be avoided, thereby further avoiding moisture erosion or metal migration problems about the metal reflection layer26.

In some embodiments, the upper surface121of the epitaxial structure12located immediately below the metal reflection layer26is flat and continuous, so that the metal reflection layer26formed thereon can be as flat as possible.

In some embodiments, a metal adhesion layer may be disposed between the metal reflection layer26and the second insulation layer322. The metal adhesion layer may be made of Ti or Cr, and has a thickness ranging from 0.1 nm to 20 nm, such as from 0.5 nm to 5 nm.

Referring toFIG.5a, in some embodiment, the first substrate edge region3010of the substrate100has a first uneven toothed surface which is similar to the first uneven toothed surface103shown inFIG.4a, and the second substrate edge region3020has a second uneven toothed surface which is similar to the second uneven toothed surface104shown inFIG.4a, and the second uneven toothed surface has a height greater than a height of the first uneven toothed surface. Accordingly, the first substrate edge region3010has a thickness (d1) less than a thickness (d2) of the second substrate edge region3020. The first substrate edge region3010is flatter than the second substrate edge region3020, so that the adhesion between the insulation layer32and the substrate100can be facilitated, thereby improving the light-emitting efficiency of the light-emitting device1, and further improving the manufacturing yield of the light-emitting device1. Besides, a part of the first semiconductor layer123which corresponds in position to the first substrate edge region3010can be fully etched, so that a current leakage which may be caused due to incomplete etching of the part of the first semiconductor layer123can be prevented.

In this embodiment, the substrate100is similar to the substrate100shown inFIGS.3aand3b, and includes a flat base layer and an uneven toothed structure layer formed on an even surface of the flat base layer. The height of the second uneven toothed surface is equal to that of the uneven toothed structure layer (referring toFIG.3a) located below the epitaxial structure12. The height of the second uneven toothed surface may range from 2 μm to 2.5 μm, and the height of the first uneven toothed surface may range from 1 μm to 2 μm.

Performance tests are respectively performed on a sample of the light-emitting device shown inFIG.4a, which is manufactured by the method of the first embodiment, and a sample of the conventional light-emitting device formed by the method shown inFIG.1b. Results of the tests are shown in the table 1 below.

As can be seen from the results shown in Table 1, the light-emitting device according to the embodiment shown inFIG.4ahas significantly improved voltage and brightness compared to the conventional light-emitting device shown inFIG.1b. As such, the disclosure is surely advantageous for improving the electrical yield and the light emitting efficiency of the light-emitting device.