Horizontal nanosheet FETs and methods of manufacturing the same

A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

BACKGROUND

Horizontal nanosheet (hNS) field effect transistors (FETs) having InGaAs channels offer the possibility of high mobility, high injection velocity, and low gate capacitance. However, InGaAs hNS FETs also tend to have small bandgaps, such as approximately 750 meV or even less than 1.1 eV for silicon. A consequence of this small direct bandgap is a large amount of band-to-band tunneling (BTBT) leakage current, which is further exacerbated by the parasitic bipolar effect (PBE) that is present in all gate-all-around (GAA) FETs. Parasitic leakage, which is a combination of the BTBT leakage and PBE gain, is exponentially sensitive to positive supply voltage (VDD) and channel length. BTBT occurs in regions of strong band-bending, which exists in the transition region between the channel and the high-doped portion of the drain extension. In related art hNS FETs in which the effective channel length (Leff) is approximately equal to the gate length (LG), the hNS FETs have very high BTBT leakage and are unusable for a mobile system on a chip (SOC) operating at supply voltages of 0.75V or higher. Additionally, the channel length sensitivity presents a significant scaling limitation because hNS FETs with an Leffof approximately 15 nm may not be able to operate with VDDabove approximately 0.7V without incurring excessive BTBT leakage.

In the related art, this significant scaling limitation may be addressed by configuring the FET such that the Leffis longer than the LG. Increasing Leffby shifting the PN junction away from the gate edges reduces band curvature and exponentially reduces BTBT leakage. Increasing the Leffalso reduced PBE gain, which has a near-exponential sensitivity to channel length. The Leffcould be increased, for instance, up to two spacer thicknesses larger than the LG. However, in related art hNS FETs, increasing Leffreduces the electron concentration in the extension regions and thus increases parasitic resistance (Rpara). The resulting increase in Rparamay render the hNS FET unsuitable. Accordingly, in related art hNS FETs, there is a tradeoff between BTBT leakage and Rpara(e.g., the BTBT leakage of related art hNS FETs may be reduced by increasing the Leff, but this reduction in BTBT leakage is at the expense of increasing the Rparaof the hNS FET).

SUMMARY

The present disclosure is directed to various embodiments of a horizontal nanosheet (hNS) field effect transistor (FET). In one embodiment, the hNS FET includes a source electrode, a drain electrode, a gate electrode between the source electrode and the drain electrode, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, a channel region under the gate electrode extending between the source electrode and the drain electrode, and at least one layer of crystalline barrier material. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The layer of crystalline barrier material has a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region. The first thickness of the layer of crystalline barrier material at the extension regions of the source and drain electrodes may be from approximately 3 nm to approximately 5 nm and the second thickness of the layer of crystalline barrier material at the channel region may be from approximately 1 nm to approximately 2 nm. The first thickness of the layer of crystalline barrier material at the extension regions of the source and drain electrodes may be from approximately 0.5 nm to approximately 5 nm and the second thickness of the layer of crystalline barrier material at the channel region may be substantially zero. The at least one layer may include a first layer of crystalline barrier material above the extension regions of the source and drain electrodes and a second layer of crystalline barrier material below the extension regions of the source and drain electrodes. The crystalline barrier material may be InP, InGaP, InAlA, AlAsSb, or combinations thereof.

The crystalline barrier material may include a II-IV semiconductor alloy, such as ZnSeTe or ZnCdTe.

Upper portions of the source and drain electrodes may be more heavily doped than remaining portions of the source and drain electrodes. The more heavily doped upper portions of the source and drain electrodes may each have a thickness from approximately 5 nm to approximately 10 nm.

The channel may include a III-V material.

The extension regions of the source and drain electrodes may be lightly doped having a doping density from approximately 5 e18/cm3to 1 e17/cm3.

An effective length of the channel region may be greater than a length of the gate electrode. The effective length of the channel region may be greater than the length of the gate electrode by at least approximately 4 nm.

The present disclosure is also directed to various methods of manufacturing a horizontal nanosheet field effect transistor. In one embodiment, the method includes forming a sacrificial barrier layer, forming a first layer of crystalline barrier material on the sacrificial barrier layer, forming a channel layer on the first layer of crystalline barrier material, forming a second layer of crystalline barrier material on the channel layer, forming a sacrificial gate, forming a pair of spacers, wherein a portion of the channel layer between the pair of spacers defines a channel region, etching to remove portions of the sacrificial barrier layer, the channel layer, and the first and second layers of crystalline barrier material outside of the pair of spacers, epitaxially re-growing a source electrode and a drain electrode, the source electrode and the drain electrode each including an extension region underneath one spacer of the pair of spacers, etching to remove the sacrificial gate and a remainder of the sacrificial barrier layer, etching to remove at least portions of the first and second layers of the crystalline barrier material above and below the channel region such that the first and second layers of the crystalline barrier material at the extension regions of the source and drain electrodes have a first thickness and the first and second layers of the crystalline barrier material at the channel region have a second thickness less than the first thickness, and depositing a gate electrode between the pair of spacers and above the channel region.

Etching to remove at least portions of the first and second layers of the crystalline barrier material above and below the channel region may include completely removing the portions of the first and second layers of the crystalline barrier material above and below the channel region.

The method may also include ultra-shallow doping of upper end portions of the source and drain electrodes.

The extension regions of the source and drain electrodes may be lightly doped having a doping density from approximately 5 e18/cm3to 1 e17/cm3.

An effective length of the channel region may be greater than a length of the gate electrode.

A method of manufacturing a horizontal nanosheet field effect transistor according to another embodiment of the present disclosure includes obtaining an initial stack including an alternating arrangement of sacrificial crystalline layers and channel layers, forming a source electrode and a drain electrode, etching the initial stack to form regions for internal spacers, epitaxially re-growing at least one layer of crystalline barrier material, the at least one layer of crystalline barrier material having a first thickness at extension regions of the source and drain electrodes and a second thickness less than the first thickness at a channel region, and depositing the internal spacers.

The method may also include depositing a gate electrode between the internal spacers. An effective length of the channel region may be greater than a length of the gate electrode.

This summary is provided to introduce a selection of features and concepts of embodiments of the present disclosure that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in limiting the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a workable device.

DETAILED DESCRIPTION

The present disclosure is directed to various embodiments of a horizontal nanosheet (hNS) field effect transistor (FET) and various methods of manufacturing the horizontal nanosheet field effect transistor. The horizontal nanosheet field effect transistor according to one embodiment of the present disclosure includes one or more layers of crystalline barrier material (CBM) at the drain electrode extension region and/or at the source electrode extension region. Additionally, according to one or more embodiments of the present disclosure, the one or more layers of CBM either do not extend to a channel region of the hNS FET or the one or more layers of CBM are thinner at the channel region compared to the source and drain extension regions. The one or more layers of CBM are configured to increase electron mobility in the extension regions of the source and drain electrodes by suppressing surface roughness scattering (SRS), which would otherwise occur at the interface between the crystalline channel and a non-crystalline overlayer. Reducing the thickness of the one or more layers of CBM at the channel region compared to the extension regions, or not providing the one or more layers of CBM in the channel region, is configured to increase electron mobility in the extension regions without increasing the equivalent oxide thickness (EOT) of the hNS FET, which would be detrimental to the short channel effects (SCE) performance of the hNS FET and would not be a practical solution for the 5 nm node and beyond. Additionally, according to one or more embodiments, the extension regions of the source and drain electrodes are lightly doped and the effective length of the channel is greater than the length of the gate. Reducing the doping in the extension regions and increasing the effective length of the channel is configured to reduce the parasitic leakage of the hNS FET. Together, the effective length of the channel, the light doping of the extension regions, and the one or more layers of CBM in the extension regions are configured to reduce the parasitic leakage of the hNS FET while not increasing or substantially not increasing the parasitic resistance of the hNS FET. Accordingly, unlike related art hNS FETs, in the hNS FET of the present disclosure there is not a tradeoff between parasitic leakage and parasitic resistance.

With reference now toFIG. 1, a horizontal nanosheet (hNS) field effect transistor (FET)100according to one embodiment of the present disclosure includes a source electrode101, a drain electrode102, a gate electrode103between the source electrode101and the drain electrode102, a first spacer104between the source electrode101and the gate electrode103, a second spacer105between the drain electrode102and the gate electrode103, and a channel region106under the gate electrode103and extending between the source electrode101and the drain electrode102. The channel region106may be formed, for example, of InxGa1-xAs or InxGa1-xSb. In one or more embodiments, the source and drain electrodes101,102may be formed of a different material than the channel region106. For example, in one embodiment in which the channel region106is formed of InxGa1-xAs, the source and drain electrodes101,102may be formed of InyGa1-yAs, where y<x. In one or more embodiments, the source and drain electrodes101,102may be formed of InAs. In the illustrated embodiment, the hNS FET100also includes a high dielectric (hi-k) interfacial layer107. The hi-k interfacial layer107extends at least partially along the gate electrode103. In the illustrated embodiment, the hi-k interfacial layer107extends along a lower surface and a pair of opposing side surfaces of the gate electrode103such that hi-k interfacial layer107separates the gate electrode103from the channel region106and the first and second spacers104,105. In the illustrated embodiment, the source electrode101includes an extension region108extending at least partially under the first spacer104and the drain electrode102includes an extension region109extending at least partially under the second spacer105.

In the illustrated embodiment, the hNS FET100also includes a first layer110of crystalline barrier material (CBM) above (e.g., on) the extension regions108,109of the source and drain electrodes101,102, respectively, and a second layer111of CBM below (e.g., underneath) the extension regions108,109of the source and drain electrodes101,102, respectively. Additionally, in the illustrated embodiment, the first and second layers110,111of CBM do not extend over or under the channel region106(i.e., the channel region106of the hNS FET100is free or substantially free of the layers110,111of CBM). In one or more embodiments, the first layer110of CBM and/or the second layer111of CBM may extend above and/or below the channel region106, but the portions of the first and/or second layers110,111of the CBM at the channel region106have a thickness less than the portions of the first and second layers110,111of CBM at the extension regions108,109of the source and drain electrodes101,102, respectively (i.e., the first layer110of CBM and/or the second layer111of CBM has a reduced thickness at the channel region106). Additionally, in one or more embodiments, the hNS FET100may be provided with a single layer of CBM for each transistor (e.g., the hNS FET may include the first layer110of CBM above the extension regions108,109or the second layer111of CBM below the extension regions108,109). In one embodiment in which the first and second layers110,111of CBM are provided at the extension regions108,109but not at the channel region106, the first and second layers110,111of CBM may each have a thickness from approximately 0.5 nm to approximately 5 nm, such as, for instance, from approximately 1 nm to approximately 3 nm. In one embodiment in which the first and second layers110,111of CBM are provided at both the extension regions108,109and the channel region106, the portions of the first and second layers110,111of CBM at the extension regions108,109may each have a thickness from approximately 3 nm to approximately 5 nm and the portions of the first and second layers110,111at the channel region106may each have a thickness less than or equal to approximately 2 nm (e.g., a thickness from approximately 1 nm to approximately 2 nm).

In one or more embodiments, the CBM of the first and second layers110,111may be InP, InGaP, InAlAs, AlAsSb, or combinations thereof. In one or more embodiments, the CBM of the first and second layers110,111may be II-IV semiconductor alloy, such as, for example, ZnSeTe, ZnCdTe, or combinations thereof. Additionally, the CBM of the first and second layers110,111is lattice-matched or substantially lattice-matched to the III-V material of the channel region106by a suitable choice of CBM stoichiometry.

The first and second layers110,111of CBM provided at the channel region106and/or at the extension regions108,109of the hNS FET100of the present disclosure are configured to significantly increase mobility in the extension regions108,109and the channel region106by suppressing surface roughness scattering (SRS), which would otherwise occur at an interface between the crystalline channel and a non-crystalline overlayer.

Reducing the thickness of the first and second layers110,111of CBM at the channel region106compared to the extension regions108,109, or not providing the first and second layers110,111of CBM in the channel region106, is configured to increase electron mobility in the extension regions108,109without increasing the equivalent oxide thickness (EOT) of the hNS FET100, which would be detrimental to the short channel effects (SCE) performance of the hNS FET100and would not be a practical solution for the 5 nm node and beyond.

In one or more embodiments, the doping of the channel region106may be very low or intrinsic. Additionally, in one or more embodiments, the doping of the extension regions108,109of the source and drain electrodes101,102may be very low, such as, for example, having a doping density (e.g., an electron density) from approximately 1 e17/cm3to approximately 5 e18/cm3. In one or more embodiments, the source and drain electrodes101,102may be moderately doped, such as, for example, having a doping density from approximately 5 e18/cm3to approximately 1 e19/cm3. Furthermore, in the illustrated embodiment, upper end portions112,113of the source and drain electrodes101,102, respectively, are more heavily doped than remaining portions of the source and drain electrodes101,102and the extension regions108,109. In one or more embodiments, the more heavily doped upper end portions112,113of the source and drain electrodes101,102may have a density from approximately 1 e19/cm3to approximately 1 e20/cm3. Additionally, in one or more embodiments, the more heavily doped upper end portions112,113may have a thickness from approximately 5 nm to approximately 10 nm. The more heavily doped upper end portions112,113of the source and drain electrodes101,102are configured to provide a good metal-semiconductor contact. Additionally, in the illustrated embodiment, the hNS FET100includes a pair of electrical contacts114,115on the highly-doped upper end regions112,113, respectively, of the source and drain electrodes101,102.

In one or more embodiments, the effective length of the channel (Leff) may be greater than the length of the gate (LG). This may be achieved by placing the doping of the extension regions108,109of the source and drain electrodes101,102sufficiently away from inner edges of the extension regions108,109that are proximate to the gate electrode103. For example, in one or more embodiments, the relatively more heavily doped portions of the extension regions may be positioned at or proximate to sides of the first and second spacers104,105that are located away from the gate electrode103(e.g., PN junctions may be located at sides of the first and second spacers104,105that are located away from the gate electrode103). In one or more embodiments, Leffmay be greater than LGby approximately 4 nm to approximately 10 nm. In one embodiment, Leffmay be greater than LGby approximately4nm, approximately 6 nm, approximately 10 nm, or more. Together, lightly doping the extension regions108,109of the source and drain electrodes101,102and providing the channel106with a greater effective length Leffthan the length of the gate106are configured to reduce band-to-band tunneling (BTBT) leakage and the parasitic bipolar effect (PBE), which acts as an amplifier of the BTBT-induced leakage (i.e., lightly doping the extension regions108,109and configuring the hNS FET100such that the effective length of the channel Leffis greater than the length of the gate LGare configured to reduce the parasitic leakage of the hNS FET100). Additionally, as described above, the first and second layers110,111of CBM at the extension regions108,109of the source and drain electrodes101,102are configured to increase electron mobility in the extension regions108,109by suppressing SRS and this increased electron mobility is configured to prevent or substantially prevent an increase in parasitic resistance, which would otherwise occur due to the low doping (i.e., low electron density) in the extension regions108,109.

Although in the illustrated embodiment the hNS FET100includes a stack of two transistors, in one or more embodiments, the hNS FET100may include any other suitable number of transistors, such as, for instance, three or more transistors.

FIG. 2is a graph comparing the carrier mobility as a function of carrier density of the hNS FET100according to one embodiment of the present disclosure to a related art, comparative example hNS FET without any layers of CBM at the extension regions.FIG. 2depicts both experimental data and the theoretical model of the hNS FET100having first and second layers110,111of CBM at the extension regions108,109of the source and drain electrodes101,102but not at the channel region106. As illustrated inFIG. 2, at a carrier density of approximately 1.10 E+12, which is the carrier density of the low-doped extension regions of the source and drain electrodes, the comparative example hNS FET has a carrier mobility of approximately 300 cm2/Vs, whereas the hNS FET according to one embodiment of the present disclosure has a carrier mobility of approximately 2,000 cm2/Vs. Additionally, as illustrated inFIG. 2, at a carrier density of approximately 4.10 E+12, which is the carrier density in the channel region, the comparative example hNS FET has a carrier mobility of approximately 200 cm2/Vs, whereas the hNS FET according to one embodiment of the present disclosure has a carrier mobility of approximately 1,000 cm2/Vs. Accordingly, the carrier mobility at the extension regions and the channel region of the hNS FET100according to one embodiment of the present disclosure is greater than the carrier mobility at the extension regions and the channel region of the related art, comparative example hNS FET that does not include any layers of CBM at the extension regions. Thus, the one or more layers of CBM at the extension regions of the source and drain electrodes are configured to increase carrier mobility compared to the related art, comparative example hNS FET that does not include any layers of CBM. In the related art, comparative example hNS FET, the extension regions and the channel region have relatively low mobility due to the high rate of surface roughness scattering (SRS) at an interface between the crystalline channel a non-crystalline overlayer. In contrast, the one or more layers of CBM provided at the channel region and/or at the extension regions of the hNS FET of the present disclosure are configured to significantly increase mobility in the extension regions and the channel region by suppressing SRS.

In one or more embodiments, the hNS FET100of the present disclosure may have a parasitic resistance (Rpara) equal or substantially equal to the Rparaof related art hNS FETs, but the hNS FET100of the present disclosure may have significantly reduced parasitic leakage (e.g., approximately a 10 times reduction in band-to-band (BTBT) tunneling and an approximately 10 times reduction in the parasitic bipolar effect (PBE), for an approximately 100 times reduction in the overall parasitic leakage).

FIGS. 3A-3Hdepict tasks of a method of forming a horizontal nanosheet (hNS) field effect transistor (FET)200according to one embodiment of the present disclosure. As illustrated inFIG. 3A, the method of forming the hNS FET200according to one embodiment includes forming or obtaining an initial stack201. In one or more embodiments, the initial stack201may be grown from a strain relaxation buffer (SRB). In one or more embodiments, the initial stack201may be transferred to an OI wafer using any suitable transfer process known in the art. In the illustrated embodiment, the initial stack201includes a sacrificial crystalline layer202, a first layer203of crystalline barrier material (CBM) on the sacrificial crystalline layer202, a channel layer204on the first layer203of CBM, and a second layer205of CBM on the channel layer204. In the illustrated embodiment, the initial stack200also includes a repetition of these layers202-205on the second layer205of CBM. Although in the illustrated embodiment the initial stack201includes two channel layers204, in one or more embodiments, the initial stack201may include any other suitable number of channel layers204depending on the desired size of the hNS FET200. The channel layers204may be formed, for example, of InxGa1-xAs or InxGa1-xSb. The CBM of the first and second layers203,205may be InP, InGaP, InAlAs, AlAsSb, or combinations thereof. In one or more embodiments, the CBM of the first and second layers203,205may be II-IV semiconductor alloy, such as, for example, ZnSeTe, ZnCdTe, or combinations thereof. Additionally, the CBM of the first and second layers203,205is lattice-matched to the channel layer204by a suitable choice of CBM stoichiometry. The layers203,205of CBM may each have a thickness from approximately 0.5 nm to approximately 5 nm, such as, for instance, from approximately 1 nm to approximately 3 nm. In one or more embodiments, each of the sacrificial crystalline layers202may have any suitable thickness depending on the desired vertical separation between adjacent channel layers204, such as, for instance, from approximately 4 nm to approximately 15 nm. Additionally, in one embodiment, the lowest sacrificial crystalline layer202of the initial stack201may be formed on any suitable isolation known in the art.

Additionally, although in the illustrated embodiment the stack includes first and second layers203,205of CBM above and below each respective channel layer204, in one or more embodiments, the initial stack201may include a single layer of CBM for each channel layer204depending on the desired configuration of the one or more layers of CBM in the hNS FET200(e.g., the initial stack201may include a single layer of CBM above or below each channel layer204). In one or more embodiments, the task of forming the initial stack201may be the same or similar to the tasks of forming a stack for a related art III-V hNS, but with the addition of the one or more layers203,205of CBM for each channel layer204.

With reference now toFIG. 3B, the method of forming the hNS FET200according to one embodiment of the present disclosure also includes a task of forming a pair of spacers206,207and a sacrificial poly gate208in the initial stack201(i.e., forming a pair of spacers206,207and a sacrificial poly gate208that extend down through the lowest sacrificial crystalline layer202). The pair of spacers206,207and the sacrificial poly gate208may be formed by any suitable manufacturing techniques or processes known in the art or hereinafter developed.

With reference now toFIG. 3C, the method of forming the hNS FET200according to one embodiment of the present disclosure also includes a task of etching to remove portions of the sacrificial crystalline layers202, the channel layers204, and the layers203,205of CBM that are outside of the pair of spacers206,207and the sacrificial poly layer208(i.e., etching to remove portions of the initial stack201that are outside of the pair of spacers206,207). In the illustrated embodiment, the method also includes a task of epitaxially re-growing source and drain electrodes209,210outside of the pair of spacers206,207. The source and drain electrodes209,210formed during the epitaxial re-growth are seeded by the channel layers204and the layers203,205of CBM. In one or more embodiments, the source and drain electrodes209,210formed during the epitaxial re-growth may be lightly in-situ doped or undoped. For example, in one or more embodiments, the source and drain electrodes209,210may have a doping density from approximately 5 e18/cm3to approximately 1 e19/cm3. Additionally, the method may include a task of forming internal spacers (not shown) by any suitable method known in the art or hereinafter developed. Following the task of etching to remove portions of the initial stack201that are outside of the pair of spacers206,207and epitaxially re-growing the source and drain electrodes209,210, the source and drain electrodes209,210include extension regions211,212, respectively, extending at least partially under the spacers206,207, respectively, and the portions of the channel layers204extending between the spacers206,207define channel regions213. Additionally, in one or more embodiments, the extension regions211,212of the source and drain electrodes209,210may be lightly doped, such as having a doping density of approximately 5 e18/cm3to 1 e17/cm3. The doping of the extension regions211,212may be from in-diffusion from adjacent regions of the epitaxially re-grown source and drain electrodes209,210and/or from in-diffusion from the layers203,205of CBM. In one or more embodiments, the doping of the extension regions211,212due to in-diffusion from adjacent regions of the epitaxially re-grown source and drain electrodes209,210may be limited by any suitable technique, such as using dopant diffusion inhibitors and/or by forming the epitaxially re-grown source and drain electrodes209,210such that the source and drain electrodes209,210are substantially lightly doped or undoped.

With reference now toFIG. 3D, the method of forming the hNS FET200according to one embodiment of the present disclosure includes a task of ultra-shallow doping upper end portions214,215of the source and drain electrodes209,210, respectively. The upper end portions214,215of the source and drain electrodes209,210that are doped may have a thickness (i.e., a depth) from approximately 5 nm to approximately 10 nm. In one or more embodiments, the upper end portions214,215of the source and drain electrodes209,210may be doped to have a doping density from approximately 1 e19/cm3to approximately 1 e20/cm3. The upper end portions214,215of the source and drain electrodes209,210that are relatively heavily doped may be used to enable low contact resistivity with subsequently formed contacts (e.g., low resistance between the source and drain electrodes209,210and subsequently formed contacts on the upper end portions214,215). The upper end portions214,215may be doped by any suitable technique or process, such as plasma implantation. Additionally, in one or more embodiments, the task of ultra-shallow doping of the upper end portions214,215of the source and drain electrodes209,210may include a task of activation annealing the upper end portions214,215.

With reference now toFIG. 3E, the method of forming the hNS FET200according to one embodiment of the present disclosure includes a task of selectively etching the sacrificial poly gate208and the remainder of each of the sacrificial crystalline layers202(i.e., the method includes removing the sacrificial poly gate208and the remainder of each of the sacrificial crystalline layers202by selective etching). The task of selectively etching the sacrificial poly gate208and the sacrificial crystalline layers202does not affect the layers203,205of CBM or the internal spacers. Accordingly, following the task of selectively etching the sacrificial poly gate208and the sacrificial crystalline layers202, the layers203,205of CBM and the internal spacers remain intact. In one or more embodiments, the material of the sacrificial crystalline layers202may be sufficiently different than the material of the channel region213to enable high-selectivity etching of the sacrificial crystalline layers202but not the channel region213(e.g., the sacrificial crystalline layers202may be formed of InyGa1-yAs or InyGa1-ySb and the channel regions213may be formed of InxGa1-xAs or InxGa1-xSb, where the composition parameter “y” is sufficiently different from the composition parameter “x” to enable selective etching of the sacrificial crystalline layers202but not the channel regions213). In one or more embodiments, the sacrificial crystalline layers202may be formed of InP, InGaP, InAlAs, or AlAsSb, where the material is chosen to be selectively etchable relative to both the layers203,205of CBM and the channel regions213.

With reference now toFIG. 3F, the method of forming the hNS FET200according to one embodiment of the present disclosure includes a task of performing a timed selective etch to completely remove portions of the layers203,205of CBM between the spacers206,207(i.e., completely removing portions of the layers203,205of CBM above and below the channel regions213). In one or more embodiments, the task of performing the timed selective etch may remove a small portion of each of the layers203,205of CBM underneath the spacers206,207(e.g., the timed selective etch may remove approximately 2 nm of the inwardly-facing portion of each layer203,205of CBM underneath the spacers206,207). Following the task of performing the timed selective etch, all or substantially all of the portions of the layers203,205of CBM at the extension regions211,212of the source and drain electrodes209,210underneath the spacers206,207, respectively, remain intact. In one or more embodiments, the task of performing a timed selective etch may be performed to reduce the thickness of the layers203,205of CBM at the channel regions213, but not completely remove the portions of the layers203,205of CBM at the channel regions213. For example, in one or more embodiments in which the layers203,205of CBM in the initial stack201each have a thickness from approximately 3 nm to approximately 5 nm, the timed selective etch may be performed to reduce the thickness of the portions of the layers203,205of CBM at the channel regions213to approximately 1 nm to approximately 2 nm while maintaining the thickness of the portions of the layer203,205of CBM at the extension regions211,212at the initial thickness of approximately 3 nm to approximately 5 nm.

With reference now toFIG. 3G, the method of forming the hNS FET200according to one embodiment of the present disclosure also includes a task of forming or depositing a metal gate electrode216and an interfacial layer (IL)217(e.g., a Hi-k gate oxide layer) for each channel region213. The metal gate electrodes216and the ILs217are deposited in regions that were previously occupied by portions of the sacrificial crystalline layers202and the layers203,205of CBM extending between the spacers206,207(i.e., the metal gate electrodes216and the ILs217are deposited in cavities that were formed during the tasks of etching the sacrificial crystalline layers202and the layers203,205of CBM, as illustrated inFIGS. 3E and 3F). The task of forming or depositing the gate electrodes216and the ILs217may be performed with any suitable manufacturing process or technique known in the art or hereinafter developed. Although in the illustrated embodiment, method includes depositing or forming three gate electrodes216and three corresponding ILs217, in one or more embodiments, the method may include forming or depositing any other suitable number of gate electrodes and ILs depending on the desired size of the hNS FET200. With reference now toFIG. 3H, the method of forming the hNS FET200according to one embodiment of the present disclosure also includes a task of forming electrical contacts218,219on the highly-doped upper end portions214,215of the source and drain electrodes209,210, respectively, to complete the hNS FET200.

In one or more embodiments, the source and drain electrodes209,210may be formed of a different material than the extension regions211,212and/or the channel region213depending on the requirements of the metal-semiconductor contact. For example, in one embodiment in which the channel region213is formed of InxGa1-xAs, the source and drain electrodes209,210may be formed of InyGa1-yAs, where y<x. In one or more embodiments, the source and drain electrodes209,210may be formed of InAs.

The tasks described above for forming the hNS FET may be performed in the order described or in any other suitable sequence. Additionally, the method described above is not limited to the tasks described. Instead, one or more of the tasks described above may be absent and/or one or more additional tasks may be performed.

A method of forming a horizontal sheet (hNS) field effect transistor (FET) according to another embodiment of the present disclosure includes forming or obtaining a standard hNS stack including an alternating arrangement of sacrificial crystalline layers and channel layers. Unlike the initial stack described above according to the method depicted inFIGS. 3A-3H, the initial stack according this embodiment does not include layers of crystalline barrier material (CBM). The method also includes a task of etching the initial stack to form regions for depositing internal spacers. The method also includes a task of forming one or more layers of CBM at extension regions of the source and drain electrodes. The one or more layers of CBM may be formed by epitaxially re-growing the layers of CBM in the extension regions of the source and drain electrodes. The method further includes a task of depositing the internal spacers after the task of epitaxially re-growing the layers of CBM in the extension regions of the source and drain electrodes.