Through silicon via and method of forming the same

The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a through silicon via (TSV) and a method of forming the same, and more particularly, to a TSV having a buffer layer and a method of forming the same.

2. Description of the Prior Art

In the modern society, the micro-processor systems comprising integrated circuits (IC) are ubiquitous devices, being utilized in diverse fields such as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increase of original applications for electronical products, the IC devices are becoming smaller, more delicate and more diversified.

As well known in the art, an IC device is produced from dies that are fabricated by conventional semiconductor manufacturing processes. The process for manufacturing a die starts with a wafer: first, different regions are marked on the wafer; secondly, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are used to form the needed circuit trace(s); then, each region of the wafer is separated to form a die, and packaged to form a chip; finally, the chip is attached onto a board, a printed circuit board (PCB), for example, and the chip is electrically coupled to the pins on the PCB. Thus, each function on the chip can be performed.

In order to evaluate the functions and the efficiency of the chip and increase the capacitance density to accommodate more IC components in a limited space, many semiconductor package technologies built up each die and/or chip by stacking, for example, Flip-Chip technology, Multi-chip Package (MCP) technology, Package on Package (PoP) technology and Package in Package (PiP) technology. Besides these technologies, a “Through Silicon Via (TSV)” technique has been developed in recent years. TSV can improve the interconnections between chips in the package so as to increase the package efficiency. However, since TSV is usually made of copper, which coefficient of thermal expansion (CTE) and the tensile modulus are very different from those of the silicon substrate, a lot of problems arise.

SUMMARY OF THE INVENTION

The present invention therefore provides a TSV having a buffer layer that has a buffer environment between the conductive electrode and the substrate.

According to one embodiment, the present invention provides a TSV disposed in a substrate having a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The buffer layer is disposed on the surface of the barrier layer. The conductive electrode is disposed on the surface of the buffer layer and completely fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface.

According to another embodiment, the present invention provides a method of forming a TSV. A substrate is provided. The substrate includes a first surface and a second surface opposite to the first surface. Then, an opening is formed on the first surface of the substrate. An insulation layer is formed on the surface of the opening and a barrier layer is formed on the surface of the insulation layer. A buffer layer is formed on the surface of the barrier layer, and a conductive electrode is formed on the barrier layer to completely fill the opening. Lastly, a planarization process is performed upon the second surface of the substrate by using the buffer layer as a stop layer.

According to another embodiment, the present invention provides another method of forming a TSV. First, a substrate is provided. The substrate has a first surface and a second surface opposite to the first surface. Then, a dielectric layer is formed on the first surface of the substrate and an opening is formed in the dielectric layer and the substrate. Next, an insulation layer is formed on the surface of the opening and a contact hole is formed in the insulation layer and the dielectric layer; Subsequently, a buffer layer is formed on the substrate, wherein the buffer layer completely fills the contact hole and covers the surface of the insulation layer in the hole, such that the buffer layer in the contact hole becomes a contact via. Next, a conductive electrode layer is formed on the surface of the buffer layer to completely fill with the opening. Lastly, a planarization process is performed upon the second surface of the substrate to expose the buffer layer.

In the present invention, since the TSV includes a barrier layer and a buffer layer, an outstanding buffer environment and a high conductivity can be provided to the conductive electrode.

DETAILED DESCRIPTION

To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer toFIG. 1toFIG. 9.FIG. 1toFIG. 9are illustrating schematic diagrams of the method of forming the TSV in the present invention. As shown inFIG. 1, a substrate300is provided. The substrate300may be a mono-crystalline silicon substrate, a gallium arsenide substrate or other kinds of substrates which are well known in the art. The substrate300includes a first surface302and a second surface304disposed at the opposite side of first surface302. In one embodiment, the thickness of the substrate300is substantially between 700 and 1000 micro meters (μm). Then, an opening306is formed in the substrate300on the side of the first surface302. The forming method, can include a dry etching step for example. In one embodiment, the aperture of the opening306is substantially between 5 and 10 μm, and the depth thereof is substantially between 50 and 100 μm. However, the forming method and the size of the opening306are not limited thereto and can be adjusted according to different designs of the products.

As shown inFIG. 2, an insulation layer308is formed on the first surface302of the substrate300to at least cover the surface of the opening306. The insulation layer308can include various kinds of insulation materials, such as SiO2. The thickness of the insulation layer308is substantially between 0.5 μm and 1.5 μm, preferably 1 μm. Subsequently, a barrier layer310is formed on the insulation layer308to at least cover the surface of the insulation layer308in the opening306. The barrier layer310may includes Ti/TiN or Ta/TaN, but is not limited thereto. The thickness of the barrier layer310is substantially between 0.005 μm and 0.02 μm, preferably 0.01 to 0.02 μm.

As shown inFIG. 3, a buffer layer312is formed on the barrier layer310to at least cover the surface of the barrier layer310in the opening306. In one preferred embodiment, the buffer layer312includes tungsten (W) and the thickness thereof is substantially between 0.05 μm and 0.2 μm, preferably 0.1 μm.

As shown inFIG. 4, a conductive electrode layer314is formed on the buffer layer312by an electroplating process for example. The buffer layer312is formed on the first surface302of the substrate300and completely fills the opening306. In one preferred embodiment, the conductive electrode layer314includes copper (Cu) and the thickness filled in the opening306is substantially 10 μm.

As shown inFIG. 5, a planarization process is performed upon the first surface302of the substrate300. For instance, a chemical mechanical polish (CMP) process or an etching back process is performed to remove the conductive electrode layer314on the first surface302by using the buffer layer312as a stop layer to level the conductive electrode layer314with the buffer layer312. The conductive electrode layer314in the opening306thus becomes a conductive electrode316.

As shown inFIG. 6, another planarization process is performed upon the first surface302of the substrate300to remove the buffer layer312and the barrier layer310outside of the opening306. The buffer layer312and the barrier layer310can be removed in one single planarization step or in two separated planarization steps. For example, a CMP process can be carried out to remove the buffer layer312and an etching step can be carried out to remove the barrier layer310. In one embodiment, the insulation layer308can be kept, while in another embodiment, the insulation layer308can be removed.

As shown inFIG. 7, a redistribution layer (RDL)318and a bumper320are formed on the first surface302of the substrate300. The RDL318and the bumper320are electrically connected to the conductive electrode316to provide a pathway for signal input/output.

As shown inFIG. 8, a planarization process is performed upon the second surface304of the substrate300. It is one salient feature of the present invention that the buffer layer312serves as a stop layer in the planarization process. That is, in the planarization process, a part of the substrate300, a part of the insulation layer308and a part of the barrier layer310are removed, while the conductive electrode316is not removed and not exposed in this planarization process. In another embodiment, another insulation layer324, another RDL326and another bumper328can be formed on the second surface304of the substrate300to electrically connect the buffer layer312to the second surface304, as shown inFIG. 9.

It should be noted that, the above-mentioned description uses the front side via-last process as an example. That is, after the front-end-of-line (FEOL) and the back-end-of-line (BEOL) processes, the opening306is formed through an etching process or a laser process, and the insulation layer308, the barrier layer310, the buffer layer312and the conductive electrode316are then sequentially formed. Subsequently, a planarization process is carried out and the RDL318and the bumper32oare formed to electrically connect to the conductive electrode316. Besides, in another embodiment, the present invention can be formed through a via middle process, which is performed between the FEOL and the BEOL processes, so that the RDL318and the bumper320can be omitted. That is, after forming the TSV322, the BEOL process is performed to form the metal interconnection system and the contact pads which are electrically connected to the TSV to provide pathways for signal input/output. In another embodiment, the present invention can also be formed through a backside via-last process.

Please refer toFIG. 8again, the present invention provides a TSV322structure. The TSV322is disposed in a via opening307in the substrate300(In this step, the opening306becomes a via opening307that penetrates through the first surface302and the second surface304). The TSV322includes an insulation layer308, a barrier layer310, a buffer layer312and a conductive electrode316. The insulation layer308is disposed on the surface of the via opening307. The barrier layer310is disposed on the surface of the insulation layer308. The buffer layer312is disposed on the surface of the barrier layer310. The conductive electrode316is disposed on the surface of the buffer layer312and completely fills the via opening307. The buffer layer312further covers a surface of the conductive electrode316at the side of the second surface304and levels with the second surface304to make the conductive electrode316not exposed to the second surface304.

In the present invention, since the buffer layer312composed of tungsten is disposed between the conductive electrode316and the substrate300, a lot of advantages can be obtained. For example, the CTE of the silicon is about 2.3 ppm/K, the CTE of the tungsten is about 4.4 ppm/K, and the CTE of the copper is about 17 ppm/K. When placing the buffer layer312composed of tungsten between the conductive electrode316composed of copper and the substrate300composed of silicon, the buffer layer312can provide a buffer environment for the conductive electrode316, and the problem of silicon cracks due to the great difference in CTE in conventional arts can be prevented. Besides, the Young's Modulus of silicon is about 130 GPa, the Young's Modulus of tungsten is about 400 GPa, and the Young's Modulus of copper is about 110 GPa. The buffer layer312composed of tungsten having a higher Young's Modulus can therefore provide physical protection to the conductive electrode316. Furthermore, since the buffer layer312is disposed on a surface of the conductive electrode316at the side of the second surface304, it can also prevent the contamination of the copper from the substrate300. It is worth noting that the present embodiment shows that the conductive electrode316is made of copper while the buffer layer312is made of tungsten. However, to one of ordinary skills in the art, the buffer layer312can be of other materials that can be matched with the conductive electrode316and the substrate300, and can be adjusted according to the materials of the conductive electrode316and the substrate300.

In addition, the TSV322in the present invention also provides a barrier layer310to increase the adhesiveness between the insulation layer308, the buffer layer312and the conductive electrode316. Since the barrier layer310includes Ti/TiN which has a Young's Modulus of about 115 GPa, it is unable to provide the buffer function when being used alone without the buffer layer312. In another aspect, when increasing the thickness of the buffer layer312, the conductivity of the TSV322will be reduced. Thus, the present invention provides the TSV322structure containing both the buffer layer312and the barrier layer310, which provides good buffer environment for the conductive electrode316and also improves the conductivity thereof. In one preferred embodiment of the present invention, a ratio of the thickness of the buffer layer312and the thickness of the conductive electrode316is substantially greater than 0.001, preferably between 0.01 and 1, and a ratio of the thickness of the barrier layer310and the thickness of the conductive electrode316is substantially between 0.001 and 0.01.

In another embodiment, when the TSV is formed in a via middle process, it can be formed simultaneously with contact via. Please refer toFIG. 10toFIG. 15, illustrating schematic diagrams of the method of forming the TSV according to another embodiment of the present invention. As shown inFIG. 10, a substrate400is provided. The substrate400may be a mono-crystalline silicon substrate, a gallium arsenide substrate or other kinds of substrates which are well known in the art. The substrate400includes a first surface402and a second surface404disposed at the opposite side of first surface402. In one embodiment, the thickness of the substrate400is substantially between 700 and 1000 micro meters. Subsequently, a semiconductor device is formed on the first surface402of the substrate400, such as a metal oxide semiconductor (MOS) device502, which includes a gate504, a gate oxide506, a spacer508and a source/drain region510, for example. These elements of the MOS device502are well-known in the art and are omitted in description. However, the MOS device502may include other semiconductor elements such as salicide or epitaxial layer, but is not limited thereto. In another embodiment, the semiconductor device can still be other types of devices, such as planar transistor, non-planar transistor, capacitor, thin-film-transistor (TFT) or even photo-sensor, optical transmission device or micro-electrical mechanical system (MEMS), and are not limited thereto. Next, a dielectric layer512is formed on the substrate400and covers the MOS device502. The dielectric layer512may include SiO2or other suitable dielectric materials. Then, an opening406is formed in the dielectric layer512and the substrate400. The opening406penetrates through the dielectric layer512and further reaches to the substrate400. In one embodiment, the aperture of the opening406is substantially between 5 and 10 μm, and the depth thereof is substantially between 50 and 100 μm. The forming method, for example, can include a dry etching step. However, the forming method and the size of the opening406are not limited thereto and can be adjusted according to different designs of the products.

As shown inFIG. 11, an insulation layer408is formed on the substrate400. The insulation layer408is formed on the surface of the dielectric layer512and conformally formed on the surface of the opening406but does not completely fill the opening406. The insulation layer408can include various kinds of insulation materials, such as SiO2. The thickness of the insulation layer408is substantially between 0.5 μm and 1.5 μm, preferably 1 μm.

As shown inFIG. 12, at least a contact hole410is formed in the insulation layer408and the dielectric layer512, exposing a part of the MOS device502, such as the gate504and the source/drain region510. Next, a buffer layer412is formed on the substrate400. The buffer layer412is formed along the surface of the insulation layer412and is completely filling the contact hole410. In detail, the buffer layer412is formed conformally on the surface of the insulation layer408in the opening406, but does not completely fill the opening406. In one preferred embodiment, the buffer layer412includes tungsten (W) and the thickness thereof is substantially between 0.05 μm and 0.2 μm, preferably 0.1 μm. Since the buffer layer412in the present invention is made of tungsten, in the subsequent steps, the buffer layer412in the contact hole410will become a contact via411, while the buffer layer412in the opening406serves as a buffer material between the conductive electrode (Cu electrode for example) and the insulation layer408in the TSV.

As shown inFIG. 13, a conductive electrode layer414is formed on the buffer layer412by an electroplating process for example. The buffer layer412is formed on the first surface402of the substrate400and completely fills the opening406. In one preferred embodiment, the conductive electrode layer414includes copper (Cu) and the thickness filled in the opening306is substantially 10 μm.

As shown inFIG. 14, a planarization process is performed upon the first surface402of the substrate400to remove the conductive electrode layer414and the buffer layer412on the insulation layer408, which serves as a stop layer in the planarization process. The conductive electrode layer414and the buffer layer412can be removed in one single planarization step or in two separated planarization steps. For example, a CMP process can be carried out to remove the conductive electrode layer414and an etching step can be carried out to remove the buffer layer412. In one embodiment, the insulation layer408can be kept, while in another embodiment, the insulation layer408and a part of the buffer layer412and conductive electrode layer414therein can be removed,

As shown inFIG. 15, a metal interconnect system516is formed on the dielectric layer512on the substrate400to electrically connect the contact via411. The metal interconnect system516, for instance, may include a plurality of metal layers and a plurality of dielectric layers (not shown). Finally, another planarization process is carried out upon the second surface404of the substrate400. In one embodiment, the buffer layer412serves as the stop layer during the planarization process, meaning that the buffer layer412will be exposed after the planarization process. In another embodiment, the conductive electrode layer414serves as the stop layer during the planarization process, meaning that the conductive electrode layer414will be exposed after the planarization process. In addition, in another embodiment, the planarization process can be carried out before forming the metal interconnect system516. After the steps shown above, the TSV422in the present embodiment can be completed.

In conventional arts, it is known that the contact via and the TSV are formed separately. Additional planarization stop layer and additional barrier layer such as Ti/TiN layer are required in conventional TSV forming methods. Therefore, in the present embodiment, it is one salient feature that the buffer layer412including tungsten is utilized to simultaneously form the contact via411and the buffer material in the TSV. Consequently, the forming method can be streamlined comparing to conventional arts. Moreover, since the buffer layer412can provide the barrier function between the conductive electrode layer414and the insulation layer408, no additional barrier layer is required in the present embodiment. On the other hand, the planarization process upon the first surface402of the substrate400utilizes the insulation layer408as the stop layer, which is able to provide a good planarization stop function. It is recognized that the method of simultaneously forming the TSV and the contact via can provide a relatively simple steps and can improve the yields.