Semiconductor structure and manufacturing method for the same and ESD  circuit

A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

BACKGROUND

1. Technical Field

The disclosure relates in general to a semiconductor structure and a manufacturing method for the same, and more particularly to an ESD circuit.

2. Description of the Related Art

The electrostatic discharge (ESD) is a phenomenon of electrostatic charge transfer between different objects with the accumulation of the electrostatic charges. The ESD occurs for an extremely short period of time, which is only within the level of several nano-seconds (ns). A very high current is generated in the ESD event, and the value of the current is usually several amperes. Consequently, once the current generated by the ESD flows through a semiconductor integrated circuit, the semiconductor integrated circuit is usually damaged. Thus, the ESD protection device between power lines has to provide a discharge path to prevent the semiconductor integrated circuit from being damaged when the high-voltage (HV) electrostatic charges are generated in the semiconductor integrated circuit.

SUMMARY

A semiconductor structure is provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

A manufacturing method for a semiconductor structure is provided. The method comprises following steps. A first doped region having a first type conductivity is formed in a substrate. A second doped region having a second type conductivity opposite to the first type conductivity is formed in the substrate. A third doped region having the first type conductivity is formed in the second doped region. The first doped region and the third doped region are separated by the second doped region. A field plate structure is formed on the second doped region.

An ESD circuit is provided. The circuit comprises a first BJT and a resistor. The resistor is coupled between a base and an emitter of the first BJT.

DETAILED DESCRIPTION

FIG. 1illustrates a top view of a semiconductor structure in one embodiment.FIG. 2illustrates a cross-section view of the semiconductor structure drawn along AB line inFIG. 1.FIG. 3illustrates a top view of the semiconductor structure in one embodiment.FIG. 4illustrates a cross-section view of the semiconductor structure drawn along CD line inFIG. 3.FIG. 5illustrates a top view of the semiconductor structure in one embodiment.FIG. 6illustrates a cross-section view of the semiconductor structure drawn along EF line inFIG. 5.FIG. 7illustrates a top view of the semiconductor structure in one embodiment.FIG. 8illustrates a cross-section view of the semiconductor structure drawn along GH line inFIG. 7.FIG. 9andFIG. 10illustrate equivalent circuits of the semiconductor structure according to embodiments.

Referring toFIG. 2, the semiconductor structure comprises a first doped region12, a second doped region14and a third doped region16. The first doped region12may comprise a doped portion18, a doped portion20and a doped portion22having a first type conductivity such as N type conductivity. The second doped region14may comprise a doped portion24and a doped portion26having a second type conductivity such as P type conductivity. The third doped region16may comprise a doped portion28having the first type conductivity such as N type conductivity. The first doped region12and the third doped region16are separated by the second doped region14.

In one embodiment, the first doped region12and the second doped region14are formed on a substrate layer50. The substrate layer50may be a bulk material such as silicon, or formed by a doping method or an epitaxial method. The doped portion22of the first doped region12is formed on the substrate layer50. The doped portion22may be formed by a doping method or an epitaxial method. The doped portion22may be a buried layer, a deep well, or a stacked structure having multi layers. The doped portion20of the first doped region12and the doped portion26of the second doped region14may be respectively formed by doping a substrate with using a patterned mask layer (not shown). The doped portion18of the first doped region12may be formed by doping the doped portion20with using a patterned mask layer (not shown). The doped portion24of the second doped region14and the doped portion28of the third doped region16may be respectively formed by doping the doped portion26with using a patterned mask layer (not shown). The doped portion18, the doped portion22, the doped portion24and the doped portion28may be heavily doped. In other embodiments, the doped portion22is omitted.

The dielectric structure42is formed on the first doped region12and the second doped region14. The dielectric structure42may comprise a first dielectric portion44and a second dielectric portion52. The first dielectric portion44may be formed on the first doped region12and the second doped region14. The second dielectric portion52may be formed on the second doped region14. The first dielectric portion44and the second dielectric portion52are not limited to LOCOS as shown inFIG. 2, and may be STI. For example, the first dielectric portion44and the second dielectric portion52may comprise an oxide such as silicon oxide.

A field plate structure36is formed on the second doped region14and the first dielectric portion44. The field plate structure36may comprise a dielectric layer38and a conductive layer40formed on the dielectric layer38. The conductive layer40may comprise a metal, a polysilicon or a silicide. In one embodiment, the conductive layer40may be formed by a polysilicon of a single layer or multi layers. In another embodiment, the conductive layer40is a stacked structure formed by various materials.

In one embodiment, as shown inFIG. 2, the field plate structure36is coupled to the second doped region14. An anode32is coupled to the doped portion18of the first doped region12. A cathode34is coupled to the field plate structure36and the doped portion28of the third doped region16.

For example, the first doped region12, the second doped region14and the third doped region16form first bipolar junction transistors (BJTs)46A,46B of a first element type such as NPN BJT. The first doped region12functions as a collector of the first BJTs46A,46B. The second doped region14functions as a base of the first BJTs46A,46B. The third doped region16functions as an emitter of the first BJTs46A,46B.

The resistor30is coupled between the doped portion24and the doped portion28. Particularly, the resistor30is coupled to a base and an emitter of the first BJTs46A,46B. In one embodiment, the resistor30may be a parasitic resistor generated due to the field plate structure36. In other embodiments, the resistor30may be formed by other resistor elements.

In one embodiment, the semiconductor structure is used as an ESD device. The resistor30coupled to the first BJTs46A,46B (or a parasitic resistor generated due to the field plate structure36) can be used for providing a HV ESD. A trigger voltage of the semiconductor structure can be adjusted by the field plate structure36. Using the field plate structure36can increase an operating voltage and a breakdown voltage of the semiconductor structure. The breakdown voltage and the trigger voltage of the semiconductor structure can be controlled by adjusting a width of the doped portion22of the first doped region12.

In embodiments, the breakdown voltage of the semiconductor structure is close to the HV device operation voltage. The trigger voltage is lower than the breakdown voltage of the HV device. The holding voltage is high. Therefore, for example, it is easier to avoid latching up for the semiconductor structure of the embodiment than a conventional silicon controlled rectifier (SCR).

In one embodiment, the semiconductor structure may comprise a MOS such as a NMOS or a PMOS, or a field transistor. For example, the first BJTs46A,46B can be designed to be a MOS such as a NMOS by other suitable structures. The total design area for the ESD device in embodiments is smaller a conventional ESD device comprising a diode for example, in a condition that the ESD devices have substantially equivalent efficiency. The semiconductor structure is insensitive to routing.

The semiconductor structure can be manufactured by a standard BCD process. Therefore, an additional mask or process is not need. The semiconductor structure of embodiments can be applied to any suitable process and operation voltage (HV or LV device), such as a general DC circuit operation.

The semiconductor structure as shown inFIG. 4differs from the semiconductor structure as shown inFIG. 2in that, the second doped region114and a fourth doped region154are separated by the first doped region112. The fourth doped region154has the second type conductivity such as P type conductivity. In one embodiment, the fourth doped region154may be formed by doping the doped portion120of the first doped region112with using a patterned mask layer (not shown), and adjacent to the doped portion118of the first doped region112. The anode132is coupled to the fourth doped region154. The fourth doped region154may be heavily doped.

Referring toFIG. 4, the fourth doped region154, the first doped region112and the second doped region114form a second BJT156of a second element type such as a PNP BJT. The fourth doped region154functions as an emitter of the second BJT156. The first doped region112functions as a base of the second BJT156. The second doped region114functions as a collector of the second BJT156. The first BJTs146A,146B are electrically connected to the second BJT156in parallel. One end of the resistor130is coupled to a base of the first BJTs146A,146B. Another end of the resistor130is coupled between the emitter of the first BJTs146A,146B and the collector of the second BJT156.

In one embodiment, the semiconductor structure is used as an ESD device. The resistor130, coupled to the first BJTs146A,146B, the second BJT156, or a parasitic resistor generated due to the field plate structure136, and the first BJTs146A,146B and the second BJT156electrically connected in parallel can provide a HV ESD protection. The first BJTs146A,146B and the second BJT156are incorporated into one ESD device. Therefore, the metal wiring and the ESD device layout area are reduced.

In one embodiment, the semiconductor structure may comprise MOSs or field transistors having opposite element types such as an NMOS and a PMOS. For example, the first BJTs146A,146B may be designed to be one kind of MOS such as a NMOS and the second BJT156may be designed to be another kind of MOS such as a PMOS by using other structures.

The semiconductor structure as shown inFIG. 6differs from the semiconductor structure as shown inFIG. 2in that the third doped region216comprises a doped portion228A and a doped portion228B having the first type conductivity such as N type conductivity and separated from each other.

A separator structure258is formed on the second doped region214between the doped portion228A and the doped portion228B. In one embodiment, the separator structure258may comprise a dielectric layer260and a conductive layer262formed on the dielectric layer260. The conductive layer262may comprise a metal, a polysilicon or a silicide. In one embodiment, the conductive layer262is formed by a polysilicon, and the separator structure258and the field plate structure236form resistors electrically connected in parallel. A trigger voltage of the semiconductor structure can be adjusted by the separator structure258.

Using the separator structure258and the doped portion228A and the doped portion228B separated by the separator structure258results in a multi-emitter BJT, comprising the first BJTs246A,246B,246C. In embodiments, the semiconductor structure can be early turned on by an additional bias to the separator structure258or the base.

The semiconductor structure as shown inFIG. 8differs from the semiconductor structure as shown inFIG. 6in that the second doped region314and the fourth doped region354are separated by the first doped region312. The fourth doped region354has the second type conductivity such as P type conductivity. In one embodiment, the fourth doped region354is formed by doping the doped portion320of the first doped region312with using a patterned mask layer (not shown), and adjacent to the doped portion318of the first doped region312. The anode332is coupled to the fourth doped region354. The fourth doped region354may be heavily doped.

Referring toFIG. 8, the fourth doped region354, the first doped region312and the second doped region314form a second BJT356of a second element type such as a PNP BJT. The fourth doped region354functions as an emitter of the second BJT356. The first doped region312functions as a base of the second BJT356. The second doped region314functions as a collector of the second BJT356. The first BJTs346A,346B are electrically connected to the second BJT356in parallel. One end of the resistor330is coupled to a base of the first BJTs346A,346B. Another end of the resistor330is coupled between the emitter of the first BJTs346A,346B and the collector of the second BJT356.

In one embodiment, the semiconductor structure is used as an ESD device. The resistor330, coupled to the first BJTs346A,346B, the second BJT356, or a parasitic resistor generated due to the field plate structure336, and the first BJTs346A,346B and the second BJT356electrically connected in parallel can provide a HV ESD protection. The first BJTs346A,346B and the second BJT356are incorporated into one ESD device. Therefore, the metal wiring and the ESD device layout area are reduced.

In one embodiment, the semiconductor structure may comprise MOSs or field transistors having opposite element types such as an NMOS and a PMOS. For example, the first BJTs346A,346B may be designed to be one kind of MOS such as a NMOS and the second BJT356may be designed to be another kind of MOS such as a PMOS by using other structures.

In embodiments, the semiconductor structure can be used as an ESD device, having circuits as shown inFIG. 9andFIG. 10. Referring toFIG. 9, the resistor430is coupled between the base and the emitter of the first BJT446. The anode432and the cathode434are respectively coupled to the base and the emitter of the first BJT446. The circuit as shown inFIG. 10differs from the circuit as shown inFIG. 9in that the resistor430is coupled to a node between the emitter of the first BJT546and the collector of the second BJT556.

According to embodiments of the present disclosure, the semiconductor structure has at least following advantages. The resistor (or the parasitic resistor generated due to the field plate structure) coupled to the BJT, and the first BJT and the second BJT electrically connected in parallel can help to provide a HV ESD protection. The separator structure can be used for adjusting a trigger voltage or increasing an operation voltage and a breakdown voltage of the semiconductor structure. A width of the doped region used as the buried layer of the first doped region can be adjusted for controlling the breakdown voltage and the trigger voltage of the semiconductor structure. Using the separator structure and the third doped regions separated from each other can result in a multi-emitter BJT. The semiconductor structure can be early turned on by an additional bias to the separator structure or the base.