MEMORY DEVICE AND METHOD OF OPERATING THE SAME

The present technology relates to an electronic device. A memory device performing efficient soft decoding by reducing the number of data provided to a memory controller includes a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer includes a plurality of latches and a read data operating component configured to generate a soft bit by logically operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2019-0100583, filed on Aug. 16, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

Field of Invention

The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the same.

Description of Related Art

A storage device is a device for storing data under control of a host device such as a computer, a smart phone, or a smart pad. The storage device includes a device for storing data into a magnetic disk such as a hard disk drive (HDD), a device that stores data in a semiconductor memory such as a solid state drive (SSD), or a memory card, in particular, a non-volatile memory.

The storage device may include a memory device for storing data and a memory controller for storing data into the memory device. The memory device may be classified into a volatile memory and a non-volatile memory. Here, the non-volatile memory includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EPM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM) and the like.

SUMMARY

An embodiment of the present disclosure provides a memory device and a method of operating the same capable of performing efficient soft decoding by reducing the number of data output to a memory controller.

A memory device according to an embodiment of the present disclosure may include a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer may include a plurality of latches, and a read data operating component configured to generate a soft bit by operating soft data, which are data read from the memory cell array, and to provide the soft bit to a memory controller, in a second read operation performed when a first read operation has failed.

A method of operating a memory device according to an embodiment of the present disclosure is a method of operating a memory device comprising a memory cell array and a page buffer connected to the memory cell array through a bit line. The method may include performing a first read operation, changing a read voltage to perform a second read operation when the first read operation has failed, logically operating soft data which are data read from the memory cell array in the second read operation to generate at least one soft bit and providing the at least one soft bit to a memory controller.

A memory device according to an embodiment of the present disclosure may include a memory cell array and a page buffer connected to the memory cell array through a bit line. The page buffer may include a plurality of latches and a plurality of transistors, and wherein the page buffer outputs a soft bit generated by logically operating data provided to a second node connected to a latch included in the page buffer among the plurality of latches, according to data provided to a first node connected to the bit line.

A method of correcting error data transferring from a memory device to a memory controller, the method may include performing, by the memory controller, a first error correction for the error data, requesting, by the memory controller, the memory device for soft data, when the first error correction for the error data has failed, reading, by the memory device, the predetermined number of soft data, performing, by the memory device, a logic operation on the predetermined number of the soft data to generate soft bits less than the number of the soft data, wherein the soft bit indicates logically operated data, transferring the soft bits from the memory device to the memory controller and performing, by the memory controller, a second error correction on the soft bits.

According to the present technology, when an error correction operation for correcting an error included in read data is failed, a read operation corresponding to a soft read command is performed, and only a soft bit generated based on a result of performing the read operation is output to a memory controller. Therefore, soft decoding may be performed without outputting all read data.

These and other features and advantages of the present disclosure will become apparent to those skilled in the art of the invention from the following detailed description in conjunction with the following drawing.

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments according to the concept which are disclosed in the present specification or application are illustrated only to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be carried out in various forms and the descriptions are not limited to the embodiments described in the present specification or application.

Hereinafter, an embodiment of the present disclosure will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical spirit of the present disclosure.

FIG. 1is a block diagram illustrating a storage device in accordance with some embodiments of the present disclosure.

Referring toFIG. 1, the storage device50may include a memory device100and a memory controller200.

The storage device50may store data under control of a host300such as a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC, or an in-vehicle infotainment system.

The storage device50may be manufactured as one of various types of storage devices according to a host interface for communicating with the host300. For example, the storage device50may be configured as any one of various types of storage devices including a multimedia card such as a SSD, an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card such as a SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a storage device such as a personal computer memory card international association (PCMCIA) card, a storage device such as a peripheral component interconnection (PCI) card, a storage device such as a PCI express (PCI-E) card, a compact flash (CF) card, a smart media card, and a memory stick.

The storage device50may be manufactured as any one of various types of packages. For example, the storage device50may be manufactured as any one of various types of package types, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The memory device100may store data. The memory device100may operate in response to control of the memory controller200. The memory device100may include a memory cell array including a plurality of memory cells for storing the data. The memory cell array may include a plurality of memory blocks. Each of the memory blocks may include a plurality of memory cells, and the plurality of memory cells may form a plurality of pages. In an embodiment, the page may indicate a basic unit for storing data in the memory device100or reading data stored in the memory device100. The memory block may be a basic unit for erasing data.

The memory device100may include a page buffer group123including a plurality of page buffers. Each of the plurality of page buffers may be connected to the memory cell array through a bit line. In an embodiment of the present disclosure, when data stored in the memory cell array is transmitted to the page buffer through each bit line during a read operation, the page buffer may temporarily store the transmitted data.

In an embodiment of the present disclosure, when a correction of an error included in read data received from the memory device100is failed, the memory device100may receive a soft read command from the memory controller200and may perform a read operation using a read voltage level different from a previous read voltage. When a result of performing the read operation using the different read voltage is output to the memory controller200, the memory controller200may perform an error correction operation of correcting the error of the read data again.

In an embodiment of the present disclosure, the memory device100may perform the read operation with the different read voltage level in response to the soft read command received from the memory controller200to output data generated on the basis of the read operation to the memory controller200.

For example, after setting initial data, the memory device100may change the initial data according the read data to output the changed data to the memory controller200. Alternatively, the memory device100may generate new data obtained by performing a specific operation (for example, an exclusive-NOR operation) on the read data to output the new data to the memory controller200.

Therefore, in some embodiments of the present disclosure, since the memory device100outputs only the changed data or the new data without needing to output all read data, the number of data output from the memory device100to the memory controller200may be reduced. Thus, as the number of data provided to the memory controller200is reduced, the memory controller200may efficiently perform an operation of correcting an error.

In an embodiment of the present disclosure, the memory device100may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), or the like. Herein, for convenience of description, it is assumed that the memory device100is a NAND flash memory.

The memory device100may be implemented as a two-dimensional array structure or a three-dimensional array structure. Hereinafter, the three-dimensional array structure is described as an example, but the present disclosure is not limited to the three-dimensional array structure. The present disclosure may be applicable not only to a flash memory device in which a charge storage layer consists of a conductive floating gate (FG), but also to a charge trap flash (CTF) in which the charge storage layer consists of an insulating film.

In an embodiment of the present disclosure, the memory device100may operate in the same way as a single level cell (SLC) in which one data bit is stored into one memory cell. Alternatively, the memory device100may operate in a manner that stores at least two data bits into one memory cell. For example, the memory device100may operate in the same way as a multi-level cell (MLC) of storing two data bits into one memory cell, a triple level cell (TLC) of storing three data bits into one memory cell, or a quadruple level cell (QLC) of storing four data bits into one memory cell.

The memory device100may be configured to receive a command and an address from the memory controller200and access a region selected by the address in the memory cell array. That is, the memory device100may perform an operation corresponding to the command on the region selected by the address. For example, the memory device100may perform a write operation (program operation), a read operation, or an erase operation according to the received command. For example, when a program command is received, the memory device100may program data into the region selected by the address. When a read command is received, the memory device100may read data from the region selected by the address. When an erase command is received, the memory device100may erase data stored in the region selected by the address.

The memory controller200may include an error corrector210. The error corrector210may correct an error of the read data received from the memory device100. Specifically, the error corrector210may correct an error of data in which error correction is failed, using a log-likelihood ratio (LLR) or a likelihood ratio (LR) generated based on an error correction code (for example, a Bose-Chaudhuri-Hocquenghem code (BCH code), a low-density parity-check Code, or the like) or read data received from the memory device100. In an embodiment of the present disclosure, the greater an absolute value of the log-likelihood ratio (LLR) or the likelihood ratio (LR), the higher reliability of the read data.

In an embodiment of the present disclosure, when the error correction of the read data is failed in spite of the error correction operation of the error corrector210, the error corrector210may generate error information. The error information may be provided to a command generator220.

The memory controller200may include the command generator220. The command generator220may generate a command corresponding to a request received from the host300or a command corresponding to an internal operation of the memory controller200. When the memory device100receives the command from the command generator220, the memory device100may perform an operation corresponding to the command.

For example, the command generator220may generate a soft read command based on the error information received from the error corrector210and output the soft read command to the memory device100. The soft read command may be a command for instructing to perform the read operations a plurality of times using a voltage higher than a previously used read voltage and a voltage lower than the previously used read voltage. For example, if the previously used read voltage is 1V, the voltage higher than a previously used read voltage may be 1.2V and the voltage lower than the previously used read voltage may be 0.8V. That is, the next read operations may be performed based on voltages that are at a predetermined distance from the previously used read voltage.

The memory device100may perform the read operations a plurality of times based on the soft read command, and transmit results of the read operations to the memory controller200.

However, in some embodiments of the present disclosure, the memory device100may not provide all data acquired from the plurality of read operations performed according to the soft read command to the memory controller200. The memory device100may perform a logical operation on all read data acquired from the plurality of read operations to provide the result of the logical operation to the memory controller200. Since the memory device100provides only the result of the logical operation to the memory controller220, rather than all data acquired from the plurality read operations, the number of data provided from the memory device100to memory controller200may be reduced, allowing an increase of efficiency of the error correction operation of the error corrector210.

The memory controller200may control overall operations of the storage device50.

When a power voltage is supplied to the storage device50, the memory controller200may execute firmware FW. When the memory device100is configured as a flash memory device100, the memory controller200may operate firmware such as a flash translation layer (FTL) for controlling communication between the host300and the memory device100.

In an embodiment, the memory controller200may receive data and a logical block address (LBA) from the host300and convert the LBA into a physical block address (PBA) indicating an address of memory cells in which data included in the memory device100is to be stored. In addition, the memory controller200may store a logical-physical address mapping table for mapping the LBA and the PBA in a buffer memory.

The memory controller200may control the memory device100to perform the program operation, the read operation, the erase operation, or the like according to the request of the host300. For example, when a program request is received from the host300, the memory controller200may converts the program request into a program command, and may provide the program command, the PBA, and data to the memory device100. When a read request is received from the host300together with the LBA, the memory controller200may change the read request into a read command, select a PBA corresponding to the LBA, and then provide the read command and the PBA to the memory device100. When an erase request is received from the host300together with the LBA, the memory controller200may change the erase request into an erase command, select a PBA corresponding to the LBA, and then provide the erase command and the PBA to the memory device100.

In an embodiment of the present disclosure, the memory controller200may generate and transmit the program command, the address, and the data to the memory device100even without the request from the host300. For example, the memory controller200may provide a command, an address, and data to the memory device100so as to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

In an embodiment of the present disclosure, the storage device50may further include a buffer memory (not shown). The memory controller200may control data exchange between the host300and the buffer memory. Alternatively, the memory controller200may temporarily store system data for controlling the memory device100into the buffer memory. For example, the memory controller200may temporarily store data input from the host300into the buffer memory, and then transmit data temporarily stored in the buffer memory to the memory device100.

In various embodiments, the buffer memory may be used as an operation memory and a cache memory of the memory controller200. The buffer memory may store codes or commands executed by the memory controller200. Alternatively, the buffer memory may store data from the memory controller200.

In an embodiment of the present disclosure, the buffer memory may be implemented as a dynamic random access memory (DRAM) such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a DDR4 SDRAM, a low power double data rate4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), or Rambus dynamic random access memory (DRAM), or a static random access memory (SRAM).

In various embodiments of the present disclosure, the buffer memory may be connected from an outside of the storage device50. In this case, the volatile memory devices100connected to the outside of the storage device50may serve as the buffer memory.

In an embodiment of the present disclosure, the memory controller200may control at least two or more memory devices100. In this case, the memory controller200may control the memory devices100according to an interleaving scheme in order to improve operation performance.

The host300may communicate with the storage device50using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high speed interchip (HSIC), a small computer system Interface (SCSI), a peripheral component interconnection (PCI), a PCI express (PCIe), a nonvolatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multi-media card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

FIG. 2is diagram illustrating a structure of the memory device ofFIG. 1in accordance with some embodiments of the present disclosure.

Referring toFIG. 2, the memory device100may include a memory cell array110, a peripheral circuit120, and a control logic130.

The memory cell array110includes a plurality of memory blocks BLK1to BLKz. The plurality of memory blocks BLK1to BLKz may be connected to a row decoder121through row lines RL. The plurality of memory blocks BLK1to BLKz may be connected to the page buffer group123through bit lines BL1to BLn. Each of the plurality of memory blocks BLK1to BLKz includes a plurality of memory cells. In accordance with an embodiment of the present disclosure, the plurality of memory cells may be configured as non-volatile memory cells. Memory cells connected to the same word line may be defined as one page. Therefore, one memory block may include a plurality of pages.

The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

Each of the memory cells included in the memory cell array110may be configured as a single level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quadruple level cell (QLC) that stores four data bits.

The peripheral circuit120may be configured to perform the program operation, the read operation, or the erase operation on a selected region of the memory cell array110under control of the control logic130. The peripheral circuit120may drive the memory cell array110. For example, the peripheral circuit120may apply various operation voltages to the row lines RL and the bit lines BL1to BLn or discharge the applied voltages under the control of the control logic130.

The peripheral circuit120may include a row decoder121, a voltage generator122, the page buffer group123, a column decoder124, an input/output circuit125, and a sensing circuit126.

The row decoder121may be connected to the memory cell array110via the row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment of the present disclosure, the word lines may include normal word lines and dummy word lines. In an embodiment of the present disclosure, the row lines RL may further include a pipe select line.

The row decoder121may be configured to decode a row address RADD received from the control logic130. The row decoder121may select at least one memory block among the memory blocks BLK1to BLKz according to a decoded address. In addition, the row decoder121may select at least one word line of the memory block selected to apply the voltages generated by the voltage generator122to at least one word line WL according to the decoded address.

For example, during the program operation, the row decoder121may apply a program voltage to a selected word line and apply a program pass voltage of a level lower than the program voltage to an unselected word line. During the program verification operation, the row decoder121may apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line. During the read operation, the row decoder121may apply a read voltage to the selected word line and apply a read pass voltage higher than the read voltage to the unselected word line.

In an embodiment of the present disclosure, the erase operation of the memory device100may be performed for each memory block. During the erase operation, the row decoder121may select one memory block according to the decoded address. During the erase operation, the row decoder121may apply a ground voltage to the word lines connected to the selected memory block.

The voltage generator122may operate under the control of the control logic130. The voltage generator122may be configured to generate a plurality of voltages using an external power voltage supplied to the memory device100. Specifically, the voltage generator122may generate various operation voltages Vop used for the program, read, and erase operations, in response to operation signal OPSIG. For example, the voltage generator122may generate the program voltage, the verification voltage, the pass voltage, the read voltage, the erase voltage, and the like in response to the control of the control logic130.

In accordance with some embodiments of the present disclosure, the voltage generator122may generate an internal power voltage by regulating the external power voltage. The internal power voltage generated by the voltage generator122may be used as an operation voltage of the memory device100.

In accordance with some embodiments of the present disclosure, the voltage generator122may generate a plurality of voltages using the external power voltage or the internal power voltage.

For example, the voltage generator122may include a plurality of pumping capacitors that receive the internal power voltage, and may selectively activate the plurality of pumping capacitors to generate the plurality of voltages, in response to the control of the control logic130.

The generated plurality of voltages may be supplied to the memory cell array110by the row decoder121.

The page buffer group123may include first to n-th page buffers PB1to PBn. The first to n-th page buffers PB1to PBn may be connected to the memory cell array110through the first to n-th bit lines BL1to BLn, respectively. The first to n-th page buffers PB1to PBn may operate under the control of the control logic130. Specifically, the first to n-th page buffers PB1to PBn may operate in response to a page buffer control signals PBSIGNALS. For example, the first to n-th page buffers PB1to PBn may temporarily store data received through the first to n-th bit lines BL1to BLn, or may sense a voltage or a current of the bit lines BL1to BLn during the read or verification operation.

Specifically, during the program operation, when the program voltage is applied to the selected word line, the first to n-th page buffers PB1to PBn may transfer data DATA received from the input/output circuit125to the selected memory cell through the first to n-th bit lines BL1to BLn. The memory cells of the selected page may be programmed according to the transferred data DATA. During the program verification operation, the first to n-th page buffers PB1to PBn may read page data by sensing the voltage or the current received from the selected memory cells through the first to n-th bit lines BL1to BLn.

During the read operation, the first to n-th page buffers PB1to PBn may read the data DATA from the memory cells of the selected page through the first to n-th bit lines BL1to BLn, and may output the read data DATA to the input/output circuit125under the control of the column decoder124.

During the erase operation, the first to n-th page buffers PB1to PBn may float the first to n-th bit lines BL1to BLn or apply the erase voltage.

In an embodiment of the present disclosure, the first to n-th page buffers PB1to PBn may include first to n-th read data operating components123_C1to123_Cn, respectively. The first to n-th read data operating components123_C1to123_Cn may perform exclusive-NOR (XNOR) operation on read data temporarily stored in latches of the first to n-th page buffers PB1to PBn, respectively, and may output a soft bit, which indicates logically operated data, to the column decoder124. The XNOR operation may be a match check operation to check whether input values match each other.

In accordance with the some embodiments of the present disclosure, since the first to n-th page buffers PB1to PBn perform the XNOR operation on the read data from the memory cells to provide logically operated (logical NXOR) data to memory controller200, the number of data provided from the memory device100to the memory controller200ofFIG. 1may be reduced. In addition, as the number of the data provided to the memory controller200ofFIG. 1is reduced, some procedures involved in the error correction operation of the memory controller200ofFIG. 1may be omitted. Therefore, the error correction efficiency of the memory controller200ofFIG. 1may be increased.

The column decoder124may transfer data between the input/output circuit125and the page buffer group123in response to a column address CADD. For example, the column decoder124may exchange data with the first to n-th page buffers PB1to PBn through data lines DL, or may exchange data with the input/output circuit125through column lines CL.

The input/output circuit125may transfer the command CMD and the address ADDR received from the memory controller200ofFIG. 1described with reference toFIG. 1to the control logic130, or may exchange data DATA with the column decoder124.

The sensing circuit126may generate a reference current in response to a permission bit signal VRYBIT during the read operation or the verification operation, and compare a sensing voltage VPB received from the page buffer group123with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

The control logic130may output the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the permission bit VRYBIT in response to the command CMD and the address ADDR to control the peripheral circuit120. For example, the control logic130may control the read operation of the selected memory block in response to a sub block read command and the address. In addition, the control logic130may control the erase operation of the selected sub block of the selected memory block in response to the sub block erase command and the address. In addition, the control logic130may determine whether the verity operation has passed or failed in response to the pass or fail signal PASS or FAIL.

The memory cells of the memory cell array110may be programmed to any one of a plurality of program states according to data stored in each memory cell. A target program state of the memory cell may be determined as any one of the plurality of program states according to the data to be stored.

FIG. 3is a diagram Illustrating the memory block in accordance with some embodiments of the present disclosure.

Referring toFIGS. 2 and 3,FIG. 3is a circuit diagram illustrating any one memory block BLKa among the plurality of memory blocks BLK1to BLKz of the memory cell array110ofFIG. 2.

A first select line, word lines, and a second select line arranged in parallel with each other may be connected to the memory block BLKa. For example, the word lines may be arranged in parallel with each other between the first and second select lines. Herein, the first select line may indicate the source select line SSL, and the second select line may indicate the drain select line DSL.

More specifically, the memory block BLKa may include a plurality of strings connected between the bit lines BL1to BLn and a source line SL. The bit lines BL1to BLn may be connected to the strings, respectively, and the source line SL may be commonly connected to the strings. Since the strings may be configured to be identical to each other, a string ST connected to the first bit line BL1will be specifically described below, as an example.

The string ST may include a source select transistor SST, a plurality of memory cells F1to F16, and a drain select transistor DST connected in series between the source line SL and the first bit line BL1. One string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and the number of the memory cells F1to F16may be more than the ones shown in the drawing.

A source of the source select transistor SST may be connected to the source line SL and a drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells F1to F16may be connected in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in the different strings may be connected to the source select line SSL, gates of the drain select transistors DST may be connected to the drain select line DSL, and gates of the memory cells F1to F16may be connected to a plurality of word lines WL1to WL16. A group of the memory cells connected to the same word line among the memory cells included in different strings may be referred to as a physical page PPG. Therefore, the memory block BLKa may include the physical pages PPG corresponding to the number of the word lines WL1to WL16.

One memory cell may store one bit of data. This is commonly referred to as a single level cell (SLC). In this case, one physical page PPG may store one logical page (LPG) data. One logical page (LPG) data may include data bits corresponding to the number of memory cells included in one physical page PPG. In addition, one memory cell may store two or more bits of data. This is commonly referred to as a multi-level cell (MLC). In this case, one physical page PPG may store two or more logical page (LPG) data.

Conventionally, a memory cell in which two or more bits of data are stored in one memory cell is referred to as a multi-level cell (MLC). However, recently, as the number of bits of data stored in one memory cell increases, the multi-level cell (MLC) refers to a memory cell in which two bits of data is stored, a memory cell in which three or more bits of data are stored is referred to as a triple level cell (TLC), and a memory cell in which four or more bits of data are stored is referred to as a quadruple level cell (QLC). In addition, a memory cell for storing a plurality of bits of data has been developed, and the present embodiment may be applicable to a memory cell for storing two or more bits of data.

In another embodiment of the present disclosure, the memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. Such plurality of memory cells may be arranged along a +X direction, a +Y direction, and a +Z direction.

FIG. 4is a diagram illustrating a process of outputting the soft read command in accordance with some embodiments of the present disclosure.

Referring toFIG. 4, the memory controller200ofFIG. 4may include the error corrector210and the command generator220.

The error corrector210may receive read data READ_DATA read from the memory device100. The read data READ_DATA may be acquired from an operation performed by the memory device100according to a read command (not shown).

An error may be included in the read data READ_DATA during a read process or due to deterioration by retention. Therefore, in order to correct the error included in the read data READ_DATA, the error corrector210may perform an error correction operation on the read data READ_DATA. For example, the error corrector210may correct an error of the read data READ_DATA by using a code such as a Bose-Chaudhuri-Hocquenghem code (BCH code) or a low-density parity-check code (LDPC).

However, when the error correction on the read data READ_DATA has failed despite the error correction operation, the error corrector210may output error information ERR_INF. The error information ERR_INF may indicate that the error correction has failed. The memory controller200may perform to correct the error of the read data READ_DATA based on the error information ERR_INF, as follows.

For example, the command generator220may receive the error information ERR_INF from the error corrector210, and then generate the soft read command SOFTRD_CMD to output the soft read command SOFTRD_CMD to the memory device100. The operation corresponding to the soft read command SOFTRD_CMD may indicate an operation for a second error correction when the error corrector210fails to correct the error of the read data READ_DATA during a first error correction.

Specifically, the memory device100may receive the soft read command SOFTRD_CMD from the command generator220to perform the read operation a plurality of times. At this time, voltages used to read the data for the second error correction may be higher or lower than the voltages used to read the data for the first error correction.

For example, when the memory device100performs the read operations twice according to the soft read command SOFTRD_CMD, the memory device100may perform the read operations with a voltage higher than the previously used read voltage (for example, the voltage used to read data for the first error correction), by qV and a voltage lower than the previously used read voltage by qV.

In addition, when the memory device100performs the read operations four times according to the soft read command SOFTRD_CMD, the memory device100may perform the read operations with a voltage higher than the previously used read voltage by 2*qV and a voltage lower than the previously used read voltage by 2*qV in addition to the voltages used when performing the read operations twice.

In addition, when the memory device100performs the read operations six times according to the soft read command SOFTRD_CMD, the memory device100may perform the read operations with a voltage higher than the previously used read voltage by 3*qV and a voltage lower than the previously used read voltage by 3*qV in addition to the voltages used when performing the read operations four times.

Hereinafter, a method of operating and outputting the read data after the memory device100performs the read operations twice, four times, or six times according to the soft read command SOFTRD_CMD will be described.

FIGS. 5A, 5B, and 5Care diagrams illustrating the operation of the memory device corresponding to the soft read command in accordance with some embodiments of the present disclosure.

FIG. 5Ashows read voltages used in the read operation corresponding to a threshold voltage distribution of the memory cells and the soft read command.FIG. 5Bshows read data and likelihood ratio LR generated based on the read data.FIG. 5Cshows a soft bit that is a result of the logical operation of the read data performed by the memory device100ofFIG. 4. The greater the absolute value of the likelihood ratio LR, the higher the reliability of the read data.

Referring toFIG. 5A,FIG. 5Ashows an adjacent threshold voltage distribution among threshold voltage distributions of the memory cells. A horizontal axis ofFIG. 5Arepresents a magnitude Vth of the threshold voltage of the memory cells, and a vertical axis ofFIG. 5Arepresents the number of memory cells.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the program operation in the same way as a multi-level cell (MLC),FIG. 5Amay show the threshold voltage distribution of the memory cells of an erase state E and a first program state P1, the first program state P1and a second program state P2, or the second program state P2and a third program state P3among the erase state E and the first to third program states P1to P3.

FIG. 5Amay also be applicable to a case where the memory device100ofFIG. 4performs the program operation in the same way as a single level cell (SLC), triple level cell (TLC), or quadruple level cell (QLC).

In the present drawings, it is assumed thatFIG. 5Ashows the threshold voltage distribution of the memory cells of the first program state P1and the second program state P2.

Referring toFIGS. 5A and 5B, the memory device100ofFIG. 4may perform the read operation with an RH voltage according to the read command received from the memory controller200ofFIG. 4. Data read by the RH voltage may be hard data HARD_DATA. When the memory device100ofFIG. 4performs the read operation with the RH voltage, since the memory cells of A1and A2regions are turned on, the hard data HARD_DATA may be “1”, and since the memory cells of A3and A4regions are turned off, the hard data HARD_DATA may be “0”.

When the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A3region among the memory cells of the first program state P1may be turned off (0) due to a change of the threshold voltage. That is, although the memory cell is the first program state P1, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “0”. In addition, when the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A2region among the memory cells of the second program state P2may be turned on (1) due to the change of the threshold voltage. That is, although the memory cell is the second program state P2, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “1”.

Therefore, the error corrector210of the memory controller200ofFIG. 4may receive data obtained using the RH voltage and perform the first error correction operation on the read data. However, when the first error correction of the data obtained using the RH voltage is failed and the memory device ofFIG. 4receives the soft read command from the memory controller200ofFIG. 4, the memory device ofFIG. 4may perform the read operation with RS1and RS2voltages for the second error correction.

In another embodiment of the present disclosure, the memory device100ofFIG. 4may perform the read operations for the second error correction using the RS1and RS2voltages and voltages other than the RS1and RS2voltages. In the present drawings, it is assumed that the memory device100ofFIG. 4performs the read operations with the RS1and RS2voltages, that is, two voltages.

Referring toFIG. 5B, the memory device100ofFIG. 4may perform the read operation with the RS1voltage to obtain first soft data SOFT_DATA1and may perform the read operation with the RS2voltage to obtain second soft data SOFT_DATA2.

Specifically, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A1region are turned on, the first soft data SOFT_DATA1obtained from the memory cells of the A1region may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A2to A4regions are turned off, the first soft data SOFT_DATA1obtained from the memory cells of the A2to A4regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A1to A3regions are turned on, the second soft data SOFT_DATA2obtained from the memory cells of the A1to A3regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A4region are turned off, the second soft data SOFT_DATA2obtained from the memory cells of the A4region may be “0”.

According to the conventional art, after the memory device100ofFIG. 4performs the read operation according to the soft read command, all read data are output to the memory controller200ofFIG. 4, and the memory controller200ofFIG. 4generates a likelihood ratio LR based on the read data received to perform the error correction operation. That is, inFIG. 5B, the memory controller200ofFIG. 4generates the likelihood ratio LR based on the first soft data SOFT_DATA1and the second soft data SOFT_DATA2corresponding to the previously read hard data HARD_DATA and the soft read command (−1, 0, 0, +1), and then performs the error correction operation based on the likelihood ratio LR.

However, in accordance with some embodiments of the present disclosure, the memory device100ofFIG. 4may not provide both of the first and second soft data SOFT_DATA1and SOFT_DATA2to the memory controller200, but a soft bit obtained by logically operating the first and second soft data SOFT_DATA1and SOFT_DATA2to the memory controller200.

Referring toFIG. 5C, the memory device100ofFIG. 4may perform an exclusive-NOR (XNOR) operation on the first and second soft data SOFT_DATA1and SOFT_DATA2. The XNOR operation may be a match check operation. A result of the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be a third soft bit SOFT_BIT3.

Instead of outputting the first and second soft data SOFT_DATA1and SOFT_DATA2to the memory controller200ofFIG. 4, the memory device100ofFIG. 4may provide only the third soft bit SOFT_BIT3to the memory controller200ofFIG. 4. Therefore, the number of data provided from the memory device100ofFIG. 4to the memory controller200ofFIG. 4may be reduced. Accordingly, error correction operation efficiency of the memory controller200ofFIG. 4may increase.

FIGS. 6A and 6Bare diagrams illustrating a method of generating the soft bit in accordance with some embodiments of the present disclosure.

Referring toFIGS. 6A and 6B,FIG. 6Ashows a part of a configuration of a page buffer included in the page buffer group123ofFIG. 2of the memory device100ofFIG. 2, andFIG. 6Bshows the soft bit generated based on the soft read command.

FIG. 6Ashows a first page buffer PB1among a plurality of page buffers included in the page buffer group123ofFIG. 2. The first page buffer PB1may include first to eighth transistors TR1to TR8and a first latch123_1. The page buffers other than the first page buffer PB1may be configured identically to the first page buffer PB1.FIG. 6Bshows data on an SO node and a Q1_N node when performing a read operation on the memory cells in the A1to A4regions ofFIG. 5A.

In an embodiment of the present disclosure, when a first control signal TRAN1of a high state is applied to a gate of the first transistor TR1, the first transistor TR1may be turned on. In addition, when a second control signal TRAN2of a high state is applied to a gate of the second transistor TR2, the second transistor TR2may be turned on.

In an embodiment of the present disclosure, the third transistor TR3connected in series with the second transistor TR2may be connected to the first latch123_L1and the sixth transistor TR6through the Q1_N node, and the third transistor TR3may be turned on or off based on a signal applied to the Q1_N node. The fourth transistor TR4connected in series with the first transistor TR1may be connected to the first latch123_L1and the fifth transistor TR5through the Q1node, and the fourth transistor TR4may be turned on or off based on a signal applied to a Q1node.

In an embodiment of the present disclosure, the fifth transistor TR5may be connected to the sixth and seventh transistors TR6and TR7through a COM node, and when a reset signal RESET1is applied to a gate of the fifth transistor TR5, the fifth transistor TR5may be turned on. The sixth transistor TR6may be connected to the fifth and seventh transistors TR5and TR7through the COM node, and when a set signal SET1of a high state is applied to a gate of the sixth transistor TR6, the sixth transistor TR6may be turned on.

In an embodiment of the present disclosure, the seventh transistor TR7may be connected to the fifth and sixth transistors TR5and TR6through the COM node, and may be connected to the first, second, and eighth transistors TR1, TR2, and TR8through the SO node. The seventh transistor TR7may be turned on or turned off based on a signal applied to the SO node.

In an embodiment of the present disclosure, the eighth transistor TR8may be connected to the first, second, and seventh transistors TR1, TR2, and TR7through the SO node. When a sensing node pre-charge signal PRECHSO_N of a low state is applied to a gate of the eighth transistor TR8, the eighth transistor TR8may be turned on.

In an embodiment of the present disclosure, before the read data read from the memory cell array is stored into the first latch123_L1, the Q1_N node may be set to “1”, which indicates a default value. Thereafter, when the sensing node pre-charge signal PRECHSO_N is applied to the gate of the eighth transistor TR8, a sensing operation may be started.

Referring toFIG. 5, the memory device100ofFIG. 4may perform the read operation with the RS1voltage according to the soft read command to obtain the first soft data SOFT_DATA1. The first soft data SOFT_DATA1may be stored into the first latch123_L1through the SO node.

Referring toFIGS. 6A and 6B, when the first soft data SOFT_DATA1is “1”, the inverted “O” may be set in the SO node. That is, when the memory cells of the A1region are obtained using the RS1voltage, “O” may be set in the SO node. When “O” is set in the SO node, since the seventh transistor TR7maintains a turn-off state, the data of the Q1_N node may be maintained as “1”.

On the contrary, when the first soft data SOFT_DATA1is “0”, the inverted “1” may be set in the SO node. That is, when the memory cells of the A2to A4regions are obtained using the RS1voltage, “1” may be set in the SO node. When “1” is set in the SO node, the seventh transistor TR7may be turned on. At this time, since the set signal SET1signal of the high state is applied to the sixth transistor TR6to connect the Q1_N node and the ground, the data of the Q1_N node may be changed from “1” to “0”.

As a result, when the first soft data SOFT_DATA1is “1”, the SO node may be set to the inverted “0”, and the data of the Q1_N node may be maintained as “1”. In addition, when the first soft data SOFT_DATA1is “0”, the SO node may be set to the inverted “1”, and the data of the Q1_N node may be changed to “O”.

Referring toFIG. 5, after performing the read operation with the RS1voltage, the memory device100ofFIG. 4may perform the read operation with the RS2voltage to obtain the second soft data SOFT_DATA2. The second soft data SOFT_DATA2may be stored into the first latch123_L1through the SO node.

Referring toFIGS. 6A and 6B, when the second soft data SOFT_DATA2is “1”, the SO node may be set to the inverted “0”. That is, when the memory cells of the A1to A3regions are obtained using the RS2voltage, the SO node may be set to “0”. When the SO node is set to “0”, since the seventh transistor TR7maintains a turn-off state, the data of the Q1_N node may be maintained without change.

On the contrary, when the second soft data SOFT_DATA2is “0”, the SO node may be set to the inverted “1”. That is, when the memory cells of the A4region are obtained using the RS2voltage, the SO node may be set to “1”. When the SO node is set to “1”, the seventh transistor TR7may be turned on. At this time, since the reset signal RESET1of the high state is applied to the fifth transistor TR5to connect the Q1_N node and ground, the data of the Q1_N node may be changed from “0” to “1” or maintain “1”.

As a result, when the second soft data SOFT_DATA2is “1”, the SO node may be set to the inverted “0”, and the data of the Q1_N node may be maintained. In addition, when the second soft data SOFT_DATA2is “0”, the SO node may be set to the inverted “1”, and the data of the Q1_N node may be changed from “0” to “1” or maintain “1”.

FIG. 7is a diagram illustrating the method of generating the soft bit in accordance with some embodiments of the present disclosure.

Referring toFIG. 7,FIG. 7shows a first page buffer PB1among the page buffers included in the page buffer group123ofFIG. 2. The first page buffer PB1ofFIG. 7may include a first latch123_L1, a second latch123_L2, and a first read data operating component123_C1. In another embodiment of the present disclosure, the first page buffer PB1may include more latches. In addition, the descriptions below may be applied to other page buffers included in the page buffer group123ofFIG. 2.

In an embodiment of the present disclosure, the memory device100ofFIG. 4may perform the read operation corresponding to the soft read command received from the memory controller200ofFIG. 4to receive the soft data through the first bit line BL1.

Referring toFIG. 5A, the first soft data SOFT_DATA1obtained from the read operation performed by the memory device100ofFIG. 4with the RS1voltage, may be stored into the first latch123_L1, and the second soft data SOFT_DATA2obtained from the read operation performed by the memory device100ofFIG. 4with the RS2voltage, may be stored into the second latch123_L2. That is, the memory device100ofFIG. 4may perform the read operations with the RS1voltage and the RS2voltage in correspondence with the soft read command to store the read data obtained from the read operations into the respective latches.

The first and second soft data SOFT_DATA1and SOFT_DATA2stored in the first and second latches123_L1and123_L2, respectively, may be outputted to the first read data operating component123_C1. The first read data operating component123_C1may receive the first and second soft data SOFT_DATA1and SOFT_DATA2to perform an XNOR operation thereon. The XNOR operation may be a match check operation. The first read data operating component123_C1may perform the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2to generate a third soft bit SOFT_BIT3(i.e., a result of XNOR operation on the first and second soft data), and may output the third soft bit SOFT_BIT3to the column decoder124ofFIG. 2through the first data line DL1.

Referring toFIG. 7, the memory device100ofFIG. 4may provide only the third soft bit SOFT_BIT3to the memory controller200ofFIG. 4instead of outputting both of the first and second soft data SOFT_DATA1and SOFT_DATA2, to the memory controller200ofFIG. 4. Therefore, the number of data provided from the memory device100ofFIG. 4to the memory controller200of theFIG. 4may be reduced. Further, since the memory device100ofFIG. 4performs the logical operation for the second error correction, the efficiency of the error correction operation of the memory controller200ofFIG. 4may be increased.

FIGS. 8A and 8Bare diagrams illustrating the operation of the memory device corresponding to the soft read command in accordance with some embodiments of the present disclosure.

Referring toFIGS. 8A and 8B,FIG. 8Ashows read voltages used in the read operation corresponding to the threshold voltage distribution of the memory cells and the soft read command, andFIG. 8Bshows read data and likelihood ratio LR generated based on the read data. The greater the absolute value of the likelihood ratio LR, the higher the reliability of the read data.

Referring toFIGS. 5A and 8A,FIG. 8Ashows a case where a read operation is additionally performed with an RS3voltage and an RS4voltage as well as the read voltages of FIG.5A.

In an embodiment of the present disclosure, as the number of bits stored in one memory cell increases, it is highly possible that an error is included in the read data. That is, as the threshold voltage distribution of the memory cells is segmented, adjacent threshold voltage distributions may be overlap due to temperature and retention. Therefore, in order to correct the error of the read data, a greater number of read operations may be performed according to the soft read command.

FIG. 8Ais assumed to illustrate the threshold voltage distribution of the memory cells of the first program state P1and the second program state P2similarly toFIG. 5A. That is,FIG. 8Ashows an adjacent threshold voltage distribution among threshold voltage distributions of the memory cells. A horizontal axis ofFIG. 8Arepresents a magnitude Vth of the threshold voltage of the memory cells, and a vertical axis ofFIG. 8Arepresents the number of memory cells.

Hereinafter, description repetitive to that ofFIG. 5Awill be omitted for clarity.

Referring toFIGS. 8A and 8B, the memory device100ofFIG. 4may perform the read operation with the RH voltage according to the read command received from the memory controller200ofFIG. 4. Data by the RH voltage may be the hard data HARD_DATA. When the memory device100ofFIG. 4performs the read operation with the RH voltage, since the memory cells of A1to A3regions are turned on, the hard data HARD_DATA may be “1”, and since the memory cells of A4to A6regions are turned off, the hard data HARD_DATA may be “0”.

When the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A4region among the memory cells of the first program state P1may be turned off (0) due to a change of the threshold voltage. That is, although the memory cell is the first program state P1, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “0”. In addition, when the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A3region among the memory cells of the second program state P2may be turned on (1) due to the change of the threshold voltage. That is, although the memory cell is the second program state P2, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “1”.

Therefore, the error corrector210ofFIG. 4included in the memory controller200ofFIG. 4may receive the data obtained using the RH voltage and perform the first error correction operation on the read data. However, if the first error correction of data obtained using the RH voltage is failed, the memory device ofFIG. 4may receive the soft read command from the memory controller200ofFIG. 4. In the present drawings, it is assumed that the memory device100ofFIG. 4performs the read operations with the RS1to RS4voltages according to the soft read command for the second error correction.

Referring toFIG. 8B, the memory device100ofFIG. 4may perform the read operation with the RS1voltage to obtain the first soft data SOFT_DATA1, may perform the read operation with the RS2voltage to obtain the second soft data SOFT_DATA2, may perform the read operation with the RS3voltage to obtain third soft data SOFT_DATA3, and may perform the read operation with the RS4voltage to obtain fourth soft data SOFT_DATA4.

Specifically, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A1and A2regions are turned on, the first soft data SOFT_DATA1obtained from the memory cells of the A1and A2regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A3to A6regions are turned off, the first soft data SOFT_DATA1obtained from the memory cells of the A3to A6regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A1to A4regions are turned on, the second soft data SOFT_DATA2obtained from the memory cells of the A1to A4regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A5and A6regions are turned off, the second soft data SOFT_DATA2obtained from the memory cells of the A5and A6regions may be “O”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS3voltage, since the memory cells of the A1region are turned on, the third soft data SOFT_DATA3obtained from the memory cells of the A1region may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS3voltage, since the memory cells of the A2and A6regions are turned off, the third soft data SOFT_DATA3obtained from the memory cells of the A2and A6regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS4voltage, since the memory cells of the A1to A5region are turned on, the fourth soft data SOFT_DATA4obtained from the memory cells of the A1to A5region may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS4voltage, since the memory cells of the A6region are turned off, the fourth soft data SOFT_DATA4obtained from the memory cells of the A6region may be “0”.

As a result, when the first error correction of the read data is failed after the read operation is performed with the RH voltage, the memory device100ofFIG. 4may perform the read operation with the RS1to RS4voltages for the second error correction, and the memory controller200ofFIG. 4may generate likelihood ratio LR based on the read data obtained using the RS1to RS4voltages (−2, −1, 0, 0, +1, +2). Thereafter, the memory controller200ofFIG. 4may perform the second error correction of the read data based on the likelihood ratio LR again.

However, in the present disclosure, the memory device100ofFIG. 4may not provide all of the first to fourth soft data SOFT_DATA1to SOFT_DATA4to the memory controller200ofFIG. 4. Instead, the memory device100ofFIG. 4may provide the soft bit obtained by performing the XNOR operation on the first to fourth soft data SOFT_DATA1to SOFT_DATA4to the memory controller200ofFIG. 4. When the memory device100ofFIG. 4performs the XNOR operation on the first to fourth soft data SOFT_DATA1to SOFT_DATA4, the memory device100ofFIG. 4may provide only two soft bits to the memory controller200ofFIG. 4.

Hereinafter, the two soft bits provided by the memory device100ofFIG. 4will be described.

FIGS. 9A and 9Bare diagrams illustrating the soft bit generated according to the operation of the memory device of FIG.8in accordance with some embodiments of the present disclosure.

Referring toFIGS. 8A, 8B, 9A, and 9B,FIG. 9Ashows a table in which a table ofFIG. 8Bis sequentially arranged from read data obtained using the lowest read voltage, andFIG. 9Bshows the soft bits generated based on the first and second soft data SOFT_DATA1and SOFT_DATA2. SinceFIG. 9Ais substantially the same table asFIG. 8B, the description ofFIG. 9Awill be omitted for clarity.

Referring toFIG. 9B,FIG. 9Bshows a fifty-first soft bit SOFT_BIT51which indicates data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2. The XNOR operation may be a match check operation.

In an embodiment of the present disclosure, the first soft data SOFT_DATA1may be obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1and A2regions with the RS1voltage, and the second soft data SOFT_DATA2may be obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1and A2regions with the RS2voltage. Both of the first soft data SOFR_DATA1and the second soft data SOFT_DATA2may be “1”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “1”.

In an embodiment of the present disclosure, the first soft data SOFT_DATA1that the memory device100ofFIG. 4may obtain by reading from the memory cells of the A3and A4regions with the RS1voltage may be “0”, and the second soft data SOFT_DATA2that the memory device100ofFIG. 4may obtain by reading from the memory cells of the A3and A4regions with the RS2voltage may be “1”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “0”.

In an embodiment of the present disclosure, both of the first soft data SOFT_DATA1that the memory device100ofFIG. 4may obtain by reading from the memory cells of the A5and A6regions with the RS1voltage, and the second soft data SOFT_DATA2that the memory device100ofFIG. 4may obtain by reading from the memory cells of the A5and A6regions with the RS2voltage, may be “0”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “1”.

FIGS. 10A and 10Bare diagrams illustrating another soft bit generated by the operation of the memory device ofFIGS. 8A and 8Bin accordance with some embodiments of the present disclosure.

Referring toFIGS. 10A and 10B,FIG. 10Ashows the same table as the table ofFIG. 9A, andFIG. 10Bshows the fifty-first soft bit SOFT_BIT51generated based on the first and second soft data SOFT_DATA1and SOFT_DATA2, and fifty-second soft bit SOFT_BIT52generated based on the third and fourth soft data SOFT_DATA3and SOFT_DATA4.

Since the fifty-first soft bit SOFT_BIT51ofFIGS. 10A and 10Bare the same as the fifty-first soft bit SOFT_BIT51ofFIGS. 9A and 9B, respectively, description repetitive to the description ofFIG. 9will be omitted for clarity.

Referring toFIG. 10B, second column shows the fifty-second soft bit SOFT_BIT52which indicates data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4. The XNOR operation may be a match check operation.

In an embodiment of the present disclosure, both of the third soft data SOFT_DATA3obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1region with the RS3voltage, and the fourth soft data SOFT_DATA4obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1region with the RS4voltage, may be “1”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “1”.

In an embodiment of the present disclosure, the third soft data SOFT_DATA3obtained by the memory device100ofFIG. 4by reading from the memory cells of the A2to A5regions with the RS3voltage may be “0”, and the fourth soft data SOFT_DATA4obtained by the memory device100ofFIG. 4by reading from the memory cells of the A2to A5regions with the RS4voltage may be “1”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “0”.

In an embodiment of the present disclosure, both of the third soft data SOFT_DATA3obtained by the memory device100ofFIG. 4by reading from the memory cells of the A6region with the RS3voltage, and the fourth soft data SOFT_DATA4obtained by the memory device100ofFIG. 4by reading from the memory cells of the A6region with the RS4voltage, may be “0”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “1”.

When the memory device100ofFIG. 4generates the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52by performing the XNOR operation based on the first to fourth soft data SOFT_DATA1to SOFT_DATA4, the memory device100ofFIG. 4may output the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52to the memory controller200ofFIG. 4. Therefore, the memory device100ofFIG. 4may provide only the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52to the memory controller200ofFIG. 4instead of providing all of the first to fourth soft data SOFT_DATA1to SOFT_DATA4to the memory controller200ofFIG. 4.

As a result, the number of data provided from the memory device100ofFIG. 4to the memory controller200ofFIG. 4may be reduced. Further, the memory device100ofFIG. 4performs the logical operation for the second error correction Instead of the memory controller200ofFIG. 4. Thus, the error correction efficiency of the memory controller200ofFIG. 4may be increased.

Although not shown in the present drawings, the memory device100ofFIG. 4may perform the XNOR on the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52. That is, the memory device100ofFIG. 4may provide only data obtained by performing the XNOR operation on the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52to the memory controller200ofFIG. 4instead of providing the fifty-first and fifty-second soft bits SOFT_BIT51and SOFT_BIT52generated based on the first to fourth soft data SOFT_DATA1to SOFT_DATA4to the memory controller200ofFIG. 4. Therefore, since the memory device100ofFIG. 4outputs a smaller number of data to the memory controller200ofFIG. 4, the error correction efficiency of the memory controller200ofFIG. 4may be increased.

In addition, although not shown in the present drawings, the read operation may be performed with RS1to RS8voltages, that is, eight voltages, according to the soft read command for the second error correction. In this case, the memory device100ofFIG. 4may obtain first to eighth soft data SOFT_DATA1to SOFT_DATA8by performing the read operation with the RS1to RS8voltages. When the first to eighth soft data SOFT_DATA1to SOFT_DATA8are obtained, the memory device100ofFIG. 4may not provide all of the first to eighth soft data SOFT_DATA1to SOFT_DATA8to the memory controller200ofFIG. 4but four soft bits obtained by performing XNOR operation on the first to eighth soft data SOFT_DATA1to SOFT_DATA8to the memory controller200ofFIG. 4.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS1to RS8voltages, the memory device100ofFIG. 4may provide fifty-first soft bit SOFT_BIT51, which is data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2, fifty-second soft bit SOFT_BIT52, which is data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4, fifty-third soft bit SOFT_BIT53, which is data obtained by performing the XNOR operation on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6, and fifty-fourth soft bit SOFT_BIT54, which is data obtained by performing the XNOR operation on the seventh and eighth soft data SOFT_DATA7and SOFT_DATA8, to the memory controller200ofFIG. 4.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS1to RS8voltages, the memory device100ofFIG. 4may provide data obtained by performing the XNOR operation on the fifty-first soft bit SOFT_BIT51and the fifty-fourth soft bit SOFT_BIT54, and data obtained by performing the XNOR operation on the fifty-second soft bit SOFT_BIT52and the fifty-third soft bit SOFT_BIT53, to the memory controller200ofFIG. 4. That is, instead of providing the fifty-first to fifty-fourth soft bits SOFT_BIT51to SOFT_BIT54to the memory controller200ofFIG. 4, the only two data obtained by performing the XNOR operation on the fifty-first to fifty-fourth soft bits SOFT_BIT51to SOFT_BIT54may be provided to the memory controller200ofFIG. 4. Furthermore, the memory device100ofFIG. 4may also output only one data obtained by performing the XNOR operation on the two data obtained by performing the XNOR operation on the fifty-first to fifty-fourth soft bits SOFT_BIT51to SOFT_BIT54, to the memory controller200ofFIG. 4.

FIGS. 11A and 11Bare diagrams illustrating the operation of the memory device corresponding to the soft read command in accordance with some embodiments of the present disclosure.

Referring toFIGS. 11A and 11B,FIG. 11Ashows read voltages used in the read operation corresponding to the threshold voltage distribution of the memory cells and the soft read command, andFIG. 11Bshows read data and likelihood ratio LR generated based on the read data. The greater the absolute value of the likelihood ratio LR, the higher the reliability of the read data.

Referring toFIGS. 8A and 11A,FIG. 11Ashows a case where a read operation is additionally performed with an RS5voltage and an RS6voltage in addition to the read voltages ofFIG. 8A.

FIG. 11Ais assumed to illustrate the threshold voltage distribution of the memory cells of the first program state P1and the second program state P2similarly toFIG. 8A. A horizontal axis ofFIG. 11Arepresents a magnitude Vth of the threshold voltage of the memory cells, and a vertical axis ofFIG. 11Arepresents the number of memory cells.

Hereinafter, description repetitive to that ofFIG. 8Awill be omitted for clarity.

Referring toFIGS. 11A and 11B, the memory device100ofFIG. 4may perform the read operation with the RH voltage according to the read command received from the memory controller200ofFIG. 4. The read data obtained using the RH voltage may be the hard data HARD_DATA. When the memory device100ofFIG. 4performs the read operation with the RH voltage, since the memory cells of A1to A4regions are turned on, the hard data HARD_DATA may be “1”, and since the memory cells of A5to A8regions are turned off, the hard data HARD_DATA may be “0”.

When the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A5region among the memory cells of the first program state P1may be turned off (0) due to a change of the threshold voltage. That is, although the memory cell is the first program state P1, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “0”. In addition, when the memory device100ofFIG. 4performs the read operation with the RH voltage, the memory cells of the A4region among the memory cells of the second program state P2may be turned on (1) due to the change of the threshold voltage. That is, although the memory cell is the second program state P2, when the read operation is performed with the RH voltage, the hard data HARD_DATA may be read as “1”.

Therefore, the error corrector210ofFIG. 4included in the memory controller200ofFIG. 4may receive the read data obtained using the RH voltage and perform the first error correction operation. However, when the error correction of the read data obtained using the RH voltage is failed, the memory device ofFIG. 4may receive the soft read command from the memory controller200ofFIG. 4. In the present drawings, it is assumed that the memory device100ofFIG. 4performs the read operation with the RS1to RS4voltages according to the soft read command for the second error correction.

Referring toFIG. 11B, the memory device100ofFIG. 4may perform the read operation with the RS1voltage to obtain the first soft data SOFT_DATA1, may perform the read operation with the RS2voltage to obtain the second soft data SOFT_DATA2, may perform the read operation with the RS3voltage to obtain third soft data SOFT_DATA3, may perform the read operation with the RS4voltage to obtain fourth soft data SOFT_DATA4, may perform the read operation with the RS5voltage to obtain fifth soft data SOFT_DATA5, and may perform the read operation with the RS6voltage to obtain sixth soft data SOFT_DATA6.

Specifically, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A1to A3regions are turned on, the first soft data SOFT_DATA1obtained by reading from the memory cells of the A1to A3regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS1voltage, since the memory cells of the A4to A8regions are turned off, the first soft data SOFT_DATA1obtained by reading from the memory cells of the A4to A8regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A1to A5regions are turned on, the second soft data SOFT_DATA2obtained by reading from the memory cells of the A1to A5regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS2voltage, since the memory cells of the A6to A8regions are turned off, the second soft data SOFT_DATA2obtained by reading from the memory cells of the A6to A8regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS3voltage, since the memory cells of the A1and A2regions are turned on, the third soft data SOFT_DATA3obtained by reading from the memory cells of the A1and A2regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS3voltage, since the memory cells of the A3to A8regions are turned off, the third soft data SOFT_DATA3obtained by reading from the memory cells of the A3to A8regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS4voltage, since the memory cells of the A1to A6regions are turned on, the fourth soft data SOFT_DATA4obtained by reading from the memory cells of the A1to A6regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS4voltage, since the memory cells of the A7and A8regions are turned off, the fourth soft data SOFT_DATA4obtained by reading from the memory cells of the A7and A8regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS5voltage, since the memory cells of the A1region are turned on, the fifth soft data SOFT_DATA5obtained by reading from the memory cells of the A1region may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS5voltage, since the memory cells of the A2to A8regions are turned off, the fifth soft data SOFT_DATA5obtained by reading from the memory cells of the A2to A8regions may be “0”.

In an embodiment of the present disclosure, when the memory device100ofFIG. 4performs the read operation with the RS6voltage, since the memory cells of the A1to A7regions are turned on, the sixth soft data SOFT_DATA6obtained by reading from the memory cells of the A1to A7regions may be “1”. In addition, when the memory device100ofFIG. 4performs the read operation with the RS6voltage, since the memory cells of the A8region are turned off, the sixth soft data SOFT_DATA6obtained by reading from the memory cells of the A8region may be “0”.

As a result, if the first error correction of the read data is failed after the read operation is performed with the RH voltage, the memory device100ofFIG. 4may perform the read operation with the RS1to RS6voltages. Then, the memory controller200ofFIG. 4may generate likelihood ratio LR based on the data obtained using the RS1to RS6voltages (−3, −2, −1, 0, 0, +1, +2). Thereafter, the memory controller200ofFIG. 4may perform the second error correction of the read data based on the likelihood ratio LR again.

However, in accordance with some embodiments of the present disclosure, the memory device100ofFIG. 4may not provide all of the first to sixth soft data SOFT_DATA1to SOFT_DATA6to the memory controller200ofFIG. 4, and may provide the soft bit obtained by performing the XNOR operation on the first to sixth soft data SOFT_DATA1to SOFT_DATA6to the memory controller200ofFIG. 4. When the memory device100ofFIG. 4performs the XNOR operation on the first to sixth soft data SOFT_DATA1to SOFT_DATA6, the memory device100ofFIG. 4may provide only two or three soft bits to the memory controller200ofFIG. 4.

Hereinafter, the two or three soft bits output by the memory device100ofFIG. 4will be described.

FIGS. 12A and 12Bare diagrams illustrating the soft bit generated according to the operation of the memory device ofFIG. 11in accordance with some embodiments of the present disclosure.

Referring toFIGS. 11A, 11B, 12A, and 12B,FIG. 12Ashows a table in which a table ofFIG. 11Bis sequentially arranged from read data obtained using the lowest read voltage, andFIG. 12Bshows the soft bits generated based on the first and second soft data SOFT_DATA1and SOFT_DATA2. SinceFIG. 12Ais substantially the same table asFIG. 11B, the description ofFIG. 12Awill be omitted for clarity.

Referring toFIG. 12B,FIG. 12Bshows a seventy-first soft bit SOFT_BIT71obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2. The XNOR operation may be a match check operation.

In an embodiment of the present disclosure, both of the first soft data SOFT_DATA1obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1to A3regions with the RS1voltage, and the second soft data SOFT_DATA2obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1to A3regions with the RS2voltage, may be “1”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “1”.

In an embodiment of the present disclosure, the first soft data SOFT_DATA1, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A4and A5regions with the RS1voltage may be “0”, and the second soft data SOFT_DATA2, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A4and A5regions with the RS2voltage may be “1”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “0”.

In an embodiment of the present disclosure, both of the first soft data SOFT_DATA1obtained by the memory device100ofFIG. 4by reading from the memory cells of the A6to A8regions with the RS1voltage, and the second soft data SOFT_DATA2obtained by the memory device100ofFIG. 4by reading from the memory cells of the A6to A8regions with the RS2voltage, may be “0”. Therefore, the data obtained by performing the XNOR operation on the first and second soft data SOFT_DATA1and SOFT_DATA2may be “1”.

FIGS. 13A and 13Bare diagrams illustrating another soft bit generated by the operation of the memory device ofFIGS. 11A and 11Bin accordance with some embodiments of the present disclosure.

Referring toFIGS. 11A to 13B,FIG. 13Ashows the same table as the table ofFIG. 12A, andFIG. 13Bshows the soft bit generated based on the third and fourth soft data SOFT_DATA3and SOFT_DATA4. SinceFIG. 13Ais the same table asFIG. 12A, description ofFIG. 13Awill be omitted.

Referring toFIG. 13B,FIG. 13Bshows seventy-second soft bit SOFT_BIT72obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4. The XNOR operation may be a match check operation.

In an embodiment of the present disclosure, both of the third soft data SOFT_DATA3, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1and A2regions with the RS3voltage, and the fourth soft data SOFT_DATA4, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1and A2regions with the RS4voltage, may be “1”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “1”.

In an embodiment of the present disclosure, the third soft data SOFT_DATA3, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A3to A6regions with the RS3voltage may be “0”, and the fourth soft data SOFT_DATA4, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A3to A6regions with the RS4voltage may be “1”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “0”.

In an embodiment of the present disclosure, both of the third soft data SOFT_DATA3, which is obtained by the memory device100ofFIG. 4reading from the memory cells of the A7and A8regions with the RS3voltage, and the fourth soft data SOFT_DATA4, which is obtained by the memory device100of FIG.4by reading from the memory cells of the A7and A8regions with the RS4voltage, may be “0”. Therefore, the data obtained by performing the XNOR operation on the third and fourth soft data SOFT_DATA3and SOFT_DATA4may be “1”.

FIGS. 14A and 14Bare diagrams illustrating another soft bit generated by the operation of the memory device ofFIGS. 11A and 11Bin accordance with some embodiments of the present disclosure.

Referring toFIGS. 11A to 14B,FIG. 14Ashows the same table as the table ofFIG. 12AandFIG. 13A, andFIG. 14Bshows the soft bit generated based on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6. SinceFIG. 14Ais the same table asFIG. 12AandFIG. 13A, description ofFIG. 14Awill be omitted for clarity.

Referring toFIG. 14B,FIG. 14Bshows seventy-third soft bit SOFT_BIT73obtained by performing the XNOR operation on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6.

In an embodiment of the present disclosure, both of the fifth soft data SOFT_DATA5, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1region with the RS5voltage, and the sixth soft data SOFT_DATA6, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A1region with the RS6voltage, may be “1”. Therefore, the data obtained by performing the XNOR operation on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6may be “1”.

In an embodiment of the present disclosure, the fifth soft data SOFT_DATA5, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A2to A7regions with the RS5voltage may be “0”, and the sixth soft data SOFT_DATA6, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the sixth soft data SOFT_DATA6regions with the RS6voltage may be “1”. Therefore, the data obtained by performing the XNOR operation on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6may be “0”.

In an embodiment of the present disclosure, both of the fifth soft data SOFT_DATA5, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A8region with the RS5voltage, and the sixth soft data SOFT_DATA6, which is obtained by the memory device100ofFIG. 4by reading from the memory cells of the A8region with the RS6voltage, may be “0”. Therefore, the data obtained by performing the XNOR operation on the fifth and sixth soft data SOFT_DATA5and SOFT_DATA6may be “1”.

FIGS. 15A and 15Bare diagrams Illustrating the soft bit output according to the operation of the memory device ofFIG. 11in accordance with some embodiments of the present disclosure.

Referring toFIGS. 12A to 15B,FIG. 15Ashows the seventy-first soft bit SOFT_BIT71ofFIG. 12B, the seventy-second soft bit SOFT_BIT72ofFIG. 13B, the seventy-third soft bit SOFT_BIT73ofFIG. 14B, andFIG. 15Bshows a soft bit newly generated based on the soft bits.

Referring toFIG. 15A, the memory device100ofFIG. 4may perform the read operation with the RS1to RS6voltages according to the soft read command received from the memory controller200ofFIG. 4, perform the XNOR operation on the read first to sixth soft data SOFT_DATA1to SOFT_DATA6, and generate the seventy-first to seventy-third soft bits SOFT_BIT71to SOFT_BIT73.

As a result, the memory device100ofFIG. 4may provide only the seventy-first to seventy-third soft bits SOFT_BIT71to SOFT_BIT73to the memory controller200ofFIG. 4instead of providing all of the first to sixth soft data SOFT_DATA1to SOFT_DATA6to the memory controller200ofFIG. 4.

Therefore, the number of data provided from the memory device100ofFIG. 4to the memory controller200ofFIG. 4is reduced, and the memory device100ofFIG. 4performs the logical operation for the second error correction instead of the memory controller200ofFIG. 4. Thus, the error correction efficiency of the memory controller200ofFIG. 4may be increased.

In an embodiment of the present disclosure, the memory device100ofFIG. 4may generate the new soft bit based on the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73. When the memory device100ofFIG. 4generates the new soft bit, the number of data provided to the memory controller200ofFIG. 4may be further reduced.

Specifically, referring toFIGS. 15A and 15B, the memory device100ofFIG. 4may perform the XNOR operation on the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73to generate a seventy-fourth soft bit SOFT_BIT74.

For example, since the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73of the memory cells of the A1and A8regions are “1”, the data obtained by performing the XNOR operation on the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73may be “1”.

In an embodiment of the present disclosure, since the seventy-first soft bit SOFT_BIT71of the memory cells of the A2, A3, A6, and A7regions is “1”, and the seventy-third soft bit SOFT_BIT73of the memory cells of the A2, A3, A6, and A7regions is “0”, the data obtained by performing the XNOR operation on the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73may be “0”.

In an embodiment of the present disclosure, since the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73of the memory cells of the A4and A5regions are “0”, the data obtained by performing the XNOR operation on the seventy-first and seventy-third soft bits SOFT_BIT71and SOFT_BIT73may be “1”.

As a result, the memory device100ofFIG. 4may provide only the seventy-fourth and seventy-second soft bits SOFT_BIT74and SOFT_BIT72to the memory controller200ofFIG. 4instead of providing all of the seventy-first to seventy-third soft bits SOFT_BIT71to SOFT_BIT73to the memory controller200ofFIG. 4. Therefore, through the additional XNOR operation of the memory device100ofFIG. 4, the number of data provided to the memory controller200ofFIG. 4may be further reduced, and the error correction efficiency of the memory controller200ofFIG. 4may be further increased.

Although not shown in the present drawings, the memory device100ofFIG. 4may provide only data obtained by performing the XNOR operation on the seventy-fourth and seventy-second soft bits SOFT_BIT74and SOFT_BIT72to the memory controller200ofFIG. 4. That is, the memory device100ofFIG. 4may provide smaller number of data to the memory controller200ofFIG. 4instead of providing the seventy-fourth and seventy-second soft bits SOFT_BIT74and SOFT_BIT72to the memory controller200ofFIG. 4. In this case, through the additional XNOR operation of the memory device100ofFIG. 4, the number of data provided to the memory controller200of FIG.4may be further reduced, and the error correction efficiency of the memory controller200ofFIG. 4may be further increased.

FIG. 16is a diagram illustrating the operation of the memory device in accordance with some embodiments of the present disclosure.

Referring toFIG. 16, in step S1601, the memory device may receive the soft read command from the memory controller. The soft read command may be output from the memory controller after the first error correction operation is failed. That is, the soft read command may be the command for the second error correction when the first error correction of the read data provided from the memory device is failed. In addition, the soft read command may be the command for instructing to perform the read operation with the voltages higher and lower than the read voltage used when performing the failed read operation.

Therefore, when the memory device receives the soft read command from the memory controller, the read operation may be performed with the soft read voltage including voltages higher and lower than the read voltage used when performing the failed read operation (S1603).

In accordance with some embodiments of the present disclosure, when the memory device performs the read operation corresponding to the soft read command, the memory device may generate the soft bit based on the data obtained from the read operation (S1605). The soft bit may be data obtained by performing the XNOR operation on the read data according to the soft read command.

For example, when the soft data is read by the read operation corresponding to the soft read command, the memory device may generate the soft bit by performing the XNOR operation on the soft data. The generated soft bit may be provided to the memory controller (S1607).

Therefore, the memory device according to some embodiments of the present disclosure may provide only the soft data to the memory controller without providing all soft data obtained based on the soft read command to the memory controller, thereby reducing the number of data provided to the memory controller. As a result, since the memory device performs the logical operation for the second error correction in advance instead of the memory controller, the error correction efficiency of the memory controller may be increased.

FIG. 17is a diagram illustrating the operation of the memory device in accordance with some embodiments of the present disclosure.

In step S1701, the initial data of the Q1_N node of the page buffers included in the page buffer group of the memory device may be set. The Q1_N node is one of the nodes connected to the latch, and the initial data may be “1”. When the initial data of the Q1_N node is set, the page buffer may read the data stored in the memory cell array and receive the read data (S1703).

In an embodiment of the present disclosure, when the page buffer receives the read data, the read data may be inverted and provided to the SO node. That is, when the read data is “1”, “0” may be set in the SO node, and when the read data is “0”, “1” may be set in the SO node. The page buffer may change the initial data based on the read data (S1705).

Specifically, when the initial data is “1” and “0” is set in the SO node, the initial data may maintain “1” without change. When the initial data is “1” and “1” is set in the SO node, the initial data may be changed from “1” to “0”. Thereafter, whenever the page buffer receives data, it may be determined whether or not the data of the Q1_N node is changed, based on the data provided to the SO node.

When the initial data of the Q1_N node of the page buffer is changed, the memory device may determine whether all read data according to the soft read command are received (S1707).

When all read data corresponding to the soft read command are received (Y), the memory device may output the data of the Q1_N node that is finally changed as the soft bit (S1709). That is, the data of the Q1_N node may be the soft bit.

However, when all read data corresponding to the soft read command is not received (N), the process may proceed to step S1703again, and the page buffer may receive the read data obtained by reading the data stored in the memory cell array.

FIG. 18is a diagram illustrating the operation of the memory device in accordance with some embodiments of the present disclosure.

Referring toFIGS. 17 and 18, steps S1801to S1811show the method of generating the soft bit, which are different from those ofFIG. 17.

In step S1801, the memory device may store data obtained from the first read operation into the first latch. The first read operation may be one of the operations corresponding to the soft read command received from the memory controller. That is, the first read operation may be performed with the read voltage different from the read voltage used when performing the failed read operation.

In step S1803, the memory device may store data obtained from the second read operation into the second latch. The second read operation may be one of the operations corresponding to the soft read command received from the memory controller. In addition, the second read operation may be the read operation performed with another read voltage, but not the read voltage of the first read operation and the read voltage used when performing the failed read operation.

When the read data corresponding to the soft read command is stored into each latch through steps S1801and S1803, the memory device may determine whether all read operations corresponding to the soft read command are performed (S1805).

When all read operations corresponding to the soft read command are not performed (N), the memory device may store data obtained from the next read operation into the next latch.

However, when all read operations corresponding to the soft read command are performed (Y), the memory device may provide only the soft bit to the memory controller.

In an embodiment of the present disclosure, when all read operations corresponding to the soft read command are performed, the memory device may generate the soft bit by performing an XNOR operation on the soft data stored in each latch (S1809). The XNOR operation performed by the memory device may be performed at least once depending from the number of latches in which data is stored.

When the soft bit is generated, the memory device may provide the generated soft bit to the memory controller (S18011). Therefore, since the memory device provides only the soft bit to the memory controller, the number of data provided from the memory device to the memory controller may be reduced.

FIG. 19is a diagram illustrating the operation of the memory device in accordance with some embodiments of the present disclosure.

Referring toFIGS. 18 and 19,FIG. 19shows the operation of the memory device performed between steps S1809and S1811.

In an embodiment, the memory device may perform the XNOR operation at least once depending from the number of latches in which data is stored.

Specifically, the memory device may determine whether three or more soft bits are generated based on the soft data corresponding to the soft read command (S1901). That is, when two or less soft bits are generated, the memory device may provide the generated bits to the memory controller. However, when three or more soft bits are generated, the memory device may logically operate some of the generated soft bits.

In an embodiment of the present disclosure, when the number of soft bits generated based on the soft data corresponding to the soft read command is not equal to or greater than three (N), that is, when the number of soft bits is equal to or less than two, the process may proceed to step S1811, and the memory device may provide one or two soft bits to the memory controller.

However, when three or more soft bits are generated based on the soft data corresponding to the soft read command (Y), the memory device may generate a new soft bit by performing an XNOR operation on the generated soft bits. (S1903). That is, in order to further reduce the number of data being provided to the memory controller, the memory device may perform the XNOR operation on the generated soft bits. In addition, the memory device may provide the newly generated soft bit and the soft bit on which the XNOR operation is not performed, to the memory controller.

FIG. 20is a block diagram illustrating a memory card system including the storage device in accordance with some embodiments of the present disclosure.

Referring toFIG. 20, the memory card system2000includes a memory controller2100, a memory device2200, and a connector2300.

The memory controller2100is connected to the memory device2200. The memory controller2100is configured to access the memory device2200. For example, the memory controller2100is configured to control read, write, erase, and background operations of the memory device2200. The memory controller2100is configured to provide an interface between the memory device2200and the host Host. The memory controller2100is configured to drive firmware for controlling the memory device2200. The memory device2200may be implemented equally to the memory device100ofFIG. 2described with reference toFIG. 2.

In an embodiment of the present disclosure, when a read operation performed by the memory device2200is failed, the memory device2200may receive a soft read command from the memory controller2100to perform a read operation corresponding to the soft read command. At this time, the memory device2200may not provide all read data obtained from the read operation corresponding to the soft read command to the memory controller2100, but the read data obtained by performing an XNOR operation on the read data to the memory controller2100.

As a result, the number of data provided from the memory device2200to the memory controller2100may be reduced. In addition, since the memory controller2100performs the XNOR operation on the read data for the second error correction, error correction efficiency of the memory controller2100may increase.

As an example, the memory controller2100may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

The memory controller2100may communicate with an external device through the connector2300. The memory controller2100may communicate with an external device (for example, the host) according to a specific communication standard. As an example, the memory controller2100is configured to communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multi-media card (MMC), an embedded MMC (MCM), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe. As an example, the connector2300may be defined by at least one of the various communication standards described above.

The memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card. For example, the memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a universal flash storage (UFS).

FIG. 21is a block diagram illustrating a solid state drive (SSD) system including the storage device in accordance with some embodiments of the present disclosure.

Referring toFIG. 21, the SSD system3000includes a host3100and an SSD3200. The SSD3200exchanges a signal SIG with the host3100through a signal connector3001and receives power PWR through a power connector3002. The SSD3200includes an SSD controller3210, a plurality of flash memories3221to322n, an auxiliary power device3230, and a buffer memory3240.

In an embodiment of the present disclosure, the SSD controller3210may perform the function of the memory controller200ofFIG. 1described with reference toFIG. 1.

The SSD controller3210may control the plurality of flash memories3221to322nin response to the signal SIG received from the host3100. As an example, the signal SIG may be signals based on an interface between the host3100and the SSD3200. For example, the signal SIG may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multi-media card (MMC), an embedded MMC (MCM), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe.

In an embodiment of the present disclosure, when a first error correction for data obtained from a read operation performed by the plurality of flash memories3221to322nis failed, the plurality of flash memories3221to322nmay receive a soft read command from the SSD controller3210to perform a read operation corresponding to the soft read command. At this time, the plurality of flash memories3221to322nmay not provide all read data obtained from the read operation corresponding to the soft read command to the SSD controller3210, but may provide the read data to the SSD controller3210by performing an XNOR operation on the read data.

As a result, the number of data provided from the plurality of flash memories3221to322nto the SSD controller3210may be reduced. In addition, since the plurality of flash memories3221to322nperform the XNOR operation on the read data, error correction efficiency of the SSD controller3210may increase.

The auxiliary power device3230is connected to the host3100through the power connector3002. The auxiliary power device3230may receive the power PWR from the host3100and may charge the power. The auxiliary power device3230may provide power of the SSD3200when power supply from the host3100is not smooth. As an example, the auxiliary power device3230may be positioned in the SSD3200or may be positioned outside the SSD3200. For example, the auxiliary power device3230may be positioned on a main board and may provide auxiliary power to the SSD3200.

The buffer memory3240operates as a buffer memory of the SSD3200. For example, the buffer memory3240may temporarily store data received from the host3100or data received from the plurality of flash memories3221to322n, or may temporarily store metadata (for example, a mapping table) of the flash memories3221to322n. The buffer memory3240may include a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, and a GRAM, or a non-volatile memory such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM.