Vertical memory devices and methods of manufacturing the same

A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2015-0147061, filed on Oct. 22, 2015, and entitled, “Vertical Memory Devices and Methods of Manufacturing the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

One or more embodiments described herein relate to vertical memory devices and methods for manufacturing vertical memory devices.

2. Description of the Related Art

A vertical memory device has been developed having a relatively high degree of integration. Such a memory device includes memory cells stacked vertically with respect to the surface of a substrate. A channel having a pillar or cylindrical shape protrudes vertically from the substrate surface, and gate lines and insulation layers surrounding the channel are repeatedly stacked.

As the degree of integration of the vertical memory device increases, the numbers of the gate lines and insulation layers increase. Thus, structural and electrical reliability of the vertical memory device may not be easily achieved.

SUMMARY

In accordance with one or more embodiments, a vertical memory device includes a substrate; gate lines stacked and spaced apart from each other along a first direction with respect to a surface of the substrate, each of the gate lines including a step portion protruding in a second direction; at least one etch-stop layer covering the step portion of at least one of the gate lines and including a conductive material; channels extending through the gate lines in the first direction; and contacts extending through the at least one etch-stop layer and on the step portions of the gate lines.

The vertical memory device may include insulating interlayer patterns spaced apart from each other by the gate lines along the first direction, each of the insulating interlayer patterns including a step portion protruding in the second direction. The at least one etch-stop layer may include a first etch-stop layer arranged along the step portions of the insulating interlayer patterns, the first etch-stop layer including an oxide; and a second etch-stop layer on the first etch-stop layer and including a conductive material. The second-etch stop layer may include a same metal as in the gate lines. The first etch-stop layer may include a same oxide as in the insulating interlayer patterns. The second etch-stop layer may be divided per each step portion of the insulating interlayer patterns. The contacts may be physically separated from the at least one etch-stop layer. The vertical memory device may include a plurality of contact spacers surrounding sidewalls of the contacts.

The at least one etch-stop layer may cover step portions of at least some of the gate lines. The gate lines may include a ground selection line (GSL), word lines, and a string selection line (SSL) sequentially stacked from the top surface of the substrate. The at least one etch-stop layer may only cover step portions of the GSL and the word lines. The at least one etch-stop layer may only cover step portions of predetermined ones of the word lines. The substrate may include a cell region on which the channels are disposed; an extension region on which the step portions of the gate lines are disposed; and a peripheral circuit region, wherein the at least one etch-stop layer is only on the cell region and the extension region.

In accordance with one or more other embodiments, a vertical memory device includes a substrate; a gate line stack structure on the substrate and including: gate lines stacked and spaced apart from each other in a first direction with respect to a surface of the substrate; insulating interlayer patterns stacked and spaced apart from each other by the gate lines in the first direction; and channels extending through the insulating interlayer patterns and the gate lines in the first direction; a first etch-stop layer on the gate line stack structure and including an insulation material; a second etch-stop layer on the first etch-stop layer and including a conductive material; and contacts extending through the second etch-stop layer and the first etch-stop layer and electrically connected to the gate lines. The insulating interlayer patterns and the gate lines may be alternately stacked along the first direction in a stepped shape, the insulating interlayer patterns and gate lines may include step portions protruding in a second direction, and step portions of the gate lines may be covered by step portions of the insulating interlayer patterns.

In accordance with one or more other embodiments, a memory device includes a substrate; a plurality of gate lines stacked on the substrate; a plurality of insulating layers between the gate lines respectively, the gate lines and insulating layers arranged in steps; a first etch-stop layer on the steps and including a first material; a second etch-stop layer on the first etch-stop layer and including a second material different from the first material; channels extending through the gate lines; and contacts extending through the first and second etch-stop layers to contact respective ones of the gate lines through corresponding ones of the insulating layers. The first material may be an oxide, and the second material may be a conductive material. The first etch-stop layer may include the first material, and the second-etch stop layer may include the second material. The gate lines may include a ground selection line, word lines, and a string selection line sequentially stacked from the surface of the substrate. The first and second etch-stop layers may cover only step portions of predetermined ones of the GSL and the word lines.

DETAILED DESCRIPTION

FIG. 1illustrates a top plan view of an embodiment of a vertical memory device, andFIGS. 2 and 3illustrate cross-sectional views taken along lines I-I′ and II-II′ inFIG. 1, respectively. InFIGS. 1 to 3, a direction substantially vertical to a top surface of a substrate is a first direction, and two directions substantially parallel to the top surface of the substrate and crossing each other are second and third directions. For example, the second and third directions are substantially perpendicular to each other. Additionally, a direction indicated by an arrow and a reverse direction thereof are considered as the same direction. The above mentioned definitions of the directions are the same throughout all the figures in this specification. (For convenience of descriptions, an illustration of some insulative structures is omitted inFIG. 1).

Referring toFIGS. 1 to 3, the vertical memory device may include a vertical channel structure, including a channel144, a dielectric layer structure142, and a filling insulation pattern146, extending in the first direction from a top surface of a substrate100. The vertical memory device may also include gate lines160, e.g., gate lines160ato160h, surrounding the vertical channel structure and stacked in a stepped shape along the first direction. Contacts197are electrically connected to the gate lines160and may extend through a mold protection layer130, a second etch-stop layer pattern165, a first etch-stop layer pattern112, and an insulating interlayer pattern106at each level. The contacts197may be electrically connected to a step portion of the gate line160at each level.

In particular, the gate lines160a-160hmay be stacked on one another in the first direction and may extend along the second direction such that the gate line106aextends further away in the second direction than adjacent gate line106b, and so forth. The decrease in length in the second direction among the gate lines160a-160hmay be the same or different among various embodiments to thereby form a step pattern.

The substrate100may include a semiconductor material, e.g., silicon and/or germanium. In example embodiments, the substrate100may include single crystalline silicon, e.g., a p-type well of the vertical memory device.

The vertical memory device may include a first region I, a second region II, and a third region III. Accordingly, the substrate100may be divided into the first region I, the second region II, and the third region III. In example embodiments, the first region I, the second region II, and the third region III may correspond to a cell region, an extension region, and a peripheral circuit region, respectively.

Memory cells of the vertical memory device may be on the cell region. For example, a cell string may be defined by the vertical channel structure and the gate lines160surrounding the vertical channel structure. The gate lines160may extend in the second direction, and the step portions of the gate lines160may be on the extension region. A peripheral circuit to drive the vertical memory device may be on the peripheral circuit region. In some embodiments, a pair of second regions II may be located symmetrically with respect to the first region I.

The channel144may be on the first region I of the substrate100and may have a hollow cylindrical shape or a cup shape. The channel144may include polysilicon or single crystalline silicon, and may include p-type impurities such as boron (B) in a portion thereof.

The filling insulation pattern146may fill an inner space of the channel144, and may have a solid cylindrical shape or a pillar shape. The filling insulation pattern146may include an insulation material such as silicon oxide. In an embodiment, the channel144may have a pillar shape or a solid cylindrical shape, and the filling insulation pattern146may be omitted.

The dielectric layer structure142may be formed on an outer sidewall of the channel144and may have a straw shape. The dielectric layer structure142may include a tunnel insulation layer, a charge storage layer, and a blocking layer sequentially stacked from the outer sidewall of the channel144. The blocking layer may include silicon oxide or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may include a nitride such as silicon nitride or a metal oxide. The tunnel insulation layer may include an oxide such as silicon oxide. For example, the dielectric layer structure142may have an oxide-nitride-oxide (ONO) layered structure.

As illustrated inFIGS. 2 and 3, a semiconductor pattern140may be between the top surface of the substrate100and the vertical channel structure. In example embodiments, a channel hole may be formed through the gate lines160and the insulating interlayer patterns106. The top surface of the substrate100may be exposed through the channel hole. The semiconductor pattern140may be formed at a lower portion of the channel hole to be in contact with the top surface of the substrate100. The channel144may be on a top surface of the semiconductor pattern140. The dielectric layer structure142may be on a peripheral portion of the top surface of the semiconductor pattern140.

A pad148may be formed on the dielectric layer structure142, the channel144, and the filling insulation pattern146. For example, an upper portion of the channel hole may be capped by the pad148. For example, the pad148may be electrically connected to, e.g., a bit line, and may serve as a source/drain region through which charges are moved or transferred to the channel144. The semiconductor pattern140and the pad148may include polysilicon or single crystalline silicon. In some embodiments, the pad148may be optionally doped with n-type impurities such as phosphorus (P) or arsenic (As).

In example embodiments, a plurality of the pads148may be arranged along the second direction on the first region I in a pad row. A plurality of pad rows may be arranged in the third direction. For convenience of descriptions, only one pad148is illustrated per each pad row inFIG. 1.

The vertical channel structures may also be arranged according to an arrangement of the pads148. For example, a plurality of the vertical channel structures may be arranged along the second direction on the first region I to form a channel row, and a plurality of the channel rows may be arranged in the third direction.

The gate lines160(e.g.,160athrough160h) may be formed on an outer sidewall of the dielectric layer structure142or the semiconductor pattern140. The gate lines160may be spaced apart from each other along the first direction. In example embodiments, each gate line160may partially surround the channels144or the vertical channel structures in at least one of the channel rows, and may extend in the second direction.

In some embodiments, each gate line160may surround the predetermined number of the channel rows, e.g., 4 channel rows. In this case, a gate line stack structure may be defined by the 4 channel rows and the gate lines160surrounding the 4 channel rows. A plurality of the gate line stack structures may be arranged along the third direction.

In example embodiments, widths or length of the gate lines160in the second direction may be reduced along the first direction from the top surface of the substrate100. For example, as illustrated inFIGS. 1 and 2, a plurality of the gate lines160may be stacked in a pyramidal shape or a stepped shape. Accordingly, the gate line160of each level may include the step portion protruding in the second direction from the gate line160at an upper level thereof. The step portion of the gate line160may serve as a pad on which the contact197may be disposed. The step portions of the gate lines160may be arranged on the second region II.

The gate lines160may include a ground selection line (GSL), a word line, and a string selection line (SSL). For example, a lowermost gate line160amay serve as the GSL, an uppermost gate line160hmay serve as the SSL, and the gate lines160bto160gbetween the GSL and the SSL may serve as the word lines. The GSL (e.g., gate line160a) may laterally surround the semiconductor pattern140. The word lines (e.g., gate lines160bto160g) and the SSL (e.g., gate line160h) may laterally surround the channel144or the dielectric layer structure142.

The gate lines160may be formed at increased levels in consideration of circuit design and/or degree of integration of the vertical memory device, e.g. 16 levels, 24 levels, 32 levels, 48 levels, etc. The SSLs may be formed at two or more levels.

The gate line160may include a metal such as tungsten (W), a metal nitride, and/or a metal silicide. In some example embodiments, the gate line160may include tungsten. In some embodiments, the gate line160may have a multi-layered structure of a metal nitride/metal, e.g., tungsten nitride/tungsten.

The gate line stack structure may further include the insulating interlayer patterns106(e.g.,106athrough106i). The insulating interlayer patterns106may be between the gate lines160neighboring in the first direction.

A lowermost insulating interlayer pattern106amay be formed between the GSL160aand the top surface of the substrate100. As illustrated inFIG. 2, the lowermost insulating interlayer pattern106amay cover the first region I and the second region II of the substrate100. In some embodiments, the lowermost insulating interlayer pattern106amay commonly cover the first region I, the second region II, and the third region III of the substrate100. An uppermost insulating interlayer pattern106imay be on the SSL160h.

The insulating interlayer pattern106may include a silicon oxide-based material, e.g., silicon dioxide (SiO2), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF). The gate lines160in one gate line stack structure may be insulated from each other by the insulating interlayer patterns106. In example embodiments, the insulating interlayer patterns106may be stacked along the first direction, for example, in a pyramidal shape or a stepped shape, substantially the same as or similar to that of the gate lines160.

The insulating interlayer pattern106at each level may also include, for example, a step portion protruding in the second direction on the second region II. For example, a top surface of the step portion of the gate line160may be covered by the step portion of the insulating interlayer pattern106.

In example embodiments, a multi-layered etch-stop layer pattern including a first etch-stop layer pattern112and a second etch-stop layer pattern165may be formed on the gate line stack structure.

The first etch-stop layer pattern112may be formed conformally along top surfaces of the insulating interlayer patterns106, sidewalls in the second direction of the insulating interlayer patterns106, and sidewalls in the second direction of the gate lines160. In some embodiments, the first etch-stop layer pattern112may not be formed on sidewalls in the third direction of insulating interlayer patterns106and gate lines160.

In example embodiments, the first etch-stop layer pattern112may cover all the step portions of the insulating interlayer patterns106and the gate lines160in the gate line stack structure. In example embodiments, the first etch-stop layer pattern112may include an oxide substantially the same as or similar to that included in the insulating interlayer pattern106.

The second etch-stop layer pattern165may be formed on the first etch-stop layer pattern112. For example, the second etch-stop layer patter165may be in contact with a substantially entire top surface of the first etch-stop layer pattern112. Accordingly, the second etch-stop layer pattern165may also cover all the step portions of insulating interlayer patterns106and gate lines160in the gate line stack structure.

In example embodiments, the second etch-stop layer pattern165may include a conductive material substantially the same as or similar to that included in the gate line160. In some embodiments, the gate line160and the second etch-stop layer pattern165may include tungsten.

In some embodiments, the vertical channel structure may extend through the second and first etch-stop layer patterns165and112on the first region I.

The mold protection layer130may be formed on the substrate100, and may cover the gate line stack structure. In example embodiments, the mold protection layer130may be formed commonly on the first region I, the second region II, and the third region III, and may be formed on top surfaces of the substrate100and the second etch-stop layer pattern165.

In some embodiments, if the lowermost insulating interlayer pattern106aextends on the third region III, the mold protection layer130may be formed on a top surface of the lowermost insulating interlayer pattern106a. In example embodiments, the mold protection layer130may include an oxide substantially the same as or similar to that included in the insulating interlayer pattern106and/or the first etch-stop layer pattern112(e.g., silicon oxide).

A cutting pattern170may be between the gate line stack structures. For example, the cutting pattern170may intersect the gate lines160, the insulating interlayer patterns106, the etch-stop layer pattern, and the mold protection layer130, and may have a fence shape extending in the second direction. The gate line stack structure including the predetermined number of the channel rows (e.g., the four channel rows) may be defined by the cutting pattern170. The cutting pattern170may include an insulation material, e.g., silicon oxide.

An impurity region101(see, e.g.,FIG. 3) may be formed at an upper portion of the substrate100under the cutting pattern170. The impurity region101may include, e.g., n-type impurities. In some embodiments, the impurity region101may extend in the second direction and may serve as a common source line (CSL) of the vertical memory device. In some embodiments, a CSL contact or a CSL pattern may be formed through the cutting pattern170and electrically connected to the impurity region101.

The contacts197may extend through the mold protection layer130, the second etch-stop layer pattern165, the first etch-stop layer pattern112, and the step portion of the insulating interlayer pattern106at each level. The contact197may be in contact with or electrically connected to the step portion of the gate line160at each level.

In some embodiments, as illustrated inFIG. 2, the contacts197may be partially inserted in some gate lines at lower levels of the gate line stack structure (e.g., the GSL160aand some word lines160bthrough160d). The contacts197may include a metal, a metal nitride, doped polysilicon, and/or a metal silicide.

A contact spacer195may be formed on a sidewall of each contact197. The contact spacer195may have a straw shape surrounding the sidewall of the contact197. The second etch-stop layer pattern165and the contact197may be insulated from each other by the contact spacer195. For example, the contact spacer195may include silicon nitride or silicon oxynitride.

In some embodiments, as illustrated inFIG. 1, the contacts197may be arranged in a substantially linear line along the second direction in a plane view. In some embodiments, the contacts197may be arranged in a different (e.g., zigzag) configuration along the second direction in the plane view.

In some embodiments, a bit line may be on the first region I and electrically connected to the pads148. Wirings may be on the mold protection layer130and electrically connected to the contacts197. The wirings may extend from the second region II to the third region III and may be electrically connected to the peripheral circuit.

According to example embodiments as described above, the multi-layered etch-stop layer pattern including the first etch-stop layer pattern112and the second etch-stop layer pattern165may be formed along top and lateral surfaces of the gate line stack structure. For example, the first etch-stop layer pattern112may include silicon oxide substantially the same as or similar to that in the insulating interlayer pattern106. The second etch-stop layer pattern165may include a metal substantially the same as or similar to that in the gate line160.

Thus, while forming contact holes in which the contacts197may be formed and through which the step portions of the gate lines160may be exposed, defects such as a punching of the gate line160or a not-open failure of the step portion may be prevented throughout all levels of the gate line stack structure utilizing the etch-stop layer pattern.

FIGS. 4 to 30illustrate top plan views and cross-sectional views of an embodiment of a method of manufacturing a vertical memory device, which, for example, may be the vertical memory device inFIGS. 1 to 3.FIGS. 9, 13, 18 and 21are top plan views illustrating the method.FIGS. 4 to 8, 10 to 12, 14, 16, 19, and 23 to 30are cross-sectional views taken along line I-I′ inFIGS. 9, 13, 18 and 21.FIGS. 15, 17, 20 and 22are cross-sectional views taken along line II-II′ in9,13,18and21. For convenience of descriptions, an illustration of insulative structures is omitted in some of the top plan views.

Referring toFIG. 4, insulating interlayers102(e.g.,102athrough102i) and sacrificial layers104(e.g.,104athrough104h) may be formed alternately and repeatedly on a substrate100to form a mold structure. The substrate100may include a semiconductor material silicon or germanium. In example embodiments, the substrate100may include a first region I, a second region II, and a third region III. For example, the first region I, the second region II, and the third region III may correspond to a cell region, an extension region, and a peripheral circuit region of the vertical memory device.

The insulating interlayer102may be formed of an oxide-based material, e.g., silicon dioxide, silicon oxycarbide, and/or silicon oxyfluoride. The sacrificial layer104may be formed of a material having an etching selectivity with respect to the insulating interlayer102and which may be easily removed by a wet etching process. For example, the sacrificial layer104may be formed of a nitride-based material, e.g., silicon nitride and/or silicon boronitride.

The insulating interlayer102and the sacrificial layer104may be formed by at least one of a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an atomic layer deposition (ALD) process, or a sputtering process.

In an embodiment, a lowermost insulating interlayer102amay be formed by a thermal oxidation process or a radical oxidation process on a top surface of the substrate100. The sacrificial layers104may be removed in a subsequent process to provide spaces for a GSL, a word line(s), and an SSL. Thus, the number of the insulating interlayers102and the sacrificial layers104may be determined in consideration of the number of the GSL, the word line(s), and the SSLs.

FIG. 4illustrates that the sacrificial layers104and the insulating interlayers102are formed at 8 levels and 9 levels, respectively. However, the number of the insulating interlayers102and the sacrificial layers104may increase depending, for example, on a degree of integration of the vertical memory device.

Referring toFIG. 5, a lateral portion of the mold structure may be partially etched in, e.g., a stepwise manner, to form a stepped mold structure. For example, a photoresist pattern covering the first region I and partially covering the second region II may be formed on an uppermost insulating interlayer102i. Peripheral portions of the uppermost insulating interlayer102iand an uppermost sacrificial layer104hmay be removed using the photoresist pattern as an etching mask. A peripheral portion of the photoresist pattern may be partially removed so that a width of the photoresist pattern may be reduced. Peripheral portions of insulating interlayers102iand102h, and sacrificial layers104hand104gmay be etched using the photoresist pattern again as an etching mask. Etching processes may be repeated with a predetermined etching amount in a similar manner as described above to obtain the stepped mold structure inFIG. 5.

In some embodiments, as illustrated inFIG. 5, a portion of the lowermost insulating interlayer102aon the third region III may be also removed while forming the stepped mold structure. In some embodiments, the lowermost insulating interlayer102amay not be etched to remain on the third region III. The insulating interlayer102and the sacrificial layer104at each level in the stepped mold structure may include step portions protruding in the second direction on the second region II. A top surface of the step portion of the sacrificial layer104may be covered by the step portion of the insulating interlayer102. The photoresist pattern may be removed by an ashing process and/or a strip process after forming the stepped mold structure.

Referring toFIG. 6, a first etch-stop layer110may be formed along a surface of the stepped mold structure on the substrate100. A preliminary second etch-stop layer115may be formed on the first etch-stop layer110. In example embodiments, the first etch-stop layer110may be formed conformally along top surfaces and sidewalls of the insulating interlayers102and sidewalls of the sacrificial layers104. The preliminary etch-stop layer115may be formed to have a shape substantially the same as or similar to that of the first etch-stop layer110.

In example embodiments, the first etch-stop layer110may be formed of an oxide-based material, e.g., silicon oxide. For example, the first etch-stop layer110may include the oxide-based material substantially the same as or similar to that in the insulating interlayer102. The preliminary second etch-stop layer115may be formed of a nitride-based material, e.g., silicon nitride. For example, the preliminary second etch-stop layer115may be formed of the nitride-based material substantially the same as or similar to that in the sacrificial layer104.

The first etch-stop layer110and the preliminary second etch-stop layer115may be formed by, e.g., an ALD process or a sputtering process having an improved step-coverage property. The first etch-stop layer110and the preliminary second etch-stop layer115may have a thickness less than that of the insulating interlayer102and the sacrificial layer104, respectively, as illustrated inFIG. 6. However, the first etch-stop layer110and the preliminary second etch-stop layer115may have a thickness substantially equal to or greater than that of the insulating interlayer102and the sacrificial layer104, respectively.

Referring toFIG. 7, portions of the first etch-stop layer110and the preliminary second etch-stop layer115formed on the third region III may be removed. In example embodiments, a photoresist pattern120covering the first region I and the second region II may be formed on the preliminary second etch-stop layer115. The preliminary second etch-stop layer115and the first etch-stop layer110may be partially removed using the photoresist pattern as an etching mask. After the etching process described above, the top surface of the substrate100or a top surface of the lowermost insulating interlayer102amay be exposed on the third region III, and the photoresist pattern120may be removed by an ashing process and/or a strip process.

Referring toFIG. 8, a mold protection layer130covering the preliminary second etch-stop layer115may be formed on the substrate100. In example embodiments, the mold protection layer130may entirely cover the stepped mold structure. In some embodiments, an upper portion of the mold protection layer130may be planarized by, e.g., a chemical mechanical polish (CMP) process.

Referring toFIGS. 9 and 10, channel holes135may be formed through the stepped mold structure on the first region I. For example, a hard mask may be formed on the mold protection layer130. The insulating interlayers102and the sacrificial layers104of the stepped mold structure may be partially etched on the first region I by performing, e.g., a dry etching process. The hard mask may be used as an etching mask to form the channel hole135. The channel hole135may also extend through the preliminary second etch-stop layer115and the first etch-stop layer110. The channel hole135may extend in the first direction from the top surface of the substrate100, and the top surface of the substrate100may be partially exposed by the channel hole135. The hard mask may be formed of silicon-based or carbon-based spin-on hardmask (SOH) materials, and/or a photoresist material.

In example embodiments, a plurality of the channel holes135may be formed along the second direction to form a channel hole row. A plurality of the channel hole rows may be formed along the third direction. The channel hole rows may be arranged such that the channel holes135in different channel hole rows may be formed in a predetermined (e.g., zigzag) arrangement along the second direction and/or the third direction. The hard mask may be removed by an ashing process and/or a strip process after the formation of the channel holes135.

Referring toFIG. 11, a semiconductor pattern140, a dielectric layer structure142, a channel144, and a filling insulation pattern146may be formed in each channel hole135. In some example embodiments, a semiconductor pattern140may be formed at a lower portion of the channel hole135. For example, the semiconductor pattern140may be formed by a selective epitaxial growth (SEG) process using the top surface of the substrate100exposed through the channel hole135as a seed. In some embodiments, an amorphous silicon layer filling the lower portion of the channel hole135may be formed, and a laser epitaxial growth (LEG) process or a solid phase epitaxi (SPE) process may be performed thereon to form the semiconductor pattern140. In some embodiments, a top surface of the semiconductor pattern140may be positioned between the sacrificial layers104aand104bat two lower levels.

A dielectric layer may be formed along sidewalls of the channel holes135and top surfaces of the semiconductor pattern140and the mold protection layer130. Upper and lower portions of the dielectric layer may be removed by an etch-back process to form the dielectric layer structure142on the sidewall of the channel hole135.

A channel layer and a filling insulation layer filling remaining portions of the channel holes135may be sequentially formed. Upper portions of the channel layer and the filling insulation layer may be planarized by, e.g., a CMP process, until the mold protection layer130is exposed. Accordingly, the channel144and the filling insulation pattern146filling the channel hole135may be formed on the semiconductor pattern140. A vertical channel structure including the dielectric layer structure142, the channel144, and the filling insulation pattern146may be formed in each channel hole135.

The dielectric layer may be formed by sequentially forming a blocking layer, a charge storage layer, and a tunnel insulation layer. The blocking layer may be formed of, e.g., silicon oxide or a metal oxide. The charge storage layer may be formed of a nitride such as silicon nitride or a metal oxide. The tunnel insulation layer may include an oxide such as silicon oxide. For example, the dielectric layer may be formed as an oxide-nitride-oxide (ONO) layered structure. The blocking layer, the charge storage layer, and the tunnel insulation layer may be formed by a CVD process, a PECVD process, an ALD process, etc.

The channel layer may be formed of polysilicon or amorphous silicon which is optionally doped with impurities. In an embodiment, a heat treatment or a laser beam irradiation may be further performed on the channel layer. In this case, the channel layer may be transformed to include single crystalline silicon. The filling insulation layer may be formed of, e.g., silicon oxide or silicon nitride. The channel layer and the filling insulation layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc.

The dielectric layer structure142may have a straw shape or a cylindrical shell shape surrounding an outer sidewall of the channel144. The channel144may have a substantially cup shape. The filling insulation pattern146may have a pillar shape inserted in the channel144. In some embodiments, the formation of the filling insulation layer may be omitted, and the channel may have a pillar shape filling the channel135.

Referring toFIG. 12, a pad148capping an upper portion of the channel hole135may be formed. For example, an upper portion of the vertical channel structure may be partially removed by, e.g., an etch-back process to form a recess. A pad layer may be formed on the dielectric layer structure142, the channel144, the filling insulation pattern146, and the mold protection layer130to sufficiently fill the recess. An upper portion of the pad layer may be planarized by, e.g., a CMP process, until a top surface of the mold protection layer130is exposed to form the pad148from a remaining portion of the pad layer.

The pad layer may be formed using polysilicon optionally doped with n-type impurities by a sputtering process or an ALD process. In an embodiment, a preliminary pad layer including amorphous silicon may be formed, and then a crystallization process may be performed thereon to form the pad layer.

According to the arrangement of the channel hole row, a plurality of pads148may define a pad row in an upper portion of the mold protection layer130. A plurality of the pad rows may be formed along the third direction. A channel row may be defined under the pad row, and a plurality of the channel rows may be arranged along the third direction.

Referring toFIGS. 13 to 15, an opening150extending through the stepped mold structure may be formed. For example, a hard mask covering the pads148and partially exposing the mold protection layer130between some of the pad rows may be formed. The mold protection layer130, the first etch-stop layer110, the preliminary second etch-stop layer115, the insulating interlayers102, and the sacrificial layers104may be partially etched by, e.g., a dry etching process using the hard mask to form the opening150. The hard mask may be formed using a photoresist material or an SOH material, and may be removed by an ashing process and/or a strip process after the formation of the opening150.

The opening150may extend in, e.g., the second direction, and a plurality of the openings150may be formed along the third direction. The predetermined number of the channel rows may be arranged between the openings150neighboring in the third direction. For example, as illustrated inFIG. 13, four channel rows may be between the neighboring openings150. However, the number of the channel rows between the openings150may be properly adjusted in consideration of circuit design or degree of integration of the vertical memory device.

As illustrated inFIG. 15, after formation of the opening150, the insulating interlayers102and the sacrificial layers104may be changed to insulating interlayer patterns106(e.g.,106athrough106i) and sacrificial patterns108(e.g.,108athrough108h). The insulating interlayer pattern106and the sacrificial pattern108at each level may have a plate shape extending in the second direction. The top surface of the substrate100and sidewalls of the insulating interlayer patterns106and the sacrificial patterns108may be exposed through the opening150.

In example embodiments, the first etch-stop layer110and the preliminary second etch-stop layer115may be also cut by the opening150to form a first etch-stop layer pattern112and a preliminary second etch-stop layer pattern117. Sidewalls of the first etch-stop layer pattern112and the preliminary second etch-stop layer pattern117may be exposed through the opening150.

Referring toFIGS. 16 and 17, the sacrificial patterns108and the preliminary second etch-stop layer pattern117exposed by the opening150may be removed. In example embodiments, the sacrificial patterns108and the preliminary second etch-stop layer pattern117may be removed by a wet etching process using, e.g., phosphoric acid as an etchant solution that has an etching selectivity for silicon nitride.

A first gap152may be defined by a space from which the sacrificial pattern108is removed between the insulating interlayer patterns106neighboring in the first direction. A sidewall of the dielectric layer structure142may be partially exposed by the first gaps152. In some embodiments, a sidewall of the semiconductor pattern140may be exposed by a lowermost first gap152.

In example embodiments, a second gap154may be defined by a space from which the preliminary second etch-stop layer pattern117is removed. The second gap154may extend in a stepped shape between the mold protection layer130and the first etch-stop layer pattern112. As illustrated inFIG. 17, an upper portion of the dielectric layer structure142may be exposed by an upper portion of the second gap154.

Referring toFIGS. 18 to 20, gate lines160(e.g.,160athrough160h) may be formed in the first gaps152, and a second etch-stop layer pattern165may be formed in the second gap154. In example embodiments, a first conductive layer substantially fully filling the first and second gaps152and154and at least partially filling the opening150may be formed. The first conductive layer may be also formed on the mold protection layer130and the pads148.

The first conductive layer may be formed using a metal such as tungsten, aluminum, copper, titanium or tantalum, or a nitride of the metal. In some embodiments, the first conductive layer may be formed of tungsten. In an embodiment, the first conductive layer may be formed as a multi-layered structure including a barrier layer formed of a metal nitride, and a metal layer. The first conductive layer may be formed by a CVD process, a PECVD process, an ALD process, a PVD process, a sputtering process, etc.

In an embodiment, before forming the first conductive layer, an additional blocking layer including, e.g., a metal oxide may be formed on inner walls of the first and second gaps152and154.

In example embodiments, an upper portion of the first conductive layer may be planarized by a CMP process until the mold protection layer130may be exposed. Portions of the first conductive layer formed in the opening150and on the top surface of the substrate100may be etched to obtain the gate lines160and the second etch-stop layer pattern165in the first gaps152and the second gap154, respectively.

The gate lines160may include the GSL (e.g., the gate line160a), the word lines (e.g., the gate lines160bthrough160g), and the SSL (e.g., the gate line160h) sequentially stacked and spaced apart from one another along the first direction.

The gate line160and the insulating interlayer pattern106at each level may extend in the second direction and may surround the predetermined number of the channel rows (e.g., four channel rows). A gate line stack structure may be defined by the gate lines160, the insulating interlayer patterns106, and the channel rows in the gate lines160and the insulating interlayer patterns106. A plurality of the gate line stack structures may be arranged along the third direction, and may be spaced apart from each other by the openings150.

The gate line stack structure may have a pyramidal shape or a stepped shape substantially the same as or similar to that of the stepped mold structure. For example, the gate line160and the insulating interlayer pattern106at each level may include a step portion protruding in the second direction in a plane view.

In example embodiments, a multi-layered etch-stop layer including the first etch-stop layer pattern112and the second etch-stop layer pattern165may be formed on the gate line stack structure. As describe above, the second etch-stop layer pattern165and the gate lines160may be formed by substantially the same deposition and etching processes from the first conductive layer.

The etch-stop layer, as illustrated inFIG. 19, may be formed on uppermost and lowermost insulating interlayer pattern106iand106b, and continuously along the step portions of the gate line stack structure. As illustrated inFIG. 20, the etch-stop layer may surround a sidewall of an upper portion of the vertical channel structure.

Referring toFIGS. 21 and 22, an ion-implantation process may be performed to form an impurity region101at an upper portion of the substrate100exposed through the opening150. A cutting pattern170filling the opening150may be formed on the impurity region101. The impurity region101may extend in the second direction, and may serve as, e.g., a CSL of the vertical memory device. A metal silicide pattern may be further formed on the impurity region101to reduce a resistance of the CSL. The cutting pattern170may be formed by filling or depositing an insulation material, e.g., silicon oxide in the opening150. In some embodiments, the cutting pattern170may be substantially merged with the mold protection layer130.

Referring toFIG. 23, a mask pattern180may be formed on the mold protection layer130. The mask pattern180may substantially fully cover the first region I, and may include holes182exposing regions for forming contact holes by subsequent processes on the second region II. In some embodiments, the mask pattern180may substantially fully cover the third region III. In some embodiments, the holes182may be also formed on the third region III for forming, e.g., a peripheral circuit contact hole. The mask pattern180may be formed of, e.g., amorphous carbon layer (ACL), an SOH material or a photoresist material.

Referring toFIG. 24, a first etching process may be performed using the mask pattern180. The mold protection layer130may be partially removed by the first etching process to form the contact holes. The first etching process may include a dry etching process having a high etching selectivity for an oxide. The contact holes formed by the first etching process may include first contact holes183aand second contact holes183b.

In example embodiments, the first contact holes183amay be formed on the gate lines160at upper levels (e.g., the gate lines160eto160h) in the gate line stack structure. The second contact holes183bmay be formed on the gate lines160of lower levels (e.g., the gate lines160dto160a) except for the gate lines160of the upper levels.

The first etching process may be ceased before a bottom of the second contact hole183breaches a portion of the second etch-stop layer pattern165at the lower levels. Accordingly, a portion of the second etch-stop layer pattern165at the upper levels may be exposed through the first contact holes183athat may have relatively small aspect ratios. The second etch-stop layer pattern165may include a conductive material (e.g., a metal such as tungsten) having a high etching selectivity with respect to the oxide. Thus, an extension of the first contact hole183amay be substantially blocked or ceased by the second etch-stop layer pattern165.

In some embodiments, as illustrated inFIG. 24, the first contact holes183amay extend partially into the second etch-stop layer pattern165.

Referring toFIG. 25, a second etching process may be performed to remove the portion of the second etch-stop layer pattern165exposed through the first contact holes183a. The second etching process may include a dry etching process having a relatively low etching selectivity for the oxide. Accordingly, the first contact holes183amay be further expanded in the first direction and penetrate through the second etch-stop layer pattern165. In some embodiments, the first contact holes183may extend partially into the first etch-stop layer pattern112.

In some embodiments, lengths of the second contact holes183bmay also increase by the second etching process. In some embodiments, the bottom of the second contact hole183bmay not reach the second etch-stop layer pattern165at the lower levels even after the second etching process, and the second contact holes183bmay remain in the mold protection layer130.

Referring toFIG. 26, a third etching process may be performed to further increase lengths of the contact holes. The third etching process may include a dry etching process having a high etching selectivity for the oxide.

In example embodiments, the first contact holes183amay extend through the first etch-stop layer pattern112and the insulating interlayer patterns106at the upper levels (e.g., the insulating interlayer patterns106fto106i) by the third etching process. The third etching process may be performed until the top surfaces of the gate lines160at the upper levels (e.g., the gate lines160eto160h) may be exposed through the first contact holes183a.

The lengths of the second contact holes183bmay further increase such that the second contact holes183bmay extend through the second etch-stop layer pattern165. For example, an upper one of the second contact holes183bmay also extend at least partially through the first etch-stop layer pattern112. In an embodiment, a lowermost second contact hole183bformed over the GSL160amay not reach the second etch-stop layer pattern165, and may still remain in the mold protection layer130.

Referring toFIG. 27, a fourth etching process may be performed such that the second contact holes183bmay additionally extend in the first direction. In example embodiments, the lengths of the second contact holes183bmay further increase by the fourth etching process to expose the step portions of the gate lines160at the lower levels (e.g., the gate lines160ato160d).

In some embodiments, the gate lines160at the upper levels (e.g., the gate lines160eto160h) may substantially serve as an etch-stop layer, and the lengths of the first contact holes183amay be maintained after the fourth etching process. In some embodiments, the gate lines160ato160dat the lower levels may be partially over-etched by the fourth etching process. Accordingly, the second contact holes183bmay extend partially into the gate lines160ato160dat the lower levels. After the first to fourth etching processes, the mask pattern180may be removed by, e.g., an ashing process and/or a strip process.

As described with reference toFIGS. 24 to 27, the first and second contact holes183aand183bmay be formed without defects such as a punching or a not-open failure of the gate lines.

In a comparative example, if the contact holes183aand183bare formed by a single etching process, etching selectivity between the oxide and the conductive material in the gate lines160may be degraded while forming, e.g., the second contact holes183bhaving relatively high aspect ratios. As a result, the second contact holes183bmay extend completely through the gate lines160(e.g.,160bto160d) to cause the punching of the gate lines160. Further, an etching rate may be excessively reduced over the lowermost gate line160a(e.g., GSL), and the lowermost gate line160amay not be exposed through the second contact hole183bto cause a not-open failure. In effort to avoid punching and a not-open failure, the contact holes183aand183bmay be formed by a plurality of photo-lithography processes. However, this may increase process costs and time by an excessive amount.

According to example embodiments as described above, the first etch-stop layer pattern112and the second etch-stop layer pattern165respectively including an oxide and a conductive material are formed on the gate line stack structure. Thus, degradation or reduction of etching selectivity may be reduced or prevented. Further, etching conditions may be finely controlled using a plurality of phases in a single etching process. Thus, lengths of the contact holes183aand183bmay be also finely controlled.

Referring toFIG. 28, a contact spacer layer190may be formed along the top surface of the mold protection layer130, and sidewalls and bottom surfaces of the contact holes183aand183b. For example, the contact spacer layer190may be formed of silicon nitride or silicon oxynitride, and may be formed by an ALD process or a sputtering process having an improved step-coverage property.

Referring toFIG. 29, portions of the contact spacer layer190formed on the top surface of the mold protection layer130, and the bottom surfaces of the contact holes183aand183bmay be removed by, e.g., an etch-back process. Accordingly, a contact spacer195may be formed on the sidewall of each of the contact holes183aand183b. In example embodiments, the contact spacer195may have a straw shape, and step portions of the gate lines160may be exposed again through the contact holes183aand183b.

Referring toFIG. 30, the contacts197filling the contact holes183aand183bmay be formed on the step portions of the gate lines160.

In example embodiments, a second conductive layer sufficiently filling the contact holes183aand183bmay be formed on the mold protection layer130. An upper portion of the second conductive layer may be planarized until the top surface of the mold protection layer130may be exposed to form the contacts197. The second conductive layer may be formed of a metal, a metal nitride, doped polysilicon and/or a metal silicide by an ALD process or a sputtering process.

The contact spacer195may surround a sidewall of the contact197. Thus, the contact197may be insulated from the second etch-stop layer pattern165including the conductive material. In some embodiments, bit lines electrically connected to the pads148, and wirings electrically connected to the contacts197may be further formed on the mold protection layer130.

FIG. 31illustrates a cross-sectional view of another embodiment of a vertical memory device. The vertical memory device ofFIG. 31may have elements and/or structures substantially the same as or similar to those illustrated inFIGS. 1 to 3, except for the shape of an etch-stop layer.

Referring toFIG. 31, as also described with reference toFIGS. 1 to 3, a multi-layered etch-stop layer including a first etch-stop layer pattern112aand a second etch-stop layer pattern165amay be formed on a top surface and a sidewall of a gate line stack structure. In example embodiments, the etch-stop layer may continuously extend from a top surface of an uppermost insulating interlayer pattern106ito a top surface of a specific insulating interlayer pattern106at a lower level.

In some embodiments, the etch-stop layer may overlap some gate lines160, e.g., from an uppermost gate line160h(e.g., an SSL) to the gate lines160that may be vulnerable to a punching. In some embodiments, the etch-stop layer may overlap step portions of the SSL160hand word lines (e.g., the gate lines160gto160b). In some embodiments, the etch-stop layer may be removed from a step portion of the gate line160that may be vulnerable to a not-open failure. In an embodiment, the etch-stop layer may be removed from a step portion of a lowermost gate line160a(e.g., a GSL).

Contacts197on the word lines160bto160hand the SSL160imay extend through a mold protection130, the second etch-stop layer pattern165a, the first etch-stop layer pattern112a, and the insulating interlayer patterns106ito106cto be in contact with the gate lines160. The contact on the GSL160amay extend through the mold protection layer130and the insulating interlayer pattern106bto be in contact with the GSL160a.

FIGS. 32 to 34illustrate cross-sectional views of another embodiment of a method for manufacturing a vertical memory device. Referring toFIG. 32, processes substantially the same as or similar to those illustrated with reference toFIGS. 4 to 6are performed. In example embodiments, insulating interlayers102(e.g.,102athrough102i) and sacrificial layers104(e.g.,104athrough104h) may be alternately and repeatedly on a substrate100including a first region I, a second region II and a third region III to form a mold structure.

A portion of the mold structure on the second region II and the third region III may be etched in a stepwise manner by a plurality of photo-lithography processes to form a preliminary stepped mold structure as illustrated inFIG. 32.

The number of the photo-lithography processes for forming the preliminary stepped mold structure may be less than that for forming the stepped mold structure illustrated inFIG. 5. Thus, the preliminary stepped mold structure may include step portions less than those of the stepped mold structure illustrated inFIG. 5.

In example embodiments, the mold structure may not be fully removed on the third region III. For example, insulating interlayers102ato102cand sacrificial layers104aand104bat lower levels may not be removed by the photo-lithography process to remain on the third region III.

Subsequently, a first etch-stop layer110and a preliminary second etch-stop layer115may be formed on the preliminary stepped mold structure as described with reference toFIG. 6.

Referring toFIG. 33, a photo-lithography process may be additionally performed to remove portions of the preliminary second etch-stop layer115and the first etch-stop layer110formed on the third region III.

In example embodiments, a photoresist pattern120selectively covering the first region I and the second region II may be formed on the preliminary second etch-stop layer115. The portions of the preliminary second etch-stop layer115and the first etch-stop layer110formed on the third region III may be removed using the photoresist pattern120. A portion of the preliminary stepped mold structure on the third region III may be also partially removed.

In some embodiments, the insulating interlayer102cand the sacrificial layer104bmay be etched by the photo-lithography process such that a step portion may be added to the preliminary stepped mold structure.

Referring toFIG. 34, a width in the second direction of the photoresist pattern120may be reduced, and a photo-lithography process may be further performed.

In example embodiments, the preliminary second etch-stop layer115and the first etch-stop layer110may be additionally etched, and the insulating interlayers102ato102cand the sacrificial layers104aand104bmay be also additionally etched by the photo-lithography process.

Accordingly, a step portion may be added again to the preliminary stepped mold structure ofFIG. 33such that a stepped mold structure may be obtained. The preliminary second etch-stop layer115and the first etch-stop layer110may cover step portions of the stepped mold structure except for a lowermost step portion.

After forming the stepped mold structure, the photoresist pattern120may be removed by an ashing process and/or a strip process. Subsequently, processes substantially the same as or similar to those illustrated with reference toFIGS. 8 to 30may be performed to obtain the vertical memory device ofFIG. 31.

According to example embodiments as described above, the etch-stop layer may be removed on a step portion of a gate line that may be vulnerable to a not-open failure (e.g., a GSL160a). An addition of the step portion in the preliminary stepped mold structure may be also implemented by the photo-lithography process for partially removing the etch-stop layer. Thus, process costs or time may be saved or reduced.

FIG. 35illustrates a cross-sectional view of another embodiment of a vertical memory device. The vertical memory device ofFIG. 35may have elements and/or structures substantially the same as or similar to those illustrated inFIGS. 1 to 3, except for the shape of an etch-stop layer.

Referring toFIG. 35, as also described with reference toFIGS. 1 to 3, a multi-layered etch-stop layer including a first etch-stop layer pattern112band a second etch-stop layer pattern165bmay be formed on a gate line stack structure. In example embodiments, the etch-stop layer may selectively overlap step portions of some specific word lines. In some embodiments, the etch-stop layer may selectively cover step portions of gate lines that may be vulnerable to a punching (e.g., the gate lines160cand160d). In some embodiments, the etch-stop layer may be removed over an SSL (e.g., the gate line160h), a GSL (e.g., the gate line160a), and some word lines (e.g., the gate lines160e,160f,160gand160b).

Contacts197on the gate lines160cand160dthat may be vulnerable to punching may extend through a mold protection layer130, the second etch-stop layer pattern165b, the first etch-stop layer pattern112b, and insulating interlayer patterns106dand106eand contact gate lines160. The contacts197on the SSL160h, the GSL160a, and the some word lines160e,160f,160gand160bmay extend through the mold protection layer130and the insulating interlayer patterns106i,106h,106g,106f,106cand106band contact the gate line160.

FIGS. 36 and 37illustrate cross-sectional views of another embodiment of a method for manufacturing a vertical memory device. Many of the processes and/or materials of this method may be substantially the same as or similar to those illustrated with reference toFIGS. 4 to 30.

Referring toFIG. 36, processes substantially the same as or similar to those inFIGS. 4 to 6may be performed. In example embodiments, insulating interlayers102(e.g.,102athrough102i) and sacrificial layers104(e.g.,104athrough104h) may be alternately and repeatedly on a substrate100including a first region I, a second region II, and a third region III to form a mold structure.

A portion of the mold structure on the second region II and the third region III may be etched in a stepwise manner by a plurality of photo-lithography processes to form a stepped mold structure. A first etch-stop layer110and a preliminary second etch-stop layer115may be sequentially formed along a surface of the stepped mold structure and a top surface of the substrate100. A photoresist pattern125selectively overlapping step portions of, e.g., some sacrificial layers104cand104dthat may be replaced with gate lines vulnerable to a punching, may be formed on the preliminary second etch-stop layer115of the second region II.

Referring toFIG. 37, portions of the preliminary second etch-stop layer115and the first etch-stop layer110that may not be covered by the photoresist pattern125may be removed by an etching process using the photoresist pattern125. Accordingly, the second etch-stop layer115and the first etch-stop layer110may selectively remain on the step portions of the some sacrificial layers104cand104d. After the etching process, the photoresist pattern125may be removed by an ashing process and/or a strip process.

Subsequently, processes substantially the same as or similar to those illustrated with reference toFIGS. 8 to 30may be performed to obtain the vertical memory device inFIG. 35.

FIG. 38illustrates a cross-sectional view of another embodiment of a vertical memory device. Many of the elements and/or structures of this embodiment may be substantially the same as or similar to those illustrated inFIGS. 1 to 3.

Referring toFIG. 38, as also described with reference toFIGS. 1 to 3, a multi-layered etch-stop layer including a first etch-stop layer pattern112and a second etch-stop layer pattern166may be formed on a top surface and a sidewall of a gate line stack structure. The first etch-stop layer pattern112may continuously extend on step portions from an uppermost gate line160hto a lowermost gate line160a.

In example embodiments, the second etch-stop layer pattern166may be individually divided per each step portion of the gate lines160. For example, each of the second etch-stop layer patterns166(e.g.,166athrough166h) may individually cover the step portions from the lowermost gate line160ato the uppermost gate line160h

Contacts198may extend through a mold protection layer130, the second etch-stop layer pattern166, the first etch-stop layer pattern112and insulating interlayer patterns106to be in contact with the gate lines160.

In some embodiments, the contact spacer195inFIGS. 1 to 3may be omitted.

In an embodiment, the second etch-stop layer pattern166may be individually separated per each level. Thus, the second etch-stop layer pattern166may be directly connected to the contact198. An efficient area of the contact198may be increased by the second etch-stop layer pattern166so that electrical resistance through the contact198may be reduced.

FIGS. 39 to 41illustrate cross-sectional views of another embodiment of a method for manufacturing a vertical memory device. Processes and/or materials of this embodiment may be substantially the same as or similar to those inFIGS. 4 to 30.

Referring toFIG. 39, processes substantially the same as or similar to those illustrated with reference toFIGS. 4 and 5may be performed. In example embodiments, insulating interlayers102(e.g.,102athrough102i) and sacrificial layers104(e.g.,104athrough104h) may be alternately and repeatedly on a substrate100including a first region I, a second region II, and a third region III to form a mold structure. A portion of the mold structure on the second region II and the third region III may be etched in a stepwise manner by a plurality of photo-lithography processes to form a stepped mold structure as inFIG. 39.

Referring toFIG. 40, a first etch-stop layer110and a preliminary second etch-stop layer116may be formed along a top surface of the substrate100and a surface of the stepped mold structure. The first etch-stop layer110may have a shape and a profile substantially the same as those illustrated inFIG. 6. In example embodiments, the preliminary second etch-stop layer116may be formed of silicon nitride by a deposition process performed under a low step-coverage condition. Accordingly, the preliminary second etch-stop layer116may be relatively thin on sidewalls of the stepped mold structure, and may be relatively thick on top surfaces of the stepped mold structure.

Referring toFIG. 41, a process substantially the same as or similar to that ofFIG. 7may be performed to remove portions of the preliminary second etch-stop layer116and the first etch-stop layer110formed on the third region III. Subsequently, the preliminary second etch-stop layer116may be additionally etched to form preliminary second etch-stop layer patterns118(e.g.,118athrough118h) individually separated per each level. In example embodiments, a portion of the preliminary second etch-stop layer116formed on the sidewall of the stepped mold structure may be removed by the etching process. A portion of the preliminary second etch-stop layer116formed on the top surface of the stepped mold structure may partially remain to form the preliminary second etch-stop layer patterns118.

Processes substantially the same as or similar to those ofFIGS. 8 to 30may be further performed to obtain the vertical memory device ofFIG. 38. In some embodiments, processes for forming a contact spacer as inFIGS. 28 and 29may be omitted. In example embodiments, the sacrificial layers104may be replaced with gate lines160, and the preliminary second etch-stop layer patterns118may be replaced with second etch-stop layer patterns166separated per each level.

FIGS. 42 and 43illustrate cross-sectional views of another embodiment of a vertical memory device. Many elements and/or structures of this embodiment may be substantially the same as or similar to those inFIGS. 1 to 3.

Referring toFIGS. 42 and 43, a first upper insulation layer200may be formed on the mold protection layer130. The first upper insulation layer200may be formed commonly on the first to third regions I, II, and III, and may cover the pads148.

A conductive pattern178may extend through the first upper insulation layer200and between gate lines stack structures neighboring each other. In example embodiments, the conductive pattern178may extend in the second direction to contact the impurity region101. In some embodiments, a metal silicide pattern including, e.g., cobalt silicide (CoSi) or nickel silicide (NiSi), may be formed between the conductive pattern178and the impurity region101.

The conductive pattern178may serve as a CSL or a CSL contact of the vertical memory device. A cutting pattern172may be formed on a sidewall of the conductive pattern178, and may extend between the gate line structures together with the conductive pattern178.

The pad148may be protected by the first upper insulation layer200while performing an etching process and/or a deposition process for forming the conductive pattern178.

A second upper insulation layer210may be formed on the first upper insulation layer200. A contact199and a contact spacer196may extend through the second and first upper insulation layers210and200, the mold protection layer130, the second etch-stop layer pattern165, the first etch-stop layer pattern112, and the insulating interlayer pattern106and contact a step portion of the gate line160at each level.

The conductive pattern178may be protected by the second upper insulation layer210while performing a deposition process and/or an etching process for forming the contact199and the contact spacer196.

The first and second upper insulation layers200and210may include an oxide-based material substantially the same as or similar to that of mold protection layer130.

In accordance with one or more of the aforementioned embodiments, a first etch-stop layer including an oxide and a second etch-stop layer including a conductive material equal to that included in a gate line may be formed on a surface of a gate line stack structure. An etch-stop layer having a structure substantially the same as or similar to a stack structure of an insulating interlayer and the gate line may be formed, and damage of, e.g., lower word lines, caused by an insufficient etching selectivity may be prevented while forming contact holes through which a step portion of each gate line may be exposed.

In example embodiments, a nonvolatile memory may be embodied to include a three dimensional (3D) memory array. The 3D memory array may be monolithically formed on a substrate (e.g., semiconductor substrate such as silicon, or semiconductor-on-insulator substrate). The 3D memory array may include two or more physical levels of memory cells having an active area above the substrate and circuitry associated with operation of those memory cells, whether such associated circuitry is above or within the substrate. The layers of each level of the array may be directly deposited on the layers of each underlying level of the array.

In example embodiments, the 3D memory array may include vertical NAND strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer.

The following patent documents, which are hereby incorporated by reference in their entirety, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array is configured as a plurality of levels with word lines and/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559.235; and US Pat. Pub. No. 2011/0233648.