Method and apparatus for duty-cycle correction in a serial data transmitter

A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

FIELD

One or more aspects of embodiments according to the present invention relate to serial data transmitters, and more particularly to a system and method for correcting duty cycle in a serial data transmitter.

BACKGROUND

In high-performance high-speed links, lane deterministic jitter (DJ) due to clock duty-cycle distortion (DCD) may be a significant fraction of the total lane deterministic jitter. In low-power high-performance links, due to the small size of the I/O driver circuits, systems and methods of calibration may be important for meeting duty-cycle distortion specifications. A large portion of deterministic jitter in a serial data transmitter may be caused by duty-cycle distortion (DCD) of the double data rate clock, and the mismatch in the output multiplexer (OMUX).

Thus, there is a need for a system and method for reducing duty-cycle distortion in a serial data transmitter.

SUMMARY

According to an embodiment of the present disclosure there is provided a circuit, including: a serial data transmitter having a data input, a clock input, and an output; a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter; and a duty cycle detection circuit, connected to the output of the serial data transmitter, the pattern generator being configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones, the serial data transmitter being configured to transmit, during each half cycle of a double data rate clock received at the clock input of the serial transmitter, a respective bit received at the data input of the serial transmitter, and the duty cycle detection circuit being configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

In one embodiment, the duty cycle detection circuit has a clock input and includes: a capacitor; a switched charge pump; and a clocked comparator, the switched charge pump being configured: to charge the capacitor when the output of the serial data transmitter is in a first state and to discharge the capacitor when the output of the serial data transmitter is in a second state, the clocked comparator being configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal at the clock input of the duty cycle detection circuit.

In one embodiment, the circuit includes a multiplexer having a first input, a second input, and an output, wherein the pattern generator is connected to the first input of the multiplexer, and the serial data transmitter is connected to the output of the multiplexer.

In one embodiment, the circuit includes a duty cycle correction circuit having an adjusted clock output connected to the clock input of the serial data transmitter, the duty cycle correction circuit being configured: to receive: a clock signal, and a duty cycle correction code; and to produce, at the adjusted clock output, an adjusted clock signal, the adjusted clock signal having a duty cycle adjusted according to the duty cycle correction code.

In one embodiment, the circuit includes a finite state machine circuit, configured: to reset the duty cycle detection circuit; to set the multiplexer to connect the pattern generator to the data input of the serial data transmitter; to command the pattern generator to generate a first pattern; and to generate a first duty cycle correction code based on one or more bits received from the duty cycle detection circuit.

In one embodiment, the finite state machine circuit includes a counter configured: to count up when a bit received from the duty cycle detection circuit has a first value, and to count down when a bit received from the duty cycle detection circuit has a second value, different from the first value.

In one embodiment, the finite state machine circuit is further configured: to command the pattern generator to generate a second pattern; to generate a second duty cycle correction code based on one or more bits received from the duty cycle detection circuit; and to feed, to the duty cycle correction circuit, a third duty cycle correction code, the third duty cycle correction code being an average of: the first duty cycle correction code, and the second duty cycle correction code.

In one embodiment, the duty cycle correction circuit includes an inverter having a programmable pull-up strength or a programmable pull-down strength.

According to an embodiment of the present disclosure there is provided a circuit, including: a serial data transmitter having a data input, a clock input, and an output; a clock source; and a duty cycle detection and correction circuit including a pattern generator configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones, the serial data transmitter being configured to transmit, during each half cycle of a double data rate clock received at the clock input of the serial transmitter, a respective bit received at the data input of the serial transmitter, the duty cycle detection and correction circuit being configured: to estimate, from a signal at the output of the serial data transmitter when the pattern is fed to the data input of the serial data transmitter, an error in a duty cycle of a clock embedded in the signal at the output of the serial data transmitter, and to form an adjusted clock signal from a clock signal produced by the clock source, the adjusted clock signal having a duty cycle adjusted to reduce the error.

In one embodiment, the duty cycle detection and correction circuit further includes a duty cycle detection circuit connected to the output of the serial data transmitter, and the pattern generator has a pattern data output configured to be selectively connected to the data input of the serial data transmitter; and the duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

In one embodiment, the duty cycle detection circuit has a clock input and includes: a capacitor; a switched charge pump; and a clocked comparator, the switched charge pump being configured: to charge the capacitor when the output of the serial data transmitter is in a first state and to discharge the capacitor when the output of the serial data transmitter is in a second state, the clocked comparator being configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal at the clock input of the duty cycle detection circuit.

In one embodiment, the circuit includes a multiplexer having a first input, a second input, and an output, wherein the pattern generator is connected to the first input of the multiplexer, and the serial data transmitter is connected to the output of the multiplexer.

In one embodiment, the circuit includes a duty cycle correction circuit having an adjusted clock output connected to the clock input of the serial data transmitter, the duty cycle correction circuit being configured: to receive: a clock signal, and a duty cycle correction code; and to produce, at the adjusted clock output, an adjusted clock signal, the adjusted clock signal having a duty cycle adjusted according to the duty cycle correction code.

In one embodiment, the circuit includes a finite state machine circuit, configured: to reset the duty cycle detection circuit; to set the multiplexer to connect the pattern generator to the data input of the serial data transmitter; to command the pattern generator to generate a first pattern; and to generate a first duty cycle correction code based on one or more bits received from the duty cycle detection circuit.

In one embodiment, the finite state machine circuit includes a counter configured: to count up when a bit received from the duty cycle detection circuit has a first value, and to count down when a bit received from the duty cycle detection circuit has a second value, different from the first value.

In one embodiment, the finite state machine circuit is further configured: to command the pattern generator to generate a first pattern; to generate a second duty cycle correction code based on one or more bits received from the duty cycle detection circuit; and to feed, to the duty cycle correction circuit, a third duty cycle correction code, the third duty cycle correction code being an average of: the first duty cycle correction code, and the second duty cycle correction code.

In one embodiment, the duty cycle correction circuit includes an inverter having a programmable pull-up strength or a programmable pull-down strength.

According to an embodiment of the present disclosure there is provided a display, including: a driver integrated circuit including a serial data receiver; and a timing controller including: a serial data transmitter having a data input, a clock input, and an output; a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter; and a duty cycle detection circuit, connected to the output of the serial data transmitter, the serial data transmitter being configured to transmit, during each half cycle of a double data rate clock received at the clock input of the serial transmitter, a respective bit received at the data input of the serial transmitter, the pattern generator being configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones, and the duty cycle detection circuit being configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

In one embodiment, the duty cycle detection circuit has a clock input and includes: a capacitor; a switched charge pump; and a clocked comparator, the switched charge pump being configured: to charge the capacitor when the output of the serial data transmitter is in a first state and to discharge the capacitor when the output of the serial data transmitter is in a second state, the clocked comparator being configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal at the clock input of the duty cycle detection circuit.

In one embodiment, the display includes a multiplexer having a first input, a second input, and an output, wherein the pattern generator is connected to the first input of the multiplexer, and the serial data transmitter is connected to the output of the multiplexer.

DETAILED DESCRIPTION

Referring toFIG. 1, in some embodiments a double data rate serial data transmitter includes a clock source110, an output multiplexer (OMUX)120, a pre-driver amplifier130and a driver amplifier140. One bit of data may be clocked out with each half-cycle of the clock, which alternately selects between the even and odd inputs of the OMUX120. Such a circuit may be designed to operate at or near the greatest operating speeds achievable by the process used to fabricate the integrated circuit, and, as such, even small imperfections in the effective duty cycle of the clock may be of importance, and may degrade the performance of the serial link.

Referring toFIG. 2A, in some embodiments a system for reducing duty-cycle distortion in a serial data transmitter includes a duty cycle detection circuit210for detecting duty cycle errors in the clock embedded in the output serial data stream, a finite state machine215, and a duty cycle correction circuit220, discussed in further detail below. The duty cycle detection circuit may include a switched charge pump212, as illustrated inFIG. 2B. The switched charge pump212may have a ganged switch controlled by the input (connected to the output of the serial data transmitter) and be configured to charge a capacitor230with current from a first current source235when the output of the serial data transmitter (and, therefore, the switch) is in a first state, and to discharge the capacitor230through a second current source240when the output of the serial data transmitter (and, therefore, the switch) is in a second state. The output CKout(or “DQ” inFIGS. 1 and 3) of the serial data transmitter is the actual point of use, and it may be well suited as a point for detecting duty cycle distortion, because it may capture aggregate distortion from several mechanisms, and introduced at several different points, in the serial data transmitter.

A clocked comparator245(or “sampler”) may periodically compare the voltage on the capacitor to a reference voltage (and, e.g., output a one if the voltage on the capacitor exceeds the reference voltage or a zero if the voltage on the capacitor is less than the reference voltage). The finite state machine215may employ the resulting sequence of zeros and ones to send an appropriate duty cycle correction code to the duty cycle correction circuit220. The duty cycle correction code may be a command to the duty cycle correction circuit220(e.g., a number written to a register in the duty cycle correction circuit220) that causes the duty cycle correction circuit220to apply a specified duty cycle correction, as discussed in further detail below.

The system ofFIG. 2Amay face obstacles to effective implementation in serial data transmitters using high clock rates, because the input to charge-pump212toggles at the highest system clock rate. For example, if the first current source235and the second current source240are small, their fractional imbalance may be significant, and if they are large, it may be difficult to switch them at a high clock rate (and their power consumption may be excessive).

To address these challenges, a system like that illustrated inFIGS. 3A and 3Bmay be employed. In the embodiment ofFIG. 3A, a finite state machine310is configured to operate at any time in one of two modes, a duty cycle calibration and correction mode, and a normal operating mode. In normal operating mode, the multiplexer320is controlled (e.g., by the finite state machine310), to transmit data from the data input of the serial data transmitter (which in the embodiment ofFIG. 3Aincludes the serializer325, the OMUX120, the pre-driver amplifier130and the driver amplifier140).

In duty cycle calibration and correction mode the multiplexer320is instead controlled (e.g., by the finite state machine310), to transmit data from a pattern generator315to the data input of the serial data transmitter, and the finite state machine310controls the pattern generator315to generate a pattern like the lower waveform ofFIG. 3B, consisting of one or more sequences of bits, each of the sequences consisting of (i) an odd number of zeros followed by the same number of ones or (ii) an odd number of ones followed by the same number of zeros. As illustrated inFIG. 3B, if the duty cycle of the clock (the upper waveform ofFIG. 3B) differs from 50%, then, because the numbers of zeros and ones are equal and odd, the duty cycle of the pattern generated by the pattern generator315will also differ from 50%, as illustrated inFIG. 3B, in which the odd number is three. The waveform of the output, when the pattern ofFIG. 3Bis transmitted, is lower in frequency (by a factor of the odd number, i.e., by a factor of three for the example ofFIG. 3B) than the clock frequency; as a result it is less challenging for a switched charge pump in the duty cycle detection circuit210to operate at the frequency of the output, in this embodiment.

In some embodiments a system controller may periodically instruct the duty cycle detection and correction circuit (which, inFIG. 3A, includes the multiplexer320, the pattern generator315, the duty cycle detection circuit210, the finite state machine310, and the duty cycle correction circuit220) to operate in duty cycle calibration and correction mode, e.g., by setting the select input of the multiplexer320so that the multiplexer320transmits the pattern generated by the pattern generator315to the input of the serial data transmitter, and asserting an enable input of the finite state machine310. The system controller may arrange for operation in duty cycle calibration and correction mode upon startup and initialization of the system of which the serial data transmitter is an element. In a display the system controller may also, or instead, arrange for operation in duty cycle calibration and correction mode during a horizontal blanking period at the end of each displayed line or during a vertical blanking period at the end of each frame.

The system controller may be a simple state machine, within the finite state machine310or separate from the finite state machine310, or the system controller may be a more complex processor (e.g., a stored-program computer) on the same integrated circuit as the serial data transmitter or on a separate integrated circuit. The finite state machine310may include a counter configured to count up when a bit received from the duty cycle detection circuit210has a first value, and to count down when a bit received from the duty cycle detection circuit210has a second value, different from the first value. The first value may be a binary one and the second value may be a binary zero, or vice versa. The output of the counter may be the duty cycle correction code sent to the duty cycle correction circuit220; if the counter reaches a large positive (or negative) value, it may be an indication that the current duty cycle differs significantly from 50% and that therefore a significant change, to be produced by the duty cycle correction circuit220, is appropriate.

The system ofFIG. 3Amay operate with two clock domains, one being the clock domain of the clock source (which may, for example, operate at a frequency greater than 1 GHz, e.g., at 5 GHz), and a second clock domain including circuits in the finite state machine310, the pattern generator315, and the duty cycle correction circuit220(except for the path that the clock signal from the clock source110takes through the duty cycle correction circuit220). The second clock domain may use a significantly lower clock (e.g., with a frequency between 0.1 MHz and 100.0 MHz) which may be derived from (e.g., using a phase locked loop or frequency divider) the signal from the clock source110, or independently generated (e.g., by an independent oscillator).

The duty cycle correction circuit220may include a chain of inverters (configured to switch at the frequency of the signal from the clock source110) and a control circuit (which is part of the second clock domain) that adjusts the asymmetry of the inverters, in accordance with the duty cycle correction code that the duty cycle correction circuit220receives from the finite state machine310. Each inverter may, for example, have a programmable pull-up strength or a programmable pull-down strength (or both). The pull-up strength may be made programmable, for example, by arranging for the inverter to include a plurality of pull-up transistors, each connected in series with a respective enabling transistor (the enabling transistors being switched on or off in accordance with the duty cycle correction code). The pull-down strength may be made programmable in an analogous manner.

In some embodiments, the effects of sources of error in the duty cycle detection and correction circuit are suppressed by first configuring the pattern generator315to generate a first pattern, and calculating a first duty cycle correction code based on the first pattern, and then generating a second pattern, the second pattern being the exact inverse of the first pattern (e.g., the second pattern having a zero wherever the first pattern has a one and the second pattern having a one wherever the first pattern has a zero) and calculating a second duty cycle correction code based on the second pattern. A third duty cycle correction code, calculated as the average of the first duty cycle correction code and the second duty cycle correction code, may then be fed to the duty cycle correction circuit220.

In some embodiments the number of zeros (and ones) of the sequences produced by the pattern generator may vary with time, to distribute the spectral content of this signal into a larger number of narrowband spectral components. For example, the pattern generator315may include a 4-bit pseudorandom number generator (using, e.g., a 4-bit linear feedback shift register), the output of which, for each sequence to be produced, may be right-shifted by one, and then decremented by one to generate an odd number to be used in generating the sequence.

Referring toFIG. 4, in one embodiment a display405contains a timing controller410configured to send high-speed digital data to a driver integrated circuit (driver IC)415, over a serial data link420. The timing controller410includes a serial data transmitter, at the transmitting end of the serial data link420, constructed according to an embodiment of the present invention to mitigate the effects of duty cycle distortion.

Although exemplary embodiments of a method and apparatus for duty-cycle correction of high speed I/O have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it is to be understood that a method and apparatus for duty-cycle correction of high speed I/O constructed according to principles of this invention may be embodied other than as specifically described herein. The invention is also defined in the following claims, and equivalents thereof.