Compensation for parasitic capacitance of a capacitive sensor

An apparatus for converting a capacitance measured on a capacitive sensor to a digital code may include a modulation capacitor to receive charge transferred from the sensor and compensation circuitry to divert charge from the modulation capacitor. A method for operating the apparatus may include generating a digital bitstream based on the capacitance of the sensor and compensating for a parasitic capacitance of the capacitive sensor.

TECHNICAL FIELD

This disclosure relates to the field of user interface devices and, in particular, to capacitive sensor devices.

BACKGROUND

In general, capacitive sensors are intended to replace mechanical buttons, knobs, and other similar mechanical user interface controls. Capacitive sensors allow the elimination of such complicated mechanical controls and provide reliable operation under harsh conditions. Capacitive sensors are also widely used in modern customer applications, providing new user interface options in existing products.

Capacitive sensing systems generally operate by detecting a change in the capacitance of a capacitive sensor resulting from proximity or contact of an object with the sensor. The ability to resolve changes in capacitance may be impaired if the changes in capacitance to be detected by the sensor are small relative to the capacitance of the sensor.

For instance, a capacitive sensor that is configured to detect an input, such as proximity or contact with a finger or other object, may have a capacitance CPwhen no input is present. The capacitance CPis known as the parasitic capacitance of the sensor. An input detected by the sensor may cause a change in capacitance CFthat is much smaller than CP. Accordingly, the parasitic capacitance CPis represented by a larger proportion of the discrete capacitance levels resolvable by the bitstream, while the capacitance change CFis represented by fewer of these discrete levels. In such cases, the capacitance change CFdue to an input may not be resolvable to a high degree of resolution.

DETAILED DESCRIPTION

Embodiments of a method and apparatus for converting a capacitance measured on a capacitive sensor element to a digital code are described. In one embodiment, such a capacitance to code converter includes capacitance sensing circuitry that measures changes in the capacitance CSof the capacitive sensor and generates a digital bitstream based on the measured capacitance CS. Changes in the capacitance CSof the capacitive sensor may be caused by inputs, such as a finger or other object in proximity or in contact with the capacitive sensor. These changes are reflected in the bitstream, which can be processed by a computer system or other circuit.

In one embodiment, the capacitance sensing circuitry converts the sensor capacitance CSto a code, or bitstream, by alternately charging the sensor capacitor and transferring charge from the sensor capacitor to a modulation capacitor. Over a number of iterations, the charge stored in the modulation capacitor increases, corresponding to an increase in the voltage level VNof the modulation capacitor. The voltage level VNof the modulation capacitor is compared with a reference voltage VREF. In one embodiment, a bit is asserted on the output bitstream when the modulation capacitor voltage VNreaches VREF.

Since the amount of charge that can be stored over a given time period by the sensor capacitor changes with the capacitance of the sensor capacitor, the amount of charge transferred to the modulation capacitor from the sensor capacitor also changes accordingly. Thus, when the capacitance of the sensor capacitor increases, more charge is stored over time in the modulation capacitor, and the modulation capacitor voltage rises to the reference voltage more quickly. Accordingly, the density of bits asserted on the output bitstream increases with the capacitance CSof the sensor.

In cases where the capacitance change CFdue to the input is much smaller than the capacitance CPof the sensor when no input is present, the change in the bit density due to CFis correspondingly smaller. However, in one embodiment, charge accumulating on the sensor capacitor attributable to CPcan be diverted away from the modulation capacitor using compensation circuitry. This decreases the density of bits corresponding to no input. In conjunction, the dynamic range of the output bitstream can also be increased so that an input corresponds to a higher bit density. This results in a higher resolution of the capacitance range over which change due to an input is likely to occur.

FIG. 1illustrates a block diagram of one embodiment of an electronic system in which a capacitance to code converter with parasitic compensation circuitry can be implemented. Electronic system100includes processing device110, touch-sensor pad120, touch-sensor slider130, touch-sensor buttons140, host processor150, embedded controller160, and non-capacitance sensor elements170. The processing device110may include analog and/or digital general purpose input/output (“GPIO”) ports107. GPIO ports107may be programmable. GPIO ports107may be coupled to a Programmable Interconnect and Logic (“PIL”), which acts as an interconnect between GPIO ports107and a digital block array of the processing device110(not illustrated). The digital block array may be configured to implement a variety of digital logic circuits (e.g., DACs, digital filters, or digital control systems) using, in one embodiment, configurable user modules (“UMs”). The digital block array may be coupled to a system bus. Processing device110may also include memory, such as random access memory (RAM)105and program flash104. RAM105may be static RAM (SRAM), and program flash104may be a non-volatile storage, which may be used to store firmware (e.g., control algorithms executable by processing core102to implement operations described herein). Processing device110may also include a memory controller unit (MCU)103coupled to memory and the processing core102.

The processing device110may also include an analog block array (not illustrated). The analog block array is also coupled to the system bus. Analog block array also may be configured to implement a variety of analog circuits (e.g., ADCs or analog filters) using, in one embodiment, configurable UMs. The analog block array may also be coupled to the GPIO107.

As illustrated, capacitance sensing circuit101may be integrated into processing device110. Capacitance sensing circuit101may include analog I/O for coupling to an external component, such as touch-sensor pad120, touch-sensor slider130, touch-sensor buttons140, and/or other devices. Capacitance sensing circuit101and processing device102are described in more detail below.

The embodiments described herein are not limited to touch-sensor pads for notebook implementations, but can be used in other capacitive sensing implementations, for example, the sensing device may be a touch screen, a touch-sensor slider130, or touch-sensor buttons140(e.g., capacitance sensing buttons). In one embodiment, these sensing devices may include one or more capacitive sensors. It should also be noted that the embodiments described herein may be implemented in other sensing technologies than capacitive sensing, such as resistive, optical imaging, surface wave, infrared, dispersive signal, and strain gauge technologies. Similarly, the operations described herein are not limited to notebook pointer operations, but can include other operations, such as lighting control (dimmer), volume control, graphic equalizer control, speed control, or other control operations requiring gradual or discrete adjustments. It should also be noted that these embodiments of capacitive sensing implementations may be used in conjunction with non-capacitive sensing elements, including but not limited to pick buttons, sliders (ex. display brightness and contrast), scroll-wheels, multi-media control (ex. volume, track advance, etc) handwriting recognition and numeric keypad operation.

In one embodiment, the electronic system100includes a touch-sensor pad120coupled to the processing device110via bus121. Touch-sensor pad120may include a multi-dimension sensor array. The multi-dimension sensor array includes multiple sensor elements, organized as rows and columns. In another embodiment, the electronic system100includes a touch-sensor slider130coupled to the processing device110via bus131. Touch-sensor slider130may include a single-dimension sensor array. The single-dimension sensor array includes multiple sensor elements, organized as rows, or alternatively, as columns. In another embodiment, the electronic system100includes touch-sensor buttons140coupled to the processing device110via bus141. Touch-sensor buttons140may include a single-dimension or multi-dimension sensor array. The single- or multi-dimension sensor array may include multiple sensor elements. For a touch-sensor button, the sensor elements may be coupled together to detect a presence of a conductive object over the entire surface of the sensing device. Alternatively, the touch-sensor buttons140may have a single sensor element to detect the presence of the conductive object. In one embodiment, touch-sensor buttons140may include a capacitive sensor element. Capacitive sensor elements may be used as non-contact sensor elements. These sensor elements, when protected by an insulating layer, offer resistance to severe environments.

The electronic system100may include any combination of one or more of the touch-sensor pad120, touch-sensor slider130, and/or touch-sensor button140. In another embodiment, the electronic system100may also include non-capacitance sensor elements170coupled to the processing device110via bus171. The non-capacitance sensor elements170may include buttons, light emitting diodes (LEDs), and other user interface devices, such as a mouse, a keyboard, or other functional keys that do not require capacitance sensing. In one embodiment, buses171,141,131, and121may be a single bus. Alternatively, these buses may be configured into any combination of one or more separate buses.

Processing device110may include internal oscillator/clocks106and communication block108. The oscillator/clocks block106provides clock signals to one or more of the components of processing device110. Communication block108may be used to communicate with an external component, such as a host processor150, via host interface (I/F) line151. Alternatively, processing block110may also be coupled to embedded controller160to communicate with the external components, such as host150. In one embodiment, the processing device110is configured to communicate with the embedded controller160or the host150to send and/or receive data.

Processing device110may reside on a common carrier substrate such as, for example, an integrated circuit (IC) die substrate, a multi-chip module substrate, or the like. Alternatively, the components of processing device110may be one or more separate integrated circuits and/or discrete components. In one exemplary embodiment, processing device110may be a Programmable System on a Chip (PSoC™) processing device, manufactured by Cypress Semiconductor Corporation, San Jose, Calif. Alternatively, processing device110may be one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit, a controller, special-purpose processor, digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like.

It should also be noted that the embodiments described herein are not limited to having a configuration of a processing device coupled to a host, but may include a system that measures the capacitance on the sensing device and sends the raw data to a host computer where it is analyzed by an application. In effect the processing that is done by processing device110may also be done in the host.

Capacitance sensing circuit101may be integrated into the IC of the processing device110, or alternatively, in a separate IC. Alternatively, descriptions of capacitance sensing circuit101may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing capacitance sensing circuit101, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.). Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe capacitance sensing circuit101.

It should be noted that the components of electronic system100may include all the components described above. Alternatively, electronic system100may include only some of the components described above.

In one embodiment, electronic system100may be used in a notebook computer. Alternatively, the electronic device may be used in other applications, such as a mobile handset, a personal data assistant (PDA), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld video player, a handheld gaming device, or a control panel.

FIG. 2illustrates in detail a capacitance sensing circuit that can be used in electronic system100, according to one embodiment of the invention. Capacitance sensing circuit200includes a capacitive sensor210having a capacitance of CSthat is represented by capacitor212(having capacitance CP) and capacitor213(having capacitance CF). Capacitive sensor210is connected to switch211, which can be connected to either VDDor node231. Switch211and capacitive sensor210can be represented as equivalent resistance215, having a value of RC. The value RCof equivalent resistance215is equal to 1/(fCS), where f is the switching frequency of switch211. Node231is connected to modulation capacitor230, having a capacitance CMOD. Modulation capacitor230is connected to discharge resistor242, having a resistance RB, and switch241, which is controlled by the voltage VMODat output node240. Node231is also connected to an input of comparator250. A reference voltage VREFis connected to another input of comparator250. An output of comparator250is connected to latch251, which is enabled by frequency divider252. Frequency divider252divides a signal from internal main oscillator253. The output of latch251is connected to output node240. Capacitance sensing circuit200also includes compensation circuitry260, which further includes resistor261(having a value RA), switch262, and pulse width modulator (PWM)263. Compensation circuitry260is connected to node231.

Capacitance sensing circuit200measures the capacitance CSof capacitive sensor210using sigma-delta modulation. Specifically, sensing circuit200alternately charges capacitive sensor210and transfers charge from sensor210to modulation capacitor230. Circuit200further asserts a bit on an output bitstream when the voltage VNat node231reaches a reference voltage VREF. The density of bits, which is the number of asserted bits over time on the bitstream at output node240, corresponds to the capacitance CSof the capacitive sensor210.

Capacitance sensing circuit200charges capacitive sensor210by connecting the sensor210to a positive voltage VDDusing switch211. This results in a potential difference across the terminals of the sensor210, which charges the sensor210.

Circuit200transfers charge stored on sensor210to modulation capacitor230by connecting sensor210to node231using switch211. Since the voltage VSon capacitive sensor210is higher than the voltage VNat node231, current flows from capacitive sensor210into node231, charging the modulation capacitor230. In one embodiment, the capacitance CMODof the modulation capacitor230is much greater than the capacitance CSof sensor210, so that the voltage increase at node231is small.

Circuit200may then repeat this process of charging sensor210and discharging sensor210into node231to build up charge stored on the modulation capacitor230over a number of cycles. This causes an increase in the voltage VNat node231over time.

Node231is connected to an input of comparator250, while the other input of comparator250is connected to a reference voltage VREF. Comparator250thus compares the voltage VNat node231with the reference voltage VREFand asserts its output when VNreaches VREF. The output of comparator is connected to latch251.

Latch251is used to synchronize the output bitstream of the capacitance sensing circuit200to a clock signal. The latch251is enabled according to a frequency divider252, which divides a frequency signal provided by internal main oscillator253. The output of comparator250is latched to the output node240according to the frequency provided by frequency divider252. Thus, the digital bitstream generated at the output node240has a base period and frequency determined by the frequency divider252.

The voltage VMODat output node240is also used to operate switch241. When switch241is open, the modulation capacitor is charged from capacitive sensor210, as previously described. When the voltage level VNof modulation capacitor230reaches VREF, the comparator250asserts its output and, through latch251, causes the output node240to also be asserted, closing switch241. When switch241is closed, the charge stored on modulation capacitor230is discharged through an impedance RB242.

Switch241reopens when modulation capacitor230has discharged enough so that the voltage VNat node231no longer exceeds VREF. This reopening of switch241may be delayed by operation of the latch251, which synchronizes the output operating switch241to a clock signal according to frequency divider252. With switch241open, the modulation capacitor230continues storing charge transferred from capacitive sensor210in the next charge transfer cycle.

For each period during which switch241is open, the voltage VNat node231increases at a rate that depends on the capacitance CSof capacitive sensor210. When CSis higher, more charge is stored in CSfor each cycle of switch211. Thus, more charge is transferred to modulation capacitor230when sensor210is connected to modulation capacitor230by switch211. Since the charge accumulates more quickly on modulation capacitor230, the voltage VNalso reaches VREFmore quickly. Accordingly, the comparator250asserts its output more frequently and the bit density of the output bitstream at output node240increases. The density of bits in the output bitstream thus corresponds to the capacitance CSof the capacitive sensor210.

In cases where the capacitance change CFdue to the input is much smaller than the capacitance CPof the sensor when no input is present, the change in the bit density due to CFis correspondingly smaller. However, in one embodiment, charge accumulating on the sensor capacitor attributable to CPcan be diverted away from the modulation capacitor using compensation circuitry.

In one embodiment, the compensation circuitry260includes an impedance, such as a resistor261(having a value RA) that is connected to node231. During the operation of capacitance sensing circuit200, as described above, resistor261diverts charge away from node231that would otherwise continue to be stored in modulation capacitor230. In one embodiment the value RAof resistor261is chosen so that resistor RAdiverts all or most of the charge attributable to the parasitic capacitance of sensor210. The charge attributable to the parasitic capacitance is the amount of charge that would be transferred from capacitive sensor210if no input were present.

The flow of charge attributable to the parasitic capacitance can also be considered as a parasitic current IPflowing into node231. Thus, RAcan be chosen so that the current IAflowing out of node231through resistor261is approximately equal to IP. This minimizes the accumulation of charge over time on the modulation capacitor230, thereby increasing the time for the voltage VNat node231to reach VREF. Due to this increase in rise time, the comparator250asserts its output less frequently and fewer bits are asserted in the output bitstream, as compared to when compensation circuitry260is not used. By reducing the offset due to the parasitic capacitance, compensation circuitry260allows the use of a higher value for resistor242to optimize the dynamic range of the capacitance sensing circuit200.

In one embodiment, resistor261is connected directly to ground. In an alternative embodiment, resistor261is connected to ground through switch262, which is controlled by pulse width modulator (PWM)263. The PWM263can be used to control switch262to adjust the equivalent resistance of compensation circuitry260. Particularly, the equivalent resistance of compensation circuitry260decreases with an increase in the proportion of time that resistor260is switched to ground by the PWM263. PWM263can thus be programmed to select an equivalent resistance that balances the compensation current IAand the parasitic current IP. For example, PWM263can be used to compensate for different parasitic capacitances between different capacitive sensors.

In a capacitance sensing circuit200that compensates for the offset from parasitic capacitance CP, the dynamic range of the circuit200can also be improved by adjusting an impedance, such as resistor242having a value RB, through which the modulation capacitor230is discharged. Specifically, the resolution of the circuit200is proportional to RB, and a higher value of RBcan be used when the parasitic capacitance is compensated using compensation circuitry260.

In one embodiment where resistor261is always connected to ground, a calculation of a value for RAthat will minimize the offset due to parasitic capacitance CPbegins with equations 1 and 2 below. In equations 1 and 2, dmodis the density of bits in the output bitstream, CSis the capacitance of sensor210, fSis the switching frequency of switch211, RBis the value of resistor242, kdis the ratio of VREF/VDD, CFis a change in capacitance resulting from an input to sensor210, and CPis the parasitic capacitance.

dmod=CF⁢fS⁢RB⁡(1kd-1)+CP⁢fS⁢RB⁡(1kd-1)-RBRA(3)
Equation 4 below can then be used to determine the resistance RAof resistor261so that dmodis as close as possible to 0 when CFis equal to 0:

Equation 4 further shows that adjusting kd, which is the ratio between voltages VREFand VDD, could also be used to trim for differences in parasitic capacitance between individual sensors.

In one embodiment, variations in parasitic capacitances between different sensors is compensated by using PWM263to switch resistor261to ground. The current flowing through resistor261is proportional to the duty cycle of switch262, so different duty cycle settings can be used for different sensors to obtain a dmodvalue for each of the different sensors that is as close as possible to 0 when no input is present.

In an alternative embodiment, a pseudo-random sequence generator is used to control switch262, instead of pulse width modulation.

FIG. 3illustrates a capacitance sensing circuit300using compensation circuitry that includes a current digital to analog converter (IDAC) according to one embodiment. Capacitance sensing circuit300includes an equivalent resistance215having a value of RC, which represents a capacitive sensor having a capacitance CSand a switch, which can be connected to either VDDor node231. Node231is connected to modulation capacitor230, having a capacitance CMOD. Modulation capacitor230is connected to discharge resistor242, having a resistance RB, and switch241, which is controlled by the voltage VMODat output node240. Node231is also connected to an input of comparator250. A reference voltage VREFis connected to another input of comparator250. An output of comparator250is connected to latch251, which is enabled by frequency divider252. Frequency divider252divides a signal from internal main oscillator253. The output of latch251is connected to output node240. Capacitance sensing circuit200also includes compensation circuitry360, which further includes a current digital to analog converter (IDAC)363and a resistor261having a resistance RA. Compensation circuitry360is connected to node231.

Capacitance sensing circuit300operates in similar fashion as capacitance sensing circuit200, previously described inFIG. 2above. In circuit300, resistor261similarly diverts charge from node231to compensate for parasitic capacitance CPof the capacitive sensor.

Circuit300further includes an IDAC363that is used to compensate for variations in parasitic capacitance between different capacitive sensors. For example, a value of RAmay be chosen based on a maximum expected parasitic capacitance CPmax. Thus, for a particular capacitive sensor with a parasitic capacitance that is less than CPmax, IDAC363can be programmed to supply a current into node231to compensate for the difference in parasitic capacitance.

Equation 5 below relates the currents flowing into and out of node231. ICis the current flowing through equivalent resistance215, IDis the current supplied by the IDAC363, IAis the current flowing through resistor261, and IBis the current flowing through resistor242.
IC+ID=IA+IB(5)

Assuming that ICremains unchanged, RAcan be selected for a desired baseline value of IA. For example, IBmay be minimized by selecting RAso that IAis approximately equal to ICwhen CSis equal to CPmax. The IDAC363can be programmed to provide a current IDso that IBis equal to 0 when no input is present at the capacitive sensor (for CP<CPmax). Resistor261with resistance RAand IDAC363supplying current IDthus remove an amount of current flowing into node231that is attributable to the parasitic capacitance.

FIG. 4illustrates a capacitance sensing circuit having compensation circuitry that includes an IDAC, according to one embodiment. Capacitance sensing circuit400includes a capacitive sensor410having a capacitance of CSthat is represented by capacitor412(having capacitance CP) and capacitor413(having capacitance CF). Capacitive sensor410is connected to switch411, which can be connected to either ground or node431. Switch411and capacitive sensor410can be represented as equivalent resistance415, having a value of RC. Node431is connected to modulation capacitor430, having a capacitance CMOD. Modulation capacitor430is connected to discharge resistor442, having a resistance RB, and switch441, which is controlled by the voltage VMODat output node440. Node431is also connected to an input of comparator450. A reference voltage VREFis connected to another input of comparator450. An output of comparator450is connected to latch451. The output of latch451is connected to output node440. Capacitance sensing circuit400also includes compensation circuitry460, which further includes IDAC463. Compensation circuitry460is connected to node431.

Capacitance sensing circuit400embodies an alternate configuration where positive charge is removed from modulation capacitor430by the capacitive sensor410through periodic cycling of switch411.

Specifically, modulation capacitor430is charged through resistor442when switch441is closed. This raises the voltage VNat node431. The positive charge stored in modulation capacitor430is transferred to capacitive sensor410when switch411connects sensor410to node431. The sensor410is then discharged to ground through switch411.

When the capacitance CSof the sensor410increases due to an input, the sensor410removes more charge over time from modulation capacitor430. Thus, the voltage VNat node431falls more quickly to the reference voltage VREF. When VNfalls below VREF, the comparator450deasserts its output high. The output of comparator450is latched through latch451and a bit is asserted in the bitstream at output node440.

The voltage at output node440controls switch441, so that when the bit is generated at the output bitstream, switch441charges modulation capacitor430through resistor442.

In circuit400, the parasitic capacitance CPof the sensor410is compensated using IDAC463, which supplies a current IDinto node431. IDis related to the current ICflowing through the equivalent resistance415of the sensor capacitor and the current IBflowing through resistor442by the equation 6 below, where all currents are flowing into node231.
IC+IDIB=0  (6)
In accord with equation 6, the IDAC463can be programmed to supply a current IDthat is approximately equal to −ICwhen no input is present. Thus, IBwill be approximately 0 when no input is present.

Since IDAC463is programmable, the IDAC current IDcan be adjusted to compensate for varying parasitic capacitances. In one embodiment, an iterative successive approximation method is used to determine a value for IDthat minimizes IBfor a particular sensor.

FIG. 5illustrates a capacitance sensing circuit that compensates for parasitic capacitance of a sensor using a switched capacitor, according to one embodiment. Capacitance sensing circuit500includes a capacitive sensor510having a capacitance of CS. The capacitance CSincludes a parasitic capacitance CPand an input capacitance CF. Capacitive sensor510is connected to switches511and512. Switch511is connected to supply voltage VDD, and switch512is connected to node531. Switches511and512and capacitive sensor210can be represented as equivalent resistance515, having a value of RC. Node531has a voltage VNand is connected to modulation capacitor230, having a capacitance CMOD. Modulation capacitor230is connected to discharge capacitor542, having a capacitance of CB, through switch544. Capacitor542is further connected to multiplexor (mux)545through switch543. Multiplexor545is controlled by the voltage VMODat output node240to connect switch543with either VDDor ground. Node231is also connected to an input of comparator250. A reference voltage VREFis connected to another input of comparator250. An output of comparator250is connected to latch251. The output of latch251is connected to output node240. Capacitance sensing circuit500also includes compensation circuitry560, which further includes capacitor561, and switches562and563. Compensation circuitry560is connected to node531.

Capacitance sensing circuit500operates in similar fashion as capacitance sensing circuit200as described with reference toFIG. 2above, except that resistor242is replaced with circuitry including capacitor542and switches543and544, and switch241is replaced by multiplexor545. Furthermore, compensation circuitry260is replaced in circuit500with compensation circuitry560, which diverts charge from node531by alternately charging and discharging compensation capacitor561through switches562and563.

More specifically, compensation circuitry560diverts charge from node531by operating switches562and563in a non-overlapping manner so that compensation capacitor561is repeatedly charged from node531and discharged to ground. For example, when switch563is closed, switch562is open and charge is transferred from modulation capacitor230to compensation capacitor561.

Since switches562and563operate in a non-overlapping manner, switches562and563are not simultaneously closed for any duration of time. Instead, switch563opens before switch562is closed to connect the compensation capacitor561to ground. When switch562closes, compensation capacitor561is discharged to ground.

Thus, over repeated cycling of switches562and563, a current IDdiverts charge from modulation capacitor230. A desired current IDcan be chosen by selecting the capacitance CDof compensation capacitor561and by selecting an appropriate frequency and duty cycle for switching the switches562and563.

In one embodiment where compensation circuitry560includes a switched compensation capacitor561, the current IDscales proportionally with changes in VDD. This reduces the effect of changes in VDDon the output bitstream of circuit500.

Instead of a resistor242having a value RBand a switch241(as described with reference toFIG. 2), a capacitor542having a value CBis used in conjunction with switches543and544and multiplexor545to configure the sensitivity, or resolution, of the capacitance sensing circuit500.

When voltage VNat node531exceeds VREF, a high bit is generated at output node240. The voltage at node240is used to control multiplexor545so that when a high bit is asserted at node240, the multiplexor545connects switch543to ground.

When switch543is connected to ground, switches543and544operate in a non-overlapping manner to alternately charge capacitor542from node531and discharge capacitor542to ground through multiplexor545. Over time, the operation of switches543and544results in charge flowing out of node531, represented by a current IB, that discharges the modulation capacitor230. The voltage VNat node531therefore decreases until it falls below VREF, which causes output node240to be deasserted low.

When output node240is low, the multiplexor545connects switch543to VDD. The operation of switches543and544then alternately charges capacitor542to VDDand then discharges capacitor542to VN. This causes the voltage VNto rise towards reference voltage VREF.

In an alternate embodiment, the multiplexor545is not used, and switch543is connected directly to ground. The voltage at output node240is used to gate an output of a clock signal that controls one or both of switches543and544. According to this arrangement, the modulation capacitor230is only discharged through capacitor542(due to operation of switches543and544) when the voltage VNat node531has exceeded VREFand caused a bit to be asserted high at output node240.

Assuming all switches511,512,543,544,562, and563are controlled by the same clock source with frequency f and assuming further that VREFis VDD/2, the currents IB, IS, and IDcan be described using equations 7, 8, and 9, respectively:

Equations 7, 8, and 9 can be substituted into equation 10, simplified to equation 11, and further reduced to equation 12, which relates capacitances CB, CS, and CD, as follows:
IB+IS+ID=0  (10)

The capacitance CSof sensor510is the sum of the parasitic capacitance CPand the input capacitance CF, as expressed in equation 13 below.
CS=CP+CF(13)
Substituting equation 13 into equation 12 yields equation 14 below:

In one embodiment, the dynamic range of the capacitance sensing circuit500is theoretically optimized when the density of bits in the output bitstream dmodis 1 when the capacitance CFdue to an input is equal to the maximum expected value CFmax. In addition, the bit density dmodshould be 0 when CFis equal to 0, such as when no input is present.

Thus, for the case where an input detected at the sensor510, equation 14 substitutes 1 in place of dmodin equation 14, yielding equation 15 below, which further reduces to equations 16 and 17.

For the case where no input is detected at sensor510, equation 14 substitutes 0 in place of dmodin equation 13, yielding equation 18 below, which further reduces to equations 19 and 20.

Combining equations 17 and 20 yields equations 21 and 22, which express CBand CDin terms of the parasitic capacitance CPand the maximum expected increase in capacitance CFmaxdue to an input at sensor510.

In one embodiment, CBcan be selected based on the highest CFthat is to be measured, and CDcan be determined using successive approximation. In practice, determining CDusing successive approximation may result in a value for CDthat differs from the theoretically ideal capacitance value by an amount CDoff.

Inserting the values CB, CD, and CDoffinto the current summing equation for node531(equation 14) results in equation 23, which reduces to equations 24 and 25.

In accord with equation 24 above, the capacitance CF, by which an input increases the capacitance of the sensor CS, is directly proportional to the density of bits dmodoutput by the capacitance sensing circuit500, although with an offset represented by CDoff.

This offset can be minimized to maximize the dynamic range and sensitivity of circuit500. In one embodiment, minimization of the offset is accomplished by trimming capacitance CDof compensation capacitor561. In addition, the offset can be further compensated using software baselining methods.

In one embodiment, trimming of the currents IBand IDcan be accomplished using programmable capacitors. For example, capacitors542and561may be programmable so that capacitance values CBand CDare adjustable. Alternatively, the IBand IDcurrents can be trimmed by adjusting the switching characteristics of switches543,544,562, and563. For example, the frequency of the switching can be adjusted to trim the currents. In one embodiment, the switches are independently configurable so that the currents IBand IDcan be trimmed separately.

FIG. 6Ais a graph illustrating a relationship between measured capacitance of a sensor and count values of bits in an output bitstream, according to one embodiment. Specifically,FIG. 6Aillustrates the relationship between count values and sensor capacitance when the parasitic capacitance of the sensor is not compensated.

When the output bitstream is generated by a capacitance sensing circuit, as previously described, the asserted bits in the bitstream are counted. The number of asserted bits corresponds to a measured capacitance value of the sensor. InFIG. 6A, the horizontal axis includes count values from 0 to 65536, while the vertical axis includes a range of possible measured capacitances of the capacitive sensor.

The parasitic capacitance is represented inFIG. 6Aas capacitance CP610, which has a value of approximately 9.5 pF. Since the parasitic capacitance is not compensated, the count value does not fall below approximately 31,100 counts, which corresponds to the capacitance CP610.

Furthermore, the input capacitance CF620, which is a change in capacitance due to an input at the capacitive sensor, is much smaller than CP610. input capacitance CFis approximately 1 pF. A sensor capacitance CSthat is measured while an input is present at the sensor includes input capacitance CF620so that CSis equal to CP+CF. This value of CS(about 10.5 pF) corresponds to a count value of approximately 34,400 counts.

Thus, during the normal course of operation of the capacitance sensing circuit, the count value stays within dynamic range 650, which spans approximately 3,300 counts. Accordingly, the capacitance sensing circuit is able to resolve the change in capacitance CFdue to an input to only about 3,300 levels.

FIG. 6Bis a graph illustrating a relationship between count values and sensor capacitance. This relationship is associated with a capacitance sensing circuit in which the parasitic capacitance of the sensor is not compensated. As compared with the capacitance sensing circuit ofFIG. 6A, the capacitance sensing circuit ofFIG. 6Bincludes a capacitive sensor having a higher value of CP630. Parasitic capacitance CP630is approximately 16.3 pF.

Input capacitance CF640is about 1 pF. When an input is present at the capacitive sensor, the sensor capacitance CSincreases from CPto CP+CF(about 17.3 pF). Accordingly, the count value generated by the capacitance sensing circuit rises from approximately 53,300 counts to approximately 56,600 counts. The dynamic range 660, similar to the dynamic range 650 ofFIG. 6A, is also about 3,300 counts. Accordingly, the input capacitance of 1 pF is resolvable to about 3,300 levels.

FIG. 7is a graph illustrating a relationship between count values and sensor capacitance. This relationship is associated with a capacitance sensing circuit in which the parasitic capacitance of the sensor is compensated using compensation circuitry.

According toFIG. 7, the parasitic capacitance CP710of the sensor is approximately 9.4 pF and the input capacitance CFis approximately 1 pF. Notably, only a portion of the parasitic capacitance CP710that is not compensated is visible in the graph inFIG. 7. Thus, the sensor capacitance CSwhen an input is present is CP+CF, which is approximately 10.4 pF.

Since the capacitance sensing circuit compensates for the parasitic capacitance710, the dynamic range 750 of the capacitance sensing circuit that corresponds to input capacitance CFcan be increased to approximately 33,000 counts. The increase may be effected, for example, by selecting an appropriate value RBof discharge resistor242to increase the gain of the capacitance sensing circuit. Thus, the input capacitance CFis resolvable to approximately 33,000 levels.

When the parasitic capacitance CP710of 9.4 pF is compensated using compensation circuitry, the capacitance sensing circuit outputs a count value of approximately 14,200 when CSis equal to CP. When an input is present, CSis equal to CP+CF, which is about 10.4 pF. The corresponding count value output by the sensing circuit is about 47,200. The total range of count values from 0-65536 corresponds to a capacitance range of 9-11 pF.

In an alternative embodiment, instead of increasing the resolution of the input capacitance CF, the compensation of parasitic capacitance CPallows for a faster scan time. For example, instead of a 16-bit count value, the sensor capacitance can be represented using fewer bits, such as 8-bits. Since the fewer bits are being transmitted through the output bitstream, the sampling of the bits takes less time. Holding other factors constant, such as base period and frequency, the 8-bit count value allows a scan time that is less than for the 16-bit count value.

In one embodiment, the dynamic range of the capacitance sensing circuit can be calibrated at various times. For example, the calibration may occur during an initialization of the circuit, or periodically during the operation of the circuit. In one embodiment, calibration may also be initiated by an external input, such as an input from a user or a separate electronic module. Calibration may also be performed upon detecting that the dynamic range of the capacitance sensing circuit does not correspond to a desired range of capacitance values.

In one embodiment, during the calibration process, the count values corresponding to particular sensor capacitance values are shifted. For example, the count value corresponding to a parasitic capacitance value CPmay be adjusted from 31,100 counts before calibration to 14,300 counts after calibration. This lowering of the count value corresponding to the parasitic capacitance is accomplished by adjusting the amount of charge diverted by the compensation circuitry.

For example, with reference toFIG. 2, the amount of charge diverted by compensation circuitry260can be selected by changing the frequency and duty cycle of the switching of switch262by PWM263. Thus, calibration can include programming of PWM263to operate switch262in a particular manner.

With reference toFIGS. 3 and 4, the amount of charge diverted by compensation circuitry360or compensation circuitry460can be selected by programming IDACs363or463, respectively. Thus, calibration of these sensing circuits300and400can include programming of IDAC363or463to supply particular currents into nodes231and431, respectively.

Calibration of the capacitance sensing circuit500illustrated inFIG. 5can include adjustment of the switching frequency of switches562and563to select a desired current IDrepresenting the amount of charge diverted from node531.

In addition to shifting of the dynamic range, the calibration process can also include scaling the dynamic range to increase the count values associated with particular capacitance values. In one embodiment, the dynamic range can be scaled so that the sensor capacitance CSwhen an input is present, which is equal to CP+CF, corresponds to a count value near the upper end of the range of available count values while the sensor capacitance CSwhen an input is not present (CS≈CP) is maintained at a count value near the lower end of the range of count values. For example, calibration may scale the dynamic range so that a 16-bit count value corresponding to the capacitance CP+CFchanges from 34,400 before calibration to 47,100 after calibration.

Scaling of the dynamic range can be accomplished by adjusting the impedance through which the modulation capacitor is discharged. For example, with reference toFIGS. 2 and 3, the value RBof resistor242can be selected to scale the dynamic range of sensing circuit200or300. With reference toFIG. 4, the value RBof resistor442can likewise be adjusted to scale the dynamic range of sensing circuit400.

With reference toFIG. 5, the dynamic range of sensing circuit500may be scaled by adjusting the switching frequency of switches543and544, or by adjusting the capacitance of capacitor542to select a desired current IB.

FIG. 8is a flow chart illustrating a process for sensing capacitance of a capacitive sensor, according to one embodiment. Capacitive sensing process800may be performed by a capacitance sensing circuit, such as capacitance sensing circuits200,300,400, or500. In alternative embodiments, the operations of capacitive sensing process800may be performed in a different sequence or in parallel.

At block802of capacitive sensing process800, the dynamic range of the capacitance sensing circuit is calibrated. This calibration may include adjusting the impedance through which the modulation capacitor is discharged, and may also include adjusting the amount of charge diverted from the modulation capacitor by the compensation circuitry, as previously described.

At block804, the capacitive sensor is charged. For example, with reference toFIG. 2, capacitive sensor210of capacitance sensing circuit200is charged by connecting the sensor210with VDDusing switch211. The sensor210is then charged by the potential difference between VDDand ground.

At block806, the charge stored on the capacitive sensor is transferred to the modulation capacitor of the sensing circuit. For example, in capacitance sensing circuit200, switch211connects the charged sensor capacitor210with the modulation capacitor230. If the sensor capacitor210has been charged to VDDor some other voltage higher than the voltage VNat node231, then charge is transferred from sensor capacitor210to modulation capacitor230.

At block808, charge is diverted from the modulation capacitor through compensation circuitry. The charge diverted from the modulation capacitor may be positive charge or negative charge. With reference toFIG. 2, compensation circuitry260of sensing circuit200diverts charge from modulation capacitor230through a current from node231to ground by operating switch262. The duty cycle of switch262and the resistance RAof resistor261determine the amount of charge that is diverted from modulation capacitor230.

In one embodiment where the compensation circuitry includes a resistor without a PWM-controlled switch, the value RAof the resistor determines the amount of charge diverted from the modulation capacitor.

Referring toFIG. 3, a capacitance sensing circuit300with compensation circuitry360that includes an IDAC363and a resistor261diverts charge according to block808by allowing a current to flow from node231to ground through resistor261. Capacitance sensing circuit300also additionally supplies current to node231using IDAC363to compensate for variations in parasitic capacitances between different sensors.

Referring toFIG. 4, capacitance sensing circuit400diverts negative charge away from modulation capacitor430in accord with block808by using compensation circuitry460, which includes IDAC463. IDAC463supplies a positive current to node431, thus removing the negative charge on modulation capacitor430.

Referring toFIG. 5, capacitance sensing circuit500diverts charge from modulation capacitor230according to block808through compensation circuitry560. The amount of charge diverted from the modulation capacitor230is determined by the capacitance of capacitor561. In one embodiment, the capacitor561is a programmable capacitor having a capacitance that is easily adjusted, for example, during a calibration process. Alternatively, the amount of charge diverted from the modulation capacitor230can be determined by the switching frequency of switches562and563.

In one embodiment, the amount of charge that is diverted is approximately an amount of charge that is attributable to the parasitic capacitance CPrepresented by capacitor212of capacitive sensor210. Alternatively, the amount of charge diverted may only be a portion of the charge attributable to the parasitic capacitance CP.

At block810, the voltage level VNof the modulation capacitor is compared with a reference voltage VREF. For example, VNand VREFmay be applied to the inputs of a comparator such as comparator250. If VNdoes not exceed VREF, the capacitive sensor is charged at block804. The operations of blocks804,806,808, and810are repeated until VNexceeds VREF.

At block810, if VNexceeds VREF, then a bit is asserted in the output bitstream in accord with block812and the modulation capacitor is discharged in accord with block814.

At block812, a bit is asserted in the output bitstream of the capacitance sensing circuit. In one embodiment, the output of comparator250is connected to a latch251, which is enabled according to a clock signal that determines the base frequency of the output bitstream. When the comparator250asserts its output, the latch responds by asserting a bit in the output bitstream produced at output node240.

At block814, the modulation capacitor is discharged. In one embodiment, a comparator250that is used to compare VNand VREFoutputs a signal that discharges the modulation capacitor by connecting it to ground through an impedance, such as resistor242, using a switch241. In an alternative embodiment, a signal indicating that VNexceeds VREFoperates a multiplexor, such as multiplexor545.

In another embodiment, a signal indicating that VNexceeds VREFgates a clock signal that controls switches, such as switches543and544, connected to a switched capacitor542. The gated clock signal causes the switches543and544to operate in a non-overlapping manner to alternately charge capacitor542from the modulation capacitor230and discharge capacitor542to ground, thus removing charge from the modulation capacitor230.

At block816, the process determines whether calibration of the capacitance sensing circuit is requested. In one embodiment, the calibration process is triggered periodically to maintain a desired dynamic range for the sensing circuit. In alternative embodiments, the calibration may occur only during initialization of the sensing circuit, or may occur in response to a request from an external source, such as a user.

If calibration is not requested, then calibration is not performed and the process continues with charging the capacitive sensor and transferring charge to the modulation capacitor according to blocks804,806,808, and810. If calibration is requested, then calibration can be performed according to block802as previously described.

As described above, the embodiments described herein describe a capacitance-to-code converter that allows continuous operation by providing a continuous output bitstream. Embodiments of the capacitance-to-code converter further compensate for parasitic capacitances of sensor capacitors to optimize dynamic range of the capacitance sensing circuitry.

The embodiments described herein may have the advantage of keeping all benefits of existing charge transfer/accumulation methods (especially in the high immunity for RF/EMI noise signals), and may be configured for easy implementation in existing devices from hardware and software perspectives, as well as in future devices.

Embodiments of the present invention, described herein, include various operations. These operations may be performed by hardware components, software, firmware, or a combination thereof. As used herein, the term “coupled to” may mean coupled directly or indirectly through one or more intervening components. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines and each of the single signal lines may alternatively be buses.

Certain embodiments may be implemented as a computer program product that may include instructions stored on a machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A machine-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). The machine-readable medium may include, but is not limited to, magnetic storage medium (e.g., floppy diskette); optical storage medium (e.g., CD-ROM); magneto-optical storage medium; read-only memory (ROM); random-access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory; electrical, optical, acoustical, or other form of propagated signal (e.g., carrier waves, infrared signals, digital signals, etc.); or another type of medium suitable for storing electronic instructions.