Control system for an optical storage device

A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for receiving the un-corrected output signal and correcting an error bit according to a Reed-Solomon algorithm to generate a corrected output signal, a lock performance detector for receiving the re-timing signal and detecting the lock performance of the re-timing signal and then outputting a lock performance index, and a servo control loop for receiving the RF signal and the lock performance index and thus generating a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads other control parameters to improve the read performance of the optical storage device.

This application claims the benefit of the filing date of Taiwan Application Ser. No. 095141605, filed on Nov. 10, 2006, the content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a control system for an optical storage device, and more particularly to a control system for determining read performance of an optical storage device according to lock performance of a re-timing signal.

2. Related Art

In a typical digital versatile disk (DVD) product, a method of adjusting a servo system parameter is to count the number of errors of an error correction code (ECC). When the number of the ECC errors is great, a servo system has to try another set of parameters and then count the number of the ECC errors again.

FIG. 1shows the architecture of a conventional control system for an optical storage device. Referring toFIG. 1, the control system10for the optical storage device includes an optical pickup12, a servo control unit13, a filtering and re-timing unit14, an error correction unit15and a servo control loop16. The optical pickup12reads a signal of an optical disc11and then generates a radio frequency (RF) signal. The filtering and re-timing unit14reads the RF signal and generates an un-corrected output signal. The error correction unit15reads the un-corrected output signal and then corrects an error bit in an error control code block of a data block memory cell according to a Reed-Solomon (RS) algorithm to generate a corrected output signal. When the error correction unit15is correcting the data, it also counts the number of errors and outputs an error counting value. The servo control loop16receives the error counting value and the RF signal associated with a servo, and outputs a servo control signal. The servo control unit13receives the servo control signal and controls operations of a spindle motor and the optical pickup12.

When the number of the ECC errors (the error counting value) is great, the servo control loop16has to try another set of parameters to count the number of the ECC errors again. Because the time for counting the number of the ECC errors is longer, the time for the overall procedure of adjusting the servo system parameters is longer.

SUMMARY OF THE INVENTION

It is therefor an object of the invention to provide a control system for determining read performance of an optical storage device according to lock performance of a re-timing signal.

The invention achieves the above-identified object by providing a control system for determining read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit, an error correction unit, a lock performance detector and a servo control loop. The filtering and re-timing unit receives a RF signal and outputs the re-timing signal and an un-corrected output signal. The error correction unit receives the un-corrected output signal and corrects an error bit according to a Reed-Solomon algorithm to generate a corrected output signal. The lock performance detector receives the re-timing signal and detects the lock performance of the re-timing signal to output a lock performance index. The servo control loop receives the RF signal and the lock performance index and thus generates a servo control signal. When the lock performance index does not reach a threshold value, the servo control loop loads another set of control parameters to improve the read performance of the optical storage device.

DETAILED DESCRIPTION OF THE INVENTION

The control system according to the invention will be described with reference to the accompanying drawings.

FIG. 2shows the architecture of a control system20for an optical storage device according to the invention. Referring toFIG. 2, the control system20includes an optical pickup12, a servo control unit13, a filtering and re-timing unit24, an error correction unit25, a servo control loop26and a lock performance detector27. The optical pickup12reads a signal of an optical disc11and then generates a RF signal. The filtering and re-timing unit24reads the RF signal and generates an un-corrected output signal. The error correction unit25reads the un-corrected output signal and then corrects an error bit of an error control code block in a data block memory cell according to a Reed-Solomon algorithm to generate a corrected output signal. The invention mainly utilizes the lock performance detector27to detect a re-timing signal outputted from the filtering and re-timing unit24, and to output a lock performance index as a reference for determining read performance of the optical storage device. The servo control loop26receives the lock performance index and the RF signal associated with a servo and outputs a servo control signal. The servo control unit13receives the servo control signal and controls operations of a spindle motor and the optical pickup12.

The invention utilizes the lock performance detector27to detect the re-timing signal outputted from the filtering and re-timing unit24and to output the lock performance index as the reference for determining the read performance of the optical storage device. If the lock performance index reaches a predetermined level (e.g., exceeds a threshold value), it represents that the servo system has been adjusted to the predetermined level. If the lock performance index is not good (e.g., lower than the threshold value), it represents that the data reading condition of the system is not good, and the control parameter of the servo system has to be adjusted. Because the invention utilizes the lock performance detector27to replace the counted number of the ECC errors and the time for the lock performance detector27to generate the lock performance index is shorter, the invention can shorten the time of adjusting the servo system parameter.

FIGS. 3 to 5shows the architectures of the lock performance detector27of the invention in conjunction with different types of clock reconstructing loops, whereinFIGS. 3 and 4correspond to an analog sampling clock reconstructing loop andFIG. 5corresponds to a fully digital sampling clock reconstructing loop.

As shown inFIG. 3, an analog processing unit31receives an input signal, and then generates an analog processing signal. A sampling clock generating unit32receives an output signal of the analog processing unit31and generates a sampling clock. A sampling unit33samples the analog processing signal according to the sampling clock and generates a re-timing signal. The lock performance detector27detects the quality of the re-timing signal and then generates the lock performance index. A digital processing unit34receives the re-timing signal and then generates the un-corrected output signal.

FIG. 4is similar toFIG. 3except that a sampling clock generating unit42is not controlled by the analog processing unit31but is controlled by a digital processing unit44and generates a sampling clock.

FIG. 5is similar toFIG. 3except that the sampling clock generating unit42generates a sampling clock with a constant frequency, and a digital processing unit54receives the re-timing signal and generates the un-corrected output signal.

FIG. 6shows the waveform constituted by the re-timing signal. As shown inFIG. 6, data points61to63of the re-timing signal are greater than 0, and data points64to66of the re-timing signal are smaller than 0. Thus, the data points63and64are two points of the zero level crossing. When the lock performance of the re-timing signal is good, the two points are respectively located on two sides of the zero level and are equally spaced from the zero level. When the lock performance of the re-timing signal is poor, the data points63and64are not equally spaced from the zero level. The invention adopts a specially designed method to count the symmetrical properties of the data points63and64. An analog-to-digital converter samples the RF signal into a signal having a sampling frequency greater than a data rate so that the data can be reproduced using a partial response maximum likelihood (PRML). If the signal quality is not bad, no re-timing signal appears around the zero. The invention also evaluates the quality of the present re-timing signal according to the symmetrical property of the re-timing signal at the zero-crossing point.

FIG. 7is a block diagram showing a lock performance detector according to an embodiment of the invention. Referring toFIG. 7, the lock performance detector27includes a first register71, a second register72, a zero-crossing point detection unit73, a zero-crossing point data comparing unit74, a lock performance detection unit75, a counting unit76and a detection period control unit.

The first register71receives and stores the re-timing signal and transfers the stored data to the second register72when new data is received. Thus, the first register71and the second register72store the re-timing signal of the neighboring two points. The first register71outputs first data RTO1_D, and the second register72outputs second data RTO2_D. So, the data RTO1_D and RTO2_D are the front and rear points of the re-timing signal. The zero-crossing point detection unit73receives the first data RTO1_D and the second data RTO2_D, detects whether the data crosses the zero level, and outputs a zero-crossing signal ZC_DET. That is, when the first data RTO1_D and the second data RTO2_D cross the zero level, the zero-crossing signal is enabled or otherwise the zero-crossing signal is disabled.

The zero-crossing point data comparing unit74receives the first data RTO1_D, the second data RTO2_D and the zero-crossing signal, and outputs the larger data RTOL and the smaller data RTOS when the zero-crossing signal is enabled. That is, the distance from the larger data RTOL to the zero level is larger than the distance from the smaller data RTOS to the zero level. In other words, the larger data RTOL corresponds to the point obtained by taking a larger one of absolute values of two crossing points, and the smaller data RTOS corresponds to the point obtained by taking a smaller one of the absolute values of the two crossing points.

The lock performance detection unit75receives the larger data RTOL, the smaller data RTOS and the zero-crossing signal, and outputs a first counting signal HIT1and a second counting signal HIT2according to the lock quality when the zero-crossing signal is enabled. For example, when 1.5*RTOS>RTOL, it means that the first data RTO1_D and the second data RTO2_D are slightly symmetrical, so the first counting signal HIT1is enabled. When RTOL−RTLS<=1, it means that the first data RTO1_D and the second data RTO2_D are quite symmetrical, so the second counting signal HIT2is enabled. The weighting of the second counting signal HIT2is higher than that of the first counting signal HIT1.

The counting unit76receives the first counting signal HIT1and the second counting signal HIT2and performs a counting operation when the first counting signal HIT1and the second counting signal HIT2are enabled. For example, the counting unit76adds 1 to the counting value when the first counting signal HIT1is enabled; and the counting unit76adds 2 to the counting value when the second counting signal HIT2is enabled.

The lock performance detection unit75and the counting unit76may also have different variations. For example, the invention may also assign different weighting coefficients according to different symmetrical properties, and the counting unit can assign the different weighting coefficients for calculation according to the bad-quality extent of the detection signal. For example, the weighting coefficient is set as 1 when 1.5*RTOS<=RTOL; the weighting coefficient is set as 2 when 2*RTOS<=RTOL; the weighting coefficient is set as 3 when 2.5*RTOS<=RTOL; and the weighting coefficient is set as 4 when 3*RTOS<=RTOL. Thus, the lock performance detection unit75outputs four counting signals and the counting unit76can add a changeable value to the counting value according to the different weighting coefficients set by the four counting signals.

The detection period control unit77receives the zero-crossing signal and controls the output operation of the counting unit76according to the zero-crossing signal. For example, the detection period control unit77can count the number of enabling times of the zero-crossing signal, and then enables and outputs a finishing signal FINISH to the counting unit76after the number of enabling times of the zero-crossing signal has exceeded a default number. Consequently, the counting unit76outputs the counting value as the lock performance index when the finishing signal FINISH is enabled. For example, the cyclic unit may be 4096 or 4096*2^N, wherein N is a positive integer.

FIG. 8shows an embodiment of the zero-crossing point data comparing unit. Referring toFIG. 8, the zero-crossing point data comparing unit74includes two absolute value calculating units81and82, one comparator83and two multiplexers84and85. The absolute value calculating units81and82respectively receive the first data RTO1_D and the second data RTO2_D and then output two absolute values RTO1_AD and RTO2_AD to the comparator83and the two multiplexers84and85. The comparator83compares the absolute values RTO1_AD and RTO2_AD with each other and then outputs a comparison signal to control the outputs of the multiplexers84and85. That is, when the absolute value RTO1_AD is greater than or equal to the absolute value RTO2_AD, the multiplexer84outputs the absolute value RTO1_AD as the larger data RTOL, and outputs the absolute value RTO2_AD as the smaller data RTOS. Oppositely, when the absolute value RTO1_AD is smaller than RTO2_AD, the multiplexer84outputs the absolute value RTO2_AD as the larger data RTOL and outputs the absolute value RTO1_AD as the smaller data RTOS.

FIG. 9shows an embodiment of the lock performance detection unit. Referring toFIG. 9, the lock performance detection unit75includes an adder91, a subtracter92, two comparators93and94and two multiplexers95and96. The adder91adds the RTOS[4:0] and RTOS[4:1] together and then outputs the sum thereof to an input terminal A of the comparator93. That is, the data outputted from the adder91is 1.5*RTOS. The comparator93compares the output data of the adder91with the larger data RTOL, and sets a first selection signal as 1 when the output data of the adder91is greater than the larger data RTOL, or otherwise sets the first selection signal as 0. The multiplexer95is controlled by the first selection signal and outputs the zero-crossing signal ZC_DET when the first selection signal is 1, or otherwise outputs 0. The subtracter92subtracts the larger data RTOL[4:0] and the smaller data RTOS[4:0] from each other. The comparator94determines whether the output result of the subtracter92is smaller than or equal to 1 by way of comparison. When the output result of the subtracter92is smaller than or equal to 1, the comparator94sets the second selection signal as 1, or otherwise sets the second selection signal as 0. The multiplexer96is controlled by the second selection signal and outputs the zero-crossing signal ZC_DET when the second selection signal is 1, or otherwise outputs 0.

FIG. 10shows an embodiment of the counting unit. Referring toFIG. 10, the counting unit76includes four multiplexers1001to1004, two registers1005and1006and two adders1007and1008. When the first counting signal HIT1is 1 (enabled), the multiplexer1001outputs the data obtained after 1 has been added by the adder1007. When the first counting signal HIT1is 0 (disable), the multiplexer1001outputs the present counting value. When the second counting signal HIT2is 1, the multiplexer1002outputs the data, which is obtained after 2 is added by the adder1008. When the second counting signal HIT2is 0 (disabled), the multiplexer1002outputs the value of the multiplexer1001. When the finishing signal FINISH is 1, the multiplexer1003outputs the data of 000H and stores the data of 000H to the register1005, and the multiplexer1004stores the data of the register1005to the register1006. When the finishing signal FINISH is 0, the multiplexer1003outputs the value of the multiplexer1002and stores the value of the multiplexer1002to the register1005, and the multiplexer1004stores the data of the register1006back to the register1006.

So, the control system for the optical storage device according to the invention utilizes the lock performance detector to detect the lock performance of the re-timing signal as the reference for determining the read performance of the optical storage device, and the time for detecting the read performance of the optical storage device can be shortened. Consequently, when the lock performance index does not reach a threshold value, the servo control loop loads another set of control parameters to improve the read performance of the optical storage device. Of course, the time for the lock performance detector to detect the lock performance of the re-timing signal is shorter, so the servo control loop may also test multiple sets of control parameters and select the control parameter corresponding to the best lock performance index as the actual control parameter of the optical storage device.

In addition, the invention may also perform the quality detection according to the T number in a certain range, and adjust the parameter according to the crossing condition of the T number (e.g., 3T to 4T) in the certain range. That is, the detection is performed only if the condition of the set T number is satisfied. The lock performance detector27may include a signal length detection unit for calculating the time between neighboring two enabling instants of the zero-crossing signal ZC_DET and enabling a range control signal when the time satisfies a default time range. In addition, the counting unit76cannot count until the condition that the range control signal is enabled is satisfied.

While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications. For example, the embodiment is implemented by detecting the good extent of the symmetrical property. Of course, the bad extent of the symmetrical property may also be detected, and another set of control parameters is loaded when the bad extent is higher than a threshold value. For example, when 1.5*RTOS<=RTOL, it means that the symmetrical property is not good. When 2*RTOS<=RTOL, it means that the symmetrical property is too bad and the weighting coefficient of the counting value can be increased. In addition, the good quality may be determined by detecting the sufficient symmetrical property in this embodiment. However, the good quality may be determined when two crossing points are greater than a predefined value.