Data load sequencer for multiple data line serializer

A data load serializer for use in conjunction with a multi-stage, multiple parallel data channel serializer is described. Each data channel of the data serializer preferably includes a data sensing stage and a data latching stage. The serializer is preferably responsive to the provision of an address for selecting data from the main buffer memory for provision to the serial buffer memory and further preferably includes sequencer control logic for receiving the main buffer memory address and for directing the transfer of data between the main and serial buffer memories and an address counter for receiving a start location address referencing a beginning serial data buffer memory location of the storage of data sourced to or from the data serializer. The sequencer control logic provides for the selection of respective data from the serial data buffer for each of the parallel data channels and enables the parallel sensing and latching of the respectively selected data in preparation for sourcing from the data serializer.

DETAILED DESCRIPTION OF THE INVENTION 
A dual parallel channel data serializer, generally indicated by the 
reference numeral 10, is shown in FIG. 1 as an exemplary serializer 
embodying the load sequencer of the present invention. As shown, a dynamic 
random access memory (DRAM) buffer 12 is utilized as the main buffer 
memory of the serializer 10. A static random access memory (SRAM) buffer 
18 is utilized as the serial data buffer memory. Internal data transfers, 
or parallel data loads, are permitted between the DRAM and SRAM buffer 
memories 12, 18 by the transfer gate block 14 as coupled thereinbetween by 
the parallel data lines 16, 20. A control and load sequencer logic unit 22 
is provided to coordinate external data transfers between a host processor 
(not shown) and DRAM buffer memory 12 and between the DRAM and SRAM buffer 
memories 12, 18. Addresses provided by the host processor are received by 
the data serializer 10 on the address lines 26. Various control signals, 
including a write control signal, are provided on lines 30 while memory 
timing signals, such as row address strobe and column address strobe are 
provided on lines 32. For data transfers between the host processor and 
the DRAM buffer memory 12, the control and load sequencer logic 22 
provides the appropriate control and timing signals to the DRAM buffer 
memory 12 via the DRAM control and timing lines 38. Depending on the 
control signals initially provided by the host processor on lines 30, data 
is transferred to or from the DRAM buffer memory 12 via the data lines 28. 
The source or destination of the data transferred with respect to the DRAM 
buffer memory 12 is specified by the host processor by its selection of 
the address provided on the address lines 26. 
Preferably, data loads between the DRAM and SRAM buffer memories 12, 18 are 
initiated in response to an address and specific combination of control 
and timing signals provided by the host processor on lines 26, 30, 32 to 
the data serializer 10. In particular, where the data capacity of the SRAM 
buffer memory matches that of a single row of the DRAM buffer memory as is 
preferred, the row selection portion of the address provided by the host 
processor is preferably utilized to designate a row within the DRAM buffer 
memory 12 as the source or destination for the data load. Further, the 
write control and the timing signals provided on lines 30, 32 preferably 
select the direction of the data load between the DRAM and SRAM buffer 
memories 12, 18. Accordingly, the control and load sequencer logic unit 22 
provides control and timing signals to the DRAM buffer memory 12 via lines 
38, to the SRAM buffer memory 18 via lines 42 and a load enable control 
signal to the load gate block 14 via the control line 40. 
Preferably also present within the data serializer 10 is an address latch 
and counter 24. Preferably the column select portion of the address 
provided on the address lines 26 is received by the address latch and 
counter 24 along with the column address strobe signal from the timing 
lines 32. Further, the address latch and counter 24 preferably receives a 
clock signal, V.sub.CLK, on line 34 as a timing signal sychronized to the 
rate that serial data is sourced to or from the data serializer 10. 
Finally, an address load enable signal is provided by the control and load 
sequencer logic unit 22 via the control line 36. The address latch enable 
signal is preferably provided whenever the control and load sequencer 
logic unit 22 determines that the host processor is providing a new, 
initial count value for use by the address latch and counter 24, such as 
in conjunction with the loading of a new row of data from the DRAM 12 to 
SRAM buffer memory 18. 
Preferably, the count value provided by the address latch and counter 24 on 
the counter output lines 46 is utilized to select corresponding memory 
locations from the SRAM buffer memory 18 and the data lines 44 of the SRAM 
buffer memory 18 for coupling via the dual parallel, serial data channel 
sense stages 52, 54 of the serializer 10. A serial data path controller 
50, operating under the controlling direction of the control and load 
sequencer logic unit 22 as manifested via the control lines 42, 
sequentially enables the respective decode selection of an SRAM data 
location, the sensing of data therefrom and provision, via sense stage 
output lines 58, 60, to a respective data latch 62, 64 and the latching of 
the data therein. The serial data path controller 50 preferably operates 
each of the parallel data channels of the preferred dual parallel channel 
serializer 10 so as to alternately provide data into the latches 62, 64. 
Thus, with each V.sub.CLK signal received by the control and load 
sequencer logic unit 22, a data channel select control signal is provided 
on the multiplexor select line 118 of a multiplexor 74 so as to 
alternately provide data obtained from the latches 62, 64, via data lines 
66, 68, onto the serial data output lines 70 of the serializer 10. 
Preferably, an external serial data output enable signal (SG.sub.x), 
provided on a control line 72 to the multiplexor 74, may be used by the 
host processor to selectively enable the multiplexed output of data onto 
the serial output lines 70. 
The diagram of FIG. 2 illustrates a system incorporating two serializers 
10.sub.1, 10.sub.2 coupled to a high speed serial shift register 80 for 
providing a bit serial stream of data as may be appropriate for high 
resolution video graphics applications. The serializers 10.sub.1, 10.sub.2 
receive, in parallel, the address and data buses 26, 28, a video clock 
signal, on the V.sub.CLK line 34, and various control and timing signals, 
here shown simply as provided on lines 30. The shifter 80 receives a high 
frequency dot clock (D.sub.CLK) signal via a line 90 in addition to at 
least some of the control signals provided on lines 30. The serial 
bi-directional data buses 70.sub.1, 70.sub.2 of the serializers 10.sub.1, 
10.sub.2 are provided in parallel to the shifter 80. Preferably, the 
serial data buses 70.sub.1, 70.sub.2 each provide four bits in parallel. 
That is, the serializers 10.sub.1, 10.sub.2 provide a serialized reduction 
in the bit parallel width of the row data initially loaded in parallel to 
their respective SRAM buffer memories 18. Thus, the shifter 80, as shown 
in FIG. 2, provides for a further serializing reduction of data width from 
the 8-bits parallel provided by the two paralleled serializers 10.sub.1, 
10.sub.2 to a single bit wide serial data stream ultimately provided on 
the shifter output line 92. 
In accordance with a preferred embodiment of the present invention, new 
data is present and available on the serial data bus 70.sub.1 from the 
serializer 10.sub.1 at the conclusion of an internal data load cycle and 
prior to the first significant edge transistion of the V.sub.CLK signal 
following the data load cycle. This presumes that the serializer 10.sub.1 
is placed in a "next cycle read" mode during the data load cycle. That is, 
in the first cycle following the conclusion of the data load cycle, newly 
available data will be read from the data serializer onto the serializer 
output bus 70.sub.1. By provision of a bi-directional transfer gate 84, 
selected in response to a copy (COPY) enable signal provided on a control 
line 82, the data from the serial bus 70.sub.1 may be also made available 
on the serial data bus 70.sub.2 of the second serializer 10.sub.2. Again 
provided that the host processor has placed the second serializer 102 in a 
"next cycle write" data mode, wherein data is sourced or written from the 
serial data bus 70.sub. 2 into the serial data SRAM buffer memory of the 
serializer 10.sub.2, a one for one transfer of data from the SRAM buffer 
memory of the serializer 101 to that of the serializer 10.sub.2 will occur 
with the subsequent, sequential provision of the V.sub.CLK signal. 
Accordingly, an image of the data contained in the DRAM memory array of 
the first serializer 10.sub.1, or any portion thereof, may be transferred 
to the DRAM buffer memory of the second serializer 10.sub.2 without 
requiring any significant host processor interaction. This system oriented 
advantage is uniquely due to the ability of the the present invention to 
provide the first new data available on the serial bus 70.sub.1 at about 
the conclusion of a data load cycle and prior to the first following 
significant V.sub.CLK edge transistion. 
Referring now to FIG. 3, the significant components of a preferred 
embodiment of a control and load sequencer unit are shown in conjunction 
with the corresponding significant portions of a complete dual data 
channel data serializer. Included within the control logic unit is a 
transfer control block 154 that receives the row address strobe (RAS) and 
transfer (XF) signals on the lines 184, 186, respectively. The transfer 
control block 154 preferably determines whether a data load cycle is being 
requested by examining the states of the row address strobe and transfer 
signals. A resulting data load transfer in progress signal (.phi..sub.TIP) 
is provided during the requested data load cycle on the transfer control 
block output line 170 to the data path controller 134, an address control 
block 162 and a mode control block 164. 
The mode control block 164 operates in response to the transfer control 
block 154 to determine whether the first serial data transfer cycle 
following a currently in progress data load cycle will be a serial data 
read or write cycle. That is, the transfer control block 154 provides the 
mode control block 164 with the data load transfer cycle in progress 
signal via line 170. At about the same time, the column address strobe and 
write select control signals are also received by the mode control block 
164 via lines 188, 190, respectively. The state of the write select signal 
at the significant edge transistion of the column address strobe signal is 
preferably utilized to identify the next cycle serial data transfer 
direction. The result of this determination by the mode control block 164 
is provided on control line 172 to the data path controller 134. 
Additionally, the occurance of the significant edge transistion of the 
column address strobe signal is reported to the address control block 162 
via control line 178. In response, the address control block 162 
preferably provides a counter load signal to the counter 160. 
Consequently, the address as provided by the host processor on the address 
bus 26 is latched into the counter 160 as its new count value. This count 
value is, in turn, provided over the counter output bus 166 to an address 
decoder 150. In subsequent operation, the counter 160 will generate new 
count values, generally in response to the V.sub.CLK signal as provided on 
line 34 to the address control block 162 and then as a counter increment 
control signal (.phi..sub.INC) to the counter 160 via increment control 
line 176. 
Finally, an even/odd control block 156 is preferably provided to select, at 
a minimum, one of the parallel data channels for providing the first new 
data at the conclusion of the current data load cycle. The even/odd 
control block 156 therefore preferably receives, at least, the single 
least significant bit of the address provided by the host processor via 
the address bus 26. An even or odd select signal, in the case of dual data 
channels, is thereby generated by the even/odd control block 156 and 
provided to the data path controller 134 via control line 168. 
In accordance with the preferred embodiment of the present invention, the 
remainder of the data serializer includes the serial data buffer memory 
partitioned as respective even and odd SRAM arrays 142, 144, dual data 
lines 106, 108 respectively coupled to the even and odd SRAM arrays 142, 
144 by respective even and odd SRA bit lines 146, 148, even and odd data 
line read circuits 110, 112, respectively coupled to the even and odd data 
lines 106, 108 at the even read data mode 109 and the odd read data mode 
111, and, further, to the multiplexor 74 by the even read data output data 
line 114 and odd read data output data line 116. The multiplexor output 
line 120 is further connected to the output buffer 122, gated in response 
to the internal (SG.sub.I) and user supplied external (SG.sub.X) serial 
output enable signals on the output enable control lines 72, 73 to finally 
provide serial data read from the even or odd SRAM arrays 142, 144 on the 
serializer data output lines 124. 
To support bi-directional serial data transfer capabilities, an input 
buffer 126 is coupled to the output data lines 124. The output of the 
input buffer 126 is provided via lines 128 to even and odd data line write 
circuits 130, 132. Preferably the even and odd data line write circuits 
130, 132 provide for the alternatively latched buffering and driving of 
data onto the respective even and odd data lines 106, 108 via the even and 
odd data line write data nodes 131, 133. Timing control of the even and 
odd data line write circuits 130, 132 is preferably again provided by the 
data path controller 134 as applied via control and timing lines 138. 
The preferred circuit architecture for the decoder 150, even and odd SRAM 
arrays 142, 144 and the dual data channel read and write circuits 100, 
102, as well as the preferred mode of operation, is shown and described in 
the aforementioned "High Speed Data Serializers". Accordingly, the 
disclosure of that application is expressly incorporated herein by 
reference. For convenience, however, FIG. 4 provides a circuit diagram of 
the significant perferred circuitry associated with respective even and 
odd SRAM memory cell logic circuits and the preferred circuitry of the 
data line read and write circuits 110, 112. Generally, as shown in FIG. 4, 
the exemplary even and odd SRAM logic circuits 200 are coupled to 
discretely decoded logic output lines 152 of the decoder 150 corresponding 
to the intended selection of their even and odd SRAM cells 232, 233. In 
ordinary operation, separate states of the decoder output lines 152 are 
enabled for ultimate storage in the even and odd latched buffers 228, 230 
by the alternate, mutually execlusive provision of the .phi..sub.SYNL(E) 
and .phi..sub.SYNL(0) signals to the respective gate control lines 206, 
208 of even and odd selection enable gates 202, 204. Thus, the contents of 
the even and odd SRAM cells 232, 233 are passed onto the respective data 
lines 106, 108 by the even and odd data pass gates 238, 240. As described 
in the aforementioned application, the preferred mode of operation 
provides for the selection of separate even and odd SRAM logic circuits 
200 during alternate clock cycles. That is, a new count value is provided 
to the decoder 150 in response to each significant edge transistion of a 
clock signal and, shortly following therefrom, either the even or odd SRAM 
array selection enable gates 202, 204 are D enabled by provision of the 
.phi..sub.SYNL(E) or .phi..sub.SYNL(0) signals. Thus, the single even or 
odd logic circuit 200, corresponding to the single decoded "on" or 
selected output line of the decoder 150, receives an SRAM select signal to 
be latched into a logic circuit 200 upon withdrawal of the 
.phi..sub.SYNL(E) or .phi..sub.SYNL(0) signal. 
Consistent with the resultant alternating selection and provision of data 
onto the even and odd data lines 106, 108, the even and odd sense 
amplifiers 242, 244 and sensed data transfer gates 254, 256 are enabled by 
the respective provision of the .phi..sub.SAE(E), .phi..sub.SAE(0), 
.phi..sub.SDBL(E) and .phi..sub.SDBL(0) signals to their respective 
control gate enable lines 250, 252, 258, 260. Thus, in alternating clock 
cycles, new data is provided to the even and odd latches 262, 264 and 
thereby made available to the multiplexor 74 via multiplexor input lines 
114, 116. Selection of an even or odd data latch 262, 264 appropriately 
alternates with each clock cycle in response to the provision of the 
.phi..sub.SDS signal on the multiplexor select control line 118. The 
output of the multiplexor 74 is provided via the output buffer 122 onto 
the serial data output lines 124. 
Ordinary write operations preferably utilize the input even and odd data 
gates 270, 272 to effectively demultiplex serial data from the output data 
line 124 as provided via the input buffer 126 out to the input buffer 
output line 128. Preferably, the .phi..sub.SDIL(E) and .phi..sub.SDIL(0) 
signals are provided from the data path controller 134 on the respective 
control gates 274, 276 during alternate clock cycles. Thus, during each 
clock cycle, data is passed via the even or odd latches 266, 268 to the 
even and odd data line write circuits 278, 280. These write circuits 278, 
280 are respectively enabled by .phi..sub.SW(E) and .phi..sub.SW(0) 
signals provided on the write control lines 282, 284, resulting in the 
driving of data onto their respective even or odd data lines 106, 108. In 
anticipation of the data being written, a respective even or odd SRAM 
logic circuit 200 is selected by the earlier provision of an appropriate 
count value to the decoder 150. Thus, data is passed from the even or odd 
data line 106, 108 to the selected even or odd SRAM cell 232, 233 via the 
SRAM data pass gate 238 or 240. 
In accordance with the present invention, even and odd decoded address 
select latches 210, 212 are provided in each of the SRAM logic circuits 
200 of the respective even and odd SRAM arrays 142, 144. The latches 210, 
212 are respectively positioned to receive and latch the logic circuit 
select signal provided on their respective decoder input lines 152 as 
received via the select signal pass gates 202, 204. Further in accordance 
with the present invention, selection signal blocking gates 214.sub.1-n 
are provided in each of the SRAM logic circuits so as to couple their 
respective latches 210, 212 with the latched buffers 228, 230. All of the 
select blocking gates 214.sub.1-n are preferably controlled in common by a 
.phi..sub.SISO signal provided on the gate control line 216. Thus, by 
provision D of the .phi..sub.SISO signal, the selection of even or odd 
SRAM cells 232, 233 can be effectively halted independent of the operation 
of the counter 160, decoder 150 and, with the exception of the 
.phi..sub.SISO signal, the data path controller 134. Finally, in 
accordance with the present invention, the output buffer 122 is modified 
to permit the selective enabling of its provision of serial data onto the 
serial data output line 124 in response to an internally generated serial 
output enable signal (SG.sub.I) provided on a control line 73 from the 
data path controller 134. In particular, as shown in FIG. 3, the internal 
(SG.sub.I) and the complementary external (SG.sub.X) serial output enable 
signals are combined by a logical AND function to determine the output 
enable state of the output buffer 122. 
Reference is now made to FIG. 5 wherein the timing of a data load cycle 
performed in accordance with the present invention and, further, with 
respect to the preferred data serializer architecture, as shown in FIG. 3, 
is illustrated. Preferably, a data load cycle is selected by a significant 
edge transistion of the transfer signal XF that of the row address strobe 
signal, occuring at about t.sub.1 and t.sub.7, respectively. In accordance 
with conventional DRAM address timing, a row address value is provided at 
about t.sub.4 and prior to the significant edge transistion of the row 
address strobe signal. Preferably, also at about t.sub.4, the state of the 
write control signal is utilized to indicate the desired data load 
direction during the current data load cycle. This data load direction 
indicator is preferably latched into the mode control block 164 in 
response to the data load transfer in progress signal from the transfer 
control block 154. Preferably, the significant edge transistion of the 
transfer in progress signal, when received by the data path controller 
134, instigates the provision of a .phi..sub.SST signal, if the data load 
transfer direction is to the SRAM arrays 142, 144, at about t.sub.8 and 
the provision of a .phi..sub.TRD signal at about t.sub.10. The 
.phi..sub.SST and .phi..sub.TRD signals are both shown and described in 
U.S. Pat. No. 4,731,758, entitled "Dual Array Memory With Inter-array 
Bi-directional Data Transfer", filed June 21, 1985 and assigned to the 
assignee of the present invention. Accordingly, the disclosure of the 
above patent application is expressly incorporated herein by reference. 
For purposes of completeness with respect to the present invention, it is 
sufficient to say that the .phi..sub.SST signal is provided beginning just 
prior to a data load cycle from the DRAM buffer memory 12 to the SRAM 
buffer memory 18 and subsequently withdrawn to latch the data load 
transferred data into the SRAM buffer memory 18. Preferably, with respect 
to data load cycle transfers from the SRAM buffer 
memory 18 to the DRAM buffer memory 12, the .phi..sub.SST signal is not 
actually generated, but rather an emmulation signal .phi..sub.SST, is 
generated to effectively define both the beginning and end of the actual 
transfer of data between the DRAM and SRAM buffer memories 12, 18. The 
generally related signal .phi..sub.TRD is provided immediately after the o 
provision of the .phi..sub.SST/SST ' signal and is utilized to enable the 
transfer gates within the transfer logic block 14. The .phi..sub.TRD 
signal is preferably withdrawn shortly after the withdrawl of the 
.phi..sub.SST/SST' signal at about t.sub.25 and, thus, after the 
transferred data has been latched into its destination. 
Also in response to the significant edge transistion of the .phi..sub.TIP 
signal, the internal serial output enable signal (SG.sub.I) is withdrawn 
at about t.sub.10. This results in a termination of the validity of the 
serial data present on the data output line 124 at about t.sub.12 ; the 
data having been present since about t.sub.7 in response to the last 
significant edge transistion of the V.sub.CLK signal occuring at about 
t.sub.1 and prior to the initiation of the current data load cycle. 
Preferably, the serial data output lines 124 of the output buffer 122 are 
simply placed in a high impedence state in response to the withdrawal of 
the internal serial output enable signal. 
The write control signal is further used, in accordance with the present 
invention, to indicate the serial data transfer direction desired in at 
least the first serial data transfer cycle following the conclusion of the 
present data load cycle. That is, following the significant edge 
transisiton of the row address strobe signal, the write control signal 
changes to a state appropriate to indicate that the next cycle following 
completion of the current data load cycle will be either a serial data 
transfer read or write. Preferably, the next cycle serial data transfer 
direction establishes the transfer direction of the serial data stream 
until the next data load cycle. In the preferred embodiment, the write 
control signal changes state beginning at about t.sub.10 along with the 
conventional change of state on the address bus to provide the column 
portion of the address. The state of the write control signal is 
preferably latched into the mode control block 164 at about t.sub.13 in 
response to the signficant edge transistion of the column address strobe 
signal. Accordingly, the mode control logic block 164 provides the data 
path controller 134 with a logic signal, via lines 172, indicative of the 
selected next cycle serial data transfer direction. This permits the data 
path controller 132 to perform the appropriate management of the data 
paths during the data load cycle in preparation for the indicated next 
cycle serial data transfer. 
Finally, at about t.sub.32, the row address strobe signal is withdrawn. 
Preferably, where a next cycle serial data read is selected for the next 
serial data transfer cycle, this trailing edge transistion of the row 
address strobe signal follows the completion of the loading of each of the 
serializer data channels. Thus, upon withdrawal of the row address strobe 
signal, serial data is available on the serial data bus 124 as early as 
about t.sub.38. The appearance of this first serial data may be delayed by 
extending the RAS active period or lost by failure to provide the external 
serial output enable signal (SG.sub.X) in time. Thus, the provision of the 
external serial output enable signal is a further prerequisite for the 
provision of valid data on the serial data output bus 124. Accordingly, 
the external serial output enable signal is preferably provided at about 
t.sub.34. 
Assuming again that the next serial data transfer cycle following the 
conclusion of a data load cycle is a serial data read cycle, beginning at 
about t.sub.40, the first of the new serial data is present and available 
on the serial data output bus 124 between about t.sub.37 to about 
t.sub.46. The significant edge transistion of the V.sub.CLK signal causes 
the next new serial transfer data to be provided onto the serial data 
output bus 124 at about t.sub.46, whereupon the data remains valid until 
about t.sub.55. Alternately, assuming that the first serial data transfer 
cycle following the data load cycle is a serial data write cycle, data 
provided by another serial data source, including another serial data 
serializer 10, is preferably present on the serial data output bus 124 
prior to the significant edge transistion of the first V.sub.CLK signal at 
about t.sub.40. Significantly with regard to both next cycle read and 
write serial data transfer operations, the present invention provides for 
the immediate provision or utilization of serial data present on the 
serial data bus 124 prior to the first significant edge transistion of the 
V.sub.CLK signal following a data load cycle. 
Considering the operation of the preferred embodiment of the present 
invention in greater detail, reference is now made to FIG. 6. In order to 
provide for the full data loading of the parallel data channels of the 
data serializer 10 during a data load cycle in preparation for a next 
cycle read of serial data in accordance with the present invention, the 
address selection of SRAM data locations is performed concurrent with the 
DRAM to SRAM buffer memory data load. The sensing of each of these 
preselected SRAM data locations begins immediately on conclusion of the 
data load and, further, in parallel for each of the data channels. In 
greater detail, the transfer signal (XF) is preferably provided as shown 
at about t.sub.1 followed by the row address strobe signal at about 
t.sub.3 to indicate the beginning of a data load cycle. Preferably the 
write control signal (not shown) is at a logic "one" level at t.sub.3 to 
indicate a DRAM to SRAM buffer memory data load direction. In response to 
the transfer in progress signal of the transfer control block 154, the 
data path controller preferably issues the .phi..sub.SST and 
.phi..sub.SISO signals at about t.sub.4. The SRAM buffer memory 18 is 
therefore set to receive the row data to be transferred while the decoder 
150 is effectively prohibited from interferring with the row data transfer 
by the selection of any individual SRAM data cells 232, 233. Additionally, 
the internal serial output enable signal is withdrawn at about t.sub.7 
preferably to prevent the inadvertent provision of data onto the serial 
data bus 124. 
While the row data selected in response to the row address, is in transit 
between the DRAM and SRAM buffer memories 12, 18 from about t.sub.5 to 
t.sub.28, the selection of a SRAM cell 232, 233 for each of the data 
channels proceeds. That is, the column address provided following the row 
address to the DRAM buffer memory 12 is latched into the counter 160 in 
response to the column address strobe and counter load signals provided 
via lines 188 and 178, 174. The column address, as a count value, is 
provided to the decoder 150 for decoding. The .phi..sub.SYNL(E) signal, 
assuming an even count value as recognized by the E/O control block 156, 
is first preferably provided about t and maintained until the output of 
the decoder 150 has settled. Thus, at about t.sub.10, the 
.phi..sub.SYNL(E) signal is withdrawn to conclude the latching of a SRAM 
cell select signal in one of the even latches 210. The .phi..sub.INC 
signal is then self-generated by the address control block 162 and 
provided to the counter 160 at about t.sub.12. Consequently, the count 
value stored by the counter 160 is incremented and again provided to the 
decoder 150 for decoding. At about t.sub.15 the .phi..sub.SYNL(0) provided 
by the data path controller 134 and maintained again until the decoded 
outputs of the decoder 150 have settled. Thus, at about t.sub.20, the 
.phi..sub.SYNL(0) signal is withdrawn with the resultant latching of a 
SRAM cell select signal in a corresponding one of the odd latches 212. 
Consequently, the initial steps in selecting respective even and odd SRAM 
cells 232, 233 is substantially complete pending only the conclusion of 
the DRAM to SRAM row data load. 
At about t.sub.29 the data path controller 134 withdraws the .phi..sub.SST 
signal to latch the row data into the SRAM buffer memory 18. This event 
signals that the loading of the serial data channels can continue. Thus, 
the withdrawal of the signal at about t.sub.30 allows the completion of 
the selection of the even and odd SRAM cells 232, 233. That is, the even 
and odd select signals transfer to the latched buffers 228, 230 and enable 
their respective data pass gates 238, 240. The data present in the even 
and odd SRAM cells 232, 233 are provided simultaneously onto the 
respective even and odd data lines 106, 108. The data path controller 134 
then provides sense amplifier enable signals .phi..sub.SAE(E) and 
.phi..sub.SAE (o) to enable the parallel operation of the even and odd 
serial data channel sense amplifiers 242, 244. Also provided are the even 
and odd sense data latch enable signals .phi..sub.SDBL(E)' 
.phi..sub.SDBL(O) to the control lines 258, 260 of the sense amplifier 
data pass gates 254, 256. After a delay appropriate for the sense 
amplifiers 242, 244 to sense the data from the respective even and odd 
data lines 106, 108, and to allow for the corresponding data to be present 
and stable in the latches 262, 264, the data path controller 134 withdraws 
the .phi..sub.SDBL(E) and .phi..sub.SDBL(O) signals. In turn, the 
.phi..sub.SAE(E) and .phi..sub.SAE(O) signals are withdrawn to conclude 
the serializer data load cycle at about t.sub.40. 
In preparation for subsequent serial data transfer cycles, the 
.phi..sub.INC signal is generated and provided by the address control 
block 162 to the counter 160 at about t.sub.40 This begins the next serial 
data loading of the serial data channel whose data is first selected for 
output following the data load cycle. As illustrated, the first serial 
data sourced will originate from the even SRAM array 142. Thus, at about 
t.sub.41, the data path controller 134 provides the .phi..sub.SYNL(E) 
signal to begin loading the even serial data transfer channel. Finally, 
the significant edge transistion of the .phi..sub.INC signal also prompts 
a change in state of the .phi..sub.SDS signal to select an appropriate 
serial data channel data latch 262, 264 for the provision of serial data 
onto the output data bus 124. As should be readily appreciated, the even 
data latch 262 is selected. In subsequent consecutive serial data read 
transfer cycles, the preferred embodiment of the present invention begins 
the SRAM cell selection process while the same serial channel's data 
buffer is selected and the alternate serial data channel senses and 
latches SRAM data. 
Finally the row address strobe signal is withdrawn, here shown at about 
t.sub.47. In response, the data path controller 134 preferably provides 
the internal serial data enable signal, assuming the prior withdrawal of 
the external serial data enable signal, with the selected multiplexed 
serial data being provided on the serial data output line 124 at about 
t.sub.51. 
Considering now the timing diagram provided illustrated in FIG. 7, a data 
transfer cycle involving a next cycle write operation is substantially 
simpler than that involving a next cycle read. As before, the significant 
edge transistions of the transfer and row address strobe signals at 
t.sub.1 and t.sub.4, respectively, are used to establish that the present 
cycle is a data load cycle. Accordingly, the data path controller 134 
preferably provides, at about t.sub.6, and thereafter maintains the 
.phi..sub.SISO, signal until the data from the SRAM buffer memory 18 is 
fully latched into the DRAM buffer memory 12 at about t.sub.30. Meanwhile, 
at about t.sub.10, the column address provided in the addressing of the 
DRAM buffer memory 12 is loaded into the counter 160 in response to the 
significant edge transistion of the column address strobe signal. Since 
serial data is to be written into the SRAM buffer memory 18, the data path 
controller 134 need provide only for the selection of a signal SRAM memory 
cell 232, 233 to receive the serial data written in the first serial data 
transfer cycle. Assuming that the column address latched into the counter 
160 corresponds to an even SRAM memory cell 232, the data path controller 
134 provides for the storage of the corresponding SRAM cell select signal 
in the even latch 210 by the provision of the .phi..sub.SYNL(E) signal 
between about t.sub.12 and t.sub.19. With the completion of the SRAM to 
DRAM data load as defined by the withdrawal of the .phi..sub.SISO, signal, 
the select signal is freed to be latched into the latched buffer 228. This 
enables the data path transistor 238 of the selected even SRAM memory cell 
232 in preparation for receipt of serial data. 
Thus, there has been described a high performance data load sequencer for 
multiple data line serializers that provides for the rapid loading of all 
of the multiple parallel data channels substantially in parallel in order 
to minimize the time required for the production of new valid data at the 
output of the data serializer following the initiation of a serializer 
data load cycle. 
Naturally, many modifications and variations of the present invention are 
possible in light of the above teachings. In particular, persons of 
ordinary skill in the art will appreciate that the various timing diagrams 
disclosed and discussed herein illustrate relatively timed events and may 
be scaled or otherwise altered within the parameters and relations taught 
above. It is therefore to be understood that, within the scope of the 
appended claims, the invention may be practiced otherwise than as 
specifically described herein.