Sentinel unit for an IT electrical distribution system having a floating reference conductor

A protection system for an IT electrical distribution system (EDS) has a floating reference conductor and two electrical conductors in the form of an active conductor and a neutral conductor. System includes two input terminals for electrically connecting to an MEN electrical power source that is upstream of system. Two output terminals are electrically connected to an electrical load in the form of an electrical motor for a compressor of an upright freezer display. A motor protection device, in the form of an MCB, electrically connects terminals to allow a supply of electrical power to a motor. The MCB is responsive to a fault signal at a port for selectively electrically disconnecting at least one of the terminals. A sentinel unit selectively generates the fault signal at port in response to the current in conductor being greater than a predetermined threshold.

CROSS-REFERENCE TO RELATED APPLICATION

This application is the U.S. national phase of PCT Appln. No. PCT/AU2009/001678 filed Dec. 21, 2009 which claims priority to Australian application 2008906556 filed Dec. 19, 2008, and Australian application 2008906566 filed Dec. 22, 2008, the disclosures of which are incorporated in their entirety by reference herein.

FIELD OF THE INVENTION

The present invention relates to a sentinel unit and in particular to a sentinel unit for an IT electrical distribution system having a floating reference conductor.

Embodiments of the invention have been developed particularly for mains voltage deployments, and will be described herein with reference to that application. It will be appreciated, however, that the invention is not limited to such a field of use, and is applicable in broader contexts. Examples of these other deployments and applications of the invention are found in an Australian patent application in the name of the present applicant and filed with IP Australia on 19 Dec. 2008 (U.S. patent application Ser. No. 13/140,756). The subject matter of that earlier application, in its entirety, is incorporated herein by way of cross-reference.

BACKGROUND

Any discussion of the background art throughout the specification should in no way be considered as an admission that such art is widely known or forms part of common general knowledge in the field.

Known protection devices have been primarily developed for TN electrical distribution systems and require a well-established and common earth connection to function correctly and safely. Most commercially available protection devices are not suitable for use in an IT electrical distribution system.

Protection devices that are available for use in an IT electrical distribution system are often complex and expensive to implement, and are only economic for use in high-end deployments.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a sentinel unit for an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source, via an electrical protection device, to a load, wherein: the protection device is responsive to a fault signal for electrically isolating the load from the source; and the sentinel unit selectively generates the fault signal in response to the current in the reference conductor being greater than a predetermined current threshold.

In one embodiment, the predetermined current threshold is less than about 10 mA.

In one embodiment, the predetermined current threshold is less than about 5 mA.

In one embodiment, the sentinel unit includes a limiting circuit for limiting the current in the reference conductor.

In one embodiment, the limiting circuit limits the current in the reference conductor to no more than the predetermined current threshold.

In one embodiment, the sentinel unit selectively generates the fault signal in response to the current in the reference conductor being greater than the predetermined current threshold and the voltage in the reference conductor being greater than a predetermined voltage threshold.

In one embodiment, the predetermined voltage threshold is less than about 40 Volts.

In one embodiment, the predetermined voltage threshold is less than about 35 Volts.

In one embodiment, the predetermined voltage threshold is less than about 30 Volts.

In one embodiment, the predetermined voltage threshold is less than a touch potential.

According to a second aspect of the invention there is provided a sentinel unit for an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the sentinel unit limits the current flowing in the reference conductor to less than a first predetermined current threshold.

In one embodiment, the IT electrical distribution system supplies electrical power from the source, via an electrical protection device, to the load, and the protection device is responsive to a fault signal for electrically isolating the load from the source.

In one embodiment, the sentinel unit selectively generates the fault signal in response to the current in the reference conductor being greater than a second predetermined current threshold.

In one embodiment, the first predetermined current threshold and the second predetermined current threshold are different.

In one embodiment, the first and second predetermined current thresholds are less than about 35 mA.

In one embodiment, the first and second predetermined current thresholds are less than about 20 mA.

In one embodiment, the first and second predetermined current thresholds are less than about 10 mA.

In one embodiment, the first and second predetermined current thresholds are about 10 mA and 8 mA respectively.

In one embodiment, the first and second predetermined current thresholds are about 8 mA and 5 mA respectively.

In one embodiment, the sentinel unit limits the current flowing in the reference conductor to less than a first predetermined current threshold after the generation of the fault signal.

According to a third aspect of the invention there is provided a sentinel unit for an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the sentinel unit provides a variable impedance to shape a current flowing in the reference conductor.

In one embodiment, the variable impedance substantially maintains a peak value of the current while reducing the average value of the current.

According to a fourth aspect of the invention there is provided a sentinel unit for an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the sentinel unit includes:

a monitoring circuit for selectively generating a fault signal in response to a fault condition in the electrical distribution system; and

policing circuit that is responsive to one or more characteristics of the monitoring circuit for selectively generating the fault signal.

In one embodiment, a failure of the policing circuit to correctly selectively generate the fault signal does not prevent the monitoring circuit from generating the fault signal.

In one embodiment, the monitoring circuit detects the fault condition from one or more characteristics of: the current flowing in the floating reference conductor; and/or the voltage of the floating reference conductor relative to one or more of the electrical conductors.

In one embodiment, the electrical power is provided as an AC voltage waveform having alternate positive half-cycles and negative half-cycles, and the monitoring circuit includes two sub-circuits that are substantively responsive to the fault condition in the positive and negative half-cycles respectively.

In one embodiment, the electrical power is provided as an AC voltage waveform having alternate positive half-cycles and negative half-cycles, and the policing circuit includes two sub-circuits that are one or more characteristics of the monitoring circuit for selectively generating the fault signal in the positive and negative half-cycles respectively.

In one embodiment, the monitoring unit limits the current in the reference conductor.

In one embodiment, the monitoring unit limits the current in the reference conductor to a predetermined peak current value.

In one embodiment, the monitoring unit shapes the current in the reference conductor such that the average current is less than that of a sine wave current having the predetermined peak value.

According to a fifth aspect of the invention there is provided a method for monitoring an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source, via an electrical protection device, to a load, wherein: the protection device is responsive to a fault signal for electrically isolating the load from the source; and the method includes the step of selectively generating the fault signal in response to the current in the reference conductor being greater than a predetermined current threshold.

According to a sixth aspect of the invention there is provided a method for monitoring an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the method includes the step of limiting the current flowing in the reference conductor to less than a first predetermined current threshold.

According to a seventh aspect of the invention there is provided a method for monitoring an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the method includes the step of providing a variable impedance to shape a current flowing in the reference conductor.

According to an eighth aspect of the invention there is provided a method for monitoring an IT electrical distribution system having a floating reference conductor and at least two electrical conductors for supplying electrical power from a source to a load, wherein the method includes the steps of:

providing a monitoring circuit for selectively generating a fault signal in response to a fault condition in the electrical distribution system; and

being responsive to one or more characteristics of the monitoring circuit for selectively generating the fault signal.

DETAILED DESCRIPTION

Referring toFIG. 1there is illustrated a protection system1for an IT electrical distribution system (EDS)2. EDS2has a floating reference conductor3and two electrical conductors in the form of an active conductor5and a neutral conductor6. System1includes two input terminals7and8for electrically connecting to an MEN electrical power source10that is upstream of system1. Two output terminals11and12are electrically connected, via respective conductors5and6, to an electrical load in the form of an electrical motor14for a compressor (not shown) of an upright freezer display15having a metal cabinet16. It will be appreciated that motor14is downstream of the system1. A protection device, in the form of an MCB17, electrically connects terminals7and8to respective terminals11and12to allow a supply of electrical power from source10to motor14. MCB17is responsive to a fault signal at a port18for selectively electrically disconnecting at least one of terminals7and8from the respective output terminals11and12to prevent the supply of electrical power. A sentinel unit19selectively generates the fault signal at port18in response to the current in conductor3being greater than a predetermined current threshold.

A more detailed description of system1is provided in an Australian patent application in the name of the present applicant and filed with IP Australia on 19 Dec. 2008 (U.S. patent application Ser. No. 13/140,756). The subject matter of that earlier application, in its entirety, is incorporated herein by way of cross-reference.

Reference is now made toFIG. 2where there is illustrated a schematic representation of a circuit101of a sentinel unit of an embodiment of the invention. The Figure shows the specific nature and arrangement of electronic components within circuit101. The actual components used in the illustrated configuration are set out in the tables below, and are identified by the reference indicia used inFIG. 2.

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The two resistors R8and R12are laser trimmed post assembly of the circuit to provide the desired triggering threshold for the sentinel unit. In this specific embodiment, R8is laser trimmed to progressively increase the resistance of R8until T2turns ON with 4.5 mA of positive current. R12is then laser trimmed until T1turns ON with 4.5 mA of negative current. This sets the level of current flowing through those resistors that will trigger the respective triacs. This current is practically equivalent to the fault current in conductor3. While the notional fault current threshold for circuit101is 5 mA, the 4.5 mA calibration is used to provide a margin for temperature variability of the triacs. For when circuit101is used in lower temperature environments, the triacs often require a slightly higher voltage—and hence a higher fault current—before triggering. Where circuit101is intended for deployment in more temperature stable applications, R8and R12are trimmed such that the respective triacs turn ON with more than 4.5 mA.

Circuit101provides a number of functions, which are categorized broadly as protection functions, on the one hand, and policing functions, on the other. The protection or monitoring functions are directed to sensing one or more external characteristics to circuit101, and being responsive to those characteristics for selectively generating the fault signal. The policing or management functions are directed to sensing one or more internal characteristics to circuit101, and being responsive to those internal characteristics for selectively generating the fault signal.

Circuit101is connected to the active and neutral conductors5and6. As these conductors are downstream from the protection device they are both open to be switched between two states, one where they are connected to source10, and the other where they are disconnected from source10. Accordingly, these conductors5and6are referred to respectively as the switched active conductor and the switched neutral conductor or, for short, the switch active and the switched neutral respectively. It will be appreciated that terminals7and8are continually connected to the source—subject only to any upstream protection device triggering—via conductors23and24, which are referred to simply as the active conductor and the neutral conductor respectively.

In circumstances where conductors5and6are disconnected from source10, circuit101will not be powered and, hence, will not be operating. Upon connection of conductors5and6with source10, circuit101will quickly power up—within a few milliseconds—and thereafter commence and continually perform the policing functions. Importantly, while there is a short delay in the policing functions being provided, circuit101will provide the required protection functions at all times, including during the transitory power-up phase.

Circuit101includes considerable symmetry and redundancy to contribute to a fast and reliable operation. This speed and reliability is relevant to both the policing functions and the protection functions and to the overall failsafe characteristics offered by circuit101.

Turning to circuit101, it will be appreciated that:The label “Port” adjacent to the switched active in the bottom right-hand side ofFIG. 2corresponds to port37ofFIG. 1.The label “Port” adjacent to the switched neutral in the centre right-hand side ofFIG. 2corresponds to port38ofFIG. 1.The labels “Port” and the adjacent label “Sensor” in the top right-hand side ofFIG. 2correspond to port36and conductor3ofFIG. 1.

The voltage on conductor5—that is, the switched active—is applied to one side of R20and, due to the operation of diodes Z6and Z7in combination, provide a ±15 V square wave voltage signal at the junction of R20and Z6. This square wave is applied, via R21, to the base of transistors Q7and Q8. In the positive and negative half-cycles of the square wave, Q8and Q7respectively are conductive and act (in combination with the associated components) to limit current in those half-cycles. The current that is limited is that current that flows from conductor3, through the respective transistors Q8and Q7, and to the switched neutral.

Due to the biasing of Q7and Q8, any current flow in conductor3appears as a modified sine wave current through resistors R22and R19. In this circuit, it is the sizing of R19that provides critical value for determining the limited of the current in conductor3. Accordingly, the resistance of R19is selected to provide the desired maximum current at the likely maximum voltage to be experienced by the circuit in normal conditions. For a normal AC voltage of 240 V, R19is selected with a value of 1.5 kOhm so that the maximum fault current—that is, the maximum current in conductor3—is limited to 8 mA. In other embodiments using different current limits and/or different voltages, the resistance of R19is selected accordingly.

The capacitor C4is placed in parallel with R22such that, during a fault condition, the sine wave current is shaped to both reduce the average current flowing through Q7and Q8and retain the peak current value. This has a number of advantages. Firstly, by reducing the average current through transistors Q7and Q8it is possible to use smaller and faster transistors. In the context of circuit101, where all the components are contained on a single circuit board having a footprint of 1 inch×0.825 inch, the ability to use smaller transistors is significant. Second, the fault current—that is, the current flowing through conductor3and which personnel are exposed to—will also be limited to a 5 mA peak and a lower average current than a pure sine wave.

The capacitor C3helps to reduce the impact of transient voltages. Typically, these voltages will only have a short duration and will not give rise to large current flows. However, these voltages are often a source of false triggering in prior art devices. For circuit101, when a transient voltage appears on the switched active, R20and C3offer a relatively low impedance path for the resultant current to flow to the switched neutral. The higher the frequency of the transient current, the less impedance that will be offered by C3. If the high frequency voltage across C3increases greatly, then Z5and Z6will also conduct to provide a further low impedance path for the transient current.

The capacitor C2also acts to improve the performance of circuit101with transients. While C3offers a low impedance path for the transient current to prevent it having an impact upon any fault current, C2functions primarily to filter the current flowing internally within circuit101—and in particular the current flowing through R7and R9—to reduce the risk of false triggering of the triacs T1and T2. This capacitor has the effect of shorting to the neutral any high frequency currents that exist on conductor3and which are, as a result, flowing though resistor R19.

The current that flows through R19in the positive half-cycle will also flow through D9, Z7and R7and then to the switched neutral. In the negative half-cycle the current will instead flow through D10, Z8and R9and then to the switched neutral. If the magnitude of this current is greater than 4.5 mA, the voltage across R7, in the positive half-cycle, and R9, in the negative half-cycle, will be sufficient to trigger triacs T2and T1respectively. A triggering of either of these triacs will effective short the lower end of solenoid coil L1to the switched neutral and cause the coil to become energized with the full mains voltage. This will result in the fault signal being generated.

As both the positive and negative half-cycles are independently monitored, the fault signal is able to be provided extremely quickly once a fault condition is sensed. It is enough that only one of triacs T1and T2is switched for the fault signal to be produced.

If the triggering of one of the triacs occurs very late in the half-cycle, it is possible that coil L1will not be energized sufficiently to create the fault signal. But at that time the voltage on the switched active will be low and, hence, any personnel should be at low risk of an electric shock. As most faults occur in both half-cycles, even if a fault is not provided in the first half-cycle, it will in the subsequent half-cycle.

It has been found that circuit101, in combination with MCB17provides an average switching time of less than 10 ms when in use with a 50 Hz 240 VAC supply source. It will be appreciated that a half-cycle for such a supply source is 10 ms. It has also been found that the time between a fault and the provision of a fault signal is no more than about half of the total switching time. That is, the switching time for unit19is less than 5 ms.

If one of the triacs T1or T2were to fail, a fault condition would still result in the other switching and, hence, a fault signal would still be generated. In this instance, it would be thought that the response time of circuit101and the subsequent triggering of MCB will take slightly longer. However, circuit101includes additional components to provide the testing and policing functions, and one of these functions is to regularly test triacs T1and T2. If one of the triacs fails while a fault is present, circuit101operates to trigger the other traic during both half-cycles to compensate for the failed triac. Accordingly, the fault signal generates just as effectively. Additionally, if one triac fails the test and a fault condition is not present, circuit101directly generate a fault signal by triggering the other triac. These functions will be described in further detail below.

After assembly of circuit101, and prior to deployment, a positive DC reference voltage is placed at the junction of C4and R22while R8is laser trimmed until T2triggers. Then, a negative DC reference voltage of the same magnitude is placed at the junction of C4and R22while R12is laser trimmed until T1triggers. The accuracy of the laser trimming is therefore tailored for the specific circuit and contributes to an extremely reliable and repeatable operation of the triacs and, hence, an extremely reliable and repeatable operation of circuit101in providing the fault signal.

Resistor R10has a dual function, one of which is to enable a power supply to the microprocessor U1and U2, and the other is to provide a timing signal to those microprocessors to indicate the zero crossing point of the voltage on the switched active.

R10connects the switched active to the junction of the gates of Q5and Q6. During the positive half-cycle, current will flow through R8and then through two paths defined, on the one hand, by D8and C1/R6, and on the other hand by Z4and Z3. This combination provides a power supply to pin1(VDD) of microprocessor U2. During the negative half-cycle, current will flow through R8and then through two paths defined, on the one hand, by D7and C5/R18, and on the other hand by Z4and Z3. This combination provides a power supply to pin8(VSS) of microprocessor U1.

The voltage at the junction of R10and the gates of Q5and Q6switches those transistors to provide respective signals to pin3of U1and pin2of U2. This signal provides U1and U2with an indication of the zero-crossing point of the voltage of the switched active. This timing indicator is used by the microprocessors, and will be described in more detail below.

The circuitry centred about diodes Z1and Z2is a power supply for providing a ±30 V power rails. These rails are used within circuit101primarily to assist with the policing functions and, particularly, to bias the internal transistor circuits so that the testing is able to occur. For example,

It will be appreciated by those skilled in the art that when a triac, such as T1or T2, is triggered or switched ON—that is, switched to a low-resistive state following the application of a voltage between the gate and the main terminal—the voltage drop across between the main terminals is relatively small. It will also be appreciated that once the current between the main terminals falls below a threshold—as will occur for a zero DC offset mains supply sine wave signal—the triac will turn OFF and there will be, effectively, on open circuit between the main terminals. These characteristics of a triac are used within circuit101to provide part of the policing function. Particularly, the biasing circuitry for the policing function includes transistors Q1, Q2, Q3and Q4. Q1and Q2operate to bias the base and collector of transistor Q8, while Q3and Q4operate to bias the base and collector of Q7.

Microprocessors U1and U2use the zero-crossing signal—as supplied to pin3of U1and pin2of U2—to respectively generate bias signals at pins6that are applied to the bases of Q4and Q2during the positive and negative half-cycles. The bias signals are not applied during every half-cycle, but only once every 2 or 3 seconds. These signals are timed to be late in the respective half-cycles in which they occur, and typically within the last millisecond of the half-cycle. With the bias applied to the relevant transistors, the microprocessors U1and U2, late in the respective half-cycles, trigger respective triacs T1and T1by generating trigger signals at pin7of U1and pin3of U2which are then applied to the gates of T1and T2. These trigger signals, while being sufficient to trigger the respective triacs, are timed for when the resultant current flow through coil L1will be so small that L1will not be energized and a fault signal will not be generated. Notwithstanding, the triggering of a triac will result in the junction of R1and T1/T2being connected to the active neutral, and hence, a voltage drop will appear at the gates of Q5and Q6which will be detected, via resistors R13and R14by U2and U1respectively. If the relevant triac does not trigger, the voltage drop will not appear at the gates of Q5and Q6, and U2and U1will not detect any change.

If a triac is tested to be operating correctly, the microprocessor that conducted that test will communicate the positive result to the other microprocessor by a control sub-circuit formed by R15, R16, R17, R37, C10and the microprocessors themselves. As successive successful test are communicated, microprocessor U1pulses pin2with the result that D11emits a periodic flash.

If, for example, triac T2failed a test, microprocessor U2would not provide a confirmation signal to U1. U2would then progress to administer a further like test to T2at the next scheduled time for such a test. If, after three such tests the result was still negative—in that U1had still not received a confirmation signal via the control sub-circuit—then U2will, via pin3, provide a series of pulses spaced by 3 ms to ensure triac T2is triggered and, if necessary, retriggered. (For the triac will turn OFF once the supply voltage passes into the next half cycle.) If triac T2is operating normally it will provide a low impedance and solenoid L1will quickly become energized. Simultaneously, U1will switch T1ON—through the application of a series of electrical pulses to the gate of T1via C9. The result being that a fault signal is generated as at least T1and likely T1and T2will be ON. During the period of the confirmatory testing—typically about ten seconds—but prior to the fault signal being generated, the rate of flashing of D11will decrease. Once the fault signal has been generated, D11will cease flashing, as circuit101will be isolated from the power source.

Solenoid L1only requires about a quarter cycle of energisation to trigger MCB17. In other embodiments, more sensitive solenoids are used to provide quicker switching times.

The microprocessors also monitor the timing of successive zero-crossing signals and, in an absence of such signals for more than three seconds, cause a fault signal to be generated.

Circuit101has many features that provide for failsafe operation. Some of these features go to internal monitoring, and others to the detection of the fault, and protection of the load circuit to prevent high fault currents even if circuit101fails to correctly function. For example:If either one of the microprocessors fails, there will be no communication between them confirming the successful testing of the triacs, and the other microprocessor will cause a fault signal to be generated within about ten seconds. In the intervening period, the functioning microprocessor will continue to provide protection to the load should a fault occur, as both triacs are able to be controlled to switch (by the relevant microprocessor) in both directions.If either one of triacs T1and T2fails, there will be an absence of full communication between the microprocessors to confirm the successful testing, and the microprocessor controlling the functioning triac will cause a fault signal to be generated within about ten seconds. In the intervening period, the functioning triac microprocessor will continue to provide protection to the load should a fault occur, as the remaining triac is able to be controlled to switch (by the relevant microprocessor) in both directions.In the event the solenoid coil L1fails by going open circuit, a fault signal will generate, as the zero-crossing signal will disappear.In the event the solenoid coil L1fails by shorting, circuit101will not be able to function to provide the fault signal and the MCB or other protection device will not move to isolate the load from the supply. However, during this time, circuit101continues to operate to limit any fault current—that is, the current in conductor3—to less than 8 mA.Detection of a fault condition occurs quickly for monitoring occurs on both the positive and negative half-cycles.The reference for determining a fault condition is a floating conductor3that should be at a low potential relative to the switched neutral. The sentinel unit connects conductor3to the switched neutral and monitors any voltage between the two that gives rise to a current flow of about 5 mA. The use of a zero-reference—that is the voltage and current between conductor3and the switched neutral—allows circuit101to be fast acting and accurate.At power-up, the current limiting functionality of circuit101operates immediately should a fault be present.The microprocessors provide the policing function of circuit101and, should it be found that key components of circuit101are faulty or not correctly operating, a fault signal is provided.If both microprocessors fail, it is only the policing function that will cease. Circuit101will continue to monitor the load circuit and, in the event of a fault, will limit the fault current. (In the above embodiments, the fault current is limited to 8 mA).

Circuit101includes two high voltage protection circuits which are included on the circuit board with the other electrical components. A first of the high voltage protection circuits is defined by a 7 mm diameter varistor V2that extends between the junction of solenoid L1and triacs T1and T2to the switched neutral. Varistor V2is primarily intended to protect triacs T1and T2from damage from high voltage surges.

The second high voltage protection circuit is defined by a 7 mm diameter varistor V3. This varistor is primarily intended to protect transistors Q7and Q8from high voltage surges, by diverting those surges to the switched neutral using R35as a series protection resistor.

For low voltage applications, one or more of the high voltage protection circuits are omitted. In other embodiments, additional or alternative high voltage protection circuits are used. For example, in an embodiment, use is made of a further high voltage protection circuit such as circuit110that is illustrated inFIG. 5. It has been found that when use is made of theFIG. 5protection circuit, in addition to the on-board protection circuits shown inFIG. 2, that circuit101is able to withstand voltage surges of up to 10 kV, administered as an over-voltage test in accordance with AS/NZS 3190-2002 RCD Standard.

The preferred embodiments described above provides for a protected IT EDS. The EDS is a true IT EDS, as an earth connection is not required. This is distinct from a prior art pseudo IT EDS which must include an earth connection or the protection system—typically including one or more RCDs—will not operate, and the prior art EDS will be unprotected.

The preferred embodiment described above also allows a plurality of separately protected load circuits to be supplied from a single isolation transformer. This allows, particularly for large installations, for a reduction in the quantum and cost of the associated infrastructure while increasing the protection available to property and personnel. This advantage, together with other advantages, is described in more detail in an Australian patent application in the name of the present applicant and filed with IP Australia on 19 Dec. 2008 (U.S. patent application Ser. No. 13/140,756).

A further advantage of the preferred embodiment described above is that the sentinel unit continually monitors the load circuit it is associated with and, upon detection of a fault, automatically actuates the associated protection device—which, inFIG. 1is an MCB. That is, there is no requirement for manual monitoring or manual intervention to isolate the load circuit.

FIG. 3is a flow chart illustrating, by way of example, the operation of the software used by processors U1and U2.

FIG. 4provides for unit101a comparison of certain characteristics with two prior art protection devices.

The methodologies described herein are, in one embodiment, performable by one or more processors that accept computer-readable (also called machine-readable) code containing a set of instructions that when executed by one or more of the processors carry out at least one of the methods described herein. Any processor capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken are included. Thus, one example is a typical processing system that includes one or more processors. Each processor may include one or more of a CPU, a graphics processing unit, and a programmable DSP unit. The processing system further may include a memory subsystem including main RAM and/or a static RAM, and/or ROM. A bus subsystem may be included for communicating between the components. The processing system further may be a distributed processing system with processors coupled by a network. If the processing system requires a display, such a display may be included, e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT) display. If manual data entry is required, the processing system also includes an input device such as one or more of an alphanumeric input unit such as a keyboard, a pointing control device such as a mouse, and so forth. The term memory unit as used herein, if clear from the context and unless explicitly stated otherwise, also encompasses a storage system such as a disk drive unit. The processing system in some configurations may include a sound output device, and a network interface device. The memory subsystem thus includes a computer-readable carrier medium that carries computer-readable code (e.g., software) including a set of instructions to cause performing, when executed by one or more processors, one of more of the methods described herein. Note that when the method includes several elements, e.g., several steps, no ordering of such elements is implied, unless specifically stated. The software may reside in the hard disk, or may also reside, completely or at least partially, within the RAM and/or within the processor during execution thereof by the computer system. Thus, the memory and the processor also constitute computer-readable carrier medium carrying computer-readable code.

Furthermore, a computer-readable carrier medium may form, or be included in a computer program product.

In alternative embodiments, the one or more processors operate as a standalone device or may be connected, for example, networked to other processor(s), in a networked deployment, the one or more processors may operate in the capacity of a server or a user machine in server-user network environment, or as a peer machine in a peer-to-peer or distributed network environment. The one or more processors may form a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine.

Thus, one embodiment of each of the methods described herein is in the form of a computer-readable carrier medium carrying a set of instructions, for example, a computer program that is for execution on one or more processors, for example, one or more processors that are part of web server arrangement. Thus, as will be appreciated by those skilled in the art, embodiments of the present invention may be embodied as a method, an apparatus such as a special purpose apparatus, an apparatus such as a data processing system, or a computer-readable carrier medium, for example, a computer program product. The computer-readable carrier medium carries computer readable code including a set of instructions that when executed on one or more processors cause the processor or processors to implement a method. Accordingly, aspects of the present invention may take the form of a method, an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of carrier medium (for example, a computer program product on a computer-readable storage medium) carrying computer-readable program code embodied in the medium.

The software may further be transmitted or received over a network via a network interface device. While the carrier medium is shown in an exemplary embodiment to be a single medium, the term “carrier medium” should be taken to include a single medium or multiple media (for example, a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “carrier medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by one or more of the processors and that cause the one or more processors to perform any one or more of the methodologies of the present invention. A carrier medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical, magnetic disks, and magneto-optical disks. Volatile media includes dynamic memory, such as main memory. Transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise a bus subsystem. Transmission media also may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications. For example, the term “carrier medium” shall accordingly be taken to included, but not be limited to, solid-state memories, a computer product embodied in optical and magnetic media; a medium bearing a propagated signal detectable by at least one processor of one or more processors and representing a set of instructions that, when executed, implement a method; a carrier wave bearing a propagated signal detectable by at least one processor of the one or more processors and representing the set of instructions a propagated signal and representing the set of instructions; and a transmission medium in a network bearing a propagated signal detectable by at least one processor of the one or more processors and representing the set of instructions.

It will be understood that the steps of methods discussed are performed in one embodiment by an appropriate processor (or processors) of a processing (that is, computer) system executing instructions (computer-readable code) stored in storage. It will also be understood that the invention is not limited to any particular implementation or programming technique and that the invention may be implemented using any appropriate techniques for implementing the functionality described herein. The invention is not limited to any particular programming language or operating system.

Similarly, it is to be noticed that the term electrically connected, when used in the claims, should not be interpreted as being limited to direct connections only. The terms “connected” and “coupled”, along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Thus, the scope of the expression a device A electrically connected to a device B should not be limited to devices or systems wherein an output of device A is directly electrically connected to an input of device B. It means that there exists an electrical path between an output of A and an input of B which may be a path including other devices or means. “Connected” may mean that two or more elements are either in direct physical or electrical contact, or that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other.