Semiconductor chip including through electrode, and semiconductor package including the same

A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0159887 filed on Nov. 25, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

This patent document relates to a semiconductor technology, and more particularly, to a semiconductor chip including a through electrode, and a semiconductor package including the semiconductor chip.

2. Related Art

Electronic products require high-volume data processing while their sizes are getting smaller. Accordingly, semiconductor chips used in such electronic products are also required to have a thin thickness and a small size. Further, a semiconductor package in which a plurality of semiconductor chips are embedded has been manufactured.

The plurality of semiconductor chips may be stacked in a vertical direction, and be electrically connected to each other by a through via passing through each semiconductor chip.

SUMMARY

In an embodiment, a semiconductor chip may include: a body portion with a front surface and a rear surface; an insulating layer disposed over the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

In another embodiment, a semiconductor chip may include: a body portion with a front surface and a rear surface; an insulating layer disposed over the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; a metal-containing thin film layer disposed over the insulating layer and connected simultaneously with the pair of through electrodes; and a rear connection electrode disposed over the metal-containing thin film layer and connected to the metal-containing thin film layer, wherein the metal-containing thin film layer includes an undercut that is formed under a sidewall of the rear connection electrode due to the metal-containing thin film layer being recessed, and wherein a width of the rear connection electrode is equal to or greater than a sum of widths of the pair of through electrodes, a distance between the pair of through electrodes, and a width of the undercut.

In another embodiment, a semiconductor package may include: first and second semiconductor chips that are stacked in a vertical direction, and each of the first and second semiconductor chips comprises: a body portion with a front surface and a rear surface; an insulating layer disposed over the rear surface of the body portion; a pair of through electrodes penetrating the body portion and the insulating layer; a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes; a wiring portion disposed over the front surface of the body portion; and a front connection electrode disposed over the wiring portion, wherein the rear connection electrode of the first semiconductor chip is connected to the front connection electrode of the second semiconductor chip, and wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

In the following description of the embodiments, when a parameter is referred to as being “predetermined”, it may be intended to mean that a value of the parameter is determined in advance when the parameter is used in a process or an algorithm. The value of the parameter may be set when the process or the algorithm starts or may be set during a period that the process or the algorithm is executed.

FIG.1is a cross-sectional view illustrating a semiconductor chip according to an embodiment of the present disclosure.

Referring toFIG.1, a semiconductor chip100of the present embodiment may include a body portion110, a wiring portion120, a through electrode130, a rear connection electrode140, a front connection electrode150, and a bonding layer160.

The body portion110may be formed of a semiconductor material, such as silicon or germanium, and may have a front surface111, a rear surface112, and a side surface that connects them to each other. The front surface111of the body portion110may refer to an active surface on which the wiring portion120is disposed, and the rear surface112of the body portion110may refer to a surface that is located on the opposite side of the front surface111.

The wiring portion120may be formed over the front surface111of the body portion110. The wiring portion120may include a circuit/wiring structure electrically connected to the through electrode130. For convenience of description, the circuit/wiring structure is simply illustrated as lines in the wiring portion120, but is not limited thereto. In this case, the circuit/wiring structure may be implemented in various ways based on the type of the semiconductor chip100. For example, when the semiconductor chip100includes volatile memory, such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM), or non-volatile memory, such as NAND flash, RRAM (Resistive RAM), PRAM (Phase-change RAM), MRAM (Magneto-resistive RAM), or FRAM (Ferroelectric RAM), the circuit/wiring structure may include a memory cell array with a plurality of memory cells.

The through electrode130may be formed in the body portion110. The through electrode130may have a pillar shape extending from the front surface111to the rear surface112to penetrate the body portion110. As an example, the through electrode130may be a TSV (Through Silicon Via). The through electrode130may include various conductive materials. As an example, the through electrode130may include a metal, such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co), or a compound of this metal. One end of the through electrode130may be connected to a part of the wiring portion120, and the other end of the through electrode130may be connected to the rear connection electrode140.

In this case, the through electrode130may include a signal through electrode130S that transmits a signal and a power through electrode130P for supplying power. The signal may include various signals that are required for driving the semiconductor chip100. As an example, when the semiconductor chip100includes memory, signals (such as a data input/output signal (DQ), a command/address signal (CA), or a chip selection signal (CS)) may move through the signal through electrode130S. Also, the power may include various levels of power voltages or a ground voltage required that drive the semiconductor chip100. In the present embodiment, one signal through electrode130S and six power through electrodes130P are illustrated, but the present disclosure is not limited thereto, and the number of the signal through electrodes130S and the number of the power through electrodes130P may be varied. In a horizontal direction, that is, in a direction that is parallel to the front surface111and the rear surface112of the body portion110, the width of the through electrodes130may be constant. That is, the width of each signal through electrode130S and the width of each power through electrode130P may be the same. For example, when the through electrode130has a cylindrical shape, the cross-sectional diameter of the signal through electrode130S and the cross-sectional diameter of the power through electrode130P may be substantially the same.

The rear connection electrode140may be formed over the rear surface112of the body portion110. The rear connection electrode140may connect the through electrode130to another component, for example, another semiconductor chip to be located over the rear surface112of the semiconductor chip100. As an example, the rear connection electrode140may include a conductive bump. The rear connection electrode140may include various metal materials, such as copper, nickel, or a combination thereof, and may have a single-layered structure or a multi-layered structure.

The rear connection electrode140may include a signal rear connection electrode140S that is connected to the signal through electrode130S, a power rear connection electrode140P that is connected to the power through electrode130P, and a dummy rear connection electrode140D that is not connected to the through electrode130.

The signal rear connection electrode140S may be formed to overlap and connect with each signal through electrode130S. One signal rear connection electrode140S and one signal through electrodes130S may correspond to each other.

The power rear connection electrode140P may be formed to simultaneously connect with a pair of power through electrodes130P. That is, one power rear connection electrode140P and two power through electrodes130P may correspond to each other. The pair of power through electrodes130P may be spaced apart from each other with a part of the body portion110therebetween.

The dummy rear connection electrode140D may be in an electrically floating state. The dummy rear connection electrode140D may function to maintain process stability in a process of stacking a plurality of semiconductor chips (to be described later) and to improve heat dissipation characteristics in a semiconductor package with the plurality of stacked semiconductor chips. This will be described in more detail in the relevant section. If necessary, the dummy rear connection electrode140D may be omitted.

The front connection electrode150may be formed over the wiring portion120. The front connection electrode150may electrical connect with another component, for example, another semiconductor chip or a substrate to be positioned over the front surface111of the semiconductor chip100. The front connection electrode150may include a conductive bump. The front connection electrode150may include various metal materials, such as copper, nickel, or a combination thereof, and may have a single-layered structure or a multi-layered structure.

The front connection electrode150may be electrically connected to the wiring portion120. Furthermore, the front connection electrode150may be electrically connected to the through electrode130through the wiring portion120. That is, unlike the rear connection electrode140, the front connection electrode150might not directly contact the through electrode130.

The bonding layer160may be formed over a surface of the front connection electrode150, which is located on the opposite side of the surface that is in contact with the wiring portion120. When a plurality of semiconductor chips100are stacked in a vertical direction, that is, in a direction perpendicular to the front surface111and the rear surface112of the body portion110, the bonding layer160may be bonded to the rear connection electrode140. The bonding layer160may include a solder material with a hemispherical shape, a ball shape, or a shape similar thereto. However, the present embodiment is not limited thereto, and the shape and material of the bonding layer160may be variously modified.

In the horizontal direction, the width of the signal rear connection electrode140S, the width of the power rear connection electrode140P, the width of the dummy rear connection electrode140D, and the width of the front connection electrode150are denoted by reference numerals WS, WP, WD, and WF, respectively. The width WS of the signal rear connection electrode140S may be greater than or equal to the width of the signal through electrode130S. The width WS of the signal rear connection electrode140S, the width WD of the dummy rear connection electrode140D, and the width WF of the front connection electrode150may be the same. On the other hand, the width WP of the power rear connection electrode140P may be greater than the width WS of the signal rear connection electrode140S, the width WD of the dummy rear connection electrode140D, and the width WF of the front connection electrode150. This is because the width WP of the power rear connection electrode140P must be large enough to overlap with the pair of power through electrodes130P and a space therebetween, whereas there is no such restriction on the width WS of the signal rear connection electrode140S, the width WD of the dummy rear connection electrode140D, and the width WF of the front connection electrode150. However, the present disclosure is not limited thereto, and the width/size of the connection electrodes140P,140D,140S, and150may be modified in various ways.

Despite the difference in width/size of the signal rear connection electrode140S, the power rear connection electrode140P, and the dummy rear connection electrode140D, the pitch of the rear connection electrodes140, that is, the distance between the center of any one of the rear connection electrodes140and the center of the adjacent rear connection electrode140may be substantially constant. For example, as shown, a pitch P1between two adjacent power rear connection electrodes140P, a pitch P2between the power rear connection electrode140P and the dummy rear connection electrode140D that are adjacent to each other, and a pitch P3between the power rear connection electrode140P and the signal rear connection electrode140S that are adjacent to each other, may have a fixed value. Furthermore, the pitch P4of the front connection electrodes150may also be substantially the same as the pitch of the rear connection electrodes140.

According to the semiconductor chip100described above, because one power rear connection electrode140P is in contact with the pair of power through electrodes130P at the same time, it may be possible to reduce the resistance of the power supply path through the power rear connection electrode140P and the pair of power through electrodes130P. As a result, power may be easily and stably supplied.

FIGS.2A to2Gare cross-sectional views illustrating a method for fabricating a semiconductor chip according to an embodiment of the present disclosure. For convenience of description, these cross-sectional views are shown based on a part of the semiconductor chip ofFIG.1(see A1).

Referring toFIG.2A, a structure with an initial body portion210that has a front surface211and an initial rear surface212and has an initial through electrode230formed therein, a wiring portion220that is disposed over the front surface211of the initial body portion210, and a front connection electrode250and a bonding layer260that are disposed over the wiring portion220, may be formed over a carrier substrate (not shown). This structure may be attached to the carrier substrate by using an adhesive material. The method of forming this structure will be described in more detail below.

First, the initial body portion210with the front surface211and the initial rear surface212may be provided. The initial rear surface212may have a greater distance from the front surface211than the rear surface112ofFIG.1, and accordingly, the initial body portion210may have a greater thickness than the body portion110ofFIG.1.

Subsequently, the initial body portion210may be etched to form a hole213in the initial body portion210. The hole213may be formed to a predetermined depth from the front surface211of the initial body portion210toward the initial rear surface212. The depth of the hole213may be smaller than the thickness of the initial body portion210.

Subsequently, the hole213may be filled with a conductive material to form the initial through electrode230. The initial through electrode230may include an initial power through electrode230P and an initial signal through electrode230S. At this time, a distance DP between a pair of initial power through electrodes230P to be connected to one power rear connection electrode may be determined based on the thickness of the initial insulating layer (see280inFIG.2C) and/or the insulating layer (see280A inFIG.2E). This will be described in more detail in the relevant section.

Subsequently, the wiring portion220may be formed over the front surface211of the initial body portion210in which the initial through electrode230is formed, and then, the front connection electrode250and the bonding layer260may be formed over the wiring portion220. Accordingly, the structure that is disposed over the carrier substrate may be obtained.

Referring toFIG.2B, a portion of the initial body portion210may be removed to form a body portion210A whose thickness is smaller than that of the initial body portion210. That is, a process of thinning the initial body portion210may be performed.

The thinning process may be performed on the initial rear surface212of the initial body portion210. Accordingly, the body portion210A may have the front surface211and a rear surface212A. The distance between the rear surface212A and the front surface211may be shorter than the distance between the initial rear surface212and the front surface211. Further, the thinning process may be performed through grinding, chemical mechanical polishing (CMP), and/or etch-back. Further, the thinning process may be performed so that a part of the initial through electrode230protrudes from the rear surface212A of the body portion210A.

Referring toFIG.2C, an initial insulating layer280may be formed over the rear surface212A of the body portion210A and the part of the initial through electrode230that protrudes from the rear surface212A of the body portion210A.

The initial insulating layer280may be transformed into an insulating layer (see280A inFIG.2E) through a planarization process that will be described later, and this insulating layer may function to protect the semiconductor chip and prevent current leakage due to metal diffusion between the through electrodes. This will be described in more detail in the relevant section.

The initial insulating layer280may be formed by various deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The initial insulating layer280may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, in the present embodiment, the initial insulating layer280may have a single-layered structure, but the present disclosure is not limited thereto. In another embodiment, the initial insulating layer280may have a multi-layered structure.

The initial insulating layer280may be formed to have a substantially uniform thickness along its lower profile. The thickness of the initial insulating layer280is denoted by reference numeral T1. In this case, the distance DP between the pair of initial power through electrodes230P may have a value that is greater than twice the thickness T1of the initial insulating layer280. This is to secure a space in which the initial insulating layer280may be formed between portions of the pair of initial power through electrodes230P, which protrude from the rear surface212A of the body portion210A. This will be described in more detail compared toFIG.2H.

FIG.2His a view for comparison withFIG.2C.FIG.2Hshows a case in which a distance DP′ between the pair of initial power through electrodes230P is shorter than the distance DP shown inFIG.2C, that is, the distance DP′ is less than twice the thickness T1of the initial insulating layer280.

Referring toFIG.2H, when the distance DP′ between the pair of initial power through electrodes230P is relatively narrow, the initial insulating layer280might not be deposited to a desired thickness between the pair of initial power through electrodes230P. This is because the upper portion of the space between the portions of the pair of initial power through electrodes230P, which protrudes over the rear surface212A of the body portion210A, is blocked with an insulating material for forming the initial insulating layer280, before the initial insulating layer280is deposited to a desired thickness, and as a result, an unwanted void V are generated in the initial insulating layer280that is formed in this space.

In this case, when the planarization process (described later) is performed, a problem may occur in which an insulating layer to be formed on the rear surface212A of the body portion210A between a pair of power through electrodes (see230PA inFIG.2E) is absent or is thinner than a desired thickness.

Referring back toFIG.2C, in the present embodiment, in order to solve the problem described inFIG.2H, the distance DP between the pair of initial power through electrodes230P may be set to have a value that is greater than twice the thickness T1of the initial insulating layer280.

Referring toFIG.2D, a sacrificial layer290may be formed over the initial insulating layer280.

The sacrificial layer290may prevent process defects from occurring during the planarization process, which will be described later. If the planarization process is performed on the resultant structure ofFIG.2Cwithout the sacrificial layer290, pressure may be concentrated on the protruding portion of the initial through electrode230, and thus, the protruding portion may break. The broken portion as a conductive material may cause various defects within the semiconductor chip. The sacrificial layer290may prevent concentration of such pressure. The sacrificial layer290may be formed to have a thickness that sufficiently covers the protruding portion of the initial through electrode230.

Referring toFIG.2E, the planarization process may be performed on the resultant structure ofFIG.2D. The planarization process may be performed by a polishing method, such as chemical mechanical polishing.

In this case, the planarization process may be performed until the initial insulating layer280that is formed over the rear surface212A of the body portion210A is exposed. As a result, substantially all of the sacrificial layer290may be removed in the planarization process. In addition, a portion of the initial through electrode230(see A2inFIG.2D), which is positioned above the upper surface of the initial insulating layer280that is formed over the rear surface212A of the body portion210A, may be removed to form a through electrode230A. Further, a portion of the initial insulating layer280, which is formed along the side and upper surfaces of the portion of the initial through electrode230(see A2inFIG.2D), may also be removed to form an insulating layer280A.

As a result, the insulating layer280A may be formed over the rear surface212A of the body portion210A, and the through electrode230A that penetrates the insulating layer280A and the body portion210A may be formed. The through electrode230A may include a signal through electrode230SA and a power through electrode230PA. One end of the through electrode230A may be electrically connected to the wiring portion220as described above, and the other end and/or the upper surface of the through electrode230A may form a flat surface with the upper surface of the insulating layer280A while being exposed from the insulating layer280A.

Meanwhile, the planarization process may be performed by using the upper surface of the initial insulating layer280that is formed over the rear surface212A of the body portion210A as a planarization stop layer, for example, a polishing stop layer. Therefore, during this planarization process, it may be assumed that there is little loss in the initial insulating layer280that is formed over the rear surface212A of the body portion210A, or the loss is negligible even if the loss exists. Accordingly, the thickness of the insulating layer280A is denoted by reference numeral T1that is equal to the thickness of the initial insulating layer280.

Referring toFIG.2F, an initial metal-containing thin film layer292may be formed over the insulating layer280A. The initial metal-containing thin film layer292may include a metal, such as copper (Cu) or titanium (Ti), or a compound of this metal, and may have a single-layered structure or a multi-layered structure. As an example, the initial metal-containing thin film layer292may have a multi-layered structure with a barrier layer and a seed layer that is disposed over the barrier layer. The barrier layer may include a metal or a metal compound, such as Ti, TiW, TiN, or NiV, and the seed layer may include a metal, such as Cu. In this case, the barrier layer may serve to prevent metal diffusion between the through electrodes230A, and the seed layer may function as a seed during subsequent electroplating.

Subsequently, a photoresist pattern294that provides spaces in which a power rear connection electrode240P and a signal rear connection electrode240S are to be formed, may be formed over the initial metal-containing thin film layer292, and then, electroplating may be performed. As a result, the power rear connection electrode240P and the signal rear connection electrode240S may be formed in the spaces that are provided by the photoresist pattern294. The power rear connection electrode240P may be connected to a pair of power through electrodes230PA, and the signal rear connection electrode240S may be connected to one signal through electrode230SA. For reference, although not shown in this figure, a dummy rear connection electrode (see140D ofFIG.1) that is not connected to the through electrode230A may also be formed in this process.

Referring toFIG.2G, after removing the photoresist pattern (294ofFIG.2F), a portion of the initial metal-containing thin film layer292, which is not covered by the power rear connection electrode240P and the signal rear connection electrode240S, may be removed. As a result, a metal-containing thin film layer292A may be formed. The metal-containing thin film layer292A may be disposed under each of the power rear connection electrode240P and the signal rear connection electrode240S, and may be connected to each of the power rear connection electrode240P and the signal rear connection electrode240S. In particular, the metal-containing thin film layer292A under the power rear connection electrode240P may be connected to the pair of power through electrodes230PA at the same time.

In this case, the portion of the initial metal-containing thin film layer292may be removed by an isotropic etching method, such as wet etching. Accordingly, the metal-containing thin film layer292A may have a side surface that is recessed inward in comparison to the side surface of each of the power rear connection electrode240P and the signal rear connection electrode240S. The space that is formed under each of the power rear connection electrode240P and the signal rear connection electrode240S by the recessed side surface of the metal-containing thin film layer292A will be hereinafter referred to as an undercut U of the metal-containing thin film layer292A.

In this case, the width WP of the power rear connection electrode240P may have a value that is equal to or greater than the sum of the widths WP′ of the pair of power through electrodes230PA, the distance DP between the pair of power through electrodes230PA, and the width WU of the undercut U.

Meanwhile, even if the undercut U is formed, the pair of power through electrodes230PA might not be exposed through the undercut U. The upper surfaces of the pair of power through electrodes230PA may be completely covered by the metal-containing thin film layer292A. To this end, the side surface of the metal-containing thin film layer292A may be located farther from the center of the power rear connection electrode240P than the side surfaces of each of the pair of power through electrodes230PA.

As a result, a semiconductor chip as shown inFIG.2Gmay be fabricated. The semiconductor chip ofFIG.2Gmay be substantially the same as the semiconductor chip ofFIG.1. In the semiconductor chip ofFIG.2G, the body portion210A, the wiring portion220, the through electrode230A with the power through electrode230PA and the signal through electrode230SA, the power rear connection electrode240P, the signal rear connection electrode240S, the front connection electrode250, and the bonding layer260may correspond to the body portion110, the wiring portion120, the through electrode130with the power through electrode130P and the signal through electrode130S, the power rear connection electrode140P, the signal rear connection electrode140S, the front connection electrode150, and the bonding layer160of the semiconductor chip100ofFIG.1, respectively.

Further, the semiconductor chip ofFIG.2Gmay further include the insulating layer280A that is disposed over the rear surface212A of the body portion210A. The through electrode230A may be formed to penetrate the body portion210A and the insulating layer280A, and the power rear connection electrode240P and the signal rear connection electrode240S may be formed over the insulating layer280A to be connected to the through electrode230A. Further, the metal-containing thin film layer292A with the undercut U may be further interposed between the power through electrode230PA and the power rear connection electrode240P, and between the signal through electrode230SA and the signal rear connection electrode240S.

Here, the distance DP between the pair of power through electrodes230PA may be greater than twice the thickness T1of the insulating layer280A. In addition, the width WP of the power rear connection electrode240P that is connected to the pair of power through electrodes230PA may be equal to or greater than the sum of the widths WP′ of the pair of power through electrodes230PA, the distance DP between the pair of power through electrodes230PA, and the width WU of the undercut U.

A detailed description of the components shown inFIG.2Ghas already been described in the manufacturing method, and thus will be omitted.

FIG.3is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure. For convenience of description, this cross-sectional view is shown based on an enlarged view of the semiconductor chip ofFIG.2G. Hereinafter, a description will be made focusing on the differences fromFIG.2G.

Referring toFIG.3, in a semiconductor chip of the present embodiment, a power through electrode330PA may include a conductive pillar332PA and a spacer insulating layer334PA that surround the sidewall of the conductive pillar332PA. The conductive pillar332PA may include a metal, such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co), or a compound of this metal. The spacer insulating layer334PA may be disposed between the conductive pillar332PA and a body portion310A to insulate them from each other. The spacer insulating layer334PA may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. Here, the width WP′ of the power through electrode330PA may mean the sum of the width of the conductive pillar332PA and the width of the spacer insulating layer334PA.

Reference numerals380A,392A, and340P, which are not described, may denote an insulating layer, a metal-containing thin film layer, and a power rear connection electrode, respectively.

Further, although not shown, a signal through electrode may also have a structure in which a spacer insulating layer surrounds a sidewall of a conductive pillar.

FIG.4is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure. For convenience of description, this cross-sectional view is shown based on an enlarged view of the semiconductor chip ofFIG.2G. Hereinafter, a description will be made focusing on differences fromFIG.2G.

Referring toFIG.4, in a semiconductor chip of the present embodiment, the thickness T2of an insulating layer480A between a pair of power through electrodes430PA may be smaller than the thickness T1of the insulating layer480A that is outside of the pair of power through electrodes430PA. The reason is as follows.

The above-described planarization process (refer toFIG.2E) may be performed to substantially maintain the thickness of the initial insulating layer, that is, to stop polishing when the upper surface of the initial insulating layer is exposed. In this case, in the process of exposing the whole upper surface of the initial insulating layer that is outside of the pair of power through electrodes430PA with a relatively large area, the initial insulating layer between the pair of power through electrodes430PA with a relatively narrow area may be over-polished. As a result, the insulating layer480A with a thickness difference as illustrated may be obtained.

The metal-containing thin film layer292A may be formed over the insulating layer480A along the profile of the insulating layer480A. Accordingly, a step height may occur in the metal-containing thin film layer292A. That is, the metal-containing thin film layer292A may have relatively low upper/lower surfaces between the pair of power through electrodes430PA, while having relatively high upper/lower surfaces in the remaining regions.

Reference numerals410A and440P, which are not described, may denote a body portion and a power rear connection electrode, respectively.

FIG.5is a cross-sectional view illustrating a semiconductor chip according to another embodiment of the present disclosure. For convenience of description, this cross-sectional view is shown based on an enlarged view of the semiconductor chip ofFIG.2G. Hereinafter, a description will be made focusing on differences fromFIG.2G.

Referring toFIG.5, in a semiconductor chip of the present embodiment, an insulating layer580A may have a multi-layered structure. For example, the insulating layer580A may have a stacked structure of a first insulating layer582A and a second insulating layer584A.

In this case, the first insulating layer582A may be formed along a rear surface of a body portion510A and a side surface of a portion of a power through electrode530PA, which protrudes from the rear surface of the body portion510A. The second insulating layer584A may be formed to fill a space that is defined by the first insulating layer582A. Accordingly, the first insulating layer582A may be interposed between the second insulating layer584A and the power through electrode530PA, and between the second insulating layer584A and the rear surface of the body portion510A.

The first insulating layer582A and the second insulating layer584A may be formed of different insulating materials. For example, when the first insulating layer582A is silicon nitride, the second insulating layer584A may be silicon oxide, and vice versa.

Reference numeral550P, which is not described, may denote a power rear connection electrode.

FIGS.6A and6Bare cross-sectional views illustrating a semiconductor chip according to another embodiment of the present disclosure. For convenience of description, this cross-sectional view is shown based on an enlarged view of the semiconductor chip ofFIG.2G. Hereinafter, a description will be made focusing on differences fromFIG.2G.

Referring toFIG.6A, in a semiconductor chip of the present embodiment, the positions of the metal-containing thin film layer692A and the power rear connection electrode640P may be moved. Even in this case, the power rear connection electrode640P may be connected to a pair of power through electrodes630PA at the same time, and the pair of power through electrodes630PA might not be exposed. The metal-containing thin film layer692A may cover the upper surfaces of the pair of power through electrodes630PA to avoid unnecessary exposure, which prevents metal ions from moving through them, resulting in an electrical short.

To this end, even if the metal-containing thin film layer692A is moved, it may move only until one sidewall of one of the pair of power through electrodes630PA and one sidewall of the metal-containing thin film layer692A are aligned. Otherwise, at least a portion of the power through electrode630PA may be unnecessarily exposed, or the power rear connection electrode640P might not be simultaneously connected to the pair of power through electrode630PA.

Referring toFIG.6B, in a semiconductor chip of the present embodiment, the power through electrode630PA may include a conductive pillar632PA and a spacer insulating layer634PA that surround the sidewall of the conductive pillar632PA.

In this case, the metal-containing thin film layer692A may move until one sidewall of the conductive pillar632PA and one sidewall of the metal-containing thin film layer692A are aligned. The upper surface of the spacer insulating layer634PA may be exposed by the metal-containing thin film layer692A.

The semiconductor chips, described above, may be stacked in a vertical direction to be implemented as a single semiconductor package. This will be exemplarily described with reference toFIG.7.

FIG.7is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. The semiconductor package may include a plurality of semiconductor chips that are stacked in a vertical direction. Each of the plurality of semiconductor chips may include substantially the same semiconductor chip as one of the semiconductor chips of the above-described embodiments.

Referring toFIG.7, a semiconductor package of the present embodiment may include a base layer700and a plurality of semiconductor chips710,720,730,740, and750that are stacked over the base layer700in the vertical direction. In the present embodiment, five semiconductor chips710,720,730,740, and750are stacked, but the present disclosure is not limited thereto, and the number of semiconductor chips that are stacked in the vertical direction may be modified in various ways. For convenience of description, the five semiconductor chips710,720,730,740, and750will be referred to as a first semiconductor chip710, a second semiconductor chip720, a third semiconductor chip730, a fourth semiconductor chip740, and a fifth semiconductor chip750based on the distance from the base layer700.

The base layer700may be a layer with a circuit and/or wiring structure in order to connect a stacked structure of the plurality of semiconductor chips710,720,730,740, and750to an external component. For example, the base layer700may include a substrate, such as a printed circuit board (PCB), an interposer, a redistribution layer, or the like. Alternatively, when the plurality of semiconductor chips710,720,730,740, and750are memory chips, the base layer700may be a semiconductor chip with a logic circuit supporting operations of these memory chips, for example, a reading operation of reading data from the memory chips or a writing operation of writing data to the memory chips.

The base layer700may have an upper surface on which the plurality of semiconductor chips710,720,730,740, and750are disposed, and a lower surface on which an external connection terminal780for connecting the semiconductor package to an external component is disposed while being located on the opposite side of the upper surface.

Each of the first to fourth semiconductor chips710,720,730, and740, except for the fifth semiconductor chip750that is positioned at the uppermost portion of the first to fifth semiconductor chips710,720,730,740, and750, may be substantially the same as one of the semiconductor chips of the above-described embodiments.

That is, the first semiconductor chip710may include a body portion711with front and rear surfaces, a wiring portion712that is disposed over the front surface of the body portion711, a through electrode713that penetrates the body portion711, a rear connection electrode714that is disposed over the rear surface of the body portion711and connected to the through electrode713, a front connection electrode715that is disposed over the wiring portion712, and a bonding layer716that is disposed over the front connection electrode715. The through electrode713may include a signal through electrode713S and a power through electrode713P. The rear connection electrode714may include a signal rear connection electrode714S, a power rear connection electrode714P, and a dummy rear connection electrode714D.

The second semiconductor chip720may include a body portion721with front and rear surfaces, a wiring portion722that is disposed over the front surface of the body portion721, a through electrode723that penetrates the body portion721, a rear connection electrode724that is disposed over the rear surface of the body portion721and connected to the through electrode723, a front connection electrode725that is disposed over the wiring portion722, and a bonding layer726that is disposed over the front connection electrode725. The through electrode723may include a signal through electrode723S and a power through electrode723P. The rear connection electrode724may include a signal rear connection electrode724S, a power rear connection electrode724P, and a dummy rear connection electrode724D. The bonding layer726may be bonded to the rear connection electrode714of the first semiconductor chip710.

Because each of the third semiconductor chip730and the fourth semiconductor chip740has the same structure as the second semiconductor chip720, detailed descriptions thereof will be omitted. The third semiconductor chip730may include a body portion731, a wiring portion732, a through electrode733with a signal through electrode733S and a power through electrode733P, a rear connection electrode734with a signal rear connection electrode734S, a power rear connection electrode734P, and a dummy rear connection electrode734D, a front connection electrode735, and a bonding layer736. The fourth semiconductor chip740may include a body portion741, a wiring portion742, a through electrode743with a signal through electrode743S and a power through electrode743P, a rear connection electrode744with a signal rear connection electrode744S, a power rear connection electrode744P, and a dummy rear connection electrode744D, a front connection electrode745, and a bonding layer746.

Because the fifth semiconductor chip750is located at the uppermost portion, it might not include a through electrode and a rear connection electrode. That is, as shown, the fifth semiconductor chip750may include a body portion751with front and rear surfaces, a wiring portion752that is disposed over the front surface of the body portion751, a front connection electrode755that is disposed over the wiring portion752, and a bonding layer756that is disposed over the front connection electrode755.

In the present embodiment, the front connection electrodes715,725,735,745, and755and the rear connection electrodes714,724,734, and744in the first to fifth semiconductor chips710,720,730,740, and750may have the same size. However, as opposed to what is shown, the sizes of the front connection electrodes715,725,735,745, and755and the rear connection electrodes714,724,734, and744may be adjusted similarly toFIG.1.

Spaces between the first semiconductor chip710and the base layer700, between the first semiconductor chip710and the second semiconductor chip720, between the second semiconductor chip720and the third semiconductor chip730, between the third semiconductor chip730and the fourth semiconductor chip740, and between the fourth semiconductor chip740and the fifth semiconductor chip750, may be filled with a filling material760. The filling material760may be formed by flowing an underfill material into the spaces through a capillary phenomenon and then curing.

Further, the base layer700and the first to fifth semiconductor chips710,720,730,740, and750may be surrounded by a molding layer770. That is, the molding layer770may be formed to cover the first to fifth semiconductor chips710,720,730,740, and750over the upper surface of the base layer700. The molding layer770may include various molding materials, such as EMC (Epoxy Mold Compound). As an example, when the filling material760is omitted, the molding layer770may be formed to fill the spaces between the first semiconductor chip710and the base layer700, between the first semiconductor chip710and the second semiconductor chip720, between the second semiconductor chip720and the third semiconductor chip730, between the third semiconductor chip730and the fourth semiconductor chip740, and between the fourth semiconductor chip740and the fifth semiconductor chip750.

According to the semiconductor package of the present embodiment, a highly integrated semiconductor package may be implemented. In addition, it may be easy to supply power to the plurality of semiconductor chips710,720,730,740, and750stacked in the vertical direction.

According to the above embodiments of the present disclosure, it may be possible to provide a semiconductor chip with a through electrode, and a semiconductor package with the semiconductor chip, which are capable of enhancing operation characteristics and improving the process margins.

FIG.8shows a block diagram illustrating an electronic system including a memory card7800employing at least one of the semiconductor packages according to the embodiments. The memory card7800includes a memory7810, such as a nonvolatile memory device, and a memory controller7820. The memory7810and the memory controller7820may store data or read out the stored data. At least one of the memory7810and the memory controller7820may include at least one of the semiconductor packages according to described embodiments.

The memory7810may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG.9shows a block diagram illustrating an electronic system8710including at least one of the semiconductor packages according to described embodiments. The electronic system8710may include a controller8711, an input/output device8712, and a memory8713. The controller8711, the input/output device8712, and the memory8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711or the memory8713may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen and so forth. The memory8713is a device for storing data. The memory8713may store data and/or commands to be executed by the controller8711, and the like.

The memory8713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. For example, a flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system8710represents equipment capable of performing wireless communication, the electronic system8710may be used in a communication system using a technique of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband Internet).

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims.