APPLICATION MERGING SYSTEM FOR MULTIPLE PLATFORMS FPGA OF A SAME SERIES

Provided is a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, which is used in a testing or manufacturing system comprising an adapter and at least two platforms. The FPGA application merging system comprises: at least two functional modules corresponding to the at least two platforms respectively; an IO selector connected to the at least two functional modules respectively, configured to select one of the at least two functional modules adaptively; and an IO attribute controller connected to the IO selector, configured to select an attribute in accordance with the selected functional module, wherein each IO has a three-state logic attribute. The FPGA application merging system may significantly reduce the cost of the FPGA version in later development, maintenance, storage, upgrading and so on, mitigate the difficulty of storage, loading and other operations on the board, and significantly increase the operation efficiency.

DETAILED DESCRIPTION OF INVENTION

Hereinbelow, implementation of the present invention will be described with reference to specific embodiments, and people skilled in the art can readily appreciate other advantages and efficacies of the present invention based on what disclosed in this specification. The present invention may further be implemented or applied in other different embodiments, and details in this specification may also be modified or changed according to different viewpoints and applications without departing from the spirit of the present invention.

Refer to the attached drawings. It shall be appreciated that, the attached drawings in this embodiment are only intended to illustrate the basic concept of the present invention, so the attached drawings only have components related to the present invention shown therein but are not depicted according to the numbers, shapes and dimensions of components in actual implementation. In actual implementation of the present invention, the forms, numbers and proportions of the components may be changed arbitrarily, and arrangement of the components may also be more complex.

Hereinbelow, the present invention will be described in detail with reference to the attached drawings and embodiments thereof.

The FPGA application merging system for multiple platforms of a same series is used in a testing or manufacturing system comprising an adapter1and at least two platforms2. The FPGA application merging system11for multiple platforms of a same series is embedded in the adapter1. In an application scene of the FPGA application merging system11as shown inFIG. 1, a platform21, a platform22. . . , a platform2Nrepresent different platforms, and the N platforms use the same devices in terms of CPUs, FPGAs and so on. The conventional solution for reducing the cost in hardware is to place general-purpose devices into a same adapter and insert the adapter into different platforms2via a slot. The IO of the FPGA or the CPU on the adapter1may control or access devices on a platform through the slot. However, in the conventional solution, when the adapter1is inserted in the different platforms2, different FPGA images need to be loaded respectively. Through use of the FPGA application merging system for multiple platforms of a same series in accordance with this embodiment, the adapter1may be directly inserted into the different platforms2, and an IO pin is adaptively configured through the FPGA to match with different platform designs.

The FPGA application merging system for multiple platforms of a same series in accordance with the present invention merges the FPGA designs using different platforms into a same image. When there is a need to develop multiple platforms in which a same FPGA is suitable for use, the operation efficiency may be increased significantly.

This embodiment provides an FPGA application merging system11for multiple platforms of a same series. As shown inFIG. 2, the FPGA application merging system11for multiple platforms of a same series comprises: N functional modules111corresponding to the platform21, the platform22. . . , the platform2Nrespectively; an IO selector112connected to the N functional modules111respectively, being configured to select one of the N functional modules111adaptively, wherein the function (e.g., the function of operating an external EROM, the function of reading an external sensor, etc.) running on each of the functional modules is set according to a user's needs; an IO attribute controller113connected to the IO selector112, being configured to select an attribute of an IO in accordance with the selected functional module111, wherein the attribute of the IO means that each IO has a three-state logic attribute, i.e., an actual IO pin (not shown) of the FPGA is configured according to a pin attribute of the selected functional module111so that the FPGA application merging system11for multiple platforms of a same series is embedded into the adapter1; and an IO pin (not shown) connected to the FPGA application merging system11for multiple platforms of a same series, being configured to embed the FPGA application merging system11for multiple platforms of a same series into the adapter1. Actually, the FPGA application merging system11for multiple platforms of a same series utilizes a two-stage structure to control the IO; and in order to enable the control of the IO to respond as soon as possible, hardware connection is adopted for the FPGA to directly read states of the platforms. For example, when the FPGA application merging system11for multiple platforms of a same series reads the platform21, the IO selector112at the first stage maps the IO configuration file of the first functional module111to the IO of the FPGA, and then the IO attribute controller113at the second stage configures the input or output attributes of each IO in accordance with the first functional module111. The IO attribute controller113at the second stage comprises a programmable input output block (IOB)1131. The IO attribute controller113requires use of an attribute of the general-purpose IO (GPIO) ports of the FPGA; i.e., each IO actually has a three-state logic attribute, and may be configured in real time into an input state, an output state, or a high impedance state. As shown inFIG. 3, taking an IO module of the Virtex6 FPGA of the Xilinx Company as an example for the programmable IOB1131, the IO module comprises a three-state logic control port, an output port, an input port, an output driver, an input driver, and a difference input port. When a signal level at the three-state logic control port is at a low level, the IO is at an output state, and a signal is transmitted to a pin of an external device from the interior of the FPGA. When the signal level at the three-state logic control port is at a high level, the IO is at a high impedance state, and an external signal may directly enter into the FPGA application merging system11for multiple platforms of a same series via the pin. Therefore, the IO attribute controller113essentially controls the three-state logic control port correspondingly according to a serial number of a platform so that the corresponding attribute may be configured adaptively by the IO.

From the viewpoint of different platforms, after the FPGA application merging system for multiple platforms of a same series identifies a specific platform and activates a corresponding function to the platform, it adapts a single functional module to the current platform, as shown inFIG. 4. This has no difference from the solution in which a plurality of FPGA application merging systems for multiple platforms of a same series are designed respectively.

The FPGA application merging system for multiple platforms of a same series in accordance with this embodiment is relatively complex in early architecture design as compared to the conventional solution in which a single mirror corresponds to a single platform, but is not increased in workload as compared to the conventional solution in which a plurality of versions are designed respectively. After the early design, advantages of this system are increased significantly. When there is a need to achieve a new characteristic of this system, it is sufficient to modify a set of codes if this characteristic is shared by the individual platforms, and this can significantly reduce the workload. However, in the conventional solution, multiple sets of codes need to be transplanted, which is very likely to cause errors. When there is a need to modify a code during maintenance of this system, the workload can also be significantly reduced if the modified part is shared by the individual platforms. For loading on the board, this system only needs to allot a storage space to a set of images without the worry of damage caused to the hardware due to mix-up of storage versions, and this can significantly reduce the cost of the hardware. Moreover, this system is adapted by the FPGA without the need of intervening in the loading process by software. The benefits of this system may be shown more clearly in Table 1.

TABLE 1Comparison between the FPGA application merging system for multipleplatforms of a same series and the conventional solutionCharacteristicsConventional solutionPresent inventionEarly designSimpleRelatively difficultCharacteristic superadditionDifficultSimpleVersion controlDifficultSimpleLater maintenanceDifficultSimpleStorage costHighLowSoftware influenceYesNo

According to the above descriptions, the present invention effectively overcomes the various shortcomings in the prior art, and is of a high industrial value.

The embodiments described above are only provided to illustrate the principles and efficacy of the present invention but not to limit the present invention. Modifications or changes may be made by those skilled in the art without departing from the spirits and scope of the present invention. Therefore, all equivalent modifications and changes made by those of ordinary skill in the art without departing from the spirits and technical concepts of the present invention shall also be covered within the scope of the claims.