Bi-directional ESD protection circuit

An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

TECHNICAL FIELD

This invention relates to integrated circuits, and more specifically relates to bi-directional electrostatic discharge (ESD) protection circuits.

BACKGROUND

As semiconductor technology has constantly been improving, the use of field effect transistors (FETs) has become more prevalent in all facets of computer and communications technology. This technological improvement has allowed for faster operation and more compact arrangement of FETs within integrated circuit (IC) chips. IC chips are widely used in all electronic equipment, including equipment that is manufactured and operated in harsh environments. However, such harsh environments increase the likelihood of exposure of IC chips to high-voltage electrostatic discharge (ESD) strikes, to which IC chips are highly vulnerable. The high current that results from ESD strikes breaks down the internal semiconductor material of the FETs, resulting in damage to the IC chip. The vulnerability of IC chips to ESD strikes has created an important need for ESD protection circuits.

It is known in the art to use a silicon-controlled rectifier (SCR) circuit to protect an IC chip from ESD strikes. A SCR circuit utilizes two bipolar junction transistors (BJTs), one NPN type and one PNP type, coupled together. The two BJTs are operative, upon being triggered by an ESD strike, to shunt current resulting from the ESD strike (e.g., to ground), thus creating a path away from the more delicate semiconductor material and saving the FET, and thus the IC chip, from damage. SCR circuits are now commonly used in many electronic devices for this ESD protective purpose. However, SCR circuits are bulky and are typically configured external to the IC chip that they are intended to protect.

SUMMARY

One aspect of the present invention relates to an electrostatic discharge device for protecting an input or output terminal of a circuit. The device comprises two transistors, each with an integral silicon-controlled rectifier (SCR). The first transistor is coupled between an input/output (I/O) terminal of the circuit and a node. The second transistor is coupled between the node and the negative terminal of the supply voltage (e.g., ground). The transistors are situated opposite one another, such that their drain terminals share a common node.

When a positive electrostatic discharge (ESD) strike occurs, the first transistor acts as a diode coupled transistor, passing current from its source to its drain through a forward biased integral body diode. The voltage of the common drain node will increase relative to the source of the second transistor until it reaches a level sufficient to trigger the integral SCR of the second transistor. The integral SCR of the second transistor will then clamp the voltage, allowing the current to pass through the second transistor to the negative voltage supply terminal, thus mitigating ESD damage.

When a negative ESD strike occurs, the second transistor acts as a diode coupled transistor, passing current from its source to its drain through a forward biased integral body diode. The voltage of the common drain node will increase relative to the source of the first transistor until it reaches a level sufficient to trigger the integral SCR of the first transistor. The integral SCR of the first transistor will then clamp the voltage, allowing the current to pass through the first transistor to the I/O terminal, thus mitigating ESD damage.

Another aspect of the present invention relates to a communication system having integral ESD protection. Similar to the first aspect described above, this aspect comprises at least one transistor having an integral SCR. The transistor is configured as a communication driver, and the circuit further comprises a buffer that receives a communication signal that is provided to the gate of the communication driver transistor. The circuit provides positive ESD strike protection in the same manner as described above. Further, it can be appreciated that, with the addition of another transistor configured with its drain sharing a node with the drain of the communication driver transistor, the circuit will also provide negative ESD strike protection.

DETAILED DESCRIPTION

The present invention relates to an ESD device (e.g., a circuit) that is capable of bi-directional electrostatic discharge (ESD) strike protection. The ESD device comprises at least one transistor with an integral silicon-controlled rectifier (SCR). In one embodiment, the ESD device comprises two such transistors, each acting as diode coupled transistors, such that each contains an integral body diode capable of forward and reverse bias. When the circuit experiences an ESD event, one of the transistors will pass current through a forward bias of one of the transistors while the other triggers the integral SCR to clamp the high ESD voltage, thus shunting the current and protecting the circuit. By employing two oppositely opposed transistors, the circuit can act bi-directionally, such that it will protect the circuit from both a positive and a negative ESD strike.

In one embodiment of the present invention, the ESD device employs laterally-diffused-metal-oxide-semiconductor-field-effect transistors (LDMOSFET). It can be appreciated, however, that any suitable transistor with an integral SCR can be used to construct the present invention. Parasitic bipolar transistors are inherent in the design of certain LDMOS transistors due to the combination and arrangement of differently doped P-type and N-type semiconductor wells. By arranging these wells in a certain way, the parasitic bipolar transistors can be formed in such a way as to create an integral SCR within the structure of the transistor. In addition, due to the arrangement of the P-type and N-type wells, PN junctions that act as parasitic body and substrate diodes are formed within the integral structure of the LDMOS transistor. From the foregoing description, it can thus be appreciated that, when arranged on a common substrate, LDMOS transistors can be situated so as to provide ESD protection within an integrated circuit (IC).

FIG. 1illustrates a dual diode configured DMOS structure10for bi-directional ESD strike protection, in accordance with an aspect of the invention.FIG. 1shows two N-type DMOS transistors, M1and M2, situated opposite one another such that the drain terminals of each transistor share a common node12. It should be noted that, in this particular configuration, the gate terminal of transistor M1has been shorted to the source terminal of transistor M1, and the gate terminal of transistor M2has been shorted to the source terminal of transistor M2. The result of the source/gate terminal short circuits is that the DMOS transistors will never operate in a normal bias condition (e.g., the transistor will always operate in the cutoff region). The common source/gate terminal of transistor M1shares a node14with the input/output (I/O) pad terminal, and the common source/gate terminal of transistor M2shares a node16with the negative supply voltage, shown inFIG. 1as ground. The circuit also contains a pull-up resistor R1that separates the circuit from a positive voltage power supply Vcc.

When a positive ESD event occurs at the I/O Pad Terminal, the source/gate terminal of transistor M1at node14is subjected to the high potential of the ESD strike relative to the common drain terminal12. Transistor M1responds by passing current from its source to the drain node12through a forward biasing action of its integral body diode (not shown). As the current flows into the common drain node12of transistors M1and M2, the voltage at the common drain node12increases. When the voltage at node12increases to a critical point relative to the negative voltage source at node16, at a voltage of perhaps 50 volts or greater, the integral SCR (not shown) of transistor M2triggers. Upon triggering of the integral SCR of transistor M2, a current path through transistor M2is created, thus clamping the voltage at common drain node12and shunting the current to the negative voltage source, shown as ground inFIG. 1. By clamping the voltage resulting from the positive ESD event, and shunting the resultant current, the circuit ofFIG. 1can be used to protect other associated circuitry from damage caused by the positive ESD event.

When a negative ESD event occurs at the I/O Pad Terminal, the source/gate terminal of transistor M1at node14is subjected to the negative potential of the ESD strike relative to the negative voltage source. Transistor M2responds by passing current from its source at the negative supply voltage, shown as grounded inFIG. 1, to the common drain node12through a forward biasing action of its integral body diode (not shown). In addition, transistor M1will also pass current from the negative voltage source to the common drain node12by a forward bias action of an integral substrate diode (not shown). As the current flows into the common drain node12of transistors M1and M2, the voltage at the common drain node12increases. When the voltage at node14becomes sufficiently negative relative to the common drain node12, at a voltage of perhaps −50 volts or less, the integral SCR (not shown) of transistor M1triggers. Upon triggering of the integral SCR of transistor M1, a current path through transistor M1is created, thus clamping the negative voltage at common drain node12and shunting the current to the I/O Pad Terminal. By clamping the voltage resulting from the negative ESD event, and shunting the resultant current, the circuit ofFIG. 1can be used to protect other associated circuitry from damage caused by the negative ESD event. Therefore, the circuit ofFIG. 1provides bi-directional ESD protection.

FIG. 2illustrates the circuit ofFIG. 1and further incorporates the parasitic diodes, thus displaying the current paths through the diodes as discussed in the above described operation of the ESD protective circuit. Diode22as shown inFIG. 2is the parasitic body diode of transistor M1, and is arranged with its anode connected to node14and its cathode connected to node12. Diode24is the parasitic body diode of transistor M2, and is arranged with its anode connected to node16and its cathode connected to node12. Diode26is the parasitic substrate diode of transistor M1, and is arranged parallel with the body diode24of transistor M2with its anode connected to node16and its cathode connected to node12.

FIG. 3shows a cross-sectional view of a generally racetrack-shaped (as indicated by the symmetry about the source terminal52) N-type LDMOS transistor50in accordance with an aspect of the invention. It should be appreciated that, although this embodiment details the present invention using a generally oval-shaped N-type LDMOS transistor, any type of suitable transistor known in the art and capable of achieving the desired parasitic effects would suffice.FIG. 3details the configuration of the particular semiconductor P-type and N-type doped regions that create the integral parasitic diodes and SCR that achieve the integral ESD protection of the present invention.

The LDMOS transistor50ofFIG. 3comprises a source terminal52, a drain terminal54, and a gate terminal56. The transistor may also contain one or more field-oxide regions58dividing the respective terminals, and the gate terminal56may be separated from the doped regions by an oxide layer60. Beneath the drain terminal54, the transistor50further comprises at least one each of a P+ anode73and an N+ anode72. The configuration depicted inFIG. 3contains an additional P+ anode70. The doped regions beneath the anodes and other transistor terminals may comprise a number of layers, including N-region62and P-region64, which are conductively coupled to the source terminal52, and the N-well66, which is conductively coupled to the drain terminal54. At the bottom of the transistor50is the P-substrate68, which may be grounded as demonstrated inFIG. 3.

The junctions of the doped regions as shown in the LDMOS transistor50ofFIG. 3are what enable the parasitic effects of the transistor. These parasitic effects are what create a body diode74, a substrate diode76, and a SCR78. Body diode74is formed by the PN junction80, with an anode at P-region64and a cathode at N-well66. Likewise, substrate diode76is formed by the PN junction82, with an anode at P-substrate68and a cathode at N-well66. The integral SCR78is formed from the PNPN junction of P+ anode73, N-well66, P-region64, and N-region62. Integral SCR78is shown inFIG. 3as an electrically coupled pair of bipolar junction transistors (BJTs) superimposed on the body of the LDMOS transistor50with its electrical terminals located to form a SCR.

Referring back toFIG. 2, when a positive ESD event occurs at the I/O Pad Terminal, the source/gate terminal of transistor M1at node14is subjected to the high potential of the ESD strike relative to the common drain terminal12. Transistor M1responds by passing current through the forward biasing of parasitic body diode22. It should be appreciated that body diode24of transistor M2may also reverse bias in response to the positive ESD event. As the current flows into the common drain node12of transistors M1and M2, the voltage at the common drain node12increases. When the voltage at node12increases to a critical point relative to the negative voltage source at node16, at a voltage of perhaps 50 volts or greater, the integral SCR (not shown) of transistor M2triggers. Upon triggering of the integral SCR of transistor M2, a current path through transistor M2is created, thus clamping the voltage at common drain node12and shunting the current to the negative voltage source, shown as ground inFIG. 2.

When a negative ESD event occurs at the I/O Pad Terminal, the source/gate terminal of transistor M1at node14is subjected to the negative potential of the ESD strike relative to the negative voltage source. Transistor M2responds by passing current from the negative voltage source, shown as grounded inFIG. 1, through the forward biasing of parasitic body diode24. In addition, transistor M1will also pass current from the negative voltage source through the forward biasing of parasitic substrate diode26. It should be appreciated that body diode22of transistor M1may also reverse bias in response to the negative ESD event. As the current flows into the common drain node12of transistors M1and M2, the voltage at the common drain node12increases. When the voltage at node14becomes sufficiently negative relative to the common drain node12, at a voltage of perhaps −50 volts or less, the integral SCR (not shown) of transistor M1triggers. Upon triggering of the integral SCR of transistor M1, a current path through transistor M1is created, thus clamping the negative voltage at common drain node12and shunting the current to the I/O Pad Terminal.

FIG. 4illustrates a communication driver circuit100with bi-directional ESD protection in accordance with another aspect of the present invention.FIG. 4shows three N-type DMOS transistors, M3, M4, and M5, with M3situated opposite M4and M5such that the drain terminals of each transistor share a common node102. It should be noted that, in this configuration, the gate terminals of transistors M3and M4have been shorted to their respective source terminals. The result of the source/gate terminal short circuits is that transistors M3and M4will never operate in a normal bias condition (e.g., the transistor will always operate in the cutoff region). The common source/gate terminal of transistor M3shares a node104with the input/output (I/O) pad terminal, and the common source/gate terminal of transistor M4shares a node106with the negative supply voltage, shown inFIG. 4as ground. The circuit also contains a pull-up resistor R2that separates the circuit from the positive voltage power supply Vcc. It should be noted that, during normal operation of the communication driver circuit100, transistor M3acts as a diode to prevent current flow from the negative supply voltage to the I/O pad terminal in the event that the I/O pad terminal voltage becomes negative with respect to the negative supply voltage.

Communication driver transistor M5, which could be a low side driver, has a drain terminal connected to common drain node102, and a source terminal connected to the negative power supply, shown as ground inFIG. 4. It should be appreciated that, although communication driver transistor M5is shown inFIG. 4as an N-type DMOS transistor, any type of communication driver transistor known in the art will suffice. The communication driver circuit100further includes a communication buffer108that receives a communication signal CSin, which is output from communication buffer108to the gate terminal of communication driver transistor M5.

As illustrated inFIG. 4, communication driver circuit100contains functional communication circuitry using communication driver transistor M5while still maintaining the same level of bi-directional ESD protection, as discussed above with regard toFIG. 1, from DMOS transistors M3and M4. It should be appreciated that the communication driver circuit100could be used in any application that requires ESD protection on a communication driver circuit, even in higher voltage applications such as an automotive bus.

FIG. 5illustrates another communication driver circuit120with bi-directional ESD protection including an integral SCR as part of the communication driver transistor in accordance with an aspect of the present invention.FIG. 5shows two N-type DMOS transistors, M6and M7situated opposite each other such that the drain terminals of each transistor share a common node122. It should be noted that, in this configuration, the gate terminal of transistor M6has been shorted to its respective source terminals. The result of the source/gate terminal short circuit is that transistor M6will never operate in a normal bias condition (e.g., the transistor will always operate in the cutoff region). The common source/gate terminal of transistor M6shares a node124with the input/output (I/O) pad terminal. The circuit also contains a pull-up resistor R3that separates the circuit from the positive voltage power supply Vcc. It should be noted that, during normal operation of the communication driver circuit120, transistor M6acts as a diode to prevent current flow from the negative supply voltage to the I/O pad terminal in the event that the I/O pad terminal voltage becomes negative with respect to the negative supply voltage.

Communication driver transistor M7, which could be a low side driver, has a drain terminal connected to common drain node122, and a source terminal connected to the negative power supply, shown as ground inFIG. 5. It should be appreciated that, although communication driver transistor M7is shown inFIG. 5as an N-type DMOS transistor, any type of communication driver transistor known in the art that is capable of achieving the desired parasitic effects will suffice. The communication driver circuit120further includes a communication buffer128that receives a communication signal CSin, which is output from communication buffer128to the gate terminal of communication driver transistor M7.

As illustrated inFIG. 5, communication driver circuit120contains functional communication circuitry using communication driver transistor M7while still maintaining the same level of bi-directional ESD protection, as discussed above with regard toFIG. 1, from DMOS transistors M6and M7. In effect, this means that communication driver M7is operable as a communication driver transistor as well as a transistor with an integral parasitic body diode (not shown), parasitic substrate diode (not shown), and SCR (not shown) capable of providing bi-directional ESD protection in combination with DMOS transistor M6. It should be appreciated that the communication driver circuit120could be used in any application that requires ESD protection on a communication driver circuit, even in higher voltage applications such as an automotive bus.

FIG. 6illustrates another communication driver circuit140with positive ESD protection including an integral SCR as part of the communication driver transistor in accordance with an aspect of the present invention. Communication driver transistor M8, which could be a low side driver, has a drain terminal connected to node144, which is shared by the I/O Pad Terminal, and a source terminal connected to the negative power supply, shown as ground inFIG. 6. It should be appreciated that, although communication driver transistor M8is shown inFIG. 6as an N-type DMOS transistor, any type of communication driver transistor known in the art that is capable of achieving the desired parasitic effects will suffice. The communication driver circuit140further includes a communication buffer148that receives a communication signal CSin, which is output from communication buffer148to the gate terminal of communication driver transistor M8.

As illustrated inFIG. 6, communication driver circuit140contains functional communication circuitry using communication driver transistor M8while still maintaining positive ESD protection, as discussed above with regard to a positive ESD strike inFIG. 1, from DMOS transistor M8. In effect, this means that communication driver M8is operable as a communication driver transistor as well as a transistor with an integral parasitic body diode (not shown) and a SCR (not shown) capable of providing positive ESD protection. It should be appreciated that the communication driver circuit140could be used in any application that requires ESD protection on a communication driver circuit, even in higher voltage applications such as an automotive bus.

FIG. 7illustrates a communication system200utilizing the communication driver circuit with bi-directional ESD protection in accordance with an aspect of the invention. The communication system200comprises a CPU202that provides a communication signal. The communication signal is sent to the communication driver circuit with bi-directional ESD protection204. This circuit could be a circuit as illustrated inFIG. 4orFIG. 5. The communication driver circuit then transmits the communication signal across the I/O communication bus206to a receiver208. The signal is then processed at the receiver208. The communication system200ofFIG. 7could be used in a variety of applications, such as in an automobile or a computer system, where there is a need for bi-directional ESD protection.