SINGLE-PHOTON AVALANCHE DIODE-BASED IMAGE SENSOR AND METHOD FOR DRIVING SAME

According to an embodiment of the present disclosure, a single-photon avalanche diode-based image sensor may comprise: a single-photon avalanche diode (SPAD) which generates a plurality of pulses corresponding to a plurality of photons, received during a predetermined exposure time, respectively; a front-end circuit which receives a set of pulses received during a partial time of the exposure time among the plurality of pulses; a counter which counts the number of pulses in the set of pulses; and a global clock which provides a plurality of clock pulses to the front-end circuit from after the partial time, wherein the quality of an image acquired using the SPAD is determined based on the timing of the global clock.

TECHNICAL FIELD

The present disclosure relates to a single-photon avalanche diode-based image sensor and a method for driving the same.

BACKGROUND ART

A single-photon avalanche diode (SPAD) is a sensing technology that detects faint light signals at a photon level. In particular, the single-photon avalanche diode has very high sensitivity because it uses avalanche multiplication to amplify a single incident photon, making it very easy to photograph in dark environments.

Meanwhile, in the single-photon avalanche diode, an operation of counting trigger pulses generated by photons is required. However, when a counter with a large number of bits is used to count a large number of photons, the size of a circuit increases, which causes the problem of increased power consumption.

The present disclosure was derived from research conducted as part of the development of a 20×20 cm large-area hybrid X-ray video detector based on a global shutter (Project ID: 1711138024, Project Number: KMDF_PR_20200901_0048-01, Research Project Name: Pan-Ministry Full-Cycle Medical Device R&D Project (Ministry of Science and ICT, Ministry of Health and Welfare, and Ministry of Trade, Industry and Energy), Project Management Agency: Pan-Ministry Full-Cycle Medical Device Research and Development Project Group, Project Executing Agency: Rayence Co., Ltd., Research Period: Mar. 1, 2021˜Dec. 31, 2022).

Meanwhile, Korean government, which provided the task, has no property interest in any aspect of the present disclosure.

SUMMARY

Technical Problem

In order to solve the above-described problem, the present disclosure provides a single-photon avalanche diode-based image sensor that reduces power consumption by estimating the number of total pulses (i.e., total photons) by utilizing an overflow time point of a counter.

Advantageous Effects

According to some embodiments of the present disclosure, power consumed by a counter can be significantly reduced by counting only a portion of total photons received in a single-photon avalanche and estimating the number of the total photons by utilizing an overflow time point of the counter.

According to some embodiments of the present disclosure, images with excellent image quality can be obtained depending on illumination conditions.

DETAILED DESCRIPTIONS OF EXEMPLARY EMBODIMENTS

According to an embodiment of the present disclosure, a single-photon avalanche diode-based image sensor includes: a single-photon avalanche diode (SPAD) configured to generate a plurality of pulses corresponding to a plurality of photons, received during a predetermined exposure time, respectively, a front-end circuit configured to receive a set of pulses received during a portion of the exposure time among the plurality of pulses, a counter configured to count the number of pulses in the set of pulses, and a global clock configured to provide a plurality of clock pulses to the front-end circuit starting after the portion of the exposure time, wherein a quality of an image acquired by using the single-photon avalanche diode may be determined based on timing of the global clock.

According to an embodiment, at least a portion of the timing of the global clock may be determined based on the number of bits of the counter.

According to an embodiment, at least a portion of the timing of the global clock may be configured to have a positive linear relationship with respect to the timing of the exposure time.

According to an embodiment, at least a portion of the timing of the global clock may be configured to have a positive linear relationship with respect to the square root of the timing of the exposure time.

According to an embodiment, at least a portion of the timing of the global clock may be configured to have a positive linear relationship with respect to the log of the timing of the exposure time.

According to an embodiment, at least a portion of the timing of the global clock may be configured to have a negative linear relationship with respect to the timing of the exposure time.

According to an embodiment, the image sensor may further include a processor configured to determine the timing of the global clock based on the number of a plurality of photons received during the exposure time.

According to an embodiment, an endpoint of the portion of the exposure time may be based on the overflow time point of the counter counting the number of pulses in the set of pulses.

According to another embodiment of the present disclosure, a method for driving a single-photon avalanche diode-based image sensor includes: generating, by a single-photon avalanche diode, a plurality of pulses corresponding to a plurality of photons, received during a predetermined exposure time, respectively, receiving, by a front-end circuit, a set of pulses received during a portion of the exposure time among the plurality of pulses, counting, by a counter, the number of pulses in the set of pulses, and providing, by a global clock, a plurality of clock pulses to the front-end circuit from after the portion of the exposure time, wherein a quality of an image acquired by using the single-photon avalanche diode may be determined based on timing of the global clock.

According to another embodiment of the present disclosure, a computer program recorded on a computer-readable recording medium may be provided to execute the method for driving the single-photon avalanche diode-based image sensor.

Below, specific details for implementing the present disclosure are described in detail with reference to the attached drawings. However, in the description below, specific descriptions of widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the gist of the present disclosure.

In the attached drawings, identical or corresponding components are given the same reference numerals. Additionally, in the description of the embodiments below, redundant description of identical or corresponding components may be omitted. However, the omission of a description of a component is not intended to imply that such component is not included in any embodiment.

The advantages and features of the disclosed embodiments and the methods of achieving them will be apparent with reference to the embodiments described below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms, and the present embodiments are provided only to make the present disclosure complete and to fully inform those skilled in the art of the scope of the present disclosure.

Terms used in this specification will be briefly described, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected from commonly used terms as much as possible while considering the functions in the present disclosure, but may vary depending on the intention of engineers working in the relevant field, case law, the emergence of new technologies, etc. Additionally, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, meanings of the terms will be described in detail in the description of the relevant invention. Therefore, the terms used in the present disclosure should be defined based on the meaning of the terms and the overall content of the present disclosure, rather than simply the names of the terms.

In this specification, singular expressions include plural expressions unless the context clearly specifies that they are singular. In addition, plural expressions include singular expressions unless the context clearly specifies that they are plural. When a part throughout this specification is described to “include” a component, this does not mean that the part excludes other components, but rather that the part may include other components, unless otherwise stated.

FIG. 1 is a block diagram showing the configuration of a single-photon avalanche diode-based image sensor according to an embodiment of the present disclosure. Simply put, an image sensor 100 may receive a plurality of photons from outside and generate an image by counting the number of the plurality of received photons. In this case, the image sensor 100 may consume a significant amount of power in counting photon(s). To this end, the present disclosure provides the image sensor 100 which reduces power consumption by counting photons only up to a predetermined number and estimating the total number of photons received by using information about a time point at which the corresponding counting ends. As illustrated, the image sensor 100 may include at least one of a single-photon avalanche diode 110, a front-end circuit 120, and a counter 130.

The single-photon avalanche diode 110 may receive the plurality of photons from the outside and generate a plurality of pulses corresponding to the plurality of received photons, respectively. For example, when N photons (here, N is a natural number) are received by the single-photon avalanche diode 110, the single-photon avalanche diode 110 may generate N pulses. After that, the plurality of pulses generated may be transmitted to the front-end circuit.

The single-photon avalanche diode 110 may receive the plurality of photons from the outside for a predetermined exposure time and generate the plurality of pulses corresponding to the plurality of received photons, respectively. For example, when N photons (here, N is a natural number) are received from 0 [ms] to 16 [ms] by the single-photon avalanche diode 110, the single-photon avalanche diode 110 may generate N pulses. After that, at least some of the plurality of pulses generated may be transmitted to the front-end circuit.

The front-end circuit 120 may receive the plurality of pulses generated by the single-photon avalanche diode 110. In this case, the plurality of pulses may refer to a plurality of pulses received by the single-photon avalanche diode 110 during the exposure time. For example, the front-end circuit 120 may receive N pulses from the single-photon avalanche diode 110 when the N photons (here, N is a natural number) are received by the single-photon avalanche diode 110 from 0 [ms] to 16 [ms]. Additionally or alternatively, the front-end circuit 120 may receive at least some of the plurality of pulses generated by the single-photon avalanche diode 110. For example, the front-end circuit 120 may receive Nor pulses (here, NOF<N) received from 0 [ms] to TOF [ms] (where TOF<16) when N photons (here, N is a natural number) are received from 0 [ms] to 16 [ms] by the single-photon avalanche diode 110. For another example, the front-end circuit 120 may receive Nor pulses (here, NOF<N) received from TOF1 [ms] to TOF2 [ms] (wherein, 0<TOF1<TOF2≤16) when N photons (here, N is a natural number) are received from 0 [ms] to 16 [ms] by the single-photon avalanche diode 110.

The front-end circuit 120 may receive a plurality of clock pulses generated from an external device (e.g., a global clock). In this case, the plurality of clock pulses may refer to a plurality of clock pulses generated during the exposure time. For example, the front-end circuit 120 may receive M clock pulses from 0 [ms] to 16 [ms]. Additionally or alternatively, the front-end circuit 120 may receive a plurality of clock pulses generated during a portion of an overall exposure time. For example, the front-end circuit 120 may receive clock pulses generated between TOF [ms] and 16 [ms] during an exposure time ranging from 0 [ms] to 16 [ms]. For another example, the front-end circuit 120 may receive clock pulses generated between 0 [ms] and TOF [ms] during the exposure time ranging from 0 [ms] to 16 [ms].

The front-end circuit 120 may initiate receiving a plurality of clock pulses generated from the external device in response to a signal received from the counter 130. In this case, the signal received from the counter 130 may refer to a signal generated in response to the counter 130 overflowing. More specifically, the signal received from the counter 130 may refer to a signal transmitted to the front-end circuit 120 in response to the overflowing of the counter 130 counting the plurality of pulses received from the single-photon avalanche diode 110 via the front-end circuit 120. For example, when the exposure time is from 0 [ms] to 16 [ms], the counter 130 with N bits may overflow after counting 2(N-1) pulses received from the single-photon avalanche diode 110 through the front-end circuit 120 by using N−1 bits from 0 [ms]. In this case, a value indicating an overflow is input into the remaining one bit of the N bits of the counter 130 that is not used for counting, and in response, the counter 130 may transmit a signal to the front-end circuit 120 at TOF [ms]. After that, in response to the signal received from the counter 130, the front-end circuit 120 may stop receiving pulses from the single-photon avalanche diode 110 and initiate receiving clock pulses from the external device. That is, the front-end circuit 120 may receive a plurality of pulses from the single-photon avalanche diode 110 from 0 [ms] to TOF [ms], and may receive a plurality of clock pulses from the external device from TOF [ms] to 16 [ms]. Meanwhile, a MUX element may be used to switch the operation of the front-end circuit 120 from an operation of counting pulses received from the single-photon avalanche diode 110 to an operation of receiving clock pulses from the external device as described above.

The counter 130 may count the number of pulse(s) input to the front-end circuit 120. For example, the counter 130 may count the number of the plurality of pulses input to the front-end circuit 120 from the single-photon avalanche diode 110 from 0 [ms] to TOF [ms]. As an additional or alternative example, the counter 130 may count the number of a plurality of clock pulses input to the front-end circuit 120 from TOF [ms] to 16 [ms].

Meanwhile, although not shown in FIG. 1, the image sensor 100 may further include a global clock (not shown) configured to generate the clock pulses described above. In this case, the total number of clock pulses generated by the global clock during the exposure time may be equal to the number of a plurality of pulses counted until just before the counter 130 with N bits (in this case, only N−1 bits of the counter 130 are used for counting) overflows (i.e., until before TOF [ms] in the above example). That is, when the counter 130 with N bits is used, the total number of clock pulses generated by the global clock during the exposure time may be preset to 2(N−1). A detailed description of this will be provided later with reference to FIG. 3.

In addition, in FIG. 1, for convenience of explanation, the image sensor 100 is illustrated as including one single-photon avalanche diode 110, but is not limited thereto. That is, the image sensor 100 may include a plurality of single-photon avalanche diodes. For example, the front-end circuit 120 may be connected to a plurality of single-photon avalanche diodes arranged in each of a plurality of pixels.

Although FIG. 1 illustrates a configuration in which only a single counter 130 is included in the device or system comprising the single-photon avalanche diode 110, the present disclosure is not limited thereto, and a plurality of counters 130 may also be included.

According to one embodiment, the device of the present disclosure includes one counter 130, which may count the number of pulses input to the front-end circuit 120 by using clock pulses generated by the global clock. In this case, the characteristics of the clock pulses generated by the global clock may vary depending on the type of the global clock. For example, when the global clock is of a first type, the rate of change in output with respect to the input of the global clock may have a first gradient. In another example, if the global clock is of a second type, the rate of change in output with respect to the input may have a second gradient different from the first.

More specifically, if the global clock is of an SQRT type, the output of the global clock may increase with its input, but the rate of change in the output may decrease. On the other hand, if the global clock is of a LOG type, both the output and the rate of change of the output with respect to the input may increase. The types of global clocks are not limited to the aforementioned SQRT and LOG types, and may be selected differently depending on purposes or operating conditions.

According to another embodiment, the device of the present disclosure may include two or more counters 130. Specifically, a first counter may count the number of pulses input to the front-end circuit 120 by using a first set of clock pulses generated when the global clock operates in a first type. Additionally, a second counter may count the number of pulses input to the front-end circuit 120 by using a second set of clock pulses generated when the global clock operates in a second type. Accordingly, the counters 130 may be configured to correspond to each type of global clock.

According to still another embodiment, the device of the present disclosure may include a single counter 130, which may count the number of pulses input to the front-end circuit 120 by using periodic clock pulses until a predetermined time. After the predetermined time, the counter 130 may switch to counting the number of pulses input to the front-end circuit 120 by using the clock pulses generated by the global clock. This embodiment will be described in more detail below with reference to FIG. 2.

FIG. 2 is a graph 200 illustrating a method for calculating the total number of photons received by the single-photon avalanche diode-based image sensor (e.g., the image sensor 100) according to an embodiment of the present disclosure. Here, it is assumed that the counter (e.g., the counter 130) provided to count pulses generated by the single-photon avalanche diode (e.g., the single-photon avalanche diode 110) and/or the global clock consists of N bits, and only N−1 bits are used for counting. In addition, TOF in FIG. 2 indicates a time point at which the counter overflows as a result of counting a plurality of pulses received from the single-photon avalanche diode.

As described above in FIG. 1, the counter counts only 2(N−1) pulses generated by the single-photon avalanche diode during time between 0 and TOF in order to reduce power consumption. In this case, since time TEXP during which the image sensor is exposed to a light source has a predetermined value, the total number of photons (NOH) received by the image sensor during the exposure time may be calculated according to the following mathematical expression 1. In this case, the power of counting photons may be saved as much as NPH/NOF. Here, NOF represents the number of photons received by the image sensor from a time point at which the exposure of the image sensor to the light source begins until a time point at which the counter overflows. However, in order to calculate the number (NOH) of photons by using mathematical expression 1, it is first required to know the TOF, which indicates the time point at which the counter overflows. A method for estimating TOF will be described later with reference to FIG. 3.

FIG. 3 is a graph 300 showing clock pulses of the global clock provided to provide clock pulse(s) to the front-end circuit according to an embodiment of the present disclosure. Likewise, it is assumed that the counter (e.g., the counter 130) provided to count pulses generated by the single-photon avalanche diode (e.g., the single-photon avalanche diode 110) and/or the global clock consists of N bits, and only N−1 bits are used for counting. Additionally, TOF and TEXP represent the time point at which the counter overflows and time during which the single-photon avalanche diode is exposed to the light source, respectively, as shown in TOF and TEXP in FIG. 2.

As described in FIG. 1, the total number M of clock pulses generated during the exposure time is set to be equal to the number (i.e., 2(N−1)) of a plurality of pulses generated by the single-photon avalanche diode between 0 and TOF. In addition, the timing of each of the entire clock pulses are set to include at least one function of a log function, a linear function, or a square-root function with respect to the exposure time. For example, clock pulses between 0 and TOF may be provided in the form of a linear function, and clock pulses between TOF and TEXP may be provided in the form of a log function. That is, a time point of each of all clock pulses has a value predetermined based on the shape of a selected function. Accordingly, the time point Tn of the last clock pulse occurring before TOF may be calculated by using the sequence number (here, n+1) and time point Tn+1 of a clock pulse occurring first after TOF. In this case, since the overflow of the counter occurs at a time point between Tn and Tn+1, TOF may be estimated as any value between NOF*(TEXP/Tn) and NOF*(TEXP/Tn+1), as in mathematical expression 2 below.

FIG. 4 is an example showing the timing of the global clock according to an embodiment of the present disclosure. Here, the global clock ΦGCLK may refer to a device that generates the above-described clock pulse at a predetermined timing. In FIG. 4, N represents the number of bits used for pulse counting in the counter. Additionally, NEX represents the number of photons received by the single-photon avalanche diode from a starting point of the exposure time to an endpoint (e.g., TEXP in FIG. 2) of the exposure time. Hereinafter, a method for estimating NEX based on various types of global clocks will be described.

FIG. 4(a) shows an example in which at least a portion of the timing of the global clock has a positive linear relationship with respect to the log (or a log value) of the exposure time. Specifically, the timing of the global clock and the log value of the exposure time TEXP may have a proportional relationship. In this case, the overflow time point TSAT of the counter according to the number M_LOG of the clock pulses of the global clock counted by the counter may be obtained through a lookup table, and NEX may be determined by using the reciprocal of the obtained overflow time point TSAT as in the following mathematical expression 3. Meanwhile, in the present disclosure, TSAT is interpreted as having the same meaning as TOF.

FIG. 4(b) shows an example in which at least a portion of the timing of the global clock has a positive linear relationship with respect to the timing of the exposure time. Specifically, an interval between a first clock pulse (e.g., 65.1 us) and a next second clock pulse (e.g., 66.5 us) generated by the global clock may have a value equal to the total exposure time TEXP divided by 2N. In this case, NEX may be calculated by using the reciprocal of the number M_EQ of clock pulses of the global clock counted by the counter, as in the following mathematical expression 4.

FIG. 4(c) shows an example in which at least a portion of the timing of the global clock has a positive linear relationship with respect to the square root of the timing of the exposure time. Specifically, the timing of the global clock and the square root of the exposure time TEXP may have a proportional relationship. In this case, the overflow time point TSAT of the counter according to the number M_SQRT of clock pulse(s) of the global clock counted by the counter may be obtained through a lookup table, and NEX may be determined by using the reciprocal of the obtained overflow time point TSAT as in the following mathematical expression 5.

Additionally or alternatively, although not shown in FIG. 4, at least a portion of the timing of the global clock may be configured to have a negative linear relationship with respect to the timing of the exposure time. In this case, NEX may be calculated according to the following mathematical expression 6.

FIGS. 5a and 5b are graphs illustrating the extrapolated gain of a global clock according to an embodiment of the present disclosure. Specifically, FIGS. 5a and 5b are graphs illustrating the output of the global clock in response to its input. As illustrated, the global clock of an EQ type may have an extrapolated gain which remains constant, and be advantageous in acquiring images in low illumination and/or medium illumination conditions. Accordingly, although not shown in FIGS. 5a and 5b, a global clock according to mathematical expression 6, on the other hand, may be advantageous in acquiring images in medium illumination and/or high illumination conditions. On the other hand, an SQRT-type global clock shows the increasing pattern of an extrapolated gain (output of the global clock), but the rate of change of the extrapolated gain (rate of change in the output of the global clock with respect to its input) decreases. Additionally, an LOG-type global clock shows the increasing pattern of an extrapolated gain, and the rate of change of the extrapolated gain also increases.

The single-photon avalanche diode-based image sensor of the present disclosure may determine the type of global clock depending on an illumination environment based on the type-specific extrapolated gain of the global clock described above. Specifically, the single-photon avalanche diode-based image sensor may include a processor that determines the timing of the global clock based on the number of a plurality of photons received during the exposure time. In this case, the processor may select an EQ-type global clock as a global clock connected to the front-end circuit (e.g. the front-end circuit 120) in a low illumination environment. In addition, the processor may select a global clock according to mathematical expression 6 as a global clock in a high illumination environment.

According to one embodiment, when the global clock is of a first type, the gain for a first illumination level of an image acquired using the single-photon avalanche diode may increase. In addition, when the global clock is of a second type, the gain for a second illumination level of an image acquired using the single-photon avalanche diode may increase. As such, the type of the global clock may be set according to the environment for image acquisition.

Additionally or alternatively, the processor may use any combination of the four types of global clocks described above, depending on an illumination environment. For example, the processor may determine to use an EQ-type global clock from the starting point to the middle time point during time for which the counter is counting the global clock, and to use a SQRT-type global clock from the middle time point to the endpoint. That is, the processor may determine the timing of the global clock based on the number of a plurality of photons received during the exposure time.

The foregoing description of the present disclosure is provided to enable those skilled in the art to perform or use the present disclosure. Various modified examples of the present disclosure will be readily apparent to those skilled in the art, and general principles defined herein may be applied to various embodiments without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is not intended to be limited to the examples described herein but is to be accorded with the widest scope consistent with the principles and novel features disclosed herein.

Although the present disclosure has been described in connection with some embodiments herein, it should be understood that various modifications and changes may be made without departing from the scope of the present disclosure as understood by those skilled in the art to which the present disclosure pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended hereto.