PACKAGE COMPRISING DUMMY INTERCONNECTS

A package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.

FIELD

Various features relate to packages that include an integrated device, but more specifically to a package that includes an integrated device and dummy interconnects.

BACKGROUND

FIG. 1illustrates a package100that includes a substrate102, an integrated device104, a passive device106, and an encapsulation layer108. The substrate102includes a plurality of dielectric layers120, a plurality of interconnects122, and a plurality of solder interconnects124. A plurality of solder interconnects144is coupled to the substrate102and the integrated device104. The encapsulation layer108encapsulates the integrated device104, the passive device106and the plurality of solder interconnects144. An integrated device130may be coupled to a bottom side of the substrate102, through the plurality of solder interconnects132. The package100may be subject to a lot of stress (e.g., shear stress, mechanical stress) when the package100is coupled to a board, which can affect the reliability of the package100. There is an ongoing need to provide more reliable packages.

SUMMARY

Various features relate to packages that include an integrated device, but more specifically to a package that includes an integrated device and dummy interconnects.

One example provides a package comprising a substrate comprising a first surface and a second surface, a passive device coupled to the first surface of the substrate, a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device, an integrated device coupled to the second surface of the substrate, a second encapsulation layer located over the second surface of the substrate, wherein the second encapsulation layer encapsulates the integrated device, a plurality of through encapsulation layer interconnects coupled to the substrate, a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and at least one dummy interconnect located in the second encapsulation layer, wherein the at least one dummy interconnect is located vertically over a back side of the integrated device.

Another example provides an apparatus comprising a substrate, a passive device, first means for encapsulation, an integrated device, second means for encapsulation, a plurality of through encapsulation layer interconnects, and at least one dummy interconnect. The substrate includes a first surface and a second surface. The substrate further comprises a plurality of interconnects. The passive device is coupled to the first surface of the substrate. The first means for encapsulation located over the first surface of the substrate, where the first means for encapsulation encapsulates the passive device. The integrated device is coupled to the second surface of the substrate. The second means for encapsulation is located over the second surface of the substrate, where the second means for encapsulation encapsulates the integrated device. The plurality of through encapsulation layer interconnects is coupled to the substrate. The plurality of encapsulation layer interconnects is coupled to the plurality of through encapsulation layer interconnects. The at least one dummy interconnect is located in the second encapsulation layer, where the at least one dummy interconnect is located vertically over a back side of the integrated device.

Another example provides a method for fabricating a package. The method provides a substrate comprising a first surface and a second surface, where the substrate further comprises a plurality of interconnects. The method couples a passive device to the first surface of the substrate. The method forms a first encapsulation layer over the first surface of the substrate, where the first encapsulation layer encapsulates the passive device. The method couples an integrated device to the second surface of the substrate. The method provides a plurality of through encapsulation layer interconnects to the substrate. The method forms a second encapsulation layer over the second surface of the substrate, where the second encapsulation layer encapsulates the integrated device. The method provides a plurality of encapsulation layer interconnects to the plurality of through encapsulation layer interconnects. The method provides at least one dummy interconnect in the second encapsulation layer, where the at least one dummy interconnect is located vertically over a back side of the integrated device.

DETAILED DESCRIPTION

The present disclosure describes a package that includes a substrate, a first encapsulation layer, a second encapsulation layer, an integrated device and a passive device. The substrate includes a plurality of interconnects. The substrate further includes a first surface and a second surface. The passive device is coupled to the first surface of the substrate. A first encapsulation layer is located over the first surface of the substrate. The first encapsulation layer encapsulates the passive device. The integrated device is coupled to the second surface of the substrate. The second encapsulation layer is located over the second surface of the substrate. The second encapsulation layer encapsulates the integrated device. The package further includes (i) a plurality of through encapsulation layer interconnects coupled to the substrate, (ii) a plurality of encapsulation layer interconnects coupled to the plurality of through encapsulation layer interconnects, and (iii) at least one dummy interconnect located in the second encapsulation layer. The at least one dummy interconnect is located vertically over a back side of the integrated device. The at least one dummy interconnect is configured to be free of an electrical connection with the integrated device. The at least one dummy interconnect is configured to be free of an electrical connection with the passive device. The at least one dummy interconnect helps provide structural support for the package, when the package is coupled to a board, which may help provide a more reliable package. Moreover, the at least one dummy interconnect may help with dissipating heat away from the integrated device, which may help with the performance of the integrated device.

Exemplary Package Comprising Dummy Interconnects

FIG. 2illustrates a profile view of a package200that includes dummy interconnects. The package200is coupled to a board290(e.g., printed circuit board). As will be further described below, the dummy interconnects help provide additional mechanical support for the package to provide board (e.g., printed circuit board (PCB)) level reliability and to provide improved heat dissipation capabilities for the package200.

The package200includes a substrate202, a first encapsulation layer204, a second encapsulation layer206, an integrated device260, a plurality of passive devices (e.g.,210,212,214,216) and an integrated device218. The substrate202includes at least one dielectric layer220and a plurality of interconnects222. The substrate2022further includes a first surface and a second surface. The passive devices (e.g.,210,212,214,216) and the integrated device218are coupled to the first surface of the substrate202(e.g., through their respective solder interconnects217). The first encapsulation layer204is located over the first surface of the substrate202. The first encapsulation layer204encapsulates the passive devices (e.g.,210,212,214,216) and the integrated device218. A solder resist layer240may be located over the first surface of the substrate202. The solder resist layer240may be considered part of the substrate202. The solder resist layer240may be located between the first encapsulation layer204and the at least one dielectric layer220. Another integrated device260is coupled to the second surface of the substrate202. For example, a front side of the integrated device260may be coupled to the second surface of the substrate202. The second encapsulation layer206is located over the second surface of the substrate202. The second encapsulation layer206encapsulates the integrated device260.

The package200also includes (i) a plurality of ball interconnects270coupled to the substrate202, (ii) a plurality of encapsulation layer interconnects262coupled to the plurality of ball interconnects270, and (iii) at least one dummy interconnect264located in the second encapsulation layer206.

The plurality of ball interconnects270may include a plurality of solder interconnects272. The plurality of solder interconnects272may help the ball interconnects270couple to the plurality of interconnects222and the plurality of encapsulation layer interconnects262. In some implementations, the plurality of ball interconnects270and the plurality of solder interconnects272are an example of a plurality of through encapsulation layer interconnects coupled to the substrate202. Thus,FIG. 2may illustrate a package200that includes (i) a plurality of through encapsulation layer interconnects coupled to the substrate202, and (ii) a plurality of encapsulation layer interconnects262coupled to the plurality of through encapsulation layer interconnects.

The at least one dummy interconnect264is located vertically over a back side of the integrated device260. The at least one dummy interconnect264is configured to be free of an electrical connection with integrated device(s) of the package200. The at least one dummy interconnect264is configured to be free of an electrical connection with the passive device(s) of the package200. The at least on dummy interconnect264may help provide mechanical support for the package200by increasing the surface area through which stress (e.g., mechanical stress, thermal stress) on the package200is applied on. Increasing the surface area of the coupling of the package200to the board290helps spread out the stress, and helps decrease stress at specific points of coupling between the package200and the board290, leading to a more reliable joint connection between the package200and the board290and ultimately a more reliable package.

Moreover, the at least one dummy interconnect264may help with heat dissipation of the package200. For example, the at least one dummy interconnect264is located closely to (or may be touching) the integrated device260. Since the at least one dummy interconnect264has a higher thermal conductivity value than the thermal conductivity value of the second encapsulation layer206, the at least one dummy interconnect264may be configured as a heat sink and/or heat spreader for the integrated device260and/or the package200. The at least one dummy interconnect264may include the same material or different material than the plurality of encapsulation layer interconnects262.

Different implementations may have different numbers of dummy interconnects. The at least one dummy interconnect264may have different shapes and/or sizes. In some implementations, the at least one dummy interconnect264may be coupled to the back side of the integrated device260.

The package200is coupled to the board290through a plurality of solder interconnects282and a plurality of solder interconnects284. The plurality of solder interconnects282is coupled to the plurality of encapsulation layer interconnects262. The plurality of solder interconnects284is coupled to the at least one dummy interconnects. The plurality of solder interconnects284may be considered a plurality of dummy solder interconnects.

FIG. 3illustrates a bottom plan view of the package200. As shown inFIG. 3, the package200includes the second encapsulation layer206, the plurality of solder interconnects282and the plurality of solder interconnects284. The plurality of solder interconnects284may be a plurality of dummy solder interconnects. The plurality of dummy solder interconnects (e.g.,284) is configured to be free of an electrical connection with integrated device(s) of the package200. The plurality of dummy solder interconnects (e.g.,284) is configured to be free of an electrical connection with the passive device(s) of the package200. Similar to the dummy interconnect264, the plurality of dummy solder interconnects284helps provide mechanical support for the package200and helps dissipate heat away from the package200and/or integrated devices in the package200.FIG. 3illustrates that the plurality of solder interconnects282laterally surrounds the plurality of solder interconnects284. The plurality of solder interconnects282may be located along a periphery of the package200, while the plurality of solder interconnects284may be located around an inner portion of the package200.

It is noted that different implementation may include different configurations of the package200. For example, different implementations of the package200may include different numbers of integrated devices and/or passive devices. For example, the package200may include more than one integrated device that is coupled to the second surface of the substrate202. In another example, one or more passive devices may be coupled to the second surface of the substrate202.

FIG. 4illustrates a package400that includes dummy interconnects. The package400is similar to the package200, and thus includes similar components as the package200. The package400includes a thermal interface material (TIM)460. The TIM460is coupled to the back side of the integrated device260and the at least one dummy interconnect264. The TIM460is encapsulated by the second encapsulation layer206. The TIM460has better (e.g., higher) thermal conductivity value than the thermal conductivity value of the second encapsulation layer206. The TIM460with the at least one dummy interconnect264may help provide better heat dissipation for the package200and/or the integrated device260than the at least one dummy interconnect264without the TIM460.

FIG. 5illustrates a package500that includes dummy interconnects. The package500is similar to the package200and/or the package400, and thus includes similar components as the package200and/or the package400. The package500includes a different through encapsulation layer interconnects. Instead of the plurality of ball interconnects270, the package500includes a plurality of vias570and a dielectric layer572. The dielectric layer572may laterally surround the plurality of vias570. The plurality of vias570may be considered a plurality of pillars. The plurality of vias570and the dielectric layer572may be encapsulated by the second encapsulation layer206. The plurality of vias570is coupled to the substrate202and the plurality of encapsulation layer interconnects262.

FIG. 6illustrates a package600that includes dummy interconnects. The package600is similar to the package200and/or the package400, and thus includes similar components as the package200and/or the package400. The package600includes a different through encapsulation layer interconnects. Instead of the plurality of ball interconnects270, the package600includes a plurality of vias670. The plurality of vias670may be encapsulated by the second encapsulation layer206. The plurality of vias670is coupled to the substrate202and the plurality of encapsulation layer interconnects262. The plurality of vias670and the plurality of encapsulation layer interconnects262may be considered the same. As will be further describe below, the plurality of vias670may be formed using a plating process and/or sputtering process.

An integrated device (e.g.,218,260) may include a die (e.g., semiconductor bare die). The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a surface acoustic wave (SAW) filters, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon carbide (SiC) based integrated device, and/or combinations thereof.

A passive device may include a capacitor and/or a resistor. The various encapsulation layers (e.g.,204,206) may include a mold, a resin, an epoxy and/or polymer. An encapsulation layer (e.g.,204,206) may be a means for encapsulation (e.g., first means for encapsulation, second means for encapsulation).

Having described various packages with dummy interconnects, processes for fabricating a package that includes dummy interconnects will now be described below.

Exemplary Sequence for Fabricating a Packaging Comprising Dummy Interconnects

FIG. 7(which includesFIGS. 7A-7F) illustrates an exemplary sequence for providing or fabricating a package that includes dummy interconnects. In some implementations, the sequence ofFIGS. 7A-7Fmay be used to provide or fabricate the package200ofFIG. 2, or any of the packages described in the disclosure.

Stage1, as shown inFIG. 7A, illustrates a state after a carrier700is provided. The carrier700may be a substrate and/or a wafer. The carrier700may include glass and/or silicon. The carrier700may be a first carrier.

Stage2illustrates a state after a plurality of interconnects702is formed over the carrier700. The plurality of interconnects702may include traces and/or pads. Forming the plurality of interconnects702may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. The plurality of interconnects702may be part of the plurality of interconnects222.

Stage3illustrates a state after the dielectric layer710is formed over the plurality of interconnects702and the carrier700. The dielectric layer710may be deposited and/or coated over the plurality of interconnects702and the carrier700. The dielectric layer710may include polymer.

Stage4illustrates a state after cavities711are formed in the dielectric layer710. An etching process may be used to form the cavities711.

Stage5illustrates a state after a plurality of interconnects712is formed over the dielectric layer710. The plurality of interconnects712may include vias, traces and/or pads. Forming the plurality of interconnects712may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. The plurality of interconnects712may be part of the plurality of interconnects222.

Stage6, as shown inFIG. 7B, illustrates a state after a dielectric layer720and a plurality of interconnects722are formed over the dielectric layer710. The dielectric layer720may be deposited and/or coated over the plurality of interconnects712and the dielectric layer710. The dielectric layer720may include polymer. Forming the dielectric layer720may include forming cavities in the dielectric layer720. An etching process may be used to form the cavities in the dielectric layer720. The plurality of interconnects722may include vias, traces and/or pads. Forming the plurality of interconnects722may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. The plurality of interconnects722may be part of the plurality of interconnects222.

Stage7illustrates a state after a dielectric layer730and a plurality of interconnects732are formed over the dielectric layer720. The dielectric layer730may be deposited and/or coated over the plurality of interconnects722and the dielectric layer720. The dielectric layer730may include polymer. Forming the dielectric layer730may include forming cavities in the dielectric layer730. An etching process may be used to form the cavities in the dielectric layer730. The plurality of interconnects732may include vias, traces and/or pads. Forming the plurality of interconnects732may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. The plurality of interconnects732may be part of the plurality of interconnects222.

Stage8illustrates a state after the solder resist layer240is formed over the substrate202. The solder resist layer240may be considered part of the substrate202. The substrate202includes the at least one dielectric layer220and the plurality of interconnects222. The at least one dielectric layer220may represent the dielectric layers710,720and730. The plurality of interconnects222may represent the plurality of interconnects712,722and732.

Stage9, as shown inFIG. 7C, illustrates a state after a plurality of passive devices (e.g.,210,212,214,216) and an integrated device218are coupled to a first surface of the substrate202. A pick and place process may be used to place the passive devices and integrated device over the first surface of the substrate202. Solder interconnects (e.g.,217) may be used to couple the passive devices (e.g.,210,212,214,216) and the integrated device218to the substrate202(e.g., interconnects of the substrate202).

Stage10illustrates a state after a first encapsulation layer204is formed over the first surface of the substrate202such that the first encapsulation layer204encapsulates the passive devices (e.g.,210,212,214,216) and the integrated device218. The process of forming and/or disposing the first encapsulation layer204may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

Stage11illustrates a state after the carrier700is decoupled from the substrate202. The carrier700may be decoupled through a grinding process and/or peel off process.

Stage12, as shown inFIG. 7D, illustrates a state after the integrated device260and the plurality of ball interconnects270is coupled to a second surface of the substrate202. The plurality of ball interconnects270is coupled to the substrate202through the plurality of solder interconnects272. The integrated device260is coupled to the substrate202through the plurality of solder interconnects266. It is noted that in some implementations, instead of the plurality of ball interconnects, the plurality of vias570and the dielectric layer572may be used instead.

Stage13, illustrates a state after a thermal interface material (TIM)460is formed over the back side of the integrated device260. The TIM460may be optional.

Stage14, as shown inFIG. 7E, illustrates a state after a lead frame760is coupled and/or being coupled to the plurality of ball interconnects270and the TIM460. In some implementations, the lead frame760may be coupled directly to the back side of the integrated device260. A lead frame760may include a structure that is electrically conductive. The lead frame760may include a unibody or may include several components. The lead frame760may be uniform in composition or may include different materials for different portions.

Stage15illustrates a state after the second encapsulation layer206is formed between the substrate202and the lead frame760. The second encapsulation layer206may encapsulate the plurality of ball interconnects270, the plurality of solder interconnects272, the integrated device260, the TIM460and/or the lead frame760. The process of forming and/or disposing the second encapsulation layer206may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

Stage16illustrates a state after portions of the lead frame760are removed leaving behind the plurality of encapsulation layer interconnect262and the at least one dummy interconnect264. The at least one dummy interconnect264may include the same material or different material than the plurality of encapsulation layer interconnects262. It is noted that the different shading between the at least one dummy interconnect264and the plurality of encapsulation layer interconnects262is to help visually distinguish a dummy interconnect from an encapsulation layer interconnect. The difference in shading does not necessarily indicate a difference in materials. A grinding process may be used to remove portions of the lead frame760. In some implementations, portions of the second encapsulation layer206may also be removed to create a flat planar surface with the plurality of encapsulation layer interconnect262and the at least one dummy interconnect264. Stage16may illustrate the package200.

Stage17illustrates a state after the plurality of solder interconnects282is coupled to the plurality of encapsulation layer interconnects262, and the plurality of solder interconnects284is coupled to the at least one dummy interconnect264. The plurality of solder interconnects284may be a plurality of dummy solder interconnects. Stage17may illustrate the package200that includes a plurality of dummy interconnects and a plurality of solder dummy interconnects.

Exemplary Flow Diagram of a Method for Fabricating a Package Comprising Dummy Interconnects

In some implementations, fabricating a package that includes dummy interconnects several processes.FIG. 8illustrates an exemplary flow diagram of a method800for providing or fabricating a package that includes dummy interconnects. In some implementations, the method800ofFIG. 8may be used to provide or fabricate the package (e.g.,200) ofFIG. 2described in the disclosure. However, the method800may be used to provide or fabricate any of the packages described in the disclosure.

It should be noted that the method ofFIG. 8may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating package. In some implementations, the order of the processes may be changed or modified.

The method provides (at805) a substrate (e.g.,202) that includes at least one dielectric layer (e.g.,220) and a plurality of interconnects (e.g.,222). The dielectric layer220may include polymer. Forming the dielectric layer220may include forming cavities in the dielectric layer220. An etching process may be used to form the cavities in the dielectric layer220. The plurality of interconnects222may include vias, traces and/or pads. Forming the plurality of interconnects222may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. Stages1-8ofFIGS. 7A-7Billustrate an example of providing a substrate.

The method couples (at810) a plurality of passive devices (e.g.,210,212,214,216) and an integrated device218to a first surface of the substrate202. A pick and place process may be used to place the passive devices and integrated device over the first surface of the substrate202. Solder interconnects (e.g.,217) may be used to couple the passive devices (e.g.,210,212,214,216) and the integrated device218to the substrate202(e.g., interconnects of the substrate202). Stage9ofFIG. 7Cillustrates an example of coupling passive devices to a substrate.

The method forms (at815) a first encapsulation layer (e.g.,204) over the first surface of the substrate and the components. The first encapsulation layer204is formed over the first surface of the substrate202such that the first encapsulation layer204encapsulates the passive devices (e.g.,210,212,214,216) and the integrated device218. The process of forming and/or disposing the first encapsulation layer204may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage10ofFIG. 7Cillustrates an example of forming a first encapsulation layer.

The method couples (at820) components (e.g., integrated device, passive device) and a plurality of through encapsulation layer interconnects (e.g., plurality of ball interconnects270) to a second surface of the substrate (e.g.,202). The plurality of ball interconnects270is coupled to the substrate202through the plurality of solder interconnects272. The integrated device260is coupled to the substrate202through the plurality of solder interconnects266. It is noted that in some implementations, instead of the plurality of ball interconnects, the plurality of vias570and the dielectric layer572may be used instead. Stage12ofFIG. 7Dillustrates an example of components being coupled to a substrate. A TIM (e.g.,460) may also be optionally coupled to the integrated device. In some implementations, the TIM is already coupled to the integrated device when the integrated device is coupled to the substrate. Stage13ofFIG. 7Dillustrates an example of a TIM coupled to an integrated device.

The method couples (at825) a lead frame (e.g.,760) to the plurality of through encapsulation layer interconnects (e.g., plurality of ball interconnects270). The lead frame760may be coupled to the TIM460. In some implementations, the lead frame760may be coupled directly to the back side of the integrated device260. A lead frame760may include a structure that is electrically conductive. The lead frame760may include a unibody or may include several components. The lead frame760may be uniform in composition or may include different materials for different portions. Stage14ofFIG. 7Dillustrates an example of a lead frame coupled to interconnects.

The method forms (at830) a second encapsulation layer (e.g.,206) between the substrate202and the lead frame760. The second encapsulation layer206may encapsulate the plurality of through encapsulation layer interconnects (e.g., plurality of ball interconnects270), the plurality of solder interconnects272, the integrated device260, the TIM460and/or the lead frame760. The process of forming and/or disposing the second encapsulation layer206may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

The method removes (at835) removes portions of portions of the lead frame760are to form the plurality of encapsulation layer interconnect262and the at least one dummy interconnect264. A grinding process may be used to remove portions of the lead frame760. In some implementations, portions of the second encapsulation layer206may also be removed to create a flat planar surface with the plurality of encapsulation layer interconnect262and the at least one dummy interconnect264. Stage16ofFIG. 7Fillustrates an example of a state after portions of the lead frame760have been removed.

The method couples (at840) (i) a plurality of solder interconnects282to the plurality of encapsulation layer interconnects262, and (ii) a plurality of solder interconnects284to the at least one dummy interconnect264. The plurality of solder interconnects284may be a plurality of dummy solder interconnects. Stage17ofFIG. 7Fillustrates an example of solder interconnects being coupled to at least one dummy interconnect.

Exemplary Sequence for Fabricating a Package Comprising Dummy Interconnects

FIG. 9(which includesFIGS. 9A-9C) illustrates an exemplary sequence for providing or fabricating a package that includes dummy interconnects. In some implementations, the sequence ofFIGS. 9A-9Cmay be used to provide or fabricate the package600ofFIG. 6, or any of the packages described in the disclosure.

Stage1, as shown inFIG. 9A, illustrates a state after a substrate (e.g.,202), a first encapsulation layer204, a plurality of passive devices (e.g.,210,212,214,216) and an integrated device218are provided. Stage1ofFIG. 7Amay represent Stage11ofFIG. 7C, and thus may be fabricated in a similar manner as described in Stages1-11ofFIGS. 7A-7C.

Stage2illustrates a state after the integrated device260is coupled to a second surface of the substrate202. The integrated device260is coupled to the substrate202through the plurality of solder interconnects266.

Stage3illustrates a state after a thermal interface material (TIM)460that is formed over the back side of the integrated device260. The TIM460may be optional.

Stage4, as shown inFIG. 9B, illustrates a state after the second encapsulation layer206is formed over the second surface of the substrate202. The second encapsulation layer206may encapsulate the integrated device260and the TIM460. The process of forming and/or disposing the second encapsulation layer206may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

Stage5illustrates a state after cavities960are formed in the second encapsulation layer206. The cavities960may be formed over the TIM460and/or the back side of the integrated device260. An etching process (e.g., lithography process) and/or a laser process may be used to form the cavities960in the second encapsulation layer.

Stage6, as shown inFIG. 9Cillustrates a state after the plurality of vias670, the plurality of encapsulation layer interconnects262and the at least one dummy interconnect264are formed. A plating process and/or a sputtering process may be used to form the plurality of vias670, the plurality of encapsulation layer interconnects262and the at least one dummy interconnect264. The plurality of vias670and the plurality of encapsulation layer interconnects262may be considered the same.

Stage7illustrates a state after the plurality of solder interconnects282is coupled to the plurality of encapsulation layer interconnects262, and the plurality of solder interconnects284is coupled to the at least one dummy interconnect264. The plurality of solder interconnects284may be a plurality of dummy solder interconnects. Stage7may illustrate the package600that includes a plurality of dummy interconnects and a plurality of solder dummy interconnects.

Exemplary Flow Diagram of a Method for Fabricating a Package Comprising Dummy Interconnects

In some implementations, fabricating a package that includes dummy interconnects several processes.FIG. 10illustrates an exemplary flow diagram of a method1000for providing or fabricating a package that includes dummy interconnects. In some implementations, the method1000ofFIG. 10may be used to provide or fabricate the package (e.g.,600) ofFIG. 6described in the disclosure. However, the method1000may be used to provide or fabricate any of the packages described in the disclosure.

It should be noted that the method ofFIG. 10may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating package. In some implementations, the order of the processes may be changed or modified.

The method provides (at1005) a substrate (e.g.,202) that includes at least one dielectric layer (e.g.,220), a plurality of interconnects (e.g.,222), a plurality of passive devices (e.g.,210,212,214,216), an integrated device218, and a first encapsulation layer204. The dielectric layer220may include polymer. Forming the dielectric layer220may include forming cavities in the dielectric layer220. An etching process may be used to form the cavities in the dielectric layer220. The plurality of interconnects222may include vias, traces and/or pads. Forming the plurality of interconnects222may include forming a seed layer, performing a lithography process, a plating process, a stripping process and/or an etching process. A pick and place process may be used to place the passive devices and integrated device over the first surface of the substrate202. Solder interconnects (e.g.,217) may be used to couple the passive devices (e.g.,210,212,214,216) and the integrated device218to the substrate202(e.g., interconnects of the substrate202). The first encapsulation layer204is formed over the first surface of the substrate202such that the first encapsulation layer204encapsulates the passive devices (e.g.,210,212,214,216) and the integrated device218. The process of forming and/or disposing the first encapsulation layer204may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stages1-11ofFIGS. 7A-7Cand Stage1ofFIG. 9A, illustrate examples of providing a substrate, passive devices, an integrated device and an encapsulation layer.

The method couples (at1010) components (e.g., integrated device, passive device) to a second surface of the substrate (e.g.,202). The integrated device260is coupled to the substrate202through the plurality of solder interconnects266. Stage2ofFIG. 9Aillustrates an example of an integrated device coupled to the substrate. A TIM (e.g.460) may be coupled to the back side of the integrated device. Stage3ofFIG. 9Aillustrates an example of a TIM coupled to a back side of the integrated device.

The method forms (at1015) a second encapsulation layer (e.g.,206) over the second surface of the substrate202. The second encapsulation layer206may encapsulate the integrated device260and the TIM460. The process of forming and/or disposing the second encapsulation layer206may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage4ofFIG. 9Billustrates an example of forming a second encapsulation layer.

The method forms (at1020) cavities (e.g.,960) in the second encapsulation layer206. The cavities960may be formed over the TIM460and/or the back side of the integrated device260. An etching process (e.g., lithography process) and/or a laser process may be used to form the cavities960in the second encapsulation layer. Stage5ofFIG. 9Bmay illustrates an example of cavities in the second encapsulation layer.

The method forms (at1025) a plurality of vias670, a plurality of encapsulation layer interconnects262and the at least one dummy interconnect264in the cavities (e.g.,960). A plating process and/or a sputtering process may be used to form the plurality of vias670, the plurality of encapsulation layer interconnects262and the at least one dummy interconnect264. The plurality of vias670and the plurality of encapsulation layer interconnects262may be considered the same. Stage6ofFIG. 9Cillustrates an example a plurality of vias670, a plurality of encapsulation layer interconnects262and the at least one dummy interconnect264in the second encapsulation layer206.

The method couples (at1030) (i) a plurality of solder interconnects282to the plurality of encapsulation layer interconnects262, and (ii) a plurality of solder interconnects284is coupled to the at least one dummy interconnect264. The plurality of solder interconnects284may be a plurality of dummy solder interconnects. Stage7ofFIG. 9Cmay illustrate an example of a plurality of solder dummy interconnects.

Exemplary Electronic Devices

FIG. 11illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package, package-on-package (PoP), System in Package (SiP), or System on Chip (SoC). For example, a mobile phone device1102, a laptop computer device1104, a fixed location terminal device1106, a wearable device1108, or automotive vehicle1110may include a device1100as described herein. The device1100may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices1102,1104,1106and1108and the vehicle1110illustrated inFIG. 11are merely exemplary. Other electronic devices may also feature the device1100including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated inFIGS. 2-6, 7A-7F, 8, 9A-9C, and/or10-11may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be notedFIGS. 2-6, 7A-7F, 8, 9A-9C, and/or10-11and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations,FIGS. 2-6, 7A-7F, 8, 9A-9C, and/or10-11and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.

In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and/or an under bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., seed layer+metal layer). In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a current (e.g., a data signal, ground or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form the interconnects. In some implementations, a chemical vapor deposition (CVD) process and/or a physical vapor deposition (PVD) process for forming the interconnects. For example, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.