Memory system such as a dual-inline memory module (DIMM) and computer system using the memory system

A memory system (250) includes a plurality of memory devices (260) adapted to be coupled to an interface (140), an indicator (272) for indicating a type of the plurality of memory devices (260), and an override circuit (280) having a first terminal adapted to be coupled to the interface (140), a second terminal coupled to the plurality of the memory devices (260), and a control input for receiving a control signal. The override circuit (280) is responsive to the control signal to alter an operation of the memory system (250).

FIELD OF THE DISCLOSURE

The invention relates generally to memory systems, and more particularly to interface circuits for memory systems.

BACKGROUND

A typical data processing system, such as a computer, microcomputer, embedded microcontroller, or other computational device, includes a central processing unit (CPU), a peripheral device interface, and a memory device. The memory device stores instructions, which are executed by the data processing system to perform a desired task. The data processing system stores and retrieves information at the memory device using an appropriate memory interface device and memory interface protocol. The memory interface protocol is often promulgated as an industry standard.

Standards are often developed and ratified by industry representatives to facilitate interoperability of device components provided by multiple manufactures. Industry standards are prevalent in the electronics industry, and cover most aspects of technology, including memory interfaces. Memory device standards can define electrical, operational, and physical attributes of a memory device so that manufacturers of individual components of a data processing system can ensure operability with memory devices provided by different memory device manufacturers.

The Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association is the semiconductor engineering standardization body of the Electronic Industries Alliance (EIA). JEDEC has set forth a memory device standard referred to as double data rate (DDR) synchronous dynamic random access memory (SDRAM) that is currently especially popular. The original DDR JEDEC standardization specification was published in the year 2000. The original DDR standard (referred to here as DDR1) was very successful and subsequent variations of the DDR standard have been adopted by industry, such as DDR2 and DDR3, which describe memory devices with increased access bandwidth and operating frequency. However, memory devices that comply with one memory standard typically cannot be substituted for devices compliant to a different memory standard.

New memory standards are revised and introduced with such regularity that the longevity of a particular standard can be relatively short. Memory suppliers are quick to transfer development and manufacturing resources to reflect a revised standard. As a result, manufacturers of equipment that interface to memory devices must regularly re-design their products to operate with memory devices that comply with the newest standard, or else stockpile inventory of memory devices that can otherwise become unavailable or prohibitively expensive.

DETAILED DESCRIPTION

FIG. 1illustrates in block diagram form a data processing system100known in the prior art. Data processing system100generally includes a microprocessor110, a peripheral component interconnect (PCI) bus120, labeled “PCI BUS,” a PCI bus peripheral122, a south bridge124, a basic input/output system (BIOS) read only memory (ROM)130, a memory interface140, and a dual inline memory module (DIMM)150. Microprocessor110includes a CPU core112, a crossbar switch114, a PCI bus bridge118, and a DDR1 synchronous dynamic random access memory (SDRAM) controller116. DIMM150includes DDR1 SDRAMs152,154, and156.

Cross bar switch114has a first bidirectional interface to CPU core112, a second bidirectional interface to PCI bus bridge118, and a third bidirectional interface to DDR1 SDRAM controller116. PCI bus bridge118has a second bidirectional interface to PCI bus120, connected to PCI bus peripheral122and to south bridge124. South bridge124has a second bidirectional interface to BIOS ROM130, and a third bidirectional interface, an Inter-Integrated circuit (I2C) interface labeled “I2C BUS,” to DIMM150. DDR1 SDRAM controller116has a second bidirectional interface140to DIMM150.

CPU core112exchanges information with PCI bus peripheral122by configuring crossbar switch114to support communication to PCI bus bridge118. PCI bus bridge118translates accesses from the internal bus protocol of microprocessor110into a PCI standard bus protocol of PCI bus120. CPU core112accesses information stored in BIOS ROM130by issuing a read request and addressing BIOS ROM130. PCI bridge118transmits the request to south bridge124, and south bridge124performs the requested memory access of BIOS ROM130. BIOS ROM130provides the requested information and the information is communicated back to CPU112via PCI bus120and the internal interfaces at microprocessor110. South bridge124is a particular PCI bus peripheral device that can provide additional functionality that may not be present at microprocessor110, such as a hard disk drive interface, a universal synchronous bus (USB) interface, an audio codec, and interfaces to other general input/output (IO) devices.

CPU core112exchanges information with memory device150via DDR1 SDRAM controller116. DDR1 SDRAM controller116provides an electrical and functional interface to DIMM150using signals and protocols commensurate with the JEDEC DDR1 standard. A DIMM, such as DIMM150, is available in a physically smaller package variation known as a small outline dual in-line memory module (SO-DIMM), and thus provides an advantage for use in compact electronic device products. Microprocessor110accesses a serial presence detect (SPD) device at DIMM150via the I2C bus that interfaces south bridge124to DIMM150. I2C is a multi-master serial computer interface.

When power or a reset signal is applied to data processing system100, microprocessor110begins accessing instructions stored at BIOS ROM130. Microprocessor110must initialize DIMM150as specified by the JEDEC DDR standard before microprocessor110can access DIMM150. A portion of the instructions stored at BIOS ROM130implements a memory initialization procedure. The initialization procedure begins when microprocessor110, under the control of BIOS130, accesses the SPD device at DIMM150through the I2C bus to determine memory system attributes such as memory speed, size, and the like, followed by initializing two mode registers, MR and EMR included at each of memory devices152,154, and156. DDR1 SDRAM controller116initializes and subsequently accesses DIMM150via memory interface140. SDRAM controller116issues MODE REGISTER SET commands to store appropriate data into MR and EMR. Once the initialization procedure is complete, microprocessor110can access DIMM150by performing read and write commands

Processors and memory systems, such as microprocessor110and DIMM150, are often subcomponents of electronic devices such as consumer appliances or industrial controllers. The processor subcomponent can be referred to as an embedded processor. The electronic device can have a long production lifetime, and can be manufactured and sold for many years. Throughout the production lifetime, the manufacturer of the electronic device must be ensured of continued and economical access to the subcomponents required to implement the electronic device. Due to the quick evolution of memory standards, manufacturers of electronic devices can experience particular difficulty procuring memory devices from a previous memory standard generation after a new memory standard becomes popular. For example, an electronic device that was designed to use DDR1 memory devices may well remain marketable even though the DDR1 memory devices may have become unavailable or prohibitively expensive. In such a case, the manufacturer of the electronic device would traditionally require the memory controller on the microprocessor to be re-designed to support the newer memory standard, such as DDR2. Alternatively, the manufacturer must estimate and procure adequate quantities of DDR1 devices, while such devices remain available, to ensure a supply of memory devices throughout the manufacturing lifetime of the electronic device.

Moreover, a microprocessor, such as microprocessor110that include DDR1 SDRAM controller116, is typically designed and fabricated as a monolithic integrated circuit on a single silicon substrate. Modifying the design of microprocessor110, such as to update DDR1 SDRAM controller116to support a new memory standard, such as DDR2, can be very expensive. In addition to engineering time and resources, new fabrication photo-masks, production test software and hardware development, and design qualification procedures are required to bring a modified microprocessor design to market. Furthermore, the original engineering team that is familiar with the microprocessor design may no longer be available to make complex revisions to a legacy integrated circuit product.

A memory system and methods are disclosed herein that alters an operation of a memory system in response to a control signal received from an interface, and based upon an indication of a type of memory device included at the memory system. For example, a processor that supports the access of DDR1 memory devices, such as microprocessor110, can access a memory system that includes DDR2 memory devices without re-designing the processor.

FIG. 2illustrates in block diagram form a data processing system200according to the present invention. Data processing system200generally includes microprocessor110, PCI BUS120, PCI bus peripheral122, south bridge124, and a memory interface140, as described above. However, data processing system200also includes a modified BIOS ROM230and a DDR2 DIMM250. DIMM250is a memory system that generally includes DDR2 memories260, a complex programmable logic device (CLPD)270, a bus switch284, and a voltage regulator290. CLPD270further includes an I2C bus interface275, a command translator282, and a SPD device271that further includes a key register272. CPLD270and bus switch284together provide an override circuit280. Memories260further includes a set of DDR2 memory devices including representative DDR2 memory devices262,264, and266.

Memory interface140is the same as inFIG. 1but is shown in greater detail here, in which it conducts individual signals labeled “CS0#” and “CS1#”, “DQ”, “DQS”, “DQM”, “CLK”, “RAS#”, “CAS#”, “WE#”, “CKE”, “ADDR”, and “BA.”

DDR2 memory devices262,264, and266each have a two-bit input terminal to receive chip select signals CS0# and CS1#, a 64-bit input/output terminal to receive data signal DQ, an eight-bit input/output terminal to receive data strobe signal DQS, an eight-bit input terminal to receive data mask signal DQM, a two-bit input terminal to receive a clock signal CLK, and a four-bit input terminal to receive row address strobe signal RAS#, column address strobe signal CAS#, write enable signal WE#, and clock enable signal CKE, all signals conducted by memory interface140. Each of DDR2 memory devices262,264, and266also has a fourteen-bit input terminal to receive an address signal, and a two-bit input terminal to receive a bank address signal. Bus switch284has a first input terminal to receive a fourteen-bit address signal ADDR[13:0], and a second input terminal to receive a two-bit bank address signal BA[1:0], both signals conducted by memory interface140. Bus switch284also has a third input terminal, a first output terminal to provide the fourteen-bit address signal to DDR2 memory devices262,264, and266, and a second output terminal to provide the two-bit bank address to memory devices262,264, and266.

Voltage regulator290has an output to provide a 1.5 V voltage reference signal to CLPD270. I2C bus interface275has an input/output terminal connected to the I2C bus to exchange information with south bridge124, an output, and a bidirectional interface to SPD device271. Command translator282has an input connected to the output of I2C bus interface275, a first output connected to the third input of bus switch284to provide a signal labeled “ENABLE”, a second output to also provide the fourteen-bit address signal to DDR2 memory devices262,264, and266, and a third output to also provide the two-bit bank address to memory devices262,264, and266.

The operation of microprocessor110, PCI BUS120, PCI bus peripheral122, south bridge124, and BIOS ROM230is described with reference toFIG. 1. The initialization procedure implemented by instructions stored at BIOS ROM230determines what type of DDR memories are incorporated at DIMM250, and performs a memory initialization procedure appropriate for that type of memory. When power or a reset signal is applied to data processing system200, microprocessor110begins accessing instructions stored at BIOS ROM230. Before microprocessor110can access DIMM250, DIMM250is initialized as specified by the appropriate JEDEC standard. The initialization procedure begins when microprocessor110, under the control of BIOS230, accesses key register272of SPD device271at CPLD270. A particular data value stored at key register272provides an indicator to microprocessor110that identifies DIMM250as a memory system incorporating DDR2 type memories260. SPD device271is configured to indicate the presence of DDR2 type memories by setting a previously unused and reserved SPD register bit location (byte two, bit seven) to a value of one. The BIOS also acquires other memory system attributes such as memory speed, size, and the like, from SPD device271. The BIOS stored at BIOS ROM230is capable of initializing memory systems that include either DDR1 or DDR2 memory devices.

In order to initialize DDR2 memories260, appropriate data values must be stored in four mode registers known as MR, EMR, EMR2, and EMR3included at each of memories262,264, and266. Microprocessor110, and DDR1 SDRAM controller116in particular, is designed to initialize the mode registers included at DDR1 memory devices, but since it was designed for DDR1 memory devices, cannot directly initialize the additional DDR2 mode registers EMR2and EMR3. However, the BIOS controls override circuit280to alter the operation of DIMM250such that microprocessor110and DDR1 SDRAM controller116can properly initialize DDR2 memories260. Override circuit280intercepts values supplied by SDRAM controller116and instead provides override values to memories260. The override values are provided to CPLD270by microprocessor110via the I2C interface bus. The override values include bank address information used to select a specific mode register, and mode register values to load into the selected mode register.

To perform a MODE REGISTER SET command, DDR1 SDRAM controller116activates selected one of signals CS0#/CS1#, RAS#, CAS#, and WE# as specified by the JEDEC DDR standard. In response to a MODE REGISTER SET command, a data value present at the fourteen-bit address input at each of memory devices262,264, and266is loaded into a mode register of each memory device. The particular mode register that is loaded is specified by a value present at the two-bit bank address input at each of memory devices262,264, and266. In the particular embodiment illustrated, command translator282is a control circuit that receives a control signal from microprocessor110via the I2C bus interface, the control signal indicating that a MODE REGISTER SET command is forthcoming. In response to the control signal, command translator282can activate or deactivate signal ENABLE and thereby select which of either of bus switch284, or command translator282, is to provide address and data information to memories260. During the memory initialization procedure, command translator282will provide this information to memories260. After the memory initialization procedure is complete, DDR1 SDRAM controller116will provide this information to memories260via bus switch284.

FIG. 3illustrates in partial schematic and partial logic diagram form bus switch284ofFIG. 2. Bus switch284includes n-type metal oxide semiconductor (NMOS) transistors302,304,306, and308, p-type metal oxide semiconductor (PMOS) transistors303,305,307, and309, and an inverter301. Inverter301has an input to receive signal ENABLE, and an output. Each of transistors302and303has a first drain/source (D/S) terminal to receive signal ADDR[13] and a second D/S terminal to provide signal memory address13. Each of transistors304and305has a first drain/source (D/S) terminal to receive signal ADDR[0] and a second D/S terminal to provide signal memory address[0]. Each of transistors306and307has a first drain/source (D/S) terminal to receive signal BA[1] and a second D/S terminal to provide a memory BA[1] signal. Transistors308and309each has a first drain/source (D/S) terminal to receive signal BA[0] and a second D/S terminal to provide a memory BA[0] signal. NMOS transistors302,304,306, and308each has a gate to receive signal ENABLE, and PMOS transistors303,305,307, and309each has a gate connected to the output of inverter301. Transistors corresponding to address signals ADDR[12-1] are omitted fromFIG. 3for clarity.

During the memory initialization procedure, command translator282, under BIOS control, sets signal ENABLE to a logic-low value, and transistors302-309are thus configured to be in an open circuit state. During this time, command translator282can provide mode register select and data information. After the initialization procedure has completed, command translator282sets signal ENABLE to a logic-high value, and each of transistors302-309are thus configured to conduct a signal present on their first D/S terminal to their corresponding second D/S terminal. Thus, signals provided by DDR1 SDRAM controller116are conducted through bus switch284, and supplied to memories260. Bus switch284is implemented using complementary MOS (CMOS) transmission gates, and signals conducted by bus switch284are not substantially delayed and the integrity of the signals is not substantially degraded. Bus switch284can be implemented using other circuit techniques that provide a desired minimum propagation delay. This permits microprocessor110to access DDR2 memories260at substantially the same speed that it can access DDR1 type memory devices.

FIG. 4illustrates a flow diagram400of a memory system initialization sequence that can be performed by data processing system200atFIG. 2. At block402, microprocessor110begins executing an initialization program stored in BIOS ROM230. At block404, microprocessor110reads SPD information from override circuit280, via the I2C bus, to determine whether DIMM250includes DDR1 or DDR2 type memory devices. Decision block406directs the procedure to block408if DIMM250includes DDR2 memory devices, and to block428if DIMM250includes DDR1 memory devices. At block408, having determined that DIMM250includes DDR2 memory devices, processor110, based on information stored in BIOS ROM230, configures override circuit280to disable connectivity of bus switch284, and to enable command translator282to instead drive memories260.

At block410, microprocessor110provides override circuit280with the particular data value specified for mode register MR, and this value is provided to the fourteen-bit address input of each of memory devices260,262, and264by command translator282. At block412, microprocessor110issues a MODE REGISTER SET command to DDR2 DIMM250to load the mode register data from override circuit280into mode register MR. Microprocessor110is performing a MODE REGISTER SET command, appropriately configuring signals CS0#/CS1#, RAS#, CAS#, and WE# and CLK, but the mode register address and data information provided by DDR1 SDRAM controller116is not communicated to memory devices260by bus switch284. Instead, address and data information is provided by command translator282.

At block414, microprocessor110provides override circuit280with the particular data value specified for mode register EMR, and this value is provided to the fourteen-bit address input of each of memory devices260,262, and264by command translator282. At block416, microprocessor110performs a MODE REGISTER SET command to DDR2 DIMM250to load the mode register data from override circuit280into mode register EMR.

At block418, microprocessor110provides override circuit280with the particular data value specified for mode register EMR2, and this value is provided to the fourteen-bit address input of each of memory devices260,262, and264by command translator282. At block420, microprocessor110issues a MODE REGISTER SET command to DDR2 DIMM250to load the mode register data from override circuit280into mode register EMR2.

At block422, microprocessor110provides override circuit280with the particular data value specified for mode register EMR3, and this value is provided to the fourteen-bit address input of each of memory devices260,262, and264by command translator282. At block424, microprocessor110issues a MODE REGISTER SET command to DDR2 DIMM250to load the mode register data from override circuit280into mode register EMR3.

Having completed loading mode registers MR, EMR, EMR2, and EMR3, processor110provides a control signal to command translator282, instructing command translator282to re-enable connectivity of bus switch284, and to disable command translator426memory interface drivers. Thus, the fourteen-bit address input and the two-bit bank address input of memory devices260,262, and264are provided by DDR1 SDRAM controller116instead of command translator282. At block430, initialization of memories260is complete, and DDR1 SDRAM controller116at microprocessor110and can perform memory accesses with DIMM250.

FIG. 5illustrates JEDEC standard mode register definitions500for DDR1 and DDR2 memory devices in a table format. During the memory initialization procedure, microprocessor110determines if DIMM250includes DDR1 or DDR2 memory devices. If DDR1 memory devices are detected, as indicated by a value stored at a register bit location at the key register of the SPD device, DDR1 SDRAM controller116uses MODE REGISTER SET commands to initialize mode registers MR and EMR as specified at table510. If DDR2 memory devices are detected, override circuit280alters the operation of DIMM250in response to signals received from the interface of data processing system200, and DDR1 SDRAM controller116uses MODE REGISTER SET commands, along with override circuit280, to initialize mode registers MR, EMR, EMR2and EMR3as specified at table520.

An override circuit, such as override circuit280, intercepts and alters data values provided by a microprocessor as illustrated, but may alter the operation of a memory system, such as DIMM250, in other ways. For example, an override circuit can receive control signals that correspond to memory commands that comply with one memory standard, and provide a translation of the memory commands to comply with another memory standard. Memory commands used to access, initialize, or otherwise configure a memory device can be received by an override circuit, and these commands can be converted into appropriate signals that are compliant with the electrical, timing, and functional protocol of another type of memory device. An indicator, such as a register data or signal value can identify the type of memory device present in the memory system and reconfigure the memory system to support the indicated memory type.

Note that override circuit280, voltage regulator290, and memories260can be incorporated into a DIMM or SO-DIMM, or can be physically organized in another manner. A manufacturer of an electronic device may prefer to use a custom memory module, such as DIMM250to avoid re-designing the main circuit board. In so doing, the manufacturer can substitute the custom memory modules containing DDR2 memory devices, include a revised initialization procedure at BIOS ROM230, adjust power supply voltages if appropriate, and no further design modifications will be required. Alternatively, the manufacturer of an electronic device may prefer to re-design the main circuit board while using standard off-the-shelf DIMMs. Such an arrangement may be preferable if the main circuit board is already being re-designed. For example, override circuit280and voltage regulator290can be added to the main circuit board to allow it to use unmodified DDR2 DIMMs.

While the use of CPLD device technology is illustrated, another device technology such as PLD, FPGA, or discrete components can be used to implement all or a portion of override circuit280or of memory system250.

Bridging from one memory interface standard to another standard can include a corresponding change in operating voltage of the memory devices. Voltage regulator290is included in DIMM250to illustrate a specific example of how a voltage regulator can be used to facilitate the use of devices with disparate operating voltage specifications. In the illustrated example, CPLD device270is designed to operate with a supply voltage of 1.5 volts, while the remainder of data processing system200operates at a 1.8 volt supply voltage potential. Power supply voltages may be configured by changing a resistor value, or a device may be designed to allow the voltages to be dynamically changed using a general purpose I/O (GPIO) and suitable circuitry. Skilled artisans will appreciate that specific supply voltage specifications can be supported with suitable partitioning of supply voltage domains, and by incorporating one or more voltage regulators to provide power to each domain. A level shifter circuit can be added to adjust the voltage level of a signal that passes from one voltage domain to another, if needed. For example, level shifters and a voltage regulator can be used by a DDR2 to DDR3 bridge circuit to supply the DDR3 memory devices with signals and power supply voltage at a different potential than used by other portions of an electronic device.