Method and tester for verifying the electrical connection integrity of a component to a substrate

A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.

BACKGROUND

Small and compact printed circuit assemblies (PCA) with miniature surface mount technology (SMT) components and custom application-specific integrated circuits (ASICs) installed on dual-sided, multi-layer printed circuit boards (PCBs) are now common. The spacing between the pins of the components becomes smaller as the designs are made to fit into smaller physical configurations. The physical spacing, such as pin spacing and wire trace spacing, is further reduced when the assembly is intended to be portable, such as an assembly for a modem designed to support the Personal Computer Memory Card International Association (PCMCIA) standard.

It is often difficult to determine if a component has been installed correctly in such a crowded and densely populated PCA. More particularly stated, it is often difficult to determine the integrity of the electrical connection between the wire traces of the PCB and the pins or leads of the installed component. The component may be an electronic device or a connector. One method of testing a PCA involves the use of a “bed of nails” test fixture with a conventional in-circuit tester, such as a 3070 Board Tester manufactured and distributed by Agilent Technologies of Santa Clara, Calif. The bed of nails test fixture provides a number of contact probes for accessing test points on the PCA. For the test method to work, there must be contact between the probes of the fixture and the component or signal paths on the PCA. The method is often called a “bed of nails” testing method because the probes are typically sharp metal contact probes configured so that the PCA can be placed on the “bed of nails” and tested. In this manner, the probes touch or access various parts of the component or the signal paths on the PCA and thereby allow measurements to be made.

Typically, the component is stimulated through signals provided through the probes. Measurements obtained from the component via other probes are then compared to “correct” values to determine if the component on the PCA is installed correctly. However, the test probes must be in contact with the appropriate signal paths for this testing method to work. Densely populated printed circuit assemblies often have inaccessible signal paths, such as wire traces beneath multiple layers on the printed circuit board assembly, thereby hampering the use of such a “bed of nails” test fixture. Therefore, “bed of nails” test fixtures are often ineffective when attempting to test a densely populated PCA.

A non-contact testing method for testing the integrity of a device's connections is capacitive testing. An example of capacitive testing is disclosed in U.S. Pat. No. 5,254,953; Crook et al., entitled “Identification of Pin-Open Faults by Capacitively Coupling through the Integrated Circuit Package”. In this patent, a system is disclosed for determining whether pins of an integrated circuit (IC) device are properly soldered to a printed circuit board (PCB) of a printed circuit assembly (PCA). A capacitive sensor is positioned over the IC device while a test probe contacts a pin under test via a pad and a connection between the pin and the pad. A 0.2 volt 10 kHz alternating current (AC) test signal is injected via the test probe into the pad connected to the pin under test. The capacitive sensor then detects this test signal via the capacitive coupling between the pin and the bottom of the capacitive sensor. The capacitive sensor converts the AC signal to an intermediate signal called a detection signal, by low-pass filtering the AC signal. The value of the detection signal is proportional to the detected amplitude of the AC signal. In this manner, the value of the detection signal from the capacitive sensor may be compared to a threshold value to determine characteristics about the detected AC signal (such as the strength of the AC signal). If the electrical connection between the test probe, the pad, and the pin under test is open, the value of the detection signal will be much smaller than anticipated. An in-circuit tester (not shown) connected to the capacitive sensor then indicates that the PCA has failed the test and declares that the pin under test is open.

In capacitive testing, several cycles, for example five cycles, of the 10 kHz analog test signal is required to test the integrity of one pin. That is, it takes as long as 500 μsec to test one single pin. Moreover, probe access to the pin under test is still required to apply the test signal for such capacitive testing. Thus capacitive testing would still be ineffective in a circuit assembly where test probe access to the pin under test is not available, such as a densely populated circuit assembly where the pin spacing and wire trace spacing are extremely small.

U.S. Pat. No. 6,104,198; Brooks, entitled “Testing the Integrity of an Electrical Connection to a Device Using an Onboard Controllable Signal Source” discloses the use of an on-board microprocessor or BSCAN device as a controllable signal source for sequentially applying a 10 kHz signal to each pin under test of a device. This solution at least partially eliminates the access problem. However, testing throughput may still be a concern, especially if there are a large number of pins to be tested. Furthermore, the need to generate a 10 kHz signal limits the application of this technique.

DETAILED DESCRIPTION OF THE EMBODIMENTS

As shown in the drawings for purposes of illustration, the invention is embodied in a novel method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate. The component includes but is not limited to an integrated circuit (IC) device, a connector, an active component such as diode, transistor, FET and a passive component such as a capacitor, capacitor pack, a resistor or a resistor pack. Indexed testing or coupon testing known to those skilled in the art for determining the value of a resistor may additionally be performed to determine if a resistor pack having the correct resistor value is placed on the substrate. The resistor pack may be connected to signal paths between two components or used as pull up, pull down or termination resistors. The substrate may be a printed circuit board (PCB), a flexible circuit or the like. The signal path may be on the surface of or embedded in the substrate. In general, the integrity of the electrical contact is determined by whether the electrical contact, such as a pin or solder pad of the component, is properly connected to the signal path of the substrate. An example of a good electrical connection of an electrical contact is one where the electrical contact is properly soldered to only the appropriate signal path of the substrate. A bad electrical connection for an electrical contact is one where the electrical contact is improperly soldered to result in either an open circuit or a short circuit on the substrate, or the signal path of the substrate to which the electrical contact is to be soldered to is broken or shorted to another signal path. Generally, the method includes generating a step signal on one of the at least one signal path connected to a respective contact, capturing a capacitively coupled signal due to the step signal at the contact, and determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. The method allows for relatively quick detection of a bad electrical connection, where there may or may not be probe access to the substrate. The use of a step signal allows this method to be used for verifying the electrical connection integrity of many circuit components in different circuit topologies under different testing situations.

FIG. 1is a block diagram of a general test system2according to an embodiment of the invention for implementing the above described method to test the integrity of the electrical connection of a number of electrical contacts4a-4dof a component6to respective signal paths8a-8dof a PCB14without requiring probe access to the electrical contacts4a-4dor the signal paths8a-8d. The system2includes a tester10and a printed circuit assembly (PCA)12under test. The PCA12includes the printed circuit board (PCB)14with signal paths thereon or therein, and the component6having electrical contacts4a-4dsoldered to the appropriate signal paths8a-8d. The tester10includes a programmable controller16and a capacitive sensor18connected to the programmable controller16. The programmable controller16is also connected to a controllable signal source20which may be a part of the tester10, a fixture (not shown) connected to the tester10or the PCA12. The controllable signal source20may be an integrated circuit (IC) soldered onto the PCB14. Such an integrated circuit (IC) includes but is not limited to a microprocessor, a microcontroller, an in-circuit emulator therefor, a field programmable gate array (FPGA), a boundary scan (BSCAN) device, a memory device or a logic gate device. Test signal output leads22a-22dof the controllable signal source20may be directly electrically connected to the signal paths8a-8das shown inFIG. 1or through passive components such as but not limited to resistors or capacitors (not shown). Alternatively, the controllable signal source20may be connected to control another IC (not shown) that is in turn connected to the signal paths8a-8d.

During use to test the integrity of the electrical connection between the contacts4a-4dof the component6and the signal paths8a-8dof the PCB14, the capacitive sensor18is placed proximate to the component6. In other words, the capacitive sensor18is placed either close to or in contact with a housing (not shown) of the component6such that the capacitive sensor18is spaced apart from the contacts4a-4dto be able to capacitively pick up a signal thereat. The programmable controller16commands the signal source20to output a step signal on each of its test signal output lead22a-22dso as to introduce the step signal via a respective signal path8a-8dto a contact4a-4dunder test. When the signal source20outputs the step signal, the programmable controller16captures a capacitively coupled signal using the capacitive sensor18. The programmable controller16then determines the integrity of the electrical connection of the electrical contact4a-4dbased on one or more characteristics of the capacitively coupled signal. Alternatively, the programmable controller16may also determine the integrity of the electrical connection based on one or more characteristics of a response signal obtained by passing the capacitively coupled signal through a measurement module17(FIG. 2). For example, the response signal may be a damped response signal obtained by amplifying the capacitively coupled signal using an amplifier circuit in the measurement module17. This damped response signal may be an under-damped, an over-damped or a critically-damped signal. The characteristics of either the capacitively coupled signal or the response signal include, but are not limited to, the amplitude, phase, timing, and frequency of the signal, and in some embodiments, the number of transitions in the response signal. The sequence90(FIG. 4) of steps for verifying electrical connection integrity will be described in more detail shortly.

In one embodiment, determining the integrity of the electrical connection may include digitizing the response signal to obtain samples thereof and performing digital signal processing on the samples to obtain the characteristic of the response signal. For example, the programmable controller16may perform Discrete Fourier Transform (DFT) on the samples to obtain the amplitude of a characteristic frequency component of the response signal. This amplitude may then be used for determining if the electrical connection is good or bad. Other forms of digital signal processing that may be used include, but are not limited to, Fast Fourier Transform (FFT) and filtering using a digital filter such as a Finite Impulse Response (FIR) filter and an Infinite Impulse Response (IIR) filter. The necessary analogue to digital (A/D) conversion and the digital signal processing may be carried out by the measurement module17or the programmable controller16. Digital signal processing may be performed by hardware, firmware, software or a combination thereof.

When testing the integrity of the electrical connection of more than one contact, a step signal may be applied to the contacts4a-4done by one in sequence and the corresponding response signal portion may be captured using the capacitive sensor18. In this case, the response signal includes a number of response signal portions. There is a one to one correspondence between a step signal applied to a contact and a response signal portion. The step signals for determining electrical connection integrity of a number of contacts need not be in any particular sequence so long as the transition in the step signal for one contact does not coincide with the transitions in the step signals for the other contacts. From the respective response signal portion, the programmable controller16is able to determine if the electrical connection involving a contact4a-4dis good or bad. In this manner, the integrity of electrical connection of each contact4a-4dmay in turn be verified. Since the result of the verification is dependent on the step signal reaching the contact under test and no other contacts of the component, it should be appreciated that a component having an output enable (OE) pin and a chip select (CS) pin should have those pins appropriately controlled when generating the step signals so that no undesirable signals appear at the other contacts to be picked up by the capacitive sensor. It is also possible to verify the electrical connection of the contacts4a-4dall at once. In order to do so, a step signal is applied to each electrical contact4a-4dsimultaneously. In this case the capacitively coupled signal captured by the capacitive sensor is a result of a combination of the simultaneously applied step signals at all the contacts4a-4d. The magnitude of such a capacitively coupled signal is larger than the magnitude of the signal portion due to a step signal at a single contact. A combination of sequential test and simultaneous test may be used for example in functional testing. Simultaneous testing is carried out first to determine if the electrical connection of all the contacts is good. If that is the case, it may not be necessary to perform the sequential test. However, if it is determined that not all the electrical connections are good, the sequential test is then carried out to determine which of the electrical connections are bad.

FIG. 11shows an in-circuit test system230according to another embodiment that includes a device232, which supports the IEEE 1149.1 Standard Test Access Port and Boundary Scan (BSCAN) Architecture, as the controllable signal source. This BSCAN device232can therefore generate the step signals. The test system230further includes a programmable controller34, a BSCAN controller236, a bed of nails test fixture38and a capacitive sensor18. In one embodiment, the programmable controller34is a computer that controls the operation of the in-circuit test system230and is capable of controlling and positioning the capacitive sensor18with respect to a populated PCA40.

The programmable controller34controls the BSCAN device232through the BSCAN controller236and the test fixture38. The BSCAN controller236is basically an interface circuit responsive to commands from the programmable controller34. The BSCAN controller236receives commands from the programmable controller34on a controller input242and, in response, provides a control signal on a controller input/output (I/O)244. The controller I/O244is connected to a test probe46of the test fixture38. The BSCAN device232has an I/O lead (or leads)48which is connected to a contact pad or test point50via an electrical connector52. The probe46contacts the test point50. Although one such test point50is illustrated, it is known that the BSCAN device232requires more than one I/O signal (e.g. TCK, TMS, TDI, TDO) and thus a corresponding number of test points50are required. The I/O signal is applied to the input lead48of the BSCAN device232, through the contact probe46, the test point50, and the connector52. In this manner, the programmable controller34is operable to initiate generation of the step signal at a selected test signal output lead254a-254dof the BSCAN device232.

The BSCAN device232only functions as a controllable signal source during the electrical connection integrity test. This same BSCAN device232operates as another part of the PCA40during normal operation. Each test signal output lead254a-254dof the BSCAN device232is connected, via a first electrical connector256a-256d, to an electrical signal path58a-58dto which the electrical contact4a-4dof the component6is also connected via a second electrical connector60a-60d. Thus, the step signal generated by the BSCAN device232can be applied to the electrical contact4a-4dof the component6even though the signal path58a-58dmaybe inaccessible to a test probe.

The BSCAN device232includes a chain270of output cells272a-272dconnected to the test signal output leads254a-254d. When the programmable controller34instructs the BSCAN controller236to control the BSCAN device232to generate a step signal, energy from the contact4a-4dcoupled through to the capacitive sensor18allows the capacitive sensor to pick up a capacitively coupled signal (not shown). A sensor amplifier in a measurement module17connected between the capacitive sensor18and the programmable controller34converts the capacitively coupled signal to a response signal280(FIG. 12). In this embodiment, the measurement module17carries out digital signal processing on the response signal280as described above. The measurement module17and the capacitive sensor18may reside on the fixture38, although they are shown to be separate from the fixture38inFIG. 11.

While only a single capacitive sensor18is illustrated inFIG. 11, the invention may be practiced using a group of sensors (not shown), with the illustrated capacitive sensor18being a selected one of the group of sensors. In this manner, the programmable controller34is capable of selecting the particular capacitive sensor18necessary to determine the integrity of the electrical connection between the electrical contacts4a-4dof the component6and the signal paths58a-58dof a PCB86. It is also possible to simultaneously capture and process another response signal obtained from another component (not shown) connected in parallel to the component6using a separate capacitive sensor so as to speed up electrical connection integrity testing of PCB86. It should be noted that the characteristics of the capacitively coupled signal depend on the characteristics, such as physical size, of the capacitive sensors. The capacitively coupled signal may also be affected by noise. Thus, the capacitance of the capacitive sensor18may be changed by connecting/disconnecting one or more capacitors to/from the capacitive sensor18. Alternatively or additionally, the measurement module17, more specifically the amplifier and/or the DSP thereof, may be configured to process the capacitively coupled signal so as to increase the integrity of the response signal. Instead of having a capacitive sensor for each component, it is also possible to have one capacitive sensor straddling more than one component.

With reference toFIG. 10, the programmable controller34generally includes a central processing unit (CPU)200that is coupled to a random access memory (RAM)202, a read only memory (ROM)204, a non-volatile storage unit206and other peripheral devices208via an internal bus210. The bus210carries data signals, control signals and power to the various components of the programmable controller34. The non-volatile storage unit206may be a floppy disk, a compact disc (CD), a chip card or a hard disk. The other peripheral devices208may include a display, a keyboard, a mouse, and other device-specific components (all not shown). The display may be a video display, LCD display, touch-sensitive display, or other display types. The ROM204or the non-volatile storage unit206may serve as a program storage device for storing a program of instructions that is executable by the CPU200for implementing the respective portion of the sequence90. The program may be implemented in any high level or low level programming languages.

With the aid ofFIGS. 12 and 13, the operation of the in-circuit test system230inFIG. 11will be described in more detail next.FIG. 13shows a sequence290of steps implemented in the in-circuit test system230for performing the electrical connection integrity test to determine if there is any open circuit. The sequence290starts in a PLACE SENSOR step292, wherein the capacitive sensor18is placed over the electrical contacts4a-4dof the component6to be proximate thereto. In one embodiment, the capacitive sensor18is rigidly fixed in a position and the PCA40is brought towards the capacitive sensor18so that the capacitive sensor18is proximate the component6. However, in an alternative embodiment, the capacitive sensor18can be robotically positioned at the desired location in response to a command from the programmable controller34.

The sequence290next proceeds to a SHIFT FIRST TEST VECTOR INTO BSCAN DATA REGISTERS step292, wherein the programmable controller34instructs the BSCAN controller236to generate the appropriate I/O signal at its control I/O44to shift a first test vector into the register (not shown) of each of the cells of the BSCAN device232such that the registers of the output cells272a-272dare filled with logic zero bits. In a subsequent UPDATE BSCAN DATA REGISTERS step293, the programmable controller34instructs the BSCAN controller236to update all the registers of the BSCAN device232so that the test signal output leads254a-254dare brought to a logic zero level. The sequence290next proceeds to a SHIFT NEXT TEST VECTOR INTO BSCAN DATA REGISTERS step294, wherein the programmable controller34instructs the BSCAN controller236to shift a next test vector into the registers of the cells of the BSCAN device232. This test vector includes a pattern “1000” which is shifted into the registers of the output cells272a-272drespectively. The sequence290next proceeds to an UPDATE BSCAN DATA REGISTERS step298, wherein the BSCAN controller236commands the BSCAN device232to perform an update operation on the registers of the cells of the BSCAN device232. In doing so, the first test signal output lead254aconnected to the output cell272ais brought from the logic zero level to a logic one level. The other test signal output leads254b-254dremain at the logic zero level. In this manner, the BSCAN device232is able to generate a rising edge300in a step signal301aat the first test signal output lead254a. The generation of the step signal301ais shown to occur at time T1inFIG. 12.

The sequence290next proceeds to a CAPTURE RESPONSE SIGNAL step302, wherein the programmable controller34captures the response signal280as a result of the rising edge300at the test signal output lead254a. More specifically, the programmable controller34captures a response signal portion303ain the response signal280that is due to the rising edge300at the test signal output lead254a. When the rising edge300is applied to a good electrical connection between the test signal output lead254aand the contact4aof the component6, the capacitive sensor18will pick up a capacitively coupled signal (not shown). The measurement module17amplifies this capacitively coupled signal to obtain the response signal portion303a. The programmable controller34will at the appropriate moment trigger the measurement module17to obtain digital samples of this response signal portion303aand to carry out digital signal processing on the signal portion303ausing the digital samples to in turn obtain an amplitude of a characteristic frequency component of the signal portion303a. In doing so, the programmable controller may configure the amplifier or modify the digital signal processing according to the characteristics of the capacitive sensor18. The sequence290next proceeds to a DETERMINE INTEGRITY step304, wherein the programmable controller34will determine if the electrical connection between the contact254aand the signal path58ais good or bad by comparing the amplitude with a corresponding predetermined threshold value stored therein. More accurately, it is the entire electrical connection between the test signal output lead254aof the BSCAN device32and the contact4aof the component6that is tested.

The sequence290next proceeds to an ALL CONTACTS TESTED? decision step306, wherein the programmable controller34determines if all contacts4a-4dof the component6have been tested for electrical connection integrity. If it is determined in this step306that all contacts4a-4dhave been tested, the sequence290ends in an END step308. However, if it is determined that there is one or more contacts4a-4dthat are yet to be tested, the sequence290returns to the SHIFT NEXT TEST VECTOR INTO BSCAN DATA REGISTERS step294, wherein the above described steps294-304are performed for a next contact4a-4dunder test. In the SHIFT NEXT TEST VECTOR INTO BSCAN DATA REGISTERS step294, another test vector is shifted into registers of the cells of the BSCAN device232such that a pattern “1100” is shifted into the output cells272a-272drespectively. The registers of the cells of the BSCAN device232are once again updated in the UPDATE BSCAN DATA REGISTERS step298to result in a rising edge at time T2in the step signal301bgenerated at the second test signal output lead254b. This step signal301bis used for checking if there is an open circuit in the electrical connection of the second contact4bof the component6. If the electrical connection is good, a corresponding signal portion303bwould appear in the response signal280. In this manner, a step signal301a-301dor more specifically a rising edge300therein is generated sequentially at the respective test signal output lead254a-254dto test each of the electrical contacts4a-4dfor an open circuit. In this embodiment, four test vectors are shifted into the registers of the cells such that the patterns “1000”, “1100”, “1110” and “1111” are shifted into the registers of the output cells272a-272dfor generating the step signals301a-301dhaving rising edges that are spaced apart in time.

Although it is described that rising edges in step signals301a-301dare in turn generated at the test signal output leads254a-254d, those skilled in the art would readily recognize from such a teaching that failing edges in step signals, as shown inFIG. 9, may also be generated at these test signal output leads254a-254dfor performing the above test. It is also possible for appropriate test vectors to be used in the BSCAN device232for generating step signals that are shown inFIG. 3.

Step signals are not limited to generation using a BSCAN device232where the registers of cells are updated only when a complete test vector has been shifted into the registers of the cells. It is possible also to generate step signals using a device wherein cells can be updated with each bit shifted into the cells. Such a device includes, but is not limited to, a shift register.

FIG. 2shows an in-circuit test system30according to another embodiment that includes such a device32and a corresponding device controller36. Like the BSCAN device232inFIG. 11, the device32only functions as a controllable signal source during the electrical connection integrity test. This same device32operates as another part of the PCA40during normal operation. Each test signal output lead54a-54dof the device32is connected, via the first electrical connector56a-56d, to the electrical signal path58a-58d. Thus, the step signal generated by device32can be applied to the electrical contact4a-4dof the component6even though the signal path58a-58dmaybe inaccessible to a test probe.

The device32includes a chain70of output cells72a-72dconnected to the test signal output leads54a-54dand cells74a-74cinterleaving these output cells72a-72d. In other words, the interleaving cells74a-74care connected alternately and regularly between the output cells72a-72d. The chain70thus includes an interleaving cell74a-74cbetween every two adjacent output cells72a-72dconnected to the test signal output leads54a-54das shown inFIG. 2. In this embodiment, these interleaving cells74a-74care not connected to any lead of the device32and are included in the device32for the sole purpose of interleaving the output cells72a-72d. In other embodiments, these interleaving cells74a-74cmay be other input or output cells connected to other leads of the device32.

With the aid ofFIGS. 3 and 4, the operation of the in-circuit test system30inFIG. 2will be described in more detail next.FIG. 4shows a sequence90of steps implemented in the in-circuit test system30for performing the electrical connection integrity test to determine if there is any open circuit. The sequence90starts in a PLACE SENSOR step92, wherein the capacitive sensor18is placed over the electrical contacts4a-4dof the component6to be proximate thereto.

The sequence90next proceeds to a SHIFT BIT step94, wherein the programmable controller34sends a command to the device controller36in order to cause the device controller36to generate the appropriate control signal at its control I/O44. The control signal is then applied to the input lead48of the onboard device32. First, a logic zero is shifted into all the output cells72a-72dto set all test signal output leads54a-54dto logic zero. The device controller36then shifts a logic one bit96(FIG. 3) to a first output cell72aconnected to a first test signal output lead54aof the device32. The sequence90next proceeds to an UPDATE CELLS step98, wherein the device controller36commands the device32to perform an update operation on the cells72a-72d,74a-74c. The device32is thus able to generate a rising edge100in a step signal101aat the first test signal output lead54a.

The sequence90next proceeds to a CAPTURE RESPONSE SIGNAL step102, wherein the programmable controller34captures a response signal portion103ain a response signal80that is due to the rising edge100at the test signal output lead54a. When the rising edge100is applied to a good electrical connection between the test signal output lead54aand the contact4aof the component6, the capacitive sensor18will pick up a capacitively coupled signal (not shown). The measurement module17amplifies this capacitively coupled signal to obtain the response signal portion103aand carries out digital signal processing on the digital samples to obtain an amplitude of a characteristic frequency component of the signal portion103a. The sequence90next proceeds to a DETERMINE INTEGRITY step104, wherein the programmable controller34will determine if the electrical connection between the contact54aand the signal path58ais good or bad by comparing the amplitude with a corresponding predetermined threshold value stored therein.

The sequence90next proceeds to an ALL CONTACTS TESTED? decision step106, wherein the programmable controller34determines if all contacts4a-4dof the component6have been tested for electrical connection integrity. If it is determined in this step106that all contacts4a-4dhave been tested, the sequence90ends in an END step108. However, if it is determined that there is one or more contacts4a-4dthat are yet to be tested, the sequence90returns to the SHIFT BIT step94, wherein the above described steps are performed for a next contact4a-4dunder test. When the logic one bit96is shifted into the first interleaving cell74ain the SHIFT BIT step94and the cells72a-72d,74a-74care updated in the UPDATE CELLS step98at time T2, the step signal at the first test signal output lead54awill go from a logic high state to a logic low state to define a failing edge110in the step signal101a. This failing edge110similarly causes another signal portion112ain the response signal80. However, the programmable controller34ignores this signal portion112aand bypasses the CAPTURE RESPONSE SIGNAL step102and DETERMINE INTEGRITY step104since the contact4ahas been tested earlier using the rising edge100in the step signal101a. However, this signal portion112amay also be used to further check if the result obtained earlier is correct. During time T2, the interleaving cell74abetween the first output cell72aand the second output cell72bwill go to a logic one state. If this interleaving cell74ais not present, the logic one bit96would be shifted into the second output cell72bcausing a rising edge100at the second test signal output lead54bat the same time as the failing edge110at the first test signal output lead54a. As a result of this coincidence of the rising edge110and the failing edge112of the two step signals101a,110b, there will be little or no response signal portion as the effects of the rising edge110and the failing edge110cancel each other out at the capacitive sensor18. In other words, the signal portion of interest may be non existent. The interleaving cells74a-74ctherefore ensure that the failing edge110in the step signal101a-101dat one test signal output lead54a-54ddoes not coincide with the rising edge100in the step signal101a-101dat the adjacent test signal output lead54a-54d. In the next loop, the logic one bit96is shifted to the second output cell72bin the SHIFT BIT step94and when the cells72a-72d,74a-74care updated in the UPDATE CELLS step98, a rising edge100in the step signal101bis generated at the second test signal output lead54bfor checking if there is an open circuit in the electrical connection of the second contact4bof the component6. In this manner, a step signal101a-101dor more specifically a rising edge100therein is generated sequentially at the respective test signal output lead54a-54dto test each of the electrical contacts4a-4dfor an open circuit. In this embodiment, the logic one bit96is shifted and the cells updated at regular intervals to generate spaced-apart rising edges100in the step signals101a-101d. It is also possible to shift a logic zero bit (not shown) through the chain70of cells72a-72d,74a-74cto perform the above test.

FIG. 5shows an in-circuit test system120similar to that inFIG. 2. The only hardware difference between the two systems30,120lies in the controllable signal source. The system120includes a device122wherein interleaving cells124(only one is shown) are not cells that are added solely for that purpose. Thus additional silicon, which is required in the case of the device32inFIG. 2, is not necessary here. In this device122, interleaving cells124are cells connected to other leads (not shown) of the device122that are not connected to the contacts4a-4eof the component6. The interleaving cell124inFIG. 5is shown connected between a second output cell126band a third output cell126c. Testing of the integrity of the electrical connection of the contacts4a-4eis no longer performed by shifting a single logic one bit through a chain128of cells124,126a-126e. Instead, several logic one bits129a-129chave to be shifted through the chain128of cells124,126a-126eto test all contacts4a-4efor electrical connection integrity.

The operation of the in-circuit test system120is described with the aid ofFIG. 6andFIG. 7which shows a sequence140of steps for checking for open circuits in the electrical connection of a component6. Most of these steps are similar to those inFIG. 4and will thus be described only briefly here. The sequence140starts in the PLACE SENSOR step92, wherein the capacitive sensor18is placed over the electrical contacts4a-4eof the component6. The sequence140next proceeds to the SHIFT BIT step94, wherein the device controller36shifts the first logic one bit129ato the first output cell126aconnected to a first test signal output lead141aof the device122. The sequence140next proceeds to a SCHEDULED UPDATE CELLS step142, wherein the device controller36commands the device122to perform an update operation on the cells126a-126e,124according to a predetermined schedule. At time T1, the update cells operation is performed so that the device122is able to generate a rising edge100in a step signal143aat the first test signal output lead141a.

The sequence140next proceeds to the CAPTURE RESPONSE SIGNAL step102, wherein the programmable controller34obtains the amplitude of a characteristic frequency component of a response signal144as described above whenever there is a rising edge100in the step signal143a-143eat any of the test signal output lead141a-141e. The programmable controller34will next determine if there is an open circuit in the electrical connection of the first contact4ain the DETERMINE INTEGRITY step104by comparing the amplitude of the characteristic frequency component with a predetermined threshold value.

The sequence140next proceeds to the ALL CONTACTS TESTED? decision step106, wherein the programmable controller34determines if all contacts4a-4eof the component6have been tested for electrical connection integrity. If it is determined in this step that all contacts4a-4ehave been tested, the sequence140ends in an END step148. However, if it is determined that there is one or more contacts4a-4ethat are yet to be tested, the sequence140returns to the SHIFT BIT step94to loop around the above described steps. At time T2, the logic one bit129awill be shifted to the second output cell126b. There is however no update of cells at time T2as determined in the SCHEDULED UPDATE CELLS step142and the step signal143aat the first output test lead141awill remain at a logic high state at time T2even though the logic one bit129ahas been shifted out of the first output cell126ainto the second output cell126b. Since there is no rising edge at any of the test signal output leads141a-141e, the programmable controller34bypasses the CAPTURE RESPONSE SIGNAL and the DETERMINE INTEGRITY steps102,104. At time T3, the device122is instructed to shift the logic one bit129ato the interleaving cell124between the second and third output cells126b,126cin the SHIFT BIT step94and to update the cells130a-130d,124as determined in the SCHEDULED UPDATE CELLS step142. The step signal143aat the first test signal output lead141awill go from a logic high state to a logic low state to define a failing edge110. At this time, the step signal143b-143eat the other test signal output leads141b-141eremain at a logic zero state and the programmable controller34will thus bypass the CAPTURE RESPONSE SIGNAL and DETERMINE INTEGRITY steps104,106. In a next loop when the first logic one bit129ais shifted to the third output cell126cin the SHIFT BIT step94and the cells126a-126e,124are updated in the SCHEDULED UPDATE CELLS step142, the step signal143cat the third test signal output lead141cwill go from a logic zero to a logic one state to define the rising edge100in the step signal143c. The programmable controller34will then obtain the amplitude of a characteristic frequency component of the response signal portion146cin the CAPTURE RESPONSE SIGNAL step102and determine the electrical connection integrity of the third contact4cin the DETERMINE INTEGRITY step104as described above. When the first logic one bit129ais shifted through the fourth output cell126dand the fifth output cell126e, no update of cells is carried out in the SCHEDULED UPDATE CELLS step142. The cells are updated only when the first logic one bit129ais shifted out of the fifth output cell126eat time T7. At this time, the step signal143cat the third test signal output lead141cgoes from the logic high to a logic low state. Thus with the one interleaving cell124, the electrical connection integrity for two contacts4a,4cof the component6can be determined with the shifting of the one logic one bit129athrough the chain128and updating of the cells at the appropriate times.

A second logic one bit129bis shifted through the chain128of cells124,126a-126efor testing the electrical connection integrity of the two other contacts. The cells are updated at times T9, T10and T12to cause a rising edge100in the step signal143b,143dat the second and fourth test signal output leads141b,141das shown inFIG. 6. The programmable controller34obtains the amplitude of a characteristic frequency component of each of the response signal portions146b,146dand determines the electrical connection integrity of the second and fourth contacts4b,4dat time T9and T12respectively. Similarly, a third logic one bit129cis shifted through the chain128of cells124,126a-126efor testing the fifth contact4e. As this logic one bit129cis shifted to the fifth output cell126eat time T20, the cells are updated in the SCHEDULED UPDATE CELLS step142to generate a rising edge100in the step signal143eat the fifth test signal output lead141eso that a response signal portion146emay be captured in the CAPTURE RESPONSE SIGNAL step102for the electrical connection integrity of the fifth contact4eto be determined in the DETERMINE INTEGRITY step104. In this manner, three logic one bits129a-129cin an appropriate test bit pattern are shifted through the chain128of cells for determining the electrical connection integrity of all five contacts4a-4eof the component6.

FIG. 8shows yet another in-circuit test system150including another device152. This device152includes output cells154a-154cconnected to respective test signal output leads156a-156c. There are no interleaving cells between the output cells154a-154c. Electrical connection integrity testing of the contacts4a-4cof the component6, such as testing for open circuits, can be performed using such a device152by shifting a suitable test bit pattern158through the output cells154a-154cand updating the output cells154a-154cat the appropriate times.FIG. 9shows an example of a suitable test bit pattern158. A series of logic one bits is shifted to the output cells154a-154cand the output cells are updated to keep each test output lead156a-156cat a logic high level. Following that, a series of zero bits is then shifted through the output cells with the cells updated at each shift so that one by one the output test signal leads156a-156care brought to a logic level zero to result in a step signal160a-160cthereat. At each transition from a logic level one to a logic level zero at the test output signal lead, the programmable controller34captures a corresponding response signal portion162a-162cfor determining the electrical connection integrity of the respective contact4a-4c.

Although the present invention is described as implemented in the above described embodiments, it is not to be construed to be limited as such. For example, in addition to use in an in-circuit test system, the method is applicable in other systems including but not limited to a functional test system, a manufacturing defects analyzer (MDA) system, and a hot mock up test system. As another example, in addition to using signal paths directly connecting the test signal output leads to the contacts for testing the electrical connection integrity therebetween, the invention may be implemented when the signal path includes one or more interconnected components (not shown), such as resistors, capacitors, filters, transistors, ICs or other types of electrical components through which the step signal may propagate.

The electrical connection integrity test is also not to be construed to be limited to a test for open circuits. Those skilled in the art would recognize that the invention may be used to detect other bad electrical connections including, but not limited to, a short to ground, a short to a supply line and a short to another electrical interconnection, such as an adjacent contact or an adjacent signal path. In the latter case, determining electrical connection integrity of a first contact includes putting a second contact adjacent to the first contact to a state that disrupts the step signal at the first contact if the two contacts are shorted. For example, when a step signal going from a logic low to a logic high level is to be used for testing the electrical integrity of a first contact, the second contact may be kept at a logic low level so that in the event of a short circuit, the signal at the first contact will be prevented from going to the logic high level. Consequently, a short circuit would be detectable.

The invention may also be used to test the electrical connection integrity of a pair of contacts connected to a pair signal paths carrying differential signals. In such a case, the electrical connection integrity test includes generating a first step signal on the signal path connected to one contact and a second step signal on the signal path connected to the other contact simultaneously. The first step signal and the second step signal are of opposite polarity. With the respective capacitively coupled signals at least substantially cancelling each other out at the capacitive sensor, the absence of or a small captured response signal would indicate that the electrical connection of both the contacts are good. If any of the electrical connection of the two contacts is bad, there will be a larger captured response signal. However, a condition where both the electrical connections are bad would not be detectable. To be able to detect such a condition, a capacitive sensor having an asymmetric sensor plate may be used. Instead of not producing any response signal when the electrical connections are good, a predetermined differential response signal is now produced. A different response signal than this predetermined differential response signal would indicate that one or both of the electrical connections are bad.

As mentioned above, the invention may be used to verify the electrical connection integrity of a component such as a capacitor pack having a number of capacitors. If two of the capacitors are connected to a pair of differential signals, the sensor plate may be placed over one of the capacitor but not the other capacitor. A differential response signal is produced when both the electrical connections to the capacitors are good. However, if there is any short on either side of the capacitors, a response signal that is different than the expected differential response signal would be produced.

As yet another example, instead of controlling the device and the BSCAN device using a respective controller of the tester, the devices may be controlled using another device on the PCB or the fixture. As yet a further example, the signal source may be one that is not controllable by the programmable controller to generate the step signals but one that generates the step signals on its own during, but not limited to, a built in self test or execution of a downloaded diagnostic test. This device may include an on board oscillator, a switching regulator or the like. When doing so, such a non-controllable signal source would send a trigger signal to the programmable controller to allow the programmable controller to synchronize the capturing of the response signal at the appropriate times. That is, the trigger signal is used to coordinate the generation of the step signals by the signal source and the capturing of the corresponding response signal portions by the programmable controller.

As a further example, the at least one signal path may include a first signal path that is pulled high, pulled low or to a fixed voltage level therebetween via a resistor on a second signal path connected to the first signal path. In other words, there are now two signal paths connected to the contact. The method described above may then be used to verify the electrical connection integrity between these signal paths and the contact. For example, if a contact is pulled high via a pull-up resistor, the test signal output lead may be changed from a low state to a tri-state state to allow the pull-up resistor to pull the test output signal lead high so that a step signal is generated thereat. If there is any open circuit in either of the signal paths, no step signal would be generated and thus no response signal would be produced. Similarly, for a contact that is pulled low, the test signal output lead may be changed from a high state to a tri-state state so that a step signal may be produced thereat for electrical connection integrity verification.