Devices and methodologies related to structures having HBT and FET

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

BACKGROUND

In some semiconductor material systems it is possible to combine different device technologies on a single semiconductor die to form hybrid structures. For example, in certain material systems, it is possible to integrate a heterojunction bipolar transistor (HBT) with a field effect transistors (FET) on a single substrate, to fabricate what is referred to as a BiFET. Devices, such as RF power amplifiers, can be fabricated using BiFET technology to have increased design flexibility. As a result, a BiFET power amplifier including an HBT and a FET can be advantageously designed to operate at a lower reference voltage than a bipolar transistor power amplifier. Of particular interest to device manufacturers are high power BiFET amplifiers, which can be formed by integrating a FET into a gallium arsenide (GaAs) HBT process. However, previous attempts to integrate a FET into a GaAs HBT process have resulted only in an n-type FET device.

Therefore, it would be desirable to have a BiFET device structure that includes a p-type FET device, and that may include complementary n-type and p-type FET devices.

SUMMARY

Embodiments of a semiconductor structure include a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer comprising a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET comprising a channel formed in the semiconductor material that forms the collector layer of the HBT.

In some embodiments, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some embodiments, the semiconductor structure can further include an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. In some embodiments, such an etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such an etch stop layer can include any material with etch selectivity to, for example, the channel layer of the FET. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

In accordance with some embodiments, the present disclosure relates to a semiconductor structure having a heterojunction bipolar transistor (HBT) that includes a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The semiconductor structure further includes a first field effect transistor (FET) located over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The semiconductor structure further includes a second field effect transistor (FET) located over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

In some embodiments, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some embodiments, semiconductor structure can further include a first etch stop layer segment located over the collector layer of the HBT and the channel of the first FET, and a second etch stop layer segment located over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such etch stop layers can include any material with etch selectivity to, for example, the channel layers of the first and second FETs. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

In a number of implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The method further includes forming a first field effect transistor (FET) over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The method further includes forming a second field effect transistor (FET) over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

In some implementations, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some implementations, the method can further include forming a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET, and forming a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

According to some implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate. The collector layer includes a semiconductor material. The method further includes forming a field effect transistor (FET) located over the substrate. The FET includes a channel formed in the semiconductor material that forms the collector layer of the HBT.

In some implementations, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some implementations, the method can further include forming an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. The etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

According to some embodiments, the present disclosure relates to a die having an integrated circuit (IC). The die includes a circuit configured to process radiofrequency (RF) signal. The die further includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the circuit. The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

In some embodiments, the circuit configured to process RF signal can include a power amplifier circuit, a controller circuit for the power amplifier circuit, or a controller for a switching circuit. In some embodiments, the assembly can further include a second FET having a channel located over the substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET, and the second FET can include an nFET. In some embodiments, the substrate can include gallium arsenide (GaAs).

In a number of embodiments, the present disclosure relates to a packaged module for a radiofrequency (RF) device. The module includes a packaging substrate and an integrated circuit (IC) formed on a die and mounted on the packaging substrate. The IC includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the IC. The HBT includes a collector layer including a semiconductor material located over a die substrate. The FET includes a channel located over the die substrate and formed in the semiconductor material that forms the collector layer of the HBT. The module further includes one or more connections configured to facilitate transfer of power to the IC and RF signals to and from the IC.

In some embodiments, the assembly can further include a second FET having a channel located over the die substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET and the second FET can include an nFET.

In accordance with some embodiments, the present disclosure relates to a wireless device having an antenna and a radiofrequency integrated circuit (RFIC) configured to process RF signals received from the antenna and for transmission through the antenna. The wireless device further includes a power amplifier (PA) circuit configured to amplify the RF signals. The PA circuit includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET). The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

In some embodiments, the PA can be configured to operate as a high power BiFET amplifier capable of operating at a lower reference voltage than that of a bipolar transistor PA. In some embodiments, the substrate can include gallium arsenide (GaAs).

DETAILED DESCRIPTION

Although described with particular reference to a device fabricated in the gallium arsenide (GaAs) material system, the structures described herein can be fabricated using other III-V semiconductor materials, such as indium phosphide (InP) and gallium nitride (GaN). Further, any of a variety of semiconductor growth, formation and processing technologies can be used to form the layers and fabricate the structure or structures described herein. For example, the semiconductor layers can be formed using molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), which is also sometimes referred to as organic metallic vapor phase epitaxy (OMVPE), or any other technique. Moreover, the thicknesses of the various semiconductor layers described below are approximate, and may range to thinner or thicker than that described. Similarly, the doping levels of the doped semiconductor layers described below are relative.

The present invention is directed to a semiconductor structure that includes a bipolar device, such as a heterojunction bipolar transistor (HBT), and a p-type field effect transistor (pFET) integrated on a common substrate, referred to generally as a BiFET, and formed in a GaAs material system. Embodiments also include a complementary BiFET (BiCFET) including a p-type FET (pFET) and an n-type FET (nFET) integrated with an HBT in a GaAs material system. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.

The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. Certain details and features have been left out of the drawings, which will be apparent to a person of ordinary skill in the art. Although structure100illustrates an exemplary BiFET comprising an NPN HBT and a pFET, which are situated over a substrate in a semiconductor die, the present invention may also apply to a BiFET comprising a PNP HBT and an NFET; an NPN HBT and both an nFET and a pFET; and a PNP HBT and both an nFET and a pFET.

FIG. 1is a schematic diagram illustrating a cross-sectional view of an exemplary structure including an exemplary BiFET in accordance with one embodiment of the present invention. Certain details and features have been left out ofFIG. 1, which are apparent to a person of ordinary skill in the art. The structure100includes BiFET102, isolation regions110,112, and114, and substrate108, which can be a semi-insulating GaAs substrate. The BiFET102includes an HBT104, which is located over substrate108between isolation regions110and112, and pFET106, which is located over substrate108between isolation regions112and114. Isolation regions110,112, and114provide electrical isolation from other devices on substrate108and can be formed in a manner known in the art.

The HBT104includes sub-collector layer116, a first collector layer segment118, a second collector layer segment119, an optional etch-stop layer segment121, a base layer segment122, an emitter layer segment124, an emitter cap layer segment126, a bottom contact layer segment132, a top contact layer segment134, collector contact136, base contacts138, and emitter contact142.

For the purpose of description herein, an emitter can include one or more parts associated with an emitter stack. In the example HBT configuration104ofFIG. 1, such an emitter stack can include the emitter layer124, the emitter cap layer126, the bottom contact layer132, and the top contact layer134. Accordingly, an emitter as described herein can include the emitter layer124and/or the emitter cap layer126.

Also for the purpose of description herein, the example HBT topology is described in the context of GaAs/InGaP. It will be understood, however, that one or more features of the present disclosure can also be applied to other material systems used for HBTs, including, for example, indium phosphide (InP), antimonides, or nitride based materials.

The pFET106includes a back gate contact113, a lightly doped N type GaAs segment152, a lightly doped P type GaAs segment154, an optional etch stop layer segment156, typically comprising lightly doped N type or P type InGaP, source contact layer158and drain contact layer162, typically comprising heavily doped P type GaAs, gate contact164, source contact166, and drain contact168. Alternatively, the optional etch stop layer segment156can be undoped. In the present embodiment, the HBT104can be an NPN HBT integrated in a complementary arrangement with the pFET106. In another embodiment, the HBT104can be a PNP HBT integrated with an nFET, or can be a PNP HBT or an NPN HBT integrated with the pFET106and with an nFET. In the present embodiment, the pFET106can be a depletion mode FET or an enhancement mode FET.

The sub-collector layer116is situated on substrate108and can comprise heavily doped N type GaAs. The sub-collector layer116can be formed by using a metal organic chemical vapor deposition (MOCVD) process or other processes. The first collector layer segment118and the collector contact136are located on the sub-collector layer116. The first collector layer segment118can comprise lightly doped N type GaAs. The second collector layer segment119can comprise lightly doped P type GaAs. The first collector layer segment118and the second collector layer segment119can be formed by using a MOCVD process or other processes. The collector contact136can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the sub-collector layer116.

The optional etch stop layer segment121can be located on the second collector layer segment119and can comprise lightly doped N type or P type InGaP. Alternatively, the optional etch stop layer segment121can be undoped. The etch stop layer segment121can be formed by using a MOCVD process or other processes.

The base layer segment122is located on the etch stop layer segment121and can comprise heavily doped P type GaAs. The base layer segment122can be formed by using a MOCVD process or other processes.

The emitter layer segment124and base contacts138are located on base layer segment122. The emitter layer segment124can comprise lightly doped N type indium gallium phosphide (InGaP) and can be formed on the base layer segment122by using a MOCVD process or other processes. The base contacts138can comprise an appropriate metal or combination of metals, which can be deposited and patterned over base layer segment122. The emitter cap layer segment126is located on the emitter layer segment124and can comprise lightly doped N type GaAs. The emitter cap layer segment126can be formed by using a MOCVD process or other processes.

The bottom contact layer segment132is located on the emitter cap layer segment126and can comprise heavily doped N type GaAs. The bottom contact layer segment132can be formed by using an MOCVD process or other processes.

The top contact layer segment134is situated on the bottom contact layer segment132and can comprise heavily doped N type indium gallium arsenide (InGaAs). The top contact layer segment134can be formed by using a MOCVD process or other processes. The emitter contact142is located on the top contact layer segment134and can comprise an appropriate metal or combination of metals, which can be deposited and patterned over top contact layer segment134.

During operation of the HBT104, current flows from the emitter contact142, through the top contact layer segment134, bottom contact layer segment132, emitter cap layer segment126, emitter layer segment124, and into the base layer segment122and is indicated by arrow137.

To form the pFET106in the collector of the HBT104, a lightly doped P type GaAs layer segment154is located over a lightly doped N type GaAs layer segment152, which is located over a heavily doped N type GaAs layer segment151. A back gate contact113is formed on the heavily doped N type GaAs layer segment151to create a back gate for the pFET106. The back gate contact113can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped N type GaAs layer segment151.

The lightly doped N type GaAs layer segment152is substantially similar in composition and formation to the first collector layer segment118discussed above. The lightly doped P type GaAs layer segment154is substantially similar in composition and formation to the second collector layer segment119discussed above.

The lightly doped P type GaAs layer segment154forms the channel of the pFET106. The etch stop layer segment156is situated on the lightly doped P type GaAs layer segment154and can comprise lightly doped N type or P type InGaP. Alternatively, the etch stop layer segment156can be undoped. The etch stop layer segment156can be formed on the lightly doped P type GaAs layer segment154by using a MOCVD process or other appropriate processes. If implemented, the etch stop layer segment156can have a thickness between approximately 10 nanometers (nm) and approximately 15 nm. In one embodiment, the pFET106can be an enhancement mode FET and the etch stop layer segment156can have a thickness less than 10 nm.

The source contact layer158and the drain contact layer162are located on the etch stop layer segment156and can comprise heavily doped P type GaAs to form source and drain regions, respectively. The source and drain contact layers158and162can be formed by using a MOCVD process or other processes. A source contact166and drain contact168are located on the etch stop layer segment156. Source contact166and drain contact168can comprise platinum gold (“PtAu”) or other appropriate metals and can be formed in a manner known in the art. A gate contact164is located on the etch stop layer segment156in gap165, which is formed between source and drain contact layers158and162, and can comprise an appropriate metal or combination of metals. The gap165can be formed by utilizing an appropriate etch chemistry to selectively etch through a layer of InGaAs and a layer of GaAs and stop on etch stop layer segment156. After the gap165has been formed, gate contact164can be formed on etch stop layer segment156in a manner known in the art. In one embodiment, the FET106can be an enhancement mode FET and gate contact164can be formed directly on the lightly doped P type GaAs layer segment154. In that embodiment, an appropriate etch chemistry can be utilized to selectively etch through etch stop layer segment156and stop on lightly doped P type GaAs layer segment154.

Thus, by forming the pFET106in the layers that comprise the collector of the HBT104, a pFET can be integrated with an NPN HBT, yielding a complementary BiFET.

FIG. 2is a schematic diagram illustrating a cross-sectional view of an alternative embodiment of the structure ofFIG. 1. The structure200shown inFIG. 2includes a BiCFET structure that includes an HBT204, a pFET206and an nFET207.

Elements and structures inFIG. 2that are similar to corresponding elements and structures inFIG. 1will not be described again in detail, but instead, will be referred to using the nomeclature2XX, where “XX” refers to a similar element inFIG. 1.

The BiCFET202includes an HBT204located between isolation region210and isolation region212, a pFET206located between isolation region212and214, and includes an nFET207located between isolation region214and isolation region215.

The HBT204includes sub-collector layer216, a first collector layer segment218, a second collector layer segment219, an optional etch-stop layer segment221, a base layer segment222, an emitter layer segment224, an emitter cap layer segment226, a second optional etch stop layer228, a bottom contact layer segment232, a top contact layer segment234, collector contact236, base contacts238, and emitter contact242.

As description herein, an emitter can include one or more parts associated with an emitter stack. In the example HBT configuration204ofFIG. 2, such an emitter stack can include the emitter layer224, the emitter cap layer226, second etch stop layer228, the bottom contact layer232, and the top contact layer234. Accordingly, an emitter as described herein can include the emitter layer224and/or the emitter cap layer226.

As also described herein, the example HBT topology is described in the context of GaAs/InGaP. It will be understood, however, that one or more features of the present disclosure can also be applied to other material systems used for HBTs, including, for example, indium phosphide (InP), antimonides, or nitride based materials.

The pFET206comprises a lightly doped P type GaAs layer segment254located over a lightly doped N type GaAs layer segment252, which is located over a heavily doped N type GaAs layer segment251. A back gate contact213is formed on the heavily doped N type GaAs layer segment251to create a back gate for the pFET206. The back gate contact213can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped N type GaAs layer segment251.

The lightly doped P type GaAs layer segment254forms the channel of the pFET206. The etch stop layer segment256is situated on the lightly doped P type GaAs layer segment254and can comprise lightly doped N type or P type InGaP. Alternatively, the optional etch stop layer segment256can be undoped. The etch stop layer segment256can be formed on the lightly doped P type GaAs layer segment254by using a MOCVD process or other appropriate processes. If implemented, the etch stop layer segment256can have a thickness between approximately 10 nanometers (nm) and approximately 15 nm. The source contact layer258and the drain contact layer262are located on the etch stop layer segment256and can comprise heavily doped P type GaAs to form source and drain regions, respectively. A source contact266and drain contact268are located on the etch stop layer segment256. A gate contact264is located on the etch stop layer segment256in gap285, which is formed between source and drain regions258and262, and can comprise an appropriate metal or combination of metals.

To form the nFET207in the layers that comprise the emitter of the HBT104, a lightly doped P type GaAs layer segment255is located over a lightly doped N type GaAs layer segment253, which is located over the heavily doped N type GaAs layer segment251. The lightly doped N type GaAs layer segment253is substantially similar in composition and formation to the first collector layer segment118discussed above. The lightly doped P type GaAs layer segment255is substantially similar in composition and formation to the second collector layer segment119discussed above.

An etch stop layer segment257is located on the lightly doped P type GaAs layer segment255and is similar to the etch stop layer segment256.

A heavily doped P type GaAs layer segment259is located on the etch stop layer segment257and is substantially similar in composition and formation to base layer segment122discussed above. A back gate contact260is formed on the heavily doped P type GaAs layer segment259to create a back gate for the nFET207. The back gate contact260can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped P type GaAs layer segment259. A lightly doped N type InGaP segment261is located on the heavily doped P type GaAs segment259and is substantially similar in composition and formation to the emitter layer segment124discussed above.

A lightly doped N type GaAs layer segment263is located on the lightly doped N type InGaP layer segment261and is substantially similar in composition and formation to the emitter cap layer segment126discussed above. The lightly doped N type GaAs layer segment263forms a channel for the nFET207. The second optional etch stop layer segment267is located on the lightly doped N type GaAs layer segment263and can comprise lightly doped N type or P type InGaP. Alternatively, the second optional etch stop layer segment267can be undoped. The second optional etch stop layer segment267can be formed on the lightly doped N type GaAs layer segment263by using a MOCVD process or other appropriate processes. In an embodiment, the second optional etch stop layer segment267can have a thickness between approximately 10 nm and approximately 15 nm. In an embodiment, the nFET207can be an enhancement mode FET and the etch stop layer segment267can have a thickness less than 10 nm.

A source region269and drain region271are located on the second optional etch stop layer segment267and can comprise heavily doped N type GaAs. The source region269and the drain region271can be formed by using a MOCVD process or other processes. Contact layer segments273and275are located on source and drain regions269and271, respectively, and can comprise heavily doped N type InGaAs. Contact layer segments273and275can be formed by using a MOCVD process or other processes.

A source contact277and a drain contact279are located on top contact layer segments271and273, respectively. A gate contact281is located on the second optional etch stop layer segment267in gap285. Gap285can be formed by utilizing an appropriate etch chemistry to selectively etch through a layer of InGaAs and a layer of GaAs and stop on second optional etch stop layer segment267. After gap285has been formed, gate contact281can be formed on the second optional etch stop layer segment267in a manner known in the art. In an embodiment, the nFET207can be an enhancement mode FET and gate contact281can be formed directly on lightly doped N type GaAs layer segment263. In that embodiment, an appropriate etch chemistry can be utilized to selectively etch through the second optional etch stop layer segment267and stop on lightly doped N type GaAs layer segment263.

Accordingly, a BiCFET can be fabricated that includes complementary pFET206and nFET207, formed on a GaAs substrate along with either an NPN or a PNP HBT.

In some embodiments as described herein, some or all of the etch stop layers (e.g.,121,156,221,228,256,257and267) can include indium gallium phosphide (InGaP) or indium gallium arsenide (InGaAs). Such an etch stop layer can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, some or all of the foregoing etch stop layers can include any material with etch selectivity to, for example, a channel of an FET. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaP or InGaAs.

FIG. 3shows a process300that can be implemented to fabricate the example BiFET102ofFIG. 1or a portion of the example BiCFET202ofFIG. 2. In block302, a semiconductor substrate can be provided. In some embodiments, such a semiconductor layer can include one or more layers disclosed herein, including a semi-insulating GaAs layer such as the example layers108and208ofFIGS. 1 and 2. In block304, a heterojunction bipolar transistor (HBT) can be formed so as to include a collector layer disposed over the substrate. In some embodiments, such a collector layer can include one or more layers disclosed herein, including a p− GaAs layer (119inFIG. 1 and 219inFIG. 2). In block306, a field effect transistor (FET) can be formed so as to include a channel region disposed over the substrate and formed from the same material as the collector layer of the HBT. In some embodiments, such a channel region can include one or more layers disclosed herein, including the p− GaAs layer (154inFIG. 1 and 254inFIG. 2). In some implementations, other structures associated with the HBT (e.g., base, emitter and contacts) and the FET (e.g., source, drain and contacts) can be formed.

FIG. 4shows a process310that can be implemented to fabricate the example BiCFET202ofFIG. 2. In block312, a semiconductor substrate can be provided. In some embodiments, such a semiconductor layer can include one or more layers disclosed herein, including a semi-insulating GaAs layer such as the example layer208ofFIG. 2. In block314, a sub-collector layer can be formed over the substrate layer. In some embodiments, such a sub-collector layer can include one or more layers disclosed herein, including the n+ GaAs layer (216and/or251inFIG. 2). In block316, an HBT can be formed over the sub-collector layer. In some embodiments, such an HBT can be formed so as to include the example layers described herein in reference toFIG. 2, including a collector219(e.g., p− GaAs), a base222(e.g., p+ GaAs), an emitter224(e.g., n− InGaP), and an emitter cap226(e.g., n− GaAs). In block318, a first FET can be formed over the sub-collector layer, so that its channel region is formed from same material as the HBT's collector region. In some embodiments, such a first FET can be formed so as to include the example layers described herein in reference toFIG. 2, including a channel layer254(e.g., p− GaAs), a source contact layer258(e.g., p+ GaAs), and a drain contact layer262(e.g., p+ GaAs). In block320, a second FET can be formed over the sub-collector layer, so that its channel region is formed from same material as the HBT's emitter cap region. In some embodiments, such a second FET can be formed so as to include the example layers described herein in reference toFIG. 2, including a channel layer263(e.g., n− GaAs), a source contact layer269(e.g., n+ GaAs), and a drain contact layer271(e.g., n+ GaAs).

FIGS. 5-7show processes that can be more specific examples of the processes described in reference toFIGS. 3 and 4, in the context of the example configurations ofFIGS. 1 and 2.FIG. 5shows a process330that can be implemented to fabricate an HBT such as those ofFIGS. 1 and 2.FIG. 6shows a process350that can be implemented to fabricate an FET such as those ofFIGS. 1 and 2.FIG. 7shows a process360that can be implemented to fabricate a second FET such as that ofFIG. 2. For the purpose of description ofFIGS. 5-7, it will be assumed that a semiconductor substrate (such as semi-insulating GaAs) and a sub-collector layer (such as n+ GaAs) are provided.

The example processes330,350and360can be performed in sequence, in parallel where applicable, or in any combination thereof. Examples of such schemes of integrating an HBT with one or more FETs are described herein in greater detail.

In the example process330ofFIG. 5where an HBT is being fabricated, a first collector layer (e.g., n− GaAs) can be formed on the sub-collector layer in block332. In block334, a second collector layer (e.g., p− GaAs) can be formed on the first collector layer. In block336, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the second collector layer. In block338, a base layer (e.g., p+ GaAs) can be formed on the first etch stop layer. In block340, an emitter layer (e.g., n− InGaP) can be formed on the base layer. In block342, an emitter cap layer (e.g., n− GaAs) can be formed on the emitter layer. In block344, a second etch stop layer (e.g., n− or p− InGaP) can be formed on the emitter cap layer. In block346, a bottom contact layer (e.g., n+ GaAs) for the emitter can be formed on the second etch stop layer. In block348, a top contact layer (e.g., InGaAs) for the emitter can be formed on the bottom contact layer. In block349, contacts for the emitter, base and collector can be formed so as to yield HBT configurations such as those (104,204) ofFIGS. 1 and 2.

In the example process350ofFIG. 6where a first FET (e.g., a pFET) is being fabricated, a doped layer (e.g., n− GaAs) can be formed on the sub-collector layer in block352. In block354, a channel layer (e.g., p− GaAs) can be formed on the doped layer. In block356, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the channel layer. In block358, source and drain contact layers (e.g., p+ GaAs) can be formed on the first etch stop layer. In block359, contacts for the source, drain, gate and back gate can be formed so as to yield FET configurations such as the example pFETs106and206ofFIGS. 1 and 2.

In the example process360ofFIG. 7where s second FET (e.g., an nFET) is being fabricated, a first doped layer (e.g., n− GaAs) can be formed on the sub-collector layer in block362. In block364, a second doped layer (e.g., p− GaAs) can be formed on the first doped layer. In block366, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the second doped layer. In block368, a third doped layer (e.g., p+ GaAs) can be formed on the first etch stop layer. In block370, a fourth doped layer (e.g., n− InGaP) can be formed on the third doped layer. In block372, a channel layer (e.g., n− GaAs) can be formed on the fourth doped layer. In block374, a second etch stop layer (e.g., n− or p− InGaP) can be formed on the channel layer. In block376, source and drain regions (e.g., n+ GaAs) can be formed on the second etch stop layer. In block378, source and drain contact layer (e.g., InGaAs) can be formed on the source and drain regions. In block379, contacts for the source, drain, gate and back gate can be formed so as to yield an FET configuration such as the example nFET (207) ofFIG. 2.

In some implementations, the foregoing integration of an HBT with one or more FETs can be achieved in a number of ways, including a re-growth methodology, a two-step methodology, and/or a co-integration methodology. In the re-growth methodology, re-growth can involve a selective area, multilayer, and/or pre-patterned multilayer techniques. The selected area technique can include growing one device, etching in one or more selected areas, and then growing the other device in those selected area(s). The multilayer technique can include a single growth run, with the device layers stacked, not merged or shared. The pre-patterned multi-layer technique can include selective etching of a substrate prior to depositing layers for two or more devices.

In the two-step growth methodology, one device can be formed first, followed by formation of the other device adjacent to the first device. In the context of integration of three devices (such as the example ofFIG. 2), such a two-step growth can be extended to include a third step growth of the third device.

In the co-integration methodology, a single growth can yield layers that are shared by two or more devices. In some implementations, the co-integration methodology can include single growth generated layers that constitute a majority of the layers of the two or more devices.

FIG. 8shows that in some embodiments, one or more features associated with the BiFET and/or BiCFET configurations described herein can be implemented as part of a semiconductor die400. For example, such a die can include a power amplifier (PA) circuit402having one or more BiFET and/or BiCFET devices404. Such a PA circuit402can be configured so as to amplify an input RF signal (RF_IN) to generate as an amplified output RF signal (RF_OUT).

FIG. 9shows another example die410that includes a PA circuit412controlled by a PA/Switch controller414. The controller414can be configured to include one or more BiFET and/or BiCFET devices404.

FIG. 10shows that in some embodiments, a die (such as the example die410ofFIG. 9) can be implemented in a packaged module420. The die410can include a PA412and a controller414having a BiFET (and/or BiCFET)404having one or more features as described herein. Such a module can further include one or more connections422configured to facilitate passage of signals and/or power to and from the die410. Such a module can further include one or more packaging structures424that provide functionalities such as protection (e.g., physical, electromagnetic shielding, etc.) for the die410.

FIG. 11shows that in some embodiments, a component such as the die410ofFIG. 9or the module420ofFIG. 10can be included in a wireless device430such as a cellular phone, a smart phone, etc. InFIG. 11, a packaged RF module420is depicted as being part of the wireless device430; and such a module is shown to include a BiFET and/or BiCFET404having one or more features as described herein. In some embodiments, an unpackaged die having similar functionality can also be utilized to achieve similar functionalities. The wireless device430is depicted as including other common components such an RFIC434and an antenna436. The wireless device436can also be configured to receive a power source such as a battery432.

While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention. For example, the invention is not limited to the gallium arsenide material system.