Vertical cavity surface emitting laser (VCSEL) array and manufacturing method

The present invention discloses a VCSEL array that can function in at least two different operational modes. In one operational mode, the VCSEL array functions as a regular-patterned array; and in the other operational mode, the VCSEL array functions as an irregular-patterned array. Thus, the same VCSEL chip may be used as an illumination light source or a structural light method light source for 3D sensing, depending on the selected operational mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the U.S. National Stage of International Application No. PCT/CN2018/107359, filed Sep. 25, 2018, the content of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This invention generally relates to Vertical Cavity Surface Emitting Laser (VCSEL) array and to the manufacturing method of VCSEL arrays.

BACKGROUND ART

Three-dimensional (3D) sensing represents a future trend of smartphones. The 3D sensing technology is also expected to enhance the functions of robots, drones, and autonomous vehicles. Compared to conventional cameras which provide two-dimensional information, 3D sensing captures the depth data in addition to a flat image and thus enables accurate facial recognition, object recognition, gesture sensing, and environmental sensing. Moreover, it enhances augmented reality (AR) and virtual reality (VR) capabilities as well. 3D sensing includes the Time-of-Flight (TOF) method and the structured light method. In the TOF approach, the depth data is obtained by measuring the traveling time of light emitted from a light source, reflected from an object, and finally detected by a sensor. In the structured light approach, a predetermined pattern of dots is projected onto an object. The pattern is distorted after it is reflected by the 3D shape of the object. The depth data of the object is calculated by analyzing changes in the pattern. VCSEL arrays may be used as light sources for the TOF and the structured light methods. For instance, the TOF method may use a VCSEL array with a regular pattern where VCSELs are configured in a matrix format. The structured light method may use a patterned VCSEL array, where VCSELs form a predetermined irregular pattern of dots.

A VCSEL emits an output beam in the direction perpendicular to its top and bottom surfaces. To become a VCSEL array, a VCSEL chip may contain multiple VCSELs which generate multiple output beams. For instance, thousands of VCSELs may be formed on a chip. Thanks to the surface emitting feature, wafer-level processing and surface-mount techniques, which are well developed in the semiconductor industry, can be utilized to manufacture VCSEL array devices in high volume inexpensively. Because of a narrow spectrum and stability with respect to temperature, plus low cost and small size, VCSEL arrays are becoming the dominant light source in 3D sensing implementations.

In illumination applications, VCSEL emitters in a VCSEL array are arranged in a regular pattern. One often-used regular pattern is matrix, where the spacing between any two adjacent VCSEL emitters in a row or column is the same. For instance, a 30×30 VCSEL array has thirty emitters in each row and each column and the centers of any two adjacent emitters may be, for instance, a constant value of forty micrometers.

In structured light method of 3D sensing, however, the VCSEL emitters of a VCSEL array are arranged in a predetermined irregular pattern, which is determined by the specific algorithm used in the structured light method. Examples include random and pseudo-random patterns depending on the design. A regular-patterned VCSEL array may be made by the same fabrication method as an irregular-patterned VCSEL array. Take a top-emitting VCSEL array for example. When a regular-patterned VCSEL array is made, VCSELs are formed on a substrate in a regular pattern. The VCSELs share a common cathode terminal and are separated from each other by isolation trenches. A contact is formed on top of each VCSEL. In the last fabrication step(s), a metal layer is deposited above the VCSELs to connect all these top contacts. When an irregular-patterned VCSEL array is made, VCSELs are formed on a substrate in a predetermined irregular pattern. The VCSELs share a common cathode terminal and are separated by isolation trenches. Similarly, a contact is formed on top of each VCSEL. In the last fabrication step(s), a metal layer is deposited to connect all top contacts of the VCSELs. The main difference between making a regular-patterned VCSEL array and making an irregular-patterned VCSEL array is that they use different sets of masks. While the manufacturing process fully utilizes current fabrication techniques and processes, it is limited to only one design of patterned array, a regular pattern or a predetermined irregular pattern. Consequently, a regular-patterned VCSEL array and an irregular-patterned VCSEL array have to be designed and manufactured separately in order to meet different needs. A VCSEL array is either a regular-patterned array or an irregular-patterned array.

SUMMARY OF INVENTION

Technical Problem

The present invention discloses a VCSEL array that can function in at least two different operational modes. In one operational mode, the VCSEL array functions as a regular-patterned array; and in the other operational mode, the VCSEL array functions as an irregular-patterned array. Thus, the same VCSEL chip may be used as an illumination light source or a structured light method light source for 3D sensing, depending on the selected operational mode.

Solution to Problem

Technical Solution

In one embodiment, a VCSEL array comprises a substrate and a plurality of VCSEL structures formed in a regular pattern on the substrate. The VCSEL structures share one electrode (e.g., the cathode terminal) and each have a contact serving as the other electrode (e.g., the anode terminal). A first customized metal layer is deposited above the plurality of VCSEL structures to electrically connect the contacts of a selected number but not all of the plurality of VCSEL structures. The selected VCSEL structures form an array of a predetermined irregular pattern. A second customized metal layer is deposited above the plurality of VCSEL structures to electrically connect the contacts of the remaining VCSEL structures. In one operational mode, the selected VCSELs are powered on to function as an irregular-patterned array. In another operational mode, all of the VCSELs are powered on to function as a regular-patterned array.

In another embodiment of the present invention, a VCSEL array comprises a substrate, a plurality of VCSEL structures formed in a regular pattern on the substrate, and an optical component mounted above the plurality of VCSEL structures. The plurality of VCSEL structures share one electrode (e.g., the cathode terminal) and each have a contact serving as the other electrode (e.g., the anode terminal). The optical component has a first and a second customized metal layer with contact pads formed on its bottom surface. The contact pads of the first metal layer are arranged in a mirror image of a predetermined irregular pattern. The contact pads of the first and second metal layers together form a mirror image of the regular pattern. After the optical component is mounted above the plurality of VCSEL structures, each of the contact pads is electrically bonded with a corresponding contact of a VCSEL structure. As a result, a selected number but not all of the plurality of VCSEL structures are electrically connected by the contact pads of the first metal layer. The VCSEL structures which are connected to the contact pads of the first metal layer form an array of the predetermined irregular pattern. In one operational mode, the VCSEL structures, which are connected to the contact pads of the first metal layer, are powered on to function as an irregular-patterned array. In another operational mode, all of the VCSEL structures are powered on to function as a regular-patterned array.

In yet another embodiment, a VCSEL array comprises a plurality of VCSEL structures mounted on a submount via the flip-chip method. The plurality of VCSEL structures are arranged in a regular pattern and share one electrode (e.g., the cathode terminal). Each VCSEL structure has a contact serving as the other electrode (e.g., the anode terminal). The submount has a first and a second customized metal layers with contact pads formed on its top surface. The contact pads of the first metal layer are arranged in an image of a predetermined irregular pattern. The contact pads of the first and second metal layers together form an image of the regular pattern. After the plurality of VCSEL structures are mounted on the submount, each of the contact pads is electrically bonded with a corresponding contact of a VCSEL structure. As a result, a selected number but not all of the plurality of VCSEL structures are electrically connected by the contact pads of the first metal layer. The VCSEL structures which are connected to the contact pads of the first metal layer form an array of the predetermined irregular pattern. In one operational mode, the VCSEL structures, which are connected to the contact pads of the first metal layer, are powered on to function as an irregular-patterned array. In another operational mode, all of the VCSEL structures are powered on to function as a regular-patterned array.

In yet another embodiment of the present invention, the two or more customized metal layers discussed in the previous embodiments may be fabricated as separate parts or portions of a single metal layer electrically insulated by nonconductive material (e.g., Silicon Nitride).

Advantageous Effects of Invention

Advantageous Effects

The present invention has advantages over prior art arrays because a VCSEL array may be used either a regular-patterned array for illumination applications or an irregular-patterned array for structured light 3D sensing applications.

MODE FOR THE INVENTION

Mode for Invention

FIG.1illustrates a prior art VCSEL array100in a cross-sectional view. Array100comprises VCSELs1,2, and3on a substrate106. It should be noted that the array100may comprise thousands of VCSELs and only three VCSELs are shown here for simplification purposes. Similarly, in other figures and descriptions below, only a few VCSELs or part of an array are shown for simplification purposes. VCSEL1,2, or3represents a VCSEL structure or VCSEL emitter which emits a laser beam when charged with an electrical current. As used herein, a VCSEL, VCSEL structure, and VCSEL emitter have the same meaning and may be used interchangeably. As shown, each VCSEL includes an active region101and reflector regions102and103. For a typical VCSEL, active region101may contain a multiple-quantum-well (MQW) structure, reflector region102may contain an n-type Distributed Bragg Reflector (DBR), and reflector region103may contain a p-type DBR. The quantum well region and DBRs are grown on substrate106in an epitaxial process. Substrate106has n-type doping. Reflector regions102and103and substrate106are electrically conductive. Metal contacts104are deposited on the p-type DBR regions. Metal layer105is deposited on the bottom surface of substrate106. Metal layers104and105serve as the anode and cathode terminals, respectively.

As shown inFIG.1, the plurality of VCSELs shares a common cathode but are separated by isolation trenches. When the array is in operation or electrically charged, each VCSEL emitter generates a laser beam. These VCSEL emitters are arranged in a regular pattern. For purpose of illustration, a VCSEL array of a regular or irregular pattern may also be called a regular-patterned or irregular-patterned VCSEL array.

A regular pattern, as used herein, may mean various configurations that follow certain rules. Examples of regular patterns include elements with equal spacing in one or more rows, elements with equal spacing in rows and columns, elements with equal spacing in concentric circles, etc. An irregular pattern, as used herein, may mean various configurations which don't follow any rule. Irregular patterns include random or pseudorandom patterns.

Prior art regular-patterned and irregular-patterned VCSEL arrays may be made with the same fabrication process, except using different lithographic masks. Both types of arrays have a common cathode terminal and connected anode terminals. All of the anode terminals are electrically connected by a metal layer in both cases. For instance as shown inFIG.2, a prior art regular-patterned VCSEL array200contains five emitters from VCSEL1to VCSEL5. A metal layer202, serving as the common cathode, is deposited on the bottom substrate surface. An insulation layer (e.g. Silicon Nitride) is deposited on the top surfaces of p-type reflector regions. A plurality of vias203are etched on the insulation. A metal layer201is deposited to electrically connect all VCSELs through the vias. Array200represents a regular-patterned VCSEL array, where the emitters are configured in a regular pattern and all of the VCSEL are turned on when the array is in operation.

InFIG.3, a prior art VCSEL array300is depicted. Array300contains VCSELs1,2, and3, where the VCSELs are configured in a predetermined pattern. Like array200ofFIG.2, VCSELs1,2, and3have a common cathode302. A metal layer301electrically connects the VCSELs through vias303. When array300is turned on, a predetermined pattern of VCSEL emitters is formed. Thus, when a prior art method is used to make a VCSEL array, the array has a fixed pattern, either a regular pattern or an irregular pattern. After a VCSEL array is made, its pattern is fixed and can't be changed.

FIG.4illustrates an exemplary VCSEL array400in a cross-sectional view, according to one embodiment of the present invention. As shown, array400includes five VCSEL emitters from VCSEL1to VCSEL5. A metal layer405is deposited on the bottom surface of the substrate and serves as the common cathode terminal for the VCSELs. Two metal layers401and402are deposited above the epitaxial regions, for example, in a sequential manner. Metal layer401is arranged to electrically connect VCSELs1,2, and5through vias403. Metal layer402is configured to electrically connect VCSELs3and4through vias404. The sections of layer401and402are respectively linked via connections not shown in the figure.

Hence, metal layers401and402are electrically connected to different VCSELs and thus may create VCSEL arrays with different patterns. For instance, metal layer401may be deposited to connect a selected number but not all of VCSELs. The selected VCSELs may form a predetermined irregular pattern. Thus, an irregular pattern may be generated by depositing a metal layer to connect selected but not all elements from a regular array. Metal layer402, on the other hand, is configured to connect the remaining VCSELs which are not selected or connected to layer401. Thus, when an electrical current is charged via metal layer401, the VCSEL array400functions as an irregular-patterned array because only those VCSEL emitters connected by metal layer401are lit up. On the other hand, when an electrical current is charged via both metal layers401and402, all VCSELs are powered on. Then array400becomes a regular-patterned VCSEL array. Therefore, VCSEL array400may operate in two different modes, a regular-patterned array mode and an irregular-patterned array mode.

Alternatively, metal layers401and402may be fabricated as two electrically insulated portions of the same metal layer and achieve the same functions described above.

FIG.5shows an exemplary VCSEL array500in a top view, according to one embodiment of the present invention. Note that this is not a cross-sectional view of the VCSEL Array500but a design view of the metals. The ring shaped objects represent metallic annular rings on the top surface of a VCSEL chip. The annular rings may be metal contacts or anode terminals of the VCSELs. Each annular ring encircles an output window of a VCSEL from where a laser beam is emitted. The short and long bars may represent two metal layers on the surface which electrically connects selected VCSELs respectively. Bond pads501and502are arranged for wire bonding. Bond wires may be bonded to connect the anode terminals of some VCSELs to a contact pad on a submount which carries the chip. Configuration of the annular rings illustrates a VCSEL array with a 4×4 matrix, i.e., an exemplary regular pattern. Bond pad501is connected to five VCSELs, which may be selected to form a predetermined pattern such as an irregular pattern. Thus, when an electrical current is charged via pad501and a common cathode terminal (not shown in the figure), VCSEL array500shows a predetermined pattern, such as a predetermined irregular pattern. When both pads501and502are used to charge an electrical current, all VCSELs are powered on. It becomes a VCSEL array of a regular pattern, a 4×4 matrix. Hence, the embodiment shown inFIG.5may be implemented to create a VCSEL array which has either a predetermined irregular pattern or a regular pattern. It should be noted that the above two metal layers may be fabricated as two insulated metal portions of the same metal layer and achieve the same functions described above.

Besides metal layers formed during the fabrication process of the VCSEL array, VCSELs of a regular-patterned array may also be selected to form a predetermined pattern by an external object, such as an optical component or a submount.FIG.6shows an exemplary optical component600in a cross-sectional view, which may be used to create a VCSEL array with either an irregular pattern or a regular pattern. Optical component600may be made using a base plate603. Plate603may be made from a material which is transparent or substantially transparent at the wavelengths of interest. Its top and bottom surfaces may be coated with an antireflection layer to reduce reflection. Two metal layers604and605are deposited on plate603in a sequential manner using plating and lithographic processes. Alternatively, metal layers604and605may also be two portions formed from the same metal layer. The metal may be aluminum or copper. The sections of layer604and605are respectively connected (not shown in the figure) so that they are electrically two separate metal layers. Between the two metal layers is an insulation layer606. Layer606may be arranged via a deposition process.

Like metal layers401and402ofFIG.4, layers604and605are used to create two patterns. They have contact pads601and602respectively. Contact pads602may be arranged to form a configuration which is a mirror image of a predetermined irregular pattern. After optical component600is mounted on a regular-patterned VCSEL array chip, contact pads601and602are connected to metal contacts of the VCSELs on the chip. The VCSELs, which are electrically connected to the contact pads601, form the predetermined irregular pattern. In addition, all VCSELs on the chip may be electrically charged simultaneously via pads601and602to produce a regular pattern.

InFIG.7, an exemplary VCSEL array700is illustrated in a cross-sectional view. It comprises a VCSEL array chip and an optical component attached to the chip. The chip contains a plurality of VCSELs, including VCSELs1,2, and3, configured in a regular pattern. The VCSEL array chip may be fabricated by using the manufacturing process of a regular-patterned VCSEL array but without the metallization that completes the connection of the VCSELs. The optical component has two metal layers704and705deposited in a sequential manner on a downward facing surface. Alternatively, metal layers704and705may also be two portions of the same metal layer. Contact pads of the optical component which are connected to layer704are arranged in a mirror image of a predetermined pattern. As shown in the figure, VCSELs1and2have metal contacts701. VCSEL3has metal contacts702. Contact701and702are deposited on the p-type DBR reflector regions as the anode terminals of the VCSELs. The optical component is mounted on the VCSEL chip such that contact pads of the optical component are bonded with metal contacts701and702respectively. The contact pads are bonded on the chip by an electrically conductive adhesive material703. Material703may be cured at an elevated temperature. As shown exemplarily, anode terminals of VCSELs1and2are electrically connected to metal layer704, while the anode terminal of VCSEL3is connected to metal layer705. The VCSELs have a common cathode terminal704. Thus, when an electrical current is charged to VCSEL array700through metal layer704, VCSELs1and2, which are connected to the contact pads leading to metal layer704, are powered on. VCSELs1and2form the predetermined pattern. Additionally, when both metal layers704and705are used to charge an electrical current, all VCSELs are powered on. Consequently, it becomes a regular-patterned VCSEL array. Therefore, an optical component may be used to make a VCSEL array have either a predetermined irregular pattern or a regular pattern. Because packaging processes are less complex than plating and lithographic processes, VCSEL array700may have advantages in cost and turnaround time over array400.

Furthermore, an optical component may provide other functionalities in addition to presenting two patterns. For instance, optical structures may be created on the upward facing surface of an optical component. The structures may include lens-like objects generated by molding or etching processes. The lens-like objects may be aligned to each VCSEL and cause an output beam less or more divergent. Moreover, an optical system may be attached to an optical component to create a subassembly or an upgraded optical component. The optical system may contain certain optical elements or even complex lens systems. Thus an optical component may provide certain functionalities besides creating a predetermined irregular pattern and a regular pattern. As a subassembly may be manufactured in advanced or outsourced, it may increase production efficiency and cut cost and turnaround time.

FIG.8illustrates an exemplary submount800in a cross-sectional view, according to the present invention. In above discussions, VCSELs are of the top-emitting type, which means that laser beams are emitted through the p-type DBR region in a direction opposite to the substrate. In some cases, a back-side-emitting VCSEL is used. The VCSEL chip is turned upside down and packaged using flip-chip methods. For a backside-emitting VCSEL chip with flip-chip bonding, output laser beams go through the substrate and the chip's anode and cathode terminals face downward towards a submount. In such situations, a submount may be used to create a VCSEL array with an irregular pattern from a regular-patterned array. The submount may work in a similar way to an optical component as shown in the above examples.

Submount800has a base plate801, where contact pads802,803,804, and805are electrically connected respectively by metal layers807,808, and809. For instance, pads802are electrically connected by metal layer807, pads804by metal layer808, and pads803and805by metal layer809. Metal layers807and808are deposited on the top surface of the submount. Metal layer809is embedded in an insulation layer806. Metal layers807and808may be two portions of the same metal layer or different metal layers. Metal layer809may be a portion of a metal layer which is electrically insulated from layers807and808. The contact pads may be fabricated using plating, etching, and lithographic techniques. The configuration of contact pads802or803, which are connected respectively, may represent an image of a predetermined pattern, such as an irregular pattern. The image may be used to create a VCSEL array with the predetermined pattern.

FIG.9illustrates an exemplary VCSEL array900in a cross-sectional view, according to the present invention. A VCSEL array die is flip-chip bonded on a submount. Before the die is mounted, its substrate portion is etched and an antireflection layer910is deposited to reduce reflection of an output laser beam. The die comprises VCSELs1,2, and3configured in a regular pattern. Metal contacts902and903are the anode and cathode terminals which are connected to the p-type DBRs and n-type DBRs of VCSELs1and2respectively. Metal contacts904and905are the anode and cathode terminals which are connected to the p-type DBR and n-type DBR of VCSEL3respectively. The submount has a base plate901and contact pads906,907,911, and912deposited on the base plate. Contact pads906and907are arranged for VCSELs1and2. Contact pads911and912are arranged for VCSEL3. Metal contacts902and903of VCSELs1and2are bonded with contact pads906and907respectively by an electrically conductive adhesive material908, while similarly metal contacts904and905of VCSEL3are bonded with contact pads911and912respectively.

Metal layers914and915may be two portions of the same metal layer or different metal layers. A metal layer913may be a portion of a metal layer which is electrically insulated from layers914and915. Contact pads906which are aligned with metal contacts902are electrically connected by metal layer914. Contact pads911which are aligned with metal contacts904are electrically connected by metal layer915. Contact pads907and912which are aligned with metal contacts903and905respectively are electrically connected by metal layer913. For instance, as shown in the figure, metal layers914and915may be deposited on the top surface of the submount, and metal layer913may be embedded in an insulation layer909. Resultantly, the anode terminals of VCSELs1and2are electrically connected to metal layer914, the anode terminal of VCSEL3is electrically connected to metal layer915, and the cathode terminals of all VCSELs are connected to metal layer913. Thus when the configuration of contact pads906or907represents an image of a predetermined pattern, VCSELs1and2, which are connected to pads906and907, form the predetermined pattern. When an electrical current is charged to the VCSELs through contact pads906and907, only VCSELs1and2are turned on, which form a predetermined pattern defined by contact pads906or907on the submount. Resultantly, array900becomes a VCSEL array with a predetermined pattern, such as a predetermined irregular pattern.

VCSELs1and2are electrically insulated from VCSEL3and so are metal layers914and915. Hence, when VCSELs1and2are turned on, VCSEL3is not affected electrically. However, when an electrical current is charged to the VCSELs though all contacting pads906,907,911and912on the submount, all VCSELs are turned on. Array900becomes a VCSEL array with the regular pattern. Therefore, like an optical component, a submount may be used to make a VCSEL array which may present either an irregular pattern or a regular pattern. Like the optical component method, the submount method has similar merits and advantages over prior art regular-patterned or irregular-patterned VCSEL arrays, such as improved cost and turnaround time.

Note that in the embodiments described above, the regular-patterned VCSEL arrays are divided into two subarrays, a first subarray is formed by using a first metal layer (e.g., metal layer401inFIG.4and metal layer604inFIG.6) to connect a select number but not all of the plurality of VCSELs, and a second subarray is formed by using a second metal layer (e.g., metal layer402inFIG.4and metal layer605inFIG.6) to connect the remaining VCSELs which are not connected to the first metal layer. And the first subarray could be in a predetermined irregular pattern. In another embodiment of the present invention, a regular-patterned VCSEL array may be divided into three or more subarrays by using three or more metal layers, and at least one of the subarrays is in a predetermined irregular pattern. In that case, the VCSEL array may be operated in three or more modes. It should be noted that all or some of the above metal layers may be fabricated as metal portions of a single metal layer, depending on the given circumstances and considerations.

FIG.10illustrates an exemplary submount1000in a top view, according to the present invention. The concentric rings may represent a pair of metallic contact pads deposited on the submount. The inner ring may represent a contact pad to be connected to an anode terminal of a VCSEL. The outer ring may represent a contact pad to be connected to a cathode terminal of a VCSEL. As aforementioned, the outer rings, to be connected to VCSELs' cathode terminals, may be electrically connected by a metal layer (not shown in the figure) beneath the surface, which may be embedded in an insulation layer on a base plate of the submount. The embedded metal layer has a contact area1003which may be used as a bonding pad for wire bonding. The submount makes VCSELs of a VCSEL die have a common cathode. Metal layers1001and1002may be two separate portions of a metal layer. The inner rings may be electrically connected to a corresponding metal layer respectively. InFIG.10for instance, inner rings marked by letter A are electrically connected to metal layer1001and inner rings marked by letter B are electrically connected to metal layer1002.

Thus, after a VCSEL die with a 4×4 matrix configuration, i.e., a regular pattern, is flip-chip mounted on submount1000, each pair of the inner and outer rings are connected to an anode and cathode terminal of a VCSEL. When an electrical current is charged to the VCSELs through metal layer1001, only VCSELs corresponding to a pair of rings marked with letter A are turned on, which may form a predetermined pattern. Resultantly, a VCSEL array with a predetermined pattern is generated. When an electrical current is charged to the VCSELs through metal layers1001and1002together, all VCSELs are turned on, A VCSEL array with the 4×4 matrix configuration, a regular pattern, is generated. Therefore, a VCSEL array with a regular pattern may be turned into an array with an irregular pattern or a regular pattern using a submount method.