Semiconductor device and manufacturing method thereof

A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

FIELD

It is related to a semiconductor device and a manufacturing method thereof.

BACKGROUND

There are various types of volatile memories formed on semiconductor substrates. Among them, a SRAM (static random access memory) is able to achieve high-speed operation and is utilized for a cache memory and the like.

A memory cell in the SRAM includes a flip-flop circuit formed of multiple MOS transistors. Information is stored in the flip-flop circuit.

Reduction in the cell size of the SRAM can contribute to downsizing of an electronic device including the SRAM such as a calculator.

Note that 2008 Symposium on VLSI Technology Digest of Technical Papers, p. 106-107, 2008 discloses techniques related to the SRAM.

SUMMARY

According to one aspect discussed herein, there is provided a semiconductor device including a semiconductor substrate in which a first active region and a second active region of a memory cell of a static random access memory are defined by a device isolation insulating film, a gate electrode formed over the device isolation insulating film and the first active region, and extending in a first direction, a first insulating film formed over the semiconductor substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to have a rectangular planar shape extending in a second direction perpendicular to the first direction, a second plug formed to penetrate the first insulating film over the second active region, a second insulating film formed over the first insulating film, and a interconnection buried in the second insulating film, and formed to extend from a position over the first c plug to a position over the second plug while receding from a side surface of the plug in the second direction, and to cover only a part of an upper surface of the first plug.

According to another aspect discussed herein, there is provided a semiconductor device including a semiconductor substrate in which a first active region and a second active region are defined by a device isolation insulating film, a gate electrode formed over the device isolation insulating film and the first active region and extending in a first direction, a first insulating film formed over the semiconductor substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to have a rectangular planar shape extending in a second direction perpendicular to the first direction, a second insulating film formed over the first insulating film, a second plug formed to penetrate the first insulating film and the second insulating film over the second active region, a interconnection formed in the second insulating film, formed integrally with the first plug and the second plug, and extending from a position over the first plug to a position over the second copper-containing plug, and a third plug formed to penetrate the first insulating film and the second insulating film.

According to yet another aspect discussed herein, there is disclosed a method of manufacturing a semiconductor device including defining, in a semiconductor substrate, a first active region and a second active region of a memory cell of a static random access memory by forming a device isolation insulating film over the semiconductor substrate, forming a gate electrode, extending in a first direction, over the device isolation insulating film and the first active region, forming a first insulating film over the semiconductor substrate and the gate electrode, forming a first hole in the first insulating film, the first hole overlapping with the gate electrode and the first active region and having a rectangular planar shape extending in a second direction perpendicular to the first direction, forming a second hole in the first insulating film over the second active region, forming a first plug and a second plug respectively in the first hole and the second hole, forming a second insulating film over the first plug, the second plug, and the first insulating film, forming a trench in the second insulating film, the trench extending from a position over the first plug to a position over the second plug, the trench being formed at a distance from a side surface of the first plug in the second direction, and forming a interconnection in the trench.

According to still another aspect discussed herein, there is provided a method of manufacturing a semiconductor device including defining, in a semiconductor substrate, a first active region and a second active region of a memory cell of a static random access memory by forming a device isolation insulating film over the semiconductor substrate, forming a gate electrode, extending in a first direction, over the device isolation insulating film and the first active region, forming a first insulating film over the semiconductor substrate and the gate electrode, forming a second insulating film over the first insulating film, forming a first hole, a second hole and a third hole by patterning the first insulating film and the second insulating film, the first hole having a rectangular planar shape overlapping with the gate electrode and the first active region and extending in a second direction perpendicular to the first direction, the second hole being located over the second active region, forming a trench by patterning the second insulating film, the trench extending from a position over the first hole to a position over the second hole, and forming first, second, and third plugs in the first, second, and third holes and forming an interconnection in the trench, thereby forming the interconnection integrally formed with the first plug and the second plug.

Other objects and further features of the present application will become apparent from the following detailed description when read in conjunction with the attached drawings.

DESCRIPTION OF EMBODIMENTS

Prior to explaining the present embodiments, preliminary matter will be explained.

The inventor has conducted various studies on planar layouts of memory cells in order to achieve reduction in the cell size of a SRAM.

FIG. 1illustrates one of such planar layouts which is an enlarged plan view of a memory cell C in the SRAM. InFIG. 1, a word-line direction is indicated by X while a bit-line direction is indicated by Y.

In this example, a device isolation insulating film2for STI (shallow trench isolation) is formed on a silicon substrate1and first active regions1aand second active regions1bof the silicon substrate1are defined by this device isolation insulating film2.

Moreover, gate electrodes5made of polycrystalline silicon are formed on these active regions1aand1band on the device isolation insulating film2so as to extend in the word-line direction.

Two driver transistors TRdrive, two access transistors TRaccess, and two load transistors TRloadare formed in a memory cell C at portions where the gate electrodes5overlap with the active regions1aand1b, as illustrated inFIG. 1.

Further, first to third tungsten plugs15ato15cfor drawing source-drain regions of the above-described transistors TRdrive, TRaccess, and TRloadto an upper layer are formed on the active regions1aand1b.

Among these tungsten plugs, the first tungsten plug15ahas a rectangular planar shape overlapping with the gate electrode5and the first active region1a, and has a function to connect the gate electrode5directly to the first active region1a. This plug is also referred to as a shared contact.

Meanwhile, a first copper-containing interconnection18ahaving an L-shaped planar shape is formed on this first tungsten plug15a. The first copper-containing interconnection18aextends in the bit-line direction Y and plays a role in connecting the first tungsten plug15ato the second tungsten plug15b.

Moreover, the first copper-containing interconnection18ais formed to cover the entire upper surface of the first tungsten plug15ain order to reduce contact resistance with the first tungsten plug15a.

In the meantime, a copper-containing pad18bhaving a rectangular planar shape extending in the word-line direction X is formed on the third tungsten plug15c.

FIG. 2is an equivalent circuit diagram of the memory cell C of this SRAM.

As illustrated inFIG. 2, in one memory cell C, the respective gate electrodes5of the two access transistors TRaccessare electrically connected to word lines WL. Meanwhile, a bit line BL is electrically connected to the respective source-drain regions of the two access transistors TRaccess.

As illustrated inFIG. 3, the gate electrodes5are formed on the silicon substrate1with gate insulating films4, each made of a thermal oxide film, interposed therebetween.

Meanwhile, p-type source-drain regions7are formed in the silicon substrate1beside the gate electrodes5, and resistance in surface layer portions of the source-drain regions7is reduced by refractory metal silicide layers10such as nickel silicide layers.

Then, a cover insulating film11made of silicon nitride and a first insulating film12made of silicon oxide are formed in this order on the gate electrodes5, and the first tungsten plug15aand the second tungsten plug15bdescribed above are buried in these insulating films11and12.

Moreover, a first copper diffusion prevention insulating film13made of silicon carbide (SiC) and a second insulating film14made of silicon oxide are formed in this order on the first insulating film12.

A first trench14aand a second trench14bare formed in these insulating films13and14, and the first copper-containing interconnection18aand the copper-containing pad18bdescribed above are buried in these trenches by a single damascene method. As described previously, the first copper-containing interconnection18ais formed to cover the entire upper surface of the first tungsten plug15ain order to reduce the contact resistance with the first tungsten plug15a.

Further, a second copper diffusion prevention insulating film21made of silicon carbide and a third insulating film22made of silicon oxide are formed on the first copper-containing interconnection18a, the copper-containing pad18b, and the second insulating film14.

A second copper-containing interconnection25and a copper-containing plug24are buried in the third insulating film22. Here, the copper-containing plug24is electrically connected to the second copper-containing plug15bvia the copper-containing pad18b.

By connecting the vertically located plugs15band24to each other via the copper-containing pad18bas described above, it is possible to ensure the contact areas between the copper-containing pad18band the respective plugs15band24, and thereby to prevent an increase in the contact resistance between these plugs15band24.

Moreover, the area of the copper-containing pad18bis increased by forming the planar shape of the copper-containing pad18binto the rectangle that extends in the word-line direction as illustrated inFIG. 1. Therefore, when forming the second trench14bby photolithography for burying therein the copper-containing pad18b, the shape of the trench14bis less affected by an optical proximity effect. In this way, it is possible to suppress deformation of the shape of the copper-containing pad18band thereby to achieve the above-described effect of preventing the increase in the contact resistance between the respective plugs15band24.

However, according to the planar layout of the SRAM illustrated inFIG. 1, the first copper-containing interconnection18ais formed into the L-shaped planar shape in order to cover the entire upper surface of the first tungsten plug15a. As a consequence, a distance D between the first copper-containing interconnection18aand the copper-containing pad18bis reduced.

Therefore, it is necessary to separate the first copper-containing interconnection18afrom the copper-containing pad18balong the bit-line direction Y in order to reduce a risk of an electrical short circuit between the first copper-containing interconnection18aand the copper-containing pad18battributable to the shorter distance D. Accordingly, this structure has a problem that it is not possible to achieve reduction in the area of the memory cell C because the memory cell C is extended in the bit-line direction Y.

Further, the first copper-containing interconnection18ahaving the L-shape has the more complicated contour as compared to a straight interconnection. Accordingly, OPC (optical proximity correction) processing to be performed on an exposure mask used for forming the first trench14ain the lithography is also complicated. For this reason, there is another problem that it takes a long time for designing the SRAM due to time-consuming calculation for the OPC.

On the other hand, as the generation of the MOS transistors advances and gate lengths thereof are shortened, the diameters of the tungsten plugs also need to be formed smaller so as to achieve reduction in size of the MOS transistors. However, the smaller diameters of the tungsten plugs may increase the resistance of tungsten plugs and may adversely affect characteristics of the MOS transistors.

FIG. 4is a graph illustrating a relation between a gate length of a MOS transistor and resistance of a tungsten plug having a diameter suitable for the gate length.

Note thatFIG. 4also illustrates a relation between the gate length and resistance of a copper-containing plug having a diameter suitable for the gate length for the purpose of comparison. Moreover, on resistance of the MOS transistor is also illustrated inFIG. 4. Here, the on resistance is resistance between a source and drain when the gate of the MOS transistor is in an on state.FIG. 4illustrates the on resistance in three types of channel widths, namely, wide, middle, and narrow widths in order to indicate how much the on resistance varies depending on the size of the channel width.

It is deemed desirable to set the resistance of the plug equal to or below about 1/10 as large as the on resistance in order to operate the MOS transistor normally.

As illustrated inFIG. 4, the resistance of the tungsten plug exceeds 1/10 of the on resistance in a generation where the gate length is shorter than 45 nm. Hence, it is understood that the tungsten plugs are unsuitable in this generation or later.

On the other hand, the resistance of the copper-containing plug exhibits a value equal to or below 1/10 of the on resistance even in the generation where the gate length is shorter than 45 nm.

Accordingly, in the above-described SRAM using the first to third tungsten plugs15ato15c, it is not possible to reduce the gate lengths of the transistors TRdrive, TRaccess, and TRloadwithout affecting the characteristics of these transistors.

In view of this knowledge, the inventor has achieved embodiments as described below.

First Embodiment

FIGS. 5A to 5Jare cross-sectional views during manufacture of a semiconductor device according to this embodiment andFIGS. 6A to 6Fare plan views thereof.

Note that both of a first cross section taken along the word-line direction and a second cross section taken along the bit-line direction are illustrated throughoutFIGS. 5A to 5J. The same applies to respective cross-sectional views illustrated in conjunction with a second embodiment and a third embodiment to be described later.

This semiconductor device is a SRAM, which is manufactured as described below.

First, as illustrated inFIG. 5A, a device isolation trench31xhaving a depth of about 300 nm is formed on a silicon substrate31serving as a semiconductor substrate.

Then, after a silicon oxide film serving as a device isolation insulating film32for the STI is formed on the entire upper surface of the silicon substrate31by a CVD (chemical vapor deposition) method, an excessive portion of the device isolation insulating film32on the surface of the silicon substrate31is polished and removed by a CMP (chemical mechanical polishing) method, thereby leaving the device isolation insulating film32only in the device isolation trench31x.

Thereafter, the device isolation insulating film32is subjected to annealing under conditions of a substrate temperature of about 1000° C. and processing time of about 30 seconds in order to increase a film density of the device isolation insulating film32.

FIG. 6Ais the plan view after completion of the above-described steps. Here, the second cross section inFIG. 5Acorresponds to a cross section taken along an X1-X1line inFIG. 6Aand the first cross section inFIG. 5Acorresponds to a cross section taken along a Y1-Y1line inFIG. 6A.

Moreover, the word-line direction is indicated by X while the bit-line direction perpendicular thereto is indicated by Y inFIG. 6A.

As illustrated inFIG. 6A, first active regions31aand second active regions31bare defined in the silicon substrate31by the device isolation insulating film32. All of these active regions31aand31bextend in the bit-line direction Y.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 5Bwill be described.

First, phosphorus is ion-implanted into the silicon substrate31in the first active region31aunder conditions of acceleration energy of 300 keV and a dose amount of 3×1013cm−2, thereby forming an n-well33.

Further, an n-type impurity diffused region for threshold adjustment is formed at a surface layer portion of the n-well33by ion implantation. As for the n-type impurity, arsenic is ion-implanted under conditions of acceleration energy of 100 keV and a dose amount of 4×1012cm−2, for example.

In the meantime, a p-well39and a p-type impurity diffused region for threshold adjustment are formed in the second active region31b. In order to form the p-well39, boron is ion-implanted under conditions of acceleration energy of 150 keV and a dose amount of 3×1013cm−2, for example. Meanwhile, as for the p-type impurity for threshold adjustment, boron is ion-implanted under conditions of acceleration energy of 10 keV and a dose amount of 4×1012cm−2, for example.

Subsequently, an annealing process is performed under conditions of a substrate temperature of 1000° C. and processing time of 10 seconds for the purpose of diffusing the impurities in the respective wells33and39. Such an annealing process is also referred to as well annealing.

Then, a thermal oxide film having a thickness of about 1.2 nm is formed as a gate insulating film34by thermally oxidizing the surface of the silicon substrate31. Although conditions of the thermal oxidation are not particularly limited, the gate insulating film34of this embodiment is formed by a RTO (rapid thermal oxidation) method under a condition of a substrate temperature of about 900° C.

Moreover, a polycrystalline silicon film having a film thickness of about 100 nm is formed on the gate insulating film34by a CVD method, and a gate electrode35is formed by patterning the polycrystalline silicon film.

Thereafter, boron serving as a p-type impurity is ion-implanted into the silicon substrate31while using the gate electrode35as a mask, thereby forming a p-type source-drain extension36ain the silicon substrate31in the first active region31a. Conditions for the ion implantation include acceleration energy of 0.5 keV and a dose amount of 1×1015cm−2, for example.

In the meantime, arsenic is ion-implanted into the silicon substrate31in the second active region31bunder conditions of acceleration energy of 3 keV and a dose amount of 1×1015cm−2, thereby forming an n-type source-drain extension36b.

Then, after forming an insulative side wall38made of a silicon oxide film beside the respective gate electrodes35, a p-type source-drain region37ais formed by ion-implanting a p-type impurity into the silicon substrate31in the first active region31a. As for the p-type impurity, boron is ion-implanted under conditions of acceleration energy of 5 keV and a dose amount of 2×1015cm−2.

In the meantime, phosphorus serving as an n-type impurity is ion-implanted into the silicon substrate31in the second active region31bunder conditions of acceleration energy of 15 keV and a dose amount of 2×1015cm−2, thereby forming an n-type source-drain region37b.

Thereafter, a stacked film including a nickel film and a titanium nitride film is formed on the entire upper surface of the silicon substrate31by a sputtering method, and then a refractory metal silicide layer40such as a nickel silicide layer is formed by annealing the stacked film to be reacted with the silicon. Although conditions for the annealing are not particularly limited, the substrate temperature is set in a range from 400° C. to 550° C. while the processing time is set in a range from several seconds to several tens of minutes in this embodiment. Meanwhile, the thickness of the nickel film is set in a range from 5 nm to 20 nm, for example.

After the annealing process, the unreacted nickel film on the device isolation insulating film32is removed by a wet etching method using a mixed solution of sulfuric acid and hydrogen peroxide water as an etchant. As a result, the refractory metal silicide layer40is left only on the source-drain regions37aand37band on the gate electrodes35.

FIG. 6Bis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 5Bcorresponds to a cross section taken along an X2-X2line inFIG. 6Band the first cross section inFIG. 5Bcorresponds to a cross section taken along a Y2-Y2line inFIG. 6B.

As illustrated inFIG. 6B, the gate electrodes35are formed respectively on the device isolation insulating film32and on the active regions31aand31b.

Moreover, two driver transistors TRdrive, two access transistors TRaccess, and two load transistors TRloadare formed in a memory cell C as illustrated inFIG. 6Bat portions where the gate electrodes35overlap with the respective active regions31aand31b.

Meanwhile, the access transistors TRaccessand the driver transistors TRdriveshare the respective source-drain region in the second active regions31b.

An equivalent circuit of the memory cell including these transistors TRdrive, TRaccess, and TRloadis similar toFIG. 2illustrated in conjunction with the preliminary matter.

Subsequently, as illustrated inFIG. 5C, a silicon nitride film serving as a cover insulating film41is formed in a thickness of about 50 nm on the entire upper surface of the silicon substrate31by the CVD method.

Moreover, a silicon nitride film is formed in a thickness of about 500 nm on the cover insulating film41by a thermal CVD method. The silicon oxide film thus formed is used as a first insulating film42.

Subsequently, as illustrated inFIG. 5D, a photoresist is coated on the first insulating film42, and a first resist pattern46provided with hole-shaped windows46ato46cis formed by exposing and developing the photoresist.

Then, the cover insulating film41and the first insulating film42are dry etched using the first resist pattern46as a mask, thereby forming first to third holes42ato42con these insulating films.

The dry etching is performed by RIE (reactive ion etching) to change etching gases between an etching process on the first insulating film42and an etching process on the cover insulating film41. In the etching process on the first insulating film42, mixed gas of C2F6gas and CH3gas is used as an etching gas while the cover insulating film41serves as an etching stopper. Meanwhile, in the etching process on the cover insulating film41, CF4gas is used as an etching gas while the refractory metal silicide layer40serves as an etching stopper.

As illustrated in the first cross section, both of the first hole42aand the third hole42care formed on the p-type source-drain region37a, and the first hole42ais formed to further overlap with the gate electrode35.

Meanwhile, as illustrated in the second cross section, the second hole42bis formed on the n-type source-drain region37b.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 5Ewill be described.

First, a tantalum film and a tantalum nitride film are formed in this order as a barrier metal film in the respective holes42ato42cand on an upper surface of the first insulating film42by the sputtering method. As for film thicknesses of the respective films, the tantalum film is set to about 5 nm while the tantalum nitride film is set to about 10 nm.

Then, a copper film is formed as a seed layer on this barrier metal film by the sputtering method and a copper plated film is formed using the seed layer as a power feeding layer, thereby completely burying the respective holes42ato42cwith the copper plated film.

Thereafter, the excessive copper plated film, the seed layer, and the barrier metal film on the first insulating film42are polished and removed by the CMP method. In this way, first to third copper-containing plugs45ato45cpenetrating the first insulating film42are formed inside the respective holes42ato42c.

FIG. 6Cis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 5Ecorresponds to a cross section taken along an X3-X3line inFIG. 6Cand the first cross section inFIG. 5Ecorresponds to a cross section taken along a Y3-Y3line inFIG. 6C.

InFIG. 6C, illustration of the cover insulating film41and the first insulating film42is omitted for the purpose of preventing complication of the drawing.

As illustrated inFIG. 6C, the first copper-containing plug45ais formed to overlap with the gate electrode35and the first active region31a, and is formed into a rectangular planar shape so as to correspond to the first hole42a(seeFIG. 5E). The extending direction of the first copper-containing plug45ais parallel to the bit-line direction Y.

Meanwhile, each of the second copper-containing plug45band the third copper-containing plug45cis formed into a square planar shape.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 5Fwill be described.

First, a silicon carbide film serving as a first copper diffusion prevention insulating film43is formed in a thickness of about 50 nm on the first insulating film42and on the first to third copper-containing plugs45ato45cby the CVD method.

Further, a silicon oxycarbide (SiOC) film is formed in a thickness of about 150 nm on the first copper diffusion prevention insulating film43by the CVD method, and the silicon oxycarbide film thus formed is used as a second insulating film44.

Then, after forming a second resist patter47on the second insulating film44, the first copper diffusion prevention insulating film43and the second insulating film44are dry etched using the second resist pattern47as a mask, thereby forming a first trench44aand a second trench44bin these insulating films.

The dry etching is performed by the RIE. In the RIE, etching gas containing either CHF-based gas or CF-based gas is used as etching gas for the second insulating film44. Here, it is also possible to add inert gas such as argon gas or nitrogen gas to the etching gas.

Meanwhile, gas containing either SO2gas or NF3gas is used as etching gas for the first copper diffusion prevention insulating film43. Since the first insulating film42functions as the etching stopper against this etching gas, the first insulating film42is prevented from being etched when forming the trenches44aand44b.

As illustrated in the second cross section, the first trench44athus formed extends from a position over the first copper-containing plug45ato a position over the second copper-containing plug45b. Meanwhile, as illustrated in the first cross section, the first trench44ais formed away in the bit-line direction Y from a side surface45xout of side surfaces of the first copper-containing plug45a, which is located close to the gate electrode35.

In the meantime, the second trench44bis formed over the third copper-containing plug45cand in the respective films43and44therearound.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 5Gwill be described.

First, a tantalum film in a thickness of about 5 nm and a tantalum nitride film in a thickness of about 10 nm are formed in this order as a barrier metal film in the respective trenches44aand44band on an upper surface of the second insulating film44by the sputtering method.

Further, a copper film is formed as a seed layer on this barrier metal film by the sputtering method and a copper plated film is formed by an electrolytic plating method while applying electricity to the seed layer, thereby completely burying the respective trenches44aand44bwith the copper plated film.

Thereafter, the excessive copper plated film, the seed layer, and the barrier metal film on the second insulating film44are polished and removed by the CMP method. In this way, a first copper-containing interconnection48ais formed in the first trench44aand a copper-containing pad48bis formed in the second trench44b. The above-described method of forming the first copper-containing interconnection48aand the copper-containing pad48bin the process different from the process to form the respective copper-containing plugs45ato45cis referred to as a single damascene method.

Here, since the first trench44ais formed away from the side surface45xof the first copper-containing plug45a, the first copper-containing interconnection48ais formed to cover only a part of an upper surface of the first copper-containing plug45a.

Meanwhile, the copper-containing pad48bis formed on the third copper-containing plug45cin a manner that the pad48bis buried in the second insulating film44around the plug45c.

FIG. 6Dis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 5Gcorresponds to a cross section taken along an X4-X4line inFIG. 6Dand the first cross section inFIG. 5Gcorresponds to a cross section taken along a Y4-Y4line inFIG. 6D.

As illustrated inFIG. 6D, the first copper-containing interconnection48aextends from the position over the first copper-containing plug45ato the position over the second copper-containing plug45b, and has a rectangular planar shape extending in the word-line direction X.

Further, the first copper-containing interconnection48ais formed to recede from the side surface45xof the first copper-containing plug45ain a recession amount ΔY in the bit-line direction Y, and thereby covers only a part of the upper surface of the first copper-containing plug45a.

Here, the planar shape of the first copper-containing interconnection48ais not limited only to the above-mentioned rectangular shape as long as the first copper-containing interconnection48arecedes from the side surface45xand to expose the upper surface of the first copper-containing plug45aas described previously. For example, the first copper-containing interconnection48amay also be formed into an L-shape as similar to the first copper-containing interconnection18a(seeFIG. 1) of the preliminary matter.

Meanwhile, the planar shape of the copper-containing pad48bis a rectangular shape extending in the word-line direction X. By applying this shape, the shape of the trench44b(seeFIG. 5F) is less affected by an optical proximity effect when forming the second trench44bby photolithography for burying therein the copper-containing pad48bas similar to the preliminary matter. Hence it is possible to suppress deformation of the shape of the copper-containing pad48b.

Subsequently, as illustrated inFIG. 5H, a second copper diffusion prevention insulating film51and a third insulating film52are formed in this order respectively on the second insulating film44, the first copper-containing interconnection48a, and the copper-containing pad48bby the CVD method.

Of these insulating films, a silicon carbide film having a thickness of about 50 nm is formed as the second copper diffusion prevention insulating film51and a silicon oxycarbide film having a thickness of about 250 nm is formed as the third insulating film52.

Thereafter, a third resist pattern53provided with a hole-shaped window53ais formed on the third insulating film52, and a fourth hole52ais formed in the copper-containing pad48bby dry etching the respective insulating films51and52using the third resist pattern53as a mask.

The dry etching is performed by the RIE. Either CHF-based gas or CF-based gas is used as etching gas for the third insulating film52. It is also possible to add inert gas such as argon gas or nitrogen gas to the etching gas.

Meanwhile, gas containing either SO2gas or NF3gas is used as etching gas for the second copper diffusion prevention insulating film51.

Subsequently, as illustrated inFIG. 5I, a photoresist is coated on the third insulating film52and in the fourth hole52a, and a fourth resist pattern54provided with a window54ahaving a wiring trench shape is formed by exposing and developing the photoresist. The fourth resist pattern54in the bottom portion of the fourth hole52ais not removed by development, but is left in the hole52a.

Then, the third insulating film52is dry etched to a halfway depth by the RIE using the fourth resist pattern54as a mask. In this way, a third trench52bexposing the fourth hole52aat a bottom and a fourth trench52clocated at a distance from the third trench52bare formed on the third insulating film52.

The etching gas containing either CHF-based gas or CF-based gas, or these gas with addition of inert gas such as argon gas or nitrogen gas is used for etching gas in this process.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 5Jwill be described.

First, a tantalum film in a thickness of about 5 nm and a tantalum nitride film in a thickness of about 10 nm are formed in this order as a barrier metal film in the respective trenches52band53cand the fourth hole52a, and on an upper surface of the third insulating film52by the sputtering method.

Further, a copper film is formed as a seed layer on this barrier metal film by the sputtering method and a copper plated film is formed by the electrolytic plating method while applying electricity to the seed layer, thereby completely burying the respective trenches52band52cas well as the fourth hole52awith the copper plated film.

Thereafter, the excessive copper plated film, the seed layer, and the barrier metal film on the third insulating film52are polished and removed by the CMP method. In this way, a fourth copper-containing plug55apenetrating the third insulating film52and a second copper-containing interconnection55bare integrally formed in the third trench52band the fourth hole52a, respectively.

Meanwhile, a third copper-containing interconnection55cconstituting a word line (WL) is formed in the fourth trench52c.

The above-described method of integrally forming the fourth copper-containing interconnection55aand the second copper-containing pad55bis referred to as a dual damascene method.

The fourth copper-containing plug55ais electrically connected to the third copper-containing plug45cvia the copper-containing pad48b. Here, contact areas between the copper-containing pad48band the respective plugs45cand55aare ensured by connecting the respective plugs45cand55ato each other via the copper-containing pad48b. Accordingly, it is possible to prevent an increase in the contact resistance between these plugs45cand55aas compared to the case of connecting the respective plugs45cand55adirectly to each other without the copper-containing pad48binterposed therebetween.

Thereafter, a silicon carbide film serving as a third copper diffusion prevention insulating film57is formed in a thickness of about 50 nm on respective upper surfaces of the third insulating film52and the copper-containing interconnections55band55cby the CVD method.

FIG. 6Eis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 5Jcorresponds to a cross section taken along an X5-X5line inFIG. 6Eand the first cross section inFIG. 5Jcorresponds to a cross section taken along a Y5-Y5line inFIG. 6E.

Thereafter, as illustrated inFIG. 6F, a bit line BL and a fourth copper-containing interconnection56are formed over the third copper-containing interconnection55cby the dual damascene method.

In this way, a basic structure of the semiconductor device according to this embodiment is finished.

According to the above-described embodiment, as illustrated in the plan view ofFIG. 6D, the first copper-containing interconnection48ais formed to recede from the side surface45xof the first copper-containing plug45ain the bit-line direction Y to thereby cover only a part of the upper surface of the first copper-containing plug45awith the first copper-containing interconnection48a.

In this way, it is possible to provide a margin for the distance D between the first copper-containing interconnection48aand the conductor pattern located in the same layer as the first copper-containing interconnection48a, such as the copper-containing pad48b, as compared to the case of forming the first copper-containing interconnection48ainto the L-shape as in the preliminary matter. Therefore, it is possible to downsize the memory cell C by reducing the distance D.

The inventor performed calculations in terms of the generation having the gate length of 22 nm, for example. In the example of the preliminary matter illustrated inFIG. 1, the length of the memory cell C in the word-line direction X is 0.5 μm while the length thereof in the bit-line direction Y is 0.264 μm. Hence the area of the memory cell C is 0.13 μm2.

On the other hand, in the layout of this embodiment illustrated inFIG. 6D, the length of the memory cell C in the word-line direction X is 0.562 μm while the length thereof in the bit-line direction Y is 0.184 μm. Hence, the area of the memory cell C is 0.10 μm2. Here, the reason why the length in the word-line direction X of the memory cell C of the embodiment is longer than the length in the preliminary matter is that a length A in the word-line direction X of another copper-containing pad48cis increased in order to ensure to the area of the copper-containing pad48cwhich is formed on the same layer as the copper-containing pad48b. Another reason is that a clearance B is intended to be ensured between the copper-containing pad48cand still another copper-containing pad48d.

In this manner, according to this embodiment, it is possible to reduce the area of the memory cell C by about 23% less than the relevant area in the case of the preliminary matter. Thus it is possible to confirm that the embodiment can contribute to reduction in the cell size of the SRAM.

Moreover, by forming the first copper-containing interconnection48areceding from the side surface45xof the first copper-containing plug45ain the bit-line direction, the planar shape of the first copper-containing interconnection48ais formed into the simple rectangular shape extending in the word-line direction.

In this way, it is possible to simplify the OPC processing to be performed on an exposure mask when exposing the second resist pattern47(seeFIG. 5F) as compared to the case of forming the first copper-containing interconnection48ainto the L-shape as in the preliminary matter. Hence it is possible to design the exposure mask in a shorter period of time.

Furthermore, in this embodiment, the copper-containing plugs having lower resistance than that of the tungsten plugs are formed as the respective plugs45ato45cto be connected to the respective active regions31aand31b. Accordingly, as illustrated inFIG. 4, the resistance of the respective copper-contain plugs45ato45ccan be maintained at about 1/10 or less of the on resistance of the MOS transistor, even when the MOS transistor comes to have a gate length of 45 nm or below with the progress of generations. In this way, it is possible to downsize the respective transistors TRdrive, TRaccess, and TRloadwhile retaining the characteristics of these transistors, and thereby to further downsize the memory cell of the SRAM.

Meanwhile, since the first copper-containing plug45ahas smaller resistance as compared to the tungsten plug, it is possible to maintain the contact resistance between the first copper-containing plug45aand the copper-containing interconnection48aeven when only a part of the upper surface of the first copper-containing plug45ais covered with the copper-containing interconnection48a.

Second Embodiment

FIGS. 7A to 7Fare cross-sectional views during manufacture of a semiconductor device according to this embodiment, andFIGS. 8A to 8Dare plan views thereof. InFIGS. 7A to 7F, the same constituents as those in the first embodiment are designated by the same reference numerals as the first embodiment, and description thereof will be omitted in the following.

In the first embodiment, the first copper-containing interconnection48ais formed by the single damascene method as described with reference toFIG. 5GIn contrast, in this embodiment, the corresponding copper-containing interconnection is formed by the dual damascene method.

To manufacture the semiconductor device according to this embodiment, the steps in the first embodiment as illustrated inFIGS. 5A to 5Care firstly executed, and then a silicon carbide film serving as an etching stopper film60is formed in a thickness of about 50 nm on the first insulating film42by the CVD method as illustrated inFIG. 7A.

Here, the etching stopper film60is not limited only to the silicon carbide film. It is also possible to form a silicon nitride film as the etching stopper film60instead.

Moreover, a second insulating film61and an antireflection insulating film62are formed in this order on this etching stopper film60. The second insulating film61is a silicon oxide film in a thickness of about 150 nm which is formed by the CVD method, for example. Meanwhile, as for the antireflection insulating film62, a silicon nitride film is formed in a thickness of about 30 nm by the CVD method.

FIG. 8Ais the plan view after completion of the above-described steps. Here, the second cross section inFIG. 7Acorresponds to a cross section taken along an X6-X6line inFIG. 8Aand the first cross section inFIG. 7Acorresponds to a cross section taken along a Y6-Y6line inFIG. 8A.

Here, the respective insulating films41,42, and60to62are omitted inFIG. 8Ain order to facilitate the understanding of planar layouts of the first and second active regions31aand31bas well as the gate electrodes35.

As illustrated inFIG. 8A, the driver transistors TRdrive, the access transistors TRaccess, and the load transistors TRloadare formed as similar to the first embodiment at the portions where the gate electrodes35overlap with the respective active regions31aand31b.

Subsequently, as illustrated inFIG. 7B, a first resist pattern63provided with hole-shaped windows63ato63cis formed on the antireflection insulating film62.

The first resist pattern63is used as a mask for etching the respective insulating films42and60to62. The first to third holes42ato42care formed in these insulating films42and60to62by the RIE.

The etching gas used in the RIE is not particularly limited. For example, gas containing SO2gas or NF3gas is used as the etching gas for the etching stopper film60.

Meanwhile, the mixed gas of C2F6gas and CH3gas is used as the etching gas for the first insulating film42and the second insulating film61, for example. When using this etching gas, the etching rate of the cover insulating film41is lower than that of the first insulating film42. Accordingly, this etching process stops on the upper surface of the cover insulating film41.

As illustrated in the first cross section, among the respective holes thus formed, both of the first hole42aand the third hole42care formed on the p-type source-drain region37aand the first hole42ais formed to further overlap with the gate electrode35.

Meanwhile, as illustrated in the second cross section, the second hole42bis formed on the n-type source-drain region37b.

Subsequently, as illustrated inFIG. 7C, the cover insulating film41below the respective contact holes42ato42cis dry etched and removed by performing the RIE while changing the etching gas into the CF4gas.

Next, as illustrated inFIG. 7D, a photoresist is coated again on the antireflection insulating film62, and then is developed by exposure to form a second resist pattern65provided with a window65ahaving a wiring trench shape and overlapping with the first hole42a.

The second resist pattern65in the bottom portions of the first hole42aand the second hole42bis not removed by development but is left in these holes42aand42b. Meanwhile, the third hole42cis completely filled with the second resist pattern65.

Then, the antireflection insulating film62and the second insulating film61are dry etched by the RIE while using the second resist pattern65as a mask, thereby forming a first trench61ain these insulating films61and62.

The etching gas with which the etching rate of the etching stopper film60is lower than that of the second insulating film61, i.e., the mixed gas of C2F6gas and CH3gas, for example, is used in this dry etching process. In this way, the etching stops on the etching stopper film60and the first insulating film42is prevented from being etched.

Meanwhile, the first trench61athus formed extends from a position over the first hole42ato a position over the second hole42bas illustrated in the second cross section.

Next, steps to be carried out in order to obtain a cross-sectional structure illustrated inFIG. 7Ewill be described.

First, a tantalum film and a tantalum nitride film are formed in this order as a barrier metal film in the respective holes42ato42cas well as the first trench61aand on an upper surface of the antireflection insulating film62by the sputtering method. Although the film thickness of the barrier metal film is not particularly limited, the tantalum film is set to about 5 nm and the tantalum nitride film is set to about 10 nm in this embodiment.

Then, a copper film is formed as a seed layer on this barrier metal film by the sputtering method and a copper plated film is formed using the seed layer as a power feeding layer, thereby completely burying the respective holes42ato42cand the first trench61awith the copper plated film.

Thereafter, the excessive copper plated film, the seed layer, and the barrier metal film on the antireflection insulating film62are polished and removed by the CMP method.

In this way, first to third copper-containing plugs70ato70care formed in the respective holes42ato42cby the dual damascene method. Moreover, in this dual damascene method, a first copper-containing interconnection70is formed in the first trench61aover the etching stopper film60.

The first copper-containing interconnection70formed by the dual damascene method is formed integrally with the first copper-containing plug70aand the second copper-containing plug70b. Meanwhile, the third copper-containing plug70cpenetrates the first insulating film42and the second insulating film61and is electrically connected to the source-drain region37a.

FIG. 8Bis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 7Ecorresponds to a cross section taken along an X7-X7line inFIG. 8Band the first cross section inFIG. 7Ecorresponds to a cross section taken along a Y7-Y7line inFIG. 8B.

As illustrated inFIG. 8B, the first copper-containing plug70ahas a rectangular planar shape so as to correspond to the first hole42a(seeFIG. 7E).

Meanwhile, the first copper-containing interconnection70has an L-shaped planar shape which is formed to cover the above-described first copper-containing plug70a.

Even when the first copper-containing interconnection70is formed into the L-shape, the copper-containing pad48b(seeFIG. 6D) is not formed on the third copper-containing plug70cin this embodiment unlike the first embodiment, so that it is possible to gain a space by omitting the copper-containing pad48b. Accordingly, it is possible to reduce the length of the memory cell C in the bit-line direction Y by curtailing the distance D between the first copper-containing interconnection70and the third copper-containing plug70c, and thereby to achieve reduction in the cell size.

Next, as illustrated inFIG. 7F, the third insulating film52, the third copper-containing interconnection55cconstituting the word line (WL), and the like are formed by carrying out the steps inFIGS. 5H to 5Jas described in the first embodiment.

FIG. 8Cis the plan view after completion of the above-described steps. Here, the second cross section inFIG. 7Fcorresponds to a cross section taken along an X8-X8line inFIG. 8Cand the first cross section inFIG. 7Fcorresponds to a cross section taken along a Y8-Y8line inFIG. 8C.

Thereafter, as illustrated inFIG. 8D, the bit line BL and the fourth copper-containing interconnection56are formed over the third copper-containing interconnection55cby the dual damascene method as similar to the first embodiment.

In this way, a basic structure of the semiconductor device according to this embodiment is finished.

According to this embodiment, as described with reference toFIG. 7E, the third copper-containing plug70cis formed simultaneously with formation of the first copper-containing interconnection70by use of the dual damascene method.

The third copper-containing plug70cformed by the damascene method is formed to penetrate the second insulating film61. Therefore, it is not necessary to provide the copper-containing pad48b(seeFIG. 5J) for establishing contact with the third copper-containing plug70cand the fourth copper-containing plug55a(seeFIG. 7F).

Accordingly, as described with reference toFIG. 8B, it is possible to arrange the first copper-containing interconnection70with wide margin by omitting the copper-containing pad48b, and to reduce the cell size by curtailing the distance D between the first copper-containing interconnection70and the third copper-containing plug70c.

Moreover, since the dual damascene method can reduce the number of steps as compared to the single damascene method, this embodiment can further simplify the process as compared to the first embodiment.

However, as illustrated inFIG. 7F, when the third copper-containing plug70cis formed by the dual damascene method, the depth of the third hole42cbecomes deeper than that in the first embodiment by the thickness of the second insulating film61. Hence an aspect ratio of the third hole42cis increased as compared to the first embodiment.

Such an increase in the aspect ratio may cause deterioration in burying performance of the barrier metal film, the copper plated film, and the like in the third hole42c. Accordingly, it may be necessary to introduce a novel film deposition apparatus or a novel process which can improve the burying performance.

To avoid this problem, it is preferable to make a diameter x1of the third hold42cas large as possible and to suppress the increase in the aspect ratio of the third hole42c. The same applies to a third embodiment to be described later.

The degree of the increase in the size of the diameter x1is not particularly limited. However, it is preferable to make the diameter x1larger than a diameter x2of the fourth hole52a, for example.

However, if the diameter x1is made too large, there is a risk of affecting reduction in the cell size. Accordingly, an upper limit of the diameter x1is preferably set about 1.2 times as large as the diameter x2.

Here, when the respective holes42cand52ahave tapered cross-sectional shapes as illustrated inFIG. 7F, the diameters x1and x2of these holes42cand52aat bottom surfaces of the respective plugs70cand55aare compared with each other.

By the way, in this embodiment, the etching stopper film60is formed between the first insulating film42and the second insulating film61. The etching stopper film60plays a role in preventing the first insulating film42from being etched when the first trench61ais formed by etching in the step illustrated inFIG. 7D.

FIGS. 9A to 9Care cross-sectional views during manufacture of a semiconductor device according to a comparative example for explaining an advantage obtained by the prevention of etching the first insulating film42in this manner. InFIGS. 9A to 9C, the same constituents as those in this embodiment will be designated by the same reference numerals as those in this embodiment and description thereof will be omitted in the following.

As illustrated inFIG. 9A, this comparative example omits the etching stopper film60and the second insulating film61from this embodiment. Then, as similar to the steps described above in conjunction withFIGS. 7B and 7C, the cover insulating film41and the first insulating film42are dry etched using the first resist pattern63as the mask, whereby the first to third holes42ato42care formed on these insulating films41and42.

After removing the first resist pattern63, the second resist pattern65is formed on the antireflection insulating film62similarly to this embodiment as illustrated inFIG. 9B.

Then, the first insulating film42is dry etched to a midway depth using the second resist pattern65as the mask, thereby forming the first trench42din the first insulating film42.

At this time, a bottom surface A of the first trench42dis not covered with the second resist pattern65, and is therefore formed into a chamfered shape as illustrated inFIG. 9Bdue to exposure to an etching atmosphere.

Subsequently, after removing the second resist pattern65, the first to third copper-containing plugs70ato70care formed in the first to third holes42ato42cby the dual damascene method as illustrated inFIG. 9C, and the first copper-containing interconnection70is formed in the first trench42d.

According to this comparative example, since the bottom surface A of the first groove42dis chambered as illustrated inFIG. 9B, the distance d between the gate electrode35and the first copper-containing interconnection70becomes shorter as illustrated inFIG. 9C, thereby incurring a problem of reduction in voltage resistance between the first copper-containing interconnection70and the gate electrode35.

On the other hand, in the present embodiment, since the bottom surface of the first groove61ais protected by the etching stopper film as illustrated inFIG. 7D, it is possible to prevent the bottom surface of the first trench61afrom being etched and to avoid reduction in the voltage resistance between the first copper-containing interconnection70and the gate electrode35.

Third Embodiment

In this embodiment, the first copper-containing interconnection70is formed by the dual damascene method as similar to the second embodiment. However, as will be described later, a stacked structure of the insulating films for burying the fist copper-containing interconnection70of this embodiment is different from the second embodiment.

FIGS. 10A to 10Fare cross-sectional views during manufacture of a semiconductor device according to this embodiment. InFIGS. 10A to 10F, the same constituents as those described in the first and second embodiments will be designated by the same reference numerals as those in the embodiments and description thereof will be omitted in the following.

Moreover, since the planar layout of the semiconductor device according to this embodiment is similar to that of the second embodiment. Therefore, the plan views of the semiconductor device will also be omitted herein.

To manufacture the semiconductor device according to this embodiment, the steps in the first embodiment as described in conjunction withFIGS. 5A to 5Care firstly executed, and then a second insulating film81is formed on the first insulating film42as illustrated inFIG. 10A.

The second insulating film81is a silicon oxycarbide film having a thickness of about 150 nm, which is formed by the CVD method, for example.

Further, a silicon oxy-nitride film serving as an antireflection insulating film82is formed in a thickness of about 30 nm on this second insulating film81by the CVD method.

Next, as illustrated inFIG. 10B, a photoresist is coated on the antireflection insulating film82, and the first resist pattern63provided with the hole-shaped windows63ato63cis formed by exposing and developing the photoresist.

Then, the respective insulating films42,81, and82are sequentially dry etched by the RIE while using this first resist pattern63as the mask, thereby forming the first to third holes42ato42cin these insulating films42,81, and82.

The mixed gas of C2F6gas and CH3gas is the etching gas usable in this dry etching process, for example. When using this etching gas, the etching rate of the cover insulating film41is lower than that of the first insulating film42. Accordingly, this etching process stops on the upper surface of the cover insulating film41.

Subsequently, as illustrated inFIG. 10C, the cover insulating film41below the respective contact holes42ato42cis dry etched and removed by performing the RIE while changing the etching gas to the CF4gas.

Next, as illustrated inFIG. 10D, a photoresist is coated again on the antireflection insulating film82, and then is developed by exposure to form the second resist pattern65provided with the window65ahaving the wiring trench shape and overlapping with the first hole42a.

This second resist pattern65located bottom portions in the first hole42aand the second hole42bis not removed by development but is left in these holes42aand42b. Meanwhile, the third hole42cis completely filled with the second resist pattern65.

Then, the antireflection insulating film82and the second insulating film81are dry etched while using the second resist pattern65as the mask, thereby forming a first trench81aexposing the first hole42aand the second hole42bat a bottom surface thereof.

The dry etching is performed by the RIE and etching gas containing either CHF-based gas or CF-based gas is used as the etching gas. Here, it is also possible to add inert gas such as argon gas or nitrogen gas to the etching gas.

When using such an etching gas, the etching rate of the first insulating film42becomes lower than that of the second insulating film81. Accordingly, the first insulating film42functions as an etching stopper film, whereby the etching process stops on the upper surface of the first insulating film42.

Subsequently, as illustrated inFIG. 10E, the barrier metal film, the seed layer, and the copper plated film are formed in this order in the first to third holes42ato42cand in the first trench81aas similar to the second embodiment.

In this way, the first to third copper-containing plugs70ato70care buried in the first to third holes42ato42cby the dual damascene method. Moreover, the first copper-containing interconnection70is formed integrally with the first and second copper-containing plugs70aand70bin the first trench81a.

Subsequently, as illustrated inFIG. 10F, the third insulating film52, the third copper-containing interconnection55cconstituting the word line (WL), and the like are formed by carrying out the steps inFIGS. 5H to 5Jas described in the first embodiment.

Thereafter, the process goes to the steps of forming the insulating film on the entire upper surface of the silicon substrate31and then forming the copper-containing interconnection constituting the bit line BL is formed on the insulating film by the dual damascene method as similar to the first embodiment. However, the description thereof will be omitted.

In this way, a basic structure of the semiconductor device according to this embodiment is finished.

According to this embodiment, as illustrated inFIG. 10D, the first insulating film42functions as the etching stopper film by using the etching gas with which the etching rate of the first insulating film42becomes lower than the etching rate of the second insulating film81. For this reason, there is no risk that the bottom surface of the first trench81ais chamfered in this etching process. Hence it is possible to suppress reduction in the voltage resistance between the gate electrode35and the first copper-containing interconnection70as observed in the comparative example inFIG. 9C, which is attributable to reduction in the distance d therebetween.

Moreover, according to this embodiment, the first insulating film42is used as the etching stopper as described above. Therefore, it is not necessary to provide the etching stopper film60formed in the second embodiment. Hence the process can be further simplified as compared to the second embodiment.