Semiconductor device

Provided is a semiconductor device including a substrate, a gate structure, a first metal layer, and a gate via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins and extends along a first direction. The first metal layer extends along a second direction and is disposed over the gate structure. The gate via is disposed between the gate structure and the first metal layer. The gate via has a longitudinal axis extending along the first direction and across the first metal layer. A length of the longitudinal axis of the gate via is greater than a width of the first metal layer.

BACKGROUND

In nanometer (nm) generations, the fin-type field effect transistors (FinFETs) have become most popular candidate for high performance and lower leakage application. With the rapid growth of semiconductor technology, the size of the FinFETs is continued to shrink, especially to shrink the gate length and gate height for both high density and high performance requirements. This narrow gate length and lower gate height benefit the transistor capacitance on both gate to channel and gate to contact. However, this gate shrinking will also result in the higher gate resistance, thereby impacting the gate delay of the high performance device. In 10 nm or under 10 nm generation, the narrower and longer gate electrode will face a trade-off between gate capacitance and gate resistance. In other word, how to solve the above problems will become an important key for the next generation technology.

DETAILED DESCRIPTION

FIG. 1is a top view of a semiconductor device in accordance with a first embodiment.FIG. 2Ais a cross-sectional view of line A-A′ ofFIG. 1.FIG. 2Bis a cross-sectional view of line B-B′ ofFIG. 1.FIG. 2Cis a cross-sectional view of line C-C′ ofFIG. 1. In some embodiments, all semiconductor devices discussed in the following embodiments include N-type metal oxide semiconductor (NMOS) FinFETs, P-type metal oxide semiconductor (PMOS) FinFETs, complementary metal oxide semiconductor (CMOS) FinFETs, or a combination thereof. In some alternative embodiments, all semiconductor devices discussed in the following embodiments may include 2D-FinFET, 3D-FinFET, or a combination thereof. Thus, no repeat in the following paragraph.

Referring toFIGS. 1, 2A, 2B, and 2C, a semiconductor device10of the first embodiment is provided. In detail, the semiconductor device10includes a substrate100, a well region102, a plurality of isolation structures103, a plurality of source and/or drain (S/D) structures106, a plurality of gate structures108, a dielectric layer116, a plurality of contacts118, two gate vias124, two source vias120, a drain via122, a dielectric layer130, a first metal layer132, a second metal layer134, and a third metal layer136.

In some embodiments, the substrate100may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate100may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate10may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some alternative embodiments, the substrate100includes bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI—Si, SOI—SiGe, III-VI material, or a combination thereof.

The substrate100has a plurality of semiconductor fins104to define an active region AA. In detail, as shown inFIG. 1, the semiconductor fins104are semiconductor strips extending along a second direction D2. In some embodiments, the semiconductor fins104may be formed on the substrate100by etching trenches in the substrate100. The etching may be any acceptable etching process, such as a reactive ion etching (RIE) process, neutral beam etching (NBE) process, the like, or a combination thereof. In other embodiments, the etching process may be an anisotropic process. In the case, as shown inFIGS. 2A, 2B, and 2C, the semiconductor fins104protrude from a top surface of the substrate100. InFIG. 1, four semiconductor fins104are shown to represent the plurality of semiconductor fins104, but the disclosure is not limited thereto. In some alternative embodiment, the plurality of semiconductor fins104include at least three semiconductor fins, such as three, four, five, six, or more semiconductor fins.

In addition, the substrate100may comprise various doped regions, such as a well region102, depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the well region102may be doped with p-type or n-type dopants. For example, the well region102may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The fabrication includes performing one or more doping processes, such as implantation processes to form the well region102in the substrate100. In some embodiments, a conductive type of the well region102is different from a conductive type of the substrate100, while the conductive type of the well region102is the same as a conductive type of the semiconductor fins104. In other embodiments, as shown inFIGS. 2A, 2B, and 2C, the well region is optional formed between the substrate100and the semiconductor fins104.

InFIGS. 2A, 2B, and 2C, the isolation structures103are disposed aside the semiconductor fins104. In some embodiments, the isolation structures103may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), the like, or a combination thereof, and may be formed by depositing an insulation material in an acceptable deposition process, such as a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or the like; planarizing the insulation material in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like; and recessing the insulation material in an acceptable etching process, such as a dry etching, a wet etching, or a combination thereof. In the case, the semiconductor fins104protrude from between adjacent isolation structures103. That is, top surfaces of the isolation structures103are lower than top surfaces of the semiconductor fins104. Further, the top surfaces of the isolation structures103may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. In some alternative embodiments, the isolation structures103may be shallow trench isolation (STI) structures.

InFIG. 1, the gate structures108are disposed across the semiconductor fins104and extends along a first direction D1. In some embodiments, the first direction D1and the second direction D2are different. For example, the first direction D1is perpendicular or orthogonal to the second direction D2. In detail, as shown inFIG. 2A, one of the gate structures108includes a gate dielectric layer110and a gate electrode112over the gate dielectric layer110. The gate dielectric layer110conformally covers surfaces of the semiconductor fins104exposed by the isolation structures103. In some embodiments, the gate dielectric layer110may be a high-k dielectric material having a k value greater than about 7, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The formation methods of the gate dielectric layer110may include Molecular-Beam Deposition (MBD), ALD, PECVD, or the like. In some alternative embodiments, the gate dielectric layer110may include SiON, Ta2O5, Al2O3, nitrogen-containing oxide layer, nitrided oxide, metal oxide dielectric material, Hf-containing oxide, Ta-containing oxide, Ti-containing oxide, Zr-containing oxide, Al-containing oxide, La-containing oxide, high k material (k>5) or a combination thereof. In some embodiments, the gate electrode112may include polysilicon, a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, a combination thereof, or multi-layers thereof. Although a single gate electrode112is shown, any number of work function tuning layers may be disposed between the gate dielectric layer110and the gate electrode112. For example, the gate structure108may include a multiple material structure selected from a group consisting of polysilicon/SiON structure, metals/high-k dielectric structure, Al/refractory metals/high-k dielectric structure, silicide/high-k dielectric structure, or a combination thereof, from top to bottom.

Further, gate spacers114are disposed along sidewalls of the gate structures108. The gate spacers114may be formed by conformally depositing a dielectric material and subsequently anisotropically etching the dielectric material. The dielectric material of the gate spacers114may include silicon oxide, silicon nitride, silicon oxynitride, SiCN, the like, or a combination thereof. The formation methods of the gate spacers114may include forming dielectric material by a deposition such as ALD, PECVD, or the like, and then performing an etch such as an anisotropic etching process.

InFIG. 2B, the S/D structures106are disposed over the semiconductor fins104at both sides of the gate structures108. In some embodiments, the S/D structures106may be epitaxial structures formed by growing epitaxial layers over exposed surfaces of the semiconductor fins104. Growing the epitaxy layers on exposed surfaces of the semiconductor fins104may include performing a pre-clean process to remove the native oxide on the surface of the semiconductor fins104. Next, an epitaxy process is performed to grow the epitaxial S/D structures106on the surfaces of the semiconductor fins104. Since the lattice constant of the epitaxial S/D structures106is different from the semiconductor fins104, channel regions of the semiconductor fins104are strained or stressed to enable carrier mobility of the device and enhance the device performance. The S/D structures106are portions of the semiconductor fins104not covered by the gate structures108, and the channel regions are the portions of the semiconductor fins104covered by the gate structures108. In an embodiment, the S/D structures106may be epitaxial structures including SiGe, SiGeC, Ge, Si, or a combination thereof when the semiconductor device10is the PMOS FET. In another embodiment, the S/D structures106may be epitaxial structures including SiP, SiC, SiPC, Si, or a combination thereof when the semiconductor device10is the NMOS FET. The S/D structures106may be formed by first etching the semiconductor fins104to form recesses (not shown), and then depositing a crystalline semiconductor material in the recess by a selective epitaxial growth (SEG) process that may fill the recess and even extend beyond the original surface of the semiconductor fins104to form a raised source/drain structure. In some cases, the S/D structures106may have facets or may have irregular shapes. The SEG process may use any suitable epitaxial growth method such as, vapor phase epitaxy (VPE), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE). In some cases, S/D structures106may be implanted with dopants using patterned photoresist masks. In some cases, the S/D structures106may be in situ doped during epitaxial growth.

InFIGS. 2A, 2B, and 2C, the dielectric layer116(also referred to as an interlayer dielectric (ILD) layer) is disposed over the semiconductor fins104and the S/D structures106. The dielectric layer116may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. In some embodiments, the dielectric layer116may include a single layer dielectric material or a multi-layer dielectric material. In this embodiment, the dielectric layer116includes dielectric layer116aand dielectric layer116bon the dielectric layer116a. The dielectric layer116aand the dielectric layer116bmay have the same material or different materials. In other some embodiments, a contact etching stop layer (CESL), not illustrated, is disposed between the dielectric layer116aand the S/D structures106and/or between the dielectric layer116aand gate electrode112, and between the dielectric layer116aand the gate spacers114.

InFIG. 2AandFIG. 2B, the dielectric layer130(also referred to as an inter-metal dielectric (IMD) layer) is formed over the dielectric layer116. In some embodiments, the dielectric layer130may be formed after the source vias120, the drain via122and the gate vias124are formed. The dielectric layer130may include a single layer dielectric material or a multi-layer dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. In some alternative embodiments, the dielectric layers130and116may have a same material or different materials.

InFIG. 2AandFIG. 2B, the first metal layer132, the second metal layer134, and the third metal layer136are disposed in the dielectric layer130. In detail, as shown inFIG. 1, the first metal layer132, the second metal layer134, and the third metal layer136extend along the second direction D2and are disposed across the gate structures108. The first metal layer132is disposed between the second metal layer134and the third metal layer136, and separated from the second metal layer134and the third metal layer136. In some embodiments, the first metal layer132, the second metal layer134, and the third metal layer136are referred to as metal one (M1). That is, the first metal layer132, the second metal layer134, and the third metal layer136are substantially at a same level. Herein, when elements are described as “at substantially the same level”, the elements are formed at substantially the same height in the same layer, or having the same positions embedded by the same layer. In some embodiments, the elements at substantially the same level are formed from the same material(s) with the same process step(s). In some embodiments, the tops of the elements at substantially the same level are substantially coplanar. For example, as shown inFIG. 2AandFIG. 2B, top surfaces of the first metal layer132, the second metal layer134, and the third metal layer136are substantially coplanar and/or the first metal layer132, the second metal layer134, and the third metal layer136have the same height. In other embodiments, the first metal layer132, the second metal layer134, and the third metal layer136may include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof and formed by an electro-chemical plating process, CVD, PVD or the like. In some embodiments, the first metal layer132, the second metal layer134, and the third metal layer136are formed before the dielectric layer130is formed. The first metal layer132, the second metal layer134, and the third metal layer136may be formed by forming a metal material on the dielectric layer116b, and the patterning the metal material by a photolithography process and an etching process such as anisotropic process. In other some embodiments, the first metal layer132, the second metal layer134, and the third metal layer136are formed after the dielectric layer130is formed. The first metal layer132, the second metal layer134, and the third metal layer136may be formed by the following processes. The dielectric layer130is patterned by a photolithography process and an etching process such as anisotropic process to form metal trenches in the dielectric layer130. A metal material is then formed on the dielectric layer130and filled in the metal trenches. The metal material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the metal material over the dielectric layer130.

InFIGS. 1, 2B, and 2C, the contacts118are formed in the dielectric layer116(i.e. dielectric layer116a) between adjacent two gate structures118. Specifically, the contacts118may include two first contacts117and a second contact119. As shown inFIG. 1, one of the first contacts117is disposed between the first gate structure108aand the second gate structure108b, and across the semiconductor fins104. Another of the first contacts117is disposed between the third gate structure108cand the fourth gate structure108d, and across the semiconductor fins104. The second contact119is disposed between the second gate structure108band the third gate structure108c, and across the semiconductor fins104. As shown inFIG. 2B, the contacts118are disposed over the S/D structures106and physically and electrically coupled to the S/D structures106. In some embodiments, the contacts118includes a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. The contacts118may be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of the contacts118may include the following steps. The dielectric layer116ais patterned to form contact trenches (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is formed on the dielectric layer116aand filled in the contact trenches. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over the dielectric layer116a. Therefore, in some embodiments, the contacts118(including the first contacts117and the second contact119) may be substantially at a same level.

From the top view ofFIG. 1, each of the first contacts117is a rectangular contact having a long side LS1and a short side SS1. The long side LS1extends from the second metal layer134and across the active region AA. In some embodiments, a ratio of the long side LS1to the short side SS1is greater than 2. In the cross-sectional view ofFIG. 2B, each of the first contacts117is a slot shape or a trapezoidal shape. That is, a top area of each of the first contacts117is greater than a bottom area of each of the first contacts117. Similarly, the second contacts119is also a rectangular contact having a long side LS2and a short side SS2. The long side LS1extends from the third metal layer136and across the active region AA. In some embodiments, a ration of the long side LS2to the short side SS2is greater than 2. The second contacts119may be a slot shape or a trapezoidal shape. That is, a top area of each of the second contacts119is greater than a bottom area of the second contacts119.

InFIG. 2B, the contacts118are physically and electrically connected to the S/D structures106. In addition, a plurality of silicide layers (not shown) may be formed respectively between the contacts118and the S/D structures106to reduce a resistance between the contacts118and the S/D structures106. The silicide layer may include TiSi2, NiSi, PtSi, CoSi2, or combination thereof.

InFIGS. 1 and 2B, the source vias120and the drain via122are formed in the dielectric layer116b. In some embodiments, the source vias120and the drain via122are formed at two sides of the active region AA. In detail, the source vias120and the rain via122are formed different sides of the active region AA, but the disclosure is not limited thereto. The source vias120are disposed between and electrically connected the second metal layer134and the first contacts117respectively. The drain via122is disposed between and electrically connected the third metal layer136and the second contact119. In some embodiments, each of the source vias120and the drain via122may include a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. The source vias120and the drain via122may be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of the source vias120and drain via122may include the following steps. The dielectric layer116bis patterned to form via openings (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is filled in the via openings and on the dielectric layer116b. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over the dielectric layer116b. Therefore, in some embodiments, the source vias120and the drain via122may be substantially at a same level.

InFIGS. 1, 2A, and 2C, the gate vias124are formed in the dielectric layers116band116a. The gate vias124are respectively disposed between the gate structures108and the first metal layer132. In detail, as shown inFIG. 1, the gate vias124may include a first gate via126and a second gate via128. The gate structures108may include a first gate structure108a, a second gate structure108b, a third gate structure108c, and a fourth gate structure108d. The first gate via126is disposed between and electrically connected the second gate structure108band the first metal layer132, while the second gate via128is disposed between and electrically connected the third gate structure108cand the first metal layer132. Although only two gate vias124are illustrated inFIG. 1, the number of the gate vias124is not limited thereto. In general, the gate vias124are disposed between the gate structures108and the first metal layer132, which means the number of the gate vias124is able be adjusted by the number of the gate structures108.

In some embodiments, the first gate via126has a longitudinal axis LA1and a horizontal axis HA1perpendicular to each other. The longitudinal axis LA1extends along the first direction D1and is across the first metal layer132. A length of the longitudinal axis LA1of the first gate via126is greater than a width W1of the first metal layer132. A length of the horizontal axis HA1is less than or equal to a width W2of the second gate structure108b. Namely, the horizontal axis HA1is within a range of the second gate structure108b. Similarly, the second gate via128has a longitudinal axis LA2and a horizontal axis HA2perpendicular to each other. The longitudinal axis LA2extends along the first direction D1and is across the first metal layer132. A length of the longitudinal axis LA2of the second gate via128is greater than a width W1of the first metal layer132. A length of the horizontal axis HA2is less than or equal to a width W3of the third gate structure108c. Namely, the horizontal axis HA2is within a range of the third gate structure108c.

In an embodiment, a ratio of the length of the longitudinal axis LA1/LA2of the gate via126/128to the width W1of the first metal layer132is greater than 1.3. In another embodiment, the longitudinal axis LA1/LA2of the gate via126/128is included within a range of the active region AA. In some alternative embodiments, the length of the longitudinal axis LA1or the horizontal axis HA1of the first gate via126may the same as or different from the length of the longitudinal axis LA2or the horizontal axis HA2of the second gate via128.

InFIG. 1andFIG. 2A, the length of the longitudinal axis LA1/LA2of the gate via126/128is greater than the width W1of the first metal layer132. In the case, a contact area between the gate via126/128and the gate structure108b/108cincreases, so as to decrease a gate resistance between the gate via126/128and the gate structure108b/108c. Therefore, a RC delay of the semiconductor device10is improved, thereby enhancing a performance of the semiconductor device10and achieving high speed circuit applications. The layout illustrated inFIG. 1to reduce the gate resistance is suitable for driver circuit, high frequency analog circuit, and SerDes (Serializer/Deserialize) circuit speed improvement. In an embodiment, the semiconductor device10may be a high speed or high driver current transistor. In another embodiment, the semiconductor device10may be used in SerDes circuit.

In some embodiments, the gate vias124includes a liner, such as a diffusion bather layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. The gate vias124may be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of the gate vias124may include the following steps. The dielectric layers116band116aare patterned to form via trenches (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is formed to fill in the via trenches and on the dielectric layer116b. The conductive material is planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over the dielectric layer116b. Therefore, in some embodiments, the gate vias124(including the first gate via126and the second gate via128) may be substantially at a same level.

It should be noted that the first gate structure108a, the second gate structure108b, the third gate structure108c, and the fourth gate structure108dare electrically connected together by the gate vias124and other gate vias (not shown) over the first gate structure108aand the fourth gate structure108d. That is, the first gate structure108a, the second gate structure108b, the third gate structure108c, and the fourth gate structure108dshare the same gate line, e.g., the first metal layer132. In the case, the first metal layer132is referred to as a common gate. In some embodiments, the first gate structure108a, the second gate structure108b, the third gate structure108c, and the fourth gate structure108dare connected in parallel. The source vias120are electrically connected to each other by the second metal layer134. That is, the source vias120share a same source line, e.g., the second metal layer134. In the case, the second metal layer134is referred to as a common source. The drain via122may include a plurality of drain vias electrically connected to each other by the third metal layer136. That is, the drain vias share a same drain line, e.g., the third metal layer136. In the case, the third metal layer136is referred to as a common drain.

FIG. 3is a top view of a semiconductor device in accordance with a second embodiment.

Referring toFIG. 3, a semiconductor device20of the second embodiment is similar to the semiconductor device10of the first embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that a length of the first metal layer232of the semiconductor device20is less than a length of the first metal layer132of the semiconductor device10. That is, the first metal layer132illustrated inFIG. 1is across the four gate structures108(e.g.108a,108b,108cand108d), while the first metal layer232illustrated inFIG. 3is only across the two gate structures108(e.g., the first and second gate structures108band108c). In addition, a length of the third metal layer236of the semiconductor device20is less than a length of the third metal layer136of the semiconductor device10(shown inFIG. 1). As shown inFIG. 3, the third metal layer236is only across the two gate structures108(e.g., the first and second gate structures108band108c).

FIG. 4Ais a top view of a semiconductor device in accordance with a third embodiment.FIG. 4Bis a cross-sectional view of line D-D′ ofFIG. 4A.

Referring toFIG. 4AandFIG. 4B, a semiconductor device30of the third embodiment is similar to the semiconductor device10of the first embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the semiconductor device30includes a second metal layers334, a third metal layer336, a fourth metal layer344, two first vias335, a fifth metal layer346, a second via337and a dielectric layer333.

In detail, the second metal layer134(shown inFIG. 1) is replaced by the second metal layers334. The second metal layers334includes two second metal layers334aand334bseparated from each other. The second metal layers334ais disposed between adjacent first gate structure108aand second gate structure108b, and separated from the first metal layer132. The second metal layers334bis disposed between adjacent the third gate structure108cand the fourth gate structure108d, and separated from the first metal layer132. In addition, the third metal layer136(shown inFIG. 1) is replaced by the third metal layer336. The third metal layer336is disposed between adjacent second gate structure108band third gate structure108c, and separated from the first metal layer132.

The dielectric layer333is formed on the dielectric layer130, the first metal layer132, the second metal layers334aand334b, and the third metal layer336. The dielectric layer333may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. In some embodiments, the dielectric layer333and130may have a same material or different materials. The dielectric layer333may include a single layer dielectric material or a multi-layer dielectric material. In some embodiments, the dielectric layer333includes a dielectric layer333aon the dielectric layer130and a dielectric layer333bon the dielectric layer333a.

The fourth metal layer344and the fifth metal layer346are located in the dielectric layer333b. The fourth metal layer344and the fifth metal layer346are disposed over the second metal layers334aand334band the third metal layer336. Further, the fourth metal layer344and the fifth metal layer346are across the gate structures108(i.e.108a,108b,108cand108d). The fourth metal layer344and the fifth metal layer346may include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof and formed by an electro-chemical plating process, CVD, PVD or the like. The formation of the fourth metal layer344and the fifth metal layer346may be similar to the first metal layer132, the second metal layer134, and the third metal layer136. The fourth metal layer344and the fifth metal layer346may be formed before or after the dielectric layer333bis formed.

The first vias335aand335band the second via337are formed in the dielectric layer333a. One of the first via335ais disposed between and electrically connected the fourth metal layer344and the second metal layer334a, and another one of the first via335bis disposed between and electrically connected the fourth metal layer344and the second metal layer334b. The second via337is disposed between and electrically connected the fifth metal layer346and the third metal layer336. In some embodiments, each of the first vias335aand335band the second via337includes a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. The first vias335aand335band the second via337may be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of the first vias335aand335band the second via337may include the following steps. The dielectric layer333ais patterned to form via openings (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is formed on the dielectric layer333aand filled in the via openings. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over the dielectric layer333a.

In some embodiments, the first vias335aand335band the second via337may be formed first, and then the fourth metal layer344and the fifth metal layer346are formed. In other some embodiments, the first vias335aand335b, the second via337, the fourth metal layer344and the fifth metal layer346may be formed at same process such as a dual damascene process. In other words, the dielectric layer333is patterned to form metal trenches (not shown) in the dielectric layer333band via openings (not shown) are formed in the dielectric layer333a. Thereafter, a conductive material is formed on the dielectric layer333band filled in the metal trenches and the via openings. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over the dielectric layer333b.

In some embodiments, the first metal layer132, the second metal layers334aand334b, and the third metal layer336are referred to as metal one (M1). That is, the first metal layer132, the second metal layers334aand334b, and the third metal layer336are substantially at the same level. In some alternative embodiments, the fourth metal layer344and the fifth metal layer346are referred to as metal two (M2). That is, the fourth metal layer344and the fifth metal layer346are substantially at the same level. The M2is higher than the M1. Further, as shown inFIG. 4B, the first metal layer132, fourth metal layer344, and the fifth metal layer346are disposed in a staggered arrangement. In the case, a capacitance between the M1and M2decreases, so that a RC delay of the semiconductor device30is improved, thereby enhancing a performance of the semiconductor device30.

FIG. 5is a top view of a semiconductor device in accordance with a fourth embodiment.

Referring toFIG. 5, a semiconductor device40of the fourth embodiment is similar to the semiconductor device30of the third embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the semiconductor device40includes fourth metal layers444, a fifth metal layer446, a sixth metal layer448, and a third via428.

In detail, fourth metal layer344and the fifth metal layer346are replaced by fourth metal layers444and the fifth metal layer446, respectively. The fourth metal layers444includes two fourth metal layers444aand444bseparated from each other. The fourth metal layers444ais disposed over the second metal layers334a, and electrically connected to the second metal layers334aby the first via335a. The fourth metal layers444bis disposed over the second metal layers334b, and electrically connected to the second metal layers334bby the first via335b. The fifth metal layer446is disposed over the third metal layer336, and electrically connected to the third metal layer336by the second via337.

In addition, the sixth metal layer448is disposed over the first metal layer232. As shown inFIG. 5, the sixth metal layer448is disposed between adjacent second gate structure108band third gate structure108c, and extends along the first direction D1. The third via428is disposed between and electrically connected the sixth metal layer448and the first metal layer232.

In some embodiments, the first metal layer232, the second metal layers334aand334b, and the third metal layer336are referred to as metal one (M1). That is, the first metal layer232, the second metal layers334aand334b, and the third metal layer336are substantially at the same level. In some alternative embodiments, the fourth metal layers444aand444b, the fifth metal layer446, and the sixth metal layer448are referred to as metal two (M2). That is, the fourth metal layers444aand444b, the fifth metal layer446, and the sixth metal layer448are substantially at the same level. The first vias335aand335b, the second via337and the third via428are disposed between the M2and the M1.

FIG. 6Ais a top view of a semiconductor device in accordance with a fifth embodiment.FIG. 6Bis a cross-sectional view of line E-E′ ofFIG. 6A.

Referring toFIG. 6AandFIG. 6B, a semiconductor device50of the fifth embodiment is similar to the semiconductor device10of the first embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the semiconductor device50includes two source vias520, a drain via522, a plurality of gate vias524, and two first metal layers532.

In detail, the source vias520is disposed over the first contacts117, and the drain via522is disposed over the second contacts119. One of the source vias520is disposed at one side S1of the second gate structure108b, and the drain via522is disposed at another side S2of the second gate structure108b. The one side S1is opposite to the another side S1. In some embodiments, a source is disposed on the semiconductor fins104at the one side S1of the gate structure108band the source vias520is disposed over the source. In some alternative embodiments, a drain is disposed on the semiconductor fins104at the another side S2of the gate structure108band the drain via522is disposed over the drain. On the other hand, another one of the source vias520and the drain via522are disposed different sides of the second gate structure108c.

The first metal layer132(FIG. 1) is replaced by two first metal layers532. Only two first metal layers532are illustrated inFIG. 6A, but the disclosure is not limited thereto. The first metal layers532extends along the second direction D2and across the gate structures108(e.g.,108a,108b,108cand108d). The first metal layers532(e.g., MD are electrically and physically coupled to each other by vias544and metal layer542(e.g., M2). In some embodiments, the first metal layers532are connected in parallel. Some of the gate vias524are disposed over the gate structures108within the active region AA. Specifically, the gate vias524includes one group of two gate vias526and another group of two gate vias528. The one group of two gate vias526is disposed between and electrically connected the second gate structure108band the first metal layers532. The another group of two gate vias528is disposed between and electrically connected the third gate structure108cand the first metal layers532. Only two gate vias526/528directly over the single gate structure108b/108care illustrated inFIG. 6A, but the disclosure is not limited thereto. In some alternative embodiment, the plurality of gate vias524include at least two gate vias over the corresponding gate structure, such as two, three, four, five, six, or more gate vias.

In some embodiments, as shown inFIG. 6A, a horizontal cross-sectional area of one of the gate vias524is represented as A1, a horizontal cross-sectional area A2of one of the source vias520or the drain via522is represented as A2, wherein A2is greater than A1. In some alternative embodiments, a ratio of the horizontal cross-sectional area of one of the source vias520or the drain via522to the horizontal cross-sectional area of one of the gate vias524is greater than 1.4 (i.e., A2/A1>1.4). In other embodiments, the semiconductor device50may be used in static random access memory (SRAM) macro word-line driver circuit.

FIG. 7Ais a top view of a semiconductor device in accordance with a sixth embodiment.FIG. 7Bis a cross-sectional view of line F-F′ ofFIG. 7A.

Referring toFIG. 7AandFIG. 7B, a semiconductor device60of the sixth embodiment is similar to the semiconductor device50of the fifth embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the two first metal layers532illustrated inFIG. 6Abecome one wider first metal layer632illustrated inFIG. 7A. In addition, the four gate vias524(i.e., gate vias526and528) are all disposed between and electrically connected the first metal layer632and the gate structure108b/108c.

FIG. 8Ais a top view of a semiconductor device in accordance with a seventh embodiment.FIG. 8Bis a cross-sectional view of line G-G′ ofFIG. 8A.

Referring toFIG. 8AandFIG. 8B, a semiconductor device70of the seventh embodiment is similar to the semiconductor device60of the sixth embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the semiconductor device70includes a second metal layers734, a third metal layer736, a fourth metal layer744, two first vias735, a fifth metal layer746, and a second via737.

In detail, the second metal layers734are similar to the second metal layers334(shown inFIG. 4A). The second metal layers734includes two second metal layers734aand734bseparated from each other. The second metal layers734ais disposed between adjacent the first gate structure108aand the second gate structure108b, and separated from the first metal layer632. The second metal layers734bis disposed between adjacent the third gate structure108cand the fourth gate structure108d, and separated from the first metal layer632. The fourth metal layer744is disposed over the second metal layers734aand734band is across the gate structures108. One first via735ais disposed between and electrically connected the fourth metal layer744and the second metal layer734a, and another first via735bis disposed between and electrically connected the fourth metal layer744and the second metal layer734b.

In addition, the third metal layers736are similar to the third metal layers336(shown inFIG. 4A). The third metal layer736is disposed between adjacent the second gate structure108band the third gate structure108c, and separated from the first metal layer632. The fifth metal layer746is disposed over the third metal layer736and across the gate structures108. The second via737is disposed between and electrically connected the fifth metal layer746and the third metal layer736.

In some embodiments, the first metal layer632, the second metal layers734aand734b, and the third metal layer736are formed in dielectric layer130and referred to as metal one (M1). That is, the first metal layer632, the second metal layers734aand734b, and the third metal layer736are substantially at the same level. In some alternative embodiments, the fourth metal layer744and the fifth metal layer746are formed in the dielectric layer333band referred to as metal two (M2). That is, the fourth metal layer744and the fifth metal layer746are substantially at the same level. The M2is higher than the M1. The first vias735aand735b, and the second via737is disposed between and electrically connected the fourth metal layer744and the second metal layer734bare formed in the dielectric layer333aand electrically connected the M1and the M2. Further, as shown inFIG. 4B, the first metal layer632, fourth metal layer744, and the fifth metal layer746are disposed in a staggered arrangement. In the case, a capacitance between the M1and M2decreases, so that a RC delay of the semiconductor device70is improved, thereby enhancing a performance of the semiconductor device70.

FIG. 9Ais a top view of a semiconductor device in accordance with an eighth embodiment.FIG. 9Bis a cross-sectional view of line H-H′ ofFIG. 9A.

Referring toFIG. 9AandFIG. 9B, a semiconductor device70of the seventh embodiment is similar to the semiconductor device10of the first embodiment. Since the materials and arrangements of the similar components are described in the above embodiments. Thus, details thereof are omitted here. A difference therebetween lies in that the semiconductor device70includes two gate vias824, two source vias820, a drain via822, two first metal layer832, a second metal layer834, a third metal layer836, two first vias835, a second via837, two fourth metal layers844, a fifth metal layer846, two third vias845, a sixth metal layer854, a fourth via847, and a seventh metal layer856.

In detail, the first metal layers832extend along the second direction D2and are across the gate structures108(108a,108b,108cand108d). Although only two first metal layers832are illustrated inFIG. 9A, the number of the first metal layers832is not limited thereto. As shown inFIG. 9A, the two first metal layers832are disposed on two sides of the active region AA respectively. The gate vias824are disposed over the gate structures108respectively and extend along the first direction D1.

One of the gate vias826is disposed between the second gate structures108band the first metal layers832, and another of the gate vias824is disposed between the third gate structures108cand the first metal layers832. The gate via826has a longitudinal axis LA3and a horizontal axis HA3perpendicular to each other. The longitudinal axis LA3extends along the first direction D1. The longitudinal axis LA3of the gate via826is across the active region AA. In some embodiments, the longitudinal axis LA3of the gate via826may extend between or extend beyond the two first metal layers832. A length of the horizontal axis HA3is less than or equal to the width W2of the second gate structure108b. Namely, the horizontal axis HA3is within a range of the second gate structure108b.

Similarly, the gate via828has a longitudinal axis LA4and a horizontal axis HA4perpendicular to each other. The longitudinal axis LA4extends along the first direction D1. The longitudinal axis LA4of the gate via828is across the active region AA. In some embodiments, the longitudinal axis LA4of the gate via828may extend between or extend beyond the two first metal layers832. A length of the horizontal axis HA4is less than or equal to a width W3of the third gate structure108c. Namely, the horizontal axis HA4is within a range of the third gate structure108c.

It should be noted that the length of the longitudinal axis LA3/LA4of the gate via826/828extend beyond the active region AA. In the case, a contact area between the gate via826/828and the gate structure108b/108cincreases, so as to decrease a gate resistance between the gate via826/828and the gate structure108b/108c. Therefore, a RC delay of the semiconductor device80is improved, thereby enhancing a performance of the semiconductor device80and achieving high speed circuit applications. The layout illustrated inFIG. 9Ato reduce the gate resistance is suitable for driver circuit, high frequency analog circuit, and SerDes circuit speed improvement. In an embodiment, the semiconductor device80may be a high speed or high driver current transistor. In another embodiment, the semiconductor device80may be used in SerDes circuit, SRAM macro word-line driver circuit, or a combination thereof.

In addition, as shown inFIG. 9A, the two second metal layers834are disposed between the two first metal layers832and separated from each other. Specifically, one of the second metal layers834is disposed between adjacent the first gate structure108aand the second gate structure108b, and another of the second metal layers834is disposed between adjacent the third gate structure108cand the fourth gate structure108d. The two fourth metal layers844are disposed over the second metal layers834respectively. The fourth metal layers844extend from the active region AA to cover one of the two first metal layers832. The first via835is disposed between and electrically connected the fourth metal layer844and the second metal layer834.

In some embodiments, the second metal layers834are directly over the active region AA and the fourth metal layers844, the first via835, the second metal layers834, the source vias820, the first contact117, and the S/D structures (i.e., a source) overlap to each other. In the case, the conductive path from the source through the first contact117, the source vias820, the second metal layers834, and the first via835to the fourth metal layers844decreases, thereby reducing the source resistance.

On the other hand, the third metal layers836is disposed between the two first metal layers832and separated from each other. The third metal layers836is disposed between adjacent the second gate structure108band the third gate structure108c. The fifth metal layer846is disposed over the third metal layers836. The fifth metal layer846extends from the active region AA to cover another one of the two first metal layers832. The second via837is disposed between and electrically connected the fifth metal layer846and the third metal layers836.

In some alternative embodiments, the third metal layer836is directly over the active region AA and the fifth metal layer846, the second via837, the third metal layers836, the drain via822, the second contact119, and the S/D structures (i.e., a drain) overlap to each other. In the case, the conductive path from the drain through the second contact119, the drain via822, the third metal layers836, and the second via837to the fifth metal layer846decreases, thereby reducing the drain resistance.

In an embodiment, the first metal layers832, the second metal layer834, and the third metal layer836are referred to as metal one (M1). That is, the first metal layers832, the second metal layer834, and the third metal layer836are substantially at a same level. In another embodiment, the fourth metal layers844and the fifth metal layer846are referred to as metal two (M2). That is, the fourth metal layers844and the fifth metal layer846are substantially at a same level.

Further, the sixth metal layer854and the seventh metal layer856are disposed in a dielectric layer853. In detail, the sixth metal layer854is disposed over one of the first metal layers832and extends along the second direction D2. The two third vias845are respectively disposed between and electrically connected the one of the first metal layers832and the sixth metal layer854. In some embodiments, the sixth metal layer854is referred to as a common source, so that the source vias820are connected in parallel. In an embodiment, the sixth metal layer854is parallel to the first metal layers832and perpendicular to the fourth metal layers844.

The seventh metal layer856is disposed over another of the first metal layers832and extends along the second direction D2. The fourth via847is disposed between and electrically connected the another of the first metal layers832and the seventh metal layer856. In some embodiments, the seventh metal layer856is referred to as a common drain, so that the drain via822including a plurality of drain vias are connected in parallel. In another embodiment, the seventh metal layer856is parallel to the first metal layers832and perpendicular to the fifth metal layers846.

In other embodiments, the sixth metal layer854and the seventh metal layer856are referred to as metal three (M3). That is, the sixth metal layer854and the seventh metal layer856are substantially at a same level. In alternative embodiments, the M3is higher than the M2, and the M2is higher than the M1.

In accordance with some embodiments of the disclosure, a semiconductor device includes a substrate, a gate structure, a first metal layer, and a gate via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins and extends along a first direction. The first metal layer extends along a second direction and is disposed over the gate structure. The gate via is disposed between the gate structure and the first metal layer. The gate via has a longitudinal axis extending along the first direction and across the first metal layer. A length of the longitudinal axis of the gate via is greater than a width of the first metal layer.

In accordance with alternative embodiments of the disclosure, a semiconductor device includes a substrate, a gate structure, a source, a drain, at least two gate vias, a source via, a drain via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins. The source is disposed on the at least three semiconductor fins at one side of the gate structure. The drain is disposed on the at least three semiconductor fins at another side of the gate structure. The at least two gate vias are disposed over the gate structure within the active region. The source via is disposed over the source. The drain via is disposed over the drain. A horizontal cross-sectional area of the source via or the drain via is greater than a horizontal cross-sectional area of one of the at least two gate vias.

In accordance with some embodiments of the disclosure, a semiconductor device includes a substrate, a gate structure, at least two first metal layers, and a gate via. The substrate has at least three semiconductor fins to define an active region. The gate structure is across the at least three semiconductor fins and extends along a first direction. The at least two first metal layers extend along a second direction and are disposed on two sides of the active region respectively. The gate via is disposed between the gate structure and the at least two first metal layers. The gate via has a longitudinal axis extending along the first direction, and the longitudinal axis of the gate via is across the active region.