Daisy chain connection for testing continuity in a semiconductor die

An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

TECHNICAL FIELD

The present disclosure relates generally to continuity tests in an electronic device. More specifically, the present disclosure relates to a daisy chain connection for testing continuity in a die.

BACKGROUND

Electronic devices (cellular telephones, wireless modems, computers, digital music players, Global Positioning System units, Personal Digital Assistants, gaming devices, etc.) have become a part of everyday life. Small computing devices are now placed in everything from automobiles to housing locks. The complexity of electronic devices has increased dramatically in the last few years. For example, many electronic devices have one or more processors that help control the device, as well as a number of digital circuits to support the processor and other parts of the device.

As electronic and wireless devices become more advanced, the complexity of circuitry has increased. Further, the amount of space available for circuitry has decreased. Attempts to combine or consolidate components on a single circuit within a wireless device may result in a larger footprint on the circuit, and may include additional considerations for functionality.

Furthermore, testing circuit functionality in electronic and wireless devices has also become more complex. With more circuitry being contained within a smaller area, testing procedures have become more extensive. Benefits may be realized by improvements to electronic devices that allow complex circuitry to be tested in convenient ways.

SUMMARY

An integrated circuit product package configured for continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively couple the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

The package substrate and the semiconductor die may be coupled together using die interconnects. The daisy chain connection may also include more than two of the die interconnects. The package substrate may also include substrate interconnects on a different surface of the package substrate than the die interconnects. The daisy chain connection may further include at least two of the substrate interconnects.

A top printed circuit board (PCB) may be coupled to the integrated circuit product package. The daisy chain connection may further include components on the top PCB. The top PCB may also be coupled to the semiconductor die using the internal routing connections. The top PCB may also be coupled to the package substrate using test probes. The test probes may be spring probes.

The integrated circuit product package may further include a second semiconductor die coupled to the package substrate. The second semiconductor die may include I/O pins and switches. The daisy chain connection may further include circuitry fabricated on the second semiconductor die, I/O pins on the second semiconductor die and at least one switch on the second semiconductor die. The second semiconductor die may be coupled to the semiconductor die using internal routing connections internal to the integrated circuit product package.

The integrated circuit product package may be coupled to a loadboard using test probes. The test probes may be spring probes. The test probes may be coupled together using a loadboard contact. The daisy chain connection may further include the test probes and the loadboard contact. The test probes may also be coupled together using multiple loadboard contacts. The daisy chain connection may further include the test probes and the multiple loadboard contacts. The multiple loadboard contacts may be connected using internal routing on the loadboard.

The daisy chain connection may further include each of the I/O pins on the semiconductor die. Additionally, the switches may selectively couple the I/O pins to facilitate multiple daisy chain connections. Each daisy chain connection may include circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. Each adjacent I/O pin may be part of a different daisy chain connection.

The switches may selectively couple the I/O pins to facilitate at least two daisy chain connections. Each of the two daisy chain connections may include circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. Each adjacent I/O pin may be part of a different daisy chain connection. Further, the I/O pins may be coupled together unto groups of I/O pins using one or more transistors on the semiconductor die. Each of the groups of I/O pins may include two or more I/O pins and switches for selectively shorting or disconnecting the two or more of the I/O pins within each group of I/O pins.

A method for generating an integrated circuit product package configured for continuity testing is also described. The method includes obtaining a package substrate. The package substrate includes internal routing connections. The method also includes obtaining a semiconductor die. The semiconductor die includes I/O pins and switches. The method also includes coupling the package substrate to the semiconductor die using die interconnects. The method also includes selectively coupling the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the die interconnects, more than two of the I/O pins and at least one switch.

An apparatus for generating an integrated circuit product package configured for continuity testing is also described. The apparatus includes a package substrate. The package substrate includes internal routing connections. The apparatus also includes a semiconductor die coupled to the package substrate. The semiconductor die includes I/O pins. The apparatus also includes means for selectively coupling the input/output pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections and more than two of the I/O pins.

DETAILED DESCRIPTION

FIG. 1illustrates one configuration of a system for testing continuity of circuitry fabricated on a semiconductor die. The system includes an integrated circuit product package102, which may include a die104and a package substrate106. The integrated circuit product package102may be coupled to a loadboard108for testing continuity of the die circuitry that is fabricated on the die104. The integrated circuit product package102may be configured to be used in an electronic device, which may be a wireless device.

Circuitry may be fabricated on the die104. Further, the die104may include input/output (I/O) pins110coupled to circuitry on the die104. The system shown inFIG. 1may be used for testing continuity of the die circuitry and other connections on the die104. For example, the system may be implemented in an automatic test equipment (ATE) environment, which is part of the production process for semiconductor devices. The system may be utilized for testing the continuity of one or more devices under test (DUTs). A device under test (DUT) may include a die104. By connecting I/O pins110of a die104to a test channel, the continuity of circuitry on the die104associated with each of the I/O pins110may be tested. Moreover, as used herein, die circuitry may refer to any circuitry implemented on a die104, including switches112, I/O pins110and other circuitry described herein.

The I/O pins110may be coupled together by one or more switches112. In some configurations, switches112may be selectively used to connect adjacent I/O pins110, for reasons that will be explained below. The switches112may be configured to connect two or more I/O pins110or switched off for disconnecting I/O pins110. In some configurations, the switches112may be analog switches. Further, the switches112may include one or more transistors. In one configuration, a switch112containing a transistor may be controlled using a voltage control signal applied to a gate of the transistor. Using the voltage control, the switch112may be turned on or off to connect or disconnect one or more I/O pins110.

Each of the I/O pins110may be coupled to a corresponding die interconnect114. The die interconnects114may be used to connect the die104to the package substrate106. In general, each die interconnect114corresponds to a different I/O pin110. The die interconnects114may also provide an electrical connection between one or more components on the die104(e.g., die circuitry, switches112, I/O pins110) and one or more internal routing connections116in the package substrate106. The die interconnects114may be physically connected to a surface of the die104. Further, the die interconnects114may be made from a variety of materials. In one configuration, the die interconnects114may be solder balls or solder pads for connecting the die104and the package substrate106. Alternatively, the die interconnects114may be implemented using vias or other technologies for connecting and/or providing an electrical connection between the die104and the package substrate106. For example, the system may be implemented using flip chip assembly, wire bond or through silicon via (TSV) technology.

A first surface of the package substrate106may be connected to the die104by the die interconnects114. The package substrate106may be made from a variety of materials. Examples of materials or substrates that may be used for implementing the package substrate106may include a printed circuit board (PCB), ceramic substrates, extended wafer level packaging technologies or other suitable material for supplying internal routing connections116between different surfaces of the package substrate106. The package substrate106may also include multiple internal routing connections116coupled to one or more I/O pins110via the die interconnects114.

The internal routing connections116in the package substrate106may pass between a first surface of the package substrate106and a second surface of the package substrate106. An internal routing connection116may be an electrical channel for passing an electrical signal through the package substrate106. Each internal routing connection may be coupled to an I/O pin110via a corresponding die interconnect114. For example, a first internal routing connection116may be coupled to a first die interconnect114and corresponding I/O pin110while a second internal routing connection116may be coupled to a second die interconnect114and different corresponding I/O pin110.

The package substrate106may include substrate interconnects118on a second surface of the package substrate106. The substrate interconnects118may be coupled to one or more die interconnects114by internal routing connections116passing between the first and second surface of the package substrate106. Each of the substrate interconnects118may correspond to a different internal routing connection116. The substrate interconnects118may use similar or different materials as the die interconnects114on the first surface of the package substrate106. In one configuration, the substrate interconnects118and die interconnects114may be solder balls or other material for connecting the package substrate106to the die104or loadboard108. Further, the solder balls used as the substrate interconnects118may be larger than the solder balls used as the die interconnects114. In one example, the solder balls used as substrate interconnects118may have a 0.4-0.5 mm pitch.

A loadboard108may be coupled to the integrated circuit product package102. The loadboard108may be used for testing continuity of circuitry on the die104. The loadboard108may include loadboard contacts122. The loadboard108may also include internal routing for coupling one or more loadboard contacts122to other circuitry on the loadboard108. The loadboard108may be made from a variety of materials. In one configuration, the loadboard108may be a printed circuit board (PCB).

The loadboard108may be coupled to the integrated circuit product package102via multiple test probes120. Each of the test probes120may be housed within a test socket on the loadboard108. When the integrated circuit product package102comes into contact with the test probes120, each of the substrate interconnects118may form an electrical connection with the test probes120on the loadboard108. The test probes120may be used to couple each of the substrate interconnects118to one or more loadboard contacts122. Connecting the integrated circuit product package102to the loadboard108in an automatic test equipment (ATE) environment may enable testing the continuity of circuitry on the die104. In some configurations, the test probes120may include spring probes. Each spring probe may be housed within one of the test sockets on the loadboard108. When the integrated circuit product package102is placed in contact with the spring probes, the spring probes may compress and form an electrical connection between the substrate interconnects118and the loadboard contacts122.

Each of the test probes120may be coupled to the loadboard108by loadboard contacts122. Some of the test probes120may be coupled together by a single loadboard contact122on the surface of the loadboard108. One or more loadboard contacts122may be used to couple two adjacent test probes120on the surface of the loadboard108. Alternatively, one or more loadboard contacts122may also be used to couple non-adjacent test probes120together using connections or internal traces on the loadboard108. Further, each loadboard contact122may be coupled or electrically connected to any other component on the loadboard108through internal traces inside the loadboard108. Thus, multiple loadboard contacts122need not necessarily be adjacent to each other, as shown in the example ofFIG. 1. Where a loadboard contact122connects two test probes120, the two test probes120and loadboard contact122may create a single electrical path for passing a signal through each of the test probes120. In one example, a loadboard contact122may be shared by a first test probe120and a second test probe120. The first test probe120may be electrically connected to the second test probe120by the loadboard contact122shared by the first test probe120and the second test probe120.

The integrated circuit product package102may implement one or more daisy chains. A daisy chain may include multiple components coupled together to form a continuous chain of components. An example of a daisy chain may include internal routing connections116, I/O pins110, switches112and circuitry on the die104. Each of the components that make up the daisy chain may be coupled together to form a single electrical path of components. A test channel may be generated using a daisy chain by passing an electrical signal from a first end of the daisy chain to a second end of the daisy chain. Therefore, each device under test (DUT) included within a daisy chain may be tested for continuity using a single test channel.

In one configuration, a first end of a daisy chain may begin at a test channel input124coupled to a first loadboard contact122. The daisy chain may continue sequentially through a first test probe120, a first substrate interconnect118, a first internal routing connection116, a first die interconnect114and into the die104through a first I/O pin110. The same daisy chain may continue through a switch112connecting the first I/O pin110and an adjacent second I/O pin110. Passing through the switch112, the daisy chain may continue through the second I/O pin110, a second die interconnect114, a second internal routing connection116, a second substrate interconnect118, a second test probe120and a second loadboard contact122coupling the second test probe120to a third test probe120. The daisy chain may continue through additional components on the integrated circuit product package102and loadboard108. The daisy chain may continue to pass through each of the loadboard contacts122, test probes120, substrate interconnects118, internal routing channels116, die interconnects114, I/O pins110and switches112on an integrated circuit product package102. A second end of the daisy chain may pass through a loadboard contact122into a test channel output126in the loadboard108. An electrical signal applied to the test channel input124may be configured to pass through each component on the daisy chain and be output at the test channel output126.

By configuring the switches112and loadboard contacts122to couple each of the I/O pins110together into a single electrical path, a daisy chain may be generated that extends through each of the I/O pins110on the die104. In some configurations, each of the I/O pins110may be included in one continuous daisy chain. A test channel may be formed using the daisy chain by connecting a first end of the daisy chain to a test channel input124and a second end of the daisy chain to a test channel output126. The continuity of the circuitry on the daisy chain may be tested by applying an electrical signal to one end of the test channel and measuring a resistance, voltage, current or other measurement on the test channel as a signal passes through the daisy chain. The continuity of each of the components on the daisy chain, including the die104, may be determined through observation of the signal that passes through the test channel.

In some configurations, multiple daisy chains may be used for testing continuity of a die104. For example, multiple daisy chains may be formed for a device under test (DUT) for testing continuity of different portions of circuitry. By using multiple daisy chains, the location of any continuity fails may be precisely detected.

By implementing a daisy chain that passes through each I/O pin110on the die104, circuitry that may be used on the loadboard108for determining continuity of a die104may be reduced in complexity as a result of one or more daisy chains reducing the number of signals to be processed. For example, by using daisy chains to test the continuity of one or more devices under test (DUTs), the continuity of circuitry on the die104may be determined without the use of a multiplexer (MUX) on the loadboard108or with using a fewer number of MUXes on the loadboard108. Simplified test circuitry on the loadboard108may allow for additional DUTs to be placed into a loadboard108without increasing the test resources in the ATE environment as fewer connections and circuitry are needed to run tests.

FIG. 2is a flow diagram of a method200for generating an integrated circuit product package102for testing continuity of circuitry fabricated on a semiconductor die. The method200may be performed by an engineer, a technician or a computer. In one configuration, the method200may be performed by a fabrication machine.

A die104with die circuitry may be obtained202. The circuitry on the die104may be part of an integrated circuit. The die104may include a switch112, a first I/O pin110, a second I/O pin110and at least one additional I/O pin110. The first I/O pin110and the second I/O pin110may be coupled together by the switch112. The first I/O pin110and second I/O pin110may be adjacent pins. The die104may also include additional I/O pins110on the die104. Further, other configurations of I/O pins110and switches112may be used on the die104. The switch112may include one or more transistors. In one configuration, the switch112containing a transistor may be controlled using a voltage control signal applied to a gate of the transistor. Using the voltage control, the switch112may be turned on or off to connect or disconnect the first I/O pin110, second I/O pin110and at least one additional I/O pin110.

A package substrate106may be obtained204. The package substrate106may include internal routing connections116. The internal routing connections116may run between a first surface of the package substrate106and a second surface of the package substrate106. Each of the internal routing connections116may be coupled to different I/O pins110on the die104. For example, a first internal routing connection116may be coupled to a first I/O pin110and a second internal routing connection116may be coupled to a second I/O pin110. Internal routing connections116may also be used to couple one I/O pin110to another I/O pin110.

The package substrate106may be connected to a loadboard108. The loadboard108may include internal routing, loadboard contacts122, test probes120and substrate interconnects118. The test probes120may be connected to the loadboard108by loadboard contacts122. The test probes120may be connected to a second surface of the package substrate106by substrate interconnects118. Using the substrate interconnects118, test probes120and loadboard contacts122, the internal routing on the loadboard108may be coupled to the internal routing connections116on the package substrate106.

A daisy chain may be generated208using the die104and the package substrate106. The daisy chain may include the die circuitry, a switch112, a first I/O pin110, a second I/O pin110and at least one additional I/O pin110. Each of the components of the daisy chain may be coupled together to form a continuous chain of components. The daisy chain may include additional components coupled together to form a test channel, including additional I/O pins110, switches112, die interconnects114and internal routing connections116in various configurations. Components on the loadboard108may also be implemented in a daisy chain for testing continuity of the die104. For example, a daisy chain may include a test channel input124, loadboard contacts122, test probes120, substrate interconnects118, internal routing connections116on the package substrate106, die interconnects114, switches112, I/O pins110, die circuitry and a test channel output126. Various configurations of daisy chains may be implemented for testing continuity of circuitry on the die104. Some examples of daisy chain configurations that may be used are explained herein.

FIG. 3illustrates one configuration of a package on package (PoP) system for testing continuity of circuitry fabricated on a semiconductor die. The package on package (PoP) system may include an integrated circuit product package302, which may include a die304and a package substrate306. The integrated circuit product package302may be coupled to a loadboard308for testing continuity of the die circuitry that is fabricated on the die304. The integrated circuit product package302may be one configuration of the integrated circuit product package102described above in connection withFIG. 1. The integrated circuit product package302may also be coupled to a top printed circuit board (PCB)328stacked vertically on top of the product package302. Stacking the top PCB328on the integrated circuit product package302may provide additional connections to substrate contacts334during testing.

The integrated circuit product package302may include a die304and a package substrate306. The die304may include I/O pins310, switches312and other circuitry on the die304. Circuitry on the die304may be implemented in an integrated circuit. The package substrate306may include internal routing connections316. The die304and the package substrate306may be connected using die interconnects314. The die304, package substrate306, I/O pins310, switches312, die interconnects314and internal routing connections316may be similar to corresponding elements104,106,110,112,114and116described above in connection withFIG. 1.

The integrated circuit product package302may also be connected to a loadboard308. The loadboard308may include internal routing, including a test channel input324and a test channel output326used for testing continuity of a circuit. The loadboard308may include loadboard contacts322and sockets for housing test probes320. The package substrate306of the integrated circuit product package302may connect to the loadboard308using substrate interconnects318and test probes320. The loadboard308, substrate interconnects318, test probes320and loadboard contacts322may be similar to corresponding elements108,118,120and122described above in connection withFIG. 1.

The package on package (PoP) system may also include a top PCB328. The top PCB328may include top PCB contacts332on a surface of the top PCB328. The top PCB328may also include internal routing (not shown). The top PCB328may be made from a variety of materials.

The top PCB328may be coupled to the integrated circuit product package302via multiple top PCB test probes330. Each of the top PCB test probes330may be housed within a test socket on the top PCB328. A first end of each top PCB test probe330may be connected to a substrate contact334while a second end of each top PCB test probe330may be connected to a top PCB contact332. In some configurations, the top PCB test probes330may include spring probes. Each spring probe may be housed within one of the test sockets on the top PCB328. When the integrated circuit product package302is placed in contact with the spring probes, the spring probes may compress and form an electrical connection between the substrate contacts334and the top PCB contacts332. In addition, the substrate contacts334may be made from a variety of materials, such as solder balls, pads or other types of interconnects.

The top PCB test probes330may be connected to the top PCB328via top PCB contacts332. The top PCB test probes330may also be connected to the package substrate306via substrate contacts334. The top PCB contacts332and substrate contacts334may be made from a variety of materials. In one configuration, the substrate contacts334and top PCB contacts332are made from solder balls or solder pads for connecting the top PCB328and/or the package substrate306to the top PCB test probes330.

An I/O pin310on the die304may be coupled to a substrate contact334through an internal routing connection316on the package substrate306. The substrate contact334may be coupled to a top PCB test probe330. The top PCB test probe330may be coupled to a top PCB contact332. Therefore, an I/O pin310may be coupled to routing or circuitry contained on the top PCB328through an internal routing connection316, a substrate contact334, a top PCB test probe330and a top PCB contact332. Two or more top PCB test probes330may be coupled together by a single top PCB contact332. While the configuration shown inFIG. 3illustrates four top PCB test probes330in a package on package (PoP) system, more or fewer top PCB test probes330may be used in other configurations.

The package on package (PoP) system may be used to implement one or more daisy chains. A daisy chain may include components on the die304, package substrate306and loadboard308. Additionally, a daisy chain may include substrate contacts334, top PCB test probes330, top PCB contacts332, internal routing on the top PCB328and other circuitry on the top PCB328. Each of the components that make up the daisy chain may be coupled together to form a single electrical path of components. A test channel may be generated using a daisy chain by passing an electrical signal from a first end of the daisy chain to a second end of the daisy chain. Therefore, components on the die304and top PCB328included within a daisy chain may be tested for continuity using a single test channel.

In one configuration, a first end of a daisy chain may begin at a test channel input324coupled to a first loadboard contact322. The daisy chain may continue sequentially through a first test probe320, a first substrate interconnect318, a first internal routing connection316, a first die interconnect314and into the die304through a first I/O pin310. The same daisy chain may continue through a switch312connecting the first I/O pin310and an adjacent I/O pin310. Passing through the switch312, the daisy chain may continue through the second I/O pin310, a second die interconnect314, a second internal routing connection316and through a first substrate contact334into a first top PCB test probe330. The daisy chain may continue through a top PCB contact332coupling the first top PCB test probe330to a second top PCB test probe330. The daisy chain may also continue through the second top PCB test probe330, a third internal routing connection316and into a third I/O pin310on the die304. The daisy chain may continue through additional components on the package on package (PoP) system, including additional die circuitry, switches312, I/O pins310, die interconnects314, internal routing connections316, substrate interconnects318, test probes320, etc. After passing through additional components on the integrated circuit product package302, loadboard308and top PCB328, a second end of the daisy chain may pass through a loadboard contact322into a test channel output326on the loadboard308. An electrical signal applied to the test channel input324may be configured to pass through each component on the daisy chain and be output at the test channel output326.

By configuring the switches312, loadboard contacts322, substrate contacts334and top PCB contacts332to couple each of the I/O pins310and one or more top PCB components together into a single electrical path, a daisy chain may be generated that extends through each of the I/O pins310on the die as well as components on the top PCB328. In some configurations, each of the I/O pins310as well as components on the top PCB328may be included in one continuous daisy chain. A test channel may be formed using the daisy chain by connecting a first end of the daisy chain to a test channel input324and a second end of the daisy chain to a test channel output326. The continuity of the circuitry on the daisy chain may be tested by applying an electrical signal to one end of the test channel and measuring a voltage or current of the test channel as a signal passes through the daisy chain. The continuity of each of the components on the daisy chain, including the die304and top PCB328, may be determined through observation of the signal that passes through the test channel. Further, by implementing one or more daisy chains that pass through both the top PCB328and the integrated circuit product package302in a package on package (PoP) system, the continuity of an electrical path from the top PCB328to the die304and an electrical path from a substrate interconnect318to the die304may be tested at the same time, instead of using a two-step testing method where the continuities of these electrical paths are tested separately.

Moreover, similar to the system described above in connection withFIG. 1, multiple daisy chains may be used for testing continuity of circuitry on the package on package (PoP) system. For example, multiple daisy chains may be formed that tests circuitry on different portions of the circuitry on both the die304and the top PCB328. By using multiple daisy chains, the location of any continuity fails on the package on package (PoP) system may be precisely detected.

By implementing a top PCB328in a package on package (PoP) system, additional components may be stacked vertically using less real estate on a loadboard308or a printed circuit board (PCB). Thus, stacking the top PCB328on the integrated circuit product package302may reduce the footprint of the integrated circuit product package302on the loadboard308as well as reduce the number of resources needed for testing continuity of a die304. Further, by stacking the top PCB328on the integrated circuit product package302, continuity of the top PCB328may be tested without connecting the top PCB328directly to the loadboard308via one or more return lines for testing continuity on the top PCB328. Eliminating the return lines and larger or specialized test probes that would span from the top PCB328to the loadboard308may substantially reduce the footprint of the DUT on the loadboard308. By reducing the footprint of DUTs on the loadboard308, it may be possible to fit additional sites into a loadboard308.

In one configuration, eight integrated circuit product packages302coupled to one or more top PCBs328may be tested using a single loadboard308. While each of the integrated circuit product packages302may be independent from each other and tested one at a time, each of the packages may be efficiently tested by duplicating the connection of one or more test channels with each of the DUTs on the loadboard308.

FIG. 4illustrates one configuration of a system in package (SiP) system for testing continuity of circuitry fabricated on a first semiconductor die and a second semiconductor die. The system in package (SiP) system may include an integrated circuit product package402including a first die404and a second die436. The integrated circuit product package402may also include a package substrate406coupled to the first die404and the second die436via die interconnects414. The integrated circuit product package402may be one configuration of the integrated product packages102,302described above in connection withFIG. 1andFIG. 3, including a first die404and a second die436.

The integrated circuit product package402may include a first die404, a second die436and a package substrate406. The first die404may include I/O pins410, switches412and other circuitry on the die404. Circuitry on the first die404may be implemented in an integrated circuit. The package substrate406may include internal routing connections416. The first die404and the package substrate406may be connected using die interconnects414. The die404, package substrate406, I/O pins410, switches412, die interconnects414and internal routing connections416may be similar to corresponding elements104,106,110,112,114and116described above in connection withFIG. 1.

The integrated circuit product package402, including the first die404and the second die436, may also be connected to a loadboard408. The loadboard408may include internal routing, including a test channel input424and a test channel output426used for testing continuity of a circuit. The loadboard408may include loadboard contacts422and sockets for housing test probes420. The package substrate406of the integrated circuit product package402may connect to the loadboard408using substrate interconnects418and test probes420. The loadboard408, substrate interconnects418, test probes420and loadboard contacts422may be similar to corresponding elements108,118,120and122described above in connection withFIG. 1.

The system in package (SiP) system may also include a second die436. The second die436may include similar components as the first die404, such as I/O pins410, switches412and circuitry. In one configuration, the circuitry on the second die436may be implemented on an integrated circuit. In some configurations, additional dies may be implemented in an SiP system. Moreover, while the SiP may be implemented using flip chip assembly technology, the same approach may be used for wire bond or through silicon via (TSV) technology.

The second die436may be coupled to the package substrate406via multiple die interconnects414. The die interconnects414may be used to attach the second die436to the package substrate406. The die interconnects414may also be used to create an electrical connection from the I/O pins410on the second die436to internal routing connections416passing through the package substrate406. Each of the I/O pins410on the second die436may correspond to a different die interconnect414. The die interconnects414may be physically connected to a surface of the second die436. Further, the die interconnects414may be made from a variety of materials, such as solder balls or solder pads for connecting the second die436and the package substrate406. The die interconnects414may also be implemented using vias or other technologies for connecting and/or providing an electrical connection between the second die436and the package substrate406.

The I/O pins410on the second die436may be coupled to one or more I/O pins410on the first die404internally to the integrated circuit product package402using the internal routing channels416on the package substrate406. By connecting each of the I/O pins410on the second die436to different I/O pins410on the first die404, each of the I/O pins410on the second die436may be coupled to internal routing416on the loadboard408via connections to the loadboard408from the first die404. Therefore, using the connections to the loadboard408from the first die404, the second die436may be electrically coupled to the loadboard408using the internal routing connections416of the package substrate406.

The SiP system may be used to implement one or more daisy chains. A daisy chain may include components on the first die404, package substrate406and loadboard408. Additionally, a daisy chain may also include components on the second die436and internal routing connections416on the package substrate406connecting the first die404and the second die436. Each of the components that make up the daisy chain may be coupled together to form a single electrical path of components. A test channel may be generated using a daisy chain by passing an electrical signal from a first end of the daisy chain to a second end of the daisy chain. Therefore, components on the first die404and second die436included within a daisy chain may be tested for continuity using a single test channel.

The SiP system ofFIG. 4illustrates two possible daisy chains that may be implemented for testing continuity of circuitry within the SiP system. A first daisy chain may begin at a first test channel input424acoupled to a first loadboard contact422. The daisy chain may continue sequentially through a first test probe420, a first substrate interconnect418, a first internal routing connection416, a first die interconnect414and into the first die404through a first I/O pin410. The same daisy chain may continue through a switch412connecting the first I/O pin410and an adjacent second I/O pin410. Passing through the switch412, the daisy chain may continue through the second I/O pin410, a second die interconnect414, a second internal routing connection416, a second substrate interconnect418, a second test probe420and a second loadboard contact422coupling the second test probe420to a third test probe420. The daisy chain may continue through additional components on the integrated circuit product package402. In one configuration, the first daisy chain passes through I/O pins410on the first die404without passing through any of the components on the second die436. A second end of the daisy chain may pass through a loadboard contact422into a first test channel output426aon the loadboard408. An electrical signal applied to the first test channel input424amay be configured to pass through each component on the daisy chain and be output at the first test channel output426a.

The SiP system may also implement a second daisy chain. In contrast to the first daisy chain, the second daisy chain passes through components on multiple dies404,436. In one configuration a first end of the second daisy chain may begin at a second test channel input424bcoupled to a first loadboard contact422. The daisy chain may continue sequentially through a first test probe420, a first substrate interconnect418, a first internal routing connection416, a first die interconnect414and into the first die404through a first I/O pin410on the first die404. The same daisy chain may extend through a switch412on the first die coupling the first I/O pin410to an adjacent I/O pin410on the first die404. Passing through the switch412, the daisy chain may continue through the second I/O pin410on the first die404, a second die interconnect414, a second internal routing connection416, a first die interconnect414on the second die436and into the second die436through a first I/O pin410on the second die436. The daisy chain may extend through a switch412on the second die436coupling the first I/O pin410on the second die436with a second I/O pin410on the second die436. Passing through the switch412, the daisy chain may continue to pass back and forth between I/O pins410on the first die404and the second die436. The daisy chain may continue through additional components on the integrated circuit product package402, including components on the first die404and the second die436. A second end of the second daisy chain may pass through a loadboard contact422into a second test channel output426bon the loadboard408. An electrical signal applied to the second test channel input424bmay be configured to pass through each component on the daisy chain, including the first die404and the second die436, and be output at the second test channel output426b.

By configuring the switches412, internal routing connections416and loadboard contacts422to couple I/O pins410on the first die404and the second die436together into a single electrical path, a daisy chain may be generated that extends through I/O pins410on both the first die404and the second die436. In some configurations, multiple I/O pins410on the first die404and multiple I/O pins410on the second die436may be included in a single daisy chain. A test channel may be formed using a daisy chain by connecting a first end of the daisy chain to a test channel input424and a second end of the daisy chain to test channel output426. The continuity of the circuitry on the first die404and the second die436may be tested by applying an electrical signal to one end of the test channel and measuring a voltage or current of the test channel as a signal passes through the daisy chain. The continuity of each of the components on the daisy chain, including the first die404and second die436, may be determined through observation of the signal that passes through the test channel.

By implementing one or more daisy chains that pass through both the first die404and the second die436in an SiP system, the continuity of a second die436coupled to a first die404using internal routing connections416may be tested without performing separate functional or structural tests on the second die436. Testing the second die436at the same time as the first die404using a single daisy chain may save space and time when testing the continuity of one or more dies in an SiP system.

FIG. 5illustrates another configuration of a system for testing continuity of circuitry fabricated on a semiconductor die. The system includes an integrated circuit product package502, which may include a die504and a package substrate506. The integrated circuit product package502may be coupled to a loadboard508for testing continuity of the die circuitry that is fabricated on the die504. The integrated circuit product package502may be one configuration of the integrated circuit product package102described above in connection withFIG. 1.

The integrated circuit product package502may include a die504and a package substrate506. The die504may include I/O pins510, switches512and other circuitry on the die504. Circuitry on the die504may be implemented in an integrated circuit. The package substrate506may include internal routing connections516. The die504and the package substrate506may be connected using die interconnects514. The die504, package substrate506, I/O pins510, switches512, die interconnects514and internal routing connections516may be similar to corresponding elements104,106,110112,114and116described above in connection withFIG. 1.

The integrated circuit product package502may also be connected to a loadboard508. The loadboard508may include internal routing516, including test channel inputs524and test channel outputs526used for testing continuity of a circuit. The loadboard508may include loadboard contacts522and sockets for housing test probes520. The package substrate506of the integrated circuit product package502may connect to the loadboard508using substrate interconnects518and test probes520. The loadboard508, substrate interconnects518, test probes520and loadboard contacts522may be similar to corresponding elements108,118,120and122described above in connection withFIG. 1.

A die504may include groups of I/O pins510shorted together using one or more switches512. The switches512may be analog switches including one or more transistors. A die504may include groups of four I/O pins510shorted together using one or more transistors on the die504. Other configurations may include additional I/O pins510(e.g., 8, 16, 32 pins) grouped together by a configurations of switches512. The switches512may be configured to short or disconnect different I/O pins510within the same group of I/O pins510. In one example, the switches512may be used to connect non-adjacent I/O pins510together. Further, the I/O pins510within a particular group may not include any switches512connecting one or more I/O pins510from that group to any other group on the die504. Therefore, the different groups of I/O pins510may not be electrically connected within the die504to other groups of I/O pins510.

The loadboard508may also include internal routings for coupling one or more loadboard contacts522to other loadboard contacts522. In one configuration, internal routing on the loadboard508may be used to couple non-adjacent loadboard contacts522together. Therefore, instead of using a loadboard contact522for coupling one or more test probes520together, internal routing on the loadboard508may be used to couple one or more test probes520together, without sharing a loadboard contact522. The loadboard contacts522coupled together by the internal routing on the loadboard508may be non-adjacent loadboard contacts522. Coupling different loadboard contacts522together may be used to couple one group of I/O pins510to another group of I/O pins510.

The integrated circuit product package502may implement daisy chains using the groupings of I/O pins510on the die. In one configuration, the switches512on the die504may be configured to generate a daisy chain that passes through multiple I/O pins510to form a single electrical path of components on the die504. A test channel may be generated using the daisy chain by passing an electrical signal from a first end of the daisy chain to a second end of the daisy chain. Therefore, using one or more daisy chains, the DUT may be efficiently tested for continuity using fewer test channels.

The system illustrated inFIG. 5illustrates two possible configurations of daisy chains that may be used when testing continuity of circuitry on a die504. A first daisy chain may begin at a first test channel input524acoupled to a first loadboard contact522. The daisy chain may continue sequentially through a first test probe520, a first substrate interconnect518, a first internal routing connection516, a first die interconnect514and into the die504through a first I/O pin510. The first I/O pin510may be a part of a group of four I/O pins510. The same daisy chain may continue through a switch512connecting the first I/O pin510and a third I/O pin510. The first I/O pin510and the third I/O pin510may be non-adjacent I/O pins510. Passing through the switch512connecting the first I/O pin510and the third I/O pin510, the daisy chain may continue through the third I/O pin510and through a corresponding die interconnect514, internal routing connection516, substrate interconnect518, test probe520and loadboard contact522coupled to the test probe520. The test probe520may be coupled to a non-adjacent loadboard contact522via internal routing on the loadboard508. The daisy chain may continue to pass through alternating non-adjacent loadboard contacts522and alternating non-adjacent I/O pins510on the die. After passing through alternating I/O pins510, a second end of the daisy chain may pass through a loadboard contact522into a first test channel output526aon the loadboard508. An electrical signal applied to the first test channel input524amay be configured to pass through each component on the daisy chain and be output at the first test channel output526a.

In addition to the first daisy chain described above, the same configuration of the integrated circuit product package502may also implement a second daisy chain for testing continuity of circuitry on the die504. A first end of the second daisy chain may begin at a second test channel input524bcoupled to a second loadboard contact522. The daisy chain may continue sequentially through a second test probe520, a second substrate interconnect518, a second internal routing connection516, a second die interconnect514and into the die504through a second I/O pin510. The second I/O pin510may be a part of a group of four I/O pins510. The same daisy chain may continue through a switch512connecting the second I/O pin510and a fourth I/O pin510. The second I/O pin510and the fourth I/O pin510may be non-adjacent I/O pins510. Passing through the switch512connecting the second I/O pin510and the fourth I/O pin510, the daisy chain may continue through the fourth I/O pin510and through a corresponding die interconnect514, internal routing connection516, substrate interconnect518, test probe520and loadboard contact522coupled to the test probe520. The test probe520may be coupled to a non-adjacent loadboard contact522via internal routing on the loadboard508. The daisy chain may continue to pass through alternating non-adjacent loadboard contacts522and alternating other non-adjacent I/O pin510on the die. After passing through alternating I/O pins510, a second end of the second daisy chain may pass through a loadboard contact522into a second test channel output526bon the loadboard508. An electrical signal applied to the second test channel input524bmay be configured to pass through each component on the daisy chain and be output at the second test channel output526b.

By configuring the switches512connecting I/O pins510together into a single electrical path, a daisy chain may be generated that extends through multiple I/O pins510on the die504. In some configurations, the integrated circuit product package502may implement two daisy chains that pass through alternating I/O pins510across the entire die504. A test channel may be formed using a daisy chain by connecting a first end of the daisy chain to a test channel input524and a second end of the daisy chain to a test channel output526. The continuity of circuitry associated with the I/O pins510on the daisy chain may be tested by applying an electrical signal to one end of the test channel and measuring a voltage or current of the test channel as a signal passes through the daisy chain. The continuity of each of the components on the daisy chain may be determined through observation of the signal that passes through the test channel.

The switches512on the die may be used specifically to connect non-adjacent I/O pins510on the die504. By connecting non-adjacent I/O pins510, it is possible to detect unwanted shorts between adjacent I/O pins510. Specifically, if adjacent I/O pins510are coupled together in a daisy chain, it may not be possible to determine if the connection between adjacent I/O pins510is through a switch512or an unwanted short. Thus, connecting non-adjacent I/O pins510using daisy chains may enable testing continuity between adjacent I/O pins510. Therefore, in an example configuration with groups of multiple (e.g., four) I/O pins510, it may be possible to check the continuity of each I/O pin510using only two daisy chains connecting alternating and non-adjacent I/O pins510on the die504. In other configurations, different numbers of I/O pins510(e.g., 8, 16, 32 pins) may be grouped together in various configurations of daisy chains. Further, any number of I/O pins510may be grouped together in various daisy chain configurations.

Multiple daisy chains may be implementing on the integrated circuit product package502depending on the number and configuration of groups of I/O pins510on the die504. For example, the integrated circuit product package502may include groups of four I/O pins510. Alternatively, the integrated circuit product package502may include groups of eight, sixteen or thirty-two I/O pins510grouped together. Further, the number of daisy chains used for testing continuity may be as few as one or as many as sixteen daisy chains for testing a die containing thirty-two I/O pins510. Therefore, depending on availability of space on a loadboard508or demands of a particular system, switches512on the die504may be configured to increase or decrease the number of daisy chains implemented on the integrated circuit product package502.

FIG. 6is a top view of patterns of die interconnects that may be used in a system for testing continuity of circuitry fabricated on a semiconductor die. Specifically,FIG. 6illustrates a first die interconnect pattern638and a second die interconnect pattern640. Each die interconnect114may be associated with a different I/O pin110on the die104. As used herein, die interconnects114may also be referred to as solder balls, pads or interconnect bumps associated with corresponding I/O pins110. Alternatively, the die interconnects114may be implemented using vias or other technologies for connecting and/or providing an electrical connection between I/O pins110on a die104and a package substrate106. Further, each row or column of the die interconnect patterns638,640may be one configuration used in the integrated product packages102,302,402and502described above in connection withFIG. 1,FIG. 3,FIG. 4andFIG. 5.

A first die interconnect pattern638and a second die interconnect pattern640are shown. The first die interconnect pattern638illustrates one configuration of interconnect bumps646that may be implemented on an integrated circuit product package102. The second die interconnect pattern640illustrates another configuration of die interconnects that may be implemented on an integrated circuit product package. Each interconnect bump646may be associated with a different I/O pin110. Each of the first die interconnect pattern638and the second die interconnect pattern640includes ten interconnect rows644a-band ten interconnect columns642a-b. Other patterns may be used with fewer or additional rows and columns of interconnect bumps646.

The interconnect bumps646on the first die interconnect pattern638and the second die interconnect pattern640may be organized in four groups. Each group may correspond to a different daisy chain. In some configurations, none of the interconnect bumps646associated with a specific daisy chain group are adjacent to other interconnect bumps646associated with the same daisy chain group. Therefore, the daisy chains may be configured to include only non-adjacent interconnect bumps646associated with non-adjacent I/O pins110on a die104.

In one configuration, a first die interconnect pattern638may include ten interconnect columns642aand ten interconnect rows644a. Each column and row may correspond to a row or column of interconnect bumps646associated with a row or column of I/O pins110. Each row or column of interconnect bumps646of the first die interconnect pattern638may be similar to the configuration of die interconnects114and I/O pins110described above in connection withFIG. 5, with alternating interconnects bumps646on each row and column being associated with a different daisy chain. For example, alternating interconnect bumps646on the first row may be connected using a first daisy chain and a second daisy chain. Alternating interconnect bumps646on the second row may be connected using a third daisy chain and a fourth daisy chain. The third row may repeat the same pattern as the first row and so forth across the first die interconnect pattern638, with alternating rows using different pairs of daisy chains. In some configurations, a row may not be connected to one or more daisy chains. As an example, the fifth column and sixth row of interconnect bumps646are not connected to one of the four daisy chains, and have no signal passing through the interconnect bumps646associated the fifth column or sixth row in the first die interconnect pattern638.

A second die interconnect pattern640may include ten interconnect columns642band ten interconnect rows644b. Each column and row may correspond to a column or row of interconnect bumps646associated with a row or column of I/O pins110. Each column of interconnect bumps646on the second die interconnect pattern640may be similar to the configuration of die interconnects514and I/O pins510described above in connection withFIG. 5, with alternating interconnect bumps646on each column being associated with a different daisy chain. In one example, each interconnect row644includes interconnect bumps646associated with each of four daisy chains. The first, second, third and fourth daisy chains may be associated with a first row of interconnect bumps646on the first, second, third and fourth column of interconnect bumps646. The second row of interconnect bumps646may include the same four daisy chains offset by two interconnect bumps646in either direction. In other words, on the second row of interconnect bumps646, the first daisy chain may pass through an interconnect bump646on the third column, the second daisy chain may pass through an interconnect bump646on the fourth column, the third daisy chain may pass through an interconnect bump646on the first column and the fourth daisy chain may pass through an interconnect bump646on the second column. Therefore, the interconnect bumps646associated with each daisy chain may be offset by two columns for each subsequent row of interconnect bumps646. Similar to the first die interconnect pattern638, the fifth column and sixth row are shown as not being connected to one of the four daisy chains, and have no signal passing through the interconnect bumps646associated with the fifth column or sixth row in the second die interconnect pattern640.

Each of the first die interconnect pattern638and the second die interconnect pattern640implement a pattern of interconnect bumps646that avoids adjacent I/O pins110being grouped together in the same daisy chain. By using four daisy chains through the die interconnect patterns638,640, none of the horizontal, vertical or diagonal interconnect bumps646share an adjacent connection with a common daisy chain. By configuring the daisy chains to avoid passing through adjacent I/O pins110, shorts between I/O pins110may be more easily detected. Because adjacent I/O pins110that share a common daisy chain may not show any potential difference when a signal passes through the common daisy chain, it may be beneficial to use different daisy chains for adjacent I/O pins110to avoid undetectable shorts between adjacent I/O pins110on the same daisy chain.

More or less than four daisy chains may be used in other configurations. Additional daisy chains may be used specifically to more precisely determine the location of fails in continuity of circuitry on a die104. Further, additional daisy chains and different pattern configurations may be used to pair non-adjacent I/O pins110together in daisy chains running through the integrated circuit product package102.

FIG. 7illustrates a circuit diagram representing a configuration of daisy chains for detecting open circuits on a semiconductor die. The circuit diagram illustrates one configuration of an open detection daisy chain configuration748. The open detection daisy chain configuration748may be modeled as a circuit with multiple resistances752representing circuits of multiple daisy chains750coupled together to form larger daisy chain circuits. The continuity of each daisy chain750may be tested by detecting open connections on each daisy chain750.

The open detection daisy chain configuration748may be used for detecting open connections on multiple daisy chains750. In one example, the open detection daisy chain configuration748may include four daisy chains750a-dpassing through various components on an integrated circuit product package102and a loadboard108similar to other configurations described herein. Each of the daisy chains750may include a first resistance752a, second resistance752b, a third resistance752cand one or more additional resistances up to an Nth resistance752n. Each resistance752on a daisy chain750may be used to represent circuitry (e.g., I/O pins110, die circuitry) within a daisy chain750. To test for open connections on the daisy chains750, each end of a first daisy chain750amay be coupled to a ground reference. Each end of a second daisy chain750b, third daisy chain750cand fourth daisy chain750dmay be coupled to open connections. A bias voltage754and/or current may be applied to a first end of the first daisy chain750aand a resistance752of the first daisy chain750amay be measured. Therefore, only one daisy chain750is connected to a complete circuit (e.g., a test channel) at a time when testing for open connections on the daisy chains750. If a measurement on the first daisy chain750areads a certain finite resistance, the tests indicate that there are not any open connections on the first daisy chain750a. If a measurement on the first daisy chain750areads an infinitely high resistance, an open circuit exists somewhere along the first daisy chain750a. The test may then be repeated for each daisy chain750by disconnecting the first daisy chain750aand repeating the test for each subsequent daisy chain750b-din the open detection daisy chain configuration748.

FIG. 8illustrates a circuit diagram representing a configuration of daisy chains for detecting shorts on a semiconductor die. The circuit diagram illustrates one configuration of a short detection daisy chain configuration856. The short detection daisy chain configuration856may be modeled as a circuit with multiple resistances852representing circuits of multiple daisy chains850coupled together to form larger daisy chain circuits. The continuity of each daisy chain850may be tested by detecting shorts on each daisy chain850.

The short detection daisy chain configuration856may be used for detecting shorts on multiple daisy chains850. In one example, the short detection daisy chain configuration856may include four daisy chains850a-dpassing through various components on an integrated circuit product package102and a loadboard108similar to other configurations described herein. Each of the daisy chains850may include a first resistance852a, second resistance852b, a third resistance852cand one or more additional resistances up to an Nth resistance852n. Each resistance on the daisy chain may be used to represent circuitry (e.g., I/O pins110, die circuitry) within a daisy chain850. To test for shorts on the daisy chains850, a first end of the first daisy chain850amay be coupled to a ground reference while a second end of the first daisy chain850ais coupled to an open connection. Each end of a second daisy chain850b, third daisy chain850cand fourth daisy chain850dmay be connected to a ground reference. A bias voltage854and/or current may be applied to a first end of the first daisy chain850aand a resistance of the first daisy chain850amay be measured. If a measurement on the first daisy chain850areads an infinitely high resistance, the tests indicate that there are not any shorts on the first daisy chain850a. If the measurement on the first daisy chain850areads a certain finite resistance, a short exists somewhere between the daisy chains850. The test may then be repeated for each daisy chain850by disconnecting the first daisy chain850aand repeating the test for each of the subsequent daisy chains850b-din the short detection daisy chain configuration856.

FIG. 9illustrates a circuit diagram representing a configuration of daisy chains for detecting shorts and open circuits on a semiconductor die. The circuit diagram includes an open and short detection daisy chain configuration958. The open and short detection daisy chain configuration958illustrates four daisy chains950modeled as a circuit with multiple resistances952representing circuits on each of the daisy chains950. The open and short detection daisy chain configuration958may be used to detect open connections and shorts for each of the daisy chains950simultaneously.

The open and short detection daisy chain configuration958may include four daisy chains950a-dpassing through various components on an integrated circuit product package102and a loadboard108similar to other configurations described herein. Each of the daisy chains950may include a first resistance952a, a second resistance952b, a third resistance952cand one or more additional resistances up to an Nth resistance952n. Each resistance952on the daisy chains950may be used to represent circuitry (e.g., I/O pins110, die circuitry) within a daisy chain950. The first end and second end of each daisy chain950may be coupled to ground.

Using the open and short detection daisy chain configuration958, open and shorted connections may be detected on each of the daisy chains950by applying a different bias voltage954to each of the daisy chains950. For example, a first bias voltage954amay be applied to a first end of the first daisy chain950a, a second bias voltage954bmay be applied to a first end of the second daisy chain950b, a third bias voltage954cmay be applied to a first end of the third daisy chain950cand a fourth bias voltage954dmay be applied to a first end of the fourth daisy chain950d. Each of the bias voltages954applied to the daisy chains950may be different voltages. A difference voltage960may also be applied to the second end of each of the daisy chains950. For example, a first difference voltage960amay be applied to the second end of the first daisy chain950a, a second difference voltage960bmay be applied to the second end of the second daisy chain950b, a third difference voltage960cmay be applied to the second end of the third daisy chain950cand a fourth difference voltage960dmay be applied to the second end of the fourth daisy chain950d. The difference voltages960may be different from a corresponding bias voltage954for the same daisy chain. For example, the difference between the first bias voltage954aand the first difference voltage960amay cause a current to flow from a first end of the first daisy chain950ato a second end of the first daisy chain950a.

A difference between the values of the bias voltages954and corresponding difference voltages960may be relatively small. Specifically, the difference between each of the bias voltages954may be much larger than the difference between each bias voltage954and the corresponding difference voltage960for the same daisy chain950. For example, the difference between the first bias voltage954aand the second bias voltage954bmay be larger than the difference between the first bias voltage954aand the first difference voltage960a. As an example, the difference between each subsequent bias voltage954on different daisy chains950may be 1 Volt (V) while the difference between each bias voltage954and corresponding difference voltage960on the same daisy chain950may be 100 millivolts (mV). By making the difference between the bias voltages954and corresponding difference voltages960relatively small, shorts may be more easily detected between different daisy chains950. Because the difference in potential between different daisy chains950is substantially larger than the difference between the bias voltages954and corresponding difference voltages960, a short between daisy chains950will cause a higher current to pass through various components on the affected daisy chains950. If a high current is detected, then a short exists somewhere along the affected daisy chains950. If zero current is detected, then there is an open connection somewhere along the daisy chain950.

By using the open and short detection daisy chain configuration958, both shorts and open circuits may be tested simultaneously. Further, each of the daisy chains950may be tested for shorts and open circuits simultaneously saving time and repetitive testing for each individual daisy chain950.

FIG. 10illustrates certain components that may be included within a wireless device1002. The wireless device1002may be an access terminal, a mobile station, a user equipment (UE), etc. The wireless device1002includes a processor1003. The processor1003may be a general purpose single- or multi-chip microprocessor (e.g., an ARM), a special purpose microprocessor (e.g., a digital signal processor (DSP)), a microcontroller, a programmable gate array, etc. The processor1003may be referred to as a central processing unit (CPU). Although just a single processor1003is shown in the wireless device1002ofFIG. 10, in an alternative configuration, a combination of processors (e.g., an ARM and DSP) could be used.

The wireless device1002also includes memory1005. The memory1005may be any electronic component capable of storing electronic information. The memory1005may be embodied as random access memory (RAM), read-only memory (ROM), magnetic disk storage media, optical storage media, flash memory devices in RAM, on-board memory included with the processor, erasable programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), registers and so forth, including combinations thereof.

Data1007aand instructions1009amay be stored in the memory1005. The instructions1009amay be executable by the processor1003to implement the methods disclosed herein. Executing the instructions1009amay involve the use of the data1007athat is stored in the memory1005. When the processor1003executes the instructions1009, various portions of the instructions1009bmay be loaded onto the processor1003, and various pieces of data1007bmay be loaded onto the processor1003.

The wireless device1002may also include a transmitter1011and a receiver1013to allow transmission and reception of signals to and from the wireless device1002via an antenna1017. The transmitter1011and receiver1013may be collectively referred to as a transceiver1015. The wireless device1002may also include (not shown) multiple transmitters, multiple antennas, multiple receivers and/or multiple transceivers.

The wireless device1002may include a digital signal processor (DSP)1021. The wireless device1002may also include a communications interface1023. The communications interface1023may allow a user to interact with the electronic device/wireless device1002.

A wireless device may be a wireless communication device or a base station. A wireless communication device may also be referred to as, and may include some or all of the functionality of, a terminal, an access terminal, a user equipment (UE), a subscriber unit, a station, etc. A wireless communication device may be a cellular phone, a personal digital assistant (PDA), a wireless device, a wireless modem, a handheld device, a laptop computer, a PC card, compact flash, an external or internal modem, a wireline phone, etc. A wireless communication device may be mobile or stationary. A wireless communication device may communicate with zero, one or multiple base stations on a downlink and/or an uplink at any given moment. The downlink (or forward link) refers to the communication link from a base station to a wireless communication device, and the uplink (or reverse link) refers to the communication link from a wireless communication device to a base station. Uplink and downlink may refer to the communication link or to the carriers used for the communication link.

A wireless device may operate in a wireless communication system that includes other wireless devices, such as base stations. A base station is a station that communicates with one or more wireless communication devices. A base station may also be referred to as, and may include some or all of the functionality of, an access point, a broadcast transmitter, a Node B, an evolved Node B, etc. Each base station provides communication coverage for a particular geographic area. A base station may provide communication coverage for one or more wireless communication devices. The term “cell” can refer to a base station and/or its coverage area, depending on the context in which the term is used.

Communication in a wireless communication system (e.g., a multiple-access system) may be achieved through transmissions over a wireless link. Such a communication link may be established via a single-input and single-output (SISO) or a multiple-input and multiple-output (MIMO) system. A multiple-input and multiple-output (MIMO) system includes transmitter(s) and receiver(s) equipped, respectively, with multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. SISO systems are particular instances of a multiple-input and multiple-output (MIMO) system. The multiple-input and multiple-output (MIMO) system can provide improved performance (e.g., higher throughput, greater capacity or improved reliability) if the additional dimensionalities created by the multiple transmit and receive antennas are utilized.

The wireless communication system may utilize both single-input and multiple-output (SIMO) and multiple-input and multiple-output (MIMO). The wireless communication system may be a multiple-access system capable of supporting communication with multiple wireless communication devices by sharing the available system resources (e.g., bandwidth and transmit power). Examples of such multiple-access systems include code division multiple access (CDMA) systems, wideband code division multiple access (W-CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) systems and spatial division multiple access (SDMA) systems.

The functions described herein may be implemented in software or firmware being executed by hardware. The functions may be stored as one or more instructions on a computer-readable medium. The terms “computer-readable medium” or “computer-program product” refers to any tangible storage medium that can be accessed by a computer or a processor. By way of example, and not limitation, a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. It should be noted that a computer-readable medium may be tangible and non-transitory. The term “computer-program product” refers to a computing device or processor in combination with code or instructions (e.g., a “program”) that may be executed, processed or computed by the computing device or processor. As used herein, the term “code” may refer to software, instructions, code or data that is/are executable by a computing device or processor.