Semiconductor memory device having mask ROM structure

A semiconductor memory device is provided with a memory cell array having a plurality of memory cells formed by a mask ROM. The memory cell array has a data area in which stored data of n bits is stored and a parity area in which a one-bit parity code corresponding to the stored data is stored. A control circuit supplies the memory cell array with an address and reads out the stored data and the one-bit parity code designated by the address. A parity check circuit determines whether the data read out from the memory cell array has a bit error and generates a correction bit responsive thereto. A memory stores predetermined indicating data indicating which of the n bits of the stored data is defective. A data correction circuit then corrects one of the n bits of the data indicated by the predetermined indicating data in response to the correction bit generated by the parity check circuit.

BACKGROUND OF THE INVENTION 
The present invention relates to a semiconductor memory device having a 
mask ROM structure, and more particularly to a semiconductor memory device 
having an error correcting function. 
A semiconductor memory device having a mask ROM structure is known. A 
memory cell array including a plurality of memory cells is configured by 
mask ROM elements. Information is written into the memory cell array 
during manufacturing the memory device. Once information is written into 
the memory cell array, it is impossible to revise the written information. 
Actually, a memory device has some defective memory cells. Thus, a 
programmable ROM is incorporated in the memory device. After fabricating 
the memory device, it is subjected to a test for locating defective memory 
cells. The address of each detected defective memory cell is written into 
the programmable ROM. That is, the defective memory cells are replaced by 
memory cells of the programmable ROM. When the address of a defective 
memory cell is designated, the corresponding memory cell of the 
programmable ROM is accessed and information stored therein is read out 
from the programmable ROM. 
However, memory cells of the programmable ROM are larger than those of the 
mask ROM. For this reason, a large area on a chip must be provided for the 
programmable ROM. This decreases the integration density of the memory 
device. Further, it takes an extremely long time to write address 
information and data on defective memory cells into the programmable ROM. 
SUMMARY OF THE INVENTION 
It is a general object of the present invention to provide an improved 
semiconductor memory device having a mask ROM structure in which the 
aforementioned disadvantages are eliminated. 
A more specific object of the present invention is to provide a 
semiconductor memory device having a mask ROM structure in which a reduced 
area of the programmable ROM on the chip is provided and it takes a 
reduced time to write information indicating the positions and data of 
defective memory cells into the programmable ROM. 
The above objects of the present invention are achieved by a semiconductor 
memory device comprising a memory cell array having a plurality of memory 
cells and formed by a mask ROM, the memory cell array having a data area 
in which data of n bits (n is an arbitrary number) is stored and a parity 
area in which a one-bit parity code relating to the data is stored; 
control means, coupled to the memory cell array, for supplying the memory 
cell array with an address and reading out the data and the one-bit parity 
code designated by the address; parity check means, coupled to the memory 
cell array, for determining whether or not the data read out from the 
memory cell array has a bit error and for generating correction data 
indicating a determination result; memory means for storing defective 
output indicating data indicating one of the n bits of the data having the 
bit error; and data correcting means, coupled to the memory cell array, 
the parity check means and the memory means, for correcting one of the n 
bits of the data indicated by the defective output indicating data by the 
correction bit. 
The above-mentioned objects of the present invention are achieved by a 
semiconductor memory device comprising a memory cell array having a 
plurality of memory cells and formed by a mask ROM, the memory cell array 
having a data area in which data of n bits (n is an arbitrary number) is 
stored and a parity area in which a one-bit parity code relating to the 
data is stored, the data area being divided into blocks each divided into 
m sub-blocks (m is an arbitrary number); control means, coupled to the 
memory cell array, for supplying the memory cell array with an address 
including information indicating one of the m sub-blocks and reading out 
the data and the one-bit parity code designated by the address; parity 
check means, coupled to the memory cell array, for determining whether or 
not the data read out from the memory cell array has a bit error and for 
generating correction data indicating a determination result; memory means 
for storing defective output indicating data indicating one of the m 
sub-blocks of each of the blocks relating to the bit error; and data 
correcting means, coupled to the memory cell array, the parity check means 
and the memory means, for correcting, by the correction bit supplied from 
the parity check means, one of the n bits of the data relating to the one 
of the m sub-blocks indicated by the defective output indicating data 
supplied from the memory means. 
Further objects, features and advantages of the present invention will 
become apparent from the following detailed description when read in 
conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIG. 1, a semiconductor memory device includes a memory cell 
array 10 formed by a mask ROM. The memory cell array 10 is divided into a 
data area 10a and a parity area 10b. In the data area 10a, each row is 
divided into n blocks (n is an arbitrary number). For example, each row is 
divided into 16 blocks. Each block stores data composed of a predetermined 
number of bits, for example, 16 bits. In this case, each block has 16 
memory cells MC. The parity area 10b stores, for each row, an even (or 
odd) number parity bit provided for each data of n bits, each of which 
relates to the respective block. Thus, n even (or odd) number parity bits 
are stored in the parity area 10b for each row. In the following 
description, each row of the data array 10a is divided into 16 blocks, 
each of which stores 16 bits for each row. 
A row address is input to a row decoder 13 through a terminal 11, and a 
column address is input to a column decoder/sense amplifier 14 through a 
terminal 14. The row decoder 13 decodes the row address and selects one of 
a plurality of word lines (rows). When a decoded row address is supplied 
to the memory cell array 10, data and the parity bits relating to the 
designated row are read out therefrom and supplied to the column 
decoder/sense amplifier 14. The column decoder/sense amplifier 14 decodes 
the column address and selects data of 16 bits and a corresponding one-bit 
parity code relating to a decoded column address among from the data and 
one-bit parity codes read out from the memory cell array 10. The 16 data 
bits selected by the column decoder/sense amplifier 14 are supplied to a 
data correction block 15 and a parity check circuit 16. At the same time, 
the one-bit parity code relating to the selected data equal to 16 bits is 
supplied to the parity check circuit 16. The data correction block 15 is 
made up of 16 data correction circuits 15.sub.1, 15.sub.2, . . . , 
15.sub.16. 
FIG. 2 is a circuit diagram of the parity check circuit 16. As is shown, 
the parity check circuit 16 is made up of a parity generator 16a and an 
exclusive-OR gate (XOR gate) 16b. The parity generator 16a receives the 
selected 16-bit data labeled SO.sub.1, SO.sub.2, . . . , SO.sub.16 and 
derives a one-bit parity output Pa. The XOR gate 16b receives the one-bit 
parity output Pa and the one-bit parity code labeled Pb supplied from the 
parity area 10b through the column decoder/sense amplifier 14, and 
generates a correction bit CB. When a parity error is detected, the 
correction bit CB is `1`. On the other hand, when no parity error is 
detected, the correction bit CB is `0`. The correction bit CB is supplied 
to the data correction circuits 15.sub.1 -15.sub.16. 
A defective output indicating memory 17 formed by a programmable ROM such 
as a fuse ROM stores address information for each 16-bit data. Address 
information indicates which one of the 16 bits forming a 16-bit data is 
defective if the 16-bit data has a one-bit error. The memory device is 
tested after it is manufactured. In test, it is determined whether each 
memory cell of the data area 10a generates a bit error. 
FIG. 3 is a circuit diagram of the defective output indicating memory 17. 
As is illustrated, the defective output indicating memory 17 has 16 
transistors Tr.sub.1, Tr.sub.2, Tr.sub.3, . . . , Tr.sub.16 and 16 fuses 
F.sub.1, F.sub.2, F.sub.3, . . . , F.sub.16 for each 16-bit data. Select 
data S.sub.1, S.sub.2, S.sub.3, . . . , S.sub.16 are drawn from the nodes 
of the transistors Tr.sub.1, Tr.sub.2, Tr.sub.3, . . . , Tr.sub.16 and the 
fuses F.sub.1, F.sub.2, F.sub.3, . . . , F.sub.16, respectively. When it 
is determined that one-bit data (memory cell) corresponding to the fuse 
F.sub.3 for example, generates a bit error, the fuse F.sub.3 is broken, 
and the other fuses relating to data bits having no error are held as they 
are. In this case, the select data S.sub.3 is switched to a high level 
(Vcc; a positive power source voltage), and the other select data are 
maintained at a low level (ground level). The select data S.sub.1 
-S.sub.16 are supplied to the data correction circuits 15.sub.1 
-15.sub.16, respectively. 
FIG. 4 is a circuit diagram of the data correction circuit 15.sub.1. Each 
of the data correction circuits 15.sub.2 -15.sub.16 has the same structure 
as the data correction circuit 15.sub.1. The correction bit CB from the 
parity check circuit 16 is supplied to an XOR gate 31 through a terminal 
30. The data bit SO.sub.1 from the column decoder/sense amplifier 14 is 
supplied to the XOR gate 31 and a transmission gate 33 through a terminal 
32. The XOR gate 31 inverts the data bit SO.sub.1 when the correction bit 
CB is `1`, and passes the data bit SO.sub.1 as it is when the correction 
bit CB is `0`. The output from the XOR gate 31 is supplied to a 
transmission gate 34. Each of the transmission gates 33 and 34 is supplied 
with the select data S.sub.1 through a terminal 35 and inverted data 
thereof formed through an inverter 36. When the select data S.sub.1 is 
`0`, the transmission gate 33 conducts. On the other hand, when the select 
data S.sub.1 is `1`, the transmission gate 34 conducts. The output from 
each of the transmission gates 33 and 34 passes through a terminal 37 and 
is applied, as an output OUT.sub.1, to an output buffer 19.sub.1 (FIG. 1). 
Table 1 represents the operation of the data correction circuit 15.sub.1. 
Each of the other data correction circuits 15.sub.2 -15.sub.16 operates in 
the same way as the data correction circuit 15.sub.1. 
TABLE 1 
______________________________________ 
S.sub.1 CB SO.sub.1 
OUT.sub.1 
______________________________________ 
0 -- 1 1 
0 -- 0 0 
1 0 1 1 
1 0 0 0 
1 1 1 0 
1 1 0 1 
______________________________________ 
By the above-mentioned manner, one of the 16 data bits relating to a 
defective memory cell in the data area 10a (FIG. 1) is corrected by a 
corresponding one of the data correction circuits 15.sub.1 -15.sub.16. The 
outputs from the data correction circuits 15.sub.1 -15.sub.16 are 
amplified by the output buffers 19.sub.1 -19.sub.16 and then output 
through terminals 20.sub.1 -20.sub.16, respectively. 
A description is given of a second embodiment of the present invention with 
reference to FIG. 5, in which those parts which are the same as those 
shown in FIG. 1 are given the same reference numerals. As is shown in FIG. 
6, each block #1, #2, . . . , #16 is divided into m blocks (m is an 
arbitrary integer), four sub-blocks in the illustrated case. One of the 
four sub-blocks is designated by two high-order bits of the column address 
applied to the terminal 12. The defective output indicating memory 17 
shown in FIG. 1 is replaced by a defective output indicating memory 40 
having a terminal 18. 
FIG. 7 is a circuit diagram of the defective output indicating memory 40. 
As is shown, the detective output indicating memory 40 is made up of a 
logic circuit 47, a programmable ROM 48 such as a fuse ROM, and an address 
decoder 49. The aforementioned two high-order bits of the column address 
labeled A1 and A2 (terminal 18 in FIG. 5) are applied to the address 
decoder 49, which outputs a decoded signal consisting of four bits. The 
fuse ROM 48 is divided into 16 circuits 48.sub.1, 48.sub.2, . . . , 
48.sub.16. The logic circuit 47 is divided into 16 sections 47.sub.1, 
47.sub.2, . . . , 47.sub.16. The circuits 48.sub.1, 48.sub.2, . . . , 
48.sub.16 of the fuse ROM 48 are provided for the sections 47.sub.1, 
47.sub.2, . . . , 47.sub.16 of the logic circuit 47, respectively. The 
circuit 48.sub.1 generates a control signal C.sub.1 and a pair of 
sub-block designation signals S.sub.11 and S.sub.12. The control signal 
C.sub.1 indicates whether or not the corresponding output from the data 
area 10a of the memory cell array 10 through the column decoder/sense 
amplifier 14 (FIG. 6) should be corrected. The pair of sub-block 
designation signals S.sub.11 and S.sub.12 indicates one of the four 
sub-blocks which has a defective memory cell to be corrected. Each of the 
other circuits 48.sub.2 -48.sub.16 generates a control signal such as 
C.sub.2 and a pair of sub-block designation signals such as S.sub.21 and 
S.sub.22 in the same way as the circuit 48.sub.1. 
The control signal C.sub.1 and the pair of sub-block designation signals 
S.sub.11 and S.sub.12 are supplied to a decoder 50 of the section 47.sub.1 
of the logic circuit 47. The section 47.sub.1 decodes the input signals 
and generates four decoded signals. The section 47.sub.1 of the logic 
circuit 47 includes NOR gates 51a, 51b, 51c and 51d, and an OR gate 52. 
The four decoded signals derived from the decoder 50 are supplied to the 
respective NOR gates 51a, 51b, 51c and 51d, which are also supplied with 
the respective signals supplied from the address decoder 49. Four outputs 
from the NOR gates 51a, 51b, 51c and 51d are input to the OR gate 52, 
which outputs a one-bit select signal X.sub.1. Each of the sections 
47.sub.2 -47.sub.16 is configured in the same way as the section 47.sub.1, 
and outputs a corresponding one-bit select signal. The select signals 
X.sub.1, X.sub.2, . . . , X.sub.16 are supplied to the data correction 
circuits 15.sub.1, 15.sub.2, . . . , 15.sub.16. 
The relationship between the signals C.sub.1, S.sub.11 and S.sub.12 and one 
of the sub-blocks to be corrected is shown in Table 2. 
TABLE 2 
______________________________________ 
C.sub.1 S.sub.12 
S.sub.11 Parity correction 
______________________________________ 
L L L first sub-block 
L L H second sub-block 
L H L third sub-block 
L H H fourth sub-block 
H X X no correction 
______________________________________ 
FIG. 8 is a circuit diagram of the address decoder 49 shown in FIG. 7. The 
address decoder 49 is composed of two inverters 49a and 49b, and four NAND 
gates 49c, 49d, 49e and 49f. Two inputs A and B are decoded and four 
outputs Y0, Y1, Y2 and Y3 are generated. 
FIG. 9 is a circuit diagram of each decoder 50 shown in FIG. 7. The decoder 
50 is composed of three inverters 50a, 50b and 50c, and four NAND gates 
50d, 50e, 50f and 50g. Three inputs Cx, Sx1, Sx2 (corresponding to the 
aforementioned control signal such as C.sub.1 and sub-block designation 
signals such as S.sub.11 and S.sub.12) are decoded and four outputs Z0, 
Z1, Z2 and Z3 are generated. The fuse ROM 48 is configured by transistors 
and fuses in the same manner as the aforementioned arrangement shown in 
FIG. 3. 
Turning to FIG. 7, when the two high-order bits A1 and A2 of the column 
address indicates the first block and the decoder of the section 47.sub.1 
of the logic circuit 47 indicates that the first block is to be corrected, 
for example, the OR gate 52 outputs the select signal X.sub.1 maintained 
at the high level (`1`). It is noted that two bits in the same sub-block 
are defective, it is impossible to correct those bits. 
According to the present invention, it is possible to correct one-bit data 
only by storing one-bit address information on a defective memory cell in 
the programmable ROM. Thus, a large-capacity programmable ROM is 
unnecessary. As a result, it is possible to suppress an increase of the 
chip area and reduce the time it takes to write address information into 
the programmable ROM. 
An alternative cofiguration of the defective output indicating memory 17 
shown in FIG. 3 is illustrated in FIG. 10. The alternative configuration 
includes four transistors Tr.sub.1 -Tr.sub.4, four associated fuses 
F.sub.1 -F.sub.4 and a decoder circuit 50. The select signals S.sub.1 
'-S.sub.4 ' are supplied to the decoder circuit 50, which decodes the 
select signals S.sub.1 '-S.sub.4 ' and derives the 16 select signals 
S.sub.1 -S.sub.16 therefrom. 
The present invention is not limited to the aforementioned embodiments, and 
variations and modifications may be made without departing from the scope 
of the present invention.