Continuous time sigma-delta A/D converter and electrical system comprising the A/D converter

A continuous time sigma-delta analog-to-digital converter comprising: a summator of an input analog signal and a feedback signal; a feed-forward integrator path connected to the summator and configured to provide a digital signal; a feedback digital-to-analog converter to convert the digital signal into a feedback analog signal; a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the summator.

BACKGROUND

1. Technical Field

The present disclosure relates to analog-to-digital converters and, particularly, to continuous time sigma-delta analog-to-digital converters.

2. Description of the Related Art

Delta-Sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a technique which has found increasing use in a range of modern electronic components, such as analog-to-digital and digital-to-analog converters.FIG. 1shows a conventional continuous time sigma-delta analog-to-digital converter provided with an integrator (consisting of an operational amplifier APAand a feedback capacitor CPA), a low pass filter FPA, a quantizer QPA, and a feedback path via a current mode digital-to-analog converter DACPA.

A low unit gain bandwidth or low slew rate of the operational amplifier employed by the integrator gives rise to distortion of the feedback signal. Particularly, in case of too low bandwidth the gain of the operational amplifier is too low to suppress the inherent non-linearity of its own transfer characteristic at higher frequencies, while in case of too low slew rate the gain of the operational amplifier becomes dependent on its input signal.

Due to the strong high pass shaping of the quantization noise in sigma-delta analog-to-digital converters, any distortion of the feedback signal results in high frequency noise being mixed with other high frequency noise and further being converted down to low frequency, thereby corrupting the noise shaping and degrading the signal to noise ratio (SNR). Hence for high signal to noise ratio and low distortion a very fast operational amplifier with high power dissipation is required.

BRIEF SUMMARY

The sigma-delta analog-to-digital converters of the prior art techniques require high performance integrators. Particularly, operational amplifiers showing large bandwidth and high slew rate are required.

According to an embodiment, a continuous time sigma-delta analog-to-digital converter is provided which comprises a summator configured to provide a difference signal equal to a difference between an input analog signal and a feedback signal; a feed-forward integrator path connected to the summator and configured to provide a digital signal; a feedback digital-to-analog converter configured to convert the digital signal into a feedback analog signal; and a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the summator.

According to another embodiment an electrical system is provided that comprises a continuous time sigma-delta analog-to-digital converter configured to produce a digital signal and a processing apparatus connected to said analog-to-digital converter and configured to process the digital signal. The analog-to-digital converter includes an input terminal structured to receive an input analog signal and a feedback signal; a feed-forward integrator path connected to the input terminal and configured to provide a digital signal; a feedback digital-to-analog converter configured to convert the digital signal into a feedback analog signal; and a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the input terminal;

DETAILED DESCRIPTION

FIG. 2schematically shows an electrical system100such as a radio tuner system structured to receive radio broadcasts and convert them into audio-frequency signals which can be fed into an amplifier600driving a loudspeaker700. Particularly, the radio tuner system100can be a highly integrated tuner which deals with transmissions using different methods of modulation or transmissions techniques, such as: FM (frequency modulation), AM (amplitude modulation) and digital audio broadcasting (DAB). In accordance with a particular example, the radio tuner system100can be installed in a vehicle (e.g. a car) radio device.

In addition to further devices known per se, the radio turner system100comprises an analog-to-digital converter200(ADC) and a further analog-to-digital converter300(ADC), a demodulator400and a digital signal processor500(DSP).

Particularly, each of the above analog-to-digital converter200and300is a continuous time sigma-delta analog-to-digital modulator and can be structurally and functionally analogous. As an example, the analog-to-digital converter200is configured to convert into a first digital signal the “I” component V1inof an analog IQ signal received at an intermediate frequency. According to this example, the further analog-to-digital converter300is configured to convert into a second digital signal the “Q” component V2inof the analog IQ signal. The IQ demodulation is performed by the demodulator400which provides output digital demodulated signals to the DSP500for further processing.

FIG. 3schematically illustrates an embodiment of the continuous time sigma-delta analog-to-digital modulator200(hereinafter also denoted as ADC converter) which comprises a summator1, configured to receive an input analog signal Vin(e.g. a voltage signal) and a feedback signal Vfffb, and a feed-forward integrator path2configured to provide a digital signal Dout on a digital output12. The ADC converter200further includes a feedback path provided with a digital-to-analog converter3(DAC), configured to convert the digital signal Dout into a feedback analog signal Vfb, and a feedback low pass filter4structured to filter the feedback analog signal Vfband provide the feedback signal Vffbto the summator1. The summator1comprises a first terminal6for receiving the feedback signal Vfffb, a second terminal7for receiving the input analog signal Vinwhich can be, according to the system100ofFIG. 2, the I″ component V1inand a third terminal8.

The feed-forward integrator path2comprises an integrator device including an operational amplifier in an integrator configuration. In accordance with the embodiment illustrated inFIG. 3, the integrator device includes an operational amplifier5provided with an inverting input “−” connected to the first terminal6of the summator1, a non-inverting input “+” connected to a ground terminal GND and the third terminal8of the summator1via input capacitor CP1, and an amplifier output9.

Moreover, in accordance with the schematization ofFIG. 3, the summator1includes a first input resistor RP1connected between the second terminal7and a the third terminal8, and a second input resistor RP2connected between the third terminal8and the inverting input of the operational amplifier5. The feed-forward integrator path2also includes a feedback capacitor C having a first terminal connected to the amplifier output9and a second terminal connected to the inverting input of the operational amplifier5via an electrical link.

This electrical link can be a conductive path or, in accordance with the illustrated embodiment, it can also include a feedback resistor RZwhich is so interposed between the feedback capacitor C and the inverting input of the operational amplifier5. Moreover, the feed-forward integrator path2includes the above mentioned second input resistor RP2and a low pass filter10having a respective input connected to the amplifier output5and a respective output connected to a quantizer11.

The feedback low pass filter4is, particularly, an RC filter including a filter capacitor having a terminal connected between the output of the digital-to-analog converter3and a ground terminal GND. The feedback low pass filter4also includes a filter resistor RPconnected to the output of the digital-to-analog converter3and the first terminal6of the summator1. The quantizer11is provided with an input terminal for a frequency signal fCLKindicating the frequency of a clock signal CLK and can include, as an example, a latched comparator.

The above described embodiment of the ADC converter200can be integrated in a semiconductor chip by employing, as an example, the CMOS (complementary metal oxide semiconductor) technology or a BiCMOS (Bipolar CMOS) technology.

In operation, at the inputs of the operational amplifier5a signal representing the difference between the input analog signal Vinand the feedback signal Vffbis supplied. The operational amplifier5, which is in the above described integrator configuration, accumulates or sums this difference and feeds an integrated analog signal to the low pass filter10. The integrated and filtered analog signal is then supplied to the quantizer11which via a sampling and a quantization produces the digital signal Dout. The frequency signal fCLKsupplied to the quantizer11determines the data rate of the digital signal Dout, which represents the input analog signal Vinplus highpass shaped quantization noise.

The digital signal Dout is then fed to the digital-to-analog converter3generating the corresponding feedback analog signal Vfbwhich can correspond to rectangular current pulses or exponentially decaying current pulses. The feedback analog signal Vfbis then filtered by the feedback low pass filter4which suppresses high frequency components carried by the feedback analog signal Vfbso as to produce the feedback signal Vffb. This feedback signal Vffbforces the digital signal Dout exiting the ADC converter200to track the average of the input analog signal Vin.

It is observed that the RC feedback low pass filter4introduces in the signal transfer function STF of the ADC converter200a passive pole p related to the capacitance of the capacitor CPand the resistance of the filter resistor RPaccording to the following expression:
p=−1/(RpCp)  (1)
In the present description electrical parameters (such as, capacitances and resistances) are indicated with the same symbols employed to identify the corresponding electrical components (i.e. resistors and capacitors) in the figures.

It is observed that the passive pole p associated with the feedback low pass filter4placed after the digital-to-analog converter3reduces considerably the requirements to the bandwidth and slew rate of the operational amplifier5, because, as already indicated, most of the high frequency components exiting the digital-to-analog converter3are already suppressed by feedback low pass filter4before they reach the operational amplifier5.

Moreover, it is observed that the feedback resistor RZ, placed in series to the feedback capacitor C, introduces a zero z in the signal transfer function of the ADC converter200:
z=−1/(RZC)  (2)
By designing the concerned electrical parameters (resistances and capacitances) so as that the product RZC is equal to product RpCp the additional zero z has the effect of compensating the pole p expressed by expression (1) so as to obtain a satisfying loop stability of the ADC converter and a noise transfer function NTF comparable to the ones associated to the prior art solution above described.

The first input resistor RP1, the second input resistor RP2and the input capacitor CP1act as an input low pass filter for the input analog signal Vinand introduce a further pole pPwhich can be expressed as:
pP=−1/(CP1(RP1//RP2))  (3)
wherein Rp1//Rp2indicated the total resistance for parallel electric connection:
RP1//RP2=RP1RP2/(RP1+RP2)
By designing the concerned electrical parameters (resistances and capacitances) so that the further pole pPof expression (3) is equal to the pole p of expression (1), high frequency components passing in the signal transfer function STF can be avoided.

Furthermore, to avoid noise amplification of the thermal noise associated with the filter resistor RPand the second input resistor RP2, the poles pPand p can be designed to show frequencies that are far outside the usable frequency band range of the ADC converter200. As an example, in the case of a fifth order ADC converter200with a bandwidth of 400 kHz and an oversampling ratio (OSR) of 100 (fCLK=40 MHz), the pole pPcould be placed at frequency of 4 MHz. In accordance with this particular example:
RP1=RP2=2 k Ohm; RP=RZ=1 kOhm; C=CP=CP1=40 pF.

With reference to the digital-to-analog converter3ofFIG. 3, it can be a pulse width modulator, a binary weighted digital-to-analog converter, a ladder network digital-to-analog converter or another type of suitable digital-to-analog converter. Particularly, the digital-to-analog converter3can be a ladder network converter operating in the current mode. The current mode technique allows the digital-to-analog converter3tolerating voltage swing on its output due to the passive pole p.

In accordance with a particular embodiment, the digital-to-analog converter3includes at least a one-bit return-to-zero converter16(FIG. 4) which is realized according the current mode technique and can be manufactured in a BiCMOS technology. The one-bit return-to-zero converter16comprises a differential pair circuit13having, as an example, the common emitter configuration. The differential pair circuit13is provided with a first current steering transistor T1and a second current steering transistor T2which are both NPN bipolar junction transistors (BJT). Each emitter terminal of the first current steering transistor T1and the second current steering transistor T2is connected to an anode of a diode14having its cathode connected to the ground GND.

A base terminal of the first current steering transistor T1is configured to receive the digital signal Dout (indicated inFIG. 4as signal Dout+) to be converted in analog form, while a base terminal of the second current steering transistor T2is configured to receive the opposite of the digital signal Dout, i.e. an inverted digital signal Dout−. The collector terminal of the first current steering transistor T1is structured to provide an analog current signal I+ representing the result of the digital-to-analog conversion of the digital signal Dout; the collector terminal of the second current steering transistor T2is structured to provide the a further analog current signal I−, i.e. the result of the conversion of the inverted digital signal Dout−.

Moreover, the described embodiment of the digital-to-analog converter3also includes a shaping filter circuit comprising a shaping resistor RDACconnected in series to a shaping capacitor CDACplaced between an input inverter15and the anode of the diode14. At the input inverter15a clock signal CLK can be fed.

Particularly, the analog-to-digital converter200including the digital-to-analog converter3ofFIG. 4is designed to produce a digital signal Dout+/− having a high level which is several hundred mV (e.g. 500 mV) smaller than two times the diode forward voltage associated with diode14, while the low level of the digital signal Dout+/− is an additional 200 mV smaller than the high level. This allows avoiding a quiescent current in the diode14and one of both first and second current steering transistors T1and T2.

When the clock signal CLK assumes a low level, the signal exiting the input inverter15assumes a high level so charging the shaping capacitor CADCvia the shaping resistor RDACand the diode14which is forward biased. In this situation, the first and second current steering transistors T1and T2are switched off. When the clock signal CLK assumes a high level, the signal exiting the input inverter15assumes a low level so allowing discharging of the shaping capacitor CADCvia the shaping resistor RDACand one of the first and second current steering transistors T1and T2. In the situation of a clock signal CLK having a high level, the voltage level associated with the digital signals Dout+/Dout− selectively switches off/on the first/second current steering transistors T1/T2so generating a corresponding current pulse I+/I−.

The shaping resistor RDACand the shaping capacitor CDAC, defining a time constant RDACCDAC, have a shaping effect which shapes the analog current pulse associated with the analog currents I+/I− to obtain either an exponential decaying shape if RDACCDAC<<1/fCLK or a nearly rectangular pulse if RDACCDAC>>1/fCLK. According to further examples, static high side current sources or a complementary high side structure can be added to the digital-to analog converter16to avoid residual static common mode currents.

To avoid distortion due to intersymbol interference, the transitions of the digital signal Dout+/Dout− are preferably timed during the low level of the clock signal CLK when both first and second current steering transistors T1and T2are switched off.

The one-bit return-to-zero converter16above described allows a large voltage swing at its output, while still providing a low noise output current due to the large degeneration via the shaping resistor RDAC. Furthermore, the amount of charge that is injected is independent of the duty cycle of the clock signal CLK, because the charge that is stored in the shaping capacitor CDACduring the lowphase of the clock signal CLK is equal to the charge that is removed from the shaping capacitor CDACduring the clock high phase. This allows designing the ADC converter200with a loop gain which is fully independent from the duty cycle of the clock signal CLK.

In accordance with another example, the digital-to-analog converter3includes an additional one-bit return-to-zero converter analogous to the one described with reference toFIG. 4, driven by the same output digital signal Dout+/Dout− but adapted to be timed by another clock signal having opposite polarity of the clock signal CLK. In this case, the output current pulses I+/I− of the one-bit return-to-zero converter16and the additional one-bit return-to-zero converter are added. For a large time constant RDACCDAC>>1/fCLK the two combined return-to-zero converters are in this way equivalent to one non-return-to-zero converter. These and other changes can be made to the embodiments in light of the above-detailed description

The described continuous time sigma-delta analog-to-digital converter allows employing operational amplifiers showing relaxed performances in comparison with the ones required by the sigma-delta analog-to-digital converter of the prior art.