Electronic package with narrow-factor via including finish layer

This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

TECHNICAL FIELD

The disclosure herein relates generally to electronic packages with vias and methods therefor.

BACKGROUND

Electronic packages, such as circuit boards and chip packages, often include a silicon die with input/output pads. Those pads may be soldered to other pads on a dielectric board. The pads on the board may be coupled to conductors within the board which may transmit electrical signals to and from the die, allowing for electrical connectivity between the silicon die and other devices by way of the board. Boards conventionally include multiple layers of conductors and other materials, such as ground planes, and the like. Vias may extend through the board to couple one layer to another.

DESCRIPTION OF EMBODIMENTS

Embedded bridge architecture may result in vias that are of such a size that, when the vias get relatively tall, such as by extending through multiple layers of the dielectric, the vias may induce relatively large amounts of stress on the pads. Such stress may result in cracking or delamination, such as on the pad or in the via. Additionally, relatively large vias may consume more material, such as copper, and may take up a larger footprint in the board, thereby increasing costs.

An architecture has been developed that may reduce via size while maintaining conventional via performance. Further, relative to conventional vias, the vias may consume less copper or other materials, may reduce solder bump cracking, may reduce via delamination, and may maintain first level interconnect (FLI) collapse. Unlike a conventional via, the via architecture is formed within a package insulator layer of the board and includes a conductor and a finish layer. The conductor extends vertically through at least some of the package insulator layer. In an example, the finish layer is secured to the conductor and includes a palladium-gold compound. In various alternative examples, the finish layer includes any of a variety of gold-based combinations, such as electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu). Additionally or alternatively, the finish layer may include or may be an organic solderabiliy preservative (OSP). As a result of the architecture, the via may be smaller than conventional vias, thereby reducing stress on the pads and improving reliability and, in various examples, reducing materials used, thereby reducing costs.

FIG. 1shows a side view of an electronic package100, in an example embodiment. The electronic package100may be a circuit board or electronic component onto which a silicon die may be coupled, such as to provide input/output to the silicon die.

The electronic package100includes package insulator layers102A,102B,102C (generically “package insulator layer102”). In various examples, the package insulator layer may be a buildup dielectric material or a solder resist. In an example, the buildup dielectric material is an Ajinomoto buildup film. The package insulator layer102may be substantially non-conductive and the various layers102A,102B,102C may be formed in sequence and in separate steps, each insulator layer102being substantially planar.

The electronic package100further includes a silicon bridge104embedded in one of the package insulator layers102C. The silicon bridge104may provide connectivity between various components such as multiple chips, including, but not limited to processor chips and memory chips, within or attached to the electronic package100. In an example, the silicon bridge104is fabricated, at least in part, from silicon. In an example, the silicon bridge104is fabricated, at least in part, from a ceramic, such as alumina. In an example, the silicon bridge104is fabricated, at least in part, from one or more organic interposers, including an organic material.

Vias106embedded within the package insulator layers102may provide electrical connectivity vertically through the package insulator layers102. In an example, a via106extends through one layer102, with multiple vias106(e.g., vias106A,106B,106C) stacking to extend through multiple layers102A,102B,102C. Each via106includes a conductor108. In various examples, some or all of the conductors108are comprised of nickel. Certain vias106A,106D,106E, include a finish layer110configured to interface between the via106generally and an external electrical component, such as a solder ball, a pin, and the like. Vias that are internal to the electronic package100and which do not interface with an external electrical component optionally do not include the finish layer110.

In various examples, the finish layer110is comprised of a gold-based compound. In an example, the gold-based compound is a palladium-gold compound. The compounds disclosed herein may be a heterogeneous mixture of materials or substantially homogeneous layers of such materials. In various alternative examples, the finish layer includes any of a variety of gold-based compounds and/or combinations, such as electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu). Additionally or alternatively, the finish layer110may include or may be an alternative noble metal based layer. Additionally or alternatively, the finish layer110may include or may be an organic solderabiliy preservative (OSP). The gold-based compound may be relatively unsusceptible to corrosion, and/or electron migration, such as in comparison with copper, or other materials conventionally used in via construction.

In an example, the finish layer110may be formed form a layer of electroless plated palladium and a layer of electroless plated gold which together may form the gold compound. In an example, the palladium layer is coupled to the conductor108and the gold layer is coupled or coupleable to a solder ball or other connector. Example dimensions may include that the palladium layer is approximately forty (40) nanometers thick and the gold layer is approximately sixty (60) nanometers thick.

The via106may be formed in the layer102into which the via106is to be embedded, plating the nickel conductor, such as with an eletroless plating process, and then by applying the finish layer110on the top of the conductor108. The vias106may provide connectivity between electrically conductive pads112, the silicon bridge104, and electronic components that may be coupled to the finish layers110, among other potential destinations. Each conductor108includes a first end114proximate an electrically conductive pad112and a second end116to which the finish layer110is secured.

In various examples, the vias106with the finish layer110, i.e., the vias106A,106D,106E, include the conductor108comprised of a first material while other vias106may include a conductor comprised of a second material different from the first material. In various examples, the first material is nickel and the second material is copper. In various alternative examples any of a variety of suitable materials may be utilized between the first and second materials.

The electronic package100may be in any of a variety of suitable dimensions for a variety of purposes. In an example implementation, the vias106A,106B,106C include conductors108having a top diameter118of forty-nine (49) micrometers. The conductors108A,108D,108E have a height120of seven (7) micrometers while the conductors108B,108C have heights122,124of twenty-seven (27) and twenty-five (25) micrometers, respectively. The pads112have a vertical thickness126of fifteen (15) micrometers and a horizontal width128of seventy-seven (77) micrometers. Other vias106D,106E have conductors108having a top diameter130of twenty-two (22) micrometers and a height132of seven (7) micrometers. In an example, the layer102A has a thickness134of twelve (12) micrometers from a top136of the pad108to the exterior surface138of the electronic package100. In an example, a separation140between pads108may be at least thirteen (13) micrometers. Pads142that optionally couple between the vias106F,106G and the silicon bridge104may have a width144of fifty (50) micrometers. The above dimensions are for example purposes only and are approximate based on circumstances and tolerances.

FIG. 2shows an electronic assembly200including a chip package202soldered to the electronic package100, in an example embodiment. The electronic assembly200illustrates an FLI architecture.

The chip package202includes a silicon die204and conductive pads206, for instance made of copper, coupled to the silicon die204. Solder balls208are or may be coupled to the conductive pads206and are coupleable to the finish layer110of the electronic package100. It is noted that the electronic assembly200is not fully formed, as illustrated. Rather, once the solder balls208are coupled to the finish layers110the electronic assembly200may be fully assembled in the illustrated example.

In the illustrated example, the chip package202further includes a wafer-level underflow layer210surrounding the conductive pads206and a capillary underfill layer212. Such layers210,212may provide stability and insulation for the chip package202. Such layers210,212may be omitted or supplemented by other layers for the same or other purposes.

In an example where the electronic package100includes the example dimensions provided above, the pads206and the wafer-level underflow layer210may have a thickness of approximately sixteen (16) micrometers. The solder ball208A and the capillary underfill layer212may have a thickness of from ten (10) to fifteen (15) micrometers. The solder balls208B,208C may have a thickness of approximately twenty (20) micrometers.

FIG. 3shows an example of an electronic package300, in an example embodiment. The electronic package300may be the same or similar to that of the electronic package100and further include solder balls302, such as paste printed solder, coupled to the finish layers110of the vias106. Thus, the electronic package300may be fully configured to couple to a chip package, such as the chip package202.

FIG. 4is a flowchart for using a microelectronic assembly, in an example embodiment. The microelectronic assembly may be the microelectronic assembly100or may be any microelectronic assembly that includes a temperature sensor102.

At operation400, an electrically conductive pad is formed. In an example, the pad is coupled to a silicon bridge.

At operation402, a package insulator layer including a substantially non-conductive material is formed, the package insulator layer being substantially planar. In an example, the package insulator layer comprises at least one of a buildup dielectric material and a solder resist. In an example, the buildup dielectric material is an Ajinomoto buildup film. In an example, the package insulator layer encloses, at least in part, the electrically conductive pad.

At operation404, a conductor of a via is formed extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end.

At operation406, a finish layer of the via is coupled to the second end of the conductor, the finish layer including a palladium-gold compound.

At operation408, a second via is formed electrically coupled between the via and the electrically conductive pad and enclosed, at least in part, by the package insulator layer. In an example, the conductor of the first via is comprised of a first material and the second via includes a conductor comprised of a second material different from the first material. In an example, the first material is nickel.

At operation410, a solder ball is coupled to the finish layer. In an example, the solder is configured to be electrically coupled to a connector of a silicon die.

An example of an electronic device using electronic assemblies as described in the present disclosure is included to show an example of a higher level device application for the disclosed subject matter.FIG. 5is a block diagram of an electronic device500incorporating at least one electronic assembly, such as an electronic package100or other electronic or microelectronic assembly related to examples herein. The electronic device500is merely one example of an electronic system in which embodiments of the present invention can be used. Examples of electronic devices500include, but are not limited to personal computers, tablet computers, mobile telephones, personal data assistants, MP3 or other digital music players, wearable devices, Internet of things (IOTS) devices, etc. In this example, the electronic device500comprises a data processing system that includes a system bus502to couple the various components of the system. The system bus502provides communications links among the various components of the electronic device500and can be implemented as a single bus, as a combination of busses, or in any other suitable manner.

An electronic assembly510is coupled to the system bus502. The electronic assembly510can include any circuit or combination of circuits. In one embodiment, the electronic assembly510includes a processor512which can be of any type. As used herein, “processor” means any type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), multiple core processor, or any other type of processor or processing circuit.

Other types of circuits that can be included in the electronic assembly510are a custom circuit, an application-specific integrated circuit (ASIC), or the like, such as, for example, one or more circuits (such as a communications circuit514) for use in wireless devices like mobile telephones, pagers, personal data assistants, portable computers, two-way radios, and similar electronic systems. The IC can perform any other type of function.

The electronic device500can also include an external memory520, which in turn can include one or more memory elements suitable to the particular application, such as a main memory522in the form of random access memory (RAM), one or more hard drives524, and/or one or more drives that handle removable media526such as compact disks (CD), digital video disk (DVD), and the like.

The electronic device500can also include a display device516, one or more speakers518, and a keyboard and/or controller530, which can include a mouse, trackconnection, touch screen, voice-recognition device, or any other device that permits a system user to input information into and receive information from the electronic device500.

Additional Examples

Example 1 may include subject matter (such as an apparatus, a method, a means for performing acts) that can include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via, formed within the package insulator layer, electrically coupled to the electrically conductive pad, the via including a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

In Example 2, the electronic package of Example 1 optionally further includes that the gold compound is a palladium-gold compound.

In Example 3, the electronic package of any one or more of Examples 1 and 2 optionally further includes that the gold compound is one of electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu).

In Example 4, the electronic package of any one or more of Examples 1-3 optionally further includes that the package insulator layer comprises at least one of a buildup dielectric material and a solder resist.

In Example 5, the electronic package of any one or more of Examples 1-4 optionally further includes that the buildup dielectric material is an Ajinomoto buildup film.

In Example 6, the electronic package of any one or more of Examples 1-5 optionally further includes that the package insulator layer encloses, at least in part, the electrically conductive pad.

In Example 7, the electronic package of any one or more of Examples 1-6 optionally further includes that the via is a first via and further comprising a second via electrically coupled between the via and the electrically conductive pad and enclosed, at least in part, by the package insulator layer.

In Example 8, the electronic package of any one or more of Examples 1-7 optionally further includes that the conductor of the first via is comprised of a first material and the second via includes a conductor comprised of a second material different from the first material.

In Example 9, the electronic package of any one or more of Examples 1-8 optionally further includes that the first material is nickel.

In Example 10, the electronic package of any one or more of Examples 1-9 optionally further includes a solder ball coupled to the finish layer.

In Example 11, the electronic package of any one or more of Examples 1-10 optionally further includes that the solder is configured to be electrically coupled to a connector of a silicon die.

In Example 12, the electronic package of any one or more of Examples 1-11 optionally further includes that the pad is coupled to a silicon bridge.

In Example 13, the electronic package of any one or more of Examples 1-12 optionally further includes that the silicon bridge is fabricated from at least one of silicon, ceramic, and an organic interposer.

Example 14 may include subject matter (such as an apparatus, a method, a means for performing acts) that can include forming an electrically conductive pad, forming a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, forming a conductor of a via extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end, and coupling a finish layer of the via to the second end of the conductor, the finish layer including a palladium-gold compound.

In Example 15, the method of Example 14 optionally further includes that the gold compound is a palladium-gold compound.

In Example 16, the method of any one or more of Examples 14 and 15 optionally further includes that the gold compound is one of electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu).

In Example 17, the method of any one or more of Examples 14-16 optionally further includes that the package insulator layer comprises at least one of a buildup dielectric material and a solder resist.

In Example 18, the method of any one or more of Examples 14-17 optionally further includes that the buildup dielectric material is an Ajinomoto buildup film.

In Example 19, the method of any one or more of Examples 14-18 optionally further includes that the package insulator layer encloses, at least in part, the electrically conductive pad.

In Example 20, the method of any one or more of Examples 14-19 optionally further includes that the via is a first via and further comprising forming a second via electrically coupled between the via and the electrically conductive pad and enclosed, at least in part, by the package insulator layer.

In Example 21, the method of any one or more of Examples 14-20 optionally further includes that the conductor of the first via is comprised of a first material and the second via includes a conductor comprised of a second material different from the first material.

In Example 22, the method of any one or more of Examples 14-21 optionally further includes that the first material is nickel.

In Example 23, the method of any one or more of Examples 14-22 optionally further includes a solder ball coupled to the finish layer.

In Example 24, the method of any one or more of Examples 14-23 optionally further includes that the solder is configured to be electrically coupled to a connector of a silicon die.

In Example 25, the method of any one or more of Examples 14-24 optionally further includes that the pad is coupled to a silicon bridge.

In Example 26, the method of any one or more of Examples 14-25 optionally further includes fabricating the silicon bridge from at least one of silicon, ceramic, and an organic interposer

Each of these non-limiting examples can stand on its own, or can be combined with one or more of the other examples in any permutation or combination.