Montgomery multiplier for RSA security module

A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a Montgomery multiplier, and more particularly, a Montgomery multiplier for an RSA security module secured from a differential power analysis attack.

2. Description of the Background Art

With the rapid growth of the internet and the electronic commerce, smart cards have been widely used as personal authentication solutions for the electronic commerce such as internet banking, electronic cash, medical cards and traffic cards. Because they can safely store personal information, personal keys and personal certificates, necessity and demand for the smart cards are increasing drastically. Especially, different from general magnetic cards, the smart cards containing microprocessors and memory functions show excellent physical security and safely store personal information. In addition, the smart cards can be used as multifunctional cards including memory, operation and security functions.

Generally public key encryption is applied to the smart cards and the RSA algorithm suggested by R. L. Rivest, A. Shamir and L. Adleman in 1978 has been known as the representative public key encryption.

The RSA encryption algorithm is performed by modular operations based on integers over 1024 bits. Security of the RSA encryption algorithm results from difficulty of factorization in prime factors of large integer coefficients. The RSA encryption algorithm is briefly explained as follows. Two different decimals ‘p’ and ‘q’ are designated as personal keys. The product of ‘p’ and ‘q’ n(=pq) and an arbitrary integer ‘e’ that is relatively prime from φ(n) are designated as public keys. Here, φ(n) represents a number of elements relatively prime from ‘n’. In addition, ‘d’ satisfying e·d=1 (mod φ(n)) is calculated and used as a personal key. That is, ‘p’, ‘q’ and ‘d’ are personal keys and ‘n’ and ‘e’ are public keys.

In encryption, a plain text M is calculated as an encrypt text C=Memod n by using the public key ‘e’, and calculated as a decrypt text M=Cdmod n. As described above, the RSA security module performs encryption and decryption by taking modular exponentiation to the pubic or personal key. The modular exponentiation is consecutive modular multiplications and the modular multiplication is consecutive additions. Normally used is a Montgomery algorithm that does not have to consider carry delay in the operation. For example, a Montgomery multiplier actually performs ABR−1mod N instead to calculate AB mod N, wherein R is an integer relatively prime from N and larger than N.

However, side channel information that is not considered in encryption algorithm design for the smart cards exists. The side channel information is classified into time differential information showing time operation differences in an operation of a microprocessor, signal information leaked from a power line, mis-operation information caused by defect inputs, and information by electromagnetic leakage, and etc.

Smart card attack techniques by side channels are generally called side channel attacks, and divided into a time differential attack by time differential information, an defect input attack by defect mis-operation information, an electromagnetic leakage attack by the electromagnetic leakage information, and a power analysis attack by power line leakage information.

Here, the power analysis attack means a password decryption technique by which binary codes of various information is read by measuring instantaneous voltage (power) variations of an IC chip when an encryption algorithm and a secret key for encryption built in the card start to operate, and important information is analyzed according to a statistical method, and forged/modulated as well. The power analysis attack is classified into a simple power analysis attack, a differential power analysis attack, an inference power analysis attack and a high-degree differential power analysis attack. Especially, the differential power analysis attack can estimate the secret key merely by using a few devices for measuring voltage variations. Accordingly, the differential power analysis attack is deemed to be more efficient than a brute-force attack using an exclusive encryption device or a super computer.

FIGS. 1A and 1Bare circuit diagrams illustrating a structure and operation of a synchronous XOR circuit generally applied to the Montgomery multiplier.

Referring toFIG. 1A, an XOR gate10receives two input signals AIN—TRUEand BIN—TRUEas shown in Table 1. When the two input values are different, the XOR gate10outputs a logical high value, and when the two input values are identical, the XOR gate10outputs a logical low value.

InFIG. 1B, the gate-level synchronous XOR circuit ofFIG. 1Ais designed in a transistor level.

As illustrated inFIG. 1B, the synchronous XOR circuit includes the first P type transistor P101and the first N type transistor N101driven by the first input signal A1and connected in series between a power supply node and a ground node, the second P type transistor P102and the second N type transistor N102driven by the voltage applied to the output node of the first P type transistor P101and connected in series between the power supply node and the ground node, the third P type transistor P103and the third N type transistor N103driven by the second input signal A2and connected in series between the power supply node and the ground node, the fourth P type transistor P104driven by the voltage applied to the output node of the third P type transistor P103and receiving the voltage applied to the output node of the second P type transistor P102, the fourth N type transistor N104driven by the second input signal A2and receiving the voltage applied to the output node of the second P type transistor P102, the fifth P type transistor P105driven by the second input signal A2and receiving the voltage applied to the output node of the first P type transistor P101, the fifth N type transistor P105driven by the voltage applied to the output node of the third P type transistor P103and receiving the voltage applied to the output node of the first P type transistor P101, and the sixth P type transistor P106and the sixth N type transistor N106driven by the voltage applied to the output node of the fourth P and N type transistors P104and N104and the output node of the fifth P and N type transistors P105and N105, and connected in series between the power supply node and the ground node. The output node of the sixth P type transistor P106outputs the final output value.

Still referring toFIG. 1B, when the output value OUTTRUEis low, five of the ten transistors are turned on, but when the output value OUTTRUEis high, three of them are turned on. That is, in the synchronous XOR circuit, the number of the switched transistors is changed according to the input values, and thus power consumption is changed. Such power difference makes the module weak to the differential power analysis attack.

Required is an operation logic for solving the problems of the synchronous XOR circuit applied to the Montgomery multiplier, and minimizing correlations between internally-operated binary data and power consumption patterns.

FIG. 2shows a data representation method by a synchronous single line method and an asynchronous double line method.

By the synchronous single line method, the data is represented as logical high or low states according to binary data ‘0’ or ‘1’. For example, as shown inFIG. 2, data ‘0100110’ represents, three logical high states and four logical high states according to input of a clock signal.

On the other hand, by the asynchronous double line method, two lines DATAFALSEand DATATRUEare used to represent one binary data. In order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSEline, and a logical low signal is applied to the DATATRUEline. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSEline, and a logical high signal is applied to the DATATRUEline.

In the case that the data is represented by the asynchronous double line method, whatever the binary data value is, the same number of logical high states and logical low states are generated. Accordingly, whatever binary data is to be operated, power consumption difference of the circuit is minimized.

When the RSA security module is formed by using the aforementioned characteristics of the asynchronous double line method, the differential power analysis attack can be defended.

FIGS. 3A to 3Care circuit diagrams illustrating a structure and operation of an asynchronous XOR circuit.

As shown inFIG. 3A, all items that can be generated by two input binary data AIN—TRUE, AIN—FALSE, BIN—TRUEand BIN—FALSEare generated by C-element devices20,22,24and26, and the outputs from the C-element devices20,22,24and26are combined by OR gates30and32.

FIG. 3Bis an exemplary diagram illustrating transistor-level design of the C-element devices20,22,24and26ofFIG. 3A. The C-element device20includes the first to the fifth P type transistors P201, P202, P203, P204and P205, and the first to the fifth N type transistors N201, N202, N203, N204and N205.FIG. 3Cis an exemplary diagram illustrating transistor-level design of the OR gates30and32ofFIG. 3A. The OR gate30is driven by the output signals C1and C2from the two C-element devices20and22, and includes the first to the third P type transistors P301, P302and P303and the first to the third N type transistors N301, N302and N303.

In the asynchronous XOR circuit, the number of the switched transistors is not changed according to the input values. However, since excessively many C-element devices are used, large space for the circuit is needed.

SUMMARY OF THE INVENTION

The present invention is achieved to solve the above problems. Accordingly, it is an object of the present invention to provide a Montgomery multiplier which is secured from a differential power analysis attack and to reduce the size in design of an RSA security module.

In order to achieve the above-described object of the invention, there is provided a Montgomery multiplier for an RSA security module, including: the first filtering means for receiving the first input signal and the second input signal represented by an asynchronous double line method, and selectively outputting the second input signal according to a logical value of the first input signal; the first carry save adder for outputting a sum and a carry of double line method by adding up a carry signal and a sum signal generated in a previous calculation procedure and the output signal from the first filtering means; the second filtering means for receiving a logical value of a least significant sum of the first carry save adder as the third input signal and a modular operation factor as the fourth signal, and filtering the fourth input signal according to the third input signal; the second carry save adder for generating a sum and a carry of double line method, by adding up the carry and the sum outputted from the first carry save adder and the output from the second filtering means; a carry storing means and a sum storing means for storing the carry and the sum from the second carry save adder; a carry propagation adder for calculating the final result by adding up the data stored in the carry storing means and the sum storing means; and an operation completion sensing means for deciding operation completion according to the output signal from the second carry save adder.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A Montgomery multiplier for an RSA security module in accordance with a preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 4is a circuit diagram illustrating the structure of the Montgomery multiplier in accordance with the present invention. The Montgomery multiplier actually performs ABR−1mod N instead to calculate AB mod N. wherein R is an integer relatively prime from N and larger than N.

The Montgomery multiplier100includes the first filtering means110for receiving the first input signal A and the second input signal B, and selectively outputting the second input signal B according to a logical value of the first input signal A, the first carry save adder130for outputting a sum and a carry of double line method by adding up a carry signal generated in a previous calculation procedure, the output signal from the first filtering means110and a sum signal generated in a previous calculation procedure, the second filtering means120for receiving a logical value of a least significant sum of the first carry save adder130as the first input signal and a modular operation factor N as the second input signal, and filtering the second input signal that is the modular operation factor N according to the first input signal, the second carry save adder132for generating a sum and a carry of double line method, by adding up the carry and the sum from the first carry save adder130and the output from the second filtering means120, a carry storing means140and a sum storing means150for storing the carry and the sum from the second carry save adder132, a carry propagation adder170for calculating the final result by adding up the data stored in the carry storing means140and the sum storing means150, an operation completion sensing means160for deciding operation completion, and a controller180for controlling the whole operation.

When the logical value of the first input signal A is ‘1’ (‘10’ in double line representation), the first filtering means110outputs the second input signal B as the resultant value, when the logical value of the first input signal A is ‘0’ (‘01’ in double line representation), the first filtering means110outputs logical 0 (‘01’ in double line representation), and when the logical value of the first input signal A does not exist (NO DATA), the first filtering means110outputs logical NO DATA regardless of the second input signal B. The second filtering means120receives the least significant data of the first carry save adder130as the first input signal and the modular operation factor N as the second signal, and operates in the same manner as the first filtering means110.

FIGS. 5A to 5Care circuit diagrams illustrating the structure and operation of the filtering means in accordance with the present invention.

As illustrated inFIG. 5A, each of the filtering means110and120includes the first logical element40for outputting a high signal only when two binary data AIN—TRUEand BIN—TRUEinputted to a DATATRUEline are logical high, and the second logical element50for outputting a low signal only when two binary data AIN—FALSEand BIN—FALSEinputted to a DATAFALSEline are logical low. Here, the first logical element40can be comprised of an AND gate and the second logical element50can be comprised of an OR gate.

InFIG. 5B, the first logical element40ofFIG. 5Ais designed in a transistor level. The first logical element40includes the first and the second P type transistors P401and P402connected in parallel to a power supply node and driven by the first input signal A1and the second input signal B1, respectively, the first and the second N type transistors N401and N402connected in series between the output node of the first and the second P type transistors P401and P402and a ground node, and driven by the first input signal A1and the second input signal B1, respectively, and the third P type transistor P403and the third N type transistor N403driven by the voltage applied to the output node of the first and the second P type transistors P401and P402, and connected in series between the power supply node and the ground node. The voltage applied to the output node of the third P type transistor P403becomes the output signal from the whole circuit.

In the transistor-level circuit of the first logical element40ofFIG. 5B, when the two input signals A1and B1are ‘0’ and ‘1’ respectively, the first P type transistor P401, the second N type transistor N402and the third N type transistor N403are turned on, and the other three transistors P402, N401and P403are turned off. In addition, when the two input signals A1and B1are ‘1’ and ‘1’, the first N type transistor N401, the second N type transistor N402and the third P type transistor P403are turned on, and the other three transistors P401, P402and N403are turned off. That is, the number of the switched transistors is not influenced by the input signals.

InFIG. 5C, the second logical element50ofFIG. 5Ais designed in a transistor level. The second logical element50includes the fourth P type transistor P501connected to a power supply node and driven by the third input signal A2and the fourth input signal B2, the fifth P type transistor P502connected in series to the fourth P type transistor P501, the fourth and the fifth N type transistors N501and N502connected in parallel between the fifth P type transistor P502and a ground node and driven by the third input signal A2and the fourth input signal B2, respectively, and the sixth P type transistor P503and the sixth N type transistor N503driven by the voltage applied to the output node of the fifth P type transistor P502and connected in series between the power supply node and the ground node. The voltage applied to the output node of the sixth P type transistor P503becomes the output signal of the whole circuit.

In the transistor-level circuit of the second logical element50, when the two input signals A2and B2are ‘0’ and ‘1’ respectively, the fourth P type transistor P501, the fifth N type transistor N502and the sixth P type transistor P503are turned on, and the other transistors P502, N501and N503are turned off. In addition, when the two input signals A2and B2are ‘1’ and ‘1’, the fourth N type transistor N501, the fifth N type transistor N502and the sixth P type transistor P503are turned on, and the other transistors P501, P502and N503are turned off. That is, the number of the switched transistors is not influenced by the input signals.

The operation of the filtering means110and120ofFIG. 5Awill now be explained.

In accordance with the asynchronous double line method, logical data ‘0’ is represented as ‘01’, and logical data ‘1’ is represented as ‘10’. Table 2 shows the output values of the filtering means110and120in regard to the two input binary data (actually, four data).

Referring toFIG. 5A, when two logical data ‘01’ are inputted, namely, when AIN—TRUEis ‘0’, AIN—FALSEis ‘1’, BIN—TRUEis ‘1’ and BIN—FALSEis ‘0’, the output signal OUTTRUEfrom the first logical element40is ‘0’ and the output signal OUTFALSEfrom the second logical element50is ‘1’. That is, the logical data ‘0’ is outputted. In addition, when two logical data ‘11’ are inputted, namely, when AIN—TRUEis ‘1’, AIN—FALSEis ‘0’, BIN—TRUEis ‘1’ and BIN—FALSEis ‘0’, the output signal OUTTRUEfrom the first logical element40is ‘1’ and the output signal OUTFALSEfrom the second logical element50is ‘0’. That is, the logical data ‘1’ is outputted.

As described above, when the first input signal A is logical ‘1’, the filtering means110and120output the second input signal B as it is, and when the first input signal A is logical ‘0’, the filtering means110and120output logical ‘0’, and when the data is not inputted to the first input signal A (NO DATA), the filtering means110and120output logical NO DATA, thereby filtering and outputting the second input signal B.

The first and the second carry save adders130and132and the carry propagation adder170will now be described.

The first and the second carry save adders130and132and the carry propagation adder170can be comprised of full adders for adding up the two input binary data A and B and the carry signal Cin generated in the previous adding up procedure. The full adders are represented by the following formula 1:

The AND and OR operations required in formula 1 can be performed by the circuits ofFIGS. 5B and 5C.FIG. 6shows gate-level and transistor-level design for the XOR operation.

FIGS. 6A to 6Care circuit diagrams illustrating the structure and operation of the XOR circuit in accordance with the present invention.

As depicted inFIG. 6A, the XOR circuit includes the first operation unit60for receiving two binary signals (actually, four signals), and outputting ‘0’ when the two binary signals are identical, and the second operation unit70for outputting ‘1’ when the two binary signals are different.

The first operation unit60includes the third logical element610for receiving the TRUE signal AIN—TRUEof the first input signals A and the FALSE signal BIN—FALSEof the second input signals B, and outputting ‘0’ when the two input signals are logical ‘0’, the fourth logical element620for receiving the FALSE signal AIN—FALSEof the first input signals A and the TRUE signal BIN—TRUEof the second input signals B, and outputting ‘0’ when the two input signals are logical ‘0’, and the fifth logical element630for receiving the output signals from the third and the fourth logical elements610and620, and outputting ‘1’ when the input signals are ‘1’. Here, the output from the fifth logical element630becomes the FALSE output from the asynchronous double line method XOR circuit.

The second operation unit70includes the sixth logical element710for receiving the FALSE signal AIN—FALSEof the first input signals A and the TRUE signal BIN—TRUEof the second input signals B, and outputting ‘1’ when the two input signals are logical ‘1’, the seventh logical element720for receiving the TRUE signal AIN—TRUEof the first input signals A and the FALSE signal BIN—FALSEof the second input signals B, and outputting ‘1’ when the two input signals are logical ‘1’, and the eighth logical element730for receiving the output signals from the sixth and the seventh logical elements710and720, and outputting ‘0’ when the input signals are ‘0’. Here, the output from the third logical element780becomes the TRUE output from the asynchronous double line method XOR circuit.

Here, the third logical element610, the fourth logical element620and the eighth logical element730can be comprised of OR gates, and the fifth logical element630, the sixth logical element710and the seventh logical element720can be comprised of AND gates.FIGS. 5B and 5Cshow the transistor-level design thereof.

Table 3 shows a truth table of the XOR circuit ofFIG. 6A.

FIG. 6Bis an exemplary diagram illustrating transistor-level design of the first operation unit60ofFIG. 6A.

As shown inFIG. 6B, the first operation unit60includes the seventh P type transistor P601connected to a power supply node and driven by the first input signal A1, the eighth P type transistor P602connected in series to the seventh P type transistor P601and driven by the second input signal B1, the seventh N type transistor N601connected in series to the eighth P type transistor P602and driven by the second input signal B1, the eighth N type transistor N602connected between the seventh N type transistor N601and a ground node and driven by the fourth input signal B2, the ninth P type transistor P603connected to the power supply node and driven by the third input signal A2, the tenth P type transistor P604connected in series to the ninth P type transistor P603and driven by the fourth input signal B2, the ninth N type transistor N603connected in series between the tenth P type transistor P604and the seventh N type transistor N601and driven by the first input signal A1, the tenth N type transistor N604connected between the ninth N type transistor N603and the ground node and driven by the third input signal A2, and the 11thP and N type transistors P605and N605driven by the voltage applied to the eighth and the tenth P type transistors P602and P604and connected in series between the power supply node and the ground node. The voltage applied to the output node of the 11thP type transistor P605becomes the final output signal.

FIG. 6Cis an exemplary diagram illustrating transistor-level design of the second operation unit70ofFIG. 6A.

As illustrated inFIG. 6C, the second operation unit70includes the 12thP type transistor P701conriected to the power supply node and driven by the first input signal A1, the 13thP type transistor P702connected in series to the 12thP type transistor P701and driven by the second input signal B1, the 12thN type transistor N701connected in series to the 13thP type transistor P702and driven by the third input signal A2, the 13thN type transistor N702connected between the 12thN type transistor N701and the ground node and driven by the first input signal A1, the 14thP type transistor P703connected between the power supply node and the output node of the 12thP type transistor P701and driven by the third input signal A2, the 15thP type transistor P704connected in series to the 14thP type transistor P703and driven by the fourth input signal B2, the 14thN type transistor N703connected in series to the 15thP type transistor P704and driven by the fourth input signal B2, the 15thN type transistor N704connected in series between the 14thN type transistor N703and the ground node and driven by the second input signal B1, and the 16thP and N type transistors P705and N705driven by the voltage applied to the 13thand the 15thP type transistors P702and P704and connected in series between the power supply node and the ground node. The voltage applied to the output node of the 16thP type transistor P705becomes the final output signal.

In the first and the second operation units60and70ofFIGS. 6B and 6C, the number of the switched transistors is always identical regardless of the input signals.

For example, when ‘0110’ are inputted as the first to the fourth input signals ofFIG. 6B, the seventh P type transistor P601, the tenth P type transistor P604, the 11thP type transistor P605, the seventh N type transistor N601and the tenth N type transistor N604are turned on, and the other transistors are turned off. In addition, when ‘1001’ are inputted as the first to the fourth input signals, the seventh P type transistor P601, the tenth P type transistor P604, the 11thP type transistor P605, the seventh N type transistor N601and the tenth N type transistor N604are turned off, and the other transistors are turned on.

On the other hand, when ‘0110’ are inputted as the first to the fourth input signals ofFIG. 6C, the 12thP type transistor P701, the 15thP type transistor P704, the 16thP type transistor P705, the 12thN type transistor N701and the 15thN type transistor N704are turned on, and the other transistors are turned off. In addition, when ‘1001’ are inputted as the first to the fourth input signals, the 12thP type transistor P701, the 15thP type transistor P704, the 16thP type transistor P705, the 12thN type transistor N701and the 15thN type transistor N704are turned off, and the other transistors are turned on.

FIG. 7is a circuit diagram illustrating the structure and operation of the operation completion sensing means in accordance with the present invention.

The operation completion sensing means160includes a plurality of the ninth logical elements80-1to80-N for receiving the carry and sum from the second carry save adder132by repetitive multiplications, and confirming whether they are correct or not, and the tenth logical element90for checking validity of the whole data by integrating the resultant values of the ninth logical elements80-1to80-N. Here, the ninth logical elements80-1to80-N can be comprised of OR gates for outputting ‘0’ only when the two input signals are ‘0’, and the tenth logical element90can be comprised of an AND gate for outputting ‘1’ only when all input signals are ‘1’. Such logical elements can be embodied as shown inFIGS. 5B and 5C.

As discussed earlier, in accordance with the present invention, the Montgomery multiplier for the RSA security module can prevent hacking by the differential power analysis attack, by minimizing power consumption difference by the input data.

Moreover, the Montgomery multiplier can compose an area-efficient circuit, by representing the data using the asynchronous double line method and minimizing the number of the used transistors.