GATE-ALL-AROUND DEVICE AND METHOD FOR FABRICATING THE SAME

Provided is a gate-all-around device. The gate-all-around device includes a substrate, a pair of heterojunction source/drain regions provided on the substrate, a heterojunction channel region provided between the pair of heterojunction source/drain regions, and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively. Each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers. The pair of ohmic electrodes extends toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application Nos. 10-2017-0115461, filed on Sep. 8, 2017, and 10-2018-0005714, filed on Jan. 16, 2018, the entire contents of which are hereby incorporated by reference herein.

BACKGROUND

The present inventive concepts relates to a gate-all-around device and a method of fabricating the same.

Gallium nitride (GaN), which is a nitride semiconductor, is a direct transition semiconductor, and has a high field electron transfer rate (e.g., 2×107cm/s) and a high heat transfer breakdown field (e.g., 3×106V/cm) and a high band gap (e.g., 3.4 eV), and forms a heterojunction structure with aluminum gallium nitride (AlGaN) to provide a high electron density on a two-dimensional scale, so that high electron mobility transistor (HEMT) may be formed, which is widely used in applications requiring high temperature and high frequency and high output.

SUMMARY

Some embodiments of the present inventive concepts provide a gate-all-around device with improved electrical characteristics and reliability.

Some embodiments of the present inventive concepts provide a method of fabricating a gate-all-around device having improved process difficulty and reliability.

According to example embodiments of the present inventive concepts, a gate-all-around device including: a substrate; a pair of heterojunction source/drain regions provided on the substrate; a heterojunction channel region provided between the pair of heterojunction source/drain regions; and a pair of ohmic electrodes provided on the pair of heterojunction source/drain regions, respectively, wherein each of the pair of heterojunction source/drain regions includes a pair of two-dimensional electron gas layers, and the pair of ohmic electrodes may extend toward an upper surface of the substrate and pass through the pair of heterojunction source/drain regions, respectively.

In some exemplary embodiments, each of the pair of ohmic electrodes may be electrically connected to the pair of two-dimensional electron gas layers.

In some exemplary embodiments, each of the pair of heterojunction source/drain regions may include: a pair of first nitride semiconductor films spaced apart from each other along a direction perpendicular to the upper surface of the substrate; and a second nitride semiconductor film interposed between the pair of first nitride semiconductor films.

In some exemplary embodiments, the gate-all-around device may further include: an insulating layer interposed between each of the pair of heterojunction source/drain regions and the substrate; and an air gap provided between the heterojunction channel region and the substrate.

In some exemplary embodiments, the heterojunction channel region may include: a second nitride semiconductor film extending in the first direction; and a first nitride semiconductor film surrounding the second nitride semiconductor film.

In some exemplary embodiments, the gate-all-around device may further include a gate electrode surrounding the heterojunction channel region, wherein the first nitride semiconductor film may be interposed between the second nitride semiconductor film and the gate electrode.

In some exemplary embodiments, each of the gate electrode and the heterojunction channel region may be provided in plural, and the plurality of gate electrodes may surround the plurality of heterojunction channel regions.

According to example embodiments of the present inventive concepts, a method of fabricating a gate-all-around device includes: forming a first nitride semiconductor film and a second nitride semiconductor film sequentially stacked on a substrate; sequentially patterning the second nitride semiconductor film and the first nitride semiconductor film to form a first recess region and a second recess region; forming a third nitride semiconductor film on an upper surface of the second nitride semiconductor film and side surfaces of the first and second nitride semiconductor films exposed by each of the first and second recess regions; forming a gate electrode on the first and third nitride semiconductor films disposed between the first and second recess regions; and forming first and second ohmic electrodes on the third nitride semiconductor film, the first and second ohmic electrodes being spaced apart from each other in a first direction parallel to an upper surface of the substrate with the gate electrode therebetween.

In some exemplary embodiment, the method may further include: forming an insulating layer interposed between the first nitride semiconductor film and the substrate; and providing an etchant into the first and second recess regions to remove the insulating layer disposed between the first and second recess regions, wherein the insulating layer may be removed to form an air gap between the first nitride semiconductor film and the substrate.

In some exemplary embodiment, the gate electrode may cover an upper surface of the third nitride semiconductor film and extend along surfaces of the third nitride semiconductor film exposed by the first recess region, the air gap, and the second recess region.

In some exemplary embodiment, the forming of the first and second ohmic electrodes may include: forming third recessed regions penetrating the first to third nitride semiconductor films on both sides of the gate electrode; and depositing metals on the third nitride semiconductor film to fill the third recess regions.

DETAILED DESCRIPTION

In order to fully understand the configuration and effects of the technical spirit of the inventive concept, preferred embodiments of the technical spirit of the inventive concept will be described with reference to the accompanying drawings. However, the technical spirit of the inventive concept is not limited to the embodiments set forth herein and may be implemented in various forms and various modifications may be applied thereto. Only, the technical spirit of the inventive concept is disclosed to the full through the description of the embodiments, and it is provided to those skilled in the art that the inventive concept belongs to inform the scope of the inventive concept completely.

Like reference numerals refer to like elements throughout the specification. Embodiments described herein will be described with reference to a perspective view, a front view, a sectional view, and/or a conceptual view, which are ideal examples of the technical idea of the inventive concept. In the drawings, the thicknesses of areas are exaggerated for effective description. Areas exemplified in the drawings have general properties, and are used to illustrate a specific shape of a semiconductor package region. Thus, this should not be construed as limited to the scope of the inventive concept. It will be understood that various terms are used herein to describe various components but these components should not be limited by these terms. These terms are just used to distinguish a component from another component. Embodiments described herein include complementary embodiments thereof.

The terms used in this specification are used only for explaining specific embodiments while not limiting the inventive concept. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of “comprises,” and/or “comprising” in this specification specifies the mentioned component but does not exclude at least one another component.

Hereinafter, preferred embodiments of the technical spirit of the inventive concept are described with reference to the accompanying drawings so that the inventive concept is described in more detail.

Referring toFIG. 1, an auxiliary buffer layer20may be formed on an auxiliary substrate10. In the exemplary embodiments, the auxiliary substrate10may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

The auxiliary buffer layer20may be formed by a chemical vapor deposition (CVD) process (for example, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process (e.g., a sputtering process), or an atomic layer deposition (ALD) process. The auxiliary buffer layer20may include a nitride semiconductor material. For example, the auxiliary buffer layer20may include GaN.

An auxiliary barrier layer30may be formed on the auxiliary buffer layer20. The auxiliary barrier layer30may be formed by a chemical vapor deposition (CVD) process (for example, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process (e.g., a sputtering process), or an atomic layer deposition (ALD) process. The auxiliary barrier layer30may include a semiconductor material that contacts the auxiliary buffer layer20to form a two-dimensional electron gas layer (not shown). For example, the auxiliary barrier layer30may include AlGaN.

An auxiliary insulating layer40may be formed on the auxiliary barrier layer30. The auxiliary insulating layer40may be formed by a chemical vapor deposition (CVD) process (for example, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process (e.g., a sputtering process), or an atomic layer deposition (ALD) process. The auxiliary insulating layer40may include an insulating material. For example, the auxiliary insulating layer40may include silicon oxide (e.g., SiO2).

A micro-cavity layer22may be formed in the auxiliary buffer layer20. The micro-cavity layer22may be a part which is separated in the transfer process described below. The micro-cavity layer22may be a part which is separated in the transfer process described below. For example, hydrogen ions may be implanted into the auxiliary buffer layer20through the auxiliary insulating layer40and the auxiliary barrier layer30by an ion implantation process.

Referring toFIGS. 2 and 3, an insulating layer200may be provided on the substrate100. In the exemplary embodiments, the substrate100may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

The insulating layer200may be formed by a chemical vapor deposition (CVD) process (for example, a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process (e.g., a sputtering process), or an atomic layer deposition (ALD) process. The insulating layer200may include an insulating material. For example, the insulating layer200may include silicon oxide (e.g., SiO2).

The auxiliary buffer layer20disposed on the micro-cavity layer22, the auxiliary barrier layer30, and the auxiliary insulating layer40may be transferred onto the insulating layer200on the substrate100. The transferring process may include separating the upper auxiliary buffer layer24and the lower auxiliary buffer layer26through a first heat treatment on the auxiliary buffer layer20, contacting the auxiliary insulating layer40to the insulating layer200, and bonding the insulating layer200and the auxiliary insulating layer40through a second heat treatment thereon. The boundary between the upper and lower auxiliary buffer layers24and26may be a micro-cavity layer22. For example, the first heat treatment process may include heating the auxiliary buffer layer20to about 400° C. to about 600° C. For example, the second heat treatment process may include heating the auxiliary insulating layer40and the insulating layer200to about 1100° C.

The insulating layer200and the auxiliary insulating layer40may include substantially the same material. Accordingly, the insulating layer200and the auxiliary insulating layer40may be a single structure having no boundary. Hereinafter, the structure in which the insulating layer200and the auxiliary insulating layer40are combined is referred to as an insulating layer200, the auxiliary barrier layer30is referred to as a first nitride semiconductor film310, and the upper auxiliary buffer layer24is referred to as a second nitride semiconductor film320.

Due to the difference in lattice constant between the first nitride semiconductor film310and the second nitride semiconductor film320, the first two-dimensional electron gas layer DEG1may be formed in the second nitride semiconductor film320. The first two-dimensional electron gas layer DEG1may be provided under the second nitride semiconductor film320adjacent to the first nitride semiconductor film310.

Referring toFIGS. 4A, 4B, and 4C, the second nitride semiconductor film320, the first nitride semiconductor film310, and the insulating layer200may be patterned. The patterning process may include forming a photoresist pattern (not shown) on the second nitride semiconductor film320and sequentially etching the second nitride semiconductor film320, the first nitride semiconductor film310, and the insulating layer200by performing an etching process using the photoresist pattern as an etching mask. The etch process may include a wet etch process, a dry etch process, or a combination of a wet etch process and a dry etch process. For example, the etching process may include performing an electron cyclotron resonance (ECR) plasma etching process or an inductively coupled plasma (ICP) etching process using CF4gas, BCl3gas, Cl2gas, or SF6gas. In the etching process, the insulating layer200may function as an etch stop layer.

The first heterojunction source/drain region SD1, the heterojunction channel regions CH, and the second heterojunction source/drain region SD2, which are arranged in a first direction parallel to the upper surface of the substrate100, may be formed by the patterning process. The first and second heterojunction source/drain regions SD1and SD2may include a first nitride semiconductor film310and a second nitride semiconductor film320. Each of the first and second heterojunction source/drain regions SD1and SD2may extend in a second direction D2that is parallel to the upper surface of the substrate100but intersects the first direction D1. Each of the heterojunction channel regions CH extends along the first direction D1between the first and second heterojunction source/drain regions SD1and SD2to directly contact the first and second heterojunction source/drain regions SD1and SD2. The heterojunction channel regions CH may be arranged along the second direction D2.

The first recess region R1and the second recess region R2may be formed by the patterning process. The first and second recess regions R1and R2may be arranged in the second direction D2. Each of the first and second recess regions R1and R2may be disposed between a pair of adjacent heterojunction channel regions CH. Each of the first and second recess regions R1and R2extends through the second nitride semiconductor film320, the first nitride semiconductor film310, and the insulating layer200, thereby exposing the upper surface of the substrate100. However, this is an exemplary one. In other exemplary embodiments, the patterning process is performed until the insulating layer200is penetrated so that the upper surface of the insulating layer200may exposed by the first and second recess regions R1and R2.

Referring toFIGS. 5A, 5B, and 5C, the insulating layer200interposed between the heterojunction channel regions CH and the substrate100may be removed. In the exemplary embodiments, removing the insulating layer200may include performing a wet etch process that provides an etchant to the insulating layer200through the first and second recess regions R1and R2. For example, the etchant may include a fluorochemical material.

By the wet etching process, air gaps AG may be provided between the heterojunction channel regions CH and the substrate100. The air gaps AG may expose the upper surface of the substrate100and the bottom surface of the first nitride semiconductor film310. The air gaps AG may be connected to the first and second recess regions R1and R2.

Referring toFIGS. 6A, 6B, and 6C, a third nitride semiconductor film330may be formed on the second nitride semiconductor film320. In the exemplary embodiments, forming the third nitride semiconductor film330may include performing a Metal Organic Chemical Vapor Deposition (MOCVD) process. The third nitride semiconductor film330may include substantially the same material as the first nitride semiconductor film310. For example, the third nitride semiconductor film330may include AlGaN. Due to the difference in lattice constant between the third nitride semiconductor film330and the second nitride semiconductor film320, the second two-dimensional electron gas layer DEG2may be formed in the second nitride semiconductor film320. The second two-dimensional electron gas layer DEG2may be provided on the second nitride semiconductor film320and may be adjacent to the third nitride semiconductor film330.

The third nitride semiconductor film330may cover the upper surface of the second nitride semiconductor film320and extend into the first and second recess regions R1and R2. The third nitride semiconductor film330may cover the side surfaces of the first and second nitride semiconductor films310and320exposed by the first and second recess regions R1and R2. The first and third nitride semiconductor films310and330may surround the second nitride semiconductor film320. The first and third nitride semiconductor films310and330may be a single film having no boundary. Accordingly, each of the first and second heterojunction source/drain regions SD1and SD2and the heterojunction channel regions CH may include the first and third nitride semiconductor films310and330surrounding the second nitride semiconductor film320and the second nitride semiconductor film320. For example, each of the first and second heterojunction source/drain regions SD1and SD2and the heterojunction channel regions CH may include a GaN film and an AlGaN film surrounding the GaN film.

Generally, a gate-all-around device may include one two-dimensional electron gas layer. The second nitride semiconductor film320according to the concept of the inventive concept may include two two-dimensional electron gas layers interposed between the first and third nitride semiconductor films310and330. Thus, the electrical characteristics of the gate-all-around device may be improved.

Referring toFIGS. 7A, 7B, 7C, and 7D, gate electrodes GE may be formed on the heterojunction channel regions CH, respectively. Forming the gate electrodes GE may include forming a photoresist pattern (not shown) exposing the heterojunction channel regions CH on the third nitride semiconductor film330, depositing a conductive material on the exposed heterojunction channel regions CH, and removing the photoresist pattern. In exemplary embodiments, depositing the conductive material may include performing a Plasma Assisted Atomic Layer Deposition (PA-ALD) process.

In other exemplary embodiments, forming the gate electrodes GE may include forming a sacrificial pattern (not shown) exposing the heterojunction channel regions CH on the third nitride semiconductor film330, depositing a conductive material on the exposed heterojunction channel regions CH, and removing the sacrificial pattern. For example, the sacrificial pattern may comprise SiN. Depositing the conductive material may include performing an Atomic Layer Deposition (ALD) process at a high temperature.

The gate electrodes GE may include a multi-layer structure. For example, each of the gate electrodes GE may include a Ni/Au structure. The gate electrodes GE may surround the heterojunction channel regions CH, respectively. Each of the gate electrodes GE may extend along the surface of the first and third nitride semiconductor films310and330. That is, each of the gate electrodes GE may extend along the upper surface of the third nitride semiconductor film330, the side surfaces of the third nitride semiconductor film330exposed by the first and second recess regions R1and R2, and the bottom surface of the first nitride semiconductor film310exposed by the air gap AG. For example, the gate electrode GE may have an annular shape.

Referring toFIGS. 8A, 8B, 8C, and 8D, third recess regions R3may be formed in the first and second heterojunction source/drain regions SD1and SD2. Forming the third recess regions R3may include forming a photoresist pattern (not shown) exposing regions, where the third recess regions R3are to be formed, on the third nitride semiconductor film330, patterning the first to third nitride semiconductor films310,320, and330by performing an anisotropic etching process using the photoresist pattern as an etching mask, and removing the photoresist pattern. The third recess regions R3may penetrate the first to third nitride semiconductor films310,320, and330to expose the upper surface of the insulating layer200.

In the exemplary embodiments, the side surfaces of the first to third nitride semiconductor films310,320, and330exposed by each of the third recessed regions R3are surface-treated so that the surface characteristics of the side surfaces damaged during the anisotropic etching process may be improved. For example, the surface treatment may provide tetramethylammonium hydroxide (TMAH) in the third recessed regions R3to prevent the side surfaces of the first to third nitride semiconductor films310,320, and330from being exposed to the TMAH.

Referring toFIGS. 9A, 9B, 9C, and 9D, a first ohmic electrode OE1and a second ohmic electrode OE2may be formed on first and second heterojunction source/drain regions SD1and SD2, respectively. Forming the first and second ohmic electrodes OE1and OE2may include forming a photoresist pattern (not shown) exposing the first and second heterojunction source/drain regions SD1and SD2on the third nitride semiconductor film330, depositing metals on the first and second heterojunction source/drain regions SD1and SD2, and removing the photoresist pattern. Each of the first and second ohmic electrodes OE1and OE2may include a multi-layer structure. For example, each of the first and second ohmic electrodes OE1and OE2may include a Ti/Al/Ni/Au structure.

Generally, forming the ohmic electrode may include performing a high-temperature rapid heat treatment process. During the high-temperature rapid heat treatment process, the shape of the ohmic electrode may be deformed. Accordingly, the gate-all-around device may not have the required electrical characteristics. That is, the reliability of the gate-all-around device may be low.

Forming the first and second ohmic electrodes OE1and OE2according to the concept of the inventive concept may not include a heat treatment process. Accordingly, the gate-all-around device may have the required electrical characteristics. As a result, the reliability of the gate-all-around device may be improved.

Each of the first and second ohmic electrodes OE1and OE2may cover the upper surface of the third nitride semiconductor film330and extend into the third recessed regions R3. The first and second ohmic electrodes OE1and OE2may fill the third recess regions R3. Each of the first and second ohmic electrodes OE1and OE2may directly contact the first and second electron gas layers DEG1and DEG2. Thus, the electrical characteristics of the gate-all-around device may be improved.

According to the concept of the inventive concept, a gate-all-around device with improved reliability may be provided.

According to the concept of the inventive concept, a gate-all-around device with improved process efficiency may be provided.

Although the exemplary embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the inventive concept as hereinafter claimed.