SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

FIGS.1A to9Eillustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

Reference is made toFIGS.1A to1E, in whichFIG.1Ais a top view of a semiconductor device below a fin top,FIG.1Bis a top view of a semiconductor device above a fin top,FIG.1Cis a cross-sectional view along line C-C ofFIG.1A,FIG.1Dis cross-sectional view along line D-D ofFIG.1A, andFIG.1Eis cross-sectional view along line E-E ofFIG.1A. In greater details,FIG.1Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.1Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

Semiconductor fins112and114are formed over the substrate100. The semiconductor fins112and114may be formed by, for example, forming a mask layer over the substrate100, in which the mask layer may include openings that expose portions of the substrate100. The exposed substrate100is then etched through the openings of the mask layer, forming trenches in the substrate100. A portion of the substrate100between neighboring trenches can be referred to as a semiconductor fin.

Isolation structures105may be formed over the substrate100and laterally surrounding bottom portions of the semiconductor fins112and114. The isolation structures105can be referred to as shallow trench isolation (STI) structures. The isolation structures105can be formed by, for example depositing a dielectric material blanket over the substrate100and overfilling the spaces between the semiconductor fins112and114, performing a planarization process such as chemical mechanical polish (CMP) to remove excess dielectric material until the top surfaces of the semiconductor fins112and114are exposed. Afterward, the dielectric material is recessed, for example, through an etching operation, in which diluted HF, SiCoNi (including HF and NH3), or the like, may be used as the etchant. After recessing the isolation structures105, top portions of the semiconductor fins112and114are higher than the top surfaces of the isolation structures105, and hence top portions of the semiconductor fins112and114protrude above the isolation structures105.

In some embodiments, the isolation structures105are made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation dielectric160may be formed using a high-density-plasma (HDP) chemical vapor deposition (CVD) process, using silane (SiH4) and oxygen (O2) as reacting precursors. In some other embodiments, the isolation structures105may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), in which process gases may include tetraethylorthosilicate (TEOS) and ozone (O3). In yet other embodiments, the isolation structures105may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Other processes and materials may be used. In some embodiments, the isolation structures105can have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner. Thereafter, a thermal annealing may be optionally performed to the isolation structures105.

InFIG.1C, in some embodiments, during the thermal annealing performed to the isolation structures105, fin bending may occur due to different amount of oxide on opposite sides of each of the semiconductor fins112and114, which cause an outward bending of the semiconductor fins112and114. As a result, the semiconductor fins112and114may bend outwardly, and the trench between the semiconductor fins112and114may include a tapered profile. For example, a width of the trench between the semiconductor fins112and114may increase as a distance from the substrate100increases. In some other embodiments, the fin bending may not occur, and thus the semiconductor fins112and114may be substantially parallel to each other.

Dummy gate structures120A and120B are formed over the substrate100and crossing the semiconductor fins112and114. In some embodiments, each of the dummy gate structures120A and120B includes a gate dielectric layer122and a gate electrode124over the gate dielectric layer122. The dummy gate structures120A and120B may be formed by, for example, depositing a gate dielectric material blanket over the substrate100, depositing a gate electrode material over the gate dielectric material, and then patterning the gate dielectric material and the gate electrode material.

In some embodiments, the gate dielectric layer122is an oxide layer, such as silicon oxide. In some embodiments, the gate dielectric layer122is made of high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials. The gate dielectric layer122may be formed by a deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD) or other suitable techniques.

In some embodiments, the gate electrode124may include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, or metals. In some embodiments, the gate electrode124includes a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multi-layers thereof. The gate electrode124may be deposited by CVD, physical vapor deposition (PVD), sputter deposition, or other techniques suitable for depositing conductive materials.

Reference is made toFIGS.2A to2E, in whichFIG.2Ais a top view of a semiconductor device below a fin top,FIG.2Bis a top view of a semiconductor device above a fin top,FIG.2Cis a cross-sectional view along line C-C ofFIG.2A,FIG.2Dis cross-sectional view along line D-D ofFIG.2A, andFIG.2Eis cross-sectional view along line E-E ofFIG.2A. In greater details,FIG.2Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.2Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

A first spacer layer130is deposited over the substrate100and lining the structures formed over the substrate100. In greater details, the first spacer layer130is formed extending along surfaces of the isolation structures105, surfaces of the semiconductor fins112and114, and surfaces the dummy gate structures120A and120B. In some embodiments, the first spacer layer130may be deposited via a conformal manner, such as using chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, the first spacer layer130may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials or other suitable dielectric material.

A second spacer layer132is then deposited over the first spacer layer130. In some embodiments, the second spacer layer132may be deposited via a conformal manner, such as using chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. However, the second spacer layer132may be deposited thick enough to overfill the trench between the semiconductor fins112and114, as shown inFIG.2C. That is, an entirety of the trench between the semiconductor fins112and114is filled with the first spacer layer130and the second spacer layer132after the deposition of the second spacer layer132is completed. In some embodiments, the second spacer layer132may be thicker than the first spacer layer130, so as to ensure that the trench between the semiconductor fins112and114is overfilled. In some embodiments, the second spacer layer132may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials or other suitable dielectric material. In some embodiments, the first spacer layer130and the second spacer layer132are made of different dielectric materials. In some embodiments, the dielectric constant of the second spacer layer132is lower than the dielectric constant of the first spacer layer130.

Reference is made toFIGS.3A to3E, in whichFIG.3Ais a top view of a semiconductor device below a fin top,FIG.3Bis a top view of a semiconductor device above a fin top,FIG.3Cis a cross-sectional view along line C-C ofFIG.3A,FIG.3Dis cross-sectional view along line D-D ofFIG.3A, andFIG.3Eis cross-sectional view along line E-E ofFIG.3A. In greater details,FIG.3Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.3Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

An etching back process is performed to remove portions of the second spacer layer132. In some embodiments where the first spacer layer130and the second spacer layer132are made of different dielectric materials, the first spacer layer130may include a higher etching resistance to the etching back process than the second spacer layer132, such that the first spacer layer130may be kept substantially intact after the etching back process is completed.

In the top view ofFIG.3Aand the cross-sectional view ofFIG.3C, it can be seen that portions of the second spacer layer132outside the space laterally between the semiconductor fins112and114are removed, while portions of the second spacer layer132laterally between the semiconductor fins112and114remain after the etching process is completed. This is because it is hard for the etching process to etch the portions of the second spacer layer132is a small space, such as the space laterally between the semiconductor fins112and114.

In the cross-sectional view ofFIG.3C, it can be seen that portions of the second spacer layer132are removed to expose the first spacer layer130. With respect to the semiconductor fin112, the semiconductor fin112may include a first sidewall distal to the semiconductor fin114and a second sidewall facing the semiconductor fin114. Portions of the second spacer layer132are removed from portions of the first spacer layer130that are above the top surface of the semiconductor fin112and on the first sidewall of the semiconductor fin112. Accordingly, the portions of the first spacer layer130that are above the top surface of the semiconductor fin112and on the first sidewall of the semiconductor fin112are exposed after the etching back process is completed. However, the portion of the first spacer layer130on the second sidewall of the semiconductor fin112remains covered by the second spacer layer132after the etching back process is completed.

With respect to the semiconductor fin114, the semiconductor fin114may include a first sidewall distal to the semiconductor fin112and a second sidewall facing the semiconductor fin112. Similarly, portions of the second spacer layer132are removed from portions of the first spacer layer130that are above the top surface of the semiconductor fin114and on the first sidewall of the semiconductor fin114. Accordingly, the portions of the first spacer layer130that are above the top surface of the semiconductor fin114and on the first sidewall of the semiconductor fin114are exposed after the etching back process is completed. However, the portion of the first spacer layer130on the second sidewall of the semiconductor fin114remains covered by the second spacer layer132after the etching back process is completed.

Stated another, inFIG.3C, only the portion of the first spacer layer130, which is in the space laterally between the semiconductor fins112and114, remains covered by the second spacer layer132after the etching back process is completed. In some embodiments, the topmost end of the first spacer layer130is higher than the topmost end of the second spacer layer132.

In the cross-sectional view ofFIG.3D, it can be seen that portions of the second spacer layer132are removed from the top portions of the first spacer layer130, such that top portions of the first spacer layer130are exposed after the etching back process is completed. Accordingly, bottom portions of the first spacer layer130remain covered by the second spacer layer132after the etching back process is completed. In some embodiments, top surfaces of the remaining portions of the second spacer layer132are lower than top surfaces of the dummy gate structures120A and120B. In some embodiments, top surfaces of the remaining portions of the second spacer layer132are lower than topmost ends of the first spacer layer130. In some embodiments, the second spacer layer132is changed from a U-shape cross-section (seeFIG.2D) to a rectangular cross-section.

In the cross-sectional view ofFIG.3E, it can be seen that portions of the second spacer layer132are removed, such that portions of the first spacer layer130that are vertically above the semiconductor fin112(or114) are exposed. Stated another way, portions of the second spacer layer132that are vertically above the semiconductor fin112(or114) are completely removed. Accordingly, in some embodiments, no second spacer layer132remains in the cross-sectional view ofFIG.3Eafter the etching back process is completed.

Reference is made toFIGS.4A to4E, in whichFIG.4Ais a top view of a semiconductor device below a fin top,FIG.4Bis a top view of a semiconductor device above a fin top,FIG.4Cis a cross-sectional view along line C-C ofFIG.4A,FIG.4Dis cross-sectional view along line D-D ofFIG.4A, andFIG.4Eis cross-sectional view along line E-E ofFIG.4A. In greater details,FIG.4Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.4Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

After the etching process performed to the second spacer layer132is completed, a third spacer layer134is deposited over the first spacer layer130and the second spacer layer132. In some embodiments, the third spacer layer134may be deposited via a conformal manner, such as using chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, the third spacer layer134may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials or other suitable dielectric material. In some embodiments, the first spacer layer130, the second spacer layer132, and the third spacer layer134are made of different dielectric materials. In some embodiments, the dielectric constant of the second spacer layer132is lower than the dielectric constant of the third spacer layer134.

In the cross-sectional view ofFIG.4C, the third spacer layer134may be in contact with the first spacer layer130and the second spacer layer132. In greater details, the third spacer layer134may be in contact with top surface of the remaining portion of the second spacer layer132that is laterally between the semiconductor fins112and114. The third spacer layer134may be in contact with portions of the first spacer layer130that are uncovered by the second spacer layer132.

In the cross-sectional view ofFIG.4D, the third spacer layer134may be in contact with the first spacer layer130and the second spacer layer132. In greater details, the third spacer layer134may be in contact with top surface of the remaining portion of the second spacer layer132. The third spacer layer134may be in contact with top portions of the first spacer layer130, and may be separated from the bottom portions of the first spacer layer130by the second spacer layer132. In some embodiments, the first spacer layer130and the third spacer layer134both include a U-shape cross-section, while the remaining portion of the second spacer layer132has a rectangular cross-section.

In the cross-sectional view ofFIG.4E, the third spacer layer134may line the first spacer layer130. Because portions of the second spacer layer132is removed from the cross-sectional view ofFIG.4E, the third spacer layer134may be in contact with vertical portions of the first spacer layer130and lateral portions of the first spacer layer130.

Reference is made toFIGS.5A to5E, in whichFIG.5Ais a top view of a semiconductor device below a fin top,FIG.5Bis a top view of a semiconductor device above a fin top,FIG.5Cis a cross-sectional view along line C-C ofFIG.5A,FIG.5Dis cross-sectional view along line D-D ofFIG.5A, andFIG.5Eis cross-sectional view along line E-E ofFIG.5A. In greater details,FIG.5Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.5Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

An etching process is performed to remove portions of the first spacer layer130, the second spacer layer132, and the third spacer layer134, and portions of the semiconductor fins112and114. In greater details, the etching process may include a first etch for etching the first spacer layer130, the second spacer layer132, and the third spacer layer134, and a second etching for etching the semiconductor fins112and114.

In some embodiments, the first etch of the etching process may include an anisotropic etch, such as a dry etch. The first etch is performed to remove horizontal portions of the first spacer layer130, the second spacer layer132, and the third spacer layer134, so as to expose semiconductor fins112and114. Afterwards, the second etch of the etching process may remove portions of the exposed semiconductor fins112and114to form recesses R1in the semiconductor fins112and114.

In the cross-sectional view ofFIG.5C, portions of the first spacer layer130, the second spacer layer132, and the third spacer layer134are removed, and then portions of the semiconductor fins112and114are removed to form the recesses R1.

In the cross-sectional view ofFIG.5D, portions of the first spacer layer130, the second spacer layer132, and the third spacer layer134are removed. In greater details, the second spacer layer132is etched, such that the second spacer layer132is changed from a rectangular cross-section (seeFIG.4D) to a U-shape cross-section. In some embodiments, the second spacer layer132may act as a protective layer to protect bottom portions of the first spacer layer130from being etched.

In the cross-sectional view ofFIG.5E, the horizontal portions of the first spacer layer130and the third spacer layer134are removed, and the semiconductor fin112(or114) is etched to form the recesses R1.

Reference is made toFIGS.6A to6E, in whichFIG.6Ais a top view of a semiconductor device below a fin top,FIG.6Bis a top view of a semiconductor device above a fin top,FIG.6Cis a cross-sectional view along line C-C ofFIG.6A,FIG.6Dis cross-sectional view along line D-D ofFIG.6A, andFIG.6Eis cross-sectional view along line E-E ofFIG.6A. In greater details,FIG.6Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.6Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

Epitaxial source/drain structures142and144are formed in the recesses R1of the semiconductor fins112and114, respectively. The epitaxy source/drain structures162are formed over the semiconductor fin112, and the epitaxy source/drain structures164are formed over the semiconductor fin114.

In greater details, as shown in the cross-sectional view ofFIGS.6D and6E, the epitaxial source/drain structures162are formed on opposite sides of the dummy gate structure120A (or120B). Similarly, the epitaxial source/drain structures164may be formed on opposite sides of the dummy gate structure120A (or120B). Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In the cross-sectional view ofFIG.6C, the epitaxial source/drain structures162and164may merge together. That is, the epitaxial source/drain structures162and164may be in contact with each other. In some embodiments, a gap G1is formed under the epitaxial source/drain structures162and164. In greater details, the gap G1is defined by the epitaxial source/drain structures162and164and the second spacer layer132. That is, top surface of the second spacer layer132may be exposed to the gap G1.

In the cross-sectional view ofFIG.6D, the source/drain structures162(or164) may be in contact with the second spacer layer132and the third spacer layer134. In some embodiments, the source/drain structures162(or164) may be in contact with the interface between the second spacer layer132and the third spacer layer134. In the cross-sectional view ofFIG.6D, the source/drain structures162(or164) may be separated from the first spacer layer130by the second spacer layer132and the third spacer layer134. Similarly, a gap G1is formed under the source/drain structures162. In greater details, the gap G1is defined by the epitaxial source/drain structure162and the second spacer layer132.

In the cross-sectional view ofFIG.6E, the source/drain structures162(or164) may be in contact with the first spacer layer130and the third spacer layer134. In some embodiments, the source/drain structures162(or164) may be in contact with the interface between the first spacer layer130and the third spacer layer134.

The epitaxial source/drain structures162and164may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, silicon phosphate (SiP) features, silicon carbide (SiC) features and/or other suitable features can be formed in a crystalline state on the recessed portions of the semiconductor fins112and114. In some embodiments, lattice constants of the epitaxial source/drain structures162and164are different from that of the semiconductor fins112and114, so that the channel region between the epitaxial source/drain structures162and164can be strained or stressed by the epitaxial source/drain structures162and164to improve carrier mobility of the semiconductor device and enhance the device performance.

The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins162and164(e.g., silicon, silicon germanium, silicon phosphate, or the like). The epitaxial source/drain structures162and164may be in-situ doped. The doping species include p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the epitaxial source/drain structures162and164are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the epitaxial source/drain structures162and164. One or more annealing processes may be performed to activate the epitaxial source/drain structures162and164. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes.

Reference is made toFIGS.7A to7E, in whichFIG.7Ais a top view of a semiconductor device below a fin top,FIG.7Bis a top view of a semiconductor device above a fin top,FIG.7Cis a cross-sectional view along line C-C ofFIG.7A,FIG.7Dis cross-sectional view along line D-D ofFIG.7A, andFIG.7Eis cross-sectional view along line E-E ofFIG.7A. In greater details,FIG.7Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.7Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

After the epitaxial source/drain structures162and164are formed, an etching back process is performed to the third spacer layer134, so as to lower top surfaces of the third spacer layer134. In some embodiments where the first spacer layer130and the second spacer layer132are made of different materials than the third spacer layer134, the first spacer layer130and the second spacer layer132may include higher etching resistance to the etching back process than the third spacer layer134.

As shown in the cross-sectional view ofFIG.7C, the third spacer layer130is removed to expose the first spacer layer130.

As shown in the cross-sectional view ofFIG.7D, the third spacer layer130is etched back, such that top surfaces of the third spacer layer130are lower than top surfaces of the first spacer layer130.

As shown in the cross-sectional view ofFIG.7E, the third spacer layer130is etched back, such that top surfaces of the third spacer layer130are lower than top surfaces of the first spacer layer130. Moreover, the top surfaces of the third spacer layer130are lower than top surfaces of the epitaxial source/drain structures162(or164).

After the etching back process is completed, gate spacers170are formed. In some embodiments, each of the gate spacers170may include remaining portions of the first spacer layer130, the second spacer layer132, and the third spacer layer134. In the cross-sectional view ofFIG.7D, the top portion of each gate spacer170is thinner than the bottom portion of each gate spacer170. For example, the top portion of each gate spacer170include the first spacer layer130and the third spacer layer134, while the bottom portion of each gate spacer170include the first spacer layer130, the second spacer layer132, and the third spacer layer134.

Reference is made toFIGS.8A to8E, in whichFIG.8Ais a top view of a semiconductor device below a fin top,FIG.8Bis a top view of a semiconductor device above a fin top,FIG.8Cis a cross-sectional view along line C-C ofFIG.8A,FIG.8Dis cross-sectional view along line D-D ofFIG.8A, andFIG.8Eis cross-sectional view along line E-E ofFIG.8A. In greater details,FIG.8Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.8Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

Contact etch stop layer (CESL)150is formed over the epitaxial source/drain structures162and164, and then an interlayer dielectric (ILD) layer155is formed over the CESL150. Afterwards, a CMP process may be performed to remove excessive materials of the ILD layer155and the CESL150to expose the dummy gate structures120A and120B. The CMP process may planarize top surfaces of the ILD layer155and the CESL150with top surfaces of the dummy gate structures120A and120B.

In the cross-sectional view ofFIG.8C, the CESL150may extend along surfaces of the epitaxial source/drain structures162and164, and may be in contact with the first spacer layer130.

In the cross-sectional view ofFIG.8D, the CESL150may be in contact with the first spacer layer130and the third spacer layer132. In greater details, the CESL150is in contact with sidewalls of the first spacer layer130and top surfaces of the third spacer layer134. In some embodiments, the CESL150is separated from the second spacer layer132by the third spacer layer134.

In the cross-sectional view ofFIG.8E, the CESL150may be in contact with the first spacer layer130and the third spacer layer132. In greater details, the CESL150is in contact with sidewalls of the first spacer layer130and top surfaces of the third spacer layer134. In some embodiments, the interface between the CESL150and the third spacer layer134may be lower than a topmost end of the epitaxial source/drain structure162(or164).

The CESL150may be a dielectric layer including silicon nitride, silicon oxynitride or other suitable materials. The CESL150can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer155may include a material different from the CESL150. In some embodiments, the ILD layer155may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD layer155may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques.

Reference is made toFIGS.9A to9E, in whichFIG.9Ais a top view of a semiconductor device below a fin top,FIG.9Bis a top view of a semiconductor device above a fin top,FIG.9Cis a cross-sectional view along line C-C ofFIG.9A,FIG.9Dis cross-sectional view along line D-D ofFIG.9A, andFIG.9Eis cross-sectional view along line E-E ofFIG.9A. In greater details,FIG.9Ais a top view (or plane view) below top surfaces of semiconductor fins (e.g., fins112and114), andFIG.9Bis a top view (or plane view) above top surfaces of semiconductor fins (e.g., fins112and114).

The dummy gate structures120A and120B are replaced with the metal gate structures180A and180B. In some embodiments, the dummy gate structures120A and120B may be removed by suitable etching process, so as to form gate trenches between each pair of the gate spacers170. Then, layers of the metal gate structures180A and180B are deposited in the gate trenches, followed by a CMP process to remove excess materials of the layers of the metal gate structures180A and180B until the ILD layer155is exposed. In some embodiments, each of the metal gate structures180A and180B may include a gate dielectric layer182, a work function metal layer184, and a gate electrode186over the work function metal layer184.

In some embodiments, the gate dielectric layer182may include one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer182may be formed by CVD, ALD or any suitable method.

In some embodiments, the work function metal layer184may be made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function metal layer144, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function metal layer184. The work function metal layer184may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. Embodiments of the present disclosure provide a method for forming a gate spacer, which includes a first spacer layer, a second spacer layer, and a third spacer layer. The second spacer layer is etched back, such that the remaining second spacer layer is below fin top. As a result, the remaining second spacer layer may mitigate metal gate extrusion (MGEX) during forming a metal gate structure. The second spacer layer is formed with a low-k dielectric material, which in turn will reduce the device capacitance. Moreover, because the second spacer layer is etched back, top portions of the gate spacer may be thinned, the thinner gate spacer may improve the growth of source/drain epitaxy structures, which will improve the device performance.

In some embodiments of the present disclosure, a method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

In some embodiments, the method further includes etching back the third spacer layer to expose sidewall of the first spacer layer after forming the epitaxial source/drain structures in the recesses.

In some embodiments, etching back the third spacer layer is performed such that a top surface of the third spacer layer is lower than a topmost end of one of the epitaxial source/drain structures.

In some embodiments, the method further includes forming a contact etch stop layer over the epitaxial source/drain structures, wherein the contact etch stop layer is in contact with the first and third spacer layers.

In some embodiments, the contact etch stop layer is separated from the second spacer layer by the third spacer layer.

In some embodiments, forming the second spacer layer is performed such that the second spacer layer has a first U-shape cross-section in a cross-sectional view along the isolation structures, etching back the second spacer layer is performed such that the second spacer layer is changed from the first U-shape cross-section to a rectangular cross-section in the cross-sectional view along the isolation structures, and etching the first, second, and third spacer layers and the semiconductor fin to form recesses is performed such that the second spacer layer is changed from the rectangular cross-section to a second U-shape cross-section.

In some embodiments, the first, second, and third spacer layers are made of different dielectric materials.

In some embodiments of the present disclosure, a method includes forming first and second semiconductor fins over the substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the first and second semiconductor fins; etching back the second spacer layer to remove portions of the second spacer layer outside a space laterally between the first and second semiconductor fins, wherein a remaining portion of the second spacer layer is laterally between the first and second semiconductor fins; etching the first and second spacer layers and the first and second semiconductor fins to form recesses; and forming epitaxial source/drain structures in the recesses.

In some embodiments, the method further includes after etching back the second spacer layer, forming a third spacer layer over and in contact with the first and second spacer layers.

In some embodiments, the method further includes etching back the third spacer layer to expose sidewall of the first spacer layer.

In some embodiments, the method further includes forming a contact etch stop layer over the epitaxial source/drain structures, wherein the contact etch stop layer is in contact with a sidewall of the first spacer layer; and forming an interlayer dielectric layer over the contact etch stop layer.

In some embodiments, the contact etch stop layer is separated from the remaining portion of the second spacer layer.

In some embodiments, the second spacer layer is thicker than the first spacer layer.

In some embodiments, forming the first spacer layer and the second spacer layer is performed such that an entirety of the space laterally between the first and second semiconductor fins is filled with the first spacer layer and the second spacer layer.

In some embodiments of the present disclosure, a device includes a substrate having a semiconductor fin, isolation structures over the substrate and laterally surrounding the semiconductor fin, a gate structure over the semiconductor fin, a gate spacer on a sidewall of the gate structure, and epitaxial source/drain structures on opposite sides of the gate structure. The gate spacer includes a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer, in which in a first cross-sectional view along the isolation structures, a top surface of the second spacer layer is lower than a top surface of the third spacer layer, and the top surface of the third spacer layer is lower than a top surface of the first spacer layer.

In some embodiments, the device further includes a contact etch stop layer over the epitaxial source/drain structures, wherein in the first cross-sectional view, the contact etch stop layer is in contact with the first spacer layer and the third spacer layer.

In some embodiments, in the first cross-sectional view, a gap is vertically between one of the epitaxial source/drain structures and the second spacer layer of the gate spacer.

In some embodiments, in a second cross-sectional view along the semiconductor fin, the top surface of the third spacer layer is lower than a top surface of one of the source/drain structures.

In some embodiments, a dielectric constant of the second spacer layer is lower than dielectric constants of the first and third spacer layers.

In some embodiments, in the first cross-sectional view, one of the epitaxial source/drain structures is in contact with the second and third spacer layers and is separated from the first spacer layer.