Gate driving circuit and display device including the same

A gate driving circuit including a plurality of stages to respectively output gate signals to gate lines and connected to each other in cascade, an ith stage from among the plurality of stages including: a first output unit to generate a gate signal from a clock signal received at an input terminal; a first control unit to control the potential of a first node; a first pull-down unit to provide a first low voltage to a gate output terminal to drop down the gate signal, the first low voltage being lower than a gate off voltage of the gate signal; a first holding unit and a stabilization unit, each to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal; and a second control unit to control an operation of the first holding unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application No. 10-2015-0171682, filed on Dec. 3, 2015, in the Korean Intellectual Property Office (KIPO), the entire content of which is incorporated by reference herein in its entirety.

BACKGROUND

One or more aspects of example embodiments of the present disclosure relate to a gate driving circuit and a display device including the same.

2. Description of the Related Art

A display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. The display device includes a gate driving circuit for sequentially providing gate signals to the plurality of gate lines, and a data driving circuit for outputting data signals to the plurality of data lines.

The gate driving circuit includes a shift register formed of a plurality of stages connected in cascade to each other. Each of the plurality of stages includes a plurality of transistors that are operatively connected to each other to output a gate voltage to a corresponding gate line.

Recently, the resolution of a display device is increased from Full High Definition (FHD) that supports 1920×1080 resolution to Ultra High Definition (UHD) that supports 7680×4320 resolution (e.g., 8K) or 3840×2160 resolution (e.g., 4K), so that the resolution of the display device becomes larger.

The above information disclosed in this Background section is for enhancement of understanding of the background of the inventive concept, and therefore, it may contain information that does not constitute prior art.

SUMMARY

One or more aspects of example embodiments of the present disclosure provide a gate driving circuit for sufficiently obtaining a pixel charging time and for reducing a variation between charging rates between upper end pixels and lower end pixels of a display device, even if the resolution of the display panel is increased, and a display device including the same.

According to an example embodiment of the inventive concept, a gate driving circuit includes a plurality of stages configured to respectively output gate signals to gate lines and connected to each other in cascade, an ith stage from among the plurality of stages, where i is an integer greater than or equal to two, including: a first output unit configured to be turned on/off according to a potential of a first node, and to generate a gate signal from a clock signal received at an input terminal of the ith stage, the gate signal being outputted to a gate output terminal of the ith stage and including a gate on voltage and a gate off voltage; a first control unit configured to control the potential of the first node; a first pull-down unit configured to provide a first low voltage to the gate output terminal of the ith stage to drop down the gate signal of the ith stage, after the gate on voltage of the gate signal of the ith stage is outputted, the first low voltage being lower than the gate off voltage of the gate signal of the ith stage; a first holding unit and a stabilization unit, each configured to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal of the ith stage, after the first low voltage is provided to the gate output terminal of the ith stage; and a second control unit configured to control an operation of the first holding unit.

In an embodiment, the first pull-down unit may include a first pull-down transistor; and the first pull-down transistor may include a control electrode configured to receive an output signal of an i+1th stage, an input electrode configured to receive the first low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the first holding unit may include: a first holding transistor, and the first holding transistor may include a control electrode connected to a second node and configured to receive an inverter signal generated based on the clock signal from the second control unit, an input electrode configured to receive the second low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the stabilization unit may include: a stabilization transistor, and the stabilization transistor may include a control electrode configured to receive an output signal of an i+2th stage, an input electrode configured to receive the second low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the first low voltage may be more than about −15 V and less than about −10 V; and the second low voltage may be more than about −9V and less than about −6 V.

In an embodiment, the gate off voltage may have the same level as that of the first low voltage.

In an embodiment, the gate driving circuit may further include a second output unit configured to be turned on or off according to a potential of the first node, and to generate a carry signal to be outputted to a carry output terminal of the ith stage from a clock signal received at the input terminal of the ith stage.

In an embodiment, the gate driving circuit may further include a second pull-down unit configured to provide the first low voltage to the carry output terminal of the ith stage after the carry signal is outputted, and the second pull-down unit may include a second pull-down transistor.

In an embodiment, the gate driving circuit may further include a second holding unit configured to maintain the carry output terminal of the ith stage at the first low voltage after the first low voltage is provided to the carry output terminal of the ith stage, and the second holding unit may include a second holding transistor.

According to an example embodiment of the inventive concept, a display device includes: a display panel including a plurality of gate lines, a plurality of data lines crossing and insulated from the plurality of gate lines, and a plurality of pixels respectively connected to the gate lines and the data lines; a data driver configured to provide data signals to the plurality of data lines; and a gate driver including a plurality of stages connected in cascade with each other and configured to provide gate signals to the plurality of gate lines, an ith stage from among the plurality of stages, where i is an integer greater than or equal to two, including: a first output unit configured to be turned on/off according to a potential of a first node, and to generate a gate signal from a clock signal received at an input terminal of the ith stage, the gate signal being outputted to a gate output terminal of the ith stage and including a gate on voltage and a gate off voltage; a first control unit configured to control the potential of the first node; a first pull-down unit configured to provide a first low voltage to the gate output terminal of the ith stage to drop down the gate signal of the ith stage, after the gate on voltage of the gate signal of the ith stage is outputted, the first low voltage being lower than the gate off voltage of the gate signal of the ith stage; a first holding unit and a stabilization unit, each configured to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal of the ith stage, after the first low voltage is provided to the gate output terminal of the ith stage; and a second control unit configured to control an operation of the first holding unit.

In an embodiment, at least one pixel from among the plurality of pixels may include: a pixel transistor connected to a corresponding gate line and a corresponding data line; a pixel electrode connected to the pixel transistor; and a common electrode opposite the pixel electrode with a liquid crystal layer there between, wherein the pixel electrode and the common electrode may form a liquid crystal capacitor configured to be charged with a data voltage received from the pixel transistor.

In an embodiment, the data voltage may be a voltage corresponding to a gray level value of a corresponding data signal applied to the corresponding data line within a range of about −8 V to about 35 V.

In an embodiment, the first pull-down unit may include a first pull-down transistor; and the first pull-down transistor may include a control electrode configured to receive an output signal of an i+1th stage, an input electrode configured to receive the first low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the first holding unit may include a holding transistor, and the holding transistor may include a control electrode connected to a second node configured to receive an inverter signal generated based on the clock signal from the second control unit, an input electrode configured to receive the second low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the stabilization unit may include a stabilization transistor, and the stabilization transistor may include a control electrode configured to receive an output signal of an i+2th stage, an input electrode configured to receive the second low voltage, and an output electrode connected to the gate output terminal.

In an embodiment, the first low voltage may be more than about −15 V and less than about −10 V; and the second low voltage may be more than about −9V and less than about −6 V.

In an embodiment, the gate off voltage may have the same level as that of the first low voltage.

According to an example embodiment of the inventive concept, a gate driving circuit includes a plurality of stages configured to respectively output gate signals to gate lines and connected in cascade with each other, an ith stage from among the plurality of stages, where i is an integer greater than or equal to two, including: an output transistor including a control electrode connected to a first node, an input electrode configured to receive a clock signal, and an output electrode connected to an output terminal; a control transistor including a control electrode configured to receive an output of an i−1th stage, an input electrode connected to the control electrode, and an output electrode connected to the first node; a pull-down transistor including a control electrode configured to receive an output signal of an i+1th stage, an input electrode configured to receive a first low voltage, and an output electrode connected to the output terminal; a holding transistor including a control electrode connected to a second node, an input electrode configured to receive a second low voltage having a higher level than that of the first low voltage, and an output electrode connected to the output terminal; and a stabilization transistor including a control electrode configured to receive an output signal of an i+2th stage, an input electrode configured to receive the second low voltage, and an output electrode connected to the output terminal.

In an embodiment, the output terminal may be configured to output a gate signal including a gate on voltage and a gate off voltage, and the gate driving circuit may further include an inverter transistor configured to maintain the second node at the gate off voltage when the gate signal is the gate on voltage.

In an embodiment, the gate driving circuit may further include a capacitor connected between the first node and the output terminal.

DETAILED DESCRIPTION

FIG. 1is a plan view of a display device according to an embodiment of the inventive concept.FIG. 2is a timing diagram illustrating signals of a display device according to an embodiment of the inventive concept.

As shown inFIGS. 1 and 2, a display device according to an embodiment of the inventive concept includes a display panel DP, a gate driving circuit (e.g., a gate driver)100, and a data driving circuit (e.g., a data driver)200.

The display panel DP is not limited to a specific embodiment of the inventive concept and may include various display panels, such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and/or an electrowetting display panel. For convenience, the display panel DP is described as a liquid crystal display panel. When the display panel DP includes a liquid crystal display panel, the liquid crystal display device including the liquid crystal display panel may further include a polarizer and a backlight unit (e.g., a backlight source).

The display panel DP includes a first substrate DS1, a second substrate DS2spaced from the first substrate DS1, and a liquid crystal layer LCL disposed between the first substrate DS1and the second substrate DS2. On a plane, the display panel DP includes a display area DA including a plurality of pixels PX11to PXnm, and a non-display area NDA surrounding the display area DA.

The display panel DP includes a plurality of gate lines GL1to GLn disposed on the first substrate DS1, and a plurality of data lines DL1to DLm crossing the plurality of gate lines GL1to GLn. The plurality of gate lines GL1to GLn are connected to the gate driving circuit100. The plurality of data lines DL1to DLm are connected to the data driving circuit200. For convenience, some of the plurality of gate lines GL1to GLn and some of the plurality of data lines DL1to DLm are illustrated inFIG. 1. Additionally, the display panel DP may further include a dummy gate line GLd disposed in the non-display area NDA of the first substrate DS1.

For convenience, some of the plurality of pixels PX11to PXnm are illustrated inFIG. 1. The plurality of pixels PX11to PXnm are respectively connected to corresponding gate lines from among the plurality of gate lines GL1to GLn and corresponding data lines from among the plurality of data lines DL1to DLm. However, the dummy gate line GLd may not be connected to the plurality of pixels PX11to PXnm.

The plurality of pixels PX11to PXnm may be divided into a plurality of groups according to a color to be displayed. The plurality of pixels PX11to PXnm may display any one of primary colors. The primary colors may include red, green, blue, and/or white. However, the inventive concept is not limited thereto, and thus, the primary colors may further include (or alternatively include) various colors, such as yellow, cyan, magenta, etc.

The gate driving circuit100and the data driving circuit200receive a control signal from a first signal control unit (e.g., a first controller, for example, a timing controller). The first control unit may be mounted on a main circuit board MCB. The first signal control unit receives image data and control signals from an external first graphic control unit (e.g., a first graphic controller). The control signals may include vertical sync signals Vsync that are signals for distinguishing frame sections Fn−1, Fn, and Fn+1, horizontal sync signals Hsync that are signals for distinguishing horizontal sections HP (e.g., row distinction signals), data enable signals (that may be, for example, in high level only during a section where data is outputted to display a data incoming area), and clock signals.

The gate driving circuit100generates gate signals GS1to GSn on the basis of a control signal (hereinafter referred to as a gate control signal) received from the first signal control unit during frame sections Fn−1, Fn, and Fn+1, and outputs the gate signals GS1to GSn to the plurality of gate lines GL1to GLn. The gate signals GS1to GSn may be sequentially outputted in correspondence to the horizontal sections HP. The gate driving circuit100and the pixels PX11to PXnm may be formed concurrently (e.g., simultaneously) through a thin film process. For example, the gate driving circuit100may be mounted in an Amorphous Silicon TFT Gate driver circuit (ASG) form or an Oxide Semiconductor TFT Gate driver circuit (OSG) form at (e.g., in) the non-display area NDA.

FIG. 1illustrates one gate driving circuit100connected to the left ends of the plurality of gate lines GL1to GLn. However, the inventive concept is not limited thereto, for example, according to an embodiment of the inventive concept, a display device may include two gate driving circuits. One of the two gate driving circuits may be connected to the left ends of the plurality of gate lines GL1to GLn and the other one of the two may be connected to the right ends of the plurality of gate lines GL1to GLn. Further, one of the two gate driving circuits may be connected to odd gate lines and the other one of the two may be connected to even gate lines.

The data driving circuit200generates gray level voltages according to image data provided from the first signal control unit on the basis of a control signal (hereinafter referred to as a data control signal) received from the first signal control unit. The data driving circuit200outputs the gray level voltages as data voltages DS to the plurality of data lines DL1to DLm.

The data voltages DS may include positive data voltages each having a positive value with respect to a common voltage, and/or negative data voltages each having a negative value with respect to the common voltage. Some of data voltages applied to the data lines DL1to DLm may each have a positive polarity and others may each have a negative polarity during each of the horizontal sections HP. The polarity of the data voltages DS may be inverted according to the frame sections Fn−1, Fn, and Fn+1, in order to prevent or reduce the deterioration of liquid crystals. The data driving circuit200may generate data voltages inverted by each frame section unit in response to an invert signal.

The data driving circuit200may include a driving chip210and a flexible circuit board220on which the driving chip210is mounted. The data driving circuit200may include a plurality of driving chips210and a plurality of flexible circuit boards220. The flexible circuit board220connects (e.g., electrically connects) the main circuit board MCB and the first substrate DS1. The plurality of driving chips210provide data signals to corresponding data lines from among the plurality of data lines DL1to DLm.

FIG. 1illustrates a Tape Carrier Package (TCP) type (form) data driving circuit200as an example. However, the inventive concept is not limited thereto, for example, according to an embodiment of the inventive concept, the data driving circuit200may be disposed at (e.g., in) the non-display area NDA of the first substrate DS1through a Chip on Glass (COG) method.

FIG. 3is an equivalent circuit diagram of a pixel PXij according to an embodiment of the inventive concept.FIG. 4is a sectional view of a pixel PXij according to an embodiment of the inventive concept. Each of the plurality of pixels PX11to PXnm shown inFIG. 1may have the same or substantially the same circuit as that shown inFIG. 3.

As shown inFIG. 3, the pixel PXij includes a pixel thin film transistor (hereinafter referred to as a pixel transistor) TRP, a liquid crystal capacitor Clc, and a storage capacitor Cst. According to an embodiment of the inventive concept, the storage capacitor Cst may be omitted.

The pixel transistor TRP is electrically connected to an ith gate line GLi and a jth data line DLj. The pixel transistor TRP outputs a pixel voltage corresponding to a data signal received from the jth data line DLj in response to a gate signal received from the ith gate line GLi.

The liquid crystal capacitor Clc charges a pixel voltage outputted from the pixel transistor TRP. An arrangement of liquid crystal directors included in the liquid crystal layer LCL (seeFIG. 4) is changed according to a charge amount charged in the liquid crystal capacitor Clc. The light incident to the liquid crystal layer LCL may be transmitted or blocked according to an arrangement of the liquid crystal directors.

The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cst maintains or substantially maintains an arrangement of the liquid crystal directors during a set or predetermined section.

As shown inFIG. 4, the pixel transistor TRP includes a control electrode CEP (hereinafter referred to as a pixel control electrode) connected to the ith gate line GLi (seeFIG. 3), an activation layer ALP (hereinafter referred to as a pixel activation layer) overlapping with the pixel control electrode CEP, an input electrode IEP (hereinafter referred to as a pixel input electrode) connected to the jth data line DLj (seeFIG. 3), and an output electrode OEP spaced from the pixel input electrode IEP.

The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL overlapping with the pixel electrode PE.

The ith gate line GLi and the storage line STL are disposed on a surface (e.g., one surface) of the first substrate DS1. The pixel control electrode CEP is branched from the ith gate line GLi. The ith gate line GLi and the storage line STL may include a metal (for example, Al, Ag, Cu, Mo, Cr, Ta, Ti, etc.) or an alloy thereof. The ith gate line GLi and the storage line STL may have a multi-layer structure, and for example, may include a Ti layer and a Cu layer.

A first insulating layer10covering the pixel control electrode CEP and the storage line STL is disposed on a surface (e.g., one surface) of the first substrate DS1. The first insulating layer10may include at least one of an inorganic material and an organic material. The first insulating layer10may be an organic layer or an inorganic layer. The first insulating layer10may have a multi-layer structure, and for example, may include a silicon nitride layer and a silicon oxide layer.

The activation layer ALP overlapping the pixel control electrode CEP is disposed on the first insulating layer10. The pixel activation layer ALP may include a semiconductor layer and an ohmic contact layer.

The pixel activation layer ALP may include amorphous silicon or poly silicon. Additionally, the pixel activation layer ALP may include a metal oxide semiconductor.

The pixel output electrode OEP and the pixel input electrode IEP are disposed on the pixel activation layer ALP. The pixel output electrode OEP and the pixel input electrode IEP are spaced from each other. Each of the pixel output electrode OEP and the pixel input electrode IEP may partially overlap with the pixel control electrode CEP.

Although the pixel transistor TRP having a staggered structure is shown inFIG. 4exemplarily, a structure of the pixel transistor TRP is not limited thereto. For example, in an embodiment, the pixel transistor TRP may have a planar structure.

A second insulating layer20covering the pixel activation part ALP, the pixel output electrode OEP, and the pixel input electrode IEP is disposed on the first insulating layer10. The second insulating layer20may provide a flat surface. The second insulating layer20may include an organic material.

The pixel electrode PE is disposed on the second insulating layer20. The pixel electrode PE is connected to the pixel output electrode OEP through the second insulating layer20and a contact hole CH penetrating the second insulating layer20. An alignment layer30covering the pixel electrode PE may be disposed on the second insulating layer20.

A color filter layer CF is disposed on a surface (e.g., one surface) of the second substrate DS2. The common electrode CE is disposed on the color filter layer CF. A common voltage is applied to the common electrode CE. A common voltage and a pixel voltage may have different values. In an embodiment, an alignment layer covering the common electrode CE may be disposed on the common electrode CE. In an embodiment, another insulating layer may be disposed between the color filter layer CF and the common electrode CE.

The pixel electrode PE and the common electrode CE with the liquid crystal layer LCL therebetween form the liquid crystal capacitor Clc. Additionally, portions of the pixel electrode PE and the storage line STL, which are disposed with the first insulating layer10and the second insulating layer20therebetween, form the storage capacitor Cst. The storage line STL receives a storage voltage having a different value from that of a pixel voltage. A storage voltage may have the same or substantially the same value as that of the common voltage.

On the other hand, a section of the pixel PXij shown inFIG. 4is just one example. For example, in an embodiment, unlike those ofFIG. 4, at least one of the color filter layer CF and the common electrode CE may be disposed on the first substrate DS1. That is, a liquid crystal display panel according to an embodiment of the inventive concept may include a pixel in a Vertical Alignment (VA) mode, a Patterned Vertical Alignment (PVA) mode, an in-plane switching (IPS) mode, a fringe-field switching (FFS) mode, or a Plane to Line Switching (PLS) mode.

FIG. 5is a block diagram illustrating a gate driving circuit according to an embodiment of the inventive concept. As shown inFIG. 5, a gate driving circuit100includes a plurality of stages SRC1to SRCn. The plurality of stages SRC1to SRCn may configure one shift register. As shown inFIG. 5, the plurality of stages SRC1to SRCn may be connected in cascade to each other.

The plurality of stages SRC1to SRCn are respectively connected to the plurality of gate lines GL1to GLn. That is, the plurality of stages SRC1to SRCn provide gate signals GS1to GSn to the plurality of gate lines GL1to GLn, respectively.

Each of the plurality of stages SRC1to SRCn includes an input terminal IN, a clock terminal CK, first and second voltage input terminals V1and V2, first and second control terminals CT1and CT2, an output terminal OT, and a carry terminal CR.

The carry terminal CR of each of the plurality of stages SRC1to SRCn is electrically connected to the input terminal IN of a next driving stage. The input terminal IN of a first stage SRC1receives a start signal STV for starting the drive of the gate driving circuit100, instead of a carry signal of a previous stage. After the first stage, the input terminal IN of each of the plurality of stages SRC2to SRCn receives a carry signal of a previous stage. The input terminal IN of the ith stage is electrically connected to the carry terminal CR of the i−1th stage. Here, i is an integer greater than 1 and less than n. As shown inFIG. 5, the input terminals IN of the second stage SRC2and the third stage SRC3respectively receive the carry signals of the first stage SRC1and the second stage SRC2.

Moreover, this is just one example, and the input terminal IN of the ith stage may be electrically connected to the carry terminal of any of a previous stage, for example, the carry terminal of the i−1th stage, the i−2th stage, or the i−3th stage. For example, the second stage SRC2may receive a start signal that is different from the start signal received by the first stage SRC1, and the input terminal IN of the third stage SRC3may receive the carry signal of the first stage SRC1.

The first control terminal CT1of each of the plurality of stages SRC1to SRCn is electrically connected to the carry terminal CR of the next stage, to receive a carry signal of the next stage. The second control terminal CT2of each of the plurality of stages SRC1to SRCn is electrically connected to the carry terminal CR of a stage connected in cascade to the next stage (e.g., a second next stage).

For example, the first control terminal CT1of the ith stage is electrically connected to the carry terminal CR of the i+1th stage, and the second control terminal CT2of the ith stage is electrically connected to the carry terminal CR of the i+2th stage. As shown inFIG. 5, the first control terminal CT1of the first stage SRC1is electrically connected to the carry terminal CR of the second stage SRC2, and the second control terminal CT2of the first stage SRC1is electrically connected to the carry terminal CR of the third stage SRC3.

However, the first and second control terminals CT1and CT2of the last driving stage SRCn from among the plurality of stages SRC1to SRCn receive signals corresponding to carry signals from dummy stages SRCd1and SRCd2. The dummy stages SRCd1and SRCd2are sequentially connected to the end (e.g., the rear end) of the last driving stage SRCn. However, the position and number of the dummy stages SRCd1and SRCd2may be variously changed according to the design of the gate driving circuit100as would be known to one skilled in the art.

Moreover, this is just one example, and the first control terminal CT1of the ith stage may be electrically connected to any of the carry terminals CR of a stage following the ith stage. Additionally, the second control terminal CT2of the ith stage may be electrically connected to any of the carry terminals CR of a stage following a stage that provides a carry signal to the first control terminal CT1.

FIG. 5is just an example of a gate driving circuit, and a connection relationship of the plurality of stages SRC1to SRCn shown inFIG. 5may be variously changed.

For example, unlike inFIG. 5, the input terminals IN of the plurality of stages SRC1to SRCn may respectively receive gate signals from the output terminals OT of previous stages. That is, carry signals or gate signals applied to the input terminals IN of the plurality of stages SRC1to SRCn are one control signal for controlling an operation of the plurality of stages SRC1to SRCn.

Additionally, in some embodiments, the first control terminal CT1of each of the plurality of stages SRC1to SRCn may be electrically connected to the output terminal OT of the next stage, instead of the carry terminal CR of the next stage, to receive a gate signal from the next stage. In some embodiments, the second control terminal CT2of each of the plurality of stages SRC1to SRCn may be electrically connected to the output terminal OT of a stage connected in cascade to the next stage (e.g., the second next stage). The second control terminal CT2of each of the plurality of stages SRC1to SRCn may receive a gate signal from a stage connected in cascade to the next stage (e.g., the second next stage).

The odd stages SRC1, SRC3, etc. and the even stages SRC2, SRC4, etc. from among the plurality of stages SRC1to SRCn receive phase-inverted signals, respectively. The clock terminals CK of the odd stages SRC1, SRC3, etc. receive clock signals CKV, and the clock terminals CK of the even stages SRC2, SRC4, etc. receive clock bar signals CKVB.

The clock signal CKV and the clock bar signal CKVB have a phase difference of, for example, about 180°. Each of the clock signal CKV and the clock bar signal CKVB may swing between a first clock voltage VCK1and a second clock voltage VCK2. The first clock voltage VCK1may be, for example, about 15V to about 35V. The second clock voltage VCK2may be, for example, about −16V to about −10V.

A first low voltage VSS1is applied to the first voltage input terminal V1of each of the plurality of stages SRC1to SRCn, and a second low voltage VSS2having a higher voltage level than that of the first low voltage VSS1is applied to the second voltage input terminal V2of each of the plurality of stages SRC1to SRCn. The second low voltage VSS2may be, for example, about −10 V to about −5 V, and the first low voltage VSS1may be, for example, about −16 V to about −10 V. As one example, the first low voltage VSS1may be about −11.5 V, and the second low voltage VSS2may be about −7.5 V. The first low voltage VSS1may have the same or substantially the same level as that of the second clock voltage VCK2.

The output terminal OT of each of the plurality of stages SRC1to SRCn is connected to a corresponding gate line. Accordingly, a gate signal outputted through the output terminal OT is applied to a corresponding gate line.

FIG. 6is a circuit diagram illustrating the ith stage SRCi from among the plurality of stages SRC1to SRCn shown inFIG. 5, andFIG. 7is an input/output signal waveform diagram of the ith stage SRCi shown inFIG. 6. Each of the plurality of stages SRC1to SRCn shown inFIG. 5may have the same or substantially the same circuit configuration as that ofFIG. 6.

The ith stage SRCi includes a first output unit111-1, a second output unit111-2, a charging unit CA, a first control unit112, a first pull-down unit113-1, a second pull-down unit113-2, a first holding unit114-1, a second holding unit114-2, a stabilization unit115, and a second control unit116.

The first output unit111-1outputs a gate signal GSi to the ith gate line, and the second output unit111-2outputs a carry signal CRSi to the i+1th stage.

The charging unit CA is charged by a high voltage of the carry signal CRSi−1 of the i−1th stage applied to a first node NQ.

The first control unit112controls on/off operations of the first output unit111-1and the second output unit111-2, by adjusting a voltage of the first node NQ. The first control unit112turns on the first output unit111-1and the second output unit111-2in response to the carry signal CRSi−1 of the i−1th stage, and turns off the first output unit111-1and the second output unit111-2in response to the carry signal CRSi+1 of the i+1th stage. Then, the first control unit112maintains or substantially maintains the first node NQ with the first low voltage VSS1in response to the carry signal CRSi+2 of the i+2th stage and a level (e.g., a potential level) of a second node NA.

The first pull-down unit113-1lowers the potential of the output terminal OT to the first low voltage VSS1, and the second pull-down unit113-2lowers the potential of the carry terminal CR to the first low voltage VSS1.

After the voltage of the output terminal OT is lowered to the first low voltage VSS1, the first holding unit114-1provides the second low voltage VSS2to the output terminal OT. After the potential of the carry terminal CR is lowered to the first low voltage VSS1, the second holding unit114-2provides the first low voltage VSS1to the carry terminal CR.

The stabilization unit115provides the second low voltage VSS2to the output terminal OT in response to the carry signal CRSi+2 of the i+2th stage.

The second control unit116controls operations of the first holding unit114-1and the second holding unit114-2. The second control unit116provides an inverter signal to the second node NA for turning on/off the first holding unit114-1and the second holding unit114-2. Herein, the second node NA is a node (e.g., a portion) where an inverter signal generated based on a clock signal from the second control unit116is applied, and is connected to the control electrode of each of the first holding unit114-1and the second holding unit114-2. Additionally, the second node NA is connected to a control terminal of a fifth control transistor TRG7of the first control unit112, and is involved in applying the first low voltage VSS1to the first node NQ.

Each of carry signals CRSi−1, CRSi, CRSi+1, and CRSi+2 includes a section for maintaining or substantially maintaining a carry-high voltage VH-C and a section for maintaining or substantially maintaining a carry-low voltage VL-C. The carry-high voltage VH-C is identical or substantially identical to the first clock voltage VCK1. The carry-low voltage VL-C is identical or substantially identical to the first low voltage VSS1.

The gate signal GSi includes a section for maintaining or substantially maintaining a gate-high voltage VH-G, a section for maintaining or substantially maintaining a first gate-low voltage VL-G1, and a section for maintaining or substantially maintaining a gate-low voltage VL-G2. The gate-high voltage VH-G is identical or substantially identical to the first clock voltage VCK1. The first gate-low voltage VL-G1is identical or substantially identical to the first low voltage VSS1. The second gate-low voltage VL-G2is identical or substantially identical to the second low voltage VSS2.

Referring toFIGS. 6 and 7, a configuration of the ith stage SRCi will be described in more detail.FIG. 7is a view illustrating a horizontal section HPi (hereinafter referred to as an ith horizontal section) where an ith gate signal GSi is outputted, an immediately previous horizontal section HPi−1 (hereinafter referred to as an i−1th horizontal section), and an immediately after horizontal section HPi+1 (hereinafter referred to as an i+1th horizontal section), from among a plurality of horizontal sections.

The first output unit111-1includes a first output transistor TRG1. The first output transistor TRG1includes an input electrode for receiving a clock signal CKV, a control electrode connected to the first node NQ, and an output electrode connected to the output terminal OT. The gate signal GSi is outputted through the output terminal OT. The first node NQ is an output terminal of the first control unit112.

The second output unit111-2includes a second output transistor TRG2. The second output transistor TRG2includes an input electrode for receiving a clock signal CKV, a control electrode connected to the first node NQ, and an output electrode connected to the carry terminal CR. A carry signal CRSi is outputted through the carry terminal CR.

The charging unit CA includes a first capacitor C1. The first capacitor C1is disposed between the control electrode and the output electrode of the first output transistor TRG1. One end of the first capacitor C1is connected to the first node NQ and the other end of the first capacitor C1is connected to the output terminal OT.

The first control unit112includes first to fifth control transistors TRG3, TRG4, TRG5, TRG6, and TRG7.

The first control transistor TRG3includes a control electrode and an input electrode, which commonly receive the carry signal CRSi−1 of the i−1th stage. The carry signal CRSi−1 of the i−1th stage is a control signal applied to the control electrode of the first control transistor TRG3. Additionally, the output electrode of the first control transistor TRG3is connected to the control electrode of each of the first output transistor TRG1and the second output transistor TRG2through the first node NQ.

The second control transistor TRG4includes an output electrode connected to the first node NQ, a control electrode for receiving the carry signal CRSi+1 of the i+1th stage, and an input electrode connected to the output electrode of the third control transistor TRG5.

In relation to the third control transistor TRG5, the output electrode is connected to the control electrode in order to perform a diode function. Additionally, the third control transistor TRG5includes an input electrode connected to the first voltage input terminal V1where the first low voltage VSS1is applied. However, the inventive concept is not limited thereto, and in an embodiment, the third control transistor TRG5may be omitted. When the third control transistor TRG5is omitted, the input electrode of the second control transistor TRG4is connected to the first voltage input terminal V1to receive (e.g., directly receive) the first low voltage VSS1.

When the first control transistor TRG3is turned on in response to the carry signal CRSi−1 of the i−1th stage, the potential of the first node NQ is raised to a first high voltage VQ1, and the first output transistor TRG1and the second output transistor TRG2are turned on. At this point, as the first output transistor TRG1of the first output unit111-1is turned on, the first low voltage VSS1of the clock signal CKV from the clock terminal CK is applied to the output terminal OT, so that the level of the first gate signal GS1becomes the first low voltage VSS1.

When the carry signal CRSi−1 of the i−1th stage is applied to the first node NQ, the first capacitor C1is charged. Then, the first output transistor TRG1is bootstrapped. That is, the first node NQ connected to the control electrode of the first output transistor TRG1is boosted from the first high voltage VQ1to a second high voltage VQ2.

When the second control transistor TRG4and the third control transistor TRG5are turned on in response to the carry signal CRSi+1 of the i+1th stage, the potential of the first node NQ is reduced. When the potential of the first node NQ is reduced, the first and second transistors TRG1and TRG2connected to the first node NQ are turned off.

The fourth control transistor TRG6includes an input electrode connected to the first voltage input terminal V1to receive the first low voltage VSS1, a control electrode connected to a second control terminal CR2to receive the carry signal CRSi+2 of the i+2th stage, and an output electrode connected to the first node NQ.

The fourth control transistor TRG6supplies the first low voltage VSS1to the first node NQ in response to the carry signal CRSi+2 of the i+2th stage. Accordingly, the potential of the first node NQ is maintained or substantially maintained at the first low voltage VSS1by the carry signal CRSi+2 of the i+2th stage.

The fifth control transistor TRG7includes an input electrode connected to the first voltage input terminal V1, a control electrode connected to the second node NA, and an output electrode connected to the first node NQ.

The fifth control transistor TRG7is turned on or off according to the potential of the second node NA. When the potential of the second node NA is low, the fifth control transistor TRG7is turned off. When the potential of the second node NA rises by the clock signal CKV, the fifth control transistor TRG7is turned on.

The turned-on fifth control transistor TRG7drops the potential of the first node NQ to the first low voltage VSS1. Thereby, the potential of the first node NQ is maintained or substantially maintained at the first low voltage VSS1by the fourth and fifth control transistors TRG6and TRG7during a low section of the gate signal GSi.

The first pull-down unit113-1includes a first pull-down transistor TRG8. The first pull-down transistor TRG8includes an output electrode connected to the output electrode of the first output transistor TRG1, a control electrode for receiving the carry signal CRSi+1 of the i+1th stage, and an input electrode connected to the first voltage input terminal V1to receive the first low voltage VSS1.

The first pull-down transistor TRG8drops a voltage of the output terminal OT to the first low voltage VSS1in response to the carry signal CRSi+1 of the i+1th stage. Because the first low voltage VSS1has a lower potential level than that of the second low voltage VSS2, a speed at which the first pull-down transistor TRG8drops a voltage of the output terminal OT to the first low voltage VSS1is faster than a speed at which the first pull-down transistor TRG8drops a voltage of the output terminal OT to the second low voltage VSS2.

The first holding unit114-1includes a first holding transistor TRG10. After the voltage of the output terminal OT is at (e.g., lowered to) the first low voltage VSS1, the first holding transistor TRG10provides the second low voltage VSS2to the output terminal OT.

The first holding transistor TRG10includes an output electrode connected to the output electrode of the first output transistor TRG1, a control electrode connected to the second node NA, and an input electrode connected to the second voltage input terminal V2to receive the second low voltage VSS2.

That is, when the first node NQ is boosted to the second high voltage VQ2in the ith horizontal section HPi, a level of the output terminal OT becomes a gate-high voltage VH-G. Then, as the first pull-down transistor TRG8of the first pull-down unit113-1is turned on by the carry signal CRSi+1 of the i+1th stage, the first pull-down transistor TRG8drops a level of the output terminal OT to a first gate-low voltage VL-G1(or a first low voltage) drastically. When a level of the second node NA becomes a high voltage VA1for the first time, the second node NA turns on the first holding transistor TRG10to apply the second low voltage VSS2to the output terminal OT.

The second pull-down unit113-2includes a second pull-down transistor TRG9. The second pull-down transistor TRG9drops a voltage of the carry terminal CR to the first low voltage VSS1in response to the carry signal CRSi+1 of the i+1th stage. The second pull-down transistor TRG9includes a control electrode for receiving the carry signal CRSi+1 of the i+1th stage, an input electrode connected to the first voltage input terminal V1to receive the first low voltage VSS1, and an output electrode connected to the carry terminal CR. The output electrode of the second pull-down transistor TRG9is connected to the control electrodes of a second inverter transistor TRG14and a third inverter transistor TRG15that will be described in more detail later. Additionally, the output electrode of the second pull-down transistor TRG9is connected to the output electrode of the second output transistor TRG2. However, the inventive concept is not limited thereto, and in an embodiment, the second pull-down transistor TRG9may be omitted.

The second holding unit114-2includes a second holding transistor TRG11. After the voltage of the carry terminal CR is at (e.g., lowered to) the first low voltage VSS1, the second holding transistor TRG11provides (e.g., continuously provides) the first low voltage VSS1to the carry terminal CR.

The second holding transistor TRG11includes an output electrode connected to the output electrode of the second output transistor TRG2, a control electrode connected to the second node NA, and an input electrode connected to the first voltage input terminal V1to receive the first low voltage VSS1.

The stabilization unit115includes a stabilization transistor TRG12. The stabilization unit115provides the second low voltage VSS2to the output terminal OT in response to the carry signal CRSi−2 of the i+2th stage.

The stabilization transistor TRG12includes a control electrode for receiving the carry signal CRSi+2 of the i+2th stage, an input electrode for receiving the second low voltage VSS2, and an output electrode connected to the output terminal OT. The stabilization unit115helps the first holding unit114-1to stably maintain the voltage of the output terminal OT at the second low voltage VSS2. When the stabilization transistor TRG12performs a part of a role for the first holding transistor TRG10, a size (or a width) of the first holding transistor TRG10may be reduced. For example, the size of the ith stage SRCi according to an embodiment of the present disclosure may be reduced by about 18% compared to the size of a comparable ith stage.

The second control unit116includes first to fifth inverter transistors TRG13, TRG14, TRG15, TRG16, and TRG17, a second capacitor C2, and a third capacitor C3.

The second control unit116supplies the first low voltage VSS1to the second node NA in response to the carry signal CRSi−1 of the i−1th stage. The first holding unit114-1and the second holding unit114-2, which receive the first low voltage VSS1, are turned off. Then, the second control unit116provides the second low voltage VSS2to the second node NA in response to the clock signal CKV. The turn-off of the first holding unit114-1and the second holding unit114-2, which receive the second low voltage VSS2, are maintained or substantially maintained.

The second control unit116supplies a voltage corresponding to the clock signal CKV to the second node NA from the i+1th horizontal section Hpi+1 of the first output unit111-1. That is, from the i+1th horizontal section Hpi+1, a low voltage VA0and a high voltage VA1are alternately applied to the second node NA.

The first inverter transistor TRG13includes an output electrode connected to the second node NA, a control electrode for receiving the carry signal CRSi−1 of the i−1th stage, and an input electrode connected to the first voltage input terminal V1to receive the first low voltage VSS1.

The second inverter transistor TRG14includes an output electrode connected to the control electrode of the first holding transistor TRG10, a control electrode for receiving the carry signal CRSi from the second output unit111-2, and an input electrode connected to the second voltage input terminal V2to receive the second low voltage VSS2. Additionally, the control electrode of the second inverter transistor TRG14is connected to the output electrode of the second pull-down transistor TRG9.

The third inverter transistor TRG15includes a control electrode for receiving the carry signal CRSi from the second output unit111-2, an input electrode connected to the second voltage input terminal V2to receive the second low voltage VSS2, and an output electrode connected to an output electrode of the fourth inverter transistor TRG16.

The fourth inverter transistor TRG16includes a control electrode and an input electrode, where the clock signal CKV is commonly applied. The output electrode of the fourth inverter transistor TRG16is connected to the output electrode of the third inverter transistor TRG15.

The fifth inverter transistor TRG17includes an input electrode for receiving a clock signal CKV, a control electrode connected to the output electrode of the fourth inverter transistor TRG16, and an output electrode connected to the second node NA.

The second capacitor C2is connected between the input electrode and the control electrode of the fifth inverter transistor TRG17, and the third capacitor C3is connected between the output electrode of the fourth inverter transistor TRG16and the output electrode of the fifth inverter transistor TRG17.

Hereinafter, an operation of the second control unit116is described in more detail.

The first inverter transistor TRG13supplies the first low voltage VSS1to the second node NA in response to the carry signal CRSi−1 of the i−1th stage.

The second inverter transistor TRG14supplies the second low voltage VSS2to the second node NA during the ith horizontal section HPi. Accordingly, the first and second holding transistors TRG10and TRG11are turned off by the second low voltage VSS2during the ith horizontal section HPi.

The third inverter transistor TRG15is turned on during the ith horizontal section HPi, so that the third inverter transistor TRG15drops the clock signal CKV outputted from the fourth inverter transistor TRG16to the second low voltage VSS2. Accordingly, the clock signal CKV is not applied (e.g., prevented from being applied) to the second node NA. Herein, the ith horizontal section HPi may correspond to a high section of the clock signal CKV.

The second and third capacitors C2and C3are charged by a voltage according to the clock signal CKV. Then, the fifth inverter transistor TRG17is turned on by the voltage charged to the second and third capacitors C2and C3. Additionally, when the first to third inverter transistors TRG13, TRG14, and TRG15are turned off, the potential of the second node NA rises by the voltage charged to the second and third capacitors C2and C3.

When the potential of the second node NA rises, the first and second holding transistors TRG10and TRG11are turned on. The turned-on first holding transistor TRG10supplies the second low voltage VSS2to the output terminal OT, and the turned-on second holding transistor TRG11supplies the first low voltage VSS1to the carry terminal CR.

FIG. 8is a graph for comparing a graph GPH of a gate signal outputted from an upper end part of a display device DD and a graph GPL of a gate signal outputted from a lower end part of the display device DD according to an embodiment of the inventive concept.

The graph GPH of the gate signal at the upper end part of the display DD may correspond to the waveform of a gate signal of a fifth stage. The graph GPL of the gate signal at the lower end part of the display DD may correspond to the waveform of a gate signal of a 120th stage.

According to an embodiment of the inventive concept, a difference DV1(hereinafter referred to as a first deviation) between a peak point of the graph GPH of the gate signal at the upper end part and a peak point of the graph GPL of the gate signal at the lower end part is less than about 1 V. Because the first deviation DV1is small (e.g., within about 1 V), a defective charging rate may be prevented or substantially prevented between pixels PXnm by a difference of gate signals outputted from the respective upper end and lower end parts of the display device DD.

FIG. 9is a graph for comparing graphs GP1and GP3of signals outputted from a display device DD according to an embodiment of the inventive concept with graphs GP2and GP4of signals outputted from a comparable display device.

The first graph GP1illustrates a gate signal outputted from the display device DD according to an embodiment of the inventive concept. The second graph GP2illustrates a gate signal outputted from the comparable display device. The third graph GP3illustrates a charging voltage of a pixel of the display device DD according to an embodiment of the inventive concept. The fourth graph GP4illustrates a charging voltage of a pixel of the comparable display device.

A difference DV2(hereinafter referred to as a second deviation) between the peak point of the first graph GP1and the peak point of the second graph GP2represents a difference between a peak point of a gate signal outputted from the display device DD according to an embodiment of the inventive concept and a peak point of a gate signal outputted from the comparable display device

Because the peak point of the first graph GP1is greater by the second difference DV2than the peak point of the second graph GP2, the peak point of the third graph GP3is greater by a third deviation DV3than the peak point of the fourth graph GP4. Each of the second deviation DV2and the third deviation DV3may be, for example, about 0.4 V. Accordingly, a charging rate of the pixels PXmn of the display device DD may be improved by about 2.28% compared to a comparable technique.

According to an embodiment of the inventive concept, a speed at which a gate on voltage of a gate signal outputted from a gate driving circuit changes into a gate off voltage becomes faster, so that a charging time may be improved. Additionally, a deviation between gate signals provided to a display panel is reduced. Accordingly, a display device with excellent display quality may be provided.

Although exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments, and that various changes and modifications can be made by one having ordinary skill in the art, within the spirit and scope of the present invention as defined by the following claims and their equivalents.