Lateral type semiconductor device

A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apart from the emitter regions with a predetermined space through the base layer; the base layer formed in a concentric circular pattern on the upper part; the emitter regions and collector regions provided with contacts respectively; and emitter and collector wiring layers connected to the contacts.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device such as a lateral transistor constituted of a plurality of emitter contacts and a plurality of collector contacts arranged and connected together in parallel respectively on the same semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This invention is based upon and claims the benefits of priority from the prior Japanese Patent Applications No. 2003-320791 on Sep. 12, 2003; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Referring toFIG. 9, the background technology will be explained.

One of lateral type power transistors used for power sources such as a low drop-out power source is a power transistor having a base layer on an upper part of a semiconductor substrate, a plurality of emitter regions provided separately from each other on an upper part in the base layer, and a collector region provided apart from the emitter region by a predetermined distance so as to surround them, the plurality of emitter regions being connected together in parallel to be used. The power transistor mentioned above is configured as follows.

InFIG. 9, the power transistor1has an N+buried layer formed on a predetermined portion of an upper part of a substantially rectangular P−type semiconductor substrate2, an N−type base layer4formed by vapor phase epitaxy so as to cover the buried layer3, and a P−isolation region5formed on the peripheral part of the base layer4by thermal diffusion. The part within the P−isolation region of the base layer4is partitioned in three compartments9a,9b, and9cby dividing the inside part in three by means of a guard ring8comprised of an N++region6and an N+region provided on the upper part of the base layer4, along approximately the periphery of the substrate in parallel with the side of the rectangular outline of the semiconductor substrate2.

A plurality of emitter regions12having a square pattern of a P++region10and a P+region11with a predetermined depth respectively are arranged one by one at a predetermined first pitch in the horizontal direction of the substrate surface and at a predetermined second pitch in the perpendicular direction thereof, on the upper part inside the base layer4in each compartment9a,9b, or9c. Furthermore, the upper part of the base region4is provided with a P+collector region13in such a manner as to surround each emitter region12spaced by a predetermined space, so that a PNP transistor14is formed locally with being centered at each emitter region12.

An insulating layer of such as SiO2is formed on the base layer4, the emitter region12, the collector region13, etc. A square emitter contact16smaller than the emitter region12is formed on a part of the insulating layer over the emitter region12so as to conduct the emitter region12. On the other hand, a rectangular collector contact17is formed on a part of the insulating layer over the collector region13between the emitter regions12adjacent to each other in the longitudinal direction along the arranged direction of the emitter regions12, so as to conduct the collector region13. Moreover, a base contact18is formed on a predetermined part of the periphery of the semiconductor substrate2.

An emitter wiring patterned to connect in parallel each emitter region12through each emitter contact16and a collector wiring20patterned to connect in parallel each collector region13through each collector contact17is formed on the insulating layer. Reference numbers22and23designate a collector pad and an emitter pad respectively provided on the insulating layer15.

However, because the rectangular collector contact17in the conventional technology is provided in the direction of the arrangement of the emitter regions12between two emitter regions12adjacent to each other in the longitudinal direction, the distance between the PNP transistor units14centered at each emitter unit12cannot be decreased. That is, the above fact causes difficult situation to make the power transistor1be more miniaturized.

In addition, the collector contact17is formed adjacent to each emitter contact16in the longitudinal direction, so that the electric current when the transistor is operated concentrates on a part where the collector contact17is nearest to each emitter contact16. Therefore, the electric current does not flow effectively to the collector region13, and this leads to a low electric current efficiency.

Additionally, because the base contact18is located on a predetermined part of the periphery of the semiconductor substrate2and the guard ring8is provided so as to divide the inside of the semiconductor substrate2in parallel with the side of the rectangular outline into three compartments, the base resistance component of the PNP transistor unit14becomes large as the transistor unit gets close to the central part inside the divided three compartments9a,9b, and9c. In consequence, the PNP transistor14becomes difficult to be operated and especially the current gain at the large current region becomes deteriorated. Though it is therefore necessary that number of the PNP transistor units should be increased to improve the characteristics, this matter is contrary to miniaturizing the power transistor1.

SUMMARY OF THE INVENTION

According to one embodiment of the present invention, a semiconductor device comprises:

a semiconductor substrate;

a base layer formed on an upper part of the semiconductor substrate;

a plurality of emitter regions, each row thereof being provided on an upper part in the base layer at an equal interval in a first direction of a surface of the substrate, being arranged with a predetermined pitch for odd number rows in a second direction substantially perpendicular to the first direction, and being arranged with the predetermined pitch for even number rows in the second direction at a position shifted by ½ of the predetermined pitch to the arrangement of the odd number rows;

a collector region provided on the upper part of the base layer to surround each of the emitter regions with a predetermined space;

an insulating layer provided on the base layer, the emitter layer, and the collector layer;

an emitter contact formed on the emitter region by opening an upper part of the insulating layer in a predetermined shape;

a collector contact formed on the collector region by opening an upper part of the insulating layer in a predetermined shape; and

a wiring layer comprising an emitter wiring and a collector wiring on the insulating layer, both the wirings having predetermined pattern and connecting the emitter contact and the collector contact respectively.

In accordance with another embodiment of the present invention, a semiconductor device comprises:

a semiconductor substrate;

a base layer formed on an upper part of the semiconductor substrate;

a plurality of emitter regions, each row thereof being provided on an upper part in the base layer at an equal interval in a first direction of a surface of the substrate, being arranged with a predetermined pitch for odd number rows in a second direction substantially perpendicular to the first direction, and being arranged with the predetermined pitch for even number rows in the second direction at a position shifted by a predetermined pitch to the arrangement of the odd number rows;

a collector region provided on the upper part of the base layer to surround each of the emitter regions with a predetermined space;

an insulating layer provided on the base layer, the emitter layer, and the collector layer;

an emitter contact formed on the emitter region by opening an upper part of the insulating layer in a predetermined shape;

at least three collector contacts formed on the collector region by opening an upper part of the insulating layer in a predetermined shape, positioned adjacent to each of the emitter contacts and located to have an equal space to one emitter contact; and

a wiring layer comprising an emitter wiring and a collector wiring on the insulating layer, both the wirings having predetermined pattern and connecting the emitter contact and the collector contact in parallel respectively.

According to further embodiment of the present invention, a semiconductor device comprises:

a semiconductor substrate;

a base layer formed on an upper part of the semiconductor substrate;

a plurality of emitter regions, each row thereof being provided on an upper part in the base layer at an equal interval in a first direction of a surface of the substrate, being arranged with a predetermined pitch for odd number rows in a second direction substantially perpendicular to the first direction, being arranged with the predetermined pitch for even number rows in the second direction at a position shifted by ½ of the predetermined pitch to the arrangement of the odd number rows, and adjacent ones thereof being positioned at vertexes of an equilateral triangle respectively;

a collector region provided on the upper part of the base layer to surround each of the emitter regions with a predetermined space;

a guard ring provided on the upper part of the base layer to divide the collector regions and the emitter regions by being provided to be inclined at 60 degrees to the arranged direction of the emitter region;

an insulating layer provided on the base layer, the emitter layer, and the collector layer;

an emitter contact formed on the emitter region by opening an upper part of the insulating layer in a predetermined shape;

a collector contact formed over the collector region by opening an upper part of the insulating layer in a predetermined shape, and positioned for each of the emitter contact at each vertex of an equilateral triangle, the center of gravity thereof being on the emitter contact, to share at least one of the adjacent emitter contacts;

a base contact formed on the base region of the periphery of the semiconductor substrate surrounding the collector region by opening an upper part of the insulating layer; and

a wiring layer comprising an emitter wiring and a collector wiring on the insulating layer, both wirings having predetermined pattern and connecting the emitter contact and the collector contact in parallel respectively.

In accordance with another embodiment of the present invention, a semiconductor device comprises:

a semiconductor substrate;

a base layer formed on an upper part of the semiconductor substrate;

a plurality of emitter regions, each row thereof being provided on an upper part in the base layer at an equal interval in a first direction of a surface of the substrate, being arranged with a predetermined pitch for odd number rows in a second direction substantially perpendicular to the first direction, and being arranged with the predetermined pitch for even number rows in the second direction at a position shifted by ½ of the predetermined pitch to the arrangement of the odd number rows; and the emitter contacts of a plurality of adjoining emitter regions being provided in a pattern where each of the emitter contacts is placed on each vertex of an isosceles triangle one by one.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1toFIG. 7, an embodiment of the present invention will be hereinafter explained.FIG. 1is a pattern diagram showing the entire construction;FIG. 2is a partial pattern diagram;FIG. 3is a cross section at Y—Y line viewed in the arrow direction inFIG. 2;FIG. 4is a plan view showing the wiring state in the emitter pad side part;FIG. 6is a partial pattern diagram showing the first variation; andFIG. 7is a cross section of the second variation.

InFIG. 1toFIG. 7, a power transistor31is provided with a substantially rectangular P−type silicon semiconductor substrate32whose mirror-polished surface has an oxide film (not shown) formed by thermal oxidation. Then, the formed oxide film is patterned so that an opening can be formed at a predetermined part thereof. Furthermore, an N+buried layer33having a predetermined plane shape is formed on a predetermined part of the upper portion of the semiconductor substrate32through the opening by patterning by the aid of thermal diffusion of for example arsenic or antimony on the upper portion of the semiconductor substrate32. On the upper surface of the semiconductor substrate32, an N−type epitaxial layer to become a base layer34having a predetermined thickness is formed by vapor phase epitaxy so as to cover the N+buried layer33. In addition, a P−isolation region35reaching the upper surface of the semiconductor substrate32is formed on the peripheral portion of the epitaxial layer by thermal diffusion of e.g. boron, along approximately the outline shape of the N+buried layer33. Thereby, the base layer34is formed on a part within the P−isolation region35.

In the base layer34inside the P−isolation region35, a guard ring38comprised of an N++region36and an N+region37of the base region is prepared on the upper part of the base layer34by means of thermal diffusion of e.g. arsenic or antimony in the upper part of the semiconductor substrate32. As shown inFIG. 1, the guard ring38has a peripheral portion38A having an N++region36and an N+region37provided in parallel with the sides of the rectangular outline of the semiconductor substrate32along the shape of the P−isolation region35. Two tilted portions38B formed by an N+region crossing the peripheral portion38A between the opposite two sides of the peripheral portion38A at an angle of 60 degrees and spreading together in two different directions like the Greek letter Λ (lambda) are provided.

The inside area within the peripheral portion38A of the guard ring38is therefore divided into three partitions, i.e. three compartments39A,39B,39C by the two tilted portions38B. For the guard ring38, the N++region36of the peripheral portion38A is formed first up to the depth getting to the N+buried layer33, then an emitter region40and a collector region41described hereinafter are formed, and thereafter the N+region is formed.

After the N++region36of the guard ring38has been formed, the emitter region40comprised of a P++region42and a P+region43is formed on a predetermined position of the upper part in the base layer34within the P−isolation layer35and the N++region36of the guard ring38. With regard to the position on which the emitter region40is formed in this case, each row of the emitter region is located at an equal interval together in the longitudinal direction of the substrate surface i.e. the first direction A of the upper part in the base layer34parallel to the longitudinal side of the rectangular outline of the semiconductor substrate32, and each of the emitter regions40is arranged with a predetermined pitch p in the lateral direction i.e. the second direction B substantially perpendicular to the first direction for each odd number row, and arranged with the same pitch p at each position shifted from the arrangement of the odd number row by ½ of the predetermined pitch p in the lateral direction for each even number row. That is to say, each of the emitter regions is positioned in a staggered arrangement. In addition, adjoining three emitter regions40on neighboring two rows are provided so as to be placed respectively on each vertex of an equilateral triangle. Therefore, the emitter regions40form a dense pattern arranged with the same pitch also in the direction parallel to the tilted portion38B of the guard ring38crossing the direction of the row by an angle of 60 degrees. In this case, the first direction A and the second direction B are determined by the arrangement pattern of the emitter region, and the longitudinal side of the rectangular substrate32is the criterion in this embodiment.

Regarding to formation of the emitter region (not shown by a figure), P++region42is formed first: i.e. an oxide film is formed on the base layer34; then a mask having a predetermined pattern is formed on the oxide film by means of patterning by photo-etching method using a photoresist; thereafter the oxide film is opened by etching; and then e.g. boron is diffused through the formed opening on a predetermined position of the upper part in the base layer34. On the other hand, the P+region43is formed simultaneously when the P+type collector region41is formed.

In other words, the collector region41is provided on the upper part in the base layer34so as to surround each emitter region40with a predetermined space. In this embodiment, because the emitter region40has a circular pattern, the concentric circular base layer34is interposed between the collector region41and the emitter region40. With regard to formation of the P+region43of the emitter region40and the P+type collector region41, a first silicon oxide film (SiO2)45constituting an insulating layer44on the entire surface of each layer and each region formed on the semiconductor substrate32is formed first, and then an opening is formed at a predetermined position of the first silicon oxide film45by means of patterning and etching by photoetching method using photoresist. Subsequently, boron, for example, is diffused into the upper part in the base region34through each formed opening up to a predetermined depth, which does not reach the N+buried layer33. Thereby, a PNP transistor unit46is locally formed on a position centered at each emitter region40.

After the emitter region40and the collector region41have been formed, a second silicon oxide film47constituting the insulating layer44is formed again on the entire surface and patterned and etched as well. Then, the peripheral portion38A and the two tilted portions38B of the guard ring38are formed by diffusing e.g. phosphorus into the upper part in the base layer up to a predetermined depth, which does not reach the N+buried layer33, through the opening formed on the position where the N+region37of the guard ring38is formed.

After the N+region of the guard ring38has been formed, a third silicon oxide film48constituting the insulating layer44is formed again on the entire surface. Then, a predetermined position of the insulating layer44is opened in the shape of, for example, a circle by means of pattering and then etching by photoetching method using photoresist, whereby an emitter contact49and a collector contact50are formed, each of the upper surfaces of the P++region42of the emitter region40and the P+type collector region41being exposed to the inner bottom portion of the emitter contact49or the collector contact50. The emitter contact49thus formed is provided on the central portion of each emitter region40, and the collector contact50is provided for each of the emitter contacts49on each of the vertexes of the equilateral triangle whose center of gravity is on the corresponding emitter contact49. The space between the periphery of the emitter contact49and the periphery of each collector contact50at the vertex is equal to each other, and each of the collector contacts is configured to be shared by the adjoining emitter contacts49. At the same time as the emitter contact49and the collector contact50being formed, a predetermined position of the insulating layer44along the peripheral portion38A of the guard ring38is opened in the shape of approximately a rectangle, and a base contact51is formed on the inner bottom portion of the opening to which the corresponding upper surface of the N++region36of the base region is exposed.

As shown inFIGS. 3 to 5, on the third silicon oxide film48of the insulating layer44on which the emitter contact49, the emitter contact50, and the base contact51are formed, an emitter wiring52patterned like teeth of a comb to connect each emitter region40together in parallel through each emitter contact49is formed. A collector wiring53patterned like teeth of a comb to connect each collector region41together in parallel through each collector contact50is also formed. The emitter wiring52and the collector wiring53are extended in the second direction (as indicated by the arrow inFIGS. 4 and 5), and formed on the same layer surface as an interdigital pattern in which the two wirings alternate together with a predetermined insulating distance.

Therefore, the power transistor31is constituted of a plurality of the PNP transistor units46centered at each emitter region40, which are connected in parallel together to share the same base layer34. With regard to formation of the wiring layer54, aluminum is evaporated first on the third silicon oxide film48so as to bury the contacts49and50, and an aluminum film to become the wiring layer54is deposited. Thereafter, a mask of a predetermined pattern is formed by means of patterning by photoetching method using a photoresist. Then, etching of the aluminum film is carried out using the mask, and the emitter wiring52, the collector wiring53of the predetermined pattern are formed. Reference numbers55and56are a collector pad and an emitter pad respectively provided on the insulating layer44at the both opposite corner portions of the semiconductor substrate32at the same time as the wiring layer54being formed. The power transistor of this embodiment is designed for the low drop-out power source, so that a transistor70is independently formed adjacent to the base contact51on the bottom side of the substrate. This transistor is comprised of the power transistor31connected commonly with the base and the emitter to constitute for example an overcurrent protection circuit of the power transistor.

In accordance with the construction described above, the emitter wiring52and the collector wiring53are formed by the single-layered wiring layer54, whereas each neighboring emitter region40is arranged effectively with the same space. Thus the distance between the PNP transistor units46centered at each emitter region40can be narrowed, and the power transistor31more miniaturized can be constructed. For reference's sake, the conventional power transistor1in which 199 pieces of the PNP transistor units14are formed inFIG. 8is compared with the power transistor31of this embodiment in which 199 pieces of the PNP transistor46are also formed inFIG. 1. The power transistor of this embodiment can be miniaturized up to 72.8% in size of the conventional type one.

Because three collector contacts50are provided at positions having an equal distance to each of the emitter contacts49and the space among the three collector contacts50can be the same, current flows almost equally in each collector contact50. Therefore, current flows effectively to the collector region41so that current efficiency can be improved.

The peripheral portion38A of the guard ring38is provided along the shape of the P−isolation region, and the tilted portion38B dividing the region inside the peripheral portion38A where the PNP transistor units46are formed into three compartments39A,39B, and39C is provided so as to be parallel to the obliquely arranged direction of the PNP transistor units46arranged with a predetermined pitch also in the direction of 60 degrees to the laterally arranged direction. Even the PNP transistor units46positioned at the central portion in the three compartments39A,39B, and39C do not have an extremely high base resistance component, so that there is no possibility that they are difficult to be operated and decreasing of the current gain at a large current range can be diminished. Moreover it is not necessary to increase the number of the PNP transistor units for improving the characteristics thereof.

In the aforementioned embodiment, the collector contacts50are provided on three positions distant equally from the emitter contact49and apart from each other with an equal space. Like a first variation shown byFIG. 6in which the same part is designated by the same mark, each of six collector contacts50are located on each vertex of a regular hexagon whose center of gravity is on the emitter contact49. The space between the collector contact50and the emitter contact49and the space between neighboring two collector contacts50are arranged to be equal together. The emitter wiring52and the collector wiring corresponding thereto are patterned appropriately to provide the single-layered wiring layer54, to be able to miniaturize.

In the embodiment described above, the PNP transistor units46are arranged so that the spaces between any adjacent emitter regions40can be equal to each other. In the embodiment shown inFIG. 7, rows (RL1, RL2, RL3, RL4and so on) of the PNP transistor units46arranged in the lateral direction (the second direction) with a predetermined pitch P are arranged also with the predetermined pitch P but shifted by ½ of the predetermined pitch P for the adjacent row, to make the pitch S between the emitter contacts49of the neighboring rows in the longitudinal direction (the first direction) differ from the interline pitch P. That is to say, for example, a triangle pattern whose vertexes are on the emitter contacts491,492, and493on the unit rows RL1, RL2, and RL3forms an isosceles triangle E1. Like the above, by arranging the emitter contacts in an isosceles triangle pattern, nearly dense arrangement of the emitter regions can be achieved, so that the semiconductor substrate can be miniaturized. The tilted portion38B of the guard ring38shown inFIG. 1is provided parallel to the oblique arrangement71of the PNP transistor units46arranged obliquely to the lateral arrangement of the emitter regions40. The collector contact50can be provided so as to assure a predetermined insulating distance between the emitter wiring52and the collector wiring53(Refer toFIG. 4), and a plurality of the collector contacts50for example three or more may be provided at positions having an equal distance from the emitter contact49. With regard to e.g. the collector contacts502,503, and504arranged so as to surround the emitter contact493of the row RL3with the same space D inFIG. 7, a triangle surrounded by the dotted lines connecting these collector contacts forms the isosceles triangle C1. The same mark as that ofFIG. 1toFIG. 6designates the same part. The triangle C1that is the arrangement pattern of the collector contact is congruent with the triangle E1that is the arrangement pattern of the emitter contact. The emitter wiring (not shown) extends in the second direction and connects commonly emitter contacts on a line. In the same way, the collector wiring (not shown) extends in the second direction and connects commonly collector contacts on a line adjacent to the emitter contact. Though the emitter wiring and the collector wiring are formed on the same layer surface, further miniaturization can be realized by patterning separately each wiring layer of a two-layered wiring layer having an inter-layer insulating layer intervening between the emitter wiring52and the collector wiring53.

Furthermore, though the power transistor31is formed so as to connect the PNP transistor units46together in parallel in the aforementioned embodiments and variations, a power transistor58can be formed by connecting NPN transistor units57together in parallel as the second variation shown inFIG. 7. Reference number59is an N−type silicon semiconductor substrate; number60is a P+buried layer; number61is a P−type base layer; number62is an N−isolation region, numbers63and64are a P++region and a P+region respectively of a guard ring65having a peripheral portion65A and a tilted portion65B; numbers66and67are an N++region and an N+region respectively of an emitter region68; and number69is an N+type collector region.

As has been clarified by the explanations mentioned above, the space between emitter regions can be narrowed and thereby the device can be miniaturized in accordance with the present invention. Moreover, the electric current can be effectively flown toward the collector region, so that the current efficiency can be improved thanks to the present invention.