SEMICONDUCTOR DEVICE AND METHOD

A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.

BACKGROUND

DETAILED DESCRIPTION

Embodiments will be described with respect to a specific context, namely, a contact plug structure of a semiconductor device and a method of forming the same. Various embodiments presented herein are discussed in the context of a Fin Field Effect Transistor (FinFET) device formed using a gate-last process. In other embodiments, a gate-first process may be used. Various embodiments may be applied, however, to dies comprising other types of transistors such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around (GAA), or the like) field effect transistors (NFETs/NSFETs), or the like in lieu of or in combination with the FinFETs. In some embodiments, silicide layers are formed on the contact plugs of a semiconductor device. The silicide layers may be used as an etch stop layer during subsequent processing steps, such as those for forming conductive features on the contact plugs. By forming a silicide as an etch stop layer, the overall number of manufacturing steps may be reduced, which can reduce manufacturing costs. The silicide may be formed using relatively low temperature processes, which can reduce thermal effects during device manufacturing. The use of the silicide layers as etch stops can also reduce the overall thickness of the device.

FIG.1illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring isolation regions56. Although the isolation regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring isolation regions56.

A gate dielectric layer92is along sidewalls and over a top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions82are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and the gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions82of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, a current flow between the source/drain regions82of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET. Subsequent figures refer to these reference cross-sections for clarity.

FIGS.2through25Bare cross-sectional views of intermediate stages in the manufacturing of FinFET devices, in accordance with some embodiments.FIGS.2through7illustrate reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.8A,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A, and25Aare illustrated along reference cross-section A-A illustrated inFIG.1, andFIGS.8B,9B,10B,11B,12B,13B,14B,14C,15B,16B,17B,18B,19B,20B,21B,22B,23B,24B, and25Bare illustrated along a similar cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.10C and10Dare illustrated along reference cross-section C-C illustrated inFIG.1, except for multiple fins/FinFETs.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region50N may be physically separated from the p-type region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P.

InFIG.3, fins52are formed in the substrate50, in accordance with some embodiments. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.

InFIG.4, an insulation material54is formed over the substrate50and between neighboring fins52, in accordance with some embodiments. The insulation material54may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material54is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material54is formed such that excess insulation material54covers the fins52. Although the insulation material54is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along surfaces of the substrate50and the fins52. Thereafter, a fill material such as those discussed above may be formed over the liner.

InFIG.5, a removal process is applied to the insulation material54to remove excess insulation material54over the fins52. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fins52such that top surfaces of the fins52and the insulation material54are substantially coplanar or level (e.g., within process variations of the planarization process) after the planarization process is completed. In embodiments in which a mask remains on the fins52, the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins52, respectively, and the insulation material54are level after the planarization process is completed.

InFIG.6, the insulation material54is recessed to form Shallow Trench Isolation (STI) regions56, in accordance with some embodiments. The insulation material54is recessed such that upper portions of fins52in the n-type region50N and in the p-type region50P protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etch. The STI regions56may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material54(e.g., etches the material of the insulation material54at a faster rate than the material of the fins52). For example, an oxide removal process using dilute hydrofluoric acid (dHF) may be used, though other processes are possible.

The process described with respect toFIGS.2through6is just one example of how the fins52may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52inFIG.5can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together.

Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., an NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

Further inFIG.6, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a P well may be formed in the n-type region50N, and an N well may be formed in the p-type region50P. In some embodiments, a P well or an N well are formed in both the n-type region50N and the p-type region50P. In the embodiments with different well types, the different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the n-type region50N. The photoresist is patterned to expose the p-type region50P of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following the implanting of the p-type region50P, a photoresist is formed over the fins52and the STI regions56in the p-type region50P. The photoresist is patterned to expose the n-type region50N of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After the implanting of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.7, a dummy dielectric layer60is formed on the fins52. The dummy dielectric layer60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layer60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layer60and then planarized using, for example, a CMP process. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be a conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. The dummy gate layer62may be made of other materials that have a high etching selectivity than materials of the STI regions56. The mask layer64may include, for example, one or more layers of silicon oxide, SiN, SiON, a combination thereof, or the like. In some embodiments, the mask layer64may comprise a layer of silicon nitride and a layer of silicon oxide over the layer of silicon nitride. In some embodiments, a single dummy gate layer62and a single mask layer64are formed across the region50N and the region50P. It is noted that the dummy dielectric layer60is shown covering only the fins52for illustrative purposes only. In some embodiments, the dummy dielectric layer60may be deposited such that the dummy dielectric layer60covers the STI regions56, extending between the dummy gate layer62and the STI regions56.

FIGS.8A through25Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.8A through25Billustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated inFIGS.8A through25Bmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure.

InFIGS.8A and8B, the mask layer64(seeFIG.7) may be patterned using acceptable photolithography and etching techniques to form masks74. The pattern of the masks74then may be transferred to the dummy gate layer62. In some embodiments (not illustrated), the pattern of the masks74may also be transferred to the dummy dielectric layer60by an acceptable etching technique to form dummy gates72. The dummy gates72cover respective channel regions58of the fins52. The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins52.

Further inFIGS.8A and8B, gate seal spacers80can be formed on exposed surfaces of the dummy gates72, the masks74, and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers80. The gate seal spacers80may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the formation of the gate seal spacers80, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above inFIG.6, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. In some embodiments, the lightly doped source/drain regions may have a concentration of impurities in the range of about 1015cm−3to about 1019cm−3. An anneal may be used to repair implant damage and/or to activate the implanted impurities.

InFIGS.9A and9B, gate spacers86are formed on the gate seal spacers80along sidewalls of the dummy gates72and the masks74. The gate spacers86may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers86may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacers86comprise multiple layers, which may be layers of different materials.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers80may not be etched prior to forming the gate spacers86, yielding “L-shaped” gate seal spacers, spacers may be formed and removed, and/or the like). Furthermore, the n-type and p-type devices may be formed using a different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers80while the LDD regions for p-type devices may be formed after forming the gate seal spacers80.

InFIGS.10A and10Bepitaxial source/drain regions82are formed in the fins52. The epitaxial source/drain regions82are formed in the fins52such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial source/drain regions82. In some embodiments the epitaxial source/drain regions82may extend into, and may also penetrate through, the fins52. In some embodiments, the gate spacers86are used to separate the epitaxial source/drain regions82from the dummy gates72by an appropriate lateral distance so that the epitaxial source/drain regions82do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions82may be selected to exert stress in the respective channel regions58, thereby improving performance.

The epitaxial source/drain regions82in the n-type region50N may be formed by masking the p-type region50P and etching source/drain regions of the fins52in the n-type region50N to form recesses in the fins52. Then, the epitaxial source/drain regions82in the n-type region50N are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the n-type region50N may include materials exerting a tensile strain in the channel region58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions82in the n-type region50N may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82in the p-type region50P may be formed by masking the n-type region50N and etching source/drain regions of the fins52in the p-type region50P to form recesses in the fins52. Then, the epitaxial source/drain regions82in the p-type region50P are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the p-type region50P may comprise materials exerting a compressive strain in the channel region58, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions82in the p-type region50P may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of about 1019cm−3to about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions82may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions82in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent source/drain regions82of a same FinFET to merge as illustrated byFIG.10C. In other embodiments, adjacent epitaxial source/drain regions82remain separated after the epitaxy process is completed as illustrated byFIG.10D. In the embodiments illustrated inFIGS.10C and10D, gate spacers86are formed covering a portion of the sidewalls of the fins52that extend above the STI regions56, thereby blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers86may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region56.

InFIGS.11A and11B, a first interlayer dielectric (ILD)88is deposited over the structure illustrated inFIGS.10A and10B. The first ILD88may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include pho spho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)87is disposed between the first ILD88and the epitaxial source/drain regions82, the masks74, and the gate spacers86. The CESL87may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD88.

InFIGS.12A and12B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD88with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the gate seal spacers80and the gate spacers86along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the gate seal spacers80, the gate spacers86, and the first ILD88are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD88. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD88with the top surface of the masks74.

InFIGS.13A and13B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that recesses90are formed. Portions of the dummy dielectric layer60in the recesses90may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layer60remains and is exposed by the recesses90. In some embodiments, the dummy dielectric layer60is removed from recesses90in a first region of a die (e.g., a core logic region) and remains in recesses90in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72with little or no etching of the first ILD88or the gate spacers86. Each recess90exposes and/or overlies a channel region58of a respective fin52. Each channel region58is disposed between neighboring pairs of the epitaxial source/drain regions82. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may then be optionally removed after the removal of the dummy gates72.

InFIGS.14A and14B, gate dielectric layers92and gate electrodes94are formed for replacement gates.FIG.14Cillustrates a detailed view of region89ofFIG.14B. Gate dielectric layers92one or more layers deposited in the recesses90, such as on the top surfaces and the sidewalls of the fins52and on sidewalls of the gate seal spacers80/gate spacers86. The gate dielectric layers92may also be formed on the top surface of the first ILD88. In some embodiments, the gate dielectric layers92comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers92include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers92may include a dielectric layer having a k-value greater than about 7.0. The formation methods of the gate dielectric layers92may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy dielectric layer60remains in the recesses90, the gate dielectric layers92include a material of the dummy dielectric layer60(e.g., silicon oxide or the like).

The gate electrodes94are deposited over the gate dielectric layers92, respectively, and fill the remaining portions of the recesses90. The gate electrodes94may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode94is illustrated inFIG.14B, the gate electrode94may comprise any number of liner layers94A, any number of work function tuning layers94B, and a fill material94C as illustrated byFIG.14C. After the filling of the recesses90, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers92and the material of the gate electrodes94, which excess portions are over the top surface of the first ILD88. The remaining portions of material of the gate electrodes94and the gate dielectric layers92thus form replacement gates of the resulting FinFETs. The gate electrodes94and the gate dielectric layers92may be collectively referred to as a “replacement gate,” a “gate structure,” or a “gate stack.” The gate and the gate stacks may extend along sidewalls of a channel region58of the fins52.

The formation of the gate dielectric layers92in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers92in each region are formed from the same materials, and the formation of the gate electrodes94may occur simultaneously such that the gate electrodes94in each region are formed from the same materials. In some embodiments, the gate dielectric layers92in each region may be formed by distinct processes, such that the gate dielectric layers92may be different materials, and/or the gate electrodes94in each region may be formed by distinct processes, such that the gate electrodes94may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.15A and15B, the gate stacks (e.g., the gate dielectric layers92and the gate electrodes94) are recessed and dielectric layers100are formed over the gate stacks, in accordance with some embodiments. The dielectric layers100may be formed, for example, by recessing the gate stacks and depositing the dielectric material of the dielectric layers100on the recessed gate stacks. In some embodiments, the gate stacks are recessed below the top surface of the first ILD88. The gate stacks may be recessed using one or more etch processes, which may include one or more wet etch processes, dry etch processes, or a combination thereof. The one or more etch processes may comprise anisotropic etch processes.

The dielectric layers100are then formed on the recessed gate stacks and over the first ILD88. In some embodiments, the dielectric layers100comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a metal oxide, another type of oxide, another type of nitride, a combination thereof, or the like, and may be formed using ALD, CVD, PVD, a combination thereof, or the like. The dielectric layers100may be formed in a self-aligned manner, and sidewalls of a dielectric layer100may be aligned with respective sidewalls of the gate seal spacers80or the gate spacers86. A planarization process, such as CMP process, may be performed to remove excess material of the dielectric layers100(e.g., from over the first ILD88). In some cases, surfaces of the dielectric layers100and surfaces of the first ILD88may be approximately level. In some embodiments, the dielectric layers100may be formed having a thickness in the range of about 5 nm to about 50 nm.

FIGS.16A through18Billustrate the formation of conductive features122(seeFIG.17B), in accordance with some embodiments. The conductive features122provide electrical connections to respective epitaxial source/drain regions82and in some cases may be considered “source/drain contact plugs” or the like.

FIGS.16A and16Billustrate a patterning process of the first ILD88and the CESL87to form openings118, in accordance with some embodiments. The openings118may expose surfaces of the epitaxial source/drain regions82. The patterning may be performed using acceptable photolithography and etching techniques. For example, a photoresist may be formed over the first ILD88and the dielectric layers100and patterned. The photoresist can be formed by using, for example, a spin-on technique and can be patterned using acceptable photolithography techniques. One or more suitable etch processes may be performed using the patterned photoresist as an etch mask, forming the openings118. The one or more etch processes may include wet and/or dry etch processes. One or more of the etch processes may be anisotropic.FIGS.16A-16Bshow the openings118as having sloped sidewalls, but the openings118may have substantially vertical sidewalls, curved sidewalls, or another sidewall profile than shown.

InFIGS.17A and17B, silicide layers120and conductive features122are formed in the openings118, in accordance with some embodiments. The silicide layers120may be formed, for example, by depositing a metallic material in the openings118. The metallic material may comprise Ti, Co, Ni, NiCo, Pt, NiPt, Ir, Ptlr, Er, Yb, Pd, Rh, Nb, a combination thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, a combination thereof, or the like. Subsequently, an annealing process is performed to form the silicide layers120. In some embodiments in which the epitaxial source/drain regions82comprise silicon, the annealing process may cause the metallic material to react with silicon to form a silicide of the metallic material at interfaces between the metallic material and the epitaxial source/drain regions82. After forming the silicide layers120, unreacted portions of the metallic material may be removed using a suitable removal process, such as a suitable etch process, for example.

After forming the silicide layers120, conductive features122are formed in the openings118. The conductive features122provide electrical connections to respective epitaxial source/drain regions82. In some embodiments, the conductive features122are formed by forming a liner (not shown), such as a barrier layer, an adhesion layer, or the like, and a conductive fill material are in the openings118. For example, a barrier layer may first be formed in the openings118. The barrier layer may extend along a bottom and sidewalls of the openings118. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. Subsequently, an adhesion layer (not individually shown) may be formed over the barrier layer within the openings118. The adhesion layer may comprise cobalt, ruthenium, an alloy thereof, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. The barrier layer and/or the adhesion layer may be omitted in other embodiments.

A conductive fill material is then formed in the openings118to form the conductive features122. The conductive fill material may comprise copper, aluminum, tungsten, ruthenium, cobalt, combinations thereof, alloys thereof, multilayers thereof, or the like, and may be formed using, for example, by plating, ALD, CVD, PVD, or other suitable methods. For example, in some embodiments, the conductive fill material may be formed by first forming a seed layer (not individually shown) over the adhesion layer within the openings118. The seed layer may comprise copper, titanium, nickel, gold, manganese, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. The conductive fill material may then be formed over the seed layer within the openings118. Other techniques for forming the conductive fill material are possible. The conductive features122may have top surfaces that are concave, convex, or flat, or may have top surfaces that are above or below the top surface of the first ILD88. Some conductive features122having different top surfaces are described below forFIGS.27A-27C.

In some embodiments, the conductive fill material overfills the openings118. After forming the conductive fill material, a planarization process may be performed to remove portions of the conductive fill material overfilling the openings118. If present, portions of the barrier layer, the adhesion layer, and/or the seed layer may also be removed. Remaining portions of the barrier layer, the adhesion layer, the seed layer, and the conductive fill material form the conductive features122in the openings118. The planarization process may comprise a CMP process, an etch back process, a grinding process, combinations thereof, or the like. After performing the planarization process, surfaces of the conductive features122and surfaces of the dielectric layers100may be substantially level. In other embodiments, a planarization process is not performed. In some embodiments, an optional anneal process is performed after the planarization process to recrystallize the conductive features122, to enlarge the grain structure of the conductive features122, to reduce micro-voids in the conductive features122, and/or to reduce impurities in the conductive features122.

InFIGS.18A and18B, silicide layers124are formed on the conductive features122, in accordance with some embodiments. In some embodiments, the silicide layers124may be used as etch stop layers during subsequent processing, described in greater detail below. For example, the silicide layers124may have a smaller etch rate than overlying layers such as the second ILD126(FIGS.19A-19B). The silicide layers124may comprise a silicide of the conductive fill material of the conductive features122. For example, in some embodiments, the conductive features122is cobalt and the silicide layers124are cobalt silicide (e.g., Co2Si, CoSi, CoSi2, CoSi3, or the like). In other embodiments, the silicide layers124comprise another silicide, such as nickel silicide. In still other embodiments, the silicide layers124may comprise a material such as tungsten, ruthenium, copper, combinations thereof, or the like. These are examples, and the conductive features122or silicide layers124may comprise other materials than these. In some cases, forming the silicide layers124may reduce the height of the conductive features122. For example, utilizing the silicide layers124as described herein may obviate the need to form a separate etch stop layer over the conductive features122.

In some embodiments, the silicide layers124may be formed by reacting a silicon-containing process gas with exposed conductive fill material of the conductive features122. As an example, silicide layers124of cobalt silicide may be formed on conductive features122of cobalt using a process gas comprising silane (SiH4), disilane (Si2H6), the like, or combinations thereof. In some embodiments, the process gas may have a flow rate in the range of about 1 sccm to about 1000 sccm. In some embodiments, the process gas may be mixed with a carrier gas such as H2, He, N2, Ar, or the like. The process gas may be flowed for a time between about 5 seconds and about 600 seconds, in some embodiments. The silicide layers124may be formed using a process temperature that is in the range of about 200° C. to about 600° C., in some embodiments. Other process parameters, process gases, or carrier gases are possible. In some embodiments, the silicide layers124may be formed having a thickness in the range of about 1 nm to about 10 nm, though other thicknesses are possible. A silicide layer124may have different regions with different thicknesses, in some cases. In some embodiments, the thickness of the silicide layers124may be controlled by controlling the flow rate and/or the flow time of the process gas.

In some embodiments, the silicide layers124may be formed such that each silicide layers124covers the respective conductive feature122. In some cases, the silicide layers124may extend between opposite sidewalls of the first ILD88and/or may extend on sidewall portions of the first ILD88. The silicide layers124may have top surfaces that are concave, convex, or flat, or may have top surfaces that are above or below the top surface of the first ILD88. Some silicide layers124having different top surfaces are described below forFIGS.28A-28C.

InFIGS.19A and19B, a second ILD126is formed over the first ILD88, the dielectric layers100, and the silicide layers124, in accordance with some embodiments. In some embodiments, the second ILD126is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD126may be a material similar to that of the first ILD88, and may be formed in a similar manner. For example, the second ILD126may be formed of a dielectric material such as an oxide, PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD or PECVD.

In some embodiments, the material of the silicide layers124and/or the material of the second ILD126are chosen such that the etch rate of the silicide layers124is less than the etch rate of the second ILD126. In this manner, the silicide layers124on the conductive features122may be considered etch stop layers. In some cases, because the silicide layers124may be used as etch stop layers over the conductive features122, the second ILD126may be formed over the first ILD88, the dielectric layers100, and the conductive features122without first depositing a separate etch stop layer (e.g., as a blanket layer). This is similar to the embodiment shown inFIGS.19A-19B, in which the second ILD126is deposited directly on the dielectric layers100and the first ILD88. Omitting the deposition of a separate etch stop layer in this manner can allow for a thinner overall device, fewer processing steps, and reduced manufacturing cost. Additionally, in some cases, the silicide layers124may be formed at a relatively low temperature, which can reduce the occurrence or severity of some thermal effects and can allow for the overall process to have a larger “thermal budget.” In other embodiments, a separate etch stop layer may be deposited over the first ILD88, the dielectric layers100, and the silicide layers124. An embodiment in which a separate etch stop layer129is utilized is described below forFIGS.30A-31B.

FIGS.20A and20Billustrate the patterning of the second ILD126and the dielectric layers100to form openings130and131, in accordance with some embodiments. The openings130and131extend through the second ILD126and the dielectric layers100to expose surfaces of the gate stacks (e.g., surfaces of the gate electrodes94). A conductive feature140(seeFIGS.24A-24B) is subsequently formed in the opening130and a portion of a combined conductive feature144(seeFIG.24B) is subsequently formed in the opening131. The conductive feature140and the combined conductive feature144make physical and electrical contact to their respective gate stacks.

The second ILD126and the dielectric layers100may be patterned using acceptable photolithography and etching techniques. For example, a first photoresist128may be formed over the second ILD126and patterned using suitable photolithography techniques. The first photoresist128may be a single layer or multilayer photoresist structure, and may be deposited using suitable techniques such as spin-on or deposition techniques. One or more suitable etch processes may then be performed using the patterned first photoresist128as an etch mask, forming the openings130and131. The one or more etch processes may include wet and/or dry etch processes.FIGS.20A-20Bshow the openings130and131as having sloped sidewalls, but the openings130or131may have substantially vertical sidewalls, curved sidewalls, or another sidewall profile in other embodiments. The first photoresist128may be removed using a suitable process such as an ashing or etching process.

InFIGS.21A and21B, a second photoresist132is formed over the second ILD126and within the openings130and131, in accordance with some embodiments. The second photoresist132may be a single layer or multilayer photoresist structure, and may be deposited using suitable techniques such as spin-on or deposition techniques. As shown inFIG.21B, the second photoresist132may overfill the openings130and131and extend over the second ILD126.

FIGS.22A and22Billustrate the patterning of the second photoresist132, the second ILD126, and the silicide layers124to form openings134and135, in accordance with some embodiments. The openings134and135extend through the second ILD126and the silicide layers124to expose surfaces of the conductive features122. A conductive feature142(seeFIGS.24A-24B) is subsequently formed in the opening134and a portion of the combined conductive feature144(seeFIG.24B) is also subsequently formed in the opening135. The conductive feature142and the combined conductive feature144make physical and electrical contact to their respective gate stacks.

The second photoresist132, the second ILD126and the silicide layers124may be patterned using acceptable photolithography and etching techniques. For example, the second photoresist132may first be formed over the second ILD126and patterned using suitable photolithography techniques. One or more suitable etch processes may then be performed using the patterned second photoresist132as an etch mask, forming the openings134and135. The one or more etch processes may include wet and/or dry etch processes. The etch process(es) may remove portions of the second ILD126and then stop or slow at the silicide layers124. Using the silicide layers124as an etch stop in this manner can reduce the chance of overetching, which can reduce the chance of forming leakage paths or other process defects. The etch process(es) may also remove portions of the silicide layers124to expose the conductive features122, or a separate etching step may be performed to remove the portions of the silicide layers124and expose the conductive features122. In some embodiments, this separate etching step may comprise an etching process that is different from an etching process used to etch the second ILD126. As shown inFIG.22B, the openings134or135may expose sidewall portions of the silicide layers124.

In some embodiments, the etch process(es) may also remove portions of the first ILD88, the CESL87, the gate spacers86, the gate seal spacers80, the dielectric layers100, and/or the second photoresist132. In some embodiments, the opening135overlaps the previously formed opening131. As such, the opening135may extend into a region of the second photoresist132within the previously formed opening131, as shown inFIG.22B.FIGS.22A-22Bshow the openings134and135as having sloped sidewalls, but the openings134or135may have substantially vertical sidewalls, curved sidewalls, or another sidewall profile in other embodiments.

The one or more etch processes may be chosen such that the etch rate of the silicide layers124is slower than the etch rate of the second ILD126or other layers. For example, in some embodiments, the etch process comprises a dry etch using one or more process gases such as CF4, CH2F2, CHF3, C4F6, O2, the like, or a combination thereof. The etch process may include a plasma power in the range of about 50 W to about 1000 W, a voltage bias in the range of about 0 V to about 450 V, a temperature in the range of about 20° C. to about 200° C., or a pressure in the range of about 5 mTorr to about 500 mTorr. Other process gases or process parameters are possible. In some embodiments, the etching selectivity of the second ILD126over the silicide layers124may be in the range of about 2:1 to about 4:1, though selectivities greater than about 4:1 are possible.

FIG.22Billustrates an embodiment in which the etch process(es) remove portions of the silicide layers124and expose portions of the conductive features122. In other embodiments, the etch process(es) may stop on or within the silicide layers124, leaving the conductive features122covered by the silicide layers124. In some embodiments, the subsequently formed conductive features140,142, or144(seeFIGS.24A-24B) may be formed on the silicide layers124covering the conductive features122. In some embodiments, the silicide layers124covering the conductive features122may be removed using a separate etch process. For example, the silicide layers124may be removed by a separate dry etch process that uses using one or more process gases such as CF4, CH2F2, CHF3, C4F6, H2, the like, or a combination thereof. Other etch processes are possible. In some embodiments, portions of the silicide layers124may be removed by a subsequently performed wet clean process, which may result in the conductive features122being exposed.

InFIGS.23A and23B, the second photoresist132is removed, forming openings130,134, and136, in accordance with some embodiments. The second photoresist132may be removed using a suitable technique, such as by ashing, etching, or the like. As shown inFIGS.23A-23B, removing the second photoresist132reveals the previously formed opening130that exposes a gate stack. Due to the overlap between the previously formed openings131and135, removing the second photoresist132forms a combined opening136that exposes the gate stack previously exposed by the opening131and the conductive feature122previously exposed by the opening135. The opening134remains exposing a conductive feature122. In some embodiments, a wet cleaning process is performed before and/or after removing the second photoresist132.

InFIGS.24A and24B, a conductive feature140, a conductive feature142, and a combined conductive feature144are formed respectively in the opening130, the opening134, and the combined opening136, in accordance with some embodiments. The conductive feature140makes electrical connection to a gate electrode94of a gate stack. Accordingly, the conductive feature140may be referred to as a gate contact or gate contact plug in some cases. The conductive feature142makes electrical connection to a conductive feature122that is electrically connected to an epitaxial source/drain region82. Accordingly, a combination of the conductive feature142and the underlying conductive feature122may be also referred to as a source/drain contact or a source/drain contact plug in some cases. The combined conductive feature144is electrically connected to both a gate stack and an epitaxial source/drain region82(through a conductive feature122). In this manner, a FinFET device comprising gate contact plugs and source/drain contact plugs may be formed.

As an example of forming the conductive features140,142and144, a liner (not shown), such as a barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings130,134, and136. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD126. The remaining liner and conductive material form the conductive features140,142and144. The conductive features140,142and144may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that the conductive features140,142and/or144may be formed in different cross-sections, which may avoid shorting.

InFIGS.25A and25B, in some embodiments, an interconnect structure comprising one or more layers of conductive features are formed over and electrically connected to the conductive features140,142, and144. In some embodiments, the interconnect structure comprises a plurality of dielectric layers such as inter-metal dielectrics (IMDs) and conductive features within the IMDs that provide various electrical interconnections.FIGS.26A-26Billustrate an IMD152with conductive features150and an IMD155with conductive features154, but more or fewer IMDs or conductive features may be formed in other embodiments. The conductive features may comprise electrical routing, conductive vias, conductive lines, or the like, and may be formed using a single damascene method, a dual damascene method, a combination thereof, or the like.

As an example of forming the IMD152and conductive features150, an etch stop layer151may first be deposited over the second ILD126and conductive features140,142, and144. The etch stop layer151may comprise a material such as silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, the like, or combinations thereof. Other materials are possible. The IMD152may then be formed over the etch stop layer151. The IMD152may be a material similar to that described for the first ILD88or the second ILD126, and may be formed in a similar manner. In some embodiments, the IMD152may be formed of a low-k dielectric material having a k-value lower than about 3.5. Other materials or techniques are possible.

Openings may then be patterned in the IMD152and the etch stop layer151to expose surfaces of the conductive features140,142, and/or144. An optional liner (not shown) may first be formed in the openings, which may be similar to the liner described previously for the conductive features140,142, and144. A conductive material may be deposited within the openings to form the conductive features150. The conductive material may be similar to those described for the conductive features140,142, and144, and may be formed in a similar manner. Other conductive materials or techniques are possible. A planarization process may be performed to remove excess conductive material from the IMD152.FIGS.25A-25Bshow the conductive features150as having sloped sidewalls, but the conductive features150may have substantially vertical sidewalls, curved sidewalls, or another sidewall profile in other embodiments.

The conductive features154may be formed in a similar manner as the conductive features150, in some embodiments. For example, an etch stop layer153may be formed over the IMD152and conductive features150, and the IMD155may be formed over the IMD152. The etch stop layer153and the IMD152may be patterned to form openings. Some of the openings may expose the conductive features150. A liner and a conductive material may then be deposited in the openings, and a CMP process may be performed to remove excess materials. This is an example, and other techniques are possible.

The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around (GAA), or the like) field effect transistors (NFETs/NSFETs). As an example,FIGS.26A and26Bare cross-sectional views of a nanostructure device, in accordance with some embodiments. The nanostructure device is similar to the FinFET device shown inFIGS.25A-25B, except for the formation of active regions comprising nanostructures160rather than active regions comprising fins52. Similar features inFIGS.25A-25BandFIGS.26A-26Bmay be labeled by similar numerical references, and descriptions of the similar features are not repeated herein. In an NSFET embodiment, the fins as described for the FinFET embodiment are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. Replacement gate structures (e.g., gate stacks) are formed in a manner similar to the above-described embodiments. The replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices.

For example, in the nanostructure device ofFIGS.26A-26B, active regions comprise a plurality of nanostructures160such that each nanostructure160is surrounded by a portion of a respective gate stack comprising gate dielectric layers92and gate electrodes94. The nanostructures160may comprise nanosheets, nanowires, or the like. In some embodiments, the nanostructures160and the substrate50comprise a similar semiconductor material. In other embodiments, the nanostructures160and the substrate50comprise different semiconductor materials. In some embodiments, portions of the gate stacks are interposed between adjacent nanostructures160. In some embodiments, spacers162are interposed between the portions of the gate stacks and the epitaxial source/drain regions82and act as isolation features between the gate stacks and the epitaxial source/drain regions82. In some embodiments, the spacers162comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as a low-k dielectric material, may be utilized. Conductive features contacting the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. For example, a silicide layer124may be formed on the conductive features122, which may be similar to the silicide layers124described previously. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety.

FIGS.27A,27B, and27Cillustrate conductive features122having respective top surfaces that are flat, concave, and convex, in accordance with some embodiments. The conductive features122shown inFIGS.27A-27Cmay be similar to those described forFIGS.17A-17B. For example,FIGS.27A-27Cshow conductive features122after a planarization process has been performed on a conductive fill material. In some embodiments, the profile of the top surfaces of the conductive features122may be controlled by controlling the parameters of the planarization process, such as controlling the slurry properties, the polish rate, or the like.

FIG.27Aillustrates a conductive feature122having a flat top surface, in accordance with some embodiments. The conductive feature122may have a flat top surface that is level with top surfaces of the first ILD88and/or the dielectric layers100. In other embodiments, the flat top surface of the conductive feature122may be below top surfaces of the first ILD88and/or the dielectric layers100(not illustrated). In some cases, an anneal process performed after the planarization process may reduce the height of the conductive feature122such that the top surface of the conductive feature122may be below top surfaces of the first ILD88and/or the dielectric layers100. In some embodiments, a flat top surface may be formed by controlling the planarization process, as described above.

FIG.27Billustrates a conductive feature122having a convex top surface, in accordance with some embodiments. In some cases, an anneal process performed after the planarization process may cause the conductive fill material of the conductive feature122to reflow and form a convex top surface. In some embodiments, a convex top surface may be formed by controlling the planarization process, as described above. The convex top surface may protrude above the top surfaces of the first ILD88and/or the dielectric layers100, as shown inFIG.27B. In some cases, a conductive feature122having a convex top surface may allow for improved contact (e.g., less resistance) between the conductive feature122and an overlying conductive feature, such as conductive features140,142, or144shown inFIGS.24A-24B. The improved contact may be due to, for example, increased contact surface area.

FIG.27Cillustrates a conductive feature122having a concave top surface, in accordance with some embodiments. In some cases, an anneal process performed after the planarization process may reduce the height of a conductive feature122such that the conductive feature122forms a concave top surface. In some embodiments, a concave top surface may be formed by controlling the planarization process, as described above. For example, the concave top surface may be formed from “dishing” during the planarization process. The concave top surface may be below the top surfaces of the first ILD88and/or the dielectric layers100, as shown inFIG.27C.

FIGS.28A,28B, and28Cshow silicide layers124formed on the conductive features122ofFIGS.27A,27B, and27C, in accordance with some embodiments. The silicide layers124shown inFIGS.28A-28Cmay be similar to the silicide layers124described previously forFIGS.18A-18B, and may be formed using similar techniques.FIG.28Ashows a silicide layer124formed on the flat top surface of the conductive feature122ofFIG.17A, in accordance with some embodiments. The silicide layer124may have a substantially flat top surface or a convex top surface, which may be below, above, or about level with the top surfaces of the first ILD88and/or the dielectric layers100.FIG.28Bshows a silicide layer124formed on the convex top surface of the conductive feature122ofFIG.17B, in accordance with some embodiments. The silicide layer124may have a convex shape, as shown inFIG.28B. The silicide layer124may have a concave bottom surface.FIG.28Cshows a silicide layer124formed on the concave top surface of the conductive feature122ofFIG.17C, in accordance with some embodiments. The silicide layer124may have a concave top surface, a substantially flat top surface, or a convex top surface, which may be below, above, or about level with the top surfaces of the first ILD88and/or the dielectric layers100. The silicide layer124may have a convex bottom surface. Silicide layers124having other shapes or profiles are possible.

FIGS.29A,29B, and29Cillustrate conductive features122and overlying conductive features142having different relative widths, in accordance with some embodiments. The conductive features122may be similar to the conductive features122described previously forFIG.18B. For example, silicide layers124may be formed on the conductive features122using techniques described herein. The conductive features142may be similar to the conductive features142described previously forFIG.24B. In each of theFIGS.29A-29C, the width of the top surface of the conductive feature122is labeled “W1” and the width of the bottom surface of the overlying conductive feature142is labeled “W2.”

FIG.29Aillustrates a conductive feature142having a width W2that is less than the width W1of a conductive feature122, in accordance with some embodiments. As shown inFIG.29A, forming a conductive feature142having a width W2less than width W1can result in portions of the silicide layer124remaining on the conductive feature122after formation of the conductive feature142. In some cases, the conductive feature142may extend through the silicide layer124, and portions of the conductive feature142may be covered by portions of the silicide layer124. In some embodiments, the conductive features142may be at least partially surrounded by portions of the silicide layer124. In some cases, forming a conductive feature142having a relatively smaller W2can reduce the risk of via-via leakage, via bridging defects, “tiger-tooth” defects, defects resulting from photolithography overlay issues, or the like.

FIG.29Billustrates a conductive feature142having a width W2that is approximately the same as the width W1of a conductive feature122, in accordance with some embodiments. In some cases, forming a conductive feature142having a width W2about the same as width W1can reduce the risk of via-via leakage, via bridging defects, “tiger-tooth” defects, defects resulting from photolithography overlay issues, or the like.FIG.29Cillustrates a conductive feature142having a width W2that is larger than the width W1of a conductive feature122, in accordance with some embodiments. In some cases, forming a conductive feature142having a width W2larger than width W1can increase the contact area between the conductive feature122and the conductive feature142. Increasing the contact area in this manner can reduce contact resistance between the conductive feature122and the conductive feature142and improve device performance.

FIGS.30A and30Billustrate an embodiment in which an etch stop layer129is formed over the silicide layers124. In some cases, the use of the silicide layers124can allow for a thinner etch stop layer129to be formed over the conductive features122, which can reduce the overall thickness of the device.FIGS.30A-30Billustrate a structure similar to that shown inFIGS.18A-18B, except that an etch stop layer129is deposited over the silicide layers124, the first ILD88, the dielectric layers100, and other exposed layers.

The etch stop layer129may comprise a dielectric material, such as silicon nitride, silicon oxy-nitride, silicon carbide, silicon carbo-nitride, a metal oxide, a metal nitride, the like, or a combination thereof. The etch stop layer129may be deposited using one or more suitable techniques, such as CVD, ALD, PVD, or the like. In some embodiments, the etch stop layer129may have a thickness that is in the range of about 1 nm to about 20 nm, though other thicknesses are possible. The etch stop layer129may be deposited as a blanket layer.

InFIGS.31A and31B, conductive features140,142, and144are formed on the structure shown inFIGS.30A-30B, in accordance with some embodiments. The conductive features140,142, and144may be similar to those described previously forFIGS.24A-24B, and may be formed using techniques similar to those described forFIGS.19A through24B. For example, a second ILD126may be formed over the etch stop layer129and patterned to form openings exposing gate stacks and/or conductive features122. The second ILD126may be similar to the second ILD described forFIGS.19A-19B, and the openings may be patterned using techniques similar to those described forFIGS.20A through23B. In some embodiments, the etch stop layer129is used as an etch stop when patterning the openings that expose the gate stacks and/or conductive features122. For example, the material of the etch stop layer129may have a lower etch rate than the material of the overlying second ILD126. The openings may extend through the etch stop layer129. Conductive material may then be deposited within the openings to form the conductive features140,142, and144. Other techniques for forming the conductive features140,142, and/or144are possible.

The embodiments described here have some advantages. For example, a silicide may be formed on a conductive feature to use as an etch stop instead of depositing a blanket etch stop layer over the structure. This can reduce the overall thickness of the device. Additionally, the use of a silicide as an etch stop can reduce the number of process steps, which can reduce manufacturing costs. In some cases, a silicide may be formed at a lower temperature than an etch stop layer. This can improve the overall “thermal budget” of the manufacturing process, which can improve yield, process flexibility, or device performance.

In accordance with some embodiments of the present disclosure, a method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug. In an embodiment, the silicide layer includes a cobalt silicide. In an embodiment, etching the opening leaves the contact plug free of the silicide layer. In an embodiment, a top surface of the silicide layer protrudes above a top surface of the first ILD. In an embodiment, the second ILD is silicon oxide. In an embodiment, the method the silicide layer laterally surrounds the conductive feature. In an embodiment, the second ILD physically contacts the silicide layer and the first ILD. In an embodiment, the method includes forming nanostructures over the substrate, wherein the gate structure surrounds each of the nanostructures.

In accordance with some embodiments of the present disclosure, a method includes forming a fin protruding from a substrate; forming a gate stack on sidewalls of the fin and over the fin; forming a source/drain region in the fin adjacent the gate stack; forming a first conductive feature on the source/drain region, wherein the first conductive feature electrically contacts the source/drain region; forming a silicide layer on the top surface of the first conductive feature; forming an insulating layer over the gate stack and over the silicide layer, wherein the insulating layer physically contacts the silicide layer; performing a first etching process to etch an opening in the insulating layer, wherein the first etching process selectively etches the material of the insulating layer more than the material of the silicide layer; and forming a second conductive feature in the opening, wherein the second conductive feature extends through the insulating layer and the silicide layer to physically and electrically contact the first conductive feature. In an embodiment, the silicide layer is used as an etch stop for the first etching process. In an embodiment, forming the second conductive feature includes etching the silicide layer using a second etching process, wherein the second etching process is different from the first etching process. In an embodiment, forming the silicide layer includes exposing the first conductive feature to a silane gas. In an embodiment, the second conductive feature physically and electrically contacts the gate stack. In an embodiment, forming the first conductive feature includes performing a planarization process and performing an anneal process after the planarization process.

In accordance with some embodiments of the present disclosure a device includes a fin protruding from a substrate; a gate stack along sidewalls of the fin and over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; a contact plug physically and electrically contacting a top surface of the epitaxial source/drain region; a silicide layer on a top surface of the contact plug; a first isolation region on a top surface of the silicide layer; and a conductive feature in the first isolation region and on the top surface of the contact plug, wherein a bottom surface of the conductive feature physically and electrically contacts the top surface of the contact plug, wherein the bottom surface of the conductive feature is below the top surface of the silicide layer. In an embodiment, the conductive feature includes cobalt and the silicide layer includes a cobalt silicide. In an embodiment, a top surface of the first isolation region and a top surface of the conductive feature are level. In an embodiment, the device includes a second isolation region surrounding the contact plug, wherein the top surface of the silicide layer is below a top surface of the second isolation region. In an embodiment, the silicide layer encircles the conductive feature.