Method and apparatus for sensing in charge trapping non-volatile memory

A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge trapping memory with a bias arrangement that reads the contents of different positions in the charge trapping structure of the memory cell with great sensitivity.

2. Description of Related Art

Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry name PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.

Conventional memory cell structures rely on the reverse read operation to determine the contents of the memory structure. However, the reverse read technique effectively couples together multiple locations of the charge trapping structure, even when only portion of the charge trapping structure contains data of interest. This dependence constrains the difficulty of using the charge trapping structure as nonvolatile memory, by narrowing the sensing window of currents measured from the reverse read technique. Less data are stored in the charge trapping structure than otherwise possible.

Thus, a need exists for a charge trapping memory cell that can be read without suffering substantial coupling between multiple locations of the charge trapping structure, even when only a portion of the charge trapping structure contains data of interest.

SUMMARY OF THE INVENTION

A method of operating a memory cell, an architecture for an integrated circuit including such a memory cell, and a method of manufacturing such memory, are provided.

A nonvolatile memory according to the described technology comprises a substrate region including source and drain regions, a bottom dielectric coupled to the substrate region, a charge trapping structure coupled to the bottom dielectric, a top dielectric coupled to the charge trapping structure, a gate coupled to the top dielectric, and logic. The charge trapping structure has a part corresponding to the source region and another part corresponding to the drain region. Each of the parts of the charge trapping structure has a charge storage state, which stores one bit or multiple bits, depending on the application and design of the memory cell. The logic applies a bias arrangement to determine the charge storage state, and measures current, including band-to-band tunneling current, flowing between the substrate region and one of the source region or the drain region to determine the charge storage state.

The voltage difference between the gate and one of the source region or the drain region creates an electric field which causes band bending in one of the source region or the drain region. The degree of band bending is affected by the charge storage state of the part of the charge trapping structure corresponding to one of the source region or the drain region, resulting in a band-to-band tunneling current in one of the source region or the drain region that varies with the charge storage state. In some embodiments, the bias arrangement applies a reverse bias voltage difference between the substrate region and one of the source region or the drain region, and floats the other of the source region or the drain region. Such a bias arrangement results in the avoidance of substantial coupling between the part of the charge trapping structure corresponding to the source region and the part of the charge trapping structure corresponding to the drain region. A current measurement that determines the charge storage state of the charge trapping structure corresponding to the source region is substantially independent of the charge storage state of the charge trapping structure corresponding to the drain region, and vice versa.

In some embodiments, the bias arrangement causes a first voltage difference between the gate and the one of the source region or the drain region, and a second voltage difference between the substrate region and the one of the source and drain regions. The first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for the measuring. However, the first voltage difference and the second voltage differences fail to change the charge storage state. Any hot holes generated during the first bias arrangement are insufficient to disturb the charge storage state. Thus, the read operation is not destructive of the data stored in the charge trapping structure. In some embodiments the first voltage difference is at least about 5 V between the gate and the one of the source region or the drain region, and the second voltage difference less than about 5 V between the substrate region and the one of the source region or the drain region.

In some embodiments, the substrate region is a well in a semiconductor substrate. In other embodiments, the substrate region is simply the semiconductor substrate.

In some embodiments, the logic applies a second bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure, and applies a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure. Net positive charge is increased in the charge trapping structure via current mechanisms such as band-to-band hot hole tunneling. Net negative charge is increased in the charge trapping structure via current mechanisms such as electron tunneling, Fowler-Nordheim tunneling, channel hot electron injection current, and channel initiated secondary electron injection current. In some embodiments, the measured current is at least about 10 times greater for the charge storage state adjusted by one of the second bias arrangement and the third bias arrangement than said measured current for the charge storage state adjusted by the other of the second bias arrangement and the third bias arrangement, for example about 100 nA for one measurement and about 1 nA for the other measurement.

Other embodiments of the technology described above include a method for measuring current flowing between the substrate region and one of the source region or the drain region, and a method of manufacturing nonvolatile memory according to the described technology.

Another embodiments of the technology described above include an integrated circuit with an array of memory cells that includes multiple bit lines and a pass transistor coupled to each bit line. The having according to the described technology.

Other aspects and advantages of the technology presented herein can be understood with reference to the figures, the detailed description and the claims, which follow.

DETAILED DESCRIPTION

FIG. 1Ais a simplified diagram of a charge trapping memory cell, showing a read operation being performed on the source side of the charge trapping structure. The p-doped substrate region170includes n+ doped source and drain regions150and160. The remainder of the memory cell includes a bottom dielectric structure140on the substrate, a charge trapping structure130on the bottom dielectric structure140(bottom oxide), a top dielectric structure120(top oxide) on the charge trapping structure130, and a gate110on the oxide structure120. Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al2O3. Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al2O3, HfO2, and others. The charge trapping structure may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawing.

The memory cell for PHINES-like cells has, for example, a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers, and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers.

In some embodiments, the gate comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni-T, metal nitrides, and metal oxides including but not limited to RuO2. High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the top dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV. For p-type polysilicon gates with silicon dioxide top dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide top dielectric.

In the diagram ofFIG. 1A, the drain side of the memory cell has been programmed, for example via band-to-band hole injection into the drain side of the charge trapping structure130. The source side of the memory cell has been erased, for example via a channel reset operation injecting electrons via Fowler-Nordheim tunneling from the gate110to the charge trapping structure130, and from the charge trapping structure130to the substrate170.

In the bias arrangement ofFIG. 1Afor reading the source side of the charge trapping structure130, the voltage of the gate110is −10 V, the voltage of the source150is 2 V, the voltage of the drain160is floating, and the voltage of the substrate170is 0 V. The memory cell ofFIG. 1Bis similar to memory cell ofFIG. 1A, except that a read operation is being performed on the drain side of the charge trapping structure rather than on the source side. In the bias arrangement ofFIG. 1Bfor reading the drain side of the charge trapping structure130, the voltage of the gate110is −10 V, the voltage of the source150is floating, the voltage of the drain160is 2 V, and the voltage of the substrate170is 0 V. The bias arrangement is determined among the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B), but to keep the potential difference between the substrate170and the source150(FIG. 1A) or the drain160(FIG. 1B) low enough such that programming does not occur, as discussed in connection withFIG. 2A.

In this bias arrangements ofFIGS. 1A and 1B, the area of the junction between the p doped substrate170, and either the n+ doped source150or the n+ doped drain160, and displays the behavior of a reverse biased p-n junction. However, the gate voltage causes the energy bands to bend sufficiently such that band-to-band tunneling occurs in the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B). The high doping concentration in the source150or the drain160, the resulting high charge density of the space charge region, and the accompanying short length of the space charge region over which the voltage changes, contribute to the sharp energy band bending. Electrons in the valence band tunnel through the forbidden gap to the conduction band and drift down the potential hill, deeper into either the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B). Similarly, holes drift up the potential hill, away from either the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B), and toward the p doped substrate170.

The voltage of the gate110controls the voltage of the portion of the substrate170by the bottom dielectric structure140(bottom oxide). In turn, the voltage of the portion of the substrate170by the bottom dielectric structure140(bottom oxide) controls the degree of band bending between the bottom dielectric structure140(bottom oxide), and either the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B). As the voltage of the gate110becomes more negative, the voltage of the portion of the substrate170by the bottom dielectric structure140(bottom oxide) becomes more negative, resulting in deeper band bending in either the n+ doped source150(FIG. 1A) or the n+ doped drain160(FIG. 1B). More band-to-band current flows, as a result of at least some combination of 1) an increasing overlap between occupied electron energy levels on one side of the bending energy bands, and unoccupied electron energy levels on the other side of bending energy bands, and 2) a narrower barrier width between the occupied electron energy levels and the unoccupied electron energy levels (Sze,Physics of Semiconductor Devices,1981).

As mentioned above, the drain side of the charge trapping structure130is programmed and occupied by holes, whereas the source side of the charge trapping structure130is erased and occupied by fewer holes than the drain side of the charge trapping structure130. As a result, in accordance with Gauss's Law, when −10 V is applied to the gate110, the bottom dielectric structure140(bottom oxide) is biased more negatively on the source side than on the drain side. Thus, more current flows between the source150and the substrate170in the bias arrangement shown inFIG. 1Afor reading the source side of the charge trapping structure130than flows between the drain160and the substrate170in the bias arrangement shown inFIG. 1Bfor reading the drain side of the charge trapping structure130.

The difference in the bias arrangements ofFIGS. 1A and 1Bfor reading, and the bias arrangement ofFIG. 2Afor programming, show a careful balance. For reading, the potential difference between the source region or the drain region should not cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state. In contrast, for programming, the potential difference between the source region or the drain region is sufficient to cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state.

FIGS. 2A,2B, and2C are simplified diagrams of a memory cell that show program and erase operations being performed on the memory cell. As generally used herein, programming refers to making more positive the net charge stored in the charge trapping structure, such as by the addition of holes to or the removal of electrons from the charge trapping. Also as generally used herein, erasing refers to making more negative the net charge stored in the charge trapping structure, such as by the removal of holes from or the addition of electrons to the charge trapping structure. However, the invention encompasses both products and methods where programming refers to making the net charge stored in the charge trapping structure more negative or more positive, and products and methods where erasing refers to making the net charge stored in the charge trapping structure more negative or more positive.

InFIG. 2A, programming is accomplished using band-to-band tunneling induced hot hole injection, and inFIGS. 2B and 2C, erasing is accomplished using the negative gate voltage, E-field induced electron tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current from the gate to the charge trapping structure, or by using the negative substrate voltage, E-field induced electron tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current from the substrate to the charge trapping structure. Thus, as illustrated inFIG. 2A, a right bit is programmed by applying 5 V to the drain260, 0 V to the source250, and −6 V to the gate210, while the substrate270is grounded. This induces hot holes having sufficient energy to jump over the tunnel dielectric240into drain side233of the charge trapping structure230, as shown by hole234which is stored in the drain side233of the charge trapping structure230. Similarly, a left bit is programmed by applying 5 V to the source250, 0 V to the drain260, and −6 V to the gate210, while the substrate270is grounded (not shown). This induces hot holes having sufficient energy to jump over the bottom dielectric structure240into the source side of the charge trapping structure230.FIG. 2Billustrates E-field assisted electron tunneling across top dielectric structure220and bottom dielectric structure240used for erase, induced by relatively high negative bias on the gate, and relatively high positive bias on the substrate. Both bits in the memory cell are simultaneously erased in the illustrated example by applying −20 V to the gate, and grounding the substrate, while both the source and the drain are floating.FIG. 2Cillustrates E-field assisted electron tunneling used for erase, induced by relatively high negative bias on the substrate, drain, and source; and relatively high positive bias on the gate. Both bits in the memory cell are simultaneously erased in the illustrated example by applying −20 V to the substrate, source, and drain; and grounding the gate. Other program and erase techniques can be used in operation algorithms applied to the PHINES type memory cell, as described for example in U.S. Pat. No. 6,690,601. Other memory cells and other operation algorithms might also be used.

FIGS. 3A and 3Bare graphs that contrast the sensing windows of an ideal memory cell with the sensing window of a memory cell that is read by a reverse read operation. Curve310represents the read current of the first bit. Curve320represents the read current of the second bit. During time interval330, the first bit is undergoing programming. During time interval340, the second bit is undergoing programming. Due to the program operation (via hot hole injection), the current (channel current) will increase in a reverse read operation and the current (BTB current) will drop in a BTB sensing operation. The read current interval is represented by the sensing window350of the memory cell.

InFIG. 3A, the ideal memory cell has a relatively wide sensing window350. During the time interval330, as the first bit is undergoing programming, the read current curve of the first bit310increases from a lowest level to a highest level. The programming of the first bit during the time interval330does not substantially affect the read current curve of the second bit320. During the time interval340, as the second bit is undergoing programming, the read current curve of the second bit320increases from a lowest level to a highest level. The programming of the second bit during the time interval340does not substantially affect the read current curve of the first bit310.

InFIG. 3B, the memory cell read by a reverse read operation has a relatively narrow sensing window350due to the second bit effect, as explained below. During the time interval330, as the first bit is undergoing programming, the read current curve of the first bit310increases from a lowest level360to a high level364. Consequently, the programming of the first bit during the time interval330substantially affects the read current curve of the second bit320, which increases from a lowest level360to a low level362. During the time interval340, as the second bit is undergoing programming, the read current curve of the second bit320increases from a low level362to a highest level366. Consequently, the programming of the second bit during the time interval340substantially affects the read current curve of the first bit310, which increases from a high level364to a highest level366. Thus, when performing a reverse read operation on a memory cell on one bit, the resulting read current is substantially affected by the programmed or erased status of the other bit, because for a given gate voltage it becomes more difficult during the reverse read operation to force the substrate portion under the other bit into depletion and inversion, and to punch through the portion of the substrate under the other bit.

FIGS. 4A,4B, and4C are graphs that show program, erase, and band-to-band read operations being performed on the memory cell.

In the graph ofFIG. 4A, a memory cell with both first and second charge trapping parts in a programmed state are erased via E-field assisted electron tunneling, induced by relatively high negative bias on the gate, and relatively high positive bias on the substrate. Both charge trapping parts in the memory cell are simultaneously erased in the graph by applying −19.5 V to the gate, and grounding the substrate, while both the source and the drain are floating. For each data point, the read operation is performed by applying −10 V to the gate, 2 V to one of the drain or source depending on the portion of the charge trapping structure being read, floating the other terminal of the drain or source, and grounding the substrate. If the source side of the charge trapping structure is being read, then 2 V is applied to the source and the drain is floated. If the drain side of the charge trapping structure is being read, then 2 V is applied to the drain and the source is floated.

In the graph ofFIG. 4B, the first charge trapping part undergoes programming, and in the graph ofFIG. 4C, the second charge trapping part undergoes programming. Curve410represents the read current of the first charge trapping part. Curve420represents the read current of the second charge trapping part. InFIG. 4B, the first charge trapping part is programmed by applying −8V to the gate and 5 V to the first terminal (the terminal closer to the storing the first charge trapping part of the charge trapping structure), floating the second terminal (the terminal farther from the first charge trapping part of the charge trapping structure), and grounding the substrate. InFIG. 4B, as the first charge trapping part is undergoing programming, the read current curve of the first charge trapping part410drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the first charge trapping part does not substantially affect the read current curve of the second charge trapping part420. InFIG. 4C, the second charge trapping part is programmed by applying −8V to the gate and 5 V to the second terminal (the terminal closer to the second charge trapping part of the charge trapping structure), floating the first terminal (the terminal farther from the second charge trapping part of the charge trapping structure storing), and grounding the substrate. InFIG. 4C, as the second charge trapping part is undergoing programming, the read current curve of the second charge trapping part420drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the second charge trapping part does not substantially affect the read current curve of the first charge trapping part410. For each data point inFIGS. 4B and 4C, the read operation is performed by applying −10 V to the gate, 2 V to one of the drain or source depending on the portion of the charge trapping structure being read, floating the other terminal of the drain or source, and grounding the substrate. If the source side of the charge trapping structure is being read, then 2 V is applied to the source and the drain is floated. If the drain side of the charge trapping structure is being read, then 2 V is applied to the drain and the source is floated.

The sensing window shown inFIGS. 4B and 4Cis relatively wide, because the band-to-band read operation is local to either the first terminal or the second terminal. The read current resulting from a band-to-band read operation performed on the first charge trapping part is relatively insensitive to the logical state of the second charge trapping part, and the read current resulting from a band-to-band read operation performed on the second charge trapping part is relatively insensitive to the logical state of the first charge trapping part. The band-to-band read operation is relatively free of the second charge trapping part effect which characterizes the reverse read operation, where the read current resulting from a read operation performed on one side of the charge trapping structure is relatively dependent on the data stored on the other side of the charge trapping structure. Each charge trapping part can store one bit or multiple bits. For example, if each charge trapping part stores two bits, then there are four discrete levels of charge.

FIGS. 5A and 5Bare simplified diagrams of memory cell strings that show program operations being performed on the memory cell.

InFIG. 5A, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. The voltage of the substrate502is 0 V. The gate of the memory cell540selected to be programmed has a voltage of −5 V. More specifically, one portion of the charge trapping structure542is selected to be programmed. The portion of the charge trapping structure to be programmed542is selected by applying a voltage of 10 V to the gate of the pass transistor510, turning on the pass transistor510. Further, a voltage of 10 V is applied to the gates of memory cells520and530. These gate voltages electrically couple a first bit line505with a voltage of 5 V to one of the source/drain region of the selected memory cell540. The selected portion of the charge trapping structure542corresponding to one of the source/drain region is programmed, for example via band-to-band hot hole programming. The remaining transistors in the string of memory cells are turned off by applying a voltage of 0 V to the gates of memory cells550,560,570, and580; and to the gate of the pass transistor590. These gate voltages electrically decouple a second bit line595from the other of the source/drain region of the selected memory cell540. The unselected portion of the charge trapping structure corresponding to the other of the source/drain region is not programmed.

InFIG. 5B, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. However, a gate voltage of 0 V is applied to the gate of the pass transistor510and to the gates of the memory cells520and530. Also, a gate voltage of 10 V is applied to the gate of the pass transistor590and to the gates of the memory cells550,560,570, and580. In contrast with the bias arrangement ofFIG. 5A, where the bit line505is electrically coupled to one of the source or drain of the memory cell540to program the portion of the charge trapping structure542, in the bias arrangement ofFIG. 5Bthe bit line595is electrically coupled to the other of the source or drain of the memory cell540to program the portion of the charge trapping structure544.

FIGS. 6A and 6Bare simplified diagrams of memory cell strings that show read operations being performed on the memory cell.

InFIG. 6A, one of the memory cells of the string of memory cells including N memory cells coupled in series is read. The voltage of the substrate602is 0 V. The gate of the memory cell640selected to be read has a voltage of −10 V. More specifically, one portion of the charge trapping structure642is selected to be read. The portion of the charge trapping structure to be read642is selected by applying a voltage of 10 V to the gate of the pass transistor610, turning on the pass transistor610. Further, a voltage of 10 V is applied to the gates of memory cells620and630. These gate voltages electrically couple a first bit line605with a voltage of 2 V to one of the source/drain region of the selected memory cell640. The selected portion of the charge trapping structure642corresponding to one of the source/drain region is read, for example via band-to-band current sensing. The remaining transistors in the string of memory cells are turned off by applying a voltage of 0 V to the gates of memory cells650,660,670, and680; and to the gate of the pass transistor690. These gate voltages electrically decouple a second bit line695from the other of the source/drain region of the selected memory cell640. The unselected portion of the charge trapping structure corresponding to the other of the source/drain region is not read.

InFIG. 6B, one of the memory cells of the string of memory cells including N memory cells coupled in series is programmed. However, a gate voltage of 0 V is applied to the gate of the pass transistor610and to the gates of the memory cells620and630. Also, a gate voltage of 10 V is applied to the gate of the pass transistor690and to the gates of the memory cells660,660,670, and680. In contrast with the bias arrangement ofFIG. 6A, where the first bit line605is electrically coupled to one of the source or drain of the memory cell640to read the portion of the charge trapping structure642, in the bias arrangement ofFIG. 6Bthe second bit line695is electrically coupled to the other of the source or drain of the memory cell640to read the portion of the charge trapping structure644.

FIGS. 7A and 7Bare simplified diagrams of memory cell strings that show erase operations being performed on the memory cells.

InFIG. 7A, all of the memory cells of the string of memory cells including N memory cells coupled in series are erased. The voltage of the substrate702is 10 V. The gates of the memory cells to be erased720,730,740,750,760,770, and780have a voltage of −10 V. The gates of pass transistors710and790are floating. The bit lines705and795are floating. The memory cells720,730,740,750,760,770, and780are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the substrate.

InFIG. 7B, all of the memory cells of the string of memory cells including N memory cells coupled in series are erased. The voltage of the substrate702is −10 V. The gates of the memory cells to be erased720,730,740,750,760,770, and780have a voltage of 10 V. The voltage of the gates of pass transistors710and790is 5V. The voltage of bit lines705and795is −10V. The memory cells720,730,740,750,760,770, and780are erased, for example via FN tunneling of electrons from the substrate to the charge trapping structure and from the charge trapping structure to the gate.

InFIG. 8, each column of memory cells is electrically coupled to at most one bit line804. Stated another way, the architecture inFIG. 8differs from the architecture ofFIG. 6in that the first bit line605and the second bit line695are permanently electrically coupled. Memory cells in the column of memory cells are selected by turning on word lines which set the gate voltages of the memory cells820,830,840,850,860,870, and880. An example of a way to control which portion of a given memory cell is read or programmed is by turning on one of pass transistors810and890and turning off the other of pass transistors810and890. Although the pass transistors810and890shown inFIG. 8are not memory cells, in other embodiments one or both pass transistors810and890are also memory cells with charge trapping structures.

InFIG. 9, an array of memory cells is erased, with multiple strings each including N memory cells coupled in series. The voltage of the substrate902is 10 V. The word lines of the memory cells to be erased920,930,940,950,960,970, and980have a voltage of −10 V. The word lines of pass transistors910and990have a voltage of 0 V. The bit lines903,904,905,906, and907are floating. The memory cells of the array are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the substrate.

InFIG. 10, an array of memory cells is erased, with multiple strings each including N memory cells coupled in series. The voltage of the substrate1002is −10 V. The word lines of the memory cells to be erased1020,1030,1040,1050,1060,1070, and1080have a voltage of 10 V. The word lines of pass transistors1010and1090have a voltage of 5 V. The bit lines1003,1004,1005,1006, and1007have a voltage of −10 V. The memory cells of the array are erased, for example via FN tunneling of electrons from the substrate (including drain and source) to the charge trapping structure and from the charge trapping structure to the gate.

InFIG. 11, several memory cells are programmed in an array of memory cells with multiple strings each including N memory cells coupled in series. The voltage of the substrate1102is 0 V. The word line1140of the memory cells to be programmed has a voltage of −5 V. With the memory cells selected by the word line1140, the charge trapping structure parts1143,1144,1145,1146, and1147are selected by turning on the pass transistor word line1110with a voltage of 10 V. The voltages of the intervening memory cell word lines1120and1130is set to 10 V. The other pass transistor word line1190and the remaining memory cell word lines1150,1160,1170, and1180are turned off with a voltage of 0 V. Out of the selected charge trapping structure parts1143,1144,1145,1146, and1147, the charge trapping structure parts1144,1146, and1147are programmed by setting the voltages of the bit lines1104,1106, and1107to 5 V. Out of the selected charge trapping structure parts1143,1144,1145,1146, and1147, the charge trapping structure parts1143and1145are not programmed, by setting the voltages of the bit lines1103and1105to 0 V.

InFIG. 12, several memory cells are programmed similar toFIG. 11. The voltage of the substrate1202is 0 V. However, with the memory cells selected by the word line1240, the charge trapping structure parts1243,1244,1245,1246, and1247are selected by turning on the pass transistor word line1290with a voltage of 10 V. The voltages of the intervening memory cell word lines1250,1260,1270, and1280is set to 10 V. The other pass transistor word line1210and the remaining memory cell word lines1220and1230are turned off with a voltage of 0 V. Out of the selected charge trapping structure parts1243,1244,1245,1246, and1247, the charge trapping structure parts1244,1246, and1247are programmed by setting the voltages of the bit lines1204,1206, and1207to 5 V. Out of the selected charge trapping structure parts1243,1244,1245,1246, and1247, the charge trapping structure parts1243and1245are not programmed, by setting the voltages of the bit lines1203and1205to 0 V.

InFIG. 13, several memory cells are read in an array of memory cells with multiple strings each including N memory cells coupled in series. The voltage of the substrate1302is 0 V. The word line1340of the memory cells to be read has a voltage of −10 V. With the memory cells selected by the word line1340, the charge trapping structure parts1343,1344,1345,1346, and1347are selected by turning on the pass transistor word line1310with a voltage of 10 V. The voltages of the intervening memory cell word lines1320and1330are set to 10 V. The other pass transistor word line1390and the remaining memory cell word lines1350,1360,1370, and1380are turned off with a voltage of 0 V. The selected charge trapping structure parts1343,1344,1345,1346, and1347, are read by setting the voltages of the bit lines1303,1304,1305,1306, and1307to 2 V. In other embodiments, a subset of all the bit lines are read by setting the voltages to 2 V for only the bit lines of interest.

InFIG. 14, several memory cells are read similar toFIG. 13. The voltage of the substrate1402is 0 V. However, with the memory cells selected by the word line1440, the charge trapping structure parts1443,1444,1445,1446, and1447are selected by turning on the pass transistor word line1490with a voltage of 10 V. The voltages of the intervening memory cell word lines1450,1460,1470, and1480are set to 10 V. The other pass transistor word line1410and the remaining memory cell word lines1420and1430are turned off with a voltage of 0 V. The selected charge trapping structure parts1443,1444,1445,1446, and1447, are read by setting the voltages of the bit lines1403,1404,1405,1406, and1407to 2 V. In other embodiments, a subset of all the bit lines are read by setting the voltages to 2 V for only the bit lines of interest.

FIG. 15is a simplified block diagram of an integrated circuit according to an embodiment. The integrated circuit1550includes a memory array1500implemented using charge trapping memory cells, on a semiconductor substrate. A row decoder1501is coupled to a plurality of word lines1502arranged along rows in the memory array1500. A column decoder1503is coupled to a plurality of bit lines1504arranged along columns in the memory array1500. Addresses are supplied on bus1505to column decoder1503and row decoder1501. Sense amplifiers and data-in structures in block1506are coupled to the column decoder1503via data bus1507. Data is supplied via the data-in line1511from input/output ports on the integrated circuit1550, or from other data sources internal or external to the integrated circuit1550, to the data-in structures in block1506. Data is supplied via the data-out line1515from the sense amplifiers in block1506to input/output ports on the integrated circuit1550, or to other data destinations internal or external to the integrated circuit1550. A bias arrangement state machine1509controls the application of bias arrangement supply voltages1508, such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells, such as with the band-to-band currents.

FIG. 16is a simplified diagram of a charge trapping memory cell, showing the substrate region as a well. The p-doped substrate region1670is a well in the n-type substrate1680. The p-doped substrate region1670includes n+ doped source and drain regions1650and1660. The remainder of the memory cell includes a bottom dielectric structure1640on the substrate region1670, a charge trapping structure1630on the bottom dielectric structure1640(bottom oxide), a top dielectric structure1620(top oxide) on the charge trapping structure1630, and a gate1610on the top dielectric structure1620.