Imaging device

An imaging device according to the present disclosure includes: a photoelectric converter generating signal charge; a semiconductor substrate including a first semiconductor layer on a surface; a charge accumulation region of a first conductivity type in the first semiconductor layer; a first transistor including, as a source or a drain, a first impurity region of the first conductivity type in the first semiconductor layer; and a blocking structure between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of a second conductivity type in the first semiconductor layer, between the charge accumulation region and the first impurity region, and a first electrode above the first semiconductor layer, overlapping at least part of the second impurity region in plan view, the first electrode being configured to be applied with a constant voltage in a period when the charge accumulation region accumulates the signal charge.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging device.

2. Description of the Related Art

Charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors are in widespread use in digital cameras and the like. These image sensors have photodiodes formed on a semiconductor substrate, which is a well-known fact.

A structure is being proposed where a photoelectric conversion layer is disposed above the semiconductor substrate instead of the photodiodes, as disclosed in International Publication Nos. 2014/002330 and 2012/147302, for example. Imaging device that has this sort of structure may be referred to as stacked imaging devices. In a stacked imaging device, charges generated by photoelectric conversion are temporarily accumulated in diffusion regions and the like formed in the semiconductor substrate, as signal charges. Signals corresponding to the amount of charges accumulated are read out via a CCD circuit or CMOS circuit formed on the semiconductor substrate.

SUMMARY

If charges that are different from signal charges expressing an image flow into diffusion regions temporarily storing signals charges, this can lead to noise. Noise causes deterioration of the obtained image. It is advantageous to be able to suppress unintended movement of charges. Hereinafter, such unintended movement of charges may be referred to as a leak current.

One non-limiting and exemplary embodiment provides the following.

In one general aspect, the techniques disclosed here feature an imaging device including: a photoelectric converter that generates a signal charge by photoelectric conversion of light; a semiconductor substrate that includes a first semiconductor layer on a surface of the semiconductor substrate; a charge accumulation region that is an impurity region of a first conductivity type in the first semiconductor layer, the charge accumulation region being configured to accumulate the signal charge; a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the first semiconductor layer; and a blocking structure that is located between the charge accumulation region and the first transistor, wherein the blocking structure includes a second impurity region of a second conductivity type in the first semiconductor layer, the second impurity region being located between the charge accumulation region and the first impurity region, the second conductivity type being different from the first conductivity type, and a first electrode that is located above the first semiconductor layer, the first electrode overlapping at least a part of the second impurity region in a plan view, the first electrode being configured to be applied with a first voltage in a period when the charge accumulation region accumulates the signal charge, the first voltage being a constant voltage.

It should be noted that general or specific embodiments may be implemented as an element, a device, a module, system, or a method. General or specific embodiments may be implemented as any selective combination of element, device, module, system, and method.

DETAILED DESCRIPTION

Aspects of the present disclosure are as described below.

a photoelectric converter that generates a signal charge by photoelectric conversion of light;

a semiconductor substrate that includes a first semiconductor layer on a surface of the semiconductor substrate;

a charge accumulation region that is an impurity region of a first conductivity type in the first semiconductor layer, the charge accumulation region being configured to accumulate the signal charge;

a first transistor that includes, as a source or a drain, a first impurity region of the first conductivity type in the first semiconductor layer; and

a blocking structure that is located between the charge accumulation region and the first transistor, wherein

the blocking structure includesa second impurity region of a second conductivity type in the first semiconductor layer, the second impurity region being located between the charge accumulation region and the first impurity region, the second conductivity type being different from the first conductivity type, anda first electrode that is located above the first semiconductor layer, the first electrode overlapping at least a part of the second impurity region in a plan view, the first electrode being configured to be applied with a first voltage in a period when the charge accumulation region accumulates the signal charge, the first voltage being a constant voltage.
Item 2

The imaging device according to Item 1, wherein the second impurity region has a first region located on the surface of the semiconductor substrate, the first electrode overlapping at least a part of the first region in the plan view.

The imaging device according to either of Item 1 or 2, further including:

a third impurity region of the second conductivity type in the first semiconductor layer, the third impurity region being adjacent to the charge accumulation region.

The imaging device according to Item 3, wherein

the semiconductor substrate includesa supporting substrate of the second conductivity type, anda second semiconductor layer of the first conductivity type, the second semiconductor layer being located between the supporting substrate and the first semiconductor layer.
Item 5

The imaging device according to any one of Items 1 through 4, wherein the first conductivity type is n-type.

The imaging device according to Item 5, wherein

the first electrode includes an n-type impurity, and

the first voltage is 0 V or a negative voltage.

The imaging device according to Item 5, wherein

the first electrode includes a p-type impurity, and

the first voltage is 1 V or less.

The imaging device according to any one of Items 1 through 7, wherein the blocking structure includes a fourth impurity region of the second conductivity type in the first semiconductor layer, the fourth impurity region being located between the charge accumulation region and the first impurity region, the fourth impurity region being different from the second impurity region.

The imaging device according to Item 8, wherein the first electrode overlaps at least a part of the fourth impurity region in the plan view.

The imaging device according to either Item 1 or 2, further comprising:

multi-layer wiring that is located above the semiconductor substrate, the multi-layer wiring including a first wiring layer closest to the first semiconductor layer, and

the first electrode is a part of the first wiring layer.

The imaging device according to Item 10, wherein

the semiconductor substrate includesa supporting substrate of the second conductivity type, anda second semiconductor layer of the first conductivity type, the second semiconductor layer being located between the supporting substrate and the first semiconductor layer.
Item 12

The imaging device according to either Item 10 or 11, wherein

the first conductivity type is n-type, and

the first voltage is equal to or less than a substrate potential.

The imaging device according to Item 12, wherein

the multi-layer wiring includes a second wiring layer that is located farther from the semiconductor substrate than the first wiring layer is, and

a part of the second wiring layer covers the charge accumulation region and the first impurity region in the plan view, the part of the second wiring layer being configured to be applied with a voltage equal to or greater than the substrate potential.

The imaging device according to either Item 10 or 11, wherein

the first conductivity type is p-type, and

the first voltage is equal to or greater than a substrate potential.

The imaging device according to Item 14, wherein

the multi-layer wiring includes a second wiring layer that is located farther from the semiconductor substrate than the first wiring layer is,

a part of the second wiring layer covers the charge accumulation region and the first impurity region in the plan view, the part of the second wiring layer being configured to be applied with a voltage equal to or less than the substrate potential.

An imaging device including one or more pixels, wherein

each of the one or more pixels includesa photoelectric converter,a semiconductor substrate having a charge accumulation region of a first conductivity type that is electrically connected to the photoelectric converter,a first transistor having a gate that is electrically connected to the photoelectric converter,a second transistor having the charge accumulation region as one of a source and a drain, anda first electrode that is located above the semiconductor substrate, and that is applied with a first voltage of constant potential during the entirety of a charge accumulation period where a charge generated by the photoelectric converter is accumulated in the charge accumulation region,

the semiconductor substrate further includesa first impurity region of a first conductivity type, that is electrically isolated from the charge accumulation region, anda second impurity region and a third impurity region of a second conductivity type that are disposed in the semiconductor substrate separated from each other between the charge accumulation region and the first impurity region,

the first transistor includes the first impurity region as one of a source and a drain, and

the first electrode covers at least a part of the second impurity region and at least a part of the third impurity region.

According to the configuration of Item 16, charges of inverse polarity from charges moving from the first impurity region toward the charge accumulation region can be concentrated in a region below the first electrode, by applying a negative voltage, for example, to the first electrode. The charges moving from the first impurity region toward the charge accumulation region can be eliminated by recombination, by accumulation of the charges of inverse polarity, contamination of the charge accumulation region by excess charges can be suppressed, and image deterioration due to leak current can be suppressed.

The imaging device according to Item 16, wherein at least one of a region of the second impurity region covered by the first electrode and a region of the third impurity region covered by the first electrode is located on a surface of the semiconductor substrate.

The imaging device according to either Item 16 or 17, wherein

the semiconductor substrate includes a first semiconductor layer of the second conductivity type, and

the charge accumulation region is located in the first semiconductor layer.

According to the configuration of Item 18, a region having a relatively low concentration of impurity can be disposed around a portion where a contact plug that has electrical connection to the photoelectric converter comes into contact with the semiconductor substrate. Accordingly, the electric field intensity at a p-n junction formed between the charge accumulation region and the periphery thereof can be reduced, for example.

The imaging device according to Item 18, wherein

the semiconductor substrate includesa supporting substrate of the second conductivity type, anda second semiconductor layer located on the supporting substrate and having the first conductivity type, and

the second semiconductor layer is located between the supporting substrate and the first semiconductor layer.

According to the configuration of Item 19, inflow of minority carriers from peripheral circuits, for example, to the charge accumulation region is suppressed by the second semiconductor layer. Accordingly, effects of suppressed deterioration of image can be obtained.

The imaging device according to any one of Items 16 through 19, wherein the first conductivity type is n-type.

According to the configuration of Item 20, a p-type silicon substrate can be used as the semiconductor substrate.

The imaging device according to Item 20, wherein

the first electrode includes an n-type impurity, and

the first voltage is 0 V or a negative voltage.

According to the configuration of Item 21, charges of inverse polarity from charges generated at the p-n junction of the first impurity region and moving toward the charge accumulation region are concentrated in a region of the semiconductor substrate directly beneath the first electrode and near the surface. Accordingly, even if there are charges generated at the p-n junction of the first impurity region and moving toward the charge accumulation region, such charges can be eliminated by recombination at the region below the first electrode.

The imaging device according to Item 20, wherein

the first electrode includes a p-type impurity, and

the first voltage is a voltage of 1 V or less.

According to the configuration of Item 22, the same effects as Item 21 can be obtained.

An imaging device including one or more pixels, wherein

each of the one or more pixels includesa photoelectric converter,a semiconductor substrate having a first semiconductor layer of a second conductivity type, and a charge accumulation region of a first conductivity type that is located in the first semiconductor layer and electrically connected to the photoelectric converter,a first transistor having a gate that is electrically connected to the photoelectric converter,a second transistor having the charge accumulation region as one of a source and a drain,a first electrode that is located above the semiconductor substrate, and that is applied with a first voltage of constant potential during the entirety of a charge accumulation period when charges generated by the photoelectric converter are accumulated in the charge accumulation region, andmulti-layer wiring located above the semiconductor substrate, and including a first wiring layer and a second wiring layer that each extend over multiple pixels,

the semiconductor substrate further includesa first impurity region of a first conductivity type, that is electrically isolated from the charge accumulation region, anda second impurity region of the second conductivity type that is located between the charge accumulation region and the first impurity region, and that has a higher concentration of impurity than the first semiconductor layer,

the first transistor includes the first impurity region as one of a source and a drain, and

the first wiring layer is located closest to the semiconductor substrate of the wiring layers included in the multi-layer wiring, and includes, as a part thereof, a first wiring portion serving as the first electrode located between the charge accumulation region and the first impurity region in a plan view.

According to the configuration of Item 23, part of the wiring layer located above the semiconductor substrate can be used as the first electrode, and the same effects as Item 16 can be obtained.

The imaging device according to Item 23,

wherein the first electrode covers at least a part of the second impurity region in the plan view,

and wherein the region of the second impurity region covered by the first electrode is located at the surface of the semiconductor substrate.

The imaging device according to either Item 23 or 24, wherein

the semiconductor substrate includesa supporting substrate of the second conductivity type, anda second semiconductor layer located on the supporting substrate and having the first conductivity type, and

the second semiconductor layer is located between the supporting substrate and the first semiconductor layer.

According to the configuration of Item 25, effects the same as Item 19 can be obtained.

The imaging device according to any one of Items 23 through 25, wherein

the first conductivity type is n-type, and

the first voltage is a voltage of substrate potential or less.

According to the configuration of Item 26, the same effects as Item 21 can be obtained.

The imaging device according to Item 26, wherein

the second wiring layer is located farther from the semiconductor substrate than the first wiring layer is, and includes a second wiring portion that covers the charge accumulation region and the first impurity region in the plan view, and is applied with a voltage of the substrate potential or greater.

According to the configuration of Item 27, the second wiring layer is located in an upper layer from the gates of the first and second transistors, so the shape of the second wiring portion in the plan view can be made to be a shape crossing the charge accumulation region, for example. Also, the first electrode functions as a shielding electrode, so a voltage different from the first voltage can be applied to the second wiring portion.

The imaging device according to any one of Items 23 through 25, wherein

the first conductivity type is p-type, and

the first voltage is a voltage of a substrate potential or greater.

According to the configuration of Item 28, the same effects as Item 22 can be obtained.

The imaging device according to Item 28, wherein

the second wiring layer is located farther from the semiconductor substrate than the first wiring layer is, and includes a second wiring portion that covers the charge accumulation region and the first impurity region in the plan view, and is applied with a voltage of the substrate potential or greater.

According to the configuration of Item 29, the same effects as Item 27 can be obtained.

Embodiments of the present disclosure will be described in detail below, with reference to the drawings. Note that the embodiments described below are all general or specific examples of the technology of the present disclosure. Accordingly, values, shapes, materials, components, layout and connection state of the components, steps, the order of steps, and so forth illustrated in the following embodiments, are only exemplary, and are not intended to restrict the present disclosure. Various aspects described in the present embodiment may be combined with each other to the extent that there is no conflict. Components in the following embodiments which are not included in an independent Claim indicating a highest order concept are described as optional components. Components having substantially the same functions may be denoted by common reference numerals, and description thereof omitted in the description below. Also, illustrations of a part of the elements may be omitted, to avoid the drawings from becoming excessively complicated.

First Embodiment

FIG. 1illustrates an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. The imaging device100illustrated inFIG. 1has multiple pixels10formed on a semiconductor substrate60, and peripheral circuits.

The pixels10each include a photoelectric converter12. The photoelectric converter12receives incident light, and generates positive and negative charges, typically a hole-electron pair. The photoelectric converter12may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate60, and may be a photodiode formed on the semiconductor substrate60. Although the photoelectric converters12of the pixel10are illustrated inFIG. 1spatially separated from each other, but this is only for convenience in describing, and the photoelectric converters12of the multiple pixels10may be continuously laid out on the semiconductor substrate60without spacing therebetween.

In the example illustrated inFIG. 1, the pixels10are arrayed in multiple rows and columns, of m rows and n columns. Here, m and n are independent integers of 1 or greater. A two-dimensional array, for example, of the pixels10on the semiconductor substrate60, forms an imaging region R1. In a case where pixels10have a photoelectric conversion structure above the semiconductor substrate60, for example, as the photoelectric converters12, the imaging region R1can be defined as a region of the semiconductor substrate60that is covered by the photoelectric conversion structure.

The number and layout of the pixels10are not restricted to those illustrated. For example, the number of pixels10included in the imaging device100may be one. Although the pixels10are arrayed with the centers thereof located on grid points of a square grid in this example, the multiple pixels10may be laid out such that the centers of the pixels10are located on grid points of a triangular grid, a hexagonal grid, or the like, for example. The imaging device100may be used as a line sensor by arraying the pixels10one-dimensionally, for example.

The peripheral circuits in the configuration exemplified inFIG. 1include a vertical scanning circuit42and a horizontal signal readout circuit44. The peripheral circuits may additionally include a control circuit46and voltage supply circuit48, as exemplified inFIG. 1. The circuits included in the peripheral circuits are provided on the semiconductor substrate60in the example illustrated inFIG. 1. Note, however, that part of the peripheral circuits may be provided on another substrate that is different from the semiconductor substrate60on which the pixels10are formed.

The vertical scanning circuit42is also referred to as a row scanning circuit, and connects to address signal lines34provided corresponding to each row of the multiple pixels10. The signal line provided corresponding to each row of the multiple pixels10is not restricted to the address signal line34, and multiple types of signal lines may be connected to the vertical scanning circuit42for each row of multiple pixels10, which will be described later. The horizontal signal readout circuit44is also referred to as a column scanning circuit, and has connection with vertical signal lines35provided corresponding to each column of the multiple pixels10.

The control circuit46receives command data, clock, and so forth, provided from the outside of the imaging device100for example, and controls the entire imaging device100. Typically, the control circuit46has a timing generator, and supplies drive signals to the vertical scanning circuit42, horizontal signal readout circuit44, voltage supply circuit48, and so forth. Note that the arrows extending from the control circuit46inFIG. 1schematically represent the flow of output signals from the control circuit46. The control circuit46may be realized by a microcontroller including one or more processor, for example. The functions of the control circuit46may be realized by a combination of general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

The voltage supply circuit48supplies a predetermined voltage to the pixels10via the voltage line38. The voltage supply circuit48is not restricted to a particular power source circuit, and may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit48may be part of the above-described vertical scanning circuit42. These circuits making up the peripheral circuits typically are laid out in a peripheral region R2outside of the imaging region R1, as schematically illustrated inFIG. 1.

FIG. 2schematically illustrates an exemplary circuit configuration of the imaging device according to the first embodiment of the present disclosure. Four pixels10A, in a 2-row 2-column array, are representatively illustrated inFIG. 2, to avoid the drawing from becoming complicated. These pixels10A each are an example of the pixels10illustrated inFIG. 1. The pixels10A each have a photoelectric conversion structure12A serving as the photoelectric converter12, and include a signal detection circuit14A electrically connected to the photoelectric conversion structure12A. The photoelectric conversion structure12A includes a photoelectric conversion layer disposed above the semiconductor substrate60, which will be described later in detail with reference to the drawings. That is to say, a stacked imaging device is exemplified here as the imaging device100. Note that in the present specification, terms such as “above”, “below”, “upper face”, and “lower face”, are used only to specify the relative positions among parts, and do not restrict the attitude of the imaging device when in use.

The photoelectric conversion structures12A of the pixels10A have connection with an accumulation control line31. When the imaging device100is operating, a predetermined voltage is applied to the accumulation control line31. For example, in a case of using, of the positive and negative charges generated by photoelectric conversion, the positive charge as the signal charge, a positive voltage of around 10 V, for example, may be applied to the accumulation control line31when the imaging device100is operating. A case of using holes as signal charges will be exemplified below.

In the configuration exemplified inFIG. 2, the signal detection circuit14A includes a signal detecting transistor22, an address transistor24, and a reset transistor26. The signal detecting transistor22, address transistor24, and reset transistor26typically are field-effect transistors formed on the semiconductor substrate60supporting the photoelectric conversion structures12A, which will be described later in detail with reference to the drawings. An example of using an N-channel metal-oxide-semiconductor (MOS) device as the transistors will be described below, unless specifically stated otherwise.

The gate of the signal detecting transistor22is electrically connected to the photoelectric conversion structure12A, as schematically illustrated inFIG. 2. Holes, for example, can be accumulated in the charge accumulation node FD as a signal charge by applying a predetermined voltage to the accumulation control line31when operating. The charge accumulation node FD is a node connecting the gate of the signal detecting transistor22to the photoelectric converter12, and includes an impurity region formed on the semiconductor substrate60as a part thereof, which will be described later with reference to the drawings. In the example illustrated inFIG. 2, the charge accumulation node FD has a function of temporarily storing charges generated by the photoelectric conversion structure12A.

The drain of the signal detecting transistor22is connected to power source wiring32that supplies power source voltage VDD around 3.3 V for example, to the pixels10A when the imaging device100is operating. The source of the signal detecting transistor22is connected to the vertical signal line35via the address transistor24. The signal detecting transistor22receives supply of the power source voltage VDD at the drain thereof, and thereby outputs signal voltage in accordance with the amount of the signal charge accumulated at the charge accumulation node FD.

The address signal line34is connected to the gate of the address transistor24connected between the signal detecting transistor22and the vertical signal line35. Accordingly, the vertical scanning circuit42can read output of the signal detecting transistor22of a selected pixel10A to the corresponding vertical signal line35by applying, to the address signal line34, a row-selection signal that controls on and off of the address transistor24. Note that the layout of the address transistor24is not restricted to the example illustrated inFIG. 2, and may be between the drain of the signal detecting transistor22and the power source wiring32.

A load circuit45and column signal processing circuit47are connected to each vertical signal line35. The load circuit45makes up a source follower circuit along with the signal detecting transistor22. The column signal processing circuit47is also referred to as a row signal accumulating circuit, and performs noise suppression signal processing of which correlated double sampling is representative, analog/digital conversion, and so forth. The horizontal signal readout circuit44sequentially reads signals from multiple column signal processing circuits47to a horizontal common signal line49. The load circuit45and column signal processing circuit47may be a part of the above-described peripheral circuits.

A reset signal line36that has connection with the vertical scanning circuit42is connected to the gate of the reset transistor26. A reset signal line36is provided to each row of multiple pixel10A in the same way as the address signal line34. The vertical scanning circuit42can select pixels10A to be the object of resetting, in increments of rows, by applying row selection signals to the address signal line34. The vertical scanning circuit42can switch the reset transistors26of the selected row on by applying a reset signal to the gate of the reset transistor26via the reset signal line36. The potential of the charge accumulation node FD is reset by the reset transistor26going on.

In this example, one of the drain and source of the reset transistor26is connected to the charge accumulation node FD, and the other of the drain and source is connected to a corresponding one of feedback lines53provided to each row of the multiple pixels10A. That is to say, the voltage of the feedback line53is supplied to the charge accumulation node FD as a reset voltage to initialize the charge of the photoelectric converter12in this example.

In the configuration exemplified inFIG. 2, the imaging device100has a feedback circuit16A that includes an inverting amplifier50in a part of its feedback path. An inverting amplifier50is provided to each of multiple columns of the multiple pixels10A, with the above-described feedback line53being connected to the output terminal of a corresponding one of the multiple inverting amplifiers50, as illustrated inFIG. 2. The inverting amplifier50may be part of the above-described peripheral circuits.

An inverting input terminal of the inverting amplifier50is connected to the vertical signal line35of a corresponding column, as illustrated inFIG. 2. When the imaging device100is operating, reference voltage Vref that is a positive voltage of 1 V or around 1 V, for example, is supplied to the non-inverting input terminal of the inverting amplifier50. Turning the address transistor24and reset transistor26on enables a feedback path for negative feedback of the pixel10A to be formed, and formation of the feedback path causes the voltage of the vertical signal line35to converge to the input reference voltage Vref to the non-inverting input terminal of the inverting amplifier50. In other words, formation of the feedback path resets the voltage of the charge accumulation node FD, so that the voltage of the vertical signal line35is Vref. The voltage of an optional magnitude within the range of power source voltage to ground voltage can be used as the reference voltage Vref. Forming the feedback path enables reset noise generated by the reset transistor26going off to be reduced. Details of suppression of reset noise using feedback are described in International Publication No. 2012/147302. International Publication No. 2012/147302 is incorporated herein by reference in its entirety, for reference.

Device Structure of Pixel10A

FIG. 3schematically illustrates an example of the device structure of the pixel10A.FIG. 4illustrates an example of the layout of the elements in the pixel10A.FIG. 4schematically illustrates the layout of the elements formed on the semiconductor substrate60when viewing the pixel10A illustrated inFIG. 3along the normal direction of the semiconductor substrate60. Taking a cross-section of the pixel10A along lines III-Ill inFIG. 4and unfolding yields the cross-section illustrated inFIG. 3.

ReferencingFIG. 3, the pixel10A includes the semiconductor substrate60, the photoelectric conversion structure12A disposed above the semiconductor substrate60, and a conductive structure89. The photoelectric conversion structure12A is supported by an inter-layer insulating layer90that covers the semiconductor substrate60. The conductive structure89is disposed within the inter-layer insulating layer90. In the exemplified example, the inter-layer insulating layer90includes multiple insulating layers. The conductive structure89includes part of each of multiple wiring layers disposed within the inter-layer insulating layer90. The multiple wiring layers disposed within the inter-layer insulating layer90may include, for example, a wiring layer that includes the address signal line34and reset signal line36and so forth as a part thereof, and a wiring layer that includes the vertical signal line35, power source wiring32, and feedback line53and so forth as a part thereof. It is needless to say that the number of insulating layers and number of wiring layers in the inter-layer insulating layer90is not restricted in particular in this example, and is optionally settable.

The photoelectric conversion structure12A includes a pixel electrode12aformed on the inter-layer insulating layer90, an opposing electrode12con the incident light side, and a photoelectric conversion layer12bdisposed between these electrodes. The photoelectric conversion layer12bof the photoelectric conversion structure12A is formed of an organic material or an inorganic material such as amorphous silicon or the like, and generates positive and negative charges by photoelectric conversion upon receiving incident light via the opposing electrode12c. The photoelectric conversion layer12btypically is formed continuously over multiple pixels10A. The photoelectric conversion layer12bmay include a layer made up of an organic material and a layer made up of an inorganic material.

The opposing electrode12cis a translucent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or the like. Note that the term “translucent” as used in the present specification means that at least part of light of a wavelength that the photoelectric conversion layer12bcan absorb is transmitted, and transmission of light over the entire wavelength spectrum of visible light is not indispensable. Typically, the opposing electrode12cis formed over multiple pixels10A in the same way as the photoelectric conversion layer12b. The opposing electrode12chas connection with the above-described accumulation control line31, although this is omitted from illustration inFIG. 3. When the imaging device100is operating, the potential of the accumulation control line31is controlled so that the potential of the opposing electrode12cis higher, for example, than the potential of the pixel electrode12a. Accordingly, positive charge of the positive and negative charges generated by the photoelectric conversion can be selectively collected by the pixel electrode12a. The opposing electrode12cmay be formed as a single continuous layer over multiple pixels10A. Accordingly, a predetermined potential can be applied in a batch to the opposing electrode12cof the multiple pixels10A.

The pixel electrode12ais an electrode formed of a metal such as aluminum, copper, or the like, a metal nitride, or polysilicon that has been imparted conductivity by being doped by an impurity, or the like. The pixel electrode12ais electrically isolated from the pixel electrodes12aof other pixels10A by being spatially isolated from the pixel electrodes12aof adjacent other pixels10A.

The conductive structure89typically includes multiple lines and plugs formed of a metal such as copper, tungsten, or the like, or metal compounds such as metal nitrides or metal oxides, and polysilicon plugs. One end of the conductive structure89is connected to the pixel electrode12a. The pixel electrode12aof the photoelectric conversion structure12A and the circuits on the semiconductor substrate60are electrically connected to each other, by the other end of the conductive structure89being connected to circuit elements formed on the semiconductor substrate60, which will be described later.

Giving attention to the semiconductor substrate60now, the semiconductor substrate60includes a supporting substrate61, and one or more semiconductor layers formed on the supporting substrate61, as schematically illustrated inFIG. 3. A p-type silicon substrate is exemplified here as the supporting substrate61.

In the configuration exemplified illustrated inFIG. 3, the semiconductor substrate60has a p-type semiconductor layer61pon the supporting substrate61, an n-type semiconductor layer62non the p-type semiconductor layer61p, a p-type semiconductor layer63pon the n-type semiconductor layer62n, and a p-type semiconductor layer65pserving as a first semiconductor layer located on the p-type semiconductor layer63p. Typically, the p-type semiconductor layer63pis formed generally over the entire face of the supporting substrate61. The p-type semiconductor layer61p, the n-type semiconductor layer62n, and the p-type semiconductor layer63pand p-type semiconductor layer65p, are each typically formed by ion injection of an impurity to a semiconductor layer formed by epitaxial growth. The concentrations of impurity at the p-type semiconductor layer63pand p-type semiconductor layer65pare around the same as each other, and are higher than the concentration of impurity of the p-type semiconductor layer61p.

The n-type semiconductor layer62nserving as the second semiconductor layer is located between the p-type semiconductor layer61pand p-type semiconductor layer63p. An unshown well contact is connected to the n-type semiconductor layer62n, although omitted from illustration inFIG. 3. The well contact is provided on the outer side of the imaging region R1, and the potential of the n-type semiconductor layer62nis controlled via the well contact when the imaging device100is operating. Providing the n-type semiconductor layer62nsuppresses inflow of minority carriers to the charge accumulation region where signal charges are accumulated from the supporting substrate61or peripheral circuits.

Further, in this example, the semiconductor substrate60has a p-type region64provided between the p-type semiconductor layer63pand p-type supporting substrate61, penetrating the p-type semiconductor layer61pand n-type semiconductor layer62n. The p-type region64has a higher concentration of impurity as compared to the p-type semiconductor layer63pand p-type semiconductor layer65p, and has a function of electrically connecting the p-type semiconductor layer63pand supporting substrate61to each other.

The supporting substrate61has connection with a substrate contact omitted from illustration inFIG. 3, provided on the outer side of the imaging region R1. When the imaging device100is operating, the potential of the supporting substrate61and p-type semiconductor layer63pis controlled via the substrate contact. The potential of the p-type semiconductor layer65pcan also be controlled via the p-type semiconductor layer63pwhen the imaging device100is operating, due to the p-type semiconductor layer65pbeing located so as to be in contact with the p-type semiconductor layer63p

In the configuration exemplified inFIG. 3, the p-type semiconductor layer65phas a p-type impurity region66phaving a lower concentration of impurity, and an n-type impurity region67nis formed in the p-type impurity region66p. The n-type impurity region67nis formed near the surface of the semiconductor substrate60, with at least part thereof being located on the surface of the semiconductor substrate60, as schematically illustrated inFIG. 3. The n-type impurity region67nhere includes a first region67a, and a second region67bthat is located within the first region67aand has a relatively higher concentration of impurity than the first region67a.

An insulating layer is disposed on the principal face of the semiconductor substrate60, on the side toward the photoelectric conversion structure12A. In this example, the principal face of the semiconductor substrate60on the side toward the photoelectric conversion structure12A is covered by a first insulating layer71, a second insulating layer72, and a third insulating layer73. The first insulating layer71is a thermally oxidized film of silicon, for example. The second insulating layer72is a silicon dioxide layer for example, and the third insulating layer73is a silicon nitride layer, for example. The second insulating layer72may have a layered structure including multiple insulating layers, and in the same way, the third insulating layer73may have a layered structure including multiple insulating layers.

The layered structure of the first insulating layer71, second insulating layer72, and third insulating layer73has a contact hole h1on the second region67bof the n-type impurity region67n. A contact plug Cp1that is part of the conductive structure89is connected to the second region67bvia the contact hole h1in the example illustrated inFIG. 3, and accordingly, the n-type impurity region67nis electrically connected to the pixel electrode12aof the photoelectric conversion structure12A via the conductive structure89.

The junction capacitance formed by the p-n junction between the p-type impurity region66pserving as a p-well and the n-type impurity region67nfunctions as capacitance that accumulates at least part of the signal charges. Thus, the n-type impurity region67nfunctions as a charge accumulation region temporarily storing signal charges. The conductive structure89and n-type impurity region67ncan also be said to make up at least part of the above-described charge accumulation node FD.

The potential of the p-type semiconductor layer65pcan be controlled via the p-type semiconductor layer63pwhen the imaging device100is operating, by placing the p-type semiconductor layer65padjacent to the p-type semiconductor layer63p, as described above. Employing this sort of structure enables a region with a relatively low concentration of impurity to be disposed in the periphery of the portion where the contact plug Cp1, which has electrical contact with the photoelectric conversion structure12A, and the semiconductor substrate60come into contact. In this example, the p-type impurity region66pis disposed around the second region67bof the n-type impurity region67n. Disposing the first region67athat has a relatively low concentration of impurity around the second region67benables the intensity of the electrical field formed by the p-n junction between the n-type impurity region67nand the p-type semiconductor layer65por the p-type impurity region66pto be reduced. Reducing the intensity of the electrical field formed by the p-n junction yields an effect of suppressing leak current due to the electrical field formed by the p-n junction.

Note that forming the second region67bin the n-type impurity region67nis not indispensable. Note, however, that making the concentration of impurity of the second region67bthat is the contact portion with the contact plug Cp1and semiconductor substrate60relatively high yields the effect of suppressing spread of the depletion layer around the portion where the contact plug Cp1and semiconductor substrate60come into contact. This also enables suppression of crystal defects in the semiconductor substrate60at the interface of the contact plug Cp1and semiconductor substrate60, in other words, unintended inflow of charges to the n-type impurity region67nserving as the charge accumulation region and/or unintended outflow of charges from the n-type impurity region67n, occurring due to the interface state. Also, connecting the contact plug Cp1to the second region67bthat has a relatively high concentration of impurity yields the effect of reduced contact resistance.

The above-described signal detection circuit14A is formed on the semiconductor substrate60. The signal detection circuit14A in the pixel10A is electrically isolated from the signal detection circuits14A in other adjacent pixels10A due to a pixel isolation region69being disposed between mutually adjacent pixels10A. The pixel isolation region69is, for example, a p-type diffusion region.

In the signal detection circuit14A, the reset transistor26includes the n-type impurity region67nas one of the drain region and source region, and includes an n-type impurity region68anas the other of the drain region and source region. The reset transistor26further includes a gate electrode26eon the first insulating layer71, with the portion of the first insulating layer71located between the gate electrode26eand the semiconductor substrate60functioning as a gate insulating layer of the reset transistor26. The n-type impurity region68anis formed in the p-type semiconductor layer65p, and is connected to a feedback line53via a contact hole h2.

Also, n-type impurity regions68bn,68cn, and68dnare provided in the p-type semiconductor layer65p. The n-type impurity regions68an,68bn,68cn, and68dnhave a higher concentration of impurity than the first region67aof the n-type impurity region67n.

The signal detecting transistor22includes the n-type impurity region68bn, the n-type impurity region68cn, and a gate electrode22eon the first insulating layer71. The gate electrode22ein this example is connected to a portion of the conductive structure89where the pixel electrode12aand contact plug Cp1come into contact, in the layer where the address signal line34, reset signal line36, and so forth are located, as schematically illustrated by the dashed line inFIG. 3. In other words, the conductive structure89also has electrical connection with the gate electrode22e.

The n-type impurity region68bnserving as a drain region is connected to a contact plug Cp3via a contact hole h3. The above-described power source wiring32serving as the source follower power source is connected to the contact plug Cp3. Note that the power source wiring32is omitted from illustration inFIG. 3.

The n-type impurity region68bnis located in the p-type semiconductor layer65p, isolated from the n-type impurity region67nserving as the charge accumulation region, as schematically illustrated inFIG. 3. In this example, impurity regions69paand69pbare interposed between the n-type impurity region68bnand n-type impurity region67n, thereby electrically isolating the n-type impurity region68bnfrom the n-type impurity region67n. The impurity regions69paand69pbare part of the above-described pixel isolation region69, and typically are p-type diffusion regions. The concentration of impurity in the impurity regions69paand69pbis higher than the concentration of impurity of the p-type semiconductor layer65p, and is in a range around 5×1017cm−3or more to 1×1019cm−3or less, for example. When viewing a cross-sectional taken perpendicular to the principal face of the semiconductor substrate60, the impurity regions69paand69pbare disposed in the p-type impurity region65pisolated from each other, between the n-type impurity region67nand the n-type impurity region68bn, as illustrated inFIG. 3.

Further, a control electrode28eis disposed in a region between the impurity region69paand impurity region69pbon the first insulating layer71. The control electrode28eis covered by the layered structure of the second insulating layer72and third insulating layer73, as illustrated inFIG. 3. Note that in this example, the layered structure of the second insulating layer72and third insulating layer73covers the gate electrode26eof the reset transistor26and later-described gate electrodes22eand24e. The control electrode28eis connected to the above-described voltage line38via the contact plug Cp8that penetrates the contact hole h8provided to the second insulating layer72and third insulating layer73. That is to say, the control electrode28eis configured to be able to apply a predetermined voltage when the imaging device100is operating via the voltage line38. A voltage line38may be provided to every multiple column of pixels10A, in the same way as the vertical signal lines35or the like. Although the voltage line38is illustrated as being in the same layer as the address signal line34and reset signal line36inFIG. 3, the voltage line38has no electrical connection with any of the address signal line34, reset signal line36, and conductive structure89.

In the configuration exemplified inFIG. 4, the control electrode28ehas a rectangular shape extending in the direction parallel to the column direction of the multiple pixels10A. The general position of the impurity region69paand impurity region69pbillustrated inFIG. 3is indicated by a two-dot dashed line inFIG. 4. The control electrode28eoverlaps the end portion of the impurity region69paand the end portion of the impurity region69pb, as schematically illustrated inFIG. 4. The region of the impurity region69pathat is covered by the control electrode28eand the region of the impurity region69pbthat is covered by the control electrode28eare located on the surface of the semiconductor substrate60, which can be seen by comparing withFIG. 3. Note that in the example illustrated inFIG. 4, the signal detecting transistor22and address transistor24are laid out on a straight line in the vertical direction in the plane of the drawing. The drain regions and source regions thereof are electrically isolated from the drain region and source region of the reset transistor26, by the pixel isolation region69that has the impurity region69paand impurity region69pbas parts thereof.

Part of the first insulating layer71is located between the control electrode28eand the semiconductor substrate60, as schematically illustrated inFIG. 3. Looking at the control electrode28eand the periphery thereof, it can be said that the structure of the control electrode28eand the periphery thereof in the pixel10A has a structure resembling a MOS capacitor. In a typical embodiment of the present disclosure, when the imaging device100is operating, a voltage of a constant potential is applied to the control electrode28e. Applying voltage to the control electrode28ecorresponding to the conductivity type of a region located below the control electrode28eand/or corresponding to the conductivity type of the control electrode28ewhen the imaging device100is operating enables charges of inverse polarity to the charges moving from the n-type impurity region68bntoward the n-type impurity region67nto be concentrated in a region78located below the control electrode28e, which will be described later in detail. Accumulating charges of inverse polarity enables the charges moving from the n-type impurity region68bntoward the n-type impurity region67nto be eliminated by recombination at the region78located below the control electrode28e. That is to say, contamination of the n-type impurity region67nthat accumulates signal charges by excess charges can be suppressed, and deterioration of the image due to leak current can be suppressed.

From this perspective, the control electrode28e, the portion of the first insulating layer71located directly beneath the control electrode28e, and the impurity regions69paand69pbcan collectively be referred to as a leak current blocking structure. Hereinafter, the structure including the control electrode28e, the portion of the first insulating layer71located directly beneath the control electrode28e, and the impurity regions69paand69pbmay be referred to as “blocking structure28A” for the sake of simplicity and convenience. Details of the structure and operations of the blocking structure28A will be described later. Although both impurity regions69paand69pbare illustrated in the cross-section inFIG. 3as being located between the n-type impurity region67nand n-type impurity region68bn, this is only for the sake of convenience for description. By placing at least one of the impurity regions69paand69pbbetween the n-type impurity region67nand n-type impurity region68bn, effects of preventing contamination of the n-type impurity region67nserving as the charge accumulation region by excess charges can be anticipated.

The address transistor24is further formed on the semiconductor substrate60. The address transistor24includes the n-type impurity region68cn, an n-type impurity region68dnand a gate electrode24eon the first insulating layer71. The n-type impurity region68cnfunctions as a drain region of the address transistor24, and the n-type impurity region68dnfunctions as a source region of the address transistor24. The portion of the first insulating layer71that is located between the gate electrode24eand the semiconductor substrate60functions as a gate insulating film of the address transistor24. In this example, the n-type impurity region68cnis shared between the address transistor24and the signal detecting transistor22, so these transistors are electrically connected to each other. The vertical signal line35is connected to the n-type impurity region68dnvia a contact hole h4, as schematically illustrated inFIG. 3.

Blocking Structure

Now, an exemplary configuration of the blocking structure and the operations thereof will be described in detail.FIG. 5illustrates the blocking structure28A and the periphery thereof extracted from the illustration thereof inFIG. 3.

Of multiple wiring layers disposed within the inter-layer insulating layer90, the wiring layer located closest to the semiconductor substrate60may be a polysilicon layer doped with an impurity. For example, the above-described contact plugs Cp1, Cp3, and Cp8may be structures formed from a polysilicon film doped with an n-type impurity. In the same way, the above-described gate electrodes22eand24e, and the control electrode28emay be electrodes formed from a polysilicon film doped with an n-type impurity.

For example, in a case of forming the control electrode28efrom polysilicon electrode doped with an n-type impurity, an accumulation state can be formed near the surface of the semiconductor substrate60directly below the control electrode28e, by applying 0 V or a negative voltage to the control electrode28e. For example, the control circuit46drives the voltage supply circuit48so as to supply a voltage of 0 V or a negative voltage with a constant potential to the voltage line38, for the exposure period, i.e., for the entire charge accumulation period where charges generated by the photoelectric converter12are accumulated in the n-type impurity region67n. Note that it is sufficient to be able to supply a predetermined voltage to the voltage line38, and connecting a power source specialized for forming an accumulation state to the voltage line38is not indispensable. For example, the voltage supply circuit48may be omitted.

As described above, a relatively high voltage of around 3.3 V is applied to the n-type impurity region68bnfunctioning as a drain region of the signal detecting transistor22when the imaging device100is operating. According to studies made by the present inventors, when electrons are generated at a p-n junction formed between a drain region where high voltage is applied and the perimeter thereof, part of the electrons can flow into the charge accumulation region due to diffusion through the interface state of the element isolation region and the interface state of the surface of the silicon substrate. This sort of leak current that occurs due to inflow of excess charges can become a cause of deterioration in the obtained image.

In comparison with this, the blocking structure28A is disposed between the n-type impurity region68bnserving as the drain region of the signal detecting transistor22and the n-type impurity region67nserving as the charge accumulation region for storing signal charges here. Accordingly, even if electrons are generated that move by dispersion from the n-type impurity region68bntoward the n-type impurity region67n, such electrons can be eliminated at the region78, by recombination with holes concentrated at the portion of the semiconductor substrate60directly beneath the control electrode28e, as schematically illustrated inFIG. 5. That is to say, movement of minority carriers to the n-type impurity region67nis blocked by the blocking structure28A, and consequently, leak current due to contamination of the n-type impurity region67nby the minority carriers is suppressed.

Thus, the blocking structure28A is disposed between the n-type impurity region68bnand the n-type impurity region67n, and an appropriate voltage is applied to the control electrode28eover the entire charge accumulation period. Accordingly, even if charges generated at the p-n junction of the n-type impurity region68bnmove toward the n-type impurity region67n, such charges can be eliminated by recombination at or nearby the region78.

Note that in the example described here, the region of the semiconductor substrate60directly beneath the control electrode28eis part of the p-type semiconductor layer65p, and the above-described region78includes p-type impurities. Before forming the control electrode28e, a region having a relatively high concentration of impurity may be formed in the region of the p-type semiconductor layer65pthat will be located beneath the control electrode28e, by diffusion of impurities or the like. In other words, the region78may be a region that has a relatively high concentration of impurity as compared to the surroundings. Forming an impurity region having a relatively high concentration of impurity in the p-type semiconductor layer65pbelow the control electrode28eenables an accumulation state to be formed with a negative voltage having a less absolute value. In other words, voltage closer to 0 V can be used as voltage to be applied to the control electrode28e.

The control electrode28emay be a polysilicon electrode doped with a p-type impurity. In this case, employing control where a voltage of 1 V or lower to the control electrode28eover the entire charge accumulation period is applied enables an accumulation state to be formed in the region of the semiconductor substrate60located below the control electrode28eand concentrate positive charges. That is to say, charges generated at the p-n junction of the n-type impurity region68bnthat move toward the n-type impurity region67ncan be eliminated by recombination, in the same way as the example illustrated inFIG. 5.

The voltage applied to the control electrode28ecan be appropriately decided taking into consideration the conductivity type of the region located below the control electrode28eand/or the conductivity type of the control electrode28e. In a case where the supporting substrate61is an n-type silicon substrate, and the control electrode28eis a polysilicon electrode doped with an n-type impurity, it is sufficient to use a voltage of −1 V or higher as the voltage to be applied to the control electrode28e. Accordingly, effects of suppressing leak current, the same as the above-described form, can be anticipated. In a case where the supporting substrate61is an n-type silicon substrate, and the control electrode28eis a polysilicon electrode doped with a p-type impurity, it is sufficient to use a voltage of 0 V or above as voltage to be applied to the control electrode28e.

First Modification

FIGS. 6 and 7illustrate an imaging device according to a first modification of the first embodiment of the present disclosure.FIG. 6illustrates an example of the layout of elements in a pixel10B that the imaging device according to the first embodiment has, andFIG. 7illustrates an exemplary circuit configuration of the pixel10B illustrated inFIG. 6.

The pixel10B illustrated inFIGS. 6 and 7has a photodiode12B as the photoelectric converter12instead of the photoelectric conversion structure12A, as compared with the pixel10A described with reference toFIGS. 2 through 4. In this example, the accumulation control line31illustrated inFIG. 2is omitted. The point of one of the drain and source of the reset transistor26being connected to the charge accumulation node FD is the same as the configuration illustrated inFIG. 2. Note, however, that the power source wiring32is connected to the other of the drain and source of the reset transistor26here.

The pixel10B includes a signal detection circuit14B connected to the photodiode12B. The signal detection circuit14B further includes a transfer transistor29connected between the gate of the signal detecting transistor22and the photodiode12B, as compared with the signal detection circuit14A of the pixel10A. A transfer signal line39is connected to a gate electrode29eof the transfer transistor29. The transfer signal line39has connection with the vertical scanning circuit42for example, and the potential thereof is controlled by the vertical scanning circuit42. The vertical scanning circuit42can control the timing of transferring signal charges generated at the photodiode12B to the charge accumulation node FD, by on and off control of the transfer transistor29.

In this example, the charge accumulation node FD is a node where the gate electrode22eof the signal detecting transistor22connects to the photodiode12B. The charge accumulation node FD includes as part thereof the n-type impurity region67nformed on the semiconductor substrate60A, in the same way as the examples described above. In the configuration exemplified inFIG. 6, the p-type impurity region66pwith a relatively low concentration of impurity is located between the gate electrode26eand gate electrode29ein plan view. The n-type impurity region67nis located in the p-type impurity region66p.

The blocking structure28A that urges recombination of charges is disposed between the n-type impurity region67nand the n-type impurity region68bnin the example illustrated inFIG. 6as well. Accordingly, the unwanted minority carriers moving toward the n-type impurity region67ncan be suppressed from contaminating the n-type impurity region67n, in the same way as with the examples described with reference toFIGS. 1 through 5.

Second Modification

FIG. 8illustrates a second modification of the imaging device according to the first embodiment of the present disclosure.FIG. 8illustrates an example of layout of elements in a pixel10C that the imaging device according to the second modification has.

The primary point of difference between the pixel10C illustrated inFIG. 8and the pixel10A illustrated inFIG. 4is that the pixel10C has the reset signal line36connected to the control electrode28einstead of the voltage line38. That is to say, in this example, the control electrode28eis equipotential with the gate electrode26eof the reset transistor26.

In this example, the vertical scanning circuit42also has the functions of the above-described voltage supply circuit48. Connecting the reset signal line36to the control electrode28eenables the voltage line38and the voltage supply circuit48to be omitted, as exemplified inFIG. 8. Accordingly, effects of suppressing leak current can be obtained with a simpler circuit. Although a predetermined voltage is applied to the control electrode28efor the entire exposure period in the embodiment according to the present disclosure, applying voltage equal to or less than the threshold voltage of the reset transistor26as voltage to be applied to the control electrode28eenables an inverted state to be formed directly beneath the control electrode28ewhile leaving the reset transistor26off. For example, in a case where the control electrode28eis formed as a polysilicon electrode doped with an n-type impurity, it is sufficient to apply a voltage of 0 V or lower to the control electrode28e.

Third Modification

FIG. 9illustrates a third modification of the imaging device according to the first embodiment.FIG. 9illustrates an exemplary circuit configuration of a pixel10D that has been representatively selected from pixels10D according to the third modification of the imaging device. A signal detection circuit14D of the pixel10D illustrated inFIG. 9further includes, in addition to the signal detecting transistor22, address transistor24, and reset transistor26, a bandwidth control transistor56, a first capacitive element51, and a second capacitive element52, in comparison with the signal detection circuit14A illustrated inFIG. 2.

The bandwidth control transistor56is connected between the reset transistor26and feedback line53, and the gate thereof is connected to a feedback control line58. The feedback control line58is connected to the vertical scanning circuit42, for example, with the gate voltage of the bandwidth control transistor56being controlled by the vertical scanning circuit42when the imaging device is operating.

The first capacitive element51has a relatively small capacitance value, and is connected to the reset transistor26in parallel. The second capacitive element52has a larger capacitance value than the first capacitive element51, with one electrode being connected to a node RD between the reset transistor26and bandwidth control transistor56. The other electrode of the second capacitive element52is connected to a sensitivity adjustment line54. The sensitivity adjustment line54is connected to the vertical scanning circuit42, for example, and the potential thereof is set to 0 V, for example, when the imaging device100is operating.

A feedback path that includes the signal detecting transistor22and the bandwidth control transistor56in the path can be formed by turning the bandwidth control transistor56on. That is to say, the feedback path formed by the feedback circuit16D illustrated inFIG. 9includes the bandwidth control transistor56in addition to the inverting amplifier50. The second capacitive element52and bandwidth control transistor56may function as a resistor-capacitor (RC) filter circuit.

Formation of the feedback loop where part or all of the output signals of the signal detecting transistor22are fed back electrically enables the effects of kTC noise that occurs when the reset transistor26and bandwidth control transistor56turn off to be reduced. Details of such noise cancellation using feedback are described in Japanese Unexamined Patent Application Publication No. 2017-046333. The reset transistor26can also be made to function as a gain switching transistor in the circuit configuration exemplified inFIG. 9. Details of such mode switching are also described in Japanese Unexamined Patent Application Publication No. 2017-046333. Japanese Unexamined Patent Application Publication No. 2017-046333 is incorporated herein by reference in its entirety, for reference.

The circuit configuration such as illustrated inFIG. 9, where the bandwidth control transistor56is connected between the reset transistor26and the feedback line53, is advantageous from the perspective of noise reduction, since contamination by excess charges at the node RD from the drain region of the signal detecting transistor22, for example, can be suppressed, and leak current at the node RD can be suppressed. Applying a connection structure the same as that of the charge accumulation node FD to the node RD enables leak current to be suppressed at the node RD, which will be described below.

Device Configuration of Pixel10D

FIG. 10schematically illustrates an example of the device structure of the pixel10D illustrated inFIG. 9.FIG. 11illustrates an example of layout of the elements in the pixel10D. Taking a cross-section of the pixel10D along lines X-X inFIG. 11and unfolding yields the cross-section illustrated inFIG. 10. Although the voltage line38is illustrated as being in the same layer as the address signal line34and reset signal line36in this example as well, like in the example described with reference toFIG. 3, the voltage line38has no electrical connection with any of the address signal line34, reset signal line36, and conductive structure89.

In the configuration exemplified inFIG. 10, the pixel10D includes a semiconductor substrate76that supports the photoelectric conversion structure12A. The semiconductor substrate76includes a p-type semiconductor layer75pformed on the p-type semiconductor layer63ps. The p-type semiconductor layer75phas the p-type impurity region66pand a p-type impurity region76p. The concentration of impurity of the p-type impurity region76pmay be around the same as that of the p-type impurity region66p. An n-type impurity region77nis formed on the p-type impurity region76p. The n-type impurity region77nfunctions as the drain region or source region of the reset transistor26.

The n-type impurity region77nincludes a first region77a, and a second region77bplaced within the first region77a, in the same way as the n-type impurity region67n. The first region77ahas a concentration of impurity that is around the same or greater than the first region67aof the n-type impurity region67n. This is because the tolerance value of leak current can be set greater for the node RD as compared to the charge accumulation node FD. Parasitic resistance at the source side of the reset transistor26, for example, can be reduced by making the concentration of impurity of the first region77ato be higher than the concentration of impurity of the first region67a, and the current driving performance of the reset transistor26can be improved.

In this example, the first insulating layer71has a contact hole h5provided in a region on the n-type impurity region77n. A contact plug Cp5is connected to the n-type impurity region77nvia this contact hole h5. The contact plug Cp5is connected to the second region77bof the n-type impurity region77nin this example. Now, the second region77bhas a higher concentration of impurity than the first region77a. Although formation of the second region77bhaving a high concentration of impurity within the n-type impurity region77nis not indispensable, forming the second region77bwithin the n-type impurity region77nyields the effects of reduced contact resistance.

The contact plug Cp5is on the same layer as other contact plugs such as the contact plug Cp1, and typically is formed by patterning of a polysilicon film. The contact plug Cp5is connected to wiring88via a metal plug p5disposed within the inter-layer insulating layer90and so forth. The wiring88is wiring connected to, out of the electrodes that the second capacitive element52has, the electrode at the side not connected to the sensitivity adjustment line54. The first capacitive element51and second capacitive element52omitted from illustration inFIG. 10may be formed in the pixel10D in the form of a metal-insulator-semiconductor (MIS) structure, or may be formed in the form of a metal-insulator-meta (MIM) structure. Using the MIM structure enables a larger capacitance value to be obtained.

The upper face of the contact plug Cp5does not have a metal silicide layer. Accordingly, the metal plug p5is directly connected to the upper face of the contact plug Cp5in this example. Directly connecting the metal plug p5to the contact plug Cp5without going through a metal silicide layer enables dispersion of metal into the n-type impurity region77nvia the contact plug Cp5, particularly dispersion of nickel, to be prevented. In other words, contamination of the node RD by excess changes can be suppressed, and noise at the pixel10D can be further suppressed.

In the example exemplified inFIG. 10, the bandwidth control transistor56shares the n-type impurity region77nwith the reset transistor26. That is to say, the n-type impurity region77nalso functions as one of the source region and drain region of the bandwidth control transistor56. The n-type impurity region68anhere is formed in the p-type semiconductor layer75p, and functions as the other of the source region and drain region of the bandwidth control transistor56.

The bandwidth control transistor56further has a gate electrode56elocated on the first insulating layer71. The gate electrode56etypically is a polysilicon electrode, and is located in the same layer as the gate electrode22eof the signal detecting transistor22, the gate electrode24eof the address transistor24, and the gate electrode26eof the reset transistor26.

The pixel10D also has the blocking structure28A including the impurity regions69paand69pblocated between the n-type impurity region68bnand n-type impurity region67n, in the same way as the example illustrated inFIGS. 3 and 4. Applying a predetermined voltage of 0 V or lower, for example, to the control electrode28eforms an accumulation state near the surface of the region of the semiconductor substrate60directly beneath the control electrode28e, whereby excess charges dispersing form the n-type impurity region68bntoward the n-type impurity region67nfunctioning as part of the charge accumulation region can be blocked by the blocking structure28A. That is to say, occurrence of leak current can be suppressed.

In the configuration exemplified inFIG. 11, the reset transistor26and bandwidth control transistor56are arrayed on a straight line in the vertical direction of the plane of the drawing. Accordingly, the second region77bthat is the connecting portion of the contact plug Cp5and the semiconductor substrate76is located between the gate electrode26eof the reset transistor26and the gate electrode56eof the bandwidth control transistor56. It can be seen fromFIG. 11that the control electrode28eand the impurity regions69paand69pbmay exist in the pixel10D in a form of extending to the side of the n-type impurity region77nin the vertical direction of the drawing. That is to say, in this example, the blocking structure28A includes a portion located between the n-type impurity region77nand the n-type impurity region68bnthat functions as the drain region of the signal detecting transistor22. According to this configuration, minority carriers generated at the n-type impurity region68bnand moving toward the n-type impurity region77ncan also be blocked by the blocking structure28A. That is to say, occurrence of leak current at the node RD can be suppressed.

Fourth Modification

FIG. 12illustrates a fourth modification of the imaging device according to the first embodiment of the present disclosure. A pixel10X illustrated inFIG. 12has a photoelectric conversion structure12Aa and a photoelectric conversion structure12Ab.

As illustrated inFIG. 12, a signal detection circuit14Xa is connected to the photoelectric conversion structure12Aa, and a signal detection circuit14Xb is connected to the photoelectric conversion structure12Ab. The photoelectric conversion structure12Aa and photoelectric conversion structure12Ab have the opposing electrode and photoelectric conversion layer12bin common, for example, but on the other hand, have pixel electrodes that are electrically independent of each other. The pixel electrode of the photoelectric conversion structure12Aa is electrically connected to a charge accumulation node FDa, and the signal detection circuit14Xa reads out to a vertical signal line35asignals corresponding to signal charges generated by the photoelectric conversion structure12Aa and stored in the charge accumulation node FDa. On the other hand, the pixel electrode of the photoelectric conversion structure12Ab is electrically connected to a charge accumulation node FDb, and the signal detection circuit14Xb reads out to a vertical signal line35bsignals corresponding to signal charges generated by the photoelectric conversion structure12Ab and stored in the charge accumulation node FDb. That is to say, the pixel10X is configured to be capable of independently reading out two types of signals, in accordance with which of the signal detection circuit14Xa and signal detection circuit14Xb is used to execute readout of signals.

In the example illustrated inFIG. 12, the signal detection circuit14Xa has a circuit configuration similar to that of the signal detection circuit14D of the pixel10D illustrated inFIG. 9, and includes the signal detecting transistor22, address transistor24, reset transistor26, bandwidth control transistor56, first capacitive element51, and second capacitive element52. In this example, the signal detection circuit14Xa further includes a third capacitive element51aof which one electrode is connected to the charge accumulation node FDa. The third capacitive element51amay have a capacitance value around the same as that of the first capacitive element51.

The signal detection circuit14Xa also has a feedback circuit16Xa for feedback of part or all of the output signals of the signal detecting transistor22. Note, however, that a feedback line53aconnected to one of the source and drain of the bandwidth control transistor56is connected to the source of the signal detecting transistor22. That is to say, in the feedback circuit16Xa, the output of the signal detecting transistor22itself is used as the reference voltage for resetting.

This circuit configuration also enables a feedback loop to be formed where part or all of the output signals of the signal detecting transistor22are fed back electrically, and the effects of kTC noise that occurs when the reset transistor26and bandwidth control transistor56turn off can be reduced. Moreover, the inverting amplifier50has been omitted in comparison with the example inFIG. 9, so noise cancellation using feedback can be implemented in increments of pixels10X. Details of noise cancellation using feedback in increments of pixels are described in Japanese Unexamined Patent Application Publication No. 2016-127593, for example. Japanese Unexamined Patent Application Publication No. 2016-127593 is incorporated herein by reference in its entirety, for reference.

The signal detection circuit14Xa further has a protection transistor55in this example. The drain or source of the protection transistor55, and the gate, are connected to the charge accumulation node FDa between the gate of the signal detecting transistor22and the photoelectric conversion structure12Aa. The one of the drain and source of the protection transistor55that is not connected to the photoelectric conversion structure12Aa is connected to a power line57that receives supply of a predetermined power source when the imaging device100is operating, by being connected to a power source that is omitted from illustration.

On the other hand, looking at the signal detection circuit14Xb having electrical connection with the photoelectric conversion structure12Ab, the signal detection circuit14Xb includes a second signal detecting transistor22bhaving a gate connected to the photoelectric conversion structure12Ab, an address transistor24bconnected between the signal detecting transistor22band the vertical signal line35b, a reset transistor26bconnected between the photoelectric conversion structure12Ab and a feedback line53b, and a second protection transistor55b. The gate of the reset transistor26bis connected to the reset signal line36b, and the vertical scanning circuit42, for example, controls on and off of the reset transistor26bby control of the potential at the reset signal line36b. The drain or source of the protection transistor55band the gate thereof are connected to a charge accumulation node FDb between the gate of the signal detecting transistor22band photoelectric conversion structure12Ab, and the one of the drain and source of the protection transistor55bthat is not connected to the photoelectric conversion structure12Ab is connected to the power line57, in the same way as the above-described protection transistor55.

An address signal line34bis connected to the gate of the address transistor24bof the signal detection circuit14Xb. The address signal line34bis connected to the vertical scanning circuit42for example, and the vertical scanning circuit42controls on and off of the address transistor24bby control of the potential at the address signal line34b. That is to say, according to the circuit exemplified inFIG. 12, one of the signal detection circuits14Xa and14Xb can be selected and signals corresponding to the amount of charge accumulated in the charge accumulation node FDa or signals corresponding to the amount of charge accumulated in the charge accumulation node FDb can be selectively read out.

The signal detection circuit14Xb includes a feedback circuit16Xb. Accordingly, due to formation of a feedback loop where part or all of the output signals of the signal detecting transistor22bare fed back electrically, the effects of kTC noise that occurs when the reset transistor26bgoes off can be reduced, in the same way as with the signal detection circuit14Xa.

The signal detection circuit14Xb has, as a part thereof, a capacitive element52bhaving a relatively large capacitance value by being provided within the pixel10X in a MIM structure, for example. As illustrated inFIG. 13, one electrode of the capacitive element52bis connected to the charge accumulation node FDb, and the other electrode is connected to the sensitivity adjustment line54. The capacitive element52bconnected to the charge accumulation node FDb has functions of increasing the capacitance value of the overall charge accumulation region that accumulates signal charges.

According to the circuit exemplified inFIG. 12, signals in accordance with the amount of charge accumulated in the charge accumulation node FDa and signals in accordance with the amount of charge accumulated in the charge accumulation node FDb can be selectively read out, as described above. The capacitive element52bthat has a relatively large capacitance value is connected to the charge accumulation node FDb in the signal detection circuit14Xb, and accordingly, more signal charges can be stored, which is advantageous in shooting in a high-luminance environment, for example. On the other hand, the signal detection circuit14Xa includes, as a part thereof, the first capacitive element51connected in parallel to the reset transistor26, and can execute noise cancellation more effectively while suppressing increase in the capacitance value of the overall charge accumulation region. Accordingly, this is particularly advantageous in shooting with high sensitivity. Thus, an arrangement may be made where two signal detection circuits are provided within one pixel, and readout of signals may be executed via the signal detection circuit of these that is more suitable for the shooting scene. The term “pixel” in the present specification indicates, for example, a unit configuring a repetitive structure in the imaging region R1, and is not restricted to a structure including a single signal detection circuit but rather may include two or more signal detection circuits.

FIG. 13illustrates an example of the layout of the elements in the pixel10X illustrated inFIG. 12, andFIG. 14illustrates an example of a two-dimensional array of the pixel10X illustrated inFIG. 12. Of the four pixels illustrated inFIG. 14, a pixel10Xa located to the lower right has a structure of a mirror image of the pixel10X on a virtual axis passing through the center of the pixel10X and extending parallel to the column direction of the multiple pixels. Of the four pixels illustrated inFIG. 14, a pixel10Xb located to the upper right and a pixel10Xc located to the upper left have a structure of a mirror image of the pixel10X and pixel10Xa on a virtual axis passing through the center of the pixel10X and extending parallel to the row direction of the multiple pixels. In the fourth modification, the imaging region R1can be formed from a repetition where a group of these four pixels10X and10Xa through10Xc are an increment.

In the example illustrated inFIG. 13, the blocking structure28A is disposed at the general middle of the pixel10X, and the signal detection circuits14Xa and14Xb are disposed in the pixel10X surrounding the blocking structure28A. The impurity region69paand impurity region69pbof the blocking structure28A is located between the n-type impurity region68bnand the n-type impurity region67nserving as the signal detection circuit14Xa side charge accumulation region in this example. Accordingly, inflow of excess charges from the n-type impurity region68bnto the n-type impurity region67nof the signal detection circuit14Xa side can be suppressed by the blocking structure28A. Placing the blocking structure28A so as to be interposed between the n-type impurity region67nof the signal detection circuit14Xa at the high-sensitivity side where demand for noise suppression is relatively strict, and the n-type impurity region68bn, enables deterioration in image quality due to leak current to be effectively suppressed. While the feedback lines53aand53bare illustrated in the form of lines inFIG. 12, the structure to electrically connect the source of the signal detecting transistor22to the bandwidth control transistor56and the structure to electrically connect the source of the signal detecting transistor22bto the reset transistor26bare not restricted to the form of lines.

Second Embodiment

FIG. 15schematically illustrates an exemplary device structure of the pixel10E that an imaging device according to a second embodiment of the present disclosure has.FIG. 16illustrates an example of layout of the elements in the pixel10E illustrated inFIG. 15. Taking a cross-section of the pixel10D along lines XV-XV inFIG. 16and unfolding yields the cross-section illustrated inFIG. 15. As in the example illustrated inFIGS. 3 and 10, the voltage line38has no electrical connection with any of the address signal line34, reset signal line36, and conductive structure89. The pixel10E has a blocking structure28B instead of the blocking structure28A, in comparison with the first embodiment.

The blocking structure28B includes a control electrode81e, a portion of the first insulating layer71and second insulating layer72that is located directly beneath the control electrode81e, and an impurity region69pc. The impurity region69pcis part of the pixel isolation region69in the same way as the above-described impurity regions69paand69pb, and typically is a p-type diffusion region. The concentration of impurity in the impurity region69pcmay be the same as the concentration of impurity in the impurity regions69paand69pb. The impurity region69pcis located between the n-type impurity region68bnand n-type impurity region67nin cross-sectional view, and electrically isolates the n-type impurity region68bnand n-type impurity region67nfrom each other.

In the configuration exemplified inFIG. 15, the inter-layer insulating layer90has a multi-layer structure including insulating layers91through94, with multi-layer wiring80being disposed within the inter-layer insulating layer90. The multi-layer wiring80includes a first wiring layer81located within the insulating layer91, a second wiring layer82located within the insulating layer92, a third wiring layer83located within the insulating layer93, and a wiring layer84located within the insulating layer94. The first wiring layer81out of these wiring layers81through84is located closest to the semiconductor substrate60.

The first wiring layer81is typically a polysilicon layer formed across multiple pixels10E in the imaging region R1, and has conductivity due to being doped with an impurity. The first wiring layer81includes the above-described contact plugs Cp1and Cp3as part thereof, and the control electrode81eis part of the first wiring layer81in this example. Also in this example, the control electrode81eis located on the second insulating layer72, and is connected to the voltage line38, so as to be capable of applying a predetermined voltage. Note that in the configuration exemplified inFIG. 15, in the layered structure of the first insulating layer71, second insulating layer72, and third insulating layer73, the control electrode81eis disposed on a portion where the third insulating layer73has been partially removed, but the third insulating layer73may be interposed between the control electrode81eand the semiconductor substrate60. That is to say, the control electrode81emay be located upon the layered structure of the first insulating layer71, second insulating layer72, and third insulating layer73. The first wiring layer81may be a metal wiring layer.

When viewing from a direction perpendicular to the semiconductor substrate60, the control electrode81eis located between the n-type impurity region67nand the n-type impurity region68bn, and covers at least part of the impurity region69pc, as schematically illustrated inFIG. 16. The control electrode81eis also located between the gate electrode22eand the gate electrode26ehere.

The region of the impurity region69pcthat is covered by the control electrode81eis located on the surface of the semiconductor substrate60, as schematically illustrated inFIG. 15. As illustrated in the example inFIGS. 15 and 16, in a structure that uses part of a wiring layer in a layer that is above the gate electrode of the transistor as a control electrode for a blocking structure, there is no need to have the impurity regions69pcand69pbdisposed separated from each other between the n-type impurity region67nand n-type impurity region68bnas in the above-described blocking structure28A. A region with a relatively high concentration of impurity can be disposed in the semiconductor substrate60in the form of a single continuous impurity region between the n-type impurity region67nand n-type impurity region68bn.

In a case where the control electrode81eis a polysilicon electrode doped with an n-type impurity for example, an accumulation state can be formed at the impurity region69pcin the same way as with the blocking structure28A in the first embodiment, by applying a voltage of 0 V or lower to the control electrode81efrom the voltage supply circuit48, for example, via the voltage line38. That is to say, minority carriers moving toward the n-type impurity region67ncan be eliminated by recombination at the region78located below the control electrode81e. Applying a voltage of 0 V or lower to the control electrode81eover the entire charge accumulation period enables contamination of the n-type impurity region67nby excess minority carriers to be suppressed, and effects of suppressed leak current can be obtained.

Thus, an arrangement may be made where part of a wiring layer in a layer that is above the gate electrode of the transistor, located above the semiconductor substrate60, is used as a control electrode for a blocking structure, instead of forming a control electrode in the same layer as the gate of the transistor included in the signal detecting circuit. In this case, a voltage can be applied that has a larger absolute value as compared to providing the control electrode in the same layer as the gate electrode of the transistor formed on the semiconductor substrate60. The control electrode81emay be a polysilicon electrode doped with a p-type impurity. In this case, a voltage equal to or greater than the substrate potential applied to the supporting substrate61via the substrate contact can be applied to the control electrode81eover the entire charge accumulation period.

Of course, in a configuration using part of a wiring layer in a layer that is above the gate electrode of the transistor as a control electrode for a blocking structure, the impurity regions69paand69pbmay be disposed separated from each other between the n-type impurity region67nand n-type impurity region68bn.FIG. 17schematically illustrates the device structure of a pixel1OF that has a blocking structure28C including impurity regions69paand69pbformed separated between the n-type impurity region67nand n-type impurity region68bn. In this example as well, the voltage line38has no electrical connection with any of the address signal line34, reset signal line36, and conductive structure89.

Part of a wiring layer located in a layer that is further above can be used as a control electrode for a blocking structure, which will be described below. Providing the control electrode of the blocking structure in a layer higher than the gate electrode of the transistor formed on the semiconductor substrate60avoids physical interference with the gate electrode, so the degree of freedom relating design of the shape of the control electrode improves. Accordingly, the control electrode can be enlarged to a position near the n-type impurity region67nin a plan view, for example. In this sort of configuration, layout of wiring where part of the control electrode overlaps the n-type impurity region67nin the plan view may be tolerated.

FIG. 18Aschematically illustrates another example of a device structure relating to a pixel that the imaging device according to the second embodiment of the present disclosure has. Although omitted from illustration inFIG. 18A, the control electrode81eis connected to the voltage line38in the same way as in the example described with reference toFIG. 15and is configured so that a predetermined voltage can be applied. Also, when viewing from a direction perpendicular to the semiconductor substrate60, the control electrode81eis located between the n-type impurity region67nand the n-type impurity region68bn, in the same way as in the example described with reference toFIG. 16.

The second wiring layer82of a pixel10Ga illustrated inFIG. 18Ahas a wiring portion83wlocated above the blocking structure28B, in addition to the address signal line34and reset signal line36. In this example exemplified here, the wiring portion83wis a portion electrically connecting a via extending upwards from the contact plug Cp1and a via extending upwards from a contact plug connected to the gate electrode22eof the signal detecting transistor22, in the conductive structure89or second wiring layer82. The wiring portion83wmay be part of wiring covering the n-type impurity region67n. The address signal line34, reset signal line36, and wiring portion83wtypically may be formed of a metal such as copper, tungsten, or the like, or a metal compound such as a metal nitride or a metal oxide, in the same way as the above-described conductive structure89. The third wiring layer83located at a position in a layer further above the second wiring layer82is located within the insulating layer92, and includes the above-described vertical signal line35, feedback line53, and so forth, as a part thereof.

FIG. 18Billustrates an example of layout of the elements in the pixel10Ga illustrated inFIG. 18A. Taking a cross-section of the pixel10Ga along lines XVIIIA-XVIIIA inFIG. 18Band unfolding yields the cross-section illustrated inFIG. 18A.

The second wiring layer82is located in an upper layer from the gate electrode of the signal detecting transistor22and so forth formed on the semiconductor substrate60, as described with reference toFIG. 18A. Accordingly, layout-related restrictions regarding structures of wiring included in the second wiring layer82and so forth are relatively few, and for example, wiring crossing the n-type impurity region67ncan be disposed within the inter-layer insulating layer90. The above-described wiring portion83wmay have a shape covering the n-type impurity region68bnand the n-type impurity region67nserving as the charge accumulation region.

A voltage that is different from the voltage applied to the control electrode81eof the blocking structure may be applied to the wiring portion83w. For example, in a case where the supporting substrate61is an n-type silicon substrate, and the control electrode81eis formed in the form of a polysilicon electrode doped with an n-type impurity, a voltage of the substrate potential or lower is applied to the control electrode81e, whereas a voltage of the substrate potential or higher can be applied to the wiring portion83w. Loss of the functions of the blocking structure28B can be avoided even if such voltage is applied to the wiring portion83w, due to the blocking effects of the control electrode81e. In the same way, in a case where the control electrode81eis a polysilicon electrode doped with a p-type impurity, a voltage that is not more than the substrate potential plus 1 V is applied to the control electrode81e, whereas voltage that is not less than the substrate potential plus 1 V can be applied to the wiring portion83w.

On the other hand, in a case where the supporting substrate61is a p-type silicon substrate, in other words, in a case where a p-type conductivity type has been employed for the n-type impurity region67n, n-type impurity region68bn, and so forth, instead of an n-type conductivity type, and in a case where the control electrode81eis formed as a polysilicon electrode doped with an n-type impurity, a voltage that is not less than the substrate potential minus 1 V is applied to the control electrode81e. At this time, a voltage of the substrate potential or lower may be applied to the wiring portion83w. In a case where the supporting substrate61is a p-type silicon substrate, and the control electrode81eis formed as a polysilicon electrode doped with a p-type impurity, a voltage of the substrate potential or higher is applied to the control electrode81e. At this time, a voltage of the substrate potential or lower may be applied to the wiring portion83w.

FIG. 19schematically illustrates yet another example of a device structure relating to a pixel that the imaging device according to the second embodiment of the present disclosure has. In the pixel10Ga illustrated inFIG. 18A, the third insulating layer73in the layered structure of the first insulating layer71, second insulating layer72, and third insulating layer73are partially removed, and the control electrode81eis disposed at the portion where the third insulating layer73has been removed. Conversely, partial removal of the third insulating layer73is not performed in a pixel10Gb illustrated inFIG. 19, and the third insulating layer73covers the impurity region69pc.

In the configuration exemplified inFIG. 19, the second wiring layer82includes a wiring portion83xas a part thereof. Although omitted from illustration inFIG. 19, the wiring portion83xis configured such that a predetermined voltage can be applied when operating, by being connected to the voltage line38. The wiring portion83xmay be part of the voltage line38. The wiring portion83xtypically is located between the n-type impurity region67nand n-type impurity region68bnin plan view.

In this example, the n-type impurity region67nand the gate electrode22eof the signal detecting transistor22are electrically connected to each other by a wiring portion83ythat is part of the third wiring layer83located at an upper layer than the second wiring layer82. The wiring portion83ymay have a shape covering the n-type impurity region68bnand the n-type impurity region67n. The wiring portion83xand wiring portion83yin the pixel10Gb typically may be formed of a metal such as copper, tungsten, or the like, or a metal compound such as a metal nitride or a metal oxide, in the same way as the above-described wiring portion83w.

In comparison with the example described with reference toFIG. 18A, the wiring portion83xthat has electrical connection with the voltage line38can be made to function in the same way as the control electrode81ein the above-described pixel10Ga, in the example illustrated inFIG. 19. That is to say, a blocking structure28F is configured of the wiring portion83x, a portion of the first insulating layer71, second insulating layer72, and third insulating layer73located directly beneath the wiring portion83x, and the impurity region69pc.

In a case where the conductivity type of the impurity region near the surface of the semiconductor substrate60, including the n-type impurity region67nas the charge accumulation region and so forth, is n-type, as exemplified inFIG. 19, a voltage of the substrate potential or lower is applied to the wiring portion83xwhen operating. At this time, voltage that is different from the voltage applied to the wiring portion83xserving as the control electrode of the blocking structure may be applied to the wiring portion83ylocated in an upper layer. For example, a voltage of the substrate potential or higher may be applied to the wiring portion83y. On the other hand, in a case where the conductivity type of the impurity region near the surface of the semiconductor substrate60is p-type, a voltage of the substrate potential or higher is applied to the wiring portion83xwhen operating. At this time, a voltage that is the substrate potential or lower may be applied to the wiring portion83ylocated in an upper layer.

Example of Layout of Elements Among Multiple Pixels

The pixels10of the imaging device100may be two-dimensionally laid out, for example, on the semiconductor substrate60, as described with reference toFIG. 1. A typical example of the layout of the elements in the pixels10two-dimensionally laid out will be described below.

FIG. 20illustrates an example of a two-dimensional array of pixels10A illustrated inFIG. 4. The imaging region R1has a two-dimensional array of sets of pixels10Aa and pixels10Ab in the example illustrated inFIG. 20. Pixels10Aa here are the same as the pixel10A illustrated inFIG. 4. On the other hand, pixels10Ab have a structure of a mirror image of the pixels10Aa on a virtual axis Ax passing through the center of the pixels10Aa and extending parallel to the column direction of the multiple pixels.

In the example illustrated inFIG. 20, an array is employed where, in the column direction of the multiple pixels, i.e., in the vertical direction of the plane of the drawing, pixels10Aa are adjacent to pixels10Aa and pixels10Ab are adjacent to pixels10Ab. On the other hand, in the row direction of the multiple pixels, i.e., in the horizontal direction of the plane of the drawing, pixels10Aa and pixels10Ab are disposed alternately repeating.

By employing this array of pixels, a blocking structure28A is always interposed between the n-type impurity region68bnand the n-type impurity region67nclosest to that n-type impurity region68bnin the row direction. Accordingly, inflow of excess minority carriers from the n-type impurity region68bnof a certain pixel10Aa to the n-type impurity region67nin a pixel10Ab adjacent to the pixel10Aa in the row direction can be effectively suppressed. In the same way, inflow of excess minority carriers from the n-type impurity region68bnof a certain pixel10Ab to the n-type impurity region67nin a pixel10Aa adjacent to the pixel10Ab in the row direction can be avoided. An array may be employed where pixels10Aa and pixels10Ab are disposed alternately repeating in the column direction instead of in the row direction, or in addition to in the row direction.

The same element layout and pixel array may be employed for the pixel10B illustrated inFIG. 6and the pixel10C illustrated inFIG. 8.FIG. 21illustrates an example of a two-dimensional array of the pixel10C illustrated inFIG. 8. In this example as well, the imaging region R1has an array of sets of pixels10Ca and pixels10Cb that have a structure of a mirror image of the pixels10Ca on a symmetric axis extending in the vertical direction of the plane of the drawing. Pixels10Ca and pixels10Cb are disposed alternately repeating in the row direction of the multiple pixels, as illustrated inFIG. 21. Of course, an array may be employed where pixels10Ca and pixels10Cb are disposed alternately repeating in the column direction in addition to in the row direction.

FIG. 22illustrates an example of the two-dimensional array of pixels10D illustrated inFIG. 11. In this illustrated example, pixels10Da, and pixels10Db that have a structure of a mirror image of the pixels10Da on a symmetric axis extending in the vertical direction of the plane of the drawing, are disposed alternately repeating in the row direction of the multiple pixels. Of course, an array may be employed where pixels10Da and pixels10Db are disposed alternately repeating in the column direction, in addition to the row direction. According to this array, inflow of excess charges to charge accumulation regions of adjacent pixels can be suppressed, in the same way as the examples inFIGS. 20 and 21.

FIG. 23illustrates an example of the two-dimensional array of pixels10E illustrated inFIG. 16. In this example as well, in the same way as with the examples described with reference toFIGS. 20 through 22, pixels10Ea, and pixels10Eb that have a structure of a mirror image of the pixels10Ea on a symmetric axis extending in the vertical direction of the plane of the drawing, are disposed alternately repeating in the row direction of the multiple pixels.

In each of the pixel10Ea and pixels10Eb, the control electrode81eof the blocking structure28B is located between the gate electrode22eof the signal detecting transistor22and the gate electrode26eof the reset transistor26. By employing the array in the example described with reference toFIGS. 20 through 22to the pixels10E that have the blocking structure28B, suppression of contamination by excess charges in charge accumulation regions of adjacent pixels can be anticipated. An array may be employed where pixels10Ea and pixels10Eb are disposed alternately repeating in the column direction in addition to in the row direction.

Other Modifications

FIG. 24illustrates another example of a pixel having a blocking structure. Pixel10H illustrated inFIG. 24has a structure similar to that of the pixel10A illustrated inFIG. 4, and includes a blocking structure28D instead of the blocking structure28A. Note that taking a cross-section of the pixel10H along lines III-Ill inFIG. 24and unfolding may yield the same as the cross-section illustrated inFIG. 3. Accordingly, illustration of a cross-section here is omitted.

In the configuration exemplified inFIG. 24, a control electrode28fof the blocking structure28D has a shape extending from one edge portion of the pixel10H to the other edge portion following the vertical signal line35in plan view, as compared with the control electrode28eillustrated inFIG. 4. The impurity regions69paand69pbalso have shapes extending from one edge portion of the pixel10H to the other edge portion. Portions corresponding to the impurity regions69paand69pbin the pixel isolation region69are schematically indicated by hatching inFIG. 24. The positions of the impurity regions69paand69pbmay be represented by hatching in the following plan views as well.

Providing this blocking structure28D in the pixel enables contamination by excess charges from the n-type impurity region68bnto be blocked. Further, charges generated at the p-n junction of the n-type impurity region68cnand the periphery thereof and moving toward the n-type impurity region67n, and/or charges generated at the n-type impurity region68dnand the periphery thereof and moving toward the n-type impurity region67n, can be blocked by the blocking structure28D. Accordingly, inflow of excess charges to the n-type impurity region67nfunctioning as part of the charge accumulation region can be suppressed, and leak current due to inflow of such excess charges can be suppressed more effectively. Note that the impurity regions69paand69pbextending from one edge portion of the pixel10H to the other end portion is not indispensable. For example, these may be placed at least between the n-type impurity region67nand n-type impurity region68bn, between the n-type impurity region67nand n-type impurity region68cn, and between the n-type impurity region67nand n-type impurity region68dn.

FIG. 25illustrates an example of the two-dimensional array of pixels10H described with reference toFIG. 24. In the example illustrated inFIG. 25, in the same way as with the examples described with reference toFIGS. 20 through 23, pixels10Ha, and pixels10Hb that have a structure of a mirror image of the pixels10Ha on a symmetric axis extending in the vertical direction of the plane of the drawing, are arrayed alternately repeating in the row direction of the multiple pixels. It is needless to say that an array may be employed where pixels10Ha and pixels10Hb are disposed alternately repeating in the column direction in addition to in the row direction.

In the configuration described inFIG. 25, the control electrode28fof the blocking structure28D continuously extends through multiple pixels10Ha or multiple pixels10Hb in the column direction of the multiple pixels. Accordingly, movement of excess charges in the row direction of the multiple pixels can be more effectively suppressed. In this example, the contact plug Cp8that electrically connects the control electrode28fto the voltage line38is provided to each of the pixels10Ha and each of the pixels10Hb. However, the control electrode28fis formed continuously over multiple pixels in this example, so there is no need to connect the control electrode28fto the voltage line38in all pixels included in the imaging region R1. For example, an arrangement may be made where the contact plug Cp8is selectively disposed in pixels located at the edge portion in the column direction out of the multiple pixels disposed in the imaging region R1, and the control electrode28fis connected to the voltage line38therein. Alternatively, an arrangement may be made where dummy pixels having the blocking structure28D are disposed in the peripheral region R2, and the contact plug Cp8is disposed at the control electrode28fin the dummy pixels, thereby electrically connecting the voltage line38to the control electrode28fin each of the pixels.

FIG. 26illustrates yet another example of a pixel having a blocking structure. Pixel101illustrated inFIG. 26has two control electrodes28hextending in the column direction at the edge portions of the pixel101, with the control electrode28finterposed between, as compared with the pixel10H described with reference toFIG. 24. The control electrodes28heach are provided along the boundary of two pixels101adjacent in the row direction, as schematically illustrated inFIG. 26.

Note that taking a cross-section of the pixel101along lines III-III inFIG. 26and unfolding may yield the same as the cross-section illustrated inFIG. 3. It can be understood from comparison withFIG. 3, that the first insulating layer71and second insulating layer72exist directly beneath the control electrodes28h, and further, the pixel isolation region69may be disposed in a region of the semiconductor substrate60covered by the control electrodes28h. The pixel isolation region69here is a p-type diffusion region, and accordingly, the pixel10I has a blocking structure28E that has a configuration generally the same as that as the blocking structure28D at and near the control electrodes28h.

As illustrated inFIG. 26, the control electrodes28hare electrically connected to the voltage line38by wiring33, and are configured such that a predetermined voltage can be applied via the voltage line38when the imaging device100is operating, in the same way as with the control electrode28f. Accordingly, blocking structures28E located at the edge portions of the pixel10I can be made to function in the same way as the blocking structure28D located at the general middle of the pixel10I.

FIG. 27illustrates an example of a two-dimensional array of the pixels10I described with reference toFIG. 26. Unlike the examples described with reference toFIGS. 20 through 25, the layout of the pixel elements are all the same in the example illustrated inFIG. 27, instead of combining with pixels that have a structure of a mirror image of the pixels10I on a symmetric axis in the column direction. It can be seen fromFIG. 27that the control electrode28fand control electrodes28heach continuously extend over multiple pixels10I in the column direction of the multiple pixels10I.

As described above, providing the blocking structure28D in the pixel10I enables inflow of excess charges from the n-type impurity regions68bn,68cn, and68dnto the n-type impurity region67nto be suppressed within each pixel10I. Further, providing the blocking structures28E at the edge portions of the pixel10I in the column direction, for example, of the multiple pixels10I enables contamination by excess charges between pixels10I adjacent to each other in the row direction to be suppressed, while not needing combining with pixels of different element layout, as illustrated inFIG. 27. There is no need to combine with pixels of different element layout, so effects of misalignment due to different processes can be avoided, and the difference in pixel properties per column can be reduced.

FIG. 28illustrates a modification of the pixel10Ga described with reference toFIGS. 18A and 18B. Taking a cross-section of pixel10J along lines XVIIIA-XVIIIA inFIG. 28and unfolding may yield the same as the cross-section illustrated inFIG. 18A. Accordingly, illustration of a cross-section is omitted here.

The pixel10J illustrated inFIG. 28has the blocking structure28B in the same way as the above-described pixel10Ga. Note, however, the control electrode81eof the blocking structure28B has a shape extending from one edge portion of the pixel10J to the other edge portion along the vertical signal line35in plan view. In accordance with the control electrode81eextending from one edge portion of the pixel10J to the other edge portion in plan view, the impurity region69pcalso extends from one edge portion of the pixel10J to the other edge portion in this example, as schematically illustrated inFIG. 28.

The control electrode81ecan be extended over the entirety of the pixel10J in the column direction for example, in the second embodiment as well, as illustrated inFIG. 28, instead of forming the control electrode81eat selective regions between the gate electrode22eand the gate electrode26e, in the same way as with the examples illustrated inFIGS. 24 through 27. According to this configuration, inflow of excess charges from the n-type impurity regions68bn,68cn, and68dnto the n-type impurity region67ncan be suppressed, in the same way as in the example illustrated inFIG. 24and so forth.

FIG. 29illustrates an example of the two-dimensional array of pixels10J described with reference toFIG. 28. In the example illustrated inFIG. 28, in the same way as in the examples described with reference toFIGS. 20 through 25, pixels10Ja, and pixels10Jb that have a structure of a mirror image of the pixels10Ja on a symmetric axis extending in the vertical direction of the plane of the drawing, are arrayed alternately repeating in the row direction of the multiple pixels. An array may be employed where pixels10Ja and pixels10Jb are disposed alternately repeating in the column direction in addition to in the row direction.

In the configuration exemplified inFIG. 28, the control electrode81eof the blocking structure28B extends continuously over multiple pixels10Ja or multiple pixels10Jb in the column direction of the multiple pixels. Electrical contact between the control electrode81eand voltage line38may be provided at pixels located on the end portion of multiple pixels in the column direction, for example.

As described above, according to embodiments of the present disclosure, the effects of leak current can be suppressed, and accordingly, an imaging device capable of imaging with high image quality can be provided. Note that the conductivity types of impurity regions in the semiconductor substrate are not restricted to the arrangements in the above-described examples, and that configurations may be made where n-type and p-type are inverted. Also note that the transistors described above, such as the signal detecting transistor22, address transistor24, reset transistor26, and so forth, may be N-channel MOS devices or may be P-channel MOS devices. These transistors do not have to be all N-channel MOS devices or all P-channel MOS devices. In a case of using N-channel MOS devices for the transistors in the pixel, and using electrons as the signal charge, it is sufficient to invert the layout of sources and drains of the transistors.

Although a configuration where the impurity regions69paand69pbare disposed separated from each other, and a configuration where the impurity region69pcis disposed below the control electrode, have been exemplified in the above-described examples, these impurity profiles are not restrictive, and the region of the semiconductor substrate directly beneath the control electrode of the blocking structure may be the pixel isolation region69. In this case, an accumulation state, for example, can be formed in the region directly beneath the control electrode by applying bias voltage with a larger absolute value to the control electrode.

According to embodiments of the present disclosure, an imaging device that can suppress effects of leak current and take high quality images is provided. The imaging device according to the present disclosure is useful in, for example, image sensors, digital cameras, and so forth. The imaging device according to the present disclosure can be used in medical cameras, robotic cameras, security cameras, cameras installed in vehicles and used, and so forth.