Methods, devices, and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems

Methods, devices and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems. An example of such a system would be a transmit path, including the power amplifier, as used in wireless transmit systems. Advances made in CMOS technology, digital to analog converter (DAC) technology make it possible to implement a substantial part of such a system in the digital domain. Another aspect is the integration of a substantial part of such a transmit system in a single integrated circuit (IC). A digital implementation that allows for linearization of a broad range of nonlinear and time variant effects. Since this digital implementations operate a high clock frequency a energy efficient implementation is essential to keep the power consumption under control. Another aspects is the reuse of methods, devices and algorithms used for the linearization a transmit system to synchronize multiple transmit systems.

FIELD OF INVENTION

The invention relates to the generation and synchronization of multiple radio frequency (RF) signals. More specifically, the invention relates to systems for the digital to analog conversion synchronization and linearization of radio frequency signals as used in, but not limited to, wireless and wired transmission systems, beam forming systems, and active antenna arrays.

BACKGROUND

Modern wireless transmission systems require high linearity, high bandwidth, and high power efficiency to produce radio frequency (RF) signals. The requirements for high linearity and bandwidth are dictated by various wireless communication standards, such Long-Term Evolution (LTE), Wideband Code Division Multiple Access (WCDMA), and Global System for Mobile Communications (GSM). The bandwidth requirements stem from the higher data-rates expected from these systems. A high output frequency range is required to allow for multi-band operation. The power efficiency requirement comes from the demand for lower operating expenses, longer battery life, and simpler cooling systems.

Designing such wireless transmission systems while simultaneously optimizing all these requirements is a difficult task. Currently available building blocks used to design such systems have many limitations. Overcoming these limitations requires the use of sophisticated correction and compensation technics.

One such technic is the digital pre-distortion (DPD) system. An implementation of such a DPD system is depicted inFIG. 1. Many of these DPD systems digitally pre-distort a baseband signal S0before it is converted in the analog domain and up-converted to RF domain (SeeFIG. 1).

With the advent of: 1) high speed digital to analog converters (DACs), providing sampling rates well above 10 Giga samples per second (GSPS) and the necessary resolution to generate analog signals in the frequency range from DC to several GHz; and, 2) deep sub-micron complementary metal-oxide semiconductor (CMOS) processes allowing for power efficient signals processing, wireless transmission systems can be built completely in the digital domain, i.e. the frequency up conversion using a digital up converter (DUC) and the digital pre-distortion (DPD) can be performed in the digital RF domain as shown inFIG. 2.

Pre-distorting the signals in the digital RF domain has many advantages over baseband pre-distortion systems. First, imperfections of the analog modulator, such as clock feed-through and image suppression, which need additional compensation efforts, do not exist. Second, the RF signals in the digital domain can be generated arbitrarily perfect, limited only by the quantization accuracy used to represent the involved signals. Third, the range, flexibility, and stability of operations and functions necessary to perform the pre-distortions is easier implemented in the digital domain compared to the analog domain. However, even in advanced low power deep sub-micron CMOS processes, operating digital systems at clock frequencies of several GHz demand efficient implementations of the DUC and DPD in order to stay within a given power budget.

Also, the implementation of the DPD must be flexible enough to compensate for all kinds of distortion effects a wireless transmission system might exhibit. Such distortion effects might include, nonlinear static transfer functions, nonlinear dynamic transfer functions, memory effects, and hysteresis effects.

Another requirement for wireless transmission systems is the synchronization of multiple individual wireless transmission systems. Active antenna arrays and beam-forming applications rely on synchronization. In embodiments of the subject invention, the term “synchronization” in this context means that the individual wireless transmission systems generate substantially the same output given the same input.

In order to achieve this, the digital subsystems (DUC and DPD engines) must be synchronized. In embodiments of the subject invention, an Engine comprises any electronic circuit that produces output signals based on a set of input signals and internal signals. The DUC includes an internal phase accumulator which gets incremented at every clock cycle. The phase accumulator is a system with an internal state. In embodiments of the subject invention, an internal state comprises the status of internal signals at any given time within a system that operates on input signals and internal signals to produce output signals. In order to achieve synchronizations, these internal states have to be synchronized. After the digital subsystems are synchronized, the remaining analog parts (DAC, power amplifier (PA), coupling element (CP)) have to be aligned. In general, only the output power and output phase of the individual subsystems are aligned.

In embodiments of the subject invention, the term “substantially” is defined as at least close to and can include a given value or state, as understood by a person of ordinary skill in the art. In one embodiment, the term “substantially” refers to ranges within 25%, preferably within 5%, more preferably within 1%, and most preferably within 0.1% of the given value or state being specified.

SUMMARY OF THE INVENTION

The subject invention discloses the implementation of a digital pre-distortion in radio frequency (RF) transmission systems. The digital pre-distortion is performed in the RF domain capable of addressing distortion terms of the remaining analog system such as nonlinear static transfer functions, nonlinear dynamic functions, memory effects, and hysteresis effects.

The subject invention also discloses the characterization of the distortion terms by equivalent energy packages and the compensations of these distortion terms by energy packages.

The subject invention further discloses the efficient implementation of the digital pre-distortion using cascaded lookup tables.

The subject invention discloses the reuse of an apparatus and method used for pre-distortion to synchronize a plurality of such transmission systems.

The subject invention also discloses the synchronization of digital subsystems within the transmission system that comprise elements with internal states.

The subject invention further discloses a digital subsystem which does not need a startup sequence to achieve synchronization.

The subject invention also discloses a digital subsystem which has a bound recovery time case of an error condition.

There has thus been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are additional features of the invention that will be described hereinafter and which will form the subject matter of the claims appended hereto. There together with other objects of the invention, along with the various features of novelty, which characterize the invention, are pointed out with particularity in the claims annexed to and forming a part of this disclosure.

DETAILED DESCRIPTION

The following will describe, in detail, several embodiments of the present invention. These embodiments are provided by way of explanation only, and thus, should not unduly restrict the scope of the invention. In fact, those of ordinary skill in the art will appreciate upon reading the specification and viewing the present drawings that the invention teaches many variations and modifications, and that numerous variations of the invention may be employed, used, and made without departing from the scope of the invention.

For a conceptual understanding of the invention and its operational advantages, refer to the accompanying drawings and descriptive matter in which there are preferred embodiments of the invention illustrated. Other features and advantages of present invention will become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, which by way of example; illustrate the principles of the invention.

FIG. 1illustrates a conventional design for a radio frequency (RF) transmission system.FIGS. 3athrough 3cillustrate the corresponding frequency domain representations of the signals involved. The baseband signal S0is delivered to the system as a complex vector with the sampling rate (fin). In the digital pre-distortion (DPD) Engine, a compensation signal is added to the S0signal to form signal S1. The compensation signal is supposed to cancel the distortion terms introduced to the system by the digital to analog converter (DAC), the I/Q Modulator, and the power amplifier (PA). This added compensation signal S1requires 3 to 7 times the bandwidth of the original signal S0, depending on the distortions which need to be corrected. Following the DPD Engine, the signal S1is converted from the digital domain into the analog domain signal S2by the digital to analog converter (DAC) and then up converted to the RF domain signal S3with the I/Q Modulator. That is, signal S1is shifted in the frequency domain from baseband to the desired carrier frequency (fc). In the final step, signal S3is amplified with a power amplifier (PA) to get the desired output signal S4. With the process technology, and digital to analog converter (DAC) technology available today, it is possible to generate a signal S3in an integrated circuit (IC). The accuracy achieved by such integrated solutions is sufficient to meet the requirements of transmission standards such as LTE. However, todays PA technology is not able to amplify signal S3to the required power levels of signal S4with an accuracy compliant with the transmission standards such as LTE.

An ideal power amplifier (PA) would generate signal fS4, as illustrated inFIG. 3b. The nonlinearities of a practical power amplifier add distortion components to the output signal, which are characterized as harmonic distortions (the 2nd harmonic is shown as signal fS42inFIG. 3b), and inter-modulation distortions (shown as signal fS41inFIG. 3b). There can be many more distortion signals depending on the characteristics of the nonlinearities of the PA. The compound signal fS4+fS41+fS42is the output of the RF transmission system without an active pre-distortion engine. The task of the digital pre-distortion (DPD) processor is to find a set of parameters for the DPD Engine so that the DPD engine can add compensation signals to fS0to suppress signals fS41and fS42. Generally, this operation does not need to completely suppress signals fS41and fS41. The goal is to reduce the distortion signals fs41and fS42to levels to allow residual signals (fS43and fS44) to pass spectral requirements of various transmission standards as illustrated inFIG. 3c.

In the system illustrated inFIG. 1, not only the power amplifier (PA) adds distortion components, the I/Q modulator generates and add distortion components to the signal too. The most prominent distortion components are carrier feed-through and images opposite the carrier frequency (fc). These distortions have to be corrected, complicating the DPD process.

FIG. 2illustrates a RF transmission system capable of suppressing inter-modulation distortions fS41as well as harmonic distortions fS42, and avoid the signal distortion components introduced by the I/Q modulator. The baseband signal S0is up-converted into the RF domain in the digital domain using a digital up converter (DUC) to yield signal S1. Distortion components are added to signal S1using a digital pre-distortion (DPD) engine, yielding signal S2. An analog to digital converter (DAC) brings signal S2into the analog domain to yield signal S3. Signal S3is then amplified using a power amplifier (PA) to yield signal S4. Part of signal S4is coupled out, using a coupling element (CP) to yield signal S5. Except for the power levels, the signal characteristics of signals S4and S5are substantially identical.

In the observation path, signal S5is processed and converted into the digital domain using an analog to digital converter (ADC) to yield signal S6. Signal S6is then compared to signal S1in the DPD processor. An error measure computes the differences between signals S1and S6. Based on the error measure a set of parameters S7is calculated. Parameters S7are then sent to the DPD engine. The DPD engine adds distortion signals to signal S1according to parameters S7. This process is repeated till the error measure of signal S6reaches a minimum using an algorithm. In embodiments of the subject invention, this algorithm may comprise an iterative learning algorithm.

In the configuration of the system illustrated inFIG. 2, the DPD process is performed after signal S0has been digital up converted into the RF domain using a digital up converter (DUC) to yield signal S1. During this up conversion process the sampling rate of signal S0is multiplied by a factor n. Where n is greater than 1. The sampling rate of the signal S1at the output of the DUC is n time higher than the input sample rate frequency (fin) of signals S0. The frequency range the DPD can compensate for distortions is set by fdac/2, the first Nyquist zone of the DAC. Therefore, using the configuration of the system illustrated inFIG. 2, higher order harmonics and images can be corrected. The minimum sample rate for fdac is set by the highest frequency the transmission system is supposed to generate. Assuming the highest frequency is 3.6 GHz, this requires the fdac to be 2*3.6 GHz=7.2 GHz. However, the operation of the transmission system can be extended to higher Nyquist zone, reducing the requirements for the sampling rate fdac. In this case the DPD engine, DPD processors and observation path have to be reconfigured to operate in the higher Nyquist zones.

In modern CMOS processes, digital to analog converters operating at sampling rates above 10 GSPS are possible. The implementation of the digital up conversion and digital pre-distortion will be competitive in terms of power consumption with modern analog solutions illustrated inFIG. 1.

In order to take full advantage of the DPD engine to correct signals in the first Nyquist zone (0 to fdac/2), the observation path must be able to observe the whole frequency range. One implementation may use an analog to digital converter (ADC) operating at sample rate fdac. However, designing such ADCs with the necessary performance for such applications is difficult. The power consumption of such an ADC would be a significant contributor to the overall power consumption of the system. Also, the input signal conditioning necessary to drive such an ADC would make an integrated solution difficult to realize.

The first part of the present invention describes the hardware configuration of the observation path. The first goal of the subject invention is to achieve the required performance with the technology available today while reducing power-consumption and minimizing the digital signal processing requirements. A second goal of the subject invention is the integration of all components ofFIG. 2into one integrated circuit (IC). Depending on the required output power of the transmission system, integration of the power amplifier might not be possible. In that embodiment of the subject invention, the power amplifier may be an external component and the integrated circuit would provide the necessary input and output signals to control the external power amplifier (PA).

FIG. 4depicts one embodiment of the hardware configuration400of the present invention. The baseband signal S0is up-converted using a digital up-converter (DUC)401. The input sample rate frequency of S0is fin. The output signals of the DUC S1is at a sampling rate fdac=n*fin, wherein ‘fdac’ is the frequency of the signal CLK. This sampling rate is the same for all digital to analog converters (DAC)403,408, the analog to digital converter (ADC)407, and the DPD Engine402. Since the digital up-conversion of signal S0can be made arbitrarily accurate, signal S1can be assumed to be essentially distortion free, and therefore can be used as a reference signal.

Signal S1is passed through the main path which comprises DPD engine402, then DAC403, and then PA404to generate output signal S4. Part of signal S4is coupled out to yield signal S4C using a coupling element (CP)405.

In the first pass the DPD engine will not modify signal S1. Therefore, signal S4will have all distortion terms added by the DAC403and the PA404. At the same time signal S1will go through the reference path comprised of a Delay Engine409and a Reference DAC408.

The distortion compensation operation can be split into two steps. In the first step, the signal S6and S4C are aligned in phase and amplitude. In the second step, the distortion terms of signal S4are removed.

In the first step, the DPD processor406will adjust the DPD engine402, the main DAC403, the delay engine409, and the reference DAC408such that signals through the main path of signal S4C and the signals through reference path of signal S6meet at substantially the same time at subtraction block410.

The subtraction block410generates the difference of signals S4C and S6to yield signal S7. The detector ADC407converts the difference signal into a digital signal useful to the DPD processor406. The DPD processor406computes the time alignment signals S10, S9a, S91, and S11a; and the amplitude alignment signal S11b.

In the second step, the DPD processor406computes the DPD Engine parameters S9busing an algorithm. In embodiments of the subject invention, this algorithm may comprise an learning algorithm. There is a trade-off between the complexity of the detector and the complexity of the algorithm. In one embodiment, the detector ADC may be reduced to an RMS detector or a peak detector. However, the information extractable from such a signal would be limited and could lead to ambiguities in the execution of the algorithm. Using an ADC simplifies the task for the DPD processor to find the correct values for signals S9a, S9b, S10, S11a, and S11b, since the complete error vector over an observation time frame is available.

The requirements for the dynamic range, resolution, and accuracy of such an ADC407is significantly reduced since only the error signal S7has to be quantized. Signal S7is the difference between output signal S4C and the reference signal S6. Adjusting the input compliance range of the detector ADC407dynamically with the DPD processor406, using signals S12, allows for improved system performance or relaxed accuracy specifications for the ADC. For example, during the amplitude and delay alignment phase of the DPD algorithm, the input range of the ADC would be set to a high value since the error signal S7is expected to be high. Once the signals S4C and S6are aligned the error signal S7will become very small. Re-adjusting the input range of the ADC effectively improves the absolute resolution of the ADC, which makes it possible to further improve the alignment of the signals S4C and S6, or extract the distortion components introduced by the main path.

In the second step, after the alignment phase, the DPD processor406analyses the distortion components of signal S7and adjusts the DPD Engine parameter S9bsuch that the error measure on signals S7and S8is a minimum. This can be achieved using an algorithm executed by the DPD Processor406. In embodiments of the subject invention, this algorithm may comprise an iterative learning algorithm or a learning algorithm.

The overall system performance hinges on the quality of the reference signal S6generated by the reference DAC408. Signal S6is an internal low power signal terminated by a well-defined load presented by the subtraction block (SUB)410.

The system illustrated inFIG. 4makes the design of a high quality reference digital to analog conversion408possible. The quality of reference DAC is limited by the matching performance of the DAC itself and coupling interactions between the reference DAC408and the rest of components in the system400. Distortions introduced to signal S6must be kept small compared the expected distortion components of signals S4and S4C.

One embodiment of subtraction block410is a Kirchhoff current node, assuming signals S6and S4C are represented in the current domain. Other exemplary embodiments may include active circuitry such as an operational amplifier.

One advantage of the present invention is that the system requires only one clock frequency. The main DAC403, the reference DAC408, and the detector ADC407all operate on the same clock frequency as illustrated inFIG. 4. Prior art systems, like the one illustrated inFIG. 1, require at least two different clock frequencies. One clock signal to operate the digital to analog converter (DAC) and the analog to digital converter (ADC), and another clock signal to operate the I/Q modulator and demodulation. Clock interference in such prior art systems, and the resulting performance degradation, is a problem that is usually solved with a carefully designed frequency plan. However, the request for more frequency agile systems as required for software defined radios (SDR) applications makes the design of such systems difficult. Since the present invention requires only one clock signal, which is at a higher frequency then the output signals, the problems of clock interference are avoided.

Another advantages of the present invention is that the necessary building components can be integrated into modern CMOS processes, with the exception of the power amplifier (PA) which can be internal or external. All other building components of the invention are well understood in the industry and already available in an integrated form.

In embodiments of the subject invention, the algorithm implemented in the DPD processor to achieve alignment of the reference signals with the transmission signal, and subsequently the compensation of the distortion errors can be based on iterative gradient decent methods or other learning algorithms.

Synchronization of RF Transmission Systems

In some applications, it is necessary to synchronize multiple RF transmission systems. Active antenna array systems and beam-forming systems are examples of such systems.FIG. 6illustrates such a system with three individual RF transmission systems600.

The present invention is not limited to three individual RF transmission systems. Any number of RF transmission systems can be synchronized with the subject invention. However, for simplicity only three RF transmission systems are illustrated. Also,FIG. 6is a generalized diagram which illustrates many possible embodiments of the synchronization system.

In an ideal case, all individual RF transmission systems behave exactly the same. That is, input to output transmission characteristics of the individual RF transmission systems are the same. However, due to different signal propagation delays in the DAC and the PA caused by part to part delay and gain variations of these components, timing skews of the CLK signals at the CLK terminals of the transmission systems TRX_SYS1to TRX_SYS3contribute to synchronization errors. Synchronization in this context is best described as follows: if the same digital signal is applied to the individual RF transmission systems, all RF transmission systems will produce output signals substantially identical in phase and power. To overcome variations in the individual RF transmission systems, calibration technics have to be applied to achieve synchronization.

FIG. 5illustrates an embodiment of an RF transmission system with calibration capability. The synchronization reference generator513generates a reference signal S16which can be added to transmission signal using adder512. The synchronization reference signal S16can be activated or deactivated by signal S14a. If the synchronization generator513is deactivated, signal S16is set to zero, i.e. the transmission signals are not altered. The switch511can route signals S6and the externally applied synchronization reference signal S13to the subtract block510at the same time (mode1) or time inter-leafed (mode2) depending on the state of signal S14c. Also depending on signals S14c, Signal S7is computed as S7=S4C−S6−S13for S15in the first state; or S7=S4C−S6in the second state; or S7=S4C−S13in the third state. The DPD processor506can adjust the delay of the main path, the signal path from signal S0to signal S4, by adjusting the delay in the FIFO515, the main DAC503, or at the phase accumulator of the digital up-converter501. The control signals for these operations are S91, S92, and S93.

Phase synchronization of the RF transmission system requires that the digital signal S2, the output of the digital sub system, produces the same signal in each individual RF transmission system.

The digital subsystem in the individual RF transmission systems is comprised of the clock generator514, the de-framer logic515, the digital up-converter501, the adder512, the FIFO515, the DPD engine502, the synchronization reference generator513, and the delay engine509.

Since, the digital up converter501has a build in phase accumulator707(i.e. a system with internal states (memory)), it must be guaranteed that all phase accumulators have the same internal states in relation to the supplied input data ‘IN’.

After synchronization of the digital subsystems is achieved, the output signals S4of the individual RF transmission systems can be aligned.

Major contributors of the alignment errors are the DAC503and the PA504, as well as the timing errors of signals CLK in the individual RF transmission systems. These errors can be addressed with a calibration technics, comparing reference signals to a similar signal routed through the main path of the system.

The technics to detect phase synchronization are similar to the technics used for distortion compensations and the same hardware components can be reused for this task. To compensate for phase synchronization mismatch, control signals S91, S92, and S93can be used. Signal S92is a coarse adjust. The resolution of signal S92is the period of CLKI.

With control signal S93fine adjustments can be made into the pico second range using analog delay lines in the clock path of the digital to analog converter503. Digital solutions are also possible using a delay filter.

In some embodiments of the subject invention, it is possible to adjust the phase of signal S4by changing the phase of the NCO in the digital up converter501using control signal S91.

Gain mismatch in the power amplifier (PA), the reference mismatch of the Digital to analog converter, and mismatches of the digital to analog converter can cause variations in the output power of individual RF transmission systems. In the present invention, the DPD engine may be used to compensate for these mismatches, using control signal S94. However, this mismatch errors can also be addressed within in the respective blocks using additional control signals.

Using the present invention, many different methods can be used for calibration. The calibration can be performed in the time domain or in the frequency domain. The system can be calibrated in reference to an ‘absolute’ signal, meaning the signals are solely generated for calibration purposes or in reference to a ‘relative signal’, meaning the output signal of a dedicated transmission system is declared the master signal and all other RF transmission systems are calibrated to match the characteristics of this master signal. The system can be calibrated in ‘foreground’ mode or in ‘background’ mode. In foreground mode, the transmission system is taken off-line and the calibration is performed. Once completed, the transmission system is placed back on-line. In background mode, the transmission system is always on-line.

For example, a frequency domain background calibration would be implemented using the synchronization reference generators513and605to generate similar signals.

The reference signals generated by513and605occupy a part of the spectrum which is not used by the payload signal (the up-converted signal S0). However, the characteristics of the signal path for the payload signal are similar to the reference signals. Thus, if the reference signals in the individual transmission systems align, the payload signals will align too.

Another example of background calibration using relative signals calibration, would involve a payload signal with a built-in characteristic which makes it possible to extract the necessary calibration information. An example would be a signal with a pilot tone.

The coordination of the synchronization procedure is the task of the sync controller606. The sync controller606activates the control signals S1, S2, S3, and S20based on a calibration mode. The sync controller606coordinates operation with the DPD processor506in the individual RF transmission systems using control signals S1, S2, and S3. The sync controller606routs signals OC1, OC2, OC3, and C0to appropriate terminals on the RF transmission systems using control signals S20. The sync controller can be implemented as a state machine using a micro controller.

In the most general form, the switch block is capable of routing all input signals OC1, OC2, OC3, and C0to all possible output signals CC1, CC2, CC3, C1, C2, and C3.

Depending on the calibration scheme not all switching combinations may be necessary.

In one embodiment of the subject invention, a synchronization reference signal generator605generates a reference signal C0which has the same characteristic as signal S16generated in the transmission system by the synchronization reference generator513. The switch block604routs signal C0to terminal S13of all individual RF transmission systems subject to synchronization,601,602, and603. The switch block604, can distribute signal C0so that either derived signals C1, C2, and C3appear on the individual transmission systems at the same time, or time interleaved such that only one signal of the set C1, C2, or C3is active at a given time. Which of the previous mentioned methods is used depends on the implementation and number of transmission systems, but is irrelevant for the synchronization method of the present invention.

However, the subject invention requires that the delays from terminal OUT of the synchronization reference generator605to the terminal S13of the individual transmission systems601,602,603be the same. The switch block also routs signal OC1to signal CC1; signal OC2to signal CC2; and signal OC3to signal CC3. In these embodiments, it is assumed that the synchronization reference generator513and the DUC501in the individual transmission systems are already synchronized.

In one embodiment the sync ref generator605can be implemented using a transmission system like601.

The synchronization of one individual transmission system to the reference signal C0is as follows, using transmission system601as an example. The procedure is repeated for the remaining transmission systems. The sync controller606configures Switch Block604to send signal C0to terminal S13, and signal OC1to terminal S4C of transmission system601. The sync controller606activates the synchronization reference generator in transmission system601, which generates signal S16. The sync controller606sets the switch511so that signal S7is the difference of signals S4C and S13. The DPD processor506will minimize the error measure of signal S7by adjusting signal parameters of signal S16and the delay settings of the FIFO515, the digital up converter501, and the main DAC503. The DPD processor506can use learning algorithms to find the minimum of the error measure of signal S7. The algorithm will stop once the error measure is sufficiently small. The DPD processor506will report the completion of the task to the sync controller606, and the sync controller will proceed with the calibration of the next transmission system. Meanwhile, the DPD processor will reconfigure the transmission system601so that distortion terms can be calibrated.

In another embodiment of the subject invention, the RF transmission systems are calibrated relative to a master transmission system. In this embodiment, it is assumed that at least one aspect of signals IN1, IN2, and IN3is similar enough so that the delay mismatch can be extracted by comparing signal OC1with signal OC2; and signal OC1with signal OC3. In this embodiment, the synchronization reference generators605,513, and adder512can be removed from the transmission systems500and600.

One of the transmission systems will be declared the master system. All the delay settings S91, S92, S93in the master system we have default values. There will be no calibration procedure for the master system.

In this example, transmission system601is declared the master system. For the calibration of the first slave system602, the switch block sends signal OC1to terminal S13of transmission system602; and signal OC2to terminal S4C of transmission system602. Transmission System602is configured by the synchronization processor such that signal S7is the difference between terminal SC4and terminal S13. From this point on, the calibration procedure is the same as the previous embodiment.

FIG. 6bdepicts a possible embodiment of the system ofFIG. 6without a switch block604. Antenna array640receives the output signal of the individual transmission systems601,602, and603. It is assumed that the coupling parameters from each antenna element (ANT1, ANT2, ANT3) to each other antenna element is well characterized.

The directional couplers607,608, and609take the signals coming from the antenna to terminals S4C. All the transmission systems process there respective payload signals. The first transmission system601adds a pilot signal to its payload signal using its internal sync reference generator513. This compound signal is transmitted over ANT1and received by ANT2and ANT3.

The received signals of ANT3are coupled to terminal S4C of system603. The DPD processor of system603calculates a delay value del_13based on the arrival from the received signals from system601, and the known delay characteristic of the antenna elements involved. Transmission system601removes the pilot signal, and system602adds the pilot signal to its payload signal. Now, the DPD processor of system603calculates a delay value del_23based on the arrival from the received signals from system602, and the known delay characteristic of the antenna elements involved.

The DPD processor of system603communicates the delay values del_13and del_23to the sync controller606. The sync-controller606communicates the delay corrections to systems601and602. The DPD processors in systems601and602will adjust the delay of the main signals path accordingly. After this step the delay values del_13and del_23are the same and hence systems603and602are synchronized. The same procedure is applied to the remaining unsynchronized transmission systems.

FIG. 6depicts the top-level view of one embodiment used for synchronization of the digital sub-system. A data source block610generates signals IN1, IN2, and IN3which are sent to the individual subsystems. The format of the signals IN1,1N2, and1N3can be based on a frame structure. An exemplary frame structure is illustrated inFIG. 7b. The frame can start and end with a marker M1or M2. D1to Dn is the payload data generated by the data sources612. PACC is the phase accumulator value for the digital up-converter. PACC is generated in the data source block610and updated with the frame rate (fr_rate). The framer block FR613, bundles M1, D1to Dn, PACC, and M2together and sends the frame to the individual transmission systems.

In the transmission system the de-framer702reverses the process. Based on the makers M1or M2the frame boundaries are detected. D1to Dn are extracted and send to terminal S. PACC is extracted and send to terminal PACC. At the end of the frame signal EOF is generated to indicate that all data was received and is valid for further processing. Component703is a typical implementation of the digital up converter. The interpolator increases the sampling rate ‘fin’ of data stream S0to ‘f_dac’ the sampling rate of data stream S1. The phase accumulator is clocked with CLKI at a sampling rate ‘f_dac’. Every clock cycle the count is increased by the frequency tuning works FTW.

The counter of the corresponding phase accumulator in the data source block611is increased with the frame rate (f_frame). The frequency tuning word of611is higher by a factor of f_dac/f_frame than the frequency tuning word of the phase accumulator in the transmission systems601,602, and603. This requirement is necessary so that the phase accumulators in the data source block and the individual transmission systems stay synchronized.

At each beginning of a frame the counter of phase accumulator707is pre-loaded with the expected phase value computed by611in the data source block610. Signal EOF is used to transfer PACC in the counter707.

The counter in707increments its value again at every clock cycle CLKI by the frequency tuning word. The output of the phase accumulator707is mapped706to sine and cosine functions, and a complex multiplier705multiplies the complex data stream D1Dn with the sine and cosine to yield the up-converted signal S1.

Timing violations (i.e. setup and hold times) between clock domains CLK and CLKI can be resolved using well established technics like FIFOs, DLLs, or PLLs.

The distortion terms of an transmission system can be modeled by static nonlinear, dynamic nonlinear, memory, and hysteresis effects as illustrated inFIG. 10. The sources of these nonlinearities are related to the components used in the transmission system and the behavior of the environment the components operate within. To compensate for the nonlinearities of the transmission systems, an error model of the systems capturing the dominant error mechanism is implemented. The error model computes error signals based on the input and internal states of the transmission system. The error signals are subtracted from the transmission signals to yield the pre-distorted signal.

For systems illustrated inFIG. 2, where the digital to analog conversion is performed in the RF domain, the correction is straight forward. These errors can be computed as energy packages since the system is updated in fixed time intervals as shown inFIG. 10. The error energy is compensated by adding or subtracting compensation energy package.

InFIG. 10the solid line displays the ideal output signals with sampling rate t1. The dotted line is an example of the actual output signal of a transmission system including all distortion terms. The area between the solid line and the dotted line, within one time period t2, is the error energy.

t1is the sampling rate necessary to generate the desired output signal. t2is the sampling rate of the transmit system. t2is a fraction of t1. Practical values for t2are ½ or ¼ of t1. Splitting up t1into two equal sub interval t2gives enough flexibility to design compensation charge packages for the first and the second half of t1so that the frequency domain properties of the resulting pre-distorted signal are sufficient for most applications. Since t2will not change during the operation of the transmission system, all errors can be expressed as energy packages of constant duration t2.

A possible implementation of such an error model is illustrated inFIG. 9.

The input signal a<n:0> is the digital representation of expected output signal of the transmission system. The model calculates a digital signal err<m:0>, which is a digital representation of the distortions the transmission system is expected to produce. Signal err<m:0> is subtracted from signal a<n:0> to yield the pre-distortion signal acorr<nn:0>. Signal acorr<nn:0> is subsequently processed by the analog subsystem of the transmission system. The analog subsystem is comprised of a digital to analog converter and a power amplifier. Since the signal acorr<nn:0> contains the expected errors the analog subsystem will add to the transmission signal a<n:0>, the output of the analog subsystem should be the substantial error free representation of the input signal a<n:0> signal.

The computation the of digital error signal err<m:0> is based on a error model of the transmission system. The errors are also a function of the environment the transmission system is operating within. Examples of such environmental factors include, but are not limited to: temperature, supply voltages, and bias voltages. There are two methods to get a value for these environmental factors. The first method is to measure the environmental factor with a sensor system. The second method is to estimate the environmental factor based on the history of the input signal a<n:0>.

For example, inFIG. 9, the temperature of the transmission system could be measured with a sensor system906, the signal is converter into the digital domain by means of an analog to digital converter and subsequently processed by computational block g8904to yield intermediate variable ex8. The status of the bias system could be predicted by a mathematical model g2903based on the history of the input data signal a<n:0>. In order to capture static nonlinear errors, a computational block g0901is used to calculate an intermediate variable ex0. In order to capture dynamic nonlinear errors a computational block g1902is used to calculate intermediate variable ex1.FIG. 9depicts computational blocks901to905which compute intermediate variables ex0to ex9for the error model. Based on the complexity of the transmission system there might be more or less intermediate variables necessary to generate a sufficient accurate error model. Based on the dependencies of the effects model by901to905, signals k1and k2are formed. Signals k1and k2are multi dimensional vectors of size sk1and sk2, wherein sk1and sk2are the number of intermediate signals ex0to ex9contributing to signals k1and k2.

The multi-dimensional vector signals k1and k2are the inputs of nonlinear mapper blocks908and909. A nonlinear mapper block computes errors signals based on its input signals. The error signals from nonlinear mapper1(908) and nonlinear mapper2(909) and are added and subsequently subtracted from the transmits signals a<n:0> to yield signal acorr<nn:0>.FIG. 9depicts two nonlinear mapper blocks. Depending on the complexity of the transmission system, more or less nonlinear mapper blocks might be necessary to achieve a sufficient accurate error model.

FIG. 8Cillustrates an implementation of an nonlinear mapper. Since the DPD engine operates at high sampling rates it is important to find an efficient implementation.FIG. 8aillustrates a typical transfer function of a transmission system where ‘a’ is the input space and ‘y’ is the output space. For a power amplifier, the ‘a’ would represent the input power and the ‘y’ would represent the output power. A common approach is to build a model for the error function ‘yerr’ which is the difference between the ideal transfer and the actual transfer function.

A common behavior of such transmission systems it that the error function is zero or very small over a very wide operating range and only substantial at the corner or fringe regions, as illustrated inFIG. 8aandFIG. 8b. One aspect of the present invention takes advantage of that behavior. The error is encoded in parameterized basis functions f0. . . fn. The input space is divided into main sections based on the most signification bits of the input space. If the approximation error of the basis function to the error function is smaller than a given limit, then basis function gets assigned to this section. If the error is bigger than a given limit, then the section is subdivided into two subsections and new basis functions are assigned to the sub sections. This process is repeated till the error between basis function and error functions in all sections are below a given limit.

For example, inFIG. 8b, the input space is 8 bits (a<7:0>) and the basis functions are linear interpolation functions (err=p1*a<5:0>+p0). Parameters p0, p1are stored as a set (e.g. f0_param) in the look-up-table803.

The first most significant bits a<7:6> are used to divide the input space into 4 sectors, 00, 01, 10, and 11. For sectors 00, 01, and 10, the error is below the limit and the zero error function f0(with the parameter set p1=0 and p0=0) is assigned to these sectors. The assignment operation is implemented with a look up table801. In Sector 11 the behavior of the error functions is very nonlinear and two basis functions have to be assigned. In look up table801, at location11_index_f, the parameters for the LUT2address generator802are stored.

The memory address generator802calculates the address for lookup table803based on parameters11_index_f and a<5:4>. In the example ofFIG. 8, parameter-set11_index_f would cause the memory address generator802to take bit a<5> and add one to it to generate the address for LUT2(803).

FIG. 8cillustrates the implementation of a nonlinear mapper in a one dimensional space. In general, the nonlinear mapper would be implemented in a multi dimensional space to model the behavior of the error model for dependent variables. In this case the input variable ‘a’ would be a composed of a subset of the variables set ex0to exn ofFIG. 9.

InFIG. 8conly one basis function calculator804is illustrated. However, multiple different basis functions might be desirably fit the error function better. To implement a plurality of basis-functions, the parameter set stored in lookup table803could be extended to hold an indicator of the basis-function to be use in the basis function calculator804. Alternatively, a plurality of systems800could be implemented in parallel to achieve a more adaptable nonlinear mapper.

The circuit illustrated inFIG. 9is a possible implementation of the DPD engine illustrated inFIGS. 4 and 5. In order to extract the parameter for the DPD engine, the DPD processor keeps a record for the transmitted data S1and collects a record of the error signals S8it receives from the detector ADC. The DPD processor reshapes the two records to align the transmission data and the received error signals and computes an error measure. Time domain and frequency domain analysis technics can be applied to achieve this goal. Based on the error measure the parameter set of the DPD engine will be adjusted to minimize the error measure. This is achieved using learning algorithms.

The many aspects and benefits of the invention are apparent from the detailed description, and thus, it is intended for the following claims to cover such aspects and benefits of the invention, which fall within the scope, and spirit of the invention. In addition, because numerous modifications and variations will be obvious and readily occur to those skilled in the art, the claims should not be construed to limit the invention to the exact construction and operation illustrated and described herein. Accordingly, all suitable modifications and equivalents should be understood to fall within the scope of the invention as claimed herein.