Semiconductor device and power conversion device

An SBD includes: a terminal well region formed to surround an active region; a field insulating film formed to cover part of the terminal well region; a surface electrode formed on a drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; a surface protection film covering an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of a single crystal substrate. An end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in a straight portion of a terminal region based on a position of an end portion of an outer side of the terminal well region.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on PCT filing PCT/JP2019/015723, filed Apr. 11, 2019, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a power conversion device, and particularly to a semiconductor device having a surface protection film and a power conversion device using the same.

BACKGROUND ART

Known is a technique of providing a p-type guard ring region (a terminal well region) in a so-called terminal region in an outer peripheral portion of an n-type semiconductor layer for securing withstanding pressure performance in a vertical semiconductor device used in a power device, for example (for example, Patent Document 1 described below). In the semiconductor device having the guard ring region, an electrical field generated when reverse voltage is applied to a main electrode of the semiconductor device is reduced by a depletion layer formed by a pn junction between the n-type semiconductor layer and the p-type guard ring region.

In a Schottky barrier diode (SBD) in Patent Document 1, a surface electrode is covered by polyimide as a surface protection film except for a region in which a wire bonding is performed. The Schottky barrier diode is sealed using a sealing material such as gel in some cases. Such a surface protection film and sealing material may be applied not only to the SBD but also to the other semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET).

PRIOR ART DOCUMENTS

Patent Documents

SUMMARY

Problem to be Solved by the Invention

The surface protection film of polyimide and the sealing material such as gel, for example, tend to include moisture under high humidity. This moisture may have a negative effect on the surface electrode. Specifically, there is a case where the surface electrode is transferred into the moisture, or the surface electrode reacts with the moisture and an insulating material is deposited. In such a case, the surface protection film tends to be peeled at an interface between the surface electrode and the surface protection film. There is a possibility that a cavity in a lower portion of the surface protection film on an outer periphery of the surface electrode formed by the peeling of the surface protection film acts as a leak path, and insulation reliability of the semiconductor device is diminished.

The present invention therefore has been made to solve problems as described above, and it is an object of the present invention to provide a semiconductor device having high insulation reliability.

Means to Solve the Problem

A semiconductor device according to the present invention includes: a semiconductor substrate; a drift layer of a first conductive type formed on the semiconductor substrate; at least one terminal well region of a second conductivity type formed on a surface layer portion of the drift layer to surround an active region in a plan view in a terminal region outside the active region; a field insulating film formed to cover part of the terminal well region on the drift layer; a surface electrode formed on the drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; an upper surface film formed on the field insulating film and the surface electrode to cover an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of the semiconductor substrate, wherein the terminal region includes a straight portion and a corner portion in a plan view, and an end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode (5;50) in the straight portion of the terminal region based on a position of an end portion of an outer side of the terminal well region.

Effects of the Invention

According to the semiconductor device of the present invention, a deposition of an insulating material on the surface electrode is suppressed in a corner portion of the terminal region, and a peeling of the upper surface film can be avoided. Thus, the present invention can contribute to increase in insulation reliability of the semiconductor device.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

DESCRIPTION OF EMBODIMENT(S)

Embodiments of the present invention are described hereinafter. In the description, “an active region” in a semiconductor device is defined as a region in which a main current flows when the semiconductor device is in an ON state, and “a terminal region” in the semiconductor device is defined as a region around the active region. “An outer side” of the semiconductor device means a direction from a center portion toward an outer peripheral portion of the semiconductor device, and “an inner side” of the semiconductor device means a direction opposite to “the outer side”. With respect to a conductivity type of an impurity, the description is based on an assumption that “a first conductivity type” is an n type and “a second conductivity type” is a p type, however, also applicable reversely is that “a first conductivity type” is a p type and “a second conductivity type” is an n type.

Herein, a term of “MOS” is formerly used for a lamination structure of metal-oxide-semiconductor, and is considered to be made up of initials of Metal-Oxide-Semiconductor. However, specifically in a field-effect transistor having a MOS structure (simply referred to as “the MOS transistor” hereinafter), materials of a gate insulating film and a gate electrode are improved from a viewpoint of a recent integration and improvement of a manufacturing process. For example, in the MOS transistor, polycrystal silicon is adopted as a material of a gate electrode in place of metal from a viewpoint of a formation of mainly a source and drain in a self-aligned form. A high-dielectric constant material is adopted as the material of the gate insulating film from a viewpoint of improvement of electrical characteristics, however, the material is not necessarily limited to oxide.

Accordingly, the term of “MOS” is not necessarily adopted only to a lamination structure of metal-oxide-semiconductor, and the same applies to the present specification. That is to say, in view of a technical common knowledge, “MOS” is defined to have a meaning of not only an abbreviated word of Metal-Oxide-Semiconductor but also widely includes a lamination structure of conductive body-insulating body-semiconductor.

When there is descriptions of “on . . . ” and “cover . . . ” in the description hereinafter, they does not hinder presence of an intervening object between the constituent elements. For example, even when there is a description of “B provided on A” or “A covers B”, it can mean that the other constituent element is provided between A and B. Used in the description hereinafter are terms each indicating a specific position or direction such as “upper side”, “lower side”, “lateral side”, “bottom”, “front”, and “back”, for example, however, these terms are used for convenience of explanation, and do not relate to a direction in an actual use.

The drawings described hereinafter illustrate schematic configurations. A size, a position, and a mutual relationship thereof of elements illustrated in the drawings are not necessarily illustrated accurately, but may be appropriately changed. A mutual relationship of sizes and positions of elements illustrated in the different drawing is not also necessarily accurately illustrated, but can be appropriately changed.

In each drawing, the same reference numerals will be assigned to constituent elements having names and functions similar to those in the other drawings. Thus, a description of the elements similar to those described already using the other drawings is omitted in some cases to avoid a redundant description.

FIG.1is a partial cross-sectional view of a Schottky barrier diode (SBD)100which is a semiconductor device according to an embodiment 1 of the present invention.FIG.2is a plan view of the SBD100, and a cross-sectional view along an A-A line inFIG.2corresponds toFIG.1. A left side portion ofFIG.1is an active region in which main current flows when the SBD100is an ON state, and a right side portion inFIG.1is a terminal region which is a region outside the active region of the SBD100. A region corresponding to the active region is referred to as “an inner side region RI” and a region corresponding to the terminal region is referred to as “an outer side region RO” hereinafter.

As illustrated inFIG.1, the SBD100is formed using an epitaxial substrate30made up of a single crystal substrate31and an epitaxial layer32formed on the single crystal substrate31. The single crystal substrate31is a semiconductor substrate made up of n-type (first conductivity type) silicon carbide (SiC), and the epitaxial layer32is a semiconductor layer made up of SiC epitaxially grown on the single crystal substrate31. That is to say, the SBD100is SiC-SBD. In the present embodiment, the epitaxial substrate30having 4H polytype is used. Herein, an upper side and a lower side of the epitaxial substrate30inFIG.1are defined as “a front side” and “a back side”, respectively, and a main surface on the back side of the epitaxial substrate30is referred to as “a back surface S1” and a main surface on the front side thereof is referred to as “a front surface S2”.

A p-type (second conductivity type) terminal well region2is selectively formed on a surface layer portion on the front side of the epitaxial layer32in the terminal region. An n-type region except for the terminal well region2in the epitaxial layer32constitutes a drift layer1in which current flows by drift. An impurity concentration of the drift layer1is lower than that of the single crystal substrate31. Thus, the single crystal substrate31has lower resistivity than the drift layer1. Herein, the impurity concentration of the drift layer1is equal to or larger than 1×1014/cm3and equal to or smaller than 1×1017/cm3.

As shown by dotted lines inFIG.2, the terminal well region2is a frame-like (ring-like) region surrounding the active region in a plan view, and functions as a so-called guard ring. As illustrated inFIG.1, assuming that an end portion of an inner side (inner peripheral side) of the terminal well region2is a boundary, an inner side of the boundary is defined as the inner side region RI which is the active region and an outer side thereof is defined as the outer side region RO which is the terminal region. The outer side region RO is a frame-like region surrounding the inner side region RI in a plan view, and includes a straight portion which is a straight region along each side of a semiconductor chip and a corner portion which is a curved region connecting the two straight portions extending in different directions.

The terminal well region2may include a plurality of regions with different impurity concentrations. The number of the terminal well regions2is not limited to one, however, the plurality of terminal well regions2disposed separately from each other in a nested form may be provided in the outer side region RO, for example.

A field insulating film3, a surface electrode5, and a surface protection film6are provided on a front surface S2of the epitaxial substrate30. A back surface electrode8is provided on the back surface S1of the epitaxial substrate30. The illustration of the field insulating film3and the surface protection film6is omitted in a plan view inFIG.2. A position of an end portion of the surface protection film6, that is to say, an outline of the surface protection film6is shown by a broken line.

The field insulating film3covers part of the terminal well region2, and goes beyond an end portion of an outer side (also referred to as “an outer peripheral end”) of the terminal well region2to extend to the outer side of the terminal well region2. The field insulating film3is formed by an insulating material such as SiO2or SiN, for example, and preferably has a thickness of 10 nm or more. For example, an SiO2film having a thickness of 1 μm can be used as the field insulating film3.

The surface electrode5is provided on at least part of the front surface S2of the inner side region RI in the epitaxial substrate30. In the present embodiment, the surface electrode5is made up of a Schottky electrode5aformed on the front surface S2of the epitaxial substrate30and an electrode pad5bformed on the Schottky electrode5a, and end portions of the Schottky electrode5aand the electrode pad5bare located on the field insulating film3.

The Schottky electrode5ahas contact with the drift layer1of the inner side region RI and the terminal well region2of the outer side region RO. Accordingly, the surface electrode5is electrically connected to the terminal well region2. Metal forming a Schottky junction with the drift layer1which is an n-type SiC semiconductor is applicable as a material of the Schottky electrode5a, and titanium (Ti), molybdenum (Mo), nickel (Ni), gold (Au), or tungsten (W), for example, can be used. A thickness of the Schottky electrode5ais preferably equal to or larger than 30 nm and equal to or smaller than 300 nm. A Ti film having a thickness of 100 nm can be used as the Schottky electrode5a, for example.

Metal including one or some of aluminum (Al), copper (Cu), Mo, or Ni or Al alloy such as Al—Si (silicon) can be used as a material of the electrode pad5b. A thickness of the electrode pad5bis preferably equal to or larger than 300 nm and equal to or smaller than 10 μm. For example, an Al film having a thickness of 3 μm can be used as the electrode pad5b.

The surface protection film6is an upper surface film provided on the field insulating film3and the surface electrode5to cover the end portion of the surface electrode5. More specifically, the surface protection film6covers an upper surface end portion and an end surface (side surface) of the electrode pad5b, and an end surface of the Schottky electrode5a. Thus, an outer peripheral portion of the upper surface of the electrode pad5bis covered by the surface protection film6. However, a center portion of the electrode pad5bis not covered by the surface protection film6so as to be able to function as an external terminal. That is to say, the surface protection film6includes an opening part exposing the upper surface of the electrode pad5bin the inner side region RI as illustrated inFIG.1. The surface protection film6covers at least part of the front surface S2of the epitaxial substrate30in the outer side region RO.

Adoptable as a material of the surface protection film6is polyimide which is an insulating material made of resin reducing stress from outside, silicon nitride (SiN) with high resistance capable of discharging external load occurring in gel via an electrode, or a multilayer film made up of these materials stacked in layers, for example.

Metal including one or some of Ti, Ni, Al, Cu, and Au, for example, can be used as a material of the back surface electrode8.

Herein, in the SBD100of the present embodiment, the end portion of the outer side (outer peripheral end) of the surface electrode5in the corner portion of the outer side region RO is located on an inner side in relation to the end portion of the outer side of the surface electrode5in the straight portion of the outer side region RO based on a position of the end portion (outer peripheral end) of the outer side of the terminal well region2. That is to say, when a distance from the outer peripheral end of the terminal well region2to the outer peripheral end of the surface electrode5is L, in a case where the outer peripheral end of the surface electrode5is located on an inner side in relation to the outer peripheral end of the terminal well region2as illustrated inFIG.1, a distance L2in the corner portion of the outer side region RO is larger than a distance L1in the straight portion of the terminal region (RO) as illustrated inFIG.2. That is to say, a relationship of L2>L1is established.

Also considered is a case where in the SBD100of the present embodiment, the outer peripheral end of the surface electrode5is located on an outer side in relation to the outer peripheral end of the terminal well region2as illustrated inFIG.3. In this case, when the distance from the outer peripheral end of the terminal well region2to the outer peripheral end of the surface electrode5is L, the distance L2in the corner portion of the outer side region RO is smaller than the distance L1in the straight portion of the outer side region RO as illustrated inFIG.4. That is to say, a relationship of L1>L2is established.

FIG.2andFIG.4, the outer peripheral end of the surface electrode5in the corner portion of the outer side region RO (terminal region) has a curved shape, but needs not have the curved shape. For example, as illustrated inFIG.5, the outer peripheral end of the surface electrode5may include a straight portion in the corner portion of the outer side region RO. As illustrated inFIG.6, the outer peripheral end of the surface electrode5may include a plurality of bended portions bended in different directions in the corner portion of the outer side region RO.

As described above, the number of the terminal well regions2provided in the outer side region RO is not limited to one, however, the plurality of terminal well regions2disposed separately from each other in a nested form may be provided as illustrated inFIG.7, for example. The surface electrode5is electrically connected to at least one of the plurality of terminal well regions2. In such a case, the outer peripheral end of the surface electrode5in the corner portion of the outer side region RO is located on the inner side in relation to the outer peripheral end of the surface electrode5in the straight portion of the outer side region RO based on a position of the outer peripheral end of the terminal well region2electrically connected to the surface electrode5in the plurality of terminal well regions2.

In the present embodiment, SiC is used as a material of the epitaxial substrate30. An SiC semiconductor has a wider band gap than an Si semiconductor, and an SiC semiconductor device is excellent in pressure resistance, and has a high allowable current density and heat resistance compared with an Si semiconductor device, thus can be operated under high temperature. The material of the epitaxial substrate30is not limited to SiC, however, Si or the other wideband gap semiconductor such as gallium nitride (GaN) is also applicable, for example.

The semiconductor device according to the present embodiment may be a diode such as a pn junction diode or a junction barrier Schottky (JBS) diode, for example, other than the SBD.

Modification Example

FIG.8is a cross-sectional view illustrating a configuration of an SBD101according to a modification example of the embodiment 1, and is a drawing corresponding toFIG.1. The plurality of terminal well regions2disposed separately from each other in a nested form are provided in the outer side region RO of the SBD101inFIG.8in the manner similar toFIG.7. Furthermore, the plurality of surface electrodes5are provided in a nested form to be connected to the plurality of terminal well regions2, respectively.

In this case, the outer peripheral end of the surface electrode5in the corner portion of the outer side region RO is located on the inner side in relation to the outer peripheral end of the surface electrode5in the straight portion of the outer side region RO based on a position of the outer peripheral end of the terminal well region2in each of the plurality of surface electrodes5electrically connected to each of the terminal well regions2.

An operation of the SBD100of the embodiment 1 is described. When negative voltage is applied to the back surface electrode8based on potential of the surface electrode5, the SBD100enters a state where current flows from the surface electrode5to the back surface electrode8, that is to say, a conduction state (ON state). In contrast, when positive voltage is applied to the back surface electrode8based on the potential of the surface electrode5, the SBD100enters a blocking state (OFF state).

When the SBD100is in the OFF state, large electrical field is applied to a surface of the inner side region RI (active region) in the drift layer1and an area near a pn junction interface between the drift layer1and the terminal well region2. Voltage applied to the back surface electrode8at a time when the electrical field reaches a critical electrical field and avalanche breakdown occurs is defined as maximum voltage (avalanche voltage) of the SBD100. Normally, rated voltage is determined so that the SBD100is used within a voltage range in which the avalanche breakdown does not occur.

In the OFF state in the SBD100, the depletion layer expands in a direction (lower direction) toward the single crystal substrate31and an outer peripheral direction (right direction) of the drift layer1from the surface of the active region in the drift layer1and the pn junction interface between the drift layer1and the terminal well region2. The depletion layer also expands from the pn junction interface between the drift layer1and the terminal well region2into the terminal well region2, and a degree of the expansion significantly depends on the concentration of the terminal well region2. That is to say, when the concentration of the terminal well region2increases, the expansion of the depletion layer is suppressed in the terminal well region2, and a position of an edge of the depletion layer is located near the boundary between the terminal well region2and the drift layer1. The edge of the depletion layer is located in the same position in the straight portion and the corner portion of the terminal region as long as a distance from the region where the surface electrode5and the terminal well region2are connected to each other and the outer peripheral end of the terminal well region2is the same.

FIG.9illustrates the position of the edge of the depletion layer expanding in the direction (lower direction) toward the single crystal substrate31and the outer peripheral direction (right direction) of the drift layer1and the position of the edge of the depletion layer expanding into the terminal well region2in the OFF state in the SBD100by broken lines. That is to say, a region between the two broken lines illustrated inFIG.9is depleted in the OFF state in the SBD100. The position of the edge of the depletion layer can be checked through a technology CAD (TCAD) simulation, for example. In the outer side region RO, a potential difference occurs from an outer peripheral side of the epitaxial layer32toward a center in a depleted region in the epitaxial layer32. A region which is not depleted in the terminal well region2can be considered to have substantial the same potential as the surface electrode5.

Considered herein is a case where the SBD100is in the OFF state under high humidity. A sealing resin provided to cover a semiconductor chip may contain moisture. For example, when the surface protection film6is made up of a resin material having high water absorption properties such as polyimide, there is a possibility that the surface protection film6contains much moisture under high humidity and the moisture reaches the surfaces of the epitaxial layer32and the electrode pad5b. When the surface protection film6is made up of a material such as SiN having high resistance, there is a possibility that a crack occurs easily in the surface protection film6around the end portion of the surface electrode5by a stress generated in the processes, and the surface electrode5is exposed to the moisture through the crack. In such a state, an end edge portion of the drift layer1acts as a positive electrode by voltage applied to the SBD100in the OFF state, and the electrode pad5bacts as a negative electrode. A reduction reaction of oxygen expressed by the following chemical formula (1) and a formation reaction of hydrogen expressed by the following chemical formula (2) occur by the moisture near the electrode pad5bwhich becomes the negative electrode.
O2+2H2O+4e−→4OH−(1)
H2O+e−→OH−+1/2H2(2)

According to these reactions, a concentration of hydroxide ion increases near the electrode pad5b. Hydroxide ion chemically reacts with the electrode pad5b. For example, when the electrode pad5bis made of aluminum, aluminum is changed into aluminum hydroxide by the chemical reaction described above in some cases.

The reaction of aluminum and hydroxide ion is accelerated by field intensity around an area of reaction. A potential gradient occurs in a depleted region in the semiconductor, thus a potential gradient along the front surface S2occurs in a region where the depletion layer is exposed to the surface of the epitaxial substrate30in the SBD100in the embodiment 1 (a region ER illustrated inFIG.9). The potential gradient is taken over by the field insulating film3and the surface protection film6on the front surface S2of the epitaxial layer32, thus electrical field occurs around the end portion of the electrode pad5b. When the field intensity in the end portion of the electrode pad5bis thereby equal to or larger than a predetermined value, a formation reaction of aluminum hydroxide occurs, and the reaction is accelerated in accordance with the increase in the field intensity. The field intensity in the end portion of the electrode pad5bcan be checked through a technology CAD (TCAD) simulation, for example, by setting a shape, dielectric constant, resistivity of each of the surface electrode5, the field insulating film3, and the surface protection film6, for example.

The field intensity in the end portion of the electrode pad5bincreases as the position of the outer peripheral end of the surface electrode5gets closer to the outer periphery based on the position of the outer peripheral end of the terminal well region2. Thus, the generation of aluminum hydroxide is accelerated as the position of the outer peripheral end of the surface electrode5gets closer to the outer periphery based on the position of the outer peripheral end of the terminal well region2.

The field intensity is generally high due to an occurrence of a two-dimensional potential gradient in a corner portion (a curved portion) of the terminal region, thus a deposition of aluminum hydroxide significantly occurs on the surface of the electrode pad5b. When the surface protection film6is pushed up by the deposition of the aluminum hydroxide, the peeling of the surface protection film6occurs at an interface between the electrode pad5band the surface protection film6in some cases.

Particularly when the epitaxial substrate30is made of SiC, a width of the terminal well region2and a width from the terminal well region2to the end edge portion of the drift layer1can be designed to be small by using high insulating breakdown electrical field of SiC. In such a design, a distance from the end edge portion of the drift layer1which becomes the positive electrode in the OFF state to the electrode pad5bwhich becomes the negative electrode decreases. Thus, the field intensity of the terminal region further increases, and the generation of aluminum hydroxide in the end portion of the electrode pad5bis promoted. As a result, the peeling of the surface protection film6from the electrode pad5boccurs more significantly.

The peeling of the surface protection film6extends onto the field insulating film3in some cases. In other words, the peeling of the surface protection film6also occurs at an interface between the field insulating film3and the surface protection film6in some cases. If a cavity is formed on the field insulating film3by this peeling, there is a possibility that moisture enters the cavity and causes an excess leakage current or an aerial discharge occurs in the cavity, thus an element breakdown occurs in the SBD100.

In contrast, in the SBD100in the embodiment 1, the outer peripheral end of the surface electrode5in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the surface electrode5in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region2. Thus, the field intensity in the end portion of the electrode pad5bin the corner portion of the terminal region is smaller than the field intensity of the end potion of the electrode pad5bin the straight portion of the terminal region. Accordingly, the generation of aluminum hydroxide is suppressed in the end portion of the electrode pad5bin the corner portion of the terminal region. As a result, obtained is an effect that increase in a leakage current and an aerial discharge caused by the peeling of the surface protection film6can be avoided.

When the plurality of terminal well regions2separated from each other are provided in a nested form as illustrated inFIG.7, the field intensity of the end portion of the electrode pad5bcan be further made small, and an effect of suppressing the generation of aluminum hydroxide is further increased.

The effect of suppressing the generation of aluminum hydroxide in the corner portion of the terminal region is also obtained in the plurality of surface electrodes5included in the SBD101in the modification example of the embodiment 1 (FIG.8). That is to say, in each of the plurality of surface electrodes5inFIG.8, the outer peripheral end of the surface electrode5in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the surface electrode5in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region2, thus the field intensity in the end portion of each of the plurality of electrode pads5bcan be made small in the corner portion. Thus, the generation of aluminum hydroxide in the end portion of the electrode pad5bin the corner portion can be suppressed, and the increase in the leakage current and the aerial discharge caused by the peeling of the surface protection film6can be avoided.

A method of manufacturing the SBD100according to the embodiment 1 is described.

Firstly, a low-resistance single crystal substrate31including an n-type impurity at a relatively high concentration (n+) is prepared. In the present embodiment, the single crystal substrate31is an SiC substrate having a polytype of 4H, and has an off angle of four degrees or eight degrees.

Subsequently, SiC is epitaxially grown on the single crystal substrate31to form the n-type epitaxial layer32having an impurity concentration equal to or larger than 1×1014/cm3and equal to or smaller than 1×1017/cm3on the single crystal substrate31. Accordingly, the epitaxial substrate30made up of the single crystal substrate31and the epitaxial layer32is obtained.

Next, a resist mask having a pattern in which a formation region of the terminal well region2is opened is formed on the epitaxial layer32by a photolithography process. Then, a p-type impurity (acceptor) such as Al or boron (B) is ion-implanted into the epitaxial layer32using the resist mask as an implantation mask to form the p-type terminal well region2on a surface layer portion of the epitaxial layer32. A dose amount of the terminal well region2is preferably equal to or larger than 0.5×1013/cm2and equal to or smaller than 5×1013/cm2, and can be set to 1.0×1013/cm2, for example.

When the p-type impurity is Al, implantation energy of ion implantation is equal to or larger than 100 keV and equal to or smaller than 700 keV, for example. In this case, the impurity concentration of the terminal well region2converted from the dose amount [cm−2] described above is equal to or larger than 1×1017/cm3and equal to or smaller than 1×1019/cm3.

When the plurality of terminal well regions2are formed as illustrated inFIG.7orFIG.8, it is also applicable to form a plurality of opening in a nested form in the resist mask as the implantation mask and simultaneously form the plurality of terminal well regions2by one ion implantation. Alternatively, it is also applicable that the formation of the implantation mask (patterning of the resist mask) and the ion implantation are repeated several times to form the plurality of terminal well regions2.

After forming the terminal well region2, annealing is performed at a temperature equal to or larger than 1300° C. and equal to or smaller than 1900° C. for thirty seconds to one hour in an inactive gas atmosphere such as argon (Ar) gas using a thermal processing device. The impurity added to the epitaxial layer32by the ion implantation is activated by the annealing.

Next, an SiO2film having a thickness of 1 μm is formed on the front surface S2of the epitaxial substrate30by a CVD method, for example. Then, the SiO2film is patterned by a photolithography process and an etching process to form the field insulating film3. At this time, the field insulating film3is patterned to have a shape of covering part of the terminal well region2and going beyond an end portion of the terminal well region2to extend to an outer peripheral side of the terminal well region2.

Subsequently, a material layer of the Schottky electrode5aand a material layer of the electrode pad5bare stacked in this order on the epitaxial layer32and the field insulating film3by a sputtering method, for example. A Ti film having a thickness of 100 nm, for example, can be used as the material layer of the Schottky electrode5a, and an Al film having a thickness of 3 μm, for example, can be used as the material layer of the electrode pad5b.

Subsequently, a resist mask having a pattern of the surface electrode5is formed on the material layer of the electrode pad5bby a photolithography process. Then, the material layer of the electrode pad5band the material layer of the Schottky electrode5aare patterned using the resist mask as an etching mask to obtain the surface electrode5made up of the Schottky electrode5aand the electrode pad5b. At this time, the surface electrode5is patterned so that the outer peripheral end of the surface electrode5in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the surface electrode5in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region2.

When the plurality of surface electrodes5are formed as illustrated inFIG.8, the material layer of the Schottky electrode5aand the material layer of the electrode pad5bare patterned to be divided into a plurality of elements.

Dry etching or wet etching can be used for etching of the material layer of the electrode pad5band the material layer of the Schottky electrode5a. In the case of the wet etching, an hydrofluoric acid (HF) or phosphoric acid system etching solution can be used as an etching solution.

The patterning of the Schottky electrode5aand the patterning of the electrode pad5bmay be performed separately. In this case, a position of the end edge portion of the Schottky electrode5aand a position of the end edge portion of the electrode pad5bmay be displaced from each other. For example, it is also applicable that the end edge portion of the electrode pad5bprotrudes from the end edge portion of the Schottky electrode5aand the electrode pad5bcompletely covers the Schottky electrode5a. Alternatively, it is also applicable that the end edge portion of the Schottky electrode5aprotrudes from the end edge portion of the electrode pad5b, and part of the Schottky electrode5ais not covered by the electrode pad5b.

Next, a resin layer which is the material layer of the surface protection film6is formed on the front surface S2of the epitaxial substrate30to cover the field insulating film3and the surface electrode5. The resin layer can be formed by applying photoactive polyimide, for example. Subsequently, the resin layer is patterned by a photolithography process to form the surface protection film6. At this time, the surface protection film6on a center portion of the surface electrode5which becomes an external connection terminal is removed. The surface protection film6is pattered to cover the end edge portion of the surface electrode5and at least part of the outer side region RO in the outer side region RO.

Finally, the back surface electrode8is formed on the back surface S1of the epitaxial substrate30by a sputtering method, for example, to obtain the SBD100illustrated inFIG.1.

The formation of the back surface electrode8may be performed before or after a process of forming the material layer of the Schottky electrode5aand the material layer of the electrode pad5b. Metal including one or some of Ti, Ni, Al, Cu, and Au, for example, can be used as a material of the back surface electrode8. A thickness of the back surface electrode8is preferably equal to or larger than 50 nm and equal to or smaller than 2 μm. A Ti/Au double-layered film having a thickness of 1 μm can be used as the back surface electrode8, for example.

As described above, according to the SBD100of the embodiment 1 and the SBD101of the modification example of the embodiment 1, the generation of aluminum hydroxide in the end portion of the electrode pad5bin the corner portion of the terminal region can be suppressed, and the peeling of the surface protection film6is thereby avoided. Thus, the increase in the leakage current and the aerial discharge caused by the peeling of the surface protection film6can be avoided, and insulation reliability of the SBD can be increased.

FIG.10is a partial cross-sectional view illustrating a configuration of a MOSFET200which is a semiconductor device according to an embodiment 2 of the present invention.FIG.11is a plan view of the MOSFET200, and a cross-sectional view along a B-B line inFIG.11corresponds toFIG.10.FIG.12is a cross-sectional view illustrating a configuration of a unit cell UC which is a minimum unit structure of a MOSFET in the inner side region RI which is the active region. The plurality of unit cells UC, each of which is illustrated inFIG.12, are arranged in the inner side region RI in the MOSFET200(the unit cell UC in an outermost periphery is illustrated in a left end portion inFIG.10). InFIGS.10to12, the same reference numerals are assigned to the elements having the same function as the constituent elements of the SBD100according to the embodiment 1 illustrated inFIG.1andFIG.2, thus the description overlapping with the embodiment 1 is omitted.

As illustrated inFIG.10, the MOSFET200is formed using the epitaxial substrate30made up of the single crystal substrate31and the epitaxial layer32formed on the single crystal substrate31. The single crystal substrate31is a semiconductor substrate made up of n-type (first conductivity type) silicon carbide (SiC), and the epitaxial layer32is a semiconductor layer made up of SiC epitaxially grown on the single crystal substrate31. That is to say, the MOSFET200is SiC-MOSFET. In the present embodiment, the epitaxial substrate30having 4H polytype is used.

A p-type (second conductivity type) element well region9is selectively formed on a surface layer portion on the front side of the epitaxial layer32in the active region. Each of an n-type source region11and a p-type contact region19having a higher impurity concentration than the element well region9is selectively formed on a surface layer portion of the element well region9.

A p-type terminal well region20is selectively formed on the surface layer portion on the front side of the epitaxial layer32in the terminal region to surround the active region. The terminal well region20includes a boundary region21having contact with a boundary between the inner side region RI and the outer side region RO and an extension region22extending outside from the boundary region21to surround the boundary region21and having a lower impurity concentration than the boundary region21. The boundary region21further includes a low concentration part21ahaving a relatively low impurity concentration and a high concentration part21bformed on a surface layer portion of the low concentration part21aand having a relatively high impurity concentration. Herein, a type of the high concentration part21bis not limited to a p type, however, an n type is also applicable.

The n-type region of the epitaxial layer32except for the impurity regions described above (the element well region9, the source region11, the contact region19, and the terminal well region20) constitutes the drift layer1in which current flows by drift. An impurity concentration of the drift layer1is lower than that of the single crystal substrate31. Thus, the single crystal substrate31has lower resistivity than the drift layer1. Herein, the impurity concentration of the drift layer1is equal to or larger than 1×1014/cm3and equal to or smaller than 1×1017/cm3.

As shown by dotted lines inFIG.11, the terminal well region20is a frame-like (ring-like) region surrounding the active region in a plan view, and functions as a so-called guard ring. As illustrated inFIG.10, assuming that an end portion of an inner side (inner peripheral side) of the terminal well region20is a boundary, an inner side of the boundary is defined as the inner side region RI which is the active region and an outer side thereof is defined as the outer side region RO which is the terminal region. The outer side region RO is a frame-like region surrounding the inner side region RI in a plan view, and includes a straight portion which is a straight region along each side of a semiconductor chip and a corner portion which is a curved region between the straight portions adjacent to each other.

A gate insulating film12is formed on the front surface S2of the epitaxial substrate30in the active region to extend on the source region11, the element well region9, and the drift layer1, and the gate electrode13is formed thereon. A surface layer portion of the element well region9covered by the gate insulating film12and the gate electrode13, that is to say, a portion between the source region11and the drift layer1in the element well region9constitutes a channel region in which an inversion channel is formed when the MOSFET200enters an ON state.

The gate electrode13is covered by an interlayer insulating film14in the active region, and a source electrode51is formed on the interlayer insulating film14. Thus, the gate insulating film12and the gate electrode13are electrically insulated from each other by the interlayer insulating film14.

The source electrode51is connected to the source region11and the contact region19through a contact hole formed in the interlayer insulating film14. The source electrode51and the contact region19form ohmic contact. The back surface electrode8functioning as a drain electrode is provided on the back surface S1of the epitaxial substrate30.

As illustrated inFIG.10, the gate insulating film12, the gate electrode13, the interlayer insulating film14, and the source electrode51partially go beyond the boundary between the inner side region RI and the outer side region RO and extend to the outer side region RO. The source electrode51drawn to the outer side region RO is connected to the high concentration part21bof the terminal well region20through a contact hole formed in the interlayer insulating film14to have ohmic contact or Schottky contact with the high concentration part21b. The gate electrode13drawn to the outer side region RO is disposed on the high concentration part21bof the terminal well region20via the gate insulating film12, and extends to have a frame-like shape in a plan view in the manner similar to the high concentration part21b.

The field insulating film3, a gate wiring electrode52, and the surface protection film6are provided on the front surface S2of the epitaxial substrate30in the terminal region. The illustration of the field insulating film3and the surface protection film6is omitted in a plan view inFIG.11. The position of the end portion of the surface protection film6, that is to say, the outline of the surface protection film6is shown by a broken line.

The field insulating film3covers part of the boundary region21in the terminal well region20and the whole extension region22, and goes beyond an outer peripheral end of the terminal well region20to extend to an outer side of the terminal well region20. The field insulating film3is not provided in the inner side region RI. In other words, the field insulating film3has an opening having the inner side region RI.

The gate wiring electrode52is formed on the interlayer insulating film14covering the gate electrode13drawn to the outer side region RO, and is connected to the gate electrode13through a contact hole formed in the interlayer insulating film14. The gate wiring electrode52functions as an electrode receiving a gate signal (control signal) for controlling an electrical path between the source electrode51and the back surface electrode8. The gate wiring electrode52is separated from the source electrode51, and is also electrically insulated from the source electrode51.

The gate wiring electrode52extends to have a frame-like shape in a plan view in the manner similar to the gate electrode13drawn to the outer side region RO. In the present embodiment, the gate wiring electrode52is made up of a gate wiring52wprovided to surround the source electrode51and a gate pad52pprovided to enter a concave portion provided in one side of the rectangular source electrode51as illustrated inFIG.11, and the gate wiring52wand the gate pad52pare connected to each other. The gate wiring electrode52illustrated inFIG.10corresponds to the gate wiring52winFIG.11. The gate pad52pfunctions as an external terminal for inputting the gate signal. InFIG.11, the gate pad52pis provided in the straight portion of the terminal region, but may also be provided in the corner portion.

In the present embodiment, a surface electrode50includes the source electrode51and the gate wiring electrode52. The surface electrode50is provided to have contact with at least part of the front surface S2of the inner side region RI in the epitaxial substrate30. The surface electrode50is formed over the whole inner side region RI, and partially goes beyond the boundary between the inner side region RI and the outer side region RO to extend to the outer side region RO. The surface electrode50is provided so that the whole surface electrode50is located on the interlayer insulating film14.

InFIG.10, an inner peripheral end of the field insulating film3has contact with the end portion of the interlayer insulating film14, and the gate electrode13and the surface electrode50are formed on an inner side in relation to the inner peripheral end of the field insulating film3. However, the interlayer insulating film14, the gate electrode13, and the surface electrode50may be formed to be located on the field insulating film3. In this case, the source electrode51is connected to the high concentration part21bof the terminal well region20through a contact hole passing through both the interlayer insulating film14and the field insulating film3.

The surface protection film6covers the source electrode51and the gate wiring electrode52on the end edge portion of the surface electrode50and at least part of the outer side region RO in the epitaxial substrate30. The surface protection film6has an opening on each of a center portion of the source electrode51and a center portion of the gate pad52pas illustrated inFIG.11. Accordingly, each of the source electrode51and the gate pad52pcan function as an external terminal.

In the MOSFET200of the embodiment 2, the outer peripheral end of the surface electrode50in the corner portion of the outer side region RO is located on the inner side in relation to the outer peripheral end of the surface electrode50in the straight portion of the outer side region RO based on a position of the outer peripheral end of the terminal well region20. That is to say, when a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the surface electrode50, that is a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the gate wiring52wis L, in a case where the outer peripheral end of the gate wiring52wis located on an inner side in relation to the outer peripheral end of the terminal well region20as illustrated inFIG.10, a distance L2in the corner portion of the outer side region RO is larger than a distance L1in the straight portion of the outer side region RO as illustrated inFIG.11. That is to say, a relationship of L2>L1is established.

Although the illustration is omitted, in a case where the outer peripheral end of the gate wiring52wis located on an inner side in relation to the outer peripheral end of the terminal well region20, when a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the surface electrode50, that is a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the gate wiring52wis L, a distance L2in the corner portion of the outer side region RO is smaller than a distance L1in the straight portion of the outer side region RO. That is to say, a relationship of L1>L2is established.

Also in the embodiment 2, the plurality of terminal well regions20disposed separately from each other in a nested form may be provided as with the terminal well region2illustrated inFIG.7andFIG.8. The surface electrode50is electrically connected to at least one of the plurality of terminal well regions20.

In the present embodiment, a material of the epitaxial substrate30is SiC. However, it is not limited to SiC, but Si or the other wideband gap semiconductor such as gallium nitride (GaN) is also applicable, for example.

The semiconductor device according to the present embodiment may be a transistor other than a MOSFET, thus may be a junction FET (JFET) or an insulated gate bipolar transistor (IGBT), for example. Furthermore, a planar type transistor is exemplified in the present embodiment, however, a trench type transistor is also applicable.

Modification Example

FIG.13is a plan view illustrating a configuration of a MOSFET201according to a modification example of the embodiment 2, and is a drawing corresponding toFIG.11. In the MOSFET201inFIG.13, a concave portion provided in one side of the rectangular source electrode51extends to enter deeply inside the source electrode51, and the gate wiring electrode52further extends to enter the concave portion. That is to say, in the MOSFET200inFIG.11, only the gate pad52penters the concave portion provided in one side of the source electrode51, and the gate wiring52wis provided to surround the source electrode51, however, in the MOSFET201inFIG.13, the elongated gate wiring52wenters the concave portion of the source electrode51, and the gate pad52pis provided in an entrance portion of the concave portion.

Also in the MOSFET201, the outer peripheral end of the surface electrode50in the corner portion of the outer side region RO is located on the inner side in relation to the outer peripheral end of the surface electrode50in the straight portion of the outer side region RO based on a position of the outer peripheral end of the terminal well region20. That is to say, when a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the surface electrode50, that is a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the source electrode51is L, in a case where the outer peripheral end of the source electrode51is located on an inner side in relation to the outer peripheral end of the terminal well region20, a distance L2in the corner portion of the outer side region RO is larger than a distance L1in the straight portion of the outer side region RO as illustrated inFIG.13. That is to say, a relationship of L2>L1is established.

Although the illustration is omitted, in a case where the outer peripheral end of the source electrode51is located on an inner side in relation to the outer peripheral end of the terminal well region20, when a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the surface electrode50, that is a distance from the outer peripheral end of the terminal well region20to the outer peripheral end of the source electrode51is L, a distance L2in the corner portion of the outer side region RO is smaller than a distance L1in the straight portion of the outer side region RO. That is to say, a relationship of L1>L2is established.

An operation of the MOSFET200of the embodiment 2 illustrated inFIG.10is described with two states.

A first state is a state where positive voltage equal to or larger than a threshold value is applied to the gate electrode13, and this state is referred to as “ON state”. When the MOSFET200is in the ON state, an inversion channel is formed in a channel region. The inversion channel functions as a path for electrons as carriers flowing between the source region11and the drift layer1. In the ON state, when high voltage is applied to the back surface electrode8based on potential of the source electrode51, current passing through the single crystal substrate31and the drift layer1flows. At this time, the voltage between the source electrode51and the back surface electrode8is referred to as “ON voltage”, and current flowing between the source electrode51and the back surface electrode8is referred to as “ON current”. The ON current flows only in the active region including the channel, and does not flow in the terminal region.

A second state is a state where voltage smaller than a threshold value is applied to the gate electrode13, and this state is referred to as “OFF state”. When the MOSFET200is in the OFF state, an inversion channel is not formed in a channel region, thus the ON current does not flow. Thus, when high voltage is applied between the source electrode51and the back surface electrode8, this high voltage is maintained. At this time, the voltage between the gate electrode13and the source electrode51is significantly small compared with the voltage between the source electrode51and the back surface electrode8, thus the high voltage is also applied between the gate electrode13and the back surface electrode8.

In the OFF state, also in the terminal region, the high voltage is applied between the gate wiring electrode52and the back surface electrode8and between the gate electrode13and the back surface electrode8. An electrical contact between the boundary region21in the terminal well region20and the source electrode51is formed in the terminal region as with a case where an electrical contact between the element well region9and the source electrode51is formed in the active region, thus avoided is that high electrical field is applied to the gate insulating film12and the interlayer insulating film14.

The terminal region in the MOSFET200functions in the manner similar to the OFF state of the SBD100described in the embodiment 1. That is to say, the high electrical field is applied near a pn junction interface between the drift layer1and the terminal well region20, and when voltage exceeding critical electrical field is applied to the back surface electrode8, avalanche breakdown occurs. Normally, rated voltage is determined so that the MOSFET200is used within a range in which the avalanche breakdown does not occur.

In the OFF state, the depletion layer expands in a direction (lower direction) toward the single crystal substrate31and an outer peripheral direction (right direction) of the drift layer1from the pn junction interface between the drift layer1and the element well region9and between the drift layer1and the terminal well region20.

Considered herein is a case where the MOSFET200is in the OFF state under high humidity. A sealing resin provided to cover a semiconductor chip may contain moisture. For example, when the surface protection film6is made up of a resin material having high water absorption properties such as polyimide, there is a possibility that the surface protection film6contains much moisture under high humidity and the moisture reaches the surfaces of the field insulating film3, the interlayer insulating film14, and the surface electrode50. When the surface protection film6is made up of a material such as SiN having high resistance, there is a possibility that a crack occurs easily in the surface protection film6around the end portion of the surface electrode5by a stress generated in the processes, and the surface electrode5is exposed to the moisture through the crack. In such a state, the end edge portion of the drift layer1acts as a positive electrode by voltage applied to the MOSFET200in the OFF state, and the surface electrode50acts as a negative electrode. A reduction reaction of oxygen expressed by the chemical formula (1) and a formation reaction of hydrogen expressed by the chemical formula (2) described in the embodiment 1 occur near the surface electrode50which becomes the negative electrode.

Accordingly, a concentration of hydroxide ion increases near the surface electrode50(when the negative voltage is applied to the gate wiring electrode52, the concentration of hydroxide ion further increases around the gate wiring electrode52). Hydroxide ion chemically reacts with the surface electrode50, thus an insulating material is deposited on an upper surface and a lateral surface of the surface electrode50in the outer end edge portion of the surface electrode50(a right end inFIG.10).

The field intensity is generally high due to the occurrence of the two-dimensional potential gradient in the corner portion (the curved portion) of the terminal region, thus a deposition of the insulating material significantly occurs on the surface of the surface electrode50. When the surface protection film6is pushed up by the deposition of the aluminum hydroxide, the peeling of the surface protection film6may occur at an interface between the surface electrode50and the surface protection film6in some cases.

The peeling of the surface protection film6extends on the interlayer insulating film14and the field insulating film3in some cases. In other words, the peeling of the surface protection film6also occurs at an interface between the interlayer insulating film14and the surface protection film6and between the field insulating film3and the surface protection film6in some cases. If a cavity is formed on the interlayer insulating film14and the field insulating film3by this peeling, there is a possibility that moisture enters the cavity and causes an excess leakage current or an aerial discharge occurs in the cavity, thus an element breakdown occurs in the MOSFET200.

If a cavity is formed between the source electrode51and the gate wiring electrode52by the peeling of the surface protection film6, there is a possibility that moisture enters the cavity and causes an excess leakage current flowing between the source and the gate.

Particularly when the epitaxial substrate30is made of SiC, a width of the terminal well region2and a width from the terminal well region20to the end edge portion of the drift layer1can be designed to be small by using high insulating breakdown electrical field of SiC. In such a design, a distance from the end edge portion of the drift layer1which becomes the positive electrode in the OFF state to the surface electrode50which becomes the negative electrode decreases. Thus, the field intensity of the terminal region further increases, and the generation of aluminum hydroxide in the end portion of the surface electrode50is promoted. As a result, the peeling of the surface protection film6from the surface electrode50occurs more significantly.

In contrast, in the MOSFET200in the embodiment 2, the outer peripheral end of the surface electrode50in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the surface electrode50in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region20. Thus, the field intensity in the end portion of the surface electrode50in the corner portion of the terminal region is smaller than the field intensity of the end potion of the surface electrode50in the straight portion of the terminal region. Accordingly, the generation of aluminum hydroxide is suppressed in the end portion of the surface electrode50in the corner portion of the terminal region. As a result, obtained is an effect that increase in a leakage current and the aerial discharge caused by the peeling of the surface protection film6can be avoided.

The effect of suppressing the generation of aluminum hydroxide in the corner portion of the terminal region is also obtained in the surface electrodes50included in the MOSFET201in the modification example of the embodiment 2 (FIG.13). That is to say, the outer peripheral end of the source electrode51in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the source electrode51in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region20, thus the field intensity in the end portion of the source electrode51in the corner portion of the terminal region can be made smaller than the field intensity in the end portion of the source electrode51in the straight portion of the terminal region. Thus, the generation of aluminum hydroxide in the end portion of the source electrode51in the corner portion can be suppressed, and the increase in the leakage current and the aerial discharge caused by the peeling of the surface protection film6can be avoided.

A method of manufacturing the MOSFET200according to the embodiment 2 is described next.

Firstly, a low-resistance single crystal substrate31including an n-type impurity at a relatively high concentration (n+) is prepared. In the present embodiment, the single crystal substrate31is an SiC substrate having a polytype of 4H, and has an off angle of four degrees or eight degrees.

Subsequently, SiC is epitaxially grown on the single crystal substrate31to form the n-type epitaxial layer32having an impurity concentration equal to or larger than 1×1014/cm3and equal to or smaller than 1×1017/cm3on the single crystal substrate31. Accordingly, the epitaxial substrate30made up of the single crystal substrate31and the epitaxial layer32is obtained.

Next, a photolithography process of forming a resist mask and an ion implantation process of performing ion implantation using the resist mask as an implantation mask to form an impurity region in the surface layer portion of the epitaxial layer32are repeated, thus the terminal well region20, the element well region9, the contact region19, and the source region11are formed in the epitaxial layer32.

In the ion implantation, nitrogen (N), for example, is used as the n-type impurity, and Al or B, for example, is used as the p-type impurity. The element well region9and the low concentration region21ain the terminal well region20can be collectively formed in the same ion implantation process. Both the contact region19and the high concentration region21bin the terminal well region20can be collectively formed in the same ion implantation process.

The impurity concentration of each of the element well region9and the low concentration region21ain the terminal well region20is preferably equal to or larger than 1.0×1018/cm3and equal to or smaller than 1.0×1020/cm3. The impurity concentration of the source region11is preferably equal to or larger than 1.0×1019/cm3and equal to or smaller than 1.0×1021/cm3in a higher range than that of the element well region9. A dose amount of the contact region19and the extension region22in the terminal well region20is preferably equal to or larger than 0.5×1013/cm2and equal to or smaller than 5×1013/cm2, and is 1.0×1013/cm2, for example.

When the impurity is Al, implantation energy of ion implantation is equal to or larger than 100 keV and equal to or smaller than 700 keV, for example. In this case, the impurity concentration of the extension region22converted from the dose amount [cm−2] described above is equal to or larger than 1×1017/cm3and equal to or smaller than 1×1019/cm3. When the impurity is N, implantation energy of ion implantation is equal to or larger than 20 keV and equal to or smaller than 300 keV, for example.

Subsequently, annealing is performed at a temperature equal or larger than 1500° C. using a thermal processing device. Accordingly, the impurity added by the ion implantation is activated.

Next, an SiO2film having a thickness equal to or larger than 0.5 μm and equal to or smaller than 2 μm is formed on the front surface S2of the epitaxial substrate30by a CVD method, for example. Then, the SiO2film is patterned by a photolithography process and an etching process to form the field insulating film3. At this time, the field insulating film3is patterned to have a shape of covering part of the terminal well region20and going beyond the end portion of the terminal well region20to extend to the outer peripheral side of the terminal well region2.

Subsequently, the surface of the epitaxial layer32which is not covered by the field insulating film3is thermally oxidized to form a SiO2film as the gate insulating film12. Then, a polycrystal silicon film having conductivity is formed on the gate insulating film12by a decompression CVD method, and the polycrystal silicon film is patterned by a photolithography process and an etching process to form the gate electrode13. At this time, the gate electrode13may be formed to be located on the field insulating film3.

Subsequently, an SiO2film as the interlayer insulating film14is formed by a CVD method. Then, contact holes passing through the gate insulating film12and the interlayer insulating film14to reach each of the contact region19, the source region11, and the high concentration part21bof the terminal region are formed by a photolithography process and an etching process. In this process, the contact hole passing through the interlayer insulating film14to reach the gate electrode13is formed in the terminal region, and the interlayer insulating film14located on the field insulating film3and on the end edge portion of the epitaxial layer32is removed.

Next, a material layer of the surface electrode50is formed on the front surface S2of the epitaxial substrate30by a sputtering method or a deposition method, for example. A material layer of the back surface electrode8is provided on the back surface S1of the epitaxial substrate30by a method similar thereto.

Metal including one or some of Ti, Ni, Al, Cu, and Au or Al alloy such as Al—Si, for example, can be used as a material of the surface electrode50. Metal including one or some of Ti, Ni, Al, Cu, and Au, for example, is used as the material of the back surface electrode8. A silicide film may be formed in advance by thermal processing on a portion having contact with the surface electrode50or the back surface electrode8in the epitaxial substrate30. The back surface electrode8may be formed at the end of all of the processes.

Next, the surface electrode50is patterned by a photolithography process and an etching process to separate the surface electrode50into the source electrode51and the gate wiring electrode52. At this time, the surface electrode50is patterned so that the outer peripheral end of the surface electrode50in the corner portion of the terminal region is located on the inner side in relation to the outer peripheral end of the surface electrode50in the straight portion of the terminal region based on the position of the outer peripheral end of the terminal well region20.

Finally, the surface protection film6is formed to cover the end edge portion of the surface electrode50and at least part of the outer side region RO in the epitaxial substrate30to obtain the MOSFET200illustrated inFIG.10. The surface protection film6is formed into a desired shape by applying and exposing photoactive polyimide, for example.

As described above, according to the MOSFET200of the embodiment 2 and the MOSFET201of the modification example of the embodiment 2, the generation of aluminum hydroxide in the end portion of the surface electrode50in the corner portion of the terminal region can be suppressed, and the peeling of the surface protection film6is thereby avoided. Thus, the increase in the leakage current and the aerial discharge caused by the peeling of the surface protection film6can be avoided, and insulation reliability of the MOSFET can be increased.

The semiconductor device according to the embodiments 1 and 2 described above is applied to a power conversion device in the present embodiment. Described hereinafter is a case where the semiconductor device according to the embodiments 1 and 2 is applied to a three-phase inverter as an embodiment 3.

FIG.14is a block diagram schematically illustrating a configuration of a power conversion system to which a power conversion device2000according to the present embodiment is applied.

A power conversion system illustrated inFIG.14includes a power source1000, the power conversion device2000, and a load3000. The power source1000is a direct current power source, and supplies a direct current power to the power conversion device2000. The power source1000can be made up of various components, thus can be made up of a direct current system, a solar battery, or a storage battery, for example, and may also be made up of a rectification circuit connected to an alternating current system or an AC/DC converter. The power source1000may also be made up of a DC/DC converter converting a direct current power being output from a direct current system into a predetermined power.

The power conversion device2000is a three-phase inverter connected between the power source1000and the load3000, converts a direct current power supplied from the power source1000into an alternating current power, and supplies the alternating current power to the load3000. As illustrated inFIG.14, the power conversion device2000includes a main conversion circuit2001converting a direct current power into an alternating current power and outputting the alternating current power, a drive circuit2002outputting a drive signal for driving each switching element of the main conversion circuit2001, and a control circuit2003outputting a control signal for controlling the drive circuit2002to the drive circuit2002.

The load3000is a three-phase electrical motor driven by the alternating current power supplied from the power conversion device2000. The load3000is not for a specific purpose of usage, but is an electrical motor mounted on various types of electrical devices, thus is used as an electrical motor for a hybrid automobile, an electrical automobile, a railroad vehicle, an elevator, or an air-conditioning machine, for example.

Details of the power conversion device200are described hereinafter. The main conversion circuit2001includes a switching element and a reflux diode (not shown), and when the switching element is switched, the main conversion circuit2001converts the direct current power supplied from the power source1000into the alternating current power, and supplies the alternating current power to the load3000. Examples of a specific circuit configuration of the main conversion circuit2001include various configurations, however, the main conversion circuit2001according to the present embodiment is a three-phase full-bridge circuit with two levels, and can be made up of six switching elements and six reflux diodes antiparallelly connected to each switching element. The semiconductor device according to any one of the embodiments 1 and 2 described above is applied to at least one of each switching element and each reflux diode of the main conversion circuit2001. The six switching elements are connected two by two in series to constitute upper and lower arms, and each pair of the upper and lower arms constitutes each phase (U phase, V phase, and W phase) of a full-bridge circuit. Output terminals of the pair of the upper and lower arms, that is to say, three output terminals of the main conversion circuit2001are connected to the load3000.

The drive circuit2002generates a drive signal for driving a switching element of the main conversion circuit2001, and supplies the drive signal to a control electrode of the switching element of the main conversion circuit2001. Specifically, the drive circuit2002outputs a drive signal for making the switching element enter an ON state and a drive signal for making the switching element enter an OFF state to a control electrode of each switching element in accordance with a control signal from the control circuit2003describe hereinafter. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) larger than a threshold voltage of the switching element, and when the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) smaller than the threshold voltage of the switching element.

The control circuit2003controls the switching element of the main conversion circuit2001so that a desired electrical power is supplied to the load3000. Specifically, the control circuit2003calculates a time (on time) at which each switching element of the main conversion circuit2001should enter the ON state based on the electrical power to be supplied to the load3000. For example, the control circuit2003can control the main conversion circuit2001by pulse width modulation (PWM) control modulating the on time of the switching element in accordance with the voltage to be output. Then, the control circuit2003outputs to a control command (control signal) to the drive circuit2002so that the ON signal is output to the switching element which should enter the ON state and the OFF signal is output to the switching element which should enter the OFF state at each point of time. The drive circuit2002outputs the ON signal or the OFF signal as the drive signal to the control electrode of each switching element in accordance with the control signal.

The semiconductor device according to the embodiment 1 can be applied as a reflux diode of the main conversion circuit2001in the power conversion device according to the present embodiment. The semiconductor device according to the embodiment 2 can be applied as a switching element of the main conversion circuit2001in the power conversion device according to the present embodiment. When the semiconductor device according to the embodiment 1 and the embodiment 2 is applied to the power conversion device2000in this manner, the semiconductor device is generally embedded in gel or resin in use, however, these materials cannot completely block moisture, thus the insulation protection of the semiconductor device is maintained by the configuration described in the embodiment 1 and he embodiment 2. The reliability can be thereby increased.

Described in the above present embodiment is the example of applying the semiconductor device according to the embodiments 1 and 2 to the three-phase inverter with two levels. However, the semiconductor device according to the embodiments 1 and 2 is not limited thereto, but can be applied to various power conversion devices. Described in the present embodiment is the power conversion device with two levels, but a power conversion device with three levels or a multilevel power conversion device may also be applied. When an electrical power is supplied to a single phase load, the semiconductor device according to the embodiments 1 and 2 may be applied to a single-phase inverter. When the electrical power is supplied to a direct current load, for example, the semiconductor device according to the embodiments 1 and 2 can be applied to a DC/DC converter or an AC/DC converter.

The power conversion device applying the semiconductor device according to the embodiments 1 and 2 can be used not only in the case where the load is the electrical motor but can be used as a power source device of an electrical discharge machine, a laser beam machine, an induction heat cooking machine, or a wireless chagrining system, and further can also be used as a power conditioner of a solar power system or an electricity storage system, for example.

According to the present invention, each embodiment can be arbitrarily combined, or each embodiment can be appropriately varied or omitted within the scope of the invention.

Although the present invention is described in detail, the foregoing description is in all aspects illustrative and does not restrict the invention. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention. For example, cases where optional constituent elements are to be modified, added, or omitted, further, at least one of the constituent elements of at least one of the embodiments is extracted and then combined with constituent elements of the other embodiment, are involved.

The “one” constituent element described in each embodiment described above may be “one or more” constituent elements so far as consistent with the embodiments. Further, constituent elements constituting the invention are conceptual units. Thus, one constituent element may include multiple structures, and one constituent element may correspond to part of some structure. The constituent element of the present invention includes a structure having a different configuration or a different shape as long as the structure of the different configuration or the different shape achieves the same function.

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