Display substrate, manufacturing method, display motherboard, and display device

The present disclosure provides a display substrate, including an array substrate, a color filter substrate, and a liquid crystal layer and a sealant arranged therebetween. A sealing cavity for receiving the liquid crystal layer is defined by the sealant, the array substrate and the color filter substrate. The display substrate is provided with a bonding side surface bonded to a chip on film, the sealant at least includes a first portion including a first side surface and a second side surface flush with the bonding side surface. The array substrate includes a display region and a non-display region surrounding the display region. A bonding pin is provided in the non-display region, extends to a side surface of the display substrate, and is exposed to the outside. The present disclosure further provides a method for manufacturing the display substrate, a display motherboard, and a display device.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a U.S. National Phase of International Application No. PCT/CN2021/090942 entitled “DISPLAY SUBSTRATE, MANUFACTURING METHOD, DISPLAY MOTHERBOARD, AND DISPLAY DEVICE,” and filed on Apr. 29, 2021. The entire contents of the above-listed application are hereby incorporated by reference for all purposes.

TECHNICAL FIELD

The present disclosure relates to the manufacture of a liquid crystal product, in particular to a display substrate, a manufacturing method thereof, a display motherboard and a display device.

BACKGROUND

Spliced screen products are a popular segment in the display industry in recent years. Display panels each with a narrow bezel are spliced to obtain an oversized display panel, but an image is displayed invalidly at a joint between two display panels, so an overall display effect is adversely affected. In order to achieve an excellent display effect, the bezel of the display panel becomes narrower and narrower. In the related art, the display panels are bonded at front faces, and the bezel has a width of about 1 mm-2 mm, which has already reached a process limit. In this case, a side bonding process has been proposed, so as to reduce a size of the bezel. In the side bonding technology, at first a glass side surface needs to be vertically ground first. At this time, a metal lead may be damaged, the stability of a contact resistance of the metal lead may decrease, and defects may be easily caused due to a change in external temperature and humidity.

SUMMARY

An object of the present disclosure is to provide a display substrate, a manufacturing method thereof, a display motherboard and a display device, so as to solve the problem in the side bonding technology where the metal lead on the display substrate is curled and damaged when a side surface of the display substrate is ground.

In one aspect, the present disclosure provides in some embodiments a display substrate, including an array substrate and a color filter substrate arranged opposite to each other. A liquid crystal layer and a sealant are arranged between the array substrate and the color filter substrate, and a sealing cavity for receiving the liquid crystal layer is defined by the sealant, the array substrate and the color filter substrate. The display substrate is provided with a bonding side surface bonded to a chip on film, the sealant at least includes a first portion close to the bonding side surface, the first portion includes a first side surface in contact with the liquid crystal layer and a second side surface arranged opposite to the first side surface, and the second side surface is flush with the bonding side surface of the display substrate. The array substrate includes a display region and a non-display region surrounding the display region. A bonding pin is provided in the non-display region, extends to a side surface of the display substrate, and is exposed to the outside.

In a possible embodiment of the present disclosure, the sealant includes a first sub-sealant surrounding the liquid crystal layer and at least one second sub-sealant surrounding the first sub-sealant, and the second sub-sealant close to the first sub-sealant is spaced apart from the first sub-sealant.

In a possible embodiment of the present disclosure, the sealant includes at least two second sub-sealants spaced part from each other.

In a possible embodiment of the present disclosure, the first sub-sealant and the second sub-sealant are formed through a same coating process.

In a possible embodiment of the present disclosure, the first portion includes a third sub-sealant in contact with the liquid crystal layer and at least one fourth sub-sealant arranged at a side of the third sub-sealant away from the liquid crystal layer, the fourth sub-sealant close to the third sub-sealant is spaced apart from the third sub-sealant, and the fourth sub-sealant is of a strip-like structure parallel to the bonding side surface and the array substrate.

In a possible embodiment of the present disclosure, the first portion includes at least two fourth sub-sealants spaced apart from each other.

In a possible embodiment of the present disclosure, the array substrate includes a base substrate and a thin film transistor array arranged on the base substrate, the thin film transistor array includes a gate metal layer, a gate insulation layer, a source/drain metal layer and an insulation protection layer laminated one on another in a direction away from the base substrate, and the bonding pin is arranged at a same layer as the gate metal layer.

In a possible embodiment of the present disclosure, the array substrate includes a base substrate and a thin film transistor array arranged on the base substrate, and the thin film transistor array includes a gate metal layer, a gate insulation layer, a source/drain metal layer and an insulation protection layer laminated one on another in a direction away from the base substrate. The bonding pin includes a first lead and a second lead, the first lead is arranged at a same layer as the gate metal layer, the second lead is arranged at a same layer as the source/drain metal layer, the array substrate further includes a transparent electrode layer arranged in the non-display region, and the first lead is coupled to the second lead by the transparent electrode layer through a via hole.

In another aspect, the present disclosure provides in some embodiments a display motherboard which is cut along a cutting line to form a plurality of the above-mentioned display substrates. The display motherboard further includes a sealing adhesive layer arranged outside the cutting line and formed integrally with the sealant.

In yet another aspect, the present disclosure provides in some embodiments a method for manufacturing a display substrate, including: providing the above-mentioned display motherboard; cutting the display motherboard along the cutting line to form a plurality of secondary substrates; grinding a side surface of each secondary substrate to form the bonding side surface, and exposing the bonding pin; transferring a metal lead at the bonding side surface in such a manner that the metal lead is coupled to the bonding pin; and enabling a chip on film to be coupled to the metal lead through a conductive adhesive layer to form the above-mentioned display substrate.

In still yet another aspect, the present disclosure provides in some embodiments a display device, including: the above-mentioned display substrate; a metal lead arranged at a side surface of the above-mentioned display substrate and coupled to the bonding pin; a chip on film coupled to the metal lead through a conductive adhesive layer; and a circuit board bonded to the chip on film.

In a possible embodiment of the present disclosure, the metal lead extends to the color filter substrate in a direction perpendicular to the array substrate.

According to the embodiments of the present disclosure, the sealant covers a to-be-ground portion, so as to protect the bonding pin on the array substrate during polishing, thereby to prevent the bonding pin from being curled and damaged.

DETAILED DESCRIPTION

In the embodiments of the present disclosure, it should be appreciated that, such words as “in the middle of”, “on/above”, “under/below”, “left”, “right”, “vertical”, “horizontal”, “inside” and “outside” may be used to indicate directions or positions as viewed in the drawings, and they are merely used to facilitate the description in the present disclosure, rather than to indicate or imply that a device or member must be arranged or operated at a specific position. In addition, such words as “first”, “second” and “third” may be merely used to differentiate different components rather than to indicate or imply any importance.

In a side bonding technology, at first a glass side surface (including a side surface of an array substrate1and a side surface of a color filter substrate2) needs to be vertically ground. During the grinding, a metal lead (i.e., a bonding pin)5of a display panel may be damaged. After the bonding, the stability of a contact resistance of the metal lead5may decrease, and detects may occur due to the thermal expansion and contraction caused by external temperature and humidity. In a conventional display panel, an organic film4is arranged on the metal lead5as a protection layer for the metal lead5, as shown inFIG.1. However, when a thickness of the organic film4exceeds a thickness of a display region, excessive support, and thereby display uniformity, may occur. The organic film4may not completely fill in a gap between the array substrate1and the color filter substrate2, so its protection effect is weak.

As shown inFIG.2toFIG.8, in order to solve the above problems, the present disclosure provides in some embodiments a display substrate, including an array substrate1and a color filter substrate2arranged opposite to each other. A liquid crystal layer100and a sealant3are arranged between the array substrate1and the color filter substrate2, and a sealing cavity for receiving the liquid crystal layer100is defined by the sealant3, the array substrate1and the color filter substrate2. The display substrate is provided with a bonding side surface bonded to a chip on film30, the sealant3at least includes a first portion301close to the bonding side surface, the first portion301includes a first side surface in contact with the liquid crystal layer and a second side surface arranged opposite to the first side surface, and the second side surface is flush with the bonding side surface of the display substrate. The array substrate1includes a display region and a non-display region surrounding the display region. A bonding pin4is arranged in the non-display region, extends to a side surface of the display substrate, and is exposed to the outside.

According to the embodiments of the present disclosure, at least a part of the existing sealant3extends to the bonding side surface of the display substrate, that is, the second side surface of the sealant3is flush with the bonding side surface of the display substrate. As compared with the related art where the organic film is arranged independently, in the embodiments of the present disclosure, the bonding pin4is protected by the sealant3, and the sealant3is completely filled in a gap between the array substrate1and the color filter substrate2, so it is able to effectively protect the bonding pin4.

The sealant3may have various structural forms, as long as the bonding pin4is protected by the sealant3and meanwhile the sealing cavity is defined by the sealant3, the array substrate1and the color filter substrate2.

The sealant3may be an integral structure, as shown inFIG.3andFIG.4, or may be a structure having a pattern (i.e., the sealant3includes a hollowed-out portion), as shown inFIG.6andFIG.7. The sealant3may completely cover the non-display region of the array substrate, as shown inFIG.3, or the sealant3may also extends from a side close to the bonding side surface to the bonding side surface to form the first portion301, as shown inFIG.4.

As shown inFIG.4, it should be appreciated that, in a direction parallel to the bonding side surface and the array substrate1(direction X inFIG.4), a length of the first portion301is, but not limited to, smaller than a length of a corresponding side of the array substrate1. For example, in the direction parallel to the bonding side surface and the array substrate1(direction X inFIG.4), the length of the first portion301may be equal to the length of the corresponding side of the array substrate1, as long as a size of the first portion301meets the requirement on the connection between the first portion301and the chip on film.

As shown inFIG.5andFIG.6, in the embodiments of the present disclosure, the sealant3includes a first sub-sealant31surrounding the liquid crystal layer100and at least one second sub-sealant32surrounding the first sub-sealant31, and the second sub-sealant32close to the first sub-sealant31is spaced apart from the first sub-sealant31.

The second sub-sealant32away from the first sub-sealant31is provided with the second side surface. Through the second sub-sealants32arranged at intervals, it is able to reduce the manufacture cost.

The quantity of the second sub-sealants32may be set according to the practical needs. In the embodiments of the present disclosure, when the sealant includes at least two second sub-sealants32, the at least two second sub-sealants32are arranged at intervals.

In the embodiments of the present disclosure, the first sub-sealant31and the second sub-sealant32are formed through a same coating process.

When the first sub-sealant31and the second sub-sealant32are formed through a single coating process, it is able to provide the first sub-sealant31and the second sub-sealant32with a same thickness, i.e., to enable a surface of the first sub-sealant31in contact with the color filter substrate2and a surface of the second sub-sealant32in contact with the color filter substrate2to be located on a same plane.

As shown inFIG.5andFIG.7, in the embodiments of the present disclosure, the first portion301includes a third sub-sealant33in contact with the liquid crystal layer100and at least one fourth sub-sealant34arranged at a side of the third sub-sealant33away from the liquid crystal layer100, the fourth sub-sealant close to the third sub-sealant is spaced apart from the third sub-sealant, and the fourth sub-sealant34is of a strip-like structure extending in a direction parallel to the bonding side surface and the array substrate1(direction X inFIG.7).

Merely the first portion301corresponding to the bonding side surface is provided with the second side surface, and there is a gap between the other portion of the sealant3adjacent to or opposite to the first portion301and the corresponding side surface of the display substrate. That is, a side surface of the other portion away from the liquid crystal layer is arranged in the array substrate1or the color filter substrate2, so as to reduce the manufacture cost.

It should be appreciated that, a length of the fourth sub-sealant34in direction X may be set according to the practical need.

In the embodiments of the present disclosure, when the first portion includes at least two fourth sub-sealants, the at least two fourth sub-sealants32are spaced apart from each other.

In the embodiments of the present disclosure, the array substrate1includes a base substrate and a thin film transistor array arranged on the base substrate, the thin film transistor array includes a gate metal layer, a gate insulation layer12, a source/drain metal layer and an insulation protection layer14laminated one on another in a direction away from the base substrate, and the bonding pin4is arranged at a same layer as the gate metal layer.

As shown inFIG.8, in the embodiments of the present disclosure, the array substrate1includes a base substrate and a thin film transistor array arranged on the base substrate, and the thin film transistor array includes a metal layer, a gate insulation layer12, a source/drain metal layer and a insulation protection layer14laminated one on another in a direction away from the base substrate. The bonding pin4includes a first lead11and a second lead13, the first lead11is arranged at a same layer as the gate metal layer, and the second lead13is arranged at a same layer as the source/drain metal layer. The array substrate1further includes a transparent electrode layer arranged in the non-display region, and the first lead11is coupled to the second lead13by the transparent electrode layer15through a via-hole.

Through the first lead11and the second lead13, it is able to increase a coupling area between the bonding pin4and the chip on film30, thereby to improve the coupling stability.

As shown inFIG.9, the present disclosure further provides in some embodiments a display motherboard which is cut along a cutting line200to form a plurality of the above-mentioned display substrates. The display motherboard further includes a sealing adhesive layer5arranged outside the cutting line200and formed integrally with the sealant3.

The sealing adhesive layer5is formed integrally with the sealant3, i.e., the sealing adhesive layer5is formed through extending the sealant3outward. In this way, after the display motherboard has been cut along the cutting line200, the second side surface of the sealant3is flush with the bonding side surface of the display substrate, so it is able to effectively protect the bonding pin4.

The present disclosure further provides in some embodiments a method for manufacturing a display substrate, including: providing the above-mentioned display motherboard; cutting the display motherboard along the cutting line200to form a plurality of secondary substrates; grinding a side surface of the secondary substrate to form the bonding side surface, and exposing the bonding pin4; transferring a metal lead10at the bonding side surface in such a manner that the metal lead10is coupled to the bonding pin4; and enabling a chip on film30to be coupled to the metal lead10through a conductive adhesive layer20to form the above-mentioned display substrate.

The present disclosure further provides in some embodiments a display device, including the above-mentioned display substrate. The display device further includes: a metal lead10arranged at a side of the above-mentioned display substrate and coupled to the bonding pin4; a chip on film30coupled to the metal lead10through a conductive adhesive layer20; and a circuit board40bonded to the chip on film30.

In the embodiments of the present disclosure, the metal lead10extends to the color filter substrate2in a direction perpendicular to the array substrate1.

When the metal lead10extends to the color filter substrate2, it is able to increase a coupling area between the metal lead10and the bonding side surface of the display substrate, thereby to improve the coupling strength.

The display device may be any product or member having a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone and a tablet computer. The display device further includes a flexible circuit board, a printed circuit board and a back plate.