Shallow trench isolations and method of manufacturing the same

A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero etch to form preliminary trenches in the substrate, performing a STI etch to the preliminary trenches to form final trenches, where the final trenches are deeper and steeper than the preliminary trenches, and filling up the final trenches with insulating material to form shallow trench isolations.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a shallow trench isolation (STI) and method of manufacturing the same, and more particularly, to a shallow trench isolation with gradual sidewalls and method of manufacturing the same.

2. Description of the Prior Art

The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has resulted in the migration from LOCOS, (local oxidation of silicon), isolation technology to an STI isolation technology. Narrow active device regions, comprising sub-micron features become difficult to maintain when isolation regions are formed via LOCOS technology. Bird beak formation, or encroachment of the silicon dioxide isolation region obtained via thermal oxidation procedures, into the adjacent silicon regions result in undesirable consumption of the designed active device region. The use of STI allows the design dimensions of the active device region to be maintained due to the absence of a thermal oxidation procedure used to grow a thick silicon dioxide isolation region. The STI regions are formed via definition of shallow trench shapes in a top portion of a semiconductor substrate, followed by insulator filling and planarization procedures.

The STI technology while not consuming adjacent silicon of an active device region, however, presents other unwanted phenomena, again at the isolation region-semiconductor interface. The dry etch procedures used to define the shallow trench shapes in a top portion of the semiconductor substrate create a sharp corner in the active device region at the STI-semiconductor interface. The sharp corner can result in an unwanted high electric field region for the active device region, translating to deleterious device parameters such as sub-threshold leakage. This phenomenon would become more critical in the 90 nm Bipolar-CMOS-DMOS (BCD) device, wherein the STI structure would be shallower and steeper with an even sharper corner profile.

SUMMARY OF THE INVENTION

This invention will describe a novel process sequence for fabrication of STI regions, in which corner rounding of adjacent active device regions is reduced. This is accomplished via use of a combination of an initial zero mark to form a preliminary trench and a normal STI etch to form a final trench.

One objective of the present invention is to provide a method of manufacturing shallow trench isolations, which includes the steps of providing a substrate, performing a zero etch to form alignment marks and preliminary trenches in the substrate, performing a STI etch to the preliminary trenches to form final trenches, wherein the final trenches are deeper and steeper than the preliminary trenches, and filling up the final trenches with insulating material to form shallow trench isolations.

In an alternative aspect, the method of the present invention further includes the step of forming a spacer on the sidewall of each preliminary trench before the STI etch for the profile of the spacer to be transferred to the final trench.

Another objective of the present invention is to provide a shallow trench isolation in a substrate, which includes a substrate, and a shallow trench isolation formed in the substrate, wherein the sidewall of the shallow trench isolation has two different slopes.

DETAILED DESCRIPTION

In the following detailed description of the present invention, reference is made to the accompanying drawings which form a part hereof and is shown byway of illustration and specific embodiments in which the invention may be practiced. These embodiments are described in sufficient details to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Before describing the preferred embodiment in more detail, further explanation shall be given regarding certain terms that may be used throughout the descriptions.

The term “etch” or “etching” is used herein to generally describe a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed. For example, it should be understood that the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) above the silicon, and then removing the areas of silicon no longer protected by the masking layer. As such, the areas of silicon protected by the mask would remain behind after the etch process is complete. However, in another example, etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete. The above description serves to distinguish the term “etching” from “removing.” When etching a material, at least a portion of the material remains behind after the process is completed. In contrast, when removing a material, substantially all of the material is removed in the process. However, in some embodiments, ‘removing’ is considered to be a broad term that may incorporate etching.

During the descriptions herein, various regions of the substrate upon which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and furthermore that the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may designate areas having certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.

The terms “forming,” “form,” “deposit,” or “dispose” are used herein to describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc. According to various embodiments, for instance, deposition may be performed according to any appropriate well-known method. For instance, deposition can comprise any process that grows, coats, or transfers material onto a substrate. Some well-known technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), high density plasma CVD (HDPCVD) and plasma-enhanced CVD (PECVD), amongst others.

The “substrate” as used throughout the descriptions is most commonly thought to be silicon. However, the substrate may also be any of a wide array of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.

FIGS. 1-8are cross-sectional views depicting an exemplary process flow of manufacturing shallow trench isolations in accordance with the embodiment of the present invention. First, please refer toFIG. 1. A semiconductor substrate100is provided to serve as base for forming the shallow trench isolations of the present invention. The substrate100is commonly divided into a high-voltage (HV) region100A and a logic region100B. The HV region100A is defined to form high voltage control logic (such as 36V high-voltage double diffused metal-oxide devices (DMOS)) and the logic region100B is defined to form low voltage control logic with relatively lower operating voltage (such as 5V or 12V). A thermal oxidation procedure is performed at a temperature between about 750 to 850° C. in an oxygen ambient, resulting in the growth of a protective silicon dioxide layer101on the substrate100.

Please refer toFIG. 2. After the silicon dioxide layer101is formed, a zero etch process is performed to form alignment marks (not shown) and preliminary trenches103in the substrate100. The alignment marks are marks for the reticle to align with in the photolithographic process. The preliminary trench103is a shallow, tapered trench with a gradual slope of sidewall. In the present invention, the preliminary trench103is formed together with alignment marks in the zero etch process with patterned photoresist. This means the preliminary trench103is general provided with a depth the same as the alignment marks. This also means the depth of the preliminary trench103can be easily adjusted depending on the product requirement by changing the etch time of zero etch without affecting the standard and routine logic process. Furthermore, in the present invention, the preliminary trench103is a predefined structure for the final trench. Since the preliminary trench103is predetermined in advance, it is possible in the present invention to form a final trench structure with more gradual sidewall103aand better corner rounding profile.

Please refer toFIG. 3. After the preliminary trench103is formed, an implantation process is performed to form a buried layer100C in the logic region100B of the substrate100. In the present invention, the buried layer100C may be all kinds of well structures necessary in the active region, such as P-type well (PW), N-type well (NW), or a common buried N-type well (BNW). The buried layer100C can be formed only in the logic region100B via the shielding of a photoresist on the high-voltage region100A. It should be noted that, in certain embodiments, the implantation process and the buried layer maybe omitted depending on the process and product characteristics.

Please refer toFIG. 4. After the buried layer100C is formed, a spacer105is formed on the sidewall103aof the preliminary trench103. In the preferred embodiment, the spacer105on the sidewall of the preliminary trench103serves as a buffer structure in following STI (shallow trench isolation) etch process. The presence of the spacer105in the process can make the desired final STI trench have more gradual sidewalls compared to those STI trench form in standard STI process, especially to form a sidewall profile with different slopes. The spacer105may be formed by first depositing a conformal silicon oxide layer, and then perform a blanket etch to reduce the thickness of the silicon oxide layer until only the spacer105on the sidewall of preliminary trench103remains. The blanket etch process would also remove the protective silicon dioxide layer101previously formed on the substrate100.

It should be noted that, in certain embodiments, the spacer105may not be formed in the process . If the desired final STI structure needs not to have a sidewall of different slopes, the spacer105would be unnecessary and may be omitted. In addition, the spacer105may be formed of any suitable insulating material other than silicon oxide.

Please refer toFIG. 5. After the spacer105is formed on the sidewall, a pad oxide layer106and a silicon nitride layer107are sequentially formed on the substrate100. The pad oxide layer106would conformally cover the spacer105and the preliminary trench103. In the embodiment, the pad oxide layer106is formed to reduce the stress of substrate surface, and the silicon nitride layer107will serve as an etch mask in following STI process.

Please refer toFIG. 6. After the pad oxide layer106and the silicon nitride layer107are formed, the silicon nitride layer107is patterned by a photolithographic process to define the pattern of the STIs both in the HV region100A and the logic region100B. A STI etch process is then performed using the patterned silicon nitride layer107to form the shallow trench in the substrate. In the present invention, the STI etch process is a standard process of logic STI loop to form shallow trench111in the logic region100B. However, please note that this STI etch would also etch the preliminary trench103again in the HV region100A. It is clearly shown in theFIG. 6that a deeper final trench109with a depth of D1and a number of normal STI trench111with a depth of D2are formed respectively in the HV region100A and the logic region100B. Since the final trench109is subject to two etch steps, i.e. the zero etch (the first etch) and the STI etch (the second etch), the final trench109would be slightly deeper and more gradual than the normal STI trench111. This also means that the depth of the final trench109is tunable by predetermining the depth of zero mark with the depth of normal STI.

Moreover, in the process that the spacer105is used, the profile of the spacer105would be transferred to the final trench109by the STI etch process. It can be seen inFIG. 6that the final trench109has a lower portion109awith slope gradient near the bottom of the final trench109. Generally, if the STI etch is performed in presence of the spacer105, the final trench109would have two or more different slopes. For example, as the final trench109shown inFIG. 6, the sidewall of the final trench109includes a lower portion109awith slope gradient near the bottom, a middle steep portion109b, and a upper portion109cfrom the sidewall103aof previous preliminary trench103, and the slope of the steep portion109bof the sidewall would be larger than the slope of the lower portion with slope gradient109aof the sidewall.

Please refer now toFIG. 7. After the final trench109and the STI trench111are formed, a high-density plasma (HDP) deposition process is performed to fill up the trench with insulating material, and the substrate with deposited insulating material is then planarized by a chemical mechanical polishing process to remove the unnecessary portion above the silicon nitride layer107, thereby forming the STIs113and115in both the HV region100A and the logic region100B. It should be noted that, since the final trench109in the HV region100A and the normal STI trench111in the logic region100B have different profiles, the resulting STIs113and115would accordingly have different profiles. Generally, STI113has sidewalls with profiles more gradual than that of the STI115, and the corner113aof the STI113in the HV region100A would have better rounding effect. Thus the unwanted high electric field resulted from the sharp corner in the HV region can be properly prevented.

Finally, please refer toFIG. 8. After the STIs113and115are formed, a STI etch-back process is performed to remove the unnecessary silicon nitride layer107. It should be noted that the height of the STI structure would be slightly reduced by this etch-back process. Furthermore, in the presence of the spacer105, the final STI113in the HV region100A would be provided with a spacer portion105on the upper portion109cof the sidewall near the surface of the substrate100. In the condition that the pad oxide layer106, the spacer105and the STI113are all made of silicon oxide, the three portions would emerge together. Alternately, the material of spacer105may be other insulating material other than oxide, then the STI113and the adjacent spacer portion105would have different materials. In this way, the STI process of the present invention is completed. After the STIs113and115are formed and the active area (AA) between the STIs are defined, the process of manufacturing the MOS devices can be subsequently conducted to complete the whole semiconductor process.