Digital shunt regulator for NFC devices

A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.

TECHNICAL FIELD

Embodiments of the disclosure relate to near field communication (NFC) devices and more particularly to voltage regulation in NFC devices.

BACKGROUND

NFC is a 13.56 MHz carrier based secure communication technology which has found its uses in as personal ID, money transaction etc. An NFC system includes an NFC tag that contains information and an NFC reader that reads information from the NFC tag. An NFC tag can be a passive NFC tag or an active NFC tag. The passive NFC tag utilizes the magnetic field or radio frequency (RF) field generated by an NFC reader for operation. When the magnetic field of the NFC reader is incident on the antenna of the passive NFC tag, a controller inside the passive NFC tag accesses its internal memory and provides information to the NFC reader by modulating the incident magnetic field. An active NFC tag generates its own magnetic field to interact with an NFC reader. It is to be noted that NFC communication technology works on the same principle as RF communication technology. Hence, the NFC devices (readers/tags) can interchangeably interact with RF devices (readers/tags).

An NFC device can communicate to a range of 50 mm, and the incident magnetic field or RF field on NFC device antenna can vary from 0.15 A/m to 12 A/m. Various applications require an NFC device antenna to have a high dynamic range. At higher field extremes, very high voltage swing is present on the NFC device antenna that could reach excess of 40 volt which would damage the NFC device.

SUMMARY

An example embodiment provides a digital shunt regulator. The digital shunt regulator includes an antenna that receives a radio frequency (RF) signal and generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.

Another example embodiment provides a near field communication (NFC) device. The NFC device includes an antenna that receives a radio frequency (RF) signal and generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.

Another example embodiment provides a method of regulating a radio frequency (RF) signal. A differential output signal is generated from the RF signal. The peak voltage of the differential output signal is detected and compared with a first voltage and second voltage. A set of shunt NMOS transistors of a plurality of shunt NMOS transistors is activated if the peak voltage is more than the second voltage and a set of shunt NMOS transistors of the plurality of shunt NMOS transistors is deactivated if the peak voltage is less than the first voltage.

Other aspects and example embodiments are provided in the Drawings and the Detailed Description that follows.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1illustrates a schematic of a receiver150that includes an analog shunt regulator100. The analog shunt regulator100includes an antenna assembly101. The antenna assembly101includes an antenna101aand matching network101b. The analog shunt regulator100receives a radio frequency (RF) signal at the antenna101a. The antenna assembly101is coupled to an RF filter103through a differential path101c. A clamp circuit112is coupled to the differential path101c. A peak sampler104is coupled to the output of RF filter103. A block102that contains slicer and digital locked loop (DLL) provides clock signal to the peak sampler104, RF filter103and other receiver components113. The other receiver components113include any of memory, controller, processing device and IF (Intermediate frequency) filters. The peak sampler104is coupled to a capacitor106and a voltage-divider circuit that includes resistor R1107and resistor R2108. A shunt amplifier109receives a reference voltage Vref and a signal from a node114which is between resistor R1107and resistor R2108. The output of shunt amplifier109is connected to shunt NMOS transistors M1110and M2111. The shunt NMOS transistors M1110and M2111are further coupled to the differential path101c. In some embodiments, the analog shunt regulator100includes plurality of shunt NMOS transistors. In one embodiment, the shunt NMOS transistors M1110and M2111are any of regulating devices known in the art. One terminal of the shunt NMOS transistors M1110and M2111is connected to the ground terminal119.

The operation of the analog shunt regulator100illustrated inFIG. 1is now explained. The antenna101areceives a radio frequency (RF) signal from a neighboring device and generates a differential output signal over the differential path101c. The neighboring device is one of RF device, NFC device or any field communication device. The matching network101bis a passive network that is used for impedance matching between the antenna101aand the differential path101c. The clamp circuit112clamps the differential output signal to remove the negative component of the differential output signal. The RF filter103removes the unwanted harmonics from the differential output signal. The peak sampler104in conjunction with the capacitor106detects the peak voltage of the signal from the RF filter103. The peak sampler and the RF filter are synchronized by the clock signal from the block102which contains the slicer and digital locked loop (DLL). The peak voltage signal from the peak sampler104is received by the voltage divider circuit that includes the resistor R1107and resistor R2108. Based on the values of the resistor R1107and resistor R2108, a corresponding voltage is generated at node114. The voltage at node114is compared with the reference voltage Vref by the shunt amplifier109and a residual error voltage is generated. The residual error voltage is amplified by the shunt amplifier109to generate the shunt amplifier output on line115. The shunt amplifier output on line115controls the resistance of the shunt NMOS transistors M1110and M2111by controlling a bias gate voltage of the shunt NMOS transistors M1110and M2111. A high field strength of RF signal at the antenna101awould result in very high potential at differential path101c. Therefore, when there is very high potential at differential path10k, the shunt amplifier output on line115is high thus providing high potential on the gate terminals of the shunt NMOS transistors M1110and M2111. This offers a very low resistance to the high potential at the differential path101e, which discharges through the shunt NMOS transistors M1110and M2111to the ground119. Thus, the other receiver components113are not subjected to the high potential at the differential path101c.

The receiver150requires that the step response of shunt regulator100should not have any undesirable overshoot or undershoot which could potentially be misinterpreted as response to incoming ASK modulation. This is important for reliable detection of the received RF signal. The feedback system of the shunt regulator100should have a good phase margin to avoid ringing in step response. Ringing refers to the unstable response of the regulator when there is transition in step input to the regulator. However, the analog shunt regulator100has a poor phase margin given the complex nature of the feedback loop. Also, the stability of the feedback loop of the shunt regulator100is heavily impacted by the delay introduced by peak sampler104, phase shift of the RF filter103, variable impedance offered by the clamp112and the matching network101b. In addition, different application demands different type of antenna and matching network, which makes the task of stabilizing the feedback loop very difficult.

FIG. 2Aillustrates a schematic of a receiver250that includes a digital shunt regulator200. The digital shunt regulator200includes an antenna assembly201. The antenna assembly201further includes an antenna201aand a matching network201b. The digital shunt regulator200receives a radio frequency (RF) signal at the antenna201a. The digital shunt regulator200in one embodiment includes an RF filter and a block containing slicer and digital locked loop (DLL) which is similar in connection and operation as indicated in description ofFIG. 1. The antenna assembly201is coupled to a peak detector202through a differential path201c. A clamp circuit207is coupled to the differential path201c. Other receiver components208include any of memory, controller, processing device and IF (Intermediate frequency) filters. A first comparator203receives the voltage output of the peak detector202and a first voltage Vi. The first voltage Vi defines the lower threshold voltage. A second comparator204receives the voltage output of the peak detector202and a second voltage Vh. The second voltage Vh defines the upper threshold voltage. A digital state machine205is configured to receive the output of the first comparator203and the output of the second comparator204. A plurality of shunt NMOS transistors206is configured to receive the output of the digital state machine205. In one embodiment, the shunt NMOS transistors are any of switching devices known in the art. The plurality of shunt NMOS transistors206is coupled to the differential path201cthereby forming a digital feedback loop. The plurality of shunt NMOS transistors206and the peak detector202are thus connected in parallel.

The operation of the digital shunt regulator200illustrated inFIG. 2Ais now explained. The antenna201areceives a radio frequency (RF) signal from a neighboring device to generate a differential output signal over the differential path201c. The neighboring device is one of RF device, NFC device or any field communication device. The matching network201bis a passive network that is used for impedance matching between the antenna201aand the differential path201c. The peak detector202detects the peak voltage of the differential output signal received over the differential path201cand generates a voltage output. The voltage output from the peak detector202defines the peak voltage of the differential output signal. The voltage output from the peak detector202is received by the first comparator203and the second comparator204. The first comparator203compares the voltage output of the peak detector and the first voltage Vi and generates a first comparator output on line203o. The second comparator204compares the voltage output of the peak detector and the second voltage Vh and generates a second comparator output on line204o. The first comparator output on line203oand the second comparator output on line204oare received by the digital state machine205. Based on the results from the first comparator203and the second comparator204, the digital state machine205controls the number of shunt NMOS transistors of the plurality of shunt NMOS transistors206that are activated to maintain voltage output of the peak detector between the first voltage Vi and the second voltage Vh. The digital state machine205controls the resistance offered by the plurality of the shunt NMOS transistors206by activating a set of shunt NMOS transistors of a plurality of shunt NMOS transistors206if the peak voltage is more than the second voltage and deactivating a set of shunt NMOS transistors of the plurality of shunt NMOS transistors206if the peak voltage is less than the first voltage. Therefore, when there is very high potential at the differential path201csuch that the voltage output of the peak detector202is more than the second voltage, the digital state machine205would increase the number of shunt NMOS transistors that are activated. This offers a very low resistance to the high potential at the differential path201cwhich discharges through the plurality of shunt NMOS transistors206to the ground. Thus, the other receiver components208are not subjected to the high potential at the differential path201c. The digital state machine205decreases the number of transistors that are activated if the voltage output of the peak detector is less than the first voltage.

FIG. 2Billustrates the configuration of the plurality of shunt NMOS transistors206illustrated inFIG. 2A. The plurality of shunt NMOS transistors206a,206band206care connected to ground terminal219through a plurality of switches b1, b2, b3and connected to voltage terminal Vdd through a plurality of switches c1, c2, c3. It is to be noted that c1, c2, and c3are inverse of b1, b2and b3respectively. For example, c1is inverse of b1. Thus, when b1is in ON state then c1will be in OFF state. During this state, shunt NMOS transistors206awould be connected to ground terminal219through switch b1. It is understood that this principle is followed by other pair of switches (b2, c2and b3, c3) as well. The plurality of shunt NMOS transistors206a,206band206care connected to differential path201c. The plurality of switches b1, b2, b3and d, c2, c3is controlled by the digital state machine205.

The functioning of digital state machine205in conjunction with the plurality of shunt NMOS transistors206depicted inFIG. 2Ais now explained. The digital state machine uses a digital logic to activate the plurality of switches b1, b2, b3and c1, c2, c3. One of the digital logic used by the digital state machine is SAR (Successive approximation register) logic which is explained later in the description with the help ofFIG. 3. The digital state machine205uses the output of the first comparator203and the second comparator204to control the resistance that is offered by the plurality of shunt NMOS transistors206by activating appropriate number of shunt NMOS transistors and ensures that the voltage output of the peak detector is between Vh and Vi. The second voltage Vh is used to avoid the voltage at the differential path201cto go above the device reliability limit. The first voltage Vi is used to avoid shunting, when too many shunt NMOS transistors at the differential path201care ON, which can reduce the incident RF signal amplitude below optimum. Initially when RF field is incident on the antenna201a, the plurality of shunt NMOS transistors206are activated, which prevent reliability issue at higher field. Once calibration is activated, the digital state machine205uses the comparison results from both comparators203and204to activate the shunt NMOS transistors so that the voltage output of the peak detector is within Vh and Vi, in successive steps. The number of steps can be determined by the digital logic used by the digital state machine205. Once the voltage output of the peak detector is within the upper and lower threshold, the bit state of the digital state machine205is configured to be constant and not modified further. Thereafter, the digital shunt regulator200operates in an open loop manner.

One of the advantages of the digital shunt regulator200is open loop nature of the circuit which ensures high stability. Further, a digital feedback loop in the digital shunt regulator200provides more flexibility to control the voltage at the differential path201cto desire value. In addition, the area used to implement digital shunt regulator200is four times lesser than used for analog shunt regulator100. This is because in digital shunt regulator200, the shunt NMOS transistors of the plurality of shunt NMOS transistors206are connected in parallel whereas in the analog shunt regulator100, the pair of shunt NMOS transistors formed a series network.

FIG. 3illustrates a digital state machine implementing SAR logic according to an embodiment. On receiving the comparison results from the comparators203and204, the digital state machine starts calibration at step301. Initially, all the shunt NMOS transistors of the plurality of shunt NMOS transistors206are turned ON. Also, the calibration is made from MSB to LSB. The logic is implemented for N bits and in one cycle, calibration of only one bit is completed. At step302, calibration of ithbit is initiated which is having a value of bi. At step303, the digital state machine205analyzes the results from comparator204which compares the peak voltage from the peak detector202Vpeak and the upper threshold voltage Vh. If the value of Vpeak is more as compared to the upper threshold voltage Vh, the system advances to step304. At step304, the value of the ith bit is not altered and the value remains bi. Further, the system reduces the bit count by one to i−1 and the system returns to step302for calibration of i−1thbit. If at step303, Vpeak is less than Vh, the system advances to step305. At step305, the digital state machine205analyzes the results from the comparator203which compares the peak voltage from the peak detector202Vpeak with the lower threshold voltage Vi. If the value of Vpeak is more as compared to the lower threshold voltage Vi, the system advances to step307. At step307, the system configures the bit state of the digital state machine205to be constant since Vpeak is between Vh and Vi and no further calibration is carried out for the remaining bits. If at step305, Vpeak is less than Vi, the value of the bit is changed to inverse of bi(bi”’). Further, the system reduces the bit count by one to i−1 and the system returns to step302for calibration of i−1thbit. In some embodiments, the digital state machine implements a digital logic in which the state of bits is changed sequentially to maintain the voltage output of the peak detector in between the first voltage and the second voltage and the state of bits is configured to be constant when the voltage output of the peak detector is in between the first voltage and the second voltage.

FIG. 4illustrates the response of the analog shunt regulator100and digital shunt regulator200to the incident radio frequency (RF) signal401at the antenna. The RF signal401consists of a continuous wave (CW)401aat the initialization of the transmission. This is followed by data transmission401billustrated by a step response. The response of analog shunt regulator100to the incident RF signal401is illustrated as402. It can be seen that the analog shunt regulator100involves ringing402aand402bduring the RF signal transitions. Ringing refers to the unstable response of the shunt regulator when there is transition in RF input to the regulator. Since, the analog shunt regulator100has a poor phase margin given the complex nature of the feedback loop, it shows ringing effect during transitions. The response of digital shunt regulator200to the incident RF signal401is illustrated as403. The initial calibration of the digital state machine205is represented by403a. Thus the system calibration is completed before the packet containing data is received by the receiver and therefore the system operates in open loop manner after the initial calibration. The impedance of the digital feedback loop in the digital shunt regulator200does not change during data reception which ensures that the system time constant does not vary and hence no ringing is seen at the differential path201c. Thus undesired undershoot or overshoot in the step response is avoided during data reception. It also eases the task of data reception and improves BER (bit error rate). In addition the digital shunt regulator200consumes low power as compared to continuous running shunt loop in analog shunt regulator100illustrated inFIG. 1. This is because the calibration in digital shunt regulator200is completed in short frame of time and thereafter the circuit operates in open loop manner.

FIG. 5is a flowchart500illustrating a method of regulating a radio frequency (RF) signal according to an embodiment. At step501, the RF signal is received at the antenna201aof an RF device. A peak detector202detects the peak voltage of the received RF signal at step502. At step503, the peak voltage from the peak detector202is compared with a lower threshold voltage Vi and an upper threshold voltage Vh. The comparison results are fed to a digital state machine205that implements a digital logic at step504for example SAR (Successive approximation register) logic. At step505, based on the comparison results, the digital state machine205activates a set of shunt NMOS transistors of a plurality of shunt NMOS transistors206if the peak voltage is more than the second voltage and deactivates a set of shunt NMOS transistors of the plurality of shunt NMOS transistors206if the peak voltage is less than the first voltage. The bit state of the digital state machine205is configured to be constant when the peak voltage from the peak detector202is between the lower threshold voltage Vi and the upper threshold voltage Vh, at step506. The RF device then operates in an open loop manner at step507.

FIG. 6illustrates a computing device according to an embodiment. The computing device600is, or is incorporated into, a mobile communication device, such as a mobile phone, a personal digital assistant, a personal computer, or any other type of electronic system.

In some embodiments, the computing device600comprises a megacell or a system-on-chip (SoC) which includes control logic such as a CPU612(Central Processing Unit), a storage614(e.g., random access memory (RAM)) and a tester610. The CPU612can be, for example, a CISC-type (Complex Instruction Set Computer) CPU, RISC-type CPU (Reduced Instruction Set Computer), or a digital signal processor (DSP). The storage614(which can be memory such as RAM, flash memory, or disk storage) stores one or more software applications630(e.g., embedded applications) that, when executed by the CPU612, perform any suitable function associated with the computing device600. The tester610comprises logic that supports testing and debugging of the computing device600executing the software application630. For example, the tester610can be used to emulate a defective or unavailable component(s) of the computing device600to allow verification of how the component(s), were it actually present on the computing device600, would perform in various situations (e.g., how the component(s) would interact with the software application630). In this way, the software application630can be debugged in an environment which resembles post-production operation.

The CPU612typically comprises memory and logic which store information frequently accessed from the storage614. The computing device600includes NFC block with digital shunt regulator616which is used for communication with neighboring field devices. The NFC block with digital shunt regulator616is analogous to the digital shunt regulator200in connections and operation. The open loop nature of the digital shunt regulator200ensures high stability. Further, a digital feedback circuit in the digital shunt regulator200provides more flexibility to control the antenna voltage to a desired value. In addition, the area used to implement digital shunt regulator200is four times lesser than used for analog shunt regulator100, therefore occupying lesser area on the computing device600.

In the foregoing discussion, the terms “connected” means at least either a direct electrical connection between the devices connected or an indirect connection through one or more passive intermediary devices. The term “circuit” means at least either a single component or a multiplicity of passive components, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, charge, data, or other signal. Also, the terms “coupled to” or “couples with” (and the like) are intended to describe either an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, that connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The term “on” applied to a transistor or group of transistors is generally intended to describe gate biasing to enable current flow through the transistor or transistors.

The foregoing description sets forth numerous specific details to convey a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. Well-known features are sometimes not described in detail in order to avoid obscuring the invention. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but only by the following Claims.