INTEGRATED CIRCUIT PACKAGES WITH DAMPENERS TO REDUCE VIBRATION EFFECTS

Integrated circuit packages with dampeners to reduce vibration effects are disclosed. An example apparatus comprises a substrate, a semiconductor die carried by the substrate, and a dampener carried by the substrate. Further, the example dampener is dimensioned to interface with a heatsink when the heatsink is thermally coupled to the semiconductor die.

BACKGROUND

The demand for greater computing power and faster computing times continues to grow. This has led to higher density connectors on computer hardware components to transfer signals more quickly. Some processor chips (e.g., land grid array (LGA) processor chip, ball grid array (BGA) processor chip, etc.) are communicatively coupled to printed circuit boards (PCBs) via sockets constructed to receive and electrically couple to contacts on the processor chips. Often a heatsink is mechanically and thermally coupled to the processor chip on a side opposite the socket to facilitate the dissipation of heat generated by the processor chip.

DETAILED DESCRIPTION

As the computing industry evolves, the demand for higher input/output (IO) speeds and throughput continues to increase. Computer hardware components, such as central processing units (CPUs), graphical processing units (GPUs), memory, motherboards, etc., are often connected by electrical connectors. For example, a CPU in a server system may be connected to one or more other components by a cable connector that connects to a mating connector on a substrate or board of the CPU. A recent trend has been to increase the IO capability by adding more pin counts to the connectors on the CPUs. However, traditional cable connectors use two rows of pins, which are very low density. As a result, adding more pins to the cable connector requires more space on the board and therefore increases the overall size of the package. In some instances, there may not be enough space to add more pins. Manufacturers desire to keep the package size small while still increasing the IO capabilities.

Some example cable connectors use socket connector type connections. Socket connectors have an array or grid of socket pins. The socket pins are relatively thin and can be placed in a high-density arrangement, thereby improving the IO capability of a system. These socket pins are relatively fragile. Further, the socket pins are usually exposed and, thus, are prone to damage. Therefore, when a person is handling the socket connector, the person has to be cautious not to touch the socket pins or hit the socket pins on any foreign object, as this could easily bend or break the socket pins.

A socket substrate includes such pins to contact pads on the surface of an opposing substrate. Typically, a compression or loading mechanism is used in order to deflect the pins so with sufficient force (e.g., at least 10 grams-force per pin) to ensure consistent and reliable electrical contact between the components. In some examples, if the socket substrate is subject to vibrations (e.g., during shipping, during vibrational testing, etc.), the pins may move (e.g., slide) relative to the pads. In such examples, the pins may scratch and/or damage the opposing pads (e.g., via fretting) which, in turn, wears down coatings on the pads that prevent oxidation. When the coatings are scratched away, the underlying material of the contact pads (e.g., nickel, copper, etc.) is exposed to environmental conditions (e.g., moisture, air, etc.). The underlying material can oxidize, which may reduce the electrical conductivity between the pins and associated pads.

Examples disclosed herein provide dampeners (e.g., dampening bodies, compressibly resilient materials, etc.) for use in socket-based architectures to mitigate risk of damage to pad surfaces. Examples disclosed herein position dampeners to resist (e.g., reduce) movement of an example socket substrate relative to an associated integrated circuit (IC) package (e.g., processor chip) and, thus, resist (e.g., reduce) movement of associated pins of the socket substrate relative to the IC package. For example, disclosed examples include dampeners that are positioned to interface with an example heatsink that presses an IC package against the socket substrate to resist movement of the IC package relative to such a substrate. Accordingly, examples disclosed herein reduce and/or eliminate fretting on pad surfaces by dampening vibrations in an associated IC package. Examples disclosed herein improve the electrical connectivity in such an IC package by increasing the number of socket pins and mitigating fretting between the socket pins and any associated pad surfaces.

FIG.1illustrates an exploded view of an example integrated circuit (IC) package heat dissipating component stack100constructed in accordance with teachings disclosed herein. InFIG.1, the component stack100includes a heatsink102, a carrier (e.g., a package carrier, a carrier plate)104, an integrated circuit (IC) package106, a bolster plate108, a socket110coupled to a printed circuit board (PCB) (e.g., a motherboard)112, and a back plate114.

In this example, the IC package106includes one or more electrical circuits on a semiconductor substrate. In some examples, the IC package106can perform processing functions, memory functions, and/or any other suitable functions. The IC package106can include any type of processing circuitry, including programmable microprocessors, one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, one or more XPUs, one or more ASICs, and/or one or more microcontrollers. InFIG.1, the IC package106is a land grid array (LGA) processor chip. Additionally or alternatively, the IC package106can be one of a ball grid array (BGA) processor chip or a pin grid array (PGA) processor chip instead. Further, other types of IC packages can be used in the component stack100instead of a processor chip (e.g., a memory chip). InFIG.1, the carrier104is used to couple the heatsink102to the IC package106prior to assembly of the entire component stack100. In some examples, the carrier104is omitted and the assembly process involves inserting the IC package106into the socket110and then attaching the heatsink102.

InFIG.1, the heatsink102is couplable (e.g., thermally couplable) to the IC package106to dissipate heat therefrom. InFIG.1, the heatsink102is mechanically coupled to the back plate114via fixture elements, loading mechanisms, or fasteners115to place the components between the heatsink102and the back plate114within the component stack100in compression when assembled. In some examples, the heatsink102is coupled to the back plate114via the bolster plate108positioned therebetween. More particularly, as shown inFIG.1, the bolster plate108is couplable to a top surface116of the PCB112while the back plate114is couplable to a bottom surface118of the PCB112opposite the bolster plate108. In this manner, the PCB112is sandwiched between the bolster plate108and the back plate114. The bolster plate108is constructed to surround the socket110positioned on the top surface116of the PCB112.

The socket110communicatively couples the IC package106to the printed circuit board112. InFIG.1, the socket110is an LGA socket, which includes a plurality of pins within the socket arranged to interface (e.g., electrically couple) with corresponding contacts/lands/pads on the IC package106. In other examples, the socket110can be implemented by any other type of socket (e.g., a BGA, a PGA, etc.) suitable to receive and interface with the IC package106. The compression created by the mechanical coupling of the heatsink102to the back plate114via the fasteners115serves to ensure that corresponding connectors (e.g., pins, lands, etc.) on the socket110and the IC package106remain in contact. However, as previously mentioned, the pins on the socket110are fragile and can subject corresponding contacts on the IC package106to fretting (e.g., during vibrations or other movement). In accordance with teachings disclosed herein, the example component stack100includes an example dampener120positioned on, carried by, and/or included with the IC package106to mitigate against fretting, as described in detail in connection with at leastFIGS.2A-7I.

FIG.2Ais a simplified cross-sectional view of the example component stack100ofFIG.1prior to the heatsink102being pressed down onto the example IC package106.FIG.2Bis another simplified cross-sectional view of the component stack100ofFIG.1after the example heatsink102has been pressed down onto the example IC package106. InFIGS.2A and2B, the component stack100includes the heatsink102ofFIG.1, the IC package106ofFIG.1, the bolster plate108ofFIG.1, the socket110ofFIG.1, the printed circuit board112ofFIG.1, the back plate114ofFIG.1, and the dampener120ofFIG.1(the carrier104ofFIG.1and the fasteners115ofFIG.1are omitted inFIGS.2A and2Bfor purposes of explanation). Further, the example component stack100ofFIGS.2A and2Billustrates example pins200in contact with example pads202on the IC package106. As such, an example surface204(e.g., bottom surface) of the IC package106can include a BGA or an LGA.

InFIG.2A, the example heatsink102is shown separate (e.g., removed, disassembled, etc.) from the IC package106. Alternatively, inFIG.2B, the example heatsink102is shown coupled to (e.g., in contact with, thermally coupled with, etc.) the IC package106. In particular, the example heatsink102thermally couples to an example semiconductor die included in the IC package106, as described in detail in connection with at leastFIGS.3-7I. In some examples, the heatsink102thermally couples to such a semiconductor die via an integrated heat spreader (IHS), as described in detail in connection with at leastFIG.4.

In some examples, when the heatsink102is separate from the IC package106(FIG.2A), the dampener120extends from the IC package106past another example surface206(e.g., top surface) of the IC package106. Further, the example dampener120is dimensioned to interface with the heatsink102when, for example, the heatsink102is thermally coupled to the IC package106(FIG.2B). More particularly, due to the dampener120extending beyond the top surface206, in some examples, when the heatsink102is pressed against the top surface206, the dampener120is in compression. Accordingly, in some examples, the dampener120can be a compressibly resilient material. In some examples, the dampener120includes foam, silicone, polyurethane, etc. In some examples, the dampener120is a dampening body having a generally rectangular cross-section, a generally circular cross-section, a generally ovular cross-section, a generally triangular cross-section, a generally trapezoidal cross-section, and/or a cross-section of any other suitable shape. In some examples, the dampener120is included in an array or pattern of dampeners, as described in detail in connection with at leastFIGS.7A-7I.

FIGS.3-5illustrate cross-sectional views of different implementations of the IC package106ofFIGS.1-2B. In other words, any of the examples described in connection withFIGS.3-5can be used to implement the IC package106ofFIGS.1-2B. Turning toFIG.3, a cross-sectional view of an example first implementation300of the IC package106is shown. In the example ofFIG.3, the IC package106includes an example semiconductor die302carried by an example package substrate304. In particular, the example package substrate304includes a surface306(e.g., on a first side308) of the package substrate304to support the semiconductor die302. In some examples, the package substrate304is an interposer. For example, the IC package106includes another package substrate interconnecting the semiconductor die302and the interposer.

In the example ofFIG.3, the dampener120is carried by (e.g., supported on) the surface306of the package substrate304. In some examples, the dampener120is coupled directly to the surface306of the package substrate304via an adhesive (e.g., an epoxy, a liquid adhesive, double sided tape, etc.). The surface306of the example package substrate304is opposite an example second side310of the package substrate304. The example second side310includes the bottom surface204(including the pads202ofFIGS.2A and2B) of the IC package106.

The example dampener120is positioned adjacent a side312of the semiconductor die302. Further, the example dampener120is laterally offset from the semiconductor die302along the surface306of the package substrate304. As such, the example dampener120is spaced apart from the side312of the semiconductor die302. Additionally, the example dampener120extends farther away from the package substrate304than the semiconductor die302. As shown inFIG.3, the example dampener120extends farther away from the package substrate304than an example backside314(facing away from the package substrate304) of the semiconductor die302. In other words, the backside314of the semiconductor die302is closer to the package substrate304than an end316of the dampener120.

In the example first implementation300, the semiconductor die302is a bare die exposed on the package substrate304. In other words, in this example, the IC package106is a bare die package. As such, the example heatsink102(FIGS.1,2A, and2B) is couplable (e.g., directly couplable) with the semiconductor die302via the backside314without a package lid or IHS positioned therebetween. In some examples, a thermal interface material (TIM) may still be positioned between the backside314of the semiconductor die302and the heatsink102. The example dampener120is dimensioned and/or otherwise positioned to interface with the heatsink102when the heatsink102is thermally coupled to the semiconductor die302. For example, referring toFIGS.2B and3, the dampener120is to be held in compression between the package substrate304and the heatsink102when the heatsink102is thermally coupled to the semiconductor die302. More particularly, the dampener120can be compressed between the heatsink102and the surface306of the package substrate304. The example dampener120includes materials that enable the dampener120to be compressibly resilient. As such, the example dampener120resists movement between the heatsink102and the IC package106when the heatsink102is thermally coupled to the semiconductor die302. This, in turn, can reduce movement between the IC package106and the socket110(FIGS.1,2A, and2B), thereby reducing fretting of the contact pads202on the IC package106.

FIG.4is an example second implementation400of the IC package106ofFIGS.1,2A, and2B. The example second implementation400ofFIG.4is similar to the example first implementation300ofFIG.3. However, the example second implementation400further includes an example IHS402(e.g., a package lid) enclosing the semiconductor die302. The example IHS402includes an example outer surface404that interfaces with the heatsink102(instead of the semiconductor die302being directly coupled (e.g., within or without a thermal interface material) to the heatsink102as inFIG.3) when the heatsink102is coupled to the IC package106(FIG.2B). In other words, the example IHS402separates the semiconductor die302from the heatsink102. The example IHS402conducts heat from the package substrate304and into the heatsink102when the heatsink102is coupled to the IC package106(FIG.2B). In some instances, a thermal interface material (TIM) is disposed between the IHS402and the heatsink102to facilitate heat transfer therebetween. Further, in some examples, a TIM can also be used between the IHS402and the heatsink102.

Further, a portion of the IHS402extends across the surface306of the package substrate304to separate the dampener120from the package substrate304. For example, the portion of the IHS402may be an example ledge406(e.g., step, protrusion, etc.) that is recessed relative to the outer surface404. The example dampener120is positioned on the ledge406. As such, the dampener120is positioned (e.g., elevated) by the ledge406to interface with the heatsink102when the heatsink102is coupled to the IC package106. Further, the example dampener120extends farther away from the package substrate304than the outer surface404is from the package substrate304(e.g., in the disassembled position ofFIG.2A). Accordingly, the example dampener120is held in compression (e.g., squeezed) between the IHS402(e.g., the ledge406of the IHS402) and the heatsink102when the heatsink102is coupled to the IC package106(FIG.2B). In some examples, the dampener120is coupled to the HIS404via an adhesive (e.g., an epoxy, a liquid adhesive, double sided tape, etc.).

FIG.5is an example third implementation500of the IC package106ofFIGS.1,2A, and2B. The example third implementation500ofFIG.5is similar to the example first implementation300ofFIG.3. However, the example third implementation500ofFIG.5further includes an example stiffener502on the surface306of the package substrate304. In the example ofFIG.5, the stiffener502is positioned between the dampener120and the package substrate304.

FIG.6is an example fourth implementation600of the example IC package106ofFIGS.1,2A, and2B. The example IC package106in the fourth implementation600inFIG.6is in contact with lateral sides of the dampener120. Any of the components described in connection withFIGS.3-5may be included in the fourth implementation600ofFIG.6. For example, the dampener120inFIG.6can contact the side312of the semiconductor die302. Further, the dampener120inFIG.6can contact the side312of the semiconductor die302and the stiffener502. Additionally, the dampener120inFIG.6can contact a side of the IHS402. Further, as shown inFIG.4, the dampener120is spaced apart from (e.g., laterally inset relative to) an outer edge408of the IHS402. However, in other examples, as shown inFIG.6, the dampener120extends out to (e.g., is flush with and/or extends laterally beyond) the outer edge408of the IHS402. Additionally or alternatively, in some examples, the dampener120extends out to (e.g., is flush with and/or extends laterally beyond) an outer edge602of the package substrate304. In other examples, the dampener120is spaced apart from (e.g., laterally inset relative to) the outer edge602of the package substrate304.

FIGS.7A-7Iare top views of different example implementations of the example package substrate304, the example dampener120, the example IC package106, and the example IHS402. More particularly, the examples ofFIGS.7A-7Iillustrate orientations, positions, locations, patterns, etc., of the example dampener120(and/or other example dampers) relative to the example IC package106. For purposes of explanation, the examples ofFIGS.7A-7Iare described in connection with the second implementation400(including the IHS402) and the fourth implementation600(having the dampener120in contact with a side of the IHS402). However, any of the example implementations300,400,500,600may be altered to demonstrate the examples ofFIGS.7A-7I.

Turning toFIG.7A, the example dampener120is positioned at a perimeter of the IHS402. In the example ofFIG.7, the perimeter of the IHS402has a generally rectangular shape. Accordingly, the orientation of the dampener120also has a generally rectangular shape. Further, in the example ofFIG.7A, the dampener120is positioned on the ledge406such that the ledge406is covered by the dampener120. In other words, the dampener120surrounds (e.g., completely surrounds, extend continuously around) the IHS402by extending along the ledge406. If, for example, the IC package106does not include the IHS402(FIG.3and/orFIG.5), the dampener120can surround the semiconductor die302on the surface306(FIG.3) of the package substrate304. For example, the dampener120can be positioned at a perimeter of the package substrate304(e.g., having a generally rectangular shape).

InFIG.7B, a plurality of example dampeners700,702are positioned at different locations around the IC package106. For example, the dampener700and the dampener702are positioned at different locations on the ledge406of the IHS402. The example dampener700is positioned adjacent (e.g., at) a first corner704of the IHS402and the example dampener702is positioned adjacent a second corner706of the IHS402. As such, the example dampener700and the dampener702are spaced apart from one another on the ledge406. Further, the example dampener700and the dampener702at least partially surround the semiconductor die302that is underneath the IHS402. In other examples, the dampener700and the dampener702can surround (e.g., partially surround) the semiconductor die302on the surface306of the package substrate304(e.g., in examples where the IHS402is removed such asFIG.3,FIG.5, etc.). For example, the dampener700may be positioned adjacent a first corner of the package substrate304and the dampener702may be positioned adjacent a second corner of the package substrate304. In the example ofFIG.7B, the two dampeners700,702are shown. However, the example IC package106may have any number of associated dampeners (e.g., at least 2, 3, 4, 10, etc.). As such, multiple ones of the dampeners700,702may be spaced apart from one another on the ledge406to surround the IHS402(e.g., and the underlying semiconductor die302). Similarly, multiple ones of the dampeners700,702may be spaced apart from one another on the surface306of the package substrate304to surround the semiconductor die302. Alternatively, one of the dampeners700,702may be removed and/or otherwise excluded (seeFIG.7Chaving only the dampener700).

InFIG.7D, example dampeners708,710are positioned at different locations around the IC package106. For example, the dampener708and the dampener710are positioned at different locations on the ledge406of the IHS402. The example dampener708is positioned adjacent a side712of the IHS402and spaced apart from the first corner704and a third corner714of the IHS402. Similarly, the example dampener710is positioned adjacent another side716of the IHS402and spaced apart from the second corner706and a fourth corner718of the IHS402. In some examples, the dampeners708,710are positioned relative to the semiconductor die302. For example, the dampener708is adjacent a side of the semiconductor die302and spaced apart from a corner of the semiconductor die302.

FIG.7Dincludes the two dampeners708,710. However, one of the dampeners708,710may be removed (seeFIG.7Eincluding only the dampener708). Alternatively, additional dampeners may be positioned on other sides720,722of the IHS402such that the underlying semiconductor die302is surrounded by 4 dampeners, one on each of the sides712,716,720,722. InFIG.7F, example dampener724is positioned adjacent the third corner714and spaced apart from the side712of the IHS402. The dampener724may be positioned adjacent a corner of the semiconductor die302and spaced apart from a side of the semiconductor die302. Further, additional dampers may be positioned adjacent the other corners704,706,718(seeFIG.7Gincluding four dampeners724,726,728,730adjacent the corners704,706,714,718). The example dampeners708,710,724,726,728,730ofFIGS.7D-7Gexhibit a generally cubical shape.

FIG.7Hincludes example dampeners732,734. The example dampeners732,734ofFIG.7Hare similar to the example dampeners708,710ofFIG.7D. However, the example dampeners732,734are different in size and shape than the example dampeners708,710. For example, the dampener732extends a first length across the side712of the IHS402, whereas the dampener708extends a second length across the side716, the second length less than the first length. As such, the example dampener732exhibits a generally rectangular prismatic shape (different from the generally cubical shape of the dampener708ofFIG.7D). The example dampener734extends a third length across the side716of the IHS402, the third length less than the first length and greater than the second length. As such, the example dampener734also exhibits a generally rectangular prismatic shape. Further, any of the example dampeners disclosed herein (e.g., the dampener120, the dampeners700,702,708,710,724,726,728,730732,734) can extend any length across the ledge406, the surface306, etc.FIG.7Hincludes the two dampeners732,734. However, one of the dampeners732,734may be removed (seeFIG.7Iincluding only the dampener732). Alternatively, additional dampeners may be positioned on the other sides720,722of the IHS402such that the underlying semiconductor die302is surrounded by 4 dampeners.

The example IC package106(in any of the example implementations300,400,500,600) disclosed herein may be included in any suitable electronic component.FIGS.8-11illustrate various examples of apparatus that may include or be included in the IC package106(in any of the example implementations300,400,500,600) disclosed herein.FIG.8is a top view of a wafer800and dies802that may be included in the IC package106(e.g., as the die302). The wafer800includes semiconductor material and one or more dies802having circuitry. Each of the dies802may be a repeating unit of a semiconductor product. After the fabrication of the semiconductor product is complete, the wafer800may undergo a singulation process in which the dies802are separated from one another to provide discrete “chips.” The die802includes one or more transistors (e.g., some of the transistors940ofFIG.9, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and/or other circuitry), and/or any other components. In some examples, the die802may include and/or implement a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuitry or electronics. Multiple ones of these devices may be combined on a single die802. For example, a memory array of multiple memory circuits may be formed on a same die802as programmable circuitry (e.g., the programmably circuitry1102ofFIG.11) and/or other logic circuitry. Such memory may store information for use by the programmable circuitry. The example IC package106(in any of the example implementations300,400,500,600) disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies are attached to a wafer800that includes others of the dies, and the wafer800is subsequently singulated.

FIG.9is a cross-sectional side view of an IC device900that may be included in the example IC package106(in any of the example implementations300,400,500,600) (e.g., in the die302). One or more of the IC devices900may be included in one or more dies802(FIG.8). The IC device900may be formed on a die substrate902(e.g., the wafer800ofFIG.8) and may be included in a die (e.g., the die802ofFIG.8). The die substrate902may be a semiconductor substrate including semiconductor materials including, for example, n-type or p-type materials systems (or a combination of both). The die substrate902may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate902may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate902. Although a few examples of materials from which the die substrate902may be formed are described here, any material that may serve as a foundation for an IC device900may be used. The die substrate902may be part of a singulated die (e.g., the dies802ofFIG.8) or a wafer (e.g., the wafer800ofFIG.8).

The IC device900may include one or more device layers904disposed on and/or above the die substrate902. The device layer904may include features of one or more transistors940(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate902. The device layer904may include, for example, one or more source and/or drain (S/D) regions920, a gate922to control current flow between the S/D regions920, and one or more S/D contacts924to route electrical signals to/from the S/D regions920. The transistors940may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors940are not limited to the type and configuration depicted inFIG.9and may include a wide variety of other types and/or configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

In some examples, when viewed as a cross-section of the transistor940along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel (e.g., within 5 degrees) to the surface of the die substrate902and two sidewall portions that are substantially perpendicular (e.g., within 5 degrees) to the top surface of the die substrate902. In other examples, at least one of the metal layers that form the gate electrode may be a planar layer that is substantially parallel to the top surface of the die substrate902and does not include sidewall portions substantially perpendicular to the top surface of the die substrate902. In other examples, the gate electrode may include a combination of U-shaped structures and/or planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

The S/D regions920may be formed within the die substrate902adjacent to the gate922of corresponding transistor(s)940. The S/D regions920may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate902to form the S/D regions920. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate902may follow the ion-implantation process. In the latter process, the die substrate902may first be etched to form recesses at the locations of the S/D regions920. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions920. In some implementations, the S/D regions920may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions920may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions920.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors940) of the device layer904through one or more interconnect layers disposed on the device layer904(illustrated inFIG.9as interconnect layers906-910). For example, electrically conductive features of the device layer904(e.g., the gate922and the S/D contacts924) may be electrically coupled with the interconnect structures928of the interconnect layers906-910. The one or more interconnect layers906-910may form a metallization stack (also referred to as an “ILD stack”)2019of the IC device900.

The interconnect structures928may be arranged within the interconnect layers906-910to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures928depicted inFIG.9). Although a particular number of interconnect layers906-910is depicted inFIG.9, examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some examples, the interconnect structures928may include lines928aand/or vias928bfilled with an electrically conductive material such as a metal. The lines928amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate902upon which the device layer904is formed. For example, the lines928amay route electrical signals in a direction in and/or out of the page from the perspective ofFIG.9. The vias928bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate902upon which the device layer904is formed. In some examples, the vias928bmay electrically couple lines928aof different interconnect layers906-910together.

The interconnect layers906-910may include a dielectric material926disposed between the interconnect structures928, as shown inFIG.9. In some examples, the dielectric material926disposed between the interconnect structures928in different ones of the interconnect layers906-910may have different compositions; in other examples, the composition of the dielectric material926between different interconnect layers906-910may be the same.

A first interconnect layer906(referred to as Metal 1 or “M1”) may be formed directly on the device layer904. In some examples, the first interconnect layer906may include lines928aand/or vias928b,as shown. The lines928aof the first interconnect layer906may be coupled with contacts (e.g., the S/D contacts924) of the device layer904.

A second interconnect layer908(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer906. In some examples, the second interconnect layer908may include vias928bto couple the lines928aof the second interconnect layer908with the lines928aof the first interconnect layer906. Although the lines928aand the vias928bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer908) for the sake of clarity, the lines928aand the vias928bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.

A third interconnect layer910(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer908according to similar techniques and/or configurations described in connection with the second interconnect layer908or the first interconnect layer906. In some examples, the interconnect layers that are “higher up” in the metallization stack919in the IC device900(i.e., further away from the device layer904) may be thicker.

The IC device900may include a solder resist material934(e.g., polyimide or similar material) and one or more conductive contacts936formed on the interconnect layers906-910. InFIG.9, the conductive contacts936are illustrated as taking the form of bond pads. The conductive contacts936may be electrically coupled with the interconnect structures928and configured to route the electrical signals of the transistor(s)940to other external devices. For example, solder bonds may be formed on the one or more conductive contacts936to mechanically and/or electrically couple a chip including the IC device900with another component (e.g., a circuit board). The IC device900may include additional or alternate structures to route the electrical signals from the interconnect layers906-910; for example, the conductive contacts936may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG.10is a cross-sectional side view of an IC device assembly1000that may include the IC package106(in any of the example implementations300,400,500,600) disclosed herein. In some examples, the IC device assembly corresponds to the IC package106(in any of the example implementations300,400,500,600). The IC device assembly1000includes a number of components disposed on a circuit board1002(which may be, for example, a motherboard). The IC device assembly1000includes components disposed on a first face1040of the circuit board1002and an opposing second face1042of the circuit board1002; generally, components may be disposed on one or both faces1040and1042. Any of the IC packages discussed below with reference to the IC device assembly1000may take the form of the example IC package106(in any of the example implementations300,400,500,600).

The IC device assembly1000illustrated inFIG.10includes a package-on-interposer structure1036coupled to the first face1040of the circuit board1002by coupling components1016. The coupling components1016may electrically and mechanically couple the package-on-interposer structure1036to the circuit board1002, and may include solder balls (as shown inFIG.10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1036may include an IC package1020coupled to an interposer1004by coupling components1018. The coupling components1018may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1016. Although a single IC package1020is shown inFIG.10, multiple IC packages may be coupled to the interposer1004; indeed, additional interposers may be coupled to the interposer1004. The interposer1004may provide an intervening substrate used to bridge the circuit board1002and the IC package1020. The IC package1020may be or include, for example, a die (the die802ofFIG.8), an IC device (e.g., the IC device900ofFIG.9), or any other suitable component. Generally, the interposer1004may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1004may couple the IC package1020(e.g., a die) to a set of BGA conductive contacts of the coupling components1016for coupling to the circuit board1002. In the example illustrated inFIG.10, the IC package1020and the circuit board1002are attached to opposing sides of the interposer1004; in other examples, the IC package1020and the circuit board1002may be attached to a same side of the interposer1004. In some examples, three or more components may be interconnected by way of the interposer1004.

The IC device assembly1000may include an IC package1024coupled to the first face1040of the circuit board1002by coupling components1010. The coupling components1010may take the form of any of the examples discussed above with reference to the coupling components1016, and the IC package1024may take the form of any of the examples discussed above with reference to the IC package1020.

The IC device assembly1000illustrated inFIG.10includes a package-on-package structure1034coupled to the second face1042of the circuit board1002by coupling components1028. The package-on-package structure1034may include a first IC package1026and a second IC package1032coupled together by coupling components1030such that the first IC package1026is disposed between the circuit board1002and the second IC package1032. The coupling components1028,1030may take the form of any of the examples of the coupling components1016discussed above, and the IC packages1026,1032may take the form of any of the examples of the IC package1020discussed above. The package-on-package structure1034may be configured in accordance with any of the package-on-package structures known in the art.

FIG.11is a block diagram of an example electrical device1100that may include one or more of the example IC package106(in any of the example implementations300,400,500,600). For example, any suitable ones of the components of the electrical device1100may include one or more of the device assemblies1000, IC devices900, or dies802disclosed herein, and may be arranged in the example IC package106(in any of the example implementations300,400,500,600). A number of components are illustrated inFIG.11as included in the electrical device1100, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some examples, some or all of the components included in the electrical device1100may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various examples, the electrical device1100may not include one or more of the components illustrated inFIG.11, but the electrical device1100may include interface circuitry for coupling to the one or more components. For example, the electrical device1100may not include a display1106, but may include display interface circuitry (e.g., a connector and driver circuitry) to which a display1106may be coupled. In another set of examples, the electrical device1100may not include an audio input device1118(e.g., microphone) or an audio output device1108(e.g., a speaker, a headset, earbuds, etc.), but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1118or audio output device1108may be coupled.

The electrical device1100may include programmable circuitry1102(e.g., one or more processing devices). The programmable circuitry1102may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device1100may include a memory1104, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory1104may include memory that shares a die with the programmable circuitry1102. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some examples, the electrical device1100may include a communication chip1112(e.g., one or more communication chips). For example, the communication chip1112may be configured for managing wireless communications for the transfer of data to and from the electrical device1100. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.

The electrical device1100may include battery/power circuitry1114. The battery/power circuitry1114may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1100to an energy source separate from the electrical device1100(e.g., AC line power).

The electrical device1100may include a display1106(or corresponding interface circuitry, as discussed above). The display1106may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1100may include an audio output device1108(or corresponding interface circuitry, as discussed above). The audio output device1108may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1100may include an audio input device1118(or corresponding interface circuitry, as discussed above). The audio input device1118may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1100may include GPS circuitry1116. The GPS circuitry1116may be in communication with a satellite-based system and may receive a location of the electrical device1100, as known in the art.

The electrical device1100may include any other output device1110(or corresponding interface circuitry, as discussed above). Examples of the other output device1110may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.

From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that provide dampeners (e.g., dampening bodies, compressibly resilient materials, etc.) for use in socket-based architectures to mitigate risk of damage to pad surfaces. Examples disclosed herein position dampeners to resist movement of an example socket substrate and, thus, associated pins. For example, disclosed examples include dampeners that are positioned to interface with an example heatsink to resist movement of such a substrate. Accordingly, examples disclosed herein reduce and/or eliminate fretting on pad surfaces by dampening vibrations in an associated IC package. Examples disclosed herein improve the electrical connectivity in such an IC package by increasing the number of socket pins and mitigating fretting between the socket pins and any associated pad surfaces.

Example 1 includes an apparatus comprising a substrate, a semiconductor die carried by the substrate, and a dampener carried by the substrate, the dampener dimensioned to interface with a heatsink when the heatsink is thermally coupled to the semiconductor die.

Example 2 includes the apparatus of example 1, further including an integrated heat spreader enclosing the semiconductor die, the dampener coupled to the integrated heat spreader.

Example 3 includes the apparatus of any of example 1 or example 2, wherein the dampener is positioned at a perimeter of the integrated heat spreader.

Example 4 includes the apparatus of any of examples 1-3, wherein the integrated heat spreader includes a ledge that is recessed relative to an outer surface of the integrated heat spreader, the outer surface to interface with the heatsink, the dampener positioned on the ledge.

Example 5 includes the apparatus of any of examples 1-4, wherein the dampener extends farther away from the substrate than the outer surface of the integrated heat spreader is from the substrate.

Example 6 includes the apparatus of any of examples 1-5, wherein the dampener is positioned adjacent a side of the semiconductor die and spaced apart from a corner of the semiconductor die.

Example 7 includes the apparatus of any of examples 1-6, wherein the dampener is positioned adjacent a corner of the semiconductor die and spaced apart from a side of the semiconductor die.

Example 8 includes the apparatus of any of examples 1-7, wherein the dampener is coupled directly to the substrate via an adhesive.

Example 9 includes the apparatus of any of examples 1-8, wherein the semiconductor die is a bare die exposed on the substrate, a backside of the semiconductor die faces away from the substrate, and the dampener extends farther away from the substrate than the backside of the semiconductor die.

Example 10 includes the apparatus of any of examples 1-9, wherein substrate includes a first surface and a second surface opposite the first surface, the semiconductor die and the dampener on the first surface of the substrate.

Example 11 includes the apparatus of any of examples 1-10, further including a stiffener on the first surface of the substrate, the stiffener between the dampener and the substrate.

Example 12 includes the apparatus of any of examples 1-11, wherein the second surface of the substrate includes a ball grid array or a land grid array.

Example 13 includes the apparatus of any of examples 1-12, wherein the substrate is an interposer and the apparatus further includes a package substrate interconnecting the semiconductor die and the interposer.

Example 14 includes the apparatus of any of examples 1-14, wherein the dampener includes at least one of a foam, silicone, or polyurethane.

Example 15 includes an integrated circuit (IC) package comprising a substrate, a semiconductor die supported on a side of the substrate, and a compressibly resilient material supported on the side of the substrate, the compressibly resilient material laterally offset from the semiconductor die along the side of the substrate, the compressibly resilient material to resist movement of a heatsink relative to the semiconductor die when the heatsink is thermally coupled to the semiconductor die.

Example 16 includes the IC package of example 15, wherein the compressibly resilient material is to be held in compression between the substrate and the heatsink when the heatsink is thermally coupled to the semiconductor die.

Example 17 includes the IC package of any of example 15 or example 16, further including an integrated heat spreader separating the semiconductor die from the heatsink, wherein a portion of the integrated heat spreader extends across the side of the substrate to separate the compressibly resilient material from the substrate.

Example 18 includes an apparatus comprising a package substrate having a surface to support a semiconductor die, a heatsink coupled to the semiconductor die, and a dampening body compressed between the heatsink and the surface of the semiconductor substrate.

Example 19 includes the apparatus of example 18, wherein the dampening body surrounds the semiconductor die on the surface of the semiconductor substrate.

Example 20 includes the apparatus of any of example 18 or example 19, wherein the dampening body is one of at least two dampening bodies, the at least two dampening bodies spaced apart from one another to surround the semiconductor die on the surface of the semiconductor substrate.