A semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0045257 filed on Apr. 6, 2023, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments relate to an electronic device and a method of manufacturing an electronic device and, more particularly, to a semiconductor device and a method of manufacturing a semiconductor device.

2. Related Art

The degree of integration of semiconductor devices is basically determined by the area that is occupied by a unit memory cell. As the improvement of the degree of integration of semiconductor devices in which a memory cell is formed on a substrate as a single layer recently reaches its limit, a three-dimensional semiconductor device in which memory cells are stacked on a substrate is proposed. Furthermore, in order to improve operation reliability of such a semiconductor device, various structures and manufacturing methods are developed.

SUMMARY

In an embodiment, a semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.

In an embodiment, a method of manufacturing a semiconductor device may include forming a first contact plug, forming a word line connected to the first contact plug and extending in a first direction, forming a second contact plug, forming a separation insulating layer on the second contact plug, forming a first opening within the word line, forming a second opening that exposes the second contact plug through the separation insulating layer, and forming a bit line including a first protruding part extending in a second direction and disposed within the first opening, a second protruding part disposed within the second opening, and a connection part connecting the first protruding part and the second protruding part, the second direction intersecting the first direction.

DETAILED DESCRIPTION

Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing a semiconductor device.

According to the present technology, the semiconductor device having a stable structure and improved reliability can be provided.

FIGS.1A to1Care diagrams for describing a semiconductor device according to an embodiment of the present disclosure.FIG.1Amay be a plan view of the semiconductor device.FIG.1Bmay be a cross-sectional view taken along line A-A′ inFIG.1A.FIG.1Cmay be a cross-sectional view taken along line B-B′ inFIG.1A.

Referring toFIGS.1A to1C, the semiconductor device may include one or more of a word line120, a bit line180, and memory cells MC. The semiconductor device may further include one or more of a first contact plug110, a second contact plug130, a separation insulating layer140, a first interlayer insulating layer IL1, and a second interlayer insulating layer IL2. The bit line180may include one or more of a first conductive layer181, a barrier layer182, and a second conductive layer183.

The word lines120may be disposed on the first contact plug110, and may extend in a first direction I. The word lines120may be spaced apart from each other and arranged in a second direction II that intersects the first direction I. Each of the word lines120may be electrically connected to the first contact plug110.

The first contact plug110may be disposed within the first interlayer insulating layer IL1. The sidewall of the first contact plug110may be surrounded by a barrier layer111. The first interlayer insulating layer IL1may be disposed below the word lines120. The second contact plug130may be disposed within the first interlayer insulating layer IL1. The second interlayer insulating layer IL2may be disposed on the word lines120. The first contact plug110and the second contact plug130may include a conductive material, such as tungsten or titanium. In this case, the first interlayer insulating layer IL1and the second interlayer insulating layer IL2may be a multi-layer. The first interlayer insulating layer IL1and the second interlayer insulating layer IL2may include an insulating material, such as oxide or nitride.

The separation insulating layer140may be disposed on the second contact plug130. The separation insulating layers140may be disposed within the first interlayer insulating layer IL1and the second interlayer insulating layer IL2. The separation insulating layer140may separate the word lines120that extend in the first direction I from each other. The separation insulating layer140may include an insulating material, such as oxide or nitride. For example, the separation insulating layer140may include tetra ethyl ortho silicate (TEOS) oxide.

The memory cell MC may include a variable resistance layer150. For example, the memory cell MC may include a portion of the variable resistance layer150disposed therein. The memory cell MC may further include an electrode layer160. The memory cell MC may be disposed between the word line120and the bit line180. The memory cell MC may be disposed within the first interlayer insulating layer IL1and the second interlayer insulating layer IL2. For example, the memory cell MC may protrude into the first interlayer insulating layer IL1. The memory cells MC that are adjacent to each other in the second direction II may be connected. For example, the variable resistance layers150and electrode layers160of the respective memory cells MC may extend in the second direction II, and may be connected.

The variable resistance layer150may be disposed to come into contact with the word line120, or an electrode layer may be additionally disposed between the variable resistance layer150and the word line120. The variable resistance layer150may be a switching material or a phase change material. For example, the variable resistance layer150may include a chalcogenide material. The electrode layer160may be disposed within the variable resistance layer150. The electrode layer160may include metal, metal nitride, carbon, or carbon nitride.

The bit lines180may be disposed over the word lines120. The bit lines180may extend in the second direction II. Each of the bit lines180may include a first protruding part180P1, a second protruding part180P2, and a connection part180P3that connects the first protruding part180P1and the second protruding part180P2and that extends in the second direction II. For example, the bit line180may include the first protruding part180P1that protrudes into the variable resistance layer150, the second protruding part180P2that is connected to the second contact plug130, and the connection part180P3.

The first protruding part180P1may protrude into the memory cell MC. The first protruding part180P1may protrude into the variable resistance layer150. The first protruding part180P1may extend through the word line120, and may play a role as a vertical bit line that intersects the word line120. The sidewall and bottom of the first protruding part180P1may be surrounded by the variable resistance layer150. The first protruding part180P1may include a first conductive layer181, a barrier layer182within the first conductive layer181, and a second conductive layer183within the barrier layer182. For example, the first protruding part180P1may include a first portion of the first conductive layer181disposed within the memory cell MC, a first portion of the barrier layer182disposed within the first portion of the first conductive layer181, and a first portion of the second conductive layer183disposed within the first portion of the barrier layer182. The electrode layer160may be disposed between the first protruding part180P1and the variable resistance layer150. The first conductive layer181and the second conductive layer183may each include a conductive material, such as tungsten or titanium. The barrier layer182may include metal nitride, such as tungsten nitride (WN) or titanium nitride (TIN). The barrier layer182can increase adhesive strength between the first conductive layer181and the second conductive layer183.

The second protruding part180P2may extend through the separation insulating layer140, and may be electrically connected to the second contact plug130. The second protruding part180P2may include the barrier layer182and the second conductive layer183within the barrier layer182. For example, the second protruding part180P2may include a second portion of the barrier layer182protruding into the electrode layer160, the variable resistance layer150, and the separation insulating layer140. The second protruding part180P2may further include a second portion of the second conductive layer183disposed within the second portion of the barrier layer182. The second protruding part180P2may play a role as a contact plug that connects the connection part180P3and the second contact plug130.

The connection part180P3may include the first conductive layer181, the barrier layer182on the first conductive layer181, and the second conductive layer183on the barrier layer182. For example, the connection part180P3may include a second portion of the first conductive layer181, a third portion of the barrier layer182disposed on the second portion of the first conductive layer181, and a third portion of the second conductive layer183disposed on the third portion of the barrier layer182.

The first protruding part180P1, the second protruding part180P2, and the third protruding part180P3may be formed by using the same process. The first conductive layer181of the first protruding part180P1and the first conductive layer181of the connection part180P3may be a single layer. For example, the first portion of the first conductive layer181in the first protruding part180P1and the second portion of the first conductive layer181in the connection part180P3may be formed as portions of a single layer using the same process. The barrier layer182of the first protruding part180P1, the barrier layer182of the second protruding part180P2, and the barrier layer182of the connection part180P3may be a single layer. For example, the first portion of the barrier layer182in the first protruding part180P1, the second portion of the barrier layer182in the second protruding part180P2, and the third portion of the barrier layer182in the connection part180P3may be formed as portions of a single layer using the same process. The second conductive layer183of the first protruding part180P1, the second conductive layer183of the second protruding part180P2, and the second conductive layer183of the connection part180P3may be a single layer. For example, the first portion of the second conductive layer183in the first protruding part180P1, the second portion of the second conductive layer183in the second protruding part180P2, and the third portion of the second conductive layer183in the connection part180P3may be formed as portions of a single layer using the same process.

According to the aforementioned structure, the bit line180may include the first protruding part180P1, the second protruding part180P2, and the connection part180P3that connects the first protruding part180P1and the second protruding part180P2.

FIGS.2A to2C,3A to3C,4A to4C,5A to5C,6A to6C, and7A to7Care diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.FIGS.2A,3A,4A,5A,6A, and7Amay be plan views of the semiconductor device.FIGS.2B,3B,4B,5B,6B, and7Bmay be cross-sectional views taken along line A-A′ inFIG.2A.FIGS.2C,3C,4C,5C,6C, and7Cmay be cross-sectional views taken along line B-B′ inFIG.2A. Hereinafter, contents that are redundant with the aforementioned contents may be omitted for the interest of brevity.

Referring toFIGS.2A to2C, a first contact plug210may be formed. The first contact plug210may be formed within a first interlayer insulating layer IL1. A barrier layer211may be formed on the sidewall of the first contact plug210. The first contact plug210may include a conductive material, such as tungsten or titanium.

A second contact plug230may be formed. The second contact plug230may be formed within the first interlayer insulating layer IL1. When the first contact plug210is formed, the second contact plug230may be formed. The second contact plug230may include a conductive material, such as tungsten or titanium.

Next, a word line220may be formed on the first interlayer insulating layer IL1. The word line220may be connected to the first contact plug210and may extend in a first direction I.

Next, a second interlayer insulating layer IL2may be formed. The second interlayer insulating layer IL2may be a single layer or a multi-layer. For example, the second interlayer insulating layer IL2may be formed by sequentially stacking a first insulating layer IL21, a second insulating layer IL22, and a third insulating layer IL23. The second interlayer insulating layer IL2may include an insulating material, such as oxide or nitride. For example, the first insulating layer IL21may include nitride, the second insulating layer IL22may include tetra ethyl ortho silicate (TEOS) oxide, and the third insulating layer IL23may include nitride.

Next, a separation insulating layer240may be formed. For example, a trench may be formed by etching the second interlayer insulating layer IL2and a conductive layer for a word line. The separation insulating layer240may be formed within the trench. Accordingly, the word line220may be formed. The word line220may be connected to the first contact plug210, and may extend in the first direction I.

The separation insulating layer240may be disposed on the second contact plug230. The separation insulating layer240may be disposed within the second interlayer insulating layer IL2and the word line220, and may extend into the first interlayer insulating layer IL1. The separation insulating layer240may separate the word lines220that extend in the first direction I from each other. The separation insulating layer240may include an insulating material, such as oxide or nitride. For example, the separation insulating layer240may include TEOS oxide.

Referring toFIGS.3A to3C, a first opening OP1may be formed within the word line220. The first opening OP1may be formed within the second interlayer insulating layer IL2and the word line220, and may extend into the first interlayer insulating layer IL1through the word line220. The first opening OP1may be disposed between the separation insulating layers240that are adjacent to each other in a second direction II that intersects a first direction I.

Referring toFIGS.4A to4C, a memory cell MC may be formed. The memory cell MC may include a variable resistance layer250. The memory cell MC may further include an electrode layer260. First, the variable resistance layer250may be formed within the first opening OP1. The variable resistance layer250may be formed along the inner side of the first opening OP1so that the first opening OP1is partially opened. For example, the variable resistance layer250may be formed along the inner side of the first opening OP1with a thickness sufficient to partially fill the first opening OP1, rather than substantially completely filling the first opening OP1. The variable resistance layer250may include a chalcogenide material. Next, the electrode layer260may be formed within the variable resistance layer250. The electrode layer260may be formed along the inner side of the variable resistance layer250so that the first opening OP1is partially opened. The electrode layer260may include metal, metal nitride, carbon, or carbon nitride. Accordingly, the memory cell MC that includes the variable resistance layer250and the electrode layer260may be formed. For example, the memory cell MC includes a portion of the variable resistance layer250disposed within the first opening OP1and a portion of the electrode layer260disposed within the portion of the variable resistance layer250.

Next, a first conductive layer281may be formed within the first opening OP1. The first conductive layer281may be formed along the inner side of the first opening OP1so that the first opening OP1is partially opened. Specifically, the first conductive layer281may be formed along the inner side of the first opening OP1with a thickness sufficient to partially fill the first opening OP1, rather than substantially completely filling the first opening OP1. For example, the first conductive layer281may be formed along the electrode layer260within the first opening OP1. The first conductive layer281may be a multi-layer. For example, the first conductive layer281may include a barrier layer and a metal layer. In this case, the barrier layer can increase adhesive strength between the electrode layer260and the first conductive layer281. The first conductive layer281may include a conductive material (e.g., tungsten or titanium), or metal nitride (e.g., tungsten nitride (WN) or tungsten nitride (TiN)), or both.

Although the memory cell MC and the first conductive layer281are formed, additional structures may be formed within the first opening OP1in a subsequent process because the state in which the first opening OP1has been opened is maintained.

Referring toFIGS.5A to5C, a second opening OP2may be formed. First, a hard mask HM may be formed on the first conductive layer281. Next, the second opening OP2may be formed by etching the first conductive layer281, the memory cell MC, and the separation insulating layer240by using the hard mask HM as an etch barrier. The second opening OP2may expose the second contact plug230through the separation insulating layer240. The second opening OP2may be formed in the state in which the first opening OP1has been at least partially opened. In other words, the hard mask HM may be formed along the inner side of the first conductive layer281so that the first opening OP1is partially filled. For example, each of portions of the variable resistance layer250, the electrode layer260, the first conductive layer281, and the hard mask HM that are disposed within the first opening OP1has a thickness sufficient to partially fill the first opening OP1, rather than substantially completely filling the first opening OP1. The hard mask HM may be removed after the second opening OP2is formed. The hard mask HM may partially remain within the first opening OP1without being removed. In the process of removing the hard mask HM, a part of the first conductive layer281may be removed, but the variable resistance layer250might not be exposed. Accordingly, the first conductive layer281can prevent the variable resistance layer250from being damaged or can minimize damage to the variable resistance layer250.

Although the hard mask HM is formed, the state in which the first opening OP1has been opened may be maintained. The first opening OP1is enlarged by removing the hard mask HM after the second opening OP2is formed. Accordingly, in a subsequent process, a second conductive layer can be formed within the first opening OP1and the second opening OP2.

Referring toFIGS.6A to6C, a second conductive layer283may be formed. The second conductive layer283may be formed along the inner sides of the first opening OP1and the second opening OP2. In this case, the first opening OP1and the second opening OP2may be substantially completely filled with the second conductive layer283so that an opened area is not substantially present. Accordingly, the second conductive layer283may protrude into the memory cell MC, and may protrude into the separation insulating layer240through the word line220.

Before the second conductive layer283is formed, a barrier layer282may be formed. The barrier layer282may be formed between the first conductive layer281and the second conductive layer283, and can increase adhesive strength between the first conductive layer281and the second conductive layer283. The barrier layer282may include metal nitride, such as tungsten nitride (WN) or titanium nitride (TiN).

Referring toFIGS.7A to7C, a bit line280that extends in a second direction II may be formed. For example, the bit lines280may be formed by patterning the second conductive layer283, the barrier layer282, and the first conductive layer281. The bit line280, including a first protruding part280P1, a second protruding part280P2, and a connection part280P3that connects the first protruding part280P1and the second protruding part280P2and that extends in the second direction II, may be formed.

In this case, the first protruding part180P1may include a first conductive layer281, a barrier layer282within the first conductive layer281, and a second conductive layer283within the barrier layer282. The electrode layer260may be disposed between the first protruding part280P1and the variable resistance layer250. The first conductive layer281and the second conductive layer283may each include a conductive material, such as tungsten or titanium. The barrier layer282may include metal nitride, such as tungsten nitride (WN) or titanium nitride (TiN). The barrier layer282can increase adhesive strength between the first conductive layer281and the second conductive layer283.

The second protruding part180P2may extend through the separation insulating layer240, and may be electrically connected to the second contact plug230. The second protruding part280P2may include the barrier layer282and the second conductive layer283within the barrier layer282. The second protruding part280P2may play a role as a contact plug that connects the connection part280P3and the second contact plug230.

The connection part280P3may include the first conductive layer281, the barrier layer282on the first conductive layer281, and the second conductive layer283on the barrier layer282.

According to the aforementioned process, in depositing the conductive layers for forming the bit line280, the conductive layers may be divided and deposited plural times. For example, the bit line280includes the first conductive layer281, the barrier layer282, and the second conductive layer283, each of which may be formed in a separate deposition process. Accordingly, the variable resistance layer250under the conductive layers can be prevented from being damaged, such as being peeled, when the conductive layers are patterned, or damage to the variable resistance layer250when the conductive layers are patterned can be minimized. For example, since the second opening OP2is formed after the first conductive layer281is formed, damage to the variable resistance layer250in the process of etching the first conductive layer281can be reduced. Furthermore, since the bit line280is formed by patterning the second conductive layer283, the barrier layer282, and the first conductive layer281, a planarization process may be omitted to form the bit line280and damage to the variable resistance layer250can be reduced compared to a case in which such a planarization process is used.

FIGS.8A to8Care diagrams for describing a semiconductor device according to an embodiment of the present disclosure.FIG.8Amay be a plan view of the semiconductor device.FIG.8Bmay be a cross-sectional view taken along A-A′ inFIG.8A.FIG.8Cmay be a cross-sectional view taken along line B-B′ inFIG.8A. Hereinafter, contents that are redundant with the aforementioned contents may be omitted for the interest of brevity.

Referring toFIGS.8A to8C, a semiconductor device may include one or more of a word line320, a bit line380, and memory cells MC. The semiconductor device may further include one or more of a first contact plug310, a second contact plug330, a separation insulating layer340, a first interlayer insulating layer IL1, and a second interlayer insulating layer IL2. The bit line380may include one or more of a first conductive layer381, a barrier layer382, and a second conductive layer383.

The word lines320may be disposed on the first contact plug310, and may extend in a first direction I. The word lines320may be spaced apart from each other and disposed in a second direction II that intersects the first direction I. Each of the word lines320may be electrically connected to the first contact plug310.

The first contact plug310may be disposed within the first interlayer insulating layer IL1. The sidewall of the first contact plug310may be surrounded by a barrier layer311. The first interlayer insulating layer IL1may be disposed below the word lines320. The second contact plug330may be disposed within the first interlayer insulating layer IL1. The second interlayer insulating layer IL2may be disposed on the word lines320. In this case, the first interlayer insulating layer IL1and the second interlayer insulating layer IL2may be a single layer or a multi-layer.

The separation insulating layer340may be disposed on the second contact plug330. The separation insulating layer340may be disposed within the first interlayer insulating layer IL1and the second interlayer insulating layer IL2. The separation insulating layer340may separate the word lines320that extend in the first direction I from each other.

The memory cell MC may include a variable resistance layer350. The memory cell MC may further include an electrode layer360. The memory cell MC may be disposed between the word line320and the bit line380. The memory cell MC may be disposed within the first interlayer insulating layer IL1and the second interlayer insulating layer IL2. For example, the memory cell MC may protrude into the first interlayer insulating layer IL1.

The variable resistance layer350may be disposed to come into contact with the word line320, or an electrode layer may be additionally disposed between the variable resistance layer350and the word line320. The electrode layer360may be disposed within the variable resistance layer350.

The bit lines380may be disposed over the word lines320. The bit lines380may extend in a second direction II. Each of the bit lines380may include a first protruding part380P1, a second protruding part380P2, and a connection part380P3that connects the first protruding part380P1and the second protruding part380P2and that extends in the second direction II.

The first protruding part380P1may protrude into the memory cell MC. The first protruding part380P1may protrude into the variable resistance layer350. The first protruding part380P1may extend through the word line320, and may play a role as a vertical bit line that intersects the word line320. The sidewall and bottom of the first protruding part380P1may be surrounded by the variable resistance layer350. The first protruding part380P1may include the first conductive layer381that protrudes into the variable resistance layer350. For example, the first protruding part380P1may include a first portion of the first conductive layer381protruding into the memory cell MC. The electrode layer360may be disposed between the first protruding part380P1and the variable resistance layer350.

The second protruding part380P2may extend through the separation insulating layer340, and may be electrically connected to the second contact plug330. The second protruding part380P2may include the barrier layer382and the second conductive layer383within the barrier layer382. For example, the second protruding part380P2may include a first portion of the barrier layer382protruding into the electrode layer360, the variable resistance layer350, and the separation insulating layer340. The second protruding part380P2may further include a first portion of the second conductive layer383disposed within the first portion of the barrier layer182. The second protruding part380P2may play a role as a contact plug that connects the connection part380P3and the second contact plug330.

The connection part380P3may include the first conductive layer381, the barrier layer382on the first conductive layer381, and the second conductive layer383on the barrier layer382. For example, the connection part380P3may include a second portion of the first conductive layer381, a second portion of the barrier layer382disposed on the second portion of the first conductive layer381, and a second portion of the second conductive layer383disposed on the second portion of the barrier layer382. The first protruding part380P1, the second protruding part380P2, and the connection part380P3may be formed by using the same process. For example, the first portion of the second conductive layer383in the second protruding part380P2and the second portion of the second conductive layer383in the connection part380P3may be formed using the same process.

According to the aforementioned structure, the first protruding part380P1of the bit line380may include the first conductive layer381. The first conductive layer381may protrude into the variable resistance layer350.

FIGS.9A to9C,10A to10C,11A to11C, and12A to12Care diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.FIGS.9A,10A,11A, and12Amay be plan views of the semiconductor device.FIGS.9B,10B,11B, and12Bmay be cross-sectional views taken along line A-A′ inFIG.9A.FIGS.9C,10C,11C, and12Cmay be cross-sectional views taken along line B-B′ inFIG.9A. Hereinafter, contents that are redundant with the aforementioned contents may be omitted for the interest of brevity.

Referring toFIGS.9A to9C, a first contact plug410may be formed within a first interlayer insulating layer IL1. When the first contact plug410is formed, a second contact plug430may be formed within the first interlayer insulating layer IL1.

Next, a word line420that is connected to the first contact plug410may be formed on the first interlayer insulating layer IL1. Next, the second interlayer insulating layer IL2may be formed on the word line420. The second interlayer insulating layer IL2may be a single layer or a multi-layer. For example, the second interlayer insulating layer IL2may be formed by sequentially stacking a first insulating layer IL21, a second insulating layer IL22, and a third insulating layer IL23.

Next, a separation insulating layer440may be formed on the second contact plug430. For example, a trench may be formed by etching the second interlayer insulating layer IL2and a conductive layer for a word line. The separation insulating layer440may be formed within the trench. Accordingly, the word line420may be formed.

Next, a first opening OP1may be formed within the word line420. The first opening OP1may be formed within the second interlayer insulating layer IL2and the word line420, and may extend into the first interlayer insulating layer IL1through the word line420.

Next, a memory cell MC including a variable resistance layer450may be formed. The memory cell MC may further include an electrode layer460. First, the variable resistance layer450may be formed within the first opening OP1. The variable resistance layer450may be formed along the inner side of the first opening OP1so that the first opening OP1is partially opened. Next, the electrode layer460may be formed within the variable resistance layer450. The electrode layer460may be formed along the inner side of the variable resistance layer450so that the first opening OP1is partially opened. Accordingly, the memory cell MC including the variable resistance layer450and the electrode layer260may be formed. For example, the memory cell MC includes a portion of the variable resistance layer450disposed within the first opening OP1and a portion of the electrode layer460disposed within the portion of the variable resistance layer450.

Next, a first conductive layer481may be formed within the first opening OP1. For example, the first opening OP1may be filled with the first conductive layer481. Accordingly, the first conductive layer481may protrude into the memory cell MC, and may protrude into the first interlayer insulating layer IL1through the word line420. The first conductive layer481may be a single layer or a multi-layer. For example, the first conductive layer481may include a barrier layer and a metal layer.

A risk in a process can be reduced because a subsequent process can be performed in the state in which the first opening OP1has been filled with the first conductive layer481. For example, if a subsequent process is performed in the state in which the first opening OP1has been opened, roughness of the first conductive layer481may be increased in a process of depositing a hard mask HM within the first opening OP1and etching the hard mask HM. In contrast, an increase in the roughness of the first conductive layer481can be reduced by performing a subsequent process in the state in which the first opening OP1has been filled with the first conductive layer481.

Referring toFIGS.10A to10C, a second opening OP2may be formed. First, the hard mask HM may be formed on the first conductive layer481. Next, the second opening OP2may be formed by etching the first conductive layer481, the memory cell MC, and the separation insulating layer440by using the hard mask HM as an etch barrier. The second opening OP2may expose the second contact plug430through the separation insulating layer440. The hard mask HM may be removed after the second opening OP2is formed. In the process of removing the hard mask HM, a part of the first conductive layer481may be removed, but the variable resistance layer450might not be exposed. Accordingly, damage to the variable resistance layer450can be prevented. Furthermore, although the first conductive layer481is partially etched in the process of etching the hard mask HM, the roughness of the first conductive layer481can be improved because an opened area is not present in the first opening OP1. Specifically, since the first conductive layer481substantially completely fills the first opening OP1, the hard mask HM may not be formed within the first opening OP1, thereby obviating the need for etching the hard mask HM within the first opening OP1. As a result, when the first conductive layer481is partially etched in the process of etching the hard mask HM, the roughness of the first conductive layer481would be significantly reduced compared to when the hard mask HM is formed within the first opening OP1and then etched from the first opening OP1.

Referring toFIGS.11A to11C, a second conductive layer483may be formed. The second conductive layer483may be formed along the inner side of the second opening OP2. In this case, the second opening OP2may be filled with the second conductive layer483so that an opened area is not present in the second opening OP2. Accordingly, the second conductive layer483may protrude into the memory cell MC, and may protrude into the separation insulating layer440through the word line420.

Before the second conductive layer483is formed, a barrier layer482may be formed. The barrier layer482may be formed between the first conductive layer481and the second conductive layer483.

Referring toFIGS.12A to12C, a bit line480that extends in the second direction II may be formed. The bit lines480may be formed by patterning the second conductive layer483, the barrier layer482, and the first conductive layer481. The bit line480, including a first protruding part480P1, a second protruding part480P2, and a connection part480P3that connects the first protruding part480P1and the second protruding part480P2and that extends in the second direction II, may be formed.

In this case, the first protruding part480P1may include a first conductive layer481that protrudes into the variable resistance layer450. The electrode layer460may be disposed between the first protruding part480P1and the variable resistance layer450.

The second protruding part480P2may extend through the separation insulating layer440, and may be electrically connected to the second contact plug430. The second protruding part480P2may include the barrier layer482and the second conductive layer483within the barrier layer482. The second protruding part480P2may play a role as a contact plug that connects the connection part480P3and the second contact plug430.

The connection part480P3may include the first conductive layer481, the barrier layer482on the first conductive layer481, and the second conductive layer483on the barrier layer482.

According to the aforementioned process, in depositing the conductive layers for forming the bit line480, the conductive layers may be divided and deposited plural times. Accordingly, the variable resistance layer450under the conductive layer can be prevented from being damaged, such as being peeled, when the conductive layer is patterned, or damage to the variable resistance layer450when the conductive layer is patterned can be minimized.

Furthermore, the second opening OP2may be formed in the state in which the first opening OP1has been filled with the first conductive layer481. In this process, the first conductive layer481may be partially etched. Since an opened area is not present in the first opening OP1, roughness of the second conductive layer483can be improved in the process of depositing the second conductive layer483for forming the bit line480.

Although embodiments according to the technical spirit of the present disclosure have been described above with reference to the accompanying drawings, the above-described embodiments have been provided to merely describe embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the embodiments. A person having ordinary knowledge in the art to which the present disclosure pertains may substitute, modify, and change the embodiments in various ways without departing from the technical spirit of the present disclosure written in the claims. Such substitutions, modifications, and changes may be said to belong to the scope of the present disclosure.