Apparatus for error detection in memory devices

The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

FIELD OF THE INVENTION

This invention relates to an apparatus for transfer of data elements between a bus master and a memory controller for a memory storage device. It also relates to a data storage interface device for transfer of data elements between a bus master and a memory controller for a memory storage device. It also relates to a method of storing data into a memory device and to a non-transitory computer readable medium.

BACKGROUND OF THE INVENTION

In automotive electronics an increasing number of applications require large amounts of RAM (Random Access Memory), often many megabytes of RAM. The process technologies currently used limit the amount of RAM on chip for practical and economical reasons. A cost effective solution is to use standalone DRAM (Dynamic Random Access Memory) components. In particular, DRAM components used in Personal Computers (PCs) and mobile phones are readily available and cost competitive.

At the same time as memory capacity requirements are increasing, so is the need for increased functional safety. When the electronics module can brake and steer a vehicle without driver intervention, it needs to be ‘safe’. Functional safety requires that faults can be quickly and reliably detected. DRAM devices are prone to random changes to the data stored in the device. Functional safety requires that any change to the data in the DRAM device can be detected and, if possible, corrected.

Non-dynamic data in RAM devices which is constant and never expected to change (such as a code image) is simple to test for errors by periodically performing a cyclic redundancy check (CRC) or checksum of the constant data. However, dynamic data, which is constantly changed by the CPU or system, cannot be checked with a CRC or checksum.

A known solution for detecting errors in dynamic data in RAM devices is to perform a simple checksum of each data element (maybe 16 bits, 32 bits or 64 bits) and store the checksum in extra RAM bits associated with each data element. These checksum bits enable detection of an error and what the correct data should be. This is called ECC (Error Correction Coding) and is for instance applicable to correct single bit errors and detect double bit errors. For example, each 32-bit data element requires additionally 7 bits for the ECC checkbits.

US2012/0005559 A1 describes an apparatus and method for managing a DRAM buffer. The DRAM buffer managing apparatus may generate an error correction code (ECC) for data to be written in the DRAM buffer, and may write the data and the ECC bits in the DRAM buffer. An address translation table is used which indicates where in the DRAM buffer, the extra ECC bits are stored.

SUMMARY OF THE INVENTION

The present invention provides an apparatus for transfer of data elements, a data storage interface device for transfer of data elements between a bus master and a memory controller for a memory storage device, a method of storing data into a memory device and to a non-transitory computer readable medium as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1schematically shows an example of an apparatus10for transfer of data elements between a CPU11and a DRAM controller12. It should be understood that the CPU11described with reference to the example ofFIG. 1is one example of a bus master and the present application is not limited thereto. Hence, any component operating as a bus master may store data using the apparatus10. The DRAM controller12interfaces between the apparatus10and a DRAM13. The CPU11is enabled to read and write data from/to the DRAM13.

The apparatus10comprises an address translator15arranged to receive a write address4from the CPU11and to modify the write address into a modified write address14. The address translator15is further arranged to send the modified write address14to the DRAM controller12. In case of a read from the DRAM13, the address translator15is arranged to receive a read address7from the CPU11, and to modify the read address into a modified read address17. The address translator15is further arranged to send the modified read address17to the DRAM controller12.

The apparatus10further comprises an ECC calculator16, which is arranged to receive write input data8associated with the write address from the CPU11, and to generate an error correction code using the write input data8. The apparatus10further comprises a concatenator18arranged to receive the write input data8from the CPU11and to receive the error correction code from the ECC calculator16. The concatenator18is arranged to concatenate the write input data8and the error correction code to obtain write output data20and to send the write output data20to the DRAM controller12. Accordingly, the write input data8, written by the CPU11into the DRAM13, is provided with and accompanied by the associated ECC, forming the write output data20. Since ECC is concatenated to the data to be written, more memory space is needed than the CPU11is aware of. Translation of a CPU address space into a DRAM address space is performed by the address translator15as will be discussed below in more detail.

The apparatus10further comprises a data checker19arranged to receive read input data21associated with the modified read address17, from the DRAM controller12. The read input data21comprises a data element and an error correction code. The data checker19is arranged to correct the data element on-the-fly using the error correction code, to obtain a corrected data element25, and to send the corrected data element25to the CPU11.

In case of a CPU write the following actions are performed. The write address4from the CPU11is translated into the modified write address14to store a concatenation of the input write data8and the write ECC into the DRAM13. The write ECC is calculated using the input write data8and the resulting ECC checkbits are concatenated with the original data, the input write data8, and written to the DRAM13at the modified write address14.

In case of a CPU read the following actions are performed. The read address7from the CPU11is translated into the modified read address17. A concatenation of a data element and the ECC checkbits (also referred to as the read ECC) is read from the DRAM13at the modified read address. The extraction may comprise a calculation of an ECC syndrome from the data element and the ECC checkbits of the read concatenation. Based on the resulting ECC syndrome, three possible data states may be indicated: 1) no error detected, 2) a 1-bit error detected, 3) a multi-bit non-correctable error detected. In the case where a 1-bit data error is detected, a corrected data element25is generated from the read data element and the ECC syndrome and returned to the CPU11. It is noted that in case no correction is needed, the data element25to be returned to the CPU11is the data element of the concatenation, which is read from the DRAM13, without the ECC checkbits.

FIG. 2schematically shows an example of an embodiment of an apparatus26for transfer of data elements between a CPU11and a DRAM controller12. The apparatus26differs from the embodiment ofFIG. 1in that it comprises an ECC calculator16′ arranged to receive the write input data8associated with the write address from the CPU11, and to receive the write address4. The ECC calculator16′ is arranged to generate an error correction code using the write input data plus the write address. So both the write address from the CPU11, as well as the write input data8is used in the ECC calculator16′.

The apparatus26also comprises a data checker19′ arranged to receive the read address7and to receive the read input data21. The read input data comprises a data element and an error correction code. The data checker19′ is arranged to correct the data element using the error correction code and the read address7, to obtain a corrected data element, and to send the corrected data element to the CPU11. By including the read address7from the CPU11in the ECC calculation and thus in the data correction (performed by the data checker19′), it is ensured that the data read from the DRAM13is read from the correct address location.

When data elements are written to the DRAM13from the CPU11, ECC checkbits are calculated for those data elements and appended to each data element and combinations of each data element and its corresponding ECC checkbits are stored in the DRAM13. Since the data with ECC is now bigger than the original data, the data is stored in DRAM13at a translated address. This translation is done by the memory management apparatus10, in particular the address translator15, and is transparent to the CPU11.

FIG. 3schematically shows a first example of the flow of data between the CPU11and the DRAM13in case of a write operation. The example ofFIG. 3is showing an implementation, which assumes that the individual data storage elements of the DRAM13have a width of 16 bits. Those skilled in the art will understand that the teaching of the present application is not limited to any specific storage element width but the skilled person is taught to apply the teaching to different storage element widths such as 8 bits, 32 bits, 64 bits and 128 bits. During a write operation of the CPU11, multiple bytes are written in parallel and each byte (8 bits) of the write operation is handled separately. In this example the CPU11writes 64 bits of data via a 64-bit bus interface31to a 64-bit write buffer32. The 64-bit write buffer32may be part of the DRAM management apparatus10shown inFIG. 1. The byte of data, see block33, is used by the ECC calculator16to calculate the so-called ECC checkbits (5 bits in this example), see block34. The byte of data33is concatenated with the ECC checkbits34plus padding bit(s) (3 padding bits in this example), to create a 16-bit data element35that is written to the DRAM13via the DRAM controller12.

FIG. 4schematically shows a second example of the flow of data between the CPU11and the DRAM13in case of a write operation. As in the previous example,FIG. 4is showing an implementation which assumes that the individual data storage elements of the DRAM13have a width of 16 bits and which should be understood as not limiting the teaching of the present application as mentioned above with reference toFIG. 3. Each byte of a write operation is handled separately. In this example the CPU11writes 64 bits of data via a 64-bit bus interface31to a 64-bit write buffer32. The 64-bit write buffer32may be part of the DRAM management apparatus10shown inFIG. 1. The byte of data, see block33, along with an address (herein a 40-bit address for the sake of illustration) of that byte, see block36, is used by the ECC calculator16′ to calculate the ECC checkbits (7 bits), see block34. As inFIG. 3, the byte of data33is concatenated with the ECC checkbits34plus padding bit(s) (1 padding bit in this example), to create a 16-bit data element35that is written to the DRAM13via the DRAM controller12.

FIG. 5schematically shows a third example of the flow of data between the CPU11and the DRAM13in case of a read operation in correspondence with the above examples relating to write operations. A read request is received from the CPU11at the DRAM management apparatus26, seeFIG. 2, and 16-bit data51is fetched from the DRAM13for every byte of data requested by the CPU11. The data51comprises an 8-bit data element52and the 7 checkbits53. The 8-bit data element52and the 7 checkbits53are concatenated with the 40-bit requesting address55and then the ECC is checked by the data checker19′. It is noted that the concatenating may differ from the example ofFIG. 5. For example, the address bits may be included at the beginning, the middle or the end of the concatenated data input to the ECC checker19′. A checked and possibly corrected 8 bits of data is returned by the data checker19′ as the requested data element to the CPU11. In this example, the data checker19′ will move the possibly corrected data element into a 64-bit read buffer57. Once the entire read buffer57is filled, it will be read as part of a 64-bit read data by the CPU11.

In the previous three examples, the data is expanded by a factor of 2. So every byte from the CPU11occupies 2 bytes in the DRAM13. During a CPU read operation, the data and ECC checkbits are read from the DRAM13; the integrity of the data is checked and, if an error is detected, the read data is corrected on the basis of the ECC checkbits. The possibly corrected data is returned to the CPU11. From the CPU's perspective, it appears that the DRAM13can be read out and written on the basis of the addressing scheme known to the CPU. In the memory management apparatus10, in particular the concatenator18, ECC checkbits are concatenated to data to be written to into the DRAM13without affecting the CPU11addressing scheme used by it.

In case a single bit error is detected in the data stored in the DRAM13, the single bit error is automatically corrected by the data checker19,19′ during a read operation. So the CPU11receives corrected data. In case a double bit error is detected in the data stored in the DRAM13, the data checker19,19′ indicates a memory error back to the CPU11.

The examples of the apparatus10,26described above enable detection of errors in a random access memory without any additional cost impact and without any additional requirements for the bus master11. The use of ECC checkbits may also allow for more elaborate ECC schemes such as including the memory address in the ECC calculation, as discussed in the examples ofFIGS. 4 and 5. Such an ECC scheme would allow detection of other DRAM faults, such as ‘stuck at’ or shorted address line, for example, a fault which causes that correct data are read from a wrong address. With the memory address encoded into the ECC checkbits during a write operation, on a read operation, not only must the data match the ECC checkbits but the read address must also match.

FIG. 6schematically shows an example of a CPU address space61which is transformed into a DRAM address space62by the address translator15of the apparatus10ofFIG. 1. At the left side ofFIG. 6the CPU address space61is shown. The CPU address space61comprises a first non-ECC protected region63. Below that region an ECC protected region64is present followed by a reserved region of DRAM65. At the bottom a second non-ECC protected region66is present. At the right side ofFIG. 6the DRAM address space62is shown. The DRAM address space62comprises a first non-ECC protected region67. Below that region an ECC protected region68is present followed by a second non-ECC protected region69.

The CPU11will see the ‘normal’ region of DRAM64followed by the ‘reserved’ region of DRAM65. The ‘normal’ region of DRAM64may be understood as randomly accessible by the CPU11and the ‘reserved’ region thereof may be understood as inaccessible by the CPU11. The address translator15translates the size of the CPU DRAM region64to the ECC protected region when data is read out from or written into the CPU DRAM region64of the DRAM13by the CPU11.

In the example ofFIG. 6, an address translation is executed only for the read and writes from/to the CPU DRAM region64. Only this CPU DRAM region64is protected by ECC. A base address of the region within the CPU address space that is protected by ECC is named Addr_low. The top address of the CPU DRAM region64is named Addr_high. The address of an element of data within the CPU DRAM region64is designated as Addr_master. The translated address in the DRAM address space62of the data element with address Addr_master in CPU address space61is called Addr_mem.

In an embodiment, the address translator15is arranged to translate a write address into a modified write address using a memory expansion factor K. This is the factor by which the data stored to DRAM is expanded by the addition of the ECC checkbits. The factor K may be calculated as follows:
K=(Size_of_data+Size_of ECC)/Size_of_data  (1)

whereinSize_of_data: the bit-width of a data element to be coded, andSize_of_ECC: the bit-width of ECC checkbits rounded up to the nearest 2nnumber.

For example, if the width of a data element is 8 bits (Size_of_data) and the width of ECC checkbits is 7 bits, the latter will be rounded to 8 bits (Size_of_ECC) resulting in the value for the factor K=(8+8)/8=2.

The translation of the address of any element of data as seen by the CPU11, to the address where the data is stored in DRAM is given by the following equation:
Addr_mem=Addr_low+K·(Addr_master−Addr_low)  (2)

whereinAddr_low: the base address of the protected region within the CPU address space,Addr_master: the address of a element of data within the protected region, andAddr_mem: the translated address in the DRAM address space of the element of data with address Addr_master in CPU address space.

The size of the region of the DRAM address space used to store data with ECC checkbits is larger than the size of the region of CPU data by the factor K. This results in a region of CPU address space that is ‘reserved’, for example see region65. CPU writes to this reserved region may have unpredictable results that will depend on the specific implementation. For example an error may be returned by the memory management apparatus10. Such error may indicate that the access to the ‘reserved’ CPU address space is not allowed.

Furthermore, from the above description, those skilled in the art will understand that the partitioning of the DRAM address space into one or more unprotected regions and one or more protected regions is configurable.

FIG. 7schematically shows an example of part of a CPU address space71translated into part of a DRAM address space72. In this example the following assumptions are made. The size of each data element is 8 bits. The width of ECC checkbits is 7 bits (rounded up to 8 bits) resulting in an expansion factor K of 2. The CPU has 64-bit read/writes access to the DRAM13. InFIG. 7, arrows73indicate where data elements74of the CPU address space71are stored in the DRAM address space72as data elements75. As can be seen fromFIG. 7, each of the data elements75is followed by ECC checkbits, which 8 bits due to rounding up. The CPU address space71continues from the master base address Addr_low to the master top address Addr_high, whereas the DRAM address space71continues from the memory base address Addr_low to the memory top address K·(Addr_high−Addr_low) with K=2.

FIG. 8schematically shows an example of a data storage interface device80for transfer of data elements between a bus master81and a memory controller83for a memory storage device82. The data storage interface device80ofFIG. 8comprises an apparatus84which may be the apparatus10as described above. A bypass88is arranged in parallel to the apparatus84to forward read/write accesses from the bus master81directly to the memory controller83. A first switch85is arranged to connect the bus master to the apparatus84in a first state, and connect the bus master to the bypass88in a second state. A second switch86is arranged to connect the apparatus84to the memory controller83in a first state, and connect the bypass88to the memory controller in a second state. The data storage interface device80further comprises a switch control unit87arranged to control the first switch85and the second switch86.

In the example ofFIG. 8the CPU read/write accesses may be initiated by an ARM QOS (Quality-of-Service) system bus switch fabric81. CPU writes may be 64 bits wide with a clock frequency of e.g., 533 MHz. The data is stored in the DRAM82. The memory controller83may have a 64-bit wide 533 MHz port from the data storage interface device80and a 32-bit wide 533 MHz DDR port to the DRAM82.

The apparatus84is arranged to generate and concatenate ECC checkbits to data elements, and to check read data received from the memory controller83using ECC checkbits incorporated in the read data. The apparatus84may comprise the address translator15, the ECC calculator16′, the concatenator18and the data checker19′ as shown inFIGS. 1 and 2. It is noted that instead of the switch fabric81any other crossbar, switch fabric, network-on-chip, or bus master may be connected to the data storage interface device80.

In an embodiment the selection of the bypass88is based on the address of the read/write request (Addr_master). Also referring toFIG. 6, the bypass may be activated by the switch control unit87, if the following is true:
Addr_master<Addr_low or Addr_master>Addr_high  (3)

So by means of the data storage interface device80ofFIG. 8, the CPU memory address space61may be transformed into the DRAM address space62as shown inFIG. 6.

The switch control unit87in conjunction with apparatus84may be arranged to perform error injection. Error injection may be performed to test that the apparatus is functioning to correct errors in the DRAM. This may be done by injecting errors into the data and/or ECC checkbits stored in DRAM; then reading that value back to verify the data is checked and corrected. For this purpose the switch control unit87may receive a command from the CPU to instruct the apparatus84to write some previously programmed data and ECC to the DRAM82at a previously programmed address. This data would contain some known error, such as 1 bit inverted from the correct value. The CPU could then perform a read operation from this address and check that the read data element was corrected.

The examples described with reference toFIGS. 3, 4 and 5show ECC calculations on byte size elements. This has the advantage that it simplifies the interface to the CPU11. Most CPUs have the capability to read and write different widths of data (e.g. 8 bits, 16 bits, 32 bits, etc.). With the ECC calculated on 8-bit data widths, it means that any access from the CPU11can be handled without the need to read-modify-write the DRAM13as would be required if the data write width is less than the ECC data size. It would also be possible to create an implementation that calculates the ECC checkbits on, for example, 32 bits of data. Such implementation would be suited for read/write requests of 32-bit data, but if the CPU wishes to write, for example, 16-bit data, then the apparatus reads32data bits plus ECC checkbits from the DRAM13, replaces the target 16 bits of data with the new data from the CPU11, calculates the ECC checkbits on this new 32-bit data, and then writes the 32 bits+ECC checkbits back to DRAM. This is referred to as read-modify-write operation.

In the examples above it has been assumed that the read/write requests are initiated by a CPU. It is noted that this invention is not limited to data storage by a CPU. It will work with any bus master that can initiate a read/write request including: DMA, DSP, hardware accelerators, debug memory access, cache controllers, communication interfaces, etc.

The description of this invention so far has exclusively described applications that use DRAM memory devices. It is not only limited to DRAM but could be used with any memory storage device, such as SRAM or flash device, or the bus interface to an ASIC (application specific integrated circuit) or FPGA (field-programmable gate array).

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. It is to be understood that the architectures depicted in the drawings are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality.

FIG. 9shows exemplary flow charts of a method of managing data in a memory device. The method comprises an exemplary write access operation and an exemplary read access operation, see900. The exemplary write access operation, see920, comprises receiving a write request from a bus master, see901. The write request comprises write input data and a write address. The method further comprises modifying the write address into a modified write address, see902. The method further comprises generating an error correction code using the write input data and optionally, the write address, see903. The method further comprises concatenating the write input data and the error correction code to obtain write output data, see904. The method further comprises sending the write output data and the modified write address to the memory controller, see905. The exemplary read access operation, see930, further comprises receiving a read request from the bus master, see906. The read request comprises a read address. The method further comprises modifying the read address into a modified read address, see907. The method further comprises sending the modified read address to the memory controller, see908. The method further comprises receiving read input data associated with the modified read address, from the memory controller, see909. The read input data comprises data element and an error correction code. The method further comprises correcting the data element on the basis of the error correction code, to obtain a corrected data element, see910. In particular, correcting the data element comprises using the read data and the error correction code to form a syndrome, which is then used to correct bit errors in the read data to obtain the corrected data element.

The method also further comprises sending the corrected data element to the bus master, see911. In particular, the correction of read data detected as erroneous is performed on-the-fly during the read request from the CPU is pending to be completed.