3DIC packaging with hot spot thermal management features

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

BACKGROUND

In the packaging of integrated circuits, semiconductor dies may be stacked through bonding, and may be bonded to other package components such as interposers and package substrates. The resulting packages are known as Three-Dimensional Integrated Circuits (3DICs). Heat dissipation is a challenge in the 3DICs. There exists a bottleneck in efficiently dissipating the heat generated in the inner dies of the 3DICs. The heat generated in the inner dies has to be dissipated to outer components such as outer dies before the heat can be conducted to any heat spreader. Between the stacked dies, however, there exist other materials such as underfill, molding compound, etc, which are not effective in conducting heat. As a result, the heat may be trapped in an inner region of a bottom stacked die and cause a sharp local temperature peak (sometimes referred to as a hot spot). Furthermore, hot spots due to heat generated by devices at the bottom of the stacked dies may also negatively affect the electrical performance of other overlaying devices in the stacked dies as well as the reliability of the whole 3DIC package.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A package with efficient hot spot thermal management features and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 1Aillustrates the cross-sectional view of an initial stage in the formation of Three-Dimensional Integrated Circuit (3DIC) package100, which includes dies10stacked on die12forming a die stack10/12. In some embodiments, dies10are memory dies that form a memory stack. In alternative embodiments, dies10are logic dies. In other alternative embodiments, dies10include both logic dies and memory dies. Die12may be a logic die, which may further be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or the like. Dies10and12may be bonded through flip chip bonding, wherein metal bumps, solder balls, or the like are used to bond dies10and12.

Die12has a top view size greater than the top view size of dies10. As shown inFIG. 1A, die12may extend laterally beyond dies10, and may include portion12athat is overlapped by dies10, and portions12bthat are not overlapped by dies10. The die stack including dies10and12are further bonded to substrate14. Substrate14may be a package substrate, an interposer, a Printed Circuit Board (PCB), or the like. Discrete passive devices (not shown) such as resistors, capacitors, transformers, and the like, may also be bonded to substrate14. Solder balls15are attached to substrate14, wherein die stack10/12and solder balls15are on opposite sides of substrate14.

Substrate14includes conductive features such as conductive layers18and conductive vias20(including through-vias20′, please refer toFIG. 1C). Conductive layers18and conductive vias20may be formed of any suitable material such as copper foil (e.g., 0.5 oz to 2 oz thick copper foil) and copper/copper alloy, respectively. Other conductive materials may also be used. Conductive features18/20may be used in package100for thermal conductive purposes to dissipate heat away from the center of die stack10/12. In some embodiments, conductive features18/20may also be used for electrical connections, for example, as ground, power, and/or signal input and output (TO) layers in substrate14. In other embodiments, some or all conductive features18/20may not serve electrical functions and may be referred to as dummy features.

A patterned solder resist16is disposed over substrate14. Solder resist16may be a protective layer that covers portions of substrate14to protect it from damage. Solder resist16may be formed of a polymer, which may also be a photoresist. The patterning of solder resist16may be performed, for example, using photolithography techniques. Solder resist16is patterned to expose portions (e.g., portions14aand14b) of a top conductive layer18in substrate14. Portions14bof the substrate may be exposed to allow electrical connections to conductive features18/20. For example, inFIG. 1A, portion14bcorresponds to the portion of substrate14underlying die stack10/12between the connectors (e.g., solder balls) of die stack10/12. In other embodiments, portion14bmay also correspond to portions of substrate14having electrical connections to discrete passive devices (not shown). Portions14aof the substrate are also exposed. Portions14amay be exposed for thermal dissipation purposes rather than electrical connection purposes. Exposed portions14amay be electrically connected to die stack10/12through exposed portion14band conductive features18/20. However, there may be no electrical devices (e.g., die stacks or passive components) in package100directly disposed over exposed portions14a.

FIG. 1Billustrates a detailed cross-sectional view of substrate14in accordance with various embodiments.FIG. 1Cillustrates alternative embodiments of substrate14. As illustrated byFIGS. 1B and 1C, substrate14may include a core14dand build-up layers14cdisposed on a front side and backside of core14d. A through-via20′ may extend from the front side of core14dand electrically connect to the backside of core14d. Core14dmay include conductive layers18(e.g., copper foil). Core14dmay include two (as illustrated inFIG. 1B), four (as illustrated inFIG. 1C), six, eight, or more conductive layers18. The number of conductive layers18may depend on layout design (e.g., electrical circuit design) of package100although additional conductive layers may increase the overall thermal conductivity of substrate14.

Build-up layers14cinclude an interconnect structure having patterned conductive layers18electrically connected by conductive vias20. In various embodiments conductive features18/20may serve functional electrical purposes such as power, ground, and/or signal IO layers. In various other embodiments, conductive features18/20may include dummy features for increased thermal conductivity. Although three build-up layers14care illustrated on either side of core14din bothFIGS. 1B and 1C, alternative embodiments may include a different number of build-up layers14cdepending on layout design.

Solder resist16is disposed over a front side of substrate14. Solder resist16may be patterned to include openings16ato expose portions of conductive layer18in substrate14. Certain openings16aallow for electrical connection to devices (e.g., die stack10/12or passive devices) to substrate14. In various embodiments, at least some openings16amay be used for heat dissipation as will be explained in greater detail in subsequent paragraphs. A solder resist17may also be disposed over a backside of substrate14. Solder resist17may also be patterned to include openings17aexposing certain conductive layers18. Solder balls (e.g., solder balls15ofFIG. 1A) may be attached to substrate14through these openings17a.

InFIG. 1D, A reflow is performed to reflow the solder balls in die stack10/12to substrate14. An underfill22may then be dispensed between die12and substrate14.

Next, referring toFIG. 1E, a thermal interface material (TIM)24is dispensed on dies10and12. TIM24includes portion24a, which is dispensed on the top of dies10. Furthermore, TIM24includes portions24b, which are also dispensed on, and may be in physical contact with, the top surfaces of portions12B of die12. TIM24may be a polymer having a good thermal conductivity, which may be between about 3 watts per meter kelvin (W/m·K) to about 5 W/m·K or more. TIM portions24bmay, or may not, form a ring. In accordance with some embodiments, when forming the ring, TIM portions24bencircle dies10. In which embodiments, portions12B of die12also form a ring encircling dies10.

Furthermore, a high thermal conductivity (Tk) material26is dispensed over exposed portions (i.e., portions14ainFIG. 1A) of substrate14. High Tk material26may be in physical contact with conductive lines18allowing heat to be thermally conducted from conductive lines18to high Tk material26. High Tk material26may be any material having high thermal conductivity, which may be between about 3 W/m·K and 50 W/m·K or more. For example, high Tk material26may be a TIM (e.g., formed of a same material as TIM24), solder, silver paste, or the like. In various embodiments, high Tk material26may have a thickness of about 50 μm to about 100 μm.

An adhesive28(e.g., an epoxy, silicon resin, or the like) is dispensed over an otherwise unoccupied portion of substrate14. Adhesive28may have a better adhering ability and a lower thermal conductivity than TIM24and high Tk material26. For example, adhesive28may have a thermal conductivity lower than about 0.5 W/m·K. Adhesive28may be positioned so as to not interfere with the placement of other features (e.g., device stack10/12, passive devices (not shown), and high Tk material26) over substrate14. In various embodiments, adhesive28may have a thickness of about 100 μm.

FIG. 1Fillustrates a top down view of substrate14, solder resist16, and adhesive28. For ease of illustration, high Tk material26is omitted fromFIG. 1F. The location of die12is indicated by a dashed line39, while a logic core region of die12is indicated by dashed line40. As illustrated inFIG. 1F, portions of conductive layer18in substrate14are exposed around and surrounding die12and logic core40. As will be explained in greater detail in subsequent paragraphs, the exposed conductive layer18may function as a heat dissipation feature to conduct heat away from logic core40. At least a portion of exposed conductive layer18may also allow electrical connections between substrate14and die stack10/12.

FIG. 1Gillustrates a cross-sectional view of die stack10/12and logic floor plans for dies10and12. Dies10and12may be laid out to minimize thermal crosstalk between devices in dies10and12and improve heat dissipation. For example, die12may include a logic core40and other logic circuits42. The other logic circuits42may include one or more Serializers/Deserializers (Serdes). Serdes42are logic control circuits that may consume a relatively high amount of power, and hence generate a relatively high amount of heat. In accordance with some embodiments, Serdes42(or other high-power circuits) are at least partially, and possibly entirely, allocated in portions12bof die12, which portions12bare not overlapped by dies10, as shown inFIG. 1G. Thus, the effect of heat generated by Serdes42may not directly affect the functionality of devices in dies10.

A logic core40may be located at least partially, and possibly entirely, in portion12aof die12, which portion12ais overlapped by dies10, as shown inFIG. 1G. An exemplary floor plan of die10(e.g., a memory die) is also illustrated. Memory die10may include a plurality of dynamic random access memory (DRAM) partitions44. Without thermal management features, heat from logic core40may negatively affect the performance of overlaying devices (e.g., DRAM partitions44) in dies10. Thus, various embodiments may include various hot spot thermal management features (e.g., comprising exposed conductive layers18) to conduct heat away from logic core40so as to not negatively impact the performance of dies10.

FIG. 1Hillustrates a sliced cross-sectional view of the attachment of a heat dissipating contour ring30to substrate14. A bottom surface of contour ring30may be adhered to substrate14through adhesive28. In a top-down view of package100(not shown), contour ring30may encircle die stack10/12. Contour ring30has a high thermal conductivity, for example, between about 200 W/m·K to about 400 W/m·K or more, and may be formed using a metal, a metal alloy, or the like. For example, contour ring30may comprise metals and/or metal alloys such as Al, Cu, Ni, Co, combinations thereof, and the like. Contour ring30may also be formed of a composite material, for example silicon carbide, aluminum nitride, graphite, and the like. Various portions of a bottom surface of contour ring30may contact TIM24band high Tk material26. Thus, contour ring30allows for the dissipation of heat from TIM24band high Tk material26away from die stack10/12. An adhesive32, which may be substantially similar to adhesive28, may be dispensed over portions of a top surface of contour ring30.

Next, referring toFIG. 1I, a heat dissipating contour lid34is mounted over die stack10/12and contour ring30. Contour lid34may be formed of substantially similar materials as contour ring30, which have a high thermal conductivity, for example, between about 200 W/m·K to about 400 W/m·K or more. Contour lid34includes bottom surfaces34aand a bottom surface34b. The position of bottom surfaces34aand34bare designed to fit the height of the top surface of dies10(and TIM portion24a) and the location of adhesive32. In the various embodiments illustrated inFIG. 1I, bottom surface34ais lower than bottom surface34b. Bottom surface34ais in contact with TIM portion24aallowing for heat dissipation from dies10through contour lid34. Bottom surface34bis in contact with adhesive32, which adheres contour lid34to contour ring30. The top surfaces of contour ring30and contour lid34may be substantially co-planar. Generally, the combination of contour ring30and contour lid34may be referred to as heat dissipation feature30/34. WhileFIG. 1Iillustrates contour ring30and contour lid34as separate pieces, in alternative embodiments, contour ring30and contour lid34may be a single piece heat dissipation feature30/34(e.g., seeFIG. 5A).

FIG. 1Jillustrates thermal dissipation away from logic core40in package100in accordance with various embodiments. Arrows36illustrate the path of thermal dissipation away from logic core40(and overlaying dies10). As illustrated inFIG. 1J, the combination of conductive features18/20, high Tk material26, and contour ring30form hot spot thermal management features in package100for conducting heat away from logic core40. Logic core40of die12is electrically connected to a conductive layer18having an exposed portion on a top surface of substrate14(e.g., portion14ainFIG. 1A). Heat generated by logic core40(or other sections of die12) is dissipated downwards to conductive features18/20in substrate14as indicated by arrows36. The heat dissipation portion of substrate14is not limited to a top most, exposed conductive layer18alone. Rather, multiple layers of interconnected conductive layers18(e.g., using vias20and through-via20′) may be used to conduct heat away die stack10/12. The heat is then conducted laterally away from logic core40/die12by conductive features18/20as indicated by arrows36b. Finally, the heat is dissipated upwards through exposed portions of conductive layer18, high Tk material26, and contour right30as indicated by arrows36c. Thus, heat may be conducted away from die stack10/12and logic core40using conductive features in substrate14to avoid or reduce thermal cross talk between logic core40and circuits in dies10(e.g., DRAM circuits). Furthermore, TIM24may also dissipate heat away from top surfaces of die stack10/12through contour ring30and contour lid34.

FIGS. 2A-2Dillustrate cross-sectional and top down views of portions of a package200in accordance with various alternative embodiments.FIG. 2Aillustrates a cross-sectional view of a portion of package300. Package200is substantially similar to package100, wherein like reference numbers correspond to like elements. However, the configuration of adhesive28and substrate14may be altered to allow for increased thermal conductivity as desired, for example, by exposing additional portions of conductive layer18. A greater area of conductive layer18may be exposed to allow for increased heat dissipation. For example,FIG. 2Billustrates a die12having multiple logic cores40, which may consume more power and generate more heat than a single logic core. To manage the high heat levels, additional portions of conductive layer18may be exposed to effectively dissipate heat away from die stack10/12. However, the increased surface area of exposed conductive layer18may limit the area available for adhesive material28on the perimeter of substrate14, negatively affecting the adhesion of contour ring30. Thus, additional adhesive material28amay be disposed on an interior region of substrate14(e.g., exposed conductive layer18may be disposed between adhesive28) for increased adhesion.

FIG. 2Cillustrates a top down view of substrate14in accordance with various alternative embodiments. In the configuration shown inFIG. 2C, die12includes three logic cores40. Each logic core is disposed over separate, non-contiguous exposed conductive layers18(labeled18a-18c). Exposed conductive layers18a-18cmay not be connected, allowing for thermal isolation amongst the three logic cores40. Furthermore, exposed conductive layers18a-18cmay have varying sizes. For example, a larger logic core40may be disposed over a larger exposed conductive layer portion18ato allow for increased heat dissipation. Various passive devices50(e.g., resistors, capacitors, transformers, and the like) may also be disposed over substrate14, wherein exposed conductive layers18do not overlap or connect to passive devices50. Adhesive28may be disposed around the perimeter and extended additional adhesive material28bmay be extended vertically and horizontally into the interior of substrate14(e.g., toward a die stack region of the package) for improved adhesion.

FIG. 2Dillustrates a top down view of substrate14in accordance with yet another alternative embodiment. In the configuration shown inFIG. 2D, die12includes two logic cores40. Logic cores40may be disposed in opposite corners of die12to increase thermal isolation between the two cores. Furthermore, logic cores40may be disposed over separate, unconnected exposed conductive layers18for increased isolation. Adhesive28may be disposed around the perimeter and extended diagonally from corners of substrate14into an interior region of substrate14(e.g., toward a die stack region of the package) to include adhesive material28cfor improved adhesion. As illustrated inFIGS. 2A-2C, the configuration of substrate14may be varied as desired depending on layout design and the configuration/power consumption levels of die stack10/12. Thus, substrate14is not limited to a particular layout, and other configurations of substrate14are also contemplated in other embodiments.

FIG. 3illustrates a cross-sectional view of a package300in accordance with various alternative embodiments having an alternative contour ring configuration. Package300is substantially similar to package100, wherein like reference numbers correspond to like elements. However, contour ring30may include additional overhang portions30aextending past adhesive28and sidewalls of substrate14. Overhang portions30aincrease the overall surface area of contour ring30, increasing heat dissipation.

FIG. 4illustrates a cross-sectional view of a package400in accordance with various alternative embodiments having an alternative configuration for die stack10/12. Package400is substantially similar to package100, wherein like reference numbers correspond to like elements. However, dies10may extend past die12in a lateral direction (i.e., dies10may fully overlap and cover die12). The heat generated by die12may create hot spots and may affect the functional operation of dies10. In order to manage these hot spots, in package400, additional high Tk material26(labeled26′) may be disposed under dies10and adjacent die12. In a top down view of package400, high Tk material26′ may or may not form a ring around die12. The corresponding portion of substrate14in contact with high Tk material26′ may include exposed conductive layers18.

As shown in the detailed view of package400(labeled400a), heat from dies10may be dissipated through additional high Tk material26′, substrate14(e.g., through conductive layers18and conductive vias20, which may include through-vias20′), high Tk material26, and contour ring30. The heat dissipation path is illustrated by arrows36. Heat from dies10may also be dissipated through TIM24and contour lid34as indicated by arrows52. Thus, high Tk material26may be disposed over substrate14as desired for additional thermal management of hot spots, and the like.

FIGS. 5A-5Billustrate a cross-sectional view of a package500in accordance with various alternative embodiments having multiple die stacks10/12. Package500is substantially similar to package100, wherein like reference numbers correspond to like elements. Package500may include plurality of die stacks10/12bonded to substrate14. Die stacks10/12may be two transistor stacks, two interposer stacks, or a combination thereof. Furthermore, dies10may be encased in a molding compound54, where outer sidewalls of molding compound54may be in alignment with outer sidewalls of die12. In the illustrated examples, there are two die stacks10/12although other embodiments may include a more than two die stacks10/12.

FIG. 5Aillustrates a cross-sectional view of the respective package. Contour ring30and contour lid34may be a single piece heat dissipation feature30/34. As shown inFIG. 5A, die stacks10/12may have heights H1 and H2, which may be equal to each other or different from each other. Accordingly, heat dissipation feature30/34comprises a plurality of portions30′/34′ extending down to different levels to compensate for any height difference of die stacks10/12. Heat dissipation feature30/34may be in contact with high Tk material26, which is disposed near die stacks10/12heat dissipation feature30/34may further be in contact with TIM24, which may extend down and contact sidewalls of die stacks10/12.

FIG. 5Billustrates a top down view of substrate14. Heat from logic cores40are dissipated away from die stack10/12through thermal management features (i.e., exposed conductive layer18, high Tk material26, and heat dissipation feature30/34) in package500as indicated by arrows36. Thus, multiple die stacks of different sizes may be incorporated in a same package having thermal management features for heat dissipation away from central areas of die stacks10/12.

By using thermal management features (e.g., a combination of exposed conductive layers in a substrate, high Tk material, and a contour ring/cover), the heat in packages may be dissipated to peripheral areas that have less effect on the function of any overlaying dies. A simulation to simulate the temperature distribution in the packages comprising stacked dies with thermal management features results are illustrated in contour plots600inFIG. 6A(showing operation temperatures of bottom die12) and6B (showing operation temperatures of top dies10). As shown byFIG. 6A, hot spots are dissipated away from logic core40to peripheral regions of die12. Furthermore, the maximum operation temperature602of the die12is reduced from 96.1° C. in conventional packages to 90.1° C. in accordance with embodiments. The maximum operation temperature604of top dies10is reduced from 93.3° C. in conventional packages to 89.3° C. in accordance with embodiments. Therefore, by adopting the thermal management features of the embodiments of the present disclosure, not only the operation temperatures of the packages are reduced, the hot spots are dissipated to peripheral regions of a die stack so as to have less impact on other devices in a die stack.

In accordance with an embodiment, a package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

In accordance with another embodiment, a package includes a substrate having an exposed conductive layer. The package further includes a die stack having one or more top dies electrically connected to a bottom die, wherein the bottom die includes a logic core electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacts the conductive layer, and a contour ring is disposed over and contacting the high thermal conductivity material.

In accordance with yet another embodiment, a method includes forming a conductive layer at a front side of a package substrate and forming a solder resist over the front side of the package substrate. The solder resist is patterned to expose a portion of the conductive layer. A die stack is attached to the front side of the package substrate, wherein the die stack is electrically connected to the conductive layer. A high thermal conductivity material is disposed over and physically contacting the exposed portion of the conductive layer. The method further includes attaching a heat dissipation feature to the front side of the package substrate, wherein the heat dissipation feature is in physical contact with the high thermal conductivity material.