Semiconductor memory device capable of reducing power supply noise caused by output data therefrom

A semiconductor device reduces power supply noise during read operations of a memory device. The semiconductor device includes a plurality of read circuits, a plurality of control circuits and a plurality of output circuits. The read circuits are coupled to the memory device and responsive to a first enable signal to provide readout data during an active period thereof. The output circuits receive the readout data and output the readout data to an external device in response to a second enable signal. The control circuits are coupled between the read circuits and the output circuits and control the output circuits. The control circuits provide output data which is gradually changed to a preset logical value during the active period and to a value equal to the value of the readout data from the read circuits after termination of the active period.

BACKGROUND OF THE INVENTION 
The present invention relates to a semiconductor device, and in particular, 
to a semiconductor device which minimizes source power noise appearing 
when data read from a memory cell array by sense amplifiers is output. 
DESCRIPTION OF THE RELATED ART 
FIG. 1 shows in a block diagram an example of a conventional semiconductor 
device. This device includes an external input signal buffer section 10, a 
memory cell selecting section 20, a data output section 300, (m+1) address 
input signals, (j+1) data output signals, and a memory cell array 23 in 
the memory cell selecting section 20. In the array 23, a memory cell is 
selected by an X address signal and a Y address signal. 
The buffer section 10 includes a CE buffer circuit 11 which receives as its 
input a chip enable signal CE and which outputs a read enable signal TSA, 
an X decoder enable signal BXD, a Y decoder enable signal BYD, and an 
output enable internal signal TCE; an OE buffer circuit 12 which receives 
as inputs thereto an output enable signal OE and the output enable 
internal signal TCE and which outputs an output buffer enable signal BOB; 
and (m+1) address buffer circuits 16.sub.o to 16.sub.m which respectively 
receive as inputs thereto X address input signals A.sub.o to A.sub.L and Y 
address input signals A.sub.L+1 to A.sub.m and which respectively output X 
address selection signals TA.sub.o, BA.sub.o to TA.sub.L, BA.sub.L, Y 
address selection signals TA.sub.L+1, BA.sub.L+1 to TA.sub.m, BA.sub.m, X 
address transition signals AT.sub.o to AT.sub.L, and Y address transition 
signals AT.sub.k+1 to AT.sub.m. In this case, signals TA.sub.o to TA.sub.m 
are in phase with signals A.sub.o to A.sub.m, whereas signals BA.sub.o to 
BA.sub.m have a phase opposite to that of signals A.sub.o to A.sub.m. 
The memory cell selecting section 20 includes an X decoder 21 which 
receives as inputs thereto the X decoder enable signal BXD and the X 
address selection signals TA.sub.o, BA.sub.o to TA.sub.L, BA.sub.L and 
which produces memory cell X selection signals M.sub.o to M.sub.n ; a Y 
decoder 22 which receives as inputs thereto the Y decoder enable signal 
BYD and the Y address selection signals TA.sub.L+1, BA.sub.L+1 to 
TA.sub.m, BA.sub.m and which creates memory cell Y selection signals 
M.sub.n+1 to M.sub.o ; and a memory cell array 23 which receives as inputs 
thereto the memory cell X selection signals M.sub.o to M.sub.n and the 
memory cell Y selection signals M.sub.n+1 to M.sub.o and which outputs 
data read signals DI.sub.o to DI.sub.j. 
The data output section 300 includes an address transition detection 
circuit (to be abbreviated as ATD herebelow) 31 which receives as inputs 
thereto the read enable signal TSA, the X address transition signals 
AT.sub.o to AT.sub.L, and the Y address transition signals AT.sub.L to 
AT.sub.m and which produces a sense amplifier enable signal TSA2 and a 
data latch control signal TSAL; (j+1) sense amplifiers 32.sub.o to 
32.sub.j which receive as inputs thereto the sense amplifier enable signal 
TSA2, the data latch control signal TSAL, and the data read signals 
DI.sub.o to DI.sub.j and which create sense amplifier output signals 
TD.sub.o to TD.sub.j ; and (j+1) output buffer circuits 34.sub.o to 
34.sub.j which receive as inputs thereto the sense amplifier output 
signals TD.sub.o to TD.sub.j and the output buffer enable signal BOB and 
which produce output signals D.sub.o to D.sub.j. 
Subsequently, a description will be given of the operation of each 
constituent component in the read operation of the conventional device. 
The read operation is enabled or disabled under control of the chip enable 
signal CE. In this specification, it is assumed that CE=0 ("L" level) 
indicates an active state in which the read operation is enabled and CE=1 
("H" level) denotes a non-active state in which the read operation is 
disabled (standby state). 
First, the external input buffer section 10 will be described with 
reference to FIGS. 2A to 3B. FIG. 2A is a circuit diagram showing an 
example of the CE buffer circuit 11, FIG. 2B is a diagram showing an 
example of a circuit of an arbitrary one of the address buffer circuits 
16.sub.o to 16.sub.m, and FIG. 2C shows waveforms of the signals of FIGS. 
2A and 2B. Additionally, FIG. 3A is a circuit diagram showing an example 
of the OE buffer circuit 12, whereas FIG. 3B shows waveforms of signals of 
FIG. 3A. 
As shown in FIG. 2A, the CE buffer circuit 11 includes inverters I.sub.130 
and I.sub.131 in a two-stage cascade connection and inverters I.sub.132 to 
I.sub.135 for receiving output signals therefrom, the signals being 
produced by branching an output signal from the inverter I.sub.131. To 
initiate a read operation, when the signal CE is altered from "1" to "0", 
the read enable signal TSA, X decoder enable signal BXD, Y decoder enable 
signal BYD, and output enable internal signal TCE produced respectively 
from the inverters I.sub.132 to I.sub.136 are varied from "0" to "1" as 
shown in FIG. 2C. In the graph of FIG. 2C, the read enable period is 
represented as period T.sub.1. 
The signal TSA controls enablement and disablement of the sense amplifiers 
32.sub.o to 32.sub.j and is supplied to ATD 31. The X decoder enable 
signal BXD and the Y decoder enable signal BYD are used to respectively 
activate or to deactivate the X decoder 21 and the Y decoder 22 and are 
respectively delivered to the X decoder 21 and the Y decoder 22. The 
output enable internal signal TCE supervises enablement and disablement of 
the output buffer circuits 34.sub.o to 34.sub.j in cooperation with the 
output enable signal OE and is supplied to the OE buffer circuit 12. 
On the other hand, the OE buffer circuit 12 includes a 2-input NOR circuit 
86, an inverter 85 connected to an input terminal of the NOR circuit 86, 
and an inverter 87 connected to an output terminal of the NOR circuit 86 
as shown in FIG. 3A. The output enable internal signal TCE is supplied to 
the inverter 85, whereas an output signal from the inverter 85 and the 
output enable signal OE are fed to the NOR circuit 86. 
In the configuration shown, when it is desired to activate the output 
buffer circuits 34.sub.o to 34.sub.j so as to output data read from 
specified memory cells to an external device, the chip enable signal CE 
and output enable signal OE are required to be set to "0" ("L" level). As 
can be seen from FIGS. 2C and 3B, when the signal OE is changed from "1" 
(inactive or nonactive) to "0" (active), the signal TCE is altered from 
"0" to "1". Consequently, the output signal from the NOR circuit 86 of 
FIG. 3A is set to "1" and hence the signal BOB from the inverter 87 is 
varied from "1" to "0" as shown in FIG. 3B. The signal BOB is utilized to 
directly control enablement and disablement of the output buffer circuits 
34.sub.o to 34.sub.j and is inputted to these circuits 34.sub.o to 
34.sub.j. 
As indicated in FIG. 2B, the address buffer circuits 16.sub.o to 16.sub.m 
each include inverters I.sub.136 to I.sub.142. When an arbitrary address 
input signal A.sub.k (k=0 to m) is altered from the low state (0="L" 
level) to the high state (1="H" level) as shown in FIG. 2C, the address 
transition signal AT.sub.k and the address selection signal TA.sub.k 
respectively outputted from the inverters I.sub.137 and I.sub.139 are 
changed from "0" to "1" (FIG. 2C), and the address selection signal 
BA.sub.k from the inverter I.sub.142 of FIG. 2B is altered from "1" to "0" 
as shown in FIG. 2C. 
The address transition signal AT.sub.k is a signal to notify an event that 
the address input signal A.sub.k has been selected. The signal AT.sub.k is 
supplied to ATD 31. The address selection signals TA.sub.k and BA.sub.k 
are used to select an address externally specified and are fed to the X 
decoder 21 and the Y decoder 22. 
In this specification, it is assumed that the points of input timing for 
the chip enable signal CE and the address input signal A.sub.k can be 
exchanged for the normal operation. Signals CE and A.sub.k are changed at 
the same time in this specification. Additionally, the inverters I.sub.130 
to I.sub.135 and I.sub.136 to I.sub.142 included respectively in the CE 
buffer circuit 11 and address buffer circuits 16.sub.o to 16.sub.m are so 
designed to fully drive the wiring capacitance of the output signals and 
the parasitic capacitance of transistors in the subsequent stage. 
Next, the memory cell selecting section 20 will be described. FIG. 4A is a 
circuit diagram showing an example of the X decoder 21, FIG. 4B is a 
diagram showing a circuit example of the Y decoder 22, and FIGS. 4C and 4D 
are tables showing a correspondence between the input signals respectively 
fed to the X and Y decoders 21 and 22 and the memory cell selection 
signals thus selected. The memory cell section procedure varies depending 
on the structure of the memory cell array 23. In FIGS. 4A to 4D, there is 
shown a selection method of selecting memory cells using four X address 
selection signals TA.sub.o, BA.sub.o, TA.sub.1, and BA.sub.1 created from 
two X address input signals A.sub.o and A.sub.1 and four Y address 
selection signals TA.sub.2, BA.sub.2, TA.sub.3, and BA.sub.3 generated 
from two Y address input signals A.sub.2 and A.sub.3. 
As can be seen from FIG. 4A, the X decoder 21 includes NAND circuits 91 and 
92 and inverters 93 and 94. Although not shown in FIG. 4A, there are also 
provided a first 3-input NAND circuit receiving as inputs thereto the 
signals BA.sub.0, TA.sub.1, and BXD; a second 3-input NAND circuit 
receiving as inputs thereto the signals BA.sub.1, TA.sub.0, and BXD; and 
inverters arranged on the output sides of these NAND circuits. Produced 
from these circuits are X selection signals M.sub.1 and M.sub.2. 
When the X decoder enable signal BXD is "0", the output signals from all 
NAND circuits such as circuits 91 and 92 are set to "1" ("H" level) and 
the memory cell X selection signals M.sub.0 to M.sub.3 produced from the 
inverters including the inverters 93 and 94 are set to "0" ("L" level) 
regardless of the address selection signals BA.sub.0, BA.sub.1, TA.sub.0, 
and TA.sub.1. Namely, neither one of the memory cell X selection signals 
is selected in this state. 
When the signal BXD is "1", one of the memory cell X selection signals 
M.sub.0 to M.sub.3 is "1" ("H" level) and the three remaining signals are 
"0" ("L" level) according to a combination of the address selection 
signals BA.sub.0, BA.sub.1, TA.sub.0, and TA.sub.1 as shown in FIG. 4C. In 
this situation, the signal set to "1" is the selected signal. For example, 
when the signals is BA.sub.0 =1, BA.sub.1 =1, TA.sub.0 =0, and TA.sub.1 
=0, only the output signal from the NAND circuit 91 is "0" ("L" level) 
such that only the signal M.sub.0 from the inverter 93 is "1" ("H" level) 
and the other signals M.sub.1 to M.sub.3 are "0" ("L" level). On this 
occasion, only the selection signal M.sub.0 is selected, i.e., the memory 
cell X selection signal can be selected only when the X decoder enable 
signal BXD is "1". 
This is also the case with the Y decoder 22. As shown in FIG. 4B, the 
circuit configuration includes four 3-input NAND circuits such as NAND 
circuits 95 and 96 and four inverters including inverters 97 and 98. Only 
when the Y decoder enable signal BYD is "1", the memory cell Y selection 
signal can be selected. FIG. 4D is a table showing the correspondence 
between the Y address selection signals BA.sub.2, BA.sub.3, TA.sub.2, and 
TA.sub.3 and the selected memory cell Y selection signal. 
The memory cell selection signals selected by the X and Y decoders 21 and 
22 are inputted to the memory cell array 23 of FIG. 1 to thereby select 
the specified memory cells. In each read operation, data items of the 
memory cells are read therefrom in association with (j+1) data output 
signals (D.sub.o to D.sub.j of FIG. 1) and are inputted as data readout 
signals DI.sub.o to DI.sub.j to the sense amplifiers 32.sub.o to 32.sub.j. 
The concrete method of generating the data readout signals DI.sub.o to 
DI.sub.j varies depending on the memory cell structure and the 
configuration of the memory array 23 and hence will not be described in 
detail in this specification. 
Subsequently, the data output section 300 will be described. FIG. 5A is a 
block diagram showing an example of ATD 31, and FIG. 5B shows the 
waveforms of the primary signals of FIG. 5A. As can be seen from FIG. 5A, 
ATD 31 includes a delay circuit 101 and signal composing circuits 102 and 
103. The circuits 102 and 103 of FIG. 5A are configured as shown in FIG. 
7. However, for simplification of explanation, it is assumed that there 
are inputted four X address transition signals AT.sub.x0 to AT.sub.x3 and 
four address transition signals AT.sub.y0 to AT.sub.y3. 
In the signal composing circuit 102, VI.sub.x0 to VI.sub.x3 of FIG. 7 
respectively correspond to the X address transition signals AT.sub.x0 to 
AT.sub.x3. Similarly, VI.sub.y0 to VI.sub.y3 are associated with the Y 
address transition signals AT.sub.y0 to AT.sub.y3 and an output signal 
VO.sub.0 corresponds to the sense amplifier enable signal TSA2. 
In the signal composing circuit 103, VI.sub.x0 to VI.sub.x3 and VI.sub.y0 
to VI.sub.y3 of FIG. 7 are respectively associated with the output signals 
DAT.sub.x0 to DAT.sub.x3 and DAT.sub.y0 to DAT.sub.y3 of the delay circuit 
101 of FIG. 5 and an output signal .sub.VO0 corresponds to the data latch 
control signal TSAL. 
Assume in this situation that the input signals to the delay circuit 101 
includes the X address transition signals AT.sub.x0 to AT.sub.x3 and Y 
address transition signals AT.sub.y0 to AT.sub.y3. Moreover, the signals 
DAT.sub.x0 to DAT.sub.x3 are in phase with the signals AT.sub.x0 to 
AT.sub.x3 and are delayed for a period of T.sub.D relative thereto, and 
the signals DAT.sub.y0 to DAT.sub.y3 are in phase with the signals 
AT.sub.y0 to AT.sub.y3 and are delayed for a period of T.sub.D relative 
thereto. 
The pulse width of the data latch control signal TSAL is designed to be 
less than the pulse width of the sense amplifier enable signal TSA2. FIG. 
5C shows waveforms of the signals TSA2 and TSAL when the read enable 
signals TSA and X address transition signal AT.sub.x0 initially acquired 
are changed from "0" to "1" at the same time and then the signals 
AT.sub.x1 and AT.sub.y0 are altered from "0" to "1" with a shift of time 
of T.sub.DI0 in a sequential fashion. 
The sense amplifier enable signal TSA2 is a pulse signal of positive 
polarity changing 0.fwdarw.1.fwdarw.0 with a pulse width T.sub.wo1 
beginning at a first transition point of the signals TSA and AT.sub.xo 
from "0" to "1". The signal TSAL is a pulse signal of positive polarity 
changing 0.fwdarw.1.fwdarw.0 with a pulse width T.sub.wo2 smaller than 
T.sub.wo1, the signal rising with delay of time T.sub.D relative to the 
signal TSA2. As above, ATD 31 detects the change of the signals TSA and 
AT.sub.S and as a result generates the signals TSA2 and TSAL. 
As scan be seen from FIG. 7, each of the signal composing circuits 102 and 
103 receives as inputs thereto the read enable signal TSA and the signals 
VI.sub.x0 to VI.sub.x3 and VI.sub.y0 to VI.sub.y3 and includes 1-pulse 
generator circuits P.sub.0 to P.sub.8, inverters I.sub.180 to I.sub.188, 
AND circuits 121 to 126 and 128, and NAND circuit 127 to produce a signal 
VO.sub.o. 
Next, the operation of the signal composing circuits 102 and 103 will be 
described. As shown in FIG. 5B, assume that the read enable signal TSA and 
input signal VI.sub.x0 are simultaneously changed from "0" ("L" level) to 
"1" ("H" level) and then the input signals VI.sub.x1 and VI.sub.yo are 
altered with an interval time of T.sub.DI from "0" ("L" level) to "1" 
(="H" level; however, input signals VI.sub.x2, VI.sub.x3, and VI.sub.y1 to 
VI.sub.y3 are maintained at "0" ("L" level)). In this situation, when the 
signal VI.sub.xo is input to the composing circuit 102 or 103, one 
positive-polarity pulse having a preset pulse width of T.sub.w is 
generated from the 1-pulse generator P.sub.o. The polarity of the pulse 
signal is then inverted through the inverter I.sub.180 to generate a pulse 
signal PG.sub.o, which is then supplied to the AND circuit 121. 
The operation above also applies to the signals TSA, VI.sub.x1, and 
VI.sub.y0. Beginning at a point where the signal is changed from "0" to 
"1", signals PG.sub.8, PG.sub.1, and PG.sub.4, each having a pulse width 
of T.sub.w, are respectively output from the inverters I.sub.188, 
I.sub.181, and I.sub.184 of FIG. 7 as shown in FIG. 5B. Signals PG.sub.2, 
PG.sub.3, and PG.sub.5 to PG.sub.7 corresponding to the signals VI.sub.x2, 
VI.sub.x3, and VI.sub.y1 to VI.sub.y3 are maintained "1" ("H" level). 
The signal OS.sub.0 is output from the AND circuit 121 which receives as 
inputs thereto the signals PG.sub.8, PG.sub.0, and PG.sub.1. The signal 
OS.sub.0 as can be seen from FIG. 5B, is a negative-polarity pulse signal 
which begins at change start point 1 of the signals TSA and VI.sub.x0 
previously changed and which ends at change point 2 where the pulse signal 
PG.sub.1 (from the signal VI.sub.x1 changed after period T.sub.D1) is 
changed from "0" to "1". Furthermore, the signal OS.sub.1 created from the 
AND circuit 122 is "1". The signal OS.sub.2 produced from the AND circuit 
123 is a negative-polarity pulse signal having pulse width T.sub.w, the 
signals OS.sub.2 being in phase with the signal PG.sub.4. The signal 
OS.sub.3 output from the AND circuit 124 is "1". 
In addition, the output signal from the AND circuit 125 is produced as a 
logical product between the output signals respectively from the AND 
circuits 121 and 122 and hence is a negative-polarity pulse signal, 
OS.sub.4 shown in FIG. 5B, and is in phase with the signal OS.sub.o. 
Moreover, the output signal from the AND circuit 126 is produced by ANDing 
the output signals from the AND circuits 123 and 124 and hence is a 
negative-polarity pulse signal, OS.sub.5 shown in FIG. 5B, and is in phase 
with the signal OS.sub.0. 
Consequently, as shown in FIG. 5B, the output signal OS.sub.6 from the NAND 
circuit 127 receiving both output signals from the AND circuits 125 and 
126 is a positive-polarity pulse signal which begins at change start point 
1 of the signals TSA and VI.sub.x0 first changed from "0" to "1" among the 
input signals VI.sub.x0, VI.sub.x1, and VI.sub.y0 and which ends at change 
point 3 where the pulse signal PG.sub.4 generated from the signal 
VI.sub.y0 last changed is changed from "0" to "1". 
The pulse signal OS.sub.6 is supplied to the AND circuit 128 together with 
the read enable signal TSA. In response thereto, since the signal TSA is 
"1", the signal VO.sub.0 output from the AND circuit 128 is equal to the 
signal OS.sub.6 as shown in FIG. 5B. 
Furthermore, when the signal TSA is "0" ("L" level), the output signal 
V0.sub.0 from the AND circuit 128 is "0" regardless of the data values of 
input signals VI.sub.x0 to VI.sub.x3 and VI.sub.y0 to VI.sub.y3. 
In this connection, FIG. 6A shows the circuit of each of the 1-pulse 
P.sub.0 to P.sub.8, and FIG. 6B shows waveforms of signals in the circuit. 
Each pulse generator includes inverters 111 to 116, a NOR circuit 117, 
resistor elements R.sub.170 and R.sub.171, and capacitors C.sub.170 and 
C.sub.171. When the input signal V.sub.i1 is changed from "0" to "1", the 
output signals S1 to S4 respectively from the inverters 111, 113, 115, and 
116 are respectively varied as shown in FIG. 6B. The signals S4 and S1 are 
supplied to the NOR circuit 117, which then creates a positive-polarity 
pulse signal V.sub.o1 having pulse width 2t as shown in FIG. 6B. The value 
of pulse width 2t is determined according to the values of the resistors 
R.sub.170 and R.sub.171 and capacitors C.sub.170 and C.sub.171. 
FIG. 6C shows an example of the delay circuit 101 shown in FIG. 5A, and 
FIG. 6D shows waveforms of signals in the delay circuit 101. As can be 
seen from FIG. 6C, the circuit 101 operates such that the polarity of the 
signal V.sub.i2 is reversed through an inverter 118 to be integrated by an 
integrating circuit including a resistor R.sub.172 and a capacitor 
C.sub.172 such that the integrated signal is fed to an inverter 119, which 
in turn produces an output signal V.sub.02 as follows. When the signal 
value is equal to or more than a predetermined threshold value, the 
polarity is inverted to obtain the signal V.sub.02 representing "0"; 
otherwise, the polarity is inverted to attain the signal V.sub.02 
indicating "1". Through the operation, there is produced the output signal 
V.sub.02 delayed t.sub.D relative to the input signal V.sub.i2 as shown in 
FIG. 6D. 
Conducting the operations above, ATD 31 detects the change of the read 
enable signal TSA and address transition signal AT.sub.s, outputs as the 
sense amplifier enable signal TSA2 the signal VO.sub.o from the signal 
composing circuit 102, and outputs as the data latch control signal TSAL 
the signal VO.sub.0 from the signal composing circuit 103. The signals 
TSA2 and TSAL are fed to the sense amplifiers 32.sub.o to 32.sub.j, which 
will be described below. 
The amplifiers 32.sub.o to 32.sub.j are equal configuration to each other 
in circuit configuration. FIG. 8A shows the circuit layout as indicated 
with 32 (32.sub.o to 32.sub.j). FIG. 8B is a circuit diagram showing an 
example of the output buffer (34.sub.o to 34.sub.j). As can be seen from 
FIG. 8A, the amplifier 32 includes a sense amplifier section 131 including 
p-channel metal oxide semiconductor (MOS) transistors (to be abbreviated 
as PchTr. herebelow) T.sub.p190 and T.sub.p191, n-channel MOS transistors 
(to be abbreviated as NchTr. herebelow) T.sub.N190 to T.sub.N193, 
inverters I.sub.190 and I.sub.191, and a reference signal generator 135 
and a data latch section 132 including p-channel MOS transistors 
T.sub.p192 to T.sub.p194, n-channel MOS transistors T.sub.N194 to 
T.sub.p196, and inverters I.sub.192, I.sub.193, and I.sub.195. 
When the enable signal TSA2 is "0" ("L" level), the transistor T.sub.N193 
is nonconductive and hence the sense amplifier section 131 is set to a 
nonactive state. The inverter I.sub.191 accordingly produces an output 
signal S.sub.190 at an intermediate potential. In this situation, the 
inverter I.sub.190 outputs a signal of "1", which is supplied to a gate of 
the transistor T.sub.N192. As a result, the transistor T.sub.N192 becomes 
conductive and hence nodes V.sub.0 and V.sub.1 are set to the same 
potential. In contrast therewith, when the signal TSA2 is "1" ("H" level), 
i.e., in a state opposite to the state above, the transistors T.sub.N193 
and T.sub.N192 are respectively conductive and nonconductive to activate 
the sense amplifier section 131. The transistors T.sub.P190 and T.sub.P191 
and the transistors T.sub.N190 and T.sub.N191 form a differential stage. 
Since the method of generating the reference signal V.sub.ref varies 
depending on the configuration of the memory cell array and the like, the 
detailed configuration of the reference signal generator 135 will not be 
described in this specification. The reference signal V.sub.ref created 
from the generator 135 has a signal level at an intermediate point between 
the levels respectively corresponding to data "0" and data "1" of the data 
read signal DI.sub.q as shown in FIG. 9A. 
For data "0", the level of signal DI.sub.q is assumed to be higher than 
that of reference level V.sub.ref (FIG. 9A). Since the signal DI.sub.q is 
applied to a gate of T.sub.N190 of FIG. 8A and the signal V.sub.ref is fed 
to a gate of T.sub.N191, the potential (drain potential of T.sub.N191) of 
node V.sub.1 is higher than that (drain potential of T.sub.N190) of node 
V.sub.0 for data "0" in the active state. Moreover, the data "1", the 
level of signal DI.sub.q is assumed to be lower than that of reference 
level V.sub.ref such that the potential of node V.sub.1 is lower than that 
of node V.sub.0 in this situation. 
Additionally, when the threshold value of inverter I.sub.191 is set to an 
intermediate value between the level of node V.sub.1 for data "0" and that 
of node V.sub.1 for data "1", the output signal from the inverter 
I.sub.191, i.e., the output signal S.sub.190 from the amplifier section 
131, is at "L" level as denoted by a solid line for data "0" and at "H" 
level as indicated by a dot-and-dash line for data "1" during a period of 
T.sub.w01 in which the enable signal TSA2 is at "H" level as shown in FIG. 
9A. In the active state, the operation is started in an equipotential 
state in which nodes V.sub.o and V.sub.1 are at the same potential and 
hence there can be implemented a high-speed sense amplifier according to 
the configuration shown. 
Subsequently, the data latch section 132 will be described. When the data 
latch control signal TSAL is "0" ("L" level), the transistor T.sub.P192 
receiving via its gate a signal obtained by inverting the signal TSAL and 
the transistor T.sub.N195 receiving the signal TSAL via its gate are in a 
nonconductive state. Therefore, T.sub.P193 and T.sub.N194 constituting a 
complementary MOS configuration are off, and the output signal S.sub.190 
delivered from the sense amplifier section 131 to the gate shared between 
T.sub.P193 and T.sub.N194 is not transferred to the subsequent stage. 
Consequently, the signal S.sub.191 from the drain common to T.sub.P193 and 
T.sub.N194 is set to an intermediate potential. 
In this state, T.sub.P194 and T.sub.N196 sharing a drain and a source 
respectively therebetween are conductive due to the data latch control 
signal TSAL at "0" level and then the output signal from the inverter 
I.sub.193 is fed to the inverter I.sub.192 and the output signal from the 
inverter I.sub.192 is delivered to the inverter I.sub.193. Namely, as can 
be seen from FIG. 9A, the data latched in the latch section 132 before the 
section 132 is enable is output as the output signal TD.sub.q (q=0 to j 
corresponding to output buffers 34.sub.o to 34.sub.j) from the inverter 
I.sub.192. 
On the other hand, when the control signal TSAL is "1" ("H" level), i.e., 
in a state reverse to the state above, the transistors T.sub.P192 and 
T.sub.N195 become conductive, and T.sub.P194 and T.sub.N196 become 
nonconductive. In this case, consequently, the output signal S.sub.190 fed 
from the amplifier section 131 to the common gate of T.sub.P193 and 
T.sub.N194 is inverted via T.sub.P193 and T.sub.N194 to be output as a 
signal S.sub.191 from the drain shared therebetween. The phase of signal 
S.sub.191 is then inverted via the inverter I.sub.192 to be output as the 
sense amplifier output signal TD.sub.q. In consequence, during a period 
T.sub.w02 in which the signal TSAL is at "H" level, the output signal 
TD.sub.q is in phase with the signal S.sub.190 produced from the amplifier 
section 131 as shown in FIG. 9A. 
Next, the output buffers 34.sub.o to 34.sub.j will be described. The 
buffers are of the same configuration including, as shown in FIG. 8B, a 
p-channel transistor T.sub.P195, an n-channel transistor T.sub.N197, an 
inverter 141, an NAND circuit 142, and an NOR circuit 143. 
In operation of the output buffers 34 (34.sub.o to 34.sub.j), when the 
output buffer enable signal BOB is "1" ("H" level), the inverter 141 
produces an output signal S.sub.194 representing "0" ("L" level) and hence 
the NAND circuit 142 creates an output signal S.sub.192 denoting "1" 
regardless of the sense amplifier output signal TD.sub.q. The NOR circuit 
143 generates an output signal S.sub.193 indicating "0" regardless of the 
signal TD.sub.q. Therefore, TP.sub.195 receiving via its gate the signal 
S.sub.192 from the NAND circuit 142 is nonconductive. Similarly, 
TN.sub.197 receiving via a gate thereof the signal S.sub.193 from the NOR 
circuit 143 is also nonconductive and the data output signal D.sub.q is 
set to an intermediate potential. 
When the enable signal BOB is "0" ("L" level), the phase of signals 
S.sub.192 and S.sub.193 is opposite to that of the signal TD.sub.q as 
shown in FIG. 9B. That is, when the signal TD.sub.q is at "H" level, the 
signals S.sub.192 and S.sub.192 are at "L" level. As a result, T.sub.P195 
is conductive and T.sub.N197 is nonconductive and the data output signal 
D.sub.q is at "H" level. When the signal TD.sub.q is at "L" level, the 
signals S.sub.192 and S.sub.193 are at "H" level. Consequently, T.sub.P195 
is nonconductive and T.sub.N197 is conductive and hence a discharge 
current I.sub.N197 flows through T.sub.N197 and the signal D.sub.q is set 
to "L" level. As a result, as can be seen from FIGS. 9A and 9B, the data 
output signal D.sub.q is in phase with the output signal TD.sub.q from the 
sense amplifier 32.sub.q, namely, the readout data is obtained. 
The read operation of the conventional semiconductor above will be briefly 
described as follows. When the chip enable signal CE is altered from "1" 
to "0" or when either one of the address input signals A.sub.o to A.sub.m 
are varied from "0" to "1" under a condition of signal CE=0, the read 
operation is carried out by the sense amplifier section 131 of the sense 
amplifier 32 for a preset period (T.sub.w01 of FIG. 5C). During a period 
from when the amplifier section 131 starts the read operation to when the 
operation is stabilized, the data latched in the data latch 132, namely, 
the data previously latched before the amplifier 32 is enable is outputted 
from the amplifier 32. 
When the predetermined period of time (T.sub.D of FIG. 5C) lapses, the data 
read out by the amplifier 32 is started to be output. The output data from 
the amplifier 32 is delivered to an external device when the output enable 
signal OE=0 is supplied to the semiconductor device. After the data output 
is completed, when the state "CE=1 and OE=1" is restored, the read 
operation is terminated and then the semiconductor device returns to the 
standby state. 
FIG. 9C shows waveforms of the sense amplifier output signal TD.sub.q, the 
data output signal D.sub.q, the GND power source, and the discharge 
current (total of all output buffers) of T.sub.N197 when the data output 
signal D.sub.q (q=0 to j) from the chip section is changed from "1" ("H" 
level) to "0" ("L" level). 
However, in accordance with the conventional semiconductor described above, 
the data output signals D.sub.o to D.sub.j are simultaneously changed and 
output at the same time. Consequently, when a plurality of output signals 
are simultaneously altered from "1" to "0", the discharge current 
(I.sub.N197) related to T.sub.N197 in the output buffer corresponding to 
each of the pertinent data output signals is transmitted to the GND power 
source at the same time. As a result, the GND potential is varied as shown 
in FIG. 9C. Alternatively, when the output signals are changed from "0" to 
"1", the charge current appearing in each p-channel MOS transistor in the 
final output stage is sent to the V.sub.CC power source at the same time, 
which as a result varies the V.sub.CC potential. 
In consequence, the output level of the data latch internal signal 
S.sub.191 (FIG. 8A) of the sense amplifier 32.sub.q exceeds the inversion 
threshold value of the inverter I.sub.192 and hence an erroneous data item 
("1"="H" level in this case) is latched, which results in the occurrence 
of a data read error. Additionally, the fluctuation of variation in the 
GND or V.sub.CC power source exerts an adverse influence in the 
constituent circuits, which may lead to operation errors. As above, in the 
conventional semiconductor device, the erroneous operations due to the 
deviation or change in the GND or V.sub.CC potential deteriorates 
reliability of the read operation. 
A device is known to overcome this difficulty, as described in the Japanese 
Patent Laid-Open Publication Ser. No. 3-54795, i.e., a semiconductor 
device including means for preventing the operation error due to noise 
components in the power source (power source noise). The operation error 
preventing means of the semiconductor device described in the Japanese 
Patent Laid-Open Publication Ser. No. 3-54795 includes a plurality of 
delay circuits connected to sense amplifiers to provide a difference of 
time between points of enable timing of the respective sense amplifiers 
according to enable signals produced from a sense amplifier enable circuit 
(corresponding to ATD 31 of FIG. 1). Thanks to the differential time 
between the enable timing points of the sense amplifiers (associated with 
32.sub.o to 32.sub.j of FIG. 1), there is provided a difference of time 
between points of the output timing of the data output signals 
(corresponding to D.sub.o to D.sub.j of FIG. 1). 
In accordance with the semiconductor device, the discharge current supplied 
to the GND power source is dispersed to thereby lower a peak value of the 
discharge current so as to suppress the variation in the GND potential. 
However, in the device described in the publication, since the points of 
timing to activate the respective sense amplifiers are sequentially 
delayed, there arises a problem that the points of timing to the output 
data items (i.e., read speed) are delayed by the difference of time 
provided to the amplifier enable timing. 
SUMMARY OF THE INVENTION 
It is therefore an object of the present invention to provide a 
semiconductor device in which the variation in the GND power source taking 
place when a plurality of data output signals are simultaneously altered 
from "1" (="H" level) to "0" (="L" level) or the variation in the V.sub.CC 
power source appearing when a plurality of data output signals are changed 
from "0" to "1" is suppressed to prevent any operation errors related 
thereto. The invention thus improves the read operation reliability to 
thereby remove the above described problem. 
Furthermore, another object of the present invention is to provide a 
semiconductor device in which the variation in the GND or V.sub.CC power 
can be suppressed to prevent operation errors associated therewith. 
To achieve the objects above in accordance with the present invention, 
there is provided a semiconductor device including a plurality of read 
circuits for achieving a memory read operation during an active period in 
which a first enable signal inputted thereto is a first logical value, 
outputting previous readout data until a control signal is inputted 
thereto during the active period, and outputting readout data thus read 
from the memory in response to the control signal; a plurality of output 
circuits for receiving as input signals thereto readout data from 
associated ones of the plural read circuits and a second enable signal and 
outputting to an external device the readout data inputted thereto during 
an active period in which the second enable signal is a predetermined 
logical value; and a plurality of control circuits provided in association 
with the plural read circuits. The control circuits receive as input 
signals thereto readout data from the read circuits and the first enable 
signal. The control circuits forcibly fix the readout data thus inputted 
thereto to a predetermined logical value regardless of values of the 
readout data during a period from a change point of the first enable 
signal to the first logical value to a point of time when the control 
signal is inputted to the read circuits. Moreover, the control circuits 
output, when the first enable signal is changed to the second logical 
value, the readout data having the logical value to the output circuits. 
In accordance with the present invention, thanks to the control circuits, 
during a period from the change point of the first enable signal to the 
first logical value to the input point of the control signal to the read 
circuit, the input readout data is forcibly fixed to a predetermined 
logical value regardless of the value of the data to supply the logic 
value to the output circuit such that the input readout data is forcibly 
fixed to a predetermined logical value regardless of the value of the data 
with mutually different values of time differences between the data items 
or between data item groups each including a plurality of data items. 
Consequently, when a plurality of readout data items are simultaneously 
changed to the predetermined logical value, the discharge current (or the 
charge current) from the final stage of the output circuit can be 
dispersed. Moreover, since the readout data is outputted to an external 
device after the read circuit enable period is finished, the readout data 
can be outputted in a state in which the GND or V.sub.CC power source is 
stable. 
In addition, the semiconductor device in accordance with the present 
invention further includes a plurality of control circuits provided in 
association with the plural read circuits for generating output circuit 
control signals in accordance with the readout data from the read circuits 
and the first enable signal and outputting the control signals to the 
output circuits. The control circuits control the output circuits by the 
control signals such that the output data therefrom is gradually changed 
to a predetermined logical value during the enable period of the read 
circuits and the output data has a logical value equal to the value of the 
readout data from the read circuits after the active period of the read 
circuits is completed. 
In accordance with the present invention, during the read circuit enable 
period, the output data is gradually changed to the predetermined logical 
value thus preset. Therefore, when a plurality of readout data items are 
simultaneously changed to the predetermined logical value, the sudden 
occurrence of the discharge current (or the charge current) from the final 
stage of the output circuit can be prevented. Furthermore, since the 
readout data is fed to an external device after the read circuit enable 
period is completed, the readout data can be outputted with the GND or 
V.sub.CC power source in a stable state.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to the drawings, description will be given of embodiments of 
the semiconductor device in accordance with the present invention. 
FIG. 10 shows in a block diagram the configuration of an embodiment of the 
semiconductor device in accordance with the present invention. The system 
of the embodiment shown in FIG. 10 preferably includes an external input 
signal buffer section 10, a memory cell selecting section 20, and a data 
output section 30 to produce (j+1) data output signals. The section 20 
includes a memory cell array of which memory cells are selected by an X 
address signal and a Y address signal. 
The buffer section 10 and the selector section 20 are respectively of the 
same configurations as those of the conventional semiconductor device 
shown in FIG. 1. Therefore, the circuit configuration and operation of the 
constituent components are also substantially the same as those of the 
prior art. In this regard, the X address input signals A.sub.o to A.sub.L 
of FIG. 1 are designated as A.sub.x in FIG. 10. Similarly, the Y address 
input signals A.sub.Ll to A.sub.m of FIG. 1 are indicated as A.sub.y in 
FIG. 10; the X address selection signals TA.sub.o, BA.sub.o to TA.sub.L, 
BA.sub.L of FIG. 1 are denoted as AD.sub.x in FIG. 10, the Y address 
selection signals TA.sub.L+1, BA.sub.L+1 to TA.sub.m, BA.sub.m of FIG. 1 
are denoted as AD.sub.y in FIG. 10; the X address transition signals 
AT.sub.o to AT.sub.L of FIG. 1 are represented as AT.sub.x in FIG. 10, the 
Y address transition signals AT.sub.L+1 to AT.sub.m of FIG. 1 are 
designated as AT.sub.y in FIG. 10; the memory cell X selection signals 
M.sub.o to M.sub.n of FIG. 1 are denoted as M.sub.x in FIG. 10, and the 
memory cell Y selection signals M.sub.n+1 to M.sub.o of FIG. 1 are 
indicated as M.sub.y in FIG. 10. 
As can be seen from FIG. 10, in accordance with an aspect of the present 
invention, control circuits 33.sub.o to 33.sub.j are respectively arranged 
for output buffers 34.sub.o to 34.sub.j in the data output section 30 in 
which output control signals CD.sub.o to CD.sub.j respectively from the 
control circuits 33.sub.o to 33.sub.j are fed to the output buffers 
34.sub.o to 34.sub.j, respectively. That is, the data output section 30 
includes an address transition detection (ATD) circuit 31, sense 
amplifiers 32.sub.o to 32.sub.j, control circuits 33.sub.o to 33.sub.j, 
and output buffers 34.sub.o to 34.sub.j. 
First Embodiment 
The control circuits 33.sub.o to 33.sub.j receive as inputs thereto a sense 
amplifier enable signal TSA2 produced from ATD 31 and sense amplifier 
output signals TD.sub.o to TD.sub.j to thereby respectively create control 
signals CD.sub.o to DC.sub.j. Circuit configurations and operations of ATD 
31 and the sense amplifiers 32.sub.o to 32.sub.j are almost the same as 
those of the conventional semiconductor device. 
The control circuit 33.sub.o to 33.sub.j are equal in configuration with 
each other. FIG. 11A shows the structure of the first embodiment of the 
control circuit 33.sub.q (q=0 to j). As can be seen from FIG. 11A, the 
circuit 33.sub.q includes a delay circuit 41, a 2-input NAND circuit 42, 
an inverter 43, and a data output switch circuit 44. 
The delay circuit 41 receives as an input thereto the sense amplifier 
enable signal TSA2 to produce signals DL.sub.q (q=0 to j respectively 
corresponding to output buffers 34.sub.o to 34.sub.j). The NAND circuit 42 
receives the signals TSA2 and DL.sub.q to thereby generate a signal 
SN.sub.20. The inverter 43 receives the signal SN.sub.20 from the NAND 
circuit 42 to produce a signal SI.sub.q for the data output switch circuit 
44. The switch circuit 44 receives the signals SI.sub.q and TD.sub.q to 
create a control signal CD.sub.q, which is then delivered to the pertinent 
output buffer 34.sub.q. 
FIG. 11B is a circuit diagram showing the first embodiment of the data 
output switch circuit 44. The circuit 44 includes an inverter 441 which 
receives the sense amplifier output signal TD.sub.q to create a signal 
S.sub.21. The circuit includes a p-channel MOS transistor T.sub.P20 having 
a source connected to the V.sub.CC power source, a gate input of the 
switch circuit input signal SI.sub.q, and a drain linked with a node 
V.sub.20. The circuit further includes a p-channel MOS transistor 
T.sub.P21 having a source connected to the node V.sub.20, a gate input of 
the inverter output signal S.sub.21, and a drain output of the buffer 
control signal CD.sub.q, and an n-channel MOS transistor T.sub.N20 having 
a drain output of the signal CD.sub.q, a gate input of the signal 
S.sub.21, and a source connected to the node V.sub.21. The circuit 
additionally includes an inverter 442 receiving the signal SI.sub.q and 
producing a signal S.sub.20, an n-channel MOS transistor T.sub.N21 having 
a drain output connected to the node V.sub.21, a gate input of the signal 
S.sub.20, and a source connected to the GND power source, and an n-channel 
MOS transistor T.sub.N22 having a drain output connected to the signal 
CD.sub.q, a gate input of the signal SI.sub.q, and a source connected to 
the GND power source. 
Subsequently, description will be given of roles and functions of the delay 
circuit 41 and data output switch circuit 44 of the control circuit 
33.sub.q. The delay circuit 41 provides a preset delay period of time to 
the sense amplifier enable signal TSA2. The delay time may be set to each 
of the output buffers 34.sub.o to 34.sub.j (i.e., data output signals 
D.sub.o to D.sub.j) in which the values of delay time assigned thereto are 
mutually different from each other. Alternatively, the buffers 34.sub.o to 
34.sub.j may be classified into groups such that the delay time is set to 
each of the groups, which will be specifically described. For example, 
eight output buffers are classified into two groups each including four 
buffers such that these two groups are assigned with mutually different 
values of delay time. 
The delay circuit 41 functions to delay for the preset period of time the 
signal TSA2 input thereto so as to produce a signal DL.sub.q. FIG. 11C 
shows in a circuit diagram the structure of the first embodiment of the 
delay circuit 41. This embodiment includes eight output buffers 34.sub.0 
to 34.sub.7 (j=7). Receiving the enable signal TSA2, the circuit produces 
non-delayed signals DL.sub.0 and DL.sub.1, signals DL.sub.2 and DL.sub.3 
delayed for t.sub.o, signals DL.sub.4 and DL.sub.5 delayed for 2t.sub.o, 
and signals DL.sub.6 and DL.sub.7 delayed for 3t.sub.o. 
Delay time t.sub.o is created from a circuit section (1)** of FIG. 11C. 
This section includes an inverter 49 which receives a signal V.sub.23 to 
produce a signal V.sub.24, a resistor element 50 having one end linked 
with an output terminal of the inverter 49, a capacitor element 51 
connected between the other end of the resistor 50 and the GND potential, 
and an inverter 52 which receives a signal V.sub.25 to generate a signal 
V.sub.26. The delay time t.sub.o can be set in accordance with the time 
constant of integration determined by the values of the resistor element 
50 and capacitor element 51. 
FNT **This number appears in a circle in the original specification. Due to 
technical difficulties, applicant is unable to reproduce that character. 
An integral multiple of t.sub.o can be obtained by appropriately arranging 
the circuit sections .oval-hollow. in a series connection. The sections 
enclosed with the dotted lines of FIG. 11C are of the same configuration. 
No delay time is set to the signals DL.sub.0 and DL.sub.1. In this 
connection, it is desirable to connect an inverter 47 having the 
characteristic of the inverter 49 to an inverter 48 having the 
characteristic of the inverter 52 in series so that the delay time is free 
of any influence from the characteristics of the inverters. 
Next, the data output switch circuit 44 serves as follows. During the 
active period of the sense amplifier 33.sub.q, the circuit 44 generates a 
signal which is changed after a fixed period of time to "0" and maintained 
in this state thereafter. During the nonactive period of the sense 
amplifier 33.sub.q, the circuit 44 generates a signal which is in phase 
with the output signal TD.sub.q. The circuit 44 functions to produce the 
output buffer control signal CD.sub.q of "0" for signal SI.sub.q =1 and 
the signal CD.sub.q which is in phase with the signal TD.sub.q for signal 
SI.sub.q =0. 
In the embodiment of the present invention, the delay time t.sub.o is set 
such that the output buffer control signals CD.sub.q are changed to "0" 
during the active period of the sense amplifier 33.sub.q. However, 
desirably, the delay time t.sub.o is set such that the data latch is 
enable after the signals CD.sub.q are changed to "0". In this 
specification, it is assumed herebelow that the delay time t.sub.o is set 
such that the data latch is enable after all output buffer control signals 
CD.sub.q are changed to "0". 
In the conventional semiconductor device described in the Japanese Patent 
Laid-Open Publication Ser. No. 3-54795, a delay circuit operating in 
accordance with an enable signal (the sense amplification enable signal 
TSA2 in this embodiment) produced from a sense amplifier enable circuit 
(ATD 31 in this embodiment) is connected to each sense amplifier (32.sub.o 
to 32.sub.j in this specification). In contrast therewith, according to 
the configuration of the embodiment, the operation is accomplished in 
accordance with the signal TSA2 from ATD 31 such that the control circuits 
33.sub.o to 33.sub.j receiving the signals TD.sub.q from the amplifiers 
32.sub.o to 32.sub.j are respectively linked with the output buffers 
34.sub.o to 34.sub.j. In this point, the device of the present invention 
is different from the conventional semiconductor device. 
Subsequently, the circuit layout of the output buffers 34.sub.o to 34.sub.j 
will be described. FIG. 12 shows in a circuit diagram the construction of 
the first embodiment of the output buffer 34.sub.q. As can be seen from 
FIG. 12, the buffer 34.sub.q includes an inverter 54 which receives the 
output buffer enable signal BOB to produce a signal S.sub.50, an NAND 
circuit 55 which receives the signals CD.sub.q and S.sub.50 and which 
generates a signal S.sub.51, an NOR circuit 56 which receives the signals 
CD.sub.q and BOB to create a signal S.sub.52, a p-channel MOS transistor 
T.sub.P50 having a source linked with the V.sub.CC power source, a gate 
input of the signal S.sub.51, and a drain output of the signal D.sub.q ; 
and an n-channel MOS transistor T.sub.N50 having a source linked with the 
GND power source, a gate input of the signal S.sub.52, and a drain output 
of the signal D.sub.q. 
Next, description will be given of roles of the control circuits 33.sub.o 
to 33.sub.j and the output buffers 34.sub.o to 34.sub.j. During the active 
period of sense amplifiers 32.sub.o to 32.sub.j, the control circuits 
33.sub.o to 33.sub.j produce signals which are changed to "0" ("L" level) 
with a fixed difference of time therebetween and are maintained in that 
state thereafter. During the nonactive period of sense amplifiers 32.sub.o 
to 32.sub.j, the control circuits 33.sub.o to 33.sub.j supply the output 
buffers 34.sub.o to 34.sub.j respectively with the output buffer control 
signals CD.sub.q which are in phase with data items read from the 
amplifiers 32.sub.o to 32.sub.j. During the active period of sense 
amplifiers 32.sub.o to 32.sub.j, the signals CD.sub.q may be changed to 
"0" in a signal-by-signal manner. Or, the signals may be classified into 
groups such that the change takes place in the group-by-group fashion. In 
this regard, when the data occurring before the enablement of amplifiers 
32.sub.o to 32.sub.j is "0", the signals CD.sub.q is kept fixed at "0" 
during the active period. 
Additionally, in the active state, the output buffers 34.sub.o to 34.sub.j 
deliver readout data sent from the control circuits 33.sub.o to 33.sub.j 
to an external device. In the active state, the output enable signal OE is 
"0", namely, the output buffer enable signal BOB is "0". 
Subsequently, description will be given of functions of the control 
circuits 33.sub.o to 33.sub.j and output buffers 34.sub.o to 34.sub.j. 
During the active period of sense amplifiers 32.sub.o to 32.sub.j, the 
control circuits 33.sub.o to 33.sub.j change the output signals CD.sub.q 
to "0" with a fixed discrepancy of time therebetween and maintain the 
signals in this state. During the nonactive period of sense amplifiers 
32.sub.o to 32.sub.j, the control circuits 33.sub.o to 33.sub.j produce 
the output signals CD.sub.q which are in phase with the sense amplifier 
output signals TD.sub.q. In the output buffer active state, the buffers 
34.sub.o to 34.sub.j output signals in phase with the signals CD.sub.q 
from the control circuits 33.sub.o to 33.sub.j. In the output buffer 
nonactive state, the buffers 34.sub.o to 34.sub.j deliver signals at an 
intermediate potential. 
Referring now the block diagram of FIG. 10 and the circuit configurations 
of FIGS. 11A to 11C and FIG. 12, description will be given of operation of 
the first embodiment in accordance with the present invention. 
In the embodiment, like in the conventional semiconductor device, when the 
X address signal A.sub.x and the Y address signal A.sub.y are specified by 
the chip enable signal CE set to "0", the sense amplifier enable signal 
TSA2 from ATD 31 is changed from "0" ("L" level) to "1" ("H" level). In 
response thereto, the sense amplifier 32.sub.o to 32.sub.j start a memory 
cell data read operation. 
FIGS. 13 and 14 are graphs showing waveforms of primary signals before, 
during, and after the active period of sense amplifiers 32.sub.o to 
32.sub.j. In this description, eight output buffers 34.sub.0 to 34.sub.7 
are classified into four groups each including two buffers. However, the 
number of output buffers 34.sub.o to 34.sub.j and that of the buffer 
groups may be arbitrarily specified. 
During the sense amplifier active period, the signal TSA2 of (A) in FIG. 13 
is "1" ("H" level). When the signal TSA2 is changed from "0" to "1" at 
time tc, the signals CD.sub.0 to CD.sub.7 from the control circuits 
33.sub.0 to 33.sub.7 are altered as follows. Namely, the signals CD.sub.0 
and CD.sub.1 are changed from "1" to "0" with delay time="0", namely, at 
time tc as shown in (L) to (O) of FIG. 13. When time t.sub.o lapses 
relative to time tc, the signals CD.sub.2 and CD.sub.3 are altered from 
"1" to "0". Similarly, when time 2t.sub.o and 3t.sub.o lapse after time 
tc, the signals CD.sub.4 and CD.sub.5 and the signals CD.sub.6 and 
CD.sub.7 are respectively varied from "1" to "0". 
The signals TD.sub.0 to TD.sub.7 from the sense amplifiers 32.sub.0 to 
32.sub.7 are fed to the controllers 33.sub.0 to 33.sub.7, respectively. 
The signals TD.sub.0 to TD.sub.7 are data signals obtained from the 
pertinent memory cells during the active period TE (reference is to be 
made to (J) and (K) of FIG. 13). When the enable period is completed and 
the operation to read data from the memory cells are terminated, the 
controllers 33.sub.0 to 33.sub.7 output as the output buffer control 
signals CD.sub.0 to CD.sub.7 the data items attained from the memory 
cells. That is, the signals CD.sub.0 to CD.sub.7 are in phase with the 
signals TD.sub.0 to TD.sub.7. 
The control signals CD.sub.0 to CD.sub.7 are supplied to the output buffers 
34.sub.0 to 34.sub.7. These buffers are enable when the enable signal OE 
is "0" to output the data from the memory cells to an external device. The 
buffers produce signals at an intermediate potential when the signal OE is 
"1". In this description, OE="0" is assumed. On receiving the signals 
CD.sub.0 to CD.sub.7, the output buffers 34.sub.0 to 34.sub.7 output data 
output signals D.sub.0 to D.sub.7 which are sequentially changed to "0" 
("L" level) during the enable period TE (reference is to be made to (P) to 
(S) of FIG. 14). 
When the enable period is finished and the read data items from the memory 
cells are determined, the buffers output the data items from the memory 
cells, namely, the signals D.sub.0 to D.sub.7 which are in phase with the 
output signals TD.sub.0 to TD.sub.7. 
The embodiment of the present invention includes, like the conventional 
semiconductor device, data latches therein. Therefore, before the data 
latch enable period T.sub.DL is started, the data items latched in the 
data latches before the enable of the amplifiers 32.sub.0 to 32.sub.7 are 
outputted as the signals TD.sub.0 to TD.sub.7 (reference is to be made to 
(J) and (K) of FIG. 13). 
Referring to FIGS. 11A and 13, description will be given in more detail of 
operation of the control circuits 33.sub.0 to 33.sub.7. At start of the 
read operation, when the signal TSA2 is altered from "0" to "1" at time tc 
as shown in (A) of FIG. 13, the delay circuit 41 delays the signals TSA2 
for a preset delay period of time to thereby produce signals DL.sub.0 to 
DL.sub.7 as shown in (B) to (E) of FIG. 13 (j=7 in this case). 
The NAND circuit 42 receives as inputs thereto the signals DL.sub.0 to 
DL.sub.7 from the delay circuit 41 and the enable signal TSA2 and then 
produces and supplies an output signal SN.sub.20 to the data output switch 
circuit 44. The signals SI.sub.q (q=0 to 7) from the inverter 43 are 
changed from "0" to "1" at the same time together with the signal DL.sub.q 
from the delay circuit 41 as indicated by (F) to (I) of FIG. 13. When the 
signal TSA2 is varied from "1" to "0", these signals SI.sub.q are altered 
from "1" to "0" at the same time. The signals SI.sub.q and the output 
signals TD.sub.q are fed to the switch circuit 44. 
Operation of the data output switch circuit 44 will be now described. The 
circuit 44 is constructed as shown in FIG. 11B in which when the signal 
SI.sub.q is varied to "1" at the sense amplifier enable, the inverter 
output signal S.sub.20 is set to "0" and hence the transistor T.sub.N21 
becomes nonconductive. Moreover, since the transistors T.sub.P20 and 
T.sub.N22 receiving the signal SI.sub.q via the respective gates are 
respectively nonconductive and conductive, the output buffer control 
signals are set to "0" ("L" level). 
Since the signal SI.sub.q is "0" during the sense amplifier nonactive 
period, the transistors T.sub.P20 and T.sub.N21 are conductive and hence 
the transistors T.sub.P21 and T.sub.N20 operate as an inverter. In this 
state, the transistor T.sub.N22 is nonconductive. 
Consequently, the phase of the signal TD.sub.q is reversed by the inverter 
441 and then is again inverted by a circuit including T.sub.P21 and 
T.sub.N20 to be delivered from the drain thereof as the output buffer 
control signals CD.sub.q. Therefore, the signals CD.sub.q are in phase 
with the signals TD.sub.q. Waveforms of signals CD.sub.0 to CD.sub.7 are 
shown in (L) to (O) of FIG. 13. 
Shown in (J) of FIG. 13 are the output signals TD.sub.0 to TD.sub.3 of 
which the data value is "1". Similarly, the output signals TD.sub.4 to 
TD.sub.7 are shown in (K) of FIG. 13 of which the data value is changed 
from "1" to "0" when the data latch enable period T.sub.DL is initiated. 
The control signals CD.sub.0 to CD.sub.7 in this state are shown in (L) to 
(O) of FIG. 13 in which the values thereof are sequentially altered from 
"1" to "0" with a difference of time therebetween. When the enable period 
TE is completed and the sense amplifier nonactive period is commenced, the 
values are changed to the data value of signals TD.sub.0 to TD.sub.7. 
Namely, when the sense amplifier nonactive period is started, the signals 
CD.sub.0 to CD.sub.3 are changed from "0" to "1", whereas the signals 
CD.sub.4 to CD.sub.7 are kept retained at "0". 
In FIG. 13, since the sense amplifier output signals TD.sub.0 to TD.sub.7 
are "1" before the sense amplifiers are enable, the values of CD.sub.0 to 
CD.sub.7 are varied from "1" to "0" at initiation of the sense amplifier 
enable period. However, when either one of the sense amplifier output 
signals TD.sub.q (q=0 to 7) is "0" before the sense amplifier enable is 
commenced, the value of the associated signals CD.sub.q (q=0 to 7) is kept 
fixed at "0". 
Referring next to FIGS. 12 and 14, description will be given in detail of 
operation of the output buffers 34.sub.o to 34.sub.j (j=7 in this case). 
In the nonactive state of buffers 34.sub.o to 34.sub.j, i.e., when the 
enable signal BOB is "1", the inverter output signal S.sub.50 is "0" in 
the output buffers 34.sub.q (q=0 to 7), the NAND output signals S.sub.51 
is "1", and the NOR output signal S.sub.52 is "0". Therefore, the 
transistors T.sub.P50 and T.sub.N50 are nonconductive and the output 
signals D.sub.q are at an intermediate potential. 
On the other hand, in the active state of the buffers 34.sub.q, namely, 
when the enable signal BOB is "0", the inverter output signal S.sub.50 is 
"1" and the phase of the NAND output signals S.sub.51 and NOR output 
signal S.sub.52 is opposite to that of the control signals CD.sub.q. 
Therefore, the output signals D.sub.q are in phase with the signals 
CD.sub.q. 
Shown in (P) to (S) of FIG. 14 are waveforms of the signals D.sub.0 to 
D.sub.7 corresponding to the control signals CD.sub.0 to CD.sub.7 in (L) 
to (O) of FIG. 13. In this connection, the waveforms of FIG. 14 are 
obtained when the enable signal BOB is "0", i.e., in the output buffer 
activate state. The data value before the sense amplifier enable is "1". 
In response to the enable of sense amplifiers, the signals D.sub.0 to 
D.sub.7 are consecutively varied from "1" to "0" with a difference of time 
t.sub.o. When the active period TE is completed and the sense amplifier 
nonactive period is initiated, the data values of output signals TD.sub.0 
to TD.sub.7 are outputted. That is, D.sub.0 to D.sub.3 are changed from 
"0" to "1" as shown in (P) and (Q) of FIG. 14, whereas D.sub.4 to D.sub.7 
are kept remained at "0" as shown in (R) and (S) of FIG. 14. With the 
operation above, the read operation is completed. 
The delay time t.sub.o is set such that all of data output signals D.sub.0 
to D.sub.7 are changed to "0" during the data latch standby period 
(T.sub.s in (T) of FIG. 14). Moreover, according to an aspect of the 
embodiment, the signal D.sub.q is varied to "0" during the sense amplifier 
active period. Consequently, the output buffers 34.sub.q are required to 
be active at initiation of the sense amplifier active period. 
Referring now to FIG. 15, description will be given of advantages of the 
first embodiment in accordance with the present invention. In the first 
embodiment, as already described in conjunction with FIG. 14 and the like, 
the data output signals D.sub.q are forced to "0" during the sense 
amplifier active period TE. Therefore, regardless of the data values of 
sense amplifier output signals TD.sub.q, the signals D.sub.q are 
sequentially fixed during the period TE (reference is to be made to (A) 
and (D) of FIG. 15). In consequence, when the expected values of signals 
D.sub.q are "0", the output signals D.sub.q is maintained at "0". 
Thereafter, the data latch control signal TSAL shown in (B) of FIG. 15 is 
altered from "0" to "1" to initiate the data latch active period in which 
the signals TD.sub.q are varied from "1" to "0" as shown in (C) of FIG. 
15. After the control signal TSAL is changed from "1" to "0", the data 
latch active period T.sub.DL is terminated. 
During the sense amplified active period TE, when the signals D.sub.q 
before the sense amplifier enable are "1", the discharge current I.sub.N50 
delivered to the GND power source is as shown in (F) of FIG. 15 for one 
output buffer circuit since the data output signals D.sub.q are altered to 
"0" in a signal-by-signal manner or for each signal group as described 
above. Namely, when all signals D.sub.q are simultaneously varied from "1" 
to "0", the total value of discharge current flowing through the 
transistor T.sub.N50 of FIG. 12 of each output buffer 34.sub.q is 
dispersed as shown in (G) of FIG. 15. Accordingly, the peak value of 
I.sub.N50 is minimized when compared with the conventional semiconductor 
device and hence the deviation in the GND power source is suppressed as 
shown in (E) of FIG. 15. 
In the example of FIG. 15, thanks to provision of four signal groups, the 
magnitude of variation in the GND power source is lowered to about one 
quarter of that of the conventional semiconductor device. In short, a 
first advantage of the embodiment resides in that the noise of power 
source (deviation of GND power source) is suppressed to prevent any 
operation errors related to the noise. 
Moreover, a second advantage of the embodiment is as follows. The operation 
in which the data output signals D.sub.q (or the data output signal 
groups) are sequentially varied to "0" with a difference of time 
therebetween is carried out during the sense amplifier active period TE, 
particularly, during the data latch standby period. This solves the 
problem of delay in the read time due to the difference of time. This 
advantage removes the problem of the conventional semiconductor described 
in the Japanese Patent Laid-Open Publication Ser. No. 3-54795 in which a 
difference of time is provided when the sense amplifiers are enabled to 
disperse the discharge current so as to suppress the power source noise. 
In this connection, when the signals D.sub.q are fixed to "0" during the 
data latch standby period, it is possible to latch data in a stable state, 
which improves reliability of the data latch operation. Thanks to the 
first and second advantages, there is obtained higher reliability in the 
read operation when a plurality of data values are changed from "1" to "0" 
at the same time. 
Second Embodiment 
Next, the second embodiment will be described in accordance with the 
present invention. This embodiment differs from the first embodiment in 
the roles, functions, and circuit configurations of the control circuits 
33.sub.o to 33.sub.j and output buffers 34.sub.o to 34.sub.j. 
First, description will be given of the roles of the control circuits and 
the output buffers in the second embodiments. Each of the control circuits 
33.sub.o to 33.sub.j produces a control signal to alter, between the 
active and nonactive period of the pertinent sense amplifier (32.sub.o to 
32.sub.j), the capacitance of the n-channel MOS transistor of the final 
stage of the associated output buffer (34.sub.o to 34.sub.j). Moreover, 
the control circuit supplies the associated output buffer (34.sub.o to 
34.sub.j) with a signal which is "0" during the sense amplifier active 
period and which is in phase with readout data obtained by the pertinent 
sense amplifier (32.sub.o to 32.sub.j). 
The output buffers 34.sub.o to 34.sub.j output data items respectively 
supplied from the control circuits 33.sub.o to 33.sub.j in the output 
buffer active state. In this state, the output buffer enable signal BOB is 
"0". 
Subsequently, description will be given of functions of the control 
circuits 33.sub.o to 33.sub.j and the output buffers 34.sub.o to 34.sub.j. 
The control circuits 33.sub.o to 33.sub.j produce output buffer control 
signals CD.sub.oq (q=0 to j respectively corresponding to buffers 34.sub.o 
to 34.sub.j) which are "0" during the sense amplifier active period and 
which are "1" during the sense amplifier nonactive period. Moreover, the 
controllers generate output buffer control signals CD.sub.1q which are "0" 
during the active period and which are in phase with the signals TD.sub.q 
during the nonactive period. 
In the output buffer nonactive state, the buffers 34.sub.o to 34.sub.j 
produce the signals D.sub.q at an intermediate potential. In the output 
buffer active state, the buffers 34.sub.o to 34.sub.j produce the signals 
D.sub.q which are gradually set to "0" during the sense amplifier active 
period TE and which are in phase with the signals TD.sub.q during the 
sense amplifier nonactive period. 
Subsequently, description will be given of the circuit configurations of 
the control circuits 33.sub.o to 33.sub.j and the output buffers 34.sub.o 
to 34.sub.j. FIG. 16A shows in a circuit diagram the constitution of the 
second embodiment of the control circuit 33q (q=0 to j). The control 
circuit 33.sub.q includes an inverter 61 which receives the sense 
amplifier enable signal TSA2 to produce an output buffer control signal 
CD.sub.0q, and NAND circuit 62 which receives the signals CD.sub.0q and 
TD.sub.q and which creates a signal S.sub.70, and an inverter 63 which 
receives the signal S.sub.70 to output a buffer control signal CD.sub.1q. 
FIG. 16B shows the circuit layout of the second embodiment of the output 
buffer 34.sub.q. The buffer 34.sub.q includes an inverter 65 which 
receives the output buffer enable signal BOB and which produces a signal 
S.sub.71, an NAND circuit 66 which receives the signals CD.sub.1q and 
S.sub.71 to create a signal SP.sub.q, an NOR circuit 67 which receives the 
signals CD.sub.1q and BOB to output a signal SN.sub.1q, an inverter 68 
which inputs the signal CD.sub.0q to produce a signal S.sub.72, a transfer 
gate including a p-channel MOS transistor T.sub.P70 and an n-channel MOS 
transistor T.sub.N70 to produce a signal SN.sub.0q, an n-channel MOS 
transistor T.sub.N72, an n-channel MOS transistor T.sub.N73, a p-channel 
MOS transistor T.sub.P71, and an n-channel MOS transistor T.sub.N71. 
It is assumed that the combination of transistors T.sub.N71 and T.sub.N73 
performs almost the same as that of T.sub.N197 of the conventional 
semiconductor (FIG. 8B). Moreover, drains and sources respectively of the 
transistors T.sub.P70 and T.sub.N70 are respectively shared therebetween. 
Receiving the signal SN.sub.1q, the circuit produces a signal SN.sub.0q. 
The transistors T.sub.N72 and T.sub.N73 include gates respectively 
receiving the signals S.sub.72 and SN.sub.0q and sources connected to the 
GND potential (i.e., grounded). The transistor T.sub.N71 includes a gate 
input of the signal SN.sub.1q, a drain receiving the signal D.sub.q, and a 
source linked with the GND power source (grounded). The transistor 
T.sub.P71 includes a gate supplied with the signal SP.sub.q, a source 
receiving the V.sub.CC power source, and a drain coupled with the drains 
of transistors T.sub.N73 to T.sub.N71. 
Next, description will be given of an outline of operation of the second 
embodiment in accordance with the present invention. FIG. 17 shows the 
waveforms of primary signals before, during, and after the active period 
of sense amplifiers 32q. When a read operation is started and the signals 
TSA2 ((A) of FIG. 17) is altered from "0" to "1", all signals CD.sub.0q 
from the controllers 33.sub.q are varied from "1" to "0" ((E) of FIG. 17). 
At the same time, the signals CD.sub.1q from the controllers 33.sub.q are 
changed from the values thereof before the sense amplifier enable to "0" 
as shown in (F) and (G) of FIG. 17. In this case, the control signals 
CD.sub.1q include four signals CD.sub.10 to CD.sub.13 and four signals 
CD.sub.14 to CD.sub.17. 
In this situation, when the output buffers 34.sub.q are in the active state 
(the enable signal BOB is "0"), the levels of the signals D.sub.q 
gradually approach to "0" in response to control signals CD.sub.0q and 
CD.sub.1q ((N) and (O) of FIG. 17). 
When the active period TE is finished and the signal TSA2 is changed from 
"1" to "0", the control signals CD.sub.0q are varied from "0" to "1" as 
shown in (E) of FIG. 17. At the same time, the control signals CD.sub.1q 
are altered from "0" to a value in phase with the output signals TD.sub.q 
as shown in (F) and (G) of FIG. 17. When the buffers 34.sub.q are in the 
active state in this situation, the output signals D.sub.q are set to 
values in phase with the output signals TD.sub.q, namely, the data values 
read from the memory cells during the active period of sense amplifiers 
32.sub.q. 
As above, according to an aspect of the embodiment, the data output signal 
D.sub.q are gradually altered to "0" during the sense amplifier active 
period TE such that the data obtained during the active period is 
outputted when the active period is terminated. Therefore, at initiation 
of the sense amplifier active period, the output buffers 34.sub.q are 
required to be enabled. 
Referring now to the circuits shown in FIGS. 16A and 16B and the waveforms 
of FIG. 17, description will be given in detail of operation of the second 
embodiment. In the controllers 33.sub.q of FIG. 16A, since the signal TSA2 
is "1" during the active period TE, the control signals C.sub.0q from the 
inverter 61 are "0" as shown in (E) of FIG. 17. In this state, the signal 
S.sub.70 from the NAND circuit 62 is "1". The phase of the signal S.sub.70 
is then reversed by the inverter 63 into control signals CD.sub.1q which 
are "0" as shown in (F) and (G) of FIG. 17. 
When the active period TE is completed, the signals TSA2 are set to "0" and 
hence the control signals CD.sub.0q are changed to "1" ((E) of FIG. 17). 
On this occasion, since the phase of signal S.sub.70 is opposite to that 
of the output signals TD.sub.q, the control signals CD.sub.1q are in phase 
with the signals TD.sub.q. Assume that among the sense amplifier output 
signals TD.sub.q including TD.sub.0 to TD.sub.7, the signals TD.sub.0 to 
TD.sub.3 are "1" ((C) of FIG. 17) and the signals TD.sub.4 to TD.sub.7 are 
changed from "1" to "0" ((D) of FIG. 17). The output control signals 
CD.sub.1q are produced in this case as follows. The signals CD.sub.10 to 
CD.sub.13 are "1" ((F) of FIG. 17) and the signals CD.sub.14 to CD.sub.17 
are changed to "0" ((G) of FIG. 17). 
Assume in the buffers 34.sub.q of FIG. 16B that the signal BOB is "0" and 
the buffers 34.sub.q are in the active state. The signal. S.sub.71 is 
obtained by reversing the phase of the signal BOB by the inverter 65 and 
is therefore "1". During the active period TE, the control signals 
CD.sub.0q are "0" ((E) of FIG. 1 7) and the signal S.sub.72 attained by 
inverting the phase of CD.sub.0q by the inverter 68 is "1". As a result, 
the transistors T.sub.P70 and T.sub.N70 are nonconductive and the 
transistor T.sub.N72 is conductive. 
Consequently, the drain potential (signal SN.sub.0q) of T.sub.N72 is "0" 
((L) and (M) of FIG. 17) during the active period TE. The transistor 
T.sub.N73 receiving SN.sub.N0q via its gate is nonconductive. 
Additionally, since the control signals CD.sub.1q are "0" as described 
above, the signal SP.sub.q from the NAND circuit 66 is set to "1" ((H) and 
(J) in FIG. 17). The transistor T.sub.P71 receiving SP.sub.q via its gate 
is nonconductive. 
At the same time, the signal SN.sub.1q from the NOR circuit 67 is "1" ((I) 
and (K) of FIG. 17) during the active period TE and hence the transistor 
T.sub.N71 is conductive. Resultantly, a discharge current is delivered 
through the drain and source of the transistor T.sub.N71 and the data 
output signals D.sub.q from the buffers 34.sub.q become "0". 
As above, the performance of the transistors T.sub.N71 and T.sub.N73 is 
assumed to be substantially equal to that of the n-channel MOS transistor 
(T.sub.N197 of FIG. 8B) in the final output stage of the conventional 
semiconductor device. Moreover, it is assumed that the transistors 
T.sub.N73 and T.sub.N71 respectively have gate lengths of about 200 
micrometers and about 100 micrometers when the transistor T.sub.N197 has a 
gate length of about 300 micrometers in this embodiment (the gate widths 
thereof are substantially identical to each other). That is, during the 
sense amplifier active period in which only the transistor T.sub.N71 is 
conductive, the capability of lowering the levels of data output signals 
D.sub.q to "0" is assumed in this embodiment to be only about one third of 
that of the conventional semiconductor. 
In this embodiment, therefore, the signals D.sub.q are gradually changed to 
"0" ((N) and (O) of FIG. 17) during the active period TE in a period of 
time which is about three times that of the conventional semiconductor 
device. The period of time necessary to alter the signals D.sub.q from "1" 
to "0" is arbitrarily varied in accordance with the specifications of 
performance of the transistors T.sub.N73 and T.sub.N71. 
When the active period TE is completed, the control signals CD.sub.0q is 
"1" and the signal S.sub.72 is "0". As a result, the transistors T.sub.P70 
and T.sub.N70 are conductive and the transistor T.sub.N72 is 
nonconductive. 
In addition, output as the control signals CD.sub.1q are the data items 
read from the memory cells during the active period TE, namely, the sense 
amplifier output signals TD.sub.q. Therefore, as shown in (H) and (K) of 
FIG. 17, the phase of signals SP.sub.q from the NAND circuit 66 and that 
of signals SN.sub.1q from the NOR circuit 67 are opposite to the phase of 
the readout data items (output signals TD.sub.q). In this situation, since 
the transfer gate including T.sub.P70 and T.sub.N70 is conductive, the 
signals SN.sub.1q appear as signals SN.sub.0q through the transfer gate. 
Namely, the phase of signals SN.sub.0q are also opposite to that of the 
readout data items as shown in (L) and (M) of FIG. 17. 
In consequence, when the anti-phase signal of the readout data item is "1", 
the transistor T.sub.P71 is nonconductive and the transistors T.sub.N71 
and T.sub.N73 are conductive and hence a discharge current is fed through 
the transistors T.sub.N71 and T.sub.N73 and the data output signals 
D.sub.q become "0". On the other hand, when the anti-phase signal of the 
readout data item is "0", the transistor T.sub.P71 is conductive and the 
transistors T.sub.N71 and T.sub.N73 are nonconductive and hence the power 
source voltage V.sub.CC is supplied from the transistor T.sub.N71 and the 
data output signals D.sub.q are "1". In short, during the sense amplifier 
nonactive period, the data output signals D.sub.q take a logical value 
equal to that of data items read from the memory cells (signals TD.sub.q). 
Moreover, the performance of the final output stage is substantially equal 
to that of the conventional semiconductor device. 
In the example of FIG. 17, the data latch control signal TSAL of (B) of 
FIG. 17 is altered from "0" to "1" during the sense amplifier active 
period TE such that when the data latch active period is commenced, the 
output signals TD.sub.0 to TD.sub.3 are retained at "1" ((C) of FIG. 17) 
and the output signals TD.sub.4 to TD.sub.7 are varied from "1" to "0" 
((D) of FIG. 17). The data latch active period T.sub.DL is completed when 
the signal TSAL is changed from "1" to "0". 
In this case, during the active period TE, the signals D.sub.0 to D.sub.3 
and D.sub.4 to D.sub.7 are changed to "0" ((N) and (O) of FIG. 17). 
Consequently, when the period TE is finished, the signals D.sub.0 to 
D.sub.3 are altered from "0" to "1", i.e., the level of the signals 
TD.sub.0 to TD.sub.3 ((N) of FIG. 17). The signals D.sub.4 to D.sub.7 are 
maintained at "0", i.e., the level of the signals TD.sub.4 to TD.sub.7 
((O) of FIG. 17). The read operation is terminated at this point. 
In the output buffer nonactive state, namely, when the output buffer enable 
signal BOB is "1", the signals SP.sub.q are "1" and the signals SN.sub.0q 
and SN.sub.1q are "0". Therefore, the transistors T.sub.N71, T.sub.N73 and 
T.sub.P71 are nonconductive and the data output signals D.sub.q are at an 
intermediate potential. 
The second embodiment of the present invention has the same advantages as 
those of the first embodiment. In the second embodiment, as can be seen 
from (N) and (O) of FIG. 17, all data output signals D.sub.q are gradually 
changed to "0" in a relatively long period of time during the sense 
amplifier active period TE. In this operation, the discharge current fed 
through the transistor T.sub.N71 (FIG. 16B) is slowly, i.e., not abruptly, 
altered as shown in ((Q) of FIG. 17). This prevents the event in which the 
discharge current is abruptly delivered to the GND power source when a 
plurality of data output signals D.sub.q are simultaneously varied from 
"1" to "0". The variation in the GND potential can, as a result, be 
suppressed as shown in (P) of FIG. 17. 
In short, a first advantage of the second embodiment is to minimize the 
noise in the power source so as to prevent any operation errors due to 
such noise. A second advantage thereof is that the operation error due to 
the noise appearing in the power source can be prevented without lowering 
the read speed. 
Third Embodiment 
Description will now be given of the third embodiment in accordance with 
the present invention. In the first embodiment, description has been given 
of a case in which noise components easily appear in the GND power source 
and the data values are changed from "1" to "0" are treated. In contrast 
therewith, in accordance with the third embodiment which is a variation of 
the first embodiment, noise components easily appear in the V.sub.CC power 
source and operation errors taking place when the data values are altered 
from "0" to "1" are prevented by configuring the control circuits 33.sub.o 
to 33.sub.j to sequentially vary the output buffer control signals 
CD.sub.q to "1" during the sense amplifier active period. 
Therefore, the role, function, and circuit configuration of the control 
circuits 33.sub.o to 33.sub.j of this embodiment are different from those 
of the first embodiment. In the third embodiment, the control circuits 
33.sub.o to 33.sub.j produce the control signals CD.sub.q which are varied 
to be fixed to "1" with a predetermined difference of time therebetween 
during the active period of the amplifiers 32.sub.0 to 32.sub.7. During 
the nonactive period thereof, the controllers create the signals CD.sub.q 
having data values acquired by the amplifiers 32.sub.o and 32.sub.j. The 
signals CD.sub.q are sent to the output buffers 34.sub.o to 34.sub.j. 
Moreover, the controllers 33.sub.o to 33.sub.j of the third embodiment 
function to change the signals CD.sub.q to a fixed value "1" with a preset 
difference of time therebetween during the active period of the amplifiers 
32.sub.0 to 32.sub.7. During the nonactive period thereof, the controllers 
create the signals CD.sub.q which are in phase with the output signals 
TD.sub.q. 
The structure of controllers 33.sub.o to 33.sub.j of the embodiment is the 
same as that shown in FIG. 11A excepting the data output switch circuit 44 
and hence description will be given of the circuit construction of the 
switch circuit 44. FIG. 18A shows the circuit of the data output switch 
circuit used in the control circuits 33.sub.o to 33.sub.j of the third 
embodiment. As can be seen from FIG. 18A, the circuit 44 includes an 
inverter 71 which receives the signals SI.sub.q to produce a signal 
S.sub.90, a p-channel MOS transistor T.sub.P90 including a source of the 
V.sub.CC power source, a gate input of the signal SI.sub.q, and a drain 
linked with a node V.sub.90, a p-channel MOS transistor T.sub.P91 
including a source coupled to the node V.sub.90, a gate input of the 
signal TD.sub.q, and a drain output of a signal S.sub.91, an n-channel MOS 
transistor T.sub.N90 including a drain input of the signal S.sub.91, a 
gate input of the signal TD.sub.q, and a source linked with a node 
V.sub.91, an n-channel MOS transistor T.sub.N91 including a drain 
connected to the node V.sub.91, a gate input of the signal S.sub.90, and a 
source coupled with the GND potential, an n-channel MOS transistor 
T.sub.N92 including a drain input of the signal S.sub.91, a gate input of 
the signal SI.sub.q, and a source coupled with the GND power source, and 
an inverter 72 which receives the signal S.sub.91 to produce output buffer 
control signals CD.sub.q. 
Subsequently, referring to FIG. 18B showing waveforms of primary signals 
before, during, and after the sense amplifier active period, description 
will be given of operation of the data output switch circuit of the third 
embodiment in accordance with the present invention. When a read operation 
is commenced and the sense amplifier enable signal TSA2 (FIG. 18B) is 
altered from "0" to "1", the signals SI.sub.q are changed from "0" to "1" 
with a difference of time therebetween in a signal-by-signal fashion. In 
this connection, the signals may be classified into signal groups such 
that the signal alteration sequentially takes place for each signal group. 
In FIGS. 18A and 18B, the system includes eight data output signals 
D.sub.0 to D.sub.7 and the signals SI.sub.0 and SI.sub.1 are varied from 
"0" to "1" with delay of time "0", namely, at initiation of the sense 
amplifier active period as indicated by SI.sub.0,1, in FIG. 18B. 
Similarly, as respectively designated by SI.sub.2,3, SI.sub.4,5, and 
SI.sub.6,7 in FIG. 18B, the signals SI.sub.2 and SI.sub.3, SI.sub.4 and 
SI.sub.5, and SI.sub.6 and SI.sub.7 are changed from "0" to "1" with delay 
of time t.sub.o, 2t.sub.o, and 3t.sub.o, respectively. 
As can be seen from FIG. 18B, the output signals TD.sub.0 to TD.sub.3 are 
maintained at "0". During the sense amplifier active period TE, when the 
control signal TSAL is changed from "0" to "1" to start the data latch 
active period, the signals TD.sub.4 to TD.sub.7 are altered from "0" to 
"1". 
In the period TE in which the signal TSA2 is "1", when the data input 
switch signals SI.sub.q (SI.sub.0 to SI.sub.7 in the example of FIG. 18B) 
are set to "1" as above, the transistor T.sub.P90 receiving the signals 
SI.sub.q via its gate is nonconductive and the transistor T.sub.N92 is 
conductive (FIG. 18A). 
Moreover, the phase of the switch signals SI.sub.q is reversed by the 
inverter 71 to produce an output signal S.sub.90 having a value of "0" and 
hence the transistor T.sub.N91 receiving the signal S.sub.90 via its gate 
is nonconductive. Since the transistor T.sub.N92 is conductive, the drain 
potential thereof, namely, the signal S.sub.91 is changed to "0". The 
phase of signal S.sub.91 is reversed by the inverter 72 to create output 
buffer control signals CD.sub.q (CD.sub.0 to CD.sub.7 in the example of 
FIG. 18B) of which the data value is "1". 
After the period TE is terminated and the input signals SI.sub.q are "0" 
(FIG. 18B), the transistor T.sub.P90 is conductive and the transistor 
T.sub.N92 is nonconductive, which makes the transistor T.sub.N91 
conductive. Therefore, since a combination of transistors T.sub.P91 and 
T.sub.N90 serves as an inverter, the phase of signal S.sub.91 is opposite 
to that of signals TD.sub.q, namely, the signals CD.sub.q are in phase 
with the signals TD.sub.q as shown in FIG. 18B. 
The signals CD.sub.q are respectively fed to the output buffers 34.sub.q. 
On receiving the signals CD.sub.q, the buffers 34.sub.q produce, in the 
output buffer active state, data output signals D.sub.q which are in phase 
with the control signals CD.sub.q. In other words, during the period TE, 
the signals D.sub.q are changed to "1" with a predetermined difference of 
time therebetween in a signal-by-signal fashion or for each signal groups, 
each signal group including a plurality of output signals D.sub.q as 
above. During the sense amplifier nonactive period, the signals D.sub.q 
are in phase with the signals TD.sub.q, i.e., the data items read from the 
memory cells. 
Next, description will be given of a feature and advantages of the third 
embodiment. In this embodiment, the data output signals D.sub.q are 
changed to "1" with a difference of time therebetween during the sense 
amplifier active period TE. Therefore, the discharge current appearing 
when a plurality of data output signals D.sub.q are varied from "0" to "1" 
can be dispersed to thereby prevent the deviation in the V.sub.cc power 
source. Consequently, a first advantage of the third embodiment is to 
suppress the noise in the power source (deviation in the potential of 
V.sub.cc power source) to prevent operation errors associated with the 
noise. A second advantage thereof is to prevent operation errors due to 
the noise without decreasing the read speed. 
Fourth Embodiment 
Next, description will be given of the fourth embodiment in accordance with 
the present invention. In the description of the second embodiment, there 
easily appear noise components in the GND power source and the data values 
are changed from "1" to "0". In accordance with the fourth embodiment 
which is a variation of the second embodiment, noise components easily 
appear in the V.sub.cc power source and operation errors occurring when 
the data values are altered from "0" to "1" are prevented by configuring 
the control circuits 33.sub.o to 33.sub.j to gradually alter the output 
buffer control signals CD.sub.q to "1" during the sense amplifier active 
period. 
Therefore, the role, function, and circuit structure of the control 
circuits 33.sub.o to 33.sub.j vary between the fourth and second 
embodiments. 
In the fourth embodiment, the control circuits 33.sub.o to 33.sub.j produce 
the control signals CD.sub.q which vary, between the sense amplifier 
active and nonactive periods, the capacitance of the p-channel MOS 
transistor of the final stage in each of the output buffers 34.sub.o to 
34.sub.j. The controllers further create signals which are "1" during the 
sense amplifier active period and which are in phase with the data items 
attained by the amplifiers 32.sub.o 32.sub.j during the sense amplifier 
nonactive period. The signals are then supplied to the output buffers 
34.sub.o to 34.sub.j. 
The role of output buffers 34.sub.o to 34.sub.j of the fourth embodiment 
are the same as that of the second embodiment. Namely, in the output 
buffer active state (i.e., when the enable signal BOB is "0"), the buffers 
34.sub.o to 34.sub.j output data items from the controllers 33.sub.o and 
33.sub.j to an external device. 
Subsequently, the controllers 33.sub.o to 33.sub.j of the fourth embodiment 
function to create output buffer signals CD.sub.0q (q=0 to j respectively 
corresponding to output buffers 34.sub.o to 34.sub.j) which are "0" during 
the amplifier active period and which are "1" during the amplifier 
inactive period. The controllers further produce output buffer signals 
CD.sub.1q which are "1" during the amplifier active period and which are 
in phase with the output signals TD.sub.q during the amplifier inactive 
period. 
The output buffers 34.sub.o to 34.sub.j generate, in the output buffer 
inactive state, the data output signals D.sub.q at an intermediate 
potential. In the output buffer active state, the buffers output the data 
output signals D.sub.q which are gradually changed to "1" during the sense 
amplifier active period and which are in phase with the output signals 
TD.sub.q during sense amplifier inactive period. 
Subsequently, description will be given of the circuit structure of the 
controllers 33.sub.o to 33.sub.j and output buffers 34.sub.o to 34.sub.j 
of the embodiment. As can be seen from FIG. 19A, the control circuit 
33.sub.q includes an inverter 74 which receives the signal TSA2 to produce 
output buffer control signals CD.sub.0q, an NOR circuit 75 which receives 
the signals TSA2 and TD.sub.q to produce a signal S.sub.102, and an 
inverter 76 which receives the signal S.sub.102 to create an output buffer 
control signal CD.sub.1q. 
Referring now to FIGS. 19A and 20, operation of the control circuit 
33.sub.q will be described. During the sense amplifier active period TE, 
the signal TSA2 is "1" ((A) of FIG. 20) and hence the control signals 
CD.sub.0q from the inverter 74 of FIG. 19A are "0" ((E) of FIG. 20) and 
the signal S.sub.102 from the NOR circuit 75 of FIG. 19A is "0". 
Therefore, the control signals CD.sub.1q are "1" as shown in (F) and (G) 
of FIG. 20. In this case, the output buffer control signals include two 
4signal groups, i.e., CD.sub.10 to CD.sub.13 and CD.sub.14 to CD.sub.17. 
When the period TE is terminated, the signal TSA2 is "0" ((A) of FIG. 20) 
and hence the signals CD.sub.0q are changed to "1" ((E) of FIG. 20). 
Simultaneously, the phase of signal S.sub.102 from the NOR circuit 75 is 
opposite to that of the signals TD.sub.q ((C) and (D) of FIG. 20) and the 
signals CD.sub.1q are in phase with the signals TD.sub.q as shown in (F) 
and (G) of FIG. 20. 
Next, description will be given of the circuit structure of the output 
buffers 34.sub.q (34.sub.o to 34.sub.j). FIG. 19B shows in a circuit 
diagram the construction of the output buffers 34.sub.q in the fourth 
embodiment in accordance with the present invention. As can be seen from 
FIG. 19B, the buffer 34q includes an inverter 78 which receives the signal 
BOB to create a signal S.sub.100, an NAND circuit 79 which receives the 
signals CD.sub.iq and S.sub.100 to generate a signal SP.sub.1q, an NOR 
circuit 80 which receives the signals CD.sub.1q and BOB to produce a 
signal SN.sub.q, an inverter 81 which receives the signal CD.sub.0q to 
create a signal S.sub.101, p-channel MOS transistors T.sub.P100, 
T.sub.P01, T.sub.P102, and T.sub.P103, and n-channel MOS transistors 
T.sub.N100 and T.sub.N101. 
The transistors T.sub.P100 and T.sub.N100 configure a transfer gate in 
which drains and sources are respectively shared therebetween. The 
transfer gate receives the signal SP.sub.1q to generate a signal 
SP.sub.0q. The transistor T.sub.P102 includes a source connected to the 
V.sub.cc potential, a gate input of the signal CD.sub.oq, and a drain 
output of the signal SP.sub.oq. The transistor T.sub.P101 includes a 
source linked with the V.sub.cc power source, a gate input of the signal 
SP.sub.1q, and a drain output of the signal D.sub.q. The transistor 
T.sub.P103 includes a source coupled with the V.sub.cc power source, a 
gate input of the signal SP.sub.0q, and a drain output of the signal 
D.sub.q. Additionally, the transistor T.sub.N101 includes a gate input of 
the signal SN.sub.q, a source connected to the GND potential, and a drain 
coupled with the drains respectively of the transistors T.sub.P103 and 
T.sub.P101. It is assumed that the total performance of T.sub.P103 and 
T.sub.P101 is substantially the same as that of T.sub.P195 of the 
conventional semiconductor device (FIG. 8B). 
In the second embodiment, all data output signals Dq are gradually altered 
to "0" during the sense amplifier active period. In contrast therewith, 
according to a feature of operation of the output buffers 34.sub.q in the 
fourth embodiment, the data output signals D.sub.q are gradually altered 
to "1" during the sense amplifier active period such that the data 
obtained during the active period is outputted when the active period is 
terminated. However, the output buffers 34.sub.q are required, as in the 
second embodiment, to be enable at initiation of the sense amplifier 
active period. 
Subsequently, operation of the output buffers 34.sub.q shown in FIG. 19B 
will be described by referring to waveforms of primary signals before, 
during, and after the active period of the output buffers 34.sub.q. Assume 
that the output buffer enable signal BOB is "0" and the output buffers 
34.sub.q are accordingly active. In this situation, the signal S.sub.100 
from the inverter 78 (FIG. 19B) is "1". As described above, the signals 
CD.sub.0q are "0" ((E) of FIG. 20) during the sense amplifier active 
period TE. The signal S.sub.101 created by reversing the phase of the 
signals CD.sub.0q via the inverter 81 is "1". Consequently, the transistor 
T.sub.P100 is nonconductive, the transistor T.sub.N100 receiving the 
signals CD.sub.0q via its gate is nonconductive and the transistor 
T.sub.P102 is conductive. Therefore, the gate of T.sub.P103 is connected 
via T.sub.P102 to the V.sub.cc potential and the signal SP.sub.0q is "1", 
which makes the transistor T.sub.P103 nonconductive. 
On the other hand, since the signals CD.sub.1q are "1" during the active 
period TE as above, the signals SP.sub.1q (SP.sub.10 to SP.sub.17 in the 
example of FIG. 20) from the NAND circuit are "0" as shown in (I) and (K) 
of FIG. 20. The transistor T.sub.P101 receiving the signals SP.sub.1q via 
its gate is conductive. Similarly, since the signals CD.sub.1q are "1", 
the signals SN.sub.q (SN.sub.0 to SN.sub.7 in the example of FIG. 20) from 
the NOR circuit 80 are "0" as shown in (H) and (J) of FIG. 20. The 
transistor TN.sub.101 receiving the signals SN.sub.q via its gate is 
nonconductive. 
As described above, the comprehensive performance of T.sub.P101 and 
T.sub.P103 is assumed to be substantially equal to the p-channel MOS 
transistor (T.sub.P195 of FIG. 8B) in the final output stage of the 
conventional semiconductor device. In consequence, during the period TE in 
which only the transistor T.sub.P101 is conductive in this embodiment, the 
capability to raise the data output signals D.sub.q to "1" is less than 
that of the semiconductor device of the prior art. Therefore, in 
accordance with the fourth embodiment, during the sense amplifier active 
period TE, the data output signals D.sub.q (D.sub.o to D.sub.7 in the 
example of FIG. 20) are changed to "1" as shown in (O) and (P) of FIG. 20 
in a longer period of time when compared with the conventional 
semiconductor device. 
In this connection, the period of time required to vary the signals D.sub.q 
to "1" can be arbitrarily changed in accordance with specifications of 
performance of transistors T.sub.P101 and T.sub.P103. 
When the active period TE is completed, the signals CD.sub.0q are "1" ((E) 
of FIG. 20) and the signal S.sub.101 is "0". Consequently, the transistors 
T.sub.P100 and T.sub.N100 are conductive and the transistor T.sub.P102 is 
nonconductive. 
Additionally, outputted as the signals CD.sub.1q are the data items 
obtained from the memory cells during the period TE, namely, the signals 
TD.sub.q. Therefore, the phase of signals SP.sub.1q and SN.sub.q 
respectively from the NAND and NOR circuits 79 and 80 is opposite to that 
of the obtained data items (signals TD.sub.q) as shown in (H) to (K) of 
FIG. 20. 
In this situation, since the transfer gate including T.sub.P100 and 
T.sub.N100 is conductive, the signal SP.sub.1q is delivered as the signal 
SP.sub.0q via the transfer gate. As a result, the phase of signals 
SP.sub.0q is also opposite to the acquired data items (signals TD.sub.q) 
as shown in (M) and (N) of FIG. 20. 
In consequence, when the signals attained by inverting the phase of the 
readout data items are "0", the transistor T.sub.N101 is nonconductive and 
the transistors T.sub.P101 and T.sub.P103 are conductive. This allows the 
charge current to flow through the transistors T.sub.P101 and T.sub.P103 
and hence the signals D.sub.q become "1". On the other hand, when the 
anti-phase signals attained by inverting the phase of the readout data 
items are "1", the transistor T.sub.N101 is conductive and the transistors 
T.sub.P101 and T.sub.P103 are nonconductive. This allows the charge 
current to pass through the transistor T.sub.N101 and hence the signals 
D.sub.q are "0". In short, during the sense amplifier inactive period, the 
signals D.sub.q have the same logical value as the data items (signals 
TD.sub.q) read from the memory cells and the performance of the final 
output stage is almost the same as that of the conventional semiconductor. 
In the example of FIG. 20, it is assumed that when the signal TSAL is 
varied during the active period TE from "0" to "1" ((B) of FIG. 20) to 
commence the data latch active period, the output signals TD.sub.0 to 
TD.sub.3 are maintained at "0" ((C) of FIG. 20) and signals TD.sub.4 to 
TD.sub.7 are altered from "0" to "1" ((D) of FIG. 20). After the signal 
TSAL is changed from "1" to "0", the data latch active period T.sub.DL is 
terminated. 
In this case, the data output signals D.sub.0 to D.sub.3 and D.sub.4 to 
D.sub.7 are varied as shown in (O) and (P) of FIG. 20 during the active 
period TE. Consequently, when the period TE is finished, the signals 
D.sub.0 to D.sub.3 are altered from "1" to "0", namely, the level of 
signals TD.sub.0 to TD.sub.3 ((O) of FIG. 20); whereas the signals D.sub.4 
to D.sub.7 are maintained at "1", i.e., the level of signals TD.sub.4 to 
TD.sub.7 ((P) of FIG. 20). The read operation is completed in this way. 
Incidentally, in the output buffer inactive state, namely, when the output 
buffer enable signal BOB is "1", the signals SP.sub.0q and SP.sub.1q are 
"1" and the signals SN.sub.q are "0" in FIG. 19B, and hence the 
transistors T.sub.P101, T.sub.103, and T.sub.N101 are nonconductive and 
the signals D.sub.q are, as a result, set to an intermediate potential. 
As above, in accordance with an aspect of the fourth embodiment of the 
present invention, the data output signals D.sub.q are gradually varied to 
"1" during the sense amplifier active period TE such that the data items 
acquired from the memory cells during the active period are output after 
the active period is terminated. Since only the transistor T.sub.P101 is 
conductive during the period TE, the charge current delivered through the 
transistor T.sub.P101 is slowly altered as shown in (R) of FIG. 20. 
Therefore, when a plurality of data output signals D.sub.q are 
simultaneously changed from "0" to "1", the peak value of the charge 
current from the V.sub.cc power source can be minimized, which suppresses 
the variation in the V.sub.cc potential to thereby prevent operation 
errors due to the variation in the V.sub.cc power source. 
In this connection, as in the second embodiment, the output buffers 
34.sub.q are required to be enable at the initiation of the sense 
amplifier active period TE. The fourth embodiment of the present invention 
has two advantages as follows. A first advantage is to decrease noise 
components in the source power (fluctuation in the V.sub.cc power) to 
prevent operation errors associated with the noise components. A second 
advantage is to prevent the operation errors related to the noise without 
decreasing the read speed. 
Embodiment 
Another embodiment of the present invention will be next described. Assume 
in FIG. 14 related to the first embodiment that the sense amplifier active 
period TE is 30 nanoseconds (ns), the delay time t.sub.o is 5 ns, the data 
latch standby period T.sub.s is 20 ns, and the data latch active period 
T.sub.DL is 5 ns. Relative to the point of time when the sense amplifier 
enable signal TSA2 is varied from "0" to "1", the period of time (delay 
time) necessary for the data output signals D.sub.0 to D.sub.7 from output 
buffers 34.sub.0 to 34.sub.7 to change from "1" (when the data value is 
"1" before the change) to "0" is assumed to be as follows. The delay time 
is "0" for signals D.sub.0 and D.sub.1, t.sub.o for signals D.sub.2 and 
D.sub.2, 2t.sub.o for signals D.sub.4 and D.sub.5, 3t.sub.o for signals 
D.sub.6 and D.sub.7. In this regard, the delay time t.sub.o is selected so 
that all signals D.sub.0 to D.sub.7 are altered to "0" during the data 
latch standby period Ts. 
Subsequently, operation of the embodiment will be described by referring to 
FIGS. 10, 13, and 14. Assume that the output signals TD.sub.0 to TD.sub.3 
are maintained at "1" and the signals TD.sub.4 to TD.sub.7 are varied from 
"1" to "0" ((J) and (K) of FIG. 13). In a read operation, when the signal 
TSA2 ((A) of FIG. 13) is altered from "0" to "1" in response to enable of 
the sense amplifiers 32.sub.7 to 32.sub.7, the control signals CD.sub.0 
and CD.sub.1 are changed from "1" to "0". Moreover, in relation to the 
change in the signals CD.sub.0 and CD.sub.1, the signals D.sub.0 and 
D.sub.1 are varied from "1" to "0" ((L) of FIG. 13 and (P) of FIG. 14). 
Additionally, when 5 ns lapse, the control signals CD.sub.2 and CD.sub.3 
are altered from "1" to "0". In response thereto, the output signals 
D.sub.2 and D.sub.3 are changed from "1" to "0" ((M) of FIG. 13 and (Q) of 
FIG. 14). Thereafter, when 5 ns lapse, namely, ten nanoseconds after the 
sense amplifiers are enable, the signals CD.sub.4 and CD.sub.5 are altered 
from "1" to "0" and then the signals D.sub.4 and D.sub.5 are varied from 
"1" to "0" ((N) of FIG. 13 and (R) of FIG. 14). Similarly, when 15 ns 
lapse after the initiation of sense amplifiers, the signals CD.sub.6 and 
CD.sub.7 are altered from "1" to "0" and then the signals D.sub.6 and 
D.sub.7 are varied from "1" to "0" ((O) of FIG. 13 and (N) of FIG. 14). 
Namely, all data output signals D.sub.0 to D.sub.7 are changed to be fixed 
to "0". 
When 20 ns lapse after the sense amplifier initiation, the signal TSAL is 
altered from "0" to "1" ((T) of FIG. 14) to start the data latch active 
period in which the signals TD.sub.4 to TD.sub.7 are varied from "1" to 
"0" ((J) and (K) of FIG. 13). When 5 ns lapse after the change of TSAL 
from "1" to "0", the data latch active period T.sub.DL is terminated. 
Furthermore, 5 ns thereafter, the signal TSA2 is changed from "1" to "0" to 
terminate the sense amplifier active period TE and the signals CD.sub.0 to 
CD.sub.7 are varied to data items which are in phase with the signals 
TD.sub.0 to TD.sub.7. That is, the signals CD.sub.0 to CD.sub.3 are varied 
from "0" to "1", whereas the signals CD.sub.4 to CD.sub.7 are maintained 
at "0". Therefore, the signals D.sub.0 to D.sub.3 are varied from "0" to 
"1" and the signals D.sub.4 to D.sub.7 are maintained at "0". At this 
point, the read operation is terminated. Since the signals D.sub.0 to 
D.sub.7 are fixed during the data latch active period T.sub.DL and the GND 
power source is stable, the data items can be appropriately latched. 
In the embodiment, when setting the sense amplifier active period TE, the 
delay time t.sub.o, the data latch standby time T.sub.s, and the data 
latch active period T.sub.DL, considerations have not been given to the 
delay of signals due to characteristics of transistors and signal wirings. 
However, when the signal delay is not negligible, it is desirable to set 
the values of these items above in consideration of the signal delay. 
Advantages of the embodiment will be described. Assume in the conventional 
semiconductor device that when the signals D.sub.4 to D.sub.7 are 
simultaneously varied from "1" to "0", the discharge current fed to the 
GND power source has a peak value of 30 milliampere (mA). In the 
semiconductor device of the present embodiment, since the signals D.sub.4 
to D.sub.5, and D.sub.6 to D.sub.7 are altered from "1" to "0" with a 
difference of time of 5 ns therebetween, the discharge current having a 
peak value 15 mA appears at an interval of 5 ns to enter the GND power 
source. Therefore, the fluctuation in the GND potential can be reduced to 
about one half of that of the conventional semiconductor device. 
When the signals D.sub.0 to D.sub.7 are varied from "1" to "0" at the same 
time, the peak value of discharge current is 60 mA in the prior art. In 
contrast therewith, the peak value is lowered to 15 mA, i.e., about one 
quarter of the peak value of the conventional device. Minimization of the 
discharge current reduces the deviation in the GND potential, which 
prevents operation errors in the constituent circuit components of the 
device. For example, the erroneous data read operation and the wrong data 
latch operation (FIG. 9C) due to an operation failure of the pertinent 
sense amplifier during the read operation can be prevented. Namely, the 
read operation can be conducted with high reliability. 
The present invention is however not restricted by the embodiments. Namely, 
in addition to the n-channel and p-channel MOS transistors, there may also 
be used bipolar transistors as well as various circuit blocks, logical 
circuits, and elements. 
In accordance with the present invention as described above, when a 
plurality of readout data items are simultaneously changed to a 
predetermined logical value, the discharge (or charge) current delivered 
from the final stage of the output circuit is dispersed or the discharge 
(or charge) current is slowly delivered from the output circuit to 
minimize the peak value of the discharge (or charge) current. Moreover, 
the readout data is fed to an external device after the active period of 
the read circuit is terminated and hence the readout data can be output 
with the stable GND (or V.sub.cc) power source. Therefore, it is possible 
to prevent the fluctuation occurring in the GND power source when a 
plurality of data output signals are changed from "1" ("H" level) to "0" 
("L" level) at the same time (or the deviation occurring in the V.sub.cc 
power source when the data output signals are changed from "0" to "1"). 
This prevents operation errors and hence improves reliability of the read 
operation. 
Additionally, in accordance with the present invention, the operation 
errors due to deviation in the GND (or V.sub.cc) power source can be 
avoided without decreasing the read speed of data output signals. During 
the active period of the rad circuit, i.e., before the readout data items 
are determined, all data output signals are varied to "0" or "1" such that 
the value is fixed to "0" or "1" only during the active period or the 
signals are gradually altered to "0" or "1". 
While the present invention has been described with reference to the 
particular illustrative embodiments, it is not to be restricted by those 
embodiments but only by the appended claims. It is to be appreciated that 
those skilled in the art can change or modify the embodiments without 
departing from the scope and spirit of the present invention.