Liquid crystal display device

A liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a liquid crystal layer disposed on the first subpixel electrode and the second subpixel electrode. A first insulating layer is disposed between the substrate and the first subpixel electrode. A second insulating layer is disposed between the second subpixel electrode and the liquid crystal layer. A common electrode is disposed on the liquid crystal layer. The first subpixel electrode is disposed farther from the substrate than the second subpixel electrode, and the first subpixel electrode and the second subpixel electrode have facing edges which are connected with each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2017-0098140 filed in the Korean Intellectual Property Office on Aug. 2, 2017, the entire contents of which are incorporated herein by reference.

BACKGROUND

(a) Technical Field

This disclosure relates to a liquid crystal display.

(b) Description of the Related Art

A liquid crystal display (LCD) includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed between the two display panels. The liquid crystal display displays an image by generating an electric field on a liquid crystal layer by applying a voltage to the field generating electrodes, thereby determining alignment directions of liquid crystal molecules of the liquid crystal layer using the generated field, and controlling polarization of incident light.

Among liquid crystal displays, there is a liquid crystal display of a vertically aligned mode in which long axes of liquid crystal molecules are arranged so as to be perpendicular to upper and lower plates in a state in which no electric field is applied. The liquid crystal display of the vertically aligned mode is spotlighted because of its high contrast ratio and wide reference viewing angle.

In the liquid crystal display of the vertically aligned mode, a technique by which one pixel is divided into a plurality of subpixels such that different voltages are applied to the respective subpixels is used. The application of different voltages requires formation of a plurality of switching elements and leads to a complex structure. Particularly, an aperture ratio and transmittance may be deteriorated as a resolution is higher.

SUMMARY

Exemplary embodiments provide a liquid crystal display capable of improving side visibility.

An exemplary embodiment provides a liquid crystal display including a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a liquid crystal layer disposed on the first subpixel electrode and the second subpixel electrode. A first insulating layer is disposed between the substrate and the first subpixel electrode. A second insulating layer is disposed between the second subpixel electrode and the liquid crystal layer. A common electrode is disposed on the liquid crystal layer, wherein a distance between the first subpixel electrode and the common electrode is smaller than a distance between the second subpixel electrode and the common electrode.

The first subpixel electrode and the second subpixel electrode are integral, and may be disposed at a same layer.

The first subpixel electrode and the second subpixel electrode may not overlap each other.

The first subpixel electrode and the second subpixel electrode may have facing end portions which are connected with each other.

The first subpixel electrode and the second subpixel electrode may be connected with a connector integral therewith.

The connector may extend along a side surface of the first insulating layer.

The first insulating layer and the second insulating layer may be different materials.

The liquid crystal display may further include a column spacer disposed on the first insulating layer, and the second insulating layer may be a same material as that of the column spacer.

A cell gap of a liquid crystal layer overlapping the second subpixel electrode may be 0.85 to 1.15 times a cell gap of a liquid crystal layer overlapping the first subpixel electrode.

A thickness of the second insulating layer may be about 0.5 μm or more.

The second insulating layer may include a protrusion that overlap the first insulating layer and protrudes toward the liquid crystal layer.

An exemplary embodiment provides a liquid crystal display including a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a liquid crystal layer disposed on the first subpixel electrode and the second subpixel electrode. A first insulating layer is disposed between the substrate and the first subpixel electrode. A second insulating layer is disposed between the second subpixel electrode and the liquid crystal layer. A common electrode is disposed on the liquid crystal layer, wherein the first subpixel electrode is disposed farther from the substrate than the second subpixel electrode, and the first subpixel electrode and the second subpixel electrode have facing edges which are connected with each other.

The first subpixel electrode and the second subpixel electrode may be connected with a connector integral therewith.

The connector may extend along a side surface of the first insulating layer.

Each of the first subpixel electrode and the second subpixel electrode may include a horizontal stem, a vertical stem that crosses the horizontal stem, and branches that extend from the horizontal stem and vertical stem in a diagonal direction, and the connector may be connected with the vertical stem of the first subpixel electrode and the vertical stem of the second subpixel electrode.

Each of the first subpixel electrode and the second subpixel electrode may include an outer stem disposed in at least one edge thereof.

The outer stem may not be disposed in at least one of facing edges of the first subpixel electrode and the second subpixel electrode.

The second insulating layer may include an overlapping portion that overlaps the first insulating layer and a non-overlapping portion that does not overlap the first insulating layer, and the overlapping portion of the second insulating layer may protrude more toward the liquid crystal layer than the non-overlapping portion.

The protrusion may overlap the connector.

The liquid crystal display may further include a transistor disposed between the substrate and the pixel electrode, the first subpixel electrode may be directly connected with the transistor by an extension, and the second subpixel electrode may be electrically connected to the transistor through the first subpixel electrode.

The first insulating layer may be continuously positioned over a plurality of first subpixel electrodes in a first direction, and the second insulating layer may be continuously positioned over a plurality of second subpixel electrodes in the first direction.

The first insulating layer and the second insulating layer may be alternately disposed in a second direction that crosses the first direction.

An edge of the first insulating layer may overlap an edge of the second insulating layer.

According to the exemplary embodiments, it is possible to provide a liquid crystal display with improved side visibility without deteriorating an aperture ratio and transmittance.

DETAILED DESCRIPTION OF THE EMBODIMENTS

To clearly describe the embodiments, parts that are irrelevant to the description are omitted, and like numerals refer to like or similar constituent elements throughout the specification.

Since sizes and thicknesses of constituent members shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the embodiments are not limited to the illustrated sizes and thicknesses. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas are exaggerated.

Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-section” means when a cross-section taken by vertically cutting an object portion is viewed from the side.

First, a liquid crystal display according to an exemplary embodiment will be described with reference toFIG. 1andFIG. 2.

FIG. 1is a layout view illustrating a liquid crystal display, sometimes called a display device, according to an exemplary embodiment, andFIG. 2is an equivalent circuit diagram illustrating one pixel of a liquid crystal display according to an exemplary embodiment.

Referring toFIG. 1, the display device according to the present exemplary embodiment includes a display panel10, a gate driver20, a data driver30, and a signal controller40.

The display panel10includes gate lines G1-Gn and data lines D1-Dm, and the gate lines G1-Gn and data lines D1-Dm are connected to pixels PX that are arranged in a substantially matrix form. The gate lines G1-Gn may extend in a first direction (e.g., a row direction), and the data lines D1-Dm may extend in a second direction (e.g., a column direction) that crosses the first direction. Each pixel PX may receive gate signals including a gate-on voltage for turning on a transistor as a switching element and a gate-off voltage for turning off the transistor as the switching element through the gate lines G1-Gn, and a data voltage corresponding to an image signal may be applied through the data lines D1-Dm when the transistor is turned on. One pixel PX, which is a unit for displaying an image, may uniquely display one of primary colors, or a plurality of pixels may alternately display the primary colors according to time, to display desired colors by a spatial or temporal sum of the primary colors.

The signal controller40controls the gate driver20and the data driver30. The signal controller40receives an image signal and control signals thereof from an external graphics processor (not illustrated). For example, the control signals include a horizontal synchronizing signal, a vertical synchronization signal, a clock signal, a data enable signal, and the like. The signal controller40processes the image signal based on the control signals to be appropriate for an operating condition of the display panel10, and then generates and outputs image data, a gate control signal, a data control signal, and clock signals.

The gate driver20receives a gate control signal from the signal controller40to generate a gate signal including a gate-on voltage and a gate-off voltage and applies it to the gate lines G1-Gn.

The data driver30receives a data control signal and image data from the signal controller40, converts the image data to a data signal (data voltage) by using a gray voltage generated in a gray voltage generator (not illustrated), and applies the data signal to the data lines D1-Dm.

Referring toFIG. 2, the display panel10includes a first display panel100and a second display panel200which face each other, and a liquid crystal layer3disposed therebetween.

Each pixel PX, e.g., a pixel PX connected with an ithgate line Gi and a jthdata line Dj, includes a transistor Q connected with the gate line Gi and the data line Dj, first and second liquid crystal capacitors Clc1and Clc2connected with the transistor Q, and first and second storage capacitors Cst1and Cst2. The first and second storage capacitors Cst1and Cst2may be omitted. Each pixel PX includes a pixel electrode191including a first subpixel electrode191aand a second subpixel electrode191bconnected with each other. Unlike in the illustrated exemplary embodiment, one pixel PX may include 3 or more subpixel electrodes and 3 or more liquid crystal capacitors.

The transistor Q positioned in the first display panel100includes a control terminal connected with the gate line Gi, an input terminal connected with the data line Dj, and an output terminal connected with the first liquid crystal capacitor Clc1and the first storage capacitor Cst1.

The first liquid crystal capacitor Clc1uses the first subpixel electrode191aof the first display panel100and a common electrode270of the second display panel200as two terminals, and the liquid crystal layer3disposed between the first subpixel electrode191aand the common electrode270serves as a dielectric material. The first subpixel electrode191ais connected with the transistor Q and the common electrode270is formed on an entire surface of the second display panel200to receive the common voltage.

The second liquid crystal capacitor Clc2uses the second subpixel electrode191bof the first display panel100and the common electrode270of the second display panel200as two terminals, and the liquid crystal layer3disposed between the second subpixel electrode191band the common electrode270serves as a dielectric material. The second subpixel electrode191bis connected with the first subpixel electrode191a. Accordingly, the second subpixel electrode191bmay receive a data voltage through the first subpixel electrode191aconnected with the transistor Q, and the data voltage applied to the second subpixel electrode191bmay be the same as the data voltage applied to the first subpixel electrode191a.

However, an intensity of an electric field generated in the liquid crystal layer3of the first liquid crystal capacitor Clc1may be different from an intensity of an electric field generated in the liquid crystal layer3of the second liquid crystal capacitor Clc2by structural features related to the first subpixel electrode191aand the second subpixel electrode191b. In other words, although the first subpixel electrode191aand the second subpixel electrode191breceive a same voltage, a charging voltage of the first liquid crystal capacitor Clc1may be different from that of the second liquid crystal capacitor Clc2. As a result, one pixel PX may include a first subpixel formed by the first liquid crystal capacitor Clc1and a second subpixel formed by the second liquid crystal capacitor Clc2, in which the arrangement of the liquid crystal molecules in the liquid crystal layer3are differently controlled, to improve the side visibility of the liquid crystal display. This will be described in detail later.

The first storage capacitor Cst1which performs an auxiliary function of the first liquid crystal capacitor Clc1is formed by using a storage electrode line (not illustrated) positioned in the first display panel100and the first subpixel electrode191awhich overlap each other with an insulator therebetween. The second storage capacitor Cst2which performs an auxiliary function of the second liquid crystal capacitor Clc2is formed by using the storage electrode line and the second subpixel electrode191bwhich overlap each other with an insulator therebetween. A predetermined voltage such as a common voltage may be applied to the storage electrode line.

An overall configuration of the liquid crystal display according to the exemplary embodiment has been described so far. Hereinafter, the liquid crystal display according to an exemplary embodiment will be described in detail based on one pixel.

FIG. 3is a top plan view illustrating one pixel PX of a liquid crystal display according to an exemplary embodiment,FIG. 4is a cross-sectional view taken along a line IV-IV′ ofFIG. 3, andFIG. 5is a cross-sectional view taken along a line V-V′ ofFIG. 3.

The top plan view ofFIG. 3illustrates one pixel PX of the liquid crystal display according to the exemplary embodiment and portions of the gate lines and gate lines connected with pixels adjacent thereto. Although one pixel PX is described as an example, such pixels PX may be arranged in a matrix form, i.e., in the first direction and in the second direction in the liquid crystal display.

Referring toFIG. 3,FIG. 4, andFIG. 5, the liquid crystal display according to the present exemplary embodiment includes the first display panel100and the second display panel200which face each other, and the liquid crystal layer3disposed therebetween.

The first display panel100will be described. A gate conductor including a gate line121, a gate electrode124, and a storage electrode line125is disposed on a first substrate110formed of a transparent insulating material such as glass.

The gate line121extends mainly in a horizontal direction to transfer a gate signal (scan signal). Unlike in the illustrated exemplary embodiment, the gate line121may extend mainly in a vertical direction. The gate electrode124is formed integrally with the gate line121and protrudes from the gate line121. In the present specification, when a first element is integrally formed or integral with a second element, this indicates that the first element and the second element are formed by using a same material and a same process, and are connected with each other, i.e., are a single piece and not a plurality of separate pieces connected together. The storage electrode line125extends mainly in the horizontal direction to transfer a predetermined voltage such as a common voltage. For example, the storage electrode line125may extend to pass between the first subpixel electrode191aand the second subpixel electrode191b. Although not illustrated, the storage electrode line125may include a portion that extends substantially in parallel with a data line171, and a shape and a disposal of the storage electrode line125may be variously modified. The gate conductor may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti), or a metal alloy thereof, and may be formed as a single layer or multiple layers.

A gate insulating layer140may be disposed on the gate conductor. The gate insulating layer140may include an inorganic insulating material such as a silicon oxide and a silicon nitride.

A semiconductor layer154is disposed on the gate insulating layer140. The semiconductor layer154may include a semiconductor material such as an oxide semiconductor, amorphous silicon, and polycrystalline silicon.

A data conductor including the data line171, a source electrode173, and a drain electrode175is disposed on the semiconductor layer154. The data line171may extend mainly in the vertical direction, but may extend mainly in the horizontal direction. The source electrode173is integrally formed with the data line171, and protrudes from the data line171. Further, a portion of the data line171may serve as the source electrode173, unlike the illustrated exemplary embodiment. The drain electrode175may be separated from the source electrode173at a predetermined interval, and may include an extension177. The data conductor may include a metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta), or a metal alloy thereof, and may be formed as a single layer or multiple layers. Although not illustrated, an ohmic contact layer may be disposed between the semiconductor layer154and the data conductor.

The gate electrode124, the source electrode173, and the drain electrode175constitute the transistor Q together with the semiconductor layer154. A channel of the transistor Q may be formed at a portion of the semiconductor layer154between the source electrode173and the drain electrode175.

A first passivation layer160a, a second passivation layer160b, and a third passivation layer160cmay be disposed on the data conductor. One or two of the first passivation layer160a, the second passivation layer160b, and the third passivation layer160cmay be omitted.

The first passivation layer160amay include an inorganic insulating material, and the second passivation layer160bmay include an organic insulating material, but the present specification is not limited thereto. The second passivation layer160bmay be a color filter. When being the color filter, the second passivation layer160bmay uniquely display one of primary colors. For example, the primary colors may include red, green, and blue, or yellow, cyan, magenta. The color filter may also display mixed colors of white or primary colors. The color filter may be disposed in the second display panel200. The third passivation layer160cmay include an inorganic insulating material or an organic insulating material. The third passivation layer160cmay prevent the color filter from being lifted and suppress contamination of the liquid crystal layer3due to an organic material such as a solvent having flowed from the color filter.

A first insulating layer180ais disposed on the third passivation layer160c. The first insulating layer180amay include an organic insulating material, and may include a photosensitive material such as a photoresist. The first insulating layer180amay be disposed in a region where the first subpixel electrode191ais formed, but may not be disposed in a region where the second subpixel electrode191bis formed. The first insulating layer180amay be continuously positioned over the adjacent pixels PX in the first direction D1. The first insulating layer180amay be formed by, e.g., forming an insulating layer on the third passivation layer160cand patterning it through a photolithography process. At this time, an insulating layer that overlaps the second subpixel electrode191bis removed. When a halftone mask is used in the photolithography process, a contact hole61that overlaps the extension177of the drain electrode175may be formed together in the first insulating layer180aand the first to third passivation layers160a,160b, and160cwhile the first insulating layer180ais formed.

The pixel electrode191including the first subpixel electrode191aand the second subpixel electrode191bis disposed on the first insulating layer180a. One pixel PX includes a first subpixel sPXa corresponding to the first subpixel electrode191aand a second subpixel sPXb corresponding to the second subpixel electrode191b. The first subpixel electrode191ais disposed to overlap the first insulating layer180a, but the second subpixel electrode191bis disposed to not overlap the first insulating layer180a. Accordingly, the first subpixel electrode191ais substantially positioned farther away from the second subpixel electrode191bby a thickness Ta of the first insulating layer180abased on the first substrate110and in a direction D3. The first subpixel electrode191aand the second subpixel electrode191bmay have a substantially rectangular shape, may be separated from each other at a predetermined interval, and may have facing edges191aeand191bewhich are connected with each other by a connector199. A distance d between the first subpixel electrode191aand the second subpixel electrode191b, which corresponds to a boundary B therebetween, may be designed in consideration of controllability of an alignment direction of liquid crystal (hereinafter simply referred to as liquid crystal controllability) and transmittance. As the distance d is narrower, the transmittance may be increased. However, as the distance d is wider, the liquid crystal controllability may be more appropriate at the boundary B between the first subpixel electrode191aand the second subpixel electrode191b. For example, the distance d may be range of about 3 to 11 μm, or 5 to 9 μm, but it is not limited thereto. The distance d may be less than about 3 μm or more than about 11 μm.

The connector199may connect the first subpixel electrode191awith the second subpixel electrode191bin a region that overlaps a substantially vertically central line of the first subpixel electrode191aand the second subpixel electrode191b. In the illustrated exemplary embodiment, the connector199is connected with the vertical stem193aof the first subpixel electrode191aand the vertical stem193bof the second subpixel electrode191b. However, the connector199may connect the first subpixel electrode191aand the second subpixel electrode191bin a different region from that of the illustrated exemplary embodiment. For example, the connector199may be formed to connect a left edge and/or a right edge of the first subpixel electrode191aand the second subpixel electrode191b, and may be formed to entirely connect facing edges191aeand191beof the first subpixel electrode191aand the second subpixel electrode191b.

Referring toFIG. 5, the connector199is formed to be inclined along a side surface180asof the first insulating layer180afacing the second subpixel electrode191b. The second subpixel electrode191band the first subpixel electrode191awhich are disposed at different heights are electrically connected to each other.

The first subpixel electrode191aincludes an extension197athat extends from an edge opposite to an edge connected with the connector199. The extension197aof the first subpixel electrode191ais connected with the extension177of the drain electrode175through the contact hole61formed the first insulating layer180aand the first to third passivation layers160a,160b, and160c. A lower surface of the extension197aof the first subpixel electrode191acontacts an upper surface of the extension177of the drain electrode175, and thus the first subpixel electrode191ais directly connected with the transistor Q.

Unlike the first subpixel electrode191a, the second subpixel electrode191bis not directly connected with the transistor Q. However, since the second subpixel electrode191bis connected with to the first subpixel electrode191aby the connector199, the connector199is electrically connected to the transistor Q through the first subpixel electrode191a. Accordingly, a data voltage applied to the first subpixel electrode191athrough the transistor Q may also be identically applied to the second subpixel electrode191b.

The first subpixel electrode191a, the second subpixel electrode191b, the extension197a, and the connector199may be formed by forming a conductive layer on the third passivation layer160cand the first insulating layer180awith a transparent conductive material such as an indium tin oxide (ITO) and an indium zinc oxide (IZO), and then patterning it through a photolithography process. Accordingly, the first subpixel electrode191a, the second subpixel electrode191b, the extension197a, and the connector199are integrally formed, and are disposed as a same layer

In addition, the first subpixel electrode191a, the second subpixel electrode191b, the extension197a, and the connector199do not overlap each other.

In the illustrated exemplary embodiment, the pixel electrode191is connected with the transistor Q positioned therebelow in the top plan view. Particularly, the first subpixel electrode191ais directly connected with the transistor Q. However, the connection between the pixel electrode191and the transistor Q may be variously modified without being limited thereto. For example, the pixel electrode191may be connected with the transistor Q positioned thereabove in the top plan view, and the second subpixel electrode191bmay be directly connected with the transistor Q.

An exemplary structure of the first subpixel electrode191aand the second subpixel electrode191b, particularly a planar structure illustrated inFIG. 3, will be described in detail. The first subpixel electrode191amay include a cross-shaped stem including a horizontal stem192aand the vertical stem193athat crosses the horizontal stem192a. In addition, the first subpixel electrode191amay include branches194athat extend in a diagonal direction from the horizontal stem192aor the vertical stem193a. The first subpixel electrode191amay be divided into four subregions by the cross-shaped stem, and the branches194amay be positioned in each of the subregions. When an electric field is generated, directions in which liquid crystal molecules310of the liquid crystal layer3are inclined in the four subregions may be differently controlled, thereby realizing a wide viewing angle.

The first subpixel electrode191amay further include an outer stem195athat surrounds at least one edge thereof. The first subpixel electrode191amay have such a shape that end portions of the branches194aare connected with each other by the outer stem195a. An effective area of the first subpixel electrode191a(an area in which the first subpixel electrode191ais actually formed) may increase by the outer stem195a, thereby increasing the transmittance of the liquid crystal display. The outer stem195amay serve to prevent liquid crystal control from being stably performed at end portions of the branches194aby a field generated in the data line171adjacent to the end portions of the branches194a. In the illustrated exemplary embodiment, the outer stem195aof the first subpixel electrode191ais formed by the left, right, and lower edges, but is not formed at an upper edge that faces the second subpixel electrode191b.

The second subpixel electrode191bmay include a horizontal stem192b, the vertical stem193b, and branches194bwhich respectively correspond to the horizontal stem192a, the vertical stem193a, and the branches194aof the first subpixel electrode191a. The second subpixel electrode191bmay further include an outer stem195bthat surrounds at least one edge thereof. Functions of the horizontal stem192b, the vertical stem193b, the branches194b, and the outer stem195bof the first subpixel electrode191bare as described above in relation to the first subpixel electrode191a. In the illustrated exemplary embodiment, the outer stem195bof the second subpixel electrode191bis formed by the left, right, and upper edges, but is not formed at a lower edge that faces the first subpixel electrode191a.

In the illustrated exemplary embodiment, at least one of the first subpixel electrode191aand the second subpixel electrode191bmay not include the outer stem195aor195b. In addition, the detailed structures of the first subpixel electrode191aand the second subpixel electrode191bare merely an example, and may be variously modified.

A second insulating layer180bis disposed on the second subpixel electrode191b. The second insulating layer180bis a layer formed on the pixel electrode191, but may be disposed only on the second subpixel electrode191b. The second insulating layer180bmay not overlap most of the first subpixel electrode191a, but a portion of the first subpixel electrode191aadjacent to the boundary B (e.g., a portion thereof that overlaps a protrusion181b) may overlap the second insulating layer180b. The second insulating layer180bmay be continuously positioned over the adjacent pixels PX in the first direction D1. The second insulating layer180bmay include an organic insulating material. The second insulating layer180bmay be formed of a material that is different from that of the first insulating layer180a, e.g., a material having a good compressive restoring force and elasticity, that is, a same material as a column spacer85. In this case, the second insulating layer180band the column spacer85may be formed together by forming a transparent insulating layer on the first and second subpixel electrodes191aand191band patterning it through a photolithography process. Time and cost can be saved since no additional process or additional mask for forming the second insulating layer180bis required. However, the second insulating layer180bmay be formed by using a process that is different from that of the column spacer85, and may be formed of a same material as that of the first insulating layer180a. The second insulating layer180bmay include an inorganic insulating material.

A thickness Tb of the second insulating layer180bmay be similar or substantially identical to the thickness Ta of the first insulating layer180a. Accordingly, a first cell gap CGa corresponding to a thickness of the liquid crystal layer3in the first subpixel sPXa may be similar or substantially identical to a second cell gap CGb corresponding to a thickness of the liquid crystal layer3in the second subpixel sPXb. For example, the second cell gap CGb may be about 0.7 to 1.4 times or 0.85 to 1.15 times the first cell gap CGa. The thickness of the second insulating layer180bmay be 0.5 μm or more, and when it is smaller, the side viewability may not be improved.

The first insulating layer180ais positioned below the first subpixel electrode191a, the second insulating layer180bis positioned on the second subpixel electrode191b, and the first subpixel electrode191aand the second subpixel electrode191bare formed as a same layer. Accordingly, the second insulating layer180bmay be considered to be positioned on the first insulating layer180a.

In the boundary B, the second insulating layer180bmay be disposed to overlap the first insulating layer180a. In this case, the protrusion181bwhich is a portion of the second insulating layer180bwhich overlaps the first insulating layer180amay convexly protrude more toward the liquid crystal layer3than a portion of the second insulating layer180bwhich overlaps the second subpixel electrode191b. The protrusion181bof the second insulating layer180bmay induce the liquid crystal molecules to tilt toward the first subpixel electrode191aor the second subpixel electrode191bin the boundary B, thereby improving liquid crystal controllability in the boundary B and suppressing texture generation. The protrusion181bmay also overlap the connector199. Unlike the illustrated exemplary embodiment, the second insulating layer180bmay not include the protrusion181b.

Next, the second display panel200will be described. A light blocking member220called a black matrix is disposed on a second substrate210that may be formed of a transparent insulating material such as glass. The light blocking member220may serve to prevent light leakage, and may be disposed in the first display panel100in another embodiment.

The common electrode270is disposed on the light blocking member220. The common electrode270may be formed of a transparent conductive material such as ITO and IZO. The common electrode270may be formed as a single plate across the pixels PX or substantially throughout the entire second display panel200. However, a slit or an opening may be formed in the common electrode270.

The liquid crystal layer3including the liquid crystal molecules310is disposed between the first display panel100and the second display panel200. The liquid crystal molecules310may have negative dielectric anisotropy, and may be arranged in a direction in which a long axis of the liquid crystal molecules310are perpendicular to the electric field. However, the liquid crystal molecules310may have positive dielectric anisotropy, and may be arranged in a direction in which the electric field and a long axis of the liquid crystal molecules310are parallel. An alignment layer (not illustrated) may be disposed between the first display panel100and the liquid crystal layer3, and between the second display panel200and the liquid crystal layer3. The alignment layer may be a vertical alignment layer.

FIG. 6is a top plan view illustrating six pixels of a liquid crystal display according to an exemplary embodiment.

InFIG. 6, e.g., six adjacent pixels PX are illustrated among pixels arranged in a matrix. In this region, the first insulating layer180aand the second insulating layer180bare indicated by diagonal lines having different directions from each other. A slit or an opening may be formed in the pixel electrode191, for example, as shown inFIG. 3, but is briefly shown in a substantially rectangular shape.

Referring toFIG. 6, in a planar disposal of the first insulating layer180aand the second insulating layer180b, the first insulating layer180amay be continuously positioned over the adjacent pixels PX, particularly the adjacent first subpixel electrodes191ain the first direction D1, and the second insulating layer180bmay also be continuously positioned over the adjacent pixels PX, particularly the adjacent second subpixel electrodes191b. The first insulating layer180aoverlaps the first subpixel electrode191a, and the second insulating layer180boverlaps the second subpixel electrode191b. Accordingly, the first insulating layer180aand the second insulating layer180bmay discontinuously alternately positioned over the adjacent pixels PX in the second direction D2. Edges of the first insulating layer180aand the second insulating layer180bmay overlap each other as illustrated therein, but may not overlap each other.

As described above, the first subpixel electrode191aand the second subpixel electrode191bare connected with the connector199to receive a same voltage. However, a voltage (effective voltage) acting to form an electric field in the liquid crystal layer is reduced by a voltage drop by the second insulating layer180bdisposed on the second subpixel electrode191b. As a result, an intensity of an electric field formed in the liquid crystal layer3of the first subpixel sPXa becomes smaller than an intensity of an electric field formed in the liquid crystal layer3of the second subpixel sPXb. In contrast, since there is no insulating layer on the first subpixel electrode191a, an effective voltage of the first subpixel sPXa may be the same as an applied voltage (data voltage). This voltage drop effect may depend on a dielectric constant and thickness of the second insulating layer180b. It is seen through a following equation that the voltage drop effect increases as the thickness is thicker and the dielectric constant is smaller.

Herein, Veffindicates effective voltage, V0indicates an applied voltage, dpindicates a thickness of the insulating layer, dlcindicates a cell gap, εpindicates a dielectric constant of the insulating layer, and εlcindicates a dielectric constant of the liquid crystal layer.

The reason why the intensity of the electric field formed in the liquid crystal layer3of the first subpixel sPXa will be described in another way. The intensity of the electric field is proportional to the voltage, and is inversely proportional to a distance between the two electrodes. A same voltage is applied to the first subpixel electrode191aand the second subpixel electrode191b. However, a distance between the first subpixel electrode191aand the common electrode270substantially corresponds to the first cell gap CGa, and a distance between the second subpixel electrode191band the common electrode270substantially corresponds to a sum of the second cell gap CGb and the thickness Tb of the second insulating layer180b. Accordingly, since the distance between the second subpixel electrode191band the common electrode270is relatively large, an intensity of an electric field generated in the liquid crystal layer3of the first subpixel sPXa may be small.

As the intensity of the electric field is larger, the liquid crystal molecules310of the liquid crystal layer3are more inclined to transmit a larger amount of light. As a result, a transmittance of the first subpixel sPXa is different from that of the of the second subpixel sPXb. When a difference in the transmittances between the first and second subpixels sPXa and sPXb is appropriately adjusted, an image viewed from the side can be controlled to approach an image viewed from the front as closely as possible, thereby improving side visibility.

Only one transistor may be disposed to apply only one data voltage in order to form the first and second subpixels sPXa and sPXb capable of improving the side visibility. Therefore, it is possible to increase an aperture ratio of the liquid crystal display and simplify a driving circuit as compared with a structure for improving the side visibility by disposing a plurality of transistors and applying a plurality of data voltages. In addition, although the intensity of the electric field is differently adjusted by using a voltage drop effect caused by the second insulating layer180bformed on the second subpixel electrode191b, a height difference between the second subpixel electrode191band the first subpixel electrode191amay be made to allow the second cell gap CGb to be equal to or more than the first cell gap CGa. Accordingly, it is possible to reduce the transmittance in the second subpixel sPXb.

By cross-referring toFIG. 2, the first subpixel electrode191aand the common electrode270constitute a first liquid crystal capacitor Clc1together with the liquid crystal layer3therebetween, and the second subpixel electrode191band the common electrode270constitute the second liquid crystal capacitor Clc2together with the liquid crystal layer3therebetween. The first and second liquid crystal capacitors Clc1and Clc2maintain the applied voltage even after the transistor Q is turned off. In addition, the first and second subpixel electrodes191aand191boverlap the storage electrode line125to constitute the first and second storage capacitors Cst1and Cst2. According to the present exemplary embodiment, a charging voltage of the second liquid crystal capacitor Clc2may be lower than that of the first liquid crystal capacitor Clc1, and thus it is possible to improve the side visibility of the liquid crystal display by differently adjusting the charging voltages of the first and second liquid crystal capacitors Clc1and Clc2.

The liquid crystal display according to the exemplary embodiment has been described in detail. Hereinafter, differences in a form of the pixel electrode between the aforementioned exemplary embodiment and some other exemplary embodiments will be mainly described. The same reference numerals are given to the same or similar constituent elements.

FIG. 7andFIG. 8are top plan views illustrating one pixel of a liquid crystal display according to an exemplary embodiment.

Referring toFIG. 7, the pixel electrode191includes a first subpixel electrode191aand a second subpixel electrode191b. The first subpixel electrode191aincludes a horizontal stem192a, a vertical stem193a, branches194a, and an outer stem195a, and the second subpixel electrode191bincludes a horizontal stem192b, a vertical stem193b, branches194b, and an outer stem195b. Similar to the exemplary embodiment ofFIG. 3, the outer stem195bof the second subpixel electrode191bis formed at left, right, and upper edges, but is not formed at a lower edge that faces the first subpixel electrode191a.

Unlike the exemplary embodiment ofFIG. 3, the outer stem195aof the first subpixel electrode191ais formed at all edges including an upper edge as well as the left, right, and lower edges. As a formation region of the outer stem195aincreases, an effective area of the first subpixel electrode191amay increase, thereby increasing the transmittance. In contrast, it may be disadvantageous in terms of liquid crystal controllability. For example, this is because a direction of a fringe field formed by the branches194ais different from that of a fringe field formed by the outer stem195a, and thus a direction in which the liquid crystal molecules are inclined may not be constant. This may cause textures or slow response times.

Therefore, formation of the outer stems195aand195bmay be designed in consideration of transmittance, liquid crystal controllability, and a distance between the first subpixel electrode191aand the second subpixel electrode191b. As described above, the transmittance and the liquid crystal controllability also depend on the distance d between the first subpixel electrode191aand the second subpixel electrode191b. The electric field generated in the first subpixel sPXa is larger than that generated in the second subpixel sPXb and the liquid crystal controllability increases as the electric field is larger. Accordingly, it may be advantageous to form the outer stem195ain the upper edge of the first subpixel electrode191aas compared with the lower edge of the second subpixel electrode191b. According to the exemplary embodiment ofFIG. 7, the transmittance may be improved by forming the outer stem195ain the upper edge of the first subpixel electrode191a, and the liquid crystal controllability may be improved by not forming the outer stem195bin the lower edge of the second subpixel electrode191b.

Referring toFIG. 8, although similar to the exemplary embodiment ofFIG. 7, the outer stem195bof the second subpixel electrode191bis formed in all edges including the lower edge as well as the left, right, and upper edges. As the formation of the outer stem195bincreases, the effective area of the second subpixel electrode191bmay increase, thereby increasing the transmittance. In contrast, it may be advantageous in terms of the liquid crystal controllability as compared with the exemplary embodiment ofFIG. 7.

Hereinafter, characteristics of the liquid crystal display according to some exemplary embodiments will be described based on simulation results with reference toFIG. 9toFIG. 15. Reference numerals for the respective constituent elements refer to the reference numerals illustrated inFIG. 1toFIG. 7. All simulations were performed while setting the first cell gap CGa of the first subpixel sPXa as 3.2 μm and varying the thickness Tb of the second insulating layer180bin the second subpixel sPXb.

FIG. 9toFIG. 15are graphs illustrating characteristics of liquid crystal displays according to some exemplary embodiments.

First,FIG. 9andFIG. 10illustrate a ratio (hereinafter referred to as a voltage ratio) of an effective voltage of the second subpixel sPXb to an effective voltage of the first subpixel sPXa. Specifically,FIG. 9illustrates a voltage ratio depending on a driving voltage (data voltage) when the second cell gap CGb is about 3.2 μm, andFIG. 10illustrates a voltage ratio depending on the second cell gap CGb and the thickness Tb of the second insulating layer180b.

Referring toFIG. 9, when the thickness Tb of the second insulating layer180bis about 1.0 μm, a voltage ratio that approaches a reference voltage ratio Ref is obtained. When the thickness Tb of the second insulating layer180bis 1.3 μm at a lower voltage and is 0.7 μm at a higher voltage, a voltage ratio closer to the reference voltage ratio Ref is obtained. Accordingly, the thickness Tb of the second insulating layer180bmay be advantageously about 0.7 to 1.3 μm or about 1.0 to 1.3 μm. However, since the reference voltage ratio Ref is not absolute, the thickness of the second insulating layer180bmay vary depending on the design. Nevertheless, when the thickness Tb of the second insulating layer180bis smaller than about 0.5 μm, the voltage ratio may approach 1, and thus it may be difficult to expect side visibility improvement. Referring toFIG. 10, it is seen that as the second cell gap CGb is reduced, the voltage ratio is reduced. Accordingly, it is required to consider both the second cell gap CGb and the thickness Tb of the second insulating layer180bin order to obtain a predetermined voltage ratio.

FIG. 11andFIG. 12illustrate a transmittance (relative transmittance) of the second subpixel sPXb with respect to the first subpixel sPXa depending on the thickness Tb of the second insulating layer180band the second cell gap CGb. An area ratio of the first subpixel sPXa and the second subpixel sPXb was set as 1:1.5. Referring toFIG. 11, when the thickness Tb of the second insulating layer180bincreases, the transmittance is reduced by the voltage drop effect. The reduction of the transmittance more significantly occurs as the second cell gap CGb is smaller. Referring toFIG. 12, as the second cell gap CGb increases, the transmittance increases. Accordingly, it may be advantageous to set the second cell gap CGb to be similar to or greater than the first cell gap CGa in order to obtain predetermined transmittance.

FIG. 13illustrates a V-T characteristic depending on the thickness Tb of the second insulating layer180bwhen the second cell gap CGb 3.2 μm. Referring toFIG. 13, the transmittance is reduced by the voltage drop effect when the thickness Tb of the second insulating layer180bincreases, and thus a V-T curve shifts right. In addition, as a slope of the V-T curve is reduced with the shift of the V-T curve, the V-T curve is formed in a direction favorable for side visibility. This is due to an effect that the voltage ratio decreases as a gray level increases.

FIG. 14andFIG. 15illustrate the side visibility characteristic depending on the thickness Tb of the second insulating layer180b. The side visibility may be evaluated by a gamma distortion index (GDI) based on a gamma curve when the pixels PX is viewed from a side at 60°. A curve ofFIG. 14shows the side visibility is improved when the thickness Tb of the second insulating layer180bis 0.5 μm or more. In addition, when the thickness Tb of the second insulating layer180bis 1 μm or more, it is possible to obtain side visibility equivalent to that of a structure that improves the side visibility by a voltage dividing effect by using two additional transistors and the reference voltage. However, the GDI increases again when the thickness (Tb) increases to some extent.

InFIG. 15illustrating six curves, a horizontal axis indicates gray, and a vertical axis is a gamma curve showing luminance (%). In a first curve ofFIG. 15, Ref indicates a gamma curve when the thickness Tb of the second insulating layer180bis 0. It is seen through the other curves ofFIG. 15that the side visibility is improved (approaching a front gamma curve) as the thickness Tb of the second insulating layer180bincreases. The side visibility may be further improved when the second cell gap CGb is 3.3 μm as compared with 2.8 μm or less. However, the loss of the transmittance may increase instead.