Defect detection and handling for memory based on pilot cells

A memory system includes a first parameter estimation module that receives pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate module generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. A second parameter estimation module generates a second estimate of the signal quality value based on the first estimate and user data signals that are generated based on user data stored in the memory. A processing module generates recovered user data based on the second estimate.

FIELD

The present disclosure relates to memory and, more particularly, to defect handling of non-volatile and volatile memory.

BACKGROUND

Non-volatile semiconductor memory may include flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM, multi-state memory, etc. Non-volatile semiconductor memory may include hard defects or soft defects. Hard defects refer to defects that occur during manufacturing of a memory device and can be detected during an inspection process. Soft defects are defects that occur due to aging and use of a memory device (“wear and tear”).

Memory may be arranged in a hierarchy having levels. Memory defects may be associated with one or more levels of the hierarchy. A memory device may be divided into the levels of the hierarchy based on memory block size. Example levels in order of decreasing size include zones, sectors, pages, and/or arrays.

The hard defects may be detected and identified via scanning. The identification may include the location, type, and size of the portion of memory associated with the defect. In contrast, the soft defects are more difficult to detect since they occur over time during use.

SUMMARY

In one embodiment, a memory system is provided that includes a first parameter estimation module that receives pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate module generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. A second parameter estimation module generates a second estimate of the signal quality value based on the first estimate and user data signals that are generated based on user data stored in the memory. A processing module generates recovered user data based on the second estimate.

In other features, the memory system includes a first storage device that stores the pilot signals based on a read signal from the memory. A second storage device that stores the user data signals based on a read signal from the memory.

In other features, the first parameter estimation module provides a coarse estimate of the signal quality value and the second parameter estimation module provides a fine estimate of the signal quality value. In other features, the pilot data and the user data are stored in the block.

In other features, the memory system includes a demultiplexer that generates the pilot signals and user data signals based on the read signal from the memory. In other features, the memory system includes the memory. In other features, the memory includes non-volatile memory.

In other features, the processing module stores the pilot data in the memory when the user data is stored in the memory. In other features, the processing module reads the pilot data from the memory when the user data is read from the memory. In other features, the processing module removes the pilot data from the memory when the user data is removed from the memory. In other features, the processing module alters the pilot data between access events to pilot cells of the memory.

In other features, the reference pilot information is hard-coded into firmware of the memory system. In other features, the reference pilot information is generated based on an algorithm run by the memory system. In other features, the reference pilot information is stored in the memory as the pilot data during an initial access to the memory.

In other features, the memory system includes another memory that stores the reference pilot information. In other features, the memory system includes a defect detection module that detects a defect of the memory based on at least one of the first estimate and the second estimate. A control module that adjusts access to the memory based on the defect.

In other features, the control module adjusts access to the memory when at least one of the first estimate and the second estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold. In other features, the control module sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio.

In other features, the memory system includes a defect detection module that detects a defect of the memory based on the first estimate and not the second estimate. In other features, the first estimate includes at least one of a signal-to-noise ratio and an estimated count of pilot signal errors.

In other features, each of the first estimate and the second estimate includes at least one of a mean value, a variance value, and a distance between mean values. In other features, the memory system includes a slicer that detects when at least one of the first estimate and the second estimate exceeds a threshold.

In other features, the first parameter estimation module generates the first estimate based on a first least means squared (LMS) process, and the second parameter estimation module generates the second estimate based on a second LMS process. In other features, the second parameter estimation module generates the second estimate based on an iterative process that is initialized with the first estimate.

In other features, a memory system is provided and includes a first parameter estimation module that receives the pilot signals based on a read signal from a memory and that generates a first estimate of a signal quality value. The signal quality value is associated with a block of the memory based on reference pilot information. A detection module detects a defect in the block based on the first estimate. A control module that alters access to the block based on the defect.

In other features, the memory system includes a storage device that stores the pilot signals based on the read signal. The first paragraph estimation module receives the pilot signals from the storage device. In other features, the control module selectively prevents writing to, reading from, and erasing from the block based on the defect.

In other features, the control module selectively prevents writing to the block when the first estimate exceeds a first threshold and selectively prevents access to the block when the first estimate exceeds a second threshold.

In other features, the control module selectively adjusts access to the memory when at least one of the first estimate and a second estimate of the signal quality value exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold.

In other features, the control module sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the first parameter estimation module generates the first estimate based on a first least means squared (LMS) process.

In other features, the control module alters access to the block based on the first estimate and a second estimate that is generated via a second LMS process that is based on the first estimate. In other features, the second LMS process is an iterative process that is initialized with the first estimate.

In other features, the memory system includes a second parameter estimation module that generates a second estimate of the signal quality value based on at least one of the first estimate and user data signals. The user data signals are generated based on user data stored in the block. The detection module detects the defect based on the second estimate.

In other features, the memory system includes a defect memory that stores a defect map of defects of the block. In other features, the defect map maps signal quality values to locations of the memory. In other features, the memory system includes an error counter that has an error value that is incremented when an error in one of the pilot signals is detected.

In other features, the detection module stores the error value in a defect memory in reference to the block. In other features, the memory system includes a signal processing module that generates recovered user data that is based on user data that is stored in the memory and the first estimate.

In other features, the memory system includes a second parameter estimation module that generates a second estimate of the signal quality value based on at least one of the first estimate and user data signals stored in the memory. In other features, the detection module detects the defect based on the first estimate and the second estimate.

In other features, the detection module detects the defect based on the first estimate and not the second estimate. In other features, the first estimate includes a signal-to-noise ratio value. In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In other features, a memory system is provided and includes a first parameter estimation module that generates a first estimate of a signal quality value based on user data signals. The user data signals are generated based on a read signal from a memory. A detection module detects a defect in a block of the memory based on the first estimate. A control module alters access to the block based on the defect.

In other features, the memory system includes a storage device that stores the user data signals based on the read signal, the first parameter estimation module receives the user data signals from the storage device.

In other features, the control module prevents writing to, reading from, and erasing from the block based on the defect. In other features, the control module prevents writing to the block when the first estimate exceeds a first threshold and prevents access to the block when the first estimate exceeds a second threshold.

In other features, the control module adjusts access to the memory when the first estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error threshold.

In other features, the control module sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the first parameter estimation module generates the first estimate based on a first least means squared (LMS) process.

In other features, the control module alters access to the block based on the first estimate and a second estimate that is generated via a second LMS process that is based on the first estimate. In other features, the second LMS process is an iterative process that is initialized with the first estimate.

In other features, the memory system includes a second parameter estimation module that generates a second estimate of the signal quality value based on the first estimate and pilot signals. The pilot signals are generated based on pilot data stored in the memory. The detection module detects the defect based on the second estimate.

In other features, the memory system includes a defect memory that stores a defect map that stores a defect map of defects of the block. In other features, the defect map maps signal quality values to locations of the memory.

In other features, the memory system includes an error counter that has an error value that is incremented when an error in one of the user data signals is detected. In other features, the memory detection module stores the error value in a defect memory in reference to the block.

In other features, the first parameter estimation module generates the first estimate based on a decision feedback signal generated based on a decoded user data signal. In other features, the memory system includes a signal processing module that generates recovered user data based on the user data signals and the first estimate.

In other features, the memory system includes a second parameter estimation module that generates a second estimate of the signal quality value based on pilot signals that are generated based on pilot data stored in the block.

In other features, the detection module detects the defect based on the first estimate and the second estimate. In other features, the detection module detects the defect based on the first estimate and not the second estimate.

In other features, the first estimate includes a signal-to-noise ratio value. In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In other features, a method of operating a memory system is provided and includes receiving pilot signals that are generated based on pilot data stored in a memory. A first estimate of a signal quality value associated with a block of the memory is generated based on reference pilot information. A second estimate of the signal quality value is generated based on the first estimate and user data signals that are generated based on user data stored in the memory. Recovered user data is generated based on the second estimate.

In other features, the method includes storing the pilot signals based on a read signal from the memory in a first storage device. The user data signals are stored based on a read signal from the memory in a second storage device.

In other features, the method includes providing a coarse estimate of the signal quality value and providing a fine estimate of the signal quality value. In other features, the pilot data and the user data are stored in the block. In other features, the method includes generating the pilot signals and user data signals based on the read signal from the memory.

In other features, the method includes storing the pilot data in the memory when the user data is stored in the memory. In other features, the method includes reading the pilot data from the memory when the user data is read from the memory. In other features, the method includes removing the pilot data from the memory when the user data is removed from the memory. In other features, the method includes altering the pilot data between access events to pilot cells of the memory.

In other features, the reference pilot information is hard-coded into firmware of the memory system. In other features, the reference pilot information is generated based on an algorithm run by the memory system. In other features, the reference pilot information is stored in the memory as the pilot data during an initial access to the memory.

In other features, the method includes storing the reference pilot information in another memory. In other features, the method includes detecting a defect of the memory based on at least one of the first estimate and the second estimate; and adjusting access to the memory based on the defect.

In other features, the method includes adjusting access to the memory when at least one of the first estimate and the second estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold.

In other features, the method includes setting the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio.

In other features, the method includes detecting a defect of the memory based on the first estimate and not the second estimate.

In other features, the first estimate includes at least one of a signal-to-noise ratio and an estimated count of pilot signal errors. In other features, each of the first estimate and the second estimate includes at least one of a mean value, a variance value, and a distance between mean values.

In other features, the method includes detecting when at least one of the first estimate and the second estimate exceeds a threshold. In other features, the first estimate is generated based on a first least means squared (LMS) process. The second estimate is generated based on a second LMS process. In other features, the second estimate is generated based on an iterative process that is initialized with the first estimate.

In other features, a method of operating a memory system is provided and includes receiving the pilot signals based on a read signal from a memory. A first estimate of a signal quality value associated with a block of the memory is generated based on reference pilot information. A defect in the block is detected based on the first estimate. Access to the block is altered based on the defect.

In other features, the method includes storing the pilot signals based on the read signal, and receiving the pilot signals from a storage device. In other features, the method includes selectively preventing writing to, reading from, and erasing from the block based on the defect.

In other features, the method includes selectively preventing writing to the block when the first estimate exceeds a first threshold and selectively prevents access to the block when the first estimate exceeds a second threshold.

In other features, the method includes selectively adjusting access to the memory when at least one of the first estimate and a second estimate of the signal quality value exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold.

In other features, the method includes setting the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the first estimate is generated based on a first least means squared (LMS) process.

In other features, the method includes altering access to the block based on the first estimate and a second estimate that is generated via a second LMS process that is based on the first estimate. In other features, the second LMS process is an iterative process that is initialized with the first estimate.

In other features, the method includes generating a second estimate of the signal quality value based on at least one of the first estimate and user data signals. The user data signals are generated based on user data stored in the block. The defect is detected based on the second estimate.

In other features, the method includes storing a defect map of defects of the block in a defect memory. In other features, the defect map maps signal quality values to locations of the memory.

In other features, the method includes incrementing an error value of an error counter when an error in one of the pilot signals is detected. In other features, the method includes storing the error value in a defect memory in reference to the block. In other features, the method includes generating recovered user data that is based on user data that is stored in the memory and the first estimate.

In other features, the method includes generating a second estimate of the signal quality value based on at least one of the first estimate and user data signals stored in the memory.

In other features, the defect is detected based on the first estimate and the second estimate. In other features, the defect is detected based on the first estimate and not the second estimate. In other features, the first estimate includes a signal-to-noise ratio value.

In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In other features, a method of operating a memory system is provided and includes generating a first estimate of a signal quality value based on user data signals. The user data signals are generated based on a read signal from a memory. A defect in a block of the memory is detected based on the first estimate. Access to the block is altered based on the defect.

In other features, the method includes storing the user data signals based on the read signal in a storage device; and receiving the user data signals from the storage device. In other features, the method includes preventing writing to, reading from, and erasing from the block based on the defect.

In other features, the method includes preventing writing to the block when the first estimate exceeds a first threshold and prevents access to the block when the first estimate exceeds a second threshold.

In other features, the method includes adjusting access to the memory when the first estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error threshold.

In other features, the method includes setting the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the method includes generating the first estimate based on a first least means squared (LMS) process.

In other features, the method includes altering access to the block based on the first estimate and a second estimate. The second estimate is generated via a second LMS process that is based on the first estimate.

In other features, the second LMS process is an iterative process that is initialized with the first estimate. In other features, the method includes generating a second estimate of the signal quality value based on the first estimate and pilot signals that are generated based on pilot data stored in the memory. The defect is detected based on the second estimate.

In other features, the method includes storing a defect map of defects of the block in a defect memory. In other features, the defect map maps signal quality values to locations of the memory.

In other features, the method includes incrementing an error value of an error counter when an error in one of the user data signals is detected. In other features, the method includes storing the error value in a defect memory in reference to the block.

In other features, the method includes generating the first estimate based on a decision feedback signal generated based on a decoded user data signal. In other features, the method includes generating recovered user data based on the user data signals and the first estimate.

In other features, the method includes generating a second estimate of the signal quality value based on pilot signals that are generated based on pilot data stored in the block. In other features, the method includes detecting the defect based on the first estimate and the second estimate.

In other features, the method includes detecting the defect based on the first estimate and not the second estimate. In other features, the first estimate includes a signal-to-noise ratio value.

In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In other features, a memory system is provided and includes first parameter estimation means for receiving pilot signals that are generated based on pilot data stored in a memory. The first parameter estimate means generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. Second parameter estimation means generates a second estimate of the signal quality value based on the first estimate and user data signals that are generated based on user data stored in the memory. Processing means generates recovered user data based on the second estimate.

In other features, the memory system includes first storage means for storing the pilot signals based on a read signal from the memory. Second storage means stores the user data signals based on a read signal from the memory.

In other features, the first parameter estimation means provides a coarse estimate of the signal quality value and the second parameter estimation means provides a fine estimate of the signal quality value. In other features, the pilot data and the user data are stored in the block.

In other features, the memory system includes demultiplexing means for generating the pilot signals and user data signals based on the read signal from the memory. In other features, the memory system includes the memory. In other features, the memory includes non-volatile memory.

In other features, the processing means stores the pilot data in the memory when the user data is stored in the memory. In other features, the processing means reads the pilot data from the memory when the user data is read from the memory. In other features, the processing means removes the pilot data from the memory when the user data is removed from the memory. In other features, the processing means alters the pilot data between access events to pilot cells of the memory.

In other features, the memory system of claim1further includes pilot generating means for generating the reference pilot information. In other features, the reference pilot information is hard-coded into firmware of the memory system. In other features, the reference pilot information is generated based on an algorithm run by the memory system. In other features, the reference pilot information is stored in the memory as the pilot data during an initial access to the memory.

In other features, the memory system includes another memory that stores the reference pilot information. In other features, the memory system includes defect detection means for detecting a defect of the memory based on at least one of the first estimate and the second estimate. Control means adjusts access to the memory based on the defect.

In other features, the control means adjusts access to the memory when at least one of the first estimate and the second estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold.

In other features, the control means sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the memory system includes defect detection means for detecting a defect of the memory based on the first estimate and not the second estimate.

In other features, the first estimate includes at least one of a signal-to-noise ratio and an estimated count of pilot signal errors. In other features, each of the first estimate and the second estimate includes at least one of a mean value, a variance value, and a distance between mean values. In other features, the memory system includes slicing means for detecting when at least one of the first estimate and the second estimate exceeds a threshold.

In other features, the first parameter estimation means generates the first estimate based on a first least means squared (LMS) process. The second parameter estimation means generates the second estimate based on a second LMS process.

In other features, the second parameter estimation means generates the second estimate based on an iterative process that is initialized with the first estimate.

In other features, a memory system is provided and includes first parameter estimation means for receiving the pilot signals based on a read signal from a memory. The first parameter estimation means generates a first estimate of a signal quality value associated with a block of the memory based on reference pilot information. Detection means detects a defect in the block based on the first estimate. Control means alters access to the block based on the defect.

In other features, the memory system includes storage means for storing the pilot signals based on the read signal. The first paragraph estimation means receives the pilot signals from the storage device. In other features, the control means selectively prevents writing to, reading from, and erasing from the block based on the defect.

In other features, the control means selectively prevents writing to the block when the first estimate exceeds a first threshold and selectively prevents access to the block when the first estimate exceeds a second threshold.

In other features, the control means selectively adjusts access to the memory when at least one of the first estimate and a second estimate of the signal quality value exceeds a threshold.

In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error count threshold.

In other features, the control means sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the first parameter estimation means generates the first estimate based on a first least means squared (LMS) process.

In other features, the control means alters access to the block based on the first estimate and a second estimate that is generated via a second LMS process that is based on the first estimate. In other features, the second LMS process is an iterative process that is initialized with the first estimate.

In other features, the memory system includes a second parameter estimation means that generates a second estimate of the signal quality value based on at least one of the first estimate and user data signals. The user data signals are generated based on user data stored in the block. The detection means detects the defect based on the second estimate.

In other features, the memory system includes defect storing means for storing a defect map of defects of the block. In other features, the defect map maps signal quality values to locations of the memory.

In other features, the memory system includes error counting means for counting an error value that is incremented when an error in one of the pilot signals is detected. In other features, the detection means stores the error value in a defect memory in reference to the block.

In other features, the memory system includes a signal processing means that generates recovered user data that is based on user data that is stored in the memory and the first estimate. In other features, the memory system includes a second parameter estimation means that generates a second estimate of the signal quality value based on at least one of the first estimate and user data signals stored in the memory.

In other features, the detection means detects the defect based on the first estimate and the second estimate. In other features, the detection means detects the defect based on the first estimate and not the second estimate. In other features, the first estimate includes a signal-to-noise ratio value. In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In other features, a memory system is provided and includes first parameter estimation means for generating a first estimate of a signal quality value based on user data signals. The user data signals are generated based on a read signal from a memory. Detection means detects a defect in a block of the memory based on the first estimate. Control means alters access to the block based on the defect.

In other features, the memory system includes storing means for storing the user data signals based on the read signal. The first parameter estimation means receives the user data signals from the storage device.

In other features, the control means prevents writing to, reading from, and erasing from the block based on the defect. In other features, the control means prevents writing to the block when the first estimate exceeds a first threshold and prevents access to the block when the first estimate exceeds a second threshold.

In other features, the control means adjusts access to the memory when the first estimate exceeds a threshold. In other features, the threshold includes at least one of a mean threshold, a variance threshold, a distance between mean values threshold, a signal-to-noise ratio threshold, and an error threshold.

In other features, the control means sets the threshold based on at least one of an ambient temperature, a number of access cycles, and a signal-to-noise ratio. In other features, the first parameter estimation means generates the first estimate based on a first least means squared (LMS) process.

In other features, the control means alters access to the block based on the first estimate and a second estimate that is generated via a second LMS process that is based on the first estimate. In other features, the second LMS process is an iterative process that is initialized with the first estimate.

In other features, the memory system includes a second parameter estimation means that generates a second estimate of the signal quality value based on the first estimate and pilot signals. The pilot signals are generated based on pilot data stored in the memory. The detection means detects the defect based on the second estimate.

In other features, the memory system includes defect storing means for storing a defect map that stores a defect map of defects of the block. In other features, the defect map maps signal quality values to locations of the memory.

In other features, the memory system includes error counting means for counting an error value that is incremented when an error in one of the user data signals is detected. In other features, the memory detection means stores the error value in a defect memory in reference to the block.

In other features, the first parameter estimation means generates the first estimate based on a decision feedback signal generated based on a decoded user data signal. In other features, the memory system includes signal processing means for generating recovered user data based on the user data signals and the first estimate.

In other features, the memory system includes second parameter estimation means for generating a second estimate of the signal quality value based on pilot signals that are generated based on pilot data stored in the block.

In other features, the detection means detects the defect based on the first estimate and the second estimate. In other features, the detection means detects the defect based on the first estimate and not the second estimate. In other features, the first estimate includes a signal-to-noise ratio value. In other features, the first estimate includes at least one of a mean value, a variance value, a standard deviation value, and a distance between mean values.

In still other features, the systems and methods described above are implemented by a computer program executed by one or more processors. The computer program can reside on a computer readable medium such as but not limited to memory, non-volatile data storage and/or other suitable tangible storage mediums.

DETAILED DESCRIPTION

In the following description many different embodiments are disclosed including various different aspects. The aspects described with respect to one embodiment are not specific to a single embodiment and may be applied to other embodiments of the present disclosure. In addition, the terms first and second are used arbitrarily. The terms may be interchanged based on the context and/or reference. The term defect refers to a flaw in one or more cells of a memory. Defect does not refer to an error in data stored in those cells. However, errors in data that is stored in the cells or in data recovered from the cells may be used to detect a defect associated with the cells.

A memory device may include non-volatile memory or volatile memory. The memory may include cache, solid-state memory, semiconductor memory, magnetic memory, memory integrated within a module or a stand-alone memory. Although the embodiments disclosed herein are primarily described with respect to non-volatile memory, the embodiments may be applied to volatile memory as well. A memory device may include hard or soft defects. The embodiments disclosed herein detect and determine the types of the defects. The soft defects may occur due to use and/or aging of the memory device over time.

A memory device may be arranged in a hierarchy having levels that are based on memory block size. Example levels in order of decreasing size include zones, sectors, pages, and/or arrays. A zone may include multiple sectors, which may each in turn include multiple pages. The pages may each include multiple arrays. Each array may contain any number of cells. A block of memory may refer to any portion of one or more of the stated levels.

In the following description, the term pilot data refers to predetermined data that is stored and/or generated by a system. The pilot data may include a predetermined data pattern that is stored during manufacture of the memory or during use of a memory. The data pattern is subject to similar disturbances and defects as other data stored in the memory. The pilot data may be generated during operation of a system via an algorithm. The algorithm may use stored and/or hard-coded values to generate the pattern. The pilot data may be stored in various locations in a memory device.

Pilot signals are generated when reading pilot data from a block of a memory device. A processing module may analyze the pilot signals based on the pilot data. The processing module may determine statistical parameters, such as signal quality parameters, which include signal parameters and noise parameters based on the analysis. The signal parameters may include mean values, distance between mean values, error count values, etc. The noise parameters may include signal-to-noise ratio (SNR) values, variance values, standard deviation values, and other disturbance values.

The statistical parameters may vary across different logical and physical pages and/or blocks of memory due to read/write cycling, manufacturing variations, and/or operating environment conditions. A processing module may determine the statistical parameters based on a comparison of a pilot signal to predetermined pilot information. Increasing the number of locations for pilot data may increase the accuracy of the determinations.

A physical page may be a grouping of memory cells having a hardwired size. A logical page may include formatted start and end-points within one or more physical pages. Logical pages may be used when data to be stored in memory has a length that differs from a length of a physical page. A logical page may be segmented and saved in multiple physical pages. A control module may set locations for storage of pilot data based on physical and/or logical page addressing.

Referring now toFIG. 1, a functional block diagram of a memory system10that includes a host14and memory16. The host14includes a memory control module17with write path modules18, read path modules20, a main control module22and a memory processing module12. The write path modules18write user data and/or pilot data to the memory16. The read path modules20read user data and/or pilot data from the memory16. The write and read path modules18and20may operate based on control signals from the main control module22. The main control module22may include software and/or firmware for facilitating read and write functions of the memory system10. The memory system10and the memory processing module12detect, identify and handle defective cells of the memory16.

The memory processing module12may include software and/or firmware and determines statistical parameter values. Data is recovered based on the statistical parameter values. The statistical parameter values may be generated in association with a level of memory hierarchy, such as in association with a page or a block of a memory. This minimizes errors in the recovered data. The memory processing module12may also provide information to the main control module22and the write and read path modules18and20for updated system operation relative to the defective cells. The updated operation refers to how a defective cell is accessed based on a permitted access state. For example, the main control module22may not perform write and/or read tasks when accessing a defective cell based on the statistical parameter values generated by the memory processing module12.

A block24of the memory16may wear out over time. The block24may wear out, for example, due to repeated writing and reading to and from the block24. As the block24degrades from use, different status states may be assigned to that block24. A first state may have a label of “Good” indicating that the block24may be used for both read and write tasks. A second state may have a label of “Average” indicating that data may be read from the block24and that data may not be written to the block24. A third state may have a label of “Bad” indicating that the block24may not be used for read and write tasks. The described states are provided as examples; other states may be incorporated in the disclosed embodiments. The memory processing module12may provide the current state of each block of the memory16to the main control module22and/or the write and read path modules18and20to assist in blocks access control.

The memory16may include non-volatile or volatile memory. The memory16may be a solid state or semiconductor memory, such as RAM, ROM, flash memory, etc. The memory16may include magnetic memory.

Referring now toFIG. 2, a functional block diagram of a memory system40is shown. The memory system40includes a host44and a memory46. The host44includes a memory control module47with write path modules48, read path modules50, a main control module52and a memory processing module53. The write path modules48write user data and/or pilot data to the memory46. The read path modules50read user data and/or pilot data from the memory46. The write and read path modules48,50may operate based on control signals generated by the mean control module52. The host44may also include a format module54, a pilot generator56, and a type determining module58.

The memory processing module53may determine the statistical parameter values based on differences between the expected or predetermined pilot information and recovered pilot data. The recovered pilot data is obtained from pilot signals that are generated based on read signals generated when reading the cells of the memory46, which contain the pilot data. These cells are referred to as pilot cells. The cells of the memory46that are associated with pilot data may be changed over time. In other words, the pilot data may not be stored in the same cells of the memory46during access to the memory46.

The memory processing module53may include an algorithm that determines the statistical parameter values and may adapt the algorithm for subsequent read/write operations. In one embodiment, the memory processing module53reads from, writes to, and erases pilot information when user data is read, written, or erased in a corresponding block of the memory46. This assures that the pilot cells experience similar usage degradation as the user data cells. Thus, statistical parameter values that are generated in association with the pilot cells are representative of signal quality and disturbance values associated with the user data cells.

The memory control module47may communicate with the memory46via the write and read path modules48,50. In one embodiment, the memory46includes non-volatile semiconductor memory. The memory46may include one or more arrays60-1,60-2, . . . , and60-A of memory cells. The arrays60may be arranged in memory blocks62-1,62-2, . . . , and62-X. The memory control module47may vary the number of memory cells per page or block in the memory46. The memory control module47may vary the number of memory cells allocated for data and overhead portions of each page. The memory control module47may also determine locations for pilot data within the memory46. The data stored in pilot cells64-1,64-2, . . . , and64-X of the memory46may be predetermined data and may be reliably used to estimate signal, noise, and disturbance parameters.

The memory control module47may include the memory processing module53, the format module54, and/or the type determining module58. The memory processing module53may determine statistical parameter values of cells in the memory46. In use, the memory control module47writes pilot data to locations in the memory46. The memory processing module53reads the data back and compares the read-back data to predetermined pilot information, which may be stored in the pilot generator56.

The pilot generator56may be implemented as part of the write and read path modules48and50, the main control module52. The pilot generator56may also be implemented as a separate storage device as shown. The pilot generator56may be used to generate pilot data, which is stored in the memory46. The pilot data may be generated and repeatedly altered. The pilot generator56may include a pilot buffer57and be used to store and/or generate predetermined pilot information, which may include or be used to generate predetermined pilot data that is the same as initially stored pilot data. The pilot information is compared with recovered pilot data from the memory46to determine statistical parameter values. The statistical parameter values may vary for each block of the memory46.

The format module54may include a pilot location module70that sets locations for pilot data in the memory46. The format module54may set locations for pilot data at a start, middle, and/or end of a physical page and/or a logical page. The format module54may also distribute locations for pilot data according to a predetermined pattern. Physical pages may be predefined and hardwired into the memory46.

The format module54may format the memory46based on locations for pilot data. Formatting may include generating a memory map. Therefore, when data that is not pilot data is read from the memory46, that data is stored in locations other than the locations for pilot data. The format module54may also adjust the memory map based on the signal processing algorithm. For example, when the memory processing module53determines that a portion of the memory46is damaged, the format module54may map the memory to discontinue use of that portion.

The type determining module58may be used to determine a type of memory that has been connected to the memory control module47, such as the type of the memory46. The type determining module58may use any method such as, but not limited to, communicating with the memory46and receiving configuration information. The configuration information may be stored in a setup portion of the memory46and have a standard or predetermined configuration. The memory control module47may read the setup portion and configure the rest of the memory46.

Once the memory type is determined, the format module54may receive memory configuration information from the type determining module58. Based on the information, the format module54may determine a predetermined arrangement of locations for pilot data for both physical and logical pages and/or blocks. The format module54may alternatively generate the locations for pilot data. The format module54may also determine the start and end of locations or addresses for each page and/or block, the density of memory cells, the number of error correction code or other overhead data (ECC/O) bytes per page, and generate the locations for pilot data based thereon.

The write and read modules48,50write and read data to and from the memory46based on the memory configuration as determined by the format module54. The write and read modules48,50write and read data to and from locations associated with the pilot data and user data, as well as to other locations in the memory46.

Referring now also toFIG. 3, an exemplary memory block80that includes pages82-1,82-2, . . . , and82-Q with variable density, page length and/or overhead is shown. The main control module52may vary the number of memory cells per page, the number of bits per memory cell, and/or the relative number of memory cells associated with the data portion and the overhead portion, respectively. Pilot data may be stored separately from the pages82or as part of each of the pages82, as designated by pilot data84and pilot data86-1,86-2, . . . , and86-Q, respectively. The pilot data may be included as part of the overhead of each of the pages. The format module54may vary locations for pilot data based on the page structure determined by the main control module52.

Referring now also toFIG. 4, an exemplary page90that includes memory cells associated with a data portion92and an overhead portion94is shown. The data portion92may include variable length/density (VL/D) cells, user data memory cells (MC), and/or other data cells. The overhead portion94may include VL/D cells, MC, pilot data cells, ECC/O cells, and/or other data cells.

Referring now also toFIG. 5, an exemplary pilot location module100is shown. The format module54may include a pilot location module that sets locations for pilot data in the memory46. The pilot location module100may include a pilot program module102that programs predetermined patterns into locations of the memory46to facilitate fast acquisition of signal, noise and disturbance parameters.

The pilot location module100may set locations for pilot data in different locations relative to a physical page. For example, the pilot location module100may set locations for pilot data at the start, end and/or at a fixed segment, for example, in the middle of the physical page. The pilot location module100may also set locations for pilot data throughout the physical page in a predefined pattern, for example, evenly spaced throughout the physical page.

The pilot location module100may also set locations for pilot data in different locations relative to a logical page. For example, the pilot location module100may set locations for pilot data at the start, end, and/or at a fixed segment, for example, in the middle of the logical page. The pilot location module100may also set locations for pilot data throughout the logical page in a predefined pattern, for example, evenly spaced throughout the logical page.

Referring now toFIG. 6, a functional block diagram illustrating the memory processing module53is shown. The memory processing module53includes a demultiplexer110, a parameter estimation module111with an acquisition path112and a tracking path114, and a signal processing module116. A read module120accesses and reads data from the memory46. The data is provided to the demultiplexer110, which divides the data into parallel paths, the acquisition path112and the tracking path114. The demultiplexer110generates pilot signals and user data signals based on the data read from the memory46. The pilot signals are provided to the acquisition path112and the user data signals are provided to the tracking path114.

The acquisition path112includes a pilot cell signal buffer120and an acquisition module122. The pilot cell signal buffer120stores the pilot cell signals. The pilot cell signal buffer120may be a non-volatile or volatile storage device that is an integrated part of the memory processing module53or may be a separate storage device. The acquisition module122generates rough estimates of statistical parameter values associated with the pilot signals. The acquisition module122may be referred to as a first or second parameter estimation module. The rough estimates are representative of statistical parameter values associated with the user data signals for the corresponding block of memory that includes the pilot data.

In one embodiment, the acquisition module122generates a first estimate of SNR for the pilot signals. The pilot signals are compared with predetermined pilot information. The predetermined pilot information may be received from the pilot generator56ofFIG. 2, generated by the memory processing module53, or received from and/or generated by another module of the corresponding memory system.

A first least means squared (LMS) technique may be used to generate the first SNR estimate. The first LMS technique may be a high-speed high-bandwidth technique. The first LMS technique is an iterative technique that makes successive corrections to provide a minimum mean-square-error estimation. The LMS technique monitors Gaussian distributions of values associated with the pilot data to determine mean, variance, and standard deviation parameter values. As an example, the mean mpand variance σp2for the p-th signal level may be determined via the following set of equations:
mp(k)=mp(k−1)+μm(rp(k)−mp(k−1))  (1)
σp2(k)=σp2(k−1)+μσ[(rp(k)−mp(k−1))2−σp2(k−1)]  (2)

The mean mp(k) and variance σp2(k) represent the mean and variance estimate after receiving the k-th signal sample for the p-th signal level, respectively; mp(k−1) and σp2(k−1) represent the previous mean and variance estimate, where μmand μσare adaptation constants for the mean and variance estimates, respectively. Note that the range of p is determined by the number of signal levels for the flash cell as well as the pilot pattern. For example, for 2 bits per cell flash cell, where pilot patterns include all 4 possible signal levels, p takes the values between 0 and 3. After the mean and variance are estimated, an SNR value can be calculated based on the estimated values. For example an estimate of SNR can be defined as provided in equation 3.

In equation 3, d1and σ1are the average of the distance between estimated means and standard deviations for all p. In other words, the distance d1may be as provided by equation 4 and the standard deviations σ1may be as provided by equation 5, where M is the total number of signal levels.

The initial mean values mp(0) and variance values σp2(0) for p=0, . . . , M−1 may be determined and/or provided based on the predetermined pilot information. The average variance σ2and SNR values may be continuously updated, stored and based on previously determined variance and SNR values. As the memory46is used, the mean estimate values mpand variance estimates σp2may change in position and/or magnitude.

A mean estimate value may be associated with each possible actual data value. For example, the possible values for two bits of data in binary are 00, 01, 10, and 11. A mean value may be generated that is associated with each of the possible two bit values for received data signals. The mean values represent the peaks of a distribution of recovered values about each of the possible data values. For example, zero (0)A may be associated with the bit value 00, where A is amperage. A distribution value range may be −0.5-0.5 mA with a peak at 0 mA. Similar distribution value ranges may exist for the other possible bit values. The distribution values may be based on voltages in stead of current values to provide voltage distributions.

As a memory cell is used, the distance d decreases and the standard deviation σ increases. Therefore, there may be increased overlap in distributions associated with each mean estimate value. Continuing from the above example, as the memory46is used, the range for bit value 00 may increase to −2-2 mA. Thus, depending on the adjacent bit value range, overlap between ranges may exist or be increased over use. Thus, the potential for error increases and the SNR decreases.

Output parameter estimates generated by the acquisition module122may be provided to the tracking path114and/or the signal processing module116. When provided to the tracking path114further refinements in the parameters may be performed.

The tracking path114includes a user data signal buffer130and a tracking module132. The user data signal buffer130receives and stores the user data signals that are based on encoded user data stored in the memory46. The user data signal buffer130may include non-volatile and/or volatile storage devices that are an integrated part of the memory processing module53or may be a separate storage device. The tracking module132generates second estimates of statistical parameter values, including a second SNR estimate, associated with the user data signals. The tracking module132may be referred to as a first or second parameter estimation module. The second SNR estimate may be based on the first SNR estimate. In one embodiment, the second SNR estimate is based on the user data signals and not the first SNR estimate. This may occur when pilot data signals are not available.

A second LMS technique may be used to generate the second SNR estimate. The second LMS technique may be a low-speed low-bandwidth technique. The second LMS technique is also an iterative technique that makes successive corrections to provide a minimum mean square error. The second LMS technique monitors a distribution of values associated with the pilot data to determine mean, variance, and standard deviation values. The second LMS technique may be performed based on output estimates from the first LMS technique and through use of equations 6 and 7, where μm′ and μσare adaptation constants. It is customary to have μm′<μmand μσ′<μσto achieve low-bandwidth adaptation. This affects the speed of the estimation.
mp(k)=mp(k−1)+μm′(rp(k)−mp(k−1))  (6)
σp2(k)=σp2(k−1)+μσ′[(rp(k)−mp(k−1)2−σp2(k−1)]  (7)
Similar to Eq. (2), a second estimate of the SNR can be estimated based on the adapted mean and variance values, viz.

In equation 8, d2and σ2are the average of the distance between estimated means and standard deviations for all p.

The initial mean m variance σ2for Equations 6 and 7 may be set equal to the converged value determined by the acquisition module122. Other statistical parameter values may also be provided from the acquisition module122to the tracking module132.

As memory cells are used the distance d2decreases and the standard deviation σuincreases, thus there may be increased overlap in distributions associated with each mean estimate value. Thus, depending on the adjacent bit value range, overlap between ranges may exist or be increased. Thus, the potential for error increases and the second SNR estimate decreases.

The parameter values, such as the variance and SNR values, determined in the tracking module132may be based on the data recovered prior to or after ECC values determined in the signal processing module116. This is referred to as decision feedback tracking. This accounts for errors in decoded user data signals. As shown, a decision feedback signal134may be provided from the signal processing module116to the tracking module132.

The signal processing module116performs adaptive processing to generate recovered user data based on the user data signals, the first parameter values and/or the second parameter values. For low latency applications, the acquired parameters can be directly used by the signal processing module116by bypassing the fine-tuning process imposed by the tracking module132. For latency insensitive applications, both the acquired and tracking parameters may be used.

As an example, when performing low-density parity-check (LDPC) decoding an estimate of variance, such as noise variance, is used. The estimate of variance generated in the acquisition module122or in the tracking module132may be used, depending upon system latency requirements. As another example, an estimate of SNR may be used when performing iterative decoding, such as during turbo code decoding.

Initial statistical parameter values, such as initial variance, SNR, and mean values, may be stored and used as reference values in comparisons with subsequently generated parameter values of the first and second LMS techniques. The initial parameter values may be stored in any one of the memories or modules disclosed herein or generated during operation of a memory system.

Referring now toFIG. 7, a functional block diagram of a memory system150is shown. The memory system150includes a host154and a memory156. The host154includes a memory control module158with write path modules160, read path modules162, a main control module164and a defect handling module165. The write path modules160write user data and/or pilot data to the memory156. The read path modules162read user data and/or pilot data from the memory156. The host158may also include a format module166, a pilot generator168with a pilot buffer169, and a type determining module170.

The memory control module158may communicate with the memory156via the write and read path modules160,162. In one embodiment, the memory156is a non-volatile semiconductor memory. The memory156may include one or more arrays180-1,180-2, . . . , and180-A of memory cells. The arrays180may be arranged in memory blocks182-1,182-2, . . . , and182-X.

The defect handling module165in addition to generating statistical parameter values performs defect handling. A defect refers to a degraded aspect of a cell of the memory156. Access to the memory156is adjusted based on predetermined and detected defects.

The defect information may be stored in a defect memory190that stores a defect map192. The defect map192may include a defect state of each of the blocks of cell of the memory156. The defect memory190may be incorporated in the memory control module158, incorporated in another module, or be a separate memory device. For each block of the memory156, the defect map192may include the following entries, a block identification (ID), a bock defect state, and one or more statistical parameter values associated with that block. The statistical parameter values may include variance values, SNR values, standard deviation values, etc. Other example statistical parameter values are disclosed herein. The information stored in the defect memory190may be available to the write and read modules160,162, the main control module164, and/or other modules of a memory system.

Referring now toFIG. 8, a functional block diagram illustrating an exemplary defect handling module200is shown. The defect handling module200includes a demultiplexer202, a parameter estimation module203with an acquisition path204and a tracking path206, a signal processing module208and a defect detection module210. A read module212accesses and reads data from a memory214. The data is provided to a demultiplexer202, which divides the data into parallel paths, the acquisition path204and the tracking path206. The demultiplexer202generates pilot signals and user data signals based on the data read from the memory214. The pilot signals are provided to the acquisition path204and the user data signal are provided to the tracking path206.

The acquisition path204includes a pilot cell signal buffer220and an acquisition module222. The pilot cell signal buffer220stores the pilot cell signals. The acquisition module222generates rough estimates of statistical parameter values associated with the pilot signals. In one embodiment, the acquisition module222generates a first estimate of SNR for the pilot signals. The pilot signals are compared with predetermined pilot information.

The first LMS technique may be used to generate the first SNR estimate, as described with respect to the embodiment ofFIG. 6. The first LMS technique may be a high-speed high-bandwidth technique. The standard deviation σ and the SNR estimate may be determined via Equations 1, 2, and 3.

Output parameter estimates generated by the acquisition module222may be provided to the tracking path206and/or the signal processing module208. When provided to the tracking path206further refinement in the parameters is performed.

The tracking path206includes a user data signal buffer224and a tracking module226. The user data signal buffer224receives and stores the user data signals. The tracking module226generates a second estimate of statistical parameter values, such as a second SNR estimate, associated with the user data signals.

The second LMS technique may be used to generate the second SNR estimate, as described with respect to the embodiment ofFIG. 6. The second LMS technique may be a low-speed low-bandwidth technique. The second LMS technique may be performed based on output estimates from the first LMS technique and through use of equations 6 and 7.

The parameters and differences may be stored in a defect map230of a defect memory232. The differences may be stored and/or compared with predetermined threshold values and/or predetermined threshold ranges. Initial parameter values may be stored and used as reference values in comparisons with subsequently generated SNR values. The information stored in the defect memory232may be available to write and read module, such as a write module234, the read module212, a main control module240, or other modules of a memory system.

When a parameter exceeds a threshold value or is outside of a threshold range, the defect detection module210may set a flag or change defect state of a page or block of cells associated with that parameter. Future use of the flagged cells may be restricted. As an alternative to using SNR values for defect detection and user data recovery, other parameter values may be used. In one embodiment, a defect flag is set when: A) a difference between an estimated mean value and a reference value exceeds a first threshold; B) a margin (distance) between estimated mean values is less than a second threshold; C) an estimated noise variance exceeds a third threshold; and any combination of A-C exists.

In one embodiment, when a first threshold value is exceeded, access to a corresponding block is limited to read and erase (remove) functions. When a second threshold is exceeded, access to a corresponding block is prevented.

As stated, when pilot signals are available, defect detection may be performed based on the pilot signals and/or the user data signals. As an example, the pilot and/or user data signals may be used to determine estimated SNR values, estimated signal parameters, estimated noise parameters, or a combination thereof.

Also, as the mean values shift, due to differences in current mean estimate values and the initial mean estimate value, performance of a memory decreases. This shift can be caused by leakage. A memory may include floating gates. Over time the ability of the floating gates to maintain a given charge decreases, thus the amount of charge that escapes increases. This changes the readout current from the floating gate significantly.

The defect map230may include a defect state of each block/page of the cells of the memory214. The defect memory232may be incorporated in the memory processing module200, incorporated in another module, or be a separate memory device. For each block of cell of the memory214, the defect map230may include the following entries, a block identification (ID), a block defect state, and one or more statistical parameter values associated with that block including variance values, SNR values, standard deviation values, etc.

The defect detection module210may include a slicer250. The slicer250may be used to compare a distribution magnitude value for a point between Gaussian distributions with a threshold. For example, the distribution magnitude in the middle of overlapped Gaussian distributions may be compared with a predetermined value to detect a defect.

The defect detection module210may handle defects based on any level of a hierarchy of a memory. A complexity, performance and memory capacity trade off exists when selecting a level of a memory hierarchy for the basis of defect handling. Complexity refers to the handling of defective and non-defective memory blocks and is associated with the size and number of the stated blocks. Performance refers to the speed in performing such handling. Memory capacity refers to the overall available storage space of a device after accounting for bad memory blocks. During defect handling, bad memory blocks are identified and subsequently no longer used. Thus, by selecting a high level of a memory hierarchy as a basis for defect handling complexity and memory capacity are substantially decreased whereas performance is increased. The larger the block of memory the higher the associated level of a memory hierarchy. On the other hand, when a low level of a memory hierarchy is selected complexity and memory capacity are minimally decreased whereas performance is decreased.

The defect detection module210may also provide early indications that a page or block of memory has potential defects or is experiencing degradation. The indications may be stored in the defect memory232. The indications may provide a current level of degradation and/or an estimate of remaining life expectancy. This allows for replacement planning of the memory214and/or planned nonuse of one or more blocks of the memory.

In one embodiment, and in association with a non-volatile semiconductor memory such as flash memory, when a block of memory is identified as defective, data recovered from that block is stored in another block. The recovered data may be stored in another block in the same or in a different memory. Future access to the defective block for read, write and erase tasks is prevented. In another related embodiment, and also in association with a non-volatile semiconductor memory such as flash memory, when a block of memory is identified as defective, the current block may be identified as average or as a read only block. Future write and erase tasks with respect to the defective block are prevented. Write and erase tasks can degrade a block of memory quicker than and/or in a more noticeable manner than read tasks.

The defect detection module210may also determine defective memory blocks based on dynamic parameters and thresholds. A dynamic parameter may refer to an ambient temperature, a memory system temperature, a current number of read and write cycles, an average estimate of SNR, etc. A dynamic threshold may refer to an ambient temperature threshold, a memory system temperature threshold, a maximum number of read and write cycles, an average number of read and write cycles of a block associated with a level of degradation, an average estimate of SNR, etc. The dynamic parameters and thresholds may be stored in the defect memory or in other memories, storage devices and/or modules disclosed herein. The temperature values may be determined via a temperature module252. The temperature module252may include or perform as one or more temperature sensors254.

In one embodiment, to simplify processing, the defect detection module210detects defects based on a number of symbol errors associated with the pilot data and/or the user data. When the number of symbol errors exceeds a predetermined threshold, a defect is detected. When associated with the pilot data, a pilot error counter260may be used to count differences between pilot data signals and predetermined pilot information. When associated with user data, a user data error counter262may be used. The value of the user data error counter262may be provided based on decoding performed by the signal processing module208. The signal processing module208generates recovered user data based on the user data signals, the first parameter values and/or the second parameter values.

Referring now toFIG. 9, a functional block diagram illustrating an exemplary defect handling module300is shown. The defect handling module300includes a demultiplexer302, a parameter estimation module303with an acquisition path304and a tracking path306, a signal processing module308and a defect detection module310. A read module312accesses and reads data from a memory314. The data is provided to the demultiplexer302, which divides the data into parallel paths, the acquisition path304and the tracking path306. The demultiplexer302generates pilot signals and user data signals based on the data read from the memory314. The pilot signals are provided to the acquisition path304and the user data signals are provided to the tracking path306.

The acquisition path304includes a pilot cell signal buffer316and an acquisition module318. The pilot cell signal buffer316stores the pilot cell signals. The acquisition module318generates rough estimates of statistical parameter values associated with the pilot signals. In one embodiment, the acquisition module318generates a first estimate of SNR for the pilot signals. The pilot signals are compared with predetermined pilot information.

The first LMS technique may be used to generate the first SNR estimate, as described with respect to the embodiment ofFIG. 6. The first LMS technique may be a high-speed high-bandwidth technique. The standard deviation σ and the SNR estimate may be determined via Equations 1, 2 and 3.

Output parameter estimates generated by the acquisition module318may be provided to the tracking path and/or the signal processing module308. When provided to the tracking path306for further refinement of the parameters.

The tracking path306includes a user data signal buffer320and a tracking module322. The user data signal buffer320receives and stores the user data signals. The tracking module322generates a second estimate of statistical parameter values, such as a second SNR estimate, associated with the user data signals.

The second LMS technique may be used to generate the second SNR estimate, as described with respect to the embodiment ofFIG. 6. The second LMS technique may be a low-speed low-bandwidth technique. The second LMS technique may be performed based on output estimates from the first LMS technique and through use of equations 6, 7 and 8.

The defect detection module310detects defects in blocks of the memory314based on the pilot signals and predetermined pilot information. The defect detection module310may perform similar tasks as the defect detection module210ofFIG. 8. The defect detection module310, however, operates based on pilot data not user data.

The defect detection module310may also provide early indications that a page or block of memory has potential defects or is experiencing degradation. The indications may provide a current level of degradation and/or an estimate of remaining life expectancy. Recovered user data may be stored in different memory blocks based on detected defects. Different defect identifications may be associated with monitored blocks of the memory. Future use of the blocks may be limited based on the associated defective states.

The defect detection module310compares the pilot signals to the predetermined pilot information to count the number of errors in the pilot signals. The number of errors, the above-stated indications and identifications, and/or other parameters may be stored in a defect map330of a defect memory332. The information stored in the defect memory332may be available to the write and read modules, such as the read module312and a write module334, a main control module336, or other modules of a memory system.

The defect map330may include a defect state of each block of the cells of the memory314. The defect memory332may be incorporated in the memory control module300, incorporated in another module, or be a separate memory device. For each block of cell of the memory314, the defect map330may include the following entries, a block identification (ID), a block defect state, a number of errors associated with that block, etc.

The defect detection module310may include a slicer340. The slicer340may be used to compare a distribution magnitude value for a point between Gaussian distributions with a threshold. When a number of pilot errors associated with a block of cells exceeds a threshold, precautious measures may be taken, some of which are described herein.

The defect detection module310may also determine defective memory blocks based on dynamic parameters and thresholds. The dynamic parameters may include ambient temperature, memory system temperature, a current number of read and write cycles, etc. The dynamic thresholds may include an ambient temperature threshold, a memory system temperature threshold, a maximum number of read and write cycles, an average number of read and write cycles of a block associated with a level of degradation, etc. The dynamic parameters and thresholds may be stored in the defect memory332and/or one of the memories, storage devices and/or modules disclosed herein. The temperature values may be determined via a temperature module350, which may perform as or include one or more temperature sensors352.

In one embodiment, to simplify processing, the defect detection module310detects defects based on a number of symbol errors associated with the pilot data. When the number of symbol errors exceeds a predetermined threshold, a defect is detected. A pilot error counter360may be used to count differences between pilot data signals and predetermined pilot information.

The signal processing module308generates recovered user data based on the user data signals, the first parameter values and/or the second parameter values from the acquisition and tracking modules318,322.

Referring now toFIG. 10, a functional block diagram of write path modules400is shown. The write path modules400include a write path signal processing module402, a pilot generator404, a multiplexer406, and a write module408. The write path signal processing module402and the pilot generator404are in communication with a main control module410. The main control module410generates pilot data when the user data is received and written to a memory412. This assures that the condition of the pilot cells of the memory412is representative of user data cells of the memory412.

The write path signal processing module402may have an ECC encoder module420that encodes an overhead portion of the memory412. The ECC encoder module420may include a cyclic redundancy (CRC) module422that generates CRC bits based on user data. The ECC encoder module420may include other encoding modules. For example, a Reed Solomon encoder module424of the ECC encoder module420may perform Reed Solomon encoding based on CRC module signals. A Bose-Chaudhuri-Hocquenghem (BCH)/LDPC encoder module426of the ECC encoder module420may perform either BCH or LDPC encoding based on Reed Solomon encoder module signals. Various other encoding modules may also be used.

The pilot generator404may include a generator module430, a format module432and a selector module434. The generator module430selectively generates pilot data. The format module432that may set cell locations in the memory412for the pilot data. The format module432may set locations for pilot data at a start, middle, and/or end of a physical page and/or a logical page. The format module432may also set locations for pilot data according to a predetermined pattern. The selector module434selects one of a plurality of sequences of pulse amplitude modulated (PAM) levels for writing to pilot cells. The selector module434may randomly select a sequence or may alternate between sequences.

The multiplexer406receives and selectively combines the encoded user data from the ECC encoder module420and the pilot data. The combination may be based on the aforementioned sequences and PAM operations. The multiplexer406selectively outputs the combined pilot and user data in a data stream to the write module408that stores the data in the memory412.

For example only, during write operations, the selector module434may select from two or more sequences for a first write operation. The two sequences may be referred to as sequence A and sequence B. The sequences may have predefined lengths or alternatively may have lengths that are based on the number of pilot cells that will be written to for a particular page or block of the memory12. The selector module434alternates between sequences A and B in subsequent write operations. Write operations may include writing to one or more cells of the memory412.

In other words, for a first write operation, sequence A may be selected to write multiple cells of the memory412. For a second write operation, sequence B may be selected to write to multiple cells (that may or may not be the same cells as those written to using sequence A). The selector module434may make subsequent selections of sequences based on complete or partial write operations to groups of memory cells. The selector module434need not complete sequence A before selecting sequence B.

The multiplexer406combines pilot data and user data (encoded data stream) to be written to the memory412. The combination may be based on the selected sequence and may fix positions of the pilot data for each logical page.

In flash memory, different cell levels may have correspondingly different voltage characteristics. The first and last cell levels may have substantially different voltage characteristics, whereas intermediate levels may have relatively similar voltage characteristics. For example, an 8 level cell may include levels 0-7. The lowest level (level 0) and highest level (level 7) may have unique characteristics while levels 1-6 may have similar characteristics.

The selector module434may select sequences that instruct write operations to write to as few levels as possible. The selector module434may therefore select a sequences that includes writing to level 0 and level 7 and two of the intermediate levels (for example levels 2 and 5). Voltage characteristics of the unselected levels (levels 1, 3, 4, 6) may be determined via interpolation and based on levels 2 and 5 because levels 1-6 have similar voltage characteristics. The selector module434sequences may therefore select 4 levels that may provide write/read-back characteristics of an entire cell or group of cells regardless of the number of possible levels. However, the present disclosure is not limited to 4 levels, and any or all levels may be used.

The following paragraph indicates 4 exemplary levels used for 8PAM signaling, 12PAM signaling, and 16PAM signaling (non-normalized) signaling. For 8PAM, the selector module434selects a sequence that includes signal levels 0, 1, 4, and 7. For 12PAM, the selector module434selects a sequence that includes signal levels 0, 1, 6 and 11. For 16PAM, the selector module434selects a sequence that includes signal levels 0, 1, 8 and 15. For 32PAM, the selector module434selects a sequence that includes pilot levels 0, 1, 16 and 31.

The selector module434may select from exemplary sequences A and B. A read path may determine whether sequence A or B is used based on the levels of the first 3 pilot cells that have been written to and are detected.

For sequence A, level 0 is written to for the first 3 pilot cells, while for Scheme B, the highest level may be written for the first 3 pilot cells. The highest level may be 7 for 8PAM, 11 for 12PAM and 15 for 16PAM, respectively. Subsequent pilot levels of sequence A are used in a cyclical pattern that includes the four levels selected. Subsequent pilot levels of sequence B may be a cyclical shift of the pilot levels of sequence A. For example, for 8PAM signaling, sequence A: 0 0 0 1 4 7 0 1 4 7 0 1 4 7 . . . , and sequence B: 7 7 7 4 1 0 7 4 1 0 7 4 1 0 . . . . Sequences A and B are not required to be cyclically shifted but may merely differ in other ways. Sequences A and B are selected so that the read module can easily distinguish between them. In the above example, the read module may do a majority of the decoding on the first three cells to decide whether the pilot sequence A or B is used. Therefore, the write module does not need to explicitly tell the read module which sequence is used.

The format module432may set locations for the pilot data that do not depend on the PAM for the memory cells. Alternatively, the multiplexer module141may insert pilot data into user data as a function of the PAM of the memory cells. For example, there may be 512 cells in for pilot data per sector of size 33 KB. Thus, for each physical page of 2 KB+64B, 32 cells are allocated for pilot data. In the following, the frequency of pilot cells appearing in the flash memory device is computed for 8PAM, 12PAM, 16PAM and 32PAM.

For 8PAM signaling, there may be 5632 cells per physical page. Therefore, every 176 cells may contain one pilot cell. Every 176*3=528 bits may contain 3 pilot bits. For 12PAM signaling, there may be 2414 cell-pairs/physical page. Therefore, every 150 cell-pairs may contain one pair of pilot cells. Every 150*7=1050 bits may contain 7 pilot bits. For 16PAM signaling, there may be 4224 cells per page. Every 132 cells may contain one pilot cell. Every 132*4=528 bits may therefore contain 4 pilot bits. For 32PAM signaling, there may be 3380 cells per page. Every 105 cells may contain one pilot cell. Every 105*5=605 bits may therefore contain 5 pilot bits.

Referring now also toFIG. 11is a functional block diagram of read path modules500is shown. The read path modules500include a read module502, a demultiplexer504, a parameter estimation module506, a signal processing module508, and a pilot buff/generator510. The read module502, the parameter estimation module506and the pilot generator510are in communication with a main control module512. The main control module512signals the pilot generator510to read pilot data when user data is read from a memory514. This further assures that the condition of the pilot cells is representative of the user data cells.

The read module502reads user data and pilot data from the memory514. The demultiplexer module204receives and demultiplexes the user data and pilot signals. A pilot cell signal buffer520receives pilot signals and a user data signal buffer522receives user data signals. An acquisition module524receives an output of the pilot cell signal buffer520. A tracking module526may receive output of the user data signal buffer522and output of the acquisition module524. The outputs of the parameter estimation modules520-526may be provided to an ECC decoder module530of the signal processing module508.

An ECC decoder module530decodes the read-back signals that were partially encoded by the ECC encoder module420. The ECC decoder module530may include a log-likelihood ratio (LLR) computation module532, a LDPC module534, a Gray Code decoder module536, and a BCH decoder module538. Outputs of the parameter estimation modules520-526may be provided to the LLR computation module532and/or the gray code decoder module536. The LDPC decoder module534may receive LLR output data from the LLR computation module532. The BCH decoder538may receive LDPC outputs from the LDPC decoder module534and/or binary outputs from the Gray code decoder module536. Finally, the outputs of the LDPC decoder module534and/or the BCH decoder module538may further be decoded by a Reed-Solomon decoder and subsequently checked by a CRC decoder to provide recovered user data.

The read path modules500may read back data from the memory514in analog or binary form as an analog or binary signal. If the signal is binary, the demultiplexer504demultiplexes the pilot bits from the input user data, and the user data is directly sent to the Gray code decoder module536. When the signal is analog, the user data and pilot data are processed with adaptive signal processing algorithms.

When data is LDPC coded, the output from the tracking module526in combination with the original user data are used by the LLR computation module532to calculate log-likelihood ratios. Otherwise, the Gray code decoder module536translates the output from the tracking module526into coded binary bits for the BCH decoder538.

Referring now toFIG. 12, a flow diagram illustrating a method of operating a memory processing module is shown. Although the following steps are described primarily with respect to the embodiment ofFIGS. 2 and 6, the steps may be applied to other embodiments of the present disclosure.

In step600, a command signal is generated to read user data from a block of a memory. In step602, a read pilot signal is generated based on the command signal. In step604, pilot data and user data is read from the block. The pilot data and the user data may be provided to a demultiplexer, such as by one of the demultiplexers disclosed herein, as a read signal.

In step606, pilot data signals and user data signals are generated based on the read signal. In step608, the pilot signals are stored in a pilot cell signal buffer, such as one of the pilot cells signal buffers disclosed herein. The user data signals are stored in a user data signal buffer, such as one of the user data signal buffers disclosed herein.

In step610, the pilot signals and corresponding pilot information is provided to an acquisition module. The acquisition module generates one or more statistical parameter values based on the pilot signals and the pilot information. This may be referred to as a first set of parameter values. The first set of parameter values may be rough estimate values.

When applied to a low latency application, the first set of parameter values are provided to the tracking module. When applied to a latency insensitive application, the first set of parameter values is provided to a signal processing module.

In step614, the signal processing module generates recovered user data based on the second set of parameter values and the user data signals. Alternatively, the signal processing module generates recovered user data based on the first set of parameter values and the user data signals.

Referring now toFIG. 13, a flow diagram illustrating a method of operating a memory processing a defect handling module is shown. Although the following steps are described primarily with respect to the embodiment ofFIGS. 7-9, the steps may be applied to other embodiments of the present disclosure.

In step650, a command signal is generated to read user data from a block of a memory. In step652, a read pilot signal is generated based on the command signal. In step654, pilot data and user data is read from the block. The pilot data and the user data may be provided to a demultiplexer, such as by one of the demultiplexers disclosed herein, as a read signal.

In step656, pilot data signals and user data signals are generated based on the read signal. In step658, the pilot signals are stored in a pilot cell signal buffer, such as one of the pilot cells signal buffers disclosed herein. The user data signals are stored on a user data signal buffer, such as one of the user data signal buffers disclosed herein.

In step660, the pilot signals and corresponding pilot information is provided to an acquisition module. The acquisition module generates one or more statistical parameter values based on the pilot signals and the pilot information. This may be referred to as a first set of parameter values. The first set of parameter values may be rough estimate values.

In step662, a defect detection module may detect one or more defects in the block based on the first set of parameter values, the pilot signal values, and/or predetermined pilot information. The defects may be detected based on additional dynamic parameter values, such as those described herein.

In step664, the defect detection module may update defect state of the block and corresponding cells in a defect memory, as well as store the first set of parameter values.

When applied to a low latency application, the first set of parameter values are provided to the tracking module. When applied to a latency insensitive application, the first set of parameter values is provided to a signal processing module

In step668, the signal processing module generates recovered user data based on the second set of parameter values and the user data signals. Alternatively, the signal processing module generates recovered user data based on the first set of parameter values and the user data signals.

In step670, a defect detection module may detect one or more defects in the block based on the first and/or second set of parameter values. The defects may be detected based on additional dynamic parameter values, such as those described herein.

In step672, the defect detection module may update defect state of the block and corresponding cells in the defect memory, as well as store the first and second set of parameter values.

The above-described steps ofFIGS. 12 and 13are meant to be illustrative examples; the steps may be performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application.

Referring now toFIGS. 14A-14G, various exemplary implementations incorporating the teachings of the present disclosure are shown.

Referring now toFIG. 14A, the teachings of the disclosure can be implemented in or in association with non-volatile memory912of a hard disk drive (HDD)900. The HDD900includes a hard disk assembly (HDA)901and an HDD printed circuit board (PCB)902. The HDA901may include a magnetic medium903, such as one or more platters that store data, and a read/write device904. The read/write device904may be arranged on an actuator arm905and may read and write data on the magnetic medium903. Additionally, the HDA901includes a spindle motor906that rotates the magnetic medium903and a voice-coil motor (VCM)907that actuates the actuator arm905. A preamplifier device908amplifies signals generated by the read/write device904during read operations and provides signals to the read/write device904during write operations.

The HDD PCB902includes a read/write channel module (hereinafter, “read channel”)909, a hard disk control module (HDC) module910, a buffer911, non-volatile memory912, a processor913, and a spindle/VCM driver module914. The read channel909processes data received from and transmitted to the preamplifier device908. The HDC module910controls components of the HDA901and communicates with an external device (not shown) via an I/O interface915. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface915may include wireline and/or wireless communication links.

The HDC module910may receive data from the HDA901, the read channel909, the buffer911, non-volatile memory912, the processor913, the spindle/VCM driver module914, and/or the I/O interface915. The processor913may process the data, including encoding, decoding, filtering, and/or formatting. The processed data may be output to the HDA901, the read channel909, the buffer911, non-volatile memory912, the processor913, the spindle/VCM driver module914, and/or the I/O interface915.

The HDC module910may use the buffer911and/or non-volatile memory912to store data related to the control and operation of the HDD900. The buffer911may include DRAM, SDRAM, etc. Nonvolatile memory912may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The spindle/VCM driver module914controls the spindle motor906and the VCM907. The HDD PCB902includes a power supply916that provides power to the components of the HDD900.

Referring now toFIG. 14B, the teachings of the disclosure can be implemented in or in association with non-volatile memory923of a DVD drive918or of a CD drive (not shown). The DVD drive918includes a DVD PCB919and a DVD assembly (DVDA)920. The DVD PCB919includes a DVD control module921, a buffer922, non-volatile memory923, a processor924, a spindle/FM (feed motor) driver module925, an analog front-end module926, a write strategy module927, and a DSP module928.

The DVD control module921controls components of the DVDA920and communicates with an external device (not shown) via an I/O interface929. The external device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface929may include wireline and/or wireless communication links.

The DVD control module921may receive data from the buffer922, non-volatile memory923, the processor924, the spindle/FM driver module925, the analog front-end module926, the write strategy module927, the DSP module928, and/or the I/O interface929. The processor924may process the data, including encoding, decoding, filtering, and/or formatting. The DSP module928performs signal processing, such as video and/or audio coding/decoding. The processed data may be output to the buffer922, non-volatile memory923, the processor924, the spindle/FM driver module925, the analog front-end module926, the write strategy module927, the DSP module928, and/or the I/O interface929.

The DVD control module921may use the buffer922and/or non-volatile memory923to store data related to the control and operation of the DVD drive918. The buffer922may include DRAM, SDRAM, etc. Nonvolatile memory923may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The DVD PCB919includes a power supply930that provides power to the components of the DVD drive918.

The DVDA920may include a preamplifier device931, a laser driver932, and an optical device933, which may be an optical read/write (ORW) device or an optical read-only (OR) device. A spindle motor934rotates an optical storage medium935, and a feed motor936actuates the optical device933relative to the optical storage medium935.

When reading data from the optical storage medium935, the laser driver provides a read power to the optical device933. The optical device933detects data from the optical storage medium935, and transmits the data to the preamplifier device931. The analog front-end module926receives data from the preamplifier device931and performs such functions as filtering and A/D conversion. To write to the optical storage medium935, the write strategy module927transmits power level and timing data to the laser driver932. The laser driver932controls the optical device933to write data to the optical storage medium935.

Referring now toFIG. 14C, the teachings of the disclosure can be implemented in or in association with memory941of a high definition television (HDTV)937. The HDTV937includes an HDTV control module938, a display939, a power supply940, memory941, a storage device942, a network interface943, and an external interface945. If the network interface943includes a wireless local area network interface, an antenna (not shown) may be included.

The HDTV937can receive input signals from the network interface943and/or the external interface945, which can send and receive data via cable, broadband Internet, and/or satellite. The HDTV control module938may process the input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of the display939, memory941, the storage device942, the network interface943, and the external interface945.

Memory941may include random access memory (RAM) and/or non-volatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device942may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The HDTV control module938communicates externally via the network interface943and/or the external interface945. The power supply940provides power to the components of the HDTV937.

Referring now toFIG. 14D, the teachings of the disclosure may be implemented in or in association with memory949of a vehicle946. The vehicle946may include a vehicle control system947, a power supply948, memory949, a storage device950, and a network interface952. If the network interface952includes a wireless local area network interface, an antenna (not shown) may be included. The vehicle control system947may be a powertrain control system, a body control system, an entertainment control system, an anti-lock braking system (ABS), a navigation system, a telematics system, a lane departure system, an adaptive cruise control system, etc.

The vehicle control system947may communicate with one or more sensors954and generate one or more output signals956. The sensors954may include temperature sensors, acceleration sensors, pressure sensors, rotational sensors, airflow sensors, etc. The output signals956may control engine operating parameters, transmission operating parameters, suspension parameters, etc.

The power supply948provides power to the components of the vehicle946. The vehicle control system947may store data in memory949and/or the storage device950. Memory949may include random access memory (RAM) and/or non-volatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device950may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The vehicle control system947may communicate externally using the network interface952.

Referring now toFIG. 14E, the teachings of the disclosure can be implemented in or in association with memory964of a cellular phone958. The cellular phone958includes a phone control module960, a power supply962, memory964, a storage device966, and a cellular network interface967. The cellular phone958may include a network interface968, a microphone970, an audio output972such as a speaker and/or output jack, a display974, and a user input device976such as a keypad and/or pointing device. If the network interface968includes a wireless local area network interface, an antenna (not shown) may be included.

The phone control module960may receive input signals from the cellular network interface967, the network interface968, the microphone970, and/or the user input device976. The phone control module960may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may be communicated to one or more of memory964, the storage device966, the cellular network interface967, the network interface968, and the audio output972.

Memory964may include random access memory (RAM) and/or non-volatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device966may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The power supply962provides power to the components of the cellular phone958.

Referring now toFIG. 14F, the teachings of the disclosure can be implemented in or in association with memory983of a set top box978. The set top box978includes a set top control module980, a display981, a power supply982, memory983, a storage device984, and a network interface985. If the network interface985includes a wireless local area network interface, an antenna (not shown) may be included.

The set top control module980may receive input signals from the network interface985and an external interface987, which can send and receive data via cable, broadband Internet, and/or satellite. The set top control module980may process signals, including encoding, decoding, filtering, and/or formatting, and generate output signals. The output signals may include audio and/or video signals in standard and/or high definition formats. The output signals may be communicated to the network interface985and/or to the display981. The display981may include a television, a projector, and/or a monitor.

The power supply982provides power to the components of the set top box978. Memory983may include random access memory (RAM) and/or non-volatile memory. Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device984may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD).

Referring now toFIG. 14G, the teachings of the disclosure can be implemented in or in association with memory992of a mobile device989. The mobile device989may include a mobile device control module990, a power supply991, memory992, a storage device993, a network interface994, and an external interface999. If the network interface994includes a wireless local area network interface, an antenna (not shown) may be included.

The mobile device control module990may receive input signals from the network interface994and/or the external interface999. The external interface999may include USB, infrared, and/or Ethernet. The input signals may include compressed audio and/or video, and may be compliant with the MP3 format. Additionally, the mobile device control module990may receive input from a user input996such as a keypad, touchpad, or individual buttons. The mobile device control module990may process input signals, including encoding, decoding, filtering, and/or formatting, and generate output signals.

The mobile device control module990may output audio signals to an audio output997and video signals to a display998. The audio output997may include a speaker and/or an output jack. The display998may present a graphical user interface, which may include menus, icons, etc. The power supply991provides power to the components of the mobile device989. Memory992may include random access memory (RAM) and/or non-volatile memory.

Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states. The storage device993may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD). The mobile device may include a personal digital assistant, a media player, a laptop computer, a gaming console, or other mobile computing device.

The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims.