Signal amplification apparatus and signal amplification method

A signal amplification apparatus which supplies an input signal to a signal processing section to perform signal processing on the input signal, amplifies a power supply voltage supplied from a power source section in accordance with the processed signal, and outputs the amplified power supply voltage. The apparatus includes output decrease prediction means for predicting decrease of the output signal on the basis of an amplitude of the input signal; power supply voltage correction signal generation means for generating a power supply voltage correction signal for correcting the power supply voltage of the power source section on the basis of the predicted decrease of the output signal; and feedforward control means for performing feedforward control of the power supply voltage of the power source section by using the power supply voltage correction signal.

CROSS REFERENCES TO RELATED APPLICATIONS

The present document contains subject matter related to Japanese Patent Application JP 2005-214680 filed in the Japanese Patent Office on Jul. 25, 2005, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to, for example, a signal processing apparatus and method for performing signal processing on an input signal, amplifying a power supply voltage in accordance with the processed signal, and outputting the amplified power supply voltage as an output signal.

2. Description of Related Art

FIG. 14is a block diagram of a related art digital amplifier system. InFIG. 14, an amplifier signal processing block141performs predetermined signal processing on an amplifier input signal145, and a delay device2delays the processed signal by the amount of delay occurring in the digital amplifier system, in order to adjust the output timing of an amplifier power block143. Then, a power source block144outputs a constant power supply voltage to the amplifier power block143under feedback control147, and the amplifier power block143amplifies the power supply voltage in accordance with the level of the delayed signal and outputs an amplifier output signal146.

The amplifier power block143of the digital amplifier system cuts out the power supply voltage supplied from the power source block144by means of the switching operation of its power MOS (metal oxide semiconductor). The voltage cut out by the power MOS is desirably a stable constant voltage, and if a voltage variation occurs, the voltage variation directly influences an audio output signal such as the amplifier output signal13and produces distortion of the audio output signal. In general, to suppress the voltage variation, the output of the power source block144is fed back (as indicated at147) to the power source block144itself so as to suppress a variation of the output voltage.

FIGS. 12A to 12Care graphs showing waveform distortions due to a power supply voltage variation, andFIG. 12Ashows a voltage applied to the power MOS (after correction),FIG. 1-2Bshows an ideal switching pulse of the power MOS, andFIG. 13Cshows a switching pulse of the power MOS during the power supply voltage variation.

If the level of the signal delayed by the delay device142increases and a lowering variation occurs in the power supply voltage supplied from the power source block144, the voltage applied to the power MOS shown inFIG. 14A(before correction) lowers from a constant voltage by the amount of the variation of the power supply voltage. As a result, the power MOS switching pulse during the power supply voltage variation shown inFIG. 12Clowers by the amount of the variation of the power supply voltage compared to the ideal power MOS switching pulse shown inFIG. 12B.

An audio switching power source has been proposed which is constructed to determine a pulse modulated signal for determining a direct-current output value of an AC-DC conversion section by means of a pulse control section on the bias of the amplitude value of a sequentially inputted digital input signal, the audio switching power source being operative to correct the direct current output voltage at the same timing as an increase of the amplitude of the digital input signal by outputting an audio signal which is power-amplified by a digital power amplification section after having delaying the digital input signal (refer to Japanese Patent Application Publication Laid-Open Number Hei 9-148851).

A power supply circuit for a power amplifier has also been proposed which varies a power supply voltage to be supplied to a power amplification device of the power amplifier, in accordance with the envelope of a signal level based on an input signal (refer to Japanese Patent Application Publication Laid-Open Number Sho 57-11507). Furthermore, a multi-signal amplifier is known which varies a bias voltage to be supplied to a power amplification circuit, in accordance with the number of input signals (refer to Japanese Patent Application Publication Laid-Open Number Hei 3-250805). In addition, a solid-state power amplifier has also heretofore been known which detects an input and an output and performs dynamic adjustment of an operation point for dynamically adjusting a direct-current bias to be supplied to the amplifier (refer to Japanese Patent Application Publication Laid-Open Number Hei 4-262608).

SUMMARY OF THE INVENTION

However, in a case where the power source block144of feedback control architecture is used as a power source of a digital amplifier, none of the above-mentioned related art power source apparatuses can follow a voltage variation due to the amplifier power block143, so that a distortion due to a power supply voltage variation occurs.

In addition, any of the arts described in the above patent documents is constructed to detect a signal level during a constant period and perform switching of the power source by using the pulse width, in order to supplying power according to the signal level. Accordingly, even with these arts, it is difficult to follow a power variation due to a load variation in real time, so that there is the disadvantage that a distortion due to the power supply voltage variation occurs.

The present invention, therefore, provides a signal amplification apparatus and a signal amplification method both of which can correct the distortion of an output signal by predicting a voltage variation of a power source and causing the output signal to follow the voltage variation in real time.

To solve the above-mentioned problems, in accordance with an embodiment of the present invention, there is provided a signal amplification apparatus which supplies an input signal to a signal processing section to perform signal processing on the input signal, amplifies a power supply voltage supplied from a power source section in accordance with the processed signal, and outputs the amplified power supply voltage. The signal simplification apparatus includes output decrease prediction means, power supply voltage correction signal generation means, and feedforward control means. The output decrease prediction means predicts a decrease of the output signal on the basis of amplitude of the input signal. The power supply voltage correction signal generation means generates a power supply voltage correction signal for correcting the power supply voltage of the power source section on the bias of the predicted lowering of the output signal. The feedforward control means performs feedforward control of the power supply voltage of the power source section by using the power supply voltage correction signal.

According to the embodiment, for example, in a signal processing section of a digital amplifier, the input signals on all the channels are added together and the result is used for the feedforward control of the power source section so as to suppress a power supply voltage variation, thereby suppressing distortion of an audio output signal due to the power supply voltage variation. The embodiment of the present invention can also be applied to a digital amplifier of analog input architecture having an analog-to-digital converter at the front stage of its signal processing section.

Since the power supply voltage variation depends on the sum of the output signal levels of all the channels, the feedforward signal to be applied to the power source section is calculated by adding the input signals on all the channels. It is noted that the feedforward signal differs according to whether the power source section has single-ended architecture or bridge tied load (BTL) architecture. In the case of the single-ended architecture, the generation of the feedforward signal is realized by simple adding processing of the input signal levels and sign inversion processing as well as an amplifier for adjusting gain.

In addition, a delay circuit may be added to each of the signal processing section output of the digital amplifier and the feedforward output to the power source section in order to synchronize the correction of a voltage variation of the power source section by the feedforward signal and the timing of signal output.

According to the embodiment of the present invention, it is possible to cause the output signal to follow the power supply voltage variation in real time by predicting the power supply voltage variation, generating the feedforward signal corresponding to the voltage variation, and performing feedforward control on the power source section.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described below with reference to the accompanying drawings.FIG. 1is a block diagram of a digital amplifier system according to an embodiment of the present invention.

InFIG. 1, an amplifier signal processing block1performs predetermined signal processing on an amplifier input signal11, and a delay device2causes the signal processed by the amplifier signal processing block1to delay by the amount of delay occurring in the digital amplifier system, in order to adjust the output timing of an amplifier power block3. Then, a power source block5outputs a constant power supply voltage to the amplifier power block3under feedback control14, and the amplifier power block3amplifies the power supply voltage in accordance with the level of the delayed signal and outputs an amplifier output signal13. This construction is similar to a related art shown inFIG. 14.

In this construction, the amplifier power block3of the digital amplifier system cuts out the power supply voltage supplied from the power source block5by means of the switching operation of its power MOS on the basis of a pulse obtained by integrating the signal delayed by the delay device2. The voltage cut out by the power MOS is desirably a stable constant voltage. This is because if a voltage variation occurs, the voltage variation directly influences an audio output signal such as the amplifier output signal13and produces distortion of the audio output signal.

For this reason, the digital amplifier system according to the embodiment of the present invention is provided with a feedforward signal generation section4. The feedforward signal generation section4calculates by addition the all channel amplifier input signal11inputted to the amplifier signal processing block1, and predicts a lowering of the amplifier output signal13on the basis of an amplitude variation of the amplifier input signal11. Namely, the prediction of the output decreasing of the amplifier output signal13is performed by predicting the time for which and the level to which the amplifier output signal13decreases in accordance with the time for which and the amplitude level at which the amplifier input signal11takes place.

The feedforward signal generation section4generates a power supply voltage correction signal12for correcting the predicted decrease of the amplifier output signal13, and supplies the power supply voltage correction signal12to the power source block5. The power supply voltage correction signal12is used for power supply voltage feedforward control in order to correct the power supply voltage of the power source block5.

In this manner, the feedforward signal generation section4can suppress the distortion of the amplifier output signal13due to the power supply voltage variation by restraining the power supply voltage variation by using the power supply voltage correction signal12for the feedforward control of the power source block5.

In general, digital amplifiers are in almost all cases used in applications which need to amplify and output signals on a plurality of channels. In the following description, by way of example, reference will be made to a specific embodiment applied to audio signals on three channels which are the left or L channel, the right or R channel and the center or C channel.

FIG. 2is a block diagram of a digital amplifier system for three channels, for example. Referring toFIG. 2, amplifier signal processing blocks21-1,21-2and21-3respectively perform predetermined signal processing on the amplifier input signals11on the first channel, the second channel and the third channel, and supply the respective processed signals to delay devices22-1,22-2and22-3. The respective delay devices22-1,22-2and22-3cause the processed signals on the first, second and third channels to delay by the amount of delay occurring in the digital amplifier system, in order to adjust the output timing of the amplifier power blocks23-1,23-2and23-3.

Meanwhile, a power source block25outputs a constant power supply voltage to each of amplifier power blocks23-1,23-2and23-3under the feedback control14. The respective amplifier power blocks23-1,23-2and23-3receive the output signals from the power source block25and amplify the supplied power supply voltages in accordance with the levels of the signals on the first, second and third channels delayed by the delay devices22-1,22-2and22-3, and output the amplifier output signals13on the first, second and third channels.

In this digital amplifier system, the respective amplifier power blocks23-1,23-2and23-3cut out the power supply voltages supplied from the power source block25by means of the switching operation of their power MOSs on the basis of pulses obtained by integrating the signals on the first, second and third channels after having been delayed by the delay devices22-1,22-2and22-3. As mentioned previously with reference to the block diagram ofFIG. 1, the power supply voltage cut out by each of the amplifier power blocks23-1,23-2and23-3is desirably a stable constant voltage. This is because if a voltage variation occurs in the power source block25, the voltage variation directly influences audio output signals such as the amplifier output signals13and produces distortion of the audio output signals.

For this reason, the3-channel digital amplifier system shown inFIG. 2is also provided with a feedforward signal generation section24. The feedforward signal generation section24adds together the amplifier input signals11on all of the first, second and third channels, which have been inputted to the respective amplifier signal processing blocks21-1,21-2and21-3, and predicts decreases of the respective amplifier output signals13on the basis of amplitude variations of the amplifier input signals11on all of the first, second and third channels.

The prediction of the output decreases of the amplifier output signals13is performed by predicting the times for which and the levels to which the amplifier output signals13on all of the first, second and third channels respectively lower in accordance with the times for which and the amplitude levels at which the amplifier input signals11on all of the first, second and third channels take place, respectively.

Similarly to the feedforward signal generation section4shown inFIG. 1, the feedforward signal generation section24generates the power supply voltage correction signal12for correcting the predicted decreases of the respective amplifier output signals13, and supplies the power supply voltage correction signal12to the power source block25. The power supply voltage correction signal12is used for power supply voltage feedforward control in order to correct the power supply voltage of the power source block25.

In this manner, the feedforward signal generation section24can suppress the distortions of the amplifier output signals13on all of the first, second and third channels due to the power supply voltage variation by restraining the power supply voltage variation by using the power supply voltage correction signal12for the feedforward control of the power source block25.

FIG. 3is a block diagram of a feedforward signal generation section for a power source block having bridge tied load (BTL) architecture. Referring toFIG. 3, since the power supply voltage variation depends on a full-load signal31which is the sum of the output signals on all of the first, second and third channels, the power supply voltage correction signal12which is a feedforward signal to be applied to the power source block25is obtained by adding together the input signals on all of the first, second and third channels at an adder32.

Decreases of the output levels of the amplifier output signals13are predicted from the signal obtained by the addition processing by the adder32. The decreases of the respective output levels are detected by predicting in real time the amplitude levels of the amplifier input signals11and the times for which level variations occur in the respective amplifier input signals11. The power supply voltage correction signal12which is the feedforward signal differs according to whether the power source block25has single-ended architecture or BTL architecture.

FIG. 5is a circuit diagram of an amplifier power block of BTL architecture. InFIG. 5, when pulses which respectively act to turn on an nMOS52and a pMOS56(pulses obtained by integrating a signal on each corresponding one of the channels) are inputted to their respective gates, a current based on a power supply voltage supplied from a power source51is amplified by flowing from the source to the drain of the nMOS52, and is acoustically outputted from a speaker58as one amplifier output signal waveform-shaped by a low-pass filter54. At this time, the other amplifier output signal flows to ground via a low-pass filter57and the pMOS56.

When pulses which respectively act to turn on an nMOS55and a pMOS53(pulses obtained by integrating signals on each corresponding one of the channels) are inputted to their respective gates, a current based on a power supply voltage supplied from the power source51is amplified by flowing from the source to the drain of the nMOS55, and is acoustically outputted from the speaker58as one amplifier output signal waveform-shaped by the low-pass filter57. At this time, the other amplifier output signal flows to ground via the low-pass filter54and the pMOS53.

Accordingly, in the amplifier power block of BTL architecture, since one amplifier output signal and the other amplifier output signal flow in the mutually opposite directions, it is necessary to acquire the absolute value of the full-load signal31which is calculated at the adder32by using an absolute value circuit33, in order to predict decreases of the respective signal levels of one amplifier output signal and the other amplifier output signal.

Then, the signal after the absolute value processing by the absolute value circuit33is sign-inverted by an inverter34, and this sign-inverted signal is amplified by a factor k into the power supply voltage correction signal12by means of an amplifier35. This factor k is selected to become a factor which acts to correct the predicted level decrease of the amplifier output signal13.

As mentioned above, in the case of BTL architecture, since the power supply voltage variation is approximately equal to a signal obtained by adding together the audio signals on all the channels and inverting the sign of only the signal having an amplitude on the plus side, the obtained signal is fed forward to the power source to predict a power supply voltage variation. The generation of the power supply voltage correction signal12which is to be the feedforward signal can be realized by simple mix processing and sign inversion processing as well as a multiplier for adjusting gain.

FIG. 4is a block diagram of a feedforward signal generation section for a power source block having single-ended architecture. InFIG. 4, since the power supply voltage variation depends on a full-load signal41which is the sum of the output signals on all of the first, second and third channels, the power supply voltage correction signal12which is to be a feedforward signal to be applied to the power source block25is obtained by adding together the input signals on all of the first, second and third channels at an adder42. The power source block25having single-ended architecture differs in construction from that having the above-mentioned BTL architecture shown inFIG. 3in signal processing which is performed after the adder42in order to generate the power supply voltage correction signal12.

An amplifier power block of single-ended architecture will be described below.FIG. 6is a circuit diagram of an amplifier power block of single-ended architecture. InFIG. 6, when a pulse obtained by integrating a signal on each corresponding one of the channels, which respectively act to turn on an nMOS62, is inputted to its gate, a current based on a power supply voltage supplied from a power source61is amplified by flowing from the source to the drain of the nMOS62, and is acoustically outputted from a speaker65as an amplifier output signal waveform-shaped by a low-pass filter64. When the amplifier output signal is not outputted from the speaker65, the amplifier output signal flows to ground via a pMOS63.

Accordingly, in the amplifier power block of single-ended architecture, since an amplifier output signal flows in one direction, it is not necessary to acquire the absolute value of the full-load signal41which is calculated at the adder42, in order to predict a decrease of the signal level of the amplifier output signal. At this time, a level decrease of the amplifier output signal13is predicted from the signal obtained by the addition processing by the adder42. The decreases of the amplifier output signals13are detected by predicting in real time the amplitude levels of the amplifier input signals11and the times for which amplitude variations occur in the respective amplifier input signals11.

Then, the signal after the addition is sign-inverted by an inverter43, and this sign-inverted signal is amplified by the factor k into the power supply voltage correction signal12by means of an amplifier44. Similarly to the factor k in the amplifier35shown inFIG. 3, the factor k is selected to become a factor which acts to correct the predicted level decrease of the amplifier output signal13.

As mentioned above, in the case of single-ended architecture, since the power supply voltage variation is approximately equal to a signal obtained by adding together the audio signals on all the channels, inverting the sign of the added signal, and multiplying the sing-inverted signal by a certain gain, the obtained signal is fed forward to the power source in advance. Accordingly, the generation of the power supply voltage correction signal12which is the feedforward signal can be realized merely by using simple mix processing and sign inversion processing as well as a multiplier for adjusting gain.

In addition, similarly to the feedforward signal generation section for the BTL architecture shown inFIG. 3, the feedforward signal generation section for the single-ended architecture may further have the absolute value circuit33for performing absolute value processing. In this case, the constructions of the feedforward signal generation sections24for both architectures may be standardized. In addition, since the gain of the feedforward signal to be applied to the power source block25needs to be selected to have an optimum value according to the output power of each individual amplifier to be used, the gain needs to be set to an optimum value during system design.

In addition, the delay devices22-1,22-2and22-3are respectively provided between the amplifier signal processing blocks21-1,21-2and21-3and the amplifier power blocks23-1,23-2and23-3in order to synchronizing the processing of correcting the voltage variation of the power source block25by using the power supply voltage correction signal12generated by the feedforward signal generation section24, with the output timing of the amplifier output signals13from the respective amplifier power blocks23-1,23-2and23-3. Since the delay time of each of the delay devices22-1,22-2and22-3is a constant value unique to the system, it is necessary to measure the delay of the system and set the delay time during system design.

The operation of the feedforward signal generation section24will be described below with reference to the flowchart shown inFIG. 7. InFIG. 7, first of all, a full-load signal is calculated by addition (step S1). Specifically, the full-load signal31which is the sum of the output signal on all of the first, second and third channels is calculated at the adder32.

Then, an output decrease due to amplitude is predicted (step S2). Specifically, a lowering of the output level of the amplifier output signal13is predicted from the added signal after the addition. The lowering of the output level of the amplifier output signal13is detected by predicting in real time the amplitude level of the amplifier input signal11and the time for which an amplitude variation occurs in the amplifier input signal11.

FIGS. 8A to 8Fare graphs showing a power supply voltage variation in the BTL architecture, that is, a waveform example 1 in which each channel has a different variation.FIG. 8Ashows a channel1speaker output,FIG. 8Bshows a channel2speaker output,FIG. 8Cshows a channel X speaker output, andFIG. 8Dshows an all channel added signal obtained by adding together the channel1speaker output, the channel2speaker output and the channel X speaker output.FIG. 8Fshows a signal obtained by predicting a decrease variation of a voltage applied to the power MOS from a voltage applied to the power MOS without a variation, shown inFIG. 8E, in the case of the added signal shown inFIG. 8D.

FIGS. 9A to 9Fare graphs showing a power supply voltage variation in the BTL architecture, that is, a waveform example 2 in which each channel has the same variation but differs in phase.FIG. 9Ashows a channel1speaker output,FIG. 9Bshows a channel2speaker output,FIG. 9Cshows a channel X speaker output, and FIG.9D shows an all channel added signal obtained by adding together the channel1speaker output, the channel2speaker output and the channel X speaker output.FIG. 9Fshows a signal obtained by predicting a decrease variation of a voltage applied to the power MOS from a voltage applied to the power MOS without a variation, shown inFIG. 9E, in the case of the added signal shown inFIG. 9D.

FIGS. 10A to 10Fare graphs showing a power supply voltage variation in the single-ended architecture, that is, a waveform example 1 in which each channel has a different variation.FIG. 10Ashows a channel1speaker output,FIG. 10Bshows a channel2speaker output,FIG. 10Cshows a channel X speaker output, andFIG. 10Dshows an all channel added signal obtained by adding together the channel1speaker output, the channel2speaker output and the channel X speaker output.FIG. 10Fshows a signal obtained by predicting a decrease variation of a voltage applied to the power MOS from a voltage applied to the power MOS without a variation, shown inFIG. 10E, in the case of the added signal shown inFIG. 10D.

FIGS. 11A to 11Fare graphs showing a power supply voltage variation in the single-ended architecture, that is, a waveform example 2 in which each channel has the same variation but differs in phase.FIG. 11Ashows a channel1speaker output,FIG. 11Bshows a channel2speaker output,FIG. 11Cshows a channel X speaker output, andFIG. 11Dshows an all channel added signal obtained by adding together the channel1speaker output, the channel2speaker output and the channel X speaker output.FIG. 11Fshows a signal obtained by predicting a decrease variation of a voltage applied to the power MOS from a voltage applied to the power MOS without a variation, shown inFIG. 11E, in the case of the added signal shown inFIG. 11D.

Returning to the flowchart ofFIG. 7, it is determined whether the architecture of the power block is BTL architecture or single-ended architecture (step S3). If it is determined in step S3that the architecture of the power block is BTL architecture, an absolute value is acquired (step S4). Specifically, the absolute value of the full-load signal31calculated at the adder32is acquired by the absolute value circuit33.

Then, the signal whose absolute value has been acquired by the absolute value circuit33is sign-inverted by the inverter34(step S5). If it is determined in step S3that the architecture of the power block is single-ended architecture, the process directly proceeds to step S5, and performs similar sign inversion processing.

Then, a multiplication of factor k is performed by the amplifier35(step S6). The multiplication of factor k is performed by amplifying the sign-inverted signal by the amplifier35with the factor k which acts to correct the predicted level decrease. Then, the power supply voltage correction signal12is inputted to the power source block25(step S7). In step S7, feedforward control of the power supply voltage of the power source block25is performed by using the power supply voltage correction signal12generated by the feedforward signal generation section24.

FIGS. 13A to 13Care graphs showing undistorted waveforms after the correction of the power supply voltage variation. Since the voltage applied to the power MOS (after correction) shown inFIG. 13Ais increased with respect to the decrease of the power supply voltage, the switching pulse of the power MOS during the power supply voltage correction shown inFIG. 13Bis increased to cancel the decrease. The switching pulse is approximately equal to the ideal switching pulse of the power MOS shown inFIG. 13B.

As is apparent from the foregoing description, according to the signal processing according to the embodiment of the present invention, it is possible to suppress the distortion of output sound due to power supply voltage variations. The embodiment of the present invention can also be applied to a digital amplifier of analog input architecture having an analog-to-digital converter at the front stage of its signal processing section, without the need for a large-scale circuit change.

According to the arrangement above, it is possible to suppress distortion generated due to power supply voltage variation, in a digital amplifier. The embodiment of the present invention is easily realized by simple mix processing, gain adjusting processing and addition of a delay circuit. A large scale circuit modification is not necessary.

The above-mentioned embodiments are not limitative, and it goes without saying that those skilled in the art can modify the construction of the present invention as needed without departing from the scope and spirit of the present invention described in the appended claims.