Amplifier circuit, biasing block with output gain compensation thereof, and electronic apparatus

An exemplary embodiment of the present disclosure illustrates an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The a biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing currents are substantially independent to temperature and/or system voltage variation.

BACKGROUND

1. Technical Field

The present disclosure relates to an amplifier, in particular, to an amplifier circuit having a biasing block with output gain compensation, and an electronic apparatus using the amplifier circuit.

2. Description of Related Art

Amplifier circuits are widely used in the electronic apparatuses of various kinds, such as radio frequency (RF) communication apparatuses. One of the amplifier circuits has a cascode low noise amplifier (LNA). The cascode LNA has higher input-output isolation, low noise figure and high gain.

The cascode LNA generally has two N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), wherein the two NMOSFETs are cascaded with each other. One of the two NMOSFETs is operating as a common source amplifier, while the other one of the two NMOSFETs is operating as a common gate amplifier. The cascode LNA improves the input-output isolation (or the reverse transmission) as there is no direct coupling from the output to the input of the cascode LNA, thus eliminating Miller effect and contributing to a much higher isolation. Moreover, at least one source degenerator circuit can be coupled to the cascode LNA for the input and/or output impedance matching.

However, when a radio frequency signal input to the cascode LNA increases, a load line of the cascode LNA may enter a saturation region due to nonlinear characteristics of the cascode LNA. Thus, the output gain of the cascode LNA is compressed, the output power of the cascode LNA is saturated, and the harmonic distortion is caused. In addition, the cascode LNA should be coupled to a biasing circuit to receive biasing voltages, such that the biasing current may not be changed due to the temperature and/or system voltage variation.

SUMMARY

An exemplary embodiment of the present disclosure provides an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing current are substantially independent to temperature and/or system voltage variation.

An exemplary embodiment of the present disclosure provides a biasing block with output gain compensation for an amplifier circuit, wherein an amplifier block is used to receive an input signal, and amplify the input signal to generate an output signal, and the biasing block coupled to the amplifier block comprises a DC biasing circuit and an output gain compensation circuit. The DC biasing circuit coupled to the amplifier block is used to provide partial of biasing voltages to bias the amplifier block, wherein the biasing current are substantially independent to temperature and/or system voltage variation. The output gain compensation circuit coupled to the amplifier block and the DC biasing circuit is used to receive partial of the biasing voltages and a feedback signal related to the output signal, wherein when input power of the input signal increases to a specific level, the feedback signal indicates the output gain compensation circuit to compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block.

An exemplary embodiment of the present disclosure provides an electronic apparatus comprising at least one function circuit and the foregoing amplifier circuit coupled to the least one function circuit.

To sum up, the amplifier circuit provided by the exemplary embodiment of the present disclosure has the biasing block to provide biasing current little affected by the temperature and/or system voltage variation to the amplifier block (i.e. compensation of the temperature and/or system voltage variation), and further to compensate the output gain compression.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present disclosure provide amplifier circuits. The amplifier circuit comprises a biasing block and an amplifier block with output gain compensation, wherein the biasing block is coupled to the amplifier block. The biasing block can provide stable biasing current not affected by the temperature and/or system voltage variation, and further compensate the output gain of the amplifier block.

To put it concretely, the biasing block comprises a direct current (DC) biasing circuit and an output gain compensation circuit, wherein the output gain compensation circuit is coupled to the DC biasing circuit and the amplifier block, and the DC biasing circuit is coupled to the amplifier block. In one exemplary embodiment of the present disclosure, the DC biasing circuit may have two transistors, such as two NMOSFETs, the amplifier block may have two transistors, such as two NMOSFETs, and the above mentioned four transistors form a Wilson current mirror. In another one exemplary embodiment of the present disclosure, the DC biasing circuit may have four transistors, such as four NMOSFETs, to form a Wilson current mirror. The Wilson current mirror is used to provide the biasing voltages to the output gain compensation circuit and the amplifier block, wherein the biasing currents are little affected by the temperature and/or system voltage variation.

The output gain compensation circuit may have two transistors, such as two NMOSFETs, wherein a control terminal of the one transistor, such as a gate of the one NMOSFET, is used to receive a feedback signal related to an output signal of the amplifier block. When the input power of the input signal is increased to a specific level, for example −20 dBm, the feedback signal received by the output gain compensation circuit is increased, and the output gain compensation circuit compensates the output gain of the amplifier block, thus extending the P1 dB compression point (p.s. P1 dB is used to indicate the input power level that causes the output gain to drop by 1 dB from its small signal value).

It is noted that, the output gain compensation circuit pulls lower a voltage on a control terminal of the one transistor (such as a gate of the one NMOSFET) in the DC biasing circuit, and thus a current flowing through the one transistor in the DC biasing circuit is decreased. Since the current flowing through the one transistor in the DC biasing circuit is constant, a voltage on a control terminal of the one transistor (such as a gate of the one NMOSFET) in the amplifier block is raised. Accordingly, a current flowing through the one transistor in the amplifier block is increased, and the output gain of the amplifier block is compensated to extend the 1 dB compression point.

Referring toFIG. 1,FIG. 1is a circuit diagram of an amplifier circuit according to an exemplary embodiment of the present disclosure. The amplifier circuit1comprises an amplifier block10and a biasing block with output gain compensation, wherein the biasing block comprises a DC biasing circuit11and an output gain compensation circuit12. The biasing block is coupled to the amplifier block10.

The amplifier block10receives an input signal from a signal source RF-IN, such as a radio frequency (RF) input signal from a RF antenna, and amplifies the input signal to generate an output signal VO1to an output load RF-OUT, such as a RF output signal to a back-end processing circuit, wherein an output gain can be a ratio of the output signal VO1to the input signal. The amplifier block10can be a cascode LNA, but the present disclosure however is not limited thereto.

The biasing block provides the biasing voltages to the amplifier block10, wherein the biasing currents are little affected by the temperature and/or system voltage variation. The biasing block further receives a feedback signal relative to the output signal VO1. When the input power of the input signal increases to a specific level, the feedback signal indicates the biasing block to compensates the output gain of the amplifier block10(i.e. for example less than 1 dB increment), such that the 1 dB compression point is extended.

The implementation details of the amplifier block10and the biasing block with gain compensation are illustrated as follows, but the present disclosure is however not limited thereto.

The amplifier block10comprises a first NMOSFET M1, a second NMOSFET M2, an input matching network, and an output matching network, wherein the first NMOSFET M1and the second NMOSFET M2are cascode with each other (i.e. a drain of the first NMOSFET M1is coupled to a source of the second NMOSFET M2), the first NMOSFET M1is coupled to the input matching network to receive the input signal from the signal source RF-IN, and the second NMOSFET M2is coupled to the output matching network to transmit the output signal VO1to the output load RF-OUT.

The input matching network and the output matching network are used to isolate the biasing voltages (i.e. large signals) from the input signal and the output signal VO1(i.e. small signals), and to perform input and output impedance matching. The implementation details of input matching network and the output matching network are illustrated as follows, but the present disclosure however is not limited thereto.

The input matching network comprises a first resistor RB1, a gate inductor Lg, a first capacitor C1, and a source inductor Ls. One end of the first capacitor C1is coupled to the input signal source RF-IN, and another one end of the first capacitor C1is coupled to one end of the gate inductor Lg and one end of the first resistor RB1. Another one end of the first resistor RB1is coupled to the drain of the first NMOSFET M1, and another end of the gate inductor Lg is coupled to a gate of the first NMOSFET M1. One end of the source inductor Ls is coupled to a source of the first NMOSFET M1, and another one end of the source inductor Ls is grounded.

The output matching network comprises a first load inductor LL1, a second load inductor LL2, a first load capacitor CL1, a second load capacitor CL2, and a load resistor RL. One end of the load first inductor LL1is used to receive the system voltage VSS, and another one end of the first load inductor LL1is coupled to a drain of the second NMOSFET M2. One end of the load resistor RL is used to receive the system voltage VSS, and another one end of the load resistor RL is coupled to the drain of the second NMOSFET M2, one end of the second load inductor LL2, and one end of the first load capacitor CL1. Another one end of the second load inductor LL2is coupled to one end of the second load capacitor CL2, another one end of the first load capacitor CL1is grounded, and another one end of the second load capacitor CL2is coupled to the output load RF-OUT.

The DC biasing circuit11comprises a third NMOSFET M3, a fourth NMOSFET M4, a first biasing capacitor CB1, a second biasing capacitor CB2, a second resistor RB2, and a constant current source IB. A drain of the fourth NMOSFET M4is coupled to the constant current source IB to receive a constant current. A gate of the fourth NMOSFET M4is coupled to the drain of the fourth NMOSFET M4, the gate of the second NMOSFET M2, and one end of the first biasing capacitor CB1. Another one end of the first biasing capacitor CB1is grounded. A source of the fourth NMOSFET M4is coupled to a drain of the third NMOSFET M3. One end of the second resistor RB2is coupled to a gate of the third NMOSFET M3and one end of the second biasing capacitor CB2, and another one end of the second biasing capacitor CB2and a source of the third NMOSFET M3are grounded.

It is noted that, based upon the above configuration, the first NMOSFET M1through the fourth NMOSFET M4form a Wilson current mirror. The ratio of the channel length to the channel width (L/W) associated with the third NMOSFET M3can be the same as those associated with the second NMOSFET M2through the fourth NMOSFET M4. By forming the Wilson current mirror, the effect which the temperature and/or system voltage variation affects the biasing current (generated by the biasing voltages applied to the gate of the first and second NMOSFETs M1, M2, such as the voltage VG) flowing through the first and second NMOSFETs M1, M2can be compensated. When the system voltages VSS changes from 2.5V to 3V, the deviation of the biasing current is about ±0.2%; when the temperature changes from −55° C. to 125° C., the deviation of the biasing current is about ±0.04%.

The output gain compensation circuit12comprises a fifth NMOSFET M5, a sixth NMOSFET M6, a feedback resistor RF1, a third resistor RB3, and a feedback capacitor CF. One end of the feedback resistor RF1is coupled to the gate of third NMOSFET M3, and another one end of the feedback resistor RF1is coupled to a drain of the fifth NMOSFET M5. One end of the third resistor RB3is coupled to one end of the feedback capacitor CF and a gate of the fifth NMOSFET M5, and another one end of the third resistor RB3is coupled to the gate of the third NMOSFET M3. Another one end of the feedback capacitor CF is coupled to the output load RF-OUT to receive the output signal VO1. A source of the fifth NMOSFET M5is grounded, and the drain of the fifth NMOSFET M5is coupled to a source of the sixth NMOSFET M6. A gate of the sixth NMOSFET M6is coupled to the gate of the fourth NMOSFET M4, and a drain of the sixth NMOSFET M6is used to receive the system voltage VSS.

It is noted that, the biasing voltages received by the gates of the first, third, and fifth NMOSFETs M1, M3, M5are the same, and the biasing voltages received by the gates of the second, fourth, and sixth NMOSFETs M2, M4, M6are the same, when there is no input signal feed in the amplifier block10, or the input power of the input signal is very small (for example, less than −30 dBm). That is, the voltage VD1on the drain of the first NMOSFET M1and the voltage Vdd1on the drain of the fifth NMOSFET M5are the same, and little affected by the temperature and/or system voltage variation.

Furthermore, the fifth and sixth NMOSFETs M5and M6form an extra gain stage to receive the feedback signal relative to the output signal VO1. The ratios of the channel length to the channel width (L/W) associated with the fifth and sixth NMOSFETs M5and M6are the same as those associated with the third and fourth NMOSFETs M3and M4. The amplifier block10may for example has the output gain around 19 to 20 dB, and the gain of the output gain compensation circuit12may be compressed earlier than the output gain of the amplifier block10.

To put it concretely, the DC component of the voltage Vdd1affects the biasing voltages to the first and second NMOSFETs M1, M2through the third NMOSFET M3. When the input power of the input signal increases to a specific level (for example −20 dBm), the feedback signal affects the voltage Vdd1through the feedback resistor RF1, and the voltage on the gate of the third NMOSFET M3is thus pulled down. However, the biasing current flowing through the third NMOSFET M3is constant value, such that the voltage VG on the gate of the second NMOSFET M2is raised, and the current flowing through the first and second NMOSFETs M1and M2is increased to compensate the output gain of the amplifier block10. Accordingly, the P1 dB compression point is extended.

Referring toFIG. 2,FIG. 2is a curve diagram showing a relation of the input power of the input signal and the output gain of the amplifier circuit inFIG. 1. The curve C21shows the relation of the input power of the input signal and the output gain of the amplifier circuit merely having the amplifier block10and the DC biasing circuit11(i.e. the amplifier circuit without having the output gain compensation circuit12), and the curve C22shows the relation of the input power of the input signal and the output gain of the amplifier circuit1. The P1 dB compression point of the amplifier circuit without having the output gain compensation circuit12is located at −16 dBm input power of the input signal (see point P21inFIG. 2), and the P1 dB compression point of the amplifier circuit1is located at −11 dBm input power of the input signal (see point P22inFIG. 2) while the output gain merely has 0.5 dB through 0.8 dB increment around −30 dBm to −10 dBm input power of the input signal.

Referring toFIG. 3,FIG. 3is a circuit diagram of an amplifier circuit according to another one exemplary embodiment of the present disclosure. The amplifier circuit3comprises an amplifier block30and a biasing block with output gain compensation, wherein the biasing block comprises a DC biasing circuit31and an output gain compensation circuit32. The biasing block is coupled to the amplifier block30.

The amplifier block30and the output gain compensation circuit32inFIG. 3are respectively the same as the amplifier block10and the output gain compensation circuit12inFIG. 1, while the implement details of the DC biasing circuit31inFIG. 3are not the same as those of the DC biasing circuit11inFIG. 1. The details of the amplifier block30and the output gain compensation circuit32are omitted, and the details of the DC biasing circuit31are illustrated as follows.

Compared to the DC biasing circuit11inFIG. 1, the DC biasing circuit31inFIG. 3further comprises the seventh and eighth NMOSFETs M7and M8. A drain of the eighth NMOSFET M8is used to receive the system voltage VSS, a gate of the eighth NMOSFET M8is coupled to the gate of the fourth NMOSFET M4, and a source of the eighth NMOSFET M8is coupled to a drain of the seventh NMOSFET M7. A gate of the seventh NMOSFET M7is coupled to the gate of the third NMOSFET M3, and a source of the seventh NMOSFET M7is grounded. Furthermore, the first resistor RB1of the input matching network in the amplifier block30is not coupled to the drain of the first NMOSFET M1. Therefore, in the exemplary embodiment, the third, fourth, seventh, eighth NMOSFETs M3, M4, M7, and M8form the Wilson current mirror to provide the biasing currents little affected by the temperature and system voltage variation to the first, second, fifth, sixth NMOSFETs M1, M2, M5, and M6.

It is noted that, the biasing voltages received by the gates of the first, fifth, NMOSFETs M1, M5are the same, and the biasing voltages received by the gates of the second and sixth NMOSFETs M2, M6are the same, when there is no input signal feed in the amplifier block30, or the input power of the input signal is very small (for example, less than −30 dBm). That is, the voltage VD1on the drain of the first NMOSFET M1, the voltage Vdd1on the drain of the fifth NMOSFET M5, and the voltage Vdd2on the drain of the seventh NMOSFET M7are the same, and little affected by the temperature and/or system voltage variation.

It is noted that, the details of the gain compensation in the exemplary embodiment are the same as those described above, and thus the repeated descriptions are omitted.

Referring toFIG. 4,FIG. 4is a curve diagram showing a relation of the input power of the input signal and the output gain of the amplifier circuit inFIG. 3. The curve C41shows the relation of the input power of the input signal and the output gain of the amplifier circuit merely having the amplifier block30and the DC biasing circuit31(i.e. the amplifier circuit without having the output gain compensation circuit32), and the curve C42shows the relation of the input power of the input signal and the output gain of the amplifier circuit3. The P1 dB compression point of the amplifier circuit without having the output gain compensation circuit32is located at −16 dBm input power of the input signal (see point P41inFIG. 4), and the P1 dB compression point of the amplifier circuit3is located at −11.2 dBm input power of the input signal (see point P42inFIG. 4) while the output gain merely has 1 dB through 2 dB increment around −20 dBm to −14 dBm input power of the input signal.

It is noted that one of the foregoing amplifier circuits can be applied in an electronic apparatus, especially a radio frequency apparatus, such as a notebook, a smartphone, or a pad. The electronic apparatus comprises one of the foregoing amplifier circuits and at least one function circuit for executing some specific functions, such as signal processing, communicating, displaying, and so on, wherein the at least one function circuit is coupled to the foregoing amplifier circuit.

To sum up, each of the amplifier circuits provided by the exemplary embodiments of the present disclosure has the biasing block to provide biasing currents little affected by the temperature and/or system voltage variation to the amplifier block (i.e. compensation of the temperature and/or system voltage variation), and further to compensate the output gain compression. In the exemplary embodiments of the present disclosure, the P1 dB compression point of the amplifier block can be extended at least 4 dBm, and the output gain increment before the output gain compress can be 1 dB to 2 dB.