Processing system and method for efficiently enabling detection of data hazards for long latency instructions

Generally, the present invention provides a processing system and method for indicating when there is a pending write to a general register of the processing system. The processing system of the present invention utilizes a plurality of general registers, a plurality of connections, a pipeline, a scoreboard, and hazard detection circuitry. The plurality of connections corresponds respectively with the general registers. The scoreboard maintains a plurality of bits such that each bit indicates whether there is a pending write to a corresponding general register. The scoreboard transmits to the hazard detection circuitry one of the bits that is indicative of whether a pending write to the one general register exists based on a value of the one bit and based on which of the connections is used to transmit the one bit. The hazard detection circuitry then detects whether a data hazard exists based on the one bit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to data processing techniques and, in particular, to a processing system and method for efficiently indicating when data produced by execution of one instruction is available for use in executing other instructions so that data hazards associated with the one instruction can be detected. The present invention is especially advantageous when the latency for producing the data of the one instruction is relatively long.

2. Related Art

To increase the performance of many processors, pipeline processing has been developed. In pipeline processing, a processor is equipped with at least one pipeline that can simultaneously process multiple instructions. Therefore, execution of one instruction in the pipeline may be commenced before the results of execution of a preceding instruction in the pipeline are available, thereby creating certain data hazards.

For example, a first instruction, when executed, may produce data and write the data to a particular register, and a second instruction, when executed, may utilize the data produced by the first instruction. If the second instruction executes before the data produced by the first instruction is available, then a data error occurs. Consequently, a data hazard exists between the two instructions until the data produced by the first instruction is available. This type of data hazard is commonly referred to as a “read-after-write” (RAW) data hazard.

In another situation, the second instruction, when executed, may write data to the same register as the first instruction, which commenced execution before the, second instruction. If the second instruction produces and writes its data to the register before the first instruction, then a data error is possible, since the register will contain the data of the first instruction instead of the second instruction after both instructions are fully executed and processed. As a result, a data hazard exists between the two instructions until the data produced by the first instruction is written to the register. This type of data hazard is commonly referred to as a “write-after-write” (WAW) data hazard.

To help prevent errors from the aforementioned data hazards and other types of data hazards, most superscalar processors include hazard detection circuitry that detects data hazards associated with the instructions being processed by the pipelines of the processor. The hazard detection circuitry usually detects the aforementioned data hazards by detecting when a later instruction utilizes (e.g., writes to or reads from) the same register as an earlier instruction that has yet to produce available data.

However, the data produced by a first instruction may not be available for use by other instructions or for writing to a particular register of a processor until well after the first instruction has been retired by the pipeline processing the first instruction (e.g., until well after the first instruction has exited the pipeline). For example, a load instruction, when executed, may generate a request to retrieve data from memory external to the processor. Depending on where the data is located in the memory hierarchy, it may take anywhere between a few clock cycles to several thousand clock cycles for the data to be returned to the processor in response to the aforementioned request. Therefore, the processor may not receive the data produced by the first instruction until after the first instruction exits the processor's pipelines or is otherwise retired. In other words, the data produced by the first instruction does not become available for use in executing other instructions until after the first instruction exits the processor's pipeline or is otherwise retired. An instruction, such as the aforementioned load instruction, that produces available data after the instruction has been retired by a pipeline shall be referred to herein as a “long latency instruction.”

To facilitate the process of detecting data hazards for long latency instructions, the processor is usually equipped with a register file, commonly referred to as a “scoreboard,” that indicates when the processor has yet to receive data produced in response to a previous execution of a producer (i.e., an instruction that produces data). In other words, the scoreboard indicates when there is a pending write to a general register. As used herein, the term “pending write” shall be used to refer to a situation in which data produced by an earlier executed instruction is destined for a general register but has yet to be written to the general register. As known in the art, a “general register” is one of a set of registers that are either written to via the execution of write instructions and/or are read from via the execution of read instructions.

The scoreboard includes a plurality of registers in which each register contains a bit value. Each scoreboard register and the bit value contained therein correspond to one of the general registers of the processor that receives data produced by the execution of write instructions. When a write instruction is retired before the data produced by the write instruction has been written to the general register that is to receive the data, the bit value in the scoreboard register that corresponds to the general register is asserted. Furthermore, when the data produced by the write instruction is finally written to the general register, the aforementioned bit value is deasserted. Therefore, to determine whether there is a pending write to one of the general registers, the bit value in the scoreboard register corresponding to the one general register can be analyzed.

Each asserted bit value in the scoreboard indicates that there is a pending write to the general register corresponding to the asserted bit value. Therefore, any instruction being processed by the processor should be prevented from writing to or reading from the foregoing general register to prevent errors from RAW or WAW data hazards, until at least the pending write expires (i.e., until the data destined for the general register is actually written to the general register). Furthermore, each deasserted bit value in the scoreboard indicates there is presently no pending write to the general register corresponding to the deasserted bit value. Therefore, an instruction being processed by the processor may read from or write to the foregoing general register without creating any errors from RAW or WAW data hazards.

When a RAW or WAW data hazard is detected by analyzing the scoreboard or otherwise, errors from the RAW or WAW data hazard are often prevented by stalling one or more instructions being processed by the processor. U.S. Patent Application entitled “Superscalar Processing System and Method for Efficiently Performing In Order Processing of Instructions,” assigned Ser. No. 09/390,199, and filed on Sep. 7, 1999, which is incorporated herein by reference, describes in more detail a process of stalling instructions to prevent data hazards. When an instruction is stalled, the processor temporarily refrains from further processing the instruction until the data hazard causing the stall expires.

Unfortunately, the wiring and other circuitry typically used to write to and read from the scoreboard is relatively complex and often utilizes a relatively large amount of surface area within a processor. To minimize the cost of the processor, it is desirable for the circuitry required to detect data hazards to be minimized. In particular, it is desirable to minimize and simplify the circuitry required to write to and read from the scoreboard.

Thus, a heretofore unaddressed need exists in the industry for providing a efficient system and method of utilizing a scoreboard to detect data hazards.

SUMMARY OF THE INVENTION

The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a system and method for executing instructions of a computer program and for efficiently indicating the existences of pending writes to general registers that are used in executing the instructions.

In architecture, the processing system of the present invention utilizes a plurality of general registers, a plurality of connections, a pipeline, a scoreboard, and hazard detection circuitry. The plurality of connections corresponds respectively with the general registers. The scoreboard maintains a plurality of bits such that each bit indicates whether there is a pending write to a corresponding register. The scoreboard transmits to the hazard detection circuitry one of the bits that is indicative of whether a pending write to the one general register exists based on a value of the one bit and based on which of the connections is used to transmit the one bit. The hazard detection circuitry then detects whether a data hazard exists based on the one bit.

In accordance with another feature of the present invention, a decoder is used to decode a register identifier associated with data being written to one of the general registers. The decoder transmits the register identifier to both the scoreboard and the hazard detection circuitry. The hazard detection circuitry may use the register identifier to detect a data hazard, and the scoreboard may use the register identifier to modify one of the bits in the scoreboard.

The present invention can also be viewed as providing a method for processing instructions of a computer program. The method can be broadly conceptualized by the following steps: providing a plurality of general registers; maintaining a plurality of bits, each of the bits respectively corresponding with one of the general registers; providing a plurality of connections, each of the connections respectively corresponding with one of the general registers; indicating, via the bits, which of the general registers are associated with pending writes; transmitting one of the bits corresponding with a particular one of the general registers across a particular one of the connections, the one connection corresponding with the particular one general register; and detecting a data hazard based on the one bit transmitted across the particular one connection.

Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention generally relates to a processing system that efficiently detects data hazards for long latency instructions with a minimal amount of circuitry and complexity. To better illustrate the principles of the present invention, first refer toFIG. 1, which depicts a conventional superscalar processing system15. The processing system15includes an instruction dispersal unit18that receives instructions of a computer program and assigns each instruction to one of a plurality of pipelines21. Each pipeline21is configured to process and execute, if appropriate, each instruction assigned to the pipeline21.

Each pipeline21is usually configured to only process particular types of instructions (e.g., integer operation, floating point operation, memory operation, etc.). Therefore, the instruction dispersal unit18is configured to assign each instruction only to a pipeline21compatible with the instruction. Furthermore, although control circuitry24, hazard detection circuitry25, and register file27, which is often referred to as a “scoreboard,” are shown for simplicity as being coupled to one pipeline21inFIG. 1, it should be noted that each pipeline21is similarly coupled to the control circuitry24, the hazard detection circuitry25, and the scoreboard27. However, if desired, the connections31, which couple the one pipeline21to a write port of the scoreboard27, may be removed for any pipeline21that does not process a long latency instruction.

It is well known that data is often written to and read from general registers29associated with the processing system15in executing the instructions received by the processing system15. Furthermore, when a general register29is utilized (i.e., written to or read from) in executing an instruction, the instruction usually includes a register identifier that identifies the general register29. The register identifier is usually an n-bit encoded binary value that is unique to the general register29identified by the register identifier.

The hazard detection circuitry25is configured to receive and compare the register identifiers included in the instructions being processed by the pipelines21to determine if any data hazards, such as RAW and/or WAW data hazards, exist between the instructions processed by the pipelines21. If the hazard detection circuitry25detects a data hazard, the hazard detection circuitry25transmits a notification signal to the control circuitry24indicating which instruction in the pipelines21is associated with the data hazard. In response, the control circuitry24may transmit a control signal to one or more pipelines21to cause the one or more pipelines21to stall (i.e., temporarily prevent further processing of instructions) in order to prevent a data error associated with the data hazard. Once the data hazard expires, the control circuitry24enables the processing of the stalled instruction or instructions to resume.

Execution of some instructions causes the retrieval of data from external registers or locations in memory outside of the processing system15. When such data is received by the processing system15, the processing system15usually writes the data to a general register29identified by the instruction that retrieved the data. Usually, the data is then utilized to execute a later instruction.

The time required to retrieve the data varies depending on where the data is located, and the instruction that requests the retrieval of the data is often retired before the data is received by the processing system15. However, once an instruction is retired and has exited the pipelines21, the hazard detection circuitry25usually can no longer detect a RAW or a WAW data hazard associated with the instruction by only comparing register identifiers of the instructions in the pipelines21, even though such a data hazard may exist until the retrieved data is at least received by the processing system15.

Therefore, additional steps are usually taken to detect data hazards associated with instructions that have been retired. For example, in the embodiment shown byFIG. 1, if a pending write is caused by a producer that is about to be retired, then the register identifier included in the producer and associated with the pending write (i.e., identifying the general register29that is to be written to) is transmitted to scoreboard27via a set of connections31. It should be noted that, for simplicity,FIG. 1shows only one set of connections31coupling one of the pipelines21to the scoreboard27. However, there are typically multiple sets of connections31that respectively couple multiple pipelines21to different write ports of the scoreboard27. Each pipeline21that processes long latency instructions should be coupled to the scoreboard27in the manner that the set of connections31couples one of the pipelines21to the scoreboard27inFIG. 1, although more pipelines21may be similarly coupled to the scoreboard27, if desired.

The scoreboard27includes a plurality of registers32, as shown byFIG. 2. Each of the scoreboard registers32respectively corresponds to a different one of the general registers29(FIG. 1) and contains a bit value. The scoreboard27includes a write port34acoupled to connections31. The write port34areceives the aforementioned register identifier included in the producer associated with the pending write and asserts the bit value in the scoreboard register32corresponding to the general register29identified by the received register identifier. The register identifier is often encoded, and the write port34a, therefore, decodes the register identifier before asserting the bit in the appropriate scoreboard register32.

Referring again toFIG. 1, the data to be written to a general register29associated with a pending write is usually received by an interface42along with a register identifier that identifies the general register29. The interface42transmits the foregoing data to the identified general register29and transmits the register identifier to the scoreboard27via connections45a. The scoreboard27includes a write port34b(FIG. 2) coupled to connections45athat receives the register identifier from connections45aand deasserts the bit value in the scoreboard register32corresponding to the general register29identified by the register identifier.

Since the interface42may receive multiple register identifiers in a single cycle, the system15, as shown byFIGS. 1 and 2, may include multiple sets of other connections, such as connections45b, and multiple other write ports, such as write port34c, to respectively transmit and receive each of the register identifiers received by interface42to scoreboard27. Furthermore, the scoreboard27usually includes multiple write ports34athat are respectively coupled to different pipelines21for receiving register identifiers from the different pipelines21. Therefore, the number of write ports34a,34b, and34ccan become quite large and the circuitry for interfacing the write ports34a,34b, and34cwith the registers32can, therefore, be complicated and expensive.

By asserting and deasserting the bit values in the registers32, as described above, the hazard detection circuitry25can detect data hazards associated with retired instructions based on the bits contained in the registers32of the scoreboard27. In this regard, if a bit contained in a scoreboard register32that corresponds to a particular one of the registers29is asserted, then there exists a pending write to the one general register29. Consequently, a RAW or WAW data hazard may exist, if another instruction being processed by the pipelines21utilizes data from the one general register29. However, if the bit contained in the foregoing register32is deasserted, then there is presently no pending write to the one general register32by a retired instruction. Therefore, a RAW or WAW data hazard associated with a retired instruction that writes to the one general register29should not exist.

Each pipeline21is usually coupled to one read port48a, as shown byFIGS. 1 and 2for one of the pipelines21. To detect a data hazard between a pending instruction in a pipeline21and a previously retired instruction, the pipeline21usually transmits via connections49an encoded n-bit register identifier identifying a general register29that is to be used in executing the pending instruction. The read port48areceives and decodes the register identifier. The read port48aalso analyzes the bit contained in the scoreboard register32that corresponds with the general register29identified by the register identifier. If the bit in the foregoing scoreboard register32indicates that there is a pending write to the general register29identified by the register identifier, the read port48atransmits, via connection52, a signal indicating that a data hazard associated with the foregoing instruction may exist. For example, if the bit in the scoreboard register32analyzed by the read port48ais asserted, then the read port48atransmits an asserted one bit signal. Otherwise, the read port48atransmits a deasserted one bit signal. Based on the signal transmitted across connection52, the hazard detection circuitry25determines whether or not a data hazard associated with the pending instruction exists.

Note that there is a finite amount of delay associated with writing to and reading from the scoreboard27. Therefore, to quickly provide the hazard detection circuitry25with updates, the register identifiers transmitted to the scoreboard27via the interface42also bypass the scoreboard27via bypass connections54aand/or54b. In certain situations, the hazard detection circuitry25may utilize the register identifiers from bypass connections54aand/or54bto prevent or remove a stall on an instruction in one of the pipelines21.

Furthermore, each instruction may utilize more than one general register29when executed and, therefore, may contain more than one register identifier. A separate set of connections49and52and a separate read port48aare usually provided for each possible register identifier. For example, if the architecture of the system15is such that each instruction in each pipeline21may include up to three register identifiers, then there is usually at least three read ports48a,48b, and48ccoupled to each pipeline21via three sets of connections49. Therefore, as can be appreciated by one skilled in the art, the number of read ports48a,48b, and48cand connections49and52in the system15can be quite large for many superscalar processors, thereby increasing the amount of wiring and the complexity of the system15. To reduce the complexity and cost of the system15and to conserve valuable space in the system15, it is desirable to minimize the circuitry utilized in writing to and reading from the scoreboard27, including the number of write ports34a,34b, and/or34cand read ports48a,48b, and/or48c.

In general, the present invention provides a processing system that efficiently and with a minimal amount of circuitry and complexity tracks pending writes caused by retired instructions.FIG. 3depicts a processing system50in accordance with the principles of the preferred embodiment of the present invention. As shown byFIG. 3, the processing system50may be employed within a computer system55for executing instructions from a computer program57that is stored in memory59.

The processing system50communicates to and drives the other elements within the system55via a local interface62, which can include one or more buses. Furthermore, an input device64, for example, a keyboard or a mouse, can be used to input data from a user of the system55, and screen display66or a printer68can be used to output data to the user. A disk storage mechanism71can be connected to the local interface62to transfer data to and from a nonvolatile disk (e.g., magnetic, optical, etc.). The system55can be connected to a network interface73that allows the system55to exchange data with a network75.

Similar to conventional system15, processing system50includes at least one pipeline21, control circuitry24, hazard detection circuitry81, and a scoreboard82, as shown byFIG. 4. Although only one pipeline21is coupled to the control circuitry24and the hazard detection circuitry81inFIG. 4, the other pipelines21are similarly coupled to the control circuitry24and the hazard detection circuitry81in the preferred embodiment. Furthermore,FIG. 4shows one pipeline21coupled to the scoreboard82via connections83and a decoder84. Each pipeline21that processes long latency instructions is similarly coupled to the scoreboard82in the preferred embodiment, although other pipelines21can be similarly coupled to the scoreboard82, if desired.

Similar to conventional hazard detection circuitry25, the hazard detection circuitry81of the preferred embodiment detects data hazards associated with the instructions being processed by the pipelines21, based on the register identifiers of the foregoing instructions. To this end, the register identifier(s) of each instruction in the pipelines21is transmitted to the hazard detection circuitry81, which compares the register identifiers to detect data hazards. However, each n-bit encoded register identifier transmitted to the hazard detection circuitry81is first decoded by a decoder84into an m-bit register identifier, where m corresponds to the number of general registers29used by the system50to write and read data produced by the execution of instructions.

In this regard, each bit of an m-bit decoded register identifier corresponds to a particular general register29. When a decoder84receives an n-bit register identifier that identifies one of the general registers29, the decoder84is configured to assert the bit in the m-bit register identifier that corresponds to the one general register29and to deassert the remaining bits in the m-bit register identifier. Therefore, by detecting which bit in the m-bit decoded register identifier is asserted, it can be determined which general register29is identified by the m-bit decoded register identifier. Commonly assigned U.S. Patent Application entitled “System and Method for Efficiently Detecting Data Hazards Between Instructions of a Computer Program,” assigned Ser. No. 09/490,390, and filed on Jan. 24, 2000, and commonly assigned U.S. Patent Application entitled “System and Method for Utilizing Instruction Attributes and Register Identifiers to Detect Data Hazards Between Pipeline Processed Instructions,” assigned Ser. No. 09/490,389, and filed on Jan. 24, 2000, which are both incorporated herein by reference, describe in more detail circuitry that may be used to implement the decoders84and circuitry that may be used by hazard detection circuitry81to detect when the register identifiers of two instructions match and, therefore, when a data hazard may exist between the two instructions.

Similar to conventional scoreboard27, the scoreboard82includes a plurality of registers32, as shown byFIG. 5, in which each scoreboard register32and, therefore, the bit value contained therein correspond to a particular general register29. When asserted, a bit in a scoreboard register32indicates that there is a pending write by a retired instruction to the corresponding general register29. When deasserted, a bit in a scoreboard register32indicates that no such pending write exists.

Therefore, the scoreboard82, similar to conventional scoreboard27, indicates which general registers29are associated with pending writes caused by retired instructions. However, as previously indicated, scoreboard27via write ports34a,34b, and34ctypically decodes the register identifiers transmitted across connections31,45a, and45b. In the preferred embodiment, the scoreboard82is coupled to at least one of the decoders84via connections83, as shown byFIG. 5. Therefore, the foregoing decoder84provides an m-bit decoded register identifier to both the hazard detection circuitry81and the scoreboard82. Since the register identifier transmitted by connections83has m bits, each of the connections83can be coupled directly to the registers32, thereby eliminating the need of a write port34a(FIG. 2) in the scoreboard82.

In this regard, each bit transmitted across one of the connections83is provided to the scoreboard register32that corresponds to the same general register29as the foregoing bit. In other words, when the m-bit register identifier transmitted across connections83identifies a particular one of the general registers29, only the scoreboard register32corresponding to the one general register29should receive an asserted bit, and the other scoreboard registers32should receive a deasserted bit. As a result, there is no need for a write port34a(FIG. 2) in the scoreboard82to detect which scoreboard register32corresponds to the general register29identified by the register identifier received by the scoreboard82. Instead, the same decoder84that provides an m-bit register identifier to hazard detection circuitry81may also be used to provide the appropriate bit values to the appropriate registers32. Accordingly, the amount and complexity of the circuitry required to detect data hazards and to appropriately assert the bits in the scoreboard82are minimized in the preferred embodiment.

In addition, the register identifiers received from connections45aand45bare preferably decoded by a decoder85instead of write ports34band34c(FIG. 2) in the scoreboard82. In this regard, the decoder85is configured to receive the n-bit encoded register identifiers presently transmitted from interface42and to output an m-bit decoded register identifier identifying each of the general registers29identified by the n-bit register identifiers that are received in the same cycle.

In the preferred embodiment, the value m corresponds to the number of general registers29in the processing system50, and each bit of the m-bit decoded register identifier transmitted by decoder85corresponds to a different general register29. The decoder85is configured to assert each bit in the m-bit decoded register identifier that corresponds to a general register29identified by one of the n-bit register identifiers received in the same cycle and to deassert the remaining bits of the m-bit decoded register identifier. Therefore, a general register29is identified by the m-bit decoded register identifier transmitted by decoder85when the corresponding bit in the decoded register identifier is asserted.

When the scoreboard82receives a new decoded register identifier from the decoder85, the scoreboard82is designed to deassert the bits in the scoreboard registers32corresponding to the general registers29identified by the decoded register identifier, since the pending writes to the foregoing general registers29should no longer exist.

In this regard, each scoreboard register32receives a bit of the decoded register identifier from decoder85. The scoreboard register32preferably corresponds to the same general register29as the bit received by the scoreboard register32. In other words, when the decoded register identifier from decoder85identifies one of the general registers29, the scoreboard register32corresponding to the identified general register29should receive an asserted bit from the decoder85. Moreover, when the value of a bit received from decoder85is asserted, the scoreboard register32receiving the asserted bit value is designed to clear (e.g., to deassert) the bit value contained in the register32. As a result, an asserted bit in a scoreboard register32corresponding to a particular one of the general registers29indicates that there is presently a pending write to the one general register29, and a deasserted bit in the scoreboard register32indicates that there is presently no such pending write.

When desired, the scoreboard82transmits, via connections88, to hazard detection circuitry81a signal corresponding to the data contained in the scoreboard registers32so that the hazard detection circuitry81can properly detect data hazards, such as RAW and WAW data hazards. In the preferred embodiment, each of the connections88is coupled to a different one of the scoreboard registers32and, therefore, corresponds to the same general register29as the one scoreboard register32coupled to the connection88. Therefore, the signal transmitted to hazard detection circuitry81is an m-bit data word, and each bit of the m-bit data word corresponds to a bit value from a different scoreboard register32. As a result, each asserted bit in the m-bit data word indicates that there is a pending write to a particular one of the general registers29. The m-bit data word is essentially an m-bit register identifier that may simultaneously identify more than one of the general registers29. Since each of the scoreboard registers32is coupled directly to the hazard detection circuitry83via one of the connections88in the preferred embodiment, the read ports48a,48, and48c(FIG. 2) in conventional scoreboard27can be eliminated.

However, since there is a finite amount of delay in writing to and reading from the scoreboard27, the data transmitted by the scoreboard82is not always updated. As a result, it is possible for the data word transmitted across connection88to indicate that a pending write exists, when the pending write has, in fact, recently expired. To provide the hazard detection circuitry81with most up-to-date information available, a bypass connection94that bypasses the scoreboard82provides the decoded m-bit register identifier from decoder85to the hazard detection circuitry81, similar to bypass connections54aand54bof conventional system15.

The hazard detection circuitry81detects data hazards by comparing the m-bit register identifiers received from the pipelines21via the decoders84to the m-bit register identifier received from connections88and/or94.FIG. 6shows an exemplary implementation of circuitry101that may be used to detect a data hazard by comparing an m-bit register identifier received from the pipelines21to the m-bit register identifier received from connections88or94.

Each AND gate104receives a bit of the m-bit register identifier from the pipeline21and a bit of the m-bit register identifier from the connections88or94. Furthermore, each bit received by the same AND gate104corresponds to the same general register29. Therefore, one of the AND gates104should produce an asserted output only when the m-bit register identifier from the pipeline21identifies one of the general registers29identified by the m-bit register identifier from connections88or94. As a result, if one of the AND gates104produces an asserted output, then the instruction associated with the m-bit register identifier from the pipeline21utilizes a general register29subject to a pending write, and a data hazard associated with the, foregoing instruction may, therefore, exist.

Consequently, when one of the AND gates104produces an asserted output, the hazard detection circuitry81detects a data hazard associated with the instruction associated with the m-bit register identifier received from the pipeline21. However, if none of the AND gates104produces an asserted output, then there should be no pending write associated with the general register29identified by the m-bit register identifier received from the pipeline21. Therefore, there should be no pending write to the general register29utilized by the instruction associated with the m-bit register identifier from the pipeline21, and the hazard detection circuitry81fails to detect a data hazard associated with the foregoing instruction.

According to the foregoing techniques, the hazard detection circuitry81may detect a data hazard and transmit a signal to control circuitry24indicating that a data hazard associated with one of the instructions in the pipelines21exists. In response, the control circuitry24, in order to prevent a data error from the detected data hazard, may transmit a control signal to the pipeline21processing the foregoing instruction indicating that the foregoing instruction should be stalled. In response, the pipeline21preferably stalls the instruction.

By later comparing the m-bit register identifier associated with the foregoing instruction with the m-bit register identifier received from connections88or94, the hazard detection circuitry81may detect that the aforementioned data hazard no longer exists. In this regard, the data destined for the general register29utilized by the instruction may have been received by the processing system50, thereby causing the aforementioned data hazard to expire. In response to the failure of the hazard detection circuitry81to detect a data hazard associated with the aforementioned instruction, the control circuitry24transmits a control signal to the pipeline21processing the instruction indicating that the instruction should not be stalled. In response, the pipeline21removes the stall on the instruction, and processing of the instruction by the pipeline21resumes.

It should be noted that the decoder85is not a necessary feature of the present invention. In this regard, it is possible for the scoreboard82to include circuitry for decoding, if necessary, the register identifiers received from connections45aand/or45b, and the register identifiers transmitted across connections45aand/or45bmay be transmitted directly to hazard detection circuitry81, similar to conventional system15. In such an embodiment, the hazard detection circuitry81may include decoders for appropriately decoding the register identifiers transmitted across connections45aand/or45b, if necessary.

Furthermore, for simplicity, the systems15and50have been shown herein as containing only four general registers29. Therefore, the value of m preferably equals four in the embodiments shown by the drawings. However, the system50can include any number of registers29in other embodiments, and the value of m, therefore, can be other integer values in other embodiments. Furthermore, it is possible for the register identifiers to be decoded or encoded into data words with lengths greater than or less than m, although such embodiments are usually less efficient than the preferred embodiment. In this regard, providing the hazard detection circuitry81with m-bit register identifiers not only may reduce the circuitry of the system50, but may also simplify and/or enable better detection of data hazards by data hazard circuitry81.

In addition, as can be seen by comparingFIG. 5toFIG. 2, the configuration of the preferred embodiment eliminates the need of including read ports48a,48b, and48cin the scoreboard82. Furthermore, one of the decoders84may efficiently perform the functionality of decoding a register identifier that is to be transmitted to both the scoreboard82and the hazard detection circuitry81. As a result, the amount of circuitry needed to implement the system50is minimized in the preferred embodiment, thereby minimizing the cost and complexity of the system50.

OPERATION

The preferred use and operation of the processing system50and associated methodology are described hereafter.

Assume that in processing the instructions of computer program57(FIG. 3), the processing system50(FIG. 4) receives a first instruction that, when executed, causes data (hereinafter referred to as the “retrieved data”) to be retrieved from memory59and stored in a general register29of the processing system50. Also, assume that the processing system50later receives a second instruction from the program57that, when executed, utilizes the retrieved data. Since the aforementioned general register29is utilized to execute both instructions, the first instruction and the second instruction both include a register identifier identifying the aforementioned general register29.

While the first instruction and the second instruction are simultaneously processed by the pipelines21, the hazard detection circuitry81can detect a RAW data hazard between the two instructions by comparing the decoded register identifiers of the two instructions. At some point, the control circuitry24may cause the second instruction to be stalled to prevent an error associated with the RAW data hazard. If the first instruction is retired before the retrieved data is received by processing system50, then the RAW hazard may exist between the first instruction and second instruction, even though the first instruction is retired.

To enable the hazard detection circuitry81to detect the RAW hazard after first instruction is retired, an m-bit register identifier identifying the general register29that is to receive the retrieved data is transmitted to scoreboard82via connections83, which are coupled to the pipeline21processing the first instruction. In response, the scoreboard82asserts the bit in the scoreboard register32(FIG. 5) that corresponds with the general register29identified by the foregoing register identifier (i.e., the general register29that is to receive the retrieved data).

Based on the bit value contained in the foregoing scoreboard register32and the register identifier of the second instruction, the hazard detection circuitry81may detect the aforementioned RAW data hazard, even though the first instruction has been retired. In response, the control circuitry24may then cause the second instruction to be stalled.

When the retrieved data is received by the interface42, the register identifier identifying the general register29to receive the retrieved data is transmitted to decoder85via connections45aor45b. In response to the register identifier, the decoder85produces an m-bit decoded register identifier that identifies at least the foregoing general register29. In this regard, the bit in the decoded register identifier corresponding to the foregoing general register29is asserted. This m-bit register identifier is then transmitted to scoreboard82, which deasserts the bit in the scoreboard register32(FIG. 5) corresponding to the foregoing general register29in response to the asserted bit in the decoded register identifier. The m-bit register identifier transmitted to scoreboard82is also transmitted to hazard detection circuitry81via bypass connection94.

Based on either the deasserted bit value in the aforementioned scoreboard register32or the foregoing m-bit register identifier transmitted across bypass, connection94, the hazard detection circuitry81detects that the RAW hazard no longer exists. In response, the control circuitry24removes the stall on the second instruction, and processing of the second instruction resumes without causing a data error associated with the aforementioned RAW data hazard.

Although the present invention has been described herein as utilizing the scoreboard82to indicate when data produced by long latency instructions is unavailable, it should be noted that the scoreboard82may be similarly used to indicate when data produced by any type of instruction is unavailable. In particular, the scoreboard82may be used to indicate whether data produced by pending instructions (i.e., instructions that have yet to be retired and are still being processed by the pipelines21) is unavailable. Furthermore, although the present invention has been described herein in some examples as utilizing the scoreboard82to indicate whether data produced by a load instruction is unavailable, the present invention should not be so limited, and the scoreboard82may also be used to indicate whether data produced by any other type of instruction is unavailable.