DC offset calibration system and method

A DC offset calibration system and method. The method includes: in a first calibration mode, outputting a first digital signal by using a control circuit, generating a first differential calibration signal according to the first digital signal by using a first digital-to-analog conversion circuit, generating a first amplified signal according to the first differential calibration signal by using an amplification circuit, and feeding back the first amplified signal to the control circuit to adjust the first digital signal; and in a second calibration mode, outputting a second digital signal by using the control circuit, generating a second differential calibration signal according to the second digital signal by using a second digital-to-analog conversion circuit, generating a second amplified signal according to the second digital signal by using an equalizing circuit and the amplification circuit, and feeding back the second amplified signal to the control circuit to adjust the second digital signal.

CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 202010760095.2 filed in China, P.R.C. on Jul. 31, 2020, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Technical Field

The present invention relates to the field of DC offset calibration, and in particular, to a DC offset calibration system and method.

Related Art

With the continuous improvement of the integrated circuit manufacturing process, high-speed serial communication technologies have been further developed. However, with an increase of a clock speed and various undesirable factors during transmission (for example, transmission line loss and manufacturing process deviation), the transmission performance of a high-speed receiver circuit will be degraded, and even the requirement of a high-speed data transmission protocol cannot be satisfied. In view of the above situation, it is necessary to add a terminal matching circuit, an equalizing circuit, and a sense amplifier to the high-speed receiver circuit to alleviate the problem, but adding these circuits also introduces a process deviation and a DC offset error, so it is very important to eliminate these errors. At present, the technologies to eliminate the DC offset are to reduce the offset error by directly increasing an element area, and to calibrate the offset error by adding an auxiliary analog circuit. The method of reducing the offset error by directly increasing the element area is simple, but may affect an operating speed of the high-speed receiver circuit. The method of adding the auxiliary analog circuit is filtering out, by using a low-pass filter, high-frequency components of a signal to obtain a DC potential to control and eliminate the DC offset. However, the disadvantage is that the low-pass filter circuit also needs to occupy the element area, which will also affect the operating speed of the high-speed receiver circuit.

SUMMARY

In view of the above, the present invention proposes a DC offset calibration system and method.

In some embodiments, the DC offset calibration system is disposed at a receiver to process a differential input signal, and is adapted to operate in one of an operation mode, a first calibration mode, and a second calibration mode. The DC offset calibration system includes a matching circuit, an equalizing circuit, an amplification circuit, a control circuit, a first digital-to-analog conversion circuit, and a second digital-to-analog conversion circuit. The equalizing circuit is electrically connected to the matching circuit, the amplification circuit is electrically connected to the equalizing circuit, and the control circuit is electrically connected to the amplification circuit. In the operation mode, the matching circuit provides impedance matching for the differential input signal. The control circuit outputs a first digital signal in the first calibration mode, and outputs a second digital signal in the second calibration mode. The first digital-to-analog conversion circuit generates a first differential calibration signal according to the first digital signal, and the second digital-to-analog conversion circuit generates a second differential calibration signal according to the second digital signal. In the first calibration mode, the amplification circuit generates a first amplified signal according to the first differential calibration signal, and feeds back the first amplified signal to the control circuit to adjust the first digital signal, thereby reducing DC offset of the amplification circuit. In the second calibration mode, the equalizing circuit and the amplification circuit generate a second amplified signal according to the second digital signal, and feed back the second amplified signal to the control circuit to adjust the second digital signal, thereby reducing DC offset of the equalizing circuit.

In some embodiments, the DC offset calibration method is adapted to operate in one of an operation mode, a first calibration mode, and a second calibration mode. The DC offset calibration method includes: providing, in the operation mode by a matching circuit, impedance matching for a differential input signal; in first calibration mode: outputting, by a control circuit, a first digital signal; generating, by a first digital-to-analog conversion circuit, a first differential calibration signal according to the first digital signal; and generating, by an amplification circuit, a first amplified signal according to the first differential calibration signal, and feeding back the first amplified signal to the control circuit to adjust the first digital signal, thereby reducing DC offset of the amplification circuit; and in the second calibration mode: outputting, by the control circuit, a second digital signal; generating, by a second digital-to-analog conversion circuit, a second differential calibration signal according to the second digital signal; and generating, by the equalizing circuit and the amplification circuit, a second amplified signal according to the second digital signal, and feeding back the second amplified signal to the control circuit to adjust the second digital signal, thereby reducing DC offset of the equalizing circuit.

Based on the above, according to the DC offset calibration system and method provided by some embodiments of the present invention, the control circuit, the first digital-to-analog conversion circuit, and the second digital-to-analog conversion circuit can be used to calibrate the DC offset during processing of the differential input signal by the matching circuit, the equalizing circuit, and the amplification circuit. In the first calibration mode, the control circuit adjusts the first digital signal according to the amplified signal fed back by the amplification circuit, and the first digital-to-analog conversion circuit outputs the first differential calibration signal to the amplification circuit according to the first digital signal, to adjust the DC offset. In the second calibration mode, the control circuit adjusts the second digital signal according to the amplified signal fed back by the amplification circuit, and the second digital-to-analog conversion circuit outputs the second differential calibration signal to the equalizing circuit according to the second digital signal, to adjust the DC offset. In the operation mode, the matching circuit can provide impedance matching for the differential input signal. Therefore, the DC offset calibration system can eliminate the DC offset.

DETAILED DESCRIPTION

FIG. 1is a schematic block diagram of a DC offset calibration system10according to some embodiments of the present invention.FIG. 2is a schematic circuit diagram of a DC offset calibration system10according to some embodiments of the present invention.FIG. 3is a schematic timing diagram of a DC offset calibration system10according to some embodiments of the present invention. Referring toFIG. 1,FIG. 2, andFIG. 3together, in some embodiments, the DC offset calibration system10is disposed at a receiver to process a differential input signal Vin, and is adapted to operate in one of an operation mode M3, a first calibration mode M1, and a second calibration mode M2. The DC offset calibration system10includes a matching circuit100, an equalizing circuit200, an amplification circuit300, a control circuit400, a first digital-to-analog conversion circuit500, and a second digital-to-analog conversion circuit600. The equalizing circuit200is electrically connected to the matching circuit100, the amplification circuit300is electrically connected to the equalizing circuit200, the control circuit400is electrically connected to the amplification circuit300, the first digital-to-analog conversion circuit500is electrically connected between the control circuit400and the amplification circuit300, and the second digital-to-analog conversion circuit600is electrically connected between the control circuit400and the equalizing circuit200. In the operation mode M3, the matching circuit100provides impedance matching for the differential input signal Vin.

In some embodiments, in the first calibration mode M1, the control circuit400outputs a first digital signal S1, and the first digital-to-analog conversion circuit500generates a first differential calibration signal D1according to the first digital signal S1. The amplification circuit300generates a first amplified signal according to the first differential calibration signal D1, and feeds back the first amplified signal to the control circuit400to adjust the first digital signal S1, thereby reducing DC offset of the amplification circuit300.

In some embodiments, in the second calibration mode M2, the control circuit400outputs a second digital signal S2, and the second digital-to-analog conversion circuit600generates a second differential calibration signal D2according to the second digital signal S2. The equalizing circuit200and the amplification circuit300generate a second amplified signal according to the second digital signal S2, and feed back the second amplified signal to the control circuit400to adjust the second digital signal S2, thereby reducing DC offset of the equalizing circuit200.

In some embodiments, specifically, a transceiver (not shown) includes a receiver end and a transmitter end. The receiver end is configured to receive a radio frequency signal, and the transmitter end is configured to receive the radio frequency signal. The receiver end of the transceiver can independently operate in the form of a receiver. The matching circuit100, the equalizing circuit200, and the amplification circuit300are front-end circuits of the receiver. In some embodiments, the DC offset calibration system10is disposed at the receiver, and is configured to generate a corresponding amplified output signal Vout according to the differential input signal Vin, and output the amplified output signal Vout to other circuits of the receiver for processing. It should be noted that the first amplified signal and the second amplified signal are respectively the amplified output signals Vout in different embodiments. Accordingly, the DC offset calibration system10responds, by using the control circuit400, to the amplified output signal Vout fed back by the amplification circuit300, in the first calibration mode M1, adjusts the first digital signal S1by using the first digital-to-analog conversion circuit500, or in the second calibration mode M2, adjusts the second digital signal S2by using the second digital-to-analog conversion circuit600, to achieve the function of reducing the DC offset of the front-end circuit of the receiver.

In some embodiments, the DC offset calibration system10is further adapted to operate in an uncalibrated operation mode M0. As shown in the timing diagram inFIG. 3, the DC offset calibration system10sequentially operates in the uncalibrated operation mode M0, the first calibration mode M1, the second calibration mode M2, and the operation mode M3. Specifically, in the uncalibrated operation mode M0, the control circuit400does not output the first digital signal S1and the second digital signal S2. Accordingly, it may be considered that the control circuit400outputs the first digital signal S1and the second digital signal S2(for example, a digital signal with a voltage of 0) that are not calibrated.

In some embodiments, in the first calibration mode M1, when the first digital signal S1is equal to a first target signal T1, the control circuit400stops adjusting the first digital signal S1according to a fact that the first amplified signal is less than a first threshold (not shown), and is switched to operate in the second calibration mode M2. In the second calibration mode M2or the operation mode M3, the control circuit400outputs the first target signal T1, and the first digital-to-analog conversion circuit500generates the corresponding first differential calibration signal D1according to the first target signal T1. Specifically, in some embodiments, when the first amplified signal is less than the first threshold, it indicates that the control circuit400has reduced the DC offset of the amplification circuit300, so that the DC offset of the amplification circuit300will not significantly affect the amplified output signal Vout. In other words, in the second calibration mode M2or the operation mode M3, when the control circuit400outputs the first target signal T1, the first amplified signal may be made less than the first threshold, and the DC offset of the amplification circuit300may be ignored (for example, the DC offset of the amplification circuit300is reduced by about 80%). It should be particularly noted that the control circuit400can simultaneously output the first target signal T1and the second digital signal S2.

In some embodiments, in the second calibration mode M2, when the second digital signal S2is equal to a second target signal T2, the control circuit400stops adjusting the second digital signal S2according to a fact that the second amplified signal is less than a second threshold (not shown), and is switched to operate in the operation mode M3. In the operation mode M3, the control circuit400outputs the second target signal T2, and the second digital-to-analog conversion circuit600generates the corresponding second differential calibration signal D2according to the second target signal T2. Specifically, in some embodiments, when the second amplified signal is less than the second threshold, it indicates that the control circuit400has reduced the DC offset of the equalizing circuit200, so that the DC offset of the equalizing circuit200will not significantly affect the amplified output signal Vout. It should be particularly noted that since the DC offset of the amplification circuit300has been reduced via the first target signal T1, the second target signal T2is mainly used to reduce the DC offset of the equalizing circuit200. In other words, in the second calibration mode M2or the operation mode M3, when the control circuit400outputs the second target signal T2, the second amplified signal may be made less than the second threshold, and the DC offset of the equalizing circuit200may be ignored (for example, the DC offset of the equalizing circuit200is reduced by about 80%). It should be particularly noted that the control circuit400can simultaneously output the first target signal T1and the second target signal T2. Therefore, in some embodiments, in the second calibration mode M2, the control circuit400keeps outputting the first target signal T1. In the operation mode M3, the control circuit400keeps outputting the first target signal T1and the second target signal T2, to reduce the DC offset. In some embodiments, the control circuit400adjusts the first digital signal S1and the second digital signal S2by using a binary search algorithm.

In some embodiments, the DC offset calibration system10is switched from the uncalibrated operation mode M0to the first calibration mode M1according to a start signal. The start signal is, for example, but not limited to being received from outside or generated from inside of the DC offset calibration system10. When the DC offset calibration system10is switched from the uncalibrated operation mode M0to the first calibration mode M1, the control circuit400starts to adjust the first digital signal S1according to the first amplified signal until the first digital signal S1is adjusted to the first target signal T1. When the DC offset calibration system10is switched from the first calibration mode M1to the second calibration mode M2, the control circuit400starts to adjust the second digital signal S2according to the second amplified signal until the second digital signal S2is adjusted to the second target signal T2. Therefore, the control circuit400keeps outputting the first target signal T1. When the DC offset calibration system10is switched from the second calibration mode M2to the operation mode M3, the control circuit400keeps outputting the first target signal T1and the second target signal T2.

In some embodiments, the matching circuit100includes two matching input terminals110, two matching output terminals120, a fixed signal input terminal130, a terminal impedance element140, a common-mode impedance element150, a first switch160, and a second switch170. The terminal impedance element140is electrically connected between two matching input terminals110, the common-mode impedance element150is electrically connected between two matching output terminals120, the first switch160is electrically connected between two matching input terminals110and two matching output terminals120, and the second switch170is electrically connected between the fixed signal input terminal130and two matching output terminals120. The two matching input terminals110are configured to receive differential input signals Vin, the two matching output terminals120are configured to output differential matching output signals V1, and the fixed signal input terminal130is configured to receive a first fixed signal Vt1. In some embodiments, the matching circuit100further includes two capacitors180, one of the capacitors180is electrically connected between a positive terminal of the matching output terminal120and the first switch160, and the other capacitor180is electrically connected between the negative terminal of the matching output terminal120and the first switch160.

In some embodiments, in the first calibration mode M1, the first switch160electrically disconnects the two matching input terminals110from the two matching output terminals120, the second switch170electrically connects the fixed signal input terminal130to the two matching output terminals120, and the matching circuit100generates the differential matching output signal V1according to the first fixed signal Vt1.

In some embodiments, in the second calibration mode M2, the first switch160electrically disconnects the two matching input terminals110from the two matching output terminals120, the second switch170electrically connects the fixed signal input terminal130to the two matching output terminals120, and the matching circuit100generates the differential matching output signal V1according to the first fixed signal Vt1. It should be particularly noted that in the first calibration mode M1or the second calibration mode M2, the first switch160is turned off, so that the differential matching output signal V1is not affected by the differential input signal Vin. In addition, the second switch170is turned on, so that the matching circuit100can shield other interference signals externally input to the matching circuit100according to the first fixed signal Vt1.

In some embodiments, in the operation mode M3, the control circuit400outputs a digital operation signal. The first switch160electrically connects the two matching input terminals110to the two matching output terminals120, the second switch170electrically disconnects the fixed signal input terminal130from the two matching output terminals120, and the matching circuit100generates the differential matching output signal V1according to the differential input signal Vin.

In some embodiments, the terminal impedance element140includes a first terminal impedance element, a second terminal impedance element, and a terminal impedance fixed input terminal. The first terminal impedance element and the second terminal impedance element are electrically connected between the two matching input terminals110in series, and the terminal impedance fixed input terminal is located at the electrical connection between the first terminal impedance element and the second terminal element, and is configured to receive a second fixed signal Vt2. In some embodiments, the common-mode impedance element150includes a first common-mode impedance element, a second common-mode impedance element, and a common-mode impedance fixed input terminal. The first common-mode impedance element and the second common-mode impedance element are electrically connected between the two matching output terminals120in series, and the common-mode impedance fixed input terminal is located at the electrical connection between the first common-mode impedance element and the second common-mode impedance element, and is configured to receive a third fixed signal Vt3.

In some embodiments, when the two matching input terminals110receive an external fixed signal instead of the differential input signal Vin (for example, an adjustment current source is electrically connected to the two matching input terminals110to provide an adjustment current signal), the control circuit400can output an adjusted digital signal S0to adjust the terminal impedance element140. The terminal impedance element140includes a plurality of adjustable termination resistors and a plurality of normally-open termination resistors. The adjustable termination resistors can be adjusted to be turned on or off according to the adjusted digital signal S0(for example, the adjustable termination resistors are all open or all closed), and the normally-open termination resistors are normally turned on and are not affected by the adjusted digital signal S0. Accordingly, the control circuit400outputs the adjusted digital signal S0, the first switch160electrically disconnects the two matching input terminals110from the two matching output terminals120according to the adjusted digital signal S0, and the second switch170electrically connects the fixed signal input terminal130to the two matching output terminals120according to the adjusted digital signal S0. Therefore, the control circuit400can respectively obtain a full-off resistance value and a full-on resistance value of the terminal impedance element140according to the adjustment current signals received by the two matching input terminals110and positive and negative terminal voltages of the terminal impedance element140. Then, the control circuit400obtains an equation between the adjusted digital signal S0and the resistance value of the terminal impedance element140according to the full-off resistance value, the full-on resistance value, the number of adjustable termination resistors, and the number of normally-open termination resistors. The equation is as follows:

“Rl” is the full-on resistance value, “Rh” is the full-off resistance value, “Rt” is the resistance value of the terminal impedance element140, “X” represents a total number of adjustable termination resistors and normally-open termination resistors, “Y” represents a number of normally-open termination resistors, and “X−Y” represents a number of adjustable termination resistors. Specifically, Equation (1) can be obtained through derivation by using the following formulae:

When the adjustable termination resistors are all turned off according to the adjusted digital signal S0, “Vph” is a positive terminal voltage value of the terminal impedance element140, and “Vnh” is a negative terminal voltage value of the terminal impedance element140. When the adjustable termination resistors are all turned on according to the adjusted digital signal S0, “Vpl” is a positive terminal voltage value of the terminal impedance element140, and “Vnl” is a negative terminal voltage value of the terminal impedance element140. “It” is a current value of an adjusted current signal, “Rs” is a resistance value of an adjustable termination resistor or a resistance value of a normally-open termination resistor, and “Rp” is a resistance value of a parasitic resistor. In some embodiments, the parasitic resistance is mainly from a test instrument or a test circuit that measures the positive and negative terminal voltages of the terminal impedance element140. Specifically, Equation (4) can be obtained by subtracting Equation (3) from Equation (2). Therefore, Equation (1) can be obtained by substituting Equation (4) into Equation (5).

In some embodiments, when the adjusted digital signal S0output by the control circuit400is equal to the matching target signal T0, the matching circuit100adjusts, according to the matching target signal T0, a specific number of adjustable termination resistors to be turned on, and the matching circuit100provides impedance matching for the differential input signal Vin according to the number of turned-on adjustable termination resistors.

FIG. 4is a schematic diagram of a first multi-stage amplification circuit210according to some embodiments of the present invention.FIG. 5is a schematic diagram of a second multi-stage amplification circuit230according to some embodiments of the present invention.FIG. 6is a schematic diagram of an amplification circuit300according to some embodiments of the present invention. Referring toFIG. 2,FIG. 4,FIG. 5, andFIG. 6together, in some embodiments, the equalizing circuit200includes the first multi-stage amplification circuit210, a third switch220, a second multi-stage amplification circuit230, and a fourth switch240. The first multi-stage amplification circuit210includes a first primary amplification circuit212and a first secondary amplification circuit214. The first primary amplification circuit212includes two first primary amplification input terminals212A and two first primary amplification output terminals212B, and the first secondary amplification circuit214includes two first secondary amplification input terminals214A and two first secondary amplification output terminals214B. The two first primary amplification input terminals212A of the first primary amplification circuit212are electrically connected to two matching output terminals120of the matching circuit100, and the two first primary amplification output terminals212B of the first primary amplification circuit212are electrically connected to the two first secondary amplification input terminals214A of the first secondary amplification circuit214and the second digital-to-analog conversion circuit600.

In some embodiments, the second multi-stage amplification circuit230includes a second primary amplification circuit232and a second secondary amplification circuit234. The second primary amplification circuit232includes two second primary amplification input terminals232A and two second primary amplification output terminals232B, and the second secondary amplification circuit234includes two second secondary amplification input terminals234A and two second secondary amplification output terminals234B. The two second primary amplification input terminals232A of the second primary amplification circuit232are electrically connected to the two first secondary amplification output terminals214B of the first secondary amplification circuit214, and the two second primary amplification output terminals232B of the second primary amplification circuit232are electrically connected to the two second secondary amplification input terminals234A of the second secondary amplification circuit234, and the two second primary amplification output terminals234A of the second secondary amplification circuit234are electrically connected to the amplification circuit300. The third switch220is electrically connected between the two second primary amplification input terminals232A of the second primary amplification circuit232, and the fourth switch240is electrically connected between the two second primary amplification output terminals234A of the second secondary amplification circuit234.

In some embodiments, the first primary amplification circuit212generates a first primary differential output signal V2according to the differential matching output signal V1of the matching circuit100, and the first secondary amplification circuit214generates a first secondary differential output signal V3according to a second differential calibration signal D2(for example, a positive signal D2P and a negative signal D2N of the second differential calibration signal shown inFIG. 4) and the first primary differential output signal V2. The second primary amplification circuit232generates a second primary differential output signal V4according to the first secondary differential output signal V3of the first secondary amplification circuit214, and the second secondary amplification circuit234generates an equalized differential output signal V5(that is, a second secondary differential output signal) according to the second primary differential output signal V4. In some embodiments, the first multi-stage amplification circuit210is configured to compensate the high frequency band loss of the differential matching output signal V1, and the second multi-stage amplification circuit230is configured to enhance strength of the overall frequency band of the first secondary differential output signal V3.

In some embodiments, in the first calibration mode M1, the equalizing circuit200turns on the third switch220and the fourth switch240according to the first digital signal S1. In the second calibration mode M2, the equalizing circuit200turns off the third switch220and the fourth switch240according to the second digital signal S2. In the operation mode M3, the control circuit400outputs a digital operation signal. The equalizing circuit200turns off the third switch220and the fourth switch240according to the digital operation signal.

Referring toFIG. 4, in some embodiments, the first primary amplification circuit212includes a transistor M1, a transistor M2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a current source I1, and a current source I2. The transistor M1includes an output terminal P12, a control terminal P14, and a current terminal P16. The transistor M2includes an output terminal P22, a control terminal P24, and a current terminal P26. The control terminal P14and the control terminal P24are the two first primary amplification input terminals212A, and the output terminals P12and P22are two the first primary amplification output terminals212B. The resistor R1is electrically connected between an operating voltage terminal and the output terminal P12, and the resistor R2is electrically connected between the operating voltage terminal and the output terminal P22. The resistor R3is electrically connected between the current terminal P16and the current terminal P26, the capacitor C1is electrically connected between the current terminal P16and the current terminal P26, the current source I1is electrically connected between the current terminal P16and a ground terminal, and the current source I2is electrically connected between the current terminal P26and the ground terminal. The first secondary amplification circuit214includes a transistor M3, a transistor M4, a resistor R4, a resistor R5, a resistor R6, a capacitor C2, a current source I3, and a current source I4. The transistor M3includes an output terminal P32, a control terminal P34, and a current terminal P36. The transistor M4includes an output terminal P42, a control terminal P44, and a current terminal P46. The control terminal P34and the control terminal P44are the two second primary amplification input terminals232A, and the output terminal P32and the output terminal P42are the two second primary amplification output terminals232B. The circuit connection mode of the first secondary amplification circuit214is similar to that of the first primary amplification circuit212, and details are not described herein again.

Referring toFIG. 5, in some embodiments, the second primary amplification circuit232includes a transistor M5, a transistor M6, a resistor R7, a resistor R8, and a current source I5. The transistor M5includes an output terminal P52, a control terminal P54, and a current terminal P56. The transistor M6includes an output terminal P62, a control terminal P64, and a current terminal P66. The control terminal P54and the control terminal P64are the two second primary amplification input terminals232A, and the output terminal P52and the output terminal P62are the two second primary amplification output terminals232B. The resistor R7is electrically connected between an operating voltage terminal and the output terminal P52, the resistor R8is electrically connected between the operating voltage terminal and the output terminal P62, and the current source I1is electrically connected between the current terminal P56and the current terminal P66. The second secondary amplification circuit234includes a transistor M7, a transistor M8, a resistor R9, a resistor R10, and a current source I6. The transistor M7includes an output terminal P72, a control terminal P74, and a current terminal P76. The transistor M8includes an output terminal P82, a control terminal P84, and a current terminal P86. The control terminal P74and the control terminal P84are the two second secondary amplification input terminals234A, and the output terminal P72and the output terminal P82are the two second secondary amplification output terminals234B. The circuit connection mode of the second secondary amplification circuit234is similar to that of the second primary amplification circuit232, and details are not described herein again.

Referring toFIG. 2andFIG. 6together, in some embodiments, the amplification circuit300includes a load circuit310, a first current source320, a second current source330, a first transistor340, a second transistor350, a third transistor360, and a fourth transistor370. The load circuit310includes a first load terminal312, a second load terminal314, and an operating voltage terminal. The first transistor340includes a first output terminal342, a first control terminal344, and a first current terminal346. The second transistor350includes a second output terminal352, a second control terminal354, and a second current terminal356. The third transistor360includes a third output terminal362, a third control terminal364, and a third current terminal366. The fourth transistor370includes a fourth output terminal372, a fourth control terminal374, and a fourth current terminal376. The first output terminal342is electrically connected to the first load terminal312, the first control terminal344is electrically connected to the first digital-to-analog conversion circuit500, and the first current terminal346is electrically connected to the first current source320. The second output terminal352is electrically connected to the second load terminal314, the second control terminal354is electrically connected to one of two second primary amplification input terminals234A of the equalizing circuit200, and the second current terminal356is electrically connected to the first current source320. The third output terminal362is electrically connected to the first output terminal342, the third control terminal354is electrically connected to the first digital-to-analog conversion circuit500, and the third current terminal356is electrically connected to the second current source330. The fourth output terminal372is electrically connected to the second output terminal352, the fourth control terminal374is electrically connected to the other of two second primary amplification input terminals234A of the equalizing circuit200, and the fourth current terminal376is electrically connected to the second current source330. The amplification circuit300generates the amplified output signal Vout at the second load terminal314by receiving the first differential calibration signal D1(for example, a positive signal D1P and a negative signal D1N of the first differential calibration signal shown inFIG. 6) at the first control terminal344and the fourth control terminal374and by receiving the equalized differential output signal V5(for example, a positive signal V5P and a negative signal V5N of the equalized differential output signal shown inFIG. 6) of the equalizing circuit200at the second control terminal354and the third control terminal364.

It should be particularly noted that, in some embodiments, in the first calibration mode M1, the equalizing circuit200turns on the third switch220and the fourth switch240. Accordingly, there are short circuits between the two second primary amplification input terminals232A of the second multi-stage amplification circuit230and between the two second primary amplification output terminals234A of the second secondary amplification circuit234, so that the equalized differential output signal V5output by the equalizing circuit200is equal to a common-mode voltage signal, that is, the second control terminal354and the third control terminal364receive the same common-mode voltage signal. Therefore, the common-mode voltage signal can adjust the output amplified output signal Vout according to the first differential calibration signal D1received by the first control terminal344and the fourth control terminal374.

FIG. 7is a schematic diagram of a first digital-to-analog conversion circuit500according to some embodiments of the present invention. Referring toFIG. 7, in some embodiments, the first digital-to-analog conversion circuit500includes a first decoding circuit510, a first current mirror circuit520, a set of first transistors530, a set of second transistors540, a first R-2R ladder network resistance circuit550, and a second R-2R ladder network resistance circuit560. The set of first transistors530includes a set of first output terminals532, a set of first control terminals534, and a set of first current terminals536, and the set of second transistors540includes a set of second output terminals542, a set of second control terminals544, and a set of second current terminals546. The first decoding circuit510is electrically connected to the control circuit400, the first R-2R ladder network resistance circuit550is electrically connected between an operating voltage terminal and the set of first output terminals532, the set of first control terminals534is electrically connected to the first decoding circuit510, the set of first current terminals536is electrically connected to the first current mirror circuit520, the second R-2R ladder network resistance circuit560is electrically connected between the operating voltage terminal and the set of second output terminals542, the set of second control terminals544is electrically connected to the first decoding circuit510, and the set of second current terminals546is electrically connected to the first current mirror circuit520.

FIG. 8is a schematic diagram showing a relationship between a first digital signal S1and a first differential calibration signal D1according to some embodiments of the present invention. Referring toFIG. 7andFIG. 8, in some embodiments, the first decoding circuit510generates a set of first positive decoded signals SS1P [M:0] and a set of first negative decoded signals S1N [M:0] according to the first digital signal S1. According to the set of first positive decoded signals S1P [M:0] received by the set of first control terminals534and the set of first negative decoded signals S1N [M:0] received by the set of second control terminals544, the first current mirror circuit520, the set of first transistors530, the set of second transistors540, the first R-2R ladder network resistance circuit550, and the second R-2R ladder network resistance circuit560generate a positive signal D1P of the first differential calibration signal at the set of first output terminals532, and generate a negative signal DIN of the first differential calibration signal at the set of second output terminals542. Specifically, the first differential calibration signal D1includes the positive signal D1P of the first differential calibration signal and the negative signal DIN of the first differential calibration signal. In some embodiments, when the first differential calibration signal D1is a voltage signal, the relationship between the first digital signal S1and the positive signal D1P and the negative signal DIN of the first differential calibration signal is shown inFIG. 8.

FIG. 9is a schematic diagram of a second digital-to-analog conversion circuit600according to some embodiments of the present invention. Referring toFIG. 9, in some embodiments, the second digital-to-analog conversion circuit600includes a second decoding circuit610, a second current mirror circuit620, a fifth transistor630, and a sixth transistor640. The second current mirror circuit620includes a reference transistor622, a plurality of mirror transistors624, and a plurality of mirror switch elements626. The reference transistor622includes a reference current terminal622A, a reference control terminal622B, and a reference ground terminal622C. Each of the mirror transistors624includes a mirror current terminal624A, a mirror control terminal624B, and a mirror ground terminal624C. The fifth transistor630includes a fifth output terminal632, a fifth control terminal634, and a fifth current terminal636, and the sixth transistor640includes a sixth output terminal642, a sixth control terminal644, and a sixth current terminal646. The second decoding circuit610is electrically connected to a control circuit400, the reference current terminal622A is electrically connected to the reference control terminal622B, and the mirror switch elements626are in a one-to-one correspondence with the mirror transistors624. Each of the mirror switch elements626is electrically connected between the reference control terminal622B of the reference transistor622and the mirror control terminal624B of the corresponding mirror transistor624, and the mirror current terminal624A of each of the mirror transistors624is electrically connected to the fifth current terminal636of the fifth transistor630and the sixth current terminal646of the sixth transistor640. The fifth output terminal632is electrically connected to the control terminal P34of the equalizing circuit200, the fifth control terminal634is electrically connected to the second decoding circuit610, the sixth output terminal642is electrically connected to the control terminal P44of the equalizing circuit200, and the sixth control terminal644is electrically connected to the second decoding circuit610.

FIG. 10is a schematic diagram showing a relationship between a second digital signal S2and a second differential calibration signal D2according to some embodiments of the present invention. Referring toFIG. 9andFIG. 10, in some embodiments, the second decoding circuit610generates a set of second positive decoded signals S2P [N:0] and a set of second negative decoded signals S2N [N:0] according to the second digital signal S2. The set of second positive decoded signals S2P [N:0] includes a plurality of sub-signals (for example, S2P [N], S2P [N−1], . . . , S2P [0]). Each of the mirror switch elements626is in a one-to-one correspondence with each of the sub-signals in the set of second positive decoded signals S2P [N:0], in other words, each of the mirror switch elements626is turned on or off respectively in response to one corresponding sub-signal in the set of second positive decoded signals S2P [N:0], and the second current mirror circuit620controls currents supplied to the fifth transistor630and the sixth transistor640according to the number of mirror switch elements626that are turned on. According to one of the sub-signals in the set of second positive decoded signals S2P [N:0] received at the fifth control terminal634, one of the sub-signals in the set of second negative decoded signals S2N [N:0] received at the sixth control terminal644, and the current provided by the second current mirror circuit620, the fifth transistor630and the sixth transistor640generate a positive signal D2P of the second differential calibration signal at the fifth output terminal632, and generate a negative signal D2N of the second differential calibration signal at the sixth output terminal642.

It should be particularly noted that, in some embodiments, the mirror switch element626corresponding to the sub-signal S2P [N] can always be set to turn-on, the fifth control terminal634receives the sub-signal S2P [N] in the set of second positive decoded signals S2P [N:0], and the sixth control terminal644receives the sub-signal S2N [N] in the set of second negative decoded signals S2N [N:0]. In some embodiments, the second differential calibration signal D2is a current signal. Specifically, the second differential calibration signal D2includes the positive signal D2P of the second differential calibration signal and the negative signal D2N of the second differential calibration signal. In some embodiments, when the second differential calibration signal D2is the current signal, the relationship between the second digital signal S2and the positive signal D2P and the negative signal D2N of the second differential calibration signal is shown inFIG. 10.

FIG. 11is flowchart of a DC offset calibration method according to some embodiments of the present invention. Referring toFIG. 1andFIG. 11, in some embodiments, the DC offset calibration method is adapted to operate in one of an operation mode, a first calibration mode, and a second calibration mode. The DC offset calibration method includes: an operation mode step (step S100), a first calibration mode step (step S200), and a second calibration mode step (step S300). In the operation mode, the operation mode step (step S100) includes: providing, by a matching circuit100, impedance matching for a differential input signal Vin (step S110). In the first calibration mode M1, the first calibration mode step (step S200) includes: outputting, by a control circuit400, a first digital signal S1(step S210); generating, by a first digital-to-analog conversion circuit500, a first differential calibration signal D1according to the first digital signal S1(step S220); and generating, by an amplification circuit300, a first amplified signal according to the first differential calibration signal D1, and feeding back the first amplified signal to the control circuit400to adjust the first digital signal S1, thereby reducing DC offset of the amplification circuit300(step S230). In the second calibration mode M2, the second calibration mode step (step S300) includes: outputting, by the control circuit400, a second digital signal S2(step S310); generating, by a second digital-to-analog conversion circuit600, a second differential calibration signal D2according to the second digital signal S2(step S320); and generating, by an equalizing circuit200and the amplification circuit300, a second amplified signal according to the second digital signal S2, feeding back the second amplified signal to the control circuit400to adjust the second digital signal S2, thereby reducing DC offset of the equalizing circuit200(step S330).

Still referring toFIG. 2, in some embodiments, the DC offset calibration method further includes a matching circuit control method. The matching circuit control method controls the differential matching output signal V1output by the matching circuit100, and includes: in the first calibration mode M1: electrically disconnecting the two matching input terminals110from the two matching output terminals120according to the first digital signal S1; electrically connecting the fixed signal input terminal130to the two matching output terminals120according to the first digital signal S1; and outputting the differential matching output signal V1at the two matching output terminals120according to the fixed signal (that is, a first fixed signal Vt1); and in the second calibration mode M2: electrically disconnecting the two matching input terminals110from the two matching output terminals120according to the second digital signal S2; electrically connecting the fixed signal input terminal130to the two matching output terminals120according to the second digital signal S2; and outputting the differential matching output signal V1at the two matching output terminals120according to the fixed signal (that is, the first fixed signal Vt1).

Based on the above, according to the DC offset calibration system and method provided by some embodiments of the present invention, the control circuit, the first digital-to-analog conversion circuit, and the second digital-to-analog conversion circuit can be used to calibrate the DC offset during processing of the differential input signal by the matching circuit, the equalizing circuit, and the amplification circuit. In the first calibration mode, the control circuit adjusts the output first digital signal according to the amplified signal fed back by the amplification circuit, and the first digital-to-analog conversion circuit outputs the first differential calibration signal to the amplification circuit according to the first digital signal, to adjust the DC offset. In the second calibration mode, the control circuit adjusts the output second digital signal according to the amplified signal fed back by the amplification circuit, and the second digital-to-analog conversion circuit outputs the second differential calibration signal to the equalizing circuit according to the second digital signal, to adjust the DC offset. In the operation mode, the matching circuit can provide impedance matching for the differential input signal. Therefore, the DC offset calibration system can eliminate the DC offset.