Phase change memory devices having buried metal silicide patterns

A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2011-0062031 filed on Jun. 27, 2011, in the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference.

BACKGROUND

Example embodiments relate to phase change memory devices and methods of manufacturing the same.

2. Description of the Related Art

In a phase change memory device, data may be stored using a resistance difference generated when a phase change material pattern undergoes a phase transition between an amorphous state and a crystalline state. The phase change memory device may include a switching device, e.g., a P-N diode or a transistor. A cell of the phase change memory device may be downsized when a P-N diode is employed as the switching device instead of a transistor.

SUMMARY

Example embodiments may provide phase change memory devices having improved operational characteristics.

Example embodiments may provide methods of manufacturing phase change memory devices having improved operational characteristics.

Example embodiments may provide a phase change memory device, including an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

The substrate may be divided into the active region and an isolation region by an isolation layer pattern, the metal silicide pattern contacting a sidewall of the isolation layer pattern.

Bottom surfaces of the metal silicide pattern and the impurity region may be coplanar with each other.

A bottom surface of the impurity region may be lower than that of the metal silicide pattern.

The metal silicide pattern may include two metal silicide patterns at opposite lateral portions of the impurity region, the two metal silicide patterns being spaced apart from each other.

The metal silicide pattern may include cobalt silicide or nickel silicide.

The impurity region may be a word line extending in a second direction.

The metal silicide pattern may extend in the second direction.

The device may further include a bit line electrically connected to the upper electrode, the bit line extending in a first direction perpendicular to the second direction.

An upper surface of the metal silicide pattern may be between upper and bottom surfaces of the impurity region, the upper surface of the metal silicide pattern facing away from the substrate.

Example embodiments may also provide a phase change memory device, including an impurity region in an upper portion of a substrate, the impurity region being a word line, a metal silicide pattern inside the impurity region, an upper surface of the metal silicide pattern being spaced a predetermined distance from an upper surface of the impurity region, a diode on the upper surface of the impurity region, the upper surfaces of the metal silicide pattern and the impurity region facing the diode, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.

The device may further include an isolation layer pattern through the impurity region, the metal silicide pattern contacting the isolation layer pattern.

The device may further include an isolation layer pattern defining the active region, the impurity region extending in the entire active region, and the metal silicide pattern contacting the isolation layer pattern.

Example embodiments may also provide a method of manufacturing a phase change memory device, the method including forming an impurity region on a substrate, the impurity region being in an active region, forming a metal silicide pattern at least partially buried in the impurity region, forming a diode on the impurity region, forming a lower electrode on the diode, forming a phase change layer pattern on the lower electrode, and forming an upper electrode on the phase change layer pattern.

The method may further include forming a plurality of trenches by partially etching the substrate, forming a first isolation layer pattern partially filling the trenches, forming a spacer on sidewalls of the trenches, removing an upper portion of the first isolation layer pattern to expose a portion of the substrate between the spacer and the first isolation layer pattern, transforming the exposed portion of the substrate into the metal silicide pattern, and implanting impurities into an upper portion of the substrate to form the impurity region.

Transforming the exposed portion of the substrate into the metal silicide pattern may include forming a metal layer on the spacer, the exposed portion of the substrate, and the first isolation layer pattern, and reacting the metal layer with the exposed portion of the substrate.

After reacting the metal layer with the exposed portion of the substrate, the method may further include removing an unreacted portion of the metal layer, removing the spacer, and forming a second isolation layer pattern filling a remaining portion of the trench.

The metal layer may be formed using cobalt and/or nickel.

Bottom surfaces of the metal silicide pattern and the impurity region may be formed to be coplanar with each other.

The method may further include forming an upper electrode on the phase change layer pattern, and forming a bit line electrically connected to the upper electrode, the bit line extending in a first direction, and the impurity region and the metal silicide pattern extending in a second direction perpendicular to the first direction.

DETAILED DESCRIPTION

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Further, it will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may also be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “adjacent” versus “directly adjacent”, etc.). Like numerals refer to like elements throughout.

FIGS. 1A and 1Bare cross-sectional views of phase change memory devices in accordance with example embodiments.

Referring toFIG. 1A, a phase change memory device may include a substrate100, an impurity region135, a metal silicide pattern130, a P-N diode149, a lower electrode156, a phase change layer pattern160, and an upper electrode165. The phase change memory device may further include a bit line180electrically connected to the upper electrode165.

The substrate100may include, e.g., a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. The substrate100may be divided into an active region I and an isolation region II by an isolation layer pattern125. A portion of the substrate100on which the isolation layer pattern125is formed may be defined as the isolation region II, and a portion of the substrate100not including the isolation layer pattern125may be defined as the active region I.

The impurity region135may be formed at an upper portion of the substrate100in the active region I. In example embodiments, the impurity region135may be formed between adjacent isolation layer patterns125, and may extend in a second direction. A plurality of the impurity regions135may be formed regularly along a first direction substantially perpendicular to the second direction, e.g., the impurity regions135may be spaced apart from each other along the first direction. In example embodiments, the impurity region135in the active region I may serve as a word line.

The metal silicide pattern130may be formed at a lateral portion of the impurity region135to make contact with a sidewall of the isolation layer pattern125. In example embodiments, a pair of the metal silicide patterns130may be formed individually at both lateral portions, e.g., at opposing ends, of the impurity region135to contact different isolation layer patterns125. For example, a metal silicide pattern130between a first isolation layer pattern125and a second isolation layer pattern125may include first and second metal silicide patterns130at the opposing ends to contact the first and second isolation layer patterns125, respectively. The metal silicide pattern130may not contact a top surface, i.e., a surface facing away from the substrate100, of the impurity region135, e.g., a portion of the impurity region135may separate the metal silicide pattern130from an overlying layer, e.g., from a first interlayer insulating layer140on the impurity region140. For example, bottom surfaces131bof the metal silicide pattern130and bottom surfaces136bof the impurity region135may be coplanar with each other. As illustrated inFIG. 1A, the bottom surfaces131band136bare surfaces facing the substrate100. For example, at least a portion of the metal silicide pattern130may be buried or embedded inside the impurity region135. Thus, the word line, i.e., the impurity region135, of the phase change memory device may have reduced electrical resistance.

In one example embodiment, the bottom surface131bof the metal silicide pattern130may be higher than that of the impurity region135. That is, the metal silicide pattern130may be completely embedded within the impurity region135, so each of an upper surface131aand the bottom surface131bof the metal silicide pattern130is spaced apart from respective upper and bottom surfaces136a,136bof the impurity region135.

According to example embodiments illustrated inFIG. 1A, the two metal silicide patterns130spaced apart from each other along the first direction may be formed individually at both lateral portions of the impurity region135. However, in other example embodiments, the two metal silicide patterns may be connected to each other. For example, as illustrated inFIG. 1B, a single metal silicide pattern130amay extend between two adjacent isolation layer patterns125to contact each of the isolation layer patterns125. For example, the metal silicide pattern130amay be disposed under an impurity region135bin the active region I, e.g., the metal silicide pattern130amay be between the impurity region135band the substrate100, as illustrated inFIG. 1B. In another example, the metal silicide pattern130amay be disposed between two impurity regions in an upper portion of the active region I.

The P-N diode149may be disposed on the impurity region135through the first insulating interlayer140. The first insulating interlayer140may be formed on the substrate100and the isolation layer pattern125.

The P-N diode149may include a first conductive pattern147aand a second conductive pattern147bsequentially stacked on the impurity region135. For example, the first conductive pattern147amay include N-type impurities and the second conductive pattern147bmay include P-type impurities. In one example embodiment, an ohmic pattern (not illustrated) including, e.g., a metal silicide, may be further disposed on the second conductive pattern147b.

The lower electrode156may be disposed on the second conductive pattern147bthrough a second insulating interlayer150formed on the first insulating interlayer140. A spacer154enclosing a sidewall of the lower electrode156may be further formed. The lower electrode156may function as a heater converting a current to a Joule-heat. A contact area between the lower electrode156and the second conductive pattern147bmay be decreased by the spacer154so that a heating efficiency may be increased. In example embodiments, the spacer154may include silicon nitride. The lower electrode156may include a metal nitride or a metal silicon nitride, e.g., titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, tantalum nitride, tantalum silicon nitride, zirconium nitride, zirconium silicon nitride, etc.

The phase change layer pattern160may be disposed on the lower electrode156and the spacer154, and the upper electrode165may be disposed on the phase change layer pattern160. The phase change layer pattern160may include a phase change material that may undergo a phase-transition by the Joule-heat from the lower electrode156. The phase change material may include a chalcogen compound or a chalcogen compound doped with carbon, nitrogen and/or a metal. The chalcogen compound may include, e.g., at least one of GeSbSe, SbSe, GeSbTe, SbTe, GeSb, AsSbTe, SnSbTe, SnInSbTe, etc. These may be used alone or in a mixture thereof. The upper electrode165may include doped polysilicon, a metal, a metal nitride, and/or a metal silicide, etc.

A third insulating interlayer170covering the upper electrode165and the phase change layer pattern160may be formed on the second insulating interlayer150. An upper electrode contact175may make contact with the upper electrode165through the third insulating interlayer170. The bit line180may be disposed on the third insulating interlayer170to be electrically connected to the upper electrode165via the upper electrode contact175. In example embodiments, the bit line180may extend in the first direction.

FIG. 2is a cross-sectional view of a phase change memory device in accordance with some example embodiments. The phase change memory device ofFIG. 2may have a construction substantially the same as or similar to that of the phase change memory device ofFIG. 1A, except for shapes of the lower electrode and the phase change layer pattern. Thus, detailed descriptions of same elements will not be repeated herein.

Referring toFIG. 2, a lower electrode254amay partially fill a first contact hole252formed through a second insulating interlayer250to make contact with the second conductive pattern147b. The lower electrode254amay not be surrounded by a spacer unlike the lower electrode156ofFIG. 1A. In example embodiments, a bottom surface of the lower electrode254amay be smaller than a top surface of the second conductive pattern147b.

A phase change layer pattern260filling a remaining portion of the first contact hole252may be disposed on the lower electrode254a.

An upper electrode265may be disposed on the second insulating interlayer250to make contact with the phase change layer pattern260. A third insulating interlayer270covering the upper electrode265may be disposed on the second insulating interlayer250. An upper electrode contact275may be disposed on the upper electrode265through the third insulating interlayer270. A bit line280may be disposed on the third insulating interlayer270to be electrically connected to the upper electrode265via the upper electrode contact275.

While two metal silicide patterns130at both lateral portions of the impurity region135are illustrated inFIG. 2, the metal silicide patterns may be also connected to each other as illustrated inFIG. 1B. As described above, the metal silicide pattern130may be at least partially buried or embedded in the impurity region135that may serve as a word line of the phase change memory device. Thus, a cell resistance between the P-N diode149and the word line may be reduced. As the cell resistance decreases, a current may easily flow from the P-N diode149to the lower electrodes156and254a, and from the lower electrodes156and254ato the phase change layer patterns160and260by a small voltage. Further, the phase change memory device may have small cell current distributions and enhanced operational characteristics.

FIGS. 3 to 22are cross-sectionals views of stages in a method of manufacturing phase change memory devices in accordance with example embodiments.

Referring toFIG. 3, a mask layer104may be formed on the substrate100, e.g., a semiconductor substrate. For example, the substrate100may include a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

The mask layer104may be formed using, e.g., silicon nitride. The mask layer104may be formed by a chemical vapor deposition (CVD) process, a low pressure vapor deposition process (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, etc.

In one example embodiment, a pad oxide layer (not illustrated) may be further formed between the substrate100and the mask layer104. The pad oxide layer may prevent the mask layer104from directly transferring a stress to the substrate100. The pad oxide layer may be formed by performing a thermal oxidation process on the substrate100.

Referring toFIG. 4, the mask layer104may be partially etched by, e.g., a photolithography process to form a mask104a. In example embodiments, a plurality of the masks104amay be spaced apart from each other along the first direction. Each mask104amay extend in the second direction.

Referring toFIG. 5, an upper portion of the substrate100may be etched using the mask104aas an etching mask to form a plurality of first trenches106. The first trench106may be defined by sidewalls of the mask104aand an etched top surface of the substrate100. The substrate100may be divided into the active region I and the isolation region II by forming the first trenches106. A portion of the substrate100including the first trench106may be defined as the isolation region II, and a portion of the substrate100not including the first trench106may be defined as the active region I.

Referring toFIG. 6, an isolation layer110filling each first trench106may be formed on the substrate100. In example embodiments, an oxide layer sufficiently filling the first trenches106may be formed on the substrate100and the mask104a. The oxide layer may be formed using silicon oxide, e.g., a Middle-Temperature Oxide (MTO), a HDP oxide, a CVD oxide, etc. An upper portion of the oxide layer may be planarized until a top surface of the mask104ais exposed to form the isolation layer110. The planarization process may include a chemical mechanical polishing (CMP) process and/or an etch-back process.

Referring toFIG. 7, an upper portion of the isolation layer110may be removed by, e.g., an etch-back process or a wet etching process using a hydrofluoric acid (HF) solution or a buffer oxide etchant (BOE) solution to form a first isolation layer pattern110a. In example embodiments, a top surface of the first isolation layer pattern110amay be lower than that of the substrate100. A remaining portion of the first trench106, i.e., a portion of the first trench106above the first isolation layer pattern110aand after forming the first isolation layer pattern110a, may be referred to as a second trench106a, hereinafter.

Referring toFIG. 8, a first spacer115may be formed on a sidewall of the second trench106a. In example embodiments, a first spacer layer may be formed along the sidewall of the second trench106a, the mask104a, and the first isolation layer pattern110a. The first spacer layer may be anisotropically etched to form the first spacer115. The first spacer layer may be formed using silicon nitride by, e.g., a CVD process, a PECVD process, a LPCVD process.

Referring toFIG. 9, an upper portion of the first isolation layer pattern110amay be removed to form a third trench106b. Accordingly, a lateral portion of the active region of the substrate100may be partially exposed between the first spacer115and the first isolation layer pattern110a. In example embodiments, the upper portion of the first isolation layer pattern110amay be removed by, e.g., an etch-back process or a wet etching process using a HF solution or a BOE solution.

Referring toFIG. 10, a metal layer120may be formed conformally on the mask104a, the first spacer115, an exposed surface of the substrate100, and the first isolation layer pattern110a. In example embodiments, the metal layer120may be formed using, e.g., cobalt (Co) or nickel (Ni). The metal layer120may be obtained by, e.g., a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a sputtering process, etc.

Referring toFIG. 11A, the metal layer120may be reacted with the lateral portion of the active region of the substrate100to form a metal silicide pattern130. For example, the metal silicide pattern130may be formed by a silicidation process through a thermal treatment, e.g., a rapid thermal annealing (RTA). In the case that the metal layer120includes cobalt, the metal silicide pattern130may include cobalt silicide. In the case that the metal layer120includes nickel, the metal silicide pattern130may include nickel silicide.

A portion of the substrate100which is covered by the first spacer115may not be reacted with the metal layer120. Thus, the first spacer115may function as a reaction prevention layer. A portion of the metal layer120which is not reacted with the substrate100may remain on the mask104aand the first spacer115.

As illustrated inFIG. 11A, the lateral portion of the substrate100not covered by the first spacer115may be partially transformed into the metal silicide pattern130. Alternatively, the lateral portion of the substrate100not covered by the first spacer115may be entirely transformed into a metal silicide pattern130a, as illustrated inFIG. 11B.

Hereinafter, subsequent processes are described using a construction illustrated inFIG. 11A.

Referring toFIG. 12, the remaining metal layer120and the first spacer115may be removed to form a fourth trench106c. The metal layer120may be removed by, e.g., a strip process or a wet etching process using an etching solution that may include hydrogen peroxide and an acidic solution. The first spacer115may be removed by, e.g., a strip process.

Referring toFIG. 13, a second isolation layer pattern filling the fourth trench106cmay be formed on the first isolation layer pattern110a. In example embodiments, an oxide layer including an oxide substantially the same as that of the first isolation layer pattern110amay be formed on the mask104aand the first isolation layer pattern110ato sufficiently fill the fourth trench106c. An upper portion of the oxide layer may be planarized by, e.g., a CMP process and/or an etch-back process, until the top surface of the mask104ais exposed to form the second isolation layer pattern. The second isolation layer pattern may be merged with the first isolation layer pattern110ato form an isolation layer pattern125. In the case that the second isolation layer pattern includes a different material from that of the first isolation layer pattern110a, the first and second isolation layer patterns may exist as individual or independent structures.

Referring toFIG. 14, the mask104amay be removed by, e.g., an etch-back process, such that an upper portion of the isolation layer pattern125may be exposed. An ion implantation process may be performed to form an impurity region135at an upper portion of the substrate100. In example embodiments, a plurality of the impurity regions135may be formed to be spaced apart from each other in the first direction and each impurity region135may extend in the second direction. The impurity region135may serve as a word line of the phase change memory device.

In example embodiments,136b,131bsurfaces of the impurity region135and the metal silicide pattern130may be coplanar with each other, e.g., a bottom surface of each of the impurity region135and the metal silicide pattern130may be directly on an upper surface of the substrate100. Alternatively, the impurity region135may have a bottom surface136bsubstantially lower than that of the metal silicide pattern130, e.g., so the bottom surfaces136bof the impurity region135may be directly on the substrate and the bottom surface131bof the metal silicide pattern130may be between the bottom and upper surfaces136b,136aof the impurity region135.

Referring toFIG. 15, an upper portion of the isolation layer pattern125may be planarized, such that top surfaces of the isolation layer pattern125and the impurity region135may be coplanar, e.g., substantially level, with each other. The first insulating interlayer140may be formed on the impurity region135and the isolation layer pattern125. The first insulating interlayer140may be formed using, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, etc. The first insulating interlayer140may be obtained by, a CVD process, a PECVD process, a spin coating process, a HDP-CVD process, etc.

Alternatively, the planarization process for the isolation layer pattern125may be omitted. For example, the first insulating interlayer140may be formed using silicon oxide on the impurity region135and the isolation layer pattern125. In this case, the first insulating interlayer140and the isolation layer pattern125may be merged with each other.

Referring toFIG. 16, the first insulating interlayer140may be partially removed by, e.g., a photolithography process, to form an opening145at least partially exposing the impurity region135.

Referring toFIG. 17, a conductive layer147filling the opening145may be formed on the impurity region135. In example embodiments, a selective epitaxial growth (SEG) process may be performed using the impurity region135as a seed to form the conductive layer147filling the opening145. A planarization process may be further performed on the conductive layer147, such that top surfaces of the conductive layer147and the first insulating interlayer140may be coplanar with each other.

If the metal silicide pattern130is exposed at the top surface of the impurity region135, the number of the seed sites may be decreased during the SEG process. Accordingly, an irregular growth of the conductive layer147may be caused, and thus the conductive layer147may include defects therein. Therefore, according to example embodiments, the metal silicide pattern130may be buried within the impurity region135, e.g., at a predetermined distance under the upper surface of the impurity region135, so that the metal silicide pattern130may not be exposed during the SEG process. That is, as illustrated inFIG. 1A, the upper surface131aof the metal silicide pattern130may be formed between the upper and lower surfaces136aand136bof the impurity region135to ensure that the upper surface131aof the metal silicide layer130is spaced apart a predetermined distance from the upper surface136aof the impurity region135. Therefore, a generation of the defects or the irregular growth of the conductive layer147may be prevented or substantially minimized.

Referring toFIG. 18, impurities may be implanted into the conductive layer147to form the first conductive pattern147aand the second conductive pattern147bsequentially stacked on the impurity region135. The first and second conductive patterns147aand147bmay include different types of the impurities from each other. For example, N-type impurities may be implanted into the conductive layer147to form the first conductive pattern147adoped with the N-type impurities, and P-type impurities may be implanted into an upper portion of the conductive layer147to form the second conductive pattern147bdoped with the P-type impurities. Accordingly, a P-N diode149may be formed in the opening145.

In one example embodiment, a silicidation process may be further performed on the P-N diode149to form an ohmic pattern (not illustrated) thereon. The ohmic pattern may include a metal silicide.

Referring toFIG. 19, the second insulating interlayer150may be formed on the first insulating interlayer140and the P-N diode149. The second insulating interlayer150may be formed using, e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., by, e.g., a CVD process, a PECVD process, a spin coating process, a HDP-CVD process. The second insulating interlayer150may be partially etched to form a first contact hole152exposing the second conductive layer pattern147b.

Referring toFIG. 20, the second spacer154may be formed on a sidewall of the first contact hole152, and the lower electrode156filling a remaining portion of the first contact hole152may be formed on the second conductive pattern147b.

In example embodiments, a second spacer layer may be formed along the second insulating interlayer150, an inner wall of the first contact hole152, and the second conductive pattern147busing, e.g., silicon nitride. The second spacer layer may be partially removed by an etch-back process or an anisotropic etching process to form the second spacer154. A lower electrode layer sufficiently filling the first contact hole152may be formed on the second conductive pattern147b. An upper portion of the lower electrode layer150may be planarized by a CMP process and/or an etch-back process until a top surface of the second insulating interlayer150is exposed to form the lower electrode156.

As described above, the second spacer154may be formed before forming the lower electrode156. Thus, contact areas between the lower electrode156and the second conductive pattern147b, and between the lower electrode156and a phase change layer pattern160(seeFIG. 21) may be reduced to improve a heating efficiency of the phase change layer pattern160.

The lower electrode layer may be formed using a metal nitride or a metal silicon nitride, e.g., at least one of titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, tantalum nitride, tantalum silicon nitride, zirconium nitride, zirconium silicon nitride, etc. The lower electrode layer may be obtained by, e.g., an ALD process, a PVD process, a sputtering process.

Referring toFIG. 21, a phase change layer and an upper electrode layer may be sequentially formed on the lower electrode156, the second spacer154, and the second insulating interlayer150. The upper electrode layer and the phase change layer may be patterned to form the upper electrode165and the phase change layer pattern160connected to the lower electrode156.

In example embodiments, the phase change layer may be formed using a chalcogen compound or a chalcogen compound doped with carbon, nitrogen and/or a metal. The chalcogen compound may include, e.g., at least one of GeSbSe, SbSe, GeSbTe, SbTe, GeSb, AsSbTe, SnSbTe, SnInSbTe, etc. These may be used alone or in a mixture thereof. The phase change layer may be obtained by a PVD process, a sputtering process, etc. The upper electrode layer may be formed using, e.g., doped polysilicon, a metal, a metal nitride or a metal silicide by a CVD process, an ALD process, a sputtering process, etc.

Referring toFIG. 22, the upper electrode contact175and the bit line180electrically connected to the upper electrode165via the upper electrode contact175may be formed. In example embodiments, the third insulating interlayer170covering the phase change layer pattern160and the upper electrode165may be formed on the second insulating interlayer150. The third insulating interlayer170may be partially removed to form a second contact hole (not illustrated) partially exposing the upper electrode165. A conductive layer sufficiently filling the second contact hole may be formed on the third insulating interlayer170and the upper electrode165. An upper portion of the conductive layer may be planarized to form the upper electrode contact165.

The bit line180may be formed on the third insulating interlayer170and the upper electrode contact175using, e.g., a metal, a metal nitride or doped polysilicon. In example embodiments, the bit line180may extend in the first direction.

FIGS. 23 to 27are cross-sectional views of stages in a method of manufacturing a phase change memory device in accordance with other example embodiments.

Referring toFIG. 23, processes substantially the same as or similar to those illustrated with reference toFIGS. 3 to 18may be performed. Accordingly, the impurity region135in which the metal silicide pattern130may be at least partially buried or embedded may be formed at the upper portion of the substrate100. The P-N diode149may be formed on the impurity region135through the first insulating interlayer140.

Referring toFIG. 24, a second insulating interlayer250may be formed on the first insulating interlayer140and the second conductive pattern147bof the P-N diode149. The second insulating interlayer250may be partially removed to form a first contact hole252partially exposing the second conductive pattern147b. A lower electrode layer sufficiently filling the fist contact hole252may be formed on the second conductive pattern147band the second insulating interlayer250. An upper portion of the lower electrode layer may be planarized to form the lower electrode254. In example embodiments, the lower electrode254may have a cross-section smaller than a top surface of the second conductive pattern147b.

Referring toFIG. 25, the upper portion of the lower electrode254may be removed by a dry etching process or a wet etching process to form the lower electrode pattern254apartially filling the first contact hole252.

Referring toFIG. 26, the phase change layer pattern260filling a remaining portion of the first contact hole252may be formed on the lower electrode pattern254a. In example embodiments, a phase change layer sufficiently filling the first contact hole may be formed on the second insulating interlayer250and the lower electrode pattern254ausing a chalcogen compound, e.g., at least one of GeSbSe, SbSe, GeSbTe, SbTe, GeSb, etc. The phase change layer may be partially planarized until a top surface of the second insulating interlayer150is exposed to form the phase change layer pattern260.

In example embodiments, the phase change layer pattern260and the lower electrode layer pattern254amay have a common cross-section and may be buried in the second insulating interlayer250. Thus, an efficiency of transferring heat and/or current to the phase change layer pattern260may be improved.

Referring toFIG. 27, an upper electrode layer may be formed on the second insulating interlayer150and the phase change layer pattern260. The upper electrode layer may be patterned to form an upper electrode265contacting the phase change layer pattern260.

The third insulating interlayer270covering the upper electrode265may be formed on the second insulating interlayer250. The upper electrode contact275may be formed on the upper electrode265through the third insulating interlayer270. The bit line280electrically connected to the upper electrode265via the upper electrode contact275may be formed on the third insulating interlayer270.

As described above, according to example embodiments, a phase change memory device may include a metal silicide pattern embedded or buried in an active region functioning as a word line of the phase change memory device, thereby reducing resistance of the words line. Thus, a cell resistance generated between the word line and a P-N diode may be reduced, so that a current may easily flow from the P-N diode to a lower electrode and from the lower electrode to a phase change material pattern by relatively small power or voltage. Therefore, the phase change memory device may have small cell current distributions and enhanced operational characteristics.

In contrast, in a conventional phase change memory device with a P-N diode, e.g., a phase change memory device without metal silicides in an impurity region functioning as a word line, as a critical dimension of each cell decreases for achieving a high degree of integration, an electrical resistance between the P-N diode and an active region of the phase change memory device may be increased. Thus, a current may not be easily transferred from a contact or a metal wiring to the cell of the phase change memory device. Further, current distributions of the cells may become larger.