Semiconductor device including DLL and semiconductor system

A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean Patent Application No. 10-2016-0162476, filed on Dec. 1, 2016, which is herein incorporated by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor device including a Delay Locked Loop (DLL) and a semiconductor system including the semiconductor device.

2. Description of the Related Art

A clock is generally used as a reference for tuning timing for an operation in a system or a circuit. Also, a clock may be used to secure a fast operation being performed without an error. When an external clock is inputted from an external device and used in an internal circuit, time delay (which is called ‘skew’) is caused by the internal circuit. Herein, a Delay Locked Loop (DLL) is used to compensate for the time delay and make an internal clock have the same phase as the external clock.

Meanwhile, the delay locked loop has an advantage in that it is less affected by noise than a phase locked loop (PLL), which has been used conventionally. For this reason, the delay locked loop is widely used for synchronous semiconductor memories, such as a Synchronous Dynamic Random Access Memory (SDRAM) and a Double Data Rate SDRAM (DDR SDRAM).

The delay locked loop may operate to compensate for a delay time difference between an external clock, i.e., a reference clock signal, and a feedback clock signal obtained as the reference clock signal passes through a replica.

However, as a frequency of the reference clock signal increases, a locking time of the delay locked loop, which is the time taken until a rising edge of the feedback clock signal and a rising edge of the reference clock signal coincides with each other, becomes considerably long. As a result, the delay locked loop does not obtain sufficient timing margin and accordingly, an operation stability of a system including a semiconductor memory device provided with the delay locked loop is deteriorated.

SUMMARY

Embodiments of the present invention are directed to a semiconductor device including a Delay Locked Loop (DLL) capable of increasing an operation timing margin by setting an optimal value of a delay control signal within a short time, and a semiconductor system including the semiconductor device.

In accordance with an embodiment of the present invention, a semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

In accordance with another embodiment of the present invention, a semiconductor device includes: a decoding unit suitable for decoding a command/address signal and generating an input control signal and an output control signal; an initial value setting unit suitable for including a plurality of storages corresponding to bits of the input control signal, sequentially storing code values of a delay control signal in the storages in response to the input control signal when a locking signal is enabled, and selecting one of the stored code values to output an initial value control signal based on the output control signal; and a delay locked loop (DLL) suitable for generating the delay control signal having an initial value that is set based on the initial value control signal, performing a locking operation of generating an internal clock signal by delaying an external clock signal based on the delay control signal, and outputting the locking signal and the delay control signal when the locking operation is finished.

In accordance with yet another embodiment of the present invention, a semiconductor system includes: a controller suitable for outputting an external clock signal, and selecting one of pre-stored code values of a delay control signal to output the selected code value as an initial value control signal based on frequency information on the external clock signal; and a semiconductor device suitable for generating the delay control signal having an initial value that is set based on the initial value control signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal.

DETAILED DESCRIPTION

It is noted that the drawings are simplified schematics and as such are not necessarily drawn to scale. In some instances, various parts of the drawings may have been exaggerated in order to more clearly illustrate certain features of the illustrated embodiments.

It is further noted that in the following description, specific details are set forth for facilitating the understanding of the present invention, however, the present invention may be practiced without some of these specific details.

Also, it is noted, that well-known structures and/or processes may have only been described briefly or not described at all to avoid obscuring the present disclosure with unnecessary well known details.

It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, an element (also referred to as a feature) described in connection with one embodiment may be used singly or in combination with other elements of another embodiment, unless specifically indicated otherwise.

FIG. 1is a block diagram illustrating a semiconductor system10in accordance with an embodiment of the present invention.

Referring toFIG. 1, the semiconductor system10may include a semiconductor device100and a controller200.

The controller200may output an external clock signal EXT_CLK and a command/address signal CMD/ADDR to the semiconductor device100. According to an embodiment of the present invention, the controller200may generate the command/address signal CMD/ADDR including frequency information on the external clock signal EXT_CLK.

The semiconductor device100may select a pre-stored code value of a delay control signal CTRL<0:K> to output the selected code value as an initial value control signal CTRL_INIT<0:K>, according to the command/address signal CMD/ADDR which is inputted from the controller200, and may output an internal clock signal INT_CLK by delaying the external clock signal EXT_CLK by a predetermined time based on the delay control signal CTRL<0:K> having an initial value which is set according to the initial value control signal CTRL_INIT<0:K>. According to an embodiment of the present invention, the semiconductor device100may be a semiconductor memory device. Particularly, the semiconductor device100may be a Dynamic Random Access Memory (DRAM).

The controller200may transfer the external clock signal EXT_CLK and the command/address signal CMD/ADDR to the semiconductor device100along with data DATA during a write operation. A data strobe signal DQS may be transferred to the semiconductor device100along with the data DATA.

The controller200may transfer the external clock signal EXT_CLK and the command/address signal CMD/ADDR to the semiconductor device100during a read operation, and the semiconductor device100may read the data DATA that is stored internally and transfer the read data DATA to the controller200along with the data strobe signal DQS. An internal circuit (not shown) of the semiconductor device100may receive the internal clock signal INT_CLK, the command/address signal CMD/ADDR, and the data DATA and perform the read operation or the write operation. Since the read operation or the write operation described above is not related to the point of the present invention, detailed description on them is omitted herein.

The controller200may include a processing unit210for generating the external clock signal EXT_CLK, the command/address signal CMD/ADDR, and the data DATA. The processing unit210may generate the command/address signal CMD/ADDR including frequency information on the external clock signal EXT_CLK.

The semiconductor device100may include a decoding unit110, an initial value setting unit130, and an internal clock generation unit150.

The decoding unit110may generate an input control signal STRB<0:M> and an output control signal SEL<0:N> by decoding the command/address signal CMD/ADDR.

The initial value setting unit130may include a plurality of storages (not shown) respectively corresponding to bits of the input control signal STRB<0:M>. Whenever a locking signal LOCK is enabled, the initial value setting unit130may sequentially store the code values of the delay control signal CTRL<0:K> in the storages corresponding to the input control signal STRB<0:M>, and select one of the pre-stored code values to output the initial value control signal CTRL_INIT<0:K> in response to the output control signal SEL<0:N>.

The internal clock generation unit150may generate the delay control signal CTRL<0:K> having an initial value that is set based on the initial value control signal CTRL_INIT<0:K>, perform a locking operation of generating the internal clock signal INT_CLK by delaying the external clock signal EXT_CLK based on the delay control signal CTRL<0:K>, and output the locking signal LOCK and the delay control signal CTRL<0:K> when the locking operation is finished. According to the embodiment of the present invention, the internal clock generation unit150may be formed of a delay locked loop (DLL), for example, a digital delay locked loop. Herein, the locking signal LOCK of the delay locked loop DLL is a signal that is enabled when the frequency and phase of a feedback clock signal FB_CLK that is internally generated coincide with the frequency and phase of the external clock signal EXT_CLK, that is, when a locking operation of the delay locked loop DLL is finished.

Meanwhile, the semiconductor device100may further include a clock pad CK_PAD for receiving the external clock signal EXT_CLK, a command/address pad CA_PAD for receiving the command/address signal CMD/ADDR, and a data pad DQ_PAD and a data strobe pad DQS_PAD for receiving/outputting the data DATA and the data strobe signal DQS, respectively. Although it is illustrated inFIG. 1that there is one data pad DQ_PAD, more data pads DQ_PAD may be provided to equal the number of input/output data burst bits. Also, although not illustrated in the drawing, an input buffer for buffering signals that are inputted through the above-mentioned pads and output drivers for driving signals that are outputted through the pads may be additionally included.

Hereafter, exemplary configurations of the constituent elements of the semiconductor device ofFIG. 1are described in detail with reference to the accompanying drawings.

FIG. 2is a block diagram illustrating the initial value setting unit130of the semiconductor device shown inFIG. 1.

Referring toFIG. 2, the initial value setting unit130may include a control signal generator310, a preceding value storage330, and an initial value outputter350.

The control signal generator310may generate a latch control signal LATEN<0:M> according to the input control signal STRB<0:M> whenever the locking signal LOCK received from the internal clock generation unit150is enabled.

The preceding value storage330may include a plurality of storages330_0to330_M that correspond to each bit of the latch control signal LATEN<0:M>, respectively. The preceding value storage330may sequentially store the delay control signal CTRL<0:K> outputted from the internal clock generation unit150(seeFIG. 1) in the storages330_0to330_M in response to each bit of the latch control signal LATEN<0:M>.

The initial value outputter350may select one output of the storages330_0to330_M to output the initial value control signal CTRL_INIT<0:K> in response to the output control signal SEL<0:N>.

FIG. 3Ais a detailed circuit diagram illustrating n exemplary configuration of the control signal generator310shown inFIG. 2.FIG. 3Bis a timing diagram illustrating an operation of the control signal generator310shown inFIG. 2.

Referring toFIG. 3A, the control signal generator310may include a plurality of flip-flops DFF0to DFFM that are coupled in series. According to an embodiment of the present invention, the flip-flops DFF0to DFFM may be D-flip-flops. An input terminal D of the foremost flip-flop DFF0among the flip-flops DFF0to DFFM may be coupled to a power source voltage (VDD) terminal. Each of the flip-flops DFF0to DFFM may receive the locking signal LOCK through a clock terminal, receive a corresponding bit of the input control signal STRB<0:M> through a reset terminal RST, and receive an output of the preceding flip-flop through the input terminal D. A corresponding bit of the latch control signal LATEN<0:M> may be outputted through an output terminal Q of each of the flip-flops DFF0to DFFM. The number of the flip-flops DFF0to DFFM may correspond to the number of the bits of the latch control signal LATEN<0:M>.

Each of the flip-flops DFF0to DFFM may output its output signal from its output terminal Q to the input terminal D of the next flip-flop when the locking signal LOCK is enabled while the corresponding bit of the input control signal STRB<0:M> is enabled. Therefore, when the bits of the input control signal STRB<0:M> are sequentially enabled, the flip-flops DFF0to DFFM may sequentially enable first to (M+1)thbits of the latch control signal LATEN<0:M>, whenever the locking signal LOCK is enabled.

Referring toFIG. 3B, the control signal generator310may generate the latch control signal LATEN<0:M> corresponding to each bit of the input control signal STRB<0:M>, whenever the locking signal LOCK is enabled.

For example, while a first bit STRB<0> of the input control signal STRB<0:M> is enabled, a first bit LATEN<0> of the latch control signal LATEN<0:M> may be enabled when the locking signal LOCK is enabled ({circle around (1)}). While a second bit STRB<1> of the input control signal STRB<0:M> is enabled, a second bit LATEN<1> of the latch control signal LATEN<0:M> may be enabled when the locking signal LOCK is enabled ({circle around (3)}). We note, that although the locking signal LOCK is enabled ({circle around (2)}), since the second bit STRB<1> of the input control signal STRB<0:M> is disabled, the second bit LATEN<1> of the latch control signal LATEN<0:M> is not enabled.

As described above, the initial value setting unit130may pre-store the code values of the delay control signal CTRL<0:K> for each frequency of the external clock signal EXT_CLK. For example, the initial value setting unit130may selectively store only the code values of the delay control signal CTRL<0:K> corresponding to a desired frequency by using the input control signal STRB<0:M>. Further, the initial value setting unit130may set a code value corresponding to a frequency of a current external clock EXT_CLK from the pre-stored code values, as the initial value of the delay control signal CTRL<0:K> by using the output control signal SEL<0:N>.

FIG. 4is a detailed block diagram illustrating an exemplary configuration of the internal clock generation unit150shown inFIG. 1.

Referring toFIG. 4, in addition to the internal clock generation unit150shown inFIG. 1, an input buffer140and an output driver160are shown together. The input buffer140may generate a reference clock signal REF_CLK by buffering the external clock signal EXT_CLK inputted through the clock pad CK_PAD. The output driver160may drive a delay clock signal DLY_CLK outputted through the internal clock generation unit150and finally output the internal clock signal INT_CLK.

The internal clock generation unit150may include a delay line410, a delay compensator420, a phase detector430, and a delay controller440.

The delay line410may generate the delay clock signal DLY_CLK by delaying the reference clock signal REF_CLK in response to the delay control signal CTRL<0:K> received from the delay controller440. The delay compensator420may generate a feedback clock signal FB_CLK by delaying the delay clock signal DLY_CLK received from the delay line410by a predetermined time. The phase detector430may generate a phase detecting signal PD_DET by comparing a phase of the reference clock signal REF_CLK received from the input buffer140with a phase of the feedback clock signal FB_CLK received from the delay compensator420.

The delay controller440may generate the delay control signal CTRL<0:K> based on the phase detecting signal PD_DET received from the phase detector. For example, the delay controller440may generate the delay control signal CTRL<0:K> to have an initial value that is set based on the initial value control signal CTRL_INIT<0:K>. The delay controller440may output the locking signal LOCK and the delay control signal CTRL<0:K>, when the frequency and phase of the reference clock signal REF_CLK coincide with the frequency and phase of the feedback clock signal FB_CLK and a desired internal clock signal INT_CLK is outputted, that is, when the locking operation is finished. Meanwhile, the delay controller440may receive a reset signal RST, and initialize the locking signal LOCK and the delay control signal CTRL<0:K> in response to the reset signal RST after the locking operation is finished.

As described above, the internal clock generation unit150may generate the delay control signal CTRL<0:K> to have the set initial value based on the initial value control signal CTRL_INIT<0:K>, delay the reference clock signal REF_CLK to generate the delay clock signal DLY_CLK by using the delay control signal CTRL<0:K>. Therefore, the internal clock generation unit150may increase a clock generation speed, and reduce a locking time of the internal clock generation unit150.

FIG. 5is a detailed circuit diagram illustrating an exemplary configuration of the delay line410shown inFIG. 4.

Referring toFIG. 5, the delay line410may include a plurality of unit delayers UD0to UDK that are coupled in series.

The unit delayers UD0to UDK may delay the reference clock signal REF_CLK based on the delay control signal CTRL<0:K> received from the delay controller440, which is formed of a plurality of bits, and finally generate the delay clock signal DLY_CLK.

The foremost unit delayer UD0among the unit delayers UD0to UDK may receive one of a power source voltage VDD and the reference clock signal REF_CLK, and the other unit delayers UD1to UDK may receive one of an output of the preceding unit delayer and the reference clock signal REF_CLK. When a corresponding bit of the delay control signal CTRL<0:K> is enabled, one of the unit delayers UD0to UDK corresponding to the enabled bit may receive the reference clock signal REF_CLK. For example, when a third bit CTRL<2> of the delay control signal CTRL<0:K> is enabled, the third unit delayer UD2may receive the reference clock signal REF_CLK instead of the output of the preceding unit delayer, and the third to Kthunit delayers UD2to UDK may sequentially delay the reference clock signal REF_CLK.

As described above, the delay line410may decide the positions of the unit delayers UD0to UDK which receive the reference clock signal REF_CLK based on the code value of the delay control signal CTRL<0:K>, and decide the number of the unit delayers UD0to UDK through which the reference clock signal REF_CLK passes.

Hereafter, an operation of the semiconductor system in accordance with an embodiment of the present invention is described with reference toFIGS. 1 to 6.

FIG. 6is a timing diagram illustrating an operation of the semiconductor system in accordance with an embodiment of the present invention.

Referring toFIG. 6, the controller200may output the external clock signal EXT_CLK and the command/address signal CMD/ADDR to the semiconductor device100. Herein, it is assumed that the command/address signal CMD/ADDR includes information representing that the frequency of the external clock signal EXT_CLK is approximately 500 MHz.

The internal clock generation unit150of the semiconductor device100may perform a locking operation of delaying the external clock signal EXT_CLK by a predetermined time to output the internal clock signal INT_CLK, and output the locking signal LOCK and the delay control signal CTRL<0:K> when the locking operation is finished. Herein the code value of the delay control signal CTRL<0:K> may include frequency information of approximately 500 MHz. After the locking operation is finished, the locking signal LOCK and the delay control signal CTRL<0:K> may be initialized based on the reset signal RST.

Meanwhile, the decoding unit110may decode the command/address signal CMD/ADDR provided by the controller200and generate the input control signal STRB<0:M>. Herein, since there is no pre-stored delay control signal CTRL<0:K>, the output control signal SEL<0:N> may be disabled.

The control signal generator310of the initial value setting unit130may generate the latch control signal LATEN<0:M> corresponding to each bit of the input control signal STRB<0:M> whenever the locking signal LOCK is enabled. In other words, while the first bit STRB<0> of the input control signal STRB<0:M> is enabled, the first bit LATEN<0> of the latch control signal LATEN<0:M> may be enabled when the locking signal LOCK is enabled. The preceding value storage330may store the delay control signal CTRL<0:K> outputted from the internal clock generation unit150in a first storage330_0in response to the first bit LATEN<0> of the latch control signal LATEN<0:M>. Therefore, the first storage330_0may store the code value “LOCK_CODE_500” of the delay control signal CTRL<0:K> for the frequency of approximately 500 MHz.

When the controller200changes the frequency of the external clock signal EXT_CLK, the controller200may output the external clock signal EXT_CLK and the command/address signal CMD/ADDR back to the semiconductor device100. Herein, it is assumed that the command/address signal CMD/ADDR includes information representing that the frequency of the external clock signal EXT_CLK is approximately 1000 MHz.

Likewise, the internal clock generation unit150may output the locking signal LOCK and the delay control signal CTRL<0:K> when the locking operation is completed. Herein, the code value of the delay control signal CTRL<0:K> may include frequency information for approximately 1000 MHz.

The decoding unit110may decode the command/address signal CMD/ADDR provided by the controller200and generate the input control signal STRB<0:M>. Herein, since there is no pre-stored delay control signal CTRL<0:K> for approximately 1000 MHz, the output control signal SEL<0:N> may be disabled.

While the second bit STRB<1> of the input control signal STRB<0:M> is enabled, the initial value setting unit130may enable the second bit LATEN<1> of the latch control signal LATEN<0:M> when the locking signal LOCK is enabled. In response to the second bit LATEN<1> of the latch control signal LATEN<0:M> the initial value setting unit130may store the delay control signal CTRL<0:K> outputted from the internal clock generation unit150in a second storage330_1. Therefore, the second storage330_1may store the code value “LOCK_CODE_1000” of the delay control signal CTRL<0:K> for the frequency of approximately 1000 MHz.

Through the method described above, the delay control signal CTRL<0:K> that is outputted whenever the locking operation is finished may be sequentially stored in the storages330_0to330_M. When the external clock signal EXT_CLK having the frequency of approximately 1000 MHz is inputted, the controller200may disable the input control signal STRB<0:M> so that the delay control signal CTRL<0:K> which is outputted when the corresponding locking operation is finished is not stored in the storages330_0to330_M.

Subsequently, when the controller200changes the frequency of the external clock signal EXT_CLK, the controller200may output the external clock signal EXT_CLK and the command/address signal CMD/ADDR to the semiconductor device100. Herein, it is assumed that the command/address signal CMD/ADDR includes information representing that the frequency of the external clock signal EXT_CLK is approximately 500 MHz.

In this case, since the code value of the delay control signal CTRL<0:K> for approximately 500 MHz is already stored in the first storage330_0, the decoding unit110may generate the output control signal SEL<0:N> for selecting the first storage330_0based on the command/address signal CMD/ADDR. The initial value outputter350of the initial value setting unit130may output the code value stored in the first storage330_0as the initial value control signal CTRL_INIT<0:K> in response to the output control signal SEL<0:N>.

The internal clock generation unit150may generate the delay control signal CTRL<0:K> having an initial value “LOCK_CODE_500” that is set based on the initial value control signal CTRL_INIT<0:K>, and perform a locking operation of generating the internal clock signal INT_CLK by delaying the external clock signal EXT_CLK based on the delay control signal CTRL<0:K>.

Subsequently, when the controller200changes the frequency of the external clock signal EXT_CLK again, the controller200may output the external clock signal EXT_CLK and the command/address signal CMD/ADDR to the semiconductor device100. Herein, it is assumed that the command/address signal CMD/ADDR includes information representing that the frequency of the external clock signal EXT_CLK is approximately 1000 MHz.

Likewise, since the code value of the delay control signal CTRL<0:K> for approximately 1000 MHz is already stored in the second storage330_1the decoding unit110may generate the output control signal SEL<0:N> for selecting the second storage330_1based on the command/address signal CMD/ADDR. The initial value outputter350of the initial value setting unit130may output the code value stored in the second storage330_1as the initial value control signal CTRL_INIT<0:K> in response to the output control signal SEL<0:N>.

The internal clock generation unit150may generate the delay control signal CTRL<0:K> having an initial value “LOCK_CODE_1000” that is set based on the initial value control signal CTRL_INIT<0:K>, and perform a locking operation of generating the internal clock signal INT_CLK by delaying the external clock signal EXT_CLK based on the delay control signal CTRL<0:K>.

As described, in the embodiment of the present invention, when the code values of the delay control signal CTRL<0:K> for each frequency of the external clock signal EXT_CLK are stored, the delay control signal CTRL<0:K> of a desired frequency may be selectively stored by using the input control signal STRB<0:M>, Further, a code value corresponding to a frequency of a current external clock EXT_CLK may be set as the initial value of the delay control signal CTRL<0:K> from the pre-stored code values of the delay control signal CTRL<0:K> by using the output control signal SEL<0:N>. Therefore, the locking time of the internal clock generation unit, i.e., the delay locked loop, maybe decreased by setting the code value corresponding to the frequency of the current external clock EXT_CLK as the initial value of the delay control signal CTRL<0:K> based on the command/address signal CMD/ADDR provided by the controller200. Also, a memory system employing the technology of the present invention exhibits enhanced stability because of an increased operation timing margin.

Hereafter, a semiconductor system in accordance with another embodiment of the present invention is described with reference to the accompanying drawings.

FIG. 7is a block diagram illustrating a semiconductor system10A in accordance with another embodiment of the present invention.

Referring toFIG. 7, the semiconductor system10A may include a semiconductor device100A and a controller200A.

The semiconductor system10A ofFIG. 7may be different from the semiconductor system10shown inFIG. 1in that the controller200A includes an initial value setting unit230A, and the controller200A receives a locking signal LOCK and a delay control signal CTRL<0:K> from the semiconductor device100A and outputs an initial value control signal C_CTRL_INIT<0:K> to the semiconductor device100A, through existing data pad DQ_PAD data strobe pad DQS_PAD, and a transmission line.

To be specific, the semiconductor device100A may include an internal clock generation unit150A. Since the internal clock generation unit150A ofFIG. 7has substantially the same structure as the internal clock generation unit150ofFIG. 1, further description on it is omitted herein.

The controller200A may include a processing unit210A and an initial value setting unit230A.

The processing unit210A may generate an input control signal C_STRB<0:M> and an output control signal C_SEL<0:N>.

The initial value setting unit230A may include a plurality of storages (not shown) respectively corresponding to bits of the input control signal C_STRB<0:M>, and receive the locking signal LOCK and the delay control signal CTRL<0:K> from the internal clock generation unit150A. Whenever the locking signal LOCK is enabled, the initial value setting unit230A may sequentially store the code values of the delay control signal CTRL<0:K> in the storages in response to the input control signal C_STRB<0:M>, and select one of the pre-stored code values to output the initial value control signal C_CTRL_INIT<0:K> to the internal clock generation unit150A, based on the output control signal C_SEL<0:N>, Since the initial value setting unit230A ofFIG. 7has substantially the same structure as the initial value setting unit230ofFIG. 1, further description on it is omitted herein.

Including the initial value setting unit230A inside the controller200A, it may be advantageous in a system where a plurality of semiconductor devices are coupled to one controller in that the load on the semiconductor devices may be reduced and the controller may more readily control the semiconductor devices collectively. When the semiconductor device100A is a semiconductor memory device, particularly, when the semiconductor device100A is a Dynamic Random Access Memory (DRAM) device, the controller200A may perform training between a data strobe signal DQS and an internal clock signal INT_CLK by varying the delay control signal CTRL<0:K> using the initial value control signal C_CTRL_INIT<0:K>.

FIG. 8is a block diagram illustrating a semiconductor system10B in accordance with yet another embodiment of the present invention.

Referring toFIG. 8, the semiconductor system10B may include a semiconductor device100B and a controller200B.

In the semiconductor system10B ofFIG. 8, the semiconductor device100B and the controller200B may all include an initial value setting unit. In other words, the semiconductor system10B ofFIG. 8has a configuration that is a hybrid between the configurations of the semiconductor systems10and10A ofFIGS. 1 and 7. In the semiconductor system10B a first initial value setting unit130B included in the semiconductor device100B or a second initial value setting unit230B included in the controller200B may be selectively used.

To be specific, the semiconductor device100B may include a decoding unit110B, the first initial value setting unit130B, and an internal clock generation unit150B. Since the semiconductor device100B ofFIG. 8has substantially the same structure as the semiconductor device100ofFIG. 1, further description on it is omitted herein.

The controller200B may include a processing unit210B and the second initial value setting unit230B. Since the controller200B ofFIG. 8has substantially the same structure as the controller200A ofFIG. 7, further description on it is omitted herein.

As both of the semiconductor device100B and the controller200B include the initial value setting unit, a first initial value control signal CTRL_INIT<0:K> outputted from the first initial value setting unit130B of the semiconductor device100B or a second initial value control signal CTRL_INIT<0:K> outputted from the second initial value setting unit230B of the controller200B may be selectively used according to the situations.

According to an embodiment of the present invention, a semiconductor device may pre-store a code value corresponding to a frequency of a current external clock as an initial value of a delay control signal. As a result, an operation speed of a delay locked loop may be increased and a locking time of the delay locked loop may be decreased.

Also, the semiconductor device according to an embodiment of the present invention may increase an operation timing margin by setting an optimal value of the delay control signal within a short time, thus securing stability of a system including the semiconductor device.

While the present invention has been described with respect to specific embodiments it will be apparent to those ski led in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

For example, the logic gates and transistors illustrated in the above-described embodiments of the present invention may be realized in different positions and different kinds according to the polarity of an input signal.