Circuits and methods for calibration of a motion detector

A circuit to detect a movement of an object has a calibration time period that ends when peak detectors in the circuit stop updating for a predetermined amount of time. A method associated with the circuit is also described.

CROSS REFERENCE TO RELATED APPLICATIONS

Not Applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

Not Applicable.

FIELD OF THE INVENTION

This invention relates generally to integrated circuits and, more particularly, to integrated circuits for detecting a movement or a rotation of a ferromagnetic object.

BACKGROUND OF THE INVENTION

Magnetic field sensors (e.g., rotation detectors) for detecting ferromagnetic articles and/or magnetic articles are known. The magnetic field associated with the ferromagnetic article or magnetic article is detected by a magnetic field sensing element, such as a Hall element or a magnetoresistance element, which provides a signal (i.e., a magnetic field signal) proportional to a detected magnetic field. In some arrangements, the magnetic field signal is an electrical signal.

The magnetic field sensor processes the magnetic field signal to generate an output signal that changes state each time the magnetic field signal crosses thresholds, either near to peaks (positive and/or negative peaks) or near to some other level, for example, zero crossings of the magnetic field signal. Therefore, the output signal has an edge rate or period indicative of a speed of rotation of the ferromagnetic or magnetic object, for example, a gear or a ring magnet.

One application for a magnetic field sensor is to detect the approach and retreat of each tooth of a rotating ferromagnetic gear, either a hard magnetic gear or a soft ferromagnetic gear. In some particular arrangements, a ring magnet having magnetic regions (permanent or hard magnetic material) with alternating polarity is coupled to the ferromagnetic gear or is used by itself and the magnetic field sensor is responsive to approach and retreat of the magnetic regions of the ring magnet. In other arrangements, a gear is disposed proximate to a stationary magnet and the magnetic field sensor is responsive to perturbations of a magnetic field as the gear rotates.

In one type of magnetic field sensor, sometimes referred to as a peak-to-peak percentage detector (or threshold detector), one or more threshold levels are equal to respective percentages of the peak-to-peak magnetic field signal. One such peak-to-peak percentage detector is described in U.S. Pat. No. 5,917,320 entitled “Detection of Passing Magnetic Articles While Periodically Adapting Detection Threshold” and assigned to the assignee of the present invention.

Another type of magnetic field sensor, sometimes referred to as a slope-activated detector (or peak-referenced detector, or peak detector for short), is described in U.S. Pat. No. 6,091,239 entitled “Detection Of Passing Magnetic. Articles With a Peak Referenced Threshold Detector,” also assigned to the assignee of the present invention. In the peak-referenced magnetic field sensor, the threshold signal differs from the positive and negative peaks (i.e., the peaks and valleys) of the magnetic field signal by a predetermined amount. Thus, in this type of magnetic field sensor, the output signal changes state when the magnetic field signal comes away from a peak or valley of the magnetic field signal by the predetermined amount.

It should be understood that, because the above-described threshold detector and the above-described peak detector both have circuitry that can identify the positive and negative peaks of a magnetic field signal, the threshold detector and the peak detector both include a circuit portion referred to as a “peak identifier” herein, which is configured to detect positive peaks and/or negative peaks of the magnetic field signal. The threshold detector and the peak detector, however, each use the detected peaks in different ways.

In order to accurately detect the positive and negative peaks of a magnetic field signal, the rotation detector is capable of tracking at least part of the magnetic field signal. To this end, typically, one or more digital-to-analog converters (DACs) can be used to generate a tracking signal, which tracks the magnetic field signal. For example, in the above-referenced U.S. Pat. Nos. 5,917,320 and 6,091,239, two DACs are used, one (PDAC) to detect the positive peaks of the magnetic field signal and the other (NDAC) to detect the negative peaks of the magnetic field signal.

Some types of rotation detectors perform one or more types of initialization or calibration, for example, at a time near to start up or power up of the rotation detector, or otherwise, from time to time as desired. During one type of calibration, the above-described threshold level is determined. In some types of calibration, a time interval during which the calibration occurs is determined in accordance with a predetermined number of cycles of the magnetic field signal. Thus, for fast magnetic field signals (e.g., for fast rotating gears), the time available for calibration is small. In those applications for which the movement or rotation is rapid and the time available for calibration is small, the rotation detector might not calibrate properly, i.e., the threshold might not be properly determined.

It would, therefore, be desirable to provide a magnetic field sensor that can accurately identify a threshold level associated with a magnetic field signal, accurate for both fast and slow magnetic field signals.

SUMMARY OF THE INVENTION

The present invention provides a magnetic field sensor that can accurately identify a threshold level associated with a magnetic field signal, accurate for both fast and slow magnetic field signals

In accordance with one aspect of the present invention, a circuit for detecting a movement of an object includes at least one magnetic field sensing element for generating a DIFF signal proportional to a magnetic field associated with the object. The circuit also includes at least one motion detector coupled to receive the DIFF signal and configured to generate a tracking signal to track the DIFF signal so as to move toward a peak of the DIFF signal. The at least one motion detector includes a PDAC configured to generate a PDAC output signal to track the DIFF signal during a PDAC update time interval within a calibration time period and to hold the DIFF signal at times outside of the PDAC update time interval within the calibration time period. The at least one motion detector also includes an NDAC configured to generate an NDAC output signal to track the DIFF signal during an NDAC update time interval within the calibration time period and to hold the DIFF signal at times outside of the NDAC update time interval within the calibration time period. The at least one motion detector also includes an update logic circuit coupled to the PDAC and to the NDAC, wherein the update logic circuit is configured to establish an end of the calibration time period by determining if a first time period since an end of the PDAC update time interval is greater than a first predetermined time threshold and by determining if a second time period since an end of the NDAC update time interval is greater than a second predetermined time threshold. In some embodiments, the first and second time thresholds can be the same predetermined time threshold.

In accordance with another aspect of the present invention, a method of detecting a movement of an object includes generating a DIFF signal with at least one magnetic field sensing element, wherein the DIFF signal is proportional to a magnetic field associated with the object. The method also includes generating a tracking signal to track the DIFF signal. The generating the tracking signal includes generating a PDAC output signal to track the DIFF signal during a PDAC update time interval within a calibration time period and to hold the DIFF signal at times outside of the PDAC update time interval within the calibration time period. The generating the tracking signal also includes generating an NDAC output signal to track the DIFF signal during an NDAC update time interval within the calibration time period and to hold the DIFF signal at times outside of the NDAC update time interval within the calibration time period. The generating the tracking signal also includes establishing an end of the calibration time period. The establishing includes determining if a first time period since an end of the PDAC update time interval is greater than a first predetermined time threshold, and determining if a second time period since an end of the NDAC update time interval is greater than a second predetermined time threshold. In some embodiments, the first and second time thresholds can be the same predetermined time threshold.

In accordance with another aspect of the present invention, a method of detecting a movement of an object includes generating a magnetic field signal with at least one magnetic field sensing element, wherein the magnetic field signal is proportional to a magnetic field associated with the object. The method also includes generating a tracking signal during a calibration mode of operation that moves toward a peak of the magnetic field signal at least until the peak is reached. The method also includes terminating the calibration mode of operation after a predetermined time interval has lapsed since the tracking signal reached the peak of the magnetic field signal.

DETAILED DESCRIPTION OF THE INVENTION

Before describing the present invention, some introductory concepts and terminology are explained. As used herein, the term “magnetic field sensing element” is used to describe a variety of types of electronic elements that can sense a magnetic field. The magnetic field sensing elements can be, but are not limited to, Hall effect elements, magnetoresistance elements, or magnetotransistors. As is known, there are different types of Hall effect elements, for example, planar Hall elements, vertical Hall elements, circular Hall elements, and Indium antimonide (InSb) sensors. As is also known, there are different types of magnetoresistance elements, for example, anisotropic magnetoresistance (AMR) elements, giant magnetoresistance (GMR) elements, tunneling magnetoresistance (TMR) elements, and magnetic tunnel junction (MTJ) elements.

As is known, some of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity parallel to a substrate that supports the magnetic field sensing element, and others of the above-described magnetic field sensing elements tend to have an axis of maximum sensitivity perpendicular to a substrate that supports the magnetic field sensing element. In particular, most, but not all, types of magnetoresistance elements tend to have axes of maximum sensitivity parallel to the substrate and most, but not all, types of Hall elements tend to have axes of sensitivity perpendicular to a substrate.

As used herein, the term “magnetic field sensor” is used to describe a circuit that includes a magnetic field sensing element. Magnetic field sensors are used in a variety of applications, including, but not limited to, a current sensor that senses a magnetic field generated by a current carried by a current-carrying conductor, a magnetic switch or proximity detector that senses the proximity of a ferromagnetic or magnetic object, a rotation detector that senses passing ferromagnetic articles, for example, magnetic domains of a ring magnet or teeth of a ferromagnetic gear, and a magnetic field sensor that senses a magnetic field density of a magnetic field. Rotation detectors are used as examples herein. However, the circuits and techniques described herein apply also to any magnetic field sensor capable of detecting a motion of an object.

Threshold detectors and peak detectors are described above. As used herein, the term “peak identifier” is used to describe a circuit that can track and perhaps hold a signal representative of a positive peak or a negative peak (or both) of a magnetic field signal. It should be understood that both a threshold detector and a peak detector both employ a peak identifier circuit.

While circuits are shown below that use threshold detectors, in other embodiments, similar circuits can use peak detectors. Also, while circuits are shown below that use rotation detectors, in some embodiments, the rotations detectors can be motion detectors configured to detect other motions of an object, for example, repetitive linear motions.

Operation of a magnetic field sensor in a so-called “calibration mode,” also referred to herein as an “initialization mode.” is described herein. Reference is also made herein to operation of a magnetic field sensor in a so-called “running mode.” The calibration mode can occur at the beginning of operation (or from time to time as desired) and the running mode is achieved at other times. Operation of the running mode is described in greater detail in one or more of the above-mentioned patents, notably, U.S. Pat. No. 5,917,320 and U.S. patent application Ser. No. 11/333,522, which are incorporated by reference herein in their entirety.

In general, during the calibration mode, an output signal from the magnetic field sensor may not be accurate, and during the running mode, the output signal is considered to be accurate, i.e., it has edges properly aligned with features of the magnetic field signal.

While a calibration time period is discussed herein, and end of which ends the calibration mode discussed herein in accordance with certain criteria, it should be recognized that other calibrations can be performed after the end of the indicated calibration time period. For example, an automatic gain control can continue calibrating after the end of the indicated calibration time period. At some point after the end of the indicated calibration time period, but not necessarily coincident with the end of the indicated calibration time period, the magnetic field sensors described herein can enter the running mode, during which updates to values of circuit parameters can update in a different way than during the calibration mode.

Referring now toFIG. 1, an exemplary magnetic field sensor10includes a magnetic field sensing element14for generating a signal14a,14b(i.e., a magnetic field signal) proportional to a magnetic field associated with an object24. The magnetic field sensing element14can be, but is not limited to, a Hall effect element, a magnetoresistance element, or a magnetotransistor.

The object24can be an object configured to rotate, for example, a ferromagnetic gear. The magnetic field sensor10can include an amplifier16coupled to receive signals14a,14bfrom the magnetic field sensing element14and configured to generate a signal16a(also a magnetic field signal).

In some embodiments, the magnetic field sensor10also includes a motion detector, here a rotation detector12, having an amplifier22coupled to receive the signal16aand configured to generate a signal22a, also referred to herein as a DIFF signal, representative of the signal16a(also a magnetic field signal). In some embodiments, the amplifier22is an automatic gain control (AGC) amplifier. The DIFF signal is also referred to herein as a magnetic field signal. Thus, the signals14a,14b,16a, and22aare all magnetic field signals, and are all indicative of a magnetic field experience by the magnetic field sensing element14.

The rotation detector12can include a threshold detector20coupled to receive the DIFF signal22aand configured to generate a ThreshOut motion signal20aindicative of a movement (i.e., rotation) of the object24. In some embodiments described more fully below, the motion signal20ais a two state square wave having a frequency proportional to the speed of rotation of the object24.

In some arrangements, the magnetic field sensing element14can be responsive to motion of the object24, for example, motion of ferromagnetic gear teeth upon a gear, of which gear teeth24a-24cupon a gear24are representative. To this end, a fixed magnet (not shown) can be disposed proximate to the magnetic field sensing element14and the gear teeth can disturb the magnetic field generated by the magnet as the gear rotates. However, in other arrangements, the magnetic field sensing element14can be responsive to movement of magnetic regions upon a magnet, for example, magnetic regions26a-26cupon a ring magnet26. In some particular arrangements, the ring magnet26and the gear24are coupled together with a shaft or the like. In these particular arrangements, the ring magnet26can be proximate to the magnetic field sensing element14, but the gear24need not be proximate to the magnetic field sensing element14.

The magnetic field sensing element14is responsive to proximity of the ring magnet26and, in particular, to proximity of passing magnetic regions north (N) and south (S)26a-26c. In operation, the magnetic field sensing element14produces the magnetic field signal14a,14a(and also the magnetic field signals16a,22a) having a generally sinusoidal shape when the ring magnet26rotates, wherein each peak (positive and negative) of the sinusoid is associated with one of the magnetic regions N, S.

The magnetic field sensor10can also include an output protocol processor28coupled to receive the ThreshOut motion signal20aand configured to generate an output signal28arepresentative of the speed of rotation of the object24. In some embodiments the output signal28ais a two state square wave having a frequency proportional to the speed of rotation of the object24. In other embodiments, the output signal28acomprises digital words representative of the speed of rotation of the object24.

Referring now toFIG. 1A, in which like elements ofFIG. 1are shown having like reference designations, another exemplary magnetic field sensor50includes a plurality of magnetic field sensing elements52a-52cfor generating signals52aa,52ab,52ba,53bb,52ca,52cb(magnetic field signals) proportional to a magnetic field.

The magnetic field sensor50includes a right channel amplifier54coupled to the magnetic field sensing elements52aand52band configured to generate a signal54a(also a magnetic field signal). The magnetic field sensor50also includes a left channel amplifier64coupled to the magnetic field sensing elements52band52cand configured to generate a signal64a(also a magnetic field signal). The signal54ais proportional to a magnetic field at a first location relative to the object24and the signal64ais proportional to a magnetic field at a second location relative to the object24. As described more fully below, the first and second locations are associated with right and left electronic channels, respectively.

The magnetic field sensor50also includes a rotation detector56, which includes right and left channel rotation detectors, here rotation detectors56a,56b, respectively. The rotation detector56acan include an amplifier60coupled to receive the signal54aand configured to generate an RDIFF signal60a(also a magnetic field signal) representative of the signal54a. The rotation detector56bcan include an amplifier66coupled to receive the signal64aand configured to generate an LDIFF signal66a(also a magnetic field signal) representative of the signal64a. In some embodiments, the amplifiers60,66are automatic gain control (AGC) amplifiers.

The rotation detector56aalso includes a right channel threshold detector58coupled to receive the RDIFF signal60aand configured to generate an RThreshOut motion signal58aindicative of a movement (i.e., rotation) of the object24. The rotation detector56balso includes a left channel threshold detector62coupled to receive the LDIFF signal66aand configured to generate an LThreshOut motion signal62aindicative of the movement (i.e., rotation) of the object24.

In some embodiments, the motion signals58a,62aare each two state square waves having a frequency proportional to the speed of rotation of the object24. It will be understood that, since the magnetic field sensing elements52a-52care at different physical locations, the RThreshOut signal58acan have a different phase than the LThreshOut signal62a. Furthermore, if the object24rotates in one direction, the phase of the RThreshOut signal58awill lead the phase of the LThreshOut signal62a, but if the object24rotates in the opposite direction, the phase relationship will reverse. Therefore, the magnetic field sensor50, unlike the magnetic field sensor10ofFIG. 1, is able to generate signals representative not only of the speed of rotation of the object24, but also signals representative of the direction of rotation of the object24.

The above designations “left” and “right” (also L and R, respectively) are indicative of physical placement of the magnetic field sensors52a-52crelative to the object24and correspond arbitrarily to left and right channels. In the illustrative embodiment, three magnetic field sensing elements52a-52care used for differential magnetic field sensing, with the central sensor52bused in both channels. While three magnetic field sensors52a-52care shown, it should be appreciated that two or more magnetic field sensors can be used. For example, in an embodiment using only two magnetic field sensors52a,52c, only magnetic field sensor52acan be coupled to the right channel amplifier54and only the magnetic field sensor54ccan be coupled to the left channel amplifier64.

The magnetic field sensor50can also include an output protocol processor68coupled to receive the RThreshOut signal58aand the LThreshOut signal62aand configured to generate an output signal68arepresentative of at least the speed of rotation of the object24. In some embodiments, the output signal68ais also representative of the direction of rotation of the object24.

In some embodiments the output signal68ais a two state square wave having a frequency proportional to the speed of rotation of the object24and a duty cycle (or pulse width) representative of the direction of the rotation of the object24. In other embodiments, the output signal28acomprises digital words representative of the speed of rotation of the object24and the direction of rotation.

Referring now toFIG. 2, in which like elements ofFIG. 1are shown having like reference designations, a circuit100includes an exemplary rotation detector102, which can be the same as or similar to the rotation detector12ofFIG. 1, but shown in greater detail.

The rotation detector102is coupled to receive the magnetic field signal16aofFIG. 1. The magnetic field signal16acan include an undesirable DC offset. Therefore, an auto offset controller104, an offset digital-to-analog converter (DAC)106, and a summer108can be provided in order to eliminate the DC offset.

The rotation detector102can also include an automatic gain control (AGC) amplifier112coupled to receive an output signal108agenerated by the summer108and configured to generate the DIFF signal22ahaving an amplitude within a controlled amplitude range. It should be understood that the DIFF signal22ais representative of the magnetic field experienced by one or more magnetic field sensing elements, for example, the magnetic field sensing element14ofFIG. 1.

The DIFF signal22ais coupled to a threshold comparator114. The threshold comparator114also receives a threshold voltage138. Generation of the threshold voltages138is further described below. The threshold comparator114is configured to generate the ThreshOut signal20a.

The threshold voltage138can switch between two different values. In one particular embodiment, the threshold voltage138can be determined by the above-described threshold detector. A first threshold value can be a first predetermined percentage e.g., eighty-five percent, of a peak-to-peak magnitude of the DIFF signal22a, e.g., near to but below a positive peak of the DIFF signal22a. A second threshold value can be a second predetermined percentage, e.g., fifteen percent, of a peak-to-peak magnitude of the DIFF signal22a, e.g., near to but above a negative peak of the DIFF signal22a. The threshold voltage138can, therefore, be relatively near to and below a positive peak of the DIFF signal22aat some times and relatively near to and above a negative peak of the DIFF signal22aat other times. Therefore, the threshold comparator114can generate the ThreshOut signal20ahaving edges closely associated with the positive and negative peaks of the DIFF signal22a.

However, in other embodiments, the threshold signal138can take on two other different values, for example, two values near to zero crossings of the DIFF signal22a, and therefore, the threshold comparator114can generate the ThreshOut signal20ahaving edges closely associated with the zero crossings of the DIFF signal22a. In still other embodiments, the threshold signal138can take on two other different values as may be generated, for example, by a peak-referenced detector, which is described above.

The threshold voltage (or voltages)138are generated by a threshold detector116, which can be the same as or similar to the threshold detector20ofFIG. 1. The threshold detector116can include a PDAC124coupled to receive a count signal120afrom a counter120. The PDAC124is configured to generate a PDAC output signal124acoupled to a first end of a resistor ladder132. The threshold detector116can also include an NDAC126coupled to receive a count signal122afrom a counter122. The NDAC126is configured to generate an NDAC output signal126acoupled to a second end of the resistor ladder132. The PDAC output signal124aand the NDAC output signal126aare also referred to herein as tracking signals.

A first switch134is coupled to receive a signal from a first tap in the resistor ladder132and a second switch136is coupled to receive a signal from a second tap in the resistor ladder132. The first switch134can be controlled by the ThreshOut signal20aand the second switch136can be controlled by an inverted ThreshOut signal20a, i.e. a ThreshOutN signal.

The threshold detector116can also include a first comparator128coupled to receive the PDAC signal124aand also coupled to receive the DIFF signal22aand configured to generate a first feedback signal128a. The threshold detector116can also include a second comparator130coupled to receive the NDAC signal126aand also coupled to receive the DIFF signal22aand configured to generate a second feedback signal130a.

The threshold detector116can also include an update logic circuit118coupled to receive the first and second feedback signals128a,130a, respectively, and configured to generate control signals118a,118bto control the counters120,122, respectively. Operation of the threshold detector116, and, in particular, the update logic circuit118, is further described below in conjunction withFIGS. 6 and 7. Let it suffice here to say that, during a calibration time period (or initialization time period) the threshold detector116operates to set the PDAC signal124ato a positive peak of the DIFF signal22aand to set the NDAC signal126ato a negative peak of the DIFF signal22a. Thus, when the first and second switches134,136, respectively, alternately switch, the threshold voltage138toggles between two values determined by the resistor divider132and by the PDAC and NDAC signals124a,126a, respectively.

Referring now toFIG. 2A, in which like elements ofFIG. 1Aare shown having like reference designations, a circuit150includes two exemplary rotation detectors152, identified as152a,152b, which can be the same as or similar to the rotation detectors56a,56bofFIG. 1A, but shown in greater detail.

The rotation detectors152can include two threshold detectors116,164, which can be the same as or similar to the threshold detectors58,62ofFIG. 1A, but shown in greater detail. The rotation detector152ais coupled to receive the magnetic field signal54aofFIG. 1Aand the rotation detector152bis coupled to receive the magnetic field signal64aofFIG. 1A. The rotation detector152ais configured to generate the RThreshOut signal58a(FIG. 1A) and the RDIFF signal60a(FIG. 1A), and the rotation detector152bis configured to generate the LThreshOut signal62a(FIG. 1A) and the LDIFF signal66a(FIG. 1A).

Operation of each one of the two rotation detectors152a,152bis the same as or similar to operation of the rotation detector102ofFIG. 2, so is not discussed here again.

Referring now toFIG. 3, a graph200has a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of voltage. The graph200includes a DIFF signal202representative, for example, of the DIFF signal22aofFIGS. 1 and 2. In normal operation, with a relatively low frequency, i.e., a slowly varying, DIFF signal202, a PDAC signal204, which is similar to the PDAC signal124aofFIG. 2, can reach and acquire positive peaks of the DIFF signal202within a small number of cycles of the DIFF signal202. Similarly, an NDAC signal206, which is similar to the NDAC signal126aofFIG. 2, can reach and acquire negative peaks of the DIFF signal202within a small number of cycles of the DIFF signal202.

A ThreshOut signal210, which is similar to the ThreshOut signal20aofFIG. 2, has edges210a-210dthat align with points202a-202d, respectively, of the DIFF signal202. It will be appreciated that, in some embodiments, the points202aand202ccan correspond to a predetermined percentage, e.g., fifteen percent, of a peak-to-peak magnitude of the DIFF signal202, e.g., near to but above a negative peak of the DIFF signal202, and the points202band202dcan correspond to a first predetermined percentage e.g., eighty-five percent, of a peak-to-peak magnitude of the DIFF signal202, e.g., near to but below a positive peak of the DIFF signal202

A first threshold value can be a first predetermined percentage e.g., eighty-five percent, of a peak-to-peak magnitude of the DIFF signal22a, e.g., near to but below a positive peak of the DIFF signal22a. A second threshold value can be a second predetermined percentage, e.g., fifteen percent, of a peak-to-peak magnitude of the DIFF signal22a, e.g., near to but above a negative peak of the DIFF signal22a.

A signal220changes state at a time corresponding to an edge220a, when the calibration is deemed to be successful and adequate in ways described more fully below. Before the edge220a, the prior art rotation detector is in the initialization or calibration mode, wherein the rotation detector is establishing the PDAC signal204and the NDAC signal206, here at or near the peaks of the DIFF signal202. After the edge220a, the prior art rotation detector is in a running mode, in which case the rotation detector102is deemed to provide a proper ThreshOut signal210.

In the prior art, timing of the edge220a, and therefore, the end of the calibration time period, is determined by counting a predetermined number of cycles of the ThreshOut signal210, for example, three cycles. For the slowly varying DIFF signal202, the calibration time period generally is sufficiently long to acquire the positive and negative peaks of the DIFF signal202.

Referring now toFIG. 4, a graph250has a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of voltage. The graph250includes a DIFF signal252representative, for example, of the DIFF signal22aofFIGS. 1 and 2. In normal operation with a relatively high frequency, i.e., a quickly varying, DIFF signal252, a PDAC signal254, which is similar to the PDAC signal124aofFIG. 2, does not have time to reach and acquire positive peaks of the DIFF signal252within a small number of cycles of the DIFF signal252. Similarly, an NDAC signal256, which is similar to the NDAC signal126aofFIG. 2, does not have time to reach and acquire negative peaks of the DIFF signal252within a small number of cycles of the DIFF signal252.

A ThreshOut signal260, which is similar to the ThreshOut signal20aofFIGS. 1 and 2, has edges260a-260d. It will be appreciated that, in some embodiments, the edges260aand260ccan correspond to a predetermined percentage, for example, fifteen percent, by which the DIFF signal252is above the NDAC signal256, and the edges260band260dcan correspond to a predetermined percentage, for example, fifteen percent, by which the DIFF signal252is below the PDAC signal254.

A signal270changes state at a time corresponding to an edge270a, when the calibration is deemed to be successful and adequate in ways described more fully below. Before the edge270a, the prior art rotation detector is in the initialization or calibration mode, wherein the prior art rotation detector is establishing the PDAC signal254and the NDAC signal256.

As described above in conjunction withFIG. 3, in the prior art, timing of the edge270a, and therefore, the end of the initialization time interval, is determined by counting a predetermined number of cycles of the ThreshOut signal260, for example, three cycles. For the rapidly varying DIFF signal252, the resulting amount of time is not sufficient to acquire the positive and negative peaks of the DIFF signal252and the ThreshOut signal260has edges that are not at desired points near peaks of the DIFF signal252.

Referring now toFIG. 5, a graph300has a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of voltage. The graph300includes a DIFF signal302representative, for example, of the DIFF signal22aofFIGS. 1 and 2. In normal operation with a relatively low frequency, i.e., a slowly varying DIFF signal302, a PDAC signal304, representative of the PDAC signal124aofFIGS. 2 and 2A, can reach and acquire positive peaks of the DIFF signal302within a small number of cycles of the DIFF signal302, for example, within one cycle. Similarly, an NDAC signal306, representative of the NDAC signal126aofFIGS. 2 and 2A, can reach and acquire negative peaks of the DIFF signal202within a small number of cycles of the DIFF signal302, for example, within one cycle.

Also shown, for a rapidly varying DIFF signal302, a PDAC signal308, representative of the PDAC signal124aofFIGS. 2 and 2A, can reach and acquire positive peaks of the DIFF signal302within a larger number of cycles of the DIFF signal302. Similarly, an NDAC signal310, representative of the NDAC signal126aofFIGS. 2 and 2A, can reach and acquire negative peaks of the DIFF signal302within a larger number of cycles of the DIFF signal302.

The PDAC signal308attempts to track the DIFF signal302between times t0and t2, t3and t4, and t7and t8, eventually achieving a positive peak of the DIFF signal at about time t8. The PDAC signal308holds at other times. The NDAC signal310attempts to track the DIFF signal302between times t0and t1, t2and t3, and t5and t6, eventually achieving a negative peak of the DIFF signal302at about time t6. The NDAC signal310holds at other times.

Referring now toFIG. 5A, a graph320has a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of voltage. The graph320includes a signal322having parts322aand322b. It will be apparent from discussion below that the signal322is representative of a logical combination (OR) of the first and second feedback signals (e.g.,128a,130a, respectively, ofFIG. 2). The signal322, like the PDAC signal304and the NDAC signal306ofFIG. 5, is representative of a slowly varying DIFF signal302. The part322ais representative of times when the PDAC signal304is updating, or tracking the DIFF signal302. The part322bis representative of times when the NDAC signal306is updating, or tracking the DIFF signal302.

Referring now toFIG. 5B, a graph340has a horizontal axis with a scale in arbitrary units of time and a vertical axis with a scale in arbitrary units of voltage. The graph340includes a signal342. It will be apparent from discussion below that the signal342is representative of a logical combination (OR) of the first and second feedback signals (e.g.,128a,130a, respectively, ofFIG. 2). The signal342, like the PDAC signal308and the NDAC signal310ofFIG. 5, is representative of a rapidly varying DIFF signal302. The signal342has high states representative of times when either the PDAC signal308or the NDAC signal310ofFIG. 5are updating, or tracking the DIFF signal302.

ComparingFIGS. 5A and 5B, it will be apparent that a time between movements of the DACS (e.g.,124,126ofFIG. 2) becomes greater as final DAC values are approached, i.e., as the DACS approach the positive and negative peaks.

Referring now toFIG. 6, a circuit350can be the same as or similar to a portion of a threshold detector, for example, a portion of the threshold detector circuit116ofFIG. 2. The circuit350can include an update logic circuit364that can be the same as or similar to the update logic circuit118ofFIG. 2.

The circuit350can include a counter352configured to generate a counter signal352a. The counter352can be the same as or similar to the counter120ofFIG. 2. The circuit350can include a PDAC354coupled to receive the counter signal352aand configured to generate a PDAC signal354a. The PDAC354can be the same as or similar to the PDAC124ofFIG. 2.

The circuit350can also include a counter358configured to generate a counter signal358a. The counter358can be the same as or similar to the counter122ofFIG. 2. The circuit350can include an NDAC360coupled to receive the counter signal358aand configured to generate an NDAC signal360a. The NDAC360can be the same as or similar to the NDAC126ofFIG. 2.

The circuit350can also include a comparator356coupled to receive the PDAC signal354a, coupled to receive a DIFF signal378, for example the DIFF signal22aofFIG. 2, and configured to generate a feedback signal356a. The comparator356can be the same as or similar to the comparator128ofFIG. 2. The circuit350can also include a comparator362coupled to receive the NDAC signal360a, coupled to receive the DIFF signal378, and configured to generate a feedback signal362a. The comparator362can be the same as or similar to the comparator130ofFIG. 2.

It will be understood that the feedback signal356ais representative of, i.e., has a state according to, whether the DIFF signal378is above or below the PDAC signal354a. Similarly, the feedback signal362ais representative of, i.e., has a state according to, whether the DIFF signal378is above or below the NDAC signal360a.

The update logic circuit364can include an update controller366, which, for example, can be in the form of a microprocessor, a programmable gate array (PGA), or any such programmable or non-programmable device. The update controller366is coupled to receive the feedback signals356a,362aand configured to generate a first signal366a(peak reset) for resetting the counters352,358, a second signal366b(positive clock) for clocking the counter352, a third signal366c(negative clock) for clocking the counter358, a fourth signal366d(timer reset) described more fully below, a fifth signal (timer clock) described more fully below, a sixth signal366f(peaks/speed OK) to indicate if the update logic circuit has successfully calibrated (i.e., if the PDAC354and the NDAC360have reached and acquired peaks of the DIFF signal378), a sixth signal366g(up/down #1) coupled to cause the counter352to count up or down, and a seventh signal366h(up/down #2) coupled to cause the counter358to count up or down.

The update logic circuit364can include a timer circuit368. The timer circuit368can include a counter370coupled to receive the timer clock signal366eat a clock input and the timer reset signal366dat a reset input. The counter370is configured to generate a count signal370a. The timer circuit368can also include a DAC372coupled to receive the count signal370aand configured to generate a DAC signal372a. The timer circuit368can also include a comparator374coupled to receive a timer threshold signal376, coupled to receive the DAC signal372a, and configured to generate a signal374arepresentative of the timer circuit368having timed a predetermined time since the last change of state of the timer reset signal366d.

The counter352can be coupled to receive the positive clock signal366bat a clock input node, coupled to receive the peak reset signal366aat a reset node, and coupled to receive the up/down #1signal366gat an up/down control node. Similarly, the counter358can be coupled to receive the negative clock signal366cat a clock input node, coupled to receive the peak reset signal366aat a reset node, and coupled to receive the up/down #2signal366hat an up/down control node.

In operation, the update logic circuit, in response to the feedback signals356a,362aand in response to the comparison signal374a, generates the various control signals366a-366hin order to cause the counters352,358to count at the proper times, causing the PDAC354and the NDAC360to move toward the positive and negative peaks, respectively, of the DIFF signal378.

Once the PDAC354and the NDAC360have reached the positive and negative peaks, respectively, of the DIFF signal378, the feedback signals356a,362ano longer change state as the DIFF signal378moves in voltage throughout its cycles. The timer circuit368can time a predetermined time interval after the feedback signals356a,362astop changing state, at which time the comparison signal374achanges state (as will occur when the PDAC output signal354areaches a positive peak of the DIFF signal378and when the NDAC output signal360areaches a negative peak of the DIFF signal378), indicating to the update controller366that the calibration time period has ended. At this time, the sixth signal366f(peaks/speed OK) can change state, indicating to other circuits that the calibration time period has ended and that the running mode can begin.

It should be understood that the calibration time period ends in the above way, not after a predetermined number of changes of state of the ThreshOut signals201,260ofFIGS. 3 and 4, respectively, as described above, but instead after a predetermined time period has elapsed since an end of updates of the PDAC354and updates of the NDAC360. In other words, the timer circuit368determines if a first time period since an end of the PDAC update time interval is greater than a predetermined time threshold determined by the counter370and determines if a second time period since an end of the NDAC update time interval is greater than the predetermined time threshold. Thus, for either a slowly changing or a quickly changing DIFF signal378, the portion350of the threshold detector circuit has sufficient time to properly acquire the positive and negative peaks of the DIFF signal378.

In some embodiments, two criteria must be met in order to end the calibration time period. Namely, in some embodiments, the calibration time period ends both after a predetermined number of changes of state of the ThreshOut signals201,260ofFIGS. 3 and 4, respectively, and also only after a predetermined time period has elapsed since an end of updates of the PDAC354and updates of the NDAC360. Conceptually, this is because a sufficient number of target features must be observed and enough time must pass for the DACs to observe them.

While one timer circuit368is shown, which is responsive to both of the comparison signals356aand362a, i.e., to both the PDAC354and to the NDAC360, it should be appreciated that, in other embodiments, there can be two timer circuits, each having a counter, and each of which can have the same timer threshold376or different timer thresholds. Therefore, since the circuit350can be replicated two times in conjunction with the circuit152ofFIG. 2A, in some embodiments, there can be up to four timer thresholds. Furthermore, any number of the four timer thresholds can be the same timer threshold.

Referring now toFIG. 6A, a timer circuit400can be used in place of the timer circuit368ofFIG. 6. The timer circuit400includes a presetable counter402, which can be preset to a predetermined count404. The counter402can be coupled to receive a timer clock signal406at a clock input and a timer preset signal408at a preset input. The counter370is configured to generate a count signal410. The timer clock signal406can be the same as or similar to the timer clock signal366eofFIG. 6, the timer preset signal408can be the same as or similar to the timer reset signal366dofFIG. 6, and the count signal410can be the same as or similar to the comparison signal374aofFIG. 6.

The timer circuit400can count down or up from the preset count404so as to reach zero, whereupon the count signal410changes state. Thus, like the timer circuit368ofFIG. 6, the timer circuit400determines if a first time period since an end of the PDAC update time interval is greater than a predetermined time threshold determined by the counter402and determines if a second time period since an end of the NDAC update time interval is greater than the predetermined time threshold.

It should be appreciated thatFIG. 7shows a flowchart corresponding to the below contemplated technique which would be implemented in an update logic circuit (364FIG. 6). Rectangular elements (typified by element422inFIG. 7), herein denoted “processing blocks,” represent computer software instructions or groups of instructions. Diamond shaped elements (typified by element424inFIG. 7), herein denoted “decision blocks,” represent computer software instructions, or groups of instructions, which affect the execution of the computer software instructions represented by the processing blocks.

Referring toFIG. 7, an exemplary method420, begins at block422, where a positive peak identifier signal, e.g., the PDAC signal354aofFIG. 6, is set low, a negative peak identifier signal, e.g., the NDAC signal360aofFIG. 6, is set high, and a timer circuit, e.g., the time r circuit368ofFIG. 6is reset.

At block424, it is detected if a signal, e.g., the DIFF signal378ofFIG. 6, is above the positive peak identifier signal, e.g.,354aofFIG. 6. At the first pass through the method420, since the positive peak identifier signal354awas set low at block422, the DIFF signal378is above the positive peak identifier signal354aand the process proceeds to block434.

At block434, the positive peak identifier (e.g., PDAC354) is clocked upward a predetermined number of times, typically one time, e.g., the counter352ofFIG. 6is clocked, the timer circuit, e.g., the timer circuit368, is reset, and the process continues to block426. In other embodiments, the positive peak identifier is clocked more than once.

At block426, it is detected if the signal, e.g., the DIFF signal378ofFIG. 6, is below the negative peak identifier signal, e.g.,360aofFIG. 6. At the first pass through the method420, since the negative peak identifier signal360awas set high at block422, the DIFF signal378is below the negative peak identifier signal360aand the process proceeds to block436.

At block436, the negative peak identifier (e.g., NDAC364) is clocked downward a predetermined number of times, typically one time, e.g., the counter358ofFIG. 6is clocked, the timer circuit, e.g., the timer circuit368, is reset, and the process continues to block428. In other embodiments, the negative peak identifier is clocked more than once.

At block428, the timer circuit, e.g., the timer circuit368ofFIG. 6is clocked a predetermined number of times, e.g., one time.

At block430, it is determined if the timer circuit, e.g., the timer circuit368, has reached the timer threshold378ofFIG. 6. At block430, on the first pass through the method420, the timer circuit368would not have reached the timer threshold376and the process returns to block424.

At block424, once the positive peak identifier signal354ahas reached a value such that the DIFF signal never exceeds the positive peak identifier signal354a, then the process continues directly to block426. At block426, once the negative peak identifier signal360ahas reached a value such that the DIFF signal never falls below the negative peak identifier signal360a, then the process continues to block428.

Thus, the process stops resetting the timer circuit368, which would otherwise occur at blocks434and436, but instead continues to clocks the timer circuit368each time the process420arrives at block428. Eventually, at block430, the timer circuit368reaches the timer threshold376and the process420reaches block432.

At block432, an indication of an acceptable DIFF signal speed and/or a peak acquisition is given, e.g., by way of a change of state of the peaks/peed OK signal366fofFIG. 6.