Wafer processing method

A wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate includes forming a mask on a back side of the wafer, so as to form an etched groove along each street through a thickness of the substrate from the back side of the wafer, performing plasma etching from the back side of the wafer through the mask to the substrate after forming the mask, thereby forming the etched groove in the substrate along each street so that the etched groove has a depth equal to the thickness of the substrate, and applying a laser beam to the device layer along each street from the front side of the wafer before etching and mask forming, thereby forming a device layer dividing groove corresponding to the etched groove along each street.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate, the device layer being partitioned by a plurality of crossing streets to thereby define a plurality of separate regions where a plurality of devices are respectively formed.

Description of the Related Art

In order to reduce the width of each street, thereby increasing the number of devices that can be obtained from a wafer or to reduce the time required for processing of the wafer, there has been proposed what is generally called plasma dicing for dividing the wafer into individual device chips by using plasma etching (see Japanese Patent Laid-open No. 2006-114825, for example).

SUMMARY OF THE INVENTION

However, the processing method described in Japanese Patent Laid-open No. 2006-114825 has the following problem. A wafer having devices formed on a front side has a device layer forming the devices. The device layer is composed of a circuit layer (metal layer) and an insulating layer. This device layer is also present on each street. Accordingly, when etching gas suitable for etching of silicon (substrate) is used, it is very difficult to etch the device layer present on each street.

Further, in the processing method described in Japanese Patent Laid-open No. 2006-114825, plasma etching is performed through a mask to the wafer from the front side thereof. Accordingly, if the thickness of the mask is not uniform, there is a possibility for the mask to be partially removed in a thin area of the mask during plasma etching, so that the front side of the wafer is exposed to cause damage to the devices.

It is therefore an object of the present invention to provide a wafer processing method which can divide a wafer into individual device chips while suppressing damage to the devices.

In accordance with an aspect of the present invention, there is provided a wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate, the device layer being partitioned by a plurality of crossing streets to thereby define a plurality of separate regions where a plurality of devices are respectively formed, the wafer processing method comprising a mask forming step of forming a mask on a back side of the wafer, so as to form an etched groove along each street through a thickness of the substrate from the back side of the wafer; a plasma etching step of performing plasma etching from the back side of the wafer through the mask to the substrate after performing the mask forming step, thereby forming the etched groove in the substrate along each street so that the etched groove has a depth equal to the thickness of the substrate; and a device layer dividing step of applying a laser beam to the device layer along each street from a front side of the wafer before performing the plasma etching step and the mask forming step, thereby forming a device layer dividing groove corresponding to the etched groove along each street.

Preferably, a width of the etched groove on the front side of the substrate is larger than a width of the device layer dividing groove on a lower surface of the device layer.

Preferably, the device layer dividing groove comprises two dividing grooves extending along each street so as to be formed at opposite ends along the width of the etched groove on the front side of the substrate.

Preferably, the wafer processing method further comprises a protective member providing step of providing a protective member on the front side of the wafer so as to cover the device layer after performing the device layer dividing step; and a transfer step of providing a support member on the back side of the wafer and removing the protective member from the front side of the wafer, after performing the plasma etching step.

The wafer processing method of the present invention has an effect that the wafer can be divided into individual device chips while suppressing damage to the devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will now be described in detail with reference to the drawings. The present invention is not limited to the preferred embodiments. In addition, the components used in the preferred embodiments may include those that can be easily assumed by persons skilled in the art or substantially the same elements as those known in the art. Moreover, the configurations described below may suitably be combined. Further, the configurations may be variously omitted, replaced, or changed without departing from the scope of the present invention.

First Preferred Embodiment

A wafer processing method according to a first preferred embodiment of the present invention will now be described with reference to the drawings.FIG. 1is a perspective view depicting a wafer1as a workpiece to be processed by the wafer processing method according to the first preferred embodiment.FIG. 2is a sectional view of an essential part of the wafer1, taken along the line II-II inFIG. 1.FIG. 3is a flowchart depicting the flow of the wafer processing method according to the first preferred embodiment.

The wafer processing method according to the first preferred embodiment is a processing method for the wafer1depicted inFIG. 1. The wafer1is a disk-shaped semiconductor wafer or an optical device wafer having a substrate2formed of silicon, sapphire, or gallium arsenide, for example. As depicted inFIGS. 1 and 2, the wafer1includes the substrate2having a front side3, and a device layer4formed on the front side3of the substrate2. Further, a plurality of crossing streets5are formed on the front side3of the substrate2to define a plurality of separate regions where a plurality of devices6are respectively formed. In the first preferred embodiment, the plural crossing streets5intersect at right angles. The substrate2has a back side7opposite to the front side3. In other words, the back side7of the substrate2is the back side of the wafer1.

Each device6is an integrated circuit (IC) or large scale integration (LSI), for example. The device layer4forms the plural devices6. The device layer4includes a plurality of circuit layers of metal forming the circuits in each device6and a plurality of insulating layers formed from low-permittivity insulating films (which will hereinafter be referred to as low-k films), in which these plural circuit layers and these plural insulating layers are alternately stacked. In other words, each device6is formed by alternately stacking the plural circuit layers of metal forming the circuits and the plural insulating layers of low-k films supporting the circuit layers. Each insulating layer of low-k film is an interlayer insulating film.

The wafer processing method according to the first preferred embodiment is a method for dividing the wafer1along the plural streets5to obtain individual device chips respectively including the plural devices6. As depicted inFIG. 3, the wafer processing method according to the first preferred embodiment includes a device layer dividing step ST1, a protective member providing step ST2, a mask forming step ST3, a plasma etching step ST4, a mask removing step ST5, and a pickup step ST6.

FIG. 4is a partially sectional side view schematically depicting the device layer dividing step ST1of the wafer processing method depicted inFIG. 3.FIG. 5is a plan view depicting an essential part of the wafer1in the condition where the device layer dividing step ST1of the wafer processing method depicted inFIG. 3is finished.FIG. 6is a sectional view taken along the line VI-VI inFIG. 5.FIG. 7is an enlarged view of a box part VII inFIG. 6.

The device layer dividing step ST1is a step of applying a laser beam31(seeFIG. 4) to the device layer4along each street5from the front side3of the substrate2of the wafer1before performing the plasma etching step ST4and the mask forming step ST3, thereby forming a device layer dividing groove20(seeFIG. 5) corresponding to an etched groove10(seeFIG. 5) to be formed in the plasma etching step ST4. The device layer dividing step ST1is performed by using a laser processing apparatus30depicted inFIG. 4. The laser processing apparatus30includes a chuck table32having a holding surface33and a laser beam applying unit34for applying the laser beam31. In the device layer dividing step ST1, the back side7of the substrate2of the wafer1is held under suction on the holding surface33of the chuck table32. Thereafter, an imaging unit (not depicted) is used to image the wafer1held on the chuck table32. According to an image obtained by the imaging unit, alignment is performed to adjust the positional relation between the wafer1and the laser beam applying unit34.

Thereafter, the chuck table32and the laser beam applying unit34are relatively moved in a horizontal direction along each street5. At the same time, the laser beam31having an absorption wavelength to the wafer1is applied from the laser beam applying unit34to each street5as depicted inFIG. 4. In the first preferred embodiment, the laser beam31is applied to the lateral end portions of each street5to thereby form a pair of device layer dividing grooves20along each street5. This operation is similarly performed along all of the streets5to form a plurality of device layer dividing grooves20along all of the streets5. That is, each device layer dividing groove20is formed by performing ablation of the device layer4along each street5.

As depicted inFIGS. 5, 6, and 7, at least the device layer4is removed at the lateral end portions of each street5by applying the laser beam31, thereby forming the pair of device layer dividing grooves20along each street5so that the substrate2is exposed to the pair of device layer dividing grooves20at the lateral end portions of each street5. Thus, two device layer dividing grooves20parallel to each other are formed along each street5so as to divide the device layer4. As depicted inFIG. 7, the two device layer dividing grooves20along each street5are two dividing grooves for dividing the device layer4at the opposite ends along width11of the etched groove10on the front side3of the substrate2.

Each device layer dividing groove20extends linearly in a longitudinal direction of each street5. In the first preferred embodiment, a part of the substrate2is also removed by each device layer dividing groove20. The two device layer dividing grooves20along each street5are formed at two positions equally spaced from the center of each street5in its lateral direction. InFIG. 7, reference numeral21denotes the distance between the bottoms of the two device layer dividing grooves20along each street5. This distance21is equal to the distance between the focal points of the laser beams31applied to form the two device layer dividing grooves20along each street5. This distance21is smaller than the width11of the etched groove10on the front side3of the substrate2. Further, reference numeral22denotes the distance between the outer edges of the two device layer dividing grooves20along each street5on the lower surface (back side) of the device layer4. The width11of the etched groove10on the front side3of the substrate2is larger than the distance22. In the first preferred embodiment, the distance22between the outer edges of the two device layer dividing grooves20along each street5on the lower surface of the device layer4corresponds to a width of a device layer dividing groove formed along each street on the lower surface of the device layer according to the present invention.

Further, the focal points of the laser beams31for forming the two device layer dividing grooves20along each street5are set so that the difference between the width11of the etched groove10on the front side3of the substrate2and the distance22between the outer edges of the two device layer dividing grooves20on the lower surface of the device layer4is greater than 0 μm but not greater than 30 μm.

In the first preferred embodiment, the device layer dividing step ST1may be performed under the following conditions, for example. The wavelength of the laser beam31is 355 nm. The power of the laser beam31is 2.5 W. The repetition frequency of the laser beam31(pulsed laser beam) is 150 kHz. The relatively moving speed of the laser beam applying unit34and the wafer1is 400 mm/sec. After finishing the device layer dividing step ST1, the wafer processing method depicted inFIG. 3proceeds to the protective member providing step ST2.

FIG. 8is a perspective view of the wafer1in the condition where the protective member providing step ST2of the wafer processing method depicted inFIG. 3is finished. The protective member providing step ST2is a step of providing an adhesive tape200as a protective member on the front side3of the substrate2so as to cover the device layer4after performing the device layer dividing step ST1.

In the protective member providing step ST2, the adhesive tape200is a circular tape larger in diameter than the wafer1. The adhesive tape200is attached to the device layer4formed on the front side3of the substrate2of the wafer1as depicted inFIG. 8. A central portion of the adhesive tape200is attached to the device layer4. Further, a ring frame210is attached to a peripheral portion of the adhesive tape200as depicted inFIG. 8. As depicted inFIG. 10, the adhesive tape200is composed of a base layer201and an adhesive layer202formed on one side of the base layer201. The base layer201is formed of an insulating synthetic resin. InFIG. 8, the device layer dividing grooves200are not depicted. While the adhesive tape200larger in diameter than the wafer1is used as a protective member in the first preferred embodiment, the protective member is not limited to the adhesive tape200in the present invention. For example, an adhesive tape having the same diameter as that of the wafer1may be used as the protective member, in which this adhesive tape is composed of the base layer201and the adhesive tape202. Further, a disk-shaped hard plate having the same diameter as that of the wafer1may also be used as the protective member, in which this hard plate is formed of a hard material. In other words, the ring frame210may be omitted. After finishing the protective member providing step ST2, the wafer processing method depicted inFIG. 3proceeds to the mark forming step ST3.

FIG. 9is a sectional side view schematically depicting a condition that a solution of water-soluble resin is supplied to the back side7of the wafer1in the mask forming step ST3of the wafer processing method depicted inFIG. 3.FIG. 10is a sectional view of an essential part of the wafer1in the condition where the water-soluble resin has been applied to the back side7of the wafer1in the mask forming step ST3of the wafer processing method depicted inFIG. 3.FIG. 11is a sectional view schematically depicting a condition that a laser beam is applied to the water-soluble resin on the back side7of the wafer1in the mask forming step ST3of the wafer processing method depicted inFIG. 3.FIG. 12is a sectional view of an essential part of the wafer1in the condition where the mask forming step ST3of the wafer processing method depicted inFIG. 3is finished.

The mask forming step ST3is a step of forming a mask40(seeFIG. 12) on the back side7of the wafer1so as to form the etched groove10along each street5through the thickness of the substrate2from the back side7of the wafer1in the plasma etching step ST4. As depicted inFIG. 9, the mask forming step ST3is performed by using a coating and cleaning apparatus50. The coating and cleaning apparatus50includes a spinner table51having a holding surface52and a water-soluble resin solution nozzle54for supplying a water-soluble resin solution41. A plurality of clamps53are provided on the outer circumference of the spinner table51. In the mask forming step ST3, the front side3of the wafer1is held under suction through the adhesive tape200on the holding surface52of the spinner table51. Further, the ring frame210is fixed by the plural clamps53to the spinner table51.

Thereafter, the spinner table51is rotated about its vertical axis and the water-soluble resin solution41is supplied from the water-soluble resin solution nozzle54to the back side7of the substrate2of the wafer1. The water-soluble resin solution41is a solution of water-soluble resin such as polyvinyl alcohol (PVA) or polyvinyl pyrrolidone (PVP).

After supplying the water-soluble resin solution41to the back side7of the substrate2of the wafer1to coat the back side7with the water-soluble resin solution41, the solution41is dried or heated to be cured, thereby forming a resin layer42on the back side7of the wafer1as depicted inFIG. 10. In other words, the resin layer42is formed by curing the water-soluble resin solution41supplied to the whole of the back side7of the substrate2of the wafer1. After coating the whole of the back side7of the wafer1with the resin layer42, the suction holding of the wafer1on the spinner table51is canceled and the clamping of the ring frame210by the clamps53is also canceled.

Thereafter, the resin layer42is grooved by using a laser processing apparatus60depicted inFIG. 11. The laser processing apparatus60includes a chuck table62having a holding surface63and a laser beam applying unit64for applying a laser beam61. In the mask forming step ST3, the front side3of the substrate2of the wafer1is held under suction through the adhesive tape200on the holding surface63of the chuck table62. Thereafter, an infrared camera (not depicted) is used to image the wafer1held on the chuck table62and thereby detect the streets5. According to an image obtained by the infrared camera, alignment is performed to adjust the positional relation between the wafer1and the laser beam applying unit64.

Thereafter, the chuck table62and the laser beam applying unit64are relatively moved in a horizontal direction along each street5. At the same time, the laser beam61having an absorption wavelength to the resin layer42is applied from the laser beam applying unit64to the resin layer42at the position corresponding to the center of each street5in the lateral direction thereof. This operation is similarly performed along all of the streets5to form a plurality of grooves43along all of the streets5so that each groove43has a depth equal to the thickness of the resin layer42. In other words, each groove43is formed by performing ablation of the resin layer42along each street5.

As depicted inFIG. 12, the resin layer42is removed at the position corresponding to the center of each street5in the lateral direction thereof by applying the laser beam61, thereby forming the groove43along each street5so that the back side7of the substrate2is exposed to the groove43at the position corresponding to the center of each street5in the lateral direction thereof. Thus, the resin layer42in which the plural grooves43respectively corresponding to the plural streets5have been formed becomes the mask40to be used in the plasma etching step ST4, in which the mask40is resistant to plasma. Each groove43extends linearly in the longitudinal direction of each street5at the position corresponding to the center of each street5in the lateral direction thereof.

InFIG. 12, reference numeral12denotes the width of each groove43. The width12of each groove43is equal to the width of each etched groove10on the back side7of the substrate2. This width12is larger than the distance21mentioned above but smaller than the distance22mentioned above. After finishing the mask forming step ST3to form the mask40, the wafer processing method depicted inFIG. 3proceeds to the plasma etching step ST4. As described above, each groove43is formed in the mask forming step ST3so that the difference between the width11of the etched groove10on the front side3of the substrate2and the distance22between the outer edges of the two device layer dividing grooves20on the lower surface of the device layer4is greater than 0 μm but not greater than 30 μm.

FIG. 13is a sectional view depicting the configuration of an etching apparatus70to be used in the plasma etching step ST4of the wafer processing method depicted inFIG. 3.FIG. 14is a schematic sectional view of an essential part of the wafer1in the condition where the plasma etching step ST4of the wafer processing method depicted inFIG. 3is finished.FIG. 15is an enlarged view of a box part XV inFIG. 14.

The plasma etching step ST4is a step of performing plasma etching from the back side7of the substrate2of the wafer1through the mask40to the substrate2after performing the mask forming step ST3, thereby forming a plurality of etched grooves10in the substrate2respectively along the plural streets5so that each etched groove10has a depth equal to the thickness of the substrate2. The plasma etching step ST4is performed by using the etching apparatus70depicted inFIG. 13. The etching apparatus70includes a chamber73having a load/unload opening72. The load/unload opening72is closed by a gate valve71. In operation, the gate valve71is opened to load the wafer1supported through the adhesive tape200to the ring frame210from the load/unload opening72. The front side3of the wafer1is electrostatically held through the adhesive tape200on an electrostatic chuck (ESC)74. In electrostatically holding the wafer1on the electrostatic chuck74, electric power is supplied from a bias radio frequency (RF) power source76through a matching unit75to an electrode77provided in the electrostatic chuck74.

Thereafter, an evacuating unit79is operated to evacuate the inside space of the chamber73through an evacuation pipe78, thereby reducing the pressure inside the chamber73to a predetermined pressure. Further, the temperature of the electrostatic chuck74is adjusted to a predetermined temperature at which no gas is generated from the adhesive tape200. In this condition, an etching step and a film deposition step are alternately repeated. The etching step is a step of etching the substrate2exposed to the bottom of each groove43of the mask40, thereby forming each etched groove10on the back side7of the substrate2and advancing each etched groove10toward the front side3of the substrate2. The film deposition step is a step of depositing a film on an inside surface of each etched groove10after performing the etching step. In the etching step after performing the film deposition step, the film deposited on the bottom of each etched groove10is removed and the bottom of each etched groove10is next etched. In this manner, the plasma etching step ST4uses what is generally called a Bosch process to perform plasma etching to the wafer1. In other words, in the plasma etching step ST4, the wafer1is divided into individual device chips respectively including the devices6by performing what is generally called plasma dicing.

In the etching step, SF6gas as etching gas is supplied from a gas supplying unit80through a gas pipe81and a gas inlet opening82to a gas discharge head83. The SF6gas thus supplied is discharged from a plurality of gas discharge openings84toward the wafer1held on the electrostatic chuck74. In the condition where the SF6gas for generating plasma is supplied to the gas discharge head83, RF power for generating a plasma and maintaining it is applied from an RF power source86through a matching unit85to the gas discharge head83, and RF power for drawing ions is applied from the RF power source86to the electrostatic chuck74. Accordingly, isotropic plasma dissociated from the SF6gas is generated in the space between the electrostatic chuck74and the gas discharge head83. This plasma is drawn through each groove43of the mask40into the substrate2of the wafer1to thereby etch the bottom of each groove43and the bottom of each etched groove10. Further, each etched groove10is advanced toward the front side3of the substrate2of the wafer1.

In the film deposition step, C4F8gas as deposition gas is supplied from the gas supplying unit80to the gas discharge head83and discharged from the gas discharge openings84toward the wafer1held on the electrostatic chuck74. In the condition where the C4F8gas for generating plasma is supplied to the gas discharge head83, RF power for generating plasma and maintaining it is applied from the RF power source86to the gas discharge head83, and RF power for drawing ions is applied from the RF power source86to the electrostatic chuck74. Accordingly, plasma dissociated from the C4F8gas is generated in the space between the electrostatic chuck74and the gas discharge head83. This plasma is drawn into the substrate2of the wafer1to thereby deposit a film on the inside surface of each etched groove10.

In the plasma etching step ST4, the number of repetitions of the etching step and the film deposition step is previously set according to the thickness of the substrate2of the wafer1. By performing the etching step and the film deposition film by the preset number of repetitions, the wafer1is etched so that each etched groove10reaches the front side3of the substrate2as depicted inFIGS. 14 and 15. Further, since the two device layer dividing grooves20are formed to divide the device layer4along each street5before performing the plasma etching step ST4, the wafer1is divided into individual device chips respectively including the devices6.

In general, steps are formed on the inside surface of each etched groove10according to the number of repetitions of the etching step and the film deposition step. However, these steps are not depicted inFIG. 14and other drawings. Further, with the advance of each etched groove10, the width of each etched groove10is gradually increased or decreased (in the first preferred embodiment, the width of each etched groove10is gradually increased). However, the width of each etched groove10is depicted to be constant inFIG. 14and the other drawings.

As depicted inFIG. 15, the width11of each etched groove10on the front side3of the substrate2is larger than the distance22on the lower surface (the back side) of the device layer4in the condition where the plasma etching step ST4is finished. Further, the difference between the width11and the distance22is greater than 0 μm but not greater than 30 μm.

While the etching apparatus70depicted inFIG. 13is used in the plasma etching step ST4in the first preferred embodiment, the etching apparatus usable in the present invention is not limited to the etching apparatus70depicted inFIG. 13. After finishing the plasma etching step ST4, the wafer processing method depicted inFIG. 3proceeds to the mask removing step ST5.

FIG. 16is a schematic sectional side view depicting the mask removing step ST5of the wafer processing method depicted inFIG. 3. The mask removing step ST5is a step of removing the mask40after performing the plasma etching step ST4.

As depicted inFIG. 16, the mask removing step ST5is performed by using the coating and cleaning apparatus50used in the mask forming step ST3. The coating and cleaning apparatus50further includes a cleaning water nozzle56for supplying cleaning water57such as pure water.

In the mask removing step ST5, the wafer1is held on the spinner table51in a manner similar to that in the mask forming step ST3. Thereafter, the spinner table51is rotated about its vertical axis, and the cleaning water57is supplied from the cleaning water nozzle56to the back side7of the substrate2of the wafer1.

The cleaning water57supplied to the back side7of the substrate2flows toward the outer circumference of the wafer1due to a centrifugal force generated by the rotation of the spinner table51, so that the resin layer42forming the mask40is removed because the resin layer42is formed of water-soluble resin, thus cleaning the back side7of the wafer1. After supplying the cleaning water57for a predetermined period of time to clean the back side7of the wafer1and next drying the wafer1, the rotation of the spinner table51is stopped. Further, the suction holding of the wafer1on the spinner table51and the clamping of the ring frame210by the clamps53are also canceled. Thereafter, the wafer processing method depicted inFIG. 3proceeds to the pickup step ST6.

FIG. 17is a schematic sectional view depicting the pickup step ST6of the wafer processing method depicted inFIG. 3.FIG. 18is an enlarged view of a box part XVIII inFIG. 17. The pickup step ST6is a step of separating each device chip including the device6from the adhesive tape200.

As depicted inFIG. 17, the pickup step ST6is performed by using a pickup apparatus90having a pickup member91. In the pickup step ST6, each of the individual device chips respectively including the devices6is held by the pickup member91of the pickup apparatus90and then raised to be separated from the adhesive tape200as depicted inFIG. 17. Since the individual device chips are held separately by the pickup member91, a portion4-1between the two device layer dividing grooves20along each street5in the device layer4is left on the adhesive tape200as depicted inFIG. 17. When all of the individual device chips are separated from the adhesive tape200, the wafer processing method depicted inFIG. 3is ended.

As described above, the wafer processing method according to the first preferred embodiment includes the plasma etching step ST4of performing plasma etching from the back side7of the substrate2of the wafer1. Accordingly, there is no possibility for the devices6to be exposed in a thin region of the mask40during plasma etching, so that damage to the devices6can be suppressed.

Further, the wafer processing method according to the first preferred embodiment includes the device layer dividing step ST1of forming the device layer dividing groove20along each street5in the device layer4before performing the plasma etching step ST4.

Accordingly, by performing the plasma etching step ST4to perform plasma etching from the back side7of the substrate2through the thickness of the substrate2, the wafer1can be divided into the individual device chips respectively including the devices6. In other words, the wafer1can be divided into the individual device chips while suppressing damage to the devices6.

Further, in the condition where the plasma etching step ST4is finished, the width11of each etched groove10on the front side3of the substrate2is larger than the distance22on the lower surface of the device layer4. Accordingly, a thermally affected area generated in the substrate2at a position below the device layer dividing groove20by the application of the laser beam31can be removed by the plasma etching. As a result, as compared with the case where the width11of each etched groove10on the front side3of the substrate2is smaller than the distance22on the lower surface of the device layer4, the die strength of each device chip can be improved.

Further, in the device layer dividing step ST1, the two device layer dividing grooves20are formed in the device layer4at the lateral end portions of each street5. Accordingly, in the pickup step ST6, the portion4-1between the two device layer dividing grooves20along each street5in the device layer4is left on the adhesive tape200. As a result, time and effort for removing the portion4-1can be eliminated.

Further, the difference between the width11of each etched groove10on the front side3of the substrate2and the distance22on the lower surface of the device layer4is greater than 0 μm but not greater than 30 μm. Accordingly, an amount4-2of projection of the device layer4from the side surface of the substrate2of each device chip as depicted inFIG. 18becomes greater than 0 μm but not greater than 15 μm. As a result, in addition to the effect that the die strength of each device chip can be improved by making the width11larger than the distance22, the projection amount4-2can be minimized to thereby suppress chipping of a portion of the device layer4projecting from the side surface of the substrate2, so that defective mounting of each device chip can be suppressed and possible separation of the device layer4from the substrate2in each device chip can also be suppressed.

Further, in the device layer dividing step ST1, the two device layer dividing grooves20are formed in the device layer4at the lateral end portions of each street5. Accordingly, as compared with the case of forming a single device layer dividing groove along each street5, the power of the laser beam31can be reduced. As a result, each device layer dividing groove20can be formed in one pass of the laser beam31, thereby suppressing a reduction in productivity. Furthermore, it is possible to suppress the damage in the thermally affected area generated in the substrate2at the position below each device layer dividing groove20by the application of the laser beam31.

Second Preferred Embodiment

A wafer processing method according to a second preferred embodiment of the present invention will now be described with reference to the drawings.FIG. 19is a flowchart depicting the flow of the wafer processing method according to the second preferred embodiment.FIG. 20is a perspective view depicting a transfer step included in the wafer processing method depicted inFIG. 19.FIG. 21is a sectional view of an essential part of the wafer1, taken along the line XXI-XXI inFIG. 20.FIG. 22is a schematic sectional view depicting a pickup step included in the wafer processing method depicted inFIG. 19. InFIGS. 19, 20, 21, and 22, the same parts as those in the first preferred embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

As depicted inFIG. 19, the wafer processing method according to the second preferred embodiment is the same as the first preferred embodiment except a transfer step ST10is added. The transfer step ST10is a step of providing an adhesive tape220, as a support member, on the back side7of the wafer1and removing the adhesive tape200as the protective member from the front side3(the device layer4) of the wafer1, after performing the plasma etching step ST4and the mask removing step ST5.

As depicted inFIGS. 20 and 21, the adhesive tape220is a circular tape larger in diameter than the wafer1, and a central portion of the adhesive tape220is attached to the back side7of the substrate2of the wafer1. A peripheral portion of the adhesive tape220is attached to the ring frame210. Thereafter, the adhesive tape220is peeled off from the device layer4of the wafer1and is also peeled off from the ring frame210. As depicted inFIG. 21, the adhesive tape220is composed of a base layer221and an adhesive layer222formed on one side of the base layer221. The base layer221is formed of an insulating synthetic resin. In the transfer step ST10, the portion4-1between the two device layer dividing grooves20along each street5in the device layer4is left on the adhesive tape200and thereby removed from the wafer1.

While the adhesive tape220larger in diameter than the wafer1is used as the support member in the second preferred embodiment, the support member usable in the present invention is not limited to the adhesive tape220depicted inFIGS. 20 and 21. For example, an adhesive tape having a diameter equal to that of the wafer1may be used as the support member without using the ring frame210, in which this adhesive tape is composed of the base layer221and the adhesive tape222. After finishing the transfer step ST10, the wafer processing method depicted inFIG. 19proceeds to the pickup step ST6.

In the pickup step ST6of the wafer processing method depicted inFIG. 19, a pickup apparatus90depicted inFIG. 22is used. The pickup apparatus90depicted inFIG. 22is the same as that depicted inFIG. 17. As depicted inFIG. 22, the device layer4of each device chip is held by the pickup member91of the pickup apparatus90and then raised to be separated from the adhesive tape220. When all of the individual device chips are separated from the adhesive tape220, the wafer processing method depicted inFIG. 19is ended.

The wafer processing method according to the second preferred embodiment also includes the plasma etching step ST4of performing plasma etching from the back side7of the substrate2of the wafer1. Accordingly, damage to the devices6can be suppressed. Further, the wafer processing method according to the second preferred embodiment also includes the device layer dividing step ST1of forming the device layer dividing groove20along each street5in the device layer4before performing the plasma etching step ST4. Accordingly, by performing the plasma etching step ST4, the wafer1can be divided into the individual device chips respectively including the devices6. Thus, as similar to the first preferred embodiment, the wafer processing method according to the second preferred embodiment has the effect that the wafer1can be divided into the individual device chips while suppressing damage to the devices6.

In addition, the wafer processing method according to the second preferred embodiment includes the transfer step ST10, in which the portion4-1between the two device layer dividing grooves20along each street5in the device layer4can be removed together with the adhesive tape200, so that time and effort for removing the portion4-1can be eliminated.

A wafer processing method according to a modification of the first and second preferred embodiments of the present invention will now be described with reference to the drawings.FIG. 23is a sectional view depicting an essential part of the wafer1in the condition where a device layer dividing step ST1included in the wafer processing method according to this modification is finished. InFIG. 23, the same parts as those in the first and second preferred embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

The wafer processing method according to this modification is the same as that according to the first and second preferred embodiments except the device layer dividing step ST1is different. In the device layer dividing step ST1of the wafer processing method according to this modification, the laser beam31(seeFIG. 4) is applied to the center of each street5in the lateral direction thereof, thereby forming a single device layer dividing groove20-1along each street5at the lateral center thereof as depicted inFIG. 23, in which this single device layer dividing groove20-1along each street5is a dividing groove for dividing the device layer4.

In this modification, the width11of each etched groove10on the front side3of the substrate2is larger than the width22-1of the single device layer dividing groove20-1on the lower surface of the device layer4as depicted inFIG. 23. Further, in this modification, the focal point of the laser beam31is set to form the device layer dividing groove20-1along each street5so that the difference between the width11of each etched groove10on the front side3of the substrate2and the width22-1of the device layer dividing groove20-1on the lower surface of the device layer4is greater than 0 μm but not greater than 30 μm.

The wafer processing method according to this modification also includes the plasma etching step ST4of performing plasma etching from the back side7of the substrate2of the wafer1. Accordingly, damage to the devices6can be suppressed. Further, the wafer processing method according to this modification also includes the device layer dividing step ST1of forming the device layer dividing groove20-1along each street5in the device layer4before performing the plasma etching step ST4. Accordingly, by performing the plasma etching step ST4, the wafer1can be divided into the individual device chips respectively including the devices6. Thus, as similar to the first and second preferred embodiments, the wafer processing method according to this modification has the effect that the wafer1can be divided into the individual device chips while suppressing damage to the devices6.

The present inventors confirmed the effect of the wafer processing method according to the first preferred embodiment.FIG. 24depicts the present invention, andFIG. 25depicts a comparison. The wafer1depicted inFIG. 24and the wafer1depicted inFIG. 25were divided by the wafer processing method according to the first preferred embodiment to obtain the individual device chips respectively including the devices6. Then, the die strength of each device6was measured.FIG. 24is a sectional view of an essential part of the wafer1in the present invention in the condition where the mask forming step is finished.FIG. 25is a sectional view of an essential part of the wafer1in the comparison in the condition where the mask forming step is finished. InFIGS. 24 and 25, the same parts as those in the first preferred embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

As depicted inFIG. 24, the wafer1in the present invention has the following configuration. The width of each groove43of the mask40, i.e., the width12of each etched groove10on the back side7of the substrate2, is larger than the distance21but smaller than the distance22. Further, the width11of each etched groove10on the front side3of the substrate2is larger than the distance22. More specifically, the width12of each etched groove10on the back side7of the substrate2was set to 33 μm, the distance21was set to 30 μm, the distance22was set to 42 μm, and the width11of each etched groove10on the front side3of the substrate2was set to 46 μm.

On the other hand, as depicted inFIG. 25, the wafer1in the comparison has the following configuration. The width of each groove43of the mask40, i.e., the width12of each etched groove10on the back side7of the substrate2, is smaller than both the distance21and the distance22. Further, the width11of each etched groove10on the front side3of the substrate2is larger than the distance21but smaller than the distance22. More specifically, the width12of each etched groove10on the back side7of the substrate2was set to 30 μm, the distance21was set to 40 μm, the distance22was set to 52 μm, and the width11of each etched groove10on the front side3of the substrate2was set to 43 μm.

Both in the present invention and in the comparison, the width of each etched groove10in the plasma etching step ST4was gradually increased with the advance of etching (with an increase in depth of each etched groove10). Both in the present invention and in the comparison, the die strength of each device chip was measured and the average of the die strengths of the plural device chips was determined. As the result, the average of the die strengths of the plural device chips in the comparison was 470 MPa, whereas the average of the die strengths of the plural device chips in the present invention was 530 MPa. Accordingly, it became apparent that the die strength of each device chip can be improved by setting the width12of each etched groove10on the back side7of the substrate2larger than the distance21but smaller than the distance22and further setting the width11of each etched groove10on the front side3of the substrate2larger than the distance22.

Further, the present inventors confirmed the effect of the wafer processing method according to the first preferred embodiment by changing the projection amount4-2mentioned above. The result is depicted in Table 1. In Table 1, “Comparison #1” is the case where the projection amount4-2was set to 0 μm, “Invention #1” is the case where the projection amount4-2was set to 1 μm, “Invention #2” is the case where the projection amount4-2was set to 15 μm, and “Comparison #2” is the case where the projection amount4-2was set to 17 μm. In Table 1, the case where the die strength was equal to or greater than a predetermined value is indicated by a circle, whereas the case where the die strength was less than the predetermined value is indicated by a cross. Further, in Table 1, the case where defective mounting due to the chipping or separation of each device chip or the separation of the device layer4was not observed is indicated by a circle, whereas the case where such defective mounting or the separation of the device layer4was observed is indicated by a cross.

According to Table 1, the die strength in “Comparison #1” is not acceptable as indicated by a cross, whereas the die strength in “Invention #1” and the die strength in “Invention #2” are both acceptable as indicated by circles. Accordingly, it became apparent that the die strength of each device chip can be improved by setting the width11of each etched groove10on the front side3of the substrate2larger than the distance22and setting the difference between this width11and the distance22to a value greater than 0 μm but not greater than 30 μm.

Further, according to Table 1, defective mounting or the separation of the device layer was observed in “Comparison #2,” whereas defective mounting or the separation of the device layer was not observed both in “Invention #1” and in “Invention #2.” Accordingly, it became apparent that the defective mounting of each device chip and the separation of the device layer4can be suppressed by setting the width11of each etched groove10on the front side3of the substrate2larger than the distance22and setting the difference between this width11and the distance22to a value greater than 0 μm but not greater than 30 μm.

The present invention is not limited to the above preferred embodiments and various modifications may be made without departing from the scope of the present invention. For example, while the mask40is formed from the resin layer42of water-soluble resin in the first and second preferred embodiments, the mask40may be formed from a die attach film (DAF) or back protective sheet (protective sheet for the back side of a flip chip, this protective sheet being left on the back side7of each device chip obtained by dividing the wafer1). In this case, the DAF or the back protective sheet is first attached to the back side7of the wafer1in the condition where the protective member providing step ST2is finished. Thereafter, a laser beam is applied to the DAF or the back protective sheet along each street5from the back side7of the wafer1, thereby performing ablation to form each groove43and thereby form the mask40. As another modification, ultraviolet (UV) curing resin curable by applying ultraviolet light may be applied to the back side7of the wafer1in the condition where the protective member providing step ST2is finished. Thereafter, nano-imprint may be performed to the UV curing resin applied, thereby forming each groove43to form the mask40.