Digital currency mining circuitry having shared processing logic

An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.

BACKGROUND

This relates to digital currencies, and more particularly, to mining digital currencies.

Digital currencies serve as a digital medium of exchange in which the digital currencies may be transferred in exchange for goods and services. Crypto-currencies are examples of digital currencies in which cryptography governs the creation and exchange of value. An example of a cryptocurrency is the bitcoin cryptocurrency that is governed by the Bitcoin protocol. This is in contrast to traditional mediums of exchange that are governed, for example, by a central authority.

The Bitcoin protocol defines a system in which the creation and distribution of the bitcoin cryptocurrency is governed by consensus among a peer-to-peer network. The network maintains a public ledger in which new transactions are verified and recorded by members of the network via cryptography. The operations of verifying and recording transactions of cryptocurrencies such as transactions in the bitcoin cryptocurrency are sometimes referred to as mining, because completion of each mining operation typically rewards the miner with newly created cryptocurrency (e.g., bitcoins). Verified transactions and newly created bitcoins are recorded in the public ledger. The public ledger serves as an official history of transactions. The amount of cryptocurrency owned by any entity may be determined from the public ledger.

Bitcoin mining operations involve identifying a solution to a cryptographic puzzle in which transactions that are to be verified form part of the puzzle parameters. Bitcoin mining operations are typically performed via brute-force techniques (e.g., an exhaustive search for a puzzle solution performed across all possible solutions). The difficulty of the cryptographic puzzle has led to the use of dedicated circuitry designed specifically for Bitcoin mining. Such dedicated circuitry can be expensive to design, purchase, and operate.

SUMMARY OF THE INVENTION

An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include processing circuitry that mines digital cryptocurrency by completing a cryptographic function according to a protocol that governs the digital cryptocurrency. The integrated circuit may include control circuitry and a number of processing cores that complete the cryptographic function in parallel. As an example, the control circuitry may control the processing cores to complete a Secure Hash Algorithm 256 (SHA-256) function in parallel for generating Bitcoin rewards based on a Bitcoin protocol.

The integrated circuit may, for example, include first, second, and third processing cores. Shared logic circuitry may be shared between each of the first, second, and third processing cores. The shared logic circuitry may be formed on a region of the integrated circuit occupied by the first, second, and/or third processing cores. The control circuitry may provide control signals to the shared logic circuitry to control the first, second, and third processing cores to complete the cryptographic function in parallel. The control circuitry may control the processing cores to complete the cryptographic function over respective first, second, and third different search spaces. The shared logic circuitry may, if desired, complete a portion of the cryptographic function corresponding to an overlap between the search spaces.

The first processing core may, for example, include a first cryptographic hashing circuit whereas the second processing core includes a second cryptographic hashing circuit and the third processing core includes a third cryptographic hashing circuit. Each of the hashing circuits may include a sequence of rounds of cryptographic hashing logic that performs a cryptographic hashing algorithm based on an initial hash value received from the control circuitry and message input words received from message scheduling circuitry. The shared logic circuitry may perform a subset of the sequential rounds (e.g., one or more leading rounds) of the cryptographic hashing algorithm for at least the first, second, and third processing cores.

Message scheduling circuitry may receive different respective messages for each of the processing cores from the control circuitry. The message scheduling circuitry may generate the message input words based on the received messages. In accordance with any of the above arrangements, the shared logic circuitry may form a portion of the message scheduling circuitry. The shared logic circuitry may generate a selected message input word based on first, second, and third messages received for the first, second, and third processing cores respectively. The shared logic circuitry may provide the selected message input word to each of the first, second, and third processing cores. The first, second, and third processing cores may perform at least one of the sequential rounds of the cryptographic hashing algorithm based on the selected message input word.

If desired, partially shared logic circuitry may be shared by the first and second processing cores but not the third processing core. An input of the partially shared logic circuitry may be coupled to an output of the shared logic circuitry. The partially shared logic circuitry may generate an additional message word based on the first and second messages and may provide the additional message word to the first and second processing cores (e.g., without providing the additional message word to the third core) for performing at least one of the sequential rounds of the cryptographic hashing algorithm (e.g., rounds that are subsequent to those performed using the selected message word generated by the shared logic circuitry). If desired, unshared logic circuitry may be formed on the first processing core but not on the second and third processing cores. An input of the unshared logic circuitry may be coupled to an output of the partially shared logic circuitry and the unshared logic circuitry may be configured to generate a message word for at least one of the sequential rounds of the first processing core.

The first processing core may generate a first hash output value based on at least one of the message word generated by the unshared logic circuitry. The hash output value may be combined with an initial hash value at adder circuitry to generate a final hash value. The final hash value may be provided to data padding circuitry or difficulty comparison circuitry for further processing.

In accordance with any of the above arrangements, a first round of cryptographic hashing circuitry may be implemented on a given processing core and may generate a first hash value based on an input value and a first message word received from message scheduling circuitry. A second round of cryptographic hashing circuitry that is implemented on two different processing cores may receive the first hash value from the first round of cryptographic hashing circuitry and may generate second and third hash values based on the first hash value and a second message word. A final round of cryptographic hashing circuitry may generate a first hash output value based at least partly on the second hash value and a third message word and may generate a second hash output value based at least partly on the third hash value and the third message word. For example, a number of intermediate sequential rounds of cryptographic hashing circuitry may be interposed between the second round and the final round. By sharing logic circuitry among the processing cores, chip area consumption and power efficiency may be improved relative to scenarios where the processing cores are formed using only dedicated logic.

Further features will be more apparent from the accompanying drawings and the following detailed description.

DETAILED DESCRIPTION

The present invention relates to mining of digital currencies such as crypto-currencies. Mining circuitry and mining operations described herein may be used for any digital medium of exchange such as digital currencies, credits, rewards, or points.

FIG. 1is an illustrative diagram of a peer-to-peer network100that may operate according to the Bitcoin protocol. Network100includes nodes10that are coupled to other nodes via paths12. Nodes10may be electronic devices such as desktop computers, laptop computers, cellular telephones, servers, or other electronic devices that implement the Bitcoin protocol. Each node10may communicate with other nodes of network100over paths12. Paths12may, for example, include network paths such as network cables and packet forwarding devices (e.g., switches, routers, etc.) that couple nodes10to other nodes. This example is merely illustrative. Nodes10of network100may be coupled via any desired underlying communications technology such as wired or wireless network technologies and network100may include any desired number of nodes (e.g., tens, hundreds, thousands, millions, or more).

Nodes10may communicate over paths12according to the Bitcoin protocol in maintaining the cryptocurrency. For example, nodes10may communicate to maintain a global ledger of all official transactions. Each node10may store a copy of the global ledger (e.g., a complete copy or only a partial copy). Transactions added to the global ledger by each node10may be verified by other nodes10to help ensure validity of the ledger.

FIG. 2is an illustrative diagram of an electronic device110that may serve as a node in a peer-to-peer network (e.g., as a node10ofFIG. 1). As shown inFIG. 2, device110may include storage and processing circuitry112. Storage and processing circuitry112may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in storage and processing circuitry112may be used to control the operation of device110. This processing circuitry may be based on one or more general purpose processing circuits such as microprocessors, microcontrollers, and digital signal processors, or dedicated processing circuits such as application specific integrated circuits, etc.

Device110may be provided with input-output devices114such as buttons, speakers, microphones, displays, and other input-output devices that accommodate user interaction with device110. Input-output devices114may include communications circuitry for communicating with other devices (e.g., other nodes of a cryptocurrency network). Mining circuitry116may perform mining operations such as verifying cryptocurrency transactions (e.g., while sharing any rewards or the mining operations between multiple entities such as a user of the device). Mining circuitry116may record the rewards in the global ledger. Mining circuitry116may, for example, be an integrated circuit chip. Electronic device110may include one or more of these chips that may be operated together or independently.

Electronic device110may be a desktop computer, a server in a rack-based system, a portable electronic device such as a tablet computer, laptop computer, or a cellular telephone. These examples are merely illustrative. Mining circuitry116may be provided to any desired electronic device that can communicate with other nodes of a cryptocurrency network. For example, a flash drive that connects with a computer may be provided with mining circuitry116. In this scenario, the mining circuitry116may operate to perform mining operations by utilizing computer resources when the flash drive is connected to a computer (e.g., by utilizing power from the computer and a network connection between the computer and nodes of a cryptocurrency network).

FIG. 3is a diagram of an illustrative cryptocurrency transaction120that may be verified using mining circuitry such as circuitry116ofFIG. 2. As shown inFIG. 3, transaction120may include header information122, a set of one or more inputs124, and a set of one or more outputs126.

Header information122may include one or more header fields including information that helps to identify the transaction. For example, the header fields may include a version number identifying the version of the Bitcoin protocol that is used. As another example, the header fields may include a current timestamp and/or other information on the transaction.

Digital currency may be stored in digital wallets that serve as sources or destinations of transactions. For example, a transaction may transfer funds from a source wallet to a destination wallet. Digital wallets may be formed using any desired data structure and may sometimes be referred to as digital accounts. Wallets may be identified using encryption schemes such as public-key cryptography in which a public-private key pair is assigned to each wallet. The public key of a wallet may serve to publicly identify the wallet (e.g., a public address to which funds may be directed), whereas the private key may be used by the owner of the wallet to sign transactions (e.g., thereby verifying the authenticity of the transactions).

Transaction120may identify an input124(e.g., a source of funds) and a set of outputs126(e.g., destinations). The inputs and outputs may, for example, be digital wallets in which currency is stored. The inputs may refer to an output of a previous transaction as a source of funding or may identify that transaction120is an originating transaction that creates new currency (sometimes referred to as a coinbase transaction).

FIG. 4is a diagram of an illustrative transaction130that transfers currency from a source wallet to a destination wallet. Transaction130may be, for example, a data packet or sequence (stream) of data packets having corresponding header fields124and126. As shown inFIG. 4, input124may include a previous transaction identifier, an output identifier, and a signature. If desired, header information122ofFIG. 3such as version number or timestamp information may be included in the transaction ofFIG. 5.

The previous transaction identifier may identify which transaction of the global ledger contains the source wallet. The previous transaction identifier may, if desired, identify the previous transaction TXPREV by a hash (e.g., H(TXPREV)) or double-hash (e.g., H(H(TXPREV)) or DH(TXPREV)) of the previous transaction. The output identifier may identify which output of the identified previous transaction serves as the source wallet of transaction130. For example, the outputs126of the previous transaction may be enumerated and the index of the source wallet may serve as the output identifier.

Transaction130may be signed to help ensure authenticity of the transaction. For example, the private key of the source wallet may be used to encrypt transaction130or a portion of transaction130to generate the signature that is stored in transaction130. The public key of the source wallet may be used by others (e.g., other network nodes) to decrypt the signature and confirm the authenticity of the transaction.

The set of outputs126identifies one or more destination wallets and a respective amount to transfer from the source wallet to each destination wallet. In the example ofFIG. 4, the transaction includes one destination wallet and a corresponding amount to be transferred from the source wallet to the destination wallet. Multiple destination wallets (e.g., two, three, four, or more) may be listed along with corresponding amounts to be transferred to each destination wallet from the source wallet. If desired, the source wallet identified by input124may also be listed as a destination wallet. For example, the amount to be transferred to the destination wallet may be less than the amount identified by the output of the previous transaction as belonging to the source wallet. In this scenario, the difference between the amount of the source wallet and the transfer amount may be assigned to the source wallet as an additional output entry. If desired, the amount assigned in outputs126to the source wallet may be less than the difference between the originally stored amount and the transfer amount. In this scenario, the difference between original source amount and the sum of amounts in output126may serve as additional reward for any miner that verifies the transaction (e.g., in addition to any predetermined reward defined by the cryptocurrency protocol).

FIG. 5is an illustrative diagram of an originating transaction (i.e., coinbase transaction) that may generate new digital currency. As shown inFIG. 5, transaction140includes information that identifies the transaction as a coinbase transaction. The information may include a reserved coinbase identifier142, a block height144, and an extra-nonce value146. If desired, header information122ofFIG. 3such as version number or timestamp information may be included in the transaction ofFIG. 5.

Reserved coinbase identifier142may be a value that is reserved for coinbase transactions. Block height144may help identify where the coinbase transaction is located within the global ledger (e.g., which block of a block chain that represents the global ledger). Extra-nonce value146is an arbitrary value that may be modified during mining operations.

In contrast to normal transactions such as transaction130ofFIG. 4, coinbase transaction140does not provide a source of funds for outputs126. Instead, coinbase transaction140may create new currency. The amount of new currency created is determined by the cryptocurrency protocol. For example, nodes of the cryptocurrency network may communicate and establish an agreed-upon reward that is created for verifying transactions. The agreed-upon reward may be determined based on the size of the global ledger (e.g., how many recorded blocks are in the global ledger). As an example, the reward for verifying and recording transactions in the Bitcoin protocol may reward a number of bitcoins (units of currency) such as 25 bitcoins. This example is merely illustrative, as the number of bitcoins rewarded may be less than 25 (e.g., 12.5, 6.25, etc.) or may even be zero.

In some scenarios, transactions that are verified using mining circuitry may include fees. For example, transaction130ofFIG. 4may assign fewer bitcoins to destination wallets than contained in the source wallet. In this scenario, the remainder may serve as fees (e.g., an additional reward) for a miner. This additional reward may be assigned to the miner's wallet in coinbase transaction140or may also be partitioned by the mining circuitry between the miner's wallets and other wallets (e.g., profit-sharing wallets).

In performing mining operations to verify and record a set of transactions, mining circuitry may generate a block to be recorded in the global ledger as shown inFIG. 6. Block150ofFIG. 6may include block header152, coinbase transaction TX0(e.g., a coinbase transaction140), and a set of transactions156to be recorded.

Block header152may include information that identifies block150and additional information generated by the mining circuitry to complete a function such as information satisfying a cryptographic puzzle. The additional information may be generated to solve the function (e.g., puzzle) for a given set of function inputs that are at least partially determined by block header152and for a desired output or range of outputs.FIG. 7is a diagram of an illustrative block header152. As shown inFIG. 7, block header152may include header fields162, a previous block identifier164, a Merkle root166, a timestamp168, a difficulty value170, and a nonce value172.

Header fields162may include any desired header fields such as a version number of the Bitcoin protocol. Previous block identifier164may identify a previous block in the global ledger (e.g., the global ledger may be a chain of blocks152in which each block references a previous block in the chain). For example, the previous block identifier may be a hash of the block header of the previous block.

Merkle root166may be generated from the transactions of block150including coinbase transaction140and the set of transactions156. Merkle root166may provide a compact representation of the transactions in block150. For example, Merkle root166may be a 256-bit (32 Byte) value, whereas the transactions of block150may be hundreds, thousands, or millions of bytes.

Difficulty value170is a parameter of the function (e.g., cryptographic puzzle) that is solved with block150. For the Bitcoin protocol, the cryptographic puzzle involves generating block header152such that the hash of block header152is less than a predetermined value. The hash may be calculated using a protocol-determined hash function such as the Secure Hash Algorithm (SHA). The predetermined value may depend on difficulty value170. For example, difficulty value170may specify how many leading zeros in a binary data representation are required in the hashed block header value.

Mining circuitry116may adjust one or more of the fields in block header152in order to provide block header152with a hash value that solves the cryptographic puzzle (e.g., a sufficiently small hash value). For example, the mining circuitry may adjust the nonce value or the timestamp value. As another example, the mining circuitry may adjust the extra-nonce value in the coinbase transaction of the block, which indirectly adjusts the Merkle root. Mining circuitry116may perform exhaustive search by iterating over all possible solutions to the cryptographic puzzle.

Hash functions used by the cryptographic puzzle may operate in sequential steps (sometimes referred to herein as stages) on block header152. If desired, a first portion174of block header152may be processed in a first hashing stage, whereas a second portion176of block header152may be processed in a second, subsequent hashing stage. Each hashing stage may involve a number of so-called rounds of logical operations. Each round of logical operations may involve the same logical functions (e.g., operating on different inputs for each round). For example, the output of a given round of logical operations in the hashing function may serve as an input for a subsequent round of the logical operations. The logical operations may iteratively be performed in this way to produce an output of the hashing function. For example, when a Secure Hashing Algorithm (SHA) 256 function is used, second portion176of block header152may be operated on by 64 rounds of SHA-256 before producing a hash output (e.g., an initial input to logical circuitry implementing the SHA-256 hashing algorithm may be operated on by the logic circuitry and provided as an input to a subsequent round of logic circuitry identical to the previous round of logical circuitry, and so on until the desired number of rounds of logic functions have been performed). This example is merely illustrative. The number of rounds of hashing may depend on the hashing algorithm performed by mining circuitry116.

Portion174may include header fields162, previous block identifier164, and a first portion of Merkle root166, whereas portion176may include a second portion of Merkle root166, timestamp168, difficulty value170, and nonce value172. The SHA function may produce an output value for the first stage based on portion174of block header152. The output value of the first stage may serve as an input to the second stage of the SHA function along with portion176of block header152. The second stage of the SHA function may produce the hash value of block header152. The SHA function may be implemented using dedicated hardware circuitry on mining circuitry116.

Merkle root166may be computed by generating a Merkle tree from the transactions of the corresponding block150.FIG. 8is a diagram of an illustrative Merkle tree180generated from a block including transactions TX0, TX1, TX2, TX3, TX4, TX5, TX6, and TX7. The example ofFIG. 8in which the block includes eight transactions is merely illustrative. A Merkle tree may be computed from any binary number of transactions (e.g., 2, 4, 6, 8, etc.). If a block does not contain a binary number of transactions, placeholder transactions may be added to complete the Merkle tree. Such placeholder transactions are used only in generating the Merkle tree and are not added to the block.

As shown inFIG. 8, Merkle tree180includes leaf nodes182that are each generated by computing the double hash of a respective transaction (e.g., using the SHA function). For example, hash value H0is computed from the (double) hash (DH) of transaction TX0(e.g., a coinbase transaction), whereas hash values H1, H2, H3, H4, H5, H6, and H7are computed from transactions TX1, TX2, TX3, TX4, TX5, TX6, and TX7, respectively. Double hash operations may involve performing a cryptographic hashing function H(Z) on an input Z to generate an output Y and performing the same cryptographic hashing function H on the output Y of the first cryptographic hashing function to generate a double hashed output X (e.g., X=H(H(Z))), for example.

Merkle tree180may be organized as a binary tree in which each non-leaf node184has two child nodes. The nodes of each successive level of the tree may be computed by hashing nodes of a lower (previous) level. The second level of the tree (e.g., the nodes storing hash values H8, H9, H10, and H11) may be generated by double hashing the values stored in leaf nodes182. For example, hash value H8is generated by concatenating leaf values H0and H1and double hashing the concatenated result. Similarly, the third level of the tree may be generated by hashing the values of the second level (e.g., hash value H12may be calculated by hashing the concatenation of H8and H9, whereas hash value H13may be calculated by hashing the concatenation of H10and H11). The number of levels in the tree may depend on the number of transactions in the block. In the example ofFIG. 8, the root of Merkle tree180is at the fourth level and is calculated from hashing values H12and H13.

The hashed value at each node of Merkle tree180has a fixed, predetermined size (e.g., 256 bits), and is dependent on the values at the children of that node. The Merkle root therefore serves as a compact representation of all of the transactions in the corresponding block, because any changes to a transaction percolate upwards to the Merkle root. For example, changes to coinbase transaction TX0causes hash value H8to change, which modifies hash value H12, which then modifies the Merkle root value. Similarly, changes to any of the transactions result in changes to the Merkle root value.

Mining circuitry116may generate some or all of Merkle tree180while searching for solutions to a cryptographic puzzle. For example, in iterating through extra-nonce values in a coinbase transaction TX0, the mining circuitry may need to re-compute the Merkle root for each new extra-nonce value. To help reduce computation time and improve performance, the mining circuitry may re-compute only a portion of Merkle tree180during each iteration. In particular, changes to coinbase transaction TX0only affect hash values H0, H8, H12, and the Merkle root, whereas the remaining nodes of the Merkle tree are unchanged. Dotted line186represents the edge of the Merkle tree that separates hash values that need to be recomputed and hash values that remain unchanged when modifying coinbase transaction TX0. Nodes to the left of edge186need to be recomputed (portion188of tree180), whereas nodes to the right of edge186do not need to be recomputed (portion190of tree180). The mining circuitry can store the constant nodes at edge186and reuse the stored values to re-compute the Merkle root. In the example ofFIG. 8, hash values H1, H9, and H13may be stored, whereas the remaining hash values of tree portion190do not need to be stored. If desired, nodes to the left of edge186may be computed off-chip by circuitry external to mining circuitry116(e.g., to save processing time, power, and chip area on mining circuitry116).

FIG. 9is an illustrative diagram of a global ledger that is formed from a block chain200. As shown inFIG. 9, block chain200may include an originating block150′ that does not point to any previous block. For example, the previous block identifier164of block150′ does not identify any other blocks. Each successive block150identifies the previous block in the chain as shown by arrows202(e.g., the previous block identifier164of each block identifies the previous block in block chain200).

During mining operations, a device collects a set of transactions that have not already been recorded in block chain200. The mining circuitry may identify the last (most recently recorded) block in block chain200. The mining circuitry may subsequently generate a new block150from the set of transactions such that the new block includes an identifier164that identifies the last block of block chain200and solves the cryptographic puzzle of the cryptocurrency protocol used by the block chain.

It is possible for block chain200to include multiple branches. For example, branch204may be generated when different puzzle solutions are discovered that each have the same previous block identifier. In this scenario, the branch that is longer and includes more blocks serves as the global register. In other words, branch204is ignored and the transactions in block150of branch204are not considered to be recorded, because branch206includes more blocks than branch204(i.e., four connected blocks in branch206compared to only three in branch204).

Mining circuitry such as circuitry116ofFIG. 2may be implemented as a dedicated integrated circuit (e.g., an application-specific integrated circuit) as shown in the diagram ofFIG. 10. As shown inFIG. 10, integrated circuit116may have input-output (I/O) circuitry212for driving signals off of device116and for receiving signals from other devices via input-output pins214. For example, I/O circuitry212and pins214may convey signals between mining circuitry116and other circuitry on electronic device110ofFIG. 2. As shown inFIG. 10, mining circuitry116may receive data from off-chip processing circuitry such as processing circuitry215. Off-chip circuitry215may be used to pre-compute portions of the hashing functions performed by circuitry116. For example, off-chip circuitry215may compute hash values of portion174of block header152as shown inFIG. 7and may provide the hash value (e.g., hash value Hi) to circuitry116. In another suitable arrangement, hash value Himay be provided by mining control circuitry216. Circuitry116may use hash value Hias an input when performing hashing functions on portion176of block header152.

Mining circuitry116may include a core region218and control circuitry216that is coupled to the core region by paths224such as interconnect paths. Core region218may include multiple core circuits220that may be controlled by control circuitry216to identify solutions to a cryptographic puzzle. For example, each core circuit220may include dedicated logic that performs a cryptographic algorithm such as the SHA function on inputs provided by control circuitry216over paths224. Core region218may include any desired number of core circuits that are operated in parallel by control circuitry216(e.g., tens, hundreds, or more core circuits).

The inputs provided by control circuitry216to a given core220may include a partially filled block header. For example, the partially filled block header may include header fields162, previous block identifier164, a current time, and difficulty value170. The inputs may include the Merkle root of the transactions of the block to be solved, the transactions themselves, or sufficient information for computing the Merkle root (e.g., Merkle tree edge186ofFIG. 8). The inputs may include hash values Hicomputed by off-chip processing circuitry215. The remaining fields of the block header and block may be generated by core220in attempting to solve the cryptographic puzzle with inputs provided by the control circuitry.

Control circuitry216may partition the search space of possible solutions to the cryptographic puzzle and assign each core circuit220a different portion of the search space (e.g., so that multiple core circuits220operating in parallel can more efficiently search for solutions to the cryptographic puzzle). The search space may be partitioned based on the inputs provided by the control circuitry to the core circuits. The search space may be partitioned, for example, by assigning different ranges of nonce values172to different cores220, by assigning different ranges of extra nonce values to different cores220, etc.

If desired, each core circuit220in mining circuitry116may include dedicated logic that performs cryptographic hash functions such as Secure Hash Algorithm (SHA) functions. For example, cores220may perform SHA-2 hash functions (e.g., SHA-256 hash functions that are computed with 32-bit words as a message schedule input to each round of hashing and that outputs 256-bit hash outputs) on inputs provided by control circuitry216over paths224.

FIG. 11is an illustrative diagram of an exemplary core220in circuitry116ofFIG. 10. In the example ofFIG. 11, circuitry220is used for performing SHA-256 hashing on inputs received from control circuitry216. However, this is merely illustrative and in general, core220may be used to perform any desired hashing algorithm on inputs received from control circuitry216(e.g., for use in a bitcoin protocol, another digital currency protocol, or for use in a cryptographic system unrelated to a digital currency), or core220may be formed separate from mining circuitry116(e.g., on a dedicated integrated circuit or integrated circuit separate from mining circuitry116) and may generally perform cryptographic hashing functions (e.g., SHA-256 hashing) on any desired input received from any desired source.

As shown inFIG. 11, core220may include communications circuitry such as communications module260that receives a message input W from control circuitry216via path224. The message input W received from control circuitry216may include portions of block header152for use as an input to a SHA-256 hashing algorithm, for example. Core220may receive an initial hash input Hifrom external circuitry215via input/output port214. The initial hash input Himay be computed off-chip based on a portion of a bit coin block header. For example, initial hash input Himay be computed at circuitry215by hashing portion174of block header152(e.g., using single or double hashing with a SHA-256 hashing protocol). Core220may include storage circuitry264that includes volatile and/or non-volatile memory.

If desired, core220may include multiple sequential hashing modules such as first hashing module262and second hashing module266. First and second hashing modules262and266may be used to perform a double SHA-256 hash based on initial hash Hiand the message input received on line224. For example, first hashing module262(sometimes referred to herein as first SHA-256 module262) may perform SHA-256 hashing on initial hash Hiand message input W to produce a first hash output H0. The first hash output H0may be provided to as a message input to second hashing module266(sometimes referred to herein as second SHA-256 module266). Second hashing module266may receive constant factors as an initial hash input (e.g., constant factors determined by the SHA-256 hashing algorithm such as one or more prime numbers). Second hashing module266may perform SHA-256 hashing on the constant factors using a message schedule based on first hash output H0to produce a second hash output HF(sometimes referred to herein as a final hash output).

In the example ofFIG. 11, initial hash Hiincludes 256 bits whereas message input W includes 512 bits. First hash output H0may include 256 bits (e.g., as determined by the SHA-256 algorithm implemented by first hashing module262). Core220may include padding circuitry268for padding first hash output H0with a desired number of zeros so that padded first hash output H0includes 512 bits (e.g., so that first hash output H0can be used as the 512-bit message input to second SHA-256 module266). The constant factors input to second hashing module266may include 256 bits. Second hash output HFmay include 256 bits (e.g., as determined by the SHA-256 algorithm implemented by second hashing module266).

Core220may include difficulty comparison circuitry270. Second hash output HFmay be provided to difficulty comparison circuitry270. Difficulty comparison circuitry270may compare second hash output HFto a predetermined difficulty value received at input272. Difficulty value272may, for example, be received from control circuitry216or other desired external circuitry. Difficulty value272may, for example, be specified by the digital currency protocol implemented by mining circuitry116or by any other source (e.g., the difficulty value may be determined by the network of nodes operating on the bitcoin protocol and may be adjusted over time so that a predictable number of solutions to the cryptographic puzzles are computed by the entire network in a given time period).

If second hash output HFsatisfies the predetermined difficulty value (e.g., if a number of least significant zero bits as specified by the Bitcoin protocol is sufficient or if value HFis less than the predetermined difficulty value), a found signal may be issued on line224indicating that a solution has been found for the given initial hash Hiand message input W (e.g., for the bitcoin block header associated with the initial hash and message). If no solution is found, the search space may be changed (e.g., using a different timestamp field168, nonce field172, extra nonce field, etc.) and computation may be repeated until a solution is found, until the search space is changed again, or until a new block150in block chain200(FIG. 9) is received.

Each hashing module262and266may perform multiple rounds of SHA-256 hashing (e.g., as specified by the SHA-256 hashing protocol). Each round of hashing may involve performing the same logical functions on an input to that round to produce an output for that round. Each round of hashing may receive a portion of the message input W (e.g., a 32-bit word of the message input or a modified 32-bit word derived from the message input W). The output of a given round may serve as an input for the next round (along with another word from the message input).

In a scenario sometimes described herein as an example (e.g., when operating under the Bitcoin or SHA-256 protocol), first hashing module262may perform 64 rounds of hashing based on initial hash Hiand input message W to produce first hash output H0. Similarly, second hashing module266may perform 64 rounds of hashing based on the constant factors and first hash output H0to produce second hash output HF. In typical scenarios, each round of SHA-256 hashing performed by first hashing module262(or second hashing module266) may be performed by dedicated logic on core220. The output of a first round of SHA-256 logic in first hashing module262may serve as an input to the second round of SHA-256 logic in first hashing module262(along with a word generated by message schedule logic based on input message W), the output of which may serve as an input to a third round of SHA-256 logic in first hashing module262(along with an additional word generated by the message schedule logic based on input message W), etc. Each round of SHA-256 performed by first hashing module262and second hashing module266may include a hash input and a corresponding message input. The hash input and message input may be combined as determined by the SHA-256 protocol to produce a hash output used as a hash input of the subsequent round of SHA-256 hashing. Hash values output by each of the rounds of SHA-256 logic except for the final round may sometimes be referred to herein as intermediate hashing values, whereas hash values generated by the final round of SHA-256 logic may sometimes be referred to herein as hash output values or output hash values. The hash output of the final (e.g., 64th) round may sometimes be referred to herein as the hash output value H0or HF. If desired, the hash output value may be combined with the corresponding initial hash value Hiusing adder circuitry to generate a value sometimes referred to herein as a final hash value.

The logical operations implemented by the SHA-256 hashing protocol may be performed by dedicated logic hardware (e.g., hardcoded circuitry) on first and second hashing modules262and266, for example. Performing logical operations using hardware may be significantly faster than performing the same logical operations using software.FIG. 12is an illustrative diagram of a single round of the SHA-256 hashing function logic that may be formed using dedicated logic on core220. The circuitry ofFIG. 12may be implemented on the first and/or second hashing modules ofFIG. 11and may be repeated on the hashing module for each number of rounds implemented by the hashing module (e.g., the circuitry ofFIG. 12may be repeated 64 times in each hashing module). The circuitry ofFIG. 12may sometimes be referred to herein as a hash schedule, hash scheduling circuitry, hash schedule logic, or hash scheduling logic.

As shown inFIG. 12, SHA-256 hashing circuitry298may include storage circuitry such as storage circuitry300and302(e.g., register circuitry300and302). Register circuitry300may serve as an input register to the corresponding round of SHA-256 hashing logic306. Data stored on register circuitry300may be passed to SHA-256 hashing logic306and operated on according to the SHA-256 hashing protocol (e.g., as shown in the logical diagram ofFIG. 12). The output of SHA-256 logic306may be passed to output register302. In typical arrangements, register circuitry300and302each include eight corresponding registers A-H (e.g., a first register A, a second register B, a third register C, etc.) that each stores a corresponding 32-bit hash value (e.g., register A may store the most significant 32 bits of initial hash Hi, whereas register H stores the least significant 32 bits of initial hash Hi, for the first round of hashing). In other words, a 256 bit hash input Hi, may be partitioned into eight 32-bit hash values A-H each stored on a corresponding register of input register circuitry300. Each 32-bit hash value may be passed to logic306along with portions (words) Wtof message input W. The output of logic306may be stored on register circuitry302(e.g., the output of logic306may be partitioned into 32-bit hash values A-H each stored on a corresponding register of output register circuitry302).

As an example, hash schedule logic298ofFIG. 12may be a first round of SHA-256 hashing logic formed on hashing module262. In this scenario, register300may receive and store initial hash Hireceived over input/output port214(e.g., partitioned into 32-bit hash portions A-H). A 32-bit input message word Wtmay be generated by message scheduling circuitry based on input message W. Adder circuitry304(e.g., addition modulo 32 circuitry) may receive word Wtfrom the message scheduling circuitry as well as a SHA-256 constant value Kt. Constant value Ktmay be specified by the SHA-256 hashing protocol and may correspond to the particular round number of SHA-256 implemented between registers300and302(e.g., Ktmay have a first value for the first round of SHA-256, a second value for the second round of SHA-256, a third value for the 64thround of SHA-256, etc.).

Input word Wtmay be provided to hash scheduling circuitry298by corresponding message scheduling logic on core220. The message scheduling logic may receive message input W from communications module260(FIG. 11) and may perform operations on message W according to the SHA-256 protocol to generate message input words Wt. For example, the message scheduling logic may perform logical operations on input message W and may output a single 32-bit word Wtof the input message W after performing the logical operations at any given time. A corresponding message input word Wtmay be provided to adder304for each round of SHA-256 in hashing module262(e.g., a first word Wtmay be provided during the first round of SHA-256, a second word Wtmay be provided during the second round of SHA-256, etc.). Word Wtmay be the most significant word of the message stored in the message scheduling logic at a given time.

The 32-bit hash values stored on registers300, the corresponding message input word Wt, and the corresponding round constant value Ktmay be passed to and processed by logic306as shown and defined inFIG. 12. The processed 32-bit hash values may be stored on output registers302. The logical functions performed by logic blocks Ch, Σ1, Ma, and Σ0in logic306are defined as shown inFIG. 12. The arrangement of logic circuitry306ofFIG. 12is determined by the SHA-256 protocol and is merely illustrative. In general, any desired logic may be formed in circuitry306for operating on input hash values stored in registers300.

The 32-bit processed hash values stored in registers302may be provided to a subsequent round of logic306(e.g., logic circuitry having the same configuration as shown inFIG. 11) and the output of the subsequent round of logic may be provided to an additional bank of register circuits. In this way, each of the 64 rounds of SHA-256 logic on hashing module262(or hashing module266) may include corresponding logic circuitry306and register circuitry300/302. In another suitable arrangement, the output of register302may loop back to register300for two or more of the 64 rounds of SHA-256 hashing. After the final round of hashing298(e.g., the 64thround), the process hash value stored on registers302in the 64thround of logic circuitry may be used as hash output H0ofFIG. 11(e.g., after passing through 64 rounds of logic306, first hash output H0may be produced as the hash value stored on the final output register circuitry302of first hashing module262). Hash output H0may be passed to second hashing module266(FIG. 11). Similar logic may be formed on second hashing module266to generate final hash output HFusing the constant factors as the initial hash value stored on input registers300of second hashing module266and using words from the message input corresponding to first hash output H0.

FIG. 13is an illustrative diagram of message scheduling logic398formed on the first and/or second hashing modules ofFIG. 11for generating input words Wtprovided to hash schedule logic298based on received message W. An initial message such as 512-bit message input W ofFIG. 11may be stored in registers400. Each register400may store a corresponding 32-bit portion (word) of message W. The stored message W may be shifted through registers400word-by-word for each round of SHA-256 performed by hash scheduling circuitry298. The most significant 32-bit word Wtafter each shift through registers400may be provided as input word Wtto the corresponding round of hash scheduling logic298. In this way, each 32-bit input word Wtis based on the message input W received from controller216.

For example, during the first round of SHA-256 hash schedule298as shown inFIG. 12, a first most significant 32-bit word Wtmay be provided to adder304over path404, and each word stored on registers400may be shifted over to the next register400(e.g., in a direction to the left as shown inFIG. 13). The most significant 32-bit word Wtafter shifting the words may be provided to adder304over path404and the words may be shifted again to the next register400. This process may continue so that a different message input word Wtis provided to each of the 64 rounds of SHA-256 hash scheduling logic298. Some of the words stored on registers400may be passed to logic406and adder circuits402(addition modulo two adder circuits402) and a corresponding word may be provided to the last (least significant) register400in message scheduling logic398.

In the example where message scheduling circuitry398is formed in first hashing module262, the 512-bit message initially stored on registers400may be message input W received from controller216. In the example where message scheduling circuitry398is formed on second hashing module266, the 512-bit message initially stored on registers400may be first hash output H0(e.g., after padding to 512 bits using padding circuitry268) generated by first hashing module262. The arrangement of logic406, registers400, and adders402may be determined by the SHA-256 hashing protocol. This example is merely illustrative and, if desired, any arrangement of registers400, logic406, and adders402may be used for generating message words Wt.

Each core220in mining circuitry116may include first and second hashing modules262/266. This example is merely illustrative and in general, cores220may include any desired number of hashing modules that perform any desired number of rounds of hashing using any desired hashing protocol. In the example ofFIGS. 11-13, each core220may include 64 rounds of hash scheduling logic298(as shown inFIG. 12) and corresponding message scheduling logic398(as shown inFIG. 13) for computing hash values in parallel (e.g., for finding a solution to the cryptographic puzzle more efficiently than if only a single core is used). For example, the first hashing module of a first core220may include 64 rounds of hash scheduling logic298, the first hashing module of a second core220adjacent to the first core may include 64 rounds of hash scheduling logic, etc. Each round of hashing logic may require a predetermined amount of chip area on mining circuitry116and a predetermined amount of power for computing SHA-256 hash functions. It may therefore be desirable to be able to reduce area and power used by cores220for computing hash functions in parallel to reduce chip cost and increase power efficiency.

If desired, portions of message scheduling logic398and/or hash scheduling logic298may be shared across multiple cores220. For example, register circuitry300and302and/or logic circuitry306from one or more rounds of hash scheduling logic298in the first or second hashing module may be shared between two or more cores220(e.g., so that multiple cores use a single logic circuit for at least some of the 64 rounds of SHA-256 hashing). In this way, the total area required by hash scheduling circuitry298and message scheduling circuitry398across multiple cores220may be reduced on integrated circuit116(and corresponding power leakage may be minimized).

FIG. 14is an illustrative block diagram showing how multiple cores220in core region218on mining circuitry116may share common message scheduling logic circuitry and common hash scheduling logic circuitry to minimize chip area consumed by the corresponding hashing modules.

As shown inFIG. 14, core region218may include adjacent hashing cores220(e.g., a first core220-0, a second core220-1, a third core220-2, and a fourth core220-4). Each core220may be formed on a corresponding logic region (area) on mining circuitry116(e.g., first core220-0may be formed on a first region of circuitry116, second core220-1may be formed on a second region of circuitry116adjacent to the region of first core220-0, third core220-2may be formed on a third region adjacent to second core220-1, and fourth core220-3may be adjacent to third core220-2). The example ofFIG. 14is merely illustrative. In general, any desired number of adjacent cores220may share hash and message scheduling logic.

Cores220may share a common communications module260for interfacing with controller216if desired. Shared communications module260may pass messages W from controller216to message scheduling logic398on cores220(a first message W0identifying the corresponding search space for core220-0, a second message W1identifying the corresponding search space for core220-1, a third message W2identifying the corresponding search space for core220-2, and a fourth message W3identifying the corresponding search space for core220-3). Messages W0-W3may include common bits (e.g., common portions) that are shared among messages W0-W3and uncommon bits (portions) that are different between two or more of messages W1-W3(e.g., because much of the search space represented by messages W1-W3may overlap). Message scheduling logic398in cores220may include shared message scheduling logic422. Shared message scheduling logic422may be shared between each of the cores220(e.g., some of all of the cores in region218). In the example ofFIG. 14, shared message scheduling logic may be formed in one or more of core regions220-0,220-1,220-2, and220-3or may be distributed across each of core regions220-0,220-1,220-2, and220-3.

Shared message scheduling logic422may utilize commonalties (e.g., common bits or portions) in messages W0-W3provided to different cores220to generate the same message input words Wtfor each of cores220-0through220-3for a desired number of rounds of SHA-256 hashing performed by hash scheduling circuitry298. The desired number of rounds may correspond to a number of rounds at which the most significant words of messages W0, W1, W2, and W3are the same (e.g., regardless of which core the messages were generated for when partitioning the search space). After the desired number of rounds of SHA-256 hashing, partially shared message scheduling logic424may be used to generate message input words Wtfor a subset of the four cores220. Partially shared message scheduling logic424may be formed in a subset of core regions220-0,220-1,220-2, and220-3or may be distributed across subsets of core regions220-0through220-3.

In the example ofFIG. 14, two partially shared message scheduling logic circuits424are each shared by two cores220. Each partially shared message scheduling logic circuit may provide the same message input word Wtto its corresponding subset of cores220for a desired number of rounds of SHA-256 hashing (e.g., a first circuit424may be shared by cores220-0and220-1and may provide the same message words Wtto cores220-0and220-1for a desired number of hash rounds subsequent to using shared message scheduling logic422to generate the message words, a second circuit424may be shared by cores220-2and220-2and may provide the same message words Wtto cores220-2and220-3for the desired number of hash rounds subsequent to using shared message scheduling logic422, etc.). The desired number of rounds for which partially shared logic424is used may correspond to a number of rounds at which the most significant words of messages W0, W1, W2, and W3are the same regardless of which of the cores associated with the respective partially shared circuit424the messages were generated for.

After partially shared message scheduling logic has been used to provide message input words Wtto its corresponding core hash scheduling logic, unshared message scheduling logic426may be used to generate words Wtfor each core220(e.g., words that are different across the cores). In this way, unshared message logic426in core region220-0may generate words Wtfor hash logic298in core region220-0, logic426in core region220-1may generate words Wtfor hash logic298in core region220-1, etc. (e.g., because words W0, W1, W2, and W3generated for cores220-0,220-1,220-2, and220-3, respectively, will eventually have 32-bit words that are dissimilar across cores, as the search space for each core was partitioned by controller216). In this way, message scheduling logic398may take advantage of shared bits across messages W0, W1, W2, and W3to use a single message scheduling logic circuit422to provide words Wtto hash circuitry298for the shared portions of messages W0, W1, W2, and W3and may take advantage of shared bits across a subset of messages W0, W1, W2, and W3to use partially shared message schedule circuits424to provide words Wtto hash circuitry298for the bits shared across the subset of messages. By using shared and partially shared message scheduling logic, circuitry218may reduce the area on chip218consumed by message scheduling logic398relative to scenarios where separate and distinct message scheduling circuitry is used for each core220.

Hash scheduling logic298in cores220may include shared hash scheduling logic428shared between each of the cores220. In the example ofFIG. 14, shared hash scheduling logic298may be formed in one or more of core regions220-0,220-1,220-2, and220-3or may be distributed across each of core regions220-0,220-1,220-2, and220-3.

Shared hash scheduling logic428may include a predetermined number of rounds of SHA-256 logic. For example, shared logic428may include logic for computing the first four rounds of SHA-256 (e.g., using the logic shown inFIG. 12). Shared logic428may receive hash input Hifrom I/O port214and may perform the logical operations as shown inFIG. 12based on messages Wtreceived from message scheduling logic398. Shared hash scheduling logic298may utilize commonalties in messages W provided to different cores220to use the same logic circuits for a given number of rounds of SHA-256 for each of the cores220(e.g., rounds for which the result of SHA-256 will be the same regardless of core because messages W0, W1, W2, and W3generated for those cores is the same).

Cores220may include partially-shared hash scheduling logic circuits430coupled to shared hash scheduling logic428. For example, shared hash scheduling logic428may include the hash logic and register circuitry associated with a first number of the 64 rounds of SHA-256 hashing, whereas partially shared logic430may include the logic and register circuitry associated with a second number of subsequent rounds of SHA-256 hashing. In the example ofFIG. 14, a first partially shared hash scheduling logic circuit may be shared between cores220-0and220-1whereas a second partially shared hash scheduling logic circuit may be shared between cores220-2and220-3(e.g., because cores220-0and220-1may have common words from messages W0and W1for the second number of rounds subsequent to the first number of rounds whereas cores220-2and220-3may have common words from messages W2and W3for the second number of rounds).

Cores220may include unshared hash scheduling logic circuits432coupled to corresponding partially shared hash scheduling logic circuits430. After the second number of rounds of SHA-256 associated with partially shared hash logic circuitry430have been completed, each core220may compute the remaining rounds of SHA-256 using respective unshared hash scheduling logic (e.g., because at this point, messages W0, W1, W2, and W3are different across each core220as determined by the assigned search space for each core). Each unshared hash scheduling logic circuit432may output a corresponding first hash output value H0to be passed to second hashing module266within that core220(e.g., a first value H00may be generated by first core220-0, a second value H01may be generated by second core220-1, a third value H02may be generated by third core220-2, and a fourth value H03may be generated by fourth core220-3). If desired, each hash output value may be added to the hash input value Hiusing adder circuitry (not shown). In this way, commonalties in the most significant words of messages W0-W3may be utilized to share hash scheduling circuitry across all or some of cores220for a given number of the 64 rounds at the beginning of SHA-256 hashing. By using shared and partially shared hash scheduling logic, circuitry218may reduce the area on chip218consumed by hash scheduling logic298relative to scenarios where separate and distinct hash scheduling circuitry is used for each core220.

The example ofFIG. 14is merely illustrative. If desired, message scheduling logic398may be shared across cores whereas hash scheduling logic298is not shared across cores. Similarly, hash scheduling logic298may be shared across cores whereas message scheduling logic398is not shared across cores. If desired, any combination of shared message scheduling logic422, partially shared message scheduling logic398, and unshared message scheduling logic426may be omitted from message scheduling circuitry398. If desired, any combination of shared hashing circuitry428, partially shared hashing circuitry430, and unshared hashing circuitry432may be omitted from hashing circuitry298.

FIG. 15is an illustrative block diagram showing how different rounds of SHA-256 hashing may be computed using shared, partially shared, and unshared hashing circuitry across cores220(e.g., in an arrangement similar to that shown inFIG. 14).

As shown inFIG. 15, shared hash scheduling logic428may receive initial hash value Hifrom I/O port214. A first round R0of hash scheduling circuitry298(e.g., as shown inFIG. 12) may process initial hash Hiand a word Wtfrom message scheduling circuitry398and may provide an output of round R0to second round R1of hash scheduling circuitry298. Message scheduling circuitry398is shown as a single block for the sake of clarity but may, if desired, include shared message scheduling logic422, partially shared message scheduling logic424, and unshared message scheduling logic426interspersed with hash scheduling circuitry298or formed around the periphery of hash scheduling circuitry298. Hashing logic in SHA-256 hashing round R1may provide an output to hashing logic round R2. Each round may include corresponding logic circuitry306, input register circuitry300, and output register circuitry302, and may receive a corresponding word Wtfrom message scheduling circuitry398. Rounds R0, R1, and R2of hashing logic298may form shared hash scheduling logic428(as shown inFIG. 14) because the output of rounds R0, R1, and R2are used for generating hash value H0for multiple cores220(e.g., first core220-0, second core220-1, third core220-2, and fourth core220-3). In the example ofFIG. 15, shared hash scheduling logic428is formed in core region220-3but may, in general, be formed in one or more of any desired core regions220.

The output of round R2may be passed to partially-shared hash scheduling logic430. Partially-shared hash scheduling logic430may include multiple logic circuits that perform round R3of SHA-256. In the example ofFIG. 15, two hash scheduling logic circuits perform the hashing operations of round R3. The output of round R3is provided to a subset of the four cores and is therefore partially shared (e.g., logic R3in core220-2provides its output to cores220-0,220-1, and220-2whereas logic R3in core220-3provides its output to core220-3). After a predetermined number of rounds of partial sharing, partially shared hash scheduling logic430may provide outputs to unshared hash scheduling logic432. After 64 total rounds of SHA-256 hashing (e.g., after round R63), the output of hashing logic R63may be provided to adder circuitry (addition modulo two circuitry)440. Adder circuitry440may add initial hash value Hito the output of hash scheduling logic R63to produce respective first hash values H0for each core220. By sharing and partially sharing one or more rounds of SHA-256 hashing logic across multiple cores220, region442on mining circuitry116may be free from logic circuitry, thereby reducing area consumption and power leakage of cores220relative to scenarios where no logic sharing is implemented across cores220.

As an example of how messages may be provided to shared, partially shared, and unshared hash scheduling circuitry, the input messages W provided to message scheduling logic398may include, in order of significance, a 32-bit Merkle root field, a 32-bit timestamp field, a 32-bit difficulty value field, a 32-bit nonce field, a fixed field including one high (e.g., logic “1”) bit followed by 319 low (e.g., logic “0”) bits (e.g., a padding field), and a fixed field identifying the size of the message. Four different input messages W0, W1, W2, and W3may be provided by controller216for four cores220, for example. In this example, the Merkle root field, timestamp field, difficulty value field, the fixed fields, and all but the two least significant bits of the nonce field may be shared across all four messages W0-W3, whereas the two least significant bits of the nonce field may be unique to each of the four messages (e.g., message W0may have nonce least significant bits (LSBs) “00,” message W1may have nonce LSBs “01,’ message W2may have nonce LSBs “10,” and message W3may have nonce LSBs “11”, representing the variation in search space between the four cores).

A given one of messages W0-W3may be stored in registers400as shown inFIG. 13(e.g., so that the most significant Merkle root field is stored in the first register400and the last 32-bits of the fixed fields is stored in the last register400) or messages W0-W3may be stored on respective registers400. At a first round R0of hash scheduling logic298, the first 32-bit word of the message stored on registers400may be used as word input Wt. Because the Merkle root field is shared by all four messages W0-W3(e.g., identical in each of the words), the word Wtused for round R0of the hash schedule would be the same for each of the four cores even though each core has a different respective message W0, W1, W2, or W3generated by controller216(e.g., the same Merkle root field may be used for all four cores at round R0, thereby allowing the cores to share scheduling circuitry). The words stored on registers400may subsequently shift by one register (e.g., in a direction to the left as shown inFIG. 13). The timestamp field may then be stored on the first register of circuitry398. As the word for round R0of the hash schedule is the same for all four cores, the hashing logic may be shared between all four cores for round R0.

At the next round R1of hash schedule logic298, the timestamp field (e.g., the most significant 32-bit word after shifting) in memory schedule logic398may be provided as word input Wtto round R1of hash schedule logic298. Because the timestamp field is shared by all four messages W0-W3(and is thereby shared by all four cores), the word Wtused for round R1of the hash schedule may be used for all four cores thereby allowing the four cores to share round R1hash schedule logic. The words stored on registers400may subsequently shift by one register. The difficulty field may then be stored on the first (most significant) register400of circuitry398. As the word for round R1of the hash schedule is the same for all four cores in this example, the same hashing logic circuit may be shared between all four cores for round R1.

At the subsequent round R2of hash schedule logic298, the difficulty field (e.g., the most significant 32-bit word after shifting) in memory schedule logic398may be provided as word input Wtto round R2of hash schedule logic298. Because the difficulty field is shared by all four messages W0-W3in this example, the word Wtused for round R2may be used for all four cores, thereby allowing the four cores to share round R2hash schedule logic circuitry. The words stored on registers400may subsequently shift by one register. The nonce field may then be stored on the first register400of circuitry398.

At subsequent round R3of hash schedule logic298, two different message words Wtmay be provided to the four cores because there is a 2-bit divergence in the nonce word provided by message schedule398(e.g., because the two LSBs of the nonce field varies between messages W0-W3). Round R3of the hash schedule logic298will thereby be partially shared across cores such that two cores220share a first logic circuit to compute round R3of SHA-256 and two additional cores220share a second logic circuit to compute round R3. In this scenario, the output registers302in the round R3of the hash schedule will vary between pairs of cores220(e.g., registers A and E of register circuitry302will store different values depending on which message word Wtis received such that two cores store a first set of bits on registers A and E and the two other cores store a second set of bits on registers A and E, whereas words stored on registers B, C, D, F, G, and H will be identical between all four cores). The words stored on registers400may subsequently shift by one register.

At subsequent round R4, the high bit of the fixed field and the first 31 low bits of the fixed field are provided as the word Wtto the partially-shared hash scheduling logic of round R4. The output registers between pairs of cores will vary in the bits stored on registers B and F of output register circuitry302. This pattern may continue for subsequent rounds R5and R6in this example until no hardware is shared and independent hash scheduling circuitry is formed in each of the four cores220. This example is merely illustrative. Any desired logic may be shared for computing rounds of SHA-256 hashing on any desired message inputs.