Connector, display screen and method for manufacturing the display screen

A connector, a display screen and a method for manufacturing the display screen are provided. The connector includes a substrate, and a conductor structure arranged on the substrate. One end of the conductor structure is connected to a data signal line on a display panel, and the other end of the conductor structure is connected to a driver integrated circuit IC arranged on a non-display side of the display panel. A target surface, away from the substrate, of the conductor structure is uneven. The connector reduces the probability of the conductor structure breaking under the stress of the substrate, thereby guaranteeing the good display effect of the display screen.

This application claims priority to Chinese Patent Application No. 201710936247.8, filed with the State Intellectual Property Office on Oct. 10, 2017, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a connector, a display screen and a method for manufacturing the display screen.

BACKGROUND

With the popularization of smart devices and the users' demand for increased screen-to-body ratios of the smart devices, frames of display screens in the smart devices are becoming narrower. The screen-to-body ratio refers to a ratio of an area of a display region of a display screen to a total area of a front surface of the display screen.

SUMMARY

There are provided in the present disclosure a connector, a display screen and a method for manufacturing the display screen.

In an aspect, there is provided a connector, comprising: a substrate, and a conductor structure arranged on the substrate, wherein one end of the conductor structure is connected to a data signal line on a display panel, and the other end of the conductor structure is connected to a driver integrated circuit IC arranged on a non-display side of the display panel; a target surface, away from the substrate, of the conductor structure is uneven.

Optionally, the substrate comprises a target region, and a first edge region and a second edge region which are located on two sides of the target region respectively, wherein a portion, located on the target region, in the target surface is uneven, and portions, located on the first edge region and the second edge region, in the target region are even.

Optionally, the substrate comprises a target region, and a first edge region and a second edge region which are located on two sides of the target region respectively, wherein portions, located on the target region, the first edge region and the second edge region, in the target surface are uneven.

Optionally, the target region of the substrate is provided with a groove whose opening faces the conductor structure.

Optionally, the conductor structure comprises m conductive layers arranged on the substrate on which n target insulating layers are also arranged, where m≥2, n≥1; the m conductive layers comprise a data conductor layer and a circuit conductor layer, wherein the data conductor layer is connected to the data signal line, and the circuit conductor layer is connected to the driver IC; the n target insulating layers are located among the m conductor layers, and the m conductor layers are connected through via holes in the n target insulating layers.

Optionally, at least one of the target insulating layers is arranged between every two adjacent conductor layers in the m conductor layers.

Optionally, m=2, n=2; two target insulating layers are stacked between two conductor layers; the data conductor layer is the second conductor layer close to the substrate; the circuit conductor layer is any one of the two second conductor layers.

Optionally, m=3, n=2; the target insulating layers and the conductor layers are alternately arranged; the data conductor layer is the third conductor layer close to the substrate; the circuit conductor layer is any one of the three conductor layers.

Optionally, m=2, n=1; one target insulating layer is arranged between two conductor layers; the data conductor layer is the second conductor layer close to the substrate; the circuit conductor layer is any one of the two conductor layers.

Optionally, the substrate comprises: a polyimide PI base, and a water blocking layer, a buffer layer and an auxiliary insulating layer which are stacked on the PI base in sequence.

In another aspect, there is provided a display screen, comprising: a display panel, a driver IC and a connector, wherein the driver IC is arranged on a non-display side of the display panel, and the connector is configured to connect the display panel and the driver IC.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence; the connector comprises a substrate on which two conductor layers and two target insulating layers are arranged, the two target insulating layers being stacked between the two conductor layers; the first conductor layer close to the substrate is formed of the same material layer as that of the first gate signal line; the first target insulating layer close to the substrate is formed of the same material layer as that of the second gate insulating layer; the second target insulating layer close to the substrate is formed of the same material layer as that of the interlayer dielectric layer; the second conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the second conductor layer close to the substrate is connected to the data signal line, and any one of the two conductor layers is connected to the driver IC.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence; the connector comprises a substrate on which three conductor layers and two target insulating layers are arranged, the conductor layers and the target insulating layers are alternately arranged; the first conductor layer close to the substrate is formed of the same material layer as that of the first gate signal line; wherein the first target insulating layer close to the substrate is formed of the same material layer as that of the second gate insulating layer; the second conductor layer close to the substrate is formed of the same material layer as that of the second gate signal line; the second target insulating layer close to the substrate is formed of the same material layer as that of the interlayer dielectric layer; the third conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the third conductor layer close to the substrate is connected to the data signal line, and any one of the third conductor layers is connected to the driver IC.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence; the connector comprises a substrate on which two conductor layers and one target insulating layer are arranged, the target insulating layer being arranged between the two conductor layers; wherein the first conductor layer close to the substrate is formed of the same material layer as that of the second gate signal line; the target insulating layer is formed of the same material layer as that of the interlayer dielectric layer; the second conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the second conductor layer close to the substrate is connected to the data signal line, and any one of the two conductor layers is connected to the driver IC.

Optionally, the substrate comprises: a PI substrate, and a water blocking layer, a buffer layer and an auxiliary insulating layer which are arranged on the PI substrate in sequence, wherein the m conductor layers are arranged on the auxiliary insulating layer, and the auxiliary insulating layer is formed of the same material layer as that of the first gate insulating layer.

Optionally, the substrate comprises: a PI substrate, and a water blocking layer, a buffer layer and an auxiliary insulating layer which are arranged on the PI substrate in sequence, wherein the m conductor layers are arranged on the auxiliary insulating layer, and the auxiliary insulating layer is formed of the same material layer as that of the first gate insulating layer.

In yet another aspect, there is provided a method for manufacturing a display screen, comprising the following steps: forming a connector by arranging, on a substrate, a conductor structure whose target surface away from the substrate is uneven; connecting one end of the conductor structure to a data signal line on a display panel; connecting the other end of the conductor structure to a driver IC; and bending the connector to arrange the driver IC on a non-display side of the display panel.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence, wherein the step of forming the connector by arranging, on the substrate, the conductor structure whose target surface away from the substrate is uneven comprises: forming two conductor layers and two target insulating layers on the substrate, the two target insulating layers being stacked between the two conductor layers, wherein the first conductor layer close to the substrate is formed of the same material layer as that of the first gate signal line; the first target insulating layer close to the substrate is formed of the same material layer as that of the second gate insulating layer; the second target insulating layer close to the substrate is formed of the same material layer as that of the interlayer dielectric layer; the second conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the step of connecting one end of the conductor structure to the data signal line on the display panel comprises: connecting the second conductor layer close to the substrate to the data signal line; the step of connecting the other end of the conductor structure to the driver IC comprises: connecting any one of the two conductor layers to the driver IC.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence; the step of forming the connector by arranging, on the substrate, the conductor structure whose target surface away from the substrate is uneven comprises: forming three conductor layers and two target insulating layers on the substrate, the conductor layers and the target insulating layers are alternately arranged, wherein the first conductor layer close to the substrate is formed of the same material layer as that of the first gate signal line; the first target insulating layer close to the substrate is formed of the same material layer as that of the second gate insulating layer; the second conductor layer close to the substrate is formed of the same material layer as that of the second gate signal line; the second target insulating layer close to the substrate is formed of the same material layer as that of the interlayer dielectric layer; the third conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the step of connecting one end of the conductor structure to the data signal line on the display panel comprises: connecting the third conductor layer close to the substrate to the data signal line; and the step of connecting the other end of the conductor structure to the driver IC comprises: connecting any one of the third conductor layers to the driver IC.

Optionally, the display panel comprises: a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence, wherein the step of forming the connector by arranging, on the substrate, the conductor structure whose target surface away from the substrate is uneven comprises: forming two conductor layers and one target insulating layer on the substrate, the one target insulating layer being arranged between the two conductor layers, wherein the first conductor layer close to the substrate is formed of the same material layer as that of the second gate signal line; the one target insulating layer is formed of the same material layer as that of the interlayer dielectric layer; the second conductor layer close to the substrate is formed of the same material layer as that of the data signal line; the step of connecting one end of the conductor structure to the data signal line on the display panel comprises: connecting the second conductor layer close to the substrate to the data signal line; the step of connecting the other end of the conductor structure to the driver IC comprises: connecting any one of the two conductor layers to the driver IC.

DETAILED DESCRIPTION

To make the principles and advantages of the present disclosure clearer, the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings.

As known by the inventors, the display screen generally includes: a display panel, a driver IC and a connector. The connector is configured to connect the display panel and the driver IC. Herein, the connector includes: a substrate, and a conductor layer arranged on the substrate. One end of the conductor layer is connected to a data signal line on the display panel, and the other end of the conductor layer is connected to the driver IC. The substrate is generally made of an inorganic material. The driver IC may send control signals (also referred to as data signals) to the data signal line through the connector, so as to control the display panel to display different images according to the control signals. In order to make a frame of the display screen narrower, it is necessary to arrange the driver IC on a non-display side (the side opposite to a display side) of the display panel, and bend the connector.

Exemplarily,FIG. 1is a schematic diagram of a structure of a display screen provided in an embodiment of the present disclosure.FIG. 1illustrates a display screen when the connector is not bent. As shown inFIG. 1, the display screen10includes a driver IC101, a display panel102, a connector103and a protection film104. The display panel102includes: a touch panel1021, a polaroid1022, a thin film encapsulation (TFE)1023, an organic light-emitting diode (OLED)1024, and a thin film transistor array1025.

The touch panel1021is arranged opposite to the thin film transistor array1025. The OLED1024and the TFE1023are arranged sequentially on one side, close to the touch panel2021, of the thin film transistor array1025. The polaroid1022is arranged on one side, close to the thin film transistor array1025, of the touch panel1021.

One end of the connector103is arranged on one side, away from the touch panel1021, of the thin film transistor array1025, and the other end of the connector103is in contact with the driver IC101. A central region (i.e., a region between the display panel and the driver IC) of the connector103may be provided with a conductor layer (not shown inFIG. 1). The conductor layer is connected to the thin film transistor array1025and the driver IC101respectively. The driver IC101may send control signals to the thin film transistor array1025through the connector103, so as to control the display panel102to display different images.

A protection film104may both be arranged on one side, away from the touch panel1021, of the thin film transistor array1025and on one side, away from the driver IC101, of the other end of the connector103.

It should be noted that the display panel102has opposite sides, i.e., a display side and a non-display side. Herein, the polaroid1022and the touch panel1021are located on the display side of the display panel102, and the protection film104is located on the non-display side of the display panel102.

FIG. 2is a schematic diagram of a structure of another display screen provided in an embodiment of the present disclosure.FIG. 2illustrates a display screen when the connector is bent. As shown inFIG. 2, after the connector103is bent, the driver IC101is arranged on the non-display side of the display panel.

As shown inFIG. 3, the connector103which is not bent includes: a substrate1031, and a conductor layer1032arranged on the substrate1031. Exemplarily, the substrate1031may include: a polyimide (PI) substrate1031f, a water blocking layer1031e, a buffer layer1031d, a first gate insulating layer1031c, a second gate insulating layer1031band an interlayer insulating layer1031awhich are stacked in sequence. The interlayer insulating layer1031ais arranged close to the conductor layer1032.

One end of the PI substrate1031fmay be arranged on one side, away from the touch panel, of the thin film transistor array in the display panel, and the other end of the PI substrate1031fis in contact with the driver IC. The interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, the buffer layer and the water blocking layer are usually made of an inorganic material, and the total thickness of the five inorganic material layers is 2.4 microns approximately. Due to high brittleness of the inorganic material, the inorganic material is more likely to fracture when the connector is bent. In addition, when the connector is bent, the inorganic material will generate a stress inside for resisting the bending. However, the conductor layer arranged on the inorganic material is more likely to be broken under the stress of the inorganic material, thereby causing ineffective connection between the driver IC and the data signal line and affecting the display effect of the display screen.

FIG. 4ais a schematic diagram of a structure of a connector provided in an embodiment of the present disclosure.FIG. 4aillustrates a connector which is not bent, where a portion, located between the display panel and the driver IC, in the connector, rather than the display panel and the driver IC, is shown. As shown inFIG. 4a, the connector60includes: a substrate601, and a conductor structure602arranged on the substrate601. One end of the conductor structure602is connected to a data signal line on the display panel, and the other end of the conductor structure602is connected to the driver IC arranged on the non-display side of the display panel. Exemplarily, the left end of the conductor structure602may be connected to the data signal line on the display panel, and the right end of the conductor structure602may be connected to the driver IC. A surface, away from the substrate601, of the conductor structure602is a target surface (not shown inFIG. 4a) of the conductor structure602. The target surface is uneven.

As shown inFIG. 4a, the substrate601may include a target region B, and a first edge region A and a second edge region C which are located on two sides of the target region B respectively. Exemplarily, the first edge region A may be arranged close to the display panel, and the second edge region C may be arranged close to the driver IC. The target region B may be a portion that needs to be bent when the connector60is bent. That is, the first edge region A may serve as a transition from the display panel to the target region B, and the second edge region C may serve as a transition from the target region B to the driver IC. Therefore, the condition that the display panel is damaged by direct bending from the edge of the display panel or the condition that the driver IC is damaged by direct bending from the edge of the driver IC is prevented.

Exemplarily, as shown inFIG. 4a, portions located on the target surface B, the first edge region A and the second edge region C in the target surface may be uneven, respectively.

From the above, the target surface of the conductor structure in the connector provided in the embodiments of the present disclosure is uneven, which is conductive to releasing the stress acting on the conductor structure when the substrate is bent. Therefore, the conductor structure is less affected by this stress, thereby reducing the probability of the conductor structure breaking under the stress of the substrate. Further, the case that the driver IC and the data signal line cannot be effectively connected due to the breakage of the conductor structure is prevented, thereby ensuring that the display screen has a good display effect.

Optionally, the structure of the connector60may also be shown inFIG. 4b, where a portion, located on the target region B, in the target surface may be uneven, and portions, located on the first edge region A and the second edge region B, in the target surface may be even.

Optionally, referring toFIG. 4aorFIG. 4b, the target region B of the substrate may be provided with a groove W whose opening faces the conductor structure602, such that the thickness of the target region B is relatively small, thereby further reducing the possibility that the target region B is broken when the connector60is bent.

Further, the conductor structure602may include: m conductive layers arranged on the substrate601and n target insulating layers further arranged on the substrate601, where m≥2, n≥1. It should be noted that a plurality of conductor layers and n target insulating layers are not shown inFIG. 4aandFIG. 4b.

Herein, the m conductor layers may include: a data conductor layer and a circuit conductor layer. The data conductor layer may be connected to the data signal line. The circuit conductor layer may be connected to the driver IC. The n target insulating layers may be located among the m conductor layers, and the m conductor layers may be connected through via holes on the n target insulating layers. Exemplarily, at least one target insulating layer may be arranged between every two adjacent conductor layers in the m conductor layers. There may be a plurality of via holes on the n target insulating layers. The plurality of via holes may be located on the target region only, or located on the entire substrate.

In the connector provided in the embodiments of the present disclosure, a plurality of conductor layers which are connected with each other are used. The data conductor layers in the plurality of conductor layers are connected to the data signal line on the display panel. The circuit conductor layer is connected to the driver IC arranged on the non-display side of the display panel. The driver IC may send control signals to the display panel through the plurality of conductor layers. When the connector is bent, even if one conductor layer is broken, the driver IC may also continue to be effectively connected to the data signal line through other conductor layers, such that the display screen may continue to have a good display effect.

It should be noted that the connector provided in the embodiment of the present disclosure has various implementation manners. The following seven implementation manners are illustrated in the embodiments of the present disclosure. In addition, in the following seven implementation manners, two recesses on the target surface of the conductor structure602represent the unevenness of the target surface of the conductor structure602. The target insulating layer having two via holes or four via holes thereon is taken as an example only.

In the first implementation manner, referring toFIG. 5a, m=2, n=2. That is, the conductor structure602includes: two conductor layers (the conductor layer D1and the conductor layer D2) arranged on the substrate601, and two target insulating layers (the insulating layer J1and the insulating layer J2) also arranged on the substrate601. The conductor layer D1may be the second conductor layer, close to the substrate601, of the two conductor layers. The conductor layer D2may be the first conductor layer, close to the substrate601, of the two conductor layers. The insulating layer J1and the insulating layer J2are stacked between the conductor layer D1and the conductor layer D2. Herein, the conductor layer D1is a data conductor layer, and the conductor layer D2is a circuit conductor layer. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D2is connected to the driver IC.

The substrate601may include: a PI base6011, and a water blocking layer6012, a buffer layer6013and an auxiliary insulating layer6014which are sequentially stacked on the PI base6011. The thickness of the PI substrate may be greater than or equal to 1 micron and less than or equal to 20 microns. The substrate601may be divided into a first edge region A, a target region B and a second edge region C. The target region B is provided with a groove (not shown inFIG. 5a) whose depth may be equal to the sum of the thicknesses of the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014.

Exemplarily, a manufacturing process of the connector in the first implementation manner refers toFIGS. 5ato5e.

As shown inFIG. 5b, in the course of manufacturing the connector, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 5b) first. Then, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014are etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). The substrate may be divided into a first edge region A, a target region B and a second edge region C. The groove is located in the target region B. The PI base and the water blocking layer6012may be made into a single layer or multiple layers. Later, as shown inFIG. 5candFIG. 5d, the conductor layer D2(i.e., the circuit conductor layer), the insulating layer J2and the insulating layer J1may continue to be sequentially formed on the auxiliary insulating layer6014and the groove, such that the right end of the conductor layer D2is connected to the driver IC. As shown inFIG. 5e, after the insulating layer J1is formed, the insulating layer J2and the insulating layer J1may be etched, such that a plurality of via holes are formed on the insulating layer J2and the insulating layer J1respectively, and therefore, the conductor layer D2at the plurality of via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of via holes are shown inFIG. 5e. Then, as shown inFIG. 5a, a conductor layer D1(i.e., the data conductor layer) may be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of via holes on the insulating layer J2and the insulating layer J1. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 5a.

In the second implementation manner, referring toFIG. 6a, m=2, n=2. That is, the conductor structure602includes two conductor layers (the conductor layer D1and the conductor layer D2) arranged on the substrate601and two target insulating layers (the insulating layer J1and the insulating layer J2) also arranged on the substrate601. The conductor layer D1may be the second conductor layer, close to the substrate601, of the two conductor layers. The conductor layer D2may be the first conductor layer, close to the substrate601, of the two conductor layers. The insulating layer J1and the insulating layer J2are stacked between the conductor layer D1and the conductor layer D2. Herein, the conductor layer D1serves as the data conductor layer and the circuit conductor layer at the same time. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D1is connected to the driver IC. The structure of the substrate601may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiments of the present disclosure.

Exemplarily, a manufacturing process of the connector in the second implementation manner refers toFIGS. 6ato6e.

As shown inFIG. 6b, in the course of manufacturing the connector, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be formed on a bearing substrate (not shown inFIG. 6b) first. Then, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014are etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). The substrate may be divided into a first edge region A, a target region B and a second edge region C. The groove is located in the target region B. The PI base6011and the water blocking layer6012may be made into a single layer or multiple layers. Later, as shown inFIG. 6candFIG. 6d, the conductor layer D2, the insulating layer J2and the insulating layer J1may continue to be sequentially formed on the auxiliary insulating layer6014and the groove. As shown inFIG. 6e, after the insulating layer J1is formed, the insulating layer J2and the insulating layer J1may be etched, such that a plurality of via holes are formed on the insulating layer J2and the insulating layer J1respectively, and therefore, the conductor layer D2at the plurality of via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of via holes are shown inFIG. 6e. Then, as shown inFIG. 6a, a conductor layer D1(i.e., the data conductor layer or the circuit conductor layer) may be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. The right end of the conductor layer D1is connected to the driver IC. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of via holes on the insulating layer J2and the insulating layer J1. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 6a.

In the third implementation manner, referring toFIG. 7a, m=3, n=2. That is, the conductor structure602includes third conductor layers (the conductor layer D1, the conductor layer D2and the conductor layer D3) arranged on the substrate601and two target insulating layers (the insulating layer J1and the insulating layer J2) also arranged on the substrate601. The conductor layer D1may be the third conductor layer close to the substrate601. The conductor layer D2may be the second conductor layer close to the substrate601. The conductor layer D3may be the first conductor layer, close to the substrate601, of the three conductor layers. The two insulating layers and the three conductor layers are alternately arranged. Exemplarily, the insulating layer J1is arranged between the conductor layer D1and the conductor layer D2, and the insulating layer J2is arranged between the conductor layer D2and the conductor layer D3. Herein, the conductor layer D1is the data conductor layer, and the conductor layer D2is the circuit conductor layer. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D2is connected to the driver IC. The structure of the substrate may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiments of the present disclosure.

Exemplarily, a manufacturing process of the connector in the third implementation manner refers toFIGS. 7ato7f.

As shown inFIG. 7b, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 6b). Then, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014are etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). Herein, the substrate may be divided into a first edge region A, a target region B and a second edge region C. The groove is located in the target region B. The PI base6011and the water blocking layer6012may be made into a single layer or multiple layers. Later, as shownFIG. 7candFIG. 7d, the conductor layer D3and the insulating layer J2may continue to be sequentially formed on the auxiliary insulating layer6014and the groove. After the insulating layer J2is formed, the insulating layer J2may be etched, such that a plurality of first via holes are formed on the insulating layer J2, and therefore, the conductor layer D3at the plurality of first via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of first via holes are shown inFIG. 7d. Later, as shown inFIG. 7eandFIG. 7f, a conductor layer D2(i.e., the circuit conductor layer) and the insulating layer J1may be sequentially formed on the insulating layer J2. The right end of the conductor layer D2is connected to the driver IC. In addition, the conductor layer D2is in contact and connection with the conductor layer D3through the plurality of first via holes on the insulating layer J2. Next, the insulating layer J1may also be etched to form a plurality of second via holes, and the conductor layer D2is exposed through the plurality of second via holes. It should be noted that only two (the via hole S3and the via hole S4) of the plurality of second via holes are shown inFIG. 7e. Then, as shown inFIG. 7a, a conductor layer D1(i.e., the data conductor layer) may continue to be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of second via holes. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 7a.

In the fourth implementation manner, referring toFIG. 8a, m=3, n=2. That is, the conductor structure602includes three conductor layers (the conductor layer D1, the conductor layer D2and the conductor layer D3) arranged on the substrate601and two target insulating layers (the insulating layer J1and the insulating layer J2) also arranged on the substrate601. The conductor layer D1may be the third conductor layer close to the substrate601. The conductor layer D2may be the second conductor layer close to the substrate601. The conductor layer D3may be the first conductor layer, close to the substrate601, of the three conductor layers. The two insulating layers and the three conductor layers are alternately arranged. Exemplarily, the insulating layer J1is arranged between the conductor layer D1and the conductor layer D2. The insulating layer J2is arranged between the conductor layer D2and the conductor layer D3. Herein, the conductor layer D1is the data conductor layer, and the conductor layer D3is the circuit conductor layer. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D3is connected to the driver IC. The structure of the substrate may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiments of the present disclosure.

Exemplarily, a manufacturing process of the connector in the fourth implementation manner refers toFIGS. 8ato8f.

As shown inFIG. 8b, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 8b) first. The PI substrate6011and the water blocking layer6012may be made into a single layer or multiple layers. After the auxiliary insulating layer6014is manufactured, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). The substrate may be divided into a first edge region A, a target region B and a second edge region C, where the groove is located in the target region B. Later, as shown inFIG. 8candFIG. 8d, the conductor layer D3(i.e., the circuit conductor layer) and the insulating layer J2may continue to be sequentially formed on the auxiliary insulating layer6014and the groove, such that the right end of the conductor layer D3is connected to the driver IC. After the insulating layer J2is formed, the insulating layer J2may be etched, such that a plurality of first via holes is formed in the insulating layer J2, and therefore, the conductor layer D3at the plurality of first via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of first via holes are shown inFIG. 8d. Later, as shown inFIG. 8eandFIG. 8f, the conductor layer D2and the insulating layer J1may be sequentially formed on the insulating layer J2. The conductor layer D2may be in contact and connection with the conductor layer D3through the plurality of first via holes. Next, the insulating layer J1may also be etched to form a plurality of second via holes, and the conductor layer D2is exposed through the plurality of second via holes. It should be noted that only two (the via hole S3and the via hole S4) of the plurality of second via holes are shown inFIG. 8e. Then, as shown inFIG. 8a, a conductor layer D1(i.e., the data conductor layer) may continue to be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of second via holes. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 8a.

In the fifth implementation manner, referring toFIG. 9a, m=3, n=2. That is, the conductor structure602includes three conductor layers (the conductor layer D1, the conductor layer D2and the conductor layer D3) arranged on the substrate601and two target insulating layers (the insulating layer J1and the insulating layer J2) also arranged on the substrate601. The conductor layer D1may be the third conductor layer close to the substrate601. The conductor layer D2may be the second conductor layer close to the substrate601. The conductor layer D3may be the first conductor layer, close to the substrate601, of the three conductor layers. The two insulating layers and the three conductor layers are alternately arranged. Exemplarily, the insulating layer J1is arranged between the conductor layer D1and the conductor layer D2. The insulating layer J2is arranged between the conductor layer D2and the conductor layer D3. Herein, the conductor layer D1serves as the data conductor layer and the circuit conductor layer at the same time. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D1is connected to the driver IC. The structure of the substrate may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiments of the present disclosure.

Exemplarily, a manufacturing process of the connector in the fifth implementation manner refers toFIGS. 9ato9f.

As shown inFIG. 9b, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 9b). The PI substrate6011and the water blocking layer6012may be made into a single layer or multiple layers. After the auxiliary insulating layer6014is manufactured, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). Herein, the substrate may be divided into a first edge region A, a target region B and a second edge region C, where the groove is located in the target region B. Later, as shownFIG. 9candFIG. 9d, the conductor layer D3and the insulating layer J2may continue to be sequentially formed on the auxiliary insulating layer6014and the groove. After the insulating layer J2is formed, the insulating layer J2may be etched, such that a plurality of first via holes are formed on the insulating layer J2, and therefore, the conductor layer D3at the plurality of first via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of first via holes are shown inFIG. 9d. Later, as shown inFIG. 9eandFIG. 9f, the conductor layer D2and the insulating layer J1may be sequentially formed on the insulating layer J2. The conductor layer D2may be in contact and connection with the conductor layer D3through the plurality of first via holes. Next, the insulating layer J1may also be etched to form a plurality of second via holes, and the conductor layer D2is exposed through the plurality of second via holes. It should be noted that only two (the via hole S3and the via hole S4) of the plurality of second via holes are shown inFIG. 9e. Then, as shown inFIG. 9a, a conductor layer D1(i.e., the data conductor layer or the circuit conductor layer) may be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. The right end of the conductor layer D1is connected to the driver IC. In addition, the conductor layer D1is in contact and connection with the conductor layer D2at the plurality of second via holes. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 9a.

In the sixth implementation manner, referring toFIG. 10a, m=2, n=1. That is, the conductor structure602includes two conductor layers (the conductor layer D1and the conductor layer D2) arranged on the substrate601and one target insulating layer (the insulating layer J1) also arranged on the substrate601. The conductor layer D1may be the second conductor layer close to the substrate601. The conductor layer D2may be the first conductor layer, close to the substrate601, of the two conductor layers. The insulating layer J1may be arranged between the conductor layer D1and the conductor layer D2. Herein, the conductor layer D1is the data conductor layer, and the conductor layer D2is the circuit conductor layer. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D2is connected to the driver IC. The structure of the substrate601may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiments of the present disclosure.

Exemplarily, a manufacturing process of the connector in the sixth implementation manner refers toFIGS. 10ato10e.

As shown inFIG. 10b, in the course of manufacturing the connector, first, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 10b). Then, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014are etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). Herein, the substrate may be divided into a first edge region A, a target region B and a second edge region C, wherein the groove is located in the target region B. The PI base6011and the water blocking layer6012may be made into a single layer or multiple layers. Later, as shown inFIG. 10candFIG. 10d, the conductor layer D2(i.e., the circuit conductor layer) and the insulating layer J1may continue to be sequentially formed on the auxiliary insulating layer6014and the groove, such that the right end of the conductor layer D2is connected to the driver IC. As shown inFIG. 10e, after the insulating layer J1is formed, the insulating layer J1may be etched, such that a plurality of via holes is formed in the insulating layer J1, and therefore, the conductor layer D2at the plurality of via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of via holes are shown inFIG. 10e. Then, as shown inFIG. 10a, a conductor layer D1(i.e., the data conductor layer) may be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of via holes. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 10a.

In the seventh implementation manner, referring toFIG. 11a, m=2, n=1. That is, the conductor structure602includes two conductor layers (the conductor layer D1and the conductor layer D2) arranged on the substrate601and one target insulating layer (the insulating layer J1) also arranged on the substrate601. The conductor layer D1may be the second conductor layer close to the substrate601. The conductor layer D2may be the first conductor layer, close to the substrate601, of the two conductor layers. The insulating layer J1may be arranged between the conductor layer D1and the conductor layer D2. Herein, the conductor layer D1serves as the data conductor layer and the circuit conductor layer at the same time. That is, the left end of the conductor layer D1is connected to the data signal line in the display panel, and the right end of the conductor layer D1is connected to the driver IC. The structure of the substrate601may refer to the structure of the substrate in the first implementation manner of the connector, which is not described repeatedly in the embodiment of the present disclosure.

Exemplarily, a manufacturing process of the connector in the seventh implementation manner refers toFIGS. 11ato11e.

As shown inFIG. 11b, in the course of manufacturing the connector, the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014may be sequentially formed on a bearing substrate (not shown inFIG. 11b). Then, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014are etched, such that a groove is formed in the substrate (including the PI substrate6011, the water blocking layer6012, the buffer layer6013and the auxiliary insulating layer6014). The substrate may be divided into a first edge region A, a target region B and a second edge region C, where the groove is located in the target region B. The PI base6011and the water blocking layer6012may be made into a single layer or multiple layers. Later, as shownFIG. 11candFIG. 11d, the conductor layer D2and the insulating layer J1may continue to be sequentially formed on the auxiliary insulating layer6014and the groove. As shown inFIG. 11e, after the insulating layer J1is formed, the insulating layer J1may be etched, such that a plurality of via holes are formed in the insulating layer J1, and therefore, the conductor layer D2at the plurality of via holes is exposed. It should be noted that only two (the via hole S1and the via hole S2) of the plurality of via holes are shown inFIG. 11e. Then, as shown inFIG. 11a, a conductor layer D1(i.e., the data conductor layer or the circuit conductor layer) may be formed on the insulating layer J1. The left end of the conductor layer D1is connected to the data signal line in the display panel. The right end of the conductor layer D1is connected to the driver IC. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of via holes. Finally, the bearing substrate may be stripped to obtain the connector as shown inFIG. 11a.

It should be noted that, in the sixth implementation manner and the seventh implementation manner of the connector, only one insulating layer is arranged between the two conductor layers in the connector, such that the processes may be reduced and the cost may be saved.

Exemplarily, the water blocking layer, the buffer layer, the auxiliary insulating layer and the target insulating layer inFIGS. 5ato 11emay be made of at least of the followings: silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), zirconia (ZrOx) and the like. The conductor layer may be made of one of molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), graphene, carbon nanotubes and the like, or may be made of an alloy or composite material consisting of several of molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), graphene, carbon nanotubes and the like.

As shown inFIG. 12, in order to solve the problem of the connector as shown inFIG. 3, before the conductor layer1032is manufactured, it is typically possible to etch a middle region of an inorganic material layer (including the water blocking layer1031e, the buffer layer1031d, the first gate insulating layer1031c, the second gate insulating layer1031band the interlayer insulating layer1031a) in the connector, such that etching holes are formed on the inorganic material layer. The middle portion is a region, which needs to be bent with a relatively great effort, in the inorganic material layer. Later, as shown inFIG. 13, the conductor layer1032may be formed after the etching holes are filled with a polymer H. That is, the inorganic material layer in the region which is bent with a relatively great effort is replaced with a polymer with small brittleness, thereby reducing the breakage probability of the substrate and further reducing the breakage risk of the conductor layer. However, in this solution, a step of etching the five-layer structure and a step of filling the polymer are added on the basis of the original process (FIG. 3), and the cost of the polymer is relatively high. Therefore, the cost of manufacturing the connector in this solution is relatively high.

However, an interlayer insulating layer is not included in the substrate of the connector provided in the embodiments of the present disclosure as shown inFIG. 4a,FIG. 4b,FIG. 5a,FIG. 6a,FIG. 7a,FIG. 8a,FIG. 9a,FIG. 10a, andFIG. 11a. Therefore, the substrate of the connector provided in the embodiments of the present disclosure is relatively thin, and the number of layers to be etched is relatively small, such that a groove is formed on the substrate at a relatively high speed. In addition, the connector provided in the embodiments of the present disclosure is not filled with a polymer, and therefore the cost of manufacturing the connector is relatively low.

FIG. 14is a schematic diagram of a structure of a display screen provided in an embodiment of the present disclosure. As shown inFIG. 14, the display screen14includes a display panel (not shown inFIG. 14), a driver IC (not shown inFIG. 14) and a connector142configured to connect the display panel and the driver IC. It should be noted thatFIG. 14illustrates the display screen when the connector142is not bent. When the connector142is bent, the driver IC is arranged on the non-display side of the display panel.

Exemplarily, the display panel may be a liquid crystal display panel or an OLED display panel. The display panel may include a substrate base (not shown inFIG. 14), and an active layer1411, a first gate insulating layer1412, a first gate signal line1413, a second gate insulating layer1414, a second gate signal line1415, an interlayer dielectric layer1416and a data signal line1417which are arranged on the substrate base in sequence. The first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer may be made of at least one of the followings: silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), zirconia (ZrOx) and the like. The first gate signal line, the second gate signal line and the data signal line may be made of one of molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), graphene, carbon nanotubes and the like, or may be made of an alloy or composite material consisting of several of molybdenum (Mo), aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), graphene, carbon nanotubes and the like.

It should be noted that a part of the structure in the connector142may be integrated with a part of the structure in the display panel101. Exemplarily, as shown inFIG. 14, a part of the structure in the connector142may be integrated with the substrate base in the display panel.

In addition, when the display screen is manufactured, the connector may be formed first by arranging, on a substrate, a conductor structure whose target surface away from the substrate is uneven. Then, one end of the conductor structure may be connected to the data signal line on the display panel, and the other end of the conductor structure may be connected to the driver IC. Finally, the connector can be bent, such that the driver IC is arranged on the non-display side of the display panel. Here, the display panel includes a substrate base, and an active layer, a first gate insulating layer, a first gate signal line, a second gate insulating layer, a second gate signal line, an interlayer dielectric layer and a data signal line which are arranged on the substrate base in sequence.

The display screen may be implemented in several manners based on different implementation manners of the connector. Here, only three of the implementation manners are illustrated as examples.

In the first implementation manner, referring toFIG. 14andFIG. 5a, or referring toFIG. 14andFIG. 6a, the auxiliary insulating layer6014in the connector may be formed of the same material layer as that of the first gate insulating layer1412in the display panel. The conductor layer D2in the connector may be formed of the same material layer as that of the first gate signal line1413in the display panel. The insulating layer J2in the connector may be formed of the same material layer as that of the second gate insulating layer1414in the display panel. The insulating layer J1in the connector may be formed of the same material layer as that of the interlayer dielectric layer1416in the display panel. The conductor layer D1in the connector may be formed of the same material layer as that of the data signal line1417in the display panel.

In the process of manufacturing the display screen, when two film layers formed of the same material layer in the display panel and the connector are manufactured, the same material layer may be formed first, and different regions of the same material layer are processed to obtain the two film layers in the display panel and the connector. Therefore, the steps of the manufacturing process are reduced, and the manufacturing time is saved.

Exemplarily, the PI substrate may be divided into a display region (a region where the display panel is to be arranged) and a non-display region. In the course of manufacturing the display screen, the PI substrate in the connector may be formed first. The active layer1411is formed on the display region (i.e., the substrate base in the display panel) of the PI substrate. A water blocking layer6012and a buffer layer6013are sequentially formed on the non-display region of the PI substrate. Later, a first gate insulating material layer is formed on the active layer1411and the buffer layer6013at the same time. The water blocking layer6012, the buffer layer6013and the first gate insulating layer on the non-display region of the PI substrate are etched to obtain the substrate601in the connector. At this time, the first gate insulating material layer located in the display region is the first gate insulating layer1412in the display panel, and the first gate insulating material layer in the non-display region is the auxiliary insulating layer6014in the connector.

Later, after the substrate601in the connector is obtained, a conductor material layer may be formed on the substrate601and the first gate insulating layer1412at the same time. The conductor material layer is processed to obtain the first gate signal line1413in the display panel and the conductor layer D2in the connector. Then, a second gate insulating material layer may be formed again on the first gate signal line1413and the conductor layer D2at the same time. The second gate insulating material layer located in the display region is the second gate insulating layer1414in the display panel, and the second gate insulating material layer located in the non-display region is the first target insulating layer (i.e., the insulating layer J2) in the connector. Later, a second gate signal line1415is formed on the second gate insulating layer1414, and then an interlayer dielectric material layer may be formed on the second gate signal line1415and the insulating layer J2at the same time. The interlayer dielectric material layer located in the display region is the interlayer dielectric layer1416in the display panel, and the interlayer dielectric material layer located in the non-display area is the second target insulating layer (i.e., the insulating layer J1) of the connector.

Finally, the two target insulating layers in the connector are etched to obtain a plurality of via holes, such that the formed conductor layer D2is exposed at the plurality of via holes. A data material layer is formed on the interlayer dielectric layer1416and the insulating layer J1at the same time. The data material layer is processed to obtain the data signal line1417in the display panel and the conductor layer D1in the connector. In addition, the conductor layer D1is in contact and connection with the conductor layer D2through the plurality of via holes.

In the second implementation manner, referring toFIG. 14andFIG. 7a, or referring toFIG. 14andFIG. 8a, or referring toFIG. 14andFIG. 9a, the auxiliary insulating layer6014in the connector may be formed of the same material layer as that of the first gate insulating layer1412in the display panel. The conductor layer D3in the connector may be formed of the same material layer as that of the first gate signal line1413in the display panel. The insulating layer J2in the connector may be formed of the same material layer as that of the second gate insulating layer1414in the display panel. The conductor layer D2in the connector may be formed of the same material layer as that of the second gate signal line1415in the display panel. The insulating layer J1in the connector may be formed of the same material layer as that of the interlayer dielectric layer1416in the display panel. The conductor layer D1in the connector may be formed of the same material layer as that of the data signal line1417in the display panel.

In the course of manufacturing the display screen, the PI substrate in the connector may be formed first. The active layer1411is formed on the display region of the PI substrate. A water blocking layer6012and a buffer layer6013are sequentially formed on the non-display region of the PI substrate. Later, a first gate insulating material layer is formed on the active layer1411and the buffer layer6013at the same time. The water blocking layer6012, the buffer layer6013and the first gate insulating layer which are located on the non-display region on the PI substrate are etched to obtain the substrate601in the connector. At this time, the first gate insulating material layer located in the display region is the first gate insulating layer1412in the display panel, and the first gate insulating material layer located in the non-display region is the auxiliary insulating layer6014in the connector.

Later, after the substrate601in the connector is obtained, a first conductor material layer may be formed on the substrate601and the first gate insulating layer1412at the same time. The first conductor material layer is processed to obtain a first gate signal line1413in the display panel and the conductor layer D3in the connector. Then, a second gate insulating material layer may be formed again on the gate signal line1413and the conductor layer D2at the same time. The second gate insulating material layer located in the display region is the second gate insulating layer1414in the display panel, and the second gate insulating material layer located in the non-display region is the first target insulating layer (i.e., the insulating layer J2) in the connector. Next, the insulating layer J2is etched to obtain a plurality of first via holes, such that the conductor layer D3is exposed at the plurality of first via holes. Thereafter, a second conductor material layer may be formed on the second gate insulating layer1414and the insulating layer J2at the same time. The second conductor material layer is processed to obtain the second gate signal line1415in the display panel and the conductor layer D2in the connector. In addition, the conductor layer D2is in contact and connection with the conductor layer D3through the plurality of first via holes. Then, an interlayer dielectric material layer is formed on the second gate signal line1415and the conductor layer D2at the same time. The interlayer dielectric material layer located in the display region is the interlayer dielectric layer1416in the display panel. The interlayer dielectric material layer located in the non-display region is the second target insulating layer (i.e., the insulating layer J1) of the connector.

Finally, the insulating layer J1is etched to obtain a plurality of second via holes, such that the formed conductor layer D2is exposed at the plurality of second via holes. A data material layer is formed on the interlayer dielectric layer1416and the insulating layer J1at the same time. The data material layer is processed to obtain the data signal line1416in the display panel and the conductor layer D1in the connector. In addition, the conductor layer D1is contact and connection with the conductor layer D2through the plurality of second via holes.

In the third implementation manner, referring toFIG. 14andFIG. 10a, or referring toFIG. 14andFIG. 11a, the auxiliary insulating layer6014in the connector may be divided into two layers: a first auxiliary layer and a second auxiliary layer. The first auxiliary layer may be a layer, away from the conductor layer, of the two auxiliary layers. The second auxiliary layer may be a layer, close to the conductor layer, of the two auxiliary layers. The first auxiliary layer is formed of the same material layer as that of the first gate insulating layer1412in the display panel. The second auxiliary layer is formed of the same material layer as that of the second gate insulating layer1414in the display panel. The conductor layer D2in the connector may be formed of the same material layer as that of the second gate signal line1415in the display panel. The insulating layer J1in the connector may be formed of the same material layer as that of the interlayer dielectric layer1416in the display panel. The conductor layer D1in the connector may be formed of the same material layer as that of the data signal line1417in the display panel.

In the course of manufacturing the display screen, the PI substrate in the connector may be formed first. The active layer1411is formed on the display region of the PI substrate. A water blocking layer6012and a buffer layer6013are sequentially formed on the non-display region of the PI substrate. Later, a first gate insulating material layer may be formed on the active layer1411and the buffer layer6013at the same time. At this time, the first gate insulating material layer located in the display region is the first gate insulating layer1412in the display panel, and the first gate insulating material layer located in the non-display region is the first auxiliary layer in the auxiliary insulating layer6014in the connector. Next, a first gate signal line1413may be formed on the first gate insulating layer1412. In addition, a second gate insulating material layer is formed on the first gate signal line1413and the first auxiliary layer at the same time. A second gate insulating material layer located in the display area is the second gate insulating layer1414. The second gate insulating material layer located in the non-display region is the second auxiliary layer in the auxiliary insulating layer6014. Thereafter, the water blocking layer6012, the buffer layer6013, the first auxiliary layer and the second auxiliary layer which are located on the non-display region of the PI substrate may be etched to obtain the substrate601in the connector.

Later, after the substrate601in the connector is obtained, a conductor material layer may be formed on the substrate601and the second gate insulating layer1414at the same time. The conductor material layer is processed to obtain the second gate signal line1415in the display panel and the conductor layer D2in the connector. Then, an interlayer dielectric material layer is formed on the second gate signal line1415and the conductor layer D2at the same time. The interlayer dielectric material layer located in the display region is the interlayer dielectric layer1416in the display panel. The interlayer dielectric material layer located in the non-display region is the target insulating layer (i.e., the insulating layer J1) of the connector.

Finally, the insulating layer J1is etched to obtain a plurality of via holes, such that the formed conductor layer D2is exposed at the plurality of via holes. A data material layer is formed on the interlayer dielectric layer1416and the insulating layer J1at the same time. The data material layer is processed to obtain the data signal line1417in the display panel and the conductor layer D1in the connector. In addition, the conductor layer D1is contact and connection with the conductor layer D2through the plurality of via holes.

From the above, the target surface of the conductor structure in the connector provided in the embodiments of the present disclosure is uneven, which is conductive to releasing the stress acting on the conductor structure when the substrate is bent. Therefore, the conductor structure is less affected by this stress, thereby reducing the probability of the conductor structure breaking under the stress of the substrate. Further, the case that the driver IC and the data signal line cannot be effectively connected due to the breakage of the conductor structure is prevented, and the display screen has a good display effect.

Additionally, there are used in the connector a plurality of conductor layers connected with each other. The data conductor layers in the plurality of conductor layers are connected to the data signal lines on the display panel. The circuit conductor layers in the plurality of conductor layers are connected to the driver IC arranged on the non-display side of the display panel. The driver IC may send control signals to the display panel through the plurality of conductor layers. When the connector is bent, even if one conductor layer is broken, the driver IC may also continue to be effectively connected to the data signal line through other conductor layers, such that the display screen may continue to have a good display effect.

The above embodiments of the display screen and the embodiments of the connector may be made reference to each other, which is not limited in the embodiments of the present disclosure. The foregoing descriptions are merely exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Within the spirit and principles of the disclosure, any modifications, equivalent substitutions, improvements, etc., are within the protection scope of appended claims of the present disclosure.