Method for fabricating light-emitting diode device

The invention provides a method for fabricating a light-emitting diode device. The method includes providing a carrier having a first surface and a second surface. The first surface has insulating micro patterns. A buffer layer, a first-type semiconductor layer, a light-emitting layer and a second-type semiconductor layer are grown on the first surface to form a light-emitting lamination layer. A substrate is provided for the second-type semiconductor layer to bond on. The carrier is lifted off from the light-emitting lamination layer by a laser lift-off process, and surfaces of the insulating micro patterns and a surface of the buffer layer between the insulating micro patterns are exposed. The insulating micro patterns and the buffer layer are removed. Recess structures are formed on the first-type semiconductor layer. A surface-roughing process is then performed on the recess structures.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of Taiwan Patent Application No. 102144771, filed on Dec. 6, 2013, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating a light-emitting diode (LED) device, and in particular it relates to a surface-roughing process in fabricating an LED device.

2. Description of the Related Art

Light-emitting diodes (LEDs) have two configurations. The LED that has electrodes arranged on the same side of an LED chip is called a horizontal LED. The LED that has electrodes arranged on the opposite sides of an LED chip is called a vertical LED. A current path flowing in and out of a semiconductor light-emitting layer of the horizontal LED needs to be turned in a direction horizontal to the LED chip. A current path can flow in and out of a semiconductor light-emitting layer of the vertical LED without turning in different directions.

The LED chip of the LED device usually grows on a substrate wafer by an epitaxial growth method. In fabrication processes of the LED device, however, the substrate wafer need to be cut to fabricate the individual LED chips for epitaxial layers to grow on the LED chips. The loss due to the substrate wafer sawing process is high when the LED chips have a small area. Therefore, the total light-emitting area of the substrate wafer is reduced. Further, a sapphire carrier removal process is required to be adopted in the conventional fabrication processes of the LED device. The sapphire carrier removal process is too complex to control the fabrication cost and yield.

Thus, a novel LED device and a method for fabricating the same are desired.

BRIEF SUMMARY OF THE INVENTION

A method for fabricating a light-emitting diode device is provided. An exemplary embodiment of the method includes providing a carrier having a first surface and a second surface on opposite sides of the carrier. The first surface has a plurality of insulating micro patterns. The carrier and the plurality of insulating micro patterns are formed by different materials. A buffer layer, a first-type semiconductor layer, a light-emitting layer and a second-type semiconductor layer are grown on the first surface of the carrier in sequence to form a light-emitting lamination layer. A substrate is provided for the second-type semiconductor layer of the light-emitting lamination layer to bond on. The carrier is lifted off from the light-emitting lamination layer by a laser lift-off process, and surfaces of the plurality of insulating micro patterns and a surface of the buffer layer between the plurality of insulating micro patterns are exposed. The plurality of insulating micro patterns and the buffer layer are removed. A plurality of recess structures is formed on the first-type semiconductor layer. A surface-roughing process is then performed on the plurality of recess structures.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with respect to embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.

Embodiments provide a method for fabricating a light-emitting diode (LED) device. In some embodiments, the LED device includes a horizontal LED device or a vertical LED device. The method for fabricating an LED device uses a sapphire carrier having a plurality of silicon oxide micro patterns for a light-emitting lamination layer to be formed thereon. Compared with the conventional method for fabricating an LED device, one embodiment of a lift-off process which is used to lift off the sapphire carrier for fabricating the LED device only focuses a laser beam on an interface between the sapphire carrier and the silicon oxide micro patterns with a planar profile. The planar interface can reduce depth of focus (DOF) of the laser beam, so that the maximum energy density of the laser beam is reduced. Also, a wet etching method can be performed to remove the μm-scaled silicon oxide micro patterns after performing the lift-off process for the sapphire carrier, so that an n-type semiconductor layer of the light-emitting lamination layer is formed as a plurality of μm-scaled recess structures. Additionally, a surface-roughing process is performed by a wet or dry etching method to further roughen surfaces of the μm-scaled recess structures of the n-type semiconductor layer, so that the surfaces of the μm-scaled recess structures are roughened as surfaces with an nm-scaled roughness. The surface-roughing process can destroy the smooth surfaces of the recess structures to increase the light-emitting efficiency of the LED device.

FIGS. 1-8are schematic cross-sectional views of one embodiment of a method for fabricating a light-emitting diode (LED) device500aof the invention. In this embodiment, the LED device500aserves as a horizontal LED device500a. Please refer toFIG. 1. Firstly, a carrier200is provided. The carrier200has a first surface201aand a second surface201bon opposite sides of the carrier200. In one embodiment, the carrier200is formed of sapphire.

Next, please refer toFIG. 2. An insulating layer202is formed on the first surface201aof the carrier200. The insulating layer202may be formed using thin-film deposition methods including an e-gun method, a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. In one embodiment, the insulating layer202may be formed of insulating materials including silicon oxide. In one embodiment, the carrier200and the insulating layer202are formed of different materials.

Next, please refer toFIG. 3. A photolithography process is performed to form a mask pattern (not shown) on the insulating layer202. In one embodiment, the size of the mask pattern is in the μm scale. The size of the mask pattern is in a range between about 1 μm and 5 μm. Next, an anisotropic etching process, for example, an inductively coupled plasma reactive ion etching (ICP-RIE) process, is performed to remove the insulating layer202without being covered by the mask pattern. Also, the mask pattern is over-etched during the anisotropic etching process. Next, the remaining mask pattern is removed to form a plurality of insulating micro patterns204. In one embodiment, the insulating micro patterns204may be silicon oxide micro patterns. In one embodiment, the size of the insulating micro patterns204, which is in the μm scale, is substantially the same as that of the mask pattern. The size of the insulating micro patterns204is in a range between about 1 μm and 5 μm. In one embodiment, the carrier200and the insulating micro patterns204are formed of different materials.

Next, please refer toFIG. 4, a buffer layer208, a first-type semiconductor layer210, a light-emitting layer212and a second-type semiconductor layer214are grown on the first surface201of the carrier200in sequence to form a light-emitting lamination layer216. In one embodiment, the first-type semiconductor layer210, the light-emitting layer212and the second-type semiconductor layer214are grown by thin-film deposition methods including a metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process. In one embodiment, a surface230of the buffer layer208is in contact with the insulating micro patterns204as shown inFIG. 4.

It should be noted that the terms “first-type” and “second-type” in the description hereinafter are used to describe a conduction type of a semiconductor layer. The first-type is a conduction type opposite to the second-type. For example, if the first-type is n-type, the second-type is p-type. Alternatively, if the first-type is p-type, the second-type is n-type. In this embodiment, the first-type semiconductor layer210is an n-type semiconductor layer, and the second-type semiconductor layer214is a p-type semiconductor layer. Also, in one embodiment, the first-type semiconductor layer210and the second-type semiconductor layer214may be formed of semiconductor materials including GaN, GaP, GaAsP, AlGaAs, InGaAlP or InGaN. In this embodiment, the first-type semiconductor layer210is an n-type GaN layer, and the second-type semiconductor layer214is a p-type GaN layer. Additionally, in one embodiment, the buffer layer208is an un-doped semiconductor layer. The buffer layer208is used to reduce stresses and defects occurring because of the lattice mismatch during the growth of the light-emitting lamination layer216. In one embodiment, the light-emitting layer212may be a semiconductor layer having multiple quantum wells (MQWs). For example, the light-emitting layer212may be formed of semiconductor materials including GaN or InGaN.

Next, an etching process is performed on an area217of the light-emitting lamination layer216as shown inFIG. 4. The etching process is performed from a surface215away from the light-emitting layer212to partially remove the second-type semiconductor layer214, the light-emitting layer212and first-type semiconductor layer210to expose a portion of the first-type semiconductor layer210a. After performing the aforementioned processes, a light-emitting mesa structure211, which includes the first-type semiconductor layer210a, a light-emitting layer212aand a second-type semiconductor layer214a, is formed as shown inFIG. 5.

Next, a photolithography process is performed to form a photoresist layer (not shown) covering an exposed surface of the first-type semiconductor layer210aand an exposed surface (i.e. the surface215) of the second-type semiconductor layer214aof the light-emitting mesa structure211as shown inFIG. 5. The photoresist layer has at least two openings (not shown), and a portion of the first-type semiconductor layer210aand a portion of the second-type semiconductor layer214aare exposed to the at least two openings. In one embodiment, formation positions of the at least two openings correspond to contact positions defined on the first-type semiconductor layer210aand the second-type semiconductor layer214aof the light-emitting mesa structure211. Next, a deposition process such as an electroplating method is performed to fill a conductive material (not shown) into the at least two openings of the photoresist layer. The conductive material is fully filled the at least two openings. In one embodiment, the conductive material may be formed of copper (Cu), gold (Au), silver (Ag) or combinations thereof. Next, a planarization process, such as an etching back process, is performed to remove a portion of the conductive material over the photoresist layer, so that a top surface of the conductive material is substantially aligned to that of the photoresist layer. After performing the planarization process, a first electrode218and a second electrode220are respectively formed on the first-type semiconductor layer210aand the second-type semiconductor layer214aof the light-emitting mesa structure211as shown inFIG. 5.

Next, a substrate226is provided as shown inFIG. 5. Next, the light-emitting mesa structure211is flipped up-side down, so that the surface215of the second-type semiconductor layer214afaces down. Next, a flip-chip bonding process is performed so that the first-type semiconductor layer210aand the second-type semiconductor layer214aof the light-emitting mesa structure211are bonded to a surface of the substrate226respectively through the first electrode218and the second electrode220. In one embodiment, the substrate226may be a semiconductor substrate including a pad layer226aand an ohmic contact layer226b. The substrate226bonds to the first electrode218and the second electrode220of the light-emitting lamination layer211through the ohmic contact layer226b. In other embodiments, the substrate226may serve as a metal substrate, such as a copper substrate. In one embodiment, the first electrode218and the second electrode220of the light-emitting lamination layer211bond to a surface217of the substrate226through the solder bumps222and224, respectively. In one embodiment, the solder bumps222and224may be formed of Sn—Ag alloys, Sn—Cu alloys, Ni—Ag alloys or combinations thereof.

Next, a laser lift-off process228is performed to lift the carrier200off the light-emitting lamination layer211, and surfaces205of the plurality of insulating micro patterns204and a surface209of the buffer layer208between the plurality of insulating micro patterns204are exposed as shown inFIG. 6. Please refer toFIGS. 6 and 16.FIG. 16is a schematic diagram of one embodiment of a laser lifting process, showing a focus position of a laser beam229. While performing the laser lifting process228, the laser beam229of the laser lifting process228is focused on an interface (also positioned at the first surface201aof the carrier200) between the carrier200and the plurality of insulating micro patterns204and scans along the interface. Therefore, the carrier200is lifted off from the surfaces205of the plurality of insulating micro patterns204and the surface209of the buffer layer208between the plurality of insulating micro patterns204. In one embodiment, the interface is substantially a planar surface. Compared with the conventional laser lift-off process, which is required to be focused on a roughened surface of a patterned sapphire substrate (PSS), one embodiment of the laser lift-off process228has a larger process window than the conventional laser lift-off process.

Next, the plurality of insulating micro patterns204and the buffer layer208as shown inFIG. 6are removed until the first-type semiconductor layer210ais exposed. Therefore, a plurality of recess structures230is formed on the first-type semiconductor layer210aas shown inFIG. 7. In one embodiment, the plurality of insulating micro patterns204is removed by a wet etching process246. In this embodiment, because the plurality of insulating micro patterns204is formed of silicon oxide materials, the plurality of insulating micro patterns204is removed by a buffer oxide etching (BOE) process. The plurality of insulating micro patterns204can be totally removed by the BOE process. Additionally, in one embodiment, the size of the plurality of recess structures230is in μm scale, and the size is in a range between about 1 μm and 5 μm.

Next, a surface-roughing process246is performed to roughen a plurality of surfaces of the plurality of recess structures230, so that a plurality of roughened recess structures230ais formed as shown inFIG. 8. In one embodiment, the surface-roughing process is performed by a dry etching or a wet etching process. In this embodiment, the surface-roughing process is performed using KOH as an etchant. In one embodiment, the size of surfaces of the plurality of roughened recess structures230ais nm scale, and the size is in a range between about 10 nm and 1000 nm. After performing the aforementioned processes, one embodiment of the LED device500ais completely formed.

FIGS. 9-15are schematic cross-sectional views of another embodiment of a method for fabricating an LED device500bof the invention. Elements of the embodiments that are the same or similar as those previously described with reference toFIGS. 1-8are hereinafter not repeated for brevity.

Firstly, a carrier200as shown inFIGS. 1-4is provided. The carrier200has a first surface201aand a second surface201bon opposite sides of the carrier200. In one embodiment, the carrier200and the insulating micro patterns204are formed of different materials. Next, a buffer layer208, a first-type semiconductor layer210, a light-emitting layer212and a second-type semiconductor layer214are grown on the first surface201aof the carrier200in sequence to form a light-emitting lamination layer216as shown inFIG. 4.

Next, please refer toFIG. 9. A substrate240is provided. In one embodiment, the substrate240may be a semiconductor substrate232including a pad layer234and an ohmic contact layer236.

Next, please refer toFIG. 10. The light-emitting lamination layer216is then flipped up-side down, so that the surface215of the second-type semiconductor layer214afaces down. Next, a flip-chip bonding process is performed so that the substrate240is bonded to the second-type semiconductor layer214of the light-emitting lamination layer216. After performing the flip-chip bonding process, the surface215of the second-type semiconductor layer214, which is away from the light-emitting layer212, is in contact with the ohmic contact layer236of the substrate240.

Next, a laser lift-off process228is performed to lift off the carrier200from the light-emitting lamination layer211, and surfaces205of the plurality of insulating micro patterns204and a surface209of the buffer layer208between the plurality of insulating micro patterns204are exposed as shown inFIG. 11. Please refer toFIGS. 11 and 16.FIG. 16is a schematic diagram of one embodiment of a laser lifting process, showing a focus position of a laser beam229. While performing the laser lifting process228, the laser beam229of the laser lifting process228is focused on an interface (also positioned at the first surface201aof the carrier200) between the carrier200and the plurality of insulating micro patterns204and scans along the interface. In one embodiment, the interface is substantially a planar surface. Compared with the conventional laser lift-off process, which is required focused on a rough surface of a patterned sapphire substrate (PSS), one embodiment of the laser lift-off process228has a larger process window than the conventional laser lift-off process.

Next, the plurality of insulating micro patterns204as shown inFIG. 11is removed until the buffer layer208is exposed. Therefore, a plurality of recess structures231is formed on the first-type semiconductor layer210as shown inFIG. 12. In one embodiment, the plurality of insulating micro patterns204is removed by a wet etching process246. In this embodiment, because the plurality of insulating micro patterns204is formed of silicon oxide materials, the plurality of insulating micro patterns204is removed by a buffer oxide etching (BOE) process. The plurality of insulating micro patterns204can be totally removed by the BOE process. Additionally, in one embodiment, the size of the plurality of recess structures231is substantially the same as that of the plurality of insulating micro patterns204. The size of the plurality of recess structures231is in μm scale, and the size is in a range between about 1 μm and 5 μm.

Next, a dry etching process242, such as inductively coupled plasma reactive ion etching (ICP-RIE), is performed by using the buffer layer208as shown inFIG. 12as an etching mask until the buffer layer208is entirely removed. Also, a portion of the first-type semiconductor layer210as shown inFIG. 12is removed. After performing the dry etching process242, a shape of the plurality of recess structures231is transferred to the first-type semiconductor layer210as shown inFIG. 12, so that a first-type semiconductor layer210bhaving a plurality of recess structures244is formed. Similarly, the size of the plurality of recess structures244of the first-type semiconductor layer210bis substantially the same as that of the plurality of insulating micro patterns204. The size of the plurality of recess structures244is in μm scale, and the size is in a range between about 1 μm and 5 μm.

Next, a surface-roughing process246is performed to roughen a plurality of surfaces of the plurality of recess structures244of the first-type semiconductor layer210b, so that a plurality of roughened recess structures244bis formed as shown inFIG. 14. Also, the light-emitting layer212and the second-type semiconductor layer214and the first-type semiconductor layer210bare collectively composed of a light-emitting lamination layer216bhaving the plurality of roughened recess structures244b. In one embodiment, the surface-roughing process is performed by a dry etching or a wet etching process. In this embodiment, the surface-roughing process is performed using KOH as an etchant. In one embodiment, the size of surfaces of the plurality of roughened recess structures230ais nm scale, and the size is in a range between about 10 nm and 1000 nm.

Next, a photolithography process is performed to form a photoresist layer covering the surfaces of the plurality of recess structures244bof the first-type semiconductor layer210bof the light-emitting lamination layer216bas shown inFIG. 15. The photoresist layer has at least one opening (not shown) to expose the first-type semiconductor layer210b. In one embodiment, formation positions of the at least one opening may correspond to a contact position defined on the first-type semiconductor layer210bof the light-emitting lamination layer216b. Next, a deposition process such as an electroplating method is performed to fill a conductive material (not shown) into the at least one opening of the photoresist layer. The conductive material is entirely filled the at least one opening. In one embodiment, the conductive material may be formed of copper (Cu), gold (Au), silver (Ag) or combinations thereof. Next, a planarization process, such as an etching back process, is performed to remove a portion of the conductive material over the photoresist layer, so that a top surface of the conductive material is substantially aligned to that of the photoresist layer. After performing the planarization process, a first-type electrode250is formed on the first-type semiconductor layer210bhaving the plurality of recess structures244b. After performing the aforementioned processes, one embodiment of the LED device500bis formed completely.

FIG. 17Ais a schematic diagram of depth of focus (DOF) of the conventional laser lifting process.FIG. 17Bis a schematic diagram showing a relationship between depth of focus (DOF) and energy of the conventional laser lifting process.FIG. 17Cis a schematic diagram of depth of focus (DOF) of one embodiment of a laser lifting process of the invention.FIG. 17Dis a schematic diagram showing a relationship between depth of focus (DOF) and energy of one embodiment of a laser lifting process of the invention. Please refer toFIGS. 17A and 17B, during performing the conventional laser lifting process, a laser beam129is required to be focused a roughened surface101aof the conventional patterned sapphire substrate (PSS)100. Also, energy of the laser beam129positioned at any point of the roughened surface101ais required to be larger than 850 mJ/cm2to ensure entirely lifting the conventional PSS100from a conventional buffer layer108. The surface-roughness (Ra) of the roughened surface101aof the conventional PSS100(i.e. an interface between the conventional PSS and the conventional buffer layer108of the conventional light-emitting lamination layer) is about 1000 nm. Therefore, the DOF of the laser beam129of the conventional laser lifting process (e.g. a depth of an area160) is required to be enlarged to about 1000 nm. Additionally, during performing the laser lifting process, the energy of the laser beam to lift the PSS is required to be larger than 850 mJ/cm2. Therefore, the energy of the laser beam129of the conventional laser lifting process is required to be larger than about 1300 mJ/cm2as show inFIG. 17B. The laser beam having over-high energy density will damage the LED devices and results in a low yield. Please refer toFIGS. 17C and 17D. Conversely, the laser beam229of one embodiment of a laser lifting process is focused on a planar interface (i.e. the first surface201aof the carrier200which is in contact with the buffer layer208) between the carrier200and the plurality of insulating micro patterns204. Therefore, the DOF of the laser beam229of one embodiment of a laser lifting process (e.g. a depth of the area260) is much less than that of the laser beam129of the conventional laser lifting process (e.g. a depth of the area260as shown inFIGS. 17A and 17B). The DOF of the laser beam229of one embodiment of the laser lifting process is only 25 nm (corresponding to the surface-roughness of the interface). Therefore, the maximum energy density of the laser beam229of one embodiment of the laser lifting process is required only to be larger than 850 mJ/cm2to ensure lifting off the carrier200such as a sapphire substrate. The maximum energy density of the laser beam229of one embodiment of the laser lifting process is much lower than that of the laser beam129of the conventional laser lifting process (FIG. 17B). One embodiment of the laser lifting process can reduce the maximum energy density of the laser beam, so that the LED device can be prevented from damage. The process yield of the LED device can be improved.

Embodiments provide a method for fabricating a light-emitting diode device. Compared with the conventional LED device fabrication processes, one embodiment of the laser lifting process is performed by focusing on a planar interface between the sapphire carrier and the silicon oxide micro patterns. One embodiment of the laser lifting process can reduce the maximum energy density of the laser beam, so that the LED device can be prevented from damages. The process yield of the LED device can be improved. Additionally, after removing the μm-scaled silicon oxide micro patterns, the μm-scaled recess structures can be formed on the n-type semiconductor layer. Also, after performing the surface-roughing process to roughen the n-type semiconductor layer, the μm-scaled recess structures can be roughened to have nm-scaled roughened surfaces. The n-type semiconductor layer having the μm-scaled recess structures with the nm-scaled roughened surfaces can further increase the light-emitting efficiency of the LED device.