Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects

A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

BACKGROUND

Technical Field

The present invention relates generally to semiconductor devices, and more specifically, to integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects.

Description of the Related Art

Unlike conventional random access memory (RAM) chip technologies, magnetic RAM (MRAM) does not store data as electric charge, but instead stores data by magnetic polarization of storage elements. Typically, storage elements are formed from two ferromagnetic layers separated by a tunneling layer. One of the ferromagnetic layers has at least one pinned magnetic polarization (or fixed layer) set to a particular polarity. The magnetic polarity of the other ferromagnetic layer (or free layer) is altered to represent either a “1” (i.e., anti-parallel polarity to the fixed layer) or “0” (i.e., parallel polarity to the fixed layer). One device having a fixed layer, a tunneling layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of a MTJ is dependent on the magnetic polarity of the free layer compared to the magnetic polarity of the fixed layer. A memory device such as MRAM can be built from an array of individually addressable MTJs.

SUMMARY

In accordance with an embodiment, a method is provided for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks.

In accordance with another embodiment, a semiconductor device is provided. The semiconductor device includes a barrier layer, such as a tantalum nitride (TaN) layer, deposited over a dielectric incorporating magnetic random access memory (MRAM) regions, magnetic tunnel junction (MTJ) stacks deposited over portions of the TaN layer, the MTJ stacks patterned and encapsulated, and spacers formed adjacent the MTJ stacks. The sections of the TaN layer are laterally etched to form an electrode under the MTJ stacks.

DETAILED DESCRIPTION

Embodiments of the present invention relate generally to a method for forming a semiconductor structure. The method includes depositing a tantalum nitride (TaN) layer over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks.

Moreover, embodiments of the present invention relate generally to a semiconductor device. The semiconductor device includes a tantalum nitride (TaN) layer deposited over a dielectric incorporating magnetic random access memory (MRAM) regions, magnetic tunnel junction (MTJ) stacks deposited over portions of the TaN layer, the MTJ stacks patterned and encapsulated, and spacers formed adjacent the MTJ stacks. Sections of the TaN layer are laterally etched to form an electrode under the MTJ stacks.

In one or more embodiments, the assembly of the semiconductor structure is started with a finished damascene level, which is planarized and finished with a barrier cap. MRAM regions are created, TaN and MTJ stacks are deposited, MTJs are patterned stopping on the TaN, and followed by encapsulation. Subsequently, spacer formation around the MTJ stacks is performed and lateral etching takes place to pull back the TaN below offset spacer, but still protect the MRAM regions.

In one or more embodiments, a structure and method to fabricate a MTJ pillar on a landing pad is presented. The MTJ is surrounded by an offset spacer and the metal below the MTJ is laterally etched, i.e., pulled back with respect to the spacer. The offset spacer can be a single material or multiple materials, and can also be L-shaped. If required for yield and reliability, for example, in case of copper (Cu) landing pads, the metal film below the MTJ is pulled back below the offset spacer, but the pull back is stopped prior to reaching the landing pad. If required for device performance, airgaps can be integrated into the process flow. Therefore, the structure and method protect the landing pads below the MTJ islands and minimize any sputtering/re-deposition onto the MTJ pillar through the use of an offset spacer and lateral etch. The process flow also requires less planarization and masking steps. The offset spacer and the lateral etch protect the landing pads and prevent re-deposition of metallic residues onto the MTJ pillar.

In one or more embodiments, the methods described herein protect the MTJ by only wet etching after the spacer is deposited, and using a wet etch tailored to remove TaN. Additionally, the methods described herein use a wet etch to open the bottom electrode after stopping IBE in the blanket bottom electrode TaN film.

In one or more embodiments, the bottom electrode protects the landing pads due to offset spacers, the bottom electrode is recessed from the spacer, wet etch for the bottom electrode does not leave metallic residues on the spacer (i.e., no shorting path between bitline and landing pads), and the landing pads and logic regions are protected during aggressive MTJ pillar etching.

As used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor.

A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields.

As used herein, the term “drain” means a doped region in the semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain.

As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel.

The term “direct contact” or “directly on” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure can be present between the first element and the second element.

The term “electrically connected” means either directly electrically connected, or indirectly electrically connected, such that intervening elements are present; in an indirect electrical connection, the intervening elements can include inductors and/or transformers.

The term “crystalline material” means any material that is single-crystalline, multi-crystalline, or polycrystalline.

The term “non-crystalline material” means any material that is not crystalline; including any material that is amorphous, nano-crystalline, or micro-crystalline.

The term “intrinsic material” means a semiconductor material which is substantially free of doping atoms, or in which the concentration of dopant atoms is less than 1015atoms/cm3.

As used herein, the terms “insulating” and “dielectric” denote a material having a room temperature conductivity of less than about 10−10(Ω-m)−1.

As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium.

As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.

As used herein, an “anisotropic etch process” denotes a material removal process in which the etch rate in the direction normal to the surface to be etched is greater than in the direction parallel to the surface to be etched. The anisotropic etch can include reactive-ion etching (RIE).

Reactive ion etching (RIE) is a form of plasma etching in which during etching the surface to be etched is placed on the RF powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface. Other examples of anisotropic etching that can be used include ion beam etching, plasma etching or laser ablation.

The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, stripping, implanting, doping, stressing, layering, and/or removal of the material or photoresist as required in forming a described structure.

The terms “gas” and “gases” are used interchangeably, unless otherwise noted, and refer to one or more precursors, reactants, catalysts, carrier, purge, cleaning, combinations thereof, as well as any other fluid introduced into the chamber body.

The semiconductor devices described herein can be any type of device. Exemplary types of semiconductor devices include planar field effect transistors (FETs), fin-type field effect transistors (FinFETs), nanowire/nanosheet devices, vertical field effect transistors (VFETs), or other devices.

FIG. 1is a cross-sectional view of a semiconductor structure including magnetic random access memory (MRAM) regions incorporated within a dielectric, in accordance with an embodiment of the present invention.

A semiconductor structure5includes a semiconductor substrate10. Magnetic random access memory (MRAM) regions14are formed within the semiconductor substrate10. For example, two MRAM regions14are shown. A low-k barrier12(BLOk) is deposited over the top portion of the MRAM regions14and the top surface of the substrate10. The top surface of the MRAM regions14is flush with the top surface of the substrate10. The low-k barrier12can be, e.g., an n-type low-k barrier.

In one or more embodiments, the substrate10can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate10can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate10can be essentially (i.e., except for contaminants) a single element (e.g., silicon), primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate10can include a compound, for example, Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate10can also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate10can also have other layers forming the substrate10, including high-k oxides and/or nitrides. In one or more embodiments, the substrate10can be a silicon wafer. In an embodiment, the substrate10is a single crystal silicon wafer.

The low-k CVD barrier film12, designated BLOk, is engineered as an alternative to silicon nitride films. It is designed to reduce the dielectric constant (k) of copper damascene structures in order to achieve faster, more powerful devices. With a dielectric constant of less than 5, the film offers up to twice the etch selectivity of SiN, demonstrates leakage that is six to seven orders of magnitude better than conventional silicon carbide (SiC) material, and features good adhesion to other films. The amorphous film is composed of silicon (Si), carbon (C) and hydrogen (H).

MRAM regions14are a type of non-volatile computer memory that utilizes a Magnetic Tunneling Junction (MTJ) comprised of two ferromagnetic films, or plates, separated by a thin insulating layer to form magnetic storage elements. It will be recognized that the magnetic material can be any suitable material, combination of materials, or alloy that exhibits magnetic properties, such as a ferromagnetic material or a ferromagnetic thin film including CoFe, CoFeB, NiFe, etc. By sharing MRAM manufacturing processes with magnetic film integration techniques, the embodiments described herein are able to more efficiently provide integrated magnetic field enhanced circuit elements.

FIG. 2is a cross-sectional view of the semiconductor structure ofFIG. 1where a top surface of a portion of the MRAM regions is exposed, in accordance with an embodiment of the present invention.

The low-k barrier12is etched to expose the top surface15of the MRAM regions14. The low-k barrier12is etched such that a portion of the MRAM regions14are exposed. The lithography needed for this step can be a low cost mask with very large dimensions.

In various embodiments, the materials and layers can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, for example plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions can be epitaxial processes, and the deposited material can be crystalline. In various embodiments, formation of a layer can be by one or more deposition processes, where, for example, a conformal layer can be formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill can be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.).

FIG. 3is a cross-sectional view of the semiconductor device ofFIG. 2where a tantalum nitride (TaN) layer is deposited, in accordance with an embodiment of the present invention.

In various embodiments, a TaN layer16is deposited. The TaN layer16extends from one end of the substrate10to the other end of the substrate10such that the TaN layer16covers the BLOk12, the top surface of the exposed substrate10and the top surface15of the MRAM regions14. TaN layer16is about 0.5 to 3 nanometers thick and is a conformal coating. Since the molecular diameter of TaN is about 0.42 nanometers, TaN layer16comprises one to six monolayers.

The TaN layer16can be deposited via sputtering. As used herein, “sputtering” means a method of depositing a film of material on a semiconductor surface. A target of the desired material, i.e., source, is bombarded with particles, e.g., ions, which knock atoms from the target, and the dislodged target material deposits on the deposition surface. Examples of sputtering techniques include, but are not limited to, DC diode sputtering (“also referred to as DC sputtering”), radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering.

Examples of sputtering apparatus that can be suitable for depositing a p-type work function metal layer include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In addition to physical vapor deposition (PVD) techniques, the p-type work function metal layer can also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).

FIG. 4is a cross-sectional view of the semiconductor device ofFIG. 3where magnetic tunnel junction (MTJ) stacks are formed over portions of the TaN layer, in accordance with an embodiment of the present invention.

In various embodiments, MTJ stacks18are deposited over portions of the TaN layer16. A SiN layer20can then be deposited over the MTJ stacks18, as well as over the remaining TaN layer16portions. The MTJ stacks18are aligned with the MRAM regions14. Stated differently, a longitudinal axis extends through a center point of the MTJ stacks18and the MRAM regions14. The SiN layer20extends a distance X over the TaN layer16positioned over the low-k barrier12, whereas the SiN layer20extends a distance D over the MTJ stacks18.

In some embodiments, depositing the SiN layer20comprises exposing the metal nitride film to a first deposition gas and a second deposition gas, either simultaneously (e.g., CVD) or sequentially (e.g., ALD). The first deposition gas can comprise any suitable silicon-containing precursor and the second deposition gas can comprise any suitable reactive gas capable of reacting with the first deposition gas. In some embodiments, the first deposition gas comprises disilane and a second deposition gas comprises ammonia and exposing the plasma treated metal nitride film to the deposition gases forms a metal-SiN film.

The magnetic tunnel junction (MTJ) stacks18are each comprised of two layers of ferromagnetic material separated by a thin insulating tunnel barrier layer. The insulating layer is sufficiently thin that quantum-mechanical tunneling of the charge carriers occurs between the ferromagnetic electrodes. The tunneling process is electron spin dependent, which means that the tunneling current across the junction depends on the spin-dependent electronic properties of the ferromagnetic materials and is a function of the relative orientation of the magnetic moments (magnetization directions) of the two ferromagnetic layers. The two ferromagnetic layers are designed to have different responses to magnetic fields so that the relative orientation of their moments can be varied with an external magnetic field. The MTJ is usable as, e.g., a memory cell in a nonvolatile magnetic random access memory (MRAM) array, and as, e.g., a magnetic field sensor, such as a magnetoresistive read head in a magnetic recording disk drive.

MRAM is a type of solid state memory that uses tunneling magnetoresistance (TMR) to store information. MRAM is made up of an electrically connected array of magnetoresistive memory elements, referred to as magnetic tunnel junctions (MTJs). Each MTJ includes a free layer having a magnetization direction that is variable, and a fixed layer having a magnetization direction that is invariable. The free layer and fixed layer each include a layer of a magnetic material, and are separated by an insulating non-magnetic tunnel barrier. An MTJ stores information by switching the magnetization state of the free layer. When the magnetization direction of the free layer is parallel to the magnetization direction of the fixed layer, the MTJ is in a low resistance state. When the magnetization direction of the free layer is antiparallel to the magnetization direction of the fixed layer, the MTJ is in a high resistance state. The difference in resistance of the MTJ can be used to indicate a logical ‘1’ or ‘0’, thereby storing a bit of information. The TMR of an MTJ determines the difference in resistance between the high and low resistance states. A relatively high difference between the high and low resistance states facilitates read operations in the MRAM.

FIG. 5is a cross-sectional view of the semiconductor device ofFIG. 4where a first etch is performed to create spacers adjacent the MTJ stacks, in accordance with an embodiment of the present invention.

In various embodiments, the SiN layer20is etched such that spacers22are formed adjacent the MTJ stacks18. The top surface19of the MTJ stacks18are exposed. The spacers22extend beyond a length of the MTJ stacks18. The spacers22also have a thickness greater than the thickness of the MTJ stacks18.

The spacers22can be formed by deposition followed by a directional etch (e.g., RIE). Spacers22can be formed along the sidewalls of the MTJ stacks18. For example, spacer material such as a nitride (e.g., silicon nitride) can be deposited in a conventional manner, such as by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Other techniques, which can be suitable for deposition of a nitride layer, include low-pres sure CVD (LPCVD) and atmospheric pressure (CVD) (APCVD). Portions of the deposited nitride layer are subsequently etched away in a conventional manner to form the spacers22. Spacer material can be silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOCN, SiOC, or any suitable combination of those materials.

FIG. 6is a cross-sectional view of the semiconductor device ofFIG. 5where a second etch is performed, the etch forming an electrode between each MRAM region and MTJ stack, in accordance with an embodiment of the present invention.

In various embodiments, an etch is performed to selectively remove portions of the TaN layer16such that electrodes24are formed between the MTJ stacks18and the MRAM regions14. The electrode24has a top surface26and a bottom surface28. The top surface26engages the MTJ stack18and the bottom surface28engages the top surface15of the MRAM region14. The bottom surface28of the electrode24extends beyond a top surface15of the MRAM region14. Thus, the length of the electrode24is greater than the length of the MRAM region14. Stated differently, the MRAM regions14(or metal islands) are fully encapsulated by the TaN electrodes24. The electrodes24fully block or cover the MRAM regions14such that the top surface15of the MRAM regions14is not exposed.

Additionally, the electrodes24are separated from each other by a distance designated by element25. It is further noted that a bottom surface of the spacers22extends beyond the top surface15of the MRAM regions14and further extends beyond the bottom surface28of the electrodes24.

As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, in one embodiment, a selective etch can include an etch chemistry that removes a first material selectively to a second material by a ratio of 10:1 or greater, e.g., 100:1 or greater, or 1000:1 or greater.

FIG. 7is a cross-sectional view of the semiconductor device ofFIG. 6where dielectric deposition and planarization takes place, in accordance with an embodiment of the present invention.

In various embodiments, an inter-layer dielectric (ILD) fill takes place. The ILD30is planarized. The ILD30encompasses or envelopes or surrounds the MTJ stacks18. The ILD30engages an outer surface of the sidewall spacers22. In one example embodiment, the ILD30extends over a top point of the spacers22. Stated differently, the ILD30covers or encompasses or engulfs the spacers22, as well as the exposed portions of the electrodes24.

In one or more embodiments, the ILD30can have a thickness in the range of about 20 nm to about 150 nm, or in the range of about 30 nm to about 50 nm.

The ILD30can be selected from the group consisting of silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the ILD30include any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.

In various embodiments, the height of the ILD30can be selectively reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

FIG. 8is a cross-sectional view of the semiconductor device ofFIG. 7where damascene processing is performed, in accordance with an embodiment of the present invention.

In various embodiments, damascene processing is performed where a via32is filled with a conducting material (e.g., a metal) and a trench34is filled with a conducting material (e.g., a metal). The via32extends up to the BLOk12. The trench34extends over the MTJ stacks18such that the top surface19of each of the MTJ stacks18is exposed. The via32can be separated from the trench34by the ILD30.

The damascene process is a process in which interconnect metal lines are delineated in dielectrics isolating them from each other, not by means of lithography and etching, but by means of chemical-mechanical planarization (CMP). In this process interconnect pattern is first lithographically defined in the layer of dielectric then metal is deposited to fill resulting trenches and then excess metal is removed by means of chemical-mechanical polishing (planarization).

The dual-damascene process is a modified version of the damascene process which is used to form metal interconnect geometry using CMP process instead of metal etching. In dual damascene, two interlayer dielectric patterning steps and one CMP step create a pattern which would require two patterning steps and two metal CMP steps when using conventional damascene process.

In this process, a thick coating of metal, such as copper that significantly overfills the trenches is deposited on the insulator, and CMP is used to remove the copper (known as overburden) that extends above the top of the insulating layer. Copper sunken within the trenches of the insulating layer is not removed and becomes the patterned conductor. Damascene processes generally form and fill a single feature with copper per Damascene stage. Dual-Damascene processes generally form and fill two features with copper at once, e.g., a trench overlying a via can both be filled with a single copper deposition using dual-Damascene.

FIG. 9is a cross-sectional view of the semiconductor device ofFIG. 3where a silicon nitride (SiN) layer and a low temperature oxide (LTO) layer are deposited over the MTJ stacks, in accordance with another embodiment of the present invention.

In various embodiments, an alternative flow can result in forming L-shaped spacers, as described with respect toFIGS. 9-14. A semiconductor structure7includes a semiconductor substrate10. Magnetic random access memory (MRAM) regions14are formed within the semiconductor substrate10. A low-k barrier12(BLOk) is deposited over the top portion of an MRAM region14. A TaN layer16is deposited over the low-k barrier12and the remaining MRAM regions14. MTJ stacks18are formed directly over the MRAM regions14. A silicon nitride (SiN) layer40and a low temperature oxide (LTO) layer42are further deposited over the MTJ stacks18. The SiN layer40is a thinner layer than that deposited in the structure ofFIG. 4. The LTO layer42is thicker than the SiN layer40. The LTO layer42extends a distance X1over the TaN layer16positioned over the low-k barrier12, whereas the LTO layer42extends a distance D1over the MTJ stacks18. The SiN layer40and the LTO42can form a dual liner encapsulation.

FIG. 10is a cross-sectional view of the semiconductor device ofFIG. 9where a first etch is performed to create spacers adjacent the MTJ stacks, in accordance with an embodiment of the present invention.

In various embodiments, a first etch occurs to form spacers44adjacent the MTJ stacks18. The etching can include a dry etching process such as, for example, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layers that are not protected by the patterned photoresist. The patterned photoresist can be removed utilizing an ashing process. In one example embodiment, RIE is performed.

The etching further results in a top portion41of the SiN layer40to be exposed at the top portion of the MTJ stacks18. Additionally, the etching results in side portions43of the SiN layer40to be exposed adjacent the distal end of the spacers44. Moreover, the spacers44are formed such that a height of the spacers is less than a height of the SiN layer40extending along a side surface of the MTJ stack18. The height difference between the spacer44and the top portion41of the SiN layer40is designated as “A.”

FIG. 11is a cross-sectional view of the semiconductor device ofFIG. 10where a second etch is performed to remove certain SiN sections to form L-shaped spacers adjacent the MTJ stacks, in accordance with an embodiment of the present invention.

In various embodiments, a second etch occurs to remove the SiN layer40, as well as the top portion41of the SiN layer40formed over the MTJ stacks18and the side portions43of the SiN layer40exposed adjacent the distal end of the spacers44. Thus, the spacers44are now flush with the MTJ stacks18. This results in L-shaped spacers46defined between each of the MTJ stacks18and the spacers44. In particular, an L-shaped spacer46is formed on the right side of the MTJ stacks18and a backwards L-shaped spacer46is formed on the left side of the MTJ stacks18.

FIG. 12is a cross-sectional view of the semiconductor device ofFIG. 11where a third etch is performed, the etch forming an electrode between each MRAM region and MTJ stack, in accordance with an embodiment of the present invention.

In various embodiments, an etch is performed to selectively remove portions of the TaN layer16such that electrodes50are formed between the MTJ stacks18and the MRAM regions14. The electrode50has a top surface52and a bottom surface54. The top surface52engages the MTJ stack18and the bottom surface54engages the top surface15of the MRAM region14. The bottom surface54of the electrode50extends beyond a top surface15of the MRAM region14. Thus, the length of the electrode50is greater than the length of the MRAM region14. Stated differently, the MRAM regions14(or metal islands) are fully encapsulated by the TaN electrodes50. The electrodes50fully block or cover the MRAM regions14such that the top surface15of the MRAM regions14is not exposed.

In contrast toFIG. 6, L-shaped SiN spacers46are formed between the spacers44and the MTJ stacks18. Thus, a bottom surface47of the L-shaped spacers46extends beyond the top surface15of the MRAM regions14and further extends beyond the bottom surface54of the electrodes50.

FIG. 13is a cross-sectional view of the semiconductor device ofFIG. 12where the LTO layer is removed, in accordance with an embodiment of the present invention.

In various embodiments, a third etch can take place where the LTO spacers44are removed. It is noted that LTO removal is optional in the exemplary embodiments of the present invention.

FIG. 14is a cross-sectional view of the semiconductor device ofFIG. 13where dielectric deposition, planarization, and damascene processing is performed, in accordance with an embodiment of the present invention.

In various embodiments, an inter-layer dielectric (ILD) fill takes place. The ILD60is planarized. The ILD60encompasses or envelopes or surrounds the MTJ stacks18. The ILD60engages an outer surface of the sidewall L-shaped spacers46. In one example embodiment, the ILD60extends over a top point of the spacers46. Stated differently, the ILD60covers or encompasses or engulfs the spacers46, as well as the exposed portions of the electrodes50.

In one or more embodiments, the ILD60can have a thickness in the range of about 20 nm to about 150 nm, or in the range of about 30 nm to about 50 nm.

In various embodiments, the height of the ILD60can be selectively reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

Subsequently, in various embodiments, damascene processing is performed where a via62is filled with a conducting material (e.g., a metal) and a trench64is filled with a conducting material (e.g., a metal). The via62extends up to the BLOk12. The trench64extends over the MTJ stacks18such that the top surface19of each of the MTJ stacks18is exposed. The via62can be separated from the trench64by the ILD60.

FIG. 15is a cross-sectional view of the semiconductor device ofFIG. 13where a dielectric barrier is deposited, in accordance with another embodiment of the present invention.

In various embodiments, an alternative flow can result in forming L-shaped spacers with an additional barrier cap, as described with respect toFIGS. 15-16. A semiconductor structure9includes a semiconductor substrate10. Magnetic random access memory (MRAM) regions14are formed within the semiconductor substrate10. A low-k barrier12(BLOk) is deposited over the top portion of an MRAM region14. A TaN layer is deposited over the low-k barrier12and the remaining MRAM regions14. MTJ stacks18are formed directly over the MRAM regions14. The TaN layer is laterally etched to form electrodes50between the MTJ stacks18and the MRAM regions14. L-shaped spacers46are formed adjacent the MTJ stacks18, as described above.

A barrier cap70is further deposited over the MTJ stacks18, as well as the rest of the structure9. A top portion73of the barrier cap70is defined over the MTJ stacks18, whereas side portions71of the barrier cap are defined over the low-k barrier12and between the MTJ stacks18.

FIG. 16is a cross-sectional view of the semiconductor device ofFIG. 15where dielectric deposition, planarization, and damascene processing is performed, in accordance with another embodiment of the present invention.

In various embodiments, an inter-layer dielectric (ILD) fill takes place. The ILD80is planarized. The ILD80encompasses or envelopes or surrounds the MTJ stacks18. The ILD80engages an outer surface of the sidewall L-shaped spacers46. In one example embodiment, the ILD80extends over a top point of the spacers46. Stated differently, the ILD80covers or encompasses or engulfs the spacers46, as well as the exposed portions of the electrodes24.

In one or more embodiments, the ILD80can have a thickness in the range of about 20 nm to about 150 nm, or in the range of about 30 nm to about 50 nm.

In various embodiments, the height of the ILD80can be selectively reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

Subsequently, in various embodiments, damascene processing is performed where a via82is filled with a conducting material (e.g., a metal) and a trench84is filled with a conducting material (e.g., a metal). The via82extends up to the BLOk12. The trench84extends over the MTJ stacks18such that the top surface/portion73of the barrier cap70contacts the trench84. The via82can be separated from the trench84by the ILD80.

FIG. 17is a cross-sectional view of the semiconductor device ofFIG. 6where airgaps or recesses are created within the dielectric, in accordance with another embodiment of the present invention.

In various embodiments, an alternative flow can result in forming spacers to reduce capacitive coupling, as described with respect toFIGS. 17-19. A semiconductor structure11includes a semiconductor substrate10. Magnetic random access memory (MRAM) regions14are formed within the semiconductor substrate10. A low-k barrier12(BLOk) is deposited over the top portion of an MRAM region14. A TaN layer is deposited over the low-k barrier12and the remaining MRAM regions14. MTJ stacks18are formed directly over the MRAM regions14. The TaN layer is laterally etched to form electrodes24between the MTJ stacks18and the MRAM regions14. Spacers22are formed adjacent the MTJ stacks18, as described above.

A first recess or cavity90is formed between the MRAM region positioned directly under the low-k barrier12and the MTJ stack18, whereas a second recess or cavity92is formed between the MTJ stacks18. The first and second recesses or cavities90,92extend beyond a depth of the MRAM regions14. The first and second recesses or cavities90,92can be equal to each other. In another example embodiment, the first and second recesses or cavities90,92are not equal to each other. For example, recess90can be bigger or wider than recess92, as shown for illustrative purposes.

FIG. 18is a cross-sectional view of the semiconductor device ofFIG. 17where dielectric deposition with pinch-off takes place, in accordance with an embodiment of the present invention.

In various embodiments, an inter-layer dielectric (ILD) fill takes place. The ILD96is planarized. The ILD96encompasses or envelopes or surrounds the MTJ stacks18. The ILD96engages a portion of an outer surface of the sidewall spacers22. In one example embodiment, the recesses90,92aid in the creation of airgaps94. The airgaps94are formed such that the sidewalls of the electrodes24are exposed. The airgaps94extend a length of the spacers22, the length being less than the total length of the sidewall of the spacer22.

In one or more embodiments, the ILD96can have a thickness in the range of about 20 nm to about 150 nm, or in the range of about 30 nm to about 50 nm.

In various embodiments, the height of the ILD96can be selectively reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing.

FIG. 19is a cross-sectional view of the semiconductor device ofFIG. 18where damascene processing is performed, in accordance with an embodiment of the present invention.

In various embodiments, damascene processing is performed where a via97is filled with a conducting material (e.g., a metal) and a trench99is filled with a conducting material (e.g., a metal). The via97extends up to the BLOk12. The trench99extends over the MTJ stacks18such that the top surface19of each of the MTJ stacks18is exposed. The via97can be separated from the trench99by the ILD96. The sidewalls of the electrodes24are also exposed after damascene processing is performed due to the formation of the airgaps94.

FIG. 20is a block/flow diagram of an exemplary method for forming a semiconductor device, in accordance with an embodiment of the present invention.

At block100, a barrier layer, such as a tantalum nitride (TaN) layer, is deposited over a dielectric incorporating magnetic random access memory (MRAM) regions.

At block102, magnetic tunnel junction (MTJ) stacks are formed over portions of the TaN layer.

At block104, the MTJ stacks are patterned and encapsulated.

At block106, spacers are formed adjacent the MTJ stacks.

At block108, sections of the TaN layer are laterally etched, after spacer formation, to form an electrode under the MTJ stacks.

The integrated magnetic tunnel junctions (MTJs) of the exemplary embodiments of the present disclosure are formed in back end of line (BEOL) interconnects. Concerning BEOL, a layer of dielectric material is blanket deposited atop the entire substrate and planarized. The blanket dielectric can be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds; the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge; carbon-doped oxides; inorganic oxides; inorganic polymers; hybrid polymers; organic polymers such as polyamides or SiLK™; other carbon-containing materials; organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials; and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, a-C:H). Additional choices for the blanket dielectric include: any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.

The blanket dielectric can be formed by various methods well known to those skilled in the art, including, but not limited to: spinning from solution, spraying from solution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputter deposition, reactive sputter deposition, ion-beam deposition, and evaporation.

The deposited dielectric is then patterned and etched to forth via holes to the various source/drain and gate conductor regions of the substrate. Following via formation interconnects are formed by depositing a conductive metal into the via holes using conventional processing, such as CVD or plating. The conductive metal can include, but is not limited to: tungsten, copper, aluminum, silver, gold, and alloys thereof. The BEOL layer can comprise one or multiple stacks of wires/vias.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention.