Memory devices and methods of manufacturing the same

A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2013-0019786, filed on Feb. 25, 2013 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

In methods of manufacturing vertical memory devices, an insulation layer and a sacrificial layer may be alternately and repeatedly formed on a substrate. Holes may be formed through the insulation layers and the sacrificial layers. Channels may be formed to fill the holes. Openings may be formed through the insulation layers and the sacrificial layers. The sacrificial layers exposed by the openings may be removed to form gaps exposing the channels. ONO layers and gate structures including gate electrodes may be formed to fill the gaps.

The holes may have a high aspect ratio and may be arranged at a small distance, relatively. Problems of forming the holes unevenly or deforming the formed holes may occur.

SUMMARY

Some embodiments provide vertical memory devices having a good reliability.

Some embodiments provide methods of manufacturing the vertical memory device having a good reliability.

According to some embodiments, there is provided a vertical memory device. The vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is disposed on a first region of a substrate and extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes are arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is disposed on a second region that is adjacent the first region of the substrate and that extends in the first direction.

In some embodiments, the dummy patterns may include silicon oxide, silicon nitride or polysilicon.

In some embodiments, the dummy patterns may have a circular shape, an elliptical shape or a polygonal shape.

In some embodiments, the dummy patterns may have a line shape which extends in a third direction that is substantially perpendicular to the first and second directions.

In some embodiments, the dummy patterns may have a smaller width than that of the channels.

In some embodiments, the dummy pattern array may include a first dummy pattern column including multiple first dummy patterns formed in a third direction that is substantially perpendicular to the first and second directions and a second dummy pattern column including multiple second dummy patterns formed in the third direction and spaced apart from the first dummy pattern column.

In some embodiments, each dummy pattern may have a top surface that is substantially coplanar with that of each channel.

According to some embodiments, there are provided methods of manufacturing a vertical memory device. In such methods, a sacrificial layer and an insulation layer are formed on a substrate alternately and repeatedly. The substrate has a first region and a second region. Holes and first dummy holes are formed through the sacrificial layers and the insulation layers to expose a top surface of the substrate in the first region and the second region, respectively. Multiple first dummy patterns are formed to fill the first dummy holes. A blocking layer pattern, a charge storage layer pattern, a tunnel insulation layer pattern and a channel are sequentially formed on a sidewall of each hole. Multiple gaps are formed by removing the sacrificial layers to expose a sidewall of each blocking layer pattern. A gate electrode is formed to fill each gap.

In some embodiments, the first dummy patterns may have a circular, elliptical, polygonal shape or a line shape which extends in third direction that is substantially parallel to the top surface of the substrate.

In some embodiments, the first dummy patterns may include silicon oxide, silicon nitride or polysilicon.

In some embodiments, the substrate may further include a third region that is adjacent the first region. When the holes and the first dummy holes are formed, second dummy holes may further be formed in the third region of the substrate. When the first dummy pattern is formed, a second dummy pattern may be further formed to fill each second dummy hole.

In some embodiments, prior to forming the gaps by removing the sacrificial layers, portions of the insulation layers and the sacrificial layers in the third region of the substrate may be further removed. The entire second dummy patterns may be further removed.

In some embodiments, each first dummy hole may have a smaller width than that of each hole.

In some embodiments, multiple first dummy patterns may be formed in a third direction that is substantially parallel to the top surface of the substrate to define a dummy pattern column.

In some embodiments, when the holes and the first dummy holes are formed, a first hole column including multiple first holes may be formed, each of which extends in a first direction that is substantially perpendicular to the top surface of the substrate and is formed in a central portion of the first region of the substrate in a third direction that is substantially parallel to the top surface of the substrate. A second hole column spaced apart from the first hole column in a second direction that is substantially perpendicular to the third direction and that includes multiple second holes may be formed, each of which is formed in an edge portion of the first region of the substrate in the third direction. A third hole column arranged between the first and the second hole columns and including multiple third holes may be formed, each of which is formed in a fourth direction that may be an oblique angle to the second from the first holes.

According to some embodiments, the vertical memory device includes channels and gate structures at a first region I of a substrate, and a dummy pattern at a second region II of the substrate. When holes for the channels are formed, dummy holes corresponding to the holes are formed, simultaneously. The dummy holes and/or the holes may be etched evenly.

Some embodiments include a vertical memory device that includes multiple channels disposed in a first region of a substrate and extending in a first direction that is substantially perpendicular to a top surface of the substrate. A charge storage layer structure may be formed on a sidewall of ones of the channels in a second direction that is substantially parallel to the top surface of the substrate and that is different from the first direction. Multiple gate electrodes may be arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction and multiple dummy patterns, one of which are disposed in a second region that is adjacent the first region of the substrate and that extend in the first direction.

In some embodiments, ones of the dummy patterns include silicon oxide, silicon nitride and/or polysilicon. Some embodiments provide that ones of the dummy patterns have a line shape which extends in a third direction that is substantially perpendicular to the first and second directions. In some embodiments, ones of the dummy patterns have a smaller width than a width of ones of the channels. Some embodiments provide that the first dummy patterns include a first dummy pattern column including multiple first dummy patterns formed in a third direction that is substantially perpendicular to the first and second directions and a second dummy pattern column including multiple second dummy patterns formed in the third direction and spaced apart from the first dummy pattern column. In some embodiments, ones of the dummy patterns have a top surface that is substantially coplanar with a top surface of ones of the plurality of channels.

It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.

FIG. 1is a perspective view illustrating a vertical memory device in accordance with some embodiments.FIG. 2is a vertical cross-sectional view cut along the line VI-VI′ inFIG. 1.FIG. 3is a local perspective view of a region V of the vertical memory device inFIG. 2.

For the convenience of the explanation,FIG. 1does not show all elements of the vertical memory device, but only shows some elements thereof, e.g., a substrate, a semiconductor pattern, a channel, a gate electrode, a pad, a bit line contact and a bit line. In the figures in this specification, a direction substantially perpendicular to a top surface of the substrate is referred to as a first direction, and two directions substantially parallel to the top surface of the substrate and substantially perpendicular to each other are referred to as a second direction and a third direction. Additionally, a direction indicated by an arrow in the figures and a reverse direction thereto are considered as the same direction.

Referring toFIGS. 1 to 3, the vertical memory device may include a plurality of channels160each of which may extend in the first direction on a substrate100, a first tunnel insulation layer pattern157, a charge storage layer pattern155and a blocking layer pattern153sequentially stacked on an outer sidewall of each channel160. The vertical memory device may further include an auxiliary blocking layer pattern205that may be sequentially stacked on and may surround a portion of the outer sidewall of each channel160.

Additionally, the vertical memory device may include a plurality of gate electrodes216,217and218that may be formed on an outer sidewall of the auxiliary blocking layer pattern205and partially cover outer sidewalls of some channels160. The vertical memory device may further include an impurity region105serving as a common source line (CSL)105and a bit line240.

The substrate100may include a semiconductor material, e.g., silicon, germanium, etc. The substrate100may include a first region I, a second region II and a third region III. In some embodiments, vertical memory elements including the channels160may be formed in the first region I. A plurality of first regions I may be formed in the second direction, and each of the first regions I may extend in the third direction. The third region III may be arranged between the first regions I. In some embodiments, the third region III may be a word line cut region to separate the vertical memory elements. The second region II may be arranged adjacent the first region I.

Each channel160may extend in the first direction in the first region I. In some embodiments, each channel160may have a pillar shape. In some embodiments, each channel160may have a cup shape of which a central bottom is opened. In this case, a space defined by an inner wall of each channel160may be filled with an insulation pattern (not shown). In some embodiments, each channel160may include doped and/or undoped polysilicon and/or single crystalline silicon.

In some embodiments, the plurality of channels160may be arranged in both of the second and third directions, and thus a channel array may be defined.

In some embodiments, the channel array may have a first channel column including a plurality of first channels160aarranged in the third direction, a second channel column including a plurality of second channels160barranged in the third direction and a third channel column including a plurality of third channels160carranged between the first and second channels160aand160b. The first channels160amay be arranged at a central portion of the first region I in the third direction. The second channels160bmay be arranged at outer portions of the first region I in the third direction. The third channels160cmay be positioned in a fourth direction, which may be an oblique angle to the second direction or the third direction, from the first or the second channels160aor160b. Accordingly, the first, second and third channels160a,160band160cmay be arranged in a zigzag pattern (that is, a staggered pattern) with respect to the third direction, and thus more channels may be arranged in a given area.

The first to third channel columns may define a channel set, and a plurality of the channel sets may be repeatedly arranged in the second direction to form the channel array. In some embodiments, one channel set may be arranged to correspond one first region I.

Referring toFIG. 3, each of the tunnel insulation layer patterns157, the charge storage layer patterns155and the blocking layer patterns153, that may be sequentially stacked on and may surround the outer sidewalls of each channel160, may have a cup shape of which a central bottom may be opened in accordance with the shape of each of the channels160. Particularly, the tunnel insulation layer pattern157, the charge storage layer pattern155and the blocking layer pattern153may surround an outer sidewall and a bottom of each channel160. Accordingly, the tunnel insulation layer pattern157, the charge storage layer pattern155and the blocking layer pattern153may define a charge storage layer structure151. In some embodiments, a plurality of charge storage layer structures151may be formed, each of which is corresponded to each channel160.

In some embodiments, the tunnel insulation layer pattern157may include an oxide, e.g., silicon oxide, the charge storage layer pattern155may include a nitride, e.g., silicon nitride, and the blocking layer pattern153may include an oxide, e.g., silicon oxide.

A semiconductor pattern147making contact with the top surface of the substrate100may be formed beneath each channel160. Accordingly, as the channel160may have a portion at a bottom thereof protruding from the charge storage layer structure151, the semiconductor pattern147may have a concave portion at a top surface thereof. The semiconductor pattern147may directly contact the channel160through the protrusion portion thereof. In some embodiments, the semiconductor pattern147may include doped and/or undoped polysilicon, single crystalline polysilicon, doped and/or undoped polygermanium and/or single crystalline germanium.

Additionally, a pad170may be formed on top surfaces of the channel160and the charge storage layer structure151. In some embodiments, the pad170may include doped and/or undoped polysilicon and/or single crystalline silicon.

A plurality of first insulation patterns115may be formed in the first direction on sidewalls of the blocking layer patterns153, respectively. For example, each first insulation pattern115may include silicon oxide.

A first opening180may be formed between the channel sets in the third region III, and a space between the first insulation layers115at each level may be defined as a gap190.

The auxiliary blocking layer pattern205may surround a sidewall of the blocking layer pattern153exposed by the gap190, that is, may surround an outer sidewall of the channel160. Thus, portions of the outer sidewalls of the channels160may be surrounded by the auxiliary blocking layer pattern205. The auxiliary blocking layer pattern205may be further formed on an inner wall of the gap190. Top and bottom end portions of the auxiliary blocking layer pattern205may extend in both of the second and third directions. The auxiliary blocking layer pattern205may include, e.g., aluminum oxide and/or silicon oxide.

The plurality of gate electrodes216,217and218may be formed on a sidewall of the auxiliary blocking layer pattern205and may fill an inner portion of the gap190. In some embodiments, the plurality of gate electrodes216,217and218may extend in the third direction.

The plurality of gate electrodes216,217and218may include a ground selection line (GSL)218, a word line216and a string selection line (SSL)217that are spaced apart from each other along the first direction.

Each of the GSL218, the word line216and the SSL217may be at a single level (e.g., one of each, each at a different height) or more than one level, and each of the first insulation layer patterns115may be interposed therebetween. In some embodiments, the GSL218and the SSL217may be at one level (e.g., two of each at different heights), respectively, and the word line216may be at 4 levels between the GSL218and the SSL217. However, the GSL218and the SSL217may be at two levels, and the word line216may be formed at 2, 8 or 16 levels.

In some embodiments, the plurality of gate electrodes216,217and218may include, for example, a metal and/or a metal nitride. For example, the plurality of gate electrodes216,217and218may include a metal and/or a metal nitride with low electrical resistance (e.g., tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride and/or platinum.)

Accordingly, the charge storage layer structure151and the plurality of gate electrodes216,217and218may define a gate structure. A plurality of gate structures may be formed in the first direction.

The gate structures may be divided by a division layer pattern165extending in the third direction and penetrating a portion of the first insulation layer patterns115. The division layer pattern165may be arranged to overlap the first channel column. The channels160may be divided by the division layer pattern165in the third direction.

Particularly, the division layer pattern165may penetrate the SSL217and the first insulation layer patterns115thereon, and may further penetrate a portion of the first insulation layer pattern115therebeneath. Thus, the SSL217may be electrically insulated from each other by the division layer pattern165. The division layer pattern165may include an oxide, e.g., silicon oxide.

The first opening180between the first regions I of the substrate100may be filled with a second insulation layer pattern220. The second insulation layer pattern220may include an oxide, e.g., silicon oxide.

The impurity region105serving as a common source line (CSL) and extending in the third direction may be formed at an upper portion of the substrate100beneath the second insulation layer pattern220. In some embodiments, the impurity region105may include n-type impurities, e.g., phosphorus, arsenic, and the like. For example, a cobalt silicide pattern (not shown) or nickel silicide pattern (not shown) may be further formed on the impurity region105.

Referring now toFIGS. 1 and 2, a first dummy pattern145aand a second dummy pattern145bmay be arranged in the second region II adjacent to the first region I. Each of the first and second dummy patterns145aand145bmay extend in the first direction. For example, the first and second dummy patterns145aand145bmay have a pillar shape, and may have a top surface substantially coplanar with the top surface of the channel160. The first and second dummy patterns145aand145bmay have a smaller width than that of the channels160.

In some embodiments, a plurality of first dummy patterns145aand a plurality of second dummy patterns145bmay be formed in the second and third directions, respectively. Accordingly a dummy pattern array may be defined.

In some embodiments, the dummy pattern array may have a first dummy pattern column including the plurality of first dummy patterns145aarranged in the third direction and a second dummy pattern including the plurality of second dummy patterns145barranged in the third direction. The second dummy patterns145bmay be positioned in the fourth direction, which may be an oblique angle to the second or third direction, from the first dummy patterns145a. Accordingly, the first and second dummy patterns145aand145bmay be arranged in a zigzag pattern (a staggered pattern) with respect to the third direction.

For example, the first and second dummy patterns145aand145bmay include silicon oxide, silicon nitride or polysilicon.

The bit line240may be electrically connected to the pad170via a bit line contact235, and thus may be electrically connected to the channels160. The bit line240may include a metal, a metal nitride, doped polysilicon, and the like. In some embodiments, the bit line240may extend in the second direction, and a plurality of bit lines240may be formed in the third direction.

The bit line contact235may fill a second opening232through a third insulation layer230, and make contact with a top surface of the pad170. The bit line contact235may include a metal, a metal nitride, doped polysilicon, and the like.

The third insulation layer230may be formed on the first and second insulation layer patterns115and220, the pad170and the division layer pattern165. In some embodiments, the third insulation layer230may include an insulating material, e.g., oxide.

As illustrated above, the vertical memory device may have the channels160and the gate structures in the first region I of the substrate100, and the dummy patterns145aand145bin the second region II of the substrate100. When holes130(SeeFIG. 5A) for the channels160are formed, dummy holes140aand140b(SeeFIG. 5A) in accordance with the dummy patterns145aand145bmay be formed, simultaneously. The dummy holes140aand140bmay be formed to form and arrange the holes130uniformly. Accordingly, the vertical memory device may have a good reliability.

FIGS. 4A to 12Aare vertical cross-sectional views illustrating methods of manufacturing vertical memory devices in accordance with some embodiments,FIGS. 5B, 7B, 8B, 9B and 12Bare plan views illustrating methods of manufacturing the vertical memory devices, andFIG. 6Bis a local perspective view illustrating methods of manufacturing the vertical memory devices. The vertical cross-sectional views are cross-sectional views cut along the line VI-VI′ of the plan views. The figures show methods of manufacturing the vertical memory devices ofFIGS. 1 to 3, however, may not be limited thereto.

Referring toFIG. 4A, a first insulation layer110and a sacrificial layer120may be alternately and repeatedly formed on a substrate100. A plurality of first insulation layers110and a plurality of sacrificial layers120may be alternately formed on each other at a plurality of levels, respectively.

The substrate100may include a semiconductor material, for example, silicon and/or germanium. The substrate100may be divided into a first region I, a second region II and a third region III in accordance with positions. In some embodiments, a vertical memory element including channels160inFIG. 7Amay be in the first region I. A plurality of first regions I may be formed in the second direction, each of which may extend in the third direction. The third region III may be arranged between the first regions I, and may be a word line cut region to separate the vertical memory elements. The second region II may be arranged adjacent a surface of the first region I.

In some embodiments, the first insulation layer110and the sacrificial layer120may be formed by, for example, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process and/or an atomic layer deposition process (ALD) process. A lowermost first insulation layer110, which may be formed directly on a top surface of the substrate100, may be formed by, for example, a thermal oxidation process. In some embodiments, the first insulation layer110may be formed to include a silicon oxide. The sacrificial layers120may be formed to include, for example, a material with etch selectivity to the first insulation layer110(e.g., silicon nitride).

The number of the first insulation layers110and the number of the sacrificial layers120stacked on the substrate100may vary according to the desired number of a GSL218, a word line216and a SSL217(refer toFIG. 11A). According to some embodiments, each of the GSL218and the SSL217may be formed at a single level, and the word line216may be formed at 4 levels. The sacrificial layer120may be formed at 6 levels, and the first insulation layer110may be formed at 7 levels. According to some embodiments, each of the GSL218and the SSL217may be formed at two levels, and the word line216may be formed at 2, 8 or 16 levels. The number of the first insulation layers110and the number of the sacrificial layers120may vary according to this case. However, the number of GSLs218, SSLs217and word lines216may not be limited herein.

Referring toFIGS. 5A and 5B, a plurality of holes130and a plurality of dummy holes135and140may be formed through the first insulation layers110and the sacrificial layers120to expose a top surface of the substrate100.

In some embodiments, after forming a hard mask127on the uppermost first insulation layer110, the first insulation layers110and the sacrificial layers120may be dry etched using the hard mask127as an etch mask to form the holes130and the dummy holes135and140. The holes130and the dummy holes135and140may extend in the first direction. Due to the characteristics of a dry etch process, the holes130and the dummy holes135and140may be of a width that becomes gradually smaller from a top portion to a bottom portion thereof.

In some embodiments, the hard mask127may be formed to include a material with etch selectivity to silicon oxide and silicon nitride that may be included in the first insulation layers110and the sacrificial layers120, respectively, e.g., polysilicon or amorphous silicon by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, and the like.

In some embodiments, a plurality of holes130a,130band130cmay be arranged in the second and third directions in the first region I. A plurality of first and second dummy holes140aand140bmay be arranged in the third direction in the second II, and a plurality of third and fourth dummy holes135aand135bmay be arranged in the third direction in the third region III.

The holes130a,130band130cformed in the first region I may define a hole array. In some embodiments, the hole array may have a first hole column including the plurality of first holes130aarranged in the third direction, a second hole column including the plurality of second holes130barranged in the third direction and a third hole column including the plurality of third holes130carranged between the first and second holes130aand130b. The first holes130amay be arranged at a central portion of the first region I in the third direction. The second holes130bmay be arranged at outer portions of the first region I in the third direction. The third holes130cmay be positioned in a fourth direction, which may be an oblique angle to the second direction or the third direction, from the first or the second holes130aor130b. Accordingly, the first, second and third holes130a,130band130cmay be arranged in a zigzag pattern with respect to the third direction, and thus more holes130may be arranged in a given area.

The first and second dummy holes140aand140bmay be formed in the second region II. In some embodiments, the plurality of the first and second dummy holes140aand140bmay be arranged in the second and third directions. Accordingly, a first dummy hole array may be defined.

In some embodiments, the first dummy hole array may have a first dummy hole column including the plurality of first holes140aarranged in the third direction and a second dummy hole column including the plurality of second holes130barranged in the third direction. The second dummy holes140bmay be positioned in the fourth direction, which may be an oblique angle to the second direction or the third direction, from the first dummy holes140a. Accordingly, the first and second dummy holes140aand140bmay be arranged in a zigzag pattern with respect to the third direction.

In some embodiments, the first and second dummy holes140aand140bmay have a diameter substantially the same as or smaller than that of the holes130.

The plurality of third and fourth dummy holes135aand135bmay be formed in the third region III. In some embodiments, the plurality of third and fourth dummy holes135aand135bmay be arranged in the second and third directions. Accordingly, the third and fourth dummy holes135aand135bmay be arranged in a zigzag pattern.

When the holes130are formed, the first to fourth dummy holes140a,140b,135aand135bmay be formed, simultaneously. The first to fourth dummy holes140a,140b,135aand135bmay be formed in the second and third regions II and III, where the holes130are not formed. In an etching process for forming the holes130, it may be etched unevenly depending on existence of other holes adjacent the holes130.

If the first to fourth dummy holes140a,140b,135aand135bare not formed, the first holes130amay be surrounded by the third holes130cin both directions. While, the second holes130bmay be surrounded by the third holes130cin a single direction. By these differences, the first and second holes130aand130bmay have different sizes and shapes after the etching process.

In some embodiments, one sidewall of the second holes130bmay be surrounded by the third holes130cand the other sidewall of the second holes130bmay be surrounded by the dummy holes140a,140b,135aor135b. Accordingly the first and second holes130aand130bmay be formed uniformly.

Additionally, the volumes of the first insulation layers110and the sacrificial layers120may be reduced after the etching process, so that a mis-alignment by a deformation of the first insulation layers110and the sacrificial layers120may be reduced or prevented.

Referring toFIGS. 6A and 6B, after dummy patterns145a,145b,134aand134bare formed to fill the dummy holes140a,140b,135aand135brespectively, a semiconductor pattern147may be formed to partially fill each hole130. Charge storage layers150may be formed on an inner wall of each hole130, a top surface of the semiconductor pattern147, and a top surface of the hard mask127.

First, a dummy pattern layer may be formed on the hard mask127to sufficiently fill the dummy holes140a,140b,135aand135b, and the dummy pattern layer may be planarized until a top surface of the hard mask127is exposed to form the first to fourth dummy patterns145a,146b,134aand134b. In some embodiments, the dummy pattern layer may include silicon oxide, silicon nitride and/or polysilicon. When the first to fourth dummy patterns145a,145b,134aand134binclude polysilicon, the first to the fourth dummy patterns145a,145b,134aand134bmay have an etch selectivity with respect to the first insulation layer110including silicon oxide and the sacrificial layer120including silicon nitride. The first to fourth dummy patterns145a,145b,134aand134bmay be removed selectively in a process for removing the sacrificial layers120(refer toFIG. 10) or in a process for etching the first insulation layer110(refer toFIG. 9A).

The dummy patterns145a,145b,134aand134bin accordance with some embodiments may reduce or prevent the first insulation layers110or the sacrificial layers120from being deformed in subsequent processes.

In some embodiments, the dummy patterns145a,145b,134aand134bmay have a plan shape in accordance with that of the dummy holes140a,140b,135aand135b. As illustrated inFIG. 7B, the plan shape of the dummy patterns145a,145b,134aand134bmay be substantially a circular shape or an elliptical shape. In some embodiments, as illustrated inFIG. 15, when the dummy holes have a polygonal shape extending in the third direction, the dummy patterns may have a polygonal shape extending in the third direction in accordance with these. In some embodiments, as illustrated inFIGS. 13 and 14, when the dummy holes have a line shape extending I the third direction, the dummy patterns may have a line shape extending in the third direction in accordance with these.

Particularly, a selective epitaxial growth (SEG) process may be performed using the exposed top surface of the substrate100as a seed to form the semiconductor pattern147. Thus, the semiconductor pattern147may be formed to include single crystalline silicon or single crystalline germanium according to the material of the substrate100, and in some cases, impurities may be doped thereinto. In some embodiments, an amorphous silicon layer may be formed to fill the holes130, and a laser epitaxial growth (LEG) process and/or a solid phase epitaxial (SPE) process may be performed on the amorphous silicon layer to form the semiconductor pattern147. In some embodiments, the semiconductor pattern147may be formed to have a top surface higher than that of the sacrificial layer120, in which the GSL218(SeeFIG. 11) may be formed subsequently.

Referring toFIG. 6B, a blocking layer152, a charge storage layer154and a tunnel insulation layer156may be sequentially formed on an inner wall of the holes130, a top surface of the semiconductor pattern147, and a top surface of the hard mask127. That is, the charge storage layers150may include the blocking layer152, the charge storage layer154and the tunnel insulation layer156. In some embodiments, the blocking layer152may be formed to include an oxide, e.g., silicon oxide, the charge storage layer154may be formed to include a nitride, e.g., silicon nitride, and the tunnel insulation layer156may be formed to include an oxide, e.g., silicon oxide.

After forming the tunnel insulation layer156, an auxiliary channel layer (not shown) may be formed on the tunnel insulation layer156. The auxiliary channel layer may be formed to include doped and/or undoped polysilicon and/or amorphous silicon. The auxiliary channel layer may prevent the tunnel insulation layer176from being damaged during the partial removal of the charge storage layer154, etc. in a subsequent process (refer toFIG. 7A).

Referring toFIGS. 7A and 7B, a bottom surface of the charge storage layer150and an upper portion of the semiconductor pattern147may be partially removed to form a first recess158. Each channel160may be formed to sufficiently fill the first recess158and a remaining portion of each hole130.

In some embodiments, a central bottom surface of the charge storage layers150(including the tunnel insulation layer156, the charge storage layer154and the blocking layer152) may be removed to partially expose the upper portion of the semiconductor pattern147, and the exposed upper portion of the semiconductor portion147may be removed to form the first recess158.

A channel layer may be formed on the charge storage layers150and the exposed semiconductor pattern147to sufficiently fill remaining portions of the holes130. The channel layer, the charge storage layers150and hard mask127may be planarized until a top surface of the uppermost first insulation layer110may be exposed. Some embodiments provide that the channel layer may be formed on the charge storage layers150and the exposed semiconductor pattern147. An insulation layer (not shown) may be formed to sufficiently fill the remaining portions of the holes130.

Thus, the channel160and a charge storage layer structure151including a blocking layer pattern153, a charge storage layer pattern155and a tunnel insulation layer pattern157(refer toFIG. 3) may be formed to fill each hole130.

In some embodiments, the blocking layer pattern153, the charge storage layer pattern155and the tunnel insulation layer pattern157may be formed to have a cup shape of which a central bottom is opened, and may be electrically connected to the semiconductor pattern147and the channel160via the central bottom surface of the charge storage layers150(the tunnel insulation layer156, the charge storage layer154and the blocking layer152, refer toFIG. 3).

In some embodiments, the channel layer may be formed to include doped and/or undoped polysilicon and/or amorphous silicon. When the channel layer is formed to include amorphous silicon, a crystallization process may be further performed.

The holes130for receiving the channels160may define a hole set including the first to third holes130a,130band130c, and further may define a hole array. The channels160in accordance with the holes130may define a channel set including first to third channels160a,160band160c, and further a channel array. The first to third channels160a,160band160cmay be formed in the first to third holes130a,130band130c, respectively.

Referring toFIGS. 8A and 8B, the channel160, the charge storage layer structure151, the first insulation layers110and the sacrificial layers120may be partially removed to form a trench162. A division layer pattern165may be formed to fill the trench162. Upper portions of the channel160and the charge storage layer structure151may be removed to form a second recess168. A pad170may be formed to fill the second recess168.

In some embodiments, the trench162may be formed to penetrate the sacrificial layers120where the SSL217(refer toFIG. 11A) are formed and the first insulation layers110thereon, and further to penetrate the first insulation layers110therebeneath in a lithography process. In some embodiments, the trench162may extend in the third direction and may be formed to overlap the first channel160a.

A division layer may be formed on the first insulation layer110to sufficiently fill the trench162. The division layer may be planarized to form the division layer pattern165filling the trench162until the top surface of the uppermost first insulation layer110is exposed. The division layer may have a material, e.g., silicon oxide, having an etching selectivity with respect to the sacrificial layers120. The planarization process may be performed by a chemical mechanical polishing (CMP) process and/or an etch back process.

Upper portions of the channel160, the charge storage layer structure151and the blocking layer pattern153may be removed by an etch back process to form the second recess168. A pad layer may be formed on the channel160, the charge storage layer structure151and the uppermost first insulation layer110to fill the second recess168, and the pad layer may be planarized until a top surface of the uppermost first insulation layer110is exposed to form the pad170. In some embodiments, the pad layer may be formed to include amorphous silicon. When the pad layer is formed to include amorphous silicon, a crystallization process may be further performed thereon.

The pad170may be formed on each of the channels160band160c, and thus may form a pad array in accordance with the channel array.

Referring toFIGS. 9A and 9B, a first opening180may be formed through the first insulation layers110and the sacrificial layers120to expose a top surface of the substrate100.

In some embodiments, after forming a hard mask (not shown) on the uppermost first insulation layer110, the insulation layers110and the sacrificial layers120may be, for example, dry etched using the hard mask as an etch mask to form the first opening180. The first opening180may extend in the first direction.

In some embodiments, a plurality of first openings180may be formed in the second direction, and each first opening180may extend in the third direction. Each first opening180may be formed in the third region III between the first regions I. Thus, the third and fourth dummy patterns134aand134bin the third region III may be removed during a process for forming the first opening180.

The first insulation layer110and the sacrificial layer120may be transformed into a first insulation layer pattern115and a sacrificial layer pattern125, respectively. A plurality of first insulation layer patterns115and a plurality of sacrificial layer patterns125may be formed in the second direction at each level, and each first insulation layer pattern115and each sacrificial layer pattern125may extend in the third direction.

Referring toFIG. 10, the sacrificial layer patterns125may be removed to form a gap190between the first insulation layer patterns115at adjacent levels. An auxiliary blocking layer200may be sequentially formed on the exposed portion of the outer sidewall of the blocking layer pattern152, the exposed portion of the sidewall of the semiconductor pattern147, an inner sidewall of the gap190, a surface of the first insulation pattern115, the exposed top surface of the substrate100, top surfaces of the pad170and the division layer pattern165. A gate electrode layer210may be formed on the auxiliary blocking layer200to sufficiently fill the remaining portions of the gap190.

In some embodiments, the sacrificial layer patterns125exposed by the first openings180may be removed by, for example, a wet etch process using an etch solution including phosphoric acid and/or sulfuric acid. During the wet etch process, the first and second dummy patterns145aand145bmay support the first insulation patterns115. Therefore, the first insulation patterns115and the channels160may not collapse.

In some embodiments, the auxiliary blocking layer200may be formed by a sequentially flow deposition (SFD) process and/or an atomic layer deposition ALD) process.

In some embodiments, the gate electrode layer210may be formed to include a metal. For example, the gate electrode210may be formed to include a metal of a low resistance, e.g., tungsten, titanium, tantalum, platinum, and the like. When the gate electrode layer210is formed to include tungsten, the gate electrode layer210may be formed by a CVD process or an ALD process using tungsten hexafluoride (WF6) as a source gas.

Referring toFIG. 11, the gate electrode layer210may be partially removed to form a plurality of gate electrodes216,217and218.

In some embodiments, the gate electrode layer210may be partially removed by, for example, a wet etch process. In some embodiments, the plurality of gate electrodes216,217and218may fill the gap190. The plurality of gate electrodes216,217and218may be formed to extend in the third direction.

The plurality of gate electrodes216,217and218may include a GSL218, the word line216and the SSL217sequentially located from a top surface of the substrate100. Each of the GSL218, the word line216and the SSL217may be formed at a single level or at a plurality of levels. According to some embodiments, each of the GSL218and the SSL217may be formed at single level, and the word line216may be formed at 4 levels between the GSL218and the SSL217. However, the number of GSLs218, word lines216and SSLs217may not be limited thereto. The GSL218may be formed adjacent the semiconductor pattern147, the word line216and the SSL217may be formed adjacent the channels160, and particularly, the SSL217may be formed adjacent the division layer pattern165.

When the gate electrode layer210is partially removed, portions of the auxiliary blocking layer pattern205on a surface of the first insulation layer pattern115and on top surfaces of the substrate100, the pad170and the division layer pattern165may also be removed to form an auxiliary blocking layer pattern205.

In a process for partially removing the gate electrode layer210, the auxiliary blocking layer200may be partially removed, the first opening180exposing a top surface of the substrate100and extending in the third direction may be formed again, and impurities may be implanted into the exposed top surface of the substrate100to form an impurity region105. In some embodiments, the impurities may include n-type impurities, for example, phosphorus and/or arsenic. In some embodiments, the impurity region105may extend in the third direction and serve as a common source line (CSL).

A metal silicide pattern (not shown), e.g., a cobalt silicide pattern or a nickel silicide pattern may be further formed on the impurity region105.

Referring toFIG. 12A, a second insulation pattern220may be formed to fill the first opening180. A bit line contact235may be formed to be electrically connected to a bit line240.

In some embodiments, after a third insulating interlayer filling the first opening180is formed on the substrate100and the uppermost the first insulation pattern115, the third insulating interlayer may be planarized until a top surface of the uppermost first insulation layer pattern115may be exposed to form the second insulation layer pattern220.

A third insulation layer230may be formed on the first and second insulation layer patterns115and220, the pad170and the division layer pattern165, and a second opening232may be formed to expose a top surface of the pad170. In some embodiments, a plurality of second openings232corresponding to the plurality of pads170may be formed to define a second opening array.

The bit line contact235may be formed on the pad170to fill the second opening232. The bit line240electrically connected to the bit line contact235may be formed to complete the vertical memory device.

In some embodiments, a plurality of bit line contacts235corresponding to the pads170may be formed to form a bit line contact array. A plurality of bit lines240may be arranged in the third direction, and each bit line240may be formed to extend in the second direction.

As mentioned above, when the holes130are formed, the dummy holes140a,140b,135aand135bmay be formed simultaneously. Also, the dummy patterns145a,145b,134aand134bmay also be formed to fill the dummy holes140a,140b,135aand135b, respectively. As the dummy holes140a,140b,135aand135band the holes130may be formed evenly. Thus, a mis-alignment by a deformation of the first insulation layers110and the sacrificial layers120may be reduced and/or prevented.

FIG. 13is a horizontal cross-sectional view illustrating methods of manufacturing vertical memory devices in accordance with some embodiments.

The methods of manufacturing the vertical memory devices may be substantially the same as or similar to that ofFIGS. 4 to 12, except for dummy openings136and141. Thus, like reference numerals refer to like elements, and repetitive explanations thereon may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIG. 4Amay be performed. A first insulation layer110and a sacrificial layer120may be alternately and repeatedly formed on a substrate100.

Referring toFIG. 13, dummy openings141and136may be formed in the second and third regions II and III of the substrate100, respectively. When the holes130are formed, the dummy openings141and136may be formed, simultaneously.

In some embodiments, when the dummy openings141and136are formed, the first dummy opening141may be formed to expose the second region II of the substrate100and the second dummy opening136may be formed to expose the third region III of the substrate100. For example, the dummy openings141and136may be formed to extend in the first direction.

In some embodiments, the first and second dummy openings141and136may have a line shape which extends in the third direction. The first and second dummy openings141and136may have a smaller width that that of holes130.

Processes substantially the same as or similar to those illustrated with reference toFIGS. 6 to 12may be performed to manufacture the vertical memory devices.

As mentioned above, when the holes130are formed, the dummy openings141and136may be formed simultaneously. Also, the dummy patterns may also be formed to fill the dummy openings141and136. The dummy patterns corresponding to the dummy openings141and136may have a line shape which extends in the third direction. The volumes of the first insulation layers110and the sacrificial layers120may be reduced to reduce or prevent mis-alignment by a deformation of the first insulation layers110and the sacrificial layers120. Thus, the holes130may be formed evenly and a mis-alignment may be reduced or prevented.

FIG. 14is a horizontal cross-sectional view illustrating method of manufacturing vertical memory devices in accordance with some embodiments.

The vertical memory device may be substantially the same as or similar to that ofFIGS. 4 to 12, except for dummy openings142a,142b,137aand137b. Thus like reference numerals refer to like elements, and repetitive explanations thereon may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIG. 4Amay be performed. A first insulation layer110and a sacrificial layer120may be alternately and repeatedly formed on a substrate100.

Referring toFIG. 14, dummy openings142a,142b,137aand137bmay be formed in the second and third regions II and III of the substrate100, respectively.

In some embodiments, when the dummy openings142a,142b,137aand137bare formed, first and second dummy openings142aand142bmay be formed to expose the second region II of the substrate100, and third and fourth dummy openings137aand137bmay be formed to expose the third region III of the substrate100. For example, the first to fourth dummy openings142a,142b,137aand137bmay be formed to extend in the first direction.

In some embodiments, the first to fourth dummy openings142a,142b,137aand137bmay have a line shape which extends in the third direction.

Processes substantially the same as or similar to those illustrated with reference toFIGS. 6 to 12may be performed to manufacture the vertical memory device.

As mentioned above, when the holes130are formed, the dummy openings142a,142b,137aand137bmay be formed simultaneously. Also, the dummy patterns may also be formed to fill the dummy openings142a,142b,137aand137b. The dummy patterns corresponding to the dummy openings142a,142b,137aand137bmay have a line shape which extends in the third direction. The volumes of the first insulation layers110and the sacrificial layers120may be reduced to reduce or prevent a mis-alignment by a deformation of the first insulation layers110and the sacrificial layers120. Thus, the holes130may be formed evenly and, a mis-alignment may be prevented or reduced.

FIG. 15is a horizontal cross-sectional view illustrating methods of manufacturing vertical memory devices in accordance with some embodiments.

The vertical memory devices may be substantially the same as or similar to that ofFIGS. 4 to 12, except for dummy holes143a,143b,138aand138b. Thus like reference numerals refer to like elements, and repetitive explanations thereon may be omitted herein.

First, processes substantially the same as or similar to those illustrated with reference toFIG. 4may be performed. A first insulation layer110and a sacrificial layer120may be alternately and repeatedly formed on a substrate100.

Referring toFIG. 15, dummy holes143a,143b,138aand138bmay be formed in the second and third regions II and III of the substrate100, respectively.

In some embodiments, when the dummy holes143a,143b,138aand138bare formed, first and second dummy holes143aand143bmay be formed to expose the second region II of the substrate100, and third and fourth dummy holes138aand138bmay be formed to expose the third region III of the substrate100. In some embodiments, a plurality of the dummy holes143a,143b,138aand138bmay be formed in the second and the third directions. In some embodiments, the first to fourth dummy holes143a,143b,138aand138bmay have a rectangular shape which extends in the third direction.

Processes substantially the same as or similar to those illustrated with reference toFIGS. 6 to 12may be performed to manufacture the vertical memory devices. For example, the dummy patterns may be formed to fill the dummy holes143a,143b,138aand138b. The dummy patterns may have a rectangular shape which extends in the third direction.

In some embodiments, the dummy holes143a,143b,138aand138bmay have a various shape to achieve the effects.

FIG. 16AandFIG. 17are a horizontal cross-sectional view illustrating methods of manufacturing vertical memory devices in accordance with some embodiments.FIG. 16Bis a vertical cross-sectional view cut along the line VII-VII′.FIG. 16Cis a vertical cross-sectional view cut along the line VIII-VIII′.

First, processes substantially the same as or similar to those illustrated with reference toFIG. 4Amay be performed. A first insulation layer110and a sacrificial layer120may be alternately and repeatedly formed on a substrate100.

Referring toFIGS. 16A to 16C, when the first holes130aare formed in the first region I of the substrate100, first dummy holes144amay be formed in the second region II of the substrate100and fourth dummy holes139bmay be formed in the third region III of the substrate100, simultaneously. In some embodiments, a plurality of first holes130a, a plurality of first dummy holes144aand a plurality of fourth dummy holes139bmay be arranged in the third direction.

In some embodiments, the first holes130aand the first and fourth dummy holes144aand139bmay have substantially the same size. The first holes130amay be spaced apart from the first and the fourth dummy holes144aand139bby a first distance d1. The first holes130aand the first and fourth dummy holes144aand139bmay be arranged at a distance, regularly and repeatedly, so that an etching process may be performed easily.

Referring toFIG. 17, when the second holes130bare formed in the first region I of the substrate100, second and third dummy holes144band139amay be formed, simultaneously. In some embodiments, a plurality of second holes130b, a plurality of second dummy holes144band a plurality of third dummy holes139amay be formed in the third direction. The second holes130bmay be spaced apart from the second and third dummy holes144band139aby the first distance d1. The second holes130band the second and third dummy holes144band139amay be arranged at a distance, regularly and repeatedly, so that an etching process may be performed easily. On the other hand, the second holes130bmay be spaced apart from the first and the fourth dummy holes144aand139bby a second distance d2which is smaller than the first distance d1. Thus, more first and second holes130aand130bmay be arranged in a given area.

Processes substantially the same as or similar to those illustrated with reference toFIGS. 6 to 12may be performed to manufacture the vertical memory devices.