Output circuit and method for suppressing switching noise therein

An output circuit (40) includes pull-up transistor (12), two pull-down transistors (14, 16), and a noise suppression circuit (58). When an input node (50) of the output circuit (40) switches to a logic high voltage, the pull-up transistor (12) is switched off. A first transistor (22) in the noise suppression circuit (58) is switched on, discharges a capacitive load (32) coupled to an output node (60) of the output circuit (40), and charges a capacitor formed by a second transistor (24) in the noise suppression circuit (58). After a time delay, the two pull-down transistors (14, 16) are switched on sequentially and establish two current paths from the output node (60) to ground (25). Then, a third transistor (56) in the noise suppression circuit (58) is switched on, discharges the capacitor (24), and establishes a third current path from the output node (60) to ground.

BACKGROUND OF THE INVENTION 
The present invention relates, in general, to an output circuit and, in 
particular, to an output circuit that includes a circuit for suppressing 
switching noise. 
Typically, a logic circuit, such as, for example, a transistor-transistor 
logic (TTL) circuit, includes an output circuit that provides a high 
output impedance and a large fan out capability. When the voltage at the 
input of the output circuit switches from one logic state to another logic 
state, a current is generated within the output circuit. The generated 
current induces a voltage in a parasitic inductance present in a bonding 
wire between a power supply bonding pad of the semiconductor chip that 
includes the output circuit and a corresponding lead in the leadframe of 
the chip. 
When the output voltage of the output circuit is switched from a high logic 
state to a low logic state, the induced voltage is referred to as 
switching noise or, more particularly, as ground bounce. Ground bounce 
causes the voltage at the output to oscillate around ground voltage. In 
logic circuits, a logic low state is defined as a voltage level lower than 
a predetermined voltage, e.g., 0.8 volt for TTL logic circuits. Ground 
bounce may raise the output voltage above the predetermined voltage, 
resulting in the output circuit transmitting an incorrect logic output 
signal. 
Ground bounce can be suppressed by reducing the lead inductance from the 
bonding pad to the lead. One approach uses a plurality of bonding wires 
for the power supply of the output circuit. Because the plurality of 
bonding wires are in parallel with each other, the total lead inductance 
is reduced. Another approach places the power supply leads to the center 
of the leadframe to shorten the length of the bonding wire, thereby 
reducing the lead inductance. However, both approaches will increase the 
complexity and the cost of packaging. Furthermore, the approach of placing 
the power supply leads to the center of the leadframe does not comply with 
the industry standard for leadframe pin outs. Ground bounce can also be 
suppressed by reducing the rate of change in the current flowing through 
the output circuit to the power supply lead during switching. One approach 
uses serpentine shaped polysilicon gates for the transistors in the output 
circuit. The transistors having serpentine shaped polysilicon gates are 
switched on gradually when the input voltage of the output circuit 
switches. Thus, the rate of change in the current in the output circuit is 
reduced. However, this approach increases the response time of the output 
circuit and significantly degrades the switching characteristics and the 
high frequency performance of the output circuit. 
Accordingly, it would be advantageous to have an output circuit and a 
method for suppressing ground bounce in the output circuit. It is 
desirable for ground bounce to be suppressed without modifying the 
packaging process and without significantly degrading the switching 
characteristics of the output circuit.

DETAILED DESCRIPTION OF THE DRAWINGS 
FIG. 1 is a schematic diagram of an output circuit 10 in accordance with a 
first embodiment of the present invention. It should be noted that output 
circuit 10 is also referred to as an output buffer or an output buffer 
circuit. Output circuit 10 includes a p-channel insulated gate field 
effect transistor (FET) 12 and n-channel insulated gate FETs 14 and 16. 
FET 14 is designed to have a smaller current conducting capacity than FET 
16. A gate electrode of FET 12 is connected to an electrode of a resistor 
11, forming an input node 20 of output circuit 10. Another electrode of 
resistor 11 is connected to a gate electrode of FET 14. A source electrode 
of FET 12 is connected to a biasing node 15 for receiving a voltage such 
as, for example, a supply voltage V.sub.DD. A source electrode of FET 14 
is coupled to a ground 25 for receiving a voltage such as, for example, 
ground voltage via a parasitic inductor 26 between a bonding pad of the 
integrated circuit chip and a corresponding lead in the leadframe of the 
chip. A drain electrode of FET 14 is connected to a drain electrode of FET 
12. A resistor 13 has one electrode connected to the gate electrode of FET 
14 and another electrode connected to a gate electrode of FET 16. A source 
electrode of FET 16 is connected to the source electrode of FET 14, 
thereby forming a node 27. A drain electrode of FET 16 is connected to the 
drain electrode of PET 12, thereby forming an output node 30 for 
transmitting an output signal of output circuit 10. 
Output circuit 10 further includes n-channel insulated gate FETs 22 and 24. 
FET 22 has a gate electrode connected to the gate electrode of FET 12, a 
source electrode connected to a gate electrode of FET 24, and a drain 
electrode connected to the drain electrode of FET 16. A source electrode 
and a drain electrode of FET 24 are connected to node 27. 
Although FETs 12, 14, 16, 22, and 24 in output circuit 10 are described as 
insulated gate FETs in FIG. 1, this is not intended as a limitation of the 
present invention. FETs 12, 14, 16, and 22 serve as switches and can be 
replaced with other types of switching devices having control electrodes 
and current conducting electrodes, e.g., bipolar transistors. When using a 
transistor as a switching device, those skilled in the art are aware that 
for a field effect transistor, a gate electrode serves as a control 
electrode, and source and drain electrodes serve as current conducting 
electrodes. Likewise, for a bipolar transistor, a base electrode serves as 
a control electrode, and emitter and collector electrodes serve as current 
conducting electrodes. It should be noted that FET 24 serves as a 
capacitive element and can be replaced with a capacitive device such as, 
for example, a capacitor, a diode, a bipolar transistor, or the like. 
FETs 12, 14, and 16 are drive transistors which determine the fan out 
capability of output circuit 10. More particularly, FET 12 is a pull-up 
transistor and FETs 14 and 16 are pull-down transistors. When an input 
signal at input node 20 is at a logic high voltage level, FET 12 is 
non-conductive and FETs 14 and 16 are conductive. FETs 14 and 16 pull the 
voltage at output node 30 to a logic low voltage level, e.g., ground. When 
the input signal at input node 20 is at a logic low voltage level, FET 12 
is conductive and FETs 14 and 16 are non-conductive. FET 12 pulls the 
voltage at output node 30 to a logic high voltage, e.g., V.sub.DD. FETs 22 
and 24 form a noise suppression circuit 28 which suppresses the switching 
noise in output circuit 10 when the output signal at output node 30 
switches from a logic high voltage level to a logic low voltage level. 
A load 32 is coupled to output node 30 of output circuit 10. Load 32 
includes any number of circuits that are coupled in parallel with each 
other and receive the output signal of output circuit 10. The maximum 
number of circuits that can be included in load 32 is determined by the 
fan out capability of output circuit 10. Load circuits are well known in 
the art. When the voltage at output node 30 changes from a logic high 
voltage level to a logic low voltage level, a load discharging current 
starts to flow from load 32 to ground via output node 30 and output 
circuit 10. The change in the load discharging current may generate ground 
bounce in an output circuit. If load 32 has a small input resistance and a 
large input capacitance, the load discharging current increases at a high 
rate during switching, which may generate a large ground bounce in an 
output circuit. If load 32 includes a plurality of load circuits coupled 
in parallel with one another, the total input capacitance of load 32 is 
equal to sum of the values of the input capacitance of each individual 
load circuit, and the total input resistance of load 32 to is equal to the 
reciprocal of the sum of the reciprocals of the input resistance of each 
individual load circuit. Therefore, a large fan out results in a large 
input capacitance and a small input resistance of load 32, which may 
generate a large ground bounce in an output circuit. 
When the input signal at input node 20 switches from a logic low voltage 
level to a logic high voltage level, FET 12 is switched off and FET 22 is 
switched on. A current path from V.sub.DD at biasing node 15 to output 
node 30 via FET 12 is open. A current flowing through FET 22 discharges 
load 32 and charges FET 24. The current flowing through FET 22 reduces the 
charge stored in the input capacitance of load 32. FET 14 is switched on 
after a time delay determined by the resistance of resistor 11 and the 
gate-source capacitance of FET 14. A current flowing through FET 14 also 
discharges load 32 by establishing a current path from output node 30 to 
ground via node 27 FET 16 is switched on to further discharge load 32 
after another time delay determined by the resistance of resistors 11 and 
13 and the gate-source capacitance of FET 16. The currents flowing through 
FETs 22, 14, and 16 pull the voltage at output node 30 to ground. 
During the switching process, the charge stored in the input capacitance of 
load 32 while the output node 30 was at a logic high voltage level is 
first reduced by the current flowing through FET 22 to the gate electrode 
of FET 24. Inductor 26 and the capacitance of FET 24 form a series 
inductor-capacitor (LC) circuit. In an LC circuit, the polarity of the 
voltage across the capacitor is opposite to the polarity of the voltage 
across the inductor. Thus, the capacitance of FET 24 tends to balance the 
effect of the inductor 26 and reduces ground bounce in output circuit 10. 
When FETs 14 and 16 are switched on, load 32 is already partially 
discharged, which results in a smaller rate of change in the current than 
that flowing through an output circuit which does not include noise 
suppression circuit 28. Furthermore, FET 14 is designed to have a smaller 
current conducting capacity than FET 16. FET 14 is switched on and 
conducts a small current to ground before FET 16 is switched on, thereby 
further reducing the rate of increase in the current flowing to ground. 
These features contribute to a suppressed ground bounce in output circuit 
10. 
Because FET 22 starts to discharge load 32, which is coupled to output node 
30, immediately after the voltage at input node 20 switches to the logic 
high voltage, output circuit 10 has a high switching speed, e.g., 
approximately two nano-seconds, and a good high frequency performance. The 
performance parameters of output circuit 10, such as switching speed, 
noise level, etc., can be optimized by adjusting the circuit parameters of 
output circuit 10, such as the current conducting capacities of FETs 14, 
16, and 22, the time delays before FETs 14 and 16 are switched on, the and 
capacitance of FET 24. 
It should be understood that resistors 11 or 13 in output circuit 10 may be 
replaced by a metal or polysilicon trace having an intrinsic resistance. 
The electrical conductivity and the cross sectional area of the trace can 
be adjusted to realize an intrinsic resistance of the trace for desired 
delay times before FETs 14 and 16 are switched on. Furthermore, in 
accordance with the present invention, resistor 11 and FET 14 are 
optional. In an output circuit which does not include resistor 11 and FET 
14, but is otherwise identical to output circuit 10, FET 16 is switched on 
after FET 22 is switched on. It should be noted that preferably there is a 
time delay between when FET 22 switches on and when FET 16 switches on. 
The performance of an output circuit which does not include resistor 11 
and FET 14 is optimized by adjusting the gate-source capacitance and the 
current conducting capacity of FET 16, the resistance of resistor 13, and 
the capacitance of FET 24. 
FIG. 2 is a schematic diagram of an output circuit 40 in accordance with a 
second embodiment of the present invention. Output circuit 40 includes all 
components in output circuit 10 of FIG. 1. It should be understood that 
the same reference numerals are used in the figures to denote the same 
elements. The gate electrode of FET 12 serves as an input node 50 for 
receiving an input signal of output circuit 40. The drain electrodes of 
FETs 12, 14, and 16 are connected together to form an output node 60 for 
transmitting an output signal of output circuit 40. Load 32 is coupled to 
output node 60. 
In addition, output circuit 40 includes a drive circuit 47, a resistor 53, 
and n-channel insulated gate FETs 48 and 56. By way of example, drive 
circuit 47 is an inverter having an input connected to the gate electrode 
of FET 12 and an output connected to a gate electrode of FET 48. A source 
electrode of FET 48 is connected to the source electrode of FET 16. A 
drain electrode of FET 48 is connected to the gate electrode of FET 16. A 
gate electrode of FET 56 is coupled to the gate electrode of FET 16 via 
resistor 53. A source electrode of FET 56 is connected to the source and 
drain electrodes of FET 24. A drain electrode of FET 56 is connected to 
the gate electrode of FET 24. 
FETs 48 and 56 serve as switches and can be replaced with other types of 
switching devices having control electrodes and current conducting 
electrodes, e.g., bipolar transistors. Like resistors 11 and 13, resistor 
53 may be replaced by a metal or polysilicon trace. 
FETs 12, 14, and 16 are drive transistors which determine the fan out 
capability of output circuit 40. More particularly, FET 12 is a pull-up 
transistor and FETs 14 and 16 are pull-down transistors. When an input 
signal at input node 50 is at a logic high voltage level, FET 12 is 
non-conductive and FETs 14 and 16 are conductive. FETs 14 and 16 pull the 
voltage at output node 60 to ground. When the input signal at input node 
50 is at a logic low voltage level, FET 12 is conductive and FETs 14 and 
16 are non-conductive. FET 12 pulls the voltage at output node 60 to a 
logic high voltage, V.sub.DD FETs 22, 24, and 56 and resistor 53 form a 
noise suppression circuit 58 which suppresses the switching noise in 
output circuit 40 when the output signal at output node 60 switches from a 
logic high voltage level to a logic low voltage level. Drive circuit 47 
and FET 48 provide a current path from the gate electrode of FET 16 to the 
source electrode of FET 16 when the input signal at input node 50 switches 
from a logic high voltage level to a logic low voltage level, thereby 
increasing the speed at which FET 16 is switched off as well as the 
switching speed of output circuit 40. 
When the input signal at input node 50 switches from a logic low voltage 
level to a logic high voltage level, the operation of FETs 12, 14, 16, 22, 
and 24 in output circuit 40 is analogous to the operation of corresponding 
FETs in output circuit 10 of FIG. 1. After FET 16 is switched on, FET 56 
is switched on. The time delay before FET 56 is switched on is determined 
by the resistance of resistors 11, 13, and 53 and the gate capacitance of 
FET 56. FET 56 discharges the charge accumulated in FET 24 and provides a 
current path from output node 60 via FET 22 to ground via node 27. A 
current flowing through FETs 22 and 56 further pulls down the voltage at 
output node 60. The currents flowing through FETs 14, 16, and 56 continue 
until the voltage at output node 30 is pulled to ground. 
In the process of switching the voltage at output node 60 from a logic high 
voltage level to a logic low voltage, FET 56 is switched on to maintain 
the current flowing from output node 60 to ground via node 27 when the 
current flowing through FET 16 approaches the current conducting capacity 
of FET 16. The current flowing through FETs 22 and 56 prevents the current 
flowing to ground 25 from decreasing. A lower rate of change in the 
current flowing to ground via node 27 generates a smaller voltage across 
inductor 26. Therefore, ground bounce is suppressed. 
Because FET 22 discharges load 32, which is coupled to output node 60, 
immediately after the voltage at input node 50 switches to the logic high 
voltage, output circuit 40 has a high switching speed, e.g., approximately 
two nano-seconds, and a good high frequency performance. The performance 
parameters of output circuit 40, such as switching speed, noise level, 
etc. can be optimized by adjusting the circuit parameters of output 
circuit 40, such as the current conducting capacities of FETs 14, 16, 22, 
and 56, the time delays before switching on FETs 14, 16, and 56, and the 
capacitance of FET 24. 
When the input signal at input node 50 switches from a logic high voltage 
level to a logic low voltage level, FET 12 is switched to a conductive 
state, thereby establishing a current path from biasing node 15 to output 
node 60. Because the gate electrode of FET 22 is directly connected to 
input node 50, FET 22 is switched to a non-conductive state. Drive circuit 
47 generates a logic high voltage at the gate electrode of FET 48, which 
is then switched on. A current path from the gate electrode to the source 
electrode of FET 16 via FET 48 switches FET 16 off. After a time delay 
determined by the resistance of resistor 11 and the gate capacitance of 
FET 14, FET 14 is switched off. FET 14 is switched off after a time delay 
determined by its gate capacitance and the resistance of resistor 11. The 
voltage at output node 60 is pulled to the supply voltage V.sub.DD, 
because FET 12 is conductive and FETs 14, 16, and 22 are non-conductive. 
FET 22 is switched off when the voltage at input node 50 switches from the 
logic high voltage to the logic low voltage because the gate electrode of 
FET 22 is directly connected to input node 50. FET 16 is switched off 
after a time delay determined by the switching speed of drive circuit 47 
and the threshold voltage of FET 48. FET 48 discharges the charge 
accumulated on the gate electrode of FET 16, thereby increasing the speed 
at which FET 16 is switched off. Thus, FET 48 serves as a discharging 
transistor for FET 16. In an output circuit which does not include drive 
circuit 47 and FET 48, but is otherwise identical to output circuit 40, 
FET 16 stays in the conductive state for a time interval determined by the 
resistance of resistors 11 and 13 and the gate capacitance of FET 16 after 
input node 50 switches from the logic high to the logic low voltage level. 
This time interval is typically longer than the switching time of drive 
circuit 47. Therefore, drive circuit 47 and FET 48 increase the speed at 
which FET 16 is switched off as well as the switching speed of output 
circuit 40. It should be noted that FET 14 stays in the conductive state 
for a time interval after input node 50 switches to a logic low voltage 
level. This time interval is determined by the resistance of resistor 11 
and the gate capacitance of FET 14. However, FET 14 typically does not 
significantly affect the switching speed of output circuit 40 because FET 
14 has a small current conducting capacity compared with FETs 16 and 22. 
It should also be noted that FET 56 stays in the conductive state for a 
time interval after input node 50 switches to a logic low voltage level. 
This time interval is determined by the switching time of drive circuit 
47, the resistance of resistor 53, and the gate capacitance of FET 56. 
Because FETs 22 and 56 are connected in series between output node 60 and 
node 25, the current flowing through FET 56 stops flowing as soon as FET 
22 is switched off. Therefore, the state of FET 56 does not affect the 
switching speed of output circuit 40 when output node 60 is switched from 
a logic low voltage level to a logic high voltage level. 
FIG. 3 is a flow chart 100 of a method for suppressing the switching noise 
in an output circuit, e.g., output circuits 10 and 40 of FIGS. 1 and 2, 
respectively, during a high to low transition at its output. With 
reference to FIG. 2, when the voltage at input node 50 of output circuit 
40 switches from a logic low voltage level to a logic high voltage level 
(step 102), the pull-up switch, FET 12, is switched off, thereby opening a 
current path from supply voltage V.sub.DD at biasing node 15 to output 
node 60 (step 103). 
The logic high voltage at input node 50 switches FET 22 on. FET 22 
establishes a first current path from output node 60 to the gate electrode 
of FET 24, which serves as a capacitor coupled between the source 
electrode of FET 22 and ground at ground 25 (step 104). The first current 
path reduces the charge on a capacitive load coupled to output node 60 and 
stores the charge in the capacitor formed by FET 
After a delay of a first time interval (step 105), the first pull-down 
transistor, FET 14, is switched on and establishes a second current path 
from output node 60 to ground via node 27 (step 106). When the second 
current path is established, load 32, which is coupled to output node 60, 
is already partially discharged through the first current path. Therefore 
the rate of increase in the current flowing to ground 25 is reduced 
compared with the case in which the second current path is established 
without discharging load 32 via the first current path. 
After a delay of a second time interval (step 107), the second pull-down 
transistor, FET 16, is switched on and establishes a third current path 
parallel to the second current path through FET 14 (step 108). FET 16 has 
a larger current conducting capacitor than FET 14. Therefore, the current 
flowing from output node 60 to ground via node 27 increases gradually. 
After a delay of a third time interval (step 109), FET 56 is switched on to 
establish a current path between the gate electrode of FET 24 and ground 
at ground 25 (step 110). FET 56 removes the charge accumulated on the gate 
electrode of FET 24 and establishes a current path via FET 22 to further 
pull down the voltage at output node 60. 
With the pull-up transistor open (step 103) and pull-down transistors 
closed (steps 106 and 108), the voltage at output node 60 is pulled to 
ground (step 112). 
By following flow chart 100, the rate of change in the current flowing from 
output node 60 to ground 25 of output circuit 40 is suppressed when the 
voltage at output node 60 is switched from a logic high voltage to a logic 
low voltage level. A suppressed rate of change in the current generates a 
suppressed voltage across inductor 26. Therefore, the switching noise in 
output circuit 40 is suppressed. Because FET 22 discharges load 32, which 
is coupled to output node 60, immediately after the voltage at input node 
50 switches to the logic high voltage, output circuit 40 has a high 
switching speed and a good high frequency performance. 
By now it should be appreciated that an output circuit and a method for 
suppressing ground bounce in the output circuit have been provided. In 
accordance with the present invention, ground bounce is suppressed by 
using a noise suppression circuit in the output circuit. Therefore, 
special packaging is not required. An integrated circuit chip which 
includes the output circuit of the present invention can be packaged using 
a cost effective packaging process which conforms with industry standards. 
Furthermore, the output circuit of the present invention suppresses ground 
bounce and maintains a high switching speed, thereby providing good high 
frequency characteristics.