Multi-chip package module and a doped polysilicon trench for isolation and connection

A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

TECHNICAL FIELD

The present invention relates to a multi-chip package module in which an intra-chip signal routing path is used to facilitate the connection of a wire bond from one chip across another chip to a lead. The present invention also relates to a doped polysilicon trench for use either as a connection to a buried layer or substrate in a vertical circuit component or as an isolation structure.

BACKGROUND OF THE INVENTION

Multi-chip packaged modules are well known in the art. In a multi-chip packaged module, a plurality of integrated circuit dies are placed on a surface of a die attach pad, which is surrounded by leads. Each die has a plurality of bonding pads. Electrical leads, such as wire bonds, connect certain bonding pads of the dies to certain leads, surrounding the die attach pad. In the prior art, if two dies are to be packaged side by side, and if an electrical connection is desired to connect the bonding pad of a first die, which is located to one side of a second die, to a lead which is on the other side of the second die, the bonding wire has to cross over the second die. This can lead to several problems. First, the wire bond must be lengthy. Second, by crossing the wire bond over the second die, the wire bond may interfere electrically with the operation of the circuit elements on the second die. Finally, if not done carefully, the wire bond may even short to other electrical terminals (including other wire bonds) over the second die. Further, in some cases, due to the presence of the adjacent die, it may not even be possible to cross the wire bond over the adjacent die.

A further problem with the prior art is if one of the dies contains a vertically oriented circuit element, such as a bipolar transistor or a vertical DMOS transistor. In that event, the bottom surface of that die is a terminal, and must be connected to a voltage other than ground. Thus, the dies cannot be connected on the same die attach pad (which is typically made of a metal), due to the potential differences between the bottom surfaces of the dies.

One prior art solution is to use multiple die attach pads, with each die attach pad for a different die, and the multiple die attach pads are then packaged in a single package. Another prior art solution is to create a re-distribution layer (RDL) with the bonding pads of the different dies connected to the RDL, and the RDL re-muting the signals to different circuit elements. Finally, another prior art solution is to connect the dies on a printed circuit board (PCB) with the PCB packaged in a die attach pad. Clearly all of these prior art solutions are expensive.

In the prior art, it is also well known to use oxide filled trenches to isolate circuit elements. In addition, through substrate vias (TSV) filled with metal have also been used to route signals from the back side of a die to the front side. Finally, junction diffusion isolation has been used to isolate circuit elements on the same die from one another.

Therefore, one object of the present invention is to reduce the cost of multi-chip packaging, and in particular to reduce the cost for a multi-chip packaging of multiple dies, where one of the dies contains a vertical circuit element.

SUMMARY OF THE INVENTION

Accordingly, in the present invention, a circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are attached to the nonconductive adhesive on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one muting path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead.

The present invention also relates to a semiconductor device which comprises a silicon layer of substantially single crystal, and has a bottom surface and a top surface. A doped layer forms a terminal along the bottom surface of the layer. A trench filled with doped polysilicon extends from the top surface to the terminal.

The present invention also relates to a semiconductor device that comprises a silicon layer of substantially single crystal, with a bottom surface and a top surface. A plurality of vertical circuit components are in the layer between the top surface and the bottom surface. A trench filled with doped polysilicon extends from the top surface to the bottom surface and isolates and separates the plurality of circuit components from one another.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring toFIG. 1there is shown a top view of the multi-chip packaged module10of the present invention. The module10comprises a die attach pad12having a surface12surrounded by a plurality of leads14(a-p). The leads14surround the surface12. Two dies18aand18bare shown, although the present invention is not limited to two dies. Each die18, as will be described hereinafter, comprises at least one circuit element. Each die18has a top surface32and a bottom surface34. On the top surface32are a plurality of bonding pads, e.g.16aand16bfor die18a. The dies18aand18bare attached to the surface12of the die attach pad along the bottom surface34of the die18with a layer of non-conductive adhesive24between the bottom surface34and the surface12of the die attach pad. As is well know in the art, wire bonds, such as20c,20dand20e, connect various bonding pads of the die18to the leads14.

In the present invention, die18bfurther comprises a signal routing layer30, on the top surface32of die18b. The routing layer30connects a bonding pad22aof the die18bto the bonding pad22b. Thus, routing layer30does not connect to any of the electrical components in the die18b, and is used solely to route signals. In the preferred embodiment, the bonding pad22ais located near a side surface which is on one side of the die18b, while the bonding pad22bis near a side surface of the die18bwhich is opposite to that of the bonding pad22a. Thus, the side surfaces to which the bonding pads22aand22bare near are parallel to one another, with the signal routing layer30routing signals from one side of the die18bto another side of the die18b. An intra-chip wire bond20aconnects bonding pad16bof die18ato bonding pad22aof die15b. Finally a bonding wire20bconnects the bonding pad22bto lead14a. In this manner, signals from the die18aat the bonding pad16bcan be electrically connected to the lead14a, without “crossing” over the die18b.

In another aspect of the present invention, one of the dies, such as die18acan contain a vertical circuit element, such as a vertical DMOS transistor. Referring toFIG. 3there is shown a cross-sectional view of a die18awith a vertical circuit element, such as a vertical DMOS transistor. As noted hereinabove, typically, in a vertical circuit component, the bottom surface34of the die18ais a doped layer33. As shown inFIG. 3, the doped layer of the die18ais a N+ layer33. In another aspect of the present invention, because the bottom surfaces34of the dies18aand18bare attached to the surface12of the die attach pad by a non-conductive adhesive24, the bottom surfaces34will not short one another. However, there remains the problem of routing the signal connection to the doped layer33along the bottom surface34. In the present invention, this is achieved by the use of a vertical trench50cut in the die18abut filled with doped polysilicon. Typically, the doped layer33is the drain of a vertical transistor, such as a bipolar transistor. In the prior art, to package a multi-chip module in which one of the dies has a vertical transistor, the connection to the drain33is done by connecting the die with its bottom surface34on a printed circuit board (PCB) substrate and then routing the signal on the PCB to the other die. With the present invention, a trench50filled with doped polysilicon connects to the drain33, and then with the connection to the trench50can be made on the same front surface32of the die18aas the rest of the electrical connections. Further, using the intra-chip signal routing path30described hereinabove, the signal from the drain33can be routed to virtually any of the leads in the die attach pad.

Referring toFIG. 4(a) there is shown a cross-sectional view of a die18with which the trench50of the present invention may be used. The die18acomprises a single crystalline substrate52, such as single crystalline silicon (although other complex single crystalline compounds, such as GaAS, may also be used). The substrate52is typically doped with P type or N type to render it conductive to act as the bottom most layer of a vertical device, such as a bipolar transistor, with the bottom surface34of the die18abeing the bottom of the substrate52, A layer54of silicon is epitaxially grown on the substrate52. Because the layer54is epitaxially grown, it will also be single crystalline, and will match the crystalline lattice structure of the substrate52. The top surface of the epitaxial layer54forms the top surface32of the die18a. A layer60of silicon (di)oxide or other insulator is grown or deposited on the top surface32. A trench50is cut into the die18a, through the oxide layer60, through the epitaxial layer54and into the substrate52. The trench50can be cut by well known techniques such as first forming a mask with a photoresist to cut into the oxide layer60. Thereafter using the exposed portion of the photoresist and the oxide60as a mask, the epitaxial layer54is cut anisotropically by reactive ion etch into the substrate52. Polysilicon is then deposited into the trench50. The polysilicon in the trench50is then doped with a dopant to render it conductive. The doping can be done by ion implant or by diffusion or may be doped in-situ with the deposition of the polysilicon in the trench50. The level of doping of the polysilicon in the trench50can be controlled to match the doping level of the substrate52to which electrical contact is desired to be made. Alternatively, a thin layer of LPCVD (Low pressure Chemical Vapor Deposition) polysilicon is first deposited into the trench50. It is then doped to either N+ or P+ to match the dopant type and concentration of the substrate layer52. Thereafter a second layer of LPCVD of polysicliocn can then be deposited into the trench50filling it. This second deposition of LPCVD can be doped to a level slightly different than the first layer of LPCVD polysilicon. The resultant structure is shown inFIG. 4(b).

Referring toFIG. 5(a) there is shown a cross-section view of another die18awith which the trench50of the present invention may be used for isolation purpose. The die18ashown inFIG. 5(a) is similar to the die shown inFIG. 4(a). The die18ashown inFIG. 5(a) comprises a layer of single crystalline substrate52of a first conductivity type. A buried layer % is formed by selectively implanting the substrate52to a second conductivity type. An epitaxial layer54is then grown on the substrate52. The epitaxial layer54is of the same conductivity as the substrate52. Due to subsequent thermal processing, dopants of the second conductivity in the buried layer56will subsequently migrate into the epitaxial layer54. Thus, the buried layer56is not a different layer, but is simply portions of the epitaxial layer54and the substrate52doped to form the connection to the vertical circuit element. In addition, the buried layer56does not extend along the entire epitaxial layer54/substrate52interface. Similar to the embodiment shown inFIGS. 4(a) and4(b) described hereinabove, trenches50are then cut into the oxide layer60through the epitaxial layer54and into the buried layer56. The trenches50are then filled with polysilicon, doped to the same conductivity type as the buried layer56to make electrical contact with the buried layer56.

Finally, referring toFIG. 6(a), there is shown a cross-section view of another embodiment of a die18afor use with the trench50of the present invention. The die18ashown inFIG. 6(a) is similar to the die18ashown inFIG. 5(a), and comprises a substrate52, with an epitaxial layer54, and a buried layer56therebetween. Unlike the embodiment shown inFIG. 5(a), however, in the embodiment shown inFIG. 6(a), the buried layer56extends across the entire interface region between the epitaxial layer54and the substrate52. Referring toFIG. 6(b) there is shown a cross section view of the die18awith the trench50made through the oxide layer60, the epitaxial layer54and into the buried layer56. The trench60is then filled with doped polysilicon to make an electrical connection to the buried layer56.

With the trench50of the present invention, because the trench50is filled with the same material (silicon) as the material through which the trench50is made (epitaxial layer54, and the buried layer56or the substrate52), there is no material incompatibility between the trench50and the layers54/56/52. Further, a doped polysilicon trench50of the present invention may also be used as an isolation structure to electrically isolate a one circuit component, such as a vertical component from other electrical components in the integrated circuit die.