Apparatus and method for a low loss coupling capacitor

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

TECHNICAL FIELD

The present invention relates to metal-oxide-semiconductor (MOS) capacitor design, and, in particular embodiments, to an apparatus and method for a low loss coupling capacitor that can be used for radio frequency (RF) or other applications.

BACKGROUND

A coupling capacitor is a type of capacitor that can be used to isolate one circuit block direct current (DC) bias from another circuit block DC bias. For example, in analog circuits, a coupling capacitor is used to connect two circuits such that only the AC signal from the first circuit can pass through to the next, while the DC is blocked. This technique helps to isolate the DC bias settings of the two coupled circuits. In another example, a coupling capacitor can be used for AC coupling in digital circuits to transmit digital signals with a zero DC component, also referred to as DC-balanced signals. DC-balanced waveforms are useful in communications systems, since they can be used over AC-coupled electrical connections to avoid voltage imbalance problems and charge accumulation between connected systems or components. There is a need to improve the coupling capacitor design to reduce losses and improve coupling efficiency, while also minimizing the design size of the capacitor structure. For example, this can be useful in compact devices to reduce size and power consumption.

SUMMARY OF THE INVENTION

In accordance with an embodiment, a circuit structure for a coupling capacitor comprises a p-doped semiconductor substrate (Psub), and a deep n-doped semiconductor well (DNW) in the Psub, a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a first block of a p-doped semiconductor material extending from a surface of the P well into the P well, and a second block of the p-doped semiconductor material extending from the surface of the P well into the P well. The first block is a source terminal, and the second block is a drain terminal. Additionally, the circuit structure comprises an insulating layer over the P well between the source and drain, a conductor material on the surface of the insulating layer serving as the gate, a metal pattern comprising a plurality of layers of metal lines approximately parallel to the surface, and a plurality of vias through the metal lines and vertical to the metal lines. The lowest level vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

In accordance with another embodiment, a circuit structure for a coupling capacitor comprises a Psub, and a n-doped semiconductor well (N well) in the Psub. The circuit structure further comprises a first block of a n-doped semiconductor material extending from a surface of the N well into the N well, and a second block of the n-doped semiconductor material extending from the surface of the N well into the N well. The first block serves is a source terminal, and the second block is a drain terminal. Additionally, the circuit structure further comprises an insulating layer on the surface of the N well between the source and drain, a conductor material on the surface of the insulating layer serving as the gate, a metal pattern comprising a plurality of layers of metal lines approximately parallel to the surface, and a plurality of vias through the metal lines and vertical to the metal lines. Contacts connect the metal lines to the gate, the source terminal, and the drain terminal.

In accordance with another embodiment, a method for making a coupling capacitor structure in a n-type varactor (NVAR) configuration includes forming a DNW in a Psub, forming a p-doped semiconductor well (P well) in the DNW, placing an insulator on the surface of the P well followed by a metal gate on a surface of the insulator. The method further includes forming, inside the P well within the surface of the P well, a p-doped semiconductor source terminal on one side of the insulator and metal gate, and a p-doped semiconductor drain terminal on an opposite side of the insulator and metal gate. A plurality of layers of metal lines is overlaid over the metal gate and the source/drain terminals. Further, a plurality of vias are inserted vertical to the layers and connecting the metal lines with the metal gate, the p-doped semiconductor source terminal, and the p-doped semiconductor drain terminal.

In accordance with yet another embodiment, a method for making a coupling capacitor structure in a p-type varactor (PVAR) configuration includes forming a N well in a Psub, placing an insulator followed by a metal gate on a surface of the N well, and forming, inside the N well within the surface of the P well, a n-doped semiconductor source terminal on one side of the insulator/metal gate, and a n-doped semiconductor drain terminal on an opposite side of the insulator/metal gate. The method further includes overlaying a plurality of layers of metal lines is overlaid over the metal gate and the source/drain terminals. Further, a plurality of vias are inserted vertical to the layers connecting the metal lines to the metal gate, the n-doped semiconductor source terminal, and the n-doped semiconductor drain terminal.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Embodiments are provided herein for low loss coupling capacitor structures, which can be constructed using metal-oxide-semiconductor (MOS) technology or other suitable integrated circuit manufacturing processes. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The choice of the configuration depends on the circuit conditions and the application of interest. A varactor is a type of diode of which capacitance varies as a function of the voltage applied across its terminals. Varactors can be used as voltage-controlled capacitors, such as in voltage-controlled oscillators, parametric amplifiers, and frequency multipliers, which can be used in radio transmitters or signal modulators, for example. In the NVAR and PVAR configurations, multiple gate and source/drain connections are realized using stacked layers of interleaved metal patterns for the gate and source/drain connections, respectively. The structures designs can reduce resistance and parasitic capacitance, which lower losses in the capacitors. The parasitic capacitance can be reduced by reverse biasing the structure well capacitance. Further, the metal pattern is designed to enhance wanted capacitance and reduce parasitic capacitance. The structures also allow the integration of multiple coupling capacitors, e.g., in an array, on a chip with compact dimensions, thus achieving high capacitance per area. Such structures can be used for radio frequency (RF) or wireless signal applications, for instance, to provide low loss RF differential signal paths. The differential signals can be accommodated by placing the capacitors in isolated wells.

FIG. 1shows an embodiment of a capacitor structure (circuit) in a NVAR configuration100. The NVAR configuration100comprises a suitable p-type semiconductor (P) block that acts as a drain101(P+ drain) and another P block that acts as a source102(P+ source) for the capacitor. For instance, the drain101and source102are p-doped silicon or other suitable semiconductor material. Both the drain101and the source102are placed in a p-type well104(P well), for instance in p-doped Si. The P well104is formed within the semiconductor substrate106, e.g., a Si substrate. Specifically, the substrate106(Psub) is p-doped. For example, the substrate106is p-dope Si. The P well104extends from the top of the surface to a suitable determined depth in the DNW105. An insulating layer119is formed on the surface of P well104, and a conductor block is formed on the top surface of the insulating layer119which is positioned approximately at the middle of the P well104beneath it. The conductor block acts as a gate103for the capacitor structure, and can be made of poly-Si or other suitable metal/conductor material. In other embodiments, semiconductor materials other than Si or poly-Si can be used to form the components above. Examples of such materials include silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN). Further, the P well104is placed in a deep n-type well105(DNW) within the substrate. The DNW105is formed within the Psub106. The DNW105extends from the top of the surface to a suitable determined depth in the substrate106. The DNW105is relatively heavily doped and is deeper and larger than the P well104and surrounds the P well104, as shown. The DNW105is more heavily doped than the P well104.

As shown, the source102and drain101are positioned in the P well104, within the substrate106, at opposite ends of the gate103, which is placed over the surface of the substrate106with an insulating layer between the gate and P well. The gate forms one terminal of the capacitor. The source102and drain101, form the second terminal, the source102and drain101are electrically connected through the P well and externally through metal connections as described below. This arrangement of the gate and source102/drain101and insulator forms the coupling capacitor, where the capacitance is generated between the gate103and the source102/drain101connection.

The cross-section side view of the structure inFIG. 1shows one pair of source102/drain101and corresponding gate103in the P well104. However, the NVAR configuration100can comprise multiple capacitor elements configured as such, by distributing and overlaying source/drain and corresponding gate blocks across corresponding wells similar to the Psub106. The capacitor elements can be interconnected, e.g., in parallel, to increase the coupling capacitance by stacking and interleaving metal lines (or wires) in layers on the surface and interconnecting the resulting metal pattern107using metal/conductor vias108to the corresponding gate and source/drain terminals at the surface level. The metal pattern107is overlaid over the surface, and the vias108are vertical vias that connect the corresponding metal lines to the corresponding gate and source/drain terminals. The metal pattern107comprises lines or wires that connect the gates, and further lines that connect the source/drain terminals. In an embodiment, the metal lines connecting the source/drain sides can be positioned next to and under the metal lines connecting the gate sides, as illustrated inFIG. 1. Examples of metal pattern design that can be used for interconnecting the capacitor elements are described below.

In the NVAR configuration100, the capacitor structure separates two circuit blocks that are applied different DC bias (different DC voltages). The DC bias of one circuit block is connected to the source102/drain101, and the DC bias for the other circuit block is connected to the gate103. As such, the two DC voltages bias the capacitor structure resulting in higher capacitance than the case where the source102/drain101and gate103were not biased. For an NVAR, the gate is at a lower potential than the source102/drain101. The voltage supply109connected to the resistor111is set to a different voltage than that applied to the source102/drain101or gate103. The purpose of the different voltage of the supply109is to reverse bias both the P well104/DNW105junction and the DNW105/Psub106junction. Reverse biasing these junctions as such reduces unwanted parasitic capacitance.

FIG. 2shows an embodiment of a capacitor structure (circuit) in a PVAR configuration200. The PVAR configuration200comprises a suitable n-type semiconductor (N) block that acts as a drain201(N+ drain) and another N block that acts as a source202(N+ source) for the capacitor. The drain201and source202are n-doped silicon or other suitable semiconductor material. Both the drain201and the source202can be placed in a n-type well210(N well), for instance in n-doped Si. The N well210is less heavily doped than the DNW105in the NVAR configuration100. In the PVAR configuration200, the N well210is formed within semiconductor substrate206, e.g., a Si substrate. Specifically, the substrate206(Psub) is p-doped. For example, the substrate206is p-dope Si. The N well210extends from the top of the surface to a suitable determined depth in Psub206. An insulating layer219is formed on the surface of the N well210followed by a conductor block positioned approximately at the middle of the N well210beneath it. The conductor block acts as a gate203for the capacitor structure, and can be made of poly-Si or other suitable metal/conductor material. In other embodiments, doped semiconductor materials other than Si or poly-Si, e.g., SiC, GaAs or Gan, can be used to form the components above.

As shown, the source202and drain201are positioned within the N well210at opposite ends of the insulator219/gate203, which is placed over the surface of P sub206. The gate203forms one terminal of the PVAR capacitor and the source202/drain201forms the second terminal of the PVAR capacitor. The source202and drain201are connected electrically by the N well210and externally by metal lines as described below.

Similar to the NVAR configuration100, the cross-section side view of the PVAR configuration200inFIG. 2shows one pair of source202/drain201and corresponding gate203in the N well210. However, the NVAR configuration200can comprise multiple capacitor elements configured as such, by distributing and overlaying source/drain and corresponding gate blocks across wells similar to the N well210. The capacitor elements can be interconnected, e.g., in parallel, to increase the coupling capacitance by stacking and interleaving metal lines (or wires) in layers on the surface and interconnecting the resulting metal pattern207using metal/conductor vias208to the corresponding gate and source/drain terminals at the surface level. The metal pattern207is overlaid over the surface, and the vias208are vertical vias that connect the corresponding metal lines to the corresponding gate and source/drain terminals. The metal pattern207is similar to the metal pattern107and comprises lines that connect the gates, and further lines that connect the source/drain terminals. Similar to an NVAR, the PVAR separates two blocks biased with different DC biases. The DC bias of one block is connected to the gate203and the other DC bias is connected to the source202/drain201. In contrast to the NVAR, the gate bias is higher than the source/drain bias.

FIG. 3is a top view of an embodiment of a metal pattern300for gate connection and source/drain connection. For example, the metal pattern may correspond to the metal pattern107in the NVAR configuration100and similarly the metal pattern207in the PVAR configuration200. The metal pattern300connects multiple source/drain terminals to other source/drain terminal blocks. The same or a similar metal arrangement connects multiple gate terminals to other gate terminal blocks on the capacitor structure (NVAR or PVAR structure), thus forming a combined capacitor with the desired increased capacitance and lower loss (e.g., due to lower parasitic capacitance and other parasitic parameters). The gate terminal forms one input of the capacitor, and the source/drain terminals form the second input of the capacitor. The source/drain terminals and gate blocks may be distributed, for example, in a two-dimensional array pattern in corresponding wells (P wells in NVAR or N wells in PVAR) in the structure substrate. The metal pattern300comprises stacked and interleaved conductor/metal lines or wires in the horizontal direction with respect to the structure substrate and vertical vias that connect the lines to their corresponding source/drain and gate blocks. The interleaved lines in any layer are adjacent lines that have alternating connections (using vias) to gate blocks and source/drain terminals. The pattern300is partially shown and shows a top view of multiple layers of lines (stacked vertically with respect to the substrate). In the actual structure, the metals lines extend to fill a given area on the substrate. In this example, the pattern300includes three layers for the gate connections and further three layers for the source/drain connections. The metal lines can be placed and aligned over the gate because capacitance between the gate and source/drain is desirable. However, the metal lines are not placed over the DNW or substrate because coupling to those areas results in undesirable parasitic capacitance. Reducing the parasitic capacitance as such reduces losses in the capacitor structure. The metal lines in each layer may be similar, and the metal lines in different layers may have different dimensions, such as different width, thickness, and or length.

FIG. 4is an isometric view of an embodiment of a metal pattern for gate and source/drain (S/D) connections, which may be used in the NVAR and similarly the PVAR configurations. The metal pattern comprises a plurality of layers, for instance, four layers (M1 to M4) in this example, of metal line connections to the gate elements and the source/drain elements. The lines in each layer are parallel and the lines of adjacent stacked layers are perpendicular. Each layer comprises alternating lines between gate connection lines and source/drain connection lines. The gate connection lines in the layers are connected to each other using vertical vias to the layers. Similarly, the source/drain connection lines in the layers are connected to each other using a separate set of vias.

FIG. 5is a top view of an embodiment of a capacitor array layout. The capacitor array can be arranged as such on the NVAR configuration100and similarly the PVAR configuration200. The array comprises a plurality of similar cells, as shown. A first top metal layer (Metal Layer 1) comprises vertical parallel metal lines with contacts (by vias) to the source, drain and gate material below the metal layers at the substrate surface. A second metal layer (Metal Layer 2) above the first metal layer comprises horizontal parallel metal lines also with vias to the first metal layer. In each metal layer above the first layer, vias connect to adjacent metal layers. In the first metal layer contacts connect to the gate and source/drain and vias connect to the layers above metal layer 1. Some of the metal lines or layers may not be directly connected to the gate and source/drain, but are connected by vias to other metal lines that are directly connected, by other vias, to the gate and source/drain. The layout can comprise additional layers of metal lines. The higher level metal layers (towards the top of the substrate) may have greater width and larger spacing than the lower metal layers. Stacking the metal connections in layers as such increases the effective capacitance of the overall structure and reduces loss due to the lower parasitic capacitance.

FIG. 6shows an embodiment of a method600for making a low loss coupling capacitor structure (circuit) with a NVAR configuration. The steps of the method600can be implemented using any suitable semiconductor processes and circuit fabrication technologies (e.g., lithographic and integrated chip fabrication processes). At step610, A deep n-type well (DNW) such as n-dope Si is formed, e.g., via doping, in a p-doped semiconductor substrate (P sub), e.g., p-type Si. At step620, an array of p-type wells (P wells) such as p-doped Si is formed in the DNW. At step625, an array of insulating layer blocks are formed on the array of P wells. At step630, an array of gate and source/drain blocks is formed on the array of P wells, at the surface of the p-doped substrate. The source and drain material is p-doped, e.g., p-type silicon, and the gate material is a conductor/metal. The source and drain blocks are placed, within the P wells, on opposite sides of the insulating layer blocks. The gate is positioned between the source and the drain blocks and on top of the insulating layer blocks. At step640, a metal pattern comprising multiple layers of metal lines are formed on the substrate over the array of gate and source/drain material. At step645, the stacked metal lines are connected with vertical vias (referred to as contacts) to the gate and source/drain array beneath the metal layers. At step650, the coupling capacitor structure is biased by connecting a DC bias to the gate connections (e.g., metal lines) and the S/D connections. The DNW/P well junction and DNW/Psub junction are reversed biased by grounding the Psub and connecting a DC voltage supply through a resistor to the DNW portion of the structure (e.g., a resistor is inserted) in series between the supply and the DNW portion of the structure.

FIG. 7shows an embodiment of a method700for making a low loss coupling capacitor structure (circuit) with a PVAR configuration. The steps of the method600can be implemented using any suitable semiconductor processes and circuit fabrication technologies (e.g., lithographic and integrated chip fabrication processes). At step710, an array of n-type wells (N wells) such as n-dope Si is formed, e.g., via doping, in a p-doped substrate (Psub), e.g., p-type Si. At step715, an array of insulating layer blocks are formed on the array of N wells. At step720, an array of gate and source/drain blocks is formed on the array of N wells, at the surface of the p-doped substrate. The source and drain material is n-doped, e.g., n-type silicon, and the gate material is a conductor/metal. The source and drain blocks are placed, within the N wells, on opposite sides of the insulating layer blocks. The gate is positioned between the source and the drain blocks and on top of the insulating layer blocks. At step730, a metal pattern comprising multiple layers of metal lines are formed on the substrate over the array of gate and source/drain material. At step735, the stacked metal lines are connected with vertical vias (contacts) to the gate and source/drain array beneath the metal layers. At step740, the coupling capacitor structure is biased by connecting a DC bias to the gate, a second DC bias to the S/D connections (e.g., metal lines), and by grounding the Psub.

FIG. 8shows an embodiment of a capacitor structure (circuit) in a NVAR configuration. The capacitor structure ofFIG. 8may be a specific implementation of the capacitor structure ofFIG. 1where an array of two or more P wells104are placed in a deep n-type well105(DNW) within a substrate106(Psub). All similarly numbered elements are as previously described.