Semiconductor packages including through mold ball connectors and methods of manufacturing the same

There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2016-0061098, filed on May 18, 2016, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor packages and, more particularly, to semiconductor packages including through mold ball connectors and methods of manufacturing the same.

2. Related Art

In the electronics industry, a single unified package including a plurality of semiconductor devices is increasingly in demand with the development of multi-functional, larger storage capacity and smaller electronic systems or products. The single unified package may be designed to reduce a total size of the package and to have various functions. The single unified package may be realized to include a plurality of semiconductor chips having different functions. This is for processing a large amount of data at a time. A system-in-package (SIP) has been proposed to provide the single unified package. For example, a lot of effort has been focused on integrating at least one microprocessor and at least one memory chip in a single system-in-package.

SUMMARY

According to an embodiment, there is provided a method of manufacturing a semiconductor package. The method includes forming an interconnection structure layer including conductive trace patterns and a dielectric layer on a dummy wafer, attaching a carrier wafer to a second surface of the interconnection structure layer opposite to the dummy wafer, removing the dummy wafer to expose a first surface of the interconnection structure layer opposite to the carrier wafer, mounting at least one first semiconductor device and through mold ball connectors (TMBCs) on the first surface of the interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors (TMBCs), respectively attaching outer connectors to the exposed portions of the through mold ball connectors (TMBCs), removing the carrier wafer to expose the second surface of the interconnection structure layer, and mounting a second semiconductor device on the second surface of the interconnection structure layer.

According to another embodiment, there is provided a method of manufacturing a semiconductor package. The method includes mounting a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors (TMBCs), respectively attaching outer connectors to the exposed portions of the through mold ball connectors (TMBCs), and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the first semiconductor device.

According to another embodiment, a semiconductor package includes a first semiconductor device disposed on a first surface of an interconnection structure layer, through mold ball connectors (TMBCs) disposed on the first surface of the interconnection structure layer to be adjacent to the first semiconductor device, a molding layer disposed on the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors (TMBCs), respectively outer connectors attached to the exposed portions of the through mold ball connectors (TMBCs), and a second semiconductor device disposed on a second surface of the interconnection structure layer opposite to the first semiconductor device. Each of the through mold ball connectors (TMBCs) includes a copper ball.

According to another embodiment, there is provided a memory card including a semiconductor package. The semiconductor package includes a first semiconductor device disposed on a first surface of an interconnection structure layer, through mold ball connectors (TMBCs) disposed on the first surface of the interconnection structure layer to be adjacent to the first semiconductor device, a molding layer disposed on the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors (TMBCs), respectively outer connectors attached to the exposed portions of the through mold ball connectors (TMBCs), and a second semiconductor device disposed on a second surface of the interconnection structure layer opposite to the first semiconductor device. Each of the through mold ball connectors (TMBCs) includes a copper ball.

According to another embodiment, there is provided an electronic system including a semiconductor package. The semiconductor package includes a first semiconductor device disposed on a first surface of an interconnection structure layer, through mold ball connectors (TMBCs) disposed on the first surface of the interconnection structure layer to be adjacent to the first semiconductor device, a molding layer disposed on the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors (TMBCs), respectively outer connectors attached to the exposed portions of the through mold ball connectors (TMBCs), and a second semiconductor device disposed on a second surface of the interconnection structure layer opposite to the first semiconductor device. Each of the through mold ball connectors (TMBCs) includes a copper ball.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but not used to define only the element itself or to mean a particular sequence.

Semiconductor packages according to the following embodiments may correspond to system-in-packages (SIPs). Each of the semiconductor packages may be realized to include a plurality of semiconductor devices, at least two of which are designed to have different functions. The semiconductor devices may be obtained by separating a semiconductor substrate such as a wafer including electronic circuits into a plurality of pieces (having semiconductor die shapes or semiconductor chip shapes) using a die sawing process. Alternatively, each of the semiconductor devices may have a package form including a package substrate and a semiconductor die mounted on the package substrate. Each of the semiconductor devices may include a plurality of semiconductor dice which are vertically stacked to have a three-dimensional structure, and the plurality of semiconductor dice may be electrically connected to each other by silicon through vias (TSVs) penetrating the plurality of semiconductor dice. The semiconductor dice may correspond to memory chips including dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, flash circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits or phase change random access memory (PcRAM) circuits which are integrated on the semiconductor substrate. The semiconductor chips or the semiconductor packages may be employed in communication systems such as mobile phones, electronic systems associated with biotechnology or health care, or wearable electronic systems.

In some embodiments, the semiconductor chip may correspond to a logic chip having a system-on-chip (SoC) form. The SoC may be an application specific integrated circuit (ASIC) chip including a microprocessor, a microcontroller, a digital signal processing core or an interface. The SoC may include a central processing unit (CPU) or a graphics processing unit (GPU). In order that the SoC operates at a high speed, the SoC has to communicate with a memory chip storing data at a high speed. That is, a short interface path and a high signal bandwidth may be required to improve an operation speed of the SoC. For example, if a GPU chip and a high bandwidth memory (HBM) chip are vertically stacked in a single SIP, an interface path between the GPU chip and the HBM chip may be reduced to improve an operation speed of the GPU chip.

In an electronic system, a bottleneck phenomenon in communication between a memory chip and a processor chip may degrade the performance of the electronic system. Accordingly, high performance memory chips such as HBM chips may be employed as memory chips of the electronic systems. The HBM chip may be configured to include a plurality of memory dice which are vertically stacked using a TSV technique to obtain a high bandwidth thereof. The HBM chip may include a plurality of TSVs connected to each of the memory dice to independently control the respective memory dice which are vertically stacked. Each of the memory dice may be configured to include two memory channels, and a plurality of TSVs, for example, one hundred and twenty eight TSVs acting as input/output (I/O) pins may be required for operation of each memory channel. Accordingly, an HBM chip comprised of four stacked memory dice may include one thousand and twenty four TSVs to independently control eight memory channels. In such a case, one of the eight memory channels may independently communicate with another one of the eight memory channels through the TSVs. Thus, a signal bandwidth of the HBM chip may be broadened because each memory channel independently and directly receives or outputs signals through the TSVs.

However, if the number of the TSVs increases to improve the bandwidth of the HBM chip, a pitch size of interconnection lines or pads included in the HBM chip may be reduced. Therefore, the following embodiments provide various SIPs having a configuration that electrically connects the memory chip to the ASIC chip using an interconnection structure layer realized with a wafer processing technique which is capable of forming fine patterns.

The same reference numerals refer to the same elements throughout the specification. Thus, even though a reference numeral is not mentioned or described with reference to a drawing, the reference numeral may be mentioned or described with reference to another drawing. In addition, even though a reference numeral is not shown in a drawing, it may be mentioned or described with reference to another drawing.

FIGS. 1 to 19are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment.

FIG. 1illustrates a step of forming an interconnection structure layer100on a dummy wafer900. The dummy wafer900may be a wafer having a first surface901and a second surface902which are opposite to each other. The interconnection structure layer100may be formed on the first surface901of the dummy wafer900. The interconnection structure layer100may be formed using a silicon processing technique or a semiconductor processing technique. The interconnection structure layer100may be formed by sequentially or alternately stacking a plurality of dielectric layers and a plurality of conductive layers. In such a case, each of the conductive layers included in the interconnection structure layer100may be patterned after it is stacked. The interconnection structure layer100may be formed to have a first surface101that faces and contacts the first surface901of the dummy wafer900and to have a second surface102which is opposite to the dummy wafer900. A multi-layered interconnection structure may be disposed in the interconnection structure layer100to electrically connect some members disposed on the first surface101of the interconnection structure layer100to each other. The interconnection structure layer100may be formed to include a plurality of stacked dielectric layers that electrically insulate or physically separate conductive trace patterns from each other.

The dummy wafer900may be used as a supporter or a substrate when the interconnection structure layer100is formed. The dummy wafer900may be a silicon wafer which may be bare. Alternatively, the dummy wafer900may be a non-semiconductor wafer. For example, the dummy wafer900may be a wafer including an insulation material or a dielectric material. In some embodiments, the dummy wafer900may be a sapphire wafer or a silicon on insulator (SOI) wafer. If a bare silicon wafer is used as the dummy wafer900, the interconnection structure layer100may be formed using semiconductor wafer processing apparatuses and semiconductor wafer processing techniques.

Although processes for forming the interconnection structure layer100are described hereinafter in conjunction with wafer processing techniques, the present disclosure is not limited thereto. For example, the interconnection structure layer100may be formed by changing or modifying a process sequence or pattern shapes used in the following embodiments. The dummy wafer900may provide the first surface901having a flat surface profile. Thus, the interconnection structure layer100may be formed to include conductive trace patterns having a fine pitch.

FIGS. 2 to 4are enlarged views illustrating a portion of the interconnection structure layer100and illustrating a step of forming the interconnection structure layer100. As illustrated inFIG. 2, first outer conductive trace patterns110may be formed on the first surface901of the dummy wafer900. Specifically, a conductive layer such as a metal layer may be formed on the first surface901of the dummy wafer900, and the conductive layer may be patterned using a photolithography process and an etch process to form the first outer conductive trace patterns110. The first outer conductive trace patterns110may be formed of a copper (Cu) layer or an aluminum (Al) layer.

The first outer conductive trace patterns110may correspond to some of interconnection lines included in the interconnection structure layer100. The first outer conductive trace patterns110may be formed to have pad shapes. The first outer conductive trace patterns110may include first patterns112and second patterns113having substantially the same shape as the first patterns112. The first and second patterns112and113of the first outer conductive trace patterns110may be connected to a first semiconductor device which is disposed as later described. The first outer conductive trace patterns110may further include third patterns114and fourth patterns115having substantially the same shape as the third patterns114. The third and fourth patterns114and115of the first outer conductive trace patterns110may be connected to outer connectors such as solder balls which are disposed as later described. The third and fourth patterns114and115of the first outer conductive trace patterns110may be formed to have a pitch (or a width) which is greater than a pitch (or a width) of the first and second patterns112and113of the first outer conductive trace patterns110. Even though a pitch of the third and fourth patterns114and115is different from a pitch of the first and second patterns112and113, all of the first outer conductive trace patterns110may be patterned to have relatively finer pitches as compared with a case that printed circuit patterns are formed on a general printed circuit board (PCB) because a surface flatness of the dummy wafer900is more well defined than that of the PCB.

As illustrated inFIG. 3, a first dielectric layer191may be formed on the first surface901of the dummy wafer900to cover and insulate the first outer conductive trace patterns110from each other. The first dielectric layer191may be formed to include at least one of various dielectric materials. For example, the first dielectric layer191may be formed of an interlayer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer comprised of a silicon oxide layer, a silicon nitride layer, or a polymer layer such as a polyimide layer. The first dielectric layer191may be formed using a lamination process, a deposition process or a coating process.

First inner conductive trace patterns120may be formed on the first dielectric layer191. The first inner conductive trace patterns120may be formed to provide routes for the first outer conductive trace patterns110. For example, the first inner conductive trace patterns120may be formed to be electrically connected to the first outer conductive trace patterns110through vias191vthat substantially penetrate the first dielectric layer191. A first pattern120A corresponding to one of the first inner conductive trace patterns120may be formed to act as a horizontal interconnection portion161electrically connecting the second pattern113of the first outer conductive trace patterns110to the third pattern114of the first outer conductive trace patterns110.

As illustrated inFIG. 4, a second dielectric layer193may be formed on the first dielectric layer191to cover and insulate the first inner conductive trace patterns120from each other. The second dielectric layer193may be formed to include at least one of various dielectric materials. Second inner conductive trace patterns130may be formed on the second dielectric layer193. The second inner conductive trace patterns130may be formed to provide routes for the first inner conductive trace patterns120. Some of the second inner conductive trace patterns130may be formed to be electrically connected to some of the first inner conductive trace patterns120through vias that substantially penetrate the second dielectric layer193.

A third dielectric layer194may be formed on the second dielectric layer193to cover and insulate the second inner conductive trace patterns130from each other. The third dielectric layer194may be formed to include at least one of various dielectric materials. Third inner conductive trace patterns140may be formed on the third dielectric layer194. The third inner conductive trace patterns140may be formed to provide routes of the second inner conductive trace patterns130. Some of the third inner conductive trace patterns140may be formed to be electrically connected to some of the second inner conductive trace patterns130through vias that substantially penetrate the third dielectric layer194.

A fourth dielectric layer195may be formed on the third dielectric layer194to cover and insulate the third inner conductive trace patterns140from each other. The fourth dielectric layer195may be formed to include at least one of various dielectric materials. Second outer conductive trace patterns150may be formed to penetrate the fourth dielectric layer195. The second outer conductive trace patterns150may be electrically connected to some of the third inner conductive trace patterns140, respectively. One of the first inner conductive trace patterns120, one of the second inner conductive trace patterns130, and one of the third inner conductive trace patterns140may constitute a first vertical interconnection portion162that electrically connects one of the first patterns112of the first outer conductive trace patterns110to one of the second outer conductive trace patterns150. Another one of the first inner conductive trace patterns120, another one of the second inner conductive trace patterns130, and another one of the third inner conductive trace patterns140may constitute a second vertical interconnection portion163that electrically connects one of the fourth patterns115of the first outer conductive trace patterns110to one of the second outer conductive trace patterns150.

The first to fourth dielectric layers191,193,194and195may constitute a body of the interconnection structure layer100that insulates the trace patterns110,120,130,140and150from each other.

FIG. 5illustrates a step of forming first bump pads250on the second surface102of the interconnection structure layer100, andFIG. 6is an enlarged view illustrating a portion of the interconnection structure layer100shown inFIG. 5. As illustrated inFIGS. 5 and 6, the first bump pads250may be formed on the interconnection structure layer100. The first bump pads250may be pads on which connectors such as bumps are landed as later described. The first bump pads250may be formed to overlap with the second outer conductive trace patterns150. The first bump pads250may be electrically connected to the second outer conductive trace patterns150, respectively. One pad250A of the first bump pads250may be electrically connected to the first vertical interconnection portion162, and another pad250B of the first bump pads250may be electrically connected to the second vertical interconnection portion163. The first bump pads250may be formed using a plating process. The first bump pads250may be formed to include copper (Cu).

FIG. 7is a cross-sectional view illustrating a step of attaching a carrier wafer800to the second surface102of the interconnection structure layer100opposite to the dummy wafer900. In one example, the first bump pads250on the second surface102of the interconnection structure layer100may be formed before the carrier wafer800is attached to the second surface102of the interconnection structure layer100. The carrier wafer800may be bonded to the interconnection structure layer100using a temporary adhesive layer810to protect the first bump pads250. The carrier wafer800may act as a supporter for handling the interconnection structure layer100in subsequent processes.

FIG. 8is a cross-sectional view illustrating a step of exposing the first surface101of the interconnection structure layer100. Specifically, the dummy wafer900may be removed from the interconnection structure layer100to expose the first surface101of the interconnection structure layer100opposite to the carrier wafer800. More specifically, the dummy wafer900may be ground to reduce a thickness of the dummy wafer900, and the remaining portion of the dummy wafer900may be etched to expose the first surface101of the interconnection structure layer100. As a result, the interconnection structure layer100may be separated from the dummy wafer900by grinding and etching the dummy wafer900.

FIG. 9is a cross-sectional view illustrating a step of forming second bump pads230on the first surface101of the interconnection structure layer100, andFIG. 10is an enlarged view of a portion of the interconnection structure layer100shown inFIG. 9. As illustrated inFIGS. 9 and 10, the second bump pads230may be formed on the first surface101of the interconnection structure layer100. Connectors such as bumps may be landed on and bonded to the second bump pads230in a subsequent process. The second bump pads230may be formed to overlap with the first and second patterns112and113of the first outer conductive trace patterns110, respectively. The second bump pads230may be electrically connected to the first and second patterns112and113, respectively. One pad230A of the second bump pads230may be electrically connected to the first vertical interconnection portion162, and another pad230B of the second bump pads230may be electrically connected to the horizontal interconnection portion161. The second bump pads230may be formed by plating a copper material.

FIG. 11is a cross-sectional view illustrating a step of forming third bump pads240on the first surface101of the interconnection structure layer100, andFIG. 12is an enlarged view of a portion of the interconnection structure layer100shown inFIG. 11. As illustrated inFIGS. 11 and 12, the third bump pads240may be formed on the first surface101of the interconnection structure layer100. The third bump pads240may be formed to have a pitch which is different from a pitch of the second bump pads230. For example, the third bump pads240may be formed to have a pitch which is greater than a pitch of the second bump pads230. The third bump pads240may be formed having a conductive layer with a thickness which is different from a thickness of the second bump pads230. For example, the third bump pads240may be formed to include a copper layer having a thickness which is greater than a thickness of the second bump pads230.

The third bump pads240may be formed to overlap with the third and fourth patterns114and115of the first outer conductive trace patterns110, respectively. The third bump pads240may be electrically connected to the third and fourth patterns114and115, respectively. One pad240A of the third bump pads240may be electrically connected to the horizontal interconnection portion161, and another pad240B of the third bump pads240may be electrically connected to the second vertical interconnection portion163. The third bump pads240may be formed by plating a copper material.

FIG. 13is a cross-sectional view illustrating a step of mounting at least one first semiconductor device300on the first surface101of the interconnection structure layer100. The first semiconductor devices300may be bonded to the second bump pads230using first chip connectors630. The first chip connectors630may be conductive connection members such as micro-bumps. One of the first semiconductor devices300may be electrically connected to the pads240A of the third bump pads240. For example, one of the first semiconductor devices300may be electrically connected to the third bump pads240through one of the first chip connectors630, one (230B ofFIG. 12) of the second bump pads230, and the horizontal interconnection portion (161ofFIG. 12). The horizontal interconnection portion (161ofFIG. 12) may be comprised of one of the second patterns113of the first outer conductive trace patterns110, the first pattern (120A ofFIG. 12) of the first inner conductive trace patterns120, and one of the third patterns114of the first outer conductive trace patterns110. At least one of the first semiconductor devices300may be electrically connected to one or more pads of the first bump pads250. At least one of the first semiconductor devices300may be electrically connected to one or more pads of the first bump pads250through one of the first chip connectors630, another one (230A ofFIG. 12) of the second bump pads230, and the first vertical interconnection portion (162ofFIG. 12). The first semiconductor devices300may be memory devices. For example, the first semiconductor devices300may be DRAM devices.

FIG. 14is a cross-sectional view illustrating a step of mounting at least one through mold ball connector (TMBCs)410B on the first surface101of the interconnection structure layer100. Specifically, the TMBCs410B may be attached to the third bump pads240, respectively. Each of the TMBCs410B may have a ball shape, for example, a copper ball shape. A solder ball containing tin (Sn) has a low melting point of about 220 degrees Celsius. Thus, the tin (Sn) based solder balls may be inappropriate for the TMBCs410B. Copper balls may have a melting point which is higher than a melting point of the tin (Sn) based solder balls. Thus, the copper balls may be appropriate for the TMBCs410B. In addition, the copper balls may have an electrical conductivity which is higher than an electrical conductivity of the tin (Sn) based solder balls. Thus, the copper balls may be more appropriate for the TMBCs410B. The copper balls coated with a solder layer that may be picked and placed on the third bump pads240, respectively. Subsequently, the copper balls may be bonded to the third bump pads240using a solder reflow process to provide the TMBCs410B attached to the third bump pads240. The solder layer coated on the TMBC410B copper balls may include a nickel solder layer or a nickel layer. The nickel solder layer may be, for example, a nickel-phosphorus (Ni—P) layer. In some other embodiments, a solder layer may be formed on surfaces of the third bump pads240without using the copper balls coated with a solder layer, and the solder layer may be reflowed to provide the TMBCs410B on the third bump pads240.

A height H1of the TMBCs410B from the first surface101of the interconnection structure layer100may be greater than a height H2of the first semiconductor devices300mounted on the second bump pads230. In order to set the height H1which is greater than the height H2, copper balls having a relatively long diameter may be used to form the TMBCs410B or a thickness of the third bump pads240may be increased. As a result, the lower ends410L of the TMBCs410B may be located at a level which is lower than surfaces301of the first semiconductor devices300. That is, the TMBCs410B may downwardly protrude from the first semiconductor devices300.

FIG. 15is a cross-sectional view illustrating a step of forming a molding layer450A on the first surface101of the interconnection structure layer100. The molding layer450A may be formed using a wafer molding process to cover the TMBCs410B and the first semiconductor devices300. The molding layer450A may be formed of a molding member such as an epoxy molding compound (EMC) material. For example, the EMC material may be heated up to a molding temperature of about 180 degrees Celsius to provide a liquid EMC material, and the liquid EMC material may be coated and molded on the first surface101of the interconnection structure layer100to cover the TMBCs410B and the first semiconductor devices300. The molded EMC material453may be cured by a post mold curing process to form the molding layer450A. The post mold curing process may be performed at a curing temperature of about 175 degrees Celsius, which is lower than the molding temperature. Since the copper balls of the TMBCs410B have a melting point which is higher than the molding temperature and the curing temperature, the TMBCs410B may possibly not be transformed even though the molding process and the post mold curing process are performed. General tin (Sn) based solder balls may have a relatively low melting point. Thus, if the TMBCs410B are formed of the tin (Sn) based solder balls without using the copper balls, the TMBCs410B may be transformed during the molding process and the post mold curing process. Accordingly, the TMBCs410B may be formed using the copper balls instead of the tin (Sn) based solder balls to provide stable ball connectors.

FIG. 16is a cross-sectional view illustrating a step of exposing surfaces410T of the TMBCs410B. Specifically, the molded material453comprising the molding layer450A on the first surface101of the interconnection structure layer100may be recessed to expose a portion of each of the TMBCs410B. While the molded material453is recessed, the exposed portions of the TMBCs410B may be removed to provide the exposed and flat surfaces410T of the TMBCs410B. The molding layer450A may be recessed using a grinding process to provide a molding layer450. In such a case, the lower ends410L of the TMBCs410B may be removed during the grinding process. As a result, the surfaces410T of the TMBCs410B may be exposed by removing a portion of the molding layer450A. Since the lower ends410L of the TMBCs410B are removed while the molding layer450A is recessed, the exposed surfaces410T of the TMBCs410B may have a flat surface profile. The molded material453may be recessed to form the molding layer450A exposing the surfaces301of the first semiconductor devices300. Since the surfaces301of the first semiconductor devices300are exposed after the molding layer450A is recessed, heat generated from the first semiconductor devices300may be efficiently radiated into an outside space. While the molding layer450A is recessed to provide the molding layer450, the first semiconductor devices300may be partially removed so that the exposed surfaces301of the first semiconductor devices300may be coplanar with a bottom surface451of the recessed molding layer450A. As a result, the exposed surfaces301of the first semiconductor devices300, a bottom surface451of the recessed surface of the molding layer450A, and the exposed and flat surfaces410T of the TMBCs410B may be coplanar with each other.

FIG. 17is a cross-sectional view illustrating a step of forming outer connectors420on the TMBCs410B. The outer connectors420may be bonded to the exposed surfaces410T of the TMBCs410B, respectively. Each of the outer connectors420may have a solder ball shape. The outer connectors420may be formed of a tin based solder material including tin (Sn), silver (Ag) and copper (Cu).

FIG. 18is a cross-sectional view illustrating a step of detaching the carrier wafer800from the interconnection structure layer100. The carrier wafer800may be detached from the interconnection structure layer100by reducing an adhesive strength of the temporary adhesive layer (810ofFIG. 17). For example, the carrier wafer800may be detached from the interconnection structure layer100by irradiating an ultraviolet (UV) ray onto the temporary adhesive layer (810ofFIG. 17) or by applying heat to the temporary adhesive layer (810ofFIG. 17). If the carrier wafer800is detached from the interconnection structure layer100, the second surface102of the interconnection structure layer100and the first bump pads250may be exposed.

FIG. 19is a cross-sectional view illustrating a step of disposing a second semiconductor device500, which may be microprocessor, on the second surface102of the interconnection structure layer100. Specifically, the second semiconductor device500may be bonded to the first bump pads250using second chip connectors650. The second chip connectors650may be conductive connection members such as micro-bumps. The second semiconductor device500may be electrically connected to the first semiconductor devices300through the first vertical interconnection portions (162ofFIG. 12). More specifically, the second semiconductor device500may be electrically connected to the first semiconductor devices300through the second chip connectors650, some (250A ofFIG. 12) of the first bump pad250, some of the first vertical interconnection portions (162ofFIG. 12) connecting the first patterns112of the first outer conductive trace patterns110to some of the second outer conductive trace patterns150, and some (230A ofFIG. 12) of the second bump pads230. The outer connectors420may be connected to the second vertical interconnection portions (163ofFIG. 12) which are disposed to vertically overlap the second semiconductor device500. The second semiconductor device500may be electrically connected to some of the outer connectors420through other second vertical interconnection portions (163ofFIG. 12) which are disconnected from the first semiconductors300. More specifically, the second semiconductor device500may be electrically connected to some of the outer connectors420through some of the second chip connectors650, some (250A ofFIG. 12) of the first bump pad250, some of the second vertical interconnection portions (163ofFIG. 12) connecting the second patterns113of the first outer conductive trace patterns110to some of the second outer conductive trace patterns150, and some (230A ofFIG. 12) of the second bump pads230.

Before the second semiconductor device500is bonded to the first bump pads250, the interconnection structure layer100and the molding layer450may be separated into a plurality of pieces by a die sawing process. The second semiconductor device500may be bonded to the first bump pads250of any one piece of the interconnection structure layer100to provide a semiconductor package10including the first and second semiconductor devices300and500attached to the first and second surfaces101and102of the interconnection structure layer100.

FIG. 20is a cross-sectional view illustrating a structure of the semiconductor package10according to an embodiment.FIG. 21is a cross-sectional view illustrating one of the first semiconductor devices300included in the semiconductor package10ofFIG. 20. The semiconductor package10shown inFIG. 20may be realized using the fabrication processes described with reference toFIGS. 1 to 19. In the semiconductor package10, the second semiconductor device500may be mounted on the second surface102of the interconnection structure layer100opposite to the first semiconductor device300. Since the second semiconductor device500is bonded to the first bump pads250through the second chip connectors650using a soldering process, the second semiconductor device500may be mounted on the second surface102of the interconnection structure layer100. The first semiconductor devices300may be disposed on the first surface101of the interconnection structure layer100. The first semiconductor devices300may be disposed side by side on the first surface101of the interconnection structure layer100. Since the first semiconductor devices300are bonded to the second bump pads230through the first chip connectors630using a soldering process, the first semiconductor devices300may be mounted on the first surface101of the interconnection structure layer100.

The second semiconductor device500may have a different function from the first semiconductor devices300, and the first and second semiconductor devices300and500may constitute a single unified system-in-package (CIP). The second semiconductor device500or each of the first semiconductor devices300may include a semiconductor substrate (not shown) such as a silicon substrate, active devices (not shown) such as transistors, and interconnection layers. The active devices may be formed on the semiconductor substrate, and the interconnection layers may be formed on the active devices and the semiconductor substrate. The interconnection layers may be formed to include an interlayer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer. The second semiconductor device500may be a logic device performing logical operations, and the first semiconductor devices300may be memory devices for storing data.

The second semiconductor device may be, for example, a central processing unit (CPU) or a graphic processing unit (GPU). The second semiconductor device500may be provided in a chip form or a package form including a molding member that protects a chip. The second semiconductor device500may be disposed on the second surface102of the interconnection structure layer100, and the first semiconductor devices300may be disposed on the first surface101of the interconnection structure layer100opposite to the second semiconductor device500. The second semiconductor device500may be vertically stacked on the first semiconductor devices300. The second semiconductor device500may signally communicate with the first semiconductor devices300through an interface physical layer (PHY). Since the second semiconductor device500is vertically stacked on the first semiconductor devices300, a length of signal paths between the second semiconductor device500and each of the first semiconductor devices300may be reduced to improve an operation speed of the semiconductor package10. If the second semiconductor device500includes a GPU and the first semiconductor devices300are memory devices, a length of signal paths between the second semiconductor device500and each of the first semiconductor devices300may be reduced to improve an image data processing speed of the semiconductor package10including the GPU.

As illustrated inFIG. 21, the first semiconductor device300may include a plurality of semiconductor dice310,300A,300B,300C and300D which are vertically stacked. For example, the master die310, the first slave die300A, the second slave die300B, the third slave die300C and the fourth slave die300D may be sequentially and downwardly stacked. The plurality of dice310,300A,300B,300C and300D may be electrically connected to each other by a through silicon via (TSV) structure including TSVs311,321A,321B and321C, internal interconnection lines312,322A,322B and322C, and connection bumps330. The first semiconductor device300may further include side molding part330M covering sidewalls of the slave dice300A,300B,300C and300D. A top surface300T of the fourth slave die300D opposite to the third slave die300C may be exposed to improve a heat emission efficiency of the semiconductor package10. The top surface300T of the fourth slave die300D may correspond to the top surface301(the lower surface as seen inFIG. 14) of the first semiconductor device300. A surface303of the master die310opposite to the slave dice300A,300B,300C and300D may also be exposed, and the first chip connectors630may be attached to the surface303of the master die310. The first semiconductor device300including the plurality of semiconductor dice310,300A,300B,300C and300D may be a high performance memory device such as a high bandwidth memory (HBM) device.

In the semiconductor package10, the TMBCs410B may be disposed on the first surface101of the interconnection structure layer100. The TMBCs410B may be disposed on the first surface101of the interconnection structure layer100to be adjacent to the first semiconductor devices300. In one example, the first and second bump pads (250and230ofFIG. 20) may be formed before the first semiconductor device300and the TMBCs410B may be mounted on first surface101of the interconnection structure layer100. Each of the TMBCs410B may include a copper ball. In some embodiments, each of the TMBCs410B may include a plurality of copper balls which are vertically stacked to have a pillar shape. The TMBCs410B may be bonded to the third bump pads240, respectively. Thus, the TMBCs410B may be electrically connected to the interconnection structure layer100through the third bump pads240.

In the semiconductor package10, the molding layer450may be provided to cover the first surface101of the interconnection structure layer100and to fill spaces between the TMBCs410B and the first semiconductor devices300. The outer connectors420may be attached to the TMBCs410B, respectively. The TMBCs410B may substantially penetrate the molding layer450to electrically connect the interconnection structure layer100to outer connectors420. The lower surfaces410T of the TMBCs410B may be exposed at a bottom surface of the molding layer450and may have a flat surface profile. The outer connectors420such as solder balls may be more readily attached to the lower surfaces410T of the TMBCs410B because the lower surfaces410T of the TMBCs410B are flat.

The interconnection structure layer100may include the signal paths160, that is, interconnection portions, disposed in a dielectric body. The interconnection portions160may include the horizontal interconnection portions161, each of which electrically connects one of the second bump pads230to one of the third bump pads240. The interconnection portions160may also include the first vertical interconnection portions162, each of which electrically connects one of the second bump pads230to one of the first bump pads250. In addition, the interconnection portions160may further include the second vertical interconnection portions163, each of which electrically connects one of the third bump pads240to one of the first bump pads250. The horizontal interconnection portions161may electrically connect the first semiconductor devices300to some of the outer connectors420, the first vertical interconnection portions162may electrically connect the first semiconductor devices300to the second semiconductor device500, and the second vertical interconnection portions163may electrically connect the second semiconductor device500to some of the outer connectors420.

The interconnection structure layer100of the semiconductor package10may be formed by depositing dielectric layers and conductive layers and by patterning the dielectric layers and the conductive layers. Thus, a thickness of the interconnection structure layer100may be reduced. This interconnection structure layer100may be formed using a fine patterning technique such as a wafer processing technique or a silicon processing technique. Accordingly, the interconnection portions160may be formed to include a plurality of interconnection lines having a fine pitch.

FIG. 22is a cross-sectional view of a portion of a defective semiconductor package in the event that TMBCs410corresponding to the TMBCs410B are formed of solder balls. Since the TMBCs410are disposed to substantially penetrate the molding layer450, it may be important to prevent generation of defects while the molding layer450is formed.

If the TMBCs410are formed of solder balls, the solder balls may come out of the molding layer450when the outer connectors (420ofFIG. 20) are attached to the solder balls410. The outer connectors (420ofFIG. 20) may be attached to the solder balls410using a solder reflow process. In such a case, the solder balls410may be melted and the molding layer450may be expanded. Thus, at least some of the solder balls410may undesirably come out of the molding layer450due to the heat generated by the solder reflow process and pressure applied to the solder balls410. This is because the solder balls410containing a tin based solder material may have a relatively low melting point of about 220 degrees Celsius. If at least one of the solder balls410is removed, a void410V may be provided in the molding layer450.

The loss of the solder balls410may cause a connection failure of the solder balls410. However, according to the embodiments, the TMBCs410may be formed of metal balls or solderless metal balls having a melting point which is higher than a melting point of a tin (Sn) material, and where solderless metal balls do not contain solder. Thus, it may prevent the void410V from being formed in the molding layer450. In some embodiments, the TMBCs410may be formed of metal balls having a melting point which is at least twice that of a tin (Sn) material. For example, each of the TMBCs410may be formed to include a copper ball. In such a case, the TMBCs410may also have a high electrical conductivity to reduce an electrical resistance of the TMBCs410. The copper ball may be coated by a nickel layer or a nickel solder layer.

FIG. 23is a cross-sectional view illustrating a semiconductor package20according to another embodiment. The semiconductor package20may be configured to include a package substrate700and the semiconductor package10(illustrated inFIGS. 19 and 20) mounted on the package substrate700. The package substrate700may electrically connect the semiconductor package10to an electronic product. The package substrate700may include connectors710such as solder balls. The package substrate700may be a printed circuit board (PCB). The semiconductor package20may further include a heat spreader750attached to the second semiconductor device500using a thermal interface material layer740. The heat spreader750may also be attached to the package substrate700using a stiffener730. The semiconductor package10may be disposed in a space which is surrounded by the heat spreader750, the stiffener730and the package substrate700.

FIG. 24is a block diagram illustrating an electronic system including a memory card7800including at least one semiconductor package according to an embodiment. The memory card1800includes a memory7810, such as a nonvolatile memory device, and a memory controller7820. The memory7810and the memory controller7820may store data or read stored data. The memory7810and/or the memory controller7820include at least one of the semiconductor packages according to some embodiments.

The memory7810may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG. 25is a block diagram illustrating an electronic system8710including at least one package according to an embodiment. The electronic system8710may include a controller8711, an input/output device8712, and a memory8713. The controller8711, the input/output device8712and the memory8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711or the memory8713may include one or more of the semiconductor packages according to embodiments of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen and so forth. The memory8713is a device for storing data. The memory8713may store data and/or commands to be executed by the controller8711, and the like.

The memory8713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. For example, a flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system and an information transmission/reception system.

If the electronic system8710is an equipment capable of performing wireless communication, the electronic system8710may be used in a communication system such as of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDAM (wideband code division multiple access), CDMA2000, LTE (long term evolution) and Wibro (wireless broadband Internet).