Multi-charge region memory cells for a vertical NAND device

A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.

FIELD

The present disclosure relates generally to the field of semiconductor devices and specifically to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of making the same.

BACKGROUND

Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory stack structure sometimes referred to as a Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.

SUMMARY

According to an aspect of the present disclosure, a memory device comprises a substrate having a major surface, and a first plurality of memory cells arranged in a first string extending in a first direction substantially perpendicular to the major surface of the substrate in a plurality of device levels. Each of the first plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate. A first select gate electrode is located between the major surface of the substrate and the first plurality of memory cells. A second select gate electrode is located above the first plurality of memory cells. Each memory cell in the first string further comprises a portion of a first control gate electrode extending in a second direction substantially parallel to the major surface, and a portion of a second control gate electrode extending in the second direction, located at a same level as the respective first control gate electrode, and spaced apart from the respective first control gate electrode in a third direction substantially parallel to the major surface and transverse to the second direction. For each memory cell in the first string, the respective first control gate electrode is electrically insulated from the respective second control gate electrode.

According to another aspect of the present disclosure, a method of reading a memory cell of a NAND memory device is provided. A first NAND string comprising a plurality of memory cells is provided. Each memory cell in the first NAND string comprises a portion of a first control gate electrode located adjacent to a first portion of a memory film and a portion of a second control gate electrode which is located adjacent to a second portion of the memory film. The second control gate electrode is electrically insulated from the first control gate electrode. A select read voltage of a first polarity type is applied to the first control gate electrode. An unselect read voltage of a second polarity type opposite to the first polarity type is applied to the second control gate electrode during the step of applying the select read voltage to the first control gate electrode.

According to yet another aspect of the present disclosure, a method of making a memory device is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. A trench is formed through the stack. The trench is filled with a separator insulating material. A memory opening is formed in the stack. The memory opening extends through the separator insulating material located in the trench. At least a portion of a memory film is formed in the memory opening. A semiconductor channel is formed in the memory opening over the at least the portion of the memory film.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods of making the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure.

The various three dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated employing the various embodiments described herein. The monolithic three dimensional NAND string is located in a monolithic, three dimensional array of NAND strings located over the substrate. At least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings.

Referring toFIG. 1, an exemplary device structure according to embodiments of the present disclosure is shown, which includes a 3D NAND stacked memory device. The exemplary device structure can be employed to incorporate any of the various embodiments for forming memory stack structures55according to the present disclosure. Each memory stack structure55can include at least a memory film50, a semiconductor channel60, and optionally a dielectric core62in case the semiconductor channel60does not fill the entire volume within the memory film50.

The exemplary device structure includes a substrate8, which can be a semiconductor substrate. Various semiconductor devices can be formed on, or over, the substrate8employing methods known in the art. For example, an array of memory devices can be formed in a device region100, and at least one peripheral device20can be formed in a peripheral device region200. Electrically conductive via contacts to the electrically conductive electrodes of the devices in the device region100can be formed in a contact region300.

The substrate8can include a substrate semiconductor layer10. The substrate semiconductor layer10is a semiconductor material layer, and can include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate8has a major surface9, which can be, for example, a topmost surface of the substrate semiconductor layer10. The major surface9can be a semiconductor surface. In one embodiment, the major surface9can be a single crystalline semiconductor surface.

As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5Ohm-cm to 1.0×105Ohm-cm, and is capable of producing a doped material having electrical conductivity in a range from 1 Ohm-cm to 1.0×105Ohm-cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a balance band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0 Ohm-cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5Ohm-cm. All measurements for electrical conductivities are made at the standard condition.

Optionally, select gate electrodes (not shown) can be formed within, or on top of, the substrate semiconductor layer10using any suitable methods for implementing the array of vertical NAND strings. For example, a lower select gate device level may be fabricated as described in U.S. patent application Ser. No. 14/133,979, filed on Dec. 19, 2013, U.S. patent application Ser. No. 14/225,116, filed on Mar. 25, 2014, and/or U.S. patent application Ser. No. 14/225,176, filed on Mar. 25, 2014, all of which are incorporated herein by reference. A source region12can be formed in a region of the substrate semiconductor layer10that is laterally offset from the memory stack structures55. Alternatively, a source region can be formed directly underneath memory stack structures55of memory cells, as described in U.S. patent application Ser. No. 14/317,274, filed on Jun. 27, 2014, which is incorporated herein by reference. A select transistor can be formed between the top of the substrate semiconductor layer10and the bottommost control gate of the memory devices.

At least one optional shallow trench isolation structure16and/or at least one deep trench isolation structure (not shown) may be employed to provide electrical isolation among various semiconductor devices on the substrate8. The at least one peripheral device20formed in the peripheral device region200can include any device known in the art and needed to support the operation of the semiconductor devices in the device region100. The at least one peripheral device20can include a driver circuit associated with the array of the memory devices in the device region100. The at least one peripheral device can comprise transistor devices in the driver circuit. In one embodiment, the at least one peripheral device can include one or more field effect transistors, each of which can include a source region201, a drain region202, a body region203(e.g., a channel region), a gate stack205, and a gate spacer206. The gate stack205can include any type of gate stack known in the art. For example, each gate stack205can include, from one side to another, a gate dielectric, a gate electrode, and an optional gate cap dielectric. Optionally, a planarization dielectric layer208including a dielectric material may be employed in the peripheral device region200to facilitate planarization of the portion of material stacks to be subsequently formed on the substrate8.

A stack of alternating layers of a first material and a second material different from the first material is formed over a top surface of the substrate8. In one embodiment, the first material can be an insulator material that forms insulator layers32, and the second material can be a conductive material that forms conductive line structures that can include control gate electrodes46, source-side select gate electrodes (not separately shown), and drain-side select gate electrodes (not separately shown). Alternatively, the first material can be an insulator material that forms insulator layers32, and the second material can be a sacrificial material that is deposited as sacrificial layers, and is at least partly replaced with a conductive material to form various conductive line structures after formation of memory stack structures55.

The memory stack structures55can be formed through the alternating stack (32,46) of the insulator layers32and the control gate electrodes46employing the various methods of the present disclosure to be described below. A drain region63can be formed on top of each semiconductor channel60. The control gate electrodes46can form terraced (stepped) structures within the contact region300in order to facilitate formation of contact via structures66. A contact region dielectric fill portion65may be optionally employed over the terraced structures of the control gate electrodes66. A dielectric liner64may be optionally formed around each contact via structure66to enhance electrical isolation of the contact via structures66. A hard mask layer36may be optionally employed to facilitate formation of the contact via structures66. Peripheral contact via structures86can be formed in the peripheral device region200. A source line76can be formed through the alternating stack (32,46) to provide electrical contact to the source region12. A dielectric spacer74can be employed to provide electrical isolation for the source line76. Subsequently, contacts (not shown) to the drain regions63can be formed, and bit lines (not shown) that overlie, and electrically shorted to, the drain regions63can be formed.

Referring toFIG. 2A, a cut-out portion of a first exemplary device structure according to a first embodiment of the present disclosure is illustrated at a processing step after formation of an alternating stack (32,42). The alternating stack (32,42) includes alternating layers of a first material and a second material different from the first material. In one embodiment, the alternating stack (32,42) can include insulator layers32composed of the first material, and sacrificial material layers42composed of a second material different from that of insulator layers32. The sacrificial material layers may comprise electrically conductive material which forms the control gate electrodes of the NAND string. Alternatively, the sacrificial material layers42may comprise electrically insulating or conductive sacrificial layers which are removed through the back side openings and replaced with metal control gate electrodes. The insulator layers32can comprise insulator layers that provide the functionality of electrical insulation, and the sacrificial material layers42can comprise sacrificial layers that are subsequently removed.

The first material can be at least one electrically insulating material. As such, each insulator layer32can be an insulating material layer. Electrically insulating materials that can be employed for the insulator layers32include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials.

The sacrificial material layers42can function as control gate electrodes made of at least one conductive material. In this case, each sacrificial material layer42can be a conductive material layer. Conductive materials that can be employed for the sacrificial material layers42that constitute the control gate electrodes include, but are not limited to, a doped semiconductor material, elemental metals, intermetallic alloys, conductive nitrides of at least one elemental metal, a silicate of at least one metal, conductive carbon allotropes, organic conductive materials, and combinations thereof. For example, the second material can be doped polysilicon, tungsten, tungsten nitride, tantalum, tantalum nitride, titanium, titanium nitride, cobalt, copper, aluminum, an alloy thereof, or a combination thereof. Alternatively, the sacrificial material layers42may comprise sacrificial layers, such as silicon nitride or polysilicon sacrificial layers. In this case, at least one, and/or each, of the sacrificial material layers42can be a sacrificial material layer. In an illustrative example, the sacrificial material layers42can be silicon nitride layers that can be subsequently removed, for example, by a wet etch employing phosphoric acid.

In one embodiment, the insulator layers32can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial layers or doped polysilicon or doped amorphous silicon layers that can be subsequently converted into doped polysilicon through a thermal anneal at an elevated temperature. The first material of the insulator layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulator layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42can be formed, for example, by physical vapor deposition (PVD; sputtering), chemical vapor deposition, electroplating, electroless plating, or combinations thereof.

The sacrificial material layers42can be suitably patterned to function as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. Each sacrificial material layer42may comprise a portion having a strip shape extending substantially parallel to the major surface9of the substrate8.

The thicknesses of the insulator layers32and the sacrificial material layers42can be in a range from 8 nm to 128 nm, although lesser and greater thicknesses can be employed for each insulator layer32and for each control gate electrode42. In one embodiment, the thicknesses of the insulator layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm. The number of repetitions of the pairs of a insulator layer32and a sacrificial material layer (e.g., control gate electrode or sacrificial material)42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes.

Referring toFIG. 2B, laterally-extending trenches39can be formed through the alternating stack (32,42). As used herein, a laterally-extending trench refers to a trench that includes a portion having a greater lateral extent along a lengthwise direction than along a widthwise direction. A laterally-extending trench may be a linear or curved, and may include multiple portions having different lengthwise directions, and may have the same width or undulating widths. The laterally-extending trenches39can be formed, for example, by application and patterning of a photoresist layer over the alternating stack (32,42), and transfer of the pattern in the patterned photoresist layer through the alternating stack (32,42) to the top surface of the substrate8(not shown; SeeFIG. 1) that is located at the bottom of the alternating stack (32,42). The laterally-extending trenches39laterally extend along a horizontal direction. In one embodiment, the laterally-extending trenches39can have a substantially uniform width, and can be parallel among one another. The laterally-extending trenches39can laterally divide the alternating stack (32,42) into a plurality of portions.

Referring toFIG. 2C, each laterally-extending trench39can be filled with another sacrificial material, which can be the same as, or different from, the second material. For example, the second material can be silicon nitride or polysilicon, and the sacrificial material deposited in the laterally-extending trenches39can be silicon nitride. Excess portions of the dielectric material can be removed from above the top surface of the alternating stack, for example, by chemical mechanical planarization (CMP), a recess etch, or a combination thereof. Remaining portions of the deposited dielectric material constitutes inter-electrode fill structures31. In one embodiment, the inter-electrode fill structures31can laterally separate various portions of the alternating stack (32,42).

Referring toFIG. 2D, a separator trench47can be formed between a neighboring pair of inter-electrode fill structures31. In one embodiment, a separator trench47can include sidewalls that are parallel to the sidewalls of the neighboring pair of inter-electrode fill structures31. In one embodiment, each separator trench47can have a uniform width throughout. Each separator trench47can vertically extend from the top surface of the alternating stack (32,42) to the top surface of the substrate8(not shown; SeeFIG. 1) that is located at the bottom of the alternating stack (32,42).

Referring toFIG. 2E, each separator trench47can be filled with a dielectric material that is different from the second material. The dielectric material that fills the separator trenches47is herein referred to as a separator insulating material. For example, the separator insulating material can be silicon oxide. Excess portions of the separator insulating material can be removed from above the top surface of the alternating stack, for example, by chemical mechanical planarization (CMP), a recess etch, or a combination thereof. Remaining portions of the deposited separator insulating material constitutes separator insulator structures43. In one embodiment, the separator insulator structures43can laterally separate various portions of the alternating stack (32,42).

Referring toFIG. 2F, another sacrificial material layer42and another insulator layer32can be sequentially deposited over the alternating stack (32,42) to increase the total number of layers within the alternating stack (32,42). The deposited sacrificial material layer42is a select gate sacrificial layer, which is subsequently replaced with select gate electrodes. The select gate sacrificial layer is deposited over an underlying insulator layer32, which is a separating insulator layer that subsequently separates select gate electrodes from underlying control gate electrodes. The deposited insulator layer32is herein referred to as an insulating cover layer.

Referring toFIG. 2G, a memory opening49can be formed through the alternating stack (32,42) by application of a photoresist layer over the alternating stack (32,42), lithographic patterning of the photoresist layer, and transfer of the pattern in the photoresist layer through the alternating stack (32,42) by an anisotropic etch such as a reactive ion etch. The photoresist layer can be subsequently removed, for example, by ashing. Each memory opening49extends through the insulating cover layer, i.e., the topmost insulator layer32, and through the select gate sacrificial layer, i.e., the topmost sacrificial material layer42, and the underlying alternating stack (32,42) of insulator layers32and sacrificial material layers42. Each memory opening49can vertically extend from the top surface of the alternating stack (32,42) to the top surface of the substrate8(not shown; SeeFIG. 1) that is located at the bottom of the alternating stack (32,42). Each memory opening49can be located between a pair of inter-electrode fill structures31and through a portion of a separator insulator structure43. In other words, a memory opening49can divide a separator insulator structure43into two physically disjoined portions. Each memory opening49in the alternating stack (32,42) can extend through the separator insulating material located in the separator trench47, i.e., through the remaining portions of the separator insulator structure43.

Referring toFIG. 2H, a memory stack structure55can be formed in each memory opening49. The memory stack structure55can include at least a portion of a memory film50, a semiconductor channel60, and optionally a dielectric core62. Each memory film50can include, from outside to inside, a blocking dielectric52, a charge storage region54, and a tunnel dielectric56. At least a portion of each memory film50is formed in a memory opening49(SeeFIG. 2G). Each semiconductor channel60is formed in a memory opening49and over the at least the portion of the memory film50.

Each blocking dielectric52can contact the sidewalls of the memory openings49. Specifically, the blocking dielectric can contact the sidewalls of the sacrificial layers42. The blocking dielectric52may include one or more dielectric material layers that can function as the dielectric material(s) of a control gate dielectric between the sacrificial layers42and a charge storage region to be subsequently formed. The blocking dielectric52can include silicon oxide, a dielectric metal oxide, a dielectric metal oxynitride, or a combination thereof. In one embodiment, the blocking dielectric52can include a stack of at least one silicon oxide layer and at least one dielectric metal oxide layer. The blocking dielectric52can be formed by a conformal deposition process such as chemical vapor deposition (CVD) and/or atomic layer deposition (ALD), and/or by deposition of a conformal material layer (such as an amorphous silicon layer) and subsequent conversion of the conformal material layer into a dielectric material layer (such as a silicon oxide layer). The thickness of the blocking dielectric52can be in a range from 6 nm to 24 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric52may be omitted from the memory opening, and instead be formed through the backside contact trench in recesses formed by removal of the sacrificial layers42prior to forming the metal control gate electrodes through the backside contact trench.

Each charge storage region54includes a dielectric charge trapping material, which can be, for example, silicon nitride, or a conductive material such as doped polysilicon or a metallic material. In one embodiment, the charge storage region54includes silicon nitride. The charge storage region54can be formed as a single charge storage region of homogeneous composition, or can include a stack of multiple charge storage material layers. The multiple charge storage material layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the charge storage region54may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage region54may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The charge storage region54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for the selected material(s) for the charge storage region. The thickness of the charge storage region54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Each semiconductor channel60can be formed on inner sidewalls of each memory film50by deposition of a semiconductor material layer and a subsequent anisotropic etch of the semiconductor material layer. The semiconductor material layer can include a doped polycrystalline semiconductor material (such as doped polysilicon), or can include a doped amorphous semiconductor material (such as amorphous silicon) that can be subsequently converted into a doped polycrystalline semiconductor material after a suitable anneal at an elevated temperature.

Optionally, a dielectric core62can be formed within a cavity inside each semiconductor channel60, for example, by deposition of a dielectric material such as silicon oxide, and subsequent planarization of the dielectric material. The planarization of the dielectric material removes the portion of the deposited dielectric material from above the top surface of the horizontal plane including the top surface of the alternating stack (32,42). The planarization of the dielectric material can be performed, for example, by chemical mechanical planarization. Each remaining portion of the dielectric material inside a memory opening constitutes a dielectric core62. The dielectric core62is an optional component, and a combination of a memory film50and a semiconductor channel60may completely fill a memory opening. A set of a memory film50, a semiconductor channel60, and a dielectric core62within a same memory opening constitutes a channel and memory structure55.

Referring toFIG. 2I, additional trenches can be formed through the topmost sacrificial material layer42and the topmost insulator layer32in areas of the inter-electrode fill structures31. The additional trenches are laterally-extending trenches, and can be formed, for example, by application and patterning of a photoresist layer over the topmost sacrificial material layer42and transfer of the pattern in the photoresist layer through the topmost sacrificial material layer42and the topmost insulator layer32by an anisotropic etch. In one embodiment, the pattern of the laterally-extending trenches through the topmost sacrificial material layer42and the topmost insulator layer32can be the same as the pattern of the inter-electrode fill structures31. The photoresist layer can be subsequently removed, for example, by ashing.

Back side trenches (79A,79B) can be formed on each side of the separator insulating material of the separator insulator structures43. In one embodiment, each back side trench can be formed in a same configuration as the back side trench ofFIG. 1within which a combination of a source line76and a dielectric spacer74is formed. In other words, each back side trench (79A,79B) can extend from the topmost surface of the alternating stack (32,42) to the top surface of the substrate8. A first back side trench79A can be formed on a first side of the separator insulating material of each separator insulator structure43, and a second back side trench79B can be formed on a second side of the separator insulating material of each separator insulator structure43.

Subsequently, the second material of the sacrificial material layers42can be removed selective to the first material of the insulator layers32to form control gate electrodes46. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material. An etchant that removes the second material of the sacrificial material layers42selective to the first material of the insulator layers32can be introduced through the back side trenches (79A,79B) to laterally etch the second material of the sacrificial material layers42and to form back side recesses. For example, the sacrificial material layers42can be removed through the first and the second back side trenches (79A,79B) to form respective first and second back side recesses. Upper select gate back side recesses can be formed in volumes from which the topmost sacrificial material layer42is removed. Lower select gate back side recesses can be formed in volumes from which the bottommost sacrificial material layer42is removed.

Referring toFIG. 2J, the back side recesses can be filled with a conductive material, for example, by chemical vapor deposition to form the control gate electrodes46, drain-side select gate electrodes48, and source-side select gate electrodes44. First electrically conductive control gate layers can be formed in the first back side recesses through the first back side trench. The first electrically conductive control gate layers can include, for example, a first control gate electrode461and a third control gate electrode473illustrated inFIG. 3A. Second electrically conductive control gate layers can be formed in the second back side recesses through the second back side trench. The second electrically conductive control gate layers can include, for example, a second control gate electrode462and a fourth control gate electrode474illustrated inFIG. 3A.

An upper select gate layer can be formed in the upper select gate back side recess through the first and the second back side trenches (79A,79B) such that the upper select gate layer surrounds the at least a portion of the memory film50located in the memory opening. The upper select gate layer includes drain-side select gate electrodes48. A lower select gate layer can be formed in the lower select gate back side recess through the first and the second back side trenches (79A,79B) such that separate lower select gate layers are located on opposite sides of the at least a portion of the memory film50located in the memory opening. The lower select gate layer includes source-side select gate electrodes44.

The separator insulating material of a separator insulator structure43electrically insulates each first electrically conductive control gate layer from a respective second electrically conductive control gate layer located in a same device level. A first source line76(SeeFIG. 1) can be formed in each first back side trench79A, and a second source line76(SeeFIG. 1) can be formed in each second back side trench79B.

A pair of source-side select gate electrodes44can be formed for each memory stack structure55. A first lower select gate layer44A can be formed in a bottommost first back side recess through the first back side trench, and a second lower select gate layer44B can be formed in another bottommost second back side recess through the second back side trench. The separator insulating material of a separator insulator structure43electrically insulates the first lower select gate layer44A from the second lower select gate layer44B.

The first exemplary device structure ofFIG. 2Jcan be incorporated into the exemplary device structure ofFIG. 1. The exemplary device structure ofFIG. 1that incorporates the first exemplary device structure ofFIG. 2Jis schematically illustrated inFIGS. 3A-3D.

Referring toFIGS. 3A-3D, a pair of source-side select gate electrodes44, pairs of control gate electrodes46, and a drain-side select gate electrode48can be provided around each memory stack structure55. The substrate8can have a major surface9. A first plurality of memory cells can be arranged in a first string, as embodied within a memory stack structure55and portions of gate electrodes in proximity thereto, extending in a first direction substantially perpendicular to the major surface9of the substrate8in a plurality of device levels. Each device level corresponds to the control gate electrodes46spaced from the major surface9by a same separation distance. Each of the first plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate8.

A second plurality of memory cells can be arranged in a second string extending in the first direction, i.e., the vertical direction, and spaced apart from the first string in the second direction, i.e., a horizontal direction. The first and the second strings can extend through the insulating material between the first and the second control gate electrodes. The first and the second strings can share the first and the second select gate electrodes, i.e., the lower select gate electrodes44and the upper gate electrodes48. The substrate8can comprise a silicon substrate. Each string of memory devices can be embodied as a memory stack structure55and portions of gate electrodes in proximity thereto, which is a monolithic three dimensional NAND string that can be located in a monolithic, three dimensional array of NAND strings located over the silicon substrate. At least one memory cell in the first device level of the three dimensional array of NAND strings can be located over another memory cell in the second device level of the three dimensional array of NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon.

At least one first select gate electrode, i.e., the source-side select gate electrodes44, can be located between the major surface9of the substrate8and the first plurality of memory cells. At least one second select gate electrode, i.e., the drain-side select gate electrodes48, can be located above the first plurality of memory cells. Each memory cell in the first string can comprise a portion of a first control gate electrode461extending in a second direction (i.e., a horizontal direction along the lengthwise direction of the control gate electrodes46) substantially parallel to the major surface9, and a portion of a second control gate electrode462extending in the second direction, located at a same level as the respective first control gate electrode461, and spaced apart from the respective first control gate electrode461in a third direction substantially parallel to the major surface9and transverse to the second direction. For each memory cell in the first string, the respective first control gate electrode461is electrically insulated from the respective second control gate electrode462by a separator insulator structure43.

Each memory cell comprises a first portion of a memory film50(SeeFIG. 1) which is located between the first control gate electrode461and a first portion of a semiconductor channel60, and a second portion of the memory film50which is located between the second control gate electrode462and a second portion of the semiconductor channel60. At least one end portion of the semiconductor channel60extends substantially perpendicular to the major surface9of a substrate8. The memory film50can comprise a blocking dielectric52(SeeFIG. 2H) in contact with the first and the second control gate electrodes (461,462), at least one charge storage region that is a portion of the charge storage region54in contact with the blocking dielectric52, and a tunnel dielectric56located between the at least one charge storage region and the semiconductor channel60.

Locations of upper select gate contacts85are schematically illustrated inFIG. 3B. The upper select gate electrodes48are located on the upper side of the word line array. The upper select gate electrodes48can be divided and individually controlled per memory opening array. The word lines can be in a comb configuration. The word line terrace can be in the contact region300, which is the location for word line contacts. The lower select gate electrodes44can be divided in a comb configuration. The operating voltages of the lower select gate electrodes44can be the same for all lower select gate electrodes44.

The exemplary device structure can include a stack comprising a plurality of control gate electrodes46extending in the second direction. The plurality of control gate electrodes46comprise the first and second control gate electrodes (461,462) located in a first device level, and third and fourth control gate electrodes (473,474) located in a second device level located over the major surface9of the substrate8and below the first device level. The stack further comprises an interlevel insulator layer, i.e., an insulator layer32, located between the first and the second control gate electrodes (461,462) in the first device level and the third and the fourth control gate electrodes (473,474) located in the second device level. The insulating material of the dielectric core62can be located in a separator trench47(SeeFIG. 2D), i.e., the memory opening, in the stack, and can separate the stack into a first portion and a second portion.

The exemplary device structure can include a device region100comprising a first plurality of memory cells, in which each memory cell is embodied in a memory stack structure55and portions of gate electrodes in proximity thereto. The exemplary device structure can further include a first stepped contact region300located on a first side of the device region100and a second stepped contact region400located on a second side of the device region100opposite to the first side. A first control gate electrode461for each memory stack structure55can comprise a first prong of a first word line, and a second control gate electrode462for each memory stack structure can comprise a second prong of a second word line. Bit lines96laterally extending in directions different from the lengthwise directions of the control gate electrodes46are electrically connected to a set of memory stack structures55,

Referring toFIG. 3B, the semiconductor channel60within each memory stack structure55extends through a second select gate electrode, i.e., an upper select gate electrode48, which comprises a select line having a contact85in the device region100.

Referring toFIG. 3C, a first word line can comprise a comb shaped word line410having a terrace contact portion412located in the first stepped contact region300and a plurality of prongs (461,463,465) extending from the terrace contact portion412into the device region100. The second word line can comprise a comb shaped word line420having a terrace contact portion422located in the second stepped contact region400and a plurality of prongs (462,464,466) extending from the terrace contact portion422into the device region100. The prongs (461,463,465) of the first word line410can be interdigitated with the prongs (462,464,466) of the second word line420. Each prong (461,462,463,464,465,466) of the word lines (410,420) can be control gate electrodes. The semiconductor channel60(SeeFIG. 2H) and the memory film50(SeeFIG. 2H) can be located between the first control gate electrode461and the second control gate electrode462.

Referring toFIG. 3D, a first select gate electrode, such as a first lower select gate electrode441, can comprise a prong of a first select line. The first select line can comprise a comb shaped select line430having a terrace contact portion432located in the first stepped contact region300and a plurality of prongs (441,443,445) extending from the terrace contact portion432into the device region100below the plurality of control gate electrodes46. A second lower select gate electrode442can comprise a prong of a second select line located between the major surface9of the substrate8and the first plurality of memory cells. The second select line can comprise a comb shaped select line450having a terrace contact portion452located in the second stepped contact region400and a plurality of prongs (442,444,446) extending from the terrace contact portion452into the device region100. The prongs of the first select line can be interdigitated with the prongs of the second select line. A semiconductor channel60(SeeFIG. 1) is located between the first select gate electrode441and the second select gate electrode442.

The exemplary device comprises a plurality of semiconductor channels60(SeeFIG. 1) and memory films50(SeeFIG. 1) extending in the first direction between the first and the second control gates electrodes (461,462).

Referring toFIG. 4A, the first control gate electrode461can be located in the first portion of the stack, and the second control gate electrode462can be located in the second portion of the stack. The second control gate electrode462can be insulated from the first control gate electrode461by the insulating material located in a separator trench47, i.e., a separator insulator structure43(SeeFIGS. 2D and 2E).

As shown inFIG. 4A. the first portion50A of the memory film50can be electrically connected to the second portion50B of the memory film50, and the first portion of the semiconductor channel60(i.e., the portion of the semiconductor channel that contacts the first portion50A of the memory film50) can be electrically connected to the second portion of the semiconductor channel60(i.e., the portion of the semiconductor channel that contacts the second portion50B of the memory film50). In one embodiment, the semiconductor channel60comprises a cylindrical hollow body surrounding a dielectric core62. The memory film50comprises a cylindrical hollow body surrounding the semiconductor channel60. The memory film50, the semiconductor channel60, and the dielectric core62together comprise a pillar, i.e., a memory stack structure55, which extends in the first direction (e.g., the vertical direction) through the insulating material of the separator insulator structure43located in the separator trench47. The first portion50A of the memory film50contacts the first control gate electrode461, and the second portion50B of the memory film50contacts the second control gate electrode462.

The NAND memory device can comprise a substrate8having a major surface9. The first plurality of memory cells are arranged in the first NAND string extending in a first direction substantially perpendicular to the major surface9of the substrate8in a plurality of device levels. Each of the first plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate8. A first select gate electrode, e.g., a lower select gate electrode44, is located between the major surface9of the substrate8and the first plurality of memory cells, and a second select gate electrode, e.g., an upper select gate electrode48, is located above the first plurality of memory cells. The first control gate electrode461extends in a second direction substantially parallel to the major surface9, and the second control gate electrode462extends in the second direction and spaced apart from the respective first control gate electrode in a third direction substantially parallel to the major surface9and transverse to the second direction. Each memory cell can comprise a first portion50A of a memory film50which is located between the first control gate electrode461and a first portion of a semiconductor channel60, and a second portion50B of the memory film50which is located between the second control gate electrode and a second portion of the semiconductor channel60. The first portion50A of the memory film50is electrically connected to the second portion50B of the memory film50, and the first portion of the semiconductor channel60is electrically connected to the second portion of the semiconductor channel60.

Each memory cell500within a memory stack structure55comprises a multi-level program cell, i.e., a multi-charge storage state cell, having multiple states such as an unprogrammed state illustrated inFIG. 4Aand a plurality of (such as the illustrated three) distinct programmed states illustrated inFIGS. 4B-4D. In the unprogrammed state, electrical charges are substantially absent in a first portion50A of the memory film50that contacts the first control gate electrode461, and are substantially absent in a second portion50B of the memory film that contacts the second control gate electrode50B462. In a first programmed state, electrical charges are substantially absent in a first portion50A of the memory film50that contacts the first control gate electrode461, and are present in a second portion50B of the memory film that contacts the second control gate electrode462. In a second programmed state, electrical charges are present in a first portion50A of the memory film50that contacts the first control gate electrode461, and are substantially absent in a second portion50B of the memory film that contacts the second control gate electrode462. In a third programmed state, electrical charges are present in a first portion50A of the memory film50that contacts the first control gate electrode461, and are present in a second portion50B of the memory film that contacts the second control gate electrode462.

Referring toFIG. 5, a circuit schematic of the array region of the first exemplary device structure is illustrated. The circuit schematic represents a plurality of NAND strings. Each NAND string comprises a plurality of memory cells. Each memory cell in the NAND string comprises a portion of a first control gate electrode461(SeeFIGS. 4A-4D) located adjacent to a first portion50A of a memory film50and a portion of a second control gate electrode462which is located adjacent to a second portion50B of the memory film50. The second control gate electrode462is electrically insulated from the first control gate electrode461.

Referring toFIGS. 3A-3D, 4A-4D, and 5collectively, each memory cell500of the NAND memory device can be read by applying a select read voltage of a first polarity type to the first control gate electrode461, and by applying an unselect read voltage of a second polarity type opposite to the first polarity type to the second control gate electrode462during the step of applying the select read voltage to the first control gate electrode461. For example, the select read voltage can comprise a positive voltage used to read a programmed first portion of the memory cell containing the first portion50A of the memory film50, and the unselect read voltage comprises a negative voltage which inhibits a read current from flowing through the second portion of the memory film located in an erased second portion50B of the memory cell50.

In a non-limiting illustrative example, a read operation of on a memory cell can be performed by applying a voltage of about 3.0 V to a selected upper select gate electrode USG, a voltage of about 0 V to an unselected upper select gate electrode, a selected-line read voltage of about 4.0 V to a selected word line (e.g., WL1/410) connected to the selected control gate electrode (e.g., a first control gate electrode461), an unselected-same-level-line read voltage of about −3.0 V to the unselected control gate electrode (e.g., WL2/420) within a pair of control gate electrodes for the memory cell at the same level (e.g., a second control gate electrode462), and an unselected-different-level-line read voltage of about 7.0 V to all other control gate electrodes46located at different levels. A voltage of about 3.0 V can be applied to the selected lower select gate electrode (e.g., LSG1/430), and a voltage of about 3.0 V can be applied to the unselected lower select gate electrode (e.g., LSG2/450) connected to the same memory stack structure55(SeeFIG. 1). A voltage of about 0 V is applied to unselected lower select gate electrodes48connected to the different memory stack structure55. A voltage of about 1.0 V can be applied to the selected bit line BL/96, and a voltage of about 0 V can be applied to the unselected bit lines (not shown). The source line SL/76can be biased at about 0 V. The various voltages can be scaled and/or adjusted as needed. Unselected word lines (e.g., WL2/420) in the same level as the selected control gate electrode461can be set at a voltage of the opposite polarity as the selected-line read voltage (e.g., a negative voltage of about −3.0 V) to suppress leak current along the intermediate and opposite area of selected word line (e.g., WL1/410) during the read operation.

In a non-limiting illustrative example, a programming operation of on a memory cell can be performed by applying a voltage of about 3.0 V to a selected upper select gate electrode USG, a voltage of about 0 V to an unselected upper select gate electrode, a selected-line programming voltage of about 20 V to a selected word line (e.g., WL1/410) connected to the selected control gate electrode (e.g., a first control gate electrode461), and an unselected programming voltage of about 7.0 V to all unselected control gate electrodes (e.g., WL2/420). A voltage of about 0 V can be applied to all lower select gate electrode (e.g., LSG1/430, LSG2/450). A voltage of about 0 V can be applied to the selected bit line BL/96, and a voltage of about 3.0 V can be applied to the unselected bit lines (not shown). The source line SL/76can be biased at about 3.0 V.

In a non-limiting illustrative example, an erase operation of on a memory cell can be performed by applying a voltage of about 12.0 V to all upper select gate electrodes USG, an erase word line voltage of about 0 V to all word lines. A voltage of about 12.0 V can be applied to all lower select gate electrode (e.g., LSG1/430, LSG2/450). A voltage of about 20 V can be applied to all bit lines BL/96. The source line SL/76can be biased at about 20 V.

Referring toFIGS. 6A and 6B, a cut-out portion of a second exemplary device structure according to a second embodiment of the present disclosure is illustrated. An array region of a second exemplary device structure is illustrated. The second exemplary device structure is a portion of an array region that can be embedded within the exemplary device structure ofFIG. 1. An alternating stack (32,42) of insulator layers32and sacrificial material layers42is formed over a substrate8. The alternating stack (32,42) can be the same as in the first embodiment. The bottommost sacrificial material layer32may have a plurality of lower insulating separators25embedded therein. The lower insulating separators25provide electrical isolation between various lower select gate electrodes to be subsequently formed.

An upper select gate electrode layer and another insulator layer32can be sequentially formed. The upper select gate electrode layer can be another sacrificial material layer42, or can be a conductive material layer including a conductive material such as doped polysilicon. The upper select gate electrode layer may have a plurality of upper insulating separators45embedded therein. The upper insulating separators45provide electrical isolation between various upper select gate electrodes to be subsequently formed. Separator trenches47can be formed through the topmost insulator layer32, the upper select gate electrode layer, and the alternating stack (32,42) of insulator layers32and sacrificial material layers42. The separator trenches47can be formed, for example, by application and patterning of a photoresist layer over the topmost insulator layer32, and transfer of the pattern in the patterned photoresist layer through the topmost insulator layer32, the upper select gate electrode layer, and the alternating stack (32,42) to the top surface of the substrate8(e.g., the top surface of the substrate semiconductor layer10or an etch stop layer, if present) that is located at the bottom of the alternating stack (32,42). The separator trenches47laterally extend along a horizontal direction. In one embodiment, the separator trenches47can have a substantially uniform width, and can be parallel among one another. The separator trenches47can laterally divide the alternating stack (32,42) into a plurality of portions. If the select gate electrode layer includes a conductive material, the remaining portions of the select gate electrode layer can constitute an upper select gate electrode48.

Referring toFIGS. 7A and 7B, the processing steps ofFIG. 2Ecan be performed to fill each separator trench47with a dielectric material that is different from the second material. Excess portions of the dielectric material can be removed from above the top surface of the alternating stack, for example, by chemical mechanical planarization (CMP), a recess etch, or a combination thereof. Remaining portions of the deposited dielectric material constitutes separator insulator structures43. In one embodiment, the separator insulator structures43can laterally separate various portions of the alternating stack (32,42).

Referring toFIGS. 8A and 8B, memory openings49can be formed through the topmost insulator layer32, the upper select gate electrodes48, and the alternating stack (32,42) by application of a photoresist layer over the topmost insulator layer32, lithographic patterning of the photoresist layer, and transfer of the pattern in the photoresist layer through the topmost insulator layer32, the upper select gate electrodes48, and the alternating stack (32,42) by an anisotropic etch such as a reactive ion etch. The photoresist layer can be subsequently removed, for example, by ashing. Each memory opening49extends through the insulating cover layer, i.e., the topmost insulator layer32, and through the upper select gate electrodes48, and the underlying alternating stack (32,42) of insulator layers32and sacrificial material layers42. Each memory opening49can vertically extend from the top surface of the alternating stack (32,42) to the top surface of the substrate8(e.g., the top surface of the substrate semiconductor layer10or an etch stop layer, if present) that is located at the bottom of the alternating stack (32,42). Each memory opening49can extend through a portion of a separator insulator structure43. In other words, a memory opening49can divide a separator insulator structure43into two physically disjoined portions. Each memory opening49in the alternating stack (32,42) can extend through the separator insulating material located in the separator insulator structures43, and divides a separator insulator structure43into two laterally disjoined portions.

Referring toFIGS. 9A and 9B, at least a portion of a memory film50is formed in each memory opening. For example, a blocking dielectric layer can be formed in the memory opening, at least one charge storage region can be formed in the memory opening, and a tunnel dielectric can be formed in the memory opening. In one embodiment, the at least one charge storage region can comprises a charge trapping dielectric layer. A blocking dielectric52, a charge storage region54, a tunnel dielectric56, and a first semiconductor channel portion601can be sequentially formed. Each of the blocking dielectric52, the charge storage region54, and the tunnel dielectric56can be the same as in the first embodiment. The first semiconductor channel portion601can be a first material portion employed to form a semiconductor channel60(SeeFIG. 1). Each stack of a blocking dielectric52, a charge storage region54, a tunnel dielectric56, and a first semiconductor channel layer can be formed, for example, by depositing, and subsequently anisotropically etching, a stack including a blocking dielectric layer, a charge storage material layer, a tunnel dielectric layer, and a first semiconductor channel layer. Optionally, a first amorphous carbon cover layer can be formed over the first semiconductor channel layer prior to the anisotropic etching process, and can be removed after the anisotropic etching process. The first semiconductor channel layer can be a doped semiconductor material layer or an undoped semiconductor material layer. For example, the first semiconductor channel layer can be a doped polysilicon layer or an undoped polysilicon layer. A top surface of the substrate semiconductor layer10can be physically exposed at the bottom of each memory opening49after the anisotropic etch.

Referring toFIGS. 10A and 10B, an optional second semiconductor channel layer602L can be deposited on the physically exposed top surfaces of the substrate semiconductor layer10and sidewalls of the first semiconductor channel portions601and over the topmost insulator layer32. The second semiconductor channel layer602L can be a doped semiconductor material layer or an undoped semiconductor material layer. For example, the second semiconductor channel layer602L can be a doped polysilicon layer or an undoped polysilicon layer. In one embodiment, the second semiconductor channel layer602L does not completely fill the cavity in each memory opening. In another embodiment, the second semiconductor channel layer602L completely fills the cavities in the memory openings.

Referring toFIGS. 11A and 11B, a photoresist layer67can be applied over the second semiconductor material layer62L and can be lithographically patterned to form openings therein. At least one opening in the patterned photoresist layer can have a shape that straddles a memory opening and overlies two separator insulator structures43that adjoin the memory opening. Further, the shape has a width that is less than the width of the underlying memory opening along a horizontal direction that is perpendicular to the horizontal direction passing through centers of the two separator insulator structures43. Specifically, the width of the shape of an opening can be selected such that a lateral stack of a portion of a blocking dielectric52, a portion of a charge storage region54, a portion of a tunnel dielectric56, a portion of a first semiconductor channel portion601, and a portion of the second semiconductor channel layer602L is present on each side of the area defined by the shape of the opening. In one embodiment, each opening in the photoresist layer67may have a lengthwise direction that is parallel to the horizontal direction passing through centers of the two separator insulator structures43. In one embodiment, each opening in the photoresist layer67may be of rectangular shape or of elliptical shape.

At each memory opening, a separation opening69can be formed through the semiconductor channel60and the memory film50to separate the semiconductor channel60and the memory film50into a first portion and a second portion along a direction parallel to the separating insulating material of the separator insulator structures43. Each separation opening69can be formed underneath each opening in the photoresist layer67by etching through portions of the second semiconductor channel layer602L and the separator insulator structures43that underlie the openings employing an anisotropic etch, which can be a reactive ion etch. If the memory openings are filled with the second semiconductor channel layer602L, the anisotropic etch can be a non-selective etch that etches the semiconductor material of the second semiconductor channel layer602L and the dielectric material of the separator insulator structures43at approximately the same etch rate. Alternatively, multiple etch chemistries may be employed to form the separation openings69. Optionally, a first amorphous carbon cover layer can be formed over the first semiconductor channel layer prior to the anisotropic etching process, and can be removed after the anisotropic etching process.

Each stack of a blocking dielectric52, a charge storage region54, a tunnel dielectric56, a first semiconductor channel portion601, and a vertical portion of the second semiconductor channel layer602L within a memory opening is physically divided into two laterally separated stacks. Each of the laterally separated stacks include a blocking dielectric52, a charge storage region54, a tunnel dielectric56, a first semiconductor channel portion601, and a vertical portion of the second semiconductor channel layer602L. The lateral separation distance between the disjoined pair of stacks of a blocking dielectric52, a charge storage region54, a tunnel dielectric56, a first semiconductor channel portion601, and a vertical portion of the second semiconductor channel layer602L can be the same as the width of the separation opening69therebetween. Each separation opening69can extend at least from the top surface of the topmost insulator layer32to the top surface of the substrate semiconductor layer10. Subsequently, the photoresist layer67can be removed, for example, by ashing.

Referring toFIGS. 12A and 12B, a dielectric core162can be formed within each core cavity69, for example, by deposition of a dielectric material such as silicon oxide, and subsequent planarization of the dielectric material. The planarization of the dielectric material removes the portion of the deposited dielectric material from above the top surface of the horizontal plane including the top surface of the alternating stack (32,42). The planarization of the dielectric material can be performed, for example, by chemical mechanical planarization. The top portion of the second semiconductor channel layer602L can be removed during the planarization process. Each remaining portion of the second semiconductor channel layer602L constitutes a second semiconductor channel portion602. Each adjoining pair of a first semiconductor channel portion601and a second semiconductor channel portion602can be a portion of a semiconductor channel, which may optionally further include a horizontal top portion of the substrate semiconductor layer10. Each remaining portion of the dielectric material inside a memory opening constitutes a dielectric core162. A combination of a portion of the dielectric core162and a pair of combinations of a memory film50and a semiconductor channel60may completely fill the volume of a memory opening as formed at the processing step ofFIGS. 8A and 8B. Thus, two memory elements can be formed per memory opening at each level.

Subsequently, the second material of the sacrificial material layers42can be removed selective to the first material of the insulator layers32to form control gate electrodes46, and optionally lower select gate electrodes and/or upper select gate electrodes48. The processing steps ofFIG. 2Jof the first embodiment may be employed to form the control gate electrodes46, and optionally lower select gate electrodes and/or upper select gate electrodes48.

The separator insulating material of the separator insulator structures43electrically insulates each first electrically conductive control gate layer from a respective second electrically conductive control gate layer located in a same device level. Further, each dielectric core162laterally contacts a pair of separator insulator structures43, and provides electrical isolation between a pair of memory elements located at the same level and in, and around, the same memory opening. A source line76(SeeFIG. 1) can be formed in each back side trench79employed to fill the back side recesses formed by removal of the sacrificial material layers42.

The second exemplary device structure ofFIGS. 12A and 12Bcan be incorporated into the exemplary device structure ofFIG. 1or derivatives therefrom.FIG. 13illustrates the second exemplary device structure upon such incorporation. Each portion of the sacrificial material layers42can be replaced with a conductive electrode46, which can include, for example, an optional conductive liner46A (including, for example, titanium nitride) and a conductive fill material portion46B (including, for example, tungsten). A drain region63can be formed at a top end of each combination of a memory film50and a semiconductor channel60. Contact via structures92can be formed on each drain region63, and bit lines96can be formed directly on the contact via structures92to access the drain regions63. A pair of semiconductor channels60can be formed in each memory opening over at least a portion of the pair of memory films50.

Source-side select transistors120may be provided in the exemplary device structure. Within each memory opening, a first portion of a memory film50located on the first side of the dielectric core162is electrically insulated from a second portion of the memory film50located on the second side of the dielectric core162. Within each memory opening, the dielectric core162electrically insulates a first portion of the semiconductor channel60located on the first side of the dielectric core162from a second portion of the semiconductor channel60located on the second side of the dielectric core162.

Referring toFIGS. 14A and 14B, a cut-out portion of an array region of a third exemplary device structure is shown, which can be the same as the second exemplary device structure ofFIGS. 6A and 6B.

Referring toFIGS. 15A and 15B, the processing steps ofFIGS. 7A and 7Bare performed to form separator insulator structures43by filling the separator trenches47with a separator insulator material.

Referring toFIGS. 16A and 16B, the processing steps ofFIGS. 8A and 8Bare performed to form memory openings49. The shape and sizes of the memory openings49can be selected such that the memory openings49do not merge with one another upon a selective expansion process to be subsequently employed. In one embodiment, the horizontal cross-sectional area of each memory opening49can be elliptical or roughly polygonal (e.g., roughly square or rectangular with rounded corners) In one embodiment, each memory opening49can extend through the entire thickness of the separator insulator material of the separator insulator structures43. Each memory opening49can separate a separator insulator structure43into two physically disjoined portions.

Referring toFIGS. 17A-17C, front side recesses49A are formed in the sacrificial material layers42through the memory openings49. The front side recesses49A can be formed, for example, by a selective etch process in which the sacrificial material of the sacrificial material layer42is etched selective to the insulator material of the insulator layers32. Optionally, the selective etch process can be selective to the conductive material of the upper select gate electrodes48. The selective etch process laterally recesses the sidewalls of the sacrificial material layer42farther away from each memory opening49than sidewalls of adjoining insulator layers32. The distance of the lateral recess for the front side recesses49A can be selected such that the front side recesses49A from neighboring memory openings49do not merge after termination of the selective etch process. In one embodiment, the front side recesses49A can have an annular shape.

Referring toFIGS. 18A-18C, a blocking dielectric layer52L can be formed in the memory opening49by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The dielectric material of the blocking dielectric layer52L can be the same as the dielectric material of the blocking dielectric52inFIG. 2H. The thickness of the blocking dielectric layer52L can be selected such that the front side recesses49A are not filled by the blocking dielectric layer52L. In one embodiment, the thickness of the blocking dielectric layer52L can be in a range from 6 nm to 24 nm, although lesser and greater thicknesses can also be employed.

Subsequently, a charge storage layer54L can be deposited on the surfaces of the blocking dielectric layer52L. The charge storage layer54L can have the same composition as, or can have a different composition from, the charge storage region54inFIG. 2H. The charge storage layer54L can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The charge storage layer54L of the third embodiment can include a conductive material or a dielectric material. In one embodiment, the charge storage layer54L can include a floating gate material, which can be a conductive material such as at least one metal and/or a doped polysilicon. In another embodiment, the charge storage layer54L can be a charge trapping dielectric layer such as a silicon nitride layer. The thickness of the charge storage layer54L can be selected such that the front side recesses49A are filled by the charge storage layer54L without completely filling a center portion of each memory opening49. The thickness of the charge storage layer54L, as measured on vertical surfaces of the blocking dielectric layer52L outside of the front side recesses49A, can be in a range from 3 nm to 60 nm, although lesser and greater thicknesses can also be employed. Thus, a cavity49′ is present at a center portion of each memory opening49after the charge storage layer54L fills the front side recesses49A of the memory opening49.

Referring toFIGS. 19A-19C, the portions of the blocking dielectric layer52L and the charge storage layer54L that do not underlie the topmost insulator layer32can be removed by an etch process, which can be an anisotropic etch, an isotropic etch, or a combination of an anisotropic etch and an isotropic etch. The cavity49′ within each memory opening expands by the volume of the removed portions of the blocking dielectric layer52L and the charge storage layer54L so that the volume of the cavity49′ is equal to, or greater than, the original volume of the memory opening49as formed at the processing steps ofFIGS. 16A and 16B. The sidewall surfaces of the insulator layers32and the upper select gate electrodes48can be physically exposed after the etch process.

Each remaining portion of the blocking dielectric layer52L constitutes a blocking dielectric52. Each remaining portion of the charge storage layer54L constitutes a charge storage region54. A pair of mutually disjoined blocking dielectrics52is present at each level of a memory opening. A pair of mutually disjoined charge storage regions54is present at each level of the memory opening. Each blocking dielectric52contacts sidewall surfaces of two separator insulator structures43. Each charge storage region54is spaced from the separator insulator structures43by a blocking dielectric52. Each blocking dielectric52can have a convex outer surface and a concave inner surface. Surfaces of each blocking dielectric52are physically exposed to a cavity49′. The blocking dielectrics52are formed in the front side recesses49A of through the memory opening. In one embodiment, the charge storage regions54can be a plurality of floating gates.

Referring toFIGS. 20A-20C, a tunnel dielectric56and a first semiconductor channel portion601can be formed within each cavity49′. Each tunnel dielectric56can have the same composition as the tunnel dielectric56illustrated inFIG. 2H. The first semiconductor channel portions601can include a doped semiconductor material or an undoped semiconductor material. For example, each first semiconductor channel portions601can be a doped polysilicon portion or an undoped polysilicon portion. An anisotropic etch can be performed. A top surface of the substrate semiconductor layer10can be physically exposed at the bottom of each memory opening49after the anisotropic etch. In one embodiment, the charge storage regions54can be a plurality of floating gates. In this case, the tunnel dielectric56can be formed in the memory opening over the plurality of floating gates.

Referring toFIGS. 21A-21C, a second semiconductor channel layer602L can be deposited on the physically exposed top surfaces of the substrate semiconductor layer10and sidewalls of the first semiconductor channel portions601and over the topmost insulator layer32. The second semiconductor channel layer602L can be a doped semiconductor material layer or an undoped semiconductor material layer. For example, the second semiconductor channel layer602L can be a doped polysilicon layer or an undoped polysilicon layer. In one embodiment, the second semiconductor channel layer602L does not completely fill the cavity in each memory opening. In another embodiment, the second semiconductor channel layer602L completely fills the cavities in the memory openings.

Referring toFIGS. 22A-22C, the processing steps ofFIGS. 11A and 11Bcan be performed. Each tunnel dielectric56, each first semiconductor channel portion601, and each vertical portion of the second semiconductor channel layer602L within a memory opening is physically divided into two laterally separated stacks. Each of the laterally separated stacks include a blocking dielectric52, a charge storage region54, a tunnel dielectric56, a first semiconductor channel portion601, and a vertical portion of the second semiconductor channel layer602L. The lateral separation distance between the disjoined pair of stacks of a blocking dielectric52, a charge storage region54, a tunnel dielectric56, a first semiconductor channel portion601, and a vertical portion of the second semiconductor channel layer602L can be the same as the width of the separation opening therebetween. Each separation opening can extend at least from the top surface of the topmost insulator layer32to the top surface of the substrate semiconductor layer10. Subsequently, the photoresist layer can be removed, for example, by ashing.

Subsequently, the processing steps ofFIGS. 12A and 12Bcan be performed. A dielectric core162can be formed within each core cavity employing the same methods as in the second embodiment. Each remaining portion of the second semiconductor channel layer602L constitutes a second semiconductor channel portion602. Each adjoining pair of a first semiconductor channel portion601and a second semiconductor channel portion602can be a portion of a semiconductor channel60, which may optionally further include a horizontal top portion of the substrate semiconductor layer10. Each remaining portion of the dielectric material inside a memory opening constitutes a dielectric core162. A combination of a portion of the dielectric core162and a pair of combinations of a memory film50and a semiconductor channel60may completely fill the volume of a memory opening. Thus, two memory elements can be formed per memory opening at each level.

Subsequently, the second material of the sacrificial material layers42can be removed selective to the first material of the insulator layers32to form control gate electrodes46, and optionally lower select gate electrodes and/or upper select gate electrodes. The processing steps ofFIG. 2Jof the first embodiment may be employed to form the control gate electrodes46, and optionally lower select gate electrodes and/or upper select gate electrodes48.

The separator insulating material of the separator insulator structures43electrically insulates each first electrically conductive control gate layer from a respective second electrically conductive control gate layer located in a same device level. Each dielectric core162provides electrical isolation between a pair of memory elements located at the same level and in, and around, the same memory opening. A source line76(SeeFIG. 1) can be formed in each back side trench79employed to fill the back side recesses formed by removal of the sacrificial material layers42.

The third exemplary device structure ofFIGS. 22A-22Ccan be incorporated into the exemplary device structure ofFIG. 1or derivatives therefrom.FIG. 23illustrates the third exemplary device structure upon such incorporation. Each portion of the sacrificial material layers42can be replaced with a conductive electrode46. A drain region63can be formed at a top end of each combination of a memory film50and a semiconductor channel60. Contact via structures92can be formed on each drain region63, and bit lines96can be formed directly on the contact via structures92to access the drain regions63. A pair of semiconductor channels60can be formed in each memory opening over at least a portion of the pair of memory films50.

Source-side select transistors120may be provided in the exemplary device structure. Within each memory opening, a first portion of a memory film50located on the first side of the dielectric core162is electrically insulated from a second portion of the memory film50located on the second side of the dielectric core162. Within each memory opening, the dielectric core162electrically insulates a first portion of the semiconductor channel60located on the first side of the dielectric core162from a second portion of the semiconductor channel60located on the second side of the dielectric core162.

In one embodiment, a first portion of the memory film50can comprises a first blocking dielectric52A and a first charge storage region54A which are located in a recess in the first portion of the stack. The first portion of the memory film50can further comprise a first tunnel dielectric56A which together with the first portion60A of the semiconductor channel60comprise a first pillar which extends in the first direction through the insulating material of the insulator layers32located in the trench defined by the memory opening. The second portion of the memory film50can comprise a second blocking dielectric52B and a second charge storage region54B which are located in a recess in the second portion of the stack. The second portion of the memory film50further comprises a second tunnel dielectric56B which together with the second portion60B of the semiconductor channel60comprise a second pillar which extends in the first direction through the insulating material located in the trench. The dielectric core162is located between the first pillar and the second pillar, and the dielectric core162electrically insulates and physically separates the first pillar from the second pillar. Further, the dielectric core162is located between the first charge storage region54A and the second charge storage region54B, and the dielectric core162electrically insulates and physically separates the first charge storage region54A from the second charge storage region54B. The first blocking dielectric52A contacts the first control gate electrode461, and the second blocking dielectric52B contacts the second control gate electrode462.

In one embodiment, each of the first charge storage region54A and the second charge storage region54B can be a floating gate dielectric. In another embodiment, each of the first charge storage region54A and the second charge storage region54B can be a charge trapping dielectric.

In one embodiment, the dielectric core162comprises a pillar having a cylindrical central portion and wing portions extending in the second direction from the central portion as illustrated inFIGS. 22A and 22C. The cylindrical central portion may have a circular, elliptical, polygonal, or rounded polygonal horizontal cross-sectional shape. The first pillar and the second pillar can extend partially coaxially around the central portion of the dielectric core162such that the first pillar is separated from the second pillar by the wing portions of the dielectric core162.

Referring toFIG. 24, a circuit schematic is shown, which can be a circuit schematic of the array region of the second or third exemplary device structure. The circuit schematic represents a plurality of NAND strings. Each NAND string comprises a plurality of memory cells. Each memory cell in the NAND string comprises a portion of a first control gate electrode461(SeeFIG. 23) located adjacent to a first portion50A of a memory film50and a portion of a second control gate electrode462which is located adjacent to a second portion50B of the memory film50. The second control gate electrode462is electrically insulated from the first control gate electrode461.

Referring toFIGS. 23 and 24collectively, each memory cell of the NAND memory device can be read by applying a select read voltage of a first polarity type to the first control gate electrode461, and by applying an unselect read voltage of a second polarity type opposite to the first polarity type to the second control gate electrode462during the step of applying the select read voltage to the first control gate electrode461. For example, the select read voltage can comprise a positive voltage used to read a programmed first portion of the memory cell containing the first portion50A of the memory film50, and the unselect read voltage comprises a negative voltage which inhibits a read current from flowing through the second portion of the memory film located in an erased second portion50B of the memory cell50.

The NAND memory device can comprise a substrate8having a major surface9. The first plurality of memory cells are arranged in the first NAND string extending in a first direction substantially perpendicular to the major surface9of the substrate8in a plurality of device levels. Each of the first plurality of memory cells is positioned in a respective one of the plurality of device levels above the substrate8. A first select gate electrode, e.g., a lower select gate electrode44, is located between the major surface9of the substrate8and the first plurality of memory cells, and a second select gate electrode, e.g., an upper select gate electrode48, is located above the first plurality of memory cells. The first control gate electrode extends in a second direction substantially parallel to the major surface9, and the second control gate electrode extends in the second direction and spaced apart from the respective first control gate electrode in a third direction substantially parallel to the major surface9and transverse to the second direction. Each memory cell can comprise a first portion50A of a memory film50which is located between the first control gate electrode461and a first portion of a semiconductor channel60, and a second portion50B of the memory film50which is located between the second control gate electrode and a second portion of the semiconductor channel60. The first portion50A of the memory film50is electrically isolated from the second portion50B of the memory film50. The core dielectric162electrically isolates the first portion of the semiconductor channel60from the second portion of the semiconductor channel60. A first word line can comprise a comb shaped word line WLL/410having a terrace contact portion (not shown) located in the first stepped contact region (not shown) and a plurality of prongs (461,463,465,467) extending from a terrace contact portion into the device region. The second word line can comprise a comb shaped word line WLR/420having a terrace contact portion (not shown) located in the second stepped contact region (not shown) and a plurality of prongs (462,464,466,468) extending from the terrace contact portion into the device region.

In a non-limiting illustrative example, a read operation of on a memory cell in a memory opening (e.g., MH1, MH2, MH3, MH4) can be performed by applying a voltage of about 6.8 V to a selected upper select gate electrode (e.g., SGDL/481), a voltage of about 0 V to an unselected upper select gate electrode (e.g., SGDR/482), a selected-line read voltage of about 0 V to a selected word line (e.g., WLL/410) connected to the selected control gate electrode (e.g., a first control gate electrode461), and an unselected-line read voltage of about 8 V to unselected word lines (e.g., WLR/420) connected to unselected control gate electrodes (including a second control gate electrode462). A voltage of about 6.8 V can be applied to the selected lower select gate electrode (e.g., SGSL/430), and a voltage of about 0 V can be applied to the unselected lower select gate electrode (e.g., SGSR/450) connected to the same memory stack structure55(SeeFIG. 1). A voltage of about 1.3 V can be applied to the selected bit line (e.g., BL1), and a voltage of about 0 V can be applied to the unselected bit lines (e.g., BL2, BL3, BL4). The source line SL/76can be biased at about 0.8 V. The various voltages can be scaled and/or adjusted as needed.

In a non-limiting illustrative example, a programming operation of on a memory cell can be performed by applying a voltage of about 2.5 V to a selected upper select gate electrode (e.g., SGDL/481), a voltage of about 0 V to an selected upper select gate electrode (e.g., SGDR/482), a selected-line programming voltage of about 20 V to a selected word line (e.g., WLL/410) connected to the selected control gate electrode (e.g., a first control gate electrode461), and an unselected programming voltage of about 8.5 V to unselected word lines (e.g., WLR/420) connected to unselected control gate electrodes. A voltage of about 0 V can be applied to the selected lower select gate electrode (e.g., SGSL/430), and a voltage of about 2.5 V can be applied to unselected lower select gate electrodes SGSR/450. A voltage of about 0 V can be applied to the selected bit line (e.g., BL1), and a voltage of about 2.5 V can be applied to the unselected bit lines (e.g., BL2, BL3, BL4). The source line SL can be biased at about 2.5 V.

In a non-limiting illustrative example, an erase operation of on a memory cell can be performed by applying about 0 V to the selected word line (e.g., WLL/410), about 23 V to the substrate semiconductor layer10, and OV volt to all bit lines (BL1, BL2, BL3, BL4)/96. The various unselected word lines and the source line SL/76can be electrically floating.