SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0119870, filed on Sep. 22, 2022, in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

The inventive concepts relate to a semiconductor device and a method of manufacturing the same.

BACKGROUND

In an electronic system requiring data storage needs, a high capacity semiconductor device may be used that may store large amounts of data. Thus, a method of increasing the data storage capacity of semiconductor devices has been studied. For example, a semiconductor device including memory cells that may be 3-dimensionally stacked has been suggested.

If a division pattern for electrically insulating memory blocks from each other in the semiconductor device has a large area, the integration degree of the semiconductor may be diminished, and if the division pattern has a small area, the electrical interference between the memory blocks may increase.

SUMMARY

Example embodiments provide a semiconductor device having improved characteristics.

Example embodiments provide a method of manufacturing a semiconductor device having improved characteristics.

According to an aspect of the inventive concept, there is provided a semiconductor device. The semiconductor device may include a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure may include gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes may extend in a second direction substantially parallel to the upper surface of the substrate. The first division pattern may extend on the substrate in the second direction through the gate electrode structure, and the first division pattern may divide the gate electrode structure in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The memory channel structure may extend through the gate electrode structure on the substrate, and may include a channel extending in the first direction and a charge storage structure on an outer sidewall of the channel. The first division pattern may include first and second sidewalls opposite to each other in the third direction. First recesses may be spaced apart from each other in the second direction on the first sidewall of the first division pattern, and second recesses may be spaced apart from each other in the second direction on the second sidewall of the first division pattern. The first recesses may not overlap the second recesses in the third direction.

According to an aspect of the inventive concept, there is provided a semiconductor device. The semiconductor device may include a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure may include gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes may extend in a second direction substantially parallel to the upper surface of the substrate. The first division pattern may extend on the substrate in the second direction through the gate electrode structure, and may divide the gate electrode structure in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The memory channel structure may extend through the gate electrode structure on the substrate, and may include a channel extending in the first direction and a charge storage structure on an outer sidewall of the channel. The first division pattern may include first and second sidewalls opposite to each other in the third direction. First recesses may be spaced apart from each other in the second direction on the first sidewall of the first division pattern, and second recesses may be spaced apart from each other in the second direction on the second sidewall of the first division pattern. Distances in the second direction between the first recesses may periodically change. Distances in the second direction between the second recesses may periodically change.

According to an aspect of the inventive concept, there is provided a semiconductor device. The semiconductor device may include a lower circuit pattern, a common source plate (CSP), a gate electrode structure, first division patterns, and a memory channel structure. The lower circuit pattern may be formed on a substrate. The CSP may be formed on the lower circuit pattern. The gate electrode structure may include gate electrodes spaced apart from each other on the CSP in a first direction substantially perpendicular to an upper surface of the substrate, and each of the gate electrodes may extend in a second direction substantially parallel to the upper surface of the substrate. Each of the first division patterns may extend on the CSP in the second direction through the gate electrode structure, and may divide the gate electrode structure in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The memory channel structure may extend through the gate electrode structure on the substrate, and may include a channel extending in the first direction and a charge storage structure on an outer sidewall of the channel. The first division pattern may include first and second sidewalls opposite to each other in the third direction. The first recesses may be spaced apart from each other in the second direction on the first sidewall of the first division pattern, and second recesses may be spaced apart from each other in the second direction on the second sidewall of the first division pattern. The first recesses may not overlap the second recesses in the third direction.

According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device. In the method, a mold layer may be formed on a substrate. First holes and second holes may be formed through the mold layer. A memory channel structure may be formed in each of the first holes. The second holes may be connected with each other by enlarging widths of the second holes to form a first opening. A portion of the mold layer may be removed through the first opening to form a gap. A gate electrode may be formed in the gap. A first division pattern may be formed in the first opening. Each of the second holes may have a shape of a triangle or a triangle with chamfered or rounded vertices in a plan view.

According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device. In the method, a mold layer may be formed on a substrate. First holes and second holes may be formed through the mold layer. A memory channel structure may be formed in each of the first holes. The second holes may be connected with each other by enlarging widths of the second holes to form an opening. A portion of the mold layer may be removed through the opening to form a gap. A gate electrode may be formed in the gap. A division pattern may be formed in the opening. Each of the second holes may have a “T” shape in a plan view.

According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device. In the method, a mold layer may be formed on a substrate. First holes and second holes may be formed through the mold layer. A memory channel structure may be formed in each of the first holes. The second holes may be connected with each other by enlarging widths of the second holes to form an opening. A portion of the mold layer may be removed through the opening to form a gap. A gate electrode may be formed in the gap. A first division pattern may be formed in the opening. The opening may include first and second sidewalls opposite to each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. First protrusion portions may be formed to be spaced apart from each other in the second direction on the first sidewall of the opening, and second protrusion portions may be formed to be spaced apart from each other in the second direction on the second sidewall of the opening. Each of the first and second protrusion portions may protrude toward a center of the opening. The first protrusion portions may not overlap the second protrusion portions in the third direction.

According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device. In the method, a mold layer may be formed on a substrate. First holes and second holes may be formed through the mold layer. A memory channel structure may be formed in each of the first holes. The second holes may be connected with each other by enlarging widths of the second holes to form an opening. A portion of the mold layer may be removed through the opening to form a gap. A gate electrode may be formed in the gap. A first division pattern may be formed in the opening. The opening may include first and second sidewalls opposite to each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. First protrusion portions may be formed to be spaced apart from each other in the second direction on the first sidewall of the opening, and second protrusion portions may be formed to be spaced apart from each other in the second direction on the second sidewall of the opening. Each of the first and second protrusion portions may protrude toward a center of the opening. Distances in the second direction between the first protrusion portions may periodically change, and distances in the second direction between the second protrusion portions may periodically change.

In the semiconductor device in accordance with example embodiments, the division pattern for separating the gate electrodes from each other may have a relatively small area, and thus the integration degree of the semiconductor device including the division pattern may be enhanced. Additionally, the recesses on the opposite sidewalls of the division pattern may be formed in a zigzag pattern in an extension direction of the division pattern, so that the electrical interference between portions of the gate electrodes in the recesses may be reduced.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device, a method for manufacturing the same, and a mass data storage system including the semiconductor device in accordance with example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

In the specification (and not necessarily in the claims), a vertical direction substantially perpendicular to an upper surface of a substrate may be referred to as a first direction D1, and two directions crossing each other among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as second and third directions D2 and D3, respectively. In example embodiments, the second and third directions D2 and D3 may be substantially perpendicular to each other.

FIGS.1to7are plan views and cross-sectional views illustrating a semiconductor device, for example, a vertical channel NAND flash memory device in accordance with example embodiments.

Particularly,FIGS.1to3are the plan views,FIG.4is a cross-sectional view taken along line A-A′ ofFIG.2,FIG.5includes cross-sectional views taken along lines B-B′ and C-C′ ofFIG.2,FIG.6is a cross-sectional view taken along line D-D′ ofFIG.2, andFIG.7is a cross-sectional view taken along line E-E′ ofFIG.2.FIGS.2to7are drawings about region X inFIG.1, andFIGS.3A and3Bare enlarged plan views of region W ofFIG.2.FIG.3Aillustrates a third division pattern in accordance with example embodiments, andFIG.3Billustrates a third division pattern in accordance with a comparative embodiment.

FIG.2does not show some elements to avoid the complexity of the drawing.

Referring toFIGS.1to7, the semiconductor device may include a lower circuit pattern, a common source plate (CSP), a gate electrode structure, first to fourth division patterns330,470,620and625, an insulation pattern structure600, a memory channel structure462, a dummy memory channel structure464, first to eighth upper contact plugs632,634,636,682,684,686,688and690, a through via950, and first to fifth upper wirings632,634,636,682,684,686,688and690on a substrate100.

Additionally, the semiconductor device may include a support layer300, a support pattern305, a sacrificial layer structure290, a channel connection pattern510, a second blocking pattern615, first and fourth insulation patterns315and650, and first to ninth insulating interlayers150,170,340,350,980,990,640,670and700.

In example embodiments, the substrate100may include a first region I and a second region II bordering or surrounding the first region I.

The first region I may be a cell array region, and the second region II may be a pad region or an extension region. The first and second regions I and II of the substrate100may form a cell region. Particularly, memory cells each of which includes a gate electrode, a channel and a charge storage structure may be formed on the first region I of the substrate100, and upper contact plugs for applying electrical signals to the memory cells and pads of the gate electrodes contacting the upper contact plugs may be formed on the second region II of the substrate100.FIG.1shows that the second region II of the substrate100entirely surrounds the first region I of the substrate100in a plan view thereof, however, embodiments of the inventive concept may not be limited thereto, and for example, the second region II of the substrate100may be formed only at opposite sides of the first region I of the substrate100in the second direction D2.

In some embodiments, the substrate100may further include a third region surrounding the second region II in a plan view thereof, and upper circuit patterns for applying electrical signals to the memory cells through the upper contact plugs may be formed on the third region of the substrate100.

The substrate100may include a field region on which an isolation pattern110is formed, and an active region101on which no isolation pattern is formed. The isolation pattern110may include an oxide, e.g., silicon oxide.

In example embodiments, the semiconductor device may have a cell over periphery (COP) structure. That is, the lower circuit pattern may be formed on the substrate100, and the memory cells, the upper contact plugs and the upper circuit pattern may be formed over the lower circuit pattern. The lower circuit pattern may include, e.g., transistors, lower contact plugs, lower wirings, lower vias, etc.

For example, first and second transistors may be formed on the second and first regions II and I, respectively, of the substrate100. The first transistor may include a first lower gate structure142on the substrate100, and first and second impurity regions102and103at upper portions, respectively, of the substrate100adjacent to the first lower gate structure142, which may serve as source/drains, respectively. The second transistor may include a second lower gate structure146on the substrate100, and third and fourth impurity regions106and107at upper portions, respectively, of the substrate100adjacent to the second lower gate structure146, which may serve as source/drains, respectively.

The first lower gate structure142may include a first lower gate insulation pattern122and a first lower gate electrode132stacked on the substrate100, and the second gate structure146may include a second lower gate insulation pattern126and a second lower gate electrode136stacked on the substrate100.

The first insulating interlayer150may be formed on the substrate100, and may be on and at least partially cover the first and second transistors. First, second, fourth and fifth lower contact plugs162,163,168and169may extend through the first insulating interlayer150to contact the first to fourth impurity regions102,103,106and107, respectively, and a third lower contact plug164may extend through the first insulating interlayer150to contact the first lower gate electrode132. In some embodiments, a sixth lower contact plug (not shown) may extend through the first insulating interlayer150to contact the second lower gate electrode136.

First to fifth lower wirings182,183,184,188and189may be formed on the first insulating interlayer150to contact upper surfaces of the first to fifth lower contact plugs162,163,164,168and169, respectively. A first lower via192, a sixth lower wiring202, a third lower via212and an eighth lower wiring222may be sequentially stacked on the first lower via182, and a second lower via196, a seventh lower wiring206, a fourth lower via216and a ninth lower wiring226may be sequentially stacked on the fourth lower wiring188.

The second insulating interlayer170may be formed on the first insulating interlayer150, and may be on and at least partially cover the first to ninth lower wiring182,183,184,188,189,202,206,222and226, and the first to fourth lower vias192,196,212and216.

Each of the first and second insulating interlayers150and170may include an oxide, e.g., silicon oxide.

The CSP240may be formed on the second insulating interlayer170. The CSP240may include, e.g., polysilicon doped with n-type impurities. Alternatively, the CSP240may include a metal silicide layer and a doped polysilicon layer sequentially stacked. The metal silicide layer may include, e.g., tungsten silicide.

The sacrificial layer structure290, the channel connection pattern510, the support layer300and the support pattern305may be formed on the CSP240.

The channel connection pattern510may be formed on the first region I of the substrate100, and the sacrificial layer structure290may be formed on the second region II of the substrate100. The channel connection pattern510may include an air gap515therein.

The support layer300may be formed on the channel connection pattern510and the sacrificial layer structure290, and may also be formed in a first opening302extending through the channel connection pattern510and the sacrificial layer structure290to expose an upper surface of the CSP240, which may be referred to as the support pattern305.

The support pattern305may have various layouts in a plan view. For example, a plurality of support patterns305may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the substrate100, the support pattern305may extend in the third direction D3 on a portion of the second region II of the substrate100adjacent to the first region I of the substrate100, and a plurality of support patterns305each of which may extend in the second direction D2 may be spaced apart from each other in the third direction D3 on the second region II of the substrate100.FIG.4shows the support pattern305extending in the third direction D3 on the portion of the second region II of the substrate100adjacent to the first region I of the substrate100.

The channel connection pattern510may include polysilicon doped with n-type impurities or undoped polysilicon. The sacrificial layer structure290may include first, second and third sacrificial layers260,270and280sequentially stacked in the first direction D1. Each of the first and third sacrificial layers260and280may include an oxide, e.g., silicon oxide, and the second sacrificial layer270may include a nitride, e.g., silicon nitride. The support layer300and the support pattern305may include a material having an etching selectivity with respect to the first to third sacrificial layers260,270and280, e.g., polysilicon doped with n-type impurities.

The gate electrode structure may include gate electrodes at a plurality of levels spaced apart from each other in the first direction D1 on the support layer300and the support pattern305. Each of the gate electrodes may extend in the second direction D2. The first insulation pattern315may be formed between the gate electrodes, and between the gate electrode and the support layer300or the support pattern305. The first insulation pattern315may include an oxide, e.g., silicon oxide.

In example embodiments, the gate electrode structure may include first, second and third gate electrodes752,754and756sequentially stacked in the first direction D1. The first gate electrode752may be formed at one or two levels, the second gate electrodes754may be formed at a plurality of levels, respectively, and the third gate electrode756may be formed at one or two levels.FIGS.4to7show that the first gate electrode752is formed at one level and the third gate electrode756is formed at two levels, however, embodiments of the inventive concept may not be limited thereto.

In example embodiments, the first gate electrode752may serve as a ground selection line (GSL), the second gate electrode754may serve as a word line, and the third gate electrode756may serve as a string selection line (SSL).

The gate electrode structure may further include a gate electrode that may be used for erasing data stored in the memory channel structure462using a gate induced drain leakage (GIDL) phenomenon, which may be referred to as a GIDL gate electrode. In an example embodiment, the GIDL gate electrode may be formed at a level lower than that of the first gate electrode752and at a level higher than that of the third gate electrode756in the first direction D1. Alternatively, the GIDL gate electrode may be formed at a level between that of the second gate electrode754and that of the third gate electrode756and at the level lower than that of the first gate electrode752in the first direction D1.

In example embodiments, the gate electrode structure may have a staircase shape in which lengths in the second direction D2 decreases in the first direction D1 from a lowermost level toward an uppermost level, and may include steps arranged in the second direction D2 on the second region II of the substrate100. The gate electrode structure may further include steps arranged in the third direction D3 on the second region II of the substrate100.

Hereinafter, a portion of the gate electrode structure corresponding to the step, that is, an end portion of each of the gate electrodes that is not overlapped by upper ones of the gate electrodes may be referred to as a pad. Thus, the pad of each of the gate electrodes may be formed on the second region II of the substrate100.

The gate electrode structure may include first pads having a relatively large length in the second direction D2 and second pads having a relatively small length in the second direction D2. The numbers of the first pads and the second pads may not be limited.

Each of the first to third gate electrodes752,754and756may include a gate conductive pattern and a gate barrier pattern on and at least partially covering a surface of the gate conductive pattern. The gate conductive pattern may include a metal having a low resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and the gate barrier pattern may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

In example embodiments, a plurality of gate electrode structures may be spaced apart from each other in the third direction D3. The third division pattern620may be formed on the CSP240between neighboring ones of the gate structures in the third direction D3. The third division pattern620may extend in the second direction D2 on the first and second regions I and II of the substrate100.

The fourth division pattern625may extend through the gate electrode structure in the second direction D2 on the first region I of the substrate100and a portion of the second region II of the substrate100adjacent to the first region I of the substrate100. Unlike the third division pattern620, the fourth division pattern625may not extend to an end portion of the second region II of the substrate100, and a plurality of fourth division patterns625may be spaced apart from each other in the second direction D2 on the second region II of the substrate100.

However, the fourth division pattern625may extend from the first region I of the substrate100to a portion of the second region II of the substrate100overlapping the third gate electrodes756in the first direction D1, and thus the third gate electrode756may be divided by the fourth division pattern625.

The third gate electrode756may be further divided by the second division pattern470extending through an upper portion of the gate structure, e.g., upper two levels at which the third gate electrodes756are formed to the portion of the second region II of the substrate100overlapping the third gate electrodes756in the first direction D1.

FIG.3Ashows a third hole490(refer toFIGS.12to14) for forming the third division pattern620, and description of the third division pattern620may also apply to the fourth division pattern625.

Referring toFIG.3A, the third division pattern620in accordance with example embodiments may have a bar shape extending in the second direction D2, and fourth recesses621may be formed at each of opposite sidewalls in the third direction D3.

That is, the third division pattern620may be formed, as described below with reference toFIGS.12to24, in a third opening493that may be formed by forming the third holes490, each of which may have a shape of a triangle in a plan view, spaced apart from each other in the second direction D2 by a first distance S1, and enlarging horizontal widths of the third holes490through an etching process so that the third holes490may be connected with each other. The fourth recess621having a sharp shape may be formed at a portion of each of opposite sidewalls in the third direction D3 of the third division pattern620adjacent to a vertex of the triangle shape of each of the third holes490.

In example embodiments, a plurality of fourth recesses621may be spaced apart from each other in the second direction D2 on each of opposite sidewalls in the third direction D3 of the third division pattern620, and neighboring two ones of the fourth recesses621in the second direction D2 may form a fourth recess pair. In example embodiments, a plurality of fourth recess pairs may be spaced apart from each other in the second direction D2 on each of opposite sidewalls in the third direction D3 of the third division pattern620, and the fourth recess pairs on the opposite sidewalls in the third direction D3 of the third division pattern620may be arranged in a zigzag pattern in the second direction D2, and may not overlap each other in the third direction D3.

Thus, a second distance S2 between neighboring ones of the fourth recesses621in the third direction D3 may have a relatively large value. Accordingly, electrical interference between portions of the gate electrodes at opposite sidewalls, respectively, in the third direction D3 of the third division pattern620, particularly, portions of the gate electrodes adjacent to the fourth recesses621having the sharp shape to which an electric field may be concentrated at the respective opposite sidewalls in the third direction D3 of the third division pattern620may be reduced.

For the convenience of explanation, the opposite sidewalls in the third direction D3 of the third division pattern620may be referred to as first and second sidewalls, respectively, and ones of the fourth recesses spaced apart from each other in the second direction D2 on the first sidewall of the third division pattern620may be referred to as sixth recesses, and ones of the fourth recesses spaced apart from each other in the second direction D2 on the second sidewall of the third division pattern620may be referred to as sixth recesses.

In example embodiments, the sixth recesses may be spaced apart from each other by a fifth distance and sixth distance alternately in the second direction D2, and the sixth distance may be greater than the fifth distance. Additionally, the seventh recesses may be spaced apart from each other by a seventh distance and eighth distance alternately in the second direction D2, and the eighth distance may be greater than the seventh distance.

That is, the sixth recesses spaced apart from each other in the second direction D2 by the fifth distance may form a sixth recess pair, and the sixth recess pairs may be spaced apart from each other in the second direction D2 by the sixth distance. Additionally, the seventh recesses spaced apart from each other in the second direction D2 by the seventh distance may form a seventh recess pair, and the seventh recess pairs may be spaced apart from each other in the second direction D2 by the eighth distance.

Thus, distances between the sixth recesses may be periodically changed in the second direction D2 to have the fifth distance and the sixth distance, and distances between the seventh recesses may be periodically changed in the second direction D2 to have the seventh distance and the eighth distance.

In example embodiments, the fifth and seventh distances may be substantially equal to each other, and the sixth and eighth distances may be substantially equal to each other.

Referring toFIG.3B, a fifth division pattern622in accordance with the comparative embodiment may be formed in a fifth opening that may be formed by forming fifth holes624, each of which may have a shape of a circle in a plan view, spaced apart from each other in the second direction D2 by a third distance S3, and enlarging horizontal widths of the fifth holes624through an etching process so that the fifth holes624may be connected with each other. Fifth recesses628may be formed to be spaced apart from each other on each of opposite sidewalls in the third direction D3 of the fifth division pattern622.

The fifth recesses628on the opposite sidewalls, respectively, of the fifth division pattern622may overlap each other in the third direction D3, and thus a fourth distance S4 between neighboring ones of the fifth recesses628in the third direction D3 may have a relatively small value, so that electrical interference between portions of the gate electrodes at opposite sidewalls, respectively, in the third direction D3 of the fifth division pattern622, particularly, portions of the gate electrodes adjacent to the fifth recesses628having the sharp shape to which an electric field may be concentrated at the respective opposite sidewalls in the third direction D3 of the fifth division pattern622may increase.

ReferringFIGS.1to7together withFIGS.10to12, the first division pattern330may be formed through the first gate electrode752on the second region II of the substrate100. In example embodiments, a plurality of first division patterns330may be spaced apart from each other in the second and third directions D2 and D3. In example embodiments, the fourth division pattern625may contact an end portion in the second direction D2 of the fourth division pattern625, and may overlap in the first direction D1 an end portion in the second direction D2 of the insulation pattern structure600.

Each of the first to fourth division patterns330,470,620and625may include an oxide, e.g., silicon oxide.

In example embodiments, a memory block including the gate electrode structure and the memory channel structures462in an area formed by neighboring ones of the third division patterns620in the third direction D3 may be defined, and a plurality of memory blocks may be arranged in the third direction D3.

In an example embodiment, the memory block may include two first gate electrodes752at each level divided by the first division pattern330, one second gate electrode754at each level, and four third gate electrodes765at each level divided by the second and fourth division patterns470and625, however, the inventive concept may not be limited thereto. Alternatively, the memory block may include two first gate electrodes752at each level, one second gate electrode754at each level, and six third gate electrodes765at each level.

ReferringFIGS.1to7together withFIG.19, the memory channel structure462may be formed on the first region I of the substrate100, and may contact an upper surface of the CSP240. The memory channel structure462may extend through the channel connection pattern510, the gate electrode structure, the first insulation pattern315, and the fourth and fifth insulating interlayers350and980. In example embodiments, the memory channel structure462may include a first filling pattern442having a pillar shape extending in the first direction D1, a channel412on a sidewall of the first filling pattern442and having a cup shape, a first capping pattern452on upper surfaces of the first filling pattern442and the channel412, and a charge storage structure402on an outer sidewall of the channel412and a sidewall of the first capping pattern452.

The charge storage structure402may include a tunnel insulation pattern392, a charge storage pattern382and a first blocking pattern372sequentially stacked in the horizontal direction, e.g., the second and/or third directions D2 and/or D3, on the outer sidewall of the channel412.

In example embodiments, a plurality of memory channel structures462may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the substrate100to form a memory channel array, and a plurality of memory channel structures462included in the memory channel array may be connected to each other by the channel connection pattern510. Particularly, the charge storage structure402may not be formed on a portion of the outer sidewall of each of the channels412, and the channel connection pattern510may contact the outer sidewalls of the channels412to electrically connect the channels412to each other.

The dummy memory channel structure464may be formed on the second region II of the substrate100, and may contact the upper surface of the CSP240. The dummy memory channel structure464may extend through the sacrificial layer structure290, the gate electrode structure, the first insulation pattern315, and the third and fourth insulating interlayers340and350. In example embodiments, the dummy memory channel structure464may include a second filling pattern444having a pillar shape extending in the first direction D1, a dummy channel414on a sidewall of the second filling pattern444and having a cup shape, a second capping pattern454on upper surfaces of the second filling pattern444and the dummy channel414, and a dummy charge storage structure404on an outer sidewall of the dummy channel414and a sidewall of the second capping pattern454.

The dummy charge storage structure404may include a dummy tunnel insulation pattern394, a dummy charge storage pattern384and a first dummy blocking pattern374sequentially stacked in the horizontal direction, e.g., the second and/or third directions D2 and/or D3, on the outer sidewall of the dummy channel414.

The dummy memory channel structure464may not serve as a memory unit for storing data or a channel through which charge carriers move, but may prevent the gate electrode structure from collapsing or reduce the likelihood of a collapse, and thus may be referred to as a support structure464.

In example embodiments, a plurality of support structures464may be spaced apart from each other in the second and third directions D2 and D3 on the second region II of the substrate100.

The channel412and the dummy channel414may include, e.g., undoped polysilicon, the first and second filling patterns442and444may include an oxide, e.g., silicon oxide, and the first and second capping patterns452and454may include, e.g., doped polysilicon.

The tunnel insulation pattern392and the dummy tunnel insulation pattern394may include an oxide, e.g., silicon oxide, the charge storage pattern382and the dummy charge storage pattern384may include a nitride, e.g., silicon nitride, and the first blocking pattern372and the first dummy blocking pattern374may include an oxide, e.g., silicon oxide.

The insulation pattern structure600may extend through a portion of the gate electrode structure on the second region II of the substrate100, and may have a shape of, e.g., a rectangle, an ellipse, a circle, etc., in a plan view. In example embodiments, the insulation pattern structure600may extend through the second pad of the gate electrode structure having a relatively large length in the second direction D2. The insulation pattern structure600may include second and third insulation patterns317and327alternately and repeatedly stacked in the first direction D1.

The second blocking pattern615may be on and at least partially cover lower and upper surfaces and a sidewall facing the memory channel structure462and the support structure464of each of the first to third gate electrodes752,754and756. The second blocking pattern615may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc.

The third insulating interlayer340may be formed on the support layer300, and may be on and at least partially cover sidewalls of the gate electrode structure and the first insulation pattern315, and the fourth and fifth insulating interlayers350and980may be stacked on the third insulating interlayer340and the first insulation pattern315.

The sixth to ninth insulating interlayers990,640,670and700may be sequentially stacked on the fifth insulating interlayer980, the memory channel structure462and the support structure464.

The first to third upper contact plugs632,634and636may extend through the third to sixth insulating interlayers340,350,980and990and the first insulation pattern315to contact upper surfaces of the first to third gate electrodes752,754and756, respectively, on the second region II of the substrate100. In example embodiments, each of the gate electrode structure may be formed in an area surrounded by the support structures464at each of the first and second pads of the gate electrode structure in a plan view. For example, the support structures464may be disposed at respective vertices of a rectangle in a plan view, and each of the first to third upper contact plugs632,634and636may be formed in an inside of the rectangle in a plan view.

FIG.2shows the layout of the first to third upper contact plugs632,634and636, however, embodiments of the inventive concept may not be limited thereto.

The through via950may extend through the third to seventh insulating interlayers340,350,980,990and640, the insulation pattern structure600, the support layer300, the sacrificial layer structure290, the CSP240, and an upper portion of the second insulating interlayer170on the second region II of the substrate100, and may contact an upper surface of the eighth lower wiring222.

In example embodiments, a plurality of through vias950may be spaced apart from each other in the area where the insulation pattern structure600is formed.FIG.2shows six through vias950in each area, however, embodiments of the inventive concept may not be limited thereto.

The fourth insulation pattern650may be formed on a sidewall of the through via950, and may be electrically connected to the support layer300and the CSP240. However, the through via950may extend through the insulation pattern structure600, that is, the second and third insulation patterns317and327to be electrically insulated from the first to third gate electrodes752,754and756, and thus if an insulation pattern is formed on sidewalls of the support layer300and the CSP240, the fourth insulation pattern650may not be formed. The fourth insulation pattern650may include an oxide, e.g., silicon oxide.

The fourth to sixth upper contact plugs682,684and686may extend through the seventh and eighth insulating interlayers640and670, and may contact upper surfaces of the first to third upper contact plugs632,634and636, respectively. The seventh upper contact plug688may extend through the eighth insulating interlayer670, and may contact an upper surface of the through via950. The eighth upper contact plug690may extend through the sixth to eighth insulating interlayers990,640and670, and may contact an upper surface of the first capping pattern452.

The first to fifth upper wirings712,714,716,718and720may extend through the ninth insulating interlayer700, and may contact upper surfaces of the fourth to eighth upper contact plugs682,684,686,688and690, respectively.

In example embodiments, the fifth upper wiring720may extend in the third direction D3, and a plurality of fifth upper wirings720may be spaced apart from each other in the second direction D2. The fifth upper wiring720may serve as a bit line. Alternatively, an upper via and a sixth upper wiring may be further formed on the fifth upper wiring720, and the sixth upper wiring may serve as the bit line.

The first to fifth upper wirings712,714,716,718and720may have various layouts on the second region II of the substrate100.

The first to sixth upper contact plugs632,634,636,682,684and686, the through via950, and the first to fifth upper wirings712,714,716,718and720may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc.

As illustrated above, the semiconductor device may include the third and fourth division patterns620and625between neighboring ones of the gate electrode structures in the third direction D3 and at least partially separating the gate electrode structures, and the fourth recess pairs on the opposite sidewalls in the third direction D3 of each of the third and fourth division patterns620and625may be arranged in a zigzag pattern in the second direction D2 not to overlap each other in the third direction D3. Thus, the distance between the portions of the gate electrodes in the fourth recesses621may increase, and the electrical interference between the gate electrodes may be reduced.

FIGS.8to38are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device, for example, a vertical channel NAND flash memory device in accordance with example embodiments. Particularly,FIGS.8,12,15,20-21,23-24,32,35and37are the plan views, andFIGS.9-11,13-14,16-19,22,25-31,33-34,36and38are the cross-sectional views.

FIGS.9-11,13,36and38are cross-sectional views taken along lines A-A′ of corresponding plan views, respectively, each ofFIGS.14,16-19and22includes cross-sectional views taken along lines B-B′ and C-C′ of corresponding plan views, respectively,FIGS.25-28,30and33are cross-sectional views taken along lines D-D′ of corresponding plan views, respectively, andFIGS.29,31and34are cross-sectional views taken along lines E-E′ of corresponding plan views, respectively.FIGS.8to38are drawings of region X ofFIG.1,FIG.19includes enlarged cross-sectional views of regions Y and Z ofFIG.18, andFIG.24is an enlarged plan view of region W ofFIG.23.

Referring toFIGS.8and9, a lower circuit pattern may be formed on a substrate100, and first and second insulating interlayers150and170on and at least partially covering the lower circuit pattern may be sequentially stacked on the substrate100.

Each element of the lower circuit pattern may be formed by a patterning process or a damascene process.

Referring toFIG.10, a CSP240and a sacrificial layer structure290may be formed on the second insulating interlayer170, the sacrificial layer structure290may be partially removed to form a first opening302exposing an upper surface of the CSP240, and a support layer300may be formed on an upper surface of the sacrificial layer structure290and the exposed upper surface of the CSP240.

The sacrificial layer structure290may include first, second and third sacrificial layers260,270and280sequentially stacked. Each of the first and third sacrificial layers260and280may include an oxide, e.g., silicon oxide, and the second sacrificial layer270may include a nitride, e.g., silicon nitride.

The first opening302may have various layouts in a plan view. For example, a plurality of first openings302may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the substrate100, the first opening302may extend in the third direction D3 on a portion of the second region II of the substrate100adjacent to the first region I of the substrate100, and a plurality of first openings302, each of which may extend in the second direction D2, may be spaced apart from each other in the third direction D3 on the second region II of the substrate100.FIG.10shows the first opening302extending in the third direction D3 on the portion of the second region II of the substrate100adjacent to the first region I of the substrate100.

The support layer300may include a material having an etching selectivity with respect to the first to third sacrificial layers260,270and280, e.g., polysilicon doped with n-type impurities. The support layer300may have a substantially constant thickness, and thus a first recess may be formed on a portion of the support layer300in the first opening302. Hereinafter, the portion of the support layer300in the first opening302may be referred to as a support pattern305.

An insulation layer310and a fourth sacrificial layer320may be alternately and repeatedly stacked on the support layer300and the support pattern305in the first direction D1, and a mold layer including the insulation layers310and the fourth sacrificial layers320may be formed. The insulation layer310may include an oxide, e.g., silicon oxide, and the fourth sacrificial layer320may include a material having an etching selectivity with respect to the insulation layer310, e.g., a nitride such as silicon nitride.

However, referring toFIG.10together withFIG.12, a first division pattern330extending through a lowermost one of the fourth sacrificial layers320may be formed. The first division pattern330may be formed on the second region II of the substrate100. In example embodiments, a plurality of first division patterns330may be spaced apart from each other in the second and third directions D2 and D3.

Referring toFIG.11, a photoresist pattern on and at least partially covering an uppermost one of the insulation layers310may be formed, and the uppermost one of the insulation layers310and an uppermost one of the fourth sacrificial layers320may be etched using the photoresist pattern as an etching mask. Thus, a portion of one of the insulation layers310directly under the uppermost one of the fourth sacrificial layers320may be exposed.

After performing a trimming process for reducing an area of the photoresist pattern, the uppermost one of the insulation layers310, the uppermost one of the fourth sacrificial layers320, the exposed one of the insulation layers310and one of the fourth sacrificial layer320directly under the exposed one of the insulation layers310may be etched by an etching process using the reduced photoresist pattern as an etching mask. The trimming process and the etching process may be repeatedly performed to form a mold having a staircase shape and including a plurality of step layers each of which may include one fourth sacrificial layer320and one insulation layer310sequentially stacked.

Hereinafter, the “step layer” may refer to all portions of the fourth sacrificial layer320and the insulation layer310at the same level, which may include an unexposed portion as well as an exposed portion of the fourth sacrificial layer320and the insulation layer310, and a “step” may refer to only the exposed portion of the “step layer.” In example embodiments, the steps may be arranged in the second direction D2. Alternatively, the steps may be arranged in the third direction D3.

In example embodiments, lengths in the second direction of the steps included in the mold may be substantially constant except for some of the steps. Lengths in the second direction D2 of some of the steps may be greater than a length in the second direction D2 of other ones of the steps, and hereinafter, ones of the steps having a relatively small length in the second direction D2 may be referred to as first steps, and ones of the steps having a relatively large length in the second direction D2 may be referred to as second steps.FIG.11shows two second steps. In plan views hereinafter, the steps are shown by dotted lines.

The mold may be formed on the support layer300and the support pattern305on the first and second regions I and II of the substrate100, and an upper surface of an edge portion of the support layer300may not be covered by the mold, but may be exposed. The steps included in the mold may be formed on the second region II of the substrate100.

Referring toFIGS.12to14, a third insulating interlayer340may be formed on the CSP240to be on and at least partially cover the mold and the exposed upper surface of the support layer300, and may be planarized until an upper surface of the uppermost one of the insulation layers310is exposed. Thus, a sidewall of the mold may be at least partially covered by the third insulating interlayer340. A fourth insulating interlayer350may be formed on the mold and the third insulating interlayer340.

An etching process may be performed to form a first hole360through the fourth insulating interlayer350, the mold, the support layer300and the sacrificial layer structure290, which may extend in the first direction D1 and expose an upper surface of the CSP240on the first region I of the substrate100. Additionally, a second hole365may be formed through the third and fourth insulating interlayers340and350, a portion of the mold, the support layer300and the sacrificial layer structure290by an etching process, which may extend in the first direction D1 and expose the upper surface of the CSP240on the second region II of the substrate100. In example embodiments, a plurality of first holes360may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the substrate100, and a plurality of second holes365may be spaced apart from each other in the second and third directions D2 and D3 on the second region II of the substrate100.

Furthermore, third and fourth holes490and495may be formed through the third and fourth insulating interlayers340and350, the mold, the support layer300and the sacrificial layer structure290by an etching process, which may extend in the first direction D1 and expose the upper surface of the CSP240on the first and second regions I and II of the substrate100.

The first to fourth holes360,365,490and495may be formed simultaneously or together by one etching process, or sequentially formed by independent etching processes. In example embodiments, the etching process may be performed until the first to fourth holes360,365,490and495expose the upper surface of the CSP240, and further, the first to fourth holes360,365,490and495may extend through an upper portion of the CSP240.

In example embodiments, each of the first and second holes360and365may have a shape of a circle, an ellipse, or a rectangle with chamfered or rounded vertices in a plan view, and each of the third and fourth holes490and495may have a shape of a triangle or a triangle with chamfered or rounded vertices in a plan view. For example, ones of the third holes490each of which has a vertex toward one direction of the third direction D3 and ones of the third holes490each of which has a vertex toward the other one of the third direction D3, that is, a reverse direction to the one direction of the third direction D3 may be alternately and repeatedly disposed in the second direction D2. Likewise, ones of the fourth holes495each of which has a vertex toward one direction of the third direction D3 and ones of the fourth holes495each of which has a vertex toward the other one of the third direction D3, that is, a reverse direction to the one direction of the third direction D3 may be alternately and repeatedly disposed in the second direction D2.

FIG.12shows that each of the first and second holes360and365has a shape of a circle in a plan view, and each of the third and fourth holes490and495has a shape of a triangle with chamfered vertices in a plan view.

In example embodiments, a plurality of third holes490may be spaced apart from each other in the second direction D2 by a first distance S1 (refer toFIG.24) on the first and second regions I and II of the substrate100, and may be disposed to each of opposite end portions in the second direction D2 of the mold having the staircase shape. Additionally, a plurality of third holes490may be spaced apart from each other in the third direction D3.

In example embodiments, a plurality of fourth holes495may be spaced apart from each other in the second direction D2 between neighboring ones of the third holes490in the third direction D3. However, unlike the third holes490disposed in the second direction D2 to the end portions of the mold by the first distance S1 on the first and second regions I and II of the substrate100, a plurality of fourth holes495may be disposed in the second direction D2 by the first distance S1 on the first region I of the substrate100, while a distance between fourth hole groups, each of which may include a plurality of fourth holes495spaced apart from each other in the second direction D2 by the first distance S1, may be greater than the first distance S1 on the second region II of the substrate100.

In example embodiments, ones of the fourth holes495may extend through a portion of the first division pattern330.

Referring toFIGS.15and16, fifth to eighth sacrificial patterns362,366,492and496may be formed in the first to fourth holes360,365,490and495, respectively.

The fifth to eighth sacrificial patterns362,366,492and496may be formed by forming a fifth sacrificial layer on the CSP240and the fourth insulating interlayer350to at least partially fill the first to fourth holes360,365,490and495, and planarizing the fifth sacrificial layer until an upper surface of the fourth insulating interlayer350is exposed.

The fifth sacrificial layer may include, e.g., polysilicon.

Referring toFIG.17, a fifth insulating interlayer980may be formed on the fourth insulating interlayer350and the fifth to eighth sacrificial patterns362,366,492and496, the fifth insulating interlayer980may be patterned to expose fifth and sixth sacrificial patterns362and366, respectively, and the exposed fifth and sixth sacrificial patterns362and366may be removed to form the first and second holes360and365exposing the upper surface of the CSP240.

Referring toFIGS.18and19, a charge storage structure layer and a channel layer may be formed on sidewalls of the first and second holes360and365, the exposed upper surface of the CSP240and an upper surface of the fifth insulating interlayer980, and a filling layer may be formed on the channel layer to at least partially fill a remaining portion of each of the first and second holes360and365.

The charge storage structure layer may include a first blocking layer, a charge storage layer and a tunnel insulation layer sequentially stacked.

The filling layer, the channel layer and the charge storage structure layer may be planarized until the upper surface of the fifth insulating interlayer980is exposed. Thus, a charge storage structure402, a channel412and a first filling pattern442may be formed in the first hole360, and a dummy charge storage structure404, a dummy channel414and a second filling pattern444may be formed in the second hole365. The charge storage structure402may include a first blocking pattern372, a charge storage pattern382and a tunnel insulation pattern392sequentially stacked, and the dummy charge storage structure404may include a dummy blocking pattern374, a dummy charge storage pattern384and a dummy tunnel insulation pattern394sequentially stacked.

Upper portions of the first filling pattern442and the channel412may be removed to form a second recess, upper portions of the second filling pattern444and the dummy channel414may be removed to form a third recess, and first and second capping patterns452and454may be formed to at least partially fill the second and third recesses, respectively.

The charge storage structure402, the channel412, the first filling pattern442and the first capping pattern452in the first hole360may form a memory channel structure462, and the dummy charge storage structure404, the dummy channel414, the second filling pattern444and the second capping pattern454may form a dummy memory channel structure464. The dummy memory channel structure464may prevent the mold from collapsing or reduce the likelihood of a collapse, and thus may also be referred to as a support structure464.

In example embodiments, each of the memory channel structure462and the support structure464may have a pillar shape extending in the first direction D1. In example embodiments, a plurality of memory channel structures462may be spaced apart from each other in the second and third directions D2 and D3 on the first region I of the substrate100, and a plurality of support structures464may be spaced apart from each other in the second and third directions D2 and D3 on the second region II of the substrate100.

Referring toFIG.20, the fifth insulating interlayer980, ones of the insulation layers310and ones of the fourth sacrificial layers320may be etched to form a second opening extending in the second direction D2 through the fifth insulating interlayer980, the ones of the insulation layers310and the ones of the fourth sacrificial layers320, and a second division pattern470may be formed in the second opening.

In example embodiments, the second division pattern470may extend through an upper portion of some ones of the memory channel structures462. Additionally, the second division pattern470may extend through the fourth and fifth insulating interlayers350and980, ones of the fourth sacrificial layers320at upper two levels, and ones of the insulation layers310at upper two levels, and may further partially extend through one of the insulation layers310directly under the ones of the insulation layers310at the upper two levels. The second division pattern470may extend in the second direction D2 on the first and second regions I and II of the substrate100, and may extend through upper two steps included in the mold. Thus, ones of the fourth sacrificial layers320at the upper two levels may be divided in the third direction D3 by the second division pattern470.

Referring toFIGS.21and22, a sixth insulating interlayer990may be formed on the fifth insulating interlayer980, the memory channel structure462and the second division pattern470, the sixth insulating interlayer990may be patterned to expose the seventh and eighth sacrificial patterns492and496, and the exposed seventh and eighth sacrificial patterns492and496may be removed to form the third and fourth holes490and495exposing the upper surface of the CSP240.

Referring toFIGS.23and24, in example embodiments, a wet etching process may be performed to enlarge widths of the third and fourth holes490and495, and thus neighboring ones of the third holes490in the second direction D2 may be connected with each other to form a third opening493and neighboring ones of the fourth holes495in the second direction D2 may be connected with each other to form a fourth opening497.

In example embodiments, the third opening493may extend in the second direction D2 to each of opposite end portions in the second direction D2 of the mold having the staircase shape on the first and second regions I and II of the substrate100, and a plurality of third openings493may be spaced apart from each other in the third direction D3. Thus, the mold may be divided into a plurality of parts spaced apart from each other in the third direction D3 by each of the third openings493. As the third opening493is formed, the insulation layers310and the fourth sacrificial layers320included in the mold may be divided into first insulation patterns315and fourth sacrificial patterns325, respectively, each of which may extend in the second direction D2.

In example embodiments, the fourth opening497may continuously extend in the second direction D2 on the first region I of the substrate100, while a plurality of fourth openings497, each of which may be formed by connecting fourth holes495included in each fourth hole group, may be spaced apart from each other in the second direction D2. The fourth openings497spaced apart from each other in the second direction D2 may be formed between neighboring ones of the third openings493in the third direction D3.

However, unlike the third opening493, a plurality of fourth openings497may be spaced apart from each other in the second direction D2, and thus the mold may not be entirely divided by the fourth opening497. In example embodiments, a portion of the mold between neighboring ones of the fourth openings497in the second direction D2 may at least partially overlap the first division pattern330in the first direction D1.

Each of the fourth openings497may continuously extend in the second direction D2 on the first region I of the substrate100, and may continuously extend to each of opposite end portions of ones of the step layers at upper two levels of the mold on the second region II of the substrate100. Thus, ones of the fourth sacrificial patterns325at the upper two levels of the mold may be divided in the third direction D3 by the fourth opening497and the second division patterns470at opposite sides in the third direction D3 of the fourth opening497.

Even though the mold is divided into a plurality of parts, each of which may extend in the second direction D2, spaced apart from each other in the third direction D3 by the wet etching process for forming the third and fourth openings493and497, the mold may not collapse due to the support structures464and the memory channel structures462.

In example embodiments, the wet etching process may be performed until the third and fourth openings493and497expose the upper surface of the CSP240, and further, the third and fourth openings493and497may extend through an upper portion of the CSP240.

In example embodiments, each of the third and fourth openings493and497may extend to a give length in the second direction D2, and first protrusion portions491protruding toward a central portion of each of the third and fourth openings493and497may be formed on each of opposite sidewalls in the third direction D3 of each of the third and fourth holes493and497. That is, a horizontal width of each of the third and fourth holes490and495having a shape of a triangle or a triangle with chamfered or rounded vertices in a plan view may be enlarged by a wet etching process, and thus neighboring ones of the third holes490may be connected with each other to form the third opening493extending in the second direction D2 and neighboring ones of the fourth holes495may be connected with each other to form the fourth opening497extending in the second direction D2.

In example embodiments, as the wet etching process is performed, the first protrusion portions491may be formed on each of opposite sidewalls of the third opening493at positions adjacent to the vertices of the third holes490arranged in the second direction D2, and the first protrusion portions491may be formed on each of opposite sidewalls of the fourth opening497at positions adjacent to the vertices of the fourth holes497arranged in the second direction D2.

In example embodiments, the first protrusion portions491may be spaced apart from each other in the second direction D2 on the sidewall of each of the third and fourth openings493and497. In example embodiments, a plurality of first protrusion portion pairs, each of which may include neighboring two ones of the first protrusion portions491in the second direction D2, may be spaced apart from each other in the second direction D2, and a distance between the first protrusion portion pairs may be greater than a distance between the first protrusion portions491in each of the first protrusion portion pairs.

In example embodiments, the first protrusion portion pairs on opposite sidewalls of each of the third and fourth openings493and497may be arranged in a zigzag pattern in the second direction D2. That is, the first protrusion portion pairs spaced apart from each other in the second direction D2 on one sidewall of each of the third and fourth openings493and497may not overlap in the third direction D3 the first protrusion portion pairs spaced apart from each other in the second direction D2 on another sidewall of a corresponding one of the third and fourth openings493and497.

Thus, one of the first protrusion portions491on one sidewall of each of the third and fourth openings493and497may be spaced apart from another one of the first protrusion portions491on another sidewall of the corresponding one of the third and fourth openings493and497by a second distance S2, which may be greater than a distance between one of the first protrusion portions491on one sidewall of each of the third and fourth openings493and497and another one of the first protrusion portions491on another sidewall of the corresponding one of the third and fourth openings493and497that overlap each other in the third direction D3.

Referring toFIG.25, a ninth sacrificial pattern may be formed on a lower portion of each of the third and fourth openings493and497, a spacer layer may be formed on an upper surface of the ninth sacrificial pattern, sidewalls of the third and fourth openings493and497and an upper surface of the sixth insulating interlayer990, and an anisotropic etching process may be performed on the spacer layer to remove a portion of the spacer layer on the upper surface of the ninth sacrificial pattern so that a spacer500may be formed.

In example embodiments, an upper surface of the ninth sacrificial pattern may be higher than an upper surface of the sacrificial layer structure290and lower than an upper surface of the support layer300in the first direction D1. Thus, the spacer500may be on and at least partially cover sidewalls of the first insulation patterns315and the fourth sacrificial patterns325exposed by each of the third and fourth openings493and497. The spacer500may include, e.g., undoped polysilicon.

The ninth sacrificial pattern may be removed.

Referring toFIG.26, the sacrificial layer structure290may be removed through the third and fourth openings493and497by, e.g., a wet etching process to form a first gap295.

The wet etching process may be performed using, e.g., hydrofluoric acid (HF) and/or phosphoric acid (H3PO4). In example embodiments, each of the third and fourth openings493and497may not extend through the support layer300and the sacrificial layer structure290, but may extend through the support pattern305on the second region II of the substrate100. Thus, the sacrificial layer structure290may not be removed by the wet etching process on the second region II of the substrate100.

As the first gap295is formed, a lower surface of the support layer300and the upper surface of the CSP240may be exposed. Additionally, a sidewall of a portion of the charge storage structure402on the first region I of the substrate100may be removed by the first gap295, and the portion of the charge storage structure402may also be removed to expose an outer sidewall of the channel412. Thus, the charge storage structure402may be divided into an upper portion extending through the mold and at least partially covering an outer sidewall of a most portion of the channel412and a lower portion at least partially covering a lower surface of the channel412on the CSP240.

Referring toFIG.27, the spacer500may be removed, and a channel connection layer may be formed on the sidewalls of the third and fourth openings493and497and in the first gap295, and a portion of the channel connection layer in the third and fourth openings493and497may be removed by, e.g., an etch back process to form a channel connection pattern510in the first gap295.

As the channel connection pattern510is formed, the channels412between neighboring ones of the third and fourth openings493and497in the third direction D3 may be connected with each other.

An air gap515may be formed in the channel connection pattern510.

Referring toFIGS.28and29, the fourth sacrificial patterns325exposed by the third and fourth openings493and497may be removed to form a second gap590between neighboring ones of the first insulation patterns315in the first direction D1, and a portion of an outer sidewall of the charge storage structure402included in the memory channel structure462and a portion of an outer sidewall of the dummy charge storage structure404included in the support structure464may be exposed by the second gap590.

In example embodiments, a wet etching process may be performed using, e.g., phosphoric acid (H3PO4) or sulfuric acid (H2SO4) to remove the fourth sacrificial patterns325.

The wet etching process may be performed through the third and fourth openings493and497, and an entire portion of the fourth sacrificial pattern325between the third and fourth openings493and497may be removed by an etching solution provided from the third and fourth openings493and497in both directions. However, in an area where the fourth opening497is not formed between the third openings493on the second region II of the substrate100, the etching solution may be provided from the third opening493in a single direction, and thus a portion of the fourth sacrificial pattern325may not be removed but remain, which may be referred to as a third insulation pattern327. Additionally, a portion of the first insulation pattern315overlapping the third insulation pattern327in the first direction D1 may be referred to as a second insulation pattern317. The second and third insulation patterns317and327alternately and repeatedly stacked in the first direction D1 may form an insulation pattern structure600.

The insulation pattern structure600may extend through a portion of the mold on the second region II of the substrate100, and may have a shape of, e.g., a rectangle, an ellipse, a circle, etc., in a plan view. In example embodiments, the insulation pattern structure600may extend through the second step of the mold having a relatively large length in the second direction D2.

Referring toFIGS.30and31, a second blocking layer610may be formed on the outer sidewalls of the charge storage structure402and the dummy charge storage structure404exposed by the third and fourth openings493and497, inner walls of the second gaps590, surfaces of the first insulation patterns315, sidewalls of the fourth to sixth insulating interlayers350,980and990, and an upper surface of the sixth insulating interlayer990, and a gate electrode layer may be formed on the second blocking layer610.

The gate electrode layer may include a gate barrier layer and a gate conductive layer sequentially stacked. The gate barrier layer may include a metal nitride, and the gate conductive layer may include a metal. The second blocking layer610may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc.

The gate electrode layer may be partially removed to form a gate electrode in each of the second gaps590. In example embodiments, the gate electrode layer may be partially removed by a wet etching process. As a result, the fourth sacrificial pattern325in the mold including the step layers of the fourth sacrificial pattern325and the first insulation pattern315may be replaced with the gate electrode and the second blocking layer620on and at least partially covering lower and upper surfaces of the gate electrode.

In example embodiments, the gate electrode may extend in the second direction D2, and a plurality of gate electrodes may be spaced apart from each other in the first direction D1 to form a gate electrode structure. The gate electrode structure may have a staircase shape including the gate electrode as a step layer. An end portion of each of the gate electrodes in the second direction D2 that is not overlapped by ones of the gate electrodes overlying each of the gate electrodes may be referred to as a pad. The gate electrode structure may include first pads having a relatively small length in the second direction D2 and second pads having a relatively large length in the second direction D2, and the numbers of the first and second pads may not be limited.

In example embodiments, a plurality of gate electrode structures may be spaced apart from each other in the third direction D3, which may be separated by the third openings493in the third direction D3. As illustrated above, the fourth openings497may be spaced apart from each other in the second direction D2, the gate electrode structure may not be entirely divided by the fourth openings497. However, one of the gate electrodes at a lowermost level in the gate electrode structure may be divided in the third direction D3 by the fourth openings497, the first division pattern330and the insulation pattern structure600, and ones of the gate electrodes at upper two levels may be divided in the third direction D3 by the fourth opening497and the second division pattern470.

The gate electrode structure may include first, second and third gate electrodes752,754and756sequentially stacked in the first direction D1. In example embodiments, the first gate electrode752may be formed at a lowermost level in the first direction D1 and serve as a ground selection line (GSL), the third gate electrode756may be formed at an uppermost level and a second level from above and serve as a string selection line (SSL), and the second gate electrode754may be formed at a plurality of levels between the first and third gate electrodes752and756and serve as a word line.

In example embodiments, the first to third gate electrodes752,754and756, the charge storage structures402and the channels412between neighboring ones of the third openings493in the third direction D3 may form a memory block, which may include, e.g., two GSLs, one word line and four SSLs at each level, however, the inventive concept may not be limited thereto.

Referring toFIGS.32to34, a third division layer may be formed on the second blocking layer610to at least partially fill the third and fourth openings493and497, and may be planarized until the upper surface of the sixth insulating interlayer is exposed.

Thus, the second blocking layer610may be transformed into a second blocking pattern615, and third and fourth division patterns620and625may be formed in the third and fourth openings493and497, respectively.

Referring toFIGS.32to34together withFIG.3A, in example embodiments, each of the third and fourth division patterns620and625may have a bar shape extending in the second direction D2, and fourth recesses621may be formed on each of opposite sidewalls in the third direction D3, which may correspond to the first protrusion portions491of the mold on each of opposite sidewalls of each of the third and fourth openings493and497.

Referring toFIGS.35and36, first to third upper contact plugs632,634and636may be formed through the third to sixth insulating interlayers340,350,980and990, and the first insulation pattern315on the second region II of the substrate100.

The first to third upper contact plugs632,634and636may contact pads of the first to third gate electrodes752,754and756, respectively.

Referring toFIGS.37and38, a seventh insulating interlayer640may be formed on the sixth insulating interlayer990, the third and fourth division patterns620and625, and the first to third upper contact plugs632,634and636, and a through via950may be formed through the third to seventh insulating interlayers340,350,980,990and640, the insulation pattern structure600, the support layer300, the sacrificial layer structure290, the CSP240and an upper portion of the second insulating interlayer170to contact an upper surface of the eighth lower wiring222.

A fourth insulation pattern650may be formed on a sidewall of the through via950, and thus the support layer300and the CSP240may be electrically insulated from each other.

Referring again toFIGS.1to7, an eighth insulating interlayer670may be formed on the seventh insulating interlayer640, the through via950and the fourth insulation pattern650, and fourth to eighth upper contact plugs682,684,686,688and690may be formed.

The fourth to sixth upper contact plugs682,684and686may extend through the seventh and eighth insulating interlayers640and670to contact upper surfaces of the first to third upper contact plugs632,634and636, respectively, the seventh upper contact plug688may extend through the eighth insulating interlayer670to contact an upper surface of the through via950, and the eighth upper contact plug690may extend through the sixth to eighth insulating interlayers990,640and670to contact an upper surface of the first capping pattern452.

A ninth insulating interlayer700may be formed on the eighth insulating interlayer670and the fourth to eighth upper contact plugs682,684,686,688and690, and first to fifth upper wirings712,714,716,718and720may be formed through the ninth insulating interlayer700.

The first to fifth upper wirings712,714,716,718and720may contact upper surfaces of the fourth to eighth upper contact plugs682,684,686,688and690, respectively.

The semiconductor device according to some embodiments may be manufactured by the above processes.

As illustrated above, when the first and second holes360and365for forming the memory channel structure462and the support structure464, respectively, are formed, the third and fourth holes490and495for forming the third and fourth division patterns620and625, respectively, may be formed. The additional etching process may be performed on the third and fourth holes490and495to enlarge the horizontal widths of the third and fourth holes490and495so that the neighboring third holes490may be connected to form the third opening493and the neighboring fourth holes495may be connected to form the fourth opening497.

In example embodiments, each of the third and fourth holes490and495may have a shape of a triangle or a triangle with chamfered or rounded vertices in a plan view. Thus, the first protrusion portion pairs of the mold on the opposite sidewalls in the third direction D3 of each of the third and fourth openings493and497may be disposed in a zigzag pattern in the second direction D2, and the second distance S2 between neighboring ones of the first protrusion portions491may have a relatively large value.

Accordingly, the neighboring ones of the fourth recesses621in the third direction D3 on the opposite sidewalls of each of the third and fourth division patterns620and625in the corresponding ones of the third and fourth holes490and495may be spaced apart from each other by the second distance S2, which has the relatively large value, and the electrical interference between the portions of the gate electrodes at the respective opposite sides in the third direction D3 of each of the third and fourth division patterns620and625may decrease.

If, as in the comparative embodiment shown inFIG.3B, the fifth holes624having a shape of a circle in a plan view are formed in the second direction D2, instead of the third and fourth holes490and495, second protrusion portions of the mold may be formed on opposite sidewalls of the fifth opening that may be formed by enlarging the horizontal widths of the fifth holes624, and the fifth recesses628may be formed to be spaced apart from each other by a given distance on each of the opposite sidewalls in the third direction D3 of the fifth division pattern622in the fifth opening.

If the fifth holes624are spaced apart from each other by the third distance S3 in the second direction D2, when the horizontal with of each of the fifth holes624is enlarged through an etching process by, e.g., half of the third distance S3, the fifth opening, which may be formed by connecting the fifth holes625with each other, may have a very small width periodically in the second direction D2, so that the division pattern622may not sufficiently separate the gate electrodes from each other. Thus, during the etching process, the horizontal width of each of the fifth holes624has to be enlarged by, more than the third distance S3, which may cause a loss of area due to the fifth division pattern622.

Additionally, the fifth recesses628on the opposite sidewalls of the fifth opening overlap each other in the third direction D3, and thus the fourth distance S4 between neighboring ones of the fifth recesses628in the third direction D3 may have a relatively small value, so that electrical interference may develop between the portions of the gate electrodes on the opposite sidewalls in the third direction D3 of the fifth division pattern622.

However, in example embodiments, each of the third and fourth holes490and495may have the shape of a triangle or a triangle with chamfered or rounded vertices in a plan view, even if the horizontal width of each of the third and fourth holes490and495is enlarged through the etching process by, e.g., half of the first distance S1 between the third holes490or the fourth holes495neighboring in the second direction D2, each of the third and fourth holes493and497that may be formed from the corresponding ones of the third and fourth holes490and495may have a sufficient large width in the third direction D3. Accordingly, the loss of the area due to the third and fourth division patterns620and625may be reduced.

FIGS.39and40are plan views illustrating the division patterns in accordance with example embodiments, which may correspond toFIG.3AorFIG.24. Descriptions of the third division pattern620may be applied to the fourth division pattern625.

Referring toFIG.39, each of the third holes490for forming the third division pattern620may have a “T” shape in a plan view.

Ones of the third holes490having a T shape toward one direction of the third direction D3 and ones of the third holes490having a T shape toward another direction of the third direction D3 may be alternately disposed in the second direction D2.

Thus, the third division pattern620in the third opening493, which may be formed by enlarging the horizontal widths of the third holes490disposed in the second direction D2 to connect the enlarged third holes490to each other, may include the fourth recesses621on each of opposite sidewalls in the third direction D3. A plurality of fourth recess pairs, each of which may include neighboring two ones of the fourth recesses621in the second direction D2, may be spaced apart from each other in the second direction D2, and the fourth recess pairs on the opposite sidewalls of the third division pattern620may be arranged in a zigzag pattern in the second direction D2 not to overlap each other in the third direction D3.

Referring toFIG.40, each of the third holes490may have a shape of a parallelogram, a rhombus, a parallelogram with chamfered or rounded vertices, or a rhombus with chamfered or rounded vertices in a plan view.

Thus, the third division pattern620in the third opening493, which may be formed by enlarging the horizontal widths of the third holes490disposed in the second direction D2 to connect the enlarged third holes490to each other, may include the fourth recesses621on each of opposite sidewalls in the third direction D3. A plurality of fourth recess pairs, each of which may include neighboring two ones of the fourth recesses621in the second direction D2, may be spaced apart from each other in the second direction D2, and the fourth recess pairs on the opposite sidewalls of the third division pattern620may be arranged in a zigzag pattern in the second direction D2 not to overlap each other in the third direction D3.

The fourth recesses621on each of the opposite sidewalls in the third direction D3 of the third division pattern620may be spaced apart from each other in the second direction D2 by a given distance.

FIG.41is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments, which may correspond toFIG.6. This semiconductor device may be substantially the same as or similar to that ofFIGS.1to7, except for the memory channel structure462, the channel connection pattern510, the support layer300and the support pattern305.

Referring toFIG.41, the memory channel structure462may further include a first semiconductor pattern732on the substrate100, and the charge storage structure402, the channel412, the first filling pattern442and the first capping pattern452may be formed on the first semiconductor pattern732.

The first semiconductor pattern732may include, e.g., single crystalline silicon or polysilicon. In an example embodiment, an upper surface of the first semiconductor pattern732may be formed at a height in the first direction D1 between a height of a lower surface of the first insulation pattern315and a height of an upper surface of the first insulation pattern315. The charge storage structure402may have a cup shape of which a lower central portion on the upper surface of the first semiconductor pattern732is opened, and may contact an upper edge surface of the first semiconductor pattern732. The channel412may have a cup shape on the first semiconductor pattern732, and may contact an upper surface of a central portion of the first semiconductor pattern732. Thus, the channel412may be electrically connected to the first semiconductor pattern732.

The support structure464may further include a second semiconductor pattern, and the dummy charge storage structure404, the second filling pattern444and the second capping pattern454may be formed on the second semiconductor pattern.

The channel connection pattern510, the support layer300and the support pattern305may not be formed between the CSP240and the first gate electrode752. In an example embodiment, one of the first insulation patterns315between the first and second gate electrodes752and754may have a thickness greater than those of other ones of the first insulation patterns315.

FIG.42is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments, which may correspond toFIG.6. This semiconductor device may be substantially the same as or similar to that ofFIGS.1to7, except for the shape of the memory channel structure462.

Referring toFIG.42, the memory channel structure462may include lower and upper portions sequentially stacked in the first direction D1, and each of the lower and upper portions may have a width in the third direction D3 gradually increasing from a bottom toward a top thereof in the first direction D1. In example embodiments, an upper surface of the lower portion of the memory channel structure462may have a width greater than a lower surface of the upper portion of the memory channel structure462.

FIG.42shows that the memory channel structure462includes two portions stacked in the first direction D1, however, embodiments of the inventive concept may not be limited thereto, and may include more than two portions stacked in the first direction D1. Each of the portions of the memory channel structure462may have a width in the third direction D3 gradually increasing from a bottom toward a top thereof in the first direction D1, and an upper surface of a portion of the memory channel structure462may have a width greater than a lower surface of a portion of the memory channel structure462thereon.

The support structure464may have a shape similar to that of the memory channel structure462. That is, the support structure464may include a plurality of portions sequentially stacked in the first direction D1, and each of the portions may have a width in the third direction D3 gradually increasing from a bottom toward a top thereof.

FIG.43is a cross-sectional view illustrating a semiconductor device in accordance with example embodiments, which may correspond toFIG.6. This semiconductor device may be substantially the same as or similar to that ofFIGS.1to7, except that the semiconductor device is overturned and bonding structures are further formed.

Referring toFIG.43, in example embodiments, tenth to thirteenth insulating interlayers800,820,840and860may be sequentially stacked on the eighth and ninth lower wirings222and226and the second insulating interlayer170. Additionally, a first bonding pattern extending through the tenth insulating interlayer800to contact the eighth lower wiring222and a second bonding pattern810extending through the tenth insulating interlayer800to contact the ninth lower wiring226may be formed, and a third bonding pattern extending through the eleventh insulating interlayer820to contact the first bonding pattern and a fourth bonding pattern830extending through the eleventh insulating interlayer820to contact the second bonding pattern810may be formed. The first and third bonding patterns and the second and fourth bonding patterns810and830may include a metal, e.g., copper, aluminum, etc., and may be formed by, e.g., a dual damascene process.

Additionally, a seventh upper wiring extending through the twelfth insulating interlayer840to contact the third bonding pattern and an eighth upper wiring850extending through the twelfth insulating interlayer840to contact the fourth bonding pattern may be formed, and a first upper via extending through the thirteenth upper insulating interlayer860to contact the seventh upper wiring and a second upper via870extending through the thirteenth insulating interlayer860to contact the eighth upper wiring850may be formed.

At least some of the first to fifth upper wirings712,714,716,718and720and the sixth upper wiring may be electrically connected to the lower circuit pattern through the first and third bonding patterns and the second and fourth bonding patterns810and830.

An upper surface and an upper sidewall of the channel412may not be covered by the charge storage structure402, and may contact the CSP240.

FIG.44is a schematic diagram illustrating an electronic system including a semiconductor device in accordance with example embodiments.

Referring toFIG.44, an electronic system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one or a plurality of semiconductor devices1100or an electronic device including a storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or a plurality of semiconductor devices1100.

The semiconductor device1100may be a non-volatile memory device, for example, a NAND flash memory device illustrated with reference toFIGS.1to7. The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F.FIG.44shows that the first structure1100F is under the second structure1100S, however, the first structure1100F may be formed at a side of or on the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied in accordance with example embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected with each other in serial. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistors MCT through gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit1110through first connection wirings1115extending to the second structure1110S in the first structure1100F. The bit lines BL may be electrically connected to the page buffer1120through second connection wirings1125extending to the second structure1100S in the first structure1100F.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection wiring1135extending to the second structure1100S in the first structure1100F.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. The electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control operations of the electronic system1000including the controller1200. The processor1210may be operated by firmware, and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221for communicating with the semiconductor device1100. Through the NAND interface1221, control command for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, data to be read from the memory cell transistors MCT of the semiconductor device1100, etc., may be transferred. The host interface1230may provide communication between the electronic system1000and an outside host. When a control command is received from the outside host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.45is a schematic perspective view illustrating an electronic system including a semiconductor device in accordance with example embodiments.

Referring toFIG.45, an electronic system2000may include a main substrate2001, a controller2002mounted on the main substrate2001, at least one semiconductor package2003, and a dynamic random access memory (DRAM) device2004. The semiconductor package2003and the DRAM device2004may be connected to the controller2002by wiring patterns2005on the main substrate2001.

The main substrate2001may include a connector2006having a plurality of pins connected to an outside host. The number and layout of the plurality pins in the connector2006may be changed depending on communication interface between the electronic system2000and the outside host. In example embodiments, the electronic system2000may communicate with the outside host according to one of a USB, peripheral component interconnect express (PCI-Express), serial advanced technology attachment (SATA), M-Phy for universal flash storage (UFS), etc. In example embodiments, the electronic system2000may be operated by power source provided from the outside host through the connector2006. The electronic system2000may further include power management integrated circuit (PMIC) for distributing the power source provided from the outside host to the controller2002and the semiconductor package2003.

The controller2002may write data to the semiconductor package2003or read data from the semiconductor package2003, and may enhance the operation speed of the electronic system2000.

The DRAM device2004may be a buffer memory for reducing the speed difference between the semiconductor package2003for storing data and the outside host. The DRAM device2004included in the electronic system2000may serve as a cache memory, and may provide a space for temporarily storing data during the control operation for the semiconductor package2003. If the electronic system2000includes the DRAM device2004, the controller2002may further include a DRAM controller for controlling the DRAM device2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. The first and second semiconductor packages2003aand2003bmay be semiconductor packages each of which may include a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, the semiconductor chips2200, bonding layers2300disposed under the semiconductor chips2200, a connection structure2400for electrically connecting the semiconductor chips2200and the package substrate2100, and a mold layer2500on and at least partially covering the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board (PCB) including package upper pads2130. Each semiconductor chip2200may include an input/output pad2210. The input/output pad2210may correspond to the input/output pad1101ofFIG.44. Each semiconductor chip2200may include gate electrode structures3210, memory channel structures3220extending through the gate electrode structures3210, and division structures3230for dividing the gate electrode structures3210. Each semiconductor chip2200may include a semiconductor device illustrated with reference toFIGS.1to7.

In example embodiments, the connection structure2400may be a bonding wire for electrically connecting the input/output pad2210and the package upper pads2130. Thus, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected with each other by a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. Alternatively, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected with each other by a connection structure including a through silicon via (TSV), instead of the connection structure2400of the bonding wire method.

In example embodiments, the controller2002and the semiconductor chips2200may be included in one package. In example embodiments, the controller2002and the semiconductor chips2200may be mounted on an interposer substrate different from the main substrate2001, and the controller2002and the semiconductor chips2200may be connected with each other by a wiring on the interposer substrate.

FIGS.46and47are schematic cross-sectional views illustrating a semiconductor package that may include a semiconductor device in accordance with example embodiments.FIGS.46and47illustrate example embodiments of the semiconductor package2003shown inFIG.45, and show a cross-section taken along a line I-I′ of the semiconductor package2003inFIG.45.

Referring toFIG.46, in the semiconductor package2003, the package substrate2100may be a PCB. The package substrate2100may include a substrate body part2120, upper pads2130(refer toFIG.45) on an upper surface of the substrate body part2120, lower pads2125on a lower surface of the substrate body part2120or exposed through the lower surface of the substrate body part2120, and inner wirings2135for electrically connecting the upper pads2130and the lower pads2125in an inside of the substrate body part2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to wiring patterns2005of the main substrate2010in the electronic system2000through conductive connection parts2800, as shown inFIG.45.

Each semiconductor chip2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region in which peripheral circuit wirings3110may be formed. The second structure3200may include a common source line3205, a gate electrode structure3210on the common source line3205, memory channel structures3220and division structures3230(refer toFIG.45) extending through the gate electrode structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate connection wirings3235electrically connected to the word lines WL of the gate electrode structure3210(refer toFIG.44).

Each semiconductor chip2200may include a through wiring3245being electrically connected to the peripheral circuit wirings3110of the first structure3100and extending in the second structure3200. The through wiring3245may be disposed at an outside of the gate electrode structure3210, and the through wirings3245may extend through the gate electrode structure3210. Each semiconductor chip2200may further include the input/output pad2210(refer toFIG.45) electrically connected to the peripheral circuit wirings3110of the first structure3100.

Referring toFIG.47, in a semiconductor package2003A, each semiconductor chip2200amay include a semiconductor substrate4010, a first structure4100on the semiconductor substrate4010, and a second structure4200on and bonded with the first structure4100by a wafer bonding method.

The first structure4100may include a peripheral circuit region in which a peripheral circuit wiring4110and first bonding structures4150may be formed. The second structure4200may include a common source line4205, a gate electrode structure4210between the common source line4205and the first structure4100, memory channel structures4220and the division structure3230(refer toFIG.45) extending through the gate electrode structure4210, and second bonding structures4250electrically connected to the memory channel structures4220and the word lines WL (refer toFIG.44) of the gate electrode structure4210. For example, the second bonding structures4250may be electrically connected to the memory channel structures4220and the word lines WL (refer toFIG.44) through the bit lines4240electrically connected to the memory channel structures4220and the gate connection wirings4235electrically connected to the word lines WL (refer toFIG.44), respectively. The first bonding structures4150of the first structure4100and the second bonding structures4250of the second structure4200may contact each other to be bonded with each other. The first bonding structures4150and the second bonding structures4250may include, for example, copper.

Each semiconductor chip2200amay further include the input/output pad2210(refer toFIG.45) electrically connected to the peripheral circuit wirings4110of the first structure4100.

The semiconductor chips2200ofFIG.46and the semiconductor chips2200aofFIG.47may be electrically connected with each other by the connection structures2400in a bonding wire method. However, in example embodiments, semiconductor chips such as the semiconductor chips2200ofFIG.46and the semiconductor chips2200aofFIG.47in the same semiconductor package may be electrically connected with each other by a connection structure including a TSV.