Active clamp overvoltage protection for switching power device

A controller for driving a power switch incorporates a protection circuit to protect the power switch from fault conditions, such as over-voltage conditions or power surge events. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is configured to monitor the voltage across the power switch and to generate a fault detection indicator signal and the protection gate drive circuit is configured to generate a gate drive signal to turn on the power switch in response to a detected fault condition. In particular, the protection gate drive circuit generates a gate drive signal that has a slow assertion transition and is clamped at a given gate voltage value. In this manner, the protection circuit implements active clamping of the gate terminal of the power switch and safe handling of the power switch during over-voltage events.

BACKGROUND OF THE INVENTION

Induction heating has been widely adopted in domestic, industrial and medical applications. Induction heating refers to the technique of heating an electrically conducting object (such as a metal) by electromagnetic induction whereby electric current is generated in a closed circuit (the object) by the fluctuation of current in another circuit placed physically close to the object. For example, an induction cooker includes a resonant tank driven by an alternating current to induce an alternating magnetic field at an induction coil. The alternating magnetic field at the induction coil induces current in a metal cooking pot placed physically near the induction coil. The current induced in the resistive metal cooking pot generates heat which in turn heats the food in the cooking pot.

A commonly used topology for induction heating applications is the single switch quasi-resonant inverter topology including a single power switch and a single resonant capacitor to supply variable resonant current to the induction coil. The single switch quasi-resonant inverter is often implemented using an insulated gate bipolar transistor (IGBT) as the power switching device due to the high power capability and high switching frequency operation of IGBTs.

Overvoltage conditions, such as a power surge, can be a serious problem for the single switch quasi-resonant inverter circuit. In particular, the power switching device in the quasi-resonant inverter circuit may fail or become permanently damaged when a voltage exceeding the voltage rating of the power switching device is applied. For example, an abnormally high surge voltage may be applied to the AC input line during a lightning event. In the event that the surge voltage exceeds the breakdown voltage of the power switching device, the power switching device may become irreversibly damaged if remedial action is not taken within a very short time from the power surge event, on the order of a few microseconds.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as a process; an apparatus; a system; and/or a composition of matter. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention.

In embodiments of the present invention, a controller for driving a power switch incorporates a protection circuit to protect the power switch from fault conditions, such as over-voltage conditions or power surge events. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is configured to monitor the voltage across the power switch and to generate a fault detection indicator signal and the protection gate drive circuit is configured to generate a gate drive signal to turn on the power switch in response to a detected fault condition. In particular, the protection gate drive circuit generates a gate drive signal that has a slow assertion transition and is clamped at a given gate voltage value. In this manner, the protection circuit implements active clamping of the gate terminal of the power switch and safe handling of the power switch during over-voltage events.

In some embodiments, the protection gate drive circuit drives the power switch to turn on for predetermined time duration to dissipate the energy from a fault over-voltage event across the power switch. In other embodiments, the fault detection circuit includes a hysteresis over-voltage detection circuit using a set voltage level and a reset voltage level for fault condition detection, the set voltage level being higher than the reset voltage level. The fault detection indicator signal is asserted when the voltage across the power switch exceeds the set voltage level and the fault detection indicator signal is deasserted when the voltage across the power switch drops below the reset voltage level. In some embodiments, the protection gate drive circuit asserts the gate drive signal to turn on the power switch at the clamped gate voltage in response to the fault detection indicator signal being asserted. The protection gate drive circuit applies the clamped gate drive signal until the fault detection indicator signal is deasserted or for a predetermined fixed time duration, whichever is shorter.

In embodiments of the present invention, the controller is applied to drive a power switch incorporated in a single switch quasi-resonant inverter for induction heating applications. The single switch quasi-resonant inverter is often implemented using an insulated gate bipolar transistor (IGBT) as the power switching device due to the high power capability and high switching frequency operation of the IGBTs. The protection circuit of the present invention implements an active gate drive protection scheme to protect a power switch and can be advantageously applied to protect the IGBT in a quasi-resonant inverter circuit used in induction heating applications.

The protection circuit of the present invention realizes advantages over conventional protection schemes for power switching devices or IGBTs. In particular, the protection circuit of the present invention implements active clamping with soft gate drive control to protect the power switching device during an over-voltage event. During an over-voltage event, the power switching device is turned on with the gate voltage clamped to protect the gate terminal of the power switching device from excessive voltages. Meanwhile, the power switching device is turned on one or more times successively to dissipate the excessive voltage and current. The soft gate drive control, including soft turn-on and soft-turn-off, dampens the oscillations that may be generated from the voltage transients across the power switching device during the on and off switching. The protection circuit of the present invention realizes effective over-voltage protection of power switching devices or IGBTs.

FIG. 1is a circuit diagram of a single switch quasi-resonant inverter applied in an induction heating application in some examples. Referring toFIG. 1, a single switch quasi-resonant inverter10includes a surge suppressor14, a bridge rectifier16, a filter circuit, a resonant tank and a power switching device M0, also referred to as a power switch. The quasi-resonant inverter10receives an AC input voltage12which is coupled to the surge suppressor14. The bridge rectifier16, also referred to as a diode bridge, converts the AC input voltage12to a DC voltage which is then filtered by the filter circuit including an input capacitor Ci, a filter inductor Lf, a filter capacitor Cfand a resistor RS. The filtered DC voltage is applied to the resonant tank formed by an induction coil Lr and a resonant capacitor Cr. The induction coil Lr is connected to the power switch M0which is switched on and off in response to a gate drive signal Vgctrl. When the power switch M0is turned on, a current iCflow from the induction coil Lr through the power switch M0to ground. When the power switch M0is turned off, no current flow through the power switch M0. Instead, a current iLrcirculates between the induction coil Lr and the resonant capacitor Cr. In the present embodiment, the power switch M0is an insulated gate bipolar transistor (IGBT). The collector terminal of the IGBT is connected to the induction coil Lr (node20) and the emitter terminal of the IGBT is connected to ground. The gate terminal of the IGBT is driven by the gate drive signal Vgctrl.

In operation, when the power switch M0(IGBT) is turned on, an alternating electric current flows through the induction coil Lr, which produces an oscillating magnetic field. The oscillating magnetic field induces an electric current into a metal cooking pot placed physically near the induction coil. The current flows in the resistive metal pot will generate heat, thereby heating the food in the cooking pot. When the power switch M0is turned off, the current iLrcirculates around the induction coil Lr and the capacitor Cr. The power switch M0is turned on and off in response to the gate drive signal Vgctrlto control the amount of electric current induced in the cooking pot, there by controlling the amount of heat generated.

The power switch M0(IGBT) is turned on and off during the operation of the single switch quasi-resonant inverter. The power switch M0can experience high voltage transients at the power terminal (node20) when the power switch is being turned off. For example, when the IGBT is switched off, the collector voltage VCE(node20) can increase very fast, such as up to 800-1000V for an AC input voltage of 220V. In this case, an IGBT with a typical voltage rating of 1.7 kV for collector-emitter voltage can handle the normal voltage transients during on-off switching operation. However, the IGBT may be exposed to fault over-voltage conditions, such as a power surge event, where a voltage surge induces a voltage at the induction coil Lr that exceeds the voltage rating of the IGBT. For instance, during a lightning event, an abnormally large power surge may be introduced to the AC power line. A power surge event caused by lightning can drive the collector voltage of the IGBT to above 2 kV, beyond the voltage rating of the IGBT, resulting in damage to the IGBT. Therefore, the power switch or IGBT in the single switch quasi-resonant inverter needs to be protected from over-voltage events, such as an excessive power surge event.

Furthermore, the power switch needs to be protected from power surge events especially when the power surge event occurs when the power switch is turned off. When the power switch is turned on, the power switch can dissipate the surge voltage to ground by conduction through its power terminals. For example, when the IGBT is turned on, the IGBT can conduct the voltage surge from the collector to the emitter which is connected to ground to dissipate the voltage surge. However, if the IGBT is turned off, the transistor does not dissipate the surge voltage and the collector terminal may experience excessive surge voltage exceeding the voltage rating of the device, causing permanent damage to the transistor.

FIG. 2is a block diagram of a controller circuit including a protection circuit coupled to drive the power switch in a single switch quasi-resonant inverter for induction heating application in embodiments of the present invention. Referring toFIG. 2, the single switch quasi-resonant inverter10ofFIG. 1is driven by a controller circuit30to switch the power switch M0on and off to conduct current alternately through the induction coil Lr. In the present embodiment, the power switch M0is an IGBT having a gate as the control terminal and collector and emitter terminals as the power terminals. In the following description, the controller circuit will be described as driving the IGBT as the power switch M0. The present description is illustrative only and not intended to be limiting. It is understood that the power switch M0can be implemented using other power switching devices other than an IGBT. A power switch or a power switching device includes a control terminal or a gate terminal receiving a control signal or a gate drive signal and a pair of power terminals conducting currents.

In embodiments of the present invention, the controller circuit30includes a normal gate drive circuit34and a protection circuit formed by a protection gate drive circuit40and a fault detection circuit50. In the present embodiment, the fault detection circuit50is constructed as an over-voltage detection circuit configured to detect an over-voltage condition or excessive voltage event at the collector terminal (node20) of the IGBT or an excessive collector-to-emitter voltage VCEat the IGBT.

In controller circuit30, the normal gate drive circuit34receives an input signal VIN(node32) for controlling the on and off switch cycle of the power switch M0or the IGBT to obtain the desired power output at the quasi-resonant inverter. The input signal VINcan be a PWM signal, or a clock signal switching between on period and off period. The normal gate drive circuit34generates an output signal on node52as the gate drive signal Vgctrlcoupled to the gate terminal (node22) of the IGBT. In the present embodiment, the normal gate drive circuit is constructed as a CMOS inverter and includes a PMOS transistor M1connected in series with an NMOS transistor M2between the positive power supply Vdd (node38) and ground. An impedance Z1is coupled to the drain terminal (node52) of the PMOS transistor M1and an impedance Z2is coupled to the drain terminal (node52) of the NMOS transistor M2. The common node52between the PMOS transistor M1and the NMOS transistor M2is the output signal of the normal gate drive circuit34.

A gate logic circuit36receives the input signal VINand generates gate control signals for the PMOS transistor M1and the NMOS transistor M2. The gate logic circuit36generates gate control signals for the PMOS transistor M1and the NMOS transistor M2so that the PMOS transistor M1and the NMOS transistor M2are turned on and off alternately in response to the input signal VIN. That is, the PMOS transistor M1and the NMOS transistor M2are not turned on at the same time. Accordingly, as the input signal VINswitches between a logical high level and a logical low level, the normal gate drive circuit34generates the gate drive signal Vgctrlto cause the IGBT to switch on and off in normal operation. More specifically, the NMOS transistor M2is turned on to drive the gate terminal of the IGBT to ground to turn off the IGBT in normal operation. Alternately, the PMOS transistor M1is turned on to drive the gate terminal of the IGBT to power supply voltage Vdd to turn on the IGBT in normal operation.

The controller circuit30includes a protection circuit providing over-voltage protection for the power switch M0or IGBT at the gate drive level. The protection circuit implements active gate clamping and safe handling of over-voltage events at the power switch of the quasi-resonant inverter. The protection circuit includes the over-voltage detection circuit50and the protection gate drive circuit40. The over-voltage detection circuit50detects for over-voltage fault conditions during the normal operation of the power switch and activates remedial actions to protect the power switch from damage. The protection gate drive circuit40is activated in response to the detection of a fault condition to generate a clamped gate voltage as the gate drive signal to bias the power switch so as to dissipate the voltage surge before any damage is done to the power switch.

The over-voltage detection circuit50receives a feedback voltage VFBon an input node54indicative of the collector-to-emitter voltage VCEof the IGBT, or the voltage across the power terminals of the power switch M0. In the present embodiment, a voltage divider formed by resistors R6and R7is coupled to the collector terminal (node20) of the IGBT to divide down the collector-to-emitter voltage as the feedback voltage VFB. The feedback voltage VFB(node24) is coupled to the over-voltage detection circuit50to detect for an over-voltage condition. In embodiments of the present invention, the over-voltage detection circuit50is operative only during the off-period of the IGBT. That is, the over-voltage detection circuit50is activated to monitor the collector-to-emitter voltage only during the time period when the IGBT is driven by the gate drive signal Vgctrlto be fully turned off.

When the IGBT is fully turned on, the IGBT conducts current from the collector to the emitter and the collector voltage (node20) is held at the saturation voltage VCE-SATvoltage. So even if there is a power surge, the collector voltage at the IGBT is low and the IGBT is protected from damage. However, during the period when the IGBT is fully turned off, a power surge at the collector terminal of the IGBT may result in a collector voltage that is too high and damage the IGBT.

During the off-period of the IGBT, the over-voltage detection circuit50compares the feedback voltage VFB(node24) to an over-voltage threshold voltage value to determine if an over-voltage condition has occurred at the collector terminal of the IGBT. The over-voltage detection circuit50generates a fault detection indicator signal in the event that the feedback voltage VFBexceeds the over-voltage threshold voltage value. More specifically, the over-voltage detection circuit50asserts the fault detection indicator signal in response to the feedback voltage VFBexceeding the over-voltage threshold voltage value and deasserts the fault detection indicator signal in response to the feedback voltage VFBbeing below the over-voltage threshold voltage value. In some embodiments, the over-voltage detection circuit is constructed as a hysteresis over-voltage detection circuit including a set voltage level and a reset voltage level for fault over-voltage condition detection, the set voltage level being higher than the reset voltage level. The fault detection indicator signal is asserted when the feedback voltage exceeds the set voltage level and the fault detection indicator signal is deasserted when the feedback voltage drops below the reset voltage level.

The fault detection indicator signal, or a signal indicative thereof, is provided to the normal gate drive circuit34and to the protection gate drive circuit40. At the normal gate drive circuit34, the fault detection indicator signal, or its equivalent, is coupled to the gate logic circuit36and is operative to disable or turn off the NMOS transistor M2when a fault over-voltage condition is detected. During the time period when the over-voltage detection circuit50is active, the IGBT is turned off, meaning that the NMOS transistor M2in the normal gate drive circuit34is activated or turned on to drive the gate drive signal to ground, thereby turning off the IGBT. In order to initiates remedial measures in response to the detection of a fault over-voltage condition, the NMOS transistor M2should be turned off or disabled so that the protection gate drive circuit40can be activated to drive the gate of the IGBT. In this manner, the protection gate drive circuit40does not have to over-drive the NMOS transistor M2. In other words, in normal operation, transistors M1and M2are alternately turned on and off to drive the gate of the IGBT. However, when an over-voltage condition is detected, both transistors M1and M2are turned off prior to or at the same time as remediation measures are being initiated at the protection gate drive circuit40.

The fault detection indicator signal, or a signal indicative thereof, is also provided to protection gate drive circuit40to initiate remedial measures to protect the IGBT. In the present embodiment, the protection gate drive circuit40includes a PMOS transistor M3connected in series with an NMOS transistor M4between the positive power supply Vdd (node38) and ground. An impedance Z3is provided at the drain terminal (node52) of the PMOS transistor M3and an impedance Z4is provided at the drain terminal (node52) of the NMOS transistor M4. The common node52between the PMOS transistor M3and the NMOS transistor M4is the output signal of the protection gate drive circuit. The protection gate drive circuit40generates an output signal on node52as the gate drive signal Vgctrlcoupled to the gate terminal (node22) of the IGBT.

The fault detection indicator signal, or a signal indicative thereof, generated by the over-voltage detection circuit50is coupled to control the PMOS transistor M3and the NMOS transistor M4through respective time controllers and gate voltage clamping circuits. At PMOS transistor M3, the fault detection indicator signal, or a signal indicative thereof, is coupled to a time controller42and a gate control circuit44. The time controller42controls the on-duration of PMOS transistor M3in response to the fault detection indicator signal. In particular, the time controller42causes the PMOS transistor M3to be turned on until the fault detection indicator signal is deasserted or for a predetermined fixed time duration (also called “one shot duration”), whichever is shorter. At NMOS transistor M4, the fault detection indicator signal is coupled to a time controller46and a gate control circuit48. The time controller46controls the on-duration of NMOS transistor M4in response to the fault detection indicator signal. In particular, the time controller46delays the off assertion time of the NMOS transistor M4to provide a soft turn-off of the IGBT, as will be explained in more detail below.

In operation, responsive to the fault detection indicator signal being asserted, the NMOS transistor M2in the normal gate drive circuit34is turned off. Meanwhile, the protection gate drive circuit40turns on both the PMOS transistor M3and the NMOS transistor M4. With both PMOS transistor M3and the NMOS transistor M4being turned on, the impedance Z3and impedance Z4form a voltage divider between the positive power supply voltage and ground. The voltage divider of Z3and Z4generates an output signal as the gate drive signal on output node52being a divided down voltage of the positive power supply voltage Vdd. In particular, the gate drive signal is clamped at a voltage value being a function of the impedances Z3and Z4and given as:

Accordingly, the protection gate drive circuit40generates an output signal at a clamped gate voltage value as the gate drive signal Vgctrlto drive the gate terminal of the IGBT. The IGBT is therefore turned on during an over-voltage event to dissipate the excessive charge at the collector terminal (node20). By driving the gate of the IGBT through a voltage divider of Z3and Z4, the gate of the IGBT is turned on gradually, achieving soft turn-on for the clamped gate voltage. In this manner, the protection gate drive circuit40turns on the IGBT in a protection mode to discharge the voltage surge.

The over-voltage detection circuit50continues to monitor the feedback voltage VFB. When the collector-to-emitter voltage VCE(node20) drops below the over-voltage threshold voltage value, or the reset voltage level in a hysteresis detection circuit, the over-voltage detection circuit50deasserts the fault detection indicator signal. The protection gate drive circuit40can then be deactivated to turn off the IGBT in the protection mode. In operation, the time controller42will deassert the gate control signal to PMOS transistor M3first to release the clamped gate voltage at the output node52. In embodiments of the present invention, the protection circuit applies the clamped gate drive signal to turn the IGBT on during an over-voltage event but the on-duration of the IGBT is limited to a maximum duration determined by a fixed time duration. In cases where the voltage surge does not get dissipated with the IGBT being turned on at the clamped gate voltage, the fault detection indicator signal may remain asserted for an extended duration which is undesirable. It is not desirable to keep the IGBT turned on for too long as it may impact the reliability of the IGBT. Accordingly, the time controller42in the protection gate drive circuit40applies a maximum one-shot duration to the on-time of PMOS transistor M3. The time controller42deasserts the gate control signal to PMOS transistor M3when the fault detection indicator signal being deasserted or when the fixed time duration has expired, whichever is sooner.

With the PMOS transistor M3being disabled, the output signal of the protection gate drive circuit40is no longer driven to the clamped gate voltage. However, the gate terminal (node22) of the IGBT needs to be discharged to ground in order to turn off the IGBT. Accordingly, when the fault detection indicator signal is deasserted, time controller46delays the deassertion of the gate drive signal to NMOS transistor M4. Therefore, when the over-voltage protection event has passed and the PMOS transistor M3has been turned off, the NMOS transistor M4remains turned on for a given delay time to discharge the gate terminal (node22) of the IGBT, thereby achieving soft turn-off of the clamped gate voltage. After the delay duration, the NMOS transistor M4is turned off and the NMOS transistor M2in the normal gate drive circuit34is turned back on to hold the gate terminal of the IGBT to ground before the IGBT returns to normal operation.

As thus configured, the protection circuit implemented in the controller circuit30realizes gate drive level over-protection for the IGBT in the quasi-resonant inverter10. In particular, by using the voltage divider of Z3and Z4, the gate voltage of the IGBT is precisely controlled between the threshold VGE_thand the Miller plateau level. Thus, the IGBT is turned on to enable the induction coil current iLrto flow through the IGBT and the resonant capacitor voltage VCrto be clamped at the desired level when the fault overvoltage condition occurs. In this manner, the protection circuit uses active gate drive to safely protect the IGBT or the power switch in the quasi-resonant inverter from voltage surge or other over-voltage events. The protection circuit implements soft turn on and turn-off operations to switch the IGBT without large transients. In some embodiments, the protection gate drive circuit is constructed using impedances Z3and Z4that ensures the clamped gate voltage to be independent of temperature variation.

FIG. 3is a circuit diagram illustrating the construction of the controller circuit ofFIG. 2in embodiments of the present invention. Referring toFIG. 3, a controller circuit60for driving the gate terminal (node22) of an IGBT includes a normal gate drive circuit66and a protection gate drive circuit68. The controller circuit60also includes a hysteresis over-voltage detection circuit80configured to detect an over-voltage condition or excessive voltage event at the collector terminal (node20) of the IGBT or an excessive collector-to-emitter voltage VCEat the IGBT.

In controller circuit60, the normal gate drive circuit66receives an input signal VIN(node62) for controlling the on and off switch cycle of the IGBT to obtain the desired power output at the quasi-resonant inverter. The normal gate drive circuit is constructed as a CMOS inverter and includes a PMOS transistor M1connected in series with an NMOS transistor M2between the positive power supply Vdd (node64) and ground. An impedance Z1is coupled to the drain terminal (node76) of the PMOS transistor M1and an impedance Z2is coupled to the drain terminal (node76) of the NMOS transistor M2. The common node76between the PMOS transistor M1and the NMOS transistor M2is the output signal of the normal gate drive circuit34. The input signal VINcan be a PWM signal, or a clock signal switching between on period and off period. The normal gate drive circuit66generates an output signal on node76as the gate drive signal Vgctrlcoupled to the gate terminal (node22) of the IGBT. In some embodiments, an impedance Z5may be coupled to the output node76to keep the gate of the IGBT grounded should the gate is not driven by any other circuitry. The impedance Z5is optional and may be omitted in other embodiments.

The input voltage VINis coupled to an NOR gate72generating a gate control signal VG2for controlling the NMOS transistor M2. The input voltage VINis further coupled to an inverter74generating a gate control signal VG1for controlling the PMOS transistor M1. The PMOS transistor M1and the NMOS transistor M2essentially function as a CMOS inverter for inverting the logical states of the input voltage VINto drive the gate terminals of transistors M1and M2. Thus, when the input voltage VINis at a logical high, the PMOS transistor M1is turned on and the NMOS transistor M2is turned off. Meanwhile, when the input voltage VINis at a logical low, the PMOS transistor M1is turned off and the NMOS transistor M2is turned on. NMOS transistor M2is further controlled by a gate control signal VG4generated by a time controller70. The input voltage VINand the gate control signal VG4are coupled to the NOR gate72. Therefore, the gate control signal VG2will assert (logical high) only when both the input voltage VINand the gate control signal VG4are at a logical low. Otherwise, the gate control signal VG2is deasserted (logical low). The gate control signal VG4is generated from the fault detection indicator signal, as will be described in more details below.

The hysteresis over-voltage detection circuit80receives a feedback voltage VFBon an input node78indicative of the collector-to-emitter voltage VCEof the IGBT. In the present embodiment, a voltage divider formed by resistors R6and R7is coupled to the collector terminal (node20) of the IGBT to divide down the collector-to-emitter voltage as the feedback voltage VFB. The feedback voltage VFB(node24) is coupled to the hysteresis over-voltage detection circuit80through an input impedance Z6as the over-voltage monitor signal OV_IN to detect for an over-voltage condition. The input impedance Z6functions as an analog filter for the feedback voltage and also provides the ESD protection for the NMOS transistor M5. In embodiments of the present invention, the hysteresis over-voltage detection circuit80is operative only during the off-period of the IGBT. Accordingly, the NMOS transistor M5is coupled to the input node79to enable or disable the over-voltage monitor signal OV_IN in response to the input voltage VIN. More specifically, the input voltage VINis coupled to a timer controller88. The timer controller88receives the input voltage signal VINand generates an output signal OV_Enable being the input voltage with an extended on-period T1. The OV_Enable signal is the gate control signal VG5coupled to drive the gate terminal of NMOS transistor M5. NMOS transistor M5is therefore turned on when the input voltage is asserted to turn on the IGBT. With NMOS transistor M5turned on, the input node79is shorted to ground and therefore the over-voltage monitor signal OV_IN is disabled. The time controller88extends the on-time of the input voltage signal so as to mask the high-to-low transition of the input voltage VINfrom the detection operation. That is, the NMOS transistor M5remains turned on for a short duration after the falling edge of the input voltage VIN. In other words, the over-voltage monitor signal OV_IN is enabled a short duration after the input voltage VINis deasserted, therefore masking the transition time from the detection operation. In this manner, the hysteresis over-voltage detection circuit80is activated to monitor the collector-to-emitter voltage VCEof the IGBT only during the time period when the IGBT is driven by the gate drive signal Vgctrlto be fully turned off.

In some embodiments, the hysteresis over-voltage detection circuit80is constructed using a hysteresis band fast response and high gain comparator using a bandgap reference voltage. The hysteresis over-voltage detection circuit80is able to provide precise detection of over-voltage conditions by monitoring of the feedback voltage.

At the hysteresis over-voltage detection circuit80, the over-voltage monitor signal OV_IN is compared to over-voltage threshold voltage values to determine if an over-voltage condition has occurred at the collector terminal of the IGBT. In particular, the hysteresis over-voltage detection circuit including a set voltage level and a reset voltage level for fault over-voltage condition detection, the set voltage level being higher than the reset voltage level. The over-voltage monitor signal OV_IN is compared to the set voltage level and the reset voltage level as the threshold voltage values. The hysteresis over-voltage detection circuit80generates a fault detection indicator signal OV_OUT (node82). The fault detection indicator signal OV_OUT is asserted when the over-voltage monitor signal OV_IN exceeds the set voltage level and the fault detection indicator signal is deasserted when the over-voltage monitor signal OV_IN drops below the reset voltage level.

The fault detection indicator signal OV_OUT (node82) is coupled to a level shifter84to adjust the voltage level of the indicator signal. The level-adjusted fault detection indicator signal VL(node85) is coupled to an inverter86to generate an inverted indicator signal VLB(node87). The level-adjusted fault detection indicator signal VLand inverted indicator signal VLBare coupled to drive the normal gate drive circuit66and the protection gate drive circuit68. In the present embodiment, the fault detection indicator signal OV_OUT is an active low signal. That is, the fault detection indicator signal OV_OUT is normally at a logical high level (deasserted) and when a fault over-voltage condition is detected, the fault detection indicator signal OV_OUT transitions to a logical low level (asserted).

The protection gate drive circuit68includes a PMOS transistor M3connected in series with an NMOS transistor M4between the positive power supply Vdd (node64) and ground. An impedance Z3is provided at the drain terminal (node76) of the PMOS transistor M3and an impedance Z4is provided at the drain terminal (node76) of the NMOS transistor M4. The common node76between the PMOS transistor M3and the NMOS transistor M4is the output signal of the protection gate drive circuit. The protection gate drive circuit68generates an output signal on node76as the gate drive signal Vgctrlcoupled to the gate terminal (node22) of the IGBT.

The fault detection indicator signal, or a signal indicative thereof, generated by the hysteresis over-voltage detection circuit80is coupled to the normal gate drive circuit66and to the protection gate drive circuit68to initiate remediation measures in response to detection of an over-voltage event. First, the inverted fault detection indicator signal VLBis coupled to the time controller70. The inverted fault detection indicator signal VLBis at a logical low level when deasserted and at a logical high level when asserted. The time controller70passes the inverted fault detection indicator signal VLBto the output but with extended on duration T2. That is, the time controller70asserts the gate control signal VG4in response to the inverted fault detection indicator signal VLBbeing asserted and the time controller70deasserts the gate control signal VG4a given delay time after the inverted fault detection indicator signal VLBis deasserted. The gate control signal VG4is coupled to the NOR gate72whose output drives the NMOS transistor M2in the normal gate drive circuit66and is also coupled to drive the NMOS transistor M4in the protection gate drive circuit68.

As described above, the hysteresis over-voltage detection circuit80is operative only during the off-period of the IGBT. In that case, the input voltage VINis deasserted (logical low) and the gate control signal VG2is at a logical high level to drive the NMOS transistor M2to a fully on-state. With NMOS transistor M2fully turned on and the PMOS transistor M1fully turned off, the gate terminal (node22) of the IGBT is discharged to ground and is held at ground during the off-period. In response to the detection of an over-voltage event, the inverted fault detection indicator signal VLBis asserted (logical high) and the gate control signal VG4is asserted (logical high) as well. Therefore, the gate control signal VG2coupled to drive the NMOS transistor M2transitions to a logical low level and the NMOS transistor M2is disabled or turned off. Thus, the normal gate drive circuit66is disabled and is no longer driving the IGBT. Meanwhile, the gate control signal VG4, being asserted, is also coupled to the gate terminal of the NMOS transistor M4to turn the NMOS transistor M4on.

Second, the fault detection indicator signal VLis coupled to the time controller71. The fault detection indicator signal VLis at a logical high level when deasserted and at a logical low level when asserted. The time controller71passes the fault detection indicator signal VLto the output with an one-shot duration control. That is, the time controller71asserts (logical low) the gate control signal VG3in response to the fault detection indicator signal VLbeing asserted and the time controller71deasserts the gate control signal VG3in response to the fault detection indicator signal VLbeing deasserted or the expiration of a fixed time duration T3, whichever occurs first. Therefore, the maximum time duration the gate control signal VG3will be asserted is the fixed time duration, also referred to as the one-shot duration. The gate control signal VG3will be asserted for the one-shot duration or shorter. The gate control signal VG3is coupled to drive the gate terminal of the PMOS transistor M3in the protection gate drive circuit68.

In response to the detection of an over-voltage event, the fault detection indicator signal VLis asserted (logical low) and the gate control signal VG3is asserted (logical low) as well. The gate control signal VG3is coupled to the gate terminal of the PMOS transistor M3to turn the PMOS transistor M3on in response to the detection of the over-voltage event. The PMOS transistor M3is turned on until the fault detection indicator signal VLis deasserted or the one-shot duration T3has expired.

In operation, responsive to the fault detection indicator signal OV_OUT being asserted, the NMOS transistor M2in the normal gate drive circuit66is turned off. Meanwhile, the protection gate drive circuit68turns on both the PMOS transistor M3and the NMOS transistor M4. With both PMOS transistor M3and the NMOS transistor M4being turned on, the impedance Z3and impedance Z4form a voltage divider between the positive power supply voltage and ground. The voltage divider of Z3and Z4generates an output signal as the gate drive signal on output node76being a divided down voltage of the positive power supply voltage Vdd. In particular, the gate drive signal is clamped at a voltage value being a function of the impedances Z3and Z4and given as (Z4/(Z3+Z4))*Vdd. Accordingly, the protection gate drive circuit68generates an output signal at a clamped gate voltage value as the gate drive signal Vgctrlto drive the gate terminal of the IGBT. The IGBT is therefore turned on during an over-voltage event to dissipate the excessive charge at the collector terminal (node20). It is imperative to note that by driving the gate of the IGBT through a voltage divider of Z3and Z4, the gate of the IGBT is turned on gradually, achieving soft turn-on control. In this manner, the protection gate drive circuit68turns on the IGBT in a protection mode to discharge the voltage surge.

In some embodiments, the ratio of the impedances Z3and Z4is 0.55. The clamped gate voltage applied to the IGBT is therefore about half of the power supply voltage Vdd. Furthermore, the protection circuit is capable of activating the protection gate drive circuit68very quickly to clamp the gate voltage of the IGBT. In one example, the peak of a power surge at the AC input may take about 15 μs to arrive at the collector terminal of the IGBT in the quasi-resonant inverter circuit. However, the protection circuit of the present invention is able to clamp the gate voltage of the IGBT at around 500 ns—long before the peak of the power surge arrives at the collector terminal. In this manner, the IGBT is turned on when the peak surge voltage reaches the collector terminal and the IGBT is able to dissipate the power surge safely, without damaging the IGBT.

The hysteresis over-voltage detection circuit80continues to monitor the feedback voltage VFB. When the collector-to-emitter voltage VCE(node20) drops below the reset voltage level, the over-voltage detection circuit80deasserts the fault detection indicator signal OV_OUT. The protection gate drive circuit68can then be deactivated to turn off the IGBT in the protection mode. In operation, the time controller71deasserts the gate control signal VG3to PMOS transistor M3when the fault detection indicator signal VLis deasserted (logical high), or when the fixed time duration has expired, whichever is sooner. The clamped gate voltage at the output node76is therefore released. Meanwhile, the time controller70deasserts the gate control signal VG4a delayed time duration T2after the inverted fault detection indicator signal VLBis deasserted (logical low). The NMOS transistor M4is kept on after the PMOS transistor M3is turned off in order to discharge the gate terminal (node22) of the IGBT to turn off the IGBT. After the delay duration T2, the NMOS transistor M4is turned off and the NMOS transistor M2in the normal gate drive circuit34is turned back on to hold the gate terminal of the IGBT to ground before the IGBT returns to normal operation.

In embodiments of the present invention, the protection circuit of the present invention generates the clamped gate voltage for the gate drive signal (node22) that is precisely controlled and without the voltage overshoot issues typically associated with conventional Zener-diode clamping method. Furthermore, the clamped gate voltage can be precisely controlled over temperature and fabrication process variations. In some embodiments, the impedances Z3and Z4are implemented using polysilicon resistors.

FIG. 4is a timing diagram illustrating the operation of the controller circuit ofFIG. 3in some examples. Referring toFIG. 4, the input signal VIN(curve102) is a PWM signal to turn the IGBT on and off to conduct current alternately through the induction coil. The time controller88generates the gate control signal OV_Enable (104) to drive the NMOS transistor M5to enable or disable the over-voltage monitoring. In particular, the OV_Enable signal is extended by a duration T1beyond the deassertion of the input signal VINto mask the high-to-low transition of the input signal from the over-voltage monitoring. In normal operation, the gate voltage Vgctrlof the IGBT (curve110) switches between ground and the power supply voltage Vdd to turn the IGBT on and off. Meanwhile, the collector current iC(curve108) increases linearly during the on-period of the IGBT and then decreases to zero during the off-period of the IGBT. In normal operation, the gate control signals for transistors M1and M2(curves112and114) have a logical low levels during the on-period and have a logical high levels during the off-period of the IGBT. In normal operation, the gate control signal for transistor M3(curve116) is at a logical high level while the gate control signal for the transistor M4(curve118) is at a logical low level to disable the protection gate drive circuit.

During the on-period of the IGBT, the collector-to-emitter voltage VCE(curve106) is driven to the collector-emitter saturation voltage VCE-SAT. However, when the IGBT is turned off, the collector voltage can increase to a large voltage value, such as 600V. The IGBT typically has a voltage rating of 1.7 kV and can withstand the normal collector voltage excursion during the normal operation of the IGBT.

The hysteresis over-voltage detection circuit monitors the college voltage VCEof the IGBT during the off period of the IGBT and after the delay period T1which masks the on-to-off transition of the input voltage VIN. At time t1, certain power surge event causes the collector voltage VCEto exceed the set voltage level of the hysteresis over-voltage detection circuit. In one example, the set voltage level corresponds to about 1.4 kV of collector voltage. The hysteresis over-voltage detection circuit asserts the fault detection indicator signal. Within a very short time, such as by time t1, remediation measure is initiated. The gate control signal for transistor M2is disabled (logical low) to turn off transistor M2. The gate control signal for transistor M3is enabled (logical low) to turn on transistor M3while the gate control signal for transistor M4is enabled (logical high) to turn on transistor M4. As a result of transistors M3and M4being turned on, the gate voltage of the IGBT rises to the clamped gate voltage value defined by the Z3/Z4voltage divider. The IGBT is turned on by the clamped gate voltage to conduct collector current is to dissipate the power surge. As a result, the collector voltage VCEdecrease.

At time t2, the collector voltage VCEdecreases below the reset voltage level of the hysteresis over-voltage detection circuit. In one example, the reset voltage level corresponds to about 1.2 kV of collector voltage. The hysteresis over-voltage detection circuit deasserts the fault detection indicator signal and transistor M3is deasserted (logical high). Transistor M4is kept on for the extended duration of T2to discharge the gate voltage of the IGBT. At time t3, at the expiration of the duration T2, transistor M4is turned off and transistor M2is turned on to resume the normal operation.

The IGBT may then be turned on again for the normal operation. During the next off-period, the IGBT may experience additional power surge events. In this case, the transistors M3and M4are turned on again to dissipate the surge voltage. In the present example, within a single off-period, the surge voltage on the collector of the IGBT may cause the collector voltage to switch between the set voltage level and the reset voltage level multiple times. Each time the collector voltage exceeds the set voltage level, the protection gate drive circuit is enabled and each time the collector voltage drops below the reset voltage level, the protection gate drive circuit is disabled. In this manner, the protection gate drive circuit may be enabled multiple times within a single off-period to discharge the power surge.

FIG. 5illustrates the collector voltage and the collector current of the IGBT during a power surge event in some examples. Referring first toFIG. 2, the purpose of the protection circuit is to make the energy induced in the induction coil Lr to be consumed in the IGBT and to clamp the capacitor voltage Cr so that the collector voltage VCEdoes not increase over the IGBT voltage rating. Now turning toFIG. 5, the collector voltage VCEof the IGBT (curve120) and the corresponding collector current iC(curve122) are shown with the corresponding set and reset voltage levels used in the hysteresis over-voltage detection circuit. Note that the set and reset voltage levels shown inFIG. 5are the corresponding voltage levels used in the hysteresis over-voltage detection circuit. The hysteresis over-voltage detection circuit receives a stepped down collector voltage for detection and the set and reset voltage levels used in the detection circuit are therefore corresponding stepped down voltage levels.

At time t1, a power surge appears at the collector terminal of the IGBT and the collector voltage increases to the set voltage level. The protection gate drive circuit is activated to turn on the IGBT at the clamped voltage level. The collector current iCbegins to increase gradually with the clamped gate voltage being applied to the IGBT. The current flow direction of the coil current iLrchanges direction. Instead of circulating between the induction coil Lr and the capacitor Cr, the coil current iLrflows towards the IGBT to be dissipated by the IGBT to ground. The collector voltage VCEis therefore clamped and do not increase further. When current iCbecomes equal to current iLrat time t2, the voltage VCEbegins to fall by the discharge of capacitor Cr and the voltage decrease slope is decided by the collector current iCand the capacitance value of capacitor Cr. Once the voltage VCEreaches the reset level at time t3, the protection gate drive circuit is disabled and the collector current iCis turned off by a soft gate control to obtain a safe shutdown. The current falling time interval (t3-t4) makes the voltage VCEdrop a little more below the reset level. Once the protection interval is completed at time t4, the IGBT returns to normal operation.

FIG. 6is a flowchart illustrating a method for providing overvoltage or short-circuit protection for the power switching device in a quasi-resonant inverter circuit in embodiments of the present invention. Referring toFIG. 6, an over-voltage protection method200monitors a feedback voltage indicative of the voltage across the power switch during an off-period of the power switch (202). The feedback voltage is compared against an over-voltage set level OV_Set (204). In response to the feedback voltage being less than the OV_Set level, the method continues to monitor the feedback voltage indicative of the voltage across the power switch. On the other hand, in response to the feedback voltage being greater than the OV_Set level, the method200disables the normal gate drive signal (206). For example, the method200turns off the NMOS transistor M2in the normal gate drive circuit that is driving the power switch to be in the off state. Then, the method200enables the protection gate drive signal (208). For example, the PMOS transistor M3and the NMOS transistor M4in the protection gate drive circuit are both turned on to form a voltage divider with impedances Z3and Z4. The method200thus generates a clamped gate drive signal with a clamped gate voltage value (210). The clamped gate drive signal is applied to turn on the power switch. With the power switch turned on by the clamped gate drive signal, the method200monitors the feedback voltage to determine if the feedback voltage has decreased below a reset voltage level OV_Reset (212). The reset voltage level OV_Reset is lower than the set voltage level OV_Set. When the feedback voltage is below the reset voltage level, the method200disables the clamped gate drive signal and discharges the power switch gate terminal (214). The method200then enables the normal gate drive circuit (216) and the method returns to monitor the feedback voltage indicative of the voltage across the power switch during an off-period of the power switch (202).

In some embodiments, in parallel with monitoring the feedback voltage to determine if the feedback voltage has decreased below a reset voltage level OV_Reset (212), the method200also monitor a time duration for which the power switch has been turned on using the clamped gate drive signal. More specifically, the method200monitors the on-duration of the power switch to determine if the on-duration has reached or exceeded a maximum duration (220). At the expiration of the maximum duration, also referred to as the one-shot duration, the method200proceeds to turn off the clamped gate drive signal (214) even if the feedback voltage has not fallen below the reset voltage level OV_Reset. The method200continues by enabling the normal gate drive circuit (216) and the method returns to monitor the feedback voltage indicative of the voltage across the power switch during an off-period of the power switch (202).