Digitally synchronized integrator for noise rejection in system using PWM dimming signals to control brightness of light source

An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.

FIELD OF THE INVENTION

The present invention relates in general to power supply systems and subsystems thereof, and is particularly directed to a circuit and methodology for digitally synchronizing the integration period of an analog-to-digital converter (ADC) with integral multiples of the period of a periodically varying analog input signal so as to prevent variations in the output of the ADC. The present invention has particular utility in system for powering a cold cathode fluorescent lamp (CCFL) of the type employed for backlighting a liquid crystal display, wherein the duty cycle of a pulse width modulation (PWM) signal is used to controllably dim (control the brightness of) the CCFL.

BACKGROUND OF THE INVENTION

There are a variety of electrical systems which require one or more sources of power for controlling the operation of a system application device. As a non-limiting example, a liquid crystal display (LCD), such as that employed in desktop and laptop computers, or in larger display applications such as large scale television screens, requires an associated set of high AC voltage-driven cold cathode fluorescent lamps (CCFLs) or other light sources mounted directly behind it for backlighting purposes. Indeed, large LCD panels require relatively large numbers (e.g., on the order of ten to forty) of such lamps for uniform backlighting.

Adjusting the brightness (or dimming) of a CCFL is customarily effected by means of a pulse width modulation (PWM) dimming signal, which controllably switches the lamp drive voltage and current off for brief periods of time; namely, the CCFL is turned ON and OFF for relatively short periods of time (e.g., from 0.1 to 5 msec. each), with the brightness of the lamp being proportional to the PWM signal's duty cycle. This methodology may be carried out by applying a separate PWM dimming signal to each inverter.

In order to properly establish the duty cycle of the PWM dimming signal, the optical output of the CCFL is monitored to measure the average brightness of the lamp over a plurality of cycles of the PWM signal. For this purpose, an analog light sensor is optically coupled to sense the light output of the CCFL, and the output of the light sensor, the amplitude of which varies in accordance with the PWM signal being applied to the CCFL, is subjected to an integration process which yields an output that ostensibly represents the average brightness of the lamp. Where the light sensor PWM output signal is converted into digital format for downstream processing, it is necessary that the digitization process be conducted over a plurality of cycles of the optical detector's output signal in order to realize an ‘average’ of the brightness of the lamp. An undesirable ‘flickering’ problem may occur if the integration period of the analog-to-digital conversion is selected arbitrarily, with no consideration being given to whether or not the integration period is synchronized with a prescribed multiple of the period of the PWM signal produced by the optical sensor.

This problem may be readily understood by reference to the waveform diagram ofFIG. 1, which shows a fixed duty cycle PWM ‘input’ signal100, as may be produced from the output of an optical sensor monitoring the modulation of the light output of the CCFL. Beginning with the assertion of a first measurement interval reset pulse100-1in the top line ofFIG. 1, then during each of three sequential ‘high’ amplitude intervals111-1,111-2and111-3of the PWM signal110following this reset pulse, the contents of a counter/integrator within an analog-to-digital converter are incremented by a prescribed clock signal applied thereto. During each ‘low’ (or zero) amplitude interval112-1and112-2of the PWM signal110, the contents of the integrator remain unchanged. Eventually, at the end of the measurement interval, which is just prior to the second measurement interval reset pulse100-2, the counter/integrator output will be at some value121. For the illustrated example, this value is based upon the sequential incrementing of a counter during the three ‘high’ amplitude pulses111-1,111-2and111-3. Upon the assertion of the second measurement interval reset pulse100-2, the value121of the integrator/counter is latched in light output monitoring and control circuitry for the next measurement interval, and the contents of the integrator/counter are then cleared.

Then, beginning with the assertion of the next succeeding measurement interval reset signal100-2, during each of two ‘high’ amplitude interval111-4and111-5of the PWM signal110, the contents120of the counter/integrator are sequentially incremented—eventually reaching a value122, just prior to the next reset pulse100-3. As can be seen fromFIG. 1, because only two ‘high’ amplitude intervals are integrated during the integration period between measurement interval reset pulses100-2and100-3, the integration value122will be less than the integration value121. This means that upon assertion of the next reset signal100-3, the relatively reduced value122of the integrator will be latched in the light output monitoring and control circuitry for the next measurement interval.

As will be appreciated from the foregoing description and as can be seen fromFIG. 1, because the above described operations are sequentially repeated for successive integration periods, the latched values will alternately change between a relatively higher value121and a relatively lower value122, even though the average value of the input signal110itself does not change (in the absence of a change its duty cycle). This alternating of the latched value constitutes the aforementioned unwanted ‘flickering’ of the average light value output of the lamp.

SUMMARY OF THE INVENTION

In accordance with the present invention, this unwanted ‘flickering’ noise problem is effectively obviated by synchronizing the times of occurrence of the integration period reset pulses with integral multiples of the period of the PWM input signal, so that the integration periods over which an average of the light value output of the lamp is determined are the same. Pursuant to an exemplary embodiment, the overall architecture of a power supply architecture for powering, controllably adjusting (dimming) and monitoring the brightness of the output of a light source such as a cold cathode fluorescent lamp, comprises a power supply, the output of which is switched on and off at a prescribed switching frequency (e.g., 100 Hz), by a PWM dimming signal generator. The output signal F_LAMP produced by the PWM dimming signal generator is coupled to both the lamp power supply and to a DIVIDE BY N divider. The divider is operative to divide the F_LAMP signal by an integral value N, so as to produce an integration interval reset or synchronization signal (or F_SYNC pulse) having a frequency which is equal to an integral fraction of the frequency of the PWM dimming signal F_LAMP. The F_SYNC pulse is coupled to prescribed control inputs of circuitry within a synchronized integrating analog to digital converter (ADC) unit.

The integrating ADC unit contains an analog light sensor, which monitors the modulated light signal emitted by the CCFL (or other light source) and outputs a voltage that tracks the variations in the light output of the CCFL (or other light source). This ANALOG INPUT signal is coupled to an integrating ADC. During relatively high portions of the ANALOG INPUT signal, the contents of the integrating ADC, which are initially cleared or reset by the F_SYNC output of the DIVIDE BY N divider, are successively incremented by the clock output of a local clock oscillator applied to a CLK input of the ADC. The running count contents COUNT of the ADC are made available at a COUNT output port, which is coupled to an ADC REGISTER.

The F_SYNC pulse output of the DIVIDE BY N divider is also applied to a RESET/START input of an auxiliary counter, which has a clock input CLK thereof coupled to the output of the local clock oscillator, so that the contents of counter will also be incremented by the output of the clock oscillator. The running count contents of this counter are made available to a PERIOD REGISTER. Each of the PERIOD REGISTER and the ADC REGISTER has a respective LATCH input thereof coupled to the F_SYNC output of the DIVIDE BY N divider. This serves to load the running count for an immediately previous count cycle of the integrating ADC into the ADC register, and to load the count of the auxiliary counter into the PERIOD register. These latched values are coupled to an ADC/PERIOD divider, which is operative to divide the ADC register's latched count value by the period register's latched count value to provide an output that is proportional to the average input between each sync pulse F_SYNC and is independent of F_LAMP.

In operation, in response to being controllably switched ON and OFF by the PWM dimming signal F_LAMP generated by the PWM dimming signal generator, the CCFL (or other light source) power supply supplies a PWM-based energization signal to the CCFL (or other light source). The light sensor detects the PWM modulation of the optical signal as produced by the ON/OFF powering of the lamp by the power supply, and outputs an analog input signal that is supplied to the integrating ADC. Similar to the waveform diagram ofFIG. 1, described above, beginning with a first synchronization signal, for successive intervals during which the input signal has a relatively high (non-zero) voltage level, the originally cleared contents of the integrating ADC will be sequentially incremented at the frequency of clock oscillator during the relatively high portions of the ANALOG INPUT signal, so as to incrementally ramp up the count contents of the integrating ADC.

As a result of this sequential incrementing, the COUNT value contents of the ADC eventually reach a count value just prior to the occurrence of the next sync pulse F_SYNC produced by the DIVIDE BY N divider, which terminates the first integration interval and starts the second integration interval. In response to this next F_SYNC pulse, the count contents of the ADC COUNT port are transferred into the ADC register which stores the latched count value for the next integration interval. In addition to causing the count value contents of the integrating ADC to be latched in its associated ADC register, the F_SYNC pulse causes the contents of the PERIOD COUNTER, which had been initially reset by the last F_SYNC pulse, to be latched into the PERIOD REGISTER. The divider divides the ADC count value that has been latched into the ADC register by the period count value that has been latched into the PERIOD REGISTER to produce a ‘normalized’ output value that is proportional to the average input from the analog light sensor and which is independent of the frequency of the PWM signal produced by PWM dimming oscillator.

In response to the next F_SYNC signal300-2, the above described counter incrementing operations are carried out during successive count incrementing intervals, where the input signal has a relatively high (non-zero) voltage level, with the integrating ADC counting clock signals from the clock signal generator at a frequency established by the relatively high portions of the ANALOG INPUT signal, so as to incrementally ramp up the COUNT port contents of the ADC. As a result of this sequential incrementing, the contents of the ADC's output COUNT port will again eventually reach a prescribed value just prior to the occurrence of the next F_SYNC pulse produced by the DIVIDE BY N divider, which terminates the second integration interval and starts the third integration interval.

In response to the next F_SYNC pulse, the accumulated contents of the ADC are transferred into the ADC register, which stores the counter value for the next integration interval. In addition to causing the incremented contents of the integrating ADC to be latched into the ADC register, the F_SYNC pulse causes the contents of the auxiliary counter, which had been initially reset by the last F_SYNC pulse, to be latched into the PERIOD REGISTER. The divider again divides the count value that has been latched into the ADC register by the count value that has been latched into the PERIOD REGISTER to produce a value that is proportional to the average input from the analog light sensor.

The above-described process is sequentially repeated for each successive integration interval. In the absence of a change in the duty cycle of the PWM dimming signal F_LAMP, and with the F_SYNC signals being synchronized with the PWM input signals, the respective values stored in ADC register and PERIOD REGISTER will be repeatedly the same, so that there is no ‘flickering’ noise problem as occurs with a non-synchronized methodology, as described above.

By comparing the ADC COUNT/PERIOD COUNT ratio produced by the divider with a desired light output from the CCFL (or other light source), it may be determined whether an adjustment by the PWM dimming oscillator needs to be made. Where the lamp brightness is controlled by an adjustable control voltage, the output of the divider may be coupled to one input of a difference amplifier within the duty cycle control unit, a second input of which receives the brightness control voltage. The output of the difference amplifier which sets the duty cycle of the PWM dimming signal may then be coupled to the PWM oscillator, so as to provide a servo loop adjustment of the duty cycle of the PWM dimming signal in accordance with the brightness control voltage, and drive the difference between the control voltage and the output of the divider to zero.

DETAILED DESCRIPTION

Before detailing the architecture and operation of the digitally synchronized integrator of the present invention, it should be observed that the invention resides primarily in a prescribed novel arrangement of conventional controlled power supply and digital switching circuits and components therefore. Consequently, the configuration of such circuits and components and the manner in which they may be interfaced with a powered utility device, such as a cold cathode fluorescent lamp, have, for the most part, been depicted inFIG. 2of the drawings by a readily understandable schematic-block diagram, and an associated waveform diagram ofFIG. 3, which show only those specific features that are pertinent to the present invention, so as not to obscure the disclosure with details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the diagrammatic illustration ofFIG. 2is primarily intended to show the major components of the invention in a convenient functional grouping, whereby the present invention may be more readily understood.

Attention is now directed toFIG. 2, which is a schematic-block diagram of the general architecture of a power supply architecture for powering, controllably adjusting (dimming) and monitoring the brightness of the output of a cold cathode fluorescent lamp, in accordance with a preferred embodiment of the present invention. As shown therein, a CCFL200has opposite terminals201and202thereof coupled to receive a switched illumination voltage supplied from a lamp power supply210. This illumination voltage is switched on and off at a prescribed switching frequency (e.g., 100 Hz), by a PWM dimming signal F_LAMP output by a PWM dimming signal generator220that drives the lamp power supply210, as well as a DIVIDE BY N divider230. Divider230is operative to divide the F_LAMP signal by an integral value N so as to produce an integration interval reset or synchronization signal F_SYNC having a frequency which is equal to an integral fraction of the frequency of the PWM dimming signal F_LAMP. The sync F_SYNC is coupled to prescribed control inputs of circuitry within a synchronized integrating analog to digital converter (ADC) unit240, as will be described.

ADC unit240contains an analog light sensor250, which is operative to monitor the modulated light signal emitted by CCFL200and outputs an AC voltage that tracks the F_LAMP signal variations in the light output of the CCFL200. This AC voltage ANALOG INPUT is coupled to the input261of an integrating ADC260. During high portions of the ANALOG INPUT signal supplied to its input261, the contents of ADC260, which are initially cleared or reset by the output of the DIVIDE BY N divider230being applied to a RESET/START input262, are successively incremented by the clock output of a local clock oscillator270applied to a CLK input263of the ADC260. The running count contents COUNT of ADC260are made available at a count output port264, which is coupled to an ADC REGISTER280.

The output of the DIVIDE BY N divider230is also applied to a RESET/START input292of an auxiliary counter290, which has a clock input CLK293thereof coupled to the output of the local clock oscillator270, so that the contents of counter290will also be incremented by the output of the clock oscillator270. The running count contents of counter290are made available at a count port OUT294, which is coupled to a PERIOD REGISTER400. Each of PERIOD REGISTER400and ADC REGISTER280has a respective LATCH input thereof coupled to the output of the DIVIDE BY N divider. This serves to load the running count for an immediately previous count cycle of integrating ADC260into ADC register280, and the count of counter290into the PERIOD register400. These latched values are made available to an ADC/PERIOD divider410, which is operative to divide the ADC register's latched count value by the period register's latched count value to provide an output that is proportional to the average input between each sync pulse F_SYNC and is independent of F_LAMP.

The operation of the architecture ofFIG. 2may be readily understood with reference to the waveform diagrams ofFIG. 3, which will now be described. In response to being controllably switched ON and OFF by the PWM dimming signal F_LAMP generated by the PWM dimming signal generator, the CCFL power supply210supplies a PWM-based lamp energization AC signal to the CCFL200. Analog light sensor250detects the PWM modulation of the optical signal as produced by the ON/OFF powering of the lamp by the power supply210, and outputs an analog input signal that is supplied to the input261of integrating ADC260.

This analog input signal is shown at301in the timing diagram ofFIG. 3. As in the case of the waveform diagram ofFIG. 1, described above, beginning with the first synchronization signal300-1, for the intervals301-1,301-2and301-3during which the input signal has a relatively high (non-zero) voltage level, the originally cleared contents of integrating ADC260will be sequentially incremented at the frequency of clock oscillator270during the relatively high portions301of the ANALOG INPUT signal, so as to incrementally ramp up the count contents of the ADC260, as shown at ramp segments371-1,371-2and371-3.

As a result of this sequential incrementing, the COUNT value contents of the ADC260eventually reach a count value372just prior to the occurrence of the next sync pulse (F_SYNC)300-2produced by DIVIDE BY N divider230, which terminates the first integration interval and starts the second integration interval. In response to this next F_SYNC pulse300-2, the count contents of the ADC260COUNT port264are transferred into ADC register280, which stores the latched count value372for the next integration interval.

In addition to causing the count value contents of ADC260to be latched in ADC register280, F_SYNC pulse300-2causes the contents of the period counter290, which had been initially reset by F_SYNC pulse300-1, to be latched in PERIOD REGISTER400. Divider410divides the ADC count value that has been latched into the ADC register280by the period count value that has been latched into the PERIOD REGISTER400to produce a ‘normalized’ output value that is proportional to the average input from the analog light sensor250and which is independent of the frequency of the PWM signal produced by PWM dimming oscillator220.

Next, in response to the second F_SYNC signal300-2, the above described counter incrementing operations are carried out during the intervals301-4,301-5and301-6, where the input signal has a relatively high (non-zero) voltage level, with ADC260counting clock signals from clock signal generator270at a frequency established by the relatively high portions301of the ANALOG INPUT signal, to incrementally ramp up the COUNT port contents of the ADC260, as shown at ramp segments371-4,371-5and371-6. As a result of this sequential incrementing, the contents of the ADC's output COUNT port264will again eventually reach a value of 372 just prior to the occurrence of F_SYNC pulse300-3produced by DIVIDE BY N divider230, which terminates the second integration interval and starts the third integration interval.

In response to this next F_SYNC pulse300-3, the accumulated contents of ADC260are transferred into ADC register280, which stores the counter value372for the next integration interval. In addition to causing the incremented contents of ADC260to be latched in ADC register280, the F_SYNC pulse300-3causes the contents of the counter290, which had been initially reset by F_SYNC pulse300-2, to be latched in PERIOD REGISTER400. Divider410again divides the count value that has been latched into the ADC register280by the count value that has been latched into the PERIOD REGISTER400to produce a value that is proportional to the average input from the analog light sensor250.

The above-described process is sequentially repeated for each successive integration interval. In the absence of a change in the duty cycle of the PWM dimming signal F_LAMP, and with the F_SYNC signals300-1,300-2,300-3, . . . ,300-nbeing synchronized with the PWM input signals, the respective values stored in ADC register280and PERIOD REGISTER400will be repeatedly the same, so that there is no ‘flickering’ noise problem as occurs with a non-synchronized methodology, as described above.

By comparing the ADC COUNT/PERIOD COUNT ratio produced by divider410with a desired light output from the CCFL200, a determination can be made as to whether an adjustment by the PWM dimming oscillator220needs to be made. Where the lamp brightness is controlled by an adjustable control voltage as shown inFIG. 4, the output of the divider410may be coupled to one input of a difference amplifier412within the duty cycle control unit, a second input of which receives the brightness control voltage. The output of the difference amplifier412which sets the duty cycle of the PWM dimming signal may then be coupled to the PWM oscillator220, so as to provide a servo loop adjustment of the duty cycle of the PWM dimming signal in accordance with the brightness control voltage, and drive the difference between the control voltage and the output of the divider to zero.