Silicon carbide MOSFET with wave-shaped channel regions

A silicon carbide MOSFET includes a plurality of first and second trenches each of which extends a predetermined vertical distance from the top of a source down through a body region and into a current spreading layer (CSL). An insulated gate member is disposed in each first trench. The first trenches are each arranged in a wave-shaped pattern that extends in first and second lateral directions. Each of the second trenches is disposed between a pair of adjacent first trenches in the first lateral direction. A shielding region extends vertically from the bottom of each of the second trenches down into a drift region. A top metal layer fill each of the second trenches and electrically contacts the source region, the body region, the CSL, and the shielding region. A bottom metal layer electrically contacts the drain region.

TECHNICAL FIELD

The present disclosure relates to silicon carbide power semiconductor devices. More specifically, the present invention relates to silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) device structures and layouts capable of withstanding high voltages.

BACKGROUND

High-voltage, field-effect transistors, also known as power transistors or power semiconductor devices, are well known in the semiconductor arts. Most often, a high-voltage power transistor comprises a vertical transistor device structure that includes an extended drain or drift region that supports the applied high-voltage when the device is in the “off” state. Power transistors of this type are commonly used in power conversion applications such as AC/DC converters for offline power supplies, motor controls, and so on. These power transistor devices can be switched at high voltages and achieve a high blocking voltage in the “off” state while minimizing the resistance to current flow between the drain and source, often referred to as the specific on-resistance (Ron), in the “on” state.

Power MOSFETs are commonly based on silicon and other wide bandgap semiconductor materials, such as silicon carbide. Silicon carbide (SiC) MOSFETs are advantageously utilized in certain electronic devices due to their superior physical properties over silicon-based devices of the same device area. For example, SiC MOSFETs are known to exhibit higher blocking voltage, lower Ron, and higher thermal conductivity as compared to silicon MOSFETs. A double-implanted metal-oxide semiconductor field-effect transistor (DMOSFET) may be formed in a SiC substrate.

Another traditional structure used in power SiC MOSFETs is a U-shaped MOSFET (UMOSFET), also referred to as a trench-gate or trench MOSFET. In fabricating a SiC UMOSFET a deep vertical trench is typically formed in the SiC substrate using a process known as reactive ion etching. A dielectric (e.g., silicon dioxide) is then formed on along the sidewalls and bottom of the trench. The remaining area inside the trench is then typically filled with polysilicon, which functions as the gate of the MOSFET. During operation in the on-state a conductive channel region is formed along the vertical sidewall of the trench.

Many power MOSFETs employ a device structure that includes an extended drain region that supports or blocks the applied high-voltage (e.g., hundreds of volts or more) when the device is in the “off” state. In a conventional vertical power MOSFET device structure, an epitaxial layer of semiconductor material forms an extended drain or drift region for current flow in the on-state. Application of an appropriate voltage potential to the gate causes a conductive channel to be formed in a body region such that current may flow through the channel and then vertically downward through semiconductor material, i.e., from a top surface of the SiC substrate where the source region is disposed, down to the bottom of the SiC substrate where the drain region is located.

The specific on-resistance (Ron) in a vertical power MOSFET is a combination of the channel resistance, JFET resistance, drift region resistance and substrate resistance. The channel resistance is a function of semiconductor material, channel width, channel length, operating conditions (e.g., drain current and voltage), carrier mobility and cell pitch. For optimal performance in the on-state, it is desirable to minimize Ron. In a SiC power transistor device channel resistance is relatively high and carrier mobility is relatively low. However, drift region resistance is a direct function of blocking voltage. Consequently, channel resistance dominates Ronat voltages less than about 1200 volts.

Past approaches to reducing the drain-to-source on-resistance of SiC power MOSFETs have typically required complicated processing steps including trenches, new technologies, or trade-offs with respect to other device performance parameters, e.g., breakdown voltage. Additionally, attempts to lower Ronby reducing the length of the channel region have been largely unsuccessful as it adds leakage that lowers the blocking voltage of the device.

In a traditional trench MOSFET structure the highest electric field while blocking drain-source voltage in the off-state is located at the bottom corner of the trench. For instance, SiC avalanche breakdown typically starts at ˜2.2 MV/cm. Scaling for the different dielectric constant between SiO2and silicon, the maximum electric field in SiO2is greater than 6 MV/cm before SiC breaks down.

DETAILED DESCRIPTION

In the following description numerous specific details are set forth in order to provide a thorough understanding of the disclosed subject matter. It will be apparent, however, to one having ordinary skill in the art that the specific details need not be employed to practice the various embodiments described. In other instances, well-known systems, devices, or methods have not been described in detail in order to avoid obscuring the disclosed subject matter.

As used herein, a “wafer” is a thin slice of crystalline material, such as silicon carbide, used in the fabrication of semiconductor devices and integrated circuits. The term “substrate” refers to the semiconductor supporting material upon which or within which the elements of a semiconductor device are fabricated, which substantially comprises the thickness of a wafer. Upon completion of the fabrication process the wafer is typically scribed and broken into individual semiconductor die, each of which consists of one or more semiconductor devices.

In the context of the present application, when a transistor is in an “off state” or “off” the transistor does not substantially conduct current. Conversely, when a transistor is in an “on state” or “on” the transistor is able to substantially conduct current. By way of example, a power transistor may comprise an N-channel MOSFET with a SiC substrate and SiC epitaxial layer which, in the off-state, supports a high blocking voltage between the first terminal, a drain, and the second terminal, a source. The power MOSFET may comprise a power switch that is driven by an integrated controller circuit to regulate energy provided to a load.

A SiC MOSFET device structure having a layout with serpentine or wave-shaped regions is described. In one embodiment, a planar SiC MOSFET device structure has a layout that provides a lower specific on-state resistance as compared to prior art approaches, while supporting very high voltages in the off-state. In other embodiments the planar SiC MOSFET device structure layout is modified to reduce lateral transistor cell pitch, which further helps lower Ron.

In yet another embodiment, a trench SiC MOSFET device structure has a layout with wave-shaped trenches wherein conduction channels are formed along the sidewalls of the trenches when the device in is the on-state. The trench SiC MOSFET device structure includes a deep P+ implant region disposed beneath the bottom of a second type of trench or pit. The deep P+ region functions to shield the gate oxide of the MOSFETs from high electric fields in the off or blocking state.

FIG. 1is a top level view of an example planar layout for a single SiC MOSFET10with channel regions11arranged in a serpentine or wave-shaped layout pattern. It is appreciated that the portion of the layout shown may represent a single transistor cell. The transistor cell shown may be replicated in a mirrored or translated fashion many times in both the X and Y lateral directions across a wafer to form a completely fabricated MOSFET device. Thus, there may be repetitions of the wave-shaped regions across the semiconductor die. The MOSFET10ofFIG. 1includes highly-doped N+ source regions12a&12bthat adjoin the outer sidewalls or boundaries of respective low-doped P-type channel regions11a&11b. A centrally-located N+ JFET region13adjoins the inner sidewalls of channel regions11a&11b.

Each of the channel regions11in the example ofFIG. 1is formed as a serpentine or wave-shaped pattern of semi-circular regions that extend in the lateral X and Y directions, with the semi-circular regions alternating orientation by 180 degrees in a wave-like manner along the lateral Y-direction. The channel length, as measured at any tangential point along the sides of channel regions11is a constant length. In one embodiment the channel length is about 0.6 μm. In other words, the radius of the inner and outer semi-circular sides that define the wave-shape of channels11are determined to be an identical distance so that the channel length separating source12from JFET region13is constant length. By way of example, adjacent semi-circular portions of channel11aare shown inFIG. 1having radiuses R1=R2=R3=R4.

Practitioners in the art will appreciate that the wave-shaped channel regions11a&11bare shown inFIG. 1as being in-phase. That is, each channel region11“crests” toward the right-hand side of the cell in the X-direction at the same points in the Y-direction. Similarly, each channel region11“crests” toward the left-hand side of the cell in the X-direction at the same points in the Y-direction.

Also shown in the layout of SiC MOSFET10are a plurality of circular-shaped, highly-doped P+ body regions14that adjoin source regions12. For instance, P+ body regions14a&14care shown laterally adjoining source region12a. Likewise, P+ body regions14b&14dare shown laterally adjoining source region12b. Note that P+ body regions14a&14care located in pocket areas to the left of channel region11a, and P+ body regions14b&14dare located in pocket areas to the right of channel region11b.

In addition, the locations of P+ body regions14b&14din the Y-direction are 180 degrees out-of-phase with respect to the position in the Y-direction of P+ body regions14a&14c. P+ body regions14a&14care respectively located under the semi-circular portions (pockets) of channel region11athat are shown cresting toward the right-hand side of the cell, whereas P+ body regions14b&14dare respectively located under the semi-circular portions (pockets) of channel region11bthat are shown cresting toward the left-hand side of the transistor cell. In one embodiment, the radius of each P+ body region14is about 1.1 μm.

It should be understood that in other embodiments there need not be a P+ body region disposed under each cresting portion of the wave-shaped channel regions. In other words, other embodiments may have fewer P+ body regions than what is shown inFIG. 1, with the P+ body regions being farther spaced-apart in the Y-direction. Reducing the number of P+ body regions may decrease source resistance versus body contact resistance. Furthermore, in still other embodiments, the shape of the P+ body regions need not be circular in shape; instead, they may be formed as other curved or rectilinear shapes.

Practitioners in the art will appreciate that locating the P+ body regions in the pocket areas of the wave-shaped channel regions helps to reduce cell pitch in the lateral X direction, which reduces Ron. In addition, the width of the channel in the Y direction is increased due to the wave-shaped layout, which substantially reduces the channel resistance, thereby further reducing Ron. Because the channel length is the same along all points of the wave-shaped channel region the likelihood of leakage due to short channel effect is also reduced.

FIG. 2is an example cross-sectional side view of the SiC MOSFET device layout shown inFIG. 1, taken along cut lines A-A′. SiC MOSFET10is a vertical transistor structure with a highly-doped N+ drain region21disposed on a planar surface24of the bottom SiC substrate28. A bottom metal layer23forms a drain terminal that provides electrical (ohmic) contact with N+ drain region21. A lightly-doped N− epitaxial layer20is disposed above N+ drain21and bottom substrate28. Epitaxial layer20forms an extended drain or drift region of SiC MOSFET10. Epitaxial layer20may be formed by a Chemical Vapor Deposition (CVD) process.

A highly-doped N+ current spreading layer (CSL)17is shown disposed above N− epitaxy layer20. A portion of N+ CSL17is shown extending up to a top planar surface25of the substrate. The portion that extends up to top surface25forms the JFET region13of SiC MOSFET10. JFET region13is bounded laterally by low-doped P− well regions16a&16b. Extending to top surface25and disposed within P− well regions16a&16bare respective N+ source regions12&12b. A P+ body region14dis also shown disposed in P− well16bat top surface25adjoining N+ source region12b.

The channel regions11a&11bare defined in the substrate where the respective P− wells16a&16bextend up to top planar surface25. The length of each channel region11is measured by the lateral distance between the source region12and JFET region13.

By way of example, for a 1200 V MOSFET device N− epitaxial layer20may have a doping concentration of about 9E15/cm3 and a thickness of about 10 μm. Bottom SiC substrate28may have a doping concentration of about 4E18/cm3 with the thickness being in a range of 100 μm to 360 μm. P− wells16are about 1 μm deep beneath top surface25and have a retrograde doping profile of about 2E18/cm3 near the junction with N− epitaxial layer20lowering to about 1E17/cm3 in the channel region11near top surface25. N+ source regions12and P+ body regions14are both shallow and doped to a concentration of about 1E19/cm3. JFET region13typically has a doping that is higher than N− epitaxial layer20, but much lower than N+ source regions12.

Continuing with the example ofFIG. 2, a gate member15is shown disposed above channel regions11a&11b, JFET region13, and a small portion of N+ source regions12a&12b. In one embodiment, gate member15comprises polysilicon. A thin gate dielectric (e.g., oxide) separates gate member15from top surface25of the semiconductor substrate. An interlayer dielectric (ILD)18covers the top and sides of gate member15, fully insulating gate member15from top metal layer22. Top metal layer22comprises a source terminal that electrically contacts source regions12a&12band P+ body region14d.

In the top view ofFIG. 1, gate member15is not shown for clarity reasons. However, persons of skill in the art would understand that gate member15may extend from slightly past the left-side of channel region11ato slightly past the right-side of channel region11b. Gate member15follows the same serpentine pattern along the far sides of channel regions11a&11b.

When a sufficiently high voltage is applied to gate member15relative to source region12, a conduction channel forms just beneath top planar surface25in each channel region11. Thus, in the on-state current flows in MOSFET10horizontally from source regions12to JFET region13, and then vertically down through CSL17and N− epitaxy layer (extended drain region)20to N+ drain region21.

It is appreciated that in one embodiment MOSFET10may be fabricated as a double-implanted metal-oxide, semiconductor field-effect transistor (DMOSFET).

FIG. 3is a top level view of another example layout for a SiC MOSFET device structure with regions having a serpentine or wave-shaped pattern, where the curved wave-shape is interrupted by straight sections. The layout ofFIG. 3shows JFET regions33a-33chaving a serpentine shape with straight sections38that are alternately connected by curved sections37&39. It is appreciated that sections37&39are identically-shaped but mirrored with respect to one another. As shown, ascending section37shifts the serpentine layout up in the X direction and descending section39shifts it down in the X direction. Note that the straight sections38are all aligned with each other in the X direction with adjacent serpentine-shaped JFET regions being 180 degrees out-of-phase. This layout causes the straight sections of adjacent JFET regions33band33cto be alternately separated by a wide distance d1and a narrow distance d2measured in the X direction.

Adjacent JFET regions33are shown being separated in the X direction by P− well regions36. For example, JFET region33ais separated from JFET region33bby P− well region36c, and JFET region33bis separated from JFET region33cby P− well region36b. A square-shaped P+ body region (contact)34is shown centrally-disposed in each area where adjacent straight sections38are separated by wide distance d1. For instance, P+ body regions34a&34eare shown centrally-disposed in the areas of P− well region36bbetween the straight sections38of adjacent JFET regions33b&33cthat are separated by distance d1. Similarly, P+ body region34cis shown centrally-disposed in the area of P− well36cbetween the straight sections38of adjacent JFET regions33a&33bthat are separated by distance d1.

It is appreciated that in other embodiments, not every area of P− well region36between the straight sections38of adjacent JFET regions33may include a P+ body region34.

Note that the source regions are not shown in the top view ofFIG. 3for clarity reasons. Persons of skill in the art will understand that the source regions adjoin P+ regions34covering the P− well regions except for the narrow channel regions disposed on opposite sides of the JFET regions. The channel regions follow the serpentine shape of each of the JFET regions. It is appreciated that an N+ source implant may be utilized to form the N+ source regions that define the channel regions (seeFIG. 1). The p-type channel regions are the part of the P− well regions36that are not implanted with the N+ source impurity.

It is appreciated that in different embodiments the length of the straight sections in the Y direction, as well as the length and shape of the curved sections, may vary. Practitioners in the art will understand that longer straight sections reduce source contact resistance, whereas shorter straight sections increase the wave nature of the channel, thus reducing channel resistance. Similarly, the shape of the P+ body regions may vary, e.g., oval, circular, rectangular, etc. In still other embodiments, the SiC MOSFET may include a combination of short and long straight sections, with the short sections being aligned with each other, and the long sections being aligned with each other, in the X direction.

FIG. 4is a top level view of the example layout ofFIG. 3additionally showing the location of gate members45. For example, dashed lines45a&45bdefine the lateral sides of a gate member that extends over JFET region33c, the adjoining channel regions, and a portion of the N+ source that adjoins the channel regions. Likewise, dashed lines45c&45ddefine the lateral sides of a gate member that extends over JFET region33b, and dashed lines45e&45fdefine the lateral sides of a gate member that extends over JFET region33a.

FIG. 5is a top level view of another example layout for a SiC MOSFET device52with a single gate member55. In this example layout the pitch in the X direction is substantially reduced, as compared with a conventional MOSFET (no wavy layout), such that adjacent wave-shaped JFET regions53are located close enough that the individual gate members (shown inFIG. 4) merge together to form a single gate member55. Gate member55is shown covering the entire layout except for oval or racetrack-shaped open areas56where a P+ body region54is centrally-located. For example, gate member55covers JFET regions53a&53band the area in between, except for the racetrack-shaped opening56cthat includes P+ body region54c. Similarly, gate member55covers JFET regions53b&53cand the area in between, except for the racetrack-shaped areas56b&56fthat respectively include P+ body regions54e&54a.

Note that the N+ source regions and the P− well regions are not shown in the layout ofFIG. 5for clarity reasons. Persons of skill in the art will understand that the P− well regions extend in the area between adjacent JFET regions53. The N+ source regions cover the P− well regions except for the area adjacent the sides of JFET regions53where the channel regions are disposed. It should also be understood that the top metal layer that forms the source terminal of MOSFET52electrically contacts the N+ source regions and P+ body regions54only within the open areas56. Gate member55is completely insulated from the top metal layer by an interlayer dielectric material (e.g., ILD18inFIG. 2).

Practitioners in the semiconductor arts will appreciate that the layout shown inFIG. 5reduces pitch in the X direction, thereby increasing the total channel width in a given area, thus reducing channel resistance and hence Ron, as compared to the embodiments shown inFIGS. 3 & 4. In one embodiment with a channel length of about 1 μm, a JFET width of 1.4 μm, a 200 μm substrate thickness, and a 5 μm pitch(x), specific on-resistance was measured at 3.65 milliohms×cm2, which is 12.5% lower than a conventional SiC MOSFET without serpentine or wavy regions. It is understood that improvement in the channel resistance may come at the expense of a slightly increased source resistance due to reduced source contact area, but Ronis improved overall.

Persons of skill in the semiconductor arts will understand that in other embodiments there need not be a P+ body region contact54in each gate polysilicon opening56.

Trench MOSFET with Wave-Shaped Channel Regions

FIG. 6is a top level view of an example layout for a SIC UMOSFET60that includes a plurality of trenches63having a serpentine or wave-shaped pattern, where the curved wave-shape is alternately interrupted by straight sections. The layout ofFIG. 6shows trenches63a-63deach having a serpentine shape with straight sections68that are alternately connected by curved sections67&69. It is appreciated that sections67&69are identically-shaped but mirrored with respect to one another.

As shown, ascending section69shifts the wave-shaped layout up in the X direction and descending section67shifts it down in the X direction. Note that the straight sections68are all aligned with each other in the X direction with adjacent serpentine-shaped trenches63being 180 degrees out-of-phase. This layout causes the straight sections of adjacent trenches63to be alternately separated by a wide distance d1 and a narrow distance d2 measured in the X direction. Straight sections68each extend a lateral distance d3 in in the Y direction.

Another way to look at it is that the wave-shaped pattern of adjacent first trenches are arranged 180 degrees out of phase with one another such that the adjacent first trenches are alternately separated in the first lateral direction by minimum distance (d2) and then a maximum distance (d1) as the adjacent first trenches extend along the second lateral direction.

In one embodiment, the distance d1 may vary in a range of 1.8 μm to 3.0 μm; d2 may vary in a range of 0.6 μm to 1.0 μm; and d3 may vary in a range of 0.5 μm to 5.0 μm.

Also shown in the layout ofFIG. 6is a plurality of rounded rectangular trenches64a-64g, each of which is centrally disposed in the area of the semiconductor substrate where trenches63are separated by the wide distance d1. For example, trenches64b&64care respectively disposed in the wide areas between trenches63a&63b; trench64dis disposed in the wide area between trenches63b&63c, and trenches64e&64fare respectively disposed in the wide areas between trenches63c&63d. The cross-hatched area surrounding trenches64, and between trenches63comprise the N+ source region66of the UMOSFET device. As shown, the lateral length of each trench64in the Y direction is substantially the same as the lateral distance d3 of each straight section of trenches63. The lateral width of each trench64in the X direction is shown as the distance d4, which in one embodiment is in a range of about 0.6 μm to 1.0 μm. In one embodiment, the parallel sidewalls of adjacent trenches64&63are equally spaced-apart by predetermined distances in the X and Y directions.

Persons of skill in the semiconductor arts will appreciate that in the completely fabricated UMOSFET60a serpentine or wave-shaped gate member is disposed in each trench63. The gate member is insulated from the adjacent N+ source region66by a thin gate oxide or other dielectric material. In the completed device, a deep P+ shield region is formed by ion implantation beneath the bottom of each trench64. The P+ shield region functions to protect the bottom corner regions of the gate oxide in the adjacent trenches63from high electric fields, which makes the SiC UMOSFET block voltage reliable.

FIG. 7is an example cross-sectional side view of UMOSFET60shown inFIG. 6, as taken along cut lines A-A′. As shown, MOSFET60includes N+ source region66disposed at the top of the substrate. A P-type body region61vertically separates N+ source region66from N+ CSL region62. A top metal layer71covers N+ source region66along the top planar surface of the SiC substrate and completely fills trench64d, making ohmic contact and anchoring the trench sidewalls and bottom to the source potential. In this example, the bottom of trench64dextends downward into N+ CSL region62.

A P+ shield implant region72dis shown vertically extending from the bottom of trench64ddeeply into N-type epitaxial drift region74, which is disposed directly above N+ drain substrate75. A bottom metal layer77forms the drain contact that provides an electrical connection to the bottom planar surface of N+ drain substrate75. Note that P+ shield implant region72dextends upward to the top of the adjacent substrate mesas. In addition to creating P+ region72dbeneath trench64d, the P-type dopant is also implanted to a shallow extend on the sidewalls of trench64d. This implant converts the entire trench sidewall surface to P+ doping.

Top metal71forms a source and shield contact. In addition to providing an electrical contact with source66, metal71also makes electrical contact with body region61, CSL62and P+ shield region72d.

FIG. 8is an example cross-sectional side view of the SiC UMOSFET60shown inFIG. 6, as taken along cut lines B-B′. Four UMOSFET trenches63a-63dand two shield trenches64cand64fare shown laterally spaced-apart in this cross-sectional view. Each of the MOSFET trenches63a-63dare shown having vertical sidewalls covered with a gate oxide78. Oxide is also shown covering the top and bottom of each trench to fully insulate corresponding polysilicon gate members73a-73dfrom the laterally adjacent SiC mesas. Each mesa includes N+ source region66disposed at the top planar surface79of the substrate, P body region61and N+ CSL62. Each trench63down into N+ CSL62. In the on-state a vertical conduction channel is formed in P body region61along the sidewall of each MOSFET trench63.

In one embodiment, the width in the X direction of each trench63and mesa is about 1.0 μm. Thus, in one embodiment UMOSFET60has four channel regions in a cell pitch of 6.0 μm, which amounts to 1.5 μm/channel. This can be seen by tracing a full pitch along the cross-section B-B′. This represents a substantial reduction in pitch reduction compared to prior art device structures. In addition to pitch reduction, channel width (as measured along the length of the sidewalls of wave-shaped trenches63in the Y direction) within a cell is greater as compared with prior art stripe channel designs. This is due to the fact that the length of a wave between any two points is necessarily longer than a straight line connected them. Persons of skill will also understand that compared with traditional trench SiC MOSFET device structures, UMOSFET60has less of a JFET pinch-effect, and hence lower specific on-resistance (Ron).

Continuing with the cross-section ofFIG. 8, shield trench64fis shown laterally disposed between MOSFET trenches63c&63d. Similarly, shield trench64cis shown laterally disposed between MOSFET trenches63a&63b. Each trench64is disposed not more than a predetermined distance from the adjacent serpentine or wave-shaped trenches63. Persons of skill in the art will appreciate that spacing apart trenches64a fixed distance from wave-shaped trenches63eliminates the risk of having the P+ shield implant affect channel doping adjoining the sidewalls of trenches63. At the same time, the P+ shield implant converts the semiconductor sidewalls of trenches64to P+ doping, thus providing ohmic contact with the adjoining semiconductor regions61,62,66and epitaxial drift region (layer)74.

As shown, P+ shield implant regions72f&72cextend deep into drift region74beneath respective trenches64f&64cto advantageously protect the bottom corner areas of the gate oxide regions78from potentially damaging high electric fields. In one embodiment, each P+ shield implant region extends 2.0-3.0 μm beneath the bottom of corresponding trenches64. Since the vertical sidewalls of trenches64are implanted by glancing ions of lower energy, implant depths into the lateral sidewalls are considerably less deep, i.e., less than 10% of the vertical implant depth at the bottom of trenches64.

Note that the adjacent-facing sidewalls of trenches63b&63care separated laterally by distance d2, whereas the adjacent-facing sidewalls of trenches63a&63b, as well as trenches63c&63d, are separated laterally by distance d1. Note further that all of the trenches63&64are formed to the same vertical depth beneath top planar substrate surface79.

FIG. 9is an example cross-sectional side view of SiC UMOSFET60shown inFIG. 6, as taken along cut lines C-C′. As shown, trenches63a-63dare substantially equally spaced apart from one another without any trenches64in the cross-section. That means that this view is through MOSFET cells only. It is also appreciated that the view of trenches63is taken through a curved section (either67or69) of the wave shape, and not through any straight section68.

FIGS. 10A-10Dshow example cross-sectional side views of a SiC wafer at various stages of the fabrication process of the SiC UMOSFET shown inFIG. 6, as taken along cut lines B-B′.FIG. 10Ashows a SiC wafer80after formation of various semiconductor layers. As shown, a highly-doped N+ drain substrate75is disposed at the bottom planar surface of SiC wafer80. A lightly-doped N− epitaxial layer74is shown formed above N+ drain substrate75. Epitaxial layer74functions an extended drain or drift region of SiC UMOSFET. Epitaxial layer74may be formed by a Chemical Vapor Deposition (CVD) process.

A highly-doped N+ current spreading layer (CSL)62is shown formed on top of N− epitaxy layer74. A P-type body61is formed on top of N+ CSL62. An N+ source66is shown formed beneath top planar substrate surface79directly above P-type body61.

By way of example, in one embodiment of a 1200 V UMOSFET device N− epitaxial layer74may have a doping concentration of about 9E15/cm3 and a thickness of about 10 μm. Bottom N+ drain substrate75may have a doping concentration of about 4E18/cm3 with the thickness being in a range of 100 μm to 360 μm. N+ source66is shallow and doped to a concentration of about 1E19/cm3. P-type body61is doped to a concentration of about 1E17/cm3, and has a thickness of about 1 μm. N+ CSL62is doped to a concentration of about 1E17/cm3 and has a thickness of 0.75 μm.

FIG. 10Bshows SiC wafer80after masking and reactive ion etching steps that form MOSFET trenches63a-63dand shielding trenches64c&64f. Trenches63and64may be etched together to the same depth. Both trenches63and64define a plurality of MOSFET mesas that extend from top substrate surface79down into N+ CSL62. Each mesa consists of stacked regions N+ CSL62, P-type body61and N+ source66.

FIG. 10Cshows SiC wafer80after ion implantation81that forms P+ shield regions72f&72cthat extend downward into N-epitaxial drift region74beneath trenches64f&64c. Note that ion implantation81also forms shallow P+ regions72f&72con the sidewalls of trenches64f&64c, converting the semiconductor sidewall regions62,61and62to P+ doping. In one embodiment, P+ shield regions72f&72care doped to a concentration of about 2E19/cm3.

FIG. 10Dshows SiC wafer80after masking and oxidation steps that form gate oxide layers78along the sidewalls of MOSFET trenches63a-63d. After the gate oxide has been grown, each of trenches63are filled with polysilicon, which forms the gate members of the MOSFET cells. The top of the polysilicon gate members may be oxidized or otherwise insulated from the subsequent metallization steps that form the source and drain contacts on the respective top and bottom surfaces of wafer80.

FIG. 11is a top level view of another example layout for a SiC UMOSFET90having wave-shaped trenches93a-93d. The layout of UMOSFET90is similar to that shown inFIG. 6, except that there are no parallel straight sections, and the shielding trenches94have a circular shape (cylindrically into the SiC substrate) instead of a rectangular shape.

Each of the serpentine or wave-shaped trenches93are laterally surrounded at the top substrate surface by N+ source regions96. As shown, in the X direction, the wave shapes of adjacent trenches93are 180 degrees out of phase. Each trench94is disposed in the central area of N+ source region96where adjacent trenches93are farthest apart in the X direction. As can be seen, trenches94band94care disposed between MOSFET trenches93aand93b; trench94dis disposed between trenches93band93c; and trenches94eand94fare disposed between MOSFET trenches93cand93d.

Practitioners in the art will appreciate that the cross-sectional side views of SiC UMOSFET90taken along cut lines A-A′, B-B′ and C-C′ are substantially the same as those shown in respectiveFIGS. 7-9. That is, all of the doped semiconductor layers/regions are the same and all of the trenches93&94have the same depth of corresponding features shown inFIG. 6. The primary difference is the lateral size (diameter) of trench94din the Y direction, taken along cut line A-A′, is substantially shorter than the length of trench64din the Y direction.

It is appreciated that in the example shown inFIG. 11the diameter of each trench94is substantially equal in dimension to the lateral width of each trench93in the X direction (e.g., 1 μm). In other embodiments, the size of trenches94cmay vary, as well as the lateral spacing and size in relation to MOSFET trenches93a&93b. In other words, in certain embodiments the diameter of each trench94may be larger or smaller than the lateral width of each trench93, as measured in the X direction.

The above description of illustrated example embodiments, including what is described in the Abstract, are not intended to be exhaustive or to be limitations to the precise forms or structures disclosed. While specific embodiments and examples of the subject matter described herein are for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example thicknesses, dimensions, material types, concentrations, voltages, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.