TRANSISTORS WITH SOURCE-CONNECTED FIELD PLATES

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

FIELD OF THE INVENTION

Embodiments of the subject matter described herein relate generally to semiconductor devices with conductive elements and methods for fabricating such devices.

BACKGROUND OF THE INVENTION

Semiconductor devices find application in a wide variety of electronic components and systems. High power, high frequency transistors find application in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly suited for these RF power and power electronics applications due to its superior electronic and thermal characteristics. In particular, the high electron velocity and high breakdown field strength of GaN make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. Field plates are used to reduce gate-drain feedback capacitance and to increase device breakdown voltage in high frequency transistors. Accordingly, there is a need for semiconductor and, in particular, GaN devices with field plates.

SUMMARY OF THE INVENTION

In an example embodiment, a method of fabricating a semiconductor device is provided. The method includes depositing interlayer dielectric material over a first dielectric layer and a first electrode on a semiconductor substrate. The first dielectric layer is disposed above a channel region of the semiconductor substrate suitable for use as a semiconductive transistor channel; the first electrode extends within a first aperture in the first dielectric layer and contacts a top surface of the channel region within the aperture; and the first electrode is disposed between a first current terminal electrically coupled to a first end of the channel region and a second current terminal electrically coupled to a second end the channel region opposite the first end of the channel region.

The method further includes performing a first patterning step that includes selectively removing the interlayer dielectric material in a first region between the first electrode and the second current terminal, thereby leaving remaining dielectric material that includes the first dielectric material above the channel region. The method also includes forming a second electrode in the first region having first and second ends. The first end of the second electrode is adjacent to the first electrode. The first end of the second electrode separated from the top surface of the channel region by at least the first dielectric layer. The second end of the second electrode is disposed above the first electrode and is separated from the first electrode by the remaining interlayer dielectric material.

Finally, the method further includes forming a conductive interconnect that extends between the first current terminal and the second electrode and electrically couples the second electrode to the first current terminal. The interconnect is disposed above the first electrode and the remaining interlayer dielectric material.

In another example embodiment, a semiconductor device is provided. The device includes a channel region defined in a semiconductor substrate; a first current terminal electrically coupled to a first end of the channel region; and a second current terminal electrically coupled to a second end of the channel region opposite the first end. The device also has a first dielectric material having a first dielectric thickness and overlying the channel region; a first interlayer dielectric material overlying the channel and the first electrode; and second interlayer dielectric material overlying the first interlayer dielectric material.

The device has a first aperture in the first dielectric material that overlies the channel region in between the first current terminal and the second current terminal; and an electrically conductive first electrode that extends within the first aperture that is in direct physical contact with a top surface of the channel region. The device also has an electrically conductive second electrode spaced apart from the first electrode.

The second electrode has a first end that overlies at least the first dielectric material and the channel region at a location between the first electrode and the second current terminal; and a second end that overlies at least a portion of the first electrode that is separated from the first electrode by the first and second interlayer dielectric materials. The device is configured to provide an electrically conductive path from the first current terminal to the second current terminal via the channel region when a sufficient control voltage is applied to the first electrode.

DETAILED DESCRIPTION

The following detailed description is exemplary in nature and is not intended to limit the invention or the application and uses of the same. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.

For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.

Directional references such as “top,” “bottom,” “left,” “right,” “above,” “below,” and so forth, unless otherwise stated, are not intended to require any preferred orientation, and are made with reference to the orientation of the corresponding figure or figures for purposes of illustration.

FIG.1is a cross-sectional schematic view of example transistor100provided with an electrode150suitable for use as a field plate according to embodiments herein. The transistor100is formed on a semiconductor substrate102and has a channel region110near a top surface112of the substrate102. The transistor includes a first current terminal120electrically coupled to a first end of the channel region110and a second current terminal125electrically coupled to a second end of the channel110opposite the first current terminal120. A first dielectric material115is disposed on the top surface112overlying the channel region110. The first current terminal120and the second current terminal125may be formed by any suitable method. For example, they may be appropriately doped regions within the semiconductor substrate102, or as metallic contacts deposited within recesses in the substrate102or on the surface of the substrate102.

A conductive first electrode (hereinafter a gate electrode130) contacts the channel region110through an aperture in the first dielectric material115. As shown, the gate electrode130may have a first portion132that contacts the channel region110within the aperture and optionally has a second portion134that overhangs the first dielectric material115. Although the gate electrode130is depicted as having vertical sidewalls, it will be understood that the first electrode130may have any suitable geometry. For instance, the first portion132of the gate electrode may have sidewalls that are curved or slanted. Similarly, the second portion134of the gate electrode130may be have sidewalls that are curved or slanted and the top of the gate electrode130(farthest from the channel region110) my have any suitable geometry. The gate electrode130is disposed in between the first current terminal120and the second current terminal125along the length of the channel region110.

It will be appreciated that the first current terminal120may be operated, for example, as a source terminal of the transistor100and the second current terminal125may be operated, for example, as a drain terminal of the transistor100. It also be understood that the gate electrode130is suitable for use as a gate electrode of the transistor100such that, when a suitable bias voltage is applied to the gate electrode130, the channel region110is configured to provide an electrically conductive path between the first current terminal120and the second current terminal125.

Additional dielectric material140overlies the gate electrode130and various portions of the channel region110. This additional dielectric material140may include a second dielectric material142and a third dielectric material144as shown inFIG.1. As shown inFIG.1, the transistor100also includes a second electrode (hereinafter a field plate150with a first end152disposed above the channel region110in between the gate electrode130and the second current terminal125. A second end154of the field plate150overlies the gate electrode130. An electrically conductive interconnect160has a first end162coupled to the first current terminal120and a second end164that electrically couples the field plate150to the first current terminal120.

It will be understood that, when the first current terminal120is operated as a source terminal of the transistor100, the field plate150is configured to operate as source-coupled field plate. In the transistor100, the conductance of the channel region110during operation of the transistor100will be influenced by the electrical potential of the gate electrode130and the field plate150. It will be appreciated that the first end152of the field plate150is capacitively coupled to the channel region110across the first dielectric material115and the second dielectric material142. Meanwhile the interconnect160is separated from the gate electrode130and the channel region110by both the dielectric materials142,144.

Generally, a source-coupled field plate such as the field plate150may be used to reduce gate-to-drain feedback capacitance (“CGD”) in transistors such as the transistor100when compared to otherwise similar transistors lacking such a field plate. However, the addition of a source-coupled field plate spaced apart from a gate electrode such as the gate electrode130will also tend to introduce additional capacitance between the gate and the source (“CGS”) which is often an undesirable trade-off. Often, a single dielectric may be deposited over a substrate that has already been provided with a channel region and a gate. In this instance, both the CGDreduction provided by a source field plate and the increased CGSassociated with the field plate will depend strongly on the thickness and dielectric properties of that single dielectric layer.

Meanwhile, in the transistor100the use of multiple dielectric layers configured as described may confer certain advantages Specifically, the relative dielectric constants and thicknesses of each of these materials may be chosen to achieve desired performance characteristics and to facilitate various fabrication procedures in embodiments herein, such as mixing use of oxide and nitride materials with different dielectric constants and etch selectivity. For instance, in the example ofFIG.1, the relative thicknesses and dielectric constants of the first dielectric material115and the second dielectric material142will tend to determine the effect of the field plate150(operating as a source-coupled field plate) on the channel region110and CGDof the transistor100. (i.e., the capacitance between the gate electrode130and the second current terminal125). Meanwhile, the dielectric constants and thicknesses of the third dielectric material144together with the second dielectric material142will largely determine the addition CGSpenalty. Thus, a material with a relatively high dielectric constant may be chosen for the dielectric material142to maximize the influence of the field plate150on the channel region110. If the dielectric material142was the only material separating the interconnect160from the gate electrode130, the resulting additional CGSmight be undesirably large. However, the CGSpenalty introduced by the field plate150and interconnect160overlying the gate130, can be mitigated by the presence of the additional dielectric material140(shown as a composite dielectric stack that includes the dielectric materials140,142) in at least two ways. First, the distance between the interconnect160and the gate electrode130may be increased by the additional thickness added by the dielectric material144disposed over the dielectric layer142. Second, the dielectric material144may be chosen to have a lower dielectric constant than the dielectric material142, further reducing unwanted additional CGS.

It will be understood that features of the transistor100above (and features of other example transistors herein) may be compatible with various transistor technologies. For instance, the transistor100and/or any other example transistor according to embodiments herein may be a metal-MOSFET or MISFET fabricated on a silicon substrate or any other suitable semiconductor substrate. For instance, In some embodiments, the transistor100is a III-V compound semiconductor-based high-electron-mobility transistor (“HEMT”), otherwise known as a heterostructure field effect transistor (“HFET”). In such embodiments the effective semiconductor channel may be a 2D electron gas (“2DEG”) formed at a semiconductor heterojunction disposed with the channel region110according to known techniques. In some embodiments, the transistor100may be a gallium-nitride (GaN) based HEMT. In some such embodiments, a 2DEG is formed at an interface between a GaN layer and an aluminum doped layer with a stochiometric composition described by the chemical formula AlxGa1−xN. In such embodiments it will be understood that the effective channel may be buried within the channel region110and may not extend to the top surface112of the substrate above the channel region110. In some embodiments, the first dielectric material115may be a material that provides surface passivation for the channel region110. For instance, the first dielectric material115may be a silicon nitride passivation layer over a GaN-based heterostructure. It will be further understood that, in embodiments where a channel region such as the channel region110is formed by a semiconductor heterostructure, that the top surface of a semiconductor substrate (e.g., the substrate102) will be defined herein for the purposes of discussion as a top surface of this heterostructure.

FIG.2is a cross-sectional schematic view of example transistor200according to embodiments herein that is a variation of the example transistor100. Similarly, to the transistor100, the transistor200is formed on a semiconductor substrate202(e.g., the substrate). The transistor200has a channel region210(e.g., the channel region110) coupled to a first current terminal220and a second current terminal225(e.g., the current terminals120,125) with a first electrode (a gate electrode230such as the electrode130) disposed between the two current terminals. The gate electrode230(e.g., the gate electrode130) has a first portion232and a second potion234. The first portion232contacts the channel region210within an aperture in the dielectric material215(e.g., the dielectric material115). The transistor200also includes a second electrode which is suitable for use a source-coupled field plate (a field plate250, such as the field plate150) and is electrically coupled to the first current terminal220via an electrically conductive interconnect260(e.g., the interconnect160).

Notably, the transistor200differs from the transistor100in that the field plate250is in direct contact with the first dielectric material215(e.g., the dielectric material115) and without an interposing portion of the dielectric245(e.g., the dielectric145). Thus, if all other dimensions and material choices are the same between the transistor100and the transistor200, then the transistor200will tend to exhibit lower CGDthan the transistor100at the cost of a relatively small increase in CGSresulting from increased overlap of the second field plate250(the source-connected field plate) with the gate electrode230.

FIGS.3-4illustrate example process flows for fabricating transistors with second electrodes operable as source-coupled field plates according to embodiments herein.FIG.3illustrates steps in an example process flow300suitable for fabricating the example transistor100. MeanwhileFIG.4illustrates steps in an example process flow400suitable for fabricating the example transistor200. As will be understood fromFIG.3andFIG.4and the descriptions below that the process flow400is substantially similar to the process flow300. Specifically, the two processes differ Thus, transistors with different trade-offs between CGDand CGSmay be fabricated from identical starting structures based on whether the process300or the process400is performed.

As shown inFIG.3, the example process300includes the steps310,320,330, and350. These steps will be described with reference to the transistor100being fabricated during each step. At the outset of the process300, the substrate102, is already provided with the channel region110, the first dielectric material115, the first and second current terminals120,125, and the gate electrode130extending within the aperture in the dielectric material115, as described above in connection withFIG.1.

At step310the dielectric materials142,144are patterned above the channel region110and the electrode130, leaving the first current terminal120uncovered. The dielectric layers142.144may be formed and patterned according to any suitable additive or subtractive method. In one example, the dielectric layers are sequentially deposited over the entire portion of the substrate102pictured. The dielectric materials142,144may then be covered by an etch mask material (such as photoresist) that protects the dielectric materials in areas where the dielectric materials are not to be removed. The dielectric material is then removed from the exposed areas using any suitable etch processes (e.g., one or more wet chemical etching and/or dry plasma etching steps). In another example, photoresist or other sacrificial material is patterned such that areas where the dielectric materials142,144are to remain are exposed, and areas where the dielectric materials142,144are not desired are protected. The dielectric materials are then deposited by any suitable process (e.g., RF sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.). The undesired dielectric material is then removed in a lift-off process that dissolves the sacrificial material underneath the dielectric materials in areas where the dielectric materials are not desired.

At step320, conductive material that will form the interconnect160once patterned. An additive lift-off process is pictured in which sacrificial material322(e.g., photoresist) has been patterned on the substrate102. Conductive material is deposited by any suitable process (e.g., sputtering, thermal, electron beam evaporation, thermal evaporation, etc.) over areas covered by the sacrificial material322and exposed areas free of the sacrificial material322. The sacrificial material322is dissolved, removing the conductive material324with it and leaving the interconnect160behind as shown at step330. Although an additive lift-off process is depicted for the formation of the interconnect160, it should be understood that well-known subtractive processes may also be suitable.

At step330, the interconnect160is used as an etch mask to protect the dielectric materials142,144from being removed above the electrode130and the region between the electrode130and the current terminal120. The dielectric material144is selectively removed from the area unprotected by the interconnect160. In some examples, the dielectric materials142,144are chosen such that the dielectric material144is preferential removed by a chosen etching process (e.g., any suitable wet chemical etch, or dry plasma etch symbolized by the arrow332).

In one or more examples the dielectric material142is an oxide material (including silicon oxides and aluminum oxides as non-limiting examples) and the dielectric material144is a nitride material (including silicon nitrides as non-limiting examples). In such examples, a reactive ion etching process using fluorinated compounds may be used to selectively remove only the dielectric material144and/or to remove the dielectric material144at a significantly faster rate than the dielectric material142(note that the area from which the dielectric144has been corresponds to the dashed region334). In some examples the area may be “overetched” to tune the residual thickness of the dielectric material142that remains. That is, the etch process chosen to remove the dielectric material144may be prolonged past the point where all the dielectric material144has been removed and the remaining thickness of the dielectric material142may be controlled by varying how long the etch time is extended beyond the time required to remove the dielectric material144). As explained above in connection withFIG.1and further below, in connection with step340, the thickness of the dielectric material142under the electrode150is one factor that determines the CGDreduction (compared to a device with no source field plate) enabled by the electrode150.

In one or more other examples, the dielectric material142is a nitride material (inducing silicon nitrides as non-limiting examples) and the dielectric material144is an oxide material (including silicon oxides and aluminum oxides as non-limiting examples).

At step340, conductive material that will form the electrode150is patterned. An additive lift-off process is pictured in which sacrificial material342(e.g., photoresist) has been patterned on the substrate102. Conductive material is deposited by any suitable process (e.g., sputtering, thermal, electron beam evaporation, thermal evaporation, etc.) over areas covered by the sacrificial material342and exposed areas free of the sacrificial material342. The sacrificial material322may be dissolved, removing the conductive material344with it and leaving the electrode150behind as shown at step340. Although an additive lift-off process is depicted for the formation of the (field plate) electrode150, it should be understood that well-known subtractive processes may also be suitable.

Finally, at step350, after the sacrificial material342, and with it, the undesired conductive material344is removed, the dielectric material142remaining above the current terminal125(indicated by the dashed area352) is optionally removed to allow for the addition of a conductive via in electrical contact with the current terminal125.

As shown inFIG.4, the example process400includes the steps410,420,430, and450. These steps will be described with reference to the transistor100being fabricated during each step. At the outset of the process400, the substrate202is already provided with the channel region220, the first dielectric material215, the first and second current terminals220,225, and the gate electrode230extending within the aperture in the dielectric material215, as described above in connection withFIG.2.

At step410(e.g., step310of process300) the dielectric layers242,244are patterned above the channel region210and the electrode230, leaving the first current terminal220uncovered. The dielectric layers242,244may be formed and patterned according to any suitable additive or subtractive method, as described above in connection with step310of the process300.

At step420(e.g., step320of process300), conductive material that will form the interconnect260once patterned is deposited, as described above in connection with step320of the process300. An additive lift-off process is pictured in which sacrificial material422(e.g., sacrificial material322) has been patterned on the substrate202as described in connection with step320of the process300. The sacrificial material422is removed, removing the conductive material424(e.g., the conductive material324) with it and leaving the interconnect260behind as shown at step430. Although an additive lift-off process is depicted for the formation of the interconnect260, it should be understood that well-known subtractive processes may also be suitable.

At step430, the interconnect260is used as an etch mask to protect the dielectric materials242,244from being removed above the electrode230and the region between the electrode230and the current terminal220. The dielectric material244is selectively removed from the area unprotected by the interconnect260as described above in connection with step330of the process300. However, in contrast to the corresponding step330of process300, step430includes removing both layers of the dielectric material244,242(e.g., the dielectric materials144,142). The dashed regions438,436indicate the areas from which the dielectric material has been removed, In some examples, the dielectric materials242,244are chosen such that the dielectric material244is preferentially removed by a chosen etching process (e.g., any suitable wet chemical etch, or dry plasma etch) such that etching of the dielectric material242proceeds more slowly than etching of the dielectric material244. In some embodiments two distinctive etch processes are used: a first etch process432(symbolized by a vertical arrow) that removes the dielectric material244and a subsequent optional etch process434removes the dielectric material242. In some such embodiments, the subsequent etch used to remove the dielectric material242is a wet etch process. In embodiments in which the dielectric material215(e.g., the dielectric material115) is a thin material (e.g., silicon nitride having a thickness less than 1000 Ansgtroms) that passivates the top surface212above the channel region210, wet etching may be desirable to avoid etch-induced damage to the dielectric material215which might adversely affect performance of the transistor200(e.g., by introducing charge-trapping states in the semiconductor band structure of the channel region210).

At step440(e.g., step340of process300), conductive material that will form the field plate250is patterned similarly to the description of step340of process300. An additive lift-off process is pictured in which sacrificial material442(e.g., the sacrificial material342) has been patterned on the substrate202. Conductive material is deposited by any suitable process (e.g., sputtering, thermal, electron beam evaporation, thermal evaporation, etc.) over areas covered by the sacrificial material442and exposed areas free of the sacrificial material442. The sacrificial material442may be dissolved, removing the conductive material444with it and leaving the field plate250behind as shown at step450. Although an additive lift-off process is depicted for the formation of the (field plate) electrode250, it should be understood that well-known subtractive processes may also be suitable.

Finally, at step450, after the sacrificial material442, and with it, the undesired conductive material44is removed, the dielectric material244remaining above the current terminal225is optionally removed to allow for the addition of a conductive via in electrical contact with the current terminal225.

In the processes300,400respective interconnects (e.g., interconnects160,260) are used as an etch mask that at least partially defines the location of subsequently formed field plates150,250configured for operation as source-connected field plates that are disposed, in part, above the interconnects160,260. In embodiments described below in connection withFIGS.5-8, electrodes similar to the field plates150,250are disposed (at least partially below) interconnects similar to the interconnects160,260.

FIG.5is a cross-sectional schematic view of example transistor500according to embodiments herein that may be understood as a variation of the example transistor100. Similarly, to the transistor100, the transistor500is formed on a semiconductor substrate502(e.g., the substrate102). The transistor500has a channel region510(e.g., a channel region110,210) coupled to a first current terminal520and a second current terminal525(e.g., current terminals120,125or220,225) with a first electrode530(e.g., an electrode130,220) disposed between the two terminals. The first electrode530has a first portion532and a second potion534(e.g., a first portion132,232and/or a second portion134,234of a respective electrode130,230). The first portion532contacts the channel region510within an aperture in the dielectric material515(e.g., dielectric material115,215). The transistor500also includes a second electrode which is suitable for use a source-coupled field plate (a field plate550; e.g., an electrode150,250) and is electrically coupled to the first current terminal520via an electrically conductive interconnect560(e.g., an interconnect160,260). In one or more embodiments, the field plate550may extend all the way to the current terminal520in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane) and the separate interconnect560may be absent.

As shown inFIG.6, the example process600includes the steps610,620,630,640, and650. These steps will be described with reference to the transistor500being fabricated during each step. At the outset of the process600, the substrate502is already provided with the channel region510, the first dielectric material515, the first and second current terminals520,525, and the first electrode530extending within the aperture in the dielectric material515, as described above in connection withFIG.1.

At step610, etch masking material612is patterned above the dielectric materials544,542and etch process614(signified by vertical arrows) configured to selectively remove the dialectic material544is performed. The etch masking material612may be any suitable material configured to withstand the etch process614configured to selectively remove the dialectic material544. The etch masking material612may be patterned using any suitable additive or subtractive process including examples described herein and/or other well-known techniques. As a result of step610, the dielectric layer544is patterned above the channel region510, the current terminals520,525and the electrode530, thereby exposing the dielectric material542above the current terminals520,525creating an aperture in the dielectric material544for the field plate550, as visible at step620inFIG.6. In one more embodiments, the process600may be altered such that the field plate550extends all the way to the current terminal520in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane) and the separate interconnect560may be absent.

It will be understood that the etch process614is chosen, at least in part, for compatibility with other materials (i.e., the dielectric material542and the masking material612). In one non-limiting example, the dielectric material542is an oxide material such as silicon oxide (SiO2or SiOxwhere x is a fractional value that is less than or greater than two) or aluminum oxide (Al2O3or Al2Oxwhere x is a value other than three), the dielectric material544is a nitride material such as silicon nitride (Si3N4or Si3Nxwhere x is value other than four), and the masking material612is photoresist. In one instance, the etch process614may be a wet chemical etch that preferentially removes the dielectric material544over the dielectric material542and the etch mask material612such as a wet etching process that uses a buffered oxide etchant (BOE) solution. In another instance, a dry plasma etching process such as a fluorine-based reactive ion etching process (using SF4, as one non-limiting example) may be used.

At step620conductive material that will form the electrode550once patterned is deposited An additive lift-off process is pictured in which sacrificial material62(e.g., sacrificial material322or other suitable material has been patterned on the substrate502. The sacrificial material612is removed, removing the conductive material614with it., leaving the field plate550behind as shown at step630. Although an additive lift-off process is depicted for the formation of the electrode550, it should be understood that well-known subtractive processes may also be suitable in which a layer is deposited and patterned by etching material that is not protected by an etch mask is removed by a suitable wet chemical or dry plasma etching process. In one more embodiments, step620is altered the field plate550extends all the way to the current terminal520in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane).

At step630, an etch process634(signified by arrows) is performed. The etch process634is configured to selectively remove the dielectric material542that is not protected by the dielectric material544, as patterned at step610. Any suitable etch process may be used, including wet chemical etches and dry plasma etches. It will be understood that the choice of etching process for the etch process634may depend on choices for various other materials (e.g., the dielectric materials515,544and the conductive material used for the electrode550). In one or more examples, the dielectric material542may be an oxide material (non-limiting examples of which include an aluminum oxide material or a silicon oxide material) and the dielectric material544may be a nitride material (e.g., a silicon nitride material). In these and other examples, a reactive ion etching process using fluorinated gases (including hydrofluorocarbons as non-limiting examples) may be used to preferentially remove the nitride materials while leaving oxide materials intact.

At step640, conductive material that will form the interconnect560once patterned is deposited, as described above in connection with steps320,420of the processes300,400respectively. An additive lift-off process is pictured in which sacrificial material642(e.g., sacrificial material322) has been patterned on the substrate502as described in connection with step320of the process300. The sacrificial material642is removed, removing the conductive material644(e.g., the conductive material324) with it, leaving the interconnect760. Although an additive lift-off process is depicted for the formation of the interconnect560, it should be understood that well-known subtractive processes may also be suitable (e.g., blanket metal deposition, followed by photolithographic patterning of an etch mask such as depicted by the patterned etch mask612in step610). In one more embodiments in which step620is altered such the field plate550extends all the way to the current terminal520in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane), step640may not be required.

FIG.7is a cross-sectional schematic view of example transistor700according to embodiments herein that may be understood as a variation of the example transistor500in which the source-connected field plate (the electrode750) directly contacts the dielectric material715(e.g., dielectric material115,215,515) rather than an intervening dielectric layer (e.g., the dielectric material544) as seen in the transistor500as depicted inFIG.5

Similarly, to the transistor500, the transistor700is formed on a semiconductor substrate702(e.g., a substrate102,202,502). The transistor700has a channel region710(e.g., a channel region110,210,510coupled to a first current terminal720and a second current terminal725(e.g., current terminals120,125,220,225, and/or520,525) with a first electrode730(e.g., an electrode130,230,530) disposed between the two terminals. The first electrode730has a first portion732and a second portion734(e.g., a first portion132,232,532and/or a second portion134,234,534of a respective electrode130,230,530). The first portion732contacts the channel region710within an aperture in the dielectric material715(e.g., dielectric material115,215,515). The transistor700also includes the second electrode which is suitable for use a source-coupled field plate (a field plate750; e.g., a field plate150,250,550) and is electrically coupled to the first current terminal720via an electrically conductive interconnect760(e.g., an interconnect160,260,560). In one or more embodiments, the field plate750may extend all the way to the current terminal720in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane) and the separate interconnect760is absent.

As shown inFIG.8, the example process800includes the steps810,820,830, and840. These steps will be described with reference to the transistor700being fabricated during each step. At the outset of the process800, the substrate702is already provided with the channel region710, the first dielectric material715, the first and second current terminals720,725and the first electrode730extending within the aperture in the dielectric material715, as described above in connection withFIG.7. It will be apparent that the process800has the advantage of requiring few processing steps than the process600as will be explained further below. In one or more embodiments, the process800may be altered such that the field plate750extends all the way to the current terminal720in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane)and the separate interconnect760may be absent.

At step810, etch masking material812is patterned above the dielectric materials744,742and an etch process814(signified by vertical arrows) configured to selectively remove the both the dielectric material744and the dielectric material742is performed. The etch masking material812may be any suitable material configured to withstand the etch process814. The etch masking material812may be patterned using any suitable additive or subtractive process including examples described herein and/or other well-known techniques. It will be understood that the etch process814will be chosen, at least in part, for compatibility with other materials (i.e., the dielectric material715and the masking material812). For instance, the etch process814should not cause excessive damage to the dielectric material715directly overlying the channel region710.

In one non-limiting example, the dielectric material742is an oxide material (including aluminum oxides and silicon oxides as non-limiting examples), the dielectric material744is a nitride material (including silicon nitrides as non-limiting examples), and the masking material812is any suitable photoresist. In one or more examples, the etch process814may be a wet chemical etch that preferentially removes the dielectric material744over the dielectric material742and the etch mask material (including a wet etch using buffered oxide etchant (BOE) solution, as a non-limiting example). In one a more other examples, a dry plasma etching process (including fluorine-based reactive ion etching processes as non-limiting examples) may be used.

Because the first end752of the field plate (the gate electrode750) is disposed directly above the dielectric material715in the transistor700, the process800(particularly the step810) enables the dielectric materials744,742to be removed above both the current terminals720,725at the same time that the opening for the first end752of the electrode750is made. As a result, the process800does not require a step similar to step640of the process600(in which dielectric material742remaining above the current terminal520and/or the current terminal525must be removed).

At step820(e.g., step620of the process600) conductive material that will form the electrode750once patterned is deposited. An additive lift-off process is pictured in which sacrificial material822(e.g., sacrificial material322,622or other suitable material) has been patterned on the substrate702. The sacrificial material822is removed, removing the unwanted conductive material824with and leaving the electrode750behind as shown at step830. Although an additive lift-off process is depicted for the formation of the electrode750, it should be understood that well-known subtractive processes may also be suitable in which a layer is deposited and patterned by etching material that is not protected by an etch mask is removed by a suitable wet chemical or dry plasma etching process. In one or more embodiments, step820is altered such that the field plate750extends all the way to the current terminal720in or more areas (e.g., in the cross-sectional plane depicted or in a different cross-sectional plane). In one or more such embodiments, the sacrificial material824is also absent above the current terminal725step820. In one or more such embodiments, step830may be omitted.

At step830conductive material that will form the interconnect760once patterned is deposited, as described above in connection with steps320,420of the processes300,400respectively. An additive lift-off process is pictured in which sacrificial material832(e.g., sacrificial material322,642) has been patterned on the substrate702as described in connection with step840of the process800. The sacrificial material832is removed, removing the conductive material834(e.g., conductive material324,644) with it, leaving the interconnect760. Although an additive lift-off process is depicted for the formation of the interconnect760, it should be understood that well-known subtractive processes may also be suitable (e.g., blanket metal deposition, followed by photolithographic patterning of an etch mask such as depicted by the patterned etch mask612in step610).

FIG.9Ais a cross-sectional schematic view of example transistor900according to embodiments herein in which the electrode950(e.g., an electrode250,550, or750) configured to be operable as a source-connected field plate) is provided with an extension956in between a first end952and a second end954of the electrode950that is disposed between the current terminal925and the first end952of the electrode950that is disposed above the channel region910and separated from the channel region910by the dielectric material915. It will be appreciated that the extension956of the field plate950will tend to lower electric fields arising in the vicinity of the dashed region957due to the presence of the corner of the field plate950nearest the second current terminal925(operable as the drain of the transistor900).

FIG.9Bshows a portion of the transistor900during a processing step920that is similar to the step820of the process800. The difference in step920is that the sacrificial material922is patterned such that the extension956is disposed above the dielectric materials944,942.

It will be appreciated that the steps of various processes above are non-limiting examples of suitable processes according to embodiments herein and are for the purposes of illustration. Devices according to embodiments herein may be fabricated using any suitable processes including those that omit steps described above, perform those steps and similar steps in different orders, and the like. As one example, the transistor500may be fabricated in a process that exposes the current terminal520and525in different steps (instead of a single step as shown in step630).

It will be appreciated well-known features of transistors may be omitted for clarity. For completeness,FIG.10shows a cross-sectional schematic view of a transistor1000in which additional dielectric material encapsulates the active structures and provides isolation between vias. Specifically, the transistor1000has an isolation dielectric1080in which a source via1021is disposed that electrically contacts the first current terminal1020via the interconnect1060and a drain via1026that electrically contacts the second current terminal1025. A gate via electrically contacting the gate electrode1030may be present but would not be visible in the cross-sectional plane depicted inFIG.10.

EXAMPLES

Features of embodiments may be understood by way of one or more of the following examples:

A method of fabricating a semiconductor device that includes depositing interlayer dielectric material over a first dielectric layer and a first electrode on a semiconductor substrate. The first dielectric layer is disposed above a channel region of the semiconductor substrate suitable for use as a semiconductive transistor channel; the first electrode extends within a first aperture in the first dielectric layer and contacts a top surface of the channel region within the aperture; and the first electrode is disposed between a first current terminal electrically coupled to a first end of the channel region and a second current terminal electrically coupled to a second end the channel region opposite the first end of the channel region.

The method further includes performing a first patterning step that includes selectively removing the interlayer dielectric material in a first region between the first electrode and the second current terminal, thereby leaving remaining dielectric material that includes the first dielectric material above the channel region. The method also includes forming a second electrode in the first region having first and second ends. The first end of the second electrode is adjacent to the first electrode. The first end of the second electrode separated from the top surface of the channel region by at least the first dielectric layer. The second end of the second electrode is disposed above the first electrode and is separated from the first electrode by the remaining interlayer dielectric material.

Finally, the method further includes forming a conductive interconnect that extends between the first current terminal and the second electrode and electrically couples the second electrode to the first current terminal. The interconnect is disposed above the first electrode and the remaining interlayer dielectric material.

A method as in Example 1, in which the interlayer dielectric material includes a first interlayer dielectric material and a second interlayer dielectric material layer disposed above the first interlayer dielectric material. In this Example, selectively removing the interlayer dielectric material in the first region further includes forming a second aperture in the second dielectric layer by removing the second interlayer dielectric from the first region. In this Example, the first end of the second electrode extends within the second aperture; and the first end of the second electrode is separated from the channel region in the second aperture by the first dielectric material and a portion of the first interlayer dielectric material disposed beneath the second aperture.

A method as in Example 2, in which forming the second aperture in the second dielectric layer includes performing an etching procedure that preferentially etches the second interlayer dielectric material over the first interlayer dielectric material for an amount of time chosen to leave a desired thickness of the first interlayer dielectric material intact in the first region.

A method as in either of Examples 2 or 3, in which forming the second electrode in the first region includes depositing conductive material that fills the second aperture and also forms an extension area adjacent to the second aperture wherein the conductive material overlies the interlayer dielectric material.

A method as in any of Examples 1-4, in which wherein the interlayer dielectric material comprises a first interlayer dielectric material and a second interlayer dielectric material layer disposed above the first interlayer dielectric material. In this Example, selectively removing the interlayer dielectric material in the first region further includes forming a second aperture in the second interlayer dielectric material by removing the second interlayer dielectric material from the first region using a first etching procedure followed by removing the first interlayer dielectric material from the first region using a second etching procedure. In this Example, the first end of the second electrode extends within the second aperture.

A method as in any of Examples 2-5 in which forming the second electrode in the first region comprises depositing conductive material that fills the second aperture and also forms an extension area adjacent to the second aperture wherein the conductive material overlies the interlayer dielectric material.

A method as in any of Examples 5-6, in which the first etching procedure is a dry plasma etching procedure and the second etching procedure is a wet chemical etching procedure.

A method as in any of Examples 5-7 that further includes forming a first via opening that exposes the first current terminal by removing the second interlayer dielectric material from a region above the first current terminal using the first etching procedure followed by removing the first interlayer dielectric material from the region above the first current terminal using the second etching procedure. This Example also includes forming a second via opening that exposes the second current terminal by removing the second interlayer dielectric material from a region above the second current terminal using the first etching procedure followed by removing the first interlayer dielectric material from the region above the second current terminal using the second etching procedure.

A method as in Example 7, in which forming the interconnect includes depositing conductive material that fills the first via opening.

A method as in any of Examples 1-9, in which selectively removing the interlayer dielectric material in the first region includes performing an etching procedure that preferentially etches the interlayer dielectric material over the first dielectric material for an amount of time chosen to leave the first dielectric material intact in the first region.

A method as in any of Examples 1-10, in which forming the second electrode in the first region comprises depositing conductive material that fills the second aperture and also forms an extension area adjacent to the second aperture wherein the conductive material overlies the first interlayer dielectric material.

A method as in any of Examples 1-11, in which performing the etching procedure that preferentially etches the interlayer dielectric material over the first dielectric material also includes: forming a first via opening that exposes the first current terminal by removing the interlayer dielectric material from a region above the first current terminal; and forming a second via opening that exposes the second current terminal by removing the interlayer dielectric material from a region above the first current terminal. In this Example, the interconnect is formed before the second electrode is formed; a first end of the interconnect electrically contacts the first terminal within the first via opening; and a second end of the interconnect electrically contacts the second end of the second electrode.

A semiconductor device that includes: a channel region defined in a semiconductor substrate; a first current terminal electrically coupled to a first end of the channel region; and a second current terminal electrically coupled to a second end of the channel region opposite the first end. The device also has a first dielectric material having a first dielectric thickness and overlying the channel region; a first interlayer dielectric material overlying the channel and the first electrode; and second interlayer dielectric material overlying the first interlayer dielectric material.

The device has a first aperture in the first dielectric material that overlies the channel region in between the first current terminal and the second current terminal; and an electrically conductive first electrode that extends within the first aperture that is in direct physical contact with a top surface of the channel region. The device also has an electrically conductive second electrode spaced apart from the first electrode.

The second electrode has a first end that overlies at least the first dielectric material and the channel region at a location between the first electrode and the second current terminal; and a second end that overlies at least a portion of the first electrode that is separated from the first electrode by the first and second interlayer dielectric materials.

The device is configured to provide an electrically conductive path from the first current terminal to the second current terminal via the channel region when a sufficient control voltage is applied to the first electrode.

A device as in Example 13, in which the first end of the second electrode directly contacts the first dielectric layer; and the second electrode further includes an electrode extension that is disposed between the first end of the second and the second current terminal and is disposed above at least the first interlayer dielectric material.

A device as in either of Examples 13 or 14, in which the first end of the second electrode directly contacts the first dielectric material; the first interlayer dielectric material and the second interlayer dielectric material have been removed from an area above the first dielectric material and beneath the first end of the second electrode; the first interlayer dielectric material has been removed by an etching procedure and is characterized by a first etch rate with respect to the etching procedure; and the first dielectric material is characterized by a second etch rate with respect to the etching procedure that is slower than the first etch rate.

A device as in any of Examples 13-15, that further includes an electrically conductive interconnect that electrically couples the second electrode to the first current terminal, the interconnect overlying the first electrode and the first and second interlayer dielectric materials, and separated from the first electrode by the first and second interlayer dielectric materials.

A device as in Example 16 in which wherein the interconnect electrically contacts the second electrode at the second end of the second electrode at a location overlying the first electrode

A device as in any of Examples 13-17, in which the second electrode includes a lateral extension that overlies the second interlayer dielectric material at a location between the first end of the second electrode and the second current terminal.

A device as in any of Examples 13-18, in which the first end of the second electrode directly overlies the first interlayer dielectric material; and the second interlayer dielectric material is absent from an area above the first interlayer dielectric material and beneath the first end of the second electrode. In this Example, the first interlayer dielectric material is characterized by a first etch rate with respect to a dry etching procedure; and the second interlayer dielectric material is characterized by a second etch rate with respect to the dry etching procedure that is faster than the first etch rate.

A device as in any of Examples 13-19, in which the channel region comprises a semiconductor heterostructure with a two-dimensional electron gas (2DEG) region formed at a semiconductor heterojunction beneath a surface of the channel region nearest to the first electrode.

The preceding detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The preceding detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.