Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This U.S. application claims the benefit of priority under 35 USC §119 to Korean Patent Application No. 10-2014-0111225, filed on Aug. 26, 2014, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.

BACKGROUND

1. Technical Field

At least one example embodiment relates to memory devices, and more particularly to semiconductor memory devices, memory systems including the same and/or methods of correcting errors in the same.

2. Discussion of the Related Art

Semiconductor memory devices can be divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of nonvolatile memory devices include phase change random access memory (PRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and ferroelectric random access memory (FRAM).

As fabrication process of the semiconductor memory devices advances and the devices become smaller in size, a bit error rate (BER) of memory cells in the semiconductor memory devices may increase.

SUMMARY

At least one example embodiment may provide a semiconductor memory device capable of enhancing error correction capability.

At least one example embodiment may provide a memory system including a semiconductor memory device capable of enhancing error correction capability.

At least one example embodiment may provide a method of correcting errors in a semiconductor memory device capable of enhancing error correction capability.

According to at least one example embodiment, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

According to at least one example embodiment, the main data includes 2pbits and the parity data includes q bits (where q is greater than p and p and q are natural numbers equal to or greater than two). The ECC circuit may generate q-bit check bits based on a main data in the read codeword and may generate the syndromes with q-bit based on the q-bit check bits and q-bit parity data in the read codeword.

According to at least one example embodiment, the ECC circuit may correct the errors when the one symbol includes errors equal to or smaller than two.

According to at least one example embodiment, values of the q-bit syndromes may be linearly independent in first through third cases. The first case may correspond to a case when the first data has an error and the second data has no error, the second case mat correspond to a case when the first data has no error and the second data has an error and the third case may correspond to a case when the first data has an error and the second data has an error respectively.

According to at least one example embodiment, the ECC circuit may include an encoder to generate the parity data based on the main data and a decoder to generate the syndromes based on the read codeword to correct the errors by unit of the symbol.

According to at least one example embodiment, the encoder may include a plurality of parity generators, and each of the parity generators may generate corresponding parity bit of the q-bit parity data based on the 2p-bit main data.

According to at least one example embodiment, the decoder may include a check bit generator to generate the q-bit check bits based on the main data of the read codeword, a syndrome generator to generate the q-bit syndromes based on the q-bit check bits and the parity data of the read codeword and a corrector to correct the errors in the read codeword by unit of the symbol based on the q-bit syndromes.

According to at least one example embodiment, the syndrome generator may generate the syndromes, each having a logic level according to whether each corresponding bit of the q-bit check bits and the q-bit parity data is equal to each other.

According to at least one example embodiment, the syndrome generator may include a plurality of logic elements, each performing an XOR operation on corresponding bits of the q-bit check bits and the q-bit parity data to generate corresponding syndrome.

According to at least one example embodiment, the corrector may include a plurality of unit correctors and each of the unit correctors corrects errors in each symbol, which is equal to or smaller than two, by unit of the symbol, based on the syndromes.

According to at least one example embodiment, each of the unit corrector may include a symbol decoder to determine whether at least one of the first data and the second data has an error based on the syndromes and a data corrector to correct errors in one symbol, which is equal to or smaller than two, based on first through third outputs of the symbol decoder.

According to at least one example embodiment, the symbol decoder may include a first sub decoder to provide the first output signal indicating whether the first data has an error based on the syndromes, a second sub decoder to provide the second output signal indicating whether the second data has an error based on the syndromes and a third sub decoder to provide the third output signal indicating whether each of the first data and second data has an error based on the syndromes.

According to at least one example embodiment, the data corrector may include a first logic element to perform an OR operation on the first output signal and the second output signal, a second logic element to perform an OR operation on the second output signal and the third output signal, a third logic element to perform an XOR operation on the first data and an output of the first logic element to output a first corrected data and a fourth logic element to perform an XOR operation on the second data and an output of the second logic element to output a second corrected data.

According to at least one example embodiment, the data corrector may invert the first when the first data has an error, may invert the second data when the second data has an error and may invert the first data and the second data when each of the first data and the second data has an error.

According to at least one example embodiment, each of the plurality of memory cells may be a dynamic memory cell. The memory cell array may include a three-dimensional memory array in which word-lines and/or bit-lines are shared between levels.

According to at least one example embodiment, each of the plurality of memory cells may be a resistive type memory cell. The memory cell array may include a three-dimensional memory array in which word-lines and/or bit-lines are shared between levels.

According to at least one example embodiment, the resistive type memory cell may be spin transfer torque magneto-resistive random access memory (STT-MRAM) cell that includes a magnetic tunnel junction (MTJ) element and a cell transistor.

According to at least one example embodiment, the semiconductor memory device may further include a matching memory to store a row address designating the selected memory cell row and to provide a selection signal to the ECC circuit. A configuration of the symbol may be changed based on the selection signal.

According to at least one example embodiment, the ECC circuit may further include a selection circuit to change the first data and the second data in the symbol to be provided to the check bit generator in response to the selection signal.

According to at least one example embodiment, a memory system includes at least one semiconductor memory device and a memory controller. The memory controller controls the at least one semiconductor memory device and exchanges main data with the at least one semiconductor memory device. The at least one semiconductor memory device includes a memory cell array and an error correcting code (ECC) circuit. A plurality of memory cells are arranged in the memory cell array. The ECC circuit generates parity data based on the main data, writes a codeword including the main data and the parity data in the memory cell array, reads the codeword from a selected memory cell row to generate syndromes and corrects errors in the read codeword on a per symbol basis, based on the syndromes, where a first data of a first memory cell of the selected memory cell row and a second data of a second memory cell of the selected memory cell row are assigned to one symbol. The first memory cell and the second memory cell are adjacent to each other.

According to at least one example embodiment, the main data may include 2pbits and the parity data may include q bits (where, q is greater than p and p and q are natural numbers equal to or greater than two). The at least one semiconductor memory device may be one of a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a phase change random access memory (PRAM) and a ferroelectric random access memory (FRAM).

According to at least one example embodiment, the main data may include 2pbits and the parity data may include q bits (where, q is greater than p and p and q are natural numbers equal to or greater than two). The at least one semiconductor memory device may be a dynamic random access memory (DRAM).

According to at least one example embodiment, a method of correcting errors in a semiconductor memory device includes reading a codeword including main data and parity data from a selected memory cell row of a memory cell array, generating syndromes based on the read codeword, and correcting errors in the read codeword on a per symbol basis, based on the syndromes, where a first data of a first memory cell of the selected memory cell row and a second data of a second memory cell of the selected memory cell row are assigned to one symbol. The first memory cell and the second memory cell are adjacent to each other.

According to at least one example embodiment, the main data may include 2pbits, the parity data may include q bits (where, q is greater than p and p and q are natural numbers equal to or greater than two) and the syndromes may include q bits.

According to at least one example embodiment, the q-bit syndromes may be generated based on q-bit check bits and the q-bit parity data and the q-bit check bits may be generated based on the 2p-bits main data. Values of the q-bit syndromes may be linearly independent in first through third cases. The first case may correspond to a case when the first data has an error and the second data has no error, the second case mat correspond to a case when the first data has no error and the second data has an error and the third case may correspond to a case when the first data has an error and the second data has an error respectively.

According to at least one example embodiment, a device comprises a decoder configured to receive a codeword from a selected memory cell row of a memory cell array, the received codeword including main data and parity data. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first memory cell and the second memory cell are adjacent to each other in the memory cell array, and the first data and the second data are assigned to a first symbol of a plurality of symbols. The decoder is configured to generate an error indicator for the first symbol based on the received codeword. The decoder is configured to detect errors in the received codeword based on the error indicator.

According to at least one example embodiment, the decoder is configured to generate the error indicator based on the parity data and check bit data derived from the main data.

According to at least one example embodiment, the decoder is configured to generate the error indicator for the first symbol by generating a first sub-error indicator for the first data, generating a second sub-error indicator for the second data, and combining the first sub-error indicator and the second error indicator.

According to at least one example embodiment, the decoder is configured to detect errors in the first and second data based on the first error indicator, the second error indicator, and the third error indicator.

According to at least one example embodiment, the combining includes performing an XOR operation on bits of the first error indicator and bits of the second error indicator.

Accordingly, errors in a codeword read from the selected memory cell row may be corrected on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments of are shown. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey inventive concepts of to those skilled in the art. Inventive concepts may be embodied in many different forms with a variety of modifications, and a few embodiments will be illustrated in drawings and explained in detail. However, this should not be construed as being limited to example embodiments set forth herein, and rather, it should be understood that changes may be made in these example embodiments without departing from the principles and spirit of inventive concepts, the scope of which are defined in the claims and their equivalents. Like numbers refer to like elements throughout. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

Specific details are provided in the following description to provide a thorough understanding of example embodiments. However, it will be understood by one of ordinary skill in the art that example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams so as not to obscure example embodiments in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.

In the following description, illustrative embodiments will be described with reference to acts and symbolic representations of operations (e.g., in the form of flow charts, flow diagrams, data flow diagrams, structure diagrams, block diagrams, etc.) that may be implemented as program modules or functional processes include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and may be implemented using existing hardware in existing electronic systems (e.g., electronic imaging systems, image processing systems, digital point-and-shoot cameras, personal digital assistants (PDAs), smartphones, tablet personal computers (PCs), laptop computers, etc.). Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits (ASICs), field programmable gate arrays (FPGAs) computers or the like.

As disclosed herein, the term “storage medium”, “computer readable storage medium” or “non-transitory computer readable storage medium” may represent one or more devices for storing data, including read only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other tangible or non-transitory machine readable mediums for storing information. The term “computer-readable medium” may include, but is not limited to, portable or fixed storage devices, optical storage devices, and various other tangible or non-transitory mediums capable of storing, containing or carrying instruction(s) and/or data.

FIG. 1is a block diagram illustrating an electronic system according to at least one example embodiment.

Referring toFIG. 1, an electronic system10may include a host15and a memory system20. The memory system20may include a memory controller100and a plurality of semiconductor memory devices200a˜200g.

The host15may communicate with the memory system20through various interface protocols such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or serial attached SCSI (SAS). In addition, the host15may also communicate with the memory system20through interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

The memory controller100may control an overall operation of the memory system30. The memory controller100may control an overall data exchange between the host20and the plurality of semiconductor memory devices200a˜200g. For example, the memory controller100may write data in the plurality of semiconductor memory devices200a˜200gor read data from the plurality of semiconductor memory devices200a˜200gin response to request from the host15.

In addition, the memory controller100may issue operation commands to the plurality of semiconductor memory devices200a˜200gfor controlling the plurality of semiconductor memory devices200a˜200g.

In at least one example embodiment, each of the plurality of semiconductor memory devices200a˜200gmay be a memory device including resistive type memory cells such as a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), a phase change random access memory (PRAM) and a ferroelectric random access memory (FRAM), etc. In other example embodiments, each of the plurality of semiconductor memory devices200a˜200gmay be a memory device including dynamic memory cells such as a dynamic random access memory (DRAM).

An MRAM is a nonvolatile computer memory based on magnetoresistance. An MRAM is different from a volatile RAM in many aspects. For example, since an MRAM is nonvolatile, the MRAM may retain all stored data even when power is turned off.

Although a nonvolatile RAM is generally slower than a volatile RAM, an MRAM has read and write response times comparable with read and write response times of a volatile RAM. Unlike a conventional RAM that stores data as electric charge, an MRAM stores data by using magnetoresistance (or magnetoresistive) elements. In general, a magnetoresistance element is made of two magnetic layers, each having a magnetization.

An MRAM is a nonvolatile memory device that reads and writes data by using a magnetic tunnel junction pattern including two magnetic layers and an insulating film disposed between the two magnetic layers. A resistance value of the magnetic tunnel junction pattern may vary according to a magnetization direction of each of the magnetic layers. The MRAM may program or remove data by using the variation of the resistance value.

An MRAM using a spin transfer torque (STT) phenomenon uses a method in which when a spin-polarized current flows in one direction, a magnetization direction of the magnetic layer is changed due to the spin transfer of electrons. A magnetization direction of one magnetic layer (e.g., a pinned layer) may be fixed and a magnetization direction of the other magnetic layer (e.g., a free layer) may vary according to a magnetic field generated by a program current.

The magnetic field of the program current may arrange the magnetization directions of the two magnetic layers in parallel or in anti-parallel. In at least one example embodiment, if the magnetization directions of the two magnetic layers are parallel, a resistance between the two magnetic layers is in a low (“0”) state. If the magnetization directions of the two magnetic layers are anti-parallel, a resistance between the two magnetic layers is in a high (“1”) state. Switching of the magnetization direction of the free layer and the high or low state of the resistance between the two magnetic layers result in write and read operations of the MRAM.

Although the MRAM is nonvolatile and provides a quick response time, an MRAM cell has a limited scale and is sensitive to write disturbance because the program current applied to switch the high and low states of the resistance between the magnetic layers of the MRAM is typically high. Accordingly, when a plurality of cells are arranged in an MRAM array, a program current applied to one memory cell changes a magnetic field of a free layer of an adjacent cell. Such a write disturbance may be mitigated (or alternatively, prevented) by using an STT phenomenon. A typical STT-MRAM may include a magnetic tunnel junction (MTJ), which is a magnetoresistive data storage device including two magnetic layers (e.g., a pinned layer and a free layer) and an insulating layer disposed between the two magnetic layers.

A program current typically flows through the MTJ. The pinned layer spin-polarizes electrons of the program current, and a torque is generated as the spin-polarized electron current passes through the MTJ. The spin-polarized electron current applies the torque to the free layer while interacting with the free layer. When the torque of the spin-polarized electron current passing through the MTJ is greater than a threshold switching current density, the torque applied by the spin-polarized electron current is sufficient to switch a magnetization direction of the free layer. Accordingly, the magnetization direction of the free layer may be parallel or anti-parallel to the pinned layer and a resistance state in the MTJ is changed.

The STT-MRAM removes a requirement of an external magnetic field for the spin-polarized electron current to switch the free layer in the magnetoresistive device. In addition, the STT-MRAM improves scaling as a cell size is reduced and the program current is reduced to mitigate (or alternatively, prevent) the write disturbance. In addition, the STT-MRAM may have a high tunnel magnetoresistance ratio, which improves a read operation in a magnetic domain by allowing a high ratio between the high and low states.

An MRAM is an all-round memory device that is low cost and has high capacity (like a dynamic random access memory (DRAM), operates at high speed (like a static random access memory (SRAM), and is nonvolatile (like a flash memory).

FIG. 2is a block diagram illustrating an example of the memory system inFIG. 1according to at least one example embodiment.

InFIG. 2, only one semiconductor memory device200ain communication with the memory controller100is illustrated for convenience. However, the details discussed herein related to semiconductor memory device200amay equally apply to the other semiconductor memory devices200b˜200g.

Referring toFIG. 2, the memory system30may include the memory controller100and the semiconductor memory device200a. The memory controller100may transmit command CMD and address ADDR to the semiconductor memory device200a. The memory controller100may exchange main data MD with the semiconductor memory device200a.

Referring toFIGS. 1 and 2, the memory controller100may input data to the semiconductor memory device200aor may output data from the semiconductor memory device200abased on the request from the host15.

FIG. 3is a block diagram illustrating an example of the semiconductor memory device inFIG. 2according to at least one example embodiment.

Referring toFIG. 3, the semiconductor memory device200amay include a control logic210, an address register220, a bank control logic230, a row address multiplexer240, a column address latch250, a row decoder260, a column decoder270, a memory cell array300, a sense amplifier unit285, an input/output (I/O) gating circuit290, an error correcting code (ECC) circuit350, a data input/output (I/O) buffer295, a refresh counter245and a matching memory255.

The memory cell array300may include first through fourth bank arrays310˜340. Each of the first through fourth bank arrays310˜340may include a plurality of memory cells MC coupled to a corresponding word-line WL and a corresponding bit-line BL. The row decoder260may include first through fourth bank row decoders260a˜260drespectively coupled to the first through fourth bank arrays310˜340, the column decoder270may include first through fourth bank column decoders270a˜270drespectively coupled to the first through fourth bank arrays310˜340, and the sense amplifier unit285may include first through fourth bank sense amplifiers285a˜285drespectively coupled to the first through fourth bank arrays310˜340. The first through fourth bank arrays310˜340, the first through fourth bank row decoders260a˜260d, the first through fourth bank column decoders270a˜270dand first through fourth bank sense amplifiers285a˜285dmay form first through fourth banks. Each of the first through fourth bank arrays310˜340may include a plurality of semiconductor memory cells RMC, and each of semiconductor memory cells RMC is coupled to a corresponding word-line and a corresponding bit-line. Although the semiconductor memory device200ais illustrated inFIG. 3as including four banks, the semiconductor memory device200amay include any number of banks.

The address register220may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from the memory controller100. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, may provide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to the bank address BANK_ADDR. One of the first through fourth bank row decoders260a˜260dcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the first through fourth bank column decoders270a˜270dcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive a refresh row address REF_ADDR from the refresh counter245. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer240may be applied to the first through fourth bank row decoders260a˜260d.

The activated one of the first through fourth bank row decoders260a˜260dmay decode the row address RA that is output from the row address multiplexer240, and may activate a word-line corresponding to the row address RA. For example, the activated bank row decoder may apply a word-line driving voltage to the word-line corresponding to the row address RA.

The column address latch250may receive the column address COL_ADDR from the address register220, and may temporarily store the received column address COL_ADDR. In at least one example embodiment, in a burst mode, the column address latch250may generate column addresses that increment from the received column address COL_ADDR. The column address latch250may apply the temporarily stored or generated column address to the first through fourth bank column decoders270a˜270d.

The activated one of the first through fourth bank column decoders270a˜270dmay decode the column address COL_ADDR that is output from the column address latch250, and may control the input/output gating circuit290in order to output data corresponding to the column address COL_ADDR.

The I/O gating circuit290may include a circuitry for gating input/output data. The I/O gating circuit290may further include read data latches for storing data that is output from the first through fourth bank arrays310˜340, and write drivers for writing data to the first through fourth bank arrays310˜340.

Codeword CW to be read from one bank array of the first through fourth bank arrays310˜340may be sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and may be stored in the read data latches. The codeword CW stored in the read data latches may be provided to the ECC circuit350for correcting errors and may be provided to the memory controller100via the data I/O buffer299. Main data MD to be written in one bank array of the first through fourth bank arrays310˜340may be provided to the data I/O buffer295from the memory controller100. The main data MD may be encoded to a codeword CW in the ECC circuit350, and the write driver may write the codeword CW in one bank array of the first through fourth bank arrays310˜340.

The ECC circuit350may generate q-bit parity data based on 2p-bit main data MD, may write a codeword CW including the main data MD and the parity data in the memory cell array300, may read the codeword CW from a selected memory cell row to generate syndromes (or error indicators) and may correct errors in the read codeword CW on a per symbol basis, based on the syndromes, where a first data of a first memory cell of the selected memory cell row and a second data of a second memory cell of the selected memory cell row are assigned to one symbol (a same symbol). The first memory cell and the second memory cell may be adjacent to each other.

The matching memory255may store a row address ROW_ADDR designating the selected memory cell row and may provide the ECC circuit350with a selection signal SS based on the row address ROW_ADDR. The ECC circuit350may change a configuration of the first data and the second data in one symbol in response to the selection signal SS. For example, a configuration of the first data and the second data constituting one symbol may be changed according to arrangement of the memory cells MC in the memory cell array300. In a first example, the selected memory cell row may be coupled to an even word-line. In a second example, the selected memory cell row may be coupled to an odd word-line.

The control logic210may control operations of the semiconductor memory device200a. For example, the control logic210may generate control signals for the semiconductor memory device200ain order to perform a write operation or a read operation. The control logic210may include a command decoder211that decodes a command CMD received from the memory controller100and a mode register212that sets an operation mode of the semiconductor memory device200a. The mode resistor212may be programmed by mode resistor set (MRS) commands. The mode resistor212may generate mode signal according to programmed operation mode.

For example, the command decoder211may generate the control signals corresponding to the command CMD by decoding a write enable signal (/WE), a row address strobe signal (/RAS), a column address strobe signal (/CAS), a chip select signal (/CS), etc.

FIGS. 4A to 4Eare circuit diagrams of examples of the memory cell inFIG. 3according to at least one example embodiment.

FIGS. 4A to 4Dillustrate memory cells which are implemented with resistive type memory cells andFIG. 4Eillustrates a memory cell which is implemented with a dynamic memory cell.

FIG. 4Aillustrates a resistive type memory cell without a selection element, whileFIGS. 4B to 4Dshow resistive type memory cells each comprising a selection element.

Referring toFIG. 4A, a memory cell MC may include a resistive element R connected to a bit-line BL and a word-line WL. Such a semiconductor memory cell having a structure without a selection element may store data by a voltage applied between bit-line BL and word-line WL.

Referring toFIG. 4B, a memory cell MC may include a resistive element R and a diode D. Resistive element R may include a resistive material for data storage. Diode D may be a selection element (or switching element) that supplies current to resistive element R or cuts off the current supply to resistive element R according to a bias of word-line WL and bit-line BL. Diode D may be coupled between resistive element R and word-line WL, and resistive element R may be coupled between bit-line BL and diode D. Positions of diode D and resistive element R may be interchangeable. Diode D may be turned on or turned off by a word-line voltage. Thus, a resistive memory cell may be not driven where a voltage of a constant level or higher is supplied to an unselected word-line WL.

Referring toFIG. 4C, a memory cell MC may include a resistive element R and a bidirectional diode BD. Resistive element R may include a resistive material for data storage. Bidirectional diode BD may be coupled between resistive element R and a word-line WL, and resistive element R may be coupled between a bit-line BL and bidirectional diode BD. Positions of bidirectional diode BD and resistive element R may be interchangeable. Bidirectional diode BD may block leakage current flowing to an unselected semiconductor memory cell.

Referring toFIG. 4D, a memory cell MC may include a resistive element R and a transistor T. Transistor T may be a selection element (or switching element) that supplies current to resistive element R or cuts off the current supply to resistive element R according to a voltage of a word-line WL. Transistor T may be coupled between resistive element R and a word-line, and resistive element R may be coupled between a bit-line BL and transistor T. Positions of transistor T and resistive element R may be interchangeable. The semiconductor memory cell may be selected or unselected depending on whether transistor T drive by word-line WL is turned on or turned off.

Referring toFIG. 4E, a memory cell MC may include a cell capacitor CC and a cell transistor CT. Cell Transistor CT may be a selection element (or switching element) that connects/disconnects cell capacitor CC to/from bit-line BL according to a voltage of a word-line WL. Cell transistor CT may be coupled between cell capacitor CC, a word-line WL and a bit-line BL, and a cell capacitor CC may be coupled between a cell transistor CT and a plate voltage (not illustrated).

FIG. 5illustrates an example of the first bank array in the semiconductor memory device ofFIG. 3according to at least one example embodiment.

Referring toFIG. 5, the first bank array310may include a plurality of word-lines WL0through WLn (where n is a natural number equal to or greater than 2), a plurality of bit-lines BL0through BLm (where M is a natural number equal to or greater than 2), and a plurality of memory cells30disposed at intersections between the word-lines WL0through WLn and the bit-lines BL0through BLm. Each of the memory cells30may be a resistive type memory cell or a dynamic memory cell.

Configuration of the first data and the second data constituting one symbol may be changed according to which word-line is selected of the plurality of word-lines WL0through WLn. For example, when a word-line WL1is selected, one symbol SB1may include a first data of a memory cell MC11coupled to a bit-line BL0and a second data of a memory cell MC12coupled to a bit-line BL1. For example, when a word-line WL0is selected, one symbol SB2may include a first data of a memory cell MC21coupled to a bit-line BL1and a second data of a memory cell MC22coupled to a bit-line BL2.

FIG. 6illustrates an example of the first bank array in the semiconductor memory device ofFIG. 3according to at least one example embodiment.

Referring toFIG. 6, the first bank array310may include a plurality of word-lines WL0through WLn (where n is a natural number equal to or greater than 2), a plurality of bit-lines BL0through BLm (where M is a natural number equal to or greater than 1), a plurality of source lines SL0through SLn, and a plurality of resistive type memory cells30disposed at intersections between the word-lines WL0through WLn and the bit-lines BL0through BLm. Each of the resistive type memory cells30may be an STT-MRAM cell. The resistive type memory cell30may include an MTJ element40having a magnetic material.

Each of the resistive type memory cells30may include a cell transistor CT and the MTJ element40. In one resistive type memory cell30, a drain (a first electrode) of the cell transistor CT may be connected to a pinned layer43of the MTJ element40. A free layer41of the MTJ40may be connected to the bit-line BL0, and a source (a second electrode) of the cell transistor CT may be connected to the source line SL0. A gate of the cell transistor CT may be connected to the word-line WL0.

The MTJ element40may be replaced by a resistive device such as a phase change random access memory (PRAM) using a phase change material, a resistive random access memory (RRAM) using a variable resistive material such as a complex metal oxide, or a magnetoresistive random access memory (MRAM) using a ferromagnetic material. Materials forming the resistive devices have resistance values that vary according to a size and/or a direction of a current or a voltage, and are nonvolatile and thus may maintain the resistance values even when the current or the voltage is cut off.

The word-line WL0may be enabled by a row decoder260a, and may be connected to a word-line driver311that drives a word-line selection voltage. The word-line selection voltage activates the word-line WL0in order to read or write a logic state of the MTJ element40.

The source line SL0is connected to a source line voltage generator294. The source line voltage generator294may receive and decode an address signal and a read/write signal, and may generate a source line selection signal in the selected source line SL0. A ground reference voltage may be supplied to the unselected source lines SL1through SLn.

The bit-line BL0is connected to a column select circuit292that is driven by column selection signals CSL0through CSLm. The column selection signals CSL0through CSLm are selected by a column decoder270a. For example, the selected column selection signal CSL0turns on a column select transistor in the column selection circuit292, and selects the bit-line BL0. A logic state of the MTJ element40is read from the bit-line BL0through a sense amplifier285a. Alternatively, a write current applied through the write driver291is transmitted to the selected bit-line BL0and is written to the MTJ element40.

FIG. 7is a perspective view illustrating the resistive type memory cell (referred to as STT-MRAM cell) inFIG. 6according to at least one example embodiment.

Referring toFIG. 7, the STT-MRAM cell30may include the MTJ element40and the cell transistor CT. A gate of the cell transistor CT is connected to a word-line (for example, the word-line WL0), and one electrode of the cell transistor CT is connected through the MTJ40to a bit-line (for example, the bit-line BL0). Also, the other electrode of the cell transistor CT is connected to a source line (for example, the source line SL0).

The MTJ element40may include the free layer41, the pinned layer43, and a tunnel layer42disposed between the free layer41and the pinned layer43. A magnetization direction of the pinned layer43may be fixed, and a magnetization direction of the free layer41may be parallel to or anti-parallel to the magnetization direction of the pinned layer43according to written data. In order to fix the magnetization direction of the pinned layer43, for example, an anti-ferromagnetic layer (not shown) may be further provided.

In order to perform a write operation of the STT-MRAM cell30, a logic high voltage is applied to the word-line WL0to turn on the cell transistor CT. A program current, that is, a write current is applied to the bit-line BL0and the source line SL0. A direction of the write current is determined by a logic state of the MTJ element40.

In order to perform a read operation of the STT-MRAM cell30, a logic high voltage is applied to the word-line WL0to turn on the cell transistor CT, and a read current is supplied to the bit-line BL0and the source line SL0. Accordingly, a voltage is developed at both ends of the MTJ element40, is detected by the sense amplifier285a, and is compared with a reference voltage from a reference voltage to determine a logic state of the MTJ element40. Accordingly, data stored in the MTJ element40may be detected.

FIGS. 8A and 8Bare block diagrams for explaining a magnetization direction according to data written to the MTJ element ofFIG. 7.

A resistance value of the MTJ element40may vary according to a magnetization direction of the free layer41. When a read current IR flows through the MTJ40, a data voltage is output according to the resistance value of the MTJ element40. Since the read current IR is much smaller than a write current, a magnetization direction of the free layer41is not changed by the read current IR.

Referring toFIG. 8A, a magnetization direction of the free layer41and a magnetization direction of the pinned layer43of the MTJ element40are parallel. Accordingly, the MTJ element40may have a high resistance value. In this case, the MTJ element40may read data ‘0’.

Referring toFIG. 8B, a magnetization direction of the free layer41and a magnetization direction of the pinned layer43of the MTJ element40are anti-parallel. Accordingly, the MTJ element40may have a high resistance value. In this case, the MTJ element40may read data ‘1’.

Although the free layer41and the pinned layer43of the MTJ40are horizontal magnetic layers, example embodiments are not limited thereto and the free layer41and the pinned layer43may be, for example, vertical magnetic layers.

FIG. 9is a block diagram for explaining a write operation of the STT-MRAM cell ofFIG. 7according to at least one example embodiment.

Referring toFIG. 9, a magnetization direction of the free layer41may be determined based on a direction of a write current IW flowing through the MTJ40. For example, when a first write current IWC1is supplied from the free layer41to the pinned layer43, free electrons having the same spin direction as that of the pinned layer43apply a torque to the free layer41. Accordingly, the free layer41may be magnetized parallel to the pinned layer43.

When a second write current IWC2is applied from the pinned layer43to the free layer41, electrons having a spin direction opposite to that of the pinned layer41return to the free layer43and apply a torque. Accordingly, the free layer41may be magnetized anti-parallel to the pinned layer43. That is, a magnetization direction of the free layer41of the MTJ40may be changed by an STT.

FIG. 10illustrates the ECC circuit and the I/O gating circuit in the semiconductor memory device ofFIG. 3according to at least one example embodiment.

Referring toFIG. 10, the ECC circuit350includes an encoder360and a decoder370. The I/O gating circuit290includes a gating unit291, a write driver293and a latch unit295.

The encoder360may receive the 2p-bit main data MD from the memory controller100, may encode the main data MD to generate q-bit parity data and may provide the I/O gating circuit290with a write codeword WCW including the main data MD and the parity data in a write operation, where q is greater than p and p and q are natural numbers equal to or greater than two). The decoder370may receive the codeword (or a read codeword) RCW from the I/O gating circuit290, may generate the check bits using the main data MD in the codeword RCW, may generate the syndromes (or error indicators) based on the check bits and the parity data in the codeword RCW and may correct errors in the codeword RCW, where a first data of a first memory cell of the selected memory cell row and a second data of a second memory cell of the selected memory cell row are assigned to one symbol (a same symbol). The first memory cell and the second memory cell may be adjacent to each other. The decoder370may correct the errors when the one symbol includes errors equal to or smaller than two.

The gating unit291gates the write codeword WCW from the write driver293to the memory cell array300in response to a decoded column address DCADDR and gates the read codeword RCW from the memory cell array300to the latch unit295. The latch unit295provides the decoder370with the read codeword RCW from the memory cell array300.

FIG. 11illustrates an example of the ECC circuit inFIG. 10according to at least one example embodiment.

Referring toFIG. 11, the encoder360may encode the 2p-bit main data MD to generate the q-bit parity data PRT and provide the write driver293with the write codeword WCW including the 2p-bit main data MD and the q-bit parity data PRT. The decoder370may receive the (2p+q)-bit read codeword RCW from the latch unit295, may correct errors in the read codeword RCW on a per symbol basis and may provide the memory controller100with the 2p-bit main data MD or 2p-bit corrected main data C_MD via the data I/O buffer299.

FIG. 12is a circuit diagram illustrating an example of the encoder inFIG. 11according to at least one example embodiment.

InFIG. 12, it is assumed that the main data MD includes 27bits, or 128 bits and the parity data PRT includes 8 bits PB0˜PB7.

Referring toFIG. 12, the encoder360amay include a plurality of parity generators361˜368.

The plurality of parity generators361˜368may generate the parity bits PB0˜PB7of the q-bit parity data PRT based on the 2p-bit main data MD, respectively.

The parity generator361may generate a first parity bit PB0based on data bits D0, D2, . . . , D127of the main data MD, and the parity generator361may include a plurality of XOR gates G11˜G15. The parity generator362may generate a second parity bit PB1based on data bits D14, D16, . . . , D127of the main data MD, and the parity generator362may include a plurality of XOR gates G21˜G25. The parity generator368may generate an eighth parity bit PB7based on data bits D0, D1, . . . , D127of the main data MD, and the parity generator368may include a plurality of XOR gates G81˜G85.

Each of the parity generators361˜368may include other logic gates performing same operation as XOR gates. The parity bits PB0˜PB7are stored in the selected memory cell row along with the main data MD.

FIG. 13is a block diagram illustrating an example of the decoder inFIG. 11according to at least one example embodiment.

Referring toFIG. 13, the decoder370may include a check bit generator380, a syndrome generator390, a corrector400and a selection circuit399.

The check bit generator380may generate q-bit check bits CHB based on the 2p-bit main data MD in the read codeword CW. The syndrome generator390may generate q-bit syndromes (or error indicators) SDR based on the q-bit check bits CHB and the q-bit parity data PRT in the read codeword CW. The corrector400may correct errors in the read codeword CW on a per symbol basis based on the q-bit syndromes SDR to output corrected main data C_MD. The selection circuit399may change the configuration of a first data and a second data in the one symbol to be provided to the check bit generator380, in response to the selection signal SS.

FIG. 14is a circuit diagram illustrating examples of the check bit generator and the syndrome generator inFIG. 13.

InFIG. 14, it is assumed that the main data MD includes 27bits, or 128 bits, the check bits CHB include 8 bits CB0˜CB7and the syndromes (or error indicators) SDR include 8 bits SY0˜SY7.

Referring toFIG. 14, the check bit generator380amay include a plurality of unit check bit generators381˜388.

The plurality of unit check bit generators381˜388may generate the check bits CB0˜CB7of the q-bit check bits CB based on the 2p-bit main data MD, respectively.

The unit check bit generator381may generate a first check bit CB0based on data bits D0, D2, . . . , D127of the main data MD, and the unit check bit generator381may include a plurality of XOR gates F11˜F15. The unit check bit generator382may generate a second check bit CB1based on data bits D14, D16, . . . , D127of the main data MD, and the unit check bit generator382may include a plurality of XOR gates F21˜F25. The unit check bit generator388may generate an eighth check bit CB7based on data bits D0, D1, . . . , D127of the main data MD, and the unit check bit generator388may include a plurality of XOR gates F81˜F85.

Each of the check bit generators381˜388may include other logic gates performing same operations as XOR gates.

The syndrome generator390amay include a plurality of XOR gates391˜398. Each of the XOR gates391˜398may perform an XOR operation on each of the check bits CB0˜CB7of the q-bit check bits CB and corresponding bit of the parity bits PB0˜PB7to output each of the syndromes SY0˜SY7. Therefore, the syndrome generator390amay generates the syndromes SY0˜SY7each having a logic level that indicates whether corresponding bits of the q-bit check bits CB and the parity bits PB0˜PB7are same with respect to each other. For example, when the check bit CB0and the parity bit PB are same with respect to each other, the syndrome SY0has a first logic level (low level) and when the check bit CB0and the parity bit PB are different from each other, the syndrome SY0has a second logic level (high level).

FIG. 15illustrates the selection circuit, the check bit generator and the syndrome generator inFIG. 13according to at least one example embodiment.

InFIG. 15, it is assumed that 128-bit main data MD and 8-bit parity data PRT are stored in the selected memory cell row.

Referring toFIG. 15, a selection circuit399amay include a plurality of selection elements SC1˜SCt (where, t is a natural number greater than 2), and each of the selection elements SC1˜SCt may be implemented with a multiplexer. The selection element SC1may select one of cell data CD135and CD0in response to the selection signal SS to output a first data D0. The selection element SC2may select one of cell data CD0and CD1in response to the selection signal SS to output a second data D1. The selection element SCt may select one of cell data CD134and CD135in response to the selection signal SS to output the check bit CB7. As described with reference toFIG. 5, the configuration of the first data and the second data constituting one symbol may be changed based on whether an even word-line or an odd word-line is selected of the plurality of word-lines WL0through WLn. For example, when the selection signal SS has a first logic level, the first data D0and the second data D1in one symbol may include the cell data CD135and CD0. For example, when the selection signal SS has a second logic level, the first data D0and the second data D1in one symbol may include the cell data CD0and CD1.

FIGS. 16A through 16Fare matrixes respectively illustrating values of the syndromes according to at least one example embodiment.

InFIGS. 16A through 16F, it is assumed that the main data MD includes 27(=128) bits, each syndrome (or error indicator) SDR includes 8 bits, and thus, the symbols S0˜S67correspond to 68. Each syndrome (or error indicator) SDR1represents bit values of the syndrome when one memory cell MC includes one error, and each syndrome (or error indicator) SDR2represents bit values of the syndrome when first and second data of adjacent two memory cells are assigned to one symbol and the each of the adjacent two memory cells has one error. The syndrome SDR1for one datum in a symbol (e.g., first data D0in symbol S0) inFIG. 16Amay be referred to as a first sub-error indicator while the syndrome SDR1for another datum in the symbol (e.g., second data D1in symbol S0) may be referred to as a second sub-error indicator.

InFIGS. 16A through 16F, the bit values of the syndrome SDR1and the bit values of the syndrome SDR2are linearly independent with respect to each other. Therefore, it is noticeable which memory cell or which symbol has an error (or errors) by decoding the syndrome SDR. In addition, the syndrome SDR2may be obtained by performing XOR operation on two adjacent syndromes SDR1corresponding to two adjacent memory cells having two errors. Thus, the bit values of the syndrome SDR2may be same as the bit values of the syndrome SDR1when only one of the two adjacent memory cells assigned to one symbol has one error. Therefore, it is noticeable whether one or two of the two adjacent memory cells assigned to one symbol has an error by decoding the syndrome SDR2.

FIG. 17is a block diagram illustrating an example of the corrector inFIG. 13according to at least one example embodiment.

Referring toFIG. 17, the corrector400may include a plurality of unit correctors410,460, and470. Each of the unit correctors410,460, and470may correct errors in each of the symbols SB0˜SB7, which are equal to or smaller than 2 on a per symbol basis, based on the syndromes (or error indicators) SDR and may provide each of corrected symbols SB0′˜SB67′.

FIG. 18is a circuit diagram illustrating an example of the corrector inFIG. 13according to at least one example embodiment.

FIG. 18illustrates the unit corrector410of the plurality of unit correctors410,460, and470.

Referring toFIG. 18, the unit corrector410may include a symbol decoder415and a data corrector450.

The symbol decoder415may determine whether at least one of the first and second data has an error based on the syndromes SDR. The data corrector450may correct errors in one symbol, which are equal to or smaller than two, based on first through third outputs of the symbol decoder415.

The symbol decoder415may include first through third sub decoders420,440and430.

The first sub decoder420may generate a first output signal OT1indicating whether the first data D0has an error based on the syndromes SDR (e.g., syndromes SDR1and SDR2fromFIGS. 16A-16F). The first sub decoder420may include a plurality of AND gates421˜427. The AND gate421receives syndrome values SY0and /SY1, the AND gate422receives syndrome values SY2and SY3, the AND gate423receives syndrome values /SY4and /SY5and the AND gate424receives syndrome values /SY6and SY7. The AND gate425receives outputs of the AND gates421and422, the AND gate426receives outputs of the AND gates423and424and the AND gate427receives outputs of the AND gates425and426to provide the first output signal OT1. Therefore, when the first data D0has an error, the first output signal OT1is a high level. It should be understood that syndrome values received by the first sub decoder420may be syndrome values from syndrome SDR1for first data D0inFIG. 16A.

The second sub decoder440may generate a second output signal OT2indicating whether the second data D1has an error based on the syndromes SDR. The second sub decoder440may include a plurality of AND gates441˜447. The AND gate441receives syndrome values /SY0and /SY1, the AND gate442receives syndrome values /SY2and /SY3, the AND gate443receives syndrome values /SY4and SY5and the AND gate444receives syndrome values SY6and SY7. The AND gate445receives outputs of the AND gates441and442, the AND gate446receives outputs of the AND gates443and444and the AND gate447receives outputs of the AND gates445and446to provide the second output signal OT1. Therefore, when the second data D1has an error, the second output signal OT2is a high level. It should be understood that syndrome values received by the second sub decoder440may be syndrome values from SDR1for second data D1inFIG. 16A.

The third sub decoder430may generate a third output signal OT3indicating whether both the first data D0and the second data D1have errors based on the syndromes SDR. The third sub decoder430may include a plurality of AND gates431˜437. The AND gate431receives syndrome values SY0and /SY1, the AND gate432receives syndrome values SY2and SY3, the AND gate433receives syndrome values /SY4and SY5and the AND gate434receives syndrome values SY6and /SY7. The AND gate435receives outputs of the AND gates431and432, the AND gate436receives outputs of the AND gates433and434and the AND gate437receives outputs of the AND gates435and436to provide the third output signal OT3. Therefore, when both the first data D0and the second data D1have errors, the third output signal OT3is a high level. It should be understood that syndrome values received by the third sub decoder430may be syndrome values from SDR2for symbol Si inFIG. 16A.

The data corrector450may include OR gates451and452and XOR gates453and454.

The OR gate451receives the first output signal OT1and the third output signal OT3. The OR gate452receives the second output signal OT2and the third output signal OT3. The XOR gate453performs an XOR operation on the first data D0and an output of the OR gate451to output a corrected first data D0′. The XOR gate454performs an XOR operation on the second data D1and an output of the OR gate452to output a corrected second data D1′.

The syndrome values SY0˜SY7input to the first through third sub decoders420,440and430are independent with respect to each other. When the first data D0has an error, only the first output signal OT1is a high level. Therefore, when the first data D0has an error, the data corrector450may invert the first data D0to output the corrected first data D0′. When the second data D1has an error, only the second output signal OT2is a high level. Therefore, when the second data D1has an error, the data corrector450may invert the second data D1to output the corrected second data D1′. When both the first data D0and the second data D1have errors, only the third output signal OT3is a high level. Therefore, when both the first data D0and the second data D1have errors, the data corrector450may invert both the first data D0and the second data D1to output the corrected first data D0′ and the corrected second data D1′.

As fabrication processes of the semiconductor memory devices advance and the devices become smaller in size, errors in two adjacent memory cells in the memory cell array300may increase.

However, according to at least one example embodiment, two data of two adjacent memory cells are assigned to one symbol and one or two errors in the two adjacent memory cells having high probability of having errors are corrected by unit of the symbol. Therefore, a number of parity bits or check bits required for correcting errors may be reduced.

FIG. 19is a flow chart illustrating a method of correcting errors in a semiconductor memory device according to at least one example embodiment.

Hereinafter, there will be description on a method of correcting errors in a semiconductor memory device with reference toFIGS. 3 through 19.

Referring toFIGS. 3 through 19, in a write operation on the semiconductor memory device200a, the ECC circuit350generates the q-bit parity data PRT based on the 2p-bit main data MD from the memory controller100, and writes the codeword CW including the main data MD and the parity data PRT in the memory cell array300, where q is greater than p and p and q are natural numbers equal to or greater than two. In a read operation on the semiconductor memory device200, the I/O gating circuit290reads the codeword CW including the 2p-bit main data MD and the q-bit parity data PRT from a selected memory cell row of the memory cell array300(S110).

The ECC circuit350generates q-bit syndromes SDR based on the read codeword CW (S120.) The q-bit syndromes may be generated based on q-bit check bits CHB and the q-bit parity data PRT and the q-bit check bits CHB may be generated based on the 2p-bits main data MD. The decoder370may correct errors in the read codeword CW on a per symbol basis, based on the syndromes SDR, where a first data of a first memory cell of the selected memory cell row and a second data of a second memory cell of the selected memory cell row are assigned one symbol (S130). The first memory cell and the second memory cell may be adjacent to each other. Values of the q-bit syndromes SDR may be linearly independent in first through third cases. The first case corresponds to a case when the first data has an error and the second data has no error, the second case corresponds to a case when the first data has no error and the second data has an error and the third case corresponds to a case when the first data has an error and the second data has an error respectively.

Therefore, according to example embodiments, errors are corrected in a codeword read from the selected memory cell row, two data of two adjacent memory cells are assigned to one symbol and one or two errors in the two adjacent memory cells having high probability of having errors are corrected by unit of the symbol. Therefore, a number of parity bits or check bits required for correcting errors may be reduced.

FIG. 20is a structural diagram illustrating a semiconductor memory device according to at least one example embodiment.

Referring toFIG. 20, a semiconductor memory device600may include first through kth semiconductor integrated circuit layers LA1through LAk, in which the lowest first semiconductor integrated circuit layer LA1is assumed to be an interface or control chip and the other semiconductor integrated circuit layers LA2through LAk are assumed to be slave chips including core memory chips. The first through kth semiconductor integrated circuit layers LA1through LA may transmit and receive signals therebetween through through-silicon-vias (TSVs). The lowest first semiconductor integrated circuit layer LA1as the interface or control chip may communicate with an external memory controller through a conductive structure formed on an external surface. A description will be made regarding structure and an operation of the semiconductor memory device600by mainly using the first semiconductor integrated circuit layer LA1or610as the interface or control chip and the nth semiconductor integrated circuit layer LAk or620as the slave chip.

The first semiconductor integrated circuit layer610may include various peripheral circuits for driving memory regions621provided in the kth semiconductor integrated circuit layer620. For example, the first semiconductor integrated circuit layer610may include a row (X)-driver6101for driving word-lines of a memory, a column (Y)-driver6102for driving bit lines of the memory, a data input/output unit (Din/Dout)6103for controlling input/output of data, a command buffer (CMD)6104for receiving a command CMD from outside and buffering the command CMD, and an address buffer (ADDR)6105for receiving an address from outside and buffering the address. The memory region621may include resistive type memory cells or dynamic memory cells as described with reference to4A through5.

The first semiconductor integrated circuit layer610may further include a control logic6107. The control logic6107may control an access to the memory region621based on a command and an address signal from a memory controller and may generate control signals for accessing the memory region621.

The kth semiconductor integrated circuit layer620may include the memory region621including a memory call array and an ECC circuit622. The ECC circuit622may perform ECC encoding and ECC decoding on data in the memory region621. The ECC circuit622may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

FIG. 21illustrates a memory system including the semiconductor memory device according to at least one example embodiment.

Referring toFIG. 21, a memory system700may include a memory module710and a memory controller720. The memory module710may include at least one semiconductor memory device730mounted on a module board. The semiconductor memory device730may employ the semiconductor memory device200aofFIG. 3. For example, the semiconductor memory device730may be constructed as a MRAM chip or a DRAM chip. In addition, the semiconductor memory device730may include a stack of semiconductor chips. In this case, the semiconductor chips may include at least one master chip731and at least one slave chip732. Signal transfer between the semiconductor chips may occur via through-silicon vias TSV.

The master chip731and the slave chip732may employ the semiconductor memory device200aofFIG. 3. Therefore, each of the master chip731and the slave chip732may include a memory cell array having resistive type memory cells or dynamic memory cells and an ECC circuit that performs ECC encoding and ECC decoding on data in the memory cell array. The ECC circuit may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

In addition, in at least one example embodiment, a three dimensional (3D) memory array is provided in semiconductor memory device730. The 3D memory array is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. The following patent documents, which are hereby incorporated by reference, describe suitable configurations for the 3D memory arrays, in which the three-dimensional memory array is configured as a plurality of levels, with word-lines and/or bit-lines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

The memory module710may communicate with the memory controller720via a system bus. Data DQ, a command/address CMD/ADD, and a clock signal CLK may be transmitted and received between the memory module710and the memory controller720via the system bus.

FIG. 22is a block diagram illustrating a memory system including the semiconductor memory device according to at least one example embodiment.

Referring toFIG. 22, a memory system740may include optical links741and742, a controller750, and a semiconductor memory device760. The optical links741and742interconnect the controller750and the semiconductor memory device760. The controller750may include a control unit751, a first transmitter752, and a first receiver754. The control unit751may transmit a first electrical signal SN1to the first transmitter752. The first electrical signal SN1may include command signals, clock signals, address signals, or write data transmitted to the semiconductor memory device760.

The first transmitter752may include a first optical modulator753, and the first optical modulator753may convert the first electrical signal SN1into a first optical transmission signal OTP1EC and may transmit the first optical transmission signal OTP1EC to the optical link741. The first optical transmission signal OTP1EC may be transmitted by serial communication through the optical link741. The first receiver754may include a first optical demodulator755, and the first optical demodulator755may convert a second optical reception signal OPT2OC received from the optical link742into a second electrical signal SN2and may transmit the second electrical signal SN2to the control unit750.

The semiconductor memory device760may include a second receiver761, a memory region765having resistive type memory cells or dynamic memory cells, and a second transmitter764. The second receiver761may include a second optical demodulator762, and the second optical demodulator762may convert the first optical reception signal OPT1OC received from the optical link741into the first electrical signal SN1and may transmit the first optical reception signal OPT1OC to the memory region765.

In the memory region765, write data is written to the memory cells in response to the first electrical signal SN1, or data read from the memory region765is transmitted as a second electrical signal SN2to the second transmitter764. In addition, the memory region765may include an ECC circuit that performs ECC encoding and ECC decoding on data in the memory cells. The ECC circuit may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors. The second electrical signal SN2may include clock signals and read data transmitted to the memory controller750. The second transmitter763may include a second optical modulator764, and the second optical modulator764may convert the second electrical signal SN2into the second optical data signal OPT2EC and transmits the second optical data signal OPT2EC to the optical link742. The second optical transmission signal OTP2EC may be transmitted by serial communication through the optical link742.

FIG. 23is a block diagram illustrating a server system including the semiconductor memory device according to at least one example embodiment.

Referring toFIG. 23, a server system770includes a memory controller772and a plurality of memory modules773. Each of the memory modules773may include a plurality of semiconductor memory devices774. The semiconductor memory devices774may include a memory cell array having resistive type memory cells or dynamic memory cells and an ECC circuit that performs ECC encoding and ECC decoding on data in the memory cell array. The ECC circuit may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

In the server system770, a second circuit board776is coupled to each of sockets775of a first circuit board771. The server system770may be designed to have a channel structure in which one second circuit board776is connected to the first circuit board771according to signal channels.

Meanwhile, a signal of the memory modules773may be transmitted via an optical IO connection. For the optical IO connection, the server system770may further include an electric-to-optical conversion unit777, and each of memory modules773may further include an optical-to-electrical conversion unit778.

The memory controller772is connected to the electric-to-optical conversion unit777through an electrical channel EC. The electric-to-optical conversion unit777converts an electrical signal received from the memory controller772through the electrical channel EC into an optical signal and transmits the optical signal to an optical channel OC. Also, the electric-to-optical conversion unit777converts an optical signal received through the optical channel OC into an electrical signal and transmits the electrical signal to the electrical channel EC.

The memory module773is connected to the electric-to-optical conversion unit777through the optical channel OC. An optical signal applied to the memory module773may be converted into an electrical signal through the optical-to-electric conversion unit778and may be transmitted to the semiconductor memory chips774. The server system770including the optical connection memory modules may support high storage capacity and a high processing speed.

FIG. 24is a block diagram illustrating a computing system including the semiconductor memory device according to at least one example embodiment.

Referring toFIG. 27, a computing system800may be mounted on a mobile device or a desktop computer. The computing system800may include a memory system810, a central processing unit (CPU)820, a RAM830, a user interface840, and a modem850such as a baseband chipset, which are electrically connected to a system bus805. The computing system800may further include an application chipset, a camera image processor (CIS), and an input/output device.

The user interface840may be an interface for transmitting data to a communication network or receiving data from the communication network. The user interface840may have a wired or wireless form, and may include an antenna or a wired/wireless transceiver. Data applied through the user interface840or the modem850or processed by the CPU820may be stored in the semiconductor memory system810.

The memory system810may include a semiconductor memory device812and a memory controller811. Data processed by the CPU820or external data is stored in the semiconductor memory device812. The semiconductor memory device812may include a memory cell array having resistive type memory cells or dynamic memory cells and an ECC circuit that performs ECC encoding and ECC decoding on data in the memory cell array. The ECC circuit may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

When the computing system800is a device that performs wireless communications, the computing system800may be used in a communication system such as code division multiple access (CDMA), global system for mobile communication (GSM), North American multiple access (NADC), or CDMA2000. The computing system800may be mounted on an information processing device such as a personal digital assistant (PDA), a portable computer, a web tablet, a digital camera, a portable media player (PMP), a mobile phone, a wireless phone, or a laptop computer.

FIG. 25is a block diagram illustrating a computing system including the semiconductor memory device according to at least one example embodiment.

Referring toFIG. 25, a computing system1100may include a processor1110, an input/output hub (IOH)1120, an input/output controller hub (ICH)1130, at least one memory module1140and a graphics card1150. In some example embodiments, the computing system1100may be a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, etc.

The processor1110may perform various computing functions, such as executing specific software for performing specific calculations or tasks. For example, the processor1110may be a microprocessor, a central process unit (CPU), a digital signal processor, or the like. In some example embodiments, the processor1110may include a single core or multiple cores. For example, the processor1110may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. AlthoughFIG. 21illustrates the computing system1100including one processor1110, in some example embodiments, the computing system1100may include a plurality of processors. The processor1110may include an internal or external cache memory.

The processor1110may include a memory controller1111for controlling operations of the memory module1140. The memory controller1111included in the processor1110may be referred to as an integrated memory controller (IMC). A memory interface between the memory controller1111and the memory module1140may be implemented with a single channel including a plurality of signal lines, or may be implemented with multiple channels, to each of which at least one memory module1140may be coupled. In some example embodiments, the memory controller1111may be located inside the input/output hub1120, which may be referred to as a memory controller hub (MCH).

The memory module1140may include a plurality of semiconductor memory devices that store data provided from the memory controller1111. Each of the plurality of semiconductor memory devices may include a memory cell array having resistive type memory cells or dynamic memory cells and an ECC circuit that performs ECC encoding and ECC decoding on data in the memory cell array. The ECC circuit may correct errors in a codeword read from the selected memory cell row on a per symbol basis, where two data of two adjacent memory cells are assigned to one symbol as described with reference toFIGS. 10 through 18. Therefore, a number of parity bits or check bits required for correcting errors may be reduced by correcting one or two errors in the two adjacent memory cells having high probability of having errors.

The input/output hub1120may manage data transfer between the processor1110and devices, such as the graphics card1150. The input/output hub1120may be coupled to the processor1110via various interfaces. For example, the interface between the processor1110and the input/output hub1120may be a front side bus (FSB), a system bus, a HyperTransport, a lightning data transport (LDT), a QuickPath interconnect (QPI), a common system interface (CSI), etc. AlthoughFIG. 21illustrates the computing system1100including one input/output hub1120, in some example embodiments, the computing system1100may include a plurality of input/output hubs. The input/output hub1120may provide various interfaces with the devices. For example, the input/output hub1120may provide an accelerated graphics port (AGP) interface, a peripheral component interface-express (PCIe), a communications streaming architecture (CSA) interface, etc.

The graphics card1150may be coupled to the input/output hub1120via AGP or PCIe. The graphics card1150may control a display device (not shown) for displaying an image. The graphics card1150may include an internal processor for processing image data and an internal semiconductor memory device. In some example embodiments, the input/output hub1120may include an internal graphics device along with or instead of the graphics card1150outside the input/output hub1120. The graphics device included in the input/output hub1120may be referred to as integrated graphics. Further, the input/output hub1120including the internal memory controller and the internal graphics device may be referred to as a graphics and memory controller hub (GMCH).

The input/output controller hub1130may perform data buffering and interface arbitration in order to efficiently operate various system interfaces. The input/output controller hub1130may be coupled to the input/output hub1120via an internal bus, such as a direct media interface (DMI), a hub interface, an enterprise Southbridge interface (ESI), PCIe, etc. The input/output controller hub1130may provide various interfaces with peripheral devices. For example, the input/output controller hub1130may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input/output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.

In some example embodiments, the processor1110, the input/output hub1120and the input/output controller hub1130may be implemented as separate chipsets or separate integrated circuits. In other example embodiments, at least two of the processor1110, the input/output hub1120and the input/output controller hub1130may be implemented as a single chipset.

The present disclosure may be applied to systems using semiconductor memory devices. The present disclosure may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.