Method and apparatus for switching clock sources

A method for switching clock sources is provided. In the method, Precision Time Protocol, PTP, packets are monitored using each of PTP ports which connect to a new grandmaster (401). A frequency and a phase for the PTP port are calculated based on the PTP packets (402). In response to a successful check for the frequency and the phase, the PTP port is added to a candidate list (403). A phase calibration and a phase stability check may be introduced prior to the alternate BMCA.

CROSS REFERENCE TO RELATED APPLICATION

This application is a 35 U.S.C. § 371 National Stage of International Patent Application No. PCT/CN2019/084888, filed Apr. 29, 2019.

TECHNICAL FIELD

The present disclosure generally relates to the field of signal processing, and more specifically to a method and apparatus for switching clock sources.

BACKGROUND

Partial-Support Telecom Boundary Clock (T-BC-P) is a boundary clock with a plurality of Precision Time Protocol (PTP) ports which are connected to a plurality of Grandmasters (GMs) and one of which may be Slave and remaining ports of which may be in a state “Passive” or “Master”, which is decided by the Best Master Clock Algorithm (BMCA). The Slave port may calculate and recover a phase/time which is distributed by an upstream GM and which will be distributed to a downstream clock via the Master ports. If the T-BC-P gets a new GM with a higher priority via another PTP port, a PTP clock may select this PTP port as the Slave port based on the BMCA, and the local phase/time may be calibrated based on the new GM and then distributed to the downstream clock. The prior art architecture for distribution of the phase/time with partial timing support from the network functions in the unicast mode only.

In an actual timing network environment, there may be a plurality of clock sources which can provide a high-accuracy Frequency or Phase. The T-BC-P may select a clock source which has the highest priority based on the Alternate BMCA. The T-BC-P has to spend some time calibrating the Frequency and Phase from the clock source. When the T-BC-P is locked to a clock source and providing the Frequency and Phase downstream, a higher priority clock source may connect to the network. According to the Alternate BMCA, the T-BC-P has to select the new clock source immediately, but its upstream node may not finish calibration for the current clock source. Therefore, at this point, the T-BC-P may provide unstable Frequency and Phase to its downstream nodes. If the downstream nodes are very sensitive to the input Frequency and Phase, a problem may occur.

A process for PTP port switchover when the new GM joins is shown inFIG.1. As illustrated inFIG.1, since the GM1has priority1=10 and the GM2has priority2=20, the T-BC-P-3may select the GM1as the best clock source. After some time, the Frequency and Phase on the T-BC-P-3may be stable, and the Frequency and Phase from the GM2may also be calibrated. The T-BC-P-3may provide the stable Frequency and Phase to downstream devices, e.g., the T-BC-P/T-TSC-P (Partial-Support Telecom Time Slave Clock). Then, the T-BC-P-1may be restarted, e.g. due to release upgrade, device replacement or node failure, etc. At this time, the T-BC-P-3may smoothly switch over to the GM2. When the T-BC-P-1is restored, the T-BC-P-3will switch back to the GM1immediately based on the Alternate BMCA. However, since the T-BC-P-1may not have finished calibration for the GM1, quality of the Frequency and Phase distributed by the T-BC-P-1to the T-BC-P-3may not be adequate. The function of the downstream node may be negatively affected.

SUMMARY

It is an object of the present disclosure to propose a new method and apparatus for smooth switchover between clocks sources.

According to a first aspect of the present disclosure, a method for switching clock sources is provided. In the method, Precision Time Protocol, PTP, packets are monitored using each of PTP ports which connect to a new grandmaster. A frequency and a phase for the PTP port are calculated based on the PTP packets. In response to a successful check for the frequency and the phase, the PTP port is added to a candidate list.

In an alternative embodiment of the first aspect, the method may further comprise: in response to an unsuccessful check for the frequency and the phase, checking a frequency and a phase for a next PTP port of the PCT ports.

In a further alternative embodiment of the first aspect, the successful check may be fulfilled in response to the phase being in a PHASE_LOCKED state.

In a further alternative embodiment of the first aspect, the successful check may be fulfilled in response to the frequency being in a FREQ_LOCKED state and a value of the phase meeting a phase threshold.

In a yet further alternative embodiment of the first aspect, the phase threshold may be predetermined or may be dynamically changed by users.

According to a second aspect of the present disclosure, an apparatus for switching clock sources is provided. The apparatus comprises a processor and a memory communicatively coupled to the processor and adapted to store instructions. When the instructions are executed by the processor, the instructions cause the apparatus to perform operations of the method according to the above first aspect.

According to a third aspect of the present disclosure, a non-transitory computer readable medium having a computer program stored thereon is provided. When the computer program is executed by a set of one or more processors of an apparatus, the computer program causes the apparatus to perform operations of the method according to the above first aspect.

In the present disclosure, a phase calibration and a phase stability check may be introduced prior to the Alternate BMCA. Therefore, the clock source switchover may occur after the PTP port obtains a desired frequency and/or phase so that a stable frequency and phase output may be provided downstream.

DETAILED DESCRIPTION

The following detailed description describes a method and apparatus for switching clock sources. In the following detailed description, numerous specific details such as logic implementations, types and interrelationships of system components, etc. are set forth in order to provide a more thorough understanding of the present disclosure. It should be appreciated, however, by one skilled in the art that the present disclosure may be practiced without such specific details. In other instances, control structures, circuits and instruction sequences have not been shown in detail in order not to obscure the present disclosure. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

An electronic device stores and transmits (internally and/or with other electronic devices) code (which is composed of software instructions and which is sometimes referred to as computer program code or a computer program) and/or data using machine-readable media (also called computer-readable media), such as machine-readable storage media (e.g., magnetic disks, optical disks, read only memory (ROM), flash memory devices, phase change memory) and machine-readable transmission media (also called a carrier) (e.g., electrical, optical, radio, acoustical or other forms of propagated signals—such as carrier waves, infrared signals). Thus, an electronic device (e.g., a computer) includes hardware and software, such as a set of one or more processors coupled to one or more machine-readable storage media to store code for execution on the set of processors and/or to store data. For instance, an electronic device may include non-volatile memory containing the code since the non-volatile memory can persist code/data even when the electronic device is turned off (when power is removed), and while the electronic device is turned on, that part of the code that is to be executed by the processor(s) of that electronic device is typically copied from the slower non-volatile memory into volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)) of that electronic device. Typical electronic devices also include a set of one or more physical interfaces to establish connections (to transmit and/or receive code and/or data using propagating signals) with other electronic devices. One or more parts of an embodiment of the present disclosure may be implemented using different combinations of software, firmware, and/or hardware.

According to the present disclosure, if there is a PTP Slave port in the T-BC-P, when a higher priority GM connects to the T-BC-P, a monitoring function may be involved prior to the Alternate BMCA. An additional PTP port of the T-BC-P which is connected to the new GM may monitor PTP packets and calculate the Frequency and Phase. After the additional PTP port finishes calibration for the new GM, the additional PTP port may be added into a BMCA candidate list. Based on a result of the Alternate BMCA, the PTP clock may smoothly switch over to the new higher priority GM with no impact on PTP performance.

FIG.2is a block diagram illustrating exemplary functional modules for switchover between clock sources according to some embodiments of the present disclosure. After PTP packets are obtained by the PTP packet via the ports and before the PTP packets are transferred to the PTP protocol stack BMCA which in turn forwards the packets to the PTP packet sender, a phase calibrator module201, a phase stability check module202and a threshold configuration module203may function in a way as specifically described with respect toFIG.3below.

FIG.3is exemplary processes for switchover between clock sources according to some embodiments of the present disclosure. A phase calibration and a phase stability check may be introduced for each of the PTP ports which receive packets from the newly joined GM. These PTP ports may not become slave ports immediately when the new GM joins. The BMCA will take effect depending on a result of the stability check. Furthermore, threshold configuration may be provided for users to change a threshold value configured for the phase stability check.

At block301, PTP port monitoring may be started. Then, in block302, packets may be received via the PTP port and calibration may be performed, e.g. by the phase calibrator module201as shown inFIG.2. The phase calibrator module201may obtain packets received through each PTP port, and calculate the Frequency and Phase for this PTP port based on the received packet stream. The phase calibration may trigger the phase stability check.

At block303, the phase stability check may be made, e.g. by the phase stability check module202as shown inFIG.2. The phase stability check module202may check whether the Frequency and Phase are locked. As an example, the phase stability check module202may determine whether the phase for the current PTP port is in a PHASE_LOCKED state, or whether the frequency for the current PTP port is in a FREQ_LOCKED state and the phase value for the current PTP port satisfies a threshold, e.g., above the threshold or below the threshold, and if so, the process may proceed to block304. The block303may be a polling function in which if the result of the check is negative, the process may proceed back to block302with regard to a next PTP port. As a further example, the threshold for judging the phase value may be a predetermined threshold, or it may be a parameter dynamically changed by users.

At block304, as a result of a successful check, the Alternate BMCA may be run.

FIG.4is a flow chart illustrating a method400for switching clock sources according to some embodiments of the present disclosure. The method400may be performed in functional switching modules (e.g., those shown inFIG.2) by way of example only for convenience of description but it is not limited thereto. As an example, operations in this and other flow charts will be described with reference to the exemplary embodiments of the other figures. However, it should be appreciated that the operations of the flow charts may be performed by embodiments of the present disclosure other than those discussed with reference to the other figures, and the embodiments of the present disclosure discussed with reference to these other figures may perform operations different than those discussed with reference to the flow charts.

In one embodiment, the method400begins with monitoring PTP packets received via each of PTP ports connected to a new GM (block401). Then, a frequency and a phase for the current PTP port may be calculated based on the received PTP packets (block402). A phase stability check may be made to the frequency and the phase for the current PTP port. In the case that the check is successful, the current PTP port may be added to a candidate list for the BMCA (block403).

As an example, if the check is unsuccessful, the phase stability check may be made to a frequency and a phase for a next PTP port connected to the new GM (block404). In other words, the phase stability check may be made continually until the result is successful.

As an example, it may be determined that the check is successful if the phase for the checked PTP port is in a PHASE_LOCKED state. As another example, it may be determined that the check is successful if the frequency for the checked PTP port is in a FREQ_LOCKED state and the phase value for the checked PTP port meets a phase threshold. As a further example, the check may be successful if the frequency for the checked PTP port is in the FREQ_LOCKED state and the phase value for the checked PTP port is less than the phase threshold. As a still further example, the phase threshold may be a predetermined parameter or a parameter dynamically changed by users.

FIG.5is a block diagram illustrating an apparatus500for switching clock sources according to some embodiments of the present disclosure. As an example, the apparatus500may be implemented in functional switching modules (e.g., those shown inFIG.2), but it is not limited thereto. It should be appreciated that the apparatus500may be implemented using components other than those illustrated inFIG.5.

With reference toFIG.5, the apparatus500may comprise at least a processor501, a memory502, an interface503and a communication medium504. The processor501, the memory502and the interface503may be communicatively coupled to each other via the communication medium504.

The processor501may include one or more processing units. A processing unit may be a physical device or article of manufacture comprising one or more integrated circuits that read data and instructions from computer readable media, such as the memory502, and selectively execute the instructions. In various embodiments, the processor501may be implemented in various ways. As an example, the processor501may be implemented as one or more processing cores. As another example, the processor501may comprise one or more separate microprocessors. In yet another example, the processor501may comprise an application-specific integrated circuit (ASIC) that provides specific functionality. In still another example, the processor501may provide specific functionality by using an ASIC and/or by executing computer-executable instructions.

The memory502may include one or more computer-usable or computer-readable storage medium capable of storing data and/or computer-executable instructions. It should be appreciated that the storage medium is preferably a non-transitory storage medium.

The interface503may be a device or article of manufacture that enables the apparatus500to send data to or receive data from external devices.

The communication medium504may facilitate communication among the processor501, the memory502and the interface503. The communication medium504may be implemented in various ways. For example, the communication medium504may comprise a Peripheral Component Interconnect (PCI) bus, a PCI Express bus, an accelerated graphics port (AGP) bus, a serial Advanced Technology Attachment (ATA) interconnect, a parallel ATA interconnect, a Fiber Channel interconnect, a USB bus, a Small Computing System Interface (SCSI) interface, or another type of communications medium.

In the example ofFIG.5, the instructions stored in the memory502may include those that, when executed by the processor501, cause the apparatus500to implement the method described with respect toFIG.4.

FIG.6is another block diagram illustrating an apparatus600for switching clock sources according to some embodiments of the present disclosure. As an example, the apparatus600may be implemented in functional switching modules (e.g., those shown inFIG.2), but it is not limited thereto. It should be appreciated that the apparatus600may be implemented using components other than those illustrated inFIG.6.

With reference toFIG.6, the apparatus600may comprise at least a monitoring unit601, a calculating unit602and an adding unit603.

The monitoring unit601may be adapted to perform at least the operation described in the block401ofFIG.4. The calculating unit602may be adapted to perform at least the operation described in the block402ofFIG.4. The adding unit603may be adapted to perform at least the operation described in the block403ofFIG.4.

As an example, the apparatus600may further comprise at least a checking unit604. The checking unit604may be adapted to perform at least the operation described in the block404ofFIG.4.

Some units are illustrated as separate units inFIG.6. However, this is merely to indicate that the functionality is separated. The units may be provided as separate elements. However, other arrangements are possible, e.g., some of them may be combined as one unit. Any combination of the units may be implemented in any combination of software, hardware, and/or firmware in any suitable location. For example, there may be more controllers configured separately, or just one controller for all of the components.

The units shown inFIG.6may constitute machine-executable instructions embodied within e.g. a machine readable medium, which when executed by a machine will cause the machine to perform the operations described. Besides, any of these units may be implemented as hardware, such as an application specific integrated circuit (ASIC), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) or the like.

Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of transactions on data bits within a computer memory. These algorithmic descriptions and representations are ways used by those skilled in the signal processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of transactions leading to a desired result. The transactions are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method transactions. The required structure for a variety of these systems will appear from the description above. In addition, embodiments of the present disclosure are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of embodiments of the present disclosure as described herein.

An embodiment of the present disclosure may be an article of manufacture in which a non-transitory machine-readable medium (such as microelectronic memory) has stored thereon instructions (e.g., computer code) which program one or more signal processing components (generically referred to here as a “processor”) to perform the operations described above. In other embodiments, some of these operations might be performed by specific hardware components that contain hardwired logic (e.g., dedicated digital filter blocks and state machines). Those operations might alternatively be performed by any combination of programmed signal processing components and fixed hardwired circuit components.

In the foregoing detailed description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Throughout the description, some embodiments of the present disclosure have been presented through flow diagrams. It should be appreciated that the order of transactions and transactions described in these flow diagrams are only intended for illustrative purposes and not intended as a limitation of the present disclosure. One having ordinary skill in the art would recognize that variations can be made to the flow diagrams without departing from the spirit and scope of the present disclosure as set forth in the following claims.