Systems and methods for phase synchronization of local oscillator paths in oscillator-operated circuits

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

FIELD OF USE

This disclosure relates to phase-locked loop (PLL) circuits, and specifically, to systems and methods for phase synchronization of local oscillator paths in oscillator-operated circuits.

BACKGROUND OF THE DISCLOSURES

Circuits typically employ oscillators to generate clock signals, e.g., in frequency synthesizers, serializers, deserializers, etc. As circuit components are operated under different clock signals, phase synchronization among different local oscillator (LO) paths on one circuit chip or on multiple circuit chips is often required. A LO path usually includes a fractional-N PLL, e.g., the frequency of the output clock signal is equivalent to the frequency of the input clock signal multiplied by a non-integer value, and the distribution circuits include dividers and buffers. The dividers can sometimes introduce phase ambiguity among different PLLs although a reference clock is shared among the different PLLs.

For example, in a wireless multiple-input multiple-output (MIMO) system, multiple transmitting and receiving signal paths need to be in-phase. At times, different dividers are used at different MIMO channels, which introduce phase ambiguity such that phases of the transmission signals at the different MIMO channels are not aligned. Sometimes a single PLL is used to track and lock the phases of transmission signals for all MIMO channels so that phase is synchronized across different MIMO channels have. However, for circuits of a larger size, using one single PLL for all MIMO channels requires a significant amount of wiring. On the other hand, when multiple PLLs are used, phase synchronization between the multiple PLLs on one circuit chip or between PLLs on multiple circuit chips can sometimes be implemented through a shared reference clock such that the phases at different oscillator outputs of the different PLLs are synchronized. However, even when the multiple PLLs share the same reference clock, the individual divider at each PLL can still introduce an incoherent state to the phases, thereby resulting in phase ambiguities in the LO paths on the circuit chip.

SUMMARY

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

In some implementations, the first phase-locked loop circuit includes an oscillator configured to generate an oscillator clock, a multi-modulus divider configured to divide the oscillator clock by a non-integer value to match a reference frequency, and a first sigma-delta modulator. The first sigma-delta modulator includes a multiplier configured to generate a multiplier output signal representing a product of a fractional part of a frequency control word and the first counter output signal, and an adder. The adder is configured to generate a sum of an integer part of the frequency control word and the generated product of the fractional part of the frequency control word and the counter value corresponding to the first counter output signal, send the generated sum as a division ratio to the multi-modulus divider.

In some implementations, the first circuit includes a second phase-locked loop coupled to the first counter. The second phase-locked loop is configured to receive the first counter output signal as a second synchronization clock and generate a second output signal having rising edges aligned according to the first counter output signal.

In some implementations, the first circuit includes a second counter configured to receive the first clock signal as an input clock and to generate a second counter output signal according to the first clock signal. The first circuit further includes a second phase-locked loop coupled to the second counter. The second phase-locked loop is configured to receive the second counter output signal, the second counter output signal serving as a second synchronization clock for the second phase-locked loop, and to generate a second output signal having rising edges aligned according to the second counter output signal.

In some implementations, the first counter output signal is sampled to match a modulator clock signal controlling the first sigma-delta modulator when a frequency of the first counter output signal and a frequency of the modulator clock signal are different.

In some implementations, the first counter is implemented as a multi-bit counter. The first counter is configured to generate the first counter output signal in response to the first clock signal irrespective of whether the first phase-locked loop is powered on or powered off.

In some implementations, the multiplier is configured to multiply a number of least significant bits of the integer part of the frequency control word and the fractional part of the frequency control word with the counter value corresponding to the first counter output signal to generate a sigma-delta modulator output. The first circuit further includes one or more serially connected half-dividers configured to divide the oscillator clock signal consecutively. The first circuit further includes a comparator configured to compare a phase corresponding to a feedback signal derived from the serially divided oscillator clock signal with a phase corresponding to the sigma-delta modulator output to generate an error component indicative of a phase difference between the feedback signal and the sigma-delta modulator output. The adder is configured to add the integer part of the frequency control word excluding a number of least significant bits of the integer part of the frequency control word, the sigma-delta modulator output and the error component to generate the division ratio for the multi-modulus divider.

In some implementations, the number of least significant bits of the integer part of the frequency control word that are combined with the fractional part of the frequency control word is determined by a number of the one or more serially connected half-dividers used to divide the oscillator clock signal.

In some implementations, the first circuit further includes one or more flip-flops governed by a feedback clock, the one or more flip-flops being configured to sample the serially divided oscillator clock signal according to the feedback clock to generate the feedback signal. The first phase-locked loop circuit is further configured to divide the oscillator clock signal by the division ratio, and sample the divided oscillator clock signal with the same feedback clock.

In some implementations, the system further includes a second circuit, which in turn includes a second counter configured to generate a second counter output signal in response to a second clock signal controlling the second counter. The second circuit further includes a second phase-locked loop coupled to the second counter. The second phase-locked loop is configured to receive the second counter output signal as a second synchronization clock and generate a second output signal having rising edges aligned according to the second counter output signal. The system further includes a reset component coupled to the first circuit and the second circuit. The reset component is configured to send a same reset signal to synchronize the first counter on the first circuit and the second counter on the second circuit.

Embodiments described herein provide a method for phase synchronization in local oscillator paths. A first counter output signal is generated, at a first counter disposed on a first circuit, in response to a first clock signal controlling the first counter. The first counter output signal is received, at a first phase-locked loop disposed on the first circuit, as a first synchronization clock for the first phase-locked loop. A first output signal having rising edges aligned according to the first counter output signal is generated.

DETAILED DESCRIPTION

This disclosure describes methods and systems for phase synchronization of local oscillator paths in oscillator-operated circuits. A circuit that employs more than one PLL typically faces the challenge to synchronize the various PLL output signals to a reference clock, as different oscillators employed in different PLLs cause phase ambiguities. In addition, in a fractional-N generation PLL, which usually employs a sigma-delta modulator (SDM) to generate a division ratio for the multi-modulus divider (MMDIV), as further illustrated inFIG. 3, the MMDIV output and the SDM operation both need to be synchronized to the same reference clock of the PLL.

Embodiments described herein provides a counter, for instance a crystal counter that includes a voltage-controlled oscillator (VCO) or digitally-controlled oscillator (DCO) generating a clock signal that operates the counter. The counter is subsequently used to generate a counter output signal as a “golden” phase reference to synchronize oscillator phases of PLLs on the circuit as shown inFIG. 1. The phase reference is also used to control the SDM within a fractional-N PLL on a circuit (as shown inFIG. 2), and to control the phase of the divider output of the PLL (as shown inFIG. 4). In this way, as long as the multiple PLLs share the same phase reference, the output phases of the PLLs are synchronized. The phase synchronization described herein (as shown inFIGS. 1-4) requires little hardware overhead, e.g., by adding only a low-power crystal clock counter and minimal modification in the SDM.

FIG. 1is a block diagram illustrating an example circuit100using a counter110or120to generate a phase reference signal, according to some embodiments described herein. A circuit chip101includes multiple PLLs103,105,107, etc. in an embodiment. Each PLL103,105or107receives a reference clock to lock the frequency and/or phase of the output clock signal of the PLL, e.g., the phase of the output clock signal is fixed relative to the phase of the reference clock. By fixating the phase of the output clock signal, the output clock signal of the PLL is “locked” to the reference clock.

A crystal counter110, operated by a clock signal102that is generated by a crystal oscillator (not shown), is disposed on the circuit chip101. For example, the crystal counter110can be implemented as a multi-bit ripple counter. The ripple counter usually includes a number of serially connected latches, and the first latch is controlled by the clock signal102, and the subsequent latches are each controlled by the output of the preceding latch. The crystal counter110is configured to generate a counter output signal104, which forms rising edges as the counter accumulates. Thus, the crystal counter110creates “golden” time stamps for phase synchronization. Sometimes the counter output signal104from the counter110includes a counting error due to the propagation delay between the input clock signal102and the counter output signal104. Further description on correcting the propagation delay induced error in a counter output signal can be found in co-pending and commonly-assigned U.S. application Ser. No. 15/812,797, filed on the same day, which is hereby expressly incorporated by reference in its entirety.

As shown at reference numeral101, for PLLs103,105,107, etc. on one circuit chip, only one counter110is used and the counter output signal104is distributed to multiple PLLs103,105,107, etc., and used as the reference clock by each PLL. Thus, in the example ofFIG. 1, the outputs of PLLs103,105,107, etc., on the circuit chip101are all synchronized as the PLL outputs are all “locked” to the same reference clock, e.g., the counter output signal104. In another embodiment, the PLLs103,105,107, etc., receive a counter output signal from a different counter (similar to110) as the reference clock, respectively, and all the counters are operated by the same clock signal102. In this way, as long as the different counters are configured to count in response to the same clock signal102, the PLLs103,105,107also remain synchronized.

For PLLs on different circuit chips101and111, each chip101or111is respectively configured to host a crystal counter110or120. Similar to the PLLs on circuit chip101, PLLs113,115,117, etc. on the circuit chip111are configured to receive the counter output signal114from the counter120and generate output signals that have their respective phases “locked” to the phase of the same counter output signal114. To synchronize the signal phases of PLLs on the circuit chip101and PLLs on the circuit chip111, a reset unit130is configured to generate and simultaneously send a reset signal131,132to reset and synchronize, in an embodiment, the counters110and120on different circuit chips such that the counters110and120are configured to restart with respect to the same crystal clock edge. In some embodiments, the reset unit130is configured to send reset signals periodically, intermittently and/or continuously. In an embodiment, the circuit chips101and111are operated by individual power-on-reset signals. Thus, as long as the circuit chips101and111are kept powered-on with the counters110and120, even when the PLLs103,105,107,113,115or117are temporarily shut down, the counters110and120remain synchronized.

In this way, as the counter time stamp captured in the counter output signal104or114is independent of the PLL reset, channel change, oscillator ambiguity (e.g., interference between oscillators operated at different frequencies, etc.) within each PLL and/or the divider initial phase within each PLL, and is only determined by the clock edge of the crystal clock signal102for the counter110and120, respectively. In addition, as the crystal clock signal102typically has a frequency below 100 MHz, the additional power consumption by adding an extra counter110to the circuit is rather insignificant.

It is noted that the two circuit chips101and111are for illustrative purpose only. A different number of circuit chips can be connected in a similar manner as shown with respect to101and111so as to share a common reset signal from reset130.

FIG. 2is a block diagram illustrating an example sigma-delta modulator (SDM) configured to employ a counter output signal, generated from the counter shown inFIG. 1, to synchronize the phase of the fractional part of a division signal, according to some embodiments described herein. An SDM is sometimes configured to convert a high-bit count digital signal into a low-bit count digital signal. For example, a high-bit count frequency control word (FCW), including bits representing the integer part211and bits representing the fractional part212, is modulated, by the SDM, onto a divisional ratio signal218corresponding to the FCW. As further described inFIG. 3, the SDM is used to provide the division ratio signal218to a multi-modulus divider (MMDIV)330in a fractional-N generation PLL.

As shown at circuit201, conventionally, an SDM includes an integrator205(e.g., a delay feedback loop) to integrate the fractional part of the FCW212continuously. The integrated output from the integrator205is then passed through a quantizer206and then the quantized output from the quantizer206is sent to an adder210. The integer part of the FCW211is added to the integrated and quantized fractional part of the FCW212at the adder210. In this way, the division ratio signal218is generated from the adder210over the period of time. The integrator205is often operated under a feedback clock signal, which typically varies between different PLLs, and thus the division ratio signal218across different PLLs is not synchronized. Hence, inasmuch as multiple PLLs sometimes experience different divider output edges due to different feedback clock edges even when each of the multiple PLLs is fed a given reference clock, the phases of different PLLs are thus unsynchronized.

In circuit202, the component215that includes a multiplier208replaces the conventional integrator205. In circuit202, a counter output signal104, e.g., as generated from the crystal counter110inFIG. 1, is fed to a multiplier208, which multiplies the fractional part of the FCW212with the counter output signal104. By multiplying the fractional part of the FCW212to the counter output signal104, the fractional part of the FCW212is sent to the adder210in an equivalent way as the signal from the integrator205. For example, instead of integrating the fractional part of the FCW (denoted by Δf) over time and outputting the fractional part as 2Δf, 3Δf, 4Δf, . . . , the multiplier208is configured to multiply Δf with a counter value directly, and generate an output equivalent to 2Δf, 3Δf, 4Δf, . . . . The output from the component215, e.g., the product of the fractional part of the FCW212and the counter output signal104, is then fed to a feedback circuit. Although the feedback circuit includes the quantizer206in the forward loop, but the integrator205is disposed in the negative feedback loop to integrate a feedback signal at the circuit202, in an embodiment. As the counter output signal104is also fed to the PLL as a reference clock (e.g., see104,114inFIG. 1), the multiplier208is then configured to generate an output to the SDM, e.g., the integrator205and the quantizer206, in synchronization with the reference clock of the PLL. By synchronizing the division ratio signal218with the counter output signal104, the division ratio signal218in the FCW is also in synchronization with the reference clock of the PLL.

The component215is configured to lock a stable output for the fractional part of the FCW to the adder210. Specifically, by using the counter output signal104as a clock to the fractional part of the FCW212, the multiplier output has a stable output clocked at the counter output signal104that is oblivious to other PLL transient noise or channel hopping. For example, when channel hopping occurs during a clock period of the counter output signal104, the FCW changes from FCW1to FCW2at a first time instance t1and changes back to FCW1at a second time instance t2. However, as the counter value corresponding to the counter output signal104remains the same as if FCW had not changed, when the channel changes back to FCW1, FCW1×counter value (t2) has the same phase as if the channel stays unchanged at FCW1until the second time instance t2.

Similar to circuits101and111inFIG. 1, within a circuit chip, the counter output signal104is distributed to each SDM within each PLL. For SDMs disposed on different circuit chips, each circuit chip employs a crystal counter to generate a counter output signal104, the output signal104being synchronized among circuit chips using the same reset signal (131,132inFIG. 1).

In some embodiments, the counter output signal104is configured to update at the clock301, and the SDM operates at a feedback clock (not shown inFIG. 2). When the two clock domains are different, the counter output signal104is re-sampled, via a sampler (not shown), to match the feedback clock before feeding to SDM.

FIG. 3is a block diagram illustrating an example PLL employing an SDM with a phase synchronization component as shown inFIG. 2, according to some embodiments described herein. The circuit300shows a PLL350, which can be any of the PLLs103,105,107,113,115or117inFIG. 1. Similar as described inFIG. 1, the PLL300is configured to receive a reference clock301(equivalent to the crystal clock that operates the counter output signal104inFIG. 1) from the crystal counter110. For example, the PLL300includes a phase/frequency detector (PFD)336that is configured to compare the reference clock301and a feedback clock335. The PFD336then detects the phase difference between the reference clock301and a feedback clock335and sends a signal representing the phase difference to an output oscillator321. The oscillator321is then configured to control the phase of the oscillator clock generated from the oscillator321to be fixed relative to the reference clock301.

As the oscillator321generates an oscillator clock that has a different frequency with the reference clock301, the MMDIV330is configured to divide the oscillator clock from the oscillator321to generate a feedback clock335that has a matching frequency with the reference clock301. To divide the oscillator clock from the oscillator321, the MMDIV330is configured to sample the received oscillator clock according to a division ratio signal218. For example, when the division ratio is a non-integer value, e.g., 2¼, 1¼, etc., the MMDIV330is configured to skip sampling the oscillator clock at a certain rate to approximate the fractional ratio, e.g., skipping one oscillator clock period every five sampling clock periods to approximate the division ratio of 5/4, etc. The FCW represents the division ratio between the frequency corresponding to the output signal from oscillator321and the reference clock301.

The division ratio signal218is generated in a similar manner as shown at202inFIG. 2. The fractional part212of the FCW is multiplied with the counter output signal104. In this way, the oscillator clock from the oscillator321is sampled at MMDIV330at a synchronized phase with the counter output signal104. Similarly, inFIG. 3, the fractional part of the FCW212is included as the multiplier input to be fed to the multiplier208, which is configured to multiply the FCW212with the counter output signal104. The output from the multiplier208is then fed to the quantizer206, with a feedback loop having the integrator205, as shown inFIG. 2. The output311from the quantizer206is then added to the integer part of the FCW211at the adder210, which is configured to generate the division ratio signal218for the MMDIV330.

FIG. 4is a block diagram illustrating an error correction circuit for correcting the phase error caused by dividers at the output of a PLL (e.g., as shown inFIG. 3), according to some embodiments described herein. At the circuit400, the output signal from the PLL350is further divided, and thus the integer part of the FCW and the fractional part of the FCW correspond to a division ratio between the divided output from the divider323inFIG. 4(instead of the output from the oscillator321) and the reference clock301. Thus, in an embodiment, the input213may also include a number of the least significant bits (LSBs) of the integer part211(e.g., see integer part211of the FCW inFIG. 3) of the FCW based on the number of dividers (e.g., see322,323inFIG. 4) used at the output of the PLL350, and the same LSBs of the integer part of the FCW that are included at input213are omitted from input214, which equals the integer part211of the FCW excluding the LSBs. In the example shown inFIG. 4, as two half-dividers322-323are used at the output end of the PLL350, the input213includes the fractional part of the FCW and two LSBs of the integer part of the FCW, and the input214includes integer part of the FCW excluding two LSBs.

Similar toFIG. 3, the input213is multiplied to the counter output signal104, and the product is passed through an SDM310to generate the SDM output311, e.g., at the output of the quantizer206(which is the same as the quantizer206shown inFIGS. 2-3). The SDM output311is then added to the remaining integer part of the FCW214.

An error correction block380is used to correct the error in the phase of any dividers outside the PLL350. The error correction block380is configured to receive the phase output signal316from the SDM310, and generate an error signal318, which is combined after the adder210to correct the phase of signals coming from dividers outside the PLL350.

As out_ph316is obtained from the multiplier output which is synchronized with the counter output signal104, the out_ph316is used as a phase reference to synchronize divided oscillator clock from the oscillator321. For example, two serially connected half dividers322and323are configured to divide the oscillator clock from the oscillator321to obtain the divided oscillator clock. The divided oscillator clock is then sampled by a feedback clock335by flip-flops, and then fed to a comparator320with the out_ph316. The comparator320is configured to compare corresponding samples between the phase317of the divided oscillator clock and the out_ph316. To align the comparison, a delay is applied to the signal316before the signal316is fed to the comparator320to account for the delay through the MMDIV330and the flip-flops generating the signal317. An error component318is generated by the comparator320by comparing the delayed out_ph316and the signal317sampled by the feedback clock335. The error component318thus represents the phase difference between the divided oscillator clock from the oscillator321and the counter output signal104, as the out_ph316is synchronized with the counter output signal104.

In some embodiments, the error component318experiences a similar latency (e.g., through the MMDIV330and the flip-flops generating the signal317) before the error component318has an effect on the signal317via the feedback loop. When the comparator320attempts to correct the phase difference, due to the latency, additional phase errors may occur in the PLL. To account for the latency in the error component318, the comparator320is configured to account for the last few cycles of the comparator output (e.g., the number of cycles required depends on the total latency the error component318experiences) by producing an output of zero during these few cycles, or by taking the sum of the recent comparator outputs and subtracting the sum from the current comparator output.

The adder210is configured to add the output311from the SDM310that represents the fractional part of the FCW and the LSBs of the integer part of the FCW to the remaining bits214of the integer part of the FCW211. The error component318representing the phase difference of the divided oscillator clock from the dividers322-323, is further added to the output218of the adder to generate the division ratio signal219for the PLL350(e.g., the division ratio signal219is fed to the MMDIV330within the PLL350, as shown inFIG. 3). The same feedback clock335as used at PFD336is used to obtain the phase of dividers322-323. Thus, whenever the oscillator321is not synchronized with the reference clock301, the phase difference from the oscillator321is fed through the dividers322and323into the comparator320. The oscillator phase difference is thus corrected over time by compensating the division ratio signal218with the error component318from the comparator. In this way, the oscillator321is synchronized with the counter output signal104. Once the feedback loop including the dividers322,323and the comparator320settles (e.g., at a stable state when the oscillator output is locked to the reference clock301), the error component318should be zero, and the PLL300and the dividers output phase317are also synchronized with the reference clock301.

It is noted that for illustrative purpose only, two half-dividers322,323are shown inFIG. 3, but any number N half-dividers can be used to divide the oscillator output by2N. When N half-dividers are used to divide the oscillator output, an exact number N of the LSBs of the integer part of the FCW are to be included in the input213with the fractional part of the FCW, and the N LSBs are omitted from the input214(e.g., input214include the integer part of the FCW excluding the N LSBs).

For multiple PLLs (e.g., see103,105,107inFIG. 1) with their own respective dividers in LO distribution path, as long as the SDM phase is controlled by the same counter output signal104, the oscillator phase and dividers phase are then all synchronized to the reference clock301.

FIG. 5is a logic flow diagram illustrating an example process500of phase synchronization in LO paths implemented by the example circuit as illustrated inFIG. 1, according to some embodiments described herein. At501, a first counter output signal (e.g., see104inFIG. 1) is generated at a first counter (e.g., see110inFIG. 1) disposed on a first circuit (e.g., see101inFIG. 1), in response to a first clock signal (e.g., see102inFIG. 1) controlling the first counter. At502, the first counter output signal (e.g., see104inFIG. 1) is received at a first phase-locked loop (e.g., see103inFIG. 1) disposed on the first circuit (e.g., see101inFIG. 1) as a first synchronization clock. At503, a first output signal (e.g., generated from PLL103inFIG. 1) having rising edges aligned according to the first counter output signal (e.g., see104inFIG. 1) is generated. At504, the first counter output signal (e.g., see104inFIG. 1) is received at a second phase-locked loop (e.g., see105inFIG. 1) disposed on the first circuit (e.g., see101inFIG. 1) as a second synchronization clock. At505, a second output signal (e.g., generated from PLL105inFIG. 1) having rising edges aligned according to the first counter output signal (e.g., see104inFIG. 1) is generated.

FIG. 6is a logic flow diagram illustrating an example process600of operating an SDM with phase synchronization implemented by the example circuits illustrated inFIGS. 2-4, according to some embodiments described herein. At601, an oscillator clock is generated at an oscillator (e.g., see321inFIG. 3) disposed within the first phase-locked loop (e.g., see300inFIG. 3). At602, the oscillator clock is divided dividing at a multi-modulus divider (e.g., see330inFIG. 3) by a non-integer value (e.g., see division ratio318inFIG. 3) to match a reference frequency (e.g., see301inFIG. 3). At603, both the integer part and the fractional part of the frequency control word (e.g., see213inFIG. 3) are multiplied at the multiplier (e.g., see208inFIG. 3) with the counter value corresponding to the first counter output signal (e.g., see104inFIG. 3) to generate a sigma-delta modulator output (e.g., see311inFIG. 3). At604, the oscillator clock signal is divided via one or more serially connected half-dividers (e.g., see322,323inFIG. 3). At605, a phase corresponding to the serially divided oscillator clock signal (e.g., see317inFIG. 3) is compared, via a comparator (e.g., see320inFIG. 3), with a phase (e.g., see316inFIG. 3) corresponding to the sigma-delta modulator output (e.g., see311inFIG. 3) to generate an error component (e.g., see318inFIG. 3). At606, the integer part of the FCW (e.g., see211inFIG. 3) is added, via the adder (e.g., see210inFIG. 3), to the sigma-delta modulator output (e.g., see311inFIG. 3) and the error component (e.g., see318inFIG. 3) to generate the division ratio (e.g., see218inFIG. 3) for the multi-modulus divider (e.g., see330inFIG. 3). At607, the generated sum as a division ratio (e.g., see218inFIG. 3) is sent to the multi-modulus divider (e.g., see330inFIG. 3).

Various embodiments discussed in conjunction withFIGS. 1-6are performed by various electronic components of one or more electronic circuits, such as but not limited to an integrated circuit, DSP, and/or the like. Various components discussed throughout this disclosure such as, but not limited to latches (e.g.,101,102inFIG. 1), XOR gates (e.g.,124inFIG. 1, 224in FIS. 2), and/or the like, are configured to include a set of electronic circuit components, and communicatively operate on one or more electronic circuits. Various electronic circuits discussed herein are configured to include any of, but not limited to logic gates, memory cells, amplifiers, filters, and/or the like. Various embodiments and components disclosed herein are configured to be at least partially operated and/or implemented by processor-executable instructions stored on one or more transitory or non-transitory processor-readable media.

While various embodiments of the present disclosure have been shown and described herein, such embodiments are provided by way of example only. Numerous variations, changes, and substitutions relating to embodiments described herein are applicable without departing from the disclosure. It is noted that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. It is intended for the following claims to define the scope of the disclosure and that methods and structures within the scope of these claims and their equivalents are to be covered thereby.

While operations are depicted in the drawings in a particular order, this is not to be construed as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve the desirable results.

The subject matter of this specification has been described in terms of particular aspects including components, functionalities and operations, but other aspects including components, functionalities and operations can be implemented and are within the scope of the following claims. For example, the operations recited in the claims can be performed in a different order and still achieve desirable results. As one example, the process depicted inFIG. 6does not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous. Other variations are within the scope of the following claims.