Device fabrication

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

FIELD

The present invention relates generally to semiconductor and memory fabrication. More specifically, bifurcated device fabrication flows and models are described.

BACKGROUND

Conventional solutions for fabricating semiconductor and integrated circuit devices have a substantial and direct effect on the cost of production and indirect effects on the potential revenue generated from the sale of commercial electronic products. However, conventional solutions are inefficient and do not account for product development trends. Typically, fabrication facilities do not optimize initial capital investment in tooling, machinery and equipment due to the rapidly advancing development in semiconductor technology. In other words, conventional solutions typically require large expenditures for capital investment in equipment used to fabricate semiconductor devices, which often becomes obsolete before the equipment has been fully depreciated, resulting in the loss of potential utilization. This trend with conventional solutions typically occurs due to the rapid rate of change in technological innovation in semiconductor-related technologies, particularly the reduction in size of semiconductor feature sizes and the ability to place a larger number of semiconductor devices such as transistors in a smaller area. Cost and time inefficiencies in conventional semiconductor development process typically result in overall industry cost increases due to relatively short usage of expensive equipment that is typically taken out of use before being fully depreciated.

Semiconductor device research and development is at the cutting edge of technology. The rapid rate of growth and development within the industry requires manufacturers to continuously update and modernize their tooling, machinery and equipment in order to remain competitive with other semiconductor manufacturers. However, non-fully depreciated equipment may be taken off line before being fully utilized (i.e., fully-depreciated) and set aside or often sold to other manufacturers at discounted prices resulting in substantial loss. These losses are typically accepted since the revenue generating potential of new semiconductor devices typically outweighs the loss of removing older equipment from service. The significant time and capital required to establish and maintain a modern fabrication facility typically contributes to the higher costs of semiconductor devices initially. As the equipment is removed from service, semiconductor device prices typically fall as semiconductor equipment is sold to second-line manufacturers. Yet costs are still relatively high for conventional semiconductor device manufacturers due to typical process allocation of semiconductor fabrication.

Conventional solutions for semiconductor device fabrication typically involve a single fabrication facility performing a range of processes, including conventional front-end-of-the-line (i.e., FEOL) fabrication processes and conventional back-end-of-the-line (i.e., BEOL) fabrication processes. As one example, conventional FEOL fabrication can include all processing steps necessary to fabricate a functional die including CMOS circuitry fabricated on the die (e.g., a die on a semiconductor substrate such as a silicon wafer) and in some applications memory fabricated on the same die as the CMOS circuitry. Whereas, conventional BEOL fabrication can include metallization steps to form pads for solder bumps, cutting (e.g., singulating) die from FEOL wafers and placing individual die in a package and electrically connecting pads on the die with bonding pads on the package, or attaching solder bumps to an array of pads on the die in preparation for attaching the die with a flip-chip package. The BEOL fabrication can also include soldering the die to the flip-chip package and encapsulating the die. However, the cost of tooling a fabrication facility to perform both conventional FEOL and conventional BEOL processes is expensive. Further, the costs of tooling for performance of BEOL processes is substantially more expensive than FEOL processes, the latter of which typically involves the fabrication of base complementary metal oxide semiconductor (CMOS) wafers. As the technology for BEOL processes advances with new innovations in semiconductor device technologies such as memory, processors, and the like, costs associated with tooling to meet fabrication demands are typically high and increasing, particularly if BEOL processes are being performed for a number of individually developed technologies such as integrated circuits for memory, processing, graphics processing/acceleration, or other functions. However, conventional FEOL and BEOL solutions are expensive to use when developing new memory technologies since unique tooling and equipment are required for the fabrication of the memory elements of a semiconductor device. In other conventional solutions, when a company considers entering the industry of semiconductor fabrication, the startup costs associated with purchasing equipment to perform conventional FEOL and BEOL processes are prohibitively expensive, requiring substantial startup investment costs. Although some conventional solutions may generalize the formation of devices on a silicon or other type of substrate, the interconnecting wiring, metal, or other layers deposited during the BEOL processes are typically different for each “fabless” semiconductor organization (i.e., company) that has developed a specialized application for the products resulting from the FEOL processes. Regardless of whether these companies intend to focus on the development of products resulting from BEOL processes, investment must still be made in equipment in order to form the necessary base CMOS wafers associated with FEOL processes. In other words, advancements in technology are generally associated only with the back end of the line BEOL processes. Front end of the line FEOL processes, such as forming circuitry on a substrate are standardized. However, conventional fabrication methods do not allow one facility to invest in just FEOL techniques or just BEOL techniques. Conventional methods require investment in tooling, equipment and machinery necessary to effectively manufacture a semiconductor device.

There are continuing efforts to improve non-volatile memory fabrication technology, processes, and business models.

Although the above-described drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the drawings are not necessarily to scale.

DETAILED DESCRIPTION

A detailed description of one or more examples is provided below along with accompanying figures. The detailed description is provided in connection with such examples, but is not limited to any particular example. The scope is limited only by the claims, and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided as examples and the described techniques may be practiced according to the claims without some or all of the accompanying details. For clarity, technical material that is known in the technical fields related to the examples has not been described in detail to avoid unnecessarily obscuring the description. The described fabrication techniques may be varied and are not limited to the examples provided.

FIG. 1Adepicts an exemplary device fabrication system. Here, system100is shown with fabricator102, transport104, fabricator106, device110and device112. In some examples, the term “fabricator” may refer to a semiconductor fabrication or manufacturing facility, plant, foundry, or the like. As shown here, fabricator102may perform one or more front-end-of-the-line (i.e., FEOL) processes to form base CMOS wafers including, in some examples, a minimum number of transistors and interconnects for logic formed during the FEOL processes using equipment, machinery or tools to form device110. For example, device110can comprise a silicon wafer including a plurality of die with each die including CMOS circuitry fabricated FEOL on the die. The FEOL processing comprises only a portion of the total processing on the die necessary to form a completed integrated circuit (IC). Upon completion of the FEOL processing, each die will undergo additional back-end-of-the-line processing to fabricate one or more layers of memory on each die. Once completed, in some examples, products resulting from FEOL processes (e.g., base CMOS wafers, or other products such as device110) may be transported via transport104to another facility (i.e., fabricator106) for performing the back-end-of-the-line (i.e., BEOL) processes to produce (i.e., fabricate, manufacture, form, or otherwise make) device112. For example, device112can comprise the silicon wafer of device110after the BEOL processing has been performed on the wafer such that each die on the wafer for the device112includes the CMOS circuitry fabricated FEOL by fabricator102and one or more layers of memory fabricated BEOL above the CMOS circuitry. Accordingly, each die at the completion of the BEOL processing is a unitary structure that includes a substrate (e.g., a silicon die) with CMOS circuitry FEOL fabricated thereon and one or more layers of memory vertically fabricated BEOL over the CMOS circuitry. In some examples, transport104may represent any type of transportation mechanism, mode, or vehicle, including air, sea, and land transport, including the use of aircraft, cargo ships, and transportation fleet vehicles, respectively. Transport can also represent the movement of the device110from one section of a manufacturing facility where the FEOL processing occurs to another section of the same manufacturing facility where the BEOL processing occurs.

In some examples, fabricator106may perform one or more BEOL processes using equipment, machinery or tools to transform device110into device112. In some examples, FEOL processes performed by fabricator102may include forming a substrate, patterning a circuit, depositing metal layers, testing, or depositing a shield layer and may be performed by techniques such as oxidation, photolithography, etching, ion implantation, metallization or others. As an example, the use of older fabrication equipment to fabricate, manufacture, or otherwise form (i.e., make) base wafers may be implemented to enable lower fabrication costs. In some examples, “older” equipment may refer to any and all types of semiconductor fabrication equipment that has been depreciated more than other equipment used by the same fabrication facility, plant, foundry, or the like. Alternatively, in other examples, “older” equipment may also refer to semiconductor fabrication equipment that is configured to produce or fabricate semiconductor chips with a feature size that is equal to or greater than another type of semiconductor chip that is being manufactured by the same fabrication facility, plant, foundry, or the like. That is, the “older” equipment is configured to fabricate semiconductor chips with larger feature sizes (e.g., 90 nm) than other “newer” equipment configured to fabricate semiconductor chips with smaller feature sizes (e.g., 45 nm) than the “older” equipment. Moreover, fabricator102may perform post fabrication processes on device110prior to transport104including but not limited to testing (e.g., using automatic testing equipment—ATE) finished FEOL wafers for good functional die on the wafer using electrical tests, test vectors, and the like, and identify die on the wafer that either passed or failed the testing procedures. Fabricator102may contract out to a third party some of the above mentioned processes.

In some examples, BEOL processes performed by fabricator106may include but are not limited to scrubbing a shield layer, patterning a circuit, depositing metal layers, testing, and forming connections and may be performed by techniques such as oxidation, photolithography, etching, ion implantation, metallization or others. In other examples, the quantity, type, function, capabilities, and other aspects of the elements shown in system100may be varied and are not limited to any examples shown or described. Other examples of BEOL processes performed by fabricator106may include but are not limited to testing (e.g., using ATE) finished die on a wafer for functionality, electrical parameters, etc., yield and the like, singulating the wafer to form individual die (e.g., good die from testing), packaging the die to form integrated circuit devices, and testing the integrated circuit devices. Fabricator106may contract out to a third party some of the above mentioned processes. As described above, the finished die comprises the FEOL CMOS circuitry portion and the BEOL memory portion. Unlike conventional multi-chip module technology or other technologies where a first die is electrically coupled with a second die using solder bumps, wire bonding, or the like, the finished die from the BEOL processing is a structure that is a unitary whole because the memory layers of the BEOL memory portion are grown directly on top of the FEOL CMOS circuitry portion using microelectronics fabrication processes including but not limited to thin-film deposition, chemical mechanical polishing, ion implantation, plasma etching, physical deposition, and photolithography, just to name a few.

As shown here, device112may be the product or resultant semiconductor device fabricated by system100and may include a two-terminal, three-terminal or multi-terminal semiconductor device such as a diode, transistor, memory device, microprocessor, or the like, formed FEOL. In other examples, system100may be implemented to fabricate, manufacture, construct, produce or create a different semiconductor device FEOL and is not limited to the examples shown and described.

As shown here, device110may constitute a portion of a semiconductor device (e.g., device112). In some examples, device110may be the result of FEOL processes being performed by fabricator102. For example, after completion of one or more FEOL processes, device110may comprise a base wafer. As another example, device110may comprise a substrate, one or more interconnects (e.g., for connection or coupling to logic (not shown)), and a decoder. As yet another example, device110may comprise a base CMOS wafer (e.g., a 300 mm silicon Si wafer) having underlying circuitry and drivers patterned for deposition of other materials or formation of devices during the performance of subsequent BEOL processes. In some examples, the base wafer may include a substrate.

As shown here, system100includes transport104, which as an example, may represent a physical transfer or re-location of device110from fabricator102to fabricator106(i.e., from one fabrication facility to another fabrication facility). In some examples, transport104may be accomplished by any mechanical or non-mechanical means of moving, shipping, hauling, carrying, delivering, conveying or otherwise transporting. In other examples, transport104may be by automobile, airplane, boat, railroad, conveyor belt or other means of motorized transportation. In other examples, transport104may be by non-motorized transportation. In yet other examples, transport104may be over long or short distances, without limitation. For example, a foundry based in a series of buildings may have a fabrication facility configured to perform FEOL processes in one building and another fabrication facility located in another building in close proximity to the former to perform BEOL processes. In still other examples, different fabrication facilities may be based within a given building and transport104may also include shipment via short-distance implementations (e.g., manual, conveyor belt, robotic or motorized transport or transfer, and others). Transport104may also include transfer, shipment, or travel over any distance, whether relatively long or short. As an example, device110may be assembled and packaged (e.g., placed in a suitable shipping container) at fabricator102. Thereafter, packaged device110may be placed into a truck or airplane and shipped, moved, delivered, transferred, or otherwise transported to fabricator106. As examples, fabricator102and fabricator106may be located on the same or different street, locale, city, state, country, or other geographic region. For example, fabricator102may be in California and fabricator106may be in New York. In other examples, transportation utilized for transport104and the distance traveled during transport104may vary and are not limited to the examples provided.

As shown here, system100may include a first fabrication facility (e.g., fabricator102) and a second fabrication facility (e.g., fabricator106). In other examples, system100may include any number of fabrication facilities, and is not limited to the quantities as shown or described. Here, fabricator102and fabricator106may be related or unrelated business entities. In other words, fabricator102and fabricator106may be operated by the same or different business entities or organizations. For example, fabricator102may be a wholly owned or a partially owned subsidiary company of fabricator106. In some examples, fabricator102and fabricator106may be located in the same physical geographic location (i.e., in the same building, same building complex, adjacent buildings, contiguous buildings or the like). In still other examples, fabricator102and fabricator106may be located in different geographic locations (e.g., in a different building, town, state, county, country or the like). In still other examples, the business or geographic relationship between fabricator102and fabricator106or any other fabrication facility may be varied and is not limited to any of the examples provided. Moreover, either one or both of fabricators102and106may contract out portions of the fabrication processes (e.g., microelectronics processing, testing, wafer sort, assembly, packaging, wafer sawing, etc.) to third parties that may be in the same of different geographic locales.

In some examples, fabricator102, fabricator106, or any other fabrication facility may own, rent, lease or otherwise possess capital assets (e.g., equipment, tools, machinery or other capital asset) configured for fabrication or manufacture of semiconductor devices. As shown here, fabricator102may have capital assets configured to perform FEOL fabrication processes and fabricator106may have capital assets configured to perform BEOL fabrication processes. In some examples, implementation of system100may allow the capital assets used by fabricator102or fabricator106to be utilized for a life span long enough to allow for full or partial depreciation of the capital asset. As an example, fabricator102may perform FEOL processes, such as fabricating a base wafer for a semiconductor device through formation of a substrate, wherein the process utilized to form a base wafer for a semiconductor device may be based upon one or more technology standards established in the semiconductor fabrication industry, without limitation. In this example, separating FEOL processes from BEOL processes may allow for semiconductor fabrication equipment (e.g., “fabrication equipment,” “equipment,” “asset”, “capital assets”) used by fabricator102to have an extended working life span, until the capital investment costs used to acquire an asset has sufficient time to fully depreciate, thereby fully realizing the cost of the investment. Subsequently, fabless semiconductor companies and organizations can focus on developing BEOL processes as opposed to FEOL and BEOL processes, including for memory applications, which are typically technically complex and difficult to standardize between different types of memory technologies (e.g., SRAM, DRAM, SDRAM, FLASH®, volatile, non-volatile, and others), thus lowering the overall cost of developing, research, making, marketing, and selling a product (i.e., a semiconductor chip, processor, or memory). In other examples, the economic life span of assets owned, rented, leased, or otherwise possessed by fabricator102, fabricator106or any other fabrication facility, including those not shown, may vary and is not limited to the examples and descriptions provided. In other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 1Billustrates a further exemplary device fabrication system. Here, device fabrication101is shown with transport104, device120, device122, device124, device126, FEOL fabrication facility130and BEOL fabrication facility132and depicts an alternative schematic diagram of an exemplary process for fabrication, manufacture or production of semiconductor devices. Here, devices120,122,124, and126are depicted in cross-sectional view to illustrate that die fabricated at the FEOL facility130where circuitry for example is fabricated on the die, undergo a transformation resulting from subsequent processing at the BEOL facility132where additional layers of material are fabricated (e.g., grown) on each die to form one or more layers of memory on top of each die, for example. In some examples, transport104may be implemented similarly or substantially similar in function and structure to transport104as shown and described inFIG. 1A. In other examples, transport104may be implemented differently and is not limited to the examples and descriptions provided.

In some examples, FEOL fabrication facility130may be configured to perform one or more processes associated with fabricating, for example, device120or device122. As used herein, FEOL fabrication facility130and BEOL fabrication facility132may each include one or more semiconductor fabrication processes associated with FEOL circuitry or BEOL memory fabrication techniques, respectively. After completion of FEOL fabrication by facility130, device120may be transformed to device124or device122may be transformed to device126through fabrication by BEOL facility132. In other words, devices120-122are representative of different types of devices (e.g., active CMOS circuitry) resulting from one or more processes performed by FEOL fabrication facility130. Likewise, devices124-126are representative of different types of devices (e.g., two-terminal cross-point memory arrays) that may be produced by BEOL fabrication facility132. As an example, FEOL fabrication facility130may include forming a substrate, depositing metal layers, testing, depositing a shield layer, or the like. As another example, BEOL fabrication facility132may include scrubbing a shield layer, depositing metal layers, depositing one or more thin-film layers of a conductive metal oxide, depositing a very thin layer of tunnel barrier material (e.g., 50 Å or less) on top of an uppermost layer of the conductive metal oxide to form a memory element, depositing additional layers of thin-film materials to form a non-ohmic device (NOD) electrically in series with the memory element, testing, forming one or more connections to create a memory array, or the like. FEOL fabrication facility130may be performed through any semiconductor fabrication technique, such as oxidation, photolithography, etching, ion implantation, metallization or others. BEOL fabrication facility132may be performed through any semiconductor fabrication technique, such as oxidation, photolithography, etching, ion implantation, metallization or others.

In some examples, FEOL fabrication facility130may be a first fabrication facility, such as fabricator102(FIG. 1A) and BEOL fabrication facility132may be a second fabrication facility, such as fabricator106(FIG. 1A). Further, FEOL fabrication facility130may be a different fabrication facility than BEOL fabrication facility132. As an example, device120may be formed (e.g., depositing materials to create a base CMOS wafer, such as forming interconnects, decoders, transistors, or other electronic devices) at fabricator102(FIG. 1A) by implementation of FEOL fabrication facility130. Device120may be transferred to fabricator106(FIG. 1A) where fabricator106may implement BEOL fabrication facility132to form device124(e.g., depositing metal or other materials to form a third-dimensional, passive, non-volatile, two-terminal, or other type of memory array. In some examples, equipment, machinery, tools or other semiconductor fabrication apparatus may be implemented at the FEOL fabrication facility130(e.g., to form device120or device122) and/or BEOL fabrication facility132(e.g., to transform device120into device124, or transform device122into device126). In other examples, FEOL fabrication facility130and BEOL fabrication facility132may be implemented differently and are not limited to the examples or descriptions provided. In still other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 1Cillustrates an integrated circuit including memory cells disposed in a single layer or in multiple layers of memory, according to various embodiments of the invention. In this example, integrated circuit155is shown to include either multiple layers150of memory (e.g., layers152a,152b, . . .152n) or a single memory layer151(e.g., layer152) formed on a base layer154. The single memory layer151or the multiple memory layers152a,152b, . . .152nare fabricated vertically above the base layer154along the +Z axis as denoted by the +Z on the X-Y-Z axes; whereas, the base layer154and its associated circuitry are positioned below the memory layer(s) on the −Z axis. In at least some embodiments, each layer (e.g., layer152or layers152a,152b, . . .152n) of memory can be a cross point memory array180including conductive array lines182and185arranged in different directions to access re-writable memory cells181such as two-terminal memory cells. Examples of conductive array lines include X-lines conductive array lines (e.g.,182) and Y-lines conductive array lines (e.g.,185). The two-terminal memory cells181can be passive non-volatile re-writable memory devices operative to store data as a plurality of conductivity profiles that can be reversibly switched by applying a write voltage of appropriate magnitude and polarity across the two terminals of the two-terminal memory cells181(e.g., part of a data operation, such as a write operation). A first polarity and magnitude of the write voltage can be operative to program the memory cell181and a second polarity and magnitude of the write voltage can be operative to erase the memory cell181. The erase can be accomplished without having to erase an entire block of memory within the array. The write voltage can be generated by circuitry in the base layer154and electrically coupled with the X direction182and the Y direction185conductive array lines that are connected with the two-terminal memory cell181. The value of stored data in each two-terminal memory cell can be non-destructively determined by applying a read voltage across the two terminals of the memory cell (e.g., as part of a data operation, such as a read operation). The read voltage is typically lower in magnitude than the write voltage (e.g., 2V for Read and 4V for Write) in order to prevent stored data from being disturbed or corrupted by the application of the read voltage. The read voltage is operative to generate a read current in the memory cell and a magnitude of the read current is indicative of the value of stored data in the memory cell181(e.g., a magnitude of the read current is inversely proportional to the value of the conductivity profile stored in the memory cell being read). Application of the read voltage does not alter the value of data stored in the memory cell. As mentioned above, circuitry fabricated on the base layer154and positioned below the memory layer(s) is configured to perform data operations (e.g., read, write, and restore operations) on the arrays or other data storage structures (e.g., embedded non-volatile memory) positioned in the memory layer(s).

Base layer154can include a bulk semiconductor substrate (e.g., a silicon wafer) upon which memory access circuits153are fabricated and configured for performing data operations on the memory cells181in memory150or151. Base layer154may include other circuitry that may or may not be related to data operations on memory. Referring back toFIGS. 1A and 1B, base layer154and circuitry153(e.g., device110) are formed FEOL by fabricator102and/or fabrication facility130and multiple memory layers150or single memory layer151(e.g., device112) are formed BEOL on top of the base layer154by fabricator106and/or fabrication facility132. For purposes of illustration, the layer152or the layers152a,152b, . . .152nare depicted as being separate from the base layer154; however, the layer152or the layers152a,152b, . . .152nare fabricated BEOL directly on top of the FEOL base layer154such that the resulting die is a unitary whole comprising a bottommost FEOL portion (e.g., base layer154) and an upper BEOL portion (e.g., layer152or layers152a,152b, . . .152n) fabricated vertically (e.g., +Z axis) above the FEOL portion (see die173inFIGS. 8A and 8C). The vertical fabrication (i.e., growing the memory layer(s) on top of the base layer154) can include but is not limited to a variety of thin-film layer deposition techniques, such as physical deposition, chemical vapor deposition (CVD), pulsed laser deposition, atomic layer deposition (ALD), sputtering, and co-sputtering, just to name a few.

One advantage to using a passive memory device is that the memory cell does not require a transistor(s) or other active devices and therefore the memory cell and its associated array don't need to be fabricated on a substrate (e.g., a silicon wafer) along with the active devices (e.g., CMOS circuitry). Fabricating the memory layers above the base layer eliminates the need for an expensive custom memory fab in which the memory and the active circuitry that performs data operations on the memory are fabricated on the same substrate (e.g., the same silicon wafer). Accordingly, a process flow for fabricating an IC that incorporates BEOL memory layers starts the manufacturing flow in a standard CMOS logic foundry where the base wafer is fabricated using trailing-edge technology at the lowest possible cost as part of a FEOL process. Upon completion of the FEOL processing, the base wafer is transferred to a BEOL memory fab where the one or more layers of memory are fabricated directly on top of the base layer (e.g., die154) using a standard metallization process and using a leading-edge fabrication technology selected for fabricating BEOL memory layers. This bifurcated fabrication strategy (e.g., FEOL for base circuitry wafer and BEOL for memory layers) has the advantage of enabling lower base wafer cost of manufacturing by using the trailing-edge FEOL technology (e.g., 90 nm feature sizes) enabling older production lines (e.g., CMOS logic) to serve as the FEOL foundry. No new investment in FEOL processing is needed. As the BEOL fabrication technology evolves from the current leading-edge BEOL process to a more advanced BEOL process (e.g., going from 45 nm to 25 nm), then higher storage density BEOL memory devices can be fabricated BEOL using the new more advanced BEOL process while still taking advantage of the low cost and mature FEOL front end technology to fabricate the base wafer. As leading-edge FEOL processes (e.g., 45 nm feature sizes) go on-line and become the latest low cost trailing-edge processes that replaces the previous trailing-edge technology (e.g., 90 nm feature sizes), the FEOL processing can be moved to a foundry that implements the latest low cost trailing-edge processes.

Moving on toFIG. 1D, where a vertically stacked array190includes a plurality of memory layers A, B, C, and D with each memory layer including memory cells181a,181b,181c, and181d. Although only four layers are depicted, the array190can include additional layers up to an nth layer, or fewer layers than depicted. The array190includes three levels of x-direction conductive array lines182a,182b, and182c, and two levels of y-direction conductive array lines185a, and185b. The memory cells181a,181b,181c, and181dshare conductive array lines with other memory cells that are positioned above, below, or both above and below that memory cell. The conductive array lines, the memory cells, dielectric materials that electrically isolate structures in the array190(not shown), and other structures in the array190are all formed BEOL above the base layer154(not shown) as indicated by +Z on the Z-axis above the dashed line at origin0; whereas, the active circuitry for performing data operations on the array190and the interconnect structure (not shown) for electrically coupling the active circuitry with the array190(e.g., the conductive array lines) are previously formed FEOL as indicated by −Z on the Z-axis below the dashed line at origin0. Accordingly, the BEOL structure for array190is formed (e.g., grown) on top of the FEOL structure for base layer154with the order of fabrication going in a direction from −Z (i.e., FEOL) to +Z (i.e., BEOL) along the Z-axis.

Turning now toFIG. 1E, a more complete cross-sectional view of the array190and base layer154includes active circuitry153fabricated FEOL on the base layer154(e.g., along the −Z axis), and vertically staked memory layers A, B, C, and D that are fabricated BEOL above the base layer154(e.g., along the +Z axis). Active circuits192-198are configured to perform data operations (e.g., reading and writing data) on the vertically staked memory layers A, B, C, and D. Driver circuits194and195are activated to select memory cell181a″ for a data operation and driver circuits193and198are activated to select memory cell181d″ for a data operation. For purposes of explanation, other circuitry such as sense amps, decoders, voltage sources, multiplexers, and the like are not shown. A dielectric material199is operative to electrically isolate the various components of array190. Electrically conductive structures that electrically couple the active circuits192-198with the array190can be positioned in an inter-level interconnect structure (not shown) formed FEOL and including vias, conductive traces, plugs, thrus, damascene structures, and the like.

Moving now toFIG. 1F, a cross-sectional view of an alternative configuration where the conductive array lines in different memory layers are electrically isolated from one another is depicted. Array190aincludes a plurality of non-volatile memory arrays that are vertically stacked above one another (e.g., along the +Z axis) and are positioned above the base layer154that includes the active circuitry153. Array190aincludes vertically stacked memory layers A and B and may include additional memory layers up to an nth memory layer. The memory layers A, B, . . . through the nth layer can be electrically coupled with the active circuitry153in the base layer153by an inter-level interconnect structure (not shown) as was described above. Layer A includes memory cells181aand first and second conductive array lines (182a,185a), Layer B includes memory cells181band first and second conductive array lines (182b,185b), and if the nth layer is implemented, then the nth layer includes memory cells181nand first and second conductive array lines (182n,185n). Dielectric materials199(e.g., SiO2) may be used where necessary to provide electrical insulation between the memory layers of the array190a. Active circuits191-198can be configured to apply the select voltage potentials for data operations (e.g., read and write voltage potentials) to selected conductive array lines (e.g.,182a, b, . . . n,and185a, b, . . . n). Driver circuits192and195are activated to select conductive array lines182b″ and185b″ to select memory cell181b″ in layer B for a data operation (e.g., to read data from or write data to memory cell181b″).

The cross-sectional views depicted inFIGS. 1E and 1Fclearly illustrate the transformation of the FEOL processed die154that includes active circuitry fabricated on the die154to a completed die that includes one or more memory layers vertically fabricated BEOL directly on top the die154and its associated active circuitry. Therefore, the transformation from FEOL die to BEOL die results in growth of the die in the vertical direction, that is, along the +Z axis. Consequently, the BEOL processing can add additional memory layer(s) or some other structure without increasing the area dimension of the die (e.g., no increase in the X-Y dimensions of the die).

Reference is now made toFIG. 1G, where a top plan view depicts two wafers170and171. Wafer170includes a plurality of base layer die154formed individually on wafer170as part of the FEOL process. As part of the FEOL process, the base layer die154may be tested172to determine their electrical characteristics, functionality, performance grading, etc. After all FEOL processes have been completed, the wafer170is transported104for BEOL processing (e.g., adding one or more layers of memory on top of each base layer die154). Base layer die154that failed testing may be identified either visually (e.g., by marking) or electronically (e.g., in a file, database, email, etc.) and communicated to the BEOL fabricator106and/or fabrication facility132. Similarly, performance graded base layer die154(e.g., graded as to frequency and/or speed of operation) may be identified and communicated to BEOL fabricator106and/or fabrication facility132. After transport104, the BEOL process forms memory device die150or151on top of the base layer die154. The memory device die150or151may be tested174and good and/or bad die identified. Subsequently, the wafer171can be singulated178to remove die176(e.g., the die150or151precision cut or sawed from wafer171) to form individual memory device die173. The die173may subsequently be assembled into packages179to form integrated circuits for mounting to a PC board or the like, for an electrical system (not shown). Packaged memory devices may undergo additional testing to ensure functionality and yield. InFIG. 1Git is important to note that wafers170and171are not two different wafers; rather, they are the same wafer at two distinctly different stages of a bifurcated fabrication process. The wafer is denoted as170during FEOL fabrication where die154is fabricated to include the active circuitry and the wafer is denoted as171during BEOL fabrication where the memory layer(s) are grown (e.g., fabricated on top of the die154) to form the die173. The use of two reference numerals170and171, for the wafer illustrates the transformation from a partially completed FEOL die154to a completed BEOL die173.

FIG. 2Aillustrates an exemplary cross-sectional view of a front-end-of-the-line (FEOL) device for device fabrication. Here, FEOL device200is shown vertically in cross-section, and includes substrate202and layers204-206. In some examples, FEOL device200may be implemented similarly or substantially similar in function and structure to device110as shown and described inFIG. 1A. Here, FEOL device200may be a base device (e.g., base CMOS wafer) formed from FEOL processes performed, for example, by fabricator102(FIG. 1A) or fabrication facility130(FIG. 1B). Substrate202may be used to deposit one or more layers (e.g.,204-206). For example, layer204may represent interconnects that are used to couple a memory device formed from BEOL processes (not shown) to the substrate202. In another example, layer204may also represent underlying metal, drivers, decoders, device circuitry, insulators, conductors, electronic devices (e.g., transistors, diodes, capacitors, and others), or other elements beyond those described here, without limitation. Further, layer206may be deposited over layer204using any type of material, including silicon dioxide (SiO2), silicon (Si), or different materials to protect FEOL device200during transport.

In some examples, FEOL device200may be the resulting product of a first part of a semiconductor device fabrication process implemented using techniques such as those described herein. Any number of semiconductor fabrication processes may be performed to fabricate FEOL device200at a fabrication facility such as fabricator102(FIG. 1A). For example, depositing a base layer of metal, silicon, or other material on substrate202may be performed. As another example, underlying device drivers and circuitry or interconnects for coupling FEOL device200to logic or memory may also be patterned (i.e., formed) during the performance of FEOL processes. Further, after fabricator102has completed any number of FEOL processes, FEOL device200may be transported (e.g.,104), delivered, relocated or otherwise moved to another fabrication facility, such as fabricator106(FIG. 1A), to perform any number of BEOL processes. As shown here, FEOL device200may include layers202-206. As an example, layer202may be formed using silicon (Si), silicon dioxide (SiO2), or layer206may be formed using material intended to protect the underlying substrate and materials deposited during the performance of FEOL processes during transport104(FIG. 1A). In other examples, the quantity, type, function, capabilities, and other aspects of the layers shown in FEOL device200may be varied and are not limited to any examples shown or described. In other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 2Billustrates an exemplary cross-sectional view of a BEOL device. Here, a cross-sectional view of BEOL device210is shown, including FEOL layers202-206and BEOL layers212-218. In some examples, BEOL device210may be implemented similarly or substantially similar in function, pattern, layout, materials, or structure to device112as shown and described inFIG. 1A. In other examples, BEOL device210may be implemented differently and is not limited to the examples and descriptions provided. Here, layers202-206may represent layers of a semiconductor device (e.g., a memory, processor, or other type of electronic device) formed by FEOL processes, such as those described herein. Layers212-218may represent memory layers that are formed during BEOL processes. In other words, BEOL device210may be the resulting product of FEOL device200(FIG. 2A) after transport and performance of BEOL processes, as described herein, to create, form, manufacture, or otherwise fabricate a semiconductor device such as a processor chip, a memory chip, or the like. BEOL device210can include more or fewer BEOL layers than depicted inFIG. 2B.

In some examples, BEOL device210may be a cross-sectional view of a semiconductor device after both FEOL and BEOL processes have been performed (e.g., die173inFIG. 1G). As an example, the FEOL processes configured in preparation for subsequent fabrication of BEOL device210may be performed at a first fabrication facility such as fabricator102(FIG. 1A), and the BEOL processes to fabricate BEOL device210may be performed at a second fabrication facility such as fabricator106(FIG. 1A). As shown here, BEOL device210may include layers202-206, which may be similar to those formed as described above in connection withFIG. 2A.

Referring back toFIG. 2B, layer206may have been deposited during the performance of FEOL processes in order to provide a shield layer or protective layer over FEOL device200. In some examples, layer206may be “scrubbed” (i.e., removed using chemical etching or other processes) in order to expose layer204, which, once exposed, may be suitable for bonding to other materials deposited over it. In other examples, layer206may be a layer of material (e.g., a dielectric material such as an oxide) that may be used as part of a completed electronic device and, once layers212-218are formed, enable a complete or substantially complete electronic device. Here, a passive third-dimensional memory array may be deposited over layer206using BEOL processes. Thereafter, fabricator106may implement any number of BEOL processes to complete fabrication of BEOL device210. In other examples, the material, quantity, type, function, capabilities, and other aspects of the layers shown in BEOL device210may be varied and are not limited to any examples shown or described. In other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 3Aillustrates an alternative exemplary cross-sectional view of a FEOL device300. Here, FEOL device300is shown vertically in cross-section, and includes layers202-206and layer302. In some examples, FEOL device300may be implemented similarly or substantially similar in function and structure to device110as shown and described inFIG. 1A. In other examples, FEOL device300may be implemented differently and is not limited to the examples and descriptions provided.

In some examples, FEOL device300may be the first part of a semiconductor device fabricated through the implementation of one or more FEOL processes. As an example, any number of FEOL processes to fabricate FEOL device300may be performed at a fabrication facility such as fabricator102(FIG. 1A). Further, after fabricator102has completed any number of FEOL processes, FEOL device300may be transported, delivered, relocated, or otherwise moved to another fabrication facility, such as fabricator106(FIG. 1A), to complete any number of BEOL processes. As shown here, FEOL device300may include layers202-206and layer302. As an example, layers202-206and302may comprise silicon (Si), silicon dioxide (SiO2), silicon nitride (SiNx), zirconia (ZrOx), silicate glass, suitable dielectric materials, passivation materials, metal, noble metals, or any type of material, which may include shield (i.e., protective) materials intended to protect FEOL device300during transport104(FIG. 1A). In other examples, the quantity, type, function, capabilities, and other aspects of the layers shown in FEOL device300may be varied and are not limited to any examples shown or described. In other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 3Billustrates an alternative exemplary cross-sectional view of a BEOL device. Here, BEOL device310is shown vertically in cross-section, and includes layers202-206, and layer312. In some examples, BEOL device310may be implemented similarly or substantially similar in function and structure to device112as shown and described inFIG. 1A. In other examples, BEOL device310may be implemented differently and is not limited to the examples and descriptions provided.

In some examples, BEOL device310may be a semiconductor device fabricated through the implementation of one or more FEOL processes and one or more BEOL processes. As an example, FEOL processes to fabricate BEOL device310may be performed at a first fabrication facility such as fabricator102(FIG. 1A), and BEOL processes to fabricate BEOL device310may be performed at a second fabrication facility such as fabricator106(FIG. 1A). As shown here, BEOL device310may include layers202-206and layer302(FIG. 3A). As an example, as part of the BEOL processing, a shield layer fabricated FEOL (e.g., layer302inFIG. 3A) may be removed by scrubbing (e.g., using a process such as chemical mechanical planarization—CMP) to expose the surface of layer206. Thereafter, fabricator106may implement any number of BEOL processes to complete fabrication of BEOL device310. In some examples, layer206may comprise any number of metal layers with circuit interconnection. In other examples, the quantity, type, function, capabilities, and other aspects of the layers shown in BEOL device310may be varied and are not limited to any examples shown or described. In other examples, the elements shown and described may be implemented differently and are not limited to the examples or descriptions provided.

FIG. 4illustrates an exemplary process400for device fabrication. Here, at a stage402, one or more FEOL processes may be performed at a first fabrication facility to form a base wafer associated with a memory device. The base wafer including a plurality of FEOL die (e.g., partially completed die154on wafer170inFIG. 1G). Using older fabrication equipment that, for example, may fabricate feature sizes larger than those that newer fabrication equipment are capable of fabricating may be used to perform FEOL processes as described herein. By using older equipment, service lives are prolonged, full or greater depreciation of the equipment may be realized with additional revenue generation resulting from the fabrication of additional products (e.g., device301(FIG.3A)), leading to greater overall industry utilization and profit generation. In some examples, one or more FEOL processes may include forming a substrate, depositing metal layers, testing, providing a shield layer, or others, without limitation. At a stage404, the base wafer is transferred from the first fabrication facility to a second fabrication. At a stage406, one or more BEOL processes are performed at a second fabrication facility to form a memory device directly on top of die154on the FEOL base wafer (e.g., completed die173from wafer171inFIG. 1Gor die173inFIGS. 8A and 8B). The one or more BEOL processes may include scrubbing a shield layer, depositing metal layers, testing, forming one or more connections to create a memory array, or the like. Additionally, the BEOL processes can include but are not limited to singulating die from the wafer, testing die on the wafer, packaging singulated die, and testing packaged IC's. In other examples, the above-described process may be varied and is not limited to the techniques provided. The above-described process may be varied in order, function, processes, steps, or other aspects and are not limited to the examples shown and described.

FIG. 5illustrates an alternative exemplary process500for device fabrication. Here, at a stage502, a first part of a memory device may be formed at a first fabrication facility, the first part of the memory device comprising a base wafer formed by one or more FEOL processes. As one example, the first part at the stage502can include fabricating CMOS circuitry on the base layer (e.g., die154inFIG. 1G), at least a portion of the CMOS circuitry configured to perform data operations on one or more layers of memory that will be subsequently formed over each die as part of a BEOL process. At a stage504, one or more BEOL processes may be performed at a second fabrication facility to form a memory device (e.g., die173inFIGS. 1G,8A, and8B), the one or more BEOL processes comprising forming the memory device by depositing one or more memory layers on the base wafer.

FIG. 6illustrates another alternative exemplary process600for device fabrication. Here, at a stage602, one or more FEOL processes may be performed to form a base wafer (e.g., wafer170with die154inFIGS. 1G and 9), the base wafer being formed at a first fabrication facility using fully depreciated fabrication equipment. At a stage604, a memory device (e.g., wafer171with die173inFIGS. 1G,8A,8B, and9) may be formed at a second fabrication facility, the second fabrication facility performing one or more BEOL processes to form the memory device. Here, the memory device comprises a completed die (e.g., die173) that can be subsequently singulated from the wafer and packaged as was described above to form a packaged integrated circuit (IC) device (e.g.,873and883inFIGS. 8A,8D, and9).

In some applications it may be desirable to incorporate embedded non-volatile memory in an IC such as an application specific integrated circuit (ASIC), a microprocessor (μP), a digital signal processor (DSP), a microcontroller (μC), a programmable logic device such as a FPGA, or an embedded controller, for example. Typical uses for the embedded non-volatile memory include but are not limited to buffers, command buffers, page buffers, data input and/or output buffers, registers, block registers, register files, cache (e.g., L2), instruction cache and/or data cache (e.g., L1), a translation look-aside buffer (TLB) (e.g., for instructions and/or data), stack memory, program memory, data memory, integer registers, on-chip trimming, on-chip encryption keys, on-chip firmware storage, just to name a few.

Turning now toFIG. 7, a conventional implementation700of an IC that includes embedded non-volatile memory includes a system753formed on a substrate721(e.g., a silicon die) having top and bottom surfaces753tand753s. The system753can be any type of electronic device that requires embedded non-volatile memory such as a microprocessor (μP), a digital signal processor (DSP), a microcontroller (μC), a FPGA, just to name a few. Here, the embedded non-volatile memory is fabricated directly on the substrate721along with the other circuitry for system753. To add the embedded non-volatile memory the X-Y dimensions (i.e., the area) of the substrate must be increased to accommodate the silicon resources required by the embedded non-volatile memory. Moreover, the addition of the embedded non-volatile memory requires generating additional photolithographic mask layers to fabricate the embedded non-volatile memory. The increase in die size reduces the number of die that can be fabricated on a wafer and increases the cost of the resulting IC because the cost of an IC is proportional to the area of the die the IC is formed on.

Accordingly, inFIG. 7, to add the embedded non-volatile memory requires M-Extra Mask and the additional costs to fabricate each additional mask plus other costs to fabricate the embedded non-volatile memory on the substrate721. For example, as many as eight additional masks (e.g., M=8) may be required to implement the embedded non-volatile memory on substrate721. Therefore, system763inFIG. 7represents the system753after embedded non-volatile memory has been added, with system763having a larger die area and a higher manufacturing cost due to the addition of the embedded non-volatile memory as compared to system753without embedded non-volatile memory. Here, the X-Y dimensions of die723are larger than the X-Y dimensions of die721. Consequently, there are disadvantages to adding embedded non-volatile memory to the die of a system including increased die size and die cost, costs for additional mask sets, additional fabrication steps and their associated costs, and costs associated with defects in the embedded non-volatile memory that reduce the number of good die per wafer.

Moving on toFIG. 8, using the FEOL and BEOL device fabrication paradigm described herein, implementation800includes a system853having active circuitry fabricated FEOL on base layer154and the system853includes embedded non-volatile memory that is fabricated BEOL vertically above base layer154in one layer152or in multiple layers152a,152b, . . .152nlayers of memory. Unlike the conventional implementation700depicted inFIG. 7, the area of base layer154(e.g., the X-Y dimensions) is not increased by the addition of the embedded non-volatile memory because the embedded non-volatile memory is fabricated BEOL after the FEOL fabrication is completed and is positioned over the base layer154and therefore does not take up space (e.g., silicon area) on the base layer154. As an example, the system853can be a microprocessor (μP) that requires embedded non-volatile memory in the form of several different types of non-volatile registers and buffers in its architecture, such as a TLB, L1 cache, L2 cache, data buffers, command buffers, and page buffers, just to name a few. Instead of fabricating those registers and buffers on the substrate (e.g., as in system763ofFIG. 7), those non-volatile registers and buffers are fabricated BEOL and are electrically coupled with the relevant FEOL circuitry configured to perform data operations on the non-volatile registers and buffers.

In implementation800, the addition of the embedded non-volatile memory BEOL on top of the FEOL base layer154requires fewer masks than the implementation700ofFIG. 7. Here, N-Extra Masks are required to fabricate the embedded non-volatile memory BEOL, where N can be three masks (e.g., N=3). In contrast, the implementation700ofFIG. 7can require eight extra masks (e.g., M=8) to implement the embedded non-volatile memory FEOL on the substrate723. Therefore, one advantage to the BEOL implementation of embedded non-volatile memory in800is that fewer masks are required (e.g., N<<M) and the cost savings associated with using fewer masks. For example, the cost for each mask in a set of masks required to fabricate a complete state-of-the-art IC can be $100K or more per mask. Therefore, using 3 masks instead of eight eliminates five masks and can provide a significant cost savings.

Implementation800allows for great flexibility in architecting the layout of the BEOL embedded non-volatile memory in the memory layer(s). As one example, one or more portions820of non-volatile array180can be used as embedded non-volatile memory by the system853. The address space associated with the memory cells181in portion820of array180can be configured by the system853(e.g., using hardware, software, or firmware) for dedicated use as a register, buffer, or the like. As another example, the BEOL embedded non-volatile memory can be a small non-volatile array180configured to store the amount of data required by the system853. For example, if the system853operates on a 64-bit word and requires a data buffer that stores 16 words, the small non-volatile array180can be configured to be an array size of 16×64 (e.g., 16 row conductive array lines182by 64 column conductive array lines185). As yet another example, each layer of memory can be partitioned such that some portions of a layer are configured for use as non-volatile RAM storage and other portions are configured for use as embedded non-volatile memory. The embedded non-volatile memory can be of different sizes and configurations and can be disposed on a single layer of memory152or among multiple layers of memory152a,152b, . . .152n. Therefore, if the system853requires any combination of DRAM, SRAM, or FLASH for RAM data storage and also requires embedded non-volatile memory, both requirements can be met by fabricating those memories BEOL above the base layer154in one or more layers (152,152a,152b, . . .152n) of BEOL memory.

Referring again toFIG. 7, the conventional implementation700may also require any combination of DRAM, SRAM, or FLASH for RAM data storage and also require embedded non-volatile memory. However, the RAM(s) are typically fabricated as one or more separate IC's750and are mounted on the same PC board as the system763and electrically coupled using PC board traces to communicate address750aand data750bsignals and other control signals (not shown). Those RAM IC's require additional PC board space to accommodate their respective packages and PC board traces and incur additional costs due to the cost of the IC's and their packaging.

Turning now toFIG. 7A, the conventional implementation700ofFIG. 7can be depicted in cross-sectional view as conventional implementation790where system763and one or more RAM(s)750are positioned in a packages (773,783), wire bonded (775,785), mounted to a PC board771using solder balls (772,782) and electrically coupled with each other using one or more PC board traces776. Not withstanding the area taken up by their respective packages (773,783) the die721for system763and RAM(s)750have die areas of A1and A2such that implementation790requires at minimum an area on PC board771of AM=A1+A2.

Attention is now directed toFIG. 8Awhere a cross-sectional view, denoted as implementation890, illustrates how die area and PC board space can be reduced by using FEOL processing for active circuitry and BEOL processing for non-volatile memory (e.g., RAM) and/or embedded non-volatile memory. Die173is positioned in package873, wired bonded875, and mounted to a PC board871using solder balls872. Active circuitry for system853ofFIG. 8is fabricated FEOL on base layer154along the −Z axis and the non-volatile RAM(s) and/or embedded non-volatile memory are fabricated BEOL above the base layer154along the +Z axis. Area A0of die173is less than the area A1because unlike the system763ofFIG. 7A, the non-volatile memory is implemented in memory layer152and therefore does not take up area on the base layer154. Furthermore, because the non-volatile memory is implemented in memory layer152the area A2for RAM(s)750is eliminated and less PC board area is required for PC board871. PC board trace776is eliminated because electrical communication between system853and the memory(s) in layer152are accomplished using an inter-level interconnect layer that electrically couples the active circuitry in base layer154with the memory(s) in layer152.

InFIG. 8B, a top plan view depicts one example of a configuration for BEOL memory layer152. Memory layer152includes three portions or partitions: a cross-point memory array152-cpa; a first embedded non-volatile memory152em1; and a second embedded non-volatile memory152em2. Embedded non-volatile memories152em1and152em2can be configured as cross-point arrays or have an application specific configuration that is not necessarily based on cross-point array architecture. The size and layout of the memories152-cpa,152em1, and152em2will be application dependent. For example, memory152-cpacan be 64-Gigabit two-terminal cross-point memory array configured as general RAM storage for system853and/or some other system in electrical communication with system853, memory152em1can be configured as a dedicated L1 cache for system853and memory152em2can be configured as a dedicated L2 cache for system853.

In some applications it may be desirable to implement multiple layers of BEOL memory. The memory layers can include one or more embedded non-volatile memories only, non-volatile RAM only, both embedded non-volatile memory(s) and non-volatile RAM(s), or any combination of those memory types.

Reference is now made toFIG. 8Cwhere a cross-sectional view of an implementation895illustrates vertically stacked memory layers. A die173includes FEOL base layer154and three layers of BEOL memory152a,152b, and152cvertically fabricated BEOL above the base layer154along the +Z axis. Die173is positioned in package883, is wire bonded885, and is mounted to PC board881using solder balls872. Die173can have the same area A0that is less than the area A1for the same reasons as described above in reference toFIG. 8A. InFIG. 8B, the volume of die173has increased slightly due to the increase in the height of the die173in the +Z direction due to the multiple memory layers as compared to the die173ofFIG. 8Ahaving only a single memory layer.

Moving on toFIG. 8D, one example of memory partitioning among the layers152band152cand includes cross-point memory arrays for non-volatile RAM data storage denoted as152b-cpafor layer152band152c-cpafor layer152c. Layer152acan be configured as depicted inFIG. 8Awith cross-point array152-cpaand embedded non-volatile memories152em1and152em2. The actual configuration for the layers152a-cwill be application dependent and implementation895can include more or fewer layers of memory than depicted inFIG. 8Cand can include any combination of embedded non-volatile memories and non-volatile RAM disposed in the layers of memory.

Attention is now directed toFIG. 9, where the transformation of a FEOL processed wafer170to a BEOL processed wafer171is depicted. FEOL wafer170includes a plurality of the aforementioned die154. A cross-sectional view of the die154is depicted along a line FF-FF to illustrate that the base layer is formed along the −Z axis and is not a finished die until the BEOL processing has fabricated the memory layer(s) on top of the base layer154along the +Z axis. After transport104, the FEOL wafer170is transformed into wafer171by BEOL processing to form completed die173that includes one layer of memory152or multiple layers of memory152a,152b,152c. . .152n, fabricated above base layer die154along the +Z axis as depicted in cross-sectional view along a line BB-BB. Upon completion of BEOL fabrication, wafer171can undergo additional fabrication steps such as singulating178(e.g., sawing) die173from the wafer171, packaging179the singulated die173into packages (e.g.,873or883), and testing181packaged die173. The die173can also be tested for yield and/or functionality prior to being singulated from the wafer171. For example, prior to packaging179, it may be desirable to test the die173for functionality and yield of the memory layer(s) that were fabricated BEOL to determine which good functional die173to package179. In some applications, the singulating, packaging, testing, or other processes can be part of the BEOL process and those processes can be accomplished by fabricator106, fabrication facility132, or by a third party. Similarly, prior to transport104, testing or other processes can be performed by fabricator102, fabrication facility130, or a third party.

Turning now toFIG. 10, a chart1000depicts key differences and advantages for processing an IC die (e.g., die173) using FEOL fabrication1003for active circuitry and BEOL fabrication1005for one or more layers of memory. A line1001denotes a demarcation or transition point between FEOL fabrication1003and BEOL fabrication1005. As one example, line1001can comprise the transport104. Focusing first on the FEOL fabrication1003, at a1FEOL fabrication of circuitry die on a wafer (e.g. Wafer A) occurs as described above. At a2a trailing edge FEOL fabrication technology having a first investment cost (1stCost) that is very low or is negligible is used for fabricating the circuitry die. For example, the technology used for the fabrication at a1can be a mature IC fabrication process for which the 1stcost is approximately zero dollars. At a3the fabrication can be accomplished using capital assets selected based on their status as substantially depreciated capital assets (e.g., either fully depreciated or almost fully depreciation in their capital value). At a4a first cost per wafer (1stCPW) is low due in substantial part to the use of the trailing edge fabrication technology of a2and the depreciated capital assets of a3. As one example, the 1stCPW can be approximately ⅓ of a total fabrication cost or less, where the total fabrication cost can include the 1stCPW and a cost per wafer for the BEOL fabrication1005as will be described below. At a5the costs and complexity associated with using extra masks for implementing embedded non-volatile memory on the FEOL circuitry die (e.g., die154) can be avoided because fewer masks (e.g., 3 masks vs. 8 masks) are used to implement the embedded non-volatile memory as part of the BEOL fabrication1005.

Focusing now on the BEOL fabrication1005, at b1one or more memory layers are fabricated directly on top of the circuitry die of a1. At b2a second investment cost (2ndCost) in a leading edge BEOL memory fabrication technology can be substantially larger than the 1stCost of a2(e.g., 2ndCost>>1stCost). For example the 2ndCost can be several hundreds of million dollars or several billions of dollars more; whereas, the 1stCost can be approximately zero dollars or only a few million dollars. At b3the BEOL fabrication is accomplished using capital assets having substantially no depreciation (e.g., little or no depreciation in their capital value). For example, the capital assets can be recently purchased capital equipment. The recently purchased capital equipment can be purchased new or can be purchased used; however, for the purchasing entity, the capital equipment is new in the sense that it has not suffered any substantial depreciation in its capital value. At b4a second cost per wafer (2ndCPW) is high due in substantial part to the use of the leading edge fabrication technology of b2and the substantially no depreciation of capital assets of b3. As one example, the 2ndCPW can be approximately ½ of the total fabrication cost or more. At b5, if embedded non-volatile memory is to be implemented, then the aforementioned fewer masks (e.g., 3 masks) can be generated to implement the embedded non-volatile memory and because the embedded non-volatile memory is fabricated BEOL on top of the circuitry die of a1, there is no area penalty on the circuitry die itself.

The term capital assets as used herein includes any capital equipment used in the FEOL1003and/or BEOL1005fabrication and can include but is not limited to deposition equipment, lithography equipment, furnaces, wet and dry etching equipment, automatic test equipment, physical analysis equipment, failure analysis equipment, inspection equipment, wafer handling equipment, clean rooms, facilities infrastructure, robotics equipment, computers, workstations, IT infrastructure, test equipment, CAD or other software, CMP equipment, buildings, facilities, and structures used in the fabrication process, just to name a few. As an example of the differences between the capital assets for a3and b3, the capital assets for a3can be a mature technology configured for fabricating FEOL circuitry having feature sizes of 90 nm or larger and the capital assets for b3can be configured for fabricating BEOL memory layer(s) having feature sizes of 45 nm or less. The total fabrication cost may not necessarily be the sum of the 1stCost and the 2ndCPW (e.g., Total Fabrication Cost≠1stCost+2ndCPW).

FIGS. 11A and 11Bdepict two parts of a bifurcated IC fabrication process1000where a first part comprises FEOL processing1100to form a FEOL circuitry die and a second part which comprises BEOL memory layer processing1150on the FEOL circuitry die fabricated in the first part. Prior to the process1000, one skilled in the art will appreciate that system to be fabricated by the process1000will have already been architected; synthesized, simulated, artwork generated, placed and routed, mask sets generated, etc. Two separate flow diagrams are depicted to illustrate the bifurcated strategy of forming the FEOL base wafer using a trailing-edge low cost technology configured for forming active circuitry in a first fabrication facility followed by BEOL memory layer fabrication directly on top of the base wafer using a leading-edge higher cost technology configured for passive memory formation in a second fabrication facility. In some applications the first and second fabrication facilities are different facilities and/or manufacturing entities and in other applications the first and second fabrication facilities are the same facility and/or manufacturing entity.

Reference is now made toFIG. 11A, where an exemplary process1100for fabricating a FEOL circuitry die (e.g., die154) includes at a stage1101providing a trailing edge FEOL circuitry fabrication technology having a first investment cost that is very low or negligible (e.g., 1stCost in a2inFIG. 10) and the trailing edge FEOL circuitry fabrication technology is configured for fabricating the FEOL circuitry die using substantially depreciated capital assets (e.g., a3ofFIG. 10). At a stage1103, the FEOL circuitry die is fabricated on a wafer using the trailing edge FEOL circuitry fabrication technology at a first cost per wafer (e.g., 1stCPW of a4inFIG. 10). Preferably, the 1stCPW is the smallest percentage of a total fabrication cost such as approximately ⅓ of the total fabrication cost or less. At a stage1105a determination can be made as to whether or not the FEOL fabrication is completed. If FEOL fabrication is completed, then the YES branch can be taken to a stage1109, or if the FEOL fabrication is not completed, then the NO branch can be taken to a stage1107. If the NO branch is taken, then any remaining FEOL processes can be completed and the process resumes at the stage1109. Examples of processes that can be executed at the stage1107include but are not limited to testing the wafer for functional die, preparing the wafer for transport104, identifying good die and failed die, determining yield on the FEOL circuitry die, just to name a few. At the stage1109the wafer is transferred (e.g., the transport104) for subsequent fabrication one or more BEOL memory layers directly on top of each of the FEOL circuitry die. After stage1109processing of the wafer continues1102and is depicted inFIG. 11Bwhere the demarcation line1001indicates a transition from FEOL circuitry processing1100to BEOL memory layer processing1150.

Turning now toFIG. 11B, a stage1151includes providing a leading edge BEOL memory fabrication technology having a second investment cost (e.g., 2ndCost of b2inFIG. 10) that is substantially larger than the 1stCost and the leading edge BEOL memory fabrication technology is configured for fabricating one or more BEOL memory layers using capital assets having substantially no depreciation (e.g., b3ofFIG. 10). The providing at the stage1101ofFIG. 11Aand the providing at the stage1151ofFIG. 11Bcan be by the same business entity or different business entities. Furthermore, any of those business entities can enlist third parties to perform some or all of the fabrication steps depicted inFIGS. 11A and 11B.

At a stage1153a determination is made as to whether or not embedded non-volatile memory is to be implemented in one or more of the BEOL memory layers. If the NO branch is taken, then the processing continues at a stage1157. If the YES branch is taken, then at a stage1155one or more of the BEOL memory layers is configured to include one or more embedded non-volatile memories. The configuration at the stage1155can include generating the mask sets (e.g., N-Extra Masks inFIG. 8) necessary for implementing the embedded non-volatile memories. In that the BEOL memory layers may be any combination of memory types such as cross-point array only, embedded non-volatile memory only, or both embedded non-volatile memories and cross-point array, the necessary masks for any of those combinations can be generated as part of the stage1155or prior to the state1155. For example, in a BEOL memory configuration in which there are four layers of BEOL memory, a first BEOL memory layer can be configured to include three embedded non-volatile memories and two cross-point memory arrays, a second BEOL memory layer can be configured to include five embedded non-volatile memories and one cross-point memory array, a third BEOL memory layer can be configured to include a single cross-point memory array, and a fourth BEOL memory layer can be configured to include a single cross-point memory array. The first through fourth BEOL memory layers are vertically stacked one upon the other. The embedded non-volatile memories can be placed in the lower two layers (i.e., the first and second layers) so that they are closer to the FEOL circuitry in the base layer (e.g., layer154) thereby reducing the length of routed interconnect lines from the base layer to the first and second layers with a concomitant reduction in propagation delays for signals communicated along the routed interconnect lines. The cross-point memory arrays in the layers can be configured to emulated different types of RAM, such a SRAM in the first layer, FLASH in the second layer, and DRAM in the third and fourth layers.

At a stage1157, the one or more BEOL memory layers are fabricated directly on top of each FEOL circuitry die using the leading edge BEOL memory fabrication technology and at a second cost per wafer (e.g., 2ndCPW of b4inFIG. 10). In that the capital assets used for the leading edge BEOL memory fabrication technology have substantially no depreciation, the 2ndCPW can be a greater percentage of the total fabrication cost and can be approximately ½ the total fabrication cost or more.

At a stage1159a determination is made as to whether or not BEOL fabrication is complete. If the NO branch is taken, then at a stage1161, any remaining BEOL processes are completed and upon completion processing continues at a stage1163. If the YES branch is taken, then the processing continues at the stage1163where a determination is made as to whether or not any post BEOL processing is required. If the NO branch is taken, then processing terminates. If the YES branch is taken, then post BEOL processing continues at1104. As one example, if BEOL processing1150is completed, whole wafers can be shipped to a customer or sold to a purchasing party. The party receiving the wafers can perform some function not entrusted to the BEOL fabricator106and/or fabrication facility132, such as testing the wafer for good die173, singulating die173from the wafer, packaging good die179, and testing packaged die181(seeFIG. 9). In some applications, the BEOL fabricator106and/or fabrication facility132will perform the aforementioned processes and the NO branch at the stage1163will be taken because those processes are part of the BEOL process1150and are not post BEOL processes1104.

The processing1100and1150allows for great flexibility in meeting the 1stCost, 1stCPW, 2ndCost, and 2ndCPW. For example, fabricator102and/or fabrication facility130can send FEOL wafers to third parties whose fabrication technology and CPW meet the requirements of stages1101and1103. For example, a third party can have deposition equipment that is more fully depreciated than that of fabricator102and/or fabrication facility130so that it makes prudent financial sense to send FEOL wafers to the third party for some or all of the FEOL depositions steps in order to contain fabrication costs within the goals for the 1stCost and the 1stCPW. As another example, BEOL fabricator106and/or fabrication facility132may lack one or more pieces of leading edge BEOL memory fabrication equipment necessary to complete the BEOL process1150(e.g., a plasma etching system) and one or more third party fabricators have the need equipment. Consequently, BEOL fabricator106and/or fabrication facility132contracts out that portion of the process1150to the third party (e.g., to perform the plasma etching portion of the process1150).

The flexibility in structuring the costs for the FEOL processing and the BEOL processing also allows those costs to be apportioned according to the needs of the manufacturing entities. As one example, because the leading-edge BEOL fabrication technology can be considerably more expensive than the FEOL fabrication technology, a cost differential between the FEOL costs and the BEOL costs can be capped at a predetermined level, such as in a range of from about 30% to about 50%. Therefore, the manufacturing entity or entities can structure the cost differential such that the extra or additional cost for the BEOL technology is no greater than 30% more of the FEOL costs.

The foregoing description, for purposes of explanation, uses specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the present invention to any embodiment; rather features and aspects of one embodiment can readily be interchanged with other embodiments. Notably, not every benefit described herein need be realized by each embodiment of the present invention; rather any specific embodiment can provide one or more of the advantages discussed above. In the claims, elements and/or operations do not imply any particular order of operation, unless explicitly stated in the claims. It is intended that the following claims and their equivalents define the scope of the invention.