Semiconductor device

Semiconductor device including semiconductor layer, first impurity region on surface layer portion of semiconductor layer, body region at interval from first impurity region, second impurity region on surface layer portion of body region, field insulating film at interval from second impurity region, gate insulating film on surface of the semiconductor layer between second impurity region and field insulating film, gate electrode on gate insulating film, first floating plate as ring on field insulating film, and second floating plate as ring on same layer above first floating plate. First and second floating plates formed by at least three plates so that peripheral lengths at centers in width direction thereof are entirely different from one another, alternately arranged in plan view so that one having relatively smaller peripheral length is stored in inner region of one having relatively larger peripheral length, and formed to satisfy relational expression: L/d=constant.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device.

2. Description of Related Art

In general, an LDMOSFET is known as a high withstand voltage device employed for a power MOSFET.

FIG. 10is a schematic sectional view of a semiconductor device including a conventional LDMOSFET.

A semiconductor device101includes a thick-film SOI substrate102. The thick-film SOI substrate102has a structure obtained by laminating an N−-type active layer105made of silicon on a silicon substrate103through a BOX layer104made of silicon oxide.

In the active layer105, a deep trench106having a depth reaching the BOX layer104from the surface thereof is formed to pass through the active layer105in the thickness direction. The inner side surface of the deep trench106is covered with a silicon oxide film107.

The inner side of the silicon oxide film107is filled up with polysilicon108. Thus, an element forming region109surrounded by the deep trench106and dielectrically isolated from the periphery thereof by the BOX layer104and the silicon oxide film107is formed on the active layer105.

An LDMOSFET110is formed in the element forming region109. More specifically, a P-type body region111is formed in the active layer105in the element forming region109. The body region111is formed along the side surface of the deep trench106over the entire thickness of the active layer105.

The region of the element forming region109other than the body region111is an N−-type drift region112.

On a surface layer portion of the body region111, an N+-type source region113and a P+-type body contact region114are formed to be adjacent to each other on positions separated from the drift region112. On a surface layer portion of the drift region112, an N+-type drain region115is formed on a position separated from the body region111.

On the surface of the drift region112, a field oxide film116is formed on a portion between the drain region115and the body region111at an interval from the body region111.

Between the source region113and the field oxide film116, a gate oxide film117is formed on the surface of the active layer105. A gate electrode plate118is formed on the gate oxide film117. The gate electrode plate118is opposed to the body region111and the drift region112through the gate oxide film117.

On the field oxide film116, a field plate119integral with the gate electrode plate118is formed to extend onto the peripheral edge portion of the field oxide film116.

Four first floating plates120are formed on the field oxide film116. The four first floating plates120are in the form of rings, having a constant width, similar to one another. The four first floating plates120are arranged to form a quadruple ring surrounding a drain electrode plate122(described later) connected to the drain region115and to divide the space between the drain electrode plate122and the field plate119at regular intervals. The first floating plates120are opposed to the drift region112through the field oxide film116.

A source electrode plate121extending over the source region113and the body contact region114is formed on the body region111. The source electrode plate121is connected to the source region113and the body contact region114.

The drain electrode plate122is formed on the drain region115. The drain electrode plate122is connected to the drain region115.

The upper portion of the thick-film SOI substrate102is covered with a first interlayer dielectric film123made of silicon oxide.

Five second floating plates124are formed on the first interlayer dielectric film123. The second floating plates124are in the form of rings, having a constant width, similar to the first floating plates120. The five second floating plates124are dividedly arranged one by one on a central portion between the drain electrode plate122and the first floating plate120adjacent thereto, central portions between the adjacent ones of the first floating plates120, and a central portion between the field plate119and the first floating plate120adjacent thereto respectively. In other words, the five second floating plates124are arranged at regular intervals while the second floating plates124and the first floating plates120are alternately arranged in plan view between the drain electrode plate122and the field plate119.

The upper portion of the first interlayer dielectric film123is covered with a second interlayer dielectric film125made of silicon oxide.

A source contact hole126facing the source electrode plate121is formed in the first interlayer dielectric film123and the second interlayer dielectric film125to pass through the same. Further, a drain contact hole127facing the drain electrode plate122is formed in the first interlayer dielectric film123and the second interlayer dielectric film125to pass through the same.

A source wire128and a drain wire129are formed on the second interlayer dielectric film125. The source wire128is connected to the source electrode plate121through a source contact plug130embedded in the source contact hole126. The drain wire129is connected to the drain electrode plate122through a drain contact plug131embedded in the drain contact hole127.

A current can be fed between the source region113and the drain region115(between a source and a drain) through the drift region112by grounding the source wire128and controlling the potential of the gate electrode plate118while applying a positive-polarity voltage (a drain voltage) to the drain wire129thereby forming a channel in the vicinity of the interface between the body region111and the gate oxide film117.

SUMMARY OF THE INVENTION

In a high withstand voltage device represented by the LDMOSFET, a high voltage is applied between a source and a drain, and hence a countermeasure for ensuring the withstand voltage is required.

As such a countermeasure, the four annular first floating plates120similar to one another are provided on the field oxide film116in the semiconductor device101. Further, the five annular second floating plates124similar to one another are provided on the first interlayer dielectric film123. Thus,10capacitors having counter electrodes defined by the drain electrode plate122and the field plate119as well as the second floating plates124and the first floating plates120alternately arranged therebetween in plan view between the plates adjacent to one another are formed in operation of the LDMOSFET110(voltage application to the drain wire129).

The second floating plates124and the first floating plates120are alternately arranged at regular intervals between the drain electrode plate122and the field plate119, whereby the capacitances of all capacitors are equalized with one another. Thus, a uniform electric field is formed between the counter electrodes of each capacitor, and the potential distribution in the drift region112is uniformized due to the influence by the electric field. The potential distribution is so uniformized that local field concentration between the source and the drain can be canceled, whereby the withstand voltage of the device can be expectedly improved.

However, the four first floating plates120are different in size from one another, and the five second floating plates124are also different in size from one another. In the aforementioned structure, therefore, the total capacitances of the capacitors cannot be equalized with one another although the capacitances per unit length in the peripheral direction of each floating plate can be equalized with one another in all capacitors. Consequently, the electric field between the counter electrodes of each capacitor not uniformized in practice, and the potential distribution in the drift region112cannot be uniformized.

An object of the present invention is to provide a semiconductor device capable of uniformizing potential distribution between a first impurity region and a second impurity region (between a source and a drain, for example).

The foregoing and other objects, features and effects of the present invention will become more apparent from the following detailed description of the embodiments with reference to the attached drawings.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer made of a first conductivity type semiconductor material; a first conductivity type first impurity region, formed on a surface layer portion of the semiconductor layer, having an impurity concentration higher than the impurity concentration in the semiconductor layer; a second conductivity type body region formed on the surface layer portion of the semiconductor layer at an interval from the first impurity region; a first conductivity type second impurity region, formed on a surface layer portion of the body region, having an impurity concentration higher than the impurity concentration in the semiconductor layer; a field insulating film formed on a portion of the surface of the semiconductor layer between the first impurity region and the second impurity region at an interval from the second impurity region; a gate insulating film formed on the surface of the semiconductor layer between the second impurity region and the field insulating film; a gate electrode formed on the gate insulating film; a first floating plate provided in the form of a ring having a constant width on the field insulating film; and a second floating plate provided in the form of a ring having a constant width on the same layer above the first floating plate, wherein the first floating plate and the second floating plate are formed by not less than three in total so that the peripheral lengths at the centers in the width direction thereof are entirely different from one another, alternately arranged in plan view so that the one having a relatively smaller peripheral length is stored in an inner region of the one having a relatively larger peripheral length, and formed to satisfy the relational expression: L/d=constant (L: the outer periphery of the inner one of the first and second floating plates adjacent to each other in plan view, d: the distance between the outer periphery of the plate defining L and the inner periphery of the first or second floating plate adjacent to the plate to be opposed to the outer periphery thereof).

According to the structure, the second conductivity type body region and the first conductivity type first impurity region having the impurity concentration higher than the impurity concentration in the semiconductor layer are formed on the surface layer portion of the semiconductor layer at an interval from each other. The first conductivity type second impurity region having the impurity concentration higher than the impurity concentration in the semiconductor layer is formed on the surface layer portion of the body region. Further, the field insulating film is formed on the portion of the surface of the semiconductor layer between the first impurity region and the second impurity region at an interval from the second impurity region. The gate insulating film is formed on the surface of the semiconductor layer between the second impurity region and the field insulating film, and the gate electrode is formed on the gate insulating film.

A current can be fed between the second impurity region and the first impurity region (between the first impurity region and the second impurity region) through a portion of the semiconductor layer between the body region and the first impurity region by grounding the second impurity region and controlling the potential of the gate electrode while applying a positive-polarity voltage to the first impurity region thereby forming a channel in the vicinity of the interface between the body region and the gate insulating film, for example.

In the semiconductor device, the first floating plate in the form of a ring having a constant width is formed on the field insulating film. Further, the second floating plate in the form of a ring having a constant width is formed on the same layer above the first floating plate. The first floating plate and the second floating plate are formed by not less than three in total, so that the peripheral lengths at the centers in the width direction thereof are entirely different from one another.

The first floating plate and the second floating plate are alternately arranged in plan view so that the one having a relatively smaller peripheral length is stored in an inner region of the one having a relatively larger peripheral length. Thus, at least two capacitors having counter electrodes defined by the first and second floating plates adjacent to each other in plan view are formed on the field insulating film.

If an electric field generated between the counter electrodes of each capacitor formed on the field insulating film is uniform, the potential distribution in a portion of the semiconductor layer located under the counter electrodes can be uniformized.

In the semiconductor device, therefore, the first floating plate and the second floating plate are formed to satisfy L/d=constant, where L and d are defined as follows:

L: the outer periphery of the inner one of the first and second floating plates adjacent to each other in plan view

d: the distance between the outer periphery of the plate defining L and the inner periphery of the first or second floating plate adjacent to the plate to be opposed to the outer periphery thereof

The total capacitance C of each capacitor formed on the field insulating film is the sum of the capacitanceC=∈·S/d per small sectionL of the outer periphery L of the inner plate in each capacitor (S: a small area of the outer peripheral surface of the inner plate perL), and expressed as C=∈·S/d.S expressing the area of the outer peripheral surface of the inner plate perL is proportionate toL, and hence S expressing the sum ofS is proportionate to L expressing the sum ofL.

Based on the condition where the first floating plate and the second floating plate satisfy L/d=constant, therefore, S/d=constant is deduced. In the plurality of capacitors having the counter electrodes defined by the first and second floating plates having entirely different peripheral lengths, therefore, the total capacitances can be entirely equalized with one another.

Consequently, an electric field generated between the counter electrodes of each capacitor can be uniformized, whereby the potential distribution between the first impurity region and the second impurity region can be uniformized, and the withstand voltage can be improved.

In the semiconductor device, the width of the first floating plate having a relatively larger peripheral length may be smaller than the width of the first floating plate having a relatively smaller peripheral length.

According to the structure, the width of the first floating plate having a relatively larger peripheral length is smaller than the width of the first floating plate having a relatively smaller peripheral length.

Thus, the distance between the outer periphery of the second floating plate arranged therebetween in plan view and the inner periphery of the first floating plate having a relatively larger peripheral length (i.e., the value d in the above relational expression) can be rendered greater than the distance between the outer periphery of the first floating plate having a relatively smaller peripheral length and the inner periphery of the second floating plate (i.e., the value d in the above relational expression). Therefore, the above relational expression: L/d=constant can be satisfied by adjusting the difference in L between the capacitors by setting d to a proper value.

In this case, the widths of all of the second floating plates may be equal to one another, and the second floating plates may be arranged at regular intervals.

In the semiconductor device, the width of the second floating plate having a relatively larger peripheral length may be smaller than the width of the second floating plate having a relatively smaller peripheral length.

According to the structure, the width of the second floating plate having a relatively larger peripheral length is smaller than the width of the second floating plate having a relatively smaller peripheral length.

Thus, the distance between the outer periphery of the first floating plate arranged therebetween in plan view and the inner periphery of the second floating plate having a relatively larger peripheral length (i.e., the value d in the above relational expression) can be rendered greater than the distance between the outer periphery of the second floating plate having a relatively smaller peripheral length and the inner periphery of the first floating plate (i.e., the value d in the above relational expression). Therefore, the above relational expression: L/d=constant can be satisfied by adjusting the difference in L between the capacitors by setting d to a proper value.

In this case, the widths of all of the first floating plates may be equal to one another, and the first floating plates may be arranged at regular intervals.

In the semiconductor device, further, the widths of all of the first floating plates may be equal to one another, the widths of all of the second floating plates may be equal to one another, and the widths of the first floating plates and the widths of the second floating plates may be equal to one another.

Embodiments of the present invention are now described in detail with reference to the attached drawings.

FIG. 1is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.FIG. 2is an enlarged view of a region surrounded by a box II inFIG. 1.FIG. 3is a sectional view of the semiconductor device taken along a line inFIG. 1.

A semiconductor device1according to the first embodiment includes a thick-film SOI substrate2. The thick-film SOI substrate2has a structure obtained by laminating an active layer5as an N−-type semiconductor layer made of silicon on a silicon substrate3through a BOX layer4made of silicon oxide.

The thickness of the BOX layer4is 1 to 6 μm, for example. The thickness of the active layer5is 10 to 50 μm, for example. The N-type impurity concentration in the active layer5is 1013to 1016cm−3, for example.

A deep trench6in the form of a rectangular ring in plan view is formed in the active layer5to pass through the same in the thickness direction. In other words, the active layer5is provided with the deep trench6in the form of a rectangular ring in plan view having a depth reaching the BOX layer4from the surface thereof.

The inner side surfaces of the deep trench6are covered with a pair of silicon oxide films7. The thickness of the silicon oxide films7is 0.2 to 1.5 μm, for example.

The inner sides of the pair of silicon oxide films7are filled up with polysilicon8. Thus, an element forming region9surrounded by the deep trench6and dielectrically isolated from the periphery thereof by the BOX layer4and the silicon oxide films7is formed on the active layer5.

An LDMOSFET10is formed in the element forming region9. More specifically, the LDMOSFET10prepared by aligning unit cells having a gate length direction defined by the right-and-left direction inFIGS. 1 and 3along the direction is formed in the element forming region9. Each ofFIGS. 1 and 3shows only one of the plurality of unit cells.

The LDMOSFET10includes a P-type body region11and an N−-type drift region12in the active layer5.

The body region11is provided in the form of a ring along the side surface of the deep trench6every unit cell, with a thickness reaching the BOX layer4from the surface of the active layer5. In other words, the body region11is formed over the entire thickness of the active layer5. The body region11has an impurity concentration of 1015to 1018cm−3, for example.

The drift region12is a region, where the conductivity type of the active layer5is maintained in the active layer5, surrounded by the body region11. The drift region12has an impurity concentration of 1013to 1016cm−3, for example.

On a surface layer portion of the body region11, an N+-type source region13as a second impurity region and a P+-type body contact region14are formed to be adjacent to (in contact with) each other on positions separated from the drift region12. The source region13and the body contact region14are formed over the entire periphery of the body region11in plan view. The impurity concentration in the source region13, higher than that in the drift region12, is 1019to 1022cm−3, for example.

On a surface layer portion of the drift region12, a drain region15as a first impurity region is formed on a position separated from the body region11. The drain region15linearly extends in a vertical direction (the direction may hereinafter be simply referred to as “vertical direction”) along the gate width orthogonal to a transverse direction (the direction may hereinafter be simply referred to as “transverse direction”) along the gate length at a generally central portion between body regions11opposed to each other in the transverse direction. The thickness of the drain region15reaches a central portion of the active layer5in the thickness direction from the surface of the active layer5. The impurity concentration in the drain region15, higher than that in the drift region12, is 1019to 1022cm−3, for example.

On the surface of the drift region12, a field insulating film16is formed on a portion between the drain region15and the source region13at an interval from the body region11, i.e., at an interval from the source region13in plan view. The field insulating film16is in the form of a ring surrounding the drain region15. The field insulating film16is made of silicon oxide, and formed by LOCOS, for example. The thickness of the field insulating film16is 0.5 to 2 μm, for example.

On the surface of the active layer5, an annular gate insulating film17along the outer peripheral edge of the field insulating film16is formed over the body region11and the drift region12between the source region13and the field insulating film16. The gate insulating film17is made of silicon oxide, for example.

A gate electrode plate18extending over the gate insulating film17and the field insulating film16is formed on the active layer5. The gate electrode plate18is in the form of a ring covering the overall region of the surface (the upper surface) of the gate insulating film17. The gate electrode plate18has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction. The gate electrode plate18integrally has an electrode portion19and a field plate portion20.

The electrode portion19is formed on the gate insulating film17, and opposed to the body region11and the drift region12through the gate insulating film17. On the other hand, the field plate portion20extends onto the outer peripheral edge of the field insulating film16.

A drain electrode plate21is formed on the drain region15in the active layer5. The drain electrode plate21is linearly formed to be in contact with the overall region of the surface of the linear drain region15exposed from the field insulating film16, and the peripheral edge thereof extends onto the inner peripheral edge of the field insulating film16.

A source electrode plate23is formed on the body region11in the active layer5. The source electrode plate23is in the form of a ring, similar to the gate electrode plate18, in contact with the annular source region13and the body contact region14exposed from the field insulating film16.

Four first floating plates22are formed on the field insulating film16separately from the gate electrode plate18. All of the four first floating plates22are formed on the field insulating film16(the same layer).

Each first floating plate22is in the form of a ring similar to the gate electrode plate18. Therefore, each first floating plate22has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (first peripheral lengths) in the peripheral direction at the centers of the four first floating plates22in the width direction are different from one another, and smaller than a length (a gate peripheral length) in the peripheral direction at the center of the gate electrode plate18in the width direction.

In the description of the first embodiment, the first floating plates22having the different first peripheral lengths may be particularly distinguished from one another as first floating plates22ato22dsuccessively from that having the largest first peripheral length.

Similarity ratios of the first floating plates22are so set that the similarity ratio between a reference first floating plate22and a plate larger by one stage than the plate with reference to the first peripheral length is identical to the similarity ratio between the reference first floating plate22and a plate smaller by one stage than the plate with reference to the first peripheral length.

With reference to the first floating plate22b, for example, the similarity ratio between the first peripheral length of the first floating plate22band that of the first floating plate22alarger by one stage than the plate22bis set to be identical to the similarity ratio between the first peripheral length of the first floating plate22band that of the first floating plate22csmaller by one stage than the plate22b.

Widths A1to A4of the first floating plates22ato22dare entirely equal to one another. In other words, the relational expression: A1=A2=A3=A4is satisfied.

The four first floating plates22are so arranged that all plates22ato22dsurround the drain electrode plate21in an inner region of the gate electrode plate18in plan view.

Further, the four first floating plates22are so arranged that the first floating plate22having a relatively smaller first peripheral length is stored in an inner region of the first floating plate22having a relatively larger first peripheral length. More specifically, the first floating plate22ahaving the largest first peripheral length is arranged on a side closest to the gate electrode plate18. The first floating plate22bsmaller by one stage than the first floating plate22ais arranged to be stored in the inner region of the first floating plate22a. The first floating plates22cand22dare also arranged to be stored in the inner regions of the plates larger by single stages than the same respectively. Thus, each first floating plate22is opposed to the drift region12through the field insulating film16.

The four first floating plates22are so arranged as to divide the space between the gate electrode plate18and the drain electrode plate21at regular intervals. In other words, the intervals between the inner peripheries of the plates having relatively larger peripheral lengths and the outer peripheries of the plates having relatively smaller peripheral lengths are equal to one another.

More specifically, the interval B1between the inner periphery of the gate electrode plate18and the outer periphery of the first floating plate22a, the interval B2between the inner periphery of the first floating plate22aand the outer periphery of the first floating plate22b, the interval B3between the inner periphery of the first floating plate22band the outer periphery of the first floating plate22c, the interval B4between the inner periphery of the first floating plate22cand the outer periphery of the first floating plate22dand the interval B5between the inner periphery of the first floating plate22dand the outer periphery of the drain electrode plate21are entirely equal to one another. In other words, the relational expression: B1=B2=B3=B4=B5is satisfied.

The upper portion of the thick-film SOI substrate2is covered with a first interlayer dielectric film24made of silicon oxide.

Five second floating plates25are formed on the first interlayer dielectric film24. All of the five second floating plates25are formed on the first interlayer dielectric film24. In other words, all of the five second floating plates25are formed on the same layer above the first floating plates22.

Each second floating plate25is in the form of a ring similar to the gate electrode plate18. Therefore, all second floating plates25are similar to all first floating plates22. Each second floating plate25has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (second peripheral lengths) in the peripheral direction at the centers of the five second floating plates25in the width direction are different from one another, and also different from the first peripheral lengths of all first floating plates22. Further, all of the second peripheral lengths of the five second floating plates25are smaller than the gate peripheral length of the gate electrode plate18.

In the description of the first embodiment, the second floating plates25having the different second peripheral lengths may be particularly distinguished from one another as second floating plates25ato25esuccessively from that having the largest second peripheral length.

In the second floating plates25, the width of the second floating plate25having a relatively larger second peripheral length is smaller than that of the second floating plate25having a relatively smaller second peripheral length.

With reference to the second floating plate25b,for example, the width of the second floating plate25bis smaller than that of the second floating plate25chaving the second peripheral length smaller by one stage than that of the plate25b. In other words, widths E1to E5of the second floating plates25ato25esatisfy the relational expression: E1<E2<E3<E4<E5.

The five second floating plates25are dividedly arranged one by one between the plates18,21and22adjacent to one another in plan view respectively. Thus, the first floating plates22and the second floating plates25are alternately arranged between the gate electrode plate18and the drain electrode plate21in plan view.

More specifically, the second floating plate25ahaving the largest second peripheral length is arranged on a side closer to the gate electrode plate18, i.e., between the gate electrode plate18and the first floating plate22a. The second floating plate25bsmaller by one stage than the second floating plate25ais arranged between the first floating plate22aand the first floating plate22b. The second floating plates25cto25eare also arranged between the plates21and22adjacent to one another in plan view respectively.

The five second floating plates25are so arranged that all of the centers thereof in the width direction coincide with those of the spaces between the lower plates18,21and22in the width direction.

The upper portion of the first interlayer dielectric film24is covered with a second interlayer dielectric film26made of silicon oxide.

A source contact hole27facing the source electrode plate23is formed in the first interlayer dielectric film24and the second interlayer dielectric film26to pass through the same. Further, a drain contact hole28facing the drain electrode plate21is also formed in the first interlayer dielectric film24and the second interlayer dielectric film26to pass through the same.

A source wire29and a drain wire30are formed on the second interlayer dielectric film26. The source wire29is in the form of a ring along the shape of the source electrode plate23on an outer region of the gate electrode plate18in plan view. Further, the source wire29is connected to the source electrode plate23through a source contact plug31embedded in the source contact hole27.

The drain wire30is in the form of a straight line along the shape of the drain electrode plate21in an inner region of the second floating plate25ein plan view. Further, the drain wire30is connected to the drain electrode plate21through a drain contact plug32embedded in the drain contact hole28.

A current can be fed between the source region13and the drain region15(between a source and a drain) through the drift region12by grounding the source wire29and controlling the potential of the gate electrode plate18while applying a positive-polarity voltage (a drain voltage) to the drain wire30thereby forming a channel in the vicinity of the interface between the body region11and the gate insulating film17.

In the semiconductor device1, as hereinabove described, the four annular first floating plates22having the constant width are formed on the field insulating film16. Further, the five annular second floating plates25having the constant width are formed on the first interlayer dielectric film24above the first floating plates22. The first peripheral lengths of all first floating plates22and the second peripheral lengths of all second floating plates25are different from one another.

The first floating plates22and the second floating plates25are so alternately arranged in plan view that the plates having relatively smaller peripheral lengths (first and second peripheral lengths) are stored in the inner regions of the plates having relatively larger peripheral lengths (first and second peripheral lengths) between the gate electrode plate18and the drain electrode plate21in plan view.

Thus, capacitors having counter electrodes defined by the plates18,21and22adjacent to one another in plan view are formed on the field insulating film16. More specifically, 10 capacitors in total are formed with eight capacitors having counter electrodes defined by the first floating plates22and the second floating plates25, a capacitor having counter electrodes defined by the gate electrode plate18and the second floating plate25a, and a capacitor having counter electrodes defined by the drain electrode plate21and the second floating plate25e.

If an electric field generated between the counter electrodes of each capacitor formed on the field insulating film16is uniform, the potential distribution in a portion of the drift region12located under the counter electrodes can be uniformized.

In the semiconductor device1, therefore, the first floating plates22and the second floating plates25are formed to satisfy L/d=constant, where the values are defined as follows:

L: the outer periphery of the inner one of the first floating plate22and the second floating plate25adjacent to each other in plan view

d: the distance between the outer periphery of the plate defining L and the inner periphery of the first floating plate22or the second floating plate25adjacent to the plate to be opposed to the outer periphery thereof

More specifically, the first floating plates22, in which the widths A1to A4of all plates22ato22dare equal to one another, are arranged to divide the space between the gate electrode plate18and the drain electrode plate21at regular intervals.

In the second floating plates25, on the other hand, the width of the second floating plate25having a relatively larger second peripheral length is smaller than the width of the second floating plate25having a relatively smaller second peripheral length. Further, the second floating plates25are arranged to be closer to the gate electrode plate18successively from the second floating plate25having a relatively larger second peripheral length. In addition, the second floating plates25are so arranged that all centers thereof in the width direction coincide with the centers of the spaces between the lower plates18,21and22in the width direction.

Thus, the distance between the counter electrodes of each capacitor in plan view can be increased in proportion to the peripheral lengths of the plates forming the counter electrodes.

More specifically, it is assumed that F1represents the distance between the second floating plate25aand the gate electrode plate18as well as the first floating plate22a.Further, it is assumed that F2represents the distance between the second floating plate25band the first floating plates22aand22b, F3represents the distance between the second floating plate25cand the first floating plates22band22c,F4represents the distance between the second floating plate25dand the first floating plates22cand22d, and F5represents the distance between the second floating plate25eand the first floating plate22das well as the drain electrode plate21. In the semiconductor device1, the relational expression: F1>F2>F3>F4>F5can be satisfied in this case.

Therefore, the above relational expression: L/d=constant can be satisfied by adjusting the differences in L (the outer peripheries of the plates) between the capacitors by setting F1to F5to proper values.

The total capacitance C of each capacitor formed on the field insulating film16is the sum of the capacitanceC=∈·S/d per small sectionL of the outer periphery L of the inner plate in each capacitor (S: a small area of the outer peripheral surface of the inner floating plate perL), and expressed as C=∈·S/d.S expressing the area of the outer peripheral surface of the inner floating plate perL is proportionate toL, and hence S expressing the sum ofS is proportionate to L expressing the sum ofL.

Based on the condition where the first floating plates22and the second floating plates25satisfy L/d=constant, therefore, S/d=constant is deduced. In the plurality of capacitors having the counter electrodes defined by the first floating plates22and the second floating plates25having entirely different peripheral lengths (first and second peripheral lengths), therefore, the total capacitances can be entirely equalized with one another.

Consequently, the electric field generated between the counter electrodes of each capacitor can be uniformized, whereby the potential distribution between the source and the drain can be uniformized. Therefore, the withstand voltage can be improved.

FIG. 4is a schematic plan view of a semiconductor device according to a second embodiment of the present invention.FIG. 5is an enlarged view of a region surrounded by a box V inFIG. 4.FIG. 6is a sectional view of the semiconductor device taken along a line VI-VI inFIG. 4. Referring toFIGS. 4 to 6, portions corresponding to those shown inFIGS. 1 to 3are denoted by the same reference numerals. In the following, detailed description is omitted as to the portions denoted by the same reference numerals.

In semiconductor device41according to the second embodiment, four first floating plates42are formed on a field insulating film16separately from a gate electrode plate18. All of the four first floating plates42are formed on the field insulating film16(the same layer).

Each first floating plate42is in the form of a ring similar to the gate electrode plate18. Therefore, each first floating plate42has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (first peripheral lengths) in the peripheral direction at the centers of the four first floating plates42in the width direction are different from one another, and smaller than a length (a gate peripheral length) in the peripheral direction at the center of the gate electrode plate18in the width direction.

In the description of the second embodiment, the first floating plates42having the different first peripheral lengths may be particularly distinguished from one another as first floating plates42ato42dsuccessively from that having the largest first peripheral length.

Widths G1to G4of the first floating plates42ato42dare entirely equal to one another. In other words, the relational expression: G1=G2=G3=G4is satisfied.

The four first floating plates42are so arranged that all plates42ato42dsurround a drain electrode plate21in an inner region of the gate electrode plate18in plan view.

Further, the four first floating plates42are so arranged that the first floating plate42having a relatively smaller first peripheral length is stored in an inner region of the first floating plate42having a relatively larger first peripheral length. More specifically, the first floating plate42ahaving the largest first peripheral length is arranged on a side closest to the gate electrode plate18. The first floating plate42bsmaller by one stage than the first floating plate42ais arranged to be stored in the inner region of the first floating plate42a. The first floating plates42cand42dare also arranged to be stored in the inner regions of the plates larger by single stages than the same respectively. Thus, each first floating plate42is opposed to a drift region12through the field insulating film16.

The four first floating plates42are arranged between the gate electrode plate18and the drain electrode plate21so that the intervals therebetween are increased in the direction toward the gate electrode plate18along the surface of the field insulating film16.

For example, the four first floating plates42are so arranged that the interval between the outer periphery of a reference first floating plate42and the inner periphery of the first floating plate42larger by one stage than the plate is greater than the interval between the inner periphery of the reference first floating plate42and the outer periphery of the first floating plate42smaller by one stage than the plate.

More specifically, with reference to the first floating plate42b, the four first floating plates42are so arranged that the interval H2between the outer periphery of the first floating plate42band the inner periphery of the first floating plate42ais greater than the interval H3between the inner periphery of the first floating plate42band the outer periphery of the first floating plate42c.

In the semiconductor device41, further, five second floating plates45are formed on a first interlayer dielectric film24. All of the five second floating plates45are formed on the first interlayer dielectric film24. In other words, all of the second floating plates45are formed on the same layer above the first floating plates42.

Each second floating plate45is in the form of a ring similar to the gate electrode plate18. Therefore, all second floating plates45are similar to the first floating plates42. Each second floating plate45has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (second peripheral lengths) in the peripheral direction at the centers of the five second floating plates45in the width direction are different from one another, and also different from the first peripheral lengths of all first floating plates42. Further, all of the second peripheral lengths of the five second floating plates45are smaller than the gate peripheral length of the gate electrode plate18.

In the description of the second embodiment, the second floating plates45having the different second peripheral lengths may be particularly distinguished from one another as second floating plates45ato45esuccessively from that having the largest second peripheral length.

Widths I1to I5of the second floating plates45ato45eare entirely equal to one another, and also equal to the widths G1to G4of the first floating plates42ato42d.In other words, the widths of all first floating plates42are equal to one another, the widths of all second floating plates45are equal to one another, and the widths of the first floating plates42and those of the second floating plates45are equal to one another. Namely, the relational expression: G1=G2=G3=G4=I1=I2=I3=I4=I5is satisfied.

The five second floating plates45are dividedly arranged one by one between the plates18,21and22adjacent to one another in plan view. Thus, the first floating plates42and the second floating plates45are alternately arranged in plan view between the gate electrode plate18and the drain electrode plate21.

More specifically, the second floating plate45ahaving the largest second peripheral length is arranged on a side closer to the gate electrode plate18, i.e., between the gate electrode plate18and the first floating plate42a. The second floating plate45bsmaller by one stage than the second floating plate45ais arranged between the first floating plate42aand the first floating plate42b. The second floating plates45cto45eare also arranged between the plates21and42adjacent to one another in plan view respectively.

The five second floating plates45are so arranged that all of the centers thereof in the width direction coincide with those of the spaces between the lower plates18,21and42in the width direction.

In the semiconductor device41, as hereinabove described, the widths of all first floating plates42are equal to one another, the widths of all second floating plates45are equal to one another, and the widths of the first floating plates42and those of the second floating plates45are equal to one another.

Further, the first floating plates42are arranged between the gate electrode plate18and the drain electrode plate21so that the intervals therebetween are increased in the direction toward the gate electrode plate18along the surface of the field insulating film16.

On the other hand, the five second floating plates45are so arranged that all of the centers thereof in the width direction coincide with those of the spaces between the lower plates18,21and42in the width direction.

Thus, the distance between counter electrodes of each capacitor in plan view can be increased in proportion to the peripheral lengths of the plates forming the counter electrodes.

More specifically, it is assumed that J1represents the distance between the second floating plate45aand the gate electrode plate18as well as the first floating plate42a.Further, it is assumed that J2represents the distance between the second floating plate45band the first floating plates42aand42b, J3represents the distance between the second floating plate45cand the first floating plates42band42c,J4represents the distance between the second floating plate45dand the first floating plates42cand42d, and J5represents the distance between the second floating plate45eand the first floating plate42das well as the drain electrode plate21. In the semiconductor device41, the relational expression: J1>J2>J3>J4>J5can be satisfied in this case.

Therefore, the above relational expression: L/d=constant can be satisfied by adjusting the differences in L (the outer peripheries of the plates) between the capacitors by setting J1to J5to proper values.

In a plurality of capacitors having counter electrodes defined by the first floating plates42and the second floating plates45all having different peripheral lengths (first peripheral lengths and second peripheral lengths), therefore, total capacitances can be entirely equalized with one another.

Consequently, an electric field generated between the counter electrodes of each capacitor can be uniformized, whereby the potential distribution between a source and a drain can be uniformized. Therefore, the withstand voltage can be improved.

FIG. 7is a schematic plan view of a semiconductor device according to a third embodiment of the present invention.

FIG. 8is an enlarged view of a region surrounded by a box VIII-VIII inFIG. 7.FIG. 9is a sectional view of the semiconductor device taken along a line IX-IX inFIG. 7. Referring toFIGS. 7 to 9, portions corresponding to those shown inFIGS. 1 to 3are denoted by the same reference numerals. In the following, detailed description is omitted as to the portions denoted by the same reference numerals.

In a semiconductor device71according to the third embodiment, four first floating plates72are formed on a field insulating film16separately from a gate electrode plate18. All of the first floating plates72are formed on the field insulating film16(the same layer).

Each first floating plate72is in the form of a ring similar to the gate electrode plate18. Therefore, each first floating plate72has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (first peripheral lengths) in the peripheral direction at the centers of the four first floating plates72in the width direction are different from one another, and smaller than a length (a gate peripheral length) in the peripheral direction at the center of the gate electrode plate18in the width direction.

In the description of the third embodiment, the first floating plates72having the different first peripheral lengths may be particularly distinguished from one another as first floating plates72ato72dsuccessively from that having the largest first peripheral length.

In the first floating plates72, the width of the first floating plate72having a relatively larger first peripheral length is smaller than the width of the first floating plate72having a relatively smaller first peripheral length.

With reference to the first floating plate72b, for example, the width of the first floating plate72bis smaller than the width of the first floating plate72chaving the first peripheral length smaller by one stage than that of the plate72b. In other words, widths K1to K4of the first floating plates72ato72dsatisfy the relational expression: K1<K2<K3<K4.

The four first floating plates72are so arranged that all plates72ato72dsurround a drain electrode plate21in an inner region of the gate electrode plate18in plan view.

Further, the four first floating plates72are so arranged that the first floating plate72having a relatively smaller first peripheral length is stored in an inner region of the first floating plate72having a relatively larger first peripheral length. More specifically, the first floating plate72ahaving the largest first peripheral length is arranged on a side closest to the gate electrode plate18. The first floating plate72bsmaller by one stage than the first floating plate72ais arranged to be stored in the inner region of the first floating plate72a. The first floating plates72cand72dare also arranged to be stored in the inner regions of the plates larger by single stages than the same respectively. Thus, each first floating plate72is opposed to a drift region12through the field insulating film16.

The four first floating plates72are arranged between the gate electrode plate18and the drain electrode plate21so that the intervals therebetween are increased in the direction toward the gate electrode plate18along the surface of the field insulating film16.

For example, the first floating plates72are so arranged that the interval between the outer periphery of a reference first floating plate72and the inner periphery of the first floating plate72larger by one stage than the plate is greater than the interval between the inner periphery of the reference first floating plate72and the outer periphery of the first floating plate72smaller by one stage than the plate.

More specifically, with reference to the first floating plate72b, the first floating plates72are so arranged that the interval M2between the outer periphery of the plate72band the inner periphery of the first floating plate72ais greater than the interval M3between the inner periphery of the first floating plate72band the outer periphery of the first floating plate72c.

In the semiconductor device71, further, five second floating plates75are formed on a first interlayer dielectric film24. All of the second floating plates75are formed on the first interlayer dielectric film24. In other words, all of the second floating plates75are formed on the same layer above the first floating plates72.

Each second floating plate75is in the form of a ring similar to the gate electrode plate18. Therefore, all second floating plates75are similar to the first floating plates72. Each second floating plate75has the same width (a constant width) orthogonal to the peripheral direction on any position in the peripheral direction.

All lengths (second peripheral lengths) in the peripheral direction at the centers of the five second floating plates75in the width direction are different from one another, and also different from the first peripheral lengths of all first floating plates72. Further, all of the second peripheral lengths of the five second floating plates75are smaller than the gate peripheral length of the gate electrode plate18.

In the description of the third embodiment, the second floating plates75having the different second peripheral lengths may be particularly distinguished from one another as second floating plates75ato75esuccessively from that having the largest second peripheral length.

Widths N1to N5of the second floating plates75ato75eare entirely equal to one another. In other words, the relational expression: N1=N2=N3=N4=N5is satisfied.

The five second floating plates75are dividedly arranged one by one between the plates18,21and72adjacent to one another in plan view. Thus, the first floating plates72and the second floating plates75are alternately arranged in plan view between the gate electrode plate18and the drain electrode plate21.

More specifically, the second floating plate75ahaving the largest second peripheral length is arranged on a side closer to the gate electrode plate18, i.e., between the gate electrode plate18and the first floating plate72a. The second floating plate75bsmaller by one stage than the second floating plate75ais arranged between the first floating plate72aand the first floating plate72b. The second floating plates75cto75eare also arranged between the plates21and72adjacent to one another in plan view respectively. The five second floating plates75are so arranged that the intervals between the plates75adjacent to one another in plan view are equal to one another.

In the semiconductor device71, as hereinabove described, the width of the first floating plate72having a relatively larger first peripheral length is smaller than the width of the first floating plate72having a relatively smaller first peripheral length. Further, the first floating plates72are arranged between the gate electrode plate18and the drain electrode plate21so that the intervals therebetween are increased in the direction toward the gate electrode plate18along the surface of the field insulating film16.

In the second floating plates75, on the other hand, the widths N1to N5of the plates75ato75eare entirely equal to one another. Further, the second floating plates75are alternately arranged with the first floating plates72in plan view, and so arranged that the intervals between the plates75adjacent to one another in plan view are equal to one another.

Thus, the distance between counter electrodes of each capacitor in plan view can be increased in proportion to the peripheral lengths of the plates forming the counter electrodes.

More specifically, it is assumed that O1represents the distance between the second floating plate75aand the gate electrode plate18as well as the first floating plate72a.Further, it is assumed that O2represents the distance between the second floating plate75band the first floating plates72aand72b, O3represents the distance between the second floating plate75cand the first floating plates72band72c,O4represents the distance between the second floating plate75dand the first floating plates72cand72d, and O5represents the distance between the second floating plate75eand the first floating plate72das well as the drain electrode plate21. In the semiconductor device71, the relational expression: O1>O2>O3>O4>O5can be satisfied in this case.

Therefore, the above relational expression: L/d=constant can be satisfied by adjusting the differences in L (the outer peripheries of the plates) between the capacitors by setting O1to O5to proper values.

In a plurality of capacitors having counter electrodes defined by the first floating plates72and the second floating plates75all having different peripheral lengths (first peripheral lengths and second peripheral lengths), therefore, total capacitances can be equalized with one another.

Consequently, an electric field generated between the counter electrodes of each capacitor can be uniformized, whereby the potential distribution between a source and a drain can be uniformized. Therefore, the withstand voltage can be improved.

While the embodiments of the present invention have been described, the present invention may be embodied in other ways.

For example, the number of the first floating plates22,42or72or the second floating plates25,45or75may be one or two, or may be not less than four.

In each of the semiconductor devices1,41and71, the conductivity types of the semiconductor regions may be inverted. In other words, the N-type regions may be replaced with P-type regions, and the P-type regions may be replaced with N-type regions in each of the semiconductor devices1,41and71.

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

This application corresponds to Japanese Patent Application No. 2008-334481 filed with the Japan Patent Office on Dec. 26, 2008, the disclosure of which is incorporated herein by reference.