Method of forming photomask

A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a photomask, and more particularly to a method of forming a photomask including an optical proximity correction process with adding the assist feature pattern.

2. Description of the Prior Art

With the trend of miniaturization of electronic products and peripheral devices, research for thin structures and high integration of semiconductor devices has become a main concern in the industry. Lithography technology plays an important role in determining the performance of semiconductor devices.

In a semiconductor manufacturing process, the integrated circuit layout is first designed and formed as a photomask pattern. The photomask pattern is then proportionally transferred to a photoresist layer disposed on the semiconductor wafer through an exposure process followed by a development process, so that a photoresist pattern with the integrated circuit layout on the semiconductor wafer is formed. Subsequently, a corresponding etching process is performed to transfer the photoresist pattern to the semiconductor wafer so as to manufacture the semiconductor devices. As the line width of the integrated circuit shrinks to be less than half the wavelength of light used in the exposure process, diffraction and interference of the light will occur, which results in deviations in the transferred pattern such as rounded right-angle corners, shortened line-ends, or increase/decrease of line widths. This phenomenon is also called the optical proximity effect (OPE).

To overcome the above problems, an optical proximity correction (OPC) process is developed to change each pattern of the photomask pattern, so that the transferred pattern may be more like the required integrated circuit layout. However, when the critical dimension is less than 65 nm, depth of focus of the lithography process is rapidly reduced. Accordingly, assist features such as dummy patterns or scattering bars are developed to be added to the photomask pattern through performing an optical simulation and disposed between the layout patterns of the original photomask pattern, for reducing the risk of deformation of the transferred pattern on the semiconductor wafer. However, when the pattern of the original photomask pattern is symmetric, the assist features generated by the optical simulation are usually asymmetric, which would cause difficulty to inspect a defect on the formed photomask and difficulty to verify the accuracy of the formed semiconductor devices on the semiconductor wafer. In the inspection of the defect of the formed photomask, two areas with the same pattern are compared, and if they are different, the defect can be found. However, when the assist features are not symmetric, it is easily to find two different patterns, but they may be correct, thereby increasing the difficulty of the inspection. Also, in the verification of the semiconductor devices, when the assist features are not symmetric, the intensity of light passing two different areas may be different, so that it is not easily to confirm if the semiconductor devices in the different areas are correct. Accordingly, a way to form a symmetric assist feature pattern to ease the inspection of the defect of the photomask and the verification of the semiconductor wafer is an important issue in the field.

SUMMARY OF THE INVENTION

An objective of the present invention is therefore to provide a method of forming a photomask that make the inspection of a defect on the formed photomask and the verification of the accuracy of the formed semiconductor devices on the semiconductor wafer more easily.

According to an embodiment of the present invention, a method of forming a photomask is provided and includes the following steps. First, a first layout pattern is provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.

In the method of forming the photomask of the present invention, the symmetric assist feature pattern is generated in the second layout pattern, and the assist feature pattern is not altered during the OPC process, so that the assist feature pattern can be still symmetric. Accordingly, the inspection of a defect on the formed photomask and the verification of the accuracy of the formed semiconductor devices on the semiconductor wafer can be easily done.

DETAILED DESCRIPTION

In the following description, numerous specific details, as well as accompanying drawings, are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details.

Refer toFIG. 1as well asFIGS. 2-12.FIG. 1is a flowchart of a method of forming a photomask according to one embodiment of the present invention, andFIGS. 2-12are schematic diagrams illustrating the method of forming the photomask according to the first embodiment of the present invention, in whichFIGS. 3-10are schematic diagrams illustrating a method of generating an assist feature pattern. As shown inFIG. 1andFIG. 2, in step S10, a first layout pattern102is provided to a computer system. The first layout pattern102includes a plurality of patterns104, which is an ideal pattern supposed to be later transferred on a mask or a material layer such as a photoresist layer on a semiconductor wafer. The patterns104are printable patterns used to construct integrated circuits (IC) such as doped region patterns, device patterns, or layout of circuits. In this embodiment, the patterns104are symmetric with respect to a horizontal center line HCL and a vertical center line VCL of the first layout pattern102. For example, in a method for manufacturing a static random access memory (SRAM) device, each pattern104may be rectangular, a length of each pattern104in a horizontal direction H is larger than a width of each pattern104in a vertical direction V, and the patterns104are arranged as a plurality of mutually staggered rows. In another embodiment, each pattern104may be other polygonal shape. For clarity, only four symmetric patterns104adjacent to each other are shown inFIG. 2, but not limited thereto. The four patterns104shown inFIG. 2may be regarded as a unit, and the first layout pattern102may include a plurality of the units, in which adjacent rows of the units may be staggered. The four patterns104are taken as an example in the following description, but the present invention is not limited thereto. Specifically, the four patterns104may be divided into two first patterns104aand two second patterns104b, in which the first patterns104aare arranged along the horizontal direction H and between the second patterns104b, and the second patterns104bare arranged along in the vertical direction V and overlap both the first patterns104ain the vertical direction V. More specifically, centers of the second pattern104band a center of a gap between the first patterns104aare arranged in a line along the vertical direction V.

As shown inFIG. 11, in step S12, after the first layout pattern102is provided, an assist feature pattern106is generated by the computer system based on the first layout pattern102, and the assist feature pattern106is inserted into the first layout pattern102to form a second layout pattern116. The assist feature pattern106includes a plurality of first assist features108and a plurality of second assist features110, in which each of the first assist features108is disposed between any two of the patterns104adjacent to each other, and each of the second assist features110is disposed at an outside of the first layout pattern102respectively. In this embodiment, a pattern formed by the first assist features108and the second assist features110are symmetrical with respect to the vertical center line VCL and the horizontal center line HCL crossing a center of the first layout pattern102. The first assist features108and the second assist features110are non-printable features; more specifically, when the photomask including the first layout pattern102and the assist feature pattern106is used in a lithography process performed on a light-sensitive material layer on the semiconductor wafer, only the patterns corresponding to the first layout pattern102can be formed on the material layer, and the patterns corresponding to the assist feature pattern106will not be formed on the light-sensitive material layer.

The following description further details the formation of the symmetric assist feature pattern. As shown inFIG. 3, first, the computer system generates a plurality of assist feature seeds112by performing an optical simulation step based on the first layout pattern102, and the assist feature seeds112are inserted into the first layout pattern102. The optical simulation step is to simulate light passing through the first layout pattern102onto the semiconductor wafer so as to find where the largest intensity of light is, and generate and insert the assist feature seeds112to areas that has the largest intensity of light. Thus, pattern density of the first layout pattern102inserted with the assist feature seeds112can be made uniform, and the light intensity distribution can be equalized. After the optical simulation step, the assist feature seeds112are inserted into the first layout pattern102. In this embodiment, the assist feature seeds112substantially surround each of the patterns104, but not limited thereto. For example, each of the assist feature seeds112may be smaller than each of the patterns104, and may be circle or other shapes, but not limited thereto. The assist feature seeds112may be divided into several parts, and the neighboring assist feature seeds112in each of the parts may be connected to each other. The size, the shape, the quantity and the arrangement of the assist feature seeds112can be modified according to process requirements. Those skilled in the art should know the optical simulation step may use an optical model, such as SPLAT, Calibre nmSRAF tool or other kinds of software, stored in the computer system, to simulate the light intensity distribution and generate the assist feature seeds112. The assist feature seeds112may be also called the Model-based assist feature. Additionally, the size range and the arrangement of the assist feature seeds112may obey the rules of the assist feature process rule check (PRC) such as limitation of the critical dimension and the critical space. In one embodiment, a width of each of the assist feature seeds112is smaller than a specific value, i.e. the maximum size of patterns in the photomask which cannot be resolved through the lithography process, and larger than the photomask manufacturing limit of the corresponding tool, i.e. the minimum size of patterns which can be formed in the photomask by a tool for manufacturing the photomask. More specifically, for a semiconductor process having critical dimensions of 20 nanometers (nm), the maximum size of the patterns in the photomask which cannot be resolved is substantially around 32 nm, and the photomask manufacturing limit is substantially around 13 nm. Accordingly, the width of each assist feature seed112is substantially between 13 nm and 32 nm, but not limited thereto. It should be noted that since the assist feature seeds112are generated by the optical simulation, the distribution of the assist feature seeds112is not regular and would be changed with the position and disposed direction of the first layout pattern102. Thus, if the first layout pattern102inserted with the assist feature seeds112is directly used to form a photomask, uncertainty and non-consistency of the formed photomask would be generated, and the asymmetry of the assist feature seeds112still exists. To avoid that, the following steps are further performed in this embodiment.

As shown inFIG. 4, after the assist feature seeds112are generated, a center line generation is performed to generate a plurality of first lines L1and a plurality of fourth lines L4by the computer system based on the first layout pattern102, and the first lines L1and the fourth lines L4are added into the first layout pattern102. Each of the first lines L1is respectively disposed at the center of the gap between any two of the patterns104adjacent to each other and parallel to sides of the any two of the patterns104, and a spacing between each of the first lines L1and one of the any two of the patterns104is the same as another spacing between each of the first lines L1and another one of the any two of the patterns104. Specifically, each of the first lines L1having a width less than the size of each of the assist feature seeds112, such as 5 nm, is generated corresponding to an inner side of each of the patterns104and between any two adjacent patterns104. In this embodiment, the first lines L1can be divided into one first vertical line VL1disposed along the vertical direction V and two first horizontal lines HL1disposed along the horizontal direction H. The first vertical line VL1is disposed between the first patterns104aand a length of the first vertical line L1is larger than that of the corresponding side of each of the first patterns104a. Also, the first vertical line VL1doesn't cross the second patterns104b, and two ends of the first vertical line VL1are respectively spaced apart from each of the second patterns104bby a distance. The first horizontal lines HL1are respectively disposed between one of the second patterns104band the first patterns104aand between the other one of the second patterns104band the first patterns104a. Since a length of each of the first horizontal lines HL1is larger than that of the corresponding side of each of the second patterns104band that of the corresponding side of each of the first patterns104a, the first horizontal lines HL1arranged in the same line along the horizontal direction H can be combined to be one first horizontal line HL1.

Additionally, each of the fourth lines L4is disposed at the outside of the first layout pattern102, and spaced apart from an outmost one of the patterns104by a predetermined distance. In this embodiment, the fourth lines L4can be divided into six fourth vertical lines VL4disposed along the vertical direction V and two fourth horizontal lines HL4disposed along the horizontal direction H. Each of the fourth vertical lines VL4is respectively generated corresponding to each vertical side of each of the second patterns104band the outer vertical side of each of the first patterns104, and doesn't cross the patterns104. Each of the fourth horizontal lines HL4is respectively generated corresponding to the outer horizontal side of each of the second patterns104b. The predetermined distance may be set according to the design requirements.

As shown inFIG. 5, another center line generation is then performed to generate a plurality of second lines L2and a plurality of fifth lines L5, and the second lines L2and the fifth lines L5are added into the first layout pattern102. For clarity, some outer parts are not shown inFIG. 5, but the present invention is not limited thereto. Each of the second lines L2is disposed at another center of another gap between each of the first lines L1and a corresponding one of the patterns104. Also, each of the second lines L2is parallel to the corresponding first line L1, and the spacing between each of the second lines L2and the corresponding first line L1is the same as the spacing between each of the second lines L2and the corresponding pattern104. Each of the second lines L2has the same length and width as the corresponding first line L1, and will not be detailed redundantly. Additionally, each of the fifth lines L5is disposed at another center of another gap between each of the fourth lines L4and a corresponding one of the patterns104and is parallel to the corresponding fourth line L4, and accordingly, the spacing between each of the fifth lines L5and the corresponding fourth line L4is the same as the spacing between each of the fifth lines L5and the corresponding pattern104. Each of the fifth lines L5has the same length and width as the corresponding fourth line L4, and will not be detailed redundantly.

Subsequently, another center line generation is further performed to generate a plurality of third lines L3and a plurality of sixth lines L6, and the third lines L3and the sixth lines L6are added into the first layout pattern102, in which each of the third lines L3is respectively disposed at another center of another gap between each of the second lines L2and a corresponding one of the patterns104and another center of another gap between each of the second lines L2and a corresponding one of the first lines L1, and each of the sixth lines L6is respectively disposed at another center of another gap between each of the fifth lines L5and a corresponding one of the patterns104and another center of another gap between each of the fifth lines L5and a corresponding one of the fourth lines L4. The generation of the third lines L3and the sixth lines L6is similar to the generation of second lines L2and the fifth lines L5, so that each of the third lines L3has the same length and width as the corresponding second line L2, and each of the sixth lines L6has the same length and width as the corresponding fifth line L5.

In this embodiment, another center line generation may be selectively performed to generate a plurality of seventh lines L7and a plurality of eighth lines L8, and the seventh lines L7and the eighth lines L8are added into the first layout pattern102, in which each of the seventh lines L7is respectively disposed at another center of another gap between each of the third lines L3and a corresponding one of the patterns104, another center of another gap between each of the third lines L3and a corresponding one of the second lines L2and another center of another gap between each of the third lines L3and a corresponding one of the first lines L1, and each of eighth lines L8is respectively disposed at another center of another gap between each of the sixth lines L6and a corresponding one of the patterns104, another center of another gap between each of the sixth lines L6and a corresponding one of the fifth lines L5and another center of another gap between each of the sixth lines L6and a corresponding one of the fourth lines L4. The generation of the seventh lines L7and the eighth lines L8is similar to the generation of the third lines L3and the sixth lines L6, so that each of the seventh lines L7has the same length and width as the corresponding third line L3, and each of the eighth lines L8has the same length and width as the corresponding sixth line L6. According the above-mentioned center line generations, all of the lines are not in contact with the patterns104, and formed among the patterns104. It should be noted that the number of the center line generations of this embodiment is four, so that a gap between any two adjacent lines can be smaller than the photomask manufacturing limit, but the present invention is not limited thereto. The center line generations of the present invention should be performed several times until the gap is smaller than the photomask manufacturing limit. The number of the center line generations may be at least three or more.

As shown inFIG. 6, the first lines L1, the second lines L2, the third lines L3and the seventh lines L7are cut off to form a plurality of line segments114based on each of the patterns104. Specifically, each of the patterns104may be used to form a plurality of cutting lines CL. Refer toFIGS. 7-8, which show the steps of forming the cutting lines. As shown inFIG. 7, all sides of each of the patterns104may be expanded and shrunk by a predetermined thickness to form two rectangles, and the rectangles can form a rectangular ring R. The thickness of the rectangular ring R is larger than the photomask manufacturing limit, i.e. two times the predetermined thickness should be larger than the photomask manufacturing limit. Then, as shown inFIG. 8, corners of each rectangular ring R are removed to form four rectangular portions RP in each of the patterns104, and an extension direction of each side of each of the rectangular portions RP is regarded as a cutting line CL. Thereafter, the cutting lines CL can be used to cut off all of the lines formed in the center line generations, and the lines between any two of cutting lines CL formed by the extension directions of the long sides of the same rectangular portion RP are removed, thereby forming the line segments114. A gap may exist between two adjacent line segments114arranged along the same line.

As shown inFIG. 9, after the line segments114are formed, a part of the line segments114is retained, and other part of the line segments114is removed based on a predetermined judgment condition. Specifically, each of the line segments114and the assist feature seeds112have an overlapping area, and the predetermined judgment condition is based on the size of the overlapping area. For example, the predetermined judgment condition is preferably that when a ratio of the overlapping area to the corresponding line segment114is greater than 0.3, the line segment114is retained. If the overlapping doesn't comply with the condition, the corresponding line segment114is removed. In another embodiment, the judgment condition may be that the overlapping area is ten times greater than a width of the corresponding line segment114. That is, the overlapping area of each of the retained part of the line segments114and the assist feature seeds112is ten times greater than the width of the corresponding line segment114. For example, when a width of each of the line segments114is 5 nm, the overlapping area should be greater than 50 nm2while the corresponding line segment114is retained.

As shown inFIG. 10, subsequently, the retained line segments114spaced apart by a distance smaller than the photomask manufacturing limit are merged, and the line segments114spaced apart by another distance larger than the photomask manufacturing limit are maintained, thereby forming the assist feature pattern106of this embodiment. Following that, as shown inFIG. 11, the assist feature seeds112are removed, and the formed assist feature pattern106is inserted into the first layout pattern102to form the second layout pattern116. The formed assist feature pattern106is symmetric with respect to the horizontal center line HCL and the vertical center line VCL of the first layout pattern102.

As shown inFIG. 12, an optical proximity correction (OPC) process is then performed with reference to both the first layout pattern102and the assist feature pattern106to the second layout pattern116by the computer system without altering the assist feature pattern106in step S14so as to correct the line width, the line end or the corner of each of the patterns of the first layout pattern102in the second layout pattern116. Accordingly, the first layout pattern102can be modified to be a corrected first layout pattern118, and a third layout pattern120can be formed. Specifically, the line width, the line end and the corner of each of the patterns104are corrected to be the corrected patterns122so as to increase the correctness of the corrected first layout pattern118transferred on the material layer on the semiconductor wafer. Thereafter, the third layout pattern120is output to form the photomask of this embodiment in step S16. It should be noted that a layout position, a layout dimension and/or a layout shape of the assist feature pattern106remains the same during the optical proximity correction process, so that the assist feature pattern106in the third layout pattern120can be still symmetric. Thus, it is easy to inspect a defect on the formed photomask by finding two different patterns and to verify the accuracy of the formed semiconductor devices on the semiconductor wafer.

As the above-mentioned description, in the present invention, the method of forming the photomask can generate the symmetric assist feature pattern in the second layout pattern, and the assist feature pattern is not altered during the OPC process, so that the assist feature pattern can be still symmetric. Accordingly, the inspection of a defect on the formed photomask and the verification of the accuracy of the formed semiconductor devices on the semiconductor wafer can be easily done.