Semiconductor structures and die assemblies including conductive vias and thermally conductive elements and methods of forming such structures

A semiconductor structure comprises conductive vias extending from an active surface of a substrate to a back side of the substrate and surrounded by a dielectric material. The conductive vias are surrounded by recessed isolation structures formed within the back side of the substrate. Conductive elements extend over the conductive vias and laterally over at least portions of the isolation structures. The conductive elements are in electrical contact with the conductive vias and electrically isolated from the substrate by the isolation structures. Thermally conductive elements in contact with the substrate are laterally spaced from the conductive elements. Die assemblies comprising the semiconductor structure, methods of forming the semiconductor structure, and methods of forming the die assemblies are also disclosed.

TECHNICAL FIELD

Embodiments disclosed herein relate to semiconductor structures and die assemblies providing enhanced thermal management and exhibiting reduced oxide-induced wafer warpage. More specifically, embodiments disclosed herein relate to semiconductor structures and die assemblies including conductive vias and thermally conductive elements having reduced wafer warpage and improved thermal management, and methods of forming such structures and die assemblies.

BACKGROUND

Increased circuit density is an ongoing goal of manufacturers of semiconductor devices. One favored configuration to increase circuit density is an assembly of vertically stacked semiconductor dice, at least some of which are interconnected electrically, the stacked die assembly being mechanically and electrically connected to higher level packaging, such as an interposer or other substrate bearing conductive traces.

One such configuration employing a plurality of stacked semiconductor dice is a Micropillar Grid Array (“MPGA”) package. Such a package comprises a stack of a plurality (for example, four (4), eight (8), sixteen (16), etc.) of dynamic random access memory (DRAM) dice vertically interconnected from an uppermost die to a lowermost die, and a plurality of electrically conductive pillars extending from the underside of the lowermost memory die for connection to a logic die, such as, by way of non-limiting example, a System on a Chip (SoC) die.

A challenge associated with stacked die packages is that the heat generated by the individual dies and associated circuitry combines and increases the operating temperatures of the individual dies, the junctions therebetween, and the package as a whole. This can cause the stacked dies to reach temperatures above their maximum operating temperatures (Tmax), especially as the density of the dies in the package increases.

Another challenge associated with stacked die packages is the formation of oxide-induced stresses on a back side of semiconductor dice that make up the stacked die package. Dielectric materials on the back side of the semiconductor dice that isolate conductive portions of the dice from the substrate thereof often induce stresses in the substrate.

Accordingly, one significant focus with regard to formation of such stacked die packages is effective thermal management of heat generated during operation by stacked memory dice of the die assembly, in combination with heat generated by a logic or SoC die at the base of the die assembly so that the maximum operational temperature of each die within the package does not exceed acceptable limits. Another focus is the effective management and reduction of induced stresses that cause wafer warpage (e.g., bowing) of the semiconductor structures, which inhibits the ability of transfer and process equipment to handle wafers effectively and without damage, as well as impairing yield of wafer-level processing techniques used to form stacked die assemblies.

DETAILED DESCRIPTION

The illustrations included herewith are not meant to be actual views of any particular systems or semiconductor structures, but are merely idealized representations that are employed to describe embodiments described herein. Elements and features common between figures may retain the same numerical designation.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing semiconductor structures or semiconductor die assemblies, and the semiconductor structures and die assemblies described below do not form a complete semiconductor device or die assembly. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete semiconductor device or a complete die assembly including the semiconductor structures may be performed by conventional techniques.

A conventional semiconductor structure100comprising a portion of a wafer is shown inFIG. 1. The semiconductor structure100includes at least one conductive element in the form of a so-called “through silicon via” (TSV)106extending from a front side104(which may also be characterized as an active surface) to a back side130of a wafer-level substrate102. The TSV106includes a conductive material that may be electrically isolated from the substrate102and surrounding structures by a dielectric material108formed around sidewalls of the TSV106. An electrically conductive element115in electrical communication with the TSV106may include a conductive seed material114and a conductive material116formed on the conductive seed material114. The conductive material116may overlie the conductive seed material114. A barrier material110may overlie the back side130of the substrate102. An electrically insulating material112may overlie the barrier material110. The barrier material110and the electrically insulating material112may electrically insulate the electrically conductive element115from the substrate102. The barrier material110and the electrically insulating material112may be continuous across the back side130of the substrate102, such as between adjacent TSVs106. However, a continuous barrier material110and a continuous electrically insulating material112extending across the back side130of the substrate102may contribute to stresses in the semiconductor material of the substrate102, causing wafer warpage and bowing.

The semiconductor structure100may also include at least one thermally conductive element125. The thermally conductive element125may include a conductive seed material114tand a thermally conductive material116t, which may also be electrically conductive, overlying the conductive seed material114t. The thermally conductive element125may be employed, in combination with a thermally conductive structure, such as a pillar or stud (not shown), to transfer heat between one semiconductor structure100and another, adjacent, superimposed semiconductor structure100(not shown), in a stacked array of semiconductor structures100. However, the barrier material110and the electrically insulating material112that isolates the conductive seed material114tand thermally conductive material116tof thermally conductive element125from the substrate102may impede heat transfer through the thermally conductive element125between adjacent semiconductor structures100.

A semiconductor structure200according to an embodiment of the disclosure and shown inFIG. 2may exhibit reduced wafer warpage and increased thermal conductivity relative to the semiconductor structure100ofFIG. 1.

Semiconductor structure200may comprise a substrate202in the form of a semiconductor substrate, a base semiconductor layer on a supporting structure, or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate202may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide.

At least one TSV206may electrically interconnect circuitry (e.g., active circuitry, integrated circuitry) from an active surface204of the semiconductor structure200to a back side230of the semiconductor structure200. The TSV206may extend from the active surface204of the substrate202to the back side230of the substrate202. The TSV206may include electrically conductive materials such as copper, aluminum, nickel, titanium, gold, tin, silver, indium, alloys thereof, or other suitable conductive material. In some embodiments, the TSV206includes copper. As used herein, the term “TSV” refers to an electrically and/or thermally conductive via structure that extends through any substrate202, which substrate202may include any of the materials described above. Thus, the TSV206may extend through materials other than, or in addition to, silicon, and the term “TSV” is not limited to structures extending only through silicon.

The TSV206may be insulated from the substrate202by a dielectric material208that may surround sidewalls of the TSV206. The dielectric material208may include, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), polyimide, tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or other dielectric materials.

An electrically conductive element215may be located over the back side230of the substrate202and electrically connected to active circuitry of the active surface204. The electrically conductive element215may extend over, or otherwise be connected to, the TSV206. The electrically conductive element215may be in electrical contact with the TSV206and may be electrically isolated from the substrate202. In some embodiments, the electrically conductive element215is directly over the TSV206. The electrically conductive element215may be configured as a discrete element in the form of, for example, a pad, which may also be characterized as a land, of a metal material or other electrically conductive material such as a conductive or conductor-filled epoxy. The electrically conductive element215may include an undersurface217that is substantially coplanar with a surface of the substrate202. For example, undersurface217of the electrically conductive element215may be substantially coplanar with the back side230of the substrate202.

The electrically conductive element215may extend laterally over at least a portion of an isolation structure205. The isolation structure205may surround a portion of the TSV206and may include an electrically insulating material212within a recess in the substrate202. The electrically insulating material212may be in contact with the electrically conductive element215. The isolation structure205may also include a barrier material210between the electrically insulating material212and the substrate202. A portion of the barrier material210may be located between the dielectric material208and the electrically insulating material212and at least a portion of the dielectric material208may be located between the TSV206and the electrically insulating material212. The barrier material210and the electrically insulating material212may not extend continuously over, or even overlie a majority of the back side230, but rather, may be a discrete structure associated with TSV206or a group (e.g., a plurality) of TSVs206, and recessed within the substrate202adjacent to the TSV206. In transverse cross-section, the isolation structure205may be shaped as a ring, an oval, a rectangle, a square, or other suitable shape extending around the TSV206. In other embodiments, the isolation structure205isolates a group of TSVs206from each other and from other TSVs206or groups of TSVs206. The isolation structure205may contact each TSV206of the group of TSVs206and may be continuous across the group of TSVs206isolated by the isolation structure205. In transverse cross-section, the isolation structure205may be shaped similar to the group of TSVs206isolated by the isolation structure205.

The electrically conductive element215may include a conductive seed material214and a conductive material216formed on the conductive seed material214. The conductive seed material214is in electrical communication with the TSV206and with the active surface204of the semiconductor structure200through the TSV206. The conductive seed material214may include a conductive material such as copper, nickel, cobalt, aluminum, titanium, palladium, silver, gold, tin, indium, and combinations thereof, such as an aluminum copper alloy or a titanium copper alloy. In some embodiments, the conductive seed material214includes a titanium copper alloy. The conductive seed material214may have a thickness between about 5 Å and about 500 Å, such as between about 5 Å and about 100 Å, between about 100 Å and about 250 Å, or between about 250 Å and about 500 Å.

The conductive material216may overlie the conductive seed material214. The conductive material216may be formed of copper, nickel, cobalt, aluminum, titanium, palladium, silver, gold, tin, indium, and combinations thereof. The conductive material216may have a thickness of between about 1,000 Å (0.1 μm) and about 40 μm, such as between about 0.1 μm and 5 μm, between about 5 μm and about 10 μm, between about 10 μm and about 20 μm, or between about 20 μm and about 40 μm. In some embodiments, the conductive material216and the conductive seed material214include the same material.

A central axis A-A of the TSV206is shown inFIG. 2. A portion of the isolation structure205may extend laterally a distance of D1from axis A-A. Electrically conductive element215may extend laterally a distance of D2from axis A-A. Distance D2may be equal to or less than distance D1such that the isolation structure205laterally extends substantially the same distance as, or further, from the TSV206than the electrically conductive element215. An outer portion of the dielectric material208may extend laterally a distance of D3from axis A-A. Distance D2may be greater than distance D3. Thus, the electrically conductive element215extends laterally beyond the dielectric material208surrounding TSV206, and at least a portion of the dielectric material208may be disposed laterally between the TSV206and the barrier material210and electrically insulating material212of the isolation structure205to electrically isolate the electrically conductive element215from the substrate202.

The semiconductor structure200may also include at least one then sally conductive element225which may be employed, in combination with a thermally conductive structure, such as a pillar or stud (not shown) to transfer heat between one semiconductor structure200and an adjacent semiconductor structure200(not shown) to remove heat from a 3D array of structures. The thermally conductive element225may be used as a thermal conductor only, and may not be configured to conduct electrical signals or power. In other words, the thermally conductive element225may not electrically connect to integrated circuitry of the semiconductor structure200, but may act only as a heat transfer conduit between adjacent semiconductor structures200in a stack of such structures. The thermally conductive element225may be in contact with the back side230of the substrate202and is electrically isolated from the electrically conductive element215. The thermally conductive element225may be in the form of, for example, a pad or land.

The thermally conductive element225may include a conductive seed material214tand a thermally conductive material216t, which may comprise the same materials as conductive seed material214and conductive material216, enabling simultaneous fabrication of thermally conductive element225and electrically conductive element215. The conductive seed material214tmay be located directly on the substrate202and may not be thermally isolated from the substrate202by an intervening thermally insulative material (e.g., silicon nitride, silicon dioxide, etc.).

Electrically conductive elements215and thermally conductive elements225may, in some embodiments, be substantially homogeneously distributed across the major surface (e.g., the back side230) of the semiconductor structure200. However, the thermally conductive elements225may also be non-homogeneously distributed, with the thermally conductive elements225placed in regions exhibiting greater heat generation during operation (e.g., regions referred to in the industry as “hot spots”). For example, a greater number of thermally conductive elements225may be formed in the hot spot regions of the semiconductor structure200than in other regions of the semiconductor structure200. The thermally conductive elements225may be of larger transverse cross-sectional surface area than the electrically conductive elements215. Thus, althoughFIG. 2depicts one thermally conductive element225per one electrically conductive element215, each semiconductor structure200may include more or fewer thermally conductive elements225than electrically conductive elements215depending on the heat load and desired heat transfer capacity through a die assembly including the semiconductor structures200.

A semiconductor structure comprises a conductive via extending from an active surface of a substrate to a back side of the substrate, a dielectric material on a sidewall of the conductive via, an isolation structure comprising an insulating material in a recess in the back side of the substrate and surrounding a portion of the conductive via, and a conductive material extending over and in contact with the conductive via and at least partially over the isolation structure in electrical isolation from the substrate.

A semiconductor structure comprises a substrate having active circuitry on a front side thereof, at least one conductive structure on a back side of the substrate and electrically connected to the active circuitry, an insulating material recessed within the back side of the substrate and in contact with the at least one conductive structure, and a thermally conductive element in contact with the back side of the substrate.

Referring toFIG. 3A, a method of forming a semiconductor structure200′ is shown. The semiconductor structure200′ includes a substrate202with completed active circuitry on an active surface204of the substrate202. The semiconductor structure200′ includes at least one TSV206electrically connected to at least a portion of the active circuitry on the active surface204. TSV206may be formed to extend from the active surface204of the substrate202to a back surface230of the substrate202. The TSV206may be electrically isolated from the substrate202by a dielectric material208. The TSV206and the dielectric material208may include any of the materials described above with reference to TSV206and dielectric material208ofFIG. 2, respectively.

The active surface204of the semiconductor structure200′ may be attached to a support wafer or other carrier (not shown) for processing of a back side230thereof. The support carrier may be adhered or otherwise attached to the active surface204of the semiconductor structure200′. In some embodiments, the TSV206may be formed partially through the substrate202from the active surface204thereof, after which the back side230of the semiconductor structure200′ may be thinned from, for example, an initial thickness of about 700 μm to expose a portion of the dielectric material208overlying TSV206as shown inFIG. 3A. In some embodiments the semiconductor structure200′ is thinned to a thickness of between about 20 μm and about 100 μm, such as between about 60 μm and about 80 μm, or between about 68 μm and about 72 μm. After thinning of the semiconductor structure200′, a portion of the dielectric material208over the TSV206may be exposed and extend beyond a surface of the substrate202.

Referring toFIG. 3B, a patterning material218may be formed over the back side230of the semiconductor structure200′. In some embodiments, the patterning material218is one of a positive photoresist and a negative photoresist. The patterning material218may be exposed to radiation (i.e., light) of an appropriate wavelength through a patterned mask and developed to form an opening220therein. The developer may include a solution including tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), xylene, or other suitable developer. In other embodiments, the opening220may be formed by laser ablation. The opening220may be centered over the TSV206and may expose a portion of the substrate202surrounding the dielectric material208. The opening220may be sized and configured for use in forming recesses in which the isolation structure205ofFIG. 2will be formed. In some embodiments, an opening220is formed around each TSV206and an isolation structure205is subsequently formed around each TSV206, each isolation structure205and corresponding TSV206isolated from other isolation structures205and TSVs206. In other embodiments, an opening220is formed over a group of TSVs206and an isolation structure205is subsequently formed around the group of TSVs206.

Referring toFIG. 3C, an exposed portion of the substrate202surrounding the dielectric material208may be removed to form a recess220ain the back side230and around a portion of the TSV206. The recess220amay laterally isolate a segment of each TSV206from the surrounding substrate202and from adjacent TSVs206. In other embodiments, the recess220amay be formed adjacent a group of TSVs206to separate the group of TSVs206from the substrate202and from other TSVs206or groups of TSVs206. Thus, although each recess220ais described herein as surrounding a TSV206, each recess220amay surround one or more TSVs206, or at least some of the recesses220amay surround a group of TSVs206while other recesses220asurround only a single TSV206. The recess220amay be of sufficient size to electrically isolate the TSV206and any conductive materials that will subsequently be formed over the TSV206from the substrate202. For example, the recess220amay extend from the back side230into the substrate202a depth between about 1 μm and about 10 μm, such as between about 1 μm and about 2 μm, between about 2 μm and about 4 μm, between about 4 μm and about 6 μm, or between about 6 μm and about 10 μm. The recess220amay extend laterally beyond the dielectric material208on each side of the TSV206. In transverse cross-section, the recess220amay have a circular, oval, rectangular, square, or any other suitable shape.

The material of the substrate202may be anisotropically etched to form the recess220a. The material of the substrate202may be removed by dry or wet etching. The etchant may be selective to the material of the substrate202(e.g., silicon) relative to the dielectric material208. The etchant may remove the material of the substrate202but may not substantially remove the dielectric material208. The etchant may include dry etchants such as CF4, SF6, NF3, Cl2, CCl2F2, combinations thereof, or other suitable etchants for removing the material of the substrate202. In some embodiments, the material of the substrate202is removed by a dry reactive ion etch (RIE). In other embodiments, the etchant may be a wet etchant, such as a solution including nitric acid and hydrofluoric acid, potassium hydroxide, ethylenediamine pyrocatechol (EDP), TMAH, or combinations thereof.

The recess220amay be defined by substantially straight sidewalls, oriented perpendicular to a major plane of substrate202. An outer sidewall of recess220amay be defined by the substrate202and an inner sidewall may be defined by the dielectric material208. During the formation of recess220a, the dielectric material208may remain over the TSV206. In some embodiments, the dielectric material208protects the underlying conductive material of TSV206from reacting with or being removed by the etchants during formation of recess220a. By way of example only, where the TSV206includes copper, the dielectric material208may prevent the formation of copper silicide over the TSV206.

With continued reference toFIG. 3C, the patterning material218(FIG. 3B) may be removed after forming the recess220a. The patterning material218may be removed with dry etchants, such as with a plasma including hydrogen, oxygen, nitrogen, argon, CF4, SF6, CHClF2, or combinations thereof. In other embodiments, the patterning material218may be wet stripped with a stripping agent including an alkaline solution (KOH, NaOH, etc.), dimethyl sulfoxide (DMSO), sulfuric acid (H2SO4), and an oxidant such as ammonium persulfate ((NH4)2S2O8).

Referring toFIG. 3D, a barrier material210may, optionally, be formed within the recess220aand over the back side230. The barrier material210may include a nitride, such as silicon nitride. The barrier material210may be formed by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), or other suitable deposition method. In some embodiments, the deposition may be a low temperature deposition process, such as a low temperature CVD carried out at temperatures between about 150° C. and about 200° C. The barrier material210may be formed such that the barrier material210exhibits good step coverage (e.g., is conformally formed) in recess220aand across the TSV206and the back side230. The barrier material210may be a diffusion barrier and substantially prevent diffusion of a conductive material (e.g., a material of electrically conductive element215(FIG. 2)) into the substrate202.

A substantial portion of recess220amay remain open after forming the barrier material210. The barrier material210may have a thickness such that the barrier material210does not completely fill recess220a(FIG. 3C), leaving an opening within the recess220a. The barrier material210may be formed to a thickness between about 100 Å and about 20,000 Å (2 μm), such as between about 100 Å and about 1,000 Å, between about 1,000 Å and about 5,000 Å, or between about 5,000 Å and about 20,000 Å. In some embodiments, the barrier material210is formed to a thickness of about 1,000 Å.

An electrically insulating material212may be formed over the barrier material210and over the back side230. The electrically insulating material212may include silicon dioxide, silicon nitride, a silicon oxynitride, tetraethyl orthosilicate (TEOS), a spin-on dielectric material, or other suitable electrically insulative material. The electrically insulating material212may fill the remainder of the recess220a(FIG. 3C) not filled by the barrier material210. In some embodiments, up to about 40,000 Å (4 μm) of the electrically insulating material212is fanned over the barrier material210. The electrically insulating material212may be formed by similar methods as the barrier material210. For example, the electrically insulating material212may be formed by one of ALD, CVD, PECVD, LPCVD, PVD, or other suitable deposition method. In some embodiments, the electrically insulating material212may be formed by a low temperature CVD process. The electrically insulating material212may exhibit good step coverage over the barrier material210. The electrically insulating material212may be formed to a thickness greater than a thickness of the barrier material210.

Referring toFIG. 3E, an isolation structure205may be formed by removing the electrically insulating material212and the barrier material210from the back side230. A portion of the back side230may be exposed, while leaving the electrically insulating material212and the barrier material210within the recess220a(FIG. 3C). In some embodiments, the electrically insulating material212and the barrier material210are removed from the back side230by chemical-mechanical planarization (CMP). The same CMP process may be used to simultaneously remove a portion of the dielectric material208over the TSV206and expose a conductive portion of the TSV206. After removing the electrically insulating material212and the barrier material210from the back side230, the electrically insulating material212and the barrier material210may remain within the recess220a(FIG. 3C) to form the isolation structure205. After the CMP process, the isolation structure205may have exposed surfaces that are coplanar with the back side230of the substrate202.

Referring toFIG. 3F, a conductive seed material214may be formed over the back side230, exposed portions of the barrier material210, the electrically insulating material212, the dielectric material208, and the TSV206. The conductive seed material214may have a thickness of between 5 Å and about 500 Å. The conductive seed material214may be formed by ALD, CVD, PECVD, LPCVD, PVD, or other suitable deposition method. In some embodiments, the conductive seed material214is formed by PVD. The conductive seed material214may include copper, nickel, cobalt, aluminum, titanium, palladium, silver, gold, tin, indium, and combinations thereof. In some embodiments, the conductive seed material214includes an alloy of copper and titanium.

Referring toFIG. 3G, a patterning material222may be formed over the conductive seed material214. The patterning material222may include the same materials as the patterning material218(FIG. 3B). Openings224,226may be formed through the patterning material222. The openings224,226may be formed by similar photolithographic methods as described above with reference to opening220formed in patterning material218inFIG. 3B.

Opening224may be formed over a portion of the conductive seed material214over the TSV206and may extend laterally from TSV206over at least a portion of the electrically insulating material212of the isolation structure205. Opening226may be formed over the conductive seed material214at a location laterally removed from the TSV206. Opening226may expose a portion of the conductive seed material214located over the substrate202.

Referring toFIG. 3H, a conductive material216and a thermally conductive material216tmay be formed through openings224,226and over conductive seed material214in the form of so-called “under bump metallization” pads. Conductive material216and thermally conductive material216t, which may comprise the same conductive material, may be formed by electroplating, CVD, PVD, or other suitable method. In some embodiments, the conductive material216and the thermally conductive material216tare formed by electroplating. The conductive material216and the thermally conductive material216tmay include copper, nickel, cobalt, aluminum, titanium, palladium, silver, gold, tin, indium, and combinations thereof. In some embodiments, the conductive material216and the thermally conductive material216tinclude the same material as the conductive seed material214. The conductive material216and the thermally conductive material216tmay each have a thickness of between about 5 μm and about 40 μm, such as between about 5 μm and about 10 μm, between about 10 μm and about 20 μm, or between about 20 μm and about 40 μm.

Referring toFIG. 3I, the patterning material222(FIG. 3H) may be removed from the back side230, the electrically insulating material212, the barrier material210, and the TSV206. The patterning material222may be removed by similar methods as described above with reference to the removal of patterning material218inFIG. 3C.

The semiconductor structure200′ may include one or more TSVs206with an electrically conductive structure215formed from the conductive seed material214and the conductive material216. The electrically conductive structure215may be electrically connected to active circuitry of the active surface204of the semiconductor structure200′ via the TSV206. However, the electrically conductive structure215may remain electrically isolated from the substrate202by the dielectric material208and the isolation structure205. Although there is not a continuous electrically insulative material across the back side230of the substrate202, the electrically conductive structure215may be electrically isolated from the substrate202due to the presence of the isolation structure205.

As noted above, semiconductor structure200′ may also include a thermally conductive element225including a conductive seed material214tand the thermally conductive material216t. Thermally conductive element225may be structured the same as, or differently than, the electrically conductive element215. The thermally conductive element225may be electrically isolated from the TSV206and may be in contact with the substrate202. Thus, thermally conductive element225may be in thermal communication with the substrate202without an electrically intervening insulative material which would otherwise impede heat transfer between the thermally conductive element225and the substrate202.

In some embodiments, it may be desirable to form an isolation material over exposed portions of the back side230of the substrate202between and around the thermally conductive element225and the electrically conductive element215. In some embodiments, a passivation material240(shown in broken lines) may be formed over the back side230and an isolation material242(shown in broken lines) may be formed over the passivation material240. The passivation material240may include the same or similar materials as barrier material210. The isolation material242may include the same or similar materials as electrically insulating material212. The passivation material240and the isolation material242may be formed by one of ALD, CVD, PECVD, LPCVD, PVD, or other suitable deposition method. The passivation material240and the isolation material242may be removed from surfaces of the electrically conductive element215and the thermally conductive element225to expose portions of each of the electrically conductive element215and the thermally conductive element225.

A method of forming a semiconductor structure comprises forming at least one conductive via extending from an active surface of a substrate to a back surface of the substrate, forming a recess within the back surface of the substrate adjacent the at least one conductive via, forming an insulating material over the back surface and within the recess, removing the insulating material from the back surface while leaving the insulating material within the recess, and forming a conductive element over and in contact with the at least one conductive via and the insulating material.

Referring toFIG. 4A, a die assembly may include a stack250of semiconductor structures200a,200b,200c, etc., in the form of, for example, singulated semiconductor dice. The semiconductor structures200a,200b,200cmay be similar to semiconductor structure200described above with reference toFIG. 2and may be in the form of semiconductor dice. The stack250may be formed by bonding an active surface204of one semiconductor structure200a,200b,200cto a back side230of an adjacent semiconductor structure200a,200b,200c. Electrically conductive elements215may interconnect TSVs206and integrated circuits of the semiconductor structures200a,200b,200c. For example, electrically conductive elements215of one semiconductor structure200a,200b,200cmay be electrically connected through a reflowed solder material234on conductive pillars232of an adjacent semiconductor structure200a,200b,200c. The conductive pillars232may be formed of a suitable conductive material, such as copper, nickel, titanium, tantalum, tungsten, molybdenum, titanium nitride, titanium tungsten (TiW), tantalum nitride, and combinations thereof. In some embodiments, the conductive pillars232are formed of the same material as the TSV206and comprise an integral structure with TSV206. The solder material234may be formed over the conductive pillars232and reflowed in a thermocompression bonding process to physically and electrically connect to electrically conductive elements215. The solder material234may include an Sn/Ag or an Sn/Pb solder material. In some embodiments, a barrier material including nickel (not shown) may be disposed between the material of conductive pillars232and the solder material234. However, the present disclosure is not limited to such examples of electrically connecting an active surface204of one semiconductor structure200a,200b,200cto a back side230of an adjacent semiconductor structure200a,200b,200c. Rather, the active surface204of one semiconductor structure200a,200b,200cmay be electrically connected to the back side230of an adjacent structure200a,200b,200cby any sufficiently conductive material or a combination thereof and have any suitable structural form to electrically connect adjacent semiconductor structures200a,200b,200c.

As described previously, a dielectric material208may surround at least a portion of each of the TSVs206and isolation structures205may be disposed within a substrate202of each semiconductor structure200a,200b,200cin the stack250. The isolation structures205may contact at least a portion of the dielectric material208surrounding each of the TSVs206.

The stack250may include thermally conductive elements225between adjacent semiconductor structures200a,200b,200c. The thermally conductive elements225may contact a substrate202of each of adjacent semiconductor structures200a,200b,200c, but may not electrically connect to integrated circuitry of the semiconductor structures200a,200b,200cand may act only as heat transfer conduits between respective semiconductor structures200a,200b,200cof stack250. A solder material234, reflowed during a thermocompression bonding process used to electrically connect semiconductor structures200a,200b,200cmay connect thermally conductive elements225to thermally conductive pillars232tprotruding from an adjacent semiconductor structure200. The thermally conductive element225may include the same or similar materials as electrically conductive elements215. The thermally conductive elements225of semiconductor structure200cmay be in thermal communication with a heat spreader, a heat dissipation structure, or other device suitable for dissipating heat from the stack250.

In some embodiments, an optional thermal transfer material236(shown in broken lines) may be located between the thermally conductive pillars232tand the substrate202on which they are located. The thermal transfer material236may include a material that is electrically insulative and thermally conductive. In some embodiments, the thermal transfer material236is a thermal interface material (TIM) and may comprise an adhesive, an elastomer, a thermal pad, or a phase change TIM. In other embodiments, the thermal transfer material236includes a dielectric material with a high thermal conductivity, such as a polymer or prepolymer material exhibiting a low dielectric constant and a relatively high thermal conductivity.

A dielectric underfill material228may be employed to fill regions between adjacent semiconductor structures200a,200b,200cof the stack250. The underfill material228may fill regions between and surrounding electrical and thermal connections between adjacent semiconductor structures200a,200b,200cof the stack250. The dielectric underfill material228may have a relatively high thermal conductivity (e.g., high k) so as to not impede heat transfer between adjacent structures. The dielectric underfill material228may include one or more of a polymer material, a prepolymer material, a polyimide material, a silicone material (e.g., an organopolysiloxane material), an epoxy material, a resin material (e.g., a thermal plastic resin material), a curing agent (i.e., a hardener), a catalyst (i.e., an accelerator), a filler material (e.g., silica, alumina, boron nitride, etc.), a fluxing agent, a coupling agent, and a surfactant. The dielectric underfill material228may comprise a capillary underfill, a pre-applied non-conductive paste, a non-conductive film, a wafer-level underfill (WLUF), or a molded underfill.

Referring toFIG. 4B, another embodiment of a die assembly including a stack250′ of semiconductor structures200a′,200b′,200c′ is shown. The semiconductor structures200a′,200b′,200c′ may be similar to semiconductor structure200a,200b,200cdescribed above with reference toFIG. 4A. As with stack250, stack250′ includes thermally conductive elements225connected to thermally conductive pillars232tby a solder material234extending between adjacent semiconductor structures200a′,200b′,200c′. However, unlike the semiconductor structures200a,200b,200cof stack250, thermally conductive elements225may be in contact with thermal TSVs206twhich extend through the substrate202of each of the semiconductor structures200a′,200b′,200c′. Consequently, a continuous heat transfer path is provided through thermally conductive elements225, thermal TSVs206t, thermally conductive pillars232t, and solder material234. An isolation material208′ may be formed around the thermal TSVs206+ of the thermally conductive elements225to electrically isolate the heat transfer path from substrates202and integrated circuitry on active surfaces204. The isolation material208′ may include a dielectric material similar to dielectric material208, as well as a barrier material, similar to barrier material210.

The thermally conductive elements225of semiconductor structure200c′ may be in thermal communication with a heat spreader, a heat dissipation structure, or other device suitable for dissipating heat from the stack250′.

A semiconductor die assembly comprises a stack of semiconductor dice, conductive structures in contact with conductive vias extending through substrates of the semiconductor dice in the stack, the conductive structures extending between semiconductor dice in the stack, dielectric material surrounding at least a portion of each of the conductive vias, isolation structures within the substrates of semiconductor dice in the stack, the isolation structures surrounding one or more of the conductive vias adjacent a substrate surface and in contact with a portion of the dielectric material surrounding each of the conductive vias, conductive elements over the substrate surface in contact with the conductive vias and the conductive structures and extending at least partially over the isolation structures, and at least one thermally conductive structure extending from a semiconductor die in the stack in contact with a thermally conductive element on a same substrate surface of an adjacent semiconductor die in the stack as the conductive elements of the adjacent semiconductor die.

A method of forming a semiconductor die assembly comprises forming recessed isolation structures each surrounding one or more conductive vias in a back side of each of a plurality of semiconductor dice, forming conductive elements in contact with the conductive vias and over the recessed isolation structures, forming thermally conductive elements over the back sides of at least some of the semiconductor dice of the plurality of semiconductor dice, and stacking the plurality of semiconductor dice such that a conductive element of one semiconductor die of the plurality of semiconductor dice contacts a conductive structure protruding from an adjacent semiconductor die of the plurality of semiconductor dice.

Accordingly, semiconductor structures and die assemblies are disclosed. Thermal flow through semiconductor structures may be increased and wafer warpage of semiconductor structures may be decreased by limiting dielectric and insulative materials around conductive structures of the semiconductor structures. For example, by limiting dielectric and insulative materials to a finite area surrounding conductive materials such as conductive vias, bond pads, bond plates, lands, etc., oxide-induced stresses that cause wafer warpage and thermally insulative materials that reduce heat transfer through semiconductor structures may be reduced. Thus, semiconductor structures and die assemblies without a continuous dielectric material across surfaces thereof (e.g., back surfaces) may have increased thermal transfer and reduced oxide-induced stresses.