Bidirectional register segmented data busing

Bidirectional register segmented data busing and addressing for such busing is described. A segmented databus includes data register segments coupled to one another via respective databus segments. Bidirectional drivers are coupled between the data register segments and the databus segments associated therewith. The bidirectional drivers are configurable for driving information along the segmented databus, wherein the databus segments are for both read and write busing.

FIELD OF THE INVENTION

One or more aspects of the invention relate generally to integrated circuits and, more particularly, to a bidirectional register segmented databus and an address bus therefore.

BACKGROUND OF THE INVENTION

One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3–75 through 3–96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Young et al. further describe the interconnect structure of the Virtex FPGA in U.S. Pat. No. 5,914,616 B1, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”.

Another such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. And yet another such FPGA, the Xilinx Virtex-II Pro™ FPGA, is described in detail in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For purposes of clarity, FPGAs are described below though other types of PLDs may be used.

Heretofore, unidirectional segmented data busing was employed in FPGAs. However, this meant that two separate buses for reading and writing were used. This consumes a significant amount of semiconductor area. Accordingly, it would be desirable and useful to provide segmented data busing that uses less busing resources.

SUMMARY OF THE INVENTION

One or more aspects of the invention generally relate to integrated circuits and more particularly, to a bidirectional register segmented databus and an address bus therefore. An aspect of the invention is a segmented databus which includes data register segments coupled to one another via respective databus segments. Bidirectional drivers are coupled between the data register segments and the databus segments associated therewith. The bidirectional drivers are configurable for driving information along the segmented databus, wherein the databus segments are for both read and write busing.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items, however, in alternative embodiments the items may be different.

FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)101, configurable logic blocks (“CLBs”)102, random access memory blocks (“BRAMs”)103, input/output blocks (“IOBs”)104, configuration and clocking logic (“CONFIG/CLOCKS”)105, digital signal processing blocks (“DSPs”)106, specialized input/output ports (“I/O”)107(e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)110. FPGA100may be used to implement system100ofFIG. 1.

In some FPGAs, each programmable tile includes a programmable interconnect element (“INT”)111having standardized connections to and from a corresponding interconnect element111in each adjacent tile. Therefore, the programmable interconnect elements111taken together implement the programmable interconnect structure for the illustrated FPGA. Each programmable interconnect element111also includes the connections to and from any other programmable logic element(s) within the same tile, as shown by the examples included at the right side ofFIG. 1.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, I/O, clock, and other control logic. Areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block110shown inFIG. 1spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. The numbers of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the right side ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic. Additional details regarding a columnar architected FPGA may be found in a co-pending patent application, namely, U.S. patent application Ser. No. 10/683,944, entitled “Columnar Architecture” by Steve P. Young, filed Oct. 10, 2003, which is incorporated by reference herein in its entirety.

FPGA100illustratively represents a columnar architecture, though FPGAs of other architectures, such as ring architectures for example, may be used. Moreover, it should be understood thatFIG. 1may be associated with a logic plane of FPGA100, and that there is another plane, namely a configuration plane, of FPGA100.

FIG. 2Ais a simplified block diagram depicting an exemplary embodiment of a frame arrangement for a configuration plane200of an FPGA100. Configuration plane200includes rows221through226, configuration memory frames (“frames”)214through219, bidirectional drivers232through235, configuration center control logic211, frame data register (“FDR”)210, shadow register229, row address decoder228, and column address decoder212. In this exemplary embodiment of configuration plane200, a centralized column address decoder212is illustratively shown.

InFIG. 2B, there is shown a simplified block diagram depicting an alternate exemplary embodiment of configuration plane200ofFIG. 2A. In this exemplary embodiment of configuration plane200, column address decoder212ofFIG. 2Ais decentralized into respective sections for each row221through226. For example, to the right of FDR210are column address decoders241through246respectively for rows226through221and to the left of FDR210are column address decoders251through256respectively for rows226through221.

Continuing the embodiment of segmentation by rows for column address decoding,FIG. 2Cis a simplified diagram of part of an exemplary embodiment of a configuration structure for a PLD310. The configuration structure includes part of a two-dimensional configuration memory array of configurable memory cells. The memory array arranged in a series of columns371,372,374,376,378, and380and a series of rows350,352,354,356,358,360,362, and364. Each column includes one or more sub-columns of memory cells, where a sub-column stores a fixed frame of configuration data and has a minor address. The column has a major address. Hence the column address for a fixed frame may include a column type, major address, and minor address as in conventional FPGAs. Further description of major and minor column addressing is found in Xilinx Application Note, entitled “Virtex Series Configuration Architecture User Guide” from Xilinx, Inc. of San Jose, Calif., XAPP151, Mar. 24, 2003. Interposed between the columns371through380are dataline drivers or repeater circuits382,384,386, and388.

Each of the rows350through364includes FDRs (“FDR1” through “FDR8”)314,316,318,320,322,324,326, and328, collectively labeled FDR312, and distributed column address decoder/HCLK rows330,332,334,336,338,340,342, and344, respectively. For example, to configure column371in row352, bit stream data is first sent to FDR2316(serially or in parallel or a combination thereof) from the configuration center (not shown). Next, the data in FDR2316is transferred to the configuration memory cells in column371in row352. The dataline drivers in columns382and384will restore the digital bit stream data as it moves across row352from FDR2316to column371. For reading back the configuration memory cell data in column371of row352, the data is sent back in parallel to FDR2316from column371of row352and then read (serially or in parallel or a combination thereof) from FDR2316to the configuration center (not shown).

FIG. 2Dis a detailed diagram of part of an exemplary embodiment of row352ofFIG. 2C. A portion of columns376and378of row352are shown in more detail. Column376of row352may include a first block of configuration memory cells for eight Configuration Logic Blocks (“CLBs”)390, an HCLK block391, and eight more CLBs392. Similarly, column378of row352may include a second block of configuration memory cells for eight CLBs394, an HCLK block395, and eight more CLBs396. CLBs are well-known and are described in the Virtex-II Pro Platform FPGA Handbook by Xilinx, Inc. of San Jose, Calif., October 2002. HCLK blocks391and395and HCLK row332are described in co-pending U.S. patent application Ser. No. 10/836,722 entitled “A Differential Clock Tree in an Integrated Circuit” by Vasisht M. Vadi, et. al, filed Apr. 30, 2004. In one example, the 16 CLBs are programmed by 40 words of configuration data. At 32 bits per word, there are 1280 configuration memory cells. In this example, HCLK blocks391and395each have 16 memory cells. FDR2316has 41 words (at 32 bits per word) or 1312 bits for a fixed frame, which includes 32 bits for the HCLK block even though only 16 bits are used.

FIG. 2Eshows a more detailed block diagram435of a part of an exemplary embodiment of row352coupled to FDR2316. Notably, shadow registers, described elsewhere herein, may be coupled between FDR2316and row control circuit428. Block diagram435shows a memory array410, a distributed column address decoder/HCLK circuit (“address decoder”)420, and row control circuit428having a read/write control circuit436. For some embodiments, the memory cells are SRAM cells, although other memory cells, both volatile and/or non-volatile (one time or many time programmable) can be used.

With reference toFIGS. 2C,2D, and2E, block diagram435shows the top half of row352, where address decoder420corresponds to HCLK row332, row segments415(1) and415(2) correspond to CLBs390and394, respectively, and dataline (“DL”) drivers414(1) and414(2) correspond to parts of dataline driver columns386and388, respectively. Memory array410has sub-rows of row352, where each sub-row is connected to read/write control circuit436via a corresponding dataline pair DL, and each column in memory array410is connected to address decoder420via a corresponding address line AL. Address decoder420is well-known, and includes circuitry to select one of address lines AL in response to an address provided on an address bus ABUS. Read/write control circuit436controls read, write, and test operations for memory array410, and is coupled to a data bus DBUS and to a control bus CBUS. DBUS provides write configuration data from FDR2316, or its corresponding shadow register, to memory array410and routes read configuration data from memory array410to FDR2316, or its corresponding shadow register, via row control circuit428, which includes read/write control circuit436. CBUS provides various control signals to read/write control circuit436.

CBUS includes control signals such as a power-on reset signal POR, a pre-charge signal PCH, a pre-discharge signal PDCH, a test signal TEST, and a write control signal WR. Further details on these CBUS signals are described in co-pending, commonly assigned U.S. patent application Ser. No. 10/796,750 entitled “Segmented Dataline Scheme in a Memory with Enhanced Full Fault Coverage Memory Cell Testability,” by Vasisht M. Vadi, et al., filed Mar. 8, 2004, which is herein incorporated by reference.

Row circuit428gates (via AND gates) PCH, PDCH, TEST, and WR with a bit of the row address (row_addr) signal (not shown) before these signals go to control circuit436. The row address signal is produced by the configuration logic in the configuration center and is the address of the row the fixed frame(s) are written to. In one embodiment the row_addr signals are a one-hot signal similar to, but different from, the fdr_addr signal. Thus, when row_addr is asserted for a row, reads to and writes from one or more columns in the row are allowed, i.e., the control signals PCH, PDCH, TEST, and WR are allowed to pass through the one or more AND gates.

As illustrated inFIG. 2E, the sub-rows of memory array410are divided into a plurality of row segments415(1)–415(n), each of which can include any suitable number of memory cells. For some embodiments, the row segments include the same number of memory cells, while in other embodiments the row segments include different numbers of memory cells. Each row segment415(1) through415(n) includes an associated dataline segment to which the memory cells therein are connected. For simplicity, the dataline segments are not shown inFIG. 2E. Dataline drivers414(1) through414(n−1) are provided to selectively buffer signals between dataline segments in adjacent row segments415in response to read and write control signals. During write operations, dataline drivers414propagate write data in a first direction from read/write control circuit436along adjacent dataline segments to selected memory cells, while during read operations dataline drivers414propagate read data in a second direction from selected memory cells along adjacent dataline segments to read/write control circuit436. In particular, using dataline drivers414rather than duplicating read/write control circuit436to drive the segments requires less area. Further details are described in co-pending, commonly assigned U.S. patent application Ser. No. 10/796,750 filed Mar. 8, 2004 entitled “Segmented Dataline Scheme in a Memory with Enhanced Full Fault Coverage Memory Cell Testability,” by Vasisht M. Vadi, et al., which is herein incorporated by reference.

Additional details regarding the embodiments illustratively shown inFIGS. 2C,2D, and2E may be found in a co-pending application entitled “A Method and System for Configuring an Integrated Circuit,” by Vasisht M. Vadi, et al., assigned application Ser. No. 10/970,964, filed Oct. 22, 2004, which is incorporated by reference herein in its entirety.

With renewed reference toFIGS. 2A and 2B, configuration plane200is further described inFIG. 3A, which is a simplified block diagram depicting an exemplary embodiment of a bidirectional segmented FDR databus300of configuration plane200. Control logic377, which in this embodiment may be configuration center logic211, is coupled to FDR segments301through305of FDR210ofFIG. 2Aor2B. Control logic377is coupled to FDR segments301through305via respective segmented databus sections370-1through370-4, hereinafter collectively and singly referred to as segmented databus370. Though in this example there are five FDR segments, it should be appreciated that fewer or more FDR segments may be used. FDR segments301through305are respectively associated with rows351-1through351-5, which may be rows221through226, respectively. In this embodiment, segmented databus370is 32 bits wide. Of course, the width of segmented databus370may be fewer or more than 32 bits. It should be appreciated that segmented databus370is both a read and a write bus. Thus, having separate read and write buses is avoided.

Having a unified read/write bus for segmented databus370, which may be fewer or more than 32 bits wide, is facilitated by bidirectional drivers323-1through323-8. For example, FDR segment301has bidirectional drivers323-4, namely a bidirectional driver for each databus line, coupled to segmented databus370-1on a side coupled to control logic377and has bidirectional drivers323-5coupled to segmented databus370-2on a side coupled to FDR segment302. In this example, each FDR segment301through305includes at least one set of bidirectional drivers coupled to a section of segmented databus370.

For a write operation, control logic377provides information to segmented databus370. In this example, write data is initially provided from control logic377to section370-1of segmented databus370for distribution to FDR segments301and304. For the chain of FDR segments301through303, write data is distributed up the chain of FDR segments, as indicated by arrows470, in part via sections370-2and370-3of segmented databus370. For the chain of FDR segments304through305, write data is distributed up the chain of FDR segments, as indicated by arrows471, in part via section370-4of segmented databus370. It should be noted that for each row351-1through351-5, information is propagated away from a central location373associated with where control logic377is coupled to section370-1of bidirectional segmented databus370. Write data is propagated up and down the chain or chains of FDR segments, where propagation in each direction is away from control logic377.

Notably, write data may be written to FDR210for writing to a frame, for example frame214. A frame may include an array of configuration random access memory (“RAM”) cells. During a conventional write operation, write data is loaded into FDR210for writing in massive parallel to a frame, for example frame214. In an embodiment of an FPGA100, a frame may be 1312 rows by 1 column of configuration RAM cells thus capable of storing 1312 bits. Frame length depends on configuration of FPGA100. Notably, frames may be any of a variety of lengths, including less than 1000 bits, from 1000 bits to 10,000 bits, and over 10,000 bits. However, as noted above, for a segmented FDR210, each FDR segment301through305is associated with a respective row351-1through351-5. Each row351-1through351-5is associated with a portion of the rows of a frame for single column frame architecture. Thus, for example, FDR segment301is associated with a respective portion of each frame associated with row351-1. Assuming a single column frame architecture, a column address may be used to select a frame, a row address may be used to select a portion of the rows of the frame, and an FDR address may be used to select an FDR segment to write or read information to or from the selected portion of the rows of the frame. Thus, for example, a row address signal230may be provided from configuration center control logic211to row address decoder228to select a row of rows221through226, and an FDR address signal220may be provided to FDR210to select an FDR segment. A column address signal (not shown) may be provided to column address decoder212, or to a column address decoder associated with the selected row and frame of column address decoders241through246and251through256. Alternatively, multiple frames, for example frames214through216, associated with a row, for example row226, may be written to or read from an associated FDR segment. Shadow register229may be used to facilitate use of FDR210while reading data from or writing data to one or more frames. Notably, shadow register229, which may be implemented with flip-flops, may be segmented and addressed like FDR segments and thus may be responsive to FDR address signaling220.

Continuing the above example, a write may be done in 1312 bit parallel for FDR210fully loaded with write data, though such write data is shifted into FDR21032 bits at a time from control logic377and provided to respective FDR segments responsive to addressing. The bit width for communication between an FDR segment and a frame will be less than the total frame length of 1312. Thus, for example, a frame length may be evenly or unevenly divided among the FDR segments. Moreover, rather than a massive parallel transfer of data from FDR210to shadow register229and then to a frame, such as frame214, multiple parallel transfers may be made from one or more FDR segments to one or more frames, such as frames214,215, and216, for a block of configuration data stored across more than one frame. The reverse direction of a write operation is used for a read operation. For purposes of clarity, additional details regarding operation of FPGA100are omitted.

With continuing reference toFIGS. 2A and 2b,FIG. 3Bis a simplified block diagram depicting an exemplary embodiment of the bidirectional segmented FDR databus300of configuration plane200ofFIG. 3Afor a read operation. In this embodiment, row351-2has been selected for a read operation for purposes of explanation and not limitation, as any row may be selected for readback of one or more frames associated therewith. Accordingly, FDR segment302having received configuration data, such as from a selected frame of frames214through219, will be read back to control logic377. Notably, it should be appreciated that for FDR segments303,304, and305, information read is propagated away from central location373or more generally away from control logic377, as indicated by arrows472. However, for the selected row351-2, FDR segment302propagates information toward control logic377as indicated by arrow473.

Read data, such as from rows of a frame, is registered in FDR segment302. Read data in FDR segment302is propagated along bidirectional databus section370-2of segmented databus370to FDR segment301, as indicated by arrow473. This read data is propagated from FDR segment301to control logic377via section370-1of segmented databus370, as indicated by arrow474. In this manner, data from a selected row may be read back via a selected FDR segment to control logic377, including each intervening FDR segment therebetween. In this example, FDR segments303through305are in a same state as for a write operation, where arrows472indicate propagation of information away from control logic377up and down the FDR segmented chain. In contrast, FDR segments301and302are in a state for a read operation. Thus, bidirectionality of segmented databus370using bidirectional/tristateable drivers facilitates using the same busing for both read and write operations. As used herein, the term “tristate” and variations thereof are used to mean a sufficiently high impedance state to prevent data from being communicated.

FIG. 4is a block/schematic diagram depicting an exemplary embodiment of an address bus400for selecting configuration state of an FDR segment, such as for either a read or a write operation. Notably, though three FDR segments301through303are illustratively shown, it should be appreciated that fewer or more FDR segments may be used. Furthermore, though only an upper portion of a segmented FDR, such as ofFIGS. 3A and 3B, is illustratively shown inFIG. 4, it should be appreciated that the following description equally applies to the bottom portion of such segmented FDR ofFIGS. 3A and 3B. Moreover, address lines401through403are referred to as the position for contacts, as indicated by respective dashed boxes497through499within address bus400, though such address lines may be rotated or shifted out, as described below.

For three FDR segments301through303, each FDR segment has three contact lines associated with it for input to control logic. In this example, FDR segment301has contact lines441through443for input to OR gate411; FDR segment302has contact lines451through453for input to OR gate412; and FDR segment303has contact lines461through463for input to OR gate413. These contact lines have an order, such as 0 through 2. Notably, there is a one-to-one correspondence between contact lines and FDR segments.

In this exemplary embodiment, an initial FDR segment301has none of its address lines401through403coupled to ground. However, each FDR segment in a chain removed from control logic377by at least one FDR segment has at least one FDR segment address line coupled to ground. In this exemplary embodiment, the most significant bit (“MSB”) of each FDR segment beyond a first FDR segment in a chain, such as FDR segment301in this example, is coupled to ground430.

Address lines401through403are respectively coupled to FDR segment301contact lines441through443. Address lines are shifted one position to the left for each subsequent FDR segment after FDR segment301. Thus, for example, FDR segment302contact lines451through453are respectively coupled to address lines402through404, where address line402is shifted into the position of address line401, address line403is shifted into the position of address line402, and an address line404in initiated to substitute for address line401, the latter of which is shifted out. This initiation of address line404is in effect a rotation of positions497through499with respect to initial positions of address lines401through403, where a new address line coupled to a fixed logic value is initiated. The newly initiated address line404is in this example coupled to ground430. FDR segment302contact line453is thus coupled to ground430.

Continuing the example, FDR segment303contact lines461through463are respectively coupled to address lines403through405, where address line403is shifted into the original position of address line401, address line404is shifted into the original position of address line402, and an address line405is initiated to substitute for address line402, which is shifted out. This initiation of address line405is in effect a rotation of positions497through499serially for this FDR segment progression, where a new address line coupled to a fixed logic value is initiated. The newly initiated address line405is in this example coupled to ground430. FDR segment303contact line463is thus coupled to ground430. It should be appreciated that subsequent address lines may be shifted and added/rotated in like manner. Notably, the address lines need not be physically shifted as indicated, but merely be coupled to a different order of contact line.

With address bus400, bidirectional driver configuration for either a read or a write operation is responsive to a row address, such as a row address for a row of rows351-1through351-3. For example, for a read operation for a read of FDR segment302, an FDR segment address may be output from control logic377, such as on: address line401as a logic low level; address line402as a logic high level; and address line403as a logic low level. Output421of OR gate411will be a logic high responsive to the logic high level on address line402coupled to contact line442, where contact lines441and443are respectively coupled to the logic low levels on address lines401and403. Output422of OR gate412will also be a logic high responsive to the logic high level on address line402coupled to contact line451, where contact lines452and453are respectively coupled to the logic low levels on address lines403and404. Output423of OR gate413will be a logic low level responsive to the logic low level on address lines403through405respectively coupled to contact lines461through463. Notably, address lines404and405are coupled to ground, and thus each have a logic low level.

Thus, in this example, FDR segment302was selected for a read operation. Accordingly outputs421and422, both being a logic high level, are used to cause information to be propagated in a direction toward a control logic377on segmented databus370. In contrast, output423of OR gate413, being a logic low level, is used to cause information to be propagated away from control logic377for a read operation. Outputs421through423may be provided as respective control signals to bidirectional drivers associated with an FDR segment. For example, for FDR segment302, bidirectional drivers323-6and323-7ofFIGS. 2A and 2Bmay be controlled responsive to output422. For a write operation, a default control signal state to each bidirectional driver will be to provide a direction of propagation away from control logic377, which in this example is a logic low level. This logic low level may thus be maintained, subject to an overriding control signal input as described for a read operation.

Thus, it should be understood that by shifting and adding address lines, where the MSBs of FDR address bits are successively grounded after an initial set of address bits, control signaling for bidirectional drivers may be generated responsive to an FDR segment address. By having at least two address bits or address lines with which segments drive other segments, each segment receives its own address and an address bit of an adjacent segment. These address bits allow a segment to determine whether it is in front of or behind an adjacent segment, with respect to direction of data propagation. Moreover, it should be understood that any location within bidirectional FDR segmented databus300may be accessed for a readback to control logic377. Furthermore, it should be understood that any location within bidirectional FDR segmented databus300may be accessed for a write operation by propagating write data away from control logic377. Moreover, though control logic377was used in this example, it should be understood that data may be controllably driven from one FDR segment to another in order to allow any FDR segment to write directly to any other FDR segment. In this embodiment of a direct write from FDR segment to FDR segment, additional address lines may be added for FDR segment to FDR segment direct writes apart from a readback to control logic377. Thus, for example, a direct write may be done from FDR segment303to FDR segment302inFIG. 3B, where bidirectional drivers associated with FDR301are tristated to prevent data propagation to control logic377.

FIG. 5is a schematic/block diagram depicting an exemplary embodiment of bidirectional drivers500. Bidirectional drivers500include bidirectional driver501and bidirectional driver502. Bidirectional driver501may be a bidirectional driver of bidirectional drivers323-6ofFIG. 3A, for example, and bidirectional driver502for example may be a bidirectional driver of bidirectional drivers323-5ofFIG. 3A. A databus line503, which may be a databus line of databus370-2ofFIG. 3A, couples input/output nodes511and512respectively of bidirectional drivers502and501. Notably, bidirectional drivers501and502may be configured for driving information in either direction, and such information may be pulled up to a logic high level for driving a logic high value, or pulled down to a logic low level for driving a logic low value.

Optionally, additional circuitry520may be coupled to databus line501, as bidirectional drivers502and501may be controllably tristated. In this manner, additional circuitry520may utilize a segmented bidirectional databus to propagate data.

Bidirectional driver501includes two tristateable buffers531and532coupled in a loop with data input/output nodes512and537. Bidirectional driver502includes two tristateable buffers533and534coupled in a loop with data input/output nodes511and536. For example, data lines542and541, which may be coupled to respective previous and subsequent databus lines via FDR segments, are coupled to respective input/output nodes536and537of bidirectional drivers502and501. As previously mentioned with reference toFIG. 4, control signals may be output from OR gates. Continuing the above example, control signal422ofFIG. 4may be coupled to bidirectional driver502, where control input signal538is responsive to control signal422, such as for outputting information from bidirectional driver502(“forward direction”). Output provided from bidirectional driver502would then be forwarded to bidirectional driver501via databus line503. Control input signal539may be responsive to control signal421ofFIG. 4to allow for inputting data to bidirectional driver501(“reverse direction”). Data line541may be coupled to another databus line via an FDR segment. Thus, for this example, a previous databus line would be coupled to node536from which information would be obtained and driven in a forward direction via bidirectional driver502to bidirectional driver501, which would forward the information to a subsequent databus segment via output node537. Notably, nodes536and537may be either input or output nodes depending on direction of propagation of information.

Accordingly, it should be understood that the entire databus may be driven from any segment along the chain. Moreover, control logic, which may be located at an end of or somewhere along the databus chain, may be used to drive data to any segment along the databus chain, and data may be read back to the control logic. Moreover, it should be understood that arbitrarily long databus chains are facilitated as the number of data buses in the databus chain may be incrementally increased. Although the above segmented data bus has been described with reference to an FPGA, an ASIC, or other integrated circuit, it should be understood that the above-described segmented data bus may be used for other bidirectional interconnect applications. Moreover, the above-described segmented data bus may be used in microchip-to-microchip communications, such as at a circuit board level, or large scale applications with databuses extending over longer distances than at a circuit board level. Thus, an address may be provided for any of: exclusive communication between FDR segments, communication between an FDR segment and control logic, communication from one integrated circuit to another, and communication from one circuit board to another circuit board.

FIG. 6Ais a schematic diagram depicting an exemplary alternative embodiment of a bidirectional driver601. Bidirectional driver601includes pass gate multiplexers603and604, the inputs of which are provided from in-series inverters605and606, respectively. Inputs to inverters605and606are respectively coupled to nodes607and608. The output of multiplexer604is connected to node607, and the output of multiplexer603is coupled to node608. For example, an input data signal621may be input to node607, which data is inverted by inverter605. Output of inverter605is passed through pass gate multiplexer603responsive to control signal624set to allow passage through such multiplexer. Output of multiplexer603is provided to node608for output data signal622. Multiplexer604is put in a tristate condition responsive to control signal623to prevent passage of data through such multiplexer.

FIG. 6Bis a schematic/block diagram depicting another exemplary alternative embodiment of a bidirectional driver602. Driver circuits603and633are coupled in a loop for bidirectional data propagation and with common input/output nodes641and642, where each such driver circuit may be used to implement a half of bidirectional driver602. Each of driver circuits603and633is the same circuit, so only driver circuit603is described in detail to avoid unnecessary repetition.

InFIG. 6B, a driver circuit603receives an input, such as an input data signal631, to input/ouput node641for input to inverter611, the output of which is coupled to a node coupled to source regions of p-type and n-type transistors coupled in source/drain parallel. P-type transistor612and n-type transistor613have their drain regions coupled to an output node614. An input node615is coupled to a gate of n-type transistor613and to an input of inverter616. Output of inverter616is used to gate p-type transistor612and thus is coupled to a gate of p-type transistor612. Notably, node615is used to provide a control signal634to gates of n-type and p-type transistors613and612for configuring lower driver circuit603to either drive data or be in a tristate condition. Thus, input data signal631is inverted by inverter611, the output of which passes through respective channels of transistors612and613as output signal632via input/output node642.

For bidirectional drivers described herein, there is a possibility that both driver circuit portions are placed via a control signal in a tristate, or non-data-driving, configuration. If both bidirectional driver circuit portions are effectively in a non-driving state, there is a possibility that a databus line coupled thereto could float. To prevent such floating, namely to hold a databus state in place, a relatively weak latch may be coupled to a databus line. By “relatively weak latch,” it is meant that a driver circuit portion at either end of a databus line segment may override latched state of the latch, or half latch.

For example,FIGS. 7A and 7Bare schematic diagrams depicting respective exemplary embodiments of a latch700and a half-latch701, which may be coupled to a databus line703. InFIG. 7A, latch700includes inverters704and705coupled in series in a closed loop where input to inverter704is coupled to databus line segment703and output of inverter705is also coupled to databus line segment703.

InFIG. 7B, inverter705is replaced with a p-type transistor706. P-type transistor706has its gate coupled to the output of inverter704. A source region of p-type transistor706is coupled to a source voltage707, and a drain region of p-type transistor706is coupled to databus segment703. Latch700may be used to maintain state on a databus line segment703by weakly latching such state, or half-latch701may be used to maintain a logic level one on databus line segment703.