Chip package having tilted through silicon via

A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion.

TECHNICAL FIELD

The present invention relates to a chip package including at least one integrated circuit die having a tilted through silicon via.

DISCUSSION OF THE BACKGROUND

Chip stacking technology can bring two chips close together, thereby enabling faster data transmission between the two chips and consuming less power. Memory chips can be stacked together to obtain a memory module with a large storage capacity. In addition to stacking two of the same chip, two chips with different functions may also be stacked together to combine different functions.

In a memory chip stack, each memory chip has a chip selection (CS) terminal, which is used to enable the memory chip. For example, a DRAM chip can have a row address strobe (RAS), column address strobe (CAS), or chip selection pin (CSP) as a chip selection terminal. When a signal is applied to the chip selection terminal of a chip in a memory chip stack, the chip can be accessed, while other chips cannot.

Conventionally, signals applied to the chip selection terminals of the memory chip stack will flow through wires. Such wires need additional processes to form, which increases risk of signal trace shortage when going to fine-pitch products. Moreover, long wires cause signal delays by occupying more space, and results in a large chip package.

This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a chip package comprising at least one integrated circuit die. In some embodiments, the at least one integrated circuit die comprises a substrate portion having an internal plane between a front side and a back side; an electrical interconnect portion on the front side; a plurality of first connection terminals on an upper surface of the electrical interconnect portion; a plurality of second connection terminals on the back side of the substrate portion; a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals; a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion; and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals; wherein at least one of the chip selection wiring and the plurality of connection wirings comprises a tilted portion with respect to the back side of the substrate portion.

In some embodiments, the tilted portion is in the substrate portion, and the chip selection wiring further comprises a vertical portion in the electrical interconnect portion.

In some embodiments, the chip selection wiring comprises a tilted portion with respect to the back side of the substrate portion, and at least one of the plurality of connection wirings comprises a vertical portion with respect to the back side of the substrate portion.

In some embodiments, at least one of the plurality of connection wirings comprises a tilted portion with respect to the back side of the substrate portion, and the chip selection wiring comprises a vertical portion in the substrate portion and a lateral portion connected to the vertical portion.

In some embodiments, at least one of the plurality of connection wirings comprises a tilted portion having a first tilt angle with respect to the back side of the substrate portion, and the chip selection wiring comprises a tilted portion having a second tilt angle with respect to the back side of the substrate portion, and the first tilt angle is different from the second tilt angle.

In some embodiments, at least one of the plurality of connection wirings comprises a tilted portion having a first tilt angle with respect to the back side of the substrate portion, and the chip selection wiring comprises a tilted portion having a second tilt angle with respect to the back side of the substrate portion, and the first tilt angle is substantially the same as the second tilt angle.

In some embodiments, the at least one of the connection wirings includes a vertical portion in the electrical interconnect portion.

In some embodiments, one of the connection wirings electrically connects one of the second connection terminals to one of the first connection terminals not vertically above the one of the second connection terminals.

In some embodiments, the chip selection terminal is disposed in the electrical interconnect portion.

In some embodiments, the chip selection terminal is disposed in the substrate portion.

In some embodiments, the plurality of first connection terminals is fewer than the plurality of the second connection terminals by at least one terminal.

In some embodiments, the at least one integrated circuit die is one of a plurality of integrated circuit dies on a wafer.

In some embodiments, the at least one integrated circuit die is an integrated circuit die separated from a wafer.

In some embodiments, the at least one integrated circuit die is a memory chip.

In some embodiments, the second connection terminals and the first connection terminals are positioned in a staggered manner along a vertical direction.

In some embodiments, the second connection terminals and the first connection terminals are positioned in a misaligned manner along a vertical direction.

In some embodiments, the chip package comprises a lower integrated circuit die and an upper integrated circuit die stacked over the lower integrated circuit die, wherein one of the plurality of second connection terminals of the upper integrated circuit die is not electrically connected to the plurality of first connection terminals of the lower integrated circuit die.

In some embodiments, the chip package comprises an adhesive layer interposed between the lower integrated circuit die and the upper integrated circuit die.

In some embodiments, the chip package comprises an object, and the at least one integrated circuit die being attached to the object, wherein the object is selected from the group consisting of a package circuit substrate, a silicon interposer, a glass interposer and another integrated circuit die.

Another aspect of the present disclosure provides a method for preparing a chip package. In some embodiments, the method comprises steps of providing a substrate portion having an internal plane between a front side and a back side; forming a chip selection terminal between the internal plane of the substrate portion and an upper surface of the electrical interconnect portion; forming an electrical interconnect portion on the front side; forming a plurality of first connection terminals on the upper surface of the electrical interconnect portion; forming a chip selection plug connected to the chip selection terminal; forming a plurality of connection plugs electrically connected to the first connection terminals; and forming a plurality of second connection terminals on the back side of the substrate portion and electrically connected to the plurality of connection plugs; wherein at least one of the chip selection plug and the plurality of connection plugs is a tilted plug with respect to the back side of the substrate portion.

In some embodiments, the method further comprises the steps of forming a mask layer having at least one opening on the back side of the substrate portion; tilting the substrate portion with respect to a horizontal plane; performing an etching process to remove a portion of the substrate portion through the at least one opening to form a hole with respect to the back side of the substrate portion; and filling the hole with a conductor.

In some embodiments, the method further comprises the steps of tilting the substrate portion with respect to a horizontal plane; performing a laser drilling process to remove a portion of the substrate portion from the back side of the substrate portion to form a hole with respect to the back side of the substrate portion; and filling the hole with a conductor.

In some embodiments, the forming of a chip selection wiring comprises performing a first etching process when the substrate portion is positioned at a first angle to form a first hole, the forming of a plurality of connection wirings comprises performing a second etching process when the substrate portion is positioned at a second angle to form a plurality of second holes, and the first hole and the second holes have different included angles with respect to the back side of the substrate portion.

In some embodiments, the forming of a chip selection wiring comprises performing a first laser drilling process when the substrate portion is positioned at a first angle to form a first hole, the forming of a plurality of connection wirings comprises performing a second laser drilling process when the substrate portion is positioned at a second angle to form a plurality of second holes, and the first hole and the second holes have different included angles with respect to the back side of the substrate portion.

In some embodiments, the method further comprises a step of stacking the at least one integrated circuit die to an object, the object is selected from the group consisting of a package circuit substrate, a silicon interposer, a glass interposer and another integrated circuit die.

In some embodiments of the present disclosure, in the integrated circuit die, at least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion (tilted through silicon via) with respect to the back side of the substrate portion, so as to shorten the signal transmitting path for the chip selection signal in the integrated circuit die.

DETAILED DESCRIPTION

The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.

References to “one embodiment,” “an embodiment,” “exemplary embodiment,” “other embodiments,” “another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.

The present disclosure is directed to a chip package including at least one integrated circuit die having a tilted through silicon via. In order to make the present disclosure completely comprehensible, detailed steps and structures are provided in the following description. Obviously, implementation of the present disclosure does not limit special details known by persons skilled in the art. In addition, known structures and steps are not described in detail, so as not to limit the present disclosure unnecessarily. Preferred embodiments of the present disclosure will be described below in detail. However, in addition to the detailed description, the present disclosure may also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the detailed description, and is defined by the claims.

FIG. 1is a cross-sectional view of a chip package100A in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100A comprises an object200and at least one integrated circuit die10A stacked to the object200by using an adhesive layer300. In some embodiments, the at least one integrated circuit die10A comprises a substrate portion110having a front side110A and a back side110B; an electrical interconnect portion120on the front side110A; a plurality of upper connection terminals121A on an upper surface120A of the electrical interconnect portion120; a plurality of lower connection terminals121B on the back side110B of the substrate portion110; a chip selection terminal111A in the electrical interconnect portion120; and a chip selection wiring119A connected to the chip selection terminal111A and one of the lower connection terminals121B, wherein the chip selection wiring119A comprises a tilted chip selection plug117A with respect to the back side110B of the substrate portion110. In some embodiments, the front side110A includes, but not limited to, the upper surface of the substrate portion110facing the electrical interconnect portion120and the space above the upper surface; similarly, the back side110B includes, but not limited to, the lower surface of the substrate portion110facing the object200and the space below the lower surface. In some embodiments, the chip selection terminal111A is electrically connected to a gate terminal of a MOS transistor in a logic circuit such as the peripheral circuit of a DRAM chip, and the MOS transistor is configured to control whether allowing the propagation of the command instructions from a source terminal to a drain terminal thereof.

In some embodiments, the object200is a package circuit substrate or silicon/glass interposer, and the plurality of lower connection terminals121B of the at least one integrated circuit die10A is attached respectively to the object200via a plurality of metal bump127. In some embodiments, the adhesive layer300is an anisotropic conductive film (ACF), an anisotropic conductive adhesive (ACA), nonconductive film/paste (NCF/NCP), underfill, MUF (molding underfill), and so on. The ACF or the ACA comprises an insulation film or an insulating adhesive, and conductive particles dispersed within the insulation film or the insulating adhesive. The NCF/NCP or underfill/MUF comprises an insulation film or adhesive, and non-conductive particles dispersed within insulation film/adhesive.

In some embodiments, the substrate portion110may include a silicon wafer. For example, the substrate portion110may include a single crystalline silicon wafer, a silicon bulk wafer including a silicon carbide (SiC) layer or silicon germanium (SiGe) layer, or a silicon-on-insulator (SOI) wafer including an insulating layer. In the present embodiments, it is assumed that the substrate portion110is a single crystalline silicon bulk wafer. In some embodiments, the at least one integrated circuit die10A may include unit devices, which may be formed in the substrate portion110and/or on the substrate portion110, and the unit device(s) may include metal-oxide-semiconductor (MOS) transistors.

In some embodiments, the at least one integrated circuit die10A is one of a plurality of integrated circuit dies on a wafer. In some embodiments, the at least one integrated circuit die10A is an integrated circuit die separated from a wafer. In some embodiments, the at least one integrated circuit die10A is a memory chip such as DRAM chips or flash memory chips. It is well known that a memory chip comprises address input terminals for addressing memory cells, data input/output terminals for inputting/outputting data to/from the memory cells, and power supply terminals.

In some embodiments, the tilted chip selection plug117A is inside the substrate portion110, and the chip selection wiring119A further comprises a vertical plug113A in the electrical interconnect portion120. In some embodiments, the chip selection terminal111A is formed on the front side110A of the substrate portion110, and there is no vertical plug below the chip selection terminal111A. In some embodiments, the chip package10A further comprises a plurality of connection wirings129A electrically connecting the upper connection terminals121A and the lower connection terminals121B, wherein at least one of the connection wirings129A includes a tilted connection plug117B in the substrate portion110. In some embodiments, the connection wirings129A further comprises a vertical portion113B in the electrical interconnect portion120. In some embodiments, the tilted angle of the tilted chip selection plug117A with respect to the back side110B of the substrate portion110is substantially the same as that of the tilted connection plug117B with respect to the back side110B of the substrate portion110.

In some embodiments, one of the connection wirings129A electrically connects one of the lower connection terminals121B to one of the upper connection terminals121A not vertically above the one of the lower connection terminals121B. In some embodiments, the lower connection terminals121B and the upper connection terminals121A are positioned in a staggered manner along a vertical direction. In some embodiments, the lower connection terminals121B and the upper connection terminals121A are positioned in a misaligned manner along a vertical direction. In some embodiments, the plurality of upper connection terminals121A is fewer than the plurality of the lower connection terminals121B by at least one terminal.

FIG. 2is a cross-sectional view of a chip package100B in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100B comprises an object200and at least one integrated circuit die10B stacked to the object200by using an adhesive layer300. In some embodiments, the substrate portion110has an internal plane110C between the front side110A and the back side110B. Compared to the integrated circuit die10A inFIG. 1having the chip selection terminal111A in the electrical interconnect portion120, the chip package100B inFIG. 2has a chip selection terminal111B in the substrate portion110, i.e., between the internal plane110C of the substrate portion110and the upper surface120A of the electrical interconnect portion120. In some embodiments, the internal plane110C is a bottom plane of an isolation structure such as a shallow trench isolation (STI).

In some embodiments, the substrate portion110has a depression (not shown in the drawings) below the front side110A, and the chip selection terminal111B is formed in the depression. In some embodiments, the integrated circuit die10B comprises a chip selection wiring119B connected to the chip selection terminal111B and one of the lower connection terminals121B. In some embodiments, the chip selection wiring119B comprises a tilted chip selection plug117A in the substrate portion110and an interconnect113C in the electrical interconnect portion120, wherein the tilted chip selection plug117A is tilted with respect to the back side110B of the substrate portion110. In some embodiments, the tilted angle of the tilted chip selection plug117A with respect to the back side110B of the substrate portion110is substantially the same as that of the tilted connection plug117B with respect to the back side110B of the substrate portion110.

FIG. 3is a cross-sectional view of a chip package100C in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100C comprises an object200and at least one integrated circuit die10C stacked to the object200by using an adhesive layer300. InFIG. 2, to connect the chip selection terminal111B and one of the lower connection terminals121B, the integrated circuit die10B uses the chip selection wiring119B including a tilted chip selection plug117A in the substrate portion110and an interconnect113C in the electrical interconnect portion120. In contrast, inFIG. 3, to connect the chip selection terminal111B and one of the lower connection terminals121B, the integrated circuit die10C uses a tilted chip selection plug119C as a chip selection wiring119C in the substrate portion110. In some embodiments, the tilted angle of the tilted chip selection plug117B with respect to the back side110B of the substrate portion110is different from that of the tilted connection plug117B with respect to the back side110B of the substrate portion110.

FIG. 4is a cross-sectional view of a chip package100D in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100D comprises an object200and at least one integrated circuit die10D stacked to the object200by using an adhesive layer300. InFIG. 1, to connect the chip selection terminal111A and one of the lower connection terminals121B, the integrated circuit die10A uses the chip selection wiring119A including a tilted chip selection plug117A in the substrate portion110and a vertical plug113A in the electrical interconnect portion120. In contrast, inFIG. 4, to connect the chip selection terminal111A and one of the lower connection terminals121B, the integrated circuit die10D uses a chip selection wiring119D including an interconnect117D in the substrate portion110and the vertical plug113A in the electrical interconnect portion120. In some embodiments, the chip selection terminal111A is formed on the upper surface of the substrate portion110, and the interconnect117D directly contacts the bottom of the chip selection terminal111A without using the vertical plug113A.

In some embodiments, the interconnect117D includes a lateral portion60A connected to the lower connection terminals121B and a vertical portion60B connected to the bottom of the chip selection terminal111A and the lateral portion60A. In some embodiments, the lateral portion60A is implemented in a redistribution layer (RDL) on the back side110B of the substrate portion110, and the vertical portion60B is implemented in the substrate portion110. In other words, in the integrated circuit die10D, a non-tilting wiring is used to connect the chip selection terminal111A and one of the lower connection terminals121B, while tilting wirings are used to connect the upper connection terminals121A and the lower connection terminals121B.

FIG. 5is a cross-sectional view of a chip package100E in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100E comprises an object200and at least one integrated circuit die10E stacked to the object200by using an adhesive layer300. InFIG. 1, to connect the upper connection terminals121A and the lower connection terminals121B, the integrated circuit die10A uses the connection wirings129A including a tilted connection plug117B in the substrate portion110and a vertical portion113B in the electrical interconnect portion120. In contrast, inFIG. 5, to connect the upper connection terminals121A and the lower connection terminals121B, the integrated circuit die10E uses a plurality of connecting wirings129E each including an interconnect113E the electrical interconnect portion120and a vertical via117E in the substrate portion110. In other words, in the integrated circuit die10E, non-tilting wirings are used to connect the upper connection terminals121A and the lower connection terminals121B, while a tilting wiring is used to connect the chip selection terminal111A and one of the lower connection terminals121B.

FIG. 6is a cross-sectional view of a chip package100F in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100F comprises an object200and at least one integrated circuit die10F stacked to the object200by using an adhesive layer300. InFIG. 1, the number of the upper connection terminals121A is fewer than the number of the lower connection terminals121B by at least one terminal. In contrast, inFIG. 6, the number of the upper connection terminals121A is the same as the number of the lower connection terminals121B. In some embodiments, the integrated circuit die10F further includes an upper connection terminal70A above the chip selection terminal111A and a vertical plug70B connecting the chip selection terminal111A and the upper connection terminal70A. In some embodiments, the upper connection terminal70A is integrally formed with the upper connection terminals121A; consequently, the number of the upper connection terminals121A is the same as the number of the lower connection terminals121B.

FIG. 7is a cross-sectional view of a chip package100G in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100G comprises an object200and at least one integrated circuit die10G stacked to the object200by using an adhesive layer300. InFIG. 1, the integrated circuit die10is stacked to the object200in a face-up manner, while the integrated circuit die10G inFIG. 7is stacked to the object200in a face-down manner.

InFIG. 7, in some embodiments, the integrated circuit die10G further includes an upper connection terminal70A and a vertical plug70B connecting the chip selection terminal111A and the upper connection terminal70A; in addition, the chip selection terminal111A is not connected to the lower connection terminals121B. Consequently, the number of the connection terminals on the upper surface120A is more than the number of the connection terminals on the back side110B. In some embodiments, the vertical plug70B in the electrical interconnect portion120is used as the chip selection plug (wiring), and there is no chip selection plug113A in the substrate portion110. In some embodiments, the integrated circuit die10G may have the chip selection terminal in the substrate portion110, as shown inFIG. 2.

FIG. 8is a cross-sectional view of a chip package100H in accordance with some embodiments of the present disclosure. Electronic equipment using semiconductor devices are essential for many modern applications. With the advancement of electronic technology, electronic equipment is becoming increasingly smaller in size and complicated in structure and functionality. Wafer level packaging (WLP) technology has been gaining popularity and is widely applied. This technology provides a wafer level manufacturing of semiconductor devices with high functions and complicated structures while the size of the semiconductor devices is minimized.

In some embodiments, the chip package100H comprises a plurality of stacked integrated circuit die10A shown inFIG. 1. In some embodiments, the chip package100H further comprises a molding compound80encapsulating the plurality of stacked integrated dies10A. In some embodiments, the molding compound80includes various materials, for example, one or more of epoxy resins, phenolic hardeners, silicas, catalysts, pigments, mold release agents, and the like. In addition to stacking the same integrated circuit dies10A inFIG. 1to form the chip package100H, the chip package100H may be formed by stacking different integrated circuit dies shown inFIGS. 1-6.

In some embodiments, considering the bottommost integrated circuit die10A to be a first integrated circuit die101A and the integrated circuit die10A right on the bottommost integrated circuit die to be a second integrated circuit die101B, one of the plurality of lower connection terminals121B (the rightmost one) of the second integrated circuit die101B is not electrically connected to the plurality of upper connection terminals121A of the first integrated circuit die101A.

In some embodiments, for example, as an electronic signal is selectively transmitted to the chip selection terminal111A of the second integrated circuit die101B via the lower connection terminals121B of the first integrated circuit die101A, the connection wiring129A of the first integrated circuit die101A and the chip selection wiring119A of the second integrated circuit die101B, the second integrated circuit die101B is selected for operation and can be accessed, while other non-select integrated circuit dies cannot be accessed. Similarly, the other integrated circuit dies10A can be selected for operation and can be accessed by selectively applying electronic signals to different lower connection terminals121B of the first integrated circuit die101A.

FIG. 9is a cross-sectional view of a chip package100I in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100I comprises a plurality of stacked integrated circuit die10A shown inFIG. 1on an object200A. In some embodiments, the chip package100I comprises a first integrated circuit die101A attached to the object200A, a second integrated circuit die101B attached to the first integrated circuit die101A from the front side110A, a third integrated circuit die101C attached to the second integrated circuit die101B from the front side110A, and a fourth integrated circuit die101D attached to the third integrated circuit die101C from the front side110A, with an adhesive layer300interposed between the integrated circuit dies. In addition to stacking the same integrated circuit dies10A inFIG. 1to form the chip package100I, the chip package100I may be formed by stacking different integrated circuit dies shown inFIGS. 1-6.

In some embodiments, the object200A is a package circuit substrate having a plurality of contacts210A,210B,210C and210D, in which each has an upper pad, a bottom pad, and a conduction path electrically connecting the bottom pad to the upper pad. In addition, the package circuit substrate or silicon/glass interposer also has a plurality of solder balls or bumps (like copper pillar bump)220A,220B,220C and220D respectively attached to the plurality of bottom pads of the plurality of contacts210A,210B,210C and210D. In some embodiments, the plurality of lower connection terminals121B of the at least one integrated circuit die10A is attached respectively to the plurality of upper pads of the package circuit substrate200via the metal bump127.

In some embodiments, for example, as electronic signals are selectively transmitted to the chip selection terminal111A of the second integrated circuit die101B via the solder ball220B, the contact210B, the connection wiring129A of the first integrated circuit die101A and the chip selection wiring119A of the second integrated circuit die101B, the second integrated circuit die101B is selected for operation and can be accessed, while other non-select integrated circuit dies cannot be accessed. Similarly, the first integrated circuit die101A can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220A, the third integrated circuit die101C can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220C, and the fourth integrated circuit die101D can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220D.

FIG. 10is a cross-sectional view of a chip package100J in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100J comprises a plurality of stacked integrated circuit die10G shown inFIG. 7on an object200A. In some embodiments, the chip package100I comprises a first integrated circuit die102A attached to the object200A, a second integrated circuit die102B attached to the first integrated circuit die102A from the back side110B, a third integrated circuit die102C attached to the second integrated circuit die102B from the back side110B, and a fourth integrated circuit die102D attached to the third integrated circuit die102C from the back side110B, with an adhesive layer300interposed between the integrated circuit dies.

In some embodiments, for example, as electronic signals are selectively transmitted to the chip selection terminal111A of the second integrated circuit die102B via the solder ball220B, the contact210B, the connection wiring129A of the first integrated circuit die102A and the vertical plug70B of the second integrated circuit die102B, the second integrated circuit die102B is selected for operation and can be accessed, while other non-select integrated circuit dies cannot be accessed. Similarly, the first integrated circuit die102A can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220A, the third integrated circuit die102C can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220C, and the fourth integrated circuit die102D can be selected for operation and can be accessed by selectively transmitting electronic signals via the solder ball220D.

FIG. 11is a cross-sectional view of a chip package100K in accordance with some embodiments of the present disclosure. In some embodiments, the chip package100K comprises a plurality of stacked integrated circuit die10A shown inFIG. 1on a first portion of an object200C and an integrated circuit die10H on a second portion of the object200C, wherein the integrated circuit die10H has different functions from the integrated circuit die10A. In some embodiments, the chip package100K further comprises an object200D, the object200C is attached to the object200D.

In some embodiments, the object200C is a glass interposer or a silicon interposer, and the object200D is a package circuit substrate. In some embodiments, the integrated circuit die10A and the integrated circuit die10H are attached to the interposer200C from a first side201A with the metal bumps127, the package circuit substrate is attached to the interposer200C from a second side201B with solder balls203, wherein the interposer200C comprises internal wirings205electrically connecting the metal bumps127on the first side201A to the solder balls203on the second side201B. In some embodiments, the first side201A includes, but not limited to, the upper surface of the interposer200C facing the integrated circuit die10A and the space above the upper surface; similarly, the second side201B includes, but not limited to, the lower surface of the interposer200C facing the object200D and the space below the lower surface.

In some embodiments, the chip package100K further comprises a molding compound90encapsulating the dies and the object200C. In some embodiments, the molding compound90includes various materials, for example, one or more of epoxy resins, phenolic hardeners, silicas, catalysts, pigments, mold release agents, and the like. In addition to stacking the same integrated circuit dies10A inFIG. 1in the chip package100K, the chip package100K may be formed by stacking different integrated circuit dies shown inFIGS. 1-6; furthermore, the chip package100K may be formed by stacking different integrated circuit dies shown inFIG. 7.

FIGS. 12-17are cross-sectional views showing the fabrication for preparing an integrated circuit die10A in accordance with some embodiments of the present disclosure.

Referring toFIG. 12, an electrical interconnect portion120is formed on a substrate portion110by fabrication processes including deposition, lithographic and etching processes. In some embodiments, the substrate portion110may include a transistor in an active area (AA) surrounded by an isolation structure such as a shallow trench isolation (STI). In some embodiments, the electrical interconnect portion120is formed on the substrate portion110by back-end-of-line (BEOL) metallization technology.

In some embodiments, the substrate portion110has a front side110A and a back side110B, and a chip selection terminal111A is formed on the front side110A, and a plurality of upper connection terminals121A are formed on an upper surface120A of the electrical interconnect portion120by fabrication processes including deposition, lithographic and etching processes. In some embodiments, the electrical interconnect portion120has a vertical plug113A below the chip selection terminal111A and a plurality of vertical plugs113B below the upper connection terminals121A respectively.

Referring toFIG. 13, in some embodiments, the substrate portion110is thinned by performing a grinding process on the back side110B of the substrate portion110.

Referring toFIG. 14, a mask layer130, such as a photoresist layer having at least one opening131, is formed on the back side of the substrate portion, and the substrate portion110is tilted with respect to a horizontal plane400. Subsequently, an etching process, such as an anisotropic dry etching by using an etching gas140A, is performed to remove a portion of the substrate portion110through the at least one opening131to form a first hole115exposing the vertical plug113A, wherein an included angle between the first hole115and the back side110B of the substrate portion110is not a right angle. In some embodiments, the etching process also forms a plurality of second holes125exposing the plurality of vertical plugs113B respectively, wherein an included angle between the second hole125and the back side110B of the substrate portion110is not a right angle.

Referring toFIG. 15, in some embodiments, instead of using anisotropic dry etching, a laser140B can be used to form the first hole115and the second holes125exposing the plurality of vertical plugs113B. Details of the laser drilling process are available in the art: (http://www.oxfordlasers.com/laser-micromachining/laser-micro-drilling/?gclid=COO7woD3g8MCFVcDvAod2K8ATw), the entirety of which is herein incorporated by reference and will not be repeated. In some embodiments, the first hole115exposes the vertical plug113A (or the bottom of the chip selection terminal111A if the chip selection terminal111A is formed in the substrate portion110).

Referring toFIG. 16, in some embodiments, the mask layer130is removed, and the first hole115is filled with a conductor117to form a tilted chip selection plug117A, and the tilted chip selection plug117A and the vertical plug113A form a chip selection wiring119. In some embodiments, the second holes125are filled with the conductor117to form a plurality of tilted connection plugs117B, and the tilted connection plugs117B and the vertical plugs113B form connection wirings129A. In some embodiments, tungsten (W) is used as the conductor117, but other conductive materials may also be used. A conventional plating technique, such as bottom-up plating mechanism for high aspect ratio trench, is used in filling the first hole115and the second holes125. In some embodiments, the tilted plug117A and the tilted plugs117B serve as tilted through silicon vias.

Referring toFIG. 17, a plurality of lower connection terminals121B are formed on the back side110B of the substrate portion110, wherein one of the lower connection terminals121B is connected to the tilted plug117A of the chip selection wiring119. In some embodiments, the other lower connection terminals121B are connected to the tilted plug117B of the connection wirings129A. Subsequently, metal bumps127are formed on the lower connection terminals121B so as to complete the integrated circuit die10A.

Subsequently, the integrated circuit die10A is attached to an object200with an adhesive layer300interposed between the integrated circuit die10A and the object200to form the chip package10, as shown inFIG. 1.

In the embodiments shown inFIGS. 14-17, the first hole115and the second hole125are formed by the same fabrication process. In some embodiments, the first hole115and the second hole125are formed by different fabrication processes. For example, the substrate portion110may be positioned at a first angle to perform a first etching (laser drilling) process to form a first hole exposing the vertical plug113A, and then the substrate portion110is then positioned at a second angle to perform a second etching (laser drilling process) to form a plurality of second holes exposing the plurality of vertical plugs113B. In some embodiments, the first angle and the second angle are the included angle between the back side110B and a vertical line, and the first hole and the second holes have different included angles with respect to the back side110B of the substrate portion110. In some embodiments, one of the first angle and the second angle is substantially a right angle.

In addition, those skilled in the art should understand that the fabrication processes disclosed inFIGS. 12-17can be readily utilized as a basis for modifying or designing to prepare the die structure shown inFIGS. 2-7.

One aspect of the present disclosure provides a chip package comprising at least one integrated circuit die. In some embodiments, the integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminal.

Another aspect of the present disclosure provides a method for preparing a chip package. In some embodiments, the method comprises steps of providing a substrate portion having an internal plane between a front side and a back side; forming a chip selection terminal between the internal plane of the substrate portion and an upper surface of the electrical interconnect portion; forming an electrical interconnect portion on the front side; forming a plurality of first connection terminals on the upper surface of the electrical interconnect portion; forming a chip selection wiring connected to the chip selection terminal; forming a plurality of connection wirings electrically connected to the first connection terminals; and forming a plurality of second connection terminals on the back side of the substrate portion and electrically connected to the plurality of connection wirings; wherein at least one of the chip selection wiring and the plurality of connection wirings comprises a tilted plug with respect to the back side of the substrate portion.

In some embodiments of the present disclosure, in the integrated circuit die, at least one of the chip selection wiring and the plurality of connection wirings includes a tilted plug (tilted through silicon via) with respect to the back side of the substrate portion, so as to shorten the signal transmitting path for the chip selection signal in the integrated circuit die.