Interconnect structure and method of manufacturing the same

A semiconductor device and a method for manufacturing the device that minimizes a line width while maximizing integration density of the semiconductor device. The method includes forming an interlayer insulating film on a semiconductor substrate, and then forming a first via hole in the interlayer insulating film, and then forming a resin material in the first via hole, and then forming a plurality of second via holes in the interlayer insulating film laterally, and then forming a resin material in the second via holes, and then simultaneously forming a plurality of third via holes in the interlayer insulating film and a trench spatially above and corresponding to the first via hole, and then removing the resin formed in the first via hole and the second via holes, and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench.

The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0136244 (filed on Dec. 24, 2007), which is hereby incorporated by reference in its entirety.

BACKGROUND

In semiconductor manufacturing, double patterning (DP) is a process for forming aluminum lines which is difficult for application in a dual damascene process. In one method of forming a double pattern, a first photolithography process is performed using a hard mask. A first etching process is then performed on the hard mask and then the hard mask is patterned by a second photolithography process. An underlying metal layer formed under the hard mask is then etched to form metal lines. Another double patterning method involves etching the underlying metal layer using a photoresist instead of a hard mask. After stripping the photoresist, a second photolithography process for etching the metal layer is performed to form final metal lines. In still another double patterning method, first and second exposure processes are performed before performing a developing process to thereby form final metal lines. As previously noted, such double patterning methods are disadvantageous since they are difficult to apply in a dual damascene process.

SUMMARY

Embodiments relate to a semiconductor device and a method for manufacturing metal lines in a semiconductor device using a double patterning process which is applicable to form a dual damascene structure.

Embodiments relate to a method for manufacturing a semiconductor device that may include at least one of the following steps: forming an interlayer insulating film on and/or over a semiconductor substrate; and then forming a first via hole in the interlayer insulating film by a photolithography process; and then forming a resin in the first via hole; and then forming plurality of second via holes adjacent to the first via hole by a photolithography process; and then forming a resin in the second via holes; and then simultaneously forming a plurality of third via holes between the second via holes by a photolithography process and a trench on and/or over and corresponding to the first via hole; and then removing the resin formed in the first via hole and the second via holes; and then forming metal layers in the first, second and third via holes and the trench.

Embodiments relate to a semiconductor device that may include at least one of the following: an interlayer insulating film formed on a semiconductor substrate; a first via formed in the interlayer insulating film exposing a portion of the semiconductor substrate; a trench via formed in the interlayer insulating film over and corresponding spatially to the first via; and a plurality of second vias formed in the interlayer insulating film adjacent to the trench via.

Embodiments relate to a method for manufacturing a semiconductor device that may include at least one of the following steps: forming an interlayer insulating film on a semiconductor substrate; and then forming a first via hole in the interlayer insulating film by a first photolithography process; and then forming a resin material in the first via hole; and then forming a plurality of second via holes in the interlayer insulating film laterally adjacent to the first via hole by a second photolithography process; and then forming a resin material in the second via holes; and then simultaneously forming a plurality of third via holes in the interlayer insulating film by a third photolithography process and a trench spatially above and corresponding to the first via hole; and then removing the resin formed in the first via hole and the second via holes; and then simultaneously forming metal layers in the first via hole and the second and third via holes and the trench.

Embodiments relate to a method that may include at least one of the following steps: sequentially forming a first interlayer insulating film and a second interlayer insulating film over a semiconductor substrate; and then forming a first via hole extending through the first interlayer insulating film and the second interlayer insulating film to expose a portion of the semiconductor substrate; and then filling the first via hole with a first resin material; and then simultaneously forming a second via hole and a third via hole extending through the second interlayer insulating film and partially in the first interlayer insulating film to expose portions of the first interlayer insulating film; and then simultaneously filling the second via hole with a second resin material and the third via hole with a third resin material; and then simultaneously forming a fourth via hole, a fifth via hole and a trench extending through the second interlayer insulating film and partially in the first interlayer insulating film, wherein the trench is formed over and corresponds spatially to the first via hole; and then removing the first, second and third resin materials to expose the first, second and third via holes, respectively; and then simultaneously forming first, second, third fourth and fifth vias and a contact in the first, second, third, fourth and fifth via holes and the trench, respectively.

DESCRIPTION

As illustrated in exampleFIG. 1A, first interlayer insulating film20and second interlayer insulating film30are sequentially formed on and/or over semiconductor substrate10. Alternatively, reference numeral10may designate a lower metal layer instead of a semiconductor substrate. In accordance with embodiments, although two interlayer insulating films20and30are formed as illustrated in exampleFIG. 1A, a single interlayer insulating film may alternatively be formed or three or more interlayer insulating films may be formed. For example, in accordance with embodiments, the interlayer insulating films may include fluorosilicate glass (FSG) film20formed on and/or over semiconductor substrate10and a nitride or oxide film30formed on and/or over FSG film20. Oxide film30may be formed using silane (SiH4) gas. If second interlayer insulating layer30is composed of a nitride film, such film may be composed of silicon nitride (SiN).

As illustrated in exampleFIG. 1B, first via hole50is formed in and extending through first interlayer insulating film20and second interlayer insulating film30exposing a portion of substrate10(or underlying metal layer) by a photolithography process. For example, first photoresist film pattern40is formed on and/or over second interlayer insulating film30A to expose an area in which first via hole50is to be formed. First interlayer insulating film20A and second interlayer insulating film30A are then etched by reactive ion etching (RIE) using first photoresist film pattern40as a mask, thereby forming first via hole50. After forming first via hole50, photoresist film pattern40is removed by ashing.

As illustrated in exampleFIG. 1C, resin material70is then formed in first via hole50. In this case, the resin70may be a novolac resin. As illustrated in exampleFIG. 1D, a plurality of second via holes52,54are then formed laterally adjacent to resin70formed in first via hole50by a photolithography process. For example, second photoresist film pattern42is formed on and/or over second interlayer insulating film30A and resin material70to expose areas in which second via holes52,54are to be formed. First interlayer insulating film20A and second interlayer insulating film30A are then etched by a second reactive ion etching (RIE) using second photoresist film pattern42as a mask to thereby form second via holes52,54. After forming second via holes52,54, photoresist film pattern42is removed. As illustrated in exampleFIG. 1E, second resin material72and third resin material74are then formed in second via holes52,54, respectively First resin70, second resin72and third resin74may each be formed as novolac resins.

As illustrated in exampleFIGS. 1F to 1H, a plurality of third via holes58,60are then formed on and/or over exposed areas of second interlayer insulating film30A not filled with second resin72and third resin74in second via holes52,54by a photolithography process. Simultaneously, trench56is formed on and/or over and corresponding spatially to first via hole50. For example, as illustrated in exampleFIG. 1F, third photoresist film pattern44is formed on and/or over second interlayer insulating film30A to expose areas in which third via holes58,60and trench56are to be formed.

As illustrated in exampleFIG. 1G, while third photoresist film pattern44is used as an etching mask, first resin70, first interlayer insulating film20A and second interlayer insulating film30A are etched by RIE, thereby forming third via holes58,60and trench56. While trench56is formed, a portion of resin70A is etched and removed such that its uppermost surface is on a plane which is spatially below the plane of the uppermost surface of second resin72and third resin74.

As illustrated in exampleFIG. 1H, after forming third via holes58,60and trench56, third photoresist film pattern44is removed by ashing.

As illustrated in exampleFIG. 1I, resins70A,72and74formed in first via hole50and second via holes52,54are removed. In a case where resins70A,72and74are novolac resins, the resins may be removed by a plasma process. After removing resins70A,72and74, at least one of an anti-diffusion film and metal barrier layer80is formed on and/or over the entire substrate10including inner walls of first via hole50, trench56, second via holes52,54and third via holes58,60in order to prevent diffusion of metal layers into interlayer insulating films20B,30B. The anti-diffusion film or metal barrier layer80may be deposited by at least one of a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. Anti-diffusion film80may be formed by depositing a material such as TaN, Ta, TaN/Ta, TiSiN, WN, TiZrN, TiN or Ti/TiN.

As illustrated in exampleFIG. 1J, first metal layer90, second metal layer92, third metal layer94, fourth metal layer96and fifth metal layer98are then formed in via holes50,52,54,58and60and trench56. Each metal layer may be formed of copper, but is not limited thereto. First metal layer90, second metal layer92, third metal layer94, fourth metal layer96and fifth metal layer98may be formed by at least one of a PVD method, a CVD method and an electroplating method. If first metal layer90, second metal layer92, third metal layer94, fourth metal layer96and fifth metal layer98are formed by a electroplating method, a seed copper film is deposited on and/or over the entire surface of anti-diffusion film80by one of a PVD method and a CVD method. Then, the resultant is immersed in an electrolyte solution to form a thick copper metal layer. The thick copper metal layer is then planarized by a chemical mechanical polishing (CMP) process to expose an upper portion of second interlayer insulating film30B, thereby forming first metal layer90, second metal layer92, third metal layer94, fourth metal layer96and fifth metal layer98.

Accordingly, a semiconductor device in accordance with embodiments is formed that includes interlayer insulating films20B,30B formed on and/or over semiconductor substrate10. Interlayer insulating films20B and30B may alternatively be formed on and/or over a lower metal layer formed on and/or over semiconductor substrate10. Meaning, the semiconductor device in accordance with embodiments may have a stacked structure obtained by repeatedly forming the structure shown in exampleFIG. 1Jin a vertical direction. In this case, first metal layer90, second metal layer92, third metal layer94, fourth metal layer96and fifth metal layer98become upper metal layers.

Interlayer insulating films20B,30B may have a multilayer structure including FSG film20B formed on and/or over semiconductor substrate10and oxide film30B formed on and/or over FSG film20B. First via91is formed in first interlayer insulating film20B on and/or over semiconductor substrate10and corresponds to the metal layer filled in first via hole50. Trench via90is formed in interlayer insulating films20B and30B spatially above first via91and corresponds to the metal layer filled in trench56. Second via92, third via94, fourth via96and fifth via98are formed adjacent to trench via90. Second via92and fourth via96correspond to the metal layers filled in second via holes52,54while third via94and fifth via98correspond to the metal layers filled in third via holes58,60.

In the semiconductor device and the method of manufacturing the device in accordance with embodiments, the metal layers are formed to be applicable to a dual damascene process by double patterning. Accordingly, it is possible to minimize a line width in the photolithography and there is an effect of maximizing integration density of the semiconductor device.