Isolation devices with faraday shields

An isolation device includes a first integrated circuit in electrical communication with first circuitry. The first integrated circuit includes a first light emitter portion to emit a first optical signal based on first electrical signals received at the first integrated circuit from the first circuitry. The isolation device includes a second integrated circuit in electrical communication with second circuitry. The second integrated circuit includes a first light-sensitive area to convert the first optical signal into second electrical signals for communication to the second circuitry. The isolation device includes an isolation material between the first integrated circuit and the second integrated circuit to electrically isolate the first integrated circuit from the second integrated circuit and to pass the first optical signal from the first light emitter portion to the first light-sensitive area. The isolation device includes a first shield to shield the first light emitter portion from electromagnetic radiation.

FIELD OF THE DISCLOSURE

Example embodiments are generally directed toward electronic isolation and devices for accommodating the same.

BACKGROUND

There are many types of electrical systems that benefit from electrical isolation. Galvanic isolation is a principle of isolating functional sections of electrical systems to prevent current flow, meaning that no direct electrical conduction path is permitted between different functional sections. As one example, certain types of electronic equipment require that high-voltage components (e.g., 1 kV or greater) interface with low-voltage components (e.g., 10V or lower). Examples of such equipment include medical devices and industrial machines that utilize high-voltage in some parts of the system, but have low-voltage control electronics elsewhere within the system. The interface of the high-voltage and low-voltage sides of the system relies upon the transfer of data via some mechanism other than electrical current.

Other types of electrical systems such as signal and power transmission lines can be subjected to voltage surges by lightning, electrostatic discharge, radio frequency transmissions, switching pulses (spikes), and perturbations in power supply. These types of systems can also benefit from electrical isolation.

Electrical isolation can be achieved with a number of different types of devices. Some examples of isolation products include galvanic isolators, optocouplers, inductive, and capacitive isolators. Previous generations of electronic isolators used two chips in a horizontal configuration with wire bonds between the chips. These wire bonds provided a coupling point for large excursions in the difference between the grounds of the systems being isolated. These excursions can be on the order of 25,000 V/usec.

As mentioned above, electrical isolation can be achieved with capacitive, inductive isolators, optical, and/or RF isolators to transmit data across an isolation boundary. There is a desire to add more optical channels to optical couplers in an attempt to meet the complex functionality requirements for various applications. However, there are concerns with respect to chip space utilization and chip pin utilization. Simply adding more channels to an optical coupler will increase package size and/or pin counts, which translates to a larger footprint on a Printed Circuit Board (PCB), which is generally undesirable in end products. It is a challenge to incorporate additional features into an existing number of channels already established in an optocoupler package.

DETAILED DESCRIPTION

Various aspects of example embodiments will be described herein with reference to drawings that are schematic illustrations of idealized configurations. As such, variations from the shapes of the illustrations as a result, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the various aspects of example embodiments presented throughout this document should not be construed as limited to the particular shapes of elements (e.g., regions, layers, sections, substrates, etc.) illustrated and described herein but are to include deviations in shapes that result, for example, from manufacturing. By way of example, an element illustrated or described as a rectangle may have rounded or curved features and/or a gradient concentration at its edges rather than a discrete change from one element to another. Thus, the elements illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the precise shape of an element and are not intended to limit the scope of example embodiments.

It will be understood that when an element such as a region, layer, section, substrate, or the like, is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be further understood that when an element is referred to as being “formed” or “established” on another element, it can be grown, deposited, etched, attached, connected, coupled, or otherwise prepared or fabricated on the other element or an intervening element.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to another element as illustrated in the drawings. It will be understood that relative terms are intended to encompass different orientations of an apparatus in addition to the orientation depicted in the drawings. By way of example, if an apparatus in the drawings is turned over, elements described as being on the “lower” side of other elements would then be oriented on the “upper” side of the other elements. The term “lower” can, therefore, encompass both an orientation of “lower” and “upper” depending of the particular orientation of the apparatus. Similarly, if an apparatus in the drawing is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can therefore encompass both an orientation of above and below.

Referring now toFIGS. 1-10, various configurations of isolation systems, isolators, and isolation devices are depicted and described. In some embodiments, the isolators described herein may be incorporated into any system which requires current and/or voltage monitoring, but is susceptible to transients. In some embodiments, the isolation system in which an isolator described herein is rated to operate at about 5 kV, 10 kV, or more. Stated another way, the input side (e.g., a high-voltage side) of the isolator or isolation system may be directly connected to a 5 kV, 10 kV, 15 kV or greater source without damaging the isolator or any electronic devices attached to the output side (e.g., a low-voltage side) of the isolator. Accordingly, an isolation system which employs one or more of the isolators disclosed herein may be configured to operate in high-voltage or high-current systems but may also be configured to separate the high-voltage or high-current systems from a low-voltage or low-current system.

Referring now toFIG. 1, an isolation system100will be described in accordance with at least one example embodiment. The system100is shown to include a first circuit (or first circuitry)104and second circuit (or second circuitry)108separated by an isolation boundary112. In some embodiments, an isolator116may provide a mechanism for carrying communication signals across the isolation boundary112.

The first circuit104may be operating in a high-voltage environment (e.g., with a ground potential at or exceeding 1 kV) whereas the second circuit108may be operating in a low-voltage environment (e.g., with a ground potential below 100V). Of course, the opposite condition may also be true without departing from the scope of example embodiments. The isolation boundary112may provide the mechanism for protecting the low-voltage environment from the high-voltage environment. The isolator116may be configured to establish and maintain the isolation boundary112while simultaneously facilitating the exchange of communications from the first circuit104to the second circuit108and vice versa. It should be appreciated, however, that the second circuit108may be operating in the high-voltage environment and the first circuit104may be operating in the low-voltage environment.

In some embodiments, the first circuit104receives a first input signal120at a first voltage (e.g., a high voltage). The first circuit104outputs a first output signal124to the isolator116. The first output signal124is still at the same nominal voltage as the first input signal120. The isolator116communicates information from the first output signal124to the second circuit108via a second input signal128. The second input signal128is now a second voltage (e.g., a low voltage) by operation of the isolator116. The second circuit108then processes the second input signal128and generates a second output signal132that is communicated to additional circuitry or controller components.

Conversely, to facilitate a bi-directional flow of information across the isolation boundary112, a third input signal136may be received at the second circuit108. The second circuit108may generate a third output signal140based on the third input signal136. The third output signal140may be provided to the isolator116. In some embodiments, the third output signal140is nominally at a similar voltage to the second input signal128. The isolator116may operate on the third output signal140in a similar fashion to the way that the first output signal124is processed, except in reverse. Specifically, the isolator116may produce a fourth input signal144that carries information previously contained in the third output signal140. The fourth input signal144may be nominally at a similar voltage to the first output signal124. The further input signal144may be provided to the first circuit104, which produces a fourth output signal148based on the fourth input signal144.

Even though the first circuit104operates at a different voltage than the second circuit108and there is an electrical isolation between the two circuits104,108, the isolator116is able to preserve the information from the first output signal124and communicate that information to the second circuit108via the second input signal128. The second input signal128may correspond to a logical representation or copy of the first output signal124. The second input signal128is essentially a reproduction of the first output signal124on different circuitry and at a different potential. Likewise, the isolator116is able to preserve information from the third output signal140and communicate that information to the first circuit104via the fourth input signal144. The fourth input signal144is essentially a reproduction of the third output signal140on different circuitry and at a different potential. It should be appreciated that the isolator116may be designed to carry information across the isolation boundary112in two different directions, either sequentially or simultaneously.

The isolation components204and208are also referred to herein as a first integrated circuit (IC)204and a second integrated circuit (IC)208. The isolation boundary112is also referred to herein as an isolation material112. The isolator116may also be referred to herein as an isolation device116.

With reference now toFIG. 2, additional details of the isolator116will be described in accordance with at least one example embodiment. The isolator116, as discussed above, is responsible for communicating information between the first circuit104and second circuit108while simultaneously maintaining the isolation boundary112between the circuits104,108. Communication of the signal124across the isolation boundary112is achieved by one or more isolation components204,208, which may correspond to optical or optoelectronic isolation components as will be discussed in further detail herein.

The isolator116may comprise first isolation component(s)204on its first side and second isolation component(s)208on its second side. The first isolation component(s)204and second isolation component(s)208may correspond to optoelectronic devices (e.g., LEDs, photodetectors, photodiodes, lasers, etc.) or the like that work together to communicate signals between one another wirelessly, thereby maintaining the isolation boundary112. In some embodiments, the isolation components204,208communicate with one another via optical coupling (e.g., by the transmission and reception of optical signals in the form of photons). Other coupling techniques such as inductive coupling, magnetic coupling, capacitive coupling, or the like may also be used by isolator116.

In at least one example embodiment, the first circuitry104and the first integrated circuit204are connected to a first ground or a first common voltage, and the second circuitry108and the second integrated circuit208are connected to a second ground or a second common voltage. Further, the isolation device116may include a leadframe or printed circuit board that supports both the first integrated circuit204and the second integrated circuit208.

FIG. 3depicts an example of an isolation device116in accordance with at least one example embodiment. In particular,FIG. 3illustrates a cross sectional view of the isolation device116.

With reference toFIGS. 1-3, the isolation device116includes a first integrated circuit204in electrical communication with first circuitry104. The first integrated circuit204includes a first light emitter portion (or light source)307configured to emit a first optical signal based on first electrical signals124received at the first integrated circuit204from the first circuitry104. The isolation device116includes a second integrated circuit208in electrical communication with second circuitry108. The second integrated circuit208includes a first light-sensitive area (or photodetector)323configured to convert the first optical signal into second electrical signals128for communication to the second circuitry. The isolation device116includes an isolation material112between the first integrated circuit204and the second integrated circuit208to electrically isolate the first integrated circuit204from the second integrated circuit208and to pass the first optical signal from the first light emitter portion307to the first light-sensitive area323. The isolation device116includes a first shield (or first electromagnetic shield)310to shield the first light emitter portion307from electromagnetic radiation.

As shown inFIG. 3, the first integrated circuit204further comprises a second light-sensitive area (or photodetector)313and the second integrated circuit208further comprises a second light emitter portion (or light source)317. The second integrated circuit208includes the second light emitter portion317configured to emit a second optical signal based on second electrical signals140received at the second integrated circuit208from the second circuitry108. The first integrated circuit204includes the second light-sensitive area313configured to convert the second optical signal into second electrical signals144for communication to the first circuitry104.

In at least one example embodiment, the first and second light sensitive areas323/313comprise one or more light sensors, such as photodiodes, phototransistors, etc. that convert incident light into electrical signals. In at least one example embodiment, the first and second light emitter portions307/317comprise light emitting diode (LED) structures.FIG. 3illustrates an example where the first and second light emitter portions307/317comprise LED structures with a base comprised of a semiconductor, such as GaAs, that supports stacked doped regions P+ (e.g., AlGaAs) and N+ (e.g., AlGaAs). The LED structures may be grown onto the substrates300/320using a metal-organic chemical vapor deposition (MOCVD) process or the like. Further, the LED structures are not limited to being formed of GaAs and may be formed of any material (e.g., Group III-V material) known in the LED art, such as AlxGa1-xAs, GaN, InP, etc.

As shown inFIG. 3, the light emitter portions307/317are formed on areas of the substrates300/320that are thinner than areas of the substrates300/320where the first and second light-sensitive areas323/313are formed.

FIG. 3further illustrates that an N-type material (e.g., doped region N+) of the first light emitter portion307is closer to the first light-sensitive area323than a P-type material (e.g., doped region P+) of the first light emitter portion307. Similarly, an N-type material (e.g., doped region N+) of the second light emitter portion317is closer to the second light-sensitive area313than a P-type material (e.g., doped region P+) of the second light emitter portion317.

In view of the above, it should be appreciated that the first light-sensitive area323and the first light emitter portion307establish a first communication channel, and the second light-sensitive area313and the second light emitter portion317establish a second communication channel. In accordance with example embodiments, the first communication channel and the second communication channel are configured to transmit different data between the first integrated circuit204and second integrated circuit208via optical signals. For example, the first communication channel carries data via the first optical signal from the first light emitter portion307to the first light-sensitive area323, and the second communication channel carries data via a second optical signal from the second light emitter portion317to the second light-sensitive area313.

As shown inFIG. 3, the second integrated circuit208further comprises a second shield325to shield the second light emitter portion317from electromagnetic radiation. As also shown inFIG. 3, the first light emitter portion307and the second light-sensitive area313are adjacent to one another in the first integrated circuit204such that a portion of the first shield310is between the first light emitter portion307and the second light-sensitive area313. Similarly, the first light-sensitive area323and the second light emitter portion317are adjacent to one another in the second integrated circuit208such that a portion of the second shield (or second electromagnetic shield)325is between the first light-sensitive area323and the second light emitter portion317. In other words, the first and second shields310/325are at least partially embedded in the first integrated circuit204and the second integrated circuit208, respectively, to shield the first and second light emitter portion310/317from electromagnetic radiation.

The first integrated circuit204includes a buried oxide (BOX) layer340while the second integrated circuit includes a BOX layer345. Layers340and345may be comprised of SiO2or other suitable oxide material. Layers340and345function as an isolator between the light sensitive areas313/323and the remainder of the substrates300/320.

The first integrated circuit204includes a third shield (or electromagnetic shield)303that shields the second light sensitive area313from electromagnetic radiation, and the second integrated circuit208includes a fourth shield (or electromagnetic shield)330that shields the first light sensitive area323from electromagnetic radiation. As shown, the shields303and330may include one or more conductive vias that connect the light sensitive areas313/323to other components in the first and second integrated circuits204/208. For example, the one or more conductive vias may electrically connect the light sensitive areas313/323to the first and second circuitry104/108, respectively.

The shields303/310/325/330may be comprised of Al or other suitable conductive material. For example, the portions of shields303/310/325/330that provide interconnect pads between vias may be formed of Al while the vias may be formed of Cu. The first and second shields310/325may be embedded in the first and second ICs204/208so as to completely surround the sides of respective light emitter portions307/317(seeFIGS. 5A-5C). Shields303/330may be embedded in the first and second ICs204/208so as to completely surround the sides of respective light sensitive portions323/313(seeFIG. 6). InFIG. 3, the shields303/310/325/330may extend all the way through the first and second ICs204/208. However, example embodiments are not limited thereto, and the shields303/310/325/330extend only part of the way through first and second ICs204/208. Alternatively, example embodiments may provide for a combination of shields that extend part of the way through the ICs204/208and shields that extend all the way through ICs204/208.

FIG. 3further shows that the first and second ICs204/208include respective shallow trench isolation regions (STI)335and350to provide additional isolation within each IC.

According to at least one example embodiment, the first shield310is grounded thereby establishing a Faraday shield around the first light emitter portion307, and the second shield325is grounded thereby establishing a Faraday shield around the second light emitter portion317. The third shield303is grounded thereby establishing a Faraday shield around the second light-sensitive area313, and the fourth shield330is grounded thereby establishing a Faraday shield around the first light-sensitive area323. For example, the shields303/310/325/330are grounded via solder bumps on back sides of the substrates300/320(e.g., if the shields303/310/325/330extend all the way through the ICs204/208). In this case, the solder bumps may comprise respective solder bumps to electrically connect portions of the shields303/310/325/330that extend through the ICs204/208. Although four solder bumps have been discussed, it should be understood that fewer or additional solder bumps may be included according to design preferences. For example, additional solder bumps may be electrically connected to the other portions of the shields303/310/325/330that extend through the first and second ICs204/208.FIGS. 7-9illustrate examples of using solder bumps to ground shields in more detail.

As shown inFIG. 3, the first and second light sensitive areas323/313are formed in substrates320and300, respectively. The substrates300/320may be semiconductor substrates comprised of Si (e.g., P-doped silicon) and/or the like. Further, the first and second light emitter portions307/317are formed in regions305and315, respectively. The regions305/315may be oxide regions comprised of SiO2and/or the like.

Although the conductive vias shown inFIG. 3are being formed of multiple intermetal layers, it should be understood that the vias may alternatively be formed as a unitary structure if desired. Further, it should be understood that these vias or intermetal layers include portions that are offset from the light sensitive areas313/323in a plan view so that the light sensitive areas313/323are able to sense optical signals from the first and second light emitter portions307/317. The one or more conductive vias and/or intermetal layers lead to one or more conductive contacts (or pads) at boundaries between the first and second integrated circuits204/208and the isolation material112.

As shown inFIG. 3, the isolation material112is sandwiched between the first integrated circuit204and the second integrated circuit208. The isolation material112may comprise an optically transparent and insulative material that electrically isolates the first and second ICs204and208but allows optical signals to travel between the first and second ICs204and208. In one example embodiment, the isolation material112includes optically transparent and insulative tape, which may assist with adhering the first IC204to the second IC208in the isolation device116. In another example embodiment, the isolation material112comprises a spun-on polyimide.

FIG. 3illustrates various example thicknesses of the first IC204, the second IC208and the isolation material112. In particular, the first IC204and the second IC208have thicknesses between about 0.2 mm and about 0.3 mm while the isolation material112has a thickness of about 0.05 mm. However, example embodiments are not necessarily limited thereto, and the specific thicknesses of the ICs204/208and the isolation material112may vary according to design preferences. For example, the thicknesses may vary so long as a ratio of thicknesses of the first integrated circuit204and the second integrated circuit208to a thickness of the isolation material112is between about 4:1 and about 6:1. That is, a ratio of a thickness of the first integrated circuit204to a thickness of the insulation material112to a thickness of the second integrated circuit208is about 4:1:4 to about 6:1:6.

FIG. 4depicts an example of a light emitter portion313/323according to at least one example embodiment.FIG. 4illustrates how an N+ side of light emitter portions313/323is connected to an electrode405. The electrode405may be comprised of a different material than the shields310/325. For example, the electrode405may include AuGe and provide electrical connectivity between the light emitter portion307/317and metal contacts of the package.

FIGS. 5A-5Cillustrate plan views of the first and second integrated circuits204/208according to at least one example embodiment. The plan views are taken from a top perspective looking down at the N+ regions of the first and second light emitter portions307/317.

With reference toFIGS. 1-4,FIGS. 5A-5Cshow examples of how the first and second shields310/325surround all sides the first and second light emitter portions307/317in a plan view. That is, the first shield310surrounds the first light emitter portion307in the plan view and the second shield325surrounds the second light emitter portion317in the plan view.

As shown inFIGS. 5A-5C, the first light emitter portion307and the second light emitter portion317each include a trace pattern500/505/510on and in electrical connection with a respective N-type material (e.g., N+ region) of the first light emitter portion307and the second light emitter portion317. This may lower the resistance of the N-type material thereby enhancing common mode performance of at least one of the first integrated circuit204and the second integrated circuit208. The trace patterns500/505/510can be considered a portion of the shields310/325that faces the first and second light-sensitive areas323/313and that is sandwiched between the N-type material of each light emitter portion and the isolation material112.

FIG. 5Aillustrates first example trace pattern500that includes a circular portion in electrical contact with a respective N+ region of light emitter portions307/317, and a horizontal linear portion in electrical contact with the circular portion and a respective one of the shields310/325.

FIG. 5Billustrates a second example trace pattern505that includes a circular portion and an X-shaped portion in electrical contact with a respective N+ region of light emitter portions307/317, and a horizontal linear portion in electrical contact with the circular, X-type portion and a respective one of the shields310/325.

FIG. 5Cillustrates a third example trace pattern510that includes a circular portion and vertical linear portions in electrical contact with a respective N+ region of light emitter portions307/317, and a horizontal linear portion in electrical contact with the circular portion and the vertical linear portions and a respective one of the shields310/325.

The trace patterns500/505/510may be formed to cover a desired amount of surface area of the N+ region. Here, the trace patterns505/510cover more surface area of the N+ region than the trace pattern500. Although the trace patterns505/510may block more incoming light from the light emitter portions307/317than trace pattern500, trace patterns505/510may reduce noise compared to trace pattern500.FIGS. 5A and 5Billustrate an example where the trace patterns500/505/510comprise the same material as the shields310/325(e.g., Al), but example embodiments are not limited thereto. Indeed, the shapes, dimensions, and material of the trace patterns500/505/510may vary according to design preferences.

In view ofFIGS. 5A-5Cit may be said that the shields310/325comprise at least one metal strip. As shown, a surface of the light emitter portions307/317facing the photodetectors313/323comprise an outer perimeter, where the at least one metal strip is disposed over the outer perimeter. For example, the at least one metal strip forms a closed loop around the outer perimeter of the surface of the light emitting portions307/317that face the photodetectors323/313.

FIG. 6illustrates a plan view of the first and second integrated circuits204/208according to at least one example embodiment. The plan view is taken from a top perspective looking down onto light sensitive areas313/323. Thus, parts of substrates300/320are shown as surrounding respective N− and N+ regions of the light sensitive areas313/323. Similar to the shields310/325inFIGS. 5A-5C, the shields303/330are formed of at least one metal strip around an outer perimeter of the light sensitive areas313/323. The at least one metal strip forms a closed loop around the outer perimeter.

FIGS. 7-10illustrate various configurations of the isolation system100inFIG. 1according to example embodiments. Accordingly,FIGS. 7-10are discussed with reference toFIGS. 1-6.FIGS. 7-10further show example locations and connections for connecting the top metal and the Faraday shield to a ground voltage or common voltage. InFIGS. 7-10, it should be appreciated that the top metal and Faraday shield may correspond to shields303/310/325/330fromFIGS. 3-6. Thus, the example locations and connections shown inFIGS. 7-10are applicable to the structure ofFIG. 3. Similar to the shields fromFIG. 3, the top metal and the Faraday shield may be comprised of a conductive material, such as Al, Cu, and/or the like.

FIG. 7illustrates an example arrangement of the system fromFIG. 1as system100A. In particular,FIG. 7illustrates an example of stacking the first and second ICs204/208and the isolation material112on a substrate that includes the first and second circuits104/108. The Faraday shield and the top metal are grounded or connected to a common voltage via wire bondings (or bonds)705/710.

As shown inFIG. 7, the first integrated circuit204and the second integrated circuit208are offset from one another such that the wire bonding705is connectable to the Faraday shield at a location on the first integrated circuit204that is adjacent to the second integrated circuit208.FIG. 7further illustrates that wire bonding710is connected to a pad portion on the second IC208, which is in turn connected to the top metal by a conductive copper via.

FIG. 8illustrates another example arrangement of the system fromFIG. 1as system100B. In particular,FIG. 8illustrates an example of sandwiching the first and second ICs204/208and the isolation material112between the first circuit104and the second circuit108. In this case, the second IC208and the second circuit108are bonded to one another via conductive bumps805. As shown, the conductive bumps805are grounded or connected to a first common voltage. As shown, the conductive bumps805are connected to respective pads on the second IC208, which are in turn connected to copper vias that lead to the top metal.

As inFIG. 7, the first IC204and the second IC208are offset so that the first IC204includes a wire bonding810connected to the Faraday shield. The wire bonding810is grounded or connected to a second common voltage in a manner similar to or the same as inFIG. 7. The first and second common voltage can be the same or different.

FIG. 9illustrates an example arrangement of the system fromFIG. 1as system100C. In particular,FIG. 9illustrates an example of stacking the first and second ICs204/208and the isolation material112on a substrate that includes the first and second circuits104/108.

The second IC208includes two pads and wire bondings905that ground the top metal through two copper vias. The first IC204is connected to the substrate with the first and second circuits104/108via conductive bumps910, which ground the Faraday shield through respective pads and copper vias. UnlikeFIGS. 7 and 8, the first and second ICs204/208ofFIG. 9are not offset, but aligned with one another.

FIG. 10illustrates another example arrangement of the system fromFIG. 1as system100D. In particular,FIG. 10illustrates an example of sandwiching the first and second ICs204/208and the isolation material112between the first circuit104and the second circuit108. In this case, the second IC208and the second circuit108are bonded to one another via conductive bumps1005. As shown, the conductive bumps1005are grounded or connected to a common voltage, and the conductive bumps1005are connected to respective pads on the second IC208, which are in turn connected to copper vias that lead to the top metal. The first IC204and the second IC208are aligned with one another.

The first IC204is bonded to the first circuit104using conductive bumps1010. The conductive bumps1010are grounded or connected to a common voltage and ground the Faraday shield through respective pads and copper vias.

With reference toFIGS. 7-10, it should be understood that fewer or additional wire bondings/vias/conductive bumps may be included according to design preferences. It should be understood that the conductive bumps may comprise solder or other suitable conductive/bonding material. Further, the wire bondings/conductive bumps inFIGS. 7-10may connect to one or more ground terminals or common voltage terminals on the first and/or second circuits104/108. Alternatively, the wire bondings/conductive bumps are grounded or connected to a common voltage that is exterior to the first and second circuits104/108.

In view ofFIGS. 1-10, it should be appreciated that the first integrated circuit204and the second integrated circuit208have substantially identical structures. For example, the second integrated circuit208is the same as the first integrated circuit204except flipped upside-down so that the light emitter portions310/317and light sensitive areas323/313align with one another in a vertical direction.

In view ofFIGS. 1-10, when the shields/top metal/Faraday shield are grounded as described above, respective Faraday cages are formed around the first and second light emitter portions307/317and the first and second light-sensitive areas313/323that shield the light emitter portions307/317and the light-sensitive areas313/323from electromagnetic radiation (e.g., external radiation caused by other components of the system).

In view ofFIGS. 1-10, it may be said that the first integrated circuit204comprises a first substrate having a first side and a second side opposing the first side. The first light emitter portion307and the second light sensitive area313are disposed on the first side of the first substrate while the second side of the first substrate is disposed on an external surface (e.g., one or more of circuits204/208).

Further, the second integrated circuit208comprises a second substrate having a first side and a second side opposing the first side, where the second light emitter portion317and the first light sensitive-area323are disposed on the second side of the second substrate that faces the first side of the first integrated circuit204. Further still, the first integrated circuit204comprises a top surface adjacent to the isolation layer112, and the first and second integrated circuits204/208comprise edges that are offset from each other such that a portion of the top surface of the first integrated circuit204is exposed.

At least the first integrated circuit204comprises at least one contact pad disposed on the portion of the top surface of the first integrated circuit204for receiving a first wire bond, and wherein the first wire bond is distanced away from the isolation layer112.

The first integrated circuit204comprises at least one electrically conductive structure (e.g., a via) configured to electrically connect a circuit disposed on a top surface of the first integrated circuit204to at least one contact pad (or pad) disposed on a bottom surface of the first integrated circuit204. The at least one contact pad is configured to receive a solder ball (or conductive bump).

The second integrated circuit208comprises a bottom surface adjacent to the isolation layer112and a top surface that is opposing the bottom surface, and the second integrated circuit208comprises at least one contact pad disposed on the top surface for receiving at least one of a wire bond and a solder ball (or conductive bump).

As can be appreciated, by utilizing the devices and methods as depicted and described herein, an isolation device is realized with a relatively reduced package size and/or footprint. For example, LED structures and light-sensitive areas are formed adjacent to one another on different ICs, which reduces the overall real estate of the isolation device. Light emitting structures in related art optocouplers may be adversely affected by common mode noise. However, example embodiments introduce concepts of grounded metal portions connected to N-regions of LED structures to create a Faraday shield that protects all sides of the LED structures. Furthermore, example embodiments introduce concepts to ground metal portions that surround light sensitive areas to create a Faraday shield that protects all sides of the light sensitive areas.

As can be appreciated, any of the isolators or isolation devices depicted and described herein may be implemented as on-chip solutions (e.g., as a single silicon wafer). In at least one example embodiment, the isolators or isolation devices may be implemented in an Integrated Circuit (IC) chip having other circuit elements provided therein. Moreover, the terms isolator and isolation device may be interchangeable terms as used herein. Indeed, any system, system component, or specific device exhibiting features and/or functions of an electrical isolator as well as an optical coupler may be considered either an isolator or isolation device.

Specific details were given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.