Retain-till-accessed power saving mode in high-performance static memories

Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to commonly assigned U.S. patent application Ser. No. 12/764,369 entitled “Reduced Power Consumption in Retain-Till-Accessed Static Memories”, and Ser. No. 12/764,399 entitled “Combined Write Assist and Retain-Till-Accessed Memory Array Bias”, both filed contemporaneously herewith and incorporated herein by reference.

Not applicable.

BACKGROUND OF THE INVENTION

This invention is in the field of integrated circuits. Embodiments of this invention are more specifically directed to solid-state static random access memories (SRAMs), and power reduction in those SRAMs.

Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now handheld portable devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, and the like. Of course, these systems and devices are battery powered in order to be mobile or handheld. The power consumption of the electronic circuitry in those devices and systems is therefore of great concern, as battery life is often a significant factor in the buying decision as well as in the utility of the device or system.

The computational power of these modern devices and systems is typically provided by one or more processor “cores”, which operate as a digital computer in carrying out its functions. As such, these processor cores generally retrieve executable instructions from memory, perform arithmetic and logical operations on digital data that are also retrieved from memory, and store the results of those operations in memory; other input and output functions for acquiring and outputting the data processed by the processor cores are of course also provided. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.

Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM memory cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data are stored as charge on solid-state capacitors, and must be periodically refreshed in order to be retained. However, SRAM cells draw DC current in order to retain their stored state. Especially as the memory sizes (in number of cells) become large, this DC current can become a substantial factor in battery-powered systems such as mobile telephones and the like.

Advances in semiconductor technology in recent years have enabled shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. However, this physical scaling of device sizes does not necessarily correlate to similar scaling of device electrical characteristics. In the context of SRAM cells, the memory cell transistors at currently-available minimum feature sizes conduct substantial DC current due to sub-threshold leakage and other short channel effects. As such, the sub-micron devices now used to realize SRAM arrays have increased the DC data retention current drawn by those arrays.

Designers have recently adopted circuit-based approaches for reducing power consumed by integrated circuits including large memory arrays. One common approach is to reduce the power supply voltage applied to memory arrays, relative to the power supply voltage applied to logic circuitry and circuitry peripheral to the memory array (e.g., decoders, sense amplifiers, etc.). This approach not only reduces the power consumed by the memory array, but also helps to reduce sub-threshold leakage in the individual cells.

Another circuit-based approach to reducing power consumption involves placing the memory functions within the integrated circuit into a “retention” state when possible. In conventional memories, the power supply voltages applied to the memory array in the retention state are reduced to voltages below that necessary for access, but above the minimum required for data states to be retained in the memory cells (i.e., above the data-state retention voltage, or “DRV”); memory peripheral circuits are also powered down in this retention mode, saving additional power. Typically, both the “Vdd” power supply voltage applied to the loads of SRAM cells (e.g., the source nodes of the p-channel transistors in CMOS SRAM cells) and also well bias voltages are reduced in the retention mode. However, significant recovery time is typically involved in biasing the memory array to an operational state from the retention state.

Recently, an intermediate power-down mode has been implemented in integrated circuits with memory arrays of significant size. This intermediate mode is referred to in the art as “retain-till-accessed”, or “RTA”, and is most often used in those situations in which the memory arrays are split into multiple blocks. In the RTA mode, the peripheral memory circuitry remains fully powered and operational. However, only those block or blocks of the memory array that are being accessed are fully powered; other blocks of the memory that are not being accessed are biased to a reduced array power supply voltage (i.e., above the retention voltage) to reduce power consumption while idle. Well and junction biases (i.e., other than the bias of p-channel MOS source nodes that receive the reduced RTA bias) are typically maintained at the same voltages in RTA mode as in read/write operation, to reduce the recovery time from RTA mode. The power saving provided by the RTA mode can be substantial, especially if some of the larger memory blocks are accessed infrequently. Because of its ability to be applied to individual blocks within a larger-scale integrated circuit, as well as its fast recovery time, the RTA standby mode is now often used with embedded memories in modern mobile Internet devices and smartphones, considering that these devices remain powered-on but not fully active for much of their useful life.

From a circuit standpoint, integrated circuit memories having an RTA mode must include circuitry that establishes the reduced RTA array bias voltage, and that switchably controls entry into and exit from RTA mode during operation.FIG. 1ais a block diagram of a conventional integrated circuit2in which such RTA standby is provided. Integrated circuit2includes memory array5, arranged into multiple memory array blocks60through63of different sizes relative to one another. Each memory array block6is associated with corresponding decode and read/write circuitry11that addresses, writes data to, and reads data from its associated memory array block6. Integrated circuit2also includes functional and power management circuitry4, which includes the logic functionality provided by integrated circuit2, and also circuitry for regulating and distributing power supply voltages throughout integrated circuit2. For purposes of this example of memory array5, functional and power management circuitry4produces a voltage on power supply line VddHDR that is sufficient for memory read and write operations. Functional and power management circuitry4also produces a “periphery” power supply voltage on power supply line VddP, which is applied to decoder and read/write circuitry11and is typically at a different voltage from that of the power supply voltage on line VddHDR applied to memory array5during reads and writes, as known in the art. The actual array power supply voltage applied to each memory array block60through63is presented on power supply lines VddAR0through VddAR3, respectively. The voltages on lines VddAR0through VddAR3are defined by way of bias/switch circuits70through73, respectively, and based on the voltage at power supply line VddHDR, as will be described below.

Each memory array block6in this conventional integrated circuit2is constructed as an array of SRAM cells arranged in rows and columns. As shown inFIG. 1bby the example of six-transistor (6-T) memory cell12j,k, which is in the jthrow and kthcolumn of one of memory array blocks6, each SRAM memory cell12is biased between the voltage on power supply line VddAR and a reference voltage (e.g., at ground reference Vss). SRAM memory cell12j,kin this case is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel transistor13pand n-channel transistor13n, and the other inverter of series-connected p-channel transistor14pand n-channel transistor14n; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. N-channel pass transistors15a,15bhave their source/drain paths connected between one of the cross-coupled nodes and a corresponding one of complementary bit lines BLk, BL*k, respectively; the gates of pass transistors15a,15bare driven by word line WLjfor the row. Accordingly, as known in the art, DC current drawn by SRAM cell12j,kamounts to the sum of the off-state source/drain leakage currents through one of p-channel transistors13p,14pand one of re-channel transistors13n,14n, plus any gate oxide leakage and junction leakage that may be present. As mentioned above, if transistors13,14are extremely small sub-micron devices, these leakage currents can be significant (as much as 1 nA per memory cell), and can thus result in significant overall standby power consumption if the number of memory cells12in memory array blocks6is large.

Referring back toFIG. 1a, memory array blocks60through63may be independently biased into RTA mode in this conventional integrated circuit2, by operation of bias/switch circuits70through73, respectively. The construction of bias/switch circuit71is illustrated inFIG. 1aby way of example. P-channel transistor8is connected in diode fashion, with its source at power supply line VddHDR and its drain and gate connected to node VddAR1; the voltage drop across transistor8from the voltage at line VddHDR thus establishes voltage on power supply line VddAR1. Shorting transistor9is a relatively large p-channel power transistor with its source/drain path connected between power supply line VddHDR and power supply line VddAR1, and its gate receiving control signal RTA*1from functional and power management circuitry4. If memory array block61is being accessed for a read or write operation, control signal RTA*1is driven to a low logic level, which turns on transistor9in bias/switch circuit71and shorts out diode8, setting the voltage at line VddAR1at that of power supply line VddHDR. Conversely, if memory array block61is to be placed in RTA mode, functional and power management circuitry4will drive control signal RTA*1to a high logic level. This turns off transistor9in bias/switch circuit71, such that the voltage drop across diode8establishes the voltage at node VddAR1at a lower voltage (by one diode drop) than the voltage at power supply line VddHDR. In this RTA mode, therefore, the power consumed by memory array block61will be reduced by an amount corresponding to at least the square of this voltage reduction. Meanwhile in this RTA mode, periphery power supply line VddP applied to peripheral memory circuitry, such as decoder and read/write circuitry11for each memory array block6, carries its normal operating voltage, so that this peripheral circuitry is ready to perform an access of its associated memory array block.

It has been observed, in connection with this invention, that it is difficult to optimize the power savings in RTA mode for memory arrays constructed in the conventional fashion. As known in the art, stored data in the SRAM may be lost if the array voltage falls below a minimum data retention bias voltage; conversely, power savings is optimized by biasing the array blocks in RTA mode at a voltage close to that minimum data retention voltage. However, it is difficult to achieve this optimization because of variations in voltage, temperature, and manufacturing parameters; selection of the size and construction of diodes8in the example ofFIG. 1ato maximize power savings is thus a difficult proposition. In addition, it is now common practice to use different size transistors in the memory cells12of memory array blocks6of different size; these differences in device sizes create additional difficulty in establishing an optimal RTA array block bias.

It has also been observed, in connection with this invention, that RTA bias optimization is made more difficult by the manner in which conventional integrated circuits with embedded memory arrays are constructed. This conventional construction is shown by way of integrated circuit2ofFIG. 1a, in which diodes8in bias/switch circuits7are constructed as part of “core” region3including functional and power management circuitry4. In this core region3, transistors are constructed substantially differently than the transistors in memory array5, for example constructed with different channel lengths, different source/drain impurity concentrations via different ion implantation parameters, different gate oxide thicknesses, and the like, relative transistors in SRAM cells12. For example, according to a conventional 28 nm CMOS manufacturing technology, memory array transistors receive such additional processing as a fluorine implant to increase the effective gate oxide thickness and reduce gate leakage, which the core transistors do not receive; other differences between core and array transistors include different “pocket” implants to implement different threshold voltages for the core and array transistors, and the use of strain engineering techniques to construct the core transistors (e.g., selectively depositing a tensile silicon nitride film over core NMOS transistors and a compressive silicon nitride film over core PMOS transistors) but not to construct the array devices. As described in U.S. patent application Publication US 2009/0258471 A1, published Oct. 15, 2009 and entitled “Application of Different Isolation Schemes for Logic and Embedded Memory”, commonly assigned with this application and incorporated herein by reference, the isolation structures and isolation doping profiles used in logic core regions of the integrated circuit may differ from those used in the memory arrays, so that tighter isolation spacing can be attained in the memory array. In summary, conventional integrated circuits often include logic core (“core”) devices that are constructed to optimize switching performance, while the array devices are constructed for low leakage and low mismatch variation. These differences in construction between transistors in core region3and transistors13,14in memory array5reduce the ability of diodes8to match transistors13,14over variations in process parameters. Additional margin must therefore be provided in selecting the construction of diodes8and the resulting voltage drop, to ensure that the minimum data retention voltage is satisfied, but this additional margin necessarily leads to additional standby power consumption.

As mentioned above, it is known in the art to use different size transistors to realize memory cells12in memory array blocks6of different size. Typically, memory array blocks6are grouped according to the number of bits (i.e., number of columns, if a common number of rows per block is enforced), with common transistor sizes based on the group. For example, thirty-two row memory array blocks6may be grouped into “bins” of increasing transistor size (W/L): from 16 to 128 columns; from 129 to 256 columns; from 257 to 320 columns, and from 321 to 512 columns. By way of further background, it is also known in the art to provide different size core device diodes8for memory array blocks6realized by transistors of different sizes. For example, the W/L of p-channel MOS diodes8may range from 1.0/0.75 (μm) for memory array blocks6of 16 to 128 columns, 1.5/0.065 for memory array blocks6of 129 to 256 columns, 2.5/0.055 for memory array blocks6of 257 to 320 columns, and 5.0/0.045 for memory array blocks6of 321 to 512 columns in size. Even according to this approach, however, it has been observed, in connection with this invention, that a large margin must still be provided for the RTA voltage, because of the wide variation in leakage with variations in power supply voltage, temperature, and process variations, as well as the variation in leakage current drawn with the number of columns in memory array blocks6even within a given bin. As such, while this “binning” reduces somewhat the leakage current drawn in the RTA mode, the RTA bias voltage must still be maintained well above the data retention voltage (DRV), and is thus not optimized.

Even though conventional RTA mode circuitry has greatly reduced the recovery time from RTA mode to normal operation, as compared with the recovery time from a retention or a full power-down mode, the recovery time from RTA mode remains sufficiently long as to be unacceptable in certain high performance applications. As such, many very large scale integrated circuits, such as the well-known “system on a chip” (or “SoC”) integrated circuits, include both high density SRAM memory, in which RTA mode and other power savings techniques are realized, and also high performance SRAM memory. Logic functionality in the integrated circuit determines which type of data to store in these different types of SRAM memory.

The lack of RTA mode in high performance SRAM memory comes at a substantial power dissipation penalty, even if the high performance SRAM capacity is minimized. For example, in one conventional SoC implementation constructed with submicron feature size technology, the memory density realized in high performance SRAM is about ⅓ that realized in high density SRAM. However, it has been observed that the high performance SRAM consumes as much power, in its data retention mode without RTA bias, as that consumed by all of the high density memory in its RTA mode.

By way of further background, some conventional high performance SRAM memories are now realized by way of eight transistor (“8-T”) memory cells, constructed by way of a 6-T latch as shown inFIG. 1b, in combination with a two-transistor read buffer. An example of this 8-T construction is illustrated inFIG. 1cin connection with SRAM cell12′j,k(in row j and column k, as before). Cell12′j,kincludes the 6-T latch of transistors13p,13n,14p,14n,15a,15b, as described above relative toFIG. 1b. However, in cell12′j,k, write word line WR_WLjconnected to the gates of pass transistors15a,15bis asserted only for the jthrow in write cycles, to connect storage nodes S1, S2to complementary write bit lines WR_BLk, WR_BL*kfor the kthcolumn. In a write to cell12′j,k, write circuitry (not shown) pulls one of write bit lines WR_BLk, WR_BL*kto ground, depending on the data state being written into cell12′j,k. Cell12′j,kalso includes n-channel transistors16n,18n, which have their source-drain paths connected in series between read bit line RD_BLkand ground. Read buffer pass transistor18nhas its drain connected to read bit line RD_BLk, and its gate receiving read word line RD_WLjfor row j. Read buffer driver transistor16nhas its drain connected to the source of transistor18nand its source at ground; the gate of transistor16nis connected to storage node S2. In a read of cell12′j,k, read word line RD_WLjis asserted active high, which turns on buffer pass transistor18nif the data state of storage node S2is a “1”; in this case, read bit line RD_BLkis pulled to ground by buffer driver transistor16nthrough buffer pass transistor18n. A read of cell12′j,kin the case in which storage node S2is a “0” results in transistor16nremaining off, in which case read bit line RD_BLkis not pulled down. A sense amplifier (not shown) is capable of detecting whether read bit line RD_BLkis pulled to ground by the selected cell in column k, and in turn communicates that data state to I/O circuitry as appropriate.

By way of still further background, the 8-T concept described in connection withFIG. 1cis further extended, in some conventional SRAM memories, to provide complementary read bit lines. An example of this extended structure is illustrated by way of cell12″j,kshown inFIG. 1d. Cell12″j,kincludes the eight transistors of cell12′j,kshown inFIG. 1c, but also includes transistors16n′,18n′that forward the data state at storage node S1to complementary read bit line RD_BL*k, in similar fashion as transistors16n,18nforward the state at storage node S2to read bitline RD_BLk. In a read cycle, enabled by read word line RD_WLjdriven active high, which turns on transistors18n,18n′, a differential signal is generated on read bit lines RD_BLk, RD_BL*kaccording to the states at storage nodes S2, S1. SRAM cells constructed as shown inFIG. 1dare referred to in the art as “10-T” cells.

BRIEF SUMMARY OF THE INVENTION

Embodiments of this invention provide a high performance static random access memory (SRAM) in which a reduced array bias is provided in a retain-till-accessed (RTA) in a manner that minimizes power consumption due to cell leakage in the RTA mode.

Embodiments of this invention provide such an SRAM in which the RTA mode array bias is useful in SRAM memories with separate read and write bit lines and word lines, such as those SRAMs realized by 8-T or 10-T CMOS SRAM cells.

Embodiments of this invention provide such an SRAM that minimizes the chip area penalty for the devices establishing the RTA mode array bias.

Other objects and advantages provided by embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.

Embodiments of this invention can be realized by constructing a static random access memory (SRAM) array constructed of 8-T or 10-T memory cells, for which separate read and write bit lines are provided. A bias device is included in series between a ground reference potential and the driver transistors in each memory cell of a given column or columns. The bias device reduces the power supply voltage across the memory cells in a reduced power mode, such as retain-till-accessed (RTA) mode.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described in connection with its preferred embodiment, namely as implemented into an integrated circuit including an embedded memory array, and constructed according to complementary metal-oxide-semiconductor (CMOS) technology. However, it is contemplated that the benefits of this invention may be attained when realized in other applications and constructed according to other technologies. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.

Referring now toFIG. 2, by way of example, integrated circuit20constructed according to embodiments of this invention will now be described at a block diagram level. As shown inFIG. 2, integrated circuit20includes functional circuitry23, power management circuitry24, and memory array25. The functionality provided by functional circuitry23may vary widely depending on the desired application. For example, if integrated circuit20is a large-scale device such as a “system on a chip”, functional circuitry23may correspond to programmable logic circuitry such as a microprocessor or digital signal processor core, along with the corresponding support and interface circuitry of which memory array25and its peripheral circuitry would serve as an embedded memory resource; at another extreme, integrated circuit20may be a stand-alone memory device, in which case functional circuitry23would provide the support and interface circuitry for accessing memory array25. As such, in embodiments of this invention, the construction and capability of functional circuitry23can correspond to any of a wide array of possibilities.

According to embodiments of this invention, memory array25is arranged as multiple memory array blocks260through263. In this example, memory array blocks260through263are of different sizes relative to one another, but of course need not be. While four memory array blocks260through263are shown, memory array25may be realized by as few as one memory block26, or by more than four memory array blocks260through263, depending on the particular application. Each memory array block26is associated with corresponding decode and read/write circuitry21, which is involved in the addressing of memory cells in its associated memory array block26, including the reading and writing of stored contents.

Power management circuitry24regulates and distributes power supply voltages throughout integrated circuit20. According to embodiments of this invention, power management circuitry24applies, to power supply line VDD, a power supply voltage sufficient to enable read and write operations to memory cells within memory array blocks26. Power management circuitry24also produces and controls other power supply voltages, such as applied to decoder and read/write circuitry21, functional circuitry23, and power management circuitry24itself. Typically, power management circuitry24generates these and other power supply voltages from an external power supply voltage, which in this case is shown inFIG. 2by external power supply terminal Vdd. Power management circuitry24may also include charge pump circuits or other functions that provide negative or other reference bias voltages, for example as applied to wells or substrate connections within integrated circuit20, as conventional in the art. In some embodiments of this invention, power management circuitry24includes bandgap reference circuit19as shown inFIG. 2.

In connection with the operation of memory array25, according to embodiments of this invention, memory array blocks260through263are associated with corresponding sets of bias devices270through273, respectively. Bias devices270through273are each connected to ground reference voltage line Vss, which in this case is a ground voltage level received from an external terminal as shown; alternatively, reference voltage line Vssmay carry a reference voltage generated by power management circuitry24, at a voltage other than external chip ground. As will be described in further detail below, bias devices270through273define corresponding reference voltages on sets of lines VSSF0through VSSF3, respectively, relative to the ground reference voltage on line Vss. Each set of reference voltage lines VSSF0through VSSF3includes one or more separate reference voltage lines connected to SRAM cells in its associated memory array block260through263, respectively. A connection between ground reference line Vssand each set of ground reference lines VSSF0through VSSF3for each memory array block260through263, respectively, is also made by way of respective sets of one or more switches290through293. As shown by way of example inFIG. 2, switch291is constructed as an n-channel MOS transistor with its source/drain path connected between its corresponding ground reference line VSSF1and ground line Vss, and with its gate driven by control signal RTA*1generated by power management circuitry24. Alternatively, other control circuitry within integrated circuit20may generate the control signals RTA*m, in each of the embodiments of the invention described herein. As will become apparent from the following description, a single switch29mmay be realized for a corresponding memory array block26m, or multiple switches29mmay be provided for memory array block26m. Switches (or sets of switches, as the case may be)290,292,293are similarly constructed and connected in the same manner as switch29k. Of course, switches29may be constructed according to any other suitable device type or structure, depending on the desired manner in which its function described below is to be carried out. It is contemplated that these switches29will be realized by relatively large transistors, to provide ample drive when turned on, as will be discussed below.

According to embodiments of this invention, memory array blocks26are each constructed as conventional high-performance CMOS static random access memory (RAM) memory cells, arranged in rows and columns. As will be described in further detail below, these memory cells are constructed as 8-T CMOS SRAM cells, with separate word lines and bit lines for read and write data paths, as will be described in further detail below. Alternatively, the memory cells of memory array blocks26may be even more complex 10-T CMOS SRAM cells in which differential lines are used for both of the read and write data paths. In any event, it is contemplated that the memory cells realizing memory array blocks26will consume some level of DC current from a power supply voltage to a ground reference voltage in retaining stored data states.

According to modern CMOS technologies, the types of transistors used to realize memory array25can differ dramatically from those used elsewhere in integrated circuit20. For example, the “array” type of transistors used to realize memory array25can be of minimum feature size (i.e., channel length), and fabricated in a different manner than the “core” transistors used to realize logic and power management functionality, to minimize the chip area required for memory array25while maintaining high performance devices in the core and periphery. In contrast, core transistors are fabricated to maximize switching performance, typically at a cost of increased chip area and process complexity. For example, to minimize gate leakage, memory array25transistors can receive an additional fluorine implant to increase the effective gate oxide thickness (e.g., by about 1 Å), while core region23transistors do not receive such an implant. Conversely, to improve performance, core region23transistors can be fabricated using conventional strain engineering techniques (e.g., selectively depositing a tensile silicon nitride film over core NMOS transistors and a compressive silicon nitride film over core PMOS transistors), while memory array25transistors do not receive such processing. The core and array transistors may also have significant differences in “pocket” implants that result in different threshold voltages relative to one another. As described in U.S. patent application Publication US 2009/0258471 A1, published Oct. 15, 2009 and entitled “Application of Different Isolation Schemes for Logic and Embedded Memory”, commonly assigned with this application and incorporated herein by reference, the isolation structures and isolation doping profiles used in core region23can differ from those used in the memory arrays, so that tighter isolation spacing and thus higher device density can be attained in memory array25. As evident from this description to those skilled in the art, these processing differences of transistors in core region23relative to transistors in memory array25involve structures that are relatively early in the manufacturing process (i.e., “base level” differences), rather than at the higher levels such as interconnections and metal conductor routing. As such, substantial chip area penalty would be involved if one were to construct a core transistor physically within memory array25. According to embodiments of this invention, memory array blocks26are realized within areas of integrated circuit20realized by array transistors and not core transistors; conversely, the transistors of core region23are formed in areas away from memory array blocks26. Memory periphery functions such as decoder and read/write circuitry21can be constructed as core devices, for example in areas of integrated circuit20near or adjacent to, but outside of, corresponding memory array blocks26.

According to embodiments of this invention, each memory array block26in memory array25is capable of operating in a retain-till-accessed (RTA) mode, in which the voltage across each memory cell is reduced to a level above the data retention voltage (DRV), but in which its associated peripheral circuitry such as decoder and read/write circuitry21remains fully biased. As will be described below, in embodiments of this invention, each switch29mserves to short its reference voltage line VSSFmto ground reference voltage line Vssduring such time as power management circuitry24determines that its memory array block26mis not in RTA mode (i.e., its control signal RTA*mis active low). Conversely, if a memory array block26mis in RTA mode, its switch29mis open, permitting its bias devices27mto establish a voltage on line or lines VSSFmthat is above the ground voltage at line Vss, thus reducing the power consumed by memory array block26mby reducing the voltage drop across its cells.

As will be evident from the following description, the arrangement of integrated circuit20shown inFIG. 2provides important advantages in optimizing the power reduction available in RTA mode for high-performance SRAM memories in which separate read and write data paths to the SRAM cells are provided. These advantages include the ability to reduce the bias across high-performance SRAM cells without impacting the read current from those SRAM cells, and with a reduced recovery time penalty, both effects of significant importance in high-performance SRAM implementations. In addition, embodiments of this invention enable additional power reduction by providing enhanced back-gate or body node bias to the pass transistors in these SRAM cells. Furthermore, embodiments of this invention enable closer matching of bias devices27to the corresponding memory array blocks26, especially if the transistor sizes among the various memory array blocks26vary from block-to-block. This improved matching enables the RTA bias level to be set closer to the DRV for the specific construction of the memory cells in each block, without risking data loss. In addition, according to some embodiments of the invention, the matching and margin of the voltage drop in RTA mode is facilitated by construction of bias devices27as array devices, rather than as core devices; in some embodiments of the invention, this construction is attained with minimal chip area penalty. These and other advantages of this invention will become apparent from the following description.

The construction and operation of an instance of bias device27m,krelative to one of SRAM cells22j,kin column k of its associated memory array block26mis shown in further detail inFIG. 3, for the example of an 8-T SRAM cell22j,k. Cell22j,kis constructed in a similar manner as described above with reference toFIG. 1c, with the same reference numerals used to refer to like elements. Cell22j,kincludes a 6-T latch of transistors13p,13n,14p,14n,15a,15bconnected to form a pair of cross-coupled CMOS inverters (one inverter of series-connected p-channel transistor13pand n-channel transistor13n, and the other inverter of series-connected p-channel transistor14pand re-channel transistor14n) where the gates of the transistors in each inverter are connected together and to the storage node (S1, S2) of the other inverter, in the usual manner. N-channel pass transistors15a,15bhave their source/drain paths connected between one of the cross-coupled nodes S1, S2and a corresponding one of differential write bit lines WR_BLk, WR_BL*k, respectively; the gates of pass transistors15a,15bare driven by write word line WR_WLjfor the row. Cell22j,kalso includes a 2-T read buffer formed of n-channel transistors16n,18nthat have their source-drain paths connected in series between read bit line RD_BLkand ground reference voltage line Vss. Read buffer pass transistor18nhas its drain connected to read bit line RD_BLkand its gate receiving read word line RD_WLjfor row j. Read buffer driver transistor16nhas its drain connected to the source of transistor18nand its source at ground reference voltage line Vss; the gate of transistor16nis connected to storage node S2; alternatively, the ground reference voltage to which the source of transistor16nis connected may be a separately switched circuit ground, to eliminate leakage during standby or otherwise non-accessed times.

In cell22j,k, the cross-coupled inverters are connected between power supply line VDD and reference voltage line VSSFm,k. As will be described in further detail below, reference voltage line VSSFm,kis dedicated to column k in memory array block26mwith its voltage defined by a corresponding instance of bias device27m,k. Alternatively, each reference voltage line VSSFmmay support a group of columns in memory array block26m. Further in the alternative, each reference voltage line VSSFmmay support all columns in memory array block26m, with its voltage defined by multiple bias devices27min parallel with one another. In any case, the source nodes of driver transistors13n,14nare connected to reference voltage line VSSFm,k. In this embodiment of the invention, the body nodes (i.e., back gate bias nodes) of n-channel transistors13n,14n,15a,15bare connected to ground reference voltage line Vss. In this manner, as will become apparent from the following description, the voltage drop across cell22j,k(i.e., the voltage drop between power supply line VDD and reference voltage line VSSFm,k) can be reduced in RTA mode, while advantageously maintaining a back-gate bias on pass transistors15a,15band thus further reducing leakage.

As shown inFIG. 3, bias device27m,khas its drain and gate connected to reference voltage line VSSFm,k, and has its source connected to ground reference voltage line Vss. As known in the art, the voltage drop across a forward biased diode depends on the diode threshold voltage, and also on the current drawn through the diode; in general, the voltage drop across a diode of a given current capacity (W/L ratio) will increase with increasing current. As such, the size (i.e., channel width and channel length) of each bias device27mcan be selected to define the desired voltage drop from reference voltage line VSSFm,kto ground reference line Vss, for an expected level of leakage current for its associated SRAM cells22. The feature sizes for bias device27m,kis therefore not necessarily at the minimum feature sizes as may be used within SRAM cells22; however, especially if bias device27m,kis realized as an “array” transistor placed within the memory array region of memory array block26m, layout efficiency is optimized if the feature sizes of bias devices27mmatch those of the transistors of SRAM cells22, as proximity effects can be avoided.

Switch29mhas its source-drain path connected across the source-drain path of bias device27m,k, and its gate controlled by control signal RTA*m. In this embodiment of the invention, switch29mis constructed as a “core” device. Each bias device27mmay be associated with a corresponding instance of switch29m. Alternatively, a single instance of switch29mmay be used to short out, in parallel, all of bias devices27mfor memory array block26m. Particularly in high-performance SRAM memories, such as memory array block26mincluding 8-T cells22, it is preferred that reference voltage line VSSFm,krapidly reach the voltage of ground reference voltage line Vssupon the exit of RTA mode with transistor29mbeing turned on. As such, switch29mis preferably a relatively large transistor (i.e., with high drive capability) and is preferably constructed for high speed switching and conduction, in the manner of core transistors described above. This large size and core transistor construction is best accomplished by placing switch29min core region23of integrated circuit20, outside of memory array region25, and distributed across multiple columns.

In normal operation (i.e., non-RTA mode) for reads and writes to memory array block26m, switch29mis turned on by power management circuitry24asserting an active high logic level as control signal RTA*m. To effect a write operation to cell22j,k, write word line WR_WLjat the gates of pass transistors15a,15bis asserted for selected row j, turning on pass transistors15a,15band coupling storage nodes S1, S2to complementary write bit lines WR_BLk, WR_BL*kfor column k. Read word line RD_WLjremains inactive low during this time, and transistors16n,18ndo not affect the write to cell22j,k. Write circuitry (not shown) will pull one of complementary write bit lines WR_BLk, WR_BL*kto ground reference voltage line Vssaccording to the data state being written into cell22j,k. This causes the corresponding storage node S1, S2connected to that bit line WR_BLk, WR_BL*kto also be pulled to ground. Upon release of write word line WR_WLj, this state remains latched into cell22j,k. Conversely, in a read operation, read word line RD_WLjis asserted active high, and write word line WR_WLjremains inactive low. In this single-ended construction of cell22j,kas shown inFIG. 3, transistor16nis then turned on if storage node S2is latched to a high logic level, in which case read bit line RD_BLkis pulled to ground reference voltage line Vss. If storage node S2is latched to a low logic level, transistor16nwill remain off, and read bit line RD_BLkwill essentially remain at its precharged level. A sense amplifier (not shown) is capable of detecting whether read bit line RD_BLkis pulled to ground by the selected cell in column k, and in turn communicates that data state to I/O circuitry as appropriate.

In RTA mode, power management circuitry24turns switch29moff, by way of an inactive low level on control signal line RTAm. In this mode, the voltage at the source nodes of driver transistors13n,14nin each cell22j,kin memory array block26mwill rise (due to leakage from power supply line VDD through cells22j,k) until it reaches a voltage that is a threshold voltage above that of ground reference voltage line Vss, namely at about the forward-biased threshold voltage drop of the diode-connected n-channel MOS transistor used to realize bias device27k,min this example, as modulated by any current-dependent voltage modulation. Of course, while in this RTA mode, both read word line RD_WLjand write word line WR_WLkare maintained inactive low.

This embodiment of the invention provides important advantages as applied to high-performance 8-T (and, by extension, 10-T) SRAM cells such as cell22j,k. One such advantage is the ability to fully read cell22j,kimmediately upon exit from RTA mode, without a degradation of the read current. Consider, for example, the case in which cell22j,kofFIG. 4is storing a “1” level at storage node S2(i.e., and thus a “0” level at storage node S1). In this case, if read word line RD_WLjcan be driven active high immediately upon exit from RTA mode, even if reference voltage line VSSFm,khas not yet fully discharged to ground reference voltage line Vss, the “1” level at storage node S2is reflected by a full read current level drawn from read bit line RD_BL through transistors16n,18n. This full current results from the source of transistor16nbeing directly connected to ground reference voltage line Vss, and because load transistor14pat node S2is biased to the full voltage at power supply line VDD (that voltage being applied to the gate of transistor16nin the read cycle). The current at read bit line RD_BLkis therefore not degraded even though cell22j,khas not fully recovered from RTA mode. In contrast, conventional RTA bias techniques applied by way of “header” devices such as described inFIG. 1awould result in reduced read current during recovery from RTA mode, because of the reduced Vddlevel that would reduce the drive applied to the gate of transistor16n.

Secondly, this embodiment of the invention serves to reduce the DC leakage drawn by cell22j,kin the RTA mode. As known in the art, bias of the body node (back gate) of an n-channel transistor to a negative voltage, below the voltage at its source, will have the effect of increasing the threshold voltage of the transistor. In the situation of SRAM cell22j,kofFIG. 3, the body nodes of driver transistors13n,14nare biased to ground reference voltage line Vss, which is below the voltage at reference voltage line VSSFm,kduring RTA mode (i.e., one threshold voltage above Vss). The effective threshold voltage of transistors13n,14nis increased during RTA mode as a result, which reduces the sub-threshold leakage through the one of transistors13n,14nthat is nominally off based on the stored state in cell22j,k(e.g., transistor14nif storage node S2is latched to a “1”). Accordingly, in addition to the reduction in DC leakage due to a reduced voltage drop across each cell22j,kin memory array block26min RTA mode, this embodiment of the invention further reduces the DC leakage by providing a negative back gate bias for pass transistors15a,15bin cell22j,kin this manner. By way of simulation, it has been observed that the DC leakage reduction provided by this back gate bias can be on the order of 25%.

In addition, it has been observed that this embodiment of the invention allows faster access upon exit from RTA mode if an optimum bit line precharge voltage is used. As shown inFIG. 3, precharge circuitry31is provided to precharge the voltage of write bit lines WR_BLk, WR_BL*kprior to each cycle; in this case, precharge circuitry31includes p-channel MOS transistors32a,32bwith source-drain paths connected between write bit lines WR_BLk, WR_BL*k, respectively, and power supply line VDD. Transistors32a,32beach receive a control signal on line PC from control circuitry (not shown) in integrated circuit20, such as within functional circuitry23, power management circuitry24, or the like. An equalization transistor32ccan also be included, with a source-drain path connected between write bit lines WR_BLk, WR_BL*k, and gate receiving control signal EQ, to ensure that the voltages on write bit lines WR_BLk, WR_BL*kare equalized prior to the cycle. At the appropriate time within each cycle, as known in the art, precharge circuitry31operates to charge the voltages on write bit lines WR_BLk, WR_BL*ktoward the voltage of power supply line VDD.

It has been observed, in connection with the embodiment of the invention shown inFIG. 3, that SRAM cells22can be accessed for write access earlier during the recovery time from RTA mode, before reference voltage line VSSFm,kis fully discharged to line Vssvia switch29m, if the precharge voltage to write bit lines WR_BLk, WR_BL*kis reduced to about 70% to 80% of its normal full level. In the example illustrated above inFIG. 3, this reduced precharge voltage can be attained by applying the appropriate voltage as control signal PC, or via the timing of control signal PC, or by using n-channel transistors connected in diode fashion in place of precharge transistors32a,32b. According to conventional architecture, the write bit line precharge voltage is nominally at that of power supply line VDD, for example at about 1.0 volts. According to this embodiment of the invention, it has been observed that a write bit line precharge voltage of about 0.7 volts, or from a range of about 0.6 volts to about 0.8 volts, allows earlier access to SRAM cells22upon RTA exit, without increasing the risk of disturbing the states of “half-selected” cells (i.e., those in a selected row but not a selected column). Good stability performance of these “half-selected” cells has been observed using this reduced write bit line precharge conditions even while reference voltage line VSSFm,kis still at 0.15 volts above the voltage of ground reference line Vss. This has been observed to translate into an access time advantage of 150 psec, relative to the time at which full discharge of reference voltage line VSSFmoccurs.

The cell stability provided by embodiments of this invention in this case of reduced write bit line precharge enables alternative methods of accessing cells22that can even further reduce power consumption. As discussed above, 8-T cell22(or a 10-T version with differential read buffers) produce a full read current level even if reference voltage line VSSFm,khas not yet fully discharged to ground reference voltage line Vss, because read buffer driver transistor16nis biased directly to Vss. As such, it has been observed, in connection with this invention, that switch29mmay remain off even during normal read operation, for both selected and unselected cells22, with no significant degradation in performance or cell stability. In this case, the reduced power consumption of the RTA mode can be attained even during active read cycles. In this arrangement and with the reduced write bit line precharge voltage, switch29mmay be turned on only during write operations, and may remain off during read cycles. In this case, also as mentioned above, the actual write access of cells22may begin before full restoration of the Vssvoltage at reference voltage line VSSFm,kthrough the action of switch29m. Further in the alternative, switch29mmay actually remain off also during write cycles, if somewhat reduced write performance is acceptable; in this case, power management circuitry24or other control circuitry may selectively turn on switch29min a margin screening test mode, in order to carry out device screening in manufacture. In the extreme, switch29mmay be eliminated altogether.

The architecture of bias devices27mand switches29mfor a memory array block26maccording to an embodiment of the invention will now be described in connection withFIG. 4a. In the portion of memory array block26mshown inFIG. 4a, SRAM cells22in two columns k, k+1, and three rows j, j+1, j+2 are illustrated by way of example, it being understood that memory array block26mwill likely include many more cells22in more columns and rows. For example, memory array blocks260through263may each have on the order of sixteen to sixty-four rows, and from as few as sixteen columns to as many as 512 columns or more. SRAM cells22in the arrangement ofFIG. 4aare constructed as described above in connection withFIG. 3. In this architecture, SRAM cells22in the same row share the same write word line and read word line (e.g., SRAM cells22j,kand22j,keach receive word lines WR_WLjand RD_WLj), and SRAM cells in the same column are coupled to the same write bit line pair (e.g., SRAM cells22j,k,22j+1,k,22j+2,kare each connected to write bit lines WR_BLk, WR_BL*k) and read bit line (RD_BLk).

In this embodiment of the invention, each column of SRAM cells22in memory array block26mis associated with an instance of a bias device27m. More specifically, SRAM cells22that are associated with write bit lines WR_BLk, WR_BL*kand read bit line RD_BLk(i.e., SRAM cells22in column k) are associated with bias device27m,k; similarly, SRAM cells22in column k+1 are associated with bias device27m,k+1. In other words, the number of bias devices27massociated with memory array block26mequals the number of columns of SRAM cells22in memory array block26m.

In addition, in this embodiment of the invention, each column of SRAM cells22in memory array block26mreceives its own dedicated reference voltage line, as shown by way of reference voltage lines VSSFm,k, VSSFm,kfor columns k, k+1, respectively, inFIG. 4a. As described above in connection withFIG. 3, these reference voltage lines VSSFm,k, VSSFm,k+1bias the source nodes of drive transistors13n,14nin the 6-T latch of each SRAM cell22in their respective columns k, k+1.

In this embodiment of the invention, referring to bias device27m,kby way of example, bias device27m,kis connected as an n-channel MOS diode with its anode at its associated reference voltage line VSSFm,kand its cathode at ground reference voltage line Vss. Each bias device27massociated with memory array block26mis constructed and connected in a similar manner. This connection is, of course, obtained by the gate and drain of the n-channel transistor constituting bias device27m,kbeing connected to reference voltage line VSSFm,k, and the source of this transistor connected to ground reference voltage line Vss. Also in this embodiment of the invention, an instance of switch29mis associated with each column, as shown inFIG. 4aby the examples of switches29m,k,29m,k+1associated with columns k, k+1, respectively. As described above in connection withFIG. 3, switches29m,k,29m,k+1in this example are each constituted by an n-channel MOS transistor with its drain at the respective reference voltage line VSSFm,k, VSSFm,k+1, its source at ground reference voltage line Vssand its gate receiving control signal RTA*m.

This individual placement of individual switches29m,k,29m,k+1per column assists rapid exit from RTA mode. Specifically, it is contemplated that the R-C delay involved in shorting reference voltage lines VSSFm,kto ground reference voltage line Vssis greatly reduced by providing these column-by-column switches29m,k,29m,k+1, as compared with using a single switch29mfor the entire memory array block260. Of course, this improved RTA mode exit performance comes at the cost of chip area for realizing these multiple devices; it is contemplated that those skilled in the art having reference to this specification can evaluate this and other trade-offs for each particular design and architecture.

In this architecture, because multiple switches29m,k,29m,k+1are provided for memory array block26m, only those switches29m,kassociated with half-addressed columns need be turned on in a write operation. In this alternative approach, the RTA*mcontrol signals applied to the gates of switches29m,kwill also depend on the column address; as such, these individualized control signals may be generated by decoder circuitry21rather than directly by power management circuitry24(FIG. 2). This approach takes advantage of the improved write performance resulting from the reduced cell voltage as described above, by allowing column-selected cells22in the selected row that are to be written in the write cycle, but not the “half-selected” columns, to receive the raised bias at their reference voltage lines VSSFm,kresulting from their corresponding switch29m,kremaining off. Also in this case, provision may be made to selectively turn on switches29mfor these selected columns in a special margin screening or test mode, in order to carry out device screening in manufacture. In addition, the reduced bit line precharge voltage described above may also be applied in this embodiment of the invention, to assist cell stability.

FIG. 4billustrates an alternative realization of this embodiment of the invention, in connection with array portion26′m. The construction of array portion26′mis essentially identical with that shown inFIG. 4a, with the exception that multiple bias devices27mare connected in parallel with one another between a shared reference voltage line VSSFmand ground reference voltage line Vss. All bias devices27massociated with memory array block26mmay be connected in parallel in this fashion, or bias devices27mmay be grouped into a few groups, connected in parallel within each group. This parallel connection essentially establishes the RTA-mode voltage drop from reference voltage line VSSFmand ground reference voltage line Vssas an average of the diode drops across the parallel-connected bias devices27m. As a result, a more robust reference voltage is defined at line VSSFm, with reduced vulnerability to defects in a single one of bias devices27m, and better tolerance to device mismatches caused by fabrication. This parallel connection also smoothes the effects of any mismatch and variations that are present.

The parallel connection of bias devices27maccording to this architecture shown inFIG. 4breduces the number of transistors required for switch29mfor memory block array26m. As shown inFIG. 4b, switch29mis realized by a single n-channel MOS transistor with its drain at reference voltage line VSSFm, its source at ground reference voltage line Vssand its gate receiving control signal RTA*m. As such, switch29mis connected in parallel with bias devices27mand serves to short out all such bias devices27mthat are connected in parallel. If, as mentioned above, multiple groups of parallel-connected bias devices27mare provided, it is contemplated that separate instances of switch29m, at least one for each such group, will be provided. Of course, as mentioned above, a larger number of columns and bias devices27supported by each switch29can involve a larger R-C delay for the shorting action of switch29.

In this example, each column of memory array block26mis associated with an instance of bias devices27m. According to this parallel bias device architecture, however, more or fewer than one bias device27mper column may be implemented, depending on layout considerations and the desired characteristics for entry into and exit from RTA mode. In addition, also as mentioned above, the voltage drop across an instance of bias device27mwill depend not only on its diode threshold voltage, but also on the current drawn through the diode; in general, the voltage drop across a diode of a given current capacity (W/L ratio) will increase with increasing current. In this embodiment of the invention, the current conducted by an instance of bias device27mdepends on the number of columns it supports. Selection of the RTA mode voltage drop across bias devices27mcan thus be made by selecting the number of parallel-connected bias devices27mimplemented to source the expected leakage current of memory array block26m. It is contemplated that those skilled in the art having reference to this specification will be readily able to determine the number and placement of bias devices27and corresponding switches29according to this parallel-connected embodiment of the invention, in a manner best suited for particular technologies and design constraints.

It is further contemplated that one skilled in the art, having reference to this specification, will be readily able to realize and layout bias devices27and their corresponding switches29, according to embodiments of this invention, in an efficient manner for a particular implementation, in a manner compatible with the construction of corresponding SRAM cells22. A generalized layout of a portion of integrated circuit20at the surface of a semiconductor substrate or other semiconducting body (e.g., the active surface of a silicon-on-insulator layer), illustrating the relative placement of devices according to embodiments of the invention, is shown inFIG. 5a.

In this layout for embodiments of the invention, two memory array blocks260,261are shown at the surface. Each of memory array blocks260,261in this arrangement have a similar number of rows (running horizontally inFIG. 5a). In this example, a “break” is provided in the layout between memory array blocks260,261, within which circuitry such as local sense amplifiers35, write circuits, column decoder circuitry, and the like is placed as shown inFIG. 5a. Switches290,291(whether realized as one per memory array block26, or one per column, or therebetween) are also placed within the break between memory array blocks260,261along with local sense amplifiers35.

In this embodiment of the invention, “core” transistors are used to realize functional circuitry23, power management circuitry24, and local sense amplifiers35. Core transistors are also used, in this embodiment of the invention, to realize switches29, to provide high levels of drive for switches29so that RTA mode can be rapidly exited, as described above. Conversely, in this example, bias devices27are each constructed as a diode-connected “array” transistor, fabricated by the same process steps and process parameters as used to fabricate n-channel transistors13n,14nin each of SRAM cells22. As a result, bias devices27mcan be physically placed within the same region as associated memory array block26m. This placement is illustrated inFIG. 5aby an instance of memory array region25within which memory array block260and its bias devices270are placed. Another instance of memory array region25contains memory array block261and its bias devices271.

If bias devices27are realized as array transistors as in this embodiment of the invention, it has been observed that the chip area required is relatively modest. For example, the construction of bias devices27as array transistors within memory array region25can be accomplished by relatively simple and efficient means, accomplished by photomask patterns, and often only at “higher” levels (contact, metal). For example, it has been observed that realization of bias devices27occupies the chip area of about an additional half-row of SRAM cells22(i.e., about an additional 1.5% of the total chip area of a thirty-two row memory array block). It is contemplated that, in most cases, this chip area cost is tolerable in order to attain the resulting reduction in RTA-mode power consumption.

As known in the art, modern memory arrays constructed with extremely small (sub-micron) device sizes are best realized by regular and periodic bit cell structures, to avoid proximity effects in photolithographic patterning and asymmetric transistor strain. For example, as known in the art, many memory arrays are constructed to have “dummy” cell structures at their edges, such dummy cells effectively serving as a sacrificial row or column of structures that enable the interior bit cell structures to be free from such proximity effects. In order to most efficiently place bias devices27within the memory array region25, as shown inFIG. 5a, the physical feature sizes (i.e., channel width and length) of the one or more transistors realizing each bias devices27are intended to be about the same as the feature sizes of SRAM cells22. Some variation in feature sizes (i.e., channel width or channel length) may be tolerable, without requiring the insertion of “dummy” devices to absorb proximity effects. In any event, it is preferable to ensure that any such variations do not destroy the periodicity of layout within memory array region25so that “live” SRAM cell structures can be placed adjacent to bias devices27as will be discussed below.

FIG. 5billustrates an alternative placement of bias devices270,271for memory array blocks260,261. In this example, bias devices270,271are constructed as core transistors, in similar manner as local sense amplifiers35, switches29, functional circuitry23(FIG. 2), and the like, differing from the construction of transistors within SRAM cells22. In this case, bias devices270for memory array block260are placed within the break between memory array blocks260,261, outside of memory array region25and along with local sense amplifiers35and corresponding one or more switches290for memory array block260. Bias devices271for memory array block261are also formed as core devices, and reside outside of the memory array region25for memory array block26k, in the break between memory array blocks260,261along with local sense amplifiers35and switches291, among other circuitry as desired. In this case, the feature sizes and current capacity of bias devices27can be selected independently from the feature sizes of transistors in SRAM cells22, enabling the designer to tune the voltage drop across bias devices27in the RTA mode.

Those skilled in the art having reference to this specification will readily comprehend alternative embodiments of this invention, and alternative implementations of the embodiments of the invention described in this specification.FIG. 6aillustrates SRAM cell22j,k, constructed as described above in connection withFIG. 3, connected to bias device37m,kaccording to an alternative embodiment of the invention. Similarly as described above, bias device37m,kis a p-channel MOS transistor with its source connected to reference voltage line VSSFm,kfor memory array block26min which SRAM cell22j,kresides, and its drain at ground reference voltage line Vss. Switch29m,kfor column k of memory array block26mhas its source-drain path connected in parallel with that of bias device37m,k, and in parallel with that of all bias devices37mfor memory array block26mas described above.

In this example, however, bias device37m,kis not diode-connected as in the embodiment of the invention described above in connection withFIG. 3. Rather, the gate of bias device37m,kis driven by reference bias voltage Vbggenerated by power management circuitry24, for example by bandgap reference voltage circuit19within power management circuitry24as shown inFIG. 2, or elsewhere, as the case may be. In this embodiment of the invention, reference bias voltage Vbgis selected to determine the drain-to-source voltage drop across bias device37m,kin RTA mode, such that the voltage drop across SRAM cells22m,kcan be set at a voltage different from that defined simply by the device threshold voltage, as in the case ofFIG. 3.

According to this embodiment of the invention, as before, bias device37mmay be deployed one-per-column, in the manner described above relative toFIG. 4a, in fewer numbers than the number of columns in memory array block26m; multiple bias devices37mmay also be connected in parallel in the manner described above relative toFIG. 4b. In any event, all bias devices37massociated with memory array block26mwould have their gates connected in common to receive reference bias voltage Vbgas shown inFIG. 6afor bias device37m,k.

The operation of this embodiment of the invention follows that described above in connection withFIG. 3. It is contemplated, in such operation, that the voltage on line Vbgcan remain constant in the RTA and normal operation mode, considering that switch29m,kcontrols whether the ground reference voltage on line Vssor the higher reference voltage defined by its bias device37m,kappears at reference voltage line VSSFm,k.

In any event, bias devices37mprovide similar advantages in defining an RTA mode bias for memory array block26mas described above in connection withFIGS. 3,4a, and4b. In summary, the voltage drop across cells22is reduced for the RTA mode while still permitting rapid read operations immediately upon exit from the RTA mode, with little or no impact on the read current seen at read bit lines RD_BLk. Selection of the appropriate write bit line precharge voltage, as described above, can further optimize cell access times during exit from RTA mode. In addition, back gate bias to the pass transistors15a,15bin SRAM cells22is provided, further reducing the DC leakage in RTA mode. Bias devices37mcan be constructed either as array transistors or as core transistors, as described above relative toFIGS. 5aand5b.

Various alternatives to these embodiments of the invention are also contemplated. For example, bias device37mmay be alternatively realized in a diode-connected fashion with its source at reference voltage line VSSFm,kand its gate and drain connected to ground reference voltage line Vss. In addition, the embodiments of this invention described above utilize single transistor bias devices. According to another embodiment of this invention, the bias devices for establishing the reference voltage applied to these high-performance SRAM cells, in RTA mode, each include more than one transistor. An example of this embodiment of the invention will now be described in detail, with reference toFIG. 6b.

In the example ofFIG. 6b, bias device47m,kis constructed as a pair of transistors48,49with their source-drain paths connected in series between reference voltage line VSSFm,kand ground reference voltage line Vss. In this example, n-channel transistor48is diode-connected, with its gate and drain at reference voltage line VSSFm,kand its body node (back gate) biased by ground reference voltage line Vss. P-channel transistor49has its source connected to the source of transistor48, its drain connected to ground reference voltage line Vss, and its gate receiving reference bias voltage Vbgas generated by bandgap voltage generator19or other circuitry within integrated circuit20. As before, bias device47m,khas an associated switch29m,kconnected in parallel with it between reference voltage line VSSFm,kand ground reference voltage line Vss. Reference voltage line VSSFm,kbiases the source nodes of n-channel driver transistors13n,14nin each SRAM cell22of column k, while ground reference voltage line biases the 2-T read buffer in each of those cells22, as described above in connection withFIG. 3.

In the RTA mode (switch29m,kturned off), the voltage at reference voltage line VSSFm,kis defined by the sum of the voltage drops across transistors48,49as leakage current conducts through SRAM cells22. The voltage drop across transistor48amounts to about the threshold voltage of diode-connected transistor48, considering the back gate bias of transistor48from ground reference voltage line Vss, and the voltage drop across transistor49is controlled by the bias voltage Vbgapplied to its gate. It is contemplated that those skilled in the art can readily determine the voltage defined by bias device47m,kin the RTA mode, for a given implementation and bias voltage Vbg.

Typically, the use of multiple series-connected transistors to realize bias device47m,kwill result in a higher voltage at reference voltage line VSSFm,k, relative to ground reference voltage line Vss, than if a single transistor is used in the previously-described embodiments of the invention. As a result, the use of multiple devices such as shown inFIG. 6bwill generally be best used in those situations in which the voltage between power supply voltage line VDD and ground reference voltage line Vssis relatively large. For example, in some modern integrated circuits, a 1.8 volt Vddpower supply is available, which is substantially higher than typical array power supply voltages of about 1.10 volts. This embodiment of the invention, in which bias device47m,kis realized by the series connection of two transistors48,49, is well-suited for such high power supply voltage applications, particularly if the data retention voltage remains relatively low (e.g., 0.65 volts).

As before, the number of bias devices47m,kprovided for a given memory array block26mmay vary from one-per-column to either more or fewer than one-per-column, depending on design and layout constraints. In addition, as described above, it is contemplated that the bias devices47massociated with a memory array block26mcan either be connected to a single column, or connected in parallel for robust performance and stable definition of the RTA mode bias voltage. Still further in the alternative, while n-channel MOS transistor48and p-channel MOS transistor49are shown as realizing bias device47m,kinFIG. 6bfor this embodiment of the invention, it is contemplated that either or both of these transistors may alternatively be realized as a p-channel transistor, with the gate connection and applied voltages modified to correspond to that channel conductivity type of device.

In any event, the embodiment of this invention shown inFIG. 6bprovides the benefits of enabling fast recovery from RTA mode and minimal read current degradation for 8-T and 10-T SRAM cells22during that recovery time, and of decreased DC current draw because of the lower-voltage and back gate bias of pass transistors15a,15bIn addition, if bias devices47are constructed as array devices, excellent device matching with the transistors of SRAM cells22can result, allowing the resulting RTA power supply bias to be placed closer to the data retention voltage.

It is contemplated that additional alternatives and variations to the embodiments of this invention described above will be apparent to those skilled in the art having reference to this specification, such alternatives and variations including the implementation of these approaches in solid-state memories of various types, constructed according to various technologies, and as may be embedded within larger-scale integrated circuits. Therefore, while the present invention has been described according to some of its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.