Self-aligned bipolar transistor without spacers and method for fabricating same

According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness.

BACKGROUND OF THE INVENTION

This application is a continuation in part of, and claims benefit of the filing date of, and hereby incorporates fully by reference, a parent application entitled “Method for Fabricating a Self-Aligned Bipolar Transistor and Related Structure,” Ser. No. 10/218,527 filed Aug. 13, 2002, and now U.S. Pat. No. 6,784,467 and assigned to the assignee of the present application. This application also hereby incorporates fully by reference a related U.S. patent application entitled “Method for Fabricating a Self-Aligned Emitter in a Bipolar Transistor” Ser. No. 09/721,344 filed Nov. 22, 2000, issued as U.S. Pat. No. 6,534,372, and assigned to the assignee of the present application.

1. Field of the Invention

The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of bipolar transistors.

2. Background Art

As modern electronic devices increase in speed while decreasing in size and price, semiconductor manufacturers are challenged to provide low-cost, high speed, and small size transistors for these devices. To meet this challenge, semiconductor manufacturers must accurately control the size of certain features that critically affect the performance of transistors on a semiconductor wafer, such as emitter widths of bipolar transistors. Furthermore, various parts of the bipolar transistor must be properly aligned to ensure that the bipolar transistor meets performance requirements. For example, the emitter and the extrinsic base implant in a heterojunction bipolar transistor (HBT) must be properly aligned to prevent an undesirable increase in base resistance.

In one conventional fabrication process for a bipolar transistor, such as an HBT, semiconductor manufacturers utilize a first photomask to control the bipolar transistor's emitter width, which is generally referred to as a critical dimension, or “CD.” A second photomask, which must be properly aligned with the first photomask, is utilized to determine the boundaries of the heavily doped extrinsic base regions of the bipolar transistor. Misalignment of the two photomasks causes, among other things, problems in manufacturability of the bipolar transistor. Additionally, in the two-photomask fabrication process described above, the first photomask must be accurately controlled to control the emitter width of the bipolar transistor. Also, misalignment of the two photomasks can cause an undesirable reduction in manufacturing yield, which can cause a corresponding increase in manufacturing cost.

Other fabrication processes and tools have been tried in attempts to solve the problem of aligning the extrinsic base to the emitter in bipolar transistor devices. One approach requires the use of selective epitaxy along with the use of an inside spacer. Selective epitaxy presents a problem in that it is not currently used in high volume production of semiconductor devices. Selective epitaxy presents another problem in that selective epitaxial deposition occurs only on silicon regions and not on oxide regions. Since most process monitoring is done on oxide regions, selective epitaxy results in a substantial loss of process monitoring capability. Use of an inside spacer presents a further problem in that variability of emitter width is greater than with other methods, so some accuracy in control of emitter width is lost.

In addition, as feature sizes of bipolar devices are reduced, it is important and more difficult to achieve accurate control over the size of certain features, such as the emitter width of the bipolar transistor.

Thus, there is need in the art for a fabrication process for bipolar transistors which does not rely on the alignment of separate photomasks to form the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region.

SUMMARY OF THE INVENTION

The present invention is directed to self-aligned bipolar transistors without spacers and method for fabricating same. The present invention addresses and resolves the need in the art for a fabrication process for bipolar transistors which does not rely on the alignment of separate photomasks to form the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region of the bipolar transistor.

According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor may be, for example, a heterojunction bipolar transistor, a silicon-germanium heterojunction bipolar transistor, or a silicon-germanium-carbon heterojunction bipolar transistor. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a second side of the sacrificial post, where the conformal layer is not separated from the first and second sides of the sacrificial post by spacers.

According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”). The sacrificial planarizing layer has a first thickness in a first region between the first and second sides of the sacrificial post and a second thickness in a second region outside of the first and second sides of the sacrificial post, where the second thickness is greater than the first thickness. In another embodiment, the present invention is a method that achieves the above-described bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to self-aligned bipolar transistors without spacers and method for fabricating same. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order to not obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.

FIG. 1shows exemplary structure100, which is utilized to describe the present invention. Certain details and features have been left out ofFIG. 1, which are apparent to a person of ordinary skill in the art. Structure100includes collector102and base120for a bipolar transistor. The present invention applies, in general, to any bipolar transistor, including a heterojunction bipolar transistor (“HBT”). For example, the present invention applies to NPN or PNP HBTs comprising silicon, silicon-germanium, gallium-arsenide, or other materials. In particular, the present invention applies to silicon-germanium-carbon HBTs where carbon is used as a diffusion suppressant. However, the present application makes specific reference to a silicon-germanium (“SiGe”) NPN bipolar transistor as an aid to describe an embodiment of the present invention. In the present embodiment, collector102is N type single crystal silicon that can be formed using a dopant diffusion process in a manner known in the art. In the present embodiment, base120is P type SiGe single crystal that might be deposited epitaxially in a low-pressure chemical vapor deposition (“LPCVD”) process. Base120may be implanted with boron ions to achieve the aforementioned P type doping. As seen inFIG. 1, base120is situated on top of, and forms a junction with, collector102. In the present embodiment, base contact122is polycrystalline SiGe that may be deposited epitaxially in a LPCVD process. Base120and base contact122connect with each other at interface124between the contact polycrystalline material and the base single crystal material. Base120has a top surface126.

As seen inFIG. 1, buried layer106, which is composed of N+ type material, i.e. it is relatively heavily doped N type material, is formed in silicon substrate107in a manner known in the art. Collector sinker108, also comprised of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker108down to buried layer106. Buried layer106, along with collector sinker108, provide a low resistance electrical pathway from collector102through buried layer106and collector sinker108to a collector contact (the collector contact is not shown in FIG.1). Deep trenches112and field oxide isolation regions114,115, and116may be composed of silicon dioxide (SiO2) material and are formed in a manner known in the art. Deep trenches112and field oxide isolation regions114,115, and116provide electrical isolation from other devices on silicon substrate107in a manner known in the art. Thus,FIG. 1shows that structure100includes several features and components used to form a bipolar transistor at a stage prior to formation of an emitter comprised of N type polycrystalline silicon above base120.

FIG. 2shows flowchart200, which describes the steps, according to one embodiment of the present invention, in the processing of a wafer that includes structure100. Certain details and features have been left out of flowchart200that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art.

While steps270through288indicated in flowchart200are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart200. It is noted that the processing steps shown in flowchart200are performed on a wafer, which, prior to step270, includes structure100shown in FIG.1. In particular, the wafer includes top surface126of base120on which formation of an emitter comprised of N type polycrystalline silicon is to take place in an “emitter window opening.”

Referring now toFIG. 3A, structure300ofFIG. 3Ashows a portion of structure100of FIG.1. Base120and top surface126of structure100are shown in structure300as base320and top surface326, respectively. For ease of illustration, other features such as base contact122, interface124, collector102, buried layer106, silicon substrate107, collector sinker108, deep trenches112, and field oxide regions114,115, and116, are not shown in structure300. Structure300thus shows the portion of a wafer including top surface326of base320, on which the formation of an emitter comprised of N type polycrystalline silicon is to take place in an emitter window opening, before processing the wafer according to one embodiment of the invention shown in flowchart200of FIG.2. In particular, structure300shows a portion of the wafer before processing step270of flowchart200.

Continuing with step270in FIG.2and structure370inFIG. 3B, step270of flowchart200comprises the formation of sacrificial post302over base oxide layer304on top surface324of base320. Base320comprises intrinsic base region309and extrinsic base regions312. Sacrificial post302may be formed by patterning and etching a layer of polycrystalline silicon, which may be deposited over base oxide layer304by chemical vapor deposition (“CVD”), as known in the art. Although polycrystalline silicon is used in one embodiment of the invention described here, it is manifest that any layer of material that is suitable for accurate patterning using a photomask or other patterning techniques may be used. The suitable material forms a temporary layer of material, i.e. sacrificial post302, which is etched away prior to formation of an emitter at a later step in the process. To provide greater control and to achieve the smallest possible emitter width, anti-reflective coating (“ARC”) layer306can be depositing over the layer of polycrystalline silicon before patterning sacrificial post302with photoresist. For example, ARC layer306may be composed of silicon oxynitride. In one embodiment, ARC layer306may not be used. The height of sacrificial post302can be, for example, between approximately 500.0 to 3500.0 Angstroms.

As seen below, sacrificial post width308determines the width of the emitter of the bipolar transistor formed as the result of the sequence of steps according to one embodiment of the present invention. Base oxide layer304prevents damage to base320during the etching used to form sacrificial post302. Base oxide layer304may be formed by depositing a layer of silicon oxide, which may be deposited in a PECVD process at a temperature of approximately 350.0 to 450.0° C., for example. In one embodiment, base oxide layer312has a thickness of approximately 80.0 Angstroms. The result of step270of flowchart200is illustrated by structure370in FIG.3B.

Referring to step272in FIG.2and structure372inFIG. 3C, at step272of flowchart200, portions of base layer304outside of sacrificial post302are removed and extrinsic base regions312are doped. Portions of base layer304outside of sacrificial post302may be removed by utilizing an appropriate etchant to etch away the portions of base layer304in a manner known in the art. Next, extrinsic base regions312are doped by ion implantation to reduce the resistance of extrinsic base regions312. The ion implantation doping uses sacrificial post302as a mask. Thus, doping of extrinsic base regions312is self-aligned, since the doping of exposed extrinsic base regions312is defined by sides303and305of sacrificial post302, and does not depend on the alignment of a photomask. Ion implantation of extrinsic base regions312results in heavily doped P+ implanted regions318within extrinsic base regions312. In one embodiment, the dopant used to form implanted regions318can be boron. Referring toFIG. 3C, the result of step272of flowchart200is illustrated by structure372.

Continuing with step274in FIG.2and structure374inFIG. 3D, at step274of flowchart200, conformal oxide layer322is deposited over ARC layer306on sacrificial post302, on sides303and305of sacrificial post302, and on top surface326of base320. Conformal oxide layer322is situated directly on sides303and305of sacrificial post and may comprise, for example, silicon oxide or other dielectric. Referring toFIG. 3D, the result of step274of flowchart200is illustrated by structure374.

Continuing with step276in FIG.2and structure376inFIG. 3E, at step276of flowchart200, sacrificial planarizing layer324is deposited over conformal oxide layer322. In the present embodiment, sacrificial planarizing layer324is deposited over conformal oxide layer322using a spin-on process. Sacrificial planarizing layer324exhibits a “planarizing” property by coating tall features of structure376, such as sacrificial post302, thinly, while providing a thicker coating of material over shorter features close to sacrificial post302. For example, thickness328of sacrificial planarizing layer324over sacrificial post302can be between approximately 0.0 Angstroms and approximately 2500.0 Angstroms. In contrast, the thickness of sacrificial planarizing layer324over shorter features of structure376, such as the regions outside of the sacrificial post, can be approximately 500.0 to 3500.0 Angstroms or even greater depending on the height of sacrificial post302. In the present embodiment, the above “planarizing” property exhibited by sacrificial planarizing layer324occurs as a result of the material sacrificial planarizing layer324comprises and the spin-on process utilized to deposit sacrificial planarizing layer324. For example, the material sacrificial planarizing layer324comprises must have a sufficiently low viscosity to enable the material to flow during the spin-on process utilized to deposit sacrificial planarizing layer324.

Sacrificial planarizing layer324can be an organic material comprising, for example, carbon, hydrogen, oxygen, and some dopants. In one embodiment, sacrificial planarizing layer324can comprise an organic material, such as an organic BARC. In one embodiment, sacrificial planarizing layer324may comprise an organic material that allows sacrificial planarizing layer324to act as an anti-reflective coating layer. In one embodiment, sacrificial planarizing layer324can be an organic material that may be deposited by an evaporation process. In such embodiment, the deposited organic material may be heated to cause the organic material to flow away from tall features of structure376and collect in shorter regions of structure376. Referring toFIG. 3E, the result of step276of flowchart200is illustrated by structure376.

Continuing with step278in FIG.2and structure378inFIG. 3F, at step278of flowchart200, mask330is deposited on sacrificial planarizing layer324and emitter window opening332is patterned in mask330. In the present embodiment, mask330comprises photoresist. In another embodiment, mask330may comprise another suitable material as is known by a person of ordinary skill in the art. As described above, sacrificial planarizing layer324provides a thin layer of material over sacrificial post302and a thicker layer of material over shorter regions of structure378adjacent to sacrificial post302. Thus, emitter window opening width338can be greater than width308of sacrificial post302, since sacrificial post302will be exposed first during a subsequent etching process, while shorter regions of structure378will remain protected by the thicker layer of material provided by sacrificial planarizing layer324. In one embodiment, emitter window opening width338can be approximately equal to width308of sacrificial post302.

Thus, the present invention does not require edges334and336of emitter window opening332to be situated over sacrificial post302to avoid etching regions of structure378outside of sacrificial post302during subsequent etching steps. In the present embodiment, as thickness328of sacrificial planarizing layer324is decreased to a minimal thickness of approximately 100.0 Angstroms, the present invention advantageously achieves increased flexibility in width338of emitter window opening332. Thus, by providing an emitter window opening that can be made sufficiently large, the present invention advantageously achieves an emitter window opening that requires minimal dimensional and alignment accuracy. In other words, critical dimension control of emitter window opening332is relaxed as emitter window opening width338is increased.

Moreover, absent the technique of the present invention, if the center of emitter window opening332is not properly aligned with the center of sacrificial post302, the resulting misalignment can create undesirable device properties, which can reduce manufacturing yield. For example, absent the present invention's technique, misalignment of the center of emitter window opening332and the center of sacrificial post302can cause edge334or edge336of emitter window opening332to be situated too close to sacrificial post302, which can create undesirable device properties and cause decreased manufacturing yield. However, according to the present invention, width338of emitter window opening332can be increased sufficiently to accommodate alignment error between the center of emitter window opening332and the center of sacrificial post302. Thus, the present invention achieves a bipolar transistor having improved manufacturability, which advantageously results in increased manufacturing yield.

By minimizing thickness328of sacrificial planarizing layer324over sacrificial post302and providing a sufficiently large emitter window opening width, the present invention achieves an emitter window opening that is practically self-aligning over sacrificial post302. In one embodiment, thickness328of sacrificial planarizing layer324over sacrificial post302can be reduced to an appropriate thickness such that mask330is not required at all. In such embodiment, thickness328, for example, may be approximately 10.0 Angstroms or less. Thus, since the thin sacrificial planarizing layer324situated over sacrificial post302is etched first in a subsequent etching step, the resulting emitter window opening is self-aligned over sacrificial post302. In other words, no mask is required to align the emitter window opening over sacrificial post302. Referring toFIG. 3F, the result of step278of flowchart200is illustrated by structure378.

Continuing with step280in FIG.2and structure380inFIG. 3G, at step280of flowchart200, sacrificial planarizing layer324is removed in emitter window opening332to expose conformal oxide layer322and extend emitter window opening332. Sacrificial planarizing layer324may be removed using, for example, a plasma etching and/or a sulfuric wet etch process which are selective to conformal oxide layer322. Referring toFIG. 3G, the result of step280of flowchart200is illustrated by structure380.

Continuing with step282in FIG.2and structure382inFIG. 3H, at step282of flowchart200, conformal oxide layer322and ARC layer306are removed in emitter window opening332to expose sacrificial post302and further extend emitter window opening332. For example, conformal oxide layer322and ARC layer306may be removed using a reactive ion etch stopping on sacrificial post302. After formation of an emitter in emitter window opening332in a subsequent step, the present invention achieves a symmetric emitter topography. Furthermore, the present invention achieves an emitter topography that remains symmetric even if the center of emitter window opening332is not properly aligned with the center of sacrificial post302.

In contrast, in a fabrication process utilizing full-height spacers, where the spacer height is approximately equal to the height of the sacrificial post, misalignment of emitter window opening332causes asymmetrical spacer etching, which results in decreased manufacturability. Thus, by utilizing no spacers to ensure a symmetric emitter topography, the present invention advantageously achieves improved manufacturability compared to a fabrication process utilizing full-height spacers on sides of sacrificial post302. Referring toFIG. 3H, the result of step282of flowchart200is illustrated by structure382.

Continuing with step284in FIG.2and structure384inFIG. 3I, at step284of flowchart200, sacrificial post302is removed in emitter window opening332to expose base oxide layer304. Sacrificial post302may be removed, for example, using a chlorine based etch that stops on base oxide layer304. Referring toFIG. 3I, the result of step284of flowchart200is illustrated by structure384.

Continuing with step286in FIG.2and structure386inFIG. 3J, at step286of flowchart200, mask330and remaining portions of sacrificial planarizing layer324are removed. Mask330and sacrificial planarizing layer324are removed in a two step process. In step one, mask330may be removed, for example, using a plasma etch in a downstream microwave plasma process as known in the art. The plasma etch used in step one also removes sacrificial planarizing layer324. In step two, any remaining sacrificial planarizing layer324material can be removed, for example, using a sulfuric acid wet strip process as known in the art. As a result of performing the two step etch process described above, conformal oxide layer projections329and331are exposed and are situated perpendicular to top surface326of base320. Referring toFIG. 3J, the result of step286of flowchart200is illustrated by structure386.

Referring to step288in FIG.2and structure388inFIG. 3K, at step288of flowchart200, base oxide layer304is removed to complete formation of emitter window opening332, and emitter342is then formed in emitter window opening332. Base oxide layer304may be removed, for example, with a wet strip such as a hydrogen fluoride (“HF”) dip. During removal of base oxide layer304, both sides of conformal oxide layer projections329and331are exposed to the wet strip, while only the top surface of the portion of conformal oxide layer322situated on top surface326of base320is exposed to the wet strip. As a result, the thickness of conformal oxide layer322can be appropriately chosen such that conformal oxide layer projections329and331are removed during removal of base oxide layer304. In one embodiment, the thickness of conformal oxide layer322can be appropriately chosen such that conformal oxide layer projections329and331are not removed during removal of base oxide layer304.

Next, emitter342is formed by depositing a polycrystalline material on top surface326of base320in emitter window opening332. In one embodiment, emitter342can comprise N type polycrystalline silicon. Emitter width344of emitter342is substantially equal to sacrificial post width308in FIG.3B. Also, emitter342is self-aligned by conformal oxide layer edges346and348to extrinsic base regions312. Subsequent steps of patterning emitter342, and forming contacts, as well as other steps, can be performed as known in the art.

As described above, by fabricating a self-aligned bipolar transistor without utilizing spacers, the present invention advantageously achieves a symmetric emitter topography. In contrast, if spacers are utilized to form the self-aligned bipolar transistor, misalignment of the emitter window opening can cause the spacers to be unevenly etched. The resulting asymmetric emitter topography can cause variations in emitter height, which affect the gain of the bipolar transistor. Thus, by providing a symmetric emitter topography, the present invention advantageously achieves a self-aligned bipolar transistor having a gain that is more stable, since there are no spacers that can be unevenly etched to cause variations in emitter height.

By way of background, performance of a bipolar transistor is generally dependent on emitter height, which dependence is undesirable. However, if the height of the emitter is sufficiently reduced, the dependence of bipolar transistor performance on emitter height can be minimized. Thus, by forming an emitter without utilizing spacers to sufficiently reduce emitter height, the present invention advantageously minimizes dependence of bipolar transistor performance on emitter height. Also, by providing an emitter having a desirably small height, the present invention achieves a correspondingly flatter emitter topography, which allows subsequent layers to be more easily processed. Furthermore, by forming an emitter without utilizing spacers, the present invention achieves an emitter having a reduced emitter aspect ratio, which is equal to emitter height divided by emitter width. As a result, the present invention advantageously achieves a self-aligned bipolar transistor with improved emitter scaling.

It is appreciated by the above detailed disclosure that the invention provides method for fabrication of a self-aligned bipolar transistor achieving improved manufacturability by providing an emitter window opening requiring minimal critical dimension control and having increased tolerance for misalignment error. Additionally, by providing a method for fabrication of a self-aligned bipolar transistor without utilizing spacers, the invention advantageously minimizes dependence of transistor performance on emitter height. Although the invention is described as applied to the fabrication of a bipolar transistor, it will be readily apparent to a person of ordinary skill in the art how to apply the invention in a similar situation where improved alignment tolerance and a reduction in critical dimension control is desirable.

From the description of the above invention it is evident that various techniques can be used for implementing the concepts of the present invention without departing from its scope and spirit. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes made in form and detail without departing from the spirit and scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. Therefore, it should be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Thus, self-aligned bipolar transistors without spacers and method for fabricating same have been described.