Curved wafer processing on method and apparatus

An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

BACKGROUND

Reduction of the size and the inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.

To further enhance the performance of metal-oxide semiconductor (MOS) devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (NMOS) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction.

DETAILED DESCRIPTION

FIGS. 1-5illustrate a method for fabricating a semiconductor device having a strained channel region in accordance with an embodiment. Referring first toFIG. 1, a substrate100having gate structure102formed thereon is shown in accordance with an embodiment. The substrate100may comprise bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. The substrate may alternatively be a Ge substrate, a SiGe substrate, a group III-V, II-VI substrate, or the like.

The gate structure102may comprise a gate insulator layer104and a gate electrode106. The gate insulator layer104may be formed of a high-K dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, a combination thereof, or the like. Other examples of such materials include aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, or combinations thereof. Other embodiments may utilize spacers (not shown) formed alongside the gate structure to protect the gate structure during processing.

In an embodiment in which the gate insulator layer104comprises an oxide layer, the gate insulator layer104may be formed by any oxidation process, such as wet or dry thermal oxidation in an ambient comprising an oxide, H2O, NO, or a combination thereof, or by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. Other methods (e.g., ALD) and materials may be used.

The gate electrode106may comprise a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, or ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, or tantalum silicide), a metal nitride (e.g., titanium nitride or tantalum nitride), doped poly-crystalline silicon, other conductive materials, or a combination thereof. In one example, amorphous silicon is deposited and recrystallized to create poly-crystalline silicon (poly-silicon). In an embodiment in which the gate electrode is poly-silicon, the gate electrode106may be formed by depositing doped or undoped poly-silicon by low-pressure CVD (LPCVD).

The gate insulator layer104and the gate electrode106may be patterned by photolithography techniques. Generally, photolithography involves depositing a photoresist material, which is then masked, exposed, and developed. After the photoresist mask is patterned, an etching process may be performed to remove unwanted portions of the gate dielectric material and the gate electrode material to form the gate structure102as illustrated inFIG. 1. In an embodiment in which the gate electrode material is poly-crystalline silicon and the gate dielectric material is an oxide, the etching process may be a wet or dry, anisotropic or isotropic, etch process.

FIG. 1further illustrates recesses110formed on opposing sides of the gate structure102. As discussed in greater detail below, a stress-inducing layer will be epitaxially grown along the bottom of the recesses110. In an embodiment, the recesses110may be etched by, for example, HBr/O2, HBr/Cl2/O2, or SF6/Cl2plasma. One skilled in the art will realize that the dimensions provided throughout the description are merely examples, and the dimensions may vary with the scaling of the technology used for forming the integrated circuits.

Referring now toFIG. 2, there is shown the substrate100attached to a substrate holder212in accordance with an embodiment. The holder212is configured to hold a substrate, such as the substrate100, such that a surface of the substrate is curved. For example, in the embodiment illustrated inFIG. 2, the holder212clasps the substrate100such that a processing surface of the substrate100exhibits a convex shape. In this manner, the width of the recesses110increases. As explained in greater detail below, an epitaxial layer will be grown in these recesses while the recesses are expanded. After the epitaxial layer is grown, the substrate is released from the holder, allowing the substrate100to return to, or near to, the original shape of the substrate100, e.g., return to planar or near-planar.

FIG. 3illustrates the formation of stress-inducing regions314along the bottoms of the recesses110. The material of the stress-inducing regions314is selected such that a lattice mismatch exists between the material of the stress-inducing regions314and the material of the substrate100. One of ordinary skill in the art will also appreciate that the type of materials may be varied depending upon the type of device being formed. For example, in forming a PMOS device using a silicon substrate, the stress-inducing regions314may be formed of SiGe, which has a larger lattice structure than the silicon substrate. The lattice structure of the SiGe stress-inducing regions314causes a compressive stress, indicated by arrows316, in the channel region, thereby increasing the hole mobility. SiGe stress-inducing regions314may be epitaxially grown in a selective epitaxial growth (SEG) process such as CVD using Si-containing gases and Ge-containing gases, such as SiH4and GeH4, respectively, as precursors. Masks may be used to limit the epitaxial growth regions.

When released, the stress-inducing regions314may exert a compressive stress in the channel region greater than that obtained using similar processes and materials on a planar wafer, at least partially due to the epitaxial growth on the curved surface increasing the volume of the recesses. The larger compressive stress is indicated inFIG. 4by larger arrows418, as compared to the smaller compressive stress indicated by the smaller arrows316inFIG. 3.

FIG. 5illustrates formation of silicide regions518in accordance with an embodiment. The embodiment illustrated inFIG. 5may be used individually or with other embodiments within the scope of the current disclosure. Similar to the formation of the stress-inducing regions314discussed above with reference toFIG. 3, the formation of the silicide regions518may also be performed while the surface of the substrate100is in a curved configuration. Generally, the silicide regions518may be formed to decrease contact resistance between the source/drain regions and contact vias extending through an overlying dielectric layer. The silicide regions518may be formed by blanket depositing a thin layer of metal, such as nickel, platinum, cobalt, and combinations thereof and annealing, such as a rapid thermal anneal, thereby causing the silicon to react with the metal where contacted. After the reaction, a layer of metal silicide is formed. The un-reacted metal may then be removed. It is believed that forming the silicide regions518while the substrate100is in a curved configuration helps reduce or avoid stress relaxation of the channel region during processing. In an embodiment, the silicide region518may be formed after the processing illustrated inFIG. 3and before releasing the substrate100illustrated inFIG. 4. Other processes, such as implant or anneal processes, may also be performed while the surface of the substrate100is in a curved configuration.

FIGS. 6 and 7illustrate embodiments similar to those discussed above with reference toFIG. 5, except that the embodiments disclosed inFIGS. 6 and 7utilize a concave processing surface. As noted above, the embodiments discussed above utilizing a convex processing surface may be particularly useful in designing PMOS. For NMOS devices, similar techniques may be utilized wherein a concave processing surface is utilized.

For example,FIG. 6illustrates an embodiment similar to that illustrated inFIG. 5in that stress-inducing regions602are formed in recesses in source/drain regions of a substrate100while the substrate100is in a curved configuration, except that the embodiment illustrated inFIG. 6exhibits a concave processing surface. The substrate100may be placed in a holder606for processing. In this example, when the substrate100comprises a silicon substrate, stress-inducing regions602may be formed of SiC, which has a smaller lattice structure than the silicon substrate100. The lattice structure of the SiC stress-inducing regions602causes a tensile stress (indicated inFIG. 6by arrows608) in the channel regions, thereby increasing the electron mobility. SiC stress-inducing regions602may be epitaxially grown in a SEG process such as CVD using Si-containing gases, such as SiH4, and C-containing gases, such as C2H4or C2H6, as precursors.

FIG. 6also illustrates an embodiment in that silicide regions622are formed while the substrate100is in a curved configuration, except that the embodiment illustrated inFIG. 6exhibits a concave processing surface. The silicide regions622may be formed in a similar manner as discussed above with reference toFIG. 5.

FIG. 7illustrates the substrate100fromFIG. 6after the substrate100has been released. As indicated by arrows708, the stress-inducing regions602exert a tensile stress in the channel region greater than that obtained using similar processes and materials on a planar wafer, at least partially due to the epitaxial growth on the curved surface decreasing the volume of the recesses.

In some embodiments, the holders212(seeFIG. 2) and 606(seeFIG. 6) may comprise a vacuum to help secure the wafer. Embodiments including a vacuum may be desirable wherein a concave processing surface is to be formed such that the vacuum may draw and hold a region of the substrate lower than surrounding regions.

Additionally, the holders212and606are illustrated as being continuous solid pieces for illustrative purposes only. In other embodiments, the holders212and606may comprise ridges, posts, stands, or the like upon which a wafer may rest. Collectively, the ridges, posts, stands, or the like may provide a support surface having a convex or concave shape as discussed above. The holder may further accommodate heating structures, cooling structures, or the like.

FIGS. 8 and 9illustrate other embodiments in which a curved processing surface may be utilized. The configurations illustrated inFIGS. 8 and 9provide an example in which embodiments may be utilized with replacement gate (RPG) processing techniques. Generally, RPG processing techniques involve forming a transistor utilizing a dummy gate structure. The dummy gate structure is then removed and replaced with another gate structure.

Referring first toFIG. 8, there is shown the substrate100having a convex processing surface with a patterned layer830formed thereon. Source/drain regions802may be formed in the substrate100. The patterned layer830may be formed by forming a dummy gate electrode and forming a dielectric layer adjacent to the dummy gate electrode such that the dummy gate electrode is exposed. The dummy gate electrode may then be removed, and the substrate placed in a configuration such that the processing surface of the substrate is convex as illustrated inFIG. 8. The opening left by the dummy gate electrode may be filled with, for example, a metallic material834.

Excess material, if any, may be removed. In an embodiment, the substrate100is released and returned to a planar or near planar configuration, and thereafter, excess metallic material may be removed using, for example, a CMP process or a wet etch.

It is believed that devices formed using processes such as those discussed above may be useful in forming NMOS devices due to higher tensile stress created in the channel region.

FIG. 9illustrates an RPG process using a concave processing surface of a substrate100, which may be useful for forming a PMOS device. Similar materials, techniques, and processes as those discussed above with reference toFIG. 8may be used in this embodiment, wherein like reference numerals refer to like elements, except that the processing surface of the substrate100exhibits a concave shape rather than a convex shape.

FIGS. 10 and 11illustrate yet other embodiments in which a convex or concave surface is utilized in combination with a stress memorization layer. Generally, a stress memorization layer is a layer having a different lattice structure than the underlying structures, such as the substrate, gate electrodes, or the like. The stress memorization layer is applied to the surface and an anneal process is performed, thereby causing the underlying structures to “memorize” the stress imparted by the stress memorization layer.

Referring first toFIG. 10, there is shown the substrate100having a convex processing surface with a stress memorization layer1040formed thereon. The stress memorization layer1040may be blanket formed, before or after a convex processing surface is formed. The stress memorization layer1040may be a single layer, such as a single layer of nitrides, oxynitrides, TEOS, other materials with internal stresses, or the like, or a plurality of layers, such as a layer of an oxide and a layer of a nitride. The stress memorization layer1040may be formed by, for example, LPCVD, plasma enhanced chemical vapor deposition, or the like. The stress memorization layer may be removed after performing an anneal. Embodiments such as that illustrated inFIG. 10may be particularly useful in fabricating, for example, NMOS devices.

FIG. 11illustrates a stress memorization process using a concave processing surface of the substrate100, which may be useful for forming, for example, a PMOS device. Similar materials, techniques, and processes as those discussed above with reference toFIG. 10may be used in this embodiment, wherein like reference numerals refer to like elements, except that the processing surface of the substrate100exhibits a concave shape rather than a convex shape.

FIGS. 12 and 13illustrate yet other embodiments in which a convex or concave processing surface is utilized in formation of a fully strained channel (FSC). Referring first toFIG. 12, a stress-inducing region1212is formed in a recess of a substrate100. The recess and the stress-inducing regions1212may be formed in a similar manner as discussed above with reference toFIGS. 1-4, except whereasFIGS. 1-4formed recesses in the source/drain regions, the embodiment illustrated inFIG. 12forms the recess1210in the channel region. The material of the stress-inducing region1212is selected such that a lattice mismatch exists between the material of the stress-inducing region1212and the material of the substrate100. In an embodiment in which a PMOS device using a silicon substrate is being formed, the stress-inducing region1212may be formed of SiGe. When released, the stress-inducing region1212may exert a compressive stress in the channel region greater than that obtained using similar processes and materials on a planar wafer, at least partially due to the epitaxial growth on the curved surface increasing the volume of the recesses. Embodiments may be applied to planar MOS technology or fin technology (e.g., FinFET).

FIG. 13illustrates a similar embodiment as that illustrated inFIG. 12, except a concave processing surface is utilized rather than a convex processing surface. In particular,FIG. 13illustrates the substrate100having a stress-inducing region1312formed in a recess. In an embodiment in which an NMOS device is being formed and the substrate100comprises a silicon substrate, the stress-inducing region1312may be formed of SiC, which has a smaller lattice structure than the silicon substrate100, thereby causing a tensile stress in the channel regions. The SiC stress-inducing region1312may be epitaxially grown in a SEG process such as CVD using Si-containing gases, such as SiH4, and C-containing gases, such as C2H4or C2H6, as precursors. When released, the stress-inducing region1312may exert a tensile stress in the channel region greater than that obtained using similar processes and materials on a planar wafer, at least partially due to the epitaxial growth on the curved surface increasing the volume of the recesses. The stress-inducing region1312may also be formed of Si on SiGe bilayer or other III-V material or its multilayer. Embodiments may be applied to planar MOS technology or fin technology (e.g., FinFET).

FIG. 14illustrates a curvature that may be used in the embodiments discussed above, in accordance with an embodiment. As shown, the substrate100may have a curvature having a radius of about 100 m to infinity. In an embodiment in which the substrate100comprises a 300 mm wafer, the radius results in the substrate100having a curvature width W of about 0 μm to about 1800 μm, as illustrated inFIG. 14. This curvature width W may be an amount of curvature for either a concave processing surface or a convex processing surface. Other wafer sizes, such as a 450 mm wafer, may also be used.

FIGS.15A1-15D2illustrate various topography patterns that may be applied to a processing surface of a substrate, wherein darker regions represent regions having a higher topography than lighter regions. Accordingly, FIGS.15A1and15A2, wherein FIG.15A2is a cross-sectional view along the A2-A2line of FIG.15A1, represent a topography in which a horizontal center band1510is higher than upper and lower horizontal bands1520, thereby creating a convex processing surface along the A2-A2line. FIGS.15B1and15B2, wherein FIG.15B2is a cross-sectional view along the B2-B2line of FIG.15B1, illustrates a reverse ofFIG. 15A, wherein a horizontal center band1530is lower than upper and lower horizontal bands1540, thereby creating a concave processing surface along the B2-B2line. FIGS.15C1and15C2, wherein FIG.15C2is a cross-sectional view along the C2-C2line of FIG.15C1, represent a topography in which a center region1550is higher than a surrounding region1560, thereby creating a convex processing surface. FIGS.15D1and15D2, wherein FIG.15D2is a cross-sectional view along the D2-D2line of FIG.15D1, represent a topography in which a center region1570is lower than a surrounding region1580, thereby creating a concave processing surface.

FIGS.16A1-16D3represent various types of holders that may be used. It should be noted that the type of holder may be varied dependent upon the topography being used. For example, FIGS.16A1-16A3correspond to types of holders that may be used, for example, with the topography illustrated inFIG. 15A; FIGS.16B1-16B3correspond to types of holders that may be used, for example, with the topography illustrated inFIG. 15B; FIGS.16C1-16C3correspond to types of holders that may be used, for example, with the topography illustrated inFIG. 15C; and FIGS.16D1-16D3correspond to types of holders that may be used, for example, with the topography illustrated inFIG. 15D.

FIGS.16A1,16B1,16C1, and16D1represent holders utilizing point contacts, such as point contacts1610. Embodiments utilizing topography ring such as FIGS.16C1and16D1may utilize more point contacts1610than embodiments utilizing bands such as FIGS.16A1and16B1.

FIGS.16A2,16B2,16C2, and16D2illustrate holders utilizing contact bands1612. As seen in FIGS.16C2and16D2that utilize peripheral topography rings extending along a perhiphery having a different topography than a center region, contact bands1612may be utilized along both axis (e.g., horizontal and vertical) as compared to embodiments illustrated in FIGS.16A2and16B2. FIG.16B2illustrates an embodiment in which contact bands1612are utilized along the horizontal axis with a topography varying only along the vertical axis.

FIGS.16A3,16B3,16C3, and16D3represent holders comprising contact rings extending completely around the substrate.

FIG. 16Eillustrates yet another type of holder in accordance with an embodiment. In this embodiment, a pull force is applied by the holder. This type of pull force may be applied individually or in combination with another type of holder, such as those discussed above. Embodiments such as these may be used to form NMOS or PMOS devices. For example, a pull force may be used to form the RPB for an NMOS device, while a pull force may be used to form epitaxial layers in the source/drain regions or the channel region (e.g., FSC) for a PMOS device.

The holders discussed above may be used to mount a wafer onto. The holder may then be placed into one or more process chambers. In an embodiment, a cluster chamber tool may be used. Generally a cluster tool includes a plurality of process chambers interconnected with a buffer chamber. The process chambers may perform similar processing or each process chambers may perform different processing. For example, the processing chambers may be configured to perform epitaxial growth, annealing, silicidation, nitridation, CVD, PVD, and the like. Interconnected to the buffer chamber may be one or more loadlock chambers. The buffer chamber and the one or more loadlock chambers permit transferring one or more wafers between the process chambers without breaking vacuum between processes or chambers.

The cluster tool may optionally further include a front-opening unified pod (FOUP) docking system and a factory interface. The FOUP docking system and the factory interface allow wafers to be loaded and unloaded without exposing the loadlock chambers, the buffer chamber, and the process chambers to air. In operation, wafers are transferred into and out of the cluster tool, either individually or in batches, via the FOUP docking system. The wafers are transferred from the FOUP docking system to the loadlock chamber via the factory interface. Once transferred into the loadlock chambers, the wafers are isolated from the ambient environment. The wafers are transferred to one or more of the process chambers.

In an embodiment, the wafer and the holder are inserted via the FOUP docking system. The wafer mounted on the holder may then be transferred to one or more of the process chambers.

FIGS. 17A and 17Billustrate another method of forming a non-planar work surface in accordance with other embodiments. Referring first toFIG. 17A, there is shown the substrate100having a compressive stress film1712applied to the backside of the substrate. The compressive stress film1712acts to create a convex processing surface along an opposing surface of the substrate100. After processing is completed, the compressive stress film1712may be removed, thereby allowing the substrate1710to return to planar or near-planar.

In an embodiment, the compressive stress film1712may be formed of SiGe, SiGeN, nitride, oxide, oxynitride, combinations thereof, and the like, formed by a CVD process, a PVD process, an ALD process, or the like. In an embodiment, the compressive stress film1712has a thickness of about 10 nm to about 1000 nm, exerting a compressive stress from about 0.1 GPa to about 20 GPa.

Referring now toFIG. 17B, there is shown the substrate100having a tensile stress film1722formed along a backside thereof. In this embodiment, the tensile stress film1722is utilized to form a concave processing surface. In an embodiment, the tensile stress film1722may be formed of SiN, oxide, oxynitride, SiC, SiCN, Ni silicide, Co silicide, combinations thereof, and the like, formed by a CVD process, a PVD process, an ALD process, or the like. In an embodiment, the tensile stress film1722has a thickness of about 10 nm to about 1,000 nm, exerting a compressive stress from about 0.1 GPa to about 20 GPa. The tensile stress film1722may be removed after processing, thereby allowing the substrate1710to return to planar or near-planar.

In an embodiment, a method of forming a semiconductor structure is provided. The method comprises providing a substrate, curving a processing surface of the substrate, and processing the substrate while the processing surface is curved.

In another embodiment, a method of forming a semiconductor structure is provided. The method comprises providing a substrate comprising a processing surface such that the processing surface of the substrate has a first curvature. The substrate is placed in a holder that is configured to maintain the substrate such that the processing surface exhibits a second curvature, the second curvature having a smaller radius than the first curvature. Thereafter, one or more process steps are performed on the processing surface of the substrate. The substrate is removed from the holder, wherein upon removing the processing surface of the substrate exhibits a third curvature, the third curvature having a greater radius than the second curvature. One or more additional processes may be performed on the substrate.

In yet another embodiment, a substrate holder is provided. The holder comprises one or more wafer support surfaces, the one or more wafer support surfaces collectively being non-planar and one or more connectors configured to hold a wafer on the wafer support surfaces.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, different types of materials and processes may be varied while remaining within the scope of the present disclosure.