Hardware emulation of parallel ATA drives with serial ATA interface

An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

BACKGROUND

1. Field of the Invention

This invention relates to storage interface. In particular, the invention relates to interface to Advanced Technology Attachment (ATA) drives.

2. Description of Related Art

The parallel ATA interface has existed in substantially the same form since 1989, and has become the highest volume disk drive interface in production. However, as demand for higher transfer and storage bandwidths increases, the parallel ATA is nearing its performance limit. Serial ATA interface is introduced to replace parallel ATA. The benefits of serial ATA include high data transfer rates up to 150 MB/s (compared to 100 MB/s for parallel ATA), low cost, easy installation and configuration, low pin count, etc. However, due the large amount of parallel ATA currently in existence, the transition from parallel ATA to serial ATA may be a problem.

Parallel ATA allows up to two devices to be connected to a single port using a master/slave communication technique. One ATA device is configured as a master and the other slave. Both devices are daisy-chained together via one ribbon cable that is an unterminated multidrop bus. This bus or connection is typically referred to as a parallel channel. In addition, a personal computer (PC) may have two parallel ATA channels: a primary channel and a secondary channel.

Serial ATA, on the other hand, connects each of the two drives with individual cables in a point-to-point fashion. Software drivers for parallel ATA have to be modified to accommodate serial ATA. In addition, new serial ATA interface is preferably backward compatible with parallel ATA device drivers to avoid transition costs and provide an easy migration path.

Therefore, there is a need to have an efficient technique to emulate parallel ATA interface in a serial ATA environment.

DESCRIPTION

In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.

FIG. 1is a diagram illustrating a computer system100in which one embodiment of the invention can be practiced. The computer system100includes a processor110, a host bus120, a memory control hub (MCH)130, a Basic Input/Output System memory135, a system memory140, an input/output control hub (ICH)150, serial ATA devices176and178, a mass storage device170, and input/output devices1801to180K.

The processor110represents a central processing unit of any type of architecture, such as embedded processors, micro-controllers, digital signal processors, superscalar computers, vector processors, single instruction multiple data (SIMD) computers, complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. In one embodiment, the processor110is compatible with the Intel Architecture (IA) processor, such as the IA-32 and the IA-64. The processor110typical contains a number of control registers to support memory management tasks such as virtual memory and cache memory. These tasks may include paging and segmentation.

The host bus120provides interface signals to allow the processor110to communicate with other processors or devices, e.g., the MCH130. The host bus120may support a uni-processor or multiprocessor configuration. The host bus120may be parallel, sequential, pipelined, asynchronous, synchronous, or any combination thereof.

The MCH130provides control and configuration of memory and input/output devices such as the system memory140and the ICH150. The MCH130may be integrated into a chipset that integrates multiple functionalities such as the isolated execution mode, host-to-peripheral bus interface, memory control. For clarity, not all the peripheral buses are shown. It is contemplated that the system100may also include peripheral buses such as Peripheral Component Interconnect (PCI), accelerated graphics port (AGP), Industry Standard Architecture (ISA) bus, and Universal Serial Bus (USB), etc.

The BIOS memory135stores boot-up code and data. The BIOS memory135typically is implemented with non-volatile memory such as Read Only Memory (ROM), flash memory, and other similar memories. The BIOS memory135may also be stored inside the MCH130. The BIOS memory135may contain a parallel ATA driver138to control the serial ATA devices176and178via the ICH150.

The system memory140stores system code and data. The system memory140is typically implemented with dynamic random access memory (DRAM) or static random access memory (SRAM). The system memory may include program code or code segments implementing one embodiment of the invention. The system memory may also include a parallel ATA driver145. The parallel ATA driver145may be part of an Operating System (OS) or an application program. The parallel ATA driver145accesses the serial ATA devices176and178via the ICH150. The parallel ATA driver138in the BIOS memory135and the parallel ATA driver145in the memory140may or may not co-exist.

The ICH150has a number of functionalities that are designed to support I/O functions. The ICH150may also be integrated into a chipset together or separate from the MCH130to perform I/O functions. The ICH150may include a number of interface and I/O functions such as PCI bus interface, processor interface, interrupt controller, direct memory access (DMA) controller, power management logic, timer, universal serial bus (USB) interface, mass storage interface, low pin count (LPC) interface, etc. In particular, the ICH150includes an ATA controller155to control serial ATA devices176and178. The ATA controller155has hardware emulator for backward compatibility with the parallel ATA device drivers. The ATA controller155provides a migration path for customers to take advantage of the serial ATA interface while using the existing parallel ATA drivers.

The serial ATA devices176and178are mass storage devices or hard disk to store archive information such as code, programs, files, data, application, operating systems, etc. The serial ATA devices176and178are connected to the hard drive controller155via serial ATA interface signals. The serial ATA interface, protocols, and standards follow the proposed draft entitled “Serial ATA/High Speed Serialized AT Attachment” by the Serial ATA Workgroup, Revision 1.0.0.1, published Apr. 9, 2001. The mass storage device170stores other archive information. The mass storage device170may include compact disk (CD) ROM172, floppy diskettes174, and hard drive176, and any other magnetic or optic storage devices. The mass storage device170provides a mechanism to read machine-readable media.

The I/O devices1801to180Kmay include any I/O devices to perform I/O functions. Examples of I/O devices1801to180Kinclude controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphics), network card, and any other peripheral controllers.

The present invention may be implemented by hardware, software, firmware, microcode, or any combination thereof. When implemented in software, firmware, or microcode, the elements of the present invention are the program code or code segments to perform the necessary tasks. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc. The program or code segments may be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a compact disk (CD-ROM), an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, Intranet, etc.

On a parallel ATA interface, after power-on, a hardware or software reset, or after execution of an Executive Device Diagnostic command, the slave device presents the diagnostic status to the master device via a PDIAG-wire in the ATA ribbon cable. Upon observing the status on the PDIAG-signal, the master device updates the status and error registers accordingly. For serial ATA interface, such direct communication between the two serial ATA devices does not exist. In addition, on a parallel ATA interface, both ATA devices on the same channel observe the signal activity on the cable. For example, the write access to the ATA Command Block registers (except the Data and Command registers) is seen and accepted by both devices. On the other hand, in serial ATA interface, each serial ATA device is independent of the other.

Another difference is the interrupt generation. On parallel ATA interface, the interrupt output pin of the ATA device(s) on the primary channel is routed to the Interrupt Request (IRQ) number14(IRQ14) and the interrupt output pin of the ATA device(s) on the secondary channel is routed to the IRQ15. On the serial ATA interface, a serial ATA device generates an interrupt by sending a Device-to-Host register Frame Information Structure (FIS) or a PIO Setup Frame Information Structure with the I bit set to “1”.

In order to mimic the interaction visible to the parallel ATA driver138, the emulator in the ATA controller155forwards and manipulates software accesses to both serial ATA devices176and178which are mapped as ATA devices on virtual ATA channel. In addition, the emulator also routes the serial ATA devices' interrupt to either IRQ14or IRQ15.

FIG. 2is a diagram illustrating the ATA controller155shown inFIG. 1according to one embodiment of the invention. The ATA controller155includes an emulator210and serial ATA host controllers (1and2)220and230.

The emulator210emulates a response of a parallel ATA device when interacting with the parallel ATA driver138. The emulator210is a hardware circuit that operates transparently to the parallel ATA driver138so that the parallel ATA driver138can still control the serial ATA devices176and178as if they were parallel ATA devices. The emulator210may be disabled when the ATA driver is written directly for the serial ATA devices176and178.

The serial ATA host controllers220and230contain registers, control circuits, and interface circuits to the serial ATA devices176and178, respectively. In particular, the serial ATA host controllers220and230contain the serial port task files225and235, respectively, which contain the operational registers that control and configure the corresponding serial ATA devices176and178. The serial ATA host controller220and230may be referred to as serial ports.

The emulator210selects a serial port as mapped to the parallel channel via the port1select or port2select signals. The emulator210writes data to the selected serial port via the write data signal path and reads data from the selected serial port via the corresponding read data signal paths. The serial ATA host controllers220and230provide the status and error conditions to the emulator210.

FIG. 3is a diagram illustrating the emulator210in the ATA controller shown inFIG. 2according to one embodiment of the invention. The emulator210includes an access detector310, a mapping circuit320, an emulation state machine330, an emulated task file register set340, and a serial port selector350.

The access detector310detects an access type of an access to one of the serial ports220and230interfacing to the serial storage devices176ad178. The access is provided by the parallel ATA driver138and is intended to one of the parallel channels interfacing to parallel storage devices via the task file registers of the parallel channels.

The mapping circuit320maps the serial ports to the parallel channels. The mapping may be done by an address translation. A serial port may be mapped to a master or slave parallel channel according to a device (DEV) bit in the device/head register.

The emulation state machine330emulates a response from one of the parallel channels based on the access type as detected by the access detector310and the mapped serial ports as provided by the mapping circuit320. The state machine330includes a number of states to perform a sequence of operations according to the access type. As will be explained later, there are five states that correspond to emulation of the response according to five different access types and an interrupt state that corresponds to emulation of interrupt generation.

The emulated task file register set340emulates the task file registers of the parallel channels. These registers may include information about the device (DEV), busy (BSY) bits and the error register.

The serial port selector350selects one of the serial ports220and230based on the mapped serial ports provided by the mapping circuit320. For example, when the parallel ATA driver138generates an access to a parallel channel, the mapping circuit320translates the address of the parallel channel into a serial port. This mapping information is passed to the serial port selector350directly or via the state machine330to select the corresponding serial port. The selection may be performed by enabling the selected serial ATA host controller.

FIG. 4is a flowchart illustrating a process400to emulate a response from a parallel channel based on access type according to one embodiment of the invention.

Upon START, the process400detects an access to the serial ATA port which is mapped to a parallel channel, either as a master or slave channel (Block410). The access is made by the parallel ATA driver. Then, the process400determines the type of access (Block420). This can be done by decoding the access information such as addresses and read/write information.

The process400determines if the access is to a bus master register except setting the START bit of Bus Master Command Register to ‘1’, a non-data command register, or a device control register (Block430). If so, the process400emulates a first type access (Block435) and is then terminated. The first type access emulation is explained in FIG.5. Otherwise, the process400determines if the access is to a device/head register (Block440). If so, the process400emulates a second type access (Block445) and is then terminated. The second type access emulation is explained in FIG.6. Otherwise, the process400determines if the access is a read access to a status register, an alternate register, or an error register of a selected serial port mapped to a slave parallel channel after a power-on, hardware or software reset, or an execution of the device diagnostics command (Block450). If so, the process400emulates the third type access (Block455) and is then terminated. The third type access emulation is explained in FIG.7. Otherwise, the process400determines if the access is a read access to a status register or an alternate register of a serial port mapped to a master parallel channel after a power-on, hardware or software reset, or an execution of the device diagnostics command (Block460). If so, the process400emulates the fourth type access (Block465) and is then terminated. The fourth type emulation is explained in FIG.8. Otherwise, the process400determines if the access is a read access to an error register of a serial port mapped to a master parallel channel after a power-on, hardware or software reset, or an execution of the device diagnostics command (Block470). If so, the process400emulates the fifth type access (Block475) and is then terminated. Otherwise, the process400emulates other types (Block485) and is then terminated.

FIG. 5is a flowchart illustrating the process435to emulate a response when the access type is the first access type according to one embodiment of the invention. The process435is performed by the first state in the state machine330shown in FIG.3.

Upon START, the process435determines if the access is a write access (Block510). If so, the process435writes the data to the selected serial port that is mapped to the parallel channel (Block515) and is then terminated. Otherwise, the access is a read access and the process435reads the data from the selected serial port that is mapped to the parallel channel according to the device (DEV) bit (Block520). Then, the process435returns the read data to the access requester and is then terminated.

FIG. 6is a flowchart illustrating the process445to emulate a response when the access type is the second access type according to one embodiment of the invention. The process445is performed by the second state in the state machine330shown in FIG.3.

Upon START, the process445determines if the access is a write access (Block610). If so, the process445writes the data to the selected serial port which is mapped to a master parallel channel (Block620). Then, the process445inverts the device (DEV) bit to the serial port mapped to a slave parallel channel (Block630). Next, the process445saves the DEV value internally (Block640) and is then terminated.

If the access is a read access, the process445determines if the access is a special case which accesses to a slave parallel channel without a serial port mapped to it in a single master configuration (Block650). If so, the process445reads the data from the selected serial port mapped to a master parallel channel (Block670). Then, the process445returns the DEV bit with a logical one (Block680). Next, the process445returns the read data (Block690) and is then terminated.

If the access is not a special case, the process445reads the data from the serial port mapped to the parallel channel according to the DEV bit and returns the internally saved DEV bit (Block660). Then, the process445returns the read data (Block690) and is then terminated.

FIG. 7is a flowchart illustrating the process455to emulate a response when the access type is the third access type according to one embodiment of the invention. The process455is performed by the third state in the state machine330shown in FIG.3.

Upon START, the process455reads the data from the selected serial port mapped to a parallel channel according to the DEV bit (Block710). Then, the process455returns the read data (Block720) and is then terminated.

FIG. 8is a flowchart illustrating the process465to emulate a response when the access type is the fourth access type according to one embodiment of the invention. The process465is performed by the fourth state in the state machine330shown in FIG.3.

Upon START, the process465determines if the access is to a non-existent slave device in a single master configuration (Block810). If so, the process465returns the first status (e.g., “00”) (Block820) and is then terminated. Otherwise, the process465determines if there is absence of both master and slave devices and thus the access is to a non-existent device (Block830). If so, the process465returns the second status (e.g., “7F” in hexadecimal) (Block840) and is then terminated. Otherwise, the process465reads the data from the serial port mapped to the parallel channel (Block850). Then, the process465merges the read data (Block860). Next, the process465performs a logical OR operation on the busy (BSY) bits of the read data (Block870). Then, the process465returns the result of the OR operation and the read data (Block880) and is then terminated.

FIG. 9is a flowchart illustrating the process475to emulate a response when the access type is the fifth access type according to one embodiment of the invention. The process475is performed by the fifth state in the state machine330shown in FIG.3.

Upon START, the process475reads the first error indication from the selected serial port mapped to a master parallel channel (Block910). Next, the process475examines the second error indication of the serial port mapped to a slave parallel channel (Block920). Then, the process475determines if the first error indication indicates a passing status (Block930). If not, the process475goes to Block970. If so, the process475determines if the second error indication indicates a passing or a device-not-present status (Block940). If so, the process475returns a first error code (e.g., “01”) (Block950) and is then terminated. Otherwise, the process475returns a second error code (e.g., “81” in hexadecimal) (Block460) and is then terminated.

At block970, the process475determines if the second error indication indicates a passing status. If so, the process475returns a third error code (e.g., “00” or “02” to “7F” in hexadecimal) (Block980) and is then terminated. Otherwise, the process475returns a fourth error code (e.g., “80” or “82” to “FF” in hexadecimal) and is then terminated.

FIG. 10is a flowchart illustrating a process1000to emulate an interrupt according to one embodiment of the invention. The process1000is perform by an interrupt state of the state machine330shown in FIG.3.

Upon START, the process1000determines if the serial ATA device generate an interrupt (Block1010). This is indicated by the setting of the I bit in the Device-to-Host register FIS or PIO Setup FIS. If not, the process1000is terminated. Otherwise, the process1000determines if the serial port is mapped to a primary parallel channel (Block1020). If so, the process1000generates an interrupt corresponding to the interrupt request (IRQ)14(Block1030). Otherwise, the serial port is mapped to a secondary parallel channel and the process1000generates an interrupt corresponding to the IRQ15(Block1040) and is then terminated.

FIG. 11is a flowchart illustrating the process485to emulate other types according to one embodiment of the invention.

Upon START, the process485determines if the access is a write access (Block1110). If so, the process485writes the data to the selected serial port that is mapped to the parallel channel according to the device (DEV) bit (Block1120) and is then terminated. Otherwise, the access is a read access and the process485reads the data from the selected serial port that is mapped to the parallel channel according to the device (DEV) bit (Block1130). Then, the process485returns the read data to the access requester (Block1140) and is then terminated.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention. For example, although the above description refers to serial and parallel ATA interfaces, the technique can be applied to any point-to-point interface.