DC to DC converter and method to transition the DC to DC converter from a buck mode to a boost mode

A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.

FIELD OF THE INVENTION

This invention relates to a DC to DC converter and a method to operate a DC to DC converter.

BACKGROUND OF THE INVENTION

In the automotive market, DC to DC converters must operate through a wide input voltage range defined by a normal variation of the supplied input voltage as well as by some transient voltages. Such a transient voltage may be, for example, a cranking pulse, i.e., a huge voltage drop that can happen when certain events occur simultaneously, for example, a discharged battery, low temperatures, and the driver attempting to start the car.

A DC to DC converter may be used to compensate such a cranking pulse and may additionally provide an adapted voltage level to connected electronic devices. Such a DC to DC converter may transform an input voltage Vinto an output voltage Vout, wherein the output voltage Voutmay be higher or lower than the input voltage Vin. A DC to DC converter capable of regulating an output voltage regardless of the input voltage Vinis called a buck-boost DC to DC converter. The buck-boost DC to DC converter comprises a buck converter that converts an input voltage Vinto a lower output voltage Voutand a boost converter that converts an input voltage Vinto a higher output voltage Vout. The buck-boost converter may be called non-inverting when the sign of the input voltage Vinis maintained.

The buck-boost DC to DC converter has too provide a constant output voltage Vout. Therefore, a transition between an operation of the buck converter (buck mode) and an operation of the boost converter (boost mode) is necessary when the input voltage Vindrops from a starting value that is higher than the desired output voltage Voutto a final value that is lower than the desired output voltage level Vout. This transition from buck mode to boost mode and vice versa must be managed smoothly and efficiently.

SUMMARY OF THE INVENTION

The present invention provides a DC to DC converter and a method to operate a DC to DC converter as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although the definition of term hereinafter should not be construed as limiting, the term as used are understood to comprise at least the following.

In the context of this specification, the term “switching element” may be used for any electronic element, for example, a generic switch or a transistor that can be changed in its state between “on” and “off”.

The term “on” in connection with the switching element may describe the used electronic element in its closed or conducting state. Further, the term “off” in connection with the switching element may describe the used electronic element in its open or isolating state.

Referring toFIG. 1, a circuit diagram of a first example of a DC to DC converter10is schematically shown. The DC to DC converter10according toFIG. 1may comprise a buck converter12and a boost converter14. The DC to DC converter10may be supplied with an input voltage Vin. The input voltage Vinmay be converted to an output voltage Voutby the DC to DC converter10. An output of the DC to DC converter10may be connected with a load46, and an optional capacitor44may be provided parallel to the load46as part of the DC to DC converter10. A capacity of the capacitor44may be chosen with respect to requirements of the load46. For example, the capacity may be increased to minimize output voltage ripples. When the input voltage Vinis higher than the desired output voltage Vout, the buck converter12of the DC to DC converter10may be active to reduce the input voltage Vin. This operating mode may be called “buck mode”. When the input voltage Vinis lower than the desired output voltage Vout, the boost converter14of the DC to DC converter10may be active to increase the input voltage Vin. This operating mode may be called “boost mode”. The functional principals of the buck converter12and the boost converter14are apparent to a person skilled in the art and will not be explained here in any further detail. Since the DC to DC converter10comprises the buck converter12and the boost converter14, it may be called a buck-boost DC to DC converter.

In the example ofFIG. 1, the buck converter12may comprise a HS (high side) diode38, a HS switching element30, and an inductor42. The boost converter14may comprise a LS (low side) diode40, a LS switching element36, and the inductor42. Thus, the inductor42may be commonly used by the buck converter12and the boost converter14. The HS switching element30and the LS switching element36may be triggered by a control unit not shown inFIG. 1.

The HS switching element30and a LS switching element36may be, for example, metal oxide semiconductor field-effect transistors (MOSFETs). However, any other electronic element that is capable of being used as a switching element may be used. Further, it may be possible to replace the HS diode38and the LS diode40by a different electronic element that may fulfil the same function, for example, an appropriate triggered transistor. The input voltage Vinmay be provided by a battery. The DC to DC converter10shown inFIG. 1may be called non-inverting because it maintains the sign of the input voltage Vin.

Referring now toFIG. 2, an example of a cranking pulse is schematically shown as a function of time. The term “cranking pulse” describes a high voltage drop that may occur with a discharged battery when the driver attempts to start up the car. Initially, at a time t1the battery voltage Vbattmay have its normal value Vnorm. At a time t2, the driver may attempt to start the car. As a result, the battery voltage Vbattmay drop to a low value Vminwithin the short time interval t3-t2before it returns to Vnormat a time t4. However, it is very important to keep any supply voltage provided to automotive electronics connected to the battery at a certain stable voltage level to avoid damage to the electronics and unpredictable data processing. The desired supply voltage for the automotive electronics may lie between Vnormand Vmin. Thus, it may be necessary to convert the supply voltage provided by the battery with a buck-boost DC to DC converter, wherein a transition between a buck mode and a boost mode is necessary when the supply voltage provided by the battery equals the desired supply voltage for the automotive electronics. This transition must be smooth without any voltage or current peaks at the output of the DC to DC converter.

Referring toFIG. 3, a further circuit diagram of a second example of a DC to DC converter10is schematically shown. The DC to DC converter10according toFIG. 2is a buck-boost converter and comprises a buck converter12, a boost converter14, and a control unit16. The basic set-ups of the buck converter12and the boost converter14as shown inFIG. 3correspond to the buck converter12and the boost converter14already known fromFIG. 1. However, the circuits are closed by connecting the LS switching element36, the HS diode38, and the capacitor44to a ground60.

The control unit16may be arranged to trigger the HS switching element30and the LS switching element36. As inFIG. 1, the HS switching element30and the LS switching element36may be MOSFETs. However, the use of different electronic elements as HS switching element30and LS switching element36are apparent to a person skilled in the art.

The control unit16may comprise a first error amplifier48, a second error amplifier50, a first comparator52, a second comparator54, a third comparator56, a HS control circuit26, a HS driver circuit28, a LS control circuit32, and a LS driver circuit34. Additionally, the control unit16may optionally comprise a filter58. The first error amplifier48, the first comparator52, the HS control circuit26, and the HS driver circuit32may be used to trigger the HS switching element30. The second error amplifier50, the second comparator54, the third comparator56, the LS control circuit32, and the LS driver circuit34may be used to trigger the LS switching element36. The functionality of the control unit16will be explained in the following.

A feedback output voltage Vout_FBmay be provided to the first error amplifier48and the second error amplifier50of the control unit16. The feedback output voltage Vout_FBmay be, for example, the output voltage Voutof the DC to DC converter10scaled by a first resistor62and a second resistor64. The first error amplifier48and the second error amplifier50may be, for example, operational amplifiers with a differential input and a single-ended output. The feedback output voltage Vout_FBand a reference voltage of the buck converter Vref_buckmay be used as input signals for the first error amplifier48. The first error amplifier48provides an error voltage of the buck converter Verr_buckat its output. The output signal of the first error amplifier48may be used as a negative feedback signal for the feedback output voltage Vout_FBat the appropriate input of the first error amplifier48.

Similarly, the feedback output voltage Vout_FBand a reference voltage of the boost converter Vref_boostmay be used as differential input signals for the second error amplifier50. The second error amplifier50provides an error voltage of the boost converter Verr_boostbased on the differential input signals. The output signal of the second error amplifier50may be used as a negative feedback signal for the feedback output voltage Vout_FBat the appropriate input of the second error amplifier50. Thus, the control unit16is arranged to calculate an error voltage of the buck converter Verr_buckbased on a feedback output voltage Vout_FBof the DC to DC converter10and a reference voltage of the buck converter Vref_buck. Further, the control unit16is arranged to calculate an error voltage of the boost converter Verr_boostbased on the feedback output voltage Vout_FBof the DC to DC converter10and the reference voltage of the boost converter Vref_boost. The reference voltage of the boost converter Vref_boostmay be shifted by an offset Voffsetas compared to the reference signal of the buck converter Vref_buck. The reference voltage of the buck converter Vref_buckmay define the desired output voltage Voutof the DC to DC converter10when operating in buck mode. Analogously, the reference voltage of the boost converter Vref_boostmay define the desired output voltage Voutof the DC to DC converter10when operating in boost mode. Due to the offset Voffset, the output voltage Voutof the DC to DC converter10may change from Vref_buckto Vref_boostwhen changing from buck mode to boost mode and vice versa. The reference voltage of the buck converter Vref_buckmay usually be larger than the reference voltage of the boost converter Vref_boost. In this case, the difference between the reference voltage of the buck converter Vref_buckand the reference voltage of the boost converter Vref_boostmay generate a hysteresis around the transition between buck mode and boost mode. The hysteresis may avoid quick oscillations of the DC to DC converter10between buck mode and boost mode.

When the input voltage Vinof the DC to DC converter10lies between the reference voltage of the buck converter Vref_buckand the reference voltage of the boost converter Vref_boost, the HS switching element30of the buck converter12is always on (i.e., conducting or closed), and the LS switching element36is always off (i.e., isolating or open). Therefore, the efficiency of the DC to DC converter10is increased because the HS switching element30and the LS switching element36are not triggered in this region and do not cause switching losses. Additionally, the output voltage Voutof the DC to DC converter10may equal its input voltage Vinand input current without additional ripples or peaks.

The error voltage of the buck converter Verr_buckmay be provided to the first comparator52together with a time-dependent sensing voltage Vsens. The time-dependent sensing voltage Vsensmay be generated based on a pulsating voltage Vpulseand a further voltage, for example, by adding the pulsating voltage Vpulseto the further voltage. The further voltage may be, for example, a voltage that represents the input current of the DC to DC converter10. The DC to DC converter10may, for example, operate in a current mode. A current pattern, i.e., a current ramp, may be sensed at the HS switching element30. The sensed current pattern may be transformed to a voltage pattern by a resistor, and the resulting voltage pattern that may correspond to the current pattern may be the pulsating voltage Vpulse. The pulsating voltage Vpulsemay be, for example, a sawtooth voltage or a triangle voltage. The pulsating voltage Vpulsemay be called a “slope compensation” that allows for the stability of the DC to DC converter10at all possible duty cycles between 0 and 100%. The first comparator52may provide a first PWM signal20at its output. Thus, the control unit16may be arranged to calculate the first PWM signal20by comparing the time-dependent sensing voltage Vsenswith the error voltage of the buck converter Verr_buck. The first PWM signal20may substantially define a duty-cycle of the buck converter12. The shape of the first PWM signal20may be, for example, rectangular. The HS control circuit26may be used to generate an input signal for the HS driver circuit28that may trigger the HS switching element30of the buck converter12. The first PWM signal20and a clock signal24may be used as input signals for the HS control circuit26. The HS control circuit26may be, for example, a flip-flop which has the first PWM signal20and the clock signal24as input signals.

A second PWM signal22may be provided by the second comparator54which has the error voltage of the boost converter Verr_boostand the time-dependent sensing voltage Vsensas input signals. Thus, the control unit16may be arranged to calculate the second PWM signal22by comparing the time-dependent sensing voltage Vsenswith the error voltage of the boost converter Verr_boost. Just like the first PWM signal20, the second PWM signal22may be, for example, rectangular. The second PWM signal22and the clock signal24may be used as input signals for the LS control circuit32that provides an output signal to a LS driver circuit34. The LS driver circuit34may trigger the LS switching element36of the boost converter14. An additional control signal18may optionally be provided to the LS control circuit32. The LS control circuit32may be, for example, a flip-flop. The control unit16may be described as a current mode PWM controller when the further voltage represents the input current of the DC to DC controller10.

The control signal18may be used as an additional input signal that overwrites an output signal of the LS control circuit32which is generated on the basis of the second PWM signal22and the clock signal24. Thus, the control signal18may activate or deactivate (i.e., engage or disengage) the boost converter14. The second PWM signal22may substantially represent a duty-cycle of the boost converter14. In particular, the second PWM signal22may define when the LS switching element36is in its open state (or conducting) or in its closed state (off of isolating). The control signal18may be generated directly or indirectly by the second comparator54that uses the error voltage of the buck converter Verr_buckand a threshold voltage Vout_of_rangeas input signals. The filter58may be optionally used for smoothing the generated control signal18.

As mentioned before, the control signal18may be used to engage or disengage the boost converter14. When the error voltage of the buck converter Verr_buckis higher than the threshold voltage Vout_of_range, the boost converter14may be engaged. When the error voltage of the buck converter Verr_buckis lower than the threshold voltage Vout_of_range, the boost converter14may be disengaged. Thus, the control unit16may be arranged to calculate the control signal18to engage and disengage the boost converter14based on the error voltage of the buck converter Verr_buck. The buck converter12is the main operating circuit, and the boost converter14can operate as an optional auxiliary circuit when the input voltage Vinof the DC to DC converter10is too low.

The reference voltage of the buck converter Vref_buckmay define the desired output voltage Voutof the buck converter12in buck mode. Thus, the error voltage of the buck converter Verr_buckmay decrease when the feedback output voltage Vout_FBof the DC to DC converter10increases. For example, the error voltage of the buck converter Verr_buckmay tend to 0 when the feedback output voltage Vout_FBof the DC to DC converter10is higher than the reference voltage of the buck converter Vref_buck, and the error voltage of the buck converter Verr_buckmay reach an upper peak value of the time-dependent sensing voltage Vsenswhen the feedback output voltage Vout_FBof the DC to DC converter10equals the reference voltage of the buck converter Vref_buck. In the same way, the error voltage of the boost converter Verr_boostmay define the desired output voltage Voutof the boost converter14in boost mode, and the error voltage of the boost converter Vref_boostmay tend to 0 or fall below a lower peak value of the time-dependent sensing voltage Vsenswhen the reference voltage of the boost converter Vref_boostequals the feedback output voltage Vout_FBof the DC to DC converter10.

The duty-cycle of the buck converter12increases when the error voltage of the buck converter Verr_buckincreases. The threshold voltage Vout_of_rangemay be chosen such that the duty-cycle of the buck converter12reaches 100 percent before the error voltage of the buck converter Verr_buckbecomes larger than the threshold voltage Vout_of_range. Additionally, the error voltage of the boost converter Verr_boostmay be chosen such that the duty-cycle of the boost converter14is larger than 0 percent when the boost converter14is engaged by the control signal18. This means that the LS switching element36of the boost converter14may be periodically triggered when the boost converter14is engaged and that a small variation of the input voltage Vindoes not significantly change the duty-cycle when the boost converter is engaged. This may avoid the generation of peaks in the output voltage Voutand the output current during the transition from buck mode to boost mode and vice versa. Thus, the electromagnetic compatibility of the DC to DC converter10is good.

It may be possible to use the control signal18as an additional input signal for the HS control circuit26. In this case, the control signal18may be used as a master signal that overwrites the normal output signal of the HS control circuit26generated on the basis of the first PWM signal20and the clock signal24. Thus, the control signal18may be used to permanently set the HS switching element30on. This may secure that the buck converter12is deactivated when the boost converter is activated. Using the control signal18as an additional input signal for the HS control circuit26may be useful when the threshold voltage Vout_of_rangeis chosen such that the duty-cycle of the buck converter12does not reach 100 percent before the error voltage of the buck converter Verr_buckbecomes larger than the threshold voltage Vout_of_range.

The DC to DC converter shown inFIG. 3may he designed as a system on a die, wherein at least parts of the DC to DC converter, for example, the buck converter12, the boost converter14, or the control unit16, are implemented on a single die1100as shown inFIG. 11. The single die may comprise, for example, a silicon substrate.

Referring now toFIG. 4, a diagram of an example of duty-cycles of a DC to DC converter and a corresponding output voltage Voutof this DC to DC converter is shown as a function of the input voltage Vin. The diagram is divided in three different regions as will be explained in the following. It can be seen fromFIG. 4that the desired output voltage Voutof the buck converter may be about 6.5 volt. In region I, the duty-cycle of the buck converter Dbuckincreases when the input voltage Vinof the DC to DC converter decreases. For example, the duty-cycle of the buck converter Dbuckmay reach 100 percent at an input voltage Vinof approximately 6.5 volt (i.e., the desired output voltage of the buck converter in this example). The duty-cycle of the boost converter Dboostis 0 in region I. Therefore, the DC to DC converter is in buck mode. A duty-cycle of the buck converter Dbuckof 100 percent means that its HS switching element known fromFIGS. 1 and 3is permanently on. When the input voltage Vinof the DC to DC converter further decreases, the error voltage of the buck converter Verr_buckincreases further, but the duty-cycle of the buck converter Dbuckhas already reached its maximum value. This leads to a decreasing output voltage Voutof the DC to DC converter10in region II. The duty-cycle of the boost converter Dboostmay reach a value larger than 0 in region II. However, the boost converter may not yet be engaged because the error voltage of the buck converter Verr_buckhas not yet reached the value of the threshold voltage Vout_of_rangeand the DC to DC converter stays in buck mode. The error voltage of the buck converter Verr_buckmay reach the threshold voltage Vout_of_rangeat the beginning of region III, and the buck converter may engage the boost converter by generating the control signal. The DC to DC converter switches to boost mode.

Due to the appropriate offset Voffsetbetween the reference voltage of the buck converter Vref_buckand the reference voltage of the boost converter Vref_boostin connection with the generation of the control signal, the duty-cycle of the boost converter Dboostdoes not start with 0 percent when the boost converter is engaged with entrance of region III. However, due to the offset Voffset, the output voltage, Voutof the DC to DC converter changes from the reference value of the buck converter Vref_buckto the reference value of the boost converter Vref_boost. The buck converter is regulating the output voltage Voutof the DC to DC converter and provides good performance versus load in region I and region II. The boost converter is regulating the output voltage Voutof the DC to DC converter in region III.

Referring now toFIG. 5, a diagram of examples of an error voltage of a buck converter Verr_buckand a corresponding control signal18is shown as a function of time.FIGS. 5, 6 and 7share a common time axis. As can be seen, at a time t between 1.1 ms and 1.15 ms, the error voltage of the buck converter Verr_buckmay reach the threshold voltage of the buck converter Vout_of_range, and a value of the control signal18may switch from 0 to 1 volt. In the example ofFIG. 5, the control signal18is shown as a voltage signal.

Referring now toFIG. 6, an example of an output signal of the LS control circuit is shown as a function of time. The buck converter may engage the boost converter when the control signal18shown inFIG. 5switches from 0 to 1. The output signal of the LS control circuit may periodically change its value according to the second PWM signal for the boost converter. The output signal of the LS control circuit may be used directly or indirectly via a LS driver circuit as a signal for triggering the LS switching element of the boost converter. Thus, the function shown inFIG. 6may substantially represent a PWM signal for the boost converter.

Referring now toFIG. 7, an example of an input voltage Vinand an output voltage Voutof a DC to DC converter is shown as a function of time. The input voltage Vindrops from an initial value larger than 7 volt at a time t=1.00 ms to a final value smaller than 6 volt at a time t=1.20 ms. At a time t=1.10 ms, the input voltage Vinintersects the output voltage Vout. At this time, the HS switching element of the buck converter may be permanently on, and the buck converter is no longer capable of regulating the output voltage Voutof the DC to DC converter in the case of a further voltage drop. In consequence, the output voltage Voutof the DC to DC converter may decrease as the input voltage Vinof the DC to DC converter decreases. At the same time, as can be seen inFIG. 5, the error voltage of the buck converter Verr_buckmay increase until the control signal18switches from 0 to 1, and the boost converter may be engaged by the buck converter. The output voltage Voutof the DC to DC converter becomes stabilised at approximately 6.25 volt by the boost converter. The output voltage Voutof the DC to DC converter may pulsate a little in boost mode. However, there are neither voltage nor current peaks, and the deviation of the output voltage Voutfrom the reference voltage of the buck converter Vref_buckor from the reference voltage of the boost converter Vref_boostmay be less than 5 percent. Thus, the electronic elements of the DC to DC converter and/or of the connected load may be dimensioned small because they are not exposed to unwanted peaks. In particular, transistors used as switching elements in the DC to DC converter may have a lower breakdown voltage.

Referring now toFIGS. 8, 9, and 10which share a common time axis,FIGS. 8 to 10show the transition between the development of the input voltage Vinand the corresponding output voltage Voutof the DC to DC converter at the transition from buck mode to boost mode in more detail. As can be seen fromFIG. 9, the duty-cycle of the boost converter increases with the decrease of the input voltage Vin, and the duty-cycle of the boost converter does not start with 0 percent.

The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention.

The computer program may be stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. All or some of the computer program may be provided on transitory or non-transitory computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.

For example, the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level 0. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. For example, the first comparator, HS control circuit, and the HS driver circuit may be replaced by a single HS amplifier circuit triggering the HS switching element directly.

Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. For example, the buck converter, the boost converter, and the control unit may be implemented as a single circuitry. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. For example, the buck converter and the boost converter may be implemented on a single integrated circuitry and the control unit may be implemented on a different integrated circuitry.