Power Semiconductor Package

Power semiconductor packages are provided. In one example, a power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount type (SMT) connection structures on the second side.

FIELD

The present disclosure relates generally to semiconductor packages.

BACKGROUND

Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide band gap semiconductor material systems such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) are being increasingly utilized in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Example power semiconductor devices may include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, thyristors, and high electron mobility transistors (HEMTs). Packaging technology may play a large role in the performance of power semiconductor devices.

SUMMARY

One example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount type (SMT) connection structures on the second side.

Another example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more SMT connection structures on the second side. Each of the one or more SMT connection structures may have a connection surface area that is greater than a connection surface area of the one or more electrical leads.

Another example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The housing having a first surface extending between the first side and the second side and a second surface opposing the first surface. The power semiconductor package may include a thermal pad. The power semiconductor package may include a step structure on the first surface of the housing. The step structure may be defined in the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness. The second thickness may be greater than the first thickness.

Another example aspect of the present disclosure is directed to a method. The method may include providing a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposing the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side, and one or more first leadless surface mount type (SMT) connection structures on the second side. The method may include providing a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposing the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side, and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

Another example aspect of the present disclosure is directed to a power semiconductor package assembly. The power semiconductor package assembly may include a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposing the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side, and one or more first leadless surface mount type (SMT) connection structures on the second side. The power semiconductor package assembly may include a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposing the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side, and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

These and other features, aspects and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, explain the related principles.

DETAILED DESCRIPTION

Discrete semiconductor packages have been developed that include a semiconductor die, such as a MOSFET or a Schottky diode. Such semiconductor packages with MOSFETs may be employed in a variety of applications to enable higher switching frequencies along with reduced associated losses, higher blocking voltages, and improved avalanche capabilities. Example applications may include high performance industrial power supplies, server/telecom power, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high-voltage DC/DC converters, electric vehicles, and battery management systems. Discrete semiconductor packages with Schottky diodes may be employed in many of the same high-performance power applications described above for MOSFETs, sometimes in systems that also include discrete power packages of MOSFETs.

Packaging technology for semiconductor devices plays an important role in defining the performance of the semiconductor devices. For example, the packaging of a power semiconductor die may limit the ability of the semiconductor die to dissipate heat, conduct current, or even switch at particular speeds (e.g., due to stray inductance). Ineffective heat dissipation can create problems for semiconductor devices (e.g., small form factor semiconductor devices) or in situations where the semiconductor device comes into close contact with the housing. Excessive heat can adversely impact the operation of the semiconductor device itself, as well as the electronic system that uses that semiconductor device.

Example aspects of the present disclosure are directed to semiconductor packages that incorporate surface mount technology (SMT) structures. The semiconductor packages may provide enhanced flexibility with different pin out options for electrical leads. In some embodiments, the semiconductor packages may include a thermal pad for topside cooling which may allow for direct attachment to a heat sink (e.g., with an electrical isolator) to enhance thermal performance. The semiconductor package may provide for increased current and voltage handling capabilities relative to other semiconductor packages with small form factors.

In some embodiments, the power semiconductor package may include a semiconductor die. The semiconductor die may be based on a wide band gap semiconductor material. A wide band gap semiconductor has a band gap greater than about 1.40 eV, such as silicon carbide and/or a Group III-nitride (e.g., gallium nitride). In some examples, the semiconductor die may include semiconductor devices, such as transistors, diodes, and/or thyristors. For instance, in some examples, the power semiconductor die may include silicon carbide-based MOSFETs located between a source contact and a drain contact to form, for instance, a vertical structure power semiconductor device.

Aspects of the present disclosure are discussed with reference to silicon carbide-based MOSFET devices for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the power semiconductor die may include other power semiconductor devices without deviating from the scope of the present disclosure, such as diodes (e.g., Schottky diodes, PiN diodes, etc.), insulated gate bipolar transistors, high electron mobility transistors, or other devices.

In some examples, the power semiconductor package may include a housing having a first side and a second side that is opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more surface mount type (SMT) connection structures on the second side. The SMT connection structures may have a size that is larger than the one or more electrical leads. For instance, the SMT connection structures may have a larger connection surface relative to each of the one or more electrical leads. More particularly, the SMT connection structures may each have a connection surface area that is greater than a connection surface area of each of the one or more electrical leads, such as at least two times greater, such as at least 2.5 times greater, such as at least three times greater.

In some examples, because of the smaller size of the electrical leads relative to the SMT connection structures, the first side may have a greater number of electrical leads relative to the number of SMT connection structures on the second side. For instance, in some examples, the power semiconductor package may have two SMT connection structures on the second side and two to fourteen electrical leads on the first side. In this way, the power semiconductor package may accommodate a high-power rating (e.g., high voltage rating) through the use of the SMT connection structures with high connection surface area, while still accommodating flexibility in providing other connections (e.g., gate, source, kelvin, sensor) through the smaller electrical leads.

In some examples, the one or more SMT connection structures may be leadless SMT connection structures. For example, the SMT connection structures may be wettable flank connection structures. In these examples, the SMT connection structures may be partially encapsulated in the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing. The wettable flank connection structure may also be exposed through at least one side surface of the housing. This may facilitate connection of the power semiconductor package to other structures (e.g., a circuit board) and may facilitate efficient design of a lead frame (e.g., conductive lead frame) for the power semiconductor package.

In some examples, the one or more SMT connection structures may be SMT connection tabs. The one or more SMT connection tabs may extend from the second side of the housing. The one or more SMT connection tabs may extend from the second side of the housing at a location below a top surface of the housing (e.g., a surface opposite the mounting surface).

In some examples, the power semiconductor package may include a thermal pad. The thermal pad may provide for cooling of the semiconductor package (e.g., topside cooling). In some examples, the power semiconductor package may include a creepage extension structure between the thermal pad and the first side of the power semiconductor package. The creepage extension structure may increase the current and voltage handling capability of the power semiconductor package. More particularly, the creepage extension structure may increase voltage isolation between the one or more electrical leads on the first side of the housing and the SMT connection structures on the second side of the housing. The creepage extension structure may effectively increase a surface distance (e.g., creepage distance) along the housing of the power semiconductor package between the one or more electrical leads on the first side of the housing and the SMT connection structures on the second side of the housing.

In some examples, the creepage extension structure may include a step structure between the one or more electrical leads and the thermal pad. Alternatively or in addition, the creepage extension structure may include a step structure between the thermal pad and the one or more SMT connection structures. The step structure may have a depth of about 0.5 mm to about 2.0 mm.

In some examples, the creepage extension structure may include one or more trenches defined in the housing. The one or more trenches may be defined between the step structure and the one or more electrical leads extending from the first side of the housing. The one or more trenches may extend at least partially along a peripheral edge of the housing at the first side of the housing. The one or more trenches may have a depth of about 0.5 mm to about 2.0 mm and a length of about 5 mm to about 10 mm. The creepage extension structure may provide a creepage distance between the one or more electrical leads and the SMT connection structures of about 5 mm to about 20 mm.

In some embodiments, the power semiconductor package may provide electrical isolation between the thermal pad and the one or more SMT connection structures. For instance, the thermal pad may be on a first side of an insulating layer of a mounting substrate for the semiconductor die. The SMT connection structures and/or conductive lead frame coupled to the SMT connection structures may be coupled to one or more conductive pads on a second side of the insulating layer of the mounting substrate such that the insulating layer is disposed between the SMT connection structures and the thermal pad. In some examples, the mounting substrate may be, for instance, a directed bonded copper (DBC) substrate or an active metal brazed (AMB) substrate.

Aspects of the present disclosure provide a number of technical effects and benefits. For instance, the power semiconductor package may provide efficient thermal dissipation through a thermal pad. The power semiconductor package may provide for multiple pin options for the electrical leads extending from the power semiconductor package, making the power semiconductor package suitable for use with multiple device families. The power semiconductor package may have a high voltage and/or a high current rating due to the use of large SMT connection structures (e.g., for connection to the source and/or drain) and due to, for instance, the creepage extension structure. The power semiconductor package may provide a small form factor. The power semiconductor package may provide for electrical isolation between the thermal pad and the SMT connection structures (e.g., drain connection).

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it may be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present, except in some examples an attach material (e.g., die-attach material, solder, paste, adhesive, sintered material or other material may be present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present, except in some examples an attach material (e.g., die-attach material, solder, paste, adhesive, sintered material or other material may be present.

Embodiments of the disclosure are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the disclosure. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Similarly, it will be understood that variations in the dimensions are to be expected based on standard deviations in manufacturing procedures. As used herein, “approximately” or “about” includes values within 10% of the nominal value.

Like numbers refer to like elements throughout. Thus, the same or similar numbers may be described with reference to other drawings even if they are neither mentioned nor described in the corresponding drawing. Also, elements that are not denoted by reference numbers may be described with reference to other drawings.

Some embodiments of the invention are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n type or p type, which refers to the majority carrier concentration in the layer and/or region. Thus, N type material has a majority equilibrium concentration of negatively charged electrons, while P type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a “+” or “−” (as in N+, N−, P+, P−, N++, N−−, P++, P−−, or the like), to indicate a relatively larger (“+”) or smaller (“−”) concentration of majority carriers compared to another layer or region. However, such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.

Aspects of the present disclosure are discussed with reference to silicon carbide-based semiconductor structures, such as silicon carbide-based MOSFETs. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the power semiconductor packages according to example embodiments of the present disclosure may be used with any semiconductor material, such as other wide band gap semiconductor materials, without deviating from the scope of the present disclosure. Example wide band gap semiconductor materials include silicon carbide (e.g., 2.996 eV band gap for alpha silicon carbide at room temperature) and the Group III-nitrides (e.g., 3.36 cV band gap for gallium nitride at room temperature).

In the drawings and specification, there have been disclosed typical embodiments and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation of the scope set forth in the following claims.

FIG.1depicts a top perspective view of an example semiconductor package100according to example embodiments of the present disclosure.FIG.2depicts a bottom perspective view of the example semiconductor package100. With reference toFIGS.1and2, the semiconductor package100includes a housing102. The semiconductor package100may be arranged to house and provide external electrical connections to a semiconductor die that is located within the housing102, such as a semiconductor die having a MOSFET or a Schottky diode.

The housing102may include a first side102′ and an opposing second side102″. The housing102may include a first surface102A (e.g., a top surface) extending between the first side102′ and the second side102″. The housing102may include a second surface102B (e.g., a bottom surface or mounting surface) extending between the first side102′ and the second side102″. The housing102may also include side surfaces102C,102D,102E, and102F. The side surface102C may be located at the first side102′. The side surface102D may be located at the second side102″. The housing102may include different arrangements of surfaces without deviating from the scope of the present disclosure. For instance, one or more notches or recesses may be formed in any of the surface102A-102F without deviating from the scope of the present disclosure.

The power semiconductor package100may be arranged as a surface mount technology (SMT) package with the first surface102A (e.g., top surface) positioned opposite an external surface, such as a printed circuit board (PCB) on which the power semiconductor package100is mounted. The second surface102B (e.g., bottom surface or mounting surface) forms a mounting side of the power semiconductor package100that is mounted to the external surface, such as a PCB.

The housing102may be formed by a molding process. The housing102may include a material capable of high temperature operation, such as a temperature of about 200° C. Example materials for the housing102may include an epoxy material or an epoxy mold compound (EMC).

The power semiconductor package100includes one or more electrical leads110extending from the first side102′ of the housing102. The electrical leads110may be SMT connection structures having a connection surface112. The connection surface112of the electrical leads110may be used to connect internal components of the power semiconductor package100to external electrical connections. The electrical leads110have the form of electrical connection pins.

The power semiconductor package100includes leadless SMT connection structures120on the second side102″ of the housing102. The leadless SMT connection structures120have a connection surface122. A surface area of the connection surface122of the leadless SMT connection structures120may be greater than a surface area of the connection surface112of the electrical leads110(e.g., electrical connection pins), such as about two times greater, such as about 2.5 times greater, such as about three times greater.

In the example power semiconductor package100ofFIGS.1and2, the leadless SMT connection structures120are wettable flank connection structures. More particularly, the leadless SMT connection structures120are partially encapsulated by the housing102such that the connection surface122of the leadless SMT connection structures120are exposed through the second surface102B (e.g., the mounting surface) of the power semiconductor package100. In some examples, the connection surface122of each leadless SMT connection structure120is coplanar with the second surface102B (e.g., the mounting surface). In some examples, a portion124of each leadless SMT connection structure120is exposed through the side surfaces102D,102E or side surfaces102D,102F of the housing102.

As illustrated, a number of electrical leads110extending from the first side102′ of the housing102may be greater than a number of leadless SMT connection structures120on the second side102″ of the housing102. For instance, the power semiconductor package100includes seven electrical leads110and two leadless SMT connection structures120. More or fewer electrical leads110may be included in the power semiconductor package100without deviating from the scope of the present disclosure. More or fewer leadless SMT connection structures120may be included in the power semiconductor package100without deviating from the scope of the present disclosure.

Referring still toFIGS.1and2, the first surface102A (e.g., the top surface) of the housing102may include a thermal pad130. The thermal pad130may include a thermally conductive material, such as a metal. The thermal pad130may be coupled to an external heat sink (e.g., with an electrical isolator) to provide topside cooling for the power semiconductor package100.

The first surface102A of the housing102may also include creepage extension structures140.1and140.2. The creepage extension structures140.1and140.2may increase a creepage distance between the electrical leads110and the leadless SMT connection structures120. In the example ofFIGS.1and2, the creepage extension structure140.1includes a first step structure142.1between the thermal pad130and the electrical leads110extending from the first side102′ of the housing102. The first step structure142.1may be defined such that the housing102has a first thickness T1at the first side102′ of the housing102and a second thickness T2at the thermal pad130. The second thickness T2is greater than the first thickness T1. For instance, the step structure may have a depth in a range of about 0.5 mm to about 2.0 mm such that T2exceeds T1by about 0.5 mm to about 2.0 mm.

The creepage extension structure140.2includes a second step structure142.2between the thermal pad130and the leadless SMT connection structures120on the second side102″ of the housing102. The second step structure142.2may be defined such that the housing102has a third thickness T3at the second side102″ of the housing102and a second thickness T2at the thermal pad130. The second thickness T2is greater than the third thickness T3. For instance, the second step structure may have a depth in a range of about 0.1 mm to about 2.5 mm such that T2exceeds T3by about 0.1 mm to about 2.5 mm. The third thickness T3may be the same as or different from the first thickness T1. The second step structure142.2may have a depth that is the same as or different from the depth of the first step structure142.1.

The housing102of the power semiconductor package100may have other creepage extension features without deviating from the scope of the present disclosure. For instance, the first creepage extension structure140.1may include a trench144defined along a peripheral edge of the housing102at the first side102′ of the housing102between the electrical leads110and the thermal pad130. The trench144may have a depth in a range of, for instance, 0.5 mm to about 2.0 mm. The total creepage distance between the electrical leads110and the leadless SMT connection structures120may be, for instance, in a range of about 5 mm to about 20 mm.

FIG.3depicts a bottom perspective view of the power semiconductor package100with the housing102transparent according to example embodiments of the present disclosure. As illustrated, a semiconductor die160may be mounted on a mounting substrate150(e.g., conductive lead frame) for the power semiconductor package. The mounting substrate150may be coupled to or integral with the thermal pad130. The semiconductor die160may be attached to the mounting substrate150, for instance, using a die-attach material.

The semiconductor die160may include one or more semiconductor devices, such as MOSFET devices, Schottky diodes, or other devices. In some examples, the semiconductor die160may be based on a wide band gap semiconductor, such as silicon carbide and/or a Group III-nitride (e.g., gallium nitride). For instance, in some examples, the power semiconductor die160may include silicon carbide-based MOSFETs located between a source contact and a drain contact to form, for instance, a vertical structure power semiconductor device. Aspects of the present disclosure are discussed with reference to silicon carbide-based MOSFET devices for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the power semiconductor die may include other power semiconductor devices without deviating from the scope of the present disclosure, such as diodes (e.g., Schottky diodes, PiN diodes, etc.), insulated gate bipolar transistors, high electron mobility transistors, or other devices.

The semiconductor die160may be, for instance, a 7 mm by 7 mm semiconductor die. However, aspects of the present disclosure are applicable to many different semiconductor die sizes, such as 1 mm by 1 mm semiconductor die to 7 mm by 9 mm semiconductor die, as some examples.

In the example of a semiconductor die160including a silicon carbide-based MOSFET device, the electrical leads110may include a first lead110.1, a second lead110.2, and a third lead110.3. The first lead110.1may include a plurality of integral electrical connection pins. The first lead110.1may be coupled to a source of the MOSFET device on the semiconductor die160using, for instance, wire bonds172. The first lead110.1may be used to connect the source of the MOSFET device on the semiconductor die160to one or more external connections (e.g., on a PCB).

The second lead110.2may include an electrical connection pin (e.g., a single electrical connection pin). The second lead110.2may be coupled to a gate of the MOSFET device on the semiconductor die160using, for instance, wire bond174. The second lead110.2may be used to connect the gate of the MOSFET device on the semiconductor die160to one or more external connections (e.g., on a PCB).

The third lead110.3may include an electrical connection pin (e.g., a single electrical connection pin). The third lead110.3may be coupled to another contact associated with the MOSFET device on the semiconductor die160, such as a source-kelvin contact and/or a sensor contact. The third lead110.3may be coupled to a gate of the MOSFET device on the semiconductor die160using, for instance, wire bond176. The third lead110.3may be used to connect the contact associated with the MOSFET device on the semiconductor die160to one or more external connections (e.g., on a PCB).

The SMT connection structures120may be connected to a drain of the MOSFET device on the semiconductor die160. More particularly, the drain of the MOSFET device may be electrically coupled (e.g., through a die-attach material) to the mounting substrate150. The SMT connection structures120may be electrically coupled to the mounting substrate150. For instance, the SMT connection structures120may be electrically coupled to the mounting substrate150through connection elbows126. The connection elbows126and/or the SMT connection structures120may be integral with the mounting substrate150in some embodiments.

As discussed above, the power semiconductor package100may include a semiconductor die160with other types of semiconductor devices without deviating from the scope of the present disclosure. For instance, in some examples, the semiconductor die160may include a Schottky diode. In this example, one or more of the electrical leads110may be coupled to a first contact of the Schottky diode on the semiconductor die160using, for instance, wire bonds. The SMT connection structures120may be connected to a second contact of the Schottky diode, for instance, through the mounting substrate150(e.g., through the connection elbows126and mounting substrate150).

FIG.4depicts a top perspective view of an example semiconductor package200according to example embodiments of the present disclosure.FIG.5depicts a bottom perspective view of the example semiconductor package200. With reference toFIGS.4and5, the semiconductor package200includes a housing202. The semiconductor package200may be arranged to house and provide external electrical connections to a semiconductor die that is located within the housing202, such as a semiconductor die having a MOSFET or a Schottky diode.

The housing202may include a first side202′ and an opposing second side202″. The housing202may include a first surface202A (e.g., a top surface) extending between the first side202′ and the second side202″. The housing202may include a second surface202B (e.g., a bottom surface or mounting surface) extending between the first side202′ and the second side202″. The housing202may also include side surfaces202C.202D,202E, and202F. The side surface202C may be located at the first side202′. The side surface202D may be located at the second side202″. The housing202may include different arrangements of surfaces without deviating from the scope of the present disclosure. For instance, one or more notches or recesses may be formed in any of the surface202A-202F without deviating from the scope of the present disclosure.

The power semiconductor package200may be arranged as a surface mount technology (SMT) package with the first surface202A (e.g., top surface) positioned opposite an external surface, such as a printed circuit board (PCB) on which the power semiconductor package200is mounted. The second surface202B (e.g., bottom surface or mounting surface) forms a mounting side of the power semiconductor package200that is mounted to the external surface, such as a PCB.

The housing202may be formed by a molding process. The housing202may include a material capable of high temperature operation, such as a temperature of about 200° C. Example materials for the housing202may include an epoxy material or an epoxy mold compound (EMC).

The power semiconductor package200includes one or more electrical leads210extending from the first side202′ of the housing202. The electrical leads210may be SMT connection structures having a connection surface212. The connection surface212of the electrical leads210may be used to connect internal components of the power semiconductor package200to external electrical connections. The electrical leads210have the form of electrical connection pins.

The power semiconductor package200includes SMT connection structures220on the second side102″ of the housing102. The SMT connection structures220have a connection surface222. A surface area of the connection surface222of the SMT connection structures220may be greater than a surface area of the connection surface212of the electrical leads210(e.g., electrical connection pins), such as about two times greater, such as about 2.5 times greater, such as about three times greater.

In the example power semiconductor package200ofFIGS.3and4, the SMT connection structures220are SMT connection tabs220. The SMT connection tabs220extend from the second side202″ of the housing202(e.g., extend from the side surface202). The SMT connection tabs220each include the connection surface222and a connection elbow226. The connection elbow226may be integral with the connection surface222. The housing202does not encapsulate at least a portion of the connection elbow226such that the connection elbow226is exposed.

In some examples, the SMT connection tabs220extend from the second side202″ of the housing202at a location below the top surface202A of the housing202. For instance,FIG.6depicts a side view of the example power semiconductor package200according to example embodiments of the present disclosure. As shown, the SMT connection tabs220extend from the side surface202D at the second side202″ of the housing202at a location below the top surface202A of the housing202, such as at a depth D1below the top surface202A of the housing202. The depth D1may be in a range of, for instance, 0.5 mm to about 2.0 mm. In some examples, the connection surface222of each of the SMT connection tabs220may be coplanar with the bottom surface202B of the housing202of the power semiconductor package200.

Referring back toFIGS.4and5, a number of electrical leads210extending from the first side202′ of the housing202may be greater than a number of SMT connection structures220extending from the second side202″ of the housing202. For instance, the power semiconductor package200includes seven electrical leads210and two SMT connection structures220. More or fewer electrical leads210may be included in the power semiconductor package200without deviating from the scope of the present disclosure. More or fewer SMT connection structures220may be included in the power semiconductor package200without deviating from the scope of the present disclosure.

Referring still toFIGS.4and5, the first surface202A (e.g., the top surface) of the housing202may include a thermal pad230. The thermal pad230may include a thermally conductive material, such as a metal. The thermal pad230may be coupled to an external heat sink (e.g., with an electrical isolator) to provide topside cooling for the power semiconductor package300.

The first surface202A of the housing202may also include a creepage extension structure240. The creepage extension structure240may increase a creepage distance between the electrical leads210and the SMT connection structures220. In the example ofFIGS.4and5, the creepage extension structure240includes a step structure242between the thermal pad230and the electrical leads210extending from the first side202′ of the housing202. The step structure242may be defined such that the housing202has a first thickness T1at the first side202′ of the housing202and a second thickness T2at the second side202″ of the housing202. The second thickness T2is greater than the first thickness T1. For instance, the step structure may have a depth in a range of about 0.5 mm to about 2.0 mm such that T2exceeds T1by about 0.5 mm to about 2.0 mm. The housing202of the power semiconductor package200may have other creepage extension features without deviating from the scope of the present disclosure.

FIG.7depicts a bottom perspective view of the power semiconductor package200with the housing202transparent according to example embodiments of the present disclosure. As illustrated, a semiconductor die260may be mounted on a mounting substrate250(e.g., conductive lead frame) for the power semiconductor package. The mounting substrate250may be coupled to or integral with the thermal pad230. The semiconductor die260may be attached to the mounting substrate250, for instance, using a die-attach material.

The semiconductor die260may include one or more semiconductor devices, such as MOSFET devices, Schottky diodes, or other devices. In some examples, the semiconductor die260may be based on a wide band gap semiconductor, such as silicon carbide and/or a Group III-nitride (e.g., gallium nitride). For instance, in some examples, the power semiconductor die260may include silicon carbide-based MOSFETs, located between a source contact and a drain contact to form, for instance, a vertical structure power semiconductor device. Aspects of the present disclosure are discussed with reference to silicon carbide-based MOSFET devices for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the power semiconductor die may include other power semiconductor devices without deviating from the scope of the present disclosure, such as diodes (e.g., Schottky diodes, PiN diodes, etc.), insulated gate bipolar transistors, high electron mobility transistors, or other devices.

The semiconductor die260may be, for instance, a 7 mm by 7 mm semiconductor die. However, aspects of the present disclosure are applicable to many different semiconductor die sizes, such as 1 mm by 1 mm semiconductor die to 7 mm by 9 mm semiconductor die, as some examples.

In the example of a semiconductor die260including a silicon carbide-based MOSFET device, the electrical leads210may include a first lead210.1, a second lead210.2, and a third lead210.3. The first lead210.1may include a plurality of integral electrical connection pins. The first lead210.1may be coupled to a source of the MOSFET device on the semiconductor die260using, for instance, wire bonds272. The first lead210.1may be used to connect the source of the MOSFET device on the semiconductor die260to one or more external connections (e.g., on a PCB).

The second lead210.2may include an electrical connection pin (e.g., a single electrical connection pin). The second lead210.2may be coupled to a gate of the MOSFET device on the semiconductor die260using, for instance, wire bond274. The second lead210.2may be used to connect the gate of the MOSFET device on the semiconductor die260to one or more external connections (e.g., on a PCB).

The third lead210.3may include an electrical connection pin (e.g., a single electrical connection pin). The third lead210.3may be coupled to another contact associated with the MOSFET device on the semiconductor die260, such as a source-kelvin contact and/or a sensor contact. The third lead210.3may be coupled to a gate of the MOSFET device on the semiconductor die260using, for instance, wire bond276. The third lead210.3may be used to connect the contact associated with the MOSFET device on the semiconductor die260to one or more external connections (e.g., on a PCB).

The SMT connection structures220may be connected to a drain of the MOSFET device on the semiconductor die260. More particularly, the drain of the MOSFET device may be electrically coupled (e.g., through a die-attach material) to the mounting substrate250. The SMT connection structures220may be electrically coupled to the mounting substrate250. For instance, the SMT connection structures220may be electrically coupled to the mounting substrate150through connection elbows226. The connection elbows226and/or the SMT connection structures120may be integral with the mounting substrate250in some embodiments.

As discussed above, the power semiconductor package200may include a semiconductor die260with other types of semiconductor devices without deviating from the scope of the present disclosure. For instance, in some examples, the semiconductor die260may include a Schottky diode. In this example, one or more of the electrical leads210may be coupled to a first contact of the Schottky diode on the semiconductor die260using, for instance, wire bonds. The SMT connection structures220may be connected to a second contact of the Schottky diode, for instance, through the mounting substrate250(e.g., through the connection elbows126and mounting substrate250).

Variations and modifications may be made to the example power semiconductor devices described herein without deviating from the scope of the present disclosure. For instance, the power semiconductor devices may include electrical leads extending from the first side of the power semiconductor die of varying size and shape.

For instance,FIG.8depicts the example power semiconductor package200ofFIGS.4and5with a different arrangement of electrical leads210according to example embodiments of the present disclosure. The example power semiconductor package200ofFIG.8includes four electrical leads210, namely a first lead210.1, a second lead210.2, a third lead210.3, and a fourth lead210.4. The first lead210.1can have a larger size relative to the second lead210.2, third lead210.3, and fourth lead210.4. In addition, in the example ofFIG.8, the power semiconductor device200may include a trench244as part of the creepage extension structure240for the power semiconductor package200. The trench244may be defined along a peripheral edge of the housing202at the first side202′ of the housing202between the electrical leads210and the thermal pad230. The trench244may have a depth in a range of, for instance, 0.5 mm to about 2.0 mm.

FIG.9depicts the example power semiconductor package200ofFIGS.4and5with another arrangement of electrical leads210according to example embodiments of the present disclosure. The example power semiconductor package200ofFIG.9includes five electrical leads210, namely a first lead210.1, a second lead210.2, a third lead210.3, a fourth lead210.4, and a fifth lead210.5. The first lead210.1can have a larger size relative to the second lead210.2, third lead210.3, fourth lead210.4, and fifth lead210.5. In addition, in the example ofFIG.9, the power semiconductor device200may include a trench244as part of the creepage extension structure240for the power semiconductor package200. The trench244may be defined along a peripheral edge of the housing202at the first side202′ of the housing202between the electrical leads210and the thermal pad230. The trench244may have a depth in a range of, for instance, 0.5 mm to about 2.0 mm.

As demonstrated byFIGS.8and9, the power semiconductor packages according to example embodiments of the present disclosure may have a variety of different electrical lead options for the electrical leads. In this way, the power semiconductor packages according to aspects of the present disclosure are suitable for a variety of different types of semiconductor devices.

FIGS.10and11depicts a power semiconductor package100similar to the power semiconductor package100ofFIGS.1and2. In the example ofFIGS.10and11, the power semiconductor package100includes a different arrangement of electrical leads110relative to the power semiconductor package100ofFIG.1. The example power semiconductor package100ofFIGS.10and11includes three electrical leads110, namely a first lead110.1, a second lead110.2, and a third lead110.3. The first lead110.1can have a larger size relative to the second lead110.2, and third lead110.3.

In addition, in the example power semiconductor package100ofFIGS.10and11, the thermal pad130is electrically isolated from SMT connection structures120. More particularly,FIG.11depicts a top perspective view of the power semiconductor package100ofFIG.10with the housing102transparent according to example embodiments of the present disclosure. As shown, the power semiconductor package100includes a mounting substrate150with an insulating layer152.

FIG.11provides a cross-sectional view of the mounting substrate150taken along line A-A′. The thermal pad130is on the insulating layer152. The insulating layer152may be formed from an insulating material, such as a ceramic material or other insulating material. The insulating substrate152may have a conductive layer154on a surface opposite the thermal pad130. The conductive layer154may be electrically coupled to the SMT connection structures120. The insulating layer152may provide electrical isolation between the thermal pad130and the SMT connection structures120. In some examples, the mounting substrate150may be, for instance, a directed bonded copper (DBC) substrate or an active metal brazed (AMB) substrate.

FIG.12depicts a top perspective view of a power semiconductor package assembly450according to example embodiments of the present disclosure.FIG.13depicts a bottom perspective view of a power semiconductor package assembly450according to example embodiments of the present disclosure. The power semiconductor package assembly450includes a first power semiconductor package300and a second power semiconductor package400. Each of the first power semiconductor package300and the second power semiconductor package400may be similar to any of the power semiconductor packages described herein, such as the power semiconductor package100ofFIG.1.

For instance, the first power semiconductor package300may include a first housing302having a first side302′ and a second side302″ opposing the first side302′. The first power semiconductor package300may include one or more first electrical leads310extending from the first side302′. The first power semiconductor package300may include one or more first SMT connection structures320on the second side302″. For instance, the first power semiconductor package300may include one or more first leadless SMT connection structures320. The first leadless SMT connection structures320may be wettable flank connection structures. The first power semiconductor package300may include a first thermal pad330. The first power semiconductor package300may include one or more first creepage extension structures340. The one or more first creepage extension structures340may include a step structure and/or a trench. The power semiconductor package300may house a semiconductor die having one or more semiconductor devices, such as a MOSFET (e.g., a silicon carbide-based MOSFET) or a Schottky diode (e.g., a silicon carbide-based Schottky diode).

The second power semiconductor package400may include a first housing402having a third side402′ and a fourth side402″ opposing the third side402′. The second power semiconductor package400may include one or more second electrical leads410extending from the third side402′. The second power semiconductor package400may include one or more second SMT connection structures420on the fourth side402″. For instance, the second power semiconductor package400may include one or more second leadless SMT connection structures420. The second leadless SMT connection structures420may be wettable flank connection structures. The second power semiconductor package400may include a second thermal pad. The second power semiconductor package400may include one or more second creepage extension structures440. The one or more second creepage extension structures440may include a step structure and/or a trench. The power semiconductor package400may house a semiconductor die having one or more semiconductor devices, such as a MOSFET (e.g., a silicon carbide-based MOSFET) or a Schottky diode (e.g., a silicon carbide-based Schottky diode).

As illustrated inFIGS.12and13, the second side302″ of the first power semiconductor package300is aligned with the fourth side402″ of the second power semiconductor package400. In this way, the one or more first leadless SMT connection structures320of the first power semiconductor package300are aligned with the one or more second leadless SMT connection structures420of the second power semiconductor package400. The one or more first electrical leads310extend in a first direction C. The one or more second electrical leads410extend in a second direction D. The first direction C is opposite the second direction D. The power semiconductor package assembly450ofFIGS.12and13may facilitate manufacturing of the power semiconductor packages according to example embodiments of the present disclosure.

For instance,FIG.14depicts a flow diagram of an example method500according to example embodiments of the present disclosure.FIG.14depicts example process steps for purposes of illustration and discussion. Those of ordinary skill in the art, using the disclosures provided herein, will understand that process steps of any of the methods described in the present disclosure may be adapted, modified, include steps not illustrated, omitted, and/or rearranged without deviating from the scope of the present disclosure.

At502, the method500may include providing a first power semiconductor package. For instance, the method may include providing the first power semiconductor package300ofFIGS.12and13. The first power semiconductor package300may include a first housing302having a first side302′ and a second side302″ opposing the first side302′. The first power semiconductor package300may include one or more first electrical leads310extending from the first side302′. The first power semiconductor package300may include one or more first SMT connection structures320on the second side302″. For instance, the first power semiconductor package300may include one or more first leadless SMT connection structures320. The first leadless SMT connection structures320may be wettable flank connection structures. The first power semiconductor package300may include a first thermal pad330. The first power semiconductor package300may include one or more first creepage extension structures340. The one or more first creepage extension structures340may include a step structure and/or a trench.

At504ofFIG.14, the method500may include providing a second power semiconductor package. The second power semiconductor package may include providing the second power semiconductor package400ofFIGS.12and13. The second power semiconductor package400may include a first housing402having a third side402′ and a fourth side402″ opposing the third side402′. The second power semiconductor package400may include one or more second electrical leads410extending from the third side402′. The second power semiconductor package400may include one or more second SMT connection structures420on the fourth side402″. For instance, the second power semiconductor package400may include one or more second leadless SMT connection structures420. The second leadless SMT connection structures420may be wettable flank connection structures. The second power semiconductor package400may include a second thermal pad. The second power semiconductor package400may include one or more second creepage extension structures440. The one or more second creepage extension structures440may include a step structure and/or a trench.

In some examples, the second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package. For instance, as shown inFIGS.12and13, the second side302″ of the first power semiconductor package300is aligned with the fourth side402″ of the second power semiconductor package400. In this way, the one or more first leadless SMT connection structures320of the first power semiconductor package300are aligned with the one or more second leadless SMT connection structures420of the second power semiconductor package400. The one or more first electrical leads310extend in a first direction C. The one or more second electrical leads410extend in a second direction D. The first direction C is opposite the second direction D.

At506ofFIG.14, the method may include separating the first power semiconductor package from the second power semiconductor package. For instance, as shown inFIG.15, the first power semiconductor package300may be separated from the second power semiconductor package400as indicated by the arrow representative of operation506ofFIG.14. In this way, the power semiconductor packages according to example embodiments of the present disclosure may be assembled in back-to-back fashion to provide the power semiconductor assembly. The power semiconductor packages may then be separated to provide individual power semiconductor packages.

Example aspects of the present disclosure are set forth below. Any of the below features or examples may be used in combination with any of the embodiments or features provided in the present disclosure.

One example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount type (SMT) connection structures on the second side.

In some examples, the one or more leadless SMT connection structures each comprise a wettable flank connection structure. In some examples, the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing. In some examples, the wettable flank connection structure is exposed through at least one side surface of the housing.

In some examples, each of the one or more leadless SMT connection structures has a larger connection surface relative to each of the one or more electrical leads. In some examples, the power semiconductor package has a greater number of electrical leads on the first side relative to a number of leadless SMT connection structures on the second side. In some examples, the one or more electrical leads comprises a first lead and a second lead, wherein the first lead has a size that is greater than a size of the second lead.

In some examples, the housing comprises a first surface defined between the first side and the second side and a second surface opposing the first surface, wherein the first surface comprises at least one creepage extension structure, the at least one creepage extension structure comprising a step structure. In some examples, the at least one creepage extension structure comprises a first step structure between a thermal pad and the first side of the housing and a second step structure between the thermal pad and the second side of the housing. In some examples, the step structure has a depth of about 0.5 mm to about 2.0 mm. In some examples, the at least one creepage extension structure comprises a trench defined between the step structure and the one or more electrical leads.

In some examples, the power semiconductor package comprises a thermal pad that is electrically isolated from the one or more leadless SMT connection structures. In some examples, the thermal pad is on an insulating layer of a mounting substrate for the semiconductor die.

In some examples, the semiconductor die comprises a wide band gap semiconductor. In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET), wherein a first lead of the one or more electrical leads is connected to a gate of the MOSFET and a second lead of the one or more electrical leads is connected to a source of the MOSFET. In some examples, the one or more leadless SMT connection structures are connected to a drain of the MOSFET. In some examples, a third lead of the one or more electrical leads is connected to a source-kelvin contact of the MOSFET or a sensor contact of the MOSFET. In some examples, the MOSFET comprises a silicon carbide-based MOSFET.

In some examples, the semiconductor die comprises a Schottky diode. In some examples, the one or more electrical leads are coupled to a first contact for the Schottky diode and the one or more SMT connection structures are coupled to a second contact for the Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

Another example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more SMT connection structures on the second side. Each of the one or more SMT connection structures may have a connection surface area that is greater than a connection surface area of the one or more electrical leads.

In some examples, the connection surface area of each of the SMT connection structures is at least two times greater than the connection surface area of each of the one or more electrical leads.

In some examples, the one or more SMT connection structures each comprise a wettable flank connection structure. In some examples, the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing and such that the wettable flank connection structure is exposed through at least one side surface of the housing.

In some examples, each of the one or more SMT connection structures comprises an SMT connection tab extending from the second side of the housing. In some examples, each SMT connection tab extends from a side surface at the second side of housing at a location below a top surface of the housing.

In some examples, the power semiconductor package has a greater number of electrical leads on the first side relative to a number of SMT connection structures on the second side. In some examples, the one or more electrical leads comprises a first lead and a second lead, wherein the first lead has a size that is greater than a size of the second lead.

In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET), wherein a first lead of the one or more electrical leads is connected to a gate of the MOSFET, a second lead of the one or more electrical leads is connected to a source of the MOSFET, and the one or more SMT connection structures are connected to a drain of the MOSFET. In some examples, the MOSFET comprises a silicon carbide-based MOSFET.

In some examples, the semiconductor die comprises a Schottky diode. In some examples, the one or more electrical leads are coupled to a first contact for the Schottky diode and the one or more SMT connection structures are coupled to a second contact for the Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

Another example aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The housing having a first surface extending between the first side and the second side and a second surface opposing the first surface. The power semiconductor package may include a thermal pad. The power semiconductor package may include a step structure on the first surface of the housing. The step structure may be defined in the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness. The second thickness may be greater than the first thickness.

In some examples, the step structure is disposed between the thermal pad and the first side of the housing. In some examples, the first surface further comprises a trench defined between the step structure and the first side of the housing. In some examples, the step structure has a depth of about 0.5 mm to about 2.0 mm.

In some examples, the power semiconductor package comprises one or more electrical leads extending from the first side of the housing and one or more surface mount type (SMT) connection structures on the second side of the housing.

In some examples, the one or more SMT connection structures each comprise an SMT connection tab extending from the second side of the housing.

In some examples, the one or more SMT connection structure each comprise a wettable flank connection structure.

In some examples, the thermal pad is electrically isolated from the one or more SMT connection structures.

In some examples, the semiconductor die comprises a wide band gap semiconductor. In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

Another example aspect of the present disclosure is directed to a method. The method may include providing a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposing the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side, and one or more first leadless surface mount type (SMT) connection structures on the second side. The method may include providing a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposing the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side, and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

In some examples, the method further comprises separating the first power semiconductor package and the second power semiconductor package.

In some examples, the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package. In some examples, the one or more first SMT connection structures each comprise a wettable flank connection structure, and the one or more second SMT connection structures each comprise a wettable flank connection structure.

In some examples, the one or more first electrical leads extend in a first direction, the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

In some examples, the first power semiconductor package comprises a first thermal pad and the second power semiconductor package comprises a second thermal pad.

In some examples, the first power semiconductor package comprises a first creepage extension structure that is part of the first housing, the first creepage extension structure comprising a first step structure, wherein the second power semiconductor package comprises a second creepage extension structure that is part of the second housing, the second creepage extension structure comprising a second step structure. In some examples, the first creepage extension structure comprises a first trench and the second creepage extension structure defines a second trench.

In some examples each of the first power semiconductor package and the second power semiconductor package comprise a wide band gap semiconductor die.

In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

Another example aspect of the present disclosure is directed to a power semiconductor package assembly. The power semiconductor package assembly may include a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposing the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side, and one or more first leadless surface mount type (SMT) connection structures on the second side. The power semiconductor package assembly may include a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposing the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side, and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

In some examples, the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package. In some examples, the one or more first leadless SMT connection structures each comprise a wettable flank connection structure, and the one or more second leadless SMT connection structure each comprise a wettable flank connection structure.

In some examples, the one or more first electrical leads extend in a first direction, the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

In some examples, the first power semiconductor package comprises a first thermal pad and the second power semiconductor package comprises a second thermal pad.

In some examples, the first power semiconductor package comprises a first creepage extension structure that is part of the first housing, the first creepage extension structure comprising a first step structure, wherein the second power semiconductor package comprises a second creepage extension structure that is part of the second housing, the second creepage extension structure comprising a second step structure. In some examples, the first creepage extension structure comprises a first trench and the second creepage extension structure defines a second trench.

In some examples, ach of the first power semiconductor package and the second power semiconductor package comprise a wide band gap semiconductor die.

In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.