SIGNAL AMPLIFYING CIRCUIT AND SIGNAL PROCESSING SYSTEM AND ANALOG-TO-DIGITAL CONVERTING SYSTEM COMPRISING THE SAME

A signal amplifying circuit includes an amplifier and a common mode feedback circuit. The amplifier generates first and second outputs. The common mode feedback circuit receives the first and second outputs, and controls an output common mode voltage of the first and second outputs to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit generates first and second control signals according to the output common mode voltage. The pull-up circuit with a first conduction degree controlled by the first control signal controls the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit with a second conduction degree controlled by the second control signal controls the output common mode voltage to be negatively correlated with the second conduction degree.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 111113928, filed on Apr. 12, 2022, which is herein incorporated by reference in its entirety.

BACKGROUND

Technical Field

The present disclosure relates to a signal amplifying circuit. More particularly, the present disclosure relates to a signal amplifying circuit including a common mode feedback circuit, and to a signal processing system and an analog-to-digital converting system comprising the signal amplifying circuit.

Description of Related Art

The signals inputted to the amplifier include the differential inputs and the common mode noise. The performance of the amplifier can be known by the common mode rejection ratio. The common mode rejection ratio is defined as the differential gain divided by the absolute value of the common mode gain. The higher the value of the common mode rejection ratio, the better the performance of the amplifier. The output common mode voltage of the fully differential amplifier is usually expected to be stable at the average value of the high and low operating voltages thereof, so as to maximize the swing of the differential voltage output of the amplifier. Implementing a common mode feedback circuit in the fully differential amplifier can not only stabilize the output common mode voltage of the amplifier through the common mode feedback circuit, but also efficiently reduce the common mode gain and improve the common mode rejection ratio.

SUMMARY

The disclosure provides a signal amplifying circuit including an amplifier and a common mode feedback circuit. The amplifier is configured to generate a first output and a second output. The common mode feedback circuit is configured to receive the first output and the second output, and is configured to control an output common mode voltage of the first output and the second output to be substantially identical to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit is configured to generate a first control signal and a second control signal according to a value of the output common mode voltage. The pull-up circuit has a first conduction degree controlled by the first control signal, and is configured to control the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit has a second conduction degree controlled by the second control signal, and is configured to control the output common mode voltage to be negatively correlated with the second conduction degree.

The present disclosure provides a signal processing system including an input amplifying stage, a low-pass filter and a delta-sigma modulator. The low-pass filter is configured to filter an output of the input amplifying stage. The delta-sigma modulator includes an integration stage, an adder, a quantizer and a feedback circuit. The integration stage is configured to integrate an output of the low-pass filter, and includes a plurality of stages of integrator. The adder is configured to add the output of the low-pass filter and an output of each stage of integrator. The quantizer is configured to generate a digital signal according to an output of the adder. The feedback circuit is configured to feedback the digital signal to the integration stage. One or more of the input amplifying stage, the integration stage and the adder include a signal amplifying circuit, and the signal amplifying circuit includes an amplifier and a common mode feedback circuit. The amplifier is configured to generate a first output and a second output, so as to correspondingly form the output of the input amplifying stage, the output of each stage of integrator and the output of the adder. The common mode feedback circuit is configured to receive the first output and the second output, and is configured to control an output common mode voltage of the first output and the second output to be substantially identical to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit is configured to generate a first control signal and a second control signal according to a value of the output common mode voltage. The pull-up circuit has a first conduction degree controlled by the first control signal, and is configured to control the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit has a second conduction degree controlled by the second control signal, and is configured to control the output common mode voltage to be negatively correlated with the second conduction degree.

The present disclosure provides an analog-to-digital converting system including an input amplifying stage, a low-pass filter and an analog-to-digital converter. The low-pass filter is configured to filter an output of the input amplifying stage. The analog-to-digital converter is configured to process an output of the low-pass filter to generate a digital signal. The input amplifying stage includes a signal amplifying circuit, and the signal amplifying circuit includes an amplifier and a common mode feedback circuit. The amplifier is configured to generate a first output and a second output to form the output of the input amplifying stage. The common mode feedback circuit is configured to receive the first output and the second output, and is configured to control an output common mode voltage of the first output and the second output to be substantially identical to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit is configured to generate a first control signal and a second control signal according to a value of the output common mode voltage. The pull-up circuit has a first conduction degree controlled by the first control signal, and is configured to control the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit has a second conduction degree controlled by the second control signal, and is configured to control the output common mode voltage to be negatively correlated with the second conduction degree.

DETAILED DESCRIPTION

FIG.1is a simplified functional block diagram of a signal amplifying circuit100according to one embodiment of the present disclosure. The signal amplifying circuit100includes an amplifier110and a common mode feedback (CMFB) circuit120. The amplifier110includes a first input terminal (e.g., the non-inverting input terminal) and a second input terminal (e.g., the inverting input terminal), and includes a first output terminal (e.g., the non-inverting output terminal) and a second output terminal (e.g., the inverting output terminal). The first input terminal of the amplifier110is configured to receive a first input Vip, and the second input terminal is configured to receive a second input Vin. The amplifier110is configured to amplify the difference between the first input Vip and the second input Vin so as to generate a first output Vop and a second output Von respectively at the first output terminal and the second output terminal thereof.

In some embodiments, the amplifier110is one of the following: a Class A amplifier, a Class B amplifier and a Class AB amplifier.

The CMFB circuit120is coupled with the first output terminal and the second output terminal of the amplifier110, and is configured to receive the first output Vop and the second output Von. The CMFB circuit120is configured to control the output common mode voltage of the first output Vop and the second output Von. In some embodiments, the output common mode voltage may be defined as an average voltage of the first output Vop and the second output Von, that is, the output common mode voltage may be Vop+Von/2.

In some embodiments, the CMFB circuit120is configured to receive a first reference voltage Vcm. The CMFB circuit120controls the output common mode voltage to be substantially identical to the first reference voltage Vcm. For example, the output common mode voltage can be within the range of first reference voltage Vcm±10%, or the output common mode voltage can be within the range of first reference voltage Vcm±5%.

In some embodiments, for realizing the aforesaid control, the CMFB circuit120includes an output common mode voltage detection circuit122, a pull-up circuit124, and a pull-down circuit126. The output common mode voltage detection circuit122is coupled with the first output terminal and the second output terminal of the amplifier110, and is configured to receive the first output Vop and the second output Von. The output common mode voltage detection circuit122calculates the value of the output common mode voltage, and generates a first control signal Vbpc and a second control signal Vbnc according to the difference between the output common mode voltage and the first reference voltage Vcm. The pull-up circuit124has a first conduction degree controlled by the first control signal Vbpc, and is configured to control the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit126has a second conduction degree controlled by the second control signal Vbnc, and is configured to control the output common mode voltage to be negatively correlated with the second conduction degree. For example, when the output common mode voltage is higher than the first reference voltage Vcm, the first control signal Vbpc reduces the first conduction degree of the pull-up circuit124, and the second control signal Vbnc increases the second conduction degree of the pull-down circuit126, so as to reduce the output common mode voltage. As another example, when the output common mode voltage is lower than the first reference voltage Vcm, the first control signal Vbpc increases the first conduction degree of the pull-up circuit124, and the second control signal Vbnc reduces the second conduction degree of the pull-down circuit126, so as to increase the output common mode voltage.

As shown inFIG.1, in some embodiments, the pull-up circuit124includes a first pull-up transistor MP1and a second pull-up transistor MP2. The aforementioned first conduction degree may include the conduction degree of the first pull-up transistor MP1and the conduction degree of the second pull-up transistor MP2. The first pull-up transistor MP1is coupled between a first power terminal VA and the first output terminal of the amplifier110. The second pull-up transistor MP2is coupled between the first power terminal VA and the second output terminal of the amplifier110. In some embodiments, the pull-down circuit126includes a first pull-down transistor MN1and a second pull-down transistor MN2. The aforementioned second conduction degree may include the conduction degree of the first pull-down transistor MN1and the conduction degree of the second pull-down transistor MN2. A terminal of the first pull-down transistor MN1is coupled with the second power terminal GA, and another terminal is directly or indirectly coupled with the first output terminal of the amplifier110. A terminal of the second pull-down transistor MN2is coupled with the second power terminal GA, and another terminal is directly or indirectly coupled with the second output terminal of the amplifier110.

In some embodiments, the voltage level of the first power terminal VA is higher than that of the second power terminal GA. In some embodiments, the first power terminal VA provides a high operating voltage (e.g., 1.8 V), and the second power terminal GA provides a low operation voltage (e.g., the ground voltage).

In some embodiments, the first pull-up transistor MP1and the second pull-up transistor MP2are P-type transistors, and the first pull-down transistor MN1and the second pull-down transistor MN2are N-type transistors. When the value of the output common mode voltage is excessively high (higher than the first reference voltage Vcm), the output common mode voltage detection circuit122increases the voltage levels of the first control signal Vbpc and the second control signal Vbnc, so as to reduce the conduction degree of the first pull-up transistor MP1and the second pull-up transistor MP2, and to increase the conduction degree of the first pull-down transistor MN1and the second pull-down transistor MN2. On the other hand, when the output common mode voltage is excessively low (lower than the first reference voltage Vcm), the output common mode voltage detection circuit122reduces the voltage levels of the first control signal Vbpc and the second control signal Vbnc, so as to increase the conduction degree of the first pull-up transistor MP1and the second pull-up transistor MP2, and to decrease the conduction degree of the first pull-down transistor MN1and the second pull-down transistor MN2.

In other words, the voltage levels of the first control signal Vbpc and the second control signal Vbnc are positively correlated with the value of the output common mode voltage. The voltage level of the first control signal Vbpc and the voltage level of the second control signal Vbnc are positively correlated with each other.

FIG.2is a circuit schematic diagram of an output common mode voltage detection circuit200according to one embodiment of the present disclosure. The output common mode voltage detection circuit200may be used to realize the output common mode voltage detection circuit122ofFIG.1, and includes a voltage-averaging circuit210, a differential input pair220, a first loading circuit230, a current mirror circuit240and a second loading circuit250. The voltage-averaging circuit210is configured to receive the first output Vop and the second output Von, and is configured to average the first output Vop and the second output Von to extract the output common mode voltage. The differential input pair220includes a first input terminal and a second input terminal, and the first input terminal and the second input terminal thereof are configured to receive the first reference voltage Vcm and the output common mode voltage, respectively. According to the first reference voltage Vcm and the output common mode voltage, the differential input pair220generates a first current Ia at the side of the first input terminal, and generates a second current Ib at the side of the second input terminal.

The first loading circuit230is coupled with the differential input pair220to generate the first control signal Vbpc according to the first current Ia, such as converting the first current Ia into the first control signal Vbpc that is a voltage signal. The current mirror circuit240is coupled with the differential input pair220to generate a third current Ic according to the second current Ib. The second loading circuit250is coupled with the current mirror circuit240to generate the second control signal Vbnc according to the third current Ic, such as converting the third current Ic into the second control signal Vbnc that is a voltage signal.

In some embodiments, the voltage-averaging circuit210includes a first resistor R1and a second resistor R2that are coupled in series. A terminal of the first resistor R1is configured to receive the first output Vop, and another terminal is coupled with the second resistor R2. A terminal of the second resistor R2is configured to receive the second output Von, and another terminal is coupled with the first resistor R1. A node between the first resistor R1and the second resistor R2is configured to provide the output common mode voltage to the second input terminal of the differential input pair220.

In some embodiments, the differential input pair220includes a transistor M1, a transistor M2and a current source CS1. The transistor M1is coupled between the first loading circuit230and the current source CS1, and a control terminal of the transistor M1is operated as the first input terminal of the differential input pair220. The transistor M2is coupled between the current mirror circuit240and the current source CS1, and a control terminal of the transistor M2is operated as the second input terminal of the differential input pair220.

In some embodiments, the first loading circuit230includes a transistor M3. A first terminal of the transistor M3is coupled with the first power terminal VA, and a second terminal of the transistor M3is configured to receive the first current Ia from the differential input pair220. A control terminal and the second terminal of the transistor M3are coupled with each other, so that the control terminal of the transistor M3generates the first control signal Vbpc.

In some embodiments, the current mirror circuit240includes a transistor M4and a transistor M5. The first terminal of the transistor M4is coupled with the first power terminal VA, and the second terminal of the transistor M4is configured to receive the second current Ib from the differential input pair220, in which a control terminal and the second terminal of the transistor M4are coupled with each other. The first terminal of the transistor M5is coupled with the first power terminal VA, and the second terminal of the transistor M5is configured to provide the third current Ic to the second loading circuit250. The control terminal of the transistor M4is coupled with the control terminal of the transistor M5.

In some embodiments, the second loading circuit250includes a transistor M6. The first terminal of the transistor M6is configured to receive the third current Ic from the current mirror circuit240, and the second terminal of the transistor M6is coupled with the second power terminal GA. The control terminal and the first terminal of the transistor M6are coupled with each other, so that the control terminal of the transistor M6generates the second control signal Vbnc.

FIG.3is a circuit schematic diagram of an output common mode voltage detection circuit300according to one embodiment of the present disclosure. The output common mode voltage detection circuit300can be used to realize the output common mode voltage detection circuit122ofFIG.1, and includes a first switch-capacitor circuit310and a second switch-capacitor circuit320. The first switch-capacitor circuit310is configured to receive the first output Vop, the second output Von, the first reference voltage Vcm and a second reference voltage Vbiasp to generate the first control signal Vbpc. The second switch-capacitor circuit320is configured to receive the first output Vop, the second output Von, the first reference voltage Vcm and a third reference voltage Vbiasn to generate the second control signal Vbnc. In some embodiments, the second reference voltage Vbiasp is higher than the third reference voltage Vbiasn.

The first switch-capacitor circuit310includes capacitors C1-C4and a plurality of switches. The capacitors C1and C2are coupled in parallel through some of the switches, and the capacitors C3and C4are coupled in parallel through other switches. The switches are controlled by a first clock signal CK1and a second clock signal CK2that are non-overlapping with each other. First, the switches controlled by the first clock signal CK1are conducted, while the switches controlled by the second clock signal CK2are switched-off. The first reference voltage Vcm and the second reference voltage Vbiasp are transmitted to two terminals of the capacitor C1and two terminals of the capacitor C3. The first output Vop is transmitted to a first terminal of the capacitor C2, and the second output Von is transmitted to a first terminal of the capacitor C4. Then, the switches controlled by the first clock signal CK1are switched-off, and the switches controlled by the second clock signal CK2are conducted, so that the capacitors C1and C2are conducted to each other to form a parallel connection, and the capacitors C3and C4are conducted to each other to form another parallel connection. Therefore, the first control signal Vbpc generated by a second terminal of the capacitor C2and a second terminal of the capacitor C4can be represented by

The second switch-capacitor circuit320includes capacitors C5-C8and a plurality of switches. The capacitors C5and C6are coupled in parallel through some switches, and the capacitors C7and C8are coupled in parallel through other switches. The second switch-capacitor circuit320has components, connection relationships and operations similar to those of the first switch-capacitor circuit310. That is, the first switch-capacitor circuit310has a first circuit topology, and the second switch-capacitor circuit320has a second circuit topology, in which the first circuit topology is substantially identical to the second circuit topology. The second control signal Vbnc can be represented by

FIG.4is a circuit schematic diagram of an amplifier400according to one embodiment of the present disclosure. The amplifier400is the Class AB amplifier that can be used to realize the amplifier110ofFIG.1. The following paragraphs will describe the embodiments in which the CMFB circuit120is applied to the Class AB amplifier, with reference toFIG.1andFIG.4.

The amplifier400is configured to receive the operating voltages from the first power terminal VA and the second power terminal GA, and is configured to amplify the difference between the first input Vip and the second input Vin to generate the first output Vop and the second output Von. The amplifier400includes a differential input pair, a plurality of current mirror circuits, a non-inverting output stage and an inverting output stage. The differential input pair includes a transistor M7, a transistor M8and a current source CS2. A control terminal of the transistor M7is configured to receive the first input Vip. A control terminal of the transistor M8is configured to receive the second input Vin. The current mirror circuits are respectively formed by (1) a combination of transistors M9, M10and M18, (2) a combination of transistors M11and M12, (3) a combination of transistors M13, M14and M15and (4) a combination of transistors M16and M17. The non-inverting output stage includes the transistors M18and M17. The inverting output stage includes the transistors M12and M13.

A partial circuit of the amplifier400that generates the first output Vop includes the following structures: the transistors M8and M14coupled in series; the transistors M15and M16coupled in series; the transistors M17and M18coupled in series; and the control terminal of the transistor M18coupled between the transistors M7and M9. Therefore, a first output terminal (e.g., the non-inverting output terminal) Nop between the transistors M17and M18generates the first output Vop.

A partial circuit of the amplifier400that generates the second output Von includes the following structures: the transistors M7and M9coupled in series; the transistors M10and M11coupled in series; the transistors M12and M13coupled in series; and the control terminal of the transistor M13coupled between the transistors M8and M14. Therefore, a second output terminal (e.g., the inverting output terminal) Non between the transistors M12and M13generates the second output Von.

As can be known fromFIG.4, in the embodiment in which the CMFB circuit120ofFIG.1is applied to the Class AB amplifier400, the pull-up circuit124is coupled with the pull-down circuit126in series through the first output terminal Nop and the second output terminal Non. In specific, the first pull-up transistor MP1is coupled with the first pull-down transistor MN1in series through the first output terminal Nop, and the second pull-up transistor MP2is coupled with the second pull-down transistor MN2in series through the second output terminal Non.

In some embodiments, the CMFB circuit120ofFIG.1can be applied to the Class B amplifier, that is, the amplifier110ofFIG.1may be the Class B amplifier. A person having ordinary skill in the art will appreciate that the Class B amplifier and the Class AB amplifier have output stages with similar structures. For example, the Class B amplifier may have the first output terminal Nop to provide the first output Vop, and may have the second output terminal Non to provide the second output Von. In the embodiments that pertain to the Class B amplifier, the pull-up circuit124is coupled with the pull-down circuit126in series through the first output terminal Nop and the second output terminal Non. In specific, the first pull-up transistor MP1is coupled with the first pull-down transistor MN1in series through the first output terminal Nop, and the second pull-up transistor MP2is coupled with the second pull-down transistor MN2in series through the second output terminal Non.

FIG.5is a circuit schematic diagram of an amplifier500according to one embodiment of the present disclosure. The amplifier500is the Class A amplifier that can be used to realize the amplifier110ofFIG.1. The following paragraphs will describe the embodiments in which the CMFB circuit120is applied to the Class A amplifier, with reference toFIG.1andFIG.5.

The amplifier500is configured to receive the operating voltages from the first power terminal VA and the second power terminal GA, and is configured to amplify the difference between the first input Vip and the second input Vin to generate the first output Vop and the second output Von. The amplifier500includes the transistors M19-M22and the current source CS3, in which the transistor M19, the transistor M20and the current source CS3form a differential input pair. A control terminal of the transistor M19is configured to receive the first input Vip. A control terminal of the transistor M20is configured to receive the second input Vin. The transistor M22is coupled with the transistor M20in series. A first output terminal (e.g., the non-inverting output terminal) Nop of the amplifier500is between the transistors M20and M22, and is configured to generate the first output Vop. The transistor M21is coupled with the transistor M19in series. A second output terminal (e.g., the inverting output terminal) Non of the amplifier500is between the transistors M19and M21, and is configured to generate the second output Von. The transistors M21and M22have control terminals configured to receive the second reference voltage Vbiasp, but this disclosure is not limited thereto.

As can be known fromFIG.5, in the embodiments in which the CMFB circuit120ofFIG.1is applied to the Class A amplifier500, the pull-up circuit124is coupled with the first output terminal Nop and the second output terminal Non, while the pull-down circuit126is coupled in parallel with the current source CS3of the differential input pair. In specific, the first pull-up transistor MP1is coupled with the first output terminal Nop, and the second pull-up transistor MP2is coupled with the second output terminal Non. A first terminal of the current source CS3is coupled with the transistors M19and M20, and the second terminal of the current source CS3is coupled with the second power terminal GA. The first pull-down transistor MN1is coupled between the first terminal of the current source CS3and the second power terminal GA. The second pull-down transistor MN2is also coupled between the first terminal of the current source CS3and the second power terminal GA.

In some embodiments, the CMFB circuit includes only the pull-up transistors, to ensure the control capability of such CMFB circuit to the output common mode voltage, the pull-up transistors of such CMFB circuit needs a large size (width-to-length ratio), but such design may affect the driving capability of the amplifier under the consideration of power saving, which will be described as follows. In an amplifier circuit design that does not contain the CMFB circuit, the pull-up transistors and the pull-down transistors of the non-inverting output terminal of the amplifier both have the width-to-length ratio of 100, and so does the inverting output terminal of the amplifier. If the CMFB circuit with only the pull-up transistors is applied to such amplifier circuit design, when the pull-up transistors of the CMFB circuit has the width-to-length ratio of 50, the pull-up transistors and the pull-down transistors of the non-inverting output terminal of the amplifier respectively require the width-to-length ratios of 50 and 100, and so does the inverting output terminal of the amplifier, in order to maintain the output current to be essentially identical to that before the CMFB circuit is applied to prevent additional power consumption. However, the above design may excessively reduce the size of the pull-up transistors of the amplifier, causing insufficient pull-up capability of the amplifier.

The CMFB circuit120ofFIG.1, by contrast, uses the pull-up transistors MP1-MP2and pull-down transistors MN1-MN2to cooperatively control the output common mode voltage, instead of using only the pull-up transistors MP1-MP2or only the pull-down transistors MN1-MN2to control. As such, the sizes (width-to-length ration) of the pull-up transistors MP1-MP2and the pull-down transistors MN1-MN2may be designed to be smaller, such as 25 for all of the pull-up and pull-down transistors. Therefore, when the CMFB circuit120is applied to the amplifier, the amplifier can have sufficient pull-up and pull-down capability under the situation that the output current is to be maintained essentially identical to that before the CMFB circuit is applied. In some embodiments, referring toFIG.4, the transistors M12-M13and M17-18may each have a width-to-length ratio of 75, and the pull-up transistors MP1-MP2and the pull-down transistors MN1-MN2may each have a width ratio of 25.

FIG.6is a simplified functional block diagram of a signal processing system600according to one embodiment of the present disclosure. The signal processing system600includes an input amplifying stage610, a low-pass filter620and a delta-sigma modulator630. The input amplifying stage610includes a signal amplifying circuit612and a plurality of feedback resistors. In some embodiments, the signal amplifying circuit612may be implemented by the signal amplifying circuit100ofFIG.1. The input amplifying stage610is configured to generate the first output Vop and the second output Von, according to the first input Vip and the second input Vin. In some embodiments, the first input Vip and the second input Vin may be audio signals generated by a microphone receiving the sound. The low-pass filter620is configured to filter outputs of the input amplifying stage610(i.e., the first output Vop and the second output Von). In some embodiments, the low-pass filter620may be implemented by a resistor-capacitor low-pass filter. For the sake of brevity, a reference sign “X” is used inFIG.6to represent the differential output of the low-pass filter620.

The delta-sigma modulator630includes an integration stage632, an adder634, a quantizer636and a feedback circuit638. The integration stage632includes a plurality of stages of integrators Iga-Igb, a unit delay Bf and a plurality of weighting units Wa-Wc. The plurality of stages of integrators Iga-Igb are configured to integrate the difference between the output X of the low-pass filter620and the output of the feedback circuit638. The output X of the low-pass filter620also passes through the unit delay Bf. Then, the adder634adds the output X of the low-pass filter620and the integration result of each stage of the integrators Iga-Igb (that are applied specific weights by the weighting units Wa-Wc). The quantizer636is configured to generate a first digital signal Do1, according to the output of the adder634. The feedback circuit638is configured to feedback the first digital signal Do1to the integration stage632. In some embodiments, the feedback circuit638may be implemented by the digital-to-analog converter (DAC).

In some embodiments, one or more of the input amplifying stage610, the integration stage632and the adder634include the signal amplifying circuit100ofFIG.1. For example, the fully differential amplifier in each stage of the integrators Iga-Igb can be implemented by the signal amplifying circuit100. The fully differential amplifier of the adder634can be implemented by the signal amplifying circuit100. The differential output generated by the signal amplifying circuit100may correspondingly form the output of the input amplifying stage610, the output of each stage of integrators Iga-Igb or the output of the adder634.

FIG.7is a simplified functional block diagram of an analog-to-digital converting system700according to one embodiment of the present disclosure. The analog-to-digital converting system700includes an input amplifying stage710, a low-pass filter720and an analog-to-digital convertor (ADC)730. The input amplifying stage710is similar to the input amplifying stage610ofFIG.6, that is, the input amplifying stage710includes the signal amplifying circuit100ofFIG.1and a plurality of feedback resistors. The input amplifying stage710is configured to generate the first output Vop and the second output Von, according to the first input Vip and the second input Vin. In some embodiments, the first input Vip and the second input Vin may be audio signals generated by the microphone receiving the sound. The low-pass filter720is configured to filter the output of the input amplifying stage710(i.e., the first output Vop and the second output Von). In some embodiments, the low-pass filter720may be implemented by the resistor-capacitor low-pass filter. The ADC730is configured to process the filtered first output Vop and the filtered second output Von outputted by the low-pass filter720, so as to generate the second digital signal Do2.

Certain terms are used in the specification and the claims to refer to specific components. However, those with ordinary skill in the art would understand that the same components may be referred to by different terms. The specification and claims do not use the differences in terms as a way to distinguish components, but the differences in functions of the components are used as a basis for distinguishing. Furthermore, it should be understood that the term “comprising” used in the specification and claims is open-ended, that is, including but not limited to. In addition, “coupling” herein includes any direct and indirect connection means. Therefore, if it is described that the first component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection or signal connections including wireless transmission, optical transmission, and the like, or the first component is indirectly electrically or signally connected to the second component through other component(s) or connection means.

It will be understood that, in the description herein and throughout the claims that follow, the phrase “and/or” includes any and all combinations of one or more of the associated listed items. Unless the context clearly dictates otherwise, the singular terms used herein include plural referents.