Method for manufacturing a semiconductor device

In a semiconductor layer formed on a first insulating film is formed an element isolation groove extending to the first insulating film. Thereafter, a second insulating film is deposited in the element isolation groove by using a vapor deposition method.

BACKGROUND OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor device in which trench isolation is provided in an SOI (Silicon On Insulator or Semiconductor On Insulator) substrate for element isolation.

A semiconductor device that has an SOI substrate formed from an insulating film and a semiconductor layer thereon and has an element such as transistor or resistance formed at the SOI substrate is known to be advantageous in that it is capable of implementing an increased operation speed or increased voltage resistance due to reduced parasitic capacitance, and capable of implementing increased reliability due to prevention of latch-up, and the like.

FIG. 14shows a cross-sectional structure of a conventional semiconductor device, specifically, a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor formed on the SOI substrate.

As shown inFIG. 14, a semiconductor substrate1is an SOI substrate in which a substrate base portion2and a substrate surface portion3are electrically isolated from each other by a first insulating film4. The substrate base portion2and the substrate surface portion3are both formed from single crystal semiconductor silicon. The substrate surface portion3is covered with a silicon oxide film5in the region other than an element formation region. An element isolation groove (hereinafter, referred to as “trench”)6is formed through the silicon oxide film5and the substrate surface portion3at the location corresponding to an element isolation region.

A second insulating film7of silicon oxide is formed at the wall surface of the trench6. The trench6having the second insulating film7formed at its wall surface is filled with an embedded layer8of polycrystalline silicon. The surface of the embedded layer8is covered with a third insulating film9of silicon oxide. A trench element isolation structure10is thus formed from the second insulting film7, the embedded layer8and the third insulating film9.

A gate electrode12is formed on the region of the substrate surface portion3surrounded by the trench element isolation structure10, i.e., on the element formation region, with a gate insulating film11interposed therebetween. A pair of impurity diffusion layers13serving as source and drain regions are formed on both sides of the gate electrode12in the substrate surface portion3. A MOS transistor14is formed from the gate electrode12, the impurity diffusion layers13and the like. Note that, in the conventional semiconductor device, another element such as bipolar element or resistive element may be formed in the element formation region, instead of or in addition to the MOS transistor14.

FIGS. 15A and 15Bare cross-sectional views illustrating the steps of forming the trench element isolation structure in the conventional semiconductor device of FIG.14.

First, as shown inFIG. 15A, the silicon oxide film5and the substrate surface portion3are etched using a mask pattern15, thereby forming the trench6extending to the first insulating film4. For example, this etching is conducted by a reactive ion etching method using a gas such as hydrogen bromide. The mask pattern15is formed from a resist film patterned by a normal photolithography technique or from a silicon nitride film or a silicon oxide film.

As shown inFIG. 15B, the substrate surface portion3is then thermally oxidized at the wall surface of the trench6, thereby forming a second insulating film7of silicon oxide. Thereafter, the resist film or the silicon nitride film or silicon oxide film used as the mask pattern15for etching is removed.

In the aforementioned conventional method for manufacturing a semiconductor device, however, oxygen atoms are introduced into the interface between the first insulating film4and the substrate surface portion3as well as the interface between the substrate surface portion3and the silicon oxide film5during thermal oxidation for forming the second insulating film7. As a result, a silicon oxide film is grown along each interface (see regions RA and RB in FIG.15B). Oxidation of the single crystal semiconductor silicon of the substrate surface portion3causes volume expansion. Therefore, compressive stresses are generated in the portion of the substrate surface portion3surrounded by the trench6, i.e., in the semiconductor layer of the element formation region, thereby producing crystal defects in the semiconductor layer. This problem becomes more remarkable when attempting dimensional reduction of the element, reduction in thickness of the single crystal silicon film serving as the substrate surface portion3.

In order to solve the aforementioned problem, Japanese Patent Gazette No. 2589209B discloses a method for relieving the stresses causing generation of crystal defects. More specifically, after a trench is formed, a polycrystalline semiconductor film is deposited in the trench in a reduced-pressure vapor phase so as to round a trench corner. A thermal oxide film is formed thereafter. Thus, the stresses are relieved particularly in the lower corner (which corresponds to the region RA of FIG.15B).

According to the method of the aforementioned Japanese Patent Gazette No. 2589209B, however, the curvature of each corner depends on the coating profile of the polycrystalline semiconductor film. Therefore, the degree of stress relief in the thermal oxidation step after deposition of the polycrystalline semiconductor film varies depending on the coating profile. This means that the aforementioned crystal defects may possibly be generated. Accordingly, the crystal defects are more likely to be generated depending on the degree of process variation, and this may become a critical cause of the reduced yield of the element.

SUMMARY OF THE INVENTION

In view of the foregoing problems, it is an object of the present invention to completely preventing crystal defects from being generated in a semiconductor layer of an element formation region due to the stresses applied to, e.g., a trench corner upon forming a trench element isolation structure in an SOI substrate.

In order to achieve the aforementioned object, a method for manufacturing a semiconductor device according to the present invention includes the steps of: forming, in a semiconductor layer formed on a first insulating film, an element isolation groove extending to the first insulating film; and depositing a second insulating film in the element isolation groove by using a vapor deposition method.

According to the manufacturing method of the present invention, the element isolation groove extending to the first insulating film is formed in the semiconductor layer on the first insulating film, and the second insulating film is deposited in the element isolation groove by using a vapor deposition method. This enables the trench element isolation structure to be formed in the SOI substrate without forming a thermal oxide film at the wall surface of the element isolation groove. In other words, the thermal oxidation step is no longer required that causes an oxide film to be grown along the interface between the first insulating film and the semiconductor layer. As a result, crystal defects can be completely prevented from being generated in the semiconductor layer of the element isolation region due to the stresses applied to the trench corner or the like.

In the manufacturing method of the present invention, the step of depositing the second insulating film is preferably conducted so as to partially fill the element isolation groove, and the method preferably further includes, after the step of depositing the second insulating film, the step of forming an embedded layer so as to completely fill the element isolation groove.

In this case, forming the embedded layer from the same material as that of the semiconductor layer would eliminate the difference of a physical constant such as thermal expansion coefficient between the embedded layer and the semiconductor layer. Therefore, in various thermal processing steps in the semiconductor manufacturing process as well, stress generation can be suppressed as compared to the case where the element isolation groove is filled only with an insulating film, thereby enabling improvement in reliability of the element.

The manufacturing method of the present invention may further include, after the step of forming the embedded layer, the step of forming a third insulating film on the embedded layer. In this case, degradation in. reliability of the element does not occur even when the embedded layer is electrically conductive.

Preferably, the manufacturing method of the present invention further includes, between the step of forming the element isolation groove and the step of depositing the second insulating film, the step of forming an oxide film by oxidizing the semiconductor layer at a wall surface of the element isolation groove, and the step of depositing the second insulating film preferably includes the step of depositing the second insulating film so as to cover the oxide film.

Thus, the trench element isolation structure can be implemented by the laminated structure of the oxide film formed at the wall surface of the element isolation groove by oxidation (specifically, thermal oxidation) and the second insulating film formed on the oxide film by a vapor deposition method. This enables significant reduction in thickness of the oxide film formed at the wall surface of the element isolation groove. As a result, in the thermal oxidation step of forming the oxide film, the thickness of the oxide film can be set so as to prevent crystal defects from being generated due to the stresses intensively applied to the trench corner or the like.

Preferably, the oxide film has a thickness of 50 nm or less.

This ensures that crystal defects are prevented from being generated in the thermal oxidation step of forming the oxide film.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the figures.

FIGS. 1to5are cross-sectional views illustrating the steps of the method for manufacturing a semiconductor device according to the first embodiment.

First, as shown inFIG. 1, a semiconductor substrate101having an SOI structure is prepared. In the semiconductor substrate101, a substrate base portion102and a substrate surface portion103are laminated each other with a first insulating film104of silicon oxide interposed therebetween. The substrate base portion102and the substrate surface portion103are both formed from single crystal semiconductor silicon. Thereafter, photoresist is applied to the whole surface of the substrate surface portion103of the semiconductor substrate101so as to form a resist film. By using a photolithography technique, the resist film thus formed is patterned into a resist pattern105having an opening on a prescribed region that will result in an element isolation region in a later step. The substrate surface portion103is then dry-etched using the resist pattern105as an etching mask, whereby an element isolation groove106extending to the first insulating film104of the semiconductor substrate101is formed through the substrate surface portion103. Note that, in the step of dry-etching the substrate surface portion103, the first insulating film104can be used as an etching stopper.

Thereafter, the resist pattern105is removed. As shown inFIG. 2, by using a vapor deposition method, a second insulating film107of silicon oxide is then deposited on the whole surface of the substrate surface portion103including the inside of the element isolation groove106so as to partially fill the element isolation groove106. Thereafter, an embedded layer108of polycrystalline silicon is formed on the second insulating film107so as to completely fill the element isolation groove106.

Then, the embedded layer108is etched back by anisotropic dry etching such as RIE (Reactive Ion Etching). Thus, as shown inFIG. 3, the embedded layer108located outside the element isolation groove106is removed, so that the embedded layer108remains only within the element isolation groove106. Subsequently, the upper portion of the remaining embedded layer108is thermally oxidized in the furnace step, forming a third insulating film109of silicon oxide at the surface of the embedded layer108. Note that, in the step of etching back the embedded layer108, the second insulating film107can be used as an etching stopper.

Thereafter, photoresist is applied to the whole surface of the semiconductor substrate101so as to form a resist film (not shown). The resist film thus formed is patterned into a resist pattern (not shown) having an opening on an element formation region. The second insulating film107is then subjected to, e.g., wet etching using the resist pattern as an etching mask. Thus, the second insulating film107located on the element formation region is removed, as shown in FIG.4. The resist pattern is then removed, thereby completing formation of a trench element isolation structure110including the second insulating film107, the embedded layer108and the third insulating film109.

Thereafter, a desired element is formed in the element formation region having the second insulating film107removed, that is, in the region of the substrate surface portion103surrounded by the trench element isolation structure110. More specifically, in the first embodiment, a gate electrode112having a desired shape is formed on the substrate surface portion103of the semiconductor substrate101with a gate oxide film111interposed therebetween, as shown in FIG.5. Thereafter, ions are implanted into the substrate surface portion103by using the second and third insulating films107,109of the trench element isolation structure110and the gate electrode112as a mask. Thus, a pair of impurity diffusion layers113having a desired conductivity type are formed as source and drain regions on both sides of the gate electrode112in the substrate surface portion103. As a result, a MOS transistor114is formed from the gate electrode112, the impurity diffusion layers113and the like.

As has been described above, according to the first embodiment, the element isolation groove106extending to the first insulating film104is formed in the substrate surface portion103(i.e., single crystal silicon layer) on the first insulating film104. The second insulating film107is then deposited in the element isolation groove106by using a vapor deposition method. Therefore, the trench element isolation structure110can be formed in the semiconductor substrate101, i.e., the SOI substrate, without forming a thermal oxide film at the wall surface of the element isolation groove106. In other words, the thermal oxidation step is no longer required which causes an oxide film to be grown along the interface of the first insulating film104and the substrate surface portion103. As a result, crystal defects can be completely prevented from being generated in the single crystal silicon layer of the element formation region due to the stresses applied to, e.g., the lower corner of the element isolation groove106. Accordingly, reliability of the element is significantly improved, resulting in significantly improved yield of the semiconductor device.

Moreover, according to the first embodiment, the second insulating film107is deposited so as to partially fill the element isolation groove106, and the embedded layer108is formed on the second insulating film107so as to completely fill the element isolation groove106. The embedded layer108is formed from the same material (silicon) as that of the substrate surface portion103. Therefore, stress generation due to the factors such as the difference of the thermal expansion coefficient between the embedded layer108and the substrate surface portion103can be suppressed, thereby enabling improvement in reliability of the element. Furthermore, the third insulating film109is formed at the surface of the embedded layer108. Therefore, degradation in reliability of the element does not occur even when the embedded layer108is electrically conductive.

Note that, in the first embodiment, the element isolation groove106is formed using the resist pattern105as an etching mask. However, the element isolation groove106may alternatively be formed using, e.g., a silicon oxide film, a silicon nitride film (see the second embodiment described below), or a laminated film of silicon oxide film and silicon nitride film as an etching mask.

Moreover, in the first embodiment, it is preferable to conduct the furnace step of annealing the second insulting film107(the annealing may be conducted either in the nitrogen atmosphere or oxygen atmosphere) after the second insulating film107is formed within the element isolation groove106. This can make the second insulating film107dense, thereby improving the electric insulation property of the second insulating film107.

Moreover, in the first embodiment, it is preferable to use a chemical vapor deposition method as a method for depositing the second insulating film107. This enables a uniform coating structure of the second insulating film107to be provided inside the element isolation groove106.

Moreover, in the first embodiment, the embedded layer108is etched back so as to remain only within the element isolation groove106. Thereafter, the furnace step of thermally oxidizing the upper portion of the remaining embedded layer108is conducted. The second insulating film107located on the element formation region is then removed using the resist pattern as an etching mask. However, the first embodiment may alternatively be implemented as follows: the embedded layer108is etched back so as to remain only within the element isolation groove106. The second insulating film107located on the element formation region is then removed using the resist pattern as an etching mask. Thereafter, the resist pattern is removed, and the furnace step of thermally oxidizing the upper portion of the remaining embedded layer108is then conducted.

Although polycrystalline silicon is used as a material of the embedded layer108in the first embodiment, another material such as amorphous silicon may alternatively be used. It should be noted that the embedded layer108is preferably formed from the same material as that of the substrate surface portion103. This eliminates the difference of a physical constant such as thermal expansion coefficient between the embedded layer108and the substrate surface portion103. Therefore, in various thermal processing steps in the semiconductor manufacturing process as well, stress generation can be suppressed as compared to the case where the element isolation groove106is filled only with an insulating film, thereby enabling improvement in reliability of the element. Furthermore, end-point detection in the step of etching back the embedded layer108is also facilitated.

Moreover, in the first embodiment, the MOS transistor114is formed in the element formation region. However, it should be understood that the present invention is not limited to this and another element such as bipolar element or resistive element may alternatively be formed therein.

Second Embodiment

Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference the figures.

FIGS. 6to13are cross-sectional views illustrating the steps of the method for manufacturing a semiconductor device according to the second embodiment.

First, as shown inFIG. 6, a semiconductor substrate201having an SOI structure is prepared. In the semiconductor substrate201, a substrate base portion202and a substrate surface portion203are laminated each other with a first insulating film204of silicon oxide interposed therebetween. The substrate base portion202and the substrate surface portion203are both formed from single crystal semiconductor silicon.

Note that, in the second embodiment, a silicon oxide film205is formed in the region other than an element formation region in the substrate surface portion203by a LOCOS (Local Oxidation of Silicon) method. In other words, in the second embodiment, the LOCOS element isolation method and the trench element isolation method are combined, so that an appropriate element isolation method can be used according to the type of the element to be formed. For example, when a BiCMOS (Bipolar-CMOS (Complementary Metal Oxide Semiconductor)) integrated circuit is to be formed, the trench element isolation method is used for isolation of the bipolar element, whereas the LOCOS element isolation method is used for isolation of the MOS transistor.

Subsequently, as shown inFIG. 6, a silicon nitride film206is formed on the whole surface of the semiconductor substrate201by using a vapor deposition method. Photoresist is then applied to the whole surface of the semiconductor substrate201so as to form a resist film (not shown). By using a photolithography technique, the resist film thus formed is patterned into a resist pattern (not shown) having an opening on a prescribed region that will result in an element isolation region in a later step. The silicon nitride film206and the silicon oxide film205are then sequentially dry-etched for patterning using the resist pattern as an etching mask. The resist pattern is then removed. Thereafter, the substrate surface portion203is dry-etched using the patterned silicon nitride film206as an etching mask, whereby an element isolation groove207extending to the first insulating film204of the semiconductor substrate201is formed through the substrate surface portion203. Note that, in the step of dry-etching the substrate surface portion203, the first insulating film204can be used as an etching stopper.

As shown inFIG. 7, by using the furnace step, the substrate surface portion203is then thermally oxidized at the wall surface of the element isolation groove207, thereby forming an oxide film208, i.e., a silicon oxide film. The oxide film208functions as an electrically insulating film. In the second embodiment, this furnace step is conducted so that the oxide film208has a thickness of about 2 nm to about 50 nm. By using a vapor deposition method, a second insulating film209of silicon oxide is then deposited on the whole surface of the semiconductor substrate201including the inside of the element isolation groove207so as to cover the oxide film208and partially fill the element isolation groove207. Thereafter, an embedded layer210of polycrystalline silicon is formed on the second insulating film209so as to completely fill the element isolation groove207.

As shown inFIG. 8, the embedded layer210is then etched back by anisotropic dry etching such as RIE. Thus, the embedded layer210located outside the element isolation groove207is removed, so that the embedded layer210remains only within the element isolation groove207. Note that, in the step of etching back the embedded layer210, the second insulating film209can be used as an etching stopper.

As shown inFIG. 10, a third insulating film211is then deposited on the whole surface of the semiconductor substrate201by using a vapor deposition method. Photoresist is then applied to the whole surface of the third insulating film211so as to form a resist film (not shown). The resist film thus formed is patterned into a resist pattern (not shown) having an opening on the element formation region. The third insulating film211is then subjected to, e.g., wet etching using the resist pattern as an etching mask. Thus, the third insulating film211located on the element formation region is removed, as shown in FIG.11. The resist pattern is then removed, thereby completing formation of a trench element isolation structure212including the oxide film208, the second insulating film209, the embedded layer210and the third insulating film211.

Thereafter, a desired element is formed in the element formation region having the third insulating film211removed, that is, in the region of the substrate surface portion203surrounded by the trench element isolation structure212. More specifically, in the second embodiment, a gate electrode214having a desired shape is formed on the substrate surface portion203of the semiconductor substrate201with a gate oxide film213interposed therebetween, as shown in FIG.12. Thereafter, ions are implanted into the substrate surface portion203by using the silicon oxide film205, the third insulating film211of the trench element isolation structure212and the gate electrode214as a mask. Thus, a pair of impurity diffusion layers215having a desired conductivity type are formed as source and drain regions on both sides of the gate electrode214in the substrate surface portion203. As a result, a MOS transistor216is formed from the gate electrode214, the impurity diffusion layers215and the like.

As has been described above, according to the second embodiment, the trench element isolation structure212can be implemented by the laminated structure of the oxide film208formed at the wall surface of the element isolation groove207by thermal oxidation and the second insulating film209formed on the oxide film208by a vapor deposition method. This enables significant reduction in thickness of the oxide film208formed at the wall surface of the element isolation groove207. As a result, in the thermal oxidation step of forming the oxide film208, the thickness of the oxide film208can be set so as to prevent crystal defects from being generated in the substrate surface portion203(i.e., single crystal silicon layer) of the element formation region due to the stresses intensively applied to, e.g., the lower corner of the element isolation groove207. Accordingly, reliability of the element is significantly improved, resulting in significantly improved yield of the semiconductor device.

Moreover, according to the second embodiment, the second insulating film209is deposited so as to partially fill the element isolation groove207, and the embedded layer210is formed on the second insulating film209so as to completely fill the element isolation groove207. The embedded layer210is formed from the same material (silicon) as that of the substrate surface portion203. Therefore, stress generation due to the factors such as the difference of the thermal expansion coefficient between the embedded layer210and the substrate surface portion203can be suppressed, thereby enabling improvement in reliability of the element. Furthermore, the third insulating film211is formed on the embedded layer210. Therefore, degradation in reliability of the element does not occur even when the embedded layer210is electrically conductive.

Note that, in the second embodiment, the oxide film208preferably has a thickness of 50 nm or less. This ensures that crystal defects are prevented from being generated in the thermal oxidation step of forming the oxide film208.

Moreover, in the second embodiment, the element isolation groove207is formed using the silicon nitride film206as an etching mask. However, the element isolation groove207may alternatively be formed using, e.g., a silicon oxide film or a laminated film of silicon oxide film and silicon nitride film as an etching mask. Alternatively, like the first embodiment, the element isolation groove207may be formed using a resist pattern as an etching mask.

Moreover, in the second embodiment, it is preferable to conduct the furnace step of annealing the second insulting film209(the annealing may be conducted either in the nitrogen atmosphere or oxygen atmosphere) after the second insulating film209is formed within the element isolation groove207. This can make the second insulating film209dense, thereby improving the electric insulation property of the second insulating film209.

Moreover, in the second embodiment, it is preferable to use a chemical vapor deposition method as a method for depositing the second insulating film209. This enables a uniform coating structure of the second insulating film209to be provided inside the element isolation groove207.

Moreover, in the second embodiment, the second insulating film209is formed on the semiconductor substrate201including the inside of the element isolation groove207, and the embedded layer210is then formed on the second insulating film209so as to completely fill the element isolation groove207. The embedded layer210is then etched back so as to remain only within the element isolation groove207. Thereafter, the second insulating film209contacting with the silicon nitride film206, and the silicon nitride film206are sequentially removed. However, the second embodiment may alternatively be implemented as follows: the silicon nitride film206is removed after formation of the element isolation groove207. Thereafter, the second insulating film209is formed on the semiconductor substrate201including the inside of the element isolation groove207, and the embedded layer210is then formed on the second insulating film209so as to completely fill the element isolation groove207. The embedded layer210is then etched back so as to remain only within the element isolation groove207. Thereafter, the second insulating film209located outside the element isolation groove207is removed. The second insulating film209located outside the element isolation groove207may be removed by wet etching or dry etching immediately after the embedded layer210is etched back. Alternatively, after the embedded layer210is etched back, the third insulating film211may be formed on the semiconductor substrate201so that the second insulating film209located on the element formation region is removed simultaneously with the third insulating film211located on the element formation region.

Moreover, in the second embodiment, there may be the case where a pair of element isolation grooves207are located adjacent to each other in the region other than the element formation region (i.e., in the region of the substrate surface portion203covered with the silicon oxide film205), as shown in FIG.13. In such a case, in the step of removing the third insulating film211located on the element formation region, the third insulating film211may be patterned so as to continuously cover the pair of element isolation grooves207.

Although polycrystalline silicon is used as a material of the embedded layer210in the second embodiment, another material such as amorphous silicon may alternatively be used. It should be noted that the embedded layer210is preferably formed from the same material as that of the substrate surface portion203. This eliminates the difference of a physical constant such as thermal expansion coefficient between the embedded layer210and the substrate surface portion203. Therefore, in various thermal processing steps in the semiconductor manufacturing process as well, stress generation can be suppressed as compared to the case where the element isolation groove207is filled only with an insulating film, thereby enabling improvement in reliability of the element. Furthermore, end-point detection in the step of etching back the embedded layer210is also facilitated.

Moreover, in the second embodiment, the MOS transistor216is formed in the element formation region. However, it should be understood that the present invention is not limited to this and another element such as bipolar element or resistive element may alternatively be formed therein.