Semiconductor device having high yield strength intermediate plate

A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device.

FIELD

The present invention relates to a power semiconductor device such as an IGBT, a MOSFET, or a diode.

BACKGROUND

There is disclosed a semiconductor device in which a semiconductor chip is bonded to an aluminum electrode substrate via solder and a copper electrode is bonded to the upper surface of the semiconductor chip via solder (for example, see PTL 1).

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

However, there exists a point where a yield strength relation between the aluminum electrode substrate and the solder is reversed within a temperature range in cooling/heating cycles and power cycles, that is, an operating temperature range of the semiconductor device. Therefore, the aluminum electrode substrate and the solder are deformed and do not return to the individual original positions. Furthermore, when the deformation amounts thereof are accumulated to be large, the semiconductor chip is finally deformed, which problematically causes deterioration of its reliability. In particular, for an SiC chip usable at high temperature or the like, the operating temperature range is wide, which causes large temperature stress.

For example, deformation of a semiconductor chip can be suppressed by covering the upper surface of the semiconductor chip with transfer molding resin. However, in the semiconductor device in which solder bonding on the upper surface of a semiconductor chip is performed, since the upper surface of the semiconductor chip is covered by solder, which tends to be deformed, it cannot be fixed with the molding resin, and therefore, it is problematically difficult for deformation of the semiconductor chip to be suppressed.

The present invention is devised in order to solve the problems as above, and an object thereof is to obtain a semiconductor device capable of improving reliability regarding cooling/heating cycles and power cycles.

Solution to Problem

A semiconductor device according to the present invention includes: an electrode substrate; a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder; a lead frame bonded to an upper surface of the semiconductor chip via a second solder; and an intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip, wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device.

Advantageous Effects of Invention

In the present invention, the intermediate plate is provided in the first solder between the electrode substrate and the semiconductor chip. Further, the yield strength of the intermediate plate is higher than the yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device. Therefore, reliability regarding cooling/heating cycles and power cycles can be improved.

DESCRIPTION OF EMBODIMENTS

A semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

FIG.1is a cross-sectional view illustrating a semiconductor device according to Embodiment 1. The semiconductor device according to the present embodiment is used for a power supply which drives, for example, a motor for vehicular power. A semiconductor chip3is bonded to the upper surface of an electrode substrate1via a first solder2. A lead frame5is bonded to the upper surface of the semiconductor chip3via a second solder4.

The semiconductor chip3is a switching semiconductor device such as an IGBT or a MOSFET, or a freewheeling semiconductor device such as a diode, these being formed, for example, of silicon. The thickness of the semiconductor chip3is optimized in accordance with the withstand voltage class thereof. For example, with the voltage of a lithium ion battery which is often used for a hybrid vehicle or an electric vehicle taken into consideration, the withstand voltage class of the semiconductor chip3is desirably 600 V to 800 V. In order to improve electric characteristics, in particular, a DC loss, the thickness of the semiconductor chip3is desirably 100 μm or less.

The electrode substrate1is formed, for example, on an insulating substrate into a plate shape by rolling or casting. Notably, on the lower surface of the insulating substrate, a conductor substrate is provided and a plurality of cooling projections are provided on the conductor substrate. By directly bringing cooling water onto the conductor substrate and the plurality of cooling projections, heat generated from the semiconductor chip3can be efficiently cooled. The electrode substrate1, the conductor substrate and the plurality of cooling projections can be integrally formed by being casted to surround the insulating substrate through aluminum casting. The main material of the electrode substrate1and the like is aluminum. Thereby, corrosion resistance against the cooling water is secured while electric and thermal conductivity is maintained, and costs and weight can be suppressed. Moreover, in order to improve thermal conduction, aluminum with 99% or more of high purity is desirable.

The first and second solders2and4are, for example, Sn—Cu-based, Sn—Ag-based or Sn—Ag—Cu-based lead-free solder. Thereby, the semiconductor chip3can be easily electrically and thermally bonded to the lead frame5or the electrode substrate1in a reducing atmosphere. Further, the first and second solders2and4can maintain their solid phase states even at or below 200° C. which is an operating temperature range of the semiconductor chip3.

The main material of the lead frame5is, for example, copper. The lead frame5is processed into an arbitrary shape by punching processing after a Cu plate material is formed, for example, by rolling a Cu material. The lead frame5is electrically connected to the second solder4.

Notably, solder bonding metal films composed of materials containing Ni are individually formed on the upper surface and the lower surface of the semiconductor chip3by an electroplating method, sputtering, or a vapor phase deposition method such as vapor deposition. The solder bonding metal films on the upper surface and the lower surface are electrically and thermally connected respectively to the first and second solders2and4.

Between the electrode substrate1and the semiconductor chip3, an intermediate plate6is provided in the first solder2. The main material of the intermediate plate6is copper. The intermediate plate6is processed into an arbitrary shape by punching processing after a Cu plate material is formed, for example, by rolling a Cu material.

The upper surface of the electrode substrate1, the first solder2, the semiconductor chip3, the second solder4, the intermediate plate6and a part of the lead frame5are covered by a sealing material7. As the sealing material7, transfer molding resin or potting resin can be used. The semiconductor chip3can be suppressed from being deformed at the portion where the sealing material7is in direct contact with the semiconductor chip3.

Subsequently, a manufacturing method of the semiconductor device according to the present embodiment is described. First, the intermediate plate6, the first solder2and the semiconductor chip3are sequentially stacked on the electrode substrate1. Next, the first solder2is heated and melted in a reducing atmosphere, and the lower surface of the semiconductor chip3is electrically and thermally bonded to the upper surface of the electrode substrate1via the first solder2and the intermediate plate6. In order to gain the maximum thermal bonding, it is desirable for almost the whole surface of the lower surface of the semiconductor chip3to be bonded. Moreover, in order to prevent voids from arising due to air drawn into the first solder2, it is desirable for the air to be discharged from the first solder2by melting the first solder2under a reduced pressure, and after that, recovering the pressure. The order of stacking the intermediate plate6and the first solder2may be reversed. In this case, when the intermediate plate6is placed right below the semiconductor chip3, by performing the placement such that burrs of the intermediate plate6due to the punching processing face the first solder2side, the semiconductor chip3can be prevented from being damaged, which can improve the yield.

Next, the lead frame5is electrically connected to the upper surface of the semiconductor chip3using the second solder4. Herein, the upper surface of the semiconductor chip3is not needed to be thermally bonded to the lead frame5. Moreover, it is needed to secure the creeping distance between the end part of the semiconductor chip3and the lead frame5. Further, it is needed to connect signal terminals on the upper surface of the semiconductor chip3to external electrodes using conductor wires or the like. Therefore, the lead frame5is bonded partially to the upper surface of the semiconductor chip3. Next, the upper surface of the electrode substrate1, the first solder2, the semiconductor chip3, the second solder4, the intermediate plate6and at least part of the lead frame5are covered by the sealing material7. Through the process above, the semiconductor device according to the present embodiment is manufactured.

FIG.2is a diagram illustrating temperature dependencies of yield strengths of the electrode substrate, the first and second solders and the intermediate plate. Herein, the yield strength indicates the 0.2% yield strength, which is a stress causing 0.2% plastic strain in unloading for many metal materials which do not exhibit a yield phenomenon. There exists a point where magnitude relation between the yield strength of the electrode substrate1and the yield strength of the first and second solders2and4is reversed within an operating temperature range of the semiconductor device. Accordingly, the first solder2and the electrode substrate1are deformed in different temperature ranges. For example, the electrode substrate1is hardly deformed when the first solder2is deformed, and the first solder2is hardly deformed when the electrode substrate1is deformed. Therefore, the position of each material does not return to the original one but the deformation amount thereof is accumulated. The deformation amount increases due to repetition of cooling/heating cycles.

Therefore, in the present embodiment, the intermediate plate6is provided in the first solder2between the electrode substrate1and the semiconductor chip3. Further, the yield strength of the intermediate plate6is higher than the yield strengths of the electrode substrate1and the first solder2within the whole operating temperature range of the semiconductor device. Accordingly, even when the electrode substrate1and the first solder2are deformed during cooling/heating cycles, the intermediate plate6is not deformed, and hence, the semiconductor chip3can be suppressed from being deformed. In particular, right below the second solder4, since the semiconductor chip3is not in direct contact with the sealing material7, the sealing material7does not reach it in terms of its force of fixing. In the case of deformation of the second solder4due to stress caused by cooling/heating cycles and power cycles, the force of constraint is lost and the semiconductor chip3tends to result in deformation. On the contrary, since the intermediate plate6which is hardly deformed is provided below the semiconductor chip3, the semiconductor chip3can be suppressed from being deformed. As a result, reliability regarding cooling/heating cycles and power cycles can be improved. Notably, while in the present embodiment, the materials of the first and second solders2and4are the same, even if they are different materials, the similar effect can be obtained as long as they have the aforementioned yield strength relation.

Moreover, in the case of using a semiconductor chip usable at high temperature, such as silicon carbide, the high temperature side of the operating temperature range is expanded up to 200° C. Moreover, for automobile application, the low temperature side thereof is expanded down to −55° C. Therefore, the deformation amounts of the electrode substrate1and the first solder2tend to become large, and it is needed for deformation of the semiconductor chip3to be suppressed by the intermediate plate6.

Moreover, stress due to cooling/heating cycles arises caused by a difference in coefficient of linear expansion between the intermediate plate6and the first solder2. This stress reaches its maximum at the end parts of the semiconductor chip3. If the first solder2is segmented by the intermediate plate6, the thickness of the first solder2becomes small at the end parts of the semiconductor chip3, which causes large stress. In particular, if the intermediate plate6is inclined in the first solder2, the thickness of the end part of the first solder2partially becomes further smaller, which causes significantly larger stress. Therefore, the intermediate plate6is made smaller than the semiconductor chip3and the first solder2, and it is positioned inward of the semiconductor chip3and the first solder2in planar view. Thereby, the intermediate plate6can be completely buried in the first solder2, and the first solder2can be prevented from being segmented at the end part of the first solder2by the intermediate plate6. As a result, reliability regarding cooling/heating cycles can be further improved.

Moreover, the end parts of the intermediate plate6are withdrawn inward from the end parts of the semiconductor chip3, and the intermediate plate6is set not to be exposed from the first solder2. Specifically, a distance d1between the end part of the semiconductor chip3and the end part of the intermediate plate6is set to be larger than a thickness t1of the first solder2. Thereby, even if the intermediate plate6is inclined in the first solder2, the thickness of the first solder2does not become smaller at the end part of the semiconductor chip3, which can achieve stable reliability.

Moreover, the second solder4is positioned inward of the intermediate plate6in planar view. When the second solder4is deformed due to stress caused by power cycles, the semiconductor chip3results in its deformation. Therefore, by supporting it with the intermediate plate6, the semiconductor chip3can be suppressed from being deformed.

FIG.3is a plan view illustrating an intermediate plate according to Embodiment 2.FIG.4is a cross-sectional view taken along I-II inFIG.3. The present embodiment is similar to Embodiment 1 except the configuration of the intermediate plate6.

A plurality of through holes8are provided in the intermediate plate6, for example, by punching processing. Thereby, since the first solder2can wet and spread both the upside and the downside through the through holes8, it is not needed for the first solder2to be placed on both the upper surface side and the lower surface side of the intermediate plate6. Accordingly, the number of components for the first solder2and assembly operation thereof can be reduced, and production costs can be reduced.

Moreover, a plating film9covers the surfaces of the intermediate plate6. The main material of the plating film9is nickel, and the plating film9has higher wettability to the first solder2than that of the intermediate plate6. Thereby, since the solder wettability can be improved, a void defect rate can be reduced, and a production loss cost can be reduced.

Moreover, since the plating film9is formed after punching processing of the through holes8, it is also formed on the sidewalls of the plurality of through holes8. Thereby, since the first solder2also wets and spreads in the sidewalls of the through holes8and the insides of the through holes8are filled with it, voids can be suppressed from arising, and reliability can be improved.

Moreover, it is preferable that the dimension of the through hole8be 500 μmΦ or less. Although voids are formed in the first solder2when air is drawn into the plurality of through holes8, there is a little thermal harmful influence with the void diameter being 500 μm or less, and deterioration in heat resistance and reduction in short circuit resistance hardly arise. Moreover, when air exceeding 500 μmΦ is drawn into the plurality of through holes8, since the air void is subdivided into the plurality of through holes8due to the surface tension of the first solder2, voids exceeding 500 μmΦ are hardly generated, and a production yield can be improved.

Moreover, an intermetallic compound is formed between the first solder2and the plating film9. Kirkendall voids arise on this intermetallic compound due to cooling/heating cycles, which, hence, occasionally leads to solder cracks. Accordingly, similarly to Embodiment 1, it is desirable that the intermediate plate6is not exposed from the first solder2.

FIG.5is a cross-sectional view illustrating a semiconductor device according to Embodiment 3. Between the electrode substrate1and the end parts of the semiconductor chip3, a plurality of bumps10are provided by using aluminum wires or the like. Since the bumps can secure the distance between the semiconductor chip3and the electrode substrate1, the semiconductor chip3can be prevented from being implemented to be inclined and the first solder2can be prevented from being partially thin.

Moreover, the intermediate plate6is positioned inward of the plurality of bumps10in planar view. Thereby, movement of the intermediate plate6during the solder bonding step is restricted by the bumps10, and thereby, the intermediate plate6can be prevented from flowing outwardly from the semiconductor chip3and being exposed from the first solder2.

Moreover, a thickness t2of the intermediate plate6is smaller than a height h1of the bumps. Thereby, even if the intermediate plate6is inclined in the first solder2in the melting state during the solder bonding step, the height of the semiconductor chip3can be maintained by the bumps10.

Notably, in Embodiments 1 to 3, when the thickness of the semiconductor chip3is 100 μm or less, although a loss of the semiconductor chip3can be reduced, the semiconductor chip3tends to be deformed to meet deformation of peripheral components. Therefore, there is high necessity to provide the intermediate plate6to prevent deterioration of reliability.

Moreover, the main material of the intermediate plate6may be molybdenum. In this case, the intermediate plate6is formed, for example, by rolling a molybdenum material to form a molybdenum plate material, and after that, processing it into an arbitrary shape by punching processing. Since by using molybdenum, the coefficient of linear expansion of the intermediate plate6is brought to be close to that of silicon, which is the main material of the semiconductor chip3, stress generated due to the difference in coefficient of thermal expansion between both can be reduced. Accordingly, since stress exerted on the semiconductor chip3due to thermal cycles or power cycles can be further relieved, reliability can be further improved while electric and thermal conductivity being maintained.

Moreover, by using a compound semiconductor for the semiconductor chip3, it can be used at or below a high temperature. In particular, by using a compound semiconductor, such as SiC having carbon, as the main material, it can be used at or below a further higher temperature. The semiconductor chip3formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor chip3enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip3is incorporated. Further, since the semiconductor chip3has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor device. Further, since the semiconductor chip3has a low power loss and a high efficiency, a highly efficient semiconductor device can be achieved. The wide-bandgap semiconductor is, for example, a gallium-nitride-based material, or diamond besides a silicon carbide.

REFERENCE SIGNS LIST