System, drivers for switches and methods for synchronizing measurements of analog-to-digital converters

A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

TECHNICAL FIELD

The invention relates to a system, drivers for switches and methods for synchronizing measurements of analog-to-digital converters (ADCs), in particular, in safety-critical power systems with power switches.

BACKGROUND

Safety engineering is a growing field in which engineers use redundancy techniques in order to mitigate adverse consequences if an error occurs. For example, space vehicles and aircrafts include redundant systems so that if an engine control component fails during flight, for example, another engine control component can be activated to allow the aircraft to land safely.

In a similar regard, timed input/output (I/O) signals in safety conscious systems can be generated and then subsequently checked to ensure they were actually delivered correctly. This can be useful in any number of applications. For example, in an automotive system, if an output drive signal (e.g., sparkplug signal from an engine controller) is provided to an automobile's engine, a feedback signal (which is derived from the output drive signal that was actually delivered to the engine) can be compared with the original output drive signal to determine whether the output drive signal was, in fact, delivered correctly. Thus, if there is a “bad” connection between the engine controller and the engine itself (or if some other error event occurs), a comparison of the original drive signal and the feedback signal can detect this error, thereby allowing a control system to notify the driver, for example, by illuminating a “check engine” light on the driver's dashboard. In this way, a driver can be informed that an engine problem (e.g., a sparkplug misfire) has occurred, and can then get the vehicle serviced to remedy any corresponding problems.

In safety-critical power systems with power switches (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs)) there is the need to analyze functional blocks in the power system before starting the operation of the system to avoid damages in case of a malfunction of some functional blocks. Furthermore, diagnosis capability is needed during runtime to detect aging effects or analyze sudden failures.

A standard output of a normal control device is not capable of driving directly the control input (gate) of a power switch. Therefore, a gate driver component with its own power supply is needed to amplify the control signals and to adapt them to the needs of power switches. To avoid losses and to ensure a correct switching behavior, the gate driver components are normally located near to the power switch.

In some cases, the gate driver component introduces a galvanic isolation barrier between the control device and the power switch since they do not refer to the same potential. Here, the gate driver comprises a “low-voltage” primary side which is connected to the “low-power” control device and a “high-voltage” secondary side connected to the power switch, wherein the primary side and the secondary side are separated by a galvanic isolation barrier. As a consequence, the diagnosis capability of the complete system is reduced, since it is rather expensive to handle analog values under these conditions. It is particularly complex and costly to implement pre-warnings or repetitive measurements and transfer of data to the control device in high-voltage devices, for example.

More sophisticated diagnostics may utilize an analog-to-digital converter (ADC) which is integrated in the secondary side of the gate driver. Due to switching behavior and commutation noise (current changes of several kV/μs may occur at a phased node), noise effects can disturb ADC measurements.

Therefore, there, e.g., exists a need for a method and system for controlling ADC measurements in gate drivers for power switches which reduces impairment of the ADC measurements by noise effects.

SUMMARY OF THE INVENTION

In accordance with an aspect of the invention, there is provided a driver for a switch, the driver comprising a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit, and the ADC is configured to start a measurement upon receiving the trigger signal.

In accordance with a further aspect of the invention, there is provided a method for synchronizing a measurement of an analog-to-digital converter (ADC) in a driver comprising a primary side having a trigger input and a secondary side comprising the ADC. The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The method comprises receiving a trigger signal at the trigger input of the primary side of the driver and forwarding the trigger signal to the ADC of the secondary side of the driver via the communication circuit to cause the ADC to start a measurement.

Further features, aspects and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1exemplarily shows a simplified schematic diagram of a system according to an embodiment of the invention. The system comprises a primary side20and a secondary side30which are separated by a galvanic isolation barrier40, as the primary side20and the secondary side30refer to different potentials. Communication between the primary side20and the secondary side30may be performed via suitable communication means or circuit (not shown inFIG. 1).

The primary side20comprises a pulse width modulation (PWM) signal input11, a data input12, an ADC trigger input13, a first transmitter channel21, a second transmitter channel22, a first multiplexer24, and a transmission control unit25. The first transmitter channel21has its input connected to the PWM signal input11, the second transmitter channel22has its input connected to the output of the first multiplexer24. The multiplexer has its first input connected to a register27, its second input connected to the data input12and its control input connected to the output of the transmission control unit25. The transmission control unit25has its input connected to the ADC trigger input13.

The secondary side30comprises a first receiver channel31, a second receiver channel32, a first edge detector33a, a second edge detector33b, a second multiplexer34, a third multiplexer35, a control unit36, a configurable delay element37, an ADC39, e.g., a successive approximation ADC, an output stage51, and an output61.

The first receiver channel31has its input connected to the first transmitter channel21via a communication circuit (not shown inFIG. 1). The second receiver channel32has its input connected to the second transmitter channel22via the communication circuit or a further communication circuit (not shown inFIG. 1).

The first transmitter channel21and the second transmitter channel22are configured to transmit data over a galvanic isolation barrier (e.g., from the primary side20to the secondary side30). The first receiver channel31and the second receiver channel32are configured to receive data over a galvanic isolation barrier (e.g., from the primary side20). Depending on the bandwidth of the communication circuit, one or more transmitter/receiver channels may use the same communication circuit or each transmitter/receiver channel may use a separate communication circuit. The communication circuit may comprise inductive couplers such as coreless transformers, capacitive couplers, or optocouplers.

The first receiver channel31has its output connected to the input of the output stage51and the inputs of the first edge detector33aand the second edge detector33b. The output stage51has its output connected to output61which may be connected to a power switch (not shown inFIG. 1). The first edge detector33ahas its output connected to a first input of the second multiplexer34and the second edge detector33bhas its output connected to a second input of the second multiplexer34.

The second receiver channel32has its first output connected to a third input of the second multiplexer34and a second input of the third multiplexer35and its second output connected to the input of the control unit36. The second multiplexer34has its control input connected to a first output of the control unit36and its output connected to the input of the configurable delay element37. The configurable delay element37has its control input connected to a second output of the control unit36and its output connected to a first input of the third multiplexer35. The third multiplexer35has its control input connected to a third output of the control unit36and its output connected to the control input of the ADC39.

The first transmitter channel21receives PWM control signals for controlling switching of an associated switch (not shown inFIG. 1) and transmits the PWM control signals via a communication circuit to the first receiver channel31. The first receiver channel31forwards the PWM signal to the output stage51which amplifies the PWM signal and outputs the amplified PWM signal via output61to an associated switch to control the switching state of the switch. The first receiver channel31forwards the PWM signal also to the first and second edge detectors33a,33bwhich will be described below.

The first multiplexer24receives a signal comprising a direct request for an ADC measurement from a register27containing a codeword for the ADC conversion request at its first input and receives configuration data signals for the control unit36located in the secondary side30of the system. The transmission control unit25is connected to the ADC trigger input to receive ADC trigger signals. Dependent on receiving or not receiving an ADC trigger signal, the transmission control unit25controls the second transmitter channel22by means of the first multiplexer24. When the transmission control unit25receives an ADC trigger signal from the ADC trigger input13, the transmission control unit25causes the first multiplexer24to forward the signal received at its first input which comprises a request for an ADC measurement to the second transmitter channel22. Otherwise, when the transmission control unit25does not receive an ADC trigger signal from the ADC trigger input13, the transmission control unit25causes the second multiplexer24to forward the configuration data signals received at its second input to the second transmitter channel22.

In devices without configuration capability, the configuration data path (as well as the multiplexer) can be omitted and an activation of the ADC trigger input13directly initiates transmission of the ADC conversion request code from register27.

The second transmitter channel22transmits the received signal(s) to the second receiver channel32via a communication circuit.

Based on the type of signal(s) received, the second receiver channel32forwards the signal(s) to different destinations. The signal comprising a direct request for an ADC measurement is forwarded to the third input of the second multiplexer34and the second input of the third multiplexer35, whereas the configuration data signals are forwarded to the control unit36.

The first edge detector33aand the second edge detector33breceive the PWM control signal from the first receiver channel31. The first edge detector33amay be configured to detect a falling edge in the received signal and output an activation signal to the first input of the second multiplexer34upon detecting a falling edge in the received signal. The second edge detector33bmay be configured to detect a rising edge in the received signal and output an activation signal to the second input of the second multiplexer34upon detecting a rising edge in the received signal.

The control unit36controls the output of the second multiplexer34based on the received configuration data. Accordingly, the second multiplexer34outputs the activation signal of one of the edge detectors33aand33bor the signal comprising a direct request for an ADC measurement received from the second receiver channel32to the configurable delay element37which delays the signal received from the second multiplexer by a certain delay time which is specified by the control unit36based on the received configuration data.

The delayed signal is then output to the first input of the third multiplexer35, which further receives the signal comprising a direct request for an ADC measurement from the second receiver channel32. The control unit36controls the output of the third multiplexer35based on the received configuration data, i.e., the control unit36causes the third multiplexer35to forward either the delayed signal received from the configurable delay element37or the signal comprising a direct request for an ADC measurement to the ADC39.

The ADC39is implemented at the secondary side of the gate driver to measure an analog value related to the secondary ground potential (in most cases the reference potential of the power switch). As the voltage range of the signals of the secondary side generally exceeds the input capability of the ADC, a voltage divider may be included.

The system described above allows to configure a trigger signal for an ADC measurement as required or desired by providing several options:

A) An ADC measurement may be directly triggered by an external trigger signal. In this case, an external trigger signal received at the ADC trigger input13causes transmission of a signal comprising a direct request for an ADC measurement. The first multiplexer24is controlled to forward the signal comprising a direct request for an ADC measurement to the second transmitter channel22which forwards the signal via the second receiver channel32to the third multiplexer35. The third multiplexer35is then controlled to forward the signal which comprises a direct request for an ADC measurement to the ADC39. Optionally, the signal comprising a direct request for an ADC measurement may be delayed by a configurable delay. Here, the second multiplexer34is controlled to forward the signal which comprises a direct request for an ADC measurement to the configurable delay element37and the third multiplexer35is then controlled to forward the delayed signal to the ADC39.

As a further option, the trigger signal may inhibit data transmission of the second transmitter channel22to the second receiver channel32via the communication circuit as long as the trigger signal is active. Then, synchronized to, e.g., the falling edge of the trigger signal, the signal comprising a direct request for an ADC measurement may be transmitted by the second transmitter channel22. With this, it is guaranteed that an ongoing data transmission can be completed before the signal comprising a direct request for an ADC measurement is transmitted an no further data transmission is started.

B) An ADC measurement is synchronized to an edge of the PWM control signal. In this case, the first multiplexer24is controlled to forward the configuration data signal(s) to the second transmitter channel22which transmits the signal(s) via the second receiver channel32to the control unit36. As the transmission of configuration data via the communication circuit may be slow, this transmission takes place before any synchronized measurement of the ADC39is required. When an ADC measurement is to be synchronized to a falling edge of the PWM control signal, the second multiplexer34is controlled to forward the activation signal output by the first edge detector33ato the configurable delay element37and, when an ADC measurement is to be synchronized to a rising edge of the PWM control signal, the second multiplexer34is controlled to forward the activation signal output by the second edge detector33bto the configurable delay element37. The activation signal of the first or second edge detector33a,33bis then delayed by a certain delay time specified by the control unit36based on the configuration data and forwarded to the third multiplexer35which is controlled to forward the delayed activation signal to the ADC39.

Option B as described above also allows to synchronize ADC measurements of the ADC39in a driver for a high-side switch and the ADC in a driver for a low-side switch of a half bridge.FIG. 2shows a simplified schematic diagram of an exemplary half bridge wherein an embodiment of the invention may be implemented. Half bridges can be used for AC motors, wherein a control circuitry for a three phase motor comprises three half bridges, for example.

The exemplary half bridge illustrated inFIG. 2comprises a high-side switch231, a high-side switch driver221for driving the high-side switch231, a low-side switch232, a low-side switch driver222for driving the low-side switch232, and a microcontroller210for controlling the high-side switch driver221and the low-side switch driver222. The drivers221and222respectively comprise a galvanic isolation barrier as the microcontroller210and the switches231and232do not refer to the same potential.

FIG. 3illustrates an exemplary method for synchronizing ADC measurements according to a further embodiment of the invention, which may be utilized in the drivers of the high-side and low-side switches of a half bridge such as the one shown inFIG. 2.

The ADC measurement of the high-side switch driver221may be triggered, after a first delay (delay_HS), by a rising edge of the PWM control signal for the high-side switch driver. The measurement of the low-side switch driver222may be triggered, after a second delay (delay_LS), by a falling edge of the PWM control signal for the low-side switch driver. Given that the delays are suitably specified, the ADC measurements can be started synchronously in the high-side switch driver and the low-side switch driver.

FIG. 3shows the variation over time of the PWM control signals for a high-side switch driver and a low-side switch driver of a half bridge. The PWM control signals must not be high (i.e., “on” which means a closed switch) for both the high-side switch and the low-side switch of the half bridge at any time. Otherwise, the half bridge would be short-circuited.

In order to guarantee that both switches are never closed at the same time, additional “dead times” are introduced in the PWM control signals: When, for example, the PWM control signal for the low-side switch changes from “high” to “low” to open the low-side switch, the PWM control signal of the high side switch remains low for a certain time, the “dead time”, before the PWM control signal changes to “high” to close the high side switch. Then, when the PWM control signal for the high-side changes from “high” to “low” to open the high-side switch, the PWM control signal of the low side switch remains low for the time duration of the “dead time”, before the PWM control signal changes to “high” to close the low side switch. This approach for avoiding short-circuits in a half bridge is also called “brake before make”. Thus, in this example, the dead time may be defined as a time period in which the PWM control signals for both the high-side switch and the low-side switch are low.

This dead time is a known value as the microprocessor which transmits the PWM control signals to the respective drivers also generates the dead time. Thus, the delays required for ADC synchronization can easily be calculated based on the known dead time. In the example according toFIG. 3, the ADC measurements are synchronized, if the first delay, delay_HS, and the second delay, delay_LS, satisfy the following equation:
delay—LS=delay—HS+dead time  (1)

It is to be appreciated that the synchronization of ADC measurements described above is only an example and other ways of synchronizing ADC measurements in a half bridge are also possible. For example, the ADC measurement of the high-side switch driver may be triggered, after a third delay (delay_HS′), by a falling edge of the PWM control signal for the high-side switch driver and the measurement of the low-side switch driver may be triggered, after a fourth delay (delay_LS′), by a rising edge of the PWM control signal for the low-side switch driver. In this case, the ADC measurements are synchronized, if the third delay, delay_HS′, and the fourth delay, delay_LS′, satisfy the following equation:
delay—HS′=delay—LS′+dead time  (1′)

FIG. 4illustrates a further exemplary method for synchronizing ADC measurements in switch drivers according to a further embodiment of the invention. Here, the ADC measurement is synchronized to an edge of a PWM control signal received by the switch driver in a way similar to the ADC synchronization described with reference toFIG. 1as Option B. However, the ADC measurement is not triggered by each edge of the PWM signal which meets the respective condition, but only when an additional external trigger signal is received by the switch driver. More precisely, the external trigger signal requests an ADC measurement which is synchronized to the next edge of the PWM control signal which meets the respective condition (e.g., either a falling edge or a rising edge).

In this approach, more time passes between the individual ADC measurements which ensures that a microcontroller which reads out the data from the ADC between subsequent separate measurements obtains compatible measurement data, i.e., measurement data of only one single ADC measurement. Accordingly, this approach prevents the microprocessor from reading a portion of a first ADC measurement and then, as a new measurement has already been carried out by the ADC, a portion of a second, subsequent ADC measurement instead one a whole data set of one single ADC measurement.

Furthermore, in numerous applications, ADC data is not always required at a high frequency. This embodiment allows to configure the time intervals lying between ADC measurements carried out periodically thereby avoiding generation of large amounts of data which is not required.