Programmable power reduction in a clock-distribution circuit

A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

BACKGROUND OF THE INVENTION 
Field of the Invention 
The invention relates to programmable integrated circuits (ICs). More 
particularly, the invention relates to a method and apparatus for 
programmably reducing power dissipation in programmable IC clock 
distribution networks. 
Description of the Background Art 
It is well known that the power dissipation of a CMOS circuit is 
proportional to the frequency of operation. As the clock frequency 
increases, the die becomes hotter, with the temperature increase at any 
level of power dissipation being determined by the thermal characteristics 
of the package. Thus, the maximum speed at which a design can operate may 
be limited not by the speed at which logic paths no longer have time to 
settle, but by the speed at which the package can no longer conduct heat 
away from the die fast enough to maintain a permissible temperature. 
For example, without airflow the minimum package thermal resistance that 
can be achieved is around 10.degree. C. per watt. (In other words, the die 
temperature increases 10.degree. C. above the ambient temperature for each 
watt dissipated.) If the maximum ambient temperature is 50.degree. C., and 
the maximum permitted die temperature is 125.degree. C., the 75.degree.C. 
temperature difference permits a maximum power dissipation of 7.5 watts. 
It is to be expected that power dissipation levels equal to or greater than 
7.5 watts will be commonplace in large high-performance ICs. Thus, 
performance will be limited by power dissipation, and reducing power 
dissipation is of value since it will permit an IC to be operated at a 
higher frequency. 
In particular, clock-distribution power is a concern in the design of ICs, 
accounting for as much as 25% of the total power dissipation. 
M. Afghahi and J. Yuan, in "Double Edge-Triggered D-Flip-Flops for 
High-Speed CMOS Circuits", IEEE Journal of Solid-State Circuits, pages 
1168-1170, Vol. 26, No. 8, August 1991, which is incorporated herein by 
reference, suggest reducing the power dissipation of a clock distribution 
circuit by using flip-flops triggered on both edges of the clock pulses 
instead of on only one edge, while distributing a clock at half frequency 
to achieve the same data rate. Afghahi and Yuan propose two circuits for 
such a double-edge triggered flip-flop. 
Additional circuits for double-edge flip-flops are disclosed by Stephen H. 
Unger in "Double-Edge-Triggered Flip-Flops," IEEE Transactions on 
Computers, Vol. C-30, No. 6, pages 447-451, June 1981; and by Shih-Lien Lu 
and Milos Ercegovac in "A Novel CMOS Implementation of 
Double-Edge-Triggered Flip-Flops", IEEE Journal of Solid-State Circuits, 
Vol. 25, No. 4, August 1990, pages 1008-1010; both of which are 
incorporated herein by reference. 
SUMMARY OF THE INVENTION 
The invention provides a clock distribution circuit and method for 
programmable ICs whereby the incoming clock frequency is optionally 
divided by two and distributed at the new, lower frequency. (The term 
"programmable ICs" as used herein includes but is not limited to FPGAs, 
mask programmable devices such as Application Specific ICs (ASICs), 
Programmable Logic Devices (PLDs), and devices in which only a portion of 
the logic is programmable.) Programmable dual-edge flip-flops are provided 
that optionally operate at twice the frequency of the distributed clock, 
being responsive to both rising and falling edges of the distributed 
clock. 
When the clock divider is disabled and the flip-flops are programmed as 
single-edge, the operating frequency is the same as the frequency of the 
incoming clock. When the clock divider is enabled and the flip-flops are 
programmed as dual-edge, the operating frequency is also the same as the 
frequency of the incoming clock; however, the frequency of the distributed 
clock is reduced by one-half. This reduction halves the frequency at which 
the clock distribution circuits operate, and consequently approximately 
halves the power dissipated by the clock distribution circuits. Therefore, 
in a programmable IC wherein the clock distribution circuits dissipate 25% 
of the total power, the method of the invention reduces the total power 
dissipation of the IC by about 12.5%. As a result, the speed at which the 
device can operate with the same maximum die temperature increases by 
12.5%. Therefore, this capability provides a programmable power-saving 
mode for the programmable IC. 
In Field Programmable Gate Arrays (FPGAs) or other programmable ICs, users 
design their own circuits to be placed in the programmable ICs. Some of 
these user circuits may require the use of both edges of the incoming 
clock. One such circuit is described by New in U.S. Pat. No. 4,621,341, 
"Method and Apparatus for Transferring Data in Parallel From a Smaller to 
a Larger Register". Other examples include input/output (I/O) circuitry, 
which sometimes clocks in data on one edge of the clock and clocks out 
data on the other edge, to increase I/O bandwidth; and state machines 
generating signal pulses narrower than a full clock period, such as a RAM 
write enable pulse one-half clock period in length. In such cases, the 
clock cannot easily be divided down. In user circuits not requiring both 
edges of the incoming clock, the power-saving mode can be utilized. 
Another application for the invention is the capability of mixing 
single-edge and double-edge flip-flops in a single design for a 
programmable IC. Prior to the invention, such circuits were typically 
implemented using a clock enable signal that deactivated a single-edge 
flip-flop every other clock cycle. This application can now be implemented 
more simply by distributing only the half-frequency clock, and programming 
each flip-flop to function at the appropriate frequency. Therefore, the 
invention supplies a useful function that can be adapted to the needs of 
the programmable IC user.

DETAILED DESCRIPTION OF THE DRAWINGS 
A programmable clock distribution circuit according to the invention is 
described. In the following description, numerous specific details are set 
forth in order to provide a more thorough understanding of the present 
invention. However, it will be apparent to one skilled in the art that the 
present invention may be practiced without these specific details. In 
other instances, well-known features have not been described in detail in 
order to avoid obscuring the present invention. 
FIG. 1 shows a clock distribution circuit for an FPGA according to a first 
embodiment of the invention. The clock distribution circuit of FIG. 1 
comprises a programmable clock divider 101, a clock distribution network 
106, and a programmably double-edge flip-flop 107, which is one of a 
plurality of such flip-flops. Incoming clock CK1 enters programmable clock 
divider 101. In programmable clock divider 101, clock CK1 drives both one 
input of multiplexer 104 and the clock input of single-edge flip-flop 103. 
The output of flip-flop 103 feeds back through inverter 102 to the data 
input D of flip-flop 103, thereby forming a clock divider that divides the 
clock frequency by two. The output of flip-flop 103 also drives one input 
of multiplexer 104. Configurable memory cell 105 selects one or the other 
input of multiplexer 104, generating an output CK2 with either the same 
frequency as clock CK1 (when multiplexer 104 selects CK1) or one-half of 
that frequency (when multiplexer 104 selects the output of flip-flop 103). 
Clock CK2 is distributed on clock distribution network 106 to a plurality 
of programmable flip-flops, one of which is programmable flip-flop 107, 
controlled by configuration memory cell 108. The bit stored in 
configuration memory cell 108 selects either single-edge or double-edge 
functionality for programmable flip-flop 107. In other embodiments, more 
than one flip-flop can be controlled by memory cell 108, or memory cells 
105, 108 can be replaced by a single memory cell. 
Programmable flip-flop 107 can be implemented in many different ways. One 
such programmable flip-flop is shown in FIG. 2, comprising two 
edge-detectors 201, 202 programmably driving a single-edge flip-flop 207. 
Clock CK2 drives three destinations: programmable multiplexer 205, rising 
edge detector 201, and falling edge detector 202. Rising edge detector 201 
generates a pulse whenever a rising edge on clock CK2 is detected. Falling 
edge detector 202 generates a pulse whenever a falling edge on clock CK2 
is detected. (Edge detectors are notoriously well-known in the art and 
therefore are not described herein.) Rising and falling edge detectors 
201, 202 both drive OR-gate 203; therefore either a rising edge or a 
falling edge on clock CK2 generates a high pulse on the output 204 of 
OR-gate 203. Multiplexer 205 has two inputs, output 204 of OR-gate 203, 
and clock CK2, one of which is selected by configuration memory cell 108. 
Therefore, configuration memory cell 108 uses multiplexer 205 to select 
between a single-edge path (from clock CK2) and a double-edge path 
(through OR-gate 203). The output 206 of multiplexer 205 is used to clock 
single-edge flip-flop 207 and create programmable flip-flop output QOUT. 
Another programmable flip-flop that can be used to implement flip-flop 107 
of FIG. 1 is shown and described by Trevor J. Bauer, Stephen M. 
Trimberger, and Steven P. Young in 08/890,951 U.S. Pat. No. 5,844,844 
entitled "FPGA Memory Element Programmably Triggered on Both Clock Edges", 
now issued U.S. Pat. No. 5,844,844, which is referenced above and 
incorporated herein by reference. The programmable flip-flop of FIG. 3 
comprises two latches, one transparent low latch 302 and one transparent 
high latch 301. One or the other of these latches, each time the clock 
changes state, latches in a new value. When configured as a dual-edge 
flip-flop, the output of the inactive latch is fed forward to drive the 
output QOUT of the dual-edge flip-flop. When configured as a single-edge 
flip-flop, the output of transparent low latch 302 is fed forward to a 
third latch 310 (which is transparent high), forming a rising edge 
flip-flop. The circuit of FIG. 3 is shown in Bauer et al's FIG. 4, and 
described in detail by Bauer et al. 
The embodiments described herein will suggest to one of ordinary skill in 
the FPGA design art the steps of adapting dual-edge triggered flip-flops 
or memory elements (currently known or unknown) to be programmably 
dual-edge or single-edge, and substituting such adapted flip-flops into 
the present invention. Dual-edge flip-flops that could be used in such a 
manner include those of Afghahi and Yuan, Lu and Ercegovac, Unger, and 
Bauer et al. 
It has been demonstrated that the programmable clock distribution circuit 
of the present invention offers significant reduction of power 
dissipation. Further, for programmable IC users little or no modification 
to their designs would be required if a programmable IC were adapted to 
use the optional power-saving mode, provided that the double-edge 
flip-flop used in a given implementation has the same inputs and outputs 
as the flip-flops in the programmable IC without said mode. 
Those having skill in the relevant arts of the invention will now perceive 
various modifications and additions which may be made as a result of the 
disclosure herein of preferred embodiments. Accordingly, all such 
modifications and additions are deemed to be within the scope of the 
invention, which is to be limited only by the appended claims and their 
equivalents.