Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same

An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

The present invention relates to semiconductor integrated circuits and, more specifically, integrated circuits manufactured on a SOI (Silicon on Insulator) substrate.

In SOI technology, a thin layer of silicon (typically featuring a thickness of a few nanometers) is separated from a semiconductor substrate by a relatively thick electrically insulating layer (typically featuring a thickness of a few tens of nanometers).

Integrated circuits in SOI technology offer a number of advantages compared to traditional “bulk” technology for CMOS (Complementary Metal Oxide Semiconductor) integrated circuits. SOI integrated circuits typically provide a lower power consumption for a same performance level. Such circuits also feature a reduced stray capacitance, allowing an increase of commutation speeds. Furthermore, the latch-up phenomena encountered in bulk technology can be mitigated. Such circuits are therefore particularly adapted to SoC (System on Chip) or MEMS (Micro electro-mechanical systems) applications. SOI circuits also are less sensitive to ionizing radiations, making them more reliable than bulk-technology circuits in applications where said radiations may induce operating problems, such as aerospace applications. SOI integrated circuits can include memory components such as SRAM (Static Random Access Memory), or logic gates.

Much research has been conducted on reducing the static power consumption of logic gates, while increasing their commutation speed. Some integrated circuits combine both logic gates with low power consumption, and logic gates with high commutation speed. In order to integrate two such logic gates on a same integrated circuit, it is known to lower the threshold voltage (typically noted VTor Vth) of some transistors belonging to the high-speed logic gates, and to increase the threshold voltage of some other transistors of the low-consumption logic gates. In bulk technology, threshold voltage modulation is implemented by differentiating the doping level of the semiconductor channel of these transistors. However, FDSOI (Fully Depleted Silicon On Insulator) transistors have, by design, a depleted channel, featuring a low doping level (typically 1015cm−3). Due to this low doping level, it is not possible to modulate the threshold voltage of transistors with the method used in bulk technology. Some studies have proposed integrating different gate materials in otherwise identical transistors, in order to obtain differing threshold voltages. However, implementing this solution is technically challenging and economically prohibitive.

In order to obtain different threshold voltages for transistors in FDSOI technology, it is also known to include an electrically biased ground plane (also named back plane, or back gate), located between a thin electrically insulating oxide layer, and the silicon substrate. This technology is often known as UTBOX (for Ultra-Thin Buried OXide layer). By adjusting the type of doping of, and the electrical bias applied to these ground planes, it is therefore possible to define several ranges of threshold voltages for said transistors. For example, it is possible to define low-threshold voltage transistors (LVT for Low Vt, typically between 300 mV and 400 mV), high-threshold voltage transistors (HVT for High Vt, typically above 450 mV preferentially 550 mV) and medium or standard threshold voltage transistors (SVT for Standard Vt, typically 450 mV).

There is a growing need for adjacent cells including transistors having different threshold voltages.FIG. 1illustrates an example of a dual STI integrated circuit9including FDSOI (Fully Depleted Silicon On Insulator) transistors according to the prior art. Such a circuit is designed to allow an independent biasing for the ground planes of the cells and is also designed to provide the highest possible integration density.

The integrated circuit9includes FDSOI transistors1a,1b,1cand1d. Transistors1aand1bform a first cell, whereas transistors1cand1dform a second cell. These transistors are located on an ultra-thin buried oxide (UTBOX) insulator layer4. In order to provide an electrical isolation between transistors:transistor1ais located between an isolation trench22and an isolation trench23;transistor1bis located between an isolation trench23and an isolation trench24;transistor1cis located between an isolation trench24and an isolation trench25;transistor1dis located between an isolation trench25and an isolation trench26.

A semiconductor well93lies below the UTBOX layer4, under the transistors1aand1b. A semiconductor well94lies below the UTBOX layer4, under the transistors1cand1d. The semiconductor wells93and94have a p-type doping. A ground plane31(also named back gate or back gate) lies beneath transistor1b. The upper surface of ground plane31is contacting the UTBOX layer4while its lower surface contacts the well93. The upper part of well93constitutes a ground plane under transistor1a. A ground plane32lies beneath transistor1c. The upper surface of ground plane32is contacting the UTBOX layer4while its lower surface contacts the well94. The upper part of well94constitutes a ground plane under transistor1d. Ground planes31and32have an n-type doping. A p-type substrate91is separated from wells93and94by a deep n-well92.

A V1biasing is applied on well93. A V2biasing is applied on well94. A V3biasing is applied on deep n-well92. A V4biasing is applied on substrate91. To avoid additional biasing contacts, the ground plane31is biased through well93and the ground plane32is biased through well94. Thus, short shallow trench isolations22and23are used to guarantee a semiconductor continuity between the V1bias contact, the well93and the ground plane31. Similarly, short shallow trench isolations25and26are used to guarantee a semiconductor continuity between the V2bias contact, the well94and the ground plane32. These short shallow trench isolations do not reach the bottom of wells93and94.

With different V1and V2bias voltages, to avoid a leakage current between wells93and94, a deep isolation trench24is located between transistors1band1cand between wells93and94. This deep isolation trench reaches the bottom of wells93and94. The deep trench24protrudes inside the deep n-well92. Deep isolation trenches21,27and28extending to the same depth as trench24are also provided.

Due to the use of two different depths for the isolation trenches, such an integrated circuit is commonly named dual STI. Wells93and94can be biased independently and good integration density can be obtained.

However, such an integrated circuit suffers from a major drawback. During the manufacturing process of the integrated circuit9, wells93and94are commonly created by ionic implantation inside the deep n-well92. Ground planes31and32are then created by ionic implantation inside wells93and94respectively. Due to the good control of the ionic implantation process, the interface between a ground plane and its well is very accurate. After the ionic implantation, the integrated circuit undergoes an annealing process, which improves the quality of the interface between a ground plane and its well. Such an accurate interface provides several advantages. However, such an interface induces a capacitive coupling between the ground plane and its well.

A corresponding equivalent electric circuit is illustrated atFIG. 2. The ground plane has a voltage Vbg. A capacitance is created by the UTBOX layer4(Vac voltage) between the ground plane and the transistor located above. The diode formed by the ground plane and the well (at voltage V1) induces a parasitic capacitance as disclosed previously. In practice, this parasitic capacitance induces a delay for the biasing of the ground plane by the well. This delay may reach approximately one second, which is far too much for transistors having switching frequencies higher than several hundreds of MHz.

Thus, there is a need for an integrated circuit having an optimal integration density, providing a reduced biasing delay between wells and ground planes, and having a minimum incidence on the manufacturing process.

The invention relates to an integrated circuit, including:a first cell, comprising:first and second FDSOI field effect transistors;a UTBOX type insulator layer lying beneath said first and second transistors;a first semiconductor well lying beneath the insulator layer and beneath said first and second transistors, said first semiconductor well having a first type of doping;a first semiconductor ground plane having a second type of doping different from the first type, said first semiconductor ground plane being located beneath said first transistor and between the insulator layer and the first semiconductor well;a first shallow trench isolation separating said first and second transistors and crossing said insulator layer without reaching the bottom of the first well;a first conductive element forming an electrical connection between the first well and the first ground plane, said first conductive element being located under said first shallow trench isolation;a second cell including a second semiconductor well;a second shallow trench isolation separating said first and second cells, crossing said insulator layer and reaching the bottom of said first and second wells.

In another embodiment, the integrated circuit further comprises a biasing circuit programmed to apply simultaneously different biasing voltages on said first and second semiconductor wells.

In another embodiment, said first ground plane is deprived of any biasing contact crossing the insulator layer above said first ground plane.

In another embodiment, the circuit further comprises:a semiconductor substrate located under said first and second wells and having the first type of doping;a semiconductor deep well separating the substrate from the first and second wells and having the second type of doping.

In another embodiment, said first and second shallow trench isolations comprise a layer of nitride on at least one of their sidewalls.

In another embodiment, a portion of the conductive element is located beneath one of said nitride layers.

In another embodiment, the conductive element includes one of the following impurity materials with a density at least ten times higher than the density of this impurity material in the first ground plane or in the first well: Ar, N, C, Se, S, Al, Cu, Ag, Ni, Pt, Co, Ti, W or Au.

In another embodiment, the integrated circuit further comprises a second conductive element forming an electrical connection between the first well and the first ground plane, and wherein the second shallow trench isolation comprises:an upper portion overlapping at least one part of the second conductive element;a lower portion extending deeper than said second conductive element.

In another embodiment, said first conductive element has a thickness comprised between 5 and 50 nm.

The invention also relates to a method for manufacturing an integrated circuit, comprising the steps of:providing a stack including a semiconductor substrate, a UTBOX type insulator layer lying above said semiconductor substrate and a semiconductor layer lying above said insulator layer;forming a first groove in said stack, the first groove reaching the semiconductor substrate;forming a second groove in said stack, the second groove extending in the semiconductor substrate beyond said first groove;forming a conductive element at the bottom of first groove;filling said first and second grooves with insulation material to form first and second shallow trench isolations respectively;doping a portion of the semiconductor substrate to form first and second wells on opposite sides of said second shallow trench isolation, said first and second wells having a first type of doping, said first well contacting said conductive element and extending on opposite sides of said first shallow trench isolation and extending deeper than the bottom of the first shallow trench isolation, and said second shallow trench isolation extending deeper than the bottom of the formed first and second wells;doping an upper portion of said first well between said first and second shallow trench isolations to form a ground plane under said insulator layer, the formed ground plane contacting the conductive element and having a second type of doping different from the first type.

In another embodiment, said step of forming a conductive element includes a step of ionic implantation in the bottom of the first groove.

In another embodiment, said ionic implantation includes the implantation of one of the following impurity materials: Ar, N, C, Se, S, As, In, Ge.

In another embodiment, said step of forming a conductive element includes a step of depositing metal at the bottom of the first groove and a step of reacting the metal deposit to form a metal silicide at the bottom of the first groove.

In another embodiment, the method further comprises a step of forming a layer of nitride on at least one sidewall of said first and second grooves.

In another embodiment, the method further comprises the steps of forming first and second FDSOI field effect transistors separated by said first shallow trench isolation, the respective source, drain and channel of each of these transistors being formed in said semiconductor layer.

According to the invention, a conductive path is created between a ground plane and its well, in an integrated circuit including FDSOI transistors and of Dual-STI type. Thus, an electric circuit such as illustrated atFIG. 4can be obtained. The conductive path between the ground plane and its well is illustrated by resistance Rbpw. The biasing delay between a ground plane and its well is thus significantly reduced.

FIG. 3is a schematic cross-section view of a portion of an integrated circuit9according to an embodiment of the invention. The integrated circuit9includes FDSOI transistors1cand1d(either of the nMOS or pMOS types). The transistors1cand1dinclude respective gate stacks and respective active semiconductor layers (typically a silicon layer). Each active semiconductor layer includes a source, a channel and a drain. A gate oxide layer covers the channel. Said gate oxide layer is covered by a gate stack comprising metal layers and polysilicon layers. These stacks are usually laterally delimited by spacers.

The source and drain of the active semiconductor layer are doped with impurities. As known in FDSOI technology, the channel has a very low doping level so as to be in a depleted state. For example, the doping concentration of the channel is lower than 1016cm−3.

The transistors1cand1dare located on an ultra-thin buried oxide (UTBOX) insulator layer4. The oxide layer4lies below the active semiconductor layer of the transistors1cand1dand provides an electrical insulation between this semiconductor layer and a silicon substrate91. The substrate91has typically a p-type doping with a doping level lower than 1016cm−3and, preferentially, lower than 5*1016cm−3. In the so-called UTBOX technology, the oxide layer4has a reduced thickness. For example, the thickness of the oxide layer4is comprised between 10 nm and 100 nm and, preferably, comprised between 10 nm and 50 nm. With a UTBOX layer, it is possible to adjust the threshold voltages of the transistors by using appropriate ground planes.

A semiconductor well94lies below the UTBOX layer4, under the transistors1cand1d. The semiconductor well94has a p-type doping. A ground plane32lies beneath transistor1c. The well94has preferentially a doping level comprised between 1016and 1019cm−3. The well94may extend to a depth of up to 150 nm or 350 nm below the UTBOX layer4.

The upper surface of ground plane32is contacting the UTBOX layer4while its lower surface contacts the well94. The upper part of well94constitutes a ground plane under transistor1d. The upper part of well94(corresponding to the ground plane) has preferentially a doping level comprised between 1018and 5*1018cm−3. The lower part of well94has preferentially a doping level comprised between 5*1016and 5*1017. Ground plane32has an n-type doping. The p-type substrate91is separated from well94by a deep well92of the n-type.

A V2biasing is applied on well94. A V3biasing is applied on deep n-well92. A V4biasing is applied on substrate91. To avoid additional biasing contacts and obtain an optimal integration density, the ground plane32is biased through well94. Thus, short shallow trench isolations (SSTI)25and26are used to guarantee a semiconductor continuity between the V2bias contact, the well94and the ground plane32. These short shallow trench isolations SSTI25and26do not reach the bottom of well94. The ground plane32extends underneath the SSTIs25and26. Direct contact biasing contacts for ground plane32are thus not necessary, which allows a higher density of integration.

To provide an electrical isolation for transistors1cand1d:transistor1cis located between an isolation trench24and an isolation trench25;transistor1dis located between an isolation trench25and an isolation trench26.

The portion of the integrated circuit9illustrated atFIG. 3only shows one cell. Such a circuit is designed to allow an independent biasing for the ground planes of adjacent cells not illustrated therein. The integrated circuit9thus includes deeper shallow trench isolations24and27located at the periphery of the illustrated cell.

A conductive pad33is located at an interface between the ground plane32and the well94. The conductive pad33is located under the isolation trench25. The conductive pad33contacts both the ground plane32and the well94. The conductive pad33provides a much higher electrical conductivity or generation/recombination current than the direct interface between the ground plane32and the well94. Due to the conductive pad33, a direct conduction path is created between the ground plane32and the well94. Thereby, the biasing delay of the ground plane32with respect to the well94is significantly reduced. As detailed afterwards, this improvement can be obtained without requesting major changes in the manufacturing process. This improvement is notably obtained without altering the properties of the channel of the FDSOI transistors.

Examples of manufacturing methods will now be disclosed. AtFIG. 5, a p-type substrate91is provided. Substrate91is covered by a UTBOX layer4. The UTBOX layer has typically a thickness between 10 and 50 nm. The UTBOX layer4is for instance a silicon oxide layer. The UTBOX layer4is covered by a semiconductor layer11(Typically a silicon layer having a thickness between 5 and 15 nm). Semiconductor layer11is typically covered by a pad oxide95(typically silicon oxide with a thickness between 3 and 15 nm) and a pad nitride96(typically silicon nitride with a thickness between 50 and 250 nm). The manufacturing method of this stack of layers is known per se from the prior art. Pad oxide95and pad nitride96may be replaced by one or more layers made out of different materials.

AtFIG. 6, grooves81a,81band81care formed through pad nitride96, pad oxide95, semiconductor layer11and UTBOX layer4. The formed grooves81a,81band81care deep enough to reach the substrate91. These grooves can be formed by an active area photolithography process, including patterning and etching steps. According to this example, grooves81a,81band81care advantageously formed simultaneously and have the same depth after this step.

In an example illustrated atFIG. 7, spacers98are formed on the sidewalls of the grooves81a,81band81c. These spacers98may be formed out of silicon nitride. These spacers98protect the edges of UTBOX layer4and semiconductor layer11for the next steps of the process. In another example illustrated atFIG. 8, no spacers are formed on the sidewalls of the grooves81a,81band81c.

Conductive elements33are then created at the bottom of grooves81a,81band81c, in the substrate91. Conductive elements33are made for instance by creating defect zones. Defect zones are created by inserting impurities into a silicon structure, whose implantation into the silicon structure cannot be healed by annealing. Thus, conductive elements33remain even after later steps of well and ground plane creation for instance.

According to the defect zone manufacturing process chosen, defect zones97are also created on the upper surface of pad nitride96. The semiconductor layer11is protected by pad nitride96and pad oxide95. Thus, whatever the process used to create defect zones for the conductive elements33, this process does not introduce impurities in the semiconductor layer11or the UTBOX layer4. Thus, channels of the FDSOI transistors to be formed will not be altered.

The conductive elements33will advantageously have a thickness comprised between 5 and 50 nm. The conductive elements33will preferentially extend up to the lower interface between the ground plane32and the well94in order to have a large defective surface located at the junction.

Amongst the possible methods for creating conductive elements33as defect zones, the following methods may be used:ionic implantation;plasma doping;metallic deposit.

Conformal doping or non-conformal doping methods may be used.

For ionic implantation and plasma doping, either inert species (like Ar, N or C) or defective species (like Se, As, In, Ge or S) can be used to create defect zones at the bottom of grooves81a,81band81c. For ionic implantation and plasma doping, the conductive element33is a semi-conductor from a chemical point of view but it behaves like a conductive element.

For ionic implantation, the following energy levels can be used: between 1 and 20 keV, preferentially from 1 to 5 keV for As. Typically, the implantation energy will be adapted to locate the peak of the implanted species at the interface between the ground plane and the well. This energy will vary depending on the molecular weight and can be determined for instance by using software distributed under the name TRIM by Mr Ziegler. The doping levels in the conductive elements33are preferentially comprised between 1013at·cm−2and 1016at·cm−2preferentially between 5*1014at·cm−2and 5*1015at·cm−2. In case ionic implantation is used to create the conductive elements33, pad nitride96is used as a shield and the upper surface of pad nitride96undergoes a ionic implantation forming defect zones97therein. Thus, the conductive elements33may be created with a wide range of doping density or implantation energy without altering UTBOX layer4or semiconductor layer11.

Metal deposits may be used to create the conductive zones by a salicidation process. Metal deposits of Ni, Pt, Co, Ag, Al, Cu, Ti, W or Au may be deposited for instance preferentially Ni or Pt or an alloy made out of Ni and Pt for its compatibility with a CMOS process. W is interesting because of its tolerance to high temperature annealing. After a metal deposit, a salicide zone may be created by at least an annealing step and an etching step. These steps may be repeated. A metal salicide is eventually formed to provide a conductive element33at the bottom of grooves81a,81band81c. The creation of a metal salicide in a semiconductor layer is known per se by someone ordinary skilled in the art.

Since the conductive elements33are created at an early stage, before the shallow trench isolations are formed, the UTBOX layer4and the semiconductor layer11are protected by upper layers. In the embodiment illustrated, layers4and11are protected by pad nitride96and pad oxide95, whatever the method chosen for creating the conductive elements33.

AtFIG. 9, a mask99is patterned, for instance by photolithography. The mask99defines openings at locations where deeper shallow trench isolations are to be created. Thus, groove81ais only partly filled by mask99, whereas grooves81band81care fully filled by mask99. Advantageously, groove81ais at least partly masked, in order to mask part of a conductive element33with mask99.

AtFIG. 10, an etching step is performed. The median part of groove81ais thereby etched. A deeper groove is thereby created through the conductive element33located at the bottom of groove81a. The deeper groove extends into substrate91. The depth of this deeper groove may reach for instance between 200 and 400 nm in substrate91. AtFIG. 11, the mask99is removed by a process known per se. Grooves81a,81band81care thus emptied.

AtFIG. 12, grooves81a,81band81care filled with an appropriate isolation material. The isolation material may for instance be silicon oxide. A chemical mechanical polishing may be performed. These steps are known per se. Shallow trench isolations24,25and26are obtained: a deeper STI24and shallower STIs25and26. The conductive elements33are covered by respective shallow trench isolations.

The deeper STI24provides an upper portion and a lower portion. The upper and lower portions are linked at the level of the corresponding conductive element33. In this embodiment, since mask99covered part of the corresponding conductive element33before the etching of the deeper groove, this covered part of the conductive element33remains beneath the upper portion of STI24.

AtFIG. 13, the pad nitride layer96is removed. The height of the protruding portions of STIs24,25and26may be adjusted.

AtFIG. 14, a deep nWell92is formed in substrate91. P-doped wells93and94are formed above deep nwell92, on respective sides of STI24. Wells93and94do not reach the bottom of STI24and are thereby separated. Well94contacts the conductive elements33located under STI25and under the upper portion of STI24. STI24extends into deep nWell92. N-doped ground plane32is formed under UTBOX layer4, between STIs24and25. Ground plane32is formed between well94and UTBOX layer4. In this embodiment, ground plane32contacts the UTBOX layer4. Ground plane32contacts the conductive elements33located under STI25and under the upper portion of STI24. Thus, these conductive elements33form an electrical connection between ground plane32and well94. Ground plane32, wells93and94and deep nWell92may be formed by an appropriate ionic implantation, with appropriate energy levels, impurity materials and implantation densities.

Due to the conductive elements33contacting both wells94and ground plane32, the biasing delay between ground plane32and well94can be significantly reduced. An electrical behavior such as illustrated atFIG. 4can thus be obtained.

FIG. 16shows an integrated circuit9according to another embodiment, at the same step of the manufacturing process asFIG. 15. In this embodiment, the conductive elements33are extending laterally beyond STIs24,25and26, beneath the UTBOX layer4and the semiconductor layer11. Thus, portions of the conductive elements33remain even in case an etching step is performed on the bottom of grooves81a,81band81c.

In case the lower part of the deeper STI24is almost as wide as the upper part, portions of the conductive element33remain on the sidewalls of groove81aeven after the etching step of the lower part of this groove. Such a configuration can be obtained for instance by an appropriate ionic implantation of the conductive elements33into substrate91.

In the previous embodiments, the short shallow trench isolations25and26have the same width as the deeper STI24. However, the integrated circuit9may be designed with a deeper STI24wider than the short shallow trench isolations25and26, with a deeper STI24having a lithographic width larger than the SSTI. Indeed the etching is self aligned and as a consequence the deeper STI24will actually have the same width as the SSTIs25and26. The defective area will then be located on the side of the deeper STI.