STACKED CAPACITOR, METHOD FOR MAKING THE SAME AND MEMORY DEVICE

A multilayer capacitor, a method for making the multilayer capacitor, and a memory device are disclosed by the present invention. The multilayer capacitor made by the method is connected to a capacitor terminal and includes a multilayer fin structure including horizontal and vertical fin elements. A first conductive layer covers a surface of the multilayer fin structure and thereby has a large surface area. A capacitor dielectric layer covers a surface of the first conductive layer, and a second conductive layer covers the capacitor dielectric layer. In this way, the multilayer capacitor has desirably large capacitance. In addition, in the method, after a layer stack is formed, it is processed into the multilayer fin structure by self-aligned anisotropic and isotropic etch, which do not require the use of any photomask or the deposition of any additional layer, resulting in low manufacturing cost. The memory device includes the multilayer capacitor.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Chinese patent application number 202310206683.5, filed on Mar. 6, 2023, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to the field of semiconductor technology and, in particular, to a stacked capacitor, a method for making the stacked capacitor, and a memory device.

BACKGROUND

Dynamic random-access memory (DRAM) stores electric charge on capacitors and maintains the electric charge on the capacitors at a readable level through periodic refresh operations. The trend toward faster operation requires DRAM capacitors to have higher capacitance.

In order to satisfy the demand for higher capacitance, stacked capacitors or trench capacitors are increasingly used because they can provide a large internal capacitor area and reduce crosstalk between DRAM cells. However, with the increasingly higher level of integration of DRAM devices, DRAM cells are shrinking in both size and area, making it more and more difficult to form trench capacitors with higher aspect ratios. This presents a great challenge to the fabrication of trench capacitors. Compared with trench capacitors, stacked capacitors are less demanding in terms of aspect ratio.

However, existing stacked capacitors still need further improvement in terms of capacitance.

SUMMARY OF THE INVENTION

The present invention provides a method capable for making a stacked capacitor with improved capacitance. Also provided are such a stacked capacitor and a memory device.

In one aspect, the present invention provides a method for making a stacked capacitor, comprising:providing a capacitor terminal formed on a surface of a first interlayer insulating layer;forming a second interlayer insulating layer over the capacitor terminal and the first interlayer insulating layer;forming an opening penetrating through the second interlayer insulating layer, wherein the capacitor terminal is exposed in the opening;forming a layer stack by stacking a first material layer and a second material layer over a surface of the second interlayer insulating layer and over an internal surface of the opening and repeating the stacking at least one time;removing portions of the second material layers and portions of the first material layers by performing a self-aligned anisotropic etch, wherein a remaining layer stack covers a sidewall of the opening and exposes the second interlayer insulating layer and the capacitor terminal;forming a multilayer fin structure connected to the sidewall of the opening by performing an isotropic etch that is used to etch back the first material layers in the layer stack and to expose surfaces of portions of the second material layers, wherein the multilayer fin structure comprises horizontal fin elements and vertical fin elements formed by portions of the second material layers; andforming a first conductive layer, a capacitor dielectric layer and a second conductive layer, wherein the first conductive layer covers a surface of the multilayer fin structure and a surface of the capacitor terminal exposed in the opening, wherein the capacitor dielectric layer covers a surface of the first conductive layer, the second conductive layer covering the capacitor dielectric layer.

In another aspect, the present invention provides a stacked capacitor, comprising:a capacitor terminal formed on a surface of a first interlayer insulating layer;a second interlayer insulating layer formed over the first insulating layer, wherein the second interlayer insulating layer has an opening penetrating therethrough, and wherein the capacitor terminal is exposed in the second interlayer insulating layer;a multilayer fin structure connected to a sidewall of the opening and exposing the capacitor terminal at a bottom of the opening, wherein the multilayer fin structure comprises horizontal fin elements and vertical fin elements;a first conductive layer covering a surface of the multilayer fin structure and a surface of the exposed capacitor terminal;a capacitor dielectric layer covering a surface of the first conductive layer; anda second conductive layer covering the capacitor dielectric layer.

In yet another aspect, the present invention provides a memory device comprising the stacked capacitor.

The stacked capacitor made by the method of the present invention is connected to the capacitor terminal and includes the multilayer fin structure including the horizontal and vertical fin elements. The first conductive layer covers the surface of the multilayer fin structure and thereby has a large surface area. In this way, the stacked capacitor has desirably large capacitance. In addition, in the method, the layer stack is formed by repeatedly depositing the first and second material layers and then processed into the multilayer fin structure by the self-aligned anisotropic and isotropic etch, which do not require the use of any photomask or the deposition of any additional layer, resulting in low manufacturing cost.

In the stacked capacitor and the memory device provided in the present invention, the multilayer fin structure can include multiple horizontal fin elements and multiple vertical fin elements. As a result, the first conductive layer covering the surface of the multilayer fin structure has a large surface area, which helps increase the capacitance of the stacked capacitor to a desired level. Further, the stacked capacitor can be fabricated at low cost.

DETAILED DESCRIPTION

Particular embodiments of the present invention will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the figures are provided in a very simplified form not necessarily drawn to exact scale for the only purpose of facilitating easy and clear description of the embodiments. Additionally, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted or otherwise oriented in (e.g., rotated), the exemplary term “over” can encompass an orientation of “under” and other orientations.

An embodiment of the present invention relates to a method for making a stacked capacitor. The method is described below with reference toFIGS.1to10.

Referring toFIG.1, capacitor terminals are formed on the surface of a first interlayer insulating layer110and a second interlayer insulating layer120is formed over the capacitor terminals and the first interlayer insulating layer110.

The capacitor terminals and the first interlayer insulating layer110are, for example, formed on a semiconductor substrate100. Each capacitor terminal is connected to a circuit such as an electronic component in or on the semiconductor substrate100. The semiconductor substrate100is, for example, a silicon substrate, a germanium (Ge) substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate or the like. As required by the design, dopant ions such as P-type or N-type ions may be injected into the semiconductor substrate100. For example, the semiconductor substrate100may comprise isolation regions and active areas defined by the isolation regions. Source/drain regions may be formed in the active areas. At least one of the source/drain regions may be connected to one of the capacitor terminals.

Referring toFIG.1, the stacked capacitors to be fabricated, for example, are used in a dynamic random-access memory (DRAM) device, and the semiconductor substrate100is, for example, a P-doped silicon substrate (P—Si). The semiconductor substrate100may undergo the following processes. At first, the isolation (e.g., shallow trench isolation (STI)) regions and the active areas are formed in the semiconductor substrate100. A plurality of word lines WL are then formed on the semiconductor substrate100, and some of the word lines WL are located above the active areas and serve as gates of MOS transistors and also some of the word lines WL are located above the isolation regions and serve as passing gates (PGs). A dielectric (e.g., silicon nitride) layer is formed on top surfaces of the word lines WL, and a gate dielectric layer101is formed between the word lines WL and the semiconductor substrate100, and spacers102on sidewalls of the word lines WL and side walls of the gate dielectric layer101. Subsequently, source regions103and drain regions104of the MOS transistors are formed in the active areas on opposite sides of the gates. The source regions103and drain regions104are, for example, heavily dope N-type (N+) regions optionally exposed in self-aligned contact holes delimited by the spacers102. Afterwards, bit lines BL connected to the drain regions104are formed by filling the contact holes in which the drain regions104are exposed. Next, the first interlayer insulating layer110is deposited over the semiconductor substrate100. The first interlayer insulating layer110may include silicon oxide, silicon nitride, silicon oxynitride, nitrogen-doped silicon carbide (NDC) or another dielectric material, or any combination thereof. Thereafter, the first interlayer insulating layer110is etched so that contact holes are formed therein, in which the source regions103are exposed, and upper portions of the contact holes are expanded to define ranges for the capacitor terminals. Following that, a conductive material is filled in the contact holes including the upper portions that define the ranges for the capacitor terminals, followed by a planarization thereby simultaneously forming, in the first interlayer insulating layer110, contact plugs105and conductive plates106located on the contact plugs105. The contact plugs105are connected to the source regions103at one end and to the conductive plates106at the other end. In other embodiments, the contact plugs105and the conductive plates106may not be formed simultaneously. A second interlayer insulating layer120is then deposited over the conductive plates106and the first interlayer insulating layer110. The second interlayer insulating layer120may include silicon oxide, silicon nitride, silicon oxynitride, NDC or another dielectric material, or any combination thereof.

In this embodiment, the conductive plates106connected to the source regions103of the MOS transistors serve as the capacitor terminals.

Referring toFIG.2, openings120apenetrating through the second interlayer insulating layer120are formed, in which the capacitor terminals (here, the conductive plates106) are exposed.

Specifically, a patterned photoresist layer PR1may be first formed on the surface of the second interlayer insulating layer120, which defines locations where the stacked capacitors are to be formed. A first anisotropic etch10may be then performed, with the photoresist layer PR1serving as a mask, to form the openings120ain the second interlayer insulating layer120. After that, the photoresist layer PR1may be removed. In this embodiment, a plurality of conductive plates106may be formed on the semiconductor substrate100serving as capacitor terminals. Correspondingly, the same number of openings120aare formed in the second interlayer insulating layer, each corresponding to a respective one of the conductive plates106. Optionally, each conductive plate106may be at least partially exposed in the respective opening120a, with the first interlayer insulating layer110remaining covered by the second interlayer insulating layer120.

Referring toFIG.3, a first material layer131and a second material layer132are deposited over both the surface of the second interlayer insulating layer120and over internal surfaces of the openings120a. This process is repeated at least one time, resulting in the formation of a layer stack130. The present invention is not limited to any particular total number of the first and second material layers131,132in the layer stack130. For example, tens of or even hundreds of such layers may be included. As an example,FIG.3shows the case of four layers, including two first material layers131and two second material layers132.

A thickness of the first and second material layers131,132are both smaller than a width of the openings120a(measured as the distance between two opposite internal surfaces of each opening120a) so that they can be stacked over the surface of the second interlayer insulating layer120and over the internal surfaces of the openings120a. Each of the first and second material layers131,132may have a thickness in the range of, for example, 2 nm to 20 nm. In this embodiment, the thickness of the layer stack130is smaller than the width of the openings120a. For example, the layer stack130lined on the internal surfaces of the openings120amay appear like a barrel.

The first and second material layers131,132may be selected from suitable insulating or conductive materials. In this embodiment, they are both insulating materials, for example. The first and second material layers131,132are preferred to show a relatively high etch selectivity ratio which enables desired performance of the subsequent self-aligned anisotropic etch. For example, the first material layers131may include silicon oxide. For example, they may be silicon oxide layers. The second material layers132may include silicon nitride. For example, they may be silicon nitride layers. In other embodiments, one of the first and second material layers131,132may be selected as a high dielectric constant (high-k material, with a k value of greater than 3.9) material, such as Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Si3N4, TiO2, etc.

Next, referring toFIGS.4to7, self-aligned anisotropic etches are performed to remove portions of each second material layer132and portions of each first material layer131in the layer stack130. As a result, the portion of the layer stack130remains on sidewalls of the openings120a, and the second interlayer insulating layer120and the conductive plates106are exposed. In this embodiment, the self-aligned anisotropic etch is proceed, for example, along a normal of the semiconductor substrate100. That is, the etch is proceed in a direction substantially perpendicular to the surface of the semiconductor substrate100.

Specifically, referring toFIG.4, first of all, a second anisotropic etch20may be carried out to etch away horizontal portions of the exposed topmost second material layer132in the layer stack130outer side of and within the openings120a. Taking advantage of the selectivity between the second and first material layers132,131, the second anisotropic etch20can be stopped when the horizontal portions of the topmost second material layer132are removed and the underlying first material layer131is exposed. As a result, the remaining portions of the topmost second material layer132extend vertically and cover vertical portions of the underlying first material layer131in a manner of spacer (the remaining portions of the topmost second material layer132are tubular and extend on the vertical portions of the underlying first material layer131). In this way, self-alignment is achieved and the use of a mask is made unnecessary.

Referring toFIG.5, a third anisotropic etch30may be performed to etch the first material layer131exposed as a result of the second anisotropic etch20. This first material layer131is the second topmost layer in the layer stack130. Taking advantage of the selectivity between the first and second material layers131,132, the third anisotropic etch30can be stopped when the exposed horizontal portions of the second-topmost first material layer131are removed and the underlying second material layer132is exposed. As a result, the remaining portions of the second-topmost first material layer131forms a similar structure as the last step and cover vertical portions of the underlying second material layer132.

Referring toFIG.6, a fourth anisotropic etch40may be performed to etch the second material layers132exposed after the completion of the third anisotropic etch30. Here, the process step is repeated as the same as shown inFIG.4. As a result, the exposed two second material layers132and one first material layer131overall extend vertically and cover vertical portions of the bottommost first material layer131.

In this way, the second material layers132and the first material layers131in the layer stack130can be alternant etched by a self-alignment and the use of a mask is made unnecessary. Referring toFIG.7, for example, a fifth anisotropic etch50may be performed to etch the bottommost first material layer131and the other exposed first material layer131in the layer stack130. Thus, by an etching-stop mode, the fifth anisotropic etch50may be stopped when the second interlayer insulating layer120and the conductive plates106in the openings120aare exposed.

In this way, portions of the layer stack130above the second interlayer insulating layer120and within the openings120acan be removed. As a result of the above self-aligned anisotropic etches, the remaining layer stack130covers the sidewalls of the openings120a. In this embodiment, at least portions of the remaining layer stack130extending vertically protrude beyond a top surface of the second interlayer insulating layer120.

Referring toFIG.8, an isotropic etch is carried out to etch back the first material layers131in the layer stack130so that surface of portions of the second material layers132are exposed. As a result, multilayer fin structures FS connected to the sidewalls of the openings120aare formed. Each of the multilayer fin structures FS includes horizontal fin elements132aand vertical fin elements132bformed by portions of the second material layers132in the layer stack130. The isotropic etch is, for example, a wet etch or a chemical dry etch (CDE).

For example, the first material layers131may be silicon oxide layers, and the etch-back process may use a hydrofluoric acid solution. The etch-back process may be conducted under appropriate etch conditions so that the first material layers131are partially removed and the surface previously covered by the removed portions are exposed. As a result of the isotropic etch, a contact area between the first and second material layers131,132is reduced, and portions of the second material layers132not in contact with any first material layer131on both sides form the fin elements. Additionally, some of the fin elements extend parallel to the surface of the semiconductor substrate100and form the horizontal fin elements132a, and the other fin elements extend parallel to the normal of the semiconductor substrate100and form the vertical fin elements132b. The remaining second material layers132is connected to the remaining first material layers131from the etch-back process, and they both are stacked on the sidewalls of the openings120aand constitute the multilayer fin structures FS. The multilayer fin structures FS may protrude beyond the top surface of the second interlayer insulating layer120.

As another result of the isotropic etch, lower portions of the openings120aare expanded, and larger portions of the conductive plates106are exposed. As shown inFIG.8, for example, portions of the layer stack130on the conductive plates106may be completely removed.

Referring toFIGS.9and10, a first conductive layer141, a capacitor dielectric layer142and a second conductive layer143are formed. The first conductive layer141covers surfaces of the multilayer fin structures and surface of portions of the conductive plates106exposed in the openings120a(i.e., the first conductive layer141is connected to the capacitor terminals). The capacitor dielectric layer142covers the first conductive layer141, and the second conductive layer143covers the capacitor dielectric layer142.

Specifically, referring toFIG.9, at first, a first conductive material layer may be deposited on the surfaces of the multilayer fin structures FS, the surface of portions of the conductive plates106exposed in the openings120aand the surface of the second interlayer insulating layer120. The first conductive material layer may include any one of tungsten (W), tungsten silicide (SiW), titanium (Ti), titanium nitride (TiN), doped polysilicon, rugged polysilicon or hemispherical-grained (HSG) polysilicon, or any combination thereof. The first conductive material layer may have a thickness of about 1 nm to 15 nm. In this embodiment, the first conductive material layer is, for example, N-doped polysilicon, rugged polysilicon or hemispherical-grained polysilicon. After that, a patterned photoresist layer PR2may be formed on the first conductive material layer, which defines a range for the first conductive layer141. Subsequently, the first conductive material layer may be etched, with the photoresist layer PR2serving as a mask, so that portions of the second interlayer insulating layer120surrounding the openings120aare exposed. Portions of the first conductive material layer surrounded by the exposed portions of the second interlayer insulating layer120constitute the first conductive layer141. The first conductive layer141surrounding two adjacent openings120aare separate from each other. The photoresist layer PR2is then removed.

Subsequently, the capacitor dielectric layer142may be deposited over surfaces of the first conductive layer141and the exposed portions of the second interlayer insulating layer120. The capacitor dielectric layer142may include any one of silicon oxide, silicon nitride, silicon oxynitride, hafnia (HfO) and arsenic pentoxide (As2O5), or any combination thereof. The capacitor dielectric layer142may have a thickness of about 1 nm to 10 nm.

A second conductive material layer may then be formed, which covers the capacitor dielectric layer142and fills up the openings120a. A top surface of the second conductive material layer may be higher than the multilayer fin structures FS. Subsequently, the top surface of the second conductive material layer may optionally undergo a planarization (e.g., CMP) resulting in the formation of the second conductive layer143. The second conductive layer143may include any one of tungsten, tungsten silicide, titanium, titanium nitride and doped polysilicon, or any combination thereof. In this embodiment, it is N-doped polysilicon, for example.

The above-described multilayer fin structures FS, first conductive layer141, capacitor dielectric layer142and second conductive layer143constitute the stacked capacitors. The second conductive layer143may be commonly shared by the stacked capacitors in the openings120a. In the stacked capacitors, each multilayer fin structure FS may include multiple horizontal fin elements132aand multiple vertical fin elements132b, which enable the first conductive layer141to have a large surface area. Moreover, there are large contact areas both between the first conductive layer141and the capacitor dielectric layer142, and between the capacitor dielectric layer142and the second conductive layer143, which enable the stacked capacitors to have desirably large capacitance. Further, in the method, the layer stack130undergoes self-aligned anisotropic and isotropic etches, which do not require the use of any photomask or the deposition of any additional layer, resulting in low manufacturing cost.

An embodiment of the present invention relates to a stacked capacitor. Referring toFIG.10, the stacked capacitor includes:a capacitor terminal (e.g., the conductive plate106shown inFIG.10) formed on a surface of a first interlayer insulating layer110;a second interlayer insulating layer120formed over the first insulating layer110, the second interlayer insulating layer120provided therein with an opening120a, wherein the capacitor terminal is exposed at the bottom of the opening120a;a multilayer fin structure FS formed on a sidewall of the opening120a, wherein the multilayer fin structure FS includes horizontal fin elements132aand vertical fin elements132b;a first conductive layer141covering a surface of the multilayer fin structure FS and an exposed surface portion of the capacitor terminal;a capacitor dielectric layer142covering a surface of the first conductive layer141; anda second conductive layer143covering a surface of the capacitor dielectric layer142.

The stacked capacitor is formed, and the multilayer fin structure FS may include alternately stacked first and second material layers131,132. The first material layers131are, for example, silicon oxide layers, and the second material layers132are, for example, silicon nitride layers. Portions of the second material layers132not in contact with any first material layer131on both sides form the fin elements. Some of the fin elements extend parallel to a surface of the semiconductor substrate100and form the horizontal fin elements132a, and the other fin elements extend parallel to a normal of the semiconductor substrate100and form the vertical fin elements132b. An upper portion of the multilayer fin structure FS may protrude beyond a top surface of the second interlayer insulating layer120.

An embodiment of the present invention relates to a memory device including a stacked capacitor as described above. The memory device is, for example, a dynamic random-access memory (DRAM) device.

Referring toFIG.10, the memory device may include a semiconductor substrate100and a first interlayer insulating layer110formed over the semiconductor substrate100. The semiconductor substrate100may include isolation (e.g., STI) regions and an active area defined by the isolation regions. The memory device may further include a MOS transistor formed on a surface of the active area. The MOS transistor may include a gate and, formed in the active area on opposite sides of the gate, a source region103and a drain region104. The memory device may further include a contact plug105and a conductive plate106. The contact plug105is formed in the first interlayer insulating layer110and is connected at one end thereof to the source region103. The conductive plate106formed on a surface of the first interlayer insulating layer110is connected to the other end of the contact plug105. In this embodiment, the conductive plate106serves as a capacitor terminal of the stacked capacitor.

In the stacked capacitor and the memory device provided in embodiments of the present invention, the multilayer fin structure FS can include multiple horizontal fin elements132aand multiple vertical fin elements132b, which enable the first conductive layer141to have a large surface area. Moreover, there are large contact areas both between the first conductive layer141and the capacitor dielectric layer142, and between the capacitor dielectric layer142and the second conductive layer143, which help increase the capacitance of the stacked capacitor. Further, the stacked capacitor can be fabricated at low cost.

It is to be noted that the embodiments disclosed herein are described in a progressive manner, with the description of each embodiment focusing on its differences from others. Reference can be made between the embodiments for their identical or similar parts.

The foregoing description is merely that of several preferred embodiments of the present invention and is not intended to limit the scope of the claims of the invention in any way. Any person of skill in the art may make various possible variations and changes to the disclosed embodiments in light of the methodologies and teachings disclosed hereinabove, without departing from the spirit and scope of the invention. Accordingly, any and all such simple variations, equivalent alternatives and modifications made to the foregoing embodiments based on the essence of the present invention without departing from the scope of the embodiments are intended to fall within the scope of protection of the invention.