Amplifier circuit

An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

TECHNICAL FIELD

The invention relates to an amplifier circuit, and specifically, to a multi-gain amplifier circuit having phase control.

BACKGROUND

The increasing use of network devices and mobile devices has driven the need for quality communication, and therefore, amplifiers are often adopted in the network devices and the mobile devices to enhance the signal quality. The amplifiers can utilize various circuit configurations to properly process received signals, thereby enhancing the signal quality. Nevertheless, the various circuit configurations will also affect the phase of the output signal of the amplifiers to various degrees, resulting in variation in the phases of the output signals.

SUMMARY

According to one embodiment of the invention, an amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a first phase adjustment unit comprising a first terminal and a second terminal. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The first terminal of the first phase adjustment unit is coupled to the input terminal of the amplifier circuit, and the second terminal of the first phase adjustment unit is coupled to the input terminal of the amplification unit; or the first terminal of the first phase adjustment unit is coupled to the second terminal of the amplification unit, and the second terminal of the first phase adjustment unit is coupled to the second voltage terminal; or the first terminal of the first phase adjustment unit is coupled to the output terminal of the amplification unit, and the second terminal of the first phase adjustment unit is coupled to the output terminal of the amplifier circuit; or the first terminal of the first phase adjustment unit is coupled to the first voltage terminal, and the second terminal of the first phase adjustment unit is coupled to the first terminal of the amplification unit; or the first terminal of the first phase adjustment unit is coupled to the input terminal of the amplification unit, and the second terminal of the first phase adjustment unit is coupled to the second voltage terminal; or the first terminal of the first phase adjustment unit is coupled to the first terminal of the amplification unit, and the second terminal of the first phase adjustment unit is coupled to the input terminal of the amplification unit; or the first terminal of the first phase adjustment unit is coupled to the input terminal of the amplification unit, and the second terminal of the first phase adjustment unit is coupled to the second terminal of the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

DETAILED DESCRIPTION

FIG.1is a block diagram of an amplifier circuit1according to an embodiment of the invention. The amplifier circuit1includes an input terminal10, an output terminal12, and an amplification unit14. The input terminal10is configured to receive an input signal RFin. The output terminal12is configured to output an output signal RFout. The input signal RFin and the output signal RFout may be radio frequency signals. The amplification unit14includes an input terminal IN, an output terminal OUT, a first terminal T1and a second terminal T2. The input terminal IN of the amplification unit14is coupled to the input terminal10of the amplifier circuit1, the output terminal OUT of the amplification unit14is coupled to the output terminal12of the amplifier circuit1, the first terminal T1of the amplification unit14is coupled to a voltage terminal VDD and the second terminal T2of the amplification unit14is coupled to a voltage terminal GND. In some embodiments, a voltage at the voltage terminal VDD may be higher than a voltage at the voltage terminal GND. For example, the voltage at the voltage terminal VDD may be, but is not limited to, an operating voltage in the system, and the voltage at the voltage terminal GND may be, but is not limited to, a ground voltage in the system. The amplifier circuit1may serve as a power amplifier or a low noise amplifier.

The gain of the amplifier circuit1may be controlled by: 1. changing a supply current Icc consumed by the amplification unit14; 2. configuring a capacitance of a capacitor between the input terminal IN and the second terminal T2of the amplification unit14; and/or 3. changing an impedance of a feedback path between the first terminal T1and the input terminal IN of the amplification unit14.

In some embodiments, the amplifier circuit1may operate in one of a plurality of gain modes, the plurality of gain modes including but not limited to a high gain mode, a low gain mode and a bypass mode. For example, when the amplifier circuit1is operated in the high gain mode, the amplifier circuit1has a high gain, e.g., 20 dB; when the amplifier circuit1is operated in the low gain mode, the amplifier circuit1has an intermediate gain between the high gain and 0 dB, e.g., 10 dB; and when the amplifier circuit1is operated in the bypass mode, the amplifier circuit1has a bypass gain less than 0 dB, e.g., −10 dB.

However, in the high gain mode, the gain is increased by: 1. increasing a transistor size of transistors in the amplification unit14by, for example, increasing the total width of the transistors, thereby increasing the supply current Icc; 2. reducing the capacitance of the capacitor between the input terminal IN and the second terminal T2of the amplification unit14; and/or 3. increasing the overall impedance of the feedback path between the first terminal T1and the input terminal IN of the amplification unit14, thereby decreasing the feedback amount in the feedback path. In one example, the feedback amount may be the power of a feedback signal in the feedback path. When the transistor size of the transistors in the amplification unit14is increased, the supply current Icc will be increased accordingly, increasing the gain and resulting in a lagging phase shift. When the capacitance of the capacitor is reduced, the gain will be increased and resulting in a leading phase shift. When both the increased transistor size and the reduced capacitance of the capacitor are adopted, the phase of the output signal RFout will be determined by a combinational result of the lagging phase shift owing to the increased transistor size and the leading phase shift owing to the reduced capacitance of the capacitor.

Furthermore, in the low gain mode, the gain is reduced by: 1. reducing the transistor size of the transistors in the amplification unit14by, for example, reducing the total width of the transistors, thereby reducing the supply current Icc; 2. increasing the capacitance of the capacitor between the input terminal IN and the second terminal T2of the amplification unit14; and/or 3. reducing the overall impedance of the feedback path between the first terminal T1and the input terminal IN of the amplification unit14, thereby increasing the feedback amount in the feedback path. When the transistor size of the transistors in the amplification unit14is decreased, the supply current Icc will be decreased accordingly, decreasing the gain and resulting in a leading phase shift. When the capacitance of the capacitor is increased, the gain will be decreased and the phase will be delayed, resulting in a lagging phase shift. When both the decreased transistor size and the increased capacitance of the capacitor are adopted, the phase of the output signal RFout will be determined by a combinational result of the leading phase shift owing to the decreased transistor size and the lagging phase shift owing to the increased capacitance of capacitor.

Accordingly, the transistor size and the capacitance of the capacitor are selected to provide the adequate gain levels, and will affect the phases of the output signals RFout in the high gain mode and low gain mode considerably.

Further, in the related art, the bypass mode is implemented by using a switch to enable a bypass path connecting between the input terminal10of the amplifier circuit1and the output terminal12of the amplifier circuit1, thereby passing the input signal RFin from the input terminal10of the amplifier circuit1to the output terminal12of the amplifier circuit1without passing through the amplification unit14. Since the input signal RFin is directed to the output terminal12of the amplifier circuit1without going through the amplification unit14, the transistors in the amplification unit14may be turned off, the phase of the output signal RFout may be substantially equal to the phase of the input signal RFin, and may be very different from the phases of the output signals RFout in the high gain mode and the low gain mode. Therefore, the phases of the output signals RFout in the various gain modes may differ from each other by a great range. When in operation, an electronic system may be required to determine the gains and phases of the amplifier circuit1for calibration. If the phases are different for the various gain modes, the electronic system may need to determine the phase upon each gain mode change, increasing a signal processing time.

One or more members of the first phase adjustment units161to167may be included in the amplifier circuit1to maintain the phases of the output signals RFout substantially unchanged or varying within a small predetermined range in the various gain modes. Each of the first phase adjustment units161to167includes a first terminal and a second terminal. The first terminal of the first phase adjustment unit161is coupled to the input terminal10of the amplifier circuit1, and the second terminal of the first phase adjustment unit161is coupled to the input terminal IN of the amplification unit14. The first terminal of the first phase adjustment unit162is coupled to the second terminal T2of the amplification unit14, and the second terminal of the first phase adjustment unit162is coupled to the voltage terminal GND. The first terminal of the first phase adjustment unit163is coupled to the output terminal OUT of the amplification unit14, and the second terminal of the first phase adjustment unit163is coupled to the output terminal12of the amplifier circuit1. The first terminal of the first phase adjustment unit164is coupled to the voltage terminal VDD, and the second terminal of the first phase adjustment unit164is coupled to the first terminal T1of the amplification unit14. The first terminal of the first phase adjustment unit165is coupled to the input terminal IN of the amplification unit14, and the second terminal of the first phase adjustment unit165is coupled to the voltage terminal GND. The first terminal of the first phase adjustment unit166is coupled to the first terminal T1of the amplification unit14, and the second terminal of the first phase adjustment unit166is coupled to the input terminal IN of the amplification unit14. In particular, the first phase adjustment unit166may be disposed on the feedback path. The first terminal of the first phase adjustment unit167is coupled to the input terminal IN of the amplification unit14, and the second terminal of the first phase adjustment unit167is coupled to the second terminal T2of the amplification unit14. In some embodiments, one or a combination of the first phase adjustment unit161to167may be selectively adopted to satisfy application and design requirements.

The impedances of the first phase adjustment units161to167are adjustable to compensate for the phase change of the output signal RFout for each of the gain modes. In particular, the first phase adjustment units161to163may be configured to adjust inductance. The first phase adjustment units164and165may be configured to adjust capacitance and inductance. The first phase adjustment unit166may be configured to adjust inductance or may be configured to adjust capacitance and resistance. The first phase adjustment unit167may be configured to adjust capacitance. In some embodiments, the first phase adjustment unit161,162or163may include a variable inductor. The first phase adjustment unit164,165or166may include a variable impedance component. The first phase adjustment unit167may include a variable capacitor. In some embodiments, the first phase adjustment units161to167may adjust the gain of the amplifier circuit1by adjusting the impedance thereof.

The amplifier circuit1may further include inductors Lg and Ls and a capacitor Co. The inductor Lg includes a first terminal coupled to the input terminal10of the amplifier circuit1, and a second terminal coupled to the first terminal of the first phase adjustment unit161. In some embodiments, the inductor Lg and the first phase adjustment unit161may swap places, so that the second terminal of the first phase adjustment unit161may be coupled to the input terminal IN of the amplification unit14through the inductor Lg. The inductor Ls includes a first terminal coupled to the second terminal of the first phase adjustment unit162, and a second terminal coupled to the voltage terminal GND. In some embodiments, the inductor Ls and the first phase adjustment unit162may swap places, so that the first terminal of the first phase adjustment unit162may be coupled to the second terminal T2of the amplification unit14through the inductor LS. The inductors Lg and Ls may be used for impedance matching of the amplifier circuit1. The capacitor Co includes a first terminal coupled to the second terminal of the first phase adjustment unit163, and a second terminal coupled to the output terminal12of the amplifier circuit1. In some embodiments, the capacitor Co and the first phase adjustment unit163may swap places, so that the first terminal of the first phase adjustment unit163may be coupled to the output terminal OUT of the amplification unit14through the capacitor Co. The capacitor Co may be a DC block capacitor.

The configurations for the three gain modes are provided in the following paragraphs to serve for exemplary purposes only, and are not intended to limit the scope of the invention.

In some embodiments, the amplifier circuit1may selectively operate in the high gain mode, the low gain mode or the bypass mode according to the power of the input signal RFin. When the input signal RFin has a first power, the amplifier circuit1may be operated in the high gain mode and the output signal RFout has a first phase; when the input signal RFin has a second power, the amplifier circuit1may be operated in the low gain mode and the output signal RFout has a second phase; and when the input signal RFin has a third power, the amplifier circuit1may be operated in the bypass mode and the output signal RFout has a third phase. The third power is higher than the second power, and the second power is higher than the first power. In some embodiments, the phases of the output signal RFout may be maintained substantially unchanged or varying within the small predetermined range in the various gain modes by controlling a phase difference between any two adjacent gain modes. Further, a phase difference between the high gain mode and the low gain mode or a phase difference between the low gain mode and the bypass mode may be controlled within a tolerance value T°. Table1shows exemplary phase angles of the first phase, the second phase and the third phase.

Table 1 shows that the phase difference between adjacent modes is controlled within the tolerance value T°. For example, in Case 5, the first phase may be set at N°, the second phase may be set at (N+T)°, and the third phase may be set at (N+2T)°. The impedances of at least one of the first phase adjustment units161to167may be adjusted to control the phase difference within the tolerance value T°. The tolerance value T° may be regarded as the predetermined range. In this manner, a difference between the first phase and the second phase or a difference between the second phase and the third phase may be controlled within the predetermined range. In another embodiment, the phases of the output signal RFout may be maintained substantially unchanged or varying within the small predetermined range in the various gain modes by selecting one of the first phase, the second phase and the third phase as a reference phase of the amplifier circuit1. The reference phase may be set to a target phase N°, and the remaining phases of the first phase, the second phase and the third phase may be set to a target phase (N+T)° or (N−T)°. For example, in Case 4, the second phase may be selected as the reference phase of the amplifier circuit1, and may be set to the target phase N°, the first phase may be set to the target phase (N−T)°, and the third phase may be set to the target phase (N+T)°. The impedances of at least one of the first phase adjustment units161to167may be adjusted to meet the respective target phases in the high gain mode, the low gain mode, and the bypass mode. The tolerance value T° may be regarded as the predetermined range. In this manner, a difference between the first phase and the second phase or a difference between the second phase and the third phase may be within the predetermined range. In the above embodiment, N° may be a value from −180 to 180, the tolerance value T° may be a value from 0 to 25. In other embodiments, the range of the tolerance value T° may be set based on the actual applications and design requirements.

FIG.2is a circuit schematic of an amplifier circuit2according to another embodiment of the invention. The main difference between the amplifier circuit2and the amplifier circuit1is that the amplifier circuit2employs the first phase adjustment units163,164,166and167, and further includes variable inductors Lv1and Lv2and a second phase adjustment unit80. The first phase adjustment unit161inFIG.1and the inductor Lg inFIG.1may be integrated into the variable inductor Lv1. The variable inductor Lv1includes a first terminal coupled to the input terminal10of the amplifier circuit2, and a second terminal coupled to the input terminal IN of the amplification unit14. The first phase adjustment unit162inFIG.1and the inductor Ls inFIG.1may be integrated into the variable inductor Lv2. The variable inductor Lv2includes a first terminal coupled to the second terminal T2of the amplification unit14, and a second terminal coupled to the voltage terminal GND. The variable inductors Lv1and Lv2may be used to not only provide impedance matching of the amplifier circuit2, but may also deliver the desired gain while maintaining the phases change of the output signal RFout within the predetermined range. The first phase adjustment unit163may include a variable inductor Lv3. The first phase adjustment unit164may include a variable impedance component Zv1. The first phase adjustment unit166may include a variable impedance component Zv2. The first phase adjustment unit167may include a variable capacitor Cv1. Explanations for the configurations and the operations of the inductors Lg and Ls and the first phase adjustment units161,162,163,164,166and167are provided in the preceding paragraphs and will not be repeated here for brevity.

The second phase adjustment unit80includes a first terminal coupled to the output terminal OUT of the amplification unit14, and a second terminal coupled to the output terminal12of the amplifier circuit2. Further, the second terminal of the second phase adjustment unit80is coupled to the output terminal12of the amplifier circuit2via the first phase adjustment unit163. In some embodiments, the second phase adjustment unit80and the first phase adjustment unit163may swap places, so that the first terminal of the second phase adjustment unit80may be coupled to the output terminal OUT of the amplification unit14via the first phase adjustment unit163. The second phase adjustment unit80includes a variable capacitor Cv2. In some embodiments, the amplifier circuit2may employ the second phase adjustment unit80in place of the capacitor Co inFIG.1. In such a case, the variable capacitor Cv2may be a DC block capacitor and may also be used to adjust the phase of the output signal RFout. The variable capacitor Cv2may be implemented by a varactor, a parallel-connected switch and capacitor or a serial-connected switch and capacitor. In some embodiments, the second phase adjustment unit80may further be used to adjust the gain of the amplifier circuit2.

FIG.3is a circuit schematic of the first phase adjustment unit161,162or163inFIG.1. The first phase adjustment unit161,162or163may include a variable inductor. The variable inductor may include an inductor L31and a switch SW31. The inductor L31includes a first terminal coupled to the first terminal of the first phase adjustment unit161,162or163, and a second terminal coupled to the second terminal of the first phase adjustment unit161,162or163. The switch SW31includes a first terminal coupled to the first terminal of the inductor L31, a second terminal coupled to the second terminal of the inductor L31, and a control terminal. In some embodiments, the quantity of the parallel-connected switches and inductors of the first phase adjustment unit161,162or163may be selectively configured based on the actual applications and design requirements.

FIG.4is a circuit schematic of the first phase adjustment unit164or165inFIG.1. The first phase adjustment unit164or165may include a variable impedance component. The variable impedance component may include an inductor L41, capacitors C41and C42, and a switch SW41. The inductor L41includes a first terminal coupled to the first terminal of the first phase adjustment unit164or165, and a second terminal coupled to the second terminal of the first phase adjustment unit164or165. The capacitor C41includes a first terminal coupled to the first terminal of the inductor L41, and a second terminal. The switch SW41includes a first terminal coupled to the second terminal of the capacitor C41, a second terminal, and a control terminal. The capacitor C42includes a first terminal coupled to the second terminal of the switch SW41, and a second terminal coupled to the second terminal of the inductor L41. The capacitors C41and C42may be DC block capacitors and may also be used with inductor L41to compensate for the phase change of the output signal RFout for each of the gain modes.

FIG.5is a circuit schematic of the first phase adjustment unit166inFIG.1. The first phase adjustment unit166may include a variable impedance component. The variable impedance component may include a capacitor C51, an inductor L51and a switch SW51. The capacitor C51includes a first terminal coupled to the first terminal of the first phase adjustment unit166, and a second terminal. The inductor L51includes a first terminal coupled to the second terminal of the capacitor C51, and a second terminal coupled to the second terminal of the first phase adjustment unit166. The switch SW51includes a first terminal coupled to the first terminal of the inductor L51, a second terminal coupled to the second terminal of the inductor L51, and a control terminal. The capacitor C51may be a DC block capacitor.

FIG.6is a circuit schematic of the first phase adjustment unit167inFIG.1. The first phase adjustment unit167may include a variable capacitor. The variable capacitor may include a capacitor C61and a switch SW61. The capacitor C61includes a first terminal coupled to the first terminal of the first phase adjustment unit167, and a second terminal. The switch SW61includes a first terminal coupled to the second terminal of the capacitor C61, a second terminal coupled to the second terminal of the first phase adjustment unit167, and a control terminal. In some embodiments, the capacitor C61and the switch SW61may swap places, so that the first terminal of the switch SW61is coupled to the first terminal of the first phase adjustment unit167, the second terminal of the switch SW61is coupled to the first terminal of the capacitor C61, and the second terminal of the capacitor C61is coupled to the second terminal of the first phase adjustment unit167. The first phase adjustment unit167may further be used for input impedance matching of the amplifier circuit1. In some embodiments, the serial-connected capacitors and switches of the first phase adjustment unit167may be arranged in correspondence to respective transistors in the amplification unit14, or may be selectively arranged in correspondence to selected transistors.

FIG.7is a circuit schematic of the amplifier circuit1inFIG.1. The amplifier circuit1may employ the first phase adjustment units161,162,164,166and167.

The amplification unit14includes transistors M1to M4. The transistor M1includes a first terminal, a second terminal coupled to the second terminal T2of the amplification unit14, and a control terminal coupled to the input terminal IN of the amplification unit14. The transistor M2includes a first terminal coupled to the first terminal of the transistor M1, a second terminal coupled to the second terminal of the transistor M1, and a control terminal coupled to the control terminal of the transistor M1. The transistor M3includes a first terminal coupled to the first terminal of the transistor M2, a second terminal coupled to the second terminal of the transistor M2, and a control terminal coupled to the control terminal of the transistor M2. The transistor M4includes a first terminal coupled to the first terminal T1and the output terminal OUT of the amplification unit14, a second terminal coupled to the first terminal of the transistor M1, and a control terminal.

Each of the first phase adjustment units161and162may be implemented by two sets of circuits inFIG.3. The first phase adjustment unit161includes inductors Lg1, Lg2and switches SW1, SW2, and the first phase adjustment unit162includes inductors Ls1and Ls2and switches SW3and SW4. The first phase adjustment unit164may be implemented by the circuit inFIG.4. The first phase adjustment unit164includes an inductor Ld, a switch SW5, and capacitors Cd1, Cd2. The first phase adjustment unit167may be implemented by two sets of circuits inFIG.6. The first phase adjustment unit167includes a capacitor C1and a switch SW6corresponding to the transistor M1, and a capacitor C2and a switch SW7corresponding to the transistor M2. Explanations for the operations and configurations of the first phase adjustment units161,162,164and167may be found in the preceding paragraphs and will not be repeated here for brevity.

The first phase adjustment unit166inFIG.7shows a circuit schematic of another embodiment of the first phase adjustment unit166inFIG.1. The first phase adjustment unit166inFIG.7may be configured to adjust impedance. The first phase adjustment unit166may include a variable impedance component. The variable impedance component may include the capacitor C3, the resistors R1to R3and the switches SW8and SW9. The capacitor C3includes a first terminal coupled to the first terminal of the first phase adjustment unit166, and a second terminal. The resistor R1includes a first terminal coupled to the second terminal of the capacitor C3, and a second terminal. The resistor R2includes a first terminal coupled to the second terminal of the resistor R1, and a second terminal. The resistor R3includes a first terminal coupled to the second terminal of the resistor R2, and a second terminal coupled to the second terminal of the first phase adjustment unit166. The switch SW8includes a first terminal coupled to the first terminal of the resistor R1, a second terminal coupled to the second terminal of the resistor R1, and a control terminal. The switch SW9includes a first terminal coupled to the first terminal of the resistor R2, a second terminal coupled to the second terminal of the resistor R2, and a control terminal. The parallel-connected resistor R2and switch SW9, the parallel-connected resistor R1and switch SW8, and the resistor R3may swap places. The first phase adjustment unit166may further be used to enhance the linearity of the amplifier circuit1.

The amplifier circuit1may further include switches SW10and SW11. Each of the switches SW10and SW11includes a first terminal, a second terminal, and a control terminal. The first terminal of the switch SW10is coupled to the second terminal of the transistor M2, and the second terminal of the switch SW10is coupled to the second terminal T2of the amplification unit14. The first terminal of the switch SW11is coupled to the second terminal of the transistor M3, and the second terminal of the switch SW11is coupled to the second terminal T2of the amplification unit14. The transistor size of the amplification unit14maybe adjusted by turning on or off the switches SW10and/or SW11. In some embodiments, each transistor or a specific transistor of the amplification unit14may be correspondingly provided with a switch coupled between the second terminal T2of the amplification unit14and a second terminal of each transistor or the specific transistor.

The transistors M1to M4and the switches SW1to SW11may be FET, BJT, or other types of transistors. In some embodiments, when the transistors M1to M4and the switches SW1to SW11are FETs, the first terminal may be a drain, the second terminal may be a source, and the control terminal may be a gate. When the transistors M1to M4and the switches SW1to SW11are BJTs, the first terminal may be a collector, the second terminal may be an emitter, and the control terminal may be a base. The transistors M1to M4and the switches SW1to SW11may be controlled by an internal circuit of the amplifier circuit1or by an external circuit other than the amplifier circuit1to turn on or off.

The inductor Lg3inFIG.7may be regarded as the inductor Lg inFIG.1, and the inductor Ls3inFIG.7may be regarded as the inductor Ls inFIG.1. Furthermore, in order to maintain the phase change of the output signal RFout within the predetermined range in all the gain modes, adjustments may be made to at least one of the equivalent inductance of the inductors Lg1to Lg3, the equivalent inductance of the inductors Ls1to Ls3, the equivalent capacitance of the capacitors Cd1and Cd2, the equivalent inductance of the inductor Ld, the equivalent capacitance of the capacitors C1and C2, the overall impedance of the resistors R1to R3and the capacitor C3, and the total width of the transistors M1to M3.

The equivalent inductance of the inductors Lg1to Lg3may be controlled by the switches SW1, SW2, the equivalent inductance of the inductors Ls1to Ls3may be controlled by the switches SW3, SW4, the equivalent capacitance of the capacitors Cd1and Cd2and the equivalent inductance of the inductor Ld may be controlled by the switch SW5, the equivalent capacitance of the capacitors C1and C2may be controlled by the switches SW6, SW7, the overall impedance of the resistors R1to R3and the capacitor C3may be controlled by the switches SW8, SW9, and the total width of the transistors M1to M3may be adjusted by the switches SW10, SW11.

In the high gain mode, the transistors M1to M4may be turned on, the switches SW3, SW4, SW10and SW11may be turned on and the switches SW1, SW2, SW5to SW9may be turned off, so as to provide the high gain while maintaining the phase change of the output signal RFout within the predetermined range. Further, the switches SW10and SW11may be turned on to couple the second terminals of transistors M2and M3to the voltage terminal GND, increasing the total width of the transistors M1to M3, increasing the supply current Icc, and resulting in a lagging phase shift. The switches SW8and SW9may be turned off to select the resistors R1and R2, decreasing the feedback amount in the feedback path. The switches SW6and SW7may be turned off to decrease the equivalent capacitance of the capacitors C1and C2, resulting in a leading phase shift. The switch SW5may be turned off to reduce the equivalent capacitance of the capacitors Cd1and Cd2and the equivalent inductance of the inductor Ld, resulting in a leading phase shift. The switches SW3and SW4may be turned on to deselect the inductors Ls1and Ls2, decreasing the equivalent inductance of the inductors Ls1to Ls3, resulting in a leading phase shift. The switches SW1and SW2may be turned off to select the serial-connected inductors Lg1and Lg2, increasing the equivalent inductance of the inductors Lg1to Lg3, resulting in a lagging phase shift. That is, at least one of the transistor size of the transistors M1to M3, the equivalent capacitance of the capacitors C1and C2, the equivalent capacitance of the capacitors Cd1and Cd2, the equivalent inductance of the inductor Ld, the equivalent inductance of the inductors Ls1to Ls3and the equivalent inductance of the inductors Lg1to Lg3may be adjusted based on the tolerance value T° of the phase difference between the high gain mode and the low gain mode or the target phase of the first phase, thereby compensating for the phase change in the high gain mode and maintain the phase change of the output signal RFout within the predetermined range.

In the low gain mode, the transistors M1, M2and M4maybe turned on, the transistor M3may be turned off, the switches SW1, SW3, SW6, SW7, SW8, SW10may be turned on and the switches SW2, SW4, SW5, SW9, SW11may be turned off, so as to provide the intermediate gain while maintaining the phase change of the output signal RFout within the predetermined range. Further, the switch SW11may be turned off to disconnect the second terminal of the transistor M3from the voltage terminal GND, leaving the transistors M1, M2and M4in operation, decreasing the total width of transistors M1to M3, decreasing the supply current Icc, and resulting in a leading phase shift. In some embodiments, the transistor M2and the switch SW10may be turned off instead of turning off the transistor M3and the switch SW11to provide the intermediate gain. The switch SW8may be turned on to deselect the resistor R1and the switch SW9may be turned off to select the resistor R2, increasing the feedback amount in the feedback path. The switches SW6and SW7may be turned on to increase the equivalent capacitance of the capacitor C1and the capacitor C2, resulting in a lagging phase shift. In some embodiments, only one of the switches SW6and SW7maybe turned on to provide a limited lagging phase shift. The switch SW5maybe turned off to decrease the equivalent capacitance of the capacitors Cd1and Cd2, resulting in a leading phase shift, and maintaining the equivalent inductance of the inductors Ld in the low gain mode substantially equal to that in the high gain mode. The switch SW3may be turned on to deselect the inductor Ls1, and the switch SW4may be turned off to select the inductor Ls2, increasing the equivalent inductance of the inductors Ls1to Ls3, resulting in a lagging phase shift. The switch SW1may be turned on to deselect the inductor Lg1, and the switch SW2may be turned off to select the inductor Lg2, decreasing the equivalent inductance of the inductors Lg1to Lg3, resulting in a leading phase shift. That is, at least one of the transistor size of the transistors M1to M3, the equivalent capacitance of the capacitors C1and C2, the equivalent capacitance of the capacitors Cd1and Cd2, the equivalent inductance of the inductor Ld, the equivalent inductance of the inductors Ls1to Ls3and the equivalent inductance of the inductors Lg1to Lg3may be adjusted based on the tolerance value T° of the phase difference between the high gain mode and the low gain mode or the tolerance value T° of the phase difference between the low gain mode and the bypass gain mode or the target phase of the second phase, thereby compensating for the phase change in the low gain mode and maintain the phase change of the output signal RFout within the predetermined range.

In the bypass mode, the transistors M1and M4may be turned on, the transistors M2and M3may be turned off, the switches SW1, SW2, SW5, SW6, SW8and SW9may be turned on and the switches SW3, SW4, SW7, SW10and SW11may be turned off, so as to provide the bypass gain while maintaining the phase change of the output signal RFout within the predetermined range. In the bypass mode, the input signal RFin is processed in a manner similar to the high gain mode and the low gain mode, that is, the input signal RFin passes through the amplification unit14. In addition, since the bypass gain is less than 0 dB, after the input signal RFin passes through the amplification unit14, the power of the input signal RFin will be reduced to generate the output signal RFout. In this manner, the phase of the output signal RFout in the bypass mode is substantially similar to those in the high gain mode and the low gain mode. Further, the switches SW10and SW11may be turned off to disconnect the second terminals of the transistors M2and M3from the voltage terminal GND, leaving the transistor M1and M4in operation, decreasing the supply current Icc, and resulting in a leading phase shift. The switches SW8and SW9may be turned on to deselect the resistors R1and R2, increasing the feedback amount in the feedback path. The switch SW6may be turned on to increase the equivalent capacitance of the capacitor C1, resulting in a lagging phase shift. The switch SW5may be turned on to increase the equivalent capacitance of the capacitors Cd1and Cd2and the equivalent inductance of the inductor Ld, resulting in a lagging phase shift. The switches SW3and SW4may be turned off to select the inductors Ls1and Ls2, maximizing the equivalent inductance of the inductors Ls1to Ls3, resulting in a lagging phase shift. The switches SW1and SW2may be turned on to deselect the inductors Lg1and Lg2, decreasing the equivalent inductance of the inductors Lg1to Lg3, resulting in a leading phase shift. That is, at least one of the transistor size of the transistors M1to M3, the equivalent capacitance of the capacitors C1and C2, the equivalent capacitance of the capacitors Cd1and Cd2, the equivalent inductance of the inductor Ld, the equivalent inductance of the inductors Lg1to Lg3and the equivalent inductance of the inductors Ls1to Ls3may be adjusted based on the tolerance value T° of the phase difference between the low gain mode and the bypass gain mode or the target phase of the third phase, thereby compensating for the phase change in the bypass mode and maintain the phase change of the output signal RFout within the predetermined range. In some embodiments, the amplification unit14are configured to have the maximum transistor size during the high gain mode, and configured to have the minimum transistor size during the bypass mode.

In addition, the equivalent inductance of the inductors Lg1to Lg3may affect the impedance matching of the amplifier circuit1. The effect of the lowered equivalent capacitance of the capacitors C1and C2for the impedance matching will be offset by an increase in the equivalent inductance of the inductors Lg1to Lg3. Likewise, the effect of the increased equivalent capacitance of the capacitors C1and C2for the impedance matching will be offset by a decrease in the equivalent inductance of the inductors Lg1to Lg3.

The equivalent inductance of the inductors Ls1to Ls3may affect the gain and the linearity of the amplifier circuit1. The linearity may be represented by the third order input intercept point (IIP3). An increase in the equivalent inductance of the inductors Ls1to Ls3may result in an increase in the IIP3 and a decrease in the gain. A decrease in the equivalent inductance of the inductors Ls1to Ls3may result in an increase in the gain and a decrease in the IIP3.

In other embodiments, the amplification unit14may include the transistors M1and M4, and the transistors M2and M3, the capacitor C2and the switches SW7, SW10and SW11being removed from the amplifier circuit1. In this circuit configuration, the transistors M1and M4may be turned on regardless of the amplifier circuit1being operated in the high gain mode, the low gain mode or the bypass mode.

FIG.8is a circuit schematic of another amplifier circuit1inFIG.1. Main difference betweenFIG.8andFIG.7is that the amplification unit14inFIG.8includes transistors M1and M2, and the transistors M3and M4, the switch SW11being removed from the amplifier circuit1. InFIG.8, the first terminal of the transistor M1is coupled to the first terminal T1and the output terminal OUT of the amplification unit14. In some embodiments, instead of coupling between the second terminal of the transistor M2and the second terminal T2of the amplification unit14, the switch SW10may be coupled between the second terminal of the transistor M1and the second terminal T2of the amplification unit14. In other embodiments, an additional switch may be arranged between the second terminal of the transistor M1and the second terminal T2of the amplification unit14. In some embodiments, the transistors M1and M2may be turned on based on actual applications and design requirements. For example, in the high gain mode, the transistors M1and M2may be turned on; in the low gain mode or the bypass mode, at least one of the transistors M1and M2may be turned on. That is, at least one of the transistors M1and M2maybe turned on regardless of the amplifier circuit1being operated in the high gain mode, the low gain mode or the bypass mode.

FIG.9is a circuit schematic of another amplifier circuit1inFIG.1. The main difference betweenFIG.9andFIG.7is that the amplification unit14inFIG.9includes the transistor M1, and the transistors M2to M4, and the capacitor C2and the switches SW7, SW10and SW11are removed from the amplifier circuit1. InFIG.9, the first terminal of the transistor M1is coupled to the first terminal T1and the output terminal OUT of the amplification unit14. The amplifier circuit1may further include a bias circuit70for providing a bias voltage Vbias to the control terminal of the transistor M1, so as to control the gain of the amplifier circuit1. For example, the bias voltage Vbias may be set at a highest voltage level for the amplifier circuit1to provide the high gain in the high gain mode, the bias voltage Vbias may be set at an intermediate voltage level for the amplifier circuit1to provide the intermediate gain in the low gain mode, and the bias voltage Vbias maybe set at a lowest voltage level for the amplifier circuit1to provide the bypass gain in the bypass mode. The transistor M1may be turned on regardless of the amplifier circuit1being operated in the high gain mode, the low gain mode or the bypass mode. In some embodiments, the amplifier circuit1inFIG.1,FIG.7orFIG.8may adopt the bias circuit70for providing a bias voltage Vbias to the control terminal of the transistor M1, so as to control the gain of the amplifier circuit1.

The embodiments of the amplifier circuit employs at least one first phase adjustment unit to maintain the phase of the output signal substantially unchanged or varying within a predetermined range while achieving various gain levels in various gain modes and reducing the signal processing time in the electronic system.