Short gate high power MOSFET and method of manufacture

A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a short gate high power MOSFET, and a method of making a short gate high power UMOSFET.

2. Description of the Background Art

In silicon carbide (SiC) MOSFETs (metal oxide semiconductor field effect transistor), inversion channel mobility is dramatically lower than in silicon based MOSFETs. The relatively poor inversion channel mobility is due in large part to the gate oxidation process, whereby a rough interface between the gate oxide and the underlying silicon carbide is formed. Defects which occur at the gate oxide/silicon carbide interface due to the rough interface reduce channel mobility.

A common approach to improving inversion channel mobility of silicon carbide MOSFETs focuses on reducing channel length, so that the distance traveled by carriers within the inversion channel underneath the gate is as short as possible. However, a problem encountered with this approach is that as channel length is reduced, breakdown voltage of the MOSFET device becomes limited. If the channel length is too short, the channel may open responsive to a high voltage applied to the drain even without a necessary voltage applied to the gate, to thus force the device into an on state when it should be off. This is commonly referred to as a short-channel effect, or an early turn-on effect. A need thus exists to protect the channel of the device from excessive drain voltage, so as to prevent short channel effects such as the early turn-on effect. Key aspects of short channel MOSFET design thus include limiting the impact of low channel mobility by reducing the length of the conduction path at the MOS interface, while at the same time preventing short-channel effects.

SUMMARY OF THE INVENTION

In accordance with a first embodiment, a semiconductor device includes in combination a substrate of a first conductivity type; a region of a second conductivity type within the substrate, the region extending from an upper surface of the substrate into the substrate, the second conductivity type opposite the first conductivity type; a first layer of the first conductivity type over the substrate and the region; a trench extending into the first layer, a bottom of the trench is within the first layer and a portion of the first layer is intermediate between the bottom of the trench and the region; a gate having gate sections over the portion of the first layer at the bottom of the trench and covering sidewalls of the trench, a central area of the portion of the first layer at the bottom of the trench exposed between the gate sections; an insulating layer covering an upper surface of the first layer and the gate sections, and within the trench covering the central area of the portion of the first layer at the bottom of the trench; and a source contact overlying the insulating layer, the source contact extending through the insulating layer and the central area of the portion of the first layer at the bottom of the trench, to contact the central area of the portion of the first layer at the bottom of the trench and the region.

In accordance with another embodiment, a vertical field effect transistor includes in combination a first layer of a first conductivity type; an implanted region of a second conductivity type extending into the first layer, the second conductivity type opposite the first conductivity type; a second layer of the first conductivity type on an upper surface of the first layer and an upper surface of the implanted region; a trench extending into the second layer above the implanted region, a portion of the second layer is disposed intermediate between a bottom of the trench and the implanted region, the implanted region extending laterally beyond sidewalls of the trench; a gate having gate sections within the trench and covering the sidewalls of the trench, a central area of the portion of the second layer at the bottom of the trench is exposed between the gate sections; an insulating layer covering the second layer and the gate sections, and within the trench; a source contact overlying the insulating layer, the source contact extending through the insulating layer within the trench and the central area of the portion of the second layer at the bottom of the trench, to contact the implanted region and the second layer; and a drain contact on a bottom surface of the first layer, the bottom surface on a side of the first layer opposite the upper surface.

In accordance with a further embodiment, a method of manufacturing a semiconductor device includes in combination forming a first region in a substrate of a first conductivity type, the first region extending from an upper surface of the substrate into the substrate and having a second conductivity type that is opposite the first conductivity type; forming a first layer of the first conductivity type over the substrate and the first region; forming a trench extending into the first layer, a bottom of the trench is within the first layer and a portion of the first layer is intermediate between the bottom of the trench and the first region; forming a gate having gate sections over the portion of the first layer at the bottom of the trench and covering sidewalls of the trench, a central area of the portion of the first layer at the bottom of the trench is exposed between the gate sections; forming an insulating layer covering an upper surface of the first layer and the gate sections, and within the trench covering the central area of the portion of the first layer at the bottom of the trench; and forming a source contact overlying the insulating layer, the source contact extending through the insulating layer and the central area of the portion of the first layer at the bottom of the trench, to contact the central area of the portion of the first layer at the bottom of the trench and the first region.

In accordance with a still further embodiment, a method of manufacturing a vertical field effect transistor includes in combination providing a first layer of a first conductivity type; implanting a first region of a second conductivity type in the first layer, the second conductivity type being opposite the first conductivity type; forming a second layer of the first conductivity type on an upper surface of the first layer and an upper surface of the implanted region; forming a trench extending into the second layer above the implanted region, a portion of the second layer is disposed intermediate between a bottom of the trench and the first region, the first region extending laterally beyond sidewalls of the trench; forming a gate having gate sections within the trench and covering the sidewalls of the trench, a central area of the portion of the second layer at the bottom of the trench is exposed between the gate sections; forming an insulating layer covering the second layer and the gate sections, and within the trench; forming a source contact overlying the insulating layer, the source contact extending through the insulating layer within the trench and through the central area of the portion of the second layer at the bottom of the trench, to contact the implanted region and the second layer; and forming a drain contact on a bottom surface of the first layer, the bottom surface on a side of the first layer opposite the upper surface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may however be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, the embodiments as described are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the shape and thickness of the elements and layers may be exaggerated for clarity, and are not necessarily drawn to scale. Also, like reference numbers are used to refer to like elements throughout the application. Description of well known methods and materials are omitted. Also, this application may include aspects or features described in copending application Ser. No. 11/855,595, which is hereby incorporated by reference in its entirety.

FIG. 1is a cross-sectional view andFIG. 2is a plan view of a semiconductor device of an embodiment of the present invention. The cross-sectional view inFIG. 1is taken along sectional line1-1shown inFIG. 2. The plan view ofFIG. 2is taken along sectional line2-2shown inFIG. 1.

As shown inFIG. 1, substrate10includes a first main or upper surface12and a second main or bottom surface14opposing first main surface12. First and second main surfaces12and14may be characterized as front and back sides of substrate10, whereby devices are disposed on or over first main surface12. In this embodiment as described, substrate10is silicon carbide (SiC) having n-type conductivity and a thickness of about 300 to 500 μm, or about 400 μm. More particularly, although not shown in detail, substrate10includes an uppermost epilayer having a thickness in a range of about 5 μm-30 μm and a dopant concentration of at least about 1015/cm3. The epilayer is disposed on a base substrate having a standard thickness of at least 350 μm and a high dopant concentration of at least about 1019/cm3. Substrate10may be doped with an n-type impurity such as nitrogen or phosphorous. Substrate10however should not necessarily be limited as silicon carbide, or as having n-type conductivity, but may be other materials such as silicon or gallium nitride (GaN). Moreover, as noted above, substrate10should not necessarily be limited as a single epitaxial layer on a single base substrate layer of silicon carbide or other substrate material, but may in general be a growth substrate with plural epitaxial layers grown thereon.

As further shown inFIG. 1, p-type region20is shown as extending from upper surface12of substrate10, into substrate10. Region20may have a thickness or depth in the vertical or y-direction or about 0.4 μm, and may be doped with a p-type impurity such as aluminum, boron or beryllium. Region20may have a dopant profile that is graded in a vertical or y-direction, as having a dopant concentration of at least about 1018/cm3near upper surface22, and a somewhat lower dopant concentration of at least about 1016/cm3near the bottom of region20. As should be understood in view ofFIG. 2, region20extends along the z-direction. Incidentally, it should be understood that grading of the dopant concentration enables shaping of the depletion profile, which can help limit the depletion of channel regions between neighboring regions20, to thus optimize resistance. However, region20should not necessarily be limited as having a dopant profile that is graded in the vertical direction, but may have a substantially uniform dopant concentration.

As further shown inFIG. 1, n-type silicon carbide layer30is disposed on an entirety of upper surface12of substrate10, and also covering upper surface22of region20. Layer30may be epitaxially grown, and may have a total thickness of at least about 0.7 μm. More particularly, although not shown in detail, layer30may consist of multilayers to have a dopant profile that is graded in the vertical or y-direction. For example, layer30may include a first sublayer having a dopant concentration of about 1016/cm3and a thickness of about 0.2 μm on substrate10and region20, and a second sublayer having a dopant concentration of about 1017/cm3and a thickness of about 0.5 μm on the first sublayer. However, layer30should not necessarily be limited as merely having two sublayers as described, but may in general be a single growth layer of substantially uniform dopant concentration, or may consist of more than two sublayers. The doping concentration and profile of layer30will determine the threshold characteristics of the device. A too high concentration or a too thick layer will result in a device with normally-on characteristics.

Layer30inFIG. 1includes a first trench32in an upper portion thereof over region20, extending from upper surface33of layer30, whereby trench bottom34of first trench32is within layer30. Portion36of layer30is intermediate or between trench bottom34of first trench32and upper surface22of region20. First trench32includes trench corner31. A narrow second trench35extends from trench bottom34of first trench32through intermediate portion36of layer30, and exposes upper surface22of region20. Second trench35is in a substantially central region of trench32. Layer30further includes n+-type source contact area38disposed within intermediate portion36as extending from trench bottom34of first trench32to upper surface22of region20, and as immediately surrounding second trench35. Source contact area38may have a dopant concentration of at least about 1019/cm3. Although not particularly shown in the plan view ofFIG. 2, first and second trenches32and35and source contact area38extend along the z-direction.

The structure shown inFIG. 1also includes a pair of gate sections64disposed over trench bottom34at peripheral areas of first trench32, as covering respective sidewalls of first trench32. In this embodiment, gate sections64are polysilicon having a thickness in the vertical or y-direction of about 0.5 μm, and may be doped with boron or aluminum. Gate oxide50having a thickness in a range of about 50-100 nm is disposed as on an entirety of upper surface33of layer30, the sidewalls of first trench32, and portions of trench bottom34of first trench32. Gate oxide50is intermediate between gate sections64and layer30. It should be understood that gate sections64are disposed as having minimal overlap with source contact area38.

As further shown inFIG. 1, field dielectric80such as silicon nitride is disposed over the entirety of the substrate, particularly as over gate oxide50and gate sections64. Field dielectric80may have a thickness in the vertical or y-direction of about 1 μm. Source contact70having a thickness of about 1 μm is disposed over the entirety of upper surface84of field dielectric80, and includes extension74that extends through via82within field dielectric80to be in contact with upper surface37of source contact area38, and through second trench35to be in contact with upper surface22of region20. Source contact70may be a multilayer including a nickel or titanium layer stacked on an aluminum layer. In the alternative, source contact70may be a single layer of titanium, aluminum or other materials, or a multilayer having more than two layers. The structure also includes drain contact90on lower or second surface14of substrate10. Drain contact90may also be a multilayer including a nickel or titanium layer stacked on an aluminum layer, but may in the alternative be a single layer of nickel, titanium, or other materials, or a multilayer having more than two layers. Also, field dielectric80may be other materials such as silicon dioxide, instead of silicon nitride.

As shown in the plan view ofFIG. 2, gate60includes gate sections64which extend along the z-direction shown inFIG. 1. Extension74of source contact70extends downward in the vertical or y-direction between gate sections64to be in contact with first contact area38and region20. That is, main gate contact60includes multiple gate sections64(which may hereinafter be referred to as gate contact fingers), and main source contact70includes multiple source contact extensions74(which may hereinafter be referred to as source contact fingers). Gate contact fingers64and source contact fingers74extend substantially parallel with respect to each other along the z-direction. As noted previously, first and second trenches32and35(not shown inFIG. 2) also extend along the z-direction, substantially along the entire length of gate contact fingers64and source contact fingers74. Multiple regions20are shown by dotted lines inFIG. 2, and are disposed respectively under a pair of gate contact fingers64and a corresponding source contact finger74. As may be appreciated in view ofFIG. 2, each region20extends widthwise underneath a corresponding first trench32(not shown) along the horizontal or x-direction substantially beyond the corresponding gate contact fingers64and the corresponding corners31of the first trench32. Regions20are disposed in a grid-like manner, and also extend lengthwise in the z-direction under the first and second trenches32and35. The semiconductor device as shown inFIG. 1may thus be disposed as part of a multi-cell MOSFET design.

It should be understood that even though only three corresponding sets of gate contact fingers64and source contact finger74with corresponding regions20are shown inFIG. 2, the number of respective sets of gate contact fingers64and source contact finger74should not be limited as shown inFIG. 2. Such a grid MOSFET device may include various multiple contact fingers and regions20within the spirit and scope of the invention. Also, it should be understood that the shape of main gate contact60, the shape of regions20, and the distances between source contact fingers74and gate contact fingers64may be exaggerated for clarity. Also, for the sake of clarity, gate oxide50and field dielectric80are not shown inFIG. 2.

Operation of the semiconductor device of this embodiment will now be described hereinafter with reference toFIG. 1. As described previously, to reduce the impact of poor channel mobility, the device is designed to have a very short gate length in the horizontal or x-direction, particularly in a range of about 0.3 μm to 1.5 μm. However, in order to realize such a short channel region, the gate must be protected from high electric fields that result from high drain voltages. In this embodiment, the device is protected from such high electric fields by region20.

In detail, upon application of a positive potential to gate sections64shown inFIG. 1through gate contact60, an inversion layer is formed in intermediate portion36(which may hereinafter be referred to as a channel) under gate sections64. The inversion layer within channel36carries current from source contact area38as applied from source contact70, substantially in the horizontal or x-direction over region20. The current subsequently flows in the vertical or y-direction through substrate10out drain contact90. The device operates as a vertical MOSFET. The inversion layer is generated at both lateral sides of second trench35within channel36, so that current flows from source contact70through layer30along both the left and right sides of second trench35. During such a normal on-state as described, there is minimal potential drop within the device and the associated electric field is minimal.

To turn off the device ofFIG. 1, a ground or negative potential is applied to gate sections64, the value of which depends on the threshold of the device. As a result, carriers (electrons) are not attracted to the interface between channel36and gate oxide50under gate sections64. The inversion layer within channel36thus no longer exists, and vertical flow of current across channel36thus stops.

In a conventional MOSFET structure of trench design that does not include a buried region such as region20as shown inFIG. 1of the present application, immediately after the device is turned off by application of ground or negative potential to the gate, a large potential is present at the drain contact and a relatively low or zero potential is present at the source contact. Under such conditions, a high electric field is concentrated at the corners of the trench of the conventional MOSFET. The high electric field stresses the gate oxide within the trench, resulting in the occurrence of short channel effects and/or device failure.

In the semiconductor device of the embodiment inFIG. 1of the present application, region20limits the electric field that penetrates to corner31of trench32. In greater detail, at trench corner31of first trench32, the MOSFET transitions from an on state with steady flow of electrons and very little potential difference across the device vertically, to an off state where suddenly the supply of electrons across channel20has been turned off. When the MOSFET is turned off, the supply of electrons is removed. The depletion region begins to extend along intermediate portion36, with an associated potential drop across this corresponding region. As the depletion region extends laterally in the horizontal or x-direction, the potential drop increases such that in the off-state, the full applied potential is dropped across the device. However, region20in the device ofFIG. 1separates gate sections64from the highest electric field. The majority of the potential drop is taken up between region20and drain contact90. If region20was not present, there would be a large potential drop between gate sections64and drain contact90. This would result in a high electric field at corner31of first trench32. However, because region20is present in the structure shown inFIG. 1and is tied to a low potential at source contact70, a large potential drop does not exist between gate sections64and upper surface22of region20, and thus the electric field present at trench corner31is relatively low. There is a larger potential drop between the bottom of region20and drain contact90, resulting in a relatively larger electric field therebetween. However, this relatively larger electric field is shielded from trench corner31by region20. Region20can thus be characterized as splitting the potential realized across the structure.

A method of making a semiconductor device as shown inFIGS. 1 and 2will now be described with respect toFIGS. 3-14. It should be understood that this description will be presented with reference to cross-sections of the device taken along section line1-1inFIG. 2. Moreover, this description follows wherein the semiconductor layers are silicon carbide, substrate10and layer30have n-type conductivity, and region20has p-type conductivity. However, one of ordinary skill should understand that the semiconductor layers may be other materials such as silicon noted previously for example, and that conductivity type may be reversed. The description that follows thus should not be construed as limiting.

With reference toFIG. 3, although not shown in detail and as described previously, silicon carbide substrate10is provided as including an epilayer on a base substrate, The epilayer has a thickness in a range of about 5 μm-30 μm with a dopant concentration in a range of at least about 1015/cm3. The base substrate has a standard thickness of at least about 350 μm with a dopant concentration in a range of at least 1019/cm3. The epilayer thickness and dopant concentration are selected based on the blocking voltage desired for the device. The epilayer may be epitaxially grown on the base substrate using well known techniques such as metal organic chemical vapor deposition (MOCVD) to form substrate10, which is shown inFIG. 3as including upper surface12and an opposite bottom surface14. Nitrogen or phosphorous may be used as the n-type dopants.

To form p-type region20, an oxide layer is first deposited on upper surface12of substrate10using a plasma enhanced chemical vapor deposition (PECVD) or a low pressure CVD (LPCVD) process. The oxide layer is then patterned using well-known photolithography to form oxide mask110as shown inFIG. 3. Ion implantation is then carried out using oxide mask110to form p-type region20within substrate10. Region20may be formed as having a depth of about 0.4 μm from upper surface12of substrate10. Aluminum, boron or beryllium may be used as the p-type dopant. Ion implantation may be carried out so that region20may have a dopant profile that is graded in the vertical or y-direction. For example, although not shown inFIG. 3, an upper portion of region20may have a dopant concentration of at least about 1018/cm3, and a lower portion of region20may have a dopant concentration of at least about 1016/cm3. Subsequent ion implantation, the structure is annealed at a temperature of about 1600° C. for about at least 5 minutes for example, to activate the impurities implanted therein. Mask110is subsequently removed.

Referring toFIG. 4, after removal of mask110shown inFIG. 3, n-type layer30having upper surface33is epitaxially regrown on the upper part of the structure by MOCVD for example, as particularly on upper surface12of substrate10and upper surface22of region20. Layer30may be epitaxially regrown to have a dopant profile that is graded in the vertical or y-direction. For example, although not shown in detail inFIG. 4, layer30may be epitaxially grown to have a total thickness of about 0.7 μm, as including a first sublayer on substrate10/region20that has a dopant concentration of about 1016/cm3and a thickness of about 0.2 μm, and a second sublayer that has a dopant concentration of about 1017/cm3and a thickness of about 0.5 μm on the first sublayer. It should be understood that the respective thicknesses and dopant concentrations of the sublayers are exemplary only, and may be selected according to design preference. Moreover, although described as having a graded dopant profile in view of the sublayers, layer30may in the alternative be epitaxially regrown as having substantially uniform concentration.

Referring toFIG. 5, subsequent epitaxial regrowth of layer30shown inFIG. 4, an oxide layer is deposited on upper surface33of layer30by MOCVD for example. The oxide layer is patterned using well-known photolithography to form oxide mask120that exposes a portion of upper surface33of layer30above region20. Layer30is subsequently etched using mask120and a dry etching technique such as reactive ion etching (RIE), to form first trench32having trench bottom34within layer30. First trench32may have a depth of about 0.5 μm from upper surface33of layer30to trench bottom34for example. As shown, intermediate portion36of layer30remains between trench bottom34and upper surface22of region20. Subsequent to the etching, ion implantation is carried out using mask120, to set the final n-type dopant concentration of intermediate portion36that will form the channel under gate sections64shown inFIG. 1. This final dopant concentration of intermediate portion36that will be disposed under gate sections64is set to about 5×1016/cm3. The concentration accuracy achieved using implantation is superior to epitaxy, and the ability to adjust the final doping level in region36by implantation allows very accurate control of the threshold voltage of the device.

With reference toFIG. 6, after the ion implantation as described with respect toFIG. 5, a silicon nitride layer40is regrown on the entirety of the structure using well-known techniques such as Plasma Enhanced Chemical Vapor Deposition (PECVD). As shown, silicon nitride layer40covers the upper surface of oxide mask120, the side surfaces of oxide mask120above first trench32, and the sidewalls and trench bottom34of first trench32. The thickness of layer40will determine the final active channel length and is chosen according to the high voltage design of the device. For example, layer40may have a thickness of about 0.3 to 1.5 microns. Alternative dielectric materials (such as silicon dioxide) may be used dependent on the required implantation profile.

With reference toFIG. 7, after formation of silicon nitride layer40as shown inFIG. 6, layer40is anisotropically etched using an RIE process, to remove portions of layer40from the upper surface of oxide mask120and from a central region of trench bottom34. Due to the anisotropic nature of the etch, portions42of layer40remain as spacers covering the side surfaces of oxide mask120and the sidewalls of first trench32, and on peripheral portions of trench bottom34near the sidewalls of first trench32. Thereafter, another n+-type ion implantation is carried out using spacers42and oxide mask120, to form n+-type source contact area38within layer30below the central region of trench bottom34between spacers42. The dopant concentration of source contact area38is at least about 1019/cm3.

It should be understood that the above noted etching of silicon nitride layer40to form spacers42as described with respect toFIG. 7defines the gate length of gate sections64shown inFIG. 1. That is, the gate length of gate sections64inFIG. 1is bounded by source contact area38, whereby the extent of source contact area38in the horizontal or x-direction is very accurately controlled by the growth and subsequent anisotropic etching of silicon nitride layer40. The gate length is thus defined by the growth of layer40, so that a short gate length in a range of about 0.3 to 1.5 μm that would otherwise be less easily achieved using standard photolithography techniques used in power device manufacture.

With reference toFIG. 8, after the implantation as described with respect toFIG. 7, spacers42and oxide mask120are removed by wet etching using hydrofluoric acid for example. The structure is then annealed at a low temperature of at least about 1200° C. to activate the impurities within source contact area38. Thereafter, gate oxide50having a thickness in a range of about 50-100 nm is grown by thermal oxidation at a temperature greater than about 1000° C. Gate oxidation50covers an entirety of the structure as shown inFIG. 8, as particularly on upper surface33of layer30, on the sidewalls of first trench32, and on trench bottom34. Gate oxide50thus covers both intermediate portion (channel)36and source contact area38. A post-oxidation anneal in nitrous oxide (NO or N2O) may be carried out to improve oxide quality. Alternatively a combination of thin thermally grown oxide may be combined with a deposited gate oxide formed using a technique such as Low Pressure Chemical Vapor Deposition (LPCVD).

With reference toFIG. 9, after formation of gate oxide50as described with respect toFIG. 8, a gate layer62that may be polycrystalline silicon having a thickness corresponding to the chosen channel length, i.e. largely equal to or greater than that of the silicon nitride later40, is deposited on the entirety of gate oxide50using an LPCVD process at a temperature of about 650° C. Gate layer62may be doped using boron or aluminum.

With reference toFIG. 10, after formation of gate layer62shown inFIG. 9, gate layer62is anisotropically etched using an RIE process, to remove portions of gate layer62from the top of gate oxide50above upper surface33of layer30, and from the central region of trench bottom34above source contact area38. Due to the anisotropic nature of the etch, portions of gate layer62remain as gate sections64on gate oxide50covering side surfaces of first trench32and over peripheral portions of trench bottom34near the sidewalls of first trench32. Gate sections64respectively have a gate length in the vertical or x-direction in a range of about 0.3 to 1.5 μm.

With reference toFIG. 11, after etching as described with respect toFIG. 10, a resist layer is subsequently formed over the entirety of the structure, particularly as on gate oxide50over upper surface33of layer30, on gate sections64, and on gate oxide50within first trench32over source contact area38. The resist layer is subsequently patterned using well-known photolithography, to form resist mask130having a narrow opening that exposes gate oxide50on trench bottom34over source contact area38. A dry etch such as RIE is subsequently carried out using resist mask130to etch and remove exposed gate oxide50, and to etch and remove source contact area38under the removed portion of gate oxide50. A narrow second trench35is thus formed through gate oxide50and source contact area38, to expose upper surface22of region20. Resist mask130is subsequently removed.

With reference toFIG. 12, after removal of resist mask130shown inFIG. 11, another resist layer is subsequently formed on the entirety of the structure, as particularly on gate oxide50over upper surface33of layer30, on gate sections64, within first trench32on gate oxide50, and within second trench35on upper surface22of region20. This resist layer is subsequently patterned using well-known photolithography, to form resist mask140which includes a narrow opening that exposes upper surface22of region20and portions of gate oxide50over source contact area38. A very short, controlled etch is subsequently carried out using resist mask140, to remove exposed gate oxide50over source contact area38. Thus, upper surfaces37of source contact area38are exposed for subsequent contact metallization. The resist mask is subsequently used in a “lift-off” process whereby a thin layer of metal such as nickel or titanium tungsten having a thickness of about 100 nm is deposited onto upper surfaces37of source contact area38, and within second trench35on upper surface22of region20. A thin layer of metal such as nickel or titanium tungsten having a thickness of about 100 nm (not shown inFIG. 12) is also deposited onto the back-surface14of the substrate10, as a preliminary drain contact layer. The structure is then annealed at a temperature of 950° C. to form ohmic metal contact72. Resist mask140is thereafter removed.

With reference toFIG. 13, after removal of resist mask140shown inFIG. 12, field dielectric layer80which may be silicon nitride having a thickness of about 1 μm, is deposited over the entirety of the surface of the structure using PECVD for example. Field dielectric layer80is particularly deposited on gate oxide50over upper surface33of layer30, on gate sections64, and within first and second trenches32and35on metal contact72and gate oxide50.

With reference toFIG. 14, after formation of field dielectric layer80as described with respect toFIG. 13, a resist layer is subsequently formed on an entirety of upper surface84of field dielectric layer80. The resist layer is subsequently patterned using well-known photolithography, to form resist mask150as having a narrow opening aligned over metal contact72. A dry etch such as RIE is then carried out using resist mask150, to remove field dielectric layer80and to thus form trench82that exposes metal contact72. Resist mask150is then removed.

With reference toFIG. 1, after removal of resist mask150as shown inFIG. 14, a metal layer is subsequently deposited over the entirety of the surface of the structure, as particularly on upper surface84of field dielectric80and to fill trench82on metal contact72. The metal layer may be a single metal layer of aluminum for instance, but in the alternative may be a multilayer stack including titanium and aluminum sublayers. The metal layer as deposited on upper surface84of field dielectric layer80may have a thickness of about 1 μm. Source contact70is thus formed, as including metal contact72(not shown inFIG. 1) and source finger74. The device is completed by depositing drain contact90on the preliminary drain contact layer deposited on bottom surface14of substrate10, wherein drain contact90may also be a single metal layer of titanium or aluminum for instance, but in the alternative may be a multilayer stack including titanium and aluminum sublayers.

Although the present invention has been described in detail, the scope of the invention should not be limited by the corresponding description and figures. Although not specifically highlighted the crystal type of the silicon carbide described in this invention is assumed to be 4H, however, alternate crystal polytypes such as 6H, 15R and 3C may also be used without impacting the design or method of operation of the device described. The orientation of the crystal is such that the epitaxial layers are grown on the “Si-face” of the crystal, but alternatively may also be grown on the “C-face”. Also, the concepts described above should be applicable as well for the case where the conductivity types of substrate10and layer30are reversed to be p-type, and the conductivity type of region20is reversed to be n-type. In this alternative case, the potentials as applied to the gate contact, the source contact and the drain contact would be inverted, as would be understood by one of ordinary skill. These various changes and modifications of the embodiments, as would become apparent to one of ordinary skill, should be considered as within the spirit and scope of the invention.