Strained silicon device manufacturing method

A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

This application is related to U.S. patent Ser. No. 10/810,950, filed Mar. 25, 2004, the disclosure of which is hereby incorporated by reference.

BACKGROUND

An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a semiconductor substrate using a fabrication process. As fabrication processes and materials improve, semiconductor device geometries continue to decrease in size since such devices were first introduced several decades ago. For example, current fabrication processes are producing devices having geometry sizes (e.g., the smallest component (or line) that may be created using the process) of less than 90 nm. However, the reduction in size of device geometries frequently introduces new challenges that need to be overcome.

As microelectronic device geometries are scaled below 65 nm, electrical efficiency becomes an issue that impacts device performance. Microelectronic device performance such as current gain can be significantly affected by the configuration and materials incorporated into microelectronic devices. Therefore, there is an inherent conflict with the configuration and/or the materials used in many of today's microelectronic devices.

Accordingly, what is needed in the art is a microelectronic device and method of manufacture that addresses the above discussed issues.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the present invention. Specific components and arrangements are described below to simplify the present disclosure by way of example, and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed, nor does it dictate that the referenced component is identical to others with the same reference numeral. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.

Referring toFIG. 1, a method10can be used for manufacturing a microelectronic device according to one or more embodiments of the present invention. For the sake of example, the method10will be described with reference to the manufacture of a semiconductor integrated circuit100, illustrated inFIGS. 2–8. The manufacturing method10can be used for the formation of a “graded junction” source/drain doped region in a semiconductor microelectronic device such as a transistor. It is understood that the method10can represent only a portion of a process flow, and it is further understood that in some embodiments, certain steps of the method may be rearranged or not performed altogether.

Referring also toFIG. 2, in the present example, the method10begins at step12for creating a microelectronics device101. The device101includes a substrate102, isolation regions104, a gate layer108, an electrode110, and a hard mask111.

The substrate102may be a semiconductor substrate, such as one including silicon. The isolation regions104may include silicon dioxide (SiO2), silicon nitride (SixNy), silicon carbide (SiC), low-k dielectric, and/or other materials. In one embodiment, the isolation regions104may be created by etching or otherwise forming a recess in the substrate102and subsequently filling with one or more layers of a dielectric.

The gate layer108, which may be gate oxide, is formed followed by the formation of the bulk gate electrode110, which may include a layer of polysilicon. In the present example, a hard mask layer111resides over the gate electrode110. The hard mask layer111is about 250 Angstroms in thickness (height, as shown inFIG. 2), and may include silicon nitride (SixNy), silicon dioxide (SiO2), silicon oxy-nitride (SiON), photoresist, and/or other materials.

At step14, doped regions106aare formed in the substrate102. In the present embodiment, the doped regions106aare lightly doped drain/source (LDD) regions that are implanted relatively shallow into the substrate102. The LDD regions106acan be created by CVD, PECVD, ALD, ion implantation, and/or other processing techniques. For example, the doped regions106amay be formed by growing a sacrificial oxide on the substrate102, opening a pattern for the location of the doped regions106aand then using a chained-implantation procedure. Alternatively, the doped regions106amay be formed by selective epitaxial growth (SEG).

For the sake of example, the doped regions106ainclude P-type impurities such as boron, boron fluoride, indium, and/or other materials. Formation of the P-type doped regions may include one or more diffusion, annealing, and/or electrical activation processes. A channel region120is thereby formed between the two doped regions106a. Continuing with the present example, the channel region120is a P-channel.

Liners112are then formed on the vertical (as illustrated inFIG. 2) sides of the gate electrode110. In the present embodiment, the liners112are L-shaped and include an oxide dielectric layer formed by CVD, PVD, ALD, PECVD, SEG, and/or other processing techniques. Spacers114are then formed on the sidewalls of the liners112. In the present embodiment, the spacers114are nitrogen based insulators, such as silicon nitride (SixNy). In alternate embodiments, the spacers114may include silicon oxide (SiO2), photoresist, and/or other polymers. In the present embodiment, the spacers114and the lower portion of the liners112are relatively wide, with a width s1of about 650 Angstroms.

Referring also toFIG. 3, at step16(ofFIG. 1), silicon recesses122are formed on either side of the spacers114. In the present example, selected portions of the doped regions106aare removed. The portions of the doped regions106alocated under the liners112and spacers114remain following the removal of the exposed portions of the doped regions106a. The exposed portions of the doped regions106amay be removed by silicon etch, chemical etch, plasma etch, or other appropriate method.

Referring also toFIG. 4, at step18(ofFIG. 1), an epi layer124is formed in the recesses122ofFIG. 3between the doped regions106aand the isolation regions104. The epi layer124may include silicon germanium (SiGe). Other embodiments include silicon carbide (SiC), and/or other epi materials. It is noted that in the present embodiment, SiGe does not accumulate on the hard mask111or on the spacers114. The epi layer124is used to make the microelectronic device101a “strained silicon” device.

Referring also toFIG. 5, at step20(ofFIG. 1), the spacers114are partially etched, forming “slim” spacers herein designated with the reference numeral114a. The slim spacers114aare shown having a width s2, which is less than the width s1(FIG. 2). The width s2of the slim spacers114amay be on the order of about 350 Angstroms. As a result, the lower portion of the liners112extend about 300 Angstroms (650−350=300 Angstroms) beyond the slim spacers114a. The slim spacers114amay be formed by chemical etch, dry etch, plasma etch, and/or other processing techniques. In one embodiment, the slim spacers114aare formed by a wet etch of phosphoric acid (H3PO4).

The hard mask111is also removed, either at the same time that the slim spacers114aare formed, or at a different time. The hard mask111may be removed by chemical etch, plasma etch, and/or other techniques. For example, the hard mask111may be removed by plasma etch, which may include an environment having reactants such as hydrochloric acid (HCl), hydrogen bromide (HBr), sulfur dioxide (SO2), sulfur hexafluoride (SF6), perfluorocarbons, and/or other gases.

Referring also toFIG. 6, at step22(ofFIG. 1), the doped regions106bare treated by a source drain implant204. The implant204may include ion implantation by conventional ion beam, plasma source ion immersion, plasma source ion implantation, and/or other processing techniques. In the present embodiment, the implant204may include P-type impurities. In other embodiments, the implant204may include impurities such as phosphorous, boron, antimony, arsenic, carbon, germanium, and/or other materials. In furtherance of the present example, the implant is heavier doped than the implant used to create the doped regions106a. It is understood that different dopants and/or different dopant concentrations can be used, as desired. Alternatively, the implant204may utilize thermal diffusion and/or formation of the doped regions106cby SEG, CVD, PVD, ALD, and/or other processing techniques.

The implant204is used to form a graded junction, which is illustrated by the creation of doped regions106a,106b,106cand106d. The doped region106bis a combination of the prior process used to create doped region106aand the implant204. If the prior process and the implant204use similar dopants, the doped region106bcan be comparatively heavier doped than the region106a. If dissimilar dopants are used, the doped region106bcan have a unique combination from the two process steps.

The doped region106d, in the present example, is deeper than the previous doped region106aofFIG. 5. In one embodiment, the implant204uses similar dopants of the prior process used to create doped region106a. In this embodiment, the doped region106dprovides a deeper grading affect. It is understood that although the grading effect is shown as a stair step inFIG. 6, in actuality the grading effect may be more gradual, or smoothed, as shown inFIG. 8.

The doped region106cis created by the implant204on the epi layer124. In the present example, the SiGe layer124allows the implant204to go deeper than that of the doped region106d. Furthermore, the resulting properties of the implant204on the SiGe layer124may be different than those on the Si substrate102used for the doped region102d. It is understood that in some embodiments, a portion of the implant204may extend beyond the epi layer124and further into the substrate102, or in the alternative, may not completely diffuse into the epi layer. It is further understood that although the grading effect is shown as a stair step inFIG. 6, in actuality the grading effect may be more gradual, or smoothed, as shown inFIG. 8.

Referring also toFIG. 7, at step24(ofFIG. 1) connections are provided to the gate, source, and drain of the transistor device101, and a clamping layer118is formed. In the present embodiment, the connections are made through a gate contact116and source/drain contacts126. The gate contact116may include a metal silicide such as cobalt silicide (CoSix), molybdenum silicide (MoSix), nickel silicide (NiSix), titanium silicide (TiSix), and/or other materials. The gate contact116may be formed by lithography, chemical etch, plasma etch, CVD, PECVD, ALD, PVD, and/or other processing techniques. Similarly, the source/drain contacts126may be include silicide formed in and/or over the doped region106c. The formation of the gate contact116and/or source/drain contacts126may also include an anneal process step.

The clamping layer118or “contact etch stop layer (CES)” may include openings positioned for the gate contact116. The clamping layer118may include silicon nitride (SixNy), silicon dioxide (SiO2), silicon oxy-nitride (SiON), silicon oxy-carbide (SiOC), silicon carbide (SiC), and/or other materials. In some embodiments, the clamping layer118may be located over the doped regions106band106cand include openings positioned for the source/drain contacts126.

The clamping layer118may also provide tensile stress and/or compressive stress which may influence the crystalline stress of the channel region120. The tensile stress of the clamping layer118may be controlled by the process parameters during the formation of the clamping layer118. Compressive stress may be induced into the clamping layer118and may also be controlled by the process parameters. In one embodiment, the clamping layer118compressive and/or tensile stress may also be adjusted by temperature, process gas flows, nitrogen content, and/or other process related parameters.

Upon completion of step24(ofFIG. 1), subsequent processing may be performed to form other features located over the gate contact116and the doped regions106c, which may include the formation of a metal silicide, a barrier layer such as tantalum nitride (TaN) or silicon oxy-carbide (SiOC), interconnects having copper (Cu) or aluminum (Al), low-k dielectric layers, and or other layers. In one embodiment, the microelectronic device101may be annealed thereby forming the “graded junction” between the doped regions106b,106a, and106c(similar to that shown inFIG. 8). The anneal may provide a smooth transition between the impurities of the doped regions106b,106a, and106c.

Referring toFIG. 8, in another embodiment, a complementary microelectronic circuit300(also referred to as complementary metal oxide semiconductor (CMOS) circuit) includes a substrate302, an isolation region304, microelectronic devices320and322, and clamping layers316a,316b, and316c. The CMOS circuit300can by created, in part, by using one or more steps of the method10ofFIG. 1. It is understood that other steps and/or layers may be created as needed, such is as well known to those of ordinary skill in the art.

The substrate302may include one or more of silicon, gallium arsenide, gallium nitride, strained silicon, silicon germanium, silicon carbide, carbide, diamond, and/or other materials. The substrate102may also include a silicon-on-insulator (SOI) substrate, such as a silicon-on-sapphire substrate, a silicon germanium-on-insulator substrate, or another substrate including an epitaxial semiconductor layer on an insulator layer. The substrate302may further include a fully depleted SOI substrate wherein the device active silicon thickness may range between about 200 nm and about 5 nm in one embodiment. In another embodiment, the substrate302may include an air gap to provide insulation for the microelectronic device300. For example, a “silicon-on-nothing” (SON) structure may be employed wherein the microelectronic device300includes a thin insulation layer formed by air and/or other insulator.

The isolation regions304may include shallow trench isolation (STI), local oxidation of silicon (LOCOS), and/or other electrical isolation features. The isolation regions104may include silicon dioxide (SiO2), silicon nitride (SixNy), silicon carbide (SiC), low-k dielectric, and/or other materials. In one embodiment, the isolation region(s)104may by etching or otherwise forming a recess in the substrate302and subsequently filling with one or more layers of a dielectric.

The microelectronic device devices320,322may also include one or more layers or other features contemplated by the microelectronic circuit300within the scope of the present disclosure, and may be formed by immersion photolithography, maskless lithography, imprint lithography, SEG, CVD, PVD, PECVD, ALD, Langmuir-Blodgett (LB) molecular assembly, chemical mechanical polishing or chemical mechanical planarization (hereafter referred to as CMP), and/or other processing techniques. Conventional and/or future-developed lithographic, etching and/or other processes may be employed to form the microelectronic device100.

The microelectronic devices320and/or322may include an N-type metal oxide semiconductor (NMOS) device and/or P-type metal oxide semiconductor (PMOS) device, respectively. The microelectronic devices320and322may include portions substantially similar to the discussions above with respect to the microelectronic device100. For example, gate layer308, liners312, spacers314, and bulk gate electrode310may be substantially similar in composition to the gate layer108, liners112, spacers114a, and the bulk gate electrode110discussed above.

In the present example, the device322was formed using an epi layer at the source/drain region, as is discussed above with reference toFIGS. 4–6. In contrast, the device320was not formed using an epi layer as described above. As a result, the device322includes a three-step graded formation of the dopant regions306a,306b,306c, and306d, while the device320includes a two-step graded formation of the dopant regions306a,306b, and306d. It is understood that since the devices320,322are not of the same type, different dopants can be used to form the layers306a–306d, such selection of dopants being well understood by those of ordinary skill in the art.

It is generally understood that different embodiments will see different benefits. For example, in some embodiments, a significant current gain will be observed over prior art devices, as well as a lower junction capacitance. Some prior art devices can only provide higher drive current with a higher junction capacitance. This improvement can occur, in some embodiments, without a significant change in threshold voltage.

The foregoing has outlined features of several embodiments according to aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. For example, there are many know ways to form a layer or structure, including deposition, diffusion, implantation, etching, growing, and so forth. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.