Process variation tolerant sense amplifier flop design

One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate generally to integrated circuit sense amplifier design and more specifically to a process variation tolerant sense amplifier flop design.

2. Description of the Related Art

Integrated circuits frequently employ certain common system building block circuits, such as logic gates, memories blocks, and other specialty circuits to construct the overall system functionality of a given integrated circuit. Process variation associated with the manufacture of integrated circuits generally imparts some variation in the operation of the individual circuit elements as well as larger circuit structures within a given integrated circuit. For example, if the fabrication of a given complementary-symmetry metal-oxide semiconductor (CMOS) wafer results in highly resistive (“slow”) p-channel field-effect transistors (P-FETs), then circuits that incorporate P-FETs will tend to be characterized by slow positive-going voltage slew rates relative to circuits fabricated on wafers that include highly conductive (“fast”) P-FETs. Process variation in n-channel field-effect transistors (N-FETs) has a similar effect in pull-down performance.

Certain types of CMOS circuits, such as conventional combinational logic gate circuits, tend to be highly robust in maintaining correct function when subjected to process variation. For example, many static logic gate circuits produce correct output values over a very wide range of process variation, with only the input to output propagation delays and output slew rates being significantly impacted by process variation. However, many types of specialty circuits commonly used in CMOS integrated circuits generally require relatively well bounded process variation to function correctly. These specialty circuits offer a very efficient implementation of a specific building block function, but certain classes of these specialty circuits malfunction catastrophically with sufficient process variation.

One type of specialty circuit is a flop-flop (or just “flop”) based on a differential sense amplifier structure. Conventional sense amplifier flop designs offer certain benefits over alternative design regimes. However, the differential structure commonly employed in the sense amplifier flop design is typically sensitive to process variation. In fact, conventional sense amplifier flop designs are prone to malfunctions due to process variation. Specifically, these differential structures require a bounded conductivity ratio between N-FETs and P-FETs within a given integrated circuit. This conductivity ratio is dictated by the process outcome for a given wafer. When the process outcome for a given wafer produces a conductivity ratio that is out of bounds for at least one sense amplifier flop within an integrated circuit on the wafer, all integrated circuits fabricated on the wafer are likely to malfunction and fail manufacturing tests, resulting in a complete loss the wafer. When a set of different integrated circuits incorporates a sense amplifier flop design that may be highly sensitive to process variation, every instance of the sense amplifier flop in every different integrated circuit design may be highly susceptible to failure, resulting in a costly overall loss of yield over many different designs and many different wafers.

One approach to improve sense amplifier flop reliability is to tighten process variation requirements on host wafers. However, such an approach tends to involve significant expense in the fabrication process and inherent yield loss during wafer sorting and qualification testing.

As the foregoing illustrates, what is needed in the art is a high-performance sense amplifier flop design that is substantially insensitive to process variation.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a process variation tolerant sense amplifier flip-flop circuit. The circuit has a differential subsystem that includes a first path to ground, a second path to ground, a third path to ground, and a fourth path to ground, and a control subsystem configured to control the second path to ground via a first N-channel field effect transistor (N-FET) and the third path to ground via a second N-FET, where the second path to ground or the third path to ground is enabled based on a delayed representation of an input data signal produced by the control subsystem.

One advantage of the disclosed circuit is that it eliminates short-circuit currents between N-FETs and P-channel field effect transistors (P-FETs) by specifically staging transitions within the sense amplifier flop. By avoiding short-circuit currents within the flop, the need to tightly control N-FET versus P-FET conductivity is substantially reduced, thereby increasing overall tolerance of process variation.

DETAILED DESCRIPTION

FIG. 1, illustrates the input/output ports of a sense amplifier flop110with scan-in and scan enable inputs, according to one embodiment of the invention. From an external port perspective, the sense amplifier flop110behaves as a generic flip-flop. Persons skilled in the art will understand that a clock signal, CLK126, determines when the sense amplifier flop110samples a data signal, D120. A transition from a logic “0” to a logic “1” on CLK126causes a sense amplifier flop110that is positive-edge triggered to sample and hold the logic level present on D120at the time of the positive edge on CLK126. The sampled value for D120is held on output Q140. When the scan enable input SE124is asserted (logical “1”), the sense amplifier flop110samples data from the scan in, SI122, rather than the data input D120. In both cases, the sampled data is presented on output Q140.

FIG. 2Aillustrates the circuit design of a process variation tolerant sense amplifier flop200with scan-in and scan-enable inputs, according to one embodiment of the invention. The process variation tolerant sense amplifier flop200, or simply “flop”200, includes four inputs and one output. The four inputs include a clock input (CLK126, fromFIG. 1), operational data input (D120), scan data input (SI122), and scan enable input (SE124). As described inFIG. 1, flop200generates a data output signal (Q140), which is an edge-sampled copy of input D120.

For each input signal D120, SI122, and SE124, a corresponding negative sense or “inverted” signal is generated. Input D120is inverted by inverter280to generate DN270, a negated version of D120. Input SI122is inverted by inverter281to generate SIN272, a negated version of SI122. Input SE124is inverted by inverter282to generate SEN274, a negated version of SE124.

N-FETs203,204,205, and206form a first pull-down path through a differential structure, while N-FETs209,210,211, and212form a second pull-down path through the differential structure. Within the first pull-down path, either N-FETs203and204or N-FETs205and206may be active at the same time. Within the second pull-down path, either N-FETs209and210or N-FETs211and213may be active at the same time. In a first scenario where SE124is inactive (logic level “0”), then input D120is selected as the source of input data to the flop200. In this first scenario, SEN274is driven to active (logic level “1”) by inverter282and N-FETs203and211are turned on. At the same time, N-FETs205and209are turned off. Therefore, when SE124is inactive, a “1” applied to D120turns on N-FET204, completing a conductive path from node “a”266to VGND261. Instead, if SE124is inactive and a “0” is applied to D120, then DN270is driven to a “1” by inverter280, thereby turning on N-FET212and completing a conductive path from node “b”267to VGND261. In a second scenario where SE124is active (logic level “1”), then input SI122(scan input) is selected as the source of input data to the flop200. In this second scenario, SEN274is driven to inactive (logic level “0”) by inverter282and N-FETs203and211are turned off. At the same time N-FETs205and209are turned on. Therefore, when SE is active, a “1” applied to SI122turns on N-FET206, completing a conductive path from node “a”266to VGND261. Instead, if SE124is active and a “0” is applied to SI122, then SIN272is driven to a “1” by inverter281, thereby turning on N-FET210and completing a conductive path from node “b”267to VGND261. In both scenarios, nodes “a”266and “b”267each form a portion of a pull-down path from node “m1”276and node “m”277, respectively.

N-FETs201and207each complete one of the two pull-down paths from “m1”276and “m”277to “a”266and “b”267, respectively. N-FET201and P-FET222form a first inverter structure, with output node “m1”276and input node “m”277. N-FET207and P-FET224form a second inverter structure, with output node “m”277and input node “m1”276. The first and second inverter structures form a cross-coupled latch, with node “a”266, node “b”267, or neither providing a pull-down path. When turned on, P-FETs221and223are configured to pull nodes “m1”276and “m”277, respectively, to VDD262(logic “1”), overriding any residual state on nodes “m1”276and “m”277.

N-FET202is configured to pull node “a”266to VGND261when node “m1_n”279is driven to a “1” by inverter285, which is controlled by node “m1”276. N-FET208is configured to pull node “b”267to VGND261when node “m_n”278is driven to a “1” by inverter286, which is controlled by node “m”277.

Inverter285drives node “m1_n”279with a delayed, inverted representation of the value on node “m1”276. When node “m1_n”279is driven to a “1,” N-FETs202and214are turned on and P-FET227is turned off. Otherwise, when node “m1_n”279is driven to a “0,” N-FETs202and214are turned off and P-FET227is turned on. Inverter286drives node “m_n”278with a delayed, inverted representation of the value on node “m”277. When node “m_n”278is driven to a “1,” N-FET208is turned on. Otherwise, when node “m_n”278is driven to a “0,” N-FET208is turned off.

A buffered output latch structure is formed by P-FETs225,226,227, N-FETs214,215,216, and inverters283and284. P-FETs227,226and N-FETs215,216form a first gated inverter structure, which is cross-coupled with inverter284to form a latch element. Inverter283inverts and buffers the value stored within the latch element to generate output Q140from flop200.

In normal operation, clock input CLK126toggles between logic “0” and logic “1.” When CLK126is driven with “0,” the flop200is in a “pre-charge” state, illustrated below inFIG. 2B. When CLK126initially swings from “0” to “1,” the flop200enters an initial evaluation state, illustrated below inFIG. 2C. After the initial evaluation state, the flop200proceeds into a mid-way evaluation state, illustrated inFIG. 2D. Once the states within the flop200have settled, the flop200enters a final evaluation state, illustrated inFIG. 2E.

FIGS. 2B through 2Eillustrate a scenario where CLK126is initially driven to “0,” Q140is driving a “0,” and D120is driven to “1.” This scenario illustrates the internal operation of the flop200while sampling a “1” on input data node D120and transitioning output node Q140from “0” to “1,” to reflect the value of the newly sampled input data. N-FET and P-FET devices inFIGS. 2B through 2Ethat are turned on are shown bolded, while the remaining N-FET and P-FET devices are turned off.

FIG. 2Billustrates pre-charge states of field-effect transistor devices within the process variation tolerant sense amplifier flop200, according to one embodiment of the invention. Clock input CLK126is driven with a “0,” causing N-FET213to turn off and P-FETs221and223to turn on. In this state, P-FET221pulls node “m1”276to VDD262, causing N-FET207to turn on. Similarly, P-FET223pulls node “m”277to VDD262, causing N-FET201to turn on. With “m1”276pulled to VDD262, inverter285drives “m1_n”279to a logic “0,” thereby turning on P-FET227and providing P-FET226a pull-up path to VDD262. P-FET226pulls node “qn”268to logic “1” through P-FET227, causing inverter283to drive Q140to the currently stored valued of “0.” With “m”277pulled up, N-FET216is also turned on. However, N-FET215is not turned on, so there is no current running through N-FETs215or216.

The scan enable input, SE124, is disabled with a “0” input, causing inverter282to drive SEN274with a “1,” which turns on N-FETs203and211. D120is driven with a “1,” causing N-FET204to turn on.

FIG. 2Cillustrates initial evaluation states of field-effect transistor devices within the process variation tolerant sense amplifier flop200, according to one embodiment of the invention. During initial evaluation, the clock input CLK126is driven with a “1,” causing N-FET213to turn on and P-FETs221and223to turn off.

At his point, P-FETs221and223are no longer pulling-up nodes “m1”276and “m”277. Either “m1”276or “m”277may be subsequently pulled down by either N-FET201or N-FET207, respectively. At this point, the scan enable input, SE124, continues to be disabled with a “0” input, causing inverter282to drive SEN274with “1,” which turns on N-FETs203and211. Furthermore, D120continues to be driven with a “1,” causing N-FET204to turn on. This specific configuration of device state creates a conductive path from GND260(logic “0”) to node “m1”276, which causes “m1”276to discharge to GND260, while leaving node “m”277charged to VDD262. Importantly, there is no pull-up activity on node “m1”276from either P-FET221or P-FET222at this point. Pull-up current from either P-FET221or P-FET222would be process variation dependent and could result in a malfunction of flop200if the P-FET pull-up current overpowered the pull-down current through N-FETs201,203,204and213. Additionally, only N-FET201or N-FET207may be turned on at a given time, enabling only one selected path through the differential structure from VDD262to GND260. This is in contrast to prior art designs, which typically allow two or more paths through a differential structure to be enabled simultaneously, leading to greater process variation sensitivity.

FIG. 2Dillustrates mid-way evaluation states of field-effect transistor devices within the process variation tolerant sense amplifier flop200, according to one embodiment of the invention. During mid-way evaluation, the clock input CLK126remains driven with a “1,” keeping N-FET213turned on P-FETs221and223turned off. Additionally, the “0” on “m1”276causes P-FET224to turn on, holding “m”277in a “1” state.

During mid-way evaluation, inverter285propagates the “1” to “0” transition on “m1”276as a “0” to “1” transition on “m1_n”279. The “1” on “m1_n”279causes ID-FET277to turn off and N-FETs202and214to turn on. As N-FET214begins to turn on, a conductive path is formed from node “qn”268to GND260, causing “qn”268to be pulled to “0.” Importantly, P-FET227is turned off prior to N-FET214being turned on, eliminating any short-circuit current scenario where the process-dependent conductivity ratio between P-FET227and N-FET214needs to be tightly bounded for correct circuit function.

FIG. 2Eillustrates final evaluation states of field-effect transistor devices within the process variation tolerant sense amplifier flop200, according to one embodiment of the invention. During final evaluation, the clock input CLK126remains driven with a “1,” keeping N-FET213turned on P-FETs221and223turned off. Additionally, the “0” on “m1”276causes P-FET224to remain on, holding “m”277in a “1” state.

During final evaluation, the “0” on “qn”268causes inverter284to propagate a “1” to the gate of P-FET226and the gate of N-FET215, causing P-FET226to turn off and N-FET215to turn on. With the transition of node “qn”268from a “1” to a “0,” inverter283drives output Q140from a “0” to a “1,” reflecting the sampled input value on D120.

FIG. 3illustrates the relative timing of certain nodes within a process variation tolerant sense amplifier flop200, according to one embodiment of the invention. The external nodes CLK126, D120, and Q140are shown, along with internal nodes “m”277, “m1”276, “m1_n”279and “q_n”268. A transition in one signal may cause a transition in a second signal, with the causal relationship illustrated as an arc from the first signal to the second signal. When input CLK126is driven to “0,” the flop200is in a pre-charge state, as described inFIG. 2B. When CLK transitions from a “0” to a “1,” the flop200passes through the evaluation states described inFIGS. 2C through 2E.

As shown in this scenario, Q140is initially in a “0” state. At a first rising edge of CLK126, flop200samples the “1” on input D120. A propagation time later, the sampled value “1” is driven on output Q140. At a second rising edge of CLK126, flop200samples the “0” on input D120. A propagation time later, the sampled value “0” is driven on output Q140.

As previously discussed inFIG. 2B, a “0” on CLK126causes the flop200to enter a pre-charge state, with nodes “m”277and “m1”276being pulled up by P-FETS223and221, respectively. Therefore, a falling edge310on CLK126results in a rising edge312on “m”277. Node “m1”276is already in a “1” state and remains in the “1” state immediately after the falling edge310. Some time after the falling edge310, D120transitions from a “0” to a “1” in preparation to be sampled by flop200when a rising edge320arrives on CLK126. Just prior to rising edge320, both “m”277and “m1”276are pre-charged to “1.” However, just after rising edge320, “m1” is pulled down by a conductive path through N-FETs201,203,204, and213. If, instead, D120was driven to “0,” node “m”277would be pulled down through N-FETs207,211,212, and213and node “m1”276would remain in a “1” state.

With “m1” pulled down to “0,” negative edge322is inverted through inverter285to generate positive edge324on node “m1_n”279. Positive edge324causes N-FET214to turn on and pull down node “q_n”268, resulting in negative edge326. Importantly, N-FET214encounters no completing pull-up activity from either P-FET225or P-FETs226and227while pulling node “q_n”268down to “0.” Negative edge326is inverted by inverter283, which generates a positive edge328on Q140.

A subsequent falling edge330of CLK126causes a rising edge332on node “m1”276as both “m1”276and “m”277are pulled up to VDD262. Rising edge332is inverted by inverter285, resulting in a negative edge334on node “m1_n”279.

A second rising edge340on CLK126results in node “m”277being discharged to “0,” through N-FETs207,211,212and213. As node “m”277is discharged to “0,” P-FET225is turned on, pulling node “q_n”268to “1,” resulting in positive edge344. Positive edge344is inverted by inverter283, resulting in negative edge346on output Q140. A subsequent negative edge350on CLK126causes node “m”277to be pulled up, resulting in positive edge352, as flop200enters the pre-charge state.

FIG. 4depicts an integrated circuit400, in which one or more aspects of the invention may be implemented. The integrated circuit400includes input/output circuits410,412,414and416. The integrated circuit400also includes combinational logic420, and storage circuitry422. The combinational logic420receives signals450and452as inputs and generates signals454,456as outputs. The storage circuitry422receives signals454as inputs and stores certain values from the input signals454. The storage circuitry422presents certain stored values as outputs on signals452. In one embodiment, an instance of the sense amplifier flop200ofFIG. 2is instantiated within the storage circuitry422as a sense amplifier flop424.

In sum, a sense amplifier flop design is disclosed that eliminates short-circuit currents between N-FETs and P-FETs by specifically staging transitions within the sense amplifier flop. By avoiding short-circuit currents within the flop, the need to tightly control N-FET versus P-FET conductivity is substantially reduced, thereby increasing overall tolerance of process variation.

While the forgoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. For example, aspects of the present invention may be implemented in complementary symmetry metal-oxide semiconductor (CMOS) fabrication technology or other related fabrication technologies. Therefore, the scope of the present invention is determined by the claims that follow.