Interconnection scheme for reconfigurable neuromorphic hardware

Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

FIELD OF THE INVENTION

The present disclosure pertains to the field of processing logic, reconfigurable neuromorphic processors, microprocessors, and associated instruction set architecture that, when executed by the processor or other processing logic, perform logical, mathematical, or other functional operations.

DESCRIPTION OF RELATED ART

A neuromorphic processor may be used (alone or in conjunction with another type of processor) to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. For example, neuromorphic processors may allow systems to perform face recognition, to extract information from large data sets, and to perform object detection tasks that may be beyond of the scope of traditionally programmed solutions. Neuromorphic processors may provide a path to computational intelligence by allowing machines to learn features from training data, when programming features in explicitly becomes too complex.

A neuromorphic processor may operate in a manner similar to biological neural networks (such as a central nervous system of an animal). Specifically, a neuromorphic processor may include a network of interconnected “neurons” that may exchange data between one another. Each connection between a neuron may be referred to as a “synapse.” A neuron may have one output that may fan out to one or more synapses. At each synapse, the output of a neuron may be multiplied by a synapse weight. This weighted output of a neuron may be transmitted via the one or more synapses to an input of one or more neurons. Neurons may sum (or integrate) these received inputs. When this sum (referred to as a “membrane potential”) exceeds a threshold value, a neuron may generate an output (or “fire”) from the neuron using a transfer function such as a sigmoid or threshold function. That output may then be passed via one or more synapses to one or more neurons as an input. Once a neuron fires, it may disregard previously received input information, thereby resetting the neuron.

A synapse weight may be selected, modified, or adjusted, making neural nets adaptive to inputs and capable of learning. Accordingly, a neuromorphic processor may not require a setup program, but rather may be a learning architecture that may be trained through iterative adjustment of synapse weights.

DETAILED DESCRIPTION

The following description describes a reconfigurable neuromorphic processor. A reconfigurable neuromorphic processor may operate alone or in conjunction with another processor. In the following description, numerous specific details such as processing logic, processor types, micro-architectural conditions, events, enablement mechanisms, and the like are set forth in order to provide a more thorough understanding of embodiments of the present disclosure. It will be appreciated, however, by one skilled in the art that the embodiments may be practiced without such specific details. Additionally, some well-known structures, circuits, and the like have not been shown in detail to avoid unnecessarily obscuring embodiments of the present disclosure.

Although the following embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present disclosure may be applied to other types of circuits or semiconductor devices that may benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present disclosure are applicable to any processor or machine that performs data manipulations. However, the embodiments are not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit, or 16-bit data operations and may be applied to any processor and machine in which manipulation or management of data may be performed. In addition, the following description provides examples, and the accompanying drawings show various examples for the purposes of illustration. However, these examples should not be construed in a limiting sense as they are merely intended to provide examples of embodiments of the present disclosure rather than to provide an exhaustive list of all possible implementations of embodiments of the present disclosure.

Although the below examples describe instruction handling and distribution in the context of execution units and logic circuits, other embodiments of the present disclosure may be accomplished by way of a data or instructions stored on a machine-readable, tangible medium, which when performed by a machine cause the machine to perform functions consistent with at least one embodiment of the disclosure. In one embodiment, functions associated with embodiments of the present disclosure are embodied in machine-executable instructions. The instructions may be used to cause a general-purpose or special-purpose processor that may be programmed with the instructions to perform the steps of the present disclosure. Embodiments of the present disclosure may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to embodiments of the present disclosure. Furthermore, steps of embodiments of the present disclosure might be performed by specific hardware components that contain fixed-function logic for performing the steps, or by any combination of programmed computer components and fixed-function hardware components.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as may be useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, designs, at some stage, may reach a level of data representing the physical placement of various devices in the hardware model. In cases wherein some semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. A memory or a magnetic or optical storage such as a disc may be the machine-readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or retransmission of the electrical signal is performed, a new copy may be made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

In modern processors, a number of different execution units may be used to process and execute a variety of code and instructions. Some instructions may be quicker to complete while others may take a number of clock cycles to complete. The faster the throughput of instructions, the better the overall performance of the processor. Thus it would be advantageous to have as many instructions execute as fast as possible. However, there may be certain instructions that have greater complexity and require more in terms of execution time and processor resources, such as floating point instructions, load/store operations, data moves, etc.

As more computer systems are used in internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures, including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O).

In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures, which may include processor logic and circuits used to implement one or more instruction sets. Accordingly, processors with different micro-architectures may share at least a portion of a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or adopters, may share at least a portion a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using new or well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file. In one embodiment, registers may include one or more registers, register architectures, register files, or other register sets that may or may not be addressable by a software programmer.

An instruction may include one or more instruction formats. In one embodiment, an instruction format may indicate various fields (number of bits, location of bits, etc.) to specify, among other things, the operation to be performed and the operands on which that operation will be performed. In a further embodiment, some instruction formats may be further defined by instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields and/or defined to have a given field interpreted differently. In one embodiment, an instruction may be expressed using an instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and specifies or indicates the operation and the operands upon which the operation will operate.

Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation) may require the same operation to be performed on a large number of data items. In one embodiment, Single Instruction Multiple Data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data elements. SIMD technology may be used in processors that may logically divide the bits in a register into a number of fixed-sized or variable-sized data elements, each of which represents a separate value. For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand containing four separate 16-bit data elements, each of which represents a separate 16-bit value. This type of data may be referred to as ‘packed’ data type or ‘vector’ data type, and operands of this data type may be referred to as packed data operands or vector operands. In one embodiment, a packed data item or vector may be a sequence of packed data elements stored within a single register, and a packed data operand or a vector operand may a source or destination operand of a SIMD instruction (or ‘packed data instruction’ or a ‘vector instruction’). In one embodiment, a SIMD instruction specifies a single vector operation to be performed on two source vector operands to generate a destination vector operand (also referred to as a result vector operand) of the same or different size, with the same or different number of data elements, and in the same or different data element order.

SIMD technology, such as that employed by the Intel® Core™ processors having an instruction set including x86, MMX™, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, ARM processors, such as the ARM Cortex® family of processors having an instruction set including the Vector Floating Point (VFP) and/or NEON instructions, and MIPS processors, such as the Loongson family of processors developed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences, has enabled a significant improvement in application performance (Core™ and MMX™ are registered trademarks or trademarks of Intel Corporation of Santa Clara, Calif.).

In one embodiment, destination and source registers/data may be generic terms to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memory, or other storage areas having other names or functions than those depicted. For example, in one embodiment, “DEST1” may be a temporary storage register or other storage area, whereas “SRC1” and “SRC2” may be a first and second source storage register or other storage area, and so forth. In other embodiments, two or more of the SRC and DEST storage areas may correspond to different data storage elements within the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers may also act as a destination register by, for example, writing back the result of an operation performed on the first and second source data to one of the two source registers serving as a destination registers.

FIG. 1Ais a block diagram of an exemplary computer system formed with a processor that may include execution units to execute an instruction, in accordance with embodiments of the present disclosure. System100may include a component, such as a processor102to employ execution units including logic to perform algorithms for process data, in accordance with the present disclosure, such as in the embodiment described herein. System100may be representative of processing systems based on the PENTIUM® III, PENTIUM® 4, Xeon™, Itanium®, XScale™ and/or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In one embodiment, sample system100may execute a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Embodiments of the present disclosure may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

Computer system100may include a processor102that may include one or more execution units108to perform an algorithm to perform at least one instruction in accordance with one embodiment of the present disclosure. One embodiment may be described in the context of a single processor desktop or server system, but other embodiments may be included in a multiprocessor system. System100may be an example of a ‘hub’ system architecture. System100may include a processor102for processing data signals. Processor102may include a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In one embodiment, processor102may be coupled to a processor bus110that may transmit data signals between processor102and other components in system100. The elements of system100may perform conventional functions that are well known to those familiar with the art.

In one embodiment, processor102may include a Level 1 (L1) internal cache memory104. Depending on the architecture, the processor102may have a single internal cache or multiple levels of internal cache. In another embodiment, the cache memory may reside external to processor102. Other embodiments may also include a combination of both internal and external caches depending on the particular implementation and needs. Register file106may store different types of data in various registers including integer registers, floating point registers, status registers, and instruction pointer register.

Execution unit108, including logic to perform integer and floating point operations, also resides in processor102. Processor102may also include a microcode (ucode) ROM that stores microcode for certain macroinstructions. In one embodiment, execution unit108may include logic to handle a packed instruction set109. By including the packed instruction set109in the instruction set of a general-purpose processor102, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor102. Thus, many multimedia applications may be accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

Embodiments of an execution unit108may also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System100may include a memory120. Memory120may be implemented as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, flash memory device, or other memory device. Memory120may store instructions and/or data represented by data signals that may be executed by processor102.

A system logic chip116may be coupled to processor bus110and memory120. System logic chip116may include a memory controller hub (MCH). Processor102may communicate with MCH116via a processor bus110. MCH116may provide a high bandwidth memory path118to memory120for instruction and data storage and for storage of graphics commands, data and textures. MCH116may direct data signals between processor102, memory120, and other components in system100and to bridge the data signals between processor bus110, memory120, and system I/O122. In some embodiments, the system logic chip116may provide a graphics port for coupling to a graphics controller112. MCH116may be coupled to memory120through a memory interface118. Graphics card112may be coupled to MCH116through an Accelerated Graphics Port (AGP) interconnect114.

System100may use a proprietary hub interface bus122to couple MCH116to I/O controller hub (ICH)130. In one embodiment, ICH130may provide direct connections to some I/O devices via a local I/O bus. The local I/O bus may include a high-speed I/O bus for connecting peripherals to memory120, chipset, and processor102. Examples may include the audio controller, firmware hub (flash BIOS)128, wireless transceiver126, data storage124, legacy I/O controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and a network controller134. Data storage device124may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

For another embodiment of a system, an instruction in accordance with one embodiment may be used with a system on a chip. One embodiment of a system on a chip comprises of a processor and a memory. The memory for one such system may include a flash memory. The flash memory may be located on the same die as the processor and other system components. Additionally, other logic blocks such as a memory controller or graphics controller may also be located on a system on a chip.

FIG. 1Billustrates a data processing system140which implements the principles of embodiments of the present disclosure. It will be readily appreciated by one of skill in the art that the embodiments described herein may operate with alternative processing systems without departure from the scope of embodiments of the disclosure.

Computer system140comprises a processing core159for performing at least one instruction in accordance with one embodiment. In one embodiment, processing core159represents a processing unit of any type of architecture, including but not limited to a CISC, a RISC or a VLIW-type architecture. Processing core159may also be suitable for manufacture in one or more process technologies and by being represented on a machine-readable media in sufficient detail, may be suitable to facilitate said manufacture.

Processing core159comprises an execution unit142, a set of register files145, and a decoder144. Processing core159may also include additional circuitry (not shown) which may be unnecessary to the understanding of embodiments of the present disclosure. Execution unit142may execute instructions received by processing core159. In addition to performing typical processor instructions, execution unit142may perform instructions in packed instruction set143for performing operations on packed data formats. Packed instruction set143may include instructions for performing embodiments of the disclosure and other packed instructions. Execution unit142may be coupled to register file145by an internal bus. Register file145may represent a storage area on processing core159for storing information, including data. As previously mentioned, it is understood that the storage area may store the packed data might not be critical. Execution unit142may be coupled to decoder144. Decoder144may decode instructions received by processing core159into control signals and/or microcode entry points. In response to these control signals and/or microcode entry points, execution unit142performs the appropriate operations. In one embodiment, the decoder may interpret the opcode of the instruction, which will indicate what operation should be performed on the corresponding data indicated within the instruction.

Processing core159may be coupled with bus141for communicating with various other system devices, which may include but are not limited to, for example, Synchronous Dynamic Random Access Memory (SDRAM) control146, Static Random Access Memory (SRAM) control147, burst flash memory interface148, Personal Computer Memory Card International Association (PCMCIA)/Compact Flash (CF) card control149, Liquid Crystal Display (LCD) control150, Direct Memory Access (DMA) controller151, and alternative bus master interface152. In one embodiment, data processing system140may also comprise an I/O bridge154for communicating with various I/O devices via an I/O bus153. Such I/O devices may include but are not limited to, for example, Universal Asynchronous Receiver/Transmitter (UART)155, Universal Serial Bus (USB)156, Bluetooth wireless UART157and I/O expansion interface158.

One embodiment of data processing system140provides for mobile, network and/or wireless communications and a processing core159that may perform SIMD operations including a text string comparison operation. Processing core159may be programmed with various audio, video, imaging and communications algorithms including discrete transformations such as a Walsh-Hadamard transform, a fast Fourier transform (FFT), a discrete cosine transform (DCT), and their respective inverse transforms; compression/decompression techniques such as color space transformation, video encode motion estimation or video decode motion compensation; and modulation/demodulation (MODEM) functions such as pulse coded modulation (PCM).

FIG. 1Cillustrates other embodiments of a data processing system that performs SIMD text string comparison operations. In one embodiment, data processing system160may include a main processor166, a SIMD coprocessor161, a cache memory167, and an input/output system168. Input/output system168may optionally be coupled to a wireless interface169. SIMD coprocessor161may perform operations including instructions in accordance with one embodiment. In one embodiment, processing core170may be suitable for manufacture in one or more process technologies and by being represented on a machine-readable media in sufficient detail, may be suitable to facilitate the manufacture of all or part of data processing system160including processing core170.

In one embodiment, SIMD coprocessor161comprises an execution unit162and a set of register files164. One embodiment of main processor165comprises a decoder165to recognize instructions of instruction set163including instructions in accordance with one embodiment for execution by execution unit162. In other embodiments, SIMD coprocessor161also comprises at least part of decoder165to decode instructions of instruction set163. Processing core170may also include additional circuitry (not shown) which may be unnecessary to the understanding of embodiments of the present disclosure.

In operation, main processor166executes a stream of data processing instructions that control data processing operations of a general type including interactions with cache memory167, and input/output system168. Embedded within the stream of data processing instructions may be SIMD coprocessor instructions. Decoder165of main processor166recognizes these SIMD coprocessor instructions as being of a type that should be executed by an attached SIMD coprocessor161. Accordingly, main processor166issues these SIMD coprocessor instructions (or control signals representing SIMD coprocessor instructions) on the coprocessor bus166. From coprocessor bus166, these instructions may be received by any attached SIMD coprocessors. In this case, SIMD coprocessor161may accept and execute any received SIMD coprocessor instructions intended for it.

Data may be received via wireless interface169for processing by the SIMD coprocessor instructions. For one example, voice communication may be received in the form of a digital signal, which may be processed by the SIMD coprocessor instructions to regenerate digital audio samples representative of the voice communications. For another example, compressed audio and/or video may be received in the form of a digital bit stream, which may be processed by the SIMD coprocessor instructions to regenerate digital audio samples and/or motion video frames. In one embodiment of processing core170, main processor166, and a SIMD coprocessor161may be integrated into a single processing core170comprising an execution unit162, a set of register files164, and a decoder165to recognize instructions of instruction set163including instructions in accordance with one embodiment.

FIG. 2is a block diagram of the micro-architecture for a processor200that may include logic circuits to perform instructions, in accordance with embodiments of the present disclosure. In some embodiments, an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment, in-order front end201may implement a part of processor200that may fetch instructions to be executed and prepares the instructions to be used later in the processor pipeline. Front end201may include several units. In one embodiment, instruction prefetcher226fetches instructions from memory and feeds the instructions to an instruction decoder228which in turn decodes or interprets the instructions. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine may execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, trace cache230may assemble decoded uops into program ordered sequences or traces in uop queue234for execution. When trace cache230encounters a complex instruction, microcode ROM232provides the uops needed to complete the operation.

Some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, decoder228may access microcode ROM232to perform the instruction. In one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder228. In another embodiment, an instruction may be stored within microcode ROM232should a number of micro-ops be needed to accomplish the operation. Trace cache230refers to an entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from micro-code ROM232. After microcode ROM232finishes sequencing micro-ops for an instruction, front end201of the machine may resume fetching micro-ops from trace cache230.

Out-of-order execution engine203may prepare instructions for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler202, slow/general floating point scheduler204, and simple floating point scheduler206. Uop schedulers202,204,206, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. Fast scheduler202of one embodiment may schedule on each half of the main clock cycle while the other schedulers may only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files208,210may be arranged between schedulers202,204,206, and execution units212,214,216,218,220,222,224in execution block211. Each of register files208,210perform integer and floating point operations, respectively. Each register file208,210, may include a bypass network that may bypass or forward just completed results that have not yet been written into the register file to new dependent uops. Integer register file208and floating point register file210may communicate data with the other. In one embodiment, integer register file208may be split into two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. Floating point register file210may include 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

Execution block211may contain execution units212,214,216,218,220,222,224. Execution units212,214,216,218,220,222,224may execute the instructions. Execution block211may include register files208,210that store the integer and floating point data operand values that the micro-instructions need to execute. In one embodiment, processor200may comprise a number of execution units: address generation unit (AGU)212, AGU214, fast Arithmetic Logic Unit (ALU)216, fast ALU218, slow ALU220, floating point ALU222, floating point move unit224. In another embodiment, floating point execution blocks222,224, may execute floating point, MMX, SIMD, and SSE, or other operations. In yet another embodiment, floating point ALU222may include a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro-ops. In various embodiments, instructions involving a floating point value may be handled with the floating point hardware. In one embodiment, ALU operations may be passed to high-speed ALU execution units216,218. High-speed ALUs216,218may execute fast operations with an effective latency of half a clock cycle. In one embodiment, most complex integer operations go to slow ALU220as slow ALU220may include integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations may be executed by AGUs212,214. In one embodiment, integer ALUs216,218,220may perform integer operations on 64-bit data operands. In other embodiments, ALUs216,218,220may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. Similarly, floating point units222,224may be implemented to support a range of operands having bits of various widths. In one embodiment, floating point units222,224, may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, uops schedulers202,204,206, dispatch dependent operations before the parent load has finished executing. As uops may be speculatively scheduled and executed in processor200, processor200may also include logic to handle memory misses. If a data load misses in the data cache, there may be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations might need to be replayed and the independent ones may be allowed to complete. The schedulers and replay mechanism of one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

The term “registers” may refer to the on-board processor storage locations that may be used as part of instructions to identify operands. In other words, registers may be those that may be usable from the outside of the processor (from a programmer's perspective). However, in some embodiments registers might not be limited to a particular type of circuit. Rather, a register may store data, provide data, and perform the functions described herein. The registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store 32-bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data. For the discussions below, the registers may be understood to be data registers designed to hold packed data, such as 64-bit wide MMX™ registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. These MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point may be contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

FIGS. 3-5may illustrate exemplary systems suitable for including processor300, whileFIG. 4may illustrate an exemplary System on a Chip (SoC) that may include one or more of cores302. Other system designs and implementations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, DSPs, graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, may also be suitable. In general, a huge variety of systems or electronic devices that incorporate a processor and/or other execution logic as disclosed herein may be generally suitable.

FIG. 4illustrates a block diagram of a system400, in accordance with embodiments of the present disclosure. System400may include one or more processors410,415, which may be coupled to Graphics Memory Controller Hub (GMCH)420. The optional nature of additional processors415is denoted inFIG. 4with broken lines.

Each processor410,415may be some version of processor300. However, it should be noted that integrated graphics logic and integrated memory control units might not exist in processors410,415.FIG. 4illustrates that GMCH420may be coupled to a memory440that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

GMCH420may be a chipset, or a portion of a chipset. GMCH420may communicate with processors410,415and control interaction between processors410,415and memory440. GMCH420may also act as an accelerated bus interface between the processors410,415and other elements of system400. In one embodiment, GMCH420communicates with processors410,415via a multi-drop bus, such as a frontside bus (FSB)495.

Furthermore, GMCH420may be coupled to a display445(such as a flat panel display). In one embodiment, GMCH420may include an integrated graphics accelerator. GMCH420may be further coupled to an input/output (I/O) controller hub (ICH)450, which may be used to couple various peripheral devices to system400. External graphics device460may include be a discrete graphics device coupled to ICH450along with another peripheral device470.

In other embodiments, additional or different processors may also be present in system400. For example, additional processors410,415may include additional processors that may be the same as processor410, additional processors that may be heterogeneous or asymmetric to processor410, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There may be a variety of differences between the physical resources410,415in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst processors410,415. For at least one embodiment, various processors410,415may reside in the same die package.

FIG. 5illustrates a block diagram of a second system500, in accordance with embodiments of the present disclosure. As shown inFIG. 5, multiprocessor system500may include a point-to-point interconnect system, and may include a first processor570and a second processor580coupled via a point-to-point interconnect550. Each of processors570and580may be some version of processor300as one or more of processors410,615.

WhileFIG. 5may illustrate two processors570,580, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors570and580are shown including integrated memory controller units572and582, respectively. Processor570may also include as part of its bus controller units point-to-point (P-P) interfaces576and578; similarly, second processor580may include P-P interfaces586and588. Processors570,580may exchange information via a point-to-point (P-P) interface550using P-P interface circuits578,588. As shown inFIG. 5, IMCs572and582may couple the processors to respective memories, namely a memory532and a memory534, which in one embodiment may be portions of main memory locally attached to the respective processors.

Processors570,580may each exchange information with a chipset590via individual P-P interfaces552,554using point to point interface circuits576,594,586,598. In one embodiment, chipset590may also exchange information with a high-performance graphics circuit538via a high-performance graphics interface539.

Chipset590may be coupled to a first bus516via an interface596. In one embodiment, first bus516may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown inFIG. 5, various I/O devices514may be coupled to first bus516, along with a bus bridge518which couples first bus516to a second bus520. In one embodiment, second bus520may be a Low Pin Count (LPC) bus. Various devices may be coupled to second bus520including, for example, a keyboard and/or mouse522, communication devices527and a storage unit528such as a disk drive or other mass storage device which may include instructions/code and data530, in one embodiment. Further, an audio I/O524may be coupled to second bus520. Note that other architectures may be possible. For example, instead of the point-to-point architecture ofFIG. 5, a system may implement a multi-drop bus or other such architecture.

FIG. 6illustrates a block diagram of a third system600in accordance with embodiments of the present disclosure. Like elements inFIGS. 5 and 6bear like reference numerals, and certain aspects ofFIG. 5have been omitted fromFIG. 6in order to avoid obscuring other aspects ofFIG. 6.

FIG. 6illustrates that processors670,680may include integrated memory and I/O Control Logic (“CL”)672and682, respectively. For at least one embodiment, CL672,682may include integrated memory controller units such as that described above in connection withFIGS. 3-5. In addition. CL672,682may also include I/O control logic.FIG. 6illustrates that not only memories632,634may be coupled to CL672,682, but also that I/O devices614may also be coupled to control logic672,682. Legacy I/O devices615may be coupled to chipset690.

FIG. 7illustrates a block diagram of a SoC700, in accordance with embodiments of the present disclosure. Similar elements inFIG. 3bear like reference numerals. Also, dashed lined boxes may represent optional features on more advanced SoCs. An interconnect units702may be coupled to: an application processor710which may include a set of one or more cores702A-N and shared cache units706; a system agent unit711; a bus controller units716; an integrated memory controller units714; a set or one or more media processors720which may include integrated graphics logic708, an image processor724for providing still and/or video camera functionality, an audio processor726for providing hardware audio acceleration, and a video processor728for providing video encode/decode acceleration; an SRAM unit730; a DMA unit732; and a display unit740for coupling to one or more external displays.

FIG. 8is a block diagram of an electronic device800for utilizing a processor810, in accordance with embodiments of the present disclosure. Electronic device800may include, for example, a notebook, an ultrabook, a computer, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

Electronic device800may include processor810communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. Such coupling may be accomplished by any suitable kind of bus or interface, such as I2C bus, System Management Bus (SMBus), Low Pin Count (LPC) bus, SPI, High Definition Audio (HDA) bus, Serial Advance Technology Attachment (SATA) bus, USB bus (versions 1, 2, 3), or Universal Asynchronous Receiver/Transmitter (UART) bus.

Such components may include, for example, a display824, a touch screen825, a touch pad830, a Near Field Communications (NFC) unit845, a sensor hub840, a thermal sensor846, an Express Chipset (EC)835, a Trusted Platform Module (TPM)838, BIOS/firmware/flash memory822, a DSP860, a drive820such as a Solid State Disk (SSD) or a Hard Disk Drive (HDD), a wireless local area network (WLAN) unit850, a Bluetooth unit852, a Wireless Wide Area Network (WWAN) unit856, a Global Positioning System (GPS), a camera854such as a USB 3.0 camera, or a Low Power Double Data Rate (LPDDR) memory unit815implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

Furthermore, in various embodiments other components may be communicatively coupled to processor810through the components discussed above. For example, an accelerometer841, Ambient Light Sensor (ALS)842, compass843, and gyroscope844may be communicatively coupled to sensor hub840. A thermal sensor839, fan837, keyboard846, and touch pad830may be communicatively coupled to EC835. Speaker863, headphones864, and a microphone865may be communicatively coupled to an audio unit864, which may in turn be communicatively coupled to DSP860. Audio unit864may include, for example, an audio codec and a class D amplifier. A SIM card857may be communicatively coupled to WWAN unit856. Components such as WLAN unit850and Bluetooth unit852, as well as WWAN unit856may be implemented in a Next Generation Form Factor (NGFF).

FIG. 9is a block diagram of a system900including a reconfigurable neuromorphic processor, according to embodiments of the present disclosure. System900may include, for example, a notebook, an ultrabook, a computer, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. System900may include CPU904communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. Such coupling may be accomplished by any suitable kind of bus or interface, such as I2C bus, System Management Bus (SMBus), Low Pin Count (LPC) bus, SPI, High Definition Audio (HDA) bus, Serial Advance Technology Attachment (SATA) bus, USB bus (versions 1, 2, 3), or Universal Asynchronous Receiver/Transmitter (UART) bus.

System900may further include reconfigurable neuromorphic processor902. Reconfigurable neuromorphic processor902may be used (alone or in conjunction with another type of processor) to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. For example, reconfigurable neuromorphic processor902may allow systems to perform facial recognition, to extract information from large data sets, and to perform object detection tasks that may be beyond of the scope of traditionally programmed solutions. Reconfigurable neuromorphic processor902may provide a path to computational intelligence by allowing machines to learn features from training data, when programming features in explicitly becomes too complex. Reconfigurable neuromorphic processor902and components thereof may be implemented using circuitry or logic.

Reconfigurable neuromorphic processor902may operate in a manner similar to biological neural networks (such as a central nervous system of an animal). Reconfigurable neuromorphic processor902may include one or more inputs906and one or more outputs908. Inputs906may include circuitry or logic to accept input of digital data. Inputs906may be coupled to CPU904, or may be connected to another component or peripheral component of system900. Outputs908may include circuitry or logic to output digital data from reconfigurable neuromorphic processor902. Outputs908may be coupled to CPU904, or may be connected to another component or peripheral component of system900.

System900may also include CPU904. In one embodiment, reconfigurable neuromorphic processor902may be located on the same chip, die, or within the same package as CPU904, which operates in conjunction with a reconfigurable neuromorphic processor. In other embodiments, a reconfigurable neuromorphic processor of the present disclosure may be located in a standalone chip, die, or within a different package as CPU904that operates in conjunction with reconfigurable neuromorphic processor902.

FIG. 10is a block diagram of an example embodiment of a reconfigurable neuromorphic processor, according to embodiments of the present disclosure. Reconfigurable neuromorphic processor1000may include one or more neurons1002. Neurons1002and components thereof may be implemented using circuitry or logic. Typically, a reconfigurable neuromorphic processor may include thousands or millions of instances of neurons1002, but any suitable number of neurons may be used. Each instance of neuron1002may include neuron input1004and neuron output1006. Neuron inputs1004and neuron outputs1006may be interconnected. Connections between neuron inputs1004and neuron outputs1006may be made through synapses1008. Each instance of neuron1002may have one neuron output1006that may fan out through one or more synapses1008to one or more neuron inputs1004. Neurons1002may sum or integrate a signal received at neuron inputs1004. In general, neurons1002may “fire” (transmit an output pulse) when inputs received through neuron input1004exceed a threshold. When this sum (referred to as a” “membrane potential”) exceeds a threshold value, a neuron may generate an output (or “fire”) from the neuron using a transfer function such as a sigmoid or threshold function. In some embodiments, neurons1002may be implemented using circuits or logic that receive inputs and integrate them. In further embodiments, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, neurons1002may include comparator circuits or logic that generate an output spike at neuron output1006when the result of applying a transfer function to neuron input1004exceeds a threshold.

An output spike may be passed from neuron output1006via one or more synapses1008to one or more neuron inputs1004of neurons1002. Accordingly, each instance of neuron1002may include neuron memory1016. Neuron memory1016may be composed of static random access memory, memristors, spin torque memory, or any other suitable type of memory circuit or logic. Neuron memory1016may include circuitry or logic that can store one or more neuron destinations. A neuron destination may include a digital address indicating an identity of a synapse to receive an input from a particular instance of neuron1002. Initial neuron destinations may be written in neuron memory1016during setup or training of reconfigurable neuromorphic processor1000. Neuron destinations may be determined based upon a task to be performed by reconfigurable neuromorphic processor1000. In some embodiments, a processer, such as CPU904, may initialize reconfigurable neuromorphic processor1000by writing initial neuron destinations in neuron memory1016.

Synapses1008may have an associated synapse weight. When synapses1008transmitted an output of an instance of neuron1002to an input of an instance of neuron1002, that output may be multiplied by a synapse weight. During operation, synapse weights of synapses1008may be selected, modified, or adjusted, making reconfigurable neuromorphic processor1000adaptive to various inputs and capable of learning. Accordingly, a reconfigurable neuromorphic processor may not require a setup program, but rather may be a learning architecture that may be trained through iterative adjustment of synapse weights. Once neuron1002fires, it may disregard previously received input information, thereby resetting neuron1002. Synapses1008and components thereof may be implemented using circuitry or logic.

Each synapse1008may include synapse memory1010. Synapse memory1010may be composed of static random access memory, memristors, spin torque memory, or any other suitable type of memory circuit or logic. Synapse memory1010may store synapse destination1012and synapse weight1014. Synapse destination1012may include a digital representation identifying a neuron to which information stored in a particular instance of synapse memory1010should be transmitted. Synapse weight1012may include a digital representation of a weight to be transmitted to the neuron identified in synapse destination1012.

FIG. 11is a block diagram of example corelets of a reconfigurable neuromorphic processor, according to embodiments of the present disclosure. Neurons and synapses of a reconfigurable neuromorphic processor may be organized into groups of synapses and neurons, referred to as “corelets.” For example, as depicted inFIG. 11, reconfigurable neuromorphic processor1100may include corelet1102aand corelet1102b(collectively “corelets1102”). Corelets1102may include one more neuron groups1104aand1104b(collectively “neuron groups1104”). Each neuron group1104may include one or more neurons, such as neurons1002, described above with references forFIG. 10. Corelets1102and components thereof may be implemented using circuitry or logic.

Corelets1102may also include synapse arrays1106a,1106b,1106cand1106d(collectively “synapse arrays1106”). Synapse arrays1106may include one or more synapses. In previous neuromorphic processors, an output of each synapse may be hard-wired to a corresponding neuron. Accordingly, the maximum number of synapses that could be connected to each neuron would be dictated by the number of synapses in the corelet. For example, each corelet1102might include two instances of synapse arrays1006. If each synapse array enables a fixed number (n) of synapses to connect to a particular neuron, each neuron may be connected to a maximum of this fixed number of synapses multiplied by the number of synapse arrays (2n). However, if fewer than 2n inputs are used, and then unused synapses may be idle and wasted.

Accordingly, reconfigurable neuromorphic processor1100may include a reconfigurable interconnect architecture rather than dedicated hard-wired interconnects to connect synapse arrays1106to neurons1104. Reconfigurable neuromorphic processor1100may include circuitry or logic that allows synaptic arrays to be allocated to different neuron groups as needed based on the neural network topology and neuron fan-in/out. For example, synaptic array inputs and outputs may be connected to neuron groups using an interconnect fabric, such as network-on-chip1112, rather than with dedicated connections. Reconfigurable neuromorphic processor1100may connect synapse arrays1106to neurons1104using synapse array routers1108a,1008b1108cand1108d(collectively “synapse array routers1108”). Outputs of neurons1104may be communicated to synapses using synapse array routers1108.

Synapse array routers1108may include an on-chip interconnect in the form of a bus, crossbar, or network-on-chip1112. For example, in some embodiments, synapse array routers1108in different corelets may be connected via network-on-chip1112. Accordingly, rather than directly connecting synapses to neurons, synapse array routers1108may allow reallocation of synapse arrays between different neurons in different corelets. Synapse array routers1108and components thereof may be implemented using circuitry or logic.

Accordingly, in a topology of reconfigurable neuromorphic processor1100where fewer than all synapses in a corelet are connected to neurons, the remaining synapses may be connected to neurons in other corelets. For example, in the example shown inFIG. 11, a maximum number of synapses that could be connected to each neuron may be limited by the total number of synapses in reconfigurable neuromorphic processor1100rather than by the number of synapses in a corelet. Synapse array routers1108may thus allow flexible synapse array mapping, which may allow reconfigurable neuromorphic processor1100to accommodate a wider variety of neural network topologies. Overall the flexibility and ease of use will improve neural network performance in computational intelligence problems.

Synapse array routers1108may use distributed routing algorithms. Synapse array routers1108may operate by identifying a destination address from an output of a synapse. For example, synapse array routers1108may read a synapse destination from a synapse memory. Based on this synapse destination, synapse array routers1108may route packets originating from a synapse array to a particular neuron1104. A packet may include digital data such as synapse weight and synapse destination. A packet may be transmitted between multiple instances of synapse array routers1108or neuron group routers1110prior to reaching a neuron group router associated with the destination neuron. Accordingly, synapse array routers1108may include circuitry or logic that can examine a synapse destination in a packet and determine, based on a routing algorithm, where to transmit the packet. Initial synapse destinations and initial synapse weights may be written in synapse array1106during setup or training of reconfigurable neuromorphic processor1100. Synapse destinations may be determined based upon a task to be performed by reconfigurable neuromorphic processor1100. In some embodiments, a processer, such as CPU904, may program reconfigurable neuromorphic processor1100by writing initial synapse weights and synapse destinations in synapse arrays1106.

Neuron groups1104may include neuron group routers1110. Neuron group routers may be similar to synapse array routers1108, but may be associated with neuron groups1104rather than synapse arrays. For example, neuron group routers1110may also use distributed routing algorithms. Furthermore, an instance of neuron group routers1110may include logic or circuitry to receive a packet, and, based on a determination that a synapse destination is located in the instance of neuron group1104associated with neuron group routers1110, to transmitted that packet to an input of a neuron within neuron groups1104. Neuron group routers1104may also transmit packets indicating that a neuron has fired. For example, neuron group router1104may receive a packet from a neuron. That packet may include one or more neuron destinations. As described above with reference toFIG. 10, a neuron destination may indicate one or more synapses to which an output of an instance of neuron1102should be transmitted. A packet may be transmitted between multiple instances of synapse array routers1108or neuron group routers1110prior to reaching a synapse array routers associated with the destination synapse. Accordingly, neuron group routers1104may include circuitry or logic that can examine a neuron destination in a packet and determine, based on a routing algorithm, where to transmit the packet. Neuron group routers1110and components thereof may be implemented using circuitry or logic.

Using synapse array routers1108and neuron group routers1110that are interconnected through network-on-chip1112rather than directly connecting synapses to neurons may have numerous advantages. For example, if fewer than all synapses in a corelet are connected to a neuron, synapse array routers1108and neuron group routers1110may be used to reallocated unused synapses to other neuron groups. This in turn may allow a greater fan-in for other neurons. Some neuron groups may be disabled with minimal effect on system area or energy since these metrics are dominated by synapse array hardware and synapse weight lookup hardware.

FIG. 12is a flow chart of a method1200for interconnecting synapses and neurons in a reconfigurable neuromorphic processor, in accordance with embodiments of the present disclosure. Although Method1200describes operation of particular elements, method1200may be performed by any suitable combination or type of elements. For example, method1200may be implemented by the elements illustrated inFIGS. 1-11or any other system operable to implement method1200. As such, the preferred initialization point for method1200and the order of the elements comprising Method1200may depend on the implementation chosen. In some embodiments, some elements may be optionally omitted, reorganized, repeated, or combined. Moreover, portions of method1200may be executed in parallel within itself.

At1205, in one embodiment initial synapse weights and synapse destinations may be written into synapse memory of synapse arrays. For example, as described above with reference toFIG. 11, initial synapse destinations and initial synapse weights may be written in synapse array during setup or training of reconfigurable neuromorphic processor. Synapse destinations may be determined based upon a task to be performed by reconfigurable neuromorphic processor. In some embodiments, a processer, such as a CPU, may initialize a reconfigurable neuromorphic processor by writing initial synapse weights and synapse destinations in synapse arrays.

At1210, in one embodiment a neuron may generate an output. Neurons may sum or integrate a signal received at neuron inputs. In general, neurons may “fire” (transmit an output pulse) when inputs received through neuron inputs exceed a threshold. When this sum exceeds a threshold value (referred to as a” “membrane potential”), a neuron may generate an output (or “fire”) from the membrane potential using a transfer function such as a sigmoid or threshold function. In some embodiments, neurons may be implemented using circuits or logic that receive inputs and integrate them. In further embodiments, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, neurons may include comparator circuits or logic that generates an output spike when the result of applying a transfer function to neuron input exceeds a threshold.

At1215, in one embodiment a neuron group router may transmit a neuron output to a synapse in a synapse array. That output may be passed through neuron output1006via one or more synapses1008to one or more neuron inputs1004of neurons1002. Each instance of neuron1002may include neuron memory1016. Neuron memory1016may be composed of static random access memory, memristors, spin torque memory, or any other suitable type of memory circuit or logic. Neuron memory1016may include circuitry or logic that can store one or more neuron destinations. A neuron destination may include a digital address indicating an identity of a synapse that may receive an input from a particular instance of neuron1002. Initial neuron destinations may be written in neuron memory1016during setup or training of reconfigurable neuromorphic processor1000. Neuron destinations may be determined based upon a task to be performed by reconfigurable neuromorphic processor1000. In some embodiments, a processer, such as CPU904, may initialize reconfigurable neuromorphic processor1000by writing initial neuron destinations in neuron memory1016. Neuron group routers1104may transmit packets indicating that a neuron has fired. For example, neuron group router1104may receive a packet from a neuron. That packet may include one or more neuron destinations. As described above with reference toFIG. 10, a neuron destination may indicate one or more synapses to which an output of an instance of a neuron should be transmitted. A packet may be transmitted between multiple instances of synapse array routers or neuron group routers prior to reaching a synapse array routers associated with the destination synapse. Accordingly, neuron group routers may include circuitry or logic that can examine a neuron destination in a packet and determine based on a routing algorithm, where to transmit the packet.

At1220, in one embodiment synapse array router may read a synapse weight and a synapse destination from a synapse memory. Synapse array routers may use distributed routing algorithms. Synapse array routers may operate by identifying a destination address from an output of a synapse. For example, synapse array routers may read a synapse destination from a synapse memory.

At1225, in one embodiment, a synapse array router may transmit a packet to a neuron group router. Based on a synapse destination, synapse array routers may route packets originating from a synapse array to a particular neuron. A packet may include digital data such as synapse weight and synapse destination. A packet may be transmitted between multiple instances of synapse array routers or neuron group routers prior to reaching a neuron group router associated with the destination neuron. Accordingly, synapse array routers may include circuitry or logic that can examine a synapse destination in a packet and determine, based on a routing algorithm, where to transmit the packet. Initial synapse destinations and initial synapse weights may be written in synapse array during setup or training of reconfigurable neuromorphic processor. Synapse destinations may be determined based upon a task to be performed by reconfigurable neuromorphic processor. In some embodiments, a processer, such as a CPU, may initialize reconfigurable neuromorphic processor by writing initial synapse weights and synapse destinations in synapse arrays.

At1230, in one embodiment, a neuron group router may receive and process a packet. Neuron groups may include neuron group routers. Neuron group routers may be similar to synapse array routers, but may be associated with neuron groups rather than synapse arrays. Accordingly, an instance of neuron group routers may include logic or circuitry to receive a packet, and, based on a determination that a synapse destination is located in the instance of neuron group associated with neuron group routers, to transmit that packet to an input of a neuron within neuron groups. Accordingly, if a neuron generates an output, method1200may return to step1210and repeat. Alternatively, at1230, method1200may optionally repeat or terminate.

Thus, techniques for performing one or more instructions according to at least one embodiment are disclosed. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on other embodiments, and that such embodiments not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure. In an area of technology such as this, where growth is fast and further advancements are not easily foreseen, the disclosed embodiments may be readily modifiable in arrangement and detail as facilitated by enabling technological advancements without departing from the principles of the present disclosure or the scope of the accompanying claims.

In some embodiments of the present disclosure, a neuromorphic processor may include a plurality of corelets. In combination with any of the above embodiments, in an embodiment each corelet may include a plurality of synapse arrays. In combination with any of the above embodiments, in an embodiment each synapse array may include a plurality of synapses. In combination with any of the above embodiments, in an embodiment, each synapse may include a synapse input. In combination with any of the above embodiments, in an embodiment each synapse may include a synapse output. In combination with any of the above embodiments, in an embodiment each synapse may include a synapse memory. In combination with any of the above embodiments, in an embodiment each synapse array may include a synapse array router coupled to the synapse outputs in the synapse array. In combination with any of the above embodiments, in an embodiment each corelet array may include a neuron array. In combination with any of the above embodiments, in an embodiment each neuron array may include a plurality of neurons. In combination with any of the above embodiments, in an embodiment each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

In combination with any of the above embodiments, in an embodiment a first synapse array router may include a second logic to route a synapse output to a neuron input of a neuron in a different corelet. In combination with any of the above embodiments, in an embodiment each synapse may further include a synapse memory to store a synapse destination and a synapse weight. In combination with any of the above embodiments, in an embodiment, a first synapse array router may include a second logic to read at least one synapse memory. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a third logic identify a synapse destination. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a fourth logic to identify a synapse weight. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a fifth logic to transmit a packet including the synapse weight and the synapse destination to a neuron group router, based on a routing algorithm. In combination with any of the above embodiments, in an embodiment in one of the corelets the number of synapses to be routed to one of the neuron inputs is greater than the number of synapses in the corelet. In combination with any of the above embodiments, in an embodiment a neuromorphic processor may include a processor including a second logic to write initial synapse destinations and initial synapse weights into the synapse memory of each of the plurality of synapses in a first corelet, wherein at least one of the synapse destinations is to a neuron array in a second corelet.

In some embodiments of the present disclosure, reconfigurable neuromorphic processor logic unit may include a plurality of corelets. In combination with any of the above embodiments, in an embodiment each corelet may include a plurality of synapse arrays. In combination with any of the above embodiments, in an embodiment each synapse array may include a plurality of synapses. In combination with any of the above embodiments, in an embodiment, each synapse may include a synapse input. In combination with any of the above embodiments, in an embodiment each synapse may include a synapse output. In combination with any of the above embodiments, in an embodiment each synapse may include a synapse memory. In combination with any of the above embodiments, in an embodiment each synapse array may include a synapse array router coupled to the synapse outputs in the synapse array. In combination with any of the above embodiments, in an embodiment each corelet array may include a neuron array. In combination with any of the above embodiments, in an embodiment each neuron array may include a plurality of neurons. In combination with any of the above embodiments, in an embodiment each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.

In combination with any of the above embodiments, in an embodiment a first synapse array router may include a second logic to route a synapse output to a neuron input of a neuron in a different corelet. In combination with any of the above embodiments, in an embodiment each synapse may further include a synapse memory to store a synapse destination and a synapse weight. In combination with any of the above embodiments, in an embodiment, a first synapse array router may include a second logic to read at least one synapse memory. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a third logic identify a synapse destination. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a fourth logic to identify a synapse weight. In combination with any of the above embodiments, in an embodiment a first synapse array router may include a fifth logic to transmit a packet including the synapse weight and the synapse destination to a neuron group router, based on a routing algorithm. In combination with any of the above embodiments, in an embodiment in one of the corelets the number of synapses to be routed to one of the neuron inputs is greater than the number of synapses in the corelet. In combination with any of the above embodiments, in an embodiment reconfigurable neuromorphic processor logic unit may include a processor including a second logic to write initial synapse destinations and initial synapse weights into the synapse memory of each of the plurality of synapses in a first corelet, wherein at least one of the synapse destinations is to a neuron array in a second corelet.

In some embodiments of the present disclosure, a method may include in a reconfigurable neuromorphic processor receiving inputs from a plurality of synapses at a first neuron of a neuron array of a corelet. In combination with any of the above embodiments, in an embodiment a method may include applying a transfer function to the inputs. In combination with any of the above embodiments, in an embodiment a method may include generating a neuron output to a synapse based on a determination that the transfer function has exceeded a threshold. In combination with any of the above embodiments, in an embodiment a method may include based on receiving the neuron output, reading a synapse weight and a synapse destination from a synapse memory. In combination with any of the above embodiments, in an embodiment a method may include transmitting the synapse weight to the synapse destination through one of a plurality of routing channels in a first synapse router.

In combination with any of the above embodiments, in an embodiment a method may include receiving, with a neuron group router, the synapse weight and the synapse destination. In combination with any of the above embodiments, in an embodiment a method may include transmitting the synapse weight to an input of a second neuron identified in the synapse destination. In combination with any of the above embodiments, in an embodiment a method may include wherein the synapse destination is a second neuron. In combination with any of the above embodiments, in an embodiment a method may include wherein the second neuron is in a different corelet from the synapse. In combination with any of the above embodiments, in an embodiment transmitting the synapse weight to the synapse destination through one of a plurality of routing channels in a synapse router may include creating a packet containing the synapse weight and the synapse destination. In combination with any of the above embodiments, in an embodiment transmitting the synapse weight to the synapse destination through one of a plurality of routing channels in a synapse router may include transmitting the packet to a second synapse router. In combination with any of the above embodiments, in an embodiment a method may include wherein a second neuron receives inputs from a number of synapses greater than the number of synapses in one of the corelets.

In some embodiments of the present disclosure, an apparatus may include means for a plurality of corelets. In combination with any of the above embodiments, in an embodiment each corelet may include a means for a plurality of synapse arrays. In combination with any of the above embodiments, in an embodiment each synapse array may include a means for plurality of synapses. In combination with any of the above embodiments, in an embodiment, each synapse may include a means for a synapse input. In combination with any of the above embodiments, in an embodiment each a means for a synapse may include a means for a synapse output. In combination with any of the above embodiments, in an embodiment each means for a synapse may include a means for a synapse memory. In combination with any of the above embodiments, in an embodiment each means for a synapse array may include a means for a synapse array router coupled to the means for synapse outputs in the synapse array. In combination with any of the above embodiments, in an embodiment each means for a corelet array may include a means for a neuron array. In combination with any of the above embodiments, in an embodiment each means for a neuron array may include a means for a plurality of neurons. In combination with any of the above embodiments, in an embodiment each means for a synapse array router may include a means to route one or more of the synapse outputs to one or more of the neuron inputs.

In combination with any of the above embodiments, in an embodiment a means for a first synapse array router may include a means for a second logic to route a synapse output to a neuron input of a neuron in a different corelet. In combination with any of the above embodiments, in an embodiment each synapse may further include a means for a synapse memory to store a means for a synapse destination and a means for a synapse weight. In combination with any of the above embodiments, in an embodiment, a means for a first synapse array router may include a means for a second logic to read at least one means for a synapse memory. In combination with any of the above embodiments, in an embodiment a means for a first synapse array router may include a means for a third logic identify a synapse destination. In combination with any of the above embodiments, in an embodiment a means for a first synapse array router may include a means for a fourth logic to identify a synapse weight. In combination with any of the above embodiments, in an embodiment a means for a first synapse array router may include a means for a fifth logic to transmit a packet including the synapse weight and the synapse destination to a neuron group router, based on a routing algorithm. In combination with any of the above embodiments, in an embodiment in one of the means for corelets the number of synapses to be routed to one of the neuron inputs is greater than the number of synapses in the corelet. In combination with any of the above embodiments, in an embodiment an apparatus may include a means for a processor including a means for a second logic to write initial synapse destinations and initial synapse weights into the synapse memory of each of the plurality of synapses in a first corelet, wherein at least one of the synapse destinations is to a neuron array in a second corelet.