Arithmetic device

According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-112313, filed on Jun. 17, 2019; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an arithmetic device.

BACKGROUND

For example, an arithmetic device is applied to a neuromorphic computer, etc. A practical arithmetic device is desirable.

DETAILED DESCRIPTION

According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.

First Embodiment

FIG.1is a schematic view illustrating an arithmetic device according to a first embodiment.

As shown inFIG.1, the arithmetic device110according to the embodiment includes an arithmetic circuit10U. The arithmetic circuit10U is, for example, an arithmetic unit. The arithmetic circuit10U includes a memory part10and an arithmetic part20. The memory part10includes multiple memory regions10R.

For example, a portion of the multiple memory regions10R can store (or retain) a first variable group xj. For example, another portion of the multiple memory regions10R can store (or retain) a second variable group wij. The second variable group wijmay be, for example, a matrix.

For example, the arithmetic device110according to the embodiment can be used in arithmetic corresponding to a neural network. In such a case, for example, the first variable group xjcorresponds to the states of neurons. For example, the second variable group wijcorresponds to the states of synapse parameters (e.g., the synaptic weight).

The information (e.g., the variable groups, etc.) that is stored in the memory part10is supplied to the arithmetic part20. The arithmetic part20performs arithmetic based on the information. For example, the arithmetic includes a multiply-add operation.

As shown inFIG.1, the arithmetic part20includes a multiply-add operation circuit20A and a nonlinear transformation circuit20B. The multiply-add operation circuit20A performs a multiply-add operation of the first variable group xjand the second variable group wijstored in the memory part10. In one example, the multiply-add operation includes the arithmetic of hi=Σwijxj. The nonlinear transformation circuit20B performs a nonlinear transformation of the output of the multiply-add operation circuit20A. The nonlinear transformation includes the derivation of the value of a nonlinear function of “hi”. The value after the transformation corresponds to the output value. For example, the arithmetic circuit10U stores the result of the nonlinear transformation in the memory part10.

The arithmetic circuit10U functions as one “core”.

FIG.2is a schematic view illustrating the arithmetic device according to the first embodiment.

FIG.2illustrates one of the multiple memory regions10R. As shown inFIG.2, the one of the multiple memory regions10R includes a capacitance50and a first electrical circuit40A. The capacitance50includes a first terminal50A and a second terminal50B. For example, the second terminal50B is set to a reference potential (e.g., a ground potential). The first electrical circuit40A is electrically connected to the first terminal50A.

In this specification, the state of being electrically connected includes the state in which a state is formable so that a current flows in multiple conductors. The state of being electrically connected includes, for example, the state in which multiple conductors physically contact each other. The state of being electrically connected includes, for example, the state in which multiple conductors are connected by another conductor. The other conductor may include a switch (e.g., a transistor or the like). For example, the state in which a switch (a transistor or the like) is provided between one conductor and another conductor so that a state is formable in which a current flows between the one conductor and the other conductor due to the operation of the switch also is included in the state of being electrically connected. In the example ofFIG.2, a first transistor41described below is provided between the first terminal50A and the first electrical circuit40A. A state in which a current flows between the first terminal50A and the first electrical circuit40A is formed by the first transistor41being set to a conducting state.

The first electrical circuit40A is configured to output a voltage signal SigV corresponding to the potential of the first terminal50A.

In the arithmetic device110, a charge is stored in the capacitance50provided in each of the multiple memory regions10R. The stored charge corresponds to information (a signal). The charge that is stored in the capacitance50is an analog quantity. In the arithmetic device110, the multiple memory regions10R are analog memory.

In the arithmetic device110, for example, the charge that is stored in the capacitance50is converted directly into a voltage by the first electrical circuit40A. The voltage that is obtained by the conversion is extracted as the voltage signal SigV. The stored state is read by detecting the voltage signal SigV. The voltage signal SigV is an analog quantity; and the stored state is analog. For the memory part10which is analog memory, high-speed operations are possible, and the reliability is high.

In the arithmetic device110, an analog multiply-adder is applicable to the multiply-add operation circuit20A. In the embodiment, for example, compared to the case where a digital circuit is used, the current consumption can be reduced by applying analog circuits to the memory part10and the arithmetic part20. For example, the circuit configuration can be simple; and downsizing is easy. For example, large-scale arithmetic can be performed more easily.

According to the embodiment, a practical arithmetic device can be provided.

Higher performance and higher functionality are desirable for computers and electronic devices. It is desirable for the arithmetic device to be capable of accommodating an enormous amount of information processing. By increasing the scale of the information processing, for example, the enormous amount of information processing of the IoT (Internet of Things), AI (Artificial Intelligence), deep learning, etc., can be accommodated.

On the other hand, the development of energy-conserving electronics also is desirable. By higher energy conservation, for example, CO2reduction which is discussed on a global scale can be accommodated. By higher energy conservation, for example, the electrical power circumstances after a large-scale disaster can be relaxed.

For such conditions, neural networks are drawing attention as energy-conserving electronics that learn from living bodies. The relationship between neural networks and electronics has an old history. For example, the neuron model of McCulloch and Pitts presented in 1943 is known (W. S. McCulloch and W. Pitts: Bull. Math. Biophys. 5, 115 (1943)).

Subsequently, Hopfield had a major breakthrough in the field of neural networks in 1982 (J. J. Hopfield: Proc. Natl. Acad. Sci. U.S.A. 79, 2554 (1982)). He showed that an interconnected network can be represented by the Hamiltonian of an Ising spin model. Thereby, it is possible to examine information processing in a neural network by using the statistical mechanics of a spin system. Further, it became possible to associate Ising spins, which can have the binary states of up or down spins, with the activity of a neuron or an information bit.

As new hardware for a neural network, an element called the True North chip was developed jointly by IBM and Cornell University in 2014 (P. A. Merolla et al., Science 345, 668 (2014)). In this example, the element was constructed using 28-nm rule CMOS technology. As an entirety, the element operated as one million neurons. Compared to the brain of a human which is configured from 14 billion neurons, the scale of the element was small.

Neural network hardware that is typified by the True North chip also is called a neuromorphic computer. This is a massively parallel distributed computer. The massively parallel distributed computer includes many arithmetic units called cores. An arithmetic part and a memory part are provided in one of the arithmetic units. A multiply-add operation and the like are performed in the arithmetic part. For example, the states of the neurons, the synapse parameters, etc., are stored in the memory part.

Generally, SRAM is used in the memory part of a massively parallel distributed computer. A digital multiply-add operation element or the like that has large energy consumption is included in the arithmetic part.

There are expectations for neuromorphic computers to be used as large-scale energy-conserving information processing devices comparable to the human brain. However, currently, scale increases of neuromorphic computers are exceedingly insufficient. One factor is that a digital arithmetic unit which has large energy consumption is included in the arithmetic part of the arithmetic unit (the core).

In the embodiment, an analog memory in which high-speed operations are possible and the reliability is high is applied to the memory part10of the core. Thereby, it is easy to use an analog arithmetic device in the arithmetic part20. Thereby, higher energy conservation of the arithmetic device is easy. A scale increase of the arithmetic device is easy. According to the embodiment, the practical use of a neuromorphic computer is easy.

As shown inFIG.2, the memory part10includes a first line L1. The first line L1is, for example, a read line Lr.

As shown inFIG.2, one of the multiple memory regions10R includes the first transistor41. The first transistor41includes a first gate g1, a first end portion41a, and a second end portion41b. The first end portion41ais, for example, one of a source or a drain. The second end portion41bis, for example, the other of the source or the drain. The first gate g1is electrically connected to the first line L1. The first end portion41ais electrically connected to the first terminal50A of the capacitance50. The second end portion41bis electrically connected to the first electrical circuit40A.

For example, a read pulse is supplied to the first line L1. Thereby, a state is formed in which a current flows between the first electrical circuit40A and the first terminal50A of the capacitance50. A value (the amount of charge) corresponding to the potential difference between the first terminal50A and the second terminal50B of the capacitance50is extracted as the voltage signal SigV by the first electrical circuit40A. For example, the first transistor41functions as a transfer transistor.

As shown inFIG.2, the current path between the first electrical circuit40A and the second end portion41bof the first transistor41includes a connection point FD. For example, the connection point FD corresponds to a floating diffusion layer. A stray capacitance FC can be considered to be formed between the connection point FD and the reference potential (e.g., the ground potential). For example, the first electrical circuit40A extracts the potential of the connection point FD as the voltage signal SigV.

As shown inFIG.2, the first electrical circuit40A includes, for example, a second transistor42and a third transistor43. The second transistor42includes a second gate g2, a third end portion42c, and a fourth end portion42d. The third end portion42cis, for example, one of a source or a drain. The fourth end portion42dis, for example, the other of the source or the drain. The third transistor43includes a third gate g3, a fifth end portion43e, and a sixth end portion43f. The fifth end portion43eis, for example, one of a source or a drain. The sixth end portion43fis, for example, the other of the source or the drain.

On the other hand, the memory part10includes a second line L2and a third line L3. The second line L2is, for example, a select line Lse. The third line L3is, for example, a column signal line Lcs.

The second gate g2is electrically connected to the second end portion41b. In other words, the second gate g2is electrically connected to the connection point FD. The third end portion42cis electrically connected to the fifth end portion43e. The fourth end portion42dis set to a first potential VDD. The first potential VDD is, for example, a power supply potential. For example, the first potential VDD is higher than the reference potential. For example, the first potential VDD is higher than the potential of the second terminal50B of the capacitance50. The third gate g3is electrically connected to the second line L2. The sixth end portion43fis electrically connected to the third line L3. The voltage signal SigV is generated in the third line L3when a select pulse is supplied to the second line L2.

As shown inFIG.2, for example, the memory part10may include a fourth line L4. The fourth line L4is, for example, a reset line Lrs. The one of the multiple memory regions10R further includes a fourth transistor44. The fourth transistor44includes a fourth gate g4, a seventh end portion44g, and an eighth end portion44h. The seventh end portion44gis, for example, one of a source or a drain. The eighth end portion44his, for example, the other of the source or the drain. The fourth gate g4is electrically connected to the fourth line L4. The seventh end portion44gis electrically connected to the second end portion41b. In other words, the seventh end portion44gis electrically connected to the connection point FD. The eighth end portion44his electrically connected to the fourth end portion42d. For example, the potential of the connection point FD is set to a reset state when a reset pulse is supplied to the fourth line L4.

As shown inFIG.2, the first line L1, the second line L2, and the third line L3extend along a first direction (e.g., an X-axis direction). A direction perpendicular to the X-axis direction is taken as a Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is taken as a Z-axis direction. For example, the third line L3extends along a second direction. The second direction crosses the first direction. In the example, the second direction is the Y-axis direction. For example, the multiple memory regions10R are provided in a matrix configuration along the X-axis direction and the Y-axis direction.

In the embodiment, for example, the capacitance50functions as a memory cell. For example, in the case of converting to a voltage, a charge of about 1 mV to 1 V can be retained in the memory cell. The memory cell has a wide dynamic range (e.g., 1000). When the off-current of the first transistor (the transfer transistor) is large, there are cases where the charge cannot be retained for a long period of time. In such a case, the rewriting is performed at a frequency similar to that of DRAM.

In the embodiment, the off-current of the first transistor41can be reduced. For example, a small off-current is obtained by including an oxide semiconductor in the semiconductor included in the first transistor. The oxide semiconductor includes, for example, oxygen and at least one of In, Ga, or Zn. An off-current of about 10−21A is obtained thereby.

On the other hand, it is favorable for the semiconductors included in the second transistor42, the third transistor43, and the fourth transistor44to include silicon. The stability of the operating characteristics is high for a transistor based on silicon. Thereby, high stability is obtained in the conversion from the charge to the voltage.

Because the first transistor41includes an oxide semiconductor and the second to fourth transistors42to44include silicon, high stability is obtained in the conversion from the charge to the voltage while stabilizing the retention state of the charge.

In the embodiment, the capacitance50may include a “buried p-n junction”. The leakage current of the capacitance50can be reduced to about 10−17A to 10−18A.

FIG.3is a schematic cross-sectional view illustrating a portion of the arithmetic device according to the first embodiment.

As shown inFIG.3, the capacitance50includes a first semiconductor layer50a, a second semiconductor layer50b, and a third semiconductor layer50c. The first semiconductor layer50ais of a first conductivity type. The second semiconductor layer50bis of the first conductivity type. The third semiconductor layer50cis provided between the first semiconductor layer50aand the second semiconductor layer50b. The third semiconductor layer50cis of a second conductivity type. In the example, the first conductivity type is a p-type; and the second conductivity type is an n-type. The first conductivity type may be the n-type; and the second conductivity type may be the p-type. For example, the first terminal50A is electrically connected to the second semiconductor layer50b.

The concentration of the impurity of the first conductivity type in the second semiconductor layer50bis higher than the concentration of the impurity of the first conductivity type in the first semiconductor layer50a. For example, the second semiconductor layer50bis a p+-region; and the first semiconductor layer50ais, for example, a p-region. In such a case, the third semiconductor layer50cis an n-region. In the embodiment, the second semiconductor layer50bmay be an n+-region; the first semiconductor layer50amay be an n-region; and the third semiconductor layer50cmay be a p-region.

The leakage current can be reduced by applying such a three-layer structure to the capacitance50. A stable memory state is obtained.

In the embodiment, for example, the capacitance50may have a MOS structure. The capacitance50may include, for example, a tunnel junction. For example, the leakage current can be reduced by such structures. For example, a charge retention time of about 1000 hours is obtained.

FIG.4is a schematic view illustrating an arithmetic device according to the first embodiment.

FIG.4illustrates one of the multiple memory regions10R. In the arithmetic device111as shown inFIG.5, the one of the multiple memory regions10R includes the capacitance50and the first to fifth transistors41to45. The configurations described in reference toFIG.2are applicable to the first to fourth transistors41to44. The first to sixth lines L1to L6are provided in the example. The configurations described in reference toFIG.2are applicable to the first to fourth lines L1to L4. Examples of the fifth transistor45, the fifth line L5, and the sixth line L6will now be described.

The fifth transistor45includes a fifth gate g5, a ninth end portion45i, and a tenth end portion45j. The fifth gate g5is electrically connected to the fifth line L5. The fifth line L5is, for example, a write control line Lw. The ninth end portion45iis electrically connected to the sixth line L6. The sixth line L6is, for example, a write data line Ld. The tenth end portion45jis electrically connected to the first terminal50A of the capacitance50.

For example, when a write select pulse is supplied to the fifth line L5, a charge that corresponds to the potential of the sixth line L6is supplied to the capacitance50via the fifth transistor45. The desired information is stored in the capacitance50. An analog quantity is stored in the capacitance50. The first transistor41is in the off-state when the fifth transistor45is in the on-state. The first transistor41is in the on-state when the fifth transistor45is in the off-state.

For example, the fifth transistor45is directly connected to the capacitance50. It is favorable for the off-current of the fifth transistor45to be small. In the embodiment, for example, it is favorable for the semiconductor included in the first transistor41and the semiconductor included in the fifth transistor45to include oxygen and at least one of In, Ga, or Zn.

Because the first transistor41and the fifth transistor45include oxide semiconductors and the second to fourth transistors42to44include silicon, high stability is obtained in the conversion from the charge to the voltage while stabilizing the retention state of the charge.

As shown inFIG.4, for example, the first transistor41and the fifth transistor45are provided in an oxide semiconductor region61X. The second to fourth transistors42to44are provided in a silicon semiconductor region61S. For example, the capacitance50is provided in the silicon semiconductor region61S.

FIG.5andFIG.6are schematic views illustrating arithmetic devices according to the first embodiment.

In arithmetic devices112and113as shown inFIG.5andFIG.6, the arithmetic circuit10U includes a light-attenuating member30. Otherwise, for example, the configuration of the arithmetic device112may be similar to that of the arithmetic device111or110. Examples of the light-attenuating member30will now be described.

The light-attenuating member30overlaps the capacitance50. In the example of the arithmetic device112, the first transistor41and the fifth transistor45are between the capacitance50and the light-attenuating member30. For example, the light-attenuating member30covers the silicon semiconductor region61S and the oxide semiconductor region61X. In the example of the arithmetic device113, the light-attenuating member30is between the silicon semiconductor region61S and the oxide semiconductor region61X.

For example, the light transmittance of the light-attenuating member30is lower than the light transmittance of the semiconductor region (e.g., a first semiconductor region, e.g., an oxide semiconductor) included in the first transistor41. For example, the light transmittance of the light-attenuating member30is lower than the light transmittance of the semiconductor layer (e.g., the first semiconductor layer50a) included in the capacitance50.

For example, when light from the outside is incident on the capacitance50, there are cases where the state of the charge stored in the capacitance50changes. For example, when the light from the outside is incident on the first transistor41, etc., there are cases where the characteristics of the first transistor41change. By providing the light-attenuating member30, such a change of the characteristics can be suppressed. More stable memory operations are obtained. The light-attenuating member30is, for example, a light shield member.

FIG.7is a schematic perspective view illustrating an arithmetic device according to the first embodiment.

As shown inFIG.7, the arithmetic device114includes the arithmetic circuit10U and the light-attenuating member30. For example, the light-attenuating member30is provided around the arithmetic circuit10U. For example, the light-attenuating member30covers the arithmetic circuit10U. More stable arithmetic operations are obtained.

FIG.8AtoFIG.8Eare schematic cross-sectional views illustrating portions of the arithmetic device according to the first embodiment.

These drawings illustrate the transistors provided in one of the multiple memory regions10R.

As shown inFIG.8A, the first transistor41includes the first gate g1, the first end portion41a, and the second end portion41b. The first transistor41includes the first semiconductor region41s. The first semiconductor region41sincludes, for example, oxygen and at least one of In, Ga, or Zn. The first semiconductor region41smay further include Sn. The first semiconductor region41sis an oxide semiconductor. Because the first semiconductor region41sincludes an oxide semiconductor, a small off-current is obtained in the first transistor41. Stable memory operations are obtained.

As shown inFIG.8A, contact regions41tand41uare provided in the first transistor41. These contact regions correspond to the first end portion41aand the second end portion41b. For example, the oxygen concentrations in these contact regions are lower than the oxygen concentrations in the first semiconductor region41s. An insulating film41I is provided between the first gate g1and the first semiconductor region41s. The insulating film41I corresponds to a gate insulating film. In the example, these components are provided on a base body41J. In the first transistor41, the vertical relationship of the first semiconductor region41sand the first gate g1is arbitrary.

As shown inFIG.8B, the second transistor42includes the second gate g2, the third end portion42c, and the fourth end portion42d. The second transistor42includes a second semiconductor region42s. The second semiconductor region42sincludes, for example, silicon. Contact regions42tand42uare provided in the second transistor42. These contact regions correspond to the third end portion42cand the fourth end portion42d. For example, an insulating film421is provided between the second gate g2and the second semiconductor region42s.

As shown inFIG.8C, the third transistor43includes the third gate g3, the fifth end portion43e, and the sixth end portion43f. The third transistor43includes a third semiconductor region43s. The third semiconductor region43sincludes, for example, silicon. Contact regions43tand43uare provided in the third transistor43. These contact regions correspond to the fifth end portion43eand the sixth end portion43f. For example, an insulating film43I is provided between the third gate g3and the third semiconductor region43s.

As shown inFIG.8D, the fourth transistor44includes the fourth gate g4, the seventh end portion44g, and the eighth end portion44h. The fourth transistor44includes a fourth semiconductor region44s. The fourth semiconductor region44sincludes, for example, silicon. Contact regions44tand44uare provided in the fourth transistor44. These contact regions correspond to the seventh end portion44gand the eighth end portion44h. For example, an insulating film44I is provided between the fourth gate g4and the fourth semiconductor region44s.

As shown inFIG.8E, the fifth transistor45includes the fifth gate g5, the ninth end portion45i, and the tenth end portion45j. The fifth transistor45includes a fifth semiconductor region45s. The fifth semiconductor region45sincludes, for example, oxygen and at least one of In, Ga, or Zn. The fifth semiconductor region45smay further include Sn. The fifth semiconductor region45sis an oxide semiconductor. Because the fifth semiconductor region45sincludes an oxide semiconductor, a small off-current is obtained in the fifth transistor45. Stable memory operations are obtained.

As shown inFIG.8E, contact regions45tand45uare provided in the fifth transistor45. These contact regions correspond to the ninth end portion45iand the tenth end portion45j. For example, the oxygen concentrations in these contact regions are lower than the oxygen concentrations in the fifth semiconductor region45s. An insulating film45I is provided between the fifth gate g5and the fifth semiconductor region45s. The insulating film45I corresponds to a gate insulating film. In the example, these components are provided on a base body45J. In the fifth transistor45, the vertical relationship of the fifth semiconductor region45sand the fifth gate g5is arbitrary.

Second Embodiment

FIG.9is a schematic view illustrating a portion of an arithmetic device according to a second embodiment.

The arithmetic device120also includes the arithmetic circuit10U; and the arithmetic circuit10U includes the memory part10and the arithmetic part20(referring toFIG.1).FIG.9illustrates the multiply-add operation circuit20A included in the arithmetic part20of the arithmetic device120.

As shown inFIG.9, the multiply-add operation circuit20A includes multiple differential amplifier circuits65and a resistance66. The resistance66is electrically connected to the outputs of the multiple differential amplifier circuits65.

For each of the multiple differential amplifier circuits65, a voltage that corresponds to one value of the first variable group xjis input between a first input65aand a second input65b. For each of the multiple differential amplifier circuits65, one voltage that corresponds to the second variable group wijis input to a third input65c. For each of the differential amplifier circuits65, a value (the voltage of a connection point65d) that corresponds to the product of the first variable group xjand the second variable group wijis output. The value that corresponds to the product is, for example, a current value. The current values that correspond to the products from the multiple differential amplifier circuits65are added by the resistance66and converted into a voltage. Thus, the result of the multiply-add operation of the first variable group xjand the second variable group wijis obtained. This result is used as an input to the next neuron circuit.

In the embodiment, the multiply-add operation circuit20A includes an analog arithmetic unit. Thereby, for example, compared to the case where a digital arithmetic unit is used, the current consumption can be reduced. For example, the circuit configuration can be simple; and downsizing is easy. For example, large-scale arithmetic can be performed more easily.

The multiply-add operation circuit20A illustrated inFIG.9is applicable to any arithmetic device according to the first embodiment.

Generally, digital elements are used in the memory part and the arithmetic part. A digital arithmetic device is one factor obstructing the scale increase of neuromorphic computers because the power consumption is large. Generally, an analog device is desirable to reduce the power consumption. However, an analog device is sensitive to the fluctuation of the characteristics of the individual elements. Therefore, many electronic devices in which high reliability is necessary are being digitized; and such a trend continues even today.

One feature of a neuromorphic computer is the learning function. This feature is different from many electronic devices which operate according to set parameters. In a neuromorphic computer, it is possible to absorb much of the fluctuation of the characteristics of the individual elements by the learning function. For example, it is possible to include the fluctuation of the gain of a transistor circuit functioning as an analog memory cell in a trainable synapse parameter (the second variable group wij). In a neuromorphic computer, the temporal stability of the individual transistors is necessary; and the fluctuation of the characteristics of the multiple transistors is not very problematic.

In the embodiment, by using an analog circuit, a memory element in which the temporal stability is high can be obtained. In the embodiment, by using an analog memory device and an analog arithmetic device, a large-scale parallel distributed computer that has a learning function and excellent energy conservation can be obtained.

FIG.10is a flowchart illustrating an operation of the arithmetic device according to the embodiment.

As shown inFIG.10, the arithmetic part20acquires the first variable group xjand the second variable group wijstored in the memory part10(step S110). The arithmetic part20performs a multiply-add operation of the first variable group xjand the second variable group wij(step S120). The arithmetic part20performs nonlinear processing (a nonlinear transformation) of the result of the multiply-add operation (step S130). The arithmetic circuit10U stores the result of the nonlinear transformation in the memory part10(step S140). Such processing may be performed repeatedly. For example, the operation of a neuromorphic computer is obtained. For example, the arithmetic circuit10U includes a learning function. The arithmetic circuit10U is a spiking neural network.

The embodiments may include the following configurations (e.g., technological proposals).

An arithmetic device, comprising an arithmetic circuit,

the arithmetic circuit including:a memory part including a plurality of memory regions; andan arithmetic part,

one of the plurality of memory regions including:a capacitance including a first terminal; anda first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.
Configuration 2

The arithmetic device according to Configuration 1, wherein

the capacitance includes:a first semiconductor layer of a first conductivity type;a second semiconductor layer of the first conductivity type; anda third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer being of a second conductivity type, and

a concentration of an impurity of the first conductivity type in the second semiconductor layer is higher than a concentration of the impurity of the first conductivity type in the first semiconductor layer.

The arithmetic device according to Configuration 2, wherein the first terminal is electrically connected to the second semiconductor layer.

The arithmetic device according to any one of Configurations 1 to 3, wherein

the memory part includes a first line,

the one of the plurality of memory regions further includes a first transistor,

the first transistor includes a first gate, a first end portion, and a second end portion,

the first gate is electrically connected to the first line,

the first end portion is electrically connected to the first terminal, and

the second end portion is electrically connected to the first electrical circuit.

The arithmetic device according to Configuration 4, wherein

the first transistor includes a first semiconductor region, and

the first semiconductor region includes oxygen and at least one of In, Ga, or Zn.

The arithmetic device according to Configuration 5, wherein

the first electrical circuit further includes a second transistor,

the second transistor includes a second semiconductor region, and

the second semiconductor region includes silicon.

The arithmetic device according to Configuration 4, wherein

the memory part further includes a second line and a third line,

the first electrical circuit includes a second transistor and a third transistor,

the second transistor includes a second gate, a third end portion, and a fourth end portion,

the third transistor includes a third gate, a fifth end portion, and a sixth end portion,

the second gate is electrically connected to the second end portion,

the third end portion is electrically connected to the fifth end portion,

the fourth end portion is set to a first potential,

the third gate is electrically connected to the second line, and

the sixth end portion is electrically connected to the third line.

The arithmetic device according to Configuration 7, wherein

the first transistor includes a first semiconductor region,

the second transistor includes a second semiconductor region,

the third transistor includes a third semiconductor region,

the first semiconductor region includes oxygen and at least one of In, Ga, or Zn, and

at least one of the second semiconductor region or the third semiconductor region includes silicon.

The arithmetic device according to Configuration 7, wherein

the memory part includes a fourth line,

the one of the plurality of memory regions further includes a fourth transistor,

the fourth transistor includes a fourth gate, a seventh end portion, and an eighth end portion,

the fourth gate is electrically connected to the fourth line,

the seventh end portion is electrically connected to the second end portion, and

the eighth end portion is electrically connected to the fourth end portion.

The arithmetic device according to Configuration 9, wherein

the first transistor includes a first semiconductor region,

the second transistor includes a second semiconductor region,

the third transistor includes a third semiconductor region,

the fourth transistor includes a fourth semiconductor region,

the first semiconductor region includes oxygen and at least one of In, Ga, or Zn, and

at least one of the second semiconductor region, the third semiconductor region, or the fourth semiconductor region includes silicon.

The arithmetic device according to Configuration 9, wherein

the memory part includes a fifth line and a sixth line,

the one of the plurality of memory regions further includes a fifth transistor,

the fifth transistor includes a fifth gate, a ninth end portion, and a tenth end portion,

the fifth gate is electrically connected to the fifth line,

the ninth end portion is electrically connected to the sixth line, and

the tenth end portion is electrically connected to the first terminal.

The arithmetic device according to Configuration 11, wherein

the first transistor includes a first semiconductor region,

the second transistor includes a second semiconductor region,

the third transistor includes a third semiconductor region,

the fourth transistor includes a fourth semiconductor region,

the fifth transistor includes a fifth semiconductor region,

the first semiconductor region and the fifth semiconductor region include oxygen and at least one of In, Ga, or Zn, and

at least one of the second semiconductor region, the third semiconductor region, or the fourth semiconductor region includes silicon.

The arithmetic device according to Configurations 5, 8, 10, or 12, wherein

the arithmetic circuit includes a light-attenuating member overlapping the capacitance, and

a light transmittance of the light-attenuating member is lower than a light transmittance of the first semiconductor region.

The arithmetic device according to Configuration 2, wherein

the arithmetic circuit includes a light-attenuating member overlapping the capacitance, and

a light transmittance of the light-attenuating member is lower than a light transmittance of the first semiconductor layer.

The arithmetic device according to any one of Configurations 1 to 14, wherein

the arithmetic part includes:a multiply-add operation circuit performing a multiply-add operation of a first variable group and a second variable group stored in the memory part, anda nonlinear transformation circuit performing a nonlinear transformation of an output of the multiply-add operation circuit.
Configuration 16

The arithmetic device according to Configuration 15, wherein the multiply-add operation circuit includes an analog arithmetic unit.

The arithmetic device according to Configuration 15, wherein

the multiply-add operation circuit includes:a plurality of differential amplifier circuits; anda resistance electrically connected to outputs of the plurality of differential amplifier circuits.
Configuration 18

The arithmetic device according to any one of Configurations 1 to 17, wherein

the arithmetic part acquires a first variable group and a second variable group stored in the memory part,

the arithmetic part performs a multiply-add operation of the first variable group and the second variable group,

the arithmetic part performs a nonlinear transformation of a result of the multiply-add operation, and

the arithmetic circuit stores a result of the nonlinear transformation in the memory part.

The arithmetic device according to any one of Configurations 1 to 18, wherein the arithmetic circuit includes a learning function.

An arithmetic device according to any one of Configurations 1 to 19, wherein the arithmetic circuit is a spiking neural network.

According to the embodiments, a practical arithmetic device can be provided.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in arithmetic devices such as arithmetic circuits, memory parts, memory regions, capacitances, transistors, arithmetic parts, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all arithmetic devices practicable by an appropriate design modification by one skilled in the art based on the arithmetic devices described above as embodiments of the invention also are within the scope of the invention to the extent that the spirit of the invention is included.