Semiconductor arrangement including a load transistor and sense transistor

A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.

TECHNICAL FIELD

The present disclosure relates to a semiconductor arrangement including a load transistor and a sense transistor.

BACKGROUND

Transistors, in particular MOS transistors, like MOSFET or IGBT, can be used as electronic switches. In those applications a load path of the transistor is connected in series to the load, with the series circuit including the transistor and the load being connected between voltage supply terminals. The transistor can be switched on and off by applying a suitable control signal to its control input.

In many applications it is desired to measure the current through the load. For measuring the current through a load a sense transistor may be used. The sense transistor is coupled to the load transistor and may be operated in the same operation point as the load transistor. If the load transistor and the sense transistor are operated in the same operation point, a sense current flowing through the sense transistor is proportional to a current flowing through the load transistor. A proportionality factor between the load current and the sense current is dependent on the ratio between the active transistor areas (channel areas) of the sense transistor and the load transistor.

The proportionality factor is equal to the ratio between the active device areas, if the load transistor and the sense transistor have identical device characteristics. However, in reality the device characteristics of the load transistor and the sense transistor may differ. In one embodiment the threshold voltages of the two transistors may be different. This difference in the device characteristics may result from systematic differences in the processes that are used for manufacturing the load transistor and the sense transistor.

Usually the load transistor and the sense transistor are integrated in a common semiconductor body (die, chip), where each of the load transistor and the sense transistor may include a number of transistor cells, that can be produced using identical processes. A first number of transistor cells is connected in parallel, thereby forming the load transistor, and a second number of transistor cells is connected in parallel, thereby forming the sense transistor. The transistor cells of the load and the sense transistor may have a common control terminal and one common first load terminal, but two different second load terminals. If the transistors are MOSFET the control terminal is a gate terminal, the first load terminal may be a drain terminal, and the second load terminals may be source terminals. Producing two different second load terminals (source terminals) may result in process variations that differently influence the threshold voltage of the load transistor cells and the sense transistor cells.

DETAILED DESCRIPTION OF THE DRAWINGS

A first embodiment of the present disclosure relates to a semiconductor arrangement, including: a semiconductor body; a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region; a number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions of at least one transistor cell through contact plugs; a second contact electrode contacting a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.

A second embodiment relates to a method for producing a semiconductor arrangement, the method including: providing a semiconductor body, having a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region; forming a number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions of at least two transistor cells; forming a second contact electrode above the first electrodes, the second contact electrode contacting a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes.

FIG. 1illustrates a circuit diagram of a semiconductor arrangement or transistor arrangement that includes a load transistor10and a sense transistor20. Each of these transistors10,20has a first load terminal12,22, a second load terminal13,23, and a control terminal11,21. Transistors10,20are, for example, MOSFET. In this case the first load terminals12,22are drain terminals, second load terminals13,23are source terminals, and control terminals11,21are gate terminals. It goes without saying that any other kind of transistors, like IGBTs or bipolar transistors, may be used as transistors as well.

Load transistor10and sense transistor20have their control terminals11,21connected together, thereby forming a control terminal1of the transistor arrangement. Further, load transistor10and sense transistor20have their first load terminals12,22connected together, thereby forming a first load terminal of the transistor arrangement.

The transistor arrangement can be used for switching a current through a load and for simultaneously measuring the current flowing through the load. As illustrated in dashed lines a load path of load transistor10may, for this purpose, be connected in series to a load Z between terminals for a first supply potential V+ and a second supply potential GND, where first supply potential V+ may be a positive supply potential and negative supply potential GND may be ground. Load transistor10may be switched on and off by applying a suitable control signal to control terminal1. A load current I10flowing through load transistor10in this transistor arrangement is measured by evaluating a sense current I20flowing through sense transistor20. Sense current I20is proportional to load current I10, if the two transistors11,21have identical device characteristics, and if these two transistors are driven in the same operation point. For operating the two transistors11,21in the same operation point and for measuring a current I20flowing through sense transistor20a control and measurement circuit M may be used that is connected to the second load terminals13,23of the two transistors10,20and that provides a current measurement signal S20being proportional to the sense current I20. Control and measurement circuits, like control and measurement circuit M according toFIG. 1, are known, so that further explanations are not required in this regard.

The accuracy of the current measurement obtained with a transistor arrangement including a load transistor and a sense transistor may vary with variations in the device characteristics of the load transistor10and the sense transistor20. The two transistors10, ideally have identical device characteristics. In this case sense current I20is proportional to load current I10, where a proportionality factor between the sense current I20and the load current I10is the ratio between the active transistor areas of the sense transistor20and the load transistor10. However, due to differences in the processes of producing the two transistors the device characteristics of the two transistors10,20may be different. Differences in the production processes may, in one embodiment, result from the need to produce the load transistor10and the sense transistor20with separate second load terminals13,23, with the second load terminal of the load transistor10serving for connecting a load Z thereto, and the second load terminal23of the sense transistor20serving for measuring the sense current I20.

An example of a transistor arrangement including a load transistor10and a sense transistor20that results from a production process that largely avoids differences in processing the load transistor10and the sense transistor20is illustrated inFIG. 2.

FIGS. 2 and 3illustrate in part a vertical cross section through an integrated semiconductor arrangement including a load transistor10and a sense transistor20. The semiconductor arrangement includes a semiconductor body100in which a number of transistor cells30are integrated. As an example up to several 10000 (ten thousand), or more, transistor cells may be integrated in a semiconductor body100. In the example according toFIG. 2transistor cells30are MOSFET cells. Each of these transistor cells include a source zone31, a drift zone35and a body zone32, the latter being arranged between source zone31and drift zone35. A gate electrode33is arranged adjacent to body zone32and is dielectrically insulated from body zone32by a gate dielectric layer34. Gate electrode33serves to control a conducting channel in the body zone32between source zone31and drain zone35along gate dielectric34. The transistor cells30further include a drain zone36that adjoins drift zone35. Optionally a field-stop zone (not illustrated) may be arranged between the drain zone36and drift zone35.

The body zone32is complementarily doped to source zone31and to drift zone35. In an n-channel MOSFET body zone32is p-doped, while source and drift zones31,35are n-doped. In an p-channel MOSFET body zone32is n-doped, while source zone and drift zones31,35are p-doped. In an MOSFET drain zone36has the same doping type as drift zone35, while in an IGBT drain zone36has a doping type that is complementary to the doping type of drift zone35. In an IGBT source zone31and drain zone36are also referred to as emitter zone and collector zone, respectively. Source zone31is a first active transistor region of the transistor cell, drain zone36is a second active transistor region, and gate electrode33is a control electrode.

In the example according toFIG. 2the transistor cells are trench cells. In such cells gate electrode33is arranged in a trench that, starting from a first side101not illustrated, extends in a vertical direction of the semiconductor body100. First side101will also be referred to as front side of the semiconductor body100in the following. In these trench cells source zone31and body zone32in a lateral direction of the semiconductor body100adjoin the gate dielectric34. If a suitable control potential is applied to the gate electrode33a conducting channel extends in a vertical direction of the semiconductor body100along gate dielectric34between source zone31and drift zone35.

The use of trench transistor cells is only an example. It goes without saying, that any other cell geometry, like planar transistor cells, may be used as well. In planar transistor cells gate electrode33is arranged on top of front side101of the semiconductor body100. An example of a transistor arrangement that includes planar transistor cells is illustrated inFIG. 3.

Referring toFIGS. 2 and 3the transistor cells have drift zone35and drain zone36in common. Drain zone36or an optional electrode61(illustrated in dashed lines) that contacts drain zone36forms the first load terminal2of the transistor arrangement.

For the purpose of further explanation it is assumed that each transistor cell30includes one body zone32, where the body zones32of the individual cells are separated from each other by gate electrode33in case of trench transistor cells and by sections of drift zone35in the case of planar transistor cells.

In a horizontal plane of the semiconductor body100transistor cells30may have any known cell geometry, like a linear (stripe) geometry, a rectangular or square geometry, a hexagonal geometry or a circular geometry. The cell geometry is, usually, defined by the geometry of the body zone32. In linear (stripe) cells body zone32has a stripe-geometry. Examples of trench transistor cells and planar transistor cells having a stripe geometry are illustrated inFIGS. 4 and 5by way of a horizontal cross section through the semiconductor body100in a first section-plane A-A. In trench transistor cells the gate electrodes33do also have a stripe-geometry, where the body zones32of the different cells are arranged between two gate electrodes33.

In rectangular, hexagonal or circular transistor cells body zones32have a rectangular, hexagonal or circular geometry. Examples of transistor cells having a rectangular geometry are illustrated inFIGS. 6 and 7for trench transistor cells (FIG. 6) and planar transistor cells (FIG. 7).

The gate electrodes33of the individual transistor cells30are electrically connected to each other, thereby forming control electrode1of the transistor arrangement. In the semiconductor arrangement having a planar cell geometry only one gate electrode is formed for all transistor cells on top of semiconductor body100, this gate electrode having contact holes for contacting the source zones31of the individual transistor cells.

Referring toFIGS. 2 and 3the transistor arrangement has a number of first contact electrodes41, with each of these first contact electrodes41electrically contacting the source zones31of a given number of transistor cells30. According to an example each of the first contact electrodes41contacts the same number of transistor cells30. In the example according toFIGS. 2 and 3each first contact electrode41contacts two transistor cells30. However, this is only an example, each of the first contact electrodes41may contact at least one but also any other number higher than one of transistor cells30. According to one example the number of transistor cells that are contacted by one first contact electrode41is less than 100, or even less than 10. Each transistor cell30is contacted by only one of the first contact electrodes41.

First contact electrodes41are arranged in a horizontal plane above the semiconductor body100. This horizontal plane will be referred to as first contact plane in the following. The different first contact electrodes41are electrically insulated from each other and from gate electrodes33by insulation regions51. These insulating regions may be comprised of any electrically insulating material, like an oxide or a nitride, that is suitable to be used in semiconductor component manufacturing processes. The first contact electrodes41are planar electrodes. “Planar” in this connection means that a thickness (i.e., the dimension in the vertical direction) of the electrodes41is smaller than at least one of the width and length of the electrodes. The thicknesses of the first electrodes41are, for example, in the range between 0.5 μm and 1 μm. The width and/or length of the first electrodes41is, for example, less than 10 μm.

The first contact electrodes41contact the transistor cells30through contact plugs42. These contact plugs electrically contact the source zone31and the body zone32, thereby short-circuiting source31and body32. The latter is usual for MOSFET and IGBT. One transistor cell, i.e., the first active transistor region of one transistor cell, is contacted by the associated first contact electrode41through at least one contact plug, where more than one contact plug42may be arranged between one transistor cell30and one first contact electrode41. In one embodiment in linear transistor cells (that will be explained below) more than one contact plug can be arranged between one transistor cell30and the first contact electrode41. Contact plugs in horizontal direction may have any cross-section, like a rectangular cross-section, a circular cross-section, or a stripe-like cross section.

The transistor arrangement includes a second contact electrode43that contacts first contact electrodes of a first group of first contact electrodes41, but that does not contact first contact electrodes41of a second group of first contact electrodes. In the part of the semiconductor arrangements illustrated inFIGS. 2 and 3one of the first contact electrodes41is not contacted by the second contact electrode43. The first group of first contact electrode includes at least two first contact electrode, and may include up to 100 and more transistor cells.

The second contact electrode43is a planar electrode that is arranged in a second electrode plane above the first electrode plane. The thickness of the second electrode42is, for example, in the range between 0.5 μm and 1 μm. In the example according toFIGS. 2 and 3an insulation layer52is arranged between the first and the second contact plane. The second contact electrode43contacts the first electrodes41of the first group through contact plugs44, with these contact plugs44being arranged in vias that extend through the insulation layer52from the second contact electrode43to the first contact electrodes41of the first group. The transistor cells30that are contacted by first contact electrodes41of the first group form the load transistor10. The second contact electrode43is the second load terminal13of the load transistor10. The transistor cells30that are contacted by the first contact electrodes41of the second group form the sense transistor20. The first contact electrodes of the second group are electrically connected with each other (not illustrated) and form the second load terminal23of sense transistor20.

Referring toFIG. 8that illustrates a lateral cross section in a second section plane B-B (seeFIGS. 1 and 2) contact plugs44—or vias in which the contact plugs are arranged—may have a rectangular geometry, a circular geometry or—in case of stripe-shaped first contact electrodes41—a stripe-like geometry.

The ratio between the number of transistor cells of the sense transistor20and the number of transistor cells of the load transistor10is the proportionality factor between the sense current I20and load current I10. This ratio is, for example, in a range between 1:104(1:E4) to 1:106(1:E6).

In the present example the second load terminals13,23of the two transistors10, are formed using first and second electrodes41,43in two electrode layers. In general it would be possible to form the two second load terminals13,23by using only one electrode layer that is split in two electrodes: a first electrode that contacts the transistor cells of the load transistor; and a second electrode that contacts the transistor cells of the sense transistor. However, splitting the electrode layer may involve the use of chemical substances that diffuse into the semiconductor body100and that may influence the threshold voltage of the transistor cells. In one embodiment transistor cells that are arranged below the edges of these electrodes can be influenced by such process. Since the number of transistor cells of the load transistor is usually much higher than the number of transistor cells of the sense transistor the proportion of transistor cells that are negatively influenced by splitting the electrode layer is much higher for the sense transistor than for the load transistor. Altogether this results in different threshold voltages of the sense transistor and the load transistor.

When producing the transistor arrangement according toFIGS. 2 and 3the groups of transistor cells that are contacted by the first contact electrodes41are influenced by the process of producing the first electrodes41in identical manner. In this connection “a group of transistor cells that are contacted by the first contact electrodes41” are the transistor cells that are connected by one first contact electrode. These groups include two transistors in the examples according toFIGS. 2 and 3. The groups of transistor cells that are contacted by the individual first contact electrodes41do therefore have identical electrical characteristics. If there is a further influence on the device characteristics of these transistor cells by forming the second insulation layer52, then these transistor cells are influenced by forming this insulation layer52in the same manner. Producing vias extending through the second insulation layer52to the first electrodes41of the first group does not or does only slightly influence the transistor cells below these first electrodes41of the first group. Also producing the second contact electrode43on top of the second insulation layer52and in the vias44does not, or does only slightly, influence the device characteristics of the transistor cells.

In case each of the first contact electrodes41contacts the same number of transistor cells, with the different cells having the same size, then the ratio between the number of first contact electrodes in the second group is equal to the proportionality factor between the load and the sense current. In the transistor arrangement according to the present example groups of transistor cells that are contacted by the individual first electrodes41do therefore have identical device characteristics. Thus, a first arrangement of transistor cells that are contacted by the first electrodes41of the first group and a second arrangement of transistor cells that are contacted by the first electrodes41of the second group have identical device characteristics. The transistor cells of the first arrangement form the load transistor10, and the transistor cells of the second arrangement form the sense transistor20, so that the load and the sense transistor10,20have identical device characteristics.

The geometry of the first contact electrodes41is adapted to the geometry of the transistor cells. In case of stripe-cells the first contact electrodes41have a stripe-like geometry.

FIG. 9illustrates an example of a transistor arrangement having stripe-like contact electrodes41by way of a cross section through the transistor arrangement in a horizontal section plane B-B. For illustration purposes only a small number of first contact electrodes41are illustrated inFIG. 9. In reality dependent on the number of transistor cells30the arrangement may include up to several ten thousand or up to several hundred thousand first contact electrodes41. The second contact electrode43is illustrated in dash-dotted lines inFIG. 9. The first contact electrodes41of the second group that are not contacted by the second electrode43are shaded inFIG. 9. The second contact electrode43covers the complete transistor cell area. For contacting the first electrodes41of the second group, and for connecting these first electrodes with each other, these first electrodes may extend in a lateral direction beyond the second electrode43, as it is illustrated inFIG. 9. These first electrode of the second group together form the second load terminal23of the sense transistor20.

In the example according toFIG. 9the transistor cells that are contacted by the first electrodes41of the first group and the first electrodes41of the second group each extend from edge to edge of the transistor cell area. However, referring toFIGS. 10 and 11the stripe-shaped transistor cells may be separated in two sub-cells, where a first sub-cell is connected by a first contact electrode41of the first group, while a second sub-cell is contacted by a first contact electrode41of the second group.FIG. 10illustrates a horizontal section in section plane B-B of the overall arrangement.FIG. 11illustrates a section in section plane A-A in an area in which the two sub-cells are arranged next to each other.

In a transistor arrangement having trench transistor cells with a stripe-like geometry the trenches with the gate electrodes may extend beyond the first contact electrodes41in a lateral direction, where the gate electrodes33may be contacted in those areas that are not overlapped by the first contact electrodes41.FIG. 12illustrates a section in section plane A-A of such arrangement, where inFIG. 12only the gate electrodes33are illustrated. Illustrated in dashed lines are the first contact electrodes41, which in this example do not completely overlap gate electrodes33. Gate electrodes33are electrically connected with each other in the area that is not overlapped by the first contact electrodes41and the second electrode43(not illustrated inFIG. 12). These gate electrodes33may be contacted with each other using a trench that runs perpendicular to the trenches with the gate electrodes33and that includes a contact electrode contacting the gate electrodes33in the individual trenches. The gate electrodes33that are connected with each other in this manner form the control electrode1of the transistor arrangement.

Further electrode layers may be arranged on top of the semiconductor arrangement, for example to contact the gate terminal or for integrating logic circuitry.

As an example, a third electrode layer71may be arranged above the second electrode43and insulated from second electrode43by a further insulation layer53. Third electrode71forms the control electrode1and contacts the different gate electrodes31through contact plugs46that extend in a vertical direction to the gate electrodes33and that are insulated from the second electrode43and the first electrodes41by insulation layers54that surrounds the contact plugs46.

A method for producing a semiconductor arrangement according toFIG. 2will now be illustrated with reference toFIGS. 14A to 14G. these figures illustrate cross sections through the semiconductor arrangement during different method steps of producing the semiconductor arrangement.

Referring toFIG. 14Aa semiconductor body100is provided in which a number of transistor cells30is integrated. These transistor cells may have any transistor cell geometry as discussed above.

In next method processes that are illustrated inFIGS. 14B and 14C, contact plugs42that contact the source zones31and the body zones32of the transistor cells30are produced. These method processes include, for example, depositing a first insulation layer51A on the first side101of the semiconductor body100(seeFIG. 14B). Insulation layer51′ may be an oxide or a nitride layer. Then, vias are produced in the insulation layer51A above source and body zones31,32of the transistor cells30, where these vias are filled with an electrode material for forming the contact plugs42. Forming the contact plugs42may include depositing an electrode material and etching or polishing the contact material down to the insulation layer51A. Contact plugs may be formed of a metal, like, for example, aluminum, copper, tungsten, . . . .

Referring toFIG. 14Da first electrode layer41′ is deposited on the contact plugs42and the remaining sections of the first insulation layer. The material of the first electrode layer may correspond to the material of the contact plugs. However, any other electrically conducting material may be used as well. The contact plugs42and the first electrode layer41′ may be formed in one process step, in which an electrode material is deposited in the vias of the insulation layer51′ and on top of insulation layer51′.

Referring toFIG. 14Ethis first electrode layer41′ is split in different pieces, with each of these pieces forming one of the first electrodes41. Splitting first electrode layer41′ into pieces may involve etching trenches into the electrode layer41′ and filling these trenches with an electrically insulating material. Filling these trenches with the insulating material may include depositing a second insulating layer51″ and etching or polishing the deposited material down to the first electrodes. The second insulating layer51″ may be comprised of the same material as the first insulating layer51′. The remaining sections of the first and second insulation layers51′,51″ form the insulation regions51according toFIGS. 2 and 3that insulate the first electrodes41from each other and the gate electrodes33.

Referring toFIG. 14Fa further insulation layer52is deposited on the first electrodes41. This layer may be comprised of the same material as first and second insulation layers51′,51″.

Referring toFIG. 14Gvias are formed in the further insulation layer52above the first contact electrodes41of the first group.

Having produced the vias in the second insulation layer52a further electrode layer is deposited, this further electrode layer forming the second contact electrode43(illustrated inFIG. 2).