An electro-optical waveguide modulator device includes a seed layer on a substrate, the seed layer having a first crystallographic plane aligned with a surface of the seed layer, an electro-optical channel extending in a first direction on the seed layer and having a second crystallographic plane aligned with the surface of the seed layer, an insulator layer on both sides of the electro-optical channel on the substrate in a second direction perpendicular to the first direction, an electrode barrier layer on the electro-optical channel and the insulator layer, and one or more of electrodes extending in the second direction. The seed layer and the insulator layer each comprise material having a refractive index that is lower than the electro-optical channel.

BACKGROUND

Field

Embodiments of the present disclosure generally relate to electro-optical devices, and more specifically, to thin-film electro-optical waveguide modulator devices integrated in a silicon platform.

Description of the Related Art

Silicon photonics has become a platform for dense and low-cost integrated photonic circuits for a wide range of applications. Adding an electro-optical (EO) material, such as barium titanate (BaTiO3, BTO) to silicon photonics enables a number of novel active photonic devices, such as modulators and switches, that could reduce power consumption and increase operation speed. Electro-optical devices integrated in a silicon platform, including electro-optical (EO) waveguide phase modulators, can also be key elements in emerging quantum technologies such as all-optical quantum computing using a single photon source and a single photon detector.

However, the development of architectures for integrated electro-optical devices that are scalable and replicable remains a missing element for progress of near-future quantum technologies.

SUMMARY

Embodiments of the present disclosure generally relate to an electro-optical waveguide modulator device. The electro-optical device includes a seed layer on a substrate, the seed layer having a first crystallographic plane aligned with a surface of the seed layer, an electro-optical channel extending in a first direction on the seed layer and having a second crystallographic plane aligned with the surface of the seed layer, an insulator layer on both sides of the electro-optical channel on the substrate in a second direction perpendicular to the first direction, an electrode barrier layer on the electro-optical channel and the insulator layer, and one or more of electrodes extending in the second direction. The seed layer and the insulator layer each comprise material having a refractive index that is lower than the electro-optical channel.

Embodiments of the present disclosure also relate to a method of forming a substrate having a crystallographically aligned surface. The method includes depositing a seed layer on a substrate through a process selected from an ion beam assisted deposition process and a pulsed laser deposition process, and annealing the deposited seed layer to align a first crystallographic plane of the seed layer with a surface of the seed layer.

Embodiments of the present disclosure further relate to a method of forming an electro-optical waveguide modulator device. The method includes depositing a seed layer on a substrate through a process selected from an ion beam assisted deposition process and a pulsed laser deposition process, annealing the deposited seed layer to align a first crystallographic plane of the seed layer with a surface of the seed layer, depositing a layer of an electro-optical material on the seed layer, annealing the deposited layer of the electro-optical material to align a second crystallographic plane of the layer of the electro-optical material with the surface of the seed layer, and patterning the layer of the electro-optical material to form an electro-optical channel extending in a first direction on the seed layer. The seed layer comprises material having a refractive index that is lower than the electro-optical channel.

DETAILED DESCRIPTION

Embodiments of the present disclosure generally relate to electro-optical (EO) devices, and more specifically, to thin-film electro-optical (EO) waveguide modulator devices integrated in a silicon platform.

In the embodiments described herein, thin film electro-optical (EO) waveguide phase modulators integrated in a silicon platform are of high quality having an EO material with crystallographic orientations aligned such that the EO material has a high electro-optic coefficient (e.g., Pockel Coefficient>700 pm/V), leading to high sensitivity to an applied electric field. The alignment of crystallographic orientations of the EO material and an underlying seed layer formed on a substrate is performed by annealing processes, such as a laser anneal process, at high temperatures as crystallographic orientations of the EO material and the seed layer as deposited are not aligned. The anneal processes are performed without breaking vacuum while the substrate is transferred between a pre-clean chamber for pre-cleaning the substrate and a process chamber for depositing the EO material and/or the seed layer.

Such thin film electrode waveguide phase modulators can have different refractive indices depending on the strength of an applied electric field to modulate phases of incident light, and thus, when combined with optical fibers, or single photon sources and single photon detectors, can be used as enabling elements in the next generation optical communications and quantum technologies.

Conventionally, electro-optical (EO) devices are fabricated on bulk lithium niobate (LiNbO3) single crystals and are combined with other optical and electronic components due to their ability to be grown as large and high quality single crystals. Recent developments towards integrated and compact optical systems on silicon call for fabrication and characterization of thin film optical and electro-optical (EO) components (e.g., waveguides, sources, modulators, and detectors) with ferroelectric oxide materials having much higher electro-optic coefficients, such as barium titanate (BaTiO3, BTO), than LiNbO3. In the embodiments described herein, examples of thin film electro-optical (EO) waveguide phase modulators formed on a silicon based platform are described. However, the present disclosure is not limited to use in this particular application and can be applied to other thin film electro-optical (EO) components.

FIG.1is a schematic diagram of an electro-optical (EO) waveguide modulator100according to one or more embodiments.FIG.2illustrates a flow diagram of a processing sequence200used to fabricate an EO waveguide modulator100according to one or more embodiments. The processing sequence200to fabricate the EO waveguide modulator100on a substrate102are performed in a substrate processing system, such as a cluster tool300described below in conjunction withFIG.3.

As used herein, the term “substrate” refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be disposed for forming the EO waveguide modulator100thereon. The substrate102may be a (001) silicon wafer, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, indium phosphide, germanium, gallium arsenide, gallium nitride, quartz, fused silica, glass, or sapphire. Moreover, the substrate102is not limited to any particular size or shape. The substrate102can be a round wafer having a 200 mm diameter, a 300 mm diameter or other diameters, such as 450 mm, among others. The substrate102can also be any polygonal, square, rectangular, curved or otherwise non-circular workpiece, such as a polygonal glass substrate.

In block202of the processing sequence200, a surface of the substrate102is pre-cleaned to remove native oxides or other sources of contaminants prior to fabricating the EO waveguide modulator100thereon. For example, the substrate102may be pre-cleaned by a wet etch process using a dilute hydrofluoric acid (dHF) etching solution at a temperature between about 24° C. and about 50° C. Alternatively, the substrate102may be pre-cleaned by a vapor etch process in a pre-clean chamber, such as a SICONI™ chamber, which is available from Applied Materials, Inc., Santa Clara, Calif. The pre-clean gas may be a mixture of nitrogen (N2) and hydrogen (H2) gases. A purge gas or carrier gas, such as argon (Ar), can also be added to the pre-clean gas mixture.

The EO waveguide modulator100includes a seed layer104formed on the substrate102. The seed layer104is formed of magnesium oxide (or magnesia, MgO) in the X-Y plane and has a thickness in the Z-direction of between about 0.25 nm and about 15 nm. The seed layer104is formed to have the (001) crystallographic plane parallel to the X-Y plane that is aligned with the crystallographic plane of the underlying substrate102(e.g., (001) silicon wafer). In some embodiments, the seed layer104is formed by depositing MgO on the pre-cleaned substrate102by a physical vapor deposition (PVD) process with a plasma based on a mixture gas including argon (Ar) and oxygen (02) gases at room temperature, in which a target housed in the PVD chamber is comprised of MgO. In block204of the processing sequence200, the seed layer104is formed by other chemical deposition processes, such as a chemical vapor deposition (CVD) process, metal organic chemical vapor deposition (MOCVD), an atomic layer deposition (ALD) process, or a molecular beam epitaxy (MBE) process. However, the seed layer104as deposited may include multiple domains of crystallites of varying sizes and crystallographic orientations, such as (200), (220), and (222) of the body-centered cubic (BCC) or the face-centered cubic (FCC) crystal lattice structure, and is thus further treated such that the seed layer104includes larger domains of MgO crystallites having a (001) crystallographic plane parallel to the X-Y plane. For example, MgO may be further deposited on the substrate102through an ion beam assisted deposition (IBAD) process. In an IBAD process, as MgO is deposited, MgO is simultaneously etched by a beam of high energy (about 300 eV and about 2000 eV) ions such as argon ions (Ar+) or oxygen ions (0+) depending on the crystallographic orientations of the MgO crystallites. When an ion beam is incident at a 45° angle with respect to the surface of the seed layer104(i.e., the X-Y plane), crystallites having a (001) crystallographic plane (out-of-plane to the ion beam) and a (101) crystallographic plane (in-plane and parallel to the ion beam) are preferentially formed while crystallites having other planes are removed. In some embodiments, the seed layer104is formed via a pulsed laser deposition (PLD) process.

In block206of the processing sequence200, the seed layer104may be further annealed to recreate crystalline structures from domains that are not yet aligned with the crystallographic plane (001), by a laser anneal process, a rapid thermal anneal (RTA) process, a furnace anneal process, or an anneal process in a vacuum anneal chamber. In the laser anneal process, the surface of the seed layer104is irradiated in an atmosphere containing oxygen (O2), hydrogen (H2), and nitrogen (N2) with a purge gas or carrier gas, such as argon (Ar), for a duration of between about 0.1 seconds and about 24 hours at a temperature of between about 700° C. and about 1100° C. at atmospheric pressure. In the RTA process, the anneal process lasts for a duration of between about 0.1 seconds and about 24 hours in an atmosphere containing oxygen (O2), hydrogen (H2), and nitrogen (N2) with a purge gas or carrier gas, such as argon (Ar) at a temperature of between about 200° C. and about 1000° C. at a high vacuum pressure. The anneal process may be a furnace anneal in a rapid thermal processing (RTP) chamber, in which the seed layer104is heated to a temperature of between about 200° C. and about 1000° C. in an atmosphere containing oxygen (O2), hydrogen (H2), and nitrogen (N2) with a purge gas or carrier gas, such as argon (Ar) for between about 0.1 seconds and about 24 hours at a high vacuum. The anneal process may be performed in a vacuum anneal or high pressure chamber at a temperature of about 1000° C. for a time duration of between about 5 minutes and about 90 minutes with a purge gas or carrier gas, such as argon (Ar).

In another embodiment, which can be combined with other embodiments described herein, the deposition process in block204and the anneal process in block206are repeated until a desired thickness of the seed layer104having a desired domain size of MgO crystallites having crystallographic plane (001) is achieved.

The EO waveguide modulator100further includes an EO channel106formed in the X-direction on the (001) crystallographic plane of the seed layer104. The EO channel106defines a waveguide region of the EO waveguide modulator100. The EO channel106is formed of material exhibiting a Pockels effect (also referred to as linear EO effect) that changes the refractive index proportionally to an electric field applied to the material. In some embodiments, the EO channel106is formed of barium titanate (BaTiO3, BTO) with the c-axis of BTO oriented in the Z-direction. Bulk BTO has the largest Pockels coefficient (>1000 pm/V) among well-known materials. The EO channel106has a width in the Y-direction of between about 4 nm and about 500 nm, and a thickness in the Z-direction of between about 100 nm and about 300 nm. The EO channel106is fabricated by forming a layer of BTO on the seed layer104and patterning the layer of BTO on the seed layer104. In block208of the processing sequence200, the layer of BTO may be formed by deposition processes, such as a PVD process, a CVD process, or an ALD process, or epitaxially grown. In block210of the processing sequence200, the layer of BTO as deposited may be annealed, substantially similarly to the annealing processes in block206, to form large domains of BTO crystallites having a (001) crystallographic plane in the X-Y plane (i.e., the c-axis along the Z-axis). In some embodiments, the EO channel106is formed of barium strontium titanate (BaO4SrTi, BSTO). In another embodiment, which can be combined with other embodiments described herein, the deposition process in block208and the anneal process in block210are repeated until a desired thickness of the seed layer104having a desired domain size of BTO crystallites having crystallographic plane (001) is achieved.

In block212of the processing sequence200, the layer of BTO along with the underling seed layer104is etched to form the EO channel106.

The lattice mismatch between cubic MgO (a=4.2313 Å at 300 K) and tetragonal BTO (a=3.992 Å, c=4.036 Å, at 300 K) is quite large. However, MgO is often used as the seed layer104for its low refractive index (about 1.7 at 1.55 μm wavelength) and optical transparency. The seed layer104optically separates the EO channel106from an underlying silicon substrate102, as the low refractive index of the seed layer104(that is lower than the refractive index of the EO channel106, which is about 2.3 when no electric field applied at 1.55 μm wavelength) insures confinement of light in the Z-direction within the EO channel106.

In some embodiments, the seed layer104is formed of strontium titanate (SrTiO3, STO), and the EO channel106is formed of lanthanum titanate (La2Ti2O7, LTO).

The EO waveguide modulator100further includes insulator layers108on the substrate102on both sides of the EO channel106in the X-direction. The insulator layers108may be formed of dielectric material having low refractive index, such as silicon oxide (SiO2, refractive index of about 1.4 at 1.55 μm wavelength), silicon nitride (Si3N4, refractive index of about 2.0 at 1.55 μm wavelength), low-k, ultra-low-k, or extreme-low-k dielectric materials, SiCH, SiCNH, SiCONH, black diamond, porous or airgap materials. In block214of the processing sequence200, the insulator layers108are formed by depositing a blanket layer of the dielectric material on the exposed surface of the seed layer104and the EO channel106by deposition processes, such as a PVD process, a CVD process, or an ALD process, and subsequently partially etching back or chemically polishing the blanket layer of the dielectric material, such that the EO channel106is exposed and planarized with the insulator layers108.

Over the EO channel106and the insulator layers108, the EO waveguide modulator100further includes an electrode barrier layer110. The electrode barrier layer110is formed of material selected from tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), and tantalum oxide (Ta2O5). The barrier layer110has a thickness in the Z-direction of between about 0.25 nm and about 15 nm. In block216of the processing sequence200, the electrode barrier layer110may be formed by deposition processes, such as a PVD process, a CVD process, or an ALD process.

The EO waveguide modulator100further includes one or more of coplanar electrodes112extending in the Y-direction formed on the sides of the EO channel106. The electrodes112are formed of nickel (Ni), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), copper (Cu), or cobalt (Co). Each of the electrodes112has a width in the Y-direction of between about 0.4 nm and about 500 nm, and a thickness in the Z-direction between about 1 nm and about 1000 nm, for example, about 100 nm. When a DC or low-frequency voltage is applied to the electrodes112, the refractive index of the EO channel106changes, resulting in modulation of phase of light propagating through the waveguide region of the EO channel106. In block218of the processing sequence200, the electrodes112are formed by depositing a layer of metal such as nickel (Ni), tungsten (W), ruthenium (Ru), aluminum (Al), molybdenum (Mo), copper (Cu), or cobalt (Co) by deposition processes, such as a PVD process, a CVD process, or an ALD process, patterning the deposited layer of metal. The electrodes112may be annealed, substantially similarly to the annealing processes in block206.

FIG.3illustrates a substrate processing system300in which the EO waveguide modulator100may be fabricated according to one or more embodiments. Examples of the substrate processing system300are the ENDURA® system and the Centura® system, commercially available from Applied Materials, Inc. of Santa Clara, Calif. Alternatively, other substrate processing systems may be also be modified in accordance with the present disclosure.

The substrate processing system300includes a vacuum-tight processing platform302, a factory interface304, and a controller306. Further, the substrate processing system300may also be referred to as a cluster tool or multi-chamber processing system.

The processing platform302includes one or more processing chambers. For example, the processing platform302may include processing chambers308,310,312,314,316,318,320,322,324. Further, the processing platform302includes one or more transfer chambers. For example, as is illustrated inFIG.3, the processing platform302includes transfer chambers326,328. The processing platform302may also include one or more pass-through chambers that allow a substrate to be transferred between transfer chambers. For example, pass-through chambers330,332may allow a substrate to be transferred between the transfer chambers326and328.

The processing platform302may also include one or more load lock chambers. For example, as is illustrated inFIG.3, the processing platform302includes load lock chambers334,336. The load lock chambers334,336may be pumped down to be operated under a vacuum before transferring substrates from the factory interface304to the transfer chamber326.

The factory interface304includes one or more docking stations338, one or more factory interface robots340, and a charging station342. The docking stations338include one or more front opening unified pods (FOUPs)344A,344B,344C,344D. The factory interface robot340may be capable of linear and rotational movement illustrated by arrows346. Further, the factory interface robot340may transfer substrates between the FOUPs344A-D, the load lock chambers334,336, and the charging station342. The substrate may be transferred by the factory interface robot340from the charging station342to one or more of the load lock chambers334,336for processing the substrate within the processing platform302. Subsequently, the processed substrate may be transferred from the load lock chambers334,336to one of the FOUPs344A-D by the factory interface robot340.

The transfer chamber326includes a transfer robot348. The transfer robot348transfers substrates to and from the load lock chambers334,336to and from the processing chambers308,310,312,314, and to and from pass-through chambers330,332. The pass-through chambers330and332may be utilized to maintain vacuum conditions while allowing substrates to be transferred within the processing platform302between the transfer chambers326and328. The transfer chamber328includes a transfer robot350. The transfer robot350transfers substrates between the pass-through chambers330,332and the processing chambers316,318,320,322,324, and among the processing chambers316,318,320,320,322,324.

The processing chambers308,310,312,314,316,318,320,322,324may be configured in any manner suitable to process a substrate. For example, the processing chambers308,310,312,314,316,318,320,322,324may be configured to deposit one or more material layers and apply one or more cleaning processes to a substrate.

The processing chambers, e.g., the processing chambers308,310,312,314may be configured to perform a pre-clean process to eliminate contaminants and/or degas volatile components from a substrate prior to transferring the substrate into another process chamber. The processing chamber322may be configured to deposit one or more layers on a substrate. Further, the processing chamber324may be configured to position a mask (e.g., a shadow mask) on a substrate before the substrate is transferred to one or more of the processing chambers316,318,320,322and unload a mask from a substrate after processing within one or more of the processing chambers316,318,320,322. The processing chambers316,318,320,322may be configured to deposit materials using a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) (e.g., sputtering process or evaporation process), among others. The processing chambers316,318,320can be Rapid Thermal Annealing (RTA) chambers, or Rapid Thermal Process (RTP) chambers, that can anneal substrates at vacuum or near vacuum pressures. An example of an RTA chamber is a RADIANCE™ chamber, commercially available from Applied Materials, Inc., Santa Clara, Calif. Alternatively, the processing chambers316,318,320can be W×Z™ deposition chambers capable of performing high temperature CVD deposition, annealing processes, or in situ deposition and annealing processes.

The controller306is configured to control the components of the substrate processing system300. The controller306may be any suitable controller for controlling the operation of one or more of the processing chambers308,310,312,314,316,318,320,322,324, the transfer chambers326and328, pass-through chambers330,332, and the factory interface304. For example, the controller306may be configured to control the operation of the transfer robot348, the transfer robot350, and the factory interface robot340. The controller306includes a central processing unit (CPU)352, a memory354, and support circuits356. The CPU352may be any general purpose computer processor that may be utilized in an industrial environment. The support circuits356are coupled to the CPU352and may include cache, clock circuits, input/output subsystems, power supplies and the like. Software routines may be stored within the memory354. The software routines may be executed by the CPU352and thus be adapted to cause various components within the substrate processing system300to perform one or more of the methods described herein. Alternatively, or additionally, one or more of the software routines may be executed by a second CPU (not illustrated). The second CPU may be part of the controller306or remote from the controller306.

One or more processing chambers308,310,312,314,316,318,320,322,324, one or more transfer chambers326and328, one or more pass-through chambers330,332, and/or the factory interface304may have a dedicated controller or controllers (not shown) configured to control at least a portion of the methods disclosed herein. The dedicated controllers may be configured similar to the controller306and may be coupled with the controller306to synchronize processing of a substrate within the substrate processing system300.

In the embodiments described herein, thin film electro-optical (EO) waveguide phase modulators integrated in a silicon platform are of high quality having an electro-optical material with crystallographic orientations aligned. Such thin film electrode waveguide phase modulators, when combined with optical fibers, or single photon sources and single photon detectors, can be used as enabling elements in the next generation optical communications and quantum technologies.