Wafers having III-Nitride and diamond layers

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A first SiC layer is formed on a silicon substrate, and using a carbon containing gas, a surface of the first SiC layer is carbonized to form carbon particles on the SiC layer. Then, a diamond layer is grown on the carbonized surface, where the carbon atoms act as seed particles for growing the diamond layer. A second SiC layer is formed on the diamond layer and a semiconductor layer having III-Nitride compounds is formed on the second SiC layer. Then, the silicon substrate and the first SiC layer are removed.

BACKGROUND

A. Technical Field

The present invention relates to semiconductor wafers, and more particularly, to wafers having a diamond layer and a semiconductor layer including III-nitride semiconductor material and methods for fabricating the wafers.

B. Background of the Invention

Gallium Nitride (GaN) or AlGaN or AlN has electrical and physical properties that make it highly suitable for radio frequency (RF) devices, such as high electron mobile transistors (HEMT). In general, an RF device produces a large amount of heat energy during operation, requiring a mechanism to extract the heat energy from the device to avoid device failure. Diamond is known to have a good thermal conductivity and can be used as material for a substrate on which the AlGaN/GaN layer is formed.

One conventional approach to form a AlGaN/GaN HEMT layer on a diamond layer is depositing AlGaN/GaN HEMT layer directly on a silicon substrate, removing the silicon substrate and forming a diamond layer on the AlGaN/GaN HEMT layer. This approach is attractive for its low manufacturing cost. Also, the material property of silicon enables producing large silicon wafers with low surface roughness, which in turn enables producing large AlGaN/GaN HEMT wafers. In addition, the silicon substrate can be removed relatively easily by conventional wafer processing techniques. However there are still difficulties in growing a high-quality AlGaN/GaN layer directly on a silicon substrate due to the large lattice mismatch between AlGaN/GaN and silicon. As such, there is a need for methods for fabricating wafers that have a diamond layer and an AlGaN/GaN layer with enhanced material property.

SUMMARY OF THE DISCLOSURE

In embodiments, a wafer includes: a semiconductor layer including a III-Nitride compound; a SiC layer formed on the semiconductor layer; an intermediate layer formed on the SiC layer; a seed layer formed on the intermediate layer and including diamond particles; and a diamond layer formed on the seed layer.

In embodiments, a method for forming a wafer includes: forming a SiC layer on a silicon substrate; forming a semiconductor layer including a III-Nitride compound on the SiC layer; removing the silicon substrate to expose a surface of the SiC layer; forming an intermediate layer on the exposed surface of the SiC layer; forming a seed layer on the intermediate layer, the seed layer including diamond particles; and growing a diamond layer on the seed layer.

In embodiments, a wafer includes: a semiconductor layer including a III-Nitride compound; an intermediate layer formed on the semiconductor layer; a seed layer formed on the intermediate layer and including diamond particles; and a diamond layer formed on the seed layer.

In embodiments, a method for forming a wafer includes: forming a SiC layer on a silicon substrate; forming a semiconductor layer including a III-Nitride compound on the SiC layer; removing the silicon substrate and the SiC layer; forming an intermediate layer on the SiC layer; forming a seed layer on the intermediate layer, the seed layer including diamond particles; and growing a diamond layer on the seed layer.

In embodiments, a wafer includes: a diamond layer having an oriented crystal structure; a SiC layer formed on the diamond layer; and a semiconductor layer including a III-Nitride compound and formed on the SiC layer.

In embodiments, a method for forming a wafer includes: forming an intermediate layer on a silicon substrate; forming a seed layer on the intermediate layer, the seed layer including diamond particles; growing a diamond layer on the seed layer; forming a SiC layer on the diamond layer; forming a semiconductor layer including a III-Nitride compound on the SiC layer; and removing the silicon substrate, seed layer and intermediate layer.

In embodiments, a method for forming a wafer includes: forming a first SiC layer on a silicon substrate; carbonizing a surface of the first SiC layer; growing a diamond layer on the carbonzied surface of the first SiC layer; forming a second SiC layer on the diamond layer; forming a semiconductor layer on the second SiC layer, the semiconductor layer including a III-Nitride compound; and removing the silicon substrate and the first SiC layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One skilled in the art shall recognize: (1) that certain steps may optionally be performed; (2) that steps may not be limited to the specific order set forth herein; and (3) that certain steps may be performed in different orders, including being done contemporaneously.

Elements/components shown in diagrams are illustrative of exemplary embodiments of the disclosure and are meant to avoid obscuring the disclosure. Reference in the specification to “one embodiment,” “preferred embodiment,” “an embodiment,” or “embodiments” means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the disclosure and may be in more than one embodiment. The appearances of the phrases “in one embodiment,” “in an embodiment,” or “in embodiments” in various places in the specification are not necessarily all referring to the same embodiment or embodiments. The terms “include,” “including,” “comprise,” and “comprising” shall be understood to be open terms and any lists that follow are examples and not meant to be limited to the listed items. Any headings used herein are for organizational purposes only and shall not be used to limit the scope of the description or the claims. Furthermore, the use of certain terms in various places in the specification is for illustration and should not be construed as limiting.

FIGS. 1-3show an exemplary process for forming a wafer that includes a diamond layer and a III-Nitride layer according to embodiments of the present disclosure. As depicted, the wafer100may include a silicon substrate102, and a SiC layer104and a III-Nitride layer106may be formed on the silicon substrate102.

In embodiments, the SiC layer104may include cubic silicon carbide (3C—SiC) and formed on the silicon substrate102by conventional wafer processing techniques, such as low pressure chemical vapor deposition (LPCVD) technique. In embodiments, the III-Nitride layer106may include one or more layers that each include a GaN compound, such as hexagonal AlGaN/GaN or cubic AlGaN/GaN. For the purpose of brevity, in the following sections, a III-Nitride layer may collectively refer to one or more layers that each include a III-Nitride compound. In embodiments, the III-Nitride layer106may be formed on the SiC layer104by conventional wafer processing techniques, such as metal-organic chemical vapor deposition (MOCVD) technique.

In embodiments, various electronic components, such as transistors, may be formed in the III-Nitride layer106of the wafer100by conventional wafer processing techniques. The lattice mismatch between III-Nitride compound (or, shortly III-Nitride) and SiC is lower than the lattice mismatch between III-Nitride and Si. As such, compared to a case where the SiC layer104is not disposed between the III-Nitride layer106and the silicon substrate102, the III-Nitride layer106on the SiC layer104has an improved material property for the electronic components.

In embodiments, after processing the III-Nitride layer106, the silicon substrate102may be removed by conventional wafer processing techniques, such as grind/lap and polishing, to form the wafer107. Then, as depicted inFIG. 3, the wafer107may be flipped over and an intermediate layer108, a seed layer110and a diamond layer112may be sequentially formed on the SiC layer104.

If the diamond layer112is directly attached to the SiC layer104, the mismatch of coefficients of thermal expansion (CTE) between the diamond layer112and the SiC layer104may generate stress on the SiC layer104during formation of the diamond layer112. In embodiments, the material and thickness of the intermediate layer108may be selected to mitigate the stress due to the mismatch of CTEs. In embodiments, the intermediate layer108may be formed of dielectric material, such as poly-Si or SiO or SiN.

In embodiments, to form the seed layer110, a wafer including the layers106,104and108may be submerged in an aqueous suspension of diamond nano particle (diamond seed particles) so that the top surface of the intermediate layer108may be in direct contact with the aqueous suspension. The diamond particles may be adsorbed onto the surface of the intermediate layer108, to form the seed layer110. Depending on the exposure time in the suspension and the concentration of the diamond particles, the density of the particles in the seed layer110may be determined. Since the diamond particles may adhere to the intermediate layer108better than to the SiC layer104, the intermediate layer108may enhance the particle number density of the seed layer110.

In embodiments, the intermediate layer108may protect the SiC layer104and the III-Nitride layer106from thermal damages during the process for forming the seed layer110and diamond layer112. In addition, the intermediate layer108may electrically insulate the SiC layer110from the diamond layer112. In embodiments, the diamond layer112may be formed by chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. In embodiments, the diamond layer112may have a poly-crystal structure.

In embodiments, the III-nitride wafer113may be diced and used in various electrical devices. Since the electronic component formed in the III-Nitride106of the wafer111may generate heat energy during operation of the electrical devices and the heat energy may be transferred to diamond layer112via the SiC layer104, intermediate layer108, and seed layer110. Since SiC has lower thermal conductivity than diamond, the heat flow from the III-Nitride layer106to the diamond layer112may be reduced if the SiC layer104is too thick. In embodiments, the thickness of the SiC layer104may be minimized so that the heat flow to the diamond layer112is enhanced while the SiC layer104may be still thick enough to mitigate the lattice mismatch between the Si substrate102and the III-Nitride layer106.

FIG. 4shows a flowchart400of an exemplary process for fabricating the wafers inFIGS. 1-3. At steps402and404, a SiC layer may be formed on a silicon substrate and a III-Nitride layer is formed on the SiC layer, respectively. Since the lattice mismatch between the SiC and III-nitride is lower than the lattice mismatch between Si and III-nitride, the SiC layer may enhance the material property of the III-nitride layer. At step406, the Si substrate may be removed. Then, at step408, an intermediate layer, seed layer and a diamond layer may be sequentially formed on the SiC layer. Optionally, the III-Nitride wafer may be device processed so that electrical components, such as transistors, may be formed in the III-Nitride layer by conventional wafer processing techniques at step410.

FIGS. 5-7show an exemplary process for forming a wafer that includes a diamond layer and a III-Nitride layer according to embodiments of the present disclosure. As shown inFIG. 5, the wafer500may have the similar structure as the wafer100inFIG. 1. Also, the SiC layer504and III-Nitride layer506may be made of similar materials and have similar functions as the SiC layer104and III-Nitride layer106, respectively. Then, the Si substrate502and the SiC layer504may be removed from the substrate500to form the wafer503. Then, a intermediate layer508, a seed layer510and a diamond layer512may be formed on the III-Nitride layer506of the wafer503.

In embodiments, the intermediate layer508, seed layer510and diamond layer512may be formed by similar techniques and have similar structures as their counterparts in the wafer113. The wafer505may be similar to the wafer113, with the difference that the SiC layer504is entirely removed from the wafer500. In embodiments, the SiC layer504may be removed by conventional techniques, such as chemical etching, dry etching, lapping (mechanical grinding) or chemical mechanical polishing (CMP).

Since the wafer505does not include any SiC layer, the heat flow rate from the III-Nitride506to the diamond layer512may be higher than the heat flow rate from the III-Nitride layer106to the diamond layer112, assuming that the intermediate layer508and seed layer510in the wafer513have the same compositions and thicknesses as their counterparts in the wafer113. In embodiments, various electrical components, such as transistors, may be formed in the III-Nitride layer506of the wafer505.

FIG. 8shows a flowchart800of an exemplary process for fabricating the wafers inFIGS. 5-7. At steps802and804, a SiC layer is formed on a silicon substrate and a III-Nitride layer is formed on the SiC layer, respectively. Since the lattice mismatch between the SiC and III-Nitride is lower than the lattice mismatch between silicon and III-Nitride, the SiC layer may enhance the material property of the GaN layer. At step806, the silicon substrate and the SiC layer may be removed. Then, at step808, an intermediate layer, a seed layer and a diamond layer may be sequentially formed on the III-Nitride layer. Optionally, the III-Nitride wafer may be device processed by conventional wafer processing techniques at step810, to thereby form electrical components, such as transistors, in the III-Nitride layer

FIGS. 9-11show an exemplary process for forming a wafer that includes a diamond layer and a III-Nitride layer according to embodiments of the present disclosure. As depicted, the wafer900may include a silicon substrate902, and an intermediate layer904, a seed layer906and a diamond layer908are sequentially formed on the silicon substrate902.

In embodiments, the intermediate layer904may be formed of dielectric material, such as poly-Si or SiN or SiO. In embodiments, to form the seed layer906, a stack of layers including the layers902and904may be submerged in an aqueous suspension of diamond nano particle (diamond seed particles) so that the top surface of the intermediate layer904may be in direct contact with the aqueous suspension. The diamond particles may be adsorbed onto the surface of the intermediate layer904, to form the seed layer906. Depending on the exposure time in the suspension and the concentration of the diamond particles, the density of the particles in the seed layer906may be determined. Since the diamond particles may adhere to the intermediate layer904better than to the Si substrate902, the intermediate layer904may enhance the particle number density of the seed layer906.

In embodiments, the diamond layer908may be formed by chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. In embodiments, the diamond seed particles in the seed layer906may act as seeds for growth of the diamond layer908. In embodiments, the crystal structure of the Si substrate902may be transferred to the diamond layer908so that the diamond layer908may have an oriented crystal structure.

In embodiments, the top surface of the diamond layer908in the wafer900may be polished to generate a mirror-like epi-ready surface and to remove defects on the top surface. In embodiments, chemical mechanical polishing (CMP) technique or mechanical lapping may be used to polish the top surface. Then, as shown inFIG. 10, a SiC layer910may be formed on the polished epi-ready top surface of the diamond layer908and a III-Nitride layer912may be formed on the SiC layer910. In embodiments, the SiC layer910may include cubic silicon carbide (3C—SiC).

The lattice mismatch between III-Nitride and SiC is lower than the lattice mismatch between III-Nitride and diamond. As such, compared to a case where the SiC layer910is not disposed between the III-Nitride layer912and the diamond layer908, the III-Nitride912on the SiC layer910has an improved material property.

In embodiments, the SiC layer910may be deposited on the diamond layer908by conventional wafer processing techniques, such as low pressure chemical vapor deposition (LPCVD) technique. In embodiments, the III-Nitride layer912may be formed by conventional wafer processing techniques, such as MOCVD technique.

In embodiments, electronic components, such as transistors, may be formed in the III-Nitride layer912of the wafer909by conventional wafer processing techniques. Upon forming the electronic components, the Si substrate902, intermediate layer904, and seed layer906may be removed from the wafer909.FIG. 11shows a wafer913that includes three layers: the diamond layer908, SiC layer910and III-Nitride layer912. In embodiments, the wafer913may be diced and used in various electrical devices. The electronic component formed in the III-Nitride912may generate heat energy during operation of the electrical devices and the heat energy may be transferred to diamond layer908via the SiC layer910. Since SiC has lower thermal conductivity than diamond, the heat flow from the III-Nitride layer912to the diamond layer908may be reduced if the SiC layer910is too thick. In embodiments, the thickness of the SiC layer910may be minimized so that the heat flow to the diamond layer908is enhanced while the SiC layer910may be still thick enough to enhance the material property of the III-Nitride layer912.

FIG. 12shows a flowchart1200of an exemplary process for fabricating the wafers inFIGS. 9-11. At step1202, an intermediate layer, a seed layer and a diamond layer may be formed on a Si substrate. Then, at step1204, the top surface of the diamond layer may be polished to remove defects on the top surface and to generate a mirror-like epi-ready surface. At step1206, a SiC layer may be formed on the polished epi-ready surface of the diamond layer and a III-Nitride layer may be formed on the SiC layer. Optionally, the III-Nitride layer1208may be device processed by conventional wafer processing techniques to form electronic components in the III-Nitride layer. Then, at step1210, the Si substrate, intermediate layer and seed layer may be removed.

FIGS. 13-15show an exemplary process for forming a wafer that includes a diamond layer and a III-Nitride layer according to embodiments of the present disclosure. As depicted inFIG. 13, a SiC layer1304may be formed on a Si substrate1302. In embodiments, the SiC layer1304may include cubic silicon carbide (3C—SiC) and formed on the silicon substrate1302by conventional wafer processing techniques, such as low pressure chemical vapor deposition (LPCVD). Then, the top surface of the SiC layer1304may be carbonized by use of a carbon containing gas, such as C2H4or C3H8or C2H2. In embodiments, the wafer1300may be disposed in a thermal chemical vapor deposition reactor (not shown inFIG. 13) and the top surface of the SiC layer1304may be exposed to carbon containing gas, such as C2H4or C3H8or C2H2, causing the top surface of the SiC layer1304to be carbonized.

During the carbonization process, carbon atoms may adhere to the top surface of the SiC layer1304. In embodiments, using the carbon atoms as seed particles, a diamond layer1306may be deposited on the SiC layer1304. In embodiments, the diamond layer1306may be formed by chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. The diamond layer1306may have an oriented crystal structure.

In embodiments, the top surface of the diamond layer1306may be polished to generate a mirror-like epi-ready surface and to remove defects on the top surface. In embodiments, chemical mechanical polishing (CMP) technique or mechanical lapping may be used to polish the top surface.

In embodiments, a SiC layer1308and a III-Nitride layer1310may be sequentially deposited on the diamond layer1306, forming the wafer1305. In embodiments, the SiC layer1308may include cubic silicon carbide (3C—SiC) and formed by conventional wafer processing techniques, such as low pressure chemical vapor deposition (LPCVD) technique. In embodiments, the III-Nitride layer1310may be formed on the SiC layer1308by conventional wafer processing techniques, such as metal-organic chemical vapor deposition (MOCVD).

The lattice mismatch between III-Nitride and SiC is lower than the lattice mismatch between III-Nitride and diamond. As such, compared to a case where the SiC layer1308is not disposed between the III-Nitride layer1310and the diamond layer1306, the III-Nitride1310on the SiC layer1308has an improved material property.

In embodiments, the III-Nitride layer1310of the wafer1305may be device processed to form various electrical components, such as transistors, using conventional wafer processing techniques. In embodiments, upon forming electrical components in the III-Nitride layer1310, the Si substrate1302and the SiC layer1304may be removed by conventional techniques, such as chemical etching, dry etching, lapping (mechanical grinding) or chemical mechanical polishing (CMP). The wafer1309, which includes the diamond layer1306, SiC layer1308, and III-Nitride layer1310, may be diced and used in various electrical devices, such as high electron mobile transistors (HEMT). During operation of the devices, the heat energy generated by the III-Nitride layer1310may be transferred to the diamond layer1306to avoid failure of the devices due to the heat energy.

Since SiC has lower thermal conductivity than diamond, the heat flow from the III-Nitride layer1310to the diamond layer1306may be reduced if the SiC layer1308is too thick. In embodiments, the thickness of the SiC layer1308may be minimized so that the heat flow to the diamond layer1306is enhanced while the SiC layer1308may be still thick enough to enhance the material property of the III-Nitride layer1310.

FIG. 16shows a flowchart1600of an exemplary process for fabricating the wafers inFIGS. 13-15. At step1602, a first SiC layer may be formed on a Si substrate. Then, at step1604, a top surface of the first SiC layer may be carbonized by carbon containing gas, such as C2H4or C3H8or C2H2, causing carbon atoms to adhere to the top surface of the first SiC layer. At step1606, a diamond layer may be formed on the first SiC layer, using the carbon atoms as seed particles for growing the diamond layer. At step1608, a top surface of the diamond layer may be polished to generate a mirror-like epi-ready surface and to remove defects on the top surface.

At step1610, a second SiC layer may be formed on the polished diamond surface and a III-Nitride layer may be formed on the second SiC layer. In embodiments, at step1612, the III-Nitride layer may be device processed to form various electrical components, such as transistors, in the III-Nitride layer. At step1614, the Si substrate and the first SiC layer may be removed.

While the invention is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the invention is not to be limited to the particular forms disclosed, but to the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims.