Optical network terminal with low-power sleep logic that substantially extends the life of the battery after the AC main power supply has been lost

An optical network terminal includes a sleep logic circuit that assumes responsibility for monitoring off-hook transitions after the AC main power supply has failed for a predetermined period of time. The sleep logic circuit is very low power and, as a result, allows the optical network terminal to remain active and provide lifeline support for a much greater period of time.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an optical network terminal (ONT) and, more particularly, to an ONT with low-power sleep logic that substantially extends the life of the battery after the AC main power supply has been lost.

2. Description of the Related Art

The subscriber end of a Fiber-To-The-Home (FTTH) network terminates a fiber optic cable in an optical network terminal (ONT) positioned at an interior or exterior location on a subscriber's premise. As a result, a substantial amount of bandwidth can be made available to the subscriber to provide a variety of services, such as plain old telephone service (POTS), Internet access (data) service, and video service.

One of the requirements of a POTS provider is to insure that, after the AC main power has failed, telephone service, known as lifeline telephone service, is continuously available for a period of time, such as eight hours. In an FTTH network, this is accomplished by providing a battery backup (BBU), such as an uninterruptible power supply, at the subscriber's premise. Thus, when power is lost, the BBU at the subscriber's premise provides power to the ONT at the subscriber's premise to maintain the lifeline telephone service for the required period of time.

FIG. 1shows a block diagram that illustrates a prior-art FTTH network100. As shown inFIG. 1, FTTH network100includes an optical line terminal (OLT)102, a subscriber104, a battery backup (BBU)106, and an ONT108that is connected to OLT102, subscriber104, and BBU106.

ONT108passes data signals and telephone signals between OLT102and subscriber104, and transmits a video signal from OLT102to subscriber104. For example, in the upstream pathway, ONT108receives a video signal, a data signal, and a voice signal from OLT102; and transmits the video signal, the data signal, and the voice signal to subscriber104when power from an AC main power source is present. In this case, ONT108consumes a first amount of power when ONT108simultaneously transmits the video signal, the data signal, and the voice signal.

As further shown inFIG. 1, ONT108includes a microprocessor110that controls the operation of ONT108when the AC main power source has been lost. In addition to microprocessor110, ONT108also includes a triplexer112(an optical transceiver that is connected to a fiber to carry an upstream wavelength, a down stream wavelength, and a video overlay wavelength) that is connected to a fiber optic cable. Further, ONT108includes a flash memory114, a RAM memory116, a clock driver118, an I2C120, a media access controller122, and a voltage converter124. These devices, along with microprocessor110and triplexer112, constitute the core logic devices of ONT108.

To provide telephone service, ONT108also includes a number of, such as four, subscriber line interface circuits (SLICs)130, which each provide interfaces to the phone lines of the subscribers, and a subscriber line audio-processing circuit (SLAC)132, which provides an interface between the SLICs130and triplexer112. ONT108additionally includes a 10/100 physical layer circuit134, a dual RS232 converter136, a phase locked loop140, and a number of LEDs142.

Further, ONT108includes a power supply that includes a first power supply150that outputs first and second voltages, such as 3.3V and 5.0V, a second power supply152that outputs a third voltage, such as 12V, and a third power supply154that outputs fourth and fifth voltages, such as −30V and −90V. First, second, and third power supplies150,152, and154supply power from the AC main power supply when the AC main power supply is available, and from backup battery106when the AC main power supply is no longer available.

As shown, each of the above devices (except for the other power supplies), is connected to the first power supply150to receive the first voltage (3.3V). In addition, the triplexer112and a 12V external source166are connected to the second power supply152to receive the third voltage (12V). Further, the SLICs130are also connected to the first power supply150to receive the second voltage (5V). The SLICs130are additionally connected to the third power supply154to receive the fourth and fifth voltages (−30V and −90V).

In operation, microprocessor110continuously monitors an AC main power supply, and checks a battery power status indicator that is output from BBU106. The battery status indicator can indicate, for example, whether the power supply or the battery module is providing the power, whether or not the battery in BBU106is charged or needs charging, and whether or not the battery in BBU106needs replacing.

When a loss of power from the AC main power source is detected, microprocessor110reports the lost power condition to OLT102, and stops the transmission of the video signal. In addition, BBU106provides power (when the battery power status indicator indicates that BBU106is charged and has the power to provide). In this case, ONT108consumes a second amount of power when ONT108simultaneously transmits the data signal and the voice signal without the video signal. The second amount of power, in turn, is less than the first amount of power, thereby saving power.

Further, after the AC main power source has been lost for a predetermined period of time, microprocessor110stops the transmission of the data signal. In this case, ONT100consumes a third amount of power when ONT108only transmits the voice signal. The third amount of power, in turn, is less than the second amount of power, thereby saving additional power.

When the power provided by BBU106reaches a failure threshold (or when the power from the power supply reaches a failure threshold when BBU106has previously failed or is unavailable), microprocessor110detects this condition, known as a last gasp condition, and reports the condition to OLT102.

During the last gasp condition, microprocessor110utilizes a charge stored in ONT108to allow microprocessor110to execute a controlled shut down. The charge, in turn, can be stored on a capacitor to provide a finite amount of energy. (ONT108can be implemented without a last gasp circuit.)

Once both power supplies have failed, ONT108shuts down, and does not turn on again until one of the two power supplies have returned. Throughout the time that power from the AC main power source is present, and during the time that power is supplied by BBU106(until the power from BBU106fails), microprocessor110detects off hook transitions that occur when subscriber104wishes to initiate a telephone call.

In the present example, ONT108provides lifeline support (detects off hook conditions while on battery power) for approximately eight hours. Although eight hours is a reasonable period of time, it is desirable to be able to provide lifeline support for a much longer period of time, such as twice as much or more.

SUMMARY OF THE INVENTION

The present invention provides a system and method of significantly extending an amount of time that battery power is available to an optical network terminal (ONT) after the AC main power has failed. The ONT of the present invention receives a video signal, a data signal, and a voice signal from an optical line terminal; and transmits the video signal, the data signal, and the voice signal to a subscriber when power from an external power source is present. The ONT consumes a first amount of power when the ONT simultaneously transmits the video signal, the data signal, and the voice signal.

In the present invention, the ONT includes a processor that continuously monitors the external power source, and checks a power status indicator from a battery power source. Further, the processor detects a loss of power from the external power source, and enters the battery mode from the normal mode and stops a transmission of the video signal after detecting the loss of power from the external power source. The ONT consumes a second amount of power when the ONT simultaneously transmits the data signal and the voice signal. The second amount of power is less than the first amount of power.

In addition, the processor stops a transmission of the data signal while in the battery mode after the external power source has been lost for a first predetermined period of time. The ONT consumes a third amount of power when the ONT only transmits the voice signal. The third amount of power is less than the second amount of power. Further, the processor detects off hook transitions when power from the external power source is present, and during the first predetermined period of time.

The present invention additionally includes a method of extending an amount of time that battery power is available to an optical network terminal (ONT) that receives a video signal, a data signal, and a voice signal from an optical line terminal; and transmits the video signal, the data signal, and the voice signal to a subscriber when power from a first power source is present. The ONT consumes a first amount of power when the video signal, the data signal, and the voice signal, are simultaneously transmitted.

The method further includes the steps of continuously monitoring the first power source, and checking a power status indicator from a second power source. Further, the method includes the steps of detecting a loss of power from the first power source, and providing power in response.

In addition, the method includes the step of stopping a transmission of the video signal when the first power source is detected as lost. The ONT consumes a second amount of power when simultaneously transmitting the data signal and the voice signal, and the video signal is turned off. The second amount of power is less than the first amount of power.

In addition, the method includes the step of stopping a transmission of the data signal after the first power source has been detected as lost for a first predetermined period of time. The ONT consumes a third amount of power when transmitting only the voice signal. The third amount of power is less than the second amount of power. The method further includes the step of detecting off hook transitions when power from the first power source is present, and during the first predetermined period of time.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2A-2Bshow a block diagram that illustrates a network200in accordance with the present invention. As described in greater detail below, network200includes an optical network terminal (ONT) which has a sleep logic circuit that assumes responsibility for monitoring off-hook transitions after the AC main power supply has been lost for a period of time. The sleep logic circuit is very low power, and thus significantly extends the lifetime of the battery, and thereby the amount of time that the ONT can provide lifeline telephone service (service after the AC main power has been lost).

As shown inFIGS. 2A-2B, network200includes an optical line terminal (OLT)202, a subscriber204, a battery backup (BBU)206, and an ONT208that is connected to OLT202, subscriber204, and BBU206. ONT208passes data signals and telephone signals between OLT202and subscriber204, and transmits a video signal from OLT202to subscriber204.

For example, in the upstream pathway, ONT208receives a video signal, a data signal, and a voice signal from OLT202; and transmits the video signal, the data signal, and the voice signal to subscriber204when power from an AC main power source is present. In this case, ONT208consumes a first amount of power when ONT208simultaneously transmits the video signal, the data signal, and the voice signal to subscriber204.

Further, ONT208includes a power supply that includes a first power supply210A that receives +18V, down converts the voltage, and outputs first and second voltages, such as 3.3V and 5.0V, and a second power supply210B that receives +18V, down converts the voltage, and outputs a third voltage, such as 12V.

In addition, the power supply also includes a third power supply210C that receives +18V, down converts the voltage, and outputs fourth and fifth voltages, such as −30V and −90V. First, second, and third power supplies210A,210B, and210C supply power from the AC main power supply when the AC main power supply is available, and from backup battery206when the AC main power supply is no longer available.

As further shown inFIGS. 2A-2B, ONT200also includes a number of power circuits212that consume power performing ONT functions, and a number of power switches214that control power to the power circuits212. The power circuits212include a first power circuit212A that includes the core logic of ONT200, a second power circuit212B that includes the circuits that continuously receive power until power is no longer available, a third power circuit212C that includes the POTS connections, and a fourth power circuit212D that includes the data connections.

As further shown inFIGS. 2A-2B, first power circuit212A includes a power line216, and a number of core logic circuits218that are connected to power line216. Power line216, in turn, is connected to the 3.3V output of the first power supply210A via a first power switch214A.

In theFIGS. 2A-2Bexample, power switch214A is controlled by a control signal 3.3V_CTL that turns on power switch214A when the voltage of the control signal 3.3V_CTL is low (ground), and turns off power switch214A when the voltage of the control signal 3.3V_CTL is high. When power switch214A is turned off, power is removed from the core logic circuits. Power is removed from the core logic circuits218only when ONT200enters a sleep mode of operation.

The core logic circuits218of first power circuit212A can include, for example, a microprocessor218A, a triplexer218B (an optical transceiver that is connected to a fiber to OLT202to carry an upstream wavelength, a down stream wavelength, and a video overlay wavelength), a flash memory218C, a RAM memory218D, a clock driver218E, an I2C218F, a media access controller218G, and a voltage converter218H.

Microprocessor218A outputs control signals to the first power supply210A that include the control signals 5V_DIS and 3.3V_DIS, and a control signal 12V_EN that is output to second power supply210B. The control signal 5V_DIS removes the 5V power supply, and the control signal 12V_EN removes the 12V power supply, when ONT200is in the dying gasp mode. The control signal 3.3V_DIS removes the 3.3V power supply (the 3.3V power supply is always on during normal operation, including the dying gasp and sleep modes).

In addition, a second power switch214B and a third power switch214C are connected to triplexer218B and the +12V output of second power supply210B, and a fourth power switch214D is connected to a 12V external circuit218I and the +12V output of second power supply210B.

Power switch214B is controlled by a control signal VDD_PD_ENA, and power switch214C is controlled by a control signal12V-L-ENA, both output by microprocessor218A. Power switches214B and214C turn on when the voltages of the control signals VDD_PD_ENA and12V-L-ENA are high, and turn off when the voltages of the control signals VDD_PD_ENA and12V-L-ENA are low (ground). When power switches214B and214C are turned off, +12V is removed from triplexer218B.

Further, power switch214D is controlled by a control signal12VX_ENA output by microprocessor218A. Power switch214D turns on when the voltage of the control signal12VX_ENA is high, and turns off when the voltage of the control signal12VX_ENA is low (ground). When power switch214D is turned off, +12V is removed from a 12V external circuit218I.

The control signals are by default deasserted and remain deasserted even when microprocessor218A is turned off. If not already turned off, microprocessor218A turns off the +12V connections with these control signals before entering the sleep mode, and turns them on as needed after awakening from the sleep mode.

Referring again toFIGS. 2A-2B, second power circuit212B includes a power line226and a number of sleep-mode circuits228that are connected to power line226. Power line226is connected to power supply210A. Unlike the first power circuit212A, the second power circuit212B is always connected to the 3.3V output of power supply210A.

The sleep-mode circuits228, which represent the low power devices of the ONT, can include a sleep mode programmable logic device (PLD)228A, a low drop out voltage regulator228B, a battery back up (BBU) alarm status circuit228C, and an osciallator228D. As shown, PLD228A outputs a control signal HV_ENA to power supply210C to enable and disable the −30V and −90V sources.

Referring again toFIGS. 2A-2B, third power circuit212C includes a power line236, and a number of circuits238that are connected to power line236. The circuits238include, for example, the 3.3V connections to a subscriber line audio-processing circuit (SLAC)/quad codec238A, and the 3.3V connections to, for example, four subscriber line interface circuits (SLICs)238B. The SLICs238B are the circuits that form a POTS interface to subscriber204, while SLAC238A provides an interface between microprocessor218A and the SLICs238B.

Power line236is connected to a fifth power switch214E which, in turn, is connected to power line226. In the example shown inFIGS. 2A-2B, power switch214E is controlled by a control signal SLAC_OFF from PLD228A. Power switch214E turns off when the voltage of the control signal SLAC_OFF is high, and turns on when the voltage of the control signal SLAC_OFF is low (ground). When power switch214E is turned off, 3.3V is removed from SLAC238A and the SLICs238B. Power is removed from SLAC238A and the SLICs238B in the third power circuit212C only when ONT200enters the dying gasp mode of operation.

In addition, in the example shown inFIGS. 2A-2B, the SLICs238B are also connected to the first power supply210A to receive the third voltage (5V), and the third power supply210C to receive the fourth voltage (−30V). Further, the SLICs238B are connected to the third power supply210C via a sixth power switch214F to receive the fifth voltage (−90V).

Power switch214F is controlled by a control signal90_DIS output from PLD228A. Power switch214F turns off when the voltage of the control signal90_DIS is high, and turns on when the voltage of the control signal90_DIS is low (ground). When power switch214F is turned off, −90V is removed from the SLICs238B. Power is removed from the SLICs238B in the third power circuit212C when ONT200enters the dying gasp mode of operation, and when in the sleep mode of operation. In addition, even more power is saved by forcing the SLICs238B to use −30V in the sleep mode of operation. This is the minimum needed to detect off-hook transitions.

As further shown inFIGS. 2A-2B, microprocessor218A and PLD228A exchange a number of control signals. In the example shown inFIGS. 2A-2B, microprocessor218A outputs microprocessor interface (MPI) and time division multiplexing (TDM) signals when microprocessor218A is not in the sleep mode.

PLD228A passes the MPI and TDM signals onto SLAC238A and the SLICs238B when microprocessor218A is not in the sleep mode. On the other hand, when microprocessor218A is in the sleep mode, PLD228A generates and outputs the MPI signals (as necessary) and the timing signals TDM. In the present invention, to further save power, PLD228A generates the timing signals TDM (the clock signal PCLK and the framing signal) at the lowest frequency that is usable by SLAC238A and the SLICs238B.

For example, PLD228A can generate and output the clock signal PCLK and the framing signal at approximately ¼ the frequency of the clock and framing signals output by microprocessor218A. PLD228A includes multiplexers that pass the MPI and TDM signals from microprocessor218A when microprocessor218A is not in the sleep mode, and passes the MPI and TDM signals from PLD228A when microprocessor218A is in the sleep mode.

The MPI signals control the operation of SLAC238A which, in turn, controls each POTS port via the SLICs238B. The TDM signals control the timing of, and the transfer of data through, the SLICs238B. The TDM signals include timing signals, such as a TDM clock signal (PCLK) and a frame synch signal, and data signals, such as transmit and receive data signals, i.e., the PCM highway.

Microprocessor218A also outputs the signals HV_ENA_CPU, DGV_CTRL_CPU, SWITCH_PCLK, SLEEP_RQT, and CLR_LAST. PLD228A outputs the signals CMD_ACK, WU_STATUS(2), and BAT_STATUS(4). Whenever microprocessor218A enters the sleep mode, PLD228A places a high impedance (tristate) on each line that is connected to microprocessor218A.

Microprocessor218A receives battery status information from the battery status signals BAT_STATUS output by PLD228A. The battery status signals BAT_STATUS can include, for example, a low battery signal, a replace battery signal, and a missing battery signal. PLD228A, in turn, receives the battery status information from battery back up (BBU)206, and passes the battery status information to microprocessor218A via the battery status signals BAT_STATUS when microprocessor218A is not in the sleep mode. On the other hand, PLD228A responds to the battery status signals BAT_STATUS when microprocessor218A is in the sleep mode.

Referring again toFIGS. 2A-2B, fourth power circuit212D includes a power line246, and a number of circuits248that are connected to power line246. The circuits248include, for example, a 10/100 physical layer circuit248A, a dual RS232 converter248B, a phase locked loop248C, and a number of LEDs248D.

Power line246is connected to power supply210A via a seventh power switch214G. In the example shown inFIGS. 2A-2B, power switch214G is controlled by a control signal DGV_CTL output from PLD228A. Power switch214G turns off when the voltage of the control signal DGV_CTL is high, and turns on when the voltage of the control signal DGV_CTL is low (ground). When power switch214G is turned off, power is removed from the fourth power circuit212D. Power is removed from the fourth power circuit212D only when ONT200enters a sleep mode of operation or the dying gasp mode of operation.

FIG. 3shows a state diagram that illustrates the operation of an ONT300in accordance with the present invention. ONT300can be implemented with ONT208and, as a result, the operation of ONT300is discussed with reference to the structures of network200.

As shown inFIG. 3, ONT300begins by leaving an off state and moving to state310where the AC main power is applied, and then moving to state312where ONT300follows a first initialization sequence. The first initialization sequence includes checking the status of a sleep mode flag stored in a register in flash memory218C to determine if ONT300is powering up from the off state or a sleep mode. When ONT300powers up from the off state, initialization can also include, for example, a test of DRAM218D.

Further, the first initialization sequence also includes the steps of loading information into the various registers to enter a ranging state where microprocessor218A waits to be polled by optical line terminal (OLT)202and, once polled by OLT202, outputs the information necessary to establish a connection between OLT202and microprocessor218A.

Once the connection between OLT202and microprocessor218A has been established, the first initialization sequence is complete and ONT300moves to state314, referred to as the Normal Mode Operation State, where the AC main power is present. In this state, when the AC main power is present, POTS, data (internet), and video services can all be provided to subscriber204.

When in the Normal Mode Operation State314, processor218A continuously monitors the battery status signals BAT_STATUS output from PLD228A (which are input to PLD228from BBU206as battery status signals). When the AC main power is lost, processor218A detects the condition of the battery via the battery status signals BAT_STATUS.

In addition, the battery supply also detects the loss of AC main power and, when detected and battery power is available, outputs battery power in lieu of the AC main power. In this case, ONT300moves to state316, referred to as the Hold Over State, where full power is maintained by the battery for a hold over period of time, such as 30 seconds, to cover the case where the AC main power failure is just a short glitch. (The Hold Over State is optional. ONT300can optionally move directly to state318.)

If the AC main power returns before a hold over timer expires, ONT300returns to the Normal Mode Operation State314. On the other hand, if the AC main power remains off at the end of the hold over period, ONT300moves to step318, referred to as the Battery Mode 1 Operation State, where microprocessor218A disables (stops the transmission of) the video services, such as by disabling the CATV and RF-Adaptor, and outputs an AC Fail Alarm to OLT202.

The time spent in the Battery Mode 1 Operation State318is programmable, and controllable by a battery mode 1 timer. For example, the battery mode 1 timer can be set to run from 5 minutes to 60 minutes in 5 minute increments with a 15 minute default. If the AC main power returns before the battery mode 1 timer expires, ONT300returns to the Normal Mode Operation State314where the video services are again resumed.

On the other hand, if the battery mode 1 timer expires, ONT300moves to state320, referred to as the Battery Mode 2 Operation State, where microprocessor218A disables (stops the transmission of) the data services in addition to the previously disabled video services. The time spent in the Battery Mode 2 Operation State320is also programmable, and controllable by a battery mode 2 timer. For example, the battery mode 2 timer can be set to run from 15 minutes to 4 hours in 15 minute increments with a 2 hour default.

The Battery Mode 2 Operation State is optional. ONT300can alternately stop the transmission of data at the same time that the transmission of video is stopped. Thus, when the video and data services are stopped sequentially at substantially the same time, the time spent in the Battery Mode 1 Operation State can be considered to be essentially zero minutes.

If the AC main power returns before the battery mode 2 timer expires, ONT300returns to the Normal Mode Operation State314where the data and video services are again resumed. On the other hand, if the battery mode 2 timer expires, ONT300moves to state322, referred to as the Sleep Mode Operation State, where control is transferred to PLD228A, and power is removed from microprocessor218A.

The Sleep Mode Operation State is intended to serve as an extended “minimal operational mode” for emergency outbound phone use. As a result, all of the core logic of power circuit212A, including microprocessor218A, is powered off during the sleep mode. Inbound calls cannot be received during sleep mode. All other services (data service and video service) are shut down in sleep mode. The goal is to maximize the time that sleep mode can be maintained. SLAC238A and the SLICs238B are powered up during the Sleep Mode Operation State322although they run at a reduced power state.

Microprocessor218A, which controls the operation of ONT300except when in the Sleep Mode Operation State322, prepares to enter the sleep mode by storing an 8-bit code in the register of flash memory218C which represents the sleep mode flag. The sleep mode flag is stored in non-volatile memory so that when microprocessor218A powers up, microprocessor218A can determine whether microprocessor218A is powering up from the off state or the sleep mode.

After this, microprocessor218A executes a number of commands in preparation for transferring control over to PLD228A. In the present example, microprocessor218A places SLAC238A and SLICs238B in a low-power standby state, which offers the lowest power consumption while still being able to detect an off-hook transition, and arms the appropriate interrupts for detecting any off-hook transitions as well as any other supervisory mode interrupts that may be required. Microprocessor218A also disables power supply210B via the 12V_EN signal.

To save additional power, microprocessor218A also commands PLD228A to output the timing signals TDM at a lower frequency by asserting the SWITCH_PCLK command to PLD228A. In response, PLD228A acknowledges by toggling the CMD_ACK signal to provide positive acknowledgement to microprocessor218A that the command was received. The command and acknowledgement handshake ensures that there is no inadvertent entry into undesired states in PLD228A, perhaps due to a misbehaving microprocessor.

Microprocessor218A then stops outputting the TDM clock signal and frame synch signal (of the timing signals TDM) to SLAC238A, while PLD228A begins generating a TDM clock signal and a frame synch signal at 1.024 MHz and 2 KHz, respectively, without generating glitches (very narrow pulses).

In the present example, SLAC238A is run at the lowest possible clock rate, which can be, for example, 1.024 MHz. In normal operation, SLAC238A runs at 4.096 MHz. Therefore, the SLAC DSP is running at ¼ it's normal rate. PLD228A takes over the responsibility for generating the TDM clock “PCLK” and frame synch “FS” timing signals. A 4.096 MHz oscillator tied to PLD238A is used to generate the 1.024 MHz PCLK and 2 KHz FS pulse, and to time the PLD internal logic.

Thus, the TDM clock signal generated by PLD228A has a lower frequency than the TDM clock signal generated by microprocessor218A such that microprocessor218A reduces a clock rate to SLAC238A before entering the sleep mode of operation. The control signals HV_ENA_CPU (high voltage enable CPU) and DGV_CTRL_CPU (dying gasp voltage control CPU) are also related to transferring control to PLD228A during the sleep mode. Similar command and acknowledgement handshake sequences can be used.

In addition, microprocessor218A monitors a register, which can generate an interrupt, that includes a clock fail bit CFAIL. The clock fail bit CFAIL will likely activate after the frequency of the timing signals TDM (the TDM clock and framing synch signals) is changed. This interrupt needs to be cleared, along with any other pending interrupts, before microprocessor218A releases control of monitoring the interrupts over to PLD228A since PLD228A will wakeup microprocessor218A on an interrupt that is supposed to be due to an off-hook transition and not any other cause (except as indicated). Thus, by waiting for the clock fail bit CFAIL to clear before proceeding, microprocessor218A knows that the TDM clock and framing are good before entering the sleep mode.

Once all of the preparations for entering the sleep mode have been completed, microprocessor218A then follows a defined handshake sequence to enter the sleep mode. In one embodiment, microprocessor218A commands PLD228A to enter the sleep mode by asserting the sleep request signal SLEEP_RQT, while PLD228A responds by removing power to the core logic by placing a low voltage (ground) on the control signal3.3V_CTL output to power switch214A. In another embodiment, microprocessor218A and PLD228A can follow a sequence of command signals that insure that the sleep mode is not inadvertently entered.

In addition, when in the sleep mode, PLD228A places a high voltage on the power switch214F via control signal90_DIS, and places a high voltage on the power switch214G via control signal DGV_CTRL, thereby powering off the circuits controlled by these switches. The control signal90_DIS removes the −90V from the SLICs238B to reduce power consumption during the sleep mode.

As noted above, once the core logic has been powered off, PLD228A places a high impedance (tristate) on each line received from and output to microprocessor218A. Xilinx offers programmable logic devices, such as Part No. XC2C256-7FT256 of the Coolrunner II Series, that have FETs on the inputs and outputs to fully isolate the connection between microprocessor218A and PLD228A.

By placing a high impedance on the lines that are connected to and from microprocessor218A, microprocessor218A can be prevented from inadvertently powering up via a voltage on one of its pins, or latching-up if it were to be powered up from the sleep mode of operation with voltage already present on its pins.

During sleep mode, PLD228A monitors for an off-hook transition (or other abnormal event) on any one of the 4 POTS interfaces, to “eventually” provide an active line to subscriber204. When an off-hook transition is detected, referred to as a wake-up event, ONT300moves to state324, referred to as the Wake-Up Mode Operation State, where ONT300again establishes a connection with OLT202.

When ONT300powers up, microprocessor218A checks the 8-bit sleep mode flag set in flash memory218C and, because the sleep mode flag indicates that microprocessor218A is powering up from the sleep mode, does a fast boot that follows a second initialization sequence that is shorter than the first initialization sequence. The second initialization sequence can exclude, for example, the test of DRAM218D.

As above, the second initialization sequence can also include the steps of loading information into the various registers to enter the ranging state where microprocessor218A waits to be polled by optical line terminal (OLT)202and, once polled by OLT202, outputs the information necessary to establish a connection between OLT202and microprocessor218A. Because the second initialization sequence is shorter than the first, microprocessor218A enters the ranging state in less time in the fast-boot second initialization sequence than in the first initialization sequence.

Once the second initialization sequence is complete, microprocessor218A reads the control signals WU_STATUS from PLD228A to see the reason microprocessor218A is awakening from the sleep mode. There are two status lines for four logical conditions that indicate four possible reasons for waking up from the sleep mode state. Microprocessor218A uses this status information, along with battery status and local AC status, to determine what to do next.

The four wake up reasons include: 1) the battery has been replaced (the default state upon PLD reset or after receiving a clear sleep status command); 2) a supervisory interrupt (e.g. an off-hook transition) has been received; 3) the AC main power has returned; and 4) the battery has a Low Battery condition.

When wake-up is due to the batteries being replaced, which is different than the battery status replace battery, this condition is detected on power-up by microprocessor218A seeing the active state of the sleep mode flag in flash memory218C and also reading the WU_STATUS and seeing that wake-up is not active (0,0). By default this means that power was completely removed while in the sleep state. This would be most likely due to replacing the battery.

When microprocessor218A detects that the batteries have been replaced, microprocessor218A immediately takes the steps to re-enter the sleep mode. To re-enter the sleep mode, microprocessor218A commands PLD228A to clear the last wakeup status to re-arm PLD228A for entering the sleep mode the next time. Microprocessor218A asserts the signal CLR_LAST.

In response, PLD228A clears the status and toggles the CMD_ACK signal to provide positive acknowledgement to microprocessor218A that the status was cleared. In addition, microprocessor218A also places SLAC238A and the SLICs238B in the standby mode, transfers TDM clock and frame synch signals to PLD228A, clears interrupts, clears the sleep mode flag in flash memory218C, and issues sleep commands to PLD228A.

When wake-up is due to an off-hook transition, microprocessor218A commands PLD228A to switch the TDM timing signals (the clock signal PCLK and the framing signal) back to the core logic control of microprocessor218A. Microprocessor218A initializes the SLAC/SLICs and proceeds to determine which channel is off-hook and also take the appropriate steps to playout a message, such as “Please wait for dial tone.”

ONT300then waits to be ranged by OLT202(receive the ranging signal) on the passive optical network (PON). There should be a smooth transition between the playout of the message and the receipt of dial tone. The message can be periodically repeated until a dial tone can be delivered.

During the Sleep Mode Operation State, ONT300is not ranged with OLT202. Only after detecting an off-hook transition does ONT300“wake-up” and proceed to range with the OLT. OLT202must initiate the ranging process (ONT300waits to be polled and then responds), so there will be some delay from the time the subscriber picks up the handset and the time when ONT300is ranged. This time will depend on how many ONT's on the PON are down and which ONT is being ranged at the time.

As noted above, while waiting for ranging, an audible message is played out to the subscriber, such as “please wait for dial tone” or the like, as a confirmation that the line will soon be available for use. In addition, “comfort” noise may also be embedded in the “background” to provide the illusion of an active line. This can be particularly heard during breaks in the message and longer pauses when the message is about to repeat. This message and the comfort noise can be played out by microprocessor218A. Once ONT300has been ranged and configured, subscriber204receives a dial tone.

When awakened by an off-hook transition, ONT300remains in the Wake-Up Mode Operation State324for a wake up period of time, such as the length of the phone call plus a remainder time, such as 15 minutes, and then returns to the Sleep Mode Operation State320. The remainder time is measured by a remainder timer. The hold over timer, the battery mode 1 timer, the battery mode 2 timer, and the remainder timer can be implemented with processor218A.

To re-enter the sleep mode, microprocessor218A commands PLD228A to clear the last wakeup status to re-arm PLD228A for entering the sleep mode the next time. Microprocessor218A asserts the signal CLR_LAST. In response, PLD228A clears the status and toggles the CMD_ACK signal to provide positive acknowledgement to microprocessor218A that the status was cleared. In addition, microprocessor218A also places SLAC238A and the SLICs238B in the standby mode, transfers TDM clock and frame synch signals to PLD228A, clears interrupts, clears the sleep mode flag in flash memory218C, and issues sleep commands to PLD228A.

If the AC main power returns while ONT300is in the Sleep Mode Operation state322, ONT300returns to state312where the system is again initialized via the first initialization sequence. Similarly, if the AC main power returns after a call has been completed while ONT300is in state324, ONT300returns to state312where the system is again initialized.

As shown inFIG. 3, when the AC main power fails while operating in the Normal Mode Operation State314and there is no battery power, ONT300moves from the Normal Mode Operation State314to state326, referred to as the Dying Gasp Operation State, where a locally charged device, such as a capacitor, provides sufficient power to execute a controlled power down sequence, which ends by moving to state328, referred to as the Powered Off State. Otherwise, if some battery power is available, ONT300moves to the Battery Mode 1 State318as described above.

If all of the power sources of ONT300run out before the main AC power is returned, ONT300moves to Powered Off State328to shutdown. If ONT300is ranged and in communication with the OLT when the final power loss occurs, a “dying gasp” message will be sent to OLT202. If ONT300is not ranged and in communication with OLT202when the final power loss occurs, the dying gasp message will not be sent because there is not enough power available to establish communication with OLT202and send the dying gasp message.

Similarly, when the battery power fails while operating in the Battery Mode 1 Operation State316, ONT300moves from the Battery Mode 1 Operation State318to the Dying Gasp Operation State326. When the battery power fails while operating in the Battery Mode 2 Operation State320, ONT300moves from the Battery Mode 2 Operation State320to the Dying Gasp Operation State326.

When the battery power fails while operating in the Wake-Up Mode Operation State324, ONT300moves from Wake-Up Mode Operation State324to the Dying Gasp Operation State326. However, when the battery power fails while operating in the Sleep Mode Operation State322, ONT300moves from Sleep Mode Operation State322to the Powered Off Operation State328, where ONT300loses all power.

If battery back up (BBU)206asserts the “Low Battery” status while in any battery state, ONT300sends a Low Battery alarm to OLT202. As shown inFIG. 3, when the battery power goes low while operating in the Battery Mode 1 Operation State318, ONT300moves from the Battery Mode 1 Operation State318to state330, referred to as the Send Low Battery Alarm State, where a low battery alarm signal is sent to OLT202. Following this, ONT300moves to the Sleep Mode Operation State322.

When the battery power goes low while operating in the Battery Mode 2 Operation State320, ONT300moves from the Battery Mode 2 Operation State320to the Send Low Battery Alarm State330to send the low battery alarm signal to OLT202. Following this, ONT300moves to the Sleep Mode Operation State322.

When the battery power goes low while operating in the Wake-Up Mode Operation State324, ONT300moves from the Wake-Up Mode Operation State324to the Send Low Battery Alarm State330to send the low battery alarm signal to OLT202. Following this, ONT300moves to the Sleep Mode Operation State322.

When the battery power goes low while operating in the Sleep Mode Operation State322, ONT300moves from the Sleep Mode Operation State322to state332, referred to as the Alarm State, where ONT300wakes up, is ranged by the PON (establishes a connection with OLT202by responding to a poll), sends the low battery alarm signal to OLT202, and then returns to the Sleep Mode State322, sending the “I am going to sleep” message.

In addition, the general state of ONT300can be determined by visually inspecting ONT300. For example, ONT300can include an AC Power LED that is on steady when operating on AC power, pulses when operating on battery power, such as in states318,320, and324, and is off when operating in states322or328. Similarly, ONT300can include a Battery Power LED that is on steady when the battery power is high, and is off when battery power is low.

The operation of ONT300is summarized below in Table 1:

The times listed for how long the ONT stays in a state are approximate, and based upon a new, fully charged battery.

FIG. 4shows a timing diagram that illustrates the power consumption of ONT300over time in accordance with the present invention. (FIG. 4does not show the power consumption that results from ONT300waking up from the sleep state to service locally originating POTS calls.)

As shown in theFIG. 4example, once the AC main power fails, ONT300moves to the Hold Over State and keeps all applications (POTS, data access and CATV) active at approximately 100% of total power for a holdover period, such as 30 seconds. If the AC main power has not returned by the end of the holdover period, ONT300moves to the Battery Operation 1 State for a first battery period, such as 15 minutes. In this state the CATV application and the RF-Adaptor are disabled to reduce power to approximately 80% of total power.

If the main AC power has not returned by the end of the first battery period, ONT300moves to the Battery Operation 2 State for a second battery period, such as 2 hours. The Battery Operation 2 State disables the data access application to save even more power, reducing power consumption to approximately 70% of total power.

If the main AC power has not returned by the end of a second battery period, ONT300moves to the Sleep State, where only active POTS calls are completed, for a sleep period of time of, for example, 20 hours. This state reduces the power consumption of ONT300to the absolute minimum, approximately 5% of total power in this example, so as to maximize the operational life of ONT300.

The data access and CATV (with RF-Adaptor) applications remain turned off. The optical link to the OLT is turned off. The POTS application goes into a mode where only PLD228A monitors the local loops for an off-hook. Regardless of the previous state, ONT300reports to OLT202that it is transitioning into the Sleep Mode Operation State by sending the “I am going to sleep” message.

When any of the POTS ports recognizes an off-hook transition while ONT300is in the sleep state, ONT300enters the Wake Up State where it fully enables all of the POTS circuits and reestablishes communication with OLT202. ONT300can stay in this state for the length of the POTS call plus 15 minutes.

Thus, one of the advantages of the present invention is that PLD228A and the Sleep Mode Operation State322can provide up to 20 hours of operation, assuming 14 three-minute phone calls during that time. (Each three-minute phone call causes ONT300to spend 18 minutes in the Wake-Up Mode State324.) As a result, the present invention provides substantially more lifeline service than is conventionally available when 14 3-minute calls are made over a 20 hour period.

It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.