Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

BACKGROUND

Electronic equipments using semiconductor devices are essential for many modern applications. With the advancement of electronic technology, the semiconductor devices are becoming increasingly smaller in size while having greater functionality and greater amounts of integrated circuitry. Due to the miniaturized scale of the semiconductor device, a wafer level packaging (WLP) is widely used for its low cost and relatively simple manufacturing operations. During the WLP operation, a number of semiconductor components are assembled on the semiconductor device. Furthermore, numerous manufacturing operations are implemented within such a small semiconductor device.

However, the manufacturing operations of the semiconductor device involve many steps and operations on such a small and thin semiconductor device. The manufacturing of the semiconductor device in a miniaturized scale becomes more complicated. The semiconductor device is assembled with numbers of integrated components including various materials with difference in thermal properties. As such, the integrated components are in undesired configurations after curing of the semiconductor device. The undesired configurations would lead to yield loss of the semiconductor device, poor electrical interconnection, development of cracks or delamination of the components, etc. Furthermore, the components of the semiconductor device includes various metallic materials which are in limited quantity and thus in a high cost. The undesired configurations of the components and the yield loss of the semiconductor would further exacerbate materials wastage and thus the manufacturing cost would increase.

Since more different components with different materials are involved, a complexity of the manufacturing operations of the semiconductor device is increased. There are more challenges to modify a structure of the semiconductor device, improve the manufacturing operations and minimize materials usage. As such, there is a continuous need to improve the manufacturing the semiconductor and solve the above deficiencies.

DETAILED DESCRIPTION

A semiconductor structure is manufactured by a number of operations. During the manufacturing, a post passivation interconnect (PPI) is disposed over a substrate for routing a die pad of the substrate, and a conductive bump is disposed on a portion of the post passivation interconnect (PPI). The substrate has to be aligned or calibrated to a correct position and orientation prior to mounting of the conductive bump on the PPI. After the alignment operation, the conductive bump is dropped and mounted on the PPI. The conductive bump has to be placed at an appropriate position of the PPI. After the reflow operation, the conductive bump is configured for electrically connecting with another substrate or device.

The conductive bump is placed on the PPI after the alignment operation. However, as the conductive bump is in substantially spherical shape, the conductive bump would be displaced from the appropriate position easily during the mounting operation. Furthermore, the conductive bump would shift during the reflow operation. Finally, the conductive bump does not seat at the appropriate and desired position. As the conductive bump is configured for bonding with a bond pad on another substrate, malposition of the conductive bump on PPI would affect subsequent operations. The conductive bump would not be able to bond with a bond pad of another substrate accurately, and ultimately the substrate would be poorly bonded with another substrate. A high yield loss and a poor reliability on the electrical connection between the conductive bump and the bond pad would be suffered.

In the present disclosure, a semiconductor structure with a structural improvement is disclosed. The semiconductor structure includes a metallic paste disposed on a predetermined position of a post passivation interconnect (PPI). The metallic paste serves as a landing pad for a conductive bump seating thereon. The conductive bump can mount on the PPI at where the metallic paste positioned. The conductive bump would form on the appropriate position of the PPI. The mounting of the conductive bump on the PPI is under control, which would minimize shifting of the conductive bump and improve reliability of the semiconductor structure. Also, the metallic paste is intermediate between the conductive bump and the PPI. Therefore, electron migration from the PPI to the conductive bump can be avoided, and thus formation of void or development of cracks within the PPI can also be avoided.

FIG. 1is an embodiment of a semiconductor structure100in accordance with various embodiments of the present disclosure. The semiconductor structure100includes a substrate101, a die pad102, a passivation103, a polymer104, a post passivation interconnect (PPI)105, a metallic paste106, a conductive bump107and a molding108.

In some embodiments, the substrate101is a piece including semiconductor materials such as silicon germanium, gallium, arsenic, and combinations thereof. A predetermined functional circuit is fabricated over the substrate101by various methods such as photolithography operations, etching or etc. In some embodiments, the substrate101includes several electrical circuits formed within the substrate101for a particular application. In some embodiments, the electrical circuits include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes and/or the like. In some embodiments, the electrical circuits are interconnected to perform one or more functions such as memory, sensors, amplifiers, input/output circuitry and/or the like.

In some embodiments, the substrate101includes a layer of a semiconductor material such as silicon, germanium and/or the like formed over an insulator layer such as buried oxide formed in the substrate. In some embodiments, the substrate101is multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like. In some embodiments, the substrate101is in a quadrilateral, a rectangular or a square shape.

The die pad102is disposed over the substrate101. In some embodiments, the die pad102is electrically connected with a circuitry external to the substrate101, so that a circuitry internal to the substrate101electrically connects with the circuitry external to the substrate101through the die pad102. In some embodiments, the die pad102is configured for receiving a conductive trace coupled with a conductive bump, so that the substrate101electrically connects with a circuitry external to the substrate101through the die pad102, the conductive trace and the conductive bump. In some embodiments, the die pad102includes gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.

The passivation103is disposed over the substrate101and surrounds an edge102aof the die pad102. In some embodiments, the passivation103is disposed on a surface101aof the substrate101. In some embodiments, the passivation103partially covers a top surface102bof the die pad102. The passivation103is configured for providing an electrical insulation and a moisture protection for the substrate101, so that the substrate101is isolated from ambient environment.

In some embodiments, the passivation103is formed with dielectric materials such as spin-on glass (SOG), silicon oxide, silicon oxynitride, silicon nitride or the like. In some embodiments, the passivation103is formed with a vapor deposition or a spin coating process.

In some embodiments, the passivation103includes a first opening103aabove the die pad102for exposing a portion of the top surface102bof the die pad102, and thus for electrically connecting the die pad102with the circuitry external to the substrate101through the conductive trace. In some embodiments, the first opening103ais tapered towards the top surface102bof the die pad102.

The polymer104is disposed over the passivation103. In some embodiments, some of the polymer104is disposed within the first opening103aof the passivation103. Some of the polymer104is conformal to the first opening103a.In some embodiments, the polymer104includes a polymeric material such as epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB) or etc.

In some embodiments, the polymer104includes a second opening104a.In some embodiments, the second opening104ais surrounded by the first opening103aof the passivation103. The second opening104ais within the first opening103a.In some embodiments, the second opening104ais tapered towards the top surface102bof the die pad102. In some embodiments, the second opening104ais conformal to a profile of the first opening103a.

The post passivation interconnect (PPI)105is disposed on the polymer104. The PPI105re-routes a path of a circuit from the die pad102. In some embodiments, the PPI105is a single material layer or a multi-layered conductive structure. In some embodiments, the PPI105includes copper, aluminum, titanium, titanium nitride, copper alloy or other mobile conductive materials.

In some embodiments, the PPI105includes an elongated portion105aand a via portion105b.The elongated portion105ais coupled with the via portion105b.In some embodiments, the elongated portion105aextends horizontally along a surface104bof the polymer104. A portion of the elongated portion105ais configured for receiving a conductive structure to connect with an external circuit or another substrate.

In some embodiments, the via portion105bis extended from the surface104bof the polymer104to contact with the die pad102. The die pad102exposed from the passivation103and the polymer104is contacted with the via portion105b.Thus, the elongated portion105ais electrically connected with the die pad102via the via portion105b.In some embodiments, the via portion105bof the PPI105is disposed within the first opening103aof the passivation103and the second opening104aof the polymer104. In some embodiments, the via portion105bis conformal to a profile of the second opening104a.In some embodiments, the via portion105bis in a V shape.

The metallic paste106is disposed on the elongated portion105aof the PPI105. The metallic paste106is disposed at a predetermined position of the elongated portion105aand serves as a landing pad for a conductive structure subsequently disposed thereon. In some embodiments, the metallic paste106includes a concavity106afor receiving a conductive structure. In some embodiments, the concavity106ais curved towards the PPI105and the substrate101. A curvature of the concavity106acorresponds to a profile of an outer surface of the conductive structure to be disposed thereon.

In some embodiments, the metallic paste106is a mixture of a metal and an adhesive. In some embodiments, the metallic paste106includes copper or nickel. In some embodiments, a thickness of the metallic paste106is about 10 um to about 50 um.

The conductive bump107is disposed over the metallic paste106. In some embodiments, the conductive bump107is received by the metallic paste106. A portion of an outer surface107aof the conductive bump107is contacted and coupled with the concavity106aof the metallic paste106. In some embodiments, a diameter of the conductive bump107is substantially same as a width of an interface between the metallic paste106and the PPI105.

In some embodiments, the concavity106aof the metallic paste106is conformal to a portion of the outer surface107aof the conductive bump107. The conductive bump107is held by the concavity106aof the metallic paste106. As such, the conductive bump107would not shift or displace from the metallic paste103or a predetermined position of the elongated portion105aof the PPI105.

In some embodiments, the conductive bump107is configured for bonding with a bond pad of another substrate, thereby an electrical connection is established between the substrate101and another substrate. In some embodiments, the conductive bump107is in a spherical shape as a solder ball or in a cylindrical shape as a pillar. In some embodiments, the conductive bump107is a solder ball, a solder bump, a solder paste or etc. In some embodiments, the conductive bump107has a cross sectional surface in circular, quadrilateral or polygonal shape. In some embodiments, the conductive bump107includes metals such as lead, tin copper, gold, nickel, etc. or metal alloy such as combination of lead, tin copper, gold, nickel, etc.

The molding108is disposed over the polymer104and the PPI105. In some embodiments, the molding108surrounds the conductive bump107and the metallic paste106. In some embodiments, the molding108is disposed around a portion of the outer surface107aof the conductive bump107. The conductive bump107is partially encapsulated by the molding108. A top portion of the outer surface107aof the conductive bump107is exposed from the molding107.

In some embodiments, an edge106bof the metallic paste106is surrounded by the molding108. The molding108covers the metallic paste106, the PPI105and the polymer104.

In some embodiments, the molding108is formed with composite materials including epoxy resins, phenolic hardeners, silicas, catalysts, pigments and mold release agents. In some embodiments, the molding108has a high thermal conductivity, a low moisture absorption rate, a high flexural strength at board-mounting temperatures, or a combination of these. In some embodiments, the molding108is a liquid molding compound (LMC).

FIG. 2is another embodiment of a semiconductor structure200in accordance with various embodiments of the present disclosure. The semiconductor structure200includes a substrate101, a die pad102, a passivation103, a polymer104, a post passivation interconnect (PPI)105, a conductive bump107, a metallic paste106and a molding108, which are in similar configuration as inFIG. 1.

In some embodiments, the metallic paste106is covered and encapsulated by the conductive bump107. An edge106band a top surface106cof the metallic paste106is contacted with the conductive bump107.

FIG. 3is another embodiment of a semiconductor structure300in accordance with various embodiments of the present disclosure. The semiconductor structure300includes a substrate101, a die pad102, a passivation103, a polymer104, a post passivation interconnect (PPI)105, a conductive bump107, a metallic paste106and a molding108, which are in similar configuration as inFIG. 1.

In some embodiments, a width of the metallic paste106is greater than a diameter of the conductive bump107. As such, a concavity106ais contacted with a portion of the outer surface107aof the conductive bump, and an edge106band a top surface106cof the metallic paste are contacted with the molding108.

FIG. 4shows the semiconductor structure100bonded with another semiconductor structure400. The semiconductor structure400includes a substrate401and a bond pad402. In some embodiments, the semiconductor structure100is mounted on the semiconductor structure400by bonding the conductive bump107of the semiconductor structure100with the bond pad402of the semiconductor structure400. The conductive bump107is attached with the bond pad402, so that the circuit within the substrate101of the semiconductor structure100is electrically connected with the circuit within the substrate401of the semiconductor structure400through the die pad102, the PPI105, the conductive bump107and the bond pad402.

In some embodiments, the semiconductor structure100is boned with the semiconductor structure400to become a semiconductor package as a final product or as an intermediate product for subsequent operations. In some embodiments, when both semiconductor structures100and400are a package respectively, a package on package (PoP) is formed.

In the present disclosure, a method of manufacturing a semiconductor structure is also disclosed. In some embodiments, a semiconductor structure is formed by a method500. The method500includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.

FIG. 5is an embodiment of a method500of manufacturing a semiconductor structure. The method300includes a number of operations (501,502,503,504,505,506,507and508).

In operation501, a substrate101including a die pad102is received or provided as inFIG. 6A. In some embodiments, the substrate101includes silicon, ceramic, copper or etc. In some embodiments, the die pad102is disposed on or over the substrate101. The die pad102is configured for connecting a circuitry within the substrate101with an external circuitry or an external device.

In operation502, a passivation103is disposed over the substrate101and around the die pad102as inFIG. 6B. In some embodiments, the passivation103covers a surface101aof the substrate101and an edge102aof the die pad102, while a portion of a top surface102bof the die pad102is exposed from the passivation103. In some embodiments, a first opening103ais formed above the die pad102upon disposing the passivation103. Some of the passivation103adjacent to the die pad102is removed to form the first opening103a.

In operation503, a polymer104is disposed over the passivation103as inFIG. 6C. In some embodiments, the polymer104is disposed on the passivation103and within the first opening103a.A portion of the passivation103is conformal to a profile of the first opening103a.In some embodiments, a second opening104ais formed above the die pad102upon disposing the polymer104. In some embodiments, some of the polymer104adjacent to the first opening103ais removed to form the second opening104a.In some embodiments, the second opening104ais within the first opening103a.

In some embodiments, the polymer104includes a polymeric material such as epoxy, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB) or etc. In some embodiments, the polymer104is disposed by spin coating or other suitable operations.

In operation504, a post passivation interconnect (PPI)105is formed over the polymer104as inFIG. 6D. In some embodiments, the PPI105is electrically connected to the die pad102. In some embodiments, the PPI105includes an elongated portion105aand a via portion105bcontacting with the die pad102. In some embodiments, the elongated portion105ais disposed on a surface104bof the polymer104, and the via portion105bis disposed within the first opening103aof the passivation103and the second opening104aof the polymer104. The via portion105bis conformal to a profile of the second opening104a.The via portion105bis surrounded by the first opening103aand the second opening104a.In some embodiments, the PPI105is formed by electroplating, sputtering or any other suitable operations.

In operation505, a stencil109is placed on or over the PPI105as inFIG. 6E. In some embodiments, the stencil109includes an aperture109a.In some embodiments, the aperture109ais configured for receiving a metallic paste or a conductive bump in subsequent operation. In some embodiments, the aperture109acorresponds to a predetermined position of the elongated portion105aof the PPI105, thereby a metallic paste subsequently disposed on the elongated portion105awould be at the predetermined position in accordance with a position of the aperture109athe stencil109. In some embodiments, a width of the aperture109aof the stencil109is about 100 um to about 300 um. In some embodiments, a width of the aperture109ais about 150 um to about 180 um.

In operation506, a metallic paste106is deposited on the elongated portion105aof the PPI105by the stencil109as inFIG. 6F. In some embodiments, the metallic paste106includes a metal and an adhesive. In some embodiments, the metallic paste106includes copper or nickel.

In some embodiments, the metallic paste106is deposited by placing the stencil109on the PPI105and filling the aperture109aof the stencil109. The metallic paste106is deposited by screen printing operations over the stencil109. The aperture109aof the stencil109is completely filled with the metallic paste106by removing the metallic paste106overflown from the aperture109aas inFIG. 6G. The overflown metallic paste106is removed by sweeping a blade110across the semiconductor structure (along a direction as arrow A) over the stencil109.

In some embodiments, the metallic paste106is wholly or partially cured before subsequent operations. In some embodiments, the metallic paste106is cured at a temperature of about 80° C. to about 150° C.

In operation507, a conductive bump107is disposed over the metallic paste106as inFIG. 6H. The conductive bump107is electrically connected with the die pad102through the PPI105. The conductive bump107is configured for bonding with a bond pad of another substrate, thereby electrically connecting the substrate101with another substrate. As a present of the metallic paste106at the predetermined position of the elongated portion105aof the PPI105, the conductive bump107can be disposed at the predetermined position of the PPI105without any shifting. The conductive bump107can be disposed at a desired position.

In some embodiments, the conductive bump107is disposed on the metallic paste106before or after curing of the semiconductor structure. In some embodiments, a concavity106ais formed for receiving the conductive bump107when the metallic paste106is cured. The metallic paste106is facilitated to hold the conductive bump107, such that the conductive bump107would not be shifted from the predetermined position during subsequent operations such as reflowing, curing, etc. In some embodiments, the conductive bump107includes metal such as lead, tin copper, gold, nickel, etc. or metal alloy such as combination of lead, tin copper, gold, nickel, etc.

The conductive bump107has different reflow temperature from the metallic paste106. In some embodiments, the conductive bump107is a lead (Pb)-containing solder which has a reflow temperature of about 180° C. to about 250° C. In some embodiments, the conductive bump107is a lead-free solder which has a reflow temperature of about 220° C. to about 250° C. In some embodiments, the metallic paste106has a reflow temperature of about 300° C. to about 800° C. In some embodiments, there is a ratio of the reflow temperature of the conductive bump107to the reflow temperature of the metallic paste106. The ratio is about 1:1.5 to about 1:3.5.

In some embodiments, the stencil109is removed before disposing the conductive bump107. In some embodiments, the conductive bump107is disposed on the metallic paste106by disposing a photoresist over the PPI105, forming a pattern on the photoresist by photolithography, plating a solder flux according to the pattern of the photoresist, stripping a remaining photoresist and reflowing the solder flux to form the conductive bump107.

In some embodiments, the conductive bump107is disposed by the stencil109. The stencil109is still placed on the PPI105. The conductive bump107is dropped on the metallic paste106in accordance with the position of the aperture109a.In some embodiments, the stencil109is removed after disposing the conductive bump107.

In operation508, a molding108is disposed over the PPI105and around the metallic paste106and the conductive bump107as inFIG. 6I. In some embodiments, the molding108is a liquid molding compound (LMC). In some embodiments, the molding108covers the metallic paste106and a portion of an outer surface107aof the conductive bump107. A portion of an outer surface107aof the conductive bump107is exposed from the molding108, so that the conductive bump107can bond with another substrate in subsequent operation. In some embodiments, the semiconductor structure600is formed, which is in similar configuration as the semiconductor structure100ofFIG. 1.

In some embodiments, the semiconductor structure600is bonded with another semiconductor structure700as inFIG. 6J. In some embodiments, the semiconductor structure700is a PCB or a semiconductor package. In some embodiments, the semiconductor structure700includes a substrate701including a circuitry and a bond pad702disposed on the substrate701. In some embodiments, the bond pad702is disposed on or over a surface of the substrate701.

In some embodiments, the conductive bump107of the semiconductor structure600is melted by heat treatment such as reflowing, and then the molten bump107is attached on the bond pad702of the semiconductor structure700. As such, the conductive bump107is bonded with the bond pad702after cooling operations. Thus, the semiconductor structure600is mounted on the semiconductor structure700, and the circuit of the substrate701is electrically connected with the circuit of the substrate101through the die pad102, the PPI105, the conductive bump107and the bond pad702.

In the present disclosure, a semiconductor structure includes a metallic paste disposed on the PPI and served as a landing pad for a conductive bump to be disposed. The metallic paste is disposed at a predetermined position of the PPI by a stencil, then the conductive bump would be disposed on the metallic paste. As such, the conductive bump can be disposed at the predetermined position according to a position of the metallic paste. In addition, the metallic paste is configured to hold the conductive bump, and therefore, the conductive bump would maintain at the predetermined position of the PPI without shifting throughout subsequent operations such as reflowing, curing, etc. Shifting of the conductive bump is minimized and a reliability of the semiconductor structure is improved. Also, the metallic paste intermediate between the conductive bump and the PPI can minimize or avoid electron migration from the PPI to the conductive bump, and thus formation of void or development of cracks within the PPI can also be avoided.

In some embodiments, a method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon, disposing a passivation over the substrate and around the die pad, disposing a polymer over the passivation, forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad, depositing a metallic paste on the elongated portion of the PPI by a stencil, disposing a conductive bump over the metallic paste, and disposing a molding over the PPI and around the metallic paste and the conductive bump.

In some embodiments, the depositing the metallic paste includes screen printing the metallic paste over the stencil. In some embodiments, the depositing the metallic paste includes sweeping across the semiconductor structure over the stencil by a blade to remove the overflown metallic paste. In some embodiments, the stencil includes an aperture corresponding to a predetermined position of the elongated portion of the PPI. In some embodiments, the conductive bump is disposed by the stencil. In some embodiments, the method further includes curing the metallic paste to form a concavity for receiving the conductive bump.

In some embodiments, the metallic paste includes a metal and an adhesive. In some embodiments, the method further includes curing the semiconductor structure before or after disposing the conductive bump. In some embodiments, the disposing the passivation includes forming a first opening above the die pad, and the via portion is disposed within the first opening. In some embodiments, the disposing the polymer includes forming a second opening above the die pad, and the via portion is disposed within the second opening.

In some embodiments, a method of manufacturing a semiconductor structure includes receiving a substrate including a passivation disposed over the substrate and a die pad exposed from the passivation, disposing a polymer over the passivation, forming a post passivation interconnect (PPI) electrically connected to the die pad, placing a stencil on the PPI, filling an aperture of the stencil by a metallic paste, disposing a conductive bump on the metallic paste, removing the stencil, and disposing a molding over the PPI and around the metallic paste and the conductive bump.

In some embodiments, the aperture of the stencil is configured for receiving the metallic paste or the conductive bump. In some embodiments, the stencil is placed on the PPI during the filling of the metallic paste and the disposing of the conductive bump. In some embodiments, the aperture of the stencil is completely filled with the metallic paste by removing the metallic paste overflown from the opening.

In some embodiments, a semiconductor structure includes a substrate, a die pad disposed over the substrate, a passivation surrounding an edge of the die pad, a polymer disposed over the passivation, a post passivation interconnect (PPI) including an elongated portion and a via portion contacted with the die pad, a metallic paste disposed on the elongated portion, a conductive bump disposed over the metallic paste, and a molding surrounding the conductive bump and the metallic paste, wherein the metallic paste includes a concavity for receiving the conductive bump, and the molding covers the metallic paste.

In some embodiments, the concavity of the metallic paste is conformal to a portion of an outer surface of the conductive bump. In some embodiments, a diameter of the conductive bump is substantially same as a width of an interface between the metallic paste and the PPI. In some embodiments, the metallic paste is a mixture of a metal and an adhesive. In some embodiments, the metallic paste includes copper or nickel. In some embodiments, a thickness of the metallic paste is about 10 um to about 5 um.