Reduced edge effect from recesses in imagers

Methods for making a recessed color filter array for a semiconductor imager employing a sidewall spacer for reducing an edge effect from the array are disclosed. In one embodiment, a substrate is provided having an upper surface. Then, a recess is formed into the upper surface of the substrate. The recess has a bottom and a sidewall. Subsequently, a sidewall spacer is formed on the sidewall of the recess. A color resist is deposited into the recess after forming the sidewall spacer. In the embodiment, the sidewall spacer is formed of a material having a surface energy lower than that of a material defining the bottom of the recess. The color resist adheres less to the sidewall than to the bottom of the recess. Thus, the color resist does not conform to a shape of an edge portion of the recess, thereby reducing the edge effect.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to imagers, and more particularly to semiconductor imagers having recessed color filter arrays.

2. Description of the Related Art

Recent developments in the electronics industry have increased demand for imagers that digitally capture images. Among other things, semiconductor imagers (e.g., CMOS imagers) are known to provide certain advantages over other types of imagers, for example, small system size, low power consumption, camera-on-a-chip integration, and low fabrication costs.

As semiconductor imagers are used in smaller devices, there has been a need to reduce the sizes of semiconductor imagers. Attempts have been made to provide a semiconductor imager with a small stack height.

One approach is to use a recessed color filter array (CFA), as discussed in co-owned, pending U.S. application Ser. No. 11/513,246, filed Aug. 31, 2006 entitled RECESSED COLOR FILTER ARRAY AND METHOD OF FORMING THE SAME. A color filter array is an imager component which filters lights of different colors prior to conversion of an image into an electrical signal. A typical color filter array is formed on an imager substrate. Unlike the typical color filter array, a recessed color filter array is positioned in a recess formed into an imager substrate. An imager with a recessed color filter array thus has a reduced stack height.

DETAILED DESCRIPTION OF EMBODIMENTS

Semiconductor Imager with Recessed Color Filter Array

FIG. 1Aillustrates an exemplary imager100according to one embodiment. The imager100includes a substrate110having an upper surface101. The substrate110includes a recess102formed into the upper surface101. The imager100also includes a color filter array (CFA)120in the recess102. The illustrated color filter array120includes a plurality of color filters arranged in a matrix pattern. The skilled artisan will appreciate that the imager100is a single die generally formed by semiconductor processing (e.g., patterning, doping, depositing, etching, etc.) several such devices on a single substrate (e.g., silicon wafer) and subsequently dicing.

The color filters of the illustrated embodiments include color filters of different colors. In one embodiment, the color filters include red (R), green (G), and blue (B) color filters. The R, G, and B color filters may be arranged in various patterns.

Referring toFIG. 1B, the illustrated filter pattern is 50% green, 25% red, and 25% blue. The filters121R,121G for pixels in every two rows in the array120have a repeating pattern of R, G, R, G. The filters122G,122B for pixels in the other alternating rows have a repeating pattern of G, B, G, B. A well-known exemplary pattern is the Bayer pattern, which follows the characteristics noted above. In another embodiment, each row in the array may have a repeating pattern of R, G, B, R, G, B.

FIG. 1Cis a cross-section of the imager100ofFIG. 1A, taken along the lines1C-1C. The illustrated imager100includes a base plate111, a dielectric structure112, a color filter array120, photodiodes130, and conductive lines140at various metal levels. In the context of this document, the base plate111and the dielectric structure112and all other integrated features may be collectively referred to as a “substrate”110.

The base plate111serves as a template which supports the photodiodes130and the dielectric structure112. In addition, the base plate111may include embedded electronic circuits for the imager100. In one embodiment, the base plate111is formed of, for example, a semiconductor such as a silicon wafer. In other embodiments, the base plate111may have a silicon-on-insulator (SOI) structure, a silicon-on-sapphire (SOS) structure, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, or other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor may be silicon-germanium, germanium, or gallium arsenide or other semiconductor materials. The base plate111may have a thickness on the order of about 500 μm for a 300 mm wafer.

The dielectric structure112is formed as a series of interlevel dielectric layers between metallization levels on the base plate111. The dielectric structure112provides insulation between conductive components of the imager100while supporting the color filter array120. In one embodiment, the dielectric structure112may include a form of silicon oxide such as BPSG, TEOS, low k dielectrics (fluorine- and/or carbon-doped porous materials, etc.), spin-on glass, or polymers such as polyamide. The dielectric structure112may have an overall thickness H1from about 4 μm to about 6 μm. The dielectric structure112has an upper surface101facing away from the base plate111.

The dielectric structure112includes a recess102formed into the upper surface101. The recess102may have various shapes, e.g., square, rectangular, or circular shape, when viewed from over the dielectric structure112. In the illustrated embodiment, the recess102has a depth D1of about 1 μm to about 3 μm, for example about 2 μm. The recess102may have a width W1from about 4 mm to about 5 mm, but may vary widely depending on the size of the die. The recess102has a bottom102aand a sidewall102b. The terms “bottom” and “sidewall” of a recess refer to the general region of the recess, rather than particular surfaces, and thus are intended to be generic to the presence or absence of lining layers within the recess. Thus, in one embodiment, surfaces of the dielectric structure112may form the bottom and sidewall of the recess. In other embodiments, there may be an additional layer between the bottom/sidewall and the dielectric structure112. In the context of this document, the terms “bottom surface” and “sidewall surface” of a recess only refer to the surfaces defined by the dielectric structure112of the substrate110.

The color filter array120is formed on the bottom102aof the recess102. The illustrated color filter array120does not protrude beyond the level of the upper surface101of the dielectric structure112. Thus, this configuration allows the stack height of the imager100to be the same as or less than the thickness of the dielectric structure112. In the context of this document, the term “stack height” refers to the height of layers above the photodiodes130within the base plate111to the top points of the color filter array120(i.e., excluding any subsequent lens structures).

The color filter array120includes a plurality of color filters121and a plurality of lenses122formed on the color filters121. The color filters121are arranged in a predetermined pattern, as described above with reference toFIG. 1B. The color filters121may be formed of a partially transparent material containing a pigment. An example of the partially transparent material is a colored photoresist. A skilled artisan will appreciate that various materials may be used for the color filters121. The lenses122are formed of a substantially transparent material, e.g., propylene glycol monoethylether acetate (PGEEA).

The photodiodes130are embedded in, formed on, or otherwise integral with the base plate111. The photodiodes130are arranged in a predetermined pattern corresponding to the color filter array pattern. Each of the photodiodes130is configured to convert light into an electrical signal. The photodiodes130are together configured to provide image signals corresponding to an image or sequence of images to which the imager100is exposed. One of the color filters121, one of the lenses122, and one of the photodiodes130are vertically aligned with one another, and together form a single pixel. In one embodiment, a single pixel has a width W2from about 1.4 μm to about 6 μm. Each pixel is also associated with circuit elements (not shown) controlling amplification and readout functions, such as a transfer transistor, reset transistor, row select transistor, source follower transistor and floating diffusion node. In some arrangements, one of more of these circuit elements may be shared among multiple pixels.

The conductive lines140are embedded in the dielectric structure112. Some of the conductive lines140are positioned under the recess102while others are positioned lateral to the recess102or lateral to the conductive lines under the recess102. The conductive lines140under the recess102are positioned so as to avoid or minimize blocking light paths between the color filters122and the photodiodes130. The conductive lines140serve to provide electrical connection between various components of the imager100.

Formation of Color Filter Array

FIGS. 2A and 2Billustrate an exemplary process of forming a recessed color filter array for a semiconductor imager. Referring toFIG. 2A, a substrate210(which may include integrated dielectric and metal layers as described above with respect toFIG. 1C) is provided having an upper surface201. The substrate210includes a recess202formed into the upper surface201. The recess202has a bottom202aand a sidewall202b. The recess202may be formed by any suitable process, including, but not limited to, photolithography and etching. In the illustrated embodiment, the recess202may have a depth of about 1 μm to about 3 μm, for example about 2 μm. Although not shown, the substrate210may be provided with a passivation layer on the upper surface201of the substrate210and/or on the bottom and sidewall surfaces202a,202bof the recess202. The passivation layer may be formed of silicon nitride (Si3N4).

Referring toFIG. 2B, a color resist221is deposited into the recess202and on the upper surface201of the substrate210. The color resist221forms a color filter layer for the imager. The color resist221may include a photosensitive material, a binder, a pigment, and various additives. The color resist221may be deposited using any suitable method. In the illustrated method, the color resist221is deposited using spin coating.

The color filter layer221formed by the illustrated method tends to have a non-uniform thickness at an edge region202cof the recess202near the sidewall202bthereof. The color filter layer221is thicker at the edge region202cof the recess202than at other regions of the recess202. In the context of this document, this phenomenon is referred to as an “edge effect.” The edge effect occurs because the surface tension of the color resist221forces the color resist221to somewhat conform to the shape of the recess202. In certain instances, the edge region202cwhere the edge effect occurs may have a horizontal width W3from about 50 μm to about 100 μm from the sidewall202b.

The edge effect causes signal drops (up to about 25%) at pixels within edge regions of a recessed color filter array.FIG. 2Cis a graph showing such light intensity signal drops due to the edge effect. InFIG. 2C, two circles indicate signal drops at or near two opposing edges of a recessed color filter array. Signals indicated by the circles are significantly lower than those in the region between the edges.

In one embodiment, the sidewall of the recess is treated prior to depositing a color filter material in order to mitigate or prevent the edge effect, particularly to reduce surface energy on adhesion characteristics. The sidewall may be selectively surface-treated so as to have a low surface energy relative to other surfaces of the imager. In one embodiment, a layer or spacer having a low surface energy is formed on the sidewall of the recess. In other embodiments, a protrusion is formed at or near a boundary between the recess and the upper surface of the substrate. The protrusion encourages the color filter material to be discontinuous between the recess and the substrate upper surface, thus reducing surface tension in the deposited color filter material. The protrusion may be vertical, horizontal, or at a certain angle relative to the substrate upper surface.

FIGS. 3A-3Iillustrate a process of forming a recessed color filter array according to one embodiment. Referring toFIG. 3A, a substrate310is provided having an upper surface301. The illustrated portion of the substrate310may include an integrated dielectric structure, and the substrate310of the illustrated embodiment is also otherwise as described above with reference toFIG. 1C. The substrate310thus also includes a base plate or workpiece (e.g., silicon wafer) underlying the dielectric structure. The substrate310may also include conductive lines (not shown) and photodiodes (not shown) embedded therein, as described above with respect to the conductive lines140and the photodiodes130ofFIG. 1C.

The substrate310includes a recess302formed into the upper surface301. The recess302has a bottom surface302cat the bottom302aof the recess302and a sidewall surface302dat the sidewall302b. The recess302may be formed by any suitable process, including, but not limited to, photolithography and etching. In the illustrated embodiment, the recess302may have a depth of about 1 μm to about 3 μm, for example about 2 μm.

Next, in the illustrated embodiment, a passivation layer303is formed conformally on the upper surface301of the substrate310and on the bottom and sidewall surfaces302c,302dof the recess302, as shown inFIG. 3B. The passivation layer303is configured to seal surfaces of the substrate310, including the surfaces302c,302dof the recess302. The passivation layer303serves to protect conductive lines, photodiodes, and various other components (e.g., circuits) under the recess302and the upper surface301of the substrate310. The passivation layer303on at least the bottom302aof the recess302may also provide a surface suitable for adhesion of a color filter material which will be described below. The passivation layer303may also be referred to as a “liner layer.”

In one embodiment, the passivation layer303may be formed of silicon nitride (Si3N4). Silicon nitride has a surface energy of about 56.8 dynes/cm. The passivation layer303may have a thickness of about 150 Å to about 400 Å, for example about 220 Å. It will be appreciated that any suitable materials may be used for the passivation layer303. Other exemplary passivation materials include silicon oxynitride (SiOxNy) and silicon carbide (SiC). It will also be appreciated that the passivation layer303may be omitted if the substrate material may provide sufficient protection over components embedded therein, and adhesion for the subsequent color filter material, in which case the bottom302aand sidewall302bwould be defined by the dielectric structure.

Subsequently, an adhesion-reduction layer304is formed on the passivation layer303, as shown inFIG. 3C. The adhesion-reduction layer304is formed of a material having a low surface energy or a hydrophobic material. In particular, the material has a surface energy lower than that of a material defining the bottom302aof the recess302. In the illustrated embodiment, the adhesion-reduction layer304has a surface energy lower than that of the passivation layer303which will define the bottom302aof the recess302, as will be better understood from description below. The surface energy of the passivation layer303may be from about 55 dynes/cm2to about 65 dynes/cm2. The surface energy of the adhesion-reduction layer304may be not greater than about 40 dynes/cm2, particularly from about 12 dynes/cm2to about 40 dynes/cm2, and more particularly from about 12 dynes/cm2to about 30 dynes/cm2.

The adhesion-reduction layer304may be formed of an organic material. In one embodiment, the adhesion-reduction layer304is formed of a self-assembled monolayer (SAM) material, particularly a fluorinated SAM material, such as 1H,1H,2H,2H-perfluorodecyltrichlorosilane (FDTS). FDTS has a surface energy of about 11.7 dynes/cm. A skilled artisan will appreciate that any suitable low surface energy or hydrophobic material may be used for the adhesion-reduction layer304.

The adhesion-reduction layer304is formed conformally or isotropically over the upper surface301of the substrate and on the bottom and sidewall302a,302bof the recess302. The adhesion-reduction layer304may have a thickness between about 10 Å and about 3,000 Å, depending on the material selection. In one embodiment, the adhesion-reduction layer304is formed using a spin coating process. It will be appreciated that any suitable deposition process may be used for forming the layer304.

As shown inFIG. 3D, the adhesion-reduction layer304is then removed from the bottom302aof the recess302, while a portion of the layer304is maintained on the sidewall302bof the recess302. In the illustrated embodiment, the adhesion-reduction layer304is removed from substantially the entire portion of the bottom302aof the recess302. The portion remaining selectively on the sidewall302bof the recess302is known as a “sidewall spacer.” The sidewall spacer will generally have a width corresponding to the thickness of the spacer material deposited (e.g., about 10 Å to about 3,000 Å). In the case of SAMs, the spacer can accomplish its function in very thin layers (e.g., 1 to 15 monolayers, particularly about 10 Å to about 150 Å).

This removal process may be conducted using an anisotropic or directional etching process, also known in the art as a spacer etch when used to selectively remove horizontal portions of a layer while leaving vertical layers on sidewall surfaces. Such an anisotropic etching process may be a dry etching process. While a purely physical sputter etch (e.g., argon sputter etch) may be used, a reactive ion etch (RIE) may supply a chemical component that is selective for the spacer material and stops on the underlying material. In certain embodiments, the etching process may be non-selective to the underlying material and actually remove the spacer material by undercutting. In the embodiment in which the adhesion-reduction layer304is formed of FDTS, an exemplary etchant used in this removal step is CF4/O2directional plasma. Because FDTS forms a very thin layer having a thickness of, for example, about 15 Å to about 30 Å, a high speed etchant may readily penetrate the thin FDTS layer. Thus, the etchant may reach the passivation layer303, and may remove a little portion of the passivation layer303underneath the FDTS layer304, thereby removing horizontal portions of the spacer material by undercutting. A skilled artisan will appreciate that various techniques may be employed to provide the structure shown inFIG. 3D.

The partially fabricated imager300shown inFIG. 3Dminimizes or prevents the edge effect when a color resist is deposited into the recess302. The imager300has different surface energies on the bottom and sidewall302a,302bof the recess302. In the illustrated embodiment, the bottom302aof the recess302has the passivation layer303having a first surface energy while the sidewall302bof the recess302has the adhesion-reduction layer304having a second surface energy lower than the first surface energy. A difference between the first and second surface energies may be between about 20 dynes/cm2and about 45 dynes/cm2, and particularly between about 30 dynes/cm2and about 45 dynes/cm2. Thus, when a color filter material is deposited into the recess302, it adheres less to the sidewall302bthan to the bottom302a, thereby minimizing or preventing the edge effect. Yet, the adhesion of the color filter material on the bottom302aof the recess302may be maintained because the bottom302aof the recess302may include a liner material suitable for the adhesion.

Subsequently, a color filter material, particularly a color resist321G, is deposited on the passivation layer303into the recess302and over the upper surface301of the substrate310, as shown inFIG. 3E. The color resist321G will be used to form a green color filter layer for the imager. The illustrated color resist321G thus contains a green pigment. In one embodiment, the color resist includes at least one of propylene glycol monomethyl ether acetate (PGMEA), ethyl 3-ethoxypropionate (EEP), cyclohexanone and acrylic resin. The color resist may include various other additives depending on the materials used for the color filter array.

The color resist of the embodiment has a surface energy higher than the material of the sidewall spacer304. In the illustrated embodiment, the color resist321G has a surface energy of about 42 dynes/cm.

Then, the color filter layer321G is patterned to provide spaces for color filters of other colors, as shown inFIG. 3F. The color filter layer321G is also removed from the upper surface301of the substrate310. The color filter layer321G may be patterned or removed, using any suitable process, including, but not limited to, photolithography. In one embodiment, the color filter layer321G is a photoresist material that is directly exposed and developed.

Next, a second color filter material, particularly a second color resist321R, is deposited into the recess302and over the upper surface301of the substrate310, as shown inFIG. 3G. This second color resist321R fills the spaces between the green color filters321G. The illustrated second color resist321R includes a red pigment and thus will serve as a red color filter in the imager. The red color resist321R is then patterned to provide spaces for color filters of yet another color, for example, blue.

Although not shown, a third color resist is deposited into the recess302and over the upper surface301of the substrate310. The third color resist321B fills the spaces between the patterned color filters321G,321R. In one embodiment, the third color resist includes a blue pigment and thus will serve as a blue color filter for the imager. The distribution of the color filters321R,321G,321B may be as described above with reference toFIG. 1B. The third color resist is thinned such that blue color filters have a height the same as those of the red and green color filters321R,321G. In one embodiment, the blue color resist overlying the upper surface301of the substrate310is also removed, exposing the passivation layer303over the upper surface301of the substrate310.

As described above, the adhesion-reduction layer304on the sidewall302bof the recess302minimizes or prevents the edge effect during deposition of the color filter materials. Thus, the resulting color filters have a substantially uniform thickness across the substrate, including the edge regions of the recess302. The color filters may have a thickness of about 0.5 μm to about 1.1 μm, e.g., about 0.9 μm.

Finally, lenses322are formed on the color filters321, as shown inFIG. 3I. It will be appreciated that any suitable process may be used to form the lenses322.

FIGS. 4A-4Gillustrate a process of forming a recessed color filter array according to another embodiment. In addition to the sidewall spacer as described above with reference toFIG. 3D, the illustrated method also includes providing a horizontal protrusion or reentrant profile at or near edges of a recess formed into a surface of a substrate. The horizontal protrusion further mitigates the edge effect by preventing a color filter layer from being continuous between the recess and the surface of the substrate during deposition.

Referring toFIG. 4A, a substrate410is provided having an upper surface401. Although not shown, the substrate410may have conductive lines, photodiodes, and the like embedded therein, as described above with reference toFIG. 1C.

Then, a hard mask (or protrusion-forming) layer405is formed on the upper surface401of the substrate410. In one embodiment, the hard mask layer405is formed of a material such as silicon nitride (Si3N4) that is resistant to a suitably selective isotropic etch of dielectric structure to be recessed.

Subsequently, a portion of the hard mask layer405is removed, as shown inFIG. 4B. This step may be conducted, using any suitable process, including, but not limited to, photolithography. In one embodiment, this hard mask removal step may be conducted, using a dry etching process.

In addition, a portion of the substrate directly underlying the portion of the hard mask layer405is also removed, thereby forming an intermediate recess406, as shown inFIG. 4B. As discussed with respect to the previous embodiments, the recess406is formed in a dielectric structure in which metallization levels are formed. As will be better understood from description below, the intermediate recess406has a size smaller than that of a recess402(FIG. 4C) which will be formed at the next step. The size may include a width and a depth. The depth of the intermediate recess406may be about 0.5 μm to about 2.5 μm.

This substrate material removal step may be conducted by continuing the etching process for removing the portion of the hard mask layer405, using the same etchant while the photoresist mask remains in place. In another embodiment, the portion of the substrate410may be removed using a different etchant selective for the substrate material relative to the hard mask layer405. In such an embodiment, the photoresist mask used to pattern the hard mask405is first removed and the hard mask layer405may serve as a mask for etching the substrate410.

Subsequently, the intermediate recess406is expanded to create a protrusion405a,405bthat shadows a reentrant region on the sidewall402b, as shown inFIG. 4C. In other words, the sidewall402b, and particularly the substrate's sidewall surface402dtakes on a reentrant profile. At this step, the size of the intermediate recess406is increased to a predetermined size, thereby completing formation of the recess402. In the illustrated embodiment, the recess402may have a depth of about 1 μm to about 3 μm, for example about 2 μm. The hard mask layer405, however, is maintained substantially intact on top of the substrate410. As a result, the protrusion405a,405bis formed to extend substantially horizontally over the recess402. Although not shown inFIG. 4C, the illustrated protrusion405a,405bis continuous and annular along the edge of the recess402when viewed from over the substrate410. In other embodiments, however, discontinuous multiple protrusions are also possible.

At this step, any suitable etching process may be used to remove the substrate material. In one embodiment, an isotropic wet etching process is conducted using an etchant selective for the substrate material (dielectric structure) relative to the hard mask layer material. In the illustrated embodiment in which the dielectric structure is formed of silicon oxide, an etchant selective for silicon oxide relative to silicon nitride may be used at this step. In one embodiment, the etch recesses between about 0.5 μm and about 2.0 μm of the dielectric structure, and particularly between about 0.5 μm and about 1.0 μm.

Next, in the illustrated embodiment, a passivation layer403is deposited conformally into the recess and on the upper surface of the substrate410, as shown inFIG. 4D. The deposition of the passivation layer403may be carried out using, for example, atomic layer deposition (ALD). The material of the passivation layer403may be as described above with respect to that of the passivation layer303ofFIG. 3B. The passivation layer403may also cover the protrusion405a,405b. The illustrated passivation layer403covers the top, side, and bottom surfaces of the protrusion405a,405b.

In another embodiment in which the passivation layer is formed using chemical vapor deposition (CVD), the passivation layer may be less thick in the reentrant region405cof the recess than in other regions of the recess. In yet another embodiment in which physical vapor deposition (PVD) is used to form the passivation layer, the passivation layer may be formed on the bottom402aand sidewall402bof the recess402and over the upper surface401of the substrate410.

An adhesion-reduction layer404is then deposited conformally on the bottom and sidewall402a,402bof the recess402and over the upper surface401of the substrate410, as shown inFIG. 4E. The adhesion-reduction layer404also covers the protrusion405a,405b. The deposition of the adhesion-reduction layer404may be carried out using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The material of the adhesion-reduction layer404may be as described above with respect to that of the adhesion-reduction layer304ofFIG. 3C.

Then, the adhesion-reduction layer404is substantially removed from the bottom402aof the recess402and the upper surface401of the substrate410, as shown inFIG. 4F. The adhesion-reduction layer404is maintained on the sidewall402bof the recess402. The adhesion-reduction layer404is also maintained on the underside of the protrusion405a,405b. The illustrated adhesion-reduction layer404also remains on edge portions of the recess402underlying the protrusion405a,405bbecause the edge portions are shadowed during the removal step. This step may be conducted using an anisotropic or directional etching process. An etchant used in this step is selective for the adhesion-reduction layer404relative to the passivation layer403. Details of this step may be as described above with respect to the step shown inFIG. 3D.

The partially fabricated imager400shown inFIG. 4Fminimizes or prevents the edge effect when a color resist is deposited into the recess402. The imager400has different surface energies on the bottom and sidewall402a,402bof the recess402. The bottom402aof the recess402has the passivation layer403having a first surface energy while the sidewall402bof the recess402has the adhesion-reduction layer404having a second surface energy lower than the first surface energy. Thus, when a color filter material such as a color resist is deposited into the recess402, it adheres less to the sidewall402bthan to the bottom402a, thereby minimizing or preventing the edge effect. Yet, the adhesion of the color filter material on the bottom402aof the recess402may be maintained because the bottom402aof the recess402exposes a material suitable for the adhesion (in the illustrated embodiment the passivation layer403). In addition, the protrusion405a,405bprevents the color resist from being formed continuously between the sidewall402bof the recess402and the uppermost surface401aof the substrate410.FIG. 4Gillustrates the resulting imager structure400with a color resist421deposited in the recess402. Although not shown, subsequently, steps for patterning the color resist and steps for forming lenses are conducted, as described above with reference toFIGS. 3F-3I.

FIGS. 5A-5Gillustrate a partial process of forming a recessed color filter array according to yet another embodiment. The illustrated method includes providing a vertical protrusion at or near an edge of a recess. Similar to the horizontal protrusion405a,405bshown inFIG. 4G, the vertical protrusion also mitigates the edge effect by preventing a color filter layer from being formed continuously between the recess and the surface of the substrate during deposition.

Referring toFIG. 5A, a substrate510is provided having an upper surface501. Although not shown, the substrate510may have conductive lines, photodiodes, and the like embedded therein, as described above with reference toFIG. 1C.

Then, a recess502is formed into the upper surface501of the substrate510, as shown inFIG. 5B. The recess502has a bottom surface502cat the bottom502aof the recess502and a sidewall surface502dat the sidewall502bof the recess502. The configuration of the recess502may be as described above with respect to the recess102ofFIG. 1C. In the illustrated embodiment, the recess502may have a depth of about 1 μm to about 3 μm, for example about 2 μm.

Next, a passivation layer503is formed conformally on the bottom and sidewall surfaces502c,502dof the recess502and on the upper surface501of the substrate510, as shown inFIG. 5C. The material of the passivation layer503may be as described above with respect to that of the passivation layer303ofFIG. 3B. In certain embodiments, the passivation layer503may be formed only on the bottom surface502cof the recess502.

Then, a protrusion505a,505bis formed over the upper surface501of the substrate510proximate to the recess502, as shown inFIG. 5D. Although not shown inFIG. 5D, the illustrated protrusion505a,505bis continuous and annular along the edge of the recess502when viewed from over the substrate510. In other embodiments, however, discontinuous multiple protrusions are also possible. The protrusion505a,505bmay be formed of any suitable material. In one embodiment, the protrusion505a,505bis formed of a material resistant to the spacer etch to be employed, such as silicon nitride (Si3N4). The protrusion505a,505bmay be formed by any suitable process, including, but not limited to, photolithography. In one embodiment, the protrusion505a,505bmay be formed by forming a layer with a protrusion-forming material and subsequently patterning the layer. The layer may have a thickness505T of between about 0.3 μm and about 2 μm, and particularly between about 0.5 μm and about 1.0 μm.

The illustrated protrusion505a,505bhas two side surfaces, one of which is approximately continuous with the sidewall402bof the recess402. The protrusion505a,505bmay have a width505W of about 0.1 μm to about 1.0 μm, and particularly about 0.2 μm to about 0.5 μm. In other embodiments, the protrusion505a,505bmay be sloped by the etch process used to pattern it. The protrusion505a,505bmay have an angle from about 0° to about 90° relative to the upper surface501of the substrate510.

An adhesion-reduction layer504is then deposited conformally on the bottom and sidewall502a,502bof the recess502and over the upper surface501of the substrate510, as shown inFIG. 5E. The illustrated adhesion-reduction layer504also covers the protrusion505a,505b. The material of the adhesion-reduction layer504may be as described above with respect to that of the adhesion-reduction layer304ofFIG. 3C.

Then, the adhesion-reduction layer504is removed from substantially entire portion of the bottom502aof the recess502and the upper surface501of the substrate510by an anisotropic spacer etch, as shown inFIG. 5F. The adhesion-reduction layer504is maintained on the sidewall502bof the recess502. The adhesion-reduction layer504is also maintained on the side surfaces of the protrusion505a,505b. This step may be conducted, using an anisotropic or directional etching process. An etchant used in this step is selective for the adhesion-reduction layer504relative to the passivation layer503. Details of this step may be as described above with respect to the step shown inFIG. 4F.

The partially fabricated imager500shown inFIG. 5Fminimizes or prevents the edge effect when a color resist is deposited into the recess502. The imager400has different surface energies on the bottom and sidewall502a,502bof the recess502. The bottom502aof the recess502has the passivation layer503having a first surface energy while the sidewall502bof the recess502has the adhesion-reduction layer504having a second surface energy lower than the first surface energy. Thus, when a color filter material such as a color resist is deposited into the recess502, it adheres less to the sidewall502bthan to the bottom502a, thereby minimizing or preventing the edge effect. Yet, the adhesion of the color filter material on the bottom502aof the recess502may be maintained because the bottom502aof the recess502may expose a material suitable for the adhesion (in the illustrated embodiment the passivation layer503). In addition, the protrusion505a,505bprevents the color resist from being formed continuously between the sidewall502bof the recess502and the upper surface501aof the substrate510.FIG. 5Gillustrates the resulting imager structure500with a color resist521deposited in the recess502. Although not shown, subsequently, steps for patterning the color resist and steps for forming lenses are conducted, as described above with reference toFIGS. 3F-3I.

FIG. 6illustrates a block diagram of a semiconductor imager600constructed in accordance with one of the embodiments described above. The imager600contains an array of pixels620and employs a sidewall spacer within the recess according to one of the embodiments shown inFIGS. 3-5. Attached to the pixel array620is signal processing circuitry for controlling the pixel array620. The pixel cells of each row in the array620are all turned on at the same time by a row select line, and the pixel cells of each column are selectively output by respective column select lines. A plurality of row select and column select lines are provided for the entire array620. The row lines are selectively activated by a row driver645in response to a row address decoder655. The column select lines are selectively activated by a column driver660in response to a column address decoder670. Thus, a row and column address is provided for each pixel cell.

The imager600is operated by a timing and control circuit652, which controls the address decoders655,670for selecting the appropriate row and column lines for pixel readout. The control circuit652also controls the row and column driver circuitry645,660such that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal Vrstand a pixel image signal Vsig, are output to the column driver660, on output lines, and are read by a sample and hold circuit661. Vrstis read from a pixel cell immediately after the pixel cell's floating diffusion region is reset. Vsigrepresents the amount of charges generated by the photosensitive element of the pixel cell in response to applied light during an integration period. A differential signal (Vrst−Vsig) is produced by a differential amplifier662for each readout pixel cell. The differential signal is digitized by an analog-to-digital converter675(ADC). The analog-to-digital converter675supplies the digitized pixel signals to an image processor680, which forms and outputs a digital image.

FIG. 7illustrates a processor system700that includes an imager600constructed in accordance with an embodiment. As discussed above, the imager600contains an array of pixels and employs a sidewall spacer within the recess according to any embodiment shown inFIGS. 3-5. The system700has digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and other imaging sensing and/or processing system.

The system700, for example a camera system, generally includes a central processing unit (CPU)702, such as a microprocessor, that communicates with an input/output (I/O) device706over a bus704. The imager600also communicates with the CPU702over the bus704. The processor system700also includes a random access memory (RAM)710, and may include a removable memory715, such as a flash memory, which also communicates with the CPU702over the bus704. The imager600may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.

In the embodiments described above, the adhesion-reduction layer on the sidewall of the recess provides a surface energy difference between the bottom and sidewall of the recess. In addition, in some of the embodiments described above, the protrusion at the edge of the recess prevents the color filter materials from being formed continuously between the sidewall of the recess and the upper surface of the substrate. These configurations minimize or prevent the edge effect during deposition of the color filter materials. Thus, the resulting color filters have a substantially uniform thickness across the array, including the edge regions of the array. Yet, the adhesion of the color filter materials on the bottom of the recess may be maintained because the bottom of the recess may include a material suitable for the adhesion.

One embodiment is a method of making a semiconductor imaging device. The method includes providing a substrate having an upper surface. Then, a recess is formed into the upper surface of the substrate. The recess has a bottom and a sidewall. A sidewall spacer is formed on the sidewall of the recess. Then, a color filter layer is formed within the recess after forming the sidewall spacer.

Another embodiment is a method of making a CMOS imager. The method includes providing a substrate having an upper surface and a recess formed into the upper surface. The recess has a bottom and a sidewall. A liner layer is formed at least on the bottom of the recess. The liner layer is formed of a first material having a first surface energy. Then, the sidewall of the recess is treated so as to have a second surface energy lower than the first surface energy. For example, a layer or spacer having a low surface energy may be formed on the sidewall of the recess.

Yet another embodiment is a semiconductor imaging device. The device includes a substrate having an upper surface. The substrate includes a recess formed into the upper surface. The recess includes a bottom and a sidewall. The device also includes a sidewall spacer formed on the sidewall of the recess. The device further includes an array of color filters formed on the bottom of the recess.