Apparatuses for configuring programmable logic devices from BIOS PROM

An apparatus comprising programmable logic devices including a field programmable gate array (FPGA) is presented. In one embodiment, the apparatus also comprises a programmable read only memory (PROM) to store a firmware which includes at least a system boot code and a configuration code. The apparatus further includes a configuration agent to configure the FPGA by using the configuration code and to release the reset to the CPU after the FPGA is configured. In one embodiment, the configuration agent comprises a SPI-FPGA bridge (serial peripheral interface to FPGA configuration interface). In one embodiment, the configuration agent is operable to determine whether the FPGA is ready for configuration based at least on a status from the FPGA.

FIELD OF THE INVENTION

Embodiments of the invention relate to configuring programmable logic devices in a computing system.

BACKGROUND OF THE INVENTION

Modern computer-based multimedia applications, such as video, graphics and audio processing, may include computationally intensive data processing. The processing burden may be distributed among other devices, such as, programmable logic devices coupled to a computing system.

Typically, after a system reset, programmable logic devices have to be configured before they can be utilized in the system. Vendor-specific configuration read-only memory (PROMs) may be required to configure/program the programmable logic devices, for example, field programmable gate arrays (FPGAs). For example, manufacturers of FPGAs produce and sell configuration PROMs which are designed specifically for programming the FPGAs. The cost of these PROMs has become another burden to many computer system manufacturers who use FPGAs in their products.

DETAILED DESCRIPTION OF THE INVENTION

An apparatus comprising programmable logic devices including a field programmable gate array (FPGA) is presented. In one embodiment, the apparatus also comprises a programmable read only memory (PROM) to store a firmware which includes at least a system boot code and a configuration code. The apparatus further includes a configuration agent to configure the FPGA by using the configuration code and to release the reset to the CPU after the FPGA is configured. In one embodiment, the configuration agent comprises a SPI-FPGA bridge (serial peripheral interface to FPGA configuration interface). In one embodiment, the configuration agent is operable to determine whether the FPGA is ready for configuration based at least on a status from the FPGA. In one embodiment, the configuration agent is operable to release the reset to the CPU after one or more FPGAs are configured.

The method and apparatus described herein are for configuring programmable logic devices. Specifically, the method and apparatus for configuring programmable logic devices are primarily discussed in reference to multi-core processor computer systems. However, the method and the apparatus for configuring programmable logic devices are not so limited, as they may be implemented on or in association with any integrated circuit device or system, such as cell phones, personal digital assistants, embedded controllers, mobile platforms, desktop platforms, and server platforms, as well as in conjunction with other resources.

Overview

An apparatus comprising programmable logic devices including a field programmable gate array (FPGA) is presented. In one embodiment, the apparatus also comprises a programmable read only memory (PROM) to store a firmware which includes at least a system boot code and a configuration code. The apparatus further includes a configuration agent to configure the FPGA by using the configuration code and to release the reset to the CPU after the FPGA is configured. In one embodiment, the configuration agent comprises a SPI-FPGA bridge (serial peripheral interface to FPGA configuration interface). In one embodiment, the configuration agent is operable to determine whether the FPGA is ready for configuration based at least on a status from the FPGA. In one embodiment, the configuration agent is operable to release the reset to the CPU after one or more FPGAs are configured.

FIG. 1is a block diagram of a system to configure programmable logic devices in accordance with one embodiment of the invention. Many related components such as buses and peripherals have not been shown to avoid obscuring the invention. Referring toFIG. 1, in one embodiment, the system includes programmable read only memory101(PROM101), serial peripheral interface bridge130(SPI bridge130), field programmable gate array152, and processor162.

In one embodiment, the aforementioned units are shown as discrete components. Other embodiments are possible where some or all of units are integrated within a device or within other components. In other embodiments, the aforementioned units are distributed throughout a system in hardware, software, or some combination thereof.

In one embodiment, PROM101stores a firmware thereon which includes at least BIOS102(basic input/output system) and FPGA configuration code103. In one embodiment, BIOS102is a system boot code which is used by the system to prepare the pre-boot environment so that an operating system can take over the system boot. In one embodiment, BIOS102and FPGA configuration103are accessible at different addresses (e.g., 0x00—000, 0x90—0000).

In one embodiment, the system boot code comprises basic input/output system (BIOS) modules or unified extensible firmware interface (UEFI) modules to prepare a pre-boot environment for an operating system.

In one embodiment, PROM101is also referred to as a SPI PROM as PROM101is operable to communicate with SPI bridge130via an SPI interface (i.e., SPI111).

In one embodiment, SPI bridge130is implemented by using a CPLD (complex programmable logic device). In other embodiments SPI bridge130is implemented using programmable logic devices (FPGA, CPLD, etc.), application specific integrated circuits, custom logic circuits, or any combinations thereof. In one embodiment, SPI bridge130includes multiplexer133(switch) and SPI-FPGA bridge131. SPI-FPGA bridge131is a bridge of a serial peripheral interface to a FPGA configuration interface. In one embodiment, SPI bridge130is coupled to processor162via SPI pass-through161.

In one embodiment, SPI-FPGA bridge131includes state machine (SPI)141, SPI master142, state machine (FPGA)145, and FPGA configuration master146. In one embodiment, SPI-FPGA bridge131is coupled to FPGA152via FPGA configuration interface151.

In one embodiment, when a system powers-up (or after a system reset), SPI bridge130determines the status of FPGA152, for example by detecting whether a status pin of FPGA152is asserted or otherwise. For example, in one embodiment, a status pin of FPGA152is asserted if FPGA152is prepared/ready for the configuration process.

In one embodiment, SPI bridge130reads configuration data (e.g., FPGA configuration code103) from PROM101and configures FPGA152using the FPGA configuration code103.

In one embodiment, PROM101is coupled to SPI bridge130(e.g., implemented using a small CPLD). In one embodiment, SPI bridge130is set in between processor162and PROM101such that PROM101is not directly coupled to processor162.

In one embodiment, FPGA152or any FPGAs to be configured is coupled to SPI bridge130, particularly SPI-FPGA bridge131.

In one embodiment, SPI bridge130holds the processor at reset while SPI bridge130reads FPGA configuration file103from PROM101. In one embodiment, SPI bridge130configures FPGA152in the system in conjunction with SPI-FPGA bridge131.

In one embodiment, state machine (SPI)141and SPI master142manage SPI operations and communications. In one embodiment, SPI Master142is able to communicate with FPGA configuration master146. In one embodiment, SPI master142sends/propagates data (e.g., FPGA configuration code103) to FPGA configuration master146for the purpose of configuring FPGA152. In one embodiment, FPGA configuration master146manages the process to configure FPGA152(and other programmable logic devices) in conjunction with state machine (FPGA)145.

In one embodiment, SPI bridge130halts the reset to processor162while configuring FPGA152. In one embodiment, after all FPGAs are configured, SPI bridge130releases the reset to processor162. SPI bridge130also provides a pass-through path for processor162to access PROM101after the configurations of FPGAs are complete. For example, SPI bridge130switches a multiplexer (i.e., multiplexer133) to create a pass-through path for processor162to access the system boot code after the reset has been released.

In one embodiment, processor162reads BIOS102stored in PROM101to configure input/output devices of a system and to prepare a pre-boot environment for an operating system.

In one embodiment, the cost of storing FPGA configuration code103on PROM101is lower than storing the code on a vendor specific configuration PROM. In one embodiment, a system allows co-location of the FPGA code and the BIOS code in a same non-volatile memory device. In one embodiment, a system uses the BIOS update utility to update the FPGA code, the BIOS image, or both concurrently.

In one embodiment, a BIOS code and a FPGA code are combined into a firmware (a firmware image) as a single integrated software release. In one embodiment, SPI bridge130enables updating a FPGA code without requiring a special JTAG cable from a FPGA vendor. As such, a JTAG interface specific to the FPGA vendor is also not required. In one embodiment, an FPGA image may be updated even if a user does not have direct access to the hardware. A user is able to update the FPGA image by using the approach in BIOS update utilities.

In one embodiment, FPGA152is a programmable logic device. In one embodiment, one or more programmable logic devices are found in a system. The programmable logic devices may include one or more field programmable gate arrays (FPGAs), one or more complex programmable logic devices (CPLDs), or any combinations thereof. In one embodiment, FPGA152includes proprietary embedded FPGA cores.

In one embodiment, processor162is a central processing unit. In one embodiment, processor162includes an input/output controller hub, for example, a platform controller hub (PCH), which supports a number of high speed peripheral devices of various I/O protocols and standards. In one embodiment, the PCH is operable to support serial peripheral interfaces. Processor162retrieves data from SPI bridge130via the PCH.

In order to provide Original Equipment Manufacturers (OEMs) the flexibility, a platform controller hub may include given host controller(s) to support peripheral device(s) in conjunction with the respective protocol(s). In one embodiment, the PCH also supports various I/O devices including devices operating in conjunction with PCIe (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment) device, and USB (Universal Serial Bus). In one embodiment, a converged I/O replaces multiple connector types found on computers (e.g., a universal serial bus (USB) interface, an IEEE 1394 interface, Ethernet, eSATA, VGA, DVI, DisplayPort, and HDMI) with a single connector type.

FIG. 2is a flow diagram of one embodiment of a process to configure programmable logic devices. The process is performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as one that is run on a general purpose computer system or a dedicated machine), or a combination of both. In one embodiment, the process is performed in conjunction with an apparatus (e.g., SPI bridge130with respect toFIG. 1). In one embodiment, the process is performed by a computer system with respect toFIG. 3.

Referring toFIG. 2, in one embodiment, processing logic begin by receiving a system event (process block500), for example, a system reset event, a reboot event, or a system boot event to reboot a computing system.

In one embodiment, processing logic holds the system reset (to a CPU) temporarily so that processing logic is able to configure one or more FPGAs. For example, processing logic holds the CPU at reset temporarily so that all FPGAs are configured before the reset is released to the CPU.

In one embodiment, processing logic determines whether the one or more FPGAs are ready for configuration by detecting status pins of the FPGAs. In one embodiment, processing logic retrieves a configuration code associated with an FPGA (process block501). The configuration code is stored on a programmable read only memory (PROM) which contains a firmware including the configuration code and a system boot code.

In one embodiment, processing logic configures the FPGA using the configuration code (process block502). It will be appreciated by those skilled in the art that the configuration of one or more FPGAs may be performed concurrently or serially using a same configuration code or different configuration codes based on the system design.

In one embodiment, processing logic enables a pass-through interface between the PROM and the CPU, such that the CPU is able to access a system boot code (process block504). For example, processing logic switches a multiplexer to create a pass-through path for the CPU to access the system boot code after the reset has been released.

In one embodiment, processing logic releases the system reset to the CPU to prepare a pre-boot environment for an operating system (process block505). In one embodiment, processing logic continues with a regular system boot sequence in accordance with the BIOS (process block506).

FIG. 3is a block diagram illustrating a computer system in accordance with one embodiment of the present invention. In one embodiment, the computer system includes processor305, memory/graphics controller308, platform controller hub309, main memory315, and non-volatile memory360. In one embodiment, processor305accesses data from level 1 (L1) cache memory306, level 2 (L2) cache memory310, and main memory315. In one embodiment, processor305is coupled to memory/graphics controller308. Memory/graphics controller308is coupled to platform controller hub309, which in turn, coupled to solid state disk325, hard disk drive320, network interface330, and wireless interface340. In one embodiment, main memory315loads operating system350.

In one embodiment, processor305comprises core301, core302, cache memory303, and cache memory306. In one embodiment, cache memory303is a private cache of core301, whereas cache memory306is a private cache of core302.

In one embodiment, main memory315may be implemented in various memory sources, such as dynamic random-access memory (DRAM), hard disk drive (HDD)320, solid state disk325based on NVRAM technology, or a memory source located remotely from a computer system via network interface330or via wireless interface340containing various storage devices and technologies. The cache memory may be located either within the processor or in close proximity to the processor, such as on the processor's local bus307.

In one embodiment, non-volatile memory360is a system read only memory (ROM) or a non-volatile memory device. In one embodiment, non-volatile memory360is not directly coupled to platform controller hub309. In one embodiment, a configuration agent is operable to configure one or more programmable logic devices of the system (not shown) using codes stored in non-volatile memory360.

In one embodiment, platform controller hub309includes one or more I/O host controllers that control one or more I/O interconnects (not shown). In one embodiment, platform controller hub309is coupled to processor305with a single link (i.e., interconnect or bus). In one embodiment, this coupling may be accomplished over a series of links. In one embodiment, processor305is coupled over a first link (e.g., local bus307) to memory/graphics controller308(where the memory complex interfaces with a memory subsystem), and memory/graphics controller308is coupled to platform controller hub309over a second link. In one embodiment, I/O interconnects are a combination of point-to-point interconnects and buses.

In many embodiments, at least one processor305is present. In one embodiment, multiple processor cores are present in the system (cores301-302). In one embodiment, multiple processors, each with single or multi-cores are present in the system (not shown). In embodiments where there are multiple cores and/or multiple processors in the system, a single master core is designated to perform boot and other such system handling processes in the system.

In one embodiment, processor305, cache memory306, memory/graphics controller308, and platform controller hub309are in a same package. In one embodiment, processor305, cache memory306, memory/graphics controller308, and platform controller hub309are on a same substrate. In one embodiment, processor305, cache memory306, memory/graphics controller308, and platform controller hub309are on a same substrate or in a same package.

Other embodiments of the invention, however, may exist in other circuits, logic units, or devices in conjunction with the system ofFIG. 3. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 3.

FIG. 4illustrates a point-to-point computer system for use with one embodiment of the invention.

FIG. 4, for example, illustrates a computer system that is arranged in a point-to-point (PtP) configuration. In particular,FIG. 4shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces.

The system ofFIG. 4may also include several processors, of which only two, processors870,880are shown for clarity. Processors870,880may each include a local memory controller hub (MCH)811,821to connect with memory850,851. Processors870,880may exchange data via a point-to-point (PtP) interface853using PtP interface circuits812,822. Processors870,880may each exchange data with a chipset890via individual PtP interfaces830,831using point to point interface circuits813,823,860,861. Chipset890may also exchange data with a high-performance graphics circuit852via a high-performance graphics interface862. Embodiments of the invention may be coupled to computer bus (834or835), or within chipset890, or coupled to data storage875, or coupled to memory850ofFIG. 4.

Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system ofFIG. 4. Furthermore, in other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 4.

The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLA), memory chips, network chips, or the like. Moreover, it should be appreciated that exemplary sizes/models/values/ranges may have been given, although embodiments of the present invention are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured.