There is disclosed a power supply stage, and a corresponding method, comprising: a plurality of amplifiers for amplifying an input signal, each amplifier receiving a power supply voltage; a common selection means for selecting one of a plurality of power supply voltages in dependence on a reference signal representing a desired power supply voltage; and a plurality of adjusting means, corresponding to the plurality of amplifiers, adapted to generate an adjusted selected power supply voltage for a respective amplifier tracking the reference signal in dependence on the one selected power supply voltage and the reference signal.

BACKGROUND TO THE INVENTION

1. Field of the Invention

The present invention relates to amplification stages for providing a modulated supply voltage, and particularly to such amplification stages organised to provide higher power than can be achieved in a single stage by using an arrangement known as a ‘corporate structure’ amplifier.

2. Description of the Related Art

It is known to provide a modulated power supply for providing a supply voltage to an amplification stage, such as a radio frequency (RF) amplification stage. An example of a particularly advantageous modulated power supply stage can be found in United Kingdom Patent No. 2398648.

In this advantageous modulated power supply stage there is provided an efficient technique for tracking the supply voltage to an RF amplifier in dependence on the RF input signal to be amplified by the amplifier. A first control loop tracks the envelope of the input signal, representing a desired supply voltage for the amplification stage, and selects one of a plurality of available supply voltages in dependence thereon. A second control loop tracks the envelope of the input signal and the actual output signal, and generates an error signal representing the difference there between. This error signal is combined with the selected supply voltage to provide an adjusted selected supply voltage for the amplification stage. The first control loop is a low frequency loop, and the second control loop is a high frequency loop.

Such an improved modulated supply stage offers significant advantages and improvements in delivering a highly accurate tracking (or tracked) power supply to an amplifier, with associated efficiency improvements.

It is also known, in amplifying signals such as RF signals, to split the input signal into portions, and then amplify each portion in a separate power amplifier, before recombining the amplified portions. The use of multiple power amplifiers to amplify a signal in this way enables a more powerful signal to be delivered than could otherwise be delivered. Typically such an amplified signal is delivered to an antenna of an RF transmitter.

Arrangements in which a signal is split in this way for amplification by multiple parallel amplifiers, before recombining, are known as ‘corporate structures’.

In the prior art highly accurate tracking power supply arrangement found in United Kingdom Patent No. 2398648, if the power supply stage is adapted for a corporate structure to deliver a power supply to n power amplifiers, then the power of each of the low frequency loop and the high frequency loop must be increased by a factor n. This has a negative effect on performance. The loops must be made physically larger. Layout problems may arise on the circuit board, with longer tracks needed to some power amplifiers. The maximum number of amplifiers which may be combined may also be restricted due to physical constraints of the power amplifiers on the feed network through which the modulated supply is delivered.

Alternatively a single modulated power supply may be provided for each single amplifier stage. This requires a large amount of replication of circuits. This adds to the cost and size of the implementations, and thus introduces of its own inefficiencies. In this arrangement, to achieve the benefits of an efficient, highly accurate tracking power supply for each single amplifier requires a high component count and associated cost.

As noted above, in a corporate structure with n amplifiers and n associated modulated supplies, regardless of the specific modulated supply implementations, disadvantages of performance, cost and size may be encountered.

It is an aim of the invention to provide a technique to enable some or all of the benefits of high accuracy tracking power supplies to be obtained in arrangements in which multiple power amplifiers are implemented in parallel.

SUMMARY OF THE INVENTION

In accordance with the invention there is provided a power supply stage, comprising: a plurality of amplifiers for amplifying an input signal, each amplifier receiving a power supply voltage; a common selection means for selecting one of a plurality of power supply voltages in dependence on a reference signal representing a desired power supply voltage; and a plurality of adjusting means, corresponding to the plurality of amplifiers, adapted to generate an adjusted selected power supply voltage for a respective amplifier tracking the reference signal in dependence on the one selected power supply voltage and the reference signal.

The common selection means may be a switched voltage supply. The plurality of adjusting means may each comprise an error correction means. Each adjusting means may be adapted to receive the adjusted selected power supply and compare it with the reference signal, to thereby generate an error signal to be added to the selected power supply voltage.

The power supply stage may further comprise means for providing the reference signal to each adjusting means, which means may provide a plurality of copies of the reference signal for the respective adjusting means.

The power supply stage may further comprise a plurality of said common selection means each associated with a plurality of amplifiers and a plurality of adjusting means.

The power supply stage may further comprise: means for distributing the reference signal to the plurality of common selection means; means for distributing the reference signal to the plurality of adjusting means associated with each common selection means; and means for distributing the reference signal distributed to each plurality of adjusting means to the individual adjusting means.

The power supply stage may further comprise means for controlling the timing of the reference signal at each of the adjusting means such that the adjusted supply voltage for each amplifier is time-aligned to the signal being carried by each amplifier. The signal being carried by each amplifier refers to the signal which each amplifier is amplifying, i.e. it's input signal. The signal being carried by each amplifier is, in a preferred embodiment, a radio frequency (RF) signal, each amplifier being an RF amplifier.

The means may be adapted to further control the timing of the reference signal at the common selection means.

In accordance with the invention there is further provided a method for providing a power supply voltage to each of a plurality of amplifiers arranged to amplify an input signal, comprising: selecting one of a plurality of power supply voltages in dependence on a reference signal representing a desired power supply voltage; and generating a plurality of adjusted selected power supply voltages for the respective plurality of amplifiers, each tracking the reference signal in dependence on the one selected power supply voltage and the reference signal.

The step of generating a plurality of adjusted selected power supply voltages may comprise receiving the adjusted selected power supply and comparing it with the reference signal, and in dependence thereon generating an error signal to be added to the selected power supply voltage.

The method may further comprise providing a plurality of copies of the reference signal for generating a plurality of adjusted selected power supply voltages.

The method may further comprise a plurality of said selecting one of a plurality of power supply voltages steps, and an associated plurality of generating a plurality of adjusted selected power supply voltages steps.

The method may further comprise: distributing the reference signal for the plurality of selecting step; distributing the reference signal for the plurality of generating steps associated with each selecting step; and distributing the reference signal distributed to each plurality of generating steps to the individual generating steps.

The method may further comprise controlling the timing of the reference signal for each of the adjusting steps such that the adjusted supply voltage for each amplifier is time-aligned to the input signal for each amplifier.

An advantage of the invention is that cost and space savings are achieved by separating out the two control loops. The low frequency control loop, which is relatively slow, is separated out from the high frequency control loop. The low frequency control loop is provided as a common control loop for a set of amplifiers. The common control loop can be adapted to be high-powered, to deliver an output to multiple amplifiers, without suffering a loss of performance. An individual high frequency loop is provided for each amplifier of the set. The provision of an individual high frequency loop for each amplifier allows the high accuracy benefits provided by advantageous arrangements to be substantially maintained, without incurring significant overheads in consuming space and an increased component count by replicating circuitry.

DESCRIPTION OF PREFERRED EMBODIMENTS

The invention is now described below by way of example with reference to non-limiting embodiments.

FIG. 1illustrates an exemplary dual-loop control system in accordance with the principles set out in United Kingdom Patent No. 2398648. United Kingdom Patent No. 2398648 is incorporated herein by reference. A difference block102and a low frequency amplifier104define a first path130. The first path may also be referred to as a first control path, or a main path. A difference block106and a high frequency amplifier108define a second path132. The second path may also be referred to as a second control path or an error correction path. In general, the second path removes an error from the first path, as will be understood from the following description.

A summer or combiner110is provided to combine the two control paths. The objective of the control system is to provide on an output line120a signal which is an accurate replica of an input signal provided on line112. The control system preferably provides an output signal on line120having a much larger current available than is associated with the input signal on line112. Such a system may be advantageously used as a high efficiency modulated or tracking power supply, with a load connected to the output signal line120.

The input signal on line112provides a first input to the difference block102. The difference block102forms an output on line114to the low frequency amplifier104. The output of the low frequency amplifier104on line116forms a first input to the combiner110, and is also fed back to form a second input to the difference block102on line118via a scaling block150.

The input signal on line112provides a first input to the difference block106on line129via a delay block131. The difference block106forms an output on line124to provide an input to the high frequency amplifier108. The high frequency amplifier108provides an output on line126which forms a second input to the combiner110. The combiner110combines the signals on lines116and126to form the output signal on line120. The output signal on line120is fed back to form the second input to the difference block106on line122via a scaling block152.

In an example application where the input signal on line112is an envelope derived from a RF signal to be amplified, the signal has a wide frequency spectrum compared to the operating frequency bandwidth of the low frequency amplifier104. In this system the low frequency amplifier104provides a large portion of the output power delivered on the output signal line120, but is incapable of operating at the higher frequency range of the input signal. The high frequency amplifier108effectively operates as an error correcting or clean-up loop to provide the missing part of the output signal on line120. The error correction or clean-up is provided by summing the signal on line126with the signal on line116to deliver a desired output signal on line120.

In the arrangement ofFIG. 1, the high frequency amplifier108must be able to operate over almost the full frequency range of the input signal. This creates demands on the dynamic range and fractional bandwidth of the high frequency amplifier108, and particularly creates demands on the design of the combiner110which must be capable of operating at a very high fractional bandwidth.

To mitigate these problems, the delay block131is preferably provided in accordance with the principles discussed in United Kingdom patent application number 0803711.1.

The provision of the delay block131reduces the low frequency content of the signal provided to the high frequency amplifier108as described further below.

The delay block131introduces a delay into the second control path equivalent to the delay through the first control path. In the arrangement ofFIG. 1a finite delay is introduced by the control loop130. The delay block131of the arrangement ofFIG. 2operates as a balancing delay, delaying the signal applied to the first input of the difference block106by an amount corresponding to the delay of the first control loop130, which delay is present in the signal delivered to the second input of the difference block106on line122. The balancing delay afforded by the delay block131is preferably substantially constant with frequency.

Thus the provision of the delay block131ensures that the difference block106provides an output on line124which has reduced low frequency signals.

The cancellation of the low frequency signals in this way means that the high frequency amplifier108is not required to amplify those signals, and the combiner110is not required to handle those signals on the input line126. Thus the removal of the low frequency content in this way allows for signal coupling in the combiner110using, for example, a transformer or a capacitor. The use of a transformer for the combiner110is a particularly advantageous, and preferable, arrangement.

Preferably the delay provided by the delay block131is a digital delay. A digital delay is preferable as this provides a constant delay at all frequencies. A digital delay is particularly appropriate where the input signal is in digital form. The invention, and embodiments thereof, are not limited to digital delays. The delay can be implemented as an analogue network.

With reference toFIG. 2, there is now illustrated schematically an exemplary dual-loop control system for a multi-stage amplifier arrangement in accordance with the principles of the invention, which utilises the principles of the preferred dual-loop control system ofFIG. 1.

It should be noted that for ease of illustration, in the following Figures the scaling blocks150and152ofFIG. 1are not illustrated. One skilled in the art will appreciate, however, that such scaling blocks may preferably be provided.

Referring toFIG. 2, the multi-stage amplifier arrangement is generally denoted by reference numeral210, and includes a plurality n of RF amplifiers. InFIG. 2there is illustrated a first RF amplifier2021, a second RF amplifier2022, and an nthRF amplifier202n. The respective RF amplifiers2021to202nreceive an input signal on a respective input2041to204nand generate an output signal on a respective output2061to206n. Each of the amplifiers2021to202nof the multi-stage amplifier arrangement210receives equivalent input signals on their respective inputs2041to204n. The input signals may be provided by a splitter stage. The output signals on outputs2061to206nmay be combined in a subsequent combiner stage.

Each RF amplifier receives, in accordance with the principles of the present invention, a modulated power supply voltage on a respective power supply line1201to120n. In the example illustrated, the RF amplifiers2021to202nare further connected to ground.

In accordance with the principles of the present invention, the multi-stage amplifier arrangement210is provided with a single low frequency amplification stage, and n high frequency amplification stages. The single low frequency amplification stage is denoted by reference numeral234, and comprises the low frequency amplification stage130ofFIG. 1together with the delay stage131ofFIG. 1. Thus the delay stage131ofFIG. 1is additionally provided as a single, common stage for the multi-stage amplifier arrangement210.

Although referred to as the low frequency amplification stage, it will be appreciated that the stage234includes the delay131which is not associated with the low frequency amplification. The stage234is in general a common stage for the multi-stage amplifier arrangement, but is referred to herein as the low frequency amplification stage in view of its main functional purpose.

As illustrated inFIG. 2, the low frequency amplifier104is a switched voltage stage. The switched voltage stage receives, in the illustrated example, four supply voltages V1to V4. One of the supply voltages V1to V4is selected for output on line116in dependence on the magnitude of the input signal from the difference block102. Such switched supply voltage stages are known in the art, and for example are described in GB Patent No. 2398648.

As illustrated inFIG. 2, for the multi-stage amplifier arrangement210a plurality n of high frequency amplification stages denoted by reference numerals2321to232nare provided. Each of the high frequency amplification stage2321to232ncorrespond to the high frequency amplification stage132ofFIG. 1. In addition each of the high frequency amplification stages2321to232nincludes a combiner equivalent to the combiner110ofFIG. 1.

Although referred to as high frequency amplification stages, it will be appreciated that the stages2321to232ninclude the combiners1101to110nwhich are associated also with the low frequency amplifications outputs. The stages2321to232nare in general dedicated stages for the multi-stage amplifier arrangement, but are referred to herein as high frequency amplification stages in view of their main functional purpose.

As illustrated inFIG. 2, the common low frequency amplification stage234receives the input reference signal on line112. The common low frequency amplification stage234provides the output signal on line116in accordance with the arrangement ofFIG. 1.

Each of the high frequency amplification stages2321to232nreceive two inputs, being the output on line116of the low frequency amplification stage234, and the output on line129which is the delayed version of the input reference signal. As noted above, each of the high frequency amplification stages2321to232ngenerates a respective modulated supply voltage on lines1201to120nin dependence on the signals on lines116and129.

Each of the high frequency amplification stages2321to232nincludes a difference block1061to106nrespectively corresponding to the difference block106ofFIG. 1, and a high frequency amplifier denoted1081to108nrespectively corresponding to the high frequency amplifier108ofFIG. 1. In addition each of the high frequency amplification stages includes a respective combiner denoted1101to110n, corresponding to the combiner110ofFIG. 1. The interconnection of the difference blocks, high frequency amplifiers, and combiners of the high frequency amplification stages2321to232nis the same as that as illustrated inFIG. 1.

The low frequency amplification stage234operates in combination with each of the high frequency amplification stages2321to232nto provide the same functional effect asFIG. 1, to provide a modulated power supply voltage on the respective lines1201to120nfor the respective individual RF amplifiers.

Thus in accordance with the principles of the invention, as set out with reference toFIG. 2, a single low frequency amplification stage in combination with multiple high frequency amplification stages allows the advantages of a highly accurate tracking system such as illustrated inFIG. 1to be maintained in a corporate structure.

The single low frequency amplification stage234can be made appropriately high powered for delivering signals to multiple low frequency amplification stages. No disadvantage is involved in this, since the low frequency amplification stage is in any event a low-speed stage, due to its characteristics as a switched voltage stage.

However, by separating out the high frequency amplification stages, they may be maintained as small-sized and fast stages, which allows the advantages of high efficiency, highly accurate tracking to be maintained.

With reference toFIG. 3, there is now illustrated a preferred implementation of the high frequency amplification stage ofFIG. 2, in accordance with the principles of UK patent application no. 0803821.8. The described preferred implementation is a transformer based power supply which is used for modulating the power supplied to a plurality of power amplifiers in an envelope tracking system.

Each of the high frequency stages2321to232nis implemented in the same way.

With reference toFIG. 3, a filtered output from the low frequency stage234on line116is coupled to a first tap403nof a secondary winding410nof a transformer404nvia a resistor418nand capacitor416nconnected in parallel. A second tap405nof the secondary winding410nis coupled to the amplifier202non output line120n.

A bypass inductor420nhas first and second terminals, the first terminal being coupled to the first tap403nof the secondary winding410n, and the second terminal being coupled to the second tap405nof the secondary winding410nvia a resistor440nrepresenting the resistance of the inductor420n. The illustration of the resistor440nis for the purposes of later discussion.

The delayed version of the input reference signal on line129is coupled to a first input of a subtractor412n, the subtractor412nhaving a second input coupled to the second tap405nof the secondary winding410n. The output of the subtractor412nis coupled to the input of a correction amplifier406n. The output of correction amplifier406nis coupled to the first tap407nof the primary winding408nof the transformer404n. The second tap409nof the primary winding408nis coupled to ground.

In overview, the voltage on line116is applied to the first tap403nof the secondary winding and the first terminal of the bypass inductor420n. The subtractor412nreceives the delayed version of the input reference signal and subtracts the value of the voltage present at the second tap405nof the secondary winding110, i.e. the output voltage, to produce a voltage error signal. This voltage error signal is then amplified in the correction amplifier406nand applied to the first tap407nof the primary winding408n. The voltage on line116and the voltage provided by the correction amplifier408nare then combined by the transformer404nto provide a corrected voltage output at the second tap405nof the secondary winding410being the output voltage.

In the arrangement ofFIG. 3, the low frequency (switched), or coarse, voltage signal on line116is applied to the secondary winding410nof the transformer, and may cause a significant DC current to flow in the secondary winding. This DC current may generate a significant magnetic flux in the transformer core, and may lead to magnetic saturation of the core.

In order to address this problem, the amplification stage232nis preferably provided with the bypass inductor420n. The bypass inductor420npreferably comprises a high power inductor and therefore presents a high impedance to high frequency signals, but a very low impedance to DC current and low frequency signals. Therefore, the bypass inductor presents a low impedance DC current bypass path around the transformer, and a large proportion of the DC current on line116will flow through the bypass inductor and not through the transformer. The flux in the transformer core due to the DC current flowing through the transformer windings will be reduced as less DC current flows through the secondary winding. Thus, the susceptibility of the core to magnetic saturation is reduced. This allows a physically smaller transformer, compared with the transformer that would otherwise be required. This is advantageous as a smaller transformer may have an improved high frequency response.

Each amplification stage2321to232nmay thus be implemented using a transformer as a combiner, but with a reduced size.

The purpose of the capacitor416nand the resistor418n, is to further provide for the desirable flow of DC current in the bypass inductor.

Bypass inductor420nhas an associated resistance value, RL, due to the length of wire in the inductor coil, represented by resistor440n. This resistance value RLis normally small. The resistor418nis preferably chosen to have a resistance value Rtransthat is greater than RL, preferably much greater. Therefore, DC current output on line116will flow preferentially through the low resistance path provided by bypass inductor420n, with its inherent low resistance, RL. The ratio of Rtransto RLthen determines the reduction in DC current flowing in the transformer secondary410n.

The resistor418nthus advantageously provides a means for directing additional current through the bypass path rather than through the transformer.

The capacitor416nprovides a low impedance path for AC current flow through the secondary winding410nof the transformer404n. By providing a low impedance path for AC currents, excessive dissipation of high frequency signals in resistor418nmay be avoided.

In the advantageous arrangement ofFIG. 3, as the flux in the transformer is further reduced, the transformer itself may be further reduced in size whilst avoiding magnetic saturation of the core.

The presence of bypass inductor420nin the amplification stages2321to232nmay provide still further benefits.

Assuming a lossless transformer, the average power delivered on line120nto the amplifier202nis the combination of the average power delivered by (i) a switchable main voltage source of the low frequency amplifier104and (ii) the correction amplifier406n. However, the instantaneous power delivered to the amplifier202nmay not be equal to the sum of the instantaneous power delivered by (i) and (ii). This is because energy is stored in the bypass inductor420nand in the transformer magnetising inductance (not shown) and this energy may be released during periods of high instantaneous output power.

The majority of the power being delivered to the amplifier202nat any one point in time is provided by the low frequency amplifier104. However, during peaks in output power, a significant amount of power is provided by the bypass inductor420n.

The net average power output of the (ideal) bypass inductor must be zero, in order for energy to be conserved. The inductor420nis ‘charged’ during periods of low instantaneous output power, and releases the stored-energy during periods of high instantaneous output power. Advantageously, this significantly reduces the peak power requirement of the correction amplifier406n.

Energy which would otherwise be stored in the magnetising inductance of the transformer404nis instead stored in a physically separate inductor420n, which unlike the transformer404n, does not need to be optimised for high frequency operation. The stored energy may then be delivered to the amplifier202nduring periods of high instantaneous output power, thereby reducing the peak power requirement of the correction amplifier406n.

With reference toFIG. 4, there is illustrated the implementation detail of the amplification stage210ofFIG. 2in a corporate structure. The modified amplification stage210ofFIG. 2is denoted by reference numeral460inFIG. 4. Reference numerals used earlier in the application are reused inFIG. 4where like elements are illustrated.

As illustrated inFIG. 4, the delayed version of the reference signal is delivered on a line532, common to the amplification arrangement460. The delayed version of the reference signal on line532is provided as an input to a splitter stage512, comprising a plurality of n buffers5141to514n. Each of the n buffers5141to514nreceive the delayed version of the reference signal on a line532, and generate a copy of that signal on their respective output lines5151to515n. The copies of the delayed version of the reference signal on lines5151to515nprovide the first inputs of the difference blocks1061to106nofFIG. 2of the high frequency amplification stages2321to232n. Thus the signal on line129shown inFIG. 2is replaced by n versions of that signal on lines5151to515n.

The arrangement ofFIG. 4is preferred in a corporate structure, where it is necessary to distribute the reference signal not only to one or more low frequency amplification stages, but to one or more sets of high frequency amplification stages. Due to the distribution of the reference signal in a hierarchical manner in a corporate structure it is necessary to split and then buffer the signal in order to ensure it is delivered to each amplification stage104or232at an appropriate level.

With reference toFIG. 5, there is illustrated an overall schematic of the distribution of the reference signal in a corporate structure containing a plurality m of amplification stages corresponding to the amplification stage460ofFIG. 4.

Turning now toFIG. 5, there is illustrated schematically an implementation of a large corporate structure architecture, comprising multiple amplifiers. In the example ofFIG. 5, there is disclosed a plurality m of groups of n amplifiers. n may vary for each group. One of the m group of n amplifiers is preferably arranged as illustrated inFIG. 4.

Each group of n corresponds, in structure, to the amplification stage ofFIG. 4. Thus there is shown m amplification arrangements4601to460m, each corresponding to the arrangement460ofFIG. 4.

The number of amplifiers n, and consequently the number of high frequency amplification stages n, in each of the stages4601to460nmay vary.

In general, with reference toFIG. 5, the reference signal on line112is provided as an input, and may be denoted the master reference signal, REFMAS. The reference signal on line112forms an input to a digital-to-analogue converter524to provide a digitised version of the analogue reference signal. The digitised version of the reference signal of the output of the digital-to-analogue converter may be considered to be the digitised master reference signal for the low frequency amplification stages, denoted REFLF—MAS, and provides an input to a low frequency splitter/buffer stage516.

The reference signal on line112additionally forms an input to a delay528, which is equivalent to the delay131ofFIGS. 1 and 2. The delayed reference signal at the output of the delay528forms an input to a digital-to-analogue converter526, which generates at its output an analogue version of the delayed reference signal, which may be considered to be the analogue master reference signal for the high frequency amplification stages, denoted REFHF—MAS. The reference signal REFHF—MASat the output of the digital-to-analogue converter526forms an input to a high frequency splitter/buffer stage518.

The low frequency splitter/buffer stage516provides a slave reference signal for the low frequency amplification stages of each of the stages4601to460m, denoted REFLF—SL1to REFLF—SLm.

The high frequency splitter/buffer stage518provides a slave reference signal for the high frequency amplification stages of each of the multi-stage amplification stages5101to510m, denoted by REFHF—SL1to REFHF—SLm.

The low frequency splitter/buffer stage516comprises a plurality m of buffers denoted5201to520m. Each buffer respectively provides an output signal on line5301to530mwhich provides the reference signal REFLF—SL1to REFLF—SLmfor the low frequency amplification stages of the respective amplification stages5101to510m.

The high frequency splitter/buffer518comprises a plurality m of buffers denoted5221to522m. The buffers5221to522mgenerate output signals on respective output lines5321to532m, which respectively provide the high frequency reference signals REFHF—SL1to REFHF—SLmfor each of the amplification stages4601to460m.

Each of the high frequency reference signals received on lines5321to532mby the amplification stages4601to460mis received at a respective buffer stage5121to512m. In amplification stages4601to4603ofFIG. 5, as can be seen with further reference toFIG. 4, there is generated for each of the n slave reference signals for the high frequency amplification signals on lines532sub-slave signals REFHF—SUB—SL1to REFHF—SUB—SLn.

The number of amplifiers n provided in any amplification stage460mmay be dependent upon the number of times the high frequency reference signal can be replicated by any given buffer stage512. This limitation may require the hierarchical generation of the high frequency reference voltage, such as illustrated inFIG. 5where an initial split of the high frequency amplification signal takes place in block518, and a subsequent split takes place in blocks512.

The factors most likely to drive this, however, are space within an amplifier rack, or a conveniently achievable power from the low frequency switched supply, which determines the number of amplifiers an individual low frequency switched supply can support.

Thus as is illustrated inFIG. 5, the advantageous structure for a multi-stage RF amplification stage as illustrated inFIG. 4may be replicated a number of times. If the number of high frequency amplification stages232nreaches a maximum, due to performance limitations, then the overall amplification stage460ofFIG. 4can be replicated as denoted inFIG. 5.

In implementing the principles of the present invention, with a distributed arrangement for the implementation of the high frequency amplification stages, it is necessary to ensure that the timing between the various high frequency amplification stages is controlled, such that synchronisation exists between the application of the signals and that in a subsequent combining stage the signals are combined with time synchronicity.

It is a requirement to (a) accurately align the RF envelope and drain voltage (supply) signals for each amplifier stage used and (b) accurately time-align all power amplifier stages within the corporate structure amplifier.

This is now further discussed with reference toFIG. 6.

FIG. 6illustrates in overall schematic the distribution of the high frequency amplification stages of the envelope path of a corporate structure envelope tracking amplifier. InFIG. 6the input reference signal is received on a line718. This forms an input to a generation and conversion block702. This block represents the processing of the input reference signal in order to convert it from digital-to-analogue form, and to generate the “master” high frequency reference voltage. This also includes the application of any appropriate delay in the envelope path (corresponding to the delay of block131inFIG. 1).

It is also necessary to delay the RF path correspondingly to achieve alignment between the RF envelope and drain (supply) voltage on all power amplifier stages.

Thereafter the “master” version of the high frequency reference signal is delivered to a splitter704, which is equivalent to the splitter/combiner518ofFIG. 5. In general, the splitter704operates to output m copies of the master high frequency voltage signal, which are “slave” high frequency reference signals, each of which forms an input to a respective further splitter/buffer7061to706m, which correspond to the splitter/buffer stages5121to512mof FIG.5. Thereafter, each of the splitter stages7061to706mgenerates an appropriate number of copies n, which are “sub-slave” high frequency reference signals for the high frequency amplification stages in a multi-stage amplifier. Thus, for example, the splitter stage706mgenerates n copies of the high frequency reference voltage which provides inputs to the high frequency amplification stage708m1to708mn. Similarly splitter7062provides copies of the high frequency reference voltage to high frequency amplification stage70821to7082n, and splitter7061provides copies of the high frequency voltage reference to high frequency amplification stage70811to7081n.

As shown inFIG. 6, each of the high frequency amplification stage708provides a modulated supply voltage to an associated RF amplifier, denoted by reference numerals70911to709mn. With reference toFIG. 2, this corresponds to the provision of the modulated supplies on lines120.

As noted hereinabove, it is important to ensure that the delivery of the reference signal, or copies of the reference signal, to the high frequency RF amplification stages708is time-aligned.

InFIG. 6, there is denoted between the various block elements time periods which represent time delays at various points. There is a time delay of t0associated with the generation and conversion block702. A further time delay of t1represents a delay caused by the transmission from the generation and conversion block702to the splitter704. There is a respective time delay between the splitter704and each of the splitters7061to706m, each of which time delays is denoted by the times t21, t22, and t2mrespectively. Further there is a time delay between each of the splitters7061to706m, and the respective amplifiers70811to7081n,70821to7082n, and708m1to708mn.

It will be appreciated by one skilled in the art that the number of RF amplifiers709and associated high frequency amplification stages708is such that additional hierarchical generation of the high frequency voltages may be required, and there may be additional stages incurring time delays.FIG. 6is merely representative of the principle of the delivery of the high frequency reference signal from a master version of such through to the individual high frequency amplification stages of the multi-stage environment. There may be more or less splitting stages required, and thus more or less time delay paths.

In order to ensure time-alignment of the high frequency amplification stages, it is necessary to ensure that the time delay between the receipt of the reference signal on line718and the delivery of the copy of the reference signal to an individual high frequency amplification stage708are equal. Thus the time delay from the input of the generation and conversion block702to the input to any one of the high frequency amplification stages708associated with the amplifiers709must be equal. For example, this requires t0+t1+t21+t31nto be equal to t0+t1+t22+t222.

Further it is important that the envelope of the RF signal of each RF amplifier709is time-aligned with the modulated supply voltage provided by each high frequency amplification stage, such that there is time-alignment between the modulated supply provided to an amplifier and the RF signal being carried by the amplifier. It should be noted that the input signal to each amplifier709will be derived from a main input signal being split and distributed, in a similar manner to the reference signal for the high frequency amplification stages inFIG. 6.

It is preferable, though not essential, that the reference signal for any low frequency amplification stage be time-aligned with the high-frequency reference signals and the input signals. Such time-alignment is less critical as the high frequency amplification stage is adapted to remove any error in the signal generated by the low frequency amplification stage.

In order to meet the time-alignment requirements, it may be necessary to take appropriate action to ensure time periods are time-aligned by introducing delays such as by controlling the length of cables for delivering signals.

The described preferred embodiments utilising an RF amplifier are not limited to any particular load being driven by such RF amplifier. However it is envisaged that such an RF amplifier will typically drive an antenna. As such, the present invention has particular advantageous uses in the field of communications, including the field of mobile communications.

The present invention is described herein by way of reference to particular preferred embodiments, and particularly by way of reference to an application in a modulated voltage supply. This description is, however, only illustrative of examples. In particular the invention may be implemented more broadly in control systems. Envisaged, but not limiting, applications include dynamic power supplies or any wide frequency range power supply.