Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.

BACKGROUND

This disclosure relates generally to non-volatile memories (NVM), and more specifically, to NVMs that use a charge pump voltage in a word line driver/decoder.

2. Related Art

Non-volatile memory (NVM) such as electrically-erasable programmable read-only memory (EEPROM) and flash uses voltage levels that exceed the input power supply voltage for use during read, write, erase, and write verify operations. In the case where these elevated voltages are internally supplied, which is the typical case, they are most commonly generated by a charge pump. The more current that must be supplied, the larger the charge pump must be and thus require more area. Any area increase ultimately leads to a cost increase that may be due to actually increase in the cost of the die as well as increased packaging size that increases the cost of the package which in turn may increase cost in using the packaged die. Accordingly it is desirable to have circuits that draw as little current as possible from the charge pump. Although for other reasons, such as battery drain, it is common to design for low current, the particular effect of circuits that use the charge pump voltage is particularly important in minimizing current drain.

Accordingly there is a need to improve upon reducing current drain on charge pumps in NVMs which are particularly dependent on charge pumps.

DETAILED DESCRIPTION

In one aspect a word line driver/decoder of a non-volatile memory (NVM) has a series decoder of N channel transistors between a select node and ground in which the select node is brought to a logic low by the N channel transistors all being conductive. Between a charge pump voltage and the select node is a conductive load that is prevented from being a leakage path from the charge pump voltage through the N channel transistors by applying a reference voltage, which may be an external power supply voltage, to the select node. This is better understood by reference to the drawings and the following description.

VB1is a voltage that limits the amount of current that P channel32may conduct to ensure that transistors38-42can pull nodes35and39to a logic low. VB2is a voltage that makes sure that devices below transistor34receive a voltage no greater than a safe voltage for low voltage transistors which means VB2equals VDD plus a threshold voltage of transistor34.

Shown inFIG. 1is a block diagram of a non-volatile memory (NVM) comprising a row pre-decoder12that receives a row address, a word line driver/decoder14coupled to the row pre-decoder and a word line WL0, a word line driver/decoder16coupled to row predecoder12and a word line WL1, a memory controller18coupled to row predecoder12and word line driver/decoders14and16that has an input/output shown as I/O, a charge pump19that is within memory controller18, column circuitry20coupled to memory controller18and that receives a column address, and an array22coupled to column circuitry20and word line driver/decoders14and16through word lines WL0and WL1, respectively.

In operation as directed by memory controller18, row decoder12receives a row address and provides predecoded signals to the word line driver/decoders such as word line driver/decoders14and16. The word line driver/decoder that is selected enables the word line to which it is coupled. The voltage applied to the selected word line is dependent upon the operation being performed, typically a read, program, or erase and may be further controlled within the performance of a program or erase operation. Voltages that are different from the voltage at the positive power supply terminal, VDD, are achieved by a charge pump19, which may include multiple pumps, within memory controller18. Column circuitry20provides biasing of the bit lines and the VS terminals, provides program data for programming, and performs sensing for reads. In a typical arrangement, array22would be one block of many blocks that make up a larger NVM storage than shown inFIG. 1. For example, for a memory having 8 megabytes, there may be 64 blocks such as array22in which only two would be active at any given time. In addition to memory controller18, including charge pump19, the particular elements shown inFIG. 1may be such that they are also used in one or more of the other blocks not shown inFIG. 1. For example portions of row predecoder12may be used by other blocks.

FIG. 2is a circuit diagram of word line driver/decoder14comprising a P channel transistor32, an N channel transistor34, an N channel transistor36, an N channel transistor38, an N channel transistor40, an N channel transistor42, a P channel transistor44, a P channel transistor46, an N channel transistor48, an N channel transistor50, and an N channel transistor52. Transistors32,34,46,48,50, and52are high voltage transistors. Transistors36,38,40,42, and44are low voltage transistors. High voltage transistors are able to withstand higher voltages than low voltage transistors, but they are not as fast and they require more space than low voltage transistors. In construction the high voltage transistors are made with a thicker gate dielectric so for a given current drive, they require significantly more channel width and thus more space. Voltage Vp is a voltage provided by charge pump19and is received at a node31. VDD is a terminal that carries a power supply voltage that is supplied by the external power supply that is external to the integrated circuit that includes memory10. The ground shown inFIG. 2is the other terminal of the external power supply that is negative relative to the voltage at VDD. Terminal N as shown inFIG. 2is for providing a negative voltage relative to ground, which is used based on various modes of operation including test and normal modes.

Transistor32has a source connected to node31, a gate that receives a bias voltage VB1, and a drain connected to a node35. Transistor34has a drain connected to node35, a gate that receives a bias voltage VB2, and a source. Transistor36has a drain connected to the source of transistor34, a gate connected to VDD, and a source connected to a node39. Transistor38has a drain connected to node39, a gate that receives a predecoded signal S0, and a source. Transistor40has a drain connected to the source of38, a gate that receives a predecoded signal S1, and a source. Transistor42has a drain connected to the source of transistor40, a gate that receives a predecoded signal S2, and a source connected to ground. Transistor46has a source connected to node31, a gate connected to node35, and a drain connected to word line WL0. Transistor48has a drain connected to word line WL0, a gate connected to node35, and a source. Transistor50has a drain connected to the source of transistor48, a gate that receives an enable signal EN, and a source connected to ground. Transistor52has a drain connected to the drain of transistor50, a gate that receives a test signal T, and a source connected to terminal N.

In operation, predecoded signals S0, S1, and S2are provided to transistors38,40, and42, respectively, from row predecoder12. When all of predecoded signals S0, S1, and S2are a logic high, word line driver/decoder14is selected. When any of signals S0, S1, and S2are a logic low, word line driver/decoder14is deselected. In a typical arrangement, there are many subarrays and all of signals S0, S1, and S2will be a logic low when array22is deselected. Thus when array22is not selected, signal S0will be a logic low which will cause transistor44to be conductive. With transistor44conductive, node39will be at the voltage at VDD, the power supply voltage. The power supply voltage is particularly convenient, but another reference could be generated and used to bias node39when array22is deselected. For the example of there being 64 subarrays, which may also be called blocks, nearly all would be deselected. The number deselected could easily all but one or two, depending upon the particular memory architecture chosen. In the case of array22being deselected, node39is clamped to the voltage at VDD to ensure that transistor36is non-conductive. With transistor36non-conductive, there is no leakage path from Vp to ground through the current path of transistors32,34,36,38,40, and42. Transistors36,38,40,42are low voltage transistors for speed and area, but by being low voltage transistors, leak significantly more current than high voltage transistors. Thus there is significant reduction in leakage from voltage Vp by blocking the path through transistors34,36,38,40, and42. Although there is still leakage through transistors38,40, and42, this current is drawn from the voltage at VDD rather than from charge pump19that supplies voltage Vp.

For the case when array22is a block that is selected, when node39is pulled to a logic low by predecoded signals S0, S1, and S2being a logic high, this is coupled through transistor36and transistor34to the gates of transistors46and48. When array22is a selected block, enable signal EN, derived from block select signals, is a logic high which causes transistor50to be conductive. With transistor50coupling the source of transistor48to ground, transistor46becomes conductive, and transistor48becomes non-conductive which causes word line WL0to switch to a logic high at the level of voltage Vp. This causes the memory cells along word line WL0to be able to be read, programmed, or erased based on the operation being performed. The voltage of the logic high is dependent on the level of voltage Vp which is dependent upon the operation in question, such as read, program, or erase. Also the level of voltage Vp can be different during an operation or even from one program operation to another such as from a regular program operation to a soft program operation.

VB1is a voltage that limits the amount of current that P channel32may conduct to ensure that transistors38,40, and42can pull nodes35and39to a logic low. VB2is a voltage that makes sure that transistors36,38,40, and42receive a voltage no greater than a safe voltage for low voltage transistors. An effective voltage for voltage VB2then is the voltage at VDD plus the threshold voltage of transistor34.

For the case of array22being a selected block but word line WL0being deselected and brought into effect with a logic low applied to word line WL0. Node39is at a logic high responsive to any one of transistors38,40, and42being non-conductive which occurs when at least one of predecoded signals S0, S1, or S2is a logic low. As stated previously, for the case of array22being a deselected block, then all three of predecoded signals S0, S1, and S2are a logic low for the duration of the deselection so that transistor44is ensured of being conductive as are all of the word line driver/decoders that drive the word lines of array22. On the other hand, for this case of array22being a selected block, then only when signal S0is a logic low is transistor44conductive and thus preventing leakage from charge pump19. Thus, when word line WL0is deselected due only to one or both of predecoded signals S1and S2being a logic low with predecoded signal S0being a logic high, there is a leakage path from voltage Vp supplied by charge pump19through transistors38,40, and42due to transistor44being non-conductive. A logic gate could be added to ensure that transistor44was active anytime word line WL0was deselected, but in light of the fact that the percentage of the blocks that are deselected at any given time is so high, the additional benefit in doing so is relatively small. With at least one of predecoded signals S0, S1, and S2being a logic low, node39is a logic high. The logic high at node39is coupled to node35through transistors34and36which are conductive. The logic high on node35makes transistor36non-conductive and enables node35to then be pulled to voltage Vp by transistor32. Voltage Vp at node35causes transistor46to be non-conductive and transistor48to be conductive. With transistor50being conductive, word line WL0is at a logic low, the deselected condition for word line WL0.

Thus, it is seen that a word line driver/decoder can use the benefits of low voltage transistors where they are most needed while avoiding having that leakage drawn from the elevated voltages that are beneficial for NVMs. The leakage still occurs, but the vast majority of that leakage is drawn from the external power supply instead of the elevated voltages which are typically generated on chip by charge pumps.

Shown inFIG. 3is a prior art word line driver/decoder100that does not have the leakage control of the word line driver/decoders of memory10. Word line driver/decoder100comprises high voltage P channel transistors106and114, N channel high voltage transistors108,116,118,120, and122, low voltage transistors110and112, and an inverter124comprised of low voltage transistors connected as shown. The functional operation is substantially the same as for word line driver/decoder14shown inFIG. 2in which, if the block is selected, word line WL is provided at a logic high if both predecoded inputs P01and P02are a logic high. Word line driver/decoder100receives only two predecoded signals from the row decoder. Transistor118, with a limit input LIM, limits current drawn from voltage VP provided by a charge pump.

By now it should be appreciated that in some embodiments, there has been provided a word line driver. The word line driver includes a first stack of transistors. The first stack includes a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals. The first stack further includes a cascode transistor having a first current electrode connected to the first node, the cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage. The first stack further includes a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the cascode transistor. The word line driver further includes a pull up transistor having a first current electrode coupled to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode coupled to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage. The word line driver further includes an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node. The word line driver has further characterizations by which the plurality of decode transistors are characterized as lower voltage transistors and the third transistor is characterized as a higher voltage transistor. The word line driver may have a further characterization by which wherein the source voltage terminal is connected to the third supply voltage terminal and supplies the third supply voltage. The word line driver may have a further characterization by which the output of the inverting circuit is coupled to a word line. The word line driver may have a further characterization by which the decode transistors and the cascode transistor are characterized as N-channel transistors and the pull up transistor and the third transistor are characterized as P-channel transistors. The word line driver may have a further characterization by which during operation, the first node operates at a voltage in a first range between a voltage of the first voltage supply terminal and a voltage of the third voltage supply terminal and the second node operates at a voltage in a second range between a voltage of the first voltage supply terminal and a voltage of the second voltage supply terminal. The word line driver may have a further characterization by which the control electrode of the pull up transistor is connected to a control electrode of a top transistor in the stack of the plurality of decode transistors. The word line driver may have a further characterization by which the inverting circuit includes an N-channel transistor and a P-channel transistor each including a control electrode connected to the input of the inverting circuit, wherein a first current electrode of the N-channel transistor is connected to a first current electrode of the P-channel transistor, wherein the N-channel transistor and the P-channel transistor are characterized as higher voltage transistors. The word line driver may have a further characterization by which during operation, the output of the inverting circuit operates at a voltage in a third range at least between a voltage of the first voltage supply terminal and a voltage of the second voltage supply terminal. The word line driver may have a further characterization by which the first stack of transistors further includes a fourth transistor located in the first stack between the second node and the cascode transistor wherein the fourth transistor is characterized as a higher voltage transistor. The word line driver may have a further characterization by which the cascode transistor is characterized as a lower voltage transistor. The word line driver may have a further characterization by which the cascode transistor and the fourth transistor are N-channel transistors. The word line driver may have a further characterization by which the cascode transistor is characterized as a lower voltage transistor. The word line driver may have a further characterization by which the cascode transistor is characterized as a higher voltage transistor. The word line driver may have a further characterization by which during operation, the pull up transistor biases the first node at the voltage of the third supply voltage terminal when the plurality of decode signals are at non asserted levels. The word line driver may have a further characterization by which the first node is at a voltage of the third supply voltage terminal and the second node is at a voltage of the second supply voltage terminal when the plurality of decode signals are at non asserted levels. The word line driver may have a further characterization by which the third transistor includes a control electrode that is connected to a second source voltage terminal for providing a second source voltage, wherein the second source voltage is less than the second supply voltage so as to limit an amount of current flowing through the transistor when conductive. The word line driver may have a further characterization by which the pull up transistor is characterized as a lower voltage transistor. The word line driver may have a further characterization by which a memory comprises the word line driver and the memory further includes an address decoder, the address decoder providing the decode signals; an array of memory cells; and a plurality of word lines, wherein the word line driver is coupled to provide a word line signal on a word line of the plurality of word lines, wherein the word line is coupled to a subset of memory cells of the array. The word line driver may have a further characterization by which a charge pump including an output coupled to the second supply voltage terminal.

Also disclosed is a word line that includes a first stack of transistors. The first stack includes a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals. The first stack further includes a first cascode transistor having a first current electrode connected to the first node, the first cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage. The first stack further includes a second cascode transistor having a first current electrode coupled to a second current electrode of the first cascode transistor. The first stack further includes a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the second cascode transistor. The word line driver further includes a pull up transistor having a first current electrode connected to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode connected to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage. The word line driver further includes an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node. The word line driver has further characterizations by which the plurality of decode transistors, the first cascode transistor, and the pull up transistor are characterized as lower voltage transistors, the third transistor and the second cascode transistor are characterized as higher voltage transistors, and the plurality of decode transistors, the first cascode transistor, and the second cascode transistor are N-channel transistors, and the pull up transistor and the third transistor are P-channel transistors.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

Although the disclosure is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. For example, it may be feasible to use an N channel transistor in place of P channel transistor44although there are advantages to using a P channel transistor. For example, predecoded signal S0can be retained as is and not require a complement. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.