Resistance variable memory apparatus

A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The resistance variable memory apparatus may include a data transmission block transmitting data between the plurality of memory banks and the peripheral region. The data transmission block includes a plurality of lower global input/output lines shared by pairs of adjacent memory banks, a plurality of lower multiplexers receiving data from pairs of adjacent lower global input/output lines and outputting data inputted from one of the lower global input/output lines, and an upper multiplexer receiving data output from the plurality of lower multiplexers and outputting data input from one of the lower multiplexers.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2016-0119830 filed on Sep. 20, 2016, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor memory apparatus, and, more particularly, to a resistance variable memory apparatus.

2. Related Art

Memory apparatuses are semiconductor-based integrated circuits that may be used in computers or other electronic apparatuses. As is well known in the art, exemplary kinds of memories include various types of RAMs such as DRAM and SDRAM, various types of ROMs, flash memories, and resistance variable memories.

The resistance variable memory apparatus may include a switching element and a resistor element. The resistance variable memory apparatus may work by changing the resistance across a resistor element. Exemplary kinds of resistance variable memory apparatuses may include programmable conductor memories, resistive random access memories (ReRAM), and phase change random access memories (PCRAM).

Currently, research is being actively conducted on a 2-terminal device, which is capable of performing switching and memory functions.

SUMMARY

In an embodiment, a resistance variable memory apparatus may include a memory cell array region, a peripheral region, and a data transmission block. The peripheral region may be disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The data transmission block may transmit data between the plurality of memory banks and the peripheral region. The data transmission block may include a plurality of lower global input/output lines, a plurality of lower multiplexers, and an upper multiplexer. The plurality of lower global input/output lines may be shared by pairs of adjacent memory banks among the plurality of memory banks. The plurality of lower multiplexers may receive data from pairs of adjacent lower global input/output lines among the plurality of lower global input/output lines, and outputting data input from one selected between the lower global input/output lines. The upper multiplexer may receive data output from the plurality of lower multiplexers, and may output data input from one selected between the lower multiplexers.

In an embodiment, a resistance variable memory apparatus may include a peripheral region, a plurality of memory banks, a first data transmission block, and a second data transmission block. The plurality of memory banks may include first memory banks which are located relatively close to the peripheral region and second memory banks which are located relatively far from the peripheral region. The first data transmission block may transmit data between the first memory banks and the peripheral region. The second data transmission block may transmit data between the second memory banks and the peripheral region. A data transmission line of the first data transmission block may be configured to detour around circuits located on opposite side of the peripheral region, and a data transmission line of the second data transmission block may be connected to the peripheral region through a short route.

In an embodiment, a resistance variable memory apparatus may include a memory cell array, a plurality of first selection circuits, a plurality of second selection circuits, and a signal transmission circuit. The memory cell array may include a plurality of pairs of memory banks. Here, memory banks of each pair may share input/output lines. Each first selection circuit may be coupled to at least two input/output lines, and may select one of the at least two input/output. Each second selection circuit may be coupled to at least two first selection circuits, and may select one of data signals that are output from the at least two first selection circuits. The signal transmission circuit may receive data signals selected by the plurality of second selection circuits and transmit the data signals to a peripheral region.

DETAILED DESCRIPTION

Hereinafter, a resistance variable memory apparatus will be described below with reference to the accompanying drawings through various examples of embodiments.

FIG. 1is a layout diagram illustrating an example of a resistance variable memory apparatus in accordance with an embodiment.

Referring toFIG. 1, a resistance variable memory apparatus10in accordance with an embodiment may include a peripheral region100and a memory cell array region200.

The peripheral region100may include various circuits (not illustrated) for controlling the operation of the memory cell array region200. Also, the peripheral region100may include a plurality of input/output pads (not illustrated) for receiving write-requested data from an external device (e.g., a host device). The data may be read out via the input/output pads in response to a read request from the external device. The plurality of input/output pads disposed in the peripheral region100may be coupled to the memory cell array region200through global input/output lines which will be described later.

The memory cell array region200may be disposed next to the peripheral region100. The peripheral region100may be disposed along an edge of memory cell array region200. For example, the peripheral region100may extend in an X-axis direction along an edge of memory cell array region200where the memory cell array region200extends in a Y-axis direction. The memory cell array region200may include a first memory bank group210and a second memory bank group220. For example, the first memory bank group210and the second memory bank group220may be arranged in the X-axis direction along an edge of the peripheral region100, and memory banks constituting the first memory bank group210and memory banks constituting the second memory bank group220are arranged in the Y-axis direction, respectively.

Each of the first memory bank group210and the second memory bank group220may include a plurality of memory banks. For the sake of convenience in explanation, it is assumed that, as shown inFIG. 1, each of the first memory bank group210and the second memory bank group220includes eight memory banks BK0to BK7.

The respective memory banks BK0to BK7of the first memory bank group210and the respective memory banks BK0to BK7of the second memory bank group220may be sequentially arranged in the Y-axis direction from one side of the peripheral region100. For example, the memory bank BK0may be disposed at a position closest to the peripheral region100, and the memory bank BK7may be disposed at a position farthest from the peripheral region100.

That is to say, when viewed from above, the first memory bank group210and the second memory bank group220may be arranged in the X-axis direction along the peripheral region100. The memory banks BK0to BK7of the first memory bank group210and the second memory bank group220may be arranged in the Y-axis direction, and may be parallel to one another. Each of the memory banks BK0to BK7of the first memory bank group210may be disposed next to a corresponding one of the memory banks BK0to BK7of the second memory bank group220.

Each of the memory banks BK0to BK7of the first memory bank group210and each of the memory banks BK0to BK7of the second memory bank group220may include a plurality of memory blocks. For the sake of convenience in explanation, it is assumed that each of the memory banks BK0to BK7includes eight memory blocks BLK0to BLK7. One memory bank BK including eight memory blocks BLK0to BLK7is illustrated inFIG. 2.

While not illustrated inFIG. 2, each of the memory blocks BLK0to BLK7may include a plurality of mats, and each of the mats may include a plurality of memory cells.

Referring toFIG. 2, in a read operation, eight data units may be read from each of the memory blocks BLK0to BLK7. Here, the “data unit” may refer to smallest addressable unit of data, such as a bit, a byte, or a word. For example, if a read request is issued from a host device, the resistance variable memory apparatus10may output sixty-four data units from a memory bank corresponding to read-requested address received from the host device. In other words, data DQ0to DQ7may be read by eight data units from each of the eight memory blocks BLK0to BLK7shown inFIG. 2, and sixty-four data units DQ0to DQ7in total may be provided to the input/output pads of the peripheral region100through corresponding global input/output lines GIO. To this end, eight global input/output lines GIO may be coupled between each of the memory blocks BLK0to BLK7and the peripheral region100. The respective global input/output lines GIO may be coupled to the plurality of memory cells included in each of the memory blocks BLK0to BLK7. In this way, the data stored in memory cells corresponding to a read-requested address, among the plurality of memory cells, may be transmitted to the peripheral region100through a corresponding global input/output line GIO.

In accessing memory cells to read out data at a high speed and transmit a large amount of data within a predetermined time, a memory bank interleaving method may be used. The memory bank interleaving method is a method that outputs data from another memory bank while data is being output from a certain memory bank and then being stored again in the certain memory bank. The memory bank interleaving method may reduce a data access time because it enables data to be successively output. As a result, the read failure rate may decrease.

However, as shown inFIG. 1, as the first and second memory bank groups210and220are disposed along an X-axis-direction edge of the peripheral region100and the memory banks BK0to BK7are arranged in the Y-axis direction, there are wide variations in distances between the peripheral region100and the memory banks BK0to BK7. This leads to an increase in the difference between a data transmission time from the memory bank BK0to the peripheral region100and a data transmission time from the memory bank BK7to the peripheral region100.

In other words, a length of time it takes to read out data to the peripheral region100from the memory bank BK7is very longer than a length of time it takes to read out data to the peripheral region100from the memory bank BK0. As a result, when a read operation is performed on the memory bank BK0after a read operation is performed on the memory bank BK7, a timing conflict between the data output from the memory bank BK7and the data output from the memory bank BK0may occur. In this case, a read failure may occur.

In addition, due to the wide variations in distances between the peripheral region100and the memory banks BK0to BK7, an interleaving margin between the memory bank BK7and the memory bank BK0may decrease, which may render an interleaving operation impossible.

Therefore, in order to secure an interleaving margin among the memory banks BK0to BK7, it is necessary to minimize the variation of data transmission distance (or data transmission time) among the memory banks BK0to BK7.

FIG. 3is a diagram illustrating an example layout of the global input/output lines of the resistance variable memory apparatus in accordance with an embodiment. For the sake of convenience in explanation, one memory bank group of the memory bank groups210and220shown inFIG. 1is illustrated inFIG. 3. It is to be noted that the other memory bank groups may have the same structure as the memory bank group illustrated inFIG. 3.

Referring toFIG. 3, the resistance variable memory apparatus10may include eight memory banks BK0to BK7each including eight memory blocks BLK0to BLK7. The resistance variable memory apparatus10may also include the peripheral region100. Also, the resistance variable memory apparatus10may include a data transmission block for transferring data between the respective memory blocks BLK0to BLK7of the respective memory banks BK0to BK7and the peripheral region100.

The data transmission block may include a plurality of lower global input/output lines LGIO, a plurality of upper global input/output lines UGIO, a plurality of lower multiplexers LM, a plurality of upper multiplexers UM, and a plurality of repeaters LR1, LR2, UR1, and UR2. Here, the terms “lower” and “upper” do not necessarily mean physical positions, but are used to distinguish between two groups of global input/output lines, between two groups of multiplexers, and between two groups of repeaters.

The plurality of lower global input/output lines LGIO may include first to fourth lower global input/output lines LGIO1to LGIO4which are shared by two adjacent memory banks among the eight memory banks BK0to BK7.

The first lower global input/output line LGIO1may be shared by the first and second memory banks BK0and BK1which are adjacent to the peripheral region100. For example, the first lower global input/output lines LGIO1may include eight first lower global input/output lines LGIO1which are shared by the respective memory blocks BLK0to BLK7of the first memory bank BK0and the respective memory blocks BLK0to BLK7of the second memory bank BK1. Further, the first lower global input/output lines LGIO1may include eight lower global input/output lines.

The second lower global input/output lines LGIO2may be shared by the third and fourth memory banks BK2and BK3adjacent to the second memory bank BK1. The third lower global input/output lines LGIO3may be shared by the fifth and sixth memory banks BK4and BK5adjacent to the fourth memory bank BK3. The fourth lower global input/output lines LGIO4may be shared by the seventh and eighth memory banks BK6and BK7adjacent to the sixth memory bank BK5.

The second lower global input/output lines LGIO2may include eight lower global input/output lines LGIO2which are shared by the respective memory blocks BLK0to BLK7of the third memory bank BK2and the respective memory blocks BLK0to BLK7of the fourth memory bank BK3. The third lower global input/output lines LGIO3may include eight lower global input/output lines LGIO3which are shared by the respective memory blocks BLK0to BLK7of the fifth memory bank BK4and the respective memory blocks BLK0to BLK7of the sixth memory bank BK5. The fourth lower global input/output lines LGIO4may include eight lower global input/output lines LGIO4which are shared by the respective memory blocks BLK0to BLK7of the seventh memory bank BK6and the respective memory blocks BLK0to BLK7of the eighth memory bank BK7.

Each of the second to fourth lower global input/output lines LGIO2to LGIO4may include eight lower global input/output lines.

Each of the plurality of lower multiplexers LM may receive data from two lower global input/output lines adjacent thereto, and may output the data input from one lower global input/output line selected between the two lower global input/output lines, to a corresponding upper multiplexer UM.

The plurality of lower multiplexers LM may include a plurality of first lower multiplexers LM1and a plurality of second lower multiplexers LM2. Each first lower multiplexer LM1may receive the data transmitted from the plurality of first lower global input/output lines LGIO1and the plurality of second lower global input/output lines LGIO2. Each second lower multiplexer LM2may receive the data transmitted from the plurality of third lower global input/output lines LGIO3and the plurality of fourth lower global input/output lines LGIO4.

For example, each first lower multiplexer LM1may receive the data transmitted from a corresponding first lower global input/output line LGIO1and the data transmitted from a corresponding second lower global input/output line LGIO2. Each first lower multiplexer LM1may select read-requested data between the two data, and may output selected data to a corresponding upper multiplexer UM.

Further, each second lower multiplexer LM2may receive the data transmitted from a corresponding third lower global input/output line LGIO3and the data transmitted from a corresponding fourth lower global input/output line LGIO4. Each second lower multiplexer LM2may select read-requested data between the two data, and may output selected data to a corresponding upper multiplexer UM.

The plurality of upper global input/output lines UGIO may include a plurality of first upper global input/output lines UGIO1and a plurality of second upper global input/output lines UGIO2. Each first upper global input/output line UGIO1may couple the plurality of first lower multiplexers LM1to upper multiplexers UM, and each second upper global input/output line UGIO2may couple the plurality of second lower multiplexers LM2to upper multiplexers UM. Each of the upper global input/output lines UGIO may include eight upper global input/output lines.

The plurality of upper multiplexers UM may receive the two data units from the plurality of first lower multiplexers LM1and the plurality of second lower multiplexers LM2, respectively. The plurality of upper multiplexers UM may select read-requested data between the two data units, and may output selected data to the repeaters LR1and UR1. Each upper multiplexer UM may be coupled to eight input/output lines.

The plurality of repeaters LR1, LR2, UR1, and UR2may receive the data from the plurality of upper multiplexers UM and output the data to the peripheral region100.

The plurality of repeaters LR1, LR2, UR1, and UR2may include first repeaters LR1and UR1, which directly receive the data from the plurality of upper multiplexers UM, and second repeaters LR2and UR2, which receive the data from the first repeaters LR1and UR1and transmit the data to the peripheral region100.

The first repeaters LR1and UR1may include a first lower repeater LR1, which receives lower-numbered data units DQ0to DQ3from the lower-numbered memory blocks BLK0to BLK3of the respective memory banks BK0to BK7, and a first upper repeater UR1, which receives higher-numbered data units DQ4to DQ7from the higher-numbered memory blocks BLK4to BLK7of the respective memory banks BK0to BK7.

Also, the second repeaters LR2and UR2may include a second lower repeater LR2, which receives the data from the first lower repeater LR1, and a second upper repeater UR2, which receives the data from the first upper repeater UR1.

The read operations of the respective memory banks BK0to BK7in accordance with an embodiment will be described below with reference toFIG. 3.

For example, in the case where a read-requested address provided from the host device belongs to the first memory bank BK0, the first lower global input/output lines LGIO1coupled to the respective memory blocks BLK0to BLK7of the first memory bank BK0may be activated, and the remaining lower global input/output lines LGIO2to LGIO4may be deactivated.

Thereafter, the data DQ0to DQ7read from the corresponding address may be respectively input to the corresponding first lower multiplexers LM1, and the first lower multiplexers LM1may select one or more of the data units DQ0to DQ7input from the first lower global input/output lines LGIO1, by referring to the read-requested address. The selected data units selected between the data units DQ0to DQ7may be output to the corresponding upper multiplexers UM through the first upper global input/output lines UGIO1. Then, the upper multiplexers UM may select one or more of the data units DQ0to DQ7input from the first upper global input/output lines UGIO1, by referring to the read-requested address, and the selected data units selected between the data units DQ0to DQ7may be output to the first repeaters LR1and UR1. The first repeaters LR1and UR1may output the input data DQ0to DQ7to the second repeaters LR2and UR2, and the second repeaters LR2and UR2may output the input data DQ0to DQ7to corresponding input/output pads of the peripheral region100.

While the above description contains many specificities, these should not be construed as limitations on the scope of the invention. For example, although the read-requested address is described as belonging to the first memory bank BK0, it is to be noted that the read-requested address may belong to the other memory blocks, and the same read operation may be performed with respect to all the memory banks BK0to BK7.

In an embodiment, in order to minimize the variation in data transmission distance (or time) between a memory bank close to the peripheral region100and a memory bank far from the peripheral region100, the global input/output lines coupled to memory banks relatively close to the peripheral region100may detour around some circuits located on opposite side of the peripheral region100, instead of a straight route to the peripheral region100, and the global input/output lines coupled to memory banks relatively far from the peripheral region100may be formed in a way that is connected to the peripheral region100through a short route.

That is to say, the data read from memory banks relatively close to the peripheral region100(e.g., the memory banks BK0to BK3) may be detoured when transmitted to the peripheral region100. As a result, the difference between a time it takes to transfer the data from memory banks relatively close to the peripheral region100(e.g., the memory banks BK0to BK3) to the peripheral region100and a time it takes to transfer the data from memory banks relatively far from the peripheral region100(e.g., the memory banks BK4to BK7) to the peripheral region100may be minimized. Therefore, an interleaving margin between memory banks may be secured.

For example, when a read operation is performed on the memory bank BK0close to the peripheral region100right after a read operation has been performed on the memory bank BK7distant from the peripheral region100, since the data read from the memory bank BK0may be detoured when transmitted to the peripheral region100, it is possible to prevent a read failure from occurring by avoiding a timing conflict between the data read from the memory bank BK7and the data read from the memory bank BK0.

In an embodiment, a resistance variable memory apparatus may include a memory cell array200, a plurality of first selection circuits, a plurality of second selection circuits, and a signal transmission circuit. The memory cell array may include a plurality of pairs of memory blocks BLK0to BLK7of memory banks BK0to BK7. Here, memory blocks of each pair may share input/output lines LGIO. Each first selection circuit may be coupled to at least two input/output lines, and may select one of the at least two input/output lines LGIO. Each second selection circuit may be coupled to at least two first selection circuits, and may select one of data signals that are output from the at least two first selection circuits. The signal transmission circuit may receive data signals selected by the plurality of second selection circuits and transmit the data signals to a peripheral region. Here, the first selection circuit may include a multiplexer LM, and the second selection circuit may include a multiplexer UM. Each of the first selection circuits is located between two pairs of memory banks. Each of the second selection circuits is located between two first selection circuits such that a distance between the second selection circuit and one of the two first selection circuits is similar to a distance between the second selection circuit and the other of the two first selection circuits. The signal transmission circuit includes a repeater LR1and UR1. The second selection circuits may be divided into two groups, and the signal transmission circuit may be located between the two groups of second selection circuits.

FIG. 4is a diagram conceptually illustrating the data transmission distances of the memory bank BK0and the memory bank BK7. For the sake of convenience in explanation, only one memory block BLK0is illustrated in each of the memory banks BK0to BK7.

Referring toFIG. 4, the transmission line of the data DQ0read from the memory block BLK0of the memory bank BK0is denoted as “{circle around (1)}” and the transmission line of the data DQ0read from the memory block BLK0of the memory bank BK7is denoted as “{circle around (2)}.” Here, the physical length of the transmission line denoted as “{circle around (1)}” and the physical length of the transmission line denoted as “{circle around (2)}” may be similar to each other.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the resistance variable memory apparatus described herein should not be limited based on the described embodiments.