Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0095271 filed on Sep. 30, 2010, the subject matter of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Embodiments of the inventive concept relate to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). More particularly, embodiments of the inventive concept relate to capacitor DAC converting circuits, ADCs including capacitor DAC converting circuits, and semiconductor devices incorporating same.

ADCs are a well known class of circuits that generate corresponding digital data values (or digital code) in response to an applied analog signal. Quite commonly, the generated digital code is correlated to one or more voltage levels of the analog signal, and a sequence of digital codes may be generated for the analog signal over a defined period of time. DACs are also a well known class of circuits that essentially operate to reproduce an analog signal from a corresponding set of digital codes.

There are many different types of ADCs and DACs. ADCs and DACs are used in many applications, and sometimes used in conjunction with one another to facilitate analog signal and digital signal processing. In certain circuits DACs are used within an ADC.

One type of DAC is the so-called capacitor DAC. Capacitor DACs are used in a variety of application such as successive approximation register (SAR) circuits and methods. SAR circuits and methods may be used, for example, to compare data by repeatedly performing digital-to-analog conversion to thereby determine the bit values of the data being compared. While capacitor DACs prove useful in a certain applications, the constituent capacitors are relatively difficult to fabricate within narrow performance tolerances. That is, the constituent capacitors exhibit performance characteristics that vary with fabrication process variations. As a result, circuits incorporating capacitor DACs (e.g., ADC/DAC circuits and SAR circuits) tend to run at relatively low operating speed.

SUMMARY OF THE INVENTION

Embodiments of the inventive concept provide digital-to-analog converters (DACs) that perform better at high operating speeds. Embodiments of the invention provide DACs including capacitors that are markedly less susceptible to performance deviation due to fabrication process variations. In certain embodiments of the inventive concept, DACs include capacitors having a capacitance defined in relation to a unit capacitor capacitance. As such, the capacitors are less sensitive to process variation and occupy relatively less area.

Other embodiments of the inventive concept provide analog-to-digital converters (ADCs) including this type of DAC, and still other embodiments of the inventive concept provide semiconductor devices incorporating this type of ADC and/or DAC.

In one aspect, embodiments of the inventive concept provide a digital-to-analog converter (DAC) receiving a digital output and generating a corresponding analog signal, the DAC comprising; a capacitor array arranging a plurality of capacitors, and at least one dummy capacitor configured within the capacitor array and having a capacitance determined such that each capacitor in the plurality of capacitors has a respective capacitance that is an integer multiple of a capacitance of a unit capacitor.

In another aspect, embodiments of the inventive concept provide a digital-to-analog converter (DAC) receiving a digital output and generating a corresponding analog signal, the DAC comprising; a first capacitor bank electrically connected to a first conductive line, a first split capacitor having a first terminal electrically connected to the first conductive line, a second conductive line electrically connected to a second terminal of the first split capacitor, a second capacitor bank electrically connected to the second conductive line, a second split capacitor having a first terminal electrically connected to the second conductive line, a third conductive line electrically connected to a second terminal of the second split capacitor, a third capacitor bank electrically connected to the third conductive line, a first compensating capacitor connected across the first split capacitor to compensate for a parasitic capacitance of the first conductive line, a second compensating capacitor connected across the second split capacitor to compensate for a parasitic capacitance of the second conductive line, and a third compensating capacitor connected across the second split capacitor to compensate for the parasitic capacitance of the first conductive line.

In another aspect, embodiments of the inventive concept provide an analog-to-digital converter (ADC), comprising; a digital-to-analog converter (DAC) configured to generate a hold voltage signal in response to a digital output and an input analog signal, a comparator circuit configured to compare the hold voltage signal with the reference voltage signal to generate a comparison output voltage signal, and a signal processing circuit configured to perform successive approximation based on the comparison output voltage signal to generate the digital output. The DAC comprises a capacitor array arranging a plurality of capacitors, and at least one dummy capacitor configured within the capacitor array and having a capacitance determined such that each capacitor in the plurality of capacitors has a respective capacitance that is an integer multiple of a capacitance of a unit capacitor.

In another aspect, embodiments of the inventive concept provide a semiconductor device, comprising; an analog-to-digital converter (ADC) configured to convert an analog input signal into a corresponding digital output; and a digital signal processing circuit configured to perform digital signal processing on the digital output. The ADC includes a digital-to-analog converter (DAC) configured to generate a hold voltage signal in response to a digital output and an input analog signal, a comparator circuit configured to compare the hold voltage signal with the reference voltage signal to generate a comparison output voltage signal, and a signal processing circuit configured to perform successive approximation based on the comparison output voltage signal to generate the digital output. The DAC comprises a capacitor array arranging a plurality of capacitors, and at least one dummy capacitor configured within the capacitor array and having a capacitance determined such that each capacitor in the plurality of capacitors has a respective capacitance that is an integer multiple of a capacitance of a unit capacitor.

DETAILED DESCRIPTION

Various embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings. It should be noted that the inventive concept may be embodied in different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art.

It will be understood that when an element is referred to as being “connected to” or “connected with” another element, it may be directly connected or connected to the other element through intervening elements. In contrast, when an element is referred to as being “directly connected to” or “directly connected with” another element, there are no intervening elements present. The term “and/or” combines the conjunctive with the alternative to specify any one listed item as well as all possible combinations thereof.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, or section from another. Thus, a first element, component, region, or section discussed below could be termed a second element, component, region, or section without departing from the teachings of the inventive concept.

Terms describing spatial relationships, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, should be interpreted with respect to orientations depicted in the drawings. If an orientation depicted in the drawings is changed, it is intended that such spatial terms change as well to reflect the new orientation. For example, if a device shown in the drawings is turned upside down, elements described as “below” or “beneath” other elements or features would then be “above” the other elements or features and, accordingly, “below” and “beneath” should be changed to “above.” Clearly, such changes in orientation do not constitute departures from the scope of the inventive concept.

Figure (FIG. 1is a block diagram illustrating an analog-to-digital converter (ADC)100in accordance with an embodiment of the inventive concept.

Referring toFIG. 1, the ADC100generally comprises a digital-to-analog converter (DAC)110, a comparator circuit130and a signal processing circuit150.

The DAC110in the illustrated embodiment includes a capacitor array including at least one split capacitor having a capacitance defined in relation to (e.g., defined as a multiple of) a given unit capacitance. The DAC110converts a digital output SAR into a corresponding analog signal (hold voltage signal VHOLD) using an analog input signal VIN.

The hold voltage signal VHOLD is applied to comparator130and compared with a reference voltage signal VREF to generate a comparison output voltage signal COMPO.

The signal processing circuit150performs successive approximation on the comparison output voltage signal COMPO to generate the digital output SAR.

In the illustrated example ofFIG. 1, the ADC100further comprises a timing circuit160and an output register170.

The timing circuit160generates a conversion control signal CON and a conversion select signal SEL in response to an applied clock signal CLK and a conversion start signal ST. One or both of the conversion control signal CON and the conversion select signal SEL may be applied to control the operation of the signal processing circuit150. The output register170stores the digital output SAR, and outputs the digital output SAR as output data in response to the output the signal processing circuit150.

The ADC100ofFIG. 1may provide any reasonable number of digital data bits (e.g., 10 bits) to generate the digital output SAR.

The ADC100ofFIG. 1is assumed to use a successive-approximation technique for analog-to-digital conversion. Those skilled in the art recognize that this may be accomplished using a variety of circuits and methods, but certain principles of successive approximation will now be described.

Each bit of a digital code representing a sampled value of an analog signal may be determined through a single iteration starting with a most significant bit (MSB or 1st). The MSB is set to a specific logic value (e.g., 0) and the next significant bit (2nd) is set to another logic value (e.g., 1). The resulting data value may then be converted to an intermediate analog signal. If the actual sampled value of the analog signal has a level less than the intermediate analog signal, the MSB of the digital code may be determined to be “0”. On the contrary, if the sampled value of the analog signal has a level greater than the intermediate analog signal, the MSB of the digital code is determined to be “1”. The next significant bit (2nd) may then be set to “1”, and a next most significant bit (3rd) may be set to “0”. The resulting data value obtained in this manner may be used to generate a next (or new) intermediate analog signal. The new intermediate analog signal is then compared with a sampled value of the analog signal to determine the value of a next significant bit of a digital code corresponding to the new intermediate analog signal. This approximation operation is successively performed until all bits of the digital code (1stthrough Nth) are determined.

In the embodiment of the inventive concept illustrated inFIG. 1, the ADC100comprises digital-to-analog converting circuit110that includes dummy capacitors and capacitors having a capacitance that is a multiple of a given unit capacitance.

FIG. 2is a circuit diagram further illustrating one possible example of DAC110ofFIG. 1.FIG. 3is a circuit diagram still further illustrating DAC110ofFIG. 2. InFIG. 2, a double-split-capacitor DAC is shown as one possible example of a DAC that may be used in certain embodiments of the inventive concept.

Referring toFIG. 2, DAC110comprises a first split capacitor CA1, a second split capacitor CA2, a first capacitor bank (CB1)112, a second capacitor bank (CB2)114, a third capacitor bank (CB3)116, a first dummy capacitor CF1and a second dummy capacitor CF2.

The first split capacitor CA1, the second split capacitor CA2, the first capacitor bank112, the second capacitor bank114, the third capacitor bank116, the first dummy capacitor CF1may each have a capacitance that is an integer multiple of the capacitance of a unit capacitor.

InFIG. 3, the first capacitor bank112is disposed in front of the first split capacitor CA1and the second capacitor bank114. In this configuration, the first split capacitor is between the first capacitor bank112and the second capacitor bank114. For purposes of general illustration, the first capacitor bank112is assumed to include capacitors having respective capacitances of C, C, and 2 C, where “C” is the given unit capacitance.

The second capacitor bank114is disposed behind the first split capacitor CA1and in front of the second split capacitor CA2, and includes capacitors having respective capacitances of C, 2 C, and 4 C.

The third capacitor bank116is disposed behind the second split capacitor CA2, and includes capacitors having capacitances of C, 2 C, 4 C, 8 C and 16 C.

A common top node N1of the capacitors in the first capacitor bank112is connected to a first terminal of the first split capacitor CA1. A common top node N2of the capacitors in the second capacitor bank114is connected a second terminal of the first split capacitor CA1and a first terminal of the second split capacitor CA2. And a common top node N3of the capacitors included in the third capacitor bank116is connected to a second terminal of the second split capacitor CA2.

One of the analog input signal VIN, a first reference voltage VRH and a second reference voltage VRL is switch-selectively applied to the respective bottom nodes of the capacitors included in each one of the first capacitor bank112, second capacitor bank114and third capacitor bank116. Thus, in the illustrated embodiment ofFIG. 1, each of the respective capacitor node switches provides one of the analog input signal VIN, first reference voltage VRH or second reference voltage VRL to the bottom node of the capacitors in accordance with the digital output SAR. In one more particular embodiment of the inventive concept, the first reference voltage VRH may be a supply voltage VDD, and the second reference voltage VRL may be ground voltage.

The bottom nodes of the first dummy capacitor CF1and the second dummy capacitor CF2are connected in the illustrated embodiment to the second reference voltage VRL.

InFIGS. 2 and 3, CP1denotes a first parasitic capacitance associated with the first common node N1. That is, the first parasitic capacitance CP1associated with the conductive line(s) connected to the first terminal of the first split capacitor CA1is accounted for in the illustrated embodiment. A second parasitic capacitance CP2is associated with the second common node N2. That is, the second parasitic capacitance CP2associated with conductive line(s) connected between the first split capacitor CA1and the second split capacitor CA2is accounted for in the illustrated embodiment.

Of note the double-split-capacitor DAC110ofFIGS. 2 and 3is just one example of a competent DAC that might be incorporated within the ADC100according to various embodiments of the inventive concept. A ladder-capacitor DAC, for example, might be alternately used.

FIG. 4is a circuit diagram further illustrating the parasitic capacitors (CP1, CP2) accounted for in the design and operation of the DAC110ofFIGS. 2 and 3. Those skilled in the art will recognize that the DAC110will inherently include certain parasitic capacitances like those modeled inFIG. 4and which are apparent at each node of constituent capacitors of DAC110, including the capacitors arranged in the respective capacitor banks (112,114,114) and also effective capacitors associated with the conductive lines connecting elements in the DAC110.

FIG. 5andFIG. 6are additional circuit diagrams illustrating one approach to determining or effectively modeling an appropriate capacitance for the dummy capacitors (CF1, CF2) included in the capacitor array of the DAC110ofFIG. 3.FIGS. 5 and 6should be considered withFIG. 4.

FIG. 5shows the first parasitic capacitance CP1and the second parasitic capacitance CP2which are respectively associated with conductive line(s) connected to the first split capacitor CA1and the second split capacitor CA2. The effective (switch-selected) capacitance of the first capacitor bank112is indicated by CL1and the effective (switch-selected) capacitance of the second capacitor bank114is indicated by CL2inFIG. 5. The “apparent” or the cumulative capacitance “seen by” or connected to the first terminal of the first split capacitor CA1is indicated inFIG. 5as C1. Similarly, the apparent capacitance seen by the second terminal of the first split capacitor CA1is indicated inFIG. 5as C2. Finally, inFIG. 5, the capacitance of the first dummy capacitor is indicated by CF1and the capacitance of the second dummy capacitor is indicated by CF2.

As described below, the capacitance CF1of the first dummy capacitor may be expressed by Equation 1 and the capacitance CF2of the second dummy capacitor may be expressed Equation 2.
CF1=CA1(CL1−1)−CL1−CP1.   (1)
CF2=CA2(CL2+1−1)−(CL2+1)−C2+1−CP2.   (2)

Referring now toFIG. 6, equivalent circuit (a) models the capacitor DAC without addition of dummy capacitor(s), while circuit (b) models the same, albeit with one or more dummy split capacitors added. InFIG. 6, the capacitance of the dummy capacitor(s) is indicated by “CA” and “CM” is the unit capacitance. In the circuit (a) ofFIG. 6, variation of the capacitance seen by the second terminal of the split capacitor CAP is given by Equation 3 below, where CL and CM are assumed to vary. In the circuit (b) ofFIG. 6, variation of capacitance seen by the second terminal of the split capacitor CA is given by Equation 4, again where CL and CM are assumed to vary.
ΔCAP=(CAP×(CM+CL)+CL×CM)/(CAP×(CM+CL−1)+CL×(CM−1))   (3)
ΔCA=(CA×(CM+CL)+(CL+CF)×CM)/(CA×(CM+CL−1)+CL×(CM−1)+(C−1)×CF)   (4)

Here, since CM is the capacitance of the unit capacitor, CM becomes 1, and a composite capacitance (CL//CLP) of a serial connection of CL and CLP becomes 1. Thus, CAP=CL/(CL−1) and Equation 5 holds.
(CAP×(1+CL)+CL)/(CAP×CL)=2.   (5)

Accordingly, Equation 4 above may be simplified to Equation 6.
(CA×(1+CL)+(CL+CF))/(CA×CL)=2.   (6)

Thus, an appropriate capacitance for the dummy capacitor may be obtained using Equation 7.
CF=(CL−1)×CA−CL(7)

Therefore, the capacitance of dummy capacitors CF1and CF2and the capacitance of the split capacitors CA1and CA2included in a double-split-capacitor DAC according to certain embodiments of the inventive concept may be obtained using the foregoing approach.

By adding dummy capacitors having appropriately calculated capacitance, the capacitance of capacitors included in capacitor DACs according to certain embodiments of the inventive concept may be defined to have respective capacitances that are multiple of the capacitance of a unit capacitor. As a result, an ADC including a DAC, such as those described above in relation toFIGS. 2 through 5, may be successfully operated at higher speed with excellent resolution.

FIG. 7is a perspective view illustrating one possible example of a capacitor having a structure that reduces the influence of parasitic capacitance in the DAC110ofFIG. 3.FIG. 8is a circuit diagram illustrating an equivalent circuit for the capacitor ofFIG. 7.

Referring toFIGS. 7 and 8, a horizontal parasitic capacitance CPB arises between a bottom node NB and the ground, and a vertical parasitic capacitance CPT arises between a top node NT and the bottom node NB. Referring toFIG. 7, the top node NT is encapsulated by conductive material118electrically connected to the bottom node NB.

Therefore, in a DAC according to an embodiment of the inventive concept, a horizontal parasitic capacitance between the ground and the bottom node NB that may adversely affect the performance of the DAC may be effectively converted into a vertical parasitic capacitance between the top node NT and the bottom node NB that is fully accounted for in the DAC design. Therefore, the capacitance of the unit capacitor for a DAC according to an embodiment of the inventive concept may be greater yet more stable than the capacitance of a unit capacitor in conventional DACs. Therefore, an ADC according to embodiments of the inventive concept and including a DAC like DAC110described above may be successfully operated at higher speed with excellent resolution.

Further, in the DAC110in accordance with certain embodiments of the inventive concept, variation of parasitic capacitance due to process variations may be uniform for the whole circuit because the whole circuit is implemented using a unit capacitor. Therefore, the DAC110will not suffer ill-effects of unbalanced overall charge distribution. Accordingly, the DAC110according to embodiments of the inventive concept may be designed in a manner that provides for markedly greater immunity to process variations.

FIG. 9is a circuit diagram illustrating one possible example of an approach to compensation for parasitic capacitors in conductive line(s) connected to both terminals of split capacitors included in the DAC110ofFIGS. 3 through 5.

InFIG. 9, the split capacitors CA1and CA2, the parasitic capacitances CP1and CP2, and compensating capacitors CMD1, CMD2and CMD3connected to the conductive lines LN1and LN2in a capacitor array of the DAC ofFIG. 5are shown for convenience. However, the capacitor banks and the dummy capacitors may be connected to the conductive lines LN1and LN2.

InFIG. 9, the first compensating capacitor CMD1, the second compensating capacitor CMD2and the third compensating capacitor CMD3provide compensation for the parasitic capacitance CP1of the first conductive line LN1and the parasitic capacitance CP2of the second conductive line LN2.

The first compensating capacitor CMD1is connected across the first split capacitor CA1and has one third the parasitic capacitance of a first conductive line LN1connected to a first terminal of the first split capacitor CA1. The second compensating capacitor CMD2is connected across the second split capacitor CA2, and has one seventh the parasitic capacitance of the second conductive line LN2connected between the second terminal of the first split capacitor CA1and the first terminal of the second split capacitor CA2. The third compensating capacitor CMD3is connected across the second split capacitor CA2and has one twenty-eighth the parasitic capacitance of the first conductive line LN1.

The capacitance of compensating capacitors used in the DAC for compensating for the parasitic capacitance CP1of the first conductive line LN1and the parasitic capacitance CP2of the first conductive line LN2may be determined using Equations 8 through 11.

FIG. 10is a circuit diagram illustrating one possible approach to compensating capacitors ofFIG. 9, as implemented in a semiconductor integrated circuit.

Referring toFIG. 10, the compensating capacitors CMD1, CMD2and CMD3may be implemented using conductive lines that have a length proportional to the length of the conductive lines LN1and LN2connected to the split capacitors CA1and CA2and are connected in parallel to the split capacitors CA1and CA2.

The first compensating capacitor CMD1may include two conductive lines LN3and LN4connected to the first terminal and the second terminal of the first split capacitor CA1. Each of the two conductive lines has one third the length of the first conductive line LN1. The second compensating capacitor CMD2may include two conductive lines LN5and LN6connected to the first terminal and the second terminal of the second split capacitor CA2. Each of the two conductive lines has one seventh the length of the second conductive line LN2. The third compensating capacitor CMD3may include two conductive lines LN7and LN8connected to the first terminal and the second terminal of the second split capacitor CA2. Each of the two conductive lines has one twenty-eighth the length of the first conductive line LN1.

For example, the conductive lines LN3and LN4may be replicas of the first conductive line LN1, and the conductive lines LN5and LN6and the conductive lines LN7and LN8may be replicas of the second conductive line LN2.

FIG. 11is a diagram illustrating an encapsulated structure of a conductive line and a replica line that may be included in the DAC110ofFIG. 3.

Referring toFIG. 11, both the conductive line and the replica line are encapsulated with conductive material. When the conductive line and the replica of the conductive line are encapsulated as shown inFIGS. 10 and 11, parasitic capacitance will exist only between each conductive line and ground. Therefore, precise compensating capacitors may be implemented using conductive lines, and also dummy capacitors may be implemented using conductive lines and their replicas.

As described above, the deterioration of capacitor performance due to process variation of the compensating capacitors CMD1, CMD2and CMD3may be decreased.

FIG. 12is a block diagram illustrating an ADC200in accordance with another embodiment of the inventive concept.

Referring toFIG. 12, the ADC200includes a digital-to-analog converter (DAC)210, a preamplifier220, a comparator circuit230and a signal processing circuit250.

The DAC210includes a capacitor array including at least one split capacitor having a capacitance that is a multiple of a unit capacitance and capacitors having respective capacitances that multiple(s) of the unit capacitance. The DAC210converts digital output SAR into a corresponding analog signal in a manner like that previously described in relation toFIG. 2However, the preamplifier220is additionally provided to amplify a difference between the hold voltage signal VHOLD and the reference voltage signal VREF.

FIG. 13is a block diagram illustrating a semiconductor device1000that includes an ADC, like the ones shown inFIGS. 1 and 12, that is designed in accordance with an embodiment of the inventive concept.

Referring toFIG. 13, the semiconductor device1000generally comprises an ADC1100and a digital signal processing circuit1200.

The ADC1100converts an analog input signal VIN to a corresponding digital signal and generates a first digital output data DOUT1. The digital signal processing circuit1200performs digital signal processing on the first digital output data DOUT1to generate a second digital output data DOUT2.

ADCs according to embodiments of the inventive concept include a DAC having dummy capacitors, and capacitors included in the DAC have a capacitance that is a multiple of a capacitance of a unit capacitor. Because capacitors included in the DAC of the ADC according to embodiments of the inventive concept have a capacitance that is a multiple of a capacitance of a unit capacitor, design of an integrated circuit is relatively straightforward. Further, the ADC may include compensating capacitors across split capacitors that are able to compensate for deterioration of capacitor performance characteristics caused by parasitic capacitance in a capacitor array. Therefore, the ADC according to embodiments of the inventive concept is relatively insensitive to process variations and may be operated at relatively high speed with excellent resolution.