Memory structure, programming method and reading method therefor, and memory control circuit thereof

The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. The appropriate set of reference currents is chosen from a number of sets of selective reference currents according to the threshold voltage distribution of each of the memory units. Thus each of the memory units of the memory structure of the present invention is sensed with its own appropriate set of reference currents correctly, and the improvement of sensing accuracy is therefore achieved.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a memory structure, and more particularly to a memory structure which uses reference group bit values to indicate sets of reference currents while sensing memory units.

2. Description of the Related Art

The memory capacity for storing data grows larger and larger recently. With the amount of the memory cells grows higher, the threshold voltage distribution range of the memory cells therefore becomes very large.FIG. 1AandFIG. 1Bare examples of threshold voltage distribution diagrams of a conventional 1-Megabites memory and a conventional 1-Gigabites memory respectively. Both of them are 2-level cell memories. The horizontal axis represents the threshold voltage of a memory cell; the vertical axis represents the amount of memory cells. The threshold voltage distribution of the 1-Megabiyte memory includes distribution regions101to104. SW1is the sensing window between the high boundary of distribution region101and low boundary of distribution region102. Similarly, SW2is the sensing window between distribution regions102and103. SW3is the sensing window between distribution regions103and104. Distribution regions105to108are threshold voltage distribution regions of the 1-Gigabiyte memory. Sensing windows SW4to SW6are the sensing windows of the 1-Gigabyte memory. As shown inFIG. 1AandFIG. 1B, the ranges of distribution regions105to108are generally larger than the ranges of distribution regions101to104, which causes sensing windows SW4to SW6of the 1-Gigabyte memory are much narrower than the sensing windows SW1to SW3of the 1-Megabyte memory. Thus, when the capacity of a memory grows higher, the diversity of the threshold voltages of the memory cells of the memory becomes larger, and the sensing windows of the memory become narrower, which causes difficulty to perform the sensing process for distinguishing states of memory cells of the memory when reading the memory.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a memory structure. The sensing accuracy of memory cells is improved by dividing the main array of the memory structure into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates the appropriate set of reference currents. Thus each of the memory units of the memory structure is sensed with its own appropriate set of reference currents.

The invention achieves the above-identified object by providing a memory structure. The memory structure includes a main array and a reference group bit array. The main array includes a number of memory units. Each of the memory units includes a number of memory cells. Each of the memory units has a number of threshold voltage distribution regions. Each of the memory units corresponds to one of a couple of reference group bit values. The reference group bit array is for storing the reference group bit values of the memory units. Each of the reference group bit values corresponds to a set of reference currents. When sensing the memory units, the reference group bit values of the memory units are first obtained from the reference group bit array. The sets of reference currents corresponding to the memory units are generated. The memory cells of each of the memory units are then read according to the corresponding set of reference currents.

The invention achieves the above-identified object by providing a method for programming a memory. The memory including a number of memory units and a reference group bit array. Each of the memory units includes a couple of memory cells. The memory cells of the memory units have been programmed. The method includes: firstly, choose one of the memory units. Next, searching the boundary or peak of the distribution of the threshold voltages of the memory cells of the chosen memory unit. After that, select one reference group bit value from a couple of reference group bit values for the chosen memory unit according to the threshold voltage distribution regions, the selected reference group bit value is relative to a selected set of reference currents for reading the chosen memory unit. Then program the reference group bit value of the chosen memory unit into the reference group bit array. Next, check if the reference group bit values relative to the memory units are all programmed, if it is true, terminate the method, if it is false, choose another one of the memory units and repeating the method from the detecting step to the checking step.

The invention achieves the above-identified object by providing a method for reading a memory. The memory includes a number of memory units. Each of the memory units includes a number of memory cells. The method includes: Firstly, read a number of reference group bit values and saving the reference group bit values to a buffer memory. Each of the reference group bit values corresponds to one of the memory units. Next, choose one of the memory units. Afterward, read the reference group bit value corresponding to the chosen memory unit from the buffer memory. Next, generate a set of reference currents relative to the reference group bit value of the chosen memory unit. Then sensing the memory cells of the chosen memory unit by using the set of reference currents. Then, output data in the memory cells of the chosen memory unit. Finally, check if all of the memory units are sensed. If it is true, terminate the method. If it is false, choose another one of the memory units and repeat the method from the step of reading the reference group bit value to the checking step.

The invention achieves the above-identified object by providing a memory control circuit, used in a memory. The memory has a couple of memory units. Each memory unit has a couple of memory cells. The circuit includes a couple of reference current generators. Each of the reference current generators generates one reference current of a set of reference currents according to a reference group bit value. The set of reference currents is used for distinguishing a plurality of states of the memory cells when reading the corresponding memory unit. Each of the reference generators includes a power decoder, a voltage driver, and a reference cell. The power decoder receives the reference group bit value and outputs a reference power voltage according to the reference group bit value. The voltage driver receives the reference power voltage as power and outputs a reference voltage accordingly. The reference cell is controlled by the reference voltage and outputs one reference current of the set of reference currents accordingly.

The invention achieves the above-identified object by providing a memory control circuit, used in a memory. The memory has a couple of memory units. Each of the memory unit has a couple of memory cells. The circuit includes a couple of reference current generators. The set of reference current generators generates one reference current of a set of reference currents according to a reference group bit value. The set of reference currents is used for distinguishing a couple of states of the memory cells when reading the corresponding memory unit. Each of the reference current generators includes a reference group bit value decoder, a number of voltage drivers, and a number of reference cells. The reference group bit value decoder receives the reference group bit value. The voltage drivers are coupled to the reference group bit value decoder. Each of the reference cells is controlled by one of the voltage drivers. The reference group bit value decoder enables one of the voltage drivers according to the reference group bit value. The enabled voltage driver outputs a reference voltage to the corresponding reference cell. The corresponding reference cell then outputs the reference current accordingly.

DETAILED DESCRIPTION OF THE INVENTION

A memory structure according to an embodiment of the present invention includes a main array and a reference group bit array.FIG. 2is the memory structure according to an embodiment of the present invention. The memory structure200includes a main array201and a reference group bit array202. The main array201includes a number of memory units. Each of the memory units includes a number of memory cells. Each of the memory units corresponds to a reference group bit value. The reference group bit value for each memory unit is relative to a set of reference currents. The set of reference currents is for distinguishing the states of memory cells in the corresponding memory unit when reading the memory. The reference group bit array202is for storing the reference group bit values.

By dividing the main array into the memory units, the set of reference currents for each memory unit is respectively set according to the threshold voltage distribution of memory cells in each memory unit, such that the set of reference currents for each memory unit is suited for performing the sensing process for distinguishing states of memory cells of each memory unit.

FIG. 3Aillustrates an example of threshold voltage distribution diagram of a memory unit A of the memory units of the main array201.FIG. 3Billustrates an example of threshold voltage distribution diagram of a memory unit B of the memory units of the main array201. The threshold voltage distributions of the memory unit A and B respectively include a number of distribution regions.

The threshold voltage distribution of the memory unit A includes distribution regions301to304. The distribution regions301to304are respectively corresponding to, for example, states 11,01,00,10 of memory cells of the memory unit A. The memory unit A corresponds to a reference group bit value, for example, 001, which corresponds to a set of reference currents C1to C3. The set of reference currents C1to C3is relative to reference voltages V1to V3inFIG. 3A, which respectively fall in sensing windows between the distribution regions301to304, when performing the sensing process. The states of the memory A can therefore be distinguished properly by the set of reference currents C1to C3. Hence, the set of reference currents C1to C3relative to the reference group bit value 001, which is corresponding to the memory unit A, is suited for reading the memory unit A.

Similarly, the threshold voltage distribution of the memory unit B includes distribution regions305to308. The distribution regions305to308are respectively corresponding to states 11, 01, 00, 10 of memory cells of the memory unit B. The memory unit B corresponds to a reference group bit value, for example, 011, which corresponds to a set of reference currents C4to C6. The set of reference currents C4to C6are relative to reference voltages V4to V6inFIG. 3B, which respectively fall in sensing windows between the distribution regions305to308. The set of reference currents C4to C6relative to the reference group bit value 011, which is corresponding to the memory unit B, is therefore suited for reading the memory unit B. As mentioned above, the set of reference currents corresponding one reference group bit value is suited for the memory unit corresponding the reference group bit value.

The distributions of the memory units of the memory structure are usually not exactly the same. Therefore, a set of reference currents suited for each memory unit may not be the same. Each memory unit of the memory structure according to the embodiment of the present invention is provided with a reference group bit value, which indicates a set of reference currents suited for each memory unit. For example, the distributions of the memory unit A and B are not the same. If the reference currents C1to C3, which are used in the memory unit A, are used to distinguish the memory unit B, as shown inFIG. 3C, then a sensing error may occur. For example, the memory cells whose threshold voltages fall to the distribution region306′ inFIG. 3Cmay be sensed as 00, instead of correct 01, due to the wrong reference voltage V2corresponding to the wrong reference current C2.

The diversity of threshold voltages of the memory cells of the whole main array is larger than the diversity of threshold voltages of the memory cell of one of the memory units. Hence the sensing windows of the whole main array are narrower than the ones of one of the memory units. In the embodiment of the present invention, by dividing the main array into the memory units, the distribution regions of the threshold voltage distribution of each memory unit become more concentrated and therefore larger sensing windows between the distribution regions of each memory unit are obtained. For each memory unit it is easier to set reference currents to distinguish states of the memory cells of each memory unit. Each memory unit in the memory structure according to the embodiment has its own reference group bit value, which indicates the appropriate set of reference currents for each memory unit. All of the memory units in the memory structure according to the embodiment of the present invention can therefore be sensed correctly.

In the memory structure according to the embodiment, the reference group bit value of each memory unit is one of 8 reference group bit values 000, 001, 010, 011, 100, 101, 110, 111. Each of the reference group bit values 000 to 111 is relative to a set of reference currents. For example, the set of reference currents for sensing the memory unit A corresponds to the reference group bit value 001, while the reference group bit value of the memory unit A is 001.

However, the reference group bit value for each of the memory unit is not limited to be chosen from the eight 3-bit reference group bit values 000 to 111. The reference group bit value for each of the memory unit can be one of a number of predetermined reference group bit values. The reference group bit value for each of the memory units is decided such that the set of reference currents corresponding to the reference group bit value is appropriate for reading each of the memory unit. The amount of reference group bit value to be selected can be more or less. That is, the amount of sets of reference currents to be selected can be more or less.

The memory structure200according to the embodiment is a multi-level cell (MLC) memory structure. However, the memory structure of the present invention can also be a single-level cell (SLC) memory structure.

FIG. 4is the flowchart of programming method for the memory structure200according to the embodiment. In step410ofFIG. 4, firstly choose one of the memory units, for example, the memory unit A of the memory structure200. Take the memory unit A as an example to explain step420to460. Next, in step420, detect the threshold voltages of the memory cells of the chosen memory unit, that is, the memory unit A. And generate a threshold voltage distribution information of the memory unit A accordingly, that is, the distribution regions301to304inFIG. 3A. The low boundaries and high boundaries of the voltage distribution regions301to304of the memory unit A are then obtained.

In step430, select one reference group bit value from a number of reference group bit values for the chosen memory unit according to the threshold voltage distribution information. The selected reference group bit value is relative to a selected set of reference currents for reading the chosen memory unit. A set of reference currents, which is the most suited for reading the chosen memory unit among the sets of reference currents, is selected by performing this step.

In this example, by checking which one of the sets of selective reference currents is the most appropriate one according to the low and high boundaries of the distribution regions301to304, the reference group bit value 001 for the memory unit A is selected from the reference group bit value 000 to 111. That is, the most appropriate set of selective reference currents for the memory unit A corresponds to the reference group bit value 001, so the reference group bit value for memory A is chosen as 001.

Then, in step440, save the reference group bit value of the chosen memory unit into the buffer memory Next, in step450, check if the reference group bit values relative to the memory units are all programmed. If it is true, goes to step460. If it is false, choose another one of the memory units in step410and repeat the method to step450until the reference group bit values for all of the memory units are saved into the buffer memory.

Then, program the reference group bit value of the chosen memory unit into the reference group bit array202of the memory structure200in step460. In this example, the reference group bit value 001 of the memory unit A is programmed into the reference group bit array202.

FIG. 5is the flowchart of the reading method of a read-only-memory. The memory has the memory structure200inFIG. 2. Firstly, in step510, read all of the reference group bit values and save the reference group bit values to a buffer memory. The reference group bit value for each of the memory units corresponds to a set of reference currents, which is for reading the memory unit. Next, In step520, choose one of the memory units, for example, the memory unit A of the memory structure200. Then in step530, read the reference group bit value, for example, 001, corresponding to the chosen memory unit, that is, the memory unit A, from the buffer memory.

Next, in step540, generate a set of reference currents relative to the reference group bit value of the chosen memory unit. In this example, the set of reference currents C1to C3relative to the reference group bit value 001 is generated. Because the reference group bit value of the memory unit A is set as 001 in the programming process described before, the set of reference currents C1˜C3are generated as the set of selective reference currents corresponding to the selective bit value 001.

After that, sense the memory cells of the chosen memory unit, the memory unit A in this example, by using the set of reference currents in step550. In this example, the memory cells of the memory unit A are sensed with the set of reference currents C1to C3. The states of the memory cells of the memory unit A are distinguished with the set of reference currents C1to C3. Next, in step560, outputting data of the chosen memory unit, the memory unit A in this example. Afterward, check if all of the memory units are sensed In step570. If it is true, in step580, terminate the reading method. If it is false, the method is repeated from step520to sense other memory units in the main array of the memory structure200until all of the memory units are sensed.

FIG. 6Ais an example of a memory control circuit. The memory control circuit600inFIG. 6Ais used for generating a set of reference currents Ca, Cb and Cc according to an inputted reference group bit value RGB, which is one of the reference group bit values 000 to 111 in the embodiment. InFIG. 6A, a memory control circuit600includes reference current generators610to630. The reference current generators610to630generate reference currents Ca, Cb and Cc respectively according to the reference group bit value RGB. Take the memory unit A of the memory structure200inFIG. 2as example to explain the operation of the memory circuit. The memory unit A corresponds to the reference group bit 001, which corresponds to the set of reference currents, e.g. 8 μA, 18 μA and 28 μA. When the reference current generators610receives the reference group bit value RGB as 001, the reference current Ca generated by the reference current generators610is then 8 μA. Similarly, the reference currents Cb and Cc generated by the reference current generators620and630are 18 μA and 28 μA respectively, when the reference current generators620and630receive the reference group bit value RGB as 001.

FIG. 6Bis an example of the detail circuit diagram of the reference current generators610to630of the memory control circuit600. The reference current generator610includes a power decoder641, a voltage driver651, and a reference cell661. The power decoder641is for decoding the reference group bit value RGB and generating a power voltage Vp1accordingly. The voltage driver651receives the power voltage Vp1as power and generates a reference voltage Vr1accordingly. The reference cell661, e.g. a NMOS, is controlled by the voltage driver651and receives the reference voltage Vr1. In the reference current generator611, the reference current Ca corresponding to the reference voltage Vr1is generated at the source of the reference cell661. In this example, the reference current Ca is generated as 8 μA, when the reference group bit value RGB is 001.

Similarly, the reference current generator620includes a power decoder642, a voltage driver652, and a reference cell662. The power decoder642generates a power voltage Vp2according to the reference group bit value RGB. The voltage driver652generates a reference voltage Vr2according to the power voltage Vp2. The reference cell662receives the reference voltage Vr2and generates the reference current Cb at the source.

Similarly, the reference current generator630includes a power decoder643, a voltage driver653, and a reference cell663. The power decoder643generates a power voltage Vp3according to the reference group bit value RGB. The voltage driver653generates a reference voltage Vr3according to the power voltage Vp3. The reference cell663receives the reference voltage Vr3and generates the reference current Cc accordingly.

The power voltages Vp1, Vp2and Vp3in the reference current generators610to630corresponding to the reference group bit value RGB can be designed to be the same or different. No matter the power voltages Vp1to Vp3are the same or different, the reference currents Ca, Cb and Cc corresponding to the inputted reference group bit value RGB are different.

FIG. 7Aillustrates an example of the relationships between the power voltages Vp1to Vp3and the reference currents Ca to Cc corresponding to the reference group bit value RGB inFIG. 6B. Take the reference group bit value RGB as 001 as an example. When the reference group bit value RGB is 001, the set of reference currents Ca, Cb and Cc are respectively 8 μA, 18 μA and 28 μA. The power voltages Vp1to Vp3in the reference current generators610to630can be designed all as 4.8V. Therefore, the threshold voltages of the reference cells661to663in the reference current generators610to630are then respectively designed to satisfy the condition.

The power voltages Vp1to Vp3in the reference current generators610to630inFIG. 6Bcan also be designed to be different.FIG. 7Billustrates another example of the relationships between the power voltages Vp1to Vp3and the reference currents Ca to Cc corresponding to the reference group bit value RGB. Again, take the reference group bit value RGB as 001 as an example, the same set of reference currents Ca, Cb, Cc corresponds to the reference group bit value 001 are still 8 μA, 18 μA, 28 μA. The power voltages Vp1to Vp3can be designed as 4.8V, 4.9V, and 4.95V respectively. The threshold voltages of the reference cells661to663in the reference current generators610to630can be designed to achieve this goal. The threshold voltages of the reference cells660can be designed even to be the same to meet this constraint.

The power voltages Vp1to Vp3in the reference current generators610to630corresponding to an inputted reference group bit value can be designed to be the same or different. Whether the power voltages Vp1to Vp3are the same or not, the threshold voltages of the reference cells661to663inFIG. 6Bare designed for generating a set of reference currents corresponding to the inputted reference group bit value.

FIG. 6Cis another example of the detail circuit diagram of one of the reference current generators610to630of the memory control circuit600. Each of the reference current generators610to630includes a reference group bit decoder670, voltage dividers681to688, reference cells691to698in this example.

The reference group bit decoder670receives the reference group bit value RGB inFIG. 6C, which is one of the reference group bit values 000 to 111, and generates one of enable signals Se1to Se8accordingly. The voltage driver681to688all receives a power voltage Vp4as power. The enable signals Se1to Se8are respectively outputted when the inputted reference group bit value is 000 to 111.

The reference cells691to698are, for instance, NMOSs. The voltage drivers681to688are respectively enabled by the enable signals Se1to Se8. The reference cells691to698are respectively controlled by the voltage drivers681to688. An enabled voltage driver outputs a reference voltage to the gate of a corresponding reference cell and turns on the corresponding reference cell. The corresponding reference cell then outputs a reference current corresponding to the reference group bit value.

Take the reference current generator610as an example to explain the operation of the reference current generator inFIG. 6C. The reference current Ca is generated by the reference current generator610inFIG. 6Caccording to the reference group bit value RGB. When the reference group bit value RGB is 001, the enable signal Se2corresponding to the reference group bit value 001 enables the voltage driver682. The enabled voltage driver682then outputs a reference voltage Vx to the reference cell692. The reference current Ca corresponding to the reference group bit value 001 is then generated at the drain of the reference cell692.

The voltage drivers681to688of the reference current generator610all receive a voltage power Vp4as power. The reference voltages outputted by the voltage drivers681to688are therefore the same. So the threshold voltages of the reference cell691to698must be different, for generating different reference currents when the reference group bit value RGB varies from 000 to 111.FIG. 8is an example of the timing diagram of reference current in the memory control circuit600according to the embodiment of the present invention. The reference current generators610,620and630can be the reference current generators inFIG. 6BorFIG. 6C. HereFIG. 6Bis taken as example to explain the timing diagram. The horizontal axis and vertical axis ofFIG. 8are time and reference current value respectively. The waveform801stands for the sensing cycle. The waveform802represents the level of reference current.

The time interval811is the first sensing cycle. In the time interval811, a reference group bit value is sensed and saved into a buffer memory when the waveform801is high. A memory unit corresponding to the reference group bit value is then sensed with the reference group bit value. The first reference cell, e.g. the reference cell661inFIG. 6B, generates the reference current during the time interval812. The waveform802during the time interval812represents the reference current generated by the first reference cell. The level of the waveform802in the time interval812is L1.

Similarly, the waveform802during the time interval813represents the reference current generated by updating the RGB value The level of the waveform802in the time interval813is L2. The waveform802during the time interval814represents the reference current generated by updating the RGB value The level of the waveform802in the time interval814is L3.

The memory control circuit600in the embodiment has three reference current generators610,620and630. The reference current generators610to630have three reference cells651,652and653for generating three reference currents for each memory unit of the main array201of the memory structure200.FIG. 9Aillustrates the relationship of the main array201and the reference cells651,652and653. However, the memory control circuit can be designed to have six or other amount of reference cells.

FIG. 9Bis another example of the relationship of the main array201and reference cells. The main array201is divided into two half arrays920and930. Each half array has three reference cells for generating a set of reference currents. The reference cells921,922and923are for generating a set of reference currents for each memory units of the half array920. When reading one memory unit of the half array920, the reference cells921to923generate a set of reference currents according to a reference group bit value of the memory unit. The reference cells921,922and923are for generating a set of reference currents for each memory units of the half array920. Similarly, when reading one memory unit of the half array930, the reference cells931to933generate a set of reference currents according to a reference group bit value of the memory unit. The main array201can be divided into more parts and therefore more reference cells are needed.

The memory cells of memory structure200according to the embodiment of the present invention can be single-level cell (SLC) memory. When the memory cells of memory structure200are single-level cells, the threshold voltage distribution of each memory unit in the memory structure has 2 distribution regions, which are relative to 2 states of memory cells of each memory unit respectively. So a set of reference currents including 1 reference currents is needed to distinguish the 2 states of memory cells of each memory unit. A memory control circuit hence needs 1 reference current generators. The memory cells of memory structure200can be N-level cells. N is an integer larger than 1. The set of the reference currents may include a different amount of reference currents. The memory control circuit therefore needs a different amount of reference currents.

The 8 reference group bit values 000 to 111 are used in the memory structure according to the embodiment of the present invention. Each of reference group bit values corresponds to a set of selective reference currents. However, it is not limited to use the eight reference group bit values.

The main array of the memory structure of the present invention is divided into a number of memory units. The diversity of the threshold voltages of the memory cells of each memory unit is reduced. The ranges of the threshold voltage distribution regions of each memory unit therefore become narrower. Larger sensing windows between the voltage distribution regions are obtained. The sensing error is hence reduced.

The most suited set of reference currents for each memory cell is recorded by storing the reference group bit value for each memory unit. Hence, each of the memory units can be sensed by the most appropriate set of reference currents, although the threshold voltage distributions of the memory units are different. Thus the improvement of sensing accuracy is therefore achieved.