Voltage detector

A voltage detector includes a first input terminal, a second input terminal, a first voltage detection circuit, a second voltage detection circuit, and a logic holder circuit. The first input terminal receives a first input voltage. The second input terminal receives a second input voltage. The first voltage detection circuit outputs a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage. The second voltage detection circuit outputs a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage. The logic holder circuit retains the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a voltage detector for power supply voltage, and more particularly, to a voltage detector for use in power-on-reset (POR) circuitry that generates a reset signal to initialize circuit components upon detecting a power supply voltage rising to a given set point during power-up, which may be implemented on a semiconductor integrated circuit for incorporation into various electronic devices, such as mobile phones and laptop computers.

2. Description of the Background Art

Voltage detectors are employed in power-on-reset (POR) circuitry to generate a reset signal upon detecting a power supply voltage rising to a given set point during power-up, which initializes electrical components, such as flip-flops, latches, counters, registers, etc., forming a central processing unit (CPU) of the system. Typically, a POR circuit with voltage detection capabilities is implemented on a semiconductor integrated circuit for incorporation into various electronic devices, such as mobile phones and laptop computers.

FIG. 1is a circuit diagram schematically illustrating a conventional voltage detector104.

As shown inFIG. 1, the voltage detector104includes an input terminal to receive an input voltage VIN, a power supply terminal to receive a power supply voltage VDD1, and an output terminal to output an output signal DOUT, as well as a step-down voltage regulator103, a voltage detection circuit101, and output circuitry formed of a pair of first and second, constant current sources115and117, a pair of first and second output transistors116and118, each being an N-channel metal-oxide semiconductor (NMOS) device, and an inverter or logic NOT gate131.

In the voltage detector104, the step-down voltage regulator103is connected to the power supply terminal to convert the power supply voltage VDD1into a lower, regulated supply voltage VDD2for supply to the voltage detection circuit101and the output circuitry.

The voltage detection circuit101includes a set of voltage divider resistors111through113connected in series between the input terminal and ground to output a sense voltage VINS at a node between the resistors111and112proportional to the input voltage VIN, and an NMOS transistor switch130connected in parallel with the grounded resistor113. Also included are a reference voltage generator114to generate a reference voltage Vref based on the power supply voltage VDD1, and a comparator110that receives the sense voltage VINS at an inverting input thereof and the reference voltage Vref at a non-inverting input thereof to generate a result of comparison between the input voltages VINS and Vref for output to the gate terminal of the transistor116.

In the output circuit, the first constant current source115and the first output transistor116are connected in series between the supply voltage VDD2and ground, with a node therebetween connected to the gate terminal of the transistor118. The second constant current source117and the second output transistor118are connected in series between the supply voltage VDD2and ground, with a node therebetween connected to the input terminal of the inverter131. The output of the inverter131constitutes the output terminal of the voltage detector104.

During operation, the voltage detector104outputs a reset signal or pulse DOUT when the input voltage VIN rises to a sufficient level for initialization during power-on, wherein the voltage detection circuit101monitors the input voltage VIN to cause the comparator110to switch its logic state whenever the input voltage VIN reaches a set point voltage Vdet, which is relatively high (“reset threshold Vdet+”) where the voltage VIN rises from a lower level, and relatively low (“detection threshold Vdet−”) where the voltage VIN falls from a higher level.

A problem encountered by the conventional voltage detector104is that it can incorrectly output a reset signal DOUT where the input voltage VIN does not reach the reset threshold Vdet+ during power-on. To illustrate the problem, consider a situation where the input voltage VIN rises to a level between the detection voltage Vdet− and the reset voltage Vdet+ prior to the power supply voltage VDD1rising to a level sufficient to activate the detection circuit101powered with the regulated supply voltage VDD2.

In such cases, the voltage divider resistors111through113generate a sense voltage VINS from the input voltage VIN before the reference voltage generator114generates a reference voltage Vref from the supply voltage VDD1. The comparator110, receiving the relatively high inverting input VINS and the relatively low non-inverting input Vref upon activation, outputs a logic low signal. The detection signal thus generated turns off the transistor116to in turn cause the transistor118to turn on and then the transistor130to turn off, resulting in the voltage detector104incorrectly outputting a reset pulse DOUT where the reset threshold Vdet+ has not been reached during power-on.

Hence, for proper operation of the voltage detector104, the power supply voltage VDD1for activating the comparator110is required to reach a specified level before the voltage divider circuit outputs the sense voltage VINS by dividing the input voltage VIN. Such requirement limits the availability of the voltage detector104, making the conventional method less practical than otherwise expected.

To date, several other conventional methods have been proposed to provide an effective voltage detector for detecting a power supply voltage to generate a reset signal.

For example, one conventional method provides a voltage detector that detects an input voltage based on a hysteresis comparator provided with a reset threshold Vdet+ and a detection threshold Vdet−, the former being higher than the latter by a given threshold voltage. The hysteresis comparator is equipped with a hysteresis voltage controller that periodically reduces the hysteresis voltage during power-on, so as to enable the comparator to output a reset pulse when the input voltage exceeds the detection threshold Vdet− but does not yet reach the reset threshold Vdet+. Once the initial reset pulse is released, the hysteresis voltage controller returns the hysteresis voltage to the original level so that the comparator no longer outputs a reset pulse unless the reset threshold Vdet+ is reached.

According to this method, the voltage detector can generate a reset signal when the input voltage reaches the relatively low threshold Vdet− instead of the relatively high threshold Vdet+ during power-on. Such capability may be used to remove variability from a reset signal that can be occasionally released whether the input voltage reaches a detection threshold Vdet− or a reset threshold Vdet+ depending on the rising edge or other characteristics of the input voltage during power-on. However, the method can cause incoherence in the system and therefore is not reasonably practical, considering that a reset signal is required to indicate whenever the reset threshold Vdet+ is reached regardless of whether it is output during or after power-on, so as to serve its intended purposes.

Another conventional method provides a voltage detector that generates a primary detection signal upon detecting a power supply voltage falling below a given detection threshold through a primary detection circuit employing a bandgap reference (BGR) circuit for reference voltage generation. The BGR-based primary detection circuit is used in combination with a secondary detection circuit formed of a series circuit composed of a resistor and a MOS transistor, which retains the logic state of the primary detection signal upon detecting the power supply voltage falling below a setpoint voltage lower than the threshold voltage.

Such dual-detector circuitry is designed to address a problem encountered when using a BGR voltage in voltage detection, wherein the BGR circuit, when supplied with a low power supply voltage, outputs an unstable reference voltage which is repeatedly reached by a monitored voltage, resulting in unreliable operation of the BGR-based voltage detector. According to this method, provision of the secondary detection circuit periodically invalidates the primary detection circuit where the BGR circuit is unstable, thereby ensuring the voltage detector reliably operates with lower supply voltages.

Although effective for its intended purposes, the conventional voltage detector fails to work properly when used in high-voltage applications where a step-down voltage regulator renders a power supply voltage into a lower, regulated voltage. That is, the voltage detector can improperly switch its output signal as the secondary detection circuit detects the regulated power supply voltage transiently falling below the setpoint voltage due to variations in the power supply voltage even though the power supply voltage still remains above the threshold voltage.

BRIEF SUMMARY

This disclosure describes an improved voltage detector.

In one aspect of the disclosure, the improved voltage detector includes a first input terminal, a second input terminal, a first voltage detection circuit, a second voltage detection circuit, and a logic holder circuit. The first input terminal receives a first input voltage. The second input terminal receives a second input voltage. The first voltage detection circuit is connected to the first input terminal to output a first detection signal that switches a logic state thereof when the first input voltage falls below a first detection voltage. The second voltage detection circuit is connected to the second input terminal to output a second detection signal that switches a logic state thereof when the second input voltage falls below a second detection voltage. The second detection voltage is lower than the first detection voltage and higher than a minimum operating voltage of the first voltage detection circuit. The logic holder circuit has an input thereof connected to the second voltage detection circuit and an output thereof connected to the first voltage detection circuit to retain the logic state of the first detection signal when the second detection signal indicates that the second input voltage is below the second detection voltage.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, examples and exemplary embodiments of this disclosure are described.

FIG. 2is a circuit diagram schematically illustrating a voltage detector4according to a first embodiment of this patent specification.

As shown inFIG. 2, the voltage detector4includes a power supply terminal to receive a power supply voltage VDD1from an external power source, an input terminal to receive an input voltage VIN from external circuitry, and an output terminal to transmit an output signal DOUT to external circuitry, as well as a step-down voltage regulator3, a first voltage detection circuit1, a second voltage detection circuit2, and output circuitry formed of a pair of first and second, constant current sources15and17, a pair of first and second, output transistors16and18, a logic holder transistor19, and an inverter or logic NOT gate31.

The first voltage detection circuit1includes a comparator10, a set of voltage divider resistors11through13, and a switch transistor30. The second voltage detection circuit2includes a detector transistor21and a resistor22. The transistors recited herein are all N-channel metal-oxide-semiconductor (NMOS) devices each having a gate, source, and drain terminals.

All the components of the voltage detector4may be integrally formed on a single integrated circuit (IC) for incorporation into various electronic devices, such as mobile phones and laptop computers, in which case the input and output terminals may be coupled to external circuits located either inside or outside the IC on which the detector4is implemented.

In the voltage detector4, the step-down voltage regulator3is connected to the power supply terminal to render the power supply voltage VDD1into a lower, regulated voltage VDD2for output to the first and second voltage detection circuits1and2, and the output circuitry.

In the first voltage detector1, the voltage divider resistors11through13are connected in series between the input terminal and ground to form a node between the resistors11and12to output a sense voltage VINS proportional to the input voltage VIN. The switch transistor30is connected in parallel with the grounded resistor13. The reference voltage generator14generates a first reference voltage Vref1based on the regulated supply voltage VDD2. The comparator10has an inverting input thereof connected to the node between the resistors11and12and a non-inverting input thereof connected to the output of the reference voltage generator14to compare the sense voltage VINS against the first reference voltage Vref1so as to output a first detection signal DOUT1at an output thereof.

In the second voltage detection circuit2, the resistor22and the detector transistor21are connected in series between the regulator output and ground to form a voltage divider that outputs a second detection signal DOUT2at an output node therebetween.

In the output circuitry, the first constant current source15and the first output transistor16are connected in series between the regulator output and ground, with a node therebetween connected to the gate terminal of the transistor18. The second constant current source17and the second output transistor18are connected in series between the regulator output and ground, with a node therebetween connected to the gate terminal of the transistor30and the input of the inverter31, respectively. The logic holder transistor19is connected between the gate of the transistor18and ground, with its gate terminal connected to the output of the second voltage detection circuit2. The output of the inverter31constitutes the output terminal of the voltage detector4.

During operation, the first voltage detection circuit1outputs the first detection signal DOUT1at the output of the comparator10as a result of comparison between the sense voltage VINS and the reference voltage Vref1, which switches a logic state thereof when the input voltage VIN falls below a first detection voltage Vdet1.

The second voltage detection circuit2outputs the second detection signal DOUT2at the node between the resistor22and the transistor21, which switches a logic state thereof when the supply voltage VDD2falls below a second detection voltage Vdet2.

The output circuitry generates the output signal DOUT according to the first and second detection signals DOUT1and DOUT2, wherein the logic holder transistor19retains the logic state of the first detection signal DOUT1when the second detection signal DOUT2indicates that the voltage VDD2is below the second detection voltage Vdet2.

The output signal DOUT thus obtained may act as a power-on-reset (POR) signal to indicate when the input voltage VIN rises to a reset voltage Vdet+ during power-on, according to which the system supplied with the voltage VIN can initialize or reset its circuit components, such as flip-flops, latches, counters, and various types of registers, forming a central processing unit (CPU).

FIG. 3Ais a circuit diagram of the second voltage detection circuit2shown with its input terminal connected to a gradually increasing input voltage V2to measure a resulting output voltage V1, andFIG. 3Bis a graph showing a relation between the input and output voltages V1and V2of the second voltage detection circuit2obtained through measurement.

As shown inFIG. 3B, the output voltage V1substantially equals the input voltage V2, as long as the input voltage V2remains below a threshold voltage Vth of the NMOS transistor21, causing the transistor21to shut off. When the input voltage V2reaches the threshold voltage Vth to cause the transistor21to turn on, the output voltage V1sharply declines to a level substantially lower than the input voltage V2. Thus, the second voltage detection circuit2outputs a logic high when the input voltage V2is lower than the threshold voltage Vth, and a logic low when the input voltage V2is higher than the threshold voltage Vth.

In the voltage detector4, the second detection voltage Vdet2is set to the threshold voltage Vth of the NMOS transistor21. The NMOS transistor21is scaled so that the second detection voltage Vdet2is lower than the first detection voltage Vdet1and higher than a minimum operating voltage of the first voltage detection circuit1. The second voltage detection circuit2, formed of the series circuit composed of the resistor22and the transistor21, can operate at voltages lower than those at which the first voltage detection circuit1operates. Accordingly, the second voltage detection circuit2starts operation before the first voltage detection circuit1is activated upon power-on, and switches its output DOUT2after activation of the first voltage detection circuit1.

Referring back toFIG. 2, now consider cases where the input voltage VIN rises to a certain operating voltage lower than the reset voltage Vdet+upon power-on, before the power supply voltage VDD1gradually increases to cause a corresponding increase in the regulated supply voltage VDD2.

In such cases, the second voltage detection circuit2, which starts operation prior to activation of the first voltage detection circuit1, initially outputs a logic high DOUT2(the amplitude of which depends on the supply voltage VDD2) for input to the logic holder transistor19. With the input signal DOUT2being high, the NMOS transistor19conducts current to cause the NMOS transistor18to shut off.

With the transistor18being nonconductive, the voltage at the gate of the transistor30is high when the supply voltage VDD2gradually increases to activate the first voltage detection circuit1as well as the constant current sources15and17of the output circuitry. This maintains the sense voltage VINS below the reference voltage Vref1as the reference voltage generator14is completely activated. Then, the comparator10, receiving the relatively low inverting input VINS and the relatively high non-inverting input Vref1, outputs a logic high DOUT1to cause the NMOS transistor16to conduct. With the transistors16and19both remaining on, the transistor18remains off so that the inverter31outputs a logic low DOUT.

Then, after activation of the first voltage detection circuit1, the supply voltage VDD2rises to exceed the second detection voltage Vdet2. This causes the second voltage detection circuit2to switch its output DOUT2from high to low, so that the transistor19shuts off. At this point, the output DOUT of the voltage detector4remains low as long as the transistor16remains conductive to keep the transistor18shut off.

Hence, the voltage detector4does not output an incorrect reset signal during power-on even where the input voltage VIN rises to an operating point prior to the power supply voltage VDD1, owing to the logic holder transistor19holding on the switch transistor30upon activation of the first voltage detection circuit1to retain the logic state of the first detection signal DOUT1. With this logic holding capability, the voltage detection circuit is not required to activate the comparator prior to the voltage divider outputting the voltage proportional to the monitored voltage, leading to broad practical applicability of the voltage detector4according to this patent specification.

FIG. 4is a circuit diagram schematically illustrating a voltage detector4aaccording to a second embodiment of this patent specification.

As shown inFIG. 4, the overall configuration of the second embodiment is similar to that depicted inFIG. 2, except that the voltage detector4aincludes, in place of the series circuit composed of the resistor22and the transistor21, a second voltage detection circuit2aformed of a pair of voltage divider resistors21aand22a, a reference voltage generator24a, and a comparator20a, as well as a series circuit composed of a constant current source25and an NMOS transistor26.

Specifically, in the second voltage detection circuit2a, the resistors21aand22aare connected in series between the regulator output and ground to output a sense voltage VDD2S at a node therebetween proportional to the regulated supply voltage VDD2. The reference voltage generator24agenerates a second reference voltage Vref2. The comparator20ahas a non-inverting input thereof connected to the node between the resistors21aand22a, and an inverting input thereof connected to the reference voltage generator24ato output a result of comparison between the input voltages VDD2S and Vref2to the gate terminal of the transistor26. The constant current source25and the transistor26are connected in series between the regulator output and ground to output a second detection signal DOUT2at a node therebetween for input to the gate terminal of the transistor19.

In such a configuration, the voltage detector4aoperates in a manner similar to that depicted primarily with reference toFIG. 2, wherein the second voltage detection circuit2aprovides the detection signal DOUT2that causes the logic holder transistor19to hold on the switch transistor30upon activation of the first voltage detection circuit1.

FIG. 5is a circuit diagram schematically illustrating a voltage detector4baccording to a third embodiment of this patent specification.

As shown inFIG. 5, the overall configuration of the third embodiment is similar to that depicted inFIG. 2, except that the voltage detector4bhas no step-down voltage regulator3to generate the lower regulated voltage VDD2, so that the first and second voltage detection circuits1and2and the output circuitry operate with the power supply voltage VDD1supplied from an external power source.

In such a configuration, the voltage detector4boperates in a manner similar to that depicted primarily with reference toFIG. 2, wherein the second voltage detection circuit2provides the detection signal DOUT2, which, in this embodiment after modification through a series circuit composed of a pair of inverters23and24, causes the logic holder transistor19to hold on the switch transistor30upon activation of the first voltage detection circuit1.

FIG. 6is a circuit diagram schematically illustrating a voltage detector4caccording to a fourth embodiment of this patent specification.

As shown inFIG. 6, the overall configuration of the fourth embodiment is similar to that depicted inFIG. 2, except that the voltage detector4cincludes a third voltage detection circuit5as well as a set of inverters23,24,53,57, and59, and a pair of logic NAND gates56and58, which together form a control circuit50cconnected between the second voltage detection circuit2and the logic holder transistor19.

Specifically, in the control circuit50c, the third voltage detection circuit5is formed of a resistor52and a switch transistor51connected in series between the regulator output and ground to output a third detection signal DOUT3at a node therebetween. The NAND gate56has one input connected to the output of the third voltage detection circuit5through the inverter53, and the other input connected to the output of the first voltage detection circuit1. The NAND gate58has one input connected to the output of the NAND gate56through the inverter57, and the other input connected to the output of the second voltage detection circuit2through the inverters23and24connected in series. The output of the NAND gate58is connected to the gate terminal of the logic holder transistor19through the inverter59.

The third voltage detection circuit5operates in a manner similar to that of the second voltage detection circuit2, with its detection and reset threshold voltages both equal to or greater than the minimum operating voltage of the first voltage detection circuit1and equal to or smaller than the second detection voltage Vdet2.

In such a configuration, the control circuit50cenables the logic holder transistor19by validating the second detection signal DOUT2when the power supply voltage remains below the minimum operating voltage of the first voltage detection circuit1, and disables the logic holder transistor19by invalidating the second detection signal DOUT2when the first detection signal DOUT1indicates that the input voltage VIN reaches the first detection voltage Vdet1to assert a reset signal.

Such control circuit50cserves to prevent the second detection signal DOUT2from acting on the logic holder transistor19where the first voltage detection circuit1operates in a detection mode, i.e., during a period of time between when the input voltage VIN rises to an operating voltage and when the power supply voltage VDD1rises to the minimum operating voltage of the voltage detector4. This arrangement prevents the voltage detector4from incorrectly deasserting a reset signal where the supply voltage VDD2transiently falls below the second detection voltage Vdet2due to variations in the power supply voltage VDD1supplied from an external power source.

FIG. 7is a circuit diagram schematically illustrating an example of the step-down voltage regulator3for generating the supply voltage VDD2.

As shown inFIG. 7, the regulator7may be configured as a simple linear regulator, consisting of an output, P-channel metal-oxide semiconductor (PMOS) transistor P1connected between the regulator input and output terminals; a pair of resistors R1and R2connected between the output terminal and ground; a reference voltage generator generating a reference voltage Vref; and a comparator C1having a non-inverting input thereof connected to a node between the resistors R1and R2, an inverting input thereof connected to the reference voltage output, and an output thereof connected to the gate terminal of the output transistor P1.

During operation, the step-down voltage regulator3converts an input voltage VDD1input to the input terminal to an output voltage VDD2for output to the output terminal by regulating current flow through the output transistor P1. Such voltage regulation is well known in the art, a further description of which is omitted for brevity.

FIG. 8is a time chart showing the input and output voltages VDD1and VDD2of the voltage regulator3depicted above, in which the input voltage VDD1varies due to external factors outside the detector circuitry.

As shown inFIG. 8, the input voltage VDD1sharply declines to cause a corresponding variation in the output voltage VDD2. This causes the output voltage VDD2to transiently fall below the second detection voltage Vdet2even where the input voltage VDD1remains above the first detection voltage Vdet1.

If not corrected, the transient variation in the supply voltage VDD2would cause the transistor19to turn on to incorrectly deassert a reset signal where the power supply voltage VDD1is above the first detection voltage Vdet1. In the voltage detector4c, such failure upon variations in the power supply voltage VDD1is prevented by the control circuit50c, which disables the logic holder transistor19when the first detection circuit1asserts a reset signal. Provision of the control circuit50cthus ensures the voltage detector4properly operates in high-voltage applications that involve step-down voltage regulation.

FIG. 9is a circuit diagram schematically illustrating a voltage detector4daccording to a fifth embodiment of this patent specification.

As shown inFIG. 9, the overall configuration of the fifth embodiment is similar to that depicted inFIG. 2, except that the voltage detector4dincludes a pair of first and second one-shot (OS) generators43and44and an RS flip-flop (RS-FF)45, as well as inverters23,24,57, and59, and a pair of logic NAND gates56and58, which together form a control circuit50dconnected between the second voltage detection circuit2and the logic holder transistor19.

Specifically, in the control circuit50d, the first OS generator43has an input connected to the voltage VDD2and an output connected to an S input of the RS-FF45. The second OS generator44has an input connected to the output of the first voltage detection circuit1and an output connected to an R input of the RS-FF45. The NAND gate56has one input connected to a Q output of the RE-FF45, and the other input connected to the output of the first voltage detection circuit1. The NAND gate58has one input connected to the output of the NAND gate56through the inverter57, and the other input connected to the output of the second voltage detection circuit2through the inverters23and24connected in series. The output of the NAND gate58is connected to the gate terminal of the logic holder transistor19through the inverter59.

During operation, the first OS generator43generates a single electrical pulse for input to the RS-FF45as the supply voltage VDD2rises to an operating voltage. The second OS generator44generates a single electrical pulse for input to the RS-FF45when the output of the first voltage detection circuit1goes from high to low to assert a reset signal.

In such a configuration, the control circuit50dinitially enables the logic holder transistor19by validating the second detection signal DOUT2until the power supply voltage exceeds the minimum operating voltage of the first voltage detection circuit1, and to subsequently disable the logic holder transistor19by invalidating the second detection signal DOUT2once the first detection signal DOUT1indicates that the input voltage VIN reaches the first detection voltage Vdet1to assert a reset signal.

Such control circuit50dserves to prevent the second detection signal DOUT2from acting on the logic holder transistor19once the first detection circuit1initially switches its output signal DOUT1after the power supply voltage VDD2rises to the operating voltage. This arrangement prevents the voltage detector4from incorrectly deasserting a reset signal where the supply voltage VDD2transiently falls below the second detection voltage Vdet2due to variations in the power supply voltage VDD1supplied from an external power source.

FIG. 10is a circuit diagram schematically illustrating a voltage detector4eaccording to a sixth embodiment of this patent specification.

As shown inFIG. 10, the overall configuration of the sixth embodiment is similar to that depicted inFIG. 2, except that the voltage detector4eincludes a pair of inverters23and24, and a delay circuit60connected in series between the output of the second voltage detection circuit2and the gate terminal of the logic holder transistor19.

With additional reference toFIG. 11, which is a circuit diagram schematically illustrating an example of the delay circuit60used in the voltage detector4e, the delay circuit60is shown consisting of an NMOS transistor61and a resistor62connected in series between the power supply voltage and ground, a capacitor63connected in parallel with the transistor61, and a PMOS transistor64and an NMOS transistor65connected in series between the power supply voltage and ground, with their common drain connected to a drain terminal of the transistor61. The delay circuit60has its input IN connected to the gate terminal of the transistor61, and its output OUT connected to the node between the transistors64and65.

In such a configuration, the delay circuit60provides a delay time between when the second detection signal DOUT2switches the logic state thereof and when the logic holder transistor19retains the logic state of the first detection signal DOUT1.

Such delay circuit60serves to prevent the second detection signal DOUT2from acting on the logic holder transistor19where the supply voltage VDD2periodically falls below the second detection voltage Vdet2to cause the second voltage detection circuit2to switch its output signal DOUT2, but immediately resumes its original level within the delay time provided by the delay circuit60. This arrangement prevents the voltage detector4from incorrectly deasserting a reset signal where the supply voltage VDD2transiently falls below the second detection voltage Vdet2due to variations in the power supply voltage VDD1supplied from an external power source.

This patent specification is based on Japanese patent application No. 2009-264914 filed on Nov. 20, 2009 in the Japanese Patent Office, the entire contents of which are hereby incorporated by reference herein.