Full and empty flag generator for synchronous FIFOS

The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

FIELD OF THE INVENTION 
This invention relates to FIFO buffers generally and more particularly to 
an asynchronous state machine design to generate full and empty flags in 
synchronous FIFO buffers. 
BACKGROUND OF THE INVENTION 
It is well known to construct a synchronous first-in first-out (FIFO) 
buffer including logic indicating when the FIFO is full or empty. In a 
typical synchronous FIFO full and empty status flags are updated by a 
single clock, either a read clock or a write clock. The logic to generate 
the full and empty flags typically consists of counters, adders, 
combinatorial logic to generate a so called internal full-1(empty+1)flag 
and a final output register. An alternate way to generate the internal 
full flag is by directly decoding the counter outputs using combinatorial 
logic. The register is typically a master-slave register. The register 
architecture may use both the look-ahead internal flag (full-1 or empty+1) 
and the non look-ahead internal flag (full or empty) or just the internal 
look-ahead flag. The register architectures which use both look-ahead and 
non look-ahead flags are simple, whereas the architectures which use only 
one internal flag have a complex resetting mechanism of the master-slave 
after the first read or the first write. Typically the full or empty flag 
is updated by the write or read clock. 
The minimum delay between the clocks is defined as a tSKEW delay. The 
updating clock, either the write or read clock, is guaranteed to recognize 
the second clock, either the read or write clock, if it occurs at least 
tSKEW delay ahead of the updation clock. If the second (read) clock occurs 
within tSKEW time from the updation clock (write), the updation clock may 
or may not recognize the second clock. 
In a counter/adder decode method there are two counters, one each for the 
read and write clocks. These two counters are reset to zero upon master 
reset and are incremented based only on their respective clocks. The 
outputs of these counters are fed into a subtractor that perform 
Wcount-Rcount, or the difference between the number of locations written 
and the number of locations read. This difference is then fed into 
combinatorial logic to determine if the FIFO is full or full-1 (empty or 
empty+1). The combinatorial logic output is used as the input to the 
D-register which is clocked by the appropriate external clock. 
Another method, called the direct decode method, uses the counters just 
like the counter/adder method. Instead of having a subtractor on the 
outputs, combinatorial logic is used to decode when the FIFO is full. This 
is done by taking the exclusive-OR (XOR) of the Wcount and the Rcount. 
This combinatorial logic can be arrived at by generating the truth table 
for the full (empty) flag with respect to the Wcount and Rcount input 
variables. This direct decode method greatly reduces the amount of logic 
required to generate an internal full status flag and improves the tSKEW 
delay. 
The output register architectures which make use of both the look-ahead and 
non look-ahead internal flags are simple. These architectures have a 
multiplexer that is used to select either the free running clock or the 
enable clock. This selection is done by the output of the slave register. 
The other alternate register implementation is accomplished exclusively 
with the internal look-ahead flag. The register receives the clock as long 
as the external flag is not active. When the external flag goes active, 
indicating a boundary condition, the master and slave registers are frozen 
by special logic. After the first read (full) or write (empty) the next 
clock resets the master and slave registers and enables the register 
clock. The reset logic design is typically very involved and complex. 
All the above architectures suffer from very high tSKEW delays (.about.8-10 
Gate Delays). Additionally these architectures also suffer from 
metastabilty problems introduced by the register trying to sample the 
asynchronous internal flag which is updated by both the asynchronous read 
and write clocks. The present invention solves both of these issues by 
providing very high MTBF and very short, even Ons tSKEW. Additionally the 
present invention gives designers the flexibility to program the tSKEW to 
any desired value, including a Ons tSKEW. The synchronous FIFO's require a 
flag updation cycle at the empty and full boundaries. Typically the fall 
through read timing (read after the first write), which is the worst, 
defines the clocking frequency. Although the flexibility to program the 
tSKEW to Ons is idealistic, the tSKEW does need to be programmed based on 
the fall through timing, which typically results in higher tSKEW 
requirements. 
SUMMARY OF THE INVENTION 
The present invention provides an asynchronous state machine with a 
programmable tSKEW that is used to generate a synchronous empty or full 
flag in a synchronous FIFO buffer. The present invention accomplishes this 
by using a set state machine which can make the external flag go low, or 
active, and a reset state machine which can only make the external flag go 
high, or inactive. The functioning of the set state machine and the reset 
state machine is controlled by a blocking logic. The output of each of the 
state machine drives a set-reset (SR) latch. The output of the SR latch is 
presented to an input of the blocking logic, which is used to control the 
mutual exclusion of the state machines. 
Objects, features and advantages of the present invention are to provide a 
system for generating a synchronous empty or full flag for use with 
synchronous FIFO buffers. The system produces the desired flags with 
extremely low tSKEW, can break the conventional tSKEW barrier of eight-ten 
gate delays, and can be programmed to produce any desired tSKEW delay all 
the way from Ons. 
It is another object of the present invention to provide a system for 
producing synchronous full and empty flags that can be ported to other 
technologies with minimal effort, can produce a consistent tSKEW delay 
that is independent of the size of the FIFO buffer, has a very high MTBF, 
can be used for the generation of both synchronous empty and full flags, 
requires less simulation when compared to prior art techniques and handles 
all the possible asynchronous clock transitions successfully.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring to FIG. 1, a block diagram of the overall architecture of the 
flag generator 10 is shown. The flag generator 10 generally comprises a 
state machine block 11, a set state machine 12, a reset state machine 14, 
a latch 16 and a blocking logic block 18. The set state machine 12 has a 
first input 20 that receives a signal Enwclk which represents an enabled 
write clock, a second input 22 that receives a signal Enrclk which 
represents an enabled read clock and a third input 24 that receives a 
signal Eflh which represents a look-ahead empty signal. The enabled read 
clock Enrclk and the enabled write clock Enwclk each drive a counter. Each 
of these counters have two built-in subcounters. A first subcounter is an 
exact subcounter and starts counting from zero after a reset signal. A 
second subcounter is a plus one counter that starts counting from a one 
after a reset. A look-ahead empty signal Eflh, is a signal that is 
generated externally from the state machines 12 and 14, but internally to 
the FIFO (not shown) and is a result of a bitwise exclusive OR of the plus 
one read subcounter and the exact write subcounter. The flag output of the 
latch 16 represents an empty flag (or full flag) indicating when the FIFO 
is either empty (or full). When the set output 26 is active the reset 
state machine 14 is enabled. Similarly, the set state machine 12 is 
enabled when the external empty (or full) flag is inactive. The blocking 
logic block 18 controls the mutual exclusion of the state machine 12 and 
14. The set output 26 can only provide a flag signal that sets the latch 
16. The latch 16 will remain in a set state until the reset state machine 
provides an output 28 that resets the latch 16. 
The reset state machine 14 has a first input 30 that receives the enabled 
write clock signal Enwclk, a second input 32 that receives a free running 
read clock rCLK and a third input 34 that receives a non-look-ahead empty 
signal Efnlh. The non-look-ahead empty signal Efnlh is a signal that is 
generated externally from the state machines 12 and 14, but internally to 
the FIFO (not shown) and is a result of a bitwise exclusive OR of the 
exact read subcounter and the exact write subcounter. 
The signals rCLK and wCLK are each free running externally generated 
clocks. The actual reading (or writing) is performed by additionally 
providing a synchronous read (write) enable input signal to the FIFO. When 
the enable input is active in a clock cycle, internally to the FIFO, an 
enabled read (write) clock is generated. These are represented by the 
Enrclk (Enwclk) inputs to the state machine. 
The reset state machine 14 produces the reset output 28 that resets the 
latch 16. The reset state machine 14 also has a fourth input 36 that 
receives a signal from the blocking logic block 18. The blocking logic 
block 18 controls the functioning of the reset state machine 14. As a 
result, the reset state machine 14 only produces a reset output 28 when 
the FIFO is empty. In contrast, no additional logic is required to control 
the set state machine 12 because, unlike the reset state machine 14, the 
set state machine 12 has an enabled read clock Enrclk as an input at input 
22. The result is that the activity of each of the state machines 12 and 
14 is mutually exclusive. While the set machine 12 is active, the reset 
state machine 14 is frozen by the blocking logic block 18. The latch 16 
receives the set output 26 and the reset output 28 and produces an output 
signal flag and an output signal flagb. The output flag is updated by the 
enabled read clock Enrclk present at the second input 22 of the state 
machine 12. A programmed tSKEW delay can be achieved by delaying the 
enabled write clock Enwclk present at the input 22 of the set state 
machine 12. This programming feature will be more apparent after reading 
the description of FIG. 2. 
Referring to FIG. 2, a more detailed block diagram of the flag generator 10 
is shown. The set state machine 12 receives the first, second and third 
inputs 20, 22 and 24, as well as a fourth input 36 that represents an 
external reset input Rstb as a control signal input Cntrlb. The input Rstb 
is an active low input. The set state machine 12 also has a fifth input 38 
that also receives the external master reset input Rstb. The reset state 
machine 14 receives the first, second and third inputs 30, 32 and 34. The 
reset state machine 14 has a fourth input 40 that receives an input from 
the external master reset signal Rstb. The reset state machine 14 also has 
a fifth input 42 that receives a control signal Cntrlb from an inverter 
44. The reset state machine receives a sixth input 43, representing an 
external flag signal flagext, from the blocking logic block 18. The 
inverter 44 receives a signal from a NOR gate 46. The NOR gate 46 has a 
first input 48 that receives a signal from the output 43 of the blocking 
logic 18, a second input 50 from the non-look-ahead empty flag Efnlh and a 
third input 52 which receives a signal Rtb that represents an external 
retransmit signal. The external retransmit signal Rtb and the external 
master reset signal Rstb are additional input signals (not shown in FIG. 
1) that provide a means to reset the flag generator 10 from an external 
source. 
The first input 20 of the set state machine 12 and the first input 30 of 
the reset state machine 14 can be delayed through a tSKEW programming 
block 54, which provides a programmable delay. The programmable delay can 
be implemented either electronically, or through discrete digital 
components, such as inverters. Regardless of the delay system used, the 
presence of a delay from the tSKEW programming block 54 makes the tSKEW 
delay programmable by the designer to fit any particular design 
requirements. If no tSKEW delay is desired, the tSKEW programming block 54 
can be eliminated. The flag generator 10 can also be used to generate a 
full flag by adjusting the retransmit and reset logic to suit the design 
specification of a full flag. 
Referring to FIG. 3, the tSKEW programming block 54 is shown in greater 
detail. The tSKEW programming block 54 has an input 56 that receives the 
signal from the enable write clock Enwclk and an output 58 that is 
received by the first input 20 of the set machine 12. The input 56 is 
received by a gate delay block 60 that provides a programmable amount of 
delay. The gate delay block 60 produces a signal that is cascaded through 
an inverter 64 and an inverter 66 produce the output 58. 
Referring to FIG. 4, a detailed schematic of the reset state machine 14 is 
shown. The reset state machine 14 has an input W, R, Eint, Rstb, Flagext 
and Cntrib that represent the inputs 30, 32, 34, 40, 43 and 42 shown in 
FIG. 2. The reset state machine 14 has a set of digital logic gates that 
perform the desired output function. The input Cntrib is received by a 
control block 80 that produces the output 26. The control block 80 
processes information necessary to produce a reset and retransmit. FIG. 4 
also includes blocks 77 (that are described in connection with FIG. 6A) 
and a block 79 (that is described in connection with FIG. 6C). 
Referring to FIG. 5, a detailed schematic of the set state machine 12 is 
shown. The set state machine 12 has inputs W, Rstb, R, Eint, Rstb, and 
Cntrlb. The set state machine 14 also has a control block 80 which 
functions identically to the control block 80 in FIG. 4. The set state 
machine 12 of FIG. 5 uses non-overlapping clock generator blocks 77 (that 
are described in connection with FIG. 6A) to produce true and complement 
signals of necessary internal signals. The set state machine 12 of FIG. 5 
also includes a block 81 (that is described in connection with FIG. 6B). 
Referring to FIG. 6A, 6B and 6C logic level diagrams showing the blocks 77, 
79 and 81 is shown. Each of the FIGS. 6A-C comprise of a generic input 
labeled Xin and a generic ouptut Xb. FIGS. 6B and 6C also include an 
output X that is equal to Xin. Each of the FIGS. 6A-6C comprise discrete 
logic components. It should be appreciated that any method of providing a 
true and complement signal can be used in place of FIGS. 6A-6C without 
departing from the spirit of the invention. 
Referring to FIG. 7, the control block 80 is shown in greater detail. The 
control block 80 has a first input 82 that receives a signal cntrib, a 
second input 84 that receives a signal IN0, a third input 86 that receives 
a signal IN1 and a fourth input 88 that receives a signal IN2. The control 
block 80 comprises a transistor 90, a transistor 92, a transistor 94, a 
transistor 96, a transistor 98, a transistor 100, a transistor 102 and a 
transistor 104. The first input 82 is received by an inverted input of the 
transistor 90 as well as an input of the transistor 100. The second input 
84 is received by an inverted input of the transistor 92 as well as an 
input of the transistor 98. The third input 86 is received by an inverted 
input of the transistor 94 as well as an input of the transistor 102. The 
fourth input 88 is received by an inverted input of the transistor 96 as 
well as an input of the transistor 104. The gates and sources of the 
transistors 92, 94, 96, 98 and 100 are cascaded together. The source of 
the transistor 92 is connected to the source of the transistor 90. The 
drain of the transistor 90 is coupled with the source of the transistor 
98, the source of the transistor 102, the source of the transistor 104 and 
the drain of the transistor 96 to provide an output 106. 
The logic of the set state machine 12 is illustrated by the following TABLE 
1: 
TABLE 1 
______________________________________ 
##STR1## 
##STR2## 
______________________________________ 
The individual columns are labeled as a three bit binary value where the 
first bit, when the flag generator 10 is configured to generate an empty 
flag, represents the look-ahead empty signal Eflh, the second bit 
represents the enabled write clock Enwclk and the third bit represents the 
enabled read clock Enrclk. The column labeled Set reprents the decoded 
output of the set state machine 12. 
A specified version of TABLE 1 where redundant states are eliminated is 
shown in the following TABLE 2: 
TABLE 2 
______________________________________ 
##STR3## 
______________________________________ 
Similar to the logic of the set state machine 12 shown in TABLE 2, the 
logic of the reset state machine 14 is illustrated by the following TABLE 
3: 
TABLE 3 
______________________________________ 
##STR4## 
##STR5## 
______________________________________ 
The individual columns are similarly labeled. The first bit, when the state 
machine 10 is configured to generate an empty flag, represents the non 
look-ahead empty signal Efnlh, the second bit represents the enabled write 
clock Enrclk and the third bit represents the free running read clock 
rCLK. The column labeled Reset represents the decoded output of the reset 
state machine 14. 
A simplified version of TABLE 3 where the redundant states are eliminated 
is shown in the following TABLE 4: 
TABLE 4 
______________________________________ 
##STR6## 
______________________________________ 
When the flag generator 10 is configured to generate a full flag the bits 
of the columns of TABLES 1-4 represent the same signals, but at different 
locations. Specifically, when the flag generator 10 is configured to 
generate a full flag, the first bit of TABLE 1 and 2 represents the 
look-ahead full signal Eflh, the second bit represents the enabled read 
clock Enrclk and the third bit represents the enabled write clock Enwclk. 
The first bit of TABLE 3 and 4 represents the non-look-ahead full signal 
Efnlh, the second bit represents the enabled read clock Enrclk and the 
third bit represents the free running write clock wCLK. 
It should also be appreciated that the present invention uses the set state 
machine 12 and the reset state machine 14 that each handle two input 
clocks and a look-ahead signal. Each of the state machines 12 and 14 has 
four possible output states, as illustrated in TABLES 2 and 4. With design 
criteria requiring five input variables and eight output states, the 
implementation of two input state machines 12 and 14 is far less complex 
than the implementation of a single state machine capable of handling all 
combinations. Furthermore, the blocking logic block 18 is insignificant 
enough to maintain the simplicity of the set/reset implementation of the 
present invention. While the use of smaller, more efficient state machines 
12 and 14 is superior using a single more complex state machine, the 
present invention can be implemented using a single larger state machine 
without departing from the spirit of the present invention. 
It is to be understood that modifications to the invention might occur to 
one skilled in the field of the invention within the scope of the appended 
claims.