Level converting circuit efficiently increasing an amplitude of a small-amplitude signal

A gate of an N-channel MOS transistor driving an output node is driven through a capacitance element in accordance with an input signal. A voltage on a source node of the drive transistor is applied as an output signal to an output node. Consequently, it is possible to perform level conversion of a voltage at a low level of the input signal having a higher voltage than the source node voltage of the drive transistor. It is thus possible to achieve a level converting circuit that can reduce the number of manufacturing steps, and can perform the level conversion of any logical level of the input signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a level converting circuit for converting an amplitude of a signal, and particularly to a level converting circuit using an insulated gate field effect transistor of a single conductivity type.

2. Description of the Background Art

In conventional semiconductor devices, there has been widely employed a CMOS circuit formed of a P-channel MOS transistor (insulated gate field effect transistor) and a N-channel MOS transistor. Based on characteristics of threshold voltages of the MOS transistors, it is general in the CMOS circuit to turn on the P-channel MOS transistor when a signal at an H level (logically high level) is to be output, and to turn on the N-channel MOS transistor when a signal at an L level (logically low level) is to be output. In the CMOS circuit, charging/discharging current flows when an output signal of the CMOS circuit changes, but no current flows when the output signal is stable, so that power consumption can be made small.

There are some cases that an internal voltage at a level different from a power supply voltage and a ground voltage is used in semiconductor devices. When the internal voltage is higher than the power supply voltage or is lower than the ground voltage, a signal changing between the power supply voltage and the ground voltage must be converted to a signal changing between the internal voltage and the ground voltage, between the power supply voltage and the internal voltage, or between first and second internal voltages, and a level converting circuit is required for such conversion.

When the level converting circuit is formed of a CMOS circuit, P- and N-channel MOS transistors must be used, resulting in an increased number of manufacturing steps. In order to avoid such increase, a level converting circuit may be formed of a single kind of MOS transistors, as is disclosed in Japanese Patent Laying-Open No. 2002-328643, for example.

The level converting circuit disclosed in the above prior art reference converts a signal changing between a ground voltage and a power supply voltage to a signal changing between the ground voltage and an internal voltage VDD2higher than power supply voltage VDD1. The level converting circuit disclosed in the above prior art reference includes an input stage formed of an N-channel MOS transistor connected in series to a diode-connected load element and having a gate receiving an input signal, a push-pull output stage formed of N-channel MOS transistors connected in series between an internal voltage supply node and a ground node, and a capacitance element connected between an output node of the push-pull output stage and an output node of the input stage. A MOS drive transistor on a high side of the output stage has a gate coupled to the output node of the input stage, and an input signal is supplied to a gate of a MOS drive transistor on a low side of the output stage.

The capacitance element is utilized as a bootstrapping capacitance. It is now assumed that the input signal is at the low level, the drive transistor in the input stage is off, and the drive transistor on the low side in the output signal is off. In this state, when the voltage level of the output signal applied from the output stage rises in accordance with the input signal, a bootstrapping effect of the capacitance element raises the gate voltage of the high-side MOS drive transistor in the output stage to a level higher than internal voltage VDD2, to produce a signal at a level of the voltage VDD2.

When the input signal is at the high level, the low-side MOS transistor in the output stage drives the output signal to the ground voltage level. In this operation, the output signal of the input stage attains a low level of a voltage level determined by on-resistances of the diode-connected load MOS transistor and the drive transistor, and the high-side MOS drive transistor in the output stage turns non-conductive.

In the above prior art reference, only N-channel MOS transistors are used in the level converting circuit for the purpose of eliminating steps of forming P-channel MOS transistor, to reduce the number of manufacturing steps.

In the structure of the level converting circuit disclosed in the above prior art reference, the high-side MOS drive transistor in the output stage has the gate set to the electrically floating state, and through the bootstrapping operation of the capacitance element, the voltage level of the gate raised to produce a signal at the high level of voltage VDD2higher than the high-level voltage VDD1of the input signal. Both low-level voltages of the input signal and the output signal are equal to the ground voltage. The drive transistor in the input stage and the low-side MOS driver transistor in the output stage are commonly supplied with the input-signal, so that the level conversion of the input signal to the high-level voltage can be performed.

However, when N-channel MOS transistor is used, the low level of the output signal cannot be made lower than the ground voltage. If the low-side MOS transistor in the output stage is coupled to a negative voltage supply instead of the ground node, the low-side MOS drive transistor in the output stage does not turn non-conductive even when its gate attains the level of ground voltage. Consequently, a through-current flows in the output stage, and the voltage of output signal at the high level lowers.

If a signal at a low level of a negative voltage lower than the ground voltage is to be produced, in the structure of the foregoing prior art reference, voltage polarities are made inverted, and the MOS transistors are formed of P-channel transistors. In this case, however, the high-level voltages of the input and output signals are both equal to the power supply voltage.

In the structure of the foregoing prior art reference, therefore, the low-level voltage of the input signal could not be converted to a voltage lower than the low-level voltage with only the N-channel MOS transistors. Likewise, it is impossible to produce an output signal having a high-level voltage higher than the high-level voltage of the input signal with only P-channel MOS transistors.

In addition, in the structure of the foregoing prior art reference, both the high- and low-level voltages of the input signal could not be converted with a common circuit structure.

SUMMARY OF THE INVENTION

An object of the invention is to provide a level converting circuit capable of easily effecting voltage level conversion of both logical levels of a signal voltage, with MOS transistors of a single kind.

Another object of the invention is to provide a level converting circuit capable of converting a low-level voltage to a voltage at a further lower level, with only N-channel MOS transistors.

Still another object of the invention is to provide a level converting circuit capable of converting a high-level voltage to a further higher voltage, with only P-channel MOS transistors.

A level converting circuit according to the invention is a level converting circuit having first and second power supplies and converting an input signal having an amplitude smaller than a voltage difference between the first and second power supplies to a signal changing between voltage levels corresponding to the voltages of the first and second power supplies, and includes a first MOS transistor coupled between an output node and the first power supply; a first capacitance element coupled between a node receiving the input signal and a gate of the first MOS transistor; a first current driving element coupled between the gate of the first MOS transistor and the first power supply, and a second current driving element coupled between the second power supply and the output node.

Through capacitance coupling or a charge pump operation of the capacitance element, a gate potential of the first MOS transistor changes with an amplitude of the input signal with reference to a voltage level of the first power supply. Therefore, the first MOS transistor can be reliably set to the conductive/non-conductive states in accordance with the input signal, and the logical level of the input signal corresponding to the first power supply voltage can be converted to the level of the first power supply voltage.

For example, if the first MOS transistor is an N-channel MOS transistor and the first power supply voltage is a negative voltage, the gate voltage of the first MOS transistor changes between the negative voltage and a voltage higher than the negative voltage. Therefore, when the input signal is at the high level, the first MOS transistor turns conductive to produce an output signal at a negative voltage level. When the input signal is at the low level, the gate of the first MOS transistor attains a low level of the negative voltage, and the first MOS transistor turns non-conductive, so that the second current driving element can bring the output signal to the high level.

If the first MOS transistor is a P-channel MOS transistor, the gate potential of the first MOS transistor is changed, by the capacitance element, between a level of the first power supply voltage and a level lower than the first power supply voltage, and the first MOS transistor can be reliably set to the conductive/non-conductive states in accordance with the input signal. When the input signal is at the low level, the gate potential of the first MOS transistor attains the low level, and the first MOS transistor turns conductive, so that a signal at the level of the first power supply voltage is produced as the output signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1shows a configuration of a level converting circuit according to a first embodiment of the invention. The level converting circuit shown inFIG. 1produces, from a signal IN changing between a high level of a voltage VDD and a low level of a reference voltage GND, a signal /OUT changing between a high level of a positive voltage VH higher than voltage VDD and a low level of a negative voltage, −VL, lower than reference voltage GND. Voltage VDD and positive voltage VH may be equal in level to each other, or may be different in level from each other. Reference voltage GND provides a measurement reference level for various voltages, and is usually at a ground voltage level.

InFIG. 1, the level converting circuit includes a resistance element5connected between a high-side power supply node3and an output node2, an N-channel MOS transistor6connected between output node2and a negative power supply node (low-side power supply node)4, a capacitance element8connected between a signal input node1and a gate node9of a MOS transistor6, and a resistance element7connected between a gate node9and low-side power supply node4.

High-side power supply node3is supplied with positive voltage VH, and low-side power supply node4is supplied with negative voltage −VL.

Resistance element5has a resistance value RL, and resistance element7has a resistance value RG. These resistance elements5and7function as current driving elements. Capacitance element8has a capacitance value Cc.

Input signal IN changes between voltage VDD and reference voltage GND. Output signal /OUT is produced on output node2as an inverted signal of input signal IN.

FIG. 2is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 1. Referring toFIG. 2, an operation of the level converting circuit shown inFIG. 1will now be described.

It is assumed that at a time t0, the level converting circuit is in a steady state, and input signal IN applied to input node1is at the level of reference voltage GND. In this case, resistance element7maintains gate node9at the level of negative voltage −VL, and MOS transistor6has the gate and source potentials made equal to each other, and thus is non-conductive. In this state, output signal /OUT from output node2is at the level of positive voltage VH due to charging from high-side power supply node3through resistance element5.

At a time t1, input signal IN applied to input node1rises from the level of reference voltage GND to the level of voltage VDD. This voltage change is transmitted to gate node9through capacitance element8. Since parasitic capacitances such as a gate capacitance of MOS transistor6and a line capacitance of gate node9are present at gate node9, these parasitic capacitances lower the level of the voltage coupled to gate node9by capacitance element8. It is assumed here that capacitance value Cc of capacitance element8is sufficiently large as compared to the parasitic capacitances, and the potential change of voltage VDD is transmitted to gate node9.

It is also assumed that a time constant determined by a product of resistance value RG of resistance element7and capacitance value Cc of capacitance element8is sufficiently larger than a time period of the high level of input signal IN. In this case, the voltage level of gate node9rises from negative voltage −VL by voltage VDD, and gradually lowers in accordance with the time constant determined by resistance element7and capacitance element8.

At time t1, the voltage VDD is applied between the gate and source of MOS transistor6as a result of the voltage rising of gate node9. Assuming that the threshold voltage of the MOS transistor is sufficiently lower than the voltage VDD, the MOS transistor turns conductive, and the voltage level of output node2lowers to (−VL+ΔVL1), where voltage ΔVL1is an output offset voltage determined by a ratio between resistance element5and the on-resistance of MOS transistor6. Therefore, when the voltage level of gate node9lowers through the discharging by resistance element7, the on-resistance of MOS transistor6increases, so that output offset voltage ΔVL1increases.

At a time t2, input signal IN lowers from voltage VDD to reference voltage GND. This voltage change is transmitted to gate node9through capacitance element8, and the voltage on gate node9lowers by the voltage VDD. At time t2, the voltage level of gate node9is lower than that at time t1by a voltage ΔVH due to the discharging through resistance element7, and the voltage level of gate node9attains a level lower than negative voltage −VL. Responsively, MOS transistor6turns non-conductive, and output node2is charged by resistance element5to attain the voltage level of positive voltage VH again.

At a time t2, the voltage level of output node2rises from (−VL+ΔVL2) to positive voltage VH. This is because the on-resistance of MOS transistor6gradually increases in accordance with the lowering of its gate potential, and accordingly, the output offset voltage level rises.

Voltages ΔVH and ΔVL2are set such that both the high and low levels of output signal /OUT from output node2are outside the range of the input logical threshold voltage of a circuit in a subsequent stage. Thus, input signal IN changing between voltages VDD and GND can be converted to a signal changing between voltages VH and (ΔVH2−VL).

Voltage ΔVH is determined by capacitance value Cc of capacitance element8, resistance value RG of resistance element7and a high-level time period of input signal IN. Voltage VL2is determined by a channel resistance in the state when the gate to source voltage of MOS transistor6is equal to (VDD−ΔVH), as well as resistance value RL of resistance element5. By appropriately selecting these parameters, it is possible to make adequately the voltages ΔVH and ΔVL2small.

FIG. 3Ashows a modification of resistance element5shown inFIG. 1. InFIG. 3A, resistance element5is replaced with a constant current source5athat has a current driving capability substantially equal to that of resistance element5, and is connected between high-side power supply node3and output node2.

FIG. 3Bshows a modification of resistance element7. In a structure shown inFIG. 3B, resistance element7is replaced with a constant current source7athat has a current driving capability substantially equal to that of resistance element7, and is connected between gate node9and low-side power supply node4.

According to the structures shown inFIGS. 3A and 3B, resistance elements5and7in the level converting circuit shown inFIG. 1are replaced with constant current supplies5aand7a, respectively. In this case, the rising speed of output signal /OUT can be accurately set by the driving current of constant current source5a. The low level of output signal /OUT is determined in accordance with a current supplied by constant current source5aand the on-resistance of MOS transistor6. Also, the discharging speed of gate node9can be accurately set by constant current source7a. Accordingly, when an amount of the driving current of constant current source7ais made adequately small, the amount ΔVH of potential lowering of gate node9can be adequately small.

FIG. 4Ashows another modification of resistance element5shown inFIG. 1. InFIG. 4A, resistance element5is replaced with an N-channel MOS transistor5bthat has a drain and a gate both coupled to high-side power supply node3, and operates in a resistance mode.

FIG. 4Bshows another modification of resistance element7shown inFIG. 7. InFIG. 4B, resistance element7is replaced with an N-channel MOS transistor7bthat has a gate and a drain connected to gate node9, and operates in a resistance mode.

These MOS transistors5band7boperate in a saturation region, and functions as resistance elements by their on-resistances. The current driving capability of MOS transistors5band7bare made substantially equal to those of resistance elements5and7, so that a current driving element with a reduce occupation area and a limited driving current, can be implemented.

MOS transistor6and MOS transistors5band7bcan be produced through the same manufacturing process steps, so that the number of manufacturing steps can be reduced.

According to the first embodiment of the invention, as described above, the gate potential of the N-channel MOS drive transistor driving the output signal to the low level is changed through the capacitance coupling in accordance with the input signal, and thus the low-level voltage of the input signal can be converted to a further lower voltage level.

FIG. 5shows a configuration of a level converting circuit according to a second embodiment of the invention. InFIG. 5, the level converting circuit includes a P-channel MOS transistor16connected between a high-side power supply node13and an output node12, a current drive element15connected between output node12and a low-side power supply node14, a current drive element17connected between high-side power supply node13and a gate node19of MOS transistor16, and a capacitance element18connected between an input node11receiving input signal IN and gate node19.

Input signal IN changes between the voltage VDD and reference voltage GND, as in to the first embodiment. High-side power supply node13receives a voltage VHG, and low-side power supply node14receives a voltage VLW. High-side power supply voltage VHG is higher than high-level voltage VDD of input signal IN. Low-side power supply voltage VLW may be reference voltage GND or may be lower than reference voltage GND. Further, low-side power supply voltage VLW may be higher than reference voltage GND.

Each of current drive elements15and17is formed of a resistance element, a constant current source or a P-channel MOS transistor operating in a resistance mode.

FIG. 6is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 5. Referring toFIG. 6, the operation of the level converting circuit shown inFIG. 5will now be described.

It is assumed that at a time t10, input signal IN is at the level of voltage VDD, gate node19is at the level of voltage VHG, and output signal /OUT generated from output node12is at the level of voltage VLW.

At a time t11, input signal IN falls from voltage VDD to reference voltage GND, and the potential change of input signal IN is transmitted to gate node19through capacitance element18, and the voltage level of node19lowers from voltage VHG to a voltage of (VHG−VDD). A parasitic capacitance of gate node19is neglected. If the voltage VDD is sufficiently higher than the absolute value of the threshold voltage of MOS transistor16, the gate-source voltage of MOS transistor16is lower than the threshold voltage thereof, so that MOS transistor16turns conductive to supply a current to output node12, and accordingly, the voltage level of output signal /OUT rises.

The high level of output signal /OUT is lower than voltage VHG by an output offset voltage ΔV2. Output offset voltage ΔV2is determined by the on-resistance of MOS transistor16as well as an amount of current driven by current drive element15or a resistance value thereof. After the voltage level of gate node19lowers by VDD in accordance with the fall of input signal IN, current drive element17supplies a current from high-side power supply node13, and the voltage level of gate node19rises. In accordance with the rising of voltage level of gate node19, the on-resistance of MOS transistor16increases, and the voltage level of output signal /OUT lowers.

The amounts of drive current or the resistance values of current drive elements15and17as well as the on-resistance of the MOS transistor are set such that the potential change of gate node19and the potential change of output signal /OUT can be substantially neglected over a time period of L-level of input signal IN. These conditions are similar to those in the first embodiment.

At a time t12, input signal IN rises from the level of reference voltage GND to the level of voltage VDD. In accordance with the voltage rising of input signal IN, the potential of gate node19rises from the voltage of (VHG−VDD+ΔV1) by voltage VDD. In accordance with the potential rising of gate node19, MOS transistor16turns non-conductive, and current drive element15discharges output node12, and accordingly, the voltage level of output node12falls to the level of low-side power supply voltage VLW. Before the falling at time t12, MOS transistor16has the on-resistance increased in accordance with the potential rising of gate node19due to the current supplied from current drive element17, and accordingly, output signal /OUT is at a lowered level of voltage of (VHG−ΔV3).

When the level converting circuit shown inFIG. 5is utilized, the high-level voltage VDD of input signal IN can be raised to the voltage level corresponding to the voltage VHG higher than high-level voltage VDD, and output signal /OUT having a high-level voltage of (VHG−ΔV3) larger than VDD can be produced. In particular, when output signal /OUT sufficiently changes into the high and low sides exceeding the input logical threshold of a circuit in a succeeding stage of the output node12of the level converting circuit, the level converting circuit shown inFIG. 5can be utilized as the level converting circuit for converting the high-level voltage.

According to the second embodiment of the invention, as described above, the gate potential of the P-channel MOS transistor driving the output signal to the high level is changed through the capacitance coupling in accordance with the input signal, and the signal having a high-level voltage higher than the high-level voltage of the input signal can be produced by using only the P-channel MOS transistors as the MOS transistors.

FIG. 7shows a configuration of a level converting circuit according to a third embodiment of the invention. In the level converting circuit shown inFIG. 7, a bootstrapping type load circuit20is used, in place of resistance element5in the level converting circuit shown inFIG. 1. The bootstrapping type load circuit20includes an N-channel MOS transistor21connected between high-side power supply node3and output node2, an N-channel MOS transistor22that has a gate and a drain connected to the high-side power supply node and has a source connected to a gate node24of MOS transistor21, and a capacitance element23connected between output node2and node24.

MOS transistor22, when conductive, charges node24to a voltage level of (VH−Vthn), where Vthn represents a threshold voltage of MOS transistor22. Other configuration of the level converting circuit shown inFIG. 7is the same as in the level converting circuit shown inFIG. 1. Corresponding portions are allotted with the same reference numerals, and description thereof will not be repeated.

A timing relationship between input signal IN and output signal /OUT of the level converting circuit shown inFIG. 7is essentially the same as that illustrated inFIG. 2.

In the level converting circuit shown inFIG. 7, when input signal IN is at a high level of voltage VDD, gate node9is at the level of voltage of (VDD−VL) so that MOS transistor6is conductive, and output signal /OUT generated from output node2attains the low level corresponding to the level of voltage −VL.

In this state, the source node of MOS transistor21in bootstrapping type load circuit20is at the side of output node2. Even when the potential of node24lowers by capacitance element23in accordance with the potential lowering of output node2, MOS transistor22is conductive, and thus sets the gate potential of MOS transistor21to the voltage of (VH−Vthn). Usually, a voltage of (VH−Vthn−(−VL)) is higher than a threshold voltage of MOS transistor21. Therefore, MOS transistor21is made conductive, and output signal /OUT attains the voltage level determined by the current drive capabilities (on-resistances) of MOS transistors21and6. When the current driving capability (or on-resistance) of MOS transistor21is made sufficiently smaller than the current driving capability (or on-resistance) of MOS transistor6, output signal /OUT can be set to the voltage level sufficiently close to voltage −VL.

When input signal IN falls from the level of voltage VDD to the level of reference voltage GND, the voltage level of gate node9lowers, and MOS transistor6turns non-conductive. In this state, MOS transistor21charges output node2to raise its voltage level. When the voltage level of output node2rises, this voltage rising is transmitted to node24through capacitance element23. When the voltage level of node24exceeds the voltage of (VH−Vthn), MOS transistor22turns non-conductive, and node24enters a floating state. Therefore, in accordance with the rising of output signal /OUT generated from output node2, the voltage level of node24further rises from the voltage of (VH−Vthn). When the voltage level of node24exceeds the voltage of (VH+Vthn), MOS transistor21supplies voltage VH to output node2, and output signal /OUT attains the level of voltage VH.

Through the bootstrapping operation of capacitance element23, MOS transistor21can be quickly set to a deep on-state, and output signal /OUT can be raised more quickly than that in a configuration utilizing resistance elements or others.

In an operation of falling of output signal /OUT from the high level to the low level, MOS transistor22in bootstrapping type load circuit20is initially in a non-conductive state, and accordingly, node24can be lowered in voltage level through the capacitance coupling of capacitance element23. Accordingly, the voltage level of node24quickly lowers to the voltage level of (VH−Vthn), and MOS transistor21has a sufficiently reduced current driving capability (or a sufficiently decreased on-resistance). Thus, MOS transistor6can quickly discharge the output node2.

Accordingly, by utilizing the bootstrapping type load circuit20shown inFIG. 7, it is possible to implement the level converting circuit that can quickly change output signal /OUT.

In particular, the level converting circuit shown inFIG. 7can achieve a higher rising rate of output signal /OUT than the level converting circuit shown inFIG. 1.

FIG. 8shows a configuration of a modification of the level converting circuit according to a third embodiment of the invention. The level converting circuit shown inFIG. 8is substantially the same as the level converting circuit shown inFIG. 5, except for inclusion of a bootstrapping type load circuit30instead of current drive element15. Other configuration of the level converting circuit shown inFIG. 8is the same as in the level converting circuit shown inFIG. 5. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

Bootstrapping type load circuit30includes a P-channel MOS transistor31that is connected between output node12and low-side power supply node14, and has a gate connected to a node34, a P-channel MOS transistor32that has a gate and a drain connected to low-side power supply node14, and has a source connected to node34, and a capacitance element33connected between output node12and node34.

MOS transistor32in the on state maintains the node34at the voltage level of (VLW+Vthp), where Vthp represents an absolute value of the threshold voltage of MOS transistor32.

FIG. 9is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 8. The operation of the level converting circuit shown inFIG. 8is similar to that represented by the signal waveforms inFIG. 6. When input signal IN falls from the high level of voltage VDD to the low level of voltage GND, the voltage level of node19lowers, and MOS transistor16is turned on so that output signal /OUT from output node12attains the high level. When output signal /OUT rises, MOS transistor32turns conductive even if the potential of node34rises through the capacitance coupling of capacitance element33, and therefore the potential of node34is maintained at the voltage level of (VLW+Vthp). In accordance with the potential rising of output node12, the source of MOS transistor31is provided by output node12. Generally, the voltage of (VH−(Vthp+VLW)) is larger than absolute value Vthp of the threshold voltage. Therefore, MOS transistor31keeps the on state. Output signal /OUT attains the voltage level determined by the current driving capabilities (on-resistances) of MOS transistors16and31. By making the current driving capability of MOS transistor31sufficiently smaller than that of MOS transistor16, output signal /OUT can be raised to the level of voltage VH.

When input signal IN rises from reference voltage GND to voltage VDD, the voltage level of gate node19rises, and MOS transistor16turns non-conductive. At this time, MOS transistor31discharges output node12to lower its voltage level. Capacitance element33transmits this voltage level lowering of output node12to node34. When the voltage level of node34lowers below the voltage of (VLW+Vthp), MOS transistor32turns non-conductive. Accordingly, node34enters the floating state, and through the capacitance coupling of capacitance element33, the voltage level of node34further lowers in accordance with the potential lowering of output node12. Thus, MOS transistor31enters a deep on-state. Accordingly, MOS transistor31discharges output node12with a large current driving power. When the potential of node34lowers to or below the voltage of (VLW−Vthp), output signal /OUT lowers to the level of low level voltage of VLW (i.e., −VL).

An amount of this voltage change of node34is determined by the capacitance division by capacitance element33and the parasitic capacitance of node34. By sufficiently increasing the capacitance value of capacitance element33, the voltage level of node34can be fully changed in accordance with output signal /OUT, and MOS transistor31can be switched between the deep on-state and the shallow on-state so that output signal /OUT from output node12can be changed.

Specifically, the level converting circuit shown inFIG. 8has the function of converting the level of the high-level voltage, and further can increase the falling rate of output signal /OUT, as compared with the case using the current drive element shown inFIG. 5.

According to the third embodiment of the invention, as described above, the bootstrapping type load circuit is utilized as the load element for the output node, and thus the level-converted signal can be quickly outputted.

FIG. 10shows a configuration of a level converting circuit according to a fourth embodiment of the invention. The level converting circuit shown inFIG. 10further includes an output assisting circuit40that produces output signal /OUT at a converted level to a final output node50in accordance with a signal produced on output node2. A circuit portion generating a signal onto output node2in accordance with input signal IN applied to input node1has the same configuration as that in the level converting circuit shown inFIG. 1. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

Output assisting circuit40has an N-channel MOS transistor41that is connected between high-side power supply node3and final output node50and has a gate connected to a node45, an N-channel MOS transistor42that has a gate and a drain connected to high-side power supply node3as well as a source connected to node45, an N-channel MOS transistor43that is connected between high-side power supply node3and output node2and has a gate connected to node45, a capacitance element45connected between output node2and node45, and an N-channel MOS transistor46that is connected between final output node50and low-side power supply node4and has a gate connected to gate node9.

In the level converting circuit shown inFIG. 10, the initial input stage receiving input signal IN and discharging output node2, has the same configuration as that of the level converting circuit shown inFIG. 1. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

FIG. 11is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 10. Referring toFIG. 11, the operation of the level converting circuit shown inFIG. 10will now be described.

Input signal IN applied to input node1changes between voltage VDD and reference voltage GND. In accordance with input signal IN, the voltage level of gate node9changes between voltage −VL and the voltage of (VDD−VL). It is now assumed that a voltage change ΔV caused by discharging through resistance element7is sufficiently small. In addition, it is assumed that the parasitic capacitance of gate node9is sufficiently smaller than the capacitance value of capacitance element8, and is substantially negligible.

When output node2is at the low level of voltage −VL, MOS transistor42maintains the node45at the level of voltage of (VH−Vthn).

When input signal IN rises from reference voltage GND to voltage VDD, the voltage level of gate node9rises, MOS transistor6has a reduced on-resistance, to lower the voltage level of output node2. In this state, MOS transistor42maintains node45at the level of voltage of (VH−Vthn). Therefore, MOS transistor41maintains the on state, and the voltage level of output node2is kept at the voltage level determined by the current driving capabilities (or on-resistances) of MOS transistors43and6.

In the above operation, MOS transistor46is also turned on, and the voltage level of output signal /OUT from final output node50lowers. Since MOS transistor41is also conductive, the lowered voltage level of output signal /OUT is determined by the current driving capabilities (or on-resistances) of MOS transistors41and46. When MOS transistor41is configured to have the current driving capability sufficiently smaller than that of MOS transistor46, or is configured to have the on-resistance sufficiently higher than that of MOS transistor46, the low-level voltage of output signal /OUT can be made substantially equal to voltage −VL.

When input signal IN falls from voltage VDD to reference voltage GND, the voltage level of gate node9lowers so that the gate to source voltage of MOS transistor6becomes equal to or lower than its threshold voltage, and MOS transistor6is turned off. Accordingly, output node2is charged by MOS transistor43, and its voltage level rises. Capacitance element44transmits this potential rising of output node2to node45, and MOS transistor42turns non-conductive, and accordingly, the voltage level of node45further rises from the precharged voltage level. Responsively, the on-resistance of MOS transistor43decreases (the current driving power increases), and the voltage level of output node2quickly rises and this voltage rising of output node2is fed back to node45. Accordingly, MOS transistor43charges output node2up to the level of voltage VH. The voltage level of node45rises from the precharged voltage of (VH−Vthn) by (VH+VL−ΔV). By this voltage rising of node45, MOS transistor41enters the deep on-state, and quickly charges output node50to raise output signal /OUT to the level of voltage VH. In this state, the gate to source voltage of MOS transistor46is equal to or lower than the threshold voltage, and MOS transistor46is in the non-conductive state, similarly to MOS transistor6.

The conductive state and the non-conductive state described above represent the state of driving the current and the state of cutting off the current, respectively.

Even the level converting circuit shown inFIG. 10can convert the signal changing between voltage VDD and reference voltage GND to the signal changing between voltage VH and voltage −VL (+ΔV). In particular, output node50is charged using MOS transistor41. Therefore, even if a capacitive load is connected to output node50, the voltage level of node45can be quickly raised to the voltage of (VH+VL−ΔV) without an influence by such capacitive load. When output signal /OUT falls, the potential of node45can be recovered from the high voltage level to the level of precharged voltage of (VH−Vthn) without an influence by the capacitive load. Thus, output signal /OUT can quickly fall from the high level to the low level.

FIG. 12shows a modification of the level converting circuit according to the fourth embodiment of the invention. The level converting circuit shown inFIG. 12includes, additionally in the level converting circuit shown inFIG. 8, a push-pull stage60for driving a final output node62in accordance with the voltages on gate node19and node34. Other configuration of the level converting circuit shown inFIG. 12is the same as in the level converting circuit shown inFIG. 8. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

Push-pull stage60includes a P-channel MOS transistor65that is connected between high-side power supply node13and final output node62and has a gate connected to node19, and a P-channel MOS transistor66that is connected between final output node62and low-side power supply node14and has a gate connected to node34.

In the configuration of the level converting circuit shown inFIG. 12, capacitance element33of the bootstrapping type load circuit is isolated from final output node62. Therefore, the bootstrapping effect of capacitance element33can be fully increased without an influence by the capacitive load at final output node62, and output signal /OUT can be quickly produced. Operation waveforms of the level converting circuit illustrated inFIG. 12are similar to those illustrated inFIG. 9. It is possible to raise quickly output signal /OUT from voltage VHG to voltage VLW (=−VL), where a factor such as a parasitic capacitance is neglected.

According to the fourth embodiment of the invention, as described above, the bootstrapping type load circuit is isolated from the final output node, and the push-pull stage drives the final output node. Thus, the output signal can be changed quickly.

FIG. 13shows a structure of a level converting circuit according to a fifth embodiment of the invention. InFIG. 13, the level converting circuit includes an input stage100that converts input signal IN applied to input node1to a signal changing between voltages VH and −VL onto a node A, a push-pull stage110for driving a node B in accordance with complementary signals applied from input stage100, a bootstrapping type drive stage120for driving a node C in accordance with an output signal of push-pull stage110, and a final drive stage130for driving an output node150in accordance with the output signals of input stage100, push-pull stage110and bootstrapping type drive stage120as well as final output signal OUT.

Input stage100has a configuration similar to that of the level converting circuit shown inFIG. 7, and includes capacitance element8transmitting input signal IN to gate node9, resistance element7connected between gate node9and a low-side power supply line104, N-channel MOS transistor6selectively made conductive in accordance with the voltage level of gate node9, to drive node A to the voltage level corresponding to the level of voltage −VL on low-side power supply line104, an N-channel MOS transistor Q1connected between a high-side power supply line102and node A, an N-channel MOS transistor Q2for transmitting a voltage of (VH−Vthn) to the gate of MOS transistor Q1when made conductive, and a capacitance element CP1connected between a gate of MOS transistor Q1and node A.

Input stage100operates similarly to the level converting circuit shown inFIG. 7, and converts input signal IN changing between voltages VDD and GND to a signal changing between voltage VH and voltage −VL onto node A.

In the following description, the influences which may be exerted on the voltage levels of the output signal and input signal due to the parasitic capacitance of an internal node, discharging through the resistance element7and the current driving powers (or on-resistances) of the MOS transistors are neglected, and each circuit is assumed to operate as a ratio circuit, to change the output signal of each stage between voltages of VH and −VL. In addition, MOS transistors6and Q1–Q15are each assumed to have a threshold voltage Vthn.

Push-pull stage110includes N-channel MOS transistor Q3for supplying a current from high-side power supply line102to node B in accordance with the signal on node A, and N-channel MOS transistor Q4for supplying a current from node B to low-side power supply line104in accordance with the signal on gate node9.

In push-pull stage110, when input signal IN rises from the low level to the high level, MOS transistor Q4turns conductive to lower the voltage level of node B. In this operation, the voltage level of output node A of input stage100lowers, and the voltage difference between nodes A and B changes to or below Vthn. Responsively, MOS transistor Q3turns non-conductive, and the voltage at node B lowers to the level of low-side power supply voltage −VL. When the voltage level of input signal IN lowers, the voltage level of gate node9lowers to turn MOS transistor Q4off. MOS transistor Q1raises the level of node A to voltage VH, and responsively MOS transistor Q3charges node B to the level of (VH−Vthn).

In push-pull stage110, the gate potential of MOS transistor Q3changes after the gate potential of MOS transistor Q4changes. Therefore, in the operation of charging the node B, MOS transistor Q3turns conductive after MOS transistor Q4turns non-conductive, and therefore, a through current hardly occurs. In the operation of discharging the node B, MOS transistor Q3turns non-conductive after MOS transistor Q4turns conductive. With the offset voltage taken into account, the gate potential of MOS transistor Q3is equal to (−VL+ΔV). Therefore, when this voltage ΔV (i.e., the output offset voltage in input stage100) is sufficiently smaller than the threshold voltage Vthn of MOS transistor Q3, MOS transistor Q3can be reliably set to the turn-off state. In this push-pull stage110, therefore, the through current flows only in the operation of discharging the node B, and thus the current (DC current) is consumed only for a short switching time period.

Bootstrapping type drive stage120includes N-channel MOS transistor Q7for driving the node C to the level of low-side power supply voltage −VL in accordance with the signal on output node B in push-pull stage110, N-channel MOS transistor Q5connected between high-side power supply line102and node C, a capacitance element CP2connected between the gate of MOS transistor Q5and node C, and N-channel MOS transistor Q6for charging the gate of MOS transistor Q5to the voltage of (VH−Vthn) when made conductive.

Bootstrapping type drive stage120operates substantially in the same manner as input stage100. When the voltage level of output node B of push-pull stage110rises, MOS transistor Q7is turned on, and node C is driven to the level of low-side power supply voltage −VL (the level determined by the on-resistances or current driving capabilities of MOS transistors Q5and Q7). When the voltage level of output node B of push-pull stage110lowers, MOS transistor Q7turns non-conductive. In this state, MOS transistor Q5charges node C and has the gate potential thereof boosted through the bootstrapping operation by capacitance element CP2, and node C is driven to the level of voltage VH. Therefore, node C changes between voltages VH and −VL.

Output drive stage130of the ratio-less bootstrap type includes N-channel MOS transistor Q8that charges a node D with a current supplied from high-side power supply line102in accordance with the signal on output node A of input stage100, N-channel MOS transistor Q12that discharges a current from node D to low-side power supply line104in accordance with output signal OUT on final output node150, N-channel MOS transistor Q13that turns conductive to discharge a node G to the voltage level of low-side power supply line104when the voltage level of node D is at the high level, a capacitance element CP3connected between nodes E and F, N-channel MOS transistor Q14discharging node F in accordance with the signal on output node B of push-pull stage110, N-channel MOS transistor Q10that charges the node F from high-side power supply line102in accordance with the signal from output node C of bootstrapping type drive stage120, N-channel MOS transistor Q9that is connected between high-side power supply line102and node E and has a gate connected to node F, N-channel MOS transistor Q11supplying a current from high-side power supply line102to output node150in accordance with the signal voltage on node F, and N-channel MOS transistor Q15that is selectively made conductive in accordance with the signal outputted from output node B of push-pull stage110, to drive final output node150to the level of voltage −VL.

In final output drive stage130of the ratio-less bootstrap type, of which detailed operations will be described below, a path of the current from high-side power supply line102to low-side power supply line104is cut off by utilizing delay in change of the signals, and accordingly the current consumption is reduced. Further, final output drive stage130of the ratio-less bootstrap type accurately produces output signal OUT changing between voltages VH and −VL.

FIG. 14is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 13. The operation of the level converting circuit shown inFIG. 13will now be described with reference toFIG. 14.

When input signal IN applied to input node1rises from reference voltage GND to high-level voltage of VDD, MOS transistor6in input stage100turns conductive to lower the level of node A from high-side power supply voltage VH to a voltage close to low-side power supply voltage −VL. It is assumed that MOS transistors Q1and6have the current driving capabilities or on-resistances adjusted such that the output offset voltage of input stage100can be substantially neglected.

In push-pull stage110, MOS transistor Q4turns conductive to discharge node B in accordance with the rising of voltage level of gate node9in input stage100, and lowers the voltage level of node B. Then, when the voltage level of output node A in input stage100lowers to the level of low-side power supply voltage −VL, the gate-source voltage of MOS transistor Q3lowers to or below the threshold voltage, and accordingly, MOS transistor Q3is turned off. Therefore, MOS transistor Q4discharges node B to the level of low-side power supply voltage −VL.

In bootstrapping type drive stage120, MOS transistor Q7transits towards the non-conductive state in accordance with the lowering of the voltage level of node B, and node C is charged by MOS transistor Q5, and through the bootstrap operation of capacitance element CP2, node C is charged to the level of high-side power supply voltage VH. In this state, node B is discharged to the level of low-side power supply voltage −VL so that MOS transistor Q7is kept in the non-conductive state.

Output drive stage130of the ratio-less bootstrap type operates as follows. First, output signal OUT is at the low level of low-side power supply voltage −VL, and MOS transistor Q12is in the non-conductive state. Output node A of input stage100is at the voltage level of low-side power supply voltage −VL, and MOS transistor Q8is also in the non-conductive state. In the previous cycle, node D attained the level of voltage (VH−Vthn) in accordance with input signal IN at the low level. In accordance with the signal on output node B of push-pull stage110, MOS transistors Q14and Q15are first set to the non-conductive state.

Then, when the voltage level of output node C of bootstrap-type drive stage120rises, MOS transistor Q10is turned on to charge the node F. In the operation of charging the node F by MOS transistor Q10, MOS transistor Q14is already in the off state in accordance with the potential on node B, and therefore a current is prevented from flowing from high-side power supply line102to low-side power supply line104through MOS transistors Q10and Q14.

When the voltage level of node F rises, MOS transistor Q11turns conductive to charge output node150to raise the voltage level of output signal OUT. In this operation of charging output node150, MOS transistor Q11turns conductive after MOS transistor Q15turns non-conductive in accordance with the signal on output node B in push-pull stage110. Therefore, no current path from high-side power supply line102to low-side power supply line104exists. When node D is maintained at the level of voltage of (VH−Vthn), node E is at the level of low-side power supply voltage −VL, and node F is charged to have its voltage level raised from low-side power supply voltage −VL to the voltage of (VH−Vthn).

When the voltage level of output signal OUT rises and the gate-source voltage of MOS transistor Q12exceeds its threshold voltage, MOS transistor Q12discharges node D to lower its voltage level, and MOS transistor Q13turns non-conductive.

When MOS transistor Q13turns non-conductive, MOS transistor Q9raises the voltage level of node E in accordance with the voltage level of node F. When the voltage of node F rises while node E is at the raised voltage level, MOS transistor Q10turns non-conductive. Accordingly, node F enters the floating state, and through capacitance coupling of capacitance element CP3, the voltage level of node F is raised to the voltage of (VH+ΔVB) in accordance with the rising of the voltage level of node E. Therefore, MOS transistor Q9charges node E to the level of voltage VH. In accordance with the boosting of voltage level of node F, the gate potential of MOS transistor Q11further rises and output signal OUT from output node150is quickly driven to the level of voltage VH.

Therefore, a current flows through a path of MOS transistors Q9and Q13in the operation of raising the voltage level of output signal OUT. However, the current consumption can be reduced by sufficiently reducing the current driving capabilities of these MOS transistors Q9and Q13. Further, DC current (flowing from high-side power supply line102to low-side power supply line104) flows through MOS transistors Q9and Q13only for a time period corresponding to a transition time of the output signal, and thus this time period can be made sufficiently short. By adequately enhancing the current driving capability of MOS transistor Q11, output signal OUT can be quickly driven to the level of voltage VH even when the load of output node150is large.

When input signal IN falls from high-level voltage VDD to the low-level voltage (reference voltage GND), the voltage level of node9in input stage100first attains the voltage level close to voltage −VL. The voltage level of node A rises, and the voltage level of node A attains high-side power supply voltage VH.

In accordance with the rising of voltage level of node A, MOS transistor Q3in push-pull stage110turns conductive to drive node B to the voltage level of (VH−Vthn). In this operation, MOS transistor Q4already turns non-conductive in accordance with the voltage level of node9. In the operation of charging node B, therefore, a current path from high-side power supply line102to low-side power supply line104does not exist.

When the voltage level of output node B in push-pull stage110rises, MOS transistor Q7in bootstrapping type drive stage120discharges the node C to lower its voltage level.

In final output stage130, MOS transistors Q14and Q15turn conductive in accordance with the rising of voltage level of output node B in push-pull stage110, and lower the voltage level at node F to the level of voltage −VL, and also lowers the voltage level of output signal OUT. Responsively, MOS transistors Q9and Q11turn conductive, and MOS transistor Q15drives the output signal OUT generated from output node150to the level of low-side power supply voltage −VL.

In accordance with the rising of voltage level of output node A in input stage100, MOS transistor Q8turns conductive to charge the node D to the voltage level of (VH−Vth), and responsively MOS transistor Q13turns conductive to drive the node E to the level of voltage −VL. When MOS transistor Q13is conductive, MOS transistor Q9already turns conductive in response to the potential lowering of node F responsive to the potential change of node B. When the voltage level of node E lowers, therefore, a path of current flowing through MOS transistors Q9and Q13does not exist.

When the voltage level of output signal OUT falls, MOS transistor Q12turns non-conductive. Before MOS transistor Q12turns non-conductive in response to fall of voltage level of output signal OUT, a current flows from high-side power supply line102to low-side power supply line104through MOS transistors Q8and Q12. However, output signal OUT is rapidly driven to low-side power supply voltage −VL, and therefore, an amount of the current flowing through MOS transistors Q8and Q12can be made sufficiently small.

In the steady state, a path for flowing a DC current from high-side power supply line102to low-side power supply line104does not exist in final output stage130. Therefore, MOS transistors Q11and Q15can have increased driving capabilities, and thus can quickly drive the final output node to change output signal OUT even when output node150is accompanied by a large output load capacitance.

Input stage100and bootstrapping type rive stage120are ratio circuits, and current flows through MOS transistors Q1and Q6as well as through MOS transistors Q5and Q7. However, in input stage100and bootstrapping type drive stage120, the voltage levels of nodes A and C change complementarily to each other. Therefore, a current flows only when one of input stage100and bootstrapping type drive stage120outputs a low-level signal in accordance with the logical level of input signal IN, and the power consumption thereof can be made substantially equal to that of the level converting circuit including only one bootstrapping type load circuit.

In the structure of the level converting circuit shown inFIG. 13, with the N-channel MOS transistors replaced with P-channel MOS transistors, and with the voltage polarities inverted by supplying the voltages −VL and VH to power supply lines102and104, respectively, a similar level converting circuit can be achieved.

According to the fifth embodiment of the invention, as described above, a ratio-less circuit is used to drive the final output node in accordance with the output signal of the level converting stage in the initial position. Thus, it is possible to implement the level converting circuit, which can quickly change the output signal with low current consumption.

FIG. 15shows a configuration of a main portion of a level converting circuit according to a sixth embodiment of the invention.FIG. 15shows a configuration of a conversion stage at an input initial stage, for driving the output node2in accordance with input signal IN. The conversion stage at input initial stage shown inFIG. 15may be combined with any one of the first to fifth embodiments. The conversion stage at input initial stage shown inFIG. 15includes an N-channel MOS transistor200that is provided between node9and low-side power supply node4and is selectively made conductive in accordance with the signal on output node2. Thus, MOS transistor200is used, e.g., in place of resistance element7of the level converting circuit shown inFIG. 1.

FIG. 16is a signal waveform diagram illustrating an operation of the level converting circuit shown inFIG. 15. Referring toFIG. 16, the operation of the conversion stage at the input initial stage shown inFIG. 15will now be described. When input signal IN is at the level of reference voltage GND, output node2is at the level of voltage VH, and MOS transistor200maintains node9at the level of low-side power supply voltage −VL.

When input signal IN rises from the low-level (GND) to the high level (VDD), the voltage level of node9rises so that MOS transistor6turns conductive to lower the voltage level of node2. The voltage level of output node2is higher than low-side power supply voltage −VL because a circuit portion for driving the output node2of the level converting stage is a ratio circuit. By sufficiently reducing the output offset voltage, MOS transistor200can be set to the non-conductive state. In this case, a leakage current merely flows in MOS transistor200, and the lowering of the voltage level of node9does not occur in contrast to the case of utilizing a resistance element. Thus, there is no restriction on the high-level time period of input signal IN, which improves flexibility of the circuitry.

Further, the gate potential of MOS transistor6can be kept constant, and accordingly, output node2is kept at a constant voltage level. Therefore, a problem of rising of the low-level voltage on output node2can be eliminated, and it is possible to improve an operating margin for the low-side voltage of the circuit receiving the voltage on output node2.

FIG. 17shows a modification of the sixth embodiment of the invention. InFIG. 17, P-channel MOS transistor16is used to convert the level of the high-level voltage of input signal IN. In this conversion stage at input initial stage, a P-channel MOS transistor202, which is selectively rendered conductive in response to the voltage on output node12, is connected between high-side power supply node3and gate node19of MOS transistor16. In other words, the input conversion stage shown inFIG. 17utilizes P-channel MOS transistor202responsive to the signal on output node12in place of current driving element17of the level converting circuit shown inFIG. 5.

In the configuration of the input conversion stage shown inFIG. 17, when input signal IN attains the low level and accordingly, capacitance element18lowers the voltage level of node19, node12is charged by MOS transistor16to attain the voltage level close to high-side power supply voltage VH. In this case, therefore, if the offset voltage of output node12is set to the voltage level maintaining MOS transistor202in the non-conductive state, MOS transistor202can be kept non-conductive. Accordingly, such a situation can be prevented that a charging current raises the voltage level of node19when input signal IN is at the low level, and thus the restriction on the low-level time period of input signal IN can be eliminated.

When input signal IN rises to the high level, node19is driven to the level of high-side power supply voltage VH by capacitance element18, and MOS transistor16turns non-conductive so that no adverse influence is exerted on the low-level voltage of output node12. In this state, MOS transistor202maintains node19at the level of high-side power supply voltage VH.

According to the sixth embodiment of the invention, as described above, the gate node of the output drive MOS transistor, which receives on its gate the input signal through the capacitance element, is connected to the MOS transistor receiving on its gate the voltage on the drive node of the output drive MOS transistor. Thus, it is possible to suppress the change in potential of the gate node of the output drive MOS transistor, and restrictions on the high- and low-level time periods of the input signal can be eliminated.

FIG. 18shows a configuration of a main portion of the level converting circuit according to the seventh embodiment of the invention. The level converting circuit shown inFIG. 18has further a resistance element210of a high resistance connected between gate node9and low-side power supply node4in the configuration of the level converting circuit shown inFIG. 15. Other configuration of the circuit shown inFIG. 18is the same as the level converting circuit shown inFIG. 15. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

Resistance element210has a sufficiently large resistance value RI. By utilizing resistance element210, the initial potential of gate node9is set to low-side power supply voltage −VL. Resistance element210has sufficiently large resistance value RI to have a driving current smaller than the leakage current of MOS transistor200. Accordingly, unnecessary change in potential level of gate node9in the steady state can be reliably suppressed, and the signal can be produced on output node2in accordance with input signal IN with the potential of gate node9accurately initialized.

Although not shown in the figure, the circuitry shown inFIG. 17can likewise be configured in accordance with the seventh embodiment of the invention such that a resistance element of a high resistance is connected in parallel with MOS transistor202. In such arrangement, the voltage level of gate node19can be initialized to high-side power supply voltage VH.

According to the seventh embodiment of the invention, as described above, the output drive MOS transistor, which receives on its gate the input signal through the capacitance element, is configured to have the gate connected to the resistance element (current limiting element) that has a high resistance and is connected in parallel with the MOS transistor receiving the output node potential on its gate. Thus, the gate potential of the output drive MOS transistor can be initialized to a predetermined voltage level.

FIG. 19shows a configuration of a main portion of the level converting circuit according to an eighth embodiment of the invention. The level converting circuit shown inFIG. 19includes, instead of resistance element210of a high resistance shown inFIG. 18, an N-channel MOS transistor220, which is rendered conductive in accordance with an output signal (power-on reset signal) POR of a Power-On Reset (POR) circuit230and has a gate node9coupled to low-side power supply node4. Other configuration of the level converting circuit shown inFIG. 19is the same as in the level converting circuit shown inFIG. 18. Corresponding portions are allotted with the same reference numerals, and description thereof is not repeated.

Power-on reset circuit230operates with operation power supply voltages of high- and low-side power supply voltages VH and −VL. When these voltages VH and −VL are supplied, power-on reset circuit230drives power-on reset signal POR to the H-level of voltage VH, and maintains the H-level for a predetermined period. In the steady state, power-on reset signal POR is maintained at the level of low-side power supply voltage −VL.

As shown inFIG. 20, both voltages VH and −VL are at the level of reference voltage GND before power up. When the power is turned on, high-side power supply voltage VH rises to the predetermined voltage level (VH), and low-side power supply voltage −VL attains the predetermined voltage level (−VL). When the voltages VH and −VL attain the predetermined voltage levels or become stable in response to the power on, power-on reset signal POR applied from power-on reset circuit230rises to the level of voltage VH. Responsively, MOS transistor220turns conductive to connect the gate node9to low-side power supply node4, and the gate node9is initialized to the level of voltage −VL.

When a predetermined time period elapses, power-on reset signal POR applied from power-on reset circuit230attains the level of voltage −VL, and MOS transistor220is turned off. In the normal operation, MOS transistor220is kept non-conductive, and accordingly exerts no adverse influence on the level converting operation on input signal IN.

FIG. 21schematically shows an example of the configuration of power-on reset circuit230shown inFIG. 19. InFIG. 21, power-on reset circuit230includes a VH-up detecting circuit240that receives the voltages VDD and GND as operation voltages and detects the power up of high-side power supply voltage VH, a VL-up detecting circuit242that receives the voltages VDD and GND as operation voltages and detects the power up of low-side power supply voltage VL, an NAND circuit244that receives voltages VDD and GND as operation power supply voltages and receives power-up detection signals PUPH and PUPL from the up detecting circuits240and242, respectively, a level converting circuit246for converting the level of the output signal of NAND circuit244, and a one-shot pulse generating circuit248for generating a pulse signal of one shot in response to the rising of an output signal MPOR of level converting circuit246.

VH-up detecting circuit240includes a capacitance element and a resistance element connected in series between the high-side power supply node and the ground node, for example. In accordance with the voltage change through the capacitance coupling of this capacitance element, VH-up detecting circuit240determines, e.g., with an inverter, whether high-side power supply voltage VH is made on, and drives power-up detection signal PUPH to the H-level upon power up.

VL-up detecting circuit242includes, for example, a resistance element and a capacitance element connected in series between the power supply node receiving voltage VDD and the low-side power supply node receiving low-side power supply voltage −VL, and detects the power-up of low-side power supply voltage through the capacitance coupling of the capacitance element. When voltage −VL is powered up, VL-up detecting circuit242drives the output signal PUPL to the H-level.

When voltage-up detection signals PUPH and PUPL are both at the H-level of voltage VDD, NAND gate244drives its output signal to the level of voltage GND. When at least one of the up detection signals PUPH and PUPL is at the low level, NAND circuit244generates a signal at the level of voltage VDD.

Level converting circuit246has the configuration shown inFIG. 1, for example, and converts the output signal of NAND circuit244to a signal changing between the voltages VH and −VL.

One-shot pulse generating circuit248operates with voltages VH and −VL being the operation power supply voltages. One-shot pulse generating circuit248produces a pulse signal of one shot in response to the rising of the signal MPOR received from level converting circuit246, to produce power-on reset signal POR.

FIG. 22is a signal waveform diagram illustrating an operation of power-on reset circuit230shown inFIG. 21. Referring toFIG. 22, the operation of power-on reset circuit23shown inFIG. 21will now be described.

In this power-on reset circuit230, it is assumed that the voltages VDD and GND are stabilized faster than the voltages VH and −VL.

When voltage VH is powered up and the voltage level thereof rises, VH-up detecting circuit240detects this voltage rising through the capacitance coupling of the internal capacitance element, and responsively raises power-up detection signal PUPH to the high level. Likewise, when voltage −VL is powered up and the voltage level thereof lowers, VL-up detecting circuit242detects this lowering of the voltage level through the capacitance coupling of the internal capacitance element, and drives power-up detection signal PUPL to the high level. When both the detection signals PUPH and PUPL attain the high level of voltage VDD, the output signal of NAND circuit244attains the low level of voltage GND.

Level converting circuit246has the same configuration as that shown inFIG. 1, for example, and inverts the logical levels of the output signal of NAND circuit244with the signal amplitude converted. Therefore, the signal MPOR outputted from level converting circuit246rises to the level of voltage VH in response to the falling of the output signal of NAND circuit244. In response to the rising of the signal MPOR, one-shot pulse generating circuit248drives the output signal POR to the level of voltage VH, and maintains it for a predetermined time period. When the predetermined time period elapses, one-shot pulse generating circuit248drives the signal POR to the level of voltage −VL.

According to the configuration of power-on reset circuit230shown inFIG. 21, therefore, power-on reset signal POR can be produced in the form of the one-shot pulse after both the voltages VH and −VL reach the predetermined voltage levels.

In addition, according to the configuration of power-on reset circuit230shown inFIG. 21, power-on reset signal POR can be produced regardless of the power-up sequence of the voltages VH and −VL after detecting circuits240and242detects the power-up of these voltages VH and −VL.

In the arrangement according to the eighth embodiment of the invention, all the N-channel MOS transistors in the configuration shown inFIG. 19can be replaced with the P-channel MOS transistors with power supply node4supplied with high-side power supply voltage VH, so that the amplitude of the high-side signal can be converted. In this case, the power-on reset signal, which is an inverted signal of the output signal POR of one-shot pulse generating circuit248shown inFIG. 21, is applied to the gate of the initializing P-channel MOS transistor.

According to the eighth embodiment of the invention, the internal node of the level converting circuit is initialized in accordance with the power-on reset signal, and thus can be accurately set to the predetermined voltage level. Further, in the normal operation mode, the internal node is set to the floating state, and the internal node can have the voltage level accurately set through capacitance coupling of the capacitance element.

The MOS transistors in the first to eighth embodiments are merely required to be field effect transistors, and may be MOS transistors formed on a semiconductor substrate or thin film transistors (TFT) formed on an insulating substrate such as glass.

According to the invention, as described above, the level converting circuit is formed of MOS transistors of the single kind, and the gate of the output drive transistor is driven through the capacitance element in accordance with the input signal. Therefore, the voltage on the source node of the output drive transistor can be outputted as the output signal of the output drive transistor independently of the voltage level of a corresponding logical level of the input signal. Accordingly, it is possible to implement the level converting circuit, which requires a decreased number of manufacturing steps, and can operate with low power consumption.