Semiconductor device including back-gated transistors and method of fabricating the device

A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device (e.g., a static random access memory (SRAM) device) including back-gated transistors, and more particularly, to a device which includes a back-gate transistor which may be fabricated using finFET technologies (e.g., a coupled backgate finFET SRAM).

2. Description of the Related Art

FIG. 1provides a circuit diagram illustrating a conventional six transistor (6-T) SRAM device100. As illustrated inFIG. 1, the conventional SRAM device100includes n-type field effect transistors (nFETs) N1-N4, and p-type field effect transistors (pFETs) P1-P2. The word line (wl) is coupled to the gates of nFETs N3, N4and the bit lines blt, blc are coupled to an arm of nFETs N3, N4, respectively.

In advanced semiconductor devices (e.g., such as the conventional SRAM device100), dopant fluctuations are becoming a serious problem in Vt (threshold voltage) control. As semiconductor devices become smaller and smaller, Vt control becomes more difficult. This problem greatly affects SRAM devices since the SRAM devices may be very small.

A known solution to this problem is to control the Vt by using back-gates in the semiconductor devices. One serious problem with this solution, however, is that the use of back-gates in semiconductor devices results in increased layout complexity, and therefore, higher cost. In addition, separately back gating the individual devices increases wiring densities and does not help in the layout compactness.

SUMMARY OF THE INVENTION

In view of the foregoing and other exemplary problems, disadvantages, and drawbacks of the aforementioned conventional systems and methods, it is a purpose of the exemplary aspects of the present invention to provide a memory cell and method of fabricating the memory cell which may be used to provide a semiconductor structure in which back-gates may be formed with relatively less layout complexity, and a method for forming the semiconductor structure.

In addition, present invention may help to increase the device density of the novel semiconductor structure. The present invention may also improve the stability of a device (e.g., an SRAM device) by coupling the back-gates of the proper nFET devices in the SRAM. In addition, the present invention may be used to apply a proper biasing condition.

The present invention includes a memory cell (e.g., static random access memory (SRAM) cell) which includes a plurality of back-gated nFETs, and a plurality of double-gated pFETs, which are operatively coupled to the plurality of nFETs.

In another exemplary aspect, a memory cell includes a plurality of back-gated, split gate n-type field effect transistors (nFETs), and a plurality of trigate p-type field effect transistors (pFETs), which are operatively coupled to the plurality of nFETs.

In still another exemplary aspect, a memory cell includes a plurality of back-gated, trigate n-type field effect transistors (nFETs) which are gated by a gate electrode formed below a body of the back-gated trigate FETs, and a plurality of trigate p-type field effect transistors (pFETs), which are operatively coupled to the plurality of nFETs.

In another aspect of the present invention, a static random access memory (SRAM) cell includes a plurality of back-gated field effect transistors (FETs) (e.g., nFETs), biasing of the back-gated FETs being adjustable to an operating condition of the memory cell, and a plurality of double-gated FETs (e.g., pFETs), which are operatively coupled to said plurality of back-gated FETs.

In another aspect of the present invention, an SRAM array includes a plurality of SRAM cells according to the exemplary aspects of the present invention, and a plurality of wordlines (e.g., and a plurality of bias lines) which are operatively coupled to the plurality of SRAM cells.

In another aspect of the present invention, a method of fabricating a back-gate semiconductor memory device includes forming a plurality of single gate finFETs on a semiconductor substrate, the finFETs (e.g., each of the finFETs) including a gate oxide, masking some of the plurality of single gate finFETs, etching the other of the plurality of single gate finFETs to expose the gate oxide, and wiring gates of the other of the plurality of single gate finFETs.

Referring now to the drawings,FIGS. 2-13Hillustrate the exemplary aspects of the present invention.

The present invention provides a compact, coupled backgating structure for a static random access memory (SRAM) device.

Referring again toFIG. 1, the inventors have recognized that by coupling the gates in the SRAM device (e.g., coupling the gates in the form of a finFET) the layout complexities can be reduced. In addition, the inventors have recognized that a forward bias that is larger than Vdd (e.g., a larger-than Vdd scheme) may help to improve the delay (e.g., in an active mode), while a reverse bias may lower the leakages of the SRAM cells in standby mode.

FIG. 2Aprovides a circuit diagram illustrating a memory cell200(e.g., a 6-T SRAM finFET cell) according to the exemplary aspects of the present invention. The pFETs (e.g., P1, P2) can be operating in double-gate mode, and the back-gates of the nFETs N1, N3(e.g., as a pair) and nFETs N2, N4(e.g., as a pair) can be connected together. The back-gates could be asymmetrical (e.g., formed with n+ front and back as p+). The memory cell200may include a coupled back-gate bias SRAM cell with forward bias exceeding Vdd and reverse bias below ground in a standby mode.

As illustrated inFIG. 2A, in the memory cell200, a word line (wl) could be coupled to the gates of nFETs N3, N4and the bit lines blt, blc could be coupled to an arm of nFETs N3, N4, respectively. Further, a body bias generator210may be coupled to the back-gates of nFETs N1, N2, N3and N4in the memory cell200. (It should be noted that the body bias generator210may be used to generate a bias voltage for a plurality of memory cells200. That is, a body bias generator210need not be provided for every memory cell200. It should also be noted that the pFETs P1, P2may include back-gated pFETs which may be biased appropriately for achieving good performance and stability.

In addition, a similar scheme (e.g., as that illustrated inFIG. 2A) could be used for stacked nFET devices to control the Vt of an nFET in active and standby mode for a 4-T cell and an 8-T cell.

FIGS. 2B-2Cillustrate a double-gate transistor250and a trigate transistor (e.g., a three gated transistor)260, which may be used in the memory cell200according to the exemplary aspects of the present invention. As illustrated inFIG. 2B, the double-gate transistor250(e.g., a finFET double-gate transistor) may include a substrate251(e.g., silicon, silicon-on-insulator (SOI), oxide, etc.), source252, drain253, front gate254and back-gate255. A common mode of operation of the double-gate FET is to switch the gates simultaneously. Another use of the two gates (e.g., three-gates) is to switch only one gate and apply a bias (e.g., a back-gate bias) to the second gate to dynamically alter the threshold voltage of the FET, in which case the double-gate FET may be described as a “back-gated FET” or “back-gate biased FET”. Similarly, the gates of the trigate transistor may be switched simultaneously or one of the gates may be biased in which case the trigate transistor may be described as a “back-gated FET” or “back-gate biased FET”. (It should be noted that a “double-gate” device may be defined as a device having two inversion channels (e.g., located on opposite sides of a finFET).

The channel region in the transistor250may include a fin-shaped bar of silicon, and the gates (e.g., front and back-gates254,255) may be wrapped around the silicon bar. The channel may therefore be controlled using the front and back-gates254,255.

As illustrated inFIG. 2C, the trigate transistor260may have a design similar to that of the double-gate transistor250(e.g., including a substrate261(e.g., silicon, silicon-on-insulator (SOI), oxide, etc.), source262, drain263, front gate264and back-gate265), but the transistor260also includes a top gate266which may also be used to control the channel.

In one exemplary embodiment, for example, the nFETs (e.g., N1-N4) may be split gate finFETs (e.g., back-gated split gate finFETs) and the pFETs (e.g., P1-P2) may be trigate transistors. In another exemplary embodiment, the nFETs (e.g., N1-N4) and pFETs (e.g., P1-P2) may be trigate FETs, the nFETs (e.g., back-gated trigate nFETs) being gated by a gate electrode formed below a body of the trigate FETs.

According to the exemplary aspects of the present invention, the memory cell200may include a semiconductor SRAM which includes at least one double-gate device with coupled back-gates with asymmetrical gates. The SRAM may include, for example, an SRAM finFET device structure where a pFET operates in double-gate symmetrical mode and the nFETs (e.g., at least one nFET) include asymmetrical double-gates.

The SRAM may also include an SRAM finFET asymmetrical back-gate structure with stacked nFETs. In addition, the SRAM back-gate bias can exceed the supply voltage in an active mode while it can be reduced below ground.

FIGS. 3A-3Cillustrate different biasing techniques which may be used according to the exemplary aspects of the present invention. Specifically,FIG. 3Aillustrates a memory device300having finFETs with external back-gate biasing,FIG. 3Billustrates a memory device310having finFETs with internal biasing (e.g., self-biasing) and external biasing, also referred to as mixed-mode back-gate biasing (e.g., internal and external back-gate biasing).FIG. 3Cillustrates another example of a memory device320having finFETs with mixed-mode back-gate biasing, according to the exemplary aspects of the present invention.

As illustrated inFIGS. 3A-3C, the cells included in the devices300,310,320(e.g., load cells305,315and325may include the memory cell (e.g., memory cell200) according the exemplary aspects of the present invention. (For simplicity, the notation for the FETs (e.g., pFETs P1, P2, and nFETs N1-N4) used inFIG. 2A, may be similarly used to describe the FETs illustrated inFIGS. 3A-3C).

As illustrated inFIG. 3A, the biasing of pass gate devices (e.g., N3, N4) and pull down devices (e.g., N1, N2) may be achieved using an external control signal. That is, when the wordline (e.g., Wl_n) goes high then the devices (e.g., N1-N4) are biased high decreasing the Vt of the devices, making them stronger. When the wordline is inactive, the biases for the devices (e.g., N1-N4) are “0” or “gnd” making the devices weak and less leaky.

FIG. 3Billustrates a mixed mode bias. That is, pull down devices (e.g., N1, N2) are self biased (e.g., gate input (from the internal node) drives the back-gate of the pull down). There is no need for external biasing with this arrangement. The back-gate of the passgate (e.g., N3, N4) is driven by the external signal activated by the wordline.

In the aspect illustrated inFIG. 3C, pass gate back biasing is done externally similar toFIG. 3Bwhile pull down device back-gate is driven by the inverted bitlines. That is, during standby mode, bitlines are pre-charged high and the bias to the pull down is “0”. However, when “0” is to be read then the pull down back-gate bias is “high” due to inverted bitline signal. This helps in reading or writing the data. The inverter used on the bitline can be supplied with higher vdd (vdd2) and lower gnd (gnd2).

In another embodiment, (e.g., a fully self-biased state which is not shown inFIGS. 3A-3C) the inverted bitline signal also drives the pass gate along with pull down.

It should be noted that the embodiments illustrated inFIGS. 3A-3Care merely illustrative and should not be considered limiting. That is, other embodiments are also possible.

Further,FIG. 3Dfurther illustrates an example of external biasing in the memory cell according to the exemplary aspects of the present invention. That is,FIG. 3Dillustrates an exemplary configuration for bias generation in a memory cell according to the present invention.

As illustrated inFIG. 3D, a bias generator395may be used to generate a bias voltage for the memory cell according to the exemplary aspects of the present invention. The external bias (e.g., bias—0. . . bias_n) in the memory cell may be derived from a prior stage of a wordline driver390(e.g., and NAND gates391receiving pre-decoded addresses1-4). The drivers can have VDD2(power) and gnd2(ground). Gnd2may be lower than gnd and Vdd2may be higher than VDD. This external bias may be used to drive the back-gates of the devices illustrated inFIGS. 3A-3C).

In short, the exemplary aspects of the present invention may provide a novel back-gate biasing scheme for stacked devices in an SRAM cell.

In the memory cell200, the pFETs P1, P2may be operating in double-gate mode. Further, control of Vt for four (4) nFETs by a back-gate biasing scheme by asymmetrical gates (e.g., n+/p+ polysilicon gates) may yield faster delays by forward body bias (FBB) and lower power by reverse body bias (RBB).

It should be noted that for double-gate (DG) devices, while there may be no benefit for a digital back-gate biasing (DBGB) scheme (e.g., Vgb (gate to body voltage)=VDD), or a lower-than DBGB scheme, a larger-than VDD biasing may improve the performance and reduce a leakage current.

As noted above, the body bias generator210for generating a bias voltage in the memory cell200may be derived through one stage before the wordline driver. Thus, it may set up the bias before a “read” operation or “write” operation for an active mode (e.g., bias≧Vdd). In addition, during a standby, the bias may be reduced to “0” or below “0”.

FIG. 4provides another circuit diagram illustrating another example of a memory cell400(e.g., 6T SRAM with double-gate FETs) according the exemplary aspects of the present invention. A switch410may be coupled to a back-gate of nFETs N1, N3which switches between active (e.g., FBB>VDD) and standby (e.g., RBB<0) modes, and a switch420may be coupled to a back-gate of nFETs N2, N4which switches between active and standby modes. (It should be noted that the switches410,420illustrated inFIG. 4may be used for switching a bias voltage to a plurality of memory cells400. That is, switches410,420need not be provided for every memory cell400.)

In the memory cell400, the double-gate (DG) mode may perform better than single gate (SG) mode, but larger-than-VDD may speed up the circuit and reduce the power due to aggressive Vt modulation.

The present invention may provide larger-than-VDD back-gate biasing for an asymmetrical double-gate (DG). In this case, only one channel (e.g., about two times higher than that of bulk) may be used, resulting in a high performance. Further, the back-gate may effectively modulate Vt, yielding higher Ion (e.g., “on” current) by FBB but lower Ioff (e.g., “off” current) by RBB. In addition, there may be a negligible Igate (e.g., gate current) for a p+ polysilicon gate at FBB due to a lower field and a higher potential barrier.

Further, a symmetrical DG turns ON when one of gates is ON. This may not be applicable due to a leakage concern.

Further, for bulk-Si FETs with larger-than-VDD scheme, a triple-well process may be used. Thus, there may be an area penalty and process complexity. Specifically, for FBB, there may be an exponential increase in junction diode current, which may fight against the linearly-increased Ion, causing a slowing down of charging/discharging. Further, increasing junction capacitance (Cj) may cause a degraded speed. Further, there may be a degraded sub-threshold swing (S) due to the reduced depletion width (td).

Further, for RBB, band-to-band tunneling current may be increased and gate-induced drain leakage (GIDL) may occur for |bias voltage (Vbs)|>30% VDD. Further, the device may be less efficient in shorter gate lengths (L) due to a lower body factor for lower Vt, worsening short channel effects (SCEs).

Referring again to the drawings,FIG. 5provides a graph500illustrating an I-V simulation for a scheme (e.g,. larger-than-VDD scheme). Specifically, the graph500illustrates a physics-based numerical simulation for 20 nm DG devices with back-gate biasing. As illustrated inFIG. 5, FBB (e.g., VGb (gate to body voltage)=0.8, 0.9, 1.0V) may result in Ion improvement. Further, RBB (e.g., VGb=0, −0.1, −0.2 V) may result in Ioff reduction, but due to the difficulty of lower-than-GND, GND could be used.

FIGS. 6A-6Bprovide graphs600,610, illustrating Ion and Ioff simulation for the scheme (e.g., a larger-than-VDD scheme), respectively. As illustrated inFIGS. 6A-6B, for DG devices with back-gate biasing, FBB with 0.2 V-larger-than VDD may result in about 25% improvement of Ion, and RBB with −0.2V may result in more than a 3× (e.g., three times) reduction of Ioff. Further, 20-40% faster read delays for 6T SRAM may be realized for 0.1-0.2 V-larger-than-VDD FBB scheme by physics-based numerical simulation.

FIG. 7provides a graph700illustrating a simulation of a read performance for a memory cell (e.g., 6T SRAM) according to the present invention. As illustrated inFIG. 7, 20% to 40% faster read delays for 6T SRAM may be predicted for 0.1 to 0.2 V-larger than VDD FBB scheme by physics-based numerical simulation.

FIG. 8is a circuit diagram illustrating a memory cell800which is a practical application of a scheme (e.g., larger-than-VDD scheme) according to the exemplary aspects of the present invention. Due to the process difficulty of the negative bias generator, FBB (e.g., only FBB) could be used to improve the circuit performance (e.g., without increasing a leakage power). As illustrated inFIG. 8, the memory cell800according to the exemplary aspects of the present invention may include a switch810coupled to a back-gate of nFETs N1, N3and switching between active (e.g., FBB>VDD) and standby (e.g., gnd) modes, and a switch820coupled to a back-gate of nFETs N2, N4and switching between active and standby modes.

Further,FIGS. 3A-3Cillustrate different biasing techniques (e.g., external back-gate biasing and mixed-mode back-gate biasing) which are practical applications of a scheme (e.g., larger-than-VDD scheme) according to the exemplary aspects of the present invention.

FIG. 9is a circuit diagram illustrating a memory cell900which may show the broad applicability of the scheme (e.g., larger-than-VDD scheme) according to the exemplary aspects of the present invention. Specifically, the scheme may be used, for example, for 4T, 8T and 6T SRAM cells.FIG. 9, for example, illustrates a memory cell900which is an 8T SRAM cell having nFETs N5, N6having back-gates coupled to a switch910switching between an active mode (e.g., FBB>VDD) and a standby mode (e.g., GND). Further, the gate of nFET N5is coupled to the read word line Rwl, and the gate of nFET N6is coupled to an arm of pFET P2. It should be noted that the bold arrow inFIGS. 2,4,8and9illustrates the current path from the bitline fully charged to Vdd when pulled down to “0”.

FIG. 10illustrates a method1000of fabricating a memory cell (e.g., a 6T SRAM cell utilizing double-gate finFETs) according to the exemplary aspects of the present invention. As illustrated inFIG. 10, the method1000includes forming (1010) a plurality of single gate finFETs on a semiconductor substrate, each of the finFETs including a gate oxide, masking (1020) some (e.g., a first portion) of the plurality of single gate finFETs, etching (1030) the other (e.g., a second portion) of the plurality of single gate finFETs to expose the gate oxide, and wiring (1040) the gates of the other of the plurality of single gate finFETs. (It should be noted that a “single gate” device may be construed to include a device with two channels (or three channels in the case of the trigate transistor) and a single piece of polysilicon.)

FIGS. 11A-11Billustrate exemplary layouts (e.g., plan views) for a memory cell (e.g., a 6T SRAM cell utilizing double-gate finFETs) according to the exemplary aspects of the present invention. Specifically,FIG. 11Aillustrates an exemplary layout for a memory cell1150having a shared back-gate bias for transfer and pull-down devices. The memory cell1150includes wordline (W/L)1101, back-gate bias1102, ground (Gnd)1103, and Vdd1104. The cell1150also includes bit lines B/L1105and B/L(bar)1106.FIG. 11Aalso illustrates pull-up devices1107having strapped front/back-gates.

FIG. 11Billustrates an exemplary layout for a memory cell1160having separate back-gate biases for transfer and pull-down devices. The memory cell1160includes wordline (W/L)1101, transfer back-gate bias1102a, pull down back-gate bias1102b, ground (Gnd)1103, and Vdd1104. The cell110also includes bit lines B/L1105and B/L(bar)1106.FIG. 11Balso illustrates pull-up devices1107(e.g., pFETs) having strapped front/back-gates (It should also be noted thatFIGS. 11A and 11Billustrate the devices1107(e.g., pFETs) with two gates that are strapped together which allows for one double-gate process with separate front and back gates to be used for several of the devices (e.g., all of the devices in the memory cell). In the mixed cases where separate and combined gates are used, there can be more process complexity.)

FIGS. 11C-11Dillustrate exemplary layouts (e.g., plan views) for a memory cell (e.g., a 6T SRAM cell utilizing single gate finFETs1198and double-gate finFETs1199) according to the exemplary aspects of the present invention. Specifically,FIG. 11Cillustrates an exemplary layout for a memory cell1170having a shared back-gate bias for transfer and pull-down devices. The memory cell1170includes wordline (W/L)1101, back-gate bias1102, ground (Gnd)1103, and Vdd1104. The cell1170also includes bit lines B/L1105and B/L(bar)1106.

FIG. 11Dillustrates an exemplary layout for a memory cell1180having separate back-gate biases for transfer and pull-down devices. The memory cell1180includes wordline (W/L)1101, transfer back-gate bias1102a, pull down back-gate bias1102b, ground (Gnd)1103, and Vdd1104. The cell1170also includes bit lines B/L1105and B/L(bar)1106.

FIGS. 11A-11Dalso include a legend to help identify the features of the memory cell1150. For example, inFIG. 11A, the wordline1101, back-gate bias1102, ground1103and Vdd1104may be formed by depositing metal M2, the bitlines1105,1106may be formed by depositing metal M1, and so forth.

Further, the legend (e.g., polysilicon gate (PC), recessed oxide (RX), first metal layer (M1), contact (CA), block P (BP), N well (NW), upper level contact (V1) and second metal layer (M2), etc.) is included to illustrate an exemplary construction of the memory cell, but should not be considered limiting.

FIGS. 12A-12Efurther illustrate the method1000of fabricating a memory cell1200according to the exemplary aspects of the present invention. Specifically,FIGS. 12A-12Eillustrate a method1000of fabricating a memory cell1200which includes single gate finFETs and double-gate finFETs.

FIG. 12Ais a plan view of the memory cell1200having source1210, gate1220and drain1230.FIG. 12Bis a cross-sectional view (e.g., a view along the channel (the source/drain regions are into and out of the page) about line A-A′ inFIG. 12A.

As noted above, in the method1000, single gate finFETs may be formed using techniques (e.g., channels may be created by an sidewall image transfer (SIT) mask, diffusion mask, etc.). Fin spacing is not necessarily on any particular pitch. The memory cell1200may include a substrate (e.g., silicon)1240, bulk oxide (e.g., silicon oxide)1250, and a gate1280which includes a fin body1282, a gate oxide (e.g., silicon oxide)1281and gate electrode (e.g., polysilicon)1283.

As illustrated inFIG. 12C, the method1000further includes applying a mask to fins that will become double-gate finFETs. Specifically, as illustrated inFIG. 12C, the resist (e.g., mask)1290may be applied, leaving a mask opening1291.

Further, as illustrated inFIG. 12D, the method100may further include etching (e.g., reactive ion etching (RIE) an exposed gate1295(e.g., endpoint on oxide). The resist (e.g., mask may also be removed.

As illustrated inFIG. 12E, gates (e.g., separate gates) may be wired (e.g., using conventional wiring or sidewall image transfer (SIT) wiring). For example,FIG. 12Eillustrates wires (e.g., SIT wires)1299which may be used to wire the gates in the memory cell. The formation of the wires (e.g., SIT wires)1299may be according to the process disclosed in IBM Docket No. BUR920040165US1 (U.S. patent application Ser. No. 10/907,971), which is commonly assigned with the present invention and incorporated by reference herein.

FIGS. 13A-13Hillustrate a method1300of fabricating a memory cell according to another aspect of the present invention. Specifically, a layer of silicon1304may be formed on an insulator (e.g., silicon oxide formed on silicon1301)1302to form an SOI wafer (FIG. 13A). A portion of the silicon layer1304may be patterned and thinned (e.g., using poly-buffered localized oxidation of silicon (e.g., LOCOS oxidation) and etch) (FIG. 13B). Conformal silicon dioxide1306may be deposited on the patterned layer1304(FIG. 13C).

The silicon dioxide1306maybe etched to form fins1308(FIG. 13D). The gate electrode1310(e.g., polysilicon) may be deposited and planarized (e.g., using etchback/CMP) (FIG. 13E). The back-gate electrode may be etched until a tall fin oxide1312is exposed (FIG. 13F). The electrode material (e.g., polysilicon)1310may be patterned and etched (FIG. 13G). Sources and drains (not shown) may be formed and wires1314(e.g., SIT wires) may be formed (FIG. 13H). As illustrated inFIG. 13H, the method1300may result in nFETs (split gate)1350and pFETs (double-gate)1360.

In short, the memory cell according to the exemplary aspects of the present invention, may include a plurality of nFETs which may include an asymmetric gate workfunction. In particular, the plurality of pFETs may operate in double-gate symmetrical mode, and the plurality of nFETs may include asymmetrical double-gates. Further, the memory cell may include a finFET asymmetrical back-gate structure, the plurality of nFETs including a plurality of stacked nFETs. In addition, in the memory cell, a back-gate bias can exceed a supply voltage in active mode and can be reduced below ground (e.g., in a standby mode).

Another aspect of the present invention includes a static random access memory (SRAM) cell, including a plurality of back-gated FETs including back-gate biasing adjusted to the operating conditions of the cell, and a plurality of double-gated FETs. The back-gate biasing may be reverse biased for low power during a standby operation, or forward biased for high speed during a read operation.

With its unique and novel features, the present invention provides a novel semiconductor structure in which back-gates may be formed with relatively less layout complexity. The present invention also provides a method for forming the novel semiconductor structure. The present invention may also help to increase the device density of the novel semiconductor structure, improve the stability of an SRAM device by coupling the back-gates of the proper nFET devices in the SRAM, and may also be used to apply a proper biasing condition.

The present invention may also be used to provide Vt tailoring, Vt adjustment, preventing Vt scatter in SRAM based on operation, high performance, low leakage and improved power. The present invention may also be especially applicable in logic devices, analog devices and phase locked loop (PLL) circuits.

While the invention has been described in terms of one or more exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Specifically, one of ordinary skill in the art will understand that the drawings herein are meant to be illustrative, and the design of the inventive assembly is not limited to that disclosed herein but may be modified within the spirit and scope of the present invention.

Further, Applicant's intent is to encompass the equivalents of all claim elements, and no amendment to any claim the present application should be construed as a disclaimer of any interest in or right to an equivalent of any element or feature of the amended claim.