RF amplification device with power protection during high supply voltage conditions

A radio frequency (RF) amplification device comprises an RF amplification circuit, and a dynamic level shifter (DLS) circuit coupled between a supply voltage and the RF amplification circuit. The DLS circuit is configured to provide a first shifted voltage to the RF amplification circuit via a first diode when the supply voltage is above a first threshold voltage level. The DLS circuit is further configured to provide a second shifted voltage to the RF amplification circuit via a first shunt transistor when the supply voltage is below the first threshold voltage level, wherein the supply voltage less the second shifted voltage is less than the supply voltage less the first shifted voltage.

FIELD OF THE DISCLOSURE

The field of the disclosure is amplifier circuits, including voltage regulation circuits for limiting the output power of one or more amplifiers in a series of amplifiers.

BACKGROUND

Conventional mobile communication circuits often include two stage and/or three stage amplifier circuits comprising a series of amplifiers. These may be constant gain or variable gain amplifiers. Constant gain amplifiers can be damaged under high supply voltage (e.g., high battery voltage) conditions that may occur as a result of supply current surges. For example, some cellular phones use batteries including three 1.5 volt cells in series, yielding a maximum theoretical voltage of 4.5 volts. After the cell phone is turned on, battery voltage (Vbat) may be 4.25 volts for a few seconds (for a short time at start up). Similarly, charging the battery during use may cause relatively high battery voltages. However, most of the time, the battery voltage is about 3.5 volts during operation. Thus, many circuits, such as constant gain amplifiers, are designed to operate efficiently at a nominal battery voltage (Vbatnom) of 3.5 volts. In these designs, a battery voltage in excess of Vbatnom may cause a maximum output power that exceeds physical limits (design limits) of a constant gain amplifier. If the constant gain amplifier is designed (tuned) for operating with a nominal battery voltage of 3.5 volts, then the constant gain amplifier may be damaged if a battery voltage of 4.25 volts is received. Further, the constant gain amplifiers can also be damaged by high input RF drive levels. The RF-based damage can be a function of both battery voltage and input RF drive levels.

Thus, amplifier topologies and techniques are needed to protect the constant gain amplifier from supply voltage conditions exceeding design limits.

SUMMARY

The field of the disclosure is amplifier circuits, including voltage regulation circuits for limiting the output power of one or more amplifiers in a series of amplifiers. In one embodiment, a radio frequency (RF) amplification device includes an RF amplification circuit, and a dynamic level shifter (DLS) circuit coupled between a supply voltage and the RF amplification circuit. The DLS circuit is configured to provide a first shifted voltage to the RF amplification circuit via a first diode when the supply voltage is above a first threshold voltage level. The DLS circuit is further configured to provide a second shifted voltage to the RF amplification circuit via a first shunt transistor when the supply voltage is below the first threshold voltage level. Further, the supply voltage less the second shifted voltage is less than the supply voltage less the first shifted voltage.

In one embodiment, the first shunt transistor is configured to short-circuit the first diode when the supply voltage is below the first threshold voltage level. A cathode of the first diode may be coupled to the RF amplification circuit and a source of the first shunt transistor, while an anode of the first diode may be coupled to a drain of the first shunt transistor. A gate of the first shunt transistor may be coupled to a voltage reference. The first diode may be a PIN diode, and the first shunt transistor may be one of a depletion mode n-type field effect transistor (FET) and a depletion mode n-type pseudomorphic high electron mobility transistor (pHEMT).

In one embodiment, the DLS circuit is further configured to (1) provide the first shifted voltage via the first diode and a second diode that is coupled in series with the first diode; (2) provide the second shifted voltage via the first shunt transistor and the second diode when the supply voltage is between the first threshold voltage level and a second threshold voltage level; and (3) provide a third shifted voltage to the RF amplification circuit via a second shunt transistor when the supply voltage is below the second threshold voltage level. The supply voltage less the third shifted voltage is less than the supply voltage less the second shifted voltage.

The first shunt transistor may be configured to short-circuit the first diode when the supply voltage is below the first threshold voltage level, while the second shunt transistor may be configured to short-circuit the first diode and the second diode when the supply voltage is below the second threshold voltage level. The first shifted voltage may be the supply voltage less a forward voltage drop of the first diode and a forward voltage drop of the second diode. Further, the second shifted voltage may be the supply voltage less the forward voltage drop of the second diode; and the third shifted voltage may be approximately equal to the supply voltage.

The cathode of the first diode may be coupled to the RF amplification circuit, the source of the first shunt transistor, and a source of the second shunt transistor. The anode of the first diode may be coupled to a cathode of the second diode and to the drain of the first shunt transistor, while an anode of the second diode may be coupled to the supply voltage and a drain of the second shunt transistor. The gate of the first shunt transistor may be coupled with a voltage reference, while a gate of the second shunt transistor may be coupled with a ground. The first diode may be a PIN diode and the second diode may be a Schottky barrier diode, while the first shunt transistor may be one of a depletion mode n-type field effect transistor (FET) and a depletion mode n-type pseudomorphic high electron mobility transistor (pHEMT). Further, the second shunt transistor may also be one of a depletion mode n-type FET and a depletion mode n-type pHEMT.

DETAILED DESCRIPTION

FIG. 1illustrates one embodiment of an RF amplification device10. The RF amplification device10includes an RF amplification circuit11that includes a plurality of RF amplifier stages (referred to generically as element12, and specifically as elements12A-12C) coupled in cascade. Accordingly, each of the plurality of RF amplifier stages12is operable to provide amplification to an RF signal14. In other words, by being coupled in cascade, the RF amplifier stages12provide amplification to the RF signal14in sequence.

The RF amplification device10shown inFIG. 1has an initial RF amplifier stage12A, an intermediate RF amplifier stage12B, and a final RF amplifier stage12C. However, other embodiments of the RF amplification device10may include any number of RF amplifier stages12greater than or equal to two (2). The initial RF amplifier stage12A is the RF amplifier stage12at a beginning of the sequence. The final RF amplifier stage12C is the RF amplifier stage12at an end of the sequence. Since at least two RF amplifier stages12are needed to provide cascaded RF amplifier stages12, the RF amplification device10includes at least the initial RF amplifier stage12A and the final RF amplifier stage12C. However, the number of RF amplifier stages12may be any integer greater than or equal to two (2). As such, there may be any number of intermediate RF amplifier stages, like the intermediate RF amplifier stage12B, coupled in cascade between the initial RF amplifier stage12A and the final RF amplifier stage12C. In the embodiment illustrated inFIG. 1, the RF amplification device10has three RF amplifier stages12. Thus, one intermediate RF amplifier stage12B is coupled in cascade between the initial RF amplifier stage12A and the final RF amplifier stage12C.

Since the RF amplifier stages12are coupled in cascade, the RF amplifier stages12provide amplification to the RF signal14in a sequence. Accordingly, the initial RF amplifier stage12A initially provides amplification to the RF signal14in accordance with an amplifier gain Ginitial. Once the RF signal14is amplified by the initial RF amplifier stage12A in accordance with the amplifier gain Ginitial, the intermediate RF amplifier stage12B amplifies the RF signal14in accordance with an amplifier gain Gintermediate. Once the RF signal14is amplified by the intermediate RF amplifier stage12B in accordance with the amplifier gain Gintermediate, the final RF amplifier stage12C amplifies the RF signal14in accordance to an amplifier gain Gfinal. As such, an aggregated amplifier gain of the plurality of RF amplifier stages12as a whole may be described as Ginitial*Gintermediate*Gfinal. In other words, an amplifier gain of the RF amplification circuit11is the aggregated amplifier gain of the plurality of RF amplifier stages12.

In the particular embodiment shown inFIG. 1, the initial RF amplifier stage12A has an input terminus16A and an output terminus18A. The intermediate RF amplifier stage12B has an input terminus16B and an output terminus18B. The final RF amplifier stage12C has an input terminus16C and an output terminus18C. With regard to the term “terminus,” terminus refers to any component or set of components configured to input and/or output RF signals. For example, inFIG. 1, the RF amplification device10is illustrated as receiving the RF signal14as a single-ended signal. Thus, the input termini16A,16B,16C, and the output termini18A,18B,18C may each be a single-ended terminal or node. However, in other embodiments, the RF signal14may be received as a differential signal. In this embodiment, the input termini16A,16B,16C, and the output termini18A,18B,18C may each be a pair of terminals or nodes configured to receive and/or transmit differential signals.

The RF amplification device10shown inFIG. 1includes an input terminus20to receive the RF signal14from upstream RF circuitry. The input terminus16A of the initial RF amplifier stage12A is coupled to receive the RF signal14from the input terminus20. The RF amplification device10shown inFIG. 1also has an output terminus22. The output terminus18C of the final RF amplifier stage12C is coupled to the output terminus22so as to provide the RF signal14after amplification to downstream RF circuitry. As a result, the RF amplifier stages12are coupled in cascade between the input terminus20and the output terminus22.

To amplify the RF signal14in accordance with the amplifier gain Ginitial, the initial RF amplifier stage12A receives the RF signal14at the input terminus16A. Once the initial RF amplifier stage12A has provided amplification to the RF signal14in accordance with the amplifier gain Ginitial, the initial RF amplifier stage12A transmits the RF signal14from the output terminus18A. The RF signal14is then received by the input terminus16B of the intermediate RF amplifier stage12B. Once the intermediate RF amplifier stage12B amplifies the RF signal14in accordance with the amplifier gain Gintermediate, the intermediate RF amplifier stage12B transmits the RF signal14from the output terminus18B. The final RF amplifier stage12C then receives the RF signal14at the input terminus16C and amplifies the RF signal14in accordance with the amplifier gain Gfinal. Once the final RF amplifier stage12C has provided amplification to the RF signal14in accordance with the amplifier gain Gfinal, the final RF amplifier stage12C transmits the RF signal14from the output terminus18C. The RF signal14may then be transmitted by the output terminus22to downstream RF circuitry, such as the load L.

To provide power for amplification, each of the RF amplifier stages12receives a supply voltage Vsupply. The power provided by the supply voltage Vsupplyis then transferred to the RF signal14by each of the RF amplifier stages12in accordance with its respective amplifier gain, Ginitial, Gintermediate, and Gfinal. However, note that as the RF signal14progresses through the sequence, each of the RF amplifier stages12handles an increasing amount of power. Therefore, the initial RF amplifier stage12A handles the least amount of power, since it receives the RF signal14prior to amplification and transmits the RF signal14amplified only in accordance with the amplifier gain Ginitial. When the intermediate RF amplifier stage12B receives the RF signal14, the RF signal14has already been amplified by the amplifier gain Ginitial. The intermediate RF amplifier stage12B further amplifies the RF signal14in accordance with the amplifier gain Gintermediate. Thus, the intermediate RF amplifier stage12B transmits the RF signal14amplified in accordance with the amplifier gain Ginitial*Gintermediate. As a result, the intermediate RF amplifier stage12B handles an intermediate amount of power. The final RF amplifier stage12C receives the RF signal14amplified in accordance with the aggregate amplifier gain Ginitial*Gintermediate. As such, when the final RF amplifier stage12C further amplifies the RF signal14by the amplifier gain Gfinal, the final RF amplifier stage12C transmits the RF signal14amplified in accordance with the aggregate amplifier gain of Ginitial*Gintermediate*Gfinal. As such, the final RF amplifier stage12C handles the most power.

Each RF amplifier stage12is configured to provide amplification so that it may handle the appropriate power levels. For example, the RF amplifier stages12may include a transistor, a network of transistors, op-amps, and/or any other type of suitable RF amplification component. Often, the initial RF amplifier stage12A and the intermediate RF amplifier stage12B are classified as “driver” RF amplifier stages12. In some embodiments, each of the driver RF amplifier stages12may have a single transistor or a pair of transistors to provide amplification. However, since the final RF amplifier stage12C handles the most power, some embodiments of the final RF amplifier stage12C may include arrays of transistors or stacks of transistors in order to handle the power levels seen by the final RF amplifier stage12C.

Referring again toFIG. 1, a voltage regulation circuit24is coupled to provide a regulated voltage VREGto the initial RF amplifier stage12A (i.e., one of the driver RF amplifier stages). The voltage regulation circuit24is configured to generate the regulated voltage VREGfrom a supply voltage VS. The supply voltage VSmay be a power source voltage, such as a battery voltage, or a bias voltage from a supply control network. Since the RF amplifier stages12of the RF amplification circuit11are configured to provide amplification at a particular supply level, under certain high RF input power and supply voltage conditions, a maximum output power of the RF amplification circuit11can be beyond the physical limits of the final RF amplifier stage12C. As a result, this excess in output power will degrade the robustness of the RF amplification circuit11. The voltage regulation circuit24operates to improve the robustness of the RF amplification circuit12by limiting the maximum output power and thus preventing damage and degradation at the final RF amplifier stage12C.

More specifically, the maximum output power of the RF amplification circuit11is set based on the regulated voltage VREG. While the supply voltage Vs is below a threshold voltage level, the voltage regulation circuit24is configured to drive the regulated voltage VREGto approximately a first voltage level. The threshold voltage level of the supply voltage VSis determined to be a level of the supply voltage VSwhere it is safe to operate the RF amplification circuit11and the final RF amplifier stage12C. While the regulated voltage VREGis maintained as approximately constant at a first voltage level, the maximum output power of the RF amplification circuit11can vary as different amount of current may be provided to the RF amplification circuit11. However, the regulated voltage VREGat the first voltage level may cause output power levels at the initial RF amplifier stage12A to result in excessive power levels at the final RF amplifier stage12C. Accordingly, while the supply voltage VSis above the threshold voltage level, the voltage regulation circuit24is configured to drive the regulated voltage VREGbelow the first voltage level such that the maximum output power of the RF amplification circuit11is provided approximately at a first power level. The first power level is a power level where the maximum output power of the RF amplification circuit11is at safe levels for operation of the final RF amplifier stage12C. As such, in this case, the voltage regulation circuit24varies the regulated voltage VREGbelow the first voltage level and based on the supply voltage VSin order to maintain the maximum output power of the RF amplification circuit11at the first power level.

To generate the regulated voltage VREG, the voltage regulation circuit24is configured to generate a control reference CR endogenously from the supply voltage VS. The control reference CR indicates a target regulated voltage. Accordingly, rather than receiving a control reference (not shown) generated externally from the voltage regulation circuit24in order to set the regulated voltage VREGgenerated by the voltage regulation circuit24, the voltage regulation circuit24is configured to generate the control reference CR from the supply voltage VSso that the control reference CR is endogenous to the voltage regulation circuit24itself. Thus, as the control reference CR changes, so does the regulated voltage VREGgenerated by the voltage regulation circuit24.

As such, to provide the behavior described above with respect to the threshold voltage level and the supply voltage VS, the voltage regulation circuit24is configured to set the control reference CR such that the control reference CR indicates that the target regulated voltage is set approximately at the first voltage level in response to the supply voltage VSbeing below the threshold voltage level. Furthermore, the voltage regulation circuit24is configured to set the control reference CR such that the control reference CR indicates that the target regulated voltage is below the first voltage level so that the voltage regulation circuit24maintains the maximum output power of the RF amplification circuit11approximately at the first power level in response to the supply voltage VSbeing above the threshold voltage level. The voltage regulation circuit24is configured to drive the regulated voltage VREGto the target regulated voltage indicated by the control reference CR. Thus, while the supply voltage VSis below a threshold voltage level, the voltage regulation circuit24is configured to drive the regulated voltage VREGto approximately the first voltage level. Also, the voltage regulation circuit24is configured to drive the regulated voltage VREGbelow the first voltage level such that the maximum output power of the RF amplification circuit11is provided approximately at the first power level while the supply voltage VSis above the threshold voltage level.

In this embodiment, each of the RF amplifier stages12includes a supply terminus (referred to generically as element “26” and specifically as elements26A-26C). More specifically, the initial RF amplifier stage12A includes a supply terminus26A, the intermediate RF amplifier stage12B includes a supply terminus26B, and the final RF amplifier stage12C includes a supply terminus26C. At each of the supply termini26, the RF amplifier stage12receives a biasing voltage for amplification of the RF signal14by the RF amplifier stage12. As shown inFIG. 1, the initial RF amplifier stage12A has the supply terminus26A coupled to receive the regulated voltage VREG. The intermediate RF amplifier stage12B has the supply terminus26B coupled to receive the supply voltage VS, and the final RF amplifier stage12C has the supply terminus26C coupled to receive the supply voltage VS. Thus, in this case, the voltage regulation circuit24only controls the initial RF amplifier stage12A. In an alternative embodiment, the voltage regulation circuit24only provides the regulated voltage VREGat the supply terminus26B of the intermediate RF amplifier stage12B, and thus only controls the intermediate RF amplifier stage12B instead of the initial RF amplifier stage12A.

Additionally, each of the RF amplifier stages12shown inFIG. 1also includes a grounding terminus (referred to generically as element “28” and specifically as elements28A-28C). More specifically, the initial RF amplifier stage12A includes a grounding terminus28A, the intermediate RF amplifier stage12B includes a grounding terminus28B, and the final RF amplifier stage12C includes a grounding terminus28C. At each of the grounding termini28, the RF amplifier stage12is connected to ground.

Referring now toFIG. 1andFIG. 1A,FIG. 1Aillustrates one embodiment of a curve implemented by the voltage regulation circuit24. As shown byFIG. 1A, the curve maps the supply voltage VSto the regulated voltage VREG. As shown inFIG. 1A, while the supply voltage VSis below the threshold voltage level TVL, the voltage regulation circuit24is configured to drive the regulated voltage VREGto approximately the first voltage level FVL. Also, the voltage regulation circuit24is configured to drive the regulated voltage VREGbelow the first voltage level FVL while the supply voltage VSis above the threshold voltage level TVL.

Accordingly, the voltage regulation circuit24is configured so that the target regulated voltage indicated by the control reference CR is set as a function of the supply voltage VSin response to the supply voltage VSbeing above the threshold voltage level TVL. In this example, the function of the supply voltage Vs decreases the target regulated voltage indicated by the control reference CR as the supply voltage VSincreases. The function shown inFIG. 1Ais approximately linear and thus results in the regulated voltage VREGbeing inversely proportional to the supply voltage VS. This function maintains the maximum output power of the RF amplification circuit11approximately at the first power level. The target regulated voltage indicated by the control reference CR, and thus the regulated voltage VREGis below the first voltage level FVL while the supply voltage VSis above the threshold voltage level TVL. While the supply voltage VSis above the threshold voltage level TVL, the target regulated voltage indicated by the control reference CR indicates the first voltage level, and thus the voltage regulation circuit24drives the regulated voltage VREGto the first voltage level FVL.

FIG. 2illustrates another embodiment of the RF amplification device10. The RF amplification device10shown inFIG. 2is the same as the RF amplification device10shown inFIG. 1, except that in this embodiment, the supply terminus26B is coupled to receive the regulated voltage VREGinstead of the supply voltage VS. In other words, the initial RF amplifier stage12A has the supply terminus26A coupled to receive the regulated voltage VREG, the intermediate RF amplifier stage12B has the supply terminus26B coupled to receive the regulated voltage VREG, and the final RF amplifier stage12C has the supply terminus26C coupled to receive the supply voltage VS. Thus, in this case, the voltage regulation circuit24controls the initial RF amplifier stage12A and the intermediate RF amplifier stage12B. Thus, the maximum output power of the RF amplification circuit11is controlled with both the initial RF amplifier stage12A and the intermediate RF amplifier stage12B.

FIG. 3illustrates yet another embodiment of the RF amplification device10. The RF amplification device10shown inFIG. 3is the same as the RF amplification device10shown inFIG. 1, except that in this embodiment, the supply terminus26B and the supply terminus26C are coupled to receive the regulated voltage VREGinstead of the supply voltage VS. In other words, the initial RF amplifier stage12A has the supply terminus26A coupled to receive the regulated voltage VREG, the intermediate RF amplifier stage12B has the supply terminus26B coupled to receive the regulated voltage VREG, and the final RF amplifier stage12C has the supply terminus26C coupled to receive the regulated voltage VREG. Therefore, in this case, the voltage regulation circuit24controls the initial RF amplifier stage12A the intermediate RF amplifier stage12B, and the final RF amplifier stage12C. Thus, the maximum output power of the RF amplification circuit11is controlled with all of the RF amplifier stages12. It should be noted that under normal operating conditions, the voltage drop across the voltage regulation circuit24inFIG. 3may more strictly limit the maximum output power of the RF amplification circuit11since this voltage drop effectively lowers the regulated voltage VREGused to supply the final RF amplifier stage12C.

FIG. 4illustrates yet another embodiment of the RF amplification device10. The RF amplification device10shown inFIG. 3is the same as the RF amplification device10shown inFIG. 1, except that in this embodiment, the intermediate RF amplifier stage12B (shown inFIG. 1) is not provided in the RF amplification circuit11but rather only the initial RF amplifier stage12A and the final RF amplifier stage12C. As such, the output terminus18A is connected to the input terminus16C. In other words, the initial RF amplifier stage12A has the supply terminus26A coupled to receive the regulated voltage VREG, the intermediate RF amplifier stage12B has the supply terminus26B coupled to receive the regulated voltage VREG, and the final RF amplifier stage12C has the supply terminus26C coupled to receive the regulated voltage VREG. Thus, in this case, the voltage regulation circuit24controls the initial RF amplifier stage12A, the intermediate RF amplifier stage12B, and the final RF amplifier stage12C. In this embodiment, the initial RF amplifier stage12A has the supply terminus26A coupled to receive the regulated voltage VREG, and the final RF amplifier stage12C has the supply terminus26C coupled to receive the supply voltage VS. Thus, in this case, the voltage regulation circuit24controls only the initial RF amplifier stage12A. In alternative embodiments, the maximum output power of the RF amplification circuit11is controlled with both the initial RF amplifier stage12A and the final RF amplifier stage12C.

Referring now toFIG. 5,FIG. 5illustrates a circuit diagram of one implementation of the voltage regulation circuit24shown inFIG. 1,FIG. 2,FIG. 3, andFIG. 4. The voltage regulation circuit24is configured to receive the supply voltage VSand generate the regulated voltage VREGfrom the supply voltage VS. More specifically, the voltage regulation circuit24includes a voltage regulator30configured to generate the regulated voltage VREGfrom the supply voltage VS. As explained above, the regulated voltage VREGis provided to the RF amplification circuit11, as described above with respect toFIG. 1,FIG. 2,FIG. 3, andFIG. 4.

The voltage regulation circuit24further includes an error detection circuit32configured to generate the control reference CR endogenously from the from the supply voltage VS. As such, the error detection circuit32is configured to set the control reference CR such that the control reference CR indicates that the target regulated voltage is set approximately at the first voltage level in response to the supply voltage VSbeing below the threshold voltage level, and set the control reference CR such that the control reference CR indicates that the target regulated voltage is below the first voltage level and maintains the maximum output power of the RF amplification circuit11(shown inFIGS. 1-4) approximately at the first power level in response to the supply voltage being above the threshold voltage level, as explained above with respect toFIG. 1A. The error detection circuit32is also configured to operate the voltage regulator30such that a voltage regulator30drives the regulated voltage VREGto the target regulated voltage indicated by the control reference CR.

In this embodiment, the error detection circuit32includes a control reference circuit34, a voltage divider36, and an error amplifier38. The voltage divider36is coupled so as to generate a feedback signal FS from the regulated voltage VREG. In this manner, the feedback signal FS indicates the regulated voltage VREG. The operation of the control reference circuit34is designed to endogenously generate the control reference CR and operate as described above with respect toFIG. 1A. The control reference circuit34is thus configured to generate the control reference CR endogenously from the supply voltage VS. The control reference circuit34is also configured to set the control reference CR such that the control reference CR indicates that the target regulated voltage is set approximately at the first voltage level in response to the supply voltage VSbeing below the threshold voltage level. Finally, the control reference circuit34is configured to set the control reference CR such that the control reference CR indicates that the target regulated voltage is below the first voltage level and maintains the maximum output power of the RF amplification circuit11(shown inFIGS. 1-4) approximately at the first power level in response to the supply voltage VSbeing above the threshold voltage level.

The error amplifier38is configured to operate the voltage regulator30such that the voltage regulator30drives the regulated voltage VREGto the target regulated voltage indicated by the control reference CR. To do this, the error amplifier38is configured to receive the feedback signal FS that indicates the regulated voltage VREGat an error amplifier input terminus TI1. The error amplifier38is also configured to receive the control reference CR from the control reference circuit34at an error amplifier input terminus TI2. The error amplifier38compares the feedback signal FS and the control reference CR and is configured to generate a voltage regulation signal VRS at an error amplifier output terminus TO. The error amplifier output terminus TO is coupled to a control terminal of the voltage regulator30. The error amplifier38may be configured to drive the voltage regulator30so that the feedback signal FS and the control reference CR are approximately equal. When the voltage difference between the control reference CR and the feedback signal FS is zero, the error amplifier maintains a voltage level of the voltage regulation signal VRS as substantially constant. However, when the voltage difference is not zero, the error amplifier38generates the voltage regulation signal VRS such that the regulated voltage VREGis adjusted, thereby adjusting the feedback signal FS. Adjustments continue until the feedback signal FS and the control reference CR are approximately equal. In this manner, the voltage regulation signal VRS operates the voltage regulator30so as to minimize a difference between the feedback signal FS and the control reference CR. Since the error amplifier output terminus TO is coupled to a control terminal of the voltage regulator30, the voltage regulator30is configured to receive the voltage regulation signal VRS and generate the regulated voltage VREGin accordance with the voltage regulation signal VRS. As such, the regulated voltage VREGis driven to the target regulated voltage indicated by the control reference CR.

In this embodiment, the voltage regulation circuit24is configured as a low-drop-out (LDO) voltage regulation circuit. The voltage regulator30is a field effect transistor (FET) having a source terminal40, a drain terminal42, and a gate terminal44connected to the error amplifier output terminus TO. In this embodiment, the voltage regulator30is a P-type FET, and thus the source terminal40is coupled to receive the supply voltage VSand the drain terminal42is configured to output the regulated voltage VREG. So long as the voltage regulator30is not saturated, the voltage regulator30regulates the regulated voltage VREGso that variations in the supply voltage VSdo not significantly affect the regulated voltage VREG. Since the voltage regulation circuit24is configured as a LDO voltage regulation circuit, the drop out voltage level is simply the saturation voltage level of the P-type FET. It should be noted that in alternative embodiments, the voltage regulation circuit24may be configured as a different type of regulation circuit, such as a standard voltage regulation circuit or a quasi LDO circuit. While not required, the LDO circuit configuration is generally preferable because the LDO circuit configuration tends to have the lowest drop out level and therefore can provide better power efficiency. The voltage divider36has a resistor R1with a resistive value of r1 and a resistor R2with a resistive value of r2.

With regard to the control reference circuit34, the control reference circuit34includes a mirror circuit46, a voltage to current converter48, a current source50, and a current source52. The current source50is configured to generate a current I1, which has a substantially constant current level. The voltage to current converter48is configured to generate a control current I2from the supply voltage VS. The voltage to current converter48has an internal variable resistance r3. Thus, the control current I2is approximately equal to Vs/r3. A resistor R4has a resistance value of r3. The current source52is configured to generate a current I3, which has a substantially constant current level. The control reference CR in this case is a reference voltage VREF. The equations below describe the operation of the control reference circuit34.
VREG=(1+R1/R2)VREF(1)
I2=VS/r3  (2)
VREF=(I1+I3−VS/r3)*r4 whenI2>I3  (3)
VREF=I1*r4 whenI2<I3  (4)

Equations (1) and (4) combine to provide
VREG=(1+r1/r2)*(I1+I3−VS/r3)*r4  (5)

Accordingly, the threshold voltage level is set by the current I3. Equation 5 shows how the regulated voltage VREGis inversely proportional to VSabove the threshold voltage level. Furthermore, the mirror circuit46is configured to generate the control reference CR (e.g., in this case is a reference voltage VREF) in accordance with the control current I2.

FIG. 6illustrates one embodiment of the voltage to current converter48shown inFIG. 5. The voltage to current converter48includes a pair of control coupled transistors54,56and an error amplifier58. The error amplifier58is configured to drive the pair of control coupled transistors54,56based on the supply voltage VSso as to generate the control current I2. In this embodiment, the error amplifier58is configured to operate the transistor54such that the transistor54drives the transistor56to generate the control current I2. To do this, the error amplifier38is configured to receive a feedback signal FS1that indicates an output voltage VOat an error amplifier input terminus TI11. The error amplifier58is also configured to receive a control voltage CV from a voltage divider60. The voltage divider60includes a resistor R5having a resistive value of r5 and a resistor R6having a resistive value r6. The feedback signal FS1is provided using the resistor R7coupled to ground. The voltage divider60is coupled between to receive the supply voltage VS. The resistor R7has a resistive value of r5.

The control voltage CV is received from the voltage divider60at the error amplifier input terminus TI22. The error amplifier58compares the feedback signal FS and the control reference CR, and is configured to generate a control signal CRS at an error amplifier output terminus TO1. The error amplifier output terminus TO1is coupled to a control terminal of the transistor54. In this embodiment, the transistors54,56are both P-type FETs that are the same size. The error amplifier58may be configured to drive the transistor54so that the feedback signal FS1and the control voltage CV are approximately equal. When the voltage difference between the control voltage CV and the feedback signal FS1is zero, the error amplifier58maintains a voltage level of the control signal CRS as substantially constant. However, when the voltage difference is not zero, the error amplifier58generates the control signal CRS such that the output voltage VOis adjusted thereby adjusting the feedback signal FS1. Adjustments continue until the feedback signal FS1and the control voltage CV are approximately equal. Since the error amplifier output terminus TO1is coupled to the control terminal (i.e., the gate terminal) of the transistor54, the transistor54is configured to receive the control signal CRS and generate the control current I2in accordance with the control signal CRS. As shown, a source terminal S1, S2of both of the transistors54,56is coupled to receive the VS. A drain terminal D1of the transistor54generates the output voltage VOwhile the drain terminal D2of the transistor56generates the control current I2.

Relevant equations for the voltage to current converter48are shown below.
CV=VS*(R5/(R5+R6))  (6)

FIG. 7illustrates another embodiment of the voltage regulation circuit24. The voltage regulation circuit24is the same as the voltage regulation circuit24shown inFIG. 5, except the voltage regulation circuit24shown inFIG. 7includes another embodiment of a control reference circuit62configured to generate the control reference CR as described inFIG. 1Aabove. The control reference circuit62includes a sense transistor64configured to generate a control current ISfrom the supply voltage VS. The sense transistor64is control coupled with the voltage regulator30. A source SS1of the sense transistor64is coupled to receive the supply voltage VSand a drain DD1of the sense transistor64is coupled to transmit the control current ISto a mirror circuit66. The control current ISis thus a mirror of the current flow through the voltage regulator30.

The mirror circuit66is configured to generate the control reference CV (e.g., the control voltage VREF) in accordance with the control current IS. More specifically, a current source68is coupled to receive the supply voltage VSand to the error amplifier input terminus TI2. The current source68generates a current I11, which has a substantially constant current level. A resistor R8is connected between the error amplifier input terminus TI2and ground. The resistor R8has a resistive value of r8. Additionally, the mirror circuit66is a current source70configured to generate a current I12also having a substantially constant current level. Equations relevant to the operation of the control reference circuit62are shown below.
VREG=(1+r1/r2)*VREF(10)
VREF=(I11+I12−IS)*r8 whenIS>I12  (11)
VREF=I11*r8 whenIS<I12  (12)

Equation (13) shows how VREGis inversely proportional to ISwhen the supply voltage VSis above the threshold voltage level as described above with respect toFIG. 1A.

FIG. 8illustrates another embodiment of the RF amplification device10. The voltage regulation circuit24shown inFIG. 1is replaced with a dynamic level shifter (DLS) circuit72. The DLS circuit72is coupled between the supply voltage VSand the initial RF amplifier stage12A. The DLS circuit72is also coupled to ground and coupled to a voltage reference VREF1. The DLS circuit72is configured to provide a reduced voltage VREDto the initial RF amplifier stage12A. In other embodiments, the voltage regulation circuit24shown inFIG. 2, 3, or4may be replaced with the DLS circuit72.

When the supply voltage VSis above a first threshold voltage level VTVL1, the DLS circuit72is configured in a first mode to provide the reduced voltage VREDas a first shifted voltage. The first shifted voltage is the supply voltage VSless a forward voltage drop of a first diode (not shown inFIG. 8) and a forward voltage drop of a second diode (not shown ifFIG. 8). When the supply voltage VSis between the first threshold voltage level VTVL1and a second threshold voltage level VTVL2, the DLS circuit72is configured in a second mode to provide the reduced voltage VREDas a second shifted voltage, wherein the second threshold voltage level VTVL2is less than the first threshold voltage level VTVL1. The second shifted voltage is the supply voltage VSless the forward voltage drop of the second diode. When the supply voltage VSis below the second threshold voltage level VTVL2, the DLS circuit72is configured in a third mode to provide the reduced voltage VREDas a third shifted voltage. The third shifted voltage may be approximately equal to the supply voltage.

FIG. 9illustrates a schematic of one embodiment of the DLS circuit72shown inFIG. 8. To provide the reduced voltage VRED, a cathode of the first diode74is coupled to the initial RF amplifier stage12A, to the source of the first shunt transistor78, and to a source of the second shunt transistor80. The anode of the first diode74is coupled to a cathode of the second diode76and to the drain of the first shunt transistor78, while an anode of the second diode76is coupled to the supply voltage VSand to a drain of the second shunt transistor80. The gate of the first shunt transistor78is coupled with a voltage reference VREF1, while a gate of the second shunt transistor may be coupled with a ground.

The first shunt transistor78is configured to short-circuit the first diode74when the first shunt transistor78is turned on. The second shunt transistor80is configured to short-circuit the first diode74and the second diode76when the second shunt transistor80is turned on. The first shunt transistor78may be considered on when a first gate-to-source threshold voltage VGS1onis exceeded. Likewise, the second shunt transistor80may be considered on when a second gate-to-source threshold voltage VGS2onis exceeded. The voltage reference VREF1is configured such that the first shunt transistor78turns on as the supply voltage VSis reduced, and the second shunt transistor80turns on as the supply voltage VSis further reduced.

In some embodiments, the first diode74may have a first diode forward voltage VD1between approximately 1.2 volts and approximately 1.3 volts; and the second diode76may have a second diode forward voltage VD2between approximately 0.75 volts and approximately 0.85 volts. In this embodiment, the first diode74may be a PIN diode and the second diode76may be a Schottky barrier diode. The PIN diode includes an undoped intrinsic semiconductor region between a p-type semiconductor region and an n-type semiconductor region.

In other embodiments, the first diode74may have a first diode forward voltage VD1between approximately 0.75 volts and approximately 0.85 volts; and the second diode76may have a second diode forward voltage VD2between approximately 1.2 volts and approximately 1.3 volts. In this embodiment, the first diode74may be a Schottky barrier diode and the second diode76may be a PIN diode.

In some embodiments, the first shunt transistor78may have a first transistor on-state resistance RS1between approximately 0.5 ohms and approximately 1.5 ohms; and the second shunt transistor80may have a second transistor on-state resistance RS2between approximately 0.8 ohms and approximately 2 ohms. The first shunt transistor78may have the first gate-to-source threshold voltage VGS1onbetween approximately −1.5 volts and approximately −1.6 volts; and the second shunt transistor80may have the second gate-to-source threshold voltage VGS2onbetween approximately −1.5 volts and approximately −1.6 volts. The shunt transistors78and80may each be a depletion mode n-type FET.

In other embodiments, the first shunt transistor78may have the first transistor on-state resistance RS1between approximately 0.5 ohms and approximately 1.5 ohms; and the second shunt transistor80may have the second transistor on-state resistance RS2between approximately 0.8 ohms and approximately 2 ohms. The first shunt transistor78may have the first gate-to-source threshold voltage VGS1onbetween approximately 0 volts and approximately −0.1 volts; and the second shunt transistor80may have the second gate-to-source threshold voltage VGS2onbetween approximately 0 volts and approximately −0.1 volts. The shunt transistors78and80may each be a depletion mode n-type pseudomorphic high electron mobility transistor (pHEMT).

When calculating a short-circuit voltage of either the first or second shunt transistors78and80, a DLS current IDLSmay be used. The DLS current IDLSmay be defined as the current that flows through the DLS circuit72from the supply voltage VSto the RF amplification device10, and may correspond with the drain-to-source current through each one of the transistors78and80. Gate currents of the first and second shunt transistors78and80may be negligible in this calculation. In some embodiments, the short-circuit voltage of the first and second shunt transistors78and80may be negligible when compared to the first and second diode forward voltages VD1and VD2.

As described inFIG. 8, the supply voltage VS, as compared with the first and second threshold voltage levels VTVL1and VTVL1define the first, second, and third modes of the DLS circuit72. ForFIG. 9, equation (14) defines the first threshold voltage level VTVL1and equation (15) defines the second threshold voltage level VTVL1.
VTVL1=VGS1+VREF1(14)
VTVL2=VGS2(15)

In other embodiments, the gate of the second shunt transistor80may be coupled to a second voltage reference VREF2(not shown) having a voltage level between the first voltage reference VREF1and ground. In this embodiment, equation (16) defines the second threshold voltage level VTVL2.
VTVL2=VGS2+VREF2(16)

When in the first mode, the DLS circuit72provides the reduced voltage VREDvia the first diode74and the second diode76. The reduced voltage VREDat the first shifted voltage level may be approximated as in equation (17).
VRED=VS−VD1−VD2whenVS>VTVL1(17)
In the first mode, the supply voltage VSis greater than the first threshold voltage level VTVL1. As such, the first gate-to-source threshold voltage VGS1onis not exceeded and the first shunt transistor78is off. Likewise, the second gate-to-source threshold voltage VGS2onis not exceeded and the second shunt transistor78is also off.

When in the second mode, the DLS circuit72provides the reduced voltage VREDvia the first shunt transistor78and the second diode76. The reduced voltage VREDat the second shifted voltage level may be approximated as in equation (18).
VRED=VS−(IDLS×RS1)−VD2whenVTVL1>VS>VTVL2(18)
In the second mode, the supply voltage VSis less than the first threshold voltage level VTVL1and greater than the second threshold voltage level VTVL2. As such, the first gate-to-source threshold voltage VGS1onis exceeded and the first shunt transistor78is on, while the second gate-to-source threshold voltage VGS2onis not exceeded and the second shunt transistor80remains off.

When in the third mode, the DLS circuit72provides the reduced voltage VREDvia the second shunt transistor80. The reduced voltage VREDat the third shifted voltage level may be approximated as in equation (19).
VRED=VS−(IDLS×RS2) whenVS<VTVL2(19)
In the third mode, the supply voltage VSis less than the second threshold voltage level VTVL2. As such, the first gate-to-source threshold voltage VGS1onis exceeded and the first shunt transistor78is on. Likewise, the second gate-to-source threshold voltage VGS2onis exceed and the second shunt transistor80is also on.

As compared with voltage regulation circuit24ofFIGS. 1 and 7, the DLS circuit72operates at a lower power efficiency. However, the DLS circuit operates in a feed forward manner without transient spikes as the supply voltage VStransitions from higher to lower voltages. The DLS circuit72can also operate at much lower values of VSthan the voltage regulation circuit24. The DLS circuit72may be implemented in any bipolar FET (BiFET) process or any other suitable semiconductor process.

FIG. 10illustrates one embodiment of a voltage response graph of the DLS circuit72ofFIG. 9. The voltage response graph depicts the reduced voltage VREDas a function of the supply voltage VS.

FIG. 11illustrates a reverse polarity DLS (RPDLS) circuit84as an alternate embodiment of the DLS circuit72. The RPDLS circuit84may be coupled to a negative supply voltage −VSto provide a negative reduced voltage −VREG. The first and second diodes74and76of the DLS circuit72are used for the RPDLS circuit84. However, the first and second shunt transistors78and80are replaced with first and second p-type shunt transistors86and88.

To provide the negative reduced voltage −VRED, the anode of the first diode74is coupled to the source of the first p-type shunt transistor86, and to a source of the second p-type shunt transistor88. The cathode of the first diode74is coupled to the anode of the second diode76and to the drain of the first p-type shunt transistor86, while the cathode of the second diode76is coupled to the negative supply voltage −VSand to a drain of the second p-type shunt transistor88. The gate of the first shunt transistor86is coupled with a negative voltage reference −VREF1, while a gate of the second shunt transistor88is coupled with ground. The RPDLS circuit84is configured to operate in a similar manner as the DLS circuit72ofFIG. 9.