Semiconductor memory device

A semiconductor memory device includes a semiconductor chip including a first voltage generating circuit that generates a first voltage in response to a first operation control signal, a second voltage generating circuit that generates a second voltage in response to a second operation control signal, a first operation control circuit that generates the first operation control signal, a second operation control circuit that generates the second operation control signal, a first bonding pad connected to an output of the first voltage generating circuit, and a second bonding pad connected to an output of the second voltage generating circuit. A packaging substrate includes a first substrate pad connected to the first bonding pad and a second substrate pad connected to the second bonding pad. The first and second substrate pads are connected to each other through the packaging substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 2005-61430, filed Jul. 07, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which can control respective operations of a plurality of internal voltage generating circuits when the semiconductor device is in a packaged state.

2. Description of the Related Art

Generally, a semiconductor memory device includes a plurality of internal voltage generating circuits which generate internal voltages which are necessary for operation of the semiconductor memory device by using an external power voltage supplied from an external location.

In the case of a dynamic random access memory (DRAM), the semiconductor memory device includes a VPP voltage generating circuit for generating a boosted voltage VPP (e.g., voltage of greater than 2 volts and less than 3.5 volts), a VINT voltage generating circuit for generating an internal operating voltage VINT (e.g., voltage of greater than 1.5 volts and less than external power voltage), and a VBB voltage generating circuit for generating a back bias voltage VBB (e.g., voltage of greater than −0.7 volts and less than ground voltage VSS).

With the continuing trend in semiconductor memory devices in the pursuit of low power consumption, high integration and high performance, the internal voltage generating circuits arranged in semiconductor memory devices continue to increase in kind and number.

For example, conventional semiconductor memory devices have employed a VBB voltage generated from the VBB voltage generating circuit as a back bias voltage of a semiconductor substrate and a negative voltage of a word line driver; however, recent semiconductor memory devices include first and second VBB voltage generating circuits and employ a VBB1voltage (e.g., greater than −0.7 volts and less than ground voltage VSS) generated from the first VBB voltage generating circuit as a back bias voltage of the semiconductor substrate and a VBB2voltage (e.g., greater than −0.4 volts and less than ground voltage VSS) generated from the second VBB voltage generating circuit as the negative voltage of the word line driver.

As the kind and number of required internal voltages are increased, certain internal voltage generating circuits in the semiconductor memory device become to generate similar, or overlapping, voltage levels.

Therefore the semiconductor memory device may select one of internal voltage generating circuits that generates voltage levels required to operate in a final, manufactured state of the semiconductor memory device, considering processing parameters and designing parameters thereof.

However, the conventional semiconductor memory device does not have a means for selecting the suitable internal voltage generating circuit among certain internal voltage generating circuits and to replace certain internal voltage generating circuits as the selected internal voltage generating circuit in a final, manufactured state of the semiconductor memory device.

As a result, when one of certain internal voltage generating circuits is needed in a state where the semiconductor chip is completely manufactured, the product manufacturer is required to reflect this in the product design and to re-manufacture the semiconductor chip. Accordingly, there is a problem in that cost and time to manufacture the semiconductor memory device are increased as a result.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor memory device in which a plurality of internal voltage generating circuits are connected to each other via a packaging substrate, and one among a plurality of internal voltage generating circuits is selected for operation in the process of packaging a semiconductor chip.

It is another object of the present invention to provide a semiconductor memory device in which a plurality of internal voltage generating circuits which are connected to each other via a packaging substrate can generate internal voltages having the same level, thereby increasing capability to supply the internal voltage and improving the resulting stability of the internal voltage.

In one aspect, the present invention is directed to a semiconductor memory device, comprising: a semiconductor chip including a first voltage generating circuit that generates a first voltage in response to a first operation control signal, a second voltage generating circuit that generates a second voltage in response to a second operation control signal, a first operation control circuit that generates the first operation control signal, a second operation control circuit that generates the second operation control signal, a first bonding pad connected to an output of the first voltage generating circuit, and a second bonding pad connected to an output of the second voltage generating circuit; and a packaging substrate including a first substrate pad connected to the first bonding pad and a second substrate pad connected to the second bonding pad, wherein the first and second substrate pads are connected to each other through the packaging substrate.

In one embodiment, each of the first and second operation control circuits is a fuse circuit which generates the first and second operation control signals in response to a programming status of a fuse.

In another embodiment, each of the first and second operation control circuits includes: a first fuse connected to a power voltage; a first PMOS transistor connected between the fuse and a node and being turned on and off in response to a control signal; a first NMOS transistor connected between the node and a ground voltage and being turned on and off in response to the control signal; a second NMOS transistor connected between the node and the ground voltage and being turned on and off in response to a feed back signal; a first inverter for inverting a signal applied to the node to generate the feed back signal; and a second inverter for inverting the feed back signal to generate an output signal.

In another embodiment, the control signal is generated when a power up is detected, i.e., when applied power is initiated.

In another embodiment, the packaging substrate connects the first and second substrate pads using at least one of a wire bonding and a beam lead.

In another aspect, the present invention is directed to a semiconductor memory device, comprising: a semiconductor chip including a first voltage generating circuit that selects whether to generate a first voltage in response to a first operation control signal and that varies a voltage level of the first voltage in response to a first voltage control signal, a second voltage generating circuit that selects whether to generate a second voltage in response to a second operation control signal, a first operation control circuit that generates the first operation control signal, a second operation control circuit that generates the second operation control signal, a first voltage control circuit that generates the first voltage control signal, a first bonding pad connected to the first voltage generating circuit, and a second bonding pad connected to the second voltage generating circuit; and a packaging substrate including a first substrate pad connected to the first bonding pad and a second substrate pad connected to the second bonding pad, wherein the first and second substrate pads are connected to each other through the packaging substrate.

In one embodiment, the first voltage generating circuit generates the first voltage which has the same voltage level as the second voltage in response to the first voltage control signal.

In another embodiment, the device further comprises a second voltage control circuit that generates a second voltage control signal, wherein the second voltage generating circuit further varies a voltage level of the second voltage in response to the second voltage control signal.

In another embodiment, the second voltage generating circuit generates the second voltage which has the same voltage level as the first voltage in response to the second voltage control signal.

In another embodiment, the first and second voltage control circuits generate a third voltage in response to the first and second voltage control signals.

In another embodiment, each of the first and second voltage control circuits is a mode register set which generates a signal in response to externally applied coding signals.

In another embodiment, each of the first and second voltage control circuits includes a plurality of fuse circuits which generate first and second voltage control signals in response to programming statuses of fuses.

In another embodiment, each of the plurality of fuse circuits includes: a first fuse connected to a power voltage; a first PMOS transistor connected between the fuse and a node and being turned on and off in response to a control signal; a first NMOS transistor connected between the node and a ground voltage and being turned on and off in response to the control signal; a second NMOS transistor connected between the node and the ground voltage and being turned on and off in response to a feed back signal; a first inverter for inverting a signal applied to the node to generate the feed back signal; and a second inverter for inverting the feed back signal to generate an output signal.

In another embodiment, the control signal is generated when a power up is detected, i.e., when applied power is initiated.

In another embodiment, each of the first and second operation control circuits is a fuse circuit which generates the first and second operation control signals in response to a programming status of a fuse.

In another embodiment, each of the first and second operation control circuits includes: a second fuse connected to a power voltage; a second PMOS transistor connected between the fuse and a node and being turned on and off in response to a control signal; a third NMOS transistor connected between the node and a ground voltage and being turned on and off in response to the control signal; a fourth NMOS transistor connected between the node and the ground voltage and being turned on and off in response to a feed back signal; a third inverter for inverting a signal applied to the node to generate the feed back signal; and a fourth inverter for inverting the feed back signal to generate an output signal.

In another embodiment, the control signal is generated when a power up is detected.

In another embodiment, the packaging substrate connects the first and second substrate pads using at least one of a wire bonding and a beam lead.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification.

FIG. 1is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring toFIG. 1, the semiconductor memory device includes a semiconductor chip1and a packaging substrate2. The semiconductor chip1includes a first internal voltage generating circuit11, a second internal voltage generating circuit12, a first operation control circuit13, a second operation control circuit14, and bonding pads BP1and BP2. The packaging substrate2includes substrate pads P1and P2and substrate wire lines SL. In one embodiment, the semiconductor memory device is packaged using a ball grid array packaging method.

The first internal voltage generating circuit11operates in response to a first operation control signal op_ctrl1, and generates a first internal voltage Vin1from an external power voltage VCC when its operation is enabled.

The second internal voltage generating circuit12operates in response to a second operation control signal op_ctrl2, and generates a second internal voltage Vin2from an external power voltage VCC when its operation is enabled.

The first and second internal voltage generating circuits11and12can be applied to various circuits which generate the internal voltages having similar voltage levels to replace the second and first internal voltage generating circuits12and11. For example, the first and second internal voltage generating circuits11and12can comprise a first VBB voltage generating circuit to generate the back bias voltage of the semiconductor substrate and a second VBB voltage generating circuit to generate the negative voltage of the word line driver.

The first operation control circuit13includes a fuse that can be programmed to generate the first operation control signal op_ctrl1for controlling operation of the first internal voltage generating circuit11. For example, the first operation control circuit13generates the operation control signal op_ctrl1for disabling operation of the first internal voltage generating circuit11when the fuse is cut, and generates the operation control signal op_ctrl1for enabling operation of the first internal voltage generating circuit11when the fuse is connected.

The second operation control circuit14includes a fuse like the first operation control circuit13and programs the fuse to generate the second operation control signal op_ctrl2for controlling operation of the second internal voltage generating circuit12.

The first bonding pad BP1is directly connected to the first internal voltage generating circuit11and is connected to the output of the second internal voltage generating circuit12through a first substrate pad P1, a substrate wire line SL, and a second substrate pad P2of the packaging substrate2and a second bonding pad BP2.

The second bonding pad BP2is directly connected to output of the second internal voltage generating circuit12and is connected to the first internal voltage generating circuit11through the second substrate pad P2, the substrate wire line SL, the first substrate pad P1of the packaging substrate2and the first bonding pad BP1.

The first substrate pad P1is directly connected to the first bonding pad BP1by a discrete connection means (e.g., wire bonding or beam lead) which is not shown, and the second substrate pad P2is directly connected to the second bonding pad BP2by a discrete connection means (e.g., wire bonding or beam lead).

The substrate wire line SL is implemented by a wire bonding or beam lead in the packaging substrate2to connect the first and second substrate pads P1and P2.

Operation of the semiconductor memory device will now be explained with reference toFIG. 1.

First, when the semiconductor chip1requires the first internal voltage Vin1as the internal voltage for operation, the semiconductor memory device operates as follows.

The fuse of the first operation control circuit13is connected so as to generate the first operation control signal op_ctrl1for enabling operation of the first internal voltage generating circuit11, and the fuse of the second operation control circuit14is cut so as to generate the second operation control signal op_ctrl2for disabling operation of the second internal voltage generating circuit12.

As a result, the first internal voltage generating circuit11is enabled and the second internal voltage generating circuit12is disabled, so that the first internal voltage Vin1is applied to the first bonding pad BP1and the second bonding pad BP2.

That is, the semiconductor memory device controls the first and second operation control circuits13and14to enable only the first internal voltage generating circuit11to thereby replace the second internal voltage Vin2as the first internal voltage Vin1.

On the other hand, when the semiconductor chip1requires the second internal voltage Vin2as an internal voltage for operation, the semiconductor memory device operates as follows.

The fuse of the first operation control circuit13is cut so as to generate the first operation control signal op_ctrl1for disabling operation of the first internal voltage generating circuit11, and the fuse of the second operation control circuit14is connected so as to generate the second operation control signal op_ctrl2for enabling operation of the second internal voltage generating circuit12. As a result, the second internal voltage generating circuit12is enabled, and the first internal voltage generating circuit11is disabled, whereby the second internal voltage Vin2is generated and applied to the second bonding pad BP2. The second internal voltage Vin2applied to the second bonding pad BP2is supplied to the first bonding pad BP1through the second substrate pad P2, the substrate wire line SL and the first substrate pad P1of the packaging substrate2. That is, the semiconductor memory device controls the first and second operation control circuits13and14to enable only the second internal voltage generating circuit12to thereby replace the first internal voltage Vin1as the second internal voltage.

FIG. 2is a circuit diagram illustrating the operation control circuit13or14according to an embodiment of the present invention.

Referring toFIG. 2, the operation control circuit includes a fuse F1connected to an external power voltage VCC, a PMOS transistor P1having a source connected to the fuse F1, a drain connected to a node n and a gate receiving a control signal con, an NMOS transistor N1having a drain connected to the node n, a source connected to a ground voltage VSS and a gate receiving the control signal con, an NMOS transistor N2having a drain connected to the node n, a source connected to the ground voltage VSS and a gate receiving an output signal of an inverter I1, and inverters I1and I2serially connected to the node n and generating the first operation control signal op_ctrl in response to the voltage of node n.

Operation of the operation control circuit ofFIG. 2will be explained below.

Here, the control signal con is generated when a power up is detected, and it has a low level at the initial stage, and transitions to a high level and transitions to a low level again when a power voltage is applied.

When the fuse F1is cut, the operation control circuit ofFIG. 2operates as follows.

When the control signal con transitions to a high level from a low level, the PMOS transistor P1is turned off, and the NMOS transistor N1is turned on, so that the voltage at node n becomes a ground voltage level. The inverters I1and I2buffer a signal having a voltage level of the node n and generate the first operation control signal op_ctrl having a low level. The NMOS transistor N2is turned on in response to a high signal from the inverter I1and maintains the voltage level of the node n.

Then, when the control signal con transitions to a low level from a high level again, the PMOS transistor P1is turned on, and the NMOS transistor N1is turned off. However, since the fuse F1is cut, the external power voltage VCC is not applied to the source of the PMOS transistor P1. So the node n maintains a ground voltage level, and the inverters I1and I2continuously generate a signal op_ctrl having a low level.

However when the fuse F1is connected, the operation control circuit ofFIG. 2operates as follows.

When the fuse F1is connected, the external power voltage VCC is applied to the source of the PMOS transistor P1.

Then, when the control signal con transitions to a high level from a low level, the PMOS transistor P1is turned off, and the NMOS transistor N1is turned on, so that the node n becomes a ground voltage level. The inverters I1and I2buffer a signal having a low level of the node n and generate the operation control signal op_ctrl having a low level, and the NMOS transistor N2is turned on in response to a signal having a high level from the inverter I1and which places the node n1at a ground voltage level.

In this state, when the control signal con transitions to a low level from a high level again, the PMOS transistor P1is turned on, and the NMOS transistor N1is turned off, so that the external power voltage VCC is applied to the node n. The inverters I1and I2buffer a signal of the node n and generate the operation control signal op_ctrl having a high level, and the NMOS transistor N2is turned off in response to a signal having a low level from the inverter I1.

As a result, the node n maintains the external voltage VCC level, and the inverters I1and I2continuously generate a signal having a high level.

The operation control circuit ofFIG. 2generates a signal the voltage level of which depends on whether the fuse is cut or not. That is, a signal generated when the fuse is cut is the operation control signal op_ctrl for disabling operation of the internal voltage generating circuit, and a signal generated when the fuse is connected is the operation control signal op_ctrl for enabling operation of the internal voltage generating circuit. It should be noted, however, that the operation control circuit can be readily configured to generate an operation control signal op_ctrl that enables operation of the corresponding internal voltage generating circuit when the fuse is cut and that disables operation of the corresponding internal voltage generating circuit when the fuse is connected.

Accordingly, the semiconductor memory device according to an embodiment of the present invention connects a plurality of internal voltage generating circuits through the packaging substrate and can select one that is required for operation among a plurality of internal voltage generating circuits by the first and second, or more, operation control circuits when packaging the semiconductor chip.

FIG. 3is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.

Referring toFIG. 3, the semiconductor memory device includes a semiconductor chip3and a packaging substrate4. The semiconductor chip3includes a first internal voltage generating circuit31, a second internal voltage generating circuit32, a first operation control circuit33, a second operation control circuit34, a first voltage control circuit35, a second voltage control circuit36, and bonding pads BP1and BP2. The packaging substrate4includes substrate pads P1and P2and substrate wire lines SL. In one embodiment, the semiconductor memory device is packaged using a ball grid array packaging method.

The first internal voltage generating circuit31operates in response to a first operation control signal op_ctrl1, and varies a voltage level of a first internal voltage Vin1according to applied first voltage control signals v_ctrl11to v_ctrl1n. For example, when enabled by the first operation control signal op_ctrl1, the first internal voltage generating circuit31varies a first reference voltage according to the first control signals v_ctrl11to v_ctrl1nand varies a voltage level of the first internal voltage Vin1according to the varied first reference voltage.

The second internal voltage generating circuit32operates in response to a second operation control signal op_ctrl2, and varies a voltage level of a second internal voltage Vin2according to applied second voltage control signals v_ctrl21to v_ctrl2n. For example, when enabled by the second operation control signal op_ctrl2, the second internal voltage generating circuit32varies a second reference voltage according to the second control signals v_ctrl21to v_ctrl2nand varies a voltage level of the second internal voltage Vin2according to the varied second reference voltage.

The first and second internal voltage generating circuits31and32can be applied to various circuits which generate the internal voltages having similar voltage levels to replace the second and first internal voltage generating circuits32and31.

The first operation control circuit33ofFIG. 3includes a fuse like the first operation control circuit13ofFIG. 1and programs the fuse to generate the first operation control signal op_ctrl1for controlling operation of the first internal voltage generating circuit31.

The second operation control circuit34includes a fuse like the second operation control circuit14ofFIG. 1and programs the fuse to generate the second operation control signal op_ctrl2for controlling operation of the second internal voltage generating circuit32.

The first voltage control circuit35can be implemented by a mode register set or by a plurality of fuses and generates the first voltage control signals v_ctrl11to v_ctrl1nfor varying a voltage level of the first internal voltage Vin1. The first voltage control circuit35generates the first voltage control signals v_ctrl1nto v_ctrl1nin response to coding signals (e.g., command signals and address signals) transmitted from an external source when implemented by a mode register set, and generates the first voltage control signals v_ctrl1nto v_ctrl1nin response to status of a plurality of fuses, when implemented by a plurality of fuses.

The second voltage control circuit36can likewise be implemented by a mode register set or by a plurality of fuses in a manner similar to the first voltage control circuit35and generates the second voltage control signals v_ctrl21to v_ctrl2nfor varying a voltage level of the second internal voltage Vin2.

The first bonding pad BP1is directly connected to an output of the first internal voltage generating circuit31and is connected to the second internal voltage generating circuit32through the second bonding pad BP2and the first and second substrate pads P1and P2and the substrate wire line SL of the packaging substrate4.

The second bonding pad BP2is directly connected to an output of the second internal voltage generating circuit32and is connected to the first internal voltage generating circuit31through the first bonding pad BP1and the first and second substrate pads P1and P2and the substrate wire line SL of the packaging substrate4.

The first substrate pad P1is directly connected to the first bonding pad BP1by a discrete connection means (e.g., wire bonding or beam lead) which is not shown, and the second substrate pad P2is directly connected to the second bonding pad BP2by a discrete connection means (e.g., wire bonding or beam lead).

The substrate wire line SL is implemented by a wire bonding or beam lead in the packaging substrate2to connect the first and second substrate pads P1and P2.

Operation of the semiconductor memory device will now be explained with reference toFIG. 3.

Here, it is assumed that the first internal voltage generating circuit31has an output voltage that ranges from a first voltage V1to a second voltage V2, the second internal voltage generating circuit32has an output voltage that ranges from a third voltage V3to a fourth voltage V4, and the amplitude of the voltage level is in the order of the third voltage V3, the first voltage V1, the fourth voltage V4, and the second voltage V2.

First, when the semiconductor chip3requires an internal voltage having a voltage level that ranges from the fourth voltage V4to the second voltage V2, the semiconductor memory device operates as follows.

The first operation control circuit33generates the first operation control signal op_ctrl1for enabling operation of the first internal voltage generating circuit31, the second operation control circuit34generates the second operation control signal op_ctrl2for disabling operation of the second internal voltage generating circuit32, and the first voltage control circuit35generates the first voltage control signals v_ctrl11to v_ctrl1nfor varying a voltage level of the first internal voltage to have a voltage level of from the fourth voltage V4to the second voltage V2. Here, the second voltage control circuit36is in a don't care state.

As a result, the first internal voltage generating circuit31is enabled in response to the first operation control signal op_ctrl1, and generates the first internal voltage Vin1having a voltage level of from the fourth voltage V4to the second voltage V2according to the first voltage control signals v_ctrl11to v_ctrl1nand applies the first internal voltage Vin1to the first bonding pad BP1. The second internal voltage generating circuit32is disabled in response to the second operation control signal op_ctrl2, so that the second internal voltage Vin2is not output by the second internal voltage generating circuit32.

The first internal voltage Vin1applied to the first bonding pad BP1is applied to the second bonding pad BP2through the first substrate pad P1, the substrate wire line SL and the second substrate pad P2of the packaging substrate4. As a result, the semiconductor memory device supplies the semiconductor chip with the first internal voltage Vin1having a voltage level of from the fourth voltage V4to the second voltage V2through the first internal voltage generating circuit31.

When the semiconductor chip3requires an internal voltage having a voltage level that ranges from the third voltage V3to the first voltage V1, the semiconductor memory device operates as follows.

The first operation control circuit33generates the first operation control signal op_ctrl1for disabling operation of the first internal voltage generating circuit31, the second operation control circuit34generates the second operation control signal op_ctrl2for enabling operation of the second internal voltage generating circuit32, and the second voltage control circuit36generates the second voltage control signals v_ctrl21to v_ctrl2nfor varying a voltage level of the second internal voltage to have a voltage level of from the third voltage V3to the first voltage V1. Here, the first voltage control circuit35is in a don't care state.

As a result, the second internal voltage generating circuit32is enabled in response to the second operation control signal op_ctrl2, and generates the second internal voltage Vin2having a voltage level of from the third voltage V3to the first voltage V1according to the second voltage control signals v_ctrl21to v_ctrl2nand applies the second internal voltage Vin2to the second bonding pad BP2. The first internal voltage generating circuit31is disabled in response to the first operation control signal op_ctrl1, so that the first internal voltage Vin1is not output by the first internal voltage generating circuit31.

The second internal voltage Vin2applied to the second bonding pad BP2is applied to the first bonding pad BP1through the second substrate pad P2, the substrate wire line SL and the first substrate pad P1of the packaging substrate4. As a result, the semiconductor memory device supplies the semiconductor chip with the second internal voltage Vin2having a voltage level of from the third voltage V3to the first voltage V1through the second internal voltage generating circuit32.

When the semiconductor chip3requires an internal voltage having a voltage level ranging from the first voltage V1to the fourth voltage V4, the semiconductor memory device operates as follows.

The first and second operation control circuits33and34respectively generate the first and second operation control signals op_ctrl1and op_ctrl2for enabling operation of both the first and second internal voltage generating circuits31and32, and the first second voltage control circuits35and36respectively generate the first and second voltage control signals v_ctrl11to v_ctrl1nand v_ctrl21to v_ctrl2nfor respectively varying voltage levels of the first and second internal voltages to have a voltage level of from the first voltage V1to the fourth voltage V4.

As a result, the first internal voltage generating circuit31is enabled in response to the first operation control signal op_ctrl1, and generates the first internal voltage Vin1having a voltage level of from the first voltage V1to the fourth voltage V4according to the first voltage control signals v_ctrl11to v_ctrl1nand applies the first internal voltage Vin1to the first bonding pad BP1. The second internal voltage generating circuit32is enabled in response to the second operation control signal op_ctrl2, and generates the second internal voltage Vin2having a voltage level of from the first voltage V1to the fourth voltage V4according to the second voltage control signals v_ctrl21to v_ctrl2nand applies the second internal voltage Vin2to the second bonding pad BP2.

As a result, the semiconductor memory device simultaneously generate the first and second internal voltages Vin1and Vin2through the first and second internal voltage generating circuits31and32and so more stably supplies the semiconductor chip with the internal voltage having a voltage level of from the first voltage V1to the fourth voltage V4.

FIG. 4is a circuit diagram illustrating the voltage control circuit35or36according to another embodiment of the present invention.

Referring toFIG. 4, the voltage control circuit includes first to n-th fuse control circuits FC1to FCn. Each of the fuse control circuits FC1to FCn has a similar configuration to the operation control circuit ofFIG. 2. Each of the fuse control circuits FC1to FCn includes a fuse F11connected to an external power voltage VCC, a PMOS transistor P11having a source connected to the fuse F11, a drain connected to an NMOS transistor N11and a gate receiving a control signal con, the NMOS transistor N11having a drain connected to the PMOS transistor P11, a source connected to a ground voltage VSS and a gate receiving the control signal con, an NMOS transistor N12having a drain connected to the PMOS transistor P11, a source connected to the ground voltage VSS and a gate receiving an output signal of an inverter I11, the inverter I11connected to the drains of the NMOS transistors N11and N12, and an inverter I12connected to an output of the inverter I11.

Each of the fuse control circuits FC1to FCn operates in the same way as the operation control circuit ofFIG. 2. That is, each generates a signal having a low level when the fuse is cut and generates a signal having a high level when the fuse is connected.

The first voltage control circuit35outputs first voltage control signals v_ctrl11to v_ctrl1nin response to whether the first to n-th fuse control circuits FC1to FCn are cut or connected.

As described above, the semiconductor memory device according to another embodiment of the present invention not only determines whether to operate the first and second internal voltage generating circuits in response to the output signals of the first and second operation control circuits, but they also vary a voltage level of the internal voltage of the first and second voltage generating circuits by the first and second voltage control circuits.

Accordingly, the semiconductor memory device of the present invention not only selects one among a plurality of internal voltage generating circuits required for operation when packaging the semiconductor chip but also can further select for operation additional ones of the plurality of internal voltage generating circuits for generating the internal voltages having same voltage level, thereby increasing the capability of the semiconductor memory device to supply the internal voltage level.

In the embodiment shown inFIGS. 3 and 4, a voltage control circuit is provided for each of the first and second internal voltage generating; however, a voltage control circuit can optionally be applied to only one of the first and second internal voltage generating circuits if needed.

As described above, the semiconductor memory device of the present invention connects a plurality of internal voltage generating circuits through the bonding pads and the pads and substrate wire lines of the packaging substrate and programs the fuse of the operation control circuit to control operation of each of a plurality of internal voltage generating circuits. Thus, since it is possible to select one among a plurality of internal voltage generating circuits for operation when packaging the semiconductor chip, cost and time to manufacture the semiconductor memory device can be significantly reduced.

Further, the semiconductor memory device of the present invention varies a voltage level of the internal voltage of the internal voltage generating circuit through the voltage control circuit when packaging the semiconductor chip. Thus, since a plurality of internal voltage generating circuits can generate the internal voltages having same voltage level, the capability of the semiconductor memory device to supply the internal voltage can be improved.