Memory Die Management

Memory die management based on biasing voltages. Some memory dies are formed of memory holes having a semi-circular shape. This semi-circular shape results in a decrease in biasing voltage compared to memory holes having a circular shape. Systems and methods described herein organize memory dies into memory die groups according to their biasing voltages. During operation, data is relocated between the memory die groups based on how often the data is read. Data may be scrambled within their respective memory die groups to maintain appropriate storage space.

BACKGROUND

This application relates generally to data storage devices and, more particularly, to organizing memory dies based on characteristics of their stored memory to counter voltage downshifts on semi-circle memory holes.

Memory dies are formed by cutting memory holes within a sheet of metal. A drain-side select gate (SGD) associated with each memory hole is biased to set a voltage of the memory hole, and therefore a voltage at which data is stored. The memory dies are split into sections, or memory blocks, by a separating oxide. When the separating oxide cuts memory dies, the corresponding memory holes have a substantially semi-circular shape. Accordingly, each block includes memory holes having a circular shape and memory holes having a semi-circular shape.

SUMMARY

When a memory die experiences large quantity of read disturb events, the SGD lower tail voltage downshifts on semi-circle memory holes. As a result, in continued erase program cycles, a high number of noisy bits occur, resulting in an increase in fail bit count events. To offset this noise from read disturb events, embodiments described herein provide for organizing memory dies according to their biasing voltage value (VSG) related to a voltage threshold. Memory dies may be organized during memory die sorting, during packaging, or during operation. Additionally, memory dies may be organized based on how often data is being read.

The disclosure provides a data storage device including, in one embodiment, a memory interface and an electronic processor. The memory interface is configured to interface with a non-volatile memory, the non-volatile memory including a plurality of memory dies. Each of the memory dies includes a bias voltage value. The electronic processor is configured to compare the bias voltage value of each of the memory dies to a voltage threshold. The electronic processor is configured to assign memory dies having a bias voltage value greater than the voltage threshold to a first group of memory dies, and assign memory dies having a bias voltage value less than or equal to the voltage threshold to a second group of memory dies.

The disclosure also provides a method. In one embodiment, the method includes comparing the bias voltage value of each of a plurality of memory dies to a voltage threshold. The method includes assigning memory dies having a bias voltage value greater than the voltage threshold to a first group of memory dies, and assigning memory dies having a bias voltage value less than or equal to the voltage threshold to a second group of memory dies.

The disclosure also provides a memory device that supports organizing memory dies. The memory device comprises a memory and a controller. The memory includes at least a first memory die and a second memory die, the first memory die having a first bias voltage value and the second memory die having a second bias voltage value. The controller is configured to sort the first memory die into a first group and the second memory die into a second group.

In this manner, various aspects of the disclosure provide for improvements in at least the technical fields of data storage devices and their design and architecture. The disclosure can be embodied in various forms, including hardware or circuits controlled by firmware (i.e., code executing on a processor), and computer systems and networks; as well as hardware-implemented methods, signal processing circuits, memory arrays, application specific integrated circuits, field programmable gate arrays, and the like. The foregoing summary is intended solely to give a general idea of various aspects of the disclosure, and does not limit the scope of the disclosure in any way.

DETAILED DESCRIPTION

In the following description, numerous details are set forth, such as data storage device configurations, controller operations, and the like, in order to provide an understanding of one or more aspects of the present disclosure. It will be readily apparent to one skilled in the art that these specific details are merely exemplary and not intended to limit the scope of this application. In particular, the functions associated with the memory device may be performed by hardware (e.g., analog or digital circuits), a combination of hardware and software (e.g., program code or firmware, stored in a non-transitory computer-readable medium, that is executed by processing or control circuitry), or any other suitable means. The following description is intended solely to give a general idea of various aspects of the disclosure, and does not limit the scope of the disclosure in any way.

Data Storage Devices

FIG.1is a block diagram of one example of a system100that includes a data storage device102. In some implementations, the data storage device102is a flash memory device. For example, the data storage device102is a Secure Digital SD® card, a microSD® card, or another similar type of data storage device. The data storage device102illustrated inFIG.1includes a memory104(e.g., a non-volatile memory) and a controller106(referred to hereinafter as “data storage device controller”) coupled to the memory104.

The data storage device102is coupled to a host device108. The host device108is configured to provide data110(for example, user data136) to the data storage device102to be stored, for example, in the memory104. The host device108is, for example, a smart phone, a music player, a video player, a gaming console, an e-book reader, a personal digital assistance device, a tablet, a notebook computer, or another similar device.

In some implementations, the memory104is NAND flash memory. The memory104illustrated inFIG.1includes a plurality of memory units107A-107N (for example, flash memory units). Each of the plurality of memory units107A-107N includes a plurality of storage elements. For example, inFIG.1, the memory unit107A includes a representative storage element109A. In some implementations, the storage element109is a multi-level cell flash memory, such as a2levels cell (“SLC”), a4levels cell (“MLC”), an8levels cell (“TLC”), a16levels cell (“QLC”), or a flash memory cell having a larger number of bits per cell (for example, between five and ten bits per cell). In some implementations, the plurality of memory units107A-107N are memory dies configured to store data.

The data storage device controller106illustrated inFIG.1includes a host interface116, a memory interface118, an error code correction (ECC) engine126, and an electronic processor128. The data storage device controller106is illustrated inFIG.1in a simplified form. One skilled in the art would recognize that a controller for a non-volatile memory would include additional modules or components other than those specifically illustrated inFIG.1. Additionally, although the data storage device102is illustrated inFIG.1as including the data storage device controller106and modules for performing, for example, flag setting, in other implementations, the data storage device controller106is instead located within the host device108or is otherwise separate from the data storage device102. As a result, flash translation layer (“FTL”) operations and flash module (“FM”) operations that would normally be performed by the data storage device controller106(for example, wear leveling, bad block management, data scrambling, garbage collection, address mapping, etc.) can be performed by the host device108or another device that connects to the data storage device102.

The data storage device controller106is configured to send data to, and receive data and instructions from, the host device108via the host interface116. The host interface116enables the host device108to, for example, read from the memory104by transmitting requests134and to write to the memory104by sending user data136and using any suitable communication protocol. Suitable communication protocols include, for example, the Universal Flash Storage (“UFS”) Host Controller Interface specification, the Secure Digital (“SD”) Host Controller specification, etc.

The data storage device controller106is also configured to send data and commands to (e.g., the user data136, the requests134), and receive data from, the memory104with the memory interface118. As an illustrative example, the data storage device controller106is configured to send data and a write command to instruct the memory104to store data in a particular memory location in the memory104. The data storage device controller106is also configured to send a read command to the memory104to read data from a particular memory location in the memory104. In some examples, the data storage device controller106is coupled to the non-volatile memory104with a bus138in combination with the memory interface118.

The data storage device controller106illustrated inFIG.1includes an electronic processor128(for example, a microprocessor, a microcontroller, a field-programmable gate array [“FPGA”] semiconductor, an application specific integrated circuit [“ASIC”], or another suitable programmable device) and a non-transitory computer readable medium or memory130(for example, including random access memory [“RAM”] and read only memory [“ROM”]). The electronic processor128is operatively connected to the various modules within the data storage device controller106and the data storage device102. For example, firmware is loaded in a ROM of the memory130as computer executable instructions. Those computer executable instructions are capable of being retrieved from the memory130and executed by the electronic processor128to control the operation of the data storage device102and perform the processes described herein (for example, flag setting and read operations). In some implementations, one or more modules of the data storage device controller106correspond to separate hardware components within the data storage device controller106. In other implementations, one or more modules of the data storage device controller106correspond to software stored within the memory130and executed by the electronic processor128. The memory130is configured to store data used by the electronic processor128during operation. For example, the memory130stores a memory die management module124implemented to trim and organize memory dies, as described below in more detail.

Memory Die Configuration and Downshifting Effect

FIGS.2A-2Billustrates a memory block200comprising a plurality of memory holes205according to one example. Each memory hole205forms a memory cell for every word line. The memory block200includes alternating layers of metal210and oxide215between each memory hole205. Each of these metal210and oxide215combinations form a layer in3D NAND memory. “Drain-side select gates”, or SGDs, and “drain-side select gate tops”, or SGDTs, are present towards the top of the stack (such as metal210A and oxide215A) and are used to either connect or disconnect the memory holes to the drain terminal. For purposes of clarity, only a few representative memory holes205are labeled. To read data stored in a memory hole205, the respective SGD is turned “ON” by being provided a predetermined voltage.

The memory block200may be partitioned into sections225by a separating oxide220. Each section225holds a set of memory holes205, such as 16 kilobytes (KB) of memory holes205. However, as seen inFIG.2A, several memory holes205are covered by the separating oxide220. Such memory holes205are not used for storing data. This results in lost space.

To better utilize the memory holes,FIGS.3A-3Billustrate a memory block300comprising a plurality of memory holes305. Similar to the memory block200, the memory block300includes alternating layers of metal310and oxide315between each memory hole305. Additionally, for the purposes of clarity, only a few representative memory holes305are labeled. The memory block300is partitioned into sections325by a separating oxide320. However, in the example ofFIGS.3A-3B, the separating oxide320is placed between several memory holes305. This alters the shape of the respective memory holes305, changing them from substantially circular to substantially semi-circular (e.g., an incomplete circle). The extent to which the respective memory holes305are “cut” is dependent on the size of the separating oxide320. This placement of the separating oxide320better utilizes the available memory holes305. However, when a cell is subjected to large quantities of read disturb events (e.g., cumulative read disturb), the voltage thresholds of the memory dies experiences a shift in value (e.g., downshift effect).

FIG.4provides several graphs illustrating the impact of cumulative read disturb on the voltages of memory holes305. As a block is read multiple times, the SGD cells experience a downshift in their voltage value. For example,FIG.4includes a first graph400showing the SGD voltage distribution for the structure shown inFIGS.2A and2B, a second graph410illustrating the SGD voltage distribution for the structure shown inFIGS.3A and3Bwith a particular process, and a third graph420also illustrating the SGD voltage distribution for the structure shown inFIGS.3A and3B, but with a different process. The SGD voltage distributions in the second graph410and the third graph420experience voltage downshifts after cumulative read disturb compared to the distribution of the first graph400, which does not involve semi-circular memory holes. The cumulative read disturb may be, for example, 100,000 cumulative read disturb events. As a result, during subsequent erase program cycles, a high number of noisy bits is present, resulting in increased fail bit count events.

FIGS.5A and5Bfurther illustrate SGDs experiencing the voltage downshift effect. Specifically,FIGS.5A and5Bprovide a memory hole500cut by a separating oxide505. The memory hole includes a channel510and a charge trap layer (CTL)515. In some embodiments, the edges of the CTL515may be damaged due to being cut by the separating oxide505. In some embodiments, the channel510may also be recessed into the memory hole500due to being cut by the separating oxide505.

InFIG.5A, the memory hole500represents an un-selected string of memory holes within the memory block300. When a neighboring memory hole (not shown) is selected, the electric field due to a high bias voltage (VSG) of the SGD of the neighboring string attracts the electrons in the CTL515of the un-selected memory hole500towards the separating oxide505, as shown inFIG.5A. However, since the channel510is recessed, there is no portion of channel510adjacent to the CTL515near the separating oxide505, and the SGD voltage threshold downshifts in value. Cumulative read disturb results in continued shift of electrons within the CTL. Additionally, as higher VSG results in a stronger electrical field, a high VSG can worsen the impact of cumulative read disturb.

InFIG.5B, the memory hole500represents a selected string of memory holes within the memory block300. When the memory hole500is selected, the VSG is applied to the memory hole500. This creates an electric field that attracts electrons within the CTL515towards the VSG. This electric field may pull electrons away from the channel510, and the SGD voltage threshold downshifts in value.

Accordingly, while placing the separating oxide320between several memory holes305increases total memory space, the impact of the separating oxide320on the memory holes305over cumulative read disturb is an SGD voltage downshift on the respective memory holes305. This results in a high number of noisy bits and an increased fail bit count. As VSG increases, the noise increases, and data that is read may be different than data that is stored. Memory dies with lower VSG experience less impact of the electric field, and therefore experience less voltage downshift. The VSG for a memory die may be selected as the minimum possible VSG value to yield a voltage margin for the voltage distribution of the memory die above a fixed threshold (or yielding a failed bit count lower than a fixed threshold) after it is subjected to a predetermined number of read events followed by an erase and subsequent program. This value varies between memory dies.

Managing and Offsetting Downshift Effect

Since memory dies with lower VSG experience less voltage downshift than memory dies with higher VSG, they may be sorted according to their VSG. Memory dies that are more susceptible to voltage downshift may then be implemented in devices that are less read-intensive.FIG.6provides a method600for sorting memory dies. In some implementations, the method600is performed during an initial memory die sorting stage during production of the data storage device102(e.g., performed by a manufacturing controller that controls the packaging of the memory dies into the data storage device102).

The method600includes selecting the next memory die (at block605). In an instance where sorting of the memory dies has just been initiated and no memory dies have been sorted, an initial (e.g., a first) memory die may be selected. The memory dies may be, for example, the memory units107A-107N within the memory104. The method600includes determining whether the VSG of the selected memory die is less than or equal to a first voltage threshold (at decision block610). The voltage threshold may be, for example, 4.6 V. In some implementations, the voltage threshold is selected such that the lowest available VSG is greater than the SGD upper tail voltage by an overdrive value A.

When the VSG of the selected memory die is not less than or equal to the first voltage threshold (“NO” at decision block610), the method600includes placing the memory die in a first VSG memory die bin (at block615). The first VSG memory die bin includes memory dies with VSG greater than the first voltage threshold. Accordingly, the memory dies in the first VSG memory die bin may be more susceptible to the impacts of downshift effect. The memory dies in the first VSG memory die bin may be implemented in products which are less read intensive so as to avoid cumulative read disturb.

When the VSG of the selected memory die is less than or equal to the first voltage threshold (“YES” at decision block610), the method600includes placing the memory die in a second VSG memory die bin (at block620). As the memory dies in the second memory die bin are less than or equal to the first voltage threshold, the memory dies in the second memory die bin may be less susceptible to the impacts of downshift effect. Accordingly, the memory dies in the second memory die bin may be implemented in products which are more read intensive.

Once the memory die is placed in either the first VSG memory die bin or the second VSG memory die bin (at block615or block620), the method600includes returning to block605and selecting the next memory die to sort.

While method600is directed to sorting memory dies during production of the data storage device102, the memory dies may instead be sorted logically by the data storage device controller106.FIG.7provides a method700for sorting memory dies into memory die groups based on their VSG. The data storage device controller106may perform the method700during an initial set-up and prior to storing any data in the memory104. In some implementations, the data storage device controller106implements the memory die management module124to perform the method700.

The method700includes selecting, with the data storage device controller106, the next memory die (at block705). In an instance where sorting of the memory dies has just been initiated and no memory dies have been sorted, an initial (e.g., a first) memory die may be selected. The memory dies may be, for example, the memory units107A-107N within the memory104. The method700includes determining, with the data storage device controller106, whether the VSG of the selected memory die is less than or equal to a first voltage threshold (at decision block710). The voltage threshold may be, for example, 4.6 V. In some implementations, the voltage threshold is selected such that the lowest available VSG is greater than the SGD upper tail voltage by an overdrive value A.

When the VSG of the selected memory die is not less than or equal to the first voltage threshold (“NO” at decision block710), the method700includes assigning, with the data storage device controller106, the memory die to a first VSG memory die group (at block715). Memory dies assigned to the first VSG memory die group may be more susceptible to the impacts of downshift effect. Accordingly, the memory dies assigned to the first VSG memory die group may store data that is less read intensive.

When the VSG of the selected memory die is less than or equal to the first voltage threshold (“YES” at decision block710), the method700includes assigning, with the data storage device controller106, the memory die to a second VSG memory die group (at block720). Memory dies assigned to the second VSG memory die group may be less susceptible to the impacts of downshift effect. Accordingly, the memory dies assigned to the second VSG memory die group may store data that is more read intensive.

Once the memory die is assigned to either the first VSG memory die group or the second VSG memory die group (at block715or block720), the method700includes returning, to block705and selecting, with the data storage device controller106, the next memory die to sort.

To ensure a memory die package is capable of handling both read intensive data and non-read intensive data, dies assigned to both the first VSG memory die group and the second VSG memory die group may be stacked within a memory package.FIG.8provides a method800of sorting memory dies during packaging. In some implementations, the data storage device controller106performs the method800during packaging of the memory dies. The data storage device controller106may implement the memory die management module124to perform the method800.

The method800includes selecting, with the data storage device controller106, memory dies for a multi-die memory package including both dies from both the first VSG memory die group and the second VSG memory die group (at block805). For example, the data storage device controller106includes at least one die from the first VSG memory die group and at least one of the second VSG memory die group in a multi-die package.

The method800includes determining, with the data storage device controller106, whether the multi-die package includes memory dies from both the first VSG memory die group and the second VSG memory die group (at decision block810). In some instances, the data storage device controller106ensures a particular ratio of memory dies from the first VSG memory die group and memory dies from the second VSG memory die group is satisfied. As one example, the data storage device controller106may ensure there are twice as many memory dies from the first VSG memory die group included in the multi-die package than memory dies from the second VSG memory die group. In other instances, the ratio of memory dies from the first VSG memory die group and memory dies from the second VSG memory die group may be a variable ratio that is varied to meet the requirements of a particular application. In yet other instances, the ratio of memory dies from the first VSG memory die group and memory dies from the second VSG memory die group may be a predetermined fixed ratio.

When the multi-die package does not include memory dies from both the first VSG memory die group and the second VSG memory die group (“NO” at decision block810), the method800includes returning, with the data storage device controller106, to block805. When the multi-die package does include memory dies from both the first VSG memory die group and the second VSG memory die group (“YES” at decision block810), the method800includes completing, with the data storage device controller106, the memory die selection process (at block815).

After the data storage device102is manufactured and storing data, the data storage device controller106may distribute data between memory dies of the first VSG memory dies and the second VSG memory dies based on how often the data is read.FIG.9provides a method900for allocating data within the memory dies based on how often the data is read. In some implementations, the data storage device controller106performs the method900. The data storage device controller106may implement the memory die management module124to perform the method900.

The method900includes monitoring, with the data storage device controller106, how often data stored in a memory die (e.g., a memory unit107A-107N) is read (at block905). The method900includes determining, with the data storage device controller106, whether the data stored in the memory die is being read repeatedly (at decision block910). As one example, the data storage device controller106compares how often data stored in the memory die is read (e.g., a cumulative read occurrence) to a read threshold. The read threshold may indicate a number of reads over time, such as, for example, 10,000 reads in an hour.

When the data stored in the memory die is not being read repeatedly (“NO” at decision block910), method900includes classifying, with the data storage device controller106, the data as “cold” data (at block915). For example, the read events over time of the data stored in the memory die is less than the read threshold. When the data stored in the memory die is being read repeatedly (“YES” at decision block910), the method900includes classifying, with the data storage device controller106, the data as “hot” data (at block920). For example, the read events over time of the data stored in the memory dies is greater than or equal to the read threshold.

After classifying the data as “hot” data (at block920), the method includes relocating, with the data storage device controller106, the “hot” data to the second VSG memory die group in the multi-die package during the next “Data Re-Program” Operation (at block925). For example, during a “Data Re-Program” Operation, the data storage device controller106ensures that data experiencing a high number of read events (e.g., cumulative read disturb) is stored within VSG memory dies with a lower VSG value. The “Data Re-Program” Operation may occur at set frequencies, such as once a day, once a week, once a month, or the like. In some instances, the “Data Re-Program” Operation occurs as soon as data is identified as “hot.” Should “hot” data be stored in a memory die within the first VSG memory die group, the data storage device controller106relocates the data to the second VSG memory die group.

As one example,FIG.10provides a multi-die package1000including a first VSG memory die group1005and a second VSG memory die group1010. The first VSG memory die group1005includes memory dies with a VSG greater than the voltage threshold (at block715ofFIG.7), and the second VSG memory die group1010includes memory dies with a VSG less than or equal to the voltage threshold (at block720ofFIG.7). Should data within the first VSG memory die group1005be identified as “hot” data, the data storage device controller106relocates the “hot” data to the second VSG memory die group1010.

Returning toFIG.9, after classifying the data as “cold” data (at block915), the method900includes relocating, with the data storage device controller106, the “cold” data to the first VSG memory die group in the multi-die package (at block930). As “hot” data is moved to memory dies in the second VSG memory die group, the space available to store data within the second VSG memory die group decreases. Accordingly, “cold” data that experiences less read events may be moved from memory dies within the second VSG memory die group to memory dies within the first VSG memory die group. Relocation of the “cold” data to the first VSG memory die group may occur during the “Data Re-Program” Operation, or may occur at a time when data is not actively being stored or read by the data storage device controller106. In some implementations, the “cold” data is relocated to the first VSG memory die group when the data storage device controller106detects that the second VSG memory die group has insufficient space (or is approaching having insufficient space) for storing new data. With reference to FIG.10, the data storage device controller106relocates the “cold” data from the second VSG memory die group1010to the first VSG memory die group1005.

After relocating the “cold” data and “hot” data at blocks930and925, respectively, the method900includes prioritizing, with the data storage device controller106, scrambling (e.g., randomizing) “hot” data within the second VSG die group and scrambling “cold” data within the first VSG die group during subsequent “Data Re-Program” Operations. Scrambling data may include relocating (or transferring) the data to a different memory block. By scrambling the data within their respective VSG die groups, the data storage device controller106maintains storage space within the VSG die groups for additional data to be stored. In some instances, scrambling is performed in response to an increase in failed bits or another similar abnormal condition of the data stored within a block.

In some instances, memory dies within the first VSG die group and the second VSG die group are stacked in the order of their VSG values. For example, when the voltage threshold (at decision block710) is 4.7 V, the first VSG die group may include memory dies having VSG values ranging from 4.8 V to 7.4 V, and the second VSG die group may include memory dies having VSG values ranging from 3.8 V to 4.7 V. The memory dies may then be stacked from lowest VSG value (3.8 V) to the highest value (4.7 V) within the second VSG die group, and stacked from lowest value (4.8 V) to the highest value (7.4 V) within the first VSG die group. In other implementations, the memory dies are scrambled within the first VSG die group and the second VSG die group such that the VSG values of the memory dies are randomized.

Additionally, in some instances, the memory dies within the multi-die package are stacked alternating according to their VSG die group. For example, a die in the first VSG die group may be sandwiched between two dies in the second VSG die group, and a die in the second VSG die group may be sandwiched between two dies in the first VSG die group.