Analog multiplying-averaging circuit and wattmeter circuit using the circuit

In an analog multiplying-averaging circuit for detecting very small mean power in a wide band and a wattmeter using the circuit, a first voltage signal is inputted to a base and a second voltage signal is inputted to a collector of one transistor circuit of a first differential amplifier, to supply a power corresponding to the multiplying-averaging of the two input signals to the collector of the transistor circuit. A base and a collector of another transistor circuit of the first amplifier are grounded to extract a DC collector voltage corresponding to junction temperature differences produced between the two transistor circuits from the collector of the other transistor circuit. A second amplifier is provided, which also has two transistor circuits. A base of one transistor circuit of the second differential amplifier is grounded. The second voltage signal is inputted to a collector of the one transistor circuit, and a base and a collector of another transistor circuit of the second amplifier are grounded to also extract a DC collector voltage corresponding to junction temperature differences of the two transistor circuits from the collector of the other transistor circuit of the second amplifier. From the two DC collector voltages, a signal corresponding to the multiplying-averaging of two input signals is obtained.

TECHNICAL FIELD 
This invention relates to an analog multiplying-averaging circuit and a 
wattmeter circuit using the circuit and, more particularly, to an analog 
multiplying-averaging circuit capable of detecting very small mean power 
in a wide band and a wattmeter circuit using said circuit therein. 
BACKGROUND ART 
An action for multiplying two input signals v(t), i(t) is essential in 
order to measure AC mean power, by way of example. In the prior art, an 
electrodynamometer type of wattmeter has been used for that purpose. But 
this type of wattmeter comprises a fixed coil and a movable coil and 
carries out mechanical action for multiplication, and in addition an error 
is generated due to reactance inside the wattmeter and the error changes 
according to a power factor of a load or a frequency, so that a compact 
wattmeter for a broad band is hardly available. 
Also there is a wattmeter circuit which uses so-called an analog multiplier 
IC and outputs an instantaneous voltage e(t) corresponding to 
v(t).times.i(t), but the circuit is extremely complicated and expensive, 
and furthermore the following calculation must be carried out separately 
outside: 
##EQU1## 
if it is necessary to know mean power 
P=.vertline.V.vertline..vertline.I.vertline. cos .theta.. 
Conventional power measurement has been carried out as described above, and 
a compact and simply constructed circuit capable of detecting very small 
mean power in a broad band, has not been available. 
DISCLOSURE OF INVENTION 
Accordingly, an object of the present invention is to provide a compact and 
simply constructed analog multiplying-averaging circuit capable of highly 
precise detection in a broad band, in which multiplying-averaging of two 
input signals is achieved, as well as a wattmeter circuit which employs 
this circuit. 
According to the present invention, the foregoing object is attained by 
providing an analog multiplying-averaging circuit characterized in that a 
first voltage signal is inputted to a base and a second voltage signal is 
inputted to a collector of one transistor circuit of a differential 
amplifier, a base and a collector of another transistor circuit are 
signally grounded. 
According to the present invention, the foregoing object is attained by 
providing a wattmeter circuit characterized by comprising: an analog 
multiplying-averaging circuit in which a first voltage signal is inputted 
to a base and a second voltage signal is inputted to a collector of one 
transistor circuit of a differential amplifier, a base and a collector of 
another transistor circuit are signally grounded; an offset-voltage 
generating circuit in which a base of one transistor circuit of a 
differential amplifier is signally grounded, said second voltage signal is 
inputted to a collector of this transistor circuit, a base and a collector 
of another transistor circuit are signally grounded; and an output takeoff 
circuit for extracting a signal proportional to a difference between 
collector voltages of the other transistor circuits of said analog 
multiplying-averaging circuit and offset-voltage generating circuit. 
And, in the analog multiplying-averaging circuit of the present invention, 
the first voltage signal is inputted to the base and the second voltage 
signal is inputted to the collector of one transistor circuit of the 
differential amplifier, thereby to supply to the collector a power 
corresponding to the multiplying-averaging of the two input signals. The 
base and collector of another transistor circuit are signally grounded, 
thereby to produce a junction temperature difference between the one 
transistor circuit and the other transistor circuit. As a result, a DC 
collector voltage corresponding to the junction temperature difference is 
obtained from the collector of the other transistor circuit. 
Further, in the wattmeter circuit according to the present invention, the 
analog multiplying-averaging circuit is such that average power in the 
form {.vertline.V.vertline..vertline.I.vertline.cos 
.theta.+f(.vertline.V.vertline.)} is supplied to the collector of one 
transistor circuit of the circuit and a DC collector voltage corresponding 
to a junction temperature difference developed between this transistor 
circuit and another transistor circuit is extracted from collector of the 
other transistor circuit. The offset-voltage generating circuit is such 
that average power in the form {f.vertline.V.vertline.} is supplied to the 
collector of one transistor circuit and a DC collector voltage 
corresponding to a junction temperature difference developed between this 
transistor circuit and another transistor circuit is extracted from the 
collector of the other transistor circuit. The output takeoff circuit 
amplifies the difference between two DC collector voltages that have been 
extracted, and delivers a DC voltage signal proportional to the difference 
{.vertline.V.vertline. .vertline.I.vertline. cos .theta.} between the two 
supplied power signals.

BEST MODE FOR CARRYING OUT THE INVENTION 
An embodiment in which the present invention is applied to a bipolar 
transistor will now be described in detail with reference to the 
accompanying drawings. 
FIG. 1 is a circuit diagram showing a wattmeter circuit embodying the 
present invention. In FIG. 1, a current i(t) is the current of an electric 
power to be measured, or a current proportional to this current, and a 
voltage v(t) likewise is the voltage of the electric power to be measured, 
or a voltage proportional to this voltage. The wattmeter includes a 
current/voltage converting circuit (CVC) 1 that converts the input current 
i(t) into a voltage source {-R.sub.r i(t)}, a voltage follower (VF) 2 for 
outputting the voltage source v(t) that is the same as the input voltage 
v(t), a collector multiplying circuit (analog multiplying-averaging 
circuit) 3 so constructed that a signal at the voltage source {-R.sub.f 
i(t)} enters a base bl of a transistor T.sub.1, a signal at the voltage 
source v(t) enters a collector cl of this transistor and a base b2 and 
collector c2' of a transistor T.sub.2 are signally grounded, an 
offset-voltage generating circuit 4 so constructed that a base b4 of a 
transistor T.sub.4 is signally grounded, the signal at the voltage source 
v(t) enters a collector c4 of this transistor and a base b5 and a 
collector c5 of a transistor T.sub.5 are signally grounded, and an output 
takeoff circuit 5 which extracts a DC voltage signal V.sub.P proportional 
to the difference between DC collector voltages V.sub.c2, V.sub.c5 of the 
transistors T.sub.2, T.sub.5 in the collector multiplying circuit 5 and 
offset-voltage generating circuit 4, respectively. 
It is preferred that these transistor circuits T.sub.1 through T.sub.6 be 
incorporated in the same IC chip made of silicon, for example, so that 
they will exhibit identical characteristics both electrically and 
thermally. 
FIG. 2 is a circuit diagram illustrating a differential-mode signal 
equivalent circuit of a collector multiplying circuit 5, and FIGS. 12 and 
13 are diagrams for describing the derivation of FIG. 2. The derivation of 
the differential-mode signal equivalent circuit of FIG. 2 will now be 
described. 
First, C.sub.c in FIG. 1 represents a coupling capacitor, and C.sub.b 
denotes a bypass capacitor. These capacitors can be regarded as being 
short-circuited with respect to the signal. Accordingly, the signal 
voltages {-R.sub.f i(t)} and v(t) are applied respectively to the base bl 
and collector cl of the transistor T.sub.1, and the base b2 and collector 
c2 of the transistor T.sub.2 are signally at ground potential. 
The equivalent circuit of FIG. 12 is obtained if we let h parameters 
represent the foregoing and let .alpha.=1, h.sub.rb =0 hold. In FIG. 12, 
R.sub.e represents a high resistance exhibited by the emitter circuit of 
the transistor T.sub.3. Since {-R.sub.f i(t)} in FIG. 12 is the voltage 
source, an identical voltage source {-R.sub.f i(t)} may be considered to 
be present in the block enclosed by the broken line of FIG. 12. 
Accordingly this circuit may be separated from the remaining circuitry at 
the potion indicated by the "x" mark in FIG. 12. 
Accordingly, the equivalent circuit of FIG. 15 is obtained by cutting off 
the portion enclosed by the dot-dash-line of FIG. 12 and rewriting it. 
When the magnitudes of the voltage source {-R.sub.f i(t)} and a voltage 
source {.alpha.i.sub.e1 /h.sub.ob } are compared, it is found that the 
following relation holds since i.sub.e1 =-R.sub.f i(t)/2h.sub.ib holds 
true from the inequality h.sub.ib &lt;&lt;R.sub.e in FIG. 12. 
##EQU2## 
where i(t).noteq.0. 
Since h.sub.ob h.sub.ib is actually very small, e.g., on the order of 
10.sup.-4, the end result is that the voltage source {-R.sub.r i(t)} of 
FIG. 15 is very small in comparison with the voltage source 
{.alpha.i.sub.e1 /h.sub.ob } and therefore is negligible. 
Accordingly, the equivalent circuit representing the portion of collector 
c1 of transistor T.sub.1 in FIG. 2 is obtained by rewriting the above 
circuit neglecting the voltage source {-R.sub.f i(t)} of FIG. 15. 
It should be noted that, since {-R.sub.f i(t)}=0 holds when i(t)=0 holds, 
the equivalent circuit representing the portion of collector c1 of the 
transistor T.sub.1 in FIG. 2 is obtained as a matter of course. 
Furthermore, input voltages v.sub.b1, V.sub.b2 to the respective base 
terminals b1, b2 may generally be represented by the sum of a common-mode 
signal and differential-mode signal as follows: 
##EQU3## 
However, since it may be considered that the common-mode signal is not 
amplified because of the high resistance R.sub.e, the following equations 
may be assumed to hold by taking into account only the differential-mode 
signal: 
##EQU4## 
Furthermore, since the high resistance R.sub.e of FIG. 12 may be considered 
to represent a short circuit with regard to the differential-mode signal, 
the differential-mode signal equivalent circuit of FIG. 2 is obtained. 
Next, the collector multiplying effect in the transistor T.sub.1 will be 
described based upon the differential-mode signal equivalent circuit in 
FIG. 2. In FIG. 2, a signal current i.sub.d =-R.sub.f i(t)/2h.sub.ib flows 
into the emitter e.sub.1 of the transistor T.sub.1 owing to the fact that 
v.sub.b1 =-R.sub.f i(t)/2 holds. In addition, since .alpha.=1 holds, an 
identical current i.sub.d is drawn from the collector c1 of the transistor 
T.sub.1. On the other hand, the signal voltage v(t) is being impressed 
upon the collector c1 of the transistor T.sub.1, and therefore 
instantaneous power p.sub.c1 (t) supplied to the collector c1 of 
transistor T.sub.1 is expressed as follows: 
##EQU5## 
Thus, the multiplying effect of the collector in the transistor T.sub.1 is 
indicated by the first term on the right side of Equation (1). Since the 
second term on the right side of this equation is superfluous, an 
identical power loss is generated in the offset-voltage generating circuit 
4, described below, so as to cancel the second term. On the other hand, 
since the signal voltage v(t) is not being impressed upon the collector c2 
of transistor T.sub.2, instantaneous power p.sub.c2 (t) supplied to the 
collector c2 of transistor T.sub.2 is equal to zero. 
If we let v(t)=V.sub.m cos.sub..omega. t and i(t)=I.sub.m cos(.sub..omega. 
t+.theta.) represent each of the input signals, we have: 
##EQU6## 
Arranging this in the form of a trigonometric equation, we have: 
##EQU7## 
Since the terms on the first line of the right side of Equation (3) 
represent a DC component, these terms apply average power to the collector 
of transistor T.sub.1. However, since the terms on the second line 
represent a 2.sub.107 component, these do not apply average power to the 
collector of transistor T.sub.1. 
FIG. 5 is a circuit diagram showing a differential-mode signal equivalent 
circuit of the offset-voltage generating circuit 4. According to FIG. 1, 
since the base inputs to the transistors T.sub.4 and T.sub.5 are both at 
ground potential, the differential input is equal zero in FIG. 5 and 
therefore the potion relating to the signal current i.sub.d also is zero. 
On the other hand, the signal voltage v(t) is being applied to the 
collector c4 of transistor T.sub.4, and therefore instantaneous power 
p.sub.c4 (t) supplied to the collector c4 of transistor T.sub.4 is 
expressed as follows: 
EQU p.sub.c4 (t)=h.sub.ob v.sup.2 (t) (4) 
Further, since the signal voltage v(t) is not being applied to the 
collector c5 of transistor T.sub.5, instantaneous power p.sub.c5 (t) 
supplied to the collector c5 of transistor T.sub.5 is equal to zero. 
Furthermore, if the input signal is expressed by v(t)=V.sub.m 
cos.sub..omega. t and rearranging is performed in a manner similar to that 
described above, we have: 
##EQU8## 
Since the first term on the right side of Equation (5) is a DC component, 
this term applies average power to the collector of transistor T.sub.4. 
However, since the second term is a 2.sub..omega. component, this does not 
apply average power to the collector of transistor T.sub.4. 
Thus, in accordance with Equation (3), signal (average) power 
.DELTA.P.sub.c1, expressed by the following equation, is supplied to the 
collector cl of transistor T.sub.1 : 
##EQU9## 
In accordance with Equation (5), signal (average) power .DELTA.P.sub.c4, 
expressed by the following equation, is supplied to the collector c4 of 
the transistor T.sub.4 : 
##EQU10## 
In addition, the temperature at the junction of transistors T.sub.1 and 
T.sub.2 varies owing to the signal power .DELTA.P.sub.c1, a heat flow 
occurs due to a difference in the power losses between the transistors 
T.sub.1 and T.sub.2, and a DC collector voltage V.sub.c2 corresponding to 
this change in junction temperature appears at the collector c2 of 
transistor T.sub.2. Similarly, the temperature at the junction of 
transistors T.sub.4 and T.sub.5 varies owing to the signal power 
.DELTA.P.sub.c4, a heat flow occurs due to a difference in the power 
losses between the transistors T.sub.4 and T.sub.5, and a DC collector 
voltage V.sub.c5 corresponding to this change in junction temperature 
appears at the collector c5 of transistor T.sub.5. Accordingly, true 
average power corresponding to the difference between .DELTA.P.sub.c1 and 
.DELTA.P.sub.c4 can be determined by detecting the difference between 
V.sub.c2 and V.sub.c5. This process will be described below. 
FIG. 4 is a circuit diagram showing a thermal equivalent circuit of the 
transistors T.sub.1 and T.sub.2. Shown in FIG. 4 are signal powers 
.DELTA.P.sub.c1, .DELTA.P.sub.c2, amounts of change .DELTA.T.sub.j1, 
.DELTA.T.sub.j2 in junction temperature due to signal power, a thermal 
resistance .theta..sub.m between junctions, and thermal resistance 
.theta..sub.ja between the junctions and ambient air. Since 
.DELTA.P.sub.c2 =0 holds in accordance with the foregoing, the common-mode 
signal component of the signal power may be represented by .DELTA.P.sub.c1 
/2 and differential-mode signal component by .+-..DELTA.P.sub.c1 /2. As a 
result, the thermal equivalent circuit of FIG. 4 can be considered upon 
being separated into a common-mode signal thermal equivalent circuit shown 
in FIG. 5 and a differential-mode signal thermal equivalent circuit shown 
in FIG. 6. 
If the common-mode signal thermal equivalent circuit of FIG. 5 is solved, 
the amount of change .DELTA.T.sub.ja in the junction temperature will be 
as follows: 
##EQU11## 
If the differential-mode signal equivalent circuit of FIG. 6 is solved, the 
amount of change .DELTA.T.sub.jd /2 in the junction temperature will be as 
follows: 
##EQU12## 
Accordingly, by substituting Equation (6) in .DELTA.P.sub.c1 of Equation 
(9) and rearranging, the junction temperature difference .DELTA.T.sub.jd 
between the junctions of transistors T.sub.1 and T.sub.2 may be expressed 
as follows: 
##EQU13## 
FIG. 11 is a graph showing the relationship between the position of the 
junction of transistors T.sub.1, T.sub.2 and the temperature at this 
junction. In FIG. 11, T.sub.a represents ambient temperature and T.sub.jo 
represents the junction temperature in the absence of a signal. These are 
related by the following equation: 
EQU T.sub.jo =T.sub.a +.theta..sub.ja P.sub.c 
where P.sub.c represents collector loss in the absence of a signal. Since 
the change in junction temperature due to the signal power is added to 
this, the junction temperatures T.sub.j1,T.sub.j2 of the transistors 
T.sub.1, T.sub.2 may be expressed by following equations: 
##EQU14## 
Thus, when the junction temperatures of the transistors T.sub.1, T.sub.2 
change, the base-to-emitter voltages of the transistors T.sub.1, T.sub.2 
change. The process for obtaining the DC collector voltage V.sub.c2 
corresponding to this change will be described below. 
FIG.7 is a circuit diagram illustrating the DC operation of the wattmeter 
circuit according to this embodiment. Signals indicated in FIG. 7 include 
direct currents I.sub.E, I.sub.B, I.sub.c, an emitter voltage V.sub.E and 
a base-emitter voltage V.sub.BE. 
In the collector multiplying circuit 5 of FIG. 7, the collector potential 
V.sub.c2 of transistor T.sub.2 is given by the following: 
EQU V.sub.c2 =V.sub.cc -R.sub.c I.sub.c2 -R.sub.c .DELTA.I.sub.c2 (13) 
Here .DELTA.I.sub.c2 represents the amount of change in the collector 
current of the transistor T.sub.2 due to a change in junction temperature 
and is obtained as set forth below. 
In general, since the base-emitter voltage of a transistor is a function of 
junction temperature, emitter current and base-collector voltage, we have 
the following relations: 
EQU V.sub.BE1 =f.sub.1 (T.sub.j1,I.sub.E1,V.sub.CB1) 
EQU V.sub.BE2 =f.sub.2 (T.sub.j2,I.sub.E2,V.sub.CB2) 
The amounts of change in these voltages may be expressed as follows in 
approximate terms: 
##EQU15## 
Accordingly, owing to the fact that the characteristics of the transistors 
T.sub.1 and T.sub.2 are identical, and by assuming that the following 
holds: 
##EQU16## 
the following relation is obtained from Equation (14): 
EQU .DELTA.V.sub.BE2 =.kappa.(.DELTA.T.sub.j1 -.DELTA.T.sub.j2)+h.sub.ib 
(.DELTA.I.sub.E1 -.DELTA.I.sub.E2) (16) 
This describes the temperature characteristics of the transistors T.sub.1 
and T.sub.2. 
In the collector multiplying circuit S shown in FIG. 7, the following 
relations hold: 
##EQU17## 
and the following relation is obtained from Equation (17): 
EQU V.sub.BE1 -V.sub.BE2 =-R.sub.b (I.sub.B1 -I.sub.B2) (18) 
With regard to the amounts of change in these voltages, the following 
relation is obtained: 
EQU .DELTA.V.sub.BE1 -.DELTA.V.sub.BE2 =-R.sub.b (.DELTA.I.sub.B1 
-.DELTA.I.sub.B2) (19) 
When this is substituted in Equation (16), the following relation is 
obtained: 
EQU -R.sub.b (.DELTA.I.sub.B1 -.DELTA.I.sub.B2)=.kappa.(.DELTA.T.sub.j1 
-.DELTA.T.sub.j2)+h.sub.ib (.DELTA.I.sub.E1 -.DELTA.I.sub.E2) (20) 
This describes the temperature dependence of the collector multiplying 
circuit 3. 
Furthermore, the following relations hold with regard to the transistors 
T.sub.1 and T.sub.2 : 
EQU .DELTA.I.sub.B1 =.DELTA.I.sub.c1 /h.sub.FE 
EQU .DELTA.I.sub.B2 =.DELTA.I.sub.c2 /h.sub.FE 
and it was assumed that .alpha.=1 holds. In addition, if I.sub.CBO =0, 
h.sub.ob =0 are assumed to hold, then .DELTA.I.sub.c1 =.DELTA.I.sub.E1, 
.DELTA.I.sub.C2 =.DELTA.I.sub.E2 can be regarded as holding. Therefore, 
when relations above are applied to Equation (20) and this equation is 
solved with regard to (.DELTA.I.sub.C1 -.DELTA.I.sub.C2), the following is 
obtained: 
##EQU18## 
Furthermore, since .DELTA.T.sub.j1 -.DELTA.T.sub.j2 =.DELTA.T.sub.jd holds 
and .DELTA.I.sub.C1 =-.DELTA. I.sub.c2 is established owing to the 
sufficiently stable current operation of the transistor T.sub.3, the 
amount of change .DELTA.I.sub.c2 in the collector current of the 
transistor T.sub.2 may be expressed as follows: 
##EQU19## 
By expressing the power to be measured, namely the average power, as 
follows: 
##EQU20## 
and substituting Equation (10) in .DELTA.T.sub.jd of Equation (22), the 
following equation is obtained: 
##EQU21## 
On the other hand, in the offset-voltage generating circuit 4 of FIG. 7, 
the collector potential V.sub.c5 of transistor T.sub.5 is given by the 
following: 
EQU V.sub.c5 =V.sub.cc -R.sub.c I.sub.c5 -R.sub.c .DELTA.I.sub.c5 (25) 
and the signal power supplied to the transistor T.sub.4 is as expressed by 
Equation (7). Therefore, .DELTA.I.sub.C5 may be expressed as follows in a 
manner similar to that set forth above: 
##EQU22## 
The output takeoff circuit 5 differentially amplifies V.sub.c2 and 
V.sub.c5 and the output voltage V.sub.P thereof is given by the following: 
##EQU23## 
Also, since these transistors T.sub.1 through T.sub.6 are chosen to have 
identical characteristics, we have I.sub.c2 =I.sub.c5. Accordingly, we 
have: 
##EQU24## 
Now, substituting Equations (24), (26) in Equation (28), we may write 
V.sub.P as follows: 
##EQU25## 
Furthermore, if sensitivity S is defined as follows: 
##EQU26## 
then the output DC voltage V.sub.P may be expressed by the following 
equation: 
##EQU27## 
Thus it is clear that the output DC voltage V.sub.P is proportional to the 
power P to be measured. 
FIG. 8 is a graph in which output DC voltage is plotted against input AC 
voltage, and FIG. 9 is a graph in which output DC voltage is plotted 
against input AC current. In FIGS. 8 and 9, .vertline.V.vertline., 
.vertline.I.vertline. are effective values. In both of these figures, the 
input/output characteristics may be regard as being substantially linear 
for an input AC voltage .vertline.V.vertline. of not more than 5V and an 
input AC current .vertline.I.vertline. of not more than 15 .mu.A. When the 
sensitivity S is found from the slope of straight line, the results shown 
in Tables 1 and 2 are obtained. 
TABLE 1 
______________________________________ 
.vertline.I.vertline. [.mu.A] 
S [mV/.mu.W] 
______________________________________ 
20 0.136 
15 0.140 
10 0.139 
5 0.142 
Mean of S 0.139 
______________________________________ 
TABLE 2 
______________________________________ 
.vertline.V.vertline. [V] 
S [mV/.mu.W] 
______________________________________ 
5 0.141 
4 0.140 
3 0.139 
2 0.138 
1 0.138 
Mean of S 0.139 
______________________________________ 
Table 1 and 2 indicate that the values of sensitivity S are substantially 
agree in all cases and that the actually measured value of sensitivity S 
is 0.139 mV/.mu.W. 
FIG. 10 is a graph in which the output DC voltage is plotted against the 
phase difference between .vertline.V.vertline. and .vertline.I.vertline.. 
The phase difference between .vertline.V.vertline. and 
.vertline.I.vertline. also can be expressed in the form V.sub.P =100 cos 
.theta.[mV], and the output DC voltage V.sub.P is proportional to cos 
.theta.. Accordingly, the wattmeter circuit can be utilized to measure 
phase difference as well as power factor. 
In the embodiment described above, the collector multiplying circuit 5 and 
the offset-voltage generating circuit 4 operate under identical 
conditions, and therefore a substantial offset effect is observed even in 
the non-linear range of the transistor characteristics. 
Further, in the foregoing embodiment, the current/voltage converting 
circuit (CVC) 1 is employed to detect the signal i(t). This means that the 
input impedance may be regarded as 0 (not more than 0.1 .OMEGA.), so that 
even a very small load current is capable of being detected in accurate 
fashion. 
In the foregoing embodiment, the voltage follower (VF) 2 is employed to 
detect the signal v(t). Since the input impedance of the voltage follower 
is very large, e,g., on the order of 10.sup.9 .OMEGA., voltage can be 
detected accurately without the load being influenced. 
Though i(t), v(t) are employed as the input signals in the foregoing 
embodiment, the present invention can be applied even in the case of other 
types of signals provided the signal is converted to a voltage source. 
Further, though a case in which an NPN transistor is used is described in 
the foregoing embodiment, it is obvious that a PNP transistor may be used 
as well. 
In accordance with the present invention, as described above, the 
arrangement is such that a first voltage signal is inputted to the base of 
one transistor circuit of a differential amplifier circuit, a second 
voltage signal is inputted to the collector thereof and the base and 
collector of another transistor circuit of the differential amplifier are 
signally grounded. As a result, an effect through which two inputs are 
multiplied is obtained at the collector of the one transistor circuit, and 
a DC voltage corresponding to the multiplying-averaging of the two inputs 
is extracted continuously from the collector of the other transistor 
circuit. Accordingly, it is possible to provide a compact and simply 
constructed analog multiplying-averaging circuit capable of highly precise 
detection over a wide band. 
Further, in accordance with the invention, the analog multiplying-averaging 
circuit is such that average power in the form 
[.vertline.V.vertline..vertline.I.vertline. cos 
.theta.+f(.vertline.V.vertline.)} is supplied to the collector of one 
transistor circuit of the circuit and a DC collector voltage corresponding 
to a junction temperature difference developed between this transistor 
circuit and another transistor circuit is extracted from collector of the 
other transistor circuit. The offset-voltage generating circuit is such 
that average power in the form {f.vertline.V.vertline.} is supplied to the 
collector of one transistor circuit and a DC collector voltage 
corresponding to a junction temperature difference developed between this 
transistor circuit and another transistor circuit is extracted from the 
collector of the other transistor circuit. The output takeoff circuit 
amplifies the difference between two DC collector voltages that have been 
extracted, and delivers a DC voltage signal proportional to the difference 
{.vertline.V.vertline. .vertline.I.vertline. cos .theta.} between the two 
supplied power signals. As a result, a compact, precise wattmeter capable 
of highly precise detection over a wide band can be provided at low cost. 
As many apparently widely different embodiments of the present invention 
may be made without departing from the spirit and scope thereof, it is to 
be understood that the invention is not limited to the specific 
embodiments thereof except as defined in the appended claims.