Method for filling a trench in a semiconductor product

Method for filling a trench in a semiconductor product is disclosed. A first material is deposited onto a semiconductor product having a surface in which at least one trench is formed. A first layer is formed within the trench and on the surface of the semiconductor product outside the trench. A second material is deposited to form a second layer above the first layer outside the trench and the trench is filled. Chemical mechanical polishing is performed so that the second layer is removed above the first layer outside the trench and whereby the first layer is at least uncovered outside the trench. Residual first material of the first layer is removed by wet-chemical etching.

This application claims priority to German Patent Application 10 2006 040 585.4, which was filed Aug. 30, 2006, and is incorporated herein by reference.

TECHNICAL FIELD

The invention relates to the field of semiconductor fabrication and in one embodiment, to a method for filling a trench in a semiconductor product.

BACKGROUND

In semiconductor fabrication, a plurality of individual structures are produced on a substrate (generally a semiconductor substrate). Etching methods, polishing methods, deposition methods and the like are used for this purpose. For many structure elements such as, for example, electrical terminal contacts, vertically contact-connecting contact hole fillings (vias), interconnects, etc., it is necessary firstly to etch trenches. Such trenches can be arranged in the semiconductor substrate, in a layer, for example, a dielectric layer, arranged on or above the semiconductor substrate, or in some other region of a semiconductor product. When the trenches are subsequently filled, usually a filling material is deposited over the whole area onto the partly finished semiconductor product and then removed superficially as far as the level of the upper edge of the trench. A partial etching back, a chemical mechanical polishing operation or some other etching method can be used for this purpose.

In semiconductor fabrication, it is always desirable for the semiconductor product to have a surface that is as planar as possible, i.e., a surface whose topmost structures produce the least possible topographies or height differences. This is necessary particularly owing to the limited depth of focus in the lithographic patterning of masks for further processing steps. A relatively planar surface is achieved by chemical mechanical polishing, for example, which involves moving a polishing pad in a lateral direction parallel to the substrate surface or to the surface of the semiconductor product, wherein a polishing slurry containing an etching component and also polishing grains that cause mechanical abrasion covers the polished surface and the polishing pad.

However, the plane surface ideally sought by means of the chemical mechanical polishing is generally achieved only approximately; different high removal rates of structure elements composed of different materials on different positions of a wafer (or within the circuit of a single chip) lead to height fluctuations of the top side which have an effect locally and globally over the entire wafer surface. These thickness fluctuations arise on account of the polishing process itself. The fluctuations turn out to be greater, the thicker a layer was that was removed beforehand by chemical mechanical polishing, the lower the selectivity is during the etching of a layer with respect to an underlying layer, and the longer the polishing operation lasts. A long polishing time is attained, in particular, when materials that are difficult to polish are to be removed. Thus, by way of example, time durations of a polishing operation carried out of 1000 seconds or more can lead to topographies that make it more difficult to further process the only partly finished semiconductor product.

If a trench is filled with a filling material, then the latter simultaneously covers the surface of the semiconductor product laterally outside the trench (and also above the trench itself) and must subsequently be removed again from the semiconductor product over the whole area at least at the level above the top side of the trench. It is typically etched back as far as a previously deposited etching stop layer that is more difficult to polish than the filling material. The etching stop layer can also comprise a layer sequence, particularly if further requirements are to be taken into account in the production of an integrated circuit. The layer sequence can comprise, for example, diffusion barrier layers, layers having a high electrical conductivity, adhesion-enhancing layers or other layers. If such layers were deposited below the actual filling material into the trench and the surface of the semiconductor product, these layers must subsequently be removed again from the surface of the semiconductor product outside the trench. Further polishing operations with in part further polishing slurries can be used for this purpose.

The polishing of the trench-filling material above the trench can already give rise to the above-mentioned unevennesses over the wafer area or the area of the semiconductor product. During the subsequent removal of the layers that were deposited below the trench filling and still cover the surface outside the trench, the unevennesses can also be intensified. By way of example, tungsten-containing layers or layer sequences can lead to additional considerable topographies, for instance if they are removed with the aid of a low polishing rate during a relatively lengthy polishing step. However, with other materials, too, there is the problem that with the aid of chemical mechanical polishing operations that are usually carried out after the filling of trenches or other depressions in order to remove excess material, the polished surface subsequently has a poorer planarity, i.e., greater unevennesses.

SUMMARY OF THE INVENTION

A method for filling a trench in a semiconductor product is provided, comprising, depositing a first material onto a semiconductor product having a surface in which at least one trench is formed, whereby a first layer is formed within the trench and on the surface of the semiconductor product outside the trench. A second material is deposited, whereby a second layer is formed above the first layer outside the trench and the trench is filled. Chemical mechanical polishing is performed, whereby the second layer is removed above the first layer outside the trench and whereby the first layer is at least uncovered outside the trench, and residual first material of the first layer is removed by wet-chemical etching.

Furthermore, a method for filling a trench in a semiconductor product is provided, comprising, providing a semiconductor product having at least one substrate, wherein the semiconductor product has a surface in which at least one trench is arranged. A first interlayer is deposited onto the surface of the semiconductor product and into the trench. A first layer composed of a metallic first material is deposited onto the first interlayer by means of a chemical vapor deposition. A second interlayer is deposited onto the first layer. A metallic second material, which predominantly contains copper, is deposited onto the second interlayer by means of an electrolytic deposition until the second material forms a second layer on the second interlayer outside the trench and the trench is completely filled with the second material. Chemical mechanical polishing is performed, whereby the first layer is uncovered outside the trench and the residual material of the first layer is retained on the first interlayer, and the residual material of the first layer is completely removed from the first interlayer by means of wet-chemical etching using hydrogen peroxide.

Furthermore, a method for producing a conductive trench filling on a semiconductor product having at least one trench is provided, comprising, providing a semiconductor product, which has a substrate and a dielectric layer above the substrate and which furthermore has at least one trench which, proceeding from a top side of the semiconductor product, reaches at least into the dielectric layer. At least one first layer composed of a first material is deposited, wherein the first layer extends over a surface of the semiconductor product and into the at least one trench. At least one second layer composed of an electrically conductive second material is deposited on or over the first layer until the second material covers the first layer over the whole area and fills the at least one trench. Chemical mechanical polishing is performed until, over the surface of the semiconductor product outside the at least one trench, the second material has been removed and the first material has been uncovered, and the uncovered first material outside the at least one trench is removed by means of wet-chemical etching until the surface of the semiconductor product has been uncovered outside the at least one trench.

Furthermore, a method for processing a semiconductor product is provided, comprising, providing a semiconductor product having at least one trench arranged in a surface of the semiconductor product. At least one first layer onto the surface of the semiconductor product is deposited and onto an inner wall of the trench, at least one second layer is deposited, which fills the trench and covers the first layer above the surface of the semiconductor product. The second layer outside the trench is etched back to the level of the first layer, whereby the first layer is at least uncovered outside the trench, and the first layer is selectively wet-chemically etched until the surface of the semiconductor product is uncovered again outside the trench.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In accordance withFIG. 1, a semiconductor product1is provided, which has a substrate2, preferably a semiconductor substrate composed of silicon, for example. Firstly, at least one trench5is etched into the semiconductor product1, which is, in particular, an only partly finished semiconductor product. The trench5is etched into a surface4of the semiconductor product1, whereby a depression is formed in the surface4. The trench5that arises in this way can extend over only one or else over a plurality of layers arranged on the semiconductor substrate. Likewise, the trench5can also extend right into the substrate2. It can also be etched as far as the rear side of the semiconductor product1or as far as the rear side of the substrate2, in which case it passes through the entire thickness of the semiconductor product1. The trench can either be etched into the surface4of a layer arranged on the substrate, or it can be etched directly into an uncovered top side of the semiconductor substrate2, which top side is simultaneously the surface4of the semiconductor product. The type of semiconductor product provided with the trench and the form and the depth of the semiconductor product depend on the respective application and can correspondingly vary.

In accordance withFIG. 2, a first interlayer11is deposited onto the surface4of the semiconductor product1and also into the trench5; the interlayer can contain titanium, in particular. The first interlayer11can be deposited, for example, by a chemical or preferably physical vapor deposition. The first interlayer11is not necessarily required; it can also be obviated, in which case the first layer12deposited in accordance withFIG. 3is deposited directly onto the semiconductor product1itself. However, the first interlayer11can be additionally provided, for example, as an additional adhesion-enhancing layer, as a contact layer or as a barrier layer between the first layer12that is still to be deposited and the semiconductor product. The first interlayer11can be, for example, a titanium layer, a titanium nitride layer or a layer sequence composed of a titanium layer and a titanium nitride layer arranged thereon (or vice versa).

In accordance withFIG. 3, a first layer12composed of a first material12ais deposited. The deposition of the first layer12is preferably effected by a chemical vapor deposition. The material of the first layer12(i.e., the first material12a) preferably substantially comprises tungsten (W). By way of example, a tungsten layer can be deposited as first layer12.

In accordance withFIG. 4, a second interlayer13is optionally deposited. However, just like the first interlayer11, the second interlayer can also be obviated. In such applications, for example, in which an additional diffusion barrier layer, an adhesion-enhancing layer or a layer that increases the conductivity is desired as second interlayer13on the first layer12, this can additionally be formed as second interlayer13. This is preferably done, in accordance withFIG. 4, by a chemical or preferably a physical vapour deposition, whereby the second interlayer13is formed on the first layer12composed of the first material12a. The second interlayer13can also be deposited on the first interlayer11, i.e., before the deposition of the first layer12. The second interlayer13can contain tantalum. The second interlayer13can have, for example, a tantalum layer, a tantalum nitride layer or a layer sequence composed of a tantalum layer and a tantalum nitride layer arranged thereabove (or vice versa). In particular, a layer that prevents or makes more difficult the diffusion of material of a second layer (reference symbol14in the subsequent figures) to be deposited thereon can be deposited as second interlayer13.

FIG. 5shows an example of a semiconductor product1which is covered, in the manner described above, with a first layer12and optionally additionally with a first and/or second interlayer11,13. The semiconductor product1can have a substrate2, for example, on which a trench5is to be etched between two transistors50. The semiconductor product1provided for this purpose has a plurality of transistors50on a surface of the semiconductor substrate2, which transistors can be high-voltage transistors or power transistors, for example. They can be in particular component parts of a “radio frequency power device” to be produced, that is to say power transistors of a semiconductor circuit that operates at radio frequency. The semiconductor circuit can be, for example, an antenna driver device or an antenna output stage for mobile radio, for instance for a base station. Accordingly, the semiconductor product1can be a base station (or some other mobile radio device) with an antenna driver device or an antenna output stage.FIG. 5illustrates by way of example such a transistor50to the right of the trench5; a further transistor50is indicated in mirror-inverted fashion with respect thereto to the left of the trench5, but is not completely represented inFIG. 5. However, its design can correspond to the transistor50arranged to the right of the trench. The transistors50have a gate electrode51, a source electrode52and a drain electrode53. The drain electrode53is surrounded by two LDD diffusion regions (lightly doped drain), wherein a first LDD diffusion region LDD1produces a lateral distance, that reduces the electric field strength, between gate electrode51and drain electrode53and a further LDD diffusion region LDD2surrounds the drain electrode53from all sides in the lateral direction and also from below. The source electrode52is arranged on the opposite side of the gate electrode51; it can likewise be surrounded by a more weakly doped region in the direction of the substrate interior and in the direction of the trench5to be filled. Arranged on the surface of the semiconductor substrate2is the gate dielectric61below the gate electrode51. Below the gate dielectric61runs the channel region60of the transistor50, covered by the gate electrode51. Finally, in addition pocket dopant regions55can also be provided, as well as field plates57, which likewise serve for shielding individual component parts of the transistor50from one another. The field plates57can cover, for example, a corner region, facing the drain region53, of the gate electrode51(or an insulation layer58arranged thereon). The field plates57and also a drain contact layer56arranged on the drain electrode53can be formed, for example, from a titanium layer, a titanium nitride layer or a layer sequence composed of a titanium layer and a titanium nitride layer.

The transistors50illustrated inFIG. 5and also further microelectronic components of the semiconductor product1can be covered, for example, by a dielectric layer3having a top side that simultaneously forms the surface4of the semiconductor product1.FIG. 5illustrates only one possible, arbitrarily chosen example of a semiconductor product1into which subsequently a trench5is etched (FIG. 1) and a sequence of a plurality of layers is deposited, which cover the surface4of the semiconductor product1and finally fill the trench.FIG. 5illustrates the first layer12composed of a first material12a, for example, a tungsten-containing material (in particular tungsten), and also the first and second interlayers11,13that are optionally additionally present. Instead of the materials presented with reference toFIGS. 2 to 4, it is also possible to choose other materials for the two interlayers and the first layer.

AlthoughFIG. 5illustrates the layer thickness of the layers11,12and13as larger outside the trench5(i.e., at its trench wall5a) than within the trench, the layer thicknesses illustrated with an exaggerated size on the surface4of the semiconductor product1only serve for clarity of illustration; in actual fact the layer thickness at least of the first layer12will in practice be just the same in magnitude on the trench wall5aas on the surface4of the semiconductor product1outside the trench5. This can be ensured, for example, by means of a suitable deposition method, for example, a chemical vapor deposition of the first layer12. The interlayers11,13are preferably deposited by means of a physical vapor deposition.

The first layer12preferably comprises a metal, for example, tungsten. An alloy can likewise be used. In this exemplary embodiment, the first layer12preferably serves for providing, within the trench5, the trench wall5awith a conductive layer that later enables an electrolytic deposition of a material14athat fills the trench5.

FIG. 5illustrates a semiconductor product1, the surface4of which is planar; on account of the dielectric layer3, which levels topographies on the substrate surface which arise as a result of the transistors50and other microelectronic structures, the semiconductor product1no longer has an appreciable topography prior to the etching of the trench. The deposition of the relatively thin layers11,12and13also does not produce an appreciable topography outside the trench5.

FIG. 5furthermore shows that a second layer14having a significantly larger layer thickness was deposited onto the semiconductor product covered with the layers11,12,13.

The implementation and the result of this deposition are illustrated schematically inFIGS. 6 and 7. In this exemplary embodiment, the deposition of the second layer14is preferably effected by means of an electrolytic deposition (FIG. 6). In addition, a preceding deposition step for forming a growth seed layer15can be provided, as will also be explained later with reference toFIGS. 21 and 22. In this case, a thin layer composed of the second material14and having a thickness of just a few atomic layers can be deposited, for example, deposited with a layer thickness of less than about 3 nanometers, before the main portion of the second material is deposited on the growth seed layer15(the growth seed layer preferably comprises copper and is preferably deposited by means of a physical vapor deposition). In all the embodiments and exemplary embodiments of this application including the drawings, it should be emphasized that the deposition of the second material, even if described in each case only with regard to the (preferably electrolytic) deposition of the second material, can always additionally comprise the preceding method step for forming the growth seed layer.

The second material14a(FIG. 7), which is deposited completely or predominantly electrolytically in accordance withFIGS. 6 and 7, serves for filling the trench5of the semiconductor product1and closing it. On account of the electrically conductive first layer12deposited previously, the trench wall5aof the trench5is covered in electrically conductive fashion and is coated during the electrolytic deposition with the second material14afrom which the second layer14is formed. In addition, the second material14ais deposited onto the outer area of the semiconductor product1outside the trench5, whereby the second layer14forms there as well.

As illustrated inFIG. 6, when implementing the electrolytic deposition, the semiconductor product1is, for example, connected to a cathode and thereby negatively biased. By way of example, an electrode20composed of copper or composed of some other copper-containing material is used as the anode, which is positively biased. The voltage source formed from anode terminal18and cathode terminal19enables an electrochemical or electrolytic deposition. The copper-containing electrode20connected to the anode terminal18serves as anode and the semiconductor product1connected to the cathode terminal19serves as cathode. The semiconductor product1and the copper-containing electrode20are dipped into a suitable electrolyte, for example, a copper sulphate solution (copper sulphate dissolved in water; CuSO4.H2O in aqueous solution). However, the electrode20and the electrolyte need not contain copper; it is likewise possible for some other material to be deposited electrolytically. On account of the first layer12composed of conductive material12aarranged on the semiconductor substrate2, and if appropriate the second interlayer13composed of likewise conductive material arranged above the first layer, the second material14afor the second layer14is also grown on the front-side surface4of the semiconductor product1including the trench inner wall5a, to be precise at least until the trench5is completely filled. In this case, the second material14agrows onto the bottom and the sidewalls of the inner wall5a(and also onto the surface4of the semiconductor product1outside the trench5). In the exemplary embodiment ofFIGS. 1 to 12, it is possible, for example, for copper or some other material to be grown electrolytically. The width and the depth of the trench decrease during the growth until the trench is completely closed.

In this way, the form of the front-side outer area of the semiconductor product that is illustrated schematically inFIG. 7arises, in which the trench is completely filled with the material14aof the second layer14. The top side of the second layer14runs at a level above the surface4of the original semiconductor product and above the previously deposited layers12or11to13.

In accordance withFIG. 8, the excess material14aof the second layer14is then removed outside the trenchs, to be precise preferably by chemical mechanical polishing in this exemplary embodiment. In this case, a polishing pad30in the presence of a polishing slurry31is moved parallel to the main area of the semiconductor product1in order to remove the second material14afrom the top side of the semiconductor product. A chemical etching by chemical action of the polishing slurry and at the same time a mechanical abrasion by the polishing grains additionally contained in the polishing slurry take place in this case. The polishing slurry can, for example, substantially contain iron nitrate or some other iron-containing etching component. By means of the chemical mechanical polishing, the second layer14is removed relative to a layer lying under it, for example, relative to the first layer12or relative to the second interlayer13.

In this way, for example, a second layer14comprising copper or a copper-containing material can be polished outside the trench5. For this purpose, a first polishing step I can be carried out, for example, in which the copper of the second layer14is removed selectively with respect to a tantalum-containing second interlayer13.

Afterwards, as illustrated inFIG. 9, a second polishing step II can optionally be provided, by means of which an optional second, for example, tantalum-containing, interlayer13, which also served as an etching stop or polishing stop during the first polishing step I in the course of polishing the second layer14, is removed selectively with respect to the first layer12. The implementation of the second polishing step II can be carried out with the aid of a different polishing slurry32from the polishing slurry31of the first polishing step I.

FIG. 9shows that the result of the second polishing step II with the aid of the polishing slurry32or, if the second interlayer13was not deposited and only the second layer14was polished later, the first layer12is uncovered after carrying out the polishing operation. A trench filling40composed of the second material14aremains within the trench5and closes the trench. Outside the trench, by contrast, the first layer12(for example, composed of tungsten) is at least uncovered. In the context of this application, the formulation that the first layer12is “at least uncovered” means, in particular, that in regions outside trenches5(of which only one trench is illustrated by way of example in the figures), the first layer12is uncovered over the whole area or, if the first layer12has already been etched through or polished through in places, a layer arranged underneath it is uncovered. No material of a second interlayer13or of the second layer14should be situated on the first layer12if the latter has been uncovered at least outside the trench5, not even in places. Consequently, the chemical mechanical polishing (including an “overpolishing”) should be continued until, on the entire wafer surface, the first layer12or at most in places a layer arranged underneath it is uncovered at the top side of the semiconductor product that has been subjected to chemical mechanical polishing.

In the exemplary embodiment described up to this point, a relatively thick layer14composed of, for example, copper or a copper-containing second material14aserving for filling the trench5was firstly deposited onto the semiconductor product (namely onto the layer12or13) and subsequently removed again at a level above the trench5by chemical mechanical polishing. Depending on the magnitude of the layer thickness and depending on the choice of materials for the polishing slurry and the second layer14, under certain circumstances a relatively long time duration of several minutes may be required for polishing in order to completely remove the second layer14at a level above the trench. On account of predetermined boundary conditions in the production of integrated semiconductor circuits, depending on the application polishing durations of 1000 seconds or more may arise, which are required in order that, for example, a copper layer14deposited electrolytically above a tungsten layer12is removed completely outside trenches5.

Given such long polishing times, unevennesses can arise on account of the polishing operation and are transferred during the further processing of the semiconductor substrate and impede the process windows for subsequent production steps, for example, in particular for lithographic patternings with limited depth of focus. Therefore, it is desirable to re-establish the initially very planar surface of the semiconductor product also after the deposition of the layers12,14and the subsequent elimination thereof outside the trenches. However, the top side, illustrated inFIG. 9, of the first layer12, which is uncovered after the chemical mechanical polishing of the second layer14(and if appropriate of a second interlayer13), will quite generally have unevennesses on account of the long polishing times, that unevennesses cannot be eliminated even by further polishing of the first layer12(and if appropriate a first interlayer11). Therefore, in the course of removing layers which were deposited in trenches5, topographies arise on the surface of the semiconductor product or in the topmost layer (the layer12inFIG. 9) arranged thereon, which topographies cannot readily be eliminated by conventional methods.

The materials specified here for the layers11,12,13and14are moreover mentioned merely by way of example; it goes without saying that other materials can likewise be used. Furthermore, in particular, one or both interlayers11,13can be obviated. If need be the first and the second layer12,14are provided for the method according to an embodiment of the invention, the second layer14typically having after deposition a layer thickness that is significantly greater than the layer thickness of the first layer12. By way of example, the layer thickness d2of the first layer12can be between 50 and 200 nm, for example 80 to 100 nm, whereas the layer thickness d4of the second layer14on the uncovered surface of the semiconductor product outside the trenches5can be, for example, between 3 and 10 μm. The polishing times required for polishing back to the second material14aare correspondingly long, particularly when the material that is actually best suited with regard to a highest possible polishing rate cannot be used owing to other boundary conditions in the production of integrated circuits and a polishing slurry having a lower polishing rate has to be used instead. In particular copper or a material that principally comprises copper is suitable as material14afor the trench filling of the trenches5that is to be formed with the aid of the second layer14. These materials can be used in particular to produce contact hole fillings serving as vias. It is likewise possible to produce interconnects above a substrate surface or electrical substrate contacts which reach either as far as the surface or right into the interior of the substrate or even as far as the rear side of the substrate. With the aid of trench fillings of trenches5which pass through the entire layer thickness of the substrate2, it is possible, for example, to produce rear-side contact-connections, that is to say contact-connections of electrical components on the substrate front side from its rear side. In this way, it is possible to produce thermal contacts serving for heat dissipation, or else electrical contacts, in particular substrate contacts or substrate rear-side contacts. It is likewise possible for trenches to be produced and filled with trench fillings which are required when a plurality of semiconductor substrates are stacked one on top of another, for the electrical contact-connection and driving of all the semiconductor substrates involved. Moreover, the substrates which are provided with trenches and trench fillings to be introduced therein can also subsequently be thinned from the rear side and, after thinning, such a trench filling can extend as far as the then uncovered substrate rear side (or else then also end in the interior of the thinned substrate).

Copper, which was mentioned above as a possible material for the second layer14, is suitable for forming any desired electrical connections such as contacts, interconnects, etc., owing to its high conductivity and integration capability. Tungsten as a material or at least a main material for the first layer12, by contrast, is suitable as a diffusion barrier preventing copper from diffusing into the silicon.

The second interlayer13can likewise be used as a diffusion barrier layer for avoiding copper diffusion and is preferably likewise electrically conductive. It can be formed in particular from tantalum and/or tantalum nitride. The first interlayer11, which can optionally be formed between the substrate2and the first layer12, can comprise, in particular, a titanium layer; this serves, in particular, for enhancing the adhesion and/or the electrical contact of the second layer12with the substrate material (for example, of tungsten on silicon); the first interlayer11is preferably likewise electrically conductive and preferably likewise comprises a diffusion barrier that prevents in particular the material of the first layer12(in particular tungsten) from diffusing into the substrate material (for example, silicon). In particular, the first interlayer is intended to prevent a chemical reaction of tungsten with the substrate material (for instance with silicon, whereby tungsten silicide would arise). For this purpose, the first interlayer can comprise a titanium nitride layer, which prevents the siliciding of tungsten also during later heat treatment steps.

The materials specified here by way of example are suitable in particular in order to completely fill trenches having a high aspect ratio without voids arising. At the same time, the layer materials used can be removed again from the surface of the semiconductor product without topographies caused by polishing steps remaining. This will be explained in more detail with reference to the further figures.

As specified above, in accordance withFIG. 8, the material14aof the second layer14is removed from the top side of the semiconductor product1covered with the layers12or11to13. In this case, the chemical mechanical polishing can be carried out until, over the whole area on the semiconductor substrate (at least outside the trenches5), at least the first layer12is uncovered (or, without being a significant disadvantage for the invention, if appropriate etched through in places). However, after the chemical mechanical polishing at the uncovered top side of the semiconductor product, the first layer12(or otherwise in places an underlying layer11,3,13or the substrate2) should be uncovered.

The operation used previously for polishing the second layer14can comprise a first polishing step I, as illustrated inFIG. 8, in which, with the aid of a first polishing pad30and a first polishing slurry31, the material14aof the second layer14is completely removed above the trenches5. In this case, the second interlayer13can serve as an etching stop or polishing stop, the material of the second interlayer can be selected according to its suitability as an etching stop or polishing stop. In particular tantalum and tantalum nitride can be used here. In particular a polishing slurry containing iron, for instance a polishing slurry containing iron nitrate or based on iron nitrate, can be used as polishing slurry31for the removal of the second layer14. When a polishing slurry based on iron nitrate is used, the second interlayer13serves in particular for providing a whole-area polishing stop that prevents a situation where in places during polishing in the presence of polishing slurry containing iron nitrate, the underlying tungsten (or material used otherwise) with respect to the first layer12is already uncovered; in such a case, an electrochemical element would form between the materials of the first and second layers12,14, which could possibly result in superficial corrosion and detachment of the (if appropriate copper-containing) filling from the trench wall. The polishing operation carried out for uncovering the first layer12can furthermore comprise a second polishing step, which is carried out using a different polishing pad30and in the presence of a different, second polishing slurry32, as illustrated inFIG. 9. Preferably, a polishing slurry based on hydrogen peroxide, which, if appropriate, also contains ammonia as an additive in dissolved form, is used in this case. (The concentration of hydrogen peroxide and, if appropriate, also ammonia in polishing slurries used in the course of one of the methods according to embodiments of the invention for etching the layers composed of titanium, titanium nitride, tungsten, tantalum or tantalum nitride is, however, significantly lower than in an etching solution which is used for wet etching and by means of which in particular residues of the first layer12are removed.) By means of the second polishing step II, the second interlayer13is removed relative to the first layer12. Over the whole area on the semiconductor wafer wherever no trench fillings of trenches5composed of the material of the second layer14are provided, the first layer12is uncovered at the latest by means of the second polishing step II. In accordance with certain topographies that arose as a result of the polishing of the second layer14and an overpolishing required as a result, generally everywhere a certain proportion of the first layer12will be removed and under that a residue of the first material12a, from which the first layer12is formed, will remain. In places the first layer12can even also be polished through if the topographies are very large. In any case, however, by means of the chemical mechanical polishing (at the latest after the second polishing step II), the material of the first layer12will largely form the top side of the semiconductor product1that has been processed up to that point. On account of the topographies, however, which was required on account of the complete polishing of the second layer14having a larger layer thickness d4, unevennesses, that is to say topographies within the layer thickness of the then uncovered first layer12, will generally have arisen. Therefore, the top side of the semiconductor product1is no longer planar. If the remaining layers12and, if appropriate,11were then removed merely by further continuation of the polishing operation, the unevennesses would merely be transferred into the next deeper layer, for example, a dielectric layer3, or into a substrate2itself. The process window for subsequent processing steps, in particular those with lithographic patterning, would thereby be reduced. This is prevented, however, by the further measures explained with reference to the subsequent figures.FIG. 9shows, moreover, on the underside of the semiconductor product1, that the trench5reaches as far as the opposite main area and thus enables through-plating of the semiconductor product1. All the embodiments can be embodied with through-plating trenches or trenches that pass through only a portion of the layer thickness of the semiconductor product (or of the substrate or of a layer arranged thereabove).

The removal of the second interlayer13by means of a second polishing step II as illustrated in accordance withFIG. 9can be carried out, for example, with the aid of a polishing slurry32containing hydrogen peroxide and optionally also additionally ammonia. It is also possible to use any other polishing slurry, preferably based on hydrogen peroxide. Although the surface of the uncovered first layer12is illustrated as planar inFIG. 9, unevennesses may have arisen as a result of the polishing of the first layer12(in particular in the case of a first layer12containing tungsten or formed from tungsten) in the surface of the semiconductor product then present, since generally sufficiently uniform planarization is no longer possible owing to the lengthy polishing process for removing the first layer12. Thus, by way of example, a polishing duration of approximately 1000 seconds may be required for removing a first layer12formed from tungsten (by means of chemical mechanical polishing), whereas a second layer14formed from copper, for example, is already polished through in 90 seconds and a tantalum-containing second interlayer13is already polished through after 150 seconds.

Consequently, the vertical position of the top side of the semiconductor product1that has been processed up to that point varies over the entire wafer area; that residue of the first material12aof the first layer12has a residual layer thickness that can vary greatly over the wafer surface. In places the first layer12can also be completely polished through and an underlying layer11or3can already be uncovered, depending on the extent of the unevennesses that arose as a result of the polishing of the second layer14.

According to an embodiment of the invention, the residue of the first material12aof the first layer12is then removed by means of a wet etching, as illustrated inFIG. 10. The wet etching is effected, for example, with the aid of hydrogen peroxide, or otherwise with any desired etching solution65that removes residual material12aof the first layer12, to be precise preferably selectively with respect to an underlying layer such as, for example, the first interlayer12or the dielectric layer3(composed of, for example, BPSG; borophosphorus silicate glass). The etching solution used for the wet etching of the first layer12can contain in addition to hydrogen peroxide also additionally ammonia in dissolved form. Preferably, the wet etching is carried out selectively with respect to the first interlayer11or, if a first interlayer11is not present, selectively with respect to the material at the surface4of the semiconductor product1. Unevennesses that are still present up to that point and are manifested by a layer thickness of the residual material of the first layer12that varies over the substrate area are eliminated as a result; after the selective removal of the first material12a, the top side of the first interlayer11or, if a first interlayer11was not present, the surface4of the semiconductor product1is uncovered again; topographies and unevennesses still present previously have been eliminated by the wet etching of the residual material of the first layer12.

At most the trench fillings40formed from the material of the second layer14acan project slightly above the surrounding top side of the semiconductor product. They can be superficially attacked and oxidized by the wet etching. In particular it is possible, though this is not depicted in the illustration inFIG. 10, for the uncovered surface of the trench filling40to be superficially oxidized by the etching solution65used during the wet etching. By way of example, the surface of a trench filling40formed from copper Cu can be superficially oxidized if the etching solution65contains hydrogen peroxide (and, if appropriate, additionally ammonia). Without additional mechanical action such as during chemical mechanical polishing, this oxide layer is retained on the trench filling40. However, this can be concomitantly removed in a subsequent polishing step for removing the first interlayer since, in the case of a polishing slurry formed from hydrogen peroxide and ammonia, for example, an external copper oxide layer is eroded as soon as the chemical action is supported by mechanical abrasion on account of the polishing pad.

In accordance withFIG. 11, finally, the first interlayer11is removed from the surface4of the semiconductor product1, to be precise preferably by means of a further polishing step III of the chemical mechanical polishing CMP. This involves using a further or identical polishing pad30in the presence of a further polishing slurry33. In the same way as the polishing slurry32of the second polishing step II or the etching solution65of the wet etching, the polishing slurry33can contain hydrogen peroxide and, if appropriate, additionally ammonia in dissolved form. In this case, not only is the first interlayer removed selectively with respect to the dielectric layer3, but an oxide layer (in particular copper oxide) formed superficially on the top side of the trench filling40is also removed by the additional mechanical action. Afterwards, the substrate surface4which is highly planar as before and is practically free of topographies is uncovered again, which enables a further rework of the semiconductor product with a large process window for subsequent processing steps. Consequently, all the topographies that arose as a result of polishing processes for removing the layers11to14have been eliminated again.

With the aid of the optionally provided second and third polishing steps, in particular tantalum-containing interlayers13and titanium-containing interlayers11can be removed selectively with respect to the respectively underlying layer. During the wet etching, the same solution can be used for the etching solution65as was already previously used during the second polishing step for removing the second interlayer13(although without polishing grains or at least without mechanical action); the purely chemical etching without mechanical abrasion eliminates residual first material12aof the first layer12independently of its local layer thickness.

For test purposes, a further layer sequence can be deposited on the semiconductor product1thus treated in accordance withFIG. 11, in order to perform further measurements. Thus, by way of example, in accordance withFIG. 12, firstly a first measurement layer66composed of silicon nitride, for example, can be deposited onto the uncovered surface4of the semiconductor product1. The first measurement layer66can have, for example, a layer thickness of about 100 to about 300 nm. A second test layer67, for example, composed of silicon oxide, can be deposited onto the first measurement layer66. The second test layer67can have, for instance, a layer thickness of about 2 to about 3 μm. These indications are by way of example, of course. The first measurement layer66composed of silicon nitride can be provided, for example, in order to prevent copper from diffusing into the second test layer67. The processing steps and subsequent layer thickness measurements or height measurements performed for test purposes can be carried out both on a wafer provided for production and on a dedicated test wafer. Likewise, on a single wafer, it is possible to provide circuits which are provided for a semiconductor chip to be produced, and additionally test structures which serve for height measurement and thus for checking the planarity of the wafer. The test structures can be provided in particular in the sawing frame, the so-called “kerf”.

FIG. 13summarizes a plurality of height measurements at different test structures that were performed for test purposes. InFIG. 13A(left-hand half ofFIG. 13), results of in each case nine individual height measurements are plotted for three different measurement points a, b, c. An absolute height measured in nanometers is specified in each case. In the case of the measurement point a, the layer thickness of the second test layer67was measured over a test structure, to be precise over a plate-type structure formed in a similar manner to the drain contact layer56inFIG. 5. In accordance withFIG. 13A, measured values that lie very close to one another in the region of 2500 nm are produced. In comparison with this,FIG. 13Bshows for the measurement point a that the measured values have a greater variation relative to one another (from approximately about 2100 to about 2400 nm) if they are measured at a second test layer67on a semiconductor product processed by a conventional method. The greater variation of the measured values is a consequence of the elimination of the layers used for filling the trenches5, the elimination being performed solely by means of chemical mechanical polishing; topographies that arose as a result of the long polishing times therefore affect subsequently deposited layers like the second test layer67.

For the measurement point b, too, the comparison betweenFIGS. 13A and 13Bshows that the variation of the measured values is smaller in the case of the method according to an embodiment of the invention in accordance withFIG. 13A. The measurement point b was based on a layer thickness measurement (performed for instance by means of an optical ellipsometry) of the dielectric layer3(preferably composed of BPSG), to be precise once again over the “plate bottom” of a structure formed in a similar manner to the drain contact layer56illustrated inFIG. 5. However, measurement was effected at a drain contact layer56arranged in the sawing frame in a respective test structure, i.e., outside the respective circuits for the semiconductor chips that are actually to be produced. Nine such test structures with a structure formed in an identical manner to the drain contact layer56were brought together for the measurements as measurement point b.

Finally, the measurement point c was based on a layer thickness measurement likewise of the dielectric layer3(BPSG), but over the “plate edge” of a structure formed in a similar manner to the drain contact layer56illustrated inFIG. 5. For the measurement point c, too, the comparison ofFIGS. 13A and 13Breveal a smaller variation of the measured values in the case of the method according to the invention, i.e., inFIG. 13A.

Finally,FIG. 14shows, for various selected test wafers w1, w2, w3, w4, the results of layer thickness measurements, which were obtained at a semiconductor product reworked by the method according to an embodiment of the invention after the two measurement layers66,67have been formed. The measurement points a to c correspond to the measurement points a to c inFIG. 13. In the case of four measured test wafers w1, w2, w3, w4, the average value of the measurements for the measurement point a varies with mainly small variation around a height H of approximately 2500 nm. Only small variations around the average height values of approximately 1700 nm and 1350 nm likewise result for the measurement points b and c, respectively, which reflects the high planarity of the semiconductor product processed by the method according to the invention. Consequently, with the aid of the method according to an embodiment of the invention, the layers deposited on account of the filling of trenches can be removed from the surface of a semiconductor product without topographies remaining which were caused by the polishing processes used.

FIGS. 15 to 20show a further exemplary embodiment of a method according to an embodiment of the invention.

In accordance withFIG. 15, a trench5is etched into the surface24of a semiconductor product1having a substrate2and a dielectric layer23above the substrate2. The trench need not reach right into the substrate or as far as the substrate surface of the substrate2, but rather can end within the layer thickness of the dielectric layer23. The trench can serve, for example, for producing interconnects and/or contact hole fillings in accordance with a (dual) Damascene technique.

In accordance withFIG. 16, at least one first layer12is deposited, which is preferably electrically conductive. The first layer12comprises a first material12a, but can also comprise a layer sequence. By way of example, further layers, for instance interlayers such as the interlayers11and13of the exemplary embodiment ofFIGS. 1 to 12, can be deposited before and/or after the deposition of the first layer12, where the deposition techniques described there can in each case be used (in the same way as for the first layer12itself). The first layer covers both the trench wall and the surface24of the semiconductor product1outside the trench5.

In accordance withFIG. 17, a second material14ais then deposited, whereby a second layer14is formed on the first layer12and the trench5is filled with the second material14a. The second material is preferably (but not necessarily) deposited electrolytically. The second material can preferably predominantly contain copper.

In accordance withFIG. 18, the second material14ais etched back as far as the top side of the first layer12outside the trench5. The etching back can be carried out by chemical mechanical polishing (CMP) with the aid of a polishing pad30and a polishing slurry, which is merely indicated inFIG. 18. The entire polishing operation and also the materials used for the polishing slurry can be chosen, for example, as in the exemplary embodiment ofFIGS. 1 to 12. As an alternative, however, it is also possible to choose other types of etching back. The etching back can also comprise a plurality of steps, wherein, for example, one of the plurality of etching-back steps is a polishing operation.

As a result of the etching back of the second material14a, the second material14aremains only in trenches5, only a single one of which is illustrated inFIGS. 15 to 20for the sake of clarity. This results in separate, preferably conductive structures which can be formed as interconnects and/or as via contact hole fillings.FIG. 18shows the exemplary embodiment of a trench filling40composed of the second material14aand formed as an interconnect70, whereasFIG. 19shows an alternative exemplary embodiment with a trench filling40formed as a via, i.e. as a contact hole filling75. Therefore, inFIG. 19, the contact hole reaches as far as the top side of the substrate. All ofFIGS. 15 to 20relate to both of these embodiments.

FIG. 19illustrates unevennesses of the top side of the first layer12after the etching back of the second layer14, in order to illustrate the topographies which can arise in particular after carrying out a relatively lengthy previous polishing process. Of the original layer thickness d2of the first layer12(FIG. 16), there remains after the etching back of the second layer14(which etching back can include a certain overetching into the first layer12, but at least uncovers the first layer outside the trenches5at least) a remaining portion d1of the original layer thickness d2of the first layer. The remaining portion d1of the layer thickness can vary over the area of a substrate, in particular of a wafer. The resultant height fluctuation of the top side of the uncovered first layer12is illustrated inFIG. 19within local structure dimensions, wherein the layer thickness fluctuations are depicted with an exaggerated size for the sake of clarity. The resultant topographies cannot simply be removed by a (further) polishing operation, but rather would thereby be transferred into the underlying layer23.

In accordance withFIG. 20, however, the residual material12aof the first layer12is removed by means of a wet-chemical etching. As a result, all the residual material12aof the first layer12is removed, independently of its layer thickness that is still present and varies over the wafer surface, to be precise preferably selectively with respect to a layer arranged underneath, for instance the dielectric layer23. In this way, further processing steps including lithographic patternings can be performed above the interconnect level L without the process window being reduced on account of the topography that has arisen in the meantime during the removal of the second and first layers14,12.

FIGS. 21,22and23show a development of the methods according to an embodiment of the invention with regard to the deposition of the second layer.FIGS. 21 and 22are directed in particular towards the step of forming the second layer14, the end result of which is illustrated inFIGS. 5 and 7, in which a layer14is arranged on an underlying layer, for instance the second interlayer13. The deposition of the second material can comprise, in addition to a deposition of the main amount of the second material14a, preferably by means of an electrolytic deposition, additionally a preceding step of forming a growth seed layer15. Such a growth seed layer15serves for attaching individual growth seeds15on the surface of the underlying layer, on which the second material can then grow more reliably and at a higher deposition rate. The growth seed layer is illustrated with an exaggerated size inFIG. 21; in practice it need be only a few atomic layers thick. As illustrated inFIG. 21, it can also comprise isolated growth seeds that are not yet interlinked. Likewise, the growth seed layer can be a layer which, although it is already interlinked overall, is still perforated. It goes without saying that an uninterrupted, continuous growth seed layer is at least likewise suitable for accelerating the subsequent, preferably electrolytic growth of the second material14a. The growth seed layer is preferably formed by a physical vapor deposition. Any other deposition methods can be used as an alternative. In accordance withFIG. 21, on account of the physical vapor deposition, growth seeds of the growth seed layer15form on the top side of the second interlayer13of the semifinished semiconductor product fromFIG. 4. The seeds form on the top side both within the trench and outside the trench. The seeds preferably, but not necessarily, comprise the second material14a, that is to say the material of the subsequently deposited second layer14.

In accordance withFIG. 22, the second material14ais subsequently deposited, for instance by means of the electrolytic deposition in accordance withFIG. 6. It is preferably deposited up to a layer thickness sufficient to completely fill the remainder of the trench volume. The second layer14is formed as a result. If the growth seed layer15is formed from the same material as the second layer14, a layer boundary is no longer discernible between the layers14and15after the deposition of the second layer14. Consequently, the second layer14then comprises the growth seed layer15. Therefore, the growth seed layer15is no longer illustrated separately inFIGS. 5 and 7and in the further figures.

FIG. 23shows the corresponding development with regard to the additional deposition of the growth seed layer15, but on the basis of the exemplary embodiment ofFIGS. 15 to 20. A growth seed layer15is then optionally deposited onto the surface of the first layer12of the semifinished semiconductor product fromFIG. 16in a manner corresponding to the exemplary embodiments described above with reference toFIGS. 21 and 22. In particular, here as well a growth seed layer composed of the second material14acan again be deposited. In all ofFIGS. 21 to 23, the growth seed layer, in the same way as the second layer14itself, can comprise a copper-containing material, for example, copper. Furthermore, a physical vapor deposition is preferably chosen for depositing the growth seed layer15.

The above-described exemplary embodiments ofFIGS. 1 to 12,15to20and ofFIGS. 21,22and23are mentioned merely by way of example; all of the individual steps and individual features of the exemplary embodiments and also of those exemplary embodiments of the patent claims can be combined with one another. Furthermore, further modifications emerge, moreover, upon application of the knowledge and abilities of a person skilled in the art.