Integrated fan-out wafer architecture and test method

A fan-out wafer comprises a first IC die having at least a first boundary scan cell (BSC) and a second BSC. The first BSC is coupled to a first demultiplexer. The second BSC is coupled to a first pad. A second IC die has at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad. A first master path connects the first demultiplexer to the second demultiplexer. A first slave path connects the first demultiplexer to the second demultiplexer. The first pad and second pad are located between the first master path and the first slave path.

FIELD

This disclosure relates to semiconductor fabrication generally, and more specifically to an architecture and test method for an integrated fan-out (InFO) wafer.

BACKGROUND

In an Integrated fan-out (InFO) wafer, a plurality of dies are embedded in a material (such as molding compound), at two or more locations horizontally or vertically separated from each other. Interconnects between dies are formed in one or more redistribution layers (RDL) above the dies. Using this technology, copper interconnects formed after the exposure of on-chip aluminum pads, known as post-passivation interconnects (PPI), allow signals to fan out to regions larger than the silicon die footprint. I/O's can be redistributed to the fan-out region outside of the silicon die footprint for increased pin count at the package or wafer level. Passive devices such as inductors and capacitors can be formed over the molding compound for lower substrate signal loss and higher electrical performance. A smaller form factor leads to better thermal behavior and hence a lower operating temperature for the same power budget, or alternatively, faster circuit operation for the same temperature profile.

DETAILED DESCRIPTION

This disclosure provides an effective and efficient test and repair method for InFO wafer level chip scale package technology. The method can be used for verification before mass production.

InFO technology introduces a variety of technical challenges, including RDL line width as fine as 2 um, RDL line pitch as fine as 4 um, small pads (e.g., 30 um×30 um) to connect RDL lines, TIV (Thru InFO Via) having a cross section 250 um×250 um, and TIV pitch: 400 um. These dimensions are expected to shrink with future technology nodes.

FIG. 1is a cross sectional view of an InFO wafer100. The InFO wafer100has a plurality of integrated circuit (IC) dies110,150. Dies110and150do not need to be fabricated using the same technology as either other, and need not have same function. Dies110and150can include any combination of logic, high speed, RF or memory circuits, for example. AlthoughFIG. 1only shows two dies, the InFO wafer100can include any number of dies, and the structures and techniques described herein can also be used for interconnects among any number of additional dies.

The dies110,150are embedded in a fan-out material104such as a molding compound. A plurality of through-InFO-vias (TIV)103provide connections between conductors on the top surface of the dies110,150and the back surface of the dies. During fabrication, the dies can be mounted on a carrier substrate101, which can be glass, for example. Subsequently, the carrier101can be removed and another device (e.g., a memory die) can be mounted to the fan-out wafer100.

At least one redistribution layer (RDL)106is formed above the dies110,150. In some embodiments, a plurality of RDL layers are included. Interconnections102between dies are formed in the RDL layers. These interconnections102are discussed further below. Additionally, the RDL layers can be used to increase the pitch between adjacent I/O pins of the final package. A plurality of solder bumps or balls105are provided for connecting to a package substrate or printed circuit board.

One or more RDL interconnections102can fail due to process variations. This disclosure provides a test and repair architecture and method for InFO cross die interconnects, which allows dies110and150to communicate normally even if there is a failure. Some embodiments of this architecture provide both quality checks and a redundant path design for yield improvement.

In some embodiments, a staggered pad array design minimizes area overhead and pad pitch. Each primary routing path (referred to herein as the “master” path), such as RDL interconnect paths between dies, has a corresponding redundant path (referred to herein as the “slave” path). To provide robust repair capability, in some embodiments, the slave paths are designed to be distant from the corresponding master path to reduce the chance of both the master path and slave path failing at the same time. For example, a short circuit due to a contamination particle contacting the master path and another line adjacent to the master path will not also short out the slave path corresponding to that master path.

FIG. 2is a schematic plan view of the InFO wafer100ofFIG. 1. The example ofFIG. 2has10interconnections between IC die110and IC die150. To permit boundary scan testing according to the JTAG IEEE 1149 protocol, each die has a respective boundary scan cell (BSC) for each respective interconnection. Thus, die110has BSC111-120, and die150has BSC151-160. One of the dies (in this example, die150) has an 1149.1 TAP controller180with five serial terminals TDI, TCK, TRST, TDO and TMS for inputting data to the BSC151-160of die150and receiving data from the BSC111-120of die110. BSC111-120are connected to each other in series, and BSC151-160are connected to each other in series. Each BSC has storage elements, such as registers, flip-flops, or the like (not shown). Thus, data can be input serially through the TDI terminal to BSC151and shifted in subsequent cycles through each of BSC152-160. Similarly, data can be shifted from BSC120through each of BSC119-111. Each die has a plurality of probe pads (Mi, Si, Mi′ and Si′), referred to below as “pads” for brevity.

InFIG. 2, the “master paths” proceed from a master pad to a corresponding slave pad. For example a master path from demultiplexer121to demultiplexer156proceeds from master pad M1to slave pad S1′. The “slave paths” proceed from a slave pad to a corresponding master pad. For example, a slave path from demultiplexer121to demultiplexer156proceeds from slave pad S1to slave pad M1′.

For ease of reference, the interconnecting paths between pads inFIG. 2are referred to herein by the IDs of the connected pads. Thus the path from pad M1to pad S1′ is referred to as master path M1-S1′. The remaining master paths are referred to as M2-S2′, M3-S3-, M4-S4′, M5-S5′, M6-S6′, M7-S7′, M8-S8′, M9-S9′ and M10-S10′. Similarly, the corresponding slave paths are referred to as S1-M1′, S2-M2′, S3-M3′, S4-M4′, S5-M5′, S6-M6′, S7-M7′, S8-M8′, S9-M9′, and S10-M10′. The connecting paths can be implemented in a plurality of redistribution layers.

A path connecting BSC160to BSC120is provided by way of demultiplexer D5170, pad M5′, pad S5, and demultiplexer131. From BSC111, the data can be output to the TDO terminal of the controller180by way of a master path including demultiplexer D1121, pad M1, pad S1′, and demultiplexer171.

Each BSC111-120can transmit data to, or receive data from, a respective demultiplexer121-130. Each BSC151-160can transmit data to, or receive data from, a respective demultiplexer161-170. Each demultiplexer121-130,161-170has a control input from the demultiplexer controller182for selecting either a master path having a line connected to a respective master pad M1-M10, M1′-M10′, or a slave path having a line connected to a respective slave pad S1-S10, S1′-S10′. The BSC can be used to test the interconnections between dies in the RDL layers, and to diagnose any failures.

FIG. 2shows an example of the master and slave paths between a single BSC111on die110and a single BSC156on die150. InFIG. 2, for ease of example, this single master path/slave path pair is highlighted. To transmit data from BSC111to BSC156, demultiplexers D1121and D1166can be switched to the primary (master) path, including master pad M1, slave pad S1′, and demultiplexer171. Alternatively, to transmit data from BSC111to BSC156, demultiplexers D1121and D1166can be switched to the slave path, including slave pad S1and master pad M1′. The interconnect lines of the master and slave paths are distant from each other. In some embodiments, the interconnect lines of the master and slave paths are separated from each other by at least one pair of pads (e.g., S6-M6′, M2-S2′, S7-M7′, M3-S3′, S8-M8′, M4-S4′, S9-M9′, M5-S5′, S10-M10′, or S1-M1′) and the interconnect line connecting that pair of pads.

For example, as shown inFIG. 2, in some embodiments, a fan-out wafer100comprises a first IC die110having at least a first boundary scan cell (BSC)111and a second BSC112. The first BSC111is coupled to a first demultiplexer D1121. The second BSC112is coupled to a first pad M2. A second IC die150has at least a third BSC156coupled to a second demultiplexer D1166, and a second pad S2′ connected to the first pad M2. A first master path M1-S1′ connects the first demultiplexer D1121to the second demultiplexer D1166. A first slave path S1-M1′ connects the first demultiplexer D1121to the second demultiplexer D1166. The first pad M2and second pad S2′ (and their connecting path M2-S2′) are located between the first master path and the first slave path. In this example, several additional pairs of pads, along with their interconnecting paths, are interposed between the primary path M1-S1′ and the redundant path S1-M1′. In other embodiments any positive integer number of pad pairs (and their interconnecting path) can be positioned between the master path (e.g., M1-S1′) and the slave path (e.g., S1-M1′) for any given pair of BSC (e.g.,111,156).

Each first demultiplexer121-130is configurable to select a respective one of the first master path or the first slave path for transmission of a signal from the respective first BSC111-120to the respective third BSC151-160. For example, demultiplexer122is configurable to select master path M2-S2′ or the slave path S2-M2′ for transmission of a signal from the BSC112to the BSC157. Demultiplexer123is configurable to select master path M3-S3′ or slave path S3-M3′ for transmission of a signal from BSC113to BSC158. Demultiplexer124is configurable to select master path M4-S4′ or slave path S4-M4′ for transmission of a signal from BSC114to BSC159. Demultiplexer125is configurable to select master path M5-S5′ or slave path S5-M5′ for transmission of a signal from BSC115to BSC160. Demultiplexer126is configurable to select master path M6-S6′ or slave path S6-M6′ for transmission of a signal from BSC116to BSC151. Demultiplexer127is configurable to select master path M7-S7′ or slave path S7-M7′ for transmission of a signal from BSC117to BSC152. Demultiplexer128is configurable to select master path M8-S8′ or slave path S8-M8′ for transmission of a signal from BSC118to BSC153. Demultiplexer129is configurable to select master path M9-S9′ or slave path S9-M9′ for transmission of a signal from BSC119to BSC154. Demultiplexer130is configurable to select master path M10-S10′ or slave path S10-M10′ for transmission of a signal from BSC120to BSC160. As the demultiplexer controller182switches each first demultiplexer D1121-D10130to the corresponding master or slave path, controller182also switches each second demultiplexer D1161-D10170to the corresponding master or slave path.

Each second demultiplexer161-170on the second die150is configurable to select a respective one of the second master path or the second slave path for transmission of a signal from the respective BSC151-160to the respective third BSC111-120. For example, demultiplexer161is configurable to select master path M1′-S1or the slave path S1′-M1for transmission of a signal from the BSC151to the BSC111. Demultiplexer162is configurable to select master path M2′-S2or the slave path S2′-M2for transmission of a signal from BSC113to BSC158, etc.

In general, each first master path includes a first master pad M1-M10on the first die110connected to a first slave pad S1-S10on the second die150. The first master pad M1-M10and the first slave pad S1-S10are connected between the first demultiplexer121-130and the second demultiplexer156-160,151-155. Each first slave path includes a second slave pad S1-S10on the first die110connected to a second master pad M1′-M10′ on the second die150. The second slave pad S1-S10and the second master pad M1′-M10′ are connected between the first demultiplexer121-130and the second demultiplexer156-160,151-155.

In general, when one of the BSC111-120of die110is transmitting data to its corresponding BSC156-160,151-155, the demultiplexer controller182switches the transmitting demultiplexer121-130to use its primary path Mi-Si′, where i varies from 1 to 10. In general, when one of the BSC151-160of die150is transmitting data to its corresponding BSC116-120,111-115, the demultiplexer controller182switches the transmitting demultiplexer161-170to use its primary path Mi′-Si, where i varies from 1 to 10. Thus, each path includes a master pad on one die and a slave pad on the other die.

As shown inFIG. 2, the master pad M1-M10in the first die110are included in a first row of master pads. The slave pads S1-S10are included in a first row of slave pads on the first die110. The first row of slave pads S1-S10is parallel to the first row of master pads M1-M10Similarly, the master pad M1′-M10′ in the second die110are included in a second row of master pads. The slave pads S1′-S10′ are included in a second row of slave pads on the second die150. The second row of slave pads S1′-S10′ is parallel to the second row of master pads M1′-M10′.

In some embodiments, the master pads and slave pads are staggered. That is, with the row of master pads oriented in the X direction, and the row of slave pads oriented in the same X direction, each slave pad has an X offset XO relative to the nearest master pad. In some embodiments, the offset XO is half the pitch P between adjacent master pads. For example, slave pad S6can be offset in the X direction from master pad M1by one half the pitch P between adjacent master pads M1and M2. In other embodiments, the offset XO can be greater than or less than one half of the pitch P between adjacent master pads. As a result of the offset between the master pads and the slave pads, the distance DP between adjacent master pads (e.g., M1and M2) can be smaller than the width of the nearest slave pad M6. Similarly, the distance between adjacent slave pads (e.g., S6and S7) can be smaller than the width of the nearest master pad M2. This adjacent master pads can have an interconnecting line therebetween, and adjacent slave pads can have an interconnecting line therebetween. Adjacent interconnecting lines can have a master pad or a slave pad therebetween. By staggering the row of slave pads relative to the row of master pads, the distance DP between adjacent pads can be reduced, relative to the width W of each pad. The overall length of the row can be reduced.

For example, a first pad M1is included in a plurality of pads arranged in a row of master pads M1-M10. The row includes a pad M2adjacent to the first pad M1. A spacing between a closest pair of respective edges of the first pad M1and the pad M2is smaller than a width W of the first pad M1in an X direction extending from the pad M1to the pad. M2. A first slave pad S1is included in a plurality of pads arranged in a row of master pads S1-S10. The row includes a pad S2adjacent to the first pad S1. A spacing between a closest pair of respective edges of the first pad S1and the pad S2is smaller than a width W of the first pad S1in an X direction extending from the pad S1to the pad. S2.

Thus, as shown inFIG. 2, master pads M1-M10on the die110are connected to the respective slave pads S1′-S10′ on the die150, and master pads M1′-M10′ on the die150are connected to the respective slave pads S1-S10on the die110. This simplifies routing, because each master pad is aligned with a corresponding slave pad on the opposite die. For example, master pad M1on die110is aligned with slave pad S1′ on the die150.

InFIG. 2, the BSC156-160are connectable to BSC111-115, and BSC151-155are connectable to BSC116-120. Thus, the BSC in die150are offset by five positions from the corresponding BSC in die110(and wrap around). In other embodiments, the BSC in die150can be offset by fewer or more than five positions relative to the corresponding BSC in die110, so long as the master path and slave path for each pair of connected demultiplexers are separated from each other by at least one master and/or slave path corresponding to another pair of connected demultiplexers.

FIG. 3shows an example in which the InFO wafer has at least two RDL layers106. In some embodiments, the master paths and slave paths described above are implemented so that the connecting lines between dies110,150are implemented in a first RDL layer, and an additional redundant set of lines are formed in a second RDL layer.

For example, a first redistribution layer RDL-1having a first conductive line M1-S1′ is coupled between a first one of the demultiplexers121on the first IC die110and a first one of the demultiplexers156on the second IC die150, as described above. A second redistribution layer RDL-2has a second conductive line R1-R1′ coupled between the demultiplexer121on the first IC die and demultiplexer156on the second IC die150. In this embodiment, each of the demultiplexers121-130and161-170is capable of switching among three different lines. In other embodiments having four or more alternative paths per BSC pair, each demultiplexer is capable of switching among that same number of paths.

As also shown inFIG. 3, the pads on each die110,150can be arranged in more than three rows. For example, inFIG. 3, in each die, the master pads are arranged in one row, the slave pads are arranged in a second row, and the redundant pads (R1, R2, R1′, R2′) are arranged in a third row. In other embodiments (not shown), the pads one each die can be arranged in more than three rows.

In other embodiments, the master paths for one of the dies are all routed through one RDL conductive line layer, and the slave paths for that die are all routed through another RDL conductive line layer.

FIG. 4is a flow chart of a text method which is performed on the InFO wafer100. For the purpose of the tests described below, any desired sequence of test data can be used. This series of tests can be performed after fabrication of the cross die interconnects in the RDL layer(s)106, and can be performed prior to packaging the InFO wafer100. In other embodiments, the testing and repairing can be performed after packaging.

At step402, a cross die boundary scan cell self test is performed. This test verifies whether data can be shifted through a loop from input terminal TDI through BSC151-160and130-121, and out of output terminal TDO. This loop is highlighted inFIG. 5.

Referring toFIG. 5, in each cycle data from TDI is stored in BSC151, data from BSC151is shifted into BSC152, and so on, till the data in BSC159is shifted into BSC160. The demultiplexer D5170is switched to use the master path M5′-S5. Data in BSC160is transmitted via path M5′-S5to the additional demultiplexer131, which has been switched to output data to BSC120. Data are switched through the BSC120-111. The data in BSC111is provided to demultiplexer D1121, which is configured to send the data via path M1-S1′ to demultiplexer171. Demultiplexer171has been switched to output data to the output terminal TDO.

Referring again toFIG. 4, at step404, the cross die master-to-slave paths from die150to die110are tested. This is shown schematically inFIGS. 6A-6C.

InFIG. 6A, the test data are shifted from the TDI input terminal through the BSC of die150, from BSC151to BSC160. After 10 cycles, each BSC151-160stores a respective test datum, with the first datum in BSC160and the 10th datum in BSC151.

FIG. 6Bis highlighted to show the data flow from each BSC151-160of die150to respective BSC126-130,121-125.

InFIG. 6Cthe data in BSC111-120are shifted out to the output terminal TDO. Demultiplexer D1121in die110is switched to output data through master path M1-S1′ to demultiplexer171. The demultiplexer171is switched to transmit the data to output terminal TDO. The data in the BSC112-120are shifted to the left, until the last data (from BSC120) is shifted out to terminal TDO.

Referring again toFIG. 4, at step406, the cross die slave-to-master paths from die150to die110are tested. This test is shown schematically inFIGS. 6A,7and6C.

First, the input data are shifted into BSC151-160, as described above with respect toFIG. 6A. InFIG. 6A, the test data are shifted from the TDI input terminal through the BSC of die150, from BSC151to BSC160. After 10 cycles, each BSC151-160stores a respective test datum, with the first datum in BSC160and the 10th datum in BSC151.

In this test, the demultiplexers161-170in die150are switched to provide data to the slave paths S6′-M6, S7′-M7, S8′-M8, S9′-M9, S10′-M10, S1′-M1, S2′-M2, S3′-M3, S4′-M4, S5′-M5. The demultiplexers121-130in die110are switched to receive data from their respective master paths M1-S1′, M2-S2′, M3-S3′, M4-S4′, M5-S5′, M6-S6′, M7-S7′, M8-S8′, M9-S9′, M10-S10′. Additionally, the demultiplexer171in die150is switched to receive data from demultiplexer D1166, and provide the data to demultiplexer D1121via path S1′-M1.

FIG. 7is highlighted to show the data flow from each BSC151-160of die150to respective BSC126-130,121-125, by way of the slave paths. At the completion of this step, the data from BSC151-160have been transferred to respective BSC116-120,111-115.

Referring again toFIG. 6C, once the data have been received by the BSC111-120, they are shifted out to the output terminal TDO as described above. Demultiplexer D1121in die110is switched to output data through master path M1-S1′ to demultiplexer171. The demultiplexer171is switched to transmit the data to output terminal TDO. The data in the BSC112-120are shifted to the left, until the last data (from BSC120) is shifted out to terminal TDO.

Referring again toFIG. 4, at step408, if any of the interconnect paths is identified during steps404and/or406as being failed, a repair is initiated.

FIG. 8Ais a flow chart of the repair logic, according to some embodiments. This logic can be implemented in a processor programmed with software, or in special purpose hardware (application specific integrated circuit).FIG. 8Auses the nomenclature ofFIG. 2, in which the master pads on die110are Mi, the slave pads on die110are Si, the master pads on die150are Mi′ and the slave pads on die150are Si′. Paths are denoted by sending pad and receiving pad (e.g., Mi-Si).

At step802, a loop including steps804-818is performed N times, where N is the number of BSC in each node. For example, in the configuration ofFIG. 2, the loop is performed 10 times.

At step806, the demultiplexer controller182is programmed to use the slave path Si-Mi′ instead of the master path Mi-Si′ to send data from die110to die150.

At step810, the demultiplexer controller182is programmed to use the master path Mi-Si′ instead of the slave path Si-Mi′ to send data from die110to die150.

At step814, the demultiplexer controller182is programmed to use the slave path Si′-Mi instead of the master path Mi′-Si.

At step818, the demultiplexer controller182is programmed to use the master path Mi′-Si instead of the slave path Si′-Mi.

FIG. 8Bshows an example of a repair as described above with reference toFIG. 8A. The testing, determines that there is an open circuit between BSC112and BSC157, indicated by the dashed line. The problem is identified as a failure of the master path M2′-S2connecting pads M2′ and S2. Upon execution of the method ofFIG. 8A, at steps812and814, the demultiplexer controller182is programmed to use the slave path S2′-M2instead of the master path M2′-S2. Thereafter, path S2′-M2is used. The repair can be verified by transmitting data through a loop highlighted inFIG. 8B, including input terminal TDI, BSC151-157, demultiplexer D2167, pad S2′, pad M2, demultiplexer D2122, BSC112, BSC111demultiplexer121, pad M1, Pad S1′, demultiplexer171and output terminal TDO.

In some embodiments, a fan-out wafer comprises a first IC die having at least a first boundary scan cell (BSC) and a second BSC. The first BSC is coupled to a first demultiplexer. The second BSC is coupled to a first pad. A second IC die has at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad. A first master path connects the first demultiplexer to the second demultiplexer. A first slave path connects the first demultiplexer to the second demultiplexer. The first pad and second pad are located between the first master path and the first slave path.

In some embodiments, the first demultiplexer is configurable to select one of the first master path or the first slave path for transmission of a signal from the first BSC to the third BSC.

In some embodiments the first pad is included in a plurality of pads arranged in a row, the row including a third pad adjacent to the first pad and a spacing between a closest pair of respective edges of the first pad and the third pad is smaller than a width of the first pad in a direction extending from the first pad to the third pad.

In some embodiments, the first master path includes a first master pad on the first die connected to a first slave pad on the second die, the first master pad and the first slave pad connected between the first demultiplexer and the second demultiplexer; and the first slave path includes a second slave pad on the first die connected to a second master pad on the second die, the second slave pad and the second master pad connected between the first demultiplexer and the second demultiplexer.

In some embodiments, the first master pad is included in a first row of master pads on the first die; the second slave pad is included in a first row of slave pads on the first die; and the first row of slave pads is parallel to the first row of master pads.

In some embodiments, the first row of slave pads is offset from the first row of master pads, in a direction extending parallel to the first row of master pads, by an amount that is approximately half of a pitch between adjacent master pads.

Some embodiments further comprise at least one redistribution layer formed above the first die and above the second die, wherein the first master path and the first slave path each include at least one conductive line in the at least one redistribution layer.

In some embodiments, a fan-out wafer comprises a first IC die having a plurality of boundary scan cells (BSC) and a plurality of demultiplexers, each BSC coupled to a respective one of the demultiplexers, each demultiplexer coupled to a respective master pad on the first die and to a respective slave pad on the first die. A second IC die has a plurality of BSC and a plurality of demultiplexers, each BSC coupled to a respective one of the demultiplexers, each demultiplexer coupled to a respective master pad on the second die and to a respective slave pad on the second die. Each master pad of the first die is connected to a respective slave pad of the second die. Each master pad of the second die is connected to a respective slave pad of the first die. The respective master pad and slave pad corresponding to each respective demultiplexer of the first die are separated from each other by at least one line connected to the master pad or slave pad corresponding to another one of the demultiplexers of the first die.

In some embodiments, each demultiplexer of the first die is configurable to select one of a respective master path including the master pad corresponding to that demultiplexer or a respective slave path including the slave pad corresponding to that demultiplexer, for transmission of a signal from the BSC coupled to that demultiplexer to a BSC on the second die.

In some embodiments, each first master pad on the first die is included in a first row of master pads. Each slave pad on the first die is included in a first row of slave pads. The first row of slave pads is parallel to the first row of master pads.

In some embodiments, each slave pad in the first row of slave pads is offset from a nearest master pad in the first row of master pads, along a length direction of the first row of master pads.

Some embodiments further comprise a respective additional demultiplexer on each of the first and second IC dies, for selectably forming a boundary scan test loop that includes all of the BSC of the first IC die and all of the BSC of the second IC die.

Some embodiments further comprise a first redistribution layer having a first conductive line coupled between a first one of the demultiplexers on the first IC die and a first one of the demultiplexers on the second IC die; and a second redistribution layer having a second conductive line coupled between the first demultiplexer on the first IC die and the first demultiplexer on the second IC die.

In some embodiments, a test method comprises: shifting first data into a first plurality of boundary scan cells (BSC) in a first die of a fan-out wafer; configuring each one of a plurality of demultiplexers to select either a respective master path or a respective slave path for outputting data from a respective one of the plurality of BSC; shifting the first data into a second plurality of BSC in a second die via the selected paths; configuring an additional demultiplexer on each of the first and second dies to form a single loop including the first and second pluralities of BSC; and shifting second data through each BSC in the loop.

In some embodiments, the step of shifting the second data include inputting the second data sequentially into a first terminal in one of the first die or the second die, and outputting the second data sequentially from a second terminal in the same one of the first die or the second die.

In some embodiments, the first plurality of BSC are arranged in a first row. The first row includes a first BSC coupled to the first terminal and a first one of the additional demultiplexers coupled to the second terminal.

In some embodiments, the second plurality of BSC are arranged in a second row. The second row includes a first BSC coupled to the first additional demultiplexer and a last BSC coupled to the second additional demultiplexer.

Some embodiments further comprise detecting that a master path corresponding to one of the first plurality of demultiplexers has failed; and switching that demultiplexer to select the corresponding slave path coupled to that one demultiplexer for outputting data.

In some embodiments, the master path corresponding to the one demultiplexer is on a first redistribution layer, the slave path corresponding to the one demultiplexer is on a second redistribution layer.

Some embodiments further comprise: shifting third data into the second plurality of BSC; configuring each one of a plurality of demultiplexers to select either a respective master path or a respective slave path for outputting data from a respective one of the second plurality of BSC; and shifting the third data into the first plurality of BSC via the selected paths.

The methods and system described herein may be at least partially embodied in the form of computer-implemented processes and apparatus for practicing those processes. The disclosed methods may also be at least partially embodied in the form of tangible, non-transitory machine readable storage media encoded with computer program code. The media may include, for example, RAMs, ROMs, CD-ROMs, DVD-ROMs, BD-ROMs, hard disk drives, flash memories, or any other non-transitory machine-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the method. The methods may also be at least partially embodied in the form of a computer into which computer program code is loaded and/or executed, such that, the computer becomes a special purpose computer for practicing the methods. When implemented on a general-purpose processor, the computer program code segments configure the processor to create specific logic circuits. The methods may alternatively be at least partially embodied in a digital signal processor formed of application specific integrated circuits for performing the methods.