Capacitive level shifter

A level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.

BACKGROUND

Field of the Invention

The invention relates to integrated circuits and more particularly to circuits for converting signals from one voltage domain to another voltage domain.

Description of the Related Art

In general, a level shifter is a circuit that translates signals from one voltage domain to another voltage domain to provide compatibility between integrated circuits having different voltage requirements. For example, a conventional level shifter converts signals of a low power application (e.g., a processor operating with a power supply voltage of 1.8 V) to signals of a high power domain (e.g., analog input/output circuits operating at 2.25 V-5.5 V).

FIG. 1illustrates a circuit diagram of a conventional level shifter. Circuit310of conventional level shifter100includes two low-voltage inverters implemented using low-voltage transistors and powered by low-voltage power supply voltage VDDto drive the gate of high-voltage n-type transistors306and308. High-voltage n-type transistors306and308control cross-coupled high-voltage p-type transistors302and304. A transition of input signal IN from a logic ‘0’ to logic ‘1’ causes the gate of transistor308to transition to approximately low-voltage power supply voltage VDD, causing the gate of transistor302to transition to approximately 0 V and pulling the gate of transistor304to high-voltage power supply voltage VCC, which turns off transistor304. Output signal OUT is an inverted version of the signal on node312. Thus, output signal OUT transitions to approximately high-voltage power supply voltage VCC. That is, a logic ‘1’ signal on input node IN in the first voltage domain (e.g., low-voltage power supply voltage VDD) results in a logic ‘1’ signal on output node OUT in the second voltage domain (e.g., high-voltage power supply voltage VCC). A transition of input signal IN from a logic ‘1’ to logic ‘0’ causes the voltage on the gate of transistor306to transition to approximately low-voltage power supply voltage VDD, causing the voltage on the gate of transistor304to transition to approximately 0 V and in the process, charges the gate of transistor302to approximately high-voltage power supply voltage VCC. Thus, output signal OUT transitions to approximately 0 V.

The propagation delay of conventional level shifter100is relatively slow (e.g., several nanoseconds in a target manufacturing technology) and is asymmetrical. For example, a transition of output signal OUT from logic ‘0’ to logic ‘1’ has a lesser propagation delay than the transition of output signal OUT from logic ‘1’ to logic ‘0.’ Asymmetrical propagation delay results in duty cycle distortion that can degrade performance of a target application. Accordingly, improved techniques for level shifting a signal are desired.

SUMMARY OF EMBODIMENTS OF THE INVENTION

In at least one embodiment of the invention, a capacitive level shifter includes a first power supply node, a second power supply node, a third power supply node, an input node, an output node, and an input circuit coupled between the second power supply node and the third power supply node. The input circuit includes complementary versions of the input node. The level shifter includes a differential amplifier coupled between a differential pair of nodes, the third power supply node, and the complementary versions of the input node. The level shifter includes a load circuit coupled between the first power supply node and the differential pair of nodes. The level shifter includes a capacitor having a first plate and a second plate. The first plate is coupled to a first node of the differential pair of nodes and the second plate is coupled to a second node of the complementary versions of the input node. The level shifter includes an output circuit coupled between the first power supply node and the third power supply node and is configured to generate an output signal on the output node based on a first voltage on the first plate and a second voltage on the second plate.

In at least one embodiment of the invention, a method for level-shifting a received signal from a first voltage domain to a second voltage domain includes establishing a charge across a capacitor based on a logic level of an input signal received by a circuit in the first voltage domain. The method includes maintaining the charge across the capacitor based on the logic level using a second circuit in the second voltage domain. The method includes generating an output signal in the second voltage domain based on the logic level using the charge across the capacitor.

In at least one embodiment of the invention, a level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.

DETAILED DESCRIPTION

A capacitive level shifter that generates a symmetrical output signal with lesser propagation delay than a conventional level shifter is described.FIG. 2illustrates an exemplary circuit diagram of an exemplary, capacitive level shifter consistent with at least one embodiment of the isolator product. Capacitive level shifter208converts input signal IN received from a low voltage domain circuit (e.g., a circuit configured to receive a low-voltage power supply voltage VDDthat is generated by a subregulator) to a high voltage domain circuit (e.g., a circuit configured to receive a high-voltage power supply voltage VCC). Capacitive level shifter208includes flying capacitor410. As referred to herein, a flying capacitor is a capacitor that floats with respect to ground. Both plates of a flying capacitor change potential relative to ground. In at least one embodiment, flying capacitor410is a metal-oxide-metal (MoM) capacitor or a parallel plate capacitor (e.g., metal-insulator-metal (MiM) capacitor or a poly-poly capacitor) and has a capacitance value in the range of 100 femto-Farads (fF) to 1 pico-Farad (pF). Flying capacitor410is the main vehicle for transmitting a logic state from one power domain to another power domain relatively quickly (e.g., in 2 ns or less as compared to 4-20 nanoseconds of a conventional level shifter). However, a flying capacitor may lose its charge over time (e.g., due to leakage currents). Capacitive level shifter208includes a mechanism for maintaining charge on plates of flying capacitor410for indefinitely long logic states to ensure that charge across flying capacitor410is consistent with the logic state of input signal IN. In at least one embodiment, capacitive level shifter208translates input signal IN from the low voltage domain to a standard or high voltage domain with sub-nanosecond propagation delays and low or negligible duty cycle distortion.

In at least one embodiment of capacitive level shifter208, a micro-power circuit maintains charge on flying capacitor410even for indefinitely long logic states. The micro-power circuit includes input buffers402, differential amplifier406, diode-mirrored load404, and clamp408. Input buffers402receive input signal IN using low-voltage transistors configured as inverters in the low voltage domain. Input buffers402includes complementary nodes configured to receive complementary buffered versions of input signal IN. Differential amplifier406includes transistor434, which is a low-voltage transistor, and transistor436, which is a high-voltage native transistor (as indicated by the transistor symbol with the filled, rectangular gate), that are configured as a high-voltage enhancement-like device with relatively low threshold voltage Vtnand sufficient current drive. Similarly, transistor438is a low-voltage transistor and transistor440is a high-voltage native transistor and transistors438and440are configured as a high-voltage enhancement-like device with relatively low threshold voltage Vtnand sufficient current drive. Transistors434and436and transistors438and440form two halves of a differential pair of transistors that are configured to steer tail current into transistors434and436when input signal IN is logic ‘0’ (i.e., has a low voltage, e.g., approximately 0 V) and steer tail current into transistors438and440when input signal IN is logic ‘1’ (i.e., has a high voltage, e.g., approximately VDD). Capacitor444, which in some embodiments is a metal-oxide semiconductor capacitor (e.g., native n-type capacitor) having a value in the range of 50 fF to 200 fF, increases the speed of the current steering from one half of the differential stage406to the other half of differential amplifier406. Unlike a conventional differential pair of transistors, the configuration of the high-voltage native transistor with the low-voltage transistor in each half of differential amplifier406causes the entire current to flow in a branch of differential amplifier406.

Note that transistors428,436, and440are illustrated as being high-voltage native transistors and have a threshold voltage of approximately 0 V, which can be less than 0 V in some corners of the semiconductor manufacturing process. In an exemplary integrated circuit manufacturing process, a native transistor is a type of transistor that is between an enhancement mode transistor (i.e., a transistor that is off at a zero gate-to-source voltage) and a depletion mode transistor (i.e., a transistor that is on at a zero gate-to-source voltage). The native transistor has a threshold voltage of approximately 0 V. The native transistor may be an undoped transistor having a first conductivity type (e.g., n-type) manufactured directly in a substrate having a second conductivity type (e.g., p-type), whereas standard transistors are manufactured in a doped well that is formed in a substrate. The manufacturing process may provide transistors having different breakdown voltages and speeds of operation as a result of gate terminals formed using oxide layers of different thicknesses. An exemplary high-voltage transistor has a thicker gate oxide and therefore has a higher breakdown voltage but is slower than a low-voltage transistor that has a thinner gate oxide thickness.

A native transistor may be manufactured with oxide having a thin-gate oxide thickness (i.e., low-voltage native transistor) or a thick-gate oxide thickness (i.e., high-voltage native transistor). The native transistor is typically larger than a standard transistor (e.g., the native transistor may have a minimum length that is three to six times the minimum length of a standard transistor (high-voltage or low-voltage) having the same oxide thickness), and typically has a lower transconductance than a standard transistor. The low-voltage native transistor and the high-voltage native transistor have threshold voltages with magnitudes less than a threshold voltage of a standard transistor. In general, a native transistor has a threshold voltage of approximately 0 V. The threshold voltage of the low-voltage transistor has a magnitude less than the threshold voltage of a high-voltage transistor. The high-voltage native transistor has a threshold voltage with a magnitude less than a threshold voltage of a high-voltage transistor. In an exemplary integrated circuit manufacturing process, the threshold voltage of the low-voltage transistor is at least 200 mV less than the threshold voltage of the high-voltage transistor (e.g., the threshold voltage of the low-voltage transistor is approximately 350-400 mV and the threshold voltage of the high-voltage transistor is approximately 600-850 mV).

Push-pull circuit412includes transistors424and446, current source448, and capacitor450that generate a gate bias for transistor426. In at least one embodiment, capacitor450is a metal-oxide semiconductor capacitor (e.g., p-type) and transistors424and446, current source448, and capacitor450are designed to maximize the magnitude of the drain-to-source voltage of transistor424while remaining within the reliability limits of transistor424, which is a low-voltage transistor, thus increasing the drive strength of the push-up, high side path of push-pull circuit412.

Push-pull circuit412includes transistors424and426that are cascaded to form a high-side transistor (i.e. a push-up to high-voltage power supply voltage VCC). Transistor426is a high-voltage transistor (as indicated by the unfilled rectangular gate) and transistor424is a low-voltage transistor. Transistors428and430form a cascaded low-side transistor using a high-voltage, native n-type transistor (as indicated by the filled rectangular gate) in series with a low-voltage enhancement mode transistor. The composite device behaves like an enhancement mode transistor with relatively low threshold voltage and substantial current drive. Inverters414are formed from high-voltage transistors and buffer the output of the push-pull stage.

Flying capacitor410shifts the logic information from the low voltage domain to the high voltage domain. Unlike a conventional current mirror, which configures a transistor to operate in the saturation region of transistor operation, transistor452of diode-mirrored load404is configured to operate in a linear region of transistor operation. When diode-mirrored load404is active (e.g., tail current442is steered through transistors434and436and then mirrored via transistor454, transistor452ensures that the top plate of flying capacitor410remains charged to high-voltage power supply voltage VCC. Transistor452operates as a resistive path ensuring the top plate of flying capacitor410remains charged to high-voltage power supply voltage VCC. The drain-to-source voltage of transistor452is close to zero Volts, thus transistor452operates in the linear region of transistor operation. When current is steered into transistors438and440, diode mirrored load404dis-engages and tail current442conducts through clamp circuit408, which clamps the top plate of capacitor410to [VCC−|VGS, LV, 432|−|VGS, HV, 422| while the bottom plate is discharged to 0 V and engages the high side path (i.e., the push up path of push-pull circuit412coupled to the high voltage domain). When current is steered into transistors434and436, diode mirrored load404engages and charges the top plate of flying capacitor410to high-voltage power supply voltage VCCwhile the bottom plate of flying capacitor410is discharged to low-voltage power supply voltage VDD, thereby engaging the low side path (i.e., the pull down path of push-pull circuit412coupled to the low voltage domain).

Flying capacitor410remains pre-charged with a first plate coupled to the high voltage domain and a second plate coupled to the low voltage domain, i.e., [VHVplate, VLVplate] at either:

where VGS, LV, 432is the gate-to-source voltage of transistor432, which is a low-voltage transistor, VGS, HV, 422is the gate-to-source voltage of transistor422, which is a high-voltage transistor (as indicated by the transistor symbol with the unfilled, rectangular gate), and where the high side path is on and the low side path is off; or
[VCC, VDD],
where the high side path is off and the low side path is on. In at least one embodiment of capacitive level shifter208, |VGS, LV, 432|+|VGS, HV, 422| is selected by design to be approximately equal to low-voltage power supply voltage VDD.

Thus, a capacitive level shifter has been described that realizes fast propagation delay (e.g., less than 2 ns) and negligible duty cycle distortion. In some embodiments, capacitive level shifter208has a propagation delay from input signal IN to output signal OUT, of less than one nanosecond with negligible duty cycle distortion (i.e., output signal OUT is symmetrical). The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location or quality. For example, “a first received network signal,” “a second received network signal,” does not indicate or imply that the first received network signal occurs in time before the second received network signal. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.