Microelectronic imagers and methods of packaging microelectronic imagers

Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

TECHNICAL FIELD

The present invention is related to microelectronic imagers and methods for packaging microelectronic imagers. Several aspects of the present invention are directed toward microelectronic imagers that are responsive to radiation in the visible light spectrum or radiation in other spectrums.

BACKGROUND

Microelectronic imagers are used in digital cameras, wireless devices with picture capabilities, and many other applications. Cell phones and Personal Digital Assistants (PDAs), for example, incorporate microelectronic imagers for capturing and sending pictures. The use of microelectronic imagers in electronic devices has been steadily increasing as imagers become smaller and produce higher quality images with increased pixel counts.

Microelectronic imagers include image sensors that use Charged Coupled Device (CCD) systems, Complementary Metal-Oxide Semiconductor (CMOS) systems, or other systems. CCD image sensors have been widely used in digital cameras and other applications. CMOS image sensors are also becoming very popular because they have low production costs, high yields, and small sizes. CMOS image sensors provide these advantages because they are manufactured using technology and equipment developed for fabricating semiconductor devices. CMOS image sensors, as well as CCD image sensors, are accordingly “packaged” to protect their delicate components and provide external electrical contacts.

FIG. 1is a schematic view of a conventional microelectronic imager1with a conventional package. The imager1includes a die10, an interposer substrate20attached to the die10, and a housing30attached to the interposer substrate20. The housing30surrounds the periphery of the die10and has an opening32. The imager1also includes a transparent cover40over the die10.

The die10includes an image sensor12and a plurality of bond-pads14electrically coupled to the image sensor12. The interposer substrate20is typically a dielectric fixture having a plurality of bond-pads22, a plurality of ball-pads24, and traces26electrically coupling bond-pads22to corresponding ball-pads24. The ball-pads24are arranged in an array for surface mounting the imager1to a board or module of another device. The bond-pads14on the die10are electrically coupled to the bond-pads22on the interposer substrate20by wire-bonds28to provide electrical pathways between the bond-pads14and the ball-pads24.

The imager1shown inFIG. 1also has an optics unit including a support50attached to the housing30and a barrel60adjustably attached to the support50. The support50can include internal threads52, and the barrel60can include external threads62engaged with the threads52. The optics unit also includes a lens70carried by the barrel60.

One problem with conventional packaged microelectronic imagers is that they have relatively large footprints and occupy a significant amount of vertical space (i.e., high profiles). For example, the footprint of the imager1inFIG. 1is the surface area of the bottom of the interposer substrate20, which is significantly larger than the surface area of the die10. Accordingly, the footprint of conventional packaged microelectronic imagers can be a limiting factor in the design and marketability of picture cell phones or PDAs because these devices are continually shrinking to be more portable. Therefore, there is a need to provide microelectronic imagers with smaller footprints and lower vertical profiles.

Another problem with conventional microelectronic imagers is the manufacturing costs for packaging the dies. For example, forming the wire-bonds28on the imager1shown inFIG. 1is complex and expensive because it requires connecting an individual wire between each bond-pad14on the die10and a corresponding pad22on the interposer substrate20. In addition, it may not be feasible to form wire-bonds for the high-density, fine-pitch arrays of some high-performance devices. Moreover, the support50and barrel60are assembled separately for each die10individually after the dies have been singulated from a wafer and attached to the interposer substrate. Therefore, there is a significant need to enhance the efficiency and reliability of packaging microelectronic imagers.

DETAILED DESCRIPTION

The following disclosure describes several embodiments of microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming support members carried by microelectronic imagers. One particular embodiment of the invention is directed toward a microelectronic imaging unit comprising a microelectronic die including a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. The imaging die also includes a plurality of electrical terminals (e.g., bond-pads) that are electrically coupled to the integrated circuit. The imaging die further includes an electrically conductive through-wafer interconnect extending through the die. A portion of the interconnect contacts the bond-pad. The die further includes a support member projecting from the bond-pad. The support member can be an integral extension of the interconnect or a separate component. The die can also have a cover carried by the support member over the image sensor.

Another particular embodiment of the invention is directed to a microelectronic imaging unit similar to the imaging unit described above. In this embodiment, however, an image sensor is not placed on the die until after the interconnect and support member have been formed through and/or on the die.

In another embodiment, the microelectronic imager includes a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. The imager also includes a plurality of bond-pads electrically coupled to the integrated circuit and a plurality of through-wafer interconnects extending through the die and in contact with corresponding bond-pads. The imager also includes support members carried by and projecting from corresponding bond-pads and a cover over the image sensor. The cover is carried by at least one of the support members. The imager can further include a stand-off on the cover and an optics unit coupled to the stand-off. The optics unit can include an optic member positioned at a desired location relative to the image sensor on the imager.

Another embodiment of the invention is directed toward a method for packaging microelectronic imagers. The method can include providing a microelectronic die having an integrated circuit and an image sensor electrically coupled to the integrated circuit. The method can further include forming a bond-pad on the substrate and electrically coupling the bond-pad to the integrated circuit. The method continues by forming a passage through the die and constructing an interconnect in at least a portion of the passage. The interconnect contacts the bond-pad to provide an array of electrical contacts on the backside of the die. The method further includes forming a support member projecting from the bond-pad. The support member, for example, can be integral with or otherwise contact the interconnect and/or the bond-pad. A cover can then be coupled to the support member over the image sensor.

Many specific details of the present invention are described below with reference to microfeature workpieces. The term “microfeature workpiece” is used throughout this disclosure to include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. For example, such microfeature workpieces can include semiconductor wafers (e.g., silicon or gallium arsenide wafers), glass substrates, insulated substrates, and many other types of substrates. The feature sizes in microfeature workpieces can be 0.11 μm or less, but microfeature workpieces can have larger submicron or supra-micron features.

Specific details of several embodiments of the invention are described below with reference to microelectronic imager dies and other microelectronic devices in order to provide a thorough understanding of such embodiments. Other details describing well-known structures often associated with microelectronic devices are not set forth in the following description to avoid unnecessarily obscuring the description of the various embodiments. Persons of ordinary skill in the art will understand, however, that the invention may have other embodiments with additional elements or without several of the elements shown and described below with reference toFIGS. 2A–6.

In the FIGS, identical reference numbers identify identical or at least generally similar elements. To facilitate the discussion of any particular element, the most significant digit or digits of any reference number refer to the FIG. in which that element is first introduced. For example, element210is first introduced and discussed with reference toFIG. 2.

B. Embodiments of Microelectronic Imagers

FIGS. 2A–2Hillustrate various stages in a method of forming electrically conductive through-wafer interconnects and support members through and/or carried by an imaging unit200in accordance with one embodiment of the invention.FIG. 2A, more specifically, is a schematic side cross-sectional view of an imaging unit200. In the illustrated embodiment, the imaging unit200includes a die210having a substrate211with a first side241and a second side242opposite the first side241, an integrated circuit230(shown schematically), and an image sensor212electrically coupled to the integrated circuit230. The image sensor212can be a CMOS device or a CCD for capturing pictures or other images in the visible spectrum. In other embodiments, the image sensor212can detect radiation in other spectrums (e.g., IR or UV ranges). The die210also includes a plurality of bond-pads222electrically coupled to the integrated circuit230.FIG. 2Aand subsequent FIGS. illustrate the various stages of forming electrically conductive interconnects and support members for two bond-pads222. It will be appreciated, however, that a plurality of through-wafer interconnects and/or support members are constructed simultaneously for a plurality of bond-pads222on a die210.

The die210can also include a first dielectric layer250over the first side241of the die210and a second dielectric layer251over the first dielectric layer250. The second dielectric layer251can also cover the bond-pads222and image sensor212. The second dielectric layer251protects the image sensor212from damage when the die210is handled in subsequent packaging steps. The first and second dielectric layers250,251, and/or one or more subsequent dielectric layers, can be a low temperature chemical vapor deposition (low temperature CVD) material, such as tetraethylorthosilicate (TEOS), parylene, silicon nitride (Si3N4), silicon oxide (SiO2), and/or other suitable materials. The foregoing list of dielectric and dielectric material options is not exhaustive. The dielectric layers250,251are generally composed of different materials, but it is possible that two or more of these layers are composed of the same material. In addition, one or more of the layers described above with reference toFIG. 2A, or described below with reference to subsequent FIGS, may be omitted.

FIG. 2Billustrates cutting passages or through-holes260through the microelectronic imaging unit200. Each through-hole260can extend through the substrate211, the corresponding bond-pad222, the first dielectric layer250, and the second dielectric layer251. The through-holes260can be formed using a laser263(shown schematically) to cut from the second side242of the substrate211toward the first side241. In a different embodiment, the laser263can conceivably cut from the first side241toward the second side242. The laser263can be aligned with respect to the corresponding bond-pads222using scanning/alignment systems known in the art.

After forming the through-holes260, they are cleaned to remove ablated byproducts (i.e., slag) and/or other undesirable byproducts resulting from the laser cut. The through-holes260can be cleaned using cleaning agents that do not attack or otherwise degrade the metal of the bond-pads222. For example, one such cleaning agent may include 6% tetramethylammonium hydroxide in propylene glycol for removing laser ablated byproducts. In other embodiments, the through-holes260can be cleaned using other methods. Alternatively, in certain other embodiments, the through-holes260are not cleaned after formation.

In other embodiments, the through-holes260can be formed by suitable etching processes. For example, the through-holes260can be etched using one or more etching steps that selectively remove material from the substrate211and dielectric layers250,251compared to the bond-pad222. An etching process used to form a hole through the second dielectric layer251and/or the hole260through the substrate211can be different than an etching process used to form a hole through the bond-pad222.

Referring next toFIG. 2C, a third dielectric layer252is applied to the die210to cover the second side242of the die210and the sidewalls of the through-holes260. The third dielectric layer252can be applied in a number of different ways. For example, in the illustrated embodiment the third dielectric layer252is applied to the die210so that it covers the exposed portions of the substrate211, the bond-pads222, and the second dielectric layer251in the through-hole260. In one embodiment the third dielectric layer252can be a low temperature CVD oxide, but in other embodiments the third dielectric layer252can be other suitable dielectric materials. The third dielectric layer252electrically insulates the components of the die210from an interconnect that is subsequently formed in the through-holes260, as described in greater detail below.

After applying the third dielectric layer252, a first conductive layer254is deposited onto the die210. In the illustrated embodiment, the first conductive layer254covers the entire third dielectric layer252. The first conductive layer254is generally a metal layer, such as a TiN layer, but in other embodiments the first conductive layer254can be other materials suitable for a particular application. When the first conductive layer354is composed of TiN, it can be formed using TiCl4TiN and an atomic layer deposition or chemical vapor deposition process. As explained below, the first conductive layer254provides a material for plating another layer of metal onto only selected areas of the wafer (e.g., in the through-holes360).

Referring next toFIG. 2D, portions of the first conductive layer254are removed from the horizontal and diagonal surfaces of the imaging unit200. In one embodiment, such portions of the first conductive layer254are removed from these surfaces by a suitable etching process, such as a “dry etch” or “spacer etch” process that preferentially removes material from horizontal surfaces and other surfaces having transverse components relative to the direction of the etchant. In other embodiments, different processes can be used to selectively remove non-vertical portions of the first conductive layer254so that the vertical portions of the first conductive layer254on the sidewalls in the through-holes260remain on the workpiece.

After removing the selected portions of the first conductive layer254, a second conductive layer256is deposited onto the remaining portions of the first conductive layer254. The second conductive layer256can act as a wetting agent to facilitate subsequently depositing additional conductive material into the through-holes260. In one embodiment, the second conductive layer256can be Ni that is deposited onto a first conductive layer254composed of TiN in an electroless plating operation. In this embodiment, when the TiN is activated by an HF:Pd wet dip, it provides nucleation for the Ni during the plating process. The plating process may also be performed using an activationless Ni chemistry with reduced stabilizer content. The TiN can enhance the adhesion and electrical properties to induce nucleation. In other embodiments, the second conductive layer256can be other suitable materials, and/or one or more of the first and second conductive layers254,256may be omitted.

Referring next toFIG. 2E, portions of the first dielectric layer251are removed from the bond-pads222by etching the first dielectric layer251to form openings261that expose the bond-pads222. In other embodiments, the first dielectric layer251can be removed around the bond-pads222using other suitable processes, including laser drilling. In this embodiment, the etching process should be terminated before damaging the bond-pads222. A conductive fill material258is then deposited into the through-holes260and openings261to form interconnects277extending through the die210. The conductive fill material258can also cover the first dielectric layer251. The fill material258can be solder or other electrically conductive materials. Various methods can be used to deposit the fill material258onto the die210. For example, the fill material258can be deposited by electroplating, stenciling, or other methods known to those of skill in the art.

Referring nextFIGS. 2E and 2F, the overburden portion of the fill material258on the first dielectric layer251shown inFIG. 2Eis removed to leave fill material258in the through-holes260and the openings261. The upper portion of the fill material258can be removed using a chemical-mechanical planarization process (CMP) and/or an etching process. The fill material258left in the openings261over the bond-pads222forms support members270projecting from at least a portion of corresponding bond-pads222on the die210. The support members270in the embodiment shown inFIG. 2Fare electrically coupled to corresponding bond-pads222and integral with corresponding interconnects277. The first dielectric layer251is then removed from the first side241of the die210using a suitable etching and/or washing process that does not damage the image sensor212.

The support members270are constructed to have a desired height “H” relative to the image sensor212for mounting a cover plate or other optical component to the imaging unit200. CMP processes are highly accurate and can provide good control of the height H across a workpiece having a large number of imaging units200. As such, the support members270are expected to provide an exceptionally accurate reference elevation for mounting optical components on the imaging unit200in subsequent packaging steps.

Referring next toFIG. 2G, an adhesive271is applied to the support members270and a cover275is mounted onto the support members270. The cover275has a first side281facing generally away from the image sensor212and a second side279facing generally toward the image sensor212. The cover275and the support members270form an enclosure276for protecting the image sensor212. In another embodiment, the cover275can be mounted to the support members270in a chamber containing an inert gas. The inert gas is trapped in the enclosure276and decreases yellowing of the image sensor212caused by oxygen. The cover275can be glass, quartz, or other materials transmissive to a desired spectrum of radiation. In embodiments directed toward imaging radiation in the visible spectrum, the cover275can also filter infrared radiation or other undesirable spectrums of radiation. The cover275, for example, can be formed from a material and/or can have a coating that filters IR or near IR spectrums.

An underfill material232is deposited around the periphery of each bond-pad222and support member270. The underfill material232enhances the integrity of the joint between the cover275and the microelectronic die210to protect the image sensor212, support member270, and bond-pad222from moisture, chemicals, and other contaminants. In other embodiments, the underfill material232may be deposited in other locations on the die210or the underfill material232may be omitted.

An array of ball-pads224is then attached to corresponding interconnects277at the second side242of the die210to provide an external connection to other electronic devices on the backside of the die210. Solder balls (not shown) can be placed on the ball-pads224to attach the die210to a module or other board. In other embodiments, conductive pastes or other electrical couplers may be placed on the interconnects277.

FIG. 3is a schematic cross-sectional view of a microelectronic imager300in accordance with an embodiment of the invention. The imager300includes the imaging unit200and an optics unit310attached to the imaging unit200. The optics unit310is positioned to transmit at least the desired spectrum of radiation to the image sensor212on the imaging unit200. The embodiment of the optics unit310shown inFIG. 3includes a substrate311, an optic member312on the substrate311, and a stand-off314attached to the substrate311. The substrate311, which can be glass, quartz, or another material, can be coated to filter infrared radiation from the visible light spectrum. The optic member312is a lens for focusing or otherwise directing the radiation. In other embodiments, the optic member312can include other optical structures for performing other functions. The stand-off314carries and positions the substrate311and the optic member312at a desired location relative to the image sensor212. For example, the stand-off314can be a cylindrical or rectilinear member having a step315at a distance “D” from the reference elevation defined by the top of the support members270and a sidewall316at a desired distance from an alignment axis A—A of the image sensor212. The step315and support members270accurately position the optic member312at a desired distance from the image sensor212. The sidewall316similarly precisely aligns the optic member312with the alignment axis A—A. The step315and sidewall316accordingly define a reference element for positioning the optic member312relative to the image sensor212. The stand-off314may include configurations such as those described in U.S. patent application Ser. No. 10/723,363, entitled “Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers,” filed on Nov. 26, 2003, which is incorporated by reference herein in its entirety. In further embodiments, the imaging unit200may not include an optics unit310as shown inFIG. 3.

The embodiment of the microelectronic imager300shown inFIG. 3provides several advantages compared to the conventional imager shown inFIG. 1. First, the microelectronic imager300can be much smaller than the conventional imager. The footprint of the microelectronic imager300can be as small as the size of the die210because the interconnects277provide an electrical connection to an array of ball-pads224on the second side242of the die210instead of using wire-bonds. The through-wafer interconnects277accordingly eliminate the need for an interposer substrate, and thus the additional footprint of the interposer substrate is also eliminated. Second, the height of the microelectronic imager300is also less than that of conventional imagers because the imager300is not mounted to an interposer substrate. Therefore, the microelectronic imager300has a lower profile than conventional imagers and can be used in smaller electronic devices, such as picture cell phones, PDAs, or other applications where space is limited.

Another advantage of the imager300is that the support members270eliminate the need for forming additional spacers around the image sensor212to position and support the cover275. The support members270also provide an exceptionally precise reference elevation for mounting the cover275and optics unit310because of the precision provided by removing the overburden of the fill material258using CMP processing as described above with reference toFIG. 2F. Accordingly, the manufacturing process is more efficient and accurate than processes that deposit beads of material around the image sensors to form spacers on the die210. Another advantage of this feature is that the footprint of each microelectronic imager300is smaller because the electrically conductive support members270are positioned on at least a portion of each corresponding bond-pad222rather than outboard of the bond-pads222.

FIG. 4is a schematic side cross-sectional view of a microelectronic imager400in accordance with another embodiment of the invention. The imaging unit200can be generally similar to the imaging unit200shown inFIG. 3; like reference numbers accordingly refer to like components inFIGS. 3 and 4. In this embodiment, an optics unit410includes a substrate411, the stand-off314, and an optic member412. The optic member412includes a first lens414and a second lens418. The first lens414can be a focus or dispersion lens, and the second lens418can be a pinhole lens having a pinhole419. The pinhole lens418can be a layer of material deposited on the substrate411, and the pinhole419can be etched or laser drilled through the layers of material. In other embodiments, the microelectronic imagers300and400can include different optical structures for performing different functions.

FIG. 5illustrates a stage in a method of forming electrically conductive through-wafer interconnects and support members in an imaging unit500in accordance with another embodiment of the invention. The initial stages of this method are at least generally similar to the steps described above with reference toFIGS. 2A–2F, and thusFIG. 5shows a workpiece configuration similar to that illustrated inFIG. 2F. The subsequent stages of this method, however, differ from that described above with reference toFIGS. 2A–2Fin that the image sensor (not shown) is not constructed on the imaging unit500until after the interconnects277and support members270have been formed. After forming an image sensor212(shown in phantom) on the die210, the imaging unit500can undergo additional packaging steps that are at least generally similar to those described above with reference toFIG. 2Gto package the imagers illustrated inFIG. 3orFIG. 4.

The embodiments described above with reference toFIGS. 2A–5include various methods for forming and/or filling through-holes in microelectronic workpieces that extend through bond-pads and/or associated substrates. In other embodiments, other methods can be used to form and/or fill such through-holes. Accordingly, the present invention is not limited to the particular methods for forming and/or filling the through-holes described above, but it also includes alternative methods for providing a conductive fill material in a through-hole to form an array of ball-pads on the backside of the imager and support members on the front side of the imager projecting from the bond-pads.

FIG. 6is a schematic cross-sectional view of an assembly600including a plurality of microelectronic imagers690that each include an imaging die210and an optics unit610. The assembly600includes a microelectronic imager workpiece602having a first substrate604and a plurality of imaging dies210formed in and/or on the first substrate604. The individual imaging dies210can be generally similar to the imaging die210described above with respect toFIG. 2H; like reference numbers accordingly refer to like components inFIGS. 2H and 6. The assembly600also includes an optics workpiece630that includes a second substrate634and a plurality of optics units610on the second substrate634. Individual optic units610can include an optic member612on the second substrate634. The optic member612can include lenses and/or filters for manipulating the radiation passing through the optics unit610.

The assembly600further includes a plurality of stand-offs660configured to position individual optic units610with respect to individual image sensors212. Suitable stand-offs are disclosed in U.S. patent application Ser. No. 10/723,363 incorporated by reference above. The microelectronic imagers690can be assembled by seating the stand-offs660so that the optics units610are accurately aligned with the image sensors212. In one embodiment, the stand-offs660are seated before singulating the individual imagers690such that all of the microelectronic imagers are assembled at the wafer level. Both of the first and second substrates604and634can then be cut along lines A—A to separate individual imagers690from each other.

One advantage of the assembly600of microelectronic imagers690illustrated inFIG. 6is that the through-wafer interconnects enable a plurality of microelectronic imagers to be fabricated at the wafer level using semiconductor fabrication techniques. Because the through-wafer interconnects provide an array of ball-pads on the backside of the imaging dies210, it is not necessary to wire-bond the bond-pads on the front side of the wafer to external devices. The bond-pads can accordingly be covered at the wafer level. This enables the process of (a) fabricating a plurality of imaging dies210at the wafer level on one substrate, (b) fabricating a plurality of optics units610at the wafer level on another substrate, and (c) assembling a plurality of optic units610with a corresponding plurality of imaging dies210at the wafer level using automated equipment. Therefore, the microelectronic imagers690with through-wafer interconnects enable processes that significantly enhance the throughput and accuracy of packaging microelectronic imagers.

Another advantage of the assembly600of microelectronic imagers690is the ability to decrease the real estate that the imagers690occupy in a cell phone, PDA, or other type of device. Because the imagers690do not require an interposer substrate to provide external electrical contacts in light of the through-wafer interconnects277, the footprint of the imagers690can be the same as that of the die210instead of the interposer substrate. The area occupied by the imagers690is accordingly less than conventional imagers because the footprint of the individual imaging dies210is significantly smaller than that of the interposer substrate. Furthermore, because the dies210provide a backside array of ball-pads224that can be coupled directly to a module without an interposer substrate, the profile is lower and the time and costs associated with mounting the die to the interposer substrate are eliminated. This results in greater throughput, lower packaging costs, and smaller imagers.

A further advantage of wafer-level imager packaging is that the microelectronic imagers690can be tested from the backside of the dies210at the wafer level before the individual imagers690are singulated. A test probe can contact the backside of the dies210to test the individual microelectronic imagers690because the through-wafer interconnects277provide backside electrical contacts. Accordingly, because the test probe engages contacts on the backside of the imager workpiece602, it will not damage the image sensors212, the optics units640, or associated circuitry on the front of the microelectronic imagers690. Moreover, the test probe does not obstruct the image sensors212during a backside test, which allows the test probe to test a larger number of dies at one time compared to processes that test imaging dies from the front side. As such, it is more efficient in terms of cost and time to test the microelectronic imagers690at the wafer level (i.e., before singulation) than to test each imager690from the front side of the dies210. Furthermore, it is advantageous to test the microelectronic imagers690in an environment where the individual image sensors212and/or optics units640will not be damaged during testing.

Yet another advantage of wafer-level processing is that the microelectronic imagers690can be singulated after assembling the optics units640to the dies210. The attached optics units640protect the imager sensors212on the front side of the dies210from particles generated during the singulation process. Thus, the likelihood that the image sensors212or associated circuitry on the front side of the dies210will be damaged during singulation and subsequent handling is significantly reduced.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, the microelectronic imagers can have any combination of the features described above with reference toFIGS. 2A–6. Accordingly, the invention is not limited except as by the appended claims.