Inductor capacitor filter in far back end of line and integration schemes

A semiconductor device is provided. The semiconductor device comprises an inductor in a far back end of line layer and a capacitor adjacent to and electrically coupled with the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via in a first insulating layer A dielectric layer is provided over the first electrode layer. A second electrode layer is provided over the dielectric layer and a metal fill layer is provided over the second electrode layer. The metal fill layer has a top surface at least level with a top surface of the first insulating layer.

FIELD OF THE INVENTION

The disclosed embodiments relate generally to semiconductor devices, and more particularly, to an inductor capacitor filter in far back end of line (far BEOL) with high density and integration schemes thereof.

BACKGROUND

An inductor capacitor (LC) filter device includes an inductor and a capacitor having a common node. A load resistor may be connected to the common node and to a ground terminal. The LC filter may be used as a low pass filter with a node of the capacitor connected to the ground terminal or as a high pass filter with a node of the inductor connected to the ground terminal. The term “low pass filter” may refer to a filter that allows signals with a frequency lower than a cut off frequency to pass. The term “high pass filter” may refer to a filter that allows signals with a frequency higher than a cut off frequency to pass.

Current wafer level LC filter devices have low density capacitance with less than a few nano Farad per mm square (nF/mm2) and inductance of less than a few nano Henry per mm square (nH/mm2). The low density capacitance and inductance is not suitable for low frequency applications such as power management in mobile devices. Discrete inductors and capacitors which are not integrated into the semiconductor chip may have higher capacitance and inductance values, respectively but they are bulky and expensive. Thus, there is a need for an improved LC filter device to overcome the challenges mentioned above.

SUMMARY

In an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device comprising an inductor in a far BEOL layer, and a capacitor adjacent to and electrically coupled to the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via opening in a first insulating layer, a dielectric layer over the first electrode layer, a second electrode layer over the dielectric layer, a metal fill layer over the second electrode layer, whereby the metal fill layer has a top surface at least level with a top surface of the first insulating layer.

In another aspect of the present disclosure, a semiconductor device is provided. The semiconductor device comprising an inductor in a far BEOL layer, and a capacitor adjacent to and electrically coupled to the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via opening in a first insulating layer, the first electrode layer extends over at least a portion of a top surface of the first insulating layer, a dielectric layer over the first electrode layer, a second electrode layer over the dielectric layer, and a metal fill layer over the second electrode layer, the metal fill layer having a top surface at least level with a top surface of the second electrode layer over the first insulating layer.

In yet another aspect of the present disclosure, a method of fabricating a semiconductor device is provided. The method comprises forming an inductor in a far BEOL layer, and forming a capacitor adjacent to and electrically coupled to the inductor. The formation of the capacitor comprises providing a first electrode layer over sidewalls and a bottom surface of a via opening in a first insulating layer, providing a dielectric layer over the first electrode layer, providing a second electrode layer over the dielectric layer and providing a metal fill layer over the second electrode layer, whereby the metal fill layer has a top surface at least level with a top surface of the first insulating layer.

Numerous advantages may be derived from the embodiments described below. The embodiments may provide an inductor capacitor filter with a high capacitance density of at least 100 nF/mm2and a high inductance density of at least 100 nH/mm2. The inductor capacitor filter is integrated into a semiconductor chip in the far BEOL layer thereby providing a compact and cost-effective solution suitable for low frequency applications of less than 50 MHz including power management in mobile devices.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the devices. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the devices. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

DETAILED DESCRIPTION

The following detailed description is exemplary in nature and is not intended to limit the devices or the application and uses of the devices. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the devices or the following detailed description.

FIG.1Ais a schematic view of a semiconductor device108, according to an embodiment of the disclosure. The semiconductor device108illustrated inFIG.1Amay be an inductor capacitor filter or an impedance matching network. The inductor capacitor filter108may comprise a capacitor128which is adjacent to and is electrically coupled to an inductor190and are provided in a far BEOL layer. An integrated circuit110comprising transistors and multiple BEOL layers may be provided below the inductor capacitor filter108. The term “far BEOL” may refer to a portion of a semiconductor processing that creates a metal layer (e.g., the under-bump-metal or redistribution layer) and associated interconnect structures forming a connection between on-chip and off-chip wiring. The term “BEOL” may refer to a portion of a semiconductor processing that creates conductive lines carrying power and signals between devices such as transistors to a semiconductor chip interface.

Referring toFIG.1A, the capacitor128may comprise a first electrode layer112arranged over sidewalls and a bottom surface of a via22in a first insulating layer106. The via22is arranged over a first metallization structure122. A dielectric layer116may be provided over the first electrode layer112. A second electrode layer118may be provided over the dielectric layer116. A metal fill layer120may provided over the second electrode layer118, whereby the metal fill layer120completely fills up the via22. In one embodiment, a top surface of the metal fill layer120may be at least level with a top surface of the first insulating layer106. In further embodiments, the top surface of the metal fill layer120may be higher than the top surface of the first insulating layer106. In one embodiment, the via22may have a height y of between 20 to 50 micrometers (μm). In another embodiment, the via22may have an upper diameter x1of at least 50 micrometers (μm). The term “metal fill” may refer to a conductive material providing a low contact resistance. For example, the metal fill layer120provides a low contact resistance for the capacitor128.

The first electrode layer112of the capacitor128may extend over at least a portion of a top surface of the first insulating layer106. For example, the width of the first electrode layer112may be wider than the upper diameter x1of the via22. For example, the portion of the top surface of the first insulating layer106has a length x2with a range between 5 to 50 micrometers (μm). A first end portion of the dielectric layer116may extend over a first end portion of the first electrode layer112. The first end portion of the dielectric layer116may completely cover the first end portion of the first electrode layer112. A second end portion of the first electrode layer112may extend beyond a second end portion of the dielectric layer116. A first contact pillar126may be provided over the second end portion of the first electrode layer112thereby providing a connection to an input node. For example, the first contact pillar126may be laterally offset from the via22of the capacitor128. The first contact pillar126provides an electrical connection to the first electrode layer112of the capacitor128on a surface of the inductor capacitor filter108thereby providing more options for circuit designers. The second electrode layer118and the metal fill layer120may extend over the dielectric layer116of the capacitor128. The extension of the first electrode layer112, the dielectric layer116, the second electrode layer118and the metal fill layer120of the capacitor128over the top surface of the first insulating layer106provides advantages of increased capacitance value as well as providing an electrical connection to other devices or input nodes.

In some embodiments, the dielectric layer116may comprise a high dielectric constant and high energy band gap material including tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), other suitable high dielectric constant material or its combinations. The term “high dielectric constant material” may refer to a dielectric material with a dielectric constant of at least 7. The term “high energy band gap material” may refer to a dielectric material with a band gap of at least 4 electron volts (eV). In further embodiments, the dielectric layer116may be made of silicon dioxide, silicon nitride or silicon oxynitride. In one embodiment, the dielectric layer116may have a thickness range between 10 nm and 30 nm. The first insulating layer106may comprise a photosensitive polyimide (PSPI) layer, bisbenzocyclobutene (BCB) or polybenzoxazoles (PBO). An advantage of using a PSPI, BCB or PBO layer as the first insulating layer106is that it may be easily patterned like a photoresist layer.

The first electrode layer112may be made of tantalum nitride (TaN), titanium nitride (TiN), copper seed (Cu) or any other suitable metal liner materials. The second electrode layer118may be made of tantalum nitride (TaN), titanium nitride (TiN), copper seed (Cu) or any other suitable metal liner materials. In one embodiment, the first electrode layer112and the second electrode layer118may be made of the same materials. In other embodiments, the first electrode layer112and the second electrode layer118may be made of different materials.

The inductor190may be provided adjacent to the capacitor128and comprises a first metallization layer138. A second metallization layer152may be provided over the first metallization layer138. A second contact pillar150may connect the first metallization layer138and the second metallization layer152. A magnetic core160may be provided between the first metallization layer138and the second metallization layer152, whereby the magnetic core160is electrically insulated from the first metallization layer138and the second metallization layer152by the first insulating layer106. In some embodiments, the inductor190may be a solenoid inductor. The first metallization layer138, the second contact pillar150and the second metallization layer152may form a solenoid coil of the inductor190.

A portion166of the second electrode layer118of the capacitor128and the metal fill layer120may extend over at least a portion of a top surface of the first insulating layer106to electrically connect with the second metallization layer152of the inductor190. Dashed lines indicate an interface between the portion166of the metal fill layer120of the capacitor128, the metal fill layer120of the capacitor128and the second metallization layer152of the inductor190. A second metallization structure156may be provided below the first metallization layer138of the inductor190, whereby the second metallization structure156may be connected to an input node. A second insulating layer132may be provided over the capacitor128and the inductor190. Openings136band136cin the second insulating layer132may expose a portion158aof the metal fill layer120of the capacitor128and a portion158bof the second metallization layer152of the inductor190respectively, for connection to a common input node. An opening136ain the second insulating layer132may expose the first contact pillar126. The second insulating layer132may comprise PSPI, BCB, PBO, or any other suitable insulating layers. In some embodiments, the first insulating layer106and the second insulating layer132may be made of the same material. In further embodiments, the first insulating layer106and the second insulating layer132may be made of different materials. In one embodiment, the first metallization structure122of the capacitor128, and the first metallization layer138of the inductor108may be made of the same material, for example, the first metallization structure122and the first metallization layer138may be formed in the same process. In other embodiments, they may be formed of different electrically conductive materials in separate processes In yet another embodiment, the metal fill layer120of the capacitor128, part of the second contact pillar150, the second metallization layer152of the inductor190and the first contact pillar126of the capacitor128may be made of the same material in the same process, or may be formed from different electrically conductive materials in other embodiments. An example of a suitable conducting material may be copper (Cu).

FIG.1Bis an exploded view of a portion of the capacitor128, according to an embodiment of the disclosure. Referring toFIG.1B, the second end portion of the second electrode layer118and an end portion of the metal fill layer120may partially cover the second end portion of the dielectric layer116.

FIG.1Cis a top view of an inductor capacitor filter108, according to an embodiment of the disclosure. From a top-down perspective, the capacitor128may have a circular shape. In further embodiments, the capacitor128may have a polygonal shape. In some embodiments, the capacitor may have a substantially square or rectangular shape, where the corners may be substantially rounded due to processing effects. The capacitor128may be connected to the inductor190by the portion166of the metal fill layer120, Dashed lines indicate an interface between the portion166of the metal fill layer120, the portion158aof the metal fill layer120of the capacitor128and the portion158bof the second metallization layer152of the inductor190. The second metallization structure156may be connected to the first metallization layer138of the inductor190and to an external input terminal.

FIG.1Dis a cross-section view of an inductor capacitor filter108taken along section line X-X′ ofFIG.1C, according to an embodiment of the disclosure.FIG.1Dis subsequently used to illustrate a fabrication process flow for an inductor capacitor filter108. In contrast toFIG.1A,FIG.1Ddoes not show a portion166of a metal fill layer120connecting a capacitor128to an inductor190, a second metallization structure156electrically connecting a first metallization layer138of the inductor190to a bond pad192of an underlying integrated circuit110and a portion158bof the second metallization layer152of the inductor190. The same reference numerals used inFIG.1Aare also used inFIG.1Cto refer to identical features.

Referring toFIG.1D, the inductor capacitor filter108may be provided in the far BEOL layer. The inductor capacitor filter108comprises a capacitor128having a first electrode layer112arranged over sidewalls and a bottom surface of a via22in a first insulating layer106and is over at least a portion of a top surface of the first insulating layer106. The via22is provided over a first metallization structure122. A dielectric layer116may be arranged over the first electrode layer112. A second electrode layer118may be arranged over the dielectric layer116. A metal fill layer120may be arranged over the second electrode layer118, whereby the metal fill layer120completely fills up the via. In an embodiment, a top surface of the metal fill layer120may be at least level with a top surface of the second electrode layer118. In further embodiments, the top surface of the metal fill layer120may be higher than the top surface of the second electrode layer118. An inductor190may be provided adjacent to the capacitor128, whereby the inductor190may be electrically coupled to the capacitor128. The inductor190and the capacitor128may be provided over an integrated circuit110.

In some embodiments, the integrated circuit110may be of various technologies including, and not limited to, 55BCDLite, power management integrated circuit (PMIC), interactive voice response (IVR) circuit, power system on chip (PowerSoC). In other embodiments, the integrated circuit110may be of various technology nodes including, and not limited to, 22 nm, 40 nm and 130 nm technologies. The inductor capacitor filter108in the far BEOL layer is electrically connected to but does not interfere with the underlying metal layers of the integrated circuit110.

FIG.1Eis a cross-section view of a portion of an inductor capacitor filter108taken along section line A-A′ ofFIG.1C, according to an embodiment of the disclosure. The cross-section view inFIG.1Eshows the second metallization structure156electrically connecting the first metallization layer138of the inductor190to a bond pad192of the underlying integrated circuit110. Although not shown, the second metallization structure156may be connected to an input terminal.

FIG.1Fis a circuit diagram of an inductor capacitor filter108used as a low pass filter, according to an embodiment of the disclosure. Referring toFIG.1F, a node158may refer to either the portion158aof the metal fill layer120of the capacitor128or the portion158bof the second metallization layer152of the inductor190. A load resistor170may be electrically connected to the node158and the first contact pillar126of the capacitor128. The first contact pillar126of the capacitor128may be connected to a ground terminal. The second metallization structure156of the inductor190may be connected to an input terminal. The inductor capacitor filter108as connected may operate as a low pass filter.

FIG.1Gis a circuit diagram of an inductor capacitor filter108used as a high pass filter, according to another embodiment of the disclosure. Referring toFIG.1G, a load resistor170may be electrically connected to the node158and the second metallization structure156of the inductor190. The second metallization structure156may be connected to a ground terminal. The first contact pillar126of the capacitor128may be connected to an input terminal. The inductor capacitor filter108as connected may operate as a high pass filter.

FIGS.2to17illustrate a fabrication process flow for an inductor capacitor filter108shown inFIG.1D, according to some embodiments of the disclosure. For simplicity, only an upper portion of the integrated circuit110is shown inFIGS.3-17.FIG.2shows an integrated circuit110with an opening12formed in a passivation layer over a bond pad172, according to some embodiments of the disclosure. Although not shown, an opening in a passivation layer may also be formed over the bond pad192shown inFIG.1E. The opening12may be formed by patterning the passivation layer using conventional photolithography process and etching by depositing a photoresist layer over the passivation layer followed by exposure and developing to form a photoresist pattern. A wet etch or dry etch process may be used to remove portions of the passivation layer that is not covered by the photoresist pattern to thereby form the opening12. The photoresist pattern may subsequently be removed.

FIG.3is a partially completed inductor capacitor filter108after deposition and patterning of a photoresist layer16to expose the bond pad172, according to some embodiments of the disclosure. The photoresist layer16may be deposited over an upper surface of the integrated circuit110and patterned by conventional photolithography process to form an opening over the bond pad172.

FIG.4is a partially completed inductor capacitor filter108after formation of a lower portion176of a first metallization structure122and a portion106aof a first insulating layer106, according to some embodiments of the disclosure. A suitable metallization material, for example, copper, may be deposited in the opening in the photoresist layer16over bond pad172by a suitable deposition method, for example, physical vapor deposition, followed by electroplating and photoresist lift-off. Although not shown, a layer of copper may also be formed over the photoresist layer16. The photoresist layer16may subsequently be removed to leave behind a layer of copper over the bond pad172thereby forming the lower portion176of the first metallization structure122. Although not shown, the second metallization structure156may also be simultaneously formed over the bond pad192shown inFIG.1E. A first insulating layer106, for example, a photosensitive polyimide (PSPI), may subsequently be deposited over the upper surface of the integrated circuit110and over the lower portion176of the first metallization structure122by coating and photo exposure and subsequently patterned with photo developing. A portion of the PSPI layer over the lower portion176of the first metallization structure122may be removed so as to expose a top surface of the lower portion176. Another portion of the PSPI layer remains on the upper surface of the integrated circuit110and next to sidewalls of the lower portion176of the first metallization structure122, thereby forming the portion106aof the first insulating layer106.

FIG.5is a partially completed inductor capacitor filter108after deposition and patterning of a photoresist layer18, according to some embodiments of the disclosure. The photoresist layer18may be deposited over the portion106aof the first insulating layer106and over the lower portion176of the first metallization structure122and subsequently patterned by conventional photolithography process to form an opening20exposing the lower portion176of the first metallization structure122. An opening36may also be formed in the photoresist layer18exposing part of the portion106aof the first insulating layer106. The opening36may be a trench opening.

FIG.6is a partially completed inductor capacitor filter108after formation of a first metallization structure122, a first metallization layer138and a portion106bof the first insulating layer106, according to some embodiments of the disclosure. A layer of suitable material such as copper may be deposited in the openings20and36in the photoresist layer18by electroplating. Although not shown, a layer of copper may also be formed over the photoresist layer18. The photoresist layer18may subsequently be removed to leave behind a layer of copper over the lower portion176of the first metallization structure122and part of the portion106aof the first insulating layer106thereby forming the first metallization structure122and the first metallization layer138, respectively. Although not shown, the first metallization layer138may also be formed over the second metallization structure156shown inFIG.1Esimultaneously. A top surface of the first metallization layer138may be substantially level with a top surface of the first metallization structure122. A layer of PSPI may subsequently be deposited over the portion106aof the first insulating layer106, the first metallization structure122and the first metallization layer138to thereby form the portion106bof the first insulating layer106. Part of the portion106bof the first insulating layer106over the first metallization structure122and the first metallization layer138may be removed to form bottom portions of vias22and50, respectively. A bottom surface of the via22may be substantially level with a bottom surface of the via50.

FIG.7is a partially completed inductor capacitor filter108after formation of a layer of magnetic material178and a photoresist layer26over the layer of magnetic material178, according to some embodiments of the disclosure. The layer of magnetic material178comprises cobalt-based alloys, nickel-ferrite based alloys, or combinations thereof may be deposited over the portion106bof the first insulating layer106by a suitable process such as physical vapor deposition or electroplating. The layer of magnetic material178may fill up the bottom portions of the vias22and50over the first metallization structure122and the first metallization layer138, respectively. A layer of photoresist may be deposited and patterned by conventional photolithography process to form the photoresist layer26over a portion of the layer of magnetic material178next to the bottom portion of the via50and over the first metallization layer138.

FIG.8is a partially completed inductor capacitor filter108after formation of a magnetic core160, according to some embodiments of the disclosure. A wet etch or dry etch process may be used to remove a portion of the layer of magnetic material178not covered by the photoresist layer26leaving behind a portion of the layer of magnetic material178next to the bottom portion of the via50over the first metallization layer138thereby forming the magnetic core160. The photoresist layer26may be removed.

FIG.9is a partially completed inductor capacitor filter108after formation of a portion106cof the first insulating layer106and vias22and50in the first insulating layer106, according to embodiments of the disclosure. Referring toFIG.9, a layer of PSPI may be deposited over the portion106bof the first insulating layer106to form the portion106cof the first insulating layer106. Part of the portion106cof the first insulating layer106over the first metallization structure122and the first metallization layer138may be removed to form vias22and50, respectively, in the first insulating layer106. The magnetic core160may be surrounded by the first insulating layer106.

FIG.10is a partially completed inductor capacitor filter108after formation of a layer of suitable conducting material such as tantalum nitride (TaN)180and a photoresist layer28, according to embodiments of the disclosure. A layer of TaN180may be deposited over sidewalls and bottom surfaces of the vias22and50and upper surfaces of the first insulating layer106by physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition processes. A layer of photoresist may be deposited over the layer of TaN180and patterned by conventional photolithography process to leave behind the photoresist layer28in the vias22and50and extending over at least an upper surface of the first insulating layer106.

FIG.11is a partially completed inductor capacitor filter108after formation of a first electrode layer112and a barrier layer182, according to embodiments of the disclosure. A portion of the TaN layer180not covered by the photoresist layer28may be removed from part of a top surface of the first insulating layer106by a wet etch or dry etch process to leave behind a portion of the TaN layer180over sidewalls and bottom surfaces of the vias22and50thereby forming the first electrode layer112and the barrier layer182, respectively. The first electrode layer112and the barrier layer182may extend across at least over a top surface of the first insulating layer106.

FIG.12is a partially completed inductor capacitor filter108after formation of a dielectric layer186and a photoresist layer30, according to embodiments of the disclosure. A layer of high dielectric constant material may be deposited by ALD, PVD, CVD or any other suitable deposition processes over the first electrode layer112, over the barrier layer182and over a top surface of the first insulating layer106to form the dielectric layer186. A layer of photoresist may be deposited over the dielectric layer186and patterned by conventional photolithography process to form the photoresist layer30covering a portion of the dielectric layer186over the sidewalls and the bottom surface of the via22and over at least a top surface of the first insulating layer106.

FIG.13is a partially completed inductor capacitor filter108after formation of a dielectric layer116, according to embodiments of the disclosure. Portions of the dielectric layer186not covered by the photoresist layer30may be removed by a wet etch or dry etch process from a top surface of the first insulating layer106and the barrier layer182to leave behind a portion of the dielectric layer186over the first electrode layer112thereby forming the dielectric layer116. Part of the first electrode layer112over a top surface of the first insulating layer106may also be exposed after the removal of the dielectric layer186. The photoresist layer30may be removed after the etching process.

FIG.14is a partially completed inductor capacitor filter108after formation of a photoresist layer38, a second electrode layer118and a barrier layer188, according to embodiments of the disclosure. A layer of photoresist may be deposited over the first electrode layer112, the dielectric layer116, a top surface of the first insulating layer106and the barrier layer182and patterned by conventional photolithography process to form a photoresist layer38over the exposed part of the first electrode layer112, over an end portion of the dielectric layer116and over the top surface of the first insulating layer106. A layer of suitable conducting material such as TaN may be deposited by PVD, ALD or any other suitable process over the dielectric layer116and the barrier layer182thereby forming the second electrode layer118and the barrier layer188, respectively.

FIG.15is a partially completed inductor capacitor filter108after formation of a metal fill layer120, a second contact pillar150and a second metallization layer152, according to embodiments of the disclosure. A layer of suitable conducting material such as copper may be deposited by electroplating over the second electrode layer118and the barrier layer188to thereby form the metal fill layer120, the second contact pillar150and the second metallization layer152, respectively. The photoresist layer38may subsequently be removed. Although not shown, a portion166of the metal fill layer120and the second electrode layer118shown inFIGS.1A and1Cmay also be formed simultaneously.

FIG.16is a partially completed inductor capacitor filter108after formation of a second insulating layer132, according to embodiments of the disclosure. A layer of suitable insulating material such as PSPI may be deposited over the first electrode layer112, the metal fill layer120of the capacitor128, a top surface of the first insulating layer106, and the second metallization layer152of the inductor190thereby forming the second insulating layer132. Portions of the second insulating layer132over the exposed portion of the first electrode layer112and over the portion of the metal fill layer120extending over a top surface of the first insulating layer106may be removed to form openings136aand136b, respectively. Although not shown, an opening136cin the second insulating layer132over the second metallization layer152of the inductor190as shown inFIG.1Amay also be formed simultaneously.

FIG.17is a partially completed inductor capacitor filter108after formation of a photoresist layer52over the second insulating layer132, according to embodiments of the disclosure. The photoresist layer52may be deposited over the second insulating layer132and a portion of the photoresist layer52may be removed to expose the opening136a. Although not shown, a layer of suitable conductive material such as copper may be deposited in the opening136aand over the photoresist layer52. The photoresist layer52may subsequently be removed to leave behind the coper layer in the opening136ato thereby form the first contact pillar126and providing the inductor capacitor filter108as shown inFIG.1D.

The terms “first”, “second”, “third”, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms “left”, “right”, “front”, “back”, “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device.

While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the devices in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the devices, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.