Silicon carrier optoelectronic packaging

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

CROSS REFERENCE TO RELATED APPLICATION

This application is related to the following commonly-owned, co-pending United States patent application filed on even date herewith, the entire contents and disclosure of which is expressly incorporated by reference herein in its entirety: U.S. patent application Ser. No. (24252), for “3D OPTOELECTRONIC PACKAGING”.

BACKGROUND

The present invention relates generally to the field of integrated circuits and silicon chip technology, and more particularly, relates to a packaging system or packaging assembly and method thereof for optoelectronic devices in integrated circuits and silicon chip technology.

Computer system performance is increasingly important in current computer systems and data centers, including for example, personal computers, servers and server farms. Computer performance is measured by, for example, system availability, speed of computation, processor speed, among other measurable aspects. The communication bandwidth between computers and within a computer is important in a computer system's overall performance. The current trend towards multi-core processors and multiple processors per machine requires an increase in communication between processors, and between a processor and its memory. Current use of electrical data links perform best over short distances, but they reach a performance limit as the link distance and frequency increases. Optical data links over fiber are capable of high speed communication with low loss over large distances, however, current optical transceivers are bulky and expensive compared with their electrical counterparts.

Therefore, there is a need for a system or assembly/package and a method for reducing the size of optical transceivers used in computers, integrated circuits and chips. It would also be desirable for a system or assembly/package and method to lower the cost of using optical transceivers in computers, integrated circuits and chips.

BRIEF SUMMARY

In an aspect of the present invention, an optoelectronic (OE) assembly for a semiconductor or computer chip includes a silicon layer with wiring, the silicon layer defines at least one optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer. The optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements is positioned in optical alignment with the optical via for receiving the light. In a related aspect, the plurality of OE elements are attached beneath the silicon layer and electrically communicating with the wiring, and the OE elements are positioned in optical alignment with the optical via for receiving the light. The assembly may further include VCSELs (vertical cavity surface emitting lasers) and photodiodes as OE elements, and interconnect elements for attaching the assembly to an additional level of packaging. The interconnect elements may include C4s, and compressions bond pads. Further, at least one of the OE elements may be a laser diode driver and transimpedance (LDD/TIA) element, the LDD/TIA element includes circuitry, and the wiring is positioned between the LDD/TIA element and the microlenses for electrically connecting the LDD/TIA element to interconnect elements. In another related aspect, the assembly may further include a carrier for interposing between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board, and the carrier electrically connects first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. Additionally, in a related aspect, the carrier may include a recessed portion for housing the OE elements. The carrier may be positioned between the wiring of the silicon layer and a circuit board and electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. In another related aspect, a carrier and thermal sink interposer may be positioned over the OE elements and in thermal contact with the OE elements. In a further related aspect, a carrier and thermal sink interposer may be positioned over the OE elements and in thermal contact with the OE elements, and the carrier may include an alignment feature for positioning the carrier in mating relation with the optical coupling layer. In another related aspect, at least one semiconductor element may be attached to a carrier, and the carrier is electrically connected to the wiring of the silicon layer and a circuit board. In another related aspect, the semiconductor element is selected from a group comprising: a processor and an application specific integrated circuit (ASIC) chip. In a relate aspect, the assembly of claim1further includes at least one additional silicon layer including active devices connected to the wiring of the silicon layer and a carrier, the carrier electrically connected to the wiring of the silicon layer and a circuit board.

In another aspect of the invention, an optoelectronic (OE) package or system for semiconductor fabrication includes a silicon layer with wiring. The silicon layer defines at least one optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements is positioned in optical alignment with the optical via for receiving the light. A carrier interposes between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board, and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board. In a related aspect, at least one of the OE elements is a laser diode driver and transimpedance (LDD/TIA) element. The LDD/TIA element includes circuitry, and the wiring is positioned between the LDD/TIA element and the microlenses for electrically connecting the LDD/TIA element to interconnect elements. In a related aspect, the carrier includes a recessed portion for housing the OE elements. The assembly may also include a thermal sink interposer positioned over the OE elements and in thermal contact with the OE elements. In a related aspect, the assembly may further include a thermal sink interposer positioned over the OE elements and in thermal contact with the OE elements. The carrier includes an alignment feature for positioning the carrier in mating relation with the optical coupling layer. The assembly may further comprise at least one additional silicon layer including active devices connected to the wiring of the silicon layer and the carrier.

In another aspect of the invention, a method for assembling or packaging a semiconductor or chip includes: fabricating a silicon layer with wiring, the silicon layer defining at least one optical via for allowing light to pass therethrough; bonding an optical coupling layer to the silicon layer, the optical coupling layer including a plurality of microlenses for focusing and or collimating the light through the optical via; coupling a plurality of OE elements to the silicon layer and the OE elements electrically communicating with the wiring; positioning at least one of the OE elements in optical alignment with the optical via for receiving the light; and interposing a carrier between electrical interconnect elements, and positioning the carrier between the wiring of the silicon layer and a circuit board and electrically connecting first interconnect elements to the wiring of the silicon layer and second interconnect elements to the circuit board. The method may further include positioning a thermal sink interposer over the OE elements and in thermal contact with the OE elements. In a related aspect, the method may further include connecting at least one additional silicon layer including active devices connected to the wiring of the silicon layer and the carrier.

DETAILED DESCRIPTION

In an illustrative embodiment of the present invention, referring toFIG. 1, an integrated optoelectric (OE) package or assembly10is depicted and may be fabricated using standard complementary metal-oxide-semiconductor (CMOS) processes. The OE assembly10includes a silicon substrate14that contains wiring layers18of fine wiring and, in an alternative embodiment, electrical circuitry. The fine wiring18interconnects OE arrays22which in the embodiment ofFIG. 1is an array of vertical cavity surface emitting lasers (VCSEL) or photo diode (PD) arrays, herein collectively referred to as the OE arrays22. The OE arrays22communicate with laser diode drivers (LDD) and transimpedance amplifiers (TIAs) collectively referred to with reference numeral26. Dedicated wiring of the fine wiring18route signals from the LDDs and TIAs26to pads30have C4 bumps34or other interconnect elements.

A through hole40(or optical via) is fabricated in the substrate. The hole40enables light42to pass from the OE device to a microlens array44on the substrate14. The through hole40is, for example, 50 to 200 microns in diameter, however smaller or larger hole sizes are possible and may be fabricated using an etch process such as, Bosch™® etch. As an alternative to individual holes (one hole/OE source or detector region), a through slot which spans all OE source/detector regions of a particular OE array may be fabricated. The microlens array44functions to collimate or focus the light to and from the OE arrays22. The glass microlens array44wafer may have a thickness of 100 to 1000 microns

In the embodiment of the present invention depicted inFIG. 1, a method for manufacturing the integrated optoelectric (OE) package or assembly10includes the steps below (which are not shown in the drawings). After silicon wiring layers (resulting in wiring layers18in the substrate14) have been fabricated on a silicon wafer, a through hole (or optical via) is fabricated (shown as hole40on the substrate14). The hole40enables light to pass from the OE device to a microlens array (shown as lens array44on the substrate14). The through hole40is for example, 50 to 200 microns in diameter however smaller and larger sizes are possible and may be fabricated using an etch process such as, Bosch™® etch. The silicon wafer is then attached to a temporary handling wafer, and is ground and polished to a thickness of between about 10 to 200 microns. After polishing, the silicon wafer may be further thinned by chemical etch (for example, using Si anisotropic etching, for example, TMAH (tetramethylammonium hydroxide) or KOH (potassium hydroxide) etching), leaving the Si wiring and Si circuitry on the glass handler. When the Si wiring is left on the glass, the high speed electrical performance of the wiring is improved. Also, by leaving the Si wiring and circuitry on the glass handler, there is no need to fabricate the optical via or optical window since all bulk Si (other than the wiring and circuitry) is removed. The silicon wafer is then transferred and attached to a glass wafer which contains microlenses. The glass wafer could contain microlenses of spherical or aspherical shapes. The microlenses could be refractive or diffractive or a combination. Instead of glass other optically transparent materials could be used such as InP or GaAs (indium phosphorus or gallium arsenide), or transparent plastic. A microlens array functions to collimate or focus the light to and from OE elements (OE arrays22). The temporary handling wafer is then removed exposing the silicon wiring and pads. The wafer may then be bumped by attaching C4 balls (shown as solder balls34on the substrate14), or other interconnect elements (for example, pins, or columns) may be attached, resulting in the silicon substrate14. The next step in the fabrication process is to attach OE devices to the substrate14. A VCSEL array (vertical cavity surface emitting laser diode array) or a PD array (photodiode array) is bonded to the silicon substrate using standard flip chip bonding tools (such as SUSS® Microtech flip chip bonder). The OE to silicon chip join may consist of micro C4s solder balls, compression bonds, or other interconnects. The LDD, TIA, and the OE may be underfilled to protect and secure the chip joins to complete the fabrication of the OE assembly10. Other processing/manufacturing sequences of the above individual steps may be used to generate the OE assembly10which are within the scope and spirit of the present invention.

The silicon wafer may be fabricated using standard CMOS processes. Alternatively other device substrates could be used such as SiGe, GaAs, or silicon on insulator (SOI). The bonding of the glass lens wafer to the silicon is performed using standard wafer to wafer bonding tools. An alignment accuracy of +/−1 micron is obtained.

Referring toFIG. 2a, the OE assembly10includes a 2×12 array of microlenses. It is understood that other lens arrangements are possible, such as a 1×12 array, a 4×12 array or larger two dimensional arrays of lenses.

FIG. 2bshows a bottom view of the OE assembly10with the LDD/TIA elements26removed. The interconnect pads30are bumped with C4 balls34as shown inFIG. 1. The interconnect pads30provide the connection between the OE assembly10and a next level of packaging. High density wiring18connects the pads to the LDDs and TIAs chips48. The LDD and TIAs chips48are connected to pads30on which the OE device10is mounted. The through hole optical via40allows light to pass to the microlenses44. Alternatively, it may be desirable, in view of high frequency electrical signal integrity, to control the electrical impedance and balance the timing skew between different channels between the pads30of the circuitry on the LDD or TIA chip48(input/interconnect pads), and the pads30connecting the OE10to another device (OE ouput pads). One way to control the electrical impedance and balance the trimming skew is by minimizing the electrical signal lines length difference between the channels in a layout circuit wiring. Another optimization includes minimizing the area of the LDD and TIA circuitry layout on the chip48, which may involve placing the individual LDD/TIA channel circuitry on the same pitch as the OE pads30or OE diodes.

Referring toFIG. 2c, a VCSEL array22is shown having the OE10with a source region52which emits light. The pads30interconnect the source region52to silicon drive circuitry. The arrangement of pads may be similar for the photodiode (PD) arrays22. It is understood that the OE lens array44(and OE devices) may be multidimensional, for example a 2×12, 4×12 or a larger array of active elements.

Referring toFIG. 3, in another embodiment of the invention, a package70includes the OE assembly10mounted on a carrier60. The carrier60may be, for example, an organic laminate, ceramic, Silicon, or other substrate material. The device drivers, i.e., the LDD drivers/TIA and OE arrays22, on the OE assembly10protrude into a cavity64on the carrier60. C4 balls34interconnect the OE assembly10to the carrier60. The C4 interconnects34may be underfilled to strengthen and protect the integrity of the join. A heat spreader68is positioned at the bottom of the cavity64. The heat spreader68may be used to transfer heat from the OE10and for example, CMOS devices, to the side of the package70for removal by, for example, an air cooled heat sink, a water cooled heat sink, or by other standard heat removal means. The carrier60may be further attached to a printed circuit board (PCB)72by means of a ball grid array (BGA) or land grid array (LGA) interconnect76. The carrier60also serves as an electrical and mechanical interposer. The OE assembly10is used to form a custom number of optical channels, with the carrier60serving as an electrical and mechanical interposer between the OE assembly10and the PCB72.

Referring toFIG. 4, another embodiment of the invention includes a package80including an embodiment of an OE assembly100wherein features consistent with the OE assembly10shown inFIG. 1have the same reference numerals. The OE assembly100includes the silicon substrate14, OE arrays22, and an attached lens array44. In this case the LDD and TIA devices26are attached to the carrier60. It is understood the carrier may be organic, ceramic, silicon, or other suitable material. It is understood that a number of OE arrays22may be extended beyond two arrays. It is also understood that a combination VCSEL and photodiode arrays22may be used on the OE assembly100to provide a transceiver function.

Referring toFIG. 5, in another embodiment of the invention, a package90includes the OE assembly10(shown inFIGS. 1 and 3) and an additional device attached to the carrier substrate60. The additional device may be a processor or ASIC (application specific integrated circuit) chip78, or another component. In some cases, it is highly desirable to place the additional device78as close as possible to the OE assembly10to minimize the electrical power and cost by incorporating some or all of the LDD circuitry26within the additional device78. In alternative cases, it may be desirable to use standard (non-custom) additional device(s) where the needed LDD/TIA26circuitry requirements are in the OE assembly10.

Referring toFIG. 6, another embodiment of a package120includes the OE assembly10rotated one hundred and eighty degrees and attached to a carrier substrate104. In the embodiment ofFIG. 6, the carrier substrate includes an optional recessed region, including an electrical interconnection in the recessed region to connect the OE assembly to the carrier104. Alternatively (not shown), the carrier could have only a hole or rectangular opening and no recessed region, in this case, electrical interconnect is done on the bottom side of the carrier. Also, an additional interposer (not shown) could be used to create a larger gap between the PCB and the OE assembly.

The light42is orientated downward towards the printed circuit board (PCB)72. Optical waveguides106are attached to the top surface of the PCB72. A lens array112is positioned on top of the waveguides106which couples the light from the OE assembly10to the waveguide cores. Also, waveguide turning mirrors108reflect the light42ninety degrees. The light42within the optical waveguides106may be conveyed across the PCB72to other optical assemblies or to an edge of the printed circuit board for interconnection with an optical backplane or optical fiber cables. A heat spreader116in positioned on the top of the carrier104. The thermal interface material69is used to connect the heat spreader116to the LDDs/TIAs22, and OE arrays22. The heat spreader116may be connected to a top side heat sink to remove heat from the package120.

Referring toFIGS. 7a,7b, and7c, the OE assembly10is attached to the carrier60and a mating waveguide/optical connector124. Referring toFIG. 7a, an optical cable126is connected to the waveguide/optical connector124. The waveguide cable126may be a polymer and incorporates turning mirror elements128, a lens array44, and a connector housing132.

Referring toFIG. 7b, an OE assembly130on the carrier60incorporates an alignment frame134. The alignment frame134is passively aligned to the lens OE assembly130lens array144, and then glued into place. During fabrication of the lens array144, additional features may be formed which can be used to accurately position the alignment frame134. For example, a step136is formed in the lens array144, for the alignment frame134to reference. Thereby, after assembly the alignment frame134is accurately referenced to the lens array144and the devices26to specified semiconductor tool tolerances, such as, within a 1 or 2 micron alignment tolerance. The OE assembly130is mated to the optical connector124as shown inFIG. 7cforming a package140. The optical connector124seals the optical elements, i.e., the turning mirrors128, the waveguide cable126and connector132from dust or other contaminates.

Referring toFIG. 8, an alternate OE assembly150according to the invention includes wiring or circuitry18on top of the silicon substrate14interconnecting the VCSEL/PDs22, and LDD/TIA26devices. The lens array44is aligned and attached to the silicon substrate or carrier14. The silicon substrate/carrier14contains through silicon vias152which connect the top side wiring14to bottom side pads30. C4 bumps34are attached to the pads30. A stiffener frame154and a heat spreader156are positioned on top of one another. The head spreader156conducts heat from the LDD/TIA26, and PDs22and spreads it laterally. A conventional heat sink may be attached to the top to cool the assembly150.

Referring toFIG. 9, where like features have the same reference numerals as the embodiments of the invention shown inFIGS. 1,3-8, another embodiment of an OE package160includes through silicon vias152in the embodiment of the OE assembly150shown inFIG. 8. The OE assembly150is attached to a carrier substrate162. In the OE package160, shown inFIG. 9, the light42is directed downward towards the PCB72.

Referring toFIG. 10, where like features have the same reference numerals as the embodiments of the invention shown inFIGS. 1,3-9, another embodiment of an OE package170includes the LDDs/TIAs26, and OE arrays22aare attached to a first silicon substrate/carrier174awhich is thicker (e.g., between 100 to 800 microns thick) than in the previous embodiments shown inFIGS. 3-6. An optical coupling glass wafer is reversed and the microlens176surface faces the OE arrays22. The glass lens array176may be thicker than in previous embodiments, since the light42passes through the glass substrate176in a collimated manner. A second silicon substrate174bincludes wiring18and through silicon vias152as shown inFIGS. 8 and 9. The second silicon substrate174bis used to redistribute the signals from fine interconnect pads on the first silicon substrate174ato larger pads30(and larger pitch) on the second silicon substrate174b. Further, the second silicon substrate174bconducts heat from the first silicon substrate174alaterally to a heat spreader/alignment frame172. The heat spreader/alignment frame172is bonded to the second silicon substrate174b. A heat sink may be attached to the heat spreader/alignment frame172to cool the OE assembly180. The heat spreader/alignment frame172may also serve as an alignment frame for mating with an optical connector. The components on the OE assembly180may be underfilled or sealed178as shown inFIG. 10. The sealing178serves to strengthen the components and protect the internal bond pads from the environment.

Referring toFIG. 11, another embodiment of an OE assembly200in an OE package210is similar to the embodiment shown inFIG. 10, however, the OE assembly200includes LDD and TIA circuitry imbedded in the first silicon substrate174a. In some cases, it is desirable to place the LDD and TIA devices as close as possible to the OE devices22to minimize the electrical power and cost by incorporating the circuitry in the first silicon substrate174a. In an alternative embodiment, the LDD/TIA circuitry is attached to the first silicon substrate. Other embodiments may also include OE devices being two dimensional, e.g., containing 2×12 arrays, 4×12 arrays or more devices per OE substrate.

FIG. 12shows an OE assembly220of an OE package230with a thicker silicon substrate224. A lens array232is shortened in comparison to previous embodiments, thereby exposing a top portion of the silicon substrate224. The exposed top portion of the silicon substrate224enables a heat spreader234to be directly attached to the top of the silicon substrate224, and to be referenced laterally by reference features233in the lens array232. By attaching the heat spreader234to the top of the silicon substrate224, heat may be conducted away from active devices, for example, OE arrays22and drivers/TIAs26, and distributed to a top side heat sink/spreader234.

Referring toFIG. 13, another embodiment of an OE package240includes the OE assembly shown inFIG. 12, however, in the OE package240, a second silicon spacer242(or silicon frame) having silicon vias there through is attached to the first silicon substrate224. In this case a cavity is not required in the organic or ceramic carrier and the OE assembly may be attached to a flat carrier as shown.

Thereby, the OE packages and OE assemblies shown in the embodiments of the invention, integrate the OE transceiver elements in a compact space. Thereby, the present invention provides a system and assembly of integrated packaging, and a method of integrated packaging for reducing the size and lowering the cost of optical transceivers. More specifically, the optoelectronic drivers and receivers are processed and packaged with optical coupling elements, and OE (VCSEL and PD) elements using a wafer scale packaging technology, together with 3D stacking, for integrating the elements in a compact space, resulting in improved density of components and lower cost manufacturing or fabrication.

While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated herein, but falls within the scope of the appended claims.