Memory management of local variables

A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates generally to processors and more particularly to managing local variables used by a processor.

2. Background Information

Many types of electronic devices are battery operated and thus preferably consume as little power as possible. An example is a cellular telephone. Further, it may be desirable to implement various types of multimedia functionality in an electronic device such as a cell phone. Examples of multimedia functionality may include, without limitation, games, audio decoders, digital cameras, etc. It is thus desirable to implement such functionality in an electronic device in a way that, all else being equal, is fast, consumes as little power as possible and requires as little memory as possible. Improvements in this area are desirable.

BRIEF SUMMARY

In some embodiments, a processor preferably comprises a processing core that generates memory addresses to access a main memory and on which pluralities of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

NOTATION AND NOMENCLATURE

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The subject matter disclosed herein is directed to a programmable electronic device such as a processor having memory in which “local variables” associated with a stack-based language (e.g., Java) and pointers associated with the local variables may be stored. The term “local variables” refers to temporary variables used by a method that executes on the processor. Multiple methods may run on the processor and each method preferably has its own set of local variables. In general, local variables have meaning only while their associated method is running. The stack-based language may comprise Java Bytecodes although this disclosure is not so limited. In Java Bytecodes, the notion of local variables (“LVs”) is equivalent to automatic variables in other programming languages (e.g., “C”) and other termed variables in still other programming languages.

The following describes the operation of a preferred embodiment of such a processor in which the methods and local variables may run and be used. Other processor architectures and embodiments may be used and thus this disclosure and the claims which follow are not limited to any particular type of processor. Details regarding the storage of the local variables and the associated pointers follow the description of the processor.

The processor described herein is particularly suited for executing Java™ Bytecodes, or comparable code. As is well known, Java is particularly suited for embedded applications. Java is a relatively “dense” language meaning that on average each instruction may perform a large number of functions compared to various other programming languages. The dense nature of Java is of particular benefit for portable, battery-operated devices that preferably include as little memory as possible to save space and power. The reason, however, for executing Java code is not material to this disclosure or the claims that follow.

Referring now toFIG. 1, a system100is shown in accordance with a preferred embodiment of the invention. As shown, the system includes at least two processors102and104. Processor102is referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor104may be referred to as a Main Processor Unit (“MPU”). System100may also include memory106coupled to both the JSM102and MPU104and thus accessible by both processors. At least a portion of the memory106may be shared by both processors meaning that both processors may access the same shared memory locations. Further, if desired, a portion of the memory106may be designated as private to one processor or the other. System100also includes a Java Virtual Machine (“JVM”)108, compiler110, and a display114. The JSM102preferably includes an interface to one or more input/output (“I/O”) devices such as a keypad to permit a user to control various aspects of the system100. In addition, data streams may be received from the I/O space into the JSM102to be processed by the JSM102. Other components (not specifically shown) may be included as desired. As such, while system100may be representative of, or adapted to, a wide variety of electronic systems, an exemplary electronic system may comprise a battery-operated, mobile cell phone such as that shown inFIG. 2. As shown inFIG. 2, a mobile communications device includes an integrated keypad412and display414. The JSM102and MPU104noted above and other components may be included in electronics package410which may be coupled to keypad410, display414, and radio frequency (“RF”) circuitry416which may be connected to an antenna418.

Referring again toFIG. 1, as is generally well known, Java code comprises a plurality of “Bytecodes”112. Bytecodes112may be provided to the JVM108, compiled by compiler110and provided to the JSM102and/or MPU104for execution therein. In accordance with a preferred embodiment of the invention, the JSM102may execute at least some, and generally most, of the Java Bytecodes. When appropriate, however, the JSM102may request the MPU104to execute one or more Java Bytecodes not executed or executable by the JSM102. In addition to executing Java Bytecodes, the MPU104also may execute non-Java instructions. The MPU104also hosts an operating system (“O/S”) (not specifically shown), which performs various functions including system memory management, the system task management that schedules the JVM108and most or all other native tasks running on the system, management of the display114, receiving input from input devices, etc. Without limitation, Java code may be used to perform any one of a variety of applications including multimedia, games or web based applications in the system100, while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU104.

The JVM108generally comprises a combination of software and hardware. The software may include the compiler110and the hardware may include the JSM102. The JVM may include a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor102.

In accordance with preferred embodiments of the invention, the JSM102may execute at least two instruction sets. One instruction set may comprise standard Java bytecodes. As is well-known, Java is a stack-based programming language in which instructions generally target a stack. For example, an integer add (“LADD”) Java instruction pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack. As will be explained in more detail below, the JSM102comprises a stack-based architecture with various features that accelerate the execution of stack-based Java code.

Another instruction set executed by the JSM102may include instructions other than standard Java instructions. In accordance with at least some embodiments of the invention, such other instruction set may include register-based and memory-based operations to be performed. This other instruction set generally complements the Java instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“C-ISA”). By complementary, it is meant that the execution of various “complex” Java Bytecodes may be substituted by “micro-sequences” using C-ISA instructions that permit address calculation to readily “walk through” the JVM data structures. Such micro-sequences also may use Bytecode instructions in addition to C-ISA instructions. The execution of Java may be made more efficient and run faster by replacing some sequences of Bytecodes by preferably shorter and more efficient sequences of C-ISA instructions. The two sets of instructions may be used in a complementary fashion to obtain satisfactory code density and efficiency. As such, the JSM102generally comprises a stack-based architecture for efficient and accelerated execution of Java bytecodes combined with a register-based architecture for executing register and memory based C-ISA instructions. Both architectures preferably are tightly combined and integrated through the C-ISA.

FIG. 3shows an exemplary block diagram of the JSM102. As shown, the JSM includes a core120coupled to data storage122and instruction storage130. The core may include one or more components as shown. Such components preferably include a plurality of registers140, three address generation units (“AGUs”)142,147, micro-translation lookaside buffers (micro-TLBs)144,156, a multi-entry micro-stack146, an arithmetic logic unit (“ALU”)148, a multiplier150, decode logic152, and instruction fetch logic154. In general, operands may be retrieved from data storage122or from the micro-stack146, processed by the ALU148, while instructions may be fetched from instruction storage130by fetch logic154and decoded by decode logic152. The address generation unit142may be used to calculate addresses based, at least in part on data contained in the registers140. The AGUs142may calculate addresses for C-ISA instructions as will be described below. The AGUs142may support parallel data accesses for C-ISA instructions that perform array or other types of processing. The AGU147couples to the micro-stack146and may manage overflow and underflow conditions in the micro-stack preferably in parallel. The micro-TLBs144,156generally perform the function of a cache for the address translation and memory protection information bits that are preferably under the control of the operating system running on the MPU104.

Referring now toFIG. 4, the registers140may include 16 registers designated as R0–R15. Registers R0–R3, R5, R8–R11and R13–R14may be used as general purposes (“GP”) registers usable for any purpose by the programmer. Other registers, and some of the GP registers, may be used for specific functions. For example, registers R4and R12may be used to store two program counters. Register R4preferably is used to store the program counter (“PC”) and register R12preferably is used to store a micro-program counter (“micro-PC”). In addition to use as a GP register, register R5may be used to store the base address of a portion of memory in which Java local variables may be stored when used by the currently executing Java method. The top of the micro-stack146may be referenced by the values in registers R6and R7. The top of the micro-stack has a matching address in external memory pointed to by register R6. The values contained in the micro-stack are the latest updated values, while their corresponding values in external memory may or may not be up to date. Register R7provides the data value stored at the top of the micro-stack. Registers R8and R9may also be used to hold the address index 0 (“AI0”) and address index 1 (“AI1”), as will be explained below. Register R14may also be used to hold the indirect register index (“IRI”). Register R15may be used for status and control of the JSM102.

Referring again toFIG. 3, as noted above, the JSM102is adapted to process and execute instructions from at least two instruction sets and one or more methods comprising such instructions. One instruction set includes stack-based operations and the second instruction set includes register-based and memory-based operations. The stack-based instruction set may include Java Bytecodes. Java Bytecodes pop, unless empty, data from and push data onto the micro-stack146. The micro-stack146preferably comprises the top n entries of a larger stack that is implemented in data storage122. Although the value of n may be vary in different embodiments, in accordance with at least some embodiments, the size n of the micro-stack may be the top eight entries in the larger, memory-based stack. The micro-stack146preferably comprises a plurality of gates in the core120of the JSM102. By implementing the micro-stack146in gates (e.g., registers) in the core120of the processor102, access to the data contained in the micro-stack146is generally very fast, although any particular access speed is not a limitation on this disclosure. The second register-based, memory-based instruction set may comprise the C-ISA instruction set introduced above. The C-ISA instruction set preferably is complementary to the Java bytecode instruction set in that the C-ISA instructions may be used to accelerate or otherwise enhance the execution of Java Bytecodes.

The ALU148adds, subtracts, and shifts data. The multiplier150may be used to multiply two values together in one or more cycles. The instruction fetch logic154generally fetches instructions from instruction storage130. The instructions may be decoded by decode logic152. Because the JSM102is adapted to process instructions from at least two instruction sets, the decode logic152generally comprises at least two modes of operation, one mode for each instruction set. As such, the decode logic unit152may include a Java mode in which Java instructions may be decoded and a C-ISA mode in which C-ISA instructions may be decoded.

The data storage122generally comprises data cache (“D-cache”)124and a data random access memory (“D-RAMset”)126. Reference may be made to copending application U.S. Ser. No. 09/591,537 filed Jun. 9, 2000, U.S. Ser. No. 09/591,656 filed Jun. 9, 2000, and Ser. No. 09/932,794 filed Aug. 17, 2001, all of which are incorporated herein by reference. The stack (excluding the micro-stack146), arrays and non-critical data may be stored in the D-cache124, while Java local variables and associated pointers as explained below, as well as critical data and non-Java variables (e.g., C, C++) may be stored in D-RAMset126. The instruction storage130may comprise instruction RAM (“I-RAMset”)132and instruction cache (“I-cache”)134. The I-RAMset132may be used to store “complex” micro-sequenced Bytecodes or micro-sequences or predetermined sequences of code. The I-cache134may be used to store other types of Java Bytecode and mixed Java/C-ISA instructions.

In accordance with a preferred embodiment of the invention, at least some applications executed by the JSM102comprise one or more methods. A “method” includes executable instructions and performs one or more functions. Other terms for “method” may include subroutines, code segments, and functions, and the term should not be used to narrow the scope of this disclosure.

A method (the “calling” method) may call another method (the “called” method). Once the called method performs its function, program control returns to the calling method. Multiple hierarchical levels of methods are possible as illustrated inFIG. 5which illustrates the interaction between three methods (Method A, Method B, and Method C). For purposes of the example ofFIG. 5, method A calls method B and method B calls method C. As such, method A is the calling method for method B which is the called method relative to method A and only while method A is executing. Similarly, method B is the calling method relative to method C which is considered the called method relative to method B.

A method may have one or more “local variables,” as explained previously. Local variables may be used to temporarily store data or other information as the method performs its task(s). The local variables preferably are specific to the method to which the variables pertain. That is, method A's local variables (“LVA”) are accessible generally by only method A and have meaning only to method A. Once method A completes, the method A local variables become meaningless. Similarly, LVB and LVC comprise local variables associated with methods B and C, respectively. Java Bytecodes refer to local variables using an index. The JVM maintains a local variables pointer (“PTR LV”) which points to the base address of the memory containing the current method's local variables. To access a particular local variable, a suitable index value is added to the base address to obtain the address of the desired local variable.

FIG. 5generally shows the state of the D-RAMset126in accordance with a time sequence of events500,510, and520as each method B and C is invoked. In sequence500, method A is invoked and storage space502is allocated for its local variables (LVA). A base pointer (PTR LVA)504also is determined or selected to point to the base portion of LVA storage space502. Using the pointer PTR LVA, references may be made to any local variable within method A's local variable set502by computing an index or offset to the PTR LVA value.

Although a plurality of methods may run on the JSM102, typically only one method is “active” at a time having its instructions actively being executed by the JSM102. The base pointer of the currently active method preferably is stored in register R5as noted previously. In general, the base pointer for the active method may be computed by the JVM108while executing the invoke bytecode of the active method. This bytecode is a complex bytecode executed by a micro-sequence or by the JVM.

Sequence510depicts the state of the D-RAMset126when method A calls method B. In accordance with the preferred embodiments of the invention, the local variables (LVB) associated with method B are stacked in storage space512generally adjacent LVA (“on top of” LVA when viewed as inFIG. 5). Following arrow505, the base pointer for LVA (PTR LVA) preferably is also stored in the D-RAMset126adjacent (e.g., below) the LVB data at location504A. Thus, the two local variable sets LVA and LVB may be separated by the base pointer (PTR LVA) for LVA and possibly other data. Once the base pointer504for LVA is stored adjacent (below) the reserved space for the LVB data set502, register R5is updated (i.e., loaded) with a base pointer514for use with the LVB data set.

The JSM102may load LVA's base pointer504into location504A by executing a store instruction to store LVA's base pointer at location504A. Location504A may be determined as the location pointed to by the base pointer of LVB (PTR LVB) minus 1. That is, the set of local variables associated with method B is mapped adjacent the pointer associated with method A's local variables. The value of PTR LVB may be determined as the sum of the value for PTR LVA504, the size of LVA502, and a value p. The value p may be an integer that is appropriate to take into account the size of the pointer itself and thus may be more than 4 bytes. Other data may be present between the storage areas for LVA502and LVB512.

Following arrow507to time sequence520, when method C is invoked (called by method B), the base pointer for method B (PTR LVB) is stored in location514A which may be on top of LVB and below PTR LVC as shown and register R5is loaded with the base pointer524(PTR LVC) to the base of the LVC data set522. Method C's local variables (LVC) are allocated to storage space522which generally is adjacent (on top of) LVB512and PTR LVB514A as shown. The PTR LVB value is stored in location514A according to a similar calculation as that described above.

FIG. 6illustrates the return process as each method (Methods C and then B) completes and returns to its calling method (methods B and then A). Beginning with time sequence530in which the local variable frame comprises LVA, LVB, and LVC along with pointers PTR LVA and PTR LVB for LVA and LVB, method C completes. Control returns to method B and LVB's base pointer is loaded from location514A into register R5as shown by arrow519at time sequence532by accessing PTR LVB through a load instruction that include a fixed offset from PTR LVC as a target address. Then, when method B completes, LVA's pointer (PTR LVA) is loaded into register R5from location504A as illustrated by arrow521at time sequence534. The base pointers may be retrieved from their locations in data cache126by loading the value located at the location pointed by the currently active method's base pointer minus an offset (e.g., 1).

In accordance with preferred embodiments of the invention, the D-RAMset126is configured to provide any one or more or all of the following properties. The implementation of the D-RAMset126to provide these properties is explained in detail below. The local variables and pointers stored in the D-RAMset126preferably are “locked” in place meaning that, although the D-RAMset126is implemented as cache memory, eviction of the local variables generally can be prevented in a controlled manner. The locking nature of the D-RAMset126may be beneficial while a method executes to ensure that no cache miss penalty is incurred. Additionally, write back of valid, dirty local variables to main memory106is avoided in at least some situations (specified below). Further, mechanisms can be employed in the event that the D-RAMset126has insufficient capacity to accommodate all desired local variables. Further still, once a method has completed, the portion of the D-RAMset allocated for the completed method's local variables remains marked as “valid.” In this way, if and when new methods are executed and re-use the same RAMset space (such as that described in one or more of the copending applications mentioned above and incorporated herein by reference), local variables associated with such new methods will be mapped to the same portion of the D-RAMset. If the RAMset lines are already marked as valid, access to those new local variables may not generate any misses. Retrieval of data from memory is unnecessary because the local variables only have significance while a method executes and a newly executing method first initializes all of its local variables before using them. Not generating misses and thus avoiding fetching lines from external memory reduces latency. After a relatively short period of time following the start of a Java program execution, all relevant lines of the RAMset are marked as valid and accesses to local variables of newly called methods do not generate misses, thereby providing superior performance of a “0-wait state memory.” Furthermore, the cache properties of RAMset allow discarding or saving of the data in main memory whenever required.

In accordance with a preferred embodiment of the invention, the local variables (LVA-LVC) and associated pointers (PTR LVA-PTR LVC) may be stored in D-RAMset126. The D-RAMset126may be implemented in accordance with the preferred embodiment described below and in copending applications entitled “Cache with multiple fill modes,” filed Jun. 9, 2000, Ser. No. 09/591,656; “Smart cache,” filed Jun. 9, 2000, Ser. No. 09/591,537; and publication no. 2002/0065990, all of which are incorporated herein by reference.

As described in greater detail below, in the preferred embodiment, the data storage122(FIG. 3) preferably comprises a 3-way cache with at least one cache way comprising D-RAMset126. The D-RAMset (or simply “RAMset”) cache126may be used to cache a contiguous block of memory (e.g., local variables and pointers as described above) starting from a main memory address location. The other two cache ways124may be configured as RAMset cache memories, or use another architecture as desired. For example, the data storage122may be configured as one RAMset cache126and a 2-way set associative cache124. As such, the data storage122generally comprises one or more forms of cache memory. The instruction storage130may be similarly configured if desired.

In operation, the processor's core102may access main memory106(FIG. 1) within a given address space. If the information at a requested address in main memory106is also stored in the data storage122, the data is retrieved from the data cache124,126. If the requested information is not stored in data cache, the data may be retrieved from the main memory106and the data cache124,126may be updated with the retrieved data.

FIG. 7illustrates a more detailed block diagram of the data storage122in accordance with a preferred embodiment with a RAMset cache and a two-way set associative cache. A cache controller222may control operation of the data storage122. Cache controller222may include a plurality of status bits including, without limitation, the following four status bits: RAM_fill_mode224, Cache_Enable226, DM/2SA228and Full_RAM_base230as well as other bits that are not specifically shown inFIG. 7. The two-way associative cache may be configured as a direct map and its other way configured as a RAMset. Alternatively, the two-way set associative cache may be configured as two additional RAMsets depending on cache control bit DM/2SA238and FULL_RAM_Set_base230as described in at least one of the documents incorporated herein by reference. However, the preferred configuration comprises a single RAMset coupled to a standard data cache. The RAMset is not limited in size, nor must the RAMset have the same size as the other cache way. Therefore, if another RAMset is needed for capacity reasons, a single RAMset with a larger capacity may be preferred.

As shown, cache controller222couples to Full_Set_Tag registers232(individually referenced as registers232athrough232c), Global_Valid bits234(individually referenced as bits234athrough234c), tag memories236(individually referenced as tag memories236band236c), valid entry bit arrays237(individually referenced as bit arrays237athrough237c) and data arrays238(individually referenced as data arrays238athrough238c). Comparators240(individually referenced as comparators240athrough240c) may couple to respective Full_Set_Tag registers232. Comparators242(individually referenced as comparators242band242c) couple to respective tag memories236. Output buffers244(individually referenced as buffers244athrough244c) may couple to respective data arrays238. Hit/Miss logic246(individually referenced as logic246athrough246c) may couple to comparators240, global valid bits234, valid bits237, RAM_fill_mode bit224and Cache_Enable bit226.

In operation, data storage122may be configured using the control bits224,226,228and230. The Cache_Enable226allows the data storage to be enabled or disabled, as in standard cache architecture. If the data storage122is disabled (e.g., Cache Enable=0), data read accesses may be performed on the main memory106without using the data storage122. If the data storage122is enabled (e.g., Cache_Enable=1), data may be accessed in the data storage122, in cases where such data is present in the data storage. If a miss occurs, a line (e.g., 16 bytes) may be fetched from main memory106and provided to the core120.

The size of the data array238amay be different than the size of the data arrays238b, cfor the other ways of the cache. For illustration purposes and without limiting this disclosure in any way, it will be assumed that data arrays238band238care each 8 Kbytes in size, configured as 512 lines, with each line holding eight two-byte data values. Data array238amay be 16 Kbytes in size, configured as 1024 lines, each line holding eight, two byte data values. The ADDR[L] signals may be used to address one line of the data array238and valid bit array237(and tag memory236, where applicable). Accordingly, for the 1024-line first way, ADDR[L] may include 10 bits [13:4] of an address from the core. For the 512-line second and third ways, ADDR[L] may include 9 bits [12:4] of an address from the core. The ADDR[H] signals define which set is mapped to a line. Thus, assuming a 4 Gbyte address space, ADDR[H] uses bits [31:14] of an address from the core for the first way and uses bits [31:13] for each of the second and third ways of the cache130.

The tag memories236and comparators242may be used for a 2-way set associative cache (e.g., D-cache124inFIG. 3). When the core120performs a memory access, the tag memories236are accessed at the low order bits of the address (ADDR[L]). The tag memory locations store the high order address bits of the main memory address of the information stored in a corresponding line of the data array238. These high order address bits may be compared with the high order address bits (ADDR[H]) of the address from the core120. If the ADDR[H] matches the contents of the tag memory at ADDR[L], a hit occurs if the valid bit associated with the low order bits indicates that the cache entry is valid. If a cache hit occurs, the data from the corresponding data array238at ADDR[L] may be provided to the core120by enabling the corresponding output buffer244. As described below, data from the 2-way cache is presented to the core120if there is a miss in the RAMset cache. By itself, the operation of the 2-way set associative cache and the direct map cache may be conventional and may not be affected by the RAMset cache126. Other cache techniques could also be used in place of the 2-way cache124.

The RAMset cache126preferably stores a contiguous block of main memory106starting at an address defined by the Full_set_tag register232for the RAMset. This contiguous block of information (e.g., local variables/pointers) may be mapped to the corresponding data array238of the RAMset. In at least some embodiments, only the high order bits of the starting address are stored in the Full_set_tag register232.FIG. 8illustrates this mapping for a single RAMset. As shown, the contents of Full_set_tag register232adefine the starting address for a contiguous block of memory cached in data array238a.

Referring again toFIG. 7, a RAMset miss may occur when the high order bits of the address from the core120do not match the contents of the Full_set_TAG register232or the global valid bit is “0”. In either case, when a RAMset miss occurs, the data storage122may behave like conventional, 2-way cache logic. As such, if there is a hit in the 2-way associative cache, then data is presented to the core120from the 2-way set associative cache. Otherwise, the data is retrieved from main memory106, forwarded to the core and loaded into a “victim” entry of the two-way associative cache.

A RAMset hit situation may occur when the high order bits of the address from the core120match the contents of the Full_set_TAG register232and the global valid bit equals “1” (the setting of the global valid bit is described in greater detail below). By default, the RAMset comparison preferably has higher priority than the other cache ways. A hit situation indicates that the requested data is mapped into the RAMset. If the Valid entry bit237corresponding to the line containing the data is set to “1”, comparator240causes hit/miss logic246to generate a “hit-hit” signal because the address hit the RAMset and the data is present in the RAMset. If the corresponding valid bit237of the RAMset entry is “0”, logic240generates a “hit-miss” because the address hit the RAM set, but the data is not yet present in the RAM set. In this latter case, the data may be fetched from main memory106and loaded into the data array238of the RAMset. A hit in the RAMset logic preferably takes precedence over the normal cache logic. The standard logic of the 2-way cache generates a miss when the RAMset logic generates a hit. Information can reside in both the RAMset and the 2-way cache without causing any misbehavior; the duplicated cache entry in the 2-way cache will eventually be evicted by the replacement mechanism of the two-way cache because such data will not be used. When configured as a RAMset, data array238a, b, c can be configured as a local RAM or as a cached segment depending on the setting of a suitable configuration bit. However, even when configured as a local RAM, individual valid bits may be updated and misses do not generate accesses to the external memory.

To configure a RAMset for operation, the Full_set_tag register232preferably is loaded with a start address (set_start_addr) and the RAM_fill_mode bit224is configured to a desired fill mode. The circuitry for filling the cache can be the same as that used to fill lines of the set associative cache. At least one fill mode may be implemented and is referred to as a “line-by-line” fill mode as described below. Other fill modes may be implemented if desired such as the “set fill” mode described in at least one of the documents incorporated by reference.

For the line-by-line fill (RAM_fill_mode=0), the global valid bit34is set to “1” and each of the valid entry bits237is set to “0” when the Full_set_tag register232is loaded with the starting address. At this point, the data array238is empty (it is assumed that the Cache_Enable bit226is set to “1” to allow operation of the data storage122). Upon receiving an address from the core120, a valid entry bit237is selected based on the low order bits of the address. As provided above, if the RAMset is 16 Kbytes in size, organized as an array of 1K×16 bytes, where 16 bytes is equivalent to a block line in the associated 2-way cache, the Full_set_TAG register232may store18bits [31:14] of the starting address (set_start_addr). The address indexing each entry of the RAMset (ADDR[L]) may include 10 bits [13:4] while the data address used to access one data value in the line may include 4 bits [3:0] (assuming data accesses are 1 byte). In Java, local variables comprise four byte entities but, as explained previously, the RAMset may be shared between local variables and other, possibly critical, data. A line of the data array238(at ADDR[L]) is loaded from main memory106each time that a hit-miss situation occurs because (1) the comparator240determines a match between ADDR[H] and Set_start_addr, (2) the Global valid bit34is set to “1” and (3) the valid bit237associated with the line at ADDR[L] is “0”. This situation indicates that the selected line is mapped to the RAMset, but has not yet been loaded into the RAMset's data array238. When the line is loaded into the data array238from main memory106, the valid bit237corresponding to the line is set to “1”.

This loading procedure (resulting in the valid bit being set to indicate the presence of valid data) has the same time penalty as a normal cache line load, but the entry will remain locked in the RAMset (i.e., the valid bit will remain set) and, therefore, the processing device will not be penalized on a subsequent access. As such, the lines used by a completed method remain valid so that re-using the lines by subsequent methods does not necessitate accesses to main memory106. Further, freeing the local variable space for a completed method generally only involves disregarding the relevant base pointer. Further still, there is no need to copy back local variables upon to main memory106upon completion of a method because such extinct local variables are not used any more.

In some situations, the capacity of the D-RAMset126may not be sufficient to hold all desired local variables. In accordance with one embodiment, excess local variables may be stored in the non-D-RAMset data arrays238. In accordance with other embodiments, a larger block of local variables (i.e., larger than just the excess local variables) may be mapped to the non-D-RAMset cache ways. During the “invoke” bytecodes, that initiates a method call, the local variable size of the called method is known by the JVM108. The JVM also knows the total RAMset size (via a readable configuration register) and the RAMset size already utilized. Therefore, based on this information, the JVM may or may not decide to map the new local variable area onto the RAMset. A method may have a large chunk of local variables and not use them on each call. Therefore, mapping those local variables onto the RAMset may force unnecessary RAMset management of the base pointer and saving/restoring of local variables of calling methods or may cause more frequent overflow of a subsequently called method. Instead, the JVM may map the methods with larger chunks of local variables onto the non-RAMset data cache and thus preserve more space in the RAMset for methods with a smaller number of local variables. In some embodiments, many methods may have less than 10 local variables and almost all methods have less than about 40 local variables, but, of course, this is application dependent. For methods with many local variables, the system may map those local variables outside the RAMset avoiding penalizing other methods. This technique is generally transparent for the return mechanism because of the management of the PTR_LV of the calling method.

Upon completion of a method, lines containing that method's local variables may remain marked as valid. As noted above, maintaining such lines marked as valid avoids generating misses in calls of new methods.

While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are exemplary only, and are not intended to be limiting. Many variations and modifications of the invention disclosed herein are possible and are within the scope of the invention. Accordingly, the scope of protection is not limited by the description set out above. Each and every claim is incorporated into the specification as an embodiment of the present invention.