System and method to avoid voltage read errors in open digit line array dynamic random access memories

Selective coupling devices directed by coupling controllers prevent cell plate and/or substrate disturbances from causing memory cell read and refresh errors in open digit line array memory devices. Using selective decoupling devices, when memory cells in an active row store an appreciably unbalanced number of either zeroes or ones, reading the cells generates a voltage transient in the cell plate and/or substrate that can be coupled to a reference digit line because the cell plates and/or substrates of the active sub-array are normally coupled to the cell plates and/or substrates of the reference arrays. By decoupling the cell plate and/or substrate of the active sub-array from the cell plates and/or substrates of the reference arrays, any coupling of the voltage transients to reference digit lines is reduced.

TECHNICAL FIELD

This invention relates to DRAM devices. More particularly, the present invention is directed to DRAM devices employing open digit line array architecture.

BACKGROUND OF THE INVENTION

As is well known in the art and shown inFIG. 1, a DRAM cell100typically comprise a capacitor104and access transistor108pair. One plate of the capacitor104is connected to a common cell plate (not shown) to which all capacitors in that DRAM cell array are connected, a subset of which is shown in FIG.1. The other plate of the capacitor104is coupled to a drain of the access transistor108. The gate of the access transistor108is connected to a word line116which allows all the DRAM cells coupled to each word line116to be activated, while the source of the access transistor108is coupled to a digit line120which the DRAM cell100will read from and write to during memory operations. Activating the gate of the access transistor allows a high voltage charge (Vcc) or low voltage charge (ground) carried by the digit line120to pass to the capacitor104, thus writing the voltage of the digit line120to the capacitor104.

DRAM cell storage technology of this type is understandably transitory in nature: the high or low voltage charge written to the capacitor will eventually dissipate, as charges stored across capacitors are known to do. As also is known in the art, stored charges leak across the dielectric core between the transistor plates, and voltages can leak from the plates through the access transistors to which they are connected. As a result, the contents of DRAM cells typically must be refreshed hundreds of times per second.

A network of sense amplifiers124(FIG. 1) typically are used to refresh the contents of the DRAM cells, each of the sense amplifiers124comparing voltages received on pairs of digit lines120to which each is connected.

The memory cells100are shown inFIG. 1arranged in an open digit line configuration in which each sense amplifier124is coupled to a column of memory cells in one array125and another column of memory cells in another memory array126. Each pair of digit lines120to which each sense amplifier124is connected comprises an active digit line and a reference digit line. The active digit line128is the digit line in one array125to which the access transistors108of the DRAM cells100being refreshed are coupled upon activation of the word lines116activating the gates of the access transistors108. The active digit line is assumed to be the top digit line128in the array125for purposes of the example of FIG.1. The reference digit line132is a digit line connected to a row of DRAM cells100whose contents will not be refreshed during the refresh cycle and is assumed to be the digit line132in the array126for purposes of the example of FIG.1. Prior to the refresh cycle, both the active digit line128and reference digit lines132are equilibrated by precharging the digit lines120to Vcc/2 so that the sense amplifiers124can measure the voltage disparity between them.

When the access transistors108of the DRAM cells100coupled to the active digit line132and the sense amplifiers124are activated, each of the sense amplifiers124determines which of the two digit lines120carries the higher voltage and the lower voltage, and then drives the higher voltage digit line toward Vcc and the lower voltage digit line toward ground. Thus, when the row of DRAM cells100coupled to the active digit line128is activated, each of these DRAM cells100storing a high voltage charge, even allowing for leakage which necessitates these refresh cycles, should carry a voltage of something greater than Vcc/2. Similarly, DRAM cells100storing a low voltage charge, allowing for leakage, should carry a voltage of less than Vcc/2. Ideally, therefore, the sense amplifiers drive the DRAM cell100coupled to each of the active digit lines toward Vcc or ground, whichever voltage was stored in the DRAM cell100before it was refreshed.

However, conditions are not always ideal. For example, depending upon the combinations of charges stored in the DRAM cells100coupled to the active digit lines128, the sense amplifiers124might not accurately read the charges on the DRAM cells100coupled to the active digit lines124. For example, if a capacitor104of a DRAM cells100stores a high voltage charge, but, for some reason, the voltage read by the sense amplifier124appears to be below the equilibrated Vcc/2 value of the reference digit line132, the sense amplifier124will drive the active digit line132toward ground, refreshing the previously high voltage charge carrying DRAM cell to100a low voltage state, corrupting data.

One way this can happen is through voltage fluctuations or noise affecting digit lines to which a sense amplifier124is coupled. More specifically, since the active digit line128extends though one array125and the reference digit line132extends through a different array126, the active digit line128and the reference digit lines132can be exposed to different noise sources. Noise signals coupled to one of the digit lines128or132but not the other132or128can cause the sense amplifiers124to sense an erroneous voltage level. The manner in which noise signals can be coupled to the active digit line128and the reference digit line132will be discussed in greater detail below.

As mentioned earlier, differential noise coupled to the digit lines128,132is a problem with the open digit line architecture shown inFIG. 1primarily because the active digit line128and the reference digit line132extend through different arrays125,126, respectively. In contrast, an array250having a folded digit line architecture shown inFIG. 2Adoes not have this problem. The folded digit line array250includes a sense amplifier262coupled to respective complimentary pairs of digit lines258provided for each column266of memory cells254. Each digit line258is connected to alternate memory cells254in each column266. For each read or write operation, one of the digit lines258in each pair serves as the active digit line and the other digit line258in the pair serves as the reference digit line. Thus, instead of extending through different arrays as in an open digit line architecture, active and reference digit lines258having a folded architecture extend through the same array250in close proximity with each other. As a result, arrays250having a folded digit line architecture have good common mode noise rejection since the active and reference digit lines258are exposed to the same noise sources to substantially the same degree.

Although a folded digit line architecture provided good common mode noise immunity, it has the disadvantage of consuming more area on a semiconductor die (not shown) compared to an open digit line architecture, which is shown in FIG.2B. As is well known in the art, each memory cell in an open digit line architecture requires only 4F2or 6F2in area, where F represents the feature size, whereas each memory cell254in a folded digit line architecture requires 8F2in area. This significant disparity allows memory devices using an open digit line architecture to consume substantially less space on a semiconductor die so that such memory device can be substantially cheaper than memory devices using a folded digit line architecture.

FIG. 2Bshows two open digit line sub-arrays200and202. Digit lines203,204connected to each sense amplifier206in the open digit line sub-arrays200and202are not connected to memory cells208in the same sub-array. Instead, each sense amplifier206is connected to one digit line203in one sub-array200and one digit line204in a second sub-array202. Each sub-array200,202has its own cell plate210,212, respectively coupled to the memory cell capacitors in its respective sub-array200,202. Furthermore, each sub-array200,202is often fabricated in separate semiconductor wells that form separate substrates214,215that are isolated from each other, such as by using a “triple well” structure, which is known in the art. As will be appreciated, the digit lines203in the first sub-array200can be exposed to difference noise sources than the noise sources to which the digit lines204in the second sub-array are exposed. Noise can be coupled to the digit lines203,204differently for several reasons. For example, because the digit lines203,204in the different sub-arrays200,202are fabricated in different substrates, noise signals generated in the substrates can be coupled to the digit lines203,204. Differential noise can also result from noise signals coupled to differently to the cell plates210,212in each sub-array200,202, respectively.

Various approaches have been used to improve the noise immunity of memory devices using an open digit line architecture. One approach has been to couple corresponding nodes in the sub-arrays200,202to each other so that a voltage disturbance or noise in one of the nodes will also occur in the corresponding node. As a result, if the voltage disturbance or noise is coupled from the node to a digit line in one array, the voltage disturbance will, in theory, also be coupled from the corresponding node to the corresponding digit line in the other array. For example, as shown inFIG. 2B, the cell plate210of the first sub-array200and the cell plate212of the second sub-array202are electrically connected by a conductive coupling217. Theoretically, this measure should alleviate uneven cell plate disturbances by bringing all the coupled cell plates to the same voltage. Similarly, a conductor219is used to couple the substrate214in which one sub-array200is fabricated to the substrate215in which the other array202is fabricated. Although these conductive couplings217,219, as well as other conductors (not shown) coupling corresponding nodes to each other, do, in fact, improve the noise immunity of the sub-arrays200,202in some cases, they can actually creates noise problems that have very adverse consequences, as will be explained below.

With further reference toFIG. 2B, assume that one of the memory cell capacitors216in the sub-array200is storing a high voltage, e.g., VCC, and all of the other memory cell capacitors in the sub-array200are storing a low voltage, e.g., ground potential. This is known as a “1 in a sea of zeros” situation. The capacitor216and all of the other capacitors in the sub-array200are coupled to the same cell plate210. As previously explained, the digit lines203in the sub-array200are equilibrated to one-half the supply voltage, ie., VCC/2, prior to a memory read operation. Assuming that the sub-array200is an active arrays when the access transistors203are activated for the memory cells208storing a 0, the voltage on each of the capacitor plates in such memory cells quickly transition from 0 volts to the equilibrated voltage VCC/2 of the digit lines. The sudden increase in voltage coupled to all of the memory cell capacitors except for the capacitor216causes the voltage of the cell plate210to also increase. The voltage increase on the cell plate210is also coupled to the memory cell capacitor216, which has a plate that has been charged to VCC.

The cell plate210is also coupled to the capacitor104of the lone cell216storing a 1. As a result, the cell plate210will tend to drive the voltage stored in the capacitor216higher as well. This makes it more likely that the sense amplifier206will correctly sense the voltage on the capacitor216as corresponding to a 1. However, because the cell plate210of the sub-array200is also coupled to the cell plate212of the array202, the voltage on the cell plate212also increases. This increase in voltage of the cell plate212can be capacitively coupled to the reference digit line204in the array202. In fact, the voltage disturbance on the cell plate210can be coupled to the reference digit line204with an even greater magnitude than it is coupled to the active digit line203, partly because any voltage increase in the active digit line203is coupled to the capacitor216, which somewhat acts as a low-pass filter. Thus, the conductor217provided to couple the cell plates210,212to each other for the purpose of reducing data read errors, can actually increase data read errors. Similarly, the conductor219coupling of the substrates214,215for the sub-arrays200,202, respectively, to each other can also increase rather than decrease memory read errors.

In an open digit line array architecture device, the types of cell plate and semiconductor substrate disturbances previously described could be overcome by refreshing the memory cells more often. After all, if memory cells were refreshed before the voltages they stored dissipated so as to closely approach Vcc/2, the type of voltage disturbances previously discussed would no longer pose a problem. On the other hand, refreshing memory cells consumes appreciable amounts of power, and it is desirable to reduce power consumption in memory devices to avoid generation of waste heat and, more importantly, to help prolong battery life in portable devices.

There is therefore a need for a circuit and method that can obtain the size advantages of an open digit line architecture without incurring the power consumption costs typically incurred by the higher refresh rates needed for memory devices using an open digit line architecture.

SUMMARY OF THE INVENTION

The present invention is directed to a system and method for selectively coupling and decoupling sub-arrays in open digit line array memory devices to prevent cell plate and semiconductor substrate disturbances from causing memory cell read and refresh errors. In particular, the present invention exploits the fact that, when the memory cells in a sub-array store an appreciably unbalanced number of either zeroes or ones, the nominal voltages of the cell plate and/or substrate for the sub-array undergo transient changes that can result in data read errors. More specifically, in an open digit line architecture, the present invention couples cell plates and/or substrates to the cell plates and/or substrates, respectively, between adjacent arrays to allow for the equalization of cell plate and/or substrate voltages up until the equilibrated active digit lines are to be coupled to the memory cells to read and/or refreshed the memory cells. The cell plate and/or substrate for the active sub-array are then decoupled from the cell plate and/or substrate of the reference sub-arrays to reduce the coupling of any voltage transient in the cell plate and/or substrate of the active sub-array to the cell plate and/or substrate of the reference sub-arrays.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3Ais a block diagram of a selective cell plate coupling system300for selectively coupling cell plates of adjacent sub-arrays to each other in an open digit line architecture.FIG. 3Ashows N sub-arrays, namely sub-array302(1), sub-array302(2), sub-array302(3). The sub-arrays302designated by an odd number in parentheses are coupled to odd-numbered word lines (not shown) and the sub-arrays302designated by an even number in parentheses are coupled to even-numbered word lines (not shown). Thus, when even numbered word lines are activated, one or more of the even-numbered arrays function as active arrays and the adjacent odd-numbered arrays function as reference arrays. Similarly, when odd numbered word lines are activated, one or more of the odd-numbered arrays function as active arrays and the adjacent even-numbered arrays function as reference arrays. A plurality of sense amplifiers308are used to read memory cells (not shown inFIG. 3A) coupled to respective active digit lines by comparing them with respective reference digit lines. The capacitors of the memory cells (not shown) in each sub-array302are coupled to individual sub-array cell plates310(1),310(2), and310(3). This much of the system300is conventional and known in the art.

Added to this system is a selective cell plate coupling transistor330which is coupled to a controller332. The transistor330has one of its terminals coupled through signal line334to all of the odd-numbered sub-arrays302and the other of its terminals coupled through signal line336to all of the even-numbered sub-arrays302. The controller332receives signals generated by other circuitry in a DRAM providing an indication of when a memory read operation is to occur, such as from a row active line337. For example, as shown inFIG. 3A, an active circuit339is coupled to the sub-arrays302for activation thereof, and is further coupled to the controller332to provide a signal to the controller332via the row active line337that is indicative of when a memory operation is to occur. The controller332normally applies a signal to the gate of the transistor330to turn ON the transistor330. The transistor330and signal lines334,336then couple the cell plates310of all of the odd-numbered sub-arrays302to the cell plates310of all of the even-numbered sub-arrays302. Thus, in this condition, the cell plates of adjacent sub-arrays302are coupled to each other. A VCC/2 generator338is coupled to the signal line336to bias the cell plates310of the even sub-arrays302to VCC/2. Of course, when the transistor330is ON, the VCC/2 generator338is also coupled to the signal line334to bias the cell plates310of the odd-arrays302to VCC/2. The large capacitance of the cell plates310allows the voltage of the cell plates310for the odd-numbered sub-arrays302to remain essentially constant at VCC/2 .

In operation, the controller332maintains the transistor330ON so that the sub-arrays302operate in a convention manner, as described above. When a memory read is to occur, the controller332outputs a signal that turns OFF the transistor330. The transistor330then isolates the cell plates310of all of the even-numbered sub-arrays302from the cell plates310for all of the odd-numbered sub-arrays302. In doing so, the transistor330isolates the cell plate310for each sub-array302from the the cell plates310for adjacent sub-arrays302. Therefore, the cell plate310for the active sub-array302is always isolated from the cell plate310for the reference sub-arrays302. For this reason, any coupling of a transient voltage in the cell plate310for the active sub-array302to a reference digit line (not shown) will have a relatively low magnitude.

FIG. 3Bshows another embodiment of the invention in which a system340is used to selectively couple the substrates of adjacent arrays to each other. More specifically, each of the sub-arrays302is fabricated in a substrate342. The substrates342for the odd-number sub-arrays302are coupled to a first signal line346and the substrates342for the even-numbered sub-arrays302are coupled to a second signal line348. The remainder of the system340is identical to the system300of FIG.3A and it operates in the same manner except that a substrate bias generator350is used in the system340in place of the VCC/2 generator used in the system300. The substrate bias generator350biases the substrates342for the sub-arrays302at a suitable bias voltage, such as zero volts or a slight negative voltage, as is well known in the art.

In operation, the controller332maintains the transistor330ON during normal operation so that the substrates of all of the sub-arrays302are coupled to each other and to the substrate bias generator350. When a memory read is to occur, the controller332outputs a signal that turns OFF the transistor330. The transistor330then isolates the substrates342for all of the even-numbered sub-arrays302from the substrates342for all of the odd-numbered sub-arrays302. In doing so, the transistor330isolates the substrate342for each sub-array302from the substrates342for the adjacent sub-arrays302. Therefore, the substrate342for the active sub-array302is always isolated from the substrates342for for the reference sub-arrays302. Any coupling of a transient voltage in the substrate342for the active sub-array302to a reference digit line (not shown) will therefore have a relatively low magnitude.

The system300shown inFIG. 3Bfor selectively coupling cell plates310to each other and the system340for selectively coupling substrates342to each other may be used individually or in combination with each other.

A memory device employing an embodiment of the present invention is shown in FIG.4. The memory device shown inFIG. 4is a synchronous dynamic random access memory (“SDRAM”) device400, although embodiments of the present invention may be used in other DRAMs and other memory devices. The SDRAM device400includes an address register412that receives either a row address or a column address on an address bus414. The address bus414is generally coupled to a memory controller (not shown). Typically, a row address is initially received by the address register412and applied to a row address multiplexer418. The row address multiplexer418couples the row address to a number of components associated with either of two memory arrays400a,400b, depending upon the state of a bank address bit forming part of the row address. The memory arrays400a,400bhave an open-array architecture incorporating one or both embodiments of the invention as shown inFIGS. 3A and 3B. Associated with each of the memory arrays400a,400bis a respective row address latch426, which stores the row address, and a row decoder428, which applies various signals to its respective memory array400aor400bas a function of the stored row address. The row address multiplexer418also couples row addresses to the row address latches426for the purpose of refreshing the memory cells in the memory arrays400a,400b. The row addresses are generated for refresh purposes by a refresh counter430, which is controlled by a refresh controller432.

After the row address has been applied to the address register412and stored in one of the row address latches426, a column address is applied to the address register412. The address register412couples the column address to a column address latch440. Depending on the operating mode of the SDRAM device400, the column address is either coupled through a burst counter442to a column address buffer444, or to the burst counter442, which applies a sequence of column addresses to the column address buffer444starting at the column address that is stored in the column-address latch. In either case, the column address buffer444applies a column address to a column decoder448, which applies various column signals to respective sense amplifiers and associated column circuitry450,452for the respective memory arrays400a,400b.

Data to be read from one of the memory arrays400a,400bare coupled to the column circuitry450,452for one of the memory arrays400a,400b, respectively. The data are then coupled to a data output register456, which applies the data to a data bus458. Data to be written to one of the memory arrays400a,400bare coupled from the data bus458through a data input register460to the column circuitry450,452and then are transferred to one of the memory arrays400a,400b, respectively. A mask register464may be used to selectively alter the flow of data into and out of the column circuitry450,452, such as by selectively masking data to be read from the memory arrays400a,400b.

The above-described operation of the SDRAM400is controlled by a command decoder468responsive to high level command signals received on a control bus470. These high level command signals, which are typically generated by a memory controller (not shown), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*, with the “*” designating the signal as active low or complement. The command decoder468generates a sequence of control signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These control signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be transmitted.

As shown inFIG. 5, a computer system500can take advantage of an embodiment of the present invention by incorporating in its system memory502DRAM devices adapted with one or both embodiments of the present invention as previously described. With reference toFIG. 5, a computer system500includes the system memory502and a processor504for performing various functions, such as performing specific calculations or tasks. In addition, the computer system500includes one or more input devices506, such as a keyboard or a mouse, coupled to the processor504through a system controller508and a system bus510to allow an operator to interface with the computer system500. Typically, the computer system500also includes one or more output devices512coupled to the processor504, such output devices typically being a printer or a video terminal. One or more data storage devices514are also typically coupled to the processor502through the system controller508to store data or retrieve data from external storage media (not shown). Examples of typical data storage devices514include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The system memory502is coupled directly (not shown) to the processor504or to the system controller508to allow data to be written to and read from the system memory502. The computer system500may also include a cache memory522coupled to the processor502through a processor bus520to provide for the rapid storage and reading of data and/or instructions, as is well known in the art.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, it will be appreciated that many variations can be applied to the embodiments shown within the broad concepts of the present invention. Accordingly, the invention is not limited except as by the appended claims.