Frequency modulation control of a buck-boost power converter

A control circuit and method are proposed to generate a control signal to operate a buck-boost power stage of a buck-boost power converter to convert an input voltage to an output voltage. The control circuit and method detect the output voltage to generate an error signal, control the frequency of two ramp signals according to the error signal, generate two pulse width modulation signals according to the error signal and the two ramp signals, and generate the control signal according to the two pulse width modulation signals. When the loading of the buck-boost power converter transits from heavy to light, the frequency of the two ramp signals is decreased to improve the efficiency of the buck-boost power converter. The peaks and valleys of the two ramp signals may be adjusted by signals related to the input voltage and the output voltage.

FIELD OF THE INVENTION

The present invention is related generally to a buck-boost power converter and, more particularly, to a control circuit and method for a buck-boost power converter.

BACKGROUND OF THE INVENTION

A buck power converter is circuitry to operate a buck power stage10as shown inFIG. 1to step down an input voltage Vin to an output voltage Vo for a load Rload, and a boost power converter is circuitry to operate a boost power stage12as shown inFIG. 2to step up an input voltage Vin to an output voltage Vo for a load Rload. Unfortunately, a conventional buck power converter or boost power converter is inadequate to provide a stable voltage for a system, for example a portable device, that uses a battery as its power source Vin because a battery is unable to provide a stable voltage all the time during its lifetime.

Since the voltage of a battery descends with exhaustion of its power, a system using a battery as its power source requires a power converter switchable between a buck mode and a boost mode. A buck-boost power converter is circuitry to operate a buck-boost power stage14as shown inFIG. 3to step down or step up an input voltage Vin to an output voltage Vo for a load Rload. However, such a buck-boost power converter produces a negative output voltage Vo and is thus unsuitable for some applications. Therefore, a buck-boost power stage16as shown inFIG. 4was proposed, by which a positive output voltage Vo is generated from an input voltage Vin. For operating the buck-boost power stage16shown inFIG. 4, there have been proposed many control circuits and methods, for example, U.S. Pat. Nos. 6,166,527 and 7,518,346. Nevertheless, these arts are still not sufficient for users' demands.

Therefore, it is desired a novel control circuit and method for a buck-boost power converter.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a control circuit and method for a buck-boost power converter.

According to the present invention, a control circuit for a buck-boost power converter includes a feedback circuit to detect the output voltage of the buck-boost power converter to generate a feedback signal, an error amplifier to amplify the difference between the feedback signal and a reference voltage to generate an error signal, a waveform generator to provide two ramp signals, a frequency controller to generate an oscillation signal according to the error signal, a clock generator to generate a clock signal according to the oscillation signal for the waveform generator to control the frequencies of the two ramp signals, a PWM comparator to generate two PWM signals according to the error signal and the two ramp signals, a gate driver to generate a control signal according to the two PWM signals to operate a buck-boost power stage to convert an input voltage to the output voltage.

According to the present invention, a control method for a buck-boost power converter detects the output voltage of the buck-boost power converter to generate a feedback signal, amplifies the difference between the feedback signal and a reference voltage to generate an error signal, generates an oscillation signal according to the error signal, generates two ramp signals according to the oscillation signal, generates two PWM signals according to the error signal and the two ramp signals, and generates a control signal according to the two PWM signals to operate a buck-boost power stage to convert an input voltage to the output voltage.

The error signal is used to control the frequencies of the two ramp signals in such a way that the frequencies are decreased for light loading to reduce the switching loss of the buck-boost power stage and thereby improve the efficiency of the buck-boost power converter.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 5is a circuit diagram of an embodiment according to the present invention, in which a buck-boost power converter18includes a control circuit20to provide control signals S1, S2, S3and S4to drive power switches Q1, Q2, Q3and Q4of a buck-boost power stage16, respectively, to step down or step up an input voltage Vin to an output voltage Vo. In the control circuit20, a feedback circuit22detects the output voltage Vo to generate a feedback signal VFB related to the output voltage Vo, an error amplifier24amplifies the difference between the feedback signal VFB and a reference voltage Vref1to generate an error signal Vc, a waveform generator26provides ramp signals Vramp1and Vramp2, a PWM comparator28generates PWM signals PWM1and PWM2according to the error signal Vc and the ramp signals Vramp1and Vramp2, a gate driver30generates the control signals S1, S2, S3and S4according to the PWM signals PWM1and PWM2, a frequency controller32generates an oscillation signal Sf according to the error signal Vc, and a clock generator34generates a clock CLK according to the oscillation signal Sf for the waveform generator26to determine the frequencies of the ramp signals Vramp1and Vramp2. The frequency of the oscillation signal Sf is determined by the error signal Vc, and the frequency of the clock CLK varies with the frequency of the oscillation signal Sf, so that the frequencies of the ramp signals Vramp1and Vramp2are determined by the error signal Vc.

The waveform generator26is established by voltage sources, resistors and capacitors, and by use of the input voltage Vin and the output voltage Vo, or other signals related to the input voltage Vin and the output voltage Vo instead, controls the peaks and valleys of the ramp signals Vramp1and Vramp2.FIG. 6is a circuit diagram of a first embodiment for the waveform generator26, in which a resistor R1and a switch Q5are connected in series between a variable voltage source Vref2and a capacitor C, a switch Q6is connected in parallel with the capacitor C, signals S5and S6control the switches Q5and Q6, respectively, to charge and discharge the capacitor C to generate the ramp signal Vramp1, a variable voltage source Vref3is connected between the capacitor C and a ground GND, a comparator36compares the ramp signal Vramp1with a voltage Vref4to generate a comparison signal Sc, an SR flip-flop38generates the signals S5and S6according to the clock CLK and the comparison signal S5, a shift circuit40level shifts the voltages Vref2, Vref3and Vref4according to the input voltage Vin and the output voltage Vo to adjust the peak and the valley of the ramp signal Vramp1. The SR flip-flop38may be substituted by a D-type flip-flop or other logic circuits for the same purpose. When the input voltage Vin is close to the output voltage Vo, the shift circuit40pulls high the voltages Vref2and Vref4or pulls low the voltage Vref3to increase the peak of the ramp signal Vramp1or to decrease the valley of the ramp signal Vramp1, thereby enabling the ramp signal Vramp1to determine, together with the error signal Vc, a proper duty for the PWM signal PWM1to improve the stability of the buck-boost power converter18. Alternatively, the shift circuit40may increase or decrease the peak and the valley of the ramp signal Vramp1simultaneously to shift the ramp signal Vramp1upward or downward, to improve the stability of the buck-boost power converter18.

If the clock CLK has a constant frequency, the ramp signal Vramp1has a waveform as shown inFIG. 7. At time t1, the clock CLK triggers the output S5of the SR flip-flop38and thereby turns on the switch Q5, to charge the capacitor C by the voltage source Vref2, and as a result the ramp signal Vramp1begins increasing. When the ramp signal Vramp1increases to greater than the voltage Vref4, as shown at time t2, the output Sc of the comparator36resets the SR flip-flop38and thereby turns off the switch Q5and turns on the switch Q6, causing the capacitor C to discharge to the level of the voltage Vref3. In this embodiment, since the frequency of the clock CLK is fixed, the ramp signal Vramp1has a constant frequency.

If the clock CLK has a variable frequency, the ramp signal Vramp1has a waveform as shown inFIG. 8. At time t3, the clock CLK triggers the SR flip-flop38and thereby turns on the switch Q5, to charge the capacitor C by the voltage source Vref2. When the ramp signal Vramp1increases to greater than the voltage Vref4, the comparator36resets the SR flip-flop38and thereby turns off the switch Q5and turns on the switch Q6, causing the capacitor C to discharge to the level of the voltage Vref3. In this embodiment, since the frequency of the clock CLK is variable, the ramp signal Vramp1has a variable frequency.

As shown inFIGS. 7 and 8, the waveform generator26provides a non-linear ramp signal Vramp1, which enables the buck-boost power converter18with better voltage regulation and transient response for heavy loading, as compared with a linear ramp signal. In addition to the waveforms shown inFIGS. 7 and 8, the waveform generator26may provide a non-linear ramp signal Vramp1with other waveforms, for example, shown inFIG. 9,10or11, by using different circuits and methods.FIG. 12is a circuit diagram of a second embodiment for the waveform generator26to provide the ramp signal Vramp1shown inFIG. 10, in which a resistor R2is additionally connected in series with the switch Q6as compared with the waveform generator26ofFIG. 6. Due to the resistor R2, the ramp signal Vramp1decreases to the level of the voltage Vref3mildly when the capacitor C discharges, as shown inFIG. 10.

The circuit for generating the ramp signal Vramp2is similar to that for generating the ramp signal Vramp1and needs not to be discussed repeatedly. As did the ramp signal Vramp1, the ramp signal Vramp2may have its frequency fixed or variable, and may have a non-linear waveform.

FIG. 13is a circuit diagram of a first embodiment for the frequency controller32, which includes a voltage-controlled oscillator (VCO)42to generate the oscillation signal Sf according to the error signal Vc, with the frequency thereof increasing or decreasing with raising or failing of the error signal Vc. At heavy load, the error signal Vc is greater and therefore the VCO42provides an oscillation signal Sf with a higher frequency. On the contrary, at light load the error signal Vc is smaller and therefore the VCO42provides an oscillation signal Sf with a lower frequency. Since the ramp signal Vramp1and Vramp2have lower frequencies at light load, the frequencies of the PWM signals PWM1and PWM2are consequently low, thereby reducing the switching loss of the buck-boost power stage16and in turn improving the efficiency of the buck-boost power converter18.

FIG. 14is a circuit diagram of a second embodiment for the frequency controller32. In addition to the VCO42, this frequency controller32further includes a switch SW1connected between the VCO42and the error amplifier24, and a comparator44to compare the error signal Vc with the voltage Vref5to generate a comparison signal Scomp to switch the switch SW1and a switch SW2connected between the VCO42and a constant voltage source Vref6by an inverter46. At heavy load, the error signal Vc is higher than the voltage Vref5, so the switch SW1is off while the switch SW2is on. In this case, the VCO42generates an oscillation signal Sf with a constant frequency according to the constant voltage Vref6. When transiting to light loading, the error signal Vc decreases, and once the error signal Vc becomes smaller than the voltage Vref5, the comparator44turns on the switch SW1and turns off the switch SW2, so that the VCO42generates an oscillation signal Sf with a variable frequency according to the error signal Vc.