Autodetect feature for a spacewire application

An autodetect circuit for a router system includes an interface to two bidirectional serial links, an input multiplexer circuit coupled to one side of the link interface for receiving input data signals and clock signals, a receiver coupled to the input multiplexer circuit and to a receive FIFO, a state machine coupled to the receiver, a transmitter coupled to the state machine, a transmit FIFO, and to the other side of the link interface for transmitting output data, and a counter coupled to the state machine for controlling the input multiplexer circuit. The autodetect circuit determines which of the two links “A” or “B” is active and available for transmission. The counter is incremented whenever a link reset occurs. When the count reaches a predetermined maximum count value, a port enable signal is toggled from the default “A” link to the “B” link. When one port is enabled, any activity on the other port is ignored.

BACKGROUND OF THE INVENTION

The present invention is related to a router network for space applications. More particularly, the present invention is related to an autodetect circuit for determining which of two links of a node in the router network is active and available for data transmission.

SpaceWire is the common name associated with the European Cooperate for Space Standardization Specification ECSS-E-50-12A. The use and/or implementation of the autodetect circuit are not specifically mentioned in the standard and are left up to the discretion of the designers and suppliers.

Prior autodetect circuits for servicing two transmission links have been developed for other standards and typically involve the duplication of many of the circuits used for just a single link.

What is desired is an autodetect circuit that can minimize the duplication of logic and simplify the circuit involved in prior art autodetect circuits.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, an autodetect circuit for a router system includes an interface to two bidirectional serial links, an input multiplexer circuit coupled to one side of the link interface for receiving input data signals and clock signals, a receiver coupled to the input multiplexer circuit and to a receive FIFO, a state machine coupled to the receiver, a transmitter coupled to the state machine, a transmit FIFO, and to the other side of the link interface for transmitting output data, and a counter coupled to the state machine for controlling the input multiplexer circuit.

If enabled, the link autodetect circuit determines which of the two links “A” or “B” is active and available for SpaceWire transmissions. The link initialization state machine is modified to implement the autodetect feature using a minimum of logic gates. The counter is incremented whenever a link reset occurs. When the count reaches two or three, a port enable signal is toggled from the “A” link, which is the default condition, to the “B” link. This “port enable” signal is sent to the receiver block and used to multiplex the two extracted clocks and the two serial data pairs received from two independent serdes (Serializer-Deserializer) blocks. When one port is enabled, any activity on the other port is ignored.

According to the design and structure of the present invention, implementation of the autodetect circuit on an FPGA is more easily realizable. While the autodetect circuit is ideally used in a router network for space applications, it can also be in a wide range of ASIC applications.

DETAILED DESCRIPTION

Referring now toFIG. 1, a network100suitable for use in conjunction with the autodetect circuit of the present invention is made up of a number of links, nodes110-126, and routing switches102-108. The nodes are the sources and destinations of data packets. For example, a processor is a type of network node. Links between the routers and the nodes provide the means for passing the data packets between one node and another. Nodes can be either directly connected by links or connected via routing switches as can be seen inFIG. 1. Usually a node only supports one link and so, can only be directly coupled to one other node or a router. Typical link connections are shown inFIG. 1. The present invention pertains to an autodetect circuit for transmitting information over a single link that is part of a two link (primary, redundant) pair. Routing switches connect together many nodes and provide a means of routing packets from one node to one of many other possible nodes. Those skilled in the art will understand that the routing network ofFIG. 1is only a portion of a, network, and that there are many other network configurations possible.

Referring now toFIG. 2, an example of a SpaceWire encoder-decoder200is shown suitable for use in a node as shown inFIG. 1. Encoder-decoder200includes a transmit clock block202, a transmitter204, a timer block206, a state machine208, a receiver210, and a clock recovery block212. Transmitter204is responsible for encoding data and transmitting it. The transmit clock block202is responsible for producing the variable data signaling clock signals used by the transmitter. The transmit clock signals are typically derived by dividing down the local system clock, or a phase locked loop multiple of the local system clock. The receiver210is responsible for decoding the Din and Sin signals to produce a data sequence that is passed on to the host system. The receive clock recovery block212is responsible for recovering the receive clock signal by simply XORing the received Data and Strobe signals together. The receive clock recovery circuit212provides all the clock signals used by the receiver210with the exception of the local clock signal used for disconnect timeout. The state machine208controls the overall operation of the link interface, as is explained in further detail below. State machine208provides link initialization, normal operation and error recovery services. Timer block206provides the After 6.4 μs and 12.8 μs timeouts used in link initialization.

Referring now toFIG. 3, the encoder-decoder300is shown in somewhat more detail, in that additional functional blocks are shown. Encoder-decoder300includes transmitter304, state machine308, receiver310, as well as transmit FIFO314, receive FIFO316, clocks/reset block318, configuration/status block320, port “A” serdes block322, port “B” serdes block324, and time code block326. The serdes blocks322and324contain high speed drivers and logic required to meet the 132 mbps bit rates for SpaceWire serial data. The receive FIFO316provides an interface between the captured SpaceWire data and the local host. The transmit FIFO314is a mirror of the receive FIFO316. The transmit FIFO314provides an interface between the local hosts data-to-send (SpaceWire packets) and the transmitter304. The configuration and status block320provides the ability to monitor status and to set various configuration via software.

Link initialization is provided by the state machine as described above. A state diagram400for the state machine is shown inFIG. 4. After power-on reset, the state machine sequences through the states as shown inFIG. 4. In the ErrorReset state, the state machine waits for 6.4 μs before transitioning the link (in a single link router system)to the ErrorWait state. If the receiver receives anything other than NULL characters in this state, a transition back to the ErrorReset state occurs, otherwise the link stays in ErrorWait for 12.8 μs. After the ErrorWait quiet time of 12.8 μs, the link transitions to the Ready state. The link stays in the Ready state until enabled. While in the Ready state, a move back to the ErrorReset state can occur if any non-NULL characters are detected. When enabled, the link transitions from the Ready to the Started state, and releases the transmitter to send NULL characters. The link returns all the way back to the ErrorReset state if NULL characters are not received before a 12.8 μs timeout, or if any non-NULL character is received. If a NULL character is detected before the 12.8 μs expires, the link transitions to the Connecting state. In the Connecting state, the link is enabled to send/receive flow control tokens (FCTs) and credit count monitoring begins. Once an FCT is received, the link finally transitions to the Run state. If no FCT is received before another 12.8 μs timeout occurs, the link returns all the way back to the ErrorReset state. Once in the Run state, the link can transmit and receive all SpaceWire characters.

A prior art autodetect circuit500for a two-link router system is shown inFIG. 5. The autodetect circuit500includes a first data input IN “A” and a first clock input CLK “A” from interface/serdes “A”540, and a second data input IN “B” and a second clock input CLK “B” from interface/serdes “B”550. Autodetect circuit500also includes first and second receivers510and524, multiplexers520and522, initialization blocks508and526, multiplexers516and518, transmitter528, receive FIFO530, and transmit FIFO514. Depending on which of the two links is enabled, multiplexer520couples receiver510to receive FIFO530, or multiplexer522couples receiver524to receive FIFO530. Similarly, depending on which of the two links is enabled, multiplexer516couples receiver510to transmitter528, or multiplexer518couples receiver524to transmitter528. The configuration of circuit500, while suitable for handling the data and clock signals of a two-link router system, does so at the expense of duplicating the receive and state machine/initialization blocks.

An autodetect circuit600for a two-link router system according to the present invention is shown inFIG. 6. The autodetect circuit600includes a first data input IN “A” and a second data input IN “B” from serdes640, and a first clock input CLK “A” and a second clock input CLK “B” from serdes650. Autodetect circuit600also includes receiver610, multiplexers628and630, initialization blocks608, transmitter604, counter632, receive FIFO616, and transmit FIFO614. The autodetect circuit600of the present invention eliminates two multiplexers, as well as duplication of the receivers and state machines.

In operation, the initialization states in the state machine are sequenced on one of the links until the Run state is entered or until a link initialization error is encountered. If a link initialization error as defined in the ECSS-E-50 Specification occurs a specified number of times, such as two or three, counter632, which counts the number of initialization errors, switches from the default link “A” to link “B” and the initialization process is attempted on the new “B” link and vice versa (“B” to “A”) until linked or disabled. This involves a slight modification of the ErrorReset state, as explained below. It is important to note that while a count of “two or three” is mentioned, any number such as four, five, or even ten can be used for the maximum predetermined count value can be used as desired.

The State Machine is modified to include outputs for incrementing and resetting the counter, and another output that controls the multiplexers630and628. The increment signal asserts whenever there is a transition from any state back to the ErrorReset state. The multiplexer control signal switches from “A” to “B” or vice versa when there is a transition back to the ErrorReset State and the counter has incremented to the maximum value. The counter reset asserts at power-on, or when the multiplexer control signal toggles, or when the state machine transitions into Run state.

The present invention describes an interface to the two serial links (the serdes). The manner of implementation for this serdes is one in which the clock produced (or extracted) is derived from the serial data using a technique commonly known as data-strobe encoding. This method of extracting the clock can produce so-called race conditions since the data is captured by the clock which was created from the data. Race conditions cause problems when a data change “beats” a clock change. Such a condition can be more prevalent in the present invention due to the multiplexing of the clocks at multiplexer630. To mitigate this, the multiplexed clock output is inverted before being used to capture the corresponding data.