Method for etching tantalum oxide layer

A method of etching tantalum oxide layer in the fabrication of dynamic random access memory (DRAM). The method comprises the steps of forming the lower electrode structure of a capacitor on a semiconductor substrate. Then, a tantalum oxide layer, a barrier layer and a conductive layer are sequentially formed over the lower electrode structure and the substrate. Next, the conductive layer is patterned using a first reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). Thereafter, the barrier layer is patterned using a second reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). Finally, the tantalum oxide layer is patterned using a third reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2).

CROSS-REFERENCE TO RELATED APPLICATION 
This application claims the priority benefit of Taiwan application serial 
no. 87105068, filed Apr. 3, 1998. 
BACKGROUND OF THE INVENTION 
1. Field of Invention 
The present invention relates to a method for etching a tantalum oxide 
(Ta.sub.2 O.sub.5) layer. More particularly, the present invention relates 
to a method of manufacturing dynamic random access memory (DRAM) that 
involves the sequential etching of a polysilicon layer and a tantalum 
oxide layer to form a pattern without having to switch etching stations. 
2. Description of Related Art 
A conventional dynamic random access memory (DRAM) structure at least 
includes a metal oxide semiconductor (MOS) transistor and a capacitor. The 
gate of the transistor is connected to a word line, and one of the 
source/drain regions is connected to a bit line BL. The other source/drain 
region is electrically connected to a capacitor, which in turn is 
connected to a ground. The capacitor structure in a DRAM can be regarded 
as a critical component in data storage. If the number of charges stored 
by a capacitor is large, the data bit stored in the capacitor is more 
stable. When the data bit stored in the capacitor is read out by an 
amplifier, a large capacitance is more capable of combating external 
noise. 
In semiconductor manufacturing, a DRAM capacitor is formed by several 
steps. First, at least one transistor structure is formed on a 
semiconductor substrate, and then a storage node is formed above one of 
the source/drain regions of the transistor, thereby forming the lower 
electrode structure of a capacitor. Next, a tantalum oxide layer, a 
titanium nitride layer (TiN) and a polysilicon layer are formed 
sequentially over the lower electrode structure. The titanium nitride 
layer is formed above the tantalum oxide layer, and the two layers 
together constitute a composite dielectric layer for the capacitor. The 
polysilicon layer acts as an upper electrode structure of the capacitor. 
Finally, the tantalum oxide layer, the titanium nitride layer and the 
polysilicon layer are patterned to complete the DRAM capacitor structure. 
FIG. 1 is a flow diagram showing the conventional manufacturing steps in 
patterning a multi-layered capacitor structure. First, step 10 represent 
the beginning of the operation where the multi-layered structure of the 
capacitor, including the lower electrode structure, the tantalum oxide 
layer, the titanium nitride layer and the polysilicon layer, has already 
been deposited. Next, step 12 is carried out by first performing a 
photolithographic operation, and then etching the polysilicon layer to 
form the upper electrode structure of the capacitor. Preferably, the 
etchant for etching the polysilicon layer is a gaseous mixture containing 
HBr/Cl.sub.2 /He--O.sub.2. Thereafter, a change in etching station is 
performed in step 14. The change is necessary because the etchant for 
etching the polysilicon layer is unsuitable for etching the tantalum oxide 
layer and the titanium nitride layer. Next, step 16 is carried out etching 
the titanium nitride layer and the tantalum oxide layer (TiN/Ta.sub.2 
O.sub.5), thereby patterning the composite dielectric layer of the 
capacitor. 
In patterning the tantalum oxide layer, the titanium nitride layer and the 
polysilicon layer, some problems often arise. The most severe problem 
occurs when etching of the polysilicon layer is finished, and the titanium 
nitride layer needs to be etched next. The etchant for etching the 
polysilicon layer is a gaseous mixture containing HBr/Cl.sub.2 
/He--O.sub.2, which is unsuitable for etching titanium nitride. Therefore, 
both the processing station and the etchants need to be changed before 
subsequent etching of the titanium nitride layer and the tantalum oxide 
can be performed. This switchover of processing station and etchants 
increases the number of processing steps. Moreover, some residual etchants 
used in etching the polysilicon layer may be carried over into the next 
etching operation. When they come into contact with the titanium nitride 
layer, some metallic ion dissociation may occur. Consequently, the 
reaction chamber may be contaminated. 
In light of the foregoing, there is a need to improve the process of 
etching the polysilicon layer, the titanium nitride layer and the tantalum 
oxide layer. 
SUMMARY OF THE INVENTION 
Accordingly, the present invention provides a method of etching a tantalum 
oxide layer that uses innovative etchants including a gaseous mixture 
containing boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 
/N.sub.2). Using the gaseous mixture, the multi-layered structure of a 
capacitor can be etched in a single etching operation; moreover, there is 
no contamination of the reaction chamber. 
To achieve these and other advantages and in accordance with the purpose of 
the invention, as embodied and broadly described herein, the invention 
provides a method of etching tantalum oxide layer in the fabrication of 
DRAM. The method comprises the steps of forming the lower electrode 
structure of a capacitor on a semiconductor substrate and then 
sequentially forming a tantalum oxide layer, a barrier layer and a 
conductive layer over the substrate and the lower electrode structure. 
Next, the conductive layer is patterned using a first reactive gas that 
includes a gaseous mixture of boron trichloride, chlorine and nitrogen 
(BCl.sub.3 /Cl.sub.2 /N.sub.2). Thereafter, the barrier layer is pattern 
using a second reactive gas that includes a gaseous mixture of boron 
trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). 
Finally, the tantalum oxide layer is patterned using a third reactive gas 
that includes a gaseous mixture of boron trichloride, chlorine and 
nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). 
It is to be understood that both the foregoing general description and the 
following detailed description are exemplary, and are intended to provide 
further explanation of the invention as claimed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Reference will now be made in detail to the present preferred embodiments 
of the invention, examples of which are illustrated in the accompanying 
drawings. Wherever possible, the same reference numbers are used in the 
drawings and the description to refer to the same or like parts. 
This invention provides an innovative etchant that contains a gaseous 
mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 
/N.sub.2). The characteristic property of this etchant is that it can etch 
polysilicon, titanium nitride (TiN) and tantalum oxide (Ta.sub.2 O.sub.5). 
Therefore, a single etching operation can be used to form the 
multi-layered structure of a capacitor. Moreover, the method is capable of 
reducing severe contamination of the reaction chamber. 
FIGS. 2A and 2B are cross-sectional views showing the progression of 
manufacturing steps in patterning a multi-layered capacitor structure 
(including a tantalum oxide layer) on a capacitor according to one 
preferred embodiment of this invention. First, as shown in FIG. 2A, a 
patterned insulating layer 21 is formed over a semiconductor substrate 20. 
Next, the lower electrode structure 22 of a capacitor, for example, a 
polysilicon layer is formed in the insulating layer 21 for electrically 
connecting a source/drain region (not shown) in the substrate 20. 
Thereafter, a multi-layered structure is formed over the lower electrode 
structure 22 and the insulating layer 21. The multi-layered structure is 
formed by depositing a thin tantalum oxide layer 23, a thin titanium 
nitride layer 24 and a polysilicon layer 25. The titanium nitride layer 24 
is formed over the tantalum oxide layer 23, and the two layers together 
form a composite dielectric structure. Since tantalum oxide has a very 
high dielectric constant of about 20 to 30, the tantalum oxide layer 23 is 
capable of increasing the capacitance of the capacitor. Hence, the 
tantalum oxide layer has applications in fabricating 16M DRAM. 
Subsequently, a photoresist layer 26 is formed over the polysilicon layer 
25. 
Next, as shown in FIG. 2B, photolithographic and etching operations are 
carried out using the photoresist layer 26 as a mask. The polysilicon 
layer 25, the thin titanium nitride layer 24 and the thin tantalum oxide 
layer 23 are etched sequentially using the characteristic etchant of this 
invention. The etchant is a gaseous mixture including boron trichloride, 
chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 N.sub.2). The ingredients of 
the gaseous mixture are mixed together in a ratio according to Table 1 
below. 
TABLE 1 
______________________________________ 
Relative gas flow rate of gaseous ingredients for etching 
polysilicon, titanium nitride and tantalum oxide. 
Ingredients (Gaseous) 
Gas Flow Rate (Unit:sccm) 
______________________________________ 
Chlorine (Cl.sub.2) 
20-80 
Boron Trichloride (BCl.sub.3) 
20-80 
Nitrogen (N.sub.2) 
20-80 
______________________________________ 
In Table 1, the unit sccm refers to the gas flow rate in standard cubic 
centimeter per minute, and each ingredient in the gaseous mixture performs 
a definite function. For example, chlorine Cl.sub.2 is a main reactive gas 
for etching, boron trichloride BCl.sub.3 is used as an agent for carrying 
out physical bombardment, and the gaseous nitrogen functions as sidewall 
passivation material. 
FIG. 3 is a flow diagram showing the steps in patterning a multi-layered 
capacitor structure according to the preferred embodiment of this 
invention. First, step 30 represent the beginning of the operation where 
the multi-layered structure of the capacitor, including the lower 
electrode structure, the tantalum oxide layer, the titanium nitride layer 
and the polysilicon layer, has already been deposited. Next, step 32 is 
carried out by first performing a photolithographic operation, and then 
etching the polysilicon layer to form the upper electrode structure of the 
capacitor. Preferably, the etchant for etching the polysilicon layer is a 
gaseous mixture of boron trichloride, chlorine and nitrogen (BCl.sub.3 
/Cl.sub.2 /N.sub.2). Next, step 34 is carried out, etching the titanium 
nitride layer and the tantalum oxide layer (TiN/Ta.sub.2 O.sub.5) to form 
the composite dielectric structure of the capacitor. Preferably, the 
etchant for etching the polysilicon layer is a gaseous mixture of boron 
trichloride, chlorine and nitrogen (BCl.sub.3 /Cl.sub.2 /N.sub.2). Hence, 
a complete capacitor structure is formed in a single etching operation 
using the gaseous mixture including boron trichloride, chlorine and 
nitrogen. 
In summary, the method of etching tantalum oxide layer provided by this 
invention has the following advantages including: 
(1) The etchant provided by this invention, namely, a gaseous mixture 
having the ingredients BCl.sub.3 /Cl.sub.2 /N.sub.2, is capable of etching 
a polysilicon layer, a titanium nitride layer and a tantalum oxide layer 
to form a uniform pattern. 
(2) The etchant provided by this invention, namely, a gaseous mixture 
having the ingredients BCl.sub.3 /Cl.sub.2 /N.sub.2, is able to etch a 
pattern out of the multi-layered structure in a single etching operation. 
Therefore, processing steps are saved. 
(3) The etchant used in this invention does not dissociate metallic ions on 
contact with a titanium nitride layer. Therefore, contamination of 
reaction chamber is greatly reduced. 
It will be apparent to those skilled in the art that various modifications 
and variations can be made to the structure of the present invention 
without departing from the scope or spirit of the invention. In view of 
the foregoing, it is intended that the present invention cover 
modifications and variations of this invention provided they fall within 
the scope of the following claims and their equivalents.