Solid-state imaging device, method of driving solid-state imaging device, and electronic device

A solid-state imaging device according to an embodiment includes a photoelectric conversion unit, a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit, a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit, a second charge modulation unit, a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period, a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit, and a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit, in which, in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT/JP2021/001808 filed on Jan. 20, 2021, which claims priority benefit of Japanese Patent Application No. JP 2020-012993 filed in the Japan Patent Office on Jan. 29, 2020. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device.

BACKGROUND ART

In in-vehicle image sensors, a problem called “LED flicker” has been highlighted, in which a blinking object such as an LED light source cannot be imaged depending on blinking timing. This LED flicker is a defect that occurs because a conventional image sensor has a low dynamic range and needs to adjust an exposure time for each object.

By the way, to cope with objects with various illuminances, the exposure time is set to be long for a low-illuminance object, and the exposure time is set to be short for a high-illuminance object. In this way, the image sensors are devised to be able to cope with various objects even in a low dynamic range.

Meanwhile, reading speed is constant regardless of the exposure time. For this reason, in a case of setting the exposure time in a unit shorter than a readout time, light incident on a photodiode at timing other than the exposure time is photoelectrically converted into charges but is not read out after charge-voltage conversion and discarded. Therefore, even if the LED light source blinks in an invalid period other than the exposure time, the LED light source cannot be imaged and the LED flicker occurs.

To cope with the LED flicker, the dynamic range needs to be expanded. Various dynamic range expansion techniques are known, and examples thereof include a time division method (see, for example, Patent Document 1), a space division method (see, for example, Patent Document 2), and a method of providing a memory in a pixel to directly increase an amount of charge handled (see, for example, Patent Document 3).

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

For example, image synthesis is essential to ensure the dynamic range of 120 dB, for example, but artifacts of moving objects cannot be avoided in the time division method. In a case of not using the time division method, sensitivity difference and capacitance difference are used, but it has been difficult to obtain a sufficient dynamic range only by the sensitivity difference and the capacitance difference due to miniaturization of pixels.

Furthermore, even in the case of expanding the dynamic range on a high-illuminance side by providing a memory in a pixel to increase the amount of charge handled (see, for example, Patent Documents 4 and 5), a low-illuminance characteristic is required at the same time, but to increase conversion efficiency and secure the low-illuminance characteristic, the capacity of floating diffusion needs to be reduced as much as possible. However, if the capacitance of the floating diffusion is reduced, a photocharge accumulated in a photodiode cannot be completely received. At this time, the photocharge that cannot be completely received is combined with the photocharge accumulated in the in-pixel capacitance and read out. However, since signal reading from the in-pixel capacitance is performed by delta data sampling, the signal is easily affected by kTC noise and white and dark currents caused by an interface state, and the photocharge that is accumulated in the photodiode and can be originally read out by correlated double sampling is wasted.

The present invention has been made in view of the foregoing, and an object of the present invention is to provide a solid-state imaging device, a method of driving a solid-state imaging device, and an electronic device that are excellent in low-illuminance characteristics and capable of expanding a dynamic range.

Solutions to Problems

A solid-state imaging device according to an embodiment includes a photoelectric conversion unit; a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit; a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit; a second charge modulation unit; a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit; a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period; and a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit, in which, in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit by the modulation switching unit and the capacitance connection unit.

MODE FOR CARRYING OUT THE INVENTION

First Embodiment

FIG.1is a schematic configuration diagram illustrating an example of a pixel constituting a solid-state imaging device according to a first embodiment.

A plurality of (for example, N rows×M columns. N and M are integers of 2 or larger) pixels10is provided to constitute a pixel array unit in the solid-state imaging device. Then, the pixel10photoelectrically converts incident light and generates a pixel signal corresponding to the amount of received incident light.

For example, as illustrated inFIG.1, the pixel10includes a photodiode21as a photoelectric conversion unit, a floating diffusion (FD) region22-1as a first charge modulation unit, a floating diffusion region22-2as a second charge modulation unit, a transfer transistor23as a charge transfer unit, an in-pixel capacitance24as a charge accumulation unit, a conversion efficiency switching transistor25as a modulation switching unit, an accumulation transistor26as a capacitance connection unit, a reset transistor27, an amplification transistor28, and a selection transistor29.

In the above configuration, the photodiode21generates a charge according to the amount of received incident light.

The floating diffusion region22and the in-pixel capacitance24accumulate a photocharge overflowing from the photodiode21during a charge accumulation period.

The transfer transistor23transfers the photocharge accumulated in the photodiode21to the floating diffusion region22.

The conversion efficiency switching transistor25modulates the photocharge accumulated in the photodiode21to a voltage signal in a state of only the floating diffusion region22-1and in a state where the floating diffusion region22-1and the floating diffusion region22-2are potential-coupled, thereby switching the conversion efficiency.

The accumulation transistor26functions as a capacitance connection unit, and couples or divides the potential between the floating diffusion region22and the in-pixel capacitance24.

The reset transistor27resets the accumulated charge and shifts to an initial state.

The amplification transistor28amplifies the voltage signal obtained by modulating the charge and outputs the amplified voltage signal as a pixel signal.

The selection transistor29has a low potential side connected to a constant current source30, and outputs the pixel signal output from the amplification transistor28to a subsequent stage at the time of conduction.

FIG.2is a processing timing chart of the first embodiment.

InFIG.2, an upper stage is a processing timing chart of pixels corresponding to a row (SH row) where an exposure start operation is performed, and a lower stage is a processing timing chart of pixels corresponding to a row (RD row) where a signal read operation is performed.

FIGS.3A and3Bare potential diagrams according to the first embodiment.

In the exposure start operation, at the timing indicated by the arrow (a) inFIG.2, the accumulation transistor26is set to an on state (conductive state) by a control signal FCG, the reset transistor27is set to the on state (conductive state) by a control signal RST, and the charge accumulated in the in-pixel capacitance24is set to a reset state, as illustrated inFIG.3B(a), and the transfer transistor23is set to the on state (conductive state) by a control signal TRG, and the conversion efficiency switching transistor25is set to the on state (conductive state) by a control signal FDG, so that the charge accumulated in the photodiode21is also set to the reset state, as illustrated inFIG.3A(a).

Then, as indicated by reference sign (b) inFIG.2, exposure is performed between the row (SH row) where the exposure start operation is performed and the row (RD row) where the signal read operation is performed as illustrated inFIGS.3A(b) and3B(b).

Then, after a certain exposure time, the selection transistor29is set to the on state by a control signal SEL to start the signal read operation. Then, the conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG, and at the timing indicated by the arrow (c) inFIG.2, a reset level R2at low conversion efficiency is acquired, as illustrated inFIG.3A(c).

At this time, at the timing indicated by the arrow (c) inFIG.2, the potentials of the floating diffusion region22-1(indicated by reference sign FD1inFIG.3A) and the floating diffusion region22-2(indicated by reference sign FD2inFIGS.3A and3B) are coupled as illustrated inFIG.3A(c).

In this case, the potentials of the floating diffusion region22-1(indicated by reference sign FD1inFIG.3A) and the floating diffusion region22-2(indicated by reference sign FD2inFIGS.3A and3B) are supplied as a gate voltage of the amplification transistor28, and the gate voltage is supplied as a pixel signal to the subsequent stage (for example, an AD converter) via the selection transistor29and a vertical signal line.

Next, at the timing indicated by the arrow (d) inFIG.2, the conversion efficiency switching transistor25is set to an off state (non-conductive state) by the control signal FDG, and a reset level R1at high conversion efficiency is acquired, as illustrated inFIG.3A(d).

Next, the transfer transistor23is set to the on state (conductive state) by the control signal TRG to transfer the charge accumulated in the photodiode21to the floating diffusion region22-1, and is then set to the off state (non-conductive state) by the control signal TRG.

Next, at the timing indicated by the arrow (e) inFIG.2, a signal level S1at high conversion efficiency is acquired as illustrated inFIG.3A(e).

Next, at the timing indicated by the arrow (f) inFIG.2, the conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG and at the same time, the transfer transistor23is set to the on state (conductive state) again by the control signal TRG, so that all the charges accumulated in the photodiode21are transferred to the floating diffusion region22, and then, the transfer transistor23is set to the off state (non-conductive state) by the control signal TRG, and then a signal level S2at low conversion efficiency is read, as illustrated inFIG.3A(f).

Here, in the case of high illuminance, the photocharge overflowing from the photodiode21is accumulated in the in-pixel capacitance24. Therefore, at the timing indicated by the arrow (g) inFIG.2, the in-pixel capacitance24, the floating diffusion region22-1, and the floating diffusion region22-2are potential-coupled by setting the accumulation transistor in the on state (conductive state) by the control signal FCG, and a signal level S4is read out, as illustrated inFIG.3B(g).

Next, in a state where the selection transistor29is set to the off state by the control signal SEL, the reset transistor27is set to the on state (conductive state) by the control signal RST, and the accumulated charge is set to the reset state.

Then, the reset transistor is set to the off state (non-conductive state) by the control signal RST, and a reset level R4is acquired as illustrated inFIG.3B(h) at the timing indicated by the arrow (h) inFIG.2.

For a difference between the signal level S1at high conversion efficiency and the reset level R1at high conversion efficiency, that is,

for S1-R1,

an image signal is generated by correlated double sampling (CDS).

Similarly, for a difference between the signal level S4and the reset level R4, that is,

for S4-R4,

an image signal is generated by delta data sampling (DDS).

In contrast, for a difference between the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency, that is,

for S2-R2,

an image signal is generated by the correlated double sampling (CDS), but the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency are not continuously read, and thus the reset level R2at low conversion efficiency needs to be temporarily held in a line memory or the like.

As a result, by combining three images corresponding to the image signals corresponding to S1-R1, S2-R2, and S4-R4, it is possible to configure an image having excellent low-illuminance characteristics, a high dynamic range, and no artifact of the object.

As described above, according to the first embodiment, in the state of the floating diffusion region22-1alone functioning as the first charge modulation unit, and in the state where the floating diffusion region22-1functioning as the first charge modulation unit and the floating diffusion region22-2functioning as the second charge modulation unit are coupled by the conversion efficiency switching transistor25functioning as the modulation switching unit, the charge accumulated in the photodiode21functioning as the photoelectric conversion unit is modulated into the voltage signal and the (high conversion efficiency and low conversion efficiency) voltage signals having different conversion efficiencies are continuously read. Moreover, the charge accumulated in the photodiode21functioning as the photoelectric conversion unit and the charge overflowing from the photodiode21and accumulated in the in-pixel capacitance24during the accumulation period are modulated into the voltage signal and the voltage signal read in the capacitance in which the floating diffusion region22-1, the floating diffusion region22-2, and the in-pixel capacitance24are coupled by the conversion efficiency switching transistor25functioning as the modulation switching unit and the accumulation transistor26functioning as the capacitance connection unit. Therefore, excellent low-illuminance characteristics and an expanded high dynamic range can be obtained.

[1.1] First Modification of First Embodiment

FIG.4is a schematic configuration diagram illustrating an example of a pixel constituting a solid-state imaging device according to a first modification of the first embodiment.

A pixel10A ofFIG.4is different from the pixel10of the first embodiment ofFIG.1in that a second accumulation transistor31functioning as a third charge transfer unit is provided between the photodiode21and the in-pixel capacitance24.

As described above, according to the configuration provided with the second accumulation transistor31, the floating diffusion region22-1and the floating diffusion region22-2can be reset before the charge accumulated in the photodiode21is read, which is advantageous in terms of charge transfer from the photodiode21to the floating diffusion region22-1and the floating diffusion region22-2and dark current white spots of the floating diffusion region22-1and the floating diffusion region22-2.

FIG.5is a processing timing chart of the first modification of the first embodiment.

FIGS.6A and6Bare potential diagrams of the first modification of the first embodiment.

In the exposure start operation, at the timing indicated by the arrow (a) inFIG.5, the accumulation transistor26is set to the on state (conductive state) by the control signal FCG, further, the reset transistor27is set to the on state (conductive state) by the control signal RST, and the charge accumulated in the in-pixel capacitance24is set to the reset state, as illustrated inFIG.6B(a), and in the on state (conductive state) of the conversion efficiency switching transistor25by the control signal FDG, the transfer transistor23is set to the on state (conductive state) by the control signal TRG, so that the charge accumulated in the photodiode21is also set to the reset state, as illustrated inFIG.6A(a).

Then, as indicated by reference sign (b) inFIG.5, exposure is performed between the row (SH row) where the exposure start operation is performed and the row (RD row) where the signal read operation is performed as illustrated inFIGS.6A(b) and6B(b).

Then, after a certain exposure time, the selection transistor29is set to the on state by the control signal SEL to start the signal read operation. The conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG, and at the timing indicated by the arrow (c) inFIG.5, the reset level R2at low conversion efficiency is acquired, as illustrated inFIG.6A(c).

At this time, at the timing indicated by the arrow (c) inFIG.5, the potentials of the floating diffusion region22-1(indicated by reference sign FD1inFIG.6A) and the floating diffusion region22-2(indicated by reference sign FD2inFIGS.6A and6B) are coupled as illustrated inFIG.6A(c).

Next, the conversion efficiency switching transistor25is set to the off state by the control signal FDG, and at the timing indicated by the arrow (d) inFIG.5, the reset level R1at high conversion efficiency is acquired, as illustrated inFIG.6A(d).

Moreover, the transfer transistor23is set to the on state (conductive state) by the control signal TRG to transfer the charge accumulated in the photodiode21to the floating diffusion region22-1.

Next, the transfer transistor23is set to the off state (non-conductive state) by the control signal TRG, and the signal level S1at high conversion efficiency is acquired as illustrated inFIG.6A(e) at the timing indicated by the arrow (e) inFIG.5.

Next, at the timing indicated by the arrow (f) inFIG.5, the conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG and at the same time, the transfer transistor23is set to the on state (conductive state) again by the control signal TRG, so that all the charges accumulated in the photodiode21are transferred to the floating diffusion region22, and the signal level S2at low conversion efficiency is read, as illustrated inFIG.6A(f).

Here, in the case of high illuminance, the photocharge overflowing from the photodiode21is accumulated in the in-pixel capacitance24. Therefore, at the timing indicated by the arrow (g) inFIG.5, the in-pixel capacitance24, the floating diffusion region22-1, and the floating diffusion region22-2are potential-coupled by setting the accumulation transistor26in the on state (conductive state) by the control signal FCG, and the signal level S4is read, as illustrated inFIG.6B(g).

Next, in the state where the selection transistor29is set to the off state by the control signal SEL, the reset transistor27is set to the on state (conductive state) by the control signal RST, and the accumulated charge is set to the reset state.

Then, the reset transistor27is set to the off state (non-conductive state) by the control signal RST, and a reset level R4is acquired as illustrated inFIG.6B(h) at the timing indicated by the arrow (h) inFIG.5.

Thereafter, for the difference between the signal level S1at high conversion efficiency and the reset level R1at high conversion efficiency, that is,

for S1-R1,

an image signal is generated by correlated double sampling (CDS).

Similarly, for the difference between the signal level S4and the reset level R4, that is,

for S4-R4,

an image signal is generated by delta data sampling (DDS).

In contrast, for the difference between the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency, that is,

for S2-R2,

an image signal is generated by the correlated double sampling (CDS), but the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency are not continuously read, and thus the reset level R2at low conversion efficiency needs to be temporarily held in a line memory or the like.

As a result, by combining three images corresponding to the image signals of S1-R1, S2-R2, and S4-R4, it is possible to configure an image having excellent low-illuminance characteristics, a high dynamic range, and no artifact of the object.

As described above, according to the first modification of the first embodiment, since the second accumulation transistor31functioning as the third charge transfer unit is provided between the photodiode21functioning as the first photoelectric conversion unit and the in-pixel capacitance24functioning as the charge accumulation unit, it becomes possible to reset the floating diffusion region22-1and the floating diffusion region22-2before reading the charge accumulated in the photodiode21, and it is advantages in terms of charge transfer from the photodiode21to the floating diffusion region22-1and the floating diffusion region22-2and dark current white spots of the floating diffusion region22-1and the floating diffusion region22-2, in addition to the effects of the first embodiment.

[1.2] Second Modification of First Embodiment

FIG.7is a schematic configuration diagram illustrating an example of a pixel constituting a solid-state imaging device according to a second modification of the first embodiment.

A pixel10B ofFIG.7is different from the pixel10of the first embodiment ofFIG.1in that the in-pixel capacitance24is connected to a connection point between the conversion efficiency switching transistor25and the reset transistor27without providing the accumulation transistor26.

FIG.8is a processing timing chart of the second modification of the first embodiment.

InFIG.8, the upper stage is a processing timing chart of pixels corresponding to the row (SH row) where the exposure start operation is performed, and the lower stage is a processing timing chart of pixels corresponding to the row (RD row) where the read operation is performed.

FIG.9is a potential diagram of the second modification of the first embodiment.

In the exposure start operation, at the timing indicated by the arrow (a) inFIG.8, the reset transistor27is set to the on state (conductive state) by the control signal RST, the charge accumulated in the in-pixel capacitance24is set to the reset state, the conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG, and the transfer transistor23is set to the on state (conductive state) by the control signal TRG, so that the charge accumulated in the photodiode21is also set to the reset state, as illustrated inFIG.9(a).

Then, as indicated by reference sign (b) inFIG.8, exposure is performed between the row (SH row) where the exposure start operation is performed and the row (RD row) where the signal read operation is performed as illustrated inFIG.9(b).

Then, after a certain exposure time, the selection transistor29is set to the on state by the control signal SEL to start the signal read operation. The conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG, and at the timing indicated by the arrow (c) inFIG.8, the reset level R2at low conversion efficiency is acquired, as illustrated inFIG.9(c).

At this time, at the timing indicated by the arrow (c) inFIG.8, the potentials of the floating diffusion region22-1(indicated by reference sign FD1inFIG.9) and the floating diffusion region22-2(indicated by reference sign FD2inFIG.9) are coupled as illustrated inFIG.9(c).

In this case, the potentials of the floating diffusion region22-1(indicated by reference sign FD1inFIG.9) and the floating diffusion region22-2(indicated by reference sign FD2inFIG.9) are supplied as a gate voltage of the amplification transistor28, and the gate voltage is supplied as a pixel signal to the subsequent stage (for example, an AD converter) via the selection transistor29and a vertical signal line.

Next, at the timing indicated by the arrow (d) inFIG.8, the conversion efficiency switching transistor25is set to the off state (non-conductive state) by the control signal FDG, and the reset level R1at high conversion efficiency is acquired, as illustrated inFIG.9(d).

Next, at the timing indicated by the arrow (e) inFIG.8, the signal level S1at high conversion efficiency is acquired as illustrated inFIG.9(e).

Next, at the timing indicated by the arrow (f) inFIG.8, the conversion efficiency switching transistor25is set to the on state (conductive state) by the control signal FDG and at the same time, the transfer transistor23is set to the on state (conductive state) again by the control signal TRG, so that all the charges accumulated in the photodiode21are transferred to the floating diffusion region22, then, the transfer transistor23is set to the off state (non-conductive state) by the control signal TRG, and then the signal level S2at low conversion efficiency is read, as illustrated inFIG.9(f).

Here, in the case of high illuminance, since the photocharge overflowing from the photodiode21is accumulated in the in-pixel capacitance24, a signal level S3is read as illustrated inFIG.9(g) at the timing indicated by the arrow (g) inFIG.8.

Next, in the state where the selection transistor29is set to the off state by the control signal SEL, the reset transistor27is set to the on state (conductive state) by the control signal RST, and the accumulated charge is set to the reset state.

Then, the reset transistor27is set to the off state (non-conductive state) by the control signal RST, and a reset level R3is acquired as illustrated inFIG.9(h)at the timing indicated by the arrow (h) inFIG.8.

For the difference between the signal level S1at high conversion efficiency and the reset level R1at high conversion efficiency, that is,

for S1-R1,

an image signal is generated by correlated double sampling (CDS).

Similarly, for the difference between the signal level S3and the reset level R3, that is,

for S3-R3,

an image signal is generated by delta data sampling (DDS).

In contrast, for the difference between the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency, that is,

for S2-R2,

an image signal is generated by the correlated double sampling (CDS), but the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency are not continuously read, and thus the reset level R2at low conversion efficiency needs to be temporarily held in a line memory or the like.

As a result, according to the second modification of the first embodiment, by combining three images corresponding to the image signals of S1-R1, S2-R2, and S3-R3, it is possible to configure an image having excellent low-illuminance characteristics, a high dynamic range, and no artifact of the object.

As described above, according to the second modification of the first embodiment, since the in-pixel capacitance24is connected to the connection point between the conversion efficiency switching transistor25and the reset transistor27without providing the accumulation transistor26, the pixel size can be reduced in addition to the effects of the first embodiment.

[2] Second Embodiment

FIG.10is a schematic configuration diagram illustrating an example of a pixel constituting a solid-state imaging device according to a second embodiment.

A plurality of (for example, N rows x M columns. N and M are integers of 2 or larger) pixels40according to the second embodiment is provided to constitute a pixel array unit in the solid-state imaging device, similarly to the first embodiment. Then, the pixel10photoelectrically converts incident light and generates a pixel signal corresponding to the amount of received incident light.

For example, as illustrated inFIG.10, the pixel40includes a high-sensitivity photodiode41as a first photoelectric conversion unit, a first floating diffusion region42as a first charge modulation unit, a transfer transistor43as a charge transfer unit, a conversion efficiency switching transistor44as a modulation switching unit, a second floating diffusion region45as a second charge modulation unit, an accumulation transistor46as a capacitance connection unit, a reset transistor47, an in-pixel capacitance48as a charge accumulation unit, a low-sensitivity photodiode50as a second photoelectric conversion unit, a third floating diffusion region51as a third charge modulation unit, an amplification transistor52, and a selection transistor53.

In the above configuration, the high-sensitivity photodiode41generates a charge corresponding to the amount of received incident light with high sensitivity.

The first floating diffusion region42functions as the first charge modulation unit and simultaneously stores a charge overflowing from the high-sensitivity photodiode41.

The transfer transistor43functions as the charge transfer unit, and transfers a photocharge accumulated in the high-sensitivity photodiode41to the first floating diffusion region42.

The conversion efficiency switching transistor44functions as the modulation switching unit, and switches conversion efficiency by modulating the photocharge accumulated in the high-sensitivity photodiode41to a voltage signal in a state of only the first floating diffusion region42, a state of coupling potentials of the first floating diffusion region42and the second floating diffusion region45, or a state of coupling potentials of the first floating diffusion region42, the second floating diffusion region45, and the third floating diffusion region51.

The first floating diffusion region42and the second floating diffusion region45function as the first charge modulation unit and the second charge modulation unit, and at the same time, store the charge overflowing from the high-sensitivity photodiode41.

The accumulation transistor46functions as the capacitance connection unit, and couples or divides the potentials of the second floating diffusion region45and the third floating diffusion region51.

The reset transistor47resets the accumulated charge and shifts to an initial state.

The low-sensitivity photodiode50functions as the second photoelectric conversion unit and generates the charge according to the amount of received incident light.

The third floating diffusion region51functions as the third charge modulation unit and at the same time, functions as the charge accumulation unit to which the in-pixel capacitance48is connected and which stores the charge generated by photoelectric conversion in the low-sensitivity photodiode50.

The amplification transistor52amplifies a voltage signal obtained by modulating the charge and outputs the amplified voltage signal as a pixel signal.

The selection transistor53has a low potential side connected to a constant current source54, and outputs the pixel signal output from the amplification transistor52to a subsequent stage at the time of conduction.

FIG.11is a processing timing chart of the second embodiment.

FIGS.12A and12Bare potential diagrams according to the second embodiment.

In an exposure start operation, at the timing indicated by the arrow (a) inFIG.11, the reset transistor47is set to an on state (conductive state) by a control signal RST and the third floating diffusion region51is set to a reset state while the accumulation transistor46is in the on-state (conductive state) by a control signal FCG, as illustrated inFIG.12B(a), and the conversion efficiency switching transistor44is set to the on state (conductive state) by a control signal FDG and the transfer transistor43is set to the on state (conductive state) by a control signal TGL, as illustrated inFIG.12A(a), so that the high-sensitivity photodiode41is set to the reset state.

Then, as indicated by reference sign (b) inFIG.11, exposure is performed between a row (SH row) where the exposure start operation is performed and a row (RD row) where a signal read operation is performed as illustrated inFIGS.12A(b) and12B(b).

Then, after a certain exposure time, the selection transistor53is set to the on state by a control signal SEL to start the signal read operation. The conversion efficiency switching transistor44is set to the on state (conductive state) by the control signal FDG, and at the timing indicated by the arrow (c) inFIG.11, a reset level R2at low conversion efficiency is acquired, as illustrated inFIG.12A(c).

At this time, at the timing indicated by the arrow (c) inFIG.11, the potentials of the first floating diffusion region42(indicated by reference sign FD1inFIG.12A) and the second floating diffusion region45(indicated by reference sign FD2inFIGS.12A and12B) are coupled as illustrated inFIG.12A(c).

Next, at the timing indicated by the arrow (d) inFIG.11, the conversion efficiency switching transistor44is set to an off state (non-conductive state) by the control signal FDG, and a reset level R1at high conversion efficiency is acquired, as illustrated inFIG.12A(d).

Next, the transfer transistor43is set to the on state (conductive state) by the control signal TGL to transfer the charge accumulated in the high-sensitivity photodiode41to the first floating diffusion region42, and is then set to the off state (non-conductive state) by the control signal TGL.

Next, at the timing indicated by the arrow (e) inFIG.11, a signal level S1at high conversion efficiency is acquired as illustrated inFIG.12A(e).

Next, at the timing indicated by the arrow (f) inFIG.11, the conversion efficiency switching transistor44is set to the on state (conductive state) by the control signal FDG, and at the same time, the transfer transistor43is set to the on state (conductive state) again by the control signal TGL, so that all the charges accumulated in the high-sensitivity photodiode41are transferred to the first floating diffusion region42and the second floating diffusion region45, then, the transfer transistor43is set to the off state (non-conductive state) by the control signal TGL, and then, a signal level S2at low conversion efficiency is read, as illustrated inFIG.12A(f).

Next, a signal level S3is read while the potentials of the first floating diffusion region42and the second floating diffusion region45are kept coupled.

Next, the selection transistor53is set to the off state by the control signal SEL, the reset transistor47is set to the on state (conductive state) by the control signal RST, and the charges accumulated in the first floating diffusion region42and the second floating diffusion region45are set to the reset state.

Then, the reset transistor47is set to the off state (non-conductive state) by the control signal RST, and a reset level R3is read as illustrated inFIG.12A(h) at the timing indicated by the arrow (h) inFIG.11.

Then, at the timing indicated by the arrow (i) inFIG.11, the accumulation transistor46is set to the on state (conductive state) by the control signal FCG, the potentials of the second floating diffusion region45and the third floating diffusion region51are combined, and a signal level S4is read, as illustrated inFIG.12B(i).

Next, in a state where the selection transistor53is set to the off state by the control signal SEL, the reset transistor47is set to the on state (conductive state) by the control signal RST, and the accumulated charge is set to the reset state.

Next, at the timing indicated by the arrow (j) inFIG.11, the selection transistor53is set to the on state (conductive state) again by the control signal SEL, and a reset level R4is acquired, as illustrated inFIG.12B(j).

Thereafter, for a difference between the signal level S1at high conversion efficiency and the reset level R1at high conversion efficiency corresponding to the high-sensitivity photodiode41, that is, for S1-R1

an image signal is generated by correlated double sampling (CDS).

In contrast, for a difference between the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency corresponding to the high-sensitivity photodiode41, that is,

for S2-R2,

an image signal is generated by the correlated double sampling (CDS), but the signal level S2at low conversion efficiency and the reset level R2at low conversion efficiency are not continuously read, and thus the reset level R2at low conversion efficiency needs to be temporarily held in a line memory or the like.

Similarly, for a difference between the signal level S3and the reset level R3corresponding to the high-sensitivity photodiode41, that is,

for S3-R3,

an image signal is generated by delta data sampling (DDS).

Thereafter, for a difference between the signal level S4and the reset level R4of the low-sensitivity photodiode50, that is,

for S4-R4,

an image signal is generated by delta data sampling (DDS).

As a result, by combining four images corresponding to the pixel signals corresponding to S1-R1, S2-R2, S3-R3, and S4-R4, it is possible to configure an image having excellent low-illuminance characteristics, a high dynamic range, and no artifact of the object.

As described above, according to the second embodiment, in the state of the first floating diffusion region42alone functioning as the first charge modulation unit and in the state where the first floating diffusion region42functioning as the first charge modulation unit and the second floating diffusion region45functioning as the second charge modulation unit are coupled by the conversion efficiency switching transistor44functioning as the modulation switching unit, the charge accumulated in the high-sensitivity photodiode41functioning as the first photoelectric conversion unit is modulated into the voltage signal and the voltage signals having different conversion efficiencies are continuously read. Moreover, the charge accumulated in the high-sensitivity photodiode41functioning as the first photoelectric conversion unit and the charge overflowing from the high-sensitivity photodiode41functioning as the first photoelectric conversion unit during the accumulation period are modulated into the voltage signal and the voltage signal is read in the capacitance in which the first floating diffusion region42functioning as the first charge modulation unit and the second floating diffusion region45functioning as the second charge modulation unit are coupled. Moreover, the charge generated in the low-sensitivity photodiode50functioning as the second photoelectric conversion unit and accumulated in the in-pixel capacitance48functioning as the charge accumulation unit is modulated into the voltage signal and the voltage signal is read in the capacitance in which the first floating diffusion region42functioning as the first charge modulation unit, the second floating diffusion region45functioning as the second charge modulation unit, and the in-pixel capacitance48functioning as the charge accumulation unit are coupled. Therefore, excellent low-illuminance characteristics and an expanded high dynamic range can be obtained.

[3] Modification of Embodiments

FIG.13is an explanatory diagram of processing timing of a short-term exposure operation and a long-term exposure operation applicable to each of the above-described embodiments and modifications.

The present processing timing can be applied to each of the above-described embodiments and modifications.

InFIG.13, a short-term exposure operation SEI and a long-term exposure operation LEI are alternately performed.

Then, shutter timing SHS for short-term exposure time is set immediately before the short-term exposure operation SEI, and signal read timing RDS for short-term exposure time is provided immediately after the short-term exposure operation SEI.

By providing the short-term exposure operation SEI as described above, the dynamic range can be further expanded.

Similarly, shutter timing SHL for long-term exposure time is set immediately before the long-term exposure operation LEI, and signal read timing RDL for long-term exposure time is provided immediately after the long-term exposure operation LEI.

FIG.14is an explanatory diagram of a modification of processing timing of a short-term exposure operation and a long-term exposure operation.

The present processing timing can also be applied to each of the above-described embodiments and modifications.

By providing a line memory for the short-term exposure operation, it is possible to reduce the artifact of the moving object without providing an interval between the short-term exposure operation SEI and the long-term exposure operation LEI, as illustrated inFIG.4.

FIG.15is a diagram for describing a configuration example of an imaging device as an electronic device.

An imaging device60includes a solid-state imaging device61including the pixels10,10A,10B, or40of each of the above-described embodiments, an optical system62including a lens group and the like, a digital signal processor (DSP)63as a signal processing circuit that processes imaging data, a display unit64that includes a liquid crystal display, an organic EL display, or the like and displays a captured image and various types of information, an operation unit65that a user performs various operations such as an imaging instruction and data setting, a controller66that controls the entire imaging device60, a frame memory67that stores image data, a recording unit68that records the imaging data on a recording medium such as a hard disk or a memory card (not illustrated), and a power supply unit69that supplies power to the entire imaging device60.

In the above configuration, the DSP63, the display unit64, the operation unit65, the controller66, the frame memory67, the recording unit68, and the power supply unit69are connected to each other via a bus line.

According to the above configuration, since the above-described solid-state imaging device61including the pixels10,10A,10B, or40is used as an imaging element, it is possible to capture an image having excellent low illuminance characteristics, a high dynamic range, and few artifacts of the object.

Examples of an actual mode of the imaging device60include camera modules for mobile terminal devices such as a video camera, a digital still camera, and a smartphone.

FIG.16is a diagram for describing a configuration example of an imaging device as another electronic device.

An imaging device70includes a solid-state imaging device71including the pixels10,10A,10B, or40of each of the above-described embodiments, an optical system72including a lens group and the like, a DSP73as a signal processing circuit that processes imaging data, an interface unit74that performs an interface operation with an external device80, and a frame memory75that stores image data.

The imaging device70of the present mode performs imaging under the control of the external device80by power supplied from the external device80, and can be applied as, for example, a camera module or the like that captures a monitoring image around a vehicle by receiving power supply from the vehicle side under the control of an in-vehicle ECU or the like as the external device80.

In this case, the external device80includes an interface unit81that performs an interface operation with the imaging device70, an image processing unit82that applies image processing for obtaining desired image data (for example, a surrounding obstacle image, a sign recognition image, and the like) to the imaging data acquired via the interface unit81, a power supply unit83that supplies operation power to the imaging device70and the external device80, an external controller84that controls the imaging device70via the interface unit81, and a recording unit85that records the imaging data on a recording medium such as a hard disk and a memory card (not illustrated).

Examples of the application of such an imaging device70include an on-vehicle sensor that is provided on a peripheral surface (front surface, side surface, or rear surface) of an automobile, in a vehicle interior, or the like, for ensuring safe driving such as automatic stop, recognition of a state of a driver, or the like, and captures a periphery of the vehicle or an inside of the vehicle, a monitoring camera for remotely monitoring traveling vehicles and roads, and a distance measuring device.

Furthermore, the imaging device can be used as an imaging device for detecting and controlling the position, action (gesture) and the like of the user, having a main body of a home appliance (an air conditioner, a refrigerator, a microwave oven, or the like) as the external device80.

Moreover, the imaging device can also be used for person authentication, skin capture, or the like.

Note that embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Moreover, the present technology may be configured as follows.

A solid-state imaging device including:

a photoelectric conversion unit;

a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit;

a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit;

a second charge modulation unit;

a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit;

a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period; and

a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit,

in which,

in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and

further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit by the modulation switching unit and the capacitance connection unit.

A solid-state imaging device including:

a first photoelectric conversion unit;

a charge transfer unit configured to transfer a charge accumulated in the first photoelectric conversion unit;

a first charge modulation unit to which the charge is transferred from the first photoelectric conversion unit by the charge transfer unit;

a second charge modulation unit;

a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit;

a second photoelectric conversion unit;

a charge accumulation unit directly connected to the second photoelectric conversion unit and configured to accumulate a charge generated in the second photoelectric conversion unit during an accumulation period; and

a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit,

in which,

in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the first photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read,

the charge accumulated in the first photoelectric conversion unit and the charge overflowing from the first photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit and the second charge modulation unit, and

further, the charge generated in the second photoelectric conversion unit and accumulated in the charge accumulation unit is modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit.

The solid-state imaging device according to (2), further including:

a second charge transfer unit provided between the second photoelectric conversion unit and the charge accumulation unit and configured to transfer the charge accumulated in the second photoelectric conversion unit to the charge accumulation unit.

a charge resetting unit provided between the second charge modulation unit and a power supply, and configured to reset the charges in the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit after the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are read.

The solid-state imaging device according to (1), further including:

a third charge transfer unit provided between the photoelectric conversion unit and the charge accumulation unit and configured to transfer the charge overflowing from the photoelectric conversion unit during the accumulation period to the charge accumulation unit.

The solid-state imaging device according to (5), further including:

a charge resetting unit provided between the second charge modulation unit and a power supply and configured to reset charges of the first charge modulation unit and the second charge modulation unit before the charge accumulated in the photoelectric conversion unit is read.

A method of driving a solid-state imaging device including

a photoelectric conversion unit,

a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit,

a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit,

a second charge modulation unit,

a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period,

a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit, and

a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit,

the method including:

modulating the charge accumulated in the photoelectric conversion unit and continuously reading voltage signals having different conversion efficiencies in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit; and

further modulating the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period into a voltage signal and reading the voltage signal in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit by the modulation switching unit and the capacitance connection unit.

An electronic device provided with a solid-state imaging device including

a photoelectric conversion unit,

a charge transfer unit configured to transfer a charge accumulated in the photoelectric conversion unit,

a first charge modulation unit to which the charge is transferred from the photoelectric conversion unit by the charge transfer unit,

a second charge modulation unit,

a charge accumulation unit configured to accumulate a charge overflowing from the photoelectric conversion unit during an accumulation period,

a modulation switching unit configured to couple or divide the first charge modulation unit and the second charge modulation unit, and

a capacitance connection unit configured to couple or divide the second charge modulation unit and the charge accumulation unit, in which,

in a state of the first charge modulation unit alone and a state where the first charge modulation unit and the second charge modulation unit are coupled by the modulation switching unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and voltage signals having different conversion efficiencies are continuously read, and

further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit by the modulation switching unit and the capacitance connection unit.

REFERENCE SIGNS LIST