COMPOSITIONALLY-MODULATED CAPPING LAYER FOR A TRANSISTOR AND METHODS FOR FORMING THE SAME

A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.

BACKGROUND

Transistors made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration since they may be processed at low temperatures and thus, will not damage previously fabricated devices. For example, the fabrication conditions and techniques do not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Elements with the same reference numerals refer to the same element, and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise.

Current flow in a semiconducting metal oxide material is affected by the concentration of charge carriers and surface defect density, i.e., interface trap density Dit. As the channel length decreases, the short channel effect and back channel leakage current adversely impacts current-voltage characteristics of transistors, and in particular thin-film transistors. Further, high contact resistance between source/drain structures and a semiconductor channel material can degrade the on-current and the reliability of the transistor.

Generally, surfaces of a semiconducting metal oxide material are susceptible to formation of various types of electronic and structural defects, which may occur during a film deposition, gas treatment, plasma treatment, and/or impurity diffusion such as diffusion of hydrogen, oxygen, water vapor, and/or metallic impurities. In instances in which such defects are formed on the backside (opposite side) of a gate electrode, a back channel layer including defects as trap centers can be formed. Such defects may cause leakage current. In a negative bias operation, electrons may be trapped in the back channel layer. These trapped electrons may provide a short channel leakage path. This leakage path may induce an initial uncontrolled negative threshold voltage (Vt) shift, and can degrade negative bias stress instability (NBTI). Reducing the charge carrier concentration in a semiconducting metal oxide material in order to reduce electron trapping can result in a low on-current with a large positive threshold voltage shift.

According to an aspect of the present disclosure, an active layer including a semiconducting metal oxide material may be formed as a main semiconducting channel of a transistor (i.e., thin-film transistor). An in-process capping layer including a dielectric metal oxide material may be formed on the active layer. The dielectric metal oxide material can be selected from materials that can reduce the interface trap density at an interface with a subsequently deposited insulating cap layer. In other words, an interface between the dielectric metal oxide material with the dielectric material of the insulating cap layer may be configured to provide a lower interface trap density than an interface between the semiconducting metal oxide material with the dielectric material of the insulating cap layer. The dielectric metal oxide material can have a similar banding gap (which may be in a range from 2.5 eV to 3.5 eV) as the semiconducting metal oxide material. Further portions of the in-process capping layer that are exposed to a source cavity or a drain cavity are converted into conductive material portions. The dielectric metal oxide material includes a material that may be reduced, upon loss of oxygen atoms, into at least one metal, or may be converted into a conductive metal-rich non-stoichiometric metal oxide material upon ion implantation with at least one metallic element. Thus, a compositionally-modulated capping layer can be formed, which provides low contact resistance for the source structure and the drain structure, and reduces the interfacial trap density on the backside (i.e., the side that is distal from a gate electrode) of a semiconducting channel, and thus, reduces the leakage current and improves the transistor characteristics.

Referring toFIG.1, an exemplary structure according to an embodiment of the present disclosure is illustrated. The exemplary structure includes a substrate8. Generally, the substrate8comprises, and/or consists essentially of, at least one material selected from an insulating material, a semiconductor material, and a metallic material. In one embodiment, the substrate8may be a semiconductor substrate such as a commercially available silicon substrate. The substrate8may include a semiconductor material layer9at least at an upper portion thereof. The semiconductor material layer9may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon. In one embodiment, the substrate8may include a single crystalline silicon substrate including a single crystalline silicon material. The first structure may include a memory region100and a logic region200.

Shallow trench isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures720. Field effect transistors701may be formed over the top surface of the semiconductor material layer9. For example, each field effect transistor701may include a source electrode733, a drain electrode738, a semiconductor channel735that includes a surface portion of the substrate8extending between the source electrode733and the drain electrode738, and a gate structure750. The semiconductor channel735may include a single crystalline semiconductor material. Each gate structure750may include a gate dielectric layer753, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal-semiconductor alloy region743may be formed on each source electrode733, and a drain-side metal-semiconductor alloy region748may be formed on each drain electrode738.

One or more of the field effect transistors701in the CMOS circuitry700may include a semiconductor channel735that contains a portion of the semiconductor material layer9in the substrate8. In embodiments in which the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel735of each field effect transistor701in the CMOS circuitry700may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a plurality of field effect transistors701in the CMOS circuitry700may include a respective node that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed. For example, a plurality of field effect transistors701in the CMOS circuitry700may include a respective source electrode733or a respective drain electrode738that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed.

In one embodiment, the substrate8may include a single crystalline silicon substrate, and the field effect transistors701may include a respective portion of the single crystalline silicon substrate as a semiconducting channel. As used herein, a “semiconducting” element may refer to an element having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. As used herein, a “semiconductor material” may refer to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, a dielectric material or an insulating material refers to a material having electrical conductivity less than 1.0×10−6S/cm. All measurements are taken at the standard condition, i.e., at 0 degrees Celsius and at 1 atmospheric pressure.

Various metal interconnect structures formed within dielectric layers may be subsequently formed over the substrate8and the semiconductor devices thereupon (such as field effect transistors701). In an illustrative example, the dielectric layers may include, for example, a first dielectric layer601that may be a layer that surrounds the contact structure connected to the source and drains (sometimes referred to as a contact-level dielectric layer601), a first interconnect-level dielectric layer610, and a second interconnect-level dielectric layer630. The metal interconnect structures may include device contact via structures613formed in the first dielectric layer601and contact a respective component of the CMOS circuitry700, first metal line structures618formed in the first interconnect-level dielectric layer610, first metal via structures633formed in a lower portion of the second interconnect-level dielectric layer630, and second metal line structures638formed in an upper portion of the second interconnect-level dielectric layer630.

Each of the dielectric layers (601,610,630) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (613,618,633,638) may include at least one conductive material, which may be a combination of a metallic liner (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures633and the second metal line structures638may be formed as integrated line and via structures by a dual damascene process. The dielectric layers (601,610,630) are herein referred to as lower-lower-level dielectric layers. The metal interconnect structures (613,618,633,638) formed within in the lower-level dielectric layers are herein referred to as lower-level metal interconnect structures.

While the present disclosure is described using an embodiment wherein transistors, such as thin film transistors, may be formed over the second interconnect-level dielectric layer630, other embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level. Further, while the present disclosure is described using an embodiment in which a semiconductor substrate is used as the substrate8, embodiments are expressly contemplated herein in which an insulating substrate or a conductive substrate is used as the substrate8.

The set of all dielectric layer that are formed prior to formation of an array of transistors (e.g., thin-film transistors, TFTs) or an array of memory cells (e.g., ferroelectric memory cells) is collectively referred to as lower-level dielectric layers (601,610,630). The set of all metal interconnect structures that is formed within the lower-level dielectric layers (601,610,630) is herein referred to as metal interconnect structures (613,618,633,638). Generally, metal interconnect structures (613,618,633,638) formed within at least one lower-level dielectric layer (601,610,630) may be formed over the semiconductor material layer9that is located in the substrate8.

According to an aspect of the present disclosure, a transistor, such as thin film transistors (TFTs) may be subsequently formed in a metal interconnect level that overlies that metal interconnect levels that contain the lower-level dielectric layers (601,610,630) and the metal interconnect structures (613,618,633,638). In one embodiment, a planar dielectric layer having a uniform thickness may be formed over the lower-level dielectric layers (601,610,630). The planar dielectric layer is herein referred to as an insulating material layer635. The insulating material layer635includes a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating material layer635may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be used.

Generally, interconnect-level dielectric layers (such as the lower-level dielectric layer (601,610,630)) containing therein the metal interconnect structures (such as the metal interconnect structures (613,618,633,638)) may be formed over semiconductor devices. The insulating material layer635may be formed over the interconnect-level dielectric layers.

In one embodiment, the substrate8may include a single crystalline silicon substrate, and lower-level dielectric layers (601,610,630) embedding lower-level metal interconnect structures (613,618,633,638) may be located above the single crystalline silicon substrate. Field effect transistors701including a respective portion of the single crystalline silicon substrate as a channel may be embedded within the lower-level dielectric layers (601,610,630). The field effect transistors may be subsequently electrically connected to at least one of a gate electrode, a source electrode, and a drain electrode of one or more, or each, of transistors, such as thin film transistors, to be subsequently formed.

An etch stop dielectric layer636may be optionally formed over the insulating material layer635. The etch stop dielectric layer636includes an etch stop dielectric material providing higher etch resistance to an etch chemistry during a subsequently anisotropic etch process that etches a dielectric material to be subsequently deposited over the etch stop dielectric layer636. For example, the etch stop dielectric layer636may include silicon carbide nitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. The thickness of the etch stop dielectric layer636may be in a range from 3 nm to 40 nm, such as from 4 nm to 30 nm, although lesser and greater thicknesses may also be used.

Referring toFIGS.2A-2C, a region of the intermediate structure for forming a transistor (e.g., thin film transistor) is illustrated after formation of a gate contact via structure12. For example, a via cavity may be formed through the etch stop dielectric layer636and the insulating layer635on a respective one of the underlying metal interconnect structures (not illustrated inFIGS.2A-2C), and at least one metallic material may be deposited in the via cavity. Excess portions of the at least one metallic material may be removed from above the horizontal plane including the top surface of the etch stop dielectric layer636by a planarization process such as a chemical mechanical planarization process. A remaining portion of the at least one metallic material constitutes the gate contact via structure12.

Referring toFIGS.3A-3C, a continuous gate electrode material layer15L, a continuous gate dielectric material layer10L, a continuous semiconducting material layer20L, and a continuous metal layer27L may be sequentially deposited over the etch stop dielectric layer636.

The continuous gate electrode material layer15L comprises at least one conductive gate electrode material. The at least one conductive gate electrode material may include, for example, a metallic barrier liner material (such as TiN, TaN, and/or WN) and a metallic fill material (such as Cu, W, Mo, Co, Ru, etc.). Other suitable metallic barrier liner and metallic fill materials are within the contemplated scope of disclosure. The continuous gate electrode material layer15L may be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the continuous gate electrode material layer15L may be in a range from 20 nm to 200 nm, although lesser and greater thicknesses may also be used.

The continuous gate dielectric material layer10L may be formed over the continuous gate electrode material layer15L. The continuous gate dielectric material layer10L may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, etc.), or a stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. In a non-limiting illustrative example, the continuous gate dielectric material layer10may comprise, and/or may consist essentially of at least one dielectric metal oxide material (such as aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, lanthanum oxide, hafnium silicate, etc.), silicon oxide, silicon nitride, an ONO stack, a ferroelectric material layer, or other memory material layers known in the art. The continuous gate dielectric material layer10L may be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thickness of the continuous gate dielectric material layer10L may be in a range from 1 nm to 13 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses may also be used.

In one embodiment, the continuous semiconducting material layer20L includes a semiconducting metal oxide material. The continuous semiconducting material layer20L may be an un-patterned (i.e., blanket) semiconductor material layer. In one embodiment, the continuous semiconducting material layer20L may comprise a compound semiconductor material. In one embodiment, the semiconducting material includes a material providing electrical conductivity in a range from 1.0 S/m to 1.0×105S/m upon suitable doping with electrical dopants (which may be p-type dopants or n-type dopants). Exemplary semiconducting materials that may be used for the continuous semiconducting material layer20L include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Generally, the continuous semiconducting material layer20L may comprise oxides of at least one metal, such as at least two metals and/or at least three metals, selected from In, Zn, Ga, Sn, Pb, Zr, Sr, Ru, Mn, Mg, Nb, Ta, Hf, Al, La, Sc, Ti, V, Cr, Mo, W, Fe, Co, Ni, Pd, Ir, Ag, and any combination of the above. In an non-limiting example, the continuous semiconducting material layer20L may have a composition of InxGayZnzMaOw, in which M can be at least one metal selected from Ti, Al, Ag, W, Ce, Sn, V, and Sc; 0<x<1; 0≤y≤1; 0≤z≤1; 0≤a≤0.5; and 1≤w≤1.5. The value of w may be selected such that the continuous semiconducting material layer20L is stoichiometric or near stoichiometric. Some of the metal elements may be present at a dopant concentration, e.g., at an atomic percentage less than 1.0%. Other suitable semiconducting materials are within the contemplated scope of disclosure. In one embodiment, the semiconducting material of the continuous semiconducting material layer20L may include indium gallium zinc oxide.

In one embodiment, the continuous semiconducting material layer20L comprises, and/or consists essentially of, a semiconducting metal oxide material having a first enthalpy of oxide formation. The continuous semiconducting material layer20L may include a polycrystalline semiconducting material, or an amorphous semiconducting material that may be subsequently annealed into a polycrystalline semiconducting material having a greater average grain size. The continuous semiconducting material layer20L may be deposited by physical vapor deposition although other suitable deposition processes may be used. The thickness of the continuous semiconducting material layer20L may be in a range from 2 nm to 50 nm, such as from 3 nm to 30 nm and/or from 4 nm to 15 nm, although lesser and greater thicknesses may also be used.

The continuous metal layer27L may be formed by deposition of at least one metal that can be subsequently converted into a dielectric metal oxide material having a second enthalpy of formation that is greater than the first enthalpy of formation of the semiconducting metal oxide material of the continuous semiconducting material layer20L. In embodiments in which the continuous metal layer27L comprises at least two metals, the alloy of the at least two metals may have a second enthalpy of formation that is greater than the first enthalpy of formation of the semiconducting metal oxide material of the continuous semiconducting material layer20L. The thickness of the continuous metal layer27L may be in a range from 0.1 nm to 1.5 nm. The thickness of the continuous metal layer27L may be greater than 0.1 nm, and/or greater than 0.2 nm, and/or greater than 0.3 nm, and/or greater than 0.5 nm, and/or greater than 0.7 nm, and/or greater than 1.0 nm, and/or greater than 1.2 nm. Further, the thickness of the continuous metal layer27L may be less than 1.5 nm, and/or less than 1.2 nm, and/or less than 1.0 nm, and/or less than 0.7 nm, and/or less than 0.5 nm, and/or less than 0.3 nm, and/or less than 0.2 nm.

The at least one metal of the continuous metal layer27L may be selected such that a dielectric metal oxide material that is subsequently formed by oxidation of the at least one metal has a similar band gap as the semiconducting metal oxide material of the continuous semiconducting material layer20L. In one embodiment, the at least one metal of the continuous metal layer27L may be selected such that the dielectric metal oxide material that is subsequently formed by oxidation of the at least one metal has a higher dissolution bonding energy than the semiconducting metal oxide material of the continuous semiconducting material layer20L. In one embodiment, the at least one metal of the continuous metal layer27L can be selected such that the dielectric metal oxide material that is subsequently formed by oxidation of the at least one metal has a higher dissolution bonding energy than InO or ZnO. Generally, the at least one metal of the continuous metal layer27L may comprise, and/or may consist of, one or more transition metals that satisfy the above requirement. In one embodiment, the at least one metal of the continuous metal layer27L may comprise, and/or may consist essentially of, one or more of Ti, Ba, Ta, W, Mo, Hf, Y, La, etc.

Referring toFIGS.4A-4C, an oxidation process may be performed to convert the continuous metal layer27L into a semiconducting metal oxide layer consisting of a dielectric metal oxide material. This semiconducting metal oxide layer functions as a capping layer for the continuous semiconducting material layer20L, and is herein referred to as a continuous capping material layer26L. The oxidation process may comprise a plasma oxidation process and/or a thermal oxidation process. The continuous capping material layer26L comprises, and/or consists essentially of, an oxide of the at least one metal of the continuous metal layer. In one embodiment, the continuous capping material layer26L may comprise, and/or may consist essentially of, titanium oxide, barium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, another transition metal oxide, or an alloy thereof.

The duration of the oxidation process may be selected such that the entirety of the continuous metal layer27L is converted into the continuous capping material layer26L. The thickness of the continuous capping material layer26L may be in a range from 0.1 nm to 2.0 nm. The thickness of the continuous capping material layer26L may be greater than 0.1 nm, and/or greater than 0.2 nm, and/or greater than 0.3 nm, and/or greater than 0.5 nm, and/or greater than 0.7 nm, and/or greater than 1.0 nm, and/or greater than 1.2 nm, and/or greater than 1.5 nm. Further, the thickness of the continuous capping material layer26L may be less than 2.0 nm, and/or less than 1.5 nm, and/or less than 1.2 nm, and/or less than 1.0 nm, and/or less than 0.7 nm, and/or less than 0.5 nm, and/or less than 0.3 nm, and/or less than 0.2 nm. The ratio of the thickness of the continuous capping material layer26L to the thickness of the continuous semiconducting material layer20L may be in a range from 0.005 to 0.5, such as from 0.01 to 0.25, and/or from 0.02 to 0.1.

In one embodiment, the semiconducting metal oxide material of the continuous semiconducting material layer20L may have a first enthalpy of formation, and the dielectric metal oxide material of the continuous capping material layer26L may have a second enthalpy of formation that is greater than the first enthalpy of formation. In one embodiment, the dielectric metal oxide material of the continuous capping material layer26L may have a greater thermal stability in a temperature range above 400 degrees Celsius than InO, ZnO, and the semiconducting metal oxide material of the continuous semiconducting material layer20L.

Generally, the dielectric metal oxide material of the continuous capping material layer26L may have a band gap that is about the same as the band gap of the semiconducting metal oxide material of the continuous semiconducting material layer20L. For example, both the semiconducting metal oxide material of the continuous semiconducting material layer20L and the dielectric metal oxide material of the continuous capping material layer26L may have band gaps in a range from 2.5 eV to 3.5 eV. Thus, the stack of the continuous semiconducting material layer20L and the continuous capping material layer26L can function as a heterojunction semiconductor structure in which the continuous semiconducting material layer20L functions as a main channel material, and the continuous capping material layer26L functions as a back channel surface layer controlling the magnitude of the back channel current.

In one embodiment, the dielectric metal oxide material of the continuous capping material layer26L provides a lower interface defect density than the semiconducting metal oxide material of the continuous semiconducting material layer20L. In an illustrative example, the semiconducting metal oxide material of the continuous semiconducting material layer20L may provide an interface defect density that is greater than 5×1011/(cm2×eV) at an interface with a silicon oxide material, and the dielectric metal oxide material of the continuous capping material layer26L may provide an interface defect density that is in a range from 1×1011/(cm2×eV) to 5×1011/(cm2×eV) at an interface with a silicon oxide material. Generally, the dielectric metal oxide material of the continuous capping material layer26L can provide an interfacial trap density that is less than 5×1011/(cm2×eV) at an interface with an overlying insulating material.

The threshold voltage shift through use of the dielectric metal oxide material of the continuous capping material layer26L as a back channel material in a transistor may suppress shift in the threshold voltage during operation of the transistor. For example, it is estimated that the threshold voltage shift in a thin film transistor using the dielectric metal oxide material of the continuous capping material layer26L is less than 200 mV after operation of the thin film transistor for 1.0×106seconds.

Referring toFIGS.5A-5C, a continuous insulating cap layer30L may be optionally deposited over the continuous capping material layer26L. The continuous insulating cap layer30L includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride. The continuous insulating cap layer30L may be deposited by a chemical vapor deposition process. The thickness of the continuous insulating cap layer30L may be in a range from 2 nm to 30 nm, such as from 4 nm to 15 nm, although lesser and greater thicknesses may also be used.

Referring toFIGS.6A-6C, a photoresist layer (not shown) may be applied over the continuous insulating cap layer30L, and may be lithographically patterned to form at least one discrete photoresist material portion, such as a two-dimensional array of discrete photoresist material portions. An anisotropic etch process may be performed to etch unmasked portions of the continuous insulating cap layer30L, continuous capping material layer26L, the continuous semiconducting material layer20L, the continuous gate dielectric material layer10L, and the continuous gate electrode material layer15L. Each patterned portion of the continuous insulating cap layer30L comprises an insulating cap layer30. Each patterned portion of the continuous capping material layer26L comprises an in-process capping layer26. Each patterned portion of the continuous semiconducting material layer20L comprises a active layer20, which is an active layer including an oxide of a binary metal alloy. Each patterned portion of the continuous gate dielectric material layer10L comprises a gate dielectric layer10. Each patterned portion of the continuous gate electrode material layer15L comprise a gate electrode15. As used herein, an “in-process” element refers to an element that is subsequently modified either in shape or in material composition.

Each vertical stack of a gate electrode15, a gate dielectric layer10, an active layer20, an in-process capping layer26, and an insulating cap layer30may have vertically coincident sidewalls, i.e., sidewalls that are located within a same vertical plane. Each stack of a gate electrode15and a gate dielectric layer10is herein referred to a gate stack (15,10). The photoresist layer may be subsequently removed, for example, by ashing or dissolved by solution.

In one embodiment, each layer within a vertical stack of a gate electrode15, a gate dielectric layer10, an active layer20, an in-process capping layer26, and an insulating cap layer30may have a same area in a plan view (such as a see-through top-down view) along a vertical direction that is perpendicular to the interface between the active layer20and the gate dielectric layer10. In one embodiment, the gate electrode15laterally extends horizontally with a uniform gate electrode thickness, and has a same area as the active layer20, the gate dielectric layer10, the in-process capping layer26, and the insulating cap layer30in the plan view.

Referring toFIGS.7A-7C, a dielectric material such as undoped silicate glass, a doped silicate glass, or organosilicate glass may be deposited over each stack of a gate electrode15, a gate dielectric layer10, an active layer20, an in-process capping layer26, and an insulating cap layer30to form a dielectric material layer40. The dielectric material layer40may be deposited by a self-planarizing deposition method (such as spin-on coating) or may be planarized after deposition (for example, by performing a chemical mechanical polishing process). The vertical distance between the top surface of each insulating cap layer30and the top surface of the dielectric material layer40may be in a range from 20 nm to 200 nm, although lesser and greater thicknesses may also be used.

Referring toFIGS.8A-8C, a photoresist layer (not shown) may be applied over the dielectric material layer40, and may be lithographically patterned to form discrete openings therein. The pattern of the discrete openings in the photoresist layer may be transferred through the dielectric material layer40and the insulating cap layer30by an anisotropic etch process to form a source cavity51and a drain cavity59over each active area20.

According to an aspect of the present disclosure, the anisotropic etch process may have an etch chemistry that etches the materials of the dielectric material layer40and the insulating cap layer30selective to the material of the in-process capping layer26. In other words, the anisotropic etch process may etch the materials of the dielectric material layer40and the insulating cap layer30without etching the material of the in-process capping layer26. In this embodiment, the in-process capping layer26functions as an etch stop layer for the anisotropic etch process. Portions of the in-process capping layer26may be physically exposed at the bottom of the source cavity51and at the bottom of the drain cavity59. The top surface of the active layer20can be covered by the in-process capping layer26. The in-process capping layer26may have a uniform thickness throughout.

The lateral spacing between the bottom periphery of the source cavity51and the bottom periphery of the drain cavity59defines the channel length of the transistor (e.g., TFT) to be subsequently formed. The channel length may be in a range from 1 nm to 100 nm, such as from 2 nm to 50 nm, although lesser and greater channel lengths may also be used. The in-process capping layer26protects the active layer20from plasma damage. Thus, the defect density of the semiconducting metal oxide material in the active layer20does not increase due to the anisotropic etch process that forms the source cavity51and the drain cavity59. Further, the dielectric metal oxide material of the in-process capping layer26provides a reduced interface defect density Dit at the interface with the insulating cap layer30relative to a hypothetical structure in which the active layer20directly contacts the insulating cap layer30. For example, the in-process capping layer26has an interfacial trap density that is less than 5×1011/(cm2×eV) at an interface with an overlying insulating material, i.e., at an interface with the insulating cap layer30.

The in-process capping layer26may function as an etch stop layer during formation of the source cavity51and the drain cavity59. The collateral etching of the material of the in-process capping layer26during the anisotropic etch process that forms the source cavity51and the drain cavity59is preferably minimal. In one embodiment, the thickness of the remaining portion of the in-process capping layer26underlying the source cavity51or the drain cavity59can be greater than 30%, and preferably greater than 50%, and even more preferably greater than 70%, and/or greater than 80%, and/or greater than 90%, and/or greater than 95%, of the thickness of the in-process capping layer26prior to the anisotropic etch process.

Referring toFIGS.9A-9C, a region of the first configuration of an embodiment structure is illustrated after formation of a compositionally-modulated capping layer28. Specifically, a reduction process can be performed on the exposed portions of the in-process capping layer26. The dielectric metal oxide material within the exposed portions of the in-process capping layer26are reduced into at least one metal that is free of oxygen. In other words, the oxygen atoms in the exposed portions of the in-process capping layer26are removed during the reduction process, thereby reducing the dielectric metal oxide material of the physically exposed portions of the in-process capping layer26into metallic material portions consisting essentially of the at least one metal (as provided in the continuous capping material layer26L). In one embodiment, the reduction process comprises a hydrogen plasma treatment process. The hydrogen plasma reacts with the oxygen atoms in the in-process capping layer26to generate water vapors, which are volatilized and pumped out of the plasma treatment chamber. Atoms of the at least one metal that loses the oxygen atoms coalesce to form metal plates, which comprise the conductive capping material portions28M.

The plasma intensity and the duration of the hydrogen plasma treatment process may be selected such that each portion of the in-process capping layer26having an areal overlap with the source cavity51or with the drain cavity59in a plan view is converted into a metallic material portion, which is herein referred to as a conductive capping material portion28M. The conductive caping material portions28M may have the same material composition as the continuous metal layer27L. For example, the conductive capping material portion28M may comprise, and/or may consist essentially of, titanium, barium, tantalum, tungsten, molybdenum, hafnium, yttrium, lanthanum, another transition metal, or an alloy thereof. Each conductive capping material portion28M may consist essentially of the at least one metal, and may provide sheet resistance less than 100 Ohms per square.

The portion of the in-process capping layer26that is not reduced into a metallic material constitutes a dielectric capping material portion28D. Generally, loss of the oxygen atoms can cause reduction of the thickness in the conductive capping material portion28M relative to the thickness of the dielectric capping material portion28D. The thickness of each conductive capping material portion28M ma be in a range from 40% to 70% of the thickness of the dielectric capping material portion28D.

Generally, physically exposed portions of the in-process capping layer26can be converted into a first conductive capping material portion28M that underlie the source cavity51and into the second conductive capping material portion28M that underlie the drain cavity59. The dielectric capping material portion28D comprises a remaining portion of the dielectric metal oxide material. The combination of the dielectric capping material portion28D and the conductive capping material portion28M constitutes a compositionally-modulated capping layer28. Thus, the in-process capping layer26can be converted into the compositionally-modulated capping layer28.

The compositionally-modulated capping layer28overlies the active layer20, and comprises a first conductive capping material portion28M, a second conductive capping material portion28M, and a dielectric capping material portion28D. The dielectric metal oxide material is an oxide of at least one metal, and the first conductive capping material portion28M and the second conductive capping material portion28M comprise, and/or consist essentially of, the at least one metal. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M are formed by reduction of the dielectric metal oxide into the at least one metal. The reduction of the dielectric metal oxide into the at least one metal is effected by performing a hydrogen plasma treatment process.

The plasma reduction process reduces the material of the physically exposed portions of the in-process capping layer26isotropically. The plasma energy and the duration of the plasma during the plasma reduction process can be selected such that the boundary between the reduced portions of the in-process capping layer26(i.e., the conductive capping material portions28M) and the unreduced portion of the in-process capping layer26(i.e., the dielectric capping material portion28D) shifts by a distance that is greater than the thickness of the in-process capping layer26. In one embodiment, each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion28M by a uniform offset distance uod, which is the plasma reduction distance. The plasma reduction distance may be in a range from 100% to 150%, such as from 100% to 120%, of the thickness of the in-process capping layer26(which is the same as the thickness of the dielectric capping material portion28D). Each sidewall of the source cavity51and the drain cavity59comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion28M by a uniform offset distance uod, which can be the plasma reduction distance.

Generally, the material composition of the conductive capping material portions28M may be the same as the material composition of the continuous metal layer27L, and may consist of the at least one metal of the continuous metal layer27L. If the continuous metal layer27L comprises at least two metals, the conductive capping material portions28M may comprise the at least two metals. Each atomic ratio between the at least two metals in the conductive capping material portions28M may be the same as a respective corresponding atomic ratio between the at least two metals within the continuous metal layer27L. Furthermore, each atomic ratio between the at least two metals within the dielectric capping material portion28D equals a corresponding atomic ratio between the at least two metals within the first conductive capping material portion28M and within the second conductive capping material portion28M. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M may be metal portions that are free of oxygen atoms.

As discussed above, the collateral etching of the material of the in-process capping layer26during the anisotropic etch process that forms the source cavity51and the drain cavity59is preferably minimal. The thickness of the conductive capping material portions28M is directly proportional to the thickness of the remaining portion of the in-process capping layer26underlying the source cavity51or the drain cavity59after the anisotropic etch process. The areal density of the at least one metal in the conductive capping material portions28M can be greater than 30%, and preferably greater than 50%, and even more preferably greater than 70%, and/or greater than 80%, and/or greater than 90%, and/or greater than 95%, of the areal density of the at least one metal within the continuous capping material layer26L as formed at the processing steps ofFIGS.4A-4C. In one embodiment, a first areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along a vertical direction within the first conductive capping material portion28M is in a range from 30% to 100% (such as from 50% to 90% and/or from 60% to 80%) of a second areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along the vertical direction within the dielectric capping material portion28D. As used herein, an areal density of an element refers to a value generated by integrating the volume density of the element along a thickness direction (such as a vertical direction).

Referring toFIGS.10A-10C, a region of the first configuration of an embodiment structure is illustrated after formation of a source structure52and a drain structure56. At least one conductive material may be deposited in the source cavity51and drain cavity59and over the dielectric material layer40. The at least one conductive material may include a metallic liner material and a metallic fill material. The metallic liner material may include a conductive metallic nitride or a conductive metallic carbide such as TiN, TaN, WN, TiC, TaC, and/or WC. The metallic fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used.

Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the dielectric material layer40by a planarization process, which may use a chemical mechanical polishing (CMP) process and/or a recess etch process. Other suitable planarization processes may be used. Each remaining portion of the at least one conductive material filling a source cavity51constitutes a source structure52. Each remaining portion of the at least one conductive material filling a drain cavity59constitutes a drain structure56. In one embodiment, the at least one conductive material may comprise a combination of the metallic liner material and the metallic fill material described above.

In one embodiment, each source structure52may include a source metallic liner53that is a remaining portion of the metallic liner material, and a source metallic fill material portion54that is a remaining portion of the metallic fill material. Each drain structure56may include a drain metallic liner57that is a remaining portion of the metallic liner material, and a drain metallic fill material portion58that is a remaining portion of the metallic fill material.

The compositionally-modulated capping layer28overlies the active layer20, and comprises a first conductive capping material portion28M, a second conductive capping material portion28M, and a dielectric capping material portion28D. The insulating cap layer30overlies the compositionally-modulated capping layer28. The dielectric material layer40overlies the insulating cap layer30, and laterally surrounds the source structure52, the drain structure56, the active layer20located on the gate dielectric layer10, and the compositionally-modulated capping layer28.

The source structure52may be formed in the source cavity51, and the drain structure56can be in the drain cavity59. The source structure52and the drain structure56can be formed on the first conductive capping material portion28M and the second conductive capping material portion28M, respectively. The source structure52can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the first conductive capping material portion28M. The drain structure56can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the second conductive capping material portion28M. In one embodiment, each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion28M by a uniform offset distance uod.

Referring toFIGS.11A-11C, a second configuration of an embodiment structure is illustrated after formation of conductive capping material portions28I. The second configuration of the exemplary structure can be derived from the exemplary structure illustrated inFIGS.8A-8Cby performing an ion implantation process that implants atoms of at least one additional metal into the physically exposed portions of the in-process capping layer26. The at least one additional metal may comprise any transition metal, aluminum, indium, or gallium. The at least one additional metal may, or may not be, the same as one or more of the at least one metal in the in-process capping layer26. In one embodiment, the at least one additional metal that is implanted into the physically exposed portions of the in-process capping layer26may be different from each of the at least one metal in the in-process capping layer26. In one embodiment, the at least one additional metal may comprise one or more transition metal elements exhibiting low diffusivity, such as refractory metal elements (e.g., tungsten, niobium, molybdenum, tantalum, and rhenium).

The exposed portions of the in-process capping layer26can be converted not into metal-rich metal oxide material portions by introducing atoms of the at least one additional metal into the exposed portions of the in-process capping layer26. The atoms of the at least one additional metal can be introduced into the in-process capping layer26by performing an ion implantation process. According to an aspect of the present disclosure, the energy of the ions of the at least one additional metal can be selected such that a predominant fraction (i.e., more than 50%) of the implanted ions are implanted into the physically exposed portions of the in-process capping layer26. Further, the dose of the implanted ions can be selected such that the metal-rich metal oxide material portions become conductive. The conductive metal-rich metal oxide material portions are herein referred to as conductive capping material portions28I.

The oxygen deficiency ratio of conductive capping material portions28I can be defined as the ratio of a first number to a second number, the first number being the number of additional oxygen atoms that would be desired to convert the material of the conductive capping material portions28I into a stoichiometric dielectric metal oxide material, and the second number being the total number of oxygen atoms in the stoichiometric dielectric metal oxide material. The oxygen deficiency ratio of conductive capping material portions28I may be in a range from 0.1 to 0.8, such as from 0.15 to 0.6 and/or from 0.2 to 0.5 and/or from 0.25 to 0.4.

Generally, the physically exposed portions of the in-process capping layer26can be converted into conductive material portions that include a first conductive capping material portion28I underlying the source cavity51and a second conductive capping material portion28I underlying the drain cavity59. The portion of the in-process capping layer26that is not implanted with the atoms of the at least one additional metal is herein referred to as a dielectric capping material portion28D. In one embodiment, the dielectric metal oxide material of the dielectric capping material portion28D is an oxide of at least one metal, and the first conductive capping material portion28I and the second conductive capping material portion28I comprise the at least one metal in the dielectric metal oxide material, and further comprises atoms of the at least one additional metal that is introduced by the ion implantation process. In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I can be conductive non-stoichiometric metal oxide portions, and can be formed by implantation of atoms of the at least one additional metal that is different from the at least one metal.

In one embodiment, the energy of the ion implantation can be selected such that the atomic concentration of the at least one additional metal in the first conductive capping material portion28I and the second conductive capping material portion28I decreases with a vertical distance downward from a horizontal plane including a top surface of the first conductive capping material portion28I and a top surface of the second conductive capping material portions28I. In one embodiment, the implanted atoms of the at least one additional metal generally increases the thickness of the implanted portions of the in-process capping layer26. In one embodiment, the dose of the ion implantation process can be selected such that the conductive capping material portions28I have a thickness that is greater than the thickness of the dielectric capping material portion28D.

The first conductive capping material portion28I and a top surface of the second conductive capping material portions28I comprise atoms of the at least one metal that is present within the dielectric capping material portion28D. In one embodiment, a fraction of the implanted ions of the at least one additional metal can be lodged in portions of the active layer20that are proximal to the conductive capping material portions28I, and render the implanted portions of the active layer non-stoichiometric, i.e., metal-rich due to the presence of atoms of the at least one additional metal. In this embodiment, a source-side metal-rich metal oxide region22S can be formed underneath the first conductive capping material portion28I that underlies the source cavity51, and a drain-side metal-rich metal oxide region22D can be formed underneath the second conductive capping material portion28I that underlies the drain cavity59. The thickness of the source-side metal-rich metal oxide region22S and the drain-side metal-rich metal oxide region22D may be in a range from 0.1 nm to 2 nm, such as from 0.2 nm to 1 nm. In one embodiment, the atomic concentration of atoms of the at least one additional metal may decrease with a downward distance from a horizontal plane including the top surfaces of the conductive capping material portions28I.

As discussed above, the collateral etching of the material of the in-process capping layer26during the anisotropic etch process that forms the source cavity51and the drain cavity59is preferably minimal. The thickness of the conductive capping material portions28I is generally proportional to the thickness of the remaining portion of the in-process capping layer26underlying the source cavity51or the drain cavity59after the anisotropic etch process. The areal density of the at least one metal in the conductive capping material portions28I can be greater than 30%, and preferably greater than 50%, and even more preferably greater than 70%, and/or greater than 80%, and/or greater than 90%, and/or greater than 95%, of the areal density of the at least one metal within the continuous capping material layer26L as formed at the processing steps ofFIGS.4A-4C. In one embodiment, a first areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along a vertical direction within the first conductive capping material portion28I is in a range from 30% to 100% (such as from 50% to 90% and/or from 60% to 80%) of a second areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along the vertical direction within the dielectric capping material portion28D.

In one embodiment, the number of implanted metal atoms in the conductive capping material portions28I may be greater than the number of pre-exiting metal atoms as provided in the physically exposed portions of the in-process capping layer26. In this embodiment, an areal density of the at least one metal as obtained by integrating a density of the at least one metal along a vertical direction within the first conductive capping material portion28I (or within the second conductive capping material portion28I) may be less than a total areal density of the at least one additional metal as obtained by integrating a volume density of the at least one additional metal along the vertical direction within the first conductive capping material portion28I (or within the second conductive capping material portion28I). In some embodiments, the oxygen deficiency ratio of conductive capping material portions28I may be in a range from 0.5 to 0.8.

Referring toFIGS.12A-12C, a region of the second configuration of the exemplary structure is illustrated after formation of a source structure52and a drain structure56. Generally, the processing steps described with reference toFIGS.10A-10Ccan be performed to form the source structure52and the drain structure56. In one embodiment, each source structure52may include a source metallic liner53and a source metallic fill material portion54. Each drain structure56may include a drain metallic liner57and a drain metallic fill material portion58.

The compositionally-modulated capping layer28overlies the active layer20, and comprises a first conductive capping material portion28I, a second conductive capping material portion28I, and a dielectric capping material portion28D. The insulating cap layer30overlies the compositionally-modulated capping layer28. The dielectric material layer40overlies the insulating cap layer30, and laterally surrounds the source structure52, the drain structure56, the active layer20located on the gate dielectric layer10, and the compositionally-modulated capping layer28.

The source structure52can be formed in the source cavity, and the drain structure56can be in the drain cavity. The source structure52and the drain structure56can be formed on the first conductive capping material portion28I and the second conductive capping material portion28I, respectively. The source structure52can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the first conductive capping material portion28I. The drain structure56can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the second conductive capping material portion28I. In one embodiment, each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion28I by a uniform offset distance uod.

Referring toFIGS.13A-13C, a third configuration of an embodiment structure is illustrated after formation of conductive capping material portions28I according to an embodiment of the present disclosure. The third configuration of the exemplary structure can be derived from the second configuration of the exemplary structure by adjusting the energy of the ion implantation process that is performed to implant atoms of the at least one additional metal. Specifically, the energy of the ion implantation process can be lowered such that the implanted ions do not enter the active layer20. In this embodiment, the source-side metal-rich metal oxide region22S and the drain-side metal-rich metal oxide region22D are not formed in the third configuration of the exemplary structure. The conductive capping material portions28I can be in direct contact with the top surface of the active layer20. Generally, the third configuration of the exemplary structure can have the same structural and compositional features as the second configuration of the exemplary structure except the presence of the source-side metal-rich metal oxide region22S and the drain-side metal-rich metal oxide region22D.

The atomic concentration of the at least one additional metal in the first conductive capping material portion28I and the second conductive capping material portion28I decreases with a vertical distance downward from a horizontal plane including a top surface of the first conductive capping material portion28I and a top surface of the second conductive capping material portions28I. In one embodiment, the implanted atoms of the at least one additional metal generally increases the thickness of the implanted portions of the in-process capping layer26. In one embodiment, the dose of the ion implantation process can be selected such that the conductive capping material portions28I have a thickness that is greater than the thickness of the dielectric capping material portion28D.

Referring toFIGS.14A-14C, a region of the third configuration of an embodiment structure is illustrated after formation of a source structure52and a drain structure56. Generally, the processing steps described with reference toFIGS.10A-10Ccan be performed to form the source structure52and the drain structure56. In one embodiment, each source structure52may include a source metallic liner53and a source metallic fill material portion54. Each drain structure56may include a drain metallic liner57and a drain metallic fill material portion58.

The compositionally-modulated capping layer28overlies the active layer20, and comprises a first conductive capping material portion28I, a second conductive capping material portion28I, and a dielectric capping material portion28D. The insulating cap layer30overlies the compositionally-modulated capping layer28. The dielectric material layer40overlies the insulating cap layer30, and laterally surrounds the source structure52, the drain structure56, the active layer20located on the gate dielectric layer10, and the compositionally-modulated capping layer28.

The source structure52can be formed in the source cavity, and the drain structure56can be in the drain cavity. The source structure52and the drain structure56can be formed on the first conductive capping material portion28I and the second conductive capping material portion28I, respectively. The source structure52can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the first conductive capping material portion28I. The drain structure56can vertically extend through the dielectric material layer40and the insulating cap layer30, and can contact a top surface of the second conductive capping material portion28I. In one embodiment, each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion28I by a uniform offset distance uod.

Referring toFIG.15, the embodiment structure is illustrated after performing additional processing steps. The embodiment structure illustrated inFIG.15may be derived from any configuration of the embodiment structure illustrated inFIGS.10A-10C,12A-12C, or14A-14C by subsequently forming additional structures thereupon. In some embodiments, second metal via structures632may be formed through the dielectric material layer40and the insulating material layer635on a respective one of the third metal line structures639concurrent with, before, or after, formation of the source structures52and the drain structures56.

A dielectric layer, which is herein referred to as a third line-level dielectric layer637, may be deposited over the dielectric material layer40. Third metal line structures639may be formed in the third line-level dielectric layer637on a respective one of the metallic structures (52,56,632) embedded within the dielectric material layer40.

Additional metal interconnect structures embedded in additional dielectric layers may be subsequently formed over the transistors, such as thin film transistors, and the third line-level dielectric layer637. In an illustrative example, the dielectric layers may include, for example, a fourth interconnect-level dielectric layer640, a fifth interconnect-level dielectric layer650, etc. The additional metal interconnect structures may include third metal via structures (not illustrated) and fourth metal lines648embedded in the fourth interconnect-level dielectric layer640, fourth metal via structures652and fifth metal line structures658embedded in the fifth interconnect-level dielectric layer650, etc.

Optionally, memory cells150may be formed below, above, or at the same level as, the transistors. In embodiments in which the transistors are formed as a two-dimensional periodic array, the memory cells150may be formed as a two-dimensional periodic array of memory cells150. Each memory cell150may include a magnetic tunnel junction, a ferroelectric tunnel junction, a phase change memory material, or a vacancy-modulated conductive oxide material portion. Further, each memory cell150may include a first electrode126including a metallic material, and a second electrode158including a metallic material and protecting an underlying data-storing portion of the memory cell150. A memory element is provided between the first electrode126(i.e., the bottom electrode) and the second electrode158(i.e., the top electrode).

In an illustrative example, in embodiments in which the memory cell150includes a magnetic tunnel junction, the memory cell150may include a layer stack including, from bottom to top, a first electrode126, a metallic seed layer128that facilitates crystalline growth of overlying material layers, a synthetic antiferromagnet (SAF) structure140, a tunneling barrier layer146, a free magnetization layer148, and a second electrode158. While the present disclosure is described using an embodiment in which the transistors, such as thin film transistors, are used as access transistors for memory cells150, embodiments are expressly contemplated herein in which the transistors are used as logic devices, as components of a peripheral circuit for a memory array, or for any other semiconductor circuitry.

In one embodiment, the substrate8may include a single crystalline silicon substrate. Lower-level dielectric layers (601,610,630) embedding lower-level metal interconnect structures (613,618,633,638) may be located between the single crystalline silicon substrate and the insulating layer635. Field effect transistors701including a respective portion of the single crystalline silicon substrate as a channel may be embedded within the lower-level dielectric layers (601,610,630), and may be electrically connected to at least one of the gate electrodes15, the source structures52, and the drain structures56.

Referring toFIG.16, a first flowchart illustrates the general processing steps for manufacturing the semiconductor devices of the present disclosure.

Referring to step1610andFIGS.1-6C, a stack can be formed over a substrate8. The stack comprises a gate electrode15, a gate dielectric layer10, an active layer20comprising a semiconducting metal oxide material, an in-process capping layer26comprising a dielectric metal oxide material.

Referring to step1620andFIGS.7A-7C, a dielectric material layer40can be formed over the stack.

Referring to step1630andFIGS.8A-8C, a source cavity51and a drain cavity59can be formed through the dielectric material layer40such that portions of the in-process capping layer26are exposed underneath the source cavity51and the drain cavity59.

Referring to step1640andFIGS.9A-14, the portions of the in-process capping layer26can be converted into conductive material portions that include a first conductive capping material portion (28M,28I) underlying the source cavity51and a second conductive capping material portion (28M,28I) underlying the drain cavity59.

In one embodiment, the method may further comprise: forming a source structure52in the source cavity51; and forming a drain structure56in the drain cavity59. In one embodiment, the method may further comprise performing a reduction process after on the exposed portions of the in-process capping layer26, whereby the dielectric metal oxide material within the portions of the in-process capping layer26are reduced into at least one metal that is free of oxygen. In one embodiment, the reduction process comprises a hydrogen plasma treatment process.

In one embodiment, the method further comprises converting the exposed portions of the in-process capping layer26into metal-rich metal oxide material portions by introducing atoms of at least one metal into the exposed portions of the in-process capping layer26. In one embodiment, the atoms of the at least one metal are introduced into the in-process capping layer26by performing an ion implantation process.

Referring toFIG.17, a second flowchart illustrates the general processing steps for manufacturing the semiconductor devices of the present disclosure.

Referring to step1710andFIGS.1-6C, a stack comprising a gate electrode15, a gate dielectric layer10, an active layer20comprising a semiconducting metal oxide material, and an in-process capping layer26comprising a dielectric metal oxide material can be formed over a substrate8.

Referring to step1720andFIGS.7A-9C,11A-11C, and13A-13C, the in-process capping layer26can be converted into a compositionally-modulated capping layer28. The compositionally modulated capping layer comprises a first conductive capping material portion (28M,28I) and a second conductive capping material portion (28M,28I) that are formed by converting portions of the dielectric metal oxide into conductive material portions, and a dielectric capping material portion28D that is a remaining portion of the dielectric metal oxide material.

Referring to step1730andFIGS.10A-10C,12A-12C,14A-14C, and15, a source structure52and a drain structure56can be formed on the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I), respectively.

In one embodiment, the method further comprises: forming a dielectric material layer40over the stack; and forming a source cavity51and drain cavity59through the dielectric material layer40, wherein the portions of the dielectric metal oxide that are subsequently converted into conductive material portions are exposed underneath the source cavity51and the drain cavity59. In one embodiment, the source structure52is formed in the source cavity51; and the drain structure56is formed in the drain cavity59. In one embodiment, the stack comprises an insulating cap layer30overlying the in-process capping layer26; and the source cavity51and the drain cavity59are formed by performing an anisotropic etch chemistry that etches materials of the dielectric material layer40and the insulating cap layer30selective to the dielectric metal oxide.

In one embodiment, the dielectric metal oxide material is an oxide of at least one metal; and the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I) comprise the at least one metal. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M consist essentially of the at least one metal. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M are formed by reduction of the dielectric metal oxide into the at least one metal. In one embodiment, the reduction of the dielectric metal oxide into the at least one metal is effected by performing a hydrogen plasma treatment process.

In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I are non-stoichiometric metal oxide portions. In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I are formed by implantation of atoms of at least one additional metal that is different from the at least one metal. In one embodiment, an atomic concentration of the at least one additional metal in the first conductive capping material portion28I decreases with a vertical distance downward from a horizontal plane including a top surface of the first conductive capping material portion28I.

Referring toFIG.18, a third flowchart illustrates the general processing steps for manufacturing the semiconductor devices of the present disclosure.

Referring to step1810andFIGS.1-6C, a stack including a gate electrode15, a gate dielectric layer10, and an active layer20comprising a semiconducting metal oxide material can be formed over a substrate8.

Referring to step1820andFIGS.7A-9C,11A-11C, and13A-13C, a compositionally-modulated capping layer28overlying the active layer20and comprising a first conductive capping material portion (28M,28I), a second conductive capping material portion (28M,28I), and a dielectric capping material portion28D can be formed.

Referring to step1830andFIGS.10A-10C,12A-12C,14A-14C, and15, a source structure52contacting a top surface of the first conductive capping material portion (28M,28I) can be formed.

Referring to step1840andFIGS.10A-10C,12A-12C,14A-14C, and15, a drain structure56contacting a top surface of the second conductive capping material portion (28M,28I) can be formed. Each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion (28M,28I) by a uniform offset distance uod.

In one embodiment, the method comprises: forming an in-process capping layer26comprising a dielectric metal oxide material over the active layer20; and converting portions of the in-process capping layer26into the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I), wherein the dielectric capping material portion28D comprises a remaining portion of the dielectric metal oxide material. In one embodiment, the active layer20comprises a semiconducting metal oxide material having a first enthalpy of oxide formation; the dielectric capping material portion28D comprises a dielectric metal oxide material having a second enthalpy of oxide formation that is higher the first enthalpy of oxide formation; and the dielectric capping material portion provides an interfacial trap density that is less than 5×1011/(cm2×eV) at an interface with an overlying insulating material.

Referring to all drawings and according to various aspects of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor comprises: a gate electrode15located over a substrate8; a gate dielectric layer10located on the gate electrode15; an active layer20located on the gate dielectric layer10; a compositionally-modulated capping layer28overlying the active layer20and comprising a first conductive capping material portion (28M,28I), a second conductive capping material portion (28M,28I), and a dielectric capping material portion28D; a dielectric material layer40overlying the compositionally-modulated capping layer28; a source structure52vertically extending through the dielectric material layer40and contacting a top surface of the first conductive capping material portion (28M,28I); and a drain structure56vertically extending through the dielectric material layer40and contacting a top surface of the second conductive capping material portion (28M,28I).

In one embodiment, the dielectric capping material portion28D comprise a dielectric metal oxide material that is an oxide of at least one metal; and the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I) comprise the at least one metal. In one embodiment, a first areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along a vertical direction within the first conductive capping material portion (28M,28I) is in a range from 30% to 100% (such as from 50% to 90% and/or from 60% to 80%) of a second areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along the vertical direction within the dielectric capping material portion28D. In one embodiment, the at least one metal comprises at least two metals; and each atomic ratio between the at least two metals within the dielectric capping material portion28D equals a corresponding atomic ratio between the at least two metals within the first conductive capping material portion (28M,28I). In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M are metal portions that are free of oxygen atoms. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M consist of the at least one metal.

In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I are non-stoichiometric metal oxide portions. In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I comprises at least one additional metal that is different from the at least one metal. In one embodiment, an areal density of the at least one metal as obtained by integrating a density of the at least one metal along a vertical direction within the first conductive capping material portion28I is less than a total areal density of the at least one additional metal as obtained by integrating a volume density of the at least one additional metal along the vertical direction within the first conductive capping material portion28I.

In one embodiment, the active layer20comprises a semiconducting metal oxide material having a first enthalpy of oxide formation; and the dielectric capping material portion28D comprises a dielectric metal oxide material having a second enthalpy of oxide formation that is higher the first enthalpy of oxide formation. In one embodiment, the dielectric capping material portion provides an interfacial trap density that is less than 5×1011/(cm2×eV) at an interface with an overlying insulating material.

According to another aspect of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor comprises: a gate electrode15located over a substrate8; a gate dielectric layer10located on the gate electrode15; an active layer20located on the gate dielectric layer10; a compositionally-modulated capping layer28overlying the active layer20and comprising a first conductive capping material portion (28M,28I), a second conductive capping material portion (28M,28I), and a dielectric capping material portion28D; a source structure52contacting a top surface of the first conductive capping material portion (28M,28I); and a drain structure56contacting a top surface of the second conductive capping material portion (28M,28I), wherein each sidewall of the source structure52and the drain structure56comprises a respective bottom periphery that is spaced from a top periphery of a respective conductive capping material portion (28M,28I) by a uniform offset distance uod.

In one embodiment, the semiconductor structure comprises: an insulating cap layer30overlying the compositionally-modulated capping layer28; and a dielectric material layer40overlying the insulating cap layer30and laterally surrounding the source structure52, the drain structure56, the active layer20located on the gate dielectric layer10, and the compositionally-modulated capping layer28. In one embodiment, the dielectric capping material portion28D comprise a dielectric metal oxide material that is an oxide of at least one metal; and the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I) comprise the at least one metal.

According to yet another aspect of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor comprises: a gate electrode15located over a substrate8; a gate dielectric layer10located on the gate electrode15; an active layer20located on the gate dielectric layer10and comprising a semiconducting metal oxide material; a compositionally-modulated capping layer28overlying the active layer20and comprising a first conductive capping material portion (28M,28I), a second conductive capping material portion (28M,28I), and a dielectric capping material portion28D comprising a dielectric metal oxide material that is an oxide of at least one metal; a source structure52contacting a top surface of the first conductive capping material portion (28M,28I); and a drain structure56contacting a top surface of the second conductive capping material portion (28M,28I), wherein: the first conductive capping material portion (28M,28I) and the second conductive capping material portion (28M,28I) comprise the at least one metal; and a first areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along a vertical direction within the first conductive capping material portion (28M,28I) is in a range from 30% to 100% (such as from 50% to 90% and/or from 60% to 80%) of a second areal density of the at least one metal as obtained by integrating a volume density of the at least one metal along the vertical direction within the dielectric capping material portion28D.

In one embodiment, the semiconductor structure comprises a dielectric material layer40overlying the compositionally-modulated capping layer28and laterally surrounding the source structure52and the drain structure56. In one embodiment, the at least one metal comprises at least two metals; and each atomic ratio between the at least two metals within the dielectric capping material portion28D equals a corresponding atomic ratio between the at least two metals within the first conductive capping material portion (28M,28I).

In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M are metal portions that are free of oxygen atoms. In one embodiment, the first conductive capping material portion28M and the second conductive capping material portion28M consist of the at least one metal. In one embodiment, the first conductive capping material portion28I and the second conductive capping material portion28I are non-stoichiometric metal oxide portions which comprises at least one additional metal that is different from the at least one metal.

The various embodiments of the present disclosure can be used to provide thin film transistors that reduces the short channel effect in the backside channel region by reducing the interface defect density, while providing reduced contact resistance between an active layer20and each of source structure52and the drain structure56. The thin film transistors of the present disclosure may be integrated in a same semiconductor structure with various additional types of semiconductor devices, non-limiting examples of which include MOSFETs, FinFETs, sensor devices, various cache memory devices, and MEMS devices.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Each embodiment described using the term “comprises” also inherently discloses additional embodiments in which the term “comprises” is replaced with “consists essentially of” or with the term “consists of,” unless expressly disclosed otherwise herein. Whenever two or more elements are listed as alternatives in a same paragraph of in different paragraphs, a Markush group including a listing of the two or more elements is also impliedly disclosed. Whenever the auxiliary verb “can” is used in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device can provide an equivalent result. As such, the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.