FIELD EFFECT TRANSISTOR WITH ASYMMETRICAL SOURCE/DRAIN REGION AND METHOD

A device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

BACKGROUND

DETAILED DESCRIPTION

Terms indicative of relative degree, such as “about,” “substantially,” and the like, should be interpreted as one having ordinary skill in the art would in view of current technological norms.

The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, active area spacing between nanostructure devices is generally uniform, source/drain epitaxy structures are symmetrical, and a metal gate surrounds four sides of the nanostructures (e.g., nanosheets). Gate-drain capacitance (“Cgd”) is increased due to larger metal gate endcap and increased source/drain epitaxy size.

Embodiments of the disclosure reduce gate-drain capacitance by reducing metal gate endcap and source/drain epitaxy size. Active area spacing is also reduced. In some embodiments, a wall structure is formed at cell boundaries. The wall structure may be a multi-layer structure. Source/drain epitaxies adjacent the wall structure are cut or trimmed to prevent merger of neighboring source/drain epitaxies. By reducing the metal gate endcap and source/drain epitaxy lateral dimensions, gate-drain capacitance may be reduced. As such, device performance is boosted, and active area spacing between nanostructure devices may be reduced, which saves chip area.

FIGS.1A-1Sillustrate diagrammatic perspective and cross-sectional top and side views of a portion of an IC device10fabricated according to embodiments of the present disclosure, where the IC device10includes nanostructure devices20A-20E, which may be gate-all-around FETs (GAAFETs).FIG.1Ais a diagrammatic perspective view of a portion of the IC device10in accordance with various embodiments.FIG.1Bis a diagrammatic top view of the portion of the IC device10including the nanostructure devices20A-20E.FIG.1Cis a diagrammatic cross-sectional side view of a portion of the IC device10including the nanostructure devices20A-20E along line C-C shown inFIG.1B.FIG.1Dis a diagram of region175having configuration different from that shown inFIG.1C.FIGS.1E and1Fare detailed views of region150shown inFIG.1Cin accordance with various embodiments.FIG.1Gis a diagrammatic cross-sectional side view of the portion of the IC device10along line G-G shown inFIG.1B.FIG.1His a diagrammatic cross-sectional side view of a portion of the IC device10along line H-H shown inFIG.1B. Certain features may be removed from view intentionally in the views ofFIGS.1A-1Hfor simplicity of illustration.

The nanostructure devices20A-20E may include at least an N-type FET (NFET) or a P-type FET (PFET) in some embodiments. Integrated circuit devices such as the IC device10frequently include transistors having different threshold voltages based on their function in the IC device. For example, input/output (IO) transistors typically have the highest threshold voltages, core logic transistors typically have the lowest threshold voltages, and a third threshold voltage between that of the IO transistors and that of the core logic transistors may also be employed for certain other functional transistors, such as static random access memory (SRAM) transistors. Some circuit blocks within the IC device10may include two or more NFETs and/or PFETs of two or more different threshold voltages.

The nanostructure devices20A-20E are formed over and/or in a substrate110, and generally include gate structures200A-200C straddling and/or wrapping around semiconductor channels, alternately referred to as “nanostructures,” located over semiconductor fins321-325protruding from, and separated by, isolation structures361,362. The channels are labeled “22AX” to “22CX,” where “X” is an integer from 1 to 5, corresponding to the five transistors20A-20E, respectively. Each gate structure200A-200C controls current flow through the channels22A1-22C5.

In many IC devices, it is beneficial for the gate structures of two or more neighboring nanostructure devices to be electrically connected. In a typical process, material layers of gate structures are formed over a large number of adjacent semiconductor fins, and isolation structures formed before or after the material layers are used to “cut” the material layers to isolate certain portions of the material layers from other portions. Each portion of the material layers may be one or more gate structures corresponding to one or more nanostructure devices. For illustrative purposes, in the configuration shown inFIGS.1A-1H, two gate isolation structures99isolate three gate structures200A-200C, such that the gate structure200B and the gate structures200A,200C are electrically isolated from each other (seeFIG.1C, for example). The gate isolation structures99are alternatively referred to as “dielectric plugs99.” The gate structure200B overlies and wraps around the nanostructures22of the nanostructure devices20B-20D. It should be understood that “wrapping around” includes the meaning of surrounding three or more sides of the nanostructures22. For example, as shown inFIG.1C, the gate structure200B extends between nanostructure22B2and nanostructures22A2,22C2so as to abut upper, lower and right sides of the nanostructure22B2without substantially or fully abutting the left side of the nanostructure22B2(e.g., the side of the nanostructure22B2facing nanostructure22B1). As another example,FIGS.1Eand IF show nanostructure22B3in expanded view, in which the gate structure200B abuts upper, lower and left sides of the nanostructure22B3, and partially abuts the right side of the nanostructure22B3(FIG.1E) or does not abut the right side of the nanostructure22B3(FIG.1F). As shown inFIG.1A, two sidewalls of the nanostructures22may face in the positive or negative X-axis direction, respectively, and are not abutted by a gate structure200. As such, as shown inFIG.1A, the gate structures200A-200C may each “wrap around” respective nanostructures22in cross-section, e.g., in the Y-Z plane illustrated inFIG.1A.

Referring toFIG.1H, the channels22(e.g., the channels22A2,22B2,22C2) are laterally abutted by source/drain regions82along the X-axis direction, and covered and surrounded by the gate structure200B. The gate structure200B controls flow of electrical current through the channels22A2-22C2to and from the source/drain regions82based on voltages applied at the gate structure200B and at the source/drain regions82. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

FIG.1Gillustrates the source/drain regions82in the Y-Z plane. InFIG.1G, source/drain regions82A,82B,82C,82D,82E, which may be referred to collectively as the source/drain regions82, overlie fins321,322,323,324,325, respectively. The source/drain regions82have asymmetrical cross-sectional profile in the Y-Z plane, as shown. For example, the source/drain region82C has a first lateral extension82EX1that extends laterally beyond the fin323and the nanostructures22thereover in a first direction (e.g., the negative Y-axis direction) by a first width W1, and a second lateral extension82EX2that extends laterally beyond the fin323and the nanostructures22in a second direction (e.g., the positive Y-axis direction) by a second width W2. The first and second widths W1, W2are different from each other. In some embodiments, the first width W1is in a range of about 10 nm to about 20 nm, and the second width W2is smaller than the first width W1, such as in a range of about 0 nm to about 10 nm. The first width W1may be larger than the second width W2by about 0 nm to about 15 nm, such as by about 1 nm to about 15 nm. If the first width W1is larger than the second width W2by more than about 15 nm, the source/drain regions82may be insufficiently large, resulting in resistance that is too high. If the first width W1is larger than the second width W2by too little, neighboring source/drain regions82(e.g., the source/drain region82B and the source/drain region82C) may merge instead of being kept separate, resulting in electrical bridging between device cells. Generally, neighboring source/drain regions82may be kept separate by trimming one or more sides of the source/drain regions82(or so-called “epitaxial cut”), reducing size of the source/drain regions82, or employing higher sidewalls during epitaxial growth to grow the source/drain regions82to a smaller size.

In some embodiments, the fins321-325include silicon. The fins321-325may not be present. In some embodiments, the nanostructure device20B is an NFET, and the source/drain regions82thereof include silicon phosphorous (SiP). In some embodiments, the nanostructure device20B is a PFET, and the source/drain regions82thereof include silicon germanium (SiGe).

The channels22A2-22C2each include a semiconductive material, for example silicon or a silicon compound, such as silicon germanium, or the like. The channels22A2-22C2are nanostructures (e.g., having sizes that are in a range of a few nanometers) and may also each have an elongated shape and extend in the X-direction. In some embodiments, the channels22A2-22C2each have a nano-wire (NW) shape, a nano-sheet (NS) shape, a nano-tube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of the channels22A2-22C2in the Y-Z plane may be rectangular, round, square, circular, elliptical, hexagonal, or combinations thereof.

In some embodiments, the lengths (e.g., measured in the X-direction) of the channels22A2-22C2may be different from each other, for example due to tapering during a fin etching process. In some embodiments, length of the channel22A2may be less than a length of the channel22B2, which may be less than a length of the channel22C2. The channels22A2-22C2each may not have uniform thickness, for example due to a channel trimming process used to expand spacing (e.g., measured in the Z-direction) between the channels22A2-22C2to increase gate structure fabrication process window. For example, a middle portion of each of the channels22A2-22C2may be thinner than the two ends of each of the channels22A2-22C2. Such shape may be collectively referred to as a “dog-bone” shape, and is illustrated inFIG.1H.

In some embodiments, the spacing between the channels22A2-22C2(e.g., between the channel22B2and the channel22A2or the channel22C2) is in a range between about 8 nanometers (nm) and about 12 nm. In some embodiments, a thickness (e.g., measured in the Z-axis direction) of each of the channels22A2-22C2is in a range between about 5 nm and about 8 nm. In some embodiments, a width (e.g., measured in the Y-axis direction, not shown inFIG.1H, orthogonal to the X-Z plane) of each of the channels22A2-22C2is at least about 8 nm.

The gate structure200B is disposed over and between the channels22A2-22C2, respectively. In some embodiments, the gate structure200B is disposed over and between the channels22A2-22C2, which are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure200B includes an interfacial layer (IL)210, one or more gate dielectric layers600, one or more work function tuning layers900(shown inFIG.4), and a conductive fill layer290.

The interfacial layer210, which may be an oxide of the material of the channels22A2-22C2, is formed on exposed areas of the channels22A2-22C2and the top surface of the fin322. The interfacial layer210promotes adhesion of the gate dielectric layers600to the channels22A2-22C2. In some embodiments, the interfacial layer210has thickness of about 5 Angstroms (A) to about 50 Angstroms (A). In some embodiments, the interfacial layer210has thickness of about 10 A. The interfacial layer210having thickness that is too thin may exhibit voids or insufficient adhesion properties. The interfacial layer210being too thick consumes gate fill window, which is related to threshold voltage tuning and resistance as described above. In some embodiments, the interfacial layer210is doped with a dipole, such as lanthanum, for threshold voltage tuning.

In some embodiments, the gate dielectric layer600includes at least one high-k gate dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer600has thickness of about 5 A to about 100 A.

In some embodiments, the gate dielectric layer600may include dopants, such as metal ions driven into the high-k gate dielectric from La2O3, MgO, Y2O3, TiO2, Al2O3, Nb2O5, or the like, or boron ions driven in from B2O3, at a concentration to achieve threshold voltage tuning. As one example, for N-type transistor devices, lanthanum ions in higher concentration reduce the threshold voltage relative to layers with lower concentration or devoid of lanthanum ions, while the reverse is true for P-type devices. In some embodiments, the gate dielectric layer600of certain transistor devices (e.g., IO transistors) is devoid of the dopant that is present in certain other transistor devices (e.g., N-type core logic transistors or P-type IO transistors). In N-type IO transistors, for example, relatively high threshold voltage is desirable, such that it may be preferable for the IO transistor high-k dielectric layers to be free of lanthanum ions, which would otherwise reduce the threshold voltage.

In some embodiments, the gate structure200B further includes one or more work function metal layers, represented collectively as work function metal layer900. When configured as an NFET, the work function metal layer900of the nanostructure device20B may include at least an N-type work function metal layer, an in-situ capping layer, and an oxygen blocking layer. In some embodiments, the N-type work function metal layer is or comprises an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The in-situ capping layer is formed on the N-type work function metal layer, and may comprise TiN, TiSiN, TaN, or another suitable material. The oxygen blocking layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type work function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen blocking layer may be formed of a dielectric material that can stop oxygen from penetrating to the N-type work function metal layer, and may protect the N-type work function metal layer from further oxidation. The oxygen blocking layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the work function metal layer900includes more or fewer layers than those described.

The work function metal layer900may further include one or more barrier layers comprising a metal nitride, such as TiN, WN, MoN, TaN, or the like. Each of the one or more barrier layers may have thickness ranging from about 5 A to about 20 A. Inclusion of the one or more barrier layers provides additional threshold voltage tuning flexibility. In general, each additional barrier layer increases the threshold voltage. As such, for an NFET, a higher threshold voltage device (e.g., an IO transistor device) may have at least one or more than two additional barrier layers, whereas a lower threshold voltage device (e.g., a core logic transistor device) may have few or no additional barrier layers. For a PFET, a higher threshold voltage device (e.g., an IO transistor device) may have few or no additional barrier layers, whereas a lower threshold voltage device (e.g., a core logic transistor device) may have at least one or more than two additional barrier layers. In the immediately preceding discussion, threshold voltage is described in terms of magnitude. As an example, an NFET IO transistor and a PFET IO transistor may have similar threshold voltage in terms of magnitude, but opposite polarity, such as +1 Volt for the NFET IO transistor and −1 Volt for the PFET IO transistor. As such, because each additional barrier layer increases threshold voltage in absolute terms (e.g., +0.1 Volts/layer), such an increase confers an increase to NFET transistor threshold voltage (magnitude) and a decrease to PFET transistor threshold voltage (magnitude).

The gate structure200B also includes conductive fill layer290. The conductive fill layer290may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. Between the channels22A2-22C2, the conductive fill layer290are circumferentially surrounded (in the cross-sectional view) by the one or more work function metal layers900, which are then circumferentially surrounded by the gate dielectric layers600. The gate structure200B may also include a glue layer that is formed between the one or more work function layers900and the conductive fill layer290to increase adhesion. The glue layer is not specifically illustrated inFIGS.1A-1Hfor simplicity. It should be understood that “fill” includes the meaning of fully filled or partially filled. For example, the conductive fill layer290shown inFIG.1Hpartially fills space between gate spacers41above the uppermost nanostructure22A2.

The nanostructure devices20A-20E also include gate spacers41and inner spacers74that are disposed on sidewalls of the gate dielectric layer600and the IL210. The inner spacers74are disposed between the channels22A2-22C2. The gate spacers41and the inner spacers74may include a dielectric material, for example a low-k material such as SiOCN, SiON, SiN, or SiOC.

The nanostructure devices20A-20E may include source/drain contacts120(a single source/drain contact120is shown inFIG.1H) that are formed over the source/drain regions82. The source/drain contacts120may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. The source/drain contacts120may be surrounded by barrier layers (not shown), such as SiN or TiN, which help prevent or reduce diffusion of materials from and into the source/drain contacts120. A silicide layer118may also be formed between the source/drain regions82and the source/drain contacts120, so as to reduce the source/drain contact resistance. The silicide layer118may contain a metal silicide material, such as cobalt silicide in some embodiments, or TiSi in some other embodiments.

The nanostructure devices20A-20E further include an interlayer dielectric (ILD)130. The ILD130provides electrical isolation between the various components of the nanostructure devices20A-20E discussed above, for example between the gate structure200B and the source/drain contacts120. An etch stop layer131may be formed prior to forming the ILD130, and may be positioned laterally between the ILD130and the gate spacers41and vertically between the ILD130and the source/drain regions82.

FIGS.1C and1Gare cross-sectional views along the lines C-C and G-G shown inFIG.1B, respectively. The cross-sectional views shown inFIGS.1C and1Gare orthogonal to the semiconductor fins321-325and parallel to the gate structures200A-200E, cutting at the gate structures200A-200C (FIG.1C) and the source/drain regions82(FIG.1G), respectively.

Wall structures300may be located at cell boundaries so as to prevent in-cell active area jog from degrading wall dielectric deposition, etch back, or both. The wall structures300include a liner dielectric layer302, an etch stop layer304and a core dielectric layer306. The liner dielectric layer302may have thickness in a range of about 2 nm to about 5 nm. Thickness of the liner dielectric layer302that is greater than about 5 nm may result in insufficiently low gate-drain capacitance Cgd. Thickness of the liner dielectric layer302less than about 2 nm may result in reduced gate control due to insufficient lateral extension of the gate structure200(see dimension D1ofFIG.1E, for example). The core dielectric layer306may have thickness (e.g., width) greater than about 15 nm. Thickness of the core dielectric layer306being less than about 15 nm may result in insufficient active area spacing, such that source/drain regions82are too short, causing difficulty driving the channels22by the gate structures200. As shown inFIG.1C, the liner dielectric layer302and the core dielectric layer306may be the same or substantially the same material, such as SiN, SiCN, SiOC, SiOCN or the like. The liner and core dielectric layers302,306being the same or substantially the same material may simplify etching operations due to similar etch selectivity for the liner and core dielectric layers302,306.

The etch stop layer304is beneficial to formation of the gate structure200, which has pi shape that may be trimmed up to the etch stop layer304without overetching into the core dielectric layer306. The etch stop layer304is between the liner dielectric layer302and the core dielectric layer306. In some embodiments, the etch stop layer304has thickness in a range of about 0.1 nm to about 2 nm, such as about 1 nm. Generally, the etch stop layer304should be thinner than the liner and core dielectric layers302,306, and should have high etch selectivity against the liner dielectric layer302, which is beneficial during a gate trimming operation that forms the structure shown inFIGS.1E,1F. If the etch stop layer304is too thick (e.g., greater than about 2 nm), the etch stop layer304may be consumed or partially consumed during recessing of the isolation regions361,362, which may result in defects.

Gate isolation structures99are between the gate structures200A,200B,200C, such that the gate structures200A,200B,200C are electrically isolated from each other. As shown inFIG.1C, a gate isolation structure99is between the gate structures200A,200B, and a gate isolation structure99is between the gate structures200B,200C. The gate isolation structures99may land on isolation regions361,362or on wall structures300. For example, the gate isolation structure99between the gate structures200A,200B lands on wall structure300, and the gate isolation structure99between the gate structures200B,200C lands on the isolation region362. In some embodiments, the gate isolation structures99include SiN or other suitable dielectric material.

InFIG.1D, the gate isolation structure99extends into the wall structure300, such as to a level about coplanar with upper surfaces of fins321,322. The gate isolation structure99may extend into the wall structure300by a distance H1shown inFIG.1D. The distance H1is in a range from substantially the upper surface of the uppermost channels22A1,22A2to substantially the upper surface304U of the etch stop layer304. In some embodiments, the distance H1is equal to or substantially equal to distance between the upper surface of the uppermost channels22A1-22A5and the upper surface of the isolation regions361,362, such that the gate isolation structures99that land on the wall structure300and the isolation region362have substantially the same height in the Z-axis direction. Generally, a single device, such as the device10, will include gate isolation structures99either landing on the upper surface of the wall structure300as shown inFIG.1Cor extending into the wall structure300as shown inFIG.1D, and will not include a combination thereof. In some embodiments, masking techniques may be employed to form the gate isolation structures99ofFIG.1Cand the gate isolation structures ofFIG.1Din different regions of the same device, such that gate isolation structures99landing on the upper surface of wall structures300and gate isolation structures99extending into wall structures300are formed (e.g., deposited) in different operations.

FIGS.1E and1Fillustrate spacer portions302S of the liner dielectric layer302.FIG.1Ealso illustrates sides of the channel22B3, including an upper side22U, a lower side22L, a first lateral side22LA1and a second lateral side22LA2. The lower side22L is opposite the upper side22U. The first lateral side22LA1is in contact with the gate structure200B and faces away from the wall structure300, for example, in a first lateral direction, such as the negative Y-direction. The second lateral side22LA2is opposite the first lateral side22LA2, is in contact with the wall structure300, and faces toward the wall structure300, for example, in direction opposite the first lateral direction, such as the positive Y-direction. Third and fourth lateral sides of the channel22B3are not illustrated inFIG.1E, asFIG.1Eis a cross-sectional diagram in the Y-Z plane. Each of the channels22includes the upper, lower and first to fourth lateral sides. InFIG.1H, a third lateral side22LA3and a fourth lateral side22LA4of the channel22A2are labeled. The third lateral side22LA3faces in a second lateral direction (e.g., the negative X-direction) transverse the first lateral direction. The fourth lateral side22LA4faces in a direction opposite the second lateral direction, such as the positive X-direction.

The spacer portions302S are positioned between the nanostructures22(e.g., the nanostructure22B3shown inFIGS.1E and1F) and the etch stop layer304and the core dielectric layer306. As shown inFIGS.1E and1F, the spacer portion302S is in contact with sidewalls of the channel22B3and the etch stop layer304. Upper and lower surfaces of the spacer portion302S are in contact with the gate structure200, such as the gate dielectric layer600. Distance or vertical extension D2between the upper surface of the channel22B3and the upper surface of the spacer portion302S is in a range of 0 nm to about 2 nm.FIG.1Fillustrates the spacer portion302S when the distance D2is zero, such that the upper surface of the spacer portion302S is level with the upper surface of the nanostructure22B3. Distance or lateral extension D1between the etch stop layer304and the nanostructure22B3is in a range of about 2 nm to about 5 nm, such as about 3 nm to about 5 nm. The distances D1, D2are beneficial for short channel effect control and alternating current capacitance penalty reduction. For example, when the lateral extension D1is greater than about 5 nm, the gate-drain capacitance Cgd may be insufficiently small, and distance from the gate structure200to the source/drain regions82may be too short. When the lateral extension D1is less than about 2 nm, control of the gate structures200may be difficult.

As shown inFIGS.1E and1F, due to trimming of the liner dielectric layer302, the conductive fill layer290may include extension portions290E adjacent the wall structure300and the channels22. For example, inFIG.1E, the extension portions290E are laterally between the channel22B3and the etch stop layer304and the core dielectric layer306. InFIG.1F, the extension portions290E are laterally between the gate dielectric layer600and the etch stop layer304and the core dielectric layer306. In some embodiments, when the gate dielectric layer600is sufficiently thick, the extension portions290E are not present, for example, when the gate dielectric layer600is thick enough to merge in the space between the channel22B3and the etch stop layer304during deposition of the gate dielectric layer600. As shown inFIG.1E, the gate structure200is in contact with the upper, lower and first lateral sides22U,22L,22LA1of the channel22B3, and is in partial contact with the second lateral side22LA2of the channel22B3, while being isolated from the third and fourth lateral sides22LA3,22LA4of the channel22B3. As shown inFIG.1F, the gate structure200is in contact with the upper, lower and first lateral sides22U,22L,22LA1of the channel22B3, while being isolated from the second, third and fourth lateral sides22LA2,22LA3,22LA4of the channel22B3. The gate structure200is described in greater detail with reference toFIG.4.

A second conductive layer297may be on the gate structure200, as shown inFIG.1A. The second conductive layer297may be or include a metal, such as tungsten. The gate isolation structures99may extend through the second conductive layer297.

In some embodiments, a capping layer is positioned over the gate structures200A-200C. The capping layer may be a self-aligned capping (SAC) layer. The capping layer provides protection to the underlying gate structures200A-200C, and may also act as a CMP stop layer when planarizing the source/drain contacts120following formation thereof. The capping layer may be a dielectric layer including a dielectric material, such as SiO2, SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, BN, or other suitable dielectric material. Between the capping layer and the conductive layer204is the optional hard dielectric layer. The hard dielectric layer may prevent current leakage following one or more etching operations, which may be performed to form gate contacts, source/drain contacts120, isolation structures (e.g., source/drain contact isolation structures150), or the like. In some embodiments, the hard dielectric layer is or comprises a dielectric material that is harder than, for example, the capping layer, such as aluminum oxide, or other suitable dielectric material. The hard dielectric layer may also be between the capping layer and the spacer layer41. The gate isolation structures99may extend through the capping layer.

FIG.1Iis a cross-sectional side view of the device10in accordance with various embodiments. In some embodiments, a wall structure300A includes the liner dielectric layer302and the core dielectric layer306while the etch stop layer304is not present, as shown inFIG.1I. The etch stop layer304, which may be referred to as the oxide liner304, oxidizes the liner dielectric layer302and the core dielectric layer306when present. Different materials may be selected for the liner and core dielectric layers302,306so as to avoid forming the oxide liner304. The liner dielectric layer302in such configurations may be a different material than the core dielectric layer306. For example, the core dielectric layer306has high etch selectivity against the liner dielectric layer302. In some embodiments, the liner dielectric layer302is SiN or SiCN, and the core dielectric layer306is SiOC or SiOCN. In some embodiments, the core dielectric layer306is SiN or SiCN, and the liner dielectric layer302is SiOC or SiOCN. Other details of the device10shown inFIG.1Iare similar to those of the device10described with reference toFIG.1C, and are not repeated for brevity.

InFIG.1I, the gate isolation structure99lands on the upper surface of the wall structure300A, for example, on the upper surface of the core dielectric layer306. InFIG.1J, the gate isolations structure99extends into the wall structure300A. As such, sidewalls of the gate isolation structure99are in contact with inner sidewalls of the core dielectric layer306, which has different material than the liner dielectric layer302.

InFIG.1KandFIG.1L, the spacer portions302S contact the core dielectric layer306. In some embodiments, the spacer portions302S extend laterally from the sidewall of the channel22B3to the sidewall of the core dielectric layer306, as shown. Other details of the spacer portions302S are described with reference toFIGS.1E and1F.

FIG.1Mis similar in many respects toFIG.1G, except that the device10shown inFIG.1Mincludes the wall structure300A instead of the wall structure300shown inFIG.1G. Relevant details of the device10shown inFIG.1Mare described with reference toFIG.1G, and not repeated here.

FIG.1Nis a perspective view of a device10in accordance with various embodiments. The device10ofFIG.1Nmay have structure beneficial for use in SRAM applications. The device10ofFIG.1Nis similar in many respects to the devices10ofFIGS.1A-1M, except that the fin323and overlying stack of nanostructures22A3,22B3,22C3are replaced (e.g., partially replaced) by an active area isolation structure530and the gate structure200B, as shown in the perspective view. The active area isolation structure530may include a dielectric material, such as a low-k dielectric material, which may be SiN or an oxide, such as silicon oxide. The dielectric material of the isolation structure530may be different than the dielectric materials of one or more of the liner dielectric layer302and the core dielectric layer306of the wall structures300. The active area isolation structure530may be used as an active area cutting structure that isolates transistors (e.g., fins32and nanostructures22) on either side of the active area isolation structure530.

FIG.1Ois a cross-sectional side view of the device10ofFIG.1N. In some embodiments, the active area isolation structure530has an upper surface that is coplanar or substantially coplanar with upper surfaces of the isolation region362and the liner dielectric layer302of the wall structure300adjacent the active area isolation structure530. A lower surface of the active area isolation structure530may be coplanar or substantially coplanar with, or may be slightly above or slightly below, lower surfaces of the isolation region362and the liner dielectric layer302adjacent thereto. In some embodiments, the lower surface of the active area isolation structure530may be substantially horizontal as shown, or may have convex shape in the Y-Z plane. Lateral sidewalls of the active area isolation structure530may be in contact with the isolation region362and the liner dielectric layer302. The upper surface of the active area isolation structure530may be in contact with the gate structure200B, such as the gate dielectric layer600of the gate structure200B. The lower surface of the active area isolation structure530may be in contact with the substrate110when the substrate110is present.

FIG.1Pshows the gate isolation structure99, which may extend into the wall structure300in the device10ofFIG.1N.FIGS.1Q and1Rillustrate embodiments of the spacer portion302S in the device10ofFIG.1N.FIGS.1P-1Rare similar toFIGS.1D-1F, and description thereof is provided with reference toFIGS.1D-1F, and not repeated here for brevity. It should be understood that the device10ofFIG.1Nincluding the active area isolation structure530may include the wall structure300or the wall structure300A.

FIGS.1Sis a detailed cross-sectional side view of the wall structure300adjacent the channel22B3and the gate structure200B in accordance with various embodiments. In some embodiments, as shown inFIG.1S, the liner dielectric layer302is not trimmed prior to forming the gate structure200B, which reduces number of operations used to manufacture the device10. As such, the conductive fill layer290may extend short of the sidewall of the channel22B3adjacent the wall structure300, and the gate dielectric layer600may have a sidewall substantially coplanar with sidewalls of the channel22B3and the liner dielectric layer302.

FIGS.2A-2QandFIGS.3A-3Iillustrate methods of forming the IC device10in accordance with various embodiments.FIGS.2A-2Qshow intermediate views of the IC device10illustrated inFIG.1Aat various operations of the method.FIGS.3A-3Ishow intermediate views of the IC device10illustrated inFIG.1Nat various operations of the method. In some embodiments, the IC device10includes logic devices and SRAM devices.FIGS.2A-2Qillustrate formation of the logic devices in accordance with various embodiments.FIGS.3A-3Iillustrate formation of the SRAM devices in accordance with various embodiments. Many operations illustrated by the views inFIGS.2A-2Qare performed simultaneously and illustrated by the views inFIGS.3A-3I. For example,FIGS.2A-2Hmay correspond toFIGS.3A-3H, respectively, withFIGS.2A-2Hillustrating operations performed in regions including the logic devices, andFIGS.3A-3Hillustrating the operations as performed in regions including the SRAM devices.

FIG.5illustrates a flowchart of a method1000for forming an IC device or a portion thereof from a workpiece, according to one or more aspects of the present disclosure. Method1000is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in method1000. Additional acts can be provided before, during and after the method1000, and some acts described can be replaced, eliminated, or moved around for additional embodiments of the methods. Not all acts are described herein in detail for reasons of simplicity. Method1000is described below in conjunction with fragmentary perspective and/or cross-sectional views of a workpiece, shown inFIGS.2A-3I, at different stages of fabrication according to embodiments of method1000. For avoidance of doubt, throughout the figures, the X direction is perpendicular to the Y direction and the Z direction is perpendicular to both the X direction and the Y direction. It is noted that, because the workpiece may be fabricated into a semiconductor device, the workpiece may be referred to as the semiconductor device as the context requires.

InFIG.2AandFIG.3A, a substrate110is provided. The substrate110may be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The semiconductor material of the substrate110may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multi-layered, or gradient substrates may be used.

Further inFIG.2AandFIG.3A, a multi-layer stack25or “lattice” is formed over the substrate110of alternating layers of first semiconductor layers21A-21C (collectively referred to as first semiconductor layers21) and second semiconductor layers23. In some embodiments, the first semiconductor layers21may be formed of a first semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbide, or the like, and the second semiconductor layers23may be formed of a second semiconductor material suitable for p-type nano-FETs, such as silicon germanium or the like. Each of the layers of the multi-layer stack25may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. As shown inFIG.2AandFIG.3A, an oxide layer28and hard mask layer29are formed over the top first semiconductor layer21A. In some embodiments, the oxide layer28is a pad oxide layer, and the hard mask layer29may include silicon. In some embodiments, a second semiconductor layer27may be present between the top first semiconductor layer21and the oxide layer28, as shown inFIG.2BandFIG.3B.

Three layers of each of the first semiconductor layers21and the second semiconductor layers23are illustrated. In some embodiments, the multi-layer stack25may include one or two each or four or more each of the first semiconductor layers21and the second semiconductor layers23. Although the multi-layer stack25is illustrated as including a second semiconductor layer23as the bottommost layer of the multi-layer stack25, in some embodiments, the bottommost layer of the multi-layer stack25may be a first semiconductor layer21.

Due to high etch selectivity between the first semiconductor materials and the second semiconductor materials, the second semiconductor layers23of the second semiconductor material may be removed without significantly removing the first semiconductor layers21of the first semiconductor material, thereby allowing the first semiconductor layers21to be released to form channel regions of nano-FETs. In some embodiments, the first semiconductor layers21are removed and the second semiconductor layers23are patterned to form channel regions. The high etch selectivity allows the first semiconductor layers21of the first semiconductor material to be removed without significantly removing the second semiconductor layers23of the second semiconductor material, thereby allowing the second semiconductor layers23to be patterned to form channel regions of nano-FETs.

InFIG.2B, fins321-325and stacks of nanostructures22are formed in the multi-layer stack25, corresponding to operation1100ofFIG.5. First nanostructures22A1-22C5(also referred to collectively as “channels22”) are formed from the first semiconductor layers21, and second nanostructures24are formed from the second semiconductor layers23. The fin321is not illustrated inFIG.2BandFIG.3B, but can be seen inFIG.1CandFIG.1O, for example. In the following, description is given with reference to the fins322-325, and it should be understood that the description is equally applicable to the fin321. In some embodiments, the nanostructures22,24and the fins322-325may be formed by etching trenches35in the multi-layer stack25and the substrate110. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Distance between adjacent fins322-325and nanostructures22,24in the Y-axis direction may be from about 18 nm to about 100 nm. The nanostructures22A3,22B3,22C3are a first stack, the nanostructures22A4,22B4,22C4are a second stack, and the nanostructures22A5,22B5,22C5are a third stack.

The fins322-325and the nanostructures22,24may be patterned by any suitable method. For example, one or more photolithography processes, including double-patterning or multi-patterning processes, may be used to form the fins322-325and the nanostructures22,24. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing for pitches smaller than what is otherwise obtainable using a single, direct photolithography process. As an example of one multi-patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins322-325. In some embodiments, the hard mask layer29is patterned, for example by a photolithography process, then the pattern is transferred by an etch process to form the fins322-325and the nanostructures22,24. Each of the fins322-325and its overlying nanostructures22,24may be collectively referred to as a “fin stack.” A fin stack26including the fin322and the nanostructures22A2,22B2,22C2,24is outlined by a dashed line inFIG.2BandFIG.3B. Four fin stacks26are shown inFIG.2BandFIG.3B, though few or more than four fin stacks may also be formed by the patterning process. In some embodiments, fin stacks26overlying a first neighboring pair of the fins322-325(e.g., the fins322,323) may be separated by a first distance in the Y-axis direction of about 40 nm to about 60 nm, and fin stacks26overlying a second neighboring pair of the fins322-325(e.g., the fins323,324) may be separated by a second distance in the Y-axis direction of about 20 nm to about 60 nm.

FIG.2BandFIG.3Billustrate the fins322-325having vertically straight sidewalls. In some embodiments, the sidewalls are substantially vertical (non-tapered), such that width of the fins322-325and the nanostructures22,24is substantially similar, and the nanostructures22,24are rectangular in shape (e.g., has rectangular profile in the Y-Z plane). In some embodiments, the fins322-325have tapered sidewalls, such that a width of each of the fins322-325and/or the nanostructures22,24continuously increases in a direction towards the substrate110. In such embodiments, the nanostructures22,24may have a different width from each other and be trapezoidal in shape (e.g., have trapezoidal profile in the Y-Z plane).

InFIG.2CandFIG.3C, wall structures300are formed in one or more of the trenches35, corresponding to operation1200ofFIG.5. As shown, one wall structure300may be formed adjacent the fin322(e.g., between the fin322and the fin321shown inFIG.1CandFIG.1O), and another wall structure300may be formed between the fins323,324and between the first stack and the second stack. Formation of the wall structures300may include one or more deposition operations. In some embodiments, the liner dielectric layer302is formed in a first deposition operation, such as a CVD, ALD or other suitable deposition operation. The liner dielectric layer302may be formed of a first dielectric material, such as a low-k dielectric material, which may be or include SiN, SiCN, SiOC, SiOCN, or the like, as described with reference toFIGS.1A-1H.

Following formation of the liner dielectric layer302, the etch stop layer304may be formed on the liner dielectric layer302. Formation of the etch stop layer304may include an operation that oxidizes material of the liner dielectric layer302. In some embodiments, the etch stop layer304is formed by depositing a layer of silicon oxide on the liner dielectric layer302, for example, by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof.

Following formation of the etch stop layer304, the core dielectric layer306is formed, for example, on the etch stop layer304. In some embodiments, the core dielectric layer306is formed of the first dielectric material in a second deposition operation, or of a second dielectric material that is substantially different than the first dielectric material. The second deposition operation may be a CVD, ALD or other suitable deposition operation. The core dielectric layer306may be or include SiN, SiCN, SiOC, SiOCN, or the like.

As described with reference toFIG.1I, the wall structure300A may be formed instead of or in addition to the wall structure300shown inFIG.2CorFIG.3C. When forming the wall structure300A, the etch stop layer304may not be formed, and the core dielectric layer306is a different material than the liner dielectric layer302, such that the liner dielectric layer302has high etch selectivity against the core dielectric layer306. For example, the liner dielectric layer302may be or include SiN or SiCN, and the core dielectric layer306may be or include SiOC or SiOCN. In some embodiments, the liner dielectric layer302may be or include SiOC or SiOCN, and the core dielectric layer306may be or include SiN or SiCN.

Following formation of the core dielectric layer306of the wall structure300or the wall structure300A, the liner dielectric layer302, the optional etch stop layer304and the core dielectric layer306may be etched to remove material thereof to a level below the upper surface of the hard mask layer29. For example, as shown inFIG.2CandFIG.3C, the upper surface of the wall structure300(or the wall structure300A) may be at a level above the uppermost channels22A2,22A3,22A4,22A5, above the second semiconductor layer27, or above the oxide layer28.

InFIG.2DandFIG.3D, laterally extending trenches37are formed (FIG.2D) through the fins322-325, overlying channels22and wall structures300(or wall structures300A) in the region including logic devices, while a mask400is in place over the region including SRAM devices (FIG.3D). The trenches37may extend to a level coplanar with, slightly above or slightly beneath that of the trenches35. The trenches37extend in a direction (e.g., the Y-axis direction) that is perpendicular to or substantially perpendicular to the direction (e.g., the X-axis direction) in which the trenches35extend. One or more removal operations may be used to form the trenches37. In some embodiments, the removal operations may be or include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Distance between adjacent fins322-325and nanostructures22,24in the X-axis direction may be from about 18 nm to about 100 nm. During formation of the trenches37, a mask400may be in place over regions of the IC device10in which the SRAM devices are being formed. Isolation trenches or openings520for forming SRAM devices may be formed in a subsequent operation illustrated inFIGS.2F and3F.

InFIGS.2E-2HandFIGS.3E-3H, isolation regions361,362, which may be shallow trench isolation (STI) regions, are formed adjacent and between the fins322-325, corresponding to operation1300ofFIG.5. The isolation regions361,362may be formed by depositing an insulation material layer36in the trenches35,37(FIG.2E) or in the trenches35(FIG.3E). In some embodiments, the insulation material layer36is formed over the substrate110, the fins322-325, and nanostructures22,24, and between adjacent fins322-325and nanostructures22,24. The insulation material layer36may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, a liner (not separately illustrated) may first be formed along surfaces of the substrate110, the fins322-325, and the nanostructures22,24. Thereafter, the insulation material layer36may be formed over the liner of a material such as those discussed above.

The insulation material layer36undergoes a removal process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like, to remove excess insulation material of the insulation material layer36over hard mask29, as shown inFIGS.2E and3E.

InFIGS.2F and3F, openings520are formed in the region including the SRAM devices (FIG.3F) while a mask500is in place over the region including the logic devices (FIG.2F). The openings520may be formed by one or more removal operations, such as suitable etch operations which may include RIE, NBE, atomic layer etch (ALE) or the like. As shown inFIG.3F, the openings520extend through or partially through the insulation material layer36, the hard mask29, the oxide layer28, the second semiconductor layer27, the channels22, the second semiconductor layers24, and one or more of the fins322-325(e.g., the fin323and the fin324, as shown). In some embodiments, the openings520land on the substrate110, extend slightly into the substrate110, or terminate slightly above the substrate110(e.g., leaving portions of the fins323,324remaining). A portion of the insulation material layer36may cover the upper surface of the wall structure300(or the wall structure300A) during formation of the openings520.

InFIGS.2G and3G, active area isolation structures530are formed in the region including the SRAM devices, then a second removal process is performed to remove the hard mask29and portions of the insulation material layer36, the active area isolation structures530and the wall structure300(or the wall structure300A) to expose the second semiconductor layer27. The active area isolation structures530may be formed by a suitable deposition process, such as a CVD, ALD, or the like, that deposits the dielectric material of the active area isolation structures530in the openings520. The second removal process may include a CMP, for example. Following the second removal process, upper surfaces of the wall structure300(or the wall structure300A), the active area isolation structures530(in the region including SRAM device) the insulation material layer36and the second semiconductor layer27are coplanar or substantially coplanar.

InFIGS.2H and3H, a third removal process is performed to remove the second semiconductor layer27, and a fourth removal process is performed to recess the isolation regions361,362. The perspective view ofFIG.2His shifted in the X-axis direction from that ofFIGS.2A-2G. In some embodiments, following the third removal process, top surfaces of the nanostructures22may be exposed and level with the insulation material layer36after the third removal process is complete. The insulation material layer36is then recessed to form the isolation regions361,362. After recessing the isolation regions361,362, the nanostructures22,24and upper portions of the fins322-325may protrude over the isolation regions361,362. The isolation regions361,362may have top surfaces that are flat as illustrated, convex, concave, or a combination thereof. In some embodiments, the isolation regions361,362are recessed by an acceptable etching process, such as an oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to the insulation material and leaves the fins322-325and the nanostructures22,24substantially unaltered.

InFIG.3H, in the region including SRAM devices, the active area isolation structures530are recessed, as shown. In some embodiments, the active area isolation structures530are recessed in the fourth removal process in which the isolation regions361,362are formed. In some embodiments, the active area isolation structures530are recessed before or after the isolation regions361,362are formed, for example, in a fifth removal process different than the fourth removal process. Following recessing of the insulation material layer36and the active area isolation structures530, upper surfaces of the isolation regions361,362and the active area isolation structures530may be coplanar or substantially coplanar (e.g., slightly offset from each other in the Z-axis direction).

InFIGS.2H and3H, appropriate wells (not separately illustrated) may be formed in the fins322-325, the nanostructures22,24, and/or the isolation regions361,362. Using masks, an n-type impurity implant may be performed in p-type regions of the substrate110, and a p-type impurity implant may be performed in n-type regions of the substrate110. Example n-type impurities may include phosphorus, arsenic, antimony, or the like. Example p-type impurities may include boron, boron fluoride, indium, or the like. An anneal may be performed after the implants to repair implant damage and to activate the p-type and/or n-type impurities. In some embodiments, in situ doping during epitaxial growth of the fins322-325and the nanostructures22,24may obviate separate implantations, although in situ and implantation doping may be used together.

FIGS.2I-2Pare perspective views illustrating formation of gate structures200and source/drain regions82in accordance with various embodiments. The description ofFIGS.2I-2Pis applicable to both the region including logic devices and the region including SRAM devices.

InFIG.2I, following formation of the isolation regions361,362, sacrificial gate structures40are formed over the fins322-325, the wall structures300(or the wall structures300A), the isolation regions361,362and the nanostructures22,24. Three sacrificial gate structures40are shown inFIG.2I, and many further sacrificial gate structures40may be formed substantially parallel to and concurrently with the sacrificial gate structures40shown.

When forming the sacrificial gate structures40, a sacrificial gate layer45is formed over the fins321-325and/or the nanostructures22,24. The sacrificial gate layer45may be made of materials that have a high etch selectivity to the isolation regions361,362. The sacrificial gate layer45may be a conductive, semiconductive, or non-conductive material and may be or include amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The sacrificial gate layer45may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. First and second mask layers47A,47B are formed over the sacrificial gate layer45, and may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, a gate dielectric layer44is formed before the sacrificial gate layer45between the sacrificial gate layer45and the fins322-325and/or the nanostructures22,24.

InFIG.2J, following formation of the sacrificial gate structures40, one or more gate spacer layers41are formed covering the sacrificial gate structures40and exposed regions of the stacks26, the fins322-325, the isolation regions361,362and the wall structures300(or the wall structures300A). The gate spacer layer41is formed by any suitable deposition process, such as a PVD, CVD, ALD, or the like. Following formation of the gate spacer layer41, horizontal portions (e.g., in the X-Y plane) of the gate spacer layer41may be removed, thereby exposing upper surfaces of the stacks26, the wall structures300(or the wall structures300A) and the isolation regions361,362. In some embodiments, capping portions41C of the gate spacer layer41remain over edge portions361E,362E of the isolation regions361,362, respectively, after removal of the horizontal portions of the gate spacer layer41.

Following removal of the horizontal portions of the gate spacer layer41, one or more removal operations are performed to recess the stacks26, the wall structures300(or the wall structures300A), the isolation regions361,362and the fins322-325exposed through the gate spacer layer41. The removal operations may include suitable etch operations for removing materials of the channels22, the second semiconductor layers24, the fins322-325, the wall structures300(or the wall structures300A) and the isolation regions361,362, such as RIE, NBE, ALE, or the like.

InFIG.2K, inner spacers74are formed. A selective etching process is performed to recess exposed end portions of the nanostructures24without substantially attacking the nanostructures22. After the selective etching process, recesses are formed in the nanostructures24at locations where the removed end portions used to be. Next, an inner spacer layer is formed to fill the recesses between the nanostructures22formed by the previous selective etching process. The inner spacer layer may be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, formed by a suitable deposition method such as PVD, CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer layers disposed outside the recesses in the nanostructures24. The remaining portions of the inner spacer layers (e.g., portions disposed inside the recesses in the nanostructures24) form the inner spacers74. The resulting structure is shown inFIG.2K.

FIG.2Lillustrates formation of the source/drain regions82, corresponding to operation1400ofFIG.5. In the illustrated embodiment, the source/drain regions82are epitaxially grown from epitaxial material(s). The source/drain regions82are grown on exposed portions of the fins322-325and contact the nanostructures22. Initially, the source/drain regions82grow between neighboring isolation structures or between an isolation structure and a wall structure, for example, between the wall structure300and the isolation structure361on the fin322, as shown. The capping portion41C on the isolation structure361laterally confines the source/drain region82as it grows upward from the fin322. In some embodiments, the source/drain regions82exert stress in the respective channels22, thereby improving performance. The source/drain regions82are formed such that each sacrificial gate structure40is disposed between respective neighboring pairs of the source/drain regions82. In some embodiments, the spacer layer41and the inner spacers74separate the source/drain regions82from the sacrificial gate layer45by an appropriate lateral distance (e.g., in the X-axis direction) to prevent electrical bridging to subsequently formed gates of the resulting device.

The source/drain regions82may include any acceptable material, such as appropriate for n-type or p-type devices. For n-type devices, the source/drain regions82include materials exerting a tensile strain in the channel regions, such as silicon, SiC, SiCP, SiP, or the like, in some embodiments. When p-type devices are formed, the source/drain regions82include materials exerting a compressive strain in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like, in accordance with certain embodiments. The source/drain regions82may have surfaces raised from respective surfaces of the fins and may have facets. Neighboring source/drain regions82may merge in some embodiments to form a singular source/drain region82over two neighboring fins of the fins322-325.

The source/drain regions82may be implanted with dopants followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm—3. N-type and/or p-type impurities for source/drain regions82may be any of the impurities previously discussed. In some embodiments, the source/drain regions82are in situ doped during growth. A contact etch stop layer (CESL) and interlayer dielectric (ILD), not illustrated for simplicity, may then be formed covering the sacrificial gate structures40and the source/drain regions82.

InFIG.2M, one or more of the source/drain regions82are cut or trimmed, such that the source/drain regions82have cross-sectional profile in the Y-Z plane that is forksheet shaped, corresponding to operation1500ofFIG.5. Portions of the source/drain regions82overlapping the wall structure300or300A are trimmed in operation1500. Prior to an etch operation used to trim the source/drain regions82, a patterned mask550may be formed overlying the source/drain regions82, the sacrificial gate structures40, the gate spacer layer41and the isolation regions361,362. The patterned mask550includes openings39that expose second lateral extensions82EX2(seeFIG.1G) of the source/drain regions82that overlie the wall structures300or300A. In some embodiments, the openings39are trenches that extend in the X-axis direction. The etch operation is performed through the openings39, and may include a suitable anisotropic etch that does not substantially attack portions of the source/drain regions82covered by the patterned mask550. Following removal of the lateral edge portions of the source/drain regions82, lateral extension of the source/drain region82past edges of the channels22may be in a range of about 0 nm to about 10 nm on the side that is trimmed, and may be in a range of about 10 nm to about 20 nm on the side that is covered by the patterned mask550.

InFIG.2N, channels22are released by removal of the nanostructures24, the mask layer47, and the sacrificial gate layer45. Prior to release, a planarization process, such as a CMP, may be performed to level the top surfaces of the sacrificial gate layer45and gate spacer layer41. The planarization process may also remove the mask layers47A,47B on the sacrificial gate layer45, and portions of the gate spacer layer41along sidewalls of the mask layer47. Accordingly, the top surfaces of the sacrificial gate layer45are exposed.

Next, the sacrificial gate layer45is removed in an etching process, so that recesses are formed. In some embodiments, the sacrificial gate layer45is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the sacrificial gate layer45without etching the spacer layer41. The sacrificial gate dielectric44, when present, may be used as an etch stop layer when the sacrificial gate layer45is etched. The sacrificial gate dielectric44may then be removed after the removal of the sacrificial gate layer45.

The nanostructures24are removed to release the nanostructures22. After the nanostructures24are removed, the nanostructures22form a plurality of nanosheets that extend horizontally (e.g., parallel to a major upper surface of the substrate110). The nanosheets may be collectively referred to as the channels22of the nanostructure devices20A-20E formed.

In some embodiments, the nanostructures24are removed by a selective etching process using an etchant that is selective to the material of the nanostructures24, such that the nanostructures24are removed without substantially attacking the nanostructures22. In some embodiments, the etching process is an isotropic etching process using an etching gas, and optionally, a carrier gas, where the etching gas comprises F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, combinations thereof, or the like.

In some embodiments, the nanostructures24are removed and the nanostructures22are patterned to form channel regions of both PFETs and NFETs. In some other embodiments, the nanostructures22may be removed and the nanostructures24may be patterned to form channel regions of both PFETs and NFETs.

In some embodiments, the nanosheets22of the nanostructure devices20A-20E are reshaped (e.g. thinned) by a further etching process to improve gate fill window. The reshaping may be performed by an isotropic etching process selective to the nanosheets22. After reshaping, the nanosheets22may exhibit the dog bone shape in which middle portions of the nanosheets22are thinner than peripheral portions of the nanosheets22along the X-axis direction.

In some embodiments, prior to removal of the nanostructures24, the mask layer47, and the sacrificial gate layer45, the ILD130is deposited over the source/drain regions82. The etch stop layer131may also be formed prior to deposition of the ILD130. Following deposition of the ILD130, the ILD130may be recessed slightly, and a second etch stop layer may be formed over the ILD130in the recess (not specifically illustrated in the figures). A CMP operation or the like may then be performed to remove excess material of the second etch stop layer, such that an upper surface of the second etch stop layer is substantially planar with upper surfaces of the etch stop layer131and the gate spacers41.

InFIG.2O, uncut replacement gate200U is formed, corresponding to operation1600ofFIG.5. The uncut replacement gate200U may be formed by one or more deposition operations, such as a CVD, ALD, or the like.FIG.4is a detailed view of the region170ofFIG.2Ocorresponding to a portion of the gate structure200B (seeFIG.2Q). Each replacement gate200, as illustrated by the gate structure200B inFIG.4, generally includes the interfacial layer (IL, or “first IL” below)210, at least one gate dielectric layer600, the work function metal layer900, and the conductive fill layer290. In some embodiments, each replacement gate200further includes at least one of a second interfacial layer240or a second work function layer700.

With reference toFIG.4, in some embodiments, the first IL210includes an oxide of the semiconductor material of the substrate110, e.g. silicon oxide. In other embodiments, the first IL210may include another suitable type of dielectric material. The first IL210has a thickness in a range between about 5 angstroms and about 50 angstroms. As shown inFIG.4, due to presence of the spacer portions302S adjacent the channels22, the first IL210may terminate on bottom and top surfaces of the spacer portions302S.

Still referring toFIG.4, the gate dielectric layer600is formed over the first IL210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer600to control thickness of the deposited gate dielectric layer600with precision. In some embodiments, the ALD process is performed using between about 40 and 80 deposition cycles, at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and/or H2O as precursors. Such an ALD process may form the first gate dielectric layer220to have a thickness in a range between about 10 angstroms and about 100 angstroms. As shown inFIG.4, the gate dielectric layer600may be a continuous layer that conforms to (e.g., is in contact with) sidewalls of the etch stop layer304of the wall structure300(or the core dielectric layer306of the wall structure300A), the bottom and top surfaces of the spacer portions302S and the first IL210or the channels22when the first IL210is not present.

In some embodiments, the gate dielectric layer600includes a high-k dielectric material, which may refer to dielectric materials having a high dielectric constant that is greater than a dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer600may include a non-high-k dielectric material such as silicon oxide. In some embodiments, the gate dielectric layer600includes more than one high-k dielectric layer, of which at least one includes dopants, such as lanthanum, magnesium, yttrium, or the like, which may be driven in by an annealing process to modify threshold voltage of the nanostructure devices20A-20E.

With further reference toFIG.4, the second IL240is formed on the gate dielectric layer600, and the second work function layer700is formed on the second IL240. The second IL240promotes better metal gate adhesion on the gate dielectric layer600. In many embodiments, the second IL240further provides improved thermal stability for the gate structure200B, and serves to limit diffusion of metallic impurity from the work function metal layer900and/or the work function barrier layer700into the gate dielectric layer600. In some embodiments, formation of the second IL240is accomplished by first depositing a high-k capping layer (not illustrated for simplicity) on the gate dielectric layer600. The high-k capping layer comprises one or more of the following: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials, in various embodiments. In a specific embodiment, the high-k capping layer comprises titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by an ALD using about 40 to about 100 cycles at a temperature of about 400 degrees C. to about 450 degrees C. A thermal anneal is then performed to form the second IL240, which may be or comprise TiSiNO, in some embodiments. Following formation of the second IL240by thermal anneal, an atomic layer etch (ALE) with artificial intelligence (AI) control may be performed in cycles to remove the high-k capping layer while substantially not removing the second IL240. Each cycle may include a first pulse of WCl5, followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k capping layer is removed to increase gate fill window for further multiple threshold voltage tuning by metal gate patterning.

Further inFIG.4, after forming the second IL240and removing the high-k capping layer, the work function barrier layer700is optionally formed, in accordance with some embodiments. The work function barrier layer700is or comprises a metal nitride, such as TiN, WN, MoN, TaN, or the like. In a specific embodiment, the work function barrier layer700is TiN. The work function barrier layer700may have thickness ranging from about 5 A to about 20 A. Inclusion of the work function barrier layer700provides additional threshold voltage tuning flexibility. In general, the work function barrier layer700increases the threshold voltage for NFET transistor devices, and decreases the threshold voltage (magnitude) for PFET transistor devices.

The work function metal layer900, which may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen blocking layer, is formed on the work function barrier layer700, in some embodiments. The N-type work function metal layer is or comprises an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and/or other suitable methods, and has a thickness between about 10 A and 20 A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or comprises TiN, TiSiN, TaN, or another suitable material, and has a thickness between about 10 A and 20 A. The oxygen blocking layer is formed on the in-situ capping layer to prevent oxygen diffusion into the N-type work function metal layer, which would cause an undesirable shift in the threshold voltage. The oxygen blocking layer is formed of a dielectric material that can stop oxygen from penetrating to the N-type work function metal layer, and may protect the N-type work function metal layer from further oxidation. The oxygen blocking layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen blocking layer is formed using ALD and has a thickness between about 10 A and about 20 A.

FIG.4further illustrates the conductive fill layer290. In some embodiments, a glue layer (not separately illustrated) is formed between the oxygen blocking layer of the work function metal layer and the conductive fill layer290. The glue layer may promote and/or enhance the adhesion between the conductive fill layer290and the work function metal layer900. In some embodiments, the glue layer may be formed of a metal nitride, such as TiN, TaN, MoN, WN, or another suitable material, using ALD. In some embodiments, thickness of the glue layer is between about 10 A and about 25 A. The conductive fill layer290may be formed on the glue layer, and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the conductive fill layer290may be deposited using methods such as CVD, PVD, plating, and/or other suitable processes. In some embodiments, a seam510, which may be an air gap, is formed in the conductive fill layer290vertically between the channels22A2,22B2. In some embodiments, the conductive fill layer290is conformally deposited on the work function metal layer900. The seam510may form due to sidewall deposited film merging during the conformal deposition. In some embodiments, the seam510is not present between the neighboring channels22A2,22B2.

FIG.2Pillustrates formation of the second conductive layer297. Prior to deposition of the second conductive layer297, the uncut gate structure200U may be recessed by, for example, a suitable etch operation. The etch operation may include an isotropic etch or an anisotropic etch that removes the conductive fill layer290without substantially attacking the gate spacer layer41, the etch stop layer131and the ILD130. Following the etch operation that recesses the uncut gate structure200U, the second conductive layer297may be deposited by an appropriate deposition operation, which may include a PVD, sputtering, a CVD, an ALD, or the like. In some embodiments, the second conductive layer297is formed by depositing a conductive material, such as tungsten. Following deposition of the second conductive layer297, excess conductive material overlying the etch stop layer131, the ILD130and the gate spacer layer41may be removed by, for example, a CHIP.

FIGS.2Q and3Iillustrate formation of gate isolation structures99. InFIG.2QandFIG.3I, one or more mask layers may be formed over the uncut gate structure200U. The mask layers may include silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the mask layers may be in a range from about 100 nm to about 200 nm, in some embodiments. In some embodiments, an uppermost mask layer of the mask layers is subjected to a planarization operation. The mask layers may include a hard mask layer, which may be deposited using any suitable processes, including spin coating, LPCVD, PECVD, PVD, ALD, or other suitable processes. The hard mask layer includes one or more layers of SiN, SOC, or the like, in accordance with some embodiments.

The hard mask layer may be etched to form openings over one or more of the wall structures300or300A, one or more of the isolation regions361,362, or both. As illustrated inFIG.2QandFIG.3I, one of the openings is formed over and exposing the wall structure300between the fins321,322, and another of the openings is formed over the isolation structure362. When formed over one of the wall structures300or300A, the opening may have width (in the Y-axis direction) less than width of the wall structure300, though larger widths may also be suitable.

To form the openings, in some embodiments, a photoresist pattern (not separately illustrated) is formed over the hard mask layer, and the hard mask layer is etched first by an anisotropic etching process selective to the material of the hard mask layer, which forms an upper portion of the openings extending from the upper surface of the hard mask layer to expose the upper surface of the second conductive layer297. Following etching of the hard mask layer, the photoresist pattern may be removed, and the hard mask layer may be used as a mask while forming a lower portion of the openings extending through the second conductive layer297, the uncut gate structure200U and optionally into the wall structure300or300A.

InFIGS.2Q and3I, following formation of the openings, the gate isolation structures99are formed in the openings. In some embodiments, the gate isolation structures99are or include silicon nitride, silicon oxide, Al2O3, ZrO2 or another suitable material. The gate isolation structures99may be deposited in the openings by a suitable process, such as CVD and/or other suitable technique. Following deposition of the gate isolation structures99, a removal process, such as CHIP or another suitable process, can be performed to remove excess material of the gate isolation structures99from over the second conductive layer297, such that upper surfaces of the gate isolation structures99are substantially level with upper surfaces of the second conductive layer297. The gate isolation structures99generally inherit the shape of the openings. At this point, the gate structures200A-200C are electrically isolated from each other.

Embodiments may provide advantages. By forming the wall structures300or300A at cell boundaries, gate-drain capacitance is reduced by reducing metal gate endcap and source/drain epitaxy size. Active area spacing is also reduced. The wall structure may be a multi-layer structure, which allows for extending gate structure200overlap with channels22by removing portions of the liner dielectric layer302of the wall structure300or300A, thereby increasing control of current through the channels22by the gate structure200. Source/drain regions82adjacent the wall structure are cut or trimmed to prevent merger of neighboring source/drain regions82. By reducing the metal gate endcap and source/drain region82lateral dimensions, gate-drain capacitance may be reduced. As such, device performance is boosted, and active area spacing between nanostructure devices20A-20E may be reduced, which saves chip area.

In accordance with at least one embodiment, a device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

In accordance with at least one embodiment, a device includes a plurality of nanostructures, a gate structure and a source/drain region. The plurality of nanostructures is over a substrate. Each of the nanostructures includes: an upper side; a lower side opposite the upper side; a first lateral side facing a first lateral direction; a second lateral side opposite the first lateral side; a third lateral side facing a second lateral direction transverse the first lateral direction; and a fourth lateral side opposite the third lateral side. The gate structure extends in the first lateral direction, and contacts the upper, lower and first lateral sides of each of the nanostructures. The gate structure is isolated from the third and fourth lateral sides of each of the nanostructures. The source/drain region is beside the plurality of nanostructures, and has an asymmetric shape in the first lateral direction.

In accordance with at least one embodiment, a method includes: forming a first stack of nanostructures, a second stack of nanostructures, and a third stack of nanostructures, the first, second and third stacks being laterally separated from each other; forming a wall structure between the first and second stacks; forming an isolation region between the second and third stacks; forming a first source/drain region contacting the first stack, forming a second source/drain region contacting the second stack, and forming a third source/drain region contacting the third stack; trimming portions of the first and second source/drain regions, the portions facing each other and vertically overlapping the wall structure; and forming a gate structure over the first, second and third stacks.