Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a bipolar transistor.

2. Description of the Related Art

A typical bipolar transistor has an emitter, a base, and a collector. Typically, the emitter and collector are semiconductor materials of one type (N- or P-type), and the base is a semiconductor material of an opposite type (P- or N-type), such that NPN or PNP junctions are formed between the emitter, base, and collector.

When the transistor is activated, a small forward bias voltage is applied between the emitter and the base. The bias voltage lowers the energy barrier that exists at the junction between the emitter and the base, causing the transistor to turn on. When such a junction is made between materials of the same basic composition, the junction is called a homojunction. When such a junction is made between two dissimilar materials, the junction is called a heterojunction.

Lately, practitioners have focused on heterojunction bipolar transistors (HBT) in an attempt to achieve higher switching speeds. For instance, one type of HBT includes an emitter structure formed of N-doped polysilicon and a base layer formed of a P-doped silicon germanium alloy (SiGe).

SUMMARY OF THE INVENTION

The invention relates to a bipolar transistor in a semiconductor chip, and methods of fabricating the transistor. The transistor may be used, for instance, in a bipolar or BiCMOS process. The transistor may be a heterojunction bipolar transistor with either a drift or a box profile.

An exemplary embodiment of a bipolar transistor within the present invention includes an emitter structure, a base layer, and a collector layer. A dielectric isolation layer including a central aperture overlies the base layer and a bird's beak region of an adjacent field oxide layer. An emitter structure makes contact with the base layer through the central aperture of the dielectric isolation area, forming the emitter-base junction. A collector pedestal implant region may be formed directly beneath the central aperture of the dielectric isolation layer. A base contact may be coupled to base layer through a link implant region.

In one embodiment, the transistor is a heterojunction bipolar transistor. The base layer of such a transistor may be formed of selectively grown SiGe.

An exemplary method of forming a bipolar transistor within the present invention includes providing a substrate including a region of a first type; forming a buried layer of a second type in the region of the substrate; forming an epitaxy layer of the second type on the buried layer; masking the surface of the epitaxy layer for defining an active area; forming a field oxide layer on the surface of the epitaxy layer surrounding the active area; patterning the substrate to define a base region in the active area; growing in the base region a base layer (e.g., selectively grown SiGe) bound by the field oxide layer; forming a dielectric isolation layer having a central aperture over the base layer and an adjacent bird's beak area of the field oxide layer; forming an emitter structure over the dielectric isolation layer in a manner such that the material of the emitter structure contacts the SiGe layer through the central aperture in the dielectric isolation layer, so that an emitter-base junction may be formed; and forming a collector contact and a base contact.

The present invention will be better understood upon consideration of the detailed description below and the accompanying drawings.

In the present disclosure, like objects that appear in more than one figure are provided with like reference numerals.

DETAILED DESCRIPTION

FIGS. 1-7illustrate steps of a process within the present invention for forming a bipolar transistor within the present invention. In this particular instance, the bipolar transistor is a heterojunction bipolar transistor (HBT), and includes a dielectric isolation layer between the emitter structure and the base layer. Among other things, the dielectric isolation layer places a high dopant concentration of an emitter structure away from an extrinsic base region, thereby reducing emitter-base capacitance. The dielectric isolation layer serves to protect a bird's beak region of a field oxide layer that is adjacent to the base layer during the fabrication process. The dielectric isolation layer also may be used as a mask for performing a collector pedestal implant that can minimize the well known Kirk effect, also called base push-out effect. The collector pedestal implant is thereby self-aligned with the emitter to ensure maximum effectiveness. A high performance heterojunction bipolar transistor with improved performance and manufacturability is thereby attained.

FIG. 1includes a top view and a corresponding cross-sectional view of a semiconductor substrate1in which the transistor is to be formed. The cross-sectional view ofFIG. 1is taken along a line A-A′ of the top view.

In this example, the fabrication process uses a lightly doped p-type silicon substrate10as the starting material. An N+ buried layer12is formed on top of the silicon substrate10. Buried layer12can have any suitable thickness and dopant concentration. The buried layer12may be 2.0 μm thick, and may have a dopant concentration of ˜2E19 cm−3. An N-type epitaxial layer (N-Epi)14is then formed on silicon substrate10. N-Epi layer14can be formed using any conventional process, such as atmospheric chemical vapor deposition (CVD). N-Epi layer14may have a dopant concentration of ˜1E16 cm−3.

The present embodiment uses a sinker16and a trench isolation structure17to provide transistor isolation. Other conventional isolation techniques can also be used. A self-aligned sinker structure in a bipolar transistor fabrication process is described in U.S. Pat. No. 5,188,971, to Pollock et al., which is incorporated herein by reference in its entirety.

Referring to the top view ofFIG. 1, a mask pattern18defines the location of the trench isolation structure17and a mask pattern19defines the location of the sinker structure16. In one embodiment, the sinker is formed by lateral dopant diffusion through the trench sidewalls. In an alternate embodiment, the sinker is formed by implantation of dopants.

FIG. 2illustrates a subsequent step in the exemplary fabrication process. A field oxidation process is performed to grow a field oxide layer22for defining the active areas where the bipolar transistor is to be formed. The active areas are defined by an active area mask26as shown in the top view of FIG.2.

Field oxidation processes are well known in the art and any conventional field oxidation process can be used. For instance, a buffer oxide layer having a thickness of about 300 Å may be thermally grown on the top surface of the semiconductor substrate1using a conventional wet or dry process. Then, a nitride layer is deposited using, e.g., a plasma-enhanced CVD or a low pressure CVD process. The nitride layer is patterned using active area mask26ofFIG. 2(top view). Oxidation is carried out so that a field oxide layer is grown where the nitride layer is absent. After the oxidation process, the nitride layer is removed. Referring toFIG. 2, a field oxide layer22is thus formed on the surface of N-epi layer14. Field oxide layer22may be approximately 5,000 Å thick.

In an alternate embodiment, a fully recessed local isolation process using deposited oxide is used to form the field oxide layer for defining the active areas. In an exemplary process, the active areas are defined using a buffer oxide and a nitride layer process, as described above. Then, a silicon etch process is carried out to remove silicon from areas not covered by the nitride layer. Then, an oxide layer is deposited over the entire surface. A chemical mechanical polishing process is performed to planarize the oxide layer. The polishing process stops on the nitride layer. The nitride layer is subsequently removed, thereby forming the field oxide isolation regions.

After the active areas are defined, the base region of the transistor can be formed. The exemplary heterojunction transistor of the present embodiment uses a selective epitaxial SiGe layer as the base layer. The selective epitaxial SiGe layer is doped with a P-type dopant such as boron. Referring toFIG. 2, a base mask28is applied to define the base region. After patterning using base mask28, the 300 Å or so of buffer oxide on the semiconductor substrate10top surface inside the base region is removed to expose the bare silicon of N-epi layer14. The 300 Å or so of buffer oxide in other active areas is left on the semiconductor substrate1top surface. Then, a selective epitaxial process is performed to selectively grow the SiGe layer on the semiconductor substrate10. A process to grow the selective epitaxial SiGe layer may be performed a low pressure reactor using B2H6, SiH2Cl2, GeH4, HCl, and H2gases at about 10 Torrs of pressure. The selective epitaxial process grows the SiGe layer only on exposed bare silicon areas (such as the base region). Such an epitaxial process will not grow a SiGe layer on areas covered by an oxide layer. As a result of the selective epitaxial process, SiGe base layer24in single crystalline form is grown in the base region of the semiconductor structure10. The SiGe base layer24may have a thickness of 800 Å to 1000 Å.

The concentration of germanium in SiGe layer24may follow a triangular profile.FIG. 2Aillustrates an exemplary secondary ion mass spectrometer (SIMS) profile of a heterojunction bipolar transistor having a SiGe base layer grown by a selective epitaxial process. Boron and germanium concentrations in the SiGe layer are shown. The germanium concentration in the SiGe base layer has an approximately triangular profile.

In an alternate embodiment, carbon may be incorporated into the SiGe base layer during the epitaxial process. The carbon functions to suppress the out-diffusion of a p-type dopant (such as boron) that is incorporated in the SiGe layer. The carbon concentration may range from about 0.04% to 0.5%, e.g., 0.1% to 0.2%.

After the formation of SiGe base layer24, the buffer oxide layer29in the other active areas is removed. However, the removal of the buffer oxide layer29after the formation of the selectively grown SiGe base layer24in the base region could introduce device damage. To illustrate this phenomenon, a dotted box25inFIG. 2denotes an inner bird's beak area of field oxide layer22around the base region, where SiGe layer24overlies the bird's beak.FIG. 3is an enlarged cross-sectional view of box25of FIG.2. Referring toFIG. 3, SiGe base layer24encroaches on the inner bird's beak of field oxide layer22. The thickness of the field oxide layer22at the bird's beak can be as small as 150 Å.

When an etching process is performed to remove the 300 Å or so of buffer oxide remaining in the active areas other than the base region, field oxide layer22will also be etched. The dotted line30inFIG. 3illustrates a hypothetical location of an etched top surface of field oxide layer22which could result after an etch step used to remove the 300 Å or so of buffer oxide. Removal of the oxide at the bird's beak areas can expose the N-epi layer14between the SiGe base layer and the etched top surface of the bird's beak. When the emitter of the transistor is subsequently formed, the exposed silicon areas adjacent the bird's beak can result in emitter-to-collector shorts, destroying the functioning of the transistor.

In accordance with the present embodiment, subsequent to the formation of selectively grown SiGe base layer24, an isolation structure is formed in the transistor. As will be described in more detail below, the isolation structure protects the inner bird's beak of the field oxide layer adjacent the base region during processing so as to prevent the shorting problem mentioned above.

FIG. 4illustrates the formation of such an isolation structure. In this example, the isolation structure is formed from a dielectric layer deposited over the upper surface of semiconductor substrate1. The dielectric layer may be an oxide layer having a thickness of 750 Å that is deposited using a production plasma enhanced CVD reactor. The dielectric layer can then be masked with a photoresist mask36, and etched to form a dielectric isolation layer32, as shown in FIG.4.

Dielectric isolation layer32covers the adjoining peripheral portions of SiGe base layer24and field oxide layer22, including the bird's beak regions of field oxide layer22and the overlap region where the SiGe base layer24overlies the bird's beak. Mask36ofFIG. 4is a ring shape in this example, and thus allows for the formation of a ring-shaped dielectric isolation layer32through an etching process.

Referring toFIG. 4, dielectric isolation layer32overlies SiGe base layer24with the exception of a central region of SiGe base layer24exposed through a central aperture33of dielectric isolation layer32.

FIG. 5is an enlarged cross-sectional view of the peripheral areas of the SiGe layer24and the bird's beak region of the field oxide layer22of the exemplary embodiment of FIG.4. InFIG. 5, dielectric isolation layer32overlies the adjoining and overlapping peripheral portions of SiGe layer24and field oxide layer22. Because dielectric isolation layer32protectively covers the critical inner bird's beak area of field oxide layer22adjacent SiGe base layer24around the base region, inadvertent removal of the oxide in the underlying regions is prevented during the subsequent buffer oxide etching step, as discussed above. After the formation of the selectively grown SiGe base layer24and dielectric isolation layer32, the base region of the transistor is completed.

In accordance with the present embodiment, the dielectric isolation layer32also may be used as a mask to perform a self-aligned collector pedestal implant. That is, after the ring-shaped dielectric isolation layer32is formed, but prior to the removal of the residual photoresist of mask36, an implantation step is performed to introduce a phosphorus n-type dopant into the N-epi layer14through central aperture33of dielectric isolation layer32and the corresponding aperture of mask36. As a result, a collector pedestal implant region34is formed in the N-epi layer14. Collector pedestal implant region34may have a dopant concentration of 5E16 to 1E17 cm−3.

Collector pedestal implant region34functions to minimize or eliminate performance degradation in the transistor caused by the Kirk effect. The Kirk effect is a well-known phenomenon where the base width is extended due to high-level injection of minority carriers into the collector. This causes an increase in base transit time and a corresponding decrease in device speed of operation. The collector pedestal implant, by introducing a heavily doped N-type region at the base-collector junction, prevents the space-charge region edge in the base from moving into the collector, thereby preventing base push-out.

FIG. 6illustrates a subsequent step in the exemplary fabrication process, wherein an emitter structure, and a collector pick up of the transistor are formed.

Referring to the example ofFIG. 6, a polysilicon layer40is deposited over the top surface semiconductor substrate10of FIG.4and is doped with arsenic to approximately ˜1E20/cm−3. Alternatively, polysilicon layer40may be doped with phosphorus. Next, a refractory metal layer42, which may be titanium, is formed on the top surface of the polysilicon layer40. Then, a layer of an isolation dielectric44, such as oxide, is deposited over the refractory metal layer42. After the polysilicon layer40, refractory metal layer42, and dielectric layer44are formed, a mask47is applied and the layers are etched, with the etch process stopping on dielectric isolation layer32. A titanium sintering process is then performed to convert the titanium refractory metal layer42on top of the polysilicon layer40into titanium suicide. Accordingly, emitter structure46and collector pick-up47are formed.

The doped polysilicon layer40of emitter structure46contacts SiGe base layer24though the central aperture33of dielectric isolation layer32. Upon subsequent thermal processing steps, the dopant of polysilicon layer40diffuses about 250 to 300 Å into the central top surface of SiGe base layer24, forming an emitter49. Accordingly, an n-p emitter base junction is formed in alignment with central aperture33of dielectric isolation layer32.

FIG. 7is a cross-sectional view of the semiconductor structure1along a line B-B′ in the top view of FIG.6. The polysilicon and titanium silicide composite layers of the emitter structure46extend over field oxide layer22to be connected to other circuit structures in the integrated circuit.

Subsequent processing steps can be performed to complete the bipolar transistor, including providing a contact to the SiGe base layer24of the transistor. For instance,FIG. 8illustrates a bipolar transistor within the present invention including a second polysilicon layer as the base contact.FIG. 9is a cross-sectional view of the transistor ofFIG. 8as viewed along line B-B′.

To form such a base contact, and referring now toFIG. 8, a link implant using a p-type dopant (such as BF2of ˜1E14 cm−2at 85 keV) may be performed using a mask to keep the implant away from the sinkers16, thereby preventing increased base-collector capacitance. The boron forms a more heavily doped region52on the peripheral surface of SiGe base layer24. The link implant region52thus formed is bound by the edge of emitter structure46and field oxide layer22. Next, a spacer50is formed on the sides of emitter structure46by first depositing a dielectric layer, such as a silicon oxide layer, is formed over the emitter structure46and then anisotropically etching the dielectric layer. Accordingly, the SiGe layer24, including link implant region52at the periphery of SiGe layer24, is exposed adjacent to spacer50. Subsequently, a second polysilicon layer48is deposited over the entire semiconductor structure. Polysilicon layer48is first implanted with a p-type dopant, to a volume concentration of ˜1E19/cm−3, and then patterned using a mask54to form extrinsic base contact56at the exposed areas of link implant region52, thereby forming a conductive contact to SiGe base layer24.

In the above described embodiments of the bipolar transistor, dielectric isolation layer32can serve at least three functions. First, after the emitter structure46is formed over SiGe base layer24, the n-type dopants in the emitter structure46will diffuse into base layer24upon subsequent thermal process steps. The dielectric isolation layer32forms a dielectric wall around emitter structure46so that the high dopant concentration of the emitter region is spaced away from the edge of the extrinsic base region (link implant region52). As a result, the emitter-base capacitance is reduced.

Second, the dielectric isolation layer32protects the critical bird's beak areas of the field oxide layer22to prevent emitter-collector shorts from occurring due to etching of the field oxide layer22during an etch step to remove a buffer oxide layer. Moreover, dielectric isolation layer32acts as an etch stop, thus preventing damage to the surface of the base layer24during etch steps used for the formation of emitter structure46.

Third, the defining photoresist along with the dielectric isolation layer32can be used as a mask to introduce a self-aligned collector pedestal implant. The collector pedestal implant region34ofFIG. 6is centrally positioned at the collector-base junction and is self-aligned with the emitter structure46to provide maximum effectiveness.

In accordance with the present invention, the collector pedestal implant step is an optional step. In other embodiments, the collector pedestal implant step can be omitted. Furthermore, according to other embodiments of the present invention, the implantation step for the collector pedestal implant can be performed using other process sequences based on the fabrication process of the present invention. For example, the collector pedestal implant can be introduced to the semiconductor substrate10ofFIG. 2prior to the formation of the SiGe base layer24. The collector pedestal implant region will thus cover the top surface of the entire base region. This approach avoids performing the collector pedestal implant through the central aperture of SiGe layer24.

In another embodiment, after the active areas have been defined by growing the field oxide layer22, the mask36ofFIG. 4can be applied on the surface of N-epi layer14for performing the collector pedestal implant. In this manner, the collector pedestal implant region can be limited to a small region, i.e., region34. However, the collector pedestal implant region will not be self-aligned to the emitter opening formed by isolation structure32. Limiting the collector pedestal implant region to a small region has the effect of reducing the collector-base capacitance. Thereafter, the photoresist material for the collector pedestal implant is removed and the SiGe layer is formed by an epitaxial process as described above with reference to FIG.2.

The detailed description provided above is merely illustrative, and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible in view of this disclosure. The present invention is defined by the appended claims.