Voltage regulator and method for providing a regulated output

A voltage regulator includes first and second MOS transistors and a bipolar transistor. The first MOS transistor has a first conductivity type and has a drain coupled to a first power supply voltage terminal, a gate for receiving a first bias voltage, and a source. The second MOS transistor has a second conductivity type and has a source coupled to the first power supply voltage terminal, a drain coupled to the source of the first MOS transistor, and a gate for receiving a second bias voltage. The bipolar transistor has a collector coupled to the source of the first MOS transistor, a base for receiving a third bias voltage, and an emitter for providing an output voltage. The first MOS transistor and the second MOS transistor control a voltage level at the collector of the bipolar transistor in response to a varying power supply voltage provided to the first power supply voltage terminal.

BACKGROUND

This disclosure relates generally to voltage supply circuits, and more specifically, to voltage regulators and methods of providing a regulated output voltage.

2. Related Art

For efficient and desirable operation of electrical circuits, a constant voltage supply must be maintained at all operating conditions. Power supplies are used for providing a constant voltage to such electrical circuits. These power supplies or regulated power sources, receive as input an unregulated voltage, which may vary due to operational parameters, and provide an output voltage, which is fixed in magnitude and therefore called a regulated voltage.

FIG. 1illustrates a prior art voltage regulator. The voltage regulator includes a first current source12, a zener diode14, a bipolar transistor16, and a second current source18. However, this voltage regulator cannot withstand high voltages (e.g., voltages greater than 20 V). In addition, the voltage regulator ofFIG. 1will have reduced performance at low voltages because the regulator drops out of regulation when the supply voltage is below the reference voltage. Therefore, a need exists for a regulator that can function over a wide range of voltages.

DETAILED DESCRIPTION

In one embodiment, a voltage regulator and method for regulating a voltage that implements a switching scheme allowing operation in a low, intermediate, and high voltage modes. In one embodiment, an N-channel field effect transistor (FET) protects an output transistor during operation in the high voltage mode and a P-channel FET maintains operation in the intermediate voltage mode. In addition, a P-channel FET may be used to optimize the output voltage for voltage levels below the reference voltage.

While an NMOS (N channel metal oxide semiconductor) transistor can be used to allow the regulator to operate at high voltages (e.g. voltages greater than 20V), it has a greater voltage drop at larger load currents, has a slower response to transient load currents, and requires higher supply voltages to function than an npn transistor. Furthermore, the NMOS transistor may have leakage to the substrate above a voltage such as 10V. Although an npn transistor does not have these issues, an npn transistor cannot withstand collector-to-emitter voltages in excess of a voltage (e.g., 19V). Therefore, the npn transistor should be protected for supply voltages greater than this voltage plus the desired voltage. However, this protection may negatively impact the low and intermediate voltage operation of the regulator. In addition, the voltage regulator may drop out of regulation when the supply voltage falls below the reference voltage. When this occurs the output voltage will be approximately Vbe less than the supply voltage for an npn or be approximately Vgs below the supply voltage for an NMOS output transistor. The voltage regulator must output a minimum voltage (Vmin). Due to the extra Vbe or Vgs lost to the output device, the voltage regulator would cease to function at a supply voltage equal to Vmin plus the drop due to the output device. The proposed voltage regulator and its various embodiments prevent the above from happening and allow the regulator to function at low, intermediate, and high voltages.

FIG. 2illustrates a voltage regulator20in accordance with one embodiment. In one embodiment, the voltage regulator is one of many voltage regulators on a die that controls the chip. The voltage regulator20includes an output transistor22that provides an output voltage, Vreg_out. (All voltages described herein are with reference to Vss, which in one embodiment is ground.) The Vreg_out may drive a car ignition gate driver, an injector driver circuit, logic gates or any other suitable application. In one embodiment, the output transistor22is a bipolar junction transistor, such as an npn transistor.

The base of the output transistor22is coupled to current source69and voltage reference67, which can be a voltage threshold generation circuit, through its base at node N2, which receives a bias voltage. The current source65is coupled to Vdd, which is a first power supply voltage, and sources I_base_ref to the first switch24. The voltage reference67is coupled to Vss, which is a second power supply voltage, and the current source69. In the embodiment illustrated, the voltage reference67as a zener diode. The voltage reference67generates voltage Dz_vref. In other embodiments, the voltage threshold generation circuit may be a band gap reference. The current source69and the voltage reference67provide a bias voltage at node N2. The bias voltage may be a pre-regulated reference voltage that will be buffered by the output transistor22.

The output transistor22is coupled to a first switch24, a second switch26, and a third switch44. The first switch24receives a bias voltage that is clamped to a predetermined maximum voltage (e.g., greater than 18V) to protect the output transistor22from a voltage higher than that which the output transistor can withstand. The second switch26supplies a voltage to the output transistor within a predetermined voltage range (e.g., 8V to 18V). The third switch26provides additional drive strength when a power supply voltage at a power supply terminal (e.g., Vdd) is below the predetermined voltage range (e.g., less than 8V).

In the embodiment illustrated, the collector of the output transistor22is coupled to a source of the first switch24and a drain of the second switch26, and the emitter of the output transistor is coupled to a drain of the third switch44. The emitter of the output transistor22is also coupled to current source21, which sources current Iq and is coupled to Vss. The current Iq is a first current source having a first terminal coupled to the emitter of the output transistor22and a second terminal coupled to a second power supply voltage terminal (Vss). Although three switches are shown inFIG. 2, either the second switch26or the third switch44may not be present.

The first switch24is coupled to the collector node N3of the output transistor and is turned on when the voltage regulator20is operating at a high voltage, which in one embodiment is greater than approximately 18V. In one embodiment, the first switch24is an NMOS transistor. Because the bipolar transistor will breakdown under the high voltage conditions, the first switch24and its associated circuitry protects the output transistor22during this high voltage operation mode. Thus, with the presence of the first switch24and its associated circuitry, the voltage regulator20can operate in the high voltage mode. The first switch24, in one embodiment, has its gate coupled to a current source65and bias circuit63, which may be a voltage reference at node N1(e.g., a bias voltage.) The current source65and the bias circuit63provide a bias voltage to N1. This bias voltage may be a cascode or clamp voltage that protects the collector of the output transistor22. The current source65is coupled to Vdd and sources current I_bias_2. The bias circuit is coupled to the current source65, the first switch24, and Vss. In the embodiment illustrated, the bias circuit63is a zener diode. However, the bias circuit can be a different device, such as a band gap reference.

The second switch26, in one embodiment, is turned on when the voltage regulator20is operating in the intermediate mode, which is one embodiment occurs at voltages between approximately 8V and approximately 18V. In one embodiment, the second switch26is a PMOS (P-channel metal oxide semiconductor) transistor. The second switch26is coupled to an input voltage transfer function30and a comparator46. The input voltage transfer function30, in the embodiment illustrated, includes a resistor36and a resistor38. The resistors36and38are a (voltage) divider and monitor Vdd. The resistors36and38are coupled between Vss and Vdd. The resistors36and38can divide Vdd by any desired amount (e.g., divide Vdd by 1). The input voltage transfer function30can be any number of resistors or any other suitable circuitry. In addition, the input voltage transfer function30may not be present and instead of the comparator46being coupled to the input voltage transfer function30, as illustrated, it can be tied directly to Vdd.

The comparator46is also coupled to Vdd. The comparator46has an input terminal for receiving an input voltage from resistors36and38, a second input terminal for receiving a reference voltage from voltage reference39and current source41, and an output for controlling a bias voltage. The comparator46includes current source35, bipolar transistor40, bipolar transistor42, transistor60, transistor32, resistor33, and voltage reference31. The current source35generates current I_tail and is coupled to Vdd and the emitters of the bipolar transistors40and42. In one embodiment, both bipolar transistors40and42are pnp transistors. Coupled to the base of the bipolar transistor42is the current source41, which generates I_bias_1, and the voltage reference39, which generates voltage Dz_v. The base of bipolar transistor40is the input voltage transfer function30, if present, or Vdd if the input voltage transfer function30is not present. The collector of the bipolar transistor42is coupled to Vss. The collector of the bipolar transistor40is coupled to the drain of the transistor60. The source of the transistor60is coupled to Vss and the gate of the transistor60is coupled to the gate of the transistor32. Furthermore, the drain and gate of the transistor60are tied together. Transistors60and32are current mirrors60and32, which may be NMOS transistors. The source of the transistor32is coupled to Vss. The drain of the transistor32is coupled to a voltage reference31and resistor33, which are also coupled to the gate of the second switch26. The voltage reference31can be a zener diode and can generate Dz_maxvgs1. The drain of the second switch26is also coupled to the output transistor22and the first switch24. In the embodiment illustrated, when the second switch26is turned on by the input voltage transfer function30and the comparator46, the second switch26changes, (e.g., increasing) the source voltage of the first switch24. Because the gate voltage of the first switch24is constant, if the source voltage of the first switch24is increased, the gate to source voltage is decreased and the first switch24turns off. Hence, a conductance of the second switch26, as determined by the first supply voltage (in this embodiment Vdd), the comparator46, the bias voltage that is from voltage reference31, transistor32, and resistor33, at least partially controls a conductance of the first switch24.

The third switch44, in one embodiment, is turned on when the voltage regulator20is operating in the low voltage mode, which in one embodiment occurs at voltages less than approximately 8V. In one embodiment, the third switch44is a PMOS transistor. The third switch44is coupled to an input voltage transfer function48and a comparator34. The input voltage transfer function48, in the embodiment illustrated, includes current source61, voltage reference59, bipolar transistor58, current source41, and voltage reference39. The current source61is coupled to Vdd and generates current I_bias_2. The current source61is also coupled to the voltage reference59, which monitors the supply voltage and generates voltage Dz_vmin. The voltage reference59is coupled to the emitter of the bipolar transistor58. The voltage reference39is coupled to the base of the bipolar transistor58. The current source41is coupled to Vdd and sources current I_bias_1. In other embodiments, the input voltage transfer function48is similar to the input voltage transfer function30. Likewise, the input voltage transfer function30could be similar to the input voltage transfer function48; for example, the input voltage transfer function30may not include the resistors36and38. The collector of the bipolar transistor58is coupled to the transistor56, which is part of the comparator34.

The comparator34includes transistors56and54, current source55, voltage reference51, resistor53, and transistors50and52. Transistors56and54are current mirrors that may include npn bipolar transistors. The bases of the transistors56and54are coupled. The collector of the transistor56is coupled to the collector of the transistor58. The emitter of the transistor56is coupled to Vss. Furthermore, the collector and base of the transistor56are coupled. The emitter of the transistor54is also coupled to Vss. The collector of transistor54is coupled to transistor52. Transistor52is in the embodiment illustrated a PMOS transistor. Its drain is coupled to the collector of transistor54and to its gate. The source of transistor52is coupled to the source of transistor50, which in the embodiment illustrated is also a PMOS transistor. Transistor50has a gate coupled to the gate and drain of the transistor52and a drain coupled to the current source55, which generates I_compare and is coupled to Vss. the drain of the transistor50is also coupled to the voltage reference51, the resistor53, and the gate of the third switch44. The voltage reference51can be a zener diode coupled to Vdd. The voltage reference51generates Dz_maxvgs2. Resistor53is coupled to Vdd.

During the operation of the voltage regulator20, if the saturation voltage of all current sources are negligible, the load current is defined as I_load, the Rdson of the second switch26is Rp(26) and the Rdson or the third switch44is defined as Rp(44), the following occurs. When operating in the intermediate or high mode, Vdd>Dz_ref. In this mode the first switch24or the second switch26are on, the output transistor22is on, and the third switch44is off. The current, I_base, flows through Dz_vref. Hence, Vreg_out=Dz_vref−Vbe(22). In the intermediate mode, the following conditions can occur: Dz_vref>Vdd>Dz_v+Vbe(58)+Dz_vmin and, thus, Vreg_out=Vdd−Vbe(22).

When operating in the low voltage mode, Vdd<Dz_v+Vbe (58)+Dz_vmin and the transistor58turns off. This disables the current through the current mirrors54and56, which shuts off the transistor50. When the transistor50is off, the current from the current source55(I_compare) enhances the third switch44. Thus, Vreg_out=Vdd−I_load*Rp(44). In this example, Dz_vref>Dz_vmin+Dz_v+Vbe(58) so that the output voltage is never larger than Dz_vref.)

To protect the output transistor22from the voltages in the modes that are above the voltage that it can sustain from its collector to emitter (BVceo) prior to breakdown (which may be voltages above approximately 19.2V), the first switch24with higher voltage capability is used. The collector voltage of the output transistor is Vc(22)=Dz_vmax−Vgs(24) for Vdd>Dz_vmax. If the transistor26is ignored, then for Vdd<Dz_vmax, Vc(22)=Vdd−Vgs(24). Thus, Vc(22) equals the base voltage of output transistor22(Vb(22)) when Dz_vmax−Vgs(24)=Dz_vref. If Vc(22)<Vb(22) then a parasitic such as a substrate pnp, is activated and the base current of the output transistor22is partially diverted to the substrate. This diversion of current decreases the output current capability of the output transistor22. To prevent or minimize the decrease in output current the second switch26may be activated so Vc(22)>Vb(22) and the collector voltage of the output transistor22is Vdd−Rp(26)*I_load. The activation voltage of the second switch26may occur when Vdd*R38/(R36+R38) is lower than Dz_v. By setting the switching point above Dz_ref, the collector voltage of the output transistor22can be greater than its base voltage.

In one embodiment, a voltage regulator includes a first metal oxide semiconductor (MOS) transistor having a first conductivity type, the first MOS transistor having a drain coupled to a first power supply voltage terminal, a gate for receiving a first bias voltage, and a source; a second MOS transistor having a second conductivity type different than the first conductivity type, the second MOS transistor having a source coupled to the first power supply voltage terminal, a drain coupled to the source of the first MOS transistor, and a gate for receiving a second bias voltage; a bipolar transistor having a collector coupled to the source of the first MOS transistor, a base for receiving a third bias voltage, and an emitter for providing an output voltage; and a first current source having a first terminal coupled to the emitter of the bipolar transistor, and a second terminal coupled to a second power supply voltage terminal; wherein the first MOS transistor and the second MOS transistor control a voltage level at the collector of the bipolar transistor in response to a varying power supply voltage provided to the first power supply voltage terminal.

In one embodiment, a voltage regulator includes an output transistor having a first current electrode, a second current electrode coupled to an output terminal for providing a regulated output voltage, and a control electrode for receiving a first bias voltage; a first transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to the first current electrode of the output transistor, and a control electrode for receiving a second bias voltage, wherein the second bias voltage is clamped to a predetermined maximum voltage to protect the output transistor from a voltage higher than the output transistor can withstand; a second transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode for receiving a third bias voltage, wherein the second transistor for supplying a voltage to the output transistor within a predetermined voltage range; and a third transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the output terminal, and a control electrode for receiving a fourth bias voltage, wherein the fourth bias voltage for causing the third transistor to provide additional drive strength when a power supply voltage at the first power supply terminal is below the predetermined voltage range.

In one embodiment, a method for providing a regulated output voltage includes providing an output transistor and first and second transistors, the output transistor having a first current electrode, a second current electrode coupled to an output terminal for providing the regulated output voltage, and a control electrode, the first transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to the first current electrode of the output transistor, and a control electrode, and a second transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode; biasing the control electrode of the output transistor with a first bias voltage; biasing the control electrode of the first transistor with a second bias voltage, the second bias voltage being clamped to a predetermined maximum voltage to protect the output transistor from a voltage higher than the output transistor can withstand; and biasing the control electrode of the second transistor with a third bias voltage, the third bias voltage for supplying a voltage to the output transistor within a predetermined voltage range.

By now it should be appreciated that there has been provided a voltage regulator and method for regulating a voltage that allows for a high operational voltage, intermediate voltage capability, or low voltage capability, or all three voltage modes. Besides operating over a broad range of supply voltages, the voltage regulator has good transient performance.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.

Some of the above embodiments, as applicable, may be implemented using a variety of different circuitry. For example, althoughFIG. 2and the discussion thereof describe an exemplary architecture, this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between blocks are merely illustrative and that alternative embodiments may merge blocks or circuit elements or impose an alternate decomposition of functionality upon various blocks or circuit elements.