Semiconductor device

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-179328, filed on Sep. 11, 2015, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to semiconductor devices.

BACKGROUND

Silicon carbide (SiC) is expected to be used as a material for a next-generation semiconductor device. SiC has the following excellent physical properties: a band gap is three times wider than that of silicon (Si); breakdown field strength is about ten times more than that of Si; and thermal conductivity is about three times more than that of Si. The use of these characteristics makes it possible to achieve a semiconductor device which has low power consumption and can operate at a high temperature.

A metal oxide semiconductor field effect transistor (MOSFET) using SiC has a problem that the carrier mobility of a channel is lower than that in a MOSFET using Si.

DETAILED DESCRIPTION

A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type provided in the SiC layer, and the first SiC region having a portion in contact with the first plane; a second SiC region of a second conductivity type provided in the SiC layer, a part of the second SiC region provided between the first SiC region and the first plane, and a part of the second SiC region being in contact with the first plane; a third SiC region of the first conductivity type provided in the SiC layer, apart of the third SiC region provided between the second SiC region and the first plane, and a part of the third SiC region being in contact with the first plane; and a fourth SiC region of the first conductivity type provided in the SiC layer, the fourth SiC region provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions in the first plane, and the fourth SiC region provided between the first SiC region and the third SiC region in the first plane.

Hereinafter, embodiments of the invention will be described with reference to the drawings. In the following description, for example, the same or similar members are denoted by the same reference numerals and the description thereof will not be repeated.

In the following description, n++, n+, n+, n−, p++, p+, p, and p−indicate the relative impurity concentrations of each conductivity type. That is, n++indicates n-type impurity concentration that is relatively higher than that of n+, n+indicates n-type impurity concentration that is relatively higher than that of n, and n−indicates n-type impurity concentration that is relatively lower than that of n. In addition, p++indicates p-type impurity concentration that is relatively higher than that of p+, p+indicates p-type impurity concentration that is relatively higher than that of p, and p−indicates p-type impurity concentration that is relatively lower than that of p. In some cases, an n++type, an n+type, and an n−type are simply referred to as an n type, and a p++type, a p+type, and a p−type are simply referred to as a p type.

First Embodiment

A semiconductor device according to a first embodiment includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type which is provided in the SiC layer and has a portion provided in the first plane; a second SiC region of a second conductivity type which is provided in the first SiC region and has a portion provided in the first plane; a third SiC region of the first conductivity type which is provided in the second SiC region and has a portion provided in the first plane; and a fourth SiC region of the first conductivity type which is provided between the second SiC region and the gate insulating film, is interposed between the second SiC regions in the first plane, and is provided between the first SiC region and the third SiC region in the first plane.

FIGS. 1, 3, and 4are cross-sectional views schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment.FIG. 2is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment.FIG. 1is a cross-sectional view taken along the line A-A′ ofFIG. 2.FIG. 3is a cross-sectional view taken along the line B-B′ ofFIG. 2.FIG. 4is a cross-sectional view taken along the line C-C′ ofFIG. 2.

A MOSFET100according to this embodiment is, for example, a double implantation MOSFET (DIMOSFET) in which a base region (body region) and a source region are formed by ion implantation. The MOSFET100is a vertical n-channel MOSFET having electrons as carriers.

The MOSFET100includes a SiC layer10, a source electrode12, a drain electrode14, a gate insulating film16, a gate electrode18, and an interlayer insulating film20. The SiC layer10includes an n+-type drain region22, an n−-type drift region (first SiC region)24, a p-type base region (second SiC region)26, an n+-type source region (third SiC region)28, a p−-type base contact region30, and an n−-type front surface region (fourth SiC region)32.

The SiC layer10is a single crystal SiC layer. The SiC layer10is, for example, a4H-SiC layer.

The SiC layer10has a first plane and a second plane. Hereinafter, the first plane is also referred to as a front surface and the second plane is also referred to as a rear surface.

For example, the first plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (0001) face. For example, the second plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (000-1) face. The (0001) face is referred to as a silicon face. The (000-1) face is referred to as a carbon face.

The n+-type drain region22is provided on the rear surface of the SiC layer10. The drain region22includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drain region22is, for example, equal to or greater than 1×1018cm−3and equal to or less than 1×1021cm−3.

The n−-type drift region24is provided on the drain region22. For example, at least a portion of the drift region24is provided in the front surface of the SiC layer10. For example, other SiC regions may be provided between the drift region24and the front surface of the SiC layer10.

The drift region24includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drift region24is, for example, equal to or greater than 5×1015cm−3and equal to or less than 5×1016cm−3. The thickness of the drift region24is, for example, equal to or greater than 4 μm and equal to or less than 150 μm.

The p-type base region26is provided in the drift region24. For example, at least a portion of the base region26is provided in the front surface of the SiC layer10. For example, other SiC regions may be provided between the base region26and the front surface of the SiC layer10.

The base region26includes, for example, aluminum (Al) as p-type impurities. The p-type impurity concentration of the base region26is, for example, equal to or greater than 5×1015cm−3and equal to or less than 1×1019cm−3. The depth of the base region26is, for example, equal to or greater than 0.4 μm and equal to or less than 0.8 μm.

The n+-type source region28is provided in the base region26. For example, at least a portion of the source region28is provided in the front surface of the SiC layer10. For example, other SiC regions may be provided between the source region28and the front surface of the SiC layer10.

The source region28includes, for example, phosphor (P) as n-type impurities. The n-type impurity concentration of the source region28is, for example, equal to or greater than 1×1018cm−3and equal to or less than 1×1021cm−3. The depth of the source region28is less than the depth of the base region26and is, for example, equal to or greater than 0.2 μm and equal to or less than 0.4 μm.

The p+-type base contact region30is provided in the base region26. The base contact region30is provided so as to come into contact with the source region28.

The base contact region30includes, for example, aluminum (Al) as p-type impurities. The p-type impurity concentration of the base contact region30is, for example, equal to or greater than 1×1018cm−3and equal to or less than 1×1021cm−3.

The depth of the base contact region30is less than the depth of the base region26and is, for example, equal to or greater than 0.2 μm and equal to or less than 0.4 μm.

The n−-type front surface region32is provided between the base region26and the gate insulating film16. For example, the front surface region32is interposed between the base regions26in the front surface of the SiC layer10. The front surface region32and the base region26are alternately formed in the front surface of the SiC layer10. For example, other SiC regions may be provided between the n−-type front surface region32and the front surface of the SiC layer10.

In addition, the front surface region32is interposed between the drift region24and the source region28in the front surface of the SiC layer10. The front surface region32comes into contact with the source region28in the front surface of the SiC layer10. The base region26is also interposed between the drift region24and the source region28in the front surface of the SiC layer10.

The front surface region32includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the front surface region32is lower than the n-type impurity concentration of the source region28. The n-type impurity concentration of the front surface region32is, for example, equal to or greater than 5×1015cm−3and equal to or less than 5×1016cm−3.

The width (“w” inFIGS. 2 and 3) of the front surface region32in the front surface of the SiC layer10is, for example, equal to or greater than 0.05 μm and equal to or less than 2.0 μm.

The depth of the front surface region32is less than the depth of the source region28and is, for example, equal to or greater than 0.05 μm and equal to or less than 0.15 μm.

The gate insulating film16is provided on the front surface of the SiC layer10. The gate insulating film16is provided on the drift region24, the base region26, the source region28, and the front surface region32. The gate insulating film16is, for example, a silicon oxide film. For example, a high-k insulating film (high-permittivity insulating film) can be applied as the gate insulating film16.

The gate electrode18is provided on the gate insulating film16. The gate electrode18is a conductive layer. The gate electrode18is, for example, a polysilicon film including p-type impurities or n-type impurities.

The interlayer insulating film20is provided on the gate electrode18. The interlayer insulating film20is, for example, a silicon oxide film.

The front surface region32which is interposed between the source region28and the drift region24below the gate electrode18functions as a channel region of the MOSFET100.

The source electrode12is provided on the front surface of the SiC layer10. The source electrode12is electrically connected to the source region28and the base contact region30. The source electrode12comes into contact with the source region28and the base contact region30. The source electrode12also has a function of applying potential to the base region26.

The source electrode12includes metal. Metal forming the source electrode12has, for example, a stacked structure of titanium (Ti) and aluminum (Al). The source electrode12may include metal silicide or metal carbide which comes into contact with the SiC layer10.

The drain electrode14is provided on the rear surface of the SiC layer10. The drain electrode14is electrically connected to the drain region22.

The drain electrode14is made of, for example, metal. The metal forming the drain electrode14has, for example, a stacked structure of nickel (Ni) and gold (Au). The drain electrode14may include metal silicide or metal carbide which comes into contact with the rear surface of the SiC layer10.

Next, a method for manufacturing the MOSFET100according to this embodiment will be described. In particular, a method for forming the front surface region32will be described.

FIGS. 5 and 6are cross-sectional views schematically illustrating the semiconductor device which is being manufactured in the semiconductor device manufacturing method according to this embodiment.

The drift region24is formed on the drain region22by epitaxial growth (FIG. 5).

Then, a mask member50is formed on the front surface of the drift region24. The mask member50is a silicon oxide film which is formed by, for example, a chemical vapor deposition (CVD) method.

Then, aluminum (Al) ions, which are p-type impurity ions, are implanted into the drift region24, using the mask member50as a mask (FIG. 6). The base region26is formed by the ion implantation.

The aluminum ions are implanted by, for example, oblique ion implantation. No aluminum is introduced into a region covered with the mask member50and the base region26is not formed in the region. In other words, a portion of the drift region24which is covered with the mask member50remains, without being removed, and the front surface region32is formed in the remaining portion. As a result, the n-type impurity concentration of the front surface region32is substantially equal to the n-type impurity concentration of the drift region24.

Then, the mask member50is removed. Then, the n+-type source region28, the p+-type base contact region30, the gate insulating film16, the gate electrode18, the interlayer insulating film20, the source electrode12, and the drain electrode14are formed by a known process. In this way, the MOSFET100is manufactured.

Next, the function and effect of the semiconductor device according to the embodiment will be described.

The MOSFET using SiC has a problem that the mobility of carriers is lower than that in a MOSFET using Si. It is considered that one of the causes of the problem is the formation of a channel in the impurity region formed in the SiC layer.

For example, the crystallinity (translation symmetry) of SiC is disrupted by ion implantation and the mobility of carriers is reduced. In addition, the mobility of carriers is reduced by Coulomb scattering caused by charge which is trapped in crystal defects that generated in the SiC layer due to ion implantation. Furthermore, the mobility of carriers is reduced by roughness scattering caused by the unevenness of the front surface of the SiC layer which occurs due to ion implantation.

In the MOSFET100according to this embodiment, a channel is formed in the front surface region32into which no impurity ions are implanted. Therefore, the disruption of crystallinity, Coulomb scattering, or roughness scattering caused by ion implantation does not occur. As a result, the mobility of carriers is improved.

During the turn-off operation of the MOSFET100according to this embodiment, the front surface region32is completely depleted and the MOSFET100is turned off.

When the width (“w” inFIGS. 2 and 3) of the front surface region32interposed between the base regions26in the front surface of the SiC layer10is w [μm], the p-type impurity concentration of the base region26is NA[cm−3], the n-type impurity concentration of the front surface region32is ND[cm−3], built-in potential (Vbi) is 3.2 [V], an elementary charge (q) is 1.602×10−19[C], the specific permittivity of vacuum (ε0) is 8.854×10−14[F/cm], and the specific permittivity of SiC (ε) is 9.7, it is preferable that the following inequality be satisfied in order to completely deplete the front surface region32:

For example, when other SiC regions are provided between the n−-type front surface region32and the SiC layer10, w is the width of a portion of the n−-type front surface region32which is close to the front surface of the SiC layer10.

When the above-mentioned inequality is satisfied, the front surface region32is completely depleted by depletion layers which are spread from both sides of the front surface region32.

For example, when NAis changed in the range of 5×1015[cm−3] to 5×106[cm−3] and NDis changed in the range of 5×1015[cm−3] to 5×1016[cm−3], the maximum value of w is 1.6 μm. At that time, NAis 5×1016[cm−3] and NDis 5×1015[cm−3]. Therefore, it is preferable that the width of the front surface region32interposed between the base regions26in the front surface of the SiC layer10be equal to or less than 1.6 μm.

In addition, it is preferable that the width of the front surface region32interposed between the base regions26be gradually reduced in a direction from the front surface to the rear surface of the SiC layer10in order to completely deplete the front surface region32during the turn-off operation of the MOSFET100. For example, as illustrated inFIG. 3, it is preferable that the front surface region32have an inverted triangle shape. Since the width of the front surface region32is gradually reduced in the depth direction, the depletion layers which are spread from both sides of the front surface region32are likely to be blocked.

It is preferable that the width (“w” inFIG. 3) of the front surface region32interposed between the base regions26in the front surface of the SiC layer10be less than the depth (“d” inFIG. 3) of the front surface region32interposed between the base regions26from the front surface of the SiC layer10, in order to completely deplete the front surface region32. Since the width of the front surface region32in the front surface of the SiC layer10is less than the depth thereof, the front surface region32is likely to be blocked by the depletion layers which are spread from both sides of the front surface region32.

It is preferable that the density of crystal defects in the front surface region32be lower than the density of crystal defects in the base region26. The Coulomb scattering of carriers due to crystal defects is suppressed and the mobility of carriers is improved. According to the manufacturing method of this embodiment, it is possible to reduce the density of crystal defects in the front surface region32.

The impurity concentration of the front surface region32and the base region26can be measured by, for example, secondary ion mass spectrometry (SIMS). In addition, the width or depth of the front surface region32can be measured by, for example, scanning capacitance microscopy (SCM). The magnitude relationship between the impurity concentrations of the front surface region32and the drift region24can be determined by, for example, SCM.

The magnitude relationship between the densities of crystal defects in the front surface region32and the base region26can be determined by, for example, a transmission electron microscope (TEM) method.

In the MOSFET100according to this embodiment, the front surface region32with high carrier mobility can be formed at the same time as the base region26. Therefore, it is possible to easily manufacture the MOSFET100according to this embodiment.

As described above, according to the MOSFET100of this embodiment, it is possible to improve the carrier mobility of a channel.

Second Embodiment

A semiconductor device according to a second embodiment is similar to the semiconductor device according to the first embodiment except that the second SiC region is provided between the fourth SiC region and the third SiC region in the first plane. Therefore, the description of the same content as that in the first embodiment will not be repeated.

FIG. 7is a cross-sectional view schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment.FIG. 8is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment.FIG. 7is a cross-sectional view taken along the line D-D′ ofFIG. 8.

A MOSFET200according to this embodiment is a DIMOSFET. The MOSFET200is a vertical n-channel MOSFET having electrons as carriers.

In the MOSFET200, a base region26is provided between a front surface region32and a source region28in the front surface of a SiC layer10. When the p-type base region26is provided, cutoff characteristics during the turn-off operation of the MOSFET200are improved, as compared to a case in which the p-type base region26is not provided.

According to the MOSFET200of this embodiment, the carrier mobility of a channel can be improved by the same function as that in the first embodiment. In addition, the cutoff characteristics during the turn-off operation of the MOSFET200are improved.

In the first and second embodiments, the4H-SiC substrate is used as the SiC substrate. However, other crystal forms, such as 3C-SiC and 6H-SiC, may be used.

In the first and second embodiments, nitrogen (N) and phosphor (P) are given as examples of the n-type impurities. However, for example, arsenic (As) and antimony (Sb) may be used as the n-type impurities. In addition, aluminum (Al) is given as an example of the p-type impurities. However, boron (B) may be used.

In the first and second embodiments, the vertical MOSFET is given as an example of the semiconductor device. However, the invention is not limited to the vertical MOSFET. The invention can be applied to other semiconductor devices including transistors having a metal insulator semiconductor (MIS) structure. For example, the invention can also be applied to a horizontal MOSFET. In addition, for example, the invention can be applied to a vertical insulated gate bipolar transistor (IGBT).

In the first and second embodiments, the first conductivity type is an n type and the second conductivity type is a p type. However, the first conductivity type may be a p type and the second conductivity type may be an n type. In this case, the transistor is a p-channel transistor having holes as carriers.