Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-014251, filed on Jan. 30, 2017; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

BACKGROUND

It is desirable to reduce the on-resistance of a semiconductor device.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes a first electrode region, a second electrode region, and a third electrode region. A first direction is from the first electrode toward the first electrode region and crosses a second direction. The second direction is from the first electrode region toward the second electrode region. A position of the third electrode region in the first direction is between a position of the first electrode region in the first direction and a position of the first electrode in the first direction. The first semiconductor region is of a first conductivity type. The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The first partial region is separated from the first electrode in a third direction. The third direction crosses the first direction and the second direction. The second partial region is separated from the first electrode region in the third direction. A position of the third partial region in the first direction is between a position of the first partial region in the first direction and a position of the second partial region in the first direction. At least a portion of the third partial region is between the first electrode and the first electrode region in the first direction. The fourth partial region is separated from the second electrode region in the third direction. The fifth partial region is between the second partial region and the fourth partial region. The second semiconductor region is of a second conductivity type. The second semiconductor region includes a sixth partial region, a seventh partial region, an eighth partial region, and a ninth partial region. The sixth partial region is positioned between the second partial region and the first electrode region in the third direction. A portion of the seventh partial region is positioned between the first electrode region and the at least a portion of the third partial region in the first direction. The eighth partial region is positioned between the fourth partial region and the second electrode region in the third direction. At least a portion of the ninth partial region is positioned between the first electrode region and the second electrode region in the second direction. The third semiconductor region is of the second conductivity type. The third semiconductor region is connected to the second semiconductor region. The third semiconductor region is positioned between the third electrode region and the at least a portion of the third partial region in the third direction. The third semiconductor region is positioned between the first electrode and another portion of the seventh partial region in the first direction. The fourth semiconductor region is of the first conductivity type. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes a tenth partial region, an eleventh partial region, and a twelfth partial region. The tenth partial region is positioned between the third semiconductor region and a portion of the third electrode region in the third direction. The eleventh partial region is positioned between the seventh partial region and another portion of the third electrode region in the third direction. The twelfth partial region is positioned between the ninth partial region and the second electrode in the third direction. The first insulating film is provided between the first electrode and the first semiconductor region, between the first electrode and the third semiconductor region, and between the first electrode and the fourth semiconductor region.

First Embodiment

FIG. 1AandFIG. 1Bare schematic views illustrating a semiconductor device according to a first embodiment.

FIG. 2AandFIG. 2Bare schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

FIG. 3is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

FIG. 4AtoFIG. 4Care schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

FIG. 5AandFIG. 5Bare schematic cross-sectional views illustrating the semiconductor device according to the first embodiment.

FIG. 1Ais a schematic see-through plan view.FIG. 1Acorresponds to a plan view as viewed along arrow AR ofFIG. 1B.FIG. 1B,FIG. 2A,FIG. 2B, andFIG. 3respectively are cross-sectional views along line A1-A2, line B1-B2, line C1-C2, and line E1-E2ofFIG. 1A.FIG. 4AtoFIG. 4C,FIG. 5A, andFIG. 5Brespectively are cross-sectional views along line L1-L2, line M1-M2, line N1-N2, line O1-O2, and line P1-P2ofFIG. 1B. As shown in these drawings, the semiconductor device110according to the embodiment includes a first electrode21, a second electrode22, first to fourth semiconductor regions11to14, and a first insulating film31. A second insulating film32and a third electrode23are further provided in the example. As shown inFIG. 1BandFIG. 2B, the second electrode22includes a first electrode region er1, a second electrode region er2, and a third electrode region er3. As described below, other electrode regions may be further provided in the second electrode22.

A first direction D1from the first electrode21toward the first electrode region er1crosses a second direction D2from the first electrode region er1toward the second electrode region er2.

The first direction D1is, for example, an X-axis direction.

One direction perpendicular to the X-axis direction is taken as a Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is taken as a Z-axis direction.

In the example, the second direction D2is the Y-axis direction.

As shown inFIG. 1B, the position of the third electrode region er3in the first direction D1(the X-axis direction) is between the position of the first electrode region er1in the first direction D1and the position of the first electrode21in the first direction D1.

As shown inFIG. 3, the second electrode region er2is continuous with the first electrode region er1. For example, the second electrode region er2is linked to the first electrode region er1by a fourth electrode region er4. The second electrode region er2is electrically connected to the first electrode region er1.

The first semiconductor region11is of a first conductivity type. The first semiconductor region11includes a first partial region11a, a second partial region11b, a third partial region11c, a fourth partial region11d, and a fifth partial region11e.

The first partial region11ais separated from the first electrode21in a third direction D3. The third direction D3crosses the first direction D1and the second direction D2. In the example, the third direction D3is the Z-axis direction. The second partial region11bis separated from the first electrode region er1in the third direction D3(the Z-axis direction).

The position of the third partial region11cin the first direction D1(the X-axis direction) is between the position of the first partial region11ain the first direction D1and the position of the second partial region11bin the first direction D1. At least a portion of the third partial region11cis between the first electrode21and the first electrode region er1in the first direction D1(the X-axis direction).

As shown inFIG. 2B, the fourth partial region11dis separated from the second electrode region er2in the third direction D3(the Z-axis direction).

As shown inFIG. 3, the fifth partial region11eis between the second partial region11band the fourth partial region11din the second direction D2.

A second semiconductor region12is of a second conductivity type.

The first conductivity type is an n-type; and the second conductivity type is a p-type. The first conductivity type may be the p-type; and the second conductivity type may be the n-type. Hereinbelow, the first conductivity type is taken to be the n-type; and the second conductivity type is taken to be the p-type.

The second semiconductor region12includes a sixth partial region12f, a seventh partial region12g, an eighth partial region12h, and a ninth partial region12i.

As shown inFIG. 1BandFIG. 3, the sixth partial region12fis positioned between the second partial region11band the first electrode region er1in the third direction D3(the Z-axis direction).

A portion (inFIG. 1B, the lower portion) of the seventh partial region12gis positioned between the first electrode region er1and the at least a portion of the third partial region11crecited above in the first direction D1(the X-axis direction).

As shown inFIG. 2BandFIG. 3, the eighth partial region12his positioned between the fourth partial region11dand the second electrode region er2in the third direction D3(the Z-axis direction).

As shown inFIG. 3, at least a portion of the ninth partial region12iis positioned between the first electrode region er1and the second electrode region er2in the second direction D2(the Y-axis direction).

In the example as shown inFIG. 3, the ninth partial region12icontacts the first electrode region er1in the second direction D2. The ninth partial region12icontacts the second electrode region er2in the second direction D2.

In the example as shown inFIG. 3, the fourth electrode region er4is provided in the second electrode22. The position of the fourth electrode region er4in the second direction D2(the Y-axis direction) is positioned between the position of the first electrode region er1in the second direction D2and the position of the second electrode region er2in the second direction D2. The ninth partial region12iis positioned between the fourth electrode region er4and the fifth partial region11ein the third direction D3(the Z-axis direction).

As shown inFIG. 1B, a third semiconductor region13is connected to the second semiconductor region12. The third semiconductor region13is of the second conductivity type (in the example, the p-type). The third semiconductor region13is positioned between the third electrode region er3and the at least a portion of the third partial region11crecited above in the third direction D3(the Z-axis direction). The third semiconductor region13is positioned between the first electrode21and another portion (inFIG. 1B, the upper portion) of the seventh partial region12gin the first direction D1(the X-axis direction).

The fourth semiconductor region14is electrically connected to the second electrode22. The fourth semiconductor region14is of the first conductivity type (in the example, the n-type). The fourth semiconductor region14includes a tenth partial region14j, an eleventh partial region14k, and a twelfth partial region14l.

As shown inFIG. 1B, the tenth partial region14jis positioned between the third semiconductor region13and a portion of the third electrode region er3in the third direction D3(the Z-axis direction).

As shown inFIG. 1BandFIG. 5B, the tenth partial region14jis positioned between the first electrode21and the first electrode region er1in the first direction D1(the X-axis direction).

As shown inFIG. 1B, the eleventh partial region14kis positioned between the seventh partial region12gand another portion of the third electrode region er3in the third direction D3(the Z-axis direction).

As shown inFIG. 1BandFIG. 5B, the eleventh partial region14kis positioned between the tenth partial region14jand the first electrode region er1in the first direction D1(the X-axis direction).

As shown inFIG. 3, the twelfth partial region14lis positioned between the ninth partial region12iand the second electrode22in the third direction D3(the Z-axis direction).

As shown inFIG. 3andFIG. 5B, for example, the twelfth partial region14lis positioned between the first electrode region er1and the second electrode region er2in the second direction D2(the Y-axis direction). For example, the twelfth partial region14lcontacts the first electrode region er1in the second direction D2(the Y-axis direction). For example, the twelfth partial region14lcontacts the second electrode region er2in the second direction D2(the Y-axis direction).

As shown inFIG. 3, the twelfth partial region14lis positioned between the ninth partial region12iand the fourth electrode region er4in the third direction D3(the Z-axis direction).

As shown inFIG. 1B, the first insulating film31is provided between the first electrode21and the first semiconductor region11, between the first electrode21and the third semiconductor region13, and between the first electrode21and the fourth semiconductor region14.

As shown inFIG. 1B, the first semiconductor region11is positioned between the third electrode23and the first electrode21in the third direction D3(the Z-axis direction) and between the third electrode23and the second electrode22in the third direction D3. Also, the other semiconductor regions are positioned between the third electrode23and the second electrode22in the third direction D3.

In the example as shown inFIG. 1B, the second electrode22further includes a portion overlapping the first electrode21in the third direction D3(the Z-axis direction). The second insulating film32is further provided in the example. The second insulating film32is positioned between the first electrode21and the portion (the overlapping portion) of the second electrode22recited above in the third direction D3. The second insulating film32electrically isolates the first electrode21and the second electrode22from each other.

The first electrode21functions as, for example, a gate electrode. The first insulating film31functions as, for example, a gate insulating film. The second electrode22functions as, for example, a source electrode. The third electrode23functions as, for example, a drain electrode.

For example, the current that flows between the second electrode22and the third electrode23is controlled according to the potential of the first electrode21. For example, the fourth semiconductor region14, the third semiconductor region13, and the first semiconductor region11are used as a channel.

As shown inFIG. 5AandFIG. 5B, the first electrode21extends along the second direction D2(the Y-axis direction). The second electrode region erg is separated from the first electrode21in the first direction D1(the X-axis direction). The first electrode21is, for example, a trench gate electrode.

The semiconductor device110is, for example, a vertical MOSFET (metal-oxide-semiconductor field-effect transistor).

In the semiconductor device110, for example, the surface area of the channel per unit surface area can be increased by the structure of the trench gate electrode. A low on-resistance is obtained.

In the embodiment, for example, the fourth semiconductor region14is used as a contact region for the second electrode22. In the embodiment, the fourth semiconductor region14includes the tenth partial region14jand the eleventh partial region14k. As shown inFIG. 1BandFIG. 5B, these partial regions are arranged with the first electrode region er1in the first direction D1(the X-axis direction). Electrical contact with the second electrode22is obtained in these partial regions.

In the embodiment, the twelfth partial region14lis provided in the fourth semiconductor region14in addition to the tenth partial region14jand the eleventh partial region14k. As shown inFIG. 3andFIG. 5B, the twelfth partial region14lis arranged with the first electrode region er1(and the second electrode region er2) in the second direction D2(the Y-axis direction). The twelfth partial region14lalso functions as a contact region with the second electrode22. By providing the twelfth partial region14l, the contact region can be enlarged. Thereby, the on-resistance can be reduced.

According to the embodiment, a semiconductor device can be provided in which the on-resistance can be reduced.

For example, the first semiconductor region11, the second semiconductor region12, the third semiconductor region13, and the fourth semiconductor region14include silicon carbide (SIC). Thereby, a high breakdown voltage is obtained. These semiconductor regions may include, for example, Al, N, P, As, etc.

In such a case, in the embodiment, at least a portion (the first electrode region er1, the second electrode region er2, etc., recited above) of the second electrode22overlaps the first electrode21in the first direction D1(the X-axis direction). The second semiconductor region12is provided under this portion of the second electrode22. Thereby, for example, the electric field that is applied to the first insulating film31is relaxed. For example, a depletion layer extends toward the first insulating film31from the second semiconductor region12under the first electrode region er1. Thereby, for example, the electric field that is applied to the first insulating film31is relaxed. Thereby, high reliability is obtained.

For example, the relaxation effect of the electric field is increased by setting the impurity concentration of the second conductivity type in the second semiconductor region12to be high.

For example, the difference between a first concentration of an impurity of the second conductivity type in the second semiconductor region12and a second concentration of an impurity of the first conductivity type in the second semiconductor region12is larger than the difference between a third concentration of the impurity of the second conductivity type in the third semiconductor region13and a fourth concentration of the impurity of the first conductivity type in the third semiconductor region13. For example, the first concentration is higher than the second concentration. The third concentration is higher than the fourth concentration.

On the other hand, for example, the difference between a fifth concentration of an impurity of the first conductivity type in the fourth semiconductor region14and a sixth concentration of an impurity of the second conductivity type in the fourth semiconductor region14is larger than the difference between a seventh concentration of the impurity of the first conductivity type in the first semiconductor region11and an eighth concentration of the impurity of the second conductivity type in the first semiconductor region11. For example, the fifth concentration is higher than the sixth concentration. The seventh concentration is higher than the eighth concentration.

By setting the impurity concentration of the first conductivity type in the fourth semiconductor region14to be high, for example, a low contact resistance is obtained between the second electrode22and the fourth semiconductor region14.

In the embodiment, the first semiconductor region11is, for example, an n-layer. The second semiconductor region12is, for example, a p+-layer. The third semiconductor region13is, for example, a p-layer. The fourth semiconductor region14is an n+-layer.

In the case where the semiconductor region includes SiC, the impurity of the first conductivity type includes, for example, at least one selected from the group consisting of nitrogen (N), phosphorus (P), and arsenic (As). The impurity of the second conductivity type includes, for example, at least one selected from the group consisting of aluminum (Al), boron (B), and germanium (Ge).

As shown inFIG. 1B, the lower end of the second semiconductor region12is positioned lower than the lower end of the first insulating film31. Thereby, for example, the electric field that is applied to the first insulating film31can be relaxed effectively.

As shown inFIG. 1B, for example, the position in the third direction D3(the Z-axis direction) of a boundary BR2between the first electrode region er1and the sixth partial region12fof the second semiconductor region12is positioned between the position in the third direction D3of the second partial region11bof the first semiconductor region11and the position in the third direction D3of a boundary BR1between the first partial region11aand the first insulating film31.

For example, the boundary BR2is lower than the boundary BR1. The sixth partial region12fis even lower than the boundary BR2. The second partial region11bis even lower than the sixth partial region12f.

As shown inFIG. 1B, at least a portion of the sixth partial region12fdoes not overlap the first insulating film31in the first direction D1(the X-axis direction).

As shown inFIG. 1B, a distance dz2along the third direction D3between the third electrode23and the sixth partial region12fis shorter than a distance dz1along the third direction D3between the third electrode23and the first insulating film31.

By such a configuration, for example, the electric field that is applied to the first insulating film31can be relaxed effectively.

As shown inFIG. 1B, a boundary Bpn may be defined between the third partial region11cof the first semiconductor region11and the seventh partial region12gof the second semiconductor region. The boundary Bpn corresponds to the boundary between the region of the first conductivity type and the region of the second conductivity type. At the boundary Bpn, for example, the impurity concentration of the first conductivity type is substantially the same as the impurity concentration of the second conductivity type.

For example, the distance along the first direction D1between the first insulating film31and the boundary Bpn is taken as a first width w1. In the embodiment, the first width w1is, for example, not less than 0.2 μm and not more than 2.5 μm.

For example, the distance along the first direction D1between the first electrode region er1and the first insulating film31is taken as a second width w2. The second width w2is, for example, not less than 0.5 μm and not more than 3 μm.

For example, the distance along the third direction D3between a boundary BR3and the boundary BR1is taken as a height h1, where the boundary BR3is between the second partial region11bof the first semiconductor region11and the sixth partial region12fof the second semiconductor region12, and the boundary BR1is between the first insulating film31and the first partial region11a. The height h1is, for example, not less than 0.5 μm and not more than 3 μm.

As shown inFIG. 3, the distance along the second direction D2between the first electrode region er1and the second electrode region er2is taken as a third width w3. The third width w3is, for example, not less than 0.5 μm and not more than 2 μm. The third width w3is, for example, about 1 μm. For example, the third width w3corresponds to the length along the second direction D2of the twelfth partial region14l. For example, the third width w3corresponds to the length along the second direction D2of the ninth partial region12i.

In the example as shown inFIG. 3andFIG. 5B, the first electrode region er1does not overlap the twelfth partial region14lin the third direction D3. The second electrode region er2does not overlap the twelfth partial region14lin the third direction D3. In the example, these electrode regions are separated by the twelfth partial region14land the ninth partial region12i. As described below, at least a portion of these electrode regions may be linked.

As shown inFIG. 4A, the first partial region11acorresponds to at least a portion of a region having a band configuration where the first electrode21is provided. In the example, the second partial region11b, the fifth partial region11e, and the fourth partial region11dcorrespond to regions having band configurations where the first electrode region er1, the second electrode region er2, etc., of the second electrode22are provided.

In the example as shown inFIG. 4B, the second semiconductor region12has a band configuration along the second direction D2.

In the example as shown inFIG. 4C, the first electrode region er1, the second electrode region er2, etc., are provided to be separated from each other inside the second semiconductor region12having the band configuration.

As shown inFIG. 5A, the first electrode21has a band configuration along the second direction D2.

As shown inFIG. 5AandFIG. 1B, for example, the first electrode21extends along the second direction D2and the third direction D3. The second direction D2and the third direction D3are aligned with the m-plane of the semiconductor region (e.g., the first semiconductor region11). For example, the first direction D1(the X-axis direction) may be substantially perpendicular to the ni-plane. For example, the first direction D1may be of substantially aligned with the a-plane.

As shown inFIG. 5B, the boundary Bpn is recessed partially at a portion corresponding to the twelfth partial region14l. For example, such a configuration can be formed by a manufacturing method including oblique implantation, etc., described below.

FIG. 6AandFIG. 6Bare schematic views illustrating another semiconductor device according to the first embodiment.

In the other semiconductor device111according to the embodiment as shown in these drawings, the second electrode22includes multiple conductive films (a first conductive film22a, a second conductive film22b, etc.). For example, the first conductive film22ais provided between the second conductive film22band the fourth semiconductor region14. Otherwise, the semiconductor device111is similar to the semiconductor device110.

The first conductive film22aincludes, for example, at least one selected from the group consisting of Al and Ni. The first conductive film22ais, for example, a contact metal film.

The second conductive film22bincludes, for example, at least one selected from the group consisting of Al and Ti. For example, at least a portion of a bonding pad may be formed of the second conductive film22b.

Other conductive films may be further provided in the second electrode22. These conductive films are stacked.

An example of a method for manufacturing the semiconductor device according to the embodiment will now be described. The following example corresponds to an example of the method for manufacturing the semiconductor device111.

A first semiconductor film11F is provided as shown inFIG. 7AtoFIG. 7C. For example, the first semiconductor film11F is obtained by performing epitaxial growth on a not-illustrated substrate. The first semiconductor film11F is used to form the first semiconductor region11. The first semiconductor film11F is of the first conductivity type. For example, a fourth semiconductor film14F is formed in the upper portion of the first semiconductor film11F. For example, an impurity of the first conductivity type is ion-implanted into the vicinity of the upper surface of the first semiconductor film11F. Thereby, the fourth semiconductor film14F is formed. A portion of the fourth semiconductor film14F is used to form the fourth semiconductor region14. These semiconductor regions include, for example, SiC.

The first semiconductor film11F and the fourth semiconductor film14F are included in a patterning body PM.

As shown inFIG. 8AtoFIG. 8C, a portion of the fourth semiconductor film14F and a portion of the first semiconductor film11F are removed using a first mask M1having openings. Thereby, a first trench T1is formed. The first trench T1includes multiple portions (a first portion T1a, a second portion T1b, etc.). The multiple portions are arranged in the X-axis direction and the Y-axis direction. The direction that connects the first portion T1aand the second portion T1bis aligned with the Y-axis direction. A portion of the first portion T1amay be linked to a portion of the second portion T1b. For example, the first trench T1is used as a source trench. The distance along the second direction D2between two portions (the first portion T1aand the second portion T1b) of the first trench T1is, for example, about 1 μm. The distance corresponds to the third width w3(referring toFIG. 3).

Ion implantation of a first element Im1is performed as shown inFIG. 9AtoFIG. 9C. The ion implantation is performed from an oblique direction with respect to the Z-axis direction as an axis. For example, the ion implantation may be performed multiple times while modifying the direction of the ion implantation. The first element Im1is an element used as the impurity of the second conductivity type. The first element Im1includes, for example, Al.

Thus, the element (the first element Im1) of the second conductivity type is implanted from multiple directions tilted with respect to an upper surface PMf of the patterning body PM.

The first mask M1is removed as shown inFIG. 10AtoFIG. 10C. A second semiconductor film12F of the second conductivity type is formed by the ion implantation recited above. A region where the first element Im1is substantially not implanted is used to form the first semiconductor region. A portion of the second semiconductor film12F is used to form the ninth partial region12i. The fourth semiconductor film14F that is provided on the region used to form the ninth partial region12iis used to form the twelfth partial region14l.

Ion implantation of a second element Im2is performed as shown inFIG. 11AtoFIG. 11C. The second element Im2is of the second conductivity type. The second element Im2includes, for example, Al. The ion implantation is performed via the fourth semiconductor film14F. The third semiconductor region13is formed by the ion implantation. The second semiconductor region12and the fourth semiconductor region14are formed.

A second trench T2is formed as shown inFIG. 12AtoFIG. 12C. The second trench T2is, for example, a gate trench.

As shown inFIG. 13AtoFIG. 13C, an insulating film31F is formed; further, the first electrode21is formed. As described below, the insulating film31F is used to form the first insulating film31. The first electrode21is, for example, polysilicon. The insulating film31F (the first insulating film31) includes, for example, silicon oxide.

The second insulating film32is formed as shown inFIG. 14AtoFIG. 14C. A portion of the insulating film31F is removed in the processing of a portion of the formation of the second insulating film32. Thereby, the first insulating film31is formed. For example, the fourth semiconductor region14, the second semiconductor region12, etc., are exposed.

The first conductive film22ais formed as shown inFIG. 15AtoFIG. 15C.

The second conductive film22bis formed as shown inFIG. 16AtoFIG. 16C.

Several examples of other semiconductor devices according to the embodiment will now be described. The portions that are different from those of the semiconductor device110are described in the description hereinbelow. Multiple conductive films (the first conductive film22a, the second conductive film22b, etc.) may be provided in the second electrode22in the semiconductor devices of the examples recited below as well.

FIG. 17toFIG. 22are schematic views illustrating other semiconductor devices according to the first embodiment.

These drawings correspond respectively to a line P1-P2cross section ofFIG. 1B.

In a semiconductor device111as shown inFIG. 17, a boundary Bns between the first electrode region er1and the twelfth partial region14lis tilted with respect to the first direction D1and tilted with respect to the second direction D2.

Because the boundary Bns is tilted, for example, the number of the ion implantations from the oblique direction of the first element Im1is reduced. For example, a semiconductor device having high productivity is obtained.

In a semiconductor device112as shown inFIG. 18, protrusions are provided at the corners of the first electrode region er1and the second electrode region er2. The distance along the second direction D2between the protrusions is shorter than the distance along the second direction D2between the regions other than the protrusions.

As shown inFIG. 18, the first electrode21extends along the second direction D2(the Y-axis direction). The first electrode region er1and the second electrode region er2are separated from the first electrode21in the first direction D1(the X-axis direction). The first electrode region er1includes a first inner region eri1and a first outer region ero1. The first outer region ero1is positioned between the first inner region eri1and the first electrode21in the first direction D1. The second electrode region er2includes a second inner region eri2and a second outer region ero2. The second outer region ero2is positioned between the second inner region eri2and the first electrode21in the first direction D1.

The distance along the second direction D2between the first outer region ero1and the second outer region ero2is taken as a second distance d2. The distance along the second direction D2between the first inner region eri1and the second inner region eri2is taken as a first distance d1. In the semiconductor device112, the second distance d2is shorter than the first distance d1.

By such a configuration, for example, the amount of the recess of the boundary Bpn (the boundary between the third partial region11cand the seventh partial region12g) can be small. Thereby, for example, a high effect of relaxing the electric field applied to the first insulating film31can be maintained.

In a semiconductor device113as shown inFIG. 19, a portion of the first electrode region er1is linked to a portion of the second electrode region er2. For example, the second electrode22further includes a fifth electrode region er5. The fifth electrode region er5is between a portion of the first electrode region er1and a portion of the second electrode region er2in the second direction D2(the Y-axis direction). The fifth electrode region er5connects the portion of the first electrode region er1to the portion of the second electrode region er2.

In the example, the twelfth partial region14lof the fourth semiconductor region14is provided between the first electrode region er1and the second electrode region er2at a portion where the fifth electrode region er5is not provided.

As shown inFIG. 20, the fifth electrode region er5is provided in a semiconductor device114as well.

As shown inFIG. 21, the fifth electrode region er5is provided in a semiconductor device115as well. In the example, the twelfth partial region14lis provided on the first electrode21side. In the example, a recess can be considered to be provided in a portion of the second electrode22having a band configuration. The twelfth partial region14lis provided in the recess.

As shown inFIG. 22, the fifth electrode region er5is provided in a semiconductor device116as well. In the example, a recess can be considered to be provided in a portion of the second electrode22having a band configuration.

Recesses are provided on two sides of the second electrode22having the band configuration. The twelfth partial region14lis provided in each of the recesses. The multiple recesses are provided alternately on the two sides of the second electrode22having the band configuration. The multiple twelfth partial regions141are provided alternately on the two sides of the second electrode22.

The twelfth partial region14lis provided in the semiconductor devices111to116as well. Thereby, for example, the contact resistance can be reduced. For example, a semiconductor device can be provided in which the on-resistance can be reduced.

Second Embodiment

The embodiment is related to a method for manufacturing a semiconductor device.

In the manufacturing method, for example, the first trench T1that includes multiple portions is formed in the upper surface PMf of the patterning body PM (referring toFIG. 8AtoFIG. 8C). The patterning body PM includes the first semiconductor film11F of the first conductivity type. The multiple portions include, for example, the first portions T1aand T1b, etc.

The manufacturing method includes implanting an element of the second conductivity type after forming the first trench T1(referring toFIG. 9AtoFIG. 9C). The element of the second conductivity type includes, for example, the first element Im1. The implantation includes implanting the element into the patterning body PM from multiple directions tilted with respect to the upper surface PMf.

Thereby, as described in reference toFIG. 10AtoFIG. 10C, a region that corresponds to the ninth partial region12iof the second semiconductor region12and a portion that corresponds to the twelfth partial region14lof the fourth semiconductor region14can be formed.

According to the manufacturing method according to the embodiment, a method for manufacturing a semiconductor device can be provided in which the on-resistance can be reduced.

According to the embodiments, a semiconductor device and a method for manufacturing the semiconductor device can be provided in which the on-resistance can be reduced.

In this specification, the “state of being electrically connected” includes the state in which multiple conductive bodies are physically in contact, and a current flows between the multiple conductive bodies. The “state of being electrically connected” includes the state in which another conductive body is inserted between multiple conductive bodies, and a current flows between these multiple conductive bodies.

Moreover, all semiconductor devices, and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices, and the methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.