Method for fabricating a local interconnect in a semiconductor device

A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.

TECHNICAL FIELD

The disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a structure and a manufacturing method for a local interconnect connecting source/drain regions.

BACKGROUND

With a decrease of dimensions of semiconductor devices with a complex layout structure, a local interconnect that connects a source/drain region to another source/drain region has been developed. A local interconnect is a conductive layer disposed below the first metal wiring layer, and connects elements having a relatively short distance. In designing standard cells, local interconnects enhance design flexibility and minimize the size of the standard cells. It has been required to provide structures and manufacturing processes for a local interconnect for more design flexibility and higher reliability.

DETAILED DESCRIPTION

FIGS. 1A and 1B to 12show exemplary views illustrating a sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure. In these figures, some layers/features are omitted for simplification. It is understood that additional operations can be provided before, during, and after processes shown by these figures, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIGS. 1A and 1Bshow one of the stages of a sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure.FIG. 1Ashows a plan (top) view, andFIG. 1Bshows a cross sectional view along line X1-X1ofFIG. 1A.

As shown inFIGS. 1A and 1B, fin structures10N and10P, as active regions, separated by an isolation insulating region15, such as shallow trench isolation, are formed over a substrate (not shown). In this embodiment, the fin structure10N is for n-type fin field effect transistor transistors (Fin FETs) and the fin structure10P is for p-type Fin FETs. In other embodiments, both the fin structures10N and10P are for the same conductivity type Fin FETs.

The substrate is, for example, a p-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm−3. In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration in a range from about 1×1015cm−3to about 1×1018cm−3. Alternatively, the substrate may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on insulator) substrate.

The fin structures are formed by, for example, trench-etching the substrate.

The isolation insulating regions15includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. The isolation insulating layer may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and/or fluorine-doped silicate glass (FSG).

After forming the isolation insulating region over the fin structures, a planarization operation is performed so as to remove part of the isolation insulating region. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process. Then, the isolation insulating region is further removed (recessed) so that the upper regions of the fin structures are exposed.

A dummy layer20for dummy gate electrodes and a dummy insulating layer (not shown) are formed over the fin structures10N,10P and the isolation insulating regions15. InFIG. 1A, the dummy layer20is omitted (transparent). The dummy layer20is, for example, a poly-silicon layer formed by chemical vapor deposition (CVD). Hard mask patterns30are then formed over the dummy layer20. In one embodiment, a thickness of the dummy layer20is in a range from about 100 nm to about 35 nm, and a thickness of the hard mask patterns30is in a range from about 50 nm to about 200 nm.

The hard mask patterns30include one or more layers of dielectric material. One or more blanket layers of dielectric material are formed over the dummy layer20, and a patterning operation including lithography and dry etching is performed to obtain the hard mask patterns30. In one embodiment, the hard mask patterns30include a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer. In other embodiments, the silicon oxide layer is disposed on the silicon nitride layer.

Next, as shown inFIGS. 2A and 2B, some of the hard mask patterns30are divided into plural pieces, each corresponding to one dummy gate pattern.FIG. 2Ashows a plan (top) view, andFIG. 2Bshows a cross sectional view along line X1-X1ofFIG. 2A. InFIG. 2A, the dummy layer20is omitted (transparent).

By using the divided hard mask patterns30, the dummy layer20is patterned into dummy gate electrodes25, as shown inFIGS. 3A and 3B.FIG. 3Ashows a plan (top) view, andFIG. 3Bshows a cross sectional view along line X1-X1ofFIG. 3A. In other embodiments, the dummy layer is patterned and then the patterned dummy layers are divided into plural pieces. In such a case, however, the dividing the patterned dummy layers may require etching for high aspect ratio patterns.

Then, as shown inFIGS. 4A-4C, a blanket layer40for sidewall spacers is formed over the patterned dummy gate electrodes25with hard mask patterns30.FIG. 4Ashows a plan (top) view,FIG. 4Bshows a cross sectional view along line X1-X1ofFIG. 4A, andFIG. 4Cshows a cross sectional view along line X2-X2ofFIG. 4A.

The blanket layer40includes one or more layers of insulating material such as SiO2, SiN, SiCN, SiON, SiOCN, formed by low pressure CVD (LPCVD), plasma CVD or atomic layer deposition (ALD). As shown inFIGS. 4B and 4C, the blanket layer is comformally formed over the patterned dummy gate electrodes25with hard mask patterns30, the fin structures and the isolation insulating region15. In one embodiment, a nitride-based insulating material is used as the blanket layer40, having a thickness in a range from about 5 nm to about 10 nm.

Then, as shown inFIGS. 5A-5C, anisotropic etching is performed so as to form sidewall spacers45on both sidewalls of the patterned dummy gate electrodes25with hard mask patterns30.FIG. 5Ashows a plan (top) view,FIG. 5Bshows a cross sectional view along line X1-X1ofFIG. 5A, andFIG. 5Cshows a cross sectional view along line X2-X2ofFIG. 5A.

After the sidewall spacers are formed, source/drain regions50N,50P are formed, as shown inFIGS. 6A-6C.FIG. 6Ashows a plan (top) view,FIG. 6Bshows a cross sectional view along line X1-X1ofFIG. 6A, andFIG. 6Cshows a cross sectional view along line X2-X2ofFIG. 6A. In the present disclosure, a source and a drain are interchangeably used.

The fin structures not covered by the dummy gate electrodes are recessed below the upper surface of the isolation insulating region. Then, source/drain regions50N,50P are formed over the recessed fin structures by using an epitaxial growth method. The source/drain regions may include a strain material to apply stress to the channel regions. Examples of the strain material are SiC, SiP or SiCP for n-type Fin FET, and SiGe for p-type Fin FET when the fin structure is Si. In other embodiments, the source/drain regions are formed by ion implantation. A silicide layer formed by, for example, Ti, Ni, Ta, Co or W may be formed in the source/drain regions.

After the source/drain structures are formed, an insulating layer60is formed over the dummy gate structures. The insulating layer60includes one or more layers of insulating material. In this embodiment, silicon oxide or a silicon oxide-based insulating material is used. Then, a planarization operation, such as CMP, is performed to remove upper portions of the insulating layer60and the hard mask pattern30on the dummy gate electrodes25, as shown inFIGS. 7A-7C.FIG. 7Ashows a plan (top) view after the metal gate patterns are formed,FIG. 7Bshows a cross sectional view along line X1-X1ofFIG. 7A, andFIG. 7Cshows a cross sectional view along line X2-X2ofFIG. 7A. InFIG. 7A, the insulating layer60is omitted.

After the planarization operation, the dummy gate structures (dummy gate electrodes and dummy insulating layers) are removed so as to make gate spaces. Then, in the gate spaces, metal gate structures including metal gate electrodes70and gate dielectric layers (not shown), such as a high-k dielectric layer, are formed, as shown inFIGS. 8A-8C.FIG. 8Ashows a plan (top) view after the metal gate patterns are formed,FIG. 8Bshows a cross sectional view along line X1-X1ofFIG. 8A, andFIG. 8Cshows a cross sectional view along line X2-X2ofFIG. 8A. InFIG. 8A, the insulating layer60is omitted.

The metal gate electrode70includes one or more layers of metal material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, other conductive materials. The metal gate electrode70may be made by CVD, physical vapor deposition (PVD), ALD or electroplating. The gate dielectric layer (not shown) includes one or more layers of metal oxides such as a high-k metal oxide. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. The gate dielectric layer may be made by CVD, PVD or ALD. In some embodiments, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer and the metal gate electrodes70. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-type FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-type FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer.

Then, as shown inFIGS. 9A-9C, the metal gate electrodes70are recessed and cap insulating layers80are formed.FIG. 9Ashows a plan (top) view after the metal gate patterns are formed,FIG. 9Bshows a cross sectional view along line X1-X1ofFIG. 9A, andFIG. 9Cshows a cross sectional view along line X2-X2ofFIG. 9A. InFIG. 9A, the insulating layer60is omitted. The cap insulating layers80include one or more layers of insulating material, such as SiO2, SiN, SiON, SiCN or SiOCN. In this embodiment, SiN or a silicon nitride-based material is used as the cap insulating layer80. The cap insulating layers80are formed by depositing a blanket layer of insulating material by CVD and performing a planarization operation (e.g., CMP).

After the cap insulating layers80are formed, an opening65is formed in the insulating layer60, as shown inFIGS. 10A-10C.FIG. 10Ashows a plan (top) view after the metal gate patterns are formed,FIG. 10Bshows a cross sectional view along line X1-X1ofFIG. 10A, andFIG. 10Cshows a cross sectional view along line X2-X2ofFIG. 10A. InFIG. 10A, the insulating layer60is omitted, and the perimeter of the opening65is shown by broken lines.

By patterning the insulating layer60, a surface of at least a part of the source/drain regions50P and50N and a surface of a part of the isolation region are exposed in the opening65.

In this embodiment, the sidewall spacers45and the cap insulating layers80are made of a silicon nitride-based material (e.g., SiN), while the insulating layer60is made of a silicon-oxide-based material (e.g., SiO2). Accordingly, during the oxide etching of the insulating layer60, the source/drain regions50N,50P are exposed in a self-aligned manner without damaging the metal gate electrodes70. The upper surface of the isolation insulating region15may be etched during the oxide etching of the insulating layer60.

In the opening65, a conductive material is filled to form a local interconnect90, as shown inFIGS. 11A-11D.FIG. 11Ashows a plan (top) view after the metal gate patterns are formed,FIG. 11Bshows a cross sectional view along line X1-X1ofFIG. 11A,FIG. 11Cshows a cross sectional view along line X2-X2ofFIG. 11AandFIG. 11Dshows a cross sectional view along line Y1-Y1ofFIG. 11A. InFIG. 11A, the insulating layer60is omitted.

One or more layers of metal material, such as tungsten, titanium, cobalt and nickel, or silicide thereof, or other suitable materials, are formed over the structure ofFIGS. 10A-10C, and a planarization operation, such as CMP, is performed, so as to obtain the structure ofFIGS. 11A-11D. The opening65is filled by the metal material, thereby forming a local interconnect90connecting the source/drain region50N and the source/drain region50P.

As shown inFIGS. 11B-11D, the local interconnect90is in contact with the upper surface of the source/drain regions50N and50P and the upper surface of a part of the isolation region15. The local interconnect90is in contact with the sidewall spacers45, and upper surfaces of the cap insulating layers8, upper surfaces (top portion) of the sidewall spacers45and upper surfaces of the local interconnect90are substantially flush with each other, i.e., on the same plane. In this disclosure, when differences in heights of features are less than 10% of the highest feature, it is considered that the features are substantially flush with each other. In one embodiment, the height of the local interconnect90from the surface of the source/drain regions is in a range from about 60 nm to about 180 nm.

FIG. 11Ashows six Fin FETs TR1, TR2, TR3, TR4, TR5and TR6. The local interconnect90connects the source/drain regions of TR1, TR2, TR3and TR4. Further, a local metal layer95, which is fabricated at the same time as the local interconnect90, is formed on the shared source/drain region between Fin FETs TR3and TR5. Such a local metal layer95may reduce a contact resistance to the source/drain regions.

FIG. 12shows an exemplary cross sectional view of a semiconductor device according to one embodiment of the present disclosure.

After the local interconnect90is formed, a first interlayer dielectric (ILD) layer ILD1is formed over the structure ofFIGS. 11A-11D. Then, a patterning operation is performed to form via holes, and the via holes are filed with one or more conductive materials so as to form a first via plug V1. A first metal wiring M1is also formed over the first via plug V1. The first metal wiring M1and the first via plug V1can be formed by a dual damascene method. Some of the first via plus V1are connected to the local interconnect90. Further, a second ILD layer ILD2is formed over the first metal wiring M1. Then, a patterning operation is performed to form via holes, and the via holes are filed with one or more conductive materials so as to form a second via plug V2. A second metal wiring M2is also formed over the second via plug V2. The second metal wiring M2and the second via plug V1can be formed by a dual damascene method. The first and second ILD layers includes one or more layers of insulating material such as silicon oxide based material such as silicon dioxide (SiO2) and SiON.

FIG. 13A-13Cshow exemplary layout structures of a semiconductor device according to various aspects of the present disclosure. The various arrangements of local interconnects are possible within a standard cell. In one embodiment, the local interconnect extends linearly in parallel with a gate electrode, in a plan view. In other embodiments, the local interconnect has a crank handle shape, in a plan view.

InFIGS. 11A, 13B and 13C, ends of gate patterns faces with each other with a space between them, and the local interconnect passes through the space. The space may be located over the source/drain region, or may be located over the isolation region.

The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, since a local interconnect (and a local metal layer) is formed in a self-aligned manner, short circuits caused by process variation (e.g., alignment errors in a lithography operation) can be avoided. Further, design flexibility in designing standard cells can be enhanced.

According to one aspect of the present disclosure, a semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least one of the second source and the second drain and a surface of a part of the isolation region.

According to another aspect of the present disclosure, a semiconductor device includes source/drain regions extending in a first direction, an isolation region separating the source/drain regions, a first gate pattern extending in a first direction, a second gate pattern extending in the first direction, a third gate pattern extending in the first direction and aligned with the second gate pattern in the first direction, and a local interconnect. One end of the second gate pattern faces one end of the third pattern with a space between them. The local interconnect is in contact with at least one of a surface of the at least one of the source/drain regions and a surface of the isolation region. The local interconnect extends in a second direction crossing the first direction and passes through the space.

In accordance with yet another aspect of the present disclosure, in a method of manufacturing a semiconductor device, an isolation region is formed in a substrate. A first transistor structure and a second transistor structure are formed over the substrate. The first transistor structure includes a first gate, a first cap insulating layer disposed over the first gate, a first sidewall spacer disposed on side faces of the first gate and the first cap insulating layer, a first source and a first drain. The second transistor structure includes a second gate, a second cap insulating layer disposed over the second gate, a second sidewall spacer disposed on side faces of the second gate and the second cap insulating layer, a second source and a second drain. A first insulating layer is formed between the first and second transistor structures. An opening is formed in the first insulating layer so that a surface of at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region are exposed. The opening is filled with a conductive material so as to form a local interconnect.