Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter

In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.

BACKGOUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to analog-to-digital converters (ADCs). More particularly, the present invention relates to sub-ADCs and sub-DACs in a pipelined ADC architecture.

2. Description of the Related Art

Analog-to-digital converters (ADCs) are common electrical components used in a wide variety of applications, including wireless communications and the digital recording industry. ADCs take continuous analog signals and convert them to digital signals, or signals with discrete parts, so that the signals can be rendered, stored, or manipulated. For example, in typical wireless communication systems, a transmitter will transmit an analog signal that is converted into a digital signal for processing.

Pipelined ADCs have been widely used because they can provide high resolution at high speeds. In a pipelined ADC architecture, multiple identical stages are used to achieve a desired resolution. The multiple stages provide redundancy of components, and, as such, may take up excessive layout area.

Attempts to reduce power consumption by sharing operational amplifiers between stages have been employed to reduce layout area in low speed applications. In high speed applications, however, such techniques may actually increase the layout area as the lower settling time required for high speed applications may necessitate larger components and higher power. Thus, the sharing of operational amplifiers may increase the power consumption of the ADC as well as the layout area required when used in high speed applications.

DETAILED DESCRIPTION

An analog-to-digital converter (ADC) having a reduced layout area is described herein, as well as techniques for implementing the ADC. The layout area is reduced by providing for the sharing of components by sequential stages. The following description sets forth techniques and exemplary embodiments for implementing the ADC and corresponding figures provide block diagrams and timing diagrams illustrating and describing the shared sub-ADC and sub-DAC.

An exemplary pipelined ADC is illustrated inFIG. 1and generally designated by the reference number10. As illustrated, the pipelined ADC10may have multiple stages. The combined output of the various stages provides a digital output. The total number of stages included in an actual implementation may vary based on a variety of factors. Generally, more stages can provide higher resolution, or a digital signal with more bits. Some factors that may be considered in determining the number of stages include, for example, cost constraints, available layout area, and desired resolution.

The first stage12of the pipelined ADC10performs a coarse initial conversion of an analog signal14. The first stage12quantizes the analog signal14and provides a digital output16to a digital correction module18. The resolution of the digital output16provided to the digital correction module18may vary and may be determined based on desired operation parameters that may be application specific. For example, the digital output signal16may be a 2 bit signal or a 4 bit signal depending upon the desired operation parameters. Power consumption, for example, may be one consideration when determining per stage resolution in a pipelined architecture. Generally, the higher the resolution per stage, the higher the power consumption. Therefore, more power will be consumed in achieving a 4 bit resolution per stage than achieving a 2 bit resolution per stage.

A residual signal20is also output from the first stage12. The second stage22receives the residue signal20from the first stage12and performs the same procedure as performed by the first stage12. The residue signal20is an analog signal representing the difference between the analog signal14input to the first stage12and the digital signal16, as will be explained in greater detail below. The second stage22quantizes the residual signal20and provides digital bits19to the digital correction module18. Additionally, the second stage22provides a residual signal to a subsequent stage, where the procedure is repeated.

The digital correction module18combines the outputs of all of the stages of the pipelined ADC10and provides a digital output signal20. Because each stage performs a conversion at a different point in time, the digital correction module18aligns the various bits received from the various stages. For example, the digital correction module18may use shift registers to time-align the bits from the various stages. Additionally, the digital correction module18checks the bits received from the stages to make sure there are no errors. For example, the digital correction module18may employ error correction techniques to correct any possible errors from being output in a digitized signal23. Furthermore, the use of digital error correction by the digital correction module18reduces the accuracy requirements of the various stages.

A more detailed illustration of the first stage12is shown inFIG. 2. The analog signal14is shown entering a sample/hold (S/H) circuit24. The S/H circuit24samples the analog signal14and during a hold cycle, a sub-ADC26performs the quantization on the held analog signal14. The sub-ADC26then provides a digital output16to the digital correction module18(FIG. 1). A sub-DAC28receives the digital output16of the sub-ADC26. The sub-DAC28converts the output signal into an analog signal30which is provided to a summing circuit32. The summing circuit32subtracts the analog signal30from the held analog signal14. The difference signal34is provided to an amplifier36before being provided as the residue signal20to the second stage22(FIG. 1).

An exemplary timing diagram for the pipelined ADC10ofFIG. 1is illustrated inFIG. 3and is generally designated by the reference numeral40. The uppermost signal in the diagram40is a non-overlapping clock42. The middle signal44represents the state of the first stage12of the pipelined ADC10, and the lower signal46represents the state of the second stage22of the pipelined ADC10. As can be seen, the first stage12is in a sampling state while the second stage22is in an amplifying state. Specifically, during phase1, the first stage12is in a sampling state, and the second stage22is in an amplifying state. Alternatively, during phase2, the first stage12is in an amplifying state and the second stage22is in a sampling state.

Turning toFIGS. 4 and 5, the operation of the first and second stages12and22, respectively, are illustrated during amplifying and sampling states for each stage. Specifically,FIG. 4illustrates the first stage12during an amplifying state and the second stage22in a sampling state, whileFIG. 5illustrates the first stage12during a sampling state and the second stage22in an amplifying state.FIG. 4, therefore, illustrates Phase2of the timing diagram40ofFIG. 3, whileFIG. 5illustrates Phase1.

As can be seen, inFIGS. 4 and 5, the first stage12and second stage22, respectively, have identical components. Specifically, they each have a sub-ADC26, a sub-DAC28, and an amplifier36. The sub-ADC26has a first comparator50, and a second comparator52. For clarity, the components of the first stage12are designated by the corresponding reference numeral and an alphabetic character, “a” (e.g.,26a,28a,36a,50a,52a,etc.), while the components of the second stage22are designated by the corresponding reference numeral and an alphabetic character, “b” (e.g.,26b,28b,36b,50b,52b,etc.).

As illustrated inFIG. 5, both the first comparator50aand the second comparator52aof the first stage12receive a Vin signal during the sampling state. The Vin signal is the original analog signal14that is to be converted to a digital signal by the pipelined ADC10ofFIG. 1. Alternatively, as illustrated inFIG. 4, the first comparator50band the second comparator52bof the second stage22receive a residue signal20from the first stage during its sampling state. In addition to the Vin signal received by the first stage12and the residue signal20received by the second stage22, the first comparators50receive a +Vref signal (reference voltage) and the second comparators52receive a −Vref signal.

Additionally, a latch (not shown) may be provided in conjunction with the first comparators50and second comparators52. The latch may be a flip-flop configured to capture the output of the first comparators50and second comparators52on a rising edge of a latch signal such as Latch1or Latch2. The output of the latch is provided to the sub-DAC28. The output of the latch does not change until it again captures the output of the comparators50and52on the next rising edge of a latch signal. Thus, the output of the latch may differ from a signal received at the inputs of the sub-ADC26.

The sub-DAC28may be a 3:1 multiplexer which receives as inputs, a +Vref, a −Vref, and a ground or zero signal. The outputs of the sub-ADC26control the output of the sub-DAC28. Specifically, the sub-DAC28outputs a +Vref, a −Vref, or a zero signal according to the outputs received from the sub-ADC28. The output from the sub-DAC28defines a crow-bar level, as will be discussed in greater detail below.

The amplifier36may be coupled to capacitors in order to create a desired amplified output from the stage. In accordance with an exemplary embodiment illustrated inFIGS. 4 and 5, a first capacitor54and a second capacitor56may be coupled to the input of the amplifier36. The first capacitor54receives the output from the sub-DAC28during an amplifying state and receives Vin during a sampling state. The Vin may be the original analog signal, or an output from the immediately preceding stage, as previously described.

The second capacitor56may also alternate between configurations according to whether it is an amplifying state or a sampling state. During a sampling state, the second capacitor56may be in an electrically parallel configuration with regards to the first capacitor54. During an amplifying state, alternatively, the second capacitor may be coupled to the output of the amplifier36in order to provide a feedback loop. The alternating configurations of the second capacitor56may be seen inFIGS. 4 and 5, and will be described below.

Referring specifically toFIG. 4, the first stage12is illustrated in an amplifying state and the second stage22in a sampling state. During the sampling state of the second stage22, the output20of the first stage12is provided to the first capacitor54band the second capacitor56b.The first and second capacitors54band56bare charged by the output20of the first stage12, thus, the total charge sampled is two times the output20. Additionally, the output20is provided to the sub-ADC26bof the second stage22. During the sampling state, no signal from the amplifier36bis provided to a subsequent stage.

Concurrent with the sampling state of the second stage22, the first stage12is in an amplifying state, as illustrated in the timing diagram40ofFIG. 3. As will be appreciated, the capacitors54aand56awere charged by the Vin signal during a previous sampling state. During the amplifying state second capacitor56ais configured to provide a feedback factor for the amplifier36a.Assuming the capacitors34aand36ahave approximately the same value, the feedback value is 1/2 Vin and the output signal would be two times Vin if no other elements were present.

The sub-ADC26and the sub-DAC28, however, define a crow-bar level for the output of the first stage, during the amplifying state. The sub-DAC28which provides an output signal to the charged first capacitor54a.The output of the sub-DAC28depends upon the sampled signal. Specifically, the output signal of the sub-DAC28is a +Vref signal if the sampled Vin signal is greater than ¼ Vref, a −Vref if the sampled Vin signal is less than −¼ Vref, and a zero signal if the sampled Vin is less than ¼ Vref but greater than −¼ Vref. This output of the sub-DAC28ais negatively summed with the charge of the first and second capacitors54aand56a.

Accordingly, the output of the amplifier36ais equal to (2*Vin)−Vref if the Vin is greater than ¼ Vref, (2*Vin)+Vref if Vin is less than −¼ Vref, and is (2*Vin) when Vin is greater than ¼ Vref but less than −¼ Vref. Table 1 summarizes the possible Vin conditions, the output of the sub-DAC, and the crow-bar level.

Turning toFIG. 5, the first stage12is illustrated during a sampling state and the second stage22is shown in an amplifying state. As can be seen, the configuration of the first and second stages12and22is different from the configuration inFIG. 4. Specifically, the first stage12is coupled to the analog signal Vin, as explained earlier because this is the first stage12Vin represents the analog signal14. The comparators50aand52asample the Vin signal and the capacitors54aand56aare charged by the Vin signal. The sub-DAC28aand the amplifier36ado not provide output signals during the sampling state.

The second stage22operates in the amplifying state while the first stage12operates in the sampling state. The first capacitor54breceives an output signal from the sub-DAC28band the amplifier36bprovides an output to a subsequent stage (not shown). Each stage alternates operating in sampling and amplifying states according to the timing diagram40illustrated inFIG. 3.

In accordance with embodiments of the present invention, the components of the first stage12and the second stage22are shared as illustrated inFIGS. 6 and 7. Specifically, the sub-ADC26and the sub-DAC28are shared between the first stage amplifier36aand the second stage amplifier36bin order to reduce layout area of a pipelined ADC.

InFIG. 6, the first stage amplifier36ais shown in an amplifying state and the second stage amplifier36bis shown in a sampling state. As can be seen, the first capacitor54aof the first stage12is coupled to the output of the sub-DAC28, while the second capacitor56aprovides a feedback loop for the amplifier36a. Because the second stage amplifier36bis in a sampling state, a residual signal20from the output of amplifier36ais provided to the first and second capacitors54band56bof the second stage22.

Additionally, the residual signal20is provided to the sub-ADC26. A compare signal58triggers the comparators50and52to compare the output of the amplifier36ato the +Vref and the −Vref signals. As previously explained, a Latch signal may be provided to indicate an output of the comparators50and52should be “latched” or held. The sub-ADC26may be configured to latch a signal on a rising edge of the Latch signal. As such, the sub-ADC is able to provide a previously sampled output from the comparators50and52to the sub-DAC28while the comparators receive a different signal.

Referring toFIG. 7, the first stage amplifier36ais illustrated in a sampling state and the second stage amplifier36bis illustrated in an amplifying state. Accordingly, a Vin signal, such as analog signal14, is provided to the first and second capacitors54aand56a. Additionally, the Vin signal is provided to the sub-ADC26. The output from the sub-DAC28is provided to the second stage22. Specifically, the first capacitor54bof the second stage22receives the output of the sub-DAC28and the second capacitor56bprovides a feedback loop for the amplifier36b.The output of the amplifier36bis provided to a subsequent stage in the pipelined ADC.

An alternative illustration of the shared sub-ADC and sub-DAC in accordance with an exemplary embodiment of the present invention is shown inFIG. 8. As can be seen, the comparators38and40are configured to compare a Vin signal with +Vref and −Vref signals respectively. The outputs of the comparators50and52are provided to a latch60. The latch60may be a flip-flop configured to capture the outputs of the comparators50and52on a rising edge of the Latch signal, as described above. The output of the latch60is provided to the sub-DAC28. The sub-DAC28provides a +Vref, −Vref, or zero signal output, as previously described in greater detail, to provide a crow-bar level during an amplifying state. Switches Φ1and Φ2coupled to the output are controlled according to the timing diagram ofFIG. 9to provide the output from the sub-DAC to the proper stage.

Turning toFIG. 9, a timing diagram corresponding to the operation of the components ofFIG. 8is illustrate and generally designated by the reference numeral62. The timing diagram62illustrates a non-overlapping clock signal42, and signals which correspond to timing of the components and switches ofFIG. 8. The timing diagram62is provided for correspond to the implementation of a type II comparator. Alternative timing schemes may be necessary for alternative comparator types.

Signals Φ1and Φ2are provided to switch the output of the sub-DAC28from operating as the output of the first stage12to operating as the output of the second stage22. Additionally, the signals Φ1and Φ2control the timing of the latch60.

A Φ1pb signal and a Φ2pb signal are provided to control the reading in of Vin signals into the comparators50and52. In accordance with one embodiment of the present invention, the rising edge of the Φ1pb signal indicates to the comparators50and52to trigger for a second stage22. For example, at point70, the comparators50and52receive a Φ1pb signal to read in a signal, such as the residue signal from stage1, for stage2. The rising edge of the Φ2signal causes the latch to read in the output from the comparators50and52. Specifically, at point72, the latch60will capture the output from the comparators50and52. The Φ2pb signal indicates to the comparator to compare a Vin signal for stage1. For example, at point74, the comparators will being comparing the Vin for stage1. The rising edge of the Φ1signal indicates the sub-DAC will output a signal to the amplifier of stage1via switch Φ1ofFIG. 8. Specifically, at point76, the output of the sub-DAC is provided to the first stage12. Additionally, the rising edge of the Φ1signal indicates to the latch to read in the output of the comparators.

Referring toFIG. 10, a block diagram of a two-channel pipelined ADC is illustrated in accordance with an alternative embodiment of the present invention and is generally designated by the reference numeral80. As its name suggests, the two-channel pipelined ADC80has a dual channel configuration with two channels configured to operate simultaneously in parallel. Other alternative embodiments may utilize more channels, such as four channels, for example, configured to operate simultaneously.

The two-channel pipelined ADC80is configured to receive two signals, one for each channel. Specifically, a first signal82aand a second signal82bare sampled by the sample and hold circuits84aand84b.The sample and hold circuits84aand84bmay share components. Specifically, as shown inFIG. 10, the sample and hold circuits84aand84bmay share an amplifier86.

The signals82aand82bare provided from the sample and hold circuits84aand84bto the first stage of the first channel88aand first stage of the second channel88b, respectively. The first stage of the first channel88aand the first stage of the second channel88bmay share components as illustrated by block90. Specifically, the first stage of the first channel88aand the first stage of the second channel88bmay share sub-ADC components, sub-DAC components, and an amplifier. The sharing of an amplifier between the two channels reduces the requirement of the amplifier and therefore reduces the power consumed by the dual channel pipelined ADC80.

In alternative embodiments, an amplifier may be shared between channels, while sub-ADC and sub-DAC components are shared between adjacent stages within a channel. The operation of the shared components between channels is similar to the operation of the shared sub-ADC and sub-DAC described in detail above with reference toFIGS. 4-7. Specifically, the shared components will alternate sampling and processing the first signal82afor the first stage of the first channel88aand sampling and processing the second signal82bfor the first stage of the second channel88b.Subsequent stages of the two-channel pipelined ADC may be configured to operate in a similar manner.

A method and apparatus for an ADC having a reduced layout area has been described above. The layout area is reduced by sharing sub-ADC and sub-DAC components between two consecutive stages or between two stages in two channels. The layout area saved is realized to a greater extent in the pipelined ADC architecture, where multiple pairs of stages share components.

While embodiments of the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of these embodiments, as defined by the following appended claims.