MEMORY DEVICE AND MANUFACTURING THEREOF

Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. Although existing semiconductor devices and methods of fabricating semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. It is desired to have improvements in this area.

DETAILED DESCRIPTION

The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, GAA (Gate All Around) FETs, such as Horizontal Gate All Around (HGAA) FETs, and Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

Embodiments of the present disclosure relate to a SRAM (static random-access memory) bit cell. Particularly, embodiments of the present disclosure relate to a SRAM bit cell with back side power rail. The SRAM bit cell according to the present disclosure has a cell height in bit-line routing direction is equal to 4 times of the gate pitch. The SRAM bit cell are formed on two doped regions, or active regions. In some embodiments, bit-line, bit-line-bar and word-line conductors all located on the front-side of the transistors, and power rail, such as CVSs conductors, are located on a back side of the transistors. In some embodiments, bit-line and bit-line-bar conductors are located on different interconnect layers. In some embodiments, local interconnect features, such as gate contact features and source/drain contact features are located in a first interconnect layer on the front side, bit-line and bit-line-bar conductors are located in the third interconnect layer on the front side, and word-line conductors are located in second interconnect layer.

FIG.1is a simplified diagram of an integrated circuit10in accordance with some embodiments of the present disclosure. The integrated circuit10includes a memory circuit20and a logic circuit40. In some embodiments, the memory circuit20and logic circuit40include GAA transistors.

The memory circuit20may include one or more memory array30of multiple memory cells arranged in rows and columns. In some embodiments, the memory cells in the memory array30may have the same circuit configuration and the same semiconductor structure. In some embodiments, the logic circuit40may be the controller for accessing the memory circuit20. In some embodiments, the logic circuit40includes circuits configured to perform a specific function or operation according to data stored in the memory circuit20. The logic circuit40includes multiple logic cells50. In some embodiments, the logic cell50may be a standard cell (STD cell), e.g., inverter (INV), AND, OR, NAND, NOR, Flip-Flop, SCAN and so on. In some embodiments, the logic cells50corresponding to the same function or operation may have the same circuit configuration with different semiconductor structures for providing various threshold voltages (Vth or Vt). In some embodiments, the integrated circuit10may be a system on chip (SOC) circuit with embedded memory circuits.

FIG.2Aschematically illustrates the memory array30the embodiments of the present disclosure. In some embodiments, the memory array30is a “SRAM” array including a plurality of bit cells102. The bit cells102are arranged in a number, n, of rows and a number, m, of columns. Each bit cell102is coupled to a word line, WL (one of WL1to WVLN), that extends horizontally across the memory array30(i.e., in an x-direction) and two complementary bit-line BL (one of BL1to BLm) and complement bit-line-bar BLB (one of BLB1to BLBm) that extend vertically across the memory array30(i.e., in a y-direction).

FIG.2Bis a schematic diagram of the bit cell102according to embodiments of the present disclosure. The bit cell102is a six-transistor (“6T”) SRAM cell. Each bit cell102includes a latch108formed by a pair of cross coupled inverters110,112. The inverter110includes a PMOS (p-channel metal-oxide semiconductor) transistor114and a NMOS (n-channel metal-oxide semiconductor) transistor118. The PMOS transistor114includes a source coupled to the supply voltage Vcc at a node140, and a drain coupled to a node133. The node133is connected to a node116. The node116serves as the output of the inverter110. The NMOS transistor118of the inverter110has a source coupled to the ground Vss at a node138, and a drain coupled to the node133, which connected to the node116. Gates of the transistors114and118are coupled together at a node120. The node120serves as the input of the inverter110and the output of the inverter112. The inverter112includes a PMOS transistor122and a NMOS transistor124. The PMOS transistor122has a source coupled to VDD at a node140, a gate coupled to the node116, and a drain coupled to a node135. The node135is connected to the node120. The NMOS transistor124has a source coupled to the ground Vss at the node138, a drain coupled to the node135, which connected to the node120, and a gate coupled to the node116.

The bit cell102also includes a pair of pass transistors126,128. In some embodiments, the pass transistors126,128are NMOS transistors, although one skilled in the art will understand that the pass transistors126,128may be implemented as PMOS transistors. The pass transistor126has a gate coupled to the word line WL at a node130, a source coupled to the node133and the node116, and a drain coupled to the bit line BL at a node132. The transistor128has a gate coupled to the word line WL at a node134, a source coupled to the node135and the node120, and a drain coupled to the complementary bit line BLB at a node136.

In some embodiments, the transistors of the bit cell102may be GAA FETs, such as HGAA-FETs, VGAA FETs, and other suitable devices. Alternatively, the transistors of the bit cell102may be formed in any suitable transistors, such as bulk planar metal oxide field effect transistors (“MOSFETs”), bulk Fin-FETs having one or more fins or fingers, semiconductor on insulator (“SO1”) planar MOSFETs, SOI Fin-FETs having one or more fins or fingers, or combinations thereof. The gates of the transistors in the bit cell102may include a polysilicon (“poly”)/silicon oxynitride (“SiON”) structure, a high-k/metal gate structure, or combinations thereof. Examples of the semiconductor substrate include, but are not limited to, bulk silicon, silicon-phosphorus (“SiP”), silicon-germanium (“SiGe”), silicon-carbide (“SiC”), germanium (“Ge”), silicon-on-insulator silicon (“SOI-Si”), silicon-on-insulator germanium (“SO1-Ge”), or combinations thereof.

FIG.3is a schematic view of transistor layout of a SRAM bit cell102according to embodiments of the present disclosure. Legend inFIG.3schematically demonstrates various layers of semiconductor devices, such as the bit cell102. Particularly, the bit cell102may include a S/D layer, a contact layer CO over the S/D layer, and a gate overlapping and interweaving with the S/D layer and contact layer CO. The gate layer and the contact layer are connected to a front side interconnect structure by via layers V0 and Gv respectfully. The front side interconnect structure includes multiple dielectric layers of dielectric materials with alternate layers of conductive lines and vias embedded therein, for example conductive layers M1, M2, M3 and via layers V1, V2 are alternatively disposed. The front side interconnect structure may include additional conductive layers and via layers. In some embodiments, the bit cell102may include a back side interconnect structure connected to the S/D layer by a back side contact layer B_CO and a via layer B V0. The back side interconnect structure includes multiple dielectric layers of dielectric materials with alternate layers of conductive lines and vias embedded therein, for example conductive layers B_M1, B_M2 and a via layer B_V1 are alternatively disposed. In some embodiments, the bit cell102include bit line conductors and word line conductors in the front side interconnect structure and power rail in the back side interconnect structure.

As shown inFIG.3, the bit cell102is formed within the cell boundary102cbhaving a cell height102hthat extends in the y-direction, or the first direction, and a cell width102wthat extends in the x-direction, or the second direction. As discussed above, the transistors of the bit cell102are formed over two doped regions226N,226P of a semiconductor substrate with four parallel gate structures230a,230b,230c,230dacross the two doped regions226,226P. The dope regions226N,226P are positioned side by side and extend along the first direction. Two fin structures228a,220brespectfully are formed in the doped regions226N,226P along the first direction. The gate structures230a,230b,230c,230dare formed along the second direction across the fin structures228a,220b. In some embodiments, the gate structures230a,230b,230c,230dare equally disposed across the bit cell102and along the second direction at a gate pitch Gp. In some embodiments, the cell height102his four times the gate pitch Gp. In some embodiments, a ratio of the cell width102wover the cell height102his in a range between about 0.4 and 1.2. In some embodiments, a ratio of the cell width102wover the cell height102his in a range between about 0.4 and 1.0.

The transistors114,118,122,124,126, and128of the bit cell102are formed over the doped regions226P,226N. The fin structures228a,228bare formed along the y-direction. The gate structures230a,230b,230c,230dare formed along the x-direction over the fin structures228a,228b. In some embodiments, each of the fin structures228a,228bincludes two or more nano-sheet semiconductor channels. During fabrication, portions of the fin structures228a,228bnot covered by the gate structures230a,230b,230c,230dare etched back, and epitaxial source/drain structures are then formed on both sides of the gate structures230a,230b,230c,230dto form the transistors114,118,122,124,126, and128.

The fin structure228bis formed over the doped region228P respectively. The fin structures228bmay have a width w1along the x-direction. The fin structure228ais formed over the n-well226n. The fin structure228amay have a width w2along the x-direction. In some embodiments, the width w1is greater than the width w2. In some embodiments, in an array of bit cells102, the fin structure228bis formed continuously along the y-direction, and the fin structure228ais formed in sections in each bit cell102. The gate structures230b,230care formed in a middle portion of the bit cell102across both the fin structures228a,228b. The gate structures230a,230dare formed above and below the gate structures230b,230c. The gate structures230a,230dcross the fin structure220b. In some embodiments, the gate structures230a,230cterminate at a position between the fin structures228aand228b. In some embodiments, the gate structures239a,230dinclude dummy portions covering ends of the fin structure228a.

The pull-down transistors118,124and the pass transistors126,128are n-type transistors formed over the doped region226P. The pull-up transistors114and122are p-type transistors formed over the doped region226N. The pull-down transistor118and the pull-up transistor114share the same gate structures238c. The pull-down transistor124and the pull-up transistor122share the same gate structures238b.

Source/drain contact features114d,118d,122d,124s,124d,126s,126d,128s,128dare formed over on epitaxial source/drain features of the transistors114,118,122,124,126,128in the contact layer CO. In some embodiments, the source/drain contact features126s,118d,114dare connected to one another, and the source/drain contact features122d,124d,128sare connected together. The nodes116,120,130,134may be implemented in form of gate contacts in the gate via layer GV. In some embodiments, source/drain contact feature114s/122s,118s/124sare formed under the epitaxial source/drain features of the transistors114,122,118,124. The nodes140,138may be implemented in form of contact vias in the back side contact layer B_CO or the back side via layer B V0. The nodes130,134.

As discussed above, the bit cell102according to the present disclosure includes both a front side interconnect structure and a back side interconnect structure. In some embodiments, the back side interconnect structure includes a power rail, and the front side interconnect structure includes bit line, bit line bar, and word line.FIGS.4A-4Dschematically demonstrate an interconnect layout400according to embodiments of the present disclosure.FIG.4Ais a schematic front side interconnect layout for the SRAM bit cell102according to the present disclosure.FIG.4Bis a schematic back side interconnect layout for the SRAM bit cell102according to the present disclosure.FIG.4Cis a schematic word line layout for two SRAM bit cells according to the present disclosure.FIG.4Dis a schematic interconnect layout for two SRAM bit cells according to the present disclosure.

FIG.4Aschematically demonstrates the conductive layers M1, M2 of the front side interconnect structure of the bit cell102. Bit line and bit line bar are formed in the first conductive layer M1, i.e. the lowest level of conductive layer. And the word line is formed in the second conductive layer M2. The first conductive layer M1 is formed immediately above the gate via layer GV and the via layer V0. The first conductive layer M1 include a conductive line M1_BL and a conductive line M1_BLB extend along the first direction. The conductive line M1_BL is connected to the node132in the via layer V0 and function as the bit line of the bit cell102. The conductive line M1_BLB is connected to the node136in the via layer V0 and functions as the bit line bar of the bit cell102. The conductors M1_BL and M1_BLB extend the cell height102hof the bit cell102.

The first conductive layer M1 further includes conductors M1 L1and M1 L2positioned to connect the nodes116and135, and the nodes120and133respectively. The conductors M1_L1 and M1_1_2 are positioned parallel to the conductors M1_BL and M1_BLB.

The first conductive layer M1 further include a conductive line M1_WL, which is connected to the nodes130,134in the gate via layer GV. The conductive line M1_WL functions word line landing to connect the word line in the upper conductive layer. In some embodiments, the conductive line M1_WL is formed on the cell boundary102cband shared with the neighboring bit cell.

The via layer V1 is formed over the first conductive layer M1. In some embodiments, a conductive via V1_WL is formed in the via layer V1 and in contact with the conductive line M1_WL. The conductive layer M2 is formed over the via layer V1. The conductive layer M2 includes a conductive line M2_WL1and a conductive line M2_WL2. The conductive line M2_WL1and conductive line M2_WL2 are parallel to each other and extend along the first direction. The conductive line M2_WL1is in electrical connection with the conductive via V1_WL and conductive line M1_WL and functions as the word line for the bit cell102. The conductive line M2_WL2 is configured to function as the word line for the bit cells on both sides of the bit cell102along the x-direction.FIG.4Cschematically demonstrates the word line arrangement of the bit cell102and a bit cell102MY. The bit cell102MY is disposed to the left of the bit cell102and is a mirror image of the bit cell102about the Y-axis. As shown inFIG.4C, the conductive line M2_WL1is the word line of the bit cell102and the conductive line M2_WL2 is the word line of the bit cell102MY.

FIG.4Bschematically demonstrates arrangement of a via layer B_V0, a conductive layer B_M1, via layer B_V1, and a conductive layer B_M2 of the back side interconnect structure of the bit cell102. As discussed inFIG.3, the nodes138,140are connected to the source/drain contact features from the back. InFIG.4B, the nodes138,140are implemented in the form of conductive vias BV0_Vss and BV0_Vdd in the back side via layer B_V0. The conductive layer B_M1 is formed next to the via layer B_V0.

The conductive layer B_M1 includes a conductive line BM1_Vss and a conductive line BM1 Vdd extend along the first direction. The conductive line BM1_Vss is connected to the node138/BV0_Vss in the via layer B_V0 and functions a conductive routing line to connect the pull-down transistors118,124to the ground. The conductive line BM1 Vdd is connected to the node140/BV0_Vdd in the via layer V0 and functions as a routing line to connect the pull-up transistors114,122to the supply voltage Vcc. The conductive line BM1_Vss and BM1_Vdd extend the cell height102hof the bit cell102.

The via layer B_V1 is formed under the conductive layer B_M1. In some embodiments, a conductive via BV1_Vss is formed in the via layer B_V1 and in contact with the conductive line BM1_Vss. The conductive layer B_M2 is formed under the via layer B_V1. The conductive layer B_M2 includes a conductive line BM2_Vss. The conductive line BM_Vss extends along the second direction across the bit cell102. The conductive line BM2_Vss, the conductive via BV1_Vss, and the conductive line BM1_Vss form a power mesh connecting the pull-down transistors118,124to the ground.

In some embodiments, the bit cell102are arranged in an array with neighboring bit cells arranged in pairs. The two bit cells102in each pair are mirror images of each other, as shown inFIG.4D.

FIGS.5A-5Bschematically demonstrate an interconnect layout500according to another embodiment of the present disclosure.FIG.5Ais a schematic front side layout of the interconnect layout500.FIG.5Bis a schematic back side layout of the interconnect layout500. The interconnect layout500inFIGS.5A-5Bis similar to the layout400inFIGS.4A-4Dexcept the layout500includes a back side contact layer B_CO disposed between the S/D layer and the via layer B_V0. In some embodiments, conductive lines BCO_Vss and BCO_Vdd. In some embodiments, the conductive lines BCO_Vss and BCO_Vdd extend along the second direction. The conductive lines BCO_Vss and BCO_Vdd allow the conductive vias BV0_Vss and BV0_Vdd to be disposed at desirable locations in the x-direction. As shown inFIG.5B, the conductive lines BCO_Vss and BCO_Vdd allow the conductive lines BM1_Vss and BM1 Vdd to be further apart or evenly distributed.

FIGS.6A-6Cschematically demonstrate an interconnect layout600according to embodiments of the present disclosure.FIG.6Ais a schematic front side layout of the interconnect layout600according to the present disclosure.FIG.6Bis a schematic back side layout of the interconnect layout600.FIG.6Cis a schematic word line layout of the interconnect layout600. The interconnect layout600is similar to the interconnect layout400except that the bit line conductor and the bit line bar conductor are positioned in different conductor layers. In some embodiments, the bit line and bit line bar are disposed in conductive layers above and below the word line conductors. In some embodiments, one of the bit line and bit line bar is disposed in the first conductive layers. For example, the bit line bar is positioned in the conductive layer M1 and the bit line is positioned in the conductive layer M3, while the word line conductors are disposed in the conductive layer M2. Alternatively, the bit line is positioned in the conductive layer M1 and the bit line bar is positioned in the conductive layer M3.

FIG.6Aschematically demonstrates the conductive layers M1, M2, M3 of the front side interconnect structure of the bit cell102. The first conductive layer M1 include a conductive line section M1_BL and a conductive line M1_BLB. The conductive line M1_BL is contact with the node132in the via layer V0. The conductive line M1_BL is a line section serving as bit line landing in the conductive layer M1. The conductive line M1_BLB is connected to the node136in the via layer V0. The conductive line M1_BLB extends across the bit cell102along the first direction and functions as the bit line bar for the bit cell102. In some embodiments, the conductive line M1_BLB in the layout600is wider than the conductive line M1_BLB in the layout400.

The first conductive layer M1 further includes conductive lines M1_L1 and M1 L2 positioned to connect the nodes116and135, and the nodes120and133respectively. The conductors M1_L1 and M1_L2 are positioned parallel to the conductive lines M1_BL and M1_BLB. In some embodiments, the conductive lines M1 L2 and M1_BL is positioned is aligned with each other. The first conductive layer M1 further include a conductive line M1_WL, which is connected to the nodes130,134in the gate via layer GV. The conductive line M1_WL functions word line landing to connect the word line in the upper conductive layer. In some embodiments, the conductive line M1_WL is formed on the cell boundary102cband shared with the neighboring bit cell.

The via layer V1 is formed over the first conductive layer M1. In some embodiments, a conductive via V1_WL is formed in the via layer V1 and in contact with the conductive line M1_WL. The conductive layer M2 is formed over the via layer V1. The conductive layer M2 includes a conductive line M2_WL1and a conductive line M2_WL2. The conductive line M2_WL1and conductive line M2_WL2 are parallel to each other and extend along the first direction. The conductive line M2_WL1is in electrical connection with the conductive via V1_WL and conductive line M1_WL and functions as the word line for the bit cell102. The conductive line M2_WL2 is configured to function as the word line for the bit cells on both sides of the bit cell102along the x-direction.

In some embodiments, a conductive via V1_BL is formed in the via layer V1 and in contact with the conductive line M1_BL. The conductive layer M2 includes a conductive line M2_BL. The conductive line M2_BL is connected to the conductive via V1_ BL. The conductive line M2_BL may be line section extending along the second direction, or parallel to the word lines M2_WL1and M2_WL2.

The via layer V2 is formed over the second conductive layer M2. In some embodiments, a conductive via V2_BL is formed in the via layer V2 and in contact with the conductive line M2_BL. The conductive layer M3 is formed over the via layer V2. The conductive layer M3 includes a conductive line M3_BL. The conductive line M3_BL extends across the bit cell102along the first direction, or parallel to the conductive line M1_BLB. The conductive line M3_BL functions as the bit line for the bit cell102.

FIG.6Bschematically demonstrates arrangement of a via layer B_V0, a conductive layer B_M1, via layer B_V1, and a conductive layer B_M2 of the back side interconnect structure of the bit cell102. The back side interconnect structure for the layout600is similar to that of the layout400. The conductive layer B_M1 includes a conductive line BM1_Vss and a conductive line BM1_Vdd extend along the first direction. The conductive line BM1 Vdd is connected to the node140/BV0_Vdd in the via layer V0 and functions as a routing line to connect the pull-up transistors114,122to the supply voltage Vcc. A conductive via BV1_Vss is formed in the via layer B_V1 and in contact with the conductive line BM1_Vss. The conductive layer B_M2 includes a conductive line BM2_Vss. The conductive line BM2_Vss extends along the second direction across the bit cell102. The conductive line BM2_Vss, the conductive via BV1_Vss, and the conductive line BM1_Vss form a power mesh connecting the pull-down transistors118,124to the ground.

FIG.6Cschematically demonstrates the word line arrangement of the bit cell102and a bit cell102MY. The bit cell102MY is disposed to the left of the bit cell102and is a mirror image of the bit cell102about the Y-axis. As shown inFIG.6C, the conductive line M2_WL1is the word line of the bit cell102and the conductive line M2_WL2 is the word line of the bit cell102MY.

FIG.7Ais a schematic front side layout of the interconnect layout700for the SRAM bit cell according to the present disclosure.FIG.7Bis a schematic back side layout of the interconnect layout700. The interconnect layout700is similar to the layout600inFIGS.6A-6Cexcept the layout600includes a continuous fin structure228a′ over the doped region226N. The bit cell102includes dummy gate structures230ad,230ddformed over the fin structure228a′ to electrically isolate source/drain features on opposite sides of the dummy gate structures230ad,230dd.

FIGS.8A-8Cschematically demonstrate an interconnect layout800according to embodiments of the present disclosure.FIG.8Ais a schematic front side layout of the interconnect layout800according to the present disclosure.FIG.8Bis a schematic back side layout of the interconnect layout800.FIG.8Cis a schematic bit line and word line layout of the interconnect layout800. The interconnect layout800is similar to the interconnect layout600except that both the bit line conductor and the bit line bar conductor disposed above the word line.

FIG.8Aschematically demonstrates the conductive layers M1, M2, M3 of the front side interconnect structure of the bit cell102. The first conductive layer M1 include conductive line sections M1_BL and M1_BLB. The conductive line M1_BL is contact with the node132in the via layer V0. The conductive line M1_BL is a line section serving as bit line landing in the conductive layer M1. The conductive line M1_BLB is contact with the node136in the via layer V0.

The first conductive layer M1 further includes conductive lines M1_L1 and M1 L2 positioned to connect the nodes116and135, and the nodes120and133respectively. The conductors M1_L1 and M1_L2 are positioned in line with the conductive lines M1_BL and M1_BLB respectively. The first conductive layer M1 further includes a conductive line M1_WL, which is connected to the nodes130,134in the gate via layer GV. The conductive line M1_WL functions word line landing to connect the word line in the upper conductive layer. In some embodiments, the conductive line M1_WL is formed on the cell boundary102cband shared with the neighboring bit cell.

The via layer V1 is formed over the first conductive layer M1. In some embodiments, a conductive via V1_WL1is formed in the via layer V1 and in contact with the conductive line M1_WL1. The conductive layer M2 is formed over the via layer V1. The conductive layer M2 includes a conductive line M2_WL1and a conductive line M2_WL2. The conductive line M2_WL1and conductive line M2_WL2 are parallel to each other and extend along the first direction. The conductive line M2_WL1is in electrical connection with the conductive via V1_WL and conductive line M1_WL and functions as the word line for the bit cell102. The conductive line M2_WL2 is configured to function as the word line for the bit cells on both sides of the bit cell102along the x-direction.

In some embodiments, conductive vias V1_BL, V1_BLB are formed in the via layer V1 and in contact with the conductive line M1_BL, M1_BLB respectively. The conductive layer M2 includes conductive line sections M2_BL, M2_BLB. The conductive line sections M2_BL, M2_BLB is connected to the conductive via V1_BL, V1_BLB respectively. The conductive line sections M2_BL, M2_BLB may be line sections extending along the second direction, or parallel to the word lines M2_WL1and M2_WL2.

The via layer V2 is formed over the second conductive layer M2. In some embodiments, conductive vias V2_BL, V2_BLB are formed in the via layer V2 and in contact with the conductive line sections M2_BL, M2_BLB respectively. The conductive layer M3 is formed over the via layer V2. The conductive layer M3 includes conductive lines M3_BL, M3_BLB. The conductive lines M3_BL, M3_BLB extend across the bit cell102along the first direction, and function as the bit line, bit line bar for the bit cell102, respectively. By moving the bit line and bit line bar away from the first conductive layer M1, the feature density of the first conductive layer M1 may be reduced, and the widths of the bit line and bit line bar may be increased.

FIG.8Bschematically demonstrates arrangement of a via layer B_V0, a conductive layer B_M1, via layer B_V1, and a conductive layer B_M2 of the back side interconnect structure of the bit cell102. The back side interconnect structure for the layout800is similar to that of the layout600. The conductive layer B_M1 includes a conductive line BM1_Vss and a conductive line BM1 Vdd extend along the first direction. The conductive line BM1 Vdd is connected to the node140/BV0_Vdd in the via layer V0 and functions as a routing line to connect the pull-up transistors114,122to the supply voltage Vcc. A conductive via BV1_Vss is formed in the via layer B_V1 and in contact with the conductive line BM1_Vss. The conductive layer B_M2 includes a conductive line BM2_Vss. The conductive line BM2_Vss extends along the second direction across the bit cell102. The conductive line BM2_Vss, the conductive via BV1_Vss, and the conductive line BM1_Vss form a power mesh connecting the pull-down transistors118,124to the ground.

FIG.8Cschematically demonstrates the word line arrangement of the bit cell102and a bit cell102MY. The bit cell102MY is disposed to the left of the bit cell102and is a mirror image of the bit cell102about the Y-axis. As shown inFIG.8C, the conductive line M2_WL1is the word line of the bit cell102and the conductive line M2_WL2 is the word line of the bit cell102MY.

FIG.9Ais a schematic front side layout of the interconnect layout900for the SRAM bit cell according to the present disclosure.FIG.9Bis a schematic back side layout of the interconnect layout900. The interconnect layout900is similar to the layout800inFIGS.8A-8Cexcept the layout900includes a continuous fin structure228a′ over the doped region226N. The bit cell102includes dummy gate structures230ad,230ddformed over the fin structure228a′ to electrically isolate source/drain features on opposite sides of the dummy gate structures230ad,230dd. The interconnect layout900further includes a front side source/drain contact feature114s/122sformed in the front side contact layer CO. The source/drain contact feature114s/122smay extends along the second direction towards the cell boundary. A contact via V0_Vdd is formed in the via layer V0 and in connection with the source/drain contact feature114s/122s. A conductive line M1 Vdd is formed in the conductive layer M1 and in connection with the contact via V0_Vdd. The conductive line M1_Vdd functions as a second power mesh connecting the pull up transistors114,122to the supply voltage Vcc. In some embodiments, the conductive line M1_Vdd and the contact via V0_Vdd are formed along the cell boundary102cband are shared by two neighboring bit cells. In some embodiments, gate contacts230ga,230gdare formed between the dummy gate structures230da,230ddand the conducive line M1_Vdd so that the dummy gates230da,230ddare tied to the supply voltage Vcc.

FIG.10is a block diagram of a cell array1000of the SRAM bit cells according to the present disclosure. The cell array1000may be connected to a word line decoder1004, and a multiplexer and write driver1006. The word line decoder1004and the multiplexer and write driver1006are periphery circuit to the memory cell array1000and configured to facilitate read and write operation to each bit cell102in the memory cell array1000. In some embodiments, the word line decoder1004, the multiplexer and write driver1006may be logic circuit or devices including components such as inverters, NAND gates, NOR gates, flip-flops, or combinations thereof.

The memory cell array1000includes an array of bit cells, such as the bit cell102described above. The memory cell array1000may include m rows by n columns of the bit cells, where m is an integer corresponding to the number of rows and n is an integer corresponding to the number of columns. InFIG.10, the cell array1000is a 32-bit cell arranged in 4 rows R1, R2, R3, R4 and 8 columns C1-C8.

The bit cells102in each column Cn (n is from 1 to 8) share one bit line BL-n, one bit line bar BLB-n. Each row Rm (m is from 1 to 4) has two word lines WL_2m-1, WL_2m. Eight bit cells in two adjacent rows and four adjacent columns form a unit. The eight bit cells in the unit are arranged in a mirror symmetric manner as shown inFIG.10. In the 32-bit arrangement, each word line WL extends across eight columns the bit cells102, but is connected to four bit cells in the row. Each bit line and bit line bar extend across four bit cells and is connected to four bit cells.

FIG.11is a partial layout of a cell array1100of SRAM bit cells according to the present disclosure. The cell array1100may be connected to a word line decoder1104, and a multiplexer and write driver1106. The memory cell array1100includes an array of bit cells, such as the bit cell102described above. The memory cell array1100may include m rows by n columns of the bit cells. Every two columns form a group. The two columns in each group are mirror images of each other about the central line. Neighboring groups are mirror images of each other.FIG.11schematically demonstrates Group N, Group N+1, Group N+2, Group N+3 in Row M, Row M+1, Row M+2, Row M+3. Nodes1108are bit line/bit line bar landing in the bit cell. Nodes1110are word line landing in the bit cell. In each unit of 32-bit cells, the word line, bit line, and bit line bar each carry 4 bit cells, resulting in faster reading and writing as compared to the conventional 32 bit cells where each bit line and bit line bar carries 8 bit cells.

Various embodiments or examples described herein offer multiple advantages over the state-of-art technology. The bit cell structure according to the present disclosure use two fin structures, instead of four, to enable further cell scaling. All N-type MOSFETs (PG/PD) are forming upon same doped region providing fully symmetry devices layout for cell stability improvement. Positioning power mesh Move Vss and/or Vdd conductors to the back-side reduces the routing loading as well as cell size further reduction. The reduced conductive lines in a given area also benefits the conductor RC performance, by lowering resistance with wider conductor, lowering Capacitance with larger spacing, or both. Embodiments of the present disclosure uses two horizontal (WL routing direction) adjacent cells grouped together to mimic two rows in one column design for bit-line RC reduction. Some embodiments place bit-line and bit-line-bar on different metal layers to achieve both low resistance and low capacitance requirements. Some embodiments place the bit-line and bit-line bar to a higher-level conductive layer for resistance reduction. Embodiments of the present disclosure also provide a more robustness power mesh in SRAM cell region by using a back side power mesh.

Some embodiments of the present provide a memory cell comprising a device layer comprising: first and second fin structures extending along a first direction; first, second, third, and fourth gate structures extending along a second direction, wherein the second direction is substantially perpendicular to the first direction; a front side interconnect structure disposed above the device layer, wherein the front side interconnect structure includes: a bit line extending along the first direction; a bit line bar extending along the first direction; and a first word line extending the second direction; a back side interconnect structure includes: a voltage supply line; and a ground line.

Some embodiments of the present disclosure provide a SRAM (static random-access memory) bit cell, comprising a first doped region having a first pull-up transistor and a second pull-up transistor formed thereon; a second doped region having a first pass transistor, a second pass transistor, a first pull down transistor, and a second pull down transistor, wherein the first pass transistor, the first pull down transistor, the second pull down transistor and the second pass transistor are linearly arranged in the second doped region; a first front side conductive layer having a bit line bar conductor formed therein; a second front side conductive layer having a word line conductor formed therein; a first back side conductive layer having a supply voltage line formed therein; and a second back side conductive layer having a ground line formed therein.

Some embodiments of the present disclosure provide an integrated circuit chip, comprising: an array of memory bit cells arranged in columns and rows, wherein each memory bit cell comprises: first and second fin structures along a first direction; and first, second, third, and fourth gate structures parallelly arranged along a second direction, wherein the second direction is substantially perpendicular to the first direction; a bit line conductor disposed along the first direction; a bit line bar conductor disposed along the first direction; a first word line along the second direction; a second word line along the second direction, wherein the first word line is electrically connected to the bit cell, and the second word line is connected to the adjacent bit cell in the same row; a supply voltage line; and a ground line.