Three dimensional nonvolatile memory device including channel structure and resistance change memory layer

A nonvolatile memory device includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2019-0111073, filed on Sep. 6, 2019, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to a nonvolatile memory device and, more particularly, to a nonvolatile memory device having a resistance change memory layer.

2. Related Art

As the design rule decreases and the degree of integration increases, research has continued on the structures of semiconductor devices that can guarantee both structural stability and operational reliability. Currently, as a charge storage structure, a nonvolatile memory device, such as a flash memory that employs a three-layer stacked structure including a charge tunneling layer, a charge trap layer, and a charge barrier layer, has been widely utilized.

Recently, various nonvolatile memory devices having different structures from existing flash memories have been proposed. An example of a nonvolatile memory device is a resistance change memory device. While a flash memory implements a memory function through charge storage, recently in other configurations, predetermined signal information can be written by varying resistance in a memory layer between a high resistance and a low resistance, and storing the changed resistance in a nonvolatile manner.

SUMMARY

A nonvolatile memory device according to an aspect includes a substrate, and a source electrode structure disposed on the substrate. The source electrode structure includes a plurality of source electrode layer patterns and a plurality of source insulation layer patterns that are alternately stacked in a first direction perpendicular to the substrate, and the source electrode structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a channel structure disposed on the substrate and disposed to contact a sidewall surface of the source electrode structure. Here, the sidewall surface of the source electrode structure is a plane formed by the first and second directions. In addition, the nonvolatile memory device includes a resistance change memory layer disposed on a sidewall surface of the channel structure on the substrate. Here, the sidewall surface of the channel structure is a plane formed by the first and second directions. The nonvolatile memory device includes a drain electrode structure disposed to contact the resistance change memory layer on the substrate. The drain electrode structure includes a plurality of drain electrode layer patterns and a plurality of drain insulation layer patterns that are alternately disposed in the first direction, and the drain electrode structure extends in the second direction. The nonvolatile memory device includes a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other along the second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the gate dielectric structure.

A nonvolatile memory device according to another aspect includes a substrate, and a global source line disposed on the substrate. The global source line includes a plurality of source electrode layer patterns spaced apart from each other in a first direction perpendicular to the substrate, and the plurality of source electrode layer patterns extend in a second direction perpendicular to the first direction. The nonvolatile memory device includes a channel structure disposed on the substrate to contact the global source line in a third direction perpendicular to the first and second directions, and a resistance change memory layer disposed to contact a sidewall surface of the channel structure in the third direction. The nonvolatile memory device includes a global drain line disposed to contact the resistance change memory layer in the third direction on the substrate. The global drain line includes a plurality of drain electrode layer patterns disposed to be spaced apart from each other in the first direction, and the plurality of drain electrode layer patterns extend in the second direction. The nonvolatile memory device includes a plurality of gate dielectric structures extending in the first direction in the channel structure and disposed to be spaced apart from each other in the second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the gate dielectric structures. The channel structure is separated from one of the plurality of gate electrode structures by one of the plurality of the gate dielectric structures.

DETAILED DESCRIPTION

Various embodiments will now be described hereinafter with reference to the accompanying drawings. In the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. As a whole, the drawings are described from an observer's viewpoint. If an element is referred to be located “on” or “under” another element, it may be understood that the element is directly located “on” or “under” the other element, or an additional element may be interposed between the element and the other element. The same reference numerals in the drawings refer to substantially the same elements as each other.

The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to the ordinary skill in the art to which the embodiments belong. If expressly defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise” or “have” are intended to specify the presence of a feature, a number, a step, an operation, an element, a component, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, elements, components, parts, or combinations thereof.

Herein, the x-direction means a direction parallel to the x-axis in the x-y-z coordinate system. Similarly, the y-direction means a direction parallel to the y-axis in the x-y-z coordinate system, and the z-direction means a direction parallel to the z-axis in the x-y-z coordinate system.

FIG. 1is a perspective view schematically illustrating a nonvolatile memory device according to an embodiment of the present disclosure.FIG. 2is a plan view of the nonvolatile memory device ofFIG. 1.FIG. 3is a cross-sectional view taken along the line A-A′ of the nonvolatile memory device ofFIG. 1.

Referring toFIGS. 1 to 3, a nonvolatile memory device1may include a substrate101, first and second source electrode structures12and16, first and second channel structures22and24, first to eighth gate dielectric structures32a,32b,32c,32d,34a,34b,34c, and34d, first to eighth gate electrode structures42a,42b,42c,42d,44a,44b,44c, and44d, first and second resistance change memory layers310and320, and a drain electrode structure14. In an embodiment, the first and second source electrode structures12and16, the first and second channel structures22and24, the first and second resistance change memory layers310and320, and the drain electrode structure14may be sequentially disposed on the substrate101in an x-direction, and may extend in a y-direction, as illustrated inFIG. 1. InFIGS. 1 to 3, although four gate dielectric structures32a,32b,32c, and32dand four gate electrode structures42a,42b,42c, and42dare arranged in the first channel structure22in the y-direction, the number of gate dielectric structures and gate electrode structures are not necessarily limited to four, and other various numbers are possible. Similarly, although four gate dielectric structures34a,34b,34c, and34dand four gate electrode structures44a,44b,44c, and44dare arranged in the second channel structure24in the y-direction, the number of gate dielectric structures and gate electrode structures are not necessarily limited to four, but other various numbers are possible.

The substrate101may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The substrate101may be doped with an n-type or a p-type dopant. For example, the substrate101may include a well region doped with an n-type or a p-type dopant.

A base insulation layer110may be disposed on the substrate101. The base insulation layer110may electrically insulate the first and second source electrode structures12and16; the first and second channel structures22and24; the first to eighth gate dielectric structures32a,32b,32c,32d,34a,34b,34c, and34d; the first to eighth gate electrode structures42a,42b,42c,42d,44a,44b,44c, and44d; the first and second resistance change memory layers310and320; and the drain electrode structure14, from the substrate101.

Although not illustrated inFIG. 1, at least one conductive layer and at least one insulation layer may be disposed between the substrate101and the base insulation layer110. The conductive layer and the insulation layer may form various circuit patterns. That is, the conductive layer and the insulation layer may form a plurality of wirings, or may compose of passive elements such as a capacitor or a resistor, or active elements such as a diode or a transistor, by way of non-limiting examples.

Referring toFIG. 1, the first source electrode structure12may be disposed on the base insulation layer110. The first source electrode structure12may include first to fourth source electrode layer patterns122a,122b,122cand122dand first to fifth source insulation layer patterns132a,132b,132c,132dand132e, which are alternately stacked on the base insulation layer110in a first direction (i.e., the z-direction) perpendicular to the substrate101. Here, the first source electrode structure12may extend in a second direction (i.e., the y-direction) perpendicular to the first direction. The first to fourth source electrode layer patterns122a,122b,122cand122dmay be electrically insulated from each other by the first to fifth source insulation layer patterns132a,132b,132c,132dand132ewith respect to the first direction (i.e., the z-direction). The first to fourth source electrode layer patterns122a,122b,122cand122dmay be conductive lines extending in the second direction (i.e., the y-direction). Each of the first to fourth source electrode layer patterns122a,122b,122cand122dmay be independently maintained a predetermined potential.

In an embodiment, the first to fourth source electrode layer patterns122a,122b,122cand122dmay each include a conductive material. The conductive material may include, for example, doped semiconductor, metal, conductive metal silicide, conductive metal nitride, conductive metal oxide, of the like. The first to fifth source insulation layer patterns132a,132b,132c,132dand132emay each include an insulative material. The insulative material may include, for example, oxide, nitride, oxynitride, or similar materials.

Referring toFIGS. 1 and 3, the first channel structure22may be disposed on the base insulation layer110. The first channel structure22may have a predetermined height along the first direction (i.e., the z-direction), have a predetermined length along the second direction (i.e., the y-direction), and have a predetermined width along the third direction (i.e., the x-direction).

In an embodiment, the first channel structure22may be disposed to contact a sidewall surface12S of the first source electrode structure12. Viewed in the x-direction, the first channel structure22may extend in the second direction (i.e., the y-direction), and may be disposed to cover or be co-extensive with a sidewall surface of the first source electrode structure12, which includes the first to fourth source electrode layer patterns122a,122b,122c, and122dand the first to fifth source insulation layer patterns132a,132b,132c,132d, and132e.

The first channel structure22may include first to fourth gate dielectric structures32a,32b,32c, and32dand first to fourth gate electrode structures42a,42b,42c, and42d. That is, the first channel structure22may be disposed to surround or envelope outer sidewalls of the first to fourth gate dielectric structures32a,32b,32c, and32d, which in turn may surround sidewalls of the first to fourth gate electrode structures42a,42b,42c, and42d.

The first channel structure22may include doped semiconductor material, metal oxide, transition metal di-chalcogenide (TMDC), or a combination of two or more thereof. The semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The metal oxide may include indium-gallium-zinc oxide, for example. In an embodiment, the first channel structure22may include silicon (Si) doped with an n-type dopant. Alternatively, the first channel structure22may include c-axis aligned indium-gallium-zinc oxide. The transition metal di-chalcogenide (TMDC) may include, for example, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2) molybdenum telluride (MoTe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), or similar materials.

The first to fourth gate dielectric structures32a,32b,32c, and32dmay be disposed in the first channel structure22. The first to fourth gate dielectric structures32a,32b,32c, and32dmay each be disposed on the base insulation layer110and extend in a pillar-like shape in the first direction (i.e., the z-direction). In addition, the first to fourth gate electrode structures42a,42b,42c, and42dmay be disposed in the corresponding first to fourth gate dielectric structures32a,32b,32c, and32d, respectively. The first to fourth gate electrode structures42a,42b,42c, and42dmay be disposed on the base insulation layer110to extend in the first direction (i.e., the z-direction). The first to fourth gate electrode structures42a,42b,42c, and42dmay each have a pillar-like shape. Thus, as illustrated inFIG. 2, each of the first to fourth gate dielectric structures32a,32b,32c, and32dmay surround or envelop outer surfaces of each of the first to fourth gate electrode structures42a,42b,42c, and42dby a predetermined thickness t32. Similarly, the first channel structure22may surround or envelope the first to fourth gate dielectric structures32a,32b,32c, and32d, which in turn surround or envelope and the first to fourth gate electrode structures42a,42b,42c, and42d, respectively.

Referring toFIG. 2, the first to fourth gate dielectric structures32a,32b,32c, and32dmay be disposed to be spaced apart from a first sidewall surface22S1of the first channel structure22in the third direction (i.e., the x-direction) by a first distance d1, and may be disposed to be spaced apart from a second sidewall surface22S2of the first channel structure22in the third direction (i.e., the x-direction) by a second distance d2. In other words, the first to fourth gate dielectric structures32a,32b,32c, and32dmay be disposed to be spaced apart from the first source electrode structure12and the first resistance change memory layer310in the third direction (i.e., the x-direction), by the first distance d1and the second distance d2. The first to fourth gate dielectric structures32a,32b,32c, and32dmay each include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or the like.

The first to fourth gate electrode structures42a,42b,42c, and42dmay be separated from the first channel structure22by the first to fourth gate dielectric structures32a,32b,32c, and32d. The first to fourth gate electrode structures42a,42b,42c, and42dmay each include a conductive material. The conductive material may include metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide, as non-limiting examples. The conductive material may include tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

Referring toFIGS. 1 to 3, the first resistance change memory layer310may be disposed on the second sidewall surface22S2of the first channel structure22. As illustrated, the second sidewall surface22S2may be a plane formed by a first direction (i.e., a z-direction) and a second direction (i.e., a y-direction). The first resistance change memory layer310may be disposed to have a predetermined thickness in the third direction (i.e., the x-direction).

An internal resistance of the first resistance change memory layer310may be variably changed when a voltage of a threshold voltage or higher, or a current of a threshold current or higher, is applied from outside. The variably changed internal resistance may be maintained even after the voltage or current is removed from the first resistance change memory layer310, so that the internal resistance may be stored in the first resistance change memory layer310as signal information in a nonvolatile manner. In an embodiment, first, when a gate voltage of a threshold voltage or higher is applied to the first to fourth gate electrode structures42a,42b,42c, and42d, a channel layer may be formed in the first channel structure22. More specifically, the channel layer may be formed in the channel structure22adjacent to the first to fourth gate dielectric structures32a,32b,32c, and32dthat respectively correspond to the first to fourth gate electrode structures42a,42b,42c, and42d. Then, after the channel layer is formed, when a voltage is applied between the first to fourth source electrode layer patterns122a,122b,122c, and122dof the first source electrode structure12and the first to fourth drain electrode layer patterns124a,124b,124c, and124dof the drain electrode structure14, that voltage may be mostly applied to the first resistance change memory layer310in the x-direction. Thus, the internal resistance of the first resistance change memory layer310may vary according to the magnitude and polarity of an externally applied voltage.

In an embodiment, the first resistance change memory layer310may include oxide having oxygen vacancies. For example, the oxide may include silicon oxide, aluminum oxide, tantalum oxide, titanium oxide, hafnium oxide, or a combination of two or more thereof.

Referring toFIGS. 1 to 3, the drain electrode structure14may be disposed on the base insulation layer110and contact the first resistance change memory layer310. The drain electrode structure14may include first to fourth drain electrode layer patterns124a,124b,124c, and124dand first to fifth drain insulation layer patterns134a,134b,134c,134d, and134e, which are alternately stacked in the first direction (i.e., the z-direction). Here, the drain electrode structure14may extend in the second direction (i.e., the y-direction).

The first to fourth drain electrode layer patterns124a,124b,124c, and124dmay be electrically insulated from each other by the first to fifth drain insulation layer patterns134a,134b,134c,134d, and134e. The first to fourth drain electrode layer patterns124a,124b,124c, and124dmay be conductive lines extending in the second direction (i.e., the y-direction). The first to fourth drain electrode layer patterns124a,124b,124c, and124dmay each maintain a predetermined potential. In an embodiment, during a write operation or a read operation into the first resistance change memory layer310of the nonvolatile memory device1, the potential of the first to fourth drain electrode layer patterns124a,124b,124c, and124dmay be different from the potential of the first to fourth source electrode layer patterns122a,122b,122c, and122dof the first source electrode structure12. During a write operation or a read operation into the second resistance change memory layer320of the nonvolatile memory device1, the potential of the first to fourth drain electrode layer patterns124a,124b,124c, and124dmay be different from the potential of the first to fourth source electrode layer patterns126a,126b,126c, and126dof the second source electrode structure16.

In an embodiment, the first to fourth source electrode layer patterns122a,122b,122c, and122dand the first to fourth drain electrode layer patterns124a,124b,124c, and124dmay be disposed at positions corresponding to each other on the same or substantially the same horizontal plane. For example, the first source electrode layer pattern122aand the first drain electrode layer pattern124amay be disposed opposite to each other, and at substantially the same vertical location on either side of the first channel structure22. In the same manner, the second to fourth source electrode layer patterns122b,122cand122dand the second to fourth drain electrode layer patterns124b,124cand124dmay be disposed at the same level on opposite sides of the first channel structure22, respectively.

In an embodiment, the first to fourth drain electrode layer patterns124a,124b,124c, and124dmay each include a conductive material. The conductive material may include doped semiconductor, metal, conductive metal silicide, conductive metal nitride, conductive metal oxide or the like. The first to fifth drain insulation layer patterns134a,134b,134c,134d, and134emay each include an insulative material. The insulative material may include, for example oxide, nitride, oxynitride, or the like.

Referring toFIGS. 1 to 3, the second resistance change memory layer320may be disposed on a sidewall surface of the drain electrode structure14opposite to the sidewall surface in contact with first resistance change memory layer310. The second resistance change memory layer320may be disposed, on the base insulation layer110, in a manner similar to the first resistance change memory layer310, with the drain electrode structure14interposed therebetween.

An internal resistance of the second resistance change memory layer320may be variably changed when a voltage of a threshold voltage or higher, or a current of a threshold current or higher, is applied from outside. The variably changed internal resistance may be maintained even after the voltage or current is removed from the second resistance change memory layer320, so that the internal resistance may be stored in the second resistance change memory layer320as signal information in a nonvolatile manner. In an embodiment, the internal resistance of the second resistance change memory layer320may be variably changed according to a voltage or a current applied between the first to fourth source electrode layer patterns126a,126b,126c, and126dof the second source electrode structure16and the first to fourth drain electrode layer patterns124a,124b,124c, and124dof the drain electrode structure14, based on a channel layer formed in the second channel structure24, as described below. The channel layer may be formed in the second channel structure24adjacent to the corresponding fifth to eighth gate dielectric structures34a,34b,34c, and34dwhen a voltage of a threshold voltage or higher is applied to the fifth to eighth gate electrode structures44a,44b,44c, and44d. A configuration of the second resistance change memory layer320may be substantially the same as a configuration of the first resistance change memory layer310.

Referring toFIGS. 1 to 3, the second channel structure24may be disposed on the base insulation layer110and contact the second resistance change memory layer320at a first sidewall surface24S1.

The second channel structure24may include the fifth to eighth gate dielectric structures34a,34b,34c, and34dand the fifth to eighth gate electrode structures44a,44b,44c, and44d. That is, the second channel structure24may surround or envelop outer surfaces of each of the fifth to eighth gate dielectric structures34a,34b,34c, and34d, which in turn surrounds or envelops the fifth to eighth gate electrode structures44a,44b,44c, and44d, respectively. A configuration of the second channel structure24may be substantially the same as the configuration of the first channel structure22.

The fifth to eighth gate dielectric structures34a,34b,34c, and34dmay each be disposed on the base insulation layer110, and extend in a pillar shape extending in the first direction (i.e., the z-direction). The fifth to eighth gate electrode structures44a,44b,44c, and44dmay each be disposed on the base insulation layer110and extend in the first direction (i.e., the z-direction). In addition, in a plan view, the fifth to eighth gate electrode structures44a,44b,44c, and44dmay be disposed in and fill the area within the fifth to eighth gate dielectric structures34a,34b,34c, and34d. Thus, as illustrated inFIG. 2, the fifth to eighth gate dielectric structures34a,34b,34c, and34dmay be disposed to surround the fifth to eighth gate electrode structures44a,44b,44c, and44dby a predetermined thickness t34.

Referring toFIG. 2, the fifth to eighth gate dielectric structures34a,34b,34cand34dmay be disposed to be spaced apart from a first sidewall surface24S1of the second channel structure24in the third direction (i.e., the x-direction) by a first distance d3, and disposed to be spaced apart from a second sidewall surface24S2of the second channel structure24in the third direction (i.e., the x-direction) by a second distance d4. In other words, the fifth to eighth gate dielectric structures34a,34b,34cand34dmay be disposed do be spaced apart from the second resistance change memory layer320, and the second source electrode structure16, in the third direction (i.e., the x-direction) by the first distance d3and second distance d4, respectively. A configuration of the fifth to eighth gate dielectric structures34a,34b,34cand34dmay be substantially the same as the configuration of the first to fourth gate dielectric structures32a,32b,32cand32d.

The fifth to eighth gate electrode structures44a,44b,44cand44dmay be separated from the second channel structure24by the fifth to eighth gate dielectric structures34a,34b,34cand34d. A configuration of the fifth to eighth gate electrode structures44a,44b,44cand44dmay be substantially the same as the configuration of the first to fourth gate electrode structures42a,42b,42cand42d.

Referring toFIGS. 1 to 3, the second source electrode structure16may be disposed on the base insulation layer110and contact the second sidewall surface24S2of the second channel structure24. The second source electrode structure16may include first to fourth source electrode layer patterns126a,126b,126cand126dand first to fifth source insulation layer patterns136a,136b,136c,136dand136e, which are alternately stacked along the first direction (i.e., the z-direction). The second source electrode structure16may extend in the second direction (i.e., the y-direction) perpendicular to the first direction.

The first to fourth source electrode layer patterns126a,126b,126cand126dmay be electrically insulated from each other by the first to fifth source insulation layer patterns136a,136b,136c,136dand136e. The first to fourth source electrode layer patterns126a,126b,126cand126dmay be conductive lines extending in the second direction (i.e., the y-direction). The first to fourth source electrode layer patterns126a,126b,126cand126dmay each maintain a predetermined potential.

In an embodiment, configurations of the first to fourth source electrode layer patterns126a,126b,126cand126dof the second electrode source structure16may be substantially the same as the configurations of the first to fourth source electrode layer patterns122a,122b,122cand122dof the first source electrode structure12. In addition, configurations of the first to fifth source insulation layer patterns136a,136b,136c,136dand136eof the second source electrode structure16may be substantially the same as the configurations of the first to fifth source insulation layer patterns132a,132b,132c,132dand132eof the first source electrode structure12.

Referring toFIGS. 1 to 3, the first and second resistance change memory layers310and320, the first and second channel structures22and24, and the first and second source electrode structures12and16may each be symmetrically disposed around a y-z plane centered on drain electrode structure14. Similarly, the first to fourth gate dielectric structures32a,32b,32c, and32dand the fifth to eighth gate dielectric structures34a,34b,34c, and34dmay be symmetrically disposed around an y-z plane centered on the drain electrode structure14, respectively. In addition, the first to fourth gate electrode structures42a,42b,42cand42dand the fifth to eighth gate electrode structures44a,44b,44cand44dmay be symmetrically disposed around an y-z plane centered on the drain electrode structure14, respectively.

Referring toFIGS. 1 and 2, the first to fourth gate dielectric structures32a,32b,32c,32dand fifth to eight gate dielectric structures34a,34b,34cand34dand the first to fourth gate electrode structures42a,42b,42c,42dand fifth to eighth gate electrode structures44a,44b,44cand44dmay be arranged in the second direction (i.e., the y-direction) in first and second channel structures22and24, respectively. The first and second resistance change memory layers310and320, the first and second source electrode structures12and16, and the drain electrode structure14may extend in the second direction (i.e., the y-direction) to cover or to be co-extensive with the first to fourth gate dielectric structures32a,32b,32c,32dand fifth to eight gate dielectric structures34a,34b,34cand34dand the first to fourth gate electrode structures42a,42b,42c,42dand fifth to eighth gate electrode structures44a,44b,44cand44d, respectively.

In some other embodiments, the number of the source electrode layer patterns of the first and second source electrode structures12and16and the number of the drain electrode layer patterns of the drain electrode structure14are not necessarily limited to four, and other various numbers are possible. In addition, the number of the source insulation layer patterns of the first and second source electrode structures12and16and the number of the drain insulation layer patterns of the drain electrode structure14are not necessarily limited to five, and other various numbers are possible. Similarly, the number of the gate dielectric structures and the gate electrode structures inside the first and second resistance change structures22and24, respectively, is not necessarily limited to four, but various other numbers are possible.

FIG. 4is a schematic circuit diagram of a nonvolatile memory device according to an embodiment of the present disclosure. The circuit diagram ofFIG. 4may correspond to a portion of the configuration of the nonvolatile memory device1described above with reference toFIGS. 1 to 3.

The first to fourth memory cells MC1, MC2, MC3and MC4may be disposed between a first global source line GSL1and a global drain line GDL, and the fifth to eighth memory cells MC5, MC6, MC7and MC8may be disposed between a second global source line GSL2and the global drain line GDL. When a gate operation voltage of a predetermined threshold voltage or higher is applied to at least one of first to fourth word lines WL1, WL2, WL3and WL4, at least one of the corresponding first to fourth selection transistors TR1, TR2, TR3and TR4may be turned on. The voltage applied to the first to fourth word lines WL1, WL2, WL3and WL4may be independently controlled, and thus, only the selected transistor to which the gate operation voltage is applied may be turned on from among the first to fourth selection transistors TR1, TR2, TR3and TR4. A source-drain voltage between the first global source line GSL1and the global drain line GDL may be applied to the memory cell in which the selected transistor is turned on. The source-drain voltage may be a write voltage or a read voltage that performs a write operation or a read operation with respect to a corresponding resistive memory layer in the first to fourth resistive memory layers CR1, CR2, CR3, and CR4.

Likewise, when a gate operation voltage of a predetermined threshold voltage or higher is applied to at least one of fifth to eighth word lines WL5, WL6, WL7and WL8, at least one of the corresponding fifth to eighth selection transistors TR5, TR6, TR7and TR8may be turned on. The voltage applied to the fifth to eighth word lines WL5, WL6, WL7and WL8may be independently controlled, and thus, only the selected transistor to which the gate operation voltage is applied may be turned on from among the fifth to eighth selection transistors TR5, TR6, TR7and TR8. A source-drain voltage between the second global source line GSL2and the global drain line GDL may be applied to the memory cell in which the selected transistor is turned on. The source-drain voltage may be a write voltage or a read voltage that performs a write operation or a read operation with respect to a corresponding resistive memory layer in the fifth to eighth resistive memory layers CR5, CR6, CR7, and CR8.

In some other embodiments, the number of the memory cells disposed between the first global source line GSL1and the global drain line GDL is not necessarily limited to four, and other various numbers are possible. Accordingly, the number of the memory cells disposed between the second global source line GSL2and the global drain line GDL is also not necessarily limited to four, and other various numbers are possible.

When comparingFIG. 4withFIGS. 1 to 3, the first global source line GSL1may correspond to any one of the first to fourth source electrode layer patterns122a,122b,122cand122dof the first source electrode structure12. The global drain line GDL may be any one of the first to fourth drain electrode layer patterns124a,124b,124cand124dof the drain electrode structure14. That is, the one of the first to fourth source electrode layer patterns122a,122b,122cand122dand the one of the first to fourth drain electrode layer patterns124a,124b,124cand124dmay be symmetrically disposed on the same plane around the first channel structure12on the same plane.

For example, when the first global source line GSL1is the fourth source electrode layer pattern122d, the global drain line GDL may be the fourth drain electrode layer pattern124d. Similarly, when the first global source line GSL1is any one of the first to third source electrode layer patterns122a,122band122c, the global drain line GDL may be any corresponding one of the first to third drain electrode layer patterns124a,124band124c.

Referring toFIGS. 4 and 5, the first to fourth selection transistors TR1, TR2, TR3and TR4may be composed of the first channel structure22, the first to fourth gate dielectric structures32a,32b,32cand32d, and the first to fourth gate electrode structures42a,42b,42cand42d, which are disposed between the first source electrode structure12and the drain electrode structure14in the nonvolatile memory device1related toFIGS. 1 to 3. Here, the first to fourth word lines WL1, WL2, WL3and WL4may correspond to the first to fourth gate electrode structures42a,42b,42cand42d, respectively. The first to fourth resistive memory layers CR1, CR2, CR3and CR4may respectively correspond to regions of the first resistance change memory layer310which contacts the channel layer regions, as described later with reference toFIG. 5.

In the same manner, the second global source line GSL2may correspond to any one of the first to fourth source electrode layer patterns126a,126b,126cand126dof the second source electrode structure16. The global drain line GDL may correspond to any one of the first to fourth drain electrode layer patterns124a,124b,124cand124dof the drain electrode structure14. Here, the one of the first to fourth source electrode layer patterns126a,126b,126cand126dand the one of the first to fourth drain electrode layer patterns124a,124b,124cand124dmay be symmetrically disposed on the same plane around the second channel structure24. For example, when the second global source line GSL2is the fourth source electrode layer pattern126d, the global drain line GDL may be the fourth drain electrode layer pattern124d. Similarly, when the second global source line GSL2is any one of the first to third source electrode layer patterns126a,126band126c, the global drain line GDL may be any corresponding one of the first to third drain electrode layer patterns124a,124band124c.

The fifth to eighth selection transistors TR5, TR6, TR7and TR8may be composed of the second channel structure24, the fifth to eighth gate dielectric structures34a,34b,34cand34d, and the fifth to eighth gate electrode structures44a,44b,44cand44d, which are disposed between the second source electrode structure16and the drain electrode structure14. Here, the fifth to eighth word lines WL5, WL6, WL7and WL8may correspond to the fifth to eighth gate electrode structures44a,44b,44cand44d, respectively. The fifth to eighth resistive memory layers CR5, CR6, CR7and CR8may respectively correspond to regions of the second resistance change memory layer320that contacts the channel layer regions, as described later with reference toFIG. 5.

As described above, the first to fourth memory cells MC1, MC2, MC3and MC4and the fifth to eighth memory cells MC5, MC6, MC7and MC8may share the global drain line GDL. When a selected transistor in at least one memory cell of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7and MC8is turned on, a predetermined resistance may be written in or read out from a resistance change memory layer in the at least one memory cell, depending on a source-drain operation voltage applied between the first global source line GSL1or the second global source line GSL2and the global drain line DSL. As such, according to an embodiment of the present disclosure, random access to any one of the first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7and MC8is possible, and a write operation or a read operation may be performed with respect to the randomly accessed memory cell.

FIG. 5is a view schematically illustrating a method of driving a nonvolatile memory device according to an embodiment of the present disclosure.FIG. 5is a section of the nonvolatile memory device1described above with reference toFIGS. 1 to 3in a plane perpendicular to the z-direction.FIG. 5illustrates a fourth source electrode layer pattern122dof a first source electrode structure12, a fourth drain electrode layer pattern124dof a drain electrode structure14, and a fourth source electrode layer pattern126dof a second source electrode structure16as components for implementing first to eighth memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7and MC8ofFIG. 4.FIG. 5also illustrates the cross-sections of first and second channel structures22and24, first and second resistance change memory layer310and320. Hereinafter, for example, a driving method of the first memory cell MC1and the eighth memory cell MC8will be described in detail.

In an embodiment, the first memory cell MC1may be comprised of the first channel structure22, a first gate dielectric structure32a, a first gate electrode structure42aand a first resistance change memory layer310, which are disposed between the fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124d. In driving the first memory cell MC1, the fourth source electrode layer pattern122dmay be selected among the first to fourth source electrode layer patterns122a,122b,122cand122dof the first source electrode structure12. The fourth drain electrode layer pattern124dof the drain electrode structure14corresponding to the fourth source electrode layer pattern122dmay be selected. The fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124dmay control the first to fourth memory cells MC1, MC2, MC3and MC4. A source bias and a drain bias having different magnitudes may be applied to the fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124d, respectively, so that the fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124dmay each have a different potential.

Then, a gate operation voltage having a magnitude of a predetermined threshold voltage or greater may be applied to the first gate electrode structure42afrom among the first to fourth gate electrode structures42a,42b,42cand42d. A channel layer22CH1may be formed in a region of the first channel structure22, adjacent to the first gate dielectric structure32a, depending on the gate operation voltage. The channel layer22CH1may be formed on the base insulation layer110in a shape of a pillar or a layer extending in a first direction (i.e., the z-direction) to surround the outer surfaces of the first gate dielectric structure32a. When the channel layer22CH1is formed, a source-drain operation voltage corresponding to a potential difference between the fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124dmay be mostly applied to the first resistance change memory layer310having a relatively high resistance state, rather than applied to the channel layer22CH1having a low resistance state. Consequently, when the source-drain operation voltage is applied, charge CF1may flow between the fourth source electrode layer pattern122dand the fourth drain electrode layer pattern124d.

The source-drain operation voltage may perform a write operation or a read operation with respect to the first resistance change memory layer310. The write operation may be an operation that varies an electrical resistance of a region of the first resistance change memory layer310that is in contact with the channel layer22CH1, depending on a predetermined write voltage. After the write voltage is removed from the first resistance change memory layer310, the changed resistance may be stored in the region of the first resistance change memory layer310in a nonvolatile manner. The read operation may be an operation of reading a resistance of the region of the first resistance change memory layer310in contact with the channel layer22CH1, depending on a predetermined read voltage.

In an embodiment, the resistance change may occur through an operation in which conductive filaments are generated in a region of the first resistance change memory layer310in contact with the channel layer22CH1, or through an operation in which the generated filaments are partially disconnected with respect to the third direction (i.e., the x-direction) when different write voltages are applied to the first resistance change memory layer310. In another embodiment, the resistance change may occur through an operation in which an insulative thin film is generated in the first resistance change memory layer310in contact with the channel layer22CH1, or through an operation in which the generated insulative thin film is removed, depending on the different write voltage.

In another embodiment, the eighth memory cell MC8may be comprised of the second channel structure24disposed between the fourth source electrode layer pattern126dand the fourth drain electrode layer pattern124d, the eighth gate dielectric structure34d, the eighth gate electrode structure44d, and the second resistance change memory layer320. In driving the eighth memory cell MC8, the fourth source electrode layer pattern126dmay be selected from the first to fourth source electrode layer patterns126a,126b,126c, and126dof the second source electrode structure16. Thus, the fourth drain electrode layer pattern124dof the drain electrode structure14corresponding to the fourth source electrode layer pattern126dof the second source electrode structure16may be selected. The fourth source electrode layer pattern126dand the fourth drain electrode layer pattern124dmay control the fifth to eighth memory cells MC5, MC6, MC7and MC8. A different source bias and drain bias may be applied to the fourth source electrode layer pattern126dof the second source electrode structure16and the fourth drain electrode layer pattern124dof the drain electrode structure14, respectively, so that the fourth source electrode layer pattern126dand the fourth drain electrode layer pattern124dmay have different potentials.

Then, a gate voltage of a predetermined threshold voltage or higher may be applied to the eighth gate electrode structure44damong the fifth to eighth gate electrode structures44a,44b,44cand44d. A channel layer24CH8may be formed in a region of the second channel structure24, in contact with the eighth gate dielectric structure34d, depending on the gate operation voltage. The channel layer24CH8may be formed on the base insulation layer110in a shape of a pillar or a layer extending in the first direction (i.e., the z-direction) to surround the outer surfaces of eighth gate dielectric structure34d. When the channel layer24CH8is formed, a source-drain operation voltage corresponding to a potential difference between the fourth source electrode layer pattern126dof the second source electrode structure16and the fourth drain electrode layer pattern124dof the drain electrode structure14may be mostly applied to the second resistance change memory layer320having a relatively high resistance state, rather than applied to the channel layer24CH8having a low resistance state. Accordingly, when the source-drain operation voltage is applied, charge CF2may flow between the fourth source electrode layer pattern126dof the second source electrode structure16and the fourth drain electrode layer pattern124dof the drain electrode structure14.

The source-drain operation voltage may perform a write operation or a read operation on the second resistance change memory layer320. The write operation may be an operation that varies the electrical resistance with respect to a region of the second resistance change memory layer320, in contact with the channel layer24CH8, depending on a predetermined write operation voltage. After the write operation voltage is removed from the second resistance change memory layer320, the changed resistance may be stored in the region of the second resistance change memory layer320in a nonvolatile manner. The read operation may be an operation of reading a resistance with respect to a region of the second resistance change memory layer320, in contact with the channel layer24CH8, depending on a predetermined read operation voltage.

In an embodiment, the resistance change may occur via an operation in which conductive filaments are generated in the third direction (i.e., the x-direction), or in which the generated conductive filaments are partially disconnected with respect to the third direction (i.e., the x-direction), in the region of the second resistance change memory layer320in contact with the channel layer24CH8, when different write voltages are applied to the second resistance change memory layer320. In another embodiment, the resistance change may occur via an operation in which an insulative thin film is generated in the second resistance change memory layer320in contact with the channel layer24CH8, or in which the generated insulative thin film is removed, depending on the different write voltages.

FIG. 6is a perspective view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.FIG. 7is a plan view of the nonvolatile memory device ofFIG. 6.

Referring toFIGS. 6 and 7, in comparison with the nonvolatile memory device1ofFIGS. 1 to 3, the nonvolatile memory device2may further include first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50j.

The first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50jmay be disposed to extend along a first direction (i.e., the z-direction) from a base insulation layer110. The first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50jmay be disposed to be spaced apart from each other in first and second channel structures22and24. The first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50jmay be disposed between neighboring gate dielectric structures32a,32b,32c,32d,34a,34b,34cand34dalong a second direction (i.e., the y-direction). The first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50jmay electrically separate the neighboring first and second channel structures22and24along the second direction (i.e., the y-direction). Accordingly, it is possible to prevent electrical signals from interfering with channel layers of the neighboring channel structures.

In an embodiment, the first to fifth cell insulation structures50a,50b,50c,50dand50emay be disposed to contact the first source electrode structure12and the first resistance change memory layer310in a third direction (i.e., the x-direction). The sixth to tenth cell insulation structures50f,50g,50h,50iand50jmay be disposed to contact the second source electrode structure16and the second resistance change memory layer320in a third direction (i.e., the x-direction).

FIG. 8is a perspective view schematically illustrating a nonvolatile memory device according to yet another embodiment of the present disclosure.FIG. 9is a plan view of the nonvolatile memory device ofFIG. 8.

Referring toFIGS. 8 and 9, in comparison with the nonvolatile memory device2ofFIGS. 6 and 7, the nonvolatile memory device3may have a different configuration in first to tenth cell insulation structures50a1,50b1,50c1,50d1,50e1,50f1,50g1,50h1,50i1and50j1.

Compared to the first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50jillustrated inFIGS. 6 and 7, the first to fifth cell insulation structures50a1,50b1,50c1,50d1and50e1of the embodiments may extend positively in a third direction (i.e., the x-direction) to directly contact a drain electrode structure14. Here, in the third direction (i.e., the x-direction), a portion of a first resistance change memory layer310between the first to fifth cell insulation structures50a1,50b1,50c1,50d1and50e1and the drain electrode structure14may be removed. In addition, the sixth to tenth cell insulation structures50f1,50g1,50h1,50i1and50j1of the embodiments may extend negatively in the third direction (i.e., the x-direction) to directly contact the drain electrode structure14. There, a portion of a second resistance change memory layer320between the sixth to tenth cell insulation structures50f1,50g1,50h1,50i1and50j1and the drain electrode structure14may be removed.

The first to tenth cell insulation structures50a1,50b1,50c1,50d1,50e1,50f1,50g1,50h1,50i1and50j1may be disposed to directly contact the drain electrode structure14in the x-direction, thereby electrically separating the first and second resistance change memory layers310and320in a second direction (i.e., the y-direction). Accordingly, electrical signal interference between neighboring memory cells in the second direction can be effectively prevented.

FIG. 10is a perspective view schematically illustrating a nonvolatile memory device according to still yet another embodiment of the present disclosure.FIG. 11is a plan view of the nonvolatile memory device ofFIG. 10.

Referring toFIGS. 10 and 11, in comparison with the nonvolatile memory device2ofFIGS. 6 and 7, the nonvolatile memory device4may include first to eighth gate dielectric structures62a,62b,62c,62d,64a,64b,64cand64dand first to eighth gate electrode structures72a,72b,72c,72d,74a,74b,74cand74dwhich have tip portions protruding in the x-direction toward the first and second resistance change memory layers310and320.

The first to eighth gate dielectric structures62a,62b,62c,62d,64a,64b,64cand64dand the first to eighth gate electrode structures72a,72b,72c,72d,74a,74b,74cand74dmay each have a rhombus shape with four vertices on a plane perpendicular to a first direction (i.e., in a horizontal plane). Accordingly, the first to fourth gate dielectric structures62a,62b,62cand62dmay have tip portions62at,62bt,62ctand62dtprotruding toward at least the first resistance change memory layer310. In addition, the fifth to eighth gate dielectric structures64a,64b,64cand64dmay have tip portions64at,64bt,64ctand64dtprotruding toward at least the second resistance change memory layer320. Likewise, the first to fourth gate electrode structures72a,72b,72cand72dmay have tip portions72at,72bt,72ctand72dtprotruding toward at least the first resistance change memory layer310. In addition, the fifth to eighth gate electrode structures74a,74b,74cand74dmay have tip portions74at,74bt,74ctand74dtprotruding toward at least the second resistance change memory layer320.

The protruding tip portions72at,72bt,72ct,72dt,74at,74bt,74ctand74dtof the first to eighth gate electrode structures72a,72b,72c,72d,74a,74b,74cand74d, and the protruding tip portions62at,62bt,62ct,62dt,64at,64bt,64ctand64dtof the first to eighth gate dielectric structures62a,62b,62c,62d,64a,64b,64cand64d, may allow an electric field to be concentrated on the protruding tip portions62at,62bt,62ct,62dt,64at,64bt,64ctand64dtwhen channels are formed in the first and second channel structures22and24, as described above. With a concentrated electric field, resistance change may effectively occur in the first and second resistance change memory layers310and320. For example, conductive filaments may be preferentially generated in the first and second resistance change memory layers310and320in which the electric field is concentrated, or generated conductive filaments may be effectively disconnected, based on the electric field concentration effect. In another example, nucleation of the insulation layer may occur preferentially in the first and second resistance change memory layers310and320in which the electric field is concentrated, or removal of the insulation layer may occur first. Thus, it is possible to effectively write and store the signal information via the resistance change.

In some other embodiments not illustrated, a configuration including the first to eighth gate dielectric structures62a,62b,62c,62d,64a,64b,64cand64d, and the first to eighth gate electrode structures72a,72b,72c,72d,74a,74b,74cand74dthat have tip portions protruding toward the first and second resistance change memory layers310and320, may be applied to the nonvolatile memory device1(described above with reference toFIGS. 1 to 3), which does not have the first to tenth cell insulation structures50a,50b,50c,50d,50e,50f,50g,50h,50iand50j.

FIG. 12is a perspective view schematically illustrating a nonvolatile memory device according to still yet another embodiment of the present disclosure.FIG. 13is a plan view of the nonvolatile memory device ofFIG. 12.FIG. 14is a cross-sectional view taken along the line B-B′ of the nonvolatile memory device ofFIG. 13.

Referring toFIGS. 12 to 14, the nonvolatile memory device5may have a different configuration in first and second source electrode structures82and86and a drain electrode structure84, in comparison with the nonvolatile memory device4described above with reference toFIGS. 10 and 11.

In some embodiments, the first source electrode structure82may include first to fourth source electrode layer patterns822a,822b,822cand822dand first to fifth source insulation layer patterns832a,832b,832c,832dand832e, which are alternately stacked along a first direction (i.e., the z-direction). The second source electrode structure86may include first to fourth source electrode layer patterns826a,826b,826cand826dand first to fifth source insulation layer patterns836a,836b,836c,836dand836e, which are alternately stacked along a first direction (i.e., the z-direction). The drain electrode structure84may include first to fourth drain electrode layer patterns824a,824b,824cand824dand first to fifth drain insulation layer patterns834a,834b,834c,834dand834e, which are alternately stacked along a first direction (i.e., the z-direction).

Referring toFIGS. 12 to 14, the first to fourth source electrode layer patterns822a,822b,822cand822dof the first source electrode structure82may be disposed to contact the first channel structure22. In contrast, the first to fifth source insulation layer patterns832a,832b,832c,832dand832emay be disposed to contact the first to fourth gate dielectric structures62a,62b,62cand62d. That is, the first to fifth source insulation layer patterns832a,832b,832c,832dand832e, rather than the first to fourth source electrode layer patterns822a,822b,822cand822d, extend along a third direction (i.e., the x-direction), and the first channel structure22is selectively removed, so that the first to fifth source insulation layer patterns832a,832b,832c,832dand832emay directly contact the first to fourth gate dielectric structures62a,62b,62cand62das illustrated inFIG. 14. In such embodiments, the first to fifth source insulation layer patterns832a,832b,832c,832dand832emay more effectively insulate between the first to fourth source electrode layer patterns822a,822b,822cand822d.

Likewise, the first to fourth source electrode layer patterns826a,826b,826cand826dof the second source electrode structure86may be disposed to contact the second channel structure24along a direction opposite to a third direction (i.e., the x-direction). In contrast, the first to fifth source insulation layer patterns836a,836b,836c,836dand836emay be disposed to contact the fifth to eighth gate dielectric structures64a,64b,64cand64d. That is, the first to fifth source insulation layer patterns836a,836b,836c,836dand836eextend negatively along the third direction, rather than the first to fourth source electrode layer patterns826a,826b,826cand826d, and the second channel structure24is selectively removed, so that the first to fifth source insulation layer patterns836a,836b,836c,836dand836emay contact the fifth to eighth gate dielectric structures64a,64b,64cand64ddirectly. In such embodiments, the first to fifth source insulation layer patterns836a,836b,836c,836dand836emay more effectively insulate between the first to fourth source electrode layer patterns826a,826b,826cand826d.

The first to fourth drain electrode layer patterns824a,824b,824cand824dof the drain electrode structure84may extend in a direction opposite to the third direction (i.e., the x-direction) and may be disposed to contact the first and second resistance change memory layers310and320, respectively. In contrast, the first to fifth drain insulation layer patterns834a,834b,834c,834dand834eof the drain electrode structure84may extend further in the third direction and the opposite direction than the first to fourth drain electrode layer patterns824a,824b,824cand824d, and may be disposed to directly contact the first to eighth gate dielectric structures62a,62b,62c,62d,64a,64b,64cand64d. In such embodiments, the first to fifth drain insulation layer patterns834a,834b,834c,834dand834emay more effectively insulate between the first to fourth drain electrode layer patterns824a,824b,824cand824d.

The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.