Methods for fabricating integrated circuits with improved patterning schemes

Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.

TECHNICAL FIELD

The technical field generally relates to lithography, and more particularly relates to methods for fabricating integrated circuits using improved patterning schemes for extreme ultraviolet (EUV) lithography.

BACKGROUND

In conventional fabrication of semiconductor devices, semiconductor wafers are processed in batch, and a large number of complicated devices are formed on a single wafer. With rapid development of very large scale integration (VLSI), wafers are developed toward higher integration density and miniaturization. In the fabrication process, the critical dimensions of integrated circuits are reduced, which raises a higher requirement for lithography processes. However, due to the restriction by the light source wavelength of conventional immersion scanners, conventional lithography cannot meet requirements of processes below 28 nanometers (nm). In order to satisfy the requirements of processes below 28 nm, extreme ultraviolet (EUV) lithography techniques are used. EUV lithography is an emerging technology utilizing extreme ultraviolet light to transfer a circuit layout pattern from a reflective EUV photomask to photoresist overlying a semiconductor substrate.

EUV lithography can be used to form self-aligned vias through interlayer dielectric for the creation of an electrical interconnect structure. Conventionally, photoresist films for exposure by EUV light are formed on an antireflective coating such as a silicon-containing antireflective coating (Si-ARC) that is in turn formed on a planar surface of a material such as a planarization layer. The planarization layer conventionally lies over an etch stop layer formed on the interlayer dielectric. After exposure of the photoresist film and selective etching of the planarization layer to form trenches, the antireflective coating is removed. Further, it may be required that residue from the antireflective coating be removed before further processing of the semiconductor substrate to avoid generating defects on the wafer. Otherwise, the defects generated from the antireflective coating residue may cause yield loss for the fabricated integrated circuit. Also, if it is determined that the etch of the planarization layer is misaligned with underlying objects to be contacted, a rework process may require a wet clean removal of the antireflective coating and a separate strip process to remove the planarization layer before the EUV patterning process is repeated. The Si-Arc removal in a rework process may generate defects on the wafer which would cause yield loss.

Accordingly, it is desirable to provide embodiments of methods for fabricating integrated circuits including improved patterning schemes for use with EUV lithography. It is further desirable to provide embodiments of a method suitable for fabricating an integrated circuit in which the risk of defect generation is minimized and the fabrication is cost effective. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask on the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.

In accordance with another embodiment, a method for fabricating an integrated circuit includes patterning a non-ashable hard mask overlying an interlayer dielectric material and objects to be contacted. The method deposits an ashable planarization layer overlying the non-ashable hard mask, and deposits an ashable pattern transfer layer overlying the ashable planarization layer. A photoresist film is patterned overlying the ashable pattern transfer layer. The method further includes etching the ashable pattern transfer layer using the photoresist film as a mask, etching the ashable planarization layer using the ashable pattern transfer layer as a mask to form trenches through the ashable planarization layer, and etching the interlayer dielectric material using the non-ashable hard mask and ashable planarization layer as a mask to form vias in the interlayer dielectric material.

In another embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate, patterning a hard mask overlying the interlayer dielectric material, depositing a planarization layer overlying the hard mask, depositing a pattern transfer layer overlying the planarization layer, forming a photoresist overlying the pattern transfer layer, and patterning the photoresist. The method determines whether the patterned photoresist is misaligned. If the patterned photoresist is misaligned then the method includes performing a rework process including removing the photoresist, re-forming the photoresist overlying the pattern transfer layer, and re-patterning the photoresist.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the methods for fabricating integrated circuits as claimed herein. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.

In accordance with the various embodiments herein, methods for fabricating integrated circuits with improved patterning schemes are provided. With these methods, problems faced by conventional patterning processes when fabricating integrated circuits may be avoided. For example, conventional self-aligned via etch processes utilizing EUV lithography typically require multiple removal steps, including measures to avoid the generation of defects on the wafer due to antireflective coating residue. As provided herein, methods for fabricating integrated circuits avoid use of an antireflective coating material. Accordingly, the methods disclosed herein may avoid use of a capping layer over the interlayer dielectric to protect the interlayer dielectric material from antireflective coating material removal processes. As a result, the methods described herein may form a patterned hard mask and portions of a planarization layer material directly on the interlayer dielectric to be patterned with vias. The methods described herein may provide for a selective reworking process when initial photoresist lithography steps are not properly aligned that involves only the removal, re-deposition and re-patterning of the photoresist rather than removal and re-deposition of underlying layers. Such capability is beneficial as compared to conventional practices wherein underlying layers must be reformed or reworked due to misalignments before self-aligned via etching. Also, embodiments of the methods described herein may provide for the simultaneous removal of photoresist, pattern transfer and planarization layers used in the formation of self-aligned vias by a single removal process, improving processing efficiency.

FIGS. 1-8illustrate steps of methods for fabricating integrated circuits in accordance with various embodiments.FIG. 9provides a flow chart illustrating a method for fabricating integrated circuits and explaining a rework loop. The processes and steps discussed in relation to each illustrated embodiment are applicable to other illustrated embodiments. Various steps in the design and composition of integrated circuits are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that integrated circuits include a varying number of components and that single components shown in the illustrations may be representative of multiple components.

In an exemplary embodiment,FIG. 1illustrates, in cross-section, steps of a method for fabricating an integrated circuit10. As shown, the method begins by providing a semiconductor substrate12, such as a bulk silicon substrate, a silicon-on-insulator substrate, or a substrate of other semiconductor material. A device or contact structure14, i.e., an object to be contacted, is formed on the semiconductor substrate12in accordance with known integrated circuit fabrication processes. An exemplary contact structure14is a conductive plug formed in contact with a source/drain region on the semiconductor substrate12. As shown, the contact structure14is surrounded by a dielectric material16. Further, a dielectric liner18, such as a low-k dielectric liner, may be formed overlying the contact structure14and dielectric material16.

An interlayer dielectric (ILD) material20, such as silicon oxide, is blanket deposited overlying the dielectric liner18. Further, a hard mask material is deposited over the ILD material20and is etched to form a patterned hard mask22. An exemplary hard mask material is titanium nitride and may be formed in any suitable manner, such as by chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The hard mask material may be patterned by forming a patterned photoresist mask over the hard mask material, and etching exposed portions of the hard mask material. As shown, the hard mask22is formed with openings24, including an opening24overlying the contact structure14. Other openings24may be aligned for formation of trenches for interconnect structures as described below. The exemplary patterned hard mask22is formed directly on the ILD material20, rather than on an intervening layer such as a TEOS layer formed on the ILD material.

InFIG. 2, a planarization layer30is blanket deposited overlying the patterned hard mask22and ILD material20. The so-called “planarization layer” forms a planar upper surface31when deposited. The planarization layer30may be an organic planarization layer, such as an amorphous carbon layer. In certain embodiments, the planarization layer30is ashable. An “ashable” material may be removed by a technique referred to as “ashing,” “plasma ashing” or “dry stripping.” During such processing, substrates with layers to be ashed, such as semiconductor substrate12, are placed into a chamber under vacuum, oxygen is introduced, and the substrates are subjected to radio frequency power that creates oxygen radicals (plasma). The radicals react with ashable material to oxidize it to water, carbon monoxide, and carbon dioxide. A “non-ashable” material is not removed by such an ashing process.

A pattern transfer layer32is deposited over the planarization layer30. An exemplary pattern transfer layer32is inorganic, and may be silicon nitride or silicon oxide. In certain embodiments, the pattern transfer layer32is low temperature oxide, commonly referred to as LTO and formed by CVD using tetraethylorthosilicate (TEOS) between about 650° C. and about 750° C. Further, an exemplary pattern transfer layer32is ashable. As further shown, a patterned photoresist film34is formed over the pattern transfer layer32. For example, a photoresist film is deposited overlying the pattern transfer layer32and is patterned by exposure to EUV light reflected from a EUV mask to form the patterned photoresist film34with an opening36. After patterning the photoresist film34, it is determined if the photoresist film is properly aligned. Specifically, it is determined if the opening36has an appropriate critical dimension (CD) and if it lies over the opening24in the hard mask22and, accordingly, the contact structure14. If the opening36is not properly aligned with the opening24and contact structure14, then the photoresist film34is removed and a new photoresist film34is deposited, patterned, and checked for alignment with the opening24and contact structure14

After the photoresist film34is determined to be in proper alignment, the process continues with the etching of the pattern transfer layer32to form a patterned or etched pattern transfer layer40inFIG. 3. Specifically, the pattern transfer layer32is etched with an anisotropic etchant while using the patterned photoresist film34as a mask. As shown, portions42of the planarization layer30are exposed by the pattern transfer layer40.

InFIG. 4, an anisotropic etch, such as a reactive ion etch (RIE), is performed on the planarization layer30using the pattern photoresist film34and the pattern transfer layer40as an etch mask to form a trench44through the planarization layer30. As shown, the trench44is aligned so that it fully lands on the ILD material20and partially on the hard mask22. As a result, an exposed portion50of the ILD material20is formed with a width smaller than the patterned opening in the pattern transfer layer40.

Because the patterned photoresist film34is aligned with the contact structure14before etching of underlying layers are commenced, the trench44and exposed portion50of the ILD material20are aligned with the contact structure14so that a self-aligned via process properly exposes the contact structure14. A self-aligned via etch process is performed to etch the exposed portion50of the ILD material20and form a self-aligned via60in the ILD material20. The self-aligned via etch process uses the hard mask22and the planarization layer30as masks. An exemplary self-aligned via etch process is an anisotropic RIE process.

InFIG. 6, the photoresist film34, pattern transfer layer40, and planarization layer30may be removed after the self-aligned via etch process. The removal of the photoresist film34, pattern transfer layer40, and planarization layer30may be performed with a single process, such as an ashing process. Such a process does not remove the hard mask22or underlying layers. As a result of the single process removal of the photoresist film34, pattern transfer layer40, and planarization layer30, fabrication method steps are minimized. The resulting structure of the partially fabricated integrated circuit10is shown inFIG. 6and includes the hard mask22, ILD material20, the dielectric liner18, the dielectric material16, self-aligned via60, the contact structure14, and the semiconductor substrate12. The self-aligned via60is in alignment with the contact structure14. As shown, the hard mask22exposes a non-etched portion62of the ILD material20.

InFIG. 7, a trench etch process is performed to form a trench66in the ILD material20. As shown, the non-etched portion62of the ILD material20lying under opening24in the hard mask22is etched to form the trench66. InFIG. 8, a conductor70, such as tungsten or other suitable material, is then deposited in the self-aligned via60and trench66in accordance with conventional processing to form electrical contacts to the contact structure14and to form interconnect structures.

FIG. 9provides a flow chart for the method described inFIGS. 1-8. As shown, the exemplary method100begins after patterning the hard mask22over the ILD material20with the step102of depositing the planarization layer30overlying the patterned hard mask22. Then, a pattern transfer layer32is deposited overlying the planarization layer30in step104. In step106, a photoresist film34is coated onto the pattern transfer layer32and is patterned with a photolithography process. After step106, the partially completed integrated circuit10has the structure shown inFIG. 2.

In step108, it is determined if the critical dimension (CD) of the patterned photoresist film34is proper and if the opening(s) formed in the patterned photoresist film34are on target, i.e., aligned with the contact structure14. If no, step110removes the photoresist film34by stripping, and the process repeats step106. If the patterned photoresist film34has an appropriate CD and is on target with the contact structure14, then the process continues with step112where the pattern transfer layer32is etched, using the photoresist film34as a mask to form a patterned or etched pattern transfer layer40. The structure of the partially completed integrated circuit10at this stage is shown inFIG. 3.

The process continues with etching the planarization layer30using the pattern transfer layer40as a mask in step114. After this step, the partially completed integrated circuit10has the structure shown inFIG. 4. At step116, the ILD material20is etched in accordance with the processes described in relation toFIG. 5. Then, the photoresist film34is stripped in step118. In an exemplary embodiment, the patterned photoresist film34, the pattern transfer layer40, and the planarization layer30are simultaneously ashed by a process for which the hard mask22and underlying layers are not ashed. Thus, the ashing process can be performed to simultaneously remove the patterned photoresist film34, the pattern transfer layer40, and the planarization layer30while leaving the hard mask22and underlying layers intact for trench formation. In step120, a trench etch is performed, resulting in the structure of the partially completed integrated circuit10shown inFIG. 7. Thereafter, metal deposition is performed to complete contact and interconnect structures as shown inFIG. 8.

Accordingly, methods for fabricating integrated circuits with improved patterning schemes have been described. Such methods described herein provide for more efficient processing. For example, embodiments herein provide for efficient reworking to attain proper alignment by only requiring removal of the photoresist film, re-deposition of the photoresist film, and re-patterning of the photoresist film, rather than reworking the underlying layers. Embodiments herein avoid use of an antireflective coating and of multiple removal processes used in conventional processing.