Frequency crossing detection using opposing pattern detectors

A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut—1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut—2). The selected frequency source is compared to fpdOut—1 and fpdOut—2 signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to phase-locked loop (PLL) circuitry and, more particularly, to a system and method for simply determining the frequency of a signal with respect to a known reference frequency.

2. Description of the Related Art

In many communication applications, the most critical process in determining device performance involves ascertaining the relationship among key frequencies. This complex process limits device performance with regard to speed of acquisition, power consumption, and integrated circuit (IC) die area.

In all PLLs, an internal oscillator is calibrated such that its frequency is exactly identical to an external reference. Modern PLLs consist of an oscillator which can be digitally calibrated. This oscillator is called a digitally calibrated oscillator (DCO). A mechanism is required to identify a digital control value that produces a DCO oscillation with frequency close to the external reference. The mechanism, called frequency band search (FBS), must be simple, such that implementation is cost competitive. Speedy convergence is also highly desirable for fast PLL lock time.

FIG. 8is a flowchart illustrating a process for acquiring a frequency band in a multi-band communication system (prior art). The PLL is ubiquitous in communication systems. Communication devices, e.g., serializer/deserializer (SERDES) devices, that operate over a wide range of frequencies require several PLLs or DCOs.

The frequency band search begins in Step800. In Step802a comparison is performed between the frequency of the reference and a divided-down oscillator frequency. The result is then analyzed in Step804. If the reference frequency is close enough to the divided-down oscillator frequency, FBS concludes in Step808. Otherwise, the digital control of the oscillator is adjusted in Step810and a comparison is performed again (Step802). A frequency band search across a band of several oscillators can be very time consuming, especially if the communication frequency band is unknown.

FIG. 1is a schematic block diagram of a frequency counter (prior art). When reset b is released, both counters start to accumulate. The most significant bit (MSB) of each counter rises when the corresponding clock finishes counting 27clock cycles. If the compClk is faster than refClk in frequency, compMSB rises before refMSB. The Edge Detector100identifies the relative time of the rising edge of compMSB and refMSB. CompFast rises if compClk is faster than refClk. However, this method requires a large number of clock cycles to make a comparison, especially if the two clocks are close in frequency. Long measurement times slow PLL frequency acquisition.

Going forward, fast lock times with large pull-in range bandwidths are going to be a required feature of modern PLL and clock and data recovery (CDR) for wired and wireless serializer/deserializer (SerDes) applications. In wired SerDes applications, the demand for multiple protocols with dynamic adaptation has pushed the fast lock requirement so that network protocol change can occur in real-time. In wireless SerDes, the demand for a new generation of data wireless networks has pushed the fast lock requirement so that data can be adapted with multiple rates.

It would be advantageous if there was a means to identify an input signal with an unknown frequency within a narrow frequency range (band), for the purpose PLL/CDR frequency acquisition applications.

SUMMARY OF THE INVENTION

Disclosed herein is a window sampling pattern means to efficiently compare the frequency between two clock signals. It enables a deterministic mechanism for phase-locked loop (PLL) convergence with a fast lock time. Unlike complex prior arts methods that require counters with many bits to accomplish frequency comparison, the simplest form of the system disclosed herein can be enabled with only 3 flip flops. The system also reduces the convergence time for a PLL, which is an extremely important requirement in many modern communication devices. The system takes advantage of cycle slipping between the two clocks, making the system 100 times faster than the conventional counter method when the signals being compared are close in frequency. By bounding the search between high frequency and low frequency window samplers, and incrementally stepping across the range of possible frequencies, the frequency band occupied by input signal is quickly determined. By reducing the time and integrated circuit (IC) area devoted to frequency locking and acquisition functions, IC power consumption is minimized.

Accordingly, a method is provided for matching a signal (compClk) with an unknown frequency to a particular frequency band in a multiband communications device. The method accepts a compClk signal having an unknown frequency. A frequency source is selected from a plurality of frequency sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected frequency source. A high frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is greater than the reference clock frequency, the high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut_1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut_2). The selected frequency source is compared to fpdOut_1and fpdOut_2signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.

More explicitly, the method iteratively selects adjacent frequency sources from the plurality of frequency sources and makes fpdOut_1and fpdOut_2comparisons. For example, the highest band frequency source may be initially selected. If an fpdOut_2signal is detected, it is an indication that the compClk frequency is lower than the reference clock reference, and the frequency source associated with the fpdOut_2signal is recorded. Then, a lower band frequency source adjacent the previously selected frequency source is selected. If an fpdOut_1signal is detected, it is an indication that the compClk frequency is higher than the reference clock. Then the frequency source associated with the fpdOut_1signal is recorded and the search ends.

Additional details of the above-described method and a window sampling system for comparing a signal with an unknown frequency to a reference clock are provided below.

DETAILED DESCRIPTION

FIGS. 2A and 2Bare schematic block diagrams of a window sampling system for comparing a signal with an unknown frequency to a reference clock. The system200ofFIG. 2Acomprises a pattern modulator202having an input on line204to accept a compClk signal and an output on line206to supply a test window. The test window has a period equal to n compClk periods, where n is an integer greater than 1. A pattern detector208has an input on line206to accept the test window and an input on line210to accept a reference clock. The pattern detector208contrasts the test window with the reference clock. In response to failing to fit n reference clock periods inside the test window, the pattern detector208supplies a frequency pattern detector output signal (fpdOut) on line212indicating that the frequency of the compClk is greater than the reference clock frequency.

In one aspect, the pattern modulator202supplies a test window having a duty cycle with a first polarity (K) of p compClk periods and with a second polarity (B) of x consecutive compClk periods, where x+p=n, as follows:

This pattern means that there are p consecutive K modulation periods followed by x consecutive B modulation periods.

Alternately, the test window may be defined with the following notation:

{Ki, Bj}, where i varies from 1 to p, and j varies from 1 to x.

FIG. 3is a diagram depicting some exemplary, test windows. Test window A is created by setting p=1 and x=1 (n=2), creating the pattern (K1, B1)=(1, 0). Test window B is created by setting p=1 and x=3 (n=4), creating the pattern (K1, B1, B2, B3)=(1, 0, 0, 0). In this example, the K polarity is associated with the high portion of the duty cycle and B is associated with the low portion. However, the high and low polarities may be associated with B and K, respectively, and the order of polarity within the duty cycle may be reversed.

Returning toFIG. 2A, the pattern detector contrasts the test window with the reference clock by sampling the polarity of modulations within the test window with the reference clock. In response to detecting a pattern of (K1. . . K(<zp)) or (B1. . . B(<zx)), where z is equal to the number of reference clock sampling edges, a fpdOut signal is supplied indicating that the frequency of the compClk is greater than the reference clock frequency. The test window may be sampled with the reference clock rising or falling edge (z=1), or with both edges (z=2).

Alternately, the pattern (K1. . . K(<zp)) may be represented as follows:

{Ki}, where i varies from 1 to less than zp.

In the case where zp=1, no K modulation periods are sampled. In other words, i=0.

Likewise, the pattern (B1. . . B(<zx)) may be represented as follows:

{Bj}, where j varies from 1 to less than zx. In the case where zx=1, no B modulation periods are sampled. In other words, j=0.

The pattern (K1. . . K(<zp)) represents the case where at least a portion of the K cycle of the test window fails to be sampled. If the compClk frequency is close to the reference clock frequency, the B cycle of the test window (B1. . . Bzx) may be fully sampled, even if the K modulation periods are not completely sampled. If the compClk is much faster, the B cycle may or may not be fully sampled.

Likewise, the pattern (B1. . . B(<zx)) represents the case where at least a portion of the B cycle of the test window fails to be sampled. If the compClk frequency is close to the reference clock frequency, the K cycle of the test window (K1. . . Kzp) may be fully sampled, even if the B modulation periods are not completely sampled. In the compClk is much faster, the K cycle may or may not be fully sampled.

It should be understood that if the reference clock is supplied to the pattern modulator on line210, and the compClk (with an unknown frequency) is supplied to the pattern detector on line204, the system can be used to determine if the compClk frequency is less than the reference clock frequency, seeFIG. 2B.

FIG. 4is a diagram depicting some sampling examples where the compClk frequency is faster than the reference clock. As inFIG. 3, test window A is creating by setting p=1 and x=1 (n=2), creating the pattern (K1, B1)=(1, 0). The compClk frequency is significantly faster than the frequency of reference clock A, and 3 consecutive patterns of (B1. . . B(zx−1))=(B0) are shown. Since z=1 and x=1, this represents a pattern where the B cycle fails to be sampled in three consecutive test windows. Alternately stated, only the K cycle of the test window (K1) is sampled in the three test windows.

Reference clock B has a frequency equal to the compClk frequency, so that the non-varying pattern of (K1. . . Kzp, B1. . . Bzx) is shown. Since p=1 and x=1, the pattern can also be represented as (K1, B1) in this example.

FIG. 5is a schematic block diagram depicting a first variation of the window sampling system ofFIG. 2A. In this aspect, pattern detector208includes a first detector500having an input to accept the test window on206and an input on line210to accept the reference clock. The first detector500samples the polarity of modulation within the test window with an edge of the reference clock with either the rising edge or the falling edge, and in response to detecting the pattern (K1. . . K(<zp)), supplies a first detector signal on line502.

A second detector504has an input on line206to accept the test window and an input on line210to accept the reference clock. The second detector504samples the polarity of modulation within the test window with one edge of the reference clock, and in response to detecting the pattern (B1. . . B(<zx)), supplies a second detector signal on line506. A logical OR circuit508has inputs on lines502and506to accept the first and second detector signals, respectively, and an output on line212to supply the fpdOut signal.

FIG. 6is a schematic block diagram depicting a second variation of the window sampling system ofFIG. 2A. In this aspect a first sampler circuit600has a signal input on line206ato accept the test window and a clock input on line210to accept the reference clock. The sampler circuit600samples the polarity of modulation of the test window with the reference clock rising edge and/or falling edge, and supplies a test window to the pattern detector on line206bhaving a an edge aligned with a reference clock edge. In one aspect, the first sampler600can be enabled using a latch or flip flop. Note: the first sampler can be implemented with the systems depicted inFIGS. 2A,5, and7.

FIG. 7is a schematic block diagram depicting a third variation of the window sampling system ofFIG. 2A. In this aspect, the pattern modulator uses values of p=2 and x=2 (n=4). The pattern detector208includes a second sampling circuit700having a signal input on line206to accept the test window and a clock input on line210to accept the reference clock. The second sampling circuit700samples the polarity of modulation within the test window with one edge (rising or falling) of the reference clock and supplies a first signal at an output on line702. If the first sampler600is used, as shown, the second sampling circuit700and first sampler must sample the test window with a common edge of the reference clock.

A third sampling circuit704has a signal input on line702to accept the first signal and a clock input on line210to accept the reference clock. The third sampling circuit704samples the polarity of the first signal with one edge of the reference clock, and supplies a second signal at an output on line706. The third sampling circuit704and first sampler600must sample the test window with a common edge of the reference clock.

A first exclusive-OR (XOR) gate708has inputs on lines206and702to accept the test window and the first signal, respectively, and an output on line710to supply a third signal. A second XOR gate712has inputs on lines702and706to accept the first and second signals, respectively, and an output on line714to supply a fourth signal. An AND gate716has inputs on lines710and714to accept the third and fourth signals, respectively, and an output on line212to supply the fpdOut signal. Note: the first sampler600is shown in this example, but it is not required.

Alternately stated, a non-varying detection of the pattern (1, 1, 0, 0) indicates that the reference clock frequency is equal to the compClk, but a pattern of (K1, B1, B2)=(1, 0, 0), which corresponds to a detected pattern of 010, indicates that the compClk frequency is faster because the K cycle of the test window is only sampled once. A pattern of (K1, K2, B1)=(1, 1, 0), which corresponds to a detected pattern of 101, indicates that the compClk frequency is faster because the B cycle of the test window is only sampled once.

FIG. 9is a schematic block diagram of a multiband communications device with a system for matching a signal (compClk) with an unknown frequency to a particular frequency band. The system900comprises a plurality of selectable frequency sources902collectively covering a range of frequency bands, where each frequency source supplies a reference clock within a corresponding frequency band. Shown are frequency sources902-0through902-m, where m is an integer variable not limited to any particular value. A multiplexer (MUX)904is shown as the frequency band selector, but the system can be enabled using other means known in the art. In one aspect, the frequency source may be a voltage controlled oscillator (VCO) that supplies a reference clock with a frequency about in the middle of its frequency range.

It should be understood that the range of frequencies associated which each VCO may vary in response to fabrication processes, and variations in voltage and temperature, often referred to as Process, Voltage, Temperature (PVT) changes. Therefore, a real-time search of the frequency ranges may be necessary to compensate for PVT change.

A high frequency (HF) window sampler906has an input on line908to accept a compClk signal with an unknown frequency, and input on line910to accept a reference clock from a selected frequency source. Due to PVT changes, the exact frequency of the reference clock may not be known. The high frequency window sampler has an output on line912to supply a first frequency pattern detector output signal (fpdOut_1) indicating that the frequency of the compClk is greater than the reference clock frequency. The high frequency window sampler may be enabled using any of the designs described above in the explanation ofFIGS. 2A,5,6, or7.

Using the system ofFIG. 2Aas an example, the high frequency window sampler may includes a pattern modulator202having an input on line204to accept the compClk signal and an output on line206to supply a test window with a period equal to n compClk periods, where n is an integer greater than 1. A pattern detector208has an input on line206to accept the test window and an input on line210to accept the reference clock. The pattern detector208contrasts the test window with the reference clock, and in response to failing to fit n reference clock periods inside the test window, supplies the fpdOut (fpdOut_1) signal. The fpdOut_1signal indicates that frequency of the compClk is greater than the reference clock frequency.

Returning toFIG. 9, a low frequency window sampler914has an input on line908to accept the compClk signal, and input on line910to accept the reference clock. The low frequency window sampler914has an output on line916to supply a second frequency pattern detector output signal (fpdOut_2) indicating that the frequency of the compClk is less than the reference clock frequency. The low frequency window sampler may be enabled using any of the designs described above in the explanation ofFIGS. 2B,5,6, or7, by reversing the compClk and refClk connections.

Taking the system ofFIG. 2Bas an example, the low frequency window sampler may be enabled with the pattern modulator202having an input on line210to accept the reference clock and an output on line206to supply a test window with a period equal to n reference clock periods, where n is an integer greater than 1. In contrast to the system ofFIG. 2A, the reference clock is supplied to the pattern modulator and the compClk is supplied to the pattern detector. The pattern detector208has an input to accept the test window on line206and an input on line204to accept the compClk signal. The pattern detector contrasts the test window with the compClk signal, and in response to failing to fit n compClk periods inside the test window, supplies the fpdOut_2signal on line212, indicating that the frequency of the compClk is lower than the reference clock frequency. Note: since the compClk and reference clock signals are reversed from the high frequency window sampler, the fpdOut_2indicates the opposite polarity of compClk with respect to the reference clock.

Returning toFIG. 9, a tuning module918has an output on line920to select a frequency source, and inputs on lines912and916to accept, respectively, the fpdOut_1and fpdOut_2signals. The tuning module918determines if the compClk frequency coarsely matches the reference clock frequency of a selected frequency source and supplies a frequency band matching signal at an output on line922in response to determining the coarse match. In one aspect, the frequency band matching signal initiates a frequency acquisition and tracking process.

The tuning module918determines the coarse match between the compClk frequency on line908and the reference clock frequency on line910by iteratively selecting adjacent frequency sources902from the plurality of frequency sources. For example, the tuning module918may determines the coarse match between the compClk frequency and the reference clock frequency by initially selecting the highest band frequency source (e.g.,902-0). If an fpdOut_2signal is detected on line916, indicating that the compClk frequency is lower than the reference clock reference, the tuning module918records the frequency source associated with the fpdOut_2signal and selects a lower band frequency source (e.g.,902-1) adjacent the previously selected frequency source (902-0). If an fpdOut_1signal is detected on line912, indicating that the compClk frequency is higher than the reference clock, the tuning module912records the frequency source associated with the fpdOut_1signal and ends the search.

A typical search may include the iterative selection of several incrementally lower frequency sources before the fdpOut_1signal is detected. Once the fpdOut_1is detected, the tuning module918accesses the identity of a first frequency band associated with the last recorded fpdOut_2signal. The tuning module918also accesses the identity of a second frequency band associated with the recorded fpdOut_1signal. Then, the tuning module selects a frequency band about midway between the first and second frequency bands, and sends the frequency band matching signal on line922. Note: the tuning module918may select either the first or second frequency bands if the first frequency band is adjacent the second frequency band, as either band is likely to be closer in frequency to the compClk signal.

Alternately, the tuning module918determines the coarse match between the compClk frequency and the reference clock frequency by initially selecting a lowest band frequency source (e.g.,902-m). If an fpdOut_1signal is detected, indicating that the compClk frequency is greater than the reference clock reference, the tuning module records the frequency source associated with the fpdOut_1signal and selects a higher band frequency source (e.g.,902-(m-1)) adjacent the previously selected frequency source. If an fpdOut_2signal is detected, indicating that the compClk frequency is lower than the reference clock, the tuning module918records the frequency source associated with the fpdOut_2signal and ends the search.

In a manner similar to the previous example, the tuning module918accesses the identity of a first frequency band associated with the last recorded fpdOut_1signal, and accesses the identity of a second frequency band associated with the recorded fpdOut_2signal. The tuning module selects a frequency band about midway between the first and second frequency bands, and sends the frequency band matching signal on line922. The tuning may be implemented as software, firmware, or hardware. As software, the tuning module would be a sequence of instructions stored in a non-transitory memory and executed by a processor. As hardware, the tuning module may be implemented in a dedicated integrated circuit or field programmable gate array (FPGA). High speed applications require a hardware (hardwired logic) implementation. For lower speed, firmware can be used. Otherwise, the tuning module is implemented as software.

Functional Description

FIGS. 10A and 10Bare flowcharts illustrating a method for matching a signal (compClk) with an unknown frequency to a particular frequency band in a multiband communications device. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. Generally however, the steps are performed in numerical order. The method starts at Step1000.

Step1002accepts a compClk signal having an unknown frequency. Step1004selects a frequency source from a plurality of frequency sources collectively covering a range of frequency bands. Step1006supplies a reference clock from the selected frequency source. In Step1008a high frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is greater than the reference clock frequency, in Step1010the high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut_1). In Step1012a low frequency window sampler compares the compClk signal with the reference clock. Step1012may be performed simultaneously with Step1008. If the frequency of the compClk is less than the reference clock frequency, in Step1014the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut_2). Step1016compares the selected frequency source to fpdOut_1and fpdOut_2signals, and Step1018determines if the selected frequency source coarsely matches the compClk frequency.

In one aspect, selecting the frequency source in Step1004includes iteratively selecting adjacent frequency sources from the plurality of frequency sources. For example, Step1004may initially select the highest band frequency source. Then, comparing the selected frequency source to the fpdOut_1and fpdOut_2signals in Step1016includes substeps. If an fpdOut_2signal is detected, indicating that the compClk frequency is lower than the reference clock reference, Step1016arecords the frequency source associated with the fpdOut_2signal, and Step1016bselects a lower band frequency source adjacent the previously selected frequency source. If an fpdOut_1signal is detected, indicating that the compClk frequency is higher than the reference clock, Step1016crecords the frequency source associated with the fpdOut_1signal, and Step1016dends the search.

Determining if the selected frequency source coarsely matches the compClk frequency in Step1018may include the following substeps. Step1018aaccesses the identity of a first frequency band associated with the last recorded fpdOut_2signal. Step1018baccesses the identity of a second frequency band associated with the recorded fpdOut_1signal. Step1018cselects a frequency band about midway between the first and second frequency bands. In one aspect, selecting the midway frequency band in Step1018cmay include selecting either the first or second frequency bands if the first frequency band is adjacent the second frequency band.

Alternately, Step1004may initially select the lowest band frequency source. Then, comparing the selected frequency source to the fpdOut_1and fpdOut_2signals may include the following substeps. If an fpdOut_1signal is detected, indicating that the compClk frequency is greater than the reference clock reference, Step1016erecords the frequency source associated with the fpdOut_1signal. Step1016fselects a higher band frequency source adjacent the previously selected frequency source. If an fpdOut_2signal is detected, indicating that the compClk frequency is lower than the reference clock, Step1016grecords the frequency source associated with the fpdOut_2signal, and Step1016dends the search.

Then, determining if the selected frequency source coarsely matches the compClk frequency may include the following substeps. Step1018daccesses the identity of a first frequency band associated with the last recorded fpdOut_1signal. Step1018eaccesses the identity of a second frequency band associated with the recorded fpdOut_2signal. Step1018cselects a frequency band about midway between the first and second frequency bands.

In another aspect, the high frequency window sampler supplying fpdOut_1may perform the follow substeps associated with Step1010. In Step1010aa pattern modulator accepts the compClk signal. In Step1010bthe pattern modulator supplies a test window with a period equal to n compClk periods, where n is an integer greater than 1. In Step1010ca pattern detector accepts the test window. In Step1010dthe pattern detector accepts the reference clock. In Step1010ethe pattern detector contrasts the test window with the reference clock. In response to failing to fit n reference clock periods inside the test window, Step1010fsupplies the fpdOut_1signal indicating that the frequency of the compClk is greater than the reference clock frequency.

The low frequency window sampler supplying fpdOut_2may perform the following substeps associated with Step1014. In Step1014aa pattern modulator accepts the reference clock. In Step1014bthe pattern modulator supplies a test window with a period equal to n reference clock periods, where n is an integer greater than 1. In Step1014ca pattern detector accepts the test window. In Step1014dthe pattern detector accepts the compClk signal. In Step1014ethe pattern detector contrasts the test window with the compClk. In response to failing to fit n compClk periods inside the test window, Step1014fsupplies the fpdOut_2signal indicating that the frequency of the compClk is lower than the reference clock frequency.

FIG. 11is a flowchart depicting an alternate aspect of the method for matching the compClk signal to a particular frequency band. The method begins with a reset in Step1100. In Step1102the maximum frequency band algorithm is selected. In Step1104the reference clock from the initial frequency band is supplied. A sufficient measurement time is allocated in Step1106. If fpdOut_2is detected in Step1114, the band is recorded in Step1116. If fpdOut_2is not detected, the method returns to Step1104where the frequency band is decremented. If fpdOut_1is detected in Step1108, the band is recorded in Step1110, and the band is held in Step1112. Step1118analyzes the recorded band cross-referenced to the fpdOut_1and fpdOut_2signals, and the closest band to the input signal is selected in Step1120.

A system and method have been provided for matching an unknown frequency to a particular frequency band using a window sampling method. Particular circuits and process steps have been used to illustrate the invention, but the invention is not necessarily limited to these examples. Other variations and embodiments of the invention will occur to those skilled in the art.