Trench MOSFET having trench contacts integrated with trench Schottky rectifiers having planar contacts

An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability.

FIELD OF THE INVENTION

This invention relates generally to the cell structure and device configuration of semiconductor devices. More particularly, this invention relates to an improved trench MOSFET configuration having trench contacts integrated with trench Schottky rectifiers having planar contacts.

BACKGROUND OF THE INVENTION

The trench Schottky rectifiers have been added externally in parallel to a semiconductor power device, e.g., a power trench MOSFET device for higher efficiency DC/DC applications. In parallel with the parasitic PN body diode, the trench Schottky rectifier acts as clamping diode to prevent the body diode from turning on. Therefore, many kinds of configuration have been proposed in prior arts to integrate the trench MOSFET and the trench Schottky rectifier on a single substrate.

FIG. 1Ashows the side cross-section of an integration configuration of a prior art (U.S. Pat. No. 6,351,018) wherein both trench MOSFET and trench Schottky rectifier are sharing a common trench gate. As shown inFIG. 1A, The disclosed integration configuration is formed on an N doped substrate102. A plurality of trenches are etched inside the substrate102and filled with doped poly within trenches to serve as trench gates106and106′ over a layer of gate oxide104. Between trench gates106′, trench Schottky rectifier110is formed with a space width of W. Near the top surface of P well regions108in trench MOSFET, N+ source regions112are implanted adjacent to the sidewalls of trench gates. Body regions114heavily doped with P doping type are formed inside the P well regions108. Metal layer120is connected to source regions112, body regions114in trench MOSFET and is connected to anode of trench Schottky rectifiers via planar contacts116and118, respectively.

Another integration configuration was proposed in U.S. Pat. No. 6,593,620 where trench MOSFET and trench Schottky rectifier have separated trench gates, as shown inFIG. 1B. The integration configuration comprising a DMOS transistor220and a trench Schottky rectifier222further includes an N+ substrate200onto which a lighter N doped epitaxial layer202is grown. A plurality of trench gates210are formed into the epitaxial layer202with gate oxide206padded on the filling-in material. The DMOS transistor220further comprises P body region204extending between trench gates210with N+ source regions212near its top surface adjacent to the sidewalls of trench gates. Metal A metal layer216is connected to source regions212, body regions204in DMOS transistor and is connected to anode of trench Schottky rectifier via planar contact. An insulating layer235is deposited on top of the trench gates210of the DMOS transistor220to isolate the metal layer216from the trench gates210. On the rear side of wafer, metal layer230is deposited to act as a common drain contact for DMOS transistors and as a common cathode electrode for trench Schottky rectifiers.

Both structures mentioned above can achieve the integration of trench MOSFET and trench Schottky rectifier on a single substrate, but it's should be noticed that, planar contacts are employed in both trench MOSFET and trench Schottky rectifier to contact the source regions and the body regions with source metal, and to contact the anode with anode metal, respectively. Especially for trench MOSFET, the planar contact will limit device shrinkage because that, the planar contact occupies a large area, resulting in a high specific on-resistance in trench MOSFET.

Another constraint of the prior art is that, please refer toFIGS. 1A and 1B, metal step coverage of the prior arts will become poor if single metal is used to fill the planar contact when the planar contact dimension is shrunk.

Accordingly, it would be desirable to provide new and improved device configuration to avoid the high specific on-resistance caused by planar contact in trench MOSFET while having a better metal step coverage capability.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide new and improved device configuration to solve the problems discussed above.

One aspect of the present invention is that, trench contact is used in trench MOSFET portion for source-body trench contact. By employing the source-body trench contact, the devices are able to be shrunk to achieve a low specific on-resistance for trench MOSFET, therefore solving the main problem.

Another aspect of the present invention is that, planar contact is provided for trench gate connection, resulting a better metal step coverage capability than prior art, and on the other hand, avoiding gate-drain shortage caused by over-etching when using trench contact for shallow trench gate.

Another aspect of the present invention is that, W (tungsten) plugs are filled into all contact trenches, including trench contacts and planar contacts, to act as contact material, and therefore improves the metal step coverage and further enhances cell density for on-resistance reduction.

Briefly, in a preferred embodiment, as shown inFIG. 2, the present invention discloses an integration configuration in parallel with a wider common trench gate formed on a substrate heavily doped with a first semiconductor doping type, e.g., N+ dopant. Onto the substrate, an epitaxial layer lighter doped with the same doping type as substrate is grown, inside which a plurality of trench gates and a wider common trench gate are formed with a gate oxide between filling-in material and the inner surface of gate trenches. The integration configuration further comprises: a trench MOSFET and a trench Schottky rectifier. The trench MOSFET further comprises: body regions of a second semiconductor doping type, e.g., P dopant, extending between trench gates with source regions heavily doped with a first semiconductor doping type near its top surface; source-body trench contacts filled with W plugs padded with a barrier layer of Ti/TiN or Co/TiN or Mo/TiN penetrating through an thick oxide interlayer and the source regions, and extending into the body regions; a body contact resistance reduction area heavily doped with the second doping type around the bottom of each said source-body trench contact to further reduce contact resistance. The trench Schottky rectifier further comprises: planar contacts filled with W plugs padded with the barrier layer penetrating through the thick oxide interlayer to the top surface of the epitaxial layer between trench gates. In common trench gate portion, the planar gate contact is provided penetrating through the thick oxide interlayer and touching to the top surface of the common trench gate. Above the thick oxide interlayer and said W plugs, a resistance-reduction metal layer of Ti or Ti/TiN is deposited and then a metal layer of Al alloys or Cu. The metal layers are finally patterned to form gate metal for the common trench gate and source metal for trench MOSFET which is also functioning as anode metal for trench Schottky rectifier. The gate metal is connected to the common trench gate via said planar gate contact, the source metal for trench MOSFET is connected to the source regions and the body regions via said source-body trench contacts, and the anode metal for trench Schottky rectifier is connected to the anode via said planar contacts. Especially, the trench gates in trench Schottky rectifier is not shorted with the anode.

Briefly, in another preferred embodiment, as shown inFIG. 3, the present invention discloses an integration configuration in parallel with a wider trench gate for trench MOSFET gate connection, and the disclosed configuration is formed on a substrate heavily doped with a first semiconductor doping type, e.g., N+ dopant. Onto the substrate, an epitaxial layer lighter doped with the same doping type as substrate is grown, inside which a plurality of trench gates and a wider trench gate for trench MOSFET gate connection are formed with a gate oxide between filling-in material and the inner surface of gate trenches. The integration configuration further comprises: a trench MOSFET and a trench Schottky rectifier. The trench MOSFET further comprises: body regions of a second semiconductor doping type, e.g., P dopant, extending between trench gates with source regions heavily doped with a first semiconductor doping type near its top surface adjacent to the sidewalls of the trench gate; source-body trench contacts filled with W plugs padded with a barrier layer of Ti/TiN or Co/TiN or Mo/TiN penetrating through an thick oxide interlayer, the source regions and extending into the body regions; a body contact resistance reduction area heavily doped with the second doping type around the bottom of each said source-body trench contact to further reduce contact resistance. The trench Schottky rectifier further comprises: planar contacts filled with W plugs padded with the barrier layer penetrating through the thick oxide interlayer and touching to the top surface of the epitaxial layer and the top surface of the trench gates to contact trench gates in trench Schottky rectifier with its anode. In the wider trench gate portion which is for trench MOSFET gate connection, a planar gate contact is provided penetrating through the thick oxide interlayer and touching to the top surface of the wider trench gate for trench MOSFET gate connection. Above the thick oxide interlayer and the W plugs, a resistance-reduction metal layer of Ti or Ti/TiN is deposited and then metal layer of Al alloys or Cu. The metal layers are finally patterned to form gate metal for trench MOSFET gate connection and source metal for trench MOSFET which is also functioning as anode metal for trench Schottky rectifier. The gate metal is connected to trench gate for trench MOSFET gate connection via said planar gate contact, the source metal for trench MOSFET is connected to the source regions and the body regions via said source-body trench contacts, and the anode metal for trench Schottky rectifier is connected to trench gate in trench Schottky rectifier and the anode via said planar contacts. Especially, the trench gates in trench Schottky rectifier is not connected with the trench gate in trench MOSFET but shorted with the anode.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer toFIG. 2for a preferred embodiment of the present invention where an N-channel trench MOSFET210is integrated with a trench Schottky rectifier220in parallel with a wider common trench gate. The integrated configuration is formed on an N+ substrate200onto which a lighter N doped epitaxial layer202is grown. Into the epitaxial layer202, a plurality of gate trenches and a wider gate trench for common trench gate are etched and filled with doped poly padded with a layer of gate oxide206to serve as trench gates211for trench MOSFET210and trench Schottky rectifier220, and a wider trench gate211′ for common trench gate, respectively. In trench MOSFET210, P body regions204are extending between two adjacent trench gates211with N+ source regions208near the top surface; source-body trench contacts214filled with W plug which is padded with a barrier layer213of Ti/TiN or Co/TiN or Mo/TiN are formed by penetrating through a thick oxide interlayer215and the source regions208, and extending into the P body regions204; p+ body contact resistance reduction areas212are implanted around the bottom of each said source-body trench contact to further reduce contact resistance. In trench Schottky rectifier220, planar contacts216filled with W plug which is padded with the barrier layer213are formed by penetrating through the thick oxide interlayer215and touching to the top surface of the epitaxial layer202between trench gates211or further extending into the epitaxial layer with a depth in the epitaxial layer less than 0.1 um due to dry over etching of the thick oxide interlayer. In common trench gate portion, planar gate contact217filled with W plug which is padded with the barrier layer213is formed by penetrating through the thick oxide interlayer215and touching to the top surface of the wider common trench gate211′ or further extending into the doped poly with a depth in the doped poly less than 0.2 um due to dry over etching of the thick oxide interlayer. Onto a resistance-reduction metal layer218of Ti or Ti/TiN which is deposited over the thick oxide interlayer215and said W plug, a metal layer219and219′ composed of Al alloys or Cu are formed. Specifically, the metal layer219is serving as source metal for trench MOSFET210and also the anode metal for trench Schottky rectifier220, metal layer219′ is serving as common gate metal for both trench MOSFET210and trench Schottky rectifier220.

Please refer toFIG. 3for another preferred embodiment of the present invention where an N-channel trench MOSFET310is integrated with a trench Schottky rectifier320in parallel with a wider trench gate for trench MOSFET gate connection. The integrated configuration is formed on an N+ substrate300onto which a lighter N doped epitaxial layer302is grown. Into the epitaxial layer302, a plurality of gate trenches and a wider gate trench are etched and filled with doped poly padded with a layer of gate oxide306to serve as trench gates311for trench MOSFET, trench gates311′ for trench Schottky rectifier and a wider trench gate311″ for trench MOSFET gate connection. In trench MOSFET310, P body regions304are extending between trench gates with N+ source regions308near its top surface adjacent to the sidewalls of trench gate311; source-body trench contacts314filled with W plug which is padded with a barrier layer313of Ti/TiN or Co/TiN or Mo/TiN are formed by penetrating through a thick oxide interlayer315and the source regions308, and extending into the P body regions304; p+ body contact resistance reduction areas312are implanted around the bottom of each said source-body trench contact to further reduce contact resistance. In trench Schottky rectifier320, planar contacts316filled with W plug which is padded with the barrier layer313are formed by penetrating through the thick oxide interlayer315and touching to the top surface of the epitaxial layer302and the top surface of trench gates311′ or further extending into the epitaxial layer302with a depth less than 0.1 um and into trench gate311′ with a depth less than 0.2 um due to dry over etching of the thick oxide interlayer315. In wider trench gate311″ portion which is for trench MOSFET gate connection, planar gate contact317filled with W which is padded with the barrier layer313is formed by penetrating through215and touching to the top surface of the wider trench gate311″ or further extending into trench gate311″ with a depth in doped poly layer less than 0.2 um due to dry over etching of the thick oxide interlayer315. Onto a resistance-reduction metal layer318of Ti or Ti/TiN which is deposited over the thick oxide interlayer315and said W plug, metal layers319and319′ composed of Al alloys or Cu are formed. Specifically, metal layer319is serving as source metal for trench MOSFET310and also the anode metal for trench Schottky rectifier320, metal layer319′ is serving as gate metal for trench MOSFET310. And different from the first embodiment, the trench gates311′ in trench Schottky rectifier in this embodiment is not connected with the trench gate in trench MOSFET but shorted with the anode.

FIGS. 4A to 4Eare a serial of exemplary steps that are performed to form the inventive integrated configuration ofFIG. 2. InFIG. 4A, an N doped epitaxial layer202is grown on an N+ substrate200. A trench mask (not shown) is employed to define a plurality of gate trenches for trench MOSFET and trench Schottky rectifier, and a wider gate trench for common trench gate. Then, these gate trenches are dry Si etched to a certain depth. After that, a sacrificial oxide layer is grown and then removed to eliminate the plasma damage may introduced during etching process. Next, a first insulation layer is deposited overlying the inner surface of all the gate trenches to serve as gate oxide206onto which doped poly is deposited within gate trenches and then etched back or CMP (Chemical Mechanical Polishing) to form trench gates211for both trench MOSFET and trench Schottky rectifier, and a wider common trench gate211′.

InFIG. 4B, a body mask (not shown) is applied to define body regions and followed by a step of P dopant Ion Implantation for the formation of P body regions204, and then a step for P body regions drive-in is carried out. After the removal of body mask, source mask (not shown) is applied to define source regions and followed by a step of N+ dopant Ion Implantation for the formation of N+ source regions308, and then a step for N+ source regions drive-in is carried out.

InFIG. 4C, the process continues with the deposition of a second insulation layer over entire front surface to act as a thick oxide interlayer215. Then, a contact mask1, as illustrated, is applied to carry out planar contact etch to open the contact trenches by applying a dry oxide etching through215. For trench Schottky rectifier, the contact trenches are etched to the front surface of the epitaxial layer between trench gates to define the planar contact trench216′ for trench Schottky rectifier. For common trench gate, the contact trench is etched to the top surface of the common trench gate211′ to define the planar contact trench217′ for common trench gate.

InFIG. 4D, after the removal of contact mask1, a contact mask2, as illustrated, is applied to carry out trench contact etch to open the contact trenches214′ for trench MOSFET by applying a dry oxide etching and a successively dry Si etching. The contact trenches214′ is penetrating through the thick oxide interlayer215and the N+ source regions208and into the P body regions204. Then, in order to form the contact area212around the bottom of each the contact trench214′, a BF2 Ion Implantation of a P dopant is carried out, and then followed by a step of RTA (Rapid Thermal Annealing, 900˜1000° C. for 15˜60 sec) to activate BF2 dopant after removing the contact mask2.

InFIG. 4E, the inner surface of all contact trenches, including contact trenches for planar contacts and trench contacts, are lined by a barrier layer213composed of Ti/TiN or Co/TiN or Mo/TiN. And a step of RTA (700˜800° C. for 15˜60 sec) is performed to form silicide. Then, onto the barrier layer213, tungsten material are deposited to fill all said contact trenches, and followed by a step of tungsten and barrier layer etching back or CMP to form source-body trench contact214for trench MOSFET, planar contact216for trench Schottky rectifier and planar gate contact217for common trench gate. Then, over entire top surface, a resistance-reduction metal layer218composed of Ti or Ti/TiN and a metal layer of Al alloys or Cu are successively deposited. After that, a metal mask (not shown) is applied to pattern the metal layer into219and219′ by dry metal etching. Especially, metal layer219is functioning as source metal for trench MOSFET and also anode metal for trench Schottky rectifier, metal layer219′ is functioning as gate metal for common trench gate.

FIGS. 5A to 5Care a serial of exemplary steps that are performed to form the inventive integrated configuration ofFIG. 3. InFIG. 5A, before the deposition of the second insulation layer, all steps are just the same as steps inFIGS. 4A and 4B. After the deposition of the second insulation layer, which is serving as the thick oxide interlayer315, a contact mask1, as illustrated, is applied to carry out planar contact etch to open the contact trenches by applying a dry oxide etching through315. For trench Schottky rectifier, the contact trench is etched to expose the front surface of epitaxial layer302and top surface of trench gates311′ to form the planar contact trench316′. For the wider trench gate, the contact trench is etched to the top surface of the wider trench gate311″ to form the planar gate contact trench317′ for trench MOSFET gate connection. InFIG. 5B, after the removal of contact mask1, a contact mask2, as illustrated, is applied to carry out trench contact etch to open the contact trenches314′ for trench MOSFET by applying a dry oxide etching and a successively dry Si etching. The contact trenches314′ is penetrating through the thick oxide interlayer315and the N+ source regions308and into the P body regions304. Then, in order to form the contact area312around the bottom of each said contact trench314′, a BF2 Ion Implantation of a P dopant is carried out, and then followed by a step of RTA (Rapid Thermal Annealing, 900˜1000° C. for 15˜60 sec) to activate BF2 dopant after removing the contact mask2.

InFIG. 5C, the inner surface of all contact trenches, including trenches for planar contacts and trench contacts, are lined by a barrier layer313composed of Ti/TiN or Co/TiN or Mo/TiN. And a step of RTA (700˜800° C. for 15˜60 sec) is performed to form silicide. Then, onto the barrier layer313, tungsten material are deposited to fill all said contact trenches, and followed by a step of tungsten and barrier layer CMP (not etching back) to form source-body trench contact314for trench MOSFET, planar contact316for trench Schottky rectifier and planar gate contact317for trench MOSFET gate connection. Then, over entire top surface, a resistance-reduction metal layer318composed of Ti or Ti/TiN and a metal layer of Al alloys or Cu are successively deposited. After that, a metal mask (not shown) is applied to pattern the metal layer into319and319′ by dry metal etching. Especially, metal layer219is functioning as source metal for trench MOSFET and also anode metal for trench Schottky rectifier, metal layer219′ is functioning as gate metal for trench MOSFET, and the trench gates311′ in trench Schottky rectifier is not connected to the trench gates in trench MOSFET but shorted with the anode.