Flash memory structure and method for forming the same

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device further includes an insulating layer formed on a sidewall of the control gate and a memory gate formed adjacent to the insulating layer. In addition, the insulating layer has a first height, and the memory gate has a second height shorter than the first height.

BACKGROUND

One of the important drivers for increased performance in computers is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. Tolerances play an important role in being able to shrink dimensions on a chip.

A flash memory cell has elements such as gate, spacers, and source and drain regions. However, controlling and shrinking the size of those elements in a flash memory cell are still challenging.

DETAILED DESCRIPTION

The making and using of various embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the various embodiments can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

Mechanisms for forming a semiconductor device structure are provided in accordance with some embodiments of the disclosure.FIGS. 1A to 1Dillustrate cross-sectional representations of various stages of forming a flash memory structure100ain accordance with some embodiments. Referring toFIG. 1A, a substrate102is provided. Substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, substrate102includes structures such as doped regions, isolation features, interlayer dielectric (ILD) layers, and/or conductive features. In addition, substrate102may further include single or multiple material layers to be patterned. For example, the material layers may include a silicon layer, a dielectric layer, and/or a doped polysilicon layer.

A polysilicon gate104is formed over substrate102in accordance with some embodiments. Polysilicon gate104may be formed by depositing a polysilicon layer over substrate102and patterning the polysilicon layer. In some embodiments, the polysilicon layer is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma enhanced CVD (PECVD), or thermal process such as furnace deposition. In some embodiments, the polysilicon layer is patterned by forming a photoresist layer over the polysilicon layer, patterning the photoresist layer, and etching the polysilicon layer. In some embodiments, the polysilicon layer is patterned by an anisotropic dry etching process.

After polysilicon gate104is formed, an insulating layer106is conformally formed over substrate102to cover polysilicon gate104, as shown inFIG. 1Ain accordance with some embodiments. In some embodiments, insulating layer106is an oxide-nitride-oxide (ONO) film. More specifically, insulating layer106includes a first oxide layer108, a nitride layer110formed over first oxide layer108, and a second oxide layer112formed over nitride layer110. Insulating layer106may be formed by CVD, although other applicable depositing processes may alternatively be used.

After insulating layer106is formed, a polysilicon layer114is conformally formed over insulating layer106, as shown inFIG. 1Ain accordance with some embodiments. In some embodiments, polysilicon layer114is formed by a thermal process such as furnace deposition, although other applicable depositing processes may alternatively be used.

Next, an etching process115is performed to remove some portions of polysilicon layer114, as shown inFIG. 1Bin accordance with some embodiments. In some embodiments, etching process115is a dry etching process. After etching process115is performed, a first polysilicon spacer116and a second polysilicon spacer116′ are formed along sidewalls of polysilicon gate104. In addition, first polysilicon spacer116and second polysilicon spacer116′ have sharp top portions117abeing close to a top portion119of polysilicon gate104.

Next, first polysilicon spacer116aand the portion of insulating layer106which is not covered by second polysilicon spacer116a′ are removed, as shown inFIG. 1Cin accordance with some embodiments. First polysilicon spacer116amay be removed by a dry etching process, and the portion of insulating layer106not covered by second polysilicon spacer116a′ may be removed by a wet etching process.

After first polysilicon spacer116ais removed, a first spacer120is formed on a sidewall of polysilicon gate104, and a second spacer120′ is formed on a sidewall of second polysilicon spacer116a′, as shown inFIG. 1Din accordance with some embodiments. Afterwards, source and drain regions126are formed in substrate102.

Next, a first silicide layer122is formed over polysilicon gate104to form a control gate128, and a second silicide layer124is formed over second polysilicon spacer116a′ to form a memory gate130ain accordance with some embodiments. In some embodiments, first silicide layer122and second silicide layer124aare made of nickel silicide, cobalt silicide, or titanium silicide. First silicide layer122and second silicide layer124may be formed in a self-aligned manner. For example, a salicide process may be performed on the top surface of the polysilicon gate104and second polysilicon spacer116a′. First, a metal layer, such as a cobalt layer, is deposited by a sputtering method on the top surface of polysilicon gate104and second polysilicon spacer116a′. Next, by performing a heat treatment using a rapid thermal annealing (RTA) method, the metal layer and polysilicon of polysilicon gate104and second polysilicon spacer116a′ are reacted to form first silicide layer122and second silicide layer124a. Afterwards, the unreacted part of the metal layer is removed.

As described above, second polysilicon spacer116a′ has sharp top portion117anear top portion119of polysilicon gate104. Therefore, first silicide layer122formed on polysilicon gate104is too close to second silicide layer124formed on second polysilicon spacer116a′, and the risk of circuit shortage between control gate128and memory gate130a(e.g. between first silicide layer122and second silicide layer124a) increases.

Accordingly, in some embodiments, an over-etching process is used to prevent such circuit shortage.FIGS. 2A to 2Dillustrate cross-sectional representations of various stages of forming a flash memory structure100bincluding over-etching polysilicon layer114in accordance with some embodiments. Some elements and manufacturing processes for forming flash memory structure100bare similar to those for forming flash memory structure100aand are not repeated herein.

Next, an over-etching process215is performed to form a first polysilicon spacer116band a second polysilicon spacer116b′, as shown inFIG. 2Bin accordance with some embodiments. Compared to etching process115, over-etching process215is performed for a longer time. Therefore, first polysilicon spacer116band second polysilicon spacer116b′ formed by over-etching polysilicon layer114are shorter than first polysilicon spacer116aand second polysilicon spacer116a′ shown inFIG. 1D. As a result, although first polysilicon spacer116band second polysilicon spacer116b′ also have slanted (or sloping) top surfaces, a top portion117bof second polysilicon spacer116b′ is relatively far from top portion119of polysilicon gate104.

Next, first polysilicon spacer116band the portion of insulating layer106which is not covered by second polysilicon spacer116b′ are removed, as shown inFIG. 2Cin accordance with some embodiments. First polysilicon spacer116bmay be removed by a dry etching process, and the portion of insulating layer106not covered by second polysilicon spacer116b′ may be removed by a wet etching process.

After first polysilicon spacer116bis removed, first spacer120is formed on a sidewall of polysilicon gate104, and a second spacer120b′ is formed on a sidewall of second polysilicon spacer116b′, as shown inFIG. 2Din accordance with some embodiments. Since second polysilicon spacer116b′ is shorter than second polysilicon spacer116a′ shown inFIG. 1D, second spacer120b′ formed on the sidewall of second polysilicon spacer116b′ is shorter than second spacer120′ shown inFIG. 1D. However, when second polysilicon spacer116b′ is too short, formation of second spacer120′ may become difficult. Afterwards, source and drain regions126are formed in substrate102.

Next, first silicide layer122is formed over polysilicon gate104to form a control gate128, and a second silicide layer124bis formed over second polysilicon spacer116b′ to form a memory gate130bin accordance with some embodiments. The material and formation of second silicide layer124bmay be similar to, or the same as, second silicide layer124adescribed previously.

As described above, since polysilicon layer114is over-etched to form second polysilicon spacer116b′ shorter than second polysilicon spacer116bshown inFIG. 1C, distance between top portion117bof second polysilicon spacer116b′ and top portion119of polysilicon gate104is relatively large. Therefore, the risk of circuit shortage between control gate128and memory gate130b(e.g. between first silicide layer122and second silicide layer124b) is reduced.

However, since over-etching process215is performed for a relatively long time, a great amount of electric charges may be trapped in insulating layer106(e.g. nitride layer110). The charging effect may result in an increase of the threshold voltage of flash memory structure100b. In addition, substrate102or other elements formed in/over substrate102(not shown) may be damaged during over-etching process215.

Furthermore, second polysilicon spacer116b′ may have poor uniformity since the height of second polysilicon spacer116b′ is difficult to control during over-etching process215. Moreover, if second polysilicon spacer116b′ formed by over-etching process215is too short, the resulting memory gate130bmay malfunction, and the risk for circuit shortage between memory gate130band source and drain regions126increases.

Accordingly, in some embodiments, a flash memory structure having a greater distance between its control gate and memory gate is formed without using over-etching process215.FIGS. 3A to 3Killustrate cross-sectional representations of various stages of forming a flash memory structure100cwithout using over-etching process215in accordance with some embodiments. Some elements and manufacturing processes for forming flash memory structure100cis similar to those for forming flash memory structure100aand100band are not repeated herein.

Referring toFIG. 3A, substrate102is provided. Polysilicon gate104is formed over substrate102in accordance with some embodiments. After polysilicon gate104is formed, insulating layer106, including first oxide layer108, nitride layer110, and second oxide layer112, is conformally formed over substrate102to cover polysilicon gate104. In some embodiments, insulating layer106(e.g. an ONO layer) has a thickness in a range from about 10 nm to about 90 nm. When the thickness of insulating layer106is too large, the threshold voltage of the resulting flash memory structure100cincreases. However, when the thickness of insulating layer106is too small, risks of circuit voltage increase.

After insulating layer106is formed, polysilicon layer114is conformally formed on insulating layer106. Next, etching process115is performed to form first polysilicon spacer116aand second polysilicon spacer116a′ along the sidewalls of polysilicon gate104, as shown inFIG. 3Bin accordance with some embodiments. In addition, first polysilicon spacer116aand second polysilicon spacer116a′ have sharp top portions117abeing close to top portion119of polysilicon gate104.

Next, a photoresist layer317is formed to cover second polysilicon spacer116a′, as shown inFIG. 3Cin accordance with some embodiments. In some embodiments, photoresist layer317is formed by forming a photoresist layer and patterning the photoresist layer afterwards. As shown inFIG. 3C, photoresist layer317also covers a portion of polysilicon gate104in accordance with some embodiments.

After photoresist layer317is formed, first polysilicon spacer116ais removed, as shown inFIG. 3Din accordance with some embodiments. In some embodiments, first polysilicon spacer116ais not covered by photoresist layer317and is removed by an isotropic dry etching process. Afterwards, another etching process, such as a wet etching process, is performed to remove exposed portions of insulating layer106, as shown inFIG. 3Ein accordance with some embodiments.

Next, a dielectric layer319is conformally formed over substrate102to cover polysilicon gate104and second polysilicon spacer116a′, as shown inFIG. 3Fin accordance with some embodiments. In some embodiments, dielectric layer319is made of silicon nitride, silicon dioxide, silicon oxide, or other applicable insulating materials. In some embodiments, dielectric layer319is formed by CVD. It should be noted that, although dielectric layer319shown inFIG. 3Fonly includes a single layer, in some other embodiments, dielectric layer319also include multilayers.

Afterwards, dielectric layer319is further etched to form first spacer120and second spacer120′, as shown inFIG. 3Gin accordance with some embodiments. In some embodiments, dielectric layer319is etched by an anisotropic dry etching process. First spacer120is formed on the sidewall of polysilicon gate104, second spacer120′ is formed on the sidewall of second polysilicon spacer116b. After first spacer120and second spacer120′ are formed, source and drain regions126are formed in substrate102. As shown inFIG. 3G, second polysilicon spacer116a′ has a relatively greater height (compared to second polysilicon spacer116b′ shown inFIG. 2C), and it is easier to form second spacer120′ on the sidewall of second polysilicon spacer116b′.

Next, a photoresist layer321is formed over substrate102to cover polysilicon gate104and first spacer120, as shown inFIG. 3Hin accordance with some embodiments. In addition, second polysilicon spacer116a′ is exposed by photoresist layer321.

Afterwards, a wet etching process323is performed to remove sharp top portion117aof second polysilicon spacer116a′ to form a shortened polysilicon spacer116c′, as shown inFIG. 3Iin accordance with some embodiments. During wet etching process323, a bottom portion of second polysilicon spacer116a′ is protected by second spacer120′ and therefore is not removed.

After wet etching process323is performed, the top surface of shortened polysilicon spacer116c′ is substantially level with the top surface of second spacer120′. Since top portion117aof second polysilicon spacer116a′ is removed by wet etching process323instead of by a dry etching process, the top surface of shortened polysilicon spacer116c′ is substantially parallel to the top surface of substrate102in accordance with some embodiments. In addition, the distance between the top surface of shortened polysilicon spacer116cand top portion119of polysilicon gate104is relatively large.

Furthermore, as shown inFIG. 3I, during wet etching process323, sharp top portion117aof second polysilicon spacer116a′ is removed, while an upper portion306of insulating layer106is not removed. Therefore, the height of insulating layer106on the sidewall of polysilicon gate104is greater than the height of shortened polysilicon spacer116c′. That is, upper portion306of insulating layer106is exposed (e.g. not covered) by shortened polysilicon spacer116c′.

In some embodiment, upper portion306of insulating layer106not covered by shortened polysilicon spacer116c′ has a length L1in a range from about 5 nm to about 150 nm. When length L1is too small, risks of circuit shortage increase. However, when length L1is too large, shortened polysilicon spacer116c′ is too short to form elements, such as a memory gate and source and drain regions126, in the sequential processes.

Next, first silicide layer122is formed over polysilicon gate104to form control gate128, and a second silicide layer124cis formed over polysilicon spacer116bto form a memory gate130c, as shown inFIG. 3Jin accordance with some embodiments. Materials and formation for second silicide layer124cmay be similar to, or the same as, those for second silicide layers124aand124b.

As shown inFIG. 3J, insulating layer106has a height H1on the sidewall of control gate128, and memory gate130chas a height H2smaller than height H1. In some embodiments, height H1is in a range from about 50 nm to about 400 nm. In some embodiments, height H2is in a range from about 30 nm to 300 nm. When height H2is too large, risks of circuit shortage between first silicide layer122and second silicide layer124cincrease. However, when height H2is too small, memory gate130ctends to malfunction and circuit shortage between source and drain regions126and memory gate130cincrease.

In some embodiments, a difference between height H1and height H2is in a range from about 5 nm to about 150 nm. Similarly, when the difference between height H1and height H2is too small, risks of circuit shortage between first silicide layer122and second silicide layer124cincrease. However, when the difference between height H1and height H2is too large, memory gate130tends to be malfunction.

In addition, control gate128has a height H3greater than height H1. In some embodiments, height H3is in a range from about 60 nm to about 450 nm. In some embodiments, a distance D1between the bottom surface of first silicide layer122and the top surface of second silicide layer124cis in a range from about 10 nm to about 200 nm. Since distance D1between first silicide layer122and second silicide layer124cis relatively high, circuit shortage between first silicide layer122and second silicide layer124ccan be prevented.

Next, a contact etch stop layer325is conformally formed over substrate102to cover control gate128and memory gate130c, as shown inFIG. 3Kin accordance with some embodiments. In some embodiments, contact etch stop layer325is made of dielectric materials such as SiN or SiON. In some embodiments, contact etch stop layer325is formed by CVD.

After contact etch stop layer325is formed, an interlayer dielectric layer327is formed on contact etch stop layer325over substrate102in accordance with some embodiments. In some embodiments, interlayer dielectric layer327is an extremely low dielectric constant (ELK) interlayer dielectric layer. In some embodiments, interlayer dielectric layer327is made of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, or other applicable dielectric materials. Interlayer dielectric layer327may be formed by CVD. It should be noted that interlayer dielectric layer327may be a single layer or may include multilayers made of various materials, and the scope of the disclosure is not intended to be limiting.

As described previously, distance D1between first silicide layer122and second silicide layer124cis relatively high (e.g. compared to the distance between first silicide layer122and second silicide layer124ashown inFIG. 1D). Therefore, risks of circuit shortage between first silicide layer122and second silicide layer124creduce.

In addition, since height H1of insulating layer106is greater than height H2of memory gate130c(e.g. compared to memory gate130bhaving the same height as insulating layer106shown inFIG. 2D), upper portion306formed on the sidewall of control gate128is not covered by memory gate130c. Therefore, circuit shortage between control gate128and memory gate130cis prevented.

Furthermore, over-etching process215is not performed when flash memory structure100cis formed. As described previously, over-etching process215may result in damaging substrate102or other elements formed on substrate102. In addition, it is difficult to control the height of memory gate130b(as shown inFIG. 2D) since memory gate130bis formed by using over-etching process215. However, when memory gate130bis too short, memory gate130bmay malfunction, and circuit shortage between memory gate130band source and drain regions126may occur. Since memory gate130cis formed by using wet etching process323instead of over-etching process215, the problems described above are avoided.

Embodiments of mechanisms for a flash memory structure are provided. The flash memory structure includes a control gate, an insulating layer formed on a sidewall of the control gate, and a memory gate formed adjacent to the insulating layer. The insulating layer has a first height on the sidewall of the control gate, and the memory gate has a second height smaller than the first height. Therefore, an upper portion of the insulating layer is not covered by the memory gate and is configured to prevent the circuit shortage between the control gate and the memory gate.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device further includes an insulating layer formed on a sidewall of the control gate and a memory gate formed adjacent to the insulating layer. In addition, the insulating layer has a first height, and the memory gate has a second height shorter than the first height.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed adjacent to the control gate over the substrate and an insulating layer formed between the control gate and the memory gate. In addition, the insulating layer comprises an upper portion formed on a sidewall of the control gate without being covered by the memory gate.

In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes providing a substrate and forming a polysilicon gate having a first sidewall and a second sidewall over the substrate. The method further includes forming an insulating layer on the second sidewall of the control gate and forming a polysilicon spacer adjacent to the insulating layer. The method further includes forming a spacer on a sidewall of the polysilicon spacer and removing a top portion of the polysilicon spacer to expose an upper portion of the insulating layer. The method also includes forming a first silicide layer over the polysilicon gate to form a control gate and a second silicide layer over the polysilicon spacer to form a memory gate. In addition, the first silicide layer and the second silicide layer is at least separated by the upper portion of the insulating layer.