Method of manufacturing semiconductor devices with transistor cells and semiconductor device

First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

This application claims priority to German patent application 10 2016 104 968.9, filed Mar. 17, 2016, which application is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to a method of manufacturing semiconductor devices and transistor cells and a semiconductor device.

BACKGROUND

With shrinking dimensions of semiconductor devices such as power semiconductor switching devices, comparatively thin semiconductor wafers have to be handled in a process environment. With decreasing thickness of the semiconductor wafers trench structures including oxide layers and extending from the front side into the semiconductor wafer as well as thick metal layers on the wafer surface bend and warp the wafer to a significant degree. Wafer warping and wafer bowing increase process complexity, e.g., for a wafer dicing process that obtains separated semiconductor dies from a semiconductor wafer. During fabrication, auxiliary carriers and/or stress relaxing features at the front side may reduce wafer warpage and wafer bowing.

It is desirable to provide economic methods for manufacturing semiconductor devices that reduce wafer bowing and/or that simplify wafer dicing.

SUMMARY

According to an embodiment a semiconductor device includes transistor cells that include body regions forming first pn junctions with a drift structure in a semiconductor portion. First longitudinal axes of first reinforcement stripes in the semiconductor portion are parallel to a first surface of the semiconductor portion. Second longitudinal axes of second reinforcement stripes between the first reinforcement stripes and the first surface are parallel to the first surface.

According to another embodiment a method of manufacturing a semiconductor device includes forming first reinforcement stripes on a process surface of a base substrate. A first epitaxial layer is formed on the process surface, wherein the first epitaxial layer covers the first reinforcement stripes. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer is formed on exposed portions of the first epitaxial layer, wherein the second epitaxial layer covers the second reinforcement stripes. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

According to a further embodiment a method of manufacturing a semiconductor device includes forming dicing stripes on a process surface of a base substrate. An epitaxial layer is formed on the process surface and covers the dicing stripes. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the epitaxial layer. Dicing trenches are formed in a vertical projection of the dicing stripes. The dicing trenches separate the semiconductor portions of semiconductor dies. An auxiliary carrier is attached at a front side of the semiconductor dies opposite to the base substrate. The base substrate is removed. The semiconductor dies are separated from each other by at least partially removing the dicing stripes.

According to a further embodiment a semiconductor device includes micro electromechanical structures. First longitudinal axes of first reinforcement stripes in the semiconductor portion are parallel to a first surface of the semiconductor portion. Second longitudinal axes of second reinforcement stripes between the first reinforcement stripes and the first surface are parallel to the first surface.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or heavily doped semiconductor material. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

FIGS. 1A to 1Gconcern a process for manufacturing a semiconductor device with at least two sets of reinforcement structures in different layers, wherein longitudinal axes of the reinforcement structures of the two sets are parallel or tilted to each other. The semiconductor substrate500aincludes a base substrate bow, wherein along a process surface101athe base substrate bow includes a layer of a semiconductor material. For example, the base substrate bow is a semiconductor wafer of silicon, germanium or a silicon germanium crystal. According to other embodiments, the base substrate bow may include a dielectric portion. For example, the base substrate100ais an SOI (silicon-on-insulator) wafer or an SOG (silicon-on-glass) wafer.

The process surface101aof the base substrate100adefines a front side of the semiconductor substrate500a. A support surface102aon the back is parallel to the process surface101a. Directions parallel to the process surface101aare horizontal directions and a direction perpendicular to the process surface101ais a vertical direction.

A first reinforcement layer361ais formed on the process surface101a. The first reinforcement layer361amay be formed by thermal oxidation of the underlying semiconductor material of the base substrate bow or by a deposition process. A resist layer may be deposited on the first reinforcement layer361aand patterned by lithography to obtain a resist mask402.

FIG. 1Ashows the resist mask402with stripe-shaped mask sections on the first reinforcement layer361a, which is formed on the process surface101a. The material of the first reinforcement layer361amay be conductive, semiconducting, or insulating. For example, the material of the first reinforcement layer361amay be thermally grown semiconductor oxide, for example silicon oxide, deposited semiconductor oxide, for example deposited silicon oxide, semiconductor nitride, for example silicon nitride, semiconductor oxynitride, for example silicon oxynitride, silicon carbide, or carbon, e.g., DLC (diamond-like carbon). According to a further embodiment the material of the first reinforcement layer361ais or contains a metal, e.g., tungsten W.

Using the first resist mask402as etch mask, an etch process, for example, a plasma etch removes exposed portions of the first reinforcement layer361a.

FIG. 1Bshows first reinforcement stripes361formed on the process surface101aof the base substrate bow. A vertical extension of the first reinforcement stripes361may be in a range from 50 nm to 50 μm, e.g., 20 μm or 5 μm, by way of example. A center-to-center distance between neighboring first reinforcement stripes361may be in a range from 100 nm to 100 μm. A width of the first reinforcement stripes361may be in a range from 500 nm to 10 μm. The first reinforcement stripes361may extend through a complete process portion of the base substrate bow. According to an embodiment, the first reinforcement stripes361have a length in a range from 100 μm to several millimeters or several centimeters, wherein the longitudinal axes of several separated first reinforcement stripes361coincide.

A first epitaxial layer100bis formed by epitaxy on exposed portions of the process surface101abetween the first reinforcement stripes361. During epitaxy, semiconductor atoms grow in registry with the crystal lattice of the semiconductor layer of the base substrate bow.

The first epitaxial layer100bcovers the first reinforcement stripes361. For example, parameters of the epitaxy may be adjusted to achieve a sufficient lateral growth across the first reinforcement stripes361. According to another embodiment, an epitaxy layer obtained by epitaxial growth may be subjected to a heat treatment that at least partially fluidifies the epitaxy layer, wherein the re-crystallized epitaxial layer covers the first reinforcement stripes361without leaving voids in the vertical projection of the first reinforcement stripes361.

For example, after epitaxy of at least a portion of the first epitaxial layer100b, the semiconductor substrate500amay be subjected to a heating treatment in a hydrogen-containing ambient at temperatures above 900° C., e.g., between 1050° C. and 1150° C. for at least five minutes or longer. Due to the high surface mobility of silicon atoms in the hydrogen-containing atmosphere, the epitaxial layer becomes viscous and a slowly moving flow of viscous silicon laterally covers the first reinforcement stripes361. The auxiliary surface101bof the first epitaxial layer100bmay be polished and planarized, for example by CMP (chemical mechanical polishing).

FIG. 1Cshows the first epitaxial layer100bwith a planar auxiliary surface101b. The first epitaxial layer100bcovers the first reinforcement stripes361. A vertical extension or thickness of the first epitaxial layer100bmay be in a range from 1 μm to 200 μm.

Second reinforcement stripes362are formed on the auxiliary surface101bin the same or in a similar way as the first reinforcement stripes361.

FIG. 1Dshows the second reinforcement stripes362on the auxiliary surface101b. Second longitudinal axes372of the second reinforcement stripes362run parallel or tilted to first longitudinal axes371of the first reinforcement stripes361. According to the illustrated embodiment, the second longitudinal axes372of the second reinforcement stripes362are orthogonal to the first longitudinal axes371of the first reinforcement stripes361. Both the first and the second reinforcement stripes361,362run parallel to the support surface102aand to the auxiliary surface101b. Material configuration, dimensions and pitch of the second reinforcement stripes362may be the same as for the first reinforcement stripes361or may differ from material configuration, dimensions and pitch of the first reinforcement stripes361. The first and second reinforcement stripes361,362are separated from each other along the vertical axis of the semiconductor substrate500a.

Forming an epitaxial layer and forming reinforcement stripes may be repeated, e.g., once or twice such that three or more planes with reinforcement stripes are successively formed.

A second epitaxial layer100cis formed on exposed portions of the auxiliary surface101bof the first epitaxial layer100b, wherein process parameters of the epitaxy process may be adjusted such that the second epitaxial layer100csufficiently overgrows the second reinforcement stripes362. Alternatively, the second epitaxial layer100cmay be at least partially fluidified and recrystallized after deposition of at least a portion of the second epitaxial layer100cas described above.

FIG. 1Eshows the semiconductor substrate500aincluding the base substrate bow, a first epitaxial layer100bmainly between the first and second reinforcement stripes361,362and the second epitaxial layer100cwith a planar main surface101c.

Front side processing may form, e.g., portions of micro electromechanical structures from a section of the second epitaxial layer100cat the front side defined by the main surface101cof the second epitaxial layer100c. According to the illustrated embodiment, the front side processing includes formation of transistor cells at the front side, wherein formation of the transistor cells TC may include forming trench structures300extending from the main surface101cof the second epitaxial layer100c. The trench structures300may include conductive structures such as gate electrodes155and field electrodes165for field compensation, wherein dielectric material, for example, silicon oxide separates the conductive structures from the material of the second epitaxial layer100c. Formation of the transistor cells TC may also include deposition of an interlayer dielectric210on the main surface101cand forming a thick front side metallization including a first load electrode310on the interlayer dielectric210.

FIG. 1Fshows the semiconductor substrate500awith transistor cells TC formed at a front side. The transistor cells TC are electrically connected in parallel to each other. Trench structures300that extend from the main surface101cinto the second epitaxial layer100cinclude gate electrodes155, gate dielectrics151, which separate the gate electrodes155from the second epitaxial layer100c, field electrodes165, field dielectrics161separating the field electrodes165from the second epitaxial layer100cand separation dielectrics171separating the gate electrodes155and the field electrodes165from each other. In mesa sections170of the second epitaxial layer100cbetween neighboring trench structures300body regions120of the transistor cells TC form first pn junctions pn1with a precursor drift structure130ain the second epitaxial layer100cand second pn junctions pn2with source regions no formed between the main surface low and the body regions120.

An interlayer dielectric210covers the main surface low. First contact structures315extending through the interlayer dielectric210electrically connect the first load electrode310with the source regions110and the body regions120in the mesa sections170of the second epitaxial layer100c.

According to other embodiments the trench structures300include only one conductive structure, for example gate electrodes or field electrodes. The trench structures300may be needle-shaped with both lateral dimensions within the same order of magnitude, e.g., approximately equal, or may be stripe-shaped with a longitudinal horizontal extension exceeding at least ten times a transverse horizontal extension.

The semiconductor substrate500ais thinned from the side of the support surface102a. Thinning may include a grinding process removing the base substrate bow completely or at least partially, wherein the resulting rear side surface of the semiconductor substrate500aon the back is planar and parallel to the main surface101c. After thinning, further implants, patterning and/or deposition processes may be performed effective on the rear side surface on the back of the semiconductor substrate500ato finalize a drift structure130. For example, dopants may be implanted to form a field stop layer and/or a heavily doped contact portion along the rear side surface. A metal may be deposited to form a back side metallization including a second load electrode320.

The semiconductor substrate500amay be diced, for example sawed or etched through along kerf lines to obtain a plurality of identical semiconductor devices500from the semiconductor substrate500a.

The semiconductor device500includes a semiconductor portion100formed from portions of the base substrate bow, the first epitaxial layer100band the second epitaxial layer100cof the semiconductor substrate500aofFIG. 1F, wherein a first surface101of a front side of the semiconductor portion100corresponds to the main surface101cof the semiconductor substrate500aofFIG. 1Fand on the back the thinning produces a second surface102of the semiconductor portion100.

An intermediate section100zof the semiconductor portion100, which includes remnants of the base substrate bow ofFIG. 1F, may separate the first reinforcement stripes361from the second metallization with the second load electrode320on the back of the semiconductor device500. A vertical extension of the intermediate section100zmay be in a range from 0 to 100 μm, for example in a range from 500 nm to 5 μm.

The drift structure130includes a drift zone131formed from portions of the first and second epitaxial layers100b,100cofFIG. 1Fand further includes a heavily doped contact portion139. The heavily doped contact portion139has the same conductivity type as the drift zone131in case the semiconductor device500is an IGFET (insulated gate field effect transistor) or has the complementary conductivity types in case the semiconductor device500is a reverse-blocking IGBT (insulated gate bipolar transistor). For reverse conducting IGBTs, the contact portion139may include zones of both conductivity types. A separation section130zof the drift structure130may separate the second reinforcement stripes362from the first reinforcement stripes361.

FIGS. 2A to 2Brefer to a semiconductor device500, which may be obtained from the process described with reference toFIGS. 1A to 1F.

The semiconductor device500may include a plurality of identical transistor cells TC and may be or may include an IGFET, for example, an MOSFET (metal oxide semiconductor FET) in the usual meaning including FETs with metal gates as well as FETs with semiconductor gates. According to another embodiment the semiconductor device500may be an IGBT or an MCD (MOS controlled diode).

A semiconductor portion100is of a single crystalline semiconductor material such as silicon (Si), germanium (Ge), a silicon germanium crystal (SiGe), or an AmBvsemiconductor.

The semiconductor portion100has a first surface101and a second surface102parallel to the first surface101. The distance between the first and second surfaces101,102is related to a voltage blocking capability the semiconductor device500is specified for, may be at least 15 μm and may range up to several 100 μm. A lateral outer surface103tilted to the first and second surfaces101,102connects the first and second surfaces101,102.

The semiconductor portion100includes a drift structure130that includes a drift zone131of a first conductivity type as well as a contact portion139between the drift zone131and the second surface102. In the drift zone131, a dopant concentration may gradually or in steps increase or decrease with increasing distance to the first surface101at least in portions of its vertical extension. According to other embodiments, the dopant concentration in the drift zone131may be approximately uniform. For a silicon-based semiconductor portion100the mean dopant concentration in the drift zone131may be between 1E15 cm−3and 1E17 cm−3, for example, in a range from 5E15 cm−3to 5E16 cm−3.

A dopant concentration in the contact portion139along the second surface102is sufficiently high to form an ohmic contact with a metal directly adjoining the second surface102. In case the semiconductor portion100is based on silicon, in an n-conductive contact portion139the dopant concentration along the second surface102may be at least 1E18 cm−3, for example at least 5E19 cm−3. In a p-conductive contact portion139, the dopant concentration may be at least 1E16 cm−3, for example at least 5E17 cm−3. For IGFETs the contact portion139has the same conductivity as the drift zone131. For IGBTs the contact portion139may have the complementary second conductivity type or may include zones of both conductivity types.

The drift structure130may include further doped regions, e.g., a field stop layer or a buffer zone between the drift zone131and the contact portion139, barrier zones as well as counterdoped regions.

A plurality of trench structures300extend from the first surface101into the semiconductor portion100. The trench structures300may form a regular stripe pattern including regularly arranged stripe-shaped trench structures300.

According to another embodiment the trench structures300may be connected to each other and form a grid pattern. According to a further embodiment the trench structures300are needle-shaped with both horizontal lateral dimensions within the same order of magnitude or approximately equal. The trench structures300may be completely filled with dielectric materials or may include one, two or more conductive structures separated from each other. For example, the trench structures300may include at least one of a gate electrode and a field electrode.

First reinforcement stripes361are formed at a first distance d1to the first surface101and second reinforcement stripes362are formed at a second distance d2to the first surface101, wherein d2is smaller than d1. First longitudinal axes371of the first reinforcement stripes361are parallel to the first surface101and tilted, e.g., orthogonal to second longitudinal axes372of the second reinforcement stripes362.

The first reinforcement stripes361may directly adjoin to the second surface102or may be formed at a distance to the second surface102. For example, the first reinforcement stripes361may be formed between the contact portion139and the drift zone131. According to other embodiments, the first reinforcement stripes361may be formed at a distance to the contact portion139.

A separation section130zof the drift structure130separates the second reinforcement stripes362from the first reinforcement stripes361. A vertical extension d3of the separation section130zmay be in a range from 0 to 50 μm. A further portion of the drift structure130separates the second reinforcement stripes362from the trench structures300.

The first and second reinforcement stripes361,362may be from different materials or may be from the same material(s). For example, the first and second reinforcement stripes361,362may be from semiconductor oxide, for example silicon oxide, semiconductor nitride, for example silicon nitride, semiconductor oxynitride, for example silicon oxynitride, silicon carbide, carbon, e.g., DLC or any combination thereof. According to a further embodiment the material of the first reinforcement stripes361, or the second reinforcement stripes362, or of both is or contains a stable metal that is inert with respect to silicon, e.g., tungsten W.

A vertical extension of the first and second reinforcement stripes361,362may be between 50 nm and 5 μm, wherein the first and second reinforcement stripes361,362may have the same vertical extension or may have different vertical extensions.

A transversal horizontal extension of the first and second reinforcement stripes361,362may be in a range from 500 nm to 20 μm, e.g., from 1 μm to 10 μm, wherein the first and second reinforcement stripes361,362may have the same horizontal transverse dimension or different horizontal transverse dimensions.

A center-to-center distance between neighboring first reinforcement stripes361and between neighboring second reinforcement stripes362may be in a range from 50 nm to 500 μm, wherein the first reinforcement stripes361and the second reinforcement stripes362may have the same or different center-to-center distances. A spacing of the first reinforcement stripes361as well as a spacing of the second reinforcement stripes362may be uniform across the semiconductor device500. According to another embodiment, the distances between neighboring first reinforcement stripes361and/or between neighboring second reinforcement stripes362may increase with increasing distance to the lateral outer surface103.

A longitudinal horizontal dimension of the first and second reinforcement stripes361,362may be at least ten times the horizontal transverse dimension. The first and second reinforcement stripes361,362may extend from one side of the semiconductor portion100to the opposite side or may be segmented along the longitudinal axis.

The first and second reinforcement stripes361,362may form regular patterns across the complete horizontal cross-section of the semiconductor device500or may spare regions of the semiconductor device500, for example a central region in the vertical projection of the trench structures300.

A distance between the first reinforcement stripes361and/or between the second reinforcement stripes362may be greater in the central portion of the semiconductor device500than in a peripheral portion close to the lateral outer surface103.

FIGS. 2C and 2Drefer to micro electromechanical devices502that may be obtained from semiconductor substrate500aand the process described with reference toFIGS. 1A to 1F.

InFIG. 2Cthe micro electromechanical device502may be or may be part of a micro electromechanical system, e.g., an accelerometer, gyroscope, microphone, microfluidic system, pressure sensor, chemo sensor, or biosensor, by way of example. In the illustrated embodiment the micro electromechanical device502includes a micro electromechanical structure MS with micromechanical components of an accelerometer390. Deformable beams392from the second epitaxial layer100cofFIGS. 1A to 1For from a layer formed on the second epitaxial layer100cconnect a mass391, which is formed in a chamber393, to a frame portion of the semiconductor portion100. Electric sensors, e.g., capacitive sensors may determine the position of the mass391with respect to a center of the chamber393.

FIG. 2Drefers to a micro electromechanical device502that includes electronic circuits380in addition to a micro electromechanical structure MS with micromechanical components of, e.g., an accelerometer390, wherein semiconducting portions of the electronic circuits380may be formed in the semiconductor portion100. The electronic circuits380may process and output signals obtained from the electric sensors of the micro electromechanical structure MS. In the illustrated embodiment, the first and second longitudinal axes of the first and second reinforcement stripes361,362are parallel to each other.

FIGS. 3A and 3Brefer to a semiconductor device500with transistor cells TC formed at the front side, wherein the trench structures300include gate electrodes155, gate dielectrics151separating the gate electrodes155from the semiconductor material of the semiconductor portion100, field electrodes165, field dielectrics161separating the field electrodes165from the semiconductor portion100and separation dielectrics171separating the gate electrodes155from the field electrodes165.

Mesa sections170of the semiconductor portion100between neighboring trench structures300may include body regions120of the transistor cells TC, wherein each body region120forms a first pn junction pn1with the drift structure130, e.g., the drift zone131, and second pn junctions pn2with source regions110in the mesa sections170. The semiconductor portion100further includes first reinforcement stripes361and second reinforcement stripes362as described with reference toFIGS. 2A and 2B.

An interlayer dielectric210is formed on the first surface101. The interlayer dielectric210may include one or more dielectric layers from thermal silicon oxide, deposited silicon oxide, a silicate glass such as BSG (boron silicate glass), PSG (phosphorus silicate glass), BPSG (boron-phosphorus silicate glass), FSG (fluorosilicate glass), and a spin-on-glass. A front side metallization includes a first load electrode310. First contact structures315extending through the interlayer dielectric210electrically connect the first load electrode310with the source and body regions110,120in the mesa sections170. Second contact structures316may electrically connect the first load electrode310with the field electrodes165. The front side metallization may further include a gate conductor330, wherein gate contacts335extending through the interlayer dielectric210electrically connect the gate conductor330with the gate electrodes155.

A back side metallization on the second surface102directly adjoins the contact portion139and includes a second load electrode320. In the on-state of the semiconductor device500a load current flows in a vertical direction through the semiconductor portion100between the first and second load electrodes310,320.

The first reinforcement stripes361may be evenly spaced from each other and the second reinforcement stripes362may be evenly spaced from each other.

In the semiconductor device500ofFIGS. 4A and 4Bboth the first and the second reinforcement stripes361,362are formed only in a peripheral portion690along the lateral outer surface103. A central portion610surrounded by the peripheral portion690is devoid of both first and second reinforcement stripes361,362. According to other embodiments, the central portion610may be devoid of only one of the first and second reinforcement stripes361,362. The central portion610may coincide with a transistor cell region in which the transistor cells TC are formed such that the reinforcement stripes361,362do not adversely affect the on-state resistance of the semiconductor device500. According to other embodiments the central portion610coincides with only a central section of the transistor cell region.

FIG. 5AtoFIG. 5Hconcern a process for manufacturing semiconductor devices by using buried dicing stripes for separating semiconductor dies formed in the same semiconductor substrate500a.

On a process surface101aof a semiconducting portion of a base substrate bow dicing stripes365are formed by photolithography as described above with reference toFIGS. 1A to 1Gfor the first and second reinforcement stripes361,362.

The process for forming the dicing stripes365from a continuous dicing layer may be highly anisotropic such that the sidewalls tilted to the process surface101aare approximately vertical.

The dicing stripes365shown inFIG. 5Amay be connected to each other to form a complete regular grid on the process surface101a. The grid may be continuous. According to other embodiments, the grid may include a plurality of narrowly spaced line portions. A horizontal width of the dicing stripes365may be in a range from 0.5 μm to 20 μm, for example in a range from 1 μm to 10 μm. A vertical extension may be in a range from 50 nm to 1 μm. The distance between neighboring dicing stripes365corresponds to an edge length of the finalized semiconductor device. The material of the dicing stripes365may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, carbon, a stable metal inert with respect to silicon, e.g., tungsten or any combination thereof.

An epitaxial layer100bis grown by epitaxy on exposed surface portions of the process surface101a. The process parameters of the epitaxy process may be selected such that the first epitaxial layer100bcompletely overgrows the dicing stripes365. According to another embodiment, an anneal in an hydrogen-containing ambient may partially fluidify a grown epitaxial layer such that after recrystallization the first epitaxial layer100bfills any void possibly formed in the vertical projection of the dicing stripes365. According to a further embodiment, the epitaxy may leave closed voids in the vertical projection of the dicing stripes365.

The epitaxial layer100bshown inFIG. 5Bmay have an approximately uniform dopant concentration different from a dopant concentration in the semiconducting portion of the base substrate bow. According to other embodiments, a vertical dopant profile in the first epitaxial layer100bmay vary as a function of a distance to the process surface101a.

Semiconductor dies501with transistor cells TC may be formed in portions of the epitaxial layer100bframed by the dicing stripes365. The semiconductor dies501may be dies of power semiconductor devices with a vertical load current flow between a front side and a rear side of the semiconductor device. A front side metallization including first load electrodes310at the exposed front side of the semiconductor dies501are formed, wherein metallizations of neighboring semiconductor dies501are separated from each other by a patterning process. By using the patterned metallization at the front side or by a further patterning process, dicing trenches370may be etched into portions of the first epitaxial layer100bin the vertical projection of the dicing stripes365.

FIG. 5Cshows the semiconductor substrate500awith the base substrate bow and semiconductor dies501with semiconductor portions100formed from the epitaxial layer100bofFIG. 5B. The semiconductor dies501may include portions of micro electromechanical structures and/or transistor cells TC with body regions120forming first pn junctions pn1with a drift structure130, which is formed outside of the body regions120in the epitaxial layer100b, and second pn junctions with source regions formed between the body regions120and a first surface101at the front side of the semiconductor portion100. Trench structures300extend from the first surface101into the semiconductor portions100. First contact structures315may electrically connect the first load electrodes310with the source regions and with the body regions120of the transistor cells TC.

The dicing trenches370extend between the metallizations of neighboring semiconductor dies501through the interlayer dielectric210into the first epitaxial layer100bofFIG. 5Band expose portions of the dicing stripes365. The dicing trenches370may be at least partly lined with a protection liner, e.g., a silicon oxide liner and/or may be filled with a sacrificial material375, e.g., silicon oxide, or a resin, such as an adhesive resin to hold the semiconductor dies501at their position after removal of the dicing stripes365.

An auxiliary carrier400is attached to the front side metallization including the first load electrodes310.

The auxiliary carrier400inFIG. 5Dmay be a silicon disc or a glass disc, by way of example. The auxiliary carrier400stabilizes the semiconductor substrate500ain the following processes which may completely remove the base substrate bow, for example, by grinding or by a process combining etch processes with grinding and/or polishing processes. A CMP (chemical-mechanical polishing) may remove at least a last portion of the base substrate bow, wherein the process may detect exposure of the dicing stripes365and may use detection of the dicing stripes365as polishing stop signal.

FIG. 5Eshows a semiconductor die composite500bincluding the auxiliary carrier400and a plurality of identical semiconductor dies501attached to the auxiliary carrier400and separated from each other by the sacrificial material375in the dicing trenches and the dicing stripes365. Removal of the base substrate bow ofFIG. 5Dexposes second process surfaces102C on the back of the semiconductor dies501.

A back side metallization including second load electrodes320is formed on the back of the semiconductor dies501opposite to the front side metallization including the first load electrode310.

For example, the semiconductor portions100of the semiconductor dies501are selectively recessed from the back, wherein the vertical extensions of the recess is smaller than the vertical extension of the dicing stripes365. Dopants may be implanted through the recessed second surfaces102of the semiconductor dies501. For example, a heavily doped contact portion139with a dopant concentration sufficiently high to ensure an ohmic contact with a metal may be implanted through the second surfaces102. In addition, dopants for a lower doped field stop layer may be implanted through the second surfaces102.

FIG. 5Fshows the recessed semiconductor portions100and heavily doped contact portions139formed along the surface102of the semiconductor dies500. The dicing stripes365protrude from the second surface102such that sidewalls of the dicing stripes365are partially exposed.

A metal-containing layer or layer stack including one or more metal-containing layers, e.g., metal alloys is deposited. Portions of the deposited metal-containing layer or layer stack formed on an exposed surface of the dicing stripes365may be removed, for example by a polishing step.

FIG. 5Gshows back side metallizations including second load electrodes320in the meshes of the grid formed by the dicing stripes365.

The semiconductor dies501are separated from each other. For example, a selective etch, e.g., an oxide etch in case the dicing stripes365are of silicon oxide, may remove the dicing stripes365, and, if applicable, the sacrificial material375in the dicing trenches370.

FIG. 5Hshows the semiconductor die composite500bwith separated semiconductor devices500obtained from the semiconductor dies501ofFIG. 5Gand attached to the auxiliary carrier400. From the auxiliary carrier400, the semiconductor devices500may be picked up and forwarded to further processing that may include, for example, wire bonding and chip packaging.

According to another embodiment, the dicing stripes365are sawed through such that a continuous oxide ring surrounds the semiconductor devices500along the second surface102.

FIGS. 6A to 6Gconcern a process using tapering dicing stripes365. A process for forming the dicing stripes365from a grown or deposited dicing layer includes a highly isotropic component.

As illustrated inFIG. 6Asidewalls of dicing stripes365resulting from etching with an isotropic component are tilted to the process surface101aof the base substrate bow. The dicing stripes365taper with increasing distance to the process surface101a. A slope angle α with respect to the process surface101amay be in a range from 30° to 70°, e.g., from about 45° to about 60°.

Portions of micro electromechanical structures may be formed in semiconductor dies501formed from portions of the grown epitaxial layer100b. According to the illustrated embodiment transistor cells TC and a front side metallization including first load electrodes310at a front side of semiconductor dies501are formed on the grown epitaxial layer100b. By using the patterned front side metallization alone, by using the patterned metallization in combination with a further patterning process or by an independent additional patterning process, dicing trenches370are formed that separate semiconductor portions100of semiconductor dies501formed from the epitaxial layer100bofFIG. 6B.

FIG. 6Cshows the dicing trenches370exposing the tapering dicing stripes365. The dicing trenches370may remain unfilled or may be filled with sacrificial material and/or at least partly lined with a protection liner.

An auxiliary carrier40ois attached at the front side of the semiconductor dies501as shown inFIG. 6Dand the base substrate bow is removed, e.g., by grinding.

FIG. 6Eshows a semiconductor die composite500bwith the exposed tapering dicing stripes365.

An etch process with an isotropic component selectively recesses the semiconductor portions100between the dicing stripes365and partially undercuts the tapering dicing stripes365. One or more metal-containing layers are deposited onto the rear side. A thickness of the deposited metal-containing layer(s) is less than a vertical extension of the recess of the semiconductor portions100.

As shown inFIG. 6F, the deposition process forms a back side metallization including second load electrodes320on the second surface102of the semiconductor dies501. Excess portions321of the deposited metal-containing layers cover the exposed surface of the dicing stripes365. The tapering dicing stripes365shadow edge sections of the semiconductor portions100against the deposition process such that edge portions of the second surface102along the lateral outer surface remain exposed.

A further isotropic process effective on the exposed semiconductor portions100may lift off the dicing stripes365.

FIG. 6Gshows the semiconductor die composite500bwith separated semiconductor devices500after removal of the dicing stripes365.

According to another embodiment, the dicing stripes365are sawed through such that a continuous oxide ring surrounds the semiconductor devices500along the second surface102.

The semiconductor device500ofFIG. 7Aincludes an oxide ring230formed from remnants of the dicing stripes365ofFIG. 5G, wherein the semiconductor dies501ofFIG. 5Gare separated by a sawing or laser cutting process cutting through the dicing stripes365. A protection liner235lining the dicing trenches370ofFIG. 5Gmay cover the exposed lateral outer surface103of the semiconductor portion100.

The semiconductor device500ofFIG. 7Bmay be obtained by a similar process using tapering dicing stripes. The lateral outer surface103may be covered by a native semiconductor oxide or by a protection liner deposited to line the dicing trenches370ofFIG. 6F.

In all embodiments, the dicing stripes365, the first reinforcement stripes361and/or the second reinforcement stripes362may be used to separate active areas in the same semiconductor device500from each other, for example low-voltage regions from high-voltage regions or sensor regions from regions conveying the load current.