Methods for the formation of interconnects separated by air gaps

The microelectronic device interconnects are fabricated by a process that utilizes a silicon-based interlayer dielectric material layer, such as carbon-doped oxide, and a chemical mixture selective to materials used in the formation of the interconnects, including, but not limited to, copper, cobalt, tantalum, and/or tantalum nitride, to remove the interlayer dielectric material layer between adjacent interconnects thereby forming air gaps therebetween.

BACKGROUND OF THE INVENTION

1. Field of the Invention

An embodiment of the present invention relates to microelectronic device fabrication. In particular, an embodiment of the present invention relates to methods for forming copper interconnects.

2. State of the Art

The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. These transistors are generally connected to one another or to devices external to the microelectronic device by conductive traces and contacts (hereinafter referred to collectively as “interconnects”) through which electronic signals are sent and/or received.

A typical process of forming interconnects includes patterning a photoresist material on an interlayer dielectric material and plasma etching the interlayer dielectric material through the photoresist material pattern to form a hole and/or a trench (hereinafter referred to collectively as an “opening”) extending into the interlayer dielectric material. The photoresist material (which may also include hard mask and antireflective coating layers) is then removed (typically by an oxygen or hydrogen plasma followed by wet cleans or all-wet cleans) and a barrier layer may be deposited within the opening to prevent conductive material (particularly copper and copper-containing alloys), which will be subsequently deposited into the opening, from migrating into interlayer dielectric material. The migration of the conductive material can adversely affect the quality of microelectronic device, such as leakage current and reliability of the interconnects. Thus, a barrier layer is deposited onto a dielectric layer to line the opening. In addition to lining the opening, a separate barrier layer is deposited across a top surface of the dielectric layer.

A seed material may then be deposited on the barrier layer, followed by performing a conventional electroplating process to form a conductive material layer. Like the barrier layer, excess conductive material layer may form on barrier layer covering the dielectric layer. The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes a portion of the conductive material layer and the barrier layer that are not within the opening from the surface of the dielectric material, to form the interconnect structure, which is electrically segregated from other such interconnect structures.

Although this is an effective way of forming an interconnect, as the size of the integrated circuitry decreases, the interlayer dielectric material becomes less able to prevent cross-talk between adjacent interconnects, as will be understood to those skilled in the art. Thus, there has been a movement to completely remove the interlayer dielectric from between the interconnects, thereby allowing an air gap to act as the dielectric (i.e., air has a dielectric constant of 1.0). However, the removal of the interlayer dielectric material has issues. With carbon-based interlayer dielectrics, removal thereof is achieved by a reducing plasma etch chemistry. However, such a removal process can result in interconnect electrical damage and/or corner rounding of the interconnects due to the ion bombardment during the process. With silicon-based interlayer dielectrics, removal thereof is achieved by a fluorine-based wet chemistry, which can potentially damage the interconnect and any capping layer (such as copper and electroless cobalt, respectively) as it is not particularly selectively to such materials. Silicon-based interlayer dielectrics may also be removed with a CFx plasma chemistry, which can result in corner rounding and/or sputtering of the interconnect material (such as copper), as will be understood by those skilled in the art.

Therefore, it would be advantageous to develop techniques to form an interconnect having an air gap dielectric, which reduces or substantially eliminates the potential of damage to the interconnect structure.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

An embodiment of the present invention relates to the fabrication of microelectronic device interconnects, wherein the fabrication process utilizes a silicon-based interlayer dielectric material layer and a chemical mixture selective to materials used in the formation of the interconnect, including, but not limited to, copper, cobalt, tantalum, and/or tantalum nitride, which removes the interlayer dielectric material layer from between adjacent interconnects thereby forming air gaps therebetween.

One embodiment of a process used to form an interconnect according to the present invention, comprises patterning a photoresist material102on a first surface104of a sacrificial dielectric material layer106, as shown inFIG. 1. An anti-reflective coating142and a metal hard mask144may also be utilized, as will be understood to those skilled in the art. The sacrificial dielectric material layer106is preferably a silicon-containing material and may include, but is not limited to, silicon dioxide, silicon nitride, carbon doped oxide, and the like, and may be porous or non-porous. The sacrificial dielectric material layer106is etched through the photoresist material102/anti-reflective coating142/hard mask144patterning to form a hole or trench (hereinafter collectively referred to as “opening108”) extending at least partially through the sacrificial dielectric material layer106from the sacrificial dielectric material layer first surface104thereof, and may extend through the sacrificial dielectric material layer106to a substrate112, such as a dielectric layer, a conductive material, a silicon wafer, and the like, as shown inFIG. 2. It is, of course, understood that the opening108can be formed by any known technique including, but not limited to, ion milling and laser ablation. The photoresist material102/anti-reflective coating142/hard mask144is then removed (typically by an oxygen plasma or hydrogen plasma followed by a cleaning process, such as wet cleans or all-wet cleans), as shown inFIG. 3.

It is, of course, understood that the etching material/process used to form opening108should be selective to the substrate112. However, it is preferred that at least a portion of the substrate112is etched to form a recess therein. This will result in a subsequently formed interconnect being anchored in the substrate112, which will prevent the interconnect from lifting during the subsequent etching process to remove the sacrificial dielectric material layer106, as will be understood to those skilled in the art.

As shown inFIG. 4, a barrier layer122, including but not limited to tantalum, tantalum nitride, titanium, and titanium nitride, may then be formed on sidewall(s)116and a bottom118of the opening108. A barrier layer122is deposited to act as a diffusion barrier, which keeps a subsequently deposited conductive material layer from diffusing into the sacrificial dielectric material layer106. The barrier layer122may be deposited by any means know in the art, including atomic layer deposition, chemical vapor deposition, physical vapor deposition, and the like.

As shown inFIG. 5, a seed material124may be deposited on the barrier layer122by any method known in the art, including atomic layer deposition, chemical vapor deposition, physical vapor deposition, and the like. The seed layer124is generally deposited on the barrier layer122, when an electroplating process will be used to deposit the subsequently deposited conductive material layer, as the deposited seed layer124will provide a surface to which the subsequently deposited conductive material will be electroplated. The seed layer124may be a copper-containing material deposited by chemical or physical deposition techniques. It is, of course, understood that the barrier layer122may be such that it acts a seed, which obviates the need for the use of the seed layer124.

The opening108(seeFIG. 5) is then filled with a conductive material, such as copper, aluminum, alloys thereof, and the like, as shown inFIG. 6, to form a conductive material layer126. In one embodiment, the conductive material may be a copper-containing material, including, but are not limited to, copper (Cu), copper-tin (CuSn), copper-indium (CuIn), copper-cadmium (CuCd), copper-bismuth (CuBi), copper-rutherium (CuRu), copper-rhodium (CuRh), copper-rhenium (CuRe), and copper-tungsten (CuW). The conductive material layer126may be formed by any method known in the art, including, but not limited to, electroplating, chemical vapor deposition, physical vapor deposition, and the like. If a seed layer124is used (seeFIG. 5) with an electroplating process, the seed layer124will be subsumed into the conductive material layer126.

Any portion of the conductive material layer126and the barrier layer122that is not within the opening108(seeFIG. 5) is removed from the sacrificial dielectric material layer first surface104, to form an intermediate interconnect130, as shown inFIG. 7, wherein the sacrificial dielectric material layer abuts at least one side136of the intermediate interconnect130. The removal of the portion of the conductive material layer126may be achieved by any technique known in the art, including, but not limited to, chemical mechanical polish, electropolishing, etching, and the like.

A capping layer132may be optionally formed on an exposed portion of the intermediate interconnect130. In one embodiment, the capping layer132is a cobalt-containing material, such as cobalt tungsten phosphide. The capping layer may be formed by any technique known in the art, including, but limited to, electroless deposition or electroplating techniques. The capping layer132prevents the electromigration and/or diffusion of the conductive material of the interconnect into a subsequently deposited or positioned materials.

As shown inFIG. 9, the sacrificial dielectric material layer106is then removed to form the interconnect140. It is, of course, understood that many interconnects140are formed with each process step, as shown inFIG. 10.

In one embodiment, the sacrificial dielectric material layer106is a silicon-containing material, including, but not limited to, carbon-doped (porous or non-porous), wherein a wet chemistry process is used for its removal. In such an embodiment, the removal of the sacrificial dielectric material layer106can be facilitated by using corrosive chemicals at a high pH, such as a organic hydroxide solution, including, but not limited to a tetra methyl ammonium hydroxide-based (hereinafter “TMAH-based”) solution (either aqueous or organic). The corrosive chemicals are chosen to remove the sacrificial dielectric material layer106for their ability to attack of the silicon-oxygen bonds or the silicon-carbon bonds (if present in the sacrificial dielectric material layer106) therein, thereby removing the sacrificial dielectric material layer106. With high pH solutions, copper containing materials can be self protecting with the formation of CuO2or go into solution based on the solution itself, as will be understood to those skilled in the art.

In a specific embodiment, the chemical mixture for a silicon-containing, sacrificial dielectric material layer106includes a tetra methyl ammonium hydroxide (TMAH) based aqueous or organic solution containing hypochlorite ions (such as from a potassium hypochlorite solution or organic hypochlorite solutions) at a high pH, which has demonstrated high selectivity to the barrier layer122(including Ta and TaN), the conductive material layer126(including copper-containing materials), and the capping layer132(including cobalt-containing materials). In a particular embodiment, the chemical mixture at pH range of about 12 to 14 comprises a TMAH concentration of up to about 10% by volume, preferably between about 5% and 10% by volume, hypochlorite ions in a concentration between about 5% and 15% by volume, and the remainder water (about 80% to 90% by volume). Such chemical mixtures can be obtained from chemical providers, such as Mallinckrodt Baker, Inc. of Phillipsburg, N.J., USA.

The technical advantage of this invention is the selective removal of the sacrificial dielectric material layer106while not significantly affecting the conductive material (e.g., copper-containing material) or the barrier materials (e.g., tantalum and/or tantalum nitride). The chemical mixture maintains interconnect structure geometry intact with little or no corner rounding or recessing of copper surface. Furthermore, the chemical mixture has selectivity to the capping layer132, when it is cobalt-containing material, due to the self-passivation of the cobalt surface resulting from formation of a dual-layer of adsorbed hypochlorite ions and organic cations, as will be understood to those skilled in the art. It has been found that the present process is capable of removing the sacrificial dielectric material layer106from spaces as small as 30 to 40 nanometers.

Examples of the copper interconnects, without a barrier layer or a capping layer, formed with the TMAH-based chemical mixture described above is show inFIGS. 11aand11b, wherein the sacrificial dielectric material layer106(seeFIG. 8) has been substantially completely removed leaving the copper interconnects intact (interconnect lines152shown inFIG. 10aand via-type interconnect structures154shown inFIG. 10b). The process comprised emersion in the TMAH-based chemical mixture or by having the chemical mixture sprayed on top of a spinning wafer on a single-wafer cleans tool, described above, for a duration of between about 20 to 60 minutes, preferably about 30 minutes, at a temperature between about 0 to 70 degrees Celsius, preferably about 60 degrees Celsius.

When a capping layer132(seeFIG. 8) is used for electromigration prevention, as previously discussed, the chemical mixture used to remove the sacrificial dielectric material layer106needs to also be selective to the material used for the capping layer132(e.g., cobalt-containing materials). For cases where in copper interconnects have cobalt-containing capping layers132, it known that cobalt is more unstable than copper over all pH ranges (as can be verified with a Pourbaix diagram). For high pH (e.g., equal to greater than about 11) aqueous mixtures, copper is unaffected due to its self-passivation with cuprous oxide (Cu2O), but cobalt is unstable. However, it has been found that the use of an aqueous high pH chemical mixture containing hypochlorite ions and organic cations (such as TMA+) results in a dramatically reduced etch rate of cobalt, even at pH of 12 or greater. This is remarkable given how unstable cobalt is at high pH region. This protection or non-removal of cobalt after exposure of the sacrificial dielectric material layer to the chemical TMAH-based chemical mixture described above is shown inFIG. 12, wherein the exposure duration was about an hour.

It is also understood that the deposition of the cobalt-containing capping layer132on copper interconnects140prior to the removal of the sacrificial dielectric material layer106should be performed due to the cobalt particles that are inherent to electroless cobalt deposition step. If the cobalt-containing capping layer132is formed after the sacrificial dielectric material layer106is removed, there is a potential that cobalt particles could form a structure in the air spaces between the copper interconnects140. This could lead to shorting or higher between copper interconnects140, which, of course, must be avoided. Thus, there is a need for the cobalt-selective, sacrificial dielectric material layer106removal chemical mixture, which the present invention satisfies.

It is, of course, understood that although the present invention has been described in terms of the formation of a single interconnect140, multiple interconnects140are formed simultaneously, and that further processing from layers of such interconnects140.FIGS. 13 and 14illustrates, as a schematic and an XSEM, respectively, a plurality of interconnects140on a first substrate162, such as dielectric layer, having air gaps160therebetween (a second substrate164, such as a dielectric layer, is shown abutting the interconnects140opposing the first substrate162).

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.