Method for forming micro-electro-mechanical system (MEMS) device structure

A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

BACKGROUND

Micro-electro mechanical system (MEMS) devices have recently been developed. MEMS devices include devices fabricated using semiconductor technology to form mechanical and electrical features. Examples of the MEMS devices include gears, levers, valves, and hinges. The MEMS devices are implemented in accelerometers, pressure sensors, microphones, actuators, mirrors, heaters, and/or printer nozzles.

Although existing devices and methods for forming the MEMS devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments for forming a micro-electro-mechanical system (MEMS) device structure are provided.FIGS. 1A-1Qshow cross-sectional representations of various stages of forming a micro-electro-mechanical system (MEMS) device structure100, in accordance with some embodiments of the disclosure.

As shown inFIG. 1A, a first substrate102is provided. In some embodiments, the first substrate102is a wafer. The first substrate102may be made of silicon or other semiconductor materials. In some embodiments, the first substrate102is a complementary metal-oxide (CMOS) semiconductor substrate or a CMOS wafer. Alternatively or additionally, the first substrate102may include other elementary semiconductor materials such as germanium. In some embodiments, the first substrate102is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the first substrate102is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the first substrate102includes an epitaxial layer.

The first substrate102includes a device region108. Some device elements are formed in the device region108. The device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements. Various processes are performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and/or other applicable processes. In some embodiments, the device elements are formed in the first substrate102in a front-end-of-line (FEOL) process.

The first substrate102may include various doped regions such as p-type wells or n-type wells). The doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the first substrate102, in a P-well structure, in an N-well structure or in a dual-well structure.

The isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features may be formed in the device region108. The isolation features may define and isolate various the device elements.

As shown inFIG. 1A, an interconnect structure110is formed on the device region108. The interconnect structure110includes multiple conductive features formed in a first dielectric layer120(such as inter-metal dielectric, IMD). The first dielectric layer120includes a single layer or multiple dielectric layers. The first dielectric layer120is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, or a combination thereof. In some embodiments, the first dielectric layer120is formed by a chemical vapor deposition (CVD) process, a spin-on process, a sputtering process, or a combination thereof.

In some embodiments, the first dielectric layer120is made of an extreme low-k (ELK) dielectric material with a dielectric constant (k) less than about 2.5. With geometric size shrinking as technology nodes advance to 30 nm and beyond, ELK dielectric material is used to minimize device RC (time constant, R: resistance, C: capacitance) delay. In some embodiments, ELK dielectric materials include carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxycarbide polymers (SiOC). In some embodiments, ELK dielectric materials include a porous version of an existing dielectric material, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), or porous silicon oxide (SiO2).

The conductive features include a first conductive via122, a conductive line124and a second conductive via126. The first conductive via122is electrically connected to the conductive line124, and the conductive line124is electrically connected to the second conductive via126. In some embodiments, the conductive features is made of metal materials, such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nickel (Ni), silver (Ag), gold (Au), indium (In), tin (Sn) or a combination thereof. In some embodiments, the conductive features are formed by electro-plating, electroless plating, sputtering, chemical vapor deposition (CVD) or another applicable process.

An outgassing prevention layer130is formed on the interconnect structure110. The outgassing prevention layer130prevents gases (e.g., oxygen, carbon dioxide, other gases, and/or any combinations thereof) from outgassing from the interconnect structure110. The outgassing prevention layer130includes one or more layers. In some embodiments, the outgassing prevention layer130is made of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbon nitride or a combination thereof.

A number of electrodes140are formed over the outgassing prevention layer130. The electrodes140are electrically connected to the second conductive via126. In some embodiments, the electrodes140are made of conductive materials, such as metal materials. The metal materials may be copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nickel (Ni), silver (Ag), gold (Au), indium (In), tungsten (W), tin (Sn), cobalt (Co), platinum (Pt), germanium (Ge) or a combination thereof. In some embodiments, the electrodes140are formed by a deposition process and a patterning process. The deposition process includes electro-plating, electroless plating, sputtering, chemical vapor deposition (CVD) or another applicable process. The patterning process includes a photolithography process and an etching process. The photolithography processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

Afterwards, as shown inFIG. 1B, a gas absorption layer150is conformally formed over the electrodes140and the outgassing prevention layer130, in accordance with some embodiments of the disclosure. The gas absorption layer150absorbs gases. In some embodiments, the gas absorption layer150is made of metal materials, such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), silver (Ag), gold (Au), indium (In), tungsten (W), tin (Sn), cobalt (Co), platinum (Pt), germanium (Ge) or a combination thereof.

Afterwards, as shown inFIG. 1C, a portion of the gas absorption layer150is removed to form a gas getter structure152, in accordance with some embodiments of the disclosure. In some embodiments, the portion of the gas absorption layer150is removed by a patterning process. The patterning process includes a photolithography process and an etching process. The etching process may be a dry etching process or a wet etching process.

Next, as shown inFIG. 1D, a second dielectric layer160is formed over the outgassing prevention layer130, the electrodes140and the gas getter structure152, in accordance with some embodiments of the disclosure. The second dielectric layer160includes a single layer or multiple dielectric layers. In some embodiments, the second dielectric layer160is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, or a combination thereof. In some embodiments, the second dielectric layer160is formed by a chemical vapor deposition (CVD) process, a spin-on process, a sputtering process, or a combination thereof.

Afterwards, as shown inFIG. 1E, a portion of the second dielectric layer160is removed to form a cavity202, a channel204, a first trench206and a second trench208, in accordance with some embodiments of the disclosure. In some embodiments, the portion of the second dielectric layer160is removed by a patterning process. The patterning process includes a photolithography process and an etching process. The etching process may be a dry etching process or a wet etching process.

The cavity202is formed between the electrodes140and gas getter structure152, and the channel204is directly formed above the electrodes140. The channel204is connected to the cavity202. The channel204is laterally extended from the cavity202. The first trench206and the second trench208are outside of the cavity202.

Afterwards, as shown inFIG. 1F, a second substrate302is above the first substrate102, in accordance with some embodiments of the disclosure. In some embodiments, the second substrate302is a MEMS substrate. In some embodiments, the first substrate102is a CMOS wafer, and the second substrate302is a MEMS wafer.

The material of the second substrate302may be the same as the material of the first substrate102. The second substrate302may be made of silicon (Si), silicon-based materials, or other semiconductor materials, such as germanium (Ge). In some embodiments, the second substrate302is a semiconductor substrate, such as a silicon (Si) wafer. In some embodiments, the second substrate302is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide.

Afterwards, as shown inFIG. 1G, the second substrate302is bonded to the first substrate102by bonding the second substrate302and the second dielectric layer160. In some embodiments, the second substrate302is bonded to the first substrate102by performing a fusion bonding process. As a result, the cavity202and the channel204are surrounded or enclosed by the electrodes140and the second substrate302. The first trench206and the second trench208are enclosed by the second dielectric layer160and the second substrate302.

Note that after the second substrate302is bonded to the second dielectric layer160, the inside region, such as the channel204, or the cavity202are in a vacuum condition. But, the outside of the second substrate302is at an ambient pressure, for example, atmospheric pressure. Therefore, the second substrate302is bent because the outer pressure (e.g. 1 atm) is greater than the inner pressure (e.g. close to vacuum). As shown inFIG. 1G, a portion of the second substrate302is bent to form a concave structure.

Afterwards, a photoresist layer304is formed over the second substrate302, and the photoresist layer304is patterned to form a patterned photoresist layer304, in accordance with some embodiments of the disclosure. The patterned photoresist layer304has a number of openings305.

Next, an etching process is performed on the second substrate302to form a number of first holes315and the second holes317, as shown inFIG. 1K. The etching process includes a number of etching cycles, and each of the etching cycles includes the following three steps as shown inFIGS. 1H-1J. The three steps are repeated until the first holes315and the second holes317have predetermined depth D1. The predetermined depth D1is the thickness of the second substrate302.

Afterwards, as shown inFIG. 1H, a deposition step11is performed to form a protection layer310in the openings305and on the patterned photoresist layer304, in accordance with some embodiments of the disclosure. The protection layer310is made of fluorocarbon compound and is used to protect the sidewall of the openings305of the patterned photoresist layer304.

The deposition step11is a plasma process. The deposition step11is performed using a fluorocarbon gas including octafluorocyclobutane (C4F8), tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2) or a combination thereof.

Next, as shown inFIG. 1I, a stripping step13is performed to remove a portion of the protection layer310, in accordance with some embodiments of the disclosure. More specifically, a bottom of the protection layer310is removed to expose a portion of the second substrate302. During the stripping step13, the second substrate302is bent to have a concave structure because the outer pressure (e.g. 1 atm) is greater than the inner pressure (e.g. close to vacuum).

The stripping step13is a plasma process. The deposition step11is performed using a gas including sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8).

Afterwards, as shown inFIG. 1J, an etching step15is performed to remove a portion of the second substrate302, in accordance with some embodiments of the disclosure. The etching step15is performed using an etching gas that may include sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8).

Afterwards, the processing steps ofFIGS. 1H-1Jmay be repeated until the second substrate302is etched through. One etching cycle includes the step ofFIGS. 1H-1J. After a number of etching cycles, the second substrate302is etched through to form the first hole315and the second hole317.

FIG. 2Ashows the relationship between the etching time and the number of cycles of the etching step15, in accordance with some embodiments of the disclosure. The etching step15has two stages including a first stage15aand a second stage15b. In some embodiments, the first stage is a main etching stage, and the second stage is an over etching stage. It should be noted that the etching step15is changed from the first stage15ato the second stage15bwhen the intermediated depth D2of the first hole315is in a range from about 70% to about 80% of the predetermined depth D1. If the range is smaller than 70%, the second stage15bmay be initiated too early, and the etching strength may be too strong to etch fast. Once the etching rate is increased too high and thus the etching depth of the second substrate302is difficult to control. If the range is greater than 80%, the second stage15bmay be initiated too late, and the etching strength may not be strong enough to remove all of the by-products. Therefore, some unwanted remaining polymer may be left in the first hole315and the second hole317to degrade the performance of the MEMS device structure100.

During the first stage15a, the etching time of each of the etching steps15is a constant value as the number of etching cycle is increased. During the second stage15b, the etching time of each of etching steps15is gradually increased as the number of etching cycle is increased. The etching time of the second stage15bis greater than the etching time of the first stage15a. Therefore, more by-products, such as unwanted polymer may be removed completely by the etching step15in the second stage15b.

In some embodiments, during the first stage15a, the etching time of the etching step15in each etching cycle is in a range from about 2.2 seconds to 2.6 seconds. During the second stage15b, the etching time of the etching step15in each etching cycle has a linear distribution, and the etching time is gradually increased as the number of etching cycle is increased. In some embodiments, the etching time of the etching step15in each etching cycle is in a range from about 3.8 seconds to 4.2 seconds.

In some embodiments, the etching process includes twenty etching cycles. In the first stage15a, the etching time of the etching step15is a constant value, such as 2.4 seconds from the first etching cycle to fifteenth etching cycles. In the second stage15b, the etching time of the etching step15is gradually increased, such as from 3.8 seconds to 4.2 seconds, from sixteenth etching cycles to twentieth etching cycles.

FIG. 2Bshows the relationship between the flow rate of the etching gas in the etching step15and the number of cycles, in accordance with some embodiments of the disclosure. During the first stage15a, the flow rate of the etching gas of each of the etching steps15is a constant value as the number of etching cycles is increased. During the second stage15b, the flow rate of the etching gas of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased. In some embodiments, during the first stage15a, the flow rate of the etching gas of the etching step15in each etching cycle is in a range from about 225 sccm to about 225 sccm. In some embodiments, during the second stage15b, the flow rate of the etching gas of the etching step15in each etching cycle is in a range from about 270 sccm to about 330 sccm.

It should be noted that if some unwanted by-products are remaining in the second hole317, the by-products may flow into the cavity202or the channel204to pollute the electrodes140by the subsequent fabricating processes. In addition, the second hole317may not be completely filled with the metal materials (formed later, shown inFIG. 1M) due to some voids may be formed in the second hole317. By solving the by-products problems, the etching step15is divided into two-stage etching operations. The unwanted by-products are removed completely by the over etching operation of the second stage15b. Therefore, the performance of the MEMS device structure100is improved.

Afterwards, as shown inFIG. 1K, after the etching process is completed, the first hole315and the second hole317are formed in the second substrate302, in accordance with some embodiments of the disclosure. The opening width of the second hole317is smaller than the opening width of the first hole315. The first hole315is connected to the cavity202. The second hole317is connected to the first trench206. When the first hole315is connected to the cavity202, the ambient pressure, for example, atmospheric pressure (e.g. 1 atm) is in the first hole315and the cavity202. Therefore, the bended second substrate302is recovered to have a planar structure.

Afterwards, as shown inFIG. 1L, a cleaning process17is performed on the first hole315and the second hole317, in accordance with some embodiments of the disclosure. The cleaning process17is used to remove any residual material left in the first hole315and/or the second hole317. If the solvent is left in the first hole315and/or the second hole317, the solvent may be heated by the subsequent processes to form vapor gas. If too much vapor gas is left in the cavity202and/or the channel204, the pressure of the cavity202may be increased because too much vapor gas accumulates inside of the second substrate302. Therefore, the second substrate302may be pushed out due to the high pressure and the risk of the peeling of the second substrate302is increased.

It should be noted that the cleaning process17is a dry plasma process and does not comprise a wet cleaning process to avoid any solvent left in the first hole315, the second hole317, and in the cavity202. If the solvent flows into the cavity202, the electrodes140may be damaged and the detection of the electrodes140may be affected. In some embodiments, the cleaning process17is performed using an oxygen (02) plasma.

It should be noted that the cleaning process17and the etching process (including the deposition step11, stripping step13and etching step15) are performed in the same chamber. In other words, the cleaning process17and the etching process are performed in-situ without transferring the MEMS device structure100to another chamber. Therefore, the pollution problems are reduced, and the fabrication time and cost are reduced.

Before the step ofFIG. 1M, an exhaust process is performed to exhaust air inside of the first hole315and the second hole317. In other words, the air in the cavity202and the channel204are exhausted. As a result, the cavity202and the channel204are in a vacuum state. The cleaning process17and the exhaust process are performed in-situ without transferring the MEMS device structure100to another chamber. Therefore, the pollution problems are reduced, and the fabrication time and cost are reduced.

Next, as shown inFIG. 1M, a conductive layer402is formed in the first hole315and the second hole317, and a third dielectric layer404is formed in the conductive layer402, in accordance with some embodiments of the disclosure.

Afterwards, as shown inFIG. 1N, a portion of the conductive layer402and a portion of the third dielectric layer404are removed to form a first plug406and a second plug408, in accordance with some embodiments of the disclosure. The portion of the conductive layer402and the portion of the third dielectric layer404are removed by a patterning process. The patterning process includes a photolithography process and an etching process. Examples of the photolithography process include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing photoresist, rinsing and drying (e.g., hard baking). The etching process may be a dry etching process or a wet etching process.

After the patterning process, the photoresist layer is removed by a removal step. The removal step includes four steps.FIG. 3shows a block diagram of the removal process for removing the photoresist layer, in accordance with some embodiments of the disclosure. The MEMS device structure100is put in a first cleaning solution10, a second cleaning solution20, a third cleaning solution30and a spin-dryer40in sequence.

It should be noted that the removal process includes four steps. In the first step, a first cleaning step is performed on the MEMS device structure100using a first cleaning solution10. The first cleaning solution10is capable of removing residual organic photoresist material. In some embodiments, the first cleaning solution10is made of amine-based solution. In some embodiments, EKC270, manufactured by EKC Technology, Inc. of Danville, Calif. is used as the first cleaning solution10. In some other embodiments, the first cleaning solution10is made of fatty alcohol solution. In some embodiments, AP841 is used as the first cleaning solution10.

Next, a second cleaning step is performed on the MEMS device structure100using a second cleaning solution20. The second cleaning solution10is a buffer solution and is used to remove the first cleaning solution10. In some embodiments, the second cleaning solution10is N-methylpyrrolidone (NMP). The polarity of the second cleaning solution20is close to that of the first cleaning solution10, and therefore the second cleaning solution20may be completely removed by the first cleaning solution. In some embodiments, the contact angle between the first cleaning solution10and the second cleaning solution20is in a range from about 60 degrees to about 80 degrees. In some embodiments, the first cleaning solution10is AP841 and the second cleaning solution20is NMP, and a contact angle between the first cleaning solution10and the second cleaning solution20is about 80 degrees.

Afterwards, a third cleaning step is performed on the MEMS device structure100using water to rinse the MEMS device structure100. Water is used to completely remove the first cleaning solution10and the second cleaning solution20.

Finally, a spin drying step is performed using a spin-dryer40to remove all solvents used in the previous steps. It should be noted that the spin drying step is a dry step to prevent any wet solvents from leaking into the cavity202and/or the channel204the MEMS device structure100. If the solvent flows into the cavity202and/or the channel204, the performance of the MEMS device structure100may be degraded.

Afterwards, as shown inFIG. 1O, a portion of the second substrate302is removed to form a third hole319, in accordance with some embodiments of the disclosure. In some embodiments, the portion of the second substrate302is removed by an etching process, such as a dry etching process or a wet etching process.

Next, as shown inFIG. 1P, a passivation layer410is formed on the first plug406, the second plug408, the remaining second substrate302and the third hole319, in accordance with some embodiments of the disclosure. The passivation layer410is used to prevent gases and moisture from diffusing from the environment to the cavity202and/or the channel204.

Next, as shown inFIG. 1Q, a portion of the passivation layer410is removed, in accordance with some embodiments of the disclosure. The portion of the passivation layer410is removed by a patterning process. The patterning process includes a photolithography process and an etching process.

After the patterning process, the photoresist layer (not shown) is removed by a removal step. The removal step includes four steps, for example, shown inFIG. 3. The removal step includes performing a first cleaning step, performing a second cleaning step, performing a third cleaning step and performing a spin drying step. The remaining photoresist layer is removed completely by above four steps to prevent the solvents from leaking into the cavity202and/or the channel204.

In some embodiments, the MEMS device structure100is a pressure sensor which includes a flexible membrane arranged over a cavity hermetically sealed with a reference pressure. Assuming the reference pressure is steady, the flexible membrane deflects in proportion to the difference between the environmental pressure and the reference pressure.

Embodiments for forming a micro-electro-mechanical system (MEMS) device structure are provided. A second substrate is formed over a first substrate, and a cavity is formed between the first substrate and the second substrate. The second substrate is etched to by an etching process to form a hole through the second substrate, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased. The etching quality of the etching step15is improved by using a two-stage etching operation. The unwanted by-products are removed completely by the two-stage etching operation. Therefore, the performance of the MEMS device structure is improved.

Furthermore, during fabrication of the MEMS device structure, the photoresist layer is removed by a removal step. The removal step includes four steps. The final step does not include a wet cleaning process, and therefore the solvents in the removal step are completely removed. Therefore, the solvent does not flow into the cavity and/or the channel inside of the MEMS device structure.

In some embodiments, a method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

In some embodiments, a method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming an electrode over a substrate and forming a cavity over the electrode. The method also includes forming a MEMS substrate over the substrate, and the cavity is formed between the first substrate and the MEMS substrate. The method further includes performing a dry etching process on the MEMS substrate to form a hole in the MEMS substrate, and the dry etching process includes a plurality of etching cycles. Each of the etching cycles includes performing a deposition step to form a protection layer on the opening, performing a stripping step to remove a portion of the protection layer, and performing an etching step to etch a portion of the MEMS substrate.

In some embodiments, a method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming an electrode over a first substrate and forming a cavity adjacent to the electrode. The method also includes forming a MEMS substrate over the electrode, and the cavity is surrounded by the first substrate and the MEMS substrate. The method further includes forming a hole through the MEMS substrate by a dry etching process and performing a cleaning process on the hole after the dry etching process. The cleaning process does not comprise a wet cleaning process.