PWM signal generator and switching power supply device having same

A PWM signal generator includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generates the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.

TECHNICAL FIELD

This disclosure relates to a switching power supply device that controls an output voltage by performing a switching operation with a pulse width modulation (PWM) method and a PWM signal generator used in the switching power supply device.

BACKGROUND

In a switching power supply device that controls an output voltage by performing a switching operation using a switching element such as a transistor, variable control of a duty, which is a ratio of an ON-period of the switching element to a switching cycle of the switching element, is performed to control the output voltage so as to be constant.

Devices that generate a PWM signal for performing PWM control are classified into an analog type and a digital type. Examples of a digital type PWM signal generator are described in JP-A-2004-343395 and JP-A-2006-527569.

JP-A-2004-343395 describes a PWM signal generator that uses a ring oscillator including plural differential buffers, which are connected in cascade, to generate a PWM signal with a resolution of a delay time corresponding to one stage of the differential buffers.

JP-A-2006-527569 describes a PWM signal generator that includes plural voltage-controlled buffers connected in series and a delay locked loop (DLL) controlling a delay time of each voltage-controlled buffer so as to be constant.

SUMMARY

In the PWM signal generator described in JP-A-2004-343395, the delay times of the differential buffers vary due to an influence of PVT (Process, Voltage, and Temperature). Accordingly, there is a possibility that a clock frequency of a counter using the output signal of the ring oscillator as a clock will also vary, and thus the resolution of the switching cycle or the duty will become an undesired value.

It may be considered that a DLL circuit such as in the device described in JP-A-2006-527569 is used in the PWM signal generator described in JP-A-2004-343395. However, addition of the DLL circuit causes an increase in circuit scale. Meanwhile, since the DLL circuit needs to be re-designed due to a change in semiconductor manufacturing processes, design costs may be increased. When the DLL circuit is used, it is concerned that there are a lot of restrictions such the lowest operation clock frequency, the setting order.

This disclosure is made in consideration of the above-mentioned circumstances and is to provide a PWM signal generator, which is able to prevent an increase in circuit scale or design cost and which generates a PWM signal with a desired resolution, and a switching power supply device including the PWM signal generator.

A PWM signal generator of this disclosure includes a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generate the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.

A switching power supply device includes: a switching element; the above described PWM signal generator; and a PWM control unit, which controls the switching element based on the PWM signal generated by the PWM signal generator.

According to this disclosure, it is possible to provide a PWM signal generator that is able to prevent an increase in circuit scale or design cost and that generate a PWM signal with a desired resolution and a switching power supply device including the PWM signal generator.

DETAILED DESCRIPTION

Hereinafter, embodiments of this disclosure will be described with reference to the accompanying drawings.

FIG. 1is a circuit diagram schematically illustrating a configuration of a PWM signal generator100used for a switching power supply device according to an embodiment of this disclosure. The switching power supply device includes switching elements such as MOSFETs and a PWM control unit that controls the switching elements based on a PWM signal generated by the PWM signal generator100.

The PWM signal generator100includes a delay circuit unit20, a PWM signal output unit30, a hardware correction circuit40, a counter4, a comparator5A, a selector5B, an AND circuit5C, a comparator6A, a selector6B, and an AND circuit6C.

The delay circuit unit20includes a delay element group having plural (2′ (where n is a natural number equal to or greater than 1) in the example illustrated inFIG. 1) delay elements3connected in series, an AND circuit2, and an OR circuit1. Each delay element3is an element that outputs an input signal with a delay of a predetermined time and employs a general buffer or the like.

The output terminal of the delay element3in the final stage of the delay element group is connected to an input terminal of the counter4and one input terminal of two input terminals of the OR circuit1.

A pulse signal is input to the other input terminal of the two input terminals of the OR circuit1from a system control unit (not illustrated) which controls the entire switching power supply device. An output terminal of the OR circuit1is connected to one input terminal of two input terminals of the AND circuit2.

An enable signal for activating the operation of the delay circuit unit20is input to the other input terminal of the two input terminals of the AND circuit2from the system control unit. An output terminal of the AND circuit2is connected to an input terminal of the delay element3in an initial stage of the delay element group.

When a starting pulse signal is input to the OR circuit1in a state where the enable signal is at a high level, in response to rising of this pulse signal, the output of the OR circuit1is changed to a high level and the output of the AND circuit2is changed to a high level with the rising of the pulse signal, and thus the pulse signal is input to the delay element group. The starting pulse signal is input only once to the OR circuit1and then becomes a low level.

The delay element group delays the pulse signal in each delay terminal3. A pulse signal output from the delay element3in the final stage of the delay element group is input to the OR circuit1, the output of the OR circuit1is changed to the high level, and the pulse signal is output from the AND circuit2. Accordingly, the pulse signal circulates in the delay circuit unit20.

The counter4counts the pulse signal output from the delay element3in the final stage of the delay element group, thereby counting a cycle in which the pulse signal circulates once in the delay circuit unit20. The count value counted by the counter4is input to the hardware correction circuit40, the comparator5A, and the comparator6A.

Even when an output signal of any element of all the elements including the AND circuit2and the 2ndelay elements3in the delay circuit unit20is input to the counter4, the cycle is able to be counted.

The output terminals of the delay elements3of the delay element group are connected to the input terminal of the selector5B and the input terminal of the selector6B.

Low-order n bits of a duty comparison value CMPd of a digital value generated by the hardware correction circuit40are input to the selector5B. The duty comparison value CMPd is information which is used to determine the length of the ON-period of a switching element.

The selector5B selects and outputs any one of the output signals of the 2ndelay elements3of the delay element group based on the low-order n bits of the input duty comparison value CMPd. The output terminal of the selector5B is connected one of two input terminals of the AND circuit5C.

The output terminal of the comparator5A is connected to the other of the two input terminals of the AND circuit5C. When the output of the comparator5A is changed to a high level, the AND circuit5C outputs the signal selected by the selector5B as a duty event pulse to the PWM signal output unit30.

The output signal of the counter4and the high-order bits of the duty comparison value CMPd are input to the comparator5A. The comparator5A compares the output signal of the counter4which is input to the comparator with the high-order bits of the duty comparison value CMPd and outputs a high-level signal to the AND circuit5C when both are identical each other.

Low-order n bits of a cycle comparison value CMPp of a digital value generated by the hardware correction circuit40are input to the selector6B. The cycle comparison value CMPp is information which is used to determine a start timing of the ON-period of a switching element.

The selector6B selects and outputs any one of the output signals of the 2ndelay elements3of the delay element group according to the input low-order n bits of the cycle comparison value CMPp. The output terminal of the selector6B is connected to one of two input terminals of the AND circuit6C.

The output terminal of the comparator6A is connected to the other of the two input terminals of the AND circuit6C. When the output of the comparator6A is changed to a high level, the AND circuit6C outputs the signal selected by the selector6B as a cycle event pulse to the PWM signal output unit30.

The output signal of the counter4and the high-order bits of the cycle comparison value CMPp are input to the comparator6A. The comparator6A compares the output signal of the counter4which is input to the comparator with the high-order bits of the cycle comparison value CMPp and outputs a high-level signal to the AND circuit6C when both are identical each other.

The PWM signal output unit30outputs a PWM signal which rises in response to the rising of the cycle event pulse and falls in response to the rising of the duty event pulse. Specifically, the PWM signal output unit30includes an AND circuit7, an AND circuit8, an OR circuit9, an AND circuit10, an AND circuit11, an OR circuit12, and an RS type flip-flop13.

The output signal (cycle event pulse) of the AND circuit6C and a cycle event terminal level setting signal from the system control unit are input to the input terminals of the AND circuit7.

The output signal (duty event pulse) of the AND circuit5C and a duty event terminal level setting signal from the system control unit are input to the input terminals of the AND circuit8.

The output signal (cycle event pulse) of the AND circuit6C and an inverted signal of the cycle event terminal level setting signal are input to the input terminals of the AND circuit10.

The output signal (duty event pulse) of the AND circuit5C and an inverted signal of the duty event terminal level setting signal are input to the input terminals of the AND circuit11.

The output signal of the AND circuit7and the output signal of the AND circuit8are input to the OR circuit9. The output terminal of the OR circuit9is connected to a setting terminal S of the RS type flip-flop13.

The output signal of the AND circuit10and the output signal of the AND circuit11are input to the OR circuit12. The output terminal of the OR circuit12is connected to a reset terminal of the RS type flip-flop13.

FIG. 2is a timing chart illustrating operations of the PWM signal output unit30of the PWM signal generator100illustrated inFIG. 1.FIG. 2illustrates a case in which the cycle event terminal level is set to 1 (high level) and the duty event terminal level is set to 0 (low level).

As illustrated inFIG. 2, when the cycle event pulse is changed to a high level, the output of the AND circuit7is changed to a high level, the output of the OR circuit9is changed to a high level, the RS type flip-flop13is changed to a set state, and the PWM signal rises. Then, when the duty event pulse is changed to a high level, the output of the AND circuit11is changed to a high level, the output of the OR circuit12is changed to a high level, the RS type flip-flop13is reset, and the PWM signal falls. In this way, the PWM signal is generated based on the cycle event pulse and the duty event pulse.

FIG. 3is a circuit diagram specifically illustrating the configuration of the hardware correction circuit40of the PWM signal generator100illustrated inFIG. 1.

The hardware correction circuit40includes a delay-amount detector40A and a digital value generator40B.

The delay-amount detector40A is a circuit which is constructed by hardware to detect an amount of delay of a signal due to the delay circuit unit20.

Specifically, the delay-amount detector40A includes a measurement cycle counter41, a reference value register42, a measured value register43, and a subtractor44.

The measurement cycle counter41outputs a capture signal to the reference value register42and the measured value register43for every unit period depending on a reference clock.

The measured value register43is a first register that holds the count value of the counter4at an input timing where the capture signal is input.

When a capture signal is input, the reference value register42is a second register that holds the count value of the counter4at an input timing where the capture signal is input immediately previous to the input timing. That is, the count value at a first timing where the capture signal is input is held in the measured value register43, and the count value at a second timing which is previous to the first timing by a unit period is held in the reference value register42.

The subtractor44subtracts the count value held in the reference value register42from the count value held in the measured value register43. The subtraction result (count value (A)) is a count value counted by the counter4in the unit period. The output value of the subtractor44is a time (amount of delay) by which delayed by the delay circuit unit20in the unit period. In this way, the delay-amount detector40A detects the output value of the subtractor44as an amount of delay of a signal due to the delay circuit unit20.

The digital value generator40B is a circuit which is constructed by hardware to correct predetermined data (cycle comparison value CMPpo) based on the count value (A), which is an amount of delay detected by the delay-amount detector40A, thereby generating the cycle comparison value CMPp and the duty comparison value CMPd.

Specifically, the digital value generator40B includes a divider45, a multiplier46, a multiplier47, and a comparison value generator48.

The output value (count value (A)) of the subtractor44and a predetermined expected count value (C) are input to the divider45. The expected count value (C) is a designed value of the amount of delay by the delay circuit unit20, and a cycle setting value and a duty setting value as a setting values corresponding to the cycle comparison value CMPpo are determined in advance based on the designed value and are stored in a storage unit (not illustrated) of the PWM signal generator100.

The divider45divides the count value (A) by the expected count value (C) and outputs the division result as a correction coefficient. The divider45is constructed by hardware.

The expected count value (C) is not particularly limited, but it is preferable that the expected count value be set to 2kwhere k is a natural number equal to or greater than 1. By setting the expected count value (C) to 2k, the calculation of count value (A)/expected count value (C) is able to be realized by k-bit shift of the count value (A) to the right. That is, since the divider45is able to be constructed by a simple bit shifter (shifter), it is possible to simplify the configuration of the hardware correction circuit40.

The correction coefficient output from the divider45and the cycle setting value stored in the storage unit are input to the multiplier46. The multiplier46generates a post-correction cycle setting value DOUTp by multiplying the correction coefficient by the cycle setting value.

The correction coefficient output from the divider45and the duty setting value stored in the storage unit are input to the multiplier47. The multiplier47generates a post-correction duty setting value DOUTd by multiplying the correction coefficient by the duty setting value.

The comparison value generator48generates a cycle comparison value CMPp by adding the cycle setting value DOUTp output from the multiplier46to the cycle comparison value CMPpo corresponding to the cycle setting value read from the storage unit. The comparison value generator48generates a duty comparison value CMPd by adding the duty setting value DOUTd output from the multiplier47to the generated cycle comparison value CMPp.

In the digital value generator40B, the positions of the divider45and the multipliers46and47may be reversed. That is, the cycle setting value DOUTp may be calculated by causing the multiplier46to multiply the count value (A) by the cycle setting value and causing the divider45to divide the resultant value by the expected count value (C). Similarly, the duty setting value DOUTd may be calculated by causing the multiplier47to multiply the count value (A) by the duty setting value and causing the divider45to divide the resultant value by the expected count value (C). When a bit shifter is used as the divider45, there is a possibility that a rounding error of low-order bits will occur due to the k-bit shift to the right, but by multiplying ahead like this, calculation errors of the cycle setting value and the duty setting value due to this error is able to be minimized.

In the PWM signal generator100having this configuration, the amount of delay of a signal due to the delay circuit unit20is designed to a desired value, but the amount of delay may be deviated from the desired value due to an influence of PVT. The deviation of the amount of delay from the designed value is calculated as a count value (A) for each unit period by the delay-amount detector40A of the hardware correction circuit40. The cycle comparison value CMPpo is appropriately corrected based on the correction coefficient which is the ratio of the count value (A) and the expected count value (C), and the cycle comparison value CMPp and the duty comparison value CMPd are appropriately corrected.

Accordingly, the deviation of the amount of delay of a signal due to the delay circuit unit20is able to be absorbed by the correction of the cycle comparison value CMPp and the duty comparison value CMPd, and it is thus possible to realize an increase in resolution of a PWM signal while maintaining a desired cycle and a desired duty.

In the PWM signal generator100, deviations of the degrees of delay of the individual delay elements3of the delay circuit unit20from the designed value are not detected, but the deviation of the amount of delay of the delay circuit unit20from the designed value as a whole is detected. In this way, since it is not necessary to detect the deviations of the degrees of delay of the individual delay elements3, it is possible to simplify the device and thus to reduce manufacturing costs.

In the PWM signal generator100, the delay elements3of the delay circuit unit20is able to be constructed by simple buffers. Accordingly, in comparison with the related art in which the voltage-controlled buffers or the differential buffers are used, it is possible to reduce the manufacturing costs of the PWM signal generator100. Unlike the related art, it is not necessary to use the DLL circuit. Accordingly, it is possible to reduce the design costs and to reduce restrictions on the lowest clock frequency, the setting order, and the like.

In the PWM signal generator100, the delay-amount detector40A and the digital value generator40B are embodied by hardware, not by software. Accordingly, it is not necessary to enhance the processing capability of the system control unit (CPU) of the switching power supply device, and thus it is possible to prevent an increase in costs of the power supply device.

In the PWM signal generator100, the hardware correction circuit40is able to be operated based on a reference clock in asynchronism with a part other than the hardware correction circuit40. Accordingly, it is possible to facilitate designing of the switching power supply device.

While this disclosure has been described above with reference to specific embodiments, the embodiments are only examples and is able to be modified in various forms without departing from the gist of this disclosure.

For example, the hardware correction circuit40is constructed by hardware, but the function of the hardware correction circuit40may be embodied by software.

In consideration of the delay time of a signal by the OR circuit1and the AND circuit2included in the delay circuit unit20, the number of delay elements3included in the delay element group may be reduced by one may be set to 2n−1. By setting the delay time of a signal by the OR circuit1and the AND circuit2to be the same as the delay time of the delay elements3, it is possible to facilitate designing of the cycle comparison value or the duty comparison value.

The delay-amount detector40A performs the process of detecting an amount of delay for every unit period, but the period of time until the detection process is performed next time after the process of detecting an amount of delay is performed may be set to be sufficiently long and the process of detecting an amount of delay may be performed in a period sufficiently longer than the unit period. By correcting the cycle comparison value CMPp and the duty comparison value CMPd for every predetermined period, it is possible to accurately perform the PWM control.

As described above, this specification discloses the followings.

The disclosed PWM signal generator includes: a delay circuit unit, which includes a plurality of delay elements connected in series, an output terminal of the delay element in a final stage among the plurality of delay elements and an input terminal of the delay element in an initial stage among the plurality of delay elements being connected to each other; a selector, which selects any one of output signals of the plurality of delay elements based on a digital value; a PWM signal output unit, which outputs a PWM signal based on the output signal selected by the selector; a delay-amount detector, which detects an amount of delay of a signal due to the delay circuit unit; and a digital value generator, which generate the digital value by correcting predetermined data based on the amount of delay detected by the delay-amount detector.

The disclosed PWM signal generator may further include a counter, which counts a pulse signal output from any delay element among the plurality of delay elements, wherein the delay-amount detector detects a count value, which is counted by the counter in a unit period, as the amount of delay.

In the disclosed PWM signal generator, the digital value generator may generates the data by correcting the digital value based on the count value and a predetermined expected count value in the unit time.

In the disclosed PWM signal generator, the plural delay elements may include 2ndelay elements where n is a natural number equal to or greater than 2, wherein the expected count value is 2kwhere k is a natural number equal to or greater than 1, and wherein the digital value generator generates the digital value by using a value which is obtained by dividing a multiplied value of the count value and a set value corresponding to the data by the expected count value.

In the disclosed PWM signal generator, the digital value generator may include: a multiplier, which multiplies the count value and the set value; and a divider, which divides an output value of the multiplier by the expected count value, and wherein the divider is a bit shifter that acquires a division result by shifting the output value of the multiplier by k bits to the right.

In the disclosed PWM signal generator, the digital value generator may include: a divider configured to divide the count value by the expected count value; and a multiplier configured to multiply an output value of the divider and the set value, and wherein the divider is a bit shifter that acquires a division result by shifting the output value by k bits to the right.

In the disclosed PWM signal generator, the delay-amount detector may include: a measurement cycle counter, which outputs a capture signal for every unit period based on a reference clock; a first register, which holds the count value of the counter at a timing where the capture signal is output; a second register, which holds the count value of the counter at a timing where the capture signal is output previous to the timing the capture signal is output; and a subtractor, which subtracts the count value held in the second register from the count value held in the first register, and wherein the delay-amount detector detects the output value of the subtractor as the amount of delay.

In the disclosed PWM signal generator, the delay-amount detector and the digital value generator may be constructed by hardware.

The disclosed switching power supply device includes: a switching element; the PWM signal generator; and a PWM control unit which controls the switching element based on the PWM signal generated by the PWM signal generator.