Method and apparatus for burst error detection and digital communication device

A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to digital communication devices, and in particular, to an enhanced error-erasure decoding method applicable to a burst error detection mechanism.

2. Description of the Related Art

In a conventional receiver, various types of noise, distortion, and interference are common factors that deteriorate signal quality to render erroneous outputs. Error-correcting coding (ECC) is a prevalent technique to help a receiver resist the above-mentioned factors, reduce the probability of errors, and enhance the reliability of the outputted data.

Concatenated coding is a kind of error-correcting coding technique that implements multiple levels of coding, such as inner coding and outer coding. For example, convolutional codes or Trellis-Coded-Modulation (TCM) codes could be used as the inner codes, which would help to overcome scattered random errors. Reed-Solomon (RS) codes or BCH codes could be used as the outer codes, which would help to overcome burst errors.

FIG. 1shows a block diagram of a conventional receiver for decoding concatenated codes. The receiver100shown inFIG. 1comprises a demodulator110, an inner decoder120, a deinterleaver130, and an outer decoder140. The demodulator110receives a radio frequency signal #RF to generate a data stream #S and may comprise components such as synthesizers for frequency down conversion, filters for anti-aliasing, synchronization means for timing or frequency recovery, and an equalizer for compensating for fading or impairment channel effects. After some or all of the above-mentioned operations are performed, the demodulator110then generates a data stream #S.

Depending on which kind of inner code is utilized, the inner decoder120may be implemented by a convolutional decoder or a TCM decoder, performing inner decoding processes on the data stream #S to generate inner decoded stream #I. Following the inner decoder120, a deinterleaver130deinterleaves the inner decoded stream #I to generate a deinterleaved stream #D. The deinterleaver130plays an important role in scattering some kinds of burst noise in order to share the error-correction burden.

The outer decoder140performs an outer-decoding process on the deinterleaved stream #D to output receiver output #OUT and could be dependently implemented by an RS decoder or a BCH decoder. For example, when RS codes are utilized as the outer codes, the outer decoder140implements an RS error decoder. The outer decoder140can correct a maximum of t errors for (n, k, 2t) RS codes. In other words, the outer decoder140has an error correction capability of t errors. However, in some communication systems, especially in terrestrial broadcasting systems, complex multi-path channels would induce severe fading or interference so that the equalizer of the demodulator110cannot entirely compensate for the fading or interference. In such circumstances, burst noise may cause errors on the inner decoder120to propagate to the outer decoder140, wherein even the deinterleaver130cannot scatter them efficiently. Therefore, an erasure marking mechanism is proposed to enhance the capability of error correction.

If the demodulator110is able to detect burst noise, and the inner decoder120has a mechanism to mark unreliable symbols as erasure indicators, the outer decoder140can be upgraded to an RS error-erasure decoder. An RS error-erasure decoder can correct x errors and y erasures for (n, k, 2t) RS codes, only if 2x+y≦2t. In other words, the outer decoder140has the opportunity to correct codewords with an actual error number that is larger than t if it is informed with some error locations marked as erasures.

An erasure marking procedure must be performed based on a reliable burst error detection, however, the burst error detection mechanism is currently a preliminary technique. It is therefore desirable to provide an enhanced burst error detector.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.

Another embodiment provides a method for decoding the data stream to generate the receiver output. Firstly, burst noise locations corresponding to the data stream are determined according to an error-check equation and accordingly generating a burst error indicator. The data stream is then decoded to generate an inner decoded stream. An erasure marking process is simultaneously performed on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. The inner decoded stream is then decoded with reference to the erasure indicator to generate the receiver output. A detailed description is given in the following embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2ashows an embodiment of a digital communication device200aaccording to the invention. In the embodiment, a burst error detector300is provided to detect burst error based on the data stream #S output from the demodulator110. The inner decoder220adapts an erasure marker225to output an erasure indicator #E based on burst error indicator #B output from the burst error detector300. More specifically, the erasure marker225maps burst error indicator #B in a symbol level to corresponding bits while the inner decoder decodes the data stream #S into recovered bits. The deinterleaver230deinterleaves the erasure indicator #E to output a deinterleaved erasure indicator #E′ to the outer decoder240awhile converting the inner decoded stream #I into a deinterleaved stream #D. The outer decoder240athen performs an adaptive error correction process based on the deinterleaved stream #D and deinterleaved erasure indicator #E′ to output the receiver output #OUT.

Depending on the structure of the transmitter generating the radio frequency signal #RF, it is noted that to the deinterleaver230is optional component.FIG. 2bshows another embodiment of a digital communication device200bwhere the deinterleaver230is not present in the digital communication device200b. As shown, the inner decoder220provides the inner decoded stream #I and the erasure indicator #E to the outer decoder240b. The outer decoder240bthen performs the adaptive error correction process based on the inner decoded stream #I and erasure indicator #E to output the receiver output #OUT. Detailed operations of each function block are further described below.

FIG. 3ashows an embodiment of the burst error detector300as shown inFIGS. 2aand2b. The data stream #S is a continuous bit stream sequentially input to the burst error detector300at a certain bit rate. The burst error detector300analyzes the data stream #S to generate a burst error indicator #B to indicate whether burst error has occurred on a corresponding timing period. In the burst error detector300, a decision unit310slices or quantizes the data stream #S, and extracts useful bits from the data stream #S to generate at least one coded stream #U. The useful bits are directed to parity bits or error check codes embedded with data bits in the data stream #S, and the formats are dependent on various coding schemes which will be described below. For example, the data stream #S may be a symbol stream, thus the decision unit310serves as a slicer or a quantizer, and the coded stream #U is output as a coded bit stream. Alternatively, if the data stream #S is provided as parallel coded bits, the coded stream #U can be a serial coded bit stream.

The combinational logic unit320couples to the output of the decision unit310, performing a combinational logic operation on the coded stream #U based on an error-check equation to generate a logic value #L for indicating correctness of a certain plurality of coded stream #U within a certain time period. In the embodiment, the error-check equation is developed by a particular algorithm associated with the coding scheme applied on the digital communication device200. The error-check equation varies with the applied coding scheme, and can be previously determined or approximated by the known structure of the corresponding transmitter. As the data stream #S are sequentially input, the logic value #L is consecutively output per time slot, each corresponding to a certain plural of coded stream #U.

Following the combinational logic unit320, a statistics unit330compiles a plurality of consecutive logic value #Ls within a time period to generate an accumulated value #A. A time period is directed to a group of consecutive time slots offsetting with time. The logic value #L is sequentially generated per time slot. Meanwhile, an accumulated value #A is preferably referred to as a summary of a plurality of logic value #Ls within consecutive time slots.

A comparator340is coupled to the statistics unit330, comparing the accumulated value #A with a threshold level #th to detect whether a burst error has occurred. If the accumulated value #A exceeds the threshold level #th, the comparator340asserts a burst error indicator #B to a particular value, such as logic “1” to indicate that a burst error has recently occurred. Conversely, if the accumulated value #A does not exceed the threshold level #th, the burst error indicator #B is set to a logic “0”. The threshold level may be a fixed value, a single-level value, or a multi-level value. Some other approach may be adapted to provide an adaptive threshold level.

FIG. 3bshows an embodiment of a statistics unit330baccording toFIG. 3a. According to the standard of convolutional codes, the coded stream #U in the data stream #S are segmented by a coding period (time period), and in the statistics unit330b, a delay line334is designated to present the coding period (time period), comprising a plurality of columns each corresponding to a slot in the time period wherein each column storing a logic value #L. The adder332sequentially receives the logic value #L from the combinational logic unit320to accumulate each column of the delay line334. Thereafter, a selector336detects the segmentation boundary (puncture boundary) of the coded stream #U and outputs one of the accumulated column values corresponding to the segmentation boundary (puncture boundary) as the accumulated value #A. The mechanism to detect the segmentation boundary can be obtained from various prior arts and therefore is not introduced herein.

In the statistics unit330, the accumulations for each column of the delay line334may be repeated for one or more time periods (coding periods of the coded stream #S), and the selector336may selects one of the columns of the delay line334having a minimal preliminary accumulation result as the boundary. The selector336then outputs the preliminary accumulation result as the accumulated value #A based on the boundary.

FIG. 3cshows another embodiment of a statistics unit330caccording toFIG. 3a. Similarly, the coded stream #U in the data stream #S are segmented by a coding period (time period), and in the statistics unit330c, a storage element344, such as a buffer, stores a preliminary accumulation result of the accumulated value #A. The adder332receives logic value #L from the combinational logic unit320and the preliminary accumulation result from the storage element344to sequentially sum each input logic value #L with the preliminary accumulation result and accordingly store the result of summation in storage element344as the preliminary accumulation result. A counter346counts a time period (coding periods of the coded stream #S), thereby enabling output of the preliminary accumulation result in the storage element344as the accumulated value #A. The counter346then reset the preliminary accumulation result storing in the storage element344.

FIG. 4ashows a conventional inner encoder400. The inner encoder400is a TCM block of the transmitter complying with the 8-VSB standard, which includes a pre-coder410, a trellis encoder420and a symbol mapper436. The pre-coder410receives two information bit streams X1and X2and generates two bit streams Y1and Y2, respectively. The pre-coder410has an XOR gate402and a delay element404with a 12-symbol delay period, and receives the bit stream X2to generate the bit stream Y2. The trellis encoder420receives two bit streams Y1and Y2and generates three output bit streams U0, U1and U2. The trellis encoder420has an XOR gate424and two delay elements422and426each having a 12-symbol delay period, which receive the bit stream Y1and generate the output bit stream U0and U1. The symbol mapper436receives three output bit streams U0, U1and U2, and generates a data stream #S using a predetermined symbol mapping rule defined by the 8-VSB standard.

In the trellis encoder420, the output bit streams U0and U1are determined by the bit stream Y1using the XOR gate424and the two delay elements422and426. According to the structure of the trellis encoder420, three equations, which involve the output bit streams U0and U1but are irrelevant to the bit stream Y0, can be determined; they are as follows:
U0[n]=Q0[n−1];  (1);
Q0[n]=U1[n]⊕Q1[n−1];  (2); and
Q1[n−1]=U0[n−1],  (3),

where n represents an index and each increment corresponds to a 12-symbol delay period, and Q0and Q1represent the outputs of the delay elements422and426, respectively.

Thus, an identity, U0[n+1]=U1[n]⊕U0[n−1], can be deduced based on equations (1), (2) and (3). Accordingly, the error-check equation is determined as follows:
P[n]=U0[n+1]⊕U1[n]⊕U0[n−1]  (4).

Using the error-check equation (4) inherent in the transmitter complying with the 8-VSB standard, an apparatus for calculating an error metric can be designed. A P[n] of a logic value “0” indicates correctness of corresponding coded stream #U. Conversely, a P[n] of logic “1” indicating incorrectness of the corresponding coded stream #U.

FIG. 4bshows embodiments of a decision unit310aand a combinational logic unit320aresponsive to the inner encoder400inFIG. 4a. In the combinational logic unit320a, the delay elements405and the XOR gate407constitute the combinational logic unit320shown inFIG. 3a. The decision unit310aand combinational logic unit320aare adapted in the embodiment ofFIG. 3ato form a burst error detector300.

As an example, the data stream #S, which generally comes from an equalizer in the demodulator110, is inputted to the decision unit310a. The decision unit310agenerates three coded streams U0, U1and U2using the symbol mapping rule symmetric to the symbol mapper436of the inner encoder400inFIG. 4a. If the coded streams U0, U1and U2are correct, it is assumed that the corresponding symbol in the data stream #S is also correct. Thus, the delay elements405in the combinational logic unit320acan be used to simplify the equation (4), whereby the coded stream U1is delayed with a 12-symbol period, and the coded stream U0is delayed with a 24-symbol period. An XOR gate407then receives the delayed coded streams U0and U1to implement the error checking operations, and the logic value #L output from the XOR gate407represents an error checking result. Apparently, in this embodiment, a logic value “0” represents a correct trial, and a logic value “1” represents an incorrect trial.

FIG. 5ashows a conventional inner encoder500. The inner encoder500is a TCM block in a transmitter complying with the standard of the ITU-T Recommendation J.83 Annex B. (hereinafter called J83B) which utilizes the 64-QAM modulation scheme. InFIG. 5a, the inner encoder500serially receives a 7-bit data stream #Din. The parser540identifies a group of four 7-bit symbols (i.e. 28 bits) and assigns as an in-phase “I” component and a quadrature “Q” component. As indicated inFIG. 5a, for the I component, the parser540outputs two upper uncoded bit streams502(I2, I5, I8, I11, I13) and (I1, I4, I7, I10, I12)504and one lower coded bit stream512a(I0, I3, I6, I9). For the Q component, the parser540outputs two upper uncoded bit streams506(Q2, Q5, Q8, Q11, Q13) and508(Q1, Q4, I7, Q10, Q12) and one lower coded bit stream512b(Q0, Q3, Q6, Q9). The uncoded bit streams502,504,506and508are sent to a QAM mapper530, and the coded bit streams512aand512bare sent to a differential pre-coder510. The differential pre-coder510performs rotationally invariant trellis coding on I and Q bit pairs, that is, Q0and I0, Q3and I3, Q6and I6, and Q9and I9. The differential pre-coder510then transmits the differentially encoded lower streams #X and #Y (4 bits) to punctured binary convolutional encoders520aand520b, respectively.

In the embodiment, the ⅘-rate punctured binary convolutional encoders520aand520bare based on ½-rate binary convolutional encoders with punctured codes. Usually, in the digital communication system, error correction codes are applied add redundancy to upgrade anti-noise capability. With the ½ code rate, the punctured binary convolutional encoders520aand520breceive four bits (#X and #Y) and generate 8 encoded bits. In addition, the puncture function applied in the punctured binary convolutional encoder520aand520bis used to compensate for the decrease in payload if all encoded bits are transmitted as the payload will be much reduced due to excessive redundancy. In other words, the transmission of some of the encoded bits previously agreed on by the transmitter and the receiver is bypassed. The punctured binary convolutional encoders520aand520b, complying with the J83B standard, transmit 5 bits for every encoded 8 bits, resulting in an overall punctured code rate ⅘. That is, 5 bits are generated according to 4 input bits.

FIG. 5bshows a punctured binary convolutional encoder520aaccording to the inner encoder500inFIG. 5a. The punctured binary convolutional encoder520bhas a structure similar to that of the punctured binary convolutional encoder520aand will not be described again. It is noted that the error-check equation deduced in the following discussion can also be applied to the punctured binary convolutional encoder520b. The punctured binary convolutional encoder520aincludes four delay elements555, two exclusive-OR logic gates524and526, and a commutator528. The four delay elements555store four previous input bits X[0], X[−1], X[−2] and X[−3], and there are 16 states in the punctured binary convolutional encoder520a. As shown inFIG. 5b, codes OUTUand OUTLcan be expressed by:
OUTU=X[1]⊕X[−1]⊕X[−3];  (5); and
OUTL=X[1]⊕X[0]⊕X[−1]⊕X[−2]⊕X[−3]  (6).

Equations (5) and (6) are determined by generating codes G1and G2, where G1=[010101] and G2=[011111]. It is noted that different convolutional coders have different generating codes. The Commutator528implements the puncture function using puncture matrix [P1;P2]=[0001;1111], where “0” indicates no transmission and “1” indicate transmission in order.

For each trellis group, the punctured binary convolutional encoder520acan generate 8 encoded bits from 4 input bits represented by X[1], X[2], X[3] and X[4]. The commutator528selects 5 bits from the 8 encoded bits to be the coded stream #U according to the puncture matrix. Here a group of the coded stream (for example, [5],U[4],U[3],U[2],U[1]) can be expressed as functions of a corresponding group of the input bits (for example, X[4],X[3],X[2],X[1]) and previous input bits (or internal states of the encoder, X[0],X[−1],X[−2],X[−3]). Generally, in an n-th group, the five output bits can be expressed by:
U[n+1]=X[n+1]⊕X[n]⊕X[n−1]⊕X[n−2]⊕X[n−3];
U[n+2]=X[n+2]⊕X[n+1]⊕X[n]⊕X[n−1]⊕X[n−2];
U[n+3]=X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]⊕X[n−1];
U[n+4]=X[n+4]⊕X[n+2]⊕X[n]; and
U[n+5]=X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n],

wherein n represents an index. In addition to the n-th group, two previous groups (the (n−2)-th and (n−1)-th groups) and two following groups (the (n+1)-th and (n+2)-th groups) are also listed for reference:

According to the five consecutive groups of the output bits, an identity, irrelevant to the input bits X, can be deduced as follows:
U[n−6]⊕U[n−5]⊕U[n−4]⊕U[n−3]⊕U[n−2]⊕U[n−1]⊕U[n+1]⊕U[n+4]⊕U[n+5]⊕U[n+8]⊕U[n+9]⊕U[n+11]⊕U[n+12]⊕U[n+13]⊕U[n+14]⊕U[n+15]≡0;

which can be further be deduced in a polynomial form, expressed as:
P(x)=x*(1+x+x2+x3+x4+x6+x7+x10+x11+x14+x16+x17+x18+x19+x20+x21)  (7).

Using the error-check equation (7) inherent in the transmitter complying with the J83B standard, a combinational logic unit320ofFIG. 3acan be designed.

On the other hand, in the receiver of the J83B cable system, it is necessary to ascertain the puncture boundary or punctured position from an incoming bit stream since there is no training sequence therein. As illustrated, a group of five output coded bits is generated by four input bits, indicating five possible punctured positions for the incoming bit stream of the TCM decoder in the receiver. Thus, the error-check equation (7) can only be applied at a correct punctured position (puncture boundary) among the five possible punctured positions.

FIG. 5cshows an embodiment of a combinational logic unit320bresponsive to the punctured binary convolutional encoder520ainFIG. 5b, which complies with the J83B standard and utilizes the error-check equation (7) to examine correctness of the data stream #S. In the digital communication device200, a radio frequency signal #RF is received and consecutively demodulated by a demodulator110into a data stream #S, using a 64-QAM demodulation scheme in this embodiment. The combinational logic unit320bincludes a delay line560having a plurality of delay elements D connected in series, and an XOR gate562having a plurality of inputs respectively coupled to the outputs of a part of the delay elements D of the delay line circuit delay line560. The decision unit310ofFIG. 3areceives the in-phase and quadrature parts of the data stream #S to reacquire coded streams #U and #V as discussed inFIG. 5a. In the embodiment, only the coded stream #U is illustrated.

The coded stream #U is sent to the combinational logic unit320b. In the combinational logic unit320b, the delay line560stores a finite sequence of the coded stream using a plurality of unit delay elements D connected in series. In the embodiment, the delay line560has 21 unit delay elements to store the sequence from U[n−6] to U[n+14] of the coded stream #U. According to the error-check equation (7), the outputs of the first (Right), second, third, fourth, fifth, sixth, eighth, eleventh, twelfth, fifteenth, sixteenth, eighteenth, nineteenth, twentieth, and twenty-first (Left) unit delay elements and the current bit are connected to the inputs of the XOR gate562. The XOR gate562consecutively performs XOR operation on these inputs to output a plurality of consecutive logic value #Ls. Each logic value #L represents a result of the error-check equation (7).

Alternatively, the burst error detector300can be widely used in all applications for burst error detection. For example,FIG. 5dshows a convolutional encoder520ddefined by Digital Video Broadcasting (DVB) standard ETSI EN 300 744 V1.4.1 (2001-01) with variable puncture rates including ½, ⅔ and ¾. The punctured convolutional encoder520dincludes six delay elements555, two exclusive-OR gates524and526, and a commutator528. The six delay elements555store six previous input bits X[0], X[−1], X[−2], X[−3], X[−4] and X[−5]. As shown, codes OUTUand OUTLinput to the commutator528can be expressed by:
OUTU=X[1]⊕X[0]⊕X[−1]⊕X[−2]⊕X[−5];  (8)
OUTL=X[1]⊕X[−1]⊕X[−2]⊕X[−4]⊕X[−5](9)

The European DVB standard suggests three options for punctured code rates, including ½, ⅔ and ¾. According to equations (8) and (9) and a specific punctured code rate, at least one identity equation merely involving the output bits and its parity check polynomial can be found. The deduction is omitted here for clarity.

When the puncture rate is set to ½, the puncture sequences [1-up 1-down] can be expressed as:
U[1]=X[1]+X[0]+X[−1]+X[−2]+X[−5];
U[2]=X[1]+X[−1]+X[−2]+X[−4]+X[−5]; and
U[3]=X[2]+X[1]+X[0]+X[−1]+X[−4].

Similarly, U[4]˜U[16] can also be obtained from the puncture sequences. Therefore, based on U[1]˜U[16], an identity can be derived, expressed as:
U[1]⊕U[2]⊕U[4]⊕U[5]⊕U[7]⊕U[8]⊕U[11]⊕U[13]⊕U[15]⊕U[16]=0;

where an error-check equation can be induced therefrom, expressed in polynomial form:
P(x)=1+x+x3+x5+x8+x9+x11+x12+x14+x15(10).

When the puncture rate is set to ⅔, the puncture sequence [1-up 1-down 2-down] can be expressed as:
U[1]=X[1]+X[0]+X[−1]+X[−2]+X[−5];
U[2]=X[1]+X[−1]+X[−2]+X[−4]+X[−5];
U[3]=X[2]+X[0]+X[−1]+X[−3]+X[−4]; and
U[4]=X[3]+X[2]+X[1]+X[0]+X[−3].

Similarly, U[5]˜U[20] can also be obtained from the puncture sequences. Therefore, according to U[1] to U[20] of rate ⅔, a corresponding error-check equation can be derived:
U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[8]⊕U[10]⊕U[12]⊕U[13]⊕U[15]⊕U[18]⊕U[19]⊕U[20]=0;

where the polynomial form is expressed as:
P(x)=1+X+x2+x5+x7+x8+x10+x12+x16+x17+x18+x19(11).

Furthermore, when the puncture rate is set to ¾, the puncture sequence [1-up 1-down 2-down 3-up] can be expressed as:
U[1]=X[1]+X[0]+X[−1]+X[−2]+X[−5];
U[2]=X[1]+X[−1]+X[−2]+X[−4]+X[−5];
U[3]=X[2]+X[0]+X[−1]+X[−3]+X[−4];
U[4]=X[3]+X[2]+X[1]+X[0]+X[−3]; and
U[5]=X[4]+X[3]+X[2]+X[1]+X[−2].

Similarly, U[6]˜U[34] can also be obtained from the puncture sequences. Therefore, according to the U[1] to U[34] of rate ¾, the identity can be:
U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[7]⊕U[10]⊕U[14]⊕U[15]⊕U[16]⊕U[24]⊕U[28]⊕U[29]⊕U[31]⊕U[32]⊕U[33]⊕U[34]=0;

where the polynomial form is expressed as:
P(x)=1+x+x2+x3+x5+x6+x10+x18+x19+x20+x24+x27+x30+x31+x32+x33(12).

Inherently, the structure proposed inFIG. 5ccan be alternated to implement various error-check equations such as (10), (11) and (12).

FIG. 6shows an embodiment of an erasure marking process implemented by the erasure marker225ofFIGS. 2aand2b. The upper part ofFIG. 6illustrates the status of the burst error indicator #B. During period C1, the burst error indicator #B is high, indicating that burst error has occurred. During periods C2, the burst error indicator #B is low, indicating that no burst error has occurred.

As an example, the inner decoder220ofFIGS. 2aand2bmay adopt the Viterbi algorithm to decode the data stream #S, and the middle part ofFIG. 6shows a survivor path found in a trace back procedure performed by the inner decoder220to thereby decode the inner decoded stream #I therefrom. The erasure marking process is performed during the Viterbi decoding process. Since burst error occurs during period C1, a higher criterion is used for determining an erasure. The marked states are represented in shadowed nodes. Conversely, the survivor paths are more reliable during period C2, so a lower criterion is used to determine an erasure. The lower part ofFIG. 6illustrates how the signal states of the erasure indicator #E are determined according to marks on the survivor path on the Trellis diagram. If a state is marked on the survivor path, the erasure marker225correspondingly asserts an erasure indicator #E of logic “1”. Conversely, for a state on the survivor path without a mark, the erasure marker225correspondingly asserts a logic “0”.

The embodiment ofFIG. 6enables the outer decoder240aofFIG. 2ato decode the deinterleaved stream #D in accordance with unreliable locations specified by the deinterleaved erasure indicator #E′ as erasure locations corresponding to the deinterleaved stream #D, wherein the deinterleaved erasure indicator #E′ is generated from the deinterleaver230ofFIG. 2aby deinterleaving the erasure indicator #E. Similarly, the embodiment ofFIG. 6is applicable to the outer decoder240bofFIG. 2bto decode inner decoded stream #I in accordance with unreliable locations specified by the erasure indicator #E as erasure locations corresponding to the inner decoded stream #I.

FIG. 7ashows an outer decoder240afor error-correcting a deinterleaved stream #D to generate a receiver output #OUT according to an embodiment of the invention. The deinterleaved stream #D is an (n, k, 2t) RS encoded signal. The outer decoder240aincludes a first error correction unit710, a second error correction unit720and a multiplexer730. As discussed, the digital communication device200aofFIG. 2ais a concatenated code receiver, and the erasure marker225functions with reference to burst noise locations determined by a burst error detector300coupled to the demodulator110, and the deinterleaved erasure indicator #E′ generated by the deinterleaver130indicates unreliable-locations of the deinterleaved stream #D while performing the decoding.

In the outer decoder240a, a first error correction unit710decodes the deinterleaved stream #D to generate a first preliminary output #O1. Since the first error correction unit710functions without reference to the deinterleaved erasure indicator #E′, the performance of the first error correction unit710will not be influenced by an erroneous erasure marking procedure possibly performed by the erasure marker225. The first error correction unit710can correct a maximum of t errors per codeword. On the other hand, the second error correction unit720decodes the deinterleaved stream #D with reference to the deinterleaved erasure indicator #E′ to generate a second preliminary output #O2. More specifically, the second error correction unit720decodes the deinterleaved stream #D by regarding the unreliable-locations indicated by the deinterleaved erasure indicator #E′ as erasure locations. A total of x errors and y erasures of a codeword can be corrected successively only if 2x+y≦2t. That is, with the additional information provided by the deinterleaved erasure indicator #E′, it is possible that the second error correction unit720can correct a maximum of 2t erasures. In other words, if all error locations of a codeword can be precisely determined by the erasure marker225as erasure locations and no erroneous erasure locations are marked, the second error correction unit720will be able to correct a maximum of 2t errors, which means twice the error correcting capability of the first error correction unit710.

In this embodiment, the first error correction unit710and the second error correction unit720function in parallel. For each codeword of the deinterleaved stream #D, both the first error correction unit710and the second error correction unit720attempt to decode the codeword to respectively generate the first preliminary output #O1and second preliminary output #O2. This strategy ensures the error-correcting capability of the outer decoder240awhen the number of errors in a codeword of the deinterleaved stream #D is not larger than t, and enhances the error-correcting capability of the outer decoder240awhen the number of errors in a codeword of the deinterleaved stream #D is larger than t.

In addition, when decoding codewords of the deinterleaved stream #D, the first error correction unit710further generates a first flag #f1to indicate whether each codeword of the deinterleaved stream #D is successively error-corrected by the first error correction unit710. Similarly, when decoding codewords of the deinterleaved stream #D with reference to the deinterleaved erasure indicator #E′, the second error correction unit720also generates a second flag #f2to indicate whether each codeword of the deinterleaved stream #D is successively error-corrected by the second error correction unit720. According to the first flag #f1and second flag #f2, the multiplexer730selects one of the first preliminary output #O1and second preliminary output #O2to be the receiver output #OUT.

Since the first error correction unit710is a relatively reliable decoder and will not be influenced by an erroneous erasure marking procedure possibly performed by the erasure marker225, as long as the first flag #f1indicates that the deinterleaved stream #D is successively error-corrected by the first error correction unit710to generate the first preliminary output #O1, the multiplexer730may selects the first preliminary output #O1to be the receiver output #OUT.

In the embodiment, the deinterleaver230is not limited to be an essential component. Generally, the deinterleaver230is set in front of the input ends of the first error correction unit710and the second error correction unit720, to deinterleave the inner decoded stream #I output from the inner decoder220before the deinterleaved stream #D is inputted into the first error correction unit710and the second error correction unit720, and to deinterleave the erasure indicator #E, thereby generating the deinterleaved erasure indicator #E′ and providing it to the second error correction unit720. Alternatively, as shown inFIG. 2b, the outer decoder240bmay directly connect to the inner decoder220, processing the inner decoded stream #I instead of the deinterlaved stream #D.

FIG. 7bshows an outer decoder240bsimilar to the embodiment ofFIG. 7a. The outer decoder240bis adaptable in the embodiment ofFIG. 2bwhere the deinterleaver230is skipped, operating based on the erasure indicator #E and the inner decoded stream #I. The first error correction unit710decodes the inner decoded stream #I to generate a first preliminary output #O1, and the second error correction unit720decodes the inner decoded stream #I with reference to the erasure indicator #E to generate a second preliminary output #O2. More specifically, the second error correction unit720decodes the inner decoded stream #I by regarding the unreliable-locations indicated by the erasure indicator #E as erasure locations. When decoding codewords of the inner decoded stream #I, the first error correction unit710further generates a first flag #f1to indicate whether each codeword of the inner decoded stream #I is successively error-corrected by the first error correction unit710. Similarly, when decoding codewords of the inner decoded stream #I with reference to the erasure indicator #E, the second error correction unit720also generates a second flag #f2to indicate whether each codeword of the inner decoded stream #I is successively error-corrected by the second error correction unit720. According to the first flag #f1and second flag #f2, the multiplexer730selects one of the first preliminary output #O1and second preliminary output #O2to be the receiver output #OUT. Those skilled in the art are able to realize how the outer decoder240bperforms these operations and functions based on the above descriptions directed to the outer decoder240a. Therefore, the detailed descriptions for these operations and functions are not repeated herein.