Method of manufacturing semiconductor elements

A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

The present application claims priority under 35 U. S. C. § 119 to Japanese Patent Application No. 2019-036768, filed Feb. 28, 2019, and Japanese Patent Application No. 2020-016939 filed on Feb. 4, 2020, the contents of which are incorporated herein by reference in their entirety.

BACKGROUND

The present disclosure relates to a method of manufacturing semiconductor elements.

Semiconductor elements such as light-emitting diodes (LEDs) can be manufactured using a method, for example, described in WO2011-161975A, in which a semiconductor layer is grown on a wafer such as a sapphire substrate serving as a growth substrate, and subsequently bonded with a support substrate. In such a method, cracks may occur in the semiconductor layer, resulting in a reduction in the productivity.

SUMMARY

The present disclosure is devised in the light of such circumstances, and it is thus an object thereof to provide a method of manufacturing semiconductor elements with good productivity.

A method of manufacturing semiconductor elements according to one embodiment of the present invention includes disposing a semiconductor layer made of a nitride semiconductor on a first wafer, and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge and the first region of the first wafer in each of first directions respectively passing through a center of the first wafer and also in parallel to a corresponding one of m-axes of the semiconductor layer is smaller than a second distance between an edge and the first region of the first wafer in each of second directions respectively passing through the center of the first wafer and also in parallel to a corresponding one of a-axes of the semiconductor layer. The second wafer has a lower surface and an upper surface, the lower surface including a flat portion and an inclined portion surrounding the flat portion, the inclined portion inclining upward toward the upper surface. In the bonding the second wafer, the second wafer is bonded to the first wafer such that outer end portions of the first wafer located in the first directions are opposite to the inclined portion of the second wafer.

Using the method of manufacturing according to certain embodiments of the disclosure, semiconductor elements can be manufactured with improved productivity.

DETAILED DESCRIPTION

Certain embodiments of the present invention will be described below with reference to the drawings. The drawings referred to in the description below are intended to schematically illustrate the embodiments. The size, space, interval, and locational relationship of the components may be exaggerated, a portion of a component may not be shown, and the dimensional ratios and the like of the components may differ from the actual ratios. The drawings may also include the components that have different dimensional relations and ratios among one another. In the description below, the same designations or the same reference numerals denote the same or like members, and repeated detailed descriptions will be omitted.

A method of manufacturing semiconductor elements according to certain embodiments of the present invention will be schematically illustrated below. The method of manufacturing semiconductor elements according to certain embodiments includes providing a first wafer10(Step S1), disposing a semiconductor layer20made of a nitride semiconductor on the first wafer10(Step S2), and bonding a second wafer30to the first wafer10via the semiconductor layer20(Step S3).

The first wafer10has an upper surface15including a first region11and a second region12surrounding a periphery of the first region11and located lower than the first region11. In a top view of the first wafer10, a first distance D1between an edge17and the first region11of the first wafer10in each of first directions V1passing through a center of the first wafer10and parallel respective m-axes of the semiconductor layer20is smaller than a second distance D2between the edge17and the first region11of the first wafer10in each of second directions V2passing through the center of the first wafer10and parallel to respective a-axes of the semiconductor layer20. The second wafer30has a lower surface31and an upper surface35, the lower surface31including a flat portion32and an inclined portion33surrounding the flat portion32, the inclined portion33inclining upward toward the upper surface35. In the step of bonding the second wafer30(Step S3), the second wafer30is bonded to the first wafer10such that outer end portions of the first wafer10located in the first directions V1are opposite to the inclined portion33of the second wafer30.

The method of manufacturing semiconductor elements according to one embodiment will be described in detail below.FIG. 1is a flow chart showing a procedure of a method of manufacturing semiconductor elements according to one embodiment of the present invention.

Providing First Wafer10

A first wafer10is provided (Step S1in the flowchart inFIG. 1).FIG. 2Ais a schematic plan view illustrating a first wafer10according to the present embodiment.FIG. 2Bis a schematic partial cross-sectional end view taken along one of the first directions V1inFIG. 2A.FIG. 2Cis a schematic partial cross-sectional end view taken along one of the second directions V2shown inFIG. 2A.

The first wafer10is, for example, a sapphire substrate, and for example, made of a single crystal sapphire. As shown inFIG. 2A, the first wafer10has a shape of substantially circular plate with a diameter of, for example, about 100 mm. The first wafer10may be provided with an orientation flat19that has a linear profile obtained by removing a chord-shape portion from the circular plate shape of the wafer. The outer periphery of the first wafer10is provided with a bevel portion18. As shown inFIG. 2BandFIG. 2C, the thickness of the first wafer10decreases toward the edge17in the bevel portion18.

In the present specification, the term “upper surface15” of the first wafer10refers to the upper surface except for the bevel portion18. The upper surface15is, for example, oriented along c-plane of the sapphire of the first wafer10. For example, the upper surface15and a sapphire c-plane are at an angle of 5° or less with each other. The upper surface15may be inclined relative to the sapphire c-plane.

First directions V1and second directions V2are determined on the upper surface15of the first wafer10. The first directions V1and the second directions V2are parallel to the upper surface15, and in the present embodiment, there are six first directions V1and six second directions V2. As described below, when the semiconductor layer20is disposed on the upper surface15of the first wafer10, each of the first directions V1passes through the center C of the first wafer10and is a positive direction along one of the m-axes of the semiconductor layer20. Meanwhile, when the semiconductor layer20is disposed on the upper surface15of the first wafer10, each of the second directions V2passes through the center C of the first wafer10and is a positive direction along one of the a-axes of the semiconductor layer20. The center C of the first wafer10corresponds to a center of a circumscribed circle of the first wafer10in a top view.

For example, an angle between two adjacent ones of the first directions V1is 60°. For example, an angle between two adjacent one of the second directions V2is 60°. For example, an angle between one of the first directions V1and its adjacent one of the second directions V2is 30°.

The first wafer10has an upper surface15including a first region11and a second region12. The second region12surrounds a periphery of the first region11and is located lower than the first region11. A step16is formed between the first region11and the second region12. For example, the second region12is located 2 μm or more lower than the first region11. In other words, the height G of the step16is, for example, 2 μm or greater, for example, 6 μm. The maximum height G of the step16can be appropriately determined. For example, the maximum height G of the step16can be, for example, 30 μm or less.

In a top view, the first region11has a shape that includes a circular part13with six protrusions14at its outer periphery, the protrusions14extending toward the edge17of the first wafer10along respective first directions V1. For example, the center of the circular part13and the center C of the first wafer10coincide. The extending length of each of the protrusions14can be, for example, in a range of 0.1 mm to 10 mm, preferably in a range of 0.5 mm to 5 mm.

Accordingly, the first distance D1between the edge17and the first region11of the first wafer10in each of the first directions V1is smaller than the second distance D2between the edge17and the first region11of the first wafer10in each of the second directions V2, by the extending length of the protrusions14. That is, the first distance D1is smaller than the second distance D2(D1<D2). The first distance D1can be, for example, in a range of 0.1 mm to 5 mm, preferably in a range of 0.2 mm to 3 mm. The second distance D2can be, for example, in a range of 1 mm to 10 mm.

The second region12is interposed between the circular part13and a bevel portion18. Meanwhile, the second region12may be or may not be interposed between the protrusions14and the bevel portion18. In the example shown inFIG. 2AandFIG. 2B, the protrusions14do not reach the bevel portion18and the second region12is interposed between the protrusions14and the bevel portion18.

Next, a semiconductor layer20made of a nitride semiconductor is disposed on the first wafer10(Step S2in the flowchart inFIG. 1).

FIG. 3Ais a schematic plan view illustrating the first wafer10and a semiconductor layer20according to the present embodiment.FIG. 3Bis a schematic partial cross-sectional end view taken along a first direction V1inFIG. 3A.FIG. 3Cis a schematic partial cross-sectional end view taken along a second direction V2shown inFIG. 3A.FIG. 4Ais a schematic plan view illustrating the crystal orientation of the semiconductor layer20.FIG. 4Bis a schematic perspective view illustrating the crystal orientation of the semiconductor layer20that has a hexagonal crystal structure.

As shown inFIG. 3AtoFIG. 3C, the semiconductor layer20can be grown, for example, by using the first wafer10as a growth substrate and using a physical vapor-phase growth method such as a metal organic chemical vapor deposition (MOCVD) method, epitaxially grown on the upper surface15of the first wafer10. The semiconductor layer20includes, for example, a III-V nitride semiconductor (InXAlYGa1-X-YN, where 0≤X, 0≤Y, and X+Y≤1). The semiconductor layer20includes, for example, an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer located between the n-type semiconductor layer and the p-type semiconductor layer. The light from the light-emitting layer may have a peak emission wavelength in a range of 330 nm to 400 nm. In such a case, when the semiconductor layer20contains a semiconductor layer that does not contain aluminum (Al) such as a semiconductor layer made of gallium nitride (GaN), light from the light-emitting layer can be easily absorbed by the semiconductor layer. With the semiconductor layer20containing, for example, an AlGaN layer that contains Al, a high transmittance to light emitted from the light emitting layer can be obtained. The semiconductor layer20includes, for example, AlxlGa1-x1N (0.03≤x1≤0.08).

In the structure described above, the outer peripheral portion of the semiconductor layer20has a thickness greater than other portions of the semiconductor layer20. The term “outer peripheral portion of the semiconductor layer20” refers to a portion located at an outer end portion of the first region11of the semiconductor layer20. When the semiconductor layer20includes a layer that contains Al, the tendency of the outer peripheral portion of the semiconductor layer20becoming greater than other regions of the semiconductor layer20becomes more apparent compared to that the semiconductor layer does not contain Al. The cause of such a tendency is thought that when the semiconductor layer20includes a semiconductor layer that contains Al, unintended growth may easily occur in the outer peripheral portion of the semiconductor layer20. The thickness of the outer peripheral portion of the semiconductor layer20depends on the directions as seen from the center C. The thickness t1of the end portions located in the first directions V1from the center C is greater than the thickness t2of the outer end portions located in the second directions V2from the center C. That is, the film thickness t1is greater than the film thickness t2(t1>t2). In the present specification, the term “thick film portion20a” refers to each portion of the semiconductor layer20disposed on the first region11, located at the outer end portions along each of the first directions V1as seen from the center C, that is, portions having a thickness of t1or close to t1. The thick film portions20aof the semiconductor layer20are present at outer end portions at six locations along the first directions V1from the center C.

The reason for the occurrence of such uneven thickness has not been clearly determined, but it is assumed as below. As described above, the first directions V1are positive directions started from the center C respectively along the m-axes of the semiconductor layer20, and the second directions V2are positive directions started from the center C respectively along the a-axes of the semiconductor layer20. Also, as shown inFIG. 4AandFIG. 4B, the (0001)c-plane of the semiconductor layer20is in parallel to the upper surface15of the first wafer10. In this case, the growth rate of the crystal on the (0001)c-plane of the semiconductor layer20along the m-axes (first directions V1) is lower than the growth rate along the a-axes (second directions V2). Accordingly, it is assumed that the crystal growth of the semiconductor layer20on the (0001)c-plane in the second directions V2with higher crystal growth rate affects the crystal growth in the first directions V1with lower crystal growth rate, which facilitates the crystal growth at the outer end portions in the first directions V2, resulting in a greater thickness at the end portions in the first directions V1than respective adjacent portions.

In the first region11of the first wafer10, protrusions14are formed in the first directions V1as seen from the center C, and the first distance D1is smaller than the second distance D2. Accordingly, the thick film portions20aof the semiconductor layer20are located at outer periphery side of the first wafer10relative to the outer end portions in the second directions V2of the semiconductor layer20. The thick film portions20aof the semiconductor layer20are formed in the portions of the first region11where the protrusions14are provided.

Bonding Second Wafer30

Next, a second wafer30is bonded to the first wafer10via the semiconductor layer20(Step S3in the flowchart inFIG. 1). The second wafer30is, for example, a silicon wafer.

FIG. 5is a schematic bottom plan view illustrating a second wafer30according to the present embodiment.FIG. 6Ais a schematic plan view illustrating the first wafer10, the semiconductor layer20, and the second wafer30according to the present embodiment.FIG. 6Bis a schematic partial cross-sectional end view taken along one of the first directions V1inFIG. 6A.FIG. 6Cis a schematic partial cross-sectional end view taken along one of the second directions V2shown inFIG. 6A.

As shown inFIG. 5andFIG. 6AtoFIG. 6C, a lower surface31of the second wafer30includes a flat portion32and an inclined portion33. The flat portion32has a substantially circular shape and for example, the center C of the flat portion32coincides with the center C of the first wafer10, in a top view. The inclined portion33is formed surrounding the flat portion32. The inclined portion33inclines from the flat portion32toward the upper surface35of the second wafer30.

In a similar manner, the second wafer30has an upper surface35including a flat portion36and an inclined portion37. For example, the flat portion36of the second wafer30is substantially entirely overlapped with the flat portion32of the first wafer10, and the inclined portion37of the second wafer30is substantially entirely overlapped with the inclined portion33of the first wafer10in a top view. The inclined portion37inclines from the flat portion36toward the lower surface31of the second wafer30. Accordingly, the outer peripheral portion of the second wafer30has a thickness decreasing toward the edge of the second wafer30. The inclined portions33and37respectively have a width of, for example, about 700 μm. The inclined portions33and37are, for example, a bevel portion of the second wafer30.

In the bonding the second wafer30to the first wafer10(Step S3), the second wafer30is bonded to the first wafer10such that the outer end portions of the first wafer located in the first directions V1as seen from the center C are opposite to the inclined portion33of the second wafer30. Accordingly, the thick film portions20aof the semiconductor layer20face the inclined portion33of the second wafer30. The inclined portion33is located above the flat portion32such that at the time of bonding the semiconductor layer20of the first wafer10and the second wafer30, the flat portion32of the second wafer30can be in contact with a flat portion other than the thick layer portions20aof the semiconductor layer20, while preventing the thick film portions20afrom coming in contact with the second wafer30. Thus, the second wafer30can be reliably bonded to the first wafer10via the semiconductor layer20.

In successive operations, using the second wafer30as a support substrate, a structure including the first wafer10, the semiconductor layer20, and the second wafer30is processed. For example, in the processing, the first wafer10serving as the growth substrate may be removed from the semiconductor layer20. After the first wafer10is removed, the structure including the semiconductor layer20and the second wafer30is singulated. Accordingly, a plurality of semiconductor elements can be manufactured from the structure including the second wafer30and the semiconductor layer20. The semiconductor elements are, for example, light-emitting elements such as light-emitting diodes (LEDs).

Next, effects of the embodiments will be described.

In the method of manufacturing semiconductor elements according to the present embodiment, the first region11and the second region12are provided on the upper surface15of the first wafer10. Accordingly, when the semiconductor layer20is disposed on the upper surface15, the outer end portion of the semiconductor layer20is located in the second region12. The step16is formed between the first region11and the second region12such that propagation of the cracks occurring in the outer end portion of the semiconductor layer20are interrupted by the step16, and are unlikely to propagate in the first region11of the semiconductor layer20. Accordingly, a crack density in the semiconductor layer20can be reduced and thus the semiconductor elements can be manufactured with a good yield.

Further, in the present embodiment, the protrusions14are provided in portions in the first region11along the first directions V1as seen from the center C. Accordingly, the first distance D1between the edge17and the first region11in the first direction V1as seen from the center C is set smaller than the second distance D2between the edge17and the first region11in the second direction V2as seen from the center C. Due to this arrangement, the thick film portions20aof the semiconductor layer20are located outer side than the outer periphery of the circular part13by the protrusions14, such that the thick film portions20aface the inclined portion33of the second wafer30at the time of bonding the first wafer10and the second wafer30. Accordingly, the thick film portions20acan be prevented from being in contact with the second wafer30. As a result, the second wafer30is allowed to adhere to the semiconductor layer20and is thus reliably secured. This allows for reliable operations performed after employing the second wafer30as the support substrate.

Thus, using the present embodiment, an improvement in yield of the semiconductor elements can be obtained while reliably performing the operations, and an improvement in productivity of the semiconductor elements can be achieved.

Comparative Example

Next, Comparative Example will be described.

FIG. 7Ais a schematic plan view illustrating a method of manufacturing semiconductor elements according to Comparative Example.FIG. 7Bis a schematic partial cross-sectional end view illustrating a method of manufacturing semiconductor elements according to Comparative Example.

As shown inFIG. 7AandFIG. 7B, a second region is not provided on the upper surface115of the first wafer110in the present Comparative Example. Accordingly, the upper surface115is entirely flat. A semiconductor layer120is disposed on the upper surface115of the first wafer110. Similar to those described in the embodiment above, the outer peripheral portion of the semiconductor layer120has a relatively large thickness. In particular, as seen from the center C, the outer end portions located in the first directions V1have thick film portions120athat have greater thickness than the outer end portions of other directions.

Next, a second wafer30is bonded to the first wafer110via the semiconductor layer120. At this time, the thick film portions120aof the semiconductor layer120are opposite to the inclined portion33of the second wafer30, such that the thick film portions120acan be prevented from being in contact with the second wafer30.

However, when the semiconductor layer120is formed using the first wafer110having entirely flat upper surface115as in the present comparative example, unintended growth of the semiconductor layer may occur at the outer end portion of the semiconductor layer120, from which cracks121may occur. As described above, in the present comparative example, the upper surface115of the first wafer110is flat without any steps, such that cracks121occurring in the outer end portion of the semiconductor layer120may easily propagate into the center portion of the semiconductor layer120. This results in a reduction in the yield of the semiconductor layer120, which results in a reduction in the productivity of the semiconductor elements. Such cracks in the outer end portion of the semiconductor layer120tends to occur when the semiconductor layer120includes a semiconductor layer containing aluminum (Al). It is assumed that, as described above, unintended growth tends to occur in the outer end portion of the semiconductor layer120when a semiconductor layer containing aluminum (Al) is contained in the semiconductor layer120, and cracks tends to occur in the portion of unintended growth.

Reference Example

Next, Reference Example will be described.

FIG. 8Ais a schematic plan view illustrating a method of manufacturing semiconductor elements according to Reference ExampleFIG. 8Bis a schematic partial cross-sectional end view illustrating a method of manufacturing semiconductor elements according to Reference Example.

As shown inFIG. 8AandFIG. 8B, in the Reference Example, a first region211and a second region212are provided on the upper surface215of the first wafer210. Any protrusion is not provided in the first region211and the first region211has an outer periphery in a circular shape in a top view. Accordingly, the thick film portions220aof the semiconductor layer220are formed in an outer peripheral portion in the first region211of the semiconductor layer220at locations in the first directions V1as seen from the center C. The outline of the first wafer210is substantially the same as the outline of the second wafer30. Because the first region211is not provided with any protrusions, the thick film portions220aare abutted to the flat portion32of the lower surface31of the second wafer30.

In the Reference Example, the second region212is provided on the upper surface215of the first wafer210, such that even when cracks occur in the example of the semiconductor layer220, propagation of the cracks are interrupted by the step216between the first region211and the second region212. Accordingly, cracks generated in the outer end portion of the semiconductor layer220are unlikely to propagate into the center portion of the semiconductor layer220.

However, in Reference Example, defect may occur at the time of bonding the second wafer30to the first wafer210via the semiconductor layer220. More specifically, when the thick film portions220aof the semiconductor layer220come in contact with the flat portion32of the second wafer30, portions of the semiconductor layer220other than the thick film portions220amay not be reliably brought in contact with the second wafer30, which may cause defective bonding. Having such a bonding defect, sufficient stability in the structure containing the first wafer210, the semiconductor layer220, and the second wafer30cannot be obtained in successive manufacturing operations, which may result in a reduction in the productivity of the semiconductor elements.

Test Example

Next, test example will be described.

FIG. 9Ais a schematic plan view illustrating the first wafer110and the semiconductor layer120according to one test example of the present invention.FIG. 9Bis a graph in which the horizontal axis represents a location in a radius direction and the vertical axis represents a height of an upper surface of the semiconductor layer120to illustrate the shape of the semiconductor layer120taken along line segment A-A′ shown inFIG. 9A.FIG. 9Cis a graph in which the horizontal axis represents an angle θ and the vertical axis represents a protruding degree H to illustrate the shape of the semiconductor layer120along the circle B shown inFIG. 9A.

The term “angle θ” used in the present specification refers to a central angle whose apex is the center C of the first wafer110. The direction of 0=0° is in conformity to one of the second directions V2. The term “protruding amount H” used in the present specification refers to a difference between a height of an edge of the semiconductor layer120and a height of a location 70 μm spaced apart from the edge of the semiconductor layer120toward the center C.FIG. 9BandFIG. 9Cshow the measurement results obtained, for example, by using a surface roughness measuring device.

In the present test example, a semiconductor layer120containing a gallium nitride-based semiconductor was epitaxially grown on the first wafer110made of sapphire, by using a MOCVD method. The semiconductor layer120contains an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer located between the n-type semiconductor layer and the p-type semiconductor layer. In the present test example and the comparative example and the reference example, the semiconductor layers are disposed under similar conditions. The semiconductor layer120is disposed with an average thickness of 10 μm.

As shown inFIG. 9B, the outer end portion becomes thicker than other portions in the semiconductor layer120. As shown inFIG. 9C, the thickness of the outer end portion of the semiconductor layer120has an angle dependency such that as seen from the center C, portions located in the second directions V2have a protruding amount H in a range of about 1.5 μm to about 3 μm, and portions located in the first directions V1have a protruding amount H in a range of about 4 μm to about 5 μm. That is, the outer end portions in the first directions V1were thicker than the outer end portions in the second directions V2.

For this reason, when the first region211has a circular outer shape as in the reference example described above, the thick film portions220aof the semiconductor layer220are brought in contact with the flat portion32of the second wafer30, defective bonding may occur. In order that the thick film portions220anot to be brought in contact with the flat portion32, a width in radial direction of the inclined portion33of the second wafer30may be increased, or the first wafer210having a diameter greater than that of the second wafer30may be employed. However, the size and shape of wafers have been standardized, such that a change in the size and/or shape requires a change in the specification of most of the processing devices used for the manufacturing semiconductor elements, resulting in a significant decrease in overall productivity of the semiconductor elements. Also, the number of semiconductor elements obtained by a series of operation may decrease.

In contrast, according to the embodiments described above, propagation of cracks can be interrupted and the thick film portions20acan be prevented from being in contact with the second wafer30, such that the semiconductor elements can be manufactured with good productivity, while using wafers complying existing standards.

The present disclosure can be used, for example, in manufacturing semiconductor elements such as light-emitting diodes (LEDs) and laser diodes (LDs).

It is to be understood that although embodiments of the present invention have been described, various other embodiments and variants may occur to those skilled in the art that are within the scope and spirit of the invention, and such other embodiments and variants are intended to be encompassed by the following claims.