Method of removing surface defects or other recesses during the formation of a semiconductor device

A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate. This etch continues until the surface defect in the dielectric layer is removed, thereby forming a nonrecessed plug.

FIELD OF THE INVENTION 
This invention relates to the field of semiconductor assembly, and more 
particularly to a method for removing surface defects from oxide or other 
materials. 
BACKGROUND OF THE INVENTION 
A structure commonly formed during the manufacture of semiconductor devices 
such as microprocessors, memory devices, and logic devices includes a plug 
or stud manufactured from polycrystalline silicon (poly) or metal such as 
tungsten. For purposes of illustration only, this disclosure discusses the 
formation of a plug from poly. The plug typically contacts a doped layer 
in a semiconductor substrate or contacts some other underlying structure. 
To manufacture the plug, a masked dielectric layer is formed over the 
underlying structure and an etch is completed to form a hole in the 
dielectric which exposes the underlying structure to which contact is to 
be made. A blanket poly layer is deposited over the dielectric layer which 
fills the hole in the dielectric layer and contacts the underlying 
structure. The poly is then removed from a planar surface of the 
dielectric, typically using a chemical mechanical polishing (CMP) process 
which leaves the plug formed within the dielectric layer. 
Ideally, the process described above would leave a poly plug having an 
upper surface which is flush with the upper level of the dielectric layer. 
CMP results in a sufficiently-flush plug but it is not a particularly 
clean or uniform process and, in practice, can damage surface structures. 
Previous dry etches are cleaner than CMP but can result in a plug having a 
concave upper surface which is recessed into the dielectric layer. It is 
difficult to form a reliable electrical connection to a recessed plug with 
a subsequently formed layer such as metal. 
Another problem with the process described above results from surface 
defects in the dielectric, such as surface scratches, cracks, or other 
voids or recesses formed during manufacture of the dielectric layer. 
During conductor formation these surface defects are filled with poly 
which remains in the void after CMP removal of the poly from the surface 
of the dielectric. The poly remaining in the voids, also referred to as 
"stringers," can form a short between other conductive structures such as 
between two or more plugs or between other structures such as metal lines 
which are subsequently formed. 
A method for forming a conductive plug or stud which reduces or eliminates 
the problems described above would be desirable. 
SUMMARY OF THE INVENTION 
The present invention provides a new method that reduces problems 
associated with the manufacture of semiconductor devices, particularly 
problems resulting in a concave profile of a conductive plug and resulting 
in stringers or other undesirable conductive fragments. In accordance with 
one embodiment of the invention a dielectric layer is formed having a 
desired hole therein and further having an undesired void therein. A 
blanket conductive layer is formed over the dielectric layer and a first 
etch is performed which clears a portion of the conductive layer. The 
first etch removes the conductive layer at a substantially faster rate 
than it removes the dielectric layer. Subsequently, a second etch is 
performed which removes the conductive layer and the dielectric layer at 
about the same rate. At least a portion of the dielectric layer is removed 
during this etch to remove the void and any conductive layer within the 
void. 
The first etch quickly clears the conductive layer and ideally stops just 
as the underlying dielectric layer is exposed. The second etch removes the 
dielectric layer and the conductive layer ideally at the same rate to form 
a conductive plug having an upper surface which is flush with an upper 
surface of the dielectric layer. It would be possible to perform the 
second etch only and omit the first etch, but the chemistry required for 
the second etch removes the conductive layer at a much slower rate and 
thus would decrease manufacturing throughput. 
Objects and advantages will become apparent to those skilled in the art 
from the following detailed description read in conjunction with the 
appended claims and the drawings attached hereto.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
A first embodiment of an inventive method which removes a void from a layer 
of dielectric material during the formation of a semiconductor device is 
depicted in FIGS. 1-3. As depicted in FIG. 1 a dielectric layer 10, in 
this embodiment borophosphosilicate glass (BPSG), is formed over a 
semiconductor substrate assembly 12. For purposes of illustration only, in 
this embodiment the assembly comprises a semiconductor substrate 14 having 
a doped region 16 therein. It should be noted, however, that the 
semiconductor substrate assembly 12 can comprise any number of structures 
such as capacitor plates or portions thereof, or conductive lines or other 
conductive structures. Further, the dielectric layer can comprise any 
number of oxides or nitrides. In this inventive embodiment the dielectric 
has a hole 18 therein and further comprises one or more voids 20 in an 
upper surface. Voids in dielectric are known to occur through previous 
manufacturing steps such as chemical mechanical polishing, through 
accidental contact with objects during production, or from manufacturing 
defects. These surface defects are generally much shallower than other 
holes or contacts intentionally formed in the dielectric. 
FIG. 1 further depicts a blanket conductive layer 22 such as 
polycrystalline silicon (poly) formed in the hole 18 to contact the doped 
region 16 in the substrate 14, which also fills the voids 20. 
After forming the FIG. 1 structure the conductive layer 22 is etched using 
an isotropic or an anisotropic etch to result in the structure of FIG. 2. 
In this embodiment an anisotropic etch is used which etches the conductive 
layer at a substantially faster rate than it etches the dielectric. One 
possible etch which removes poly substantially faster than it removes BPSG 
comprises an environment in an Applied Materials 5000 etcher having a 
pressure of from 20 to 60 millitorr, (preferably about 25 millitorr), a 
power of from 150 to 350 watts (preferably about 250 watts), zero to 40 
Gauss (preferably about zero Gauss) and a feed gas flow rate comprising 40 
to 80 standard cubic centimeters (sccm) NF.sub.3 and zero to 15 sccm 
Cl.sub.2 (preferably about 65 sccm NF.sub.3 and about 6 sccm Cl.sub.2). An 
etch for a duration of about 60 seconds will remove about 4,200 angstroms 
(.ANG.) of poly. Another etch selective to the dielectric which would 
provide adequate uniformity and endpoint control includes the use of an 
NF.sub.3, He, and O.sub.2 chemistry. The endpoint of the etch should be 
called as soon as the poly over the surface of the dielectric begins to 
clear in order to prevent the plug from over-recessing. In general, once 
the exposed poly on the surface of the dielectric goes from 100% exposed 
poly to about 10% or less exposed poly and about 90% or more exposed 
dielectric, the endpoint should be called. 
The etch is ideally timed to produce a conductive plug 24 which is flush 
with the dielectric 10. Leaving the plug flush, however, leaves conductive 
material within the voids which can form "stringers" or other conductive 
fragments and short subsequently formed layers and results in a 
malfunctioning device. If the conductive layer is over-etched to remove 
the material from the voids, an undesirable recessed conductive plug is 
formed which is difficult to connect with subsequent conductive layers. 
Next, an etch is performed on the FIG. 2 structure which removes the 
conductive layer and the dielectric layer simultaneously at about the same 
rate. This etch removes the stringers 20, a portion of the dielectric 10 
including the dielectric comprising the void, and a portion of the plug 24 
to result in the FIG. 3 structure. Ideally, the etch will remove the 
conductive layer and the dielectric layer at a 1:1 ratio, but removal of 
the two layers at about the same rate is sufficient if the conductive 
layer is not overly recessed (which could create another recess at the 
location of the conductive layer) or as long as an inordinate amount of 
dielectric is not removed relative to the conductive layer (which could 
result in an inadequate oxide thickness or portions of the conductive 
layer remaining on the surface of the wafer assembly). The etch rate 
should be sufficiently close to a 1:1 ratio such that subsequent 
processing steps are not adversely affected. To ensure removal of the 
void, the etch can be performed for a sufficient duration to over-etch the 
void in the dielectric. The actual amount of material removed during this 
nonselective etch is determined by the depth of the surface defect plus 
the desired over-etch margin. This is an optimization process determined 
by yield enhancement data. With typical processing using the inventive 
method, at least 300.ANG. of dielectric material will be removed although 
the inventive process may be useful for removing less than 300.ANG. 
depending on the device being manufactured and the individual use of the 
invention. 
An example of a dry or plasma etch which removes polycrystalline silicon 
and BPSG at about the same rate comprises an environment in an Applied 
Materials 5000 etcher having a pressure of from 150 to 250 millitorr 
(preferably about 200 millitorr), a power of from 650 to 850 watts 
(preferably about 750 watts), from about zero to 40 Gauss (preferably 
about zero Gauss), and a feed gas flow rate comprising 40 to 80 sccm 
CF.sub.4, zero to 20 sccm CHF.sub.3, and zero to 60 sccm Ar (preferably 
about 60 sccm CF.sub.4, about 12 sccm CHF.sub.3, and about 40 sccm Ar). An 
etch for a duration of about 20 seconds will remove about 1,300.ANG. of 
BPSG oxide and/or poly. 
In another embodiment the conductive layer of FIG. 1 is somewhat 
underetched during the first etch to result in the structure of FIG. 4. 
The second etch is then performed on the FIG. 4 structure until the voids 
in the dielectric and the stringers or other conductive fragments are 
adequately removed. This embodiment reduces the likelihood of over-etching 
the conductive plug which would recess the plug during the first etch, yet 
minimizes the impact on manufacturing throughput. 
In yet another embodiment the first etch is omitted and only the etch which 
etches the conductive layer and dielectric layer at a 1:1 ratio is 
performed on the FIG. 1 structure. While this etch will minimize recessing 
the conductive plug within the dielectric layer, throughput will be more 
greatly affected since the second etch removes the conductive layer more 
slowly than the first etch. 
Finally, nitride may be used instead of the oxide described above. In an 
embodiment comprising nitride the same first and second etches can be 
used. The second etch in a nitride embodiment can be optimized for nitride 
by altering the preferred parameter values away from those listed for 
oxide, but within the ranges specified. Parameter values close to those 
preferred in the oxide embodiment would likely yield optimized results. 
While this invention has been described with reference to illustrative 
embodiments, this description is not meant to be construed in a limiting 
sense. Various modifications of the illustrative embodiments, as well as 
additional embodiments of the invention will be apparent to persons 
skilled in the art upon reference to this description. It is therefore 
contemplated that the appended claims will cover any such modifications or 
embodiments as fall within the true scope of the invention.