Amplifier circuit having adjustable gain

An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of priority to Taiwan Patent Application No. 110127807, filed on Jul. 29, 2021. The entire content of the above identified application is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to an amplifier circuit, and more particularly to an amplifier circuit having an adjustable gain.

BACKGROUND OF THE DISCLOSURE

With the rise in popularity of the Internet and mobile devices, a demand for communication quality is getting higher. However, conventional single-stage amplifiers have a limited range of gain values, and cannot meet current design or practical requirements. Therefore, providing an amplifier circuit having an adjustable gain is an important issue in the related field.

SUMMARY OF THE DISCLOSURE

In response to the above-referenced technical inadequacy, the present disclosure provides an amplifier circuit having an adjustable gain.

In one aspect, the present disclosure provides an amplifier circuit having an adjustable gain. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal is used for receiving an input signal. The output terminal is used for outputting an output signal. The amplifier includes an input terminal and an output terminal. The input terminal of the amplifier receives the input signal through the input terminal of the amplifier circuit. The output terminal of the amplifier is used for outputting the input signal that is amplified. The attenuation circuit includes an input terminal and an output terminal. The input terminal of the attenuation circuit is coupled to the output terminal of the amplifier, and the output terminal of the attenuation circuit is coupled to the output terminal of the amplifier circuit, so as to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal. Alternatively, the input terminal of the attenuation circuit is coupled to the input terminal of the amplifier circuit, and the output terminal of the attenuation circuit is coupled to the output terminal of the amplifier circuit, so as to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

First Embodiment

Referring toFIG.1,FIG.1is a schematic block diagram of an amplifier circuit having an adjustable gain according to a first embodiment of the present disclosure. An amplifier circuit1having an adjustable gain of the first embodiment of the present disclosure includes an input terminal11and an output terminal12. Moreover, the amplifier circuit1can include an amplifier20and an attenuation circuit40.

The input terminal11can be used for receiving an input signal Sin, and the output terminal12can be used for outputting an output signal Sout. The output signal Sout can be used in a back-end circuit. Each of the input signal Sin and the output signal Sout is, for example but not limited to, a radio frequency signal.

An input terminal of the amplifier20can receive the input signal Sin through the input terminal11, and can amplify the input signal Sin according to a gain of the amplifier20, so as to output the input signal that is amplified Sin′ through an output terminal of the amplifier20. The amplifier20can include a low-noise amplifier or a power amplifier.

An input terminal of the attenuation circuit40can be coupled to the output terminal of the amplifier20, and an output terminal of the attenuation circuit40can be coupled to the output terminal12. The attenuation circuit40can be configured to provide a plurality of attenuation to the input signal that is amplified Sin′, and accordingly generate an attenuation signal Sat1. For example, the attenuation circuit40can select one of the plurality of attenuations according to a gain value required for the amplifier circuit1, so as to attenuate an amplitude of the input signal that is amplified Sin′ to a certain value, thereby generating the attenuation signal Sat1. The output signal Sout can be generated from the attenuation signal Sat1. In this way, the gain value of the amplifier circuit1can be related to a degree of the attenuation of the input signal that is amplified Sin′. That is to say, the gain value required for the amplifier circuit1can be achieved based on the degree of attenuation of the input signal that is amplified Sin′. The gain value of the amplifier circuit1can be 0 dB or more. It should be noted that, since the attenuation circuit40can be used for providing the plurality of attenuations to the input signal that is amplified Sin′, the gain value of the amplifier circuit1is no longer limited to a gain value range of the amplifier20, but a gain value range of the amplifier circuit1can be expanded and the gain value of the amplifier circuit1can be adjusted through the attenuation circuit40. In addition, since the attenuation circuit40is arranged behind the output terminal of the amplifier20, the attenuation circuit40is less likely to generate a loading effect at the input terminal of the amplifier20, such that a performance of the amplifier circuit1is less likely to be affected, and a linearity and a noise figure of the amplifier circuit1can be maintained.

Second Embodiment

Referring toFIG.2,FIG.2is a schematic block diagram of an amplifier circuit having an adjustable gain according to a second embodiment of the present disclosure. The difference between the second embodiment and the first embodiment is that, an amplifier circuit2having an adjustable gain of the second embodiment of the present disclosure can include the amplifier20and an attenuation circuit50.

An input terminal of the attenuation circuit50can be coupled to the input terminal11, and an output terminal of the attenuation circuit50can be coupled to the output terminal12. The attenuation circuit50can be configured to provide a plurality of attenuation to the input signal Sin, and accordingly generate an attenuation signal Sat2. For example, the attenuation circuit50can select one of the plurality of attenuations according to a gain value required for the amplifier circuit2, so as to attenuate an amplitude of the input signal Sin to a certain value, thereby generating the attenuation signal Sat2.

Furthermore, the amplifier circuit2can operate in an amplification mode or a bypass mode. When an intensity of the input signal Sin is not strong enough and needs to be amplified by the amplifier20, the amplifier20is enabled and the amplifier circuit2can operate in the amplification mode so as to have a first gain value. Moreover, the input signal Sin is input from the input terminal11to the amplifier20, and the amplifier20amplifies the input signal Sin according to a gain of the amplifier20, so as to output the input signal that is amplified Sin′ from the output terminal of the amplifier20. The output signal Sout can be generated from the input signal that is amplified Sin′. Accordingly, the first gain value is related to the gain of the amplifier20. When the intensity of the input signal Sin is strong enough that the amplification through the amplifier20is no longer required, the amplifier20is disabled and the amplifier circuit2can operate in the bypass mode so as to have a second gain value. It should be noted that unnecessary current consumption can be decreased in the amplifier20that is disabled. Further, the input signal Sin is input from the input terminal11to the attenuation circuit50, and the attenuation circuit50attenuates the input signal Sin according to the one of the plurality of attenuations that is selected so as to generate the attenuation signal Sat2. The output signal Sout can be generated from the attenuation signal Sat2. In this way, the second gain value is related to a degree of the attenuation of the input signal Sin. That is to say, the second gain value required for the amplifier circuit2can be achieved based on the degree of attenuation of the input signal Sin. The second gain value can be less than the first gain value. The first gain value can be greater than 0 dB, and the second gain value can be 0 dB or less. It should be noted that, since the attenuation circuit50can be used for providing the plurality of attenuations to the input signal Sin, a gain value range of the amplifier circuit2can be expanded and the gain value of the amplifier circuit2can be adjusted through the attenuation circuit50.

Third Embodiment

Referring toFIG.3,FIG.3is a schematic block diagram of an amplifier circuit having an adjustable gain according to a third embodiment of the present disclosure. The difference between the third embodiment and the second embodiment is that, an amplifier circuit3having an adjustable gain of the third embodiment of the present disclosure can further include the attenuation circuit40. The input terminal of the attenuation circuit40can be coupled to the output terminal of the amplifier20, and the output terminal of the attenuation circuit40can be coupled to the output terminal12. The attenuation circuit40and the attenuation circuit50can provide the plurality of attenuations to the input signal that is amplified Sin′ and the input signal Sin, respectively, and accordingly generate the attenuation signal Sat1and the attenuation signal Sat2, respectively.

Compared to the second embodiment, when the amplifier circuit3operates in the amplification mode, the attenuation circuit40attenuates the input signal that is amplified Sin′ according to the one of the plurality of attenuations that is selected, so as to generate the attenuation signal Sat1. The output single Sout can be generated from the attenuation signal Sat1. In this way, the first gain value is related to the degree of attenuation of the input signal that is amplified Sin′. That is to say, in the present embodiment, the first gain value required for the amplifier circuit3can be achieved based on the degree of attenuation of the input signal that is amplified Sin′, and the second gain value required for the amplifier circuit3can be achieved based on the degree of attenuation of the input signal Sin. Since the input signal that is amplified Sin′ is generated after the input signal Sin passes through the amplifier20, the first gain value can be greater than the second gain value. The first gain value can be 0 dB or more, and the second gain value can be 0 dB or less.

Referring toFIG.4,FIG.4is a schematic circuit layout diagram of the amplifier circuit1having the adjustable gain according to the first embodiment of the present disclosure. An amplifier201and an attenuation circuit401ofFIG.4can respectively correspond to the amplifier20and the attenuation circuit40ofFIG.1.

For example, as shown inFIG.4, the amplifier201can include a transistor M1and a transistor M2. A first terminal of the transistor M1is coupled to an output terminal of the amplifier201, and a control terminal of the transistor M1can be used for receiving an operation signal VGG. The operation signal VGG can be used for enabling or disabling the amplifier201. A first terminal of the transistor M2is coupled to a second terminal of the transistor M1, a second terminal of the transistor M2is coupled to a reference potential terminal13, and a control terminal of the transistor M2is coupled to an input terminal of the amplifier201and can be further used for receiving a bias signal Vbias. The bias signal Vbias can be used for biasing the transistor M2. The reference potential terminal13can be, but is not limited to, a ground potential terminal in a system. The attenuation circuit401can include a plurality of attenuation units ATU0to ATUn. Each of the plurality of attenuation units ATU0to ATUn is coupled between an input terminal and an output terminal of the attenuation circuit401, and can be used for providing one of the plurality of attenuations. For example, the attenuation unit ATU0can be used for providing an attenuation of 0 dB, the attenuation unit ATU1can be used for providing an attenuation of 5 dB, the attenuation unit ATUi can be used for providing an attenuation of 10 dB, and the attenuation unit ATUn can be used for providing an attenuation of 20 dB. In other words, each of the plurality of attenuation units ATU0to ATUn can be used for providing an attenuation of a different amount. It should be noted that, when one of the plurality of attenuation units (e.g., the attenuation unit ATU0) is enabled, the rest of the plurality of attenuation units (e.g., the attenuation units ATU1to ATUn) are disabled.

The one of the plurality of attenuation units (e.g., the attenuation unit ATU0) can include a switch SW40, and a control terminal of the switch SW40is used for receiving a control signal CS40. The control signal CS40can be used for turning on or turning off the switch SW40, so as to enable or disable the attenuation unit ATU0(e.g., turning on the switch SW40can enable the attenuation unit ATU0, thereby providing the attenuation of 0 dB).

The rest of the plurality of attenuation units (e.g., the attenuation units ATU1to ATUn) can each include a π-type attenuator. Further, the π-type attenuator of the attenuation unit ATU1can include a switch SW411, a switch SW421, and a switch SW431, and a control terminal of each of the switch SW411, the switch SW421, and the switch SW431is used for receiving a control signal CS41; the control signal CS41can be used for correspondingly turning on or turning off the switch SW411, the switch SW421, and the switch SW431, so as to enable or disable the attenuation unit ATU1(e.g., turning on the switch SW411, the switch SW421, and the switch SW431can enable the attenuation unit ATU1, thereby providing the attenuation of 5 dB); the π-type attenuator of the attenuation unit ATUi can include a switch SW41i, a switch SW42i, and a switch SW43i, and a control terminal of each of the switch SW41i, the switch SW42i, and the switch SW43iis used for receiving a control signal CS4i; the control signal CS4ican be used for correspondingly turning on or turning off the switch SW41i, the switch SW42i, and the switch SW43i, so as to enable or disable the attenuation unit ATUi; the π-type attenuator of the attenuation unit ATUn can include a switch SW41n, a switch SW42n, and a switch SW43n, and a control terminal of each of the switch SW41n, the switch SW42n, and the switch SW43nis used for receiving a control signal CS4n; the control signal CS4ncan be used for correspondingly turning on or turning off the switch SW41n, the switch SW42n, and the switch SW43n, so as to enable or disable the attenuation unit ATUn, and so on, where i and n are positive numbers. The control signals CS40to CS4ncan be provided by an internal circuit of the attenuation circuit401(not shown in the figures) or an external circuit other than the attenuated circuit401(not shown in the figures). It should be noted that, although a quantity of the attenuation units shown inFIG.4is greater than two, in practice, the quantity of the attenuation units may vary depending on design or practical requirements. Therefore, the quantity of the attenuation units shown inFIG.4is for illustrative purposes only, and should not be construed as limiting the present disclosure.

In addition, a first terminal of the switch SW40is coupled to the input terminal of the attenuation circuit401, and a second terminal of the switch SW40is coupled to the output terminal of the attenuation circuit401. A first terminal of each of the switches SW411to SW41nis coupled to the input terminal of the attenuation circuit401, and a second terminal of each of the switches SW411to SW41nis coupled to the reference potential terminal13. A first terminal of each of the switches SW421to SW42nis coupled to the output terminal of the attenuation circuit401, and a second terminal of each of the switches SW421to SW42nis coupled to the reference potential terminal13. A first terminal of each of the switches SW431to SW43nis coupled to the input terminal of the attenuation circuit401, and a second terminal of each of the switches SW431to SW43nis coupled to the output terminal of the attenuation circuit401. In another embodiment, the attenuation circuit40shown inFIG.3can also include an architecture of the attenuation circuit401shown inFIG.4.

The attenuation corresponding to each of the plurality of attenuation units ATU1to ATUn can be related to a resistance value of each of the plurality of attenuation units ATU1to ATUn. For example, a resistance value of an on-resistance of each of the switches SW411, SW421, and SW431, can be designed based on the attenuation corresponding to the attenuation unit ATU1; a resistance value of an on-resistance of each of the switches SW41i, SW42i, and SW43i, can be designed based on the attenuation corresponding to the attenuation unit ATUi; a resistance value of an on-resistance of each of the switches SW41n, SW42n, and SW43n, can be designed based on the attenuation corresponding to the attenuation unit ATUn, and so on. That is to say, the switches SW411to SW43ncan not only be used for switching the corresponding attenuation unit ATU1to ATUn, but also for providing the corresponding attenuation based on actual design. In another embodiment, the resistance values of the on-resistances of the switches SW411and SW421can be designed to be the same; the resistance values of the on-resistances of the switches SW41iand SW42ican be designed to be the same; the resistance values of the on-resistances of the switches SW41nand SW42ncan be designed to be the same, and so on. In addition, taking the attenuation units ATU1, ATUi, and ATUn being respectively used for providing the attenuations of 5 dB, 10 dB, and 20 dB as an example, the resistance value of the on-resistance of the switch SW431can be less than the resistance value of the on-resistance of the switch SW43i, and the resistance value of the on-resistance of the switch SW43ican be less than the resistance value of the on-resistance of the switch SW43n. In the present embodiment, through a design of a channel width-to-length ratio of the switches SW411to SW43n, the switches SW411to SW43neach can have the appropriate resistance value of the on-resistance. In this way, when one of the attenuation units ATU1to ATUn is enabled, the corresponding attenuation can be provided.

It should be noted that, the attenuation circuit401includes the plurality of π-type attenuators and can be accordingly considered as having a roughly symmetrical circuit architecture. Under such the circuit architecture, a difference between an impedance value of the input terminal of the attenuation circuit401and an impedance value of the output terminal of the attenuation circuit401can be within a predetermined range regardless of which one of the attenuation units ATU0to ATUn is enabled. The predetermined range can be ±10%. In another embodiment, the impedance value of the input terminal of the attenuation circuit401and the impedance value of the output terminal of the attenuation circuit401can be substantially equal, which can refer to a conjugate match that is achieved between the impedance value of the input terminal of the attenuation circuit401and the impedance value of the output terminal of the attenuation circuit401. That is to say, the impedance value of the output terminal of the attenuation circuit401is a conjugate complex number of the impedance value of the input terminal of the attenuation circuit401. Further, the impedance value of the input terminal of the attenuation circuit401can be an equivalent impedance value viewed inward from the input terminal of the attenuation circuit401, and the impedance value of the output terminal of the attenuation circuit401can be an equivalent impedance value viewed outward from the output terminal of the attenuation circuit401. In addition, a difference between an equivalent impedance value viewed inward from the output terminal of the amplifier201and an equivalent impedance value viewed outward from the output terminal12of the amplifier circuit1can also be within the predetermined range.

As shown inFIG.4, the amplifier circuit1can further include a matching circuit60, and capacitors AC1, AC2, and AC3. The matching circuit60is coupled between the output terminal of the amplifier201and the input terminal of the attenuation circuit401, and can be used for providing an output impedance matched to the amplifier201. The matching circuit60can include a resistor, an inductor, a capacitor, or any combination thereof. In the present embodiment, since in the attenuation circuit401the difference between the impedance value of the input terminal of the attenuation circuit401and the impedance value of the output terminal of the attenuation circuit401can be within the predetermined range, the arrangement of the attenuation circuit401does not easily affect a matching of the output impedance of the amplifier201.

The capacitor AC1is coupled between the matching circuit60and the attenuation circuit401, the capacitor AC2is coupled between the attenuation circuit401and the output terminal12, and the capacitor AC3is coupled between the attenuation circuit401and the reference potential terminal13. The capacitor AC1can be used for blocking a direct current bias from the amplifier201, and the capacitors AC2and AC3can be used for blocking a direct current bias from the attenuation circuit401.

Referring toFIG.5,FIG.5is another schematic circuit layout diagram of the attenuation circuit40of the amplifier circuit1or3having the adjustable gain according to the first embodiment or the third embodiment of the present disclosure. An attenuation circuit402ofFIG.5can correspond to the attenuation circuit40ofFIG.1orFIG.3.

The main difference between the attenuation circuit401shown inFIG.4and the attenuation circuit402ofFIG.5is that, the π-type attenuator of the attenuation unit ATU1can further include resistors R411, R421, and R431; the π-type attenuator of the attenuation unit ATUi can further include resistors R41i, R42i, and R43i; the π-type attenuator of the attenuation unit ATUn can further include resistors R41n, R42n, and R43n, and so on.

As shown inFIG.5, a first terminal of each of the resistors R411to R41nis coupled to the input terminal of the attenuation circuit402, and a second terminal of each of the resistors R411to R41nis coupled to the first terminal of the switches SW411to SW41nthat respectively correspond to the resistors R411to R41n. A first terminal of each of the resistors R421to R42nis coupled to the output terminal of the attenuation circuit402, and a second terminal of each of the resistors R421to R42nis coupled to the first terminal of the switches SW421to SW42nthat respectively correspond to the resistors R421to R42n. A first terminal of each of the resistors R431to R43nis coupled to the input terminal of the attenuation circuit402, and a second terminal of each of the resistors R431to R43nis coupled to the first terminal of the switches SW431to SW43nthat respectively correspond to the resistors R431to R43n.

The resistor R411to R43ncan be used for increasing a flexibility of the design corresponding to the resistance value of the attenuation units ATUi to ATUn. Further, the resistance values of the on-resistances of the switches SW411, SW421, and SW431and/or resistance values of the resistors R411, R421, and R431can be designed based on the attenuation corresponding to the attenuation unit ATU1; the resistance values of the on-resistances of the switches SW41i, SW42i, and SW43iand/or resistance values of the resistors R41i, R42i, and R43ican be designed based on the attenuation corresponding to the attenuation unit ATUi; the resistance values of the on-resistances of the switches SW41n, SW42n, and SW43nand/or resistance values of the resistors R41n, R42n, and R43ncan be designed based on the attenuation corresponding to the attenuation unit ATUn, and so on. That is to say, the switches SW411to SW43ncan not only be used for switching the corresponding attenuation unit ATUi to ATUn, but also for providing the corresponding attenuation based on actual design. In another embodiment, an overall resistance value of the switch SW411and the resistor R411and an overall resistance value of the switch SW421and the resistor R421can be designed to be the same; an overall resistance value of the switch SW41iand the resistor R41iand an overall resistance value of the switch SW42iand the resistor R42ican be designed to be the same; an overall resistance value of the switch SW41nand the resistor R41nand an overall resistance value of the switch SW42nand the resistor R42ncan be designed to be the same, and so on. In addition, taking the attenuation units ATU1, ATUi, and ATUn being respectively used for providing the attenuations of 5 dB, 10 dB, and 20 dB, as an example, an overall resistance value of the switch SW431and the resistor R431can be less than an overall resistance value of the switch SW43iand the resistor R43i, and the overall resistance value of the switch SW43iand the resistor R43ican be less than an overall resistance value of the switch SW43nand the resistor R43n. In the present embodiment, through a design of a channel width-to-length ratio of the switches SW411to SW43n, the switches SW411to SW43neach can have the appropriate resistance value of the on-resistance. In this way, when one of the attenuation units ATU1to ATUn is enabled, the corresponding attenuation can be provided.

Referring toFIG.6,FIG.6is still another schematic circuit layout diagram of the attenuation circuit40of the amplifier circuit1or3having the adjustable gain according to the first embodiment or the third embodiment of the present disclosure. An attenuation circuit403ofFIG.6can correspond to the attenuation circuit40ofFIG.1orFIG.3.

The main difference between the attenuation circuit402shown inFIG.5and the attenuation circuit403ofFIG.6is that, the resistors R411to R43nare arranged in different positions. As shown inFIG.6, the first terminal of each of the resistors R411to R41nis coupled to the second terminal of the switches SW411to SW41nthat respectively correspond to the resistors R411to R41n, and the second terminal of each of the resistors R411to R41nis coupled to the reference potential terminal13. The first terminal of each of the resistors R421to R42nis coupled to the second terminal of the switches SW421to SW42nthat respectively correspond to the resistors R421to R42n, and the second terminal of each of the resistors R421to R42nis coupled to the reference potential terminal13. The first terminal of each of the resistors R431to R43nis coupled to the second terminal of the switches SW431to SW43nthat respectively correspond to the resistors R431to R43n, and the second terminal of each of the resistors R431to R43nis coupled to the output terminal of the attenuation circuit403. A principle and operation of the attenuation circuit403are similar to those of the attenuation circuit402, and will not be reiterated herein. It should be noted that, when one of the plurality of attenuation units ATU1to ATUn is disabled, the switch SW431to SW43nthat corresponds to the one of the plurality of attenuation units ATU1to ATUn is turned off, such that a noise generated by the resistor R431to R43nthat corresponds to the one of the plurality of attenuation units ATU1to ATUn is less likely to affect a signal transmission path, thereby reducing a noise figure of the amplifier circuit.

Referring toFIG.7,FIG.7is yet another schematic circuit layout diagram of the attenuation circuit40of the amplifier circuit1or3having the adjustable gain according to the first embodiment or the third embodiment of the present disclosure. An attenuation circuit404ofFIG.7can correspond to the attenuation circuit40ofFIG.1orFIG.3.

The main difference between the attenuation circuit401shown inFIG.4and the attenuation circuit404ofFIG.7is that, one of the plurality of attenuation units (e.g., the attenuation unit ATU0) can include a switch SW70, and the rest of the plurality of attenuation units (e.g., the attenuation units ATU1to ATUn) can each include a T-type attenuator. As shown inFIG.7, a control terminal of the switch SW70is used for receiving a control signal CS70, and the control signal CS70can be used for turning on or turning off the switch SW70, thereby enabling or disabling the attenuation unit ATU0(e.g., turning on the switch SW70can enable the attenuation unit ATU0, thereby providing the attenuation of 0 dB); the T-type attenuator of the attenuation unit ATU1can include switches SW711, SW721, and SW731, and a control terminal of each of the switches SW711, SW721, and SW731is used for receiving a control signal CS71; the control signal CS71can be used for turning on or turning off the switches SW711, SW721, and SW731, thereby enabling or disabling the attenuation unit ATU1(e.g., turning on the switches SW711, SW721, and SW731can enable the attenuation unit ATU1, thereby providing the attenuation of 5 dB); the T-type attenuator of the attenuation unit ATUi can include switches SW71i, SW72i, and SW73i, and a control terminal of each of the switches SW71i, SW72i, and SW73iis used for receiving a control signal CS7i; the control signal CS7ican be used for turning on or turning off the switches SW71i, SW72i, and SW73i, thereby enabling or disabling the attenuation unit ATUi; the T-type attenuator of the attenuation unit ATUn can include switches SW71n, SW72n, and SW73n, and a control terminal of each of the switches SW71n, SW72n, and SW73nis used for receiving a control signal CS7n; the control signal CS7ncan be used for turning on or turning off the switches SW71n, SW72n, and SW73n, thereby enabling or disabling the attenuation unit ATUn, and so on, where i and n are positive numbers. The control signals CS70to CS7ncan be provided by an internal circuit of the attenuation circuit404(not shown in the figures) or an external circuit other than the attenuated circuit404(not shown in the figures). It should be noted that, although a quantity of the attenuation units shown inFIG.7is greater than two, in practice, the quantity of the attenuation units may vary depending on a practical application or a design requirement. Therefore, the quantity of the attenuation units shown inFIG.7is for illustrative purposes only, and should not be construed as limiting the present disclosure.

In addition, a first terminal of the switch SW70is coupled to the input terminal of the attenuation circuit404, and a second terminal of the switch SW70is coupled to the output terminal of the attenuation circuit404. A first terminal of each of the switches SW711to SW71nis coupled to the input terminal of the attenuation circuit404. A first terminal of each of the switches SW721to SW72nis correspondingly coupled to a second terminal of the switches SW711to SW71n, and a second terminal of each of the switches SW721to SW72nis coupled to the output terminal of the attenuation circuit404. A first terminal of each of the switches SW731to SW73nis correspondingly coupled to a second terminal of the switches SW711to SW71nand the first terminal of the switches SW721to SW72n, and a second terminal of each of the switches SW731to SW73nis coupled to the reference potential terminal13.

The attenuation corresponding to each of the plurality of attenuation units ATUi to ATUn can be related to a resistance value of each of the plurality of attenuation units ATUi to ATUn. For example, a resistance value of an on-resistance of each of the switches SW711, SW721, and SW731, can be designed based on the attenuation corresponding to the attenuation unit ATU1; a resistance value of an on-resistance of each of the switches SW71i, SW72i, and SW73i, can be designed based on the attenuation corresponding to the attenuation unit ATUi; a resistance value of an on-resistance of each of the switches SW71n, SW72n, and SW73n, can be designed based on the attenuation corresponding to the attenuation unit ATUn, and so on. That is to say, the switches SW711to SW73ncan not only be used for switching the corresponding attenuation unit ATUi to ATUn, but also for providing the corresponding attenuation based on actual design. In another embodiment, the resistance values of the on-resistances of the switches SW711and SW721can be designed to be the same; the resistance values of the on-resistances of the switches SW71iand SW72ican be designed to be the same; the resistance values of the on-resistances of the switches SW71nand SW72ncan be designed to be the same, and so on. In addition, taking the attenuation units ATU1, ATUi, and ATUn being respectively used for providing the attenuations of 5 dB, 10 dB, and 20 dB as an example, the resistance value of the on-resistance of the switch SW731can be greater than the resistance value of the on-resistance of the switch SW73i, and the resistance value of the on-resistance of the switch SW73ican be greater than the resistance value of the on-resistance of the switch SW73n. In the present embodiment, through a design of a channel width-to-length ratio of the switches SW711to SW73n, the switches SW711to SW73ncan each have the appropriate resistance value of the on-resistance. In this way, when one of the attenuation units ATU1to ATUn is enabled, the corresponding attenuation can be provided.

It should be noted that, the attenuation circuit404includes the plurality of T-type attenuators and can be accordingly considered as having a roughly symmetrical circuit architecture. Under such circuit architecture, a difference between an impedance value of the input terminal of the attenuation circuit404and an impedance value of the output terminal of the attenuation circuit404can be within a predetermined range regardless of which one of the attenuation units ATU0to ATUn is enabled. The predetermined range can be ±10%. In another embodiment, the impedance value of the input terminal of the attenuation circuit404and the impedance value of the output terminal of the attenuation circuit404can be substantially equal, which can refer to a conjugate match is achieved between the impedance value of the input terminal of the attenuation circuit404and the impedance value of the output terminal of the attenuation circuit404. That is to say, the impedance value of the output terminal of the attenuation circuit404is a conjugate complex number of the impedance value of the input terminal of the attenuation circuit404. Further, the impedance value of the input terminal of the attenuation circuit404can be an equivalent impedance value viewed inward from the input terminal of the attenuation circuit404, and the impedance value of the output terminal of the attenuation circuit404can be an equivalent impedance value viewed outward from the output terminal of the attenuation circuit404. In addition, in conjunction withFIG.4andFIG.7, a difference between an equivalent impedance value viewed inward from the output terminal of the amplifier201and an equivalent impedance value viewed outward from the output terminal12of the amplifier circuit1can also be within the predetermined range.

Referring toFIG.8,FIG.8is yet another schematic circuit layout diagram of the attenuation circuit40of the amplifier circuit1or3having the adjustable gain according to the first embodiment or the third embodiment of the present disclosure. An attenuation circuit405ofFIG.8can correspond to the attenuation circuit40ofFIG.1orFIG.3.

The main difference between the attenuation circuit405shown inFIG.8and the attenuation circuit404ofFIG.7is that, the T-type attenuator of the attenuation unit ATU1can further include resistors R711, R721, and R731; the T-type attenuator of the attenuation unit ATUi can further include resistors R71i, R72i, and R73i; the T-type attenuator of the attenuation unit ATUn can further include resistors R71n, R72n, and R73n, and so on.

As shown inFIG.8, a first terminal of each of the resistors R711to R71nis coupled to the second terminal of the switches SW711to SW71nthat respectively correspond the resistors R711to R71n, and a second terminal of each of the resistors R711to R71nis coupled to the first terminal of the switches SW731to SW73nthat respectively correspond to the resistors R711to R71n. A first terminal of each of the resistors R721to R72nis coupled to the first terminal of the switches SW731to SW73nthat respectively correspond to the resistors R721to R72n, and a second terminal of each of the resistors R721to R72nis coupled to the first terminal of the switches SW721to SW72nthat respectively correspond to the resistors R721to R72n. A first terminal of each of the resistors R731to R73nis coupled to the second terminal of the switches SW731to SW73nthat respectively correspond to the resistors R731to R73n, and a second terminal of each of the resistors R731to R73nis coupled to the reference potential terminal13.

The resistor R711to R73ncan be used for increasing a flexibility of the design corresponding to the resistance value of the attenuation units ATUi to ATUn. Further, the resistance values of the on-resistances of the switches SW711, SW721, and SW731and/or resistance values of the resistors R711, R721, and R731can be designed based on the attenuation corresponding to the attenuation unit ATU1; the resistance values of the on-resistances of the switches SW71i, SW72i, and SW73iand/or resistance values of the resistors R71i, R72i, and R73ican be designed based on the attenuation corresponding to the attenuation unit ATUi; the resistance values of the on-resistances of the switches SW71n, SW72n, and SW73nand/or resistance values of the resistors R71n, R72n, and R73ncan be designed based on the attenuation corresponding to the attenuation unit ATUn, and so on. That is to say, the switches SW711to SW73ncan not only be used for switching the corresponding attenuation unit ATUi to ATUn, but also for providing the corresponding attenuation based on actual design. In another embodiment, an overall resistance value of the switch SW711and the resistor R711and an overall resistance value of the switch SW721and the resistor R721can be designed to be the same; an overall resistance value of the switch SW71iand the resistor R71iand an overall resistance value of the switch SW72iand the resistor R72ican be designed to be the same; an overall resistance value of the switch SW71nand the resistor R71nand an overall resistance value of the switch SW72nand the resistor R72ncan be designed to be the same, and so on. In addition, taking the attenuation units ATU1, ATUi, and ATUn being respectively used for providing the attenuations of 5 dB, 10 dB, and 20 dB, as an example, an overall resistance value of the switch SW731and the resistor R731can be greater than an overall resistance value of the switch SW73iand the resistor R73i, and the overall resistance value of the switch SW73iand the resistor R73ican be greater than an overall resistance value of the switch SW73nand the resistor R73n. In the present embodiment, through a design of a channel width-to-length ratio of the switches SW711to SW73n, the switches SW711to SW73neach can have the appropriate resistance value of the on-resistance. In this way, when one of the attenuation units ATUi to ATUn is enabled, the corresponding attenuation can be provided. It should be noted that, when one of the plurality of attenuation units ATUi to ATUn is disabled, the switch SW711to SW71nand SW721to SW72nthat corresponds to the one of the plurality of attenuation units ATU1to ATUn is turned off, such that a noise generated by the resistor R711to R71nand R721to R72nthat corresponds to the one of the plurality of attenuation units ATUi to ATUn is less likely to affect a signal transmission path, thereby reducing a noise figure of the amplifier circuit.

Referring toFIG.9,FIG.9is a schematic circuit layout diagram of the amplifier circuit2having the adjustable gain according to the second embodiment of the present disclosure. An amplifier201and an attenuation circuit501ofFIG.9respectively correspond to the amplifier20and the attenuation circuit50ofFIG.2. The amplifier201is described in the above embodiment, and is not reiterated herein.

In the present embodiment, the attenuation circuit501can include the same components as the attenuation circuit403shown inFIG.6, but the present disclosure is not limited thereto. In another embodiment, the attenuation circuit501can include the same components as one of the attenuation circuits401,402,404, and405respectively shown inFIG.4,FIG.5,FIG.7, andFIG.8.

Similarly, the attenuation circuit50shown inFIG.3can also include the same components as one of the attenuation circuits401to405respectively shown inFIG.4toFIG.8.

Referring toFIG.10,FIG.10is a schematic circuit layout diagram of the amplifier circuit3having the adjustable gain according to the third embodiment of the present disclosure. An amplifier201, attenuation circuits403and502ofFIG.10respectively correspond to the amplifier20, and the attenuation circuits40and50ofFIG.3. The amplifier201and the attenuation circuit403are described in the above embodiment, and are not reiterated herein.

In the present embodiment, the attenuation circuit502can include the same components as the attenuation circuit405shown inFIG.8, but the present disclosure is not limited thereto. In another embodiment, the attenuation circuit502can include the same components as one of the attenuation circuits401to404respectively shown inFIG.4toFIG.7. In addition, in another embodiment, the attenuation circuit403can be replaced with one of the attenuation circuits401,402,404and405respectively shown inFIG.4,FIG.5,FIG.7, andFIG.8.

As shown inFIG.10, the amplifier circuit3can further include the matching circuit60and capacitors BC1, BC2, and BC3. The matching circuit60is described in the above embodiment, and is not reiterated herein. The capacitor BC1is coupled between the input terminal11and the attenuation circuit502, the capacitor BC2is coupled between the attenuation circuit502and the output terminal12, and the capacitor BC3is coupled between the attenuation circuit502and the reference potential terminal13. The capacitor BC1can be used for blocking a direct current bias from the input terminal11, and the capacitors BC2and BC3can be used for blocking a direct current bias from the attenuation circuit502.

In the above embodiment, each of the switches SW40to SW73nand the transistors M1and M2can be a field effect transistor (FET) or other types of transistors. When the switches SW40to SW73nor the transistors M1and M2is the FET, the first terminal of the switches SW40to SW73nor the transistors M1and M2can be one of a drain terminal and a source terminal, the second terminal of the switches SW40to SW73nor the transistors M1and M2can be another one of the drain terminal and the source terminal, and the control terminal of the switches SW40to SW73nor the transistors M1and M2can be a gate terminal.

Beneficial Effects of the Embodiments

In conclusion, in the amplifier circuit having the adjustable gain provided by the present disclosure, the gain value range of the amplifier circuit can be expanded and the gain value of the amplifier circuit can be adjusted through the attenuation circuit. Moreover, since the attenuation circuit can be designed to have the roughly symmetrical circuit architecture, the arrangement of the attenuation circuit does not easily affect the matching of the output impedance of the amplifier of the amplifier circuit.