Clock recovery circuit, optical module, and clock recovery method

A VCO generates a clock signal. A phase and frequency detector compares phases and frequencies of the clock signal generated by the VCO and an input signal. A charge pump adjusts a control voltage of the VCO based on an output of the phase and frequency detector. An identical digit detector generates a first signal by delaying a rising timing of the input signal by a first time, generates a second signal by delaying a falling timing of the input signal by a second time, detects succession of identical digits in the input signal based on the first signal and the second signal, and stops adjustment of the control voltage by the charge pump when the identical digits succeed by a predetermined number of identical digits or more.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-200384, filed on Oct. 8, 2015, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a clock recovery circuit, an optical module, and a clock recovery method.

BACKGROUND

With recent improvement in signal transmission speed and a recent increase in signal transmission capacity between information processing devices in high-end servers or supercomputers, optical interconnection using a high-speed optical transmission technique in short-range or middle-range signal transmission between CPUs has been studied in order to break a limit of electrical signal transmission. In the optical interconnection, an optical module or the like that converts an electrical signal into an optical signal is employed and data is transmitted between a transmitting-side optical transmission device and a receiving-side optical transmission device using an optical signal via a transmission line such as an array optical fiber. Regarding a signal speed, there is a need for high-speed data communication of, for example, 25 Gb/s so as to cope with wide-band signal transmission between the information processing devices.

In order to satisfactorily transmit and receive digital signals, there is a need for determining each data bit at a correct timing in a receiving-side information processing device. Accordingly, the receiving-side information processing device determines data using timing information for determining a timing at which data is read. As a simple unit that acquires the timing information, there is a method of causing a transmitting-side information processing device to transmit a clock signal in parallel with a data signal.

On the other hand, in recent high-speed data communication such as optical interconnection, since it is difficult to combine a clock timing transmitted in parallel with data due to a transmission delay, transmission of a clock signal in parallel with a data signal is not performed, but a method of embedding clock information in a data signal and causing a receiving-side information processing device to recover a clock is often used. Regeneration of a clock is performed by a clock recovery circuit of the receiving-side information processing device.

A phase-locked loop (PLL) circuit or the like is used in the clock recovery circuit, and the phase-locked loop circuit includes a phase/frequency detector, a loop filter, and a voltage-controlled oscillator (VCO). A clock signal is recovered by adjusting a control voltage of a clock VCO through comparison with a phase of an internal clock signal at data edges which are a rising edge and a falling edge of a received data signal using the phase-locked loop circuit.

A technique of generating an edge pulse in which a rising edge and a falling edge of a reference pulse are delayed by a predetermined time in order to detect data edges of a data signal is known in the related art. In addition, a technique of detecting edges using a NOR circuit or a NAND circuit and an inverter circuit is known in the related art.Patent Document 1: Japanese Laid-open Patent Publication No. 57-210718Patent Document 2: Japanese Laid-open Utility Model Publication No. 61-131130Patent Document 3: Japanese Laid-open Patent Publication No. 06-125251

In a clock recovery circuit using the above-mentioned phase-locked loop circuit, when there is no data edge, phase comparison at that time is not performed and adjustment of a clock signal is not performed. Accordingly, when identical digits succeed as a data signal for a long time, a control voltage of a clock VCO varies and a phase shift, that is, a jitter, of a clock signal occurs. Accordingly, there is a possibility that data will not be determined at a correct timing and a bit error or the like will occur, thereby causing degradation in transmission quality.

Therefore, it is considered that the degradation in transmission quality is reduced by detecting succession of identical digits in an input data signal and stopping the phase-locked loop circuit during the succession of identical digits.

However, in the technique of adding a predetermined delay to an edge pulse or the technique using a NOR circuit or a NAND circuit and an inverter circuit, the succession of identical digits is not detected. Accordingly, it is difficult to reduce the degradation in transmission quality when identical digits succeed in a data signal.

SUMMARY

According to an aspect of an embodiment, a clock recovery circuit includes: a voltage-controlled oscillator that generates a clock signal; a phase and frequency detector that compares phases and frequencies of the clock signal generated by the voltage-controlled oscillator and an input signal; a voltage adjuster that adjusts a control voltage of the voltage-controlled oscillator based on an output of the phase and frequency detector; a first signal generator that generates a first signal by delaying a rising timing of the input signal by a first time; a second signal generator that generates a second signal by delaying a falling timing of the input signal by a second time; and a controller that detects succession of identical digits in the input signal based on the first signal and the second signal and stops adjustment of the control voltage by the voltage adjuster when identical digits succeed by a predetermined number of identical digits or more.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be explained with reference to accompanying drawings. The clock recovery circuit, the optical module, and the clock recovery method disclosed in the present application are not limited by the following embodiments.

[a] First Embodiment

FIG. 1is a diagram illustrating an example of a system configuration of an information system using an optical module. As illustrated inFIG. 1, an optical module14is used for communication between information processing devices1such as servers. The optical modules14of the information processing devices1are connected to each other using an optical communication cable such as an optical fiber.

A CPU11mounted on the information processing device1performs a computing process using a memory12, an HDD13, and the like. The CPU11communicates with another information processing device1via the optical module14. The optical module14performs communication, for example, using Ethernet (registered trademark).

Specifically, the CPU11supplies a data signal to be transmitted to another information processing device1to the optical module14. At this time, the CPU11embeds a clock signal in the data signal. Then, the optical module14converts the data signal received from the CPU11from an electrical signal to an optical signal. The optical module14outputs the data signal converted into the optical signal to the optical module14of another information processing device1.

When an optical signal is received from the optical module14of another information processing device1, the optical module14converts the received data signal into an electrical signal. The optical module14according to this embodiment converts the optical signal into the electrical signal and recovers a clock from the electrical data signal. Thereafter, the optical module14determines the received data signal using the recovered clock. The optical module14transmits the determined data signal to the CPU11.

While a server or the like is exemplified as the information processing device1, the information processing device1may be another device as long as it transmits and receives a data signal and may be, for example, a storage. The optical module14may receive a data signal from a unit other than the CPU11. The clock recovery circuit is not limited to the optical module, but may be a circuit of transmitting and receiving an electrical signal.

The optical module14of the information processing device1may be on any one of a data transmitting-side and a data receiving side. In the following description, it is assumed that one of the optical modules communicating with each other is a transmitting-side optical module and the other is a receiving-side optical module. That is, the optical module14practically has both functions of the transmitting-side optical module and the receiving-side optical module in the following description.

FIG. 2is a block diagram illustrating a transmitting-side optical module. A transmitting-side optical module20includes an input buffer21, a decision unit103, a driver23, and a light-emitting element24. The transmitting-side optical module20further includes a VCO105, a phase and frequency detector106, a charge pump107, a loop filter108, and an identical sign detector110. Here, for example, a circuit including the VCO105, the phase and frequency detector106, the charge pump107, the loop filter108, and the identical digit detector110corresponds to an example of the “clock recovery circuit.”

The input buffer21receives an input of a data signal from the CPU11. The input buffer21performs shaping of the received signal. Thereafter, the input buffer21outputs the data signal to the decision unit103. Here, the data signal output from the input buffer21includes noise or jitter due to signal transmission from the CPU11to the optical module14and is not a data signal having accurate information.

The decision unit103is constituted, for example, by a flip-flop (FF). The decision unit103receives an input of the data signal from the input buffer21. The decision unit103receives an input of a clock signal generated by the VCO105to be described later. The decision unit103identifies the received data signal. That is, the decision unit103determines the data signal at the timing indicated by the acquired clock signal and determines information of the data signal. The decision by the decision unit103may be referred to as retiming. The data signal has accurate data through decision by the decision unit103. The decision unit103outputs the data signal having information determined to the driver23.

The driver23receives an input of the data signal from the decision unit103. Then, the driver23controls the light-emitting element24depending on the acquired data signal.

The light-emitting element24is, for example, a vertical cavity surface emitting laser (VCSEL). The light-emitting element24outputs an optical signal corresponding to the data signal to a receiving-side optical module100via an optical fiber under the control of the driver23.

The VCO25is an oscillator of which an oscillation frequency varies depending on an input control voltage. The VCO25receives an input of a voltage from the loop filter108. The VCO25generates a clock signal by oscillating depending on the input voltage. The clock signal generated by the VCO25is output to the decision unit103and the phase and frequency detector107.

The phase and frequency detector26receives an input of the clock signal from the VCO25. The phase and frequency detector26acquires the data signal output from the input buffer21. The phase and frequency detector26compares frequencies and phases of the data signal and the clock signal. Thereafter, the phase and frequency detector26outputs the comparison result, that is, a signal proportional to an error between the data signal and the clock signal, to the charge pump27. Specifically, the phase and frequency detector26outputs a degree of adjustment of the voltage to be input to the VCO25, that is, information indicating how much the voltage is raised or lowered, depending on the error to the charge pump27.

The charge pump27receives an input of the degree of adjustment of the voltage to be input to the VCO25from the phase and frequency detector26. The charge pump27causes the loop filter28to perform charging and discharging of charges depending on the input degree of adjustment. The charge pump107corresponds to an example of the “voltage adjuster.”

The loop filter28performs charging and discharging of charges under the control of the charge pump27and removes noise. The loop filter28inputs a control voltage to the VCO25depending on an amount of charges held therein.

The identical digit detector110acquires the data signal output from the input buffer21. Then, the identical digit detector110determines whether data of identical digits succeed by a predetermined number in the data signal. When the data of identical digit succeed by a predetermined number, the identical digit detector110stops the operation of the charge pump107. Thereafter, when the sign of the data is changed, the identical digit detector110restarts the operation of the charge pump107.

The receiving-side optical module100will be described below with reference toFIG. 3.FIG. 3is a block diagram of the receiving-side optical module.

The receiving-side optical module100includes a light-receiving element101, a trans impedance amplifier (TIA)102, the decision unit103, an output buffer104, the VCO105, the phase and frequency detector106, the charge pump107, the loop filter108, and the identical digit detector110. Here, for example, a circuit including the VCO105, the phase and frequency detector106, the charge pump107, the loop filter108, and the identical digit detector110corresponds to an example of the “clock recovery circuit.”

The light-receiving element101is, for example, a photo diode (PD). The light-receiving element101receives the optical signal output from the transmitting-side optical module20via an optical fiber. Then, the light-receiving element101converts a data signal which is the received optical signal into a current. Then, the light-receiving element101outputs the data signal converted into the current to the TIA102.

The TIA102receives an input of the data signal converted into the current from the light-receiving element101. Then, the TIA102converts the data signal as the current in impedance, amplifies the data signal, and converts the data signal into a voltage. Then, the TIA102outputs the data signal converted into the voltage to the decision unit103.

The decision unit103is constituted, for example, by a FF. The decision unit103receives an input of the data signal from the TIA102. The decision unit103receives an input of a clock signal generated by the VCO105to be described later. The decision unit103identifies the received data signal. That is, the decision unit103determines the data signal at the timing indicated by the acquired clock signal and determines information of the data signal. The decision unit103outputs the data signal having information determined to the output buffer104.

The output buffer104receives an input of the data signal from the decision unit103. Then, the output buffer104adjusts the current which flows as the data signal and outputs the data signal as an electrical signal to the CPU11.

The VCO105is an oscillator of which an oscillation frequency varies depending on an input control voltage. The VCO105receives an input of a voltage from the loop filter108. The VCO105generates a clock signal by oscillating depending on the input voltage. The clock signal generated by the VCO105is output to the decision unit103and the phase and frequency detector106.

The phase and frequency detector106receives an input of the clock signal from the VCO105. The phase and frequency detector106acquires the data signal output from the TIA102. The phase and frequency detector106compares frequencies and phases of the data signal and the clock signal. Thereafter, the phase and frequency detector106outputs the comparison result, that is, a signal proportional to an error between the data signal and the clock signal, to the charge pump107. Specifically, the phase and frequency detector106outputs a degree of adjustment of the voltage to be input to the VCO105, that is, information indicating how much the voltage is raised or lowered, depending on the error to the charge pump107.

The charge pump107receives an input of the degree of adjustment of the voltage to be input to the VCO105from the phase and frequency detector106. The charge pump107causes the loop filter108to perform charging and discharging of charges depending on the input degree of adjustment. The charge pump107corresponds to an example of the “voltage adjuster.”

The loop filter108performs charging and discharging of charges under the control of the charge pump107and removes noise. The loop filter108inputs a control voltage to the VCO105depending on an amount of charges held therein.

The identical digit detector110acquires the data signal output from the TIA102. Then, the identical digit detector110determines whether data of identical digits succeed by a predetermined number in the data signal. When the data of identical digits succeed by a predetermined number, the identical digit detector110stops the operation of the charge pump107. Thereafter, when the sign of the data is changed, the identical digit detector110restarts the operation of the charge pump107. Details of the identical digit detector110will be described below by exemplifying the receiving-side optical module. The identical digit detecting operation is the same as in the transmitting-side optical module20or a clock recovery circuit of an electrical signal.

FIG. 4is a block diagram of the identical digit detector. As illustrated inFIG. 4, the identical digit detector110includes a rising delay signal generator111, a falling delay signal generator112, a buffer113, a buffer114, and an OR circuit115.

The rising delay signal generator111is a circuit that generates a rising delay signal having a waveform in which a rising timing of the data signal acquired from the TIA102is delayed by a predetermined time.FIG. 5is a circuit diagram illustrating an example of the rising delay signal generator. The rising delay signal generator111outputs the generated rising delay signal to the buffer113. The rising delay signal generator111corresponds to an example of the “first signal generator.” The rising delay signal corresponds to an example of the “first signal,” and the predetermined time which is the rising delay time of the waveform of the rising delay signal relevant to a rising of the data signal corresponds to an example of the “first time.”

The buffer113receives an input of the rising delay signal from the rising delay signal generator111. Then, the buffer113outputs the rising delay signal to the OR circuit115.

The falling delay signal generator112is a circuit that generates a falling delay signal having a waveform in which a falling timing of the data signal acquired from the TIA102is delayed by a predetermined time. The falling delay signal generator112outputs the generated falling delay signal to the buffer114. The falling delay signal generator112corresponds to an example of the “second signal generator.” The falling delay signal corresponds to an example of the “second signal,” and the predetermined time which is the falling delay time of the waveform of the falling delay signal relevant to a falling of the data signal corresponds to an example of the “second time.”

The buffer114receives an input of the falling delay signal from the falling delay signal generator112. Thereafter, the buffer114inverts the falling delay signal. Then, the buffer114outputs the inverted falling delay signal to the OR circuit115.

The OR circuit115receives an input of the rising delay signal from the buffer113. The OR circuit115receives an input of the inverted falling delay signal from the buffer114. Then, the OR circuit115calculates a logical OR of the rising delay signal and the inverted falling delay signal and generates an identical digit detection signal. Then, the OR circuit115outputs the identical digit detection signal to the charge pump107. When the value of the identical digit detection signal output from the OR circuit115is high, the charge pump107stops its operation. That is, when it is determined that the identical digit succeed by a predetermined number, the OR circuit115sets the identical digit detection signal to be high to stop the operation of the charge pump107. The OR circuit115corresponds to an example of the “controller.”

Generation of the identical digit detection signal will be described below in brief with reference toFIG. 5.FIG. 5is a diagram illustrating the generation of the identical digit detection signal. InFIG. 5, the vertical axis represents a voltage and the horizontal axis represents the lapse of time.

Here, an example in which a signal having a waveform indicated by graph301is the data signal input from the TIA102will be described.

Graph303indicates a rising delay signal which is generated from the signal indicated by graph301by the rising delay signal generator111. The rising delay signal generator111delays the rising of the signal indicated by graph301by a predetermined time. In the signal of graph301, a waveform in which the falling occurs within the delay time from occurrence of the rising is crushed, and the rising timing of a waveform in which the falling occurs after the delay time elapses is delayed by the delay time. Accordingly, the rising delay signal generator111generates the rising delay signal indicated by graph303.

Graph305indicates a falling delay signal which is generated from the signal indicated by graph301by the falling delay signal generator112. The falling delay signal generator112delays the falling of the signal indicated by graph301by a predetermined time. In the signal of graph301, a waveform in which the rising occurs within the delay time from occurrence of the falling is crushed, and the rising timing of a waveform in which the rising occurs after the delay time elapses is delayed by the delay time. Accordingly, the falling delay signal generator112generates the falling delay signal indicated by graph305.

Graph306indicates a signal which is acquired by causing the buffer114to invert the falling delay signal indicated by graph305.

The OR circuit115receives an input of the rising delay signal indicated by graph303and an input of the inverted falling delay signal indicated by graph306. Then, the OR circuit115calculates the logical OR of the signal indicated by graph303and the signal indicated by graph306and generates an identical digit detection signal indicated by graph307.

When a high signal is input from the identical digit detector110, the charge pump107stops its operation. That is, in a high part of the identical digit detection signal indicated by graph307, the identical digit detector110stops the operation of the charge pump107. In other words, the identical digit detector110determines that identical digits succeed by a predetermined number in periods T11, T12, and T13, and stops the operation of the charge pump107in the periods.

Details of the operation of the rising delay signal generator111as an example of the “first signal generator” will be described below with reference toFIG. 6. For example, as illustrated inFIG. 6, the rising delay signal generator111includes a current source211, a transistor212, a capacitor213, and a buffer214. The capacitor213corresponds to an example of the “first capacitor.”

The current source211adjusts a current output from a voltage source to a predetermined value. The current source211is, for example, a current mirror. A degree of adjustment of a current in the current source211is variable.

The emitter of the transistor212is connected to the current source211and the collector is connected to the ground (GND). The data signal output from the TIA102is input to the base of the transistor212. In the drawing, a configuration employing a pnp transistor is illustrated, but the same operation is obtained using even a p-type metal oxide semiconductor (MOS) transistor.

A path extending from the emitter of the transistor212is connected to the capacitor213and the buffer214. The capacitor213is disposed between the emitter of the transistor212and the GND.

When the data signal is low, the transistor212is turned on. In this case, charges accumulated in the capacitor213flow as indicated by path A2and discharging of the capacitor213is carried out at a high speed.

When the data signal is high, the transistor212is turned off. In this case, a predetermined current flows by the current source211as indicated by path A1. Accordingly, the capacitor213is charged at a low speed. The buffer214identifies the voltage of the capacitor213using a predetermined threshold value and outputs the decision result as a rising delay signal.

Here, the value of the predetermined current which is adjusted by the current source211is determined to take time for charging of the capacitor213using path A1. That is, the charging of the capacitor213using path A1is slow but the discharging of the capacitor213using path A2is fast. Since the discharging of the capacitor213is fast, the falling is performed in an instant. Since the charging is slow, time is taken until the data signal is high and the rising timing is shifted back.

FIG. 7is a diagram illustrating generation of a rising delay signal. InFIG. 7, the vertical axis represents a voltage and the horizontal axis represents the lapse of time.

Here, it is assumed that a signal indicated by the same graph301as inFIG. 5is input from the TIA102. When a data signal having the waveform of graph301is input to the transistor212, the transistor212is turned off at the rising of graph301and then the voltage relevant to the buffer214slowly rises. That is, the signal input to the buffer214slowly rises. The signal input to the buffer214is indicated by graph302.

Here, a threshold value321of graph302is a threshold value which is used to perform decision by the buffer214. That is, the buffer214determines to be low when the voltage of the input signal is less than the threshold value321, and determines to be high when the voltage of the input signal is equal to or greater than the threshold value321. The result of the rising delay signal which is generated by decision by the buffer214using the threshold value321is indicated by graph303. For example, since discharging is performed before the first rising of graph301becomes equal to or greater than the threshold value321, the rising edge of the rising delay signal indicated by graph303is crushed as indicated by arrow331. Since the falling occurs after the rising becomes equal to or greater than the threshold value321, the rising corresponding to the second rising of graph301in the rising delay signal indicated by graph303is shifted as indicated by arrow332. Similarly, the rising edge of the rising delay signal is crushed or shifted as indicated by another arrow. As a result, the rising delay signal indicated by graph303rises at only time T1and time T2.

InFIG. 7, the rising timing is delayed by two bits, but the degree of delay of the rising timing can be adjusted by a current flowing from the current source211. By adjusting the current of the current source211, for example, it is possible to further delay the rising timing and to increase the number of rising edges serving as a reference when it is determined that a high part succeeds. On the other hand, for example, when the rising timing is further advanced, it is possible to reduce the number of rising edges serving as a reference when it is determined that a high part succeeds. The current source211corresponds to an example of the “first current source.” The current flowing from the current source211corresponds to an example of the “first predetermined value.”

Details of the operation of the falling delay signal generator112as an example of the “second signal generator” will be described below with reference toFIG. 8.FIG. 8is a circuit diagram illustrating an example of the falling delay signal generator. For example, as illustrated inFIG. 8, the falling delay signal generator112includes a transistor221, a current source222, a capacitor223, and a buffer224. The capacitor223corresponds to an example of the “second capacitor.”

The collector of the transistor221is connected to a voltage source and the emitter thereof is connected to the current source222and the GND. The data signal output from the TIA102is input to the base of the transistor221. In the drawing, a configuration employing an npn transistor is illustrated, but the same operation is obtained using even an n-type MOS transistor.

A path extending from the emitter of the transistor221is connected to the capacitor223and the buffer224. The capacitor223is disposed between the emitter of the transistor221and the GND.

The current source222adjusts a current discharged from the capacitor223to a predetermined value. The current source222is, for example, a current mirror. A degree of adjustment of a current in the current source222is variable.

When the data signal is high, the transistor221is turned on. In this case, the current output from the voltage source flows as indicated by path A3. Accordingly, the capacitor223is charged at a high speed. The buffer224identifies the voltage of the capacitor223using a predetermined threshold value and outputs the decision result as a falling delay signal.

When the data signal is low, the transistor221is turned off. In this case, charges accumulated in the capacitor223flow as indicated by path A4and discharging of the capacitor223is carried out at a low speed.

Here, the value of the predetermined current which is adjusted by the current source222is determined to take time for discharging of the capacitor223using path A4. That is, the charging of the capacitor223using path A4is slow but the charging of the capacitor223using path A3is fast. Since the charging of the capacitor223is fast, the rising of the signal input to the buffer224is performed in an instant. Since the discharging of the capacitor223is slow, time is taken until the buffer224determines that the data signal is low, and the falling timing is shifted back.

FIG. 9is a diagram illustrating generation of a falling delay signal. InFIG. 9, the vertical axis represents a voltage and the horizontal axis represents the lapse of time.

Here, it is assumed that a signal indicated by the same graph301as inFIG. 5is input from the TIA102. When a data signal having the waveform of graph301is input to the transistor221, the transistor221is turned on at the rising of graph301. The transistor221is turned off at the falling timing of graph301. Thereafter, the voltage relevant to the buffer224slowly falls. That is, the signal input to the buffer224slowly falls. The signal input to the buffer224is indicated by graph304.

Here, a threshold value341of graph304is a threshold value which is used to perform decision by the buffer224. That is, the buffer224determines to be low when the voltage of the input signal is less than the threshold value341, and determines to be high when the voltage of the input signal is equal to or greater than the threshold value341. The result of the falling delay signal which is generated by decision by the buffer224using the threshold value341is indicated by graph305. For example, since charging is started before the first falling of graph301becomes less than the threshold value341, the falling edge of the falling delay signal indicated by graph305is crushed as indicated by arrow351. Since the falling occurs after the falling becomes less than the threshold value341, the falling corresponding to the fourth falling of graph301in the falling delay signal indicated by graph305is shifted as indicated by arrow352. Similarly, the falling edge of the falling delay signal is crushed or shifted as indicated by another arrow. As a result, the falling delay signal indicated by graph305falls at only time T3.

InFIG. 9, the falling timing is delayed by two bits, but the degree of delay of the falling timing can be adjusted by a current flowing from the current source222. By adjusting the current of the current source222, for example, it is possible to further delay the falling timing and to increase the number of falling edges serving as a reference when it is determined that a low part succeeds. On the other hand, for example, when the falling timing is further advanced, it is possible to reduce the number of rising edges serving as a reference when it is determined that a low part succeeds. The current source222corresponds to an example of the “second current source.” The current flowing from the current source222corresponds to an example of the “second predetermined value.”

As described above, it is possible to change a degree of delay of the rising by changing the current flowing from the current source211, and it is possible to change a degree of delay of the falling by changing the current flowing from the current source222. That is, by changing the degrees of delay of the rising and the falling, it is possible to adjust the number of identical digits serving as a reference for detecting succession of identical digits. Accordingly, it is possible to adjust the period in which the identical digit detection signal generated by the identical digit detector110is in the high state. That is, the period in which the identical digit detection signal is in the high state is extended when the number of identical digit serving as a determination reference decreases, and the period in which the identical digit detection signal is in the high state is shortened when the number of identical digits serving as a determination reference increases.

When the period in which the identical digit detection signal is in the high state is extended, the operation of the charge pump107is not stopped until multiple identical digits succeed. In this case, the receiving-side optical module100can generate a clock signal to accurately correspond to the sign change, but coping performance with a phase shift of the clock signal due to succession of identical digits degrades. On the other hand, when the period in which the identical digit detection signal is in the high state is shortened, the operation of the charge pump107is stopped due to slight succession of identical digit. In this case, the receiving-side optical module100is improved in coping performance with the phase shift of the clock signal due to the succession of identical digits, but degrades in coping precision with the sign change. Accordingly, it is preferable that the currents which are adjusted by the current sources211and222be determined by balance of the coping performance with the phase shift due to succession of identical digits with the coping accuracy with the sign change.

A flow of a clock recovery process in the receiving-side optical module100will be described below with reference toFIG. 10.FIG. 10is a flowchart illustrating the clock recovery process in the clock repeat circuit. The flow of the clock recovery process is the same as in the transmitting-side optical module or an electrical signal clock recovery circuit.

The VCO105oscillates on the basis of a voltage input from the loop filter108and generates a clock signal (step S1).

Then, the charge pump107adjusts the voltage to be input to the VCO105on the basis of the signal input from the phase and frequency detector106(step S2).

Then, the rising delay signal generator111of the identical digit detector110generates a rising delay signal (step S3). The falling delay signal generator112of the identical digit detector110generates a falling delay signal (step S4).

Thereafter, the OR circuit115of the identical digit detector110receives an input of the rising delay signal and an input of the falling delay signal. Then, the OR circuit115generates an identical digit detection signal (step S5).

The identical digit detector110determines whether identical digits succeed on the basis of the sign of the generated identical digit detection signal (step S6). When identical digits succeed (YES in step S6), the identical digit detector110stops the operation of the charge pump107and stops the adjustment of a voltage for the VCO105(step S7).

On the other hand, when identical digits do not succeed (NO in step S6), the identical digit detector110activates the charge pump107and activates the adjustment of a voltage for the VCO105(step S8).

Then, the phase and frequency detector106acquires a data signal output from the TIA102. The phase and frequency detector106acquires a clock signal generated by the VCO105. Then, the phase and frequency detector106determines whether the frequency of the data signal matches the frequency of the clock signal (step S9).

When the frequencies do not match each other (NO in step S9), the process flow is returned to step S1. On the other hand, when the frequencies match each other (YES in step S9), the phase and frequency detector106determines whether the phase of the data signal and the phase of the clock signal match each other (step S10).

When the phases do not match each other (NO in step S10), the process flow is returned to step S1. On the other hand, when the phases match each other (YES in step S10), the clock recovery circuit ends this clock adjusting operation. The process flow illustrated inFIG. 10represents the first clock adjusting operation and the clock recovery circuit actually repeats the process flow illustrated inFIG. 10.

In the flow illustrated inFIG. 10, for the purpose of convenience of description, the processes of determining succession of identical digits illustrated in steps S3to S6is performed before the phases and the frequencies are compared, but these processes may be actually performed in parallel. Here, the succession of identical digits is determined by the identical digit detector110and the operation of the charge pump107is stopped, but the identical digit detector110may be configured to stop the operation by simply outputting the generated identical digit detection signal to the charge pump107.

A flow of a signal receiving process in the receiving-side optical module100will be described below with reference toFIG. 11.FIG. 11is a flowchart illustrating a signal receiving process in an optical module.

The light-receiving element101receives a data signal which is an optical signal from the transmitting-side optical module20via an optical fiber (step S11).

Then, the light-receiving element101converts the received data signal into an electrical signal (step S12). Then, the light-receiving element101outputs the data signal converted into the electrical signal to the TIA102.

The TIA102converts the received data signal into a voltage and amplifies the converted data signal (step S13). Then, the TIA102outputs the data signal to the decision unit103.

The VCO105oscillates depending on a voltage input from the loop filter108and recovers a clock signal (step S14). Here, the VCO105receives the voltage, which is controlled by the clock recovery process illustrated inFIG. 10, from the loop filter108.

The decision unit103receives an input of the data signal from the TIA102. The decision unit103receives an input of the clock signal generated by the VCO105. The decision unit103identifies the data signal using the clock signal (step S15). Then, the decision unit103outputs the data signal of which information is determined by the decision to the output buffer104.

The output buffer104receives an input of the data signal of which information is determined by the decision from the decision unit103. Then, the output buffer104outputs an electrical signal which is the data signal having information determined to the CPU11(step S16).

A flow of a signal transmitting process in the transmitting-side optical module20will be described below with reference toFIG. 12.FIG. 12is a flowchart illustrating a signal transmitting process in an optical module.

The input buffer21receives a data signal which is an electrical signal from the CPU11(step S21). The input buffer21outputs the received data signal to the decision unit103, the phase and frequency detector106, and the identical digit detector110.

The VCO105oscillates depending on a voltage input from the loop filter108and recovers a clock signal (step S22).

The decision unit103receives an input of the data signal from the input buffer21. The decision unit103receives an input of the recovered clock signal from the VCO105. Then, the decision unit103identifies the data signal using the received recovered clock signal (step S23). Thereafter, the decision unit103outputs the identified data signal to the driver23(step S24).

The driver23receives an input of the identified data signal from the decision unit103. The driver23amplified the received data signal (step S25). Thereafter, the driver23outputs the data signal to the light-emitting element24.

The light-emitting element24receives an input of the data signal from the driver23. Then, the light-emitting element24converts the data signal as an electrical signal into an optical signal (step S26). Then, the light-emitting element24transmits the data signal converted into the optical signal to the receiving-side optical module100.

FIG. 13is a block diagram when the falling delay circuit is used as the “first signal generator” and the “second signal generator.” Here, the falling delay circuit is a circuit illustrated inFIG. 8. Here, the functions of the rising delay signal generator111and the buffer113are realized by the buffer501, the falling delay signal generator112, and the buffer502.

FIG. 14is a diagram illustrating a simulation result of an identical digit detection signal in the clock recovery circuit when the identical digit detector illustrated inFIG. 13is used. In graphs401to404ofFIG. 14, the vertical axis represents a voltage and the horizontal axis represents a time.

Graph401indicates a waveform of a data signal input to the identical digit detector110. In the simulation illustrated inFIG. 14, it is assumed that a signal having a waveform in which a time in which an identical digit succeeds gradually increases is input to the receiving-side optical module100as indicated by graph401.

In this configuration, the first signal in which the rising timing is delayed by the first time and the second signal in which the falling timing is delayed by the second time are generated using the falling delay signal generator112. That is, by inputting the signal indicated by graph401to the falling delay signal generator112, the falling delay signal can be acquired. By inverting the signal indicated by graph401, the falling and the rising are inverted. Therefore, by inputting the signal which is obtained by inverting the signal indicated by graph401to the falling delay signal generator112, a signal which is obtained by inverting the rising delay signal which is generated when graph401is input to the rising delay signal generator111can be acquired.

Graph402is a graph indicating the signal in which the rising delay signal is inverted and a falling delay signal. In graph402, the graph indicated by a dotted line indicates a signal in which the rising delay signal is inverted. In graph402, the graph indicated by a solid line is the falling delay signal. As indicated by graph402, the signal in which the rising delay signal is inverted gradually falls in voltage in a part corresponding to the rising of graph401. The falling delay signal gradually falls in voltage in a part corresponding to the falling of graph401.

Graph403is a graph indicating the falling delay signal and the signal in which the rising delay signal of graph402is inverted. That is, graph403, the graph indicated by a dotted line indicates the rising delay signal. In graph403, the graph indicated by a solid line is a graph which is obtained by inverting the falling delay signal.

Two signals indicated by graph403are input to the OR circuit115of the identical digit detector110. The identical digit detection signal output from the OR circuit115is the signal indicated by graph404. A part in which the signal indicated by graph404is in the high state represents that an identical digit succeeds. Here, it can be seen that graph404is in the high state in the part corresponding to the signal in which multiple identical digits succeed in graph401. That is, it can be seen that the identical digit detector110according to this embodiment accurately detects succession of an identical digit.

FIG. 15is a diagram illustrating a simulation result of an identical digit detection signal when the delay time is changed. In graphs411and412ofFIG. 15, the vertical axis represents a voltage and the horizontal axis represents a time. In graphs413and414, the vertical axis represents a current and the horizontal axis represents a time.

Graph411is the same signal as graph401inFIG. 14and indicates a waveform of a data signal input to the identical digit detector110.

Waveforms in graph412indicate the identical digit detection signals when the delay time is changed by adjusting currents flowing from the current sources211and222. As indicated by graph412, since the slope of the rising is changed in the waveforms, it can be seen that the delay time is changed.

Graph413is a graph indicating the operation of the charge pump107when the charge pump107in which a current of 20 (μA) is controlled using signals corresponding to the waveforms in graph412. In graph413, when the current is 0 (A), the operation of the charge pump107is stopped. For example, it can be seen that the charge pump107is stopped in the part indicated by area431.

Graph414is a graph indicating the operation of the charge pump107when the charge pump107in which a current of 25 (μA) is controlled using the signals corresponding to the waveforms in graph412. In graph414, when the current is 0 (A), the operation of the charge pump107is stopped. For example, it can be seen that the charge pump107is stopped in the part indicated by area441.

In any of graphs413and414, it can be seen that the shorter the delay time becomes, the longer the time in which the charge pump107is stopped becomes. In a part having small succession of identical digits in graph401, it can be seen that the charge pump107performs its normal operation in any of graphs413and414.

FIG. 16is a block diagram when the rising delay circuit is used as the “first signal generator” and the “second signal generator.” Here, the rising delay circuit is a circuit illustrated inFIG. 6. Here, the functions of the falling delay signal generator112and the buffer114are realized by the buffer511, the rising delay signal generator111, and the buffer512.

FIG. 17is a diagram illustrating a simulation result of an identical digit detection signal in the clock recovery circuit when the rising delay signal generator is used. That is, the simulation is performed using a falling delay circuit which is the falling delay signal generator112inFIGS. 14 and 15, but the simulation is performed using a rising delay circuit which is the rising delay signal generator111inFIG. 17.

Graph421indicates a waveform of a data signal input to the identical digit detector110. Graph422indicates the rising delay signal which is generated by the rising delay signal generator111using a signal having a waveform indicated by graph421and a signal in which the falling delay signal is inverted. Here, the rising delay signal is indicated by a dotted line and the signal in which the falling delay signal is inverted is indicated a solid line.

In this case, similarly to the falling delay signal generator112, signals in which the rising and the falling are appropriately delayed are generated. That is, in this simulation, similarly to a case in which the falling delay signal generator112is used, it can be seen that an appropriate identical digit detection signal is generated.

As described above, the clock recovery circuit according to this embodiment detects that an identical digit of the data signal succeeds and stops the operation of the charge pump. Accordingly, it is possible to suppress occurrence of a phase shift of a clock signal due to succession of identical digits and to reduce degradation in transmission quality such as a bit error.

A method of detecting the succession of identical digits using edge detection can be considered, but in case of high-speed data communication such as optical interconnection, a pulse becomes finer than 1 bit, a response to identical digit detection is not immediate, and an increase in speed is difficult. On the other hand, since the clock recovery circuits according to the above-mentioned embodiments detect succession of identical digits without using the edge detection, it is possible to implement an increase in detection speed. Since the rising delay time and the falling delay time are variable, it is possible to adjust the length of the succession of identical digits to be detected.

According to one aspect of the clock recovery circuit, the optical module, and the clock recovery method disclosed in the present application, it is possible to reduce degradation in transmission quality in data communication.