Germanium-based sensor with junction-gate field effect transistor and method of fabricating thereof

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

BACKGROUND

The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process, such that realizing continued advances in ICs calls for similar advances in semiconductor manufacturing processes and technology.

As one example, semiconductor sensors are widely used for a variety of applications to measure physical, chemical, biological, and/or environmental parameters. Some specific types of semiconductor sensors include gas sensors, pressure sensors, temperature sensors, and optical image sensors, among others. For optical image sensors, dark current is a major concern for performance and reliability. Dark current, which is current that flows in the absence of light, can more generally be described as leakage current present in an optical image sensor. In at least some cases, poor quality of interfaces between various semiconductor layers used in optical image sensors and/or poor quality of surfaces of the various semiconductor layers may result in significant dark current. Another major concern for performance and/or reliability of optical image sensors is optical fill factor, which generally indicates a ratio of a light sensitive area of a pixel (e.g., a photodiode area) ratio to a total area of the pixel. Although existing optical image sensors and methods for fabricating such have been generally adequate for their intended purpose, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

The present disclosure relates generally to photosensitive devices, and more particularly to, germanium-based photosensitive devices and methods of fabrication thereof.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of description of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.5 nm to 5.5 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−10% by one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure provides germanium-based photosensitive devices and methods of fabrication thereof. The disclosed germanium-based photosensitive devices can reduce leakage current and/or dark current from germanium photodiodes, improve optical fill factor, improve conversion gain, and/or reduce noise. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor. The disclosed germanium-based photosensitive devices can be implemented in indirect time-of-flight (iTOF) applications. For example, the exemplary germanium-based sensors can be a TOF sensor used in TOF applications. Details of embodiments of the present disclosure are described hereafter.

FIGS.1A-1Jare diagrammatic cross-sectional views of a photosensitive device100, in portion or entirety, at various fabrication stages according to various aspects of the present disclosure.FIGS.1A-1Jhave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in photosensitive device100, and some of the features described can be replaced, modified, or eliminated in other embodiments of photosensitive device100.

Turning toFIG.1A, fabrication begins with forming a silicon cavity in a silicon substrate in a device region of a photosensitive device. For example, photosensitive device100has a device region102A and a device region102B and fabricating can begins with receiving a silicon substrate (wafer)105, forming a patterned oxide layer110over silicon substrate105, and forming cavities115(also referred to as trenches or recesses) in silicon substrate105in device region102A and device region102B using patterned oxide layer110as an etch mask. In some embodiments, patterned oxide layer110is formed by depositing an oxide layer over silicon substrate105, performing a lithography process to form a patterned resist layer over the oxide layer, and performing an etching process to transfer a pattern formed in the patterned resist layer to the oxide layer, thereby forming patterned oxide layer110. Patterned oxide layer110has an oxide layer portion110A, an oxide layer portion110B, and an oxide layer portion110C, where an opening112A that exposes silicon substrate105is formed by oxide layer portion110A and oxide layer portion110B and an opening112B that exposes silicon substrate105is formed by oxide layer portion110B and oxide layer portion110C. Patterned oxide layer110has a thickness t1. In some embodiments, thickness t1is about 50 nm to about 90 nm. The lithography process can include forming a resist layer on the oxide layer (for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The etching process uses the patterned resist layer as an etch mask to remove exposed portions of the oxide layer, thereby forming opening112A and opening112B that extend through the oxide layer and expose silicon substrate105. The etching process can include a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. After the etching process, the patterned resist layer can be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is removed, completely or partially, during etching of the oxide layer and/or during etching of silicon substrate105. In some embodiments, the exposure process can implement maskless lithography, electron-beam writing, and/or ion-beam writing.

An etching process is then performed using patterned oxide layer110as an etch mask to form cavities115in silicon substrate105. For example, portions of silicon substrate105exposed by opening112A and opening112B of patterned oxide layer110are removed by the etching process, thereby forming cavities115having bottoms and sidewalls formed by silicon substrate105. Cavities115have a depth D and a width W. In some embodiments, depth D is about 900 nm to about 1,500 nm. In some embodiments, width W is about 2,000 nm to about 10,000 nm. In some embodiments, the etching process is configured to selectively remove silicon substrate105with respect to patterned oxide layer110. In other words, the etching process substantially removes silicon substrate105but does not remove, or does not substantially remove, patterned oxide layer110. For example, an etchant is selected for the etch process that etches silicon (i.e., silicon substrate105) at a higher rate than silicon oxide (i.e., patterned oxide layer110) (i.e., the etchant has a high etch selectivity with respect to silicon). The etching process is a dry etching process, a wet etching process, other suitable etching process, or combinations thereof.

Turning toFIG.1B, a doped silicon layer is formed in and partially fill the silicon cavities. For example, doped silicon layers120are formed in and partially fill cavities115. Doped silicon layers120include n-type dopant (e.g., phosphorus, arsenic, other n-type dopant, or combinations thereof), p-type dopant (e.g., boron, indium, other p-type dopant, or combinations thereof), or combinations thereof. A dopant concentration of doped silicon layers120is greater than a dopant concentration of silicon substrate105. In some embodiments, doped silicon layers120have a dopant concentration of about 5×1016atoms/cm3(cm−3) to about 5×1018cm−3. In some embodiments, silicon substrate105has a dopant concentration that is less than about 1×1015cm−3. In some embodiments, doped silicon layers120include n-type dopant, such as phosphorous, and can be referred to as n-doped silicon layers (e.g., Si:P layers or Si:C:P layers). In some embodiments, doped silicon layers120include p-type dopant, such as boron, and can be referred to as p-doped silicon layers (e.g., Si:B layers). Doped silicon layers120are disposed along and covers bottoms and sidewalls of cavities115. A thickness t2of doped silicon layers120along bottoms of cavities115is less than depth D of cavities115, and a total thickness of doped silicon layers120along sidewalls of cavities115(i.e., a sum of a thickness t3along a first sidewall of a respective silicon cavity115and a thickness t4along a second sidewall of a respective silicon cavity) is less than width W of cavities115. In some embodiments, thickness t2, thickness t3, and thickness t4are substantially the same, such that doped silicon layers120are conformal layers (i.e., a layer having a substantially uniform thickness over various surfaces). In some embodiments, thickness t2is different than thickness t3and/or thickness t4. In some embodiments, thickness t3is substantially the same as thickness t4. In some embodiments, thickness t3is different than thickness t4. In some embodiments, thickness t2, thickness t3, and/or thickness t4is about 10 nm to about 100 nm. In the depicted embodiment, doped silicon layers120are substantially u-shaped. Doped silicon layers120can have different shapes depending on a profile of cavities115.

In some embodiments, doped silicon layers120are formed by a deposition process that selectively grows silicon on silicon substrate105without growing silicon on patterned oxide layer110. For example, doped silicon layers120are formed by epitaxially growing silicon from silicon substrate105. An epitaxy process for forming doped silicon layers120can implement chemical vapor deposition (CVD) deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LPCVD), and/or plasma enhanced CVD (PECVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxy process can use gaseous and/or liquid precursors, which include a silicon-containing precursor (for example, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (DCS) (Si2H2Cl2), other suitable silicon-containing precursor, or combinations thereof) and a carrier precursor (for example, a hydrogen precursor (e.g., H2), an argon precursor (e.g., Ar), a helium precursor (e.g., He), a nitrogen precursor (e.g., N2), a xenon precursor, other suitable inert precursor, or combinations thereof). In the depicted embodiment, the epitaxy process further uses a dopant precursor, such as phosphine (PH3), arsine (AsH3), diborane (B2H6), other suitable dopant-containing precursor, or combinations thereof. Epitaxially grown silicon is thus doped during deposition (i.e., in-situ doped). In some embodiments, epitaxially grown silicon is doped after deposition, for example, by an ion implantation process and/or a diffusion process. In some embodiments, a cleaning process and/or a surface treatment process (collectively referred to as a cleaning process) is performed before forming doped silicon layers120to remove defects from silicon substrate105and/or patterned oxide layer110, such as any native oxide, contaminates, and/or other defects on silicon substrate105and/or patterned oxide layer110. In some embodiments, the cleaning process is a baking process performed in an etchant-comprising ambient, where defects are removed (etched) from silicon substrate105and/or patterned oxide layer110during the baking process. For example, a chlorine-based baking process, such as an HCl baking process, is performed that can remove (clean) surface nucleation sites on patterned oxide layer110.

Turing toFIG.1C, a germanium layer is formed in and fills a remainder of the silicon cavity. For example, germanium layers130are formed in and fill remainders of cavities115. Germanium layers130each have a first portion wrapped by a respective doped silicon layer120and a second portion disposed above doped silicon layer120and between respective oxide layer portions of patterned oxide layer110. For example, doped silicon layers120are disposed along bottoms and sidewalls of the first portions of germanium layers130, while the second portions of germanium layers130cover top surfaces of sidewall portions of doped silicon layers120and contact oxide layer portion110A, oxide layer portion110B, and/or oxide layer portion110C. The first portion has a thickness t5that is less than depth D (e.g., thickness t5=depth D−thickness t2) and a width that is less than width W (e.g., first portion width=width W−(thickness t3+thickness t4)), and the second portion has a thickness t6and a width that is about the same as width W. In some embodiments, thickness t5is about 900 nm to about 1,500 nm. Thickness t6is less than thickness t1of patterned oxide layer110, such that germanium layers130partially fill opening112A and opening112B of patterned oxide layer110and a distance d1is between top surfaces of germanium layers130and a top surface of patterned oxide layer110. In some embodiments, thickness t6is about 0 nm to about 10 nm. In some embodiments, distance d1is about 0 nm to about 10 nm. In the depicted embodiment, germanium layers130are pure germanium layers. In some embodiments, germanium layers130are undoped (or unintentionally doped (UID)) (i.e., germanium layers130are substantially free of dopant). In some embodiments, germanium layers130having a dopant concentration that is considered undoped. In some embodiments, germanium layers130are doped with n-type dopant (e.g., phosphorous), p-type dopant (e.g., boron), or combinations thereof.

In some embodiments, germanium layers130are formed by a deposition process that selectively grows germanium on doped silicon layers120without growing germanium on patterned oxide layer110. For example, germanium layers130are formed by epitaxially growing germanium from doped silicon layers120. An epitaxy process for forming germanium layers130can implement CVD deposition techniques (for example, VPE, UHV-CVD, LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process can use gaseous and/or liquid precursors. For example, the epitaxy process uses a germanium-containing precursor (for example, germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), germanium dichloride (GeCl2), other suitable germanium-containing precursor, or combinations thereof) and a carrier precursor (for example, a hydrogen precursor (e.g., H2), an argon precursor (e.g., Ar), a helium precursor (e.g., He), a nitrogen precursor (e.g., N2), a xenon precursor, other suitable inert precursor, or combinations thereof). The epitaxy process is performed until epitaxially grown germanium extends between respective oxide layer portions of patterned oxide layer110and covers top surfaces of sidewall portions of doped silicon layers120. In some embodiments, the epitaxy process is performed until epitaxially grown germanium fills opening112A and opening112B and, in some embodiments, extends a distance above the top surface of patterned oxide layer110. A planarization process, such as a chemical mechanical polishing (CMP), can be performed to remove portions of epitaxially grown germanium extending above and/or over the top surface of patterned oxide layer110, where patterned oxide layer110can function as a planarization stop (i.e., the planarization process stops upon reaching patterned oxide layer110). In some embodiments, the top surface of patterned oxide layer110and top surfaces of germanium layers130are substantially planar after the planarization process. An etch back process can be performed on germanium layers130to recess the top surfaces of germanium layers130distance d1from the top surface of patterned oxide layer110. In some embodiments, the planarization process recesses the epitaxially grown germanium relative to the top surface of patterned oxide layer110, such that the top surfaces of germanium layers130are distance d1below the top surface of patterned oxide layer110after the planarization process. In such embodiments, an additional etch back process may be unnecessary. In embodiments where germanium layers130are doped, the epitaxy process can use a dopant precursor, such as those described herein, to in-situ dope the epitaxially grown germanium. In some embodiments, the epitaxially grown germanium is doped after deposition, for example, by an ion implantation process and/or a diffusion process. In some embodiments, a cleaning process is performed before forming germanium layers130to remove defects from doped silicon layers120and/or patterned oxide layer110, such as any native oxide, contaminates, and/or other defects on doped silicon layers120and/or patterned oxide layer110. In some embodiments, the cleaning process is a baking process, such as described herein.

Turning toFIG.1D, an undoped (or UID) cap layer is formed over the germanium layer. For example, cap layers135are formed over germanium layers130. In the depicted embodiment, cap layers135are undoped silicon layers (i.e., silicon layers that are substantially free of dopant, such as n-type dopant (e.g., phosphorous) or p-type dopant (e.g., boron)). In some embodiments, cap layers135having a dopant concentration that is considered undoped. Cap layers135fill remainders of openings in patterned oxide layer110, such as opening112A and opening112B. In the depicted embodiment, a first one of cap layers135is disposed between oxide layer portion110A and oxide layer portion110B, and a second one of cap layers135is disposed between oxide layer portion110B and oxide layer portion110C. Cap layers135have a thickness t7, which is less than thickness t1of patterned oxide layer110, and a width that is about the same as width W. In some embodiments, thickness t7is about 10 nm to about 50 nm. In some embodiments, thickness t7is substantially equal to distance d1. In some embodiments, cap layers135are formed by a deposition process that selectively grows silicon on germanium layers130without growing silicon on patterned oxide layer110. For example, cap layers135are formed by epitaxially growing silicon from germanium layers130. An epitaxy process for forming cap layers135can implement CVD deposition techniques (for example, VPE, UHV-CVD, LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process can use gaseous and/or liquid precursors, such as a silicon-containing precursor and a carrier precursor, such as those described herein. The epitaxy process is performed until epitaxially grown silicon fills opening112A and opening112B of patterned oxide layer110. In some embodiments, the epitaxially grown silicon may overfill opening112A and opening112B, such that the epitaxially grown silicon extends above the top surface of patterned oxide layer110. In such embodiments, a planarization process, such as CMP, can be performed to remove portions of epitaxially grown silicon extending above and/or over the top surface of patterned oxide layer110, where patterned oxide layer110can function as a planarization stop. In some embodiments, the top surface of patterned oxide layer110and top surfaces of cap layers135are substantially planar after the planarization process. In some embodiments, cap layers135are formed by depositing an undoped semiconductor layer over patterned oxide layer110, doped silicon layers120, and germanium layers130, where the undoped semiconductor layer fills remainders of opening112A and opening112B, and then, performing a planarization process to remove the undoped semiconductor layer formed over the top surface of patterned oxide layer110. In some embodiments, a cleaning process is performed before forming cap layers135to remove defects from germanium layers130and/or patterned oxide layer110, such as any native oxide, contaminates, and/or other defects on germanium layers130and/or patterned oxide layer110. In some embodiments, the cleaning process is a baking process, such as those described herein.

Turning toFIG.1E, an oxide layer is formed over the photosensitive device. For example, an oxide layer140is formed over photosensitive device100, such that oxide layer140covers device region102A and device region102B. In the depicted embodiment, oxide layer140covers patterned oxide layer110and cap layers135. Oxide layer140includes oxygen and, in some embodiments, another suitable constituent. For example, oxide layer140can include silicon and oxygen (e.g., SiO2) and be referred to as a silicon oxide layer. Oxide layer140has a thickness t8. In some embodiments, thickness t8is about 10 nm to about 20 nm. Any suitable deposition process is implemented for forming oxide layer140, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), rapid thermal CVD (RTCVD), PECVD, plasma enhanced ALD (PEALD), LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. In the depicted embodiment, oxide layer140is formed over photosensitive device100by CVD.

First type doped regions145extend from top surfaces of cap layers135to a depth D1in germanium layers130. First type doped regions150are disposed in germanium layers130at a depth D2, extending from depth D2to depth D1(which is greater than D2) in germanium layer130. Second type doped regions155are disposed in germanium layers130at a depth D3, extending from depth D3to depth D2(which is greater than depth D3) in germanium layer130. First type doped regions160extend from top surfaces of cap layers135to depth D3in germanium layers130. Depth D1, depth D2, and depth D3are measured from top surfaces of germanium layers130. In some embodiments, depth D1is about 100 nm to about 200 nm. In some embodiments, depth D2is about 60 nm to about 90 nm. In some embodiments, depth D3is about 10 nm to about 20 nm. First type doped regions160are disposed over second type doped regions155, where p-n junctions are formed by interfaces between first type doped regions160and second type doped region155. Second type doped regions155are further disposed between first type doped regions145, where p-n junctions are formed by interfaces between second type doped regions155and first type doped regions145. First type doped regions160are also disposed between first type doped regions145, where interfaces are between first type doped regions160and first type doped regions145. First type doped regions150extend under second type doped regions155, where p-n junctions are formed by interfaces between first type doped regions150and second type doped regions155. First type doped regions145are disposed along doped silicon layers120and overlap an entire width of first type doped regions150. In some embodiments, first type doped regions145extend a depth into germanium layers130that is less than depth D1, such that first type doped regions145partially overlap first type doped regions150along their width. First type doped regions145have a thickness t9and a width W1, first type doped regions150have a thickness t10and a width W2, second type doped regions155have a thickness t11and a width W3, and first type doped regions160have a thickness t12and width W3. First type doped regions145disposed in a respective germanium layer130are separated by a spacing S1(which, in the depicted embodiment, is substantially equal to width W3) and first type doped regions150disposed in the respective germanium layer130are separated by a spacing S2(which, in the depicted embodiment, is less than width W3). In some embodiments, thickness t9is about 85 nm to about 200 nm. In some embodiments, thickness t10is about 20 nm to about 30 nm. In some embodiments, thickness t11is about 60 nm to about 150 nm. In some embodiments, thickness t12is about 5 nm to about 20 nm. In some embodiments, width W1is about 400 nm to about 1,500 nm. In some embodiments, width W2is about 800 nm to about 2,500 nm. In some embodiments, width W3is about 3,000 nm to about 5,000 nm. In some embodiments, thickness t9is a sum of thickness t7and depth D1, thickness t10is a difference of depth D1and depth D2, thickness t11is a difference of depth D2and depth D3, and/or thickness t12is a sum of thickness t7and depth D3.

The various doped regions can be formed in cap layers135and/or germanium layers130by lithography processes, such as those described herein, and implantation processes. For example, forming the various doped regions can include performing a first lithography process to form a first implant mask that exposes first areas of germanium layers130and performing a first implantation process using the first implant mask to introduce first type dopant into the first areas of germanium layers130to form first type doped regions145; performing a second lithography process to form a second implant mask that exposes second areas of germanium layers130(which can partially overlap the first areas) and performing a second implantation process using the second implant mask to introduce first type dopant into the second areas of germanium layers130to form first type doped regions150; performing a third lithography process to form a third implant mask that exposes a third area of germanium layers130(which can partially overlap the second areas and span between the first areas) and performing a third implantation process using the third implant mask to introduce second type dopant into the third area of germanium layers130to form second type doped regions155; and performing a fourth lithography process to form a fourth implant mask that exposes a fourth area of germanium layers130(which can overlap an entirety of the third area) and performing a fourth implantation process using the fourth implant mask to introduce first type dopant into the fourth area of germanium layers130to form first type doped regions160. In some embodiments, second type doped regions155and first type doped regions160are formed using one lithography process, instead of two. For example, the fourth lithography process can be omitted, and both the third implantation process and the fourth implantation process can use the third implant mask to form second type doped regions155and first type doped regions160, respectively. In such embodiments, parameters of the implantation processes, such as implant energy, implant dopant type, implant dosage, implant angle, and/or other suitable implant parameter, can be tuned to provide second type doped regions155and first type doped regions160in germanium layers130. The present disclosure contemplates the first, second, third, and fourth lithography/implantation processes being performed in any order. In some embodiments, parameters of the first, second, third, and/or fourth implantation processes, such as implant energy, implant dopant type, implant dosage, implant angle, and/or other suitable implant parameter, are tuned to achieve desired depths, desired dopant concentrations, desired dimensions (e.g., thicknesses and/or widths), and/or configurations of first type doped regions145, first type doped regions150, second type doped regions155, and/or first type doped regions160.

Turing toFIGS.1G-1J, doped polysilicon gates are formed over the germanium layer and first type doped regions are formed in the germanium layer under the doped polysilicon gates by self-diffusion. InFIG.1G, fabrication can include forming a patterned mask layer170over oxide layer140, where the patterned mask layer170has a gate opening178A and a gate opening178B in device region102A and device region102B that expose oxide layer140. Gate openings178A and gate openings178B are located over second type doped regions155and first type doped regions160formed in germanium layers130. In the depicted embodiment, patterned mask layer170has a patterned dielectric layer172and a patterned oxide layer175disposed over patterned dielectric layer172. Patterned dielectric layer172includes a dielectric material that is suitable for subsequently-formed gate spacers, such as a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable constituent, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, and/or silicon oxycarbonitride). Patterned oxide layer175includes a dielectric material that includes oxygen, and in some embodiments, another suitable constituent. In the depicted embodiment, patterned dielectric layer172includes silicon and nitrogen and can be referred to as a silicon nitride layer and patterned oxide layer175includes silicon and oxygen and can be referred to as a silicon oxide layer. Patterned dielectric layer172has a thickness t13, which corresponds with a thickness of subsequently-formed gate spacers, and patterned oxide layer175has a thickness t14. In some embodiments, thickness t13is about 30 nm to about 50 nm. In some embodiments, thickness t14is about 20 nm to about 40 nm.

In some embodiments, patterned mask layer170is formed by depositing a dielectric layer over oxide layer140, depositing an oxide layer over the dielectric layer, performing a lithography process to form a patterned resist layer over the oxide layer, and performing an etching process to transfer a resist pattern formed in the patterned resist layer to the oxide layer and the dielectric layer, thereby forming patterned mask layer170having patterned dielectric layer172and patterned oxide layer175. The dielectric layer and the oxide layer are deposited by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, RTCVD, PECVD, PEALD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. The lithography process can include forming a resist layer on the oxide layer (for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process, such as described herein. The etching process uses the patterned resist layer as an etch mask to remove exposed portions of the oxide layer and the dielectric layer to form gate openings178A and gate openings178B therein, which correspond with locations for subsequently-formed gates of photosensitive device100. The etching process includes a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. In some embodiments, portions of the oxide layer are removed to form patterned oxide layer175using the patterned resist layer as an etch mask and portions of the dielectric layer are removed to form patterned dielectric layer172using the patterned resist layer and/or patterned oxide layer175as an etch mask. In some embodiments, the etching process includes multiple steps, such as a first etch step that selectively etches the oxide layer and a second etch step that selectively etches the dielectric layer (e.g., the first etch step and the second etch step implement different etchants). In some embodiments, the oxide layer and the dielectric layer are removed using the same etchant. In some embodiments, the etching process stops upon reaching oxide layer140. In the depicted embodiment, the etching process, intentionally or unintentionally, etches and recesses exposed portions of oxide layer140a distance d2, which provides oxide layer140with a varying thickness. For example, unexposed portions of oxide layer140have thickness t1, and exposed portions of oxide layer140have a thickness that is less than thickness t1(for example, thickness of exposed portions of oxide layer140=thickness t1−distance d2). In some embodiments, distance d2is about 0 nm to about 5 nm. After the etching process, the patterned resist layer can be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is removed, completely or partially, during etching of the oxide layer and/or the dielectric layer.

InFIG.1H, fabrication can proceed with removing patterned oxide layer175from photosensitive device100and forming a doped polysilicon layer180over patterned dielectric layer172, where doped polysilicon layer180fills gate openings178A and gate openings178B. In some embodiments, patterned oxide layer175is removed by an etching process, such as a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. The etching process is configured to selectively remove patterned oxide layer175with respect to patterned dielectric layer172. In other words, the etching process substantially removes patterned oxide layer175but does not remove, or does not substantially remove, patterned dielectric layer172. For example, an etchant is selected for the etch process that etches silicon oxide (i.e., patterned oxide layer175) at a higher rate than silicon nitride (i.e., patterned dielectric layer172) (i.e., the etchant has a high etch selectivity with respect to silicon oxide). In the depicted embodiment, a selective wet etching process removes patterned oxide layer175using a diluted hydrofluoric acid (DHF) solution. In some embodiments, a selective wet etching process removes patterned oxide layer175using a buffered oxide etch (BOE) solution.

Doped polysilicon layer180is formed by depositing a polysilicon material over patterned dielectric layer172by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, RTCVD, PECVD, PEALD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In the depicted embodiment, dopant is introduced into the polysilicon material during the depositing (i.e., in-situ). In some embodiments, dopant is introduced into the polysilicon material after the depositing (e.g., by an implantation process). In some embodiments, doped polysilicon layer180includes n-type dopant, such as phosphorous, and can be referred to as an n-doped polysilicon layer. In some embodiments, doped polysilicon layer180includes p-type dopant, such as boron, and can be referred to as a p-doped polysilicon layer. In some embodiments, doped polysilicon layer180has a dopant concentration of about 1×1019cm−3to about 1×1021cm−3. Doped polysilicon layer180covers a top surface of patterned dielectric layer172, fills gate openings178A and gate openings178B, and physically contacts oxide layer140. A portion of doped polysilicon layer180over the top surface of patterned dielectric layer172has a thickness t15. In some embodiments, thickness t15is about 80 nm to about 120 nm. Portions of doped polysilicon layer180that fill gate openings178A,178B have a thickness that is less than a sum of thickness t13of patterned dielectric layer172and thickness t1of oxide layer140(e.g., thickness=thickness t13+distance d2).

InFIG.1I, fabrication can proceed with performing a patterning process on doped polysilicon layer180and patterned dielectric layer172, thereby forming polysilicon gates180A and polysilicon gates180B from doped polysilicon layer180and gate spacers184from patterned dielectric layer172. Polysilicon gates180A and polysilicon gates180B have first portions disposed between respective gate spacers184and second portions disposed over and covering top surfaces of respective gate spacers184. The first portions have a thickness t16and a width W4, and the second portions have a thickness t17and a width W5that is greater than width W4. In some embodiments, width W4is about 200 nm to about 600 nm. In some embodiments, width W5is about 30 nm to about 50 nm. In some embodiments, thickness t16is about equal to thickness t13of patterned dielectric layer172. In some embodiments, thickness t17is about equal to thickness t15. In some embodiments, thickness t17is less than thickness t15. Gate spacers184are disposed along sidewalls of the first portions of polysilicon gates180A and sidewalls of the first portions of polysilicon gates180B. Gate spacers184have a height that is about equal to thickness t16and a width W6, which is about equal to a difference of width W5and width W4(e.g. width W6=width−width W4).

In some embodiments, the patterning process includes performing a lithography process to form a patterned resist layer over doped polysilicon layer180and performing an etching process to transfer a resist pattern formed in the patterned resist layer to doped polysilicon layer180, thereby forming polysilicon gates180A and polysilicon gates180B. The lithography process can include forming a resist layer on doped polysilicon layer180(for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process, such as described herein. The etching process uses the patterned resist layer as an etch mask to remove exposed portions of doped polysilicon layer180, such that unexposed, covered portions of doped polysilicon layer180remain to provide polysilicon gates180A and polysilicon gates180B over oxide layer140. The etching process includes a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. In some embodiments, portions of doped polysilicon layer180are removed to form polysilicon gates180A and polysilicon gates180B using the patterned resist layer as an etch mask and portions of patterned dielectric layer172are removed to form gate spacers184using the patterned resist layer and/or polysilicon gates180A and polysilicon gates180B as an etch mask. In embodiments where polysilicon gates180A and polysilicon gates180B are used as etch masks for etching patterned dielectric layer172, the etching process may, intentionally or unintentionally, etch second portions of polysilicon gates180A and polysilicon gates180B, such that thickness t17is less than thickness t15. In some embodiments, the etching process includes multiple steps, such as a first etch step that selectively etches doped polysilicon layer180and a second etch step that selectively etches patterned dielectric layer172(e.g., the first etch step and the second etch step implement different etchants). The etching process is configured to selectively remove doped polysilicon layer180and/or patterned dielectric layer172with respect to oxide layer140. In other words, the etching process substantially removes doped polysilicon layer180and/or patterned dielectric layer172but does not remove, or does not substantially remove, oxide layer140. For example, an etchant is selected for the etch process that etches doped polysilicon (i.e., doped polysilicon layer180) and/or silicon nitride (i.e., patterned dielectric layer172) at a higher rate than silicon oxide (i.e., oxide layer140) (i.e., the etchant has a high etch selectivity with respect to doped polysilicon and/or silicon nitride). In some embodiments, a mask layer is formed over doped polysilicon layer180and the patterned resist layer is formed over the mask layer. In such embodiments, a first etching process may remove portions of the mask layer to form a patterned mask layer, and a second etching process removes portions of doped polysilicon layer180and/or patterned dielectric layer172using the patterned mask layer as an etch mask. After the etching process, the patterned resist layer can be removed, for example, by a resist stripping process. In some embodiments, the patterned resist layer is removed, completely or partially, during etching of doped polysilicon layer180and/or patterned dielectric layer172.

After forming polysilicon gates180A and polysilicon gates180B, fabrication can include performing a diffusion process to diffuse dopant form polysilicon gates180A and polysilicon gates180B into germanium layers130, thereby forming first type doped regions185that connect polysilicon gates180A and polysilicon gates180B to first type doped regions160in germanium layers130. First type doped regions185extend from polysilicon gates180A and polysilicon gates180B to a depth D4in germanium layers130, such that first type doped regions185overlap first type doped regions160. Depth D4is measured from top surfaces of germanium layers130, and in the depicted embodiment, is less than depth D3. First type doped regions185thus include first type doped silicon portions (i.e., portions of cap layers135) and first type doped germanium portions (i.e., portions of germanium layers130). In some embodiments, depth D4is about 5 nm to about 10 nm. First type doped regions185have a dopant concentration that is greater than a dopant concentration of first type doped regions160. In some embodiments, first type doped regions185have a dopant concentration of about 1×1019cm−3to about 9×1020cm−3. In some embodiments, first type doped regions185include n-type dopant, such as phosphorous, and can be referred to as n-doped germanium regions (Ge N+). In some embodiments, first type doped regions185include p-type dopant, such as boron, and can be referred to as p-doped germanium regions (Ge P+). In the depicted embodiment, first type doped regions185have a width that is about equal to width W4. In some embodiments, first type doped regions185have a width that is greater than or less than width W4. First type doped regions185have a thickness t18. In some embodiments, thickness t18is about 30 nm to about 60 nm. In some embodiments, the diffusion process is an anneal process that drives dopant from polysilicon gates180A and polysilicon gates180B into germanium layers130to form first type doped regions185. In some embodiments, the anneal process exposes polysilicon gates180A and polysilicon gates180B to heat having a temperature of about 700° C. to about 850° C. In some embodiments, the anneal process is performed for about 30 minutes to about 120 minutes. Forming first type doped regions185by self-diffusion prevents damage to photosensitive device100that can arise when first type doped regions185are formed by an implantation process, such as damage to doped regions (i.e., first type doped regions145, first type doped regions150, second type doped regions155, and/or first type doped regions160) in germanium layers130and/or damage to p-n junctions in germanium layers formed by interfaces between the doped regions. Since first type doped regions185are formed by self-diffusion of gates, first type doped regions185can alternatively be referred to as gate diffusion regions and/or diffusion regions.

Turing toFIG.1J, additional doped regions are formed in the germanium layer. For example, second type doped regions190are formed in germanium layers130. Second type doped regions190extend a depth D5in germanium layers130, such that second type doped regions190overlap first type doped regions145, second type doped regions155, and first type doped regions160. Second type doped regions190overlap interfaces between first type doped regions145and first type doped regions160and interfaces between first type doped regions145and second type doped regions155(which interfaces form p-n junctions). Second type doped regions190are spaced a distance from first type doped regions185. Depth D5is measured from top surfaces of germanium layers130, and in the depicted embodiment, is greater than depth D3and less than depth D2. Second type doped regions190thus include second type doped silicon portions (i.e., portions of cap layers135) and second type doped germanium portions (i.e., portions of germanium layers130). In some embodiments, depth D5is about 20 nm to about 40 nm. In some embodiments, such as depicted, second type doped regions190extend into oxide layer140and have second type doped oxide portions. Second type doped regions190further have a width W7and a thickness t19. In some embodiments, width W7is about 30 nm to about 50 nm. In some embodiments, thickness t19is about 300 nm to about 1,500 nm. Second type doped regions190have a dopant concentration that is greater than a dopant concentration of first type doped regions145, second type doped regions155, and/or first type doped regions160. In some embodiments, second type doped regions190have a dopant concentration of about 1×1017cm−3to about 9×1018cm−3. In some embodiments, second type doped regions190include p-type dopant, such as boron, and can be referred to as p-doped germanium regions (Ge P+). In some embodiments, second type doped regions190include n-type dopant, such as phosphorous, and can be referred to as n-doped germanium regions (Ge N+).

First type doped regions195are also formed in germanium layers130. First type doped regions195extend a depth D6in germanium layers130, such that first type doped regions195overlap first type doped regions160. First type doped regions195are located between respective first type doped regions185and spaced a distance from the respective first type doped regions185. In some embodiments, the distance is about equal to width W6of gate spacers184. Depth D6is measured from top surfaces of germanium layers130, and in the depicted embodiment, is less than depth D3. First type doped regions195thus include first type doped silicon portions (i.e., portions of cap layers135) and first type doped germanium portions (i.e., portions of germanium layers130). In some embodiments, depth D6is about 5 nm to about 10 nm. First type doped regions195further have a width W8and a thickness t20. In some embodiments, width W8is about equal to a spacing between polysilicon gates180A and polysilicon gates180B. In some embodiments, width W8is about 2,000 nm to about 5,000 nm. In some embodiments, thickness t20is about 10 nm to about 20 nm. First type doped regions195have a dopant concentration that is greater than a dopant concentration of first type doped regions160. In some embodiments, first type doped regions195have a dopant concentration of about 1×1018cm−3to about 1×1020cm−3. In some embodiments, first type doped regions195include n-type dopant, such as phosphorous, and can be referred to as n-doped germanium regions. In some embodiments, first type doped regions195include p-type dopant, such as boron, and can be referred to as p-doped germanium regions.

In some embodiments, second type doped regions190are formed by performing a lithography process to form an implant mask that exposes areas of germanium layers130that overlap interfaces between first type doped regions145and first type doped regions160and/or interfaces between first type doped regions145and second type doped regions155and performing an implantation process using the implant mask to introduce second type dopant into the exposed areas of germanium layers130. In some embodiments, first type doped regions195are formed by performing a lithography process to form an implant mask that exposes areas of germanium layers130between polysilicon gates180A and polysilicon gates180B and performing an implantation process using the implant mask to introduce first type dopant into the exposed areas of germanium layers130. In some embodiments, first type doped regions195are formed after second type doped regions190. In some embodiments, first type doped regions195are formed before second type doped regions190. In some embodiments, an anneal process is performed after forming first type doped regions195and/or second type doped regions190, for example, to activate dopant therein and/or in other doped regions of photosensitive device100, such as first type doped regions145, first type doped regions150, second type doped regions155, first type doped regions160, and/or first type doped regions185. In some embodiments, the anneal process is a rapid thermal anneal (RTA). In some embodiments, the anneal process exposes photosensitive device100to heat having a temperature of about 700° C. to about 900° C. In some embodiments, the anneal process is performed for about 10 seconds (s) to about 30 s.

FIG.2provides a diagrammatic top view and a diagrammatic cross-sectional view of one device region, such as device region102A, of photosensitive device100along line A-A of the top view, in portion or entirety, after undergoing fabrication associated withFIGS.1A-1Jand, in some embodiments, additional fabrication, according to various aspects of the present disclosure. For ease of understanding, oxide layer140and cap layer135are omitted from the top view ofFIG.2. Device region102A includes a germanium-based sensor having a germanium photodiode that can convert photons (e.g., electromagnetic radiation, such as light) into charge carriers (e.g., electrons and/or holes), which can be measured as current and/or voltage. The germanium photodiode is located in silicon substrate105. For example, germanium layer130is wrapped by silicon substrate105(e.g., silicon substrate105is disposed along sidewalls and bottoms of germanium layer130), and germanium layer130has a laterally diffused photodiode (LD-PD) formed therein by p-n junctions between second type doped region155and first type doped regions145, such as a p-n junction A (which can be referred to as a left p-n junction) and a p-n junction B (which can be referred to as a right p-n junction). A first, left floating voltage node (FN_L) and a second, right floating voltage node (FN_R) are connected to respective second type doped regions190, such that p-n junction A and p-n junction B are electrically connected to first, left floating voltage node and second, right floating voltage node by respective second type doped regions190. Leakage current (also referred to as dark current) from the germanium photodiode is reduced by inserting doped silicon layer120between germanium layer130and silicon substrate105. In some embodiments, the leakage current can potentially be reduced by as much as 1000% compared to conventional germanium-based sensors, which do not have a doped silicon layer between a germanium photodiode and a silicon substrate. The germanium-based sensor in device region102A further has a double-gate junction field effect transistor (JFET), which improves control of the germanium photodiode. For example, gates of the double-gate JFET are provided by polysilicon gate180A (and underlying first type doped region185) and polysilicon gate180B (and underlying first type doped region185), a channel of the double-gate JFET is provided by second type doped region155(P-channel or N-channel (also be referred to as a channel layer and/or a JFET channel)), and source/drain regions of the double-gate JFET are provided by second type doped regions190(P+regions or N+ regions (also referred to as source/drain regions). A first, left gate voltage node (JFETG_L) and a second, right gate voltage node (JFETG_R) are connected to polysilicon gate180A and polysilicon gate180B, respectively. In the germanium-based sensor, first type doped region160functions as a passivation layer for the LD-PD, which reduces leakage current at a surface of the germanium photodiode, and first type doped region195is a pinned photodiode (PPD) (e.g., n-type PPD (NPPD) or p-type (PPPD)) that provides additional passivation for the LD-PD, further reducing leakage current at the surface of the germanium photodiode. Further, first type doped regions150function as electron lenses (e-lenses) in the germanium-based sensor, which increases optical fill factor (FF) of the germanium-based sensor. For example, first type doped regions150(i.e., e-lenses) can effectively guide or direct light to the LD-PD as well as metal light guiding structures, eliminating the need for the germanium-based sensor to have backside metal light guiding structures (i.e., a metal grid over a back surface of silicon substrate105to guide the light to the LD-PD), which provides the germanium-based sensor with a greater area upon which light can be guided to the LD-PD (and thus greater photosensitive area) compared to conventional sensors and thus improves optical fill factor. By reducing leakage current of the germanium photodiode, increasing optical fill factor of the germanium photodiode, and/or improving control of the germanium photodiode with the double-gate JFET, the germanium-based sensor with JFET exhibits better sensitivity, better conversion gain, and/or less noise than conventional germanium-based sensors. In some embodiments, the germanium-based sensor with JFET is a hole-sensing sensor. In such embodiments, first type doped regions145, first type doped regions150, first type doped regions160, first type doped regions185, and first type doped regions195are n-doped regions, while second type doped regions155and second type doped regions190are p-doped regions. In furtherance of such embodiments, polysilicon gates180A and polysilicon gates180B are n-doped polysilicon gates. In some embodiments, the germanium-based sensor with JFET is an electron-sensing sensor. In such embodiments, first type doped regions145, first type doped regions150, first type doped regions160, first type doped regions185, and first type doped regions195are p-doped regions, while second type doped regions155and second type doped regions190are n-doped regions. In furtherance of such embodiments, polysilicon gates180A and polysilicon gates180B are p-doped polysilicon gates. Different embodiments may have different advantages, and no particular advantage is required of any embodiment.FIG.2has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in device region102A of photosensitive device100, and some of the features described below can be replaced, modified, or eliminated in other embodiments of device region102A of photosensitive device100.

FIGS.3A-3Jare diagrammatic cross-sectional views of a photosensitive device200, such as a germanium-based sensor with junction-gate field effect transistor, in portion or entirety, at various fabrication stages according to various aspects of the present disclosure. For clarity and simplicity, similar features of photosensitive device100inFIGS.1A-1Jand photosensitive device200inFIGS.3A-3Jare identified by the same reference numerals. Fabrication of photosensitive device200inFIGS.3A-3Jis similar in many respects to fabrication of photosensitive device100inFIGS.1A-1J, except the germanium photodiode of photosensitive device200is fabricated and located on silicon substrate105, instead of in silicon substrate105. For example, turning toFIG.3A, fabrication begins with receiving silicon substrate105, depositing an oxide layer205over silicon substrate105, and forming cavities215in oxide layer205. Oxide layer205includes oxygen and, in some embodiments, another suitable constituent. For example, oxide layer205can include silicon and oxygen (e.g., SiO2) and be referred to as a silicon oxide layer. Oxide layer205has a thickness t21, which in some embodiments, is substantially the same as a desired depth (e.g., depth D) of cavities215. In some embodiments, thickness t21is about 900 nm to about 1,500 nm. Any suitable deposition process is implemented for forming oxide layer205, such as those described herein. Any suitable lithography process and etching process, such as those described herein, are implemented for patterning oxide layer205to form cavities215. In contrast to cavities115, cavities215extend through oxide layer205and expose silicon substrate105, such that cavities215have sidewalls formed by oxide layer205and bottoms formed by silicon substrate105. Turning toFIGS.3B-3J, fabrication of photosensitive device200then proceeds similar to photosensitive device100, for example, by forming doped silicon layers120that partially fill cavities215(FIG.3B), forming germanium layers130over doped silicon layers120that fill remainders of cavities215(FIG.3C), forming cap layers135over germanium layers130(FIG.3D), forming oxide layer140over photosensitive device200(FIG.3E), forming various doped regions in germanium layers130(e.g., first type doped regions145, first type doped regions150, second type doped regions155, and first type doped regions160) (FIG.3F), forming polysilicon gates180A and polysilicon gates180B over germanium layers130(FIGS.3G-3I), forming first type doped regions185in germanium layers130(FIG.3I), and forming second type doped regions190and first type doped regions195in germanium layers130(FIG.3J). In some embodiments, the deposition process implemented to form doped silicon layers120in cavities215is a non-selective deposition process, for example, that can grow epitaxial silicon from both silicon substrate105and oxide layer205.FIGS.3A-3Jhave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in photosensitive device200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of photosensitive device200.

FIG.4provides a diagrammatic top view and a diagrammatic cross-sectional view of one device region, such as device region102A, of photosensitive device200along line A-A of the top view, in portion or entirety, after undergoing fabrication associated withFIGS.3A-3Jand, in some embodiments, additional fabrication, according to various aspects of the present disclosure. For ease of understanding, oxide layer140is partially omitted and cap layer135is omitted from the top view of photosensitive device200inFIG.4. Device region102A of photosensitive device200inFIG.4is similar in many respects to device region102A of photosensitive device100inFIG.2. For example, device region102A includes a germanium-based sensor that is configured to reduce leakage current of its germanium photodiode, increase optical fill factor of its germanium photodiode, and/or improve control of its germanium photodiode with a double-gate JFET, such that the germanium-based sensor exhibits better sensitivity than conventional germanium-based sensors. Further, in photosensitive device200, leakage current from the germanium photodiode is further reduced by isolating sidewalls of the germanium photodiode with oxide layer205. Different embodiments may have different advantages, and no particular advantage is required of any embodiment.FIG.4has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in device region102A of photosensitive device200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of device region102A of photosensitive device200.

FIG.5is a diagrammatic cross-sectional view of a photosensitive device300, in portion or entirety, according to various aspects of the present disclosure. For clarity and simplicity, similar features of photosensitive device100inFIGS.1A-1Jand photosensitive device300inFIG.5are identified by the same reference numerals. Photosensitive device300is similar in many respects to photosensitive device100, except first type doped regions145do not overlap first type doped regions150. For example, first type doped regions145extend to depth D2in germanium layers130, instead of depth D3in germanium layers130, such that first doped regions145and first type doped regions150have interfaces at depth D2in germanium layers130.FIG.5has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in photosensitive device300, and some of the features described below can be replaced, modified, or eliminated in other embodiments of photosensitive device300.

FIG.6is a diagrammatic cross-sectional view of a photosensitive device400, in portion or entirety, according to various aspects of the present disclosure. For clarity and simplicity, similar features of photosensitive device200inFIGS.3A-3Jand photosensitive device400inFIG.6are identified by the same reference numerals. Photosensitive device400is similar in many respects to photosensitive device200, except first type doped regions145do not overlap first type doped regions150. For example, first type doped regions145extend to depth D2in germanium layers130, instead of depth D3in germanium layers130, such that first doped regions145and first type doped regions150have interfaces at depth D2in germanium layers130.FIG.6has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in photosensitive device400, and some of the features described below can be replaced, modified, or eliminated in other embodiments of photosensitive device400.

FIG.7is a flow chart of a method500for fabricating a photosensitive device, such as those depicted inFIGS.1A-1J,FIG.2,FIGS.3A-3J,FIG.4,FIG.5, andFIG.6, in portion or entirety, according to various aspects of the present disclosure. Method500begins with forming a sensor cavity over a silicon substrate at block505. Method500proceeds with forming an in-situ doped silicon layer that partially fills and lines the sensor cavity at block510, forming a germanium layer over the doped silicon layer that fills a remainder of the sensor cavity at block515, forming a photodiode and a junction field effect transistor that include the germanium layer (where the junction field effect transistor has a polysilicon gate) at block520, and forming a pinned photodiode passivation layer in the germanium layer at block525. In some embodiments, self-diffusion is used to form a diffusion region under the polysilicon gate. For example, method500includes performing an anneal process on the polysilicon gate.FIG.5has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional steps can be provided before, during, and after method500, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method500.

The various doped regions described herein, such as first type doped regions145, first type doped regions150, second type doped regions155, first type doped regions160, first type doped regions185, second type doped regions190, and first type doped regions195, can include both first type dopant and second type dopant, where a doped region is considered a first type doped region where a first type dopant concentration of the first type dopant is greater than a second type dopant concentration of the second type dopant (and thus provides a doped region having a first conductivity) and a second type doped region where the first type dopant concentration of the first type dopant is less than the second type dopant concentration of the second type dopant (and thus provides a doped region having a second conductivity).

The present disclosure provides for many different embodiments, including hole-sensing photosensitive devices and electron-sensing photosensitive devices, such as those described herein. The disclosed photosensitive devices have double-gate junction field effect transistors to improve control and various doped regions to improve performance, such as e-lenses for increasing optical fill factor, and/or channel layer and/or passivation layers that reduce leakage current and thereby improve performance.

An exemplary photosensitive device includes a silicon substrate, a germanium layer disposed over the silicon substrate, and a doped silicon layer disposed between the silicon substrate and the germanium layer. The photosensitive device further includes a first doped region, a second doped region, and a third doped region disposed in the germanium layer. The first doped region is disposed between the second doped region and the third doped region. The first doped region includes a first type dopant. The second doped region and the third doped region include a second type dopant. The photosensitive device further includes a fourth doped region, a fifth doped region, and a sixth doped region disposed in the germanium layer. The fourth doped region overlaps a first interface between the first doped region and the second doped region. The fifth doped region overlaps a second interface between the first doped region and the third doped region. The sixth doped region is disposed over the first doped region and between the fourth doped region and the fifth doped region. The fourth doped region and the fifth doped region include the first type dopant, and the sixth doped region includes the second type dopant. The photosensitive device further includes a polysilicon gate disposed over the sixth doped region. The polysilicon gate includes the second type dopant. The photosensitive device further includes a seventh doped region disposed in the germanium layer under the polysilicon gate. The seventh doped region includes the second type dopant.

In some embodiments, the first type dopant is n-type dopant and the second type dopant is p-type dopant. In some embodiments, the first type dopant is p-type dopant and the second type dopant is n-type dopant. In some embodiments, doped silicon layer is disposed between the silicon substrate and sidewalls of the germanium layer and between the silicon substrate and a bottom of the germanium layer. In some embodiments, the doped silicon layer is further disposed between an oxide layer and the germanium layer. In some embodiments, the doped silicon layer is disposed between the oxide layer and sidewalls of the germanium layer and between the silicon substrate and a bottom of the germanium layer.

In some embodiments, the photosensitive device further includes an eighth doped region and a ninth doped region disposed in the germanium layer. The second doped region is disposed over the eighth doped region. The third doped region is disposed over the ninth doped region. The first doped region is disposed over the eighth doped region and the ninth doped region. The eighth and the ninth doped region include the second type dopant. In some embodiments, the second doped region and the third doped region overlap the eighth doped region and the ninth doped region, respectively. In some embodiments, wherein the polysilicon gate is a first polysilicon gate and the photosensitive device further includes a second polysilicon gate disposed over the sixth doped region and an eighth doped region disposed in the germanium layer under the second polysilicon gate. The first polysilicon gate and the second polysilicon gate are disposed between the fourth doped region and the fifth doped region. The second polysilicon gate includes the second type dopant. The seventh doped region includes the second type dopant. In such embodiments, the photosensitive device can further include a ninth doped region disposed in the germanium layer between the first polysilicon gate and the second polysilicon gate. The ninth doped region includes the second type dopant.

Another exemplary photosensitive device includes a silicon substrate and a germanium-based photodiode having a germanium layer disposed over the silicon substrate. The germanium-based photodiode further has two first doped regions of a first conductivity type disposed in the germanium layer; two second doped regions of the first conductivity type disposed in the germanium layer over the two first doped regions, respectively; a third doped region of a second conductivity type disposed in the germanium layer over the two first doped regions and between the two second doped regions; and a fourth doped region of the first conductivity type disposed in the germanium layer over the third doped region. A doped silicon layer is disposed between and separates the silicon substrate and the germanium layer of the germanium-based photodiode. The photosensitive device further includes two doped polysilicon gates disposed over the third doped region. The fourth doped region is disposed between the two doped polysilicon gates. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type. In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type. In some embodiments, the photosensitive device further includes a silicon cap layer disposed over the germanium layer. In such embodiments, the two second doped regions and the fourth doped region are further disposed in the silicon cap layer. In some embodiments, the photosensitive device further includes two fifth doped regions of the first conductivity type disposed in the germanium layer under the two doped polysilicon gates, respectively. In some embodiments, the photosensitive device further includes an oxide layer disposed over the silicon substrate. In such embodiments, the doped silicon layer is further disposed between and separates the oxide layer and the germanium layer.

An exemplary method for forming a photosensitive device includes forming a sensor cavity over a silicon substrate, forming an in-situ doped silicon layer that partially fills and lines the sensor cavity, forming a germanium layer over the in-situ doped silicon layer that fills a remainder of the sensor cavity, and forming a photodiode and a junction field effect transistor that include the germanium layer. The junction field effect transistor has a polysilicon gate. In some embodiments, forming the junction field effect transistor includes performing a diffusion process to cause dopant to diffuse from the polysilicon gate into the germanium layer. In some embodiments, forming the sensor cavity includes etching the silicon substrate. In some embodiments, the method includes forming an oxide layer over the silicon substrate, where forming the sensor cavity includes etching the oxide layer to expose the silicon substrate.