Image sensor with voltage buffer for self-test

A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.

TECHNICAL FIELD

This disclosure relates generally to image sensors, and in particular but not exclusively, relates to test voltage sample and hold circuitry for use in self-testing an image sensor.

BACKGROUND INFORMATION

Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. Image sensors commonly utilize Complementary-Metal-Oxide-Semiconductor (CMOS) image sensors to capture image data of an imaged scene. CMOS devices include an array of pixels which are photosensitive to incident light from a scene for a particular amount of time. This exposure time allows charges of individual pixels to accumulate until the pixels have a particular signal voltage value, also known as the pixel grey value. These individual signal voltage values may then be correlated into digital image data representing the imaged scene.

Image quality is very important for an image sensor. To achieve higher quality, the increase of the number of pixels within the array provides one solution. To make sure such an image sensor work properly to match the more and more challenging design requirements, test and debug capabilities provided to an image sensor are the essence to ensure its quality. Test of mage sensors can be carried out externally and internally. For internal tests, the current image sensor only has very limited analog test modes built-in by default. Development of the some of the needed test capabilities, including some of the important self-tests becomes critical for debug purposes.

DETAILED DESCRIPTION

Examples directed to test voltage sample and hold circuitry with self-test control is described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise.

FIG. 1illustrates one example of an imaging system100in accordance with an embodiment of the present disclosure. Imaging system100includes pixel array102, control circuitry106, column arranged readout bitlines108, readout circuitry116, and function logic118. In one example, pixel array102is a two-dimensional (2D) array of photodiodes, or image sensor pixel cells104(e.g., pixels P1, P2. . . , Pn). As illustrated, photodiodes are arranged into rows (e.g., rows R1to Ry) and columns (e.g., column C1to Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc. However, photodiodes do not have to be arranged into rows and columns and may take other configurations.

In one example, after each image sensor photodiode/pixel in pixel array102has acquired its image data or image charge, the image data is readout by readout circuitry116and then transferred to the function logic118. The readout circuitry116may be coupled to read out image data from the plurality of photodiodes in pixel array102through bitlines108. In various examples, the readout circuitry116may comprise amplification circuitry and column ADC circuitry109. As will be described in greater detail below, the readout circuitry116may also comprise test voltage sample and hold (S/H) circuitry110. The test voltage S/H circuitry110may be controlled by S/H control signal(s)112from the control circuitry106to sample a test voltage with a pre-determined value to be held in a voltage storage and to output the stored test voltage114to be used by either the readout circuitry116and/or the control circuitry106. The control circuitry106may control the readout circuitry116with control signals120, or test voltages122which may be introduced to various pixels, ADCs109for testing purposes. The control circuitry106may also provide expected data178to the function logic118for testing.

In one example, function logic118may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry116may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels104simultaneously.

In one example, imaging system100may be included in a digital camera, cell phone, laptop computer, security system, automobile, or the like. Additionally, imaging system100may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system100, extract image data from imaging system100, or manipulate image data supplied by imaging system100.

FIG. 2Ais a schematic example200that illustrates how a test voltage sample and hold (S/H) circuitry210functions in a readout circuitry216. Inside the readout circuitry216, a ramp generator224provides ramp voltage Vramp226to a plurality of ADC comparators228as well as an input buffer230of the test voltage S/H circuitry210, where each ADC comparator228of the ADC109receives its other input from a respective bitline208. Inside the test voltage S/H circuitry210, the output of the input buffer230is coupled to one terminal of an S/H switch (SW)232. The other terminal of the S/H SW232is coupled to a voltage hold capacitor CS237and also to an output buffer260. A test voltage output214of the output buffer260is coupled to a control circuitry206. The control circuitry206provides a SW control signal212to turn SW232on or off, a ramp control signal220to control the ramp generator224, and a test voltage222to be injected to inputs of a device under test (DUT).

A plurality of column arranged readout bitlines208is introduced to the readout circuitry216. Each column bitline i208(i=1, 2, . . . , x, x is an integer) carries an analog image voltage signal that represent the brightness of a pixel in the current readout row j (j=1, 2, . . . , y, y is an integer) which is illuminated by the incident light. The analog image voltage signal is converted to digital image signal by a column ADC109which is associated with each column bitline208. The converted digital image signal is then transmitted to the function logic118for storage, comparison for test, or further processing as previously described.

The example column ADC implemented and used in the readout circuitry216may be a ramp ADC109. Each ramp ADC109may comprise a comparator228that compares between the analog image voltage and a linear ramp signal Vramp226generated by a ramp generator224. The ramp generator224may be shared by all column ADCs109or a portion of a plurality of column ADCs109.

The ramp signal Vramp226may ramp upward or downward either configured or directly controlled by the control circuitry206. The range of the ramp voltage is determined by the voltage range of the image signal between black and white introduced through the bitlines208. For a ramp-down Vramp226, since the ramp signal Vramp226is going to sweep through a very wide range of voltage from high to low each time it is used to convert the analog image signal to digital image signal, a pulse signal can be sent by the control circuitry206at the moment the predetermined voltage value is demanded to turn on switch SW232and allow the Vramp226value at the time t, VTT236, to be sampled through the input buffer230and held (stored) in the hold capacitor CS237during a readout of a current row j. The voltage value VTT236stored in the hold capacitor CS237can be fed to the control circuitry206through the output buffer260during the next row j+1. The control circuitry206can decide to inject to any injecting inputs predesigned in the pixels104, or the bitlines208, or the ADCs109at certain time during the readout on row j+1.

The result of the entire frame through voltage injections can be viewed on a final output image and used to debug on what problem appeared at what place of the injections. This is possible because each row of the displayed frame may be set to a predefined value as in a known function. All of those row values in combined may form a certain frame pattern that may be easily examined even by human eyes.

As a self-test, such a testing mechanism of injecting voltage values can be built in to the pixel array102or anywhere in the readout circuitry116. At any downstream data flow point from the pixel104to the bitline108or to the ADC109, the injected voltage value can be compared with the expected values to evaluate on whether the circuit is doing what it was designed to do. If any discrepancy is observed which indicates problem surfaced, a warning can be sent to alarm such a problem.

The exact voltage value of VTT236is sampled by a sample and hold (S/H) signal VSH234. VSH234is a short pulse signal212asserted by the control circuitry206. Since the control circuitry206also controls the ramp generator224, the starting time t0of each Vramp226is controlled by a ramp enable signal220of the control circuitry206. In an example where the Vramp226starts to roll down with a known constant linear rate, the exact voltage of Vramp226at a time t may be calculated based on how long (t-t0) the Vramp226has been ramping down from its initial voltage value since a starting time to. That is, if the enable signal220controls the ramp starting time t0and the pulse S/H signal212controls the S/H time t of when the Vramp226is sampled, the voltage value of VTT236is set by both signals220and212of the same control circuitry206.

Once the test voltage VTT236is sampled by the S/H signal VSH234, VTT236is held in the hold capacitor CS237. The hold capacitor CS237serves as a temporary voltage storage of the test voltage VTT236. For a typical fast frame rate of 60-100 frames per second and a multiple thousands of rows per frame, the continuously held voltage value is accurate enough to be used (for testing) during the current row of readout when sampled and held during the immediate previous row of readout.

Since the ramp signal Vramp226is mainly used to drive a plurality of ADC comparators228of the ADCs, the accuracy of Vramp226is extremely critical to the performance of the ADCs. To minimize the interference to Vramp226caused by switch SW232due to the activation of the S/H signal VSH234and the hold capacitor CS237(and other circuits that may also be connected to the SW232) when SW232is on, the input buffer230may be used to isolate the test voltage S/H circuitry210from disturbing the integrity of Vramp226. For the similar reason, the output buffer260may also be implemented to shield the test voltage S/H circuitry210from the control circuitry206.

Both the input buffer230and output buffers260may be made of a source follower or an operational amplifiers with a unity gain. In the case of both buffers230and260made of the source follower, since the gain of the buffer is smaller than 1, the sampling time t should be readjusted by the S/H signal VSH234which may be controlled by the control circuitry206accordingly. Such timing modifications assures that once the test voltage VTT236sampled at time t is received by the control circuitry206, it carries the needed driving voltage value222to be applied to a device under test (DUT)274in general as illustrated inFIG. 2B. The DUT may represent a portion of the pixel array102, a portion of the readout circuitry216, or any portion, standalone or combined, of the data circuit to be tested.

FIG. 2Billustrates a self-test circuitry268that may be configured to test the DUT274. A 2-to-1 multiplexer272is introduced to an input273of the DUT274to select between a default signal input271and a test value222driven by the control circuitry206. And a test comparator276is introduced to compare between an output of the DUT274and an expected value278. The selection of the 2-to-1 mux272is controlled by a test enable signal270from the control circuitry206. For normal operation, the signal input271is selected as a default input to the DUT274when the test enable signal270is set to low. The DUT274performs its designed function. For test operation, the driving value222is introduced to the DUT274through an injecting input269of the 2-to-1 mux272when the test enable signal270is set to high. The mux272may be replaced by two analog switches controlled by two inversely related signals, respectively. The expected value278may come from the control circuitry206or may be generated and provided locally within the DUT.

When each test value222is driven to the injecting input269to drive the DUT274, the DUT274responds with a measured value275. The measured value275is compared with the expected value278in the comparator278. If the measured value275equals to the expected value278, the pass/fail signal277indicates a pass, if otherwise, a fail. The test comparator276may be implemented to directly follow the DUT274physically at its output275or implemented in function logic118. The comparison task of test comparator276may be accomplished with either hardware, software, or a combination of hardware and software, to determine whether the test at local level or global level is a success or not. As a result, a self-test is established when an autonomous mechanism is constructed in an image sensor100, with a concluding signal277indicating the pass or fail of the self-test.

If a whole frame of an image sensor100is to be generated and tested using the S/H test voltages VTT236illustrated inFIG. 2A, a sequence illustrated inFIG. 2Cis to be followed.

FIG. 2Cis a flow chart280that illustrates a complete cycle of a frame readout of the image sensor under self-test in accordance with the embodiments of the present disclosure. The flow chart280begins at process block282. Process block282marks the beginning of a frame readout cycle starting with a new current row j (j=1, 2, . . . , y, y is an integer). A plurality of pixel cells in row j is being read out by the readout circuitry216through bitlines208. During block282, while Vramp226is ramping up or down for the ADC comparators228, at time t, SW232is closed momentarily by a short pulse234from SW control signal212. A test voltage VTT236is sampled at time t from Vramp226and held in a hold capacitor CS237.

The process block282may be followed by process block284. During block284, sequentially, image data of a plurality of pixel cells of the next row j+1 is being read out by the readout circuitry216through bitlines208. The test voltage VTT236which is sampled and held in the hold capacitor CS237during the readout of row j is accessed by the control circuitry206through an output buffer260and a test voltage output214. The control circuitry206then routes the test voltage VTTto the pre-configured injection inputs269in the image sensor under self-test. The test data based on the test voltage VTTmay later be compared with the expected data. Still in the readout period of row j+1, the data comparison may happen either within the local circuit block “on the fly” where the test data is injected to or happen down the signal flow stream until the function logic118. Once the image data is stored in the function logic118, the tested data may be compared with the expected data either concurrently or at a later time after the image data of the entire frame has been acquired.

The process block284may be followed by process block288. During block288, if the current row j+1 is determined not yet reaching the last row (that is, j+1=y) of the subject image frame, the process block288may be followed by process block290. If the current row j+1 is determined to be the very last row (j+1=y) of the subject image frame, the process block288may be followed by process block292.

In process block290, the next row to be read out in block282is set to be row j+2 (serves as the new “current row” in block282). It then loops back to process block282subsequently.

At the point the process block292has been reached, the “image data” of the entire frame based on the test data has been stored in the function logic118. The stored data are the measured data come from the readout circuitry216driven by the injected test data from the control circuitry206. It brings the needed test information. If there is any problem with the pixels104, bitlines108, or ADCs, etc, in the readout circuitry216, the self-test may be able to catch it by comparing the measured data with the expected data. The self-test disclosed here may be achieved either by hardware only, or by combinatory use of hardware and software. The expected data may also be stored locally in the function logic118or generated by the control circuitry206“on the fly” based on what test data has been injected to the image sense100under test, and provided to the function logic118.

The process block292may be followed by process block294. During block294, the self-test flow280for each frame as illustrated inFIG. 2Cis concluded.

As may be observed inFIG. 2C, due to the limitation (of having only one hold capacitor) of the test voltage S/H circuitry210disclosed inFIG. 2A, the test voltage VTT236can be sampled and held during the readout of row j and injected to the injection input269during the readout of the next row j+1. Therefore the so-called image data of the entire frame only has every alternate rows injected with test data by the control circuitry206. That means, only the interleaved rows of each frame are self-tested. To resolve this imperfection, the following embodiment is further disclosed.

FIG. 3Ais another schematic example300that illustrates how a test voltage S/H circuitry310functions in a readout circuitry316.

Inside the test voltage S/H circuitry310, an input buffer330still receives its input from a ramp voltage Vramp326which is generated by a ramp generator324of the readout circuitry316. The output of the input buffer330is coupled to two different hold capacitors CS1337and CS2347through S/H switches SW11332and SW21342, respectively. Test voltages VTT1336and VTT2346can therefore be sampled and held in separate hold capacitors CS1337and CS2347during the readout periods of any two adjacent rows, alternately. This makes it possible to have the sample and use (more like write/read to memory) operations take place in parallel during the readout of the same row.

For example, when the test voltage VTT2346is sampled and held in hold capacitors CS2347and the previously held VTT1336in the hold capacitors CS1337can be provided to a control circuitry306for test purpose. As a result, each single readout row will continuously receive a single driving signal322from the control circuitry306which was sampled and held during the readout of the previous row. The self-test therefore has every single rows of the entire frame covered under test completely, in comparing to interleaved 50% coverage disclosed inFIGS. 2A and 2C.

The sampled test voltages VTT1334or VTT2344can be achieved under control of the sample and hold signals VSH1334and VSH2344. VSH1334and VSH2344are pulse signals212asserted by the control circuitry206. Since the control circuitry306also controls the ramp generator324, the starting time t10/t20of each Vramp326are controlled by a ramp enable signal320of the control circuitry306.

In an example where the Vramp326starts to roll down with a known constant linear rate, the exact voltage of Vramp326at a time t1may be calculated based on how long (t1-t10) the Vramp326has been ramping down from its initial voltage value at a starting time t10. That is, if the enable signal320controls the ramp starting time t10and the pulse signal312controls the S/H time t1of when the Vramp326is sampled, the voltage value of VTT1336is set by both signals320and312of the same control circuitry306.

In similar way, when the Vramp326starts to roll down with a known constant linear rate, the exact voltage of Vramp326at a time t2may be calculated based on how long (t2-t20) the Vramp326has been ramping down from its initial voltage value at a starting time t20. That is, if the enable signal320controls the ramp starting time t20and the pulse signal312controls the S/H time t2of when the Vramp326is sampled, the voltage value of VTT2346is set by both signals320and312of the same control circuitry306.

Once the test voltage VTT1334or VTT2344are sampled by the S/H signal VSH1334or VSH2344, VTT1334or VTT2344are held in hold capacitor CS1337or CS2347. The hold capacitors CS1337and CS2347serve as the voltage storage of the test voltage VTT1334or VTT2344, respectively.

As can be expected, to accommodate the added second hold capacitor CS2347, selection switches SW12338and SW22348are also added to route only one of VTT1336or VTT2346to the input terminal354of an output buffer360at each time. SW12338or SW22348are set by VEN1340or VEN2350where each is one of the control signals312of the control circuitry306. The selected test voltage VTT1336or VTT2346is accessed by the control circuitry306through an output buffer360at a test voltage output314.

The control circuitry306then applies the test voltage VTT1336or VTT2346to drive a DUT274in an image sensor100under a self-test configuration. A test value322from a control circuitry306enabled by the test voltage VTT1336or VTT2346may be compared with an expected value278. Still in the readout period of each row, the data comparison may happen either within the local circuit block “on the fly” where the test value222is just freshly injected to the DUT274or takes effects somewhere down the signal flow stream until the measured value275arrives at the function logic118. Once the image test data is stored in the function logic118, the measured value275from the DUT274driven by the test value322may be compared with the expected value278either concurrently or at a later time after the image test data of the entire frame has been acquired.

The same as inFIG. 2A, since the ramp signal Vramp326inFIG. 3Ais mainly used to drive a plurality of ADC comparators328, the accuracy of Vramp326is extremely critical to the performance of the ADCs109. To minimize the interference to Vramp326caused by switches SW11332and SW21342due to the activation of the S/H signals VSH1334and VSH2344and the hold capacitors CS1337and CS2347, and other circuits that may also be connected to the SW11332and SW21342, when SW11332and SW21342are closed, the input buffer330may be used to isolate the test voltage S/H circuitry310from disturbing the integrity of Vramp326. For similar reason, the output buffer360may also be implemented to shield the test voltage S/H circuitry310from the control circuitry306.

Both the input buffer330and output buffers360may be made of a source follower or an operational amplifiers with a unity gain. In the case of both buffers330and360made of the source follower, since the gain of the buffer is smaller than 1, the sampling time t1/t2may need to be readjusted by the S/H signal VSH1334and VSH2344which may be controlled by the control circuitry306accordingly. Such timing modifications assures that once the test voltage VTT1336or VTT2346sampled at time t1/t2are received by the control circuitry306, it carries the needed value of voltage to drive the DUT274. The self-test circuit268ofFIG. 2Bmay be implemented in the pixel array102, or the bitline208, or the readout circuitry316where the control circuitry306may be able to drive.

The sameFIG. 2Billustrates a self-test circuit268that may be configured for the DUT274. A 2-to-1 multiplexer272is introduced to an input273of the DUT274to select between a default signal input271and a test value222/322driven by the control circuitry206/306. And a test comparator276is introduced to compare between an output of the DUT274and an expected value278. The selection of the 2-to-1 mux272is controlled by a test enable signal270from the control circuitry206/306. For normal operation, the signal input271is selected as a default input to the DUT274when the test enable signal270is set to low. For test operation, the test value222/322is driven to the DUT274through the 2-to-1 mux272when the test enable signal270is set to high. The mux272may be replaced with two analog switches controlled by two inversely related signals. The expected value278may come from the control circuitry206/306or may be provided locally within the DUT.

For each test value222/322introduced to the DUT274, the DUT274responds with a measured value275. The measured value275is compared with the expected value278in the comparator276. If the measured value275equals to the expected value278, the pass/fail signal277indicates a pass, if otherwise, a fail. The test comparator276may be implemented to directly follow the DUT274physically at its output275or implemented in function logic118(to display an entire frame of the image sensor100, for instance). The comparing task of test comparator276may be accomplished with either hardware, software, or a combination of hardware and software, to determine whether the test at local level or global level is a success or not. As a result, a self-test is established when an autonomous mechanism is constructed in an image sensor100, with a concluding signal277indicating the pass or fail of the self-test process.

If a whole frame of an image sensor100is to be generated and tested using the S/H test voltages out of VTT1336or VTT2346as illustrated inFIG. 3A, a sequence illustrated inFIG. 3Bis to be followed.

FIG. 3Bis a flow chart380that illustrates a complete cycle of a frame readout of the image sensor under self-test in accordance with all the embodiments of the present disclosure. The flow chart380begins at process block382. Process block382marks the beginning of a frame readout cycle starting with a new current row j (j=1, 2, . . . , y, y is an integer). A plurality of pixel cells in row j is being read out by the readout circuitry316. During block382, while Vramp326is ramping up or down for the ADC comparators328, at time t1, SW11332is closed momentarily by a short pulse334from SW control signal312. A test voltage VTT1336is sampled at time t1from Vramp326and held in a hold capacitor CS1337. During the same period of row j readout, operating in parallel, the previously held voltage VTT2346from CS2is fed to the control circuitry306and is selected to drive the injecting input(s) implemented in the image sensor100.

The test data based on the test voltage VTT1336or VTT2346may be compared with the expected data. Still in the readout period of row j, the data comparison may happen either within the local circuit block “on the fly” where the test data is injected to or happen down the signal flow stream until the function logic118. Once the image data is stored in the function logic118, the measured data may be compared with the expected data either concurrently or at a later time after the image data of the entire frame has been acquired.

The process block382may be followed by process block384. During block384, sequentially, image data of a plurality of pixel cells of the next row j+1 is being read out by the readout circuitry316. While Vramp326is ramping up or down for the ADC comparators328, at time t2, SW11332is closed momentarily by a short pulse344from SW control signal312. A test voltage VTT2346is sampled at time t2from Vramp326and held in a hold capacitor CS2347. During the same period of row j+1 readout, operating in parallel, the previously held voltage VTT1336from CS1337during block382was fed to the control circuitry306and was selected to drive the injecting input(s) implemented in the image sensor100.

The test data based on the test voltage VTT1336or VTT2346may be compared with the expected data. Still in the readout period of row j+1, the data comparison may happen either within the local circuit block “on the fly” where the test data is injected to or happen down the signal flow stream until the function logic118. Once the image data is stored in the function logic118, the tested data may be compared with the expected data either concurrently or at a later time after the image data of the entire frame has been acquired.

The process block384may be followed by process block388. During block388, if the current row j+1 is determined not yet reaching the last row (j+1=y) of the subject image frame, the process block388may be followed by process block390. If the current row j+1 is determined to be the very last row (j+1=y) of the subject image frame, the process block388may be followed by process block392.

In process block390, the next row to be read out in block382is set to be row j+2 (serves as the new “current row” for block382). It then loops back to process block382subsequently.

At the point the process block392has been reached, the image data of the entire frame as measured has been stored in the function logic118. The stored data are the measured data come from the readout circuitry316driven by the injected data from the control circuitry306. It brings all the needed test information. If there is any problem with the pixels104, bitlines108, or ADCs, or any circuit in the readout circuitry316, the self-test may be able to catch it by comparing the measured data against the expected data. The self-test disclosed here may be achieved by hardware only, or by combinatory use of hardware and software. The expected data may also be stored in the function logic118or generated by the control circuitry306“on the fly” based on what test data has been driven to the image sense100under test.

The process block392may be followed by process block394. During block394, the self-test flow380as illustrated inFIG. 3Bis concluded.

As may be observed inFIGS. 3A and 3B, the limitation of having only one hold capacitor of the test voltage S/H circuitry210disclosed inFIGS. 2A and 2Bhas been lifted. Hold capacitors CS1337and CS2347may take turns to hold the sampled voltages VTT1336and VTT2346, and to provide a demanded test voltage to the control circuitry306in an alternate ping-ponged way during each single row readout. That is, during one row readout, when one capacitor CS1337is busy holding voltage the newly sampled voltage VTT1336from the ramp generator324, the other capacitor CS2347is busy outputting pre-held voltage VTT2346to the control circuitry306. Next, during the subsequent row readout, when one capacitor CS2347is busy updating its newly sampled voltage VTT2346from the ramp generator324, its counterpart capacitor CS1337is busy providing its voltage VTT1336held during the immediate previous row readout to the control circuitry306. Therefore the test data of the entire frame has every single row stand a chance to be driven with test data by the control circuitry306.

WithFIGS. 3A and 3B, the coverage of the self-test rows spread over the entire frame instead of only the interleaved rows as disclosed inFIGS. 2A and 2B. That means, 100% of the rows in a frame may be self-tested in accordance with the teachings of the present disclosure. That is an improvement from 50% of the earlier disclosure as shown inFIGS. 2A and 2B.