Amplifying circuit and amplifying device with start-up function

An amplifying circuit is provided. The amplifying circuit includes a bias circuit receiving an operating voltage from a power supply circuit and generating a first bias voltage, a resistance circuit connected between the bias circuit and a gate node and transferring the first bias voltage to the gate node, a start-up circuit generating a high-level start-up voltage and supplying the start-up voltage to the gate node before the operating voltage is supplied, based on a control signal, and an amplifier started-up by receiving the start-up voltage and then receiving the operating voltage and the first bias voltage to amplify a high frequency signal input through the gate node.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit under 35 USC § 119(a) of priority to Korean Patent Application No. 10-2020-0061511 filed on May 22, 2020 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

The following description relates to an amplifying circuit and an amplifying device with a start-up function.

2. Description of Related Art

Typically, in a front-end module (FEM) embedded in a wireless communications device such as a mobile phone, a transmitting unit (or transmitter) and a receiving unit (or receiver) may share a single antenna implementing wireless fidelity (Wi-Fi) communications. Since the receiving unit and the transmitting unit share the antenna according to predetermined times in a time division duplex (TDD) manner, a switching time is important for the FEM.

In an example in which the FEM operates within 200 ns (within 400 ns at maximum) after receiving a control signal for a reception-on operation, the FEM should be operated within the predetermined period of time.

Generally, a low-noise amplifier (LNA) included in the receiving unit of the FEM may not use external power, but may receive an operating voltage through an internal power supply circuit including a bandgap reference (BGR), a low dropout (LDO), or the like.

In an example where the external power is approximately 3 V to 5 V, when the external power is directly applied to the LNA, an element such as an internal complementary metal-oxide-semiconductor (CMOS) transistor may be damaged. Therefore, the internal power supply circuit drops the external power to a stable voltage, and supplies the reduced voltage as the operating voltage (VDD) of the LNA.

In the typical LNA, in an example where the operating voltage (VDD) is supplied through the internal power supply circuit, and a bias voltage is generated by using the operating voltage (VDD), a point in time at which the operating voltage (VDD) is supplied after receiving the control signal may be delayed, and a point in time at which the bias voltage is generated and supplied may be delayed. Therefore, a point in time at which the LNA is operated is delayed, which is problematic.

SUMMARY

In a general aspect, an amplifying circuit includes a bias circuit, configured to receive an operating voltage from a power supply circuit, and generate a first bias voltage, a resistance circuit, connected between the bias circuit and a gate node, and configured to transfer the generated first bias voltage to the gate node, a start-up circuit, configured to generate a high-level start-up voltage, and supply the generated start-up voltage to the gate node before a supply of the operating voltage, based on a control signal; and an amplifier, configured to start up based on a receipt of the generated start-up voltage, and receive the operating voltage and the first bias voltage to amplify a high frequency signal input through the gate node.

The start-up circuit may be configured to output the generated start-up voltage with a level that is increased to a high level from a point in time at which the control signal has an operation-on level, and is configured to be maintained at the high level until a point in time at which the operating voltage is increased to a high voltage level.

The bias circuit may include a first resistor, a second resistor, and a bias transistor connected in series between an operating voltage terminal and a ground, the bias transistor may include a drain and a gate, which are commonly connected, and a source connected to the gate through a capacitor and connected to the ground, and in the bias circuit, a second bias voltage is output from a first node positioned between the first resistor and the second resistor to the amplifier, and the first bias voltage is supplied from the gate of the bias transistor.

The amplifying circuit may include an input matching circuit connected between an input terminal and the gate node, and configured to transfer the high frequency signal input from the input terminal to the amplifier through the gate node; and an output matching circuit connected between an output node of the amplifier, an operating voltage terminal, and an output terminal, and configured to transfer the operating voltage to the amplifier, and transfer a high frequency signal output from the amplifier to the output terminal.

The amplifier may include a first amplifying transistor and a second amplifying transistor that are connected in cascode between the operating voltage terminal and the ground, the first amplifying transistor may include a gate connected to the gate node, a source connected to the ground, and a drain connected to a source of the second amplifying transistor, and the second amplifying transistor may include a gate through which the second bias voltage is input, the source connected to the drain of the first amplifying transistor, and a drain connected to an output node of the amplifier.

The start-up circuit may include an exclusive disjunction circuit, configured to perform an exclusive disjunction on the control signal and the operating voltage; and a switch element, configured to perform a switching operation based on a switching signal of the exclusive disjunction circuit, and transfer the start-up voltage to the gate node when the switch element is in an ON state.

The first amplifying transistor may be configured to form a current mirror structure together with the bias transistor, a gate length of the first amplifying transistor is equal to a gate length of the bias transistor, and a gate width of the first amplifying transistor and a gate width of the bias transistor have a predetermined ratio, 1:k, where k is a real number equal to or greater than 1.

In a general aspect, an amplifying device includes a power supply circuit, configured to generate an operating voltage in response to a control signal; and an amplifying circuit, configured to receive the generated operating voltage to amplify an input high frequency signal, wherein the amplifying circuit may include a bias circuit, configured to receive the operating voltage from the power supply circuit and generate a first bias voltage; a resistance circuit, connected between the bias circuit and a gate node, and configured to transfer the generated first bias voltage to the gate node; a start-up circuit, configured to generate a high-level start-up voltage, and supply the generated start-up voltage to the gate node before a supply of the operating voltage, based on the control signal; and an amplifier, configured to start up based on a receipt of the start-up voltage, and receive the operating voltage and the first bias voltage to amplify the high frequency signal input through the gate node.

The start-up circuit is configured to output the generated start-up voltage with a level that is increased to a high level from a point in time at which the control signal has an operation-on level, and is configured to be maintained at the high level until a point in time at which the operating voltage is increased to a high voltage level.

The bias circuit may include a first resistor, a second resistor, and a bias transistor connected in series between an operating voltage terminal and a ground, the bias transistor includes a drain and a gate, which are commonly connected, and a source connected to the gate through a capacitor and connected to the ground, and in the bias circuit, a second bias voltage is output from a first node positioned between the first resistor and the second resistor to the amplifier, and the first bias voltage is supplied from the gate of the bias transistor.

The resistance circuit may include a resistor configured to transfer the first bias voltage to the gate node, and configured to suppress the high frequency signal input through the gate node.

The amplifying device may further include an input matching circuit connected between an input terminal and the gate node, and configured to transfer a signal input from the input terminal to the amplifier through the gate node; and an output matching circuit connected between an output node of the amplifier, an operating voltage terminal, and an output terminal, and configured to transfer the operating voltage to the amplifier, and transfer a high frequency signal output from the amplifier to the output terminal.

The amplifier may include a first amplifying transistor and a second amplifying transistor that are connected in cascode between the operating voltage terminal and the ground, the first amplifying transistor may include a gate connected to the gate node, a source connected to the ground, and a drain connected to a source of the second amplifying transistor, and the second amplifying transistor may include a gate through which the second bias voltage is input, the source connected to the drain of the first amplifying transistor, and a drain connected to an output node of the amplifier.

The start-up circuit may include an exclusive disjunction circuit, configured to perform an exclusive disjunction on the control signal and the operating voltage; and a switch element, configured to perform a switching operation based on a switching signal of the exclusive disjunction circuit, and transfer the start-up voltage to the gate node when the switch element is in an ON state.

The first amplifying transistor may be configured to form a current mirror structure together with the bias transistor, a gate length of the first amplifying transistor is equal to a gate length of the bias transistor, and a gate width of the first amplifying transistor and a gate width of the bias transistor have a predetermined ratio, 1:k, where k is a real number equal to or greater than 1.

In a general aspect, a communication terminal includes an amplifying device including a power supply circuit configured to generate an operating voltage in response to a control signal, and an amplifying circuit configured to receive the operating voltage, and amplify a high frequency signal input through an input terminal, wherein the amplifying circuit includes a start-up circuit configured to generate a high-level start-up voltage, and transmit the generated start-up voltage to an amplifier of the amplifying circuit, and wherein the amplifier is configured to start up upon receipt of the start-up voltage, and before the operating voltage is received.

The amplifying circuit may further include a bias circuit, configured to generate a first bias circuit, and the amplifier may be configured to amplify the high frequency signal based on the operating voltage and the first bias voltage.

The start-up circuit may include an exclusive disjunction circuit configured to output a switching signal by performing an exclusive disjunction on the control signal and the operating voltage, and a switch element configured to perform a switching operation based on the switching signal, and transfer the start-up voltage to the amplifier in an ON state.

The amplifying circuit may be one of a low-noise amplifier and a power amplifier.

DETAILED DESCRIPTION

FIG. 1illustrates an example amplifying circuit and an example amplifying device, in accordance with one or more embodiments.

Referring toFIG. 1, an amplifying device10, in accordance with one or more embodiments, may include a power supply circuit50and an amplifying circuit100.

In an example, the power supply circuit50may generate an operating voltage VDD in response to a control signal SC. For example, the control signal SC may be a control signal for operation-on (for example, a reception-on operation or a transmission-on operation). In an example, the control signal SC may be a reception-on control signal or transmission-on control signal in a time division duplex (TDD) wireless communications terminal. The control signal, however, is not limited to the above example. Herein, it is noted that use of the term ‘may’ with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists where such a feature is included or implemented while all examples and embodiments are not limited thereto.

The amplifying circuit100may receive the operating voltage VDD, amplify a high frequency signal input through an input terminal IN, and output the amplified signal through an output terminal OUT. In a non-limiting example, in the TDD wireless communications terminal, the amplifying circuit100may include a low-noise amplifier (LNA) or a power amplifier (PA).

In the respective drawings of the present disclosure, an unnecessarily overlapping description of components having the same reference numeral and the same function may be omitted and a difference may be mainly described.

FIG. 2illustrates an example internal configuration of the amplifying circuit100ofFIG. 1.

Referring toFIGS. 1 and 2, the amplifying circuit100may include a bias circuit110, a resistance circuit120, a start-up circuit150, and an amplifier130.

The bias circuit110may receive the operating voltage VDD from the power supply circuit50, and generate a first bias voltage Vg1.

The resistance circuit120may be connected between the bias circuit110and a gate node Ng, and may receive the generated first bias voltage Vg1from the bias circuit110, and transfer the received first bias voltage Vg1to the gate node Ng.

The start-up circuit150may generate a high-level start-up voltage Vstg and transmit the generated start-up voltage Vstg to the amplifier130through the gate node Ng before the operating voltage VDD is supplied, based on the control signal SC.

In an example, the start-up circuit150may output the start-up voltage Vstg, whose level is increased, to a high level from a point in time T1when the control signal SC has an operation-on level, and may be maintained at the high level until a point in time T2when the operating voltage VDD is increased to a high voltage level. In an example, the operation-on level may be a high level corresponding to a reception-on level or transmission-on level.

The amplifier130may be started-up upon receipt of the start-up voltage Vstg, and may then receive the operating voltage VDD and the first bias voltage Vg1to amplify a high frequency signal input through the gate node Ng. In an example, the amplifier130may include at least a first amplifying transistor M31.

FIG. 3is a detailed circuit diagram illustrating an example of the internal configuration of the amplifying circuit100ofFIG. 1.

Referring toFIG. 3, the bias circuit110may include a first resistor R11, a second resistor R12, and a bias transistor M11that are connected in series between an operating voltage (VDD) terminal and a ground.

In an example, the bias transistor M11may include a drain and a gate, commonly connected, and a source connected to the gate through a capacitor C11and connected to the ground.

In an example, in the bias circuit110, a second bias voltage Vg2may be output from a first node N1positioned between the first resistor R11and the second resistor R12to the amplifier130, and the first bias voltage Vg1may be transmitted from the gate of the bias transistor M11. However, in an example, the bias circuit110may be a circuit that may supply the first and second bias voltages Vg1and Vg2. Accordingly, the bias circuit110is not limited to the above example.

The resistance circuit120may include a resistor R20connected between the bias circuit110and the gate node Ng. The resistance circuit120may transfer the first bias voltage Vg1to the gate node Ng, and suppress the high frequency signal input through the gate node Ng.

In an example in which the start-up circuit150is not provided, and the first bias voltage Vg1is transferred to the amplifier through the resistance circuit120, an increase of a gate voltage of the first amplifying transistor M31is delayed as much as a delay time according to a time constant determined based on a resistance of the resistance circuit120and a parasitic capacitance of the first amplifying transistor M31included in the amplifier130, which is disadvantageous.

Each example herein adopts the start-up circuit150in order to solve the above disadvantages.

Additionally, referring toFIGS. 2 and 3, the amplifying circuit100may include an input matching circuit IMC and an output matching circuit OMC.

The input matching circuit IMC may be connected between the input terminal IN and the gate node Ng, and may transfer a signal input from the input terminal IN to the amplifier130through the gate node Ng.

In an example, the input matching circuit IMC may include an inductor L61and a capacitor C61connected in series between the input terminal IN and the amplifier130for input impedance matching between the input terminal IN and the amplifier130.

The output matching circuit OMC may be connected between an output node NO of the amplifier130, the operating voltage (VDD) terminal, and the output terminal OUT. The output matching circuit OMC may transfer the operating voltage VDD to the amplifier130, and may transfer a high frequency signal from the amplifier130to the output terminal OUT.

In an example, the output matching circuit OMC may include an inductor L71and a capacitor C71for output impedance matching between the output node NO of the amplifier130and the output terminal OUT. In an example, the inductor L71may be connected between the output node NO of the amplifier130and the operating voltage (VDD) terminal, and may supply the operating voltage VDD to the amplifier130. The capacitor C71may be connected between the output node NO of the amplifier130and the output terminal OUT, and may transfer the high frequency signal output from the amplifier130to the output terminal OUT.

In an example, the amplifier130may include the first amplifying transistor M31, and a second amplifying transistor M32that are connected in cascode between the operating voltage (VDD) terminal and the ground.

In an example, the first amplifying transistor M31may include a gate connected to the gate node Ng, a source connected to the ground through an inductor L31, and a drain connected to a source of the second amplifying transistor M32. In an example, the first amplifying transistor M31may be started-up by receiving the start-up voltage Vstg through the gate node Ng, and may then receive the first bias voltage Vg1to perform an amplifying operation.

The second amplifying transistor M32may include a gate through which the second bias voltage Vg2is input, a source connected to the drain of the first amplifying transistor M31, and a drain connected to the output node NO of the amplifier130. In an example, the second amplifying transistor M32may be operated by receiving the second bias voltage Vg2.

In an example, the start-up circuit150may include an exclusive disjunction switch151and a switch element152.

The exclusive disjunction circuit151may output a switching signal SSW by performing an exclusive disjunction on the control signal SC and the operating voltage VDD.

The switch element152may perform a switching operation according to the switching signal SSW of the exclusive disjunction circuit151and transfer the start-up voltage Vstg to the gate node Ng when the switch element152is in an ON state.

Further, the first amplifying transistor M31may form a current mirror structure together with the bias transistor M11. In an example, a gate length of the first amplifying transistor M31may be the same as a gate length of the bias transistor M11, and a gate width of the first amplifying transistor M31and a gate width of the bias transistor M11may have a predetermined ratio (1:k, where k is a real number of 1 or more).

In an example, once the control signal SC is input to operate the amplifying device10, the power supply circuit50supplies the operating voltage VDD. The operating voltage VDD may be supplied to the amplifier130of the amplifying circuit100, and the bias circuit110may supply the respective first and second bias voltages Vg1and Vg2to the respective gates of the first and second amplifying transistors M31and M32, with the operating voltage VDD.

As described above, in addition to a driving time of the power supply circuit50, the resistance circuit120connected to an output terminal of the bias circuit may delay a switching time for operation of the amplifier130, which is disadvantageous.

In order to solve such a disadvantage, the start-up voltage Vstg may be transmitted to the first amplifying transistor M31of the amplifier130to start-up the first amplifying transistor M31before the operating voltage VDD is applied to the amplifier130, and then the power supply circuit50may apply the operating voltage VDD to the amplifier130, thereby enabling the amplifier130to be rapidly operated.

Additionally, referring toFIG. 3, the start-up circuit150may supply the start-up voltage Vstg to the amplifier130from the point in time T1when the control signal SC is supplied until the operating voltage VDD is supplied, such that the amplifier130is started-up in advance to prepare for operation. Then, once the operating voltage VDD is supplied, the amplifier130may perform the amplifying operation immediately.

FIG. 4is a point in time chart illustrating main signals and voltages of an example amplifying device without the start-up circuit, andFIG. 5is a point in time chart illustrating main signals and voltages of an example amplifying device with the start-up circuit.

Referring toFIG. 4, in an example, in the amplifying device without the start-up circuit, once the control signal SC has the operation-on level, the operating voltage VDD may be supplied after a predetermined period of time, and the first bias voltage Vg1may be supplied with the operating voltage VDD. In an example, the operation-on level may be a high level corresponding to a reception-on level or transmission-on level.

It may be appreciated that, with such an operation process, a long delay time DT (approximately 0.15 μsec) may be necessary from the point in time T1when the control signal SC is supplied to the point in time T2when the first bias voltage Vg1is increased to a high level.

Referring toFIG. 5, in the amplifying device with the start-up circuit, the start-up circuit150sets the switching signal SSW to an ON state to supply the start-up voltage Vstg from a point in time at which the control signal SC has the operation-on level to a point in time at which the operating voltage VDD is supplied, such that a gate voltage VG may be increased to a high level in advance by the start-up voltage Vstg. As a result, once the operating voltage VDD is supplied, the amplifier130may be operated immediately. In an example, the operation-on level may be a high level corresponding to a reception-on level or transmission-on level.

It may be appreciated that, with such an operation process, a short delay time DT (approximately 0.05 μsec) is required from the point in time T1when the control signal SC is supplied to the point in time T2when the first bias voltage Vg1is increased to a high level.

FIG. 6is a response characteristic graph of the example amplifying device without the start-up circuit, andFIG. 7is a response characteristic graph of the example amplifying device with the start-up circuit.

InFIGS. 6 and 7, it is assumed that T1is a point in time at which the control signal SC is supplied, T2is a point in time at which an output signal Sout of the amplifying device10is output, and a time between two points in time (T1and T2) is a response time. Referring toFIG. 6, it may be appreciated that a response time of the amplifying device without the start-up circuit is approximately 405.47 nsec. On the other hand, a response time of the amplifying device with the start-up circuit is approximately 131.43 nsec, which indicates that the amplifying device according to the present disclosure has an improved response time.

As set forth above, according to the examples, the start-up voltage for start-up may be supplied before supplying the operating voltage based on the control signal for operation-on, thereby enabling the amplifying circuit to be more rapidly operated.