According to one embodiment, a thin-film transistor includes a polycrystalline semiconductor layer, a gate electrode opposing the polycrystalline semiconductor layer, a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode, and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-022627, filed Feb. 9, 2016, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a thin-film transistor comprising a polycrystalline semiconductor layer.

BACKGROUND

For example, as a thin-film transistor applicable to display devices such as liquid crystal displays, various control circuits and the like, a type which uses polycrystalline silicon (polysilicon) for the semiconductor layer is developed.

Polycrystalline silicon contains a plurality of crystals different from each other in size and orientation surface. Polycrystalline silicon is obtained by, for example, the following technique in which a laser beam is irradiated onto amorphous silicon and then the fused silicon re-solidifies into poly-crystals. But, during this operation, crystals may collide with each other to create a projection in a crystal boundary (to be referred to as grain boundary hereinafter).

If such polycrystalline silicon is used for the semiconductor layer of a thin-film transistor, a gate insulating film is brought into contact with the projection created in the grain boundary of the polycrystalline silicon. Therefore, in the boundary between the semiconductor layer and the gate insulating film, an interface state is easily created. If an interface state is produced in the boundary between the semiconductor layer and the gate insulating film, the drain current flows at a voltage lower or equal to the threshold voltage, thereby creating the tendency of degrading the sub-threshold characteristics. Further, there are further tendencies of increasing the leakage current flowing into the semiconductor layer from the gate electrode, or decreasing the voltage resistance of the gate insulating film, which decreases the reliability of the thin-film transistor.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided a thin-film transistor comprising: a polycrystalline semiconductor layer; a gate electrode opposing the polycrystalline semiconductor layer; a gate insulating film provided between the gate electrode and the polycrystalline semiconductor layer and in contact with the gate electrode; and an amorphous layer provided between the gate insulating film and the polycrystalline semiconductor layer, and in contact with the gate insulating film and the polycrystalline semiconductor layer.

According to another embodiment, there is provided a thin-film transistor comprising: an insulating substrate; a polycrystalline semiconductor layer formed above a top surface of the insulating substrate; an amorphous layer in contact with a top surface of the polycrystalline semiconductor layer; an insulating film in contact with a top surface of the amorphous layer; a gate electrode in contact with a top surface of the insulating film; and first and second electrodes each in contact with the polycrystalline semiconductor.

According to yet another embodiment, there is provided a thin-film transistor comprising: an insulating substrate; a gate electrode formed above a top surface of the insulating substrate; an insulating film in contact with a top surface of the gate electrode; an amorphous layer in contact with a top surface of the insulating film; a polycrystalline semiconductor layer in contact with a top surface of the amorphous layer; and first and second electrodes each in contact with a top surface of the polycrystalline semiconductor layer.

First Embodiment

FIG. 1is a cross section schematically showing a thin-film transistor TR1according to the first embodiment. The thin-film transistor TR1is a top-gate thin-film transistor.

An insulating substrate10is formed from, for example, an insulating material such as glass or resin. The insulating substrate10includes a top surface10T, on which a first insulating film11is formed as an underlayer.

On the first insulating film11, an island-like semiconductor layer SC is formed. The semiconductor layer SC is formed from, for example, a polycrystalline semiconductor such as low-temperature polycrystalline silicon (LTPS).

The semiconductor layer SC comprises a source region SCa, a drain region SCb and a channel region SCc. The source region SCa and the drain region SCb are provided respectively on both ends of the semiconductor layer SC. To the source region SCa and the drain region SCb, impurities including, for example, phosphorus (P) are implanted to reduce the resistances of the regions. The channel region SCc is formed between the source region SCa and the drain region SCb. The channel region SCc has an impurity concentration lower than those of the source region SCa and the drain region SCb, and therefore has a high resistance.

On the semiconductor layer SC, an amorphous layer AL is formed. The amorphous layer AL is in contact with the top surface SCT of the semiconductor layer SC. In the example illustrated, the amorphous layer AL covers the entire top surface SCT. That is, the amorphous layer AL covers the source region SCa, the drain region SCb and the channel region SCc.

The amorphous layer AL is formed from, for example, a transparent amorphous oxide semiconductor (TAOS) containing an oxide of at least one of, for example, indium (In), gallium (Ga), zinc (Zn) and tin (Sn). The amorphous layer AL may be formed from, for example, some other amorphous material such as amorphous silicon, besides TAOS. When compared with the amorphous silicon, the oxide semiconductor is preferable because of its advantages, namely, high mobility, steep sub-threshold characteristics, low off-state current and the like.

The amorphous layer AL is thinner than the semiconductor layer SC and has such a degree of thickness that can flatten (planarize) the irregularities created by the grain boundary on the surface of the semiconductor layer SC. For example, a thickness WAL of the amorphous layer AL is, for example, approximately one tenth of a thickness WSC of the semiconductor layer SC. As an example, the thickness WSC of the semiconductor layer SC is 20 nm to 100 nm, whereas the thickness WAL of the amorphous layer AL is 2 nm to 10 nm.

The amorphous layer AL, the semiconductor layer SC and the first insulating film11are covered by a second insulating film12as a gate insulating film. In the example illustrated, the second insulating film12is in contact with the entire top surface ALT of the amorphous layer AL, the semiconductor layer SC and the first insulating film11.

On the second insulating film12, a gate electrode GE is formed. The gate electrode GE is in contact with a top surface12T of the second insulating film12. The gate electrode GE is formed at a location which opposes the channel region SCc of the semiconductor layer SC.

The gate electrode GE and the second insulating film12are covered by a third insulating film13as an interlayer insulating film. The first to third insulating films11to13are each formed of, for example an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride.

On the third insulating film13, a source electrode SE and a drain electrode DE are formed. The source electrode SE and the drain electrode DE are connected to the source region SCa and the drain region SCb of semiconductor layer SC, respectively, via contact holes CH1and CH2made through the third insulating film13, the second insulating film12and the amorphous layer AL. Further, the source electrode SE and the drain electrode DE are in contact with the amorphous layer AL within the contact holes CH1and CH2.

Next, a method of manufacturing the thin-film transistor TR1shown inFIG. 1will be described with reference toFIG. 2, (a) to (d).

As shown inFIG. 2, (a), the first insulating film11of, for example, silicon oxide is formed on the insulating substrate10using, for example, a plasma chemical vapor deposition (CVD). Next, on the first insulating film11, an amorphous silicon layer is formed using, for example, plasma CVD. Subsequently, pulsed light of an excimer laser, for example, is irradiated onto the amorphous silicon layer. Thus, silicon is fused then re-solidified to form the polycrystalline silicon layer SCd. Then, photolithography is carried out, and thereafter the polycrystalline silicon layer SCd is etched into the island-like semiconductor layer SC.

Next, as shown inFIG. 2, (b), the amorphous layer ALa of TAOS is formed so as to cover the semiconductor layer SC and the first insulating film11using, for example, a sputtering method. The amorphous layer ALa contains an oxide of at least one of, for example, indium (In), gallium (Ga), zinc (Zn) and tin (Sn). Subsequently, photolithography is carried out and thereafter, the amorphous layer ALa is etched to form the amorphous layer AL which covers only the top surface SCT of the semiconductor layer SC.

Next, as shown inFIG. 2, (c), the second insulating film12of, for example, silicon oxide is formed so as to cover the amorphous layer AL, the semiconductor layer SC and the first insulating film11using, for example, the plasma CVD. Subsequently, the gate electrode GE is formed on the second insulating film12, so as to correspond to, for example, the central portion of the semiconductor layer SC. That is, a metal layer is formed from a metal material such as copper, aluminum, titanium, molybdenum or tungsten or an alloy containing at least one of these using, for example, the sputtering method. Then, photolithography is carried out and thereafter the metal layer is etched to form the gate electrode GE.

Next, n-type impurity ions of, for example, phosphorus (P), are implanted to the semiconductor layer SC with use of the gate electrode GE as a mask. Thus, the source region SCa and the drain region SCb, which have high impurity concentration and low resistance, are formed. Further, the channel region SCc having an impurity concentration lower than and a resistance higher than those of the source region SCa and the drain region SCb are formed between the source region SCa and the drain region SCb, that is, in the region opposing the gate electrode GE. In the amorphous layer AL as well, impurity ions are implanted to the region where the source region SCa and the drain region SCb overlap, and thus the impurity concentration of the region (where with the source region SCa and the drain region SCb overlap) becomes higher than that of the region which overlaps the channel region SCc.

Next, as shown inFIG. 2, (d), the third insulating film13of, for example, silicon oxide is formed all over the first insulating film11using, for example, the plasma CVD. Subsequently, the contact holes CH1and CH2are formed in through the third insulating film13, the second insulating film12and the amorphous layer AL, so as to partially expose the source region SCa and the drain region SCb of semiconductor layer SC.

Next, on the third insulating film13, a metal material such as copper, aluminum, titanium, molybdenum or tungsten, or an alloy containing at least one of these is formed to embedded the contact holes CH1and CH2with the metal material using, for example, the sputtering method. Subsequently, the metal material is patterned to form the source electrode SE and the drain electrode DE connected to contact plugs in the contact holes CH1and CH2, and thus the thin-film transistor TR1shown inFIG. 1is formed.

Note that when the resistance of the amorphous layer AL exposed by the contact holes CH1and CH2is lower with use of, for example, silane gas, the contact holes CH1and CH2shown inFIG. 2, (d) or 1 need not be made through the amorphous layer AL. In this case, the contact plugs provided in the contact holes CH1and CH2are in contact with the amorphous layer AL made to have low resistance. The source electrode SE and the drain electrode DE are electrically connected to the semiconductor layer SC through the contact plugs provided in the contact holes CH1and CH2, respectively, and the amorphous layer AL.

In this embodiment, the second insulating film12covers all over the first insulating film11, but it suffices if the second insulating film12is formed directly under at least the gate electrode GE. In other words, the second insulating film12should only be formed at least in the region which overlaps the channel region SCc.

According to this embodiment, the amorphous layer AL is formed between the semiconductor layer SC and the second insulating film12. The amorphous layer AL has a function of flattening (planarizing) irregularities created on the surface of the semiconductor layer SC by the grain boundary of the semiconductor layer SC between the semiconductor layer SC and the gate insulating film. In other words, since the amorphous layer AL covers projections created in the grain boundary of the semiconductor layer SC, the gate electrode GE is formed in the location opposing the flattened (planarized) portion of the amorphous layer AL. With this configuration, as compared to the case where the second insulating film12is formed in contact with the projections created in the grain boundary of the semiconductor layer SC, the interface state produced in the boundary between the semiconductor layer SC and the second insulating film12can be suppressed. As a result, the sub-threshold characteristics of the thin-film transistor TR1can be improved, and the increase in leakage current flowing to the semiconductor layer from the gate electrode can be suppressed. Furthermore, the voltage resistance of the gate insulating film can be improved, thereby making it possible to improve the electrical characteristics of the thin-film transistor TR1.

Moreover, the thickness WAL of the amorphous layer AL is such a thickness that can cover the irregularities created on the surface of the semiconductor layer SC by the grain boundary of semiconductor layer SC, but sufficiently less than that of the semiconductor layer SC. With this configuration, the most of the current passing through the thin-film transistor TR1flows through the semiconductor layer SC. That is, the electrical characteristics of the thin-film transistor TR1is determined mainly by the semiconductor layer SC. Therefore, the thin-film transistor TR1of this embodiment can decrease the generation of the interface state, which is a problem specific to the thin-film transistors using polycrystalline silicon, while maintaining the high carrier mobility, which is also a feature of the thin-film transistors using polycrystalline silicon.

Second Embodiment

FIG. 3is a cross section schematically showing a thin-film transistor TR2according to the second embodiment. The second embodiment is different from the first embodiment in that the thin-film transistor TR2is a bottom-gate type. Hereafter, the main differences will be described.

A gate electrode GE is formed on a top surface10T side of the substrate10. In the example illustrated, it is formed on the first insulating film11. The gate electrode GE and the first insulating film11are covered by a second insulating film12. That is, the second insulating film12is in contact with the top surface GET of the gate electrode GE and the first insulating film11.

On the second insulating film12, an amorphous layer AL, for example, of TAOS is formed. In the example illustrated, the amorphous layer AL is in contact with an entire top surface12T of the second insulating film12. On the amorphous layer AL, a semiconductor layer SC formed from, for example, a low-temperature polycrystalline silicon, is formed. In the example illustrated, the semiconductor layer SC is in contact with an entire top surface ALT of the amorphous layer AL. Since the amorphous layer AL is interposed between the semiconductor layer SC and the second insulating film12, the semiconductor layer SC is separated from the second insulating film12.

On the semiconductor layer SC, a source electrode SE and a drain electrode DE are formed. The source electrode SE and the drain electrode DE are in contact with a top surface SCT of the semiconductor layer SC. The source electrode SE partially overlaps an end region of the gate electrode GE and the drain electrode DE partially overlaps the other end region of the gate electrode GE.

The relationship between a thickness WAL of the amorphous layer AL and a thickness WSC of semiconductor layer SC is similar to that of the first embodiment.

According to this embodiment, the amorphous layer AL is formed on the entire surface of the second insulating film12and the semiconductor layer SC is formed on the amorphous layer AL. That is, even with a bottom-gate thin-film transistor, it is possible to obtain an advantageous effect similar to that of the first embodiment by forming the amorphous layer AL between the semiconductor layer SC and the second insulating film12.

Third Embodiment

FIG. 4is a cross section schematically showing a thin-film transistor TR3according to the third embodiment. The third embodiment is different from the first embodiment in that the amorphous layer AL selectively covers the channel region SCc to expose the source region SCa and the drain region SCb. That is, the amorphous layer AL is formed in a region between semiconductor layer SC and the second insulating film12, which opposes at least the gate electrode GE. The second insulating film12is in contact with the top surface AL of the amorphous layer AL and also with the top surface SCT of semiconductor layer SC. The source electrode SE and the drain electrode DE are separated from the amorphous layer AL.

According to this embodiment, the amorphous layer AL is formed between the channel region SCc and the second insulating film12of the thin-film transistor TR3, and therefore an advantageous effect similar to that of the first embodiment can be obtained.

Fourth Embodiment

FIG. 5is a cross section schematically showing a thin-film transistor TR4according to the fourth embodiment.

The fourth embodiment is different from the second embodiment in that the amorphous layer is provided selectively between the source electrode SE and the drain electrode DE. In the example illustrated, both ends of the amorphous layer AL overlap the source electrode SE and the drain electrode DE, respectively. The semiconductor layer SC is in contact with the top surface ALT of the amorphous layer AL and also with the top surface12T of the second insulating film12.

In this embodiment as well, the amorphous layer AL is formed in a region equivalent to the channel region, that is, a region opposing the gate electrode GE and between the source electrode SE and the drain electrode DE, and therefore an advantageous effect similar to that of the first embodiment can be obtained.