PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE INCLUDING THE PRINTED CIRCUIT BOARD

A printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. A cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Terms and words used in the present specification and claims are not to be construed as a general or dictionary meaning, but are to be construed as meaning and concepts meeting the technical ideas of the present invention based on a principle that the inventors can appropriately define the concepts of terms in order to describe their own inventions in the best mode.

Throughout the present specification, unless explicitly described to the contrary, “comprising” any components will be understood to imply the inclusion of other elements rather than the exclusion of any other elements. A term “part,” “module,” “device,” or the like, described in the specification means a unit of processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software.

FIG. 3is a view showing a structure of a printed circuit board according to an exemplary embodiment of the present invention.

Referring toFIG. 3, the printed circuit board320′ according to the exemplary embodiment of the present invention is configured to include a base substrate321, a cavity321c,pads322pand an electronic component330. Here, the printed circuit board320′ including the electronic component330is substantially identical to a lower semiconductor package320of a semiconductor package to be described below.

The base substrate321includes a plurality of circuit patterns322,606and607. The base substrate321may have a single layer or multi layer structure. In the exemplary embodiment, the base substrate321of a multi layer structure will be described. Further, the circuit patterns322,606and607are formed on at least one of the upper surface and the lower surface, or the inside of the base substrate321. As shown in the drawing, in the base substrate321employed in the present invention, the circuit patterns322,606and607are formed on all of the upper and lower surfaces and the inside of the base substrate321.

The cavity321cis formed above the base substrate321. The cavity321cserves to mount an electronic component330(e.g., a semiconductor chip) therein. Further, an alignment pattern601may be formed on the lower portion of the sidewall of the cavity321cfor forming the cavity (seeFIG. 7A). The alignment pattern601is the remaining part of the protective layer601during the manufacturing process of the printed circuit board to be described below. The detailed description of which will be given below. The dimensions of the cavity321c,that is, the width and depth are variable depending on the width and depth of an electronic component330mounted therein and on the manufacturing specifications of a semiconductor package to be described below.

The pads322pare exposed through the substrate bottom surface of the cavity321cand are embedded in the base substrate321. The pads322pexposed through the bottom surface of the substrate are the top surfaces of the respective circuit patterns322. The upper surfaces of the pads322pand the bottom surface of the cavity321care in the same plane. The detailed description of which will be given below.

The electronic component330is mounted in the cavity321cand is electrically connected to the pads322p.Here, the electronic component330includes external terminals and is mounted in a face-down position in which the external terminals face the pads322p.

The printed circuit board according to the exemplary embodiment the present invention is preferably formed in the inside of the base substrate321, and may further include vias323,604and605electrically connecting the circuit patterns322,606and607to each other and the pads322pto the circuit patterns322,606and607.

Now, a manufacturing method of the printed circuit board according to the exemplary embodiment will be described.

For the sake of easy understating,FIG. 4which illustrates a semiconductor package will be described afterFIG. 5andFIGS. 6A to 6Eare described, which relate to a manufacturing method of the printed circuit board.

FIG. 5is a flowchart illustrating a manufacturing method of the printed circuit board according to the exemplary embodiment, andFIGS. 6A to 6Eare views sequentially illustrating the manufacturing processes of the manufacturing method of the printed circuit board according to the present invention.

Referring toFIG. 5andFIGS. 6A to 6E, in a manufacturing method of a printed circuit board according to the present invention, firstly, a first protective layer601for protecting circuits is formed on a predetermined region of an upper surface of a base substrate321(S501,FIG. 6A). The base substrate321may have circuit patterns322formed on its upper and lower surfaces and its inside, and vias323connecting the upper and lower circuit patterns322formed therein.

The first protective layer601may be formed by removing the protective layer formed on both surfaces of a detach core used in the early process, leaving only a predetermined region for forming the cavity321cto be described. Alternatively, the first protective layer601may be formed only on a predetermined region where the cavity321cis to be formed, including the circuit patterns on the upper surface of the base substrate321and adjacent insulating portion. As the material for the protective layer, a single metal or an alloy may be used. In some cases, non-metal material may also be used.

After the first protective layer601is formed, insulating layers602and603are formed on the upper surface where the first protective layer601is formed and on the lower surface, respectively (S502,FIG. 6B). As the material for the insulating layers602and603, synthetic resins (epoxy resins, polyester resins, urea resins, phenolic resins) may be used.

After the insulating layers602and603are formed, vias604and605are formed through the upper and lower insulators602and603, and then circuits606and607are formed on the upper surface of the upper insulator602and on the lower surface of the lower insulator603, respectively (S503,FIG. 6C). The vias604and605may be formed by forming holes in the upper and lower insulating layers602and603using a laser drill and then filling the holes with metal material (e.g., copper) by electrical plating. The circuits606and607formed on the upper and lower surfaces of the insulating layers602and603may be formed by performing photolithography using a mask.

After the circuits606and607are formed on the upper and lower surfaces of the insulators602and603, second protective layers608and609for protecting circuits may be formed, at the gaps between the circuits606and607, respectively (S504,FIG. 6D). As the material for the second protective layers608and609, solder resist may be used. Again, photolithography using a mask may be used for forming the second protective layers608and609.

After the second protective layers608and609are formed, a cavity321cfor mounting an electronic component330(shown inFIG. 3) is formed at a position in the upper insulating layer602where the first protective layer601has been formed (S505,FIG. 6E). Any one of wet etching and dry etching, preferably dry etching may be used for forming the cavity321c.

In forming of the cavity321c,the first protective layer601embedded in the upper insulating layer602is also removed, such that the top surfaces of the circuit patterns322exposed through the bottom of the cavity321care in the same plane with the bottom surface of the cavity321cwith no difference in level.

Since the plane of the circuits322exposed through the bottom of the cavity321cwhere the electronic component330is mounted is flat with the plane of the bottom of the cavity321c,an insulation distance may be formed high so that the electronic component330may be inserted into the cavity321c.Accordingly, it is easy to obtain the depth of the cavity321cwith relatively wide ranges (e.g., 40 to 150 μm) in the upper insulating layer602.

Further, in forming the cavity321c,as shown inFIG. 7A, a part of the first protective layer601may remain at the lower portion of the sidewall of the cavity321c.The remaining part of the first protective layer601may be used as an alignment mark to allow the electronic component330to be accurately mounted when the electronic component330is mounted in the cavity321cin the process of manufacturing a semiconductor package. As appreciated, the first protective layer601may be completely removed when the cavity321cis formed as shown inFIG. 7B.

Now, a description will be made referring back toFIG. 4.

FIG. 4is a view of a semiconductor package including the printed circuit board according to the exemplary embodiment shown inFIG. 3.

Referring toFIG. 4, the semiconductor package including the printed circuit board according to the exemplary embodiment of the present invention has a PoP structure that an upper semiconductor package310is stacked on an lower semiconductor package320.

The lower semiconductor package320includes a printed circuit board320′ having a cavity321cof a predetermined size formed on a part of the upper surface, and an electronic component330mounted in the cavity321c.

Further, the printed circuit board320′ is the one described above with reference toFIG. 3.

That is, the printed circuit board320′ includes the base substrate321, the cavity321cand the pads322p.

The base substrate321includes a plurality of circuit patterns322,606and607. The base substrate321may have a single layer or multi layer structure. Further, the circuit patterns322,606and607are formed on at least one of the upper surface and the lower surface, or the inside of the base substrate321. As shown in the drawing, in the base substrate321employed in the present invention, the circuit patterns322,606and607are formed on all of the upper and lower surfaces and the inside of the base substrate321.

The cavity321cis formed above the base substrate321. The cavity321cis formed to mount an electronic component330(e.g., a semiconductor chip) therein. Further, an alignment pattern601may be formed on the lower portion of the sidewall of the cavity321cfor forming the cavity. The alignment pattern601is the remaining part of the protective layer601during the manufacturing process of the printed circuit board. The dimensions of the cavity321c,that is, the width and depth are variable depending on the width and depth of an electronic component330mounted therein and on the manufacturing specifications of a semiconductor package to be described below.

The pads322pare exposed through the substrate bottom surface of the cavity321cand embedded in the base substrate321. The pads322pexposed through the bottom surface of the substrate are the top surfaces of the respective circuit patterns322. The upper surfaces of the pads322pand the bottom surface of the cavity321care in the same plane.

The electronic component330is mounted in the cavity321cand electrically connected to the pads322p.Here, the electronic component330includes external terminals and is mounted in a face-down position in which the external terminals face the pads322p.

The printed circuit board320′ according to the exemplary embodiment the present invention is preferably formed in the inside of the base substrate321, and may further include vias323,604and605electrically connecting the circuit patterns322,606and607to each other and the pads322pto the circuit patterns322,606and607.

As described above, according to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

Further, since the plane of circuits exposed through the bottom surface of the cavity in which an electronic component is mounted is flat with the bottom surface of the cavity, an insulation distance may be formed high so that the electronic component may be inserted into the cavity. Accordingly, it is easy to obtain the depth of the cavity with relatively wide ranges in the upper insulating layer.

As stated above, according to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

Although the exemplary embodiments of the present invention have been disclosed for illustrative purposes, the present invention is not limited thereto, but those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Therefore, the true scope of the present invention to be protected should be defined only by the appended claims and it is apparent to those skilled in the art that technical ideas equivalent thereto are within the scope of the present invention.