Method for placing a device in a selected mode of operation

A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 09/523,610, filed Mar. 13, 2000 now U.S. Pat. No. 6,681,332, and allowed on Aug. 21, 2003, entitled SYSTEM AND METHOD TO PLACE A DEVICE IN POWER DOWN MODES/STATES AND RESTORE BACK TO FIRST MODE/STATE WITHIN USER-CONTROLLED TIME WINDOW.

FIELD OF THE INVENTION

This invention relates generally to serial communication interfaces, and is more particularly directed toward utilizing a read-only serial interface to select an operating mode for a device.

BACKGROUND OF THE INVENTION

The popularity of battery-operated equipment, and the demand for smaller integrated circuit devices having lower power consumption (with consequent longer periods between battery replacement or recharging), has given rise to a need for reducing power consumption in the devices used in such equipment. One technique that has been developed involves supplying full power to a device during periods of so-called “normal” operation, and placing the device in a low power consumption mode (sometimes referred to as “inactive,” “power down,” or “sleep” mode) during intervening non-operating periods.

U.S. Pat. No. 5,619,204 describes an analog-to-digital converter (ADC) with optional low power mode that is controlled by monitoring the state of a “conversion start” (CONVST) signal with respect to the conversion completion point. U.S. Pat. No. 5,714,955 ('955 Patent) describes dual function control circuitry for effecting the switchover between operating modes of a serial ADC. The control signals used to trigger this switchover between operating modes are signals associated with the conversion process and not with the serial data transfer.

FIG. 1is a block diagram of an ADC of the prior art (generally depicted by the numeral100) that is configured to accommodate operating mode programming, in this case for power-down mode control. A CLK (clock) signal101is used to synchronise the conversion operation, and a CONV (conversion) signal102is used to initiate the conversion operation. The CLK101and CONV102signals are provided as inputs to internal control logic103that controls operation of the SAR (successive approximation register) and parallel to serial converter logic104. The serial output data108of the device100is derived by shifting out the SAR contents serially after the conversion is complete.

The CLK101and CONV102signals also serve to produce power-down and power-up commands. They thus serve as dual-function pins. However, these signals do not produce these power-up and power-down commands when operating in the usual manner across the serial interface. The manner in which these signals must be asserted with respect to each other is not easily configured over a standard serial interface, and cannot provide power-down and power-up commands when standard serial communication is taking place. Instead, the signals are asserted as shown in the timing diagram ofFIG. 2.

When CLK201is low, two CONV202pulses command the ADC to enter a first power-down mode, in this case a reduced power consumption mode denominated the NAP mode203. When CLK201remains low, two additional CONV202pulses are required to place the part in a second power-down mode, in this case the SLEEP mode204, consuming even less power than the NAP mode203. The timing of CONV and CLK are not easily generated over a standard serial interface with a microcontroller, and are not available from a DSP in the manner required.

The closest known practice exists in a family of serial ADCs manufactured by Analog Devices, Inc. Shutdown is controlled via the state of “chip select” (CS) when the device is in read-only mode. When CS is low, the device is fully powered up, and when CS is high the device is fully powered down. This means that shutdown is enforced after each conversion, and so the required power-up time must be allowed before each conversion, slowing down the overall throughput of the device. Conventional ADC circuits typically use a dedicated input in order to implement a power-down function, and this utilization of single-purpose inputs extends to mode-control programming generally. This requirement for a dedicated input increases the number of lines in the chip package.

A need thus arises for a mode control implementation that does not require a dedicated input or complex, multi-line protocol, and thus does not interfere with device throughput.

SUMMARY OF THE INVENTION

These shortcomings of the prior art, and others, are addressed using the versatile mode programming of the present invention. The read-only serial interface can be used to place an ADC or other integrated circuit device in one or more power-down modes without writing to a control register or using a dedicated shut-down pin. Other operating modes not specifically related to power saving can also be controlled in this way. Mode control utilizing the interface described herein involves monitoring the state of CS with respect to the system clock (SCLK). After the falling edge of CS, shut-down is detected by checking the point where CS returns to a logic high during the following set of 16 SCLKs. Subsequent power-up is detected in the same way.

Three modes of operation related to power consumption are provided. These are the Fully-Powered Mode, Partial Power-Down Mode, and Full Power-Down Mode. In the Fully-Powered Mode, all portions of the device are fully powered at all times, so this mode of operation yields fastest device throughput but increased power consumption.

In the Partial Power-Down Mode of operation, power is removed from most portions of the device except when a conversion has been initiated. The Partial Power-Down Mode requires an extra conversion cycle for the first conversion performed, so device throughput is reduced in return for reduced power consumption.

In Full Power-Down Mode, all analog circuitry on the device is powered down. This mode of operation is intended for applications in which power conservation is of the utmost importance. Device throughput is relatively low in Full Power-Down Mode, primarily because of the extended time periods required both to place the device in Full Power-Down and to “wake it up” again.

Of course, as noted above, control of other operating modes for a device can also be implemented using this technique. The basic principle of changing the mode in response to a pre-determined number of logic state transitions at the clock input occurring between logic state transitions at the device select input remains the same. In an exemplary embodiment of the present invention, operating mode control capability includes not only power control, but also adds the ability to change the operating mode from stand-alone to daisy chain mode. In daisy chain mode, multiple devices are connected together in serial fashion. If the chip select pin is taken high between the 10th and the 13th falling clock edges, for example, then the part enters a daisy chain mode.

Many other extensions to this protocol are possible. For example, a device may decode the result of the device select pin going high after any number of clock edges, (not even limited to the 16 required for data transfer), where each position of this transition is associated with a unique operating mode. Yet another implementation uses the technique described above to place the device into a mode where the next time CS goes low, data present at a selected device pin may be loaded into an internal register. In yet a further implementation, analog input voltage range may be controlled when a different number of logic state transitions are allowed to occur between transitions of the device select input.

In accordance with the invention, a method is provided for placing a device in a selected mode of operation, which may, for example, be a reduced power consumption mode of operation, or another operating mode, such as a DAISY CHAIN mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. In one form of the invention, the step of initializing a device select signal further comprises the step of placing the device select signal into an inactive logic state. The inactive logic state may comprise a HIGH logic state. The step of asserting the device select signal further comprises the step of placing the device select signal into an active logic state, which may comprise a LOW logic state.

In one form of the invention, the device includes a clock signal input and the step of returning the device select signal to the first logic state within a first user-controlled time window further comprises the step of returning the device select signal to the first logic state after the occurrence of a first transition of the clock signal, but before the occurrence of a second subsequent transition of the clock signal. The first transition of the clock signal preferably comprises the second falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state, while, for a reduced power consumption mode of operation, the second subsequent transition of the clock signal comprises the tenth falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state.

It should be noted that the term “first transition” of the clock signal does not necessarily mean the clock signal's first measurable activity, nor does the term “second transition” necessarily characterize the immediately subsequent clock signal activity. As recited above, the first transition is preferably the second falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state, while the second transition is preferably some subsequent falling edge of the clock signal that occurs after assertion of the device select signal in a second logic state. It should be apparent that the precise temporal position of the second transition is determined by a user-controlled time window dependent upon the operational mode programming being effected. This user-controlled time window is measurable in terms of the number of clock cycles occurring between these transitions.

In accordance with another aspect of the invention, the device is restored to normal mode by the additional steps of asserting the device select signal in the second logic state, and returning the device select signal to the first logic state within a second user-controlled time window. The second user-controlled time window is defined by at least ten falling edges of the clock signal.

In accordance with yet another aspect of the invention, a method is provided for placing an integrated circuit device having a chip select (CS) input and a clock (CLK) input into a selected mode of operation. The method comprises the steps of controlling the CS input of the device to place the CS input into an initial inactive logic state, placing the CS input into an active logic state to select the device, and, within a first user-controlled time window defined by transitions of the CLK signal, returning the CS input to the initial inactive logic state. The initial inactive logic state may be a HIGH logic state, while the active logic state may be a logic LOW state.

In accordance with a further aspect of the invention, the first user-controlled time window defined by transitions of the CLK signal comprises a time window beginning with the second falling edge of the CLK signal that occurs after CS is placed in an active logic state, and, for reduced power consumption mode of operation, ending with the tenth subsequent falling edge of the CLK signal that occurs while CS is in the active logic state. In one form of the invention, the device is restored to normal mode by the additional steps of placing the CS input into the active logic state to select the device, and, within a second user-controlled time window defined by transitions of the CLK signal, returning the CS input to the initial inactive logic state. Preferably, the second user-controlled time window is defined by at least ten falling edges of the CLK signal.

In accordance with another embodiment of the invention, a device comprises means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a user-controlled number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. In one form of the invention, the means for detecting logic state transitions at a device select input and a clock input further comprises clock divide logic and counter circuitry coupled to the serial clock signal and the device select signal, the clock divide logic and counter circuitry generating intermediate control signals including a first intermediate control signal that occurs after the second falling edge of the serial clock signal and a second intermediate control signal that occurs after the tenth falling edge of the serial clock signal.

In another aspect of the present invention, the means for changing operating mode of the device places the device in a first selected mode of operation in response to a first combination of logic state transitions, and places the device in a second mode of operation in response to a second combination of logic state transitions. The first combination of logic state transitions comprises between two and ten logic state transitions at the clock input, occurring between logic state transitions at the device select input, while the second combination of logic state transitions comprises at least ten logic state transitions at the clock input, occurring between logic state transitions at the device select input.

In accordance with yet another aspect of the invention, an analog-to-digital converter comprises means for converting an analog input signal into a corresponding digital signal in response to a control signal, means for outputting the corresponding digital signal in serial form in response to a serial clock signal, means for generating at least one command signal in response to a number of serial clock signal cycles occurring between changing states of the control signal, and means for selecting an operating mode of the analog-to-digital converter in response to the command signal.

In yet a further aspect of the invention, the means for converting an analog input signal into a corresponding digital signal further comprises a track and hold circuit coupled to the analog input signal, and a successive approximation ADC coupled to the track and hold circuit. The means for outputting the corresponding digital signal further comprises a data multiplexer coupled to the means for converting the analog input signal, and to the serial clock signal, and a serial data output coupled to the data multiplexer.

In another form of the invention, the means for generating at least one command signal further comprises clock divider and counter logic coupled to the serial clock signal and the control signal, wherein the clock divider and counter logic generates a plurality of command signals conditioned, at least in part, by the number of serial clock signal cycles occurring between changing states of the control signal. The means for selecting an operating mode of the analog-to-digital converter further comprises control and power management logic coupled to the control signal and the clock divider and counter logic.

In accordance with still another aspect of the present invention, an integrated circuit subsystem comprises a plurality of integrated circuit devices each having a signal input and a signal output, the devices interconnected such that a signal output of a preceding device is coupled to a signal input of a subsequent device, and the integrated circuit devices share common device select and serial clock input signals, and control circuitry coupled to the device select and serial clock input signals, the control circuitry placing the plurality of integrated circuits into a DAISY CHAIN mode of operation in response to a user-controlled number of logic state transitions of the serial clock input signal occurring between logic state transitions of the device select signal.

In yet a further aspect of the invention, an analog-to-digital converter having an analog input signal and a digital output signal corresponding to a digital representation of the analog input signal comprises a conversion subsystem that converts the analog input signal into the digital output signal, and a range programming subsystem responsive to a device select input signal and a serial clock input signal. Full-scale input voltage range of the analog-to-digital converter is selected from among a plurality of full-scale input voltage ranges in response to a user-controlled number of logic state transitions of the serial clock input signal occurring between logic state transitions of the device select signal.

Further objects, features, and advantages of the present invention will become apparent from the following description and drawings.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with the present invention, a read-only serial interface is used to place an integrated circuit device in a selected operating mode. The present invention provides distinct advantages when compared to mode control methodologies known in the prior art.

An example of an ADC integrated circuit having operational mode control in accordance with one form of the present invention is shown in simplified block diagram form inFIG. 3, and generally depicted by the numeral300. The ADC300includes a track and hold circuit301for acquiring an analog input voltage302. A 12-bit successive approximation register (SAR) ADC303converts the analog input signal302into a corresponding digital signal. The integrated circuit300includes control logic304that controls the operation of the other components of the integrated circuit300, and also includes power control circuitry for selectively applying/removing power from portions of the device, although this power control circuitry is not illustrated in the simplified block diagram ofFIG. 3.

The control logic304also functions as a conversion circuit for outputting the corresponding digital signal in serial form (SDATA)305in response to a serial clock input (SCLK)306. The control logic304further includes a monitoring circuit that generates internal control signals in response to the number of SCLK cycles occurring between states of the chip select (CS) input signal307. These internal control signals control power-down mode operation, and will be discussed in more detail subsequently.

FIG. 4is a detailed timing diagram illustrating serial communication with the ADC300ofFIG. 3. The serial clock SLK401provides the conversion clock and also controls the transfer of information from the ADC300during conversion. CS (chip select)402initiates the data transfer and conversion processes. The falling edge of CS402puts the track and hold into hold mode, takes the SDATA output403out of the high impedance state, and the analog input is sampled at this point. The conversion is also initiated at this point, and requires 16 SCLK401cycles to complete. It should be noted that the SDATA output403is in a high impedance, “third” logic state when the ADC300is not performing a conversion, and also when the device has completed a serial data transfer. This third logic state is sometimes called “3-state,” there being three possible conditions: logic HIGH, logic LOW, and high impedance.

On the 16th SCLK401falling edge, the SDATA (serial data) line403goes back into 3-state. If the rising edge of CS occurs before 16 SCLK active edges have occurred, the conversion is terminated and the SDATA line goes back into 3-state, otherwise SDATA returns to 3-state on the 16th SCLK falling edge as shown. Sixteen serial clock cycles are required to perform the conversion process and to access data from the ADC300.

While the active edge of SCLK401is the falling edge, or the HIGH-to-LOW logic transition, in the preferred form of the invention, a system could easily be configured to employ either the falling or rising edge of SCLK as the active edge. Similarly, in the preferred embodiment of the invention, the CS signal402selects the ADC300when CS402is in a LOW logic state, but an ADC300in accordance with the present invention could also be made responsive to a HIGH logic level on CS402if design considerations so dictated.

The first serial clock falling edge following CS going low (point A) provides the first data bit to be read in by the microcontroller or DSP that interfaces with the ADC300. This SCLK falling edge also clocks out the second data bit, thus the second falling clock edge on the serial clock has the second data bit provided. The final bit in the data transfer is valid on the sixteenth falling edge, having been clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge.

There are three possible modes of operation: Fully-Powered Mode, Partial Power-Down Mode, and Full Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated, combined with the previous operating mode, determines which of the three operating modes the device will assume.

These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. Choosing the mode of operation can be done with either a standard 8 SCLK burst or a standard 16 SCLK burst from a microcontroller or other form of programmable device. Of course, depending upon the capabilities of a particular microcontroller to accommodate multiple-byte serial data transfers, two standard 8 SCLK bursts or a single 16 SCLK burst may be required. If a DSP or other programmable device is used to provide the interface to the ADC300, the programmable device can be programmed to provide a SCLK sequence of any desired length within the device select active window.

The fully-powered mode of operation is intended for fastest throughput rate performance, as the user does not have to worry about any power-up times (the ADC300remains fully powered all the time).FIG. 5is a timing diagram that depicts the ADC300in its fully-powered mode of operation. A conversion is initiated on the falling edge of CS as described previously. To ensure the ADC300remains fully powered up at all times, CS501must remain low until at least 10 SCLK502falling edges have occurred after the falling edge of CS501. The 10th SCLK502occurs at point B ofFIG. 5.

If CS501is brought high any time after the 10th SCLK502falling edge, the ADC300will remain powered up. If fewer than 16 SCLK502falling edges have elapsed when CS501is brought high, the conversion will be terminated and SDATA503will go back into 3-state. If 16 or more SCLK502falling edges are applied to the ADC300while CS501is low, then the conversion will terminate on the 16th SCLK502falling edge, putting SDATA503back into 3-state at this point. Sixteen serial clock cycles502are required to complete the conversion and access the conversion result. (CS501may idle HIGH until the next conversion, or may idle LOW until sometime prior to the next conversion, effectively idling CS LOW). Once a data transfer is complete (SDATA503has returned to 3-state), another conversion can be initiated after the quiet time, tquiet, has elapsed by bringing CS501LOW again from its previous HIGH logic state.

The Partial Power-Down Mode is intended for use in applications where lower power consumption is required, and slower throughput rates still meet system requirements. Either the ADC300is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC300is powered down for a relatively long duration between these bursts of several conversions. When the ADC300is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer.

To enter Partial Power-Down Mode from Fully-Powered Mode, the conversion process must be interrupted by bringing CS601high anywhere after the second falling edge of SCLK602and before the tenth falling edge of SCLK602as shown in the timing diagram ofFIG. 6. Once CS601has been brought high in this window of SCLKs, then the ADC300will enter partial power-down, the conversion that was initiated by the falling edge of CS601will be terminated, and SDATA603will go back into 3-state. If CS601is brought high before the second SCLK602falling edge, then the ADC300will remain in Fully-Powered Mode and will not power down. This will avoid accidental power-down due to glitches on the CS line.

A dummy conversion is performed in order to exit this partial power-down mode of operation and power the ADC300up again, as shown inFIG. 7. On the falling edge of CS701, the ADC300will begin to power up and will continue to power up as long as CS701is held low until after the falling edge of the tenth SCLK702, as shown at point A. The device will be fully powered up once 16 SCLKs702have occurred, and valid data703will result from the next conversion. If CS701is brought high before the second falling edge of SCLK702, then the device will go back into partial power-down mode again. This avoids accidental power-up due to glitches on the CS line. Even though the device may begin to power up on the falling edge of CS701, it will power down again on the rising edge of CS701if the rising edge of CS701occurs before the second falling edge of SCLK702. If the ADC300is in partial power-down mode before CS701is brought low, and CS is subsequently brought high between the second and tenth falling edges of SCLK, then the device will enter Full Power Down.

The Full Power-Down Mode is intended for use in applications where still lower power consumption is required, and even slower throughput rates (still consistent with operational requirements) can be tolerated. Of course, the throughput constraints of this mode are evident, since power-up from a full power-down cannot be completed in one dummy conversion alone. This mode is more suited to applications where a single or a series of high speed conversions is followed by a long period of inactivity, and hence power-down. When the ADC300is in full power-down, all analog circuitry is powered down.

Full Power-Down is entered in a way similar to partial power down, except the timing sequence depicted inFIG. 6must be executed twice, as depicted in the timing diagram ofFIG. 8. The conversion process must be interrupted in a similar fashion by bringing CS801high anywhere after the second falling edge of SCLK802and before the tenth falling edge of SCLK. The device will enter partial power-down at this point. To reach full power down, the next conversion cycle must be interrupted in the same way. Once CS801has been brought high in this window of SCLKs (interval B), then the ADC300will power down completely. It is not necessary to complete the 16 SCLKs802once CS801has been brought high to enter a power-down mode.

To exit Full Power-Down and power the ADC300up again, a dummy conversion is performed just as when powering up from partial power-down. The exit from full power-down mode is shown in the timing diagram ofFIG. 9. On the falling edge of CS901, the device will begin to power up, and will continue to power up as long as CS901is held low until after the falling edge of the tenth SCLK902, which occurs at point C. The power-up time is longer than one dummy conversion cycle, however, and this time must elapse before a conversion can be initiated once again.

FIG. 10is a detailed block diagram of the ADC illustrated inFIG. 3. The ADC300uses a successive-approximation architecture based on 16 SCLK pulses, active on the falling edge. A conversion is initiated by CS307going LOW, which puts the ADC300into hold. The bit trials are driven by SCLK, which drives a Johnson Counter1001. The Johnson Counter1001performs two duties. It must control both the bit trials and the serial data output by addressing the SAR1002and the 12:1 data output multiplexer1003respectively.

The bit trials commence on the 2nd falling edge of SCLK306, which decides the most significant bit, or MSB (DB11), and finish on the LSB (DB0) decision on the 13th falling edge. SCLK306also provides the edges required for clocking out the serial data305. In this particular embodiment, the first four SCLKs clock out leading zeroes, followed by the MSB value and so on through to the LSB.

Generation of internal control signalling is depicted inFIG. 11. Signal csb1101is the start conversion signal. A falling edge on csb1101initiates a conversion, and if the conversion is not complete when this line goes HIGH it will be aborted. The system clock (SCLK) clocks a counter (not shown) that counts the number of falling edges on SCLK after csb1101has been taken LOW. After two such clock edges, the signal after_21102goes HIGH for one SCLK cycle before going LOW again on the 3rd clock edge. The signal after_101103is similarly set after ten SCLK edges during a conversion, and is cleared on the eleventh falling edge of SCLK.

There are two outputs from the control signal generating logic. The sleep signal1104, when HIGH, shuts down the comparator1004(FIG. 10) and puts the reference buffer1005into a low current mode. This is partial power-down. A full shut-down is achieved when all the analog circuitry, including the bias generator1006, is shut down. This happens when both sleep1104and deep_sleep1105are driven HIGH. When both deep_sleep1105and sleep1104are LOW, then the ADC300is fully powered up. The ADC300is never in a power-down mode during a conversion. It can only enter a power-down mode by aborting a conversion in progress.

csb1101is inverted once by inverter x11106to become conv_abortb1107. conv_abortb1107is inverted by x21108to become conv_abort_slow1109. conv_abort_slow1109is used primarily to force the signals deep_sleep1105and sleep1104LOW when csb1101is itself LOW. This means that when csb1101goes LOW, which starts a conversion, the ADC300is always powered up, regardless of any mode that it was in previously. The new sleep mode only takes effect when conv_abort_slow1109goes HIGH. The power-down mode that the ADC300will enter is selected when csb1101is brought HIGH during a conversion. This corresponds to a falling edge on conv_abortb1107.

The signal conv_abortb1107changes the current power-down mode by setting the signal latch_mode1110, the output of NOR gate x61111. latch_mode1110will only be permitted to go HIGH if the signal glitch_block1112is LOW. When latch_mode1110goes HIGH, the flip-flop x101113will update its output Q, dp_slp_mode1114, and the latch x91115will store its current D input value at its output Q, slp_mode1116.

The signal glitch_block1112is required to prevent the ADC300from entering a different power-down mode due to glitches on csb1101. The glitch protection circuit is made up of inverter x51117driven by S-R latch SR11118. SR11118is implemented by cross-connected NOR gates x31119and x41120. The SET signal of the S-R latch, after_21121, is normally LOW: it goes HIGH when a conversion is started (csb1101LOW), and two SCLK falling edges have been recognized by the ADC300. after_21121goes LOW again on the third SCLK falling edge. A HIGH signal on after_21121causes the S-R latch output to be SET, which causes glitch_block1112to go LOW via inverter x51117. At this point, the signal latch_mode1110is no longer held LOW by x61111, but is allowed to go HIGH when conv_abortb1107goes HIGH, clocking the latch x91115and flip-flop x101113.

Until glitch_block1112goes low, a glitch on csb1101that causes it to go momentarily HIGH then LOW (i.e., HIGH then LOW within two SCLK active edges), mimicking an aborted conversion, will not cause the power management mode to be changed in error, as the storage elements x91115and x101113will see no change to their clk inputs. When csb1101goes HIGH to signal the end of a conversion, conv_abort_slow1109will go HIGH, which resets the S-R latch SR11118, ensuring that further glitches do not cause the ADC to enter the wrong mode.

The latch output slpmode_set1122determines which mode the ADC300should enter the next time csb1101is brought HIGH. If slpmode_set1122is 0 then the ADC will remain powered up at the end of conversion. If slpmode_set1122is 1, then the ADC300will enter one of its two sleep modes, depending on the previous mode before a conversion was initiated. The value of slpmode_set1122is determined by the two signals after_21102and after_101103via S-R latch SR21123. If a conversion is started and two SCLK signals have been recognised by the ADC300, then the signal after21102will go HIGH on the second falling edge of SCLK for one clock cycle, setting the output of SR21123. SR21123will remain set until the signal after_101103has gone HIGH to reset it. After_101103will go HIGH for one clock cycle when the ADC300has counted ten SCLK falling edges inside a csb LOW pulse. This will cause the value of slpmode_set1122to go HIGH.

The signals slp_mode1116and dp_slp_mode1114remember which mode the ADC300was in just before csb1101started a new conversion. As explained, slp_mode1116and dp_slp_mode1114are prevented by the glitch blocking circuitry from changing the power management mode, until after the second clock pulse within a conversion has been recognised by the ADC300. If more than two SCLK edges have elapsed within a conversion, then the glitch rejection circuitry is disabled and the interface is free to change the power-down mode when csb1101is brought HIGH. Both storage elements x91115and x101113are clocked by the rising edge on latch_mode1110when csb1101is brought HIGH. When this happens, dp_slp_mode1114assumes the old value of slp_mode1116, and slp_mode1116assumes the old value of slpmode_set1122.

If the ADC300is in fully-powered mode and the user wants to put it into partial power-down mode, then csb1101must be taken LOW, and between two and ten serial clock cycles must be supplied before bringing csb back HIGH. On the second clock pulse during the conversion, slpmode_set1122will be set to a 1 by SR21123and the glitch reject circuit will be disabled. If csb1101is brought HIGH before the 10th SCLK pulse, then dp_slp_mode1114will remain unchanged (LOW) and slp_mode1116will assume its new HIGH value. When conv_abort_slow1109goes HIGH, it releases x13's1124output from being held HIGH. The output of x131124will then go LOW causing sleep1104to go HIGH. deep_sleep1105will still be LOW at this point.

If this process above is repeated, then on the rising edge of latch_mode1110the old value of slp_mode1116(which was HIGH) will be clocked through to dp_slp_mode1114, which sets deep_sleep1105once conv_abort_slow1109has gone HIGH. slp_mode1116itself will be HIGH, forcing sleep1104HIGH in the same way. If both sleep1104and deep_sleep1105are HIGH, then all of the analog circuitry will be powered down once csb1101returns to a HIGH level.

Taking the ADC300out of power-down requires slpmode_set1122to be cleared before the conversion is aborted. This is achieved by waiting more than ten SCLK edges in a conversion before bringing csb1101HIGH. If csb1101is brought HIGH after ten SCLK edges have passed, then slp_mode1116will go LOW, which also resets the Q output of x101113. Both sleep1104and deep_sleep1105will stay LOW when conv_abort_slow1109goes HIGH, leaving the ADC300powered up.

As noted previously, operational mode control using the read-only serial interface is not limited to placing a device in a reduced power consumption mode of operation. Other device operating modes can also be selected using this interface.FIG. 12is a block diagram of a device in which more than one operational mode can be programmed.

Counter1209is similar to counter1001described with reference toFIG. 10. Just as inFIG. 10, counter1209ofFIG. 12is used to count clocks and control the bit trials. The counter1209counts up to 16. Very little additional circuitry is needed to decode other conditions. A simple latch circuit included as part of Mode Selection Logic1205is set on the 10thfalling clock edge and reset on the 13th falling clock edge. If the device select pin307transitions high while the output of the latch is set, then the device changes modes.

As a result, the operational state of the device changes from the normal mode (where the device performs a conversion and outputs the result), to a mode where the part outputs data that occurred on the SDATA pin120116 clock cycles earlier. This allows users to daisy chain any number of parts together so that the data from all the parts will be read into one serial input port on an associated processor. Effectively, the interconnected devices (ADCs in this case) become a serial shift register. The serial data stored in each part of this register, prior to shifting, is the result of the most recent conversion of that particular ADC. Multiplexer1206selects between the daisy chain data and the conventional conversion result.

Operation of a plurality of devices in the daisy chain mode of operation involves three control signals as described below, and interconnection of the SDATA and DOUTsignals in a daisy chain as illustrated inFIG. 14. The control signals provided externally are the serial clock signal SCLK306and the chip select signal (actually, its complement CSB, or chip select bar,307). A shift signal enabling the serial shifting of data from one device to another is generated internally by an appropriate CSB transition. Thus, the daisy chaining protocol described herein requires only two externally generated control signals.

FIG. 14illustrates four devices1403–1406connected in daisy chain mode. The SDATA signal1201is coupled to the first device1403, with the data out signal DOUT of the first device1403coupled to the SDATA input of device two1404. DOUTfrom the last device1406is the output signal for the system. A collection of analog input signals1401is provided for the aggregate devices.

Considering a single device under normal operation, the channel for the next conversion is read in the SDATA pin on the third bit (CHNI) as illustrated by the input data word format ofFIG. 15. The output data word format ofFIG. 16shows that CHNoindicates the channel just converted and the MOD and STY bits in the input and output data words are used as daisy chaining indicators and commands.

As noted previously, each device has the capability to operate in a number of distinct modes. Of particular interest in this portion of the discussion are the NORMAL and DAISY CHAIN modes of operation. As discussed with respect to device operation above, in NORMAL mode, the conversion result is copied into an internal shift register on the 13thSCLK edge. The user can tell the device is in this mode when the MOD bit equals the CHNobit.

FIG. 13is a logic diagram illustrating generation of internal control signals for the device ofFIG. 12. The circuitry1306to1309, plus associated gates, detects whether the CHN and STY bits in the serial data (SDATA) word are the same or different. Signals CHN_bit_b and STY_bit_b go low for the clock cycles that the CHN and STY bits are valid in the serial data (SDATA) word, respectively.

Logic gate1306and D-type flip-flop1307monitor the CHN and STY bits. The QB output of flip-flop1307STY ≠CHN (STY NOT EQUAL TO CHN) is HIGH if the CHN and STY bits are different, and LOW if they are the same. The signal STY ≠CHN needs to be HIGH for the part to remain in DAISY CHAIN mode.

D-type flip-flop1303and associated gates determine which mode (NORMAL or DAISY CHAIN) that the part is in. To enter DAISY CHAIN mode initially, the circuit requires that the device be in NORMAL mode and stconv (inverse of CSB) transition low between the 10th and 13th clock edges. To remain in DAISY CHAIN mode, the circuit requires that the device already be in DAISY CHAIN mode, the device must receive more than 13 clock edges in the CSB low time, and the STY bit must be the inverse of the CHN bit.

When the operational mode is changed to DAISY CHAIN, each device1403–1406(FIG. 14) operates as a shift register. When all the devices are in DAISY CHAIN mode, every 16 SCLK cycles and one CSB frame (one read cycle) results in the data stored in each internal shift register being shifted one device to the right. For the configuration ofFIG. 14in DAISY CHAIN mode, if one applies four read cycles, the data from all four devices will appear at the system DOUTpin in sequence, and one may also write individual control words to the SDATA pin1201, which will come to rest with one such control word in each device, so each device1403–1406now has an individual channel assigned to it.

To change between modes, a conversion is performed where the CSB input goes high in bits10/11/12(i.e. after the 10thSCLK falling edge and before the 13thSCLK falling edge). The user can see which mode the device is in by looking at the MOD bit. If MOD=CHNothe device is in NORMAL mode, and if MOD equals the inverse of CHNothe device is in DAISY CHAIN mode. A conversion with the input STY bit equal to the CHNIbit while the device is in DAISY CHAIN mode forces the device back into NORMAL mode. This means that if the channel is selected by tying SDATA HIGH or LOW, the device will not get stuck in DAISY CHAIN mode. These mode changes are summarized in the state transition diagram ofFIG. 17, with the mode and output bit states shown in each state circle1701,1702, and the CSB, SDATA conditions for a transition given on the state transition vectors1703–1707.

A timing diagram for system operation is provided inFIG. 18, with a time scale for system events, in microseconds (μs), provided on the horizontal axis. It can be appreciated that, in interval A (between seven and eight μs) that a normal conversion is being performed, with every device on its selected channel and the result stored in each device's internal shift register.

During interval B (eight to nine μs), a mode change is signalled, with a CSB HIGH event occurring between bits10and12as shown on CSB timeline1801. This transition switches each interconnected device into DAISY CHAIN mode. A read cycle operation occurs during interval C, between 9 and 10 μs, wherein each device reads in one word through its SDATA pin and outputs the conversion performed during interval A through its DOUTpin. This process of taking CSB low, applying16clock cycles, then returning CSB high, continues until all data words have been read.

The block diagram ofFIG. 19illustrates yet another embodiment in accordance with the present invention. This implementation includes an input range control capability in which the input full-scale voltage is selected using the procedure outlined above.

It is known that by sampling onto a capacitor that is smaller than the DAC capacitance, the input voltage required to obtain full scale is increased. For example, by sampling onto a capacitor equal to one-half the DAC capacitance, full scale output is obtained for an input signal having an amplitude that is twice the reference voltage.

In this example, the mechanism for changing ranges is the same technique described previously of counting clock edges while the device select input is in a user defined state. If the CSB input307is taken LOW (to its active state) and 11 cycles are applied to the clock input SCLK306before CSB307is taken HIGH again, then the device ofFIG. 19is designed to enter an operating mode in which full scale corresponds to the reference voltage. If, on the other hand, 12 serial clock cycles are applied to the SCLK306input between CSB307transitions, then the device enters an operating mode in which full scale corresponds to twice the reference voltage.

Of course, the number of cycles occurring on SCLK may be selected by design to be any workable number. The numbers introduced in the prior paragraph are intended to be examples only. Anyone skilled in the art will quickly understand that through the introduction of appropriate hardware, the full-scale voltage can be selected as virtually any multiple of the reference voltage. Of course, added complexity may outweigh any benefit derived if additional hardware is allowed to become too cumbersome.

There has been described herein a read-only serial interface used to place an integrated circuit device in a selected operating mode. The inventive system demonstrates distinct improvements over the prior art. It will be apparent to those skilled in the art that modifications may be made without departing from the spirit and scope of the invention. Accordingly, it is not intended that the invention be limited except as may be necessary in view of the appended claims.