Interconnecting structure for semiconductor integrated circuits and method

An interconnecting structure for a semiconductor integrated circuit and a method for manufacturing said interconnecting structure. The interconnecting structure comprises a top layer, a bottom layer, and a dielectric isolation layer. The top layer completely covers and encloses the bottom layer. The dielectric isolation layer is disposed between the top layer and the bottom layer. At least one contact opening is formed through the top layer of the structure, thereby exposing a selected region of said bottom layer. A contact is formed on the selected region of the bottom layer.

FIELD OF THE INVENTION 
This invention relates generally to semiconductor integrated circuits, and 
more particularly to an interconnecting structure for semiconductor 
integrated circuits. 
BACKGROUND OF THE INVENTION 
Interconnecting structures for interconnecting layers of semiconductor 
material are typically employed in semiconductor integrated circuits. A 
prior art interconnecting structure is shown in FIG. 1 and comprises a 
bottom layer 12 crossed by a top layer 10, with contacts 22 formed on the 
bottom layer 12 at a lateral distance from the top layer 10, and a 
dielectric insulating layer 20 (not shown) separating the two layers 10, 
12. 
FIG. 2 shows a section taken along line A--A of FIG. 1. Besides the top 
layer 10 and the underlying bottom layer 12, the dielectric isolation 
layer 20 between the two layers 10, 12 can be seen, which isolates the two 
layers 10, 12 from each other. If the dielectric layer 20 is thin enough, 
a capacitance structure is obtained. 
FIG. 3 shows a section taken along line B--B of FIG. 1 through the bottom 
layer 12. The contacts 22 are formed on the surface of the bottom layer 12 
via conventional etching procedures. As can be seen, spacers 30 are formed 
at the sides of the bottom layer 12 during the etching procedure to form 
the top layer 10 (shown in FIG. 2). This is due to the fact that in the 
area of the edges of the bottom layer 12, the top layer 10 must be etched 
in double thickness. In other words, these spacers 30 are formed because 
in certain areas of the layers 10, 12, the entire coating, i.e., the sum 
of the thicknesses of layers 10 and 12, has to be etched away. As a 
result, if the etching is sufficiently anisotropic, the spacers 30 are 
left behind at the side surfaces of the bottom layer 12. Further, if a 
high-melting metal is then deposited by sputtering to form a silicide in 
order to achieve an improvement in the electrical characteristics of the 
arrangement, as is frequently done, the spacers 30 may cause short 
circuits to develop between the top layer 10 and the bottom layer 12 or 
oxide breakdowns may result. 
Accordingly, it is the object of the present invention to substantially 
overcome and eliminate such disadvantages by providing an improved 
interconnecting structure for semiconductor integrated circuits that 
avoids the undesirable electrical characteristics associated with prior 
art interconnecting structures. 
SUMMARY OF THE INVENTION 
The present invention is directed to an interconnecting structure for 
semiconductor integrated circuits and a method for manufacturing such 
interconnecting structures. The interconnecting structure generally 
comprises a top layer, a bottom layer, and a dielectric isolation layer. 
The dielectric isolation layer is disposed between the top layer and the 
bottom layer. The top layer completely covers and encloses the dielectric 
isolation layer and the bottom layer. At least one opening is formed 
through the top layer, thereby exposing a selected region of the bottom 
layer. A contact is formed on the selected region of the bottom layer.

DETAILED DESCRIPTION OF THE DRAWINGS 
Referring to FIG. 4, a top view of an exemplary embodiment of the 
interconnecting structure 40 of the present invention is shown. The 
interconnecting structure 40 generally comprises a top layer 42 of 
semiconductor material completely covering a bottom layer 44 (shown by 
dotted line) of semiconductor material and a dielectric isolation layer 46 
(shown in FIG. 5) of silicon dioxide or the like disposed between the top 
layer 42 and the bottom layer 44. A contact opening 50 extends through the 
top layer and the dielectric layer and exposes a selected region 45 of the 
surface of the bottom layer 44. A metallized contact 22 is formed on the 
selected region 45 of the surface of the bottom layer 44. Since the 
contact opening 50 is etched only in the top layer 42 and the dielectric 
isolation layer 46, no spacers resulting from the etching through both the 
top and bottom layers 42, 44 are left behind, as in the prior art 
interconnecting structure of FIGS. 1-3. 
The interconnecting structure 40 shown in FIG. 4 is manufactured according 
to the following method. 
In FIG. 5a, the bottom layer 44 of semiconductor material of the 
interconnecting structure 40 has been deposited on a semiconductor 
substrate and patterned using conventional techniques, such as CVD and 
photolithography. 
In FIG. 5b, the dielectric isolation layer 46 is shown deposited over the 
entire surface of the bottom layer 44, using conventional techniques. 
In FIG. 5c, the top layer 42 has been deposited over the dielectric 
isolation layer 46 and the bottom layer 44, such that the top layer 42 
completely covers and encloses the layers 46, 44. The top layer 42 is 
deposited using conventional CVD techniques and the like. 
In FIG. 5d, an opening 50 having a predetermined size and shape has been 
formed through the top layer 42 and the dielectric isolation layer 46, 
using conventional etching techniques, thereby exposing the selected 
region 45 of the surface of the bottom layer 44. 
In FIG. 5e, the metallic contact 48 is shown formed on the selected region 
45 of the surface of the bottom layer 44. Techniques for forming such 
metallic contacts 48 are well known in the art. It should be understood 
that the present invention is not limited to one contact and that any 
number of contacts can be formed on the bottom layer 44, as desired. 
Accordingly, the interconnecting structure 40 of the present invention 
provides an improved interconnecting structure for semiconductor 
integrated circuits that avoids the undesirable electrical characteristics 
associated with prior art interconnecting structures. 
While preferred forms and arrangements have been shown in illustrating the 
invention, it is to be understood that various changes may be made without 
departing from the spirit and scope of this disclosure.