Integrated circuit and a method for recovering from a low-power period

A system that has low power recovery capabilities, the system includes: a switch that is adapted to provide a gated power supply to a power gated circuit in response to a control current; and a control signal generator adapted to control an intensity of the control current in response to a reception of a low power period end indicator, a value of the continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of a high switching point buffer that is inputted by the gated supply voltage.

FIELD OF THE INVENTION

This disclosure relates generally to an integrated circuit and a method for recovering from a low-power period.

BACKGROUND OF THE INVENTION

The power consumption of an integrated circuit can be reduced by completely shutting down one or more modules (circuits) of the integrated circuit. These circuits are shut down during one or more low-power periods. These shut-down circuits are also known as power-gated circuits as they receive a gated supply during non-low-power periods and do not receive the gated supply during the low-power period.

State retention power gating (SRPG) involves shutting down (by an on-die switch or often by multiple switch devices) the power-gated circuits while saving their status during low-power periods. Integrated circuits in which this technique is implemented include retention circuits that are powered by the continuous (retention) power supply and store, during each low-power period, state information reflecting a state of a power-gated circuit.

The low-power period ends by performing a power up process (also referred to recovery process) during which the gated supply voltage is provided to the power gated circuit (by connection of the gated supply to main continuous supply by a switch device) and then state information is sent to the power gated circuits.

A typical integrated circuit includes a very large number (hundreds, thousands, and even more) of SRPG flip-flops, each including a state retention circuit and a power gated circuit.

Retention circuits are usually fed by a local continuous power grid that can be weak in the sense of the amount of power it can convey and is connected to the main continuous power grid and has a low local intrinsic capacitance and therefore is susceptible to noise. This noise can be caused by e.g. powering up multiple power gated circuit components during a power up process that ends the low-power period. This power up process comprises charging the intrinsic capacitance of the power gated circuit, accompanied by large main continuous power supply current drain, causing (this current-induced) power grid voltage sag and ground voltage bounce (also known as IR-drop). Obviously, the retention power grid connected to the main continuous power grid outside the power gated circuit, becomes noisy as well. The noise cannot be adequately suppressed by the retention power grid and can cause retained state information errors. In order to eliminate such noise, it is known to very slow increment the gated supply voltage level during the powering up process, in order to reduce the mentioned current drain and to e.g. connect the retention circuits to the power gated circuits by multiple switch devices in a sequential manner or to establish a significant power switch impedance during the powering up process. The attempt to eliminate completely the retention power grid noises usually has highest priority compare to the other power up process parameters. Hence, the powering up process is usually very long. The duration of this process often determines whether or not is worth to use the low power mode, and is therefore critical for the integrated circuit power consumption reduction.

SUMMARY OF THE PRESENT INVENTION

The present invention provides a method and a device as described in the accompanying claims. Specific embodiments of the invention are set forth in the dependent claims. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following specification, the invention will be described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

It has been found that the exit from a low power period can be accelerated by selectively activating a strong current drain that contributed to a control current that controls a switch that selectively provides a gated supply voltage. The control current can be responsive, during at least one period, to a voltage drop that is developed within a continuous voltage supply grid.

FIG. 1schematically shows an example of an embodiment of a system100. The shown system100includes a power gated circuit102, a powered on during low power mode circuit104, a switch106, a power grid108, a low power mode controller170and a control signal generator110. The control signal generator110includes a Schmidt trigger circuit160, a weak current driver140, a strong current drain130, and a strong current drain controller150.

As shown inFIG. 1, switch106can include a first PMOS transistor105that has a gate that is connected to weak driver140and strong current drain130in order to receive a control current CC181. CC181controls first PMOS transistor105. Especially, the intensity of CC181determines how fast first PMOS transistor105“opens”—e.g. how fast a capacitance (such as a gate) of first PMOS transistor105is discharged—in order to enable First PMOS transistor105to conduct.

The source of First PMOS transistor105, a source of second PMOS transistor152and a source of fifth PMOS transistor142of weak driver140are connected to a first node109of power grid108at a port112of control signal generator110.

Another node107of power grid108is connected to continuous voltage supply port180. Continuous voltage supply port180can be an output port of a continuous voltage supply circuit or an output port of another circuit (such as a pad of an integrated circuit) that receives the continuous power supply Vddc188. A power supply voltage drop (also referred to as IRdrop) is developed on power grid108—between node107and node109. For simplicity of explanation the continuous supply voltage at node107is denoted Vddc while the continuous supply voltage at node109is denoted Vddcad (Vddc after IRdrop). In mathematical terms, assuming that the IR drop is denoted with IRdrop, then:
Vddc=IRdrop+Vddcad(1)

The drain of first PMOS transistor105provides a gated supply voltage Vddg183to power gated circuit102in response to CC181. Vddg183gradually increases as first PMOS transistor105gradually opens, during a first period, a second period and a third period of time that follow the end of the low power period, as is explained below in more detail.

Control signal generator110is adapted to control an intensity of control current181based on a low power period end indicator (LPPEI)184, a value of Vddcad185, a value of Vddg183and an output signal (Sst)187of high switching point buffer160that is fed by Vddg183. The intensity of control current181can be positive when LPPEI184is positive.

Output signal Sst187of high switching point buffer160can be a high value (HV) or a low value (LV). The high value (HV) is set above a first value of Vddg183that closes first branch150(1) of strong current drain controller150. HV can e.g. be few hundred millivolts above the first value of Vddg183.

The shown strong current drain controller150includes inverter151, second PMOS transistor152, third PMOS transistor153, fourth PMOS transistor154, diode155and resistor156. First branch150(1) of strong current drain controller150includes third PMOS transistor153. A second branch150(2) includes fourth PMOS transistor154and diode155.

An input of inverter151receives LPPEI184and its output is connected to a gate of second PMOS transistor152. The source of second PMOS transistor152is connected to port112of control signal generator110. The drain of second PMOS transistor152is connected to the sources of third and fourth PMOS transistors153and154. The drain of third PMOS transistor153is connected to a node199. Node199is also connected to a first end of resistor156, to cathode of diode155and to a gate of NMOS transistor131. NMOS transistor131is included within strong current drain130. The voltage at node199is also referred to control voltage (CV)182. The drain of fourth PMOS transistor154is connected to anode of diode155while another end of the diode is connected to node199.

The gate of third PMOS transistor153receives Vddg183. The gate of fourth PMOS transistor154receives Sst187. Third PMOS transistor153becomes closed when Vddg183reaches a first value V1. Fourth PMOS transistor154becomes closed when Vddg183reaches a second value (V2) that is higher than the first value (V1). When Vddg183reaches the second value, Sst187turns from the low value (LV) to the high value (HV) and fourth PMOS transistor154closes.

Weak current driver140includes an inverter that includes fifth PMOS transistor142and second NMOS transistor144. The gates of fifth PMOS transistor142and second NMOS transistor144receive LPPEI184(from low power mode controller170—but for simplicity of explanation this connection is not shown) and provide an inverted signal (IS)181to the gate of first PMOS transistor105. The weak current driver140drives a logic high value when the circuit is in low power mode and is driving logic low value if the circuit is in non-low power mode.

Strong current drain130contributes to CC181when it is activated. It speeds up the opening of first PMOS transistor105by increasing the discharge rate of the gate capacitor of the first PMOS transistor105. Strong current drain130determines the first PMOS transistor105gate potential discharge rate indifferent to the voltage of Vddcad185during a first period and determines the first PMOS transistor105gate potential discharge rate dependent on the voltage of Vddcad185during a second period.

Strong current drain130is capable of generating a current that is stronger than the current drained by weak driver140.

Referring toFIG. 2, the first period starts at point in time T1301—after a reception of the low power end indicator LPPEI184and ends at point in time T2−Vddg183reaches first value V1310. The second period starts at a point in time after the beginning of the first period (it can start a T2302but this is not necessarily so as it can start after T1301) and ends at point in time T3303—when Vddg183reaches V2320that is higher than V1310and causes high switching point buffer160to output a high value signal that closes fourth PMOS transistor154. The first PMOS transistor105gate potential discharge current is responsive to a value of voltage drop (also referred to as IRdrop) over power grid108in theFIG. 1.

Thus, during the first period the first PMOS transistor105gate potential discharge rate is accelerated by providing CC181that is not responsive to IRdrop while during the second period the discharge rate is accelerated by providing CC181that is responsive to IRdrop, as higher IRdrop values decrease the conductivity of strong current drain130and even shut it down while lower IR values increase the conductivity of strong current drain130.Especially, diode155acts as a biasing element that converts Vddcad185to CV182, wherein during the second period CV182can change (in response to changes in IRdrop) within a voltage range that includes the threshold voltage (Vth) of first NMOS transistor131. Thus, different values of IRdrop can activate or deactivate strong current drain130and thus affect the value of CC181. In other words, forward biased diode155translates Vddcad185(actually responsive to the amount of IRdrop) to a voltage (CV182) that activates strong current drain150and translates a large amount of IRdrop to a control voltage decrease that deactivates the strong current drain.

During the first period third PMOS transistor153“mirrors” Vddcad185to CV182so that CV182substantially equals Vddcad185. Vddcad185is expected to be much higher than the threshold voltage of first NMOS transistor131and changes in IRdrop are not expected to alter the conductivity of first NMOS transistor131. Accordingly, during the first period strong current drain150generates a voltage drop indifferent draining current.

FIG. 2also illustrates CV182and CC181. Both signals are very low (zero level) between T0300and T1301, jump to a very high level at T1and substantially maintain at this level during the entire first period. During the second period both signals fluctuate wherein during the second period CV can fluctuate below and above the threshold voltage VT171of first NMOS transistor131.

CC181is above zero during a third period that follows the second period and later on drops to zero. At the end of the third period Vddg183reaches its maximum value.

FIG. 3schematically shows an example of an embodiment of method400.

Method400for recovering from a low-power period starts by stage410of maintaining a power gated circuit in a low power mode, during a low power period.

Stage410is followed by stage420of receiving, by a control signal generator, a low power period end indicator.

Stage420is followed by stage430of determining an intensity of a control current, charging the switch device gate, in response to a value of a continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of high switching point buffer160that is inputted by the gated supply voltage.

Stage430is followed by stage440of controlling the intensity of the control current in response to the determination.

Stage440is followed by stage450of providing the control signal to a switch.

Stage450is followed by stage460of providing, by the switch, in response to the control signal a gated supply voltage to a power gated circuit.

Stage440can include stage442of generating, by a strong current drain, the draining current which is indifferent to the voltage drop during the first period.

Stage440can also include stage444of generating, by the strong current drain, a week voltage drop responsive draining current during a second period. The voltage drop responsive draining current is responsive to a value of a voltage drop that represents a difference between the value of the continuous supply voltage at the port of the control signal generator and the value of the continuous supply voltage at a continuous voltage supply port.

Accordingly, during the first and second periods the control current can include at least one of the voltage drop indifferent draining current and the voltage drop responsive draining current.

Stage440can include stages446and448. Stage446includes controlling the strong current drain by a first branch of a strong current drain controller during the first period. Stage448includes controlling the strong current drain by a second branch of the strong current drain controller during the second period.

Stage448can include stage449of translating, by a voltage adjustment element of the second branch, a low amount of voltage drop to a control voltage that activates the strong current drain and translating a high amount of retention power supply to a control voltage that deactivates the strong current drain. Stage449can include utilizing a voltage adjustment element that may include (but not necessarily) a forward biased diode.

Stage449can include providing, by the second branch and to the gate of the strong current drain control, voltages within a voltage range that comprises the threshold voltage of the strong current drain.

Stage446can include stage447of providing, by the first branch and to a gate of the strong current drain, control voltages that are much above a threshold voltage of the strong current drain.

FIG. 4schematically shows an example of an embodiment of method500.

Method500for recovering from a low-power period starts by stage410of maintaining a power gated circuit in a low power mode, during a low power period.

Stage410is followed by stage420of receiving, by a control signal generator, a low power period end indicator.

Stage520includes determining an intensity of a voltage drop indifferent draining current generated by a strong current drain.

Stage520is followed by stage525of generating, by a strong current drain, a voltage drop indifferent draining current during a first period. The first period starts after a reception of the low power end indicator and ends when the gated power supply voltage reaches a first value.

Stage530includes determining an intensity of a voltage drop responsive draining current generated by a strong current drain.

Stage530is followed by stage535of generating, by the strong current drain, a voltage drop responsive draining current during a second period. The second period starts after a beginning of the first period and ends when the gated supply voltage reaches a second value that is higher than the first value and causes the high switching point buffer to output a high value signal. The voltage drop responsive draining current is responsive to a value of a voltage drop that represents a difference between the value of the continuous power supply voltage at the port of the control signal generator and the value of the continuous supply voltage at a continuous voltage supply port.

Stage525and535are followed by stage540of providing a control signal to a switch. The control signal includes at least one of the voltage drop indifferent draining current and the voltage drop responsive draining current.

Stage540is followed by stage550of providing, by the switch, in response to the control signal, a gated supply current to a power gated circuit.

Stage525can include controlling the strong current drain by a first branch of a strong current drain controller during the first period.

Stage535can include controlling the strong current drain by a second branch of the strong current drain controller during the second period.

Stage535can include mirroring by a voltage adjustment element that comprises a forward biased diode, the retention power supply voltage to the strong current drain control voltage.

Stage525can include providing, by the first branch and to a gate of the strong current drain, control voltages that are much above a threshold voltage of the strong current drain; and stage535can include providing, by the second branch and to the gate of the strong current drain control, voltages within a voltage range that comprises the threshold voltage of the strong current drain.

Either one of methods400and500can be implemented by system200ofFIG. 1.

Referring to the power supply gating covers also the ground gating which is completely symmetric to the power supply gating. Those skilled in the art may note that in this situation the elements of the system200change their polarity (e.g. NMOS transistor becomes PMOS transistor and vice-versa). Obviously current drains become current sources (and vice-versa), and the control signal polarity is also changing.

In addition, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device.

The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.