Variable gain circuit and tuner system provided with same

A variable gain transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner. A variable gain circuit may include the variable gain transconductance amplifier.

BACKGROUND

The present disclosure relates a cascode-type transconductance amplifier which is capable of reducing distortion and a variable gain circuit which is capable of reducing distortion and noise.

Tuner systems that receive transmitted signals each containing multiple channels and that select and demodulate a desired one of the multiple channels are required to have low-noise and low-distortion characteristics. For example, the Integrated Service Digital Broadcasting-Terrestrial (ISDB-T) in Japan has 40 channels, in total, from Channel 13 (473.143 MHz) to Channel 52 (707.143 MHz), where each channel has a signal band of 6 MHz. A tuner system is required to realize high sensitivity of −80 dBm or less and immunity of 50 dBc or more with respect to the input levels of interfering waves.

The reception characteristics of a tuner system of this type depend on the noise characteristics and distortion characteristics of a variable gain circuit that processes RF signals that have been just received by an antenna, for example. On the other hand, a tuner system installed in a mobile terminal is required to reduce its power consumption.

A variable gain circuit configured to process an RF signal in two paths in a switchable manner depending on the signal strength is disclosed (see, for example, U.S. Pat. No. 8,018,285). Specifically, an RF signal having a low signal strength is amplified by a transconductance amplifier provided in a first path. On the other hand, an RF signal having a high signal strength is attenuated by an attenuator provided in a second path, and then amplified by a transconductance amplifier provided in the second path.

With this configuration in which the first path is turned on and the second path is turned off if an RF signal has a low signal strength, and the first path is turned off and the second path is turned on if an RF signal has a high signal strength, an attempt to reduce noise and distortion has been carried out.

SUMMARY

In the configuration of U.S. Pat. No. 8,018,285, however, if the signal strength is high, the transconductance amplifier in the first path that is supposed to be kept off is intermittently turned on due to the signal amplitude, and the distorted signal leaks from the first path to the output. Consequently, the distortion characteristics of the variable gain circuit are deteriorated. If a grounded-gate amplifier is used as the transconductance amplifier, the input impedance fluctuates remarkably, and consequently, an input to the transconductance amplifier in the second path distorts the signal. These phenomena become more remarkable if a transistor with a low threshold voltage is used to reduce the power consumption of the variable gain circuit. It is therefore difficult, with the variable gain circuit of U.S. Pat. No. 8,018,285, to reduce the power consumption.

In view of the foregoing, it is therefore an object of the present disclosure to provide a cascode-type transconductance amplifier which is capable of reducing the distortion, and a variable gain circuit which is capable of reducing the noise, distortion, and power consumption.

To achieve the object, the present disclosure provides the following: A cascode-type transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner.

This configuration allows for connecting or disconnecting, by the switching circuit, the connection node of the amplifier transistor and the cascode transistor that are connected between the input and output nodes to or from the fixed potential in a switchable manner.

For example, if a signal having a large amplitude is input, the switching circuit is controlled to connect the connection node to the fixed potential. Consequently, the signal that has passed through the amplifier transistor is sent to the fixed potential via the switching circuit, which prevents the signal from leaking to the output node through the cascode transistor. On the other hand, if a signal having a small amplitude is input, the switching circuit is controlled to disconnect the connection node from the fixed potential. Consequently, the signal is transmitted to the output node through the amplifier transistor and the cascode transistor.

The use of this cascode-type transconductance amplifier as the amplifier in the first path prevents a distorted signal from being output through the first path even when a signal having a large amplitude has been input in a state where the first path is off, thereby maintaining the distortion characteristics of the variable gain circuit good.

Since the use of this cascode-type transconductance amplifier allows for maintaining the distortion characteristics good even when a signal having a large amplitude has been input, it is possible to employ a transistor having a low threshold voltage in the variable gain circuit.

These features enable the variable gain circuit to reduce the distortion and power consumption.

Further, the present disclosure provides a variable gain circuit including a first path and a second path which are connected in parallel between an input terminal and an output terminal and which are capable of amplifying a signal. The first path has a first variable attenuator which is connected to the input terminal, and which attenuates an input signal by a variable amount of attenuation, and a first variable gain transconductance amplifier which is connected between the first variable attenuator and the output terminal, and which amplifies an output from the first variable attenuator. The second path has a second variable attenuator which attenuates an input signal by a variable amount of attenuation, and a second variable gain transconductance amplifier which is connected between the second variable attenuator and the output terminal, and which amplifies an output from the second variable attenuator. An input side of the second variable attenuator is connected to the input terminal or between the first variable attenuator and the first variable gain transconductance amplifier. The first variable gain transconductance amplifier has a greater maximum gain than the second variable gain transconductance amplifier.

With this configuration, each of the first and second paths has the associated variable attenuator and the associated variable gain transconductance amplifier. The first variable gain transconductance amplifier is designed to have a greater maximum gain than the second variable gain transconductance amplifier. A signal input to the variable gain circuit passes through the first and second paths, and then, is output. Here, if the input signal has a large amplitude, the first variable attenuator is turned on and the first variable gain transconductance amplifier is turned off in the first path, while the second variable attenuator and the second variable gain transconductance amplifier are both turned on in the second path.

In this case, in the first path, the output from the first variable attenuator is input to the first variable gain transconductance amplifier. Therefore, even if the input signal has a large amplitude, the signal is attenuated by the first variable attenuator before being input to the first variable gain transconductance amplifier. This allows for preventing the first variable gain transconductance amplifier from being turning on intermittently due to the amplitude of a signal, thereby enabling reduction of distortion of the signal.

Further, since the first variable gain transconductance amplifier processes a signal of which the amplitude has been reduced by the first variable attenuator, a transistor having a low threshold voltage can be employed in the variable gain circuit.

These features enable the variable gain circuit to reduce the distortion and power consumption.

If an input signal has a small amplitude, the first variable attenuator is turned off and the first variable gain transconductance amplifier is turned on in the first path, while the second variable attenuator is turned off and the second variable gain transconductance amplifier is turned on in the second path.

In this case, the input signal is not attenuated but amplified in the first and second paths. In particular, the first variable gain transconductance amplifier provides a high degree of amplification, which enables noise reduction.

Furthermore, the input side of the second variable attenuator may be connected to a point between the first variable attenuator and the first variable gain transconductance amplifier, i.e., to the output side of the first variable attenuator. This configuration enables a signal in the second path to be attenuated by both the first and second variable attenuators. Therefore, the second variable attenuator needs to provide only a small amount of attenuation, which consequently allows for reducing the area of the variable gain circuit.

The present disclosure also provides a tuner system which includes at least one of the cascode-type transconductance amplifier or the variable gain circuit.

This configuration enables the tuner system to reduce the noise, distortion, and power consumption.

The present disclosure provides a cascode-type transconductance amplifier which is capable of reducing the distortion and a variable gain circuit which is capable of reducing the noise, distortion, and power consumption.

DETAILED DESCRIPTION

First Embodiment

FIG. 1is a diagram showing a configuration of a variable gain circuit according to a first embodiment. The variable gain circuit2of this embodiment is configured to amplify a signal that is input to its input terminal Sin, and outputs the amplified signal from its output terminal Sout. The signal input to the input terminal Sin has been received by an antenna, for example.

Specifically, the variable gain circuit2includes a first path P1and a second path P2that are connected in parallel with each other between the input terminal Sin and the output terminal Sout.

The first path P1has a variable attenuator4(hereinafter abbreviated as ATT4) connected to the input terminal Sin, and a variable gain transconductance amplifier6(hereinafter abbreviated as Gm6) connected between the ATT4and the output terminal Sout.

The ATT4is capable of attenuating the input signal by a variable amount of attenuation. The Gm6is capable of amplifying the output from the ATT4by a variable gain.

The second path P2has a variable attenuator8(hereinafter abbreviated as ATT8) connected to the input terminal Sin, and a variable gain transconductance amplifier10(hereinafter abbreviated as Gm10) connected between the ATT8and the output terminal Sout.

The ATT8is capable of attenuating the input signal by a variable amount of attenuation. The Gm10is capable of amplifying the output from the ATT8by a variable gain. The Gm10is designed to have a smaller maximum gain than the Gm6.

Configuration examples of the ATT4, the ATT8, the Gm6, and the Gm10will be described later.

The variable gain circuit2further includes a load11and a control circuit12that are connected to the output terminal Sout.

The control circuit12controls the amounts of attenuation of the ATT4and the ATT8and the gains by the Gm6and the Gm10, based on the signal output from the output terminal Sout, for example. The control circuit12may detect the signal level at a location other than the output terminal Sout of the variable gain circuit2.

How the variable gain circuit2of this embodiment operates is now described. For example, if a signal received by the antenna has low field intensity, that is, if the amplitude of the signal input to the input terminal Sin is small, the control circuit12performs control to turn off both the ATT4and the ATT8. Consequently, the ATT4and the ATT8allow the input signal to pass therethrough as it is.

The control circuit12also performs control such that the Gm6and the Gm10provides the respective maximum gains, for example. As a result, the Gm6amplifies the input signal by the maximum gain that is greater than the maximum gain of the Gm10, and the Gm10amplifies the input signal by the maximum gain of itself.

The outputs from the Gm6and the Gm10are combined with each other, and the resultant composite signal is output from the output terminal Sout.

Here, the maximum gain of the Gm6is greater than that of the Gm10. Therefore, even if a signal having a low S/N ratio is input, the signal is amplified by the Gm6without being attenuated by the ATT4. This allows for noise reduction.

On the other hand, if a signal received by the antenna has high field intensity, i.e., if the amplitude of the signal input to the input terminal Sin is large, the control circuit12performs control to turn on the ATT4and the ATT8. Consequently, the ATT4and the ATT8attenuate the input signal by respective predetermined amounts of attenuation.

The control circuit12also performs control to turn off the Gm6and turn on the Gm10. This control results in that the signal to be input to the Gm6is attenuated by the ATT4, which can prevent the Gm6from being turned on due to the amplitude of the signal. This allows for preventing the signal from being distorted on the input side of the Gm6or the distorted signal from leaking to the output terminal Sout from the Gm6that is off. Thus, distortion reduction of the variable gain circuit2is achieved.

In addition, even if the input signal has a large amplitude, the ATT4reduces the amplitude of the signal to be input to the Gm6. This allows for employing a transistor having a low threshold voltage as the Gm6. The Gm6comprised of such a transistor consumes less power, which results in a decrease in the power consumption of the variable gain circuit2.

Thus, according to this embodiment, the first path P1is provided with the ATT4and the Gm6, the second path P2is provided with the ATT8and the Gm10, and the Gm6is designed to provide a greater maximum gain than the Gm10. If a signal input to the input terminal Sin has a small amplitude, the variable gain circuit performs the control to turn off the ATT4and the ATT8and to turn on the Gm6and the Gm10. On the other hand, if a signal input to the input terminal Sin has a large amplitude, the variable gain circuit performs the control to turn on the ATT4, the ATT8, and the Gm10, and to turn off the Gm6.

As can be seen from the foregoing, with this configuration, the variable gain circuit2, which consumes less power while maintaining good noise characteristics and good distortion characteristics, is provided.

In this embodiment, the input side of the ATT8is connected to the input terminal Sin. The input side of the ATT8may, however, be connected between the ATT4and the Gm6, as shown inFIG. 2. In other words, the ATT4may be shared by the first path P1and the second path P2.

With this configuration, if a signal input to the input terminal Sin has a large amplitude, the signal is attenuated by the ATT4and the ATT8in the second path P2. Therefore, the amount of attenuation of the ATT8can be smaller than that of the ATT4. This allows for reducing the area of the ATT8, which results in a decrease in the area of the variable gain circuit2.

Next, configuration examples of the Gm6, the Gm10, the ATT4, and the ATT8will be described with reference to the drawings. Note that in the following description, the term “fixed potential” refers to ground potential, for example.

Configuration Examples of Gm6and Gm10

Specific examples of the Gm6and the Gm10are described below with reference toFIGS. 3 to 8.

Configuration Example 1

FIG. 3shows a configuration example of the variable gain transconductance amplifiers ofFIG. 1. Specifically, as shown inFIG. 3, each of the variable gain transconductance amplifiers serving as the Gm6and Gm10includes a transistor Tr1as an amplifier transistor and a transistor Tr2as a cascode transistor. The transistors Tr1and Tr2are Nch transistors, for example.

The transistor Tr1has its source connected to the input node in of the variable gain transconductance amplifier and has its gate connected to a bias voltage VB1. That is to say, the transistor Tr1operates as a grounded-gate amplifier transistor.

The transistor Tr2has its source connected to the drain of the transistor Tr1, its drain connected to the output node out of the variable gain transconductance amplifier, and its gate connected to a bias voltage VB2. Each of the bias voltages VB1and VB2may have an arbitrary magnitude.

Configuring each of the Gm6and the Gm10ofFIG. 1as shown inFIG. 3makes the matching (impedance matching) between the antenna and the circuit ofFIG. 1good.

Here, the amplifier transistor Tr1of the Gm6is designed to be larger in size than the amplifier transistor Tr1of the Gm10. As a result, the maximum gain of the Gm6is greater than that of the Gm10.

The Gm6and the Gm10may suitably have other configurations as long as the maximum gain of the Gm6is greater than that of the Gm10.

Configuration Example 2

FIG. 4shows another configuration example of the variable gain transconductance amplifiers ofFIG. 1. Here, differences between the configuration examples ofFIGS. 3 and 4are described mainly.

The transistor Tr1has its gate which is connected to the input node in of the variable gain transconductance amplifier and to a bias voltage VB1via a resistive element. The source of the transistor Tr1is connected to a fixed potential. That is to say, this transistor Tr1operates as a common-source transistor.

Configuring the transistor Tr1as a common-source transistor in this manner makes the variable gain transconductance amplifier have good noise characteristics.

Configuration Example 3

FIG. 5shows another configuration example of the variable gain transconductance amplifiers ofFIG. 1. As shown inFIG. 5, the Gm6and the Gm10ofFIG. 1may be configured to process a differential signal. In this case, a differential signal generator circuit is suitably provided in or before the variable gain transconductance amplifier. Here, differences between the configuration examples ofFIGS. 3 and 5are described mainly.

The variable gain transconductance amplifier ofFIG. 5includes, in addition to the transistors Tr1and Tr2, a transistor Tr3, a transistor Tr4, and capacitive elements C1and C2.

The transistor Tr1has its source connected to the input node in_p of the variable gain transconductance amplifier. The transistor Tr2has its gate connected to the gate of the transistor Tr1, and its drain connected to the output node out_p of the variable gain transconductance amplifier.

The transistor Tr3is a differential amplifier transistor that forms a differential pair with the transistor Tr1. The transistor Tr3has its source connected to the differential input node in_n of the variable gain transconductance amplifier.

The transistor Tr4is a differential cascode transistor that forms a differential pair with the transistor Tr2. The transistor Tr4has its source connected to the drain of the transistor Tr3and its drain connected to the differential output node out_n of the variable gain transconductance amplifier.

The source of the transistor Tr1is connected to the gate of the transistor Tr3via the capacitive element C1. The source of the transistor Tr3is connected to the gate of the transistor Tr1via the capacitive element C2.

The gates of the transistors Tr1and Tr3are connected to a bias voltage VB1, and the gates of the transistors Tr2and Tr4are connected to a bias voltage VB2.

Configuring each of the Gm6and Gm10ofFIG. 1as shown inFIG. 5provides the advantages of both the configurations examples ofFIGS. 3 and 4.

The intermediate node between the transistors Tr1and Tr2may be connectable to a fixed potential. Such a configuration will be described below.

Configuration Example 4

FIG. 6shows another configuration example of the Gm6ofFIG. 1. Here, differences between the configuration examples ofFIGS. 3 and 6are described mainly.

The variable gain transconductance amplifier ofFIG. 6includes, in addition to the transistors Tr1and Tr2, a switch14which operates as a switching circuit and which is an Nch transistor, for example. This variable gain transconductance amplifier further includes a switch15which connects the gate of the transistor Tr1to a fixed potential or a bias voltage VB1, and a switch16which connects the gate of the transistor Tr2to a fixed potential or a bias voltage VB2.

The switch14connects or disconnects the intermediate node between the transistors Tr1and Tr2to or from a fixed potential in a switchable manner.

The switches14,15, and16are controlled by the control circuit12shown inFIG. 1. Specifically, if the Gm6ofFIG. 1is off, the control circuit12turns on the switch14so as to connect the intermediate node between the transistors Tr1and Tr2to the associated fixed potential. The control circuit12also connects at least one of the switch15or16to the associated fixed potential.

On the other hand, if the Gm6is on, the control circuit12turns off the switch14so as to disconnect the intermediate node between the transistors Tr1and Tr2from the associated fixed potential. The control circuit12performs control to connect the switches15and16to the bias voltages VB1and VB2, respectively.

This configuration allows for hindering distortion from leaking from the input node in to the output node out when the Gm6is off. Therefore, the use of the variable gain transconductance amplifier having the configuration shown inFIG. 6as the Gm6ofFIG. 1further improves the distortion characteristics of the variable gain circuit2.

Configuration Example 5

FIG. 7shows another configuration example of the Gm6ofFIG. 1. Here, differences between the configuration examples ofFIGS. 4 and 7are described mainly.

The variable gain transconductance amplifier ofFIG. 7includes, in addition to the transistors Tr1and Tr2, a switch14which connects or disconnects the intermediate node between the transistors Tr1and Tr2to or from a fixed potential in a switchable manner. This variable gain transconductance amplifier further includes a switch15which connects an end of a resistive element, of which the other end is connected to the gate of the transistor Tr1, to a fixed potential or a bias voltage VB1, and a switch16which connects the gate of the transistor Tr2to a fixed potential or a bias voltage VB2.

Configuration Example 6

FIG. 8shows another configuration example of Gm6ofFIG. 1. Here, differences between the configuration examples ofFIGS. 5 and 8are described mainly.

The variable gain transconductance amplifier ofFIG. 8includes, in addition to the transistors Tr1to Tr4, a switch14which connects or disconnects the intermediate node between the transistors Tr1and Tr2and the intermediate node between the transistors Tr3and Tr4to or from a fixed potential in a switchable manner.

This variable gain transconductance amplifier further includes a switch15which connects the gates of the transistors Tr1and Tr3to a fixed potential or a bias voltage VB1, and a switch16which connects the gates of the transistors Tr2and Tr4to a fixed potential or a bias voltage VB2.

The above configurations, in which, when the Gm6is off, the intermediate node between the transistor Tr1and Tr2shown inFIGS. 6 to 8and the intermediate node between the transistors Tr3and Tr4shown inFIG. 8can be grounded, allows for further improving the distortion characteristics of the variable gain circuit2.

The switch15or16may be omitted from the configurations ofFIGS. 6 to 8. If so, the gates of the transistors Tr1and Tr2and the gates of the transistors Tr3and Tr4may be connected to the bias voltages VB1and VB2, respectively.

Configuration Examples of ATT4and ATT8

Next, specific examples of the ATT4and the ATT8will be described with reference toFIGS. 9 to 12.

Configuration Example 1

FIG. 9shows a configuration example of the variable attenuators ofFIG. 1. As shown inFIG. 9, each of the variable attenuators serving as the ATT4and ATT8includes a resistive element R and paths RP1to RPn (wherein n is a natural number).

The resistive element R is provided between the input node in and the output node out of the variable attenuator. Each of the paths RP1to RPn is configured to connect in parallel an associated point located between the input node in and the output node out to an associated fixed potential.

Specifically, each of the paths RP1to RPn has an associated one of resistive elements R1to Rn and an associated one of switches S1to Sn that are respectively connected to the resistive elements R1to Rn. The control circuit12shown inFIG. 1performs control to turn on or off the switches S1to Sn, which varies the amount of attenuation of the variable attenuator.

The input node in of this variable attenuator is connected to the input terminal Sin of the variable gain circuit2ofFIG. 1.

Configuration Example 2

FIG. 10shows another configuration example of the variable attenuators ofFIG. 1. As shown inFIG. 10, in order to maintain the noise characteristics of the variable attenuator better, the resistive element R shown inFIG. 9may be omitted, and the circuit configuration shown inFIG. 10may be combined with the impedance of an input signal source.

Configuration Example 3

FIG. 11shows another configuration example of the variable attenuators ofFIG. 1. As shown inFIG. 11, the resistive elements R and R1to Rn shown inFIG. 9may be replaced with capacitive elements C and C1to Cn.

Specifically, as shown inFIG. 11, each of the variable attenuators serving as the ATT4and ATT8has the capacitive element C and paths CP1to CPn.

The capacitive element C is provided between the input node in and the output node out of the variable attenuator. Each of the paths CP1to CPn is configured to connect in parallel an associated point located between the input node in and the output node out to an associated fixed potential.

Each of the paths CP1to CPn has an associated one of the capacitive elements C1to Cn and an associated one of switches S1to Sn that are respectively connected to the capacitive elements C1to Cn.

Configuration Example 4

FIG. 12shows another configuration example of the variable attenuator ofFIG. 1. The variable attenuator ofFIG. 12corresponds to the combination of the variable attenuators ofFIGS. 9 and 11. Specifically, the variable attenuator may include paths RP1to RPn that have resistive elements R1to Rn and associated switches SR1to SRn, and path CP1to CPn that have a capacitive element C, capacitive elements C1to Cn and associated switch SC1to SCn.

The number of the paths RP1to RPn may differ from the number of the paths CP1to CPn.

This configuration allows for extending the range within which the amount of attenuation of the variable attenuator is varied.

As shown inFIGS. 9 to 12, each of the ATT4and ATT8may be comprised of two or more switch resistor circuits that each include a resistive element and a switch and that are connected in parallel with each other, and the amounts of attenuation of the ATT4and ATT8may be varied by means of resistive voltage division. Alternatively, each of the ATT4and ATT8may be comprised of two or more switch capacitor circuits that each include a capacitive element and a switch and that are connected in parallel with each other, and the amounts of attenuation of the ATT4and ATT8may be varied by means of capacitive voltage division. Further, each of the ATT4and ATT8may be configured as a combination of a switch resistor circuit and a switch capacitor circuit.

In each of the variable attenuators shown inFIGS. 9 to 12, a switch is suitably provided to any one of the paths RP1to RPn or any one of the paths CP1to CPn.

Each of the variable attenuators shown inFIGS. 9 to 12may be provided with one path connecting a point between the input node in and output node out to a fixed potential, and the path may suitably be provided with at least one of a resistive element or a capacitive element and with a switch. That is to say, each attenuator may have any suitable configuration as long as the amount of attenuation is variable.

Next, another manner in which the variable gain circuit2of this embodiment operates will be described with reference toFIG. 13.

FIG. 13shows how the variable gain circuit ofFIG. 1operates in a different manner Specifically,FIG. 13shows an example in which the variable gain circuit2is controlled such that its gain varies gradually. The control circuit12performs control to gradually vary the amounts of attenuation of the ATT4and ATT8and the gains of the Gm6and Gm10.

Specifically, if the variable gain circuit2operates to provide the maximum gain, the amount of attenuation of each of the ATT4and ATT8is 0 dB (i.e., the ATT4and ATT8are in a pass-through mode), and the maximum gains of the Gm6and Gm10are, for example, 15 dB and 4 dB, respectively.

If the maximum gain of the variable gain circuit2decreases to be an intermediate gain, the amount of attenuation of the ATT4gradually increases to be −5 dB, for example, whereas the gain of the Gm6gradually decreases to be 0 dB. At this time, the amount of attenuation of the ATT8remains 0 dB and the gain of the Gm10remains 4 dB.

If the gain of the variable gain circuit2further decreases to be the minimum gain, the amount attenuation of the ATT4remains −5 dB, whereas the Gm6is off, the amount of attenuation of the ATT8is −10 dB, for example, and the gain of the Gm10is −10 dB, for example.

As can be seen from the forgoing, the gain of the variable gain circuit2is attenuated in such a manner that, from a state in which the two paths P1and P2are both on, the gain of one path is reduced to become sufficiently smaller than the gain of the other, and then, the one path is brought into an off state. In this manner, the gain variation is implemented seamlessly.

To increase the gain, the variable gain circuit2operates in reverse, and the same or similar advantages are obtained.

Here, with the configuration of Patent Document 1, switching between the two paths is performed depending on the strength of a signal. Therefore, at the timing of the path switching, the gain of the variable gain circuit and the phase relationship between input and output signals fluctuate significantly, which results in serious deterioration of the signal quality.

This problem is reduced by controlling the gain of the variable gain circuit2in a manner as shown inFIG. 13.

In the operation shown inFIG. 13, the gradual increase in the amount of attenuation by the ATT4may begin before or after the gain of the Gm6begins to decrease gradually. Further, the gradual increase in the amount of attenuation of the ATT8may begin before or after the gain of the Gm10begins to decrease gradually.

FIG. 13shows the operation example in which the gain of the variable gain circuit2is controllable at three values or more. The number of the steps in which the amounts of attenuation of the ATT4and ATT8and the gains of the Gm6and Gm10are varied can be set as desired.

Second Embodiment

FIG. 14shows a configuration of a tuner system according to a second embodiment. InFIG. 14, all of the signal processing blocks except the antenna21can be configured as an integrated circuit by using scaled complementary metal-oxide semiconductor (CMOS) process. The signal strength of an RF signal received by the antenna21is adjusted by the variable gain circuit2. The RF signal may be a wire signal input via a cable. The variable gain circuit2is of the above-described embodiment.

The RF signal processed by the variable gain circuit2is converted into a baseband signal by a mixer with the use of a local oscillator signal generated by a phase locked loop (PLL)23. The conversion method may be any one of a Low-IF method or a direct conversion method. The baseband signal is sent to a low-pass filter (LPF)25, in which unnecessary high-frequency components are removed to a sufficient extent from the baseband signal. Thereafter, the signal is converted into a digital signal by an A/D converter (ADC)26. The signal is finally subjected to demodulation and other processes by a digital signal processor (DSP)27. Since the input level of the RF signal is detected by the DSP27, the variability characteristics of the ATT4, the ATT8, the Gm6, and the Gm10of the variable gain circuit2shown inFIG. 1can be controlled in accordance with the detection results.

For example, if Channel 13 (473.143 MHz) of the Integrated Service Digital Broadcasting-Terrestrial in Japan is received, the PLL3outputs a local oscillator signal of 470.143 MHz, and the received RF signal is converted by the mixer24into a baseband signal having an intermediate frequency of 3 MHz that corresponds to the difference between the received frequency and the local oscillator signal frequency. At this time, although a high-frequency signal of 943.286 MHz that corresponds to the sum of the received frequency and the local oscillator signal frequency is also generated, such a high-frequency component is sufficiently attenuated through the filtering process by the LPF25. For example, the signal band of the LPF25is the same as the signal band of the channel, i.e. 6 MHz. When other channels are received, the oscillation frequency of the PLL23is varied in accordance with the desired channels.

In the tuner system of this embodiment, the RF signal that has been just received by the antenna21is processed by the above-described variable gain circuit2. This allows for obtaining good distortion characteristics and good noise characteristics and reducing the power consumption.

To process differential signals by the tuner system, the ADC26may be configured to perform single-end conversion, for example.

The tuner system of this embodiment may include the cascode-type transconductance amplifier shown inFIG. 6, for example.

The cascode-type transconductance amplifier of the present disclosure is capable of maintaining its distortion characteristic good. The variable gain circuit of the present disclosure has good distortion characteristics and good noise characteristics and is capable of reducing the power consumption. Therefore, the cascode-type transconductance amplifier and the variable gain circuit of the present disclosure are useful for stationary TV sets that receive analog and digital broadcasting waves, portable terminals, and other devices.