Efficient zadoff-chu sequence generation

Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.

BACKGROUND

The subject disclosure relates generally to wireless communication and, more particularly, to on-time generation of Zadoff-Chu sequences and computer generated sequences.

Wireless communication systems are widely deployed to provide various types of communication content such as voice, video, data, and so on. These systems may be multiple-access systems capable of supporting simultaneous communication of multiple terminals with one or more base stations. Multiple-access communication relies on sharing available system resources (e.g., bandwidth and transmit power). Examples of multiple-access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, and orthogonal frequency division multiple access (OFDMA) systems.

Communication between a terminal in a wireless system (e.g., a multiple-access system) and a base station is effected through transmissions over a wireless link comprised of a forward link and a reverse link. Such communication link may be established via a single-input-single-output (SISO), multiple-input-single-output (MISO), or a multiple-input-multiple-output (MIMO) system. A MIMO system consists of transmitter(s) and receiver(s) equipped, respectively, with multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. SISO and MISO systems are particular instances of a MIMO system. A MIMO channel formed by NTtransmit and NRreceive antennas may be decomposed into NVindependent channels, which are also referred to as spatial channels, where NV≦min{NT,NR}. Each of the NVindependent channels corresponds to a dimension. The MIMO system can provide improved performance (e.g., higher throughput, greater capacity, or improved reliability) if the additional dimensionalities created by the multiple transmit and receive antennas are utilized.

A Zadoff-Chu sequence is a complex-valued mathematical sequence which, when applied to radio signals, gives rise to an electromagnetic signal of constant amplitude, whereby cyclically shifted versions of the sequence comprising the signal do not cross-correlate with each other when the signal is recovered at the receiver. A generated Zadoff-Chu sequence that has not been shifted is known as a “root sequence”. The sequence then exhibits the useful property that cyclic-shifted versions of itself remain orthogonal to one another, provided, that is, that each cyclic shift, when viewed within the time domain of the signal, is greater than the combined propagation delay and multi-path delay-spread of that signal between the transmitter and receiver. Zadoff-Chu sequence is known as a CAZAC sequence (constant amplitude zero autocorrelation waveform). Zadoff-Chu sequences are used in the 3GPP LTE (Long Term Evolution) air interface in the definition of pilot signals (“reference signals” (RS)), random access preamble (PRACH) and HARQ ACK/NACK responses on Physical Uplink Control Channel (PUCCH).

SUMMARY

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key or critical elements nor delineate the scope of such embodiments. Its purpose is to present some concepts of the described embodiments in a simplified form as a prelude to the more detailed description that is presented later.

The subject innovation provides that system(s) and apparatus(es) are provided to wireless communication reference signals are generated in two ways. The first way used for 1 and 2 resource block allocations as well as PUCCH (uplink control channel) spreading consists of arbitrary standard defined sequences stored in random access memory (RAM). The second is with Zadoff-Chu sequences that are generated when needed. A reference signal generator generates post discrete Fourier transform (DFT) reference signals, taking advantage of a relationship between the frequency and time domain versions of the reference signals. This will allow the reference symbol to bypass the DFT engine and the PUCCH signal path to bypass the DFT engine. This will allow the DFT engine clock to be off for power savings.

In one aspect, a method is provided for generation of a reference signal for wireless communication by employing a processor executing computer executable instructions stored on a computer readable storage medium to implement the following acts. A reference sequence is generated in frequency domain. Cyclic time shifts are generated for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. A communication signal is processed using the frequency domain reference signal and time domain transform of the reference signal.

In another aspect, a computer program product is provided for generation of a reference signal for wireless communication comprises at least one computer readable storage medium storing computer executable instructions that when executed by at least one processor implement components. A set of codes causes a computer to generate a reference sequence in frequency domain. A set of codes causes the computer to generate cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. A set of codes causes the computer to process a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

In an additional aspect, an apparatus is provided for generation of a reference signal for wireless communication. At least one computer readable storage medium stores computer executable instructions that when executed by at least one processor implement a means for generating a reference sequence in frequency domain. A means is implemented for generating cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. Means are implemented for processing a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

In a further aspect, an apparatus is provided for generation of a reference signal for wireless communication. A processor operatively coupled to a computer readable medium having stored there on the following computer executable components. A component generates a reference sequence in frequency domain. A component generates cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. A component processes a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

To the accomplishment of the foregoing and related ends, one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and are indicative of but a few of the various ways in which the principles of the embodiments may be employed. Other advantages and novel features will become apparent from the following detailed description when considered in conjunction with the drawings and the disclosed embodiments are intended to include all such aspects and their equivalents.

DETAILED DESCRIPTION

Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.

Furthermore, the terms “code” and “symbol sequence,” or the simpler term “sequence,” are intended to convey the same notion and are employed interchangeably. It is to be noted that in the subject specification the term “code” is also utilized to indicate “computer programming code.” The context of the passages of this description wherein “code” is employed conveys to one of ordinary skill in the art the intended meaning for the subject term; in instances where the context may not be sufficiently clear an explicit reference to the meaning of the term “code” is provided.

Various embodiments are described herein in connection with a wireless terminal. A wireless terminal may refer to a device providing voice and/or data connectivity to a user. A wireless terminal may be connected to a computing device such as a laptop computer or desktop computer, or it may be a self contained device such as a personal digital assistant (PDA). A wireless terminal can also be called a system, a subscriber unit, a subscriber station, a mobile station, a mobile terminal, a mobile, a remote station, an access point, a remote terminal, an access terminal, a user terminal, a user agent, a user device, customer premises equipment, or user equipment. A wireless terminal may be a subscriber station, wireless device, cellular telephone, PCS telephone, cordless telephone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device having wireless connection capability, or other processing device connected to a wireless modem.

A base station may refer to a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminals, and with other base stations through backhaul network communication. The base station may act as a router between the wireless terminal and the rest of the access network, which may include an IP network, by converting received air-interface frames to IP packets. The base station also coordinates management of attributes for the air interface. Moreover, various embodiments are described herein in connection with a base station. A base station may be utilized for communicating with mobile device(s) and may also be referred to as an access point (AP), Node B, evolved Node B (eNodeB), evolved base station (eBS), access network (AN) or some other terminology.

With reference toFIG. 1, a wireless communication system100that utilizes reference signals, which can comprise or be created from Zadoff-Chu (ZC) sequence for a first communicating entity102to encode or spread a signal104that is decoded or despread by a second communicating entity106. In an illustrative aspect, the first communicating entity102is a mobile terminal or user equipment (UE) transmitting on an uplink107and the second communicating entity106comprises a base station or base node. However, it should be appreciated that applications exist as well on a downlink108.

For instance, a ZC sequence lookup table (LUT)110can provide an efficient source of a reference signal for shorter sequences that do not require a large local storage or can be readily downloaded on the downlink108. Alternatively or in addition, a reference signal generator112can provide on-time generation, especially for longer sequences. In an illustrative implementation, the reference signal generator112uses an on-time ZC sequence generator114and an arbitrary sequence generator116to produce a computer generated sequence (CGS) or a ZC sequence. For example, these sequences can be used for an uplink (UL) PUSCH (uplink shared channel) reference signal (RS)118, UL sounding RS120, UL ACK/CQI122, UL PUCCH (uplink control channel) spreading124, and RACH (random access channel)126. The base node106can include a reference sequence generator128to receive these channels.

First, the DFT operation is skipped by directly generating the spectrum of the Chu sequence, which itself is a Chu sequence but with different parameters. Second, to generate a Chu sequence either in the time or in the frequency domain, a recursive formula is used instead of the regular quadratic-exponential formula. Third, in order to perform extension or truncation of the Chu sequence, the recursive formula is stopped earlier or later than the Chu sequence period. In this way, memory copy and transfer operations can be avoided, which otherwise would be required for the extension operation. Fourth, the cyclic shift of the final time domain sequence is performed as a phase ramp in the frequency domain, which requires no additional operations beyond initializing register content in the case of using the recursive generation method.

InFIG. 2, a methodology or sequence of operations200is provided for simultaneous generation of frequency and time domain Chu sequence for use in wireless communication. For instance, a processor can be employed for executing computer executable instructions stored on a computer readable storage medium to implement the following acts. In block202, a reference sequence is generated in frequency domain. In block204cyclic time shifts are generated for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. In block206, a communication signal is processed using the frequency domain reference sequence and time domain transform of the reference sequence. For instance, UE can process by encoding a reference signal or spreading a signal using the reference sequence. As another instance, a base node can process by decoding or despreading using the reference sequence.

Referring now to the drawings,FIG. 3is an illustration of a wireless multiple-access communication system300in accordance with various aspects disclosed in the subject specification. In one example, the wireless multiple-access communication system300includes multiple base stations310a-310cand multiple terminals320a-320c. Further, one or more base stations310a-310ccan communicate with one or more terminals320. By way of non-limiting example, a base station (e.g., base station310a) can be an access point, a Node B, and/or another appropriate network entity. Each base station310provides communication coverage for a particular geographic area302a-c. As used herein and generally in the art, the term “cell” can refer to a base station (e.g.,310a) and/or its coverage area (e.g.,302a) depending on the context in which the term is used.

To improve system capacity, the coverage area302a,302b, or302ccorresponding to a base station310can be partitioned into multiple smaller areas (e.g., areas304a,304b, and304c). Each of the smaller areas304a-304ccan be served by a respective base transceiver subsystem (BTS, not shown). As used herein and generally in the art, the term “sector” can refer to a BTS and/or its coverage area depending on the context in which the term is used. As an example, sectors304a,304b,304cin cell302a(or cells302band302c) can be formed by groups of antennas (not shown) at a base associated with such sector (e.g., base station310a), where each group of antennas is responsible for communication with terminals320a-cin a portion of cell302a,302b, or302c. Such utilization of a specific group of antennas is known as beamforming, wherein multiple antennas are employed to transmit a signal in a directed, localized pattern. For example, base station310serving cell302acan have a first antenna group corresponding to sector304a, a second antenna group corresponding to sector304b, and a third antenna group corresponding to sector304c. In an aspect, each sector304a,304b, and304cin sectorized cell302a(or cells302band302c) can have a sector identifier. Such an identifier can be acquired during cell search. It should be appreciated that various aspects of the innovation described herein can be used in a system having sectorized or unsectorized cells since cell acquisition occurs among a base station and one or more terminals320a-cirrespective of sectorization. Furthermore, all suitable wireless communication networks having substantially any number of sectorized or unsectorized cells are intended to fall within the scope of the hereto appended claims.

For simplicity, the term “base station” (or other terminology that indicates “base station”) as employed herein can refer both to a station that serves a sector as well as a station that serves a cell. While the following description generally relates to a system in which each terminal communicates with one serving access point for simplicity, it should be appreciated that terminals can communicate with any number of serving base stations.

In accordance with one aspect, terminals320a-ccan be dispersed throughout the system300. Each terminal320a-ccan be stationary or mobile. By way of non-limiting example, a terminal can be an access terminal (AT), a mobile station, user equipment, a subscriber station, a wireless device, a cellular phone, a personal digital assistant (PDA), a wireless modem, a handheld device, or another appropriate device that communicates wirelessly.

As an example, the system300can utilize a centralized architecture by employing a system controller330that can be coupled to one or more base stations310a-cand provide coordination and control for the base stations310a-c. In accordance with alternative aspects, system controller330can be a single network entity or a collection of network entities. Additionally, the system300can utilize a distributed architecture to allow the base stations310to communicate with each other as needed. In one example, system controller330can additionally contain one or more connections to multiple networks. These networks can include the Internet, other packet based networks, and/or circuit switched voice networks that can provide information to and/or from terminals320in communication with one or more base stations310in system300. In another example, system controller330can include or be coupled with a scheduler (not shown) that can schedule transmissions to and/or from terminals320. Alternatively, the scheduler can reside in each individual cell302, each sector304, or a combination thereof.

In an example, system300can utilize one or more multiple-access schemes, such as CDMA, TDMA, FDMA, OFDMA, Single-Carrier FDMA (SC-FDMA), and/or other suitable multiple-access schemes. TDMA utilizes time division multiplexing (TDM), wherein transmissions for different terminals320are orthogonalized by transmitting in different time intervals. FDMA utilizes frequency division multiplexing (FDM), wherein transmissions for different terminals320a-care orthogonalized by transmitting in different frequency subcarriers. For instance, TDMA and FDMA systems can also use code division multiplexing (CDM), wherein transmissions for multiple terminals can be orthogonalized using different orthogonal codes (e.g., Walsh codes, Gold codes, Kasami codes, Zadoff-Chu sequences) even though they are sent in the same time interval or frequency sub-carrier. OFDMA utilizes Orthogonal Frequency Division Multiplexing (OFDM), and SC-FDMA utilizes Single-Carrier Frequency Division Multiplexing (SC-FDM). OFDM and SC-FDM can partition the system bandwidth into multiple orthogonal subcarriers (e.g., tones, bins, . . . ), each of which can be modulated with data. Typically, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM. Additionally and/or alternatively, the system bandwidth can be divided into one or more frequency carriers, each of which can contain one or more subcarriers. System300can also utilize a combination of multiple-access schemes, such as OFDMA and CDMA. While the power control techniques provided herein are generally described for an OFDMA system, it should be appreciated that the techniques described herein can similarly be applied to any wireless communication system.

In accordance with an aspect, system300can employ centralized scheduling via one or more schedulers implemented at, for example, system controller330and/or each base station310. In a system utilizing centralized scheduling, scheduler(s) can rely on feedback from terminals320to make appropriate scheduling decisions. As an example, such feedback can include an offset added to receive other sector interference information in order to allow the scheduler to estimate a supportable reverse link peak rate for a terminal320a-c, from which such feedback is received, and to allocate system bandwidth accordingly.

With reference toFIG. 4, in a MIMO-capable communication system400, a transmitter system410(e.g., evolved node (eNB) or base station) and a receiver system450(e.g., access terminal, user equipment (UE)) are depicted. At the transmitter system410, traffic data for a number of data streams can be provided from a data source412to transmit (TX) data processor414. In an embodiment, each data stream is transmitted over a respective transmit antenna. TX data processor414formats, codes, and interleaves the traffic data for each data stream based on a particular coding scheme selected for that data stream to provide coded data. The coded data for each data stream may be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and can be used at the receiver system to estimate the channel response. The multiplexed pilot and coded data for each data stream is then modulated (e.g., symbol mapped) based on a particular modulation scheme (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), multiple phase-shift keying (M-PSK), or M-ary quadrature amplitude modulation (M-QAM)) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream may be determined by instructions executed by processor430; the instructions as well as the data may be stored in memory432. To the accomplishment of that end, processor430can rely on instructions and data structures stored in memory432.

The modulation symbols for all data streams are then provided to a TX MIMO processor420, which may further process the modulation symbols (e.g., OFDM). TX MIMO processor420then provides NTmodulation symbol streams to NTtransceiver (TMTR/RCVR)422Athrough422T. In certain embodiments, TX MIMO processor420applies beamforming weights (or precoding) to the symbols of the data streams and to the antenna from which the symbol is being transmitted. Each transceiver422receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. NTmodulated signals from transceivers422Athrough422Tare then transmitted from NTantennas424Athrough424T, respectively. At receiver system450, the transmitted modulated signals are received by NRantennas452Athrough452Rand the received signal from each antenna452is provided to a respective transceiver (RCVR/TMTR)454Athrough454R. Each transceiver454A-454Rconditions (e.g., filters, amplifies, and downconverts) a respective received signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding “received” symbol stream.

An RX data processor460then receives and processes the NRreceived symbol streams from NRtransceivers454A-454Rbased on a particular receiver processing technique to provide NT“detected” symbol streams. The RX data processor460then demodulates, deinterleaves, and decodes each detected symbol stream to recover the traffic data for the data stream. The processing by RX data processor460is complementary to that performed by TX MIMO processor420and TX data processor414at transmitter system410. A processor470periodically determines which pre-coding matrix to use; such a matrix can be stored in memory472. Processor470formulates a reverse link message comprising a matrix index portion and a rank value portion. Memory472may store instructions that when executed by processor470resulting in formulating the reverse link message. The reverse link message may comprise various types of information regarding the communication link or the received data stream, or a combination thereof. As an example, such information can comprise an adjusted communication resource, an offset for adjusting a scheduled resource, and information for decoding a data packet format. The reverse link message is then processed by a TX data processor438, which also receives traffic data for a number of data streams from a data source436, modulated by a modulator480, conditioned by transceiver454Athrough454R, and transmitted back to transmitter system410. In addition, processor470can process received synchronization channels according, at least in part, to the functionalities associated with synchronization channel processing component. To the accomplishment of the latter, processor470can rely on code instruction and algorithms stored in memory472.

At transmitter system410, the modulated signals from receiver system450are received by antennas424A-424T, conditioned by transceivers422A-422T, demodulated by a demodulator440, and processed by a RX data processor442to extract the reserve link message transmitted by the receiver system450. Processor430then determines which pre-coding matrix to use for determining the beamforming weights and processes the extracted message.

Single-user (SU) MIMO mode of operation corresponds to the case in which a single receiver system450communicates with transmitter system410, as illustrated inFIG. 4and according to the operation described above. It should be appreciated that in the subject mode of operation, inter-cell power can be effected as described hereinbefore. In a SU-MIMO system, the NTtransmitters424A-424T(also known as TX antennas) and NRreceivers452A-452R(also known as RX antennas) form a matrix channel (e.g., Rayleigh channel, or Gaussian channel) for wireless communication. The SU-MIMO channel is generally described by a NR×NTmatrix of random complex numbers. The rank of the channel equals the algebraic rank of the NR×NTchannel. In space-time or space-frequency coding, the rank equals the number of data streams, or layers, that are sent over the channel. It should be appreciated that the rank is at most equal to min{NT, NR}. A MIMO channel formed by the NTtransmit and NRreceive antennas may be decomposed into NVindependent channels, which are also referred to as spatial channels, where NV≦min{NT, NR}. Each of the NVindependent channels corresponds to a dimension or communication layer.

In one aspect, transmitted/received symbols with OFDM, at tone ω, can be modeled by:
y(ω)=H(ω)c(ω)+n(ω).  Eqn. 1
Here, y(ω) is the received data stream and is a NR×1 vector,H(ω) is the channel response NR×NTmatrix at tone ω (e.g., the Fourier transform of the time-dependent channel response matrixh), c(ω) is an NT×1 output symbol vector, and n(ω) is an NR×1 noise vector (e.g., additive white Gaussian noise). Precoding can convert a NV×1 layer vector to NT×1 precoding output vector. NVis the actual number of data streams (layers) transmitted by transmitter410, and NVcan be scheduled at the discretion of the transmitter based at least in part on channel conditions and the rank reported by the terminal. It should be appreciated that c(ω) is the result of at least one multiplexing scheme, and at least one pre-coding (or beamforming) scheme applied by the transmitter. Additionally, c(ω) is convoluted with a power gain matrix, which determines the amount of power transmitter410allocates to transmit each data stream NV. In view of the forward link/reverse link reciprocity of a wireless channel, it should be appreciated that a transmission from MIMO receiver450can also be modeled in the fashion of Eqn. 1, including substantially the same elements. In addition, receiver450can also apply pre-coding schemes prior to transmitting data in the reverse link.

In system400(FIG. 4), when NT=NR=1, the system reduces to a single-input single-output (SISO) system that can provide for sector communication in a wireless communication environment in accordance with one or more aspects set forth herein. Alternatively, a single-input multiple output (SIMO) mode of operation corresponds to NT>1 and NR=1. Furthermore, when multiple receivers communicate with transmitter system410, a multiuser (MU) MIMO mode of operation is established.

With regard to using ZC sequences in a MIMO-capable system, it should be appreciated that ZC sequences are used for Uplink RS (reference signals), Uplink ACK and CQI (channel quality indicators), and potentially uplink sounding RS. Advantageously, a generation of ZC sequences can support features for sequence planning, sequence hopping within a group, and cyclic shift hopping. In particular, such generation can be achieved per hop at both the eNB and UE without having to perform a large, brute force LUT (Look Up Table). As it will be appreciated with the benefit of the present disclosure, on-time generation can support these needs, especially without having to perform a two-step generation of a Chu sequence followed by a Discrete Fourier Transform (DFT) of the Chu sequence.

In an illustrative scenario, consider what the number of ZC sequences are given allowing for all DFT sizes between 12 and 1296 in increments of 12, that can be factorized as powers of {2, 3, 5}. This results in the number of possible sizes being 35. It has been proposed that the number be somewhat further restricted to 12 to 1200 perhaps depending on guard tones for larger bandwidth. The number of ZC sequences for a given length can be determined based upon a definition of a Chu sequence:
x(n)=exp(−j*pi*ξ*n*(n+1)/N),  Eqn. 2
where ξ and N need to be mutually prime and (ξ, N)=1. Thus, given N, one can pick all prime numbers between 1 and N−1 for ξ.

With reference toFIG. 5, from prime number theorem, we know that the number of primes between 1 and N, which is depicted by an exact plot500, can be approximated as:

“Approximation 1” depicted at502:p(N)˜N/(log(N)−1)better for large values of N;

“Approximation 2” depicted at504:p(N)˜N/log(N)better for small values of N.
For a given N, we need all prime numbers between 1 and N−1, which ranges from 5 (N=12) to 210 (N=1296).

Considering the impact of restricted hopping, for a given value of {N, cell ID} only a few sequences are allowed with hopping across different allowed values and hopping at slot boundaries. Given the size of allowed set<=M, then the number of allowed sequences for a given N=Nmax: Nmax=min {p(N−1), M}. It should be appreciated that planned mode is a special case of restricted hopping. Conventionally as depicted inFIG. 6at600, the size of the Look Up Table (LUT) can be quite large. Thus, the eNB would have to store the allowed complex sequences within a cell. The UE can then store those allowed complex sequences applicable to the serving cell and perhaps those of one or more neighboring cells for efficient handoff.

Observations follow then that the LUT size for planned mode is 16.4K complex samples. For restricted hopping mode with M=3, there are 49.2K complex samples. For M=9, there are 148K complex samples. Thus, unless the number of groups within the restricted hopping mode is extremely small, LUT approach is not quite beneficial. For planned mode, LUT looks attractive for eNB. Depending on active set size, it might be attractive for UE as well.

Alternatively or in addition, generation on the fly can be implemented for a Chu sequence:
x(n)=exp(−j*pi*Φ(n))  Eqn. 3
Φ(n)=ξ*n*(n+1)/NEqn. 4
where the phase is recursively determined using the following recursive formula for phase:
Φ(n+1)=Φ(n)+ξ*2*(n+1)/NEqn. 5
Φ(0)=0  Eqn. 6

In an exemplary aspect, Sine/cosine LUT can be constructed separately. A hybrid implementation with both LUT and on-time generation can be used. LUT can be used for small values of N (e.g., persistent Voice over IP (VoIP) assignments on physical uplink shared channel (PUSCH), PUCCH, etc.). On-time generation can be used for larger values of N.

In the exemplary implementation, Chu sequence generation is discussed below including aspects of (1) basic Chu sequence setup for the uplink (UL), (2) Recursive Sequence Generation (RSG) hardware architecture, (3) signaled parameters, and (4) calculated parameters.

BASIC CHU SEQUENCE SETUP. For clarity, inFIG. 7, emphasis is placed on an UL pilot generator700, although it should be appreciated that other CHU sequences can be generated in a similar manner. An input signal xλ(k) at input stage “A” at702is passed to a signal processor (SP)704that is configured to perform as a Discrete Fourier Transform (DFT). Output from SP704at stage “B” at706passes to a tone map component708and is output at stage “C” at710. In turn, an Inverse Fast Fourier Transform (IFFT) component712then produces at stage “D” at714.

Recursive Sequence Generation can use the following formula to generate signal x(k) at stage “B”706:

It should be appreciated that these bit widths are illustrative and that sequences of different bit widths can be implement consistent with aspects disclosed herein.

A list of configuration dependent signaled parameters can comprise:

N′: number of occupied tones (@B), always multiple of 12;

F: RB offset (@C), not Chu sequence specific, will be ignored here;

N: Chu sequence modulus (@A and @B), should be a prime, close to N′;

λ: the base index (@A), g.c.d.(λ, N)=1, if N is a prime then this condition is automatically satisfied. There could be a set of ˜30+ possible λ values specified for each N;

Another parameter (implicit) is the N to N′ sequence transformation; need to specify left or right extension/truncation, no signaling is required for this;

The main goal of this presentation to give the internal mapping:
{N,N′,λ,a}→{α,β,γ}  Eqn. 9

In a first aspect for calculated parameters for the Chu sequence generator, assume N odd and 0≦k≦N−1, instead of −(N−1)/2≦k≦(N−1)/2:
γ=2048·((−1/λ)modN)/N,Eqn. 10
where keeps twenty one (21) fractional bits. As an example: λ=3, N=11→γ=2048·(11−4)/11=1303.272727 . . . .
β=1024·((−1/λ)modN)/N+1024·m(N,λ)+2048·a/12,  Eqn. 11
where keeps 10 fractional bits, m(N, λ) is a stored one bit value mapped to {0, 1}. As an example: λ=3, N=11, a=1→β=1024·(11−4)/11+1024·m(N, λ)+2048/12.
α=a(N,λ),  Eqn. 12
where there is no closed form for this. The values come from a limited set, so indexing is possible. No fractional bits are used, thus value is an integer in the range [0 . . . 2047].

In a second aspect for calculated parameters for the Chu sequence generator, assume N odd and _(N−1)/2≦k≦(N−1)/2 instead of 0≦k≦N−1:
γ=2048·((−1/λ)modN)/N,Eqn. 13
where keeps twenty one (21) fractional bits. An example is: λ=3, N=11→γ=2048·(11−4)/11=1303.272727 . . . .
β=2048·m(N,λ)+2048·a/12,  Eqn. 14
where keeps ten (10) fractional bits and m(N, λ) is calculated as described below.
α=α(N,λ),  Eqn. 15
where the values come from a limited set, so indexing is possible; however closed form solution is given below. An alternative solution is to compute the DC value of the time domain sequence but this is disadvantaged from a complexity perspective. No fractional bits in fixed point α, value is an integer in the range [0 . . . 2047].

Thus, an illustrative number of possible sequences are provided in TABLE 1:

The lower bandwidth (BW) cases are always a subset of higher BW cases, therefore it is sufficient to deal with the 20 MHz option only→35 cases for N. ‘For each N’, it is expected to have ˜9 . . . 12 different λ and 6 . . . 12 different ‘a’ defined.

With regard to sequence segmentation, consider a useful segmentation property: For N odd, it is sufficient to generate the first (N+1)/2 elements, the (N−1)/2 elements in the second half are the mirror image:
x((N+1)/2+k)=x((N−1)/2−k),0≦k<(N−1)/2.  Eqn. 16
For N even, it is sufficient to generate the first N/2 elements, the second half is repeated with alternating sign flip:
x(k+N/2)=(−1)k|1x(k),0≦k<N/2,  Eqn. 17
with the same principle can be used with N/4, N/8 segmentations when 4 or 8 divides N.

Further segmentation is also possible but the sub-segments would then have to be independently generated. Reduces processing by way of parallelization requires multiple hardware blocks.

With regard to sequence extension/truncation, for PUSCH reference signals, the frequency domain signal is extended or truncated, i.e. N′≠N. In LTE, only extension will be used. Generating a truncated sequence is trivial, the unwanted portion can be discarded, or the sequence generator can be stopped before it generates the unwanted portion. Generating an extended sequence can be accomplished by first generating the Chu sequence for length N and then using memory copy operation to create the cyclic extension. This, however, does not give the desired result whenever the cyclic time shift ‘a’ is not zero because the factor corresponding to ‘a’ is not periodic by N′, therefore the cyclically wrapped around portion will not be an identical copy.

A simpler apparatus is just to keep clocking the same algorithm described in this presentation past reaching the Nthelement. This gives the proper extension both from the perspective of the Chu sequence and the cyclic time shift ‘a’.

REFERENCE SIGNAL GENERATOR. Reference signals are generated in two ways. The first way used for 1 and 2 resource block allocations as well as PUCCH spreading consists of arbitrary standard defined sequences stored in Random Access Memory (RAM). The second is with Chu sequences which are generated when needed.

InFIG. 8, a reference signal generator800generates the post DFT reference signals. This will allow the reference symbol to bypass the DFT engine and the PUCCH signal path to bypass the DFT engine. This will allow the DFT engine clock to be off for power savings. Reference sequence requirements for the reference signal generator800in an illustrative implementation can be one sample per clock, sequence is generated in sequential order, can be stalled by downstream block, programmable arbitrary sequences, and mode to alternate reference symbols with 0 for Sounding Reference Signal.

With regard to reference signal generator signals, the following TABLE 2 shows the reference signal generator IO ports.

InFIG. 8, a reference signal generator800outputs from a Chu sequence generator802and an arbitrary sequence generator804are multiplexed at a multiplexer806.

InFIG. 9, an exemplary Chu sequence generator900is depicted. Chu sequences are used as the reference signal for PUSCH. The elements in a Chu sequence are complex samples of magnitude “1” with an increasing phase difference between consecutive elements. This can be implemented as two accumulators902,904and a sine cosine LUT906. The DFT of a Chu sequence results in another sequence. The UE TX hardware can exploit this property to allow for the symbols using Chu sequences to bypass the DFT path in the TX data path.

There are four parameters for the Chu sequence generator. The values for these will come from a systems team look up table converting the pre DFT parameters into post DFT parameters. These LUTs can be implemented in DSP software.

The Chu sequence generator can comply with requirements such as one sample per clock, sequence is generated in sequential order, and normal or complex conjugate output (e.g., software programmable).

With regard to the Chu sequence signals, the following TABLE 3 shows the UE Chu generator IO ports.

With reference toFIG. 9, an illustrative Chu sequence generator900consists of two 32-bit accumulators902,904and a phase-to-rectangular converter906. When the start signal is received, the multiplexers (“muxes”) in the accumulators902,904are set so that alpha and beta are loaded into the registers and a counter is reset to zero. Each subsequent clock cycle will generate a new theta.

The phase to rectangular converter906is implemented as a ⅛ circle sine cosine LUT with 256 entries. Three upper bits of the phase are used to decide if I or Q gets plus or minus sin or plus or minus cosine. The downstream user of the Chu sequence has the ability with the ready_in signal to stall the sequence generator at any time.

Arbitrary sequences can be around 60 sequences, thirty (30) for PUCCH and one resource block (RB) assignments and thirty (30) for two resource block assignments. The PUCCH and one resource block assignments can have twelve (12) entries per sequence. Then two resource block sequences can have twenty four (24) entries per sequence. Requirements for arbitrary sequence generation can comprise one sample per clock, sequence is output in sequential order, and cyclic shift can be applied, can be stalled by downstream block, and can be programmable arbitrary sequences.

Illustrative arbitrary sequence signals depicted for the input/output (IO) ports of the arbitrary sequence generator804(FIG. 8) are depicted in TABLE 4:

With reference toFIG. 10, in an exemplary implementation of an arbitrary sequence generator1000, all the sequences can be stored in memory. A DSP, depicted as control1002initializes a memory, depicted as Random Access Memory (RAM)1004prior to starting transmission. The sequences are stored consecutively in the memory1004. The tasks contain a starting address for the sequence to be used. A counter1006tracks which element in the sequence is being generated. The output of the counter1006is added to the starting address to generate an address to the sequence memory address to get the sample value. The values stored in memory1004post Fast Fourier Transform (FFT) values so that the PUCCH and reference symbols do not need to go through the FFT generator.

An illustrative implementation can provide for sounding reference signal generation. The sounding reference signal (SRS) occupies one OFDM symbol during PUSCH or PUCCH transmission subframe. The eNode-B signals to the UE if it wants a sounding reference transmission. The SRS consists of alternating samples from the reference sequence as described above and 0. The top level of the reference generator will insert the 0 samples into the sequence when the sounding reference is called for.

The PUSCH modulation task and PUCCH tasks have the following SRS parameters.

even (1: sequence on even tones, 0: sequence on odd tones);

symbol (sounding reference transmitted on symbol 0 to 13 of subframe);

CHU SEQUENCE TIME-FREQUENCY DUALITY. To further describe calculations for initializing the generator hardware described above, the Zadoff-Chu sequence of length N is defined as:

X⁡(k)={exp⁢{-j⁢2⁢π⁢⁢γN⁢(12⁢k2+qk)},even⁢⁢Nexp⁢{-j⁢2⁢π⁢⁢γN⁢(12⁢k⁡(k+1)+qk)},odd⁢⁢NEqn.⁢18
where γ, co-prime to N, is called the Chu base index. There is a secondary frequency ramping which is governed by the parameter q. One can show a “duality”: The DFT (or IDFT) of a Chu sequence with base index γ is another Chu sequence with base index δ, with

γδ=−1 mod N

Note that the duality mapping is unique, for γ and/or δ are co-prime to N.

Main Results—The IDFT Theorem (Frequency to Time Translation). Without loss of generality, we assume the frequency-domain Chu sequence X(k) with q=0. More specifically,

The time-domain sequence, x(n), after IDFT is given by

x⁡(n)=∑k=0N-1⁢X⁡(k)⁢exp⁢{j⁢2⁢πN⁢nk},⁢n=0,…⁢,N-1.Eqn.⁢20
For a given base index γ, define γ′ as the unique solution in ZNof

and similarly, γ″ of

The constant term CN(γ) is given by

Moreover, the modulus of CN(γ) is constant regardless of the base index and |CN(γ)|=√{square root over (N)}, which can be shown by comparing the energy of x(n) and X(k).

The DFT Theorem (Time to Frequency Translation). Without loss of generality, we assume the time-domain Chu sequence x(n) with q=0. More specifically,

X⁡(k)=∑n=0N-1⁢x⁡(n)⁢exp⁢{-j⁢2⁢πN⁢nk},⁢k=0,…⁢,N-1.Eqn.⁢24
is also a Chu sequence

PROOF. We will only derive the IDFT theorem. The co-prime condition gcd(γ, N)=1 is a key to our proof. There exist a γ′ in ZNand an integer “a” such that
γγ=aN+1.  Eqn. 26

Note that γγ′≡1 mod N and

Let γγ″≡−1 mod N. Substituting (γγ′)2≡1 mod N, one has γγ″≡−γ2γ′2, and thus

Let k′=k−γ′n, one has

∑k=0N-1⁢exp⁢{-j⁢2⁢π⁢⁢γN⁢12⁢(k-γ′⁢n)2}=∑k′=-γ′⁢nN-1-γ′⁢n⁢exp⁢{-j⁢2⁢π⁢⁢γN⁢12⁢k′2}=∑k′=0N-1⁢exp⁢{-j⁢2⁢π⁢⁢γN⁢12⁢k′2},(since⁢⁢exp⁢{-j⁢2⁢π⁢⁢γN⁢12⁢k2}⁢is⁢⁢periodic⁢⁢in⁢⁢k⁢⁢with⁢⁢period⁢⁢N⁢⁢for⁢⁢⁢even⁢⁢N.)=CN⁡(γ)Eqn.⁢29
Hence, one has

Since −γγ′2≡γ″ mod N, there exists an integer b such that −γγ′2=bN+γ″. So

Since γγ″≡1 mod N, one can write γγ″=cN−1. We claim the integers “b” and “c” have the same parity. To see this, multiply both sides of −γγ′2=bN+γ″ by γ, and use γγ′=aN+1. One has
−(aN+1)2=bNγ+cN−1−α2N−2a=bγ+c.

Since N is even and is co-prime to γ, γ must be odd. Therefore, bγ and b have the same parity, and b+c must be even which shows b and c have the same parity.

Thus, one has

x⁡(n)=CN⁡(γ)⁢exp⁢{-j⁢2⁢πγ″N⁢12⁢n2}⁢exp⁢{-j⁢⁢c⁢⁢n⁢⁢π}.
It is interesting to see that depending on the parity of “c”, the time-domain sequence may have {1, −1, 1, −1, . . . } alternating phase ramping. Next, we characterize such a frequency ramping parameter.

Similar to the case of even N, the first term equals to CN(γ), and hence

COMPUTER SIMULATIONS. We verify the above analytical results via computer simulations.

N=64: The index mapping table (γδ(γ″)) for N=64 is given in TABLE 5 by

InFIG. 11, the absolute value of CN(γ) for N=64 is depicted as constant (equals to √{square root over (N)}) at1100and its phase varies with base index as depicted at1102.

N=71: The index mapping table (γδ(γ″)) for N=71 in TABLE 6 is given by

InFIG. 13, a depiction of amplitude1300and phase1302is provided for CN(γ) for N=71.

InFIG. 14, a depiction1400is given for numerical versus closed-form calculation of IDFT depicted at1400and of DFT depicted at1402of Chu Sequence (N=71).

CHU SEQUENCE AND CGS GENERATION—SUMMARY. Chu sequences and Computer Generated Sequences (CGS) are used for various purposes in the LTE UL. The following is a summary of their UL applications:

PUSCH DM-RS for ≧3RB and SRS with more than 36 tones or more: Extended Chu sequence (periodically extended in the frequency domain); and

We first describe the proposed Chu sequence generator structure and then describe how the same structure can be adapted to generate CGS.

The generic Chu sequence generator formula is given below:

Note the following:

When extended Chu sequences are used, N is always prime, N is odd, and any 1≦λ<N is possible. The only non-extended Chu sequence is the RACH sequence, which is also prime length, so the same holds in general for all LTE Chu sequences.

While φ=0 is true for the un-modulated Chu sequence, any modulation of the Chu sequence could be carried out by adjusting φ. For example, for carrying out QPSK modulation, we can use φε{π/4, 3π/4, 5π/4, 7π/4}.

The sequences are generated in the frequency domain so that the generated sequence can be directly input to the tone mapping. Referring again toFIG. 7where the generated sequence, either Chu or CGS, will be input in Stage B706. Due to the frequency-domain sequence generation, the time domain shifts of the Chu sequences are implemented as phase ramp.

Recursive Sequence Generation. With reference toFIG. 15, since the Chu sequence follows a quadratic-exponential formula, we can generate the phase of the sequence elements with a recursive formula depicts graphically at1500. Conceptually, the hardware generator1500can be described mathematically as

The above recursive equations lead to the following quadratic formula

With the fixed point implementation, the generator signal x(k) is given as

The definition of the various parameters used inFIG. 15is as follows:

LUT: Sin/Cos look up table defined as

φ(k): Output phase, used to address sin/cos look up table (LUT);

γ: Phase acceleration (external parameter) related to the Chu sequence index if the sequence is defined in the frequency domain and is generated in the frequency domain, or related to the negative inverse of the Chu sequence index if the sequence is defined in the time domain and is generated in the frequency domain;

β: Constant phase increment (external parameter); consists of three components: (1) Offset equals to γ; (2) Phase ramp corresponding to cyclic time shift; (3) Fourier transform parameter, which is zero if the sequence is defined in the frequency domain and is generated in the frequency domain and non-zero if the sequence is defined in the time domain and is generated in the frequency domain;

α: Constant phase (external parameter); consists of two components: (1) Modulation symbol phase, if modulation is incorporated in the sequence generator; and (2) Fourier transform parameter, which is zero if the sequence is defined in the frequency domain and is generated in the frequency domain and non-zero if the sequence is defined in the time domain and is generated in the frequency domain.

The frequency domain extension of the Chu sequence can be created by simply continuing to clock the recursive generator. Since the Chu sequence naturally wraps around with period N, this gives a perfect extension from length period N to length N′, except for fixed point rounding errors. The frequency domain phase ramp used to carry out the time domain cyclic shift wraps around with period N′, rather than with period N, but this is also properly handled by the continued use of the recursive generator.

As mentioned above, some of the parameter values are external parameters; however, they may not be signaled directly in general. In the following subsection, we describe the signaled parameters and their conversion to sequence generator input parameters.

Calculating Input Parameters—PUSCH DM-RS. The reference signal for PUSCH of 3RB or larger is a Chu sequence specified directly in the frequency domain (and thus no DFT operation inFIG. 7).

x⁡(k)=exp⁢{-j⁢2⁢π⁢⁢kSN′}⁢exp⁢{-j⁢π⁢⁢qk⁡(k+1)N},0≤k<N′,Eqn.⁢38
where N′: number of occupied tones (Stage B706,FIG. 7), always multiple of 12, N: Chu sequence natural length (Stage B706,FIG. 7), largest prime number less than N′, q: the root of Chu sequence; and S: time domain shift, x(n−S), as implemented as a frequency ramping.

From equation

we can computer the input parameters to the hardware generator α=0;

The notation ODRULFmeans the Odd Dithered Rounding to an unsigned number of I-integer bits and F-fractional bits.

Calculating Input Parameters—PRACH (Physical Random Access Channel). The PRACH signal is a natural length Chu sequence specified in the time domain. It is applied, after DFT, to frequency domain. A closed form formula has been found for the DFT of a Chu sequence based on which we can compute the hardware input parameters.

In the following, we give a list of signaled parameters. Referring back toFIG. 7, the following notation is used:

N′: number of occupied tones (Stage B706), always multiple of 12;

F: RB offset (Stage C710), not Chu sequence specific, will be ignored here;

N: Chu sequence modulus (Stage A702and Stage B706), greatest prime number less than N′;

λ: the base index (Stage A702), g.c.d.(λ, N)=1. Since N is a prime, this condition is automatically satisfied. There could be a set of ˜30 possible λ values specified for each N; and

a: time shift value (Stage D714), should be from the set {0, 1, . . . , 11}. The actual signaled parameter can be the parameter value itself or an index pointing to the parameter value within a standard set.

Next, we give the internal mapping: {N, N′, λ, a}←→{α, β, γ}. Note that the assumed example bit resolutions are the same as inFIGS. 7 and 15.
γ=2048·((−1/λ)modN)/N;Keep 21 fractional bits

Note that in the above, the following notation was used:

The values come from a limited set, so indexing should be possible; however, closed form solution is given below. Alternative solution is to compute the DC value of the time domain sequence but this is disadvantaged from a complexity perspective. No fractional bits in fixed point α, value is an integer in the range [0 . . . 2047].

Storing the Sequence Generator Input Parameters. The closed form calculations can be avoided if parameters {α, β, γ} are stored. In order to determine the required memory to support this, first consider the number of cases for N′ as shown in TABLE 7 below.

As it can be seen from TABLE 7, there are 33 distinct sequence length cases for the PUSCH DM RS and one length case for the PRACH.

Assume that for each N′, 30 sequence indices are defined. Then the storage requirements can be calculated as shown in TABLE 8.

TABLE 8Parameter Storage Memory Requirements for Time Domain Chu SequencesGenerated in the Frequency DomainParameterBit-widthMemory Requirement (bits)γ3233*30*32 = 31680β2133*30*21 = 20790α1133*30*11 = 10890

If we wanted to calculate the parameters in TABLE 8 instead of storing them, then for γ, for example, a search for integer reciprocal would be required, which is prohibitively costly.

If the Chu sequences are defined in the frequency domain, then the parameter calculation is simplified since α doesn't need to be calculated and there are only 12 cyclic shift cases for β. The resulting storage requirements are shown in TABLE 9.

TABLE 9Parameter Storage Memory Requirements for Frequency Domain ChuSequences Generated in the Frequency DomainBit-MemoryParameterwidthRequirement (bits)γ3233*30*32 = 31680β2133*12*21 = 8316α110

If we wanted to calculate the parameters {α, β, γ} in TABLE 9 instead of storing them, it would involve only an integer division and binary shift. However, integer division can be costly in hardware, therefore storing the parameter values might be considered. Note that combining parameter storage and calculation can also be implemented, i.e., storing one parameter type while calculating another type.

Sequence Segmentation. Further simplifications could be achieved by using certain properties of the Chu sequences:

For N odd, it is sufficient to generate the first (N+1)/2 elements, the (N−1)/2 elements in the second half are the mirror image
x((N+1)/2+k)=x((N−1)/2−k),0≦k<(N−1)/2  Eqn. 41

For N even (doesn't occur in LTE), it would be sufficient to generate the first N/2 elements, the second half is repeated with alternating sign flip
x(k+N/2)=(−1)k+1x(k),0≦k<N/2  Eqn. 42

Same principle can be used with N/4, N/8 segmentations when 4 or 8 divides N

Further segmentation is also possible but the sub-segments would then have to be independently generated. This reduces processing time by way of parallelization; but it requires multiple hardware blocks.

CGS Sequence Generation. Computer Generated Sequences (CGS) can be generated with the same structure as shown inFIG. 15. The recursive sequence generator1500is used only to generate the phase ramp sequence corresponding to the required cyclic time shift. Input parameter γ is set to zero. Input parameter α can also be set to zero, or alternatively, α can be set to the phase value corresponding to the PUCCH sequence spreading (Hadamard or DFT) or to the CQI data modulation. The latter options avoid an element-wise phase offset after the sequence generation. However, if digital gain is applied to the frequency domain sequence then there is no real savings with this solution.

CGS are frequency domain QPSK sequences, so the discrete sequence elements need to be stored. Since the structure shown inFIG. 15only generates the phase ramp sequence, the QPSK element-wise modulation needs to be applied separately. This can be easily achieved by the following operation modifying φ(k):
φ′(k)=(φ(k)+256+512·s(k))mod 2048  Eqn. 43
where an 11-bit LUT address space is assumed and s(k)ε{0, 1, 2, 3} represents the F-QPSK modulating sequence.

Note that since the LUT only contains the first half-quadrant of the unit circle, i.e., the values corresponding to φ(k)=0, 1, . . . , 255, the modulation operation described above doesn't actually change the LUT address but rather changes the sign and I-Q swap operations that are controlled by the 3 MSB of φ(k).

The storage requirements could be reduced by using the fact that some of the sequences are frequency reversed (time conjugate) or frequency conjugate (time reversed) versions of another sequence; however, considering the moderate storage requirements, this option seems unnecessary complication.

Fixed Point Implementation. Here we consider bit-width options for the Chu sequence generator. The conclusions are directly applicable to the CGS generator as well.

An illustrative fixed point implementation is used to simulate the various bit-width options. The following settings were assumed: (a) Sequence length=1201 (CHUTestSize=1201); (b) Sequence Extension Off; (c) DFT On (CHUTestDFT=1); (d) Lambda=27 (CHUTestLambda=27); and (e) Cyclic shift=⅔ of symbol length (CHUTestB=8, CHUTestBN=12).

In the first set of results, we compare various options for the look up table (LUT) implementation.FIG. 16shows results corresponding to the different LUT cases. For these results, we used the following settings: (a) CHUAlphaBits=ChuPhaseBits; (b) CHUBetaBits=21; and (c) CHUGammaBits=30.

InFIG. 16, a graphic1600is depicted for Chu Sequence SNR and LUT memory size as a function of LUT address size (Phase Bits) and LUT data bit-width (LUT bits). For each case, there are two curves included, one shows the output sequence SNR (referenced to the left y-axis), the other shows the total LUT size (referenced to the right y-axis). SNR plots are depicted for thirteen (13) phase bits1601, twelve (12) phase bits1602, eleven (11) phase bits1603, ten (10) phase bits1604, nine (9) phase bits1605, and eight (8) phase bits1606. LUT plots are depicted for thirteen (13) phase bits1607, twelve (12) phase bits1608, eleven (11) phase bits1609, ten (10) phase bits1610, nine (9) phase bits1611, and eight (8) phase bits1612.

Based on the results shown inFIG. 16, assuming a required minimum SNR of 50 dB, the optimum choice is 10 phase bits paired with 9 LUT data bits. The resulting data structure is: (a) 128 values of sin(φ) each quantized to 9 bits; and (b) 128 values of cos(φ) each quantized to 9 bits, which results in a total LUT size of 288 bytes.

Note that we can use the fact that the LUT data sign is always positive for the stored values, which reduces the required number of bits by one; therefore the LUT can be implemented using 256 bytes of memory. Note that the above is a change relative to the earlier assumption of 11-bit phase and 8-bit data.

Using 11-bit phase and 9-bit data would improve SNR by about 1 . . . 2 dB at the cost of doubling the LUT size. This is also a possible option; the final decision should be made based on hardware cost.

Next, we look at the required phase ramp (β) bit resolution.FIG. 17shows at1700results corresponding to the different phase ramp bit-width settings, in particular Chu sequence SNR as a function of phase ramp (Beta) bit resolution. For these results, the following was assumed: (a) CHUAlphaBits=ChuPhaseBits=10; and (b) CHULUTBits=9. The remainder of the simulation assumptions was as described earlier. As it can be seen fromFIG. 17, twenty one (21) bits seem to be a good choice, which matches the earlier assumption.

Next, we look at the SNR sensitivity to the phase acceleration (γ) bit resolution. The earlier assumption was CHUGammaBits=32; however, with the BPM fixed point implementation, only up to 30 bit resolution can be supported, therefore we tested up to 30 bit accumulator length. The assumptions were as follows:

DFT Off

The SNR was evaluated by finding the minimum SNR for any sequence with any possible sequence index 1≦λ<1201. We show the results for minimum Chu sequence SNR as a function of phase acceleration (Gamma) bit resolution at1800inFIG. 18. CHUGammaBits=30 is shown to give acceptable performance. However, the recommendation is to use CHUGammaBits=32 as originally assumed.

Fixed Point Simulation Conclusion. Based on the results presented here, the following recommendations are given: (a) CHUAlphaBits=ChuPhaseBits=10; (b) CHULUTBits=9; (c) ChuBetaBits=21; and (d) ChuGammaBits=32. ChuGammaBits=31, 30 are also acceptable choices.

Performance Results. The initial performance results have been presented above. With the recommended bit-widths, the generated sequence SNR will be above 50 dB. Note that the subsequent IFFT operation may limit the achievable SNR to a lower value.

InFIG. 19, a serving radio access network (RAN), depicted as an evolved base node (eNB)1900, has a computing platform1902that provides means such as sets of codes for causing a computer to generate a reference sequence for wireless communication. In particular, the computing platform1902includes a computer readable storage medium (e.g., memory)1904that stores a plurality of modules1906-1910executed by a processor(s)1920. A modulator1922controlled by the processor1920prepares a downlink signal for modulation by a transmitter1924, radiated by antenna(s)1926. A receiver1928receives uplink signals from the antenna(s)1926that are demodulated by a demodulator1930and provided to the processor1920for decoding. In particular, component (e.g., module, set of codes)1906is provided for generating a reference sequence for wireless communication. Component (e.g., module, set of codes)1908is provided for generating cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. Component (e.g., module, set of codes)1910is provided for processing a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

With continued reference toFIG. 19, the mobile station or user equipment (UE)1950, has a computing platform1952that provides means such as sets of codes for causing a computer to perform generation of a reference sequence for wireless communication. In particular, the computing platform1952includes a computer readable storage medium (e.g., memory)1954that stores a plurality of modules1956-1958executed by a processor(s)1970. A modulator1972controlled by the processor1970prepares an uplink signal for modulation by a transmitter1974, radiated by antenna(s)1976as depicted at1977to the eNB1900. A receiver1978receives downlink signals from the eNB1900from the antenna(s)1976that are demodulated by a demodulator1980and provided to the processor1970for decoding. In particular, component (e.g., module, set of codes)1956is provided for generating a reference sequence in frequency domain. Component (e.g., module, set of codes)1957is provided for generating cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. Component (e.g., module, set of codes)1958is provided for processing a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

With reference toFIG. 20, illustrated is a system2000for generation of a reference sequence for wireless communication. For example, system2000can reside at least partially within user equipment (UE). It is to be appreciated that system2000is represented as including functional blocks, which can be functional blocks that represent functions implemented by a computing platform, processor, software, or combination thereof (e.g., firmware). System2000includes a logical grouping2002of electrical components that can act in conjunction. For instance, logical grouping2002can include an electrical component for generating a reference sequence in frequency domain2004. For another instance, logical grouping2002can include an electrical component for generating cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence2006. Further, logical grouping2002can include an electrical component for processing a communication signal using the frequency domain reference signal and time domain transform of the reference signal2008. Additionally, system2000can include a memory2014that retains instructions for executing functions associated with electrical components2004-2008. While shown as being external to memory2014, it is to be understood that one or more of electrical components2004-2008can exist within memory2014.

InFIG. 21, an apparatus2102is provided for generation of a reference sequence for wireless communication. A means2104is provided for generating a reference sequence in frequency domain. A means2106is provided for generating cyclic time shifts for a time domain transform of the frequency domain reference sequence by generating a phase ramp sequence. A means2108is provided for processing a communication signal using the frequency domain reference signal and time domain transform of the reference signal.

As it employed herein, the term “processor” can refer to a classical architecture or a quantum computer. Classical architecture is intended to comprise, but is not limited to comprising, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Quantum computer architecture may be based on qubits embodied in gated or self-assembled quantum dots, nuclear magnetic resonance platforms, superconducting Josephson junctions, etc. Processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

Furthermore, in the subject specification, the term “memory” refers to data stores, algorithm stores, and other information stores such as, but not limited to, image store, digital music and video store, charts and databases. It will be appreciated that the memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). Additionally, the disclosed memory components of systems or methods herein are intended to comprise, without being limited to, these and any other suitable types of memory.

What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “includes,” “including,” “possess,” “possessing,” or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.