Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique

A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.

BACKGROUND

1. Field of the Invention

This invention relates generally to testing and diagnostics of line processes used for the manufacture of integrated circuit devices, and more particularly to the measurement and monitoring of the charging status in a gate dielectric layer of a test structure during semiconductor processing steps.

2. Background of the Invention

The manufacture of large-scale integrated circuits involves hundreds of discrete processing steps. These steps are typically divided into two sub-processes. The first of these sub-processes is often referred to as the front-end of line (FEOL) sub-process during which the semiconductor devices are formed within a silicon wafer. The second of the sub-processes is often termed the back-end of line (BEOL) sub-process during which various metal interconnecting layers and contacts are formed on top of the semiconductor devices formed during the FEOL sub-process.

Many of the processing steps comprising the FEOL and BEOL sub-processes involve depositing layers of material, patterning the layers by photolithographic techniques, and then etching away unwanted portions of the deposited material. The deposited materials primarily consist of insulators and metal alloys. In some instances the pattern layer serves as temporary protective mass, while on others they are functional components of the integrated circuit chips being formed.

Radio frequency (RF) plasmas are often used in many of the processing steps, especially in the processing steps comprising the BEOL sub-process. For example, RF plasmas are used in Reactive Ion Etching (RIE), which is used to etch the layers of material as described above. RIE provides the etching anisotropy required to achieve the requisite high degree of pattern definition and precision and the requisite precision dimensional control. In RIE, gaseous chemical etching is assisted by unidirectional ion bombardment provided by an RF plasma. Photo-resist layers, used in the photolithographic patterning described above, are also frequently removed using plasma ashing.

Unfortunately, the numerous exposures to the RF plasmas, and other forms of ionic radiation, results in radiation damage and the accumulation of charge on exposed conductive components, which leads to damaging current flows and trapped charges affecting the semiconductor devices and integrated circuit chips being formed. The surfaces of the patterned semiconductor wafer present multiple areas of conductors and insulators to the RF plasmas. The multiple areas of conductors and insulators produce local non-uniformities in the plasma currents, which can result in charge build up on the electrically floating conductor surfaces. This charge build up can produce the damaging current flows and can affect the threshold voltages for semiconductor structures formed on the silicon wafer.

The semiconductor devices often comprise some form of field effect transistor comprising a gate, drain, and source regions. The mechanism of current flow through the oxide layer forming the gate is primarily the result of Fowler-Nordheim (FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electro potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 Å. Such potentials are easily achieved in conventional plasma reactors used to generate RF plasmas and semiconductor processing. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide layer forming the gate, which can lead to subsequent dielectric breakdown.

As the semiconductor wafer is exposed to successive processing steps, the damage or potential damage is increased. As a result, efforts are made to assess the damage produced in the various semiconductor processing steps. For example, one common way to test for the level of damage is to produce test wafers or test chips comprising structures designed to measure, or allow measurement of, the damage produced by various processing steps.

Test structures are typically formed within a specifically designated test site on a semiconductor wafer being processed. Alternatively, entire wafers can be devoted to providing a plurality of test structures for process monitoring. Thus, the test structures are run through the process which results in charge build up that can be then measured. A common method for measuring the charging status is to use Capacitance-Voltage (CV) techniques or floating gate testers. Such conventional techniques, however, are often unsatisfactory for the semiconductor industry because of their low sensitivity, high test chip cost, or long delay time associated with the production of data related to the testing.

For example, conventional CV method can only be used for processes with uniform charging effect. In other words, for processes that result in charge accumulating at the edge of the gate structure, conventional CV methods will suffer from insufficient capacitance change produced by the trapped charges. The insufficient capacitance change will render conventional CV methods insufficient for monitoring the charging status.

SUMMARY

A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a shift in the flatband voltage (Vfb) has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.

These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.”

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The systems and methods described herein are directed to simple capacitor-like test structures that can be used to reduce test wafer costs and shorten the delay time for producing test data that can be used to modify the semiconductor processes at issue in order to reduce damage resulting from charge accumulation during processing steps.

As described above, there are many semiconductor processing steps that can induce a charging effect onto the gate dielectric layer of a semiconductor structure, causing threshold voltage shifts and/or gate dielectric degradation. For memory devices including floating gate devices, such as EEPROMs and flash devices, and charge-trapping devices, such as SONOS devices, the charging effect will result in a wide initial threshold voltage distribution, which can impact the device's operation window. The charging effect can result from various electric fields, plasmas, or radiation, such as UV light, to which a semiconductor wafer is exposed during semiconductor processing.

FIGS. 1A-1Care diagrams illustrating various views of an example semiconductor test structure100configured in accordance with one embodiment of the systems and methods described herein.FIG. 1Ais a diagram illustrating a top view of test structure100. As can be seen, test structure100comprises a gate electrode102and a diffusion region106.FIG. 1Bis a perspective view of test structure100illustrating that diffusion region106sits atop a substrate108. For example, substrate108can be a bulk Si substrate.FIG. 1Cis a diagram illustrating a cross section of test structure100along line A-A′. In the cross-sectional view ofFIG. 1C, charge-trapping layer104can be seen. Charge-trapping layer can reside under electrode102and over diffusion region106.

Charge-trapping layer104is a dielectric layer designed to trap charges within structure100. In one embodiment, charge-trapping layer104comprises an oxide-nitride-oxide structure. In another embodiment, charge-trapping layer104comprises an oxide-Si-oxide structure, such as a SiO2-Si—SiO2 structure. It will be apparent, however, that any dielectric layer or structure that can be used to trap charge in accordance with the systems and methods described below can be used for charge-trapping layer104.

Gate electrode102can comprise a polysilicon layer depending on the embodiment. In one embodiment, substrate108is a P-type substrate, while diffusion region106comprises an N-type region. In other embodiments, substrate108can be a N-type substrate, while diffusion region106is a P-type region.

As illustrated inFIG. 2, diffusion region106and gate electrode102can be metallized with metal layers202and204respectively. For example, in one embodiment, metal layers202and204can be metal silicide layers. Metallizing diffusion region106and gate electrode102can reduce the resistance associated with diffusion region106and gate electrode102.

Testing of structure100can be accomplished by directly probing on diffusion region106and gate electrode102. Alternatively, interconnection leads, such as interconnection lead206, can be connected with metal layers202and/or204. These interconnection leads can then be probed in order test the charging status of structure100.

Thus, test structure100can be subjected to the process steps being monitored. This will result in charge being imparted to charge-trapping layer104during the various process steps. The charge can be imparted, as explained above, by an electric field, plasma, charge particles, radiation (UV) or other sources. The amount of charge or charge status in charge-trapping layer104can then be monitored by probing gate electrode102and diffusion region106or interconnection leads attached thereto.

It should be noted that diffusion region106can be formed before or after the process steps being tested are performed depending on the embodiment.

FIG. 3is a diagram illustrating how various processing steps can result in trapped charges304residing in trapping layer104of test structure100. For example, charge304can be trapped as a result of high-energy charges301produced by a plasma300, a large e-field produced by a processing step, or UV radiation302. By subjecting test structure100to the processing step and exposing it to one of these sources, the charging of test structure100can be monitored to determine if the charging of test structure100is uniform or non-uniform, e.g., the process results in an edge charging effect for test structure100.

This can be illustrated in conjunction withFIGS. 4,5A, and5B.FIG. 4illustrates that when test structure100is subjected to UV radiation402, charge404will be induced into layer104of test pattern100. A CV measurement for test structure100, e.g., as illustrated inFIG. 5B, can then be performed. The graph ofFIG. 5Billustrates that as the voltage applied to gate electrode102of test structure100is increased, the test structure will go through an accumulation, depletion, and then inversion stages. The point separating accumulation from inversion is referred to as the flatband voltage (Vfb). Inversion occurs once the gate voltage exceeds the threshold voltage (Vt).

When charge404is trapped in trapping layer104, however, charge404will block charge406flowing between diffusion region106so that the curve ofFIG. 5Bcan only be measured at higher gate voltages. In other words, the curve illustrated in5B shifts to the right when induced charge404is trapped in trapping layer104.

This shift to the right of the curve inFIG. 5Bcan be referred to as a Vfb shift. This shift will only occur, however, if UV radiation402caused uniform injection of charge404into trapping layer104. If, on the other hand, the induced charge is not uniform, then the delayed inversion point scenario illustrated inFIG. 5Bwill exist. The delayed inversion point refers to the bottom side of the curve inFIG. 5B. The curve inFIG. 5Bactually represents a plurality of curves, each different curve representing the CV measurement for test structure100after an increasing amount of stress, or UV exposure time.

For example, in the case where test structure100has experienced an edge charging effect as inFIG. 5A, then the induced charge will not be uniform and the right hand side of the curve inFIG. 5Bwill push out gradually with increased UV exposure. This delayed inversion point can then be monitored in order to determine the charging status of test structure100. The monitored charged status can then be used to modify the process step being tested.

As illustrated inFIGS. 6-11, test structures comprising different test patterns can be designed for different process-monitoring purposes. For example,FIG. 6illustrates several example shapes that can be used for gate electrode102depending on the embodiment. Thus, depending on the embodiment, test structure100can comprise a circular gate electrode502, a square gate electrode504, a star-shaped gate electrode506, etc. A more complex shape can be used for gate electrode102depending on the process being monitored. For example, a gate electrode508with a plurality of fingers508acan be used in certain embodiments of test structure100. Other embodiments of test structure100can use a gate electrode512that includes a plurality of long lines512a.

Gate electrodes can be configured with a different axis of orientation as well. For example, gate electrode508can be oriented along a horizontal axis of orientation or a vertical axis of orientation as illustrated inFIG. 6. Similarly, gate electrode512can be oriented along a horizontal axis or a vertical axis as required by a specific embodiment.

As would be understood, the charging effect that occurs during the various processing steps is a result of various conductive layers and areas acting like an antenna that attract charge produced during the various processing steps. Configuring gate electrodes with, e.g., long fingers508aor long lines512acan increase or decrease this antenna effect, which can be used to produce more relevant or accurate test data.

In other embodiments, gate electrodes configured in various shapes can be combined with oxide regions in a manner configured to achieve the desired testing for different processes and monitoring purposes. For example,FIG. 7is a diagram illustrating a gate electrode508and a gate electrode512combined with a partial oxide region602to form a test structure600. Test structure600can, for example, be used to test for the antenna effect referred to above. In other embodiments, partial oxide region602can be combined with a gate electrode508alone or a gate electrode512alone. Further, in other embodiments, other gate electrodes of various shapes and orientations can be combined with oxide region602.

FIG. 8is a diagram illustrating a test structure700comprising a circular gate electrode502surrounded by an oxide region702. Test structure700can be used to isolate a leakage path within test structure700. Again, it will be clear that other gate electrodes comprising other shapes and/or orientations can be combined with oxide region702depending on the embodiment.

In other embodiments, the diffusion region can be separated into two or more regions, e.g., by the gate electrode structure. For example, the diffusion region can be separated into source and drain regions as would be found in a MOSFET structure.FIG. 9is a diagram illustrating an example test structure800comprising a gate electrode802separating a drain region804and source region806. Drain and source region can be formed in substrate808.FIG. 10is a diagram illustrating another test structure900comprising a drain region904and source region906separated by a gate electrode902.

It will be clear that a plurality of diffusion regions can also be included in a test structure configured as described herein. For example,FIG. 11is a diagram illustrating a test structure1000comprising four diffusion regions,1004,1006,1008, and1010, separated by gate electrode1002. In general any number of diffusion regions required to achieve the test data being sought can be included within the test structure configured in accordance with the systems and methods described herein. Further, the shape of the gate electrode can be varied as required to achieve the test data being sought and to separate the various diffusion regions.

When the diffusion region is separated into two or more regions, as with the embodiments ofFIGS. 9-11, the charging effect can be measured for each diffusion region independently. This can be illustrated with the aid of the test structure illustrated inFIG. 12.FIG. 12illustrates a test structure1100comprising a gate electrode1102separating a drain diffusion region1106and the source diffusion region1110formed on substrate1108. The charge effect can be determined by applying certain bias voltages to gate electrode1102, drain1106, and source1110and then monitoring the delayed inversion point.

Multiple test structures can be laid out with different orientations, e.g., in order to provide information related to an isotropic charging effect. InFIG. 13, for example, a plurality of test structures1100are laid out in a pattern1300. As can be seen, test structure1100and pattern1300can have vertical, horizontal, or diagonal orientations. A pattern of test structures, such as pattern1300with varying orientations can be useful in providing an isotropic charging effect information. It will be apparent that other test structure patterns can comprise more or less test structures along with more or less orientations. Further, a test pattern can comprise test structures with different shapes and dimensions as well as different orientations.

As mentioned above, the size, shape, and orientation of a test structure, gate electrode, and/or diffusion regions can be varied to achieve the desired test data.FIGS. 14 and 15illustrate two example embodiments of test structures1400and1500respectively that are slightly more complex than the previous structures illustrated above. It will be clear, however, that the embodiments described herein are by way of example only and that the particular test structures described should not be seen as limiting the systems and methods described herein to any particular test structures, shapes, orientations, or levels of complexity.

FIG. 15is a diagram illustrating a test structure1500in accordance with one embodiment of the systems and methods described herein. Test structure15comprises a gate electrode1504separating a plurality of diffusion regions1506-1522, formed on a substrate1502.FIG. 14is a diagram illustrating a test structure1400configured in accordance with another embodiment of the systems and methods described herein. Test structure14comprises a circular gate electrode1404separating diffusion regions1406-1420formed on substrate1402.

A plurality of test structures, such as those described above, can be arranged on a single wafer, either in the scribe line or in the chip area, for process monitoring. As mentioned, multiple test structures can be arranged comprising different shapes and orientations. Further, one or more of the test structures can be packaged into a discreet device as a sensing element for plasma or radiation detecting.

While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.