Power amplifier system

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

FIELD OF THE DISCLOSURE

The disclosure relates generally to power amplifier systems of radio frequency transmitters and in particular to power amplifier systems that provide bias signals for amplifiers over a wide range of temperature.

BACKGROUND

A power amplifier is used to amplify radio frequency signals to be transmitted from an antenna of a wireless device such as a mobile telephone. A number of conventional power amplifiers employ bias circuitry that provides an inadequate bias signal level when the radio frequency signals reach a peak power level. As such, these conventional power amplifiers often suffer from output signal distortion at peak power levels. For example, the inadequate bias signal level results in amplitude modulation-amplitude modulation distortion that can cause an out-of-specification adjacent channel leakage ratio. Thus, a power amplifier system having a bias circuitry that provides adequate bias signal levels over a wide range of input power levels and associated temperature changes is needed.

SUMMARY

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also include is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input.

In exemplary embodiments, the power amplifier system further includes a controller having a communication port in communication with the first digital input of the first digital-to-analog converter and a digital processor in communication with the communication port. The digital processor is configured to receive an indication of temperature of the power amplifier through the communication port, generate the first digital setting correlating with the indication of temperature of the power amplifier, and send the first digital setting through the communication port to the first digital input of the first digital-to-analog converter.

Other exemplary embodiments include a second digital-to-analog converter having a second converter output coupled to the first voltage input, and a second digital input, wherein the second digital-to-analog converter is configured to adjust voltage at the first voltage input in response to a second digital setting received at the second digital input. In these exemplary embodiments, the digital processor is further configured to receive the indication of temperature of the power amplifier through the communication port, generate the second digital setting correlating with the indication of temperature of the power amplifier, and send the second digital setting through the communication port to the second digital input of the second digital-to-analog converter.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram of a first exemplary embodiment of a power amplifier system10that is structured in accordance with the present disclosure. In this first exemplary embodiment, the power amplifier system10has a power amplifier12with a signal input14and a signal output16(RFOUT) and bias circuitry18. The bias circuitry18includes a bandgap reference circuit20coupled between a reference node22and a fixed voltage node24, and a bias generator26has a bias input28coupled to the reference node22. The bias generator26has a bias output30coupled to the signal input14of the power amplifier12. In at least some embodiments, the power amplifier is based on bipolar junction transistor (BJT) technology.

In this exemplary embodiment, the bandgap reference circuit20is made up of a pair of stacked transistors Q1and Q2that are BJTs and that are each in a diode configuration. A collector and a base of the transistor Q1are coupled to the reference node22, while a collector and a base of the transistor Q2are coupled to an emitter of transistor Q1. An emitter of the transistor Q2is coupled to the fixed voltage node24, which in this case is ground. However, it is to be understood that a desired bias voltage and/or current can also be generated by replacing the pair of stacked transistors Q1and Q2with a single transistor, one or more diodes, or combinations thereof. One or more resistors can also be combined with the transistor(s) and/or diode(s) to more particularly refine the desired bias voltage and/or current at the reference node22. Also, in this exemplary embodiment, the bias generator26includes a transistor Q3that is a BJT and has a base coupled to the bias input28, and an emitter coupled to the signal input14through a resistor R1.

Moreover, a first capacitor C1is coupled between the reference node22and the fixed voltage node24, which in this exemplary embodiment is ground. The first capacitor C1filters noise from the voltage at the reference node22. A second capacitor C2is coupled between a radio frequency (RF) signal input32(RFIN) and the signal input14of the power amplifier12. The second capacitor C2is a coupling capacitor that couples an RF signal applied to the RF signal input to the signal input14.

In the exemplary embodiment of the power amplifier system10ofFIG. 1, the power amplifier12and the bias circuitry18are integrated into an integrated circuit34. Power from a battery voltage rail VBAT is supplied to the collector of transistor Q3through a power input36. Further still, in this exemplary embodiment, the power amplifier12is represented as a single BJT labeled Q4; however, it is to be understood that the power amplifier12may include additional transistors to provide increased gain. Moreover, the power amplifier12is not limited to a particular amplifier technology.

Also included is a first digital-to-analog converter38having a first analog output40coupled to the reference node22, a first analog input42, and a first digital input44, wherein the first digital-to-analog converter38is configured to adjust a reference voltage at the reference node22in response to a first digital setting received at the first digital input44. In the exemplary embodiment ofFIG. 1, the first digital-to-analog converter38is of the resistor type that changes a resistance value between the first analog input42and the first analog output40in response to a digital value of the first digital setting received at the first digital input44. In this embodiment, a voltage at the first analog input42is supplied by a fixed voltage source VDC1.

In the exemplary embodiment ofFIG. 1, a controller46includes the first digital-to-analog converter38. The controller46further includes a communication port48, a digital processor50, and a look-up table52. The digital processor50communicates with a communication bus54and the first digital-to-analog converter38through the communication port48. The look-up table52is typically stored in memory that is accessed directly by the digital processor50.

During operation of the exemplary embodiment ofFIG. 1, the digital processor50receives information passed through the communication port48from the communication bus54, wherein the information is indicative of a current temperature of the power amplifier12. Generally, the look-up table52has a list of data entries indicative of temperatures expected to be experienced by the power amplifier12versus first digital settings for the first digital-to analog converter38. The information may, for example, be a current power level setting for the power amplifier12. In this case, the look-up table has a list of power level settings versus first digital settings for the first digital-to-analog converter38. In this exemplary embodiment, the digital processor50is configured to retrieve from the look-up table52a first digital setting associated with a current power level setting received by the digital processor.

In response to the received current power level setting, the digital processor50retrieves from the look-up table52a corresponding first digital setting and passes the first digital setting through the communication port48to the first digital input44of the first digital-to-analog converter38. In response, the first digital-to-analog converter38adjusts the reference voltage at the reference node22in response to the first digital setting received at the first digital input44. As a result, a bias signal generated by the bias circuitry18and applied to the signal input14of the power amplifier12is at a correct level to ensure that the gain of the power amplifier12remains appropriate for the current temperature of the power amplifier12.

FIG. 2is a schematic of a second exemplary embodiment of the power amplifier system10that is structured in accordance with the present disclosure. This second exemplary embodiment further includes a second digital-to-analog converter56that replaces the fixed voltage source VDC1. The second digital-to-analog converter56has a second analog output58coupled to the first analog input42of the first analog-to-digital converter38, and a second digital input60coupled to the communication port48. A second analog input62is coupled to the fixed voltage node24.

During operation of the exemplary embodiment ofFIG. 2, the digital processor50receives information passed through the communication port48from the communication bus54, wherein the information is indicative of a current temperature of the power amplifier12. Generally, the look-up table52has a list of data entries indicative of temperatures expected to be experienced by the power amplifier12versus first digital settings and second digital settings for the first digital-to analog converter38and the second digital-to analog converter56, respectively. The data entries indicative of temperatures expected to be experienced by the power amplifier12may be power level settings for the power amplifier12that individually correspond to the data entries indicative of temperatures expected to be experienced by the power amplifier12. In this case, the look-up table52has a first list of power level settings versus first digital settings for the first digital-to-analog converter38and the same list as a second list of power level settings versus second digital settings for the second digital-to-analog converter56.

In response to a received current power level setting, the digital processor50retrieves from the look-up table a corresponding first digital setting and passes the first digital setting through the communication port48to the first digital input44of the first digital-to-analog converter38. In response, the first digital-to-analog converter38adjusts the reference voltage at the reference node22in response to the first digital setting received at the first digital input44. The digital processor50further retrieves from the look-up table a corresponding second digital setting and passes the second digital setting through the communication port48to the second digital input60of the second digital-to-analog converter56. In response, the second digital-to-analog converter56further adjusts the reference voltage at the reference node22in response to the second digital setting received at the second digital input60. As a result of both adjustments of the reference voltage, the bias signal generated by the bias circuitry18and applied to the signal input14of the power amplifier12is at a further corrected level to ensure that the gain of the power amplifier12remains appropriate for the current temperature of the power amplifier12. The desired range for the gain of the amplifier12is predetermined to prevent unacceptable distortion of the RF signal being amplified by the power amplifier12.

In this exemplary embodiment ofFIG. 2, the first digital-to-analog converter38and the second digital-to-analog converter56are integrated with the controller46. Moreover, in this exemplary embodiment, the first digital-to-analog converter38is a resistance-type digital-to-analog converter and the second digital-to-analog converter56is a voltage-type digital-to-analog converter.

FIG. 3is a schematic of a third exemplary embodiment of the power amplifier system10that is structured in accordance with the present disclosure. This third exemplary embodiment further includes a temperature sensor64that is integrated with the power amplifier12within the integrated circuit34. Also further included is an analog-to-digital converter66that can be either integrated into the integrated circuit34or integrated with the controller46. A sensor output68of the temperature sensor64is coupled to a sensor input70of the analog-to-digital converter66. The communication port48is coupled to a digital output72of the analog-to-digital converter66. Notice that in this exemplary embodiment, both the first digital-to-analog converter38and the second digital-to-analog converter56are integrated into the integrated circuit34.

During operation of the exemplary embodiment ofFIG. 3, the digital processor50receives a digital temperature reading passed through the communication port48from the analog-to-digital converter66, wherein the information is indicative of a current temperature of the power amplifier12. In this case, the look-up table52has a list of temperature readings versus first digital settings for the first digital-to-analog converter38and the same list of temperature readings versus second digital settings for the second digital-to-analog converter56.

In response to a received digital temperature reading, the digital processor50retrieves from the look-up table a corresponding first digital setting and passes the first digital setting through the communication port48to the first digital input44of the first digital-to-analog converter38. In response, the first digital-to-analog converter38adjusts the reference voltage at the reference node22in response to the first digital setting received at the first digital input44. The digital processor50further retrieves from the look-up table a corresponding second digital setting and passes the second digital setting through the communication port48to the second digital input60of the second digital-to-analog converter56. In response, the second digital-to-analog converter56further adjusts the reference voltage at the reference node22in response to the second digital setting received at the second digital input60. As a result of both adjustments of the reference voltage, the bias signal generated by the bias circuitry18and applied to the signal input14of the power amplifier12is at a further corrected level to ensure that the gain of the power amplifier12remains within a desired range for the current temperature of the power amplifier12. The desired range for the gain of the amplifier12is predetermined to prevent unacceptable distortion of the RF signal being amplified by the power amplifier12.

In yet another operation mode of the exemplary embodiment ofFIG. 3, further information, such as a current power level setting can be received from the communication bus54through the communication port48. In this case, the look-up table further includes a first list of power level settings and temperature readings versus first digital settings for the first digital-to-analog converter38and the same list as a second list of power level settings and temperature readings versus second digital settings for the second digital-to-analog converter56.

In response to a received current power level setting and a received current temperature reading, the digital processor50retrieves from the look-up table52a corresponding first digital setting and passes the first digital setting through the communication port48to the first digital input44of the first digital-to-analog converter38. The first digital-to-analog converter38then adjusts the reference voltage at the reference node22in response to the first digital setting received at the first digital input44. The digital processor50further retrieves from the look-up table a corresponding second digital setting and passes the second digital setting through the communication port48to the second digital input60of the second digital-to-analog converter56. The second digital-to-analog converter56further adjusts the reference voltage at the reference node22in response to the second digital setting received at the second digital input60. As a result of both adjustments of the reference voltage, the bias signal generated by the bias circuitry18and applied to the signal input14of the power amplifier12is at a further corrected level to ensure that the gain of the power amplifier12remains appropriate for the current power setting and current temperature of the power amplifier12. The desired range for the gain of the amplifier12is predetermined to prevent unacceptable distortion of the RF signal being amplified by the power amplifier12.

FIG. 4is a graph depicting gain as a function of temperature for exemplary voltages applied to the reference node22of the bias circuitry18that provides the bias signal to the power amplifier12when the resistance between the first analog input42and the first analog output40of the first digital-to-analog converter38is set to a resistance value of 150Ω. Notice that in this case the gain is relatively flat for a reference voltage of 2.8 V at the reference node22over a wide range of temperatures in comparison to a lower reference voltage of 2.55 V and a higher reference voltage of 3.1 V. Thus, the first digital-to-analog converter38and the second digital-to-analog converter56depicted inFIGS. 2 and 3can be controlled by the controller46to maintain the resistance coupled to the reference node at 150Ω while maintaining a reference voltage VREF at 2.8 V for temperatures between −40° C. and 140° C. The graph ofFIG. 4also illustrates why the first digital-to-analog converter38is a resistance-type digital-to-analog converter used to correct quiescent current level associated with current biasing.

FIG. 5is a graph depicting gain for the power amplifier12as a function of temperature for exemplary resistance values for the first analog-to-digital converter38coupled to the reference node22of the bias circuitry18for a fixed reference voltage of 2.8 V. Notice that the gain of the power amplifier12is relatively flat with the resistance of the first analog-to-digital converter set to any of 150 Ω, 500Ω, and 1000Ω over a wide range of temperatures. However, also notice that the gain of the power amplifier12is above 27 dB for the 150Ω value in comparison to the higher resistance value of 500Ω with gain that is less than 26 dB and the yet higher resistance value of 1000Ω with gain that is less than 23 dB. Thus, the first digital-to-analog converter38and the second digital-to-analog converter56depicted inFIGS. 2 and 3can be controlled by the controller46to maintain a relatively high gain for the amplifier12for temperatures between −40° C. and 140° C. by controlling both current biasing and voltage biasing as a function of indicated temperature of the power amplifier12.

FIG. 6is a graph depicting gain for the power amplifier12as a function of temperature for exemplary resistance values for the first analog-to-digital converter38coupled to the reference node22of the bias circuitry18for a fixed reference voltage of 3.11 V. Notice that with the higher fixed reference voltage of 3.11 V, the gain of the power amplifier12is no longer relatively flat with the resistance of the first analog-to-digital converter set to any of 150 Ω, 500Ω, and 1000Ω over the wide range of temperatures between −40° C. and 140° C. The graph ofFIG. 6also illustrates why the second digital-to-analog converter56is a voltage-type digital-to-analog converter used to correct temperature coefficients associated with voltage biasing.