Method for managing flash memory module and associated flash memory controller and electronic device

The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the method includes the steps of: using a time management circuit to generate current time information; when data is written into any one of the blocks, recording the time information generated by the time management circuit; and determining at least one specific block according to quantity of invalid pages within each block and the time information of each block.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flash memory controller.

2. Description of the Prior Art

With the developments of flash memory techniques, the arrangement of memory units in a flash memory chip has changed from parallel arranging fashions to stacked multi-layer fashions, which allows a chip to comprise more memory units and therefore increases the overall capacity of the chip. However, the aforementioned 3D flash memory design may suffer from some data retention issues, such as, the data quality thereof could drops drastically right after the chip is written with data, making the data be read incorrectly. Further, data may also suffer from the read disturbing issues when being read too often, thereby further deteriorating the data quality.

SUMMARY OF THE INVENTION

Therefore, the present invention proposes a method for managing a flash memory, which is achieved by further referring to the time information of blocks when storing data, to determine the sequential order of performing the garbage collecting operation. The proposed method may effectively solve the data retention issues as well as the reading interference issues of blocks.

An embodiment of the present invention discloses a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, the flash memory module comprises multiple flash memory chips, each of the flash memory chips comprises multiple blocks, each of the block comprises multiple pages, and the flash memory controller comprises a read only memory (ROM), a microprocessor and a time management circuit. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control the access of the flash memory module. The time management circuit is coupled to the microprocessor and arranged to generate current time information. When the microprocessor writes data into any block of said multiple blocks, the microprocessor records the time information generated by the time management circuit; and the microprocessor further selects at least one specific block that needs to be performed with a garbage collecting operation according to the number of invalid pages in each block and the time information of said each block.

Another embodiment of the present invention discloses a method for managing a flash memory module. The flash memory module comprises multiple flash memory chips, each of the flash memory chips comprises multiple blocks, and each of the block comprises multiple pages. The method comprises: using a time management circuit to generate current time information; recording the time information generated by the time management circuit when data is written into any block of said multiple blocks; and selecting at least one specific block that needs a garbage collecting operation according to the number of invalid pages in each block and the time information corresponding to said each block.

Yet another embodiment of the present invention discloses an electronic device which comprises a flash memory module and a flash memory controller. The flash memory module comprises multiple flash memory chips, each of the flash memory chips comprises multiple blocks, and each of the blocks comprises multiple pages. The flash memory controller is arranged to access the flash memory module. The flash memory controller generates current time information, and when the flash memory controller writes data into any block of said multiple blocks, the flash memory controller records the time information generated by the time management circuit. The flash memory controller further selects at least one specific block that needs to be performed with a garbage collecting operation according to the number of invalid pages in each block and the time information corresponding to said each block.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a memory device100according to a first embodiment of the present invention. The memory device100comprises a flash memory module120and a flash memory controller110, and the flash memory controller110is arranged to access the flash memory module120. In this embodiment, the flash memory controller110comprises a microprocessor112, a read only memory (ROM)112M, a control logic114, a buffer memory116, an interface logic118and a time-management circuit119. The ROM112M is arranged to store a program code112C, and the microprocessor112is arranged to execute the program code112C to control the access of the flash memory module120. The control logic114comprises an encoder132and a decoder134, wherein the encoder132is arranged to encode the data written into the flash memory module120in order to generate a corresponding checking code (which can be also called as error correction code (ECC)), and the decoder134is arranged to decode the data read from the flash memory module120.

Typically, the flash memory module120comprises multiple flash memory chips, and each flash memory chip comprises a plurality of blocks. The flash memory controller110may use “block” as the unit to erase data from the flash memory module120. A block may record a specific number of pages, and the flash memory controller110may use “page” as the unit to write data into the flash memory module120. In this embodiment, the flash memory module120may be a 3D NAND-type flash memory module.

In practice, the flash memory controller110may utilize the internal elements thereof to use the microprocessor112to execute the program code112C, in order to perform various control operations, such as utilizing the control logic114to control the access of the flash memory module120(more particularly, the access of at least one block or at least one page), utilizing the buffer memory116to perform the required buffering process, and utilizing the interface logic118to communicate with a host device130. Further, the time-management circuit119may be connected to a specific pin N2of the host device via a specific pin N1of the flash memory controller. The buffer memory116may be implemented with a random access memory (RAM). For example, the buffer memory116may be a static random access memory (SRAM), but the present invention is not limited thereto.

In an embodiment, the memory device100may be a portable memory device (e.g. a memory card conforming to the SD/MMC, CF, MS and/or XD specification), and the host device130is an electronic device connectable to an electronic device, such as a smartphone, laptop computer, desktop computer, etc. In another embodiment, the memory device100may be a solid state drive (SSD) or an embedded storage device conforming to the Universal flash storage (UFS) or Embedded Multi Media Card (EMMC) specification. The memory device100can be installed in an electronic device, such as a smartphone, laptop computer or desktop computer, wherein the host device130may be a processor of the electronic device.

FIG. 2is a diagram illustrating a block200in the flash memory module120according to an embodiment of the present invention, wherein the flash memory module120is a 3D NAND-type flash memory. As shown inFIG. 2, the block200comprises multiple memory units (e.g. the floating-gate transistor202or the charge trapping elements shown in the figure), and constructs a 3D NAND-type flash memory structure with multiple bit lines (e.g. the bit lines BL1-BL3shown in the figure) and multiple word lines (e.g. the word lines WL0-WL2, WL4-WL6shown in the figure). Please refer toFIG. 2, taking the uppermost plane as an example, all floating-gate transistors on the word line WL0construct at least one page, all floating-gate transistors on the word line WL1construct at least another page, and all floating-gate transistors on the word line WL2further construct at least another page, and so on. Furthermore, based on different writing methods of the flash memory, the definition between the word line WL0and the page can be different. Specifically, when writing in the single-level cell (SLC) manner, all floating-gate transistors on the word line WL0are only corresponding to one single logic page; when writing in the multi-level cell (MLC) manner, all floating-gate transistors on the word line WL0are corresponding to two logic pages; when writing in triple-level cell (TLC) manner, all floating-gate transistors on the word line WL0are corresponding to three logic pages; and when writing using quad-level cell (QLC) manner, all floating-gate transistors on the word line WL0are corresponding to four logic pages. Since one skilled in the art should be readily to understand the structure and of a 3D NAND-type flash memory and the relationship between word lines and pages, the detailed descriptions thereof are omitted here for brevity.

The architecture shown inFIG. 2is merely a rough illustration of the basic structure of the 3D flash memory, while in an actual manufacturing process, more stack layers might be applied in order to reach a denser storage capacity. Since the 3D flash memory adopts the stacked structure shown inFIG. 2, data storing may suffer severe data retention problems. That is, if the data is written into the block200, after a period of time, the memory units therein will encounter problems on data quality such as the data writing level shift, threshold voltage drift, etc., resulting in difficulties of decoding the data read from the block200, or even resulting in data lost due to unsuccessful decoding. Further, the aforementioned stacked structure also deteriorates the reading interference problems. To address this issue, this embodiment proposes a method for managing the flash memory module120, which may place a time management circuit119in the flash memory controller110to effectively record the time information of each block, which can be referred by the microprocessor112when there is a need for creating the sequential order of the garbage collecting operation. The operational details are described as follows.

FIG. 3depicts a block200that comprises multiple pages P0-PN. When the flash memory controller110needs to write data into the block200, such as the data from the host device130, the data from other blocks of the flash memory module120, and/or the data temporarily stored in the flash memory controller110, the flash memory controller110may sequentially write the data into the pages, starting from the first page P0to the last page PN. In this embodiment, when the flash memory controller110is going to write data into the very last page PN or last few pages, the time-management circuit119will send a request command to the host device130via the specific pin N1in order to request the host device130to provide current time information. Since the host device130is connected to the operating system, the current time information (e.g. the month, date, minute, second, etc.) may be provided to the time-management circuit119. After the time-management circuit119calculates the time information, it will provide the time information to the microprocessor112, so as to be processed by the encoder132and be written along with other data into the page PN.

Since the last page PN of the block200records the absolute time (e.g. the timestamp), the microprocessor112may easily determine how long the data has been stored in the block200anytime, as a reference of deciding the sequential order of a later garbage collecting operation. It should be noted, however, although in the embodiment ofFIG. 3, the last page PN of the block200records the time point of the last written data, this feature is not meant to be a limitation of the present invention. In other embodiments, the time information may not necessarily be corresponding to the last page PN, and the time information stored in the block200may be the time point where the block200starts storing data, or the time point of writing any data into the block200, as long as the time information is able to show the time information of the data in the block200.

In another embodiment of the present invention, except for writing the time information into the last page PN of each block, the microprocessor112may further create a time information comparison table400as shown inFIG. 4, which records the time information (e.g., the timestamps TS1-TS10shown inFIG. 4) that are written into each block (e.g., the blocks B1-B10inFIG. 4). In this embodiment, the time information comparison table400may be temporarily stored in an external dynamic random access memory or an internal buffer memory116of the flash memory controller110, so that the flash memory controller110may quickly determine how long the data in each block has been stored, without the need for reading each block of the flash memory module120, and the flash memory controller110may perform appropriate processing later.

Further, when the flash memory controller110is about to be powered off or the memory needs to release space, the time information comparison table400may be written to a proper address in the flash memory module120in order to prevent data lost.

In another embodiment, for more effectively using the memory space, the contents of the time information comparison table400may be integrated to another comparison table/mapping table (e.g. a logical address to physical address mapping table or a physical address to logical address mapping table).

It should be noted in the embodiment shown inFIG. 1, the time management circuit119directly obtains the current time information from the host device130, so as to write the current time information into the last page PN of the block200, but this is not a limitation of the present invention. In other embodiments of the present invention, the time management circuit119may calculate the current time information by using a counter or other means.

In another aspect, during the flash memory controller110writing data into the flash memory module120, the microprocessor112may also create/update an invalid page number comparison table500shown inFIG. 5according to the data written into the flash memory module120, wherein the invalid page number comparison table500records each block (e.g., the blocks B1-B10shown inFIG. 5) as well as the number of invalid pages in said each block. The following is an example illustrating the update operation of the invalid page number comparison table500, assuming that the page P2of the block B2currently stores the data with a first logic address, and meanwhile, the microprocessor112receives a writing command from the host device130, wherein the writing command comprises the first logic address and associated data. Since the writing command is arranged to update the contents stored by the page P2of the block B2(wherein the updated data will be written into another block), the page P2of the block B2may be later labeled as an invalid page. Meanwhile, the microprocessor112may add “1” onto the invalid page number of the block B2recorded in the invalid page number comparison table500.

Since the time information comparison table400records the time information of each block which may reveal whether the block has encountered data retention or reading interference problems. Hence, by referring the time information comparison table400and the invalid page number comparison table500to select multiple specific blocks that need to be performed with the garbage collecting operation, and by determining the sequential order of performing the garbage collecting operation, the problem that the blocks suffer from data retention or reading interference issues may be solved while the memory space is effectively released.

Specifically, when the flash memory controller110is not busy, or the flash memory controller110needs to perform the garbage collecting operation due to some triggering conditions (e.g., the space of the flash memory module120is insufficient), the microprocessor112will select multiple specific blocks that need to be performed with the garbage collecting operation and the sequential order thereof according to the time information comparison table400and the invalid page number comparison table500, and then accordingly perform the garbage collecting operation. In a first example, the microprocessor112may refer to the invalid page number comparison table500first, to select a portion of blocks whose invalid page number is greater than a threshold value as said multiple specific blocks. Taking the threshold value “50” as an example, the microprocessor112may select blocks B3, B4, B5and B7to be performed with the garbage collecting operation. Next, the microprocessor112may further refer to the time information comparison table400to determine the sequential order of performing the garbage collecting operation upon the block B3, B4, B5and B7. In an example, the microprocessor112refers to the timestamps TS3, TS4, TS5and TS7respectively corresponding to the blocks B3, B4, B5and B7to determine the sorting order, wherein the block with an earlier timestamp will have a higher priority, that is, a specific block corresponding to an earlier timestamp may be performed with the garbage collecting operation in a higher priority.

In a second example, the microprocessor112may refer to the time information comparison table400first, to select a portion of blocks corresponding to the time information that is earlier than a time point, as said multiple specific blocks. For example, assuming that the time point is 20 days, the microprocessor112may select blocks with the timestamp from the time information comparison table400more than 20 days earlier to be as said multiple specific blocks. The following illustrations assume that said multiple specific blocks are B2, B3, B4and B7. Next, the microprocessor112further refers to the invalid page number comparison table500to determine the sequential order of the garbage collecting operation for the blocks B2, B3, B4and B7. In an example, the microprocessor112may refer to the invalid page number corresponding to blocks B2, B3, B4and B7to determine the sorting thereof. TakingFIG. 5as example, the sequential order of performing the garbage collecting operation is B7, B4, B3and B2, sequentially.

In the third example, the microprocessor112may refer to the time information comparison table400first, to select a portion of blocks corresponding to time information earlier than a time point. For example, assuming that the time point is 20 days, the microprocessor112may select blocks with the timestamp from the time information comparison table400more than 20 days earlier, e.g. the blocks B2, B3, B4and B7. After that, the microprocessor112further refers to the invalid page number comparison table500to select blocks with invalid page number greater than a threshold value from said at least one portion of block as said multiple specific blocks. Taking the threshold value “50” as an example, the microprocessor112may select the blocks B3, B4, B7from the blocks B2, B3, B4and B7to be performed with the garbage collecting operation.

It should be noted, however, the above three embodiments are merely for illustrative purposes, and are not meant to be a limitation of the present invention. In other embodiments, as long as the sequential order of the garbage collecting operation can be determined according to the time information of the number of invalid pages in each block, various modifications made to the above embodiments shall belong to the scope of the present invention.

In other embodiment of the present invention, the microprocessor112may create the sequential order of blocks that need to be performed with the garbage collecting operation at any suitable time according to the contents of the above embodiments, to be used in the follow-up garbage collecting operation.

FIG. 6is a flowchart illustrating a method for managing a flash memory module according to an embodiment of the present invention. The flowchart ofFIG. 6summarizes the contents of the aforementioned embodiments as follows:

Step600: The flow begins.

Step602: Use a time management circuit to generate the current time information.

Step604: When data is written into any block within the blocks of the flash memory module, record the time information generated by the time management circuit.

Step606: Refer to the number of invalid pages in each block and the time information corresponding to each block to select specific blocks that need to be performed with the garbage collecting operation, and determine the sequential order the specific blocks perform the garbage collecting operation.

To summarize, in the flash memory controller of the present invention, by referring to the number of invalid pages in each block and the time information of the block to determine the sequential order of performing the garbage collecting operation upon blocks, blocks that have more invalid pages or more likely suffer from data retention or reading interference problems may be preferentially performed with the garbage collecting operation. Therefore, the valid storage space of the flash memory module can be increased, thereby improving the overall data quality.