Device, system and method of multi-channel processing

Some demonstrative embodiments include devices, systems and methods of multi-channel processing. For example, a multi-channel data processor may process data of a plurality of channels, the multi-channel data processor is to switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch during a single clock cycle, the context switch including storing first state context corresponding to a processing state of the first channel and loading previously stored second state context corresponding to a processing state of the second channel.

BACKGROUND

Some communication networks, may communicate data over a plurality of communication channels.

For example, a cable network may include a cable modulator-demodulator (modem) capable of transferring downstream data, which is modulated over a plurality of downstream channels, from a Cable-Modem-Termination-System (CMTS) to one or more devices (subscriber devices), and transferring upstream data, which is modulated over a plurality of upstream channels, from the devices to the CMTS.

DETAILED DESCRIPTION

Some portions of the detailed description, which follow, are presented in terms of algorithms and symbolic representations of operations on data bits or binary digital signals within a computer memory. These algorithmic descriptions and representations may be the techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art.

Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing”, “computing”, “calculating”, “determining”, or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, or transmission devices. The terms “a” or “an”, as used herein, are defined as one, or more than one. The term plurality, as used herein, is defined as two, or more than two. The term another, as used herein, is defined as, at least a second or more. The terms including and/or having, as used herein, are defined as, but not limited to, comprising.

The term coupled as used herein, is defined as operably connected in any desired form for example, mechanically, electronically, digitally, directly, by software, by hardware and the like.

Some embodiments may be used in conjunction with various devices and systems, for example, a communication system, a communication device, a wired communication device, a cable communication device, a wired communication system, a cable communication system, a modem, a gateway, a cable network, a cable modem, a cable gateway, a Personal Computer (PC), a server, a networking device, a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a server computer, a handheld computer, a handheld device, a Personal Digital Assistant (PDA) device, a handheld PDA device, an on-board device, an off-board device, a hybrid device, a vehicular device, a non-vehicular device, a mobile or portable device, a consumer device, a non-mobile or non-portable device, a wireless communication station, a wireless communication device, a wireless Access Point (AP), a wired or wireless router, a wired or wireless modem, a video device, an audio device, an audio-video (A/V) device, a wired or wireless network, a wireless area network, a Wireless Video Area Network (WVAN), a Local Area Network (LAN), a Wireless LAN (WLAN), a Personal Area Network (PAN), a Wireless PAN (WPAN), and the like. It will be understood by those skilled in the art that this is a very brief list of the many, many devices in or with which the disclosed embodiments may be used.

Although not limited in this respect, the term “integrated circuit” (IC), as used herein refers to any suitable microcircuit, microchip, hybrid integrated circuit, digital integrated circuit and/or any other suitable electronic circuit, which includes, for example, a plurality of electronic devices manufactured in the surface of a thin substrate.

Although not limited in this respect, the term “system on chip” (SoC), as used herein refers to a single IC including a plurality of modules and/or components of a system. The SoC includes digital, analog, mixed-signal, radio-frequency (RF) and/or any other suitable functions.

In one embodiment, the SoC may include one or more controllers, processors, microcontrollers, microprocessors, Digital-Signal-Processing (DSP) cores; one or more memories; one or more timing sources, e.g., oscillators and/or phase locked loops; one or more peripherals, e.g., counter-timers or power-on reset generators; one or more external interfaces, e.g., a Universal Serial Bus (USB), an Ethernet interface, Universal Asynchronous Receiver-Transmitter (UART), a Serial Peripheral Interface (SPI), and the like; one or more digital interfaces; one or more analog interfaces; and/or any other suitable modules.

For example, a communication device, e.g., a cable modulator-demodulator (modem) or a cable gateway, may include a SoC capable of processing downstream and/or upstream digital samples corresponding to downstream and/or upstream RF channels of a communication system, e.g., a cable communication system.

The term “communicating” as used herein with respect to a communication signal includes transmitting the communication signal and/or receiving the wireless communication signal. For example, a wired or wireless communication unit, which is capable of communicating a wired or wireless communication signal, may include a transmitter to transmit the communication signal to at least one other wired or wireless communication unit, and/or a receiver to receive the communication signal from at least one other communication unit.

Reference is no made toFIG. 1, which schematically illustrates a system100, in accordance with some demonstrative embodiments.

In some demonstrative embodiments, system100may include one or more devices, e.g., devices102and104, capable of communicating over at least one communication medium106.

In some demonstrative embodiments, system100may include a cable communication system.

In one example, device102may include a cable communication device, e.g., a cable modem, device104may include a cable communication device, e.g., a Cable-Modem-Termination-System (CMTS)104, and/or communication medium106may include a cable network.

According to this example, device102may transfer downstream (DS) data signals from device104to one or more devices (also referred to as “subscriber devices”, or “client devices”)140, and/or device102may transfer upstream (US) data signals from subscriber devices140to the device104.

In some demonstrative embodiments, device102may include, or may be part of, a cable modem, a cable gateway, and the like.

In some demonstrative embodiments, system100may include a Cable Television (CATV) communication system capable of communicating data between device104and client devices118via RF signals transmitted through medium106. Medium106may include, for example, a network of coaxial cables and, optionally, optical fibers, e.g., if medium106includes a Hybrid Fiber Coaxial (HFC) infrastructure. The data communicated between device104and client devices118may include, for example, television data, video data, audio data, Internet data, telephony data, and the like.

In some demonstrative embodiments, one or more elements of system100may be configured to communicate in accordance with the Data Over Cable Service Interface Specification (DOCSIS), e.g., DOCSIS 3.0, and/or any other cable communication standard and/or specification.

In some demonstrative embodiments, client devices118may include, for example, at least one of a television device capable of receiving television data from device104via device102, a telephone device cable of exchanging telephone signals with device104via device102, a video device capable of receiving video data from device104via device102, an audio device capable of receiving audio data from device104via device102, an internet-protocol (IP) device capable of exchanging IP signals with device104via device102, a storage device capable of storing and/or processing data received from device104via device102, a Wireless Local Area Network (WLAN) device capable of communicating data to/from device104via a WLAN, and the like.

Although some demonstrative embodiments are described herein with respect to one or more cable communication devices and/or cable communication systems, other embodiments may include any other suitable wired or wireless communication devices and/or systems. For example, in some demonstrative embodiments devices102and104may include wireless communication devices, and communication medium106may include a wireless communication medium.

In some demonstrative embodiments, device102and/or device104may include at least one RF tuner109to communicate over a plurality of channels, e.g., via medium106. For example, RF tuner109of device102may be implemented as part of a suitable Analog Front End (EFE) of device102, and/or any other module or element of device102.

In some demonstrative embodiments, RF tuner109may receive, e.g., via communication medium106, downstream signals including downstream data communicated from device104to device102; and/or RF tuner109may transmit, e.g., via communication medium106, upstream signals including upstream data communicated from device102to device104.

In some demonstrative embodiments, the downstream and/or upstream signals may include analog signals configured to be communicated over a cable network, e.g., if system100includes a cable communication system and communication medium106includes a cable network.

For example, RF tuner109may be configured to receive from the cable network the downstream signals in the form of an analog input including a plurality of downstream data channels. In one non-limiting example, RF tuner109may be configured to receive the downstream signals in the form of an analog RF signal modulated over an RF downstream frequency band, e.g., an RF frequency band of 54-1002 Megahertz (MHz), or any other RF frequency band. In one non-limiting example, the downstream signals may include at least sixteen downstream channels, e.g., at least 32 downstream channels. In other embodiments, the downstream signals may be modulated over any other RF band and/or may include any other number of downstream channels.

For example, RF tuner109may be configured to transfer the upstream signals over the cable network in the form of an analog output including an upstream data channel. In one non-limiting example, RF tuner109may be configured to provide the upstream signals in the form of an analog RF signal modulated over an RF upstream frequency band, e.g., an RF frequency band of 5-85 MHz, or any other RF frequency band. In other embodiments, the upstream signals may be modulated over any other RF band and/or may include two or more upstream channels.

In some demonstrative embodiments, device102and/or device104may include at least one multi-channel processing module110to process data of the plurality of communication channels, e.g., as described in detail below.

In some demonstrative embodiments, multi-channel processing module110may receive digital data samples corresponding to the data communicated over the plurality of communication channels. For example, analog data signals received via communication medium106may be converted into digital data samples, for example, using one or more Analog to Digital Converters (ADCs), e.g., as described below with reference toFIG. 2.

In some demonstrative embodiments, multi-channel processing module110may include or may be implemented as part of a multi-channel receiver (MCR) to process received data, e.g., received by RF tuner109, from the plurality of communication channels, e.g., as described in detail below.

In other demonstrative embodiments, multi-channel processing module110may include or may be implemented as part of a multi-channel transmitter to process data to be transmitted, e.g., by RF tuner109, over the plurality of communication channels.

In some demonstrative embodiments, device102may include two separate multi-channel processing modules110, e.g., a multi-channel receiver and a multi-channel transmitter, to process the received and transmitted data, respectively. In other embodiments, device102may include a multi-channel processing module110to process both the received and transmitted data.

In some demonstrative embodiments, multi-channel processing module110may include, or may be implemented as part of, a SoC. For example, multi-channel processing module110may include a SoC capable of processing downstream and/or upstream digital samples communicated over downstream and/or upstream RF channels of system100, e.g., in accordance with the DOCSIS and/or any other standard.

In some demonstrative embodiments, multi-channel processing module110may include a multi-channel data processor120configured to process the data of the plurality of channels, e.g., as described in detail below.

For example, if multi-channel processing module110performs the functionality of a MCR, multi-channel data processor120may perform the functionality of a plurality of receiver processors, which may process data of the received data of the plurality of the channels, respectively. In one example, multi-channel data processor120may “wrap” a single instance of a receiver processor and utilize the wrapped instance for processing the received data of the plurality of channels.

In some demonstrative embodiments, multi-channel data processor120may include, or may be implemented as part of, a hardware engine, a processing engine, and the like.

Reference is made toFIG. 2, which schematically illustrates a multi-channel receiver200, in accordance with some demonstrative embodiments. In some demonstrative embodiments, multi-channel receiver200may perform the functionality of multi-channel processing module110(FIG. 1).

In some demonstrative embodiments, multi-channel receiver200may be included as part of a receiver unit202. For example, receiver unit202may be included as part of a cable modem to receive downstream signals over a cable network, e.g., as described above. In other demonstrative embodiments, receiver unit202may be included as part of any other wired or wireless communication device.

In some demonstrative embodiments, receiver unit202may include a plurality of AFEs204to receive analog RF signals205of a respective plurality of communication channels via a communication medium, e.g., via communication medium106(FIG. 1).

In some demonstrative embodiments, receiver unit202may include a plurality of ADCs206to convert the analog signals of the plurality of communication channels into a plurality of streams209of digital samples, e.g., each stream209corresponding to a respective communication channel of the plurality of communication channels.

In some demonstrative embodiments, multi-channel receiver200may include a multi-channel data processor210to process the digital samples of streams209and to provide a plurality of streams211including processed digital data of the plurality of communication channels, e.g., each stream211corresponding to a respective communication channel of the plurality of communication channels.

In some demonstrative embodiments, multi-channel receiver200may be configured to perform the functionality of a plurality of data processors, e.g., a plurality of single-channel data processors, each configured to process a single channel of the plurality of communication channels.

In some demonstrative embodiments, receiver unit202may include one or more elements, e.g., a Media-Access-Control (MAC) module218, to process streams211.

Referring back toFIG. 1, in some demonstrative embodiments, multi-channel data processor120may operate at a relatively high frequency, e.g., an operating frequency greater than an actual processing rate, which may be required for processing the data of the plurality of channels, e.g., greater than a data rate of data streams209(FIG. 2).

In some demonstrative embodiments, multi-channel processing module110may include a plurality of input queues122to queue the data samples of the plurality of communication channels, e.g., a received from streams209(FIG. 2), for example, prior to processing by multi-channel data processor120.

In some demonstrative embodiments, multi-channel processing module110may include a plurality of output queues124to queue processed data samples of the plurality of communication channels, e.g., after processing by multi-channel data processor120.

In some demonstrative embodiments, queues122and/or124may include First In First Out (FIFO) queues and/or any other queues.

In some demonstrative embodiments, multi-channel data processor120may process the data samples of the plurality of communication channels according to a predefined timing scheme, e.g., as described below.

In some demonstrative embodiments, the timing scheme may include a Time-Division-Multiplexing (TDM) scheme. For example, the TDM scheme may divide a time line into a sequence of timeslots. The plurality of channels may be assigned to the timeslots, e.g., in a cyclic order or in any other order. During each time slot, multi-channel data processor120may process a channel, which is assigned to the time slot. Once the time slot ends, multi-channel data processor120may switch to process a channel assigned to a subsequent time slot.

Reference is made toFIG. 3, which schematically illustrates a multi-channel timing scheme300, in accordance with some demonstrative embodiments. In some demonstrative embodiments, timing scheme300may be utilized by multi-channel data processor120(FIG. 1).

In some demonstrative embodiments, timing scheme300may schedule a plurality of communication channels, including N>1 channels.

As shown inFIG. 3, in some demonstrative embodiments the communication channels may be assigned to a sequence of time slots according to an order of the communication channels. For example, a first channel, denoted CH1, may be assigned to a time slot301, a second channel, denoted CH2, may be assigned to a time slot302, immediately successive to time slot301, a third channel, denoted CH3, may be assigned to a time slot303, immediately successive to time slot302, and so on, e.g., until the N-th channel, denoted CH−N, is assigned to a time slot305.

As shown inFIG. 3, the communication channels may be assigned to the time slots in a cyclical manner. For example, the first channel may be assigned to a time slot306, immediately successive to time slot305, the second channel may be assigned to a time slot307, immediately successive to time slot306, and so on.

Referring back toFIG. 1, in some demonstrative embodiments multi-channel data processor120may process data of a channel (“the processed channel”) utilizing state context135corresponding to the processed channel.

The state context may include any suitable information corresponding to a state (“processing state”) of the processed channel, e.g., a state of multi-channel data processor120, data processed by multi-channel data processor120, e.g., channel data of the processed channel, processed data corresponding to the processed channel, and the like. For example, the state context corresponding to a particular channel may include information, which may indicate and/or define a state of multi-channel data processor120at a particular point of processing the particular channel, e.g., immediately prior to a context switch between the particular channel and another channel. The state context may include, for example, information to enable multi-channel data processor120to resume processing the particular channel, e.g., from the particular point. In one example, the state context may include one or more values stored in a memory or storage of multi-channel data processor120, for example, one or more, e.g., all, Flip-Flop (FF) circuits of multi-channel data processor120. For example, the state context may include values of one or more states of one ore more state machines utilized by multi-channel data processor120, one or more delay lines utilized by multi-channel data processor120, one or more intermediate results, and the like.

In some demonstrative embodiments, multi-channel data processor120may switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch.

In some demonstrative embodiments, the context switch may include storing first state context corresponding to a processing state of the first channel and loading previously stored second state context corresponding to a processing state of the second channel.

Reference is now mad toFIG. 4, which schematically illustrates a multi-channel processing architecture400including a multi-channel data processor402, in accordance with some demonstrative embodiments. In some demonstrative embodiments, multi-channel processing architecture400may be implemented by multi-channel processing module110(FIG. 1), and/or multi-channel data processor may perform the functionality of multi-channel data processor402may perform the functionality of multi-channel data processor120(FIG. 1).

In some demonstrative embodiments, architecture400may include a plurality of FIFO input queues404, e.g., N FIFO input queues, to queue input data of a plurality of communication channels, e.g., the N communication channels discussed above. In some demonstrative embodiments, queues404may perform the functionality of queues122(FIG. 1).

In some demonstrative embodiments, architecture400may include a plurality of FIFO output queues406, e.g., N FIFO output queues, to queue output data of the plurality of communication channels after processing by multi-channel data processor402. In some demonstrative embodiments, queues406may perform the functionality of queues124(FIG. 1).

In some demonstrative embodiments, multi-channel data processor402may sequentially process data of the plurality of channels, for example, by switching between queues404.

In some demonstrative embodiments, architecture400may include a switch412to switch an input of multi-channel data processor402between input queues404.

In some demonstrative embodiments, architecture400may include a switch414to switch an output of multi-channel data processor402between output queues406.

For example, switch412may be configured to switch between queues404, and/or switch414may be configured to switch between queues406according to timing scheme300(FIG. 3).

In some demonstrative embodiments, multi-channel data processor402may utilize state context408corresponding to a channel being processed by multi-channel data processor402.

In some demonstrative embodiments, architecture400may include a memory (“state bank”)410to store a plurality of state contexts corresponding to the plurality of channels.

In some demonstrative embodiments, memory410may include a Random Access Memory (RAM), e.g., as described below. In other embodiments, memory410may include any other suitable type of memory and/or storage.

In some demonstrative embodiments, multi-channel data processor402may switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch to switch between state context408corresponding to the first and second channels.

In some demonstrative embodiments, the context switch may include storing, e.g., in state bank410, first state context corresponding to a processing state of the first channel, and loading, .g., from state bank410, previously stored second state context corresponding to a processing state of the second channel.

In one example, at the beginning of time slot301(FIG. 3), the state context corresponding to the channel CH1 may be loaded from state bank410as state408, and switch412may be switched to provide to multi-channel data processor402data of the channel CH1 for processing. At the end of time slot301(FIG. 3), the state context corresponding to the channel CH1 may be stored in state bank410, the state context corresponding to the channel CH2 may be loaded from state bank410as state408, switch414may be switched to provide the processed data corresponding to the channel CH1 from multi-channel data processor402to output queue406, and switch412may be switched to provide to multi-channel data processor402data of the channel CH2 for processing.

In some demonstrative embodiments, architecture400may enable utilizing multi-channel processing module110(FIG. 1) in conjunction with a communication module, e.g., a receiver, without performing substantially any redesign of the communication.

In some demonstrative embodiments, architecture400may be modified and/or adapted to support various numbers of channels, for example, in a fast and/or easy manner, e.g., by adapting queues404and/or406.

Referring back toFIG. 1, in some demonstrative embodiments multi-channel data processor120may be configured to perform the context switch, for switching from processing the first channel to processing the second channel, during a single clock cycle, e.g., as described below.

In some demonstrative embodiments, multi-channel processing module110may include a memory, e.g., a RAM130, to store a plurality of state contexts corresponding to the plurality of channels.

In some demonstrative embodiments, the context switch may include storing in RAM130first state context corresponding to a processing state of the first channel and loading from RAM130previously stored second state context corresponding to a processing state of the second channel, e.g., as described above.

In some demonstrative embodiments, the operation of storing the first state context of a channel in RAM130and loading the second state context from memory130may require a relatively long time period, for example, 200 clock cycles, e.g., if a data size of the state context is about 100 times greater than width of RAM130, which may require a relatively large number of iterations to RAM130.

In some demonstrative embodiments, an efficiency of multi-channel processing module110may be relatively low, for example, if multi-channel data processor120would be required wait at an idle state during this relatively long time period during each context switch.

In some demonstrative embodiments multi-channel data processing module110may be configured to perform the context switch, during a single clock cycle, e.g., as described below.

In some demonstrative embodiments, multi-channel processing module110may include a register126(also referred to as “shadow state register”).

In some demonstrative embodiments, register126may be configured to exchange a content of register126with state context135within a single clock cycle. Register126may include, for example, a FF-based memory or any other type of memory and/or storage. Register126may have, for example, a data size substantially equal to or greater than the data size of the state context.

In some demonstrative embodiments, register126may load the second state context from RAM130, for example, prior to the context switch between the state context of the first and second channels, e.g., while multi-channel data processor120is processing the first state context of the first channel.

In some demonstrative embodiments, at the context switch between the state context of the first and second channels, multi-channel data processor120may load the second state context from register126and store the first state context in register126.

In some demonstrative embodiments, subsequent to the context switch, register126may write the first state context to RAM130, and may load from RAM130third state context of a third channel to be subsequently processed by multi-channel data processor120.

In some demonstrative embodiments, register126may be configured to “offload” from multi-cannel data processor120the task of accessing RAM130, thereby enabling multi-cannel data processor120to process the data of the plurality of channels, e.g., substantially continuously and/or at almost 100% utilization, e.g., since the single clock which is used for the context switch may be negligible compared to the duration of each channel time slot.

Reference is made toFIG. 5, which schematically illustrates a context-switch timing scheme500, in accordance with some demonstrative embodiments. In some demonstrative embodiments, a multi-channel processing module, e.g., multi-channel processing module110(FIG. 1) may utilize context-switch timing scheme500to perform a sequence of context switches between state context of a sequence of channels, e.g., including the sequence of channels denoted k−2, k−1, k, k+1 and K+2.

As shown inFIG. 5, the multi-channel processing module, e.g., multi channel data processor120(FIG. 1), may process data of the channel k−1, for example, during a channel time slot502assigned to the channel k−1, e.g., as described above. During the time slot502, the state context of the channel k−2 may be stored, for example, by writing the content of register126(FIG. 1) to RAM130(FIG. 1), and the state context of the channel k may be loaded by reading the state context of the channel k from RAM130(FIG. 1) into register126(FIG. 1).

As also shown inFIG. 5, a context switch may be performed, e.g., at the end of the timeslot502, for example, by exchanging the content between register126(FIG. 1) and the state context135(FIG. 1) of multi-channel data processor120(FIG. 1), e.g., during a single clock cycle.

As also shown inFIG. 5, multi-channel data processor120(FIG. 1) may start processing the data of the channel k during a consecutive time slot504, for example, using the state context of the channel k, e.g., substantially immediately.

As further shown inFIG. 5, during the time slot504, the state context of the channel k−1 may be stored, for example, by writing the content of register126(FIG. 1) to RAM130(FIG. 1), and the state context of the channel k+1 may be loaded by reading the state context of the channel k+1 from RAM130(FIG. 1) into register126(FIG. 1).

As further shown inFIG. 5, another context switch may be performed, e.g., at the end of the timeslot504, for example, by exchanging the content between register126(FIG. 1) and the state context135(FIG. 1) of multi-channel data processor120(FIG. 1), e.g., during a single clock cycle.

As further shown inFIG. 5, multi-channel data processor120(FIG. 1) may start processing the data of the channel k+1 during a consecutive time slot506, for example, using the state context of the channel k+1, e.g., substantially immediately.

Referring back toFIG. 1, in some demonstrative embodiments, multi-channel processing module110may include a delay controller132to maintain a constant delay between adding an input data sample to an input queue of input queues122and receiving an output data sample corresponding to the input data sample from an output queue of queues124, e.g., as described in detail below.

In some demonstrative embodiments, delay controller132may be configured to maintain a constant delay added by multi-channel data processing module110to a data path of a channel of the plurality of channels.

In some demonstrative embodiments, delay controller132may be configured to maintain a constant consistent delay of multi-channel data processing module110, for example, by consistently maintaining the constant delay after each restart of multi-channel data processor120.

Reference is now made toFIG. 6, which schematically illustrates a delay control scheme600, in accordance with some demonstrative embodiments.

In some demonstrative embodiments, delay control scheme600may control an input queue602and an output queue604of a multi-channel data processor606. For example, delay control scheme600may perform the functionality of delay controller132(FIG. 1), input queue604may perform the functionality of input queue122(FIG. 1), multi-channel data processor604may perform the functionality of multi-channel data processor120(FIG. 1) and/or output queue606may perform the functionality of output queue124(FIG. 1).

In some demonstrative embodiments, queues602and606may be flushed, e.g., when multi-channel data processor606is restarted. For example, delay control scheme600may receive a signal601indicating the restart of multi-channel data processor606.

In some demonstrative embodiments, delay control scheme600may be configured to enable writing to input queue602, while not enabling reading from output queue604, e.g., after restart.

In some demonstrative embodiments, delay control scheme600may be configured to enable reading from output queue604, for example, after a predefined threshold number of samples have been written to input queue602. For example, delay control scheme600may include a sample counter603to count the number of samples written to input queue602since restart, and to enable reading from output queue604, e.g., when the number of samples reaches the predefined threshold number of samples.

In some demonstrative embodiments, delay control scheme600may be configured to enable reading a sample from output queue604for each sample that is written to input queue602. Accordingly, delay control scheme600may maintain a constant delay.

In some demonstrative embodiments, an amount of delay in the channel may be based on the predefined threshold number of samples. Delay control scheme600may be configured to maintain a consistent constant delay of the channel for example, by maintaining the predefined threshold number of samples constant.

In some demonstrative embodiments, the predefined threshold number of samples may represent a number of samples that are “trapped” in multi-channel processing module110(FIG. 1). An actual delay of multi-channel processing module110may be obtained, for example, by multiplying the predefined threshold number of samples by a sample rate. Accordingly, channels having different sample rates may have a different delay.

FIG. 7is a schematic illustration of a delay-control timing scheme700, in accordance with some demonstrative embodiments. In some demonstrative embodiments, delay-control timing scheme700may be utilized by delay control scheme600(FIG. 6). For example, delay control scheme600(FIG. 6) may control queues602and604(FIG. 6) using write enable signal710and a read enable signal712, as described below.

As shown inFIG. 7, a restart signal708, e.g., signal601(FIG. 6), may have a restart state indicating restart of multi-channel processing module110(FIG. 1). Write enable signal710may be at a disable state to disable writing to input queue602(FIG. 6) and read enable signal712may be at a disable state to disable reading from output queue604(FIG. 6), e.g., as long as restart signal708is at the restart state.

As shown inFIG. 7, write enable signal may be switched to an enable state, e.g., immediately after restart, to enable writing to input queue602(FIG. 6). As also shown inFIG. 7, read enable signal712may remain at the disable state during a time period704, e.g., until the predefined threshold number of samples have been written to input queue602(FIG. 6).

As further shown inFIG. 7, read enable signal712may be switched to an enable state to enable reading from output queue604(FIG. 6), e.g., after the number of samples written to input queue602(FIG. 6) has reached the predefined threshold.

Referring back toFIG. 1, in some demonstrative embodiments, multi-channel processing module110may include a plurality of register files124corresponding to the plurality of channels. Register files124may store control data defining a configuration of multi-channel data processor120with respect to the plurality of channels. For example, a first register file124corresponding to the first channel may store control data defining a configuration of multi-channel data processor120with respect to the first channel, and a second register file124corresponding to the second channel may store control data defining a second configuration, different from the first configuration, of multi-channel data processor120with respect to the second channel.

In some demonstrative embodiments, multi-channel data processor120may configure control parameters corresponding to the plurality of channels based on register files124. The control parameters of a channel may include, for example, a baud of the channel, a rate of the channel, a constellation of the channel, and the like.

In some demonstrative embodiments, a register file124corresponding to a channel may also store status data corresponding to a status of the channel, e.g., as by multi-channel data processor110when processing the channel. For example, the first register file124may store status data corresponding to a status of the first channel provided by multi-channel data processor110when processing the first channel, and/or the second register file124may store status data corresponding to a status of the second channel provided by multi-channel data processor110when processing the second channel.

In some demonstrative embodiments, register files124may be accessed by a host processor (“host”)168of device100. For example, host168may update the control information of one or more of register files124, and/or host168may read the status information of one or more registers file124. In one example, host168may read the first register file124, e.g., when multi-channel data processor120processes the second channel.

Reference is made toFIG. 8, which schematically illustrates a register file scheme800, in accordance with some demonstrative embodiments.

In some demonstrative embodiments, register file scheme800may be configured to enable setting two or more different configurations to two or more channels.

In some demonstrative embodiments, register file scheme800may include a plurality of register files804corresponding to a plurality of channels to be processed by a multi-channel data processor802. For example, register files804may perform the functionality of register files124(FIG. 1).

In some demonstrative embodiments, register files804may be accessible by a host processor816. For example, host processor816may upload to a register file804, which corresponds to a particular channel, configuration information to be applied for configuring multi-channel data processor802with respect to the particular channel.

In some demonstrative embodiments, register file scheme800may include a multiplexer806to provide the configuration information of the particular channel to multi-channel data processor802, e.g., at the timeslot assigned for processing the particular channel. For example, multiplexer806may be controlled by a signal814indicative of the channel currently being processed by multi-channel data processor802.

In some demonstrative embodiments, register file scheme800may be configured to enable writing to register files804status information provided by multi-channel data processor802. Host816may access register files804to read the status corresponding to the channels.

In some demonstrative embodiments, register file scheme800may include a plurality of capture registers810corresponding to the plurality of register files804. For example, a particular register810may capture the value of a status signal812when the particular channel is being processed by multi-channel data processor802. Accordingly, host816may be able to read the status of the particular channel, e.g., even when the particular channel is not being processed by multi-channel processor802. Capture registers810may be selectively associated with multi-channel data processor802, e.g., based on signal814.

Reference is now made toFIG. 9, which schematically illustrates a method of multi-channel processing, in accordance with some demonstrative embodiments. One or more operations of the method ofFIG. 9may be performed, for example, by a system, e.g., system100(FIG. 1), a device, e.g., device102and/or104(FIG. 1), a multi-channel processing module, e.g., multi-channel processing module110(FIG. 1), and/or a multi-channel data processor, e.g., multi-channel data processor120(FIG. 1).

As indicated at block902, the method may include processing data of a plurality of channels by a multi-channel data processor. For example, multi-channel data processing module110(FIG. 1) may process the data of the N channels, e.g., as described above.

As indicated at block903, processing the data of the plurality of channels may include storing in a memory a plurality of state contexts corresponding to the plurality of channels. For example, multi-channel data processing module110(FIG. 1) may store in RAM130(FIG. 1) N state contexts corresponding to the N channels.

As indicated at block904, processing the data of the plurality of channels may include processing a first channel of the plurality of channels. For example, multi-channel data processor120(FIG. 1) may process the data of a k-th channel, e.g., as described above.

As indicated at block906, processing the data of the plurality of channels may include switching from the first channel to a second channel of the plurality of channels by performing a context switch during a single clock cycle. For example, multi-channel data processing module110(FIG. 1) may switch from the k-th channel to a k+1 channel by performing a context switch during a single clock cycle, e.g., as described above.

In some demonstrative embodiments, the context switch may include storing first state context corresponding to a processing state of the first channel, e.g., from the multichannel processor, and loading, e.g., to the multi-channel processor, previously stored second state context corresponding to a processing state of the second channel. For example, multi-channel data processing module110(FIG. 1) may store state context corresponding to a processing state of the k-th channel, e.g., in RAM130(FIG. 1), and may load, e.g., from RAM130(FIG. 1) to multi-channel processor120(FIG. 1), previously stored state context corresponding to a processing state of the k+1 channel, e.g., as described above.

As indicated at block910, the method may include loading the second state context from the memory to a register, e.g., prior to the context switch. For example, multi-channel processing module110(FIG. 1) may load the state context corresponding to the k+1 channel into register126(FIG. 1), e.g., as described above.

As indicated at block912, the method may include at the context switch, loading the second state context from the register to the multi-channel data processor and storing the first state context in the register. For example, multi-channel processing module110(FIG. 1) may load the state context corresponding to the k+1 channel from register126(FIG. 1) to multi-channel data processor120(FIG. 1), and may store the state context of the k-th channel in register126(FIG. 1), e.g., as described above.

As indicated at block914, the method may include writing the first state context from the register to the memory and loading from the memory to the register third state context of a third channel to be subsequently processed by the multi-channel data processor, e.g., subsequent to the context switch. For example, multi-channel processing module110(FIG. 1) may write the state context of the k-th channel from register126(FIG. 1) to Ram130(FIG. 1), and may load from RAM130(FIG. 1) to register126(FIG. 1) state context of a k+2 channel, e.g., as described above.

As indicated at block916, the method may include maintaining a constant delay between adding an input data sample to an input queue and receiving an output data sample corresponding to the input data sample from an output queue. For example, delay controller132(FIG. 1) may maintain a constant delay between adding an input data sample to input queue122(FIG. 1) and receiving an output data sample corresponding to the input data sample from output queue124(FIG. 1), e.g., as described above.

As indicated at block918, maintaining the constant delay may include consistently maintaining the constant delay after each restart of the multi-channel data processor. For example, delay controller132(FIG. 1) may maintain the consistent constant delay, e.g., as described above.

As indicated at block920, the method may include configuring the multi-channel data processor with first configuration for processing the first channel, and configuring the multi-channel data processor with a second configuration, different from the first configuration, for processing the second channel. For example, multi-channel data processor120(FIG. 1) may be configured based on register files124(FIG. 1), e.g., as described above.

As indicated at block922, the method may include storing status data corresponding to a status of the first channel provided by the multi-channel data processor when processing the first channel. For example, multi-channel data processor120(FIG. 1) may provide the status data to register files124(FIG. 1), e.g., as described above.

As indicated at block924, the method may include communicating with a host processor, for example, for providing the status data to the host processor, e.g., when the multi-channel data processor processes the second channel, and/or receiving the configuration information from the host processor. For example, host processor168(FIG. 1) may access register files124(FIG. 1), for example, to update the configuration information and/or to retrieve the status information, e.g., as described above.

Reference is made toFIG. 10, which schematically illustrates a product of manufacture1000, in accordance with some demonstrative embodiments. Product1000may include a non-transitory machine-readable storage medium1002to store logic1004, which may be used, for example, to perform at least part of the functionality of device102(FIG. 1), device104(FIG. 1), multi-channel processing module110(FIG. 1), multi-channel data processor120(FIG. 1), and/or to perform one or more operations of the method ofFIG. 9. The phrase “non-transitory machine-readable medium” is directed to include all computer-readable media, with the sole exception being a transitory propagating signal.