Optical sensor package and method of making an optical sensor package

A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

TECHNICAL FIELD

The present invention generally relates to the packaging of integrated circuit chips and, in particular, to the packaging of integrated circuit chips that perform optical sensor functions such as, for example, light emission and light detection.

BACKGROUND

There are a number of common optical sensor applications that require the use of an integrated circuit chip configured as a light emitter and an integrated circuit chip configured as a light detector. An example of such an optical sensor application is a Time-of-Flight (ToF) sensor which utilizes a light emitter integrated circuit chip in the form of a vertical-cavity surface-emitting laser (VCSEL) or light emitting diode (LED) and a light detector integrated circuit chip in the form of a photodiode. These optical integrated circuit chips must be packaged, and it is critical that the packaging be easily manufacturable, robust and of low cost.

SUMMARY

In an embodiment, a package comprises: a molded carrier formed by a unitary body made of a laser direct structuring (LDS) material and including back side and a front side with a blind opening extending into the unitary body of the molded carrier from the front side, said blind opening delimited by a sidewall surface and a bottom surface, wherein the unitary body includes: a floor body portion having a lower surface defining said back side and an upper surface defining the bottom surface of the blind opening and an outer peripheral wall body portion whose outer surface defines an outer surface of the molded carrier and whose inner surface defines at least part of the sidewall surface of the blind opening.

The package further comprises: a first die attach pad at the bottom surface of the blind opening; a first bonding pad at the bottom surface of the blind opening; a plurality of land grid array (LGA) pads at the back side; and a plurality of vias extending through the floor body portion to electrically connect the die attach pad to one LGA pad and electrically connect the bonding pad to another LGA pad; wherein said first die attach pad, first bonding pad, LGA pads and vias are formed by platings at LDS activated surfaces of the molded carrier.

In an embodiment, a method comprises: molding a laser direct structuring (LDS) material to form a unitary body of a wafer-scale molded carrier that includes a back side and a front side with a plurality of blind openings extending into the unitary body from the front side, each blind opening delimited by a sidewall surface and a bottom surface, wherein the unitary body includes: a floor body portion having a lower surface defining said back side and an upper surface defining the bottom surface of the blind opening and a plurality of wall body portions having inner surfaces which define the sidewall surfaces of the blind openings.

The method further comprises: laser drilling through openings extending through the floor body portion at each blind opening; activating sidewalls of the through openings; activating portions of the bottom surface and back side; plating the activated sidewalls to form vias extending through the floor body portion; plating the activated portions to form a die attach pad at the bottom surface of each blind opening; a bonding pad at the bottom surface of each blind opening; and a land grid array (LGA) pad opposite each die attach pad and bonding pad. The vias electrically connect the each die attach pad to one LGA pad and electrically connect each bonding pad to another LGA pad.

The method further comprises cutting through certain ones of the wall body portions to singulate the wafer-scale molded carrier into a plurality of assemblies.

DETAILED DESCRIPTION

Reference is made toFIGS.1A and1Bwhich show orthogonal cross-sectional views of an optical sensor package10. A substrate layer12has a front side14and a back side16. The substrate layer12may, for example, be made of an organic material normally comprising a lamination of a plurality of layers. An example of such a substrate12is commonly referred to as a printed circuit board (PCB).FIG.2shows a plan view of the front side14of the substrate layer12andFIG.3shows a plan view of the back side16of the substrate layer12. A plurality of die attach pads20are mounted to the front side14of the substrate layer12. A plurality of bonding pads22are also mounted to the front side14of the substrate layer12. The front side14of the substrate layer12may further include a plurality metal traces (see, reference15), forming a redistribution layer (RDL), that are electrically connected to the die attach pads20and/or the bonding pads22. A plurality of land grid array (LGA) pads26are mounted to the back side16of the substrate layer12. A plurality of metal vias28extend through the substrate layer12to electrically interconnect each die attach pad20(or the metal trace of the RDL connected thereto, if used) to a corresponding one of the LGA pads26and electrically interconnect each bonding pad22(or the metal trace of the RDL connected thereto, if used) to a corresponding one of the LGA pads26.

Integrated circuit chips30are mounted at the front side14of the substrate layer12to the die attach pads20. Each integrated circuit chip30includes an optical integrated circuit32and a bonding pad34at a top (or front) surface. As an example, the integrated circuit chips30may include a chip30awith a light emitter for the optical integrated circuit32in the form of a vertical-cavity surface-emitting laser (VCSEL) or light emitting diode (LED) and a chip30bwith a light detector for the optical integrated circuit32in the form of a photodiode. A bottom (or back) surface of the integrated circuit chip30is mounted to the die attach pads20using a conductive adhesive (not explicitly shown). A bonding wire38electrically connects each bonding pad34for the integrated circuit chip30to a corresponding one of the bonding pads22for the substrate layer12. It will be noted in positioning the via for the bonding pad22that it is important for the via location to be offset from the wire bonding area for the bonding wire38. The use of the RDL metal traces15can provide a way to effectively offset the via location away from the wire bonding area of pad22.

A cap structure40is mounted to the front side14of the substrate layer12. The cap structure40may have a number of different configurations as shown inFIGS.1A-1B,5A-5B and7A-7B. In the configuration shown inFIGS.1A-1B, the cap structure40comprises a cap frame42formed by an outer peripheral wall44and an inner wall46joining two opposite sides of the outer peripheral wall; with a perspective view as shown inFIG.4. The cap frame42is typically made of an opaque material. A bottom edge of the cap frame is attached to the front side14of carrier12by way of an adhesive layer (not explicitly shown). In the configuration shown inFIGS.5A-5B, the cap structure40comprises the cap frame42and a transparent cover50(for example, comprising a light filter and/or optics) mounted to an upper edge of the cap frame by way of an adhesive layer (not explicitly shown); with perspective view as shown inFIG.6. In the configuration shown inFIGS.7A-7B, the cap structure40comprises a housing60including an outer peripheral wall62, an inner wall64joining two opposite sides of the outer peripheral wall, and a cover (or front wall)66; with a perspective view as shown inFIG.8. The housing60is typically made of an opaque material. A bottom edge of the housing60is attached to the front side14of the carrier12by way of an adhesive layer (not explicitly shown). The cover66includes an opening68aligned with the location of the optical integrated circuit32of each integrated circuit chip30. A transparent optical element70(for example, comprising a light filter and/or optics) is mounted to an underside surface72of the cover66at the location of each opening68by way of an adhesive layer (not explicitly shown).

Reference is made toFIGS.9A and9Bwhich show orthogonal cross-sectional views of an optical sensor package100. A molded carrier112is made of a unitary body of material and includes a front side114and a back side116. A plurality of blind openings118extend into the unitary body of the molded carrier112from the front side114. Each blind opening118is delimited by a sidewall surface120and a bottom surface122. A depth of each opening118is less than a thickness of the molded carrier112. The material for the molded carrier112is a laser direct structuring (LDS) material.

As known to those skilled in the art, LDS is a technology where a resin containing additives is molded (for example, injection molded) to form a unitary body. A laser beam can be applied to a surface of the unitary body in order to transfer thereon a desired pattern by activating the additives. A metallization process, such as an electroless plating involving a metal such as copper, nickel and/or gold, is then used to plate a conductive pattern (matching the desired pattern of the activated additives) onto the laser treated surface. The conductive pattern may include, for example, pad structures (for forming die attach pads, bonding pads and/or land grid array (LGA) pads) and line structures (for forming metal traces of a redistribution layer (RDL)). The LDS technology can also be used to form openings in and through the unitary body that when plated (or filled) with metal form interconnection structures such as vias.

The unitary body of the molded carrier112includes a floor body portion130whose lower surface defines the back side116and whose upper surface defines the bottom surface122of each blind opening118. The unitary body of the molded carrier112also includes an outer peripheral wall body portion132whose outer surface defines the outer surface of the molded carrier112and whose inner surface defines parts of the sidewall surface120of each blind opening118. The unitary body of the molded carrier112still further includes an inner wall body portion134joining two opposite sides of the outer peripheral wall body portion132and whose lateral surfaces define further parts of the sidewall surface120of each blind opening118.FIG.10shows a perspective view of the unitary body of the molded carrier112.

FIG.11shows a top view of the optical sensor package100(i.e., looking down at the front side114) andFIG.12shows a bottom view of the optical sensor package100(i.e., looking up at the back side116).

At least one die attach pad140is mounted to the molded carrier112at the bottom surface122of each blind opening118. At least one bonding pad142is also mounted to the molded carrier112at the bottom surface122of each blind opening118. The bottom surface122may further include a plurality metal traces (see, reference145), forming a redistribution layer (RDL), that are electrically connected to the die attach pads140and/or the bonding pads142. A plurality of land grid array (LGA) pads26are mounted to the back side16of the molded carrier112. A plurality of metal vias148extend through the floor body portion130of the molded carrier112to electrically interconnect each die attach pad140(or the metal trace of the RDL connected thereto, if used) to a corresponding one of the LGA pads146and electrically interconnect each bonding pad142(or the metal trace of the RDL connected thereto, if used) to a corresponding one of the LGA pads146.

The metal vias148are formed in the molded carrier112using LDS processing techniques. A laser is used to open a hole extending completely through the floor body portion130of the molded carrier112at the locations where vias148are desired. This is accomplished using well known laser-drilling techniques. LDS activation of the additives of the LDS material at the sidewall of the hole is then performed using a laser exposure. After LDS activation of the sidewall, the activated sidewall is plated with a conductive material such as copper, nickel and/or gold. Conventional plating techniques can be used for this step (including, for example, an electroless plating process).

The die attach pads140, bonding pads142and RDL metal traces (if utilized) are formed on the bottom surface122of each blind opening118in the molded carrier112using LDS processing techniques. LDS activation of the additives of the LDS material at the bottom surface122at the locations where the die attach pads140, bonding pads142and RDL metal traces are desired is performed using a laser exposure in accordance with a pattern corresponding to the desired shapes of the die attach pads140, bonding pads142and RDL metal traces. After LDS activation of the bottom surface122, the activated portions of the bottom surface122are plated with a conductive material such as copper, nickel and/or gold. Conventional plating techniques can be used for this step (including, for example, an electroless plating process).

The LGA pads146and RDL metal traces (if utilized) are formed on the back side116of the molded carrier112using LDS processing techniques. LDS activation of the additives of the LDS material at the back side116at the locations where the LGA pads146and RDL metal traces are desired is performed using a laser exposure in accordance with a pattern corresponding to the desired shapes of the LGA pads146and RDL metal traces. After LDS activation of the back side116, the activated portions of the back side116are plated with a conductive material such as copper, nickel and/or gold. Conventional plating techniques can be used for this step (including, for example, an electroless plating process).

Integrated circuit chips150are mounted at the bottom surface122of each blind opening118to the die attach pads140. Each integrated circuit chip150includes an optical integrated circuit152and a bonding pad154at a top (or front) surface. As an example, the integrated circuit chips150may include a chip150awith a light emitter for the optical integrated circuit152in the form of a vertical-cavity surface-emitting laser (VCSEL) or light emitting diode (LED) and a chip150bwith a light detector for the optical integrated circuit152in the form of a photodiode. A bottom (or back) surface of the integrated circuit chip150is mounted to the die attach pads140using a conductive adhesive (not explicitly shown). A bonding wire158electrically connects each bonding pad154for the integrated circuit chip150to a corresponding one of the bonding pads142at the bottom surface122of each blind opening118. It will be noted in positioning the via for the bonding pad142that it is important for the via location to be offset from the bonding area for the bonding wire158. The use of the RDL metal traces145can provide a way to effectively offset the via location away from the bonding area of pad142.

A protective structure160may be utilized to protect the integrated circuit chips150. The protective structure160may have a number of different configurations as shown inFIGS.13A-13B,14A-14B and15A-15B. In the configuration shown inFIGS.13A-13B, the protective structure160comprises a transparent material162that fills each of the blind openings118in the molded carrier112. In the configuration shown inFIGS.14A-14B, the protective structure160further comprises a cap layer164extending over the co-planar front side114of the molded carrier112and front surface166of the transparent material162fill. The cap layer164is preferably made of an opaque resin material that is transfer molded onto the assembly that includes the molded carrier112and the transparent material162fill, or the structure or is separately molded and attached to that assembly using an adhesive. The cap layer164includes an opening168aligned with the location of the optical integrated circuit152of each integrated circuit chip150. In the configuration shown inFIGS.15A-15B, the protective structure160comprises a transparent plate170that is attached to the front side114of the molded carrier112. The transparent plate170may, for example, be made of a glass material.

In an embodiment, the molded carrier112with LDS fabricated die attach pads140, bonding pads142, LGA pads146and RDL metal traces as shown in any of the implementations ofFIGS.9A-9B,13A-13B,14A-14B and15A-15Bmay include a solder resist layer180as shown inFIGS.16A-16B. The layer180may be provided on both the bottom surface122of each blind opening118and the back side116of the molded carrier112(as shown inFIGS.16A-16B). Alternatively, the layer180may be provided only on the back side116of the molded carrier112. The layer180includes openings182at the locations of the die attach pads140, bonding pads142and LGA pads146(and will typically cover the RDL metal traces, if present).

Reference is now made toFIGS.17A to171-2for a description of a wafer scale method of manufacturing the optical sensor packages.FIG.17Ashows the result of a molding process wherein a laser direct structuring (LDS) material is molded to form a wafer-scale carrier112′ that includes a plurality of blind openings118. Notice should be made of the wall body portions132′ between some of the openings118which have a width W that is sufficient to allow cutting therethrough so as to form two peripheral wall body portions132. The molding process may, for example, utilize well known injection molding techniques where the LDS material is injected into a cavity defined by a closed two-part mold, with the first and second mold forms of the two-part mold defining the faces114,116and the openings118.FIG.17Bshows the result of the performance of the laser drilling, LDS surface activation and plating operations that define the die attach pads140, bonding pads142(not explicitly shown), LGS pads146, vias148and RDL metal traces (if needed).FIG.17Cshows the result of the performance of the process for depositing and patterning the solder resist layer180. It will be noted thatFIG.17Cshows presence of the solder resist layer180on both the bottom surface of each opening118and the back side of the carrier112′. This is just one example implementation, and in an alternative implementation the solder resist layer180is provided only on the back side of the carrier112′. Any suitable deposition or printing process can be used to provide the patterned solder resist layer180.FIG.17Dshows the result of the performance of the process for attaching the integrated circuit chips150to the die attach pads140. Any suitable pick-and-place operation can be used to install the chips150in the openings118.FIG.17Eshows the result of the performance of the process for electrically connecting the bonding pads of the chips150to the bonding pads142(not explicitly shown) with a bonding wire158. Any suitable wirebonding operation can be used to make the electrical connection.

As noted above, there are several options for providing a protective structure160protect the integrated circuit chips150. With respect to the configuration shown in FIGS.13A-13B,FIG.17F-1shows the result of the performance of the process for depositing a transparent material162that fills each of the blind openings118in the wafer-scale molded carrier112′.FIG.17F-2shows the result of the performance of the process for singulating the assembly by cutting through (reference190) the walls132′ to produce individual optical sensor packages.

With respect to the configuration shown inFIGS.14A-14B,FIG.17G-1shows the result of the performance of the process for depositing a transparent material162that fills each of the blind openings118in the wafer-scale molded carrier112′.FIG.17G-2shows the result of the performance of the process for providing a cap layer164(with openings168) extending over the co-planar front side of the wafer-scale molded carrier112′ and front surface of the transparent material162fill. The cap layer164is preferably made of an opaque resin material that is transfer molded onto the assembly that includes the wafer-scale molded carrier112′ and the transparent material162fill, or the structure or is separately molded and attached to that assembly using an adhesive.FIG.17G-3shows the result of the performance of the process for singulating the assembly by cutting through (reference190) the walls132′ to produce individual optical sensor packages.

With respect to the configuration shown inFIGS.15A-15B,FIG.17H-1shows the result of the performance of the process for attaching a transparent wafer192to the front side of the wafer-scale molded carrier112′.FIG.17H-2shows the result of the performance of the process for singulating the assembly by cutting through (reference190) the walls132′ and wafer192to produce individual optical sensor packages, where each package includes a transparent plate170.

In an alternative implementation for the configuration shown inFIGS.15A-15B,FIG.171-1shows the result of the performance of the process for singulating the assembly by cutting through (reference190) the walls132′ to produce a plurality of assemblies, with each assembly including the molder carrier112.FIG.171-2shows the result of the performance of the process for attaching the transparent plate170to the front side of the molded carrier112for each singulated assembly.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.