Printed circuit board with ground corner regions

Plural pins are arranged on a printed circuit board to form a generally square shape and are electrically connected to terminals of a QFP-IC. In the pins, a pin disposed at a corner portion of the generally square shape is used as a GND terminal, and a pin adjoining the GND terminal is used as a source terminal. A conductive region is provided to extend radially from the corner portion, and is electrically connected to the ground terminal. Further, another conductive region is provided in the generally square shape and is electrically connected to the radial conductive region.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of Japanese Patent Application No. 2000-243282 filed on Aug. 10, 2000, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a printed circuit board on which ICs are mounted, which is suitably used for electronics that are required to have a reduced noise level, such as an IC for controlling vehicle braking.

2. Description of the Related Art

Recently, various regulations have required a reduction in the noise level of ICs, a typical example of which is a central processing unit. In a conventional IC, two opposed pins (two terminals respectively disposed at opposed two sides when the IC forms a rectangle) receive a source potential and a ground potential, respectively. However, plural terminals are conventionally arranged for receiving the source potential and the ground potential in an IC, in view of noise regulations.

In such a case, because the number of required pins is increased, package size and the number of bypass-capacitors are increased. As a result, an area of a substrate occupied by the bypass-capacitors and wiring members for connecting them is increased.

Further, this effect lessens flexibility of substrate pattern design to make the noise countermeasures on the substrate difficult. As a result, the noise level may be raised on the contrary. Incidentally, it is conceivable that a multilayered substrate can solve the above-described problem; however, the multilayered substrate results in high cost.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above problem. An object of the present invention is to decrease a noise level while suppressing an increase in occupied substrate area.

According to the present invention, in a printed circuit board on which a plurality of pins are arranged to form a generally polygonal shape, the pins includes a first pin as a ground terminal and a second pin as a source terminal. The ground terminal is disposed at a corner portion of the generally polygonal shape, and the source terminal adjoins the ground terminal. Further, a first conductive region extends radially from the corner portion of the polygonal shape and is electrically connected to the ground terminal.

Because the source terminal adjoins the ground terminal, a substrate area occupied by a bypass capacitor can be restricted from increasing. Further, because the ground terminal is electrically connected to the first conductive region, ground impedance can be lowered, resulting in noise reduction.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 , in a preferred embodiment, a QFP (Quad Flat Package)-IC 2 is mounted on a printed circuit board 1 . Several pins (terminals) 3 are arranged in a generally square shape on the printed circuit board 1 . Each pin 3 is disposed to extend in a direction perpendicular to a corresponding side forming the square shape. These pins 3 are respectively connected to electronic parts and the like (not shown) disposed on the printed circuit board 1 and the like.

In these pins 3 , pins 3 a are arranged at edge portions of the respective sides constituting the generally square shape, and are used as GND terminals (ground terminals) having a ground potential. Pins 3 b are disposed to adjoin the respective pins 3 a , and are used as source terminals having a source potential. The pines 3 a are referred to as GND terminals and the pins 3 b are referred to as source terminals.

The QFP-IC 2 is mounted in the central portion of the pins 3 arranged in the generally square shape, and terminals formed with the QFP-IC 2 are electrically connected to the pins 3 through wires 4 by wire bonding. Incidentally, although FIG. 1 shows only wires connected to one GND terminal 3 a and one source terminal 3 b , in practice, all the pins 3 are electrically connected to the QFP-IC 2 through the wires 4 .

A conductive pattern 5 is printed on the printed circuit board 1 to be electrically connected to the GND terminals 3 a . Referring to FIG. 2 , a slant portion corresponds to a region where the conductive pattern 5 is formed on the printed circuit board 1 . The conductive pattern 5 is disposed, by set-solid printing, at an inside of the generally square shape formed by the pins 3 , at the respective corner portions of the generally square shape, and at portions connecting these regions.

In the conductive pattern 5 , conductive regions 5 a disposed on the corner portions extend radially from the respective corner portions. That is, on each corner portion of the generally square shape, two GND terminals 3 a are disposed to extend perpendicularly to the respective sides of the square shape and perpendicularly to each other. That is, the two GND terminals 3 a define therebetween a space having an about right-angled corner, and in the space, there is no pin connected to a terminal of the QFP-IC 2 . Each conductive region 5 a is formed in this space by printing. Incidentally, in the present embodiment, each conductive region 5 a extends radially, i.e., further outside the GND terminals 3 a arranged at the edges of the sides. More specifically, the GND terminals 3 a do not define a gap with the conductive region 5 a disposed outside thereof.

Also, the conductive pattern 5 has a conductive region 5 b disposed inside the generally square shape. The conductive region 5 b is formed by printing to contain a region corresponding to almost an entire area of the generally square shape, i.e., to contain a region facing the back surface of the QFP-IC 2 shown in FIG. 1 , but has a side slightly shorter than that of the generally square shape formed by the edges of the pins at the side of the QFP-IC 2 .

Conductive regions 5 c of the conductive pattern 5 , which connect the conductive regions 5 a and the conductive region 5 b , are formed by printing to pass through the inside and the outside of the generally square shape formed by the pins 3 , via gaps between the GND terminals 3 a positioned on the respective corner portions. Each gap defined between the GND terminals 3 a disposed at each corner portion may be changed in accordance with the width of the corresponding conducive region 5 c . Here, the gap is set at a dimension that allows current to flow out through the conductive region 5 c and that enables low impedance between the GND terminals 3 a.

Further, bypass capacitors 6 are disposed between the conductive region 5 a of the conductive pattern 5 and the respective source terminals 3 b . Thus, because the respective source terminals 3 b adjoin the respective GND terminals 3 a , a length of a wiring member for each bypass capacitor 6 disposed between the terminals 3 a , 3 b can be made shortest. As a result, a substrate area occupied by wiring members of the bypass capacitors 6 can be prevented from increasing largely.

Connecting configurations of the bypass capacitors 6 are determined based on the size of each bypass capacitor 6 as follows.

The relation between the size of the bypass capacitor 6 and the connecting configurations is explained referring to FIGS. 3A to 3 F. The connecting configurations of the bypass capacitor 6 are sorted into two cases where an arrangement direction of the neighboring GND terminal 3 a and the source terminal 3 b corresponds to a longitudinal direction of the bypass capacitor 6 (lateral arrangement), and where the arrangement direction is perpendicular to the longitudinal direction of the bypass capacitor 6 (lengthwise arrangement).

FIGS. 3A to 3 F schematically show connecting configurations of bypass capacitors 6 having different sizes in the cases where each bypass capacitor is disposed at a lateral or lengthwise arrangement. Specifically, FIGS. 3A and 3D show a case where the bypass capacitor 6 has dimension S in the longitudinal direction that is sufficiently larger than interval T between the GND terminal 3 a and the source terminal 3 b , FIGS. 3B and 3E show a case where the dimension S is larger than the interval T, and FIGS. 3C and 3F show a case where the dimension S is approximately equal to the interval T. Further, FIGS. 3A to 3 C shows the case of the lateral arrangement, while FIGS. 3D to 3 F shows the case of the lengthwise arrangement.

As shown in FIGS. 3A to 3 C, ends of the bypass capacitor 6 are respectively connected to a pad 7 a formed with the conductive pattern 5 and a pad 7 b extending from the source terminal 3 b . Comparing lengths of current passes flowing from the source terminal 3 b to the GND terminal 3 a through the bypass capacitor 6 in the respective cases shown in FIGS. 3A to 3 C, the current pass at the lengthwise arrangement is shorter than that at the lateral arrangement in the case where the dimension S of the bypass capacitor 6 is larger than the interval T between the GND terminal 3 a and the source terminal 3 b . On the other hand, in the case where the dimension S is approximately equal to the interval T, the current pass at the lateral arrangement is shorter than that at the lengthwise arrangement.

Because of this, the bypass capacitor 6 and the conductive pattern 5 and the source terminal 3 b are electrically connected to each other with a configuration that is selected to make the current pass short based on the relation between the dimension S of the bypass capacitor 6 and the interval T between the GND terminal 3 a and the source terminal 3 b.

At that time, it is preferable that no via (via hole) is disposed on the current pass mainly extending between the pad 7 b of the bypass capacitor 6 as a source terminal and the source terminal 3 b . This is to make almost all source current pass through the vicinity of the pads 7 b of the capacitor 6 . A main current line from the source terminal 3 b should not branch on the way toward the bypass capacitor 6 . No via means no branch on the way.

The printed circuit board 1 having the above structure has the following advantages.

First, the GND terminals 3 a are arranged at the corner portions of the generally square shape formed by the pins 3 , and the conductive pattern 5 formed on the printed circuit board 1 is connected to the GND terminals 3 a at the corner portions. Because of this, the ground impedance between the GND terminals 3 a can be lowered.

Accordingly, occurrence of ground bounce can be restricted when a signal return current from the QFP-IC 2 flows, and noise propagation to other circuits can be prevented. Also, because the impedances between the GND terminals 3 a of the QFP-IC 2 and between the bypass capacitors 6 can be lowered, noise produced by feed through current, which is produced in switching MOSFET and the like formed in the QFP-IC 2 , can be lessened.

Because the source terminal 3 b and the GND terminal 3 a are disposed adjacently to each other, the mutual inductance between the respective terminals can be raised. The mutual inductance works to cancel the self-inductance. Therefore, the occurrence of a counter electromotive force by inductance can be decreased. Further, because the length of the wiring member for the bypass capacitor (decoupling capacitor) 6 can be made shortest by disposing the bypass capacitor 6 between the source terminal 3 b and the GND terminal 3 a adjoining each other, the ESL (parasitic serial inductance) of the capacitor can be minimized, resulting in noise reduction.

Also, the conductive region 5 b is formed by set-solid printing at a region including the lower part of the QFP-IC 2 , and the respective GND terminals 3 a are connected to each other through the conductive region 5 b , thereby achieving low impedance between the GND terminals 3 a . Because of this, the GND terminals 3 a can be stabilized, and the noise amount can be reduced. Further, a direct radiant quantity from the QFP-IC 2 can be reduced due to an effect of image current flowing in the conductive pattern 5 immediately under the QFP-IC 2 .

The noise reducing effect in the case of adopting the printed circuit board 1 constructed as above was experimentally compared to a conventional one. Specifically, assuming the printed circuit board 1 in the present embodiment, a printed circuit board shown in FIG. 4A was prepared. In the printed circuit board, conductive regions 5 a are provided at two corner portions of a square shape, and a square conductive region 5 b is provided and connected to the conductive regions 5 a through conductive regions 5 c . Further, a conventional printed circuit board as shown in FIG. 4B was prepared as a comparative sample, in which neighboring two pins 3 a , 3 b , which are disposed at one side of a square shape, are set to have a source potential and a ground potential, respectively. Then, noise of the two printed circuit boards' was examined. The results are shown in FIG. 5 .

This figure shows voltage fluctuations in the QFP-IC 2 with a frequency in a specific range, and the fluctuation amount corresponds to noise. In FIG. 4B , the fluctuation was measured at a grounded terminal 3 b at an opposite side of the two pins 3 a , 3 b . A solid line indicates the voltage fluctuation in the case of the printed circuit board 1 shown in FIG. 4A , and a one-dot chain line indicates the voltage fluctuation in the case of the conventional printed circuit board shown in FIG. 4 B.

According to this result, it is revealed that the noise in the case of the printed circuit board 1 shown in FIG. 4A is sufficiently reduced in comparison with the noise in the case of the conventional printed circuit board shown in FIG. 4 B.

As explained above, in the printed circuit board 1 according to the present embodiment, noise can be reduced without increasing the substrate area occupied by the bypass capacitors 6 and the wiring members thereof.

In the above-described embodiment, although the radial conductive regions 5 a are disposed at all the corner portions of the generally square shape formed by the several pins, it is not always necessary that all the corner portions have the radial conductive portions 5 a . For example, as shown in FIG. 6 , the conductive regions 5 a may be formed at only two corner portions positioned at both ends of one side of the generally square shape. Otherwise, as shown in FIG. 7 , the conductive regions 5 a may be formed at only two corner portions diagonally disposed in the generally square shape.

Also, in the above-described embodiment, the two GND terminals 3 a disposed at one corner are connected to the conductive region 5 a ; however, the effect of reducing the ground impedance of the GND terminals 3 a can be attained by connecting at least one GND terminal 3 a . In this case, it is not necessary that the conductive region 5 a occupies the entire space having about 90 degrees and defined between the two terminals, and for example, about a half of the space may be occupied by the conductive region 5 b . Further, the present invention is not limited to the case where respective ends of sides forming a corner portion are connected to ground terminals, but the present invention can be applied to a case where only one end may be connected to a ground terminal.

In the above-described embodiment, the conductive region 5 a is radial and has an angle of about 90 degrees; however, it is not limited to this structure provided that, when the bypass capacitor 6 is disposed, the wiring width can be set at W/2 where W is the maximum length between the GND terminals 3 a (FIG. 2 ), i.e., the conductive region 5 a has a dimension in a radial direction that is approximately W/2 at least. That is, the minimum wiring width (ground width) should be secured even when the conductive regions 5 a are not arranged ideally due to the various parts mounted on the printed circuit board and the layout thereon. Then, the arrangements of the bypass capacitors 6 (lengthwise arrangement, lateral arrangement) should be determined appropriately to satisfy the above relation.

Also, as shown in FIG. 8A , a ground via 10 may be formed to electrically connect the conductive region 5 a with a conductive pattern formed on another layer and having a ground potential. Further, as shown in FIG. 8B , although it does not achieve electrical connection of the conductive region 5 a , a via 11 may be formed for signal transmission for achieving electrical connection between other layers (for example, between second and third layers).

Although the above-described embodiment exemplifies the case where the several pins are arranged to form a generally square shape, several pins may be arranged to form a generally polygonal shape (for example, a quadrangle) and the present invention is applicable in this case as well.