Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

FIELD OF THE DISCLOSURE

The present disclosure is directed to a hard macro having blockage sites and toward a method of routing through the hard macro, and, more specifically, toward a hard macro having a plurality of blockage sites at which vias can be formed and toward a method of routing an electrical connection through the hard macro by forming vias at the blockage sites.

BACKGROUND

“Macros” or “cores” are functional circuit elements or building blocks or units of logic that can be used by chip fabricators to create an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Two common types of macros are referred to as “soft” and “hard” macros. Soft macros include logic for performing a particular function along with various interconnection rules for connecting sub-portions of the soft macro and/or for connecting portions of the soft macro to other elements outside the soft macro. They may comprise, for example, a gate-level netlist. Soft macros do not specify a physical wiring pattern and thus allow for flexibility in final physical implementation; however, due to the lack of a pre-specified physical wiring pattern, they may need to be optimized for desired performance and/or final layout in a floor-plan. Hard macros specify a fixed wiring pattern and are not modifiable. Hard macros are thus less flexible than soft macros but can be optimized for performance and physical layout prior to use.

Hard and soft macros are used in two dimensional integrated circuits. However, it is becoming more common to stack multiple integrated circuit layers and form three dimensional integrated circuits or “3D IC's” to achieve higher device packing density, lower interconnect RC delay, and lower cost. The size and configuration of macros must be taken into account during the floor-planning of a chip, especially a 3D IC. Soft macros may be modified to a degree and thus it may sometimes be possible to allow connections from elements in a layer above the soft macro to elements in a layer below the soft macro to run through the soft macro. Hard macros, however, have a fixed form factor, and it is generally necessary to route inter-layer connections around them. This increases the length of various interconnections and may require the use of additional buffers to compensate. Regions near the edges of hard macros can also become congested with conduction pathways from elements above or below the hard macro that need to pass by the hard macro to reach another layer of the chip.

FIG. 1shows a multi-layer chip100having a first layer102having a first circuit element104, a second layer106having a hard macro108, and a third layer110having a second circuit element112. The first circuit element104and/or second circuit element112could alternately represent pins or connection pads for the multi-layer chip100rather than actual circuit elements. The design of the chip100requires that the first circuit element104be connected to the second circuit element112located on the layer beneath the hard macro and two layers below the first circuit element104. In order to make this connection, a via114is provided at a distance from the hard macro108, and the first circuit element104is connected to the via114by a first trace116and the second circuit element is connected to the via114by a second trace118. If the hard macro108were not present, a via could be provided directly beneath or closer to the first circuit element104or the second circuit element112to shorten the connection path therebetween. The presence of the hard macro108in the second layer106between the first and second circuit elements104,112increases the length of the connection between the first and second circuit elements104,112.

In some cases it may be possible to break a single large hard macro into two or more smaller hard macros and provide the necessary interconnection rules for allowing the hard macros to communicate and to operate as if they were a single hard macro. This arrangement, however, requires on-chip optimization and may lead to a decrease in chip performance. It would therefore be desirable to provide a hard macro that retains the benefits of hard macros discussed above and which allows for greater flexibility in routing.

SUMMARY

The following summary is not an extensive overview of all contemplated aspects. As sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

An aspect of the disclosure comprises a hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom.

Another aspect of the disclosure comprises a non-volatile computer readable medium storing instructions that, when executed by a computer, cause a computer-controlled device to create a hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, and a plurality of vias extending through the hard macro from the top to the bottom.

A further aspect of the disclosure comprises a hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom. The hard macro includes a regular pattern of blockage sites on the hard macro top, the blockage sites extending through the hard macro from the top to the bottom.

Still another aspect of the disclosure comprises a non-volatile computer readable medium storing instructions that, when executed by a computer, cause a computer-controlled device to create a hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, and a regular pattern of blockage sites on the hard macro top, the blockage sites extending through the hard macro from the top to the bottom.

Still a further aspect of the disclosure comprises an integrated circuit including a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace. The top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Another aspect of the disclosure comprises a non-volatile computer readable medium storing instructions that, when executed by a computer, cause a computer-controlled device to create an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace. The top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

A further aspect of the disclosure comprises a method that includes forming a first layer of an integrated circuit, forming a second layer of the integrated circuit on the first layer of the integrated circuit, the second layer including at least one hard macro, forming at least one via through the hard macro, forming a third layer on top of the second layer, and electrically connecting an element on the first layer to an element on the third layer using the at least one via.

Still another aspect of the disclosure comprises an integrated circuit comprising a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including hard macro means form performing an operation and the bottom layer including a bottom layer conductive trace. The top layer conductive trace is connected to the bottom layer conductive trace by the hard macro means.

Still a further aspect of the disclosure comprises a method that includes steps for forming a first layer of an integrated circuit, steps for forming a second layer of the integrated circuit on the first layer of the integrated circuit, the second layer including at least one hard macro, steps for forming a via through the hard macro, steps for forming a third layer on top of the second layer and steps for electrically connecting an element on the first layer to an element on the third layer using the via.

DETAILED DESCRIPTION

The terminology used herein is only for the purpose of describing particular examples according to embodiments, and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein the terms “comprises”, “comprising,”, “includes” and/or “including” specify the presence of stated structural and functional features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other structural and functional feature, steps, operations, elements, components, and/or groups thereof.

Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields, electron spins particles, electrospins, or any combination thereof.

The term “topology” as used herein refers to interconnections of circuit components and, unless stated otherwise, indicates nothing of physical layout of the components or their physical locations relative to one another. Figures described or otherwise identified as showing a topology are no more than a graphical representation of the topology and do not necessarily describe anything regarding physical layout or relative locations of components.

FIG. 2illustrates a multi-layer chip200having a first layer202having a first circuit element204, a second layer206having a hard macro208, and a third layer210having a second circuit element212. The first circuit element204and/or second circuit element212could alternately represent pins or connection pads for the multi-layer chip200rather than actual circuit elements. The design of the multi-layer chip200requires that the first circuit element204be connected to the second circuit element212located on the layer beneath the hard macro208and two layers below the first circuit element204. The hard macro208is provided with at least one and preferably a plurality of blockage sites214that are formed without logic elements or connections and at which blockage sites214vias216can be formed without adversely affecting the operation of the hard macro208. InFIG. 2, three blockage sites214are illustrated; however a greater or lesser number of blockage sites214can be provided on the chip200. Instead of routing a connection from the first circuit element204to the second circuit element212around the edge of the hard macro208, a via216is formed at one of the blockage sites214to provide a shorter connection path from the first circuit element204to the second circuit element212. The blockage sites211extend linearly through the hard macro208.

FIGS. 3 and 4illustrate a multi-layer chip300having a first layer302having a first circuit element301, a second layer306having a hard macro308, and a third layer310having a second circuit element312. The first circuit element304and/or the second circuit element312could alternately represent pins or connection pads for the multi-layer chip300rather than actual circuit elements. The design of the multi-layer chip300requires that the first circuit element301be connected to the second circuit element312located on the layer beneath the hard macro308and two layers below the first circuit element304. The hard macro308is provided with at least one and preferably a plurality of blockage sites314that are formed without logic elements or connections and at which blockage sites314vias318can be formed without adversely affecting the operation of the hard macro308. Only two blockage sites314are illustrated inFIGS. 3 and 4, but a greater number would generally be provided. Unlike the multi-layer chip200ofFIG. 2, the blockage sites314of chip300are horizontally offset from at least one of the first circuit element304and the second circuit element312. However, even with such offsets, the connection from the first circuit element304to the second circuit element312is shorter than connections of the prior art which would have needed to route completely around the hard macro308.

FIG. 3shows a first connection route316which connects the first circuit element304to the second circuit element312by way of a via318in one of the blockage sites314close to the first circuit element304.FIG. 4shows a second connection route402which connects the first circuit element304to the second circuit element312by way of a via404formed in the blockage site314closer to the second circuit element312. Which of these two routes is selected for via placement may depend on the other connections to and among the first and second circuit elements301,312and/or the other circuit elements (not shown) and/or other electrical pathways (not shown) on the first, second and third layers302,306and310.

It may be possible to design a hard macro with blockage sites located in predetermined locations based on the desired final design of the 3D integrated circuit and the various elements that it will contain. However, it may be more practical to provide a relatively large number of blockage sites on the hard macro to provide flexibility to circuit designers who can place vias at as few or as many of the blockage sites as needed when laying out circuit interconnections. With reference toFIG. 5, hard macro500includes a plurality of blockage sites502arranged in a regular pattern having a constant spacing therebetween in the X and Y directions, a mesh or array of rows and columns in this case. The regular pattern could alternately have a regular spacing in one direction only or be arranged in a zigzag or non-rectangular pattern. The locations of the blockage sites may also be arranged in an irregular pattern. It should be noted that the blockage sites take up very little room and need only be large enough to accommodate several vias. The vias are so small that a few can be formed even in very small blockage areas. The size of the blockage sites relative to the hard macros and to the circuit elements are greatly exaggerated in the drawings.

It is unlikely that a circuit designer will ultimately form a via at every one of these blockage sites. It is also unlikely that elements which require interconnection will be located directly above and below a blockage site and so that they can be connected by a single vertical electrical connection. However, the large number of blockage sites spread across the surface of the hard macro provides improved routing flexibility and reduces the need to route around the edge of a hard macro, instead, providing various pathways through the hard macro which can be used as necessary.

Locations for the blockage sites are determined in part based on the block-to-block pin statistics from the block-level design netlist. Based on relevant design rules (including inter-tier via/landing pad pitch, etc.) and the block-to-block pin statistics the area available for blockage sites is calculated. Given the allowable area overhead budget (which is minimal due to extremely small sizes of monolithic 3D inter-tier vias) the number of blockage sites across the block can be determined. After blockage insertion, the modified block is taken through the physical implementation, e.g., placement and routing (“P&R”).

FIG. 6illustrates an exemplary wireless communication system600in which one or more embodiments of the disclosure may be advantageously employed. For purposes of illustration,FIG. 6shows three remote units620,630, and650and two base stations640. It will be recognized that conventional wireless communication systems may have many more remote units and base stations. The remote units620,630, and650include integrated circuits or other semiconductor devices625,635and655(including hard macros as disclosed herein), which are among embodiments of the disclosure as discussed further below.FIG. 6shows forward link signals680from the base stations640and the remote units620,630, and650and reverse link signals690from the remote units620,630, and650to the base stations640.

InFIG. 6, the remote unit620is shown as a mobile telephone, the remote unit630is shown as a portable computer, and the remote unit650is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be any one or combination of a mobile phone, hand-held personal communication system (PCS) unit, portable data unit such as a personal data assistant (PDA), navigation device (such as GPS enabled devices), set top box, music player, video player, entertainment unit, fixed location data unit such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 6illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the disclosure may be suitably employed in any device having active integrated circuitry including memory and on-chip circuitry for test and characterization.

A method according to an embodiment comprises a block702of forming a first layer of an integrated circuit, a block704of forming a second layer of the integrated circuit on the first layer of the integrated circuit, the second layer including at least one hard macro, a block706of forming a via through the hard macro, a block708of forming a third layer on top of the second layer and a block710of electrically connecting an element on the first layer to an element on the third layer using the via.

The foregoing disclosed devices and functionalities (such as the devices ofFIGS. 2-5or any combination thereof) may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The semiconductor chips can be employed in electronic devices, such as described hereinabove.

Accordingly, an embodiment of the invention can include a computer readable medium embodying a method for implementation. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.