Electrical erasable programmable read-only memory and manufacturing method thereof

An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.

The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2011-0105445 (filed on Oct. 14, 2011), which is hereby incorporated by reference in its entirety.

BACKGROUND

Non-volatile memory devices such as EEPROMs or similar devices may be capable of storing information even when the supply of external power is stopped. EPROMs may include an EPROM having a stacked-gate structure in which two polycrystalline silicon layers acting as a gate are vertically stacked, an EPROM having a single gate structure using a single polycrystalline silicon layer, and similar configurations.

Stacked-gate structure EPROMs may be advantageous for high integration of devices, but stacked-gate structure EPROMs may have the drawback of requiring a relatively complicated manufacturing process that includes manufacturing together with logic devices (e.g. metal oxide semiconductor field effect transistors (MOSFET) or complementary MOSFET (CMOSFET) that use a single gate process in a single-layered structure). However, single gate structure EPROMs have a relatively simple standard process, even though single gate structure EPROMs may have drawbacks compared to stacked-gate structure EPROMs in terms of cell integration and performance.

Accordingly, single gate structure EEPROMs may often be embedded in CMOS logic and mixed-signal circuits and usefully applied as low-priced, low-density devices. A single gate structure EPROM may be compatible with a standard logic process and therefore memory cell functions may be added without significant additional processes or cost. Accordingly, single gate structure EPROMs may be easily mounted in a logic device product.

FIG. 1is a top plan view of an EPROM having a single gate structure andFIG. 2is a cross-sectional view of the EPROM shown inFIG. 1, in accordance with the related art. An EPROM may include P-type well12and N-type well13formed in parallel on/over a semiconductor substrate11. P-type well12and N-type well13may be isolated from each other by swallow trench isolation (STI) region14. First gate insulation film15may be formed on/over semiconductor substrate11where P-type well12is formed. First gate16or a select gate (SG) may be formed on/over first gate insulation film15.

An N-type source junction region may be formed in an upper portion of P-type well12at one side of first gate16. An N-type drain junction region may be formed in an upper portion of P-type well12at the other side of first gate16. Accordingly, select NMOS transistor1may be formed by first gate16and source/drain junction regions18. Similarly, first gate insulation film15may be formed on/over semiconductor substrate11where N-type well13is formed. Second gate17or floating gate (FG) may be formed on/over first gate insulation film15.

A P-type source junction region may be formed in an upper portion of N-type well13at one side of second gate17. A P-type drain junction region may be formed in an upper portion of N-type well13at the other side of second gate17. Floating PMOS transistor2may be formed by second gate17and source/drain junction regions19. Salicide blocking layer20may be formed on/over second gate17, thereby preventing salicide from being formed on second gate17.

However, EPROMs according to the related art may have a problem that electrical erasure is impossible or unreliable even with the advantage of a simplified standard manufacturing process.

SUMMARY

Embodiments relate to an electrical erasable programmable read-only memory (EEPROM) which is useable as multiple time programmable (MTP) EEPROM with by enabling electrical erasure while maintaining a small cell size through the change of the structure of a single gate EPROM, and a manufacturing method thereof.

Embodiments relate to an EEPROM including at least one of: (1) A floating transistor formed on/over a semiconductor substrate. (2) A tunneling transistor formed on/over a semiconductor substrate and configured to erase electrons trapped in the floating transistor, wherein the tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion.

In embodiments, the width of the gate of the tunneling transistor is narrower than the width of the gate of the floating transistor. In embodiments, the gate of the floating transistor has a width ranging from about 0.5 μm to 0.6 μm. In embodiments, the gate of the tunneling transistor has a width ranging from. about 0.16 μm to 0.2 μm. In embodiments, the gate of the tunneling transistor has an end portion intersecting edge portions of the source junction region and the drain junction region at a preset length. In embodiments, the preset length ranges from about 0.16 μm to 0.2 μm.

Embodiments relate to a method for manufacturing an EEPROM including at least one of: (1) Forming a floating gate and a tunneling gate on/over a semiconductor substrate. (2) Forming a floating transistor by forming a source junction region and a drain junction region in contact with the floating gate. (3) Forming a tunneling transistor by forming a source junction region and a drain junction region integrally joined by lateral diffusion in contact with the tunneling gate.

In embodiments, the width of the tunneling gate is formed to be narrower than of the width of the floating gate. In embodiments, an end portion of the tunneling gate is formed to intersect edge portions of the integrally connected source junction region and drain junction region at a preset length. In embodiments, the integrally joined source junction region and drain junction region are formed by an ion implantation process with a tilt of about 25° to 45°. In embodiments, the ion implantation process is performed at an ion implantation energy ranging from about 65 KeV to 100 KeV is used and a dose amount ranges from about 5E12/cm2to 1E13/cm2.

DETAILED DESCRIPTION

The advantages and features of embodiments and methods of accomplishing these will be clearly understood from the following description taken in conjunction with the accompanying drawings. However, embodiments are not limited to those embodiments described, as embodiments may be implemented in various forms. It should be noted that the present embodiments are provided to make a full disclosure and also to allow those skilled in the art to know the full range of the embodiments. Therefore, the embodiments are to be defined only by the scope of the appended claims.

FIG. 3is a top plan view of an EEPROM in accordance with embodiments.FIG. 4is a cross-sectional view of the EEPROM illustrated inFIG. 3, in accordance with embodiments. A cross-sectional view taken along the line IV-IV ofFIG. 3is illustrated on the left inFIG. 4and a cross-sectional view taken along the line IV′-IV′ ofFIG. 3is illustrated on the right inFIG. 4.FIGS. 3 and 4illustrate only a unit cell region of the EEPROM, in accordance with embodiments.

Hereinafter, for convenience of explanation, first well111of the first conductivity, second well131of the first conductivity, well121, source/drain junction regions127of the first conductivity, first source/drain junction regions117of the second conductivity, and second source/drain junction regions137of the second conductivity are designated as “P-type first well111”, “P-type second well131”, “N-type well121”, “P-type source/drain junction regions127”, “N-type first source/drain junction regions117”, and “N-type second source/drain junction regions137”, respectively. As such, while the following description will be made on the assumption that the first conductivity means the P-type and the second conductivity means the N-type, they may be interchangeable, in accordance with embodiments.

In embodiments, an EEPROM may be divided into select transistor110, floating transistor120, and tunneling transistor130. A method of manufacturing the EEPROM in accordance with embodiments is illustrated inFIGS. 3 and 4.

First, P-type first well (PW)111may be formed on one side of the top of semiconductor substrate101. N-type well (NW)121may be formed at the front part of the other side of the top of the semiconductor substrate101. P-type second well (PW)131may be formed at the rear part of the other side of the top of the semiconductor substrate101. In embodiments, P-type first well (PW)111, N-type well (NW)121, and P-type second well (PW) may be formed next to each other in/on/over semiconductor substrate110, in that respective order. In embodiments, P-type first well111, N-type well121, and P-type second well131may be formed at the same depth.

STI region103may be formed in an upper portion of the semiconductor substrate101to define an active region and an inactive region. P-type first well111, N-type well121, and P-type second well131may be isolated from each other by STI region103. In embodiments, as illustrated inFIG. 4, only upper portions of P-type first well111, N-type well121, and P-type second well131may be isolated by STI regions103. In embodiments, P-type first well111, the N-type well121, and the P-type second well131may be fully separated and/or isolated from each other. P-type first well111may serve as a base layer for select transistor110. N-type well121may serves as a base layer for floating transistor120. P-type second well131may serves as a base layer for tunneling transistor130.

In accordance with embodiments, an insulation film and a polysilicon film may be sequentially formed on the top surface of semiconductor substrate101and then patterned, thereby forming first gate insulation film113, second gate instillation film123, and third gate insulation film133. First gate (SG)115may be formed on/over first gate insulation film113, which is on/over P-type first well111, in accordance with embodiments. Second gate125may be formed on/over second gate insulation film123, which is on/over N-type well121, in accordance with embodiments. Third gate135may be formed on/over third gate insulation film133, which is on/over P-type second well131, in accordance with embodiments. In embodiments, during these processes, first gate115, second gate125, and third gate135may be simultaneously formed by the same process, or sequentially formed by separate processes.

In embodiments, a salicide reaction preventing film may be formed before patterning insulation films and a polysilicon film. The salicide reaction preventing film, insulation films, and the polysilicon film may be patterned together to form first salicide blocking layer129on/over second gate125and second salicide blocking layer139on/over third gate135, in accordance with embodiments. First salicide blocking layer129and second salicide blocking layer139may prevent salicide from being formed on second gate125and third gate135, in accordance with embodiments.

In embodiments, an N-type source junction region may be formed by ion implantation in an upper portion of P-type first well111at one side of the first gate115and an N-type drain junction region may be formed in an upper portion of P-type first well111at the other side of first gate115, thereby forming N-type first source/drain junction regions117in contact with the first gate115, in accordance with embodiments. Similarly, a P-type source junction region may be formed by ion implantation in an upper portion of N-type well121at one side of second gate125and a P-type drain junction region is formed in an upper portion of N-type well121at the other side of second gate125, thereby forming P-type second source/drain junction regions127in contact with second gate125, in accordance with embodiments. Similarly, an N-type source junction region may be formed by ion implantation in an upper portion of P-type second well131on one side of third gate135and an N-type drain junction region may be formed in an upper portion of P-type second well131on the other side of third gate135, thereby forming N-type second source/drain junction regions137in contact with third gate135, in accordance with embodiments. In embodiments, N-type first source/drain junction regions117and N-type second source/drain junction regions137may be simultaneously formed by the same process or sequentially formed by separate processes.

In embodiments, select transistor110including first gate115and first source/drain junction regions117may be formed in the region of P-type first well111. In embodiments, floating transistor120including second gate125and P-type source/drain junction regions127may be formed in the region of N-type well121. In embodiments, tunneling transistor130including third gate135and N-type second source/drain junction regions137may be formed in the region of P-type second well131. Though not shown in detail, structures such as a lightly doped drain (LDD) region, a sidewall, a spacer, and the like may be further be selectively included in each transistor region, in accordance with embodiments.

In embodiments, as illustrated inFIG. 4, Fowler-Nordheim (F-N) tunneling may occur in the source junction region and the drain junction region, separately, as indicated by the “arrows”. In embodiments, a single gate EPROM may be modified to include tunneling transistor130in its structure, while maintaining a relatively small cell size without additional mask processes. In operation, an erasure voltage is applied to a single gate EPROM using tunneling transistor130, thereby enabling the erasing of electrons trapped in floating transistor120, in accordance with embodiments.

FIG. 5is a top plan view of an EEPROM in accordance with embodiments andFIG. 6is a cross-sectional view of the. EEPROM illustrated inFIG. 5. A cross-section of line VI-VI ofFIG. 5is illustrated on the left inFIG. 6and a cross-section of line VI′-VI′ ofFIG. 5is illustrated on the right inFIG. 6.FIGS. 5 and 6illustrate only a unit cell region of an EEPROM, in accordance with embodiments.

Embodiments illustrated inFIGS. 5 and 6have several similarities with the embodiments illustrated inFIGS. 3 and 4, corresponding with like reference numbers. A notable difference between the embodiments illustrated inFIGS. 5 and 6is that tunneling transistor130amay be modified based on modifications of third gate insulation film133a, a third gate135a, N-type second source/drain junction regions137a, and a second salicide blocking layer139aor none-salicide (NSAL) layer.

In embodiments, in the patterning process for the formation of third gate135a, the width W2of third gate135amay be patterned to be narrower than the width W1of second gate125. For example, in embodiments, the width W1of second gate125may be patterned to be between about 0.5 μm and 0.6 μm and the width W2of third gate135amay be patterned to be between about 0.16 μm and 0.2 μm.

In embodiments, when the width W2of third gate135ais patterned to be narrower than the width W1of second gate125, N-type second source/drain junction regions137amay be formed to be integrally joined by lateral diffusion. The width W2of third gate135amay be formed to be narrow so that lateral diffusion occurs during an ion implantation process for formation of N-type second source/drain junction regions137a, in accordance with embodiments. For example, in embodiments, an ion implantation process for formation of N-type second source/drain junction regions137amay be performed under the condition that an ion implantation angle with a tilt of about 25° to 45° is used, an ion implantation energy ranging from about 65 KeV to 100 KeV is used, and a dose amount ranges from about 5E12/cm2to 1E13/cm2.

In accordance with embodiments,FIG. 6illustrates F-N tunneling occurring at the connecting portion of source/drain junction regions, as indicated by the “arrow”. Embodiments illustrated inFIG. 6may be distinguished from embodiments illustrated inFIG. 4, asFIG. 4illustrates Fowler-Nordheim (F-N) tunneling occurring in the source junction region and the drain junction region separately, as indicated by the “arrow”. This may contribute to increases in the junction breakdown voltage and may reduce an erase time using a high bias.

FIG. 7is a top plan view of an EEPROM, in accordance with embodiments. Embodiments illustrated inFIG. 7have several similarities with the embodiments illustrated inFIG. 5, corresponding with like reference numbers. A notable difference between the embodiments illustrated inFIG. 7is that tunneling transistor130bis modified, in accordance with embodiments.

Tunneling transistor130bmay formed by adjusting the length at which an end portion of third gate (135aofFIG. 6) intersects edge portions of N-type second source/drain junction regions (137aofFIG. 6), so as to be reduced by a preset length L, in accordance with embodiments. For example, in embodiments, preset length L may be between about 0.16 μm and 0.2 μm. In embodiments, preset length L may be made substantially equal to the width of third gate135aofFIG. 6. In embodiments, by adjusting the length at which an end portion of third gate (135aofFIG. 6) intersects edge portions of N-type second source/drain junction regions (137aofFIG. 6) to be reduced, N-type second source/drain junction regions (137aofFIG. 6) may be integrally joined by lateral diffusion and may be formed more easily.

In embodiments, the single gate EPROM may maintain a relatively small cell size by changing its structure without additional mask processes and include a tunneling transistor. Single gate EPROM may be useable as a MTP EEPROM because electrical erasing may be enabled. In embodiments, a single gate structure EEPROM may have a relatively small cell size. In embodiments, a degree of freedom for adjusting an erasure voltage may be enhanced by adjusting the width of a gate constituting the tunneling transistor.

While embodiments have been shown and described, it will be understood by those skilled in the art that various changes and modification may be made without departing the scope of the embodiments as defined the following claims.