DETERMINING A LOCKED STATUS OF A CLOCK TRACKING CIRCUIT

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

FIELD

One or more examples relate, generally, to error detection, including phase and frequency error detection. One or more examples relate, generally, to determining a locked status of a clock tracking circuit.

BACKGROUND

Clock-tracking circuits such as phase locked loops and delay locked loops, are circuits utilized to generate a signal with a pre-determined relationship to a clock and other oscillating signal. An output signal of a clock-tracking circuit is locked to the phase and frequency of a reference signal. Clock-tracking circuits are utilized in a variety of operational contexts, including when two signals having known relationships are utilized to transmit information.

DETAILED DESCRIPTION

The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not mean that the structures or components are necessarily identical in size, composition, configuration, or any other property.

It will be readily understood that the components of the examples as generally described herein and illustrated in the drawing could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

Those of ordinary skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of presentation and description. It will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, wherein the bus may have a variety of bit widths and the present disclosure may be implemented on any number of data signals including a single data signal.

As used herein, any relational term, such as “over,” “under,” “on,” “underlying,” “upper,” “lower,” without limitation, is used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.

In this description the term “coupled” and derivatives thereof may be used to indicate that two elements co-operate or interact with each other. When an element is described as being “coupled” to another element, then the elements may be in direct physical or electrical contact or there may be intervening elements or layers present. In contrast, when an element is described as being “directly coupled” to another element, then there are no intervening elements or layers present. The term “connected” may be used in this description interchangeably with the term “coupled,” and has the same meaning unless expressly indicated otherwise or the context would indicate otherwise to a person having ordinary skill in the art.

As used herein, the term “assert” when used with “signal” means to set a signal to an active state. As used herein, the term “de-assert” when used with “signal” means to set a signal to an inactive or default state. For example, signals may be active high and inactive low, or active low and inactive high.

A “clock signal” or just a “clock,” is a signal that oscillates between two discrete state—a low state and a high state—in a reliably predictable manner. The change from a low state to a high state or a high state to a low state is referred to as an “edge.” The type or direction of a change, low state to high state or high state to low state, is referred to as the “polarity” of the edge. A change from low state to high state is called a “positive polarity” or a “rising edge.” A change from high state to low state is called a “negative polarity” or a “falling edge.” One or more circuits may be responsive to a rising edge or falling edge of a clock, as a non-limiting example, to coordinate acts.

A clock tracking circuit, such as a phase locked loop (PLL), without limitation, generates an output signal exhibiting a phase, frequency, or both having a predetermined relationship to a phase or frequency of a reference signal. Causing and maintaining such a predetermined relationship between the phase or frequency of an output signal and a reference signal is referred to herein as “tracking.” The predetermined relationship may be that the output signal and reference signal are in-phase or within some predetermined phase difference. The predetermined relationship may be that the frequency of the output signal is the same as, or a multiple of, a frequency of the reference signal. As a non-limiting example, the frequency of the output signal may be an integer or fractional multiple of the frequency of the reference signal, such as 1/200, 1/10, 10, or 200 times the frequency of the reference signal.

A typical clock tracking circuit includes an electronic oscillator that the clock tracking circuit controls to generate an output signal that tracks the reference signal. An electronic oscillator may include one or more banks of control elements (e.g., capacitors, inductors, delay circuits, without limitation) that are voltage controlled, current controlled, digitally controlled, or a combination or sub-combination thereof. Enabling and disabling respective control elements changes the capacitance, inductance, or delay, as the case may be, of the electronic oscillator in a predictable manner, which changes the output phase and frequency of the electronic oscillator in a predictable manner.

An electronic oscillator may include multiple inputs for controlling (enabling/disabling) various banks of control elements and, accordingly, governing the phase and frequency of an output signal. Non-limiting examples of electronic oscillators include a voltage controlled oscillator (VCO) that generates an output signal exhibiting a phase or frequency governed by a voltage of a control signal, a current controlled oscillator (CCO) that generates an output signal exhibiting a phase or frequency governed by a current of a control signal, a digitally controlled oscillator (DCO) that generates an output signal exhibiting a phase or frequency governed, at least in part, by a value of a control code, and combinations/subcombinations thereof.

When a clock tracking circuit reliably tracks an output signal to a reference signal, that is referred to as “locked” or being in a “locked state.” Being locked is also referred to as a “NULL condition” ‘because the phase error is zero or suitably small or “NULL.” When locked, if the phase or frequency of a reference signal changes, the clock tracking circuit correspondingly adjusts the phase or frequency of the output signal to maintain the predetermined relationship. Similarly, when locked, if the phase or frequency of the output signal changes, the clock tracking circuit correspondingly adjusts the phase or frequency of the output signal to maintain the predetermined relationship. An internal signal is generated at the clock tracking circuit to indicate locked state. Such a locked state signal may be utilized, as a non-limiting example, to enable output drivers and to initiate other clock tracking calibration functions.

The threshold for determining a locked state (i.e., the thresholds for determining that an output signal is operating in a stable defined range, without limitation) depends, as a non-limiting example, on specific operating conditions. For example, some applications may tolerate less accuracy (i.e., greater difference) between the target frequency and the output frequency, while others will not tolerate it.

Sometimes analog control signals to the electronic oscillator (e.g., to an analog proportional input of the electronic oscillator, without limitation) are used to determine a locked status. Whether or not the output signal is operating in a stable, defined range may be inferred based on the control signals. The inventors of this disclosure appreciate that such an approach requires analog references and comparators targeted at the clock tracking circuits specific operating points that define its stable, defined range, and analog components require a lot of real-estate compared to digital components. Further, while analog control signals may be generated based on phase error, they do not directly include phase error information. Locked status is either deduced, which may be imprecise or wholly inaccurate, or determined using control signals, which are an imperfect representation of the phase error, in either case locked status determinations are subject to error.

One or more examples relate to a locked status detector for a clock tracking circuit. In some examples, the locked status detector determines locked status at least partially based on the reference clock and feedback clock, an UP signal and DOWN signal generated by a binary error detector (e.g., by a phase-frequency detector, without limitation), or both.

In one or more examples, the locked status detector includes a phase detector with a phase threshold and a status signal. The phase threshold is settable. The phase detector compares the phase difference between two input signals (e.g., a reference clock and a feedback clock, without limitation) to the phase threshold. If the phase difference between the two input signals is greater than or equal to the phase threshold, the phase detector sets its output to a first value. If the phase difference between the two input signals is less than the phase threshold the phase detector sets its status signal to a second value, the second value different than the first value. The value of the status signal of the phase detector indicates the relationship between phase difference and phase threshold. The first value indicates the phase difference between the two inputs signals is greater than or equal to the phase threshold and that one of the input signals (e.g., a feedback clock, without limitation) is operating outside the phase detector's set dead-zone. The second value indicates the phase difference between the two inputs signals is less than the phase threshold and that one of the input signals (e.g., a feedback clock, without limitation) is operating within the phase detector's set dead-zone.

The term “dead-zone” typically refers to an operating region in which a phase detector (or the phase detector output—the error signal) exhibits zero or near zero gain (e.g., here, gain refers to the magnitude of the error signal) because the phase difference between two input signals is zero or near zero. In one or more examples, a phase detector has a “set dead-zone.” The set dead-zone is set via the phase threshold. In one or more examples, a phase error region associated with a set dead-zone may be the same or different than a phase error region associated with an actual dead-zone of the phase error detector.

The status signal may change from indicating outside to indicating within the dead-zone in response to a changing phase difference between input signals. The status signal may change from indicating within to indicating outside the set dead-zone in response to a changing phase difference between input signals. In the context of locked status detection, the set dead-zone corresponds to a predetermined range of phase error pre-associated with a locked state.

The phase threshold of the phase detector may be settable (e.g., programmable, configurable, or otherwise settable, without limitation), and so the phase detector is adaptive or adaptable, as the case may be, to operating conditions at least partially based on the phase threshold. In one or more examples, the phase threshold may be pre-set or set in real-time.

In one or more examples, the status signal of the phase detector is sampled and the status signal samples are decoded to determine the locked status. In one or more examples, a digital discriminator discriminates between steady-state phase error information and transitory phase error information in the status signal. Steady-state phase error is the phase error present when a clock tracking circuit is locked. Transitory phase error is phase error that is temporary in nature and may or may not be present at any given time. Generally speaking, information about steady-state phase error should be used to determine locked status, while information about transitory phase error should be reduced or eliminated in such a determination.

In one or more examples, the digital discriminator is a digital filter that keeps or passes digital signals (e.g., in the status signal, without limitation) that are indicative of steady-state phase error and blocks or discards digital signals (e.g., in the status signal, without limitation) that are indicative of transitory phase error. In one or more examples, the digital discriminator is a state-machine that implements a pattern-matcher that does bit-wise comparison of a digital signal and predetermined patterns indicative of the locked status of the phase detector. In one or more examples, the digital discriminator is an accumulator and a comparator, and the accumulator accumulates the state of the status signal and the comparator detects when the accumulated state is above a predetermined threshold indicative of a steady-state phase error. The output of the comparator is used as the locked status signal.

A status signal sample is a value of the status signal at a specific intervals—i.e., a discrete time, discrete value signal. Notably, the status signal of the phase detector may be a digital signal, which is a discrete time, discrete value signal. So, the status signal may be a series of samples received, as a non-limiting example, in a shift-register. In one or more examples, a sample rate may be set to ensure a set of samples obtained is representative of the phase detector's state. Generally speaking, the higher the sample rate, the greater the number of status signal samples, and the more representative of the phase detector's state.

FIG.1is a block diagram of an apparatus100for determining a locked status of a clock tracking circuit, in accordance with one or more examples. Apparatus100may also be referred to as a “locked status detector100.”

Apparatus100includes a phase detector102, a digital discriminator106, and a logic circuit112.

Apparatus100receives a reference clock118, a feedback clock120, a phase threshold116, and generates a locked status signal110at least partially responsive thereto. Feedback clock120is generated by a clock tracking circuit to track the reference clock118. Reference clock118represents the target frequency and phase that the clock tracking circuit tracks. In one or more examples, feedback clock120may be derived from an output clock, generated by the clock tracking circuit to track reference clock118and fed back, optionally through a frequency divider, for comparison with the reference clock118. Feedback clock120may be the same as the output clock generated by the clock tracking circuit (e.g., the output clock is fed directly to an input of phase detector102, without limitation) or may be indicative of one or more of the phase, frequency, or pulse width of output clock. In the specific non-limiting examples depicted byFIG.1, reference clock118and feedback clock120are fed directly to inputs of phase detector102. In one or more examples, one or more signals indicative of a phase relationship between reference clock118and feedback clock120may be fed to one or more inputs of phase detector102, such as the output of a binary phase detector (such as a bang-bang phase detector, without limitation), the output of a digital or analog sub-sampling phase detector, the output of a digital or analog sampling phase detector, without limitation.

Phase threshold116is a value, or a range of values, predetermined to represent the threshold of a set dead-zone at phase threshold116, and in the context of locked status detection, it also represents an amount of phase error pre-associated with a locked state.

Phase threshold116is utilized by phase detector102to determine a state of the phase error between reference clock118and feedback clock120. If the phase error is greater than or equal to phase threshold116that indicates the phase error is outside the range associated with a locked state, and if the phase error is less than phase threshold116that indicates the phase error is within the rage associated with a locked state. As a non-limiting example, if phase threshold116is set (e.g., by a logic circuit or user, without limitation) to ±5 degrees, then as long as the phase difference between feedback clock120and reference clock118is within +5 to −5 degrees, apparatus100considers the phase-error within the range associated with a locked state.

Locked status signal110indicates the locked status of a clock tracking circuit, i.e., indicates whether or not the clock tracking circuit is in a locked state. In one or more examples, a first value of locked status signal110indicates the clock tracking circuit is not in a locked state, and a second value of locked status signal110indicates the clock tracking circuit is in the locked state. The first value and the second value of locked status signal110are different.

Phase detector102receives reference clock118, feedback clock120and phase threshold116and generates status signal104at least partially responsive thereto. Status signal104indicates whether or not the feedback clock120is operating in the set dead-zone of phase detector102, as discussed below.

Phase detector102determines whether a phase difference between reference clock118and feedback clock120and is less than phase threshold116. If phase detector102determines that the phase difference is less than phase threshold116, then feedback clock120is determined to be operating within the set dead-zone and phase detector102sets status signal104to a value that indicates that feedback clock120is operating within the set dead-zone of phase detector102. If phase detector102determines that the phase difference is greater than or equal to phase threshold116, then feedback clock120is determined to be operating outside the set dead-zone and phase detector102sets status signal104to a value that indicates that feedback clock120is operating outside the set dead-zone of phase detector102. Since feedback clock120is based on the output clock of the clock tracking circuit, a determination whether or not feedback clock120is operating within the set dead-zone is also a determination whether or not the output signal is operating within the set dead-zone.

Phase detector102may change the value of status signal104from a value indicating outside the set dead-zone to a value indicating within the set dead-zone in response to a changing phase difference between reference clock118and feedback clock120. Phase detector102may change the value of status signal104from a value indicating within the set dead-zone to a value indicating outside the set dead-zone in response to a changing phase difference between reference clock118and feedback clock120. Thus, the state of status signal104may change over time at least partially responsive to changes in the phase difference between reference clock118and feedback clock120.

A value of phase threshold116may be predetermined at least partially based on an acceptable amount of phase difference for determining a locked state. The value of status signal104is at least partially based on whether or not a phase difference of reference clock118and feedback clock120is less than phase threshold116, so status signal104is indicative of a locked status of the clock tracking circuit. Stated another way, information about the phase difference between feedback clock120and reference clock118and locked status of a clock tracking circuit is included in status signal104. Status signal104includes information about the steady-state phase error between feedback clock120and reference clock118, and the locked status of the clock tracking circuit may be determined from the steady-state phase error information. Thus, in one or more examples, a state of status signal104may be decoded to determine a locked status of the clock tracking circuit, as described below.

Digital discriminator106receives status signal104and processes status signal104to produce samples108of status signal104. Digital discriminator106distinguishes between steady-state phase error information and transitory phase error information in the status signal104. Digital discriminator106stores samples108of status signal104that include the steady-state phase information.

Logic circuit112processes samples108to determine patterns indicative of locked status in the state information about phase detector102included in set of samples108. Logic circuit112determines the locked status of the clock tracking circuit of reference clock118and feedback clock120. If logic circuit112determines that the locked status is a locked state then it sets locked status signal110to a value indicative of locked state. If logic circuit112determines that the locked status is not locked state then it sets locked status signal110to a value indicative of not being in a locked state.

The status signal104and status signal samples108include steady-state phase error information that logic circuit112uses to determine (e.g., infer, without limitation) the locked status of the clock tracking circuit. Phase detector102changes the state of status signal104in a predictable manner so that the state information may be utilized to determine locked status.

FIG.2is a block diagram depicting an apparatus200that is an example of a phase detector, in accordance with one or more examples. Apparatus200may also be referred to herein as “phase detector200.” Apparatus200is a non-limiting example of phase detector102ofFIG.1.

Generally speaking, if both input signals exhibit a transition from a low state to high state (rising edge) within a predetermined range then apparatus100asserts threshold detected signal212, and if both input signals do not exhibit a rising edge within the predetermined range then apparatus100de-asserts threshold detected signal212. Apparatus200performs a binary check, either the phase relationship is within the predetermined range, or it is not.

In one or more examples, threshold detected signal212may be used as status signal104. When the rising edge of both signal have arrived the phase detector re-arms for the next comparison. Stated another way, apparatus200sets threshold detected signal212to an asserted (high) state in response to determining that a time difference between an occurrence of a rising edge of first signal214and an occurrence of a rising edge of second signal216is less than phase threshold116, and sets threshold detected signal212to a de-asserted (low) state in response to determining that the time difference between an occurrence of the rising edge of first signal214and an occurrence of the rising edge of second signal216is greater than phase threshold116.

Apparatus200includes a first flip-flop202, a second flip-flop204, a third flip-flop220, a fourth flip-flop218, a first delay circuit208, a second delay circuit222, a NAND gate206, and a NOR gate210.

First flip-flop202, second flip-flop204, third flip-flop220, and fourth flip-flop218are edge-triggered flip-flops, which is a type of flip-flop that responds to the change (or “edge”) of its clock input rather than the level of the clock input. Each flip-flop202,204,220, and224has a Data (D) input, a clock (CLK) input and an output (Q). The state at data (D) input is captured and transferred to the output (Q) in response to the state at clock (CLK) input experiencing a specified edge transition (either rising or falling, but in this example a rising edge). When the clock (CLK) input experiences an edge transition other than the specified edge transition the state at data (D) input is not captured or transferred, and the state at output (Q) is the state at the data (D) input the last time a specified edge transition occurred at the clock (CLK) input.

In one or more examples, the flip-flops may have a single output, Q, capable of exhibiting at least two states, or, alternatively, two separate outputs, Q and Q′, that respectively represent one of the two states.

NAND gate206is an electronic logic gate that produces an output which is false only when all of its inputs are true. In other words, if any of its inputs are in a low state, then the output will be high state. NOR gate210is an electronic logic gate that produces an output which is true only when all of its inputs are false. In other words, if any of its inputs are true, then the output will be false.

First delay circuit208and second delay circuit222are delay circuits that introduce a respective predetermined amount of time delay to the propagation of a signal from its input to its output. In one or more examples, the respective predetermined amount of time delay introduced is equal to, or at least partially based on, phase threshold116. In one or more examples, first delay circuit208and second delay circuit are programmable, wherein the amount of delay varies partially based on phase threshold116.

Respective data (D) inputs of first flip-flop202and second flip-flop204are coupled to a supply voltage to set the data (D) inputs to a high state. The clock (CLK) input of first flip-flop202is coupled to receive a first signal214and the clock (CLK) input of second flip-flop204is coupled to receive a second signal216. In one or more examples, one of first signal214or second signal216is set as the reference clock118and the other one of first signal214or second signal216is set as the feedback clock120.

In one or more examples, first signal214and second signal216may be set by signals that are indicative of the phase relationship between reference clock118and feedback clock120, such as UP and DOWN signals generated by a phase/frequency detector, such as a bang-bang phase-frequency detector, without limitation. As long as the timing of the rising edges of first signal214and second signal216includes the phase information about the signals of interest (e.g., reference clock118and feedback clock120, without limitation) they can be utilized by apparatus200to determine if a phase difference is within the phase-error threshold.

The output (Q) of first flip-flop202is coupled to the data (D) input of third flip-flop220, an input of first delay circuit208, and an input of NAND gate206. The output (Q) of second flip-flop204is coupled to the data (D) input of fourth flip-flop218, an input of second delay circuit222, and the other input of NAND gate206. The output of NAND gate206is coupled to respective reset (R) inputs of first flip-flop202and second flip-flop204. The output of first delay circuit208is coupled to the clock (CLK) input of third flip-flop220and the output of second delay circuit222is coupled to the clock (CLK) input of fourth flip-flop218. The Q output of third flip-flop220is coupled to a first input of NOR gate210and the Q output of fourth flip-flop218is coupled to a second output of NOR gate210. The output of NOR gate210represents threshold detected signal212.

The outputs (Q) of first flip-flop202and second flip-flop204are received at NAND gate206. If both of the outputs (Q) of first flip-flop202and second flip-flop204are high state, then the output of NAND gate206is set to a low state, which low state at the output of NAND gate206resets first flip-flop202and second flip-flop204because their respective reset (R) inputs are active low. When first flip-flop202and second flip-flop204are reset, their outputs (Q) are forced to low state (i.e., low state at the reset (R) input overrides the data (D) input and clock (CLK) input and forces output (Q) to the low state).

When either or both of the outputs (Q) of first flip-flop202and second flip-flop204are in a low state, the output of NAND gate206is set to high state. The reset (R) inputs of first flip-flop202and second flip-flop204are active low, so when high state is received at respective reset (R) inputs, the first flip-flop202and second flip-flop204operate normally and do not reset, responding only to data (D) input and clock (clk) input.

Accordingly, if both of the outputs (Q) of first flip-flop202and second flip-flop204are in the high state, then NAND gate206resets both flip-flops causing respective outputs (Q) of first flip-flop202and second flip-flop204to be in a low state.

Assume for purposes of example, that all of first flip-flop202, second flip-flop204, third flip-flop220and fourth flip-flop218are initialized to output a low state.

If the output (Q) of first flip-flop202changes to high state, responsive to a rising edge of first signal214, and the output (Q) of second flip-flop204is in the low state, since the rising edge of second signal216has not yet occurred, the high state is received at the data (D) input of third flip-flop220and the input of first delay circuit208, and the received high state is propagated through first delay circuit208. The low state at the output (Q) of second flip-flop204is received at the data (D) input of fourth flip-flop218and the input of second delay circuit222, and the received low state is propagated through second delay circuit222.

After the predetermined delay time of first delay circuit208and second delay circuit222, i.e., the delay set by phase threshold116, the delayed high state (i.e., the output (Q) of first flip-flop202delayed by first delay circuit208) is received at the clock (CLK) input of third flip-flop220, so clock (CLK) input of third flip-flop220sees a change from low state to high state (rising edge) and triggers, thereby passing the high state received at the data (D) input of third flip-flop220to the Q output of third flip-flop220. Also after the predetermined delay time, the delayed low state (i.e., the delayed output (Q) of second flip-flop204) is receive at the clock (CLK) input of fourth flip-flop218, and fourth flip-flop218does not see a change from low state to high state and does not trigger. The output of third flip-flop220is a high state, and the output of fourth flip-flop218is the last value at data (D) input when it was triggered, in this example, a low state. The output of NOR gate210, threshold detected signal212, is thus low since the Q output of third flip-flop220is high. As indicated above, threshold detected signal212in the low state is indicative that the time difference between an occurrence of the rising edge of first signal214and an occurrence of the rising edge of second signal216is greater than phase threshold116.

If second signal216exhibits a rising edge before the predetermined time delay, second flip-flop204is triggered setting the Q output of second flip-flop204to a high state. Since the Q outputs of first flip-flop202and second flip-flop204are in the high state, NAND gate206resets first flip-flop202and second flip-flop204so that the Q outputs of first flip-flop202and second flip-flop204fall to the low state. After the predetermined delay time of first delay circuit208, the delayed high state (i.e., the output (Q) of first flip-flop202delayed by first delay circuit208) is received at the clock (CLK) input of third flip-flop220, so clock (CLK) input of third flip-flop220sees a change from low state to high state (rising edge) and triggers, thereby passing the low state received at the data (D) input of third flip-flop220to the Q output of third flip-flop220. Similarly, after the predetermined delay time of second delay circuit222, the delayed high state (i.e., the output (Q) of second flip-flop204delayed by second delay circuit222) is received at the clock (CLK) input of fourth flip-flop218, so clock (CLK) input of fourth flip-flop218sees a change from low state to high state (rising edge) and triggers, thereby passing the low state received at the data (D) input of fourth flip-flop218to the Q output of fourth flip-flop218. The output of NOR gate210, threshold detected signal212, is thus high since the Q output of both third flip-flop220and fourth flip-flop218are low.

While the above has been described in an example of the rising edge of first signal214preceding the rising edge of second signal216, those skilled in the art will recognize that the same results occur when the rising edge of second signal216precedes the rising edge of first signal214.

If first signal214and second signal216both exhibit a rising edge within phase threshold116(i.e., the time between when first signal214exhibits a rising edge and second signal216exhibits a rising edge is less than phase threshold116) then apparatus200sets threshold detected signal212to low state, and if both first signal214and second signal216do not exhibit a falling edge within phase threshold116(i.e., the time between when first signal214exhibits a rising edge and second signal216exhibits a rising edge is greater than phase threshold116) than apparatus200sets threshold detected signal212to high state. In the specific non-limiting example depicted byFIG.2, asserting threshold detected signal212is setting it to low state, and de-asserting threshold detected signal212is setting it to high state, but use of other states does not exceed the scope of this disclosure.

FIG.3is a block diagram of an apparatus300for discriminating between steady-state and transitory phase error in a status signal of a phase detector and optionally determining locked status based thereon, in accordance with one or more examples. Apparatus300is a non-limiting example of a digital discriminator106and logic circuit112ofFIG.1.

Digital filter302filters the status signal104of phase detector102to block status signal that is indicative of transitory phase error and pass status signal that is indicative of steady-state phase error. By way of non-limiting example, digital filter302may be a digital low-pass filter that allows steady-state phase error signals to pass while attenuating high-frequency transitory phase error signals. Non-limiting examples of a digital low-pass filter include a moving average filter, a finite impulse response (FIR) filter, a digital loop filter, and adaptive filters.

Register304receives and stores the status signal samples provided by digital filter302. The status signal samples include the steady-state phase error information that may be used to determine the locked status of the clock tracking circuit.

Logic circuit112monitors the status signal samples stored at the register304, determines locked status information from the status signal samples, determines the locked status of the clock tracking circuit at least partially based on the status information, and sets locked status signal110to indicate the determined locked status.

FIG.4is a block diagram of an apparatus400for discriminating between steady-state and transitory phase error in a status signal of a phase detector and optionally determining locked status based thereon, in accordance with one or more examples. Apparatus400is a non-limiting example of a digital discriminator106and logic circuit112ofFIG.1.

Accumulation register402accumulates states of status signal104. The accumulated value408(“acc value408”) stored at accumulation register402, which represents the integral of the states of status signal104, is provided to comparator404. The integral of the status of status signal104is the steady-state phase error information.

Comparator404is a digital comparator that determines the relationship between acc value408and a threshold value, and sets respective outputs of comparator404to indicate the determined relationship. In one or more examples, the relationships may be whether or not the accumulated value is less than or greater than a predetermined threshold. If it is greater than the predetermined threshold that indicates the locked status of the clock tracking circuit is a locked state, and if it is less than the predetermined threshold that indicates the locked status of the clock tracking circuit is not locked state. Logic circuit112may set locked status signal110to indicate that locked status indicated by comparator404. Alternatively, in one or more examples, the output of comparator404may be provided as locked status signal110.

In one or more examples, the number of samples generated is at least partially based on a sampling rate. In one or more examples, the sampling rate at apparatus400may be set to cause a suitable resolution for the digital discriminator106to process the status signal104and maintain the steady-state phase error information. A suitable resolution is one that ensures a set of status signal samples is representative of phase error information. Generally speaking, the higher the sample rate, the greater the number of status signal samples, and the higher the resolution.

In some cases, a processing rate may be set at phase detector102as discussed below, to increase the resolution of status signal104. Status signal104may be a digital signal, which is a discrete time, discrete value signal. Increasing the processing rate phase detector102increases the frequency with which it updates status signal104, One way to increase the processing rate is to increase the clock rate of feedback clock120and reference clock118.

FIG.5is a block diagram depicting an apparatus500for setting a sampling rate, in accordance with one or more examples. Apparatus500includes phase detector102and sampling clock divider502.

Sampling clock divider502receives feedback clock120, reference clock118, and sampling rate504, frequency divides feedback clock120and reference clock118by an amount that corresponds to sampling rate504, and produces divided reference clock506and divided feedback clock508. Clock rates of divided reference clocks506and divided feedback clock508may be greater than or less than of reference clock118and feedback clock120, based on, for example, sampling rate504.

Sampling rate504may be a value that represents, as a non-limiting example, a number of clock cycles per sampling interval, a number of samples per unit interval, or a divisor. Sampling rate504may be pre-set by a user or logic circuit.

Sampling logic circuit602receives the sampling rate608, determines whether to perform up-sampling based on the sampling rate608, i.e., to increase the number of samples based on interpolation, or down-sampling, reduce the number of samples based on decimation, generates decimation rate614for decimator606or interpolation rate616for interpolator604at least partially based on the determination, and generates selection signal610to selects the output of decimator606or interpolator604via multiplexer612as the status signal samples provided to digital discriminator106. If sampling logic circuit602determines, based on the sampling rate608, to perform up-sampling, sampling logic circuit602determines a value for a target interpolation rate based on sampling rate608, and sets interpolation rate616based on the determined value. In one or more examples, when up-sampling, sampling logic circuit602may set decimation rate614to a value indicative of no decimation. If sampling logic circuit602determines, based on sampling rate608, to perform down-sampling, sampling logic circuit602determines a value for target decimation rate based on sampling rate608and sets decimation rate614based on the determined value. In one or more examples, when down-sampling, sampling logic circuit602may set interpolation rate616to value indicative of no interpolation. Decimator606receives status signal104and decimation rate614, selects every Nth value of status signal104(where the Nth value is at least partially based on the decimation rate614), and provides the selected values as the status signal samples. As a non-limiting example, decimator606may include a shift register to hold and move bits of status signal104and a logic circuit to select which values of status signal104to keep (and conversely, which values to discard). Decimator606keeps the values of status signal104that the logic circuit selects to keep and discards the rest of the values.

Interpolator604receives status signal104and interpolation rate616, up samples values for status signal104at least partially based on interpolation rate616, and provides the up sampled values as the status signal samples. As a non-limiting example, interpolator604may include a shift register hold and move bits of original values of status signal104and thereby insert gaps (e.g., respective gaps may comprise one or more zeros, without limitation) between the bits of original values of status signal104, and a logic circuit to interpolate values between the original values of status signal104and replace the zeros with the interpolated values (fill the gaps).

Sometimes it may be advantageous for the sampling clock or signal that sets the sampling rate of status signal104to be at least partially based on the reference clock118, feedback clock120, or the phase difference therebetween, to increase the amount of steady-state phase information in status signal104or samples thereof.

Sometimes it may be advantageous for the sampling clock or signal that sets the sampling rate of status signal104to be at least partially based on the reference clock118, feedback clock120, or the phase difference therebetween, to increase the amount of steady-state phase information in status signal104or samples thereof.

FIG.7is a block diagram depicting an apparatus700for generating a sampling clock for sampling a status signal of a phase detector, in accordance with one or more examples. Apparatus300is a non-limiting example of clock source for optional sampling clock306or optional sampling clock410,

Apparatus700includes sampling clock divider704and NAND gate708. Sampling clock divider704receives produced clk710and sampling rate706, divides produced clk710at least partially based on sampling rate706, and generates sampling clock702. NAND gate708generates produced clk710at least partially based on a reference clock118and feedback clock120.

FIG.8is a flow diagram depicting a process800to determine a locked status of a clock tracking circuit, in accordance with one or more examples.

Although the example process800depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process800. In other examples, different components of an example device or system that implements the process800may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, process800includes setting a status signal of a phase detector, wherein the status signal of the phase detector is set at least partially based on an amount of phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock at operation802. In one or more examples, the status signal may be set directly based on the feedback clock and reference clock, or directly based on one or more signals indicative of the phase difference between the reference clock and the feedback clock such as UP signals and DOWN signals generated by a phase-frequency detector.

According to one or more examples, process800includes generating a signal indicative of a locked status of the clock tracking circuit at least partially based on the status signal of the phase detector at operation804.

FIG.9is a flow diagram depicting a process900to set a status signal of a phase detector, in accordance with one or more examples. Some or a totality of operations of process900may be performed, as a non-limiting example, by apparatus100, phase detector102, or apparatus200.

Although the example process900depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process900. In other examples, different components of an example device or system that implements the process900may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, process900includes determining whether or not a phase relationship between a reference clock and a feedback clock falls within a predetermined range at operation902. In one or more examples, the phase relationship is a phase difference between the reference clock and the feedback clock. In one or more examples, the phase threshold represents a boundary condition for the predetermined range. At operation902, process900examines whether the phase relationship between the reference clock and the feedback clock falls within a predetermined range utilizing the phase threshold, and need not measure the exact phase difference.

According to one or more examples, process900includes setting the status signal of the phase detector at least partially based on the determination at operation904. In one or more examples, operation902is a binary check, either the phase relationship is within the phase threshold or it is not. Setting the status signal may include setting it a value indicative of the result of the binary check of operation902.

FIG.10is a flow diagram depicting a process1000to set the status signal of the phase detector, in accordance with one or more examples.

Although the example process1000depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process1000. In other examples, different components of an example device or system that implements the process1000may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, process1000includes setting the status signal of the phase detector to a first value at least partially responsive to determining that a determined amount of difference is greater than a phase threshold at operation1002.

According to one or more examples, process1000includes setting the status signal of the phase detector to a second value at least partially responsive to determining that a determined amount of difference is equal to or less than the phase threshold, wherein the second value is different than the first value at operation1004.

FIG.11is a flow diagram depicting a process1100for setting a status signal to indicate a status of phase difference between a reference clock and a feedback clock, in accordance with one or more examples. Some or a totality of operations of process2200may be performed by, as a non-limiting example, by apparatus1600or phase error detector1604.

Although the example process1100depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process1100. In other examples, different components of an example device or system that implements the process1100may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the process1100includes detecting occurrences of like respective edges of the reference clock and the feedback clock at operation1102.

According to one or more examples, the process1100includes setting the status signal to indicate whether or not the detected occurrences of like respective edges were within a predetermined range at operation1104.

According to one or more examples, the process1100includes optionally setting the status signal to the first value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is less than the phase threshold at operation1106.

According to one or more examples, the process1100includes optionally setting the status signal to the second value responsive to the time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is greater than or equal to the phase threshold at operation1108.

FIG.12is a flow diagram depicting a process1200to determine the locked status of a clock tracking circuit at least partially based on a status signal of a phase detector, in accordance with one or more examples.

Although the example routine depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the routine. In other examples, different components of an example device or system that implements the routine may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, process1200includes obtaining samples of a status signal of a phase detector, the status of the phase detector is set at least partially based on whether or not a phase relationship between a reference clock and a feedback clock falls within a predetermined range at operation1202. In one or more examples, process1200may obtain samples by processing (e.g., via digital discriminator106, without limitation) the status signal in a manner that passes or keeps steady-state phase error information and discards or blocks transitory phase error information.

According to one or more examples, process1200includes optionally obtaining samples includes decimating the status signal at operation1204.

According to one or more examples, process1200includes optionally obtaining samples includes interpolating values based on the status signal at operation1206.

Optional operation1206and optional operation1208, some or a totality of operations for decimation, interpolation, or both may be performed, as a non-limiting example, by apparatus600. In one or more examples, a decimation rate or interpolation rate may be set in response to or based on a sampling rate.

According to one or more examples, process1200includes decoding status information from samples of the status signal of phase detector at operation1208.

According to one or more examples, process1200includes determining the locked status of the clock tracking circuit at least partially based on the decoded status information at operation1210.

According to one or more examples, process1200includes optionally set a signal indicative of a locked status of a clock tracking circuit to the determined locked status at operation1212.

FIG.13is a block diagram depicting an apparatus1300to track a clock (and may also be referred to herein as a “clock tracking circuit1300”), that offers locked status determination in accordance with one or more examples. In one or more examples, clock tracking circuit1300may be a hybrid PLL or digital PLL.

Clock tracking circuit1300operates, generally, to generate an output clock signal1308phase-locked and frequency-locked to reference clock1314. Clock tracking circuit1300includes an error detector1302, a controller1304, a controlled-oscillator1306, and a locked status detector1318.

Locked status detector1318determines the locked status of clock tracking circuit1300and generates locked status signal1322to indicate the determined locked status. In one or more examples, locked status detectors1318may be or include an apparatus100or apparatus300.

In one or more examples, locked status detector1318may determine locked status of clock tracking circuit1300based on reference clock1314and feedback clock signal1316, or, alternatively, the error signal generated by error detector1302.FIG.13depicts a specific non-limiting example where error detector1302generates two error signal that include magnitude and direction information about the phase difference between set of samples reference clock1314and feedback clock signal1316and indirectly about the frequency difference between reference clock1314and feedback clock signal1316. This disclosure is not limited to determining locked state based on error signals in those cases where the error signals are UP and DOWN signals. Any error signal where the timing of falling edges includes phase information about signals of interest (e.g., reference clock118and feedback clock120, without limitation) may be utilized. In cases where, as non-limiting examples, the error signals generated by error detector1302are not suitable for determining locked status of a clock tracking circuit1300or where operating conditions might otherwise dictate, reference clock1314and feedback clock signal1316may be utilized to determined locked status of clock tracking circuit1300.

Error detector1302receives reference clock1314and feedback clock signal1316and generates error signals including UP1312and DOWN1320at least partially responsive thereto. More specifically, error detector1302generates an error signal that is proportional to the phase difference between two input signals to error detector1302. More specifically, the magnitude and direction of the error signals are proportional to the phase difference between the input signals. If the phase and frequency of the two inputs signals is substantially the same, the magnitude and direction information in UP1312and DOWN1320will be zero, indicating that the phase and frequency of the two signals are the same. If there is a phase or frequency difference between the two input signals, then the magnitude and direction information in UP1312or DOWN1320will be non-zero and proportional to the difference between the phase (and indirectly, the frequency) of the two input signals.

In one or more examples, error detector1302may be a binary phase detector that generates error detector1302as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. Error detector1302generates the UP signal and the DOWN signal as a series of pulses, where pulses on respective ones of the UP signal and DOWN signal indicate the magnitude and direction of error. The one of the UP signal and the DOWN signal that first exhibits a pulse indicates which one of the two input-selected signals leads the other; and, conversely, which one of the two input-selected signals lags the other. The magnitude of the error signal is represented by the pulse width of a pulse generated in the UP signal or DOWN signal. A larger pulse width indicating a larger phase difference between the two input signals, and a smaller pulse width indicating a smaller phase difference. One of the inputs of error detector1302is preset as the reference input that is led, lagged, or locked to, and the other one of the inputs of error detector1302is preset as the feedback (or “controlled”) input that is leading, lagging, or locked on. As a non-limiting example, in a clock-tracking circuit the reference signal is provided to the reference input, and the output signal (or derivative thereof) is provided to the feedback input.

Reference clock1314may be generated by any suitable clock source for a given operational context. Feedback clock signal1316may be the same as output clock signal1308generated by clock tracking circuit1300(e.g., output clock signal1308is provided directly to an input of error detector1302, without limitation) or may be a clock signal indicative of the phase and frequency of output clock signal1308. For example, the phase and frequency of feedback clock signal1316may be the same or different than output clock signal1308, but in either case, is relatable back to the phase and frequency of output clock signal1308. In one or more examples, feedback clock signal1316may be a frequency divided version of output clock signal1308(e.g., via a frequency divider or buffer, without limitation). In one or more, error detector1302may be any suitable error detector for producing a digital signal that represents the phase error between reference clock1314and feedback clock signal1316, as a non-limiting example, a bang-bang phase detector, without limitation.

Digitally controlled-oscillator1306is an electronic oscillator for generating output clock signal1308at least partially in response to control signal1310, which control signal1310are a digital control signal or digital control code. The control signal1310is fed to an input of digitally controlled-oscillator1306.

Controller1304provides control signal1310to digitally controlled-oscillator1306to adjust output clock signal1308. In one or more examples, controller1304may include circuits (analog circuits, digital circuits, or both) to provide a proportional control path and an integral control path for control of digitally controlled-oscillator1306.

A typical phase-frequency detector (PFD) is rising-edge triggered or falling-edge triggered, but not both rising-edge triggered and falling-edge triggered. To utilize rising edges and falling edges of input clock signals, sometimes two PFDs are utilized: one of the PFDs is triggered by rising-edges, the other one of the PFDs is triggered by falling-edges.

Ideally, the two PFDs are perfectly matched at least in terms of: rise and fall times, input to output delay (also called “response time”), layout, output load, and non-idealities (e.g., non-idealities that result from the from fabrication process, without limitation). A rising edge triggered PFD and falling edge triggered PFD may exhibit differences in behavior that are non-negligible because they are not perfectly matched. So, sometimes two PFDs are utilized that are triggered by like edges (i.e., both PFDs are rising edge triggered or both PFDs are falling edge triggered), and one of the PFDs receives a non-inverted version of the input clock signals, and the other one of the PFDs receives an inverted version of the input clock signals.

Edge locking ambiguity may occur when an edge having a first polarity is converted to an edge having a second, different polarity (e.g., a rising edge converted to a falling edge or vice-versa, without limitation), respectively, for dual-edge detection. A clock tracking circuit utilizing dual-edge detection may false-lock a rising edge to falling edge or vice-versa because of a PFD transfer curve NULL condition at about 180-degrees. A NULL condition at 180-degrees, i.e., where two signals are 180-degrees out of phase, is a false positive and may cause a clock tracking circuit to be locked out-of-phase. If the clock tracking circuit locks out of phase, e.g., a rising edge with a falling edge, it may require intervention to unlock.

Additionally, due to differences between rising and falling edge detection circuit paths, a reference spur may arise when the clock tracing circuit locks to opposite edge. Reference spurs degrade noise performance. A “reference spur” is an undesired phase or frequency component in an output signal due to residual difference between the output signal and the reference signal that remain uncorrected due, as non-limiting examples, to non-idealities and imperfections in the error detector or loop filter.

FIG.14is a timing diagram1400depicting a non-limiting example of a conventional dual-edge based lock detection that experiences a false NULL condition at 180-degrees, as known to the inventors of this disclosure.

Timing diagram1400includes waveforms for signals: reference clock, feedback clock, UP signal, DOWN signal, and RESET signal. The waveforms depict an example with 180-degrees phase difference (AO between feedback clock and reference clock.

At time T0, the UP signal is asserted (rising edge) in response to a rising edge of the reference clock (REFCLK) and DOWN signal is asserted (rising edge) in response to a falling edge of the feedback clock (FBCLK). A short time duration after time T0, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being high state. Both the UP signal and the DOWN signal are de-asserted (falling edge) in response to the asserted RESET signal.

At time T1, the UP signal is asserted (rising edge) in response to a falling edge of the reference clock (REFCLK) and DOWN signal is asserted (rising edge) in response to a rising edge of the feedback clock (FBCLK). A short time duration after time T1, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being high state. Both the UP signal and the DOWN signal are de-asserted (falling edge) in response to the asserted RESET signal.

If a phase comparison were performed based on the UP signal and DOWN signal, the phase difference would appear to be zero or negligible, and a conventional dual-edge based lock detector might determine, based on these UP and DOWN signals that the clock tracking circuit is in a locked state.

Sometimes, edges occur during a PFD reset time interval and are missed. Missed edges may cause false NULL condition when the input signals are 180-degrees out of phase.

FIG.15is a timing diagram1500depicting a non-limiting example of a false NULL condition at 180-degrees out of phase due to a missed edge, as known to the inventors of this disclosure.

At time T0, the DOWN signal is asserted (rising edge) in response to the rising edge of the feedback clock. The UP signal was already in a high state having been asserted earlier in response to the rising edge of the reference clock. Notably, the phase difference between the reference clock and the feedback clock is nearly 180-degrees.

At time T1, the RESET signal is asserted (rising edge) in response to rising edges of both the UP signal and the DOWN signal being high state.

At time T2, while the RESET signal is being asserted, the reference clock exhibits a falling edge and the falling edge of the reference clock is missed. The next edge that is detected is the falling edge of feedback clock at time T3, and the DOWN signal is asserted (rising edge) in response to the falling edge of feedback clock.

At time T4, the UP signal is asserted (rising edge) in response to a rising edge of reference clock.

At time T5, the RESET signal is asserted (rising edge) in response to both UP signal and DOWN signal being in the high state. Also at time T5, both UP signal and DOWN signal are de-asserted (falling edge) in response to RESET signal being asserted.

In the case depicted byFIG.15, the phase information in the first set of UP and DOWN signals is accurate, but the phase information in the second set of UP and DOWN signals is not accurate due to the missed falling edge of the reference clock.

One or more examples relate to single and dual-edge triggered phase error detection. The dual edge phase error detection is not performed until the phase error is less than false NULL condition threshold. False NULL condition threshold is a threshold value, 180-degrees or less, that ensures a false NULL condition does not occur, depending on specific operating conditions.

FIG.16is a block diagram depicting an apparatus1600that provides single and dual-edge triggered phase error detection, in accordance with one or more examples.

Phase detector1602generates status signal1616at least partially responsive to two input signals, here, reference clock1610and feedback clock1612. Phase detector1602determines a phase difference between reference clock1610and feedback clock1612and the status of the determined phase difference. Status signal1616indicates a status of phase difference1618between reference clock1610and feedback clock1612.

Status of phase difference1618is a value that represents the instantaneous status of phase difference between reference clock1610and feedback clock1612, or a set of sequential values that represent the continuous status of phase difference between reference clock1610and feedback clock1612.

In one or more examples, that status of phase difference1618that phase detector1602detects is whether or not a phase relationship between reference clock1610and feedback clock1612is less than false NULL condition threshold, e.g., 180-degrees, optionally by some threshold amount, to avoid a false NULL condition. If phase detector1602determines that the phase relationship between reference clock1610and feedback clock1612is less than the false NULL condition threshold, then phase detector1602sets status signal1616to a first value. If phase detector1602determines that the phase relationship between reference clock1610and feedback clock1612greater than the false NULL condition threshold, then phase detector1602sets status signal1616to a second value, different than the first value.

Phase detector1602may change the value of status signal1616from a value indicating the phase relationship is less than 180-degrees to a value indicating not less than 180-degrees in response to a changing (i.e., increasing), phase difference between reference clock1610and feedback clock1612. Thus, in one or more examples, status of phase difference1618and the state of status signal1616may change over time at least partially responsive to changes in the phase difference between reference clock1610and feedback clock1612.

Phase error detector1604receives reference clock1610, feedback clock1612, and phase threshold status signal1616, and generates error signal1614at least partially responsive thereto.

In one or more examples, phase error detector1604generates an error signal that is proportional to a phase difference between two input-selected signals (here, reference clock1610and feedback clock1612). More specifically, the magnitude and direction of the phase error indicated in the error signal is proportional to the phase difference between the input-selected signals. If the phase and frequency of the two input-selected signals is substantially the same, the magnitude and direction information in the error signal will be zero, indicating that the phase and frequency of the two signals are the same. If there is a phase or frequency difference between the two input signals, then the magnitude and direction information in the error signal will be non-zero and proportional to the difference between the phase (and indirectly, the frequency) of the two input signals.

In one or more examples, phase error detector1604may be a binary phase detector that generates error signal1614as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. Phase error detector1604generates the UP signal and the DOWN signal as a series of pulses, where pulses on respective ones of the UP signal and DOWN signal indicate the magnitude and direction of error. The one of the UP signal and the DOWN signal that first exhibits a pulse indicates which one of the two input-selected signals leads the other; and, conversely, which one of the two input-selected signals lags the other. The magnitude of error signal1614is represented by the pulse width of a pulse generated in the UP signal or DOWN signal. A larger pulse width indicating a larger phase difference between the two input signals, and a smaller pulse width indicating a smaller phase difference. One of the inputs of phase error detector1604is preset as the reference input that is led, lagged, or locked to, and the other one of the inputs of phase error detector1604is preset as the feedback (or “controlled”) input that is leading, lagging, or locked on. As a non-limiting example, in a clock-tracking circuit the reference signal is provided to the reference input, and the output signal (or derivative thereof) is provided to the feedback input.

Phase error detector1604operates according to one of single-edge triggered1606or dual-edge triggered1608.

While single-edge triggered1606, phase error detector1604triggers (i.e., generates error signal1614responsive to) only on edges of reference clock1610and feedback clock1612having a first polarity, but not on edges having a second, different polarity. The edges having the first polarity may be one of rising edges or falling edges, and edges having the second polarity may be the other one of rising edges or falling edges. Single-edge triggered may also be referred to as “single-polarity edge triggered.” While single-edge triggered1606, the phase information about reference clock1610and feedback clock1612in error signal1614is based solely on edges of reference clock1610and feedback clock1612having the first polarity.

While dual-edge triggered1608, phase error detector1604triggers (i.e., generates error signal1614responsive to) edges of reference clock1610and feedback clock1612having a first polarity and edges of reference clock1610and feedback clock1612having a second, different polarity. The edges having the first polarity may be one of rising edges or falling edges, and edges having the second polarity may be the other one of rising edges or falling edges. Dual-edge triggered may also be referred to as “dual-polarity edge triggered,” where “dual-polarity” refers to the first polarity and the second, different polarity. While dual-edge triggered1608, the phase information about reference clock1610and feedback clock1612in error signal1614is based on edges of reference clock1610and feedback clock1612having the first polarity and edges of reference clock1610and feedback clock1612having the second polarity.

Being single-edge triggered1606or dual-edge triggered1608is set at phase error detector1604at least partially in response to a value of status signal1616. A first value of status signal1616indicates that the phase difference between reference clock1610and feedback clock1612is less than the false NULL condition threshold. A second value of status signal1616indicates that the phase difference between reference clock1610and feedback clock1612is greater than or equal to the false NULL condition threshold. In this manner, phase error detector1604may operate single-edge triggered1606while the phase difference between reference clock1610and feedback clock1612is greater than or equal to the false NULL condition threshold, and operate dual-edge triggered1608while the phase difference between reference clock1610and feedback clock1612is less than the false NULL condition threshold.

Edges fed into phase error detector1604when dual-edge triggered are converted the same polarity unless already that polarity. If an edge of feedback clock1612or reference clock1610has a different polarity, it is converted to the same polarity. The phase error detector1604could lock edges of feedback clock1612and reference clock1610having different polarities if the phase error was greater than or equal to 180-degrees. Limiting the phase error detection based on edges having a first polarity until the phase error is less than 180-degrees and then detecting phase error based on both of edges having first polarity and edges having a second polarity, ensures the false NULL conditions do not occur.

One or more examples relate, generally, to phase error detection that operates single-edge triggered until the phase-error between two input signals is less than 180 degrees and then operates dual-edge triggered. During single-edge mode, the phase error detection is at least partially based on un-converted versions of the input signals. During dual-edge mode, the phase error detection is at least partially based on converted versions of the input signals.

Examples reduce or eliminate the false NULL condition that would otherwise occur in the dual-edge mode PFD transfer function, and which might prevent the clock-tracking circuit from being locked at a suitably small phase error.

FIG.17is a block diagram depicting an apparatus1700that provides single and dual-edge triggered phase error detection, in accordance with one or more examples. Apparatus1700may also be referred to herein as a “phase error detector1700.”

Apparatus1700changes from single-edge lock detect to dual-edge lock detect, dynamically. Apparatus1700changes from single-edge lock detect in response to determining that the phase-error between two input signals is less than the false NULL condition threshold, here, 180-degrees.

Apparatus1700includes Phase detector1702, an inverter1704, an inverter1706, an AND gate1708, an AND gate1710, a first flip-flop1712, a second flip-flop1714, a third flip-flop1716, a fourth flip-flop1718, an OR gate1722, an OR gate1724, a delay1726, a and NAND gate1728.

Phase detector1702is a non-limiting examples of phase detector1602ofFIG.16(status of phase difference1618is omitted solely to avoid unnecessarily clutteringFIG.17). The remaining sequential logic circuit inFIG.17is a non-limiting example of phase error detector1604ofFIG.16, and UP signals1738and DOWN signal1740are examples of components error signals of error signal1614.

Phase detector1702generates status signal1732at least partially responsive to two input signals, here, reference clock1734and feedback clock1736. Phase detector1702may be, as a non-limiting example, phase detector200ofFIG.2where the false NULL condition threshold is set to be 180-degrees. Status signal104indicates the phase relationship between reference clock1734and feedback clock1736, namely, whether or not it is less than the false NULL condition threshold to ensure NULL conditions discussed above, do not occur. Phase detector1702determines whether or not a phase relationship between reference clock1734and feedback clock1736is less than 180-degrees, and sets status signal1732to a value based on the determination. In the specific non-limiting example depicted byFIG.17, the set value of status signal1732is maintained unless/until the phase difference increases above the 180-degrees threshold. In other examples, it is specifically contemplated that the value of status signal1732does not change once set to indicate the phase difference is less than 180-degrees, unless/until the phase relationship increases above the 180-degrees threshold.

If phase detector1702determines that the phase difference is not less than 180-degrees, then phase detector1702sets the status signal1732to a value that indicates the same. In the specific non-limiting example depicted byFIG.17, phase detector1702utilizes a high state or ‘1’ to indicate the phase difference is less than 180-degrees and utilizes a low state or ‘0’ to indicate that the phase difference is not less than 180-degrees. Other conventions may be utilized with minor circuit modifications to the apparatus1700that would be readily apparent to a person having ordinary skill in the art, and so use of other conventions does not exceed the scope of this disclosure.

First flip-flop1712, second flip-flop1714, third flip-flop1716, and fourth flip-flop1718are edge-triggered flip-flops. Each flip-flop202,204,220, and224has a Data (D) input, a clock (CLK) input and an output (Q).

When first flip-flop1712, second flip-flop1714, third flip-flop1716, or fourth flip-flop1718is reset, its respective output (Q) is forced to low state (i.e., low state at the reset (R) input overrides the data (D) input and clock (CLK) input and forces output (Q) to low state). Respective reset (R) inputs of first flip-flop1712, second flip-flop1714, third flip-flop1716, and fourth flip-flop1718are active low.

Delay1726is a delay circuit that introduce a predetermined amount of time delay to the propagation of a signal from its input to its output. In one or more examples, the predetermined amount of time delay introduced is equal to, or at least partially based on, a suitable time to allow components in a clock tracking circuit a minimum ON time so they can settle before the state of the output of phase error detector1700changes.

Respective data (D) inputs of first flip-flop1712, second flip-flop1714, third flip-flop1716, and fourth flip-flop1718are coupled to a supply voltage to set the data (D) inputs to a high state. The clock (CLK) input of first flip-flop1712receives reference clock1734, and the clock (CLK) input of third flip-flop1716receives feedback clock1736. One of the inputs of OR gate1722receives the output (Q) of first flip-flop1712, and one of the inputs of OR gate1722receives the output of second flip-flop1714. The output of OR gate1722is provided as UP signal1738. One of the inputs of OR gate1724receives the output (Q) of third flip-flop1716, and one of the inputs of OR gate1724receives the output of fourth flip-flop OR gate1724. The output of OR gate1724is provided as DOWN signal1740.

An input of delay1726receives the output of NAND gate1728. The respective reset (R) inputs of first flip-flop1712and third flip-flop1716receive the output of delay1726, which is the delayed output of NAND gate1728. The output of delay1726i.e., delayed output of NAND gate1728, may also be referred to herein as a reset signal1742. As long as at least one of the inputs of NAND gate1728is set to low state, its output is set to high state, which does not reset first flip-flop1712or third flip-flop1716.

While the phase difference between reference clock1734and feedback clock1736is greater than or equal to 180-degrees, phase detector1702maintains the clock (CLK) inputs of second flip-flop1714and fourth flip-flop1718to low state via inverter1704, AND gate1708, inverter1706and AND gate1710. While the clock (CLK) inputs are maintained at low state, the respective outputs (Q) of second flip-flop1714and fourth flip-flop1718do not change from the reset state and therefore are in the low state. This condition corresponds to setting apparatus1700to operate as single-edge triggered. When the phase difference between reference clock1734and feedback clock1736is less than 180-degrees, Phase detector1702sets apparatus1700to operate dual-edge triggered, as discussed below.

In single-edge mode, apparatus1700is rising-edge triggered. When one of reference clock1734or feedback clock1736changes from low state to high state (i.e., exhibits a rising edge), then the corresponding one of UP signal1738or DOWN signal1740change from low state to high state. When the other one of reference clock1734or feedback clock1736changes from low state to high state, then the other corresponding one of UP signal1738or DOWN signal1740changes from low state to high state. First flip-flop1712and third flip-flop1716are reset, after predetermined delay time provided by delay1726, in response to both UP signal1738and DOWN signal1740having changed from low state to high state by the action of NAND gate1728. Respective outputs (Q) of first flip-flop1712and third flip-flop1716are set to low state (forced to low state) in response to being reset. UP signal1738and DOWN signal1740change from high state to low state in response to the outputs (Q) of first flip-flop1712and third flip-flop1716changing from high state to low state. Upon the respective outputs (Q) of the flip-flops being forced to a low-state the reset signal1742changes from a high state to a low state due to the action of NAND gate1728.

When the phase difference between reference clock1734and feedback clock1736is less than 180-degrees, phase detector1702enables dual-edge mode at apparatus1700. Specifically, phase detector1702sets status signal1732to a high state and maintains the high state. One of the inputs of AND gate1708and AND gate1710is set to high state in response to status signal1732being set to high state. The other one of the inputs of AND gate1708and AND gate1710receives inverted reference clock1734via inverter1704and inverted feedback clock1736via inverter1706, respectively. Maintaining one of the inputs of AND gate1708and AND gate1710at high state effectively sets the respective outputs of AND gate1708and AND gate1710to be responsive to reference clock1734and feedback clock1736, respectively, and so sets respective clock (CLK) inputs second flip-flop1714and fourth flip-flop1718to be responsive to inverted reference clock1734and inverted feedback clock1736, respectively. Setting respective clock (CLK) inputs of second flip-flop1714and fourth flip-flop1718to be responsive to inverted reference clock1734and feedback clock1736is effectively setting respective clock (CLK) inputs of second flip-flop1714and fourth flip-flop1718to be responsive to falling edges of reference clock1734and feedback clock1736. So, when one of reference clock1734or feedback clock1736changes from high state to low state (i.e., exhibits a falling edge), the corresponding one of second flip-flop1714or fourth flip-flop1718is triggered, and its output (Q) changes from low state to high state.

In dual-edge mode, rising edge triggering is performed the same as in single-edge mode, discussed above. For falling-edge triggering, when one of reference clock1734or feedback clock1736changes from high state to low state (i.e., exhibits a falling edge), then the corresponding one of UP signal1738or DOWN signal1740change from low state to high state through the respective one of OR gate1722and OR gate1724. When the other one of reference clock1734or feedback clock1736changes from high state to logic low, then the other corresponding one of UP signal1738or DOWN signal1740changes from low state to high state. First flip-flop1712and third flip-flop1716are reset, after the predetermined delay time provided by delay1726, in response to both UP signal1738and DOWN signal1740having changed from low state to high state, due to the action of NAND gate1728. Respective outputs (Q) of second flip-flop1714and fourth flip-flop1718are set to low state (forced to low state) in response to being reset. UP signal1738and DOWN signal1740change from high state to low state in response to the outputs (Q) of first flip-flop1712and third flip-flop1716changing from high state to low state.

FIG.18is a flow diagram depicting a process1800for improved dual-edge detection, in accordance with one or more examples. Some or a totality of operations of process1800may be performed by, as a non-limiting example, by apparatus1600or phase error detector1604, phase error detector1700.

Although the example process1800depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process1800. In other examples, different components of an example device or system that implements the process1800may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes generating, via a phase error detector, an error signal proportional to a phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock at operation1802.

According to one or more examples, the method includes responsive to a status signal indicate status of phase difference between the reference clock and the feedback clock, setting the phase error detector to be responsive to either.

Edges of the reference clock and the feedback clock having a first polarity; or Edges of the reference clock and the feedback clock having a first polarity and edges of the reference clock and the feedback clock having a second polarity, wherein the second polarity is different than the first polarity at operation1804.

FIG.19is a flow diagram depicting a process1900for setting a status signal to indicate status of phase difference between a reference clock and a feedback clock, in accordance with one or more examples. Some or a totality of operations of process1900may be performed by, as a non-limiting example, by apparatus1600or phase detector1602.

Although the example process1900depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process1900. In other examples, different components of an example device or system that implements the process1900may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes determining a respective status of phase difference between the reference clock and the feedback clock at operation1902.

According to one or more examples, the method includes setting the status signal to indicate the determined respective status of phase difference at operation1904.

FIG.20is a flow diagram depicting a process2000for setting a status signal to indicate status of phase difference between a reference clock and a feedback clock, in accordance with one or more examples. Some or a totality of operations of process2000may be performed by, as a non-limiting example, by apparatus1600or phase detector1602.

Although the example process2000depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process2000. In other examples, different components of an example device or system that implements the process2000may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes setting the status signal to a first value to indicate a phase difference between the reference clock and the feedback clock is less than a false NULL condition threshold at operation2002.

According to one or more examples, the method includes setting the status signal to second value to indicate the phase difference between the reference clock and the feedback clock is greater than or equal to the false NULL condition threshold, wherein the second value is different than the first value at operation2004.

FIG.21is a flow diagram depicting a process2100for determining a status of phase difference between a reference clock and a feedback clock, in accordance with one or more examples. Some or a totality of operations of process2100may be performed by, as a non-limiting example, by apparatus1600or phase detector1602.

Although the example process2100depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process2100. In other examples, different components of an example device or system that implements the process2100may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes determining a first status of phase relationship responsive to determining the phase relationship being less than a false NULL condition threshold at operation2102.

According to one or more examples, the method includes determining a second status of phase relationship responsive to determining the phase relationship is greeter than or equal to the false NULL condition threshold at operation2104.

FIG.22is a flow diagram depicting a process2200for determining phase error, in accordance with one or more examples. Some or a totality of operations of process2200may be performed by, as a non-limiting example, by apparatus1600or phase error detector1604.

Although the example process2200depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process2200. In other examples, different components of an example device or system that implements the process2200may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes while the phase error detector is set to be responsive to edges of the reference clock and feedback clock having the first polarity, determining, by the phase error detector, phase error at least partially based edges of the first polarity. at operation2202.

According to one or more examples, the method includes whiling the phase error detector is set to be responsive to edges of the reference clock and feedback clock having the first polarity and edges of the reference clock and feedback clock having the second polarity, determining, by the phase error detector, phase error at least partially based on edges of the reference clock and the feedback clock having the first polarity and edges of the reference clock and the feedback clock having the second polarity at operation2204.

FIG.23is a flow diagram depicting a process2300for setting a phase error signal to indicate magnitude and direction of phase difference between a reference clock and a feedback clock, in accordance with one or more examples. Some or a totality of operations of process2200may be performed by, as a non-limiting example, by apparatus1600or phase error detector1604.

Although the example process2300depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the process2300. In other examples, different components of an example device or system that implements the process2300may perform functions at substantially the same time or in a specific sequence.

According to one or more examples, the method includes whiling the phase error detector is set to be responsive to edges of the reference clock and feedback clock having the first polarity, setting, by the phase error detector, an error signal (e.g., error signal1614ofFIG.16, or UP signal1738and DOWN signal1740ofFIG.17, without limitation) to indicate magnitude and direction of phase error between edges of the reference clock and the feedback clock having the first polarity, at operation2302.

According to one or more examples, the method includes while the phase error detector is set to be responsive to edges of the reference clock and feedback clock having the first polarity and edges of the reference clock and feedback clock having the second polarity, setting, by the phase error detector, an error signal (e.g., error signal1614ofFIG.16, or UP signal1738and DOWN signal1740ofFIG.17, without limitation) to indicate magnitude and direction of phase difference between edges of the reference clock and the feedback clock having the first polarity and edges of the reference clock and the feedback clock having the second polarity at operation2304.

FIG.24illustrates an example2400for setting a status signal to indicate a status of phase relationship between a reference clock and a feedback clock based on a false NULL condition threshold, in accordance with one or more examples.

Although the example2400depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the2400. In other examples, different components of an example device or system that implements the2400may perform functions at substantially the same time or in a specific sequence.

According to some examples, the method includes detecting occurrences of like respective edges of the reference clock and the feedback clock at operation2402.

According to some examples, the method includes setting the status signal to the first value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is less than a false NULL condition threshold at block2404.

According to some examples, the method includes setting the status signal to the second value responsive to the time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is greater than or equal to the false NULL condition threshold at block2406.

FIG.25is a timing diagram2500depicting an example operation of a dual-edge PFD such as apparatus1700, without limitation.

Timing diagram2500includes waveforms for signals reference clock1734, feedback clock1736, UP signal1738, DOWN signal1740, and reset signal1742. The waveforms depict an example with small phase difference (AO.

At time T0, UP signal1738is asserted (causing a rising edge) in response to a rising edge of reference clock1734.

At time T1, the DOWN signal1740is asserted (causing a rising edge) in response to a rising edge of feedback clock1736.

At time T1(plus an optional delay due to delay1726but not shown inFIG.18), in response to rising edges UP signal1738and DOWN signal1740, and both being high state, reset signal1742is asserted (causing a rising edge), maintained at a high state for a predetermined time duration, and then de-asserted (causing a falling edge). Notably, in the example apparatus1700ofFIG.17, reset signal1742is active low (as discussed above with respect to the reset (R) inputs of respective flip-flops of apparatus1700ofFIG.17), neverthelessFIG.25depicts a pulse (low state to high state, and then high state to low state) for ease of description. Any convention may be used without exceeding the scope (e.g., active low or active high).

At time T1+the predetermined time duration (during which UP signal1738and DOWN signal1740are maintained in a high state), the UP signal1738and the DOWN signal1740are both de-asserted (causing respective falling edges) in response to the assertion of the reset signal1742.

From time Toto time T1, phase frequency detector PFD phase comparison is made between reference clock1734and feedback clock1736utilizing the timing of their respective rising edges, and the phase detector PFD determines the phase difference (Δϕ) is less than 180-degrees and asserts status signal1732(status signal1732is not depicted byFIG.25). Asserting status signal1732enables dual-edge detection, and more specifically, triggering on both rising and falling edges of reference clock1734and feedback clock1736.

At time T2, UP signal1738is asserted (causing a rising edge) in response to a falling edge of reference clock1734.

At time T3, the DOWN signal1740is asserted (causing a rising edge) in response to a falling edge of feedback clock1736.

At time T3+a predetermined time duration, in response to falling edges of UP signal1738and DOWN signal1740and both being low state, reset signal1742is asserted (causing a rising edge), maintained at a high state for a predetermined time duration, and then de-asserted (causing a falling edge).

At time T3+the predetermined time duration (during which UP signal1738and DOWN signal1740are maintained in a high state), the UP signal1738and the DOWN signal1740are both de-asserted (causing respective falling edges) in response to the assertion of the reset signal1742.

FIG.26is a graph2600of a simulation plot that shows a curve representing a single-edge mode PFD transfer function of a phase error detector in accordance with one or more examples. The PFD exhibits a NULL condition only at 0-degrees but not 180-degrees and therefore always aligns rising edges to rising edges.

FIG.27is a graph2700of a simulation plot that shows a curve representing a nominal dual-edge mode PFD transfer function which has an undesirable NULL at 180-degrees and a desirable NULL at 0-degrees. The false NULL condition at 180-degrees allows the clock tracking circuit to phase lock to opposite edges and increases mismatch and reference spurs.

FIG.28is a graph2800of a simulation plot that shows a curve that represents the dynamic dual-edge mode transfer function. There is no longer a NULL condition at 180-degrees. Hence, the PFD will push the PLL to lock rising edge to rising edge as in the single-edge mode case. When the phase error is small dual-edge mode is enabled resulting in a 2× transfer curve gain (triggered on both rising and falling edges instead of only one of rising edges or falling edges) just and a doubling of the PFD rate. The portions of the curve exhibiting 2× the slope correspond to the circuit operating in dual edge mode with 2× the gain (for that range of phase error). Negative phase error refers to the case where the feedback clock leads to the reference clock. Positive phase error refers to the case where the feedback clock lags the reference clock.

It will be appreciated by those of ordinary skill in the art that functional elements of examples disclosed herein (e.g., functions, operations, acts, processes, or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof.FIG.29illustrates non-limiting examples of implementations of functional elements disclo sed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware capable of carrying out the functional elements.

FIG.29is a block diagram of a circuitry2900that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. The circuitry2900includes one or more processors processor(s)2902(sometimes referred to herein as “processor(s)2902”) operably coupled to one or more data storage devices storage2906(sometimes referred to herein as “storage2906”). The storage2906includes machine executable code2908stored thereon and the processors processor(s)2902include logic circuit2904. The machine executable code2908information describing functional elements that may be implemented by (e.g., performed by) the logic circuit2904. The logic circuit2904is adapted to implement (e.g., perform) the functional elements described by the machine executable code2908. The circuitry2900, when executing the functional elements described by the machine executable code2908, should be considered as special purpose hardware for carrying out functional elements disclosed herein. In some examples the processors processor(s)2902may perform the functional elements described by the machine executable code logic circuit2904sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

When implemented by logic circuit machine executable code2908of the processors processor(s)2902, the machine executable code2908adapts the processors processor(s)2902to perform operations of examples disclosed herein, including for determining a locked status of a clock tracking circuit. By way of non-limiting example, the machine executable code2908may adapt the processor(s)2902to perform some or a totality of operations of one or more of: process800, process900, process1000, process1100, or process1200.

Also by way of non-limiting example, the machine executable code2908may adapt the processors processor(s)2902to perform some or a totality of features, functions, or operations disclosed herein for one or more of: apparatus100, apparatus200, apparatus300, apparatus400, apparatus500, apparatus600, apparatus700. More specifically, features, functions, or operations disclosed herein for one or more of: phase detector102, a digital discriminator106, and a logic circuit112ofFIG.1; apparatus200includes first flip-flop202, a second flip-flop204, third flip-flop220, a fourth flip-flop218. a first delay circuit208, a second delay circuit222, a NAND gate206, and a NOR gate210ofFIG.2; and digital filter302and register304; accumulation register402, comparator404, sampling clock divider502, sampling logic circuit602, interpolator604, decimator606, multiplexer612, clock tracking circuit1300, error detector1302, controller1304, controlled-oscillator1306, or locked status detector1318.

When implemented by logic circuit machine executable code2908of the processors processor(s)2902, the machine executable code2908adapts the processors processor(s)2902to perform operations of examples disclosed herein, including for dual edge triggered phase error detection. By way of non-limiting example, the machine executable code2908may adapt the processor(s)2902to perform some or a totality of operations of one or more of: process1800, process1900, process2000, process2100, process2200, process2300,2400, timing diagram2500, graph2600, graph2700, or graph2800.

Also by way of non-limiting example, the machine executable code2908may adapt the processors processor(s)2902to perform some or a totality of features, functions, or operations disclosed herein for one or more of: apparatus1600and apparatus1700. More specifically, features, functions, or operations disclosed herein for one or more of: phase detector1602, phase error detector1604, single-edge triggered1606, dual-edge triggered1608; phase detector1702, inverter1704, inverter1706, AND gate1708, AND gate1710, first flip-flop1712, second flip-flop1714, third flip-flop1716, fourth flip-flop1718, OR gate1722, OR gate1724, delay1726, NAND gate1728.

The processors processor(s)2902may include a general purpose processor, a special purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable device, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer while the general-purpose computer executes functional elements corresponding to the machine executable code2908(e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure. It is noted that a general-purpose processor (may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in the alternative, the processors502may include any conventional processor, controller, microcontroller, or state machine. The processor(s)2902may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

In some examples the storage2906includes volatile data storage (e.g., random-access memory (RAM)), non-volatile data storage (e.g., Flash memory, a hard disc drive, a solid state drive, erasable programmable read-only memory (EPROM), without limitation). In some examples the processor(s)2902and the storage2906may be implemented into a single device (e.g., a semiconductor device product, a system on chip (SOC), without limitation). In some examples the processor(s)2902and the storage2906may be implemented into separate devices.

In some examples the machine executable code2908may include computer-readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer-readable instructions may be stored by the storage2906, accessed directly by the processor(s)2902, and executed by the processor(s)2902using at least the logic circuit2904. Also by way of non-limiting example, the computer-readable instructions may be stored on the storage2906, transferred to a memory device (not shown) for execution, and executed by the processors502using at least the logic circuit2904. Accordingly, in some examples the logic circuit508includes electrically configurable logic circuit2904.

In some examples the machine executable code2908may describe hardware (e.g., circuitry) to be implemented in the logic circuit2904to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. At a high-level of abstraction, a hardware description language (HDL) such as an IEEE Standard hardware description language (HDL) may be used. By way of non-limiting examples, Verilog™, SystemVerilog™ or very large-scale integration (VLSI) hardware description language (VHDL) may be used.

HDL descriptions may be converted into descriptions at any of numerous other levels of abstraction as desired. As a non-limiting example, a high-level description can be converted to a logic-level description such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, micro-operations to be performed by hardware logic circuits (e.g., gates, flip-flops, registers, without limitation) of the logic circuit2904may be described in a RTL and then converted by a synthesis tool into a GL description, and the GL description may be converted by a placement and routing tool into a layout-level description that corresponds to a physical layout of an integrated circuit of a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples the machine executable code2908may include an HDL, an RTL, a GL description, a mask level description, other hardware description, or any combination thereof.

In examples where the machine executable code2908includes a hardware description (at any level of abstraction), a system (not shown, but including the storage2906) implements the hardware description described by the machine executable code2908. By way of non-limiting example, the processor(s)2902may include a programmable logic device (e.g., an FPGA or a PLC) and the logic circuit2904may be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit2904. Also by way of non-limiting example, the logic circuit2904may include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage2906) according to the hardware description of the machine executable code2908.

Regardless of whether the machine executable code2908includes computer-readable instructions or a hardware description, the logic circuit2904is adapted to perform the functional elements described by the machine executable code2908when implementing the functional elements of the machine executable code2908. It is noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description are capable of performing.

As used in the present disclosure, the term “combination” with reference to a plurality of elements may include a combination of all the elements or any of various different subcombinations of some of the elements. For example, the phrase “A, B, C, D, or combinations thereof” may refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

Terms used in the present disclosure and especially in the appended claims (e.g., bodies of the appended claims, without limitation) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including, but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes, but is not limited to,” without limitation). As used herein, the term “each” means “some or a totality.” As used herein, the term “each and every” means a “totality.”

Example 1: An apparatus, comprising: a phase detector, wherein a status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock; a digital discriminator to sample the status signal of the phase detector; and a logic circuit to determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

Example 2: The apparatus according to Example 1, wherein the phase detector to set the status signal at least partially based on a phase threshold and the phase relationship between the reference clock and the feedback clock.

Example 3: The apparatus according to any of Examples 1 and 2, wherein a value of the phase threshold is settable.

Example 4: The apparatus according to any of Examples 1 through 3, wherein the phase detector to: set the status signal to a first value at least partially responsive to determining that a determined amount of difference is greater than a phase threshold.

Example 5: The apparatus according to any of Examples 1 through 4, wherein the phase detector to: set the status signal of the phase detector to a second value at least partially responsive to determining that a determined amount of difference is equal to or less than a phase threshold, wherein the second value is different than a first value.

Example 6: The apparatus according to any of Examples 1 through 5, wherein, to determine the locked status of the clock tracking circuit, the logic circuit to: decode locked status information from samples of the status signal of a phase detector; and determine the locked status of the clock tracking circuit at least partially based on the decoded locked status information.

Example 7: The apparatus according to any of Examples 1 through 6, wherein the logic circuit to set a locked status signal to a first value to indicate a locked state and set the locked status signal to a second value to indicate a not locked state.

Example 8: The apparatus according to any of Examples 1 through 7, wherein the phase detector to: detect occurrences of like respective edges of the reference clock and the feedback clock; and set the status signal to indicate whether or not the detected occurrences of like respective edges were within a predetermined range.

Example 9: The apparatus according to any of Examples 1 through 8, wherein the phase detector to: set the status signal to a first value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is less than a phase threshold.

Example 10: The apparatus according to any of Examples 1 through 9, wherein the phase detector to: set the status signal to a second value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is greater than or equal to a phase threshold.

Example 11: The apparatus according to any of Examples 1 through 10, wherein the digital discriminator includes a decimator to decimate values of the status signal.

Example 12: The apparatus according to any of Examples 1 through 11, wherein the digital discriminator includes an interpolator to interpolate values based on the status signal.

Example 13: The apparatus according to any of Examples 1 through 12, wherein the digital discriminator includes a digital filter to block status signal that is indicative of transient phase error and pass status signal that is indicative of steady-state phase error.

Example 14: A method, comprising: setting a status signal of a phase detector, wherein the status signal of the phase detector is set at least partially based on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock; and generating a signal indicative of a locked status of the clock tracking circuit at least partially based on the status signal of the phase detector.

Example 15: The method according to Example 14, comprising: determining whether or not the phase relationship between the reference clock and feedback clock falls within a predetermined range; and setting the status signal of the phase detector at least partially based on the determination.

Example 16: The method according to any of Examples 14 and 15, comprising: setting the status signal of the phase detector to a first value at least partially responsive to determining that a determined amount of difference is greater than a phase threshold.

Example 17: The method according to any of Examples 14 through 16, comprising: setting the status signal of the phase detector to a second value at least partially responsive to determining that a determined amount of difference is equal to or less than a phase threshold, wherein the second value is different than a first value.

Example 18: The method according to any of Examples 14 through 17, detecting occurrences of like respective edges of the reference clock and the feedback clock; and setting the status signal to indicate whether or not the detected occurrences of like respective edges were within a predetermined range.

Example 19: The method according to any of Examples 14 through 18, wherein setting the status signal to indicate whether or not the detected occurrences of like respective edges were within the predetermined range comprises: setting the status signal to a first value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is less than a phase threshold.

Example 20: The method according to any of Examples 14 through 19, wherein setting the status signal to indicate whether or not the detected occurrences of like respective edges were within the predetermined range comprises: setting the status signal to a second value responsive to a time difference between the detected occurrences of like respective edges of the reference clock and the feedback clock is greater than or equal to a phase threshold.

Example 21: The method according to any of Examples 14 through 120, obtaining samples of the status signal of the phase detector; decoding locked status information from samples of the status signal of the phase detector; and determining the locked status of the clock tracking circuit at least partially based on the decoded locked status information.

While the present disclosure has been described herein with respect to certain illustrated examples, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described examples may be made without departing from the scope of the invention as hereinafter claimed along with their legal equivalents. In addition, features from one example may be combined with features of another example while still being encompassed within the scope of the invention as contemplated by the inventor.