Electro static discharge clamping device

Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.

TECHNICAL FIELD

The present invention relates generally to electro static discharge, and more particularly to a semiconductor device for protecting against electro static discharge.

BACKGROUND

As electronic components are getting smaller along with the internal structures in integrated circuits, it is increasingly easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Generally, electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages, caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry.

Device failures resulting from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses. Such a weakened device may result in reliability problems. Therefore, various ESD protection circuits should be included in an integrated circuit to protect its various components.

When a transistor is impacted by an ESD pulse, the extremely high voltage of the ESD pulse can break down the transistor and can potentially cause permanent damage. Consequently, the transistors of an integrated circuit need to be protected from ESD pulses to prevent such damage.

Integrated circuits and the geometry of the transistors that make up the integrated circuits continue to be reduced in size and the transistors are arranged closer together. A transistor's physical size limits the voltage that the transistor can withstand without being damaged. Thus, breakdown voltages of transistors are lowered and currents capable of overheating components are more frequently reached by the voltages and currents induced by an ESD event.

Thus, there is a need for small ESD protection devices that can be rapidly triggered and conduct through the duration of the pulse, yet are robust against spurious effects such as false triggering.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention.

Embodiments of the invention include electrostatic discharge clamps. In accordance with a preferred embodiment of the present invention, a semiconductor device includes a first transistor, the first transistor comprising a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further comprises an OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely an electro static discharge clamp. The invention may also be applied, however, to other types of applications and devices.

Gate-biased electro static discharge (ESD) power supply clamps are used in the art for protection against ESD. Gate-biasing is generated typically from the output voltage of an RC-timer circuit which is amplified by one or more buffer stages. A standard RC-timed MOS power supply clamp (“RCMOS”) is shown inFIG. 1a. The clamp is triggered with the rising edge of the ESD pulse and remains conducting as determined by the RC-time constant. The RC time constant is determined by the resistance of the resistor10and the capacitance of the capacitor20. The buffers30amplify the voltage at a node between the capacitor20and the resistor10to transiently bias the gate of the MOS transistor100. However, after the transient (a time given by the time constant of the RC timer), the MOS transistor100of the RCMOS clamp is not conducting any more as the gate bias drops after the charging of the capacitor20because the node voltage drops close to ground. Hence, if the time constant of the RC timer circuit is less than that of the ESD event, the RCMOS clamp cannot provide a conductive path during the full duration of the ESD event. As the pulse width of the ESD event and the time constant of the RC circuit are independent, the RC-time constant needs to be large enough to cover the duration of an ESD pulse. Further, the RC timer circuit has to be designed to accommodate the worst case scenario (largest pulse expected). Hence, in practice, the RCMOS clamp requires large area capacitors, and results in a deleterious increase in stand-by leakage current.

To overcome the limitation of requiring large RC timer circuits, feed back circuits are added to the RCMOS clamps. For example, as illustrated inFIG. 1b, additional, feedback loops are used to enhance the gate-bias effect and to increase the effective RC-time constant without requiring more (IC-area consuming) capacitance. InFIG. 1b, an additional buffer31forms a feedback loop that sustains a longer transient at the gate of the MOS transistor100. Thus, the gate bias signal at the MOS transistor100is sustained for a longer time than the original RC-time constant of the RC circuit. However, RC-timed MOS power supply clamps exhibit many problems including unintended triggering and/or increased leakage currents during e.g. power ramp up or noise/voltage spikes on the supply line. Particularly, RCMOS with feedback loops have to be very carefully designed to avoid oscillation. Furthermore, all RC-timed MOS clamps are specifically sensitive to trailing electrical overstress (EOS), an unwanted phenomenon occurring in some ESD testing equipment, where parts of the remaining charge cannot be drained away due to the shut-off of the clamp after RC-time-out.

Another approach in the art is the use of substrate pumping. The substrate-pumped clamp, as illustrated inFIG. 2, features a pump transistor that pumps current into the local substrate of the actual ESD shunt element (e.g. by a ring). The substrate pumping allows the MOS transistor100to uniformly conduct by a combination of MOS source to drain current arising from the extra gate biasing, enhanced MOS current due to the increased substrate potential and thus utilization of the MOS-body effect, and finally bipolar current due to the injected substrate current acting as base current for the parasitic bipolar. Yet, as in the case of the RCMOS device discussed above, a RC-timer circuit is required to turn on the clamp (MOS transistor100) for the complete duration of the ESD pulse. Another drawback is the large size required for the pump transistor (within the buffers30), which may typically reach the size of the clamp device itself.

Because of mainly MOS-based device operation, both clamping approaches described above can be used without the need for silicide blocking. Silicide blocking is a process feature formed by blocking the formation of the silicide over the source/drain regions. The absence of silicide adds ballasting resistance in the source/drain regions. Silicide blocking would prevent failure of the device due to local heating arising from non-uniform current distribution. With silicide blocking, the current would be forced through a larger region resulting in better heat dissipation. Silicide blocking is not needed in the prior art devices mentioned and is generally not preferred as it requires a separate masking step resulting in an increase in production cost.

In various embodiments, the present invention overcomes these limitations by providing an ESD clamp whose conduction is determined by the ESD event (rather than an independent RC timer), that is robust against false triggering during power up, and/or against supply noise, and immune from trailing EOS. Further, the present invention in various embodiments comprises a device that is fabricated in a small area due to the low capacitive requirements, and consumes lower power (low leakage).

Embodiments of the invention use RC-triggering for generating a bias voltage only for the initial turn of the ESD clamp comprising a MOS transistor. After the MOS transistor of the ESD clamp is turned on, the bias voltage for the remainder of the ESD pulse will be generated by the clamp itself. Further, the ESD clamp is “self-timed” to match the duration of the ESD pulse. In various embodiments, the clamping device is a MOS transistor that operates at the transition between MOS-mode and bipolar-mode. This inter mode operation of the MOS transistor results in an elevated substrate potential. The elevated substrate potential is fed back to a circuit from which the bias voltage is generated. However, the elevated substrate potential is only existent for the duration of the ESD pulse resulting in an “auto-biased” device. Embodiments of the present invention disclosure include circuit implementations and additional device design and layout techniques for realizing this clamping technique for ESD protection.

In contrast to the above mentioned prior art, the auto-biased self-timing (ABST) clamp does not inject a substrate current by a pumping circuit, but picks up an inherent substrate potential. Unlike the embodiment ofFIG. 1b, a circular feedback mechanism of the gate voltage is not used. Rather, a moderate avalanche breakdown at the onset of parasitic bipolar conduction makes the clamp advantageously immune to false triggering during normal circuit operating conditions. Embodiments of the invention include omitting use of silicide blocking for the MOS clamp transistor, thus saving area and processing costs.

An embodiment of the invention will be described usingFIG. 2. Simulations illustrating the operation of the ESD will be described usingFIG. 3. Further embodiments of the ESD clamp will be described usingFIGS. 4-9. Structural embodiment of the MOS transistor in the ESD clamp will be described usingFIGS. 10 and 11.

FIG. 2, which includesFIGS. 2aand2b, illustrates the ESD clamp device in accordance with an embodiment of the invention.

FIG. 2aillustrates an ESD clamp device in accordance with an embodiment of the invention. The ESD clamp device comprises a MOS transistor100coupled between power supply line VDD, and substrate voltage line VSS. A parasitic bipolar device101is also illustrated. The gate of the MOS transistor100is coupled to a RC timer circuit through an inverting buffer stage30(or a plurality of inverting buffer stages) and a NOR gate40. In particular, a first plate of the capacitor20is coupled to the power supply line VDD and a second plate of the capacitor20is coupled to the substrate voltage line VSS through the resistor10. The first input of the NOR gate40is coupled to the second plate of the capacitor20, while a second input of the NOR gate40is coupled to the substrate of the MOS transistor100. However, unlike prior embodiments, the substrate of the MOS transistor100is coupled to the second input of the NOR gate40through a pickup node P. The coupling of the substrate of the MOS transistor100to the second input of the NOR gate40forms the auto biasing circuit.

The MOS transistor100, in various embodiments, comprises a large width. In one embodiment, the gate length of the MOS transistor100may be at a minimum possible length, and, for example, about 50 nm in one embodiment. The width of the MOS transistor100is at least 10 μm, and about 200 μm to about 400 μm in one embodiment. The local substrate of the MOS transistor100is coupled to the substrate voltage line VSS through a substrate resistance (Rsub) depending on the design of the MOS transistor100. In one embodiment, the local substrate is shielded from the substrate contact by counter doped regions. For optimal pickup of the local substrate potential, the substrate resistance Rsub is larger than the pickup resistance between the junction of the MOS transistor100(e.g., the source/substrate junction) generating the carriers and the pickup node P of the MOS transistor100. Hence, the pickup point P for picking the local substrate potential is closer to the junction of the MOS transistor100than the substrate pickup point for contacting the substrate or body of the MOS transistor100. Further, the pickup resistance is reduced as much as possible.

The operation of the ESD clamp device will be described usingFIG. 2b. The drain-to-source current (Ids) versus drain-to-source voltage (Vds) response of the MOS transistor (in linear scale) is illustrated inFIG. 2b. At low voltages the MOS transistor behaves like a conventional MOS transistor. Hence, when the gate bias is turned on due to the initial transient of the RC circuit, a drain-to-source current flows. Hence, the NOR gate40outputs a low signal to the inverting buffer stage(s)30if the capacitor20is charging in response to an ESD pulse. The inverting buffer stage(s)30outputs an amplified high signal on the gate of the MOS transistor100forming a conductive path between power supply line (Vdd), and substrate voltage line (Vss).

After this initial transient response of the ABST clamp which is determined by the RC timer circuit, the high electric field across the drain and the substrate junction breaks down the junction due to avalanche breakdown. Consequently, this pulls up the local substrate potential of the MOS transistor100. As the substrate node of the MOS transistor100is coupled to the second input of the NOR gate40, this results in a transfer of the local substrate potential to the second input of the NOR gate40. Again as the NOR gate40outputs a low signal to the inverting buffer stage(s)30, and the inverting buffer stage(s)30outputs an amplified high signal on the gate of the MOS transistor100. Thus, the substrate potential is amplified into a gate bias of the MOS transistor100. The high gate bias preserves the inversion region of the MOS transistor100and maintains the conductive path between power supply line (Vdd), and substrate voltage line (Vss). The conduction through the drain/substrate junction due to moderate avalanche breakdown stops when the drain voltage drops after the duration of the ESD pulse. Hence, the substrate voltage drops to a lower value closer to the substrate voltage line (Vss). As the substrate is coupled to the NOR gate40through the pickup node P, the gate bias on the MOS transistor100drops and the MOS transistor100stops conducting.

Thus, the auto-biased self-timed ESD clamp uses RC-triggering only for providing a bias signal for initial turn like an RCMOS. The gate bias voltage for the main portion of the ESD pulse is generated by the clamp itself. After RC-time out, the clamping device is operated at the transition between MOS-mode and bipolar-mode which results in an elevated substrate potential. The clamp remains in conducting mode in a self-sustaining way through the duration of the ESD pulse, after which the clamp turns off.

In contrast to prior art, the ABST clamp does not pump the substrate and does not feed back its own gate bias. Rather, the ABST clamp generates its own gate biasing by feeding back its own substrate potential. As the device is operated by moderate avalanche breakdown and at moderately higher clamping voltages at the transition region from MOS conduction to parasitic bipolar conduction, the ABST clamp is immune to false triggering during normal circuit operating conditions, which are substantially lower than supply voltage Vdd. In various embodiments, silicided source/drain regions are formed on the MOS transistor100without the need for blocking the formation of silicide regions. This saves an extra mask step along with the related processing saving area and processing costs.

FIG. 3, which includesFIGS. 3aand3b, illustrates the detailed operation of an auto biased self timing ESD clamp, in accordance with embodiments of the invention.

Circuit simulations of a 2 kV human body model (HBM) ESD discharge illustrate the operation and advantage of the Auto-Biased Self-Timed (ABST) MOS Clamp, in accordance to embodiments of the invention. InFIGS. 3aand3b, the ABST clamp is compared against a RCMOS clamp as described inFIG. 1a.

The ABST clamp demonstrates an improved gate bias voltage V(Gate) over the RCMOS clamp during the entire duration of the ESD pulse and results in a better clamping as seen by the reduced drain voltage (vdd). The simulation is performed using a RC timer circuit with a time constant of 20 ns which is much smaller than the time constant of a human body model (HBM) ESD pulse, which is typically about 150 ns. For the simulation illustrated inFIG. 3, the gate length of the MOS transistor100is about 230 nm, and the width is about 1000 μm.

The drawback of the reference design is clearly visible inFIG. 3a. As illustrated inFIG. 3a, after the time constant of the RC timer circuit, the gate voltage V(Gate) of the MOS transistor100drops. The increasing drain voltage V(vdd) results in the break down of the drain-substrate junction due to a hard avalanche breakdown resulting in a breakdown current I(Ddb). In contrast, the ABST clamp device shows a much smaller drop in gate voltage V(Gate) resulting in continued flow of source/drain current (Id). Hence, an effective clamping of the drain voltage is achieved.

FIG. 3billustrates the robustness of the ABST design by comparing the reference RCMOS clamp and the ABST clamp using two different RC timer circuits. The time constant of the first RC timer circuit is about 10 ns, whereas the time constant of the second RC timer circuit is about 20 ns. This is visible in the curves illustrating the gate voltage of the RCMOS clamp (labeled “RC time out”). The actual duration of the gate voltage is about 35 ns and 55 ns for the first and the second RC timer circuits respectively for reference RCMOS. The gate voltage of the ABST clamp is much higher, and almost indistinguishable for both time constants. Hence, as expected, the drain voltage clamping is also similar for the ABST clamps using the different RC timer circuits. Unlike the RCMOS clamps, the voltage clamping of the ABST clamp is independent of the RC time constant of the RC circuits illustrating the robust applicability and proof of the concept of auto biasing in accordance with an embodiment of the invention.

FIG. 4illustrates an embodiment of the ESD clamp device in accordance with an embodiment of the invention. In this embodiment, the NOR gate40and the inverting buffers30are replaced by an OR gate42. Hence, the operation of this device is similar to that described above.

FIG. 5illustrates an embodiment of a circuit implementation of the invention using ABST techniques discussed inFIG. 2. The ABST clamp comprises a NOR gate40comprising a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2. A third PMOS transistor P3and a third NMOS transistor N3form an inverting buffer stage. The RC timer circuit comprises a capacitor20and a resistor10, the RC timer coupled to the NOR gate40and the power supply lines as described above with respect toFIG. 2. The MOS transistor100comprises a fourth NMOS transistor N4. The fourth NMOS transistor N4, in various embodiments, comprises a large width transistor. In various embodiments, the gate length of the fourth NMOS transistor N4is a minimum length transistor. In one embodiment, the gate length of the fourth NMOS transistor N4is about 50 nm to about 100 nm. The width of the fourth NMOS transistor N4is at least 10 μm in one embodiment.

FIG. 6illustrates a simplified embodiment of a circuit implementation of the invention using ABST techniques discussed inFIG. 2.

Unlike the embodiment ofFIG. 2a, in this embodiment, the NOR gate ofFIG. 2ais replaced by an inverting buffer stage. Hence, the circuit comprises a first inverting buffer stage comprising a first PMOS transistor P1and a first NMOS transistor N1, and a second inverting buffer stage comprising a second PMOS transistor P2and a second NMOS transistor N2(MOS transistor100). In this embodiment, some of the initial trigger signal of the RC circuit is also used for generating a substrate bias. After timeout of the RC circuit, the circuit draws a signal from the local substrate pickup and generates the gate bias for the MOS transistor100.

FIG. 7illustrates an embodiment of a circuit implementation of the invention using ABST techniques discussed inFIG. 2. This embodiment is similar to that shown inFIG. 5, but includes additional inverting buffer stages.

As described with respect toFIG. 5, the NOR gate comprises a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2. A first inverting stage comprising a third PMOS transistor P3and a third NMOS transistor N3is coupled to the NOR gate.

UnlikeFIG. 5, two additional inverting buffer stages are coupled to the gate of the MOS transistor100. Hence, the gate bias on the MOS transistor100is amplified more than the embodiment of theFIG. 5. A second inverting stage comprising a fourth PMOS transistor P4and a fourth NMOS transistor N4is coupled to the first inverting stage. A third inverting stage comprising a fifth PMOS transistor P5and a fifth NMOS transistor N5is coupled to the second inverting stage. The third inverting stage is coupled to the MOS transistor100. Although in this embodiment two additional inverting buffer stages are added, in other embodiments, more number of inverting buffer stages may be added. In various embodiments, the inverting buffer stages are added in increments of two till the required gate signal amplification is achieved.

FIG. 8illustrates an embodiment of a circuit implementation of the invention using ABST techniques discussed inFIG. 2. In various embodiments, the capacitance required for the triggering the ABST clamp is small due to the dependence on the RC circuit only for the initial triggering. This is in contrast to the RCMOS devices that require large capacitors. Hence, in some embodiments, the intrinsic capacitance of the MOS transistor100is used as the initial triggering capacitor. During normal operating conditions, the third NMOS transistor N3is “on” acting as a resistor, similar to the resistor10of the RC timer circuit.

Referring toFIG. 8, the drain-gate capacitance (Cdg) of the MOS transistor100is used similar to the RC timer circuit. The drain-gate capacitance (Cdg) arises primarily due to the overlap of the drain extension regions under the gate electrode of the MOS transistor100. In various embodiments, the MOS transistor100can be designed to vary this intrinsic capacitance also called Miller capacitance. Consequently using the embodiment, the external RC circuit is eliminated.

FIG. 9illustrates an embodiment of the ABST clamp device using a PMOS transistor as the clamping transistor. Although the embodiments ofFIGS. 5-8are described using a NMOS transistor as the MOS clamp transistor, other embodiments may use PMOS transistors.

Referring toFIG. 9, the placement of the resistor10and the capacitor20is exchanged relative toFIG. 2a. Further, the NOR gate40inFIG. 2ais replaced by a NAND gate43. The substrate resistance Rsub to the substrate voltage line VSS is replaced with the nwell resistance Rnwell to the power supply line VDD. Thus, the NAND gate43is coupled to the inverting buffers30forming an AND logic block.

In particular, a first plate of the capacitor20is coupled to the power supply line VDD through a resistor10and a second plate of the capacitor20is coupled to the substrate voltage line VSS. The first input of the NAND gate43is coupled to the first plate of the capacitor20, while a second input of the NAND gate43is coupled to the local substrate (nwell) of the MOS transistor100through a pickup node P. The coupling of the local nwell potential of the MOS transistor100to the second input of the NAND gate43forms the auto biasing circuit.

FIGS. 10 and 11describe the layout of the MOS transistor used in various embodiments described inFIGS. 2-9.FIG. 10, which includes10a-10c, illustrates the layout of MOS transistor in accordance with an embodiment of the invention.

FIG. 10aillustrates a top view of an embodiment of the MOS transistor100as described in, for example,FIG. 2.FIGS. 10band10cillustrate cross sectional views ofFIG. 10aaccording to alternate embodiments of the invention.

Referring toFIG. 10a, the MOS transistor100(a NMOS transistor as an example) comprises a first ring120(for example, a p type region) coupled to a standard substrate potential node. A second ring130comprising an n type region is disposed around the first ring120. In various embodiments, the second ring130is floating or coupled to a reference potential. A gate150(for example, U shaped gate) is disposed centrally forming the MOS transistor100. The various regions are contacted using contacts160. Further, source (S), and drain (D) regions of the MOS transistor100are illustrated in the top view. In various embodiments, the number or transistor fingers can vary, and in one embodiment determined by the targeted ESD hardness of the clamp device.

The MOS transistor100additionally comprises a pickup region140(a third ring) disposed between the gate150and the second ring130(n-well). In various embodiments, the pickup region140comprises any suitable shape. The pickup region140(e.g. a p type doped region in the shape of a ring) is coupled to the substrate and comprises contacts that form the substrate pickup nodes. In various embodiments, the pickup region140comprises a p+ region for efficient pick up of the substrate potential without resistive losses. The pick up region140is shielded from the first ring120by the second ring130because the second ring is floating or coupled to a fixed potential node (for example, drain voltage Vdd).

The cross section views ofFIG. 10aare illustrated inFIGS. 10band10cwhich illustrate alternate embodiments.FIG. 10billustrates a dual well process, whereasFIG. 10cillustrates a triple well process. Embodiments of the invention described above may include any of the cross sections illustrated inFIGS. 10band10c.

The MOS transistor100comprises source regions170and drain regions180separated by channel regions disposed in a first well region141(p well region for a NMOS). The first well region141is disposed on a lower doped substrate142. For example, in one embodiment, the lower doped substrate142comprises a deep well region formed in a substrate, in other embodiments the lower doped substrate142comprises the doping of the substrate before fabrication, for example, a p type doped wafer in one embodiment. The first well region141is formed within the lower doped substrate142. The first well region141comprises a same type of doping, in one embodiment.

A first ring120comprising a heavily doped region (p+doping for a NMOS) is disposed on the first well region141as illustrated inFIG. 10a. A ring shaped second well region131is disposed under the second ring130(seeFIG. 10a). The second well region131is disposed adjacent the first well region141and separates the first well region141into a first portion and a second portion. The second well region131comprises an n−doping for a NMOS transistor. A second ring130is disposed in the second well region131. A pickup region140comprising a heavily doped region (p+doping for a NMOS) is disposed on the first well region141as illustrated inFIG. 10a. The second ring130is thus disposed between the first ring120and the pickup region140. The second ring130shields the first ring120from the active part of the substrate (e.g., the source/substrate junction of the MOS transistor100). Thus, the second ring130enables the pickup region140to tap into the substrate potential more efficiently.

In the dual well process illustrated inFIG. 10b, the substrate of the MOS transistor100is coupled to the body or substrate contact (first ring120) through a lower doped region and hence through an effective substrate resistance Rsub. This coupling of the substrate to the substrate potential line VSS is also depicted in various embodiments in above Figures (e.g.FIGS. 4-8illustrate this embodiment as effective substrate resistance Rsub). In various embodiments, the first well region141is about 0.5 μm to about 5 μm deep, and about 2 μm in one embodiment.

In contrast, in the triple well design (FIG. 10c) a second well region143is formed disposed within the lower doped substrate142. The second well region143is deeper than the first well region141and comprises an opposite type doping. Hence, the triple well design creates an isolated portion of the first well region141. The isolated first well region141is shielded from the substrate contact (first ring120) by second ring130laterally and vertically by the second well region143. Hence, this results in optimal pickup of the potential under the active MOS device.

FIG. 11illustrates an alternate embodiment of the top view of MOS transistor described with respect toFIG. 10a. UnlikeFIG. 10a, the pickup region140is placed centrally while the gate150is disposed between source regions170and drain regions180on either side of the device. As the pickup region140is placed centrally additional shielding rings (example, second ring ofFIG. 10a) are not necessary resulting in area savings. Although this layout is more efficient, a decrease in efficiency of pickup is likely. In some embodiments, a lower efficiency of the potential pickup may be acceptable for the gains in area.

In various embodiments, the ESD clamp device described above comprises a device with a low capacitance unlike the RCMOS clamp illustrated for example inFIG. 1a. Hence, in various embodiments, the ESD clamp device is used for protection of local input/output (I/O) pads. In various embodiments, the ABST clamp described above is applied to CMOS bulk, SOI technologies with substrate or body contacts as well as bipolar and/or mixed signal technologies.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.