INTEGRATED CIRCUIT INCLUDING THROUGH-SILICON VIA AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT

An integrated circuit may include a bit cell array including a plurality of bit cells and a peripheral region including a peripheral circuit. The peripheral region may include a plurality of devices over a substrate, at least one pattern configured to provide a first voltage to at least one of the plurality of devices, at least one power line extending under the substrate, and at least one first via passing through the substrate in a vertical direction in the peripheral region and electrically connecting the at least one pattern to the at least one power line.

CROSS-REFERENCE TO RELATED APPLICATION

FIELD

The inventive concept relates to an integrated circuit, and more particularly, to an integrated circuit including a through silicon via and a method of manufacturing the integrated circuit.

BACKGROUND

Integrated circuits may include devices and patterns for supplying power to the devices. The patterns for supplying the power to the devices may be regularly arranged for stably supplying the power to the devices. As semiconductor processes advance, the size of devices may decrease and routing for signals may be affected by patterns for supplying power.

SUMMARY

The inventive concept provides an integrated circuit including a through silicon via for supplying power to devices and a method of manufacturing the integrated circuit.

According to an aspect of the inventive concept, there is provided an integrated circuit including a plurality of gate lines extending in a first horizontal direction over a substrate, first to fourth active patterns extending in a second horizontal direction intersecting the first horizontal direction over the substrate, a first pattern extending in the second horizontal direction over a region between the first active pattern and the second active pattern, the first pattern being configured to receive a first voltage, a second pattern extending in the second horizontal direction over a region between the third active pattern and the fourth active pattern, the second pattern being configured to receive a second voltage, at least one first via contacting the first pattern and electrically connecting the first pattern to bodies of devices comprising at least a portion of the first active pattern or the second active pattern, and at least one second via passing through the substrate in a vertical direction and electrically connecting the second pattern to a first power line extending under the substrate.

According to another aspect of the inventive concept, there is provided an integrated circuit including a plurality of gate lines extending in a first horizontal direction over a substrate, first to fourth active patterns extending in a second horizontal direction intersecting the first horizontal direction over the substrate, a first pattern extending in the second horizontal direction over a region between the first active pattern and the second active pattern, the first pattern being configured to receive a first voltage, a second pattern extending in the second horizontal direction over a region between the third active pattern and the fourth active pattern, the second pattern being configured to receive a second voltage, a first via passing through the substrate in a vertical direction and electrically connecting the first pattern to a first power line extending under the substrate, and a second via passing through the substrate in the vertical direction and electrically connecting the second pattern to a second power line extending under the substrate.

According to another aspect of the inventive concept, there is provided an integrated circuit including a bit cell array including a plurality of bit cells and a peripheral region including a peripheral circuit, wherein the peripheral region includes a plurality of devices over a substrate, at least one pattern configured to provide a first voltage to at least one of the plurality of devices, at least one power line extending under the substrate, and at least one first via passing through the substrate in a vertical direction in the peripheral region and electrically connecting the at least one pattern to the at least one power line.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIGS.1A and1Bare diagrams illustrating examples of an integrated circuit according to embodiments. Hereinafter, repeated descriptions ofFIGS.1A and1Bmay be omitted.

Herein, an X-axis direction may be referred to as a first horizontal direction, a Y-axis direction may be referred to as a second horizontal direction, and a Z-axis direction may be referred to as a vertical direction. The terms “first,” “second,” etc. may be used herein merely to distinguish one element, component, region, or direction from another. A plane based on an X axis and a Y axis may be referred to as a horizontal surface, an element relatively arranged in a +Z direction compared to another element may be referred to as being over the other element, and an element relatively arranged in a −Z direction compared to another element may be referred to as being under the other element. Also, an area of an element may denote a size occupied by the element in a surface parallel to a horizontal surface, and a width of an element may denote a dimension thereof in a direction perpendicular to a direction in which the element extends. A surface exposed in or normal to the +Z direction may be referred to as a top surface, a surface exposed in or normal to the −Z direction may be referred to as a bottom surface, and a surface exposed in or normal to a ±X direction or a ±Y direction may be referred to as a side surface. For convenience of illustration, only some layers may be illustrated in the drawings, and a via connecting an upper pattern with a lower pattern may be illustrated for understanding despite being disposed under the upper pattern. Also, a pattern including a conductive material like a pattern of a wiring layer may be referred to as a conductive pattern, or may be simply referred to as a pattern. The terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated elements, but do not preclude the presence of additional elements. The term “and/or” includes any and all combinations of one or more of the associated listed items.

Referring toFIG.1A, an integrated circuit10amay include a wiring layer11aand a substrate12a. Devices (for example, transistors) may be formed over the substrate12a, and examples of the devices are described below with reference toFIGS.3A to3D. The wiring layer11amay be disposed over the devices, and patterns including a conductive material may be formed in the wiring layer11a. For example, as illustrated inFIG.1A, patterns (herein, may be referred to as signal patterns) for input signals and/or output signals of the devices may be formed in the wiring layer11a, and patterns (herein, may be referred to as power patterns) for supplying power to the devices may be formed in the wiring layer11a. In some embodiments, the patterns formed in the wiring layer11amay include metal, and the wiring layer11amay be referred to as a metal layer. The integrated circuit10amay include a plurality of wiring layers, and patterns formed in each of adjacent wiring layers may be electrically connected with (also referred to as electrically connected to) each other through a via. For example, the integrated circuit10amay include at least one wiring layer between the wiring layer11aand the substrate12aand may include at least one wiring layer on the wiring layer11a.

A supply voltage (for example, a positive supply voltage and/or a negative supply voltage) may be applied to power patterns. For example, the devices may receive the supply voltage, applied to a pad over a plurality of wiring layers, through patterns formed in each of the plurality of wiring layers. As described above, a structure where the supply voltage is provided from above the substrate12amay be referred to as a front-side power delivery network (FSPDN). In some embodiments, power patterns may be regularly arranged in the wiring layer11aso that power is stably supplied to the devices, and signal patterns may be disposed in a region, where the power patterns are not provided, of the wiring layer11a. For example, as illustrated inFIG.1A, the power patterns may extend in parallel in the Y-axis direction at certain intervals in the wiring layer11a, and the signal patterns may extend in the Y-axis direction between the power patterns in the wiring layer11a. As a semiconductor process advances, a size of devices formed on the substrate12amay decrease, and thus, it may not be easy to form signal patterns for routing input signals and output signals of the devices and the power patterns may increase routing congestion.

Referring toFIG.1B, an integrated circuit10bmay include a wiring layer11b, a substrate12b, and a backside wiring layer13b. Devices (for example, transistors) may be formed over the substrate12b. The wiring layer11bmay be disposed over the devices, and the backside wiring layer13bmay be disposed under the substrate12b. The wiring layer11bmay be referred to as a front-side wiring layer, so as to be differentiated from the backside wiring layer13b. As illustrated inFIG.1B, signal patterns may be formed in the wiring layer11b, and power patterns may be formed in the backside wiring layer13b. The power patterns may be omitted in the wiring layer11b, and the signal patterns may be disposed in a region where the power patterns are omitted. Therefore, the integrated circuit10bofFIG.1Bmay provide routability which is greater than that of the integrated circuit10aofFIG.1A.

To supply power to a device by using the power patterns formed in the backside wiring layer13b, the integrated circuit10bmay include a through silicon via (TSV). As described below with reference toFIG.2, a TSV may be connected with the backside wiring layer13band may be connected with a pattern formed in a wiring layer between the wiring layer11band the substrate12b. Elements or components described herein as “connected” to or with one another may be physically and/or electrically connected. Elements or components that are “directly” on or connected to or with one another may be free of intervening elements or components therebetween. Accordingly, the supply voltage may be supplied to devices through the TSV from the power pattern formed in the backside wiring layer13b. As described above, a structure where the supply voltage is provided from a portion under the substrate12amay be referred to as a backside power delivery network (BSPDN). Herein, the power pattern formed in the backside wiring layer13bmay be referred to as a power line.

In some embodiments, the TSV may be connected with a pattern formed in a first wiring layer (for example, an M1layer) closest to the substrate12b. Patterns formed in the first wiring layer may have a resistance which is higher than that of patterns formed in the other wiring layers, and thus, a device disposed at a relatively long distance from the TSV may receive a decreased positive supply voltage and/or an increased negative supply voltage. As described below with reference to the drawings, the integrated circuit10bmay include TSVs which are disposed so that power is stably supplied to the devices, and thus, the performance and reliability of the integrated circuit10bmay be improved. Also, an additional area for placing TSVs may be omitted, and an increase in area of the integrated circuit10bmay be limited. Also, due to the power patterns disposed in the backside wiring layer13b, routing resources may increase in front-side wiring layers including the wiring layer11b, and thus, routing congestion may be alleviated or removed in the integrated circuit10b.

FIG.2is a diagram illustrating a layout of an integrated circuit20according to an embodiment. The upper drawing ofFIG.2is a plan view illustrating a layout of the integrated circuit20as seen in a −Z-axis direction, and the lower drawing ofFIG.2is a cross-sectional view illustrating a cross-sectional surface, taken along line X1-X2, of the layout of the integrated circuit20.

Referring toFIG.2, the integrated circuit20may include gate lines (or gate electrodes or gates) extending in an X-axis direction and may include p-channel field effect transistor (PFET) regions and n-channel field effect transistor (NFET) regions extending in a Y-axis direction. As illustrated inFIG.2, a pitch of the gate lines may be referred to as a contact poly pitch (CPP). As described below with reference toFIGS.3A to3C, in each of the PFET regions and the NFET regions, portions protruding in a +Z-axis direction and extending in the Y-axis direction may configure an active region of a transistor, and herein, may be referred to as an active pattern. A source/drain may be formed at each of both sides of the gate line, a contact may be formed on the source/drain, and a channel may be formed between source/drains under the gate line. A via of a first via layer VO may be disposed on the contact and may be connected with the contact and a pattern of a first wiring layer M1. For example, as illustrated inFIG.2, a via V21may be connected with a contact C21and a second pattern M22.

The integrated circuit20may include a first power line PL21and a second power line PL22, which extend in the Y-axis direction under a substrate SUB. For example, as illustrated inFIG.2, the first power line PL21may extend in the Y-axis direction under the PFET region, and a positive supply voltage VDD may be applied to the first power line PL21. Also, the second power line PL22may extend in the Y-axis direction under the NFET region, and a negative supply voltage VSS may be applied to the second power line PL22. A backside interlayer dielectric (BILD) may be formed between the first power line PL21and the second power line PL22.

The integrated circuit20may include a TSV which passes through the substrate SUB and is connected with a power line. For example, as illustrated inFIG.2, a TSV T21may pass through the PFET region and the substrate SUB and may be connected with the first power line PL21and a first pattern M21of the first wiring layer M1. Accordingly, the positive supply voltage VDD may be applied to the first pattern M21, and the devices may receive the positive supply voltage VDD from the first pattern M21. Similarly, the integrated circuit20may include a TSV which is connected with the second power line PL22and the second pattern M22. Accordingly, the negative supply voltage VSS may be applied to the second pattern M22, and the devices may receive the negative supply voltage VSS from the second pattern M22. For example, as illustrated inFIG.2, a source/drain SD may receive a negative supply voltage from the second pattern M22through the via V21and the contact C21. In one embodiment, the power lines (e.g., the first power line PL21and the second power line PL22) used to provide power from the backside of the substrate as illustrated inFIG.2may be referred to as backside power rails (BSPR).

FIGS.3A to3Dare diagrams illustrating examples of a device according to embodiments. For example,FIG.3Aillustrates a fin field effect transistor (FinFET)30a,FIG.3Billustrates a gate-all-around field effect transistor (GAAFET)30b,FIG.3Cillustrates a multi-bridge channel field effect transistor (MBCFET)30c, andFIG.3Dillustrates a vertical field effect transistor (VFET)30d. For convenience of illustration,FIGS.3A to3Cillustrate a shape where one of two source/drain regions are removed, andFIG.3Dillustrates a cross-sectional surface taken along a line of the VFET30dand illustrates a surface which is parallel to a plane including an X axis and a Z axis and passes through a channel CH of the VFET30d.

Referring toFIG.3A, the FinFET30amay be configured by a fin-shaped active pattern extending in the Y-axis direction between shallow trench isolations (STIs) and a gate G extending in the X-axis direction. A source/drain S/D may be formed at each of both sides of the gate G, and thus, a source and a drain may be apart from each other in the Y-axis direction. An insulation layer may be formed between the channel CH and the gate G. In some embodiments, the FinFET30amay be configured by the gate G and a plurality of active patterns which are apart from each other in the Y-axis direction.

Referring toFIG.3B, the GAAFET30bmay be configured by active patterns (i.e., nanowires), which are apart from one another in a Z-axis direction and extend in the Y-axis direction, and a gate G which extends in the X-axis direction. A source/drain S/D may be formed at each of both sides of the gate G, and thus, a source and a drain may be apart from each other in the Y-axis direction. An insulation layer may be formed between the channel CH and the gate G. The number of nanowires included in the GAAFET30bis not limited to the illustration ofFIG.3B.

Referring toFIG.3C, the MBCFET30cmay be configured by active patterns (i.e., nanosheets), which are apart from one another in a Z-axis direction and extend in the Y-axis direction, and a gate G which extends in the X-axis direction. A source/drain S/D may be formed at each of both sides of the gate G, and thus, a source and a drain may be apart from each other in the Y-axis direction. An insulation layer may be formed between the channel CH and the gate G. The number of nanosheets included in the MBCFET30cis not limited to the illustration ofFIG.3C.

Referring toFIG.3D, the VFET30dmay include a top source/drain T_S/D and a bottom source/drain B_S/D, which are apart from each other in a Z-axis direction with a channel CH therebetween. The VFET30dmay include a gate G which surrounds a perimeter of the channel CH, between the top source/drain T_S/D and the bottom source/drain B_S/D. An insulation layer may be formed between the channel CH and the gate G.

Hereinafter, an integrated circuit including the FinFET30aor the MBCFET30cis mainly described, but devices included in the integrated circuit are not limited to the embodiments ofFIGS.3A to3D. For example, the integrated circuit may include a ForkFET having a structure where nanosheets for a P-type transistor are separated from nanosheets for an N-type transistor by a dielectric wall, and thus, the N-type transistor is closer to the P-type transistor. Also, the integrated circuit may include a bipolar junction transistor as well as an FET such as a complementary FET (CFET), a negative capacitance FET (NCFET), or a carbon nanotube FET (CNTFET).

FIGS.4A and4Bare plan views illustrating layouts of an integrated circuit according to embodiments. For example, the plan view ofFIG.4Aillustrates an integrated circuit40aincluding a structure for biasing a well W41, and the plan view ofFIG.4Billustrates an integrated circuit40bincluding a TSV and a structure for biasing a well W41. Hereinafter, repeated descriptions ofFIGS.4A and4Bmay be omitted.

Referring toFIG.4A, the integrated circuit40amay include first to fifth gate lines G41to G45extending in an X-axis direction, and may include a first active pattern A41and a second active pattern A42each extending in a Y-axis direction. In other words, the active patterns A41, A42may be adjacent one another in the X-axis direction and may extend along the Y-axis direction (also referred to herein as extending side-by-side in the Y-axis direction). The integrated circuit40amay include a first pattern M41and a second pattern M42of a first wiring layer M1extending in the Y-axis direction over the first to fifth gate lines G41to G45. The integrated circuit40amay include a well W41extending in the Y-axis direction under the second active pattern A42. The well W41may have a conductive type which differs from a portion (i.e., a substrate) under the first active pattern A41. Accordingly, the first active pattern A41and the second active pattern A42may respectively configure complementary transistors. For example, the well W41and the substrate may be respectively doped N type and P type, and thus, an NFET may be configured by the first active pattern A41and a PFET may be configured by the second active pattern A42. Hereinafter, it may be assumed that the well W41is doped N type, and it may be assumed that the substrate is doped P type.

Each of the substrate and the well W41may be biased. For example, the well W41may be biased to a positive supply voltage VDD, and the substrate may be biased to a negative supply voltage VSS. The integrated circuit40amay include a structure for biasing each of the well W41and the substrate, and a corresponding structure may be referred to as a tap structure. For example, the positive supply voltage VDD may be applied to the second pattern M42, and a fifth via V45and a sixth via V46may be connected with the second active pattern A42through contacts. In the second active pattern A42, a source/drain may be doped N type, and thus, the positive supply voltage VDD may be supplied to the well W41. In some embodiments, the negative supply voltage VSS may be applied to the first pattern M41.

In a portion of the second active pattern A42configuring a PFET, the source/drain may be doped P type. Therefore, the second active pattern A42may be cut (e.g., may include a discontinuity or may be removed) at a boundary between a portion doped P type and a portion doped N type. For example, as illustrated inFIG.4A, the second active pattern A42may be removed in a third region R43and a fourth region R44. Due to a semiconductor process of manufacturing the integrated circuit40a, it may not be easy to dope only the source/drain of the second active pattern A42ofFIG.4Aas an N type. Accordingly, the semiconductor process may dope, as an N type, a source/drain of the first active pattern A41adjacent to the second active pattern A42and the source/drain of the second active pattern A42. As a result, the integrated circuit40amay include a bias region BR for biasing the well W41and a dummy region DR adjacent to the bias region BR. The first active pattern A41in the dummy region DR may be cut in the first region R41and the second region R42. In some embodiments, sources/drains of the first active pattern A41may be respectively connected with the first to fourth vias V41to V44through contacts, and thus, the negative supply voltage VSS may be applied to the sources/drains of the first active pattern A41.

Referring toFIG.4B, the integrated circuit40bmay include first to fifth gate lines G41to G45extending in an X-axis direction and may include a first active pattern A41and a second active pattern A42each extending in a Y-axis direction. The integrated circuit40bmay include a first pattern M41and a second pattern M42of a first wiring layer M1extending in the Y-axis direction over the first to fifth gate lines G41to G45. The integrated circuit40bmay include a well W41extending in the Y-axis direction under the second active pattern A42. The first active pattern A41may be removed in a first region R41and a second region R42, and the second active pattern A42may be removed in a third region R43and a fourth region R44.

In some embodiments, the integrated circuit40bmay include a TSV region TR adjacent to a bias region BR and may include at least one TSV in the TSV region TR. For example, as illustrated inFIG.4B, the integrated circuit40bmay include the bias region BR corresponding to the bias region BR ofFIG.4Aand may include the TSV region TR which differs from the dummy region DR ofFIG.4A. First to fourth TSVs T41to T44may be disposed in the TSV region TR, and each of the first to fourth TSVs T41to T44may be connected with a power line extending under the substrate and the first pattern M41. For example, a negative supply voltage VSS may be applied to the power line, and thus, the first pattern M41may receive the negative supply voltage VSS through the first to fourth TSVs T41to T44. As illustrated inFIG.4B, each of the first to fourth TSVs T41to T44may be disposed between two adjacent gate lines and may have a diameter which is less than a CPP. Herein, each of the first to fourth TSVs T41to T44may be referred to as a nano TSV.

As described above with reference toFIG.4A, due to a semiconductor process, a dummy region DR adjacent to the bias region BR may be needed. The integrated circuit40bofFIG.4Bmay use, as the TSV region TR, the dummy region DR adjacent to the bias region BR, and thus, may have the same area as that of the integrated circuit40aofFIG.4Aand may include a TSV which is connected with the power line.

FIGS.5A to5Care plan views illustrating layouts of an integrated circuit according to embodiments. For example, the plan view ofFIG.5Aillustrates an integrated circuit50aincluding a structure (i.e., a tap structure) for biasing a well W51, the plan view ofFIG.5Billustrates an integrated circuit50bincluding a TSV and a structure for biasing a well W51, and the plan view ofFIG.5Cillustrates an integrated circuit50cincluding a TSV. Hereinafter, repeated descriptions ofFIGS.5A to5Cmay be omitted.

Referring toFIG.5A, the integrated circuit50amay include first to fifth gate lines G51to G55extending in an X-axis direction and may include a first active pattern A51and a second active pattern A52each extending in a Y-axis direction. The integrated circuit50amay include a first pattern M51and a second pattern M52of a first wiring layer M1extending in the Y-axis direction on the first to fifth gate lines G51to G55. The integrated circuit50amay include a well W51which extends in the Y-axis direction under the first active pattern A51and the second active pattern A52. As described above with reference toFIG.4A, the first active pattern A51may be removed in a first region R51and a second region R52, and the second active pattern A52may be removed in a third region R53and a fourth region R54.

A positive supply voltage VDD may be applied to the first pattern M51and the second pattern M52, the first via V51and the second via V52may be connected with a source/drain of the first active pattern A51through contacts, and the third via V53and the fourth via V54may be connected with a source/drain of the second active pattern A52through contacts. In the first active pattern A51and the second active pattern A52, a source/drain may be doped N type, and thus, a positive supply voltage VDD may be supplied to the well W51. That is, the integrated circuit50amay include a first bias region BR1and a second bias region BR2for biasing the well W51, and the first bias region BR1may be adjacent to the second bias region BR2.

Referring toFIG.5B, the integrated circuit50bmay include first to fifth gate lines G51to G55extending in an X-axis direction and may include a first active pattern A51and a second active pattern A52each extending in a Y-axis direction. The integrated circuit50bmay include a first pattern M51and a second pattern M52of a first wiring layer M1extending in the Y-axis direction over the first to fifth gate lines G51to G55. The integrated circuit50bmay include a well W51which extends in the Y-axis direction under the first active pattern A51and the second active pattern A52. The first active pattern A51may be removed in a first region R51and a second region R52, and the second active pattern A52may be removed in a third region R53and a fourth region R54.

In some embodiments, the integrated circuit50bmay include a TSV region TR adjacent to a bias region BR and may include at least one TSV in the TSV region TR. For example, as illustrated inFIG.5B, the integrated circuit50bmay include the bias region BR corresponding to the second bias region BR2ofFIG.5Aand may include the TSV region TR which differs from the first bias region BR1ofFIG.5A. A first TSV T51and a second TSV T52may be disposed in the TSV region TR, and the first TSV T51and the second TSV T52may be connected with a power line extending under a substrate and the first pattern M51. For example, a positive supply voltage VDD may be applied to the power line, and thus, the first pattern M51may receive the positive supply voltage VDD through the first TSV T51and the second TSV T52. As illustrated inFIG.5B, each of the first TSV T51and the second TSV T52may be a nano TSV.

Referring toFIG.5C, the integrated circuit50cmay include first to fifth gate lines G51to G55extending in an X-axis direction and may include a first active pattern A51and a second active pattern A52each extending in a Y-axis direction. The integrated circuit50cmay include a first pattern M51and a second pattern M52of a first wiring layer M1extending in the Y-axis direction on the first to fifth gate lines G51to G55. The integrated circuit50cmay include a well W51which extends in the Y-axis direction under the first active pattern A51and the second active pattern A52. The first active pattern A51may be removed in a first region R51and a second region R52, and the second active pattern A52may be removed in a third region R53and a fourth region R54.

In some embodiments, the integrated circuit50cmay include TSV regions adjacent to each other. For example, as illustrated inFIG.5C, the integrated circuit50cmay include a first TSV region TR1corresponding to the TSV region TR ofFIG.5Band may include a second TSV region TR2which differs from the second bias region BR2ofFIG.5Aand the bias region BR ofFIG.5B. A first TSV T51and a second TSV T52may be disposed in the first TSV region TR1, and the first TSV T51and the second TSV T52may be connected with a power line extending under a substrate and the first pattern M51. For example, a positive supply voltage VDD may be applied to the power line, and thus, the first pattern M51may receive the positive supply voltage VDD through the first TSV T51and the second TSV T52. Also, a third TSV T53and a fourth TSV T54may be disposed in the second TSV region TR2, and the third TSV T53and the fourth TSV T54may be connected with the power line extending under the substrate and the second pattern M52. For example, the positive supply voltage VDD may be applied to the power line, and thus, the second pattern M52may receive the positive supply voltage VDD through the third TSV T53and the fourth TSV T54. As illustrated inFIG.5C, each of the first to fourth TSVs T51to T54may be a nano TSV.

When structures for biasing the well W51are sufficient, as illustrated inFIGS.5B and5C, an integrated circuit may include TSVs in a TSV region. For example, as described below with reference toFIG.10, when it is determined that bias regions are sufficiently disposed in a layout of an integrated circuit in a design process of the integrated circuit, at least one bias region may be replaced with at least one TSV region and the integrated circuit may include a TSV in the at least one TSV region. Accordingly, a TSV may be provided without an increase in area of an integrated circuit, and thus, devices of the integrated circuit may be stably supplied with power.

FIG.6is a plan view illustrating a layout of an integrated circuit60according to embodiment. In describingFIG.6, descriptions which are the same as or similar to descriptions given above with reference to the drawings may be omitted.

Referring toFIG.6, the integrated circuit60may include first to seventh gate lines G61to G67extending in an X-axis direction and may include active patterns extending in a Y-axis direction. The integrated circuit60may include first to fourth patterns M61to M64of a first wiring layer M1extending in the Y-axis direction on gate lines. The integrated circuit60may include a well extending in the Y-axis direction under a corresponding active pattern.

In some embodiments, the integrated circuit60may include a TSV which passes through a gate line. For example, as illustrated inFIG.6, a first TSV T61and a third TSV T63may be disposed between the first gate line G61and the third gate line G63and may pass through the second gate line G62between the first gate line G61and the third gate line G63. Also, a second TSV T62and a fourth TSV T64may pass through the sixth gate line G66between the fifth gate line G65and the seventh gate line G67. Each TSV ofFIG.6may have a diameter which is greater than that of a nano TSV disposed between two gate lines (i.e., disposed in 1CPP) described above with reference to the drawings, and thus, may be disposed within 2CPP.

In some embodiments, the integrated circuit60may include a structure for biasing a well between TSVs. For example, a positive supply voltage VDD may be applied to the second pattern M62of the first wiring layer M1, and a first via V61and a second via V62each connected with the second pattern M62may provide the positive supply voltage VDD to a well W61through a contact and a source/drain doped N type. Therefore, as illustrated inFIG.6, a first TSV region TR1may be formed between the first gate line G61and the third gate line G63, a bias region BR may be formed between the third gate line G63and the fifth gate line G65, and a second TSV region TR2may be formed between the fifth gate line G65and the seventh gate line G67.

In some embodiments, active patterns adjacent to a TSV may be removed. For example, as illustrated inFIG.6, active patterns may be removed between the first gate line G61and the third gate line G63, and active patterns may be removed between the fifth gate line G65and the seventh gate line G67.

FIGS.7A and7Bare plan views illustrating layouts of an integrated circuit according to embodiments. For example, the plan views ofFIGS.7A and7Billustrate layouts of an integrated circuit including a memory cell.

Referring toFIG.7A, an integrated circuit70amay include memory cells for storing data and a peripheral circuit for controlling the memory cells. For example, as illustrated inFIG.7A, the integrated circuit70amay include a first bit cell array71and a second bit cell array72each including a plurality of bit cells. The bit cell may store at least one bit or may output the at least one stored bit, based on control by the peripheral circuit. In some embodiments, the bit cell may be a non-volatile memory cell like flash memory or resistive random access memory (RRAM), or may be a volatile memory cell like dynamic random access memory (DRAM) or static random access memory (SRAM). Examples of the first bit cell array71and the second bit cell array72are described below with reference toFIG.7B.

The integrated circuit70amay include a row decoder73, a first input/output (I/O) circuit74, a second I/O circuit75, and a control logic76, which are peripheral circuits. Herein, a region where a peripheral circuit is disposed may be referred to as a peripheral region. The row decoder73may control bit cells corresponding to an address in the first bit cell array71and the second bit cell array72, based on control by the control logic76. The first I/O circuit74and the second I/O circuit75may provide the first bit cell array71and the second bit cell array72with a signal corresponding to write data, or may generate a signal, corresponding to read data, from a signal output from each of the first bit cell array71and the second bit cell array72, based on control by the control logic76. The control logic76may control the row decoder73, the first I/O circuit74, and the second I/O circuit75in response to a signal (for example, a command) provided from the outside.

In some embodiments, the integrated circuit70amay include TSVs disposed in a peripheral circuit and/or a bit cell array. For example, as illustrated inFIG.7A, the TSVs may be disposed adjacent to edges of the first bit cell array71, the second bit cell array72, and the row decoder73. Also, the TSVs may be disposed in edges of the first I/O circuit74, the second I/O circuit75, and the control logic76, and moreover, may be disposed in inner portions apart from the edges thereof. As described above with reference to the drawings, a TSV may be disposed in a TSV region that replaces or is otherwise provided in a dummy region adjacent to a bias region, or may be disposed in a TSV region that replaces or is otherwise provided in the bias region (e.g., an excess bias region). Accordingly, inFIG.7A, TSVs disposed in a bit cell array and/or a peripheral circuit may not cause an increase in area of the integrated circuit70a. Examples of TSVs disposed in a bit cell array and/or a peripheral circuit in the integrated circuit70aare described below with reference toFIGS.8A to8C.

Referring toFIG.7B, an integrated circuit may include a bit cell array70b. As described above with reference toFIG.7A, the bit cell array70bmay include a plurality of bit cells, and a peripheral circuit may be disposed adjacent to the bit cell array70b. As illustrated inFIG.7B, the bit cell array70bmay include a first bit cell region77, a second bit cell region78, and an auxiliary region79. In some embodiments, the bit cell array70bmay include three or more bit cell regions.

Each of the first bit cell region77and the second bit cell region78may include a plurality of bit cells, and the auxiliary region79may include dummy cells and/or tap cells. As described above with reference to the drawings, the tap cell may bias a substrate or a well and may have the same dimension (for example, a length thereof in an X-axis direction and/or a length thereof in a Y-axis direction) as that of the bit cell. Also, the dummy cell may be adjacent to the tap cell and may have the same dimension (for example, a length thereof in the X-axis direction and/or a length thereof in the Y-axis direction) as that of the bit cell.

The bit cell array70bmay include TSVs disposed therein. For example, as illustrated inFIG.7B, the TSVs may be disposed in the auxiliary region79and may be disposed between the first bit cell region77and the second bit cell region78. In some embodiments, as described above with reference to the drawings, the TSV may be disposed in the dummy cell.

FIGS.8A to8Care plan views illustrating layouts of an integrated circuit according to embodiments. For example, the plan views ofFIGS.8A to8Cillustrate examples of layouts of an integrated circuit including a memory cell. Hereinafter,FIGS.8A to8Care described with reference toFIG.7A.

Referring toFIG.8A, an integrated circuit80amay include gate lines extending in an X-axis direction and may include active patterns extending in a Y-axis direction. The integrated circuit80amay include wells extending in the Y-axis direction under active patterns in a substrate. The integrated circuit80amay include patterns extending in the Y-axis direction in a first wiring layer M1on gate lines. In some embodiments, as illustrated inFIG.8A, the integrated circuit80amay include a bias region BR and a TSV region TR, which are alternately arranged. The bias region BR may include a via of a first via layer VO connected with a pattern of the first wiring layer M1, and the TSV region TR may include a TSV connected with the pattern of the first wiring layer M1. In some embodiments, a structure ofFIG.8Amay be in a peripheral region where the peripheral circuit is provided.

Referring toFIG.8B, an integrated circuit80bmay include gate lines extending in an X-axis direction and may include active patterns extending in a Y-axis direction. The integrated circuit80bmay include wells extending in the Y-axis direction under active patterns in a substrate. The integrated circuit80bmay include patterns extending in the Y-axis direction in a first wiring layer M1over gate lines. In some embodiments, the integrated circuit80bmay include a well extending under three or more adjacent active patterns and may include a TSV region TR and a bias region BR each overlapping the well. Components or layers described with reference to “overlap” in a particular direction may be at least partially obstructed by one another when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction. For example, as illustrated inFIG.8B, the integrated circuit80bmay include a well W81having a wide width (i.e., a long length thereof in the X-axis direction) and may include a TSV region TR and a bias region BR each overlapping the well W81. The bias region BR may include a via of a first via layer VO connected with a pattern of the first wiring layer M1, and the TSV region TR may include a TSV connected with the pattern of the first wiring layer M1. In some embodiments, a structure ofFIG.8Bmay be in an edge of a peripheral region.

Referring toFIG.8C, an integrated circuit80cmay include gate lines extending in an X-axis direction and may include active patterns extending in a Y-axis direction. The integrated circuit80cmay include wells extending in the Y-axis direction under active patterns in a substrate. The integrated circuit80cmay include patterns extending in the Y-axis direction in a first wiring layer M1on gate lines. In some embodiments, as illustrated inFIG.8C, the integrated circuit80cmay include a bias region BR and a TSV region TR, which are alternately arranged. The bias region BR may include a via of a first via layer VO connected with a pattern of the first wiring layer M1, and the TSV region TR may include a TSV connected with the pattern of the first wiring layer M1. In some embodiments, a structure ofFIG.8Cmay be in an edge of a peripheral region.

FIG.9is a flowchart illustrating a method of manufacturing an integrated circuit IC, according to an embodiment. In detail, the flowchart ofFIG.9illustrates an example of a method of manufacturing the integrated circuit IC including standard cells. The standard cell may be a unit of a layout included in the integrated circuit IC and may be simply referred to as a cell. The cell may include a transistor and may be designed to perform a predetermined function. For example, the standard cell may have a certain length in the X-axis direction inFIG.4A, and for example, may have a length corresponding to a pitch of the first pattern M41and the second pattern M42. As illustrated inFIG.9, the method of manufacturing the integrated circuit IC may include a plurality of operations S10, S30, S50, S70, and S90.

A cell library (or a standard cell library) D12may include information about the standard cells (for example, information about a function, a characteristic, a layout, etc.). In some embodiments, the cell library D12may define a tap cell and a dummy cell as well as function cells which generate an output signal from an input signal. In some embodiments, the cell library D12may define the tap cell including a bias region and a dummy region. Also, the cell library D12may define a standard cell including a TSV. As described above with reference to the drawings, in some embodiments, a standard cell including the TSV may have the same size as that of the tap cell and/or the dummy cell. Herein, a standard cell including the TSV may be referred to as a through cell.

A design rule D14may include requirements which the layout of the integrated circuit IC has to observe. For example, the design rule D14may include requirements such as a space between widths, a minimum width of a pattern, and a routing direction of a wiring layer, in the same layer. In some embodiments, the design rule D14may define a minimum separation distance in the same track of the wiring layer.

In operation S10, a logic synthesis operation of generating netlist data D13from register-transfer-level (RTL) data D11may be performed. For example, a semiconductor design tool (for example, a logic synthesis tool) may perform logic synthesis with reference to the cell library D12from the RTL data D11written in a hardware description language (HDL) such as a very high speed integrated circuit (VHSIC) hardware description language (VHDL) and Verilog and may generate the netlist data D13including a bitstream or a netlist. The netlist data D13may correspond to an input of place and routing (P&R) described below.

In operation S30, standard cells may be placed. For example, the semiconductor design tool (for example, a P&R tool) may place standard cells used in the netlist data D13with reference to the cell library D12. In some embodiments, the semiconductor design tool may place standard cells in a row extending in the Y-axis direction, and the placed standard cell may receive power from a power line extending in the Y-axis direction under a transistor. An example of operation S30is described below with reference toFIG.10.

In operation S50, pins of the standard cells may be routed. For example, the semiconductor design tool may generate interconnections which electrically connect input pins and output pins of placed standard cells and may generate layout data D15which defines the placed standard cells and the generated interconnections. The interconnection may include a via of a via layer and/or a pattern of a wiring layer. The layout data D15may have, for example, a format, such as GDSII, and may include geometric information about the interconnections and the cells. The semiconductor design tool may refer to the design rule D14while routing the pins of the cells. The layout data D15may correspond to an output of place and routing. Operation S50or operation S30and operation S50may be referred to as a method of designing an integrated circuit.

In operation S70, an operation of fabricating a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion, such as refraction caused by a characteristic of light in photolithography, may be applied to the layout data D15. Patterns on a mask may be defined for forming patterns provided in a plurality of layers, based on data to which OPC is applied, and at least one mask (or a photomask) for forming the patterns of each of the plurality of layers may be fabricated. In some embodiments, the layout of the integrated circuit IC may be restrictively modified in operation S70, and an operation of restrictively modifying the integrated circuit IC in operation S70may be post-processing for optimizing a structure of the integrated circuit IC and may be referred to as design polishing.

In operation S90, an operation of manufacturing the integrated circuit IC may be performed. For example, a plurality of layers may be patterned by using at least one mask which is manufactured in operation S70, and thus, the integrated circuit IC may be manufactured. A front-end-of-line (FEOL) may include, for example, an operation of planarizing and cleaning a wafer, an operation of forming a trench, an operation of forming a well, an operation of forming a gate electrode, and an operation of forming a source and a drain, and based on the FEOL, individual devices (for example, a transistor, a capacitor, and a resistor) may be formed on a substrate. Also, a back-end-of-line (BEOL) may include, for example, an operation of performing silicidation of a gate region, a source region, and a drain region, an operation of adding a dielectric, an operation of forming a hole, an operation of adding a metal layer, an operation of forming a via, and an operation of forming a passivation layer, and based on the BEOL, the individual devices (for example, the transistor, the capacitor, and the resistor) may be connected with one another. In some embodiments, a middle-of-line (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on the individual devices. Subsequently, the integrated circuit IC may be packaged in a semiconductor package and may be used as parts of various applications.

FIG.10is a flowchart illustrating a method of designing an integrated circuit, according to an embodiment. For example, the flowchart ofFIG.10illustrates an example of operation S30ofFIG.9. As described above with reference toFIG.9, standard cells may be placed in operation S30′ ofFIG.10. As illustrated inFIG.10, operation S30′ may include a plurality of operations S51to S54.

Referring toFIG.10, a tap cell and a dummy cell may be placed in operation S51. For example, the semiconductor design tool may place the tap cell so as to bias a substrate and/or a well, and the dummy cell may be placed adjacent to the tap cell. In some embodiments, the design rule D14ofFIG.9may define the number of tap cells needed per unit area, and the semiconductor design tool may place the tap cell and the dummy cell with reference to the design rule D14. The semiconductor design tool may place function cells in a region where the tap cell and the dummy cell are placed. In some embodiments, when the dummy cell including a bias region and a dummy region is defined in the cell library D12, the semiconductor design tool may omit placement of the dummy cell.

In operation S52, a through cell may be placed. For example, similar to the description ofFIG.4B, the semiconductor design tool may replace the dummy cell, which is placed in operation S51, with the through cell, and thus, the through cell may be placed. Accordingly, the through cell may be placed in the integrated circuit without an increase in area of the integrated circuit.

In operation S53, whether there is an excess tap cell may be determined. For example, the semiconductor design tool may identify the excess tap cell of the tap cells which are placed in operation S51. In some embodiments, the semiconductor design tool may identify, as the excess tap cell, a tap cell which is greater than the number of tap cells per unit area defined in the design rule D14. As illustrated inFIG.10, when there is an excess tap cell, operation S54may be performed subsequently.

In operation S54, the excess tap cell may be replaced with a through cell. For example, similar to the descriptions ofFIGS.5A to5C, the semiconductor design tool may replace the excess tap cell of the tap cells, which are placed in operation S51, with the through cell. Accordingly, the through cell may be placed in the integrated circuit without disturbing biasing of a substrate and/or a well or increasing an area of the integrated circuit.

FIG.11is a block diagram illustrating a system on chip (SoC)110according to an embodiment. The SoC110may be a semiconductor device and may include an integrated circuit according to an embodiment. In the SoC110, like intellectual property (IP) performing various functions, complicated blocks may be implemented in one chip, and based on a method of designing an integrated circuit according to embodiments, the SoC110may be designed and thus may have high performance and efficiency. Referring toFIG.11, the SoC110may include a modem112, a display controller113, a memory114, an external memory controller115, a central processing unit (CPU)116, a transaction unit117, a power management integrated circuit (PMIC)118, and a graphics processing unit (GPU)119, and the function blocks of the SoC110may communicate with one another through a bus111.

The CPU116for controlling an operation of the SoC110in an uppermost layer may control operations of the other function blocks (112to119). The modem112may demodulate a signal received from the outside of the SoC110, or may modulate a signal generated by the SoC110and may transmit a modulated signal to the outside. The external memory controller115may control an operation of transmitting or receiving data to or from an external memory device connected with the SoC110. For example, a program and/or data stored in the external memory device may be provided to the CPU116or the GPU119, based on control by the external memory controller115. The GPU119may execute program instructions associated with graphics processing. The GPU119may receive graphics data through the external memory controller115and may transmit graphics data, obtained through processing by the GPU119, to the outside of the SoC110through the external memory controller115. The transaction unit117may monitor data transactions of the function blocks, and the PMIC118may control power supplied to each of the function blocks, based on control by the transaction unit117. The display controller113may control a display (or a display device) outside the SoC110and may thus transmit data, generated by the SoC110, to the display. The memory114may include a non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM) or flash memory, or may include a volatile memory, such as DRAM or SRAM.

FIG.12is a block diagram illustrating a computing system120including a memory storing a program, according to an embodiment. A method of designing an integrated circuit according to embodiments (for example, at least some of the operations of the flowchart described above) may be performed by the computing system (or a computer)120.

The computing system120may be a stationary computing system, such as a desktop computer, a workstation, or a server, or may be a portable computing system, such as a laptop computer. As illustrated inFIG.12, the computing system120may include a processor121, input/output (I/O) devices122, a network interface123, random access memory (RAM)124, read only memory (ROM)125, and a storage device126. The processor121, the I/O devices122, the network interface123, the RAM124, the ROM125, and the storage device126may be connected with the bus127and may communicate with one another through the bus127.

The processor121may be referred to as a processing unit, and for example, may include at least one core for executing an arbitrary instruction set (for example, Intel Architecture-32 (IA-32), 64 bit extension IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, or IA-64) such as a microprocessor, an application processor (AP), a digital signal processor (DSP), or a GPU. For example, the processor121may access a memory (for example, the RAM124or the ROM125) through the bus127and may execute instructions stored in the RAM124or the ROM125.

The RAM124may store a program124_1for the method of designing the integrated circuit according to an embodiment or at least a portion thereof, and the program124_1may allow the processor121to perform the method of designing the integrated circuit (for example, at least some of the operations included in the methods ofFIG.9). That is, the program124_1may include a plurality of instructions executable by the processor121, and the plurality of instructions included in the program124_1may allow the processor121to perform, for example, at least some of the operations included in the flowcharts described above.

The storage device126may not erase data stored therein even when power supplied to the computing system120is cut off. For example, the storage device126may include a non-volatile memory device, or may include a storage medium, such as magnetic tape, an optical disk, or a magnetic disk. Also, the storage device126may be detachably attached on the computing system120. The storage device126may store the program124_1according to an embodiment, and the program124_1or at least a portion thereof may be loaded from the storage device126into the RAM124before the program124_1is executed by the processor121. On the other hand, the storage device126may store a file written in a program language, and the program124_1generated from the file by a compiler or at least a portion thereof may be loaded into the RAM124. Also, as illustrated inFIG.12, the storage device126may store a database (DB)1261, and the DB126_1may include information (for example, information about designed blocks or the cell library D12and/or the design rule D14ofFIG.9) needed for designing an integrated circuit.

The storage device126may store data, which is to be processed by the processor121, or data obtained through processing by the processor121. That is, the processor121may process data stored in the storage device126to generate data, based on the program124_1, and may store the generated data in the storage device126. For example, the storage device126may store the RTL data D11, the netlist data D13, and/or the layout data D15ofFIG.9.

The I/O devices122may include an input device such as a keyboard or a pointing device and may include an output device such as a display device or a printer. For example, a user may trigger execution of the program124_1by using the processor121through the I/O devices122, input the RTL data D11and/or the netlist data D13ofFIG.9, or check the layout data D15ofFIG.9.

The network interface123may provide access to a network outside the computing system120. For example, the network may include a plurality of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or arbitrary type of links.

Hereinabove, exemplary embodiments have been described in the drawings and the specification. Embodiments have been described by using the terms described herein, but this has been merely used for describing the inventive concept and has not been used for limiting a meaning or limiting the scope of the inventive concept defined in the following claims. Therefore, it may be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments may be implemented from the inventive concept.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.