Semiconductor device

PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

BACKGROUND OF THE INVENTION

The present invention relates to a method for separately measuring capacitive components in a semiconductor device and a Test Element Group (TEG) pattern having its function.

In the design and development of high-performance LSIs, it is significant to sample (measure) the characteristics of semiconductor elements placed in an LSI with high accuracy, and a technique for sampling (measuring) the same and the optimal design of a TEG are required.

In recent years, as semiconductor elements become finer, the influences of noises caused by crosstalk and the degradation of delay characteristics due to a Miller capacitance have become more obvious. Therefore, it has been required to sample capacitive components of individual conductor members, such as interconnects and semiconductor layers, of the characteristics of the semiconductor device with high accuracy.

A technique for sampling parasitic capacitances as disclosed in Patent Document 1 (U.S. Pat. No. 6,300,765 B1) has been conventionally known. The objective of this technique is to separately measure interconnect-to-interconnect capacitances C12and C13.

FIG. 7is a circuit diagram illustrating the structure of a capacitance measuring circuit for measuring parasitic capacitances as disclosed in Patent Document 1.

As shown in this figure, a P-type Metal Insulator Semiconductor Field Effect Transistor (PMISFET)101and an N-type Metal Insulator Semiconductor Field Effect Transistor)102are connected in series to each other, and the drain of each of the PMISFET101and the NMISFET102is connected via a node N1to an interconnect W1. The source of the PMISFET101is connected to a power supply pad PST for supplying a power supply voltage Vdd, while the source of the NMISFET102is connected to a ground pad GND (voltage Vss). The gate of the PMISFET101is connected to a charging pad111, while the gate of the NMISFET102is connected to a discharging pad112. Furthermore, there are provided an interconnect W2arranged in a layer higher than the interconnect W1and crossing the interconnect W1when viewed in a plane, and an interconnect W3extending substantially parallel to the interconnect W1and crossing the interconnect W2when viewed in the same plane. The interconnect W2is connected to a first pad113for measuring current via a node N2and an NMISFET103, while the interconnect W3is connected to a second pad114for measuring current via a node N3and an NMISFET104. The gate of each of the NMISFETs103and104is connected to a current-monitoring pad115. The capacitance measuring circuit is configured so that it can measure currents I1and I2by bringing the first and second pads113and114for measuring current into contact with probes of ammeters121and122, respectively. When the probes of the ammeters121and122come into contact with the pads113and114for measuring current, respectively, the sources of the NMISFETs103and104are fixed at 0V.

The interconnect W2is connected via an NMISFET105to the ground pad GND, while the interconnect W3is connected via an NMISFET106to the ground pad GND.

Here, the capacitance between the interconnects W1and W2is designated C12, the capacitance between the interconnects W1and W3is designated C13, and the capacitance between the interconnects W2and W3is designated C23. In this relation, the capacitance C12is a value obtained by dividing a charge induced in the interconnect W2when a voltage is applied to the interconnect W1, by the applied voltage. The capacitance C13is a value obtained by dividing a charge induced in the interconnect W3when a voltage is applied to the interconnect W1, by the applied voltage.

FIG. 8is a timing diagram illustrating the operation of the capacitance measuring circuit shown inFIG. 7. The known capacitance measuring circuit operation will be described with reference toFIG. 8.

First, the power supply voltage Vdd is fixed at a voltage Vcc, while the ground voltage Vss is fixed at 0V. A charging voltage V111and a discharging voltage V112are switched between the voltages Vcc and Vss such that both of the PMISFET101and the NMISFET102are not ON at any timing. However, there exists a timing at which both of the PMISFET101and the NMISFET102are OFF. Therefore, no flow-through current passing through both of the PMISFET101and the NMISFET102is produced.

Between timings t0and t1, the discharging voltage V112is held at the voltage Vcc so that the NMISFETs102,105and106are ON. Therefore, the potentials of the nodes N1, N2and N3are fixed at the ground voltage Vss.

Between timings t2and t3, since the PMISFET101and the NMISFET102are OFF, and the NMISFETs103and104are ON, it is possible to monitor currents.

Between timings t3and t4, since the PMISFET101is ON, a charge from the interconnect W1to the interconnects W2and W3is induced. At this time, currents are monitored using the ammeters121and122, thereby measuring the capacitances C12, C13and C23. The time between the timings t3and t4is set at a time enough to induce a charge in the interconnect W1and monitor the currents using the ammeters121and122.

Between timings t5and t6, since all the MISFETs are OFF, it becomes impossible to monitor the currents.

Between timings t6and t7, the same operations as between the timings t0and t1are carried out. Thereafter, the above-mentioned operations for the timings t1through t7are periodically repeated.

The value to be observed by a measuring device using this circuit is a mean value between the currents I1and I2detected over time by the ammeters121and122, respectively. When the frequency of the gate input waveform is f(=1/T) (T denotes the time from the timing t0to the timing t7), the following formulae (1) and (2) hold:
I1=C12·Vcc·f(1)
I2=C13·Vcc·f(2)

By using the formulae (1) and (2), measured capacitance values C12and C13are obtained from the following formulae (3) and (4):
C12=I1/(Vcc·f)  (3)
C13=I2/(Vcc·f)  (4)

This known technique is characterized in that the desired capacitances C12and C13can directly be measured without the need for canceling the parasitic capacitance of a transistor.

SUMMARY OF THE INVENTION

The known technique, however, has the following defects:

(1) the capacitance value C23between the interconnects W2and W3as shown inFIG. 7cannot be measured using a circuit pattern shown inFIG. 7;

(2) even when the circuit pattern shown inFIG. 7is used, the charge induced in the interconnect W1when a voltage is applied to the interconnect W2and the charge induced in the interconnect W1when a voltage is applied to the interconnect W3cannot be measured; and

(3) the number of pads is large for the number of measurable items and typically the area of each of the pads is approximately 100 μm×100 μm, leading to an increase in the area occupied by the semiconductor device.

It is an object of the present invention to provide a semiconductor device including a capacitance measuring circuit that can separately measure capacitance components.

The semiconductor device of the present invention comprises a capacitance measuring circuit in which, when there exist first through third conductor members, the first and second conductor members are connected via respective switching transistors to a common charging voltage supply part and the second and third conductor members are connected via respective switching transistors to a current sampling part.

Thereby, besides parasitic capacitances between the first and second conductor members and parasitic capacitances between the first and third conductor members, parasitic capacitances between the second and third conductor members can also be measured. Only two pads connected to a charging voltage supply part and a current sampling part, respectively become necessary on a semiconductor chip corresponding to the capacitance measuring circuit. Therefore, the number of pads of the whole semiconductor device can be decreased.

Furthermore, if all the conductor members are chargeable and dischargeable, then the parasitic capacitance caused between the second conductor member and the first conductor member when the second conductor member is charged or the parasitic capacitance caused between the third conductor member and the first conductor member when the third conductor member is charged, for example, can also be measured.

Preferably, there is provided a discharge part, and the conductor member whose parasitic capacitance is not to be measured is discharged while the parasitic capacitance between the other two conductor members is measured.

The first through third conductor members may be all interconnects or may be any three-way combination of a source/drain region, a substrate region and a gate electrode of a MISFET. In the latter case, the semiconductor chip has a triple well structure, thereby reducing the influence of noises in the capacitance measurement.

If the charging voltage supply part is operated at a power supply voltage lower than that supplied to a control circuit, then the influence of substrate noises leading to problems in the measurement of the capacitances representing analog quantities can be suppressed.

There may be provided an oscillator for generating a clock signal having a higher frequency than an external clock signal. This allows the control circuit to generate a waveform. The provision of a frequency divider facilitates external monitoring of the frequency.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a circuit diagram illustrating the structure of a capacitance measuring circuit placed in a semiconductor device (LSI) according to a first embodiment. The capacitance measuring circuit located in the semiconductor device of this embodiment is configured to measure the capacitance (parasitic capacitance) between each two of three conductor members forming a target capacitor section (section to be measured in capacitance).

As shown inFIG. 1, the target capacitor section in the semiconductor device of this embodiment is provided with three conductor members each two opposed with dielectrics interposed therebetween. The three conductor members are an interconnect W1(first conductor member), an interconnect W2(second or third conductor member) placed in a layer higher than the interconnect W1and crossing the interconnect W1when viewed in a plane, and an interconnect W3(third or second conductor member) extending substantially parallel to the interconnect W1and crossing the interconnect W2when viewed in the same plane. Capacitances between the interconnects W1and W2are designated C12and C21, capacitances between the interconnects W1and W3are designated C13and C31, and capacitances between the interconnects W2and W3are designated C23and C32. In this relation, the capacitance C12is a value obtained by dividing a charge induced in the interconnect W2when a voltage is applied to the interconnect W1, by the applied voltage. The capacitance C21is a value obtained by dividing a charge induced in the interconnect W1when a voltage is applied to the interconnect W2, by the applied voltage. The capacitance C13is a value obtained by dividing a charge induced in the interconnect W3when a voltage is applied to the interconnect W1, by the applied voltage. The capacitance C31is a value obtained by dividing a charge induced in the interconnect W1when a voltage is applied to the interconnect W3, by the applied voltage. The capacitance C23is a value obtained by dividing a charge induced in the interconnect W3when a voltage is applied to the interconnect W2, by the applied voltage. The capacitance C32is a value obtained by dividing a charge induced in the interconnect W2when a voltage is applied to the interconnect W3, by the applied voltage.

In the capacitance measuring circuit, there are placed three PMISFETs1,2and3(charge-side switching transistors) placed in parallel with one another and three NMISFETs4,5and6(discharge-side switching transistors) connected in series to the PMISFETs1,2and3, respectively. The sources of the PMISFETs1,2and3are commonly connected via a charging voltage supply part to a power supply pad PST for supplying a power supply voltage Vdd, while the sources of the NMISFETs4,5and6are commonly connected via a discharging part to a ground pad GND (voltage Vss). The drains of the PMISFET1and the NMISFET4are connected via a node N1to the interconnect W1. The drains of the PMISFET2and the NMISFET5are connected via a node N2to the interconnect W2. The drains of the PMISFET3and the NMISFET6are connected via a node N3to the interconnect W3.

That is, the interconnect W1is connected via the PMISFET1to the charging voltage supply part and the power supply pad PST, the interconnect W2is connected via the PMISFET2to the charging voltage supply part and the power supply pad PST, and the interconnect W3is connected via the PMISFET3to the charging voltage supply part and the power supply pad PST.

Although not shown inFIG. 1, the power supply pad PST is also connected to an active region (substrate region) of each of the PMISFETs1,2and3, and the ground pad GND is also connected to an active region of each of the NMISFETs4,5,6,7,8, and9, whereby these pads supply potentials to the substrates.

The interconnect W1is connected via the node N1and the NMISFET7(third switching transistor for measuring current) through a current sampling part to a current-monitoring pad41. The interconnect W2is connected via the node N2and the NMISFET8(first or second switching transistor for measuring current) through the current sampling part to the current-monitoring pad41. The interconnect W3is connected via the node N3and the NMISFET9(second or first switching transistor for measuring current) through the current sampling part to the current-monitoring pad41. That is, all of the interconnects W1, W2and W3are connected to the current-monitoring pad41through the common current-sampling part and are configured so that their currents I can be measured by bringing a probe of an ammeter45into contact with the current-monitoring pad41. The outlet side of the ammeter45is fixed at the ground level (0V).

A control circuit31, an oscillator32for generating a clock signal having a higher frequency than an external clock signal and a frequency divider33are connected in parallel to one another between the power supply pad PST (voltage Vdd) and the ground pad GND (voltage Vss). The control circuit31operates in synchronization with a high-frequency clock signal Clk generated by the oscillator32and applies a bias for ON/OFF switching to each of the gates G1through G9of the MISFETs1through9. A high-frequency signal output from the oscillator32is input to an input part of the frequency divider33, and an output part of the frequency divider33is connected to a frequency-monitoring pad43.

According to the semiconductor device of this embodiment, in the capacitance measuring circuit, the interconnect W1that is the first conductor member is connected via the PMISFET1that is the charge-side switching transistor to the charging voltage supply part, the interconnect W2(or W3) that is the second conductor member and the interconnect W3(or W2) that is the third conductor member are connected to the current-sampling part via the NMISFETs8and9that are the switching transistors for measuring current, respectively, and the interconnect W2(or W3) that is the second conductor member is connected to the charging voltage supply part via the PMISFET2(or3) that is the charge-side switching transistor. Therefore, it becomes possible to measure the capacitance C23between the interconnects W2and W3(or the capacitance C32between the interconnects W3and W2) in addition to the capacitance C12between the interconnects W1and W2and the capacitance C13between the interconnects W1and W3.

Furthermore, the interconnects W2and W3are connected to the charging voltage supply part via the PMISFET2and3that are the charge-side switching transistors, and the interconnect W1is connected to the current-sampling part via the NMISFET7that is the switching transistor for measuring current. Therefore, as will be described later, it becomes possible to separately measure all the capacitive components among the three interconnects W1, W2and W3, i.e., the capacitances C12and C21between the interconnects W1and W2, the capacitances C13and C31between the interconnects W1and W3and the capacitances C23and C32between the interconnects W2and W3.

Moreover, the interconnects W1, W2and W3are connected via the NMISFETs4,5and6that are the discharge switching transistors, respectively, through the discharge part to the ground pad. Therefore, in a mode for measuring the capacitance between two interconnects, it becomes possible to fix the potential of an interconnect that is not involved in the capacitance measurement, thereby preventing the accuracy of measuring the capacitance from being deteriorated due to the influence of the interconnect that is not involved in the capacitance measurement.

The capacitance measuring circuit of this embodiment has the advantages that the inclusion of the oscillator32therein allows the control circuit31to generate a waveform by applying a clock signal having a higher frequency than an external clock signal to the control circuit31and the inclusion of the frequency divider33therein simplifies the external monitoring of the frequency.

FIG. 2is a timing diagram illustrating the time variation of gate biases Vg1through Vg9that are output from the control circuit31in the capacitance measurement using the capacitance measuring circuit and are applied to the gates G1through G9of the MISFETs1through9. In this figure, T12denotes the period during which the capacitance C12is monitored, T13denotes the period during which the capacitance C13is monitored, T21denotes the period during which the capacitance C21is monitored, T23denotes the period during which the capacitance C23is monitored, T31denotes the period during which the capacitance C31is monitored, and T32denotes the period during which the capacitance C32is monitored. Although not shown inFIG. 2, the power supply voltage Vdd is fixed at a voltage Vcc, and the ground voltage Vss is fixed at 0V.

Control During the Period T12

First, the NMISFETs4,5and6are ON at a timing t10, because the gate biases Vg4, Vg5and Vg6of the NMISFETs4,5and6are all at H level. The PMISFETs1,2and3are OFF, because the gate biases Vg1, Vg2and Vg3of the NMISFETs1,2and3are all at H level. The NMISFETs7,8and9are OFF, because the gate biases Vg7, Vg8and Vg9of the NMISFETs7,8and9are all at L level. Since at this time the NMISFETs4,5and6are ON and the PMISFET1,2and3are OFF, charges on the nodes N1, N2and N3are all released into the ground.

At a timing t11, the gate biases Vg4and Vg5of the NMISFETs4and5change to L level so that the NMISFETs4and5turn OFF. Therefore, the nodes N1and N2are cut off from the ground pad GND.

Next, at a timing t12, the gate bias Vg8of the NMISFET8changes to H level so that the NMISFET8turns ON. Therefore, the interconnect W2is brought into conduction with the current-monitoring pad41via the node N2.

Next, at a timing t13, the gate bias Vg1of the PMISFET1changes to L level so that the PMISFET1turns ON. Therefore, the interconnect W1is brought into conduction with the power supply pad PST via the node N1, and thus the interconnect W1is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t13to the timing t14to measure the current I, the capacitance value C12between the interconnects W1and W2can be measured from the current I corresponding to the charge induced in the interconnect W2when the voltage Vcc is applied to the interconnect W1, on the basis of the following formula (5):
C12=I/(Vcc·f)  (5)
where f(=1/T) is the frequency of the gate input waveform and T denotes the time from the timing t10to the timing t17.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t13, t12, t11, and t10are carried out at the timings t14, t15, t16, and t17, respectively. Finally, the control state at the timing17is returned to the same state as at the timing t10.

During the period T12, the PMISFET1and the NMISFET4or the NMISFET7are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET1and the NMISFET4or the NMISFET7does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T12, the PMISFETs2and3are always OFF. Thus, the interconnects W2and W3are not charged with the voltage Vcc. Moreover, during the period T12, the NMISFETs7and9are always OFF. Thus, the nodes N1and N3are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W1and W3are not observed. Since during the period T12the gate bias Vg6of the NMISFET6is always at H level, the NMISFET6is always ON, and the potential of the node N3is fixed at 0V. Therefore, the capacitance relating to the interconnect W3is not observed.

Control During the Period T13

First, at a timing t20, each of the gate biases Vg1through Vg9of the MISFETs1through9is at the same voltage level as at the timing t10during the period T12.

At a timing t21, the gate biases Vg4and Vg6of the NMISFETs4and6change to L level so that the NMISFETs4and6turn OFF. Therefore, the nodes N1and N3are cut off from the ground pad GND.

Next, at a timing t22, the gate bias Vg9of the NMISFET9changes to H level so that the NMISFET9turns ON. Therefore, the interconnect W3is brought into conduction with the current-monitoring pad41via the node N3.

Next, at a timing t23, the gate bias Vg1of the PMISFET1changes to L level so that the PMISFET1turns ON. Therefore, the interconnect W1is brought into conduction with the power supply pad PST via the node N1, and thus the interconnect W1is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t23to the timing t24to measure the current I, the capacitance value C13between the interconnects W1and W3can be measured from the current I corresponding to the charge induced in the interconnect W3when the voltage Vcc is applied to the interconnect W1, on the basis of the following formula (6):
C13=I/(Vcc·f)  (6)
where f(=1/T) is the frequency of the gate input waveform and T denotes the time from the timing t20to the timing t27.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t23, t22, t21, and t20are carried out at the timings t24, t25, t26, and t27, respectively. Finally, the control state at the timing27is returned to the same state as at the timing t20.

During the period T13, the PMISFET1and the NMISFET4or the NMISFET7are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET1and the NMISFET4or the NMISFET7does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T13, the PMISFETs2and3are always OFF. Thus, the interconnects W2and W3are not charged with the voltage Vcc. Moreover, during the period T13, the NMISFETs7and8are always OFF. Thus, the nodes N1and N2are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W1and W2are not observed. Since during the period T13the gate bias Vg5of the NMISFET5is always at H level, the NMISFET5is always ON, and the potential of the node N2is fixed at 0V. Therefore, the capacitance relating to the interconnect W2is not observed.

Control During the Period T21

First, at a timing t30, each of the gate biases Vg1through Vg9of the MISFETs1through9is at the same voltage level as at the timing t10during the period T12.

At a timing t31, the gate biases Vg4and Vg5of the NMISFETs4and5change to L level so that the NMISFETs4and5turn OFF. Therefore, the nodes N1and N2are cut off from the ground pad GND.

Next, at a timing t32, the gate bias Vg7of the NMISFET7changes to H level so that the NMISFET7turns ON. Therefore, the interconnect W1is brought into conduction with the current-monitoring pad41via the node N1.

Next, at a timing t33, the gate bias Vg2of the PMISFET2changes to L level so that the PMISFET2turns ON. Therefore, the interconnect W2is brought into conduction with the power supply pad PST via the node N2, and thus the interconnect W2is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t33to the timing t34to measure the current I, the capacitance value C21between the interconnects W2and W1can be measured from the current I corresponding to the charge induced in the interconnect W1when the voltage Vcc is applied to the interconnect W2, on the basis of the following formula (7):
C21=I/(Vcc·f)  (7)
where f(=1/T) is the frequency of the gate input waveform and T denotes a time from the timing t30to the timing t37.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t33, t32, t31, and t30are carried out at the timings t34, t35, t36, and t37, respectively. Finally, the control state at the timing t37is returned to the same state as at the timing t30.

During the period T21, the PMISFET2and the NMISFET5or the NMISFET8are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET2and the NMISFET5or the NMISFET8does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T21, the PMISFETs1and3are always OFF. Thus, the interconnects W1and W3are not charged with the voltage Vcc. Moreover, during the period T21, the NMISFETs7and9are always OFF. Thus, the nodes N1and N3are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W1and W3are not observed. Since during the period T21the gate bias Vg6of the NMISFET6is always at H level, the NMISFET6is always ON, and the potential of the node N3is fixed at 0V. Therefore, the capacitance relating to the interconnect W3is not observed.

Control During the Period T23

First, at a timing t40, each of the gate biases Vg1through Vg9of the MISFETs1through9is at the same voltage level as at the timing t10during the period T12.

At a timing t41, the gate biases Vg5and Vg6of the NMISFETs5and6change to L level so that the NMISFETs5and6turn OFF. Therefore, the nodes N1and N3are cut off from the ground pad GND.

Next, at a timing t42, the gate bias Vg9of the NMISFET9changes to H level so that the NMISFET9turns ON. Therefore, the interconnect W3is brought into conduction with the current-monitoring pad41via the node N3.

Next, at a timing t43, the gate bias Vg2of the PMISFET2changes to L level so that the PMISFET2turns ON. Therefore, the interconnect W2is brought into conduction with the power supply pad PST via the node N2, and thus the interconnect W2is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t43to the timing t44to measure the current I, the capacitance value C23between the interconnects W2and W3can be measured from the current I corresponding to the charge induced in the interconnect W3when the voltage Vcc is applied to the interconnect W2, on the basis of the following formula (8):
C23=I/(Vcc·f)  (8)
where f(=1/T) is the frequency of the gate input waveform and T denotes the time from the timing t40to the timing t47.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t43, t42, t41, and t40are carried out at the timings t44, t45, t46, and t47, respectively. Finally, the control state at the timing t47is returned to the same state as at the timing t40.

During the period T23, the PMISFET2and the NMISFET5or the NMISFET8are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET2and the NMISFET5or the NMISFET8does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T23, the PMISFETs1and3are always OFF. Thus, the interconnects W1and W3are not charged with the voltage Vcc. Moreover, during the period T23, the NMISFETs7and8are always OFF. Thus, the nodes N1and N2are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W1and W2are not observed. Since during the period T23the gate bias Vg4of the NMISFET4is always at H level, the NMISFET4is always ON, and the potential of the node N1is fixed at 0V. Therefore, the capacitance relating to the interconnect W1is not observed.

Control During the Period T31

First, at a timing t50, each of the gate biases Vg1through Vg9of the MISFETs1through9is at the same voltage level as at the timing t10during the period T12.

At a timing t51, the gate biases Vg4and Vg6of the NMISFETs4and6change to L level so that the NMISFETs4and6turn OFF. Therefore, the nodes N1and N3are cut off from the ground pad GND.

Next, at a timing t52, the gate bias Vg7of the NMISFET7changes to H level so that the NMISFET7turns ON. Therefore, the interconnect W1is brought into conduction with the current-monitoring pad41via the node N1.

Next, at a timing t53, the gate bias Vg3of the PMISFET3changes to L level so that the PMISFET3turns ON. Therefore, the interconnect W3is brought into conduction with the power supply pad PST via the node N3, and thus the interconnect W3is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t53to the timing t54to measure the current I, the capacitance value C31between the interconnects W3and W1can be measured from the current I corresponding to the charge induced in the interconnect W1when the voltage Vcc is applied to the interconnect W3, on the basis of the following formula (9):
C31=I/(Vcc·f)  (9)
where f(=1/T) is the frequency of the gate input waveform and T denotes the time from the timing t50to the timing t57.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t53, t52, t51, and t50are carried out at the timings t54, t55, t56, and t57, respectively. Finally, the control state at the timing t57is returned to the same state as at the timing t50.

During the period T31, the PMISFET3and the NMISFET6or the NMISFET9are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET3and the NMISFET6or the NMISFET9does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T31, the PMISFETs1and2are always OFF. Thus, the interconnects W1and W2are not charged with the voltage Vcc. Moreover, during the period T31, the NMISFETs8and9are always OFF. Thus, the nodes N2and N3are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W2and W3are not observed. Since during the period T31the gate bias Vg5of the NMISFET5is always at H level, the NMISFET5is always ON, and the potential of the node N2is fixed at 0V. Therefore, the capacitance relating to the interconnect W2is not observed.

Control During the Period T32

First, at a timing t60, each of the gate biases Vg1through Vg9of the MISFETs1through9is at the same voltage level as at the timing t10during the period T12.

At a timing t61, the gate biases Vg5and Vg6of the NMISFETs5and6change to L level so that the NMISFETs5and6turn OFF. Therefore, the nodes N2and N3are cut off from the ground pad GND.

Next, at a timing t62, the gate bias Vg8of the NMISFET8changes to H level so that the NMISFET8turns ON. Therefore, the interconnect W2is brought into conduction with the current-monitoring pad41via the node N2.

Next, at a timing t63, the gate bias Vg3of the PMISFET3changes to L level so that the PMISFET3turns ON. Therefore, the interconnect W3is brought into conduction with the power supply pad PST via the node N3, and thus the interconnect W3is charged.

Accordingly, when the probe of the ammeter45is brought into contact with the current-monitoring pad41during a period from the timing t63to the timing t64to measure the current I, the capacitance value C32between the interconnects W3and W2can be measured from the current I corresponding to the charge induced in the interconnect W1when the voltage Vcc is applied to the interconnect W3, on the basis of the following formula (10):
C32=I/(Vcc·f)  (10)
where f(=1/T) is the frequency of the gate input waveform and T denotes the time from the timing t60to the timing t67.

Thereafter, gate biases are changed such that the operations opposite to those at the timings t63, t62, t61, and t60are carried out at the timings t64, t65, t66, and t67, respectively. Finally, the control state at the timing t67is returned to the same state as at the timing t60.

During the period T32, the PMISFET3and the NMISFET6or the NMISFET9are not ON simultaneously. Thus, a flow-through current that flows through the PMISFET3and the NMISFET6or the NMISFET9does not flow from the power supply pad PST into the current-monitoring pad41and the ground pad GND. During the period T32, the PMISFETs1and2are always OFF. Thus, the interconnects W1and W2are not charged with the voltage Vcc. Moreover, during the period T32, the NMISFETs7and9are always OFF. Thus, the nodes N1and N3are not brought into conduction with the current-monitoring pad41, and consequently currents from the interconnects W1and W3are not observed. Since during the period T32the gate bias Vg4of the NMISFET4is always at H level, the NMISFET4is always ON, and the potential of the node N1is fixed at 0V. Therefore, the capacitance relating to the interconnect W1is not observed.

According to the capacitance measuring circuit of this embodiment, when there exist three interconnects W1, W2and W3, the capacitances C21, C23, C31, and C32can be measured by charging the interconnects W2and W3, besides the capacitances C12and C13that can be observed by charging the interconnect W1.

In addition, only five pads are necessary for this embodiment. Therefore, the number of pads can be significantly decreased as compared with the number of pads, seven, that is required for the known capacitance measuring circuit shown inFIG. 7, resulting in the reduced area of the semiconductor device.

FIG. 3is a circuit diagram illustrating the structure of a capacitance measuring circuit placed in a semiconductor device (LSI) according to a second embodiment. The capacitance measuring circuit located in the semiconductor device of this embodiment is configured to measure the capacitance (parasitic capacitance) between each two of three conductor members forming a target capacitor section.

As shown inFIG. 3, the target capacitor section in the semiconductor device of this embodiment is also provided with three conductor members each two opposed with dielectrics interposed therebetween. However, unlike the first embodiment, the three conductor members of this embodiment are a source/drain region SD (first conductor member) formed by doping part of a semiconductor substrate with impurities, a substrate region SUB (second conductor member) corresponding to a well and a gate electrode GT (third conductor member).

On the other hand, the structure of the capacitance measuring circuit is the same as that of the first embodiment. Capacitances between the source/drain region SD and the substrate region SUB are designated Cdb (corresponding to C12) and Cbd (corresponding to C21), capacitances between the source/drain region SD and the gate electrode GT are designated Cdg (corresponding to C13) and Cgd (corresponding to C31), and capacitances between the substrate region SUB and the gate electrode GT are designated Cbg (corresponding to C23) and Cgb (corresponding to C32). In this relation, the capacitance Cdb is a value obtained by dividing a charge induced in the substrate region SUB when a voltage is applied to the source/drain region SD, by the applied voltage. The capacitance Cbd is a value obtained by dividing a charge induced in the source/drain region SD when a voltage is applied to the substrate region SUB, by the applied voltage. The capacitance Cdg is a value obtained by dividing a charge induced in the gate electrode GT when a voltage is applied to the source/drain region SD, by the applied voltage. The capacitance Cgd is a value obtained by dividing a charge induced in the source/drain region SD when a voltage is applied to the gate electrode GT, by the applied voltage. The capacitance Cbg is a value obtained by dividing a charge induced in the gate electrode GT when a voltage is applied to the substrate region SUB, by the applied voltage. The capacitance Cgb is a value obtained by dividing a charge induced in the substrate region SUB when a voltage is applied to the gate electrode GT, by the applied voltage.

FIG. 4is a cross sectional view of the semiconductor device of this embodiment. As shown in this figure, the semiconductor device of this embodiment has a structure in which the target capacitor section is surrounded by a triple well.

This figure shows the cross sectional structure of the target capacitor section and the capacitance measuring circuit that are part of a logic circuit located in the semiconductor device but does not show the other regions such as a memory region and a peripheral circuit region.

The semiconductor substrate is partitioned into plural active regions by isolation regions55having a shallow trench structure. In the semiconductor substrate, there are provided a P-well51occupying most of the semiconductor substrate, a deep N-well52the lower side of which is surrounded by the P-well51, a P-well53the lower side of which is covered by the deep N-well52, and an N-well54for separating the P-wells53and51from each other.

The NMISFET of the target capacitor section comprises a source/drain region56(SD) formed by doping the P-well53corresponding to the substrate region SUB with N-type impurities, and a gate electrode61(GT). On the other hand, the NMISFET of the capacitance measuring circuit comprises a source/drain region58formed by doping the P-well51with N-type impurities, and a gate electrode62.

Also in this embodiment, when the capacitances C12and C21in the first embodiment are replaced with the capacitances Cdb and Cbd, the capacitances C13and C31are replaced with the capacitances Cdg and Cgd, and the capacitances C23and C32are replaced with the capacitances Cbg and Cgb, each of the capacitances Cdb, Cbd, Cdg, Cgd, Cbg, and Cgb can be measured utilizing the control method shown inFIG. 2and the formulae (5) through (10).

Since this embodiment employs, particularly, the structure of the semiconductor device in which the target capacitor section is surrounded by the triple well, capacitances between each two of members of the MISFET can be measured with high accuracy, while noises from the MISFET in the capacitance measuring circuit operating by a high-frequency clock are cut off.

Furthermore, when the voltages of the power supply pad PST, the ground pad GND and the pad41for measuring current are changed, the capacitances can be measured in an arbitrary voltage state. In particular, the MIS capacitance has a voltage dependency. The voltage dependencies of the capacitances can be measured by the following formula (11).
C(v)={I(V+δV)−I(V)}/f(11)

FIG. 5is a circuit diagram illustrating the structure of a capacitance measuring circuit placed in a semiconductor device (LSI) according to a third embodiment. The capacitance measuring circuit located in the semiconductor device of this embodiment is configured to measure the capacitance (parasitic capacitance) between each two of three conductor members forming a target capacitor section.

Also in this embodiment, as shown inFIG. 5, an interconnect W1(first conductor member), an interconnect W2(second conductor member) and an interconnect W3(third conductor member) are placed as three conductor members in the target capacitor section. The target capacitor section is configured to measure the capacitances C12and C21between the interconnects W1and W2, the capacitances C13and C31between the interconnects W1and W3, and the capacitances C23and C32between the interconnects W2and W3.

The structure of the capacitance measuring circuit of this embodiment is characterized in that two MISFETs7aand7bthat are equivalent to the NMISFET7in the first embodiment are connected in series, two MISFETs8aand8bthat are equivalent to the NMISFET8are connected in series, and two MISFETs9aand9bthat are equivalent to the NMISFET9are connected in series. The pairs of MISFETs receive common gate biases Vg7, Vg8and Vg9, respectively. While one of each pair of MISFETs (for example, NMISFET7a,8aor9a) is a current-monitoring MISFET having the same threshold voltage as the NMISFETs7,8or9in the first embodiment, the other (for example, NMISFETs7b,8bor9b) is a MISFET for suppressing off-leakage current, which has a higher threshold voltage than the NMISFETs7,8and9in the first embodiment. The other structure is identical with the structure of the measuring circuit shown inFIG. 1.

Also in the capacitance measuring circuit of this embodiment, the capacitances C12and C21between the interconnects W1and W2, the capacitances C13and C31between the interconnects W1and W3, and the capacitances C23and C32between the interconnects W2and W3can be measured utilizing the control method shown inFIG. 2and the formulae (5) through (10).

According to the capacitance measuring circuit of this embodiment, as in the first embodiment, the capacitances C12, C21, C13, C31, C23, and C32between each two of the three conductor members can be measured while the number of pads is decreased.

In addition, since in the capacitance measuring circuit of this embodiment, a current-monitoring MISFET (for example, NMISFETs7a,8aor9a) and a MISFET for suppressing off-leakage current (for example, NMISFET7b,8bor9b) having a higher threshold voltage than the current-monitoring MISFET are placed in series between each of the nodes N1, N2and N3and the pad41for measuring current, this effectively decreases leakage current.

Furthermore, since the operations of the current-monitoring MISFET and the MISFET for suppressing off-leakage current are controlled by a common control signal (a gate bias Vg7, Vg8or Vg9), a redundant control circuit is unnecessary. Therefore, the structure of the control circuit can be simplified.

When the capacity to drive the current-monitoring MISFET is less necessary, the number of MISFETs placed in series with that current-monitoring MISFET can be increased, thereby enhancing the effect of decreasing leakage current.

The conductor members in the third embodiment are not limited to the interconnects W1, W2and W3but may be a source/drain region, a substrate region and a gate electrode as shown inFIGS. 3 and 4.

FIG. 6is a circuit diagram illustrating the structure of a capacitance measuring circuit for measuring the capacitances of capacitors placed in a semiconductor device (LSI) according to a fourth embodiment. The capacitance measuring circuit located in the semiconductor device of this embodiment is configured to measure the capacitance between each two of three conductor members forming a target capacitor section.

Also in this embodiment, as shown inFIG. 6, an interconnect W1(first conductor member), an interconnect W2(second conductor member) and an interconnect W3(third conductor member) are placed as three conductor members in the target capacitor section. The target capacitor section is configured to measure the capacitances C12and C21between the interconnects W1and W2, the capacitances C13and C31between the interconnects W1and W3, and the capacitances C23and C32between the interconnects W2and W3.

The structure of the capacitance measuring circuit of this embodiment is characterized in that there are provided power supply pads PST1and PST2for individually supplying power supply voltages Vdd1(for example, 0.1V) and Vdd2(for example, 1.2V) to the capacitance measuring circuit and the interconnects W1, W2and W3of the target capacitor section. The configurations of the other parts are identical with those of the first embodiment.

Also in the capacitance measuring circuit of this embodiment, the capacitances C12and C21between the interconnects W1and W2, the capacitances C13and C31between the interconnects W1and W3, and the capacitances C23and C32between the interconnects W2and W3can be measured utilizing the control method shown inFIG. 2and the formulae (5) through (10).

According to the capacitance measuring circuit of this embodiment, as in the first embodiment, the capacitances C12, C21, C13, C31, C23, and C32between each two of the three conductor members can be measured while the number of pads is decreased.

In addition, since in the semiconductor device of this embodiment there are provided power supply pads PST1and PST2for individually supplying power supply voltages Vdd1and Vdd2to the capacitance measuring circuit and the interconnects W1, W2and W3of the target capacitor section, the following effects can be delivered.

The power supply voltage Vdd1supplied to the interconnects W1, W2and W3is not for controlling the operations of the MISFETs. Thus, the voltage Vdd1is not required to be much high. The reason is that the gate biases Vg1through Vg9of the MISFETs1through9are supplied from the control circuit31. If the voltage between the source and drain in each of the MISFETs1through9is lowered, the operating speed of that MISFET1through9may be decreased to some extent. In such a case, since the operating frequency is lowered, the function of measuring the capacitances is not degraded. When the voltages applied to the interconnects W1, W2and W3are increased, noises are easily included in the currents I to be measured. Contrarily, when, as in this embodiment, the power supply voltage Vdd1is decreased, the occurrence of the noise can be suppressed.

On the other hand, the power supply voltage Vdd2supplied to a capacitance sampling part such as the control circuit31is for controlling the operations of the MISFETs. Thus, in order to keep the operating speeds of the MISFETs high, the voltage Vdd2must be high to some extent. Even when the power supply voltage Vdd2is made higher, the occurrence of noise has less effect on the operation of each MISFET. In general, noises of the substrate lead to inconveniences for an analog circuit but present no problem for a logic circuit.

The conductor members of the fourth embodiment are not limited to the interconnects W1, W2and W3but may be a source/drain region, a substrate region and a gate electrode as shown inFIGS. 3 and 4. In the capacitance measuring circuit of the fourth embodiment, each of the NMISFETs7,8and9may comprise plural MISFETs placed in series as shown inFIG. 5.

The number of conductor members placed in the target capacitor section, for example, interconnects, may be four or more. Also in this case, if, as shown inFIGS. 1,3,5, and6, one PMISFET and two NMISFETs are placed for each of the conductor members, then the capacitance between each two of the interconnects can be measured.

In each of the embodiments, the semiconductor substrate includes a substrate wholly made of a semiconductor (for example, a semiconductor such as Si, Ge or GaAs), an SOI substrate, and a substrate having a heterojunction (for example, a Si/SiGe-type semiconductor substrate).

According to the semiconductor device of the present invention, the capacitances (parasitic capacitances) among three or more conductor members can be measured separately while the number of necessary pads is decreased.