Memory controller and method for handling host request based on data character

A method for managing a memory includes: receiving a write request from a host; selecting an internal storage region among a plurality of internal storage regions of the memory based on data characterization information of a data received from a host according to the write request from a host; generating a metadata including the data characterization information of the data according to the write request; and storing the metadata along with the data in the selected internal storage region.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2016-0025661 filed on Mar. 3, 2016, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate generally to a semiconductor designing technology and, more particularly, to a memory controller and method for managing memory.

2. Description of the Related Art

The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. As a result, use of portable electronic devices such as mobile phones, digital cameras, and notebook computers continues to increase rapidly. These portable electronic devices generally use a memory system (also referred to as a data storage device) having one or more semiconductor memory devices for storing data. The memory system may be used as a main memory device or an auxiliary memory device of a portable electronic device.

Memory systems may provide excellent stability, durability, high information access speed, and low power consumption, since they have no moving parts. Examples of memory systems include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).

SUMMARY

Embodiments of the present invention are directed to a memory controller for a memory system and a method for efficiently managing a storage region of a semiconductor memory included in the memory system.

In accordance with an embodiment of the present invention, a method for managing a memory, may include: receiving a write request from a host; selecting an internal storage region among a plurality of internal storage regions of the memory based on data characterization information of a data received from a host according to the write request from a host; generating a metadata including the data characterization information of the data according to the write request; and storing the metadata along with the data in the selected internal storage region.

The method may further include: receiving a read request for the data received from the host, after the data is stored along with the metadata in the selected internal storage region, selecting one internal storage region among the plurality of the internal storage regions based on the data characterization information of the data according to the read request; reading the metadata corresponding to the data according to the read request out of the selected internal storage region, which is selected based on the data characterization information of the data according to the read request; determining whether the data characterization information of the data according to the write request that is included in the read metadata is the same as the data characterization information of the data according to the read request; and reading the data according to the read request out of the selected internal storage region, which is selected based on the data characterization information of the data according to the read request when the data characterization information of the data according to the write request that is included in the read metadata is the same as the data characterization information of the data according to the read request.

The method may further include: when the data characterization information of the data according to the write request that is included in the read metadata is not the same as the data characterization information of the data according to the read request, not reading the data according to the read request.

The method may further include: transferring data characteristics discrepancy and read failure information to the host.

the storing of the metadata along with the data in the selected internal storage region may include: checking out whether a sum of a size of the data and a size of the metadata is greater than a size of an empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The checking out of whether the sum of the size of the data and the size of the metadata is greater than the size of the empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request may include: calculating a size of an address region corresponding to the sum, and comparing the calculated size of the address region with a size of a selected address region corresponding to the empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request; when the calculated size of the address region is greater than the size of the selected address region, confirming that the size of the sum is greater than the size of the selected internal storage region; and when the calculated size of the address region is not greater than the size of the selected address region, confirming that the size of the sum is not greater than the size of the selected internal storage region.

The storing of the metadata along with the data in the selected internal storage region may further include: when the sum of the size of the data and the size of the metadata is not greater than the size of the empty space of the selected internal storage region, storing the data and the metadata in the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The storing of the metadata along with the data in the selected internal storage region may further include: when the sum of the size of the data and the size of the metadata is greater than the size of the empty space of the selected internal storage region, not storing the data and the metadata in the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The storing of the metadata along with the data in the selected internal storage region may further include: when the sum of the size of the data and the size of the metadata is greater than the size of the empty space of the selected internal storage region, transferring overflow and storage failure information to the host.

In accordance with an embodiment of the present invention, a memory controller, may include: a memory; and a processor. The processor may be suitable for: dividing a storing region of the memory into a plurality of internal storage regions; selecting one internal storage region among the plurality of the internal storage regions based on data characterization information of a data according to a write request from a host; generating a metadata including the data characterization information of the data according to the write request; and storing the metadata along with the data in the selected internal storage region.

The processor may be further suitable for: when a read request for the data is received from the host, after the data is stored along with the metadata in the selected internal storage region, selecting one internal storage region among the plurality of the internal storage regions based on the data characterization information of the data according to the read request; reading the metadata corresponding to the data according to the read request out of the selected internal storage region, which is selected based on the data characterization information of the data according to the read request, and figuring out whether the data characterization information of the data according to the write request that is included in the read metadata is the same as the data characterization information of the data according to the read request; and when the data characterization information of the data according to the write request that is included in the read metadata is the same as the data characterization information of the data according to the read request, reading the data according to the read request out of the selected internal storage region, which is selected based on the data characterization information of the data according to the read request.

The processor may be further suitable for: when the data characterization information of the data according to the write request that is included in the read metadata is not the same as the data characterization information of the data according to the read request, not reading the data according to the read request.

The processor may be further suitable for: transferring data characteristics discrepancy and read failure information to the host.

The processor may be further suitable for: checking out whether a sum of a size of the data and a size of the metadata is greater than a size of an empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The processor may be further suitable for checking out whether a sum of a size of the data and a size of the metadata is greater than a size of an empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request by including: calculating a size of an address region corresponding to the sum, and comparing the calculated size of the address region with a size of a selected address region corresponding to the empty space of the selected internal storage region, which is selected based on the data characterization information of the data according to the write request; when the calculated size of the address region is greater than the size of the selected address region, confirming that the size of the sum is greater than the size of the selected internal storage region; and when the calculated size of the address region is not greater than the size of the selected address region, confirming that the size of the sum is not greater than the size of the selected internal storage region.

The processor may be further suitable for: when the sum of the size of the data and the size of the metadata is not greater than the size of the empty space of the selected internal storage region, storing the data and the metadata in the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The processor may be further suitable for: when the sum of the size of the data and the size of the metadata is greater than the size of the empty space of the selected internal storage region, not storing the data and the metadata in the selected internal storage region, which is selected based on the data characterization information of the data according to the write request.

The processor may be further suitable for: when the sum of the size of the data and the size of the metadata is greater than the size of the empty space of the selected internal storage region, transferring overflow and storage failure information to the host.

DETAILED DESCRIPTION

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to more clearly illustrate the various elements of the embodiments. For example, in the drawings, the size of elements and the intervals between elements may be exaggerated compared to actual sizes and intervals for convenience of illustration.

Hereinafter, the various embodiments of the present invention will be described in detail with reference to the attached drawings. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

Referring now toFIG. 1a data processing system100including a memory system110is provided, according to an embodiment of the present invention. The data processing system100may include a host102operatively coupled to the memory system.

The host102may include a portable electronic device, such as, a mobile phone, an MP3 player and a laptop computer, or a fixed electronic device, such as, a desktop computer, a game player, a television (TV) and a projector.

The memory system110may operate in response to a request from the host102. In particular, the memory system110may store data to be accessed by the host102. The memory system110may be used as a main memory system or an auxiliary memory system of the host102. The memory system110may be implemented as any one of various kinds of storage devices, according to the protocol of a host interface to be electrically coupled with the host102. For example, the memory system110may be implemented as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and so forth.

The memory system110may include a memory device150for storing data to be accessed by the host102, and a controller130for controlling the operation of the memory device150and its interfacing with the host.

The controller130and the memory device150may be integrated into a single semiconductor device. For instance, the controller130and the memory device150may be integrated into a single semiconductor device configured as a solid state drive (SSD). When the memory system110is used as an SSD, the operation speed of the host102that is electrically coupled with the memory system110may be significantly increased.

The controller130and the memory device150may be integrated into a single semiconductor device configured as a memory card. The controller130and the memory card150may be integrated into a single semiconductor device configured as a memory card, such as, a Personal Computer Memory Card International Association (PCMCIA) card, a compact flash (CF) card, a smart media (SM) card (SMC), a memory stick, a multimedia card (MMC), an RS-MMC and a micro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD and an SDHC, and a universal flash storage (UFS) device.

For another instance, the memory system110may be configured as a storage device of a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage configuring a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various component elements configuring a computing system.

In an embodiment, the memory device150may be a nonvolatile memory device capable of retaining stored data therein even when power supply is interrupted. The memory device150may store data provided from the host102during a write operation, and may also provide stored data to the host102during a read operation. The memory device150may include a plurality of memory blocks152,154and156. Each of the memory blocks152,154and156may include a plurality of pages. Each of the pages may include a plurality of memory cells. In an embodiment, a page includes a plurality of memory cells coupled to the same word line. In an embodiment the memory device150may be a flash memory having a three-dimensional (3D) stack structure.

The controller130may control the memory device150in response to a request received from the host102. The controller130may control the operations of the memory device150, including, for example, read, write, program and erase operations. For example, the controller130may provide data read from the memory device150to the host102in response to a read request received for the host102. Also, for example, the controller130may store data provided from the host102to the memory device150, in response to a program (write) request received for the host102.

According to the illustrated embodiment ofFIG. 1, the controller130may include a host interface unit132, a processor134, an error correction code (ECC) unit138, a power management unit (PMU)140, a NAND flash controller (NFC)142, and a memory144.

The host interface unit132may process commands and data provided from the host102, and may communicate with the host102through at least one of various interface protocols, such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component Interconnect-express (PCI-E), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

The ECC unit138may detect and correct errors in the data read from the memory device150during a read operation. The ECC unit138may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and may output an error correction fall signal indicating a failure in correcting the error bits.

The ECC unit138may perform an error correction operation based on a coded modulation, such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC unit138may include all circuits, systems or devices that are suitable for the error correction operation.

The PMU140may provide and manage power for the controller130, that is, power for the component elements included in the controller130. PMUs are well-known in the art, hence, further details thereof are omitted. Any suitable PMU may be employed.

The NFC142is an example of a suitable memory interface between the controller130and the memory device150when the memory device150is a NAND flash memory device. The NFC142provides and interface to allow the controller130to control the memory device150in response to a request from the host102. The NFC142may also generate control signals for the memory device150and process data under the control of the processor134. When the memory device150is not a NAND flash memory a different suitable interface may be employed among many well-known memory interfaces in the art.

The memory144may serve as a working memory of the memory system110and the controller130, and store data for driving the memory system110and the controller130. The controller130may control the memory device150in response to a request from the host102. For example, the controller130may provide the data read from the memory device150to the host102and store the data provided from the host102in the memory device150. When the controller130controls the operations of the memory device150, the memory144may store data used by the controller130and the memory device150for such operations as read, write, program and erase operations.

The memory144may be implemented with a volatile memory. The memory144may be implemented for example with a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the memory144may store data used by the host102and the memory device150for the read and write operations. To store the data, the memory144may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and so forth.

The processor134may control the operations of the memory system110. For example, the processor134may control a write operation or a read operation for the memory device150, in response to a write request or a read request from the host102. The processor134may drive firmware, which is referred to as a flash translation layer (FTL), to control the operations of the memory system110. The processor134may be implemented, for example, with a microprocessor or a central processing unit (CPU).

A management unit (not shown) may be included in the processor134for performing bad block management for the memory device150. For example, the management unit may find bad memory blocks included in the memory device150, which are in unsatisfactory condition for further use, and perform bad block management on the bad memory blocks. When the memory device150is a flash memory (e.g., a NAND flash memory), a program failure may occur during the write operation (i.e., the program operation), due to characteristics of a NAND logic function. During the bad block management, the data of the program-failed memory block or the bad memory block may be programmed into a new memory block. Bad blocks due to a program fail may seriously deteriorate the utilization efficiency of the memory device150and the overall reliability of the memory system100. Hence, reliable bad block management may be included.

FIG. 2illustrates a configuration example of the memory144of the memory system110shown inFIG. 1. More specifically,FIG. 2shows how the storage region of the memory144among the constituent elements of the memory system110shown inFIG. 1may be organized.

As mentioned with reference toFIG. 1, the memory144may be used for many purposes. For example, the memory144may store data needed to perform a data write operation between the host102and the memory device150. For another example, the memory144may store data needed to perform a data read operation between the host102and the memory device150. The memory144may include a program memory, a data memory, a write buffer, a read buffer, and a map buffer to store the data needed to perform a data write operation and a data read operation between the host102and the memory device150.

The storage region of the memory144included in the memory system110may be divided into a plurality of internal storage regions according to how the host102uses the memory system110. For example, as shown inFIG. 2, the storage region of the memory144may be divided into five internal storage regions, i.e., a first internal storage region1441, a second internal storage region1442, a third internal storage region1443, a fourth internal storage region1444, and a fifth internal storage region1445according to how the host102uses the memory system110. As illustrated, the first internal storage region1441may be a register region REGISTER for temporarily storing a data or a signal that is transferred in the inside of the memory system110. The second internal storage region1442may be a data storage memory region DATA for storing a data during a write operation and/or a read operation between the host102and the memory device150. The third internal storage region1443may be a buffer region BUFFER for buffering a data during a write operation and/or a read operation between the host102and the memory device150. The fourth internal storage region1444may be a main memory region MAIN for storing a firmware code for controlling the operation in the inside of the memory system110. The fifth internal storage region1445may be a link region LINK for storing an address map table.

The structure shown inFIG. 2is a mere example, and the storage region of the memory144may be divided into more internal storage regions or less internal storage regions than the first to fifth internal storage regions1441-1445and managed according to how the host102uses the memory system110. In the illustrated embodiment ofFIG. 2, as an example, it is provided that the first storage region1441has a size of 64 KB, the second storage region1442has a size of 384 KB, the third storage region1443has a size of 32 KB, the fourth storage region1444has a size of 32 KB, and the fifth storage region1445has a size of 48 KB. It is noted, however, that the size of each internal storage region may be changed according to design.

FIG. 3illustrates how the memory144ofFIG. 2is related with the operations of the host102ofFIG. 1.

Referring toFIG. 3, a plurality of operations FUNCTION<1:8> are performed in the host102. The storage region of the memory144included in the memory system110is divided into a plurality of internal storage regions1441,1442,1443,1444and1445, which respectively correspond to the operations FUNCTION<1:8>.

First, it is assumed, for illustration purposes that a total of 8 operations FUNCTION<1:8> are performed in the host102. Herein, the 8 operations FUNCTION<1:8> may be the operations of reading/writing/erasing data from/to the memory device150of the memory system110, and the operations of testing, debugging, coding, and verifying the memory system110. In short, the operations FUNCTION<1:8> may represent all the operations performed by the host102for controlling the memory system110.

Herein, the multiple operations FUNCTION<1:8> performed in the host102are illustrated to be eight operations, but this is for the sake of convenience in description. It is noted, more or less operations than the 8 operations may be performed in the host.

Also, as described with reference toFIG. 2, the memory144included in the memory system110is assumed to include the first to fifth internal storage regions1441,1442,1443,1444and1445.

Herein, it is further assumed that only the first internal storage region1441of the storage region of the memory144is accessed during a first operation FUNCTION<1> performed in the host102(1). In other words, it is assumed that data are inputted or outputted to/from the first internal storage region1441of the storage region of the memory144during the first operation FUNCTION<1> performed in the host102, and that no data are inputted/outputted to/from the remaining second to fifth internal storage regions1442,1443,1444and1445.

Also, it is assumed that only the first internal storage region1441and the second internal storage region1442of the storage region of the memory144are accessed during a second operation FUNCTION<2> performed in the host102as denoted by arrows2-1and2-2. In other words, it may be assumed that data are inputted/outputted to/from the first internal storage region1441and the second internal storage region1442of the storage region of the memory144during the second operation FUNCTION<2> performed in the host102, and that data are not inputted/outputted to/from the third to fifth internal storage regions1443,1444and1445.

Also, it is assumed that only the second internal storage region1442and the fourth internal storage region1444of the storage region of the memory144are accessed during a third operation FUNCTION<3> performed in the host102as denoted by arrows3-1and3-2. In other words, it may be assumed that data are inputted/outputted to/from the second internal storage region1442and the fourth internal storage region1444of the storage region of the memory144during the third operation FUNCTION<3> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the third internal storage region1443, and the fifth internal storage region1445.

Also, it is assumed that only the second internal storage region1442of the storage region of the memory144are accessed during a fourth operation FUNCTION<4> performed in the host102(4). In other words, it may be assumed that data are inputted/outputted to/from the second internal storage region1442of the storage region of the memory144during the fourth operation FUNCTION<4> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the third internal storage region1443, the fourth internal storage region1444and the fifth internal storage region1445.

Also, it is assumed that only the second internal storage region1442and the fifth internal storage region1445of the storage region of the memory144are accessed during a fifth operation FUNCTION<5> performed in the host102(5-1and5-2). In other words, it may be assumed that data are inputted/outputted to/from the second internal storage region1442and the fifth internal storage region1445of the storage region of the memory144during the fifth operation FUNCTION<5> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the third internal storage region1443, and the fourth internal storage region1444.

Also, it is assumed that the second internal storage region1442and the fifth internal storage region1445of the storage region of the memory144are accessed during a sixth operation FUNCTION<6> performed in the host102(6-1and6-2). In other words, it may be assumed that data are inputted/outputted to/from the second internal storage region1442and the fifth internal storage region1445of the storage region of the memory144during the sixth operation FUNCTION<6> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the third internal storage region1443, and the fourth internal storage region1444.

Also, it is assumed that only the third internal storage region1443of the storage region of the memory144are accessed during a seventh operation FUNCTION<7> performed in the host102(7). In other words, it may be assumed that data are inputted/outputted to/from the third internal storage region1443of the storage region of the memory144during the seventh operation FUNCTION<7> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the second internal storage region1442, the fourth internal storage region1444and the fifth internal storage region1445.

Also, it is assumed that only the fourth internal storage region1444of the storage region of the memory144are accessed during an eighth operation FUNCTION<8> performed in the host102(8). In other words, it may be assumed that data are inputted/outputted to/from the fourth internal storage region1444of the storage region of the memory144during the eighth operation FUNCTION<8> performed in the host102, and that data are not inputted/outputted to/from the first internal storage region1441, the second internal storage region1442, the third internal storage region1443, and the fifth internal storage region1445.

Each of the above described operations FUNCTION<1:8> performed in the host102is performed by selecting and accessing a predetermined internal storage region among the multiple internal storage regions1441,1442,1443,1444and1445included in the memory144according to the characteristics of the operation.

Therefore, it may be seen that an internal storage region may be accessed for at least one of the operations performed in the host102.

For example, as illustrated inFIG. 3, the first internal storage region1441of the storage region of the memory144is accessed when the first operation FUNCTION<1> or the second operation FUNCTION<2> is performed in the host102, and data DATA<0:1> are stored in the first internal storage region1441.

Also, the second internal storage region1442of the storage region of the memory144is accessed when the second operation FUNCTION<2>, the third operation FUNCTION<3>, the fourth operation FUNCTION<4>, the fifth operation FUNCTION<5>, or the sixth operation FUNCTION<6> is performed in the host102, and data DATA<2:6> are stored in the second internal storage region1442.

Also, the third internal storage region1443of the storage region of the memory144is accessed when the seventh operation FUNCTION<7> is performed in the host102, and a data DATA<7> is stored in the third internal storage region1443.

Also, the fourth internal storage region1444of the storage region of the memory144is accessed when the third operation FUNCTION<3> or the eighth operation FUNCTION<8> is performed in the host102, and data DATA<8:9> are stored in the fourth internal storage region1444.

Also, the fifth internal storage region1445of the storage region of the memory144is accessed when the fifth operation FUNCTION<5> or the sixth operation FUNCTION<6> is performed in the host102, and data DATA<10:11> are stored in the fifth internal storage region1445.

As described above, each of the internal storage regions1441,1442,1443,1444and1445included in the memory144may be accessed through one, two or more operations among the multiple operations FUNCTION<1:8> performed in the host102, dependent upon the characteristics of each operation.

Meanwhile, the memory system110does not know what operation makes the data DATA<0:11> stored in the internal storage regions1441,1442,1443,1444and1445included in the memory144. Only the host102may know what operation makes the data DATA<0:11> stored in the internal storage regions1441,1442,1443,1444and1445included in the memory144.

For example, the data DATA<2:6> may be stored in the second Internal storage region1442of the storage region of the memory144included in the memory system110through the second operation FUNCTION<2>, the third operation FUNCTION<3>, the fourth operation FUNCTION<4>, the fifth operation FUNCTION<5>, or the sixth operation FUNCTION<6> among the multiple operations FUNCTION<1:8> that may be performed in the host102. Herein, what data is stored in the second internal storage region1442through which operation is known in the host102. However, the memory system110does not know which operation of the host102makes the data DATA<2:6> stored in the second internal storage region1442of the memory144.

Herein, when the operations FUNCTION<1:8> performed in the host102are normally processed without an error, it does not matter whether the memory system110does or does not know what data DATA<0:11> are stored in the internal storage regions1441,1442,1443,1444and1445of the memory144, because the host102knows what data DATA<0:11> are stored in the internal storage regions1441,1442,1443,1444and1445of the memory144and properly manages the data DATA<0:11>.

However, the operations FUNCTION<1:8> being processed normally without an error in the host102is just an ideal case. The reality is that some of the operations FUNCTION<1:8> may not be normally processed due to a reason which is unknown in the host102.

If malfunction occurs in some of the operations FUNCTION<1:8> performed in the host102and thus information on what data DATA<0:11> are stored in the internal storage regions1441,1442,1443,1444and1445of the memory144is lost, the data stored in some internal storage regions of the internal storage regions1441,1442,1443,1444and1445may be managed erroneously, which may lead to an abnormal operation of the memory system110.

FIG. 4illustrates a memory management method according to an embodiment of the present invention. The method ofFIG. 4may be applied to the memory144ofFIGS. 1 to 3. For example, the method ofFIG. 4may be performed by the processor134of the memory controller130inFIG. 1.

Referring toFIG. 4, a plurality of operations FUNCTION<1:8> are performed in the host102, as described above with reference toFIG. 3. The storage region of the memory144included in the memory system110is divided into a plurality of internal storage regions (e.g., internal storage regions1441,1442,1443,1444and1445), which correspond to the operations FUNCTION<1:8>.

Compared to what was described above with reference toFIG. 3, metadata M<1:8> are now stored in the internal storage regions1441,1442,1443,1444and1445of the memory144along with the data DATA<0:11>.

First, it may be assumed that a total of 8 operations FUNCTION<1:8> are performed in the host102. Herein, the 8 operations FUNCTION<1:8> may be the operations of reading/writing/erasing data from/to a memory device150of the memory system110, and the operations of testing, debugging, coding and verifying the memory system110. In short, the operations FUNCTION<1:8> performed in the host102signify all the operations performed by the host102to control the memory system110.

Herein, the multiple operations FUNCTION<1:8> performed in the host102are illustrated to be eight operations, but this is for the sake of convenience in description, and it is also possible to perform more operations or less operations than the 8 operations.

As described with reference toFIGS. 2 and 3, the memory144included in the memory system110includes the first to fifth internal storage regions1441,1442,1443,1444and1445. In other words, an operation of dividing the storage region of the memory144into the multiple internal storage regions1441,1442,1443,1444and1445according to the usage of the memory system110is performed first in the host102.

Subsequently, when the host102requests the memory system110to write the data DATA<0:11> in the memory144of the memory system110, the memory system110performs an operation of selecting one internal storage region among the internal storage regions1441,1442,1443,1444and1445of the memory144based on the data characteristics information of the data DATA<0:11> according to a write request transferred from the host102.

After one internal storage region among the internal storage regions1441,1442,1443,1444and1445of the memory144is selected based on the data characterization information of the write data DATA<0:11> transferred from the host102, metadata M<1:8> including the data characterization information of the write data DATA<0:11> is generated, and the generated metadata M<1:8> is then stored in the selected internal storage region along with the write data DATA<0:11>.

In the illustrated example, the data characterization information of the write data DATA<0:11> transferred from the host102may be information on what operation among the operations FUNCTION<1:8> performed in the host102is to be performed when the write data DATA<0:11> are written in the memory device.

For example, when a first operation FUNCTION<1> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the first operation FUNCTION<1> is performed in the host102. Therefore, the first internal storage region1441among the internal storage regions1441,1442,1443,1444and1445of the memory144is selected corresponding to the first operation FUNCTION<1>. Subsequently, a first metadata M1including information indicating that the first operation FUNCTION<1> is performed in the host102is generated and stored in the first internal storage region1441along with the data DATA<0:11> transferred from the host102.

Also, when a second operation FUNCTION<2> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the second operation FUNCTION<2> is performed in the host102. Therefore, one internal storage region between the first internal storage region1441and the second internal storage region1442is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the second operation FUNCTION<2>. Subsequently, a second metadata M2including information indicating that the second operation FUNCTION<2> is performed in the host102is generated and stored in the internal storage region selected between the first internal storage region1441and the second internal storage region1442along with the data DATA<0:11> transferred from the host102. Herein, whether the second metadata M2and the data DATA<0:11> transferred from the host102are stored in the first internal storage region1441or the second internal storage region1442is decided based on how the second operation FUNCTION<2> is performed in the host102.

Also, when a third operation FUNCTION<3> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the third operation FUNCTION<3> is performed in the host102. Therefore, one internal storage region between the second internal storage region1442and the fourth internal storage region1444is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the third operation FUNCTION<3>. Subsequently, a third metadata M3including information indicating that the third operation FUNCTION<3> is performed in the host102is generated and stored in the internal storage region selected between the second internal storage region1442and the fourth internal storage region1444along with the data DATA<0:11> transferred from the host102. Herein, whether the third metadata M3and the data DATA<0:11> transferred from the host102are stored in the second internal storage region1442or the fourth internal storage region1444is decided based on how the third operation FUNCTION<3> is performed in the host102.

Also, when a fourth operation FUNCTION<4> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the fourth operation FUNCTION<4> is performed in the host102. Therefore, the second internal storage region1442is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the fourth operation FUNCTION<4>. Subsequently, a fourth metadata M4including information indicating that the fourth operation FUNCTION<4> is performed in the host102is generated and stored in the second internal storage region1442along with the data DATA<0:11> transferred from the host102.

Also, when a fifth operation FUNCTION<5> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the fifth operation FUNCTION<5> is performed in the inside of the host102. Therefore, one internal storage region between the second internal storage region1442and the fifth internal storage region1445is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the fifth operation FUNCTION<5>. Subsequently, a fifth metadata M5including information indicating that the fifth operation FUNCTION<5> is performed in the host102is generated and stored in the internal storage region selected between the second internal storage region1442and the fifth internal storage region1445along with the data DATA<0:11> transferred from the host102. Herein, whether the fifth metadata M5and the data DATA<0:11> transferred from the host102are stored in the second internal storage region1442or the fifth internal storage region1445is decided based on how the fifth operation FUNCTION<5> is performed in the host102.

Also, when a sixth operation FUNCTION<6> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the sixth operation FUNCTION<6> is performed in the host102. Therefore, one internal storage region between the second internal storage region1442and the fifth internal storage region1445is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the sixth operation FUNCTION<6>. Subsequently, a sixth metadata M6including information indicating that the sixth operation FUNCTION<6> is performed in the host102is generated and stored in the internal storage region selected between the second internal storage region1442and the fifth internal storage region1445along with the data DATA<0:11> transferred from the host102. Herein, whether the sixth metadata M6and the data DATA<0:11> transferred from the host102are stored in the second internal storage region1442or the fifth internal storage region1445is decided based on how the sixth operation FUNCTION<6> is performed in the host102.

Also, when a seventh operation FUNCTION<7> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that the seventh operation FUNCTION<7> is performed in the host102. Therefore, the third internal storage region1443is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the seventh operation FUNCTION<7>. Subsequently, a seventh metadata M7including information indicating that the seventh operation FUNCTION<7> is performed in the host102is generated and stored in the third internal storage region1443along with the data DATA<0:11> transferred from the host102.

Also, when an eighth operation FUNCTION<8> is performed in the host102and the host102requests the memory system110to write the data DATA<0:11> in the memory144, the data characterization information of the data DATA<0:11> is information representing that eighth operation FUNCTION<8> is performed in the host102. Therefore, the fourth internal storage region1444is selected among the internal storage regions1441,1442,1443,1444and1445of the memory144corresponding to the eighth operation FUNCTION<8>. Subsequently, an eighth metadata M8including information indicating that the eighth operation FUNCTION<8> is performed in the host102is generated and stored in the fourth internal storage region1444along with the data DATA<0:11> transferred from the host102.

To sum up, when the write data DATA<0:11> transferred from the host102is received, the memory system110generates the metadata M<1:8> including the data characterization information of the write data DATA<0:11> transferred from the host102, and stores the generated metadata M<1:8> in the memory144along with the data characterization information of the write data DATA<0:11> transferred from the host102. Therefore, each of the internal storage regions1441,1442,1443,1444and1445of the memory144not only stores the data DATA<0:11> but also stores the metadata M<1:8> representing what operation the stored data DATA<0:11> correspond to.

Meanwhile, described in the above is that the number of the data DATA<0:11> transferred from the host102to the memory144of the memory system110and stored in the memory144of the memory system110is assumed to be 12 data DATA<0:11> and that a zeroth data DATA0corresponds to the first operation FUNCTION<1> in the host102; a first data DATA1and a second data DATA2correspond to the second operation FUNCTION<2> in the host102; a third data DATA3and an eighth data DATA8correspond to the third operation FUNCTION<3> in the host102; a fourth data DATA4corresponds to the fourth operation FUNCTION<4> in the host102; a fifth data DATA5and a tenth data DATA10correspond to the fifth operation FUNCTION<5> in the host102; a sixth data DATA6and an eleventh data DATA11correspond to the sixth operation FUNCTION<6> in the host102; a seventh data DATA7corresponds to the seventh operation FUNCTION<7> in the host102; and a ninth data DATA9corresponds to the eighth operation FUNCTION<8> in the host102. However, the above description is simply no more than an example. It is actually difficult to predict to what operation among the operations FUNCTION<1:8> of the host102, the data DATA<0:11> transferred from the host102to the memory144corresponds to. The memory system110just includes the data characterization information of the data DATA<0:11> in the metadata M<1:8> and stores the metadata M<1:8> including the data characterization information in the memory144, when the data characterization information of the data DATA<0:11> is transferred from the host102to the memory system110along with the data DATA<0:11>. The method ofFIG. 4may be performed by the processor134of the memory controller130inFIG. 1.

Referring toFIG. 5A, an operation performed when a write request for the data DATA<0:11> is transferred from the host102is described in detail among the memory management method ofFIG. 4, according to an embodiment of the present invention.

First, in step S10, the storage region of the memory144of the memory system110is divided into a plurality of internal storage regions, for example five internal storage regions1441,1442,1443,1444and1445as illustrated inFIG. 4.

In step S20, when the host102requests the memory system110to write the data DATA<0:11> in the memory144of the memory system110after the step S10, one internal storage region among the plurality of the internal storage regions1441,1442,1443,1444and1445of the memory144is selected based on the data characterization information of the write data DATA<0:11> transferred from the host102.

In step S30, the metadata M<1:8> which includes the data characterization information of the write data DATA<0:11> is generated, and the generated metadata M<1:8> is stored in the selected internal storage region along with the write data DATA<0:11>.

Hereafter, the operation in step S30is described in more detail. The step S30includes steps S31, S32, S33and S34.

In step S31, the metadata M<1:8> including the data characterization information of the write data DATA<0:11> transferred from the host102is generated. Since the data characterization information of the write data DATA<0:11> has been described above with reference toFIG. 4, further description thereof is omitted herein.

In step S32, the sum of the size of the write data DATA<0:11> and the size of the metadata M<1:8> generated in step S31is compared with the size of the empty space of the selected internal storage region1441,1442,1443,1444or1445, which is selected in step S20.

When it turns out in step S32that the sum of the size of the write data DATA<0:11> and the size of the metadata M<1:8> generated in step S31is not greater than the size of the empty space of the selected internal storage region1441,1442,1443,1444or1445, the write data DATA<0:11> and the metadata M<1:8> generated in the operation of step S31are stored in the empty space of the selected internal storage region1441,1442,1443,1444or1445, which is selected in the step S20, in step S33.

When it turns out in step S32that the sum of the size of the write data DATA<0:11> and the size of the metadata M<1:8> generated in step S31is greater than the size of the empty space of the selected internal storage region, the write data DATA<0:11> and the metadata M<1:8> generated in the operation of the step S31are not stored in the empty space of the selected internal storage region, (which was selected in step S20). Accordingly, overflow and storage failure information is transferred to the host102in step S34.

Referring back toFIG. 4, an example of the operations of the steps S31to S34will now be described.

In the first place, it may be assumed that the third operation FUNCTION<3> is performed in the host102and a third data DATA3is requested to be written in the second internal storage region1442of the memory144. In step S31, the data characterization information of the third data DATA3is generated as the third metadata M3. The data characterization information of the third data DATA3is the information representing that the third data DATA3requested to be written in the second internal storage region1442of the memory144is transferred to the memory system110through the third operation FUNCTION<3> performed in the host102.

After the data characterization information of the third data DATA3is generated as the third metadata M3, it is determined in step S32whether the sum of the size of the third data DATA3and the size of the third metadata M3is greater than the size of the empty space of the second internal storage region1442.

When the sum of the size of the third data DATA3and the size of the third metadata M3is not greater than the size of the empty space of the second internal storage region1442, the third data DATA3and the third metadata M3are stored in the second internal storage region1442in the step S33.

When the sum of the size of the third data DATA3and the size of the third metadata M3is greater than the size of the empty space of the second internal storage region1442, the third data DATA3and the third metadata M3are not stored in the second internal storage region1442and instead overflow and storage failure information is transferred to the host102in step S34.

Herein, the overflow and storage failure information transferred to the host102represents that the third data DATA3cannot be stored in the memory144because an unpredictable error occurs in the third operation FUNCTION<3> performed in the host102. In other words, the host102may be informed that a problem has occurred in the write operation of the third operation FUNCTION<3> performed in the host102and, hence, the host102may appropriately cope with the problem.

Hereafter, the operation of the step S32is described in detail. The step S32includes steps S321, S322, S323and S324.

In step S321, the size of an address region corresponding to the sum of the write data DATA<0:11> and the metadata M<1:8> generated in the operation of the step S31is calculated.

In step S322, the size of the address region calculated in the step S321is compared with the size of an address region corresponding to the empty space of the selected internal storage region1441,1442,1443,1444or1445, which is selected in step S20.

When in step S323the size of the address region calculated in step S321is smaller than the size of the address region corresponding to the empty space of the selected internal storage region1441,1442,1443,1444or1445, which is selected in the step S20, the third data DATA3and the third metadata M3are written in the second internal storage region1442in step S33.

When it turns out in the step S324that the size of the address region calculated in the step S321is greater than the size of the address region corresponding to the empty space of the selected internal storage region1441,1442,1443,1444or1445, which is selected in the step S20, the third data DATA3and the third metadata M3are not written in the second internal storage region1442and instead overflow and storage failure information is transferred to the host102in the step S34.

Referring toFIG. 5B, an operation performed when a read request for the data DATA<0:11> is transferred from the host102is described in detail among the memory management method ofFIG. 4according to the embodiment of the present invention.

First, in step S10, the storage region of the memory144of the memory system110is divided into a plurality of internal storage regions, for example the five internal storage regions1441,1442,1443,1444and1445according to the operations of the host102, as described above with reference toFIGS. 4 and 5A.

When the host102requests the memory system110to read the data DATA<0:11> from the memory144of the memory system110after the step S10, one internal storage region among the internal storage regions1441,1442,1443,1444and1445of the memory144is selected in step S40based on the data characterization information of the data DATA<0:11> according to the read request transferred from the host102.

In step S50, the metadata M<1:8> corresponding to the read-requested data DATA<0:11> is read from the selected internal storage region which is selected in the step S40. In other words, the operation of step S50is an operation of reading the metadata M<1:8> corresponding to the read-requested data DATA<0:11> out of the selected internal storage region1441,1442,1443,1444or1445, which is selected in the step S40, before reading the data DATA<0:11> according to the read request transferred from the host102out of the selected internal storage region1441,1442,1443,1444or1445.

Subsequently, in step S60, it is determined whether the data characterization information of the data DATA<0:11> that is stored through the operation of the step S30according to the write request transferred from the host102and included in the metadata M<1:8>, which is read in the step S50, is the same as the data characterization information of the data DATA<0:11> according to the read request transferred from the host102.

When the data characterization information of the data DATA<0:11> that is stored through the operation of step S30according to the write request transferred from the host102and included in the metadata M<1:8>, which is read in the step S50is the same as the data characterization information of the data DATA<0:11> according to the read request transferred from the host102(step S60, YES), the data DATA<0:11> according to the read request transferred from the host102is read out of the selected internal storage region1441,1442,1443,1444or1445in step S80.

When the data characterization information of the data DATA<0:11> that is stored through the operation of the step S30according to the write request transferred from the host102and included in the metadata M<1:8>, which is read in the step S50is not the same as the data characterization information of the data DATA<0:11> according to the read request transferred from the host102(step S60, NO), the data DATA<0:11> according to the read request transferred from the host102is not read out of the selected Internal storage region1441,1442,1443,1444or1445and data characteristics discrepancy and read failure information is transferred to the host102in step S70.

Referring back toFIG. 4, the operations of steps S40to S80are described, hereafter, with the help of an example.

First, it may be assumed that the data DATA<0:11> are stored in the multiple internal storage regions1441,1442,1443,1444and1445of the memory144as illustrated inFIG. 4. Also, it may be assumed that there is a normal case where the third data DATA3is requested to be read out of the memory144as the third operation FUNCTION<3> is performed in the host102, and there is an abnormal case where the fourth data DATA4is requested to be read out of the memory144as the third operation FUNCTION<3> is performed in the host102.

Since both of the third data DATA3and the fourth data DATA4according to the read request transferred from the host102are stored in the second internal storage region1442among the internal storage regions1441,1442,1443,1444and1445of the memory144, the second internal storage region1442is selected in step S40.

After the second internal storage region1442is selected in step S40, the third metadata M3corresponding to the third data DATA3and the fourth metadata M4corresponding to the fourth data DATA4are read out of the second internal storage region1442in step S50. Herein, the third data DATA3and the fourth data DATA4that are requested by the host102to be read are not read in step S50.

After the third metadata M3is read in the step S50, as a first operation, it is determined in step S60whether the data characterization information of the third data DATA3that is stored through the operation of step S30according to the write request transferred from the host102and included in the third metadata M3is the same as the data characterization information of the third data DATA3according to the read request transferred from the host102. Likewise, after the fourth metadata M4is read in the step S50, as a second operation, it is determined in step S60whether the data characterization information of the fourth data DATA4that is stored through the operation of the step S30according to the write request transferred from the host102and included in the fourth metadata M4is the same as the data characterization information of the fourth data DATA4according to the read request transferred from the host102.

Hereafter, the first operation of step S60is described.

First, the data characterization information of the third data DATA3according to the write request transferred from the host102which are included in the third metadata M3corresponding to the third data DATA3that is stored in the second internal storage region1442of the memory144represents that the third operation FUNCTION<3> is performed in the host102.

Also, since the third data DATA3is requested to be read while the host102performs the third operation FUNCTION<3>, the data characterization information of the third data DATA3according to the read request transferred from the host102represents that the third operation FUNCTION<3> is performed in the host102.

This shows that the data characterization information of the third data DATA3according to the write request transferred from the host102and included in the third metadata M3corresponding to the third data DATA3that is stored in the second internal storage region1442of the memory144is the same (step S60, YES) as the data characterization information of the third data DATA3according to the read request transferred from the host102. Therefore, in step $80, the third data DATA3according to the read request transferred from the host102is read out of the selected second internal storage region1442, which is selected in step S40.

Hereafter, the second operation of step S60is described.

First, the data characterization information of the fourth data DATA4according to the write request transferred from the host102which is included in the fourth metadata M4corresponding to the fourth data DATA4that is stored in the second internal storage region1442of the memory144represents that the fourth operation FUNCTION<4> is performed in the host102.

Also, since the fourth data DATA4is requested to be read while the host102performs the third operation FUNCTION<3>, the data characterization information of the fourth data DATA4according to the read request transferred from the host102represents that the third operation FUNCTION<3> is performed in the host102.

This shows that the data characterization information of the fourth data DATA4according to the write request transferred from the host102and included in the fourth metadata M4corresponding to the fourth data DATA4that is stored in the second internal storage region1442of the memory144is not the same (step S60, NO) as the data characterization information of the fourth data DATA4according to the read request transferred from the host102. Therefore, in the step S70, the fourth data DATA4according to the read request transferred from the host102is not read out of the selected second internal storage region1442, which is selected in step S40, and data characteristics discrepancy and read failure information is transferred to the host102.

Herein, the data characteristics discrepancy and read failure information transferred to the host102in step S70informs the host102that an unpredictable error occurs in the third operation FUNCTION<3> performed in the host102and the fourth data DATA4, which cannot be read through the third operation FUNCTION<3>, is tried to be read. In other words, through the operation of the step S70, the host102may be informed that a problem has occurred in the read operation of the third operation FUNCTION<3> performed in the host102and the host102may appropriately cope with the problem.

According to the embodiments of the present invention, when a host requests a memory system to write a data in a memory of the memory system, data characterization information of the data to be stored upon the write request from the host is stored along with the write data as metadata.

When the data stored upon the write request from the host is requested to be read, the data characterization information of the stored data according to a read request may be compared with the data characterization information of the stored data according to the write request that is included in the metadata. Through a comparison of data characterization information an erroneous read request may thus be detected.