High-resolution synchronous delay line

A synchronous delay line (SDL) for generating delayed signals synchronized with a clock signal is described. The present SDL includes a phase generator and a plurality of serially coupled voltage controlled delay elements. The phase generator takes the clock signal and generates a first trigger signal and a second trigger signal, which are substantially deskewed with respect to each other. Each of the delay elements receives two trigger inputs and outputs a delayed signal and two trigger outputs. The first and second trigger signals are coupled to one of the delay elements as trigger inputs. Each transition of the first and second trigger signals triggers the propagation of two waves through the delay line. The present SDL has a minimum tap-to-tap delay of only one inverter delay, versus a minimum tap-to-tap delay of two NAND gates in prior SDLs. Thus, the present SDL provides for double the number of output taps, and hence, double the resolution as compared to prior SDLs.

FIELD OF THE INVENTION 
The present invention relates to the generation of timing pulses having 
precise delays. More particularly, the present invention relates to a high 
resolution synchronous delay line for use in metal oxide-semiconductor 
(MOS) integrated circuits. 
BACKGROUND OF THE INVENTION 
Complementary metal oxide semiconductor (CMOS) integrated circuits often 
perform complex multistep operations having critical timing. A reference 
clock can provide at most two precision edges; e.g. the leading and 
trailing edges. Multistep operations that must be triggered at other 
points in the clock period therefore cannot use the reference clock as a 
trigger source. 
The synchronous delay line (SDL)is a MOS circuit function which provides 
timing edges at precise, evenly-spaced intervals, and is insensitive to 
variations in processing, Vcc, or temperature. These timing edges enable 
the triggering of logic operations practically at any time with high 
resolution and precision. 
A prior art synchronous delay line is shown in FIG. 1. This SDL was 
disclosed in U.S. Pat. No. 4,994,695, entitled "Synchronous Delay Line 
with Quadrature Clock Phases", which is assigned to the assignee of the 
present invention. SDL 20 is comprised of a phase generator 21, a 
plurality of series coupled voltage-controlled delay (VCD) stages 22, and 
a sample-and-hold circuit 23. SDL 20 includes 8 VCD stages, with each VCD 
stage 22 providing an output, or tap, of SDL 20. 
FIG. 2 illustrates prior art phase generator 21, which includes a D-type 
master latch, a D-type slave latch, an edge-triggered D-type flip-flop, 
and several buffers. Phase generator 21 accepts the reference clock signal 
CLK and divides it by two to generate two pairs of complementary clock 
phases, PHI.sub.1 /PHI.sub.2 and PHIQ.sub.1 /PHIQ.sub.2. Two trigger 
signals PA.sub.0 and PB.sub.0 are also generated by the phase generator 
21. PA.sub.0 and PB.sub.0 are also derived from the reference clock signal 
CLK and are complementary to each other. PA.sub.0 and PB.sub.0 are 
coupled to the first VCD stage 22 as trigger inputs. Although clock phases 
PHI.sub.1 and PHI.sub.2 could serve as trigger inputs, separate trigger 
inputs are generated due to the heavy capacitive loads that PHI.sub.1 and 
PHI.sub.2 typically drive. 
The latches and flip-flops of FIG. 2 may be implemented in different ways, 
each one having advantages. FIG. 3A illustrates typical prior art latch 
that samples its D-input when CLK is low. FIG. 3B illustrates a typical 
prior art phase that samples its D-input when CLK is high. If the rising 
edge of CLK is used as the reference edge then the latch of FIG. 3A is 
used as the master latch and the latch of FIG. 3B is used as the slave 
latch in the circuit of FIG. 2. On the other hand, if the falling edge of 
CLK is designated as the reference edge then the roles of the latches of 
FIG. 3A and FIG. 3B are reversed. 
FIG. 4 illustrates the waveforms generated by prior art phase generator 21 
when using the latches of FIG. 3 and the rising edge of CLK as the 
reference. FIG. 4 reveals several characteristics of the prior art phase 
generator. First, PHI.sub.1 is logically the same as PA.sub.0 ; they both 
divide the frequency of CLK by two. Similarly, PHI.sub.2 and PB.sub.0 are 
logically identical to each other and are logical complements of PHI.sub.1 
and PA.sub.0. Second, the rising edge of PHIQ.sub.1 always leads the 
falling edge of PHIQ.sub.2, just as the rising edge of PHIQ.sub.2 always 
leads the falling edge of PHIQ.sub.1. This characteristic arises from the 
latch of FIG. 3A, which serves as the master latch. In this circuit, Q can 
go low only after Q goes high, and conversely, Q can go low only after Q 
goes high. Third, the falling edge of PHI.sub.1 always leads the rising 
edge of PHI.sub.2, while the falling edge of PHI.sub.2 always leads the 
rising edge of PHI.sub.1. These same relationships hold for PA.sub.0 and 
PB.sub.0. The structure of the latch of FIG. 3B, which serves as the slave 
latch, gives rise to this characteristic. Q can go high only after Q goes 
low, and conversely, Q can go high only after Q goes low. 
These characteristics cause an inherent skew between trigger signals 
PA.sub.0 and PB.sub.0 that cannot be eliminated. 
The outputs of each VCD stage 22, designated as PA.sub.n and PB.sub.n, are 
coupled as trigger inputs to subsequent stages. 
A prior art VCD 22, or delay element 22, is shown in FIG. 5. The delay 
element 22 includes two cross-coupled NAND gates, A and B. Due to the 
design of delay element 22, only one of the complementary trigger inputs, 
PA.sub.0 or PB.sub.0, will propagate a signal, or wave, down SDL 20. The 
SDL 20 is triggered when either of the trigger inputs, PA.sub.0 or 
PB.sub.0, transistions from high to low. The route followed by the 
propagating wave is different in each clock phase. FIG. 6 indicates the 
route followed by the wave generated when PA.sub.0 goes low and PB.sub.0 
goes high. FIG. 7 shows the route followed by the wave generated when 
PA.sub.0 goes high and PB.sub.0 goes low. 
Clearly, only the low-going trigger input triggers propagation. The other 
trigger input, the high-going one, simply enables wave propagation. The 
timing skew between trigger inputs PA.sub.0 and PB.sub.0 is not critical: 
the enabling input may switch within a large window surrounding the 
switching of the triggering trigger input. 
The delay between taps of SDL 20 is equal to the delay through the two 
gates, A and B, in each delay element 22. On alternate clocks, the 
propagation path of the wave through each delay element is reversed so 
that the delay through an arbitrary delay element is t.sub.dh (A)+t.sub.dl 
(B) for one clock, and t.sub.dl (A)+t.sub.dh (B) for the next clock, where 
t.sub.dh is the gate high-going delay time, and t.sub.dl is the gate 
low-going delay time. Because the gates are matched in all respects, 
including in layout, the delay through the gates on alternate clocks is 
identical. Consequently, the delay through the delay element 22 on 
alternate clocks is identical. 
The delay control voltage V.sub.CTRL controls the delay time of each delay 
element 22 and, consequently, the SDL end-to-end delay. As V.sub.CTRL 
increases so does the SDL end-to-end delay. Through negative feedback, 
V.sub.CTRL stabilizes at a value which causes the SDL end-to-end delay to 
just equal the clock period TP. Thus, the higher the operating frequency, 
the lower the steady-state value of V.sub.CTRL. 
The resolution of SDL 20 is limited by the tap-to-tap delay t.sub.del. The 
delay is given by t.sub.del =TP/N, where N is the number of SDL taps. The 
number of taps is determined by the highest operating frequency of the 
integrated circuit in which the SDL is implemented. At the highest 
operating frequency V.sub.CTRL is approximately OV because the SDL 
operates at the highest frequency with minimum delay. Thus, the maximum 
number of SDL taps that can be implemented is determined by the SDL 
end-to-end delay at the maximum frequency. Because each delay element 
contributes one t.sub.dh and one t.sub.dl of delay, the maximum number of 
taps N.sub.max is given by 
EQU N.sub.max =TP.sub.min /(t.sub.dh,min +t.sub.dl,min) 
where: 
TP.sub.min is the clock period at the maximum frequency; and 
t.sub.dh,min and t.sub.dl,min are the minimum values of t.sub.dh and 
t.sub.dl, respectively, which are obtained when V.sub.CTRL is 
approximately OV. 
In other words, the maximum number of taps that can be implemented in a 
prior art SDL, which is synonymous with the maximum resolution obtainable 
from a prior art SDL, is limited by the fact that the delay contributed by 
each delay element is two gate delays. This is less than optimum 
resolution for certain high performance multi-step operations. 
SUMMARY OF THE INVENTION 
A synchronous delay line (SDL) for generating delayed signals synchronized 
with a clock signal is described. The present SDL includes a phase 
generator and a plurality of serially coupled voltage controlled delay 
elements. The phase generator takes the clock signal and generates a first 
trigger signal and a second trigger signal, which are substantially 
deskewed with respect to each other. Each of the delay elements receives 
two trigger inputs and outputs a delayed signal and two trigger outputs. 
The first and second trigger signals are coupled to one of the delay 
elements as trigger inputs. Each transition of the first trigger signal 
and second trigger signal causes the propagation of two waves through the 
SDL. 
It is an object of the present invention to provide a high resolution, 
precision SDL. 
It is another object of the present invention to provide an SDL with a 
tap-to-tap delay of no more than one gate delay. 
Another object of the present invention is to provide a method of deskewing 
trigger signals generated by a phase generator. 
Other objects, features, and advantages of the present invention will be 
apparent from the accompanying drawings and from the detailed description 
that follows below.

DETAILED DESCRIPTION 
As will be described in detail below, using the present voltage-controlled 
delay elements the present SDL provides double the number of taps and 
twice the resolution of prior SDLs given the same end-to-end delay. The 
present delay elements propagate two parallel waves through the present 
SDL. Eliminating the skew between the two parallel waves requires 
generating two deskewed trigger signals. Unlike prior art phase 
generators, the present phase generator may be adjusted to eliminate the 
skew between trigger signals. 
FIGS. 8A-8B illustrate in block diagram form the high resolution 
synchronous voltage-controlled delay line 40 of the present invention. 
SDL 40 includes phase generator 41, several serially coupled delay elements 
42a-42p and sample-and-hold circuit 43. The number of taps available from 
SDL 40 is a function of the number of delay elements 42, which is a design 
choice. 
Phase generator 41 receives reference clock signal CLK 60 as its input. 
Phase generator 41 divides the frequency of CLK 60 by two to generate two 
pairs of complementary clock phases, PHI.sub.1 /PHI.sub.2 62/64 and 
PHIQ.sub.1 /PHIQ.sub.2 66/68. Although phase generator 41 divides CLK 60 
by two, the actual division factor is a matter of choice. 
In-phase clock signals, PHI.sub.1 62 and PHI.sub.2 64, are complementary to 
each other and in-phase with reference clock signal CLK 60. In practice a 
slight time lag may exist between CLK 60 and PHI.sub.1 /PHI.sub.2 62/64, 
but such a lag is not critical to the present SDL. Quadrature clock phases 
PHIQ.sub.1 66 and PHIQ.sub.2 68 are complementary to each other and are 
shifted approximately 90.degree. with respect to both CLK 60 and PHI.sub.1 
/PHI.sub.2 62/64. 
Phase generator 41 also outputs two complementary trigger signals, 
WVA.sub.0 70 and WVB.sub.0 72, which are also derived from CLK 60 and have 
a 50% duty cycle. WVA.sub.0 70 and WVB.sub.0 72 are applied as trigger 
inputs to the first delay element, delay element 42a. Although clock 
phases PHI.sub.1 62 and PHI.sub.2 64 could serve as the trigger inputs to 
delay element 42a, separate trigger inputs WVA.sub.0 70 and WVB.sub.0 72 
are utilized because PHI.sub.1 62 and PHI.sub.2 64 are typically slowed 
down by the heavy capacitive loads they drive. 
The various signals generated by phase generator 41 are shown schematically 
in FIG. 9. CLK 60 has a predetermined clock frequency; the clock period is 
designated as TP. Because of the divide-by-two operation of phase 
generator 41, each of the clock phases, PHI.sub.1 62 and PHI.sub.2 64, is 
high for a period TP and low for a period TP. PHIQ.sub.1 66 is a 
time-shifted version of PHI.sub.1 62. Similarly, PHIQ.sub.2 68 is a 
time-shifted version of PHI.sub.2 64. In the preferred embodiment, the 
time shift between PHI.sub.1 /PHI.sub.2 62/64 and PHIQ.sub.1 /PHIQ.sub.2 
66/68 corresponds to approximately 90.degree.. 
As can be seen in FIGS. 8A-8B, phases PHI.sub.1 62 and PHI.sub.2 64 are 
coupled to interior delay elements 42c-42n and quadrature phases 
PHIQ.sub.1 66 and PHIQ.sub.2 68 are coupled to exterior delay elements 
42a, 42b, 42o, 42p. 
The number of delay elements connected to phase pair PHI.sub.1 /PHI.sub.2 
and to phase pair PHIQ.sub.1 /PHIQ.sub.2 is, to a certain extent, 
flexible. The designer can choose how many delay elements to connect to 
each phase pair as long as the resulting high and low times of the output 
taps are solid. Usually, about 1/4-1/2 the taps would be connected to 
PHIQ.sub.1 /PHIQ.sub.2 66/68 and about 3/4-1/2 the taps to PHI.sub.1 
/PHI.sub.2 62/64. 
In response to trigger signals WVA.sub.0 70 and WVB.sub.0 72 two parallel 
waves, one positive and one negative, propagate through delay elements 
42a-42p. Positive waves are triggered by one of the trigger signals 
WVA.sub.0 70 and WVB.sub.0 72 going high. Similarly, negative waves are 
triggered by one of the trigger signals 70 and 72 going low. In one clock 
cycle, WVA.sub.0 70 triggers a positive wave and WVB.sub.0 72 triggers a 
negative wave. In the next clock cycle WVA.sub.0 70 triggers a negative 
wave and WVB.sub.0 triggers a positive wave. Positive waves provide 
outputs to even-numbered taps and negative waves provide outputs to 
odd-numbered taps. 
Any skew between WVA.sub.0 70 and WVB.sub.0 72 causes the tap-to-tap delay 
of synchronous delay line 40 to be unequal. Two types of skew are 
possible. In one type of skew, high-going waves generated by WVA.sub.0 or 
WVB.sub.0 lead their associated low-going waves, generated by WVB.sub.0 or 
WVA.sub.0. This situation is illustrated in FIG. 10A. When high-going 
waves lead, even numbered tap outputs lead the odd numbered tap outputs. A 
second type of skew, illustrated in FIG. 10B occurs when the high-going 
waves generated by WVA.sub.0 or WVB.sub.0 lag their associated low-going 
waves, generated by WVB.sub.0 or WVA.sub.0. Lagging high-going waves cause 
the even numbered tap outputs to lag the odd-numbered tap outputs. 
Deskewing trigger signals WVA.sub.0 70 and WVB.sub.0 72 requires precise 
alignment of the high-going and low-going waves. 
A schematic diagram of phase generator 41 is shown in FIG. 11. Unlike prior 
art phase generators, phase generator 41 may be adjusted to eliminate skew 
between trigger signals 70 and 72. Phase generator 41 includes two 
flip-flops 61 and 63, pass network 65 and a plurality of inverters. 
Flip-flops 61 and 63 are D-type level-triggered flip-flops, which operate 
as master and slave flip-flops, respectively. Master flip-flop 61 
generates PHIQ.sub.1 66, as well as the D input to flip-flop 63. The Q 
output of flip-flop 61 serves as PHIQ.sub.2 68. PHI.sub.1 62 is derived 
from the Q output of slave flip-flop 63, while PHI.sub.2 64 is derived 
from the Q output of flip-flop 63. Each of the Q and Q outputs from 
flip-flops 61 and 63 are buffered before being output as PHI.sub.1 
/PHI.sub.2 62/64 and PHIQ.sub.1 /PHIQ.sub.2 66/68. PHI.sub.2 64 is coupled 
back as the D input to flip-flop 61. 
Reference clock signal CLK 60 is coupled to the clock inputs of flip-flops 
61, 63, and pass network 65. The outputs from master flip-flop 61 provide 
a nominal shift of 90.degree. with respect to the outputs from slave 
flip-flop 63. The 90.degree. shift occurs when the duty cycle of CLK 60 is 
at 50%. If the duty cycle of CLK 60 is not 50%, then the shift is either 
less than or more than 90.degree. depending on the duty cycle. The actual 
amount of shift is not critical to the present SDL, as long as the shift 
provides for sufficient low and high times for the respective tap outputs. 
Pass network 65 generates trigger signals WVA.sub.0 70 and WVB.sub.0 72. 
Pass network 65 allows trigger signals WVA.sub.0 70 and WVB.sub.0 72 to 
transition in opposite directions independently of each other. Both 
signals 70 and 72 transition when CLK 60 goes high. The direction in which 
WVA.sub.0 70 transitions depends upon PHIQ.sub.2 68, while the direction 
in which WVB.sub.0 72 transitions depends upon PHIQ.sub.1 66. As seen in 
FIG. 11, pass network 65 includes a number of transistors, which are also 
referred to as pass devices herein. 
When CLK 60 goes low, pass devices P.sub.1A and N.sub.1A turn on connecting 
WVA.sub.0 70 to PHI.sub.1 62. Because pass devices N.sub.2A and P.sub.2A 
are turned off, WVA.sub.0 70 is disconnected from PHIQ.sub.2 68. Thus, 
WVA.sub.0 70 is unaffected by the transition of PHIQ.sub.2 68, which 
occurs when CLK 60 goes low. Similarly, WVB.sub.0 72 is connected to 
PHI.sub.2 64 while CLK 60 is low because pass devices P.sub.1B and 
N.sub.1B are on. Pass devices P.sub.2B and N.sub.2B are turned off, 
disconnecting WVB.sub.0 72 from PHIQ.sub.1 66. 
WVA.sub.0 70 and WVB.sub.0 72 transition after PHIQ.sub.1 66 and PHIQ.sub.2 
68 are stable and when CLK 60 goes high. When CLK 60 goes high, pass 
devices P.sub.1A and N.sub.1A turn off and devices P.sub.2A and N.sub.2A 
turn on. When this occurs, the state of WVA.sub.0 70 depends upon 
PHIQ.sub.2 68. If PHIQ.sub.2 68 is high, WVA.sub.0 70 is connected to 
ground via pass device N.sub.3A. On the other hand, if PHIQ.sub.2 68 is 
low, WVA.sub.0 70 is connected to V.sub.cc, approximately 2.5 volts to 5 
volts, via P.sub.3A. 
Again, WVB.sub.0 72 operates analogously to WVA.sub.0 70. When CLK 60 goes 
high pass devices P.sub.1B and N.sub.1B turn off and pass devices N.sub.2B 
and P.sub.2B turn on. The state of WVB.sub.0 72 now depends upon 
PHIQ.sub.1 66. If PHIQ.sub.1 66 is high, WVB.sub.0 72 is connected to 
ground via pass device N.sub.3B. If PHIQ.sub.1 66 is low, WVB.sub.0 72 is 
connected to V.sub.cc via pass device P.sub.3B. 
Pass network 65 thus generates trigger signals 70 and 72 that are mutually 
independent. As a result, WVA.sub.0 70 and WVB.sub.0 72 can transition 
substantially simultaneously, thereby greatly reducing the skew between 
signals 70 and 72. 
Any remaining skew between trigger signals 70 and 72 can be removed through 
proper selection of pass device sizes prior to fabrication. Because the 
rise and fall times of WVA.sub.0 70 and WVB.sub.0 72 are mutually 
independent, their rise and fall times may be adjusted independently. The 
rise time of WVA.sub.0 70 depends on the size of pass devices P.sub.2A and 
P.sub.3A, which connect WVA.sub.0 70 to V.sub.cc when PHIQ.sub.2 68 is low 
and CLK 60 goes high. The size of pass devices N.sub.2A and N.sub.3A 
determine the fall time of WVA.sub.0 70 because they connect WVA.sub.0 70 
to ground when PHIQ.sub.2 68 is high and CLK 60 goes high. The rise time 
of WVB.sub.0 72 is determined solely by the size of pass devices P.sub.2B 
and P.sub.3B because they connect WVB.sub.0 72 to V.sub.cc when PHIQ.sub.1 
66 is low and CLK 60 goes high. Similarly, the size of pass devices 
N.sub.2B and N.sub.3B determine the fall time of WVB.sub.0 72 because they 
connect WVB.sub.0 72 to ground when CLK 60 goes high and PHIQ.sub.1 66 is 
high. 
The independence of the rise and fall times of WVA.sub.0 70 and WVB.sub.0 
72 allows relatively easy adjustments to eliminate skew between signals 70 
and 72. For example, the rise time of WVA.sub.0 70 can be decreased with 
respect to its fall time by increasing the ratio of the sizes of pass 
devices P.sub.2A and P.sub.3A relative to the sizes of pass devices 
N.sub.2A and N.sub.3A. We will define this ratio, which we shall call 
ratio A, as: 
##EQU1## 
Similarly, the rise time of WVA.sub.0 70 relative to its fall time can be 
increased by decreasing ratio A. The rise and fall times of WVB.sub.0 72 
can be adjusted by adjusting ratio B, which we denote as: 
##EQU2## 
The skew between WVA.sub.0 70 and WVB.sub.0 72 can be adjusted in 
simulations prior to fabrication by adjusting ratio A and ratio B until 
WVA.sub.0 70 and WVB.sub.0 72 are completely deskewed. 
In FIG. 12 a schematic diagram of the present delay element 42 is shown. 
Delay element 42 includes three inverters, 80, 82, 84, two 
voltage-controlled capacitors, 86 and 88, and a pass network 90. Any 
device providing inversion, such as a NAND gate or a NOR gate, may be used 
in place of inverters 80 and 82; however, inverters are preferred because 
their delay is typically less than that of a NAND or NOR gate. Delay 
element 42 is implemented in complementary metal-oxide-semiconductor 
(CMOS) technology in the preferred embodiment; however, any of a number of 
MOS technologies could be used. 
A pair of trigger inputs WVA.sub.n 92 and WVBA.sub.n 94 are coupled to 
inverters 80 and 82. In the case of the delay element 42a, WVA.sub.0 70 is 
input to inverter 80 and WVB.sub.0 72 is input to inverter 82. In each 
succeeding delay element the wave outputs from the previous stage are 
input as trigger inputs. Thus, WVA.sub.1 and WVB.sub.1 are input as 
trigger inputs to delay element 42b. The trigger outputs from each stage 
of SDL 40 are just inverted, time-delayed versions of the trigger inputs 
to that stage. 
The delay through inverters 80 and 82, and thus the delay through delay 
element 42, is adjusted via voltage-controlled capacitors 86 and 88 and 
control voltage V.sub.CTRL 44. Capacitor 86 is coupled to the output of 
inverter 80 and capacitor 88 is similarly coupled to the output of 
inverter 82. The delay through each inverter 80 and 82 increases as its 
associated capacitance increases. The capacitance of capacitors 86 and 88 
is varied by V.sub.CTRL 44; thus, V.sub.CTRL controls the end-to-end delay 
of SDL 40. 
The control voltage V.sub.CTRL controls the delay of SDL 40 by causing the 
delay of inverters 80 and 82 to be long for inverter output voltages that 
are less than or equal to V.sub.CTRL minus V.sub.T, where V.sub.T is the 
threshold voltage of the N-type transistors within the pass devices 
connected to V.sub.CTRL. Alternatively, for output voltages from inverters 
80 and 82 which are greater than V.sub.CTRL minus V.sub.T, capacitors 86 
and 88 are effectively disconnected from the outputs of inverters 80 and 
82. By varying V.sub.CTRL, the fraction of an inverter output transition 
during which the output is fully loaded down by the load capacitors 86 and 
88 is varied. 
The outputs of each inverter 80 and 82 are input to pass network 90, which 
includes two pass devices, or transistors, 100 and 102. Pass network 90 
determines which inverter 80 or 82 output will be output to Tap.sub.n 
depending upon the state of the complementary clock phase signals. Pass 
network 90 receives two phasing signals, which are applied to inputs SA 96 
and SB 98. Depending upon the location of a particular delay element 
either PHI.sub.1 62 and PHI.sub.2 64 or PHIQ.sub.1 66 and PHIQ.sub.2 68 
are applied to SA 96 and SB 98. Preferably, PHI.sub.1 62 and PHI.sub.2 64 
are input to the middle 1/2-3/4 of delay elements 42 of synchronous delay 
line 40, while PHIQ.sub.1 66 and PHIQ.sub.2 68 are input to the remaining 
1/2-1/4 of delay elements 42 at the ends of synchronous delay 40. 
Given delay elements 42, two waves propagate down SDL 40 every clock, each 
triggered by one of the trigger inputs WVA.sub.0 70 and WVB.sub.0 72. 
These waves follow the same path each clock cycle, with only their 
polarity inverted on alternate clocks. 
As compared to prior art SDL 20, in SDL 40 each wave travels through half 
the number of gates. Thus, given the same end-to-end delay, SDL 40 
provides more than double the number of taps and more than twice the 
resolution as prior SDL 20. The number of taps is more than doubled 
because the delay of an inverter is typically less than that of a NAND 
gate. 
Because SDL 40 relies upon two waves propagating in parallel, as opposed to 
a single wave as in the prior SDL 20, it is important that the two waves 
be precisely aligned. Precise alignment for waves WVA.sub.0-(N-1) and 
WVB.sub.0-(N-1) is guaranteed by designing phase generator 41 to eliminate 
any skew between WVA.sub.0 and WVB.sub.0, as previously discussed. 
Sample-and-hold circuit 43 will not be described in detail. In 
substantially the same manner as prior art sample-and-holds, 
sample-and-hold circuit 43 generates a control voltage V.sub.CTRL that 
forces the end-to-end delay T.sub.D of SDL 40 to equal the clock period 
TP. Negative feedback is used by sample-and-hold circuit 43 to generate 
the appropriate value for V.sub.CTRL. 
Thus, a high resolution synchronous delay line has been described. The SDL 
includes voltage controlled delay elements that propagate two parallel 
waves and a phase generator which generates deskewed trigger signals. 
In the foregoing specification, the invention has been described with 
reference to specific exemplary embodiments thereof. It will, however, be 
evident that various modifications and changes may be made thereto without 
departing from the broader spirit and scope of the invention as set forth 
in the appended claims. The specification and drawings are, accordingly, 
to be regarded in an illustrative rather than restrictive sense.