Techniques for generating multiple low noise reference voltages

Techniques to generate two separate temperature independent reference voltages. The reference voltages can be generated using a chain of ΔVBE cells. A cross-quad ΔVBE-cell-based bandgap voltage reference can cancel out noise of associated current sources by forcing them to correlate. Several ΔVBE stages can be cascaded together to generate an appreciable PTAT component that can cancel the CTAT component from VBE. In some example configurations, only BJTs are used—without requiring use of an amplifier—to generate the bandgap voltages; in this way, extremely low noise voltage references can be generated. The PTAT and the CTAT voltages can be combined to generate a bandgap voltage of approximately VG0 or approximately 2VG0.

FIELD OF THE DISCLOSURE

This document pertains generally, but not by way of limitation, to integrated circuits, and more particularly, to voltage reference circuits.

BACKGROUND

Within the field of semiconductor circuits, certain categories of circuitry require a reliable operation over a range of temperatures. One circuit that may be used to provide a constant reference source is a bandgap voltage reference.

Bandgap voltage reference circuits are designed to sum two voltages with opposite temperature slopes. One of the voltages is a Complementary-To-Absolute Temperature (CTAT) voltage typically provided by a base-emitter voltage (VBE) of a forward biased bipolar transistor. The other is a Proportional-To-Absolute Temperature (PTAT) voltage typically derived from the base-emitter voltage differences of two bipolar transistors operating at different collector current densities. When the PTAT voltage and the CTAT voltage are summed together, the summed voltage is at a first order temperature insensitive.

SUMMARY OF THE DISCLOSURE

This disclosure describes techniques that can generate two separate temperature independent reference voltages. The reference voltages can be generated using a chain of ΔVBEcells. A cross-quad ΔVBE-cell-based bandgap voltage reference can cancel out noise of associated current sources by forcing them to correlate. Several ΔVBEstages can be cascaded together to generate an appreciable PTAT component that can cancel the CTAT component from VBE. In some example configurations, only BJTs are used-without requiring use of an amplifier—to generate the bandgap voltages; in this way, extremely low noise voltage references can be generated. The PTAT and the CTAT voltages can be combined to generate a bandgap voltage of approximately VG0or approximately 2VG0.

In some aspects, this disclosure is directed to a voltage reference circuit to generate at least a first reference voltage and a second reference voltage. The circuit comprises a plurality of cascaded ΔVBEstages, each ΔVBEstage including four bipolar junction transistors (BJTs) connected in a cross-quad configuration, each ΔVBEstage arranged to generate a proportional to absolute temperature (PTAT) voltage, the plurality of ΔVBEstages cascaded such that their PTAT voltages are summed; a first reference voltage stage cascaded within the plurality of ΔVBEstages, the first reference voltage arranged to offset a complementary to absolute temperature (CTAT) voltage with a first sum of PTAT voltages to provide the first reference voltage; and a second reference voltage stage cascaded within the plurality of ΔVBEstages, the second reference voltage stage coupled to the summed PTAT voltages, the second reference voltage stage arranged to generate multiple VBEvoltages that are summed with a second sum of PTAT voltages to provide the second reference voltage.

In some aspects, this disclosure is directed to a method of generating at least a first reference voltage and a second reference voltage. The method comprises cascading a plurality of ΔVBEstages, each ΔVBEstage including four bipolar junction transistors (BJTs) connected in a cross-quad configuration; generating, at each ΔVBEstage, a proportional to absolute temperature (PTAT) voltage and summing the PTAT voltages of the plurality of cascaded ΔVBEstages; offsetting, using a first reference voltage stage, a complementary to absolute temperature (CTAT) voltage with a first sum of PTAT voltages to provide the first reference voltage; generating multiple VBEvoltages, using a second reference voltage stage cascaded within the plurality of ΔVBEstages; and summing the multiple VBEvoltages with a second sum of PTAT voltages to provide the second reference voltage.

In some aspects, this disclosure is directed to a voltage reference circuit to generate at least a first reference voltage and a second reference voltage. The circuit comprises a plurality of cascaded ΔVBEstages, each ΔVBEstage including four bipolar junction transistors (BJTs) connected in a cross-quad configuration; at each ΔVBEstage, means for generating a proportional to absolute temperature (PTAT) voltage and means for summing the PTAT voltages of the plurality of cascaded ΔVBEstages; means for offsetting a complementary to absolute temperature (CTAT) voltage with a first sum of PTAT voltages to provide the first reference voltage; means for generating multiple VBEvoltages; and means for summing the multiple VBEvoltages with a second sum of PTAT voltages to provide the second reference voltage.

DETAILED DESCRIPTION

A bandgap voltage reference is a type of voltage reference circuit having a low or zero temperature coefficient (TC). The low TC is achieved by generating a voltage having a positive TC, or Proportional-To-Absolute Temperature (PTAT) voltage, and summing it with a voltage having a negative TC, or Complementary-To-Absolute Temperature (CTAT) voltage, to create a reference voltage with a first-order zero TC.

In an approach to generating a bandgap reference voltage, an amplifier can provide equal currents to two bipolar junction transistors (BJTs) Q1and Q2.

However, the current densities of Q1and Q2are intentionally made different, e.g., by emitter area scaling or current scaling, such that the base-emitter voltages (VBE) for the two transistors are different. This difference, or ΔVBE, is a PTAT voltage that appears across a resistor. It can be gained and summed with the VBEof Q1, which is a CTAT voltage, to generate a reference voltage VREF, which is given by Equation (1):
VREF=VBE,Q1+G*VPTAT=G1*VBE,Q1+G2*k*T/q*ln(N),  Equation (1)
where G1 is the VBEgain, G2 is the PTAT gain, k is Boltzmann's constant, T is the temperature in Kelvin, q is the charge of an electron, and N is the ratio of the current densities. The gain, G, can be arranged such that the total temperature dependence is small. The ratio of current densities of Q1and Q2can be altered by changing the relative emitter areas, scaling the relative collector currents, or both.

A voltage reference circuit capable of providing ultra-low noise performance is described in commonly assigned U.S. Pat. No. 9,285,820 to Kalb et al., titled “Ultra-low Noise Voltage Reference Circuit” and filed on Feb. 1, 2013, the entire contents of which being incorporated herein by reference. In U.S. Pat. No. 9,285,820, the voltage reference circuit included a plurality of ΔVBE cells, each including four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ΔVBE voltage. The plurality of ΔVBE cells are stacked such that their ΔVBE voltages are summed. A last stage is coupled to the summed ΔVBE voltages. The last stage is arranged to generate a VBE voltage which is summed with the ΔVBE voltages to provide a reference voltage. This arrangement serves to cancel out the first-order noise and mismatch associated with the two current sources present in each ΔVBE cell, such that the present voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.

A low noise signal path can benefit from low noise voltage references. A higher reference voltage value can be desirable for higher dynamic range signals whereas a signal path with a lower reference voltage can be desirable for lower dynamic range signals. An integrated circuit die may have both kinds of signal paths present and, as such, it may be desirable to have two different reference voltages. One way to generate two reference voltages can be to generate a higher reference voltage (e.g., ˜2.4V) and then generate a lower reference voltage from it through a resistor ladder. However, such a simple solution may not be desirable because of cross-coupling of noise between the two reference voltage nodes because one reference voltage is generated based on the other.

The present inventors have recognized the desirability of providing a low noise voltage reference circuit that can generate two separate reference voltages. A voltage reference circuit that can generate two separate reference voltages, as described in this disclosure, can help save power and reduce die area, and can exhibit very little cross-coupling between the two references. As such, the voltage reference circuit of this disclosure can help provide a power-efficient and low-noise reference voltage generation and distribution scheme.

The techniques of this disclosure can generate two separate temperature independent reference voltages. The reference voltages can be generated using a chain of ΔVBEcells. A cross-quad ΔVBE-cell-based bandgap voltage reference can cancel out noise of associated current sources by forcing them to correlate. Several ΔVBEstages can be cascaded together to generate an appreciable PTAT component that can cancel the CTAT component from VBE. In some example configurations, only BJTs are used-without requiring use of an amplifier—to generate the bandgap voltages; in this way, extremely low noise voltage references can be generated. The PTAT and the CTAT voltages can be combined to generate a bandgap voltage of approximately VG0or approximately 2VG0.

Additional cross-quad cell stacking can be done in a single ΔVBEstage to leverage a higher power supply voltage, e.g., the 5V supply, such that only two such stages can give sufficient PTAT component so as to cancel the CTAT component due to VBEand generate a bandgap voltage of approximately VG0. Further stages of stacked ΔVBEcells can be cascaded to generate more PTAT component so as to cancel a CTAT component due to 2*VBEand generate approximately 2 VG0, such as explained further below.

FIG. 1is a schematic diagram of an example of a cross-quad ΔVBEcell. The “cross-quad ΔVBEcell” ofFIG. 1can cancel out to a first-order the noise and mismatch of the two current sources that provide currents I1and I2. The cross-quad ΔVBEcell was described in detail in commonly assigned U.S. Pat. No. 9,285,820, incorporated herein by reference including for its description of a cross-quad ΔVBEcell, and for purposes of conciseness, will not be described in detail again.

Without the cross-quad connection, the current sources can be the dominant sources of noise and mismatch in the overall ΔVBEoutput voltage. Here, however, the voltage reference provides ultra-low 1/f noise in the bandgap voltage output, making it suitable for demanding low-noise applications such as medical instrumentation. For example, one possible application is as an ultra-low-noise voltage reference for an electrocardiograph (ECG) medical application-specific standard product (ASSP).

The transistor MN1, e.g., an N-type or other n-channel field-effect transistor (FET), can be employed as an active resistance across which the cell's output voltage (ΔVBE) appears, and transistor MN2, e.g., NMOS FET, can be connected as shown to drive the bases of Q3and Q4. In some example configurations, transistor MN2can alternatively be implemented with an NPN transistor, and that the functions provided by MN1and MN2can alternatively be provided by other means such as can include other transistors or circuitry.

In this configuration, the high-current-density transistor pair Q1and Q4, e.g., Ix-sized devices, and the low-current-density transistor pair Q2and Q3, e.g., Nx-sized devices, each have one NPN with a collector current originating from I1and one NPN with a collector current originating from I2. The noise components introduced by MP2and MP3are forced to be correlated via the cross-quad configuration. Thus, the 1/f and wideband noise, and the mismatch of the PMOS current mirror transistors, are rejected to an amount limited only by the beta of the NPNs used in the cross-quad configuration.

The cross-quad configuration used in the circuit ofFIGS. 2A and 2Bis similar to the configuration shown inFIG. 1.

FIGS. 2A and 2Bare a schematic diagram of an example of a power-efficient and low-noise reference voltage generation and distribution scheme that can generate two reference voltages, in accordance with various techniques of this disclosure. As seen inFIGS. 2A and 2B, the example of a reference voltage circuit10can include multiple cascaded ΔVBEstages, e.g., stage 1 through stage 5. As described in detail below, each ΔVBEstage can be arranged to generate a ΔVBEvoltage and the ΔVBEstages can be cascaded such that their ΔVBEvoltages are summed.

Each ΔVBEstage, e.g., stage 1 through stage 5, can include four bipolar junction transistors (BJTs) connected in a cross-quad configuration. An example of four BJTs connected in a cross-quad configuration is shown generally at12, with the current sources shown explicitly as transistors Q1-Q4. Another example of four BJTs connected in a cross-quad configuration is shown generally at14. In the example configuration shown at12, a parallel RC network16can be included to compensate the feedback loop18.

At least some of the ΔVBEstages can further include additional pairs of cross-coupled BJTs. For example, Stage 1 can include additional pairs of cross-coupled BJTs, as shown generally at20, and Stage 2 can include additional pairs of cross-coupled BJTs, as shown generally at22. In the example shown inFIGS. 2A and 2B, the BJTs forming the additional pairs can have a ratio N of emitter areas that is greater than 1. In some example configurations, the BJTs connected in a cross-quad configuration can include a ratio M of emitter areas that is greater than 1.

It should be noted that, in some examples, all low-current density transistors, e.g., Nx-sized or Mx-sized devices, can have a separate scaling. Further, the low-current density transistors, e.g., Nx-sized or Mx-sized devices, do not need to be in pairs of ratios, e.g., N on one side and N on the other side of the cross-quad configuration. Similarly, all high-current density transistors, e.g., Ix-sized devices, can have a separate scaling.

In some examples, M does not equal N. For example, in a non-limiting illustrative configuration, the emitter ratios can be chosen such that M=14 and N=24 in stages 1 and 2 so that the PTAT component cancels the CTAT component at the end of Stage 2, resulting in a reference voltage Vref_1p2 with approximately a first-order zero temperature coefficient at the end of Stage 2. The actual reference value realized is approximately the band-gap voltage of silicon. As described below, the voltage reference Vref_1p2 can optionally be amplified through a non-inverting buffer stage having a gain greater than 1. In this manner, any reference voltage value greater than the silicon bandgap voltage can be obtained and an accurate absolute trim functionality can be implemented by changing a feedback tap point, for example. It can be desirable in some configurations to select a gain as close to 1 as possible to minimize noise gain.

In some example configurations, the emitter area ratios can be selected to be different for one or more of the stages such that the PTAT and CTAT components cancel at the reference voltage outputs, e.g., first reference voltage Vref_1p2 and second reference voltage Vref_2p4. For example, in a non-limiting configuration, the emitter ratios in stage 3 can be chosen such that K=8 and N=24, while the emitter ratios in stages 1 and 2 can be chosen such that M=14 and N=24. The emitter ratios in Stage 3 can be chosen as 8 and 24 so that at the end of Stage 5, the CTAT component due to two VBEvoltage drops cancels the summed PTAT components of Stages 1-5.

For two transistors having different current densities due to their different emitter areas and operating with the same collector current, the difference in their base emitter voltages represents ΔVBE, which is the PTAT voltage. For the same collector current, the difference in VBEfor a 1× emitter area device and an N times larger (Nx) emitter area device is ΔVBE, which is the PTAT voltage. The VBEsummation will now be explained. Starting from ground at the left of Stage 1, an increase of 1× VBE5is achieved through the base-emitter junction of BJT Q5. Another increase of 1× VBE8is achieved through the base-emitter junction of BJT Q8, and so forth through Q9and Q12until node24is reached.

Now, going downward from node24, a decrease of an M times larger (Mx) emitter area transistor VBE,Q11(a smaller VBEthan VBE,Q12) is achieved through the base-emitter junction of BJT Q11. Another decrease of VBE,Q10is achieved through the Mx base-emitter junction of BJT Q10. A decrease of VBE,Q7is achieved through the Nx base-emitter junction of BJT Q7and another decrease of VBE,Q6is achieved through the Nx base-emitter junction of BJT Q6until node P1is reached. In this manner, a summed ΔVBEvoltage (or PTAT voltage) generated by Stage 1 at node P1is equal to 4*ΔVBE, or VPTAT1. More particularly, the voltage at node P1, VPTAT1=VBE,Q5+VBE,Q8+VBE,Q9+VBE,Q12−VBE,Q11−VBE,Q10−VBE,Q7−VBE,Q6=(VBE,Q5−VBE,Q7)+(VBE,Q8−VBE,Q6)+(VBE,Q9−VBE,Q11)+(VBE,Q12−VBE,Q10)=4*ΔVBE.

In the example configuration shown inFIG. 2A, a transistor Q13, e.g., a FET operating in its triode region, can be part of the feedback loop18. The transistor Q13can be feedback regulated so that the ΔVBEnode voltage at P1, VP1, can be dropped across Q13and its source-coupled resistor while maintaining the current dictated by transistor Q2.

Stage 2 is coupled to Stage 1 in a cascaded arrangement with the output of Stage 1 at node P1being the input to Stage 2, such that the PTAT ΔVBEvoltages of Stages 1 and 2 are summed. Similar to Stage 1, the transistors Q14-Q21in Stage 2 can generate a summed ΔVBEvoltage (or PTAT voltage) equal to 4*ΔVBE, or VPTAT2, between node P1and the emitter of transistor Q15. More particularly, VPTAT2=VBE,Q14+VBE,Q17+VBE,Q18+VBE,Q21−VBE,Q20−VBE,Q19−VBE,Q16−VBE,Q15=(VBE,Q14−VBE,Q16)+(VBE,Q17−VBE,Q15)+(VBE,Q21−VBE,Q19)+(VBE,Q18−VBE,Q20)=4*ΔVBE. Thus, with Stages 1 and 2 cascaded, a summed ΔVBEvoltage (or PTAT voltage) of VPTAT1+VPTAT2=8*ΔVBEcan be generated at the emitter of the Nx BJT Q15(node labeled as P2), and a CTAT voltage is generated across the adjustable resistor R1using the VBE,Q15of the Nx BJT Q15. Summed ΔVBEvoltages (or PTAT voltages) can be similarly generated for Stage 3 (VPTAT3), Stage 4 (VPTAT4), and Stage 5 (VPTAT5).

In some examples, a resistive element R1can be coupled in series with the summed ΔVBEvoltage (or PTAT voltage) of cascaded ΔVBEstages, e.g., of stages 1 and 2. The resistive element R1can have a resistance across which a CTAT voltage can be generated and placed in series with a summed ΔVBEvoltage (or PTAT voltage) of 8*ΔVBEto provide a first reference voltage Vref_1p2. By summing the PTAT and CTAT voltages and by adjusting the resistive element R1, the PTAT and CTAT voltages can cancel each other and a temperature independent first reference voltage can be generated at output node26, e.g., at the bandgap voltage of silicon. The resistance of resistive element R1can be adjusted, such as by using laser trimming, on-chip digital selection, tap selection, or using one or more other adjustment techniques.

In the example configuration shown inFIGS. 2A and 2B, the actual reference value realized, or output at node26, is slightly less than the bandgap voltage value. This can be done so that the unbuffered reference voltage can be amplified through a non-inverting buffer stage, e.g., buffer circuit46inFIG. 3having a gain greater than 1. In this manner, any reference voltage value near the bandgap voltage value can be obtained and an accurate absolute trim functionality can be implemented by changing the feedback tap point at the output of the buffer circuit46.

The resistive element R1coupled across the base emitter junction of the BJT Q15with an emitter area of N allows only an adjustable fraction of the CTAT VBEvoltage to be summed with the summed PTAT component developed at node P2using the cascaded Stages 1 and 2 to cancel temperature dependence to a first order, resulting in a first-order zero temperature coefficient bandgap reference voltage at node Vref_1p2. The resistive element R1can be a potentiometer having various tap points. The reference voltage Vref_1p2 is given by Equation (2):
Vref_1p2=G1*(VPTAT1+VPTAT2)+G2*VBE,  Equation (2)
where G1 is the VBEgain, G2 is the PTAT gain. In Equation (2), the reference voltage Vref_1p2 is a reference voltage with a first-order zero temperature coefficient. In some examples, the actual reference value realized is 1.105 and is smaller than the bandgap value VG0of 1.2V. The voltage VBEis the base emitter voltage VBE,Q15of the BJT Q15with an emitter area of N and is a CTAT voltage such that it has negative temperature coefficient. The voltage VPTAT1is equal to 4*ΔVBE(from Stage 1) and VPTAT2is equal to 4*ΔVBE(from Stage 2) for a summed PTAT voltage of 8*ΔVBE. The voltage (VPTAT1+VPTAT2) has positive temperature coefficient. A PTAT voltage is kT/q*ln(N1*N2*N3), where N1-N3 represent the current density ratios. For emitter ratios of M and N in a stage, VPTAT=kT/q*(2*ln (M)+2*ln(N)).

The resistance of the adjustable resistive element R1is the total resistance across VBE, and R1=R1A+R1B is fixed (R1A and R1B not depicted). In some examples, the resistive element R1A is approximately equal to 1 Megaohm and resistive element RIB is approximately 200-300 kiloohm (R1A and R1B are not depicted). The variable G2 is programmable, such as by changing a tapping point on R1. In Equation (2), the term G2*VBEis approximately equal to 0.5V such that the negative slope with respect to absolute temperature (CTAT) of VBEcancels with the positive slope of (VPTAT1+VPTAT2).

The resistance of resistive element R1can be large, e.g., about 1 Megaohm, so that it does not significantly alter the current into the collector of the BJT Q14with the smaller emitter area. In Stage 2, the collector currents for the bottom-most BJT pair can differ by about 10% as some of the current meant for the collector of the BJT with the smaller emitter area is diverted to R1. The diverted current can be about 0.4 microamps at room temperature, in an illustrative example. This difference in the collector current can cause a slight dependence of Vptat2 on the finite base-collector current gain (beta) of the BJTs.

Stage 3 can be coupled to Stage 2 in a cascaded arrangement such that the ΔVBEvoltages of Stages 1-3 are summed. Similar to Stage 1, the circuitry in Stage 3 can generate a summed ΔVBEvoltage (or PTAT voltage) equal to 4*ΔVBE. A summed ΔVBEvoltage (or PTAT voltage) of 12*ΔVBE(VPTAT1+VPTAT2+VPTAT3) is generated at the emitter of the BJT Q23(labeled as P3).

Stage 4 can be coupled to Stage 3 in a cascaded arrangement such that the ΔVBEvoltages of Stages 1-3 are summed. Stages 1-3 include a stack of 4 pairs of transistors. For headroom reasons, however, Stages 4 and 5 include a stack of two pairs of transistors. As a result, the circuitry in Stage 4 can generate a summed ΔVBEvoltage (or PTAT voltage) equal to 2*ΔVBE. A summed ΔVBEvoltage (or PTAT voltage) of 14*ΔVBE(VPTAT1+VPTAT2+VPTAT3+VPTAT4) is generated at the emitter of the Nx BJT Q25(labeled as P4).

Stage 5 can be coupled to Stage 4 in a cascaded arrangement such that the ΔVBEvoltages of Stages 1-4 are summed. The circuitry in Stage 5 can generate a summed ΔVBEvoltage (or PTAT voltage) equal to 2*ΔVBE. A summed ΔVBEvoltage (or PTAT voltage) of 16*ΔVBE(VPTAT1+VPTAT2+VPTAT3+VPTAT4+VPTAT5) is generated at the emitter of the Nx BJT Q27(labeled as P5).

Another reference voltage stage 28 can be cascaded within the plurality of ΔVBEStages 1-5 and, in particular, coupled to the summed ΔVBEvoltages at node P5. The reference voltage stage 28 is arranged to generate multiple VBEvoltages that are summed with a sum of ΔVBEvoltages to provide a second reference voltage at output node30. The output is taken from the base of transistors Q30, Q31such that the summed ΔVBEvoltages of Stages 1-5 of 16*ΔVBE(or PTAT voltages) is summed with the two VBEvoltages (or CTAT voltages) of the two Nx BJTs Q28, Q31to generate the second reference voltage Vref_2p4 having a first-order zero temperature coefficient.

The second reference voltage Vref_2p4 is given by Equation (3):
Vref_2p4=VBE1+VBE2+VPTAT_BIAS+VPTAT5+VPTAT4+VPTAT3+VPTAT2+VPTAT1,  Equation (3)
where VBE1is the base emitter voltage across BJT Q31; VBE2is the base emitter voltage across BJT Q28, VPTAT_BIASis the PTAT voltage across the resistive element R2in the final stage 28 that generates the PTAT bias; VPTAT5is the PTAT voltage generated in Stage 5; VPTAT4is the PTAT voltage generated in Stage 4; VPTAT3is the PTAT voltage generated in Stage 3; VPTAT2is the PTAT voltage generated in Stage 2; and VPTAT1is the PTAT voltage generated in Stage 1. For emitter ratios of M and N in a stage, VPTAT=kT/q*(2*ln(M)+2*ln(N)).

FIG. 3is a schematic diagram of an example of a multi-channel circuit40that can implement various techniques of this disclosure. In some example implementations, the multi-channel circuit40ofFIG. 3can form a portion of an electrocardiogram (ECG) measurement circuit in combination with the voltage reference circuit10ofFIGS. 2A and 2B. As described above, the techniques ofFIGS. 2A and 2Bcan generate two separate temperature independent reference voltages. InFIG. 3, the multi-channel circuit40can include two separate reference buffers for the two separate temperature independent reference voltages.

InFIG. 3, the block42represents the circuitry ofFIGS. 2A and 2B. The block42outputs two temperature independent reference voltages, namely first reference voltage Vref_1p2 and second reference voltage Vref_2p4. The circuit40ofFIG. 3includes two buffer circuits44,46. By utilizing the circuit ofFIGS. 2A and 2Bin block42in which two separate reference voltages are generated, very little cross-coupling occurs between the two buffer circuits44,46.

The first buffer circuit44receives the reference voltage Vref_2p4 and, using the feedback resistor divider network48, can amplify the reference voltage Vref_2p4 to generate a first channel reference voltage of about 2.56V, such as for use with an ECG channel. In some example configurations, the buffer circuit44can be a BJT-based circuit, which can have better noise performance characteristic when compared with CMOS-based circuits.

The second buffer circuit46receives the reference voltage Vref_1p2 and, using the feedback resistor divider network50, can amplify the reference voltage Vref_1p2 to generate a second channel reference voltage of about 1.28V, such as for use with a pace channel. In some example configurations, the buffer circuit46can be a FET-based circuit, e.g., CMOS-based. Being CMOS-based, the buffer circuit46will not load the second stage or disturb the current in the second stage. This can provide good crosstalk performance as the high performance 2.4V reference is not affected even if the buffer circuit46drives a switched capacitor or other noisy load.

Using the various techniques described above, a low noise voltage reference circuit can be provided that can generate two separate reference voltages, exhibiting very little cross-coupling between them the references. A voltage reference circuit that can generate two separate reference voltages, as described above, can save power and reduce die area, thereby providing a power-efficient and low-noise reference voltage generation and distribution scheme.

Various Notes

Each of the non-limiting aspects or examples described herein may stand on its own, or may be combined in various permutations or combinations with one or more of the other examples.