Space vector modulation for multilevel inverters

Inverter is modulated based on first, second, and third switching states determined according to a reference vector represented as a sum of a remainder vector connecting the reference vector with a first vertex of a modulation triangle and a set of vertex vectors connecting a center vertex of space vector diagram with the first vertex. A first switching state of the inverter at the first vertex is determined based on angles of vertex vectors in the set. A second switching state of the inverter at a second vertex of the modulation triangle and a third switching state of the inverter at a third vertex of the modulation triangle are determined based on the first switching state and the remainder vector.

FIELD OF THE INVENTION

This invention relates generally to electrical power conversion systems, and more space vector modulation for a multilevel inverter based on a space vector diagram of switching states of the inverter.

BACKGROUND OF THE INVENTION

Multilevel inverters are widely used in high-power high-voltage applications due to advantageous performance over two-level inverters, including reduced voltage pressure or tension on the power devices, lower harmonics, lower instantaneous rate of voltage change (dv/dt), and lower common-mode voltage.

Among various modulation strategies for multilevel inverters, space vector pulse width modulation (SVPWM), provides significant flexibility to optimize switching waveforms, and is suitable for implementation in digital signal processors. For an n-level inverter, there are n3switching states and 6(n−1)2modulation triangles in the space vector diagram. A reference vector defining desired switching state of the inverter can be placed at any modulation triangle of the space vector diagram. To reduce the harmonics and voltage surges during the switching transients, the Nearest Three Vectors (NTV) is commonly adopted. According to the NTV approach, the reference vector of the voltage is equivalent to the nearest three vectors in terms of the average voltage during a switching cycle. However as the level of the inverter increases the increased number of triangles, switching states, and calculation of duty cycles enlarges the complexity of SVPWM for multilevel inverters.

There are two common methods of SVPWM for multilevel inverters. The first method determines the modulation triangle, and then solve three simultaneous equations for that triangle to obtain the duty cycles, see T. Ishida, et al., “A control strategy for a five-level double converter with adjustable dc link voltage,” Proc. Ind. Appl. Conf., October 2002, vol. 1, pp. 530-536. The second method determines the modulation triangle, and then uses the particular duty cycle equations pre-stored in the lookup table for this triangle, see S. Mondal, et al., “A neural-network based space-vector PWM controller for a three-level voltage-fed inverter induction motor drive,” IEEE Trans. Power Electron., vol. 38, no. 3, pp. 660-669, May/June 2002. However, with the increasing number of levels of the inverter, both of those two methods become intensive in computation.

Several SVPWM based methods are known for three-level inverters. However, those methods are not readily extended to four or higher level inverters. For example, one method partitions the three-level space vector diagram into six two-level space vector diagrams, see H. Zhang, et al., “Multilevel inverter modulation schemes to eliminate common-mode voltages,” IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 1645-1653, November/December 2000. In H. Zhang's method, the axes of the d-q plane are rotated by a certain angle in each calculation of the reference vector location, and no general method for switching sequence selection or application for four or higher level inverter is introduced.

A similar method for three-level inverter is described by J. Seo, et al., “A new simplified space-vector PWM method for three-level inverters,” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 545-550, July 2001. In J. Seo's method, a two-phase to three-phase conversion is performed to calculate the shift of origin of a virtual two-level inverter. After the shift of origin and 60° coordinate transformation, duty cycles are calculated using two-level equations. Because of the two-phase to three-phase conversion for each partition of the space vector diagram, the complexity and computation of the method are increased when applied to a four or higher level inverter. Moreover, no general switching sequence selection is used by the method.

A Euclidean vector system based SVPWM is describe by N. Celanovic, et al., “A fast space vector modulation algorithm for multilevel three phase converters,” WEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637-641, March/April 2001. However, several matrix transformations are needed, and no systematic approach for determining the switching states or real-time implementation is provided in N. Celanovic's method. A coordinate transformation and switching sequence mapping based SVPWM scheme is described by A. Gupta, et al., “A space vector PWM scheme for multilevel inverters based on two-level space vector PWM,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1631-1639, October 2006. In A. Gupta's method, a coordinate transformation is needed to determine the location of the reference vector and to calculate the duty cycles, and a pre-stored switching sequence mapping table is needed to determine the switching sequence. However, because the number of possible switching sequences increases with the increasing level of the inverter, more memory is needed and slower mapping speed is achieved when A. Gupta's method is applied to higher level inverters.

Accordingly, there is a need for general SVPWM based method for multilevel inverters.

SUMMARY OF THE INVENTION

It is an object of some embodiments to an invention to provide a method for a space vector pulse width modulation (SVPWM) for a multilevel inverter based on a space vector diagram of switching states of the inverter. It is a further objective of some embodiments, to provide a method that avoids a lookup table to increase the flexibility of the SVPWM method for multilevel inverters. It is further objective of some embodiments, to provide a method that can be implemented for inverters of any level.

Some embodiments are based on a realization that a reference vector can be represented as a sum of a remainder vector connecting the reference vector with a first vertex of a modulation triangle enclosing the reference vector, and a set of vertex vectors connecting a center vertex of the space vector diagram with the first vertex.

A “vertex vector” is a vector connecting two adjacent vertices, and a length of the vertex vector can be multiple of Vdc, which is the voltage of a DC source for the inverter. A sequence of vertex vectors connects the center vertex of the space vector diagram of the multilevel inverter with the first vertex of the modulation triangle enclosing the reference vector. The “remainder vector” is the vector enclosed by the modulation triangle and connecting the first vertex of the modulation triangle with the reference vector.

Some embodiments are based on a further realization that due to construction of the vertex vectors in the space vector diagram, the switching states at the vertices for each vertex vector in the set can be iteratively determined, starting from a current switching state of the inverter at the center vertex, by modifying a corresponding phase of the current switching state. For each iteration, a type of a modification and the corresponding phase can be determined based on a function s of the angle φ of the corresponding vertex vector related to, e.g., axis A of the space vector diagram of the multilevel inverter, and the corresponding phase is increased or decreased by a unit value based on the type of the modification. The unit value can be equal to the multiple of Vdcused to construct the space vector diagram. Typically, the unit value and the multiple of Vdcis one.

Such realizations allow determining the switching state at the first vertex without using the lookup table, which adds flexibility in designing the inverter of arbitrarily level. Also, knowing the switching state of the first vertex, the switching states of the second and the third vertexes of the modulation triangle enclosing the reference vector can also be determined without the lookup table.

Furthermore, because the remainder vector is inside a hexagon which is a space vector diagram of a two-level inverter, various methods can be reused to determine the duty cycles of the inverter. Moreover, the switching sequence can be determined by calculating the appropriate switching states of the inverter at a second vertex and at a third vertex of the modulation triangle and by selecting the appropriate sequence of the switching states at the three vertices of the modulation triangle. The switching sequence modes can include first mode mode=1 when the switching sequence is counterclockwise selected, and second mode mode=2 when the switching sequence is clockwise selected.

Some embodiments are based on another realization that the relationship between functions of the angles of the vertex and remainder vectors and the type of modification of the corresponding phase can be determining, stored in a memory as predetermined mappings, and reused during the modulation. For example, the function of the angle of the vertex vector can include a ratio of the angle of vertex vector with a minimum angle between two adjacent vertex vectors, e.g., π/3. The ratio can be mapped to a type of modification of a switching state to produce the first mapping. The type of modification can include increase or decrease of a value of a phase of the switching state by a unit value, e.g., by one.

Similarly, the function of the angle of the remainder vector can determine a region number of the modulation triangle nested in a second-level diagram based on the angle of the remainder vector. The region number can be mapped to the type of modification of the switching state according to a switching sequence mode to produce a second mapping. The first and the second mappings reduces the processing time to switch states, with minimum increase of the memory, while preserving the adaptability to arbitrarily levels of the inverter.

In some embodiments of the invention, the SVPWM controller includes a combination of at least one or multiple modules including a modulation region classifier, a reference vector location generator, a duty cycles generator, and a switching sequence generator. The command reference voltage is at first classified and modified by the modulation region classifier according to the magnitude of the reference voltage. The classified and modified reference voltage is then used by the reference vector location generator to determine the remainder vector V′ref, and to determine the switching states at the origin of V′ref. Based on V′refand the command switching frequency, the duty cycles generator determines the value of a region number reg and the duty cycles. The switching sequence generator then produces the switching sequence according to the switching states at the origin of V′ref, the region number reg, and the selected switching sequence mode. Finally, the generated switching sequence and the duty cycles are decoded and sent to the inverter as gate driving signals.

In one embodiment, a value of the reference voltage in over-modulation region is modified to achieve the feasibility of the modulation, i.e., a sum of the duty cycles of the switches is smaller than the switching cycle. In another embodiment, the space vector diagram for the reference voltage at a low-modulation range is modified to reduce the number of vertex vectors for locating the reference voltage, which decreases the complexity for determining the switching states.

One embodiment of the invention is extended to produce the switching sequence for other specific requirements. For example, symmetric switching sequence can be generated conveniently. The voltage balance of the DC link capacitors can be controlled by tuning the duty cycles of the zero vectors, or by selecting different redundant switching states and changing the switching sequence in the present invention.

Accordingly, one embodiment of the invention discloses a method for space vector modulation of a multilevel inverter based on a space vector diagram of switching states of the inverter, wherein each switching state defines a combination of phases, wherein the space vector diagram includes a hexagon having a size proportional to a level of the inverter, the hexagon includes a set of vertices uniformly spaced to partition the hexagon into a set of modulation triangles, wherein sides of each modulation triangle are formed by vertex vectors connecting corresponding vertices, wherein the switching states of adjacent vertices are different by a unit value of the phase determined by an angle of the vertex vector connecting the adjacent vertices.

The method includes representing a reference vector as a sum of a remainder vector and a set of vertex vectors connecting a center vertex of the hexagon with a first vertex of the modulation triangle enclosing the reference vector, wherein the remainder vector connects the first vertex with the reference vector; modifying iteratively, for each vertex vector in the set, starting from a current switching state of the inverter at the center vertex, a corresponding phase of the current switching state to produce a first switching state of the inverter at the first vertex, wherein, for each iteration, a type of the modification and the corresponding phase is determined based on a function of the angle of the corresponding vertex vector, and the corresponding phase is increased or decreased by the unit value based on the type of the modification; determining a second switching state of the inverter at a second vertex of the modulation triangle and a third switching state of the inverter at a third vertex of the modulation triangle based on an angle of the remainder vector; and modulating the inverter based on the first, the second, and the third switching states.

Another embodiment discloses a method for a space vector modulation of a multi-level inverter based on a space vector diagram of switching states of the inverter, including representing a reference vector as a sum of a remainder vector connecting the reference vector with a first vertex of a modulation triangle enclosing the reference vector and a set of vertex vectors connecting a center vertex of the space vector diagram with the first vertex; determining a first switching state of the inverter at the first vertex based on angles of vertex vectors in the set and a first mapping between functions of the angles of vertex vectors and types of modification of the switching states; determining a second switching state of the inverter at a second vertex of the modulation triangle and a third switching state of the inverter at a third vertex of the modulation triangle based on the first switching state, the remainder vector and a second mapping of a function of an angle of the remainder vector, switching sequence modes, and the types of modification of the switching states; and modulating the inverter based on the first, the second, and the third switching states.

Yet another embodiment discloses a controller for a space vector modulation of a multi-level inverter based on a space vector diagram of switching states of the inverter. The controller includes a reference vector location generator for determining a first switching state of the inverter at a first vertex based on a set of vertex vectors connecting a center vertex of the space vector diagram with the first vertex of a modulation triangle enclosing the reference vector; a duty cycles generator for determining, based on a remainder vector, a duty cycle and a region number of the modulation triangle nested in a second-level diagram; and a switching sequence generator for determining switching sequence according to the first switching state, the region number, and a switching sequence mode.

DETAILED DESCRIPTION OF THE INVENTION

Multilevel inverters are used in high-power medium-voltage applications due to their superior performance compared to two-level inverters. Space vector pulse width modulation (SVPWM) is preferred for various modulation strategies for multilevel inverters because SVPWM offers significant flexibility to optimize switching waveforms, and because SVPWM is well suitable for digital signal processor implementation. In order to reduce the harmonics and voltage surges during the switching transients, the “Nearest Three Vectors” (NTV), is commonly adopted for SVPWM.

For an n-level inverter, however, there are n3switching states and 6(n−1)2triangles in the space vector diagram. The complexity of conventional SVPWM for multilevel inverters is due to the difficulty in determining the location of the reference vector, the calculation of duty cycles, and the determination and selection of switching states. As the level of the inverter increases, the increased number of switching states, triangles, and calculation of duty cycles adds to the complexity of convention SVPWM for multilevel inverters.

FIG. 1shows an example of a multilevel inverter according to some embodiments of the invention. Voltage of the DC source110is supplied on input lines111to the capacitors. For an n-level inverter, usually there are (n−1) capacitors preferably, but not necessary, having the same nominal capacitance value. In this example, the capacitors are connected in parallel with the DC source110. Those capacitors are preferably charged with the same voltage. Only four capacitors112,114,116, and118are shown inFIG. 1, and the symbol119means all the other capacitors are omitted. The voltages of the capacitors are supplied on input lines113to the inverter120. The inverter120provides AC voltage through output lines123to the load130. The gate driving signals146of the inverter120are produced by the SVPWM controller140according to the command reference voltage142and the command switching frequency144.

For an n-level inverter, the output voltage vector is

Vout=Vd⁢⁢c·(Sa+Sb·ⅇj⁢23⁢π+Sc·ⅇj⁢43⁢π),(1)
where Vdcis voltage of the DC source110, and Sa, Sb, and Scare the switching states of phase A, B, and C, respectively. For an n-level inverter, there are n switching states of each phase, which represent n different voltage levels of the phase and the different voltage levels are 0, Vdc/(n−1), 2·Vdc/(n−1), . . . Vdcwhen the voltage of the DC source negative pole115is considered as a base. If the value of Sa, Sband Scare Sa, Sb, Sc=0, 1, . . . n−1, then the output voltage of phase A, B, and C are

FIGS. 2A-Cshow an example of a basic circuit structure of one phase of a five-level inverter, and corresponding space vector diagram of switching states, and ON-OFF statuses of the switches. InFIG. 2A, elements212,214,216, and218are capacitors and219are clamped diodes. The switching state of a phase225and the corresponding ON-OFF statuses of the switches220are shown inFIG. 2C, where the status 1 means the switch is turned-ON and the status 0 means the switch is turned-OFF.

FIG. 2Bshows a space vector diagram of the five-level inverter ofFIG. 2A. The space vector diagram includes all possible output voltage vectors and the corresponding switching states of the three phases determined according to Equation (1). The axes A231, B233, and C235correspond to the three AC output phases. The space vector diagram includes a hexagon260having a size proportional to the level of the inverter, and each vertex on and inside the hexagon260represents an output voltage vector. The numbers at the vertices on and inside the hexagon260denote the switching states combining the three phases. For example, the number at vertex250is403, which means the switching states for phase A, B, and C are 4, 0, and 3, respectively. As can be seen fromFIG. 2B, some different switching states, e.g.411and300at vertex255, can produce the same three-phase output voltage vector, thus those switching states are redundant switching states. The redundant switching states increase the complexity of conventional SVPWM for multilevel inverters. In the space vector diagram ofFIG. 2B, the redundant switching states at each vertex are listed decreasingly from top to bottom according to the switching states of phase A.

The objectives of SVPWM can include finding the nearest three vectors of the reference vector, determining the duty cycles of the nearest three vectors, and selecting the appropriate switching states and switching sequence. For example, some embodiments determine the nearest three vectors V01242, V02244, and V03246of the reference vector Vref240of the vertices242,244, and246. The duty cycles d1, d2, and d3of the nearest three vectors242,244, and246can be determined according to
Vref/fs=d1·V01+d2·V02+d3·V03,  (2)
where fsis the command switching frequency144. The vertices242,244, and246form a triangle, which encloses the reference vector240and is called the “modulation triangle” in the present invention. The length of each side of each modulation triangle in the present invention is Vdc, where Vdcis the voltage of the DC source110.

Some embodiments of the invention enable a space vector modulation of a multilevel inverter based on a space vector diagram of switching states of the inverter, such that the modulation does not require lookup tables and is adaptable to any type and level of the inverters. Specifically, the embodiments take advantage of a realization that a reference vector can be represented as a sum of a remainder vector connecting the reference vector with a first vertex of a modulation triangle enclosing the reference vector and a set of vertex vectors connecting a center vertex of the space vector diagram with the first vertex. This realization allows locating a modulation triangle enclosing the reference vector in the space vector diagram, and determining the switching states of the vertexes of that modulation triangle.

FIGS. 3A-Cschematically show realization and a diagram of a modulation method employed by some embodiments. For purposes of exemplifying the realization, the space vector diagram of a five-level inverter, as shown inFIG. 2B, is used to illustrate the SVPWM method of the embodiments. It is understood that the SVPWM method can be implemented in any level inverters.

The reference vector240is represented380as a sum of a set391of “vertex vectors”310,320, and330and a “remainder vector”340. A “vertex vector”310,320, or330is a vector connecting two adjacent vertices, e.g. the vertex vector310connects adjacent vertices300and302, and the length of the vertex vector is multiple of Vdc, where Vdcis the voltage of the DC source110. The multiple of Vdcalso defines a unit value of a difference between phases of the switching states of adjacent vertices. Typically, the multiple, and the unit value equal one.

The vertex vectors310,320, and330connect the center vertex300of the hexagon260with the first vertex244of the modulation triangle enclosing the reference vector240. The “remainder vector”340is the vector enclosed by the modulation triangle and connecting the first vertex244with the reference vector240.

In one embodiment, the set of vertex vectors310,320, and330are determined based on a set of nested hexagons370,360, and350enclosing the reference vector240. Each nested hexagon370,360, or350corresponds to a specific level ranging from (n−1) to a second level, and centers at the vertex302,304, or244of the vertex vector310,320, or330. More detailed description of this embodiment for determining the set of vertex vector is provided below.

In another embodiment, the set of vertex vectors are determined based on increase or decrease the difference between the reference and the vertex vector. For example, for each interaction, a set of possible vertex vectors is tested, and the vertex vector subtracted from the reference vector and resulting in a minimum subtracted vector is selected. In alternative embodiment, the selection of the set of vertex vector is arbitrarily until a magnitude of the subtracted vector is less than a magnitude of the vertex vector, i.e., the subtracted vector is the remainder vector.

The switching states at the vertices302,304, and244are determined382iteratively for each vertex vector310,320, and330in the set391, starting from a current switching state of the inverter at the origin vertex300. For each iteration, a corresponding phase of the current switching state is modified to produce a first switching state392of the inverter at the first vertex244. For each iteration, a type of a modification and the corresponding phase is determined based on a function s of the angle φ of the corresponding vertex vector related to axis A231, and the corresponding phase is increased or decreased by the unit value based on the type of the modification. In one embodiment, in accordance with the definition of the switching states in Equation (1), the unit value is selected as one. It is understood that the unit value can be selected as other values if the switching states are defined differently.

In some embodiments, the first switching state of the inverter at the first vertex is determined based on angles of vertex vectors in the set and a first mapping395between functions of the angles of vertex vectors and types of modification of the switching states. For example, in one embodiment, the function s of the angle φ of the corresponding vertex vector can be simply described as
s=3φ/π,  (3)
where 0≦φ<2π.

Typically, the modulation triangles are equilateral, and thus, the angle φ of the vertex vector is multiple of a minimum angle between two adjacent vertex vectors, such as of π/3. Accordingly, in some embodiments, the function of the angle of the vertex vector includes a ratio of the angle of vertex vector with the minimum angle between two adjacent vertex vectors. That ratio can be mapped to a type of modification of a switching state to produce the first mapping.

FIG. 4Ashows an example of the first mapping of the ratio determined by the function s to the type of modification that includes increase or decrease of a value of a phase of the switching state by a unit value. InFIG. 4A, the letters A, B, or C means the switching state of phase A, B, or C needs to be modified, respectively. The up-arrow “↑” means the switching state needs to increase by the unit value, e.g., by one, and the down-arrow “↓” means the switching state needs to decrease by one.

For example, if s=3, then the modification for the switching states is “B↑”, which means the switching states at the current vertex need to increase by one for the switching state of phase B. Since the switching states for each phase of an n-level inverter can only value from 0 to (n−1) in the present invention, a modified switching state needs to be excluded when the corresponding switching state of phase A, B, or C is larger than (n−1) or less than zero.

Based on the first mapping ofFIG. 4A, the switching states480at the first vertex244of the modulation triangle and the vertices302and304are shown inFIG. 3AandFIG. 4B, which can be verified by being compared with the space vector diagram shown inFIG. 2B. The invalid switching states490, i.e., 454, 353, and −120 are excluded sequentially, as shown inFIG. 4B.

After the first switching state is determined, some embodiments determine a second switching state393of the inverter at a second vertex of the modulation triangle and a third switching state394of the inverter at a third vertex of the modulation triangle based on an angle of the remainder vector340. Next, the inverter is modulated386based on the first, the second, and the third switching states. Some embodiments also determine duty cycles and the switching sequence of the inverter.

FIG. 3Bshows a determination of the duty cycles and the switching sequence. The duty cycles can be determined using principles of a two-level inverter, because the remainder vector340is inside a hexagon350which is a space vector diagram of a two-level inverter. Determining the switching sequence means to determine the appropriate switching states of the inverter at a second vertex242and at a third vertex246of the modulation triangle and to select the appropriate sequence of the switching states at the vertices242,244, and246.

There are two switching sequence modes used by embodiments, i.e., the switching sequence mode is mode=1 when the switching sequence is counterclockwise selected, and the switching sequence mode is mode=2 when the switching sequence is clockwise selected. In one embodiment, the switching sequence is determined based on the switching sequence mode and a function reg of the angle δ of the remainder vector340related to axis A231, and the function reg of the angle δ can be described as
3δ/π<reg≦3δ/π+1  (4)
where 0≦δ<2π and reg=1, 2, . . . 6. In some embodiments, the function reg is basically a region number of the modulation triangle nested in a second-level diagram based on the angle of the remainder vector.

For example, in one embodiment, a second switching state393of the inverter at a second vertex of the modulation triangle and a third switching state394of the inverter at a third vertex of the modulation triangle are determined based on the first switching state392, the remainder vector340and a second mapping396of a function of an angle of the remainder vector, switching sequence modes, and the types of modification of the switching states.

FIG. 5Ashows an example of the second mapping396in a tabular form. In this example of the second mapping, each element of the mapping includes five sub-elements. For example, “ABC↑(L)” when the function reg=1 and mode=1, and “ACB↓(U)” when reg=3 and mode=2. The letter A, B, or C means the switching state of phase A, B, or C to be modified sequentially. The symbol “↑” or “↓” means the state of the corresponding phase is modified by the unit value, e.g., increased by one or decreased by one, respectively.

In the space vector diagram, the redundant switching states at each vertex are listed decreasingly from top to bottom corresponding to the switching states of phase A, as shown inFIG. 2B. The letter “L” in the parentheses represents the word “lower” and means the first switching state at the first vertex244of the modulation triangle is not the top one, and the letter “U” in the parentheses represents the word “upper” and means the first switching state at the first vertex244of the modulation triangle is not the bottom one. As an example, for the remainder vector340shown inFIG. 3B, the value of reg is reg=2.

FIG. 5Bshows the switching sequences according to different switching sequence modes determined based on the second mapping ofFIG. 5A. The accuracy of the switching sequences can be verified based on space vector diagram ofFIG. 2B. In some embodiments, the function reg of the remainder vector340is determined using digital signal processor implementation, as described below.

FIG. 6shows a block diagram of the SVPWM controller140according to one embodiment of the invention. The SVPWM controller140of this embodiment can be implemented using a processor600and can include a modulation region classifier610, a reference vector location generator620, a duty cycles generator630, and a switching sequence generator640. Other embodiments of the invention can include more or less modules than embodiments ofFIG. 6. For example, one embodiment does not include the modulation region classifier610.

A command reference voltage142is at first classified and modified by the modulation region classifier610according to the magnitude of the command reference vector142. The modulation region classifier610is enclosed by dashed line because the modulation region classifier610is a recommended option, and the modulation region classifier610is not necessary when the command reference voltage142is not in over-modulation region or in low-modulation region. The classified and modified reference vector612is then used by the reference vector location generator620to determine the remainder vector V′ref340and to determine the switching states392at the first vertex244of the modulation triangle.

Based on V′refand the switching frequency144, the duty cycles generator630determines the value636of function reg and the duty cycles632. The switching sequence generator640then produces the switching sequence645according to the switching states at the first vertex244of the modulation triangle, the value of reg, and the selected switching sequence mode660. Finally, the generated switching sequence and the obtained duty cycles are decoded by a decoder650according to, e.g., a method ofFIG. 2Cand sent to the inverter120as gate driving signals146.

Classification of the Modulation Region

The command reference vector142for an n-level inverter is

Vref=(n-1)·(Va*+Vb*·ⅇj⁢23⁢π+Vc*·ⅇj⁢43⁢π)=Vm·ⅇj⁢⁢θ=Vx+j·Vy,(5)
where V*a, V*b, and V*care the command reference voltage of phase A, B, and C, respectively. Vmis the magnitude of the command reference vector142, and θ is the phase angle of the command reference vector142. Vxand Vyare real numbers and represent the real part and imaginary part of Vref142, respectively.

In one embodiment, the command reference vector is at first classified into different modulation regions according to the magnitude of the reference vector by the modulation region classifier610. For purposes of exemplifying the embodiment, the space vector diagram of the five-level inverter as shown inFIG. 2Bis used as an example to illustrate the classification method.

FIG. 7Ashows an example of the classification method in the invention of one embodiment, in which the space vector diagram is partitioned into different regions by circles720,730,740, and750, whose centers all are the origin of the n-level space vector diagram. Each circle720,730,740, or750is an inscribed circle of a hexagon, and the hexagon represents the space vector diagram of a certain level inverter. For example, the circle740is an inscribed circle of a hexagon710, which is a space vector diagram of a three-level inverter.

For an n-level inverter, there are n regions as

In some embodiments, the region is called “over-modulation region” when r=n; when r=n−1, the region is called “regular region;” when 0<r<n−1, the region is called “low-modulation region.”

The modulation region classifier610can modify the reference vector Vref142according to the region that the reference vector Vref142lies in. Define the reference vector modified by the modulation region classifier as
Vref0=Vm0·ejθ0=Vrx0+j·Vry0,  (7)
where Vm0is the magnitude of the modified reference vector Vref0, and θ0is the phase angle of the modified reference vector Vref0. Vrx0and Vry0are real numbers and represent the real part and imaginary part of Vref0, respectively.

When the command reference vector Vref142is located in the “regular region,” i.e., r=n−1, or the “low-modulation region”, i.e., 0<r<n−1, the command reference vector Vref142does not need to be modified by the modulation region classifier610, so
Vref0=Vref,  (8)
and the values of Vm0, θ0, Vrx0, and Vry0can be obtained by Equation (7).

FIG. 7Bshows an example of the reference vector Vref142located in the “over-modulation region”, i.e., r=n, i.e., the command reference vector142is modified by the modulation region classifier610. The circle755with the radius of Vm, i.e., the magnitude of the command reference vector Vref142, and the circle755is the requested reference vector trajectory. Limited by the n-level space vector diagram, however, the real reference vector trajectory is drawn by bolded lines760.

There are two possible locations of the command reference vector Vref142. One possible location of Vrefis that the command reference vector Vrefis inside the n-level space vector diagram, e.g. the vector Vr1770, and in this condition Vr1does not need to be modified by the modulation region classifier610. The other possible location of Vref142is that the command reference vector Vrefis outside the n-level space vector diagram, e.g. the vector Vr2780, and in this condition Vr2needs to be modified to the vector Vr3790.

In one embodiment, the modified reference vector Vref0for the reference vector Vreflocating in the “over-modulation region” is calculated as follows

Determining Set of Vertex Vectors of Reference Vector

Determining the location of the reference vector includes determination of the switching states at the first vertex244of the modulation triangle of the command reference vector142. Such determination can be treated differently by the reference vector location generator620according to the modulation region in. Equation (6) and the modified reference vector Vref0in Equation (8) or Equation (9) determined by the modulation region classifier610.

Generally, if the modulation region of the command reference vector Vref142of the n-level inverter is r determined by Equation (6) and 0<r<n−1, i.e., then the command reference vector Vrefis in the “low-modulation region,” then the command reference vector Vrefis treated as in a (r+1)-level space vector diagram instead of in a n-level space vector diagram by the reference vector location generator620of the invention. For example, the modulation region for the reference vector700shown inFIG. 7Ais r=2<n−1, thus the reference vector700is in the low-modulation region and is treated as in a 3-level space vector diagram by the reference vector location generator620of the invention.

If the modulation region of the command reference vector Vrefof the n-level inverter is r determined by Equation (6) and r=n−1, i.e., then the command reference vector Vrefis in the “regular region”, or r=n, i.e., the command reference vector Vrefis in the “over-modulation region,” then the command reference vector Vrefis treated as in the n-level space vector diagram by the reference vector location generator620of the invention. The difference is that when the command reference vector Vrefis locating in the “over-modulation region”, i.e., r=n, the command reference vector Vrefis modified by Equation (9). If the reference vector Vrefis in the “over-modulation region” or the “regular region,” then the modified reference vector Vref0is treated as in the n-level space vector diagram by the reference vector location generator620.

FIGS. 8A-Cshow an example of a method implemented by, e.g., the reference vector location generator620, for determining the set of vertex vectors based on determining a set of nested hexagons370,360, and350enclosing the reference vector240. For exemplifying purposes, the space vector diagram of the five-level inverter as shown inFIG. 2Bis used in this example. It's understood that this method can be implemented in any level inverters.

The space-vector diagram of the n-level inverter is partitioned into six sectors by six dashed lines850. The six dashed lines850pass through the center300of the n-level space-vector diagram and their angles are from π/6 to 11π/6, and the angle between any two adjacent dashed lines is π/3. Then consider the space-vector diagram of the n-level inverter as being composed of six hexagons that are the space-vector diagrams of (n−1)-level inverters. For clarity, only three hexagons810,820, and370of the six hexagons that are the space-vector diagrams of (n−1)-level inverters are shown inFIG. 8A.

The center vertices of the six (n−1)-level hexagons also form a hexagon830, whose center vertex300is the center vertex300of the original n-level space-vector diagram. For each sector enclosed by two adjacent dash lines850, the reference vector lying within is considered as only belonging to one of the six (n−1)-level hexagons. Number the six (n−1)-level hexagons from 1 to 6, and consider the ith(i=1, 2, . . . 6) sector belonging to the ith(n−1)-level hexagon, whose center vertex is in the sector. If the order number of the (n−1)-level hexagon370that contains the reference vector240is S1(S1=1, 2, . . . 6), then the order number of the selected (n−1)-level hexagon370, called the nested (n−1)-level hexagon370, can be determined by the phase angle θ0of the reference vector Vref0240as

Some embodiments of the invention determine a set of nested hexagons enclosing the reference vector. Each nested hexagon corresponds to a specific level, wherein the specific level ranging from the level of the inverter to a second level inverter. Next, the set of vertex vectors sequentially connecting centers of the nested hexagons is determined. In those embodiments, the first vertex is a center vertex of the second level inverter.

For example, because the phase angle of the Vref0240shown inFIG. 8Ais π/2<θ0<5π/6, the order number of the nested (n−1)-level hexagon370containing the Vref0240is S1=3. The value of S1can also be determined by Equation (11)

s1={1,if⁢⁢(Vr⁢⁢x⁢⁢0>0⁢⁢and-33⁢Vr⁢⁢x⁢⁢0<Vry⁢⁢0≤33⁢Vr⁢⁢x⁢⁢0);2,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢0>0⁢⁢and⁢⁢Vry⁢⁢0>33⁢Vr⁢⁢x⁢⁢0)⁢⁢or(Vr⁢⁢x⁢⁢0=0⁢⁢and⁢⁢Vry⁢⁢0>0);3,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢0<0⁢⁢and⁢⁢Vry⁢⁢0>-33⁢Vr⁢⁢x⁢⁢0);4,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢0<0⁢⁢and⁢⁢33⁢Vr⁢⁢x⁢⁢0≤Vry⁢⁢0<-33⁢Vr⁢⁢x⁢⁢0);5,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢0<0⁢⁢and⁢⁢Vry⁢⁢0<33⁢Vr⁢⁢x⁢⁢0);6,else(11)
where Vrx0and Vry0represent the real part and imaginary part of Vref0240, respectively. The value of s1is used to determine the switching states at the center vertex302of the nested (n−1)-level hexagon370according to the first mapping ofFIG. 4A.

After the value of s1is determined, the origin of the reference vector240is changed to the center302of the nested (n−1)-level hexagon370. This is achieved by subtracting the vertex vector310connecting the two center vertices300and302of the n-level hexagon260and the nested (n−1)-level hexagon370from the reference vector240, as shown inFIG. 8B. Generally, the new reference voltage vector Vref(1)860, called the subtracted reference vector860, can be obtained as

With the subtracted reference vector Vref(1)860, the nested (n−1)-level hexagon370can also be partitioned into six sectors by dashed lines865and is composed of six hexagons that are the space-vector diagrams of (n−2)-level inverters. Then, a new subtracted reference vector Vref(2)870and the order number S2of a nested (n−2)-level hexagon360can be determined. The processing is similar to the processing with the n-level space-vector diagram described above. Repeat the above processing, as shown inFIG. 8AtoFIG. 8C, until the finally selected nested hexagon350becomes the space-vector diagram of a second-level inverter, as shown inFIG. 3A. Accordingly, a center vertex of the nested hexagon of the specific level is determined based on the angle of a subtracted reference vector connecting a center vertex of a closest higher-level nested hexagon and the reference vector.

There are totally (n−2) such steps for an n-level inverter, and after the (k+1)thstep, k=1, 2, . . . n−3, the order number Sk+1of the selected nested (n−k−1)-level hexagon and the subtracted reference vector Vref(k+1)are

sk+1={1,if⁢⁢(Vr⁢⁢x⁢⁢(k)>0⁢⁢and-33⁢Vr⁢⁢x⁢⁢(k)<Vry⁢⁢(k)≤33⁢Vr⁢⁢x⁢⁢(k));2,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢(k)>0⁢⁢and⁢⁢Vry⁢⁢(k)>33⁢Vr⁢⁢x⁢⁢(k))⁢⁢or(Vr⁢⁢x⁢⁢(k)=0⁢⁢and⁢⁢Vry⁢⁢(k)>0);3,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢(k)<0⁢⁢and⁢⁢Vry⁢⁢(k)≥-33⁢Vr⁢⁢x⁢⁢(k));4,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢(k)<0⁢⁢and⁢⁢33⁢Vr⁢⁢x⁢⁢(k)≤Vry⁢⁢(k)<-33⁢Vr⁢⁢x⁢⁢(k));5,else⁢⁢if⁢⁢(Vr⁢⁢x⁢⁢(k)<0⁢⁢and⁢⁢Vry⁢⁢(k)<33⁢Vr⁢⁢x⁢⁢(k));6,else.(13)⁢andVref⁡(k+1)=Vref⁡(k)-Vd⁢⁢c·ⅇj⁡(sk+1-1)⁢π/3=Vm⁡(k+1)·ⅇjθk+1=Vrx⁡(k+1)+j·Vry⁡(k+1)(14)
where Vdcis the voltage of the DC source110, Vm(k+1)and θk+1are the magnitude and phase angle of the subtracted reference vector Vref(k+1). Vrx(k+1)and Vry(k+1)are real numbers and represent the real part and imaginary part of Vref(k+1), respectively.

At the final step, Vref(n-2)340is determined, and Vref(n−2)340can be decomposed into two vectors as with the second-level inverter, as shown inFIG. 3B. The nearest three vectors of the reference vector240are the vectors V01242, V02244, and V03246, as shown inFIG. 2B. The detailed decomposition processing of Vref(n-2)340in the present invention is described below.

The subtracted reference vector at the final step, i.e., Vref(n-2)340, is called the remainder vector340and is signed with V′refas
V′ref=Vref(n−2)=Vdc·(Vrx+j·Vry)  (15)
where Vrxand Vryare real numbers and represent the real part and imaginary part of V′ref/Vdc, respectively. The first vertex244of the modulation triangle is the center vertex244of the nested second-level hexagon350at the final step.

FIG. 9Ashows an example of the reference vector Vreflocating in the “low-modulation region.” The Vrefstill can be handled by the above-described method. For example, a reference vector Vf1700is in the low-modulation region and the corresponding vertex vectors are910,920, and930. The first vertex253of the modulation triangle of the reference vector Vf1700can be determined as shown inFIG. 9A.

FIG. 9Bshows an example of the method of another embodiment that handles the reference vector Vreflocating in the “low-modulation region” in a more simplified way. According to the modulation region of the reference vector Vf1700calculated in Equation (6) by the modulation region classifier610, the reference vector Vf1700is treated as in the 3-level space-vector diagram710. The corresponding vertex vector is910as shown inFIG. 9B, and the number of the vertex vectors is reduced from three to one. The first vertex253of the modulation triangle of the reference vector Vf1700is also determined by the embodiment ofFIG. 9B.

Based on the first mapping of switching states, the switching states970at the first vertex253of the modulation triangle of the reference vector Vf1700according toFIG. 9AandFIG. 9Bcan be calculated as shown inFIG. 9CandFIG. 9D, respectively. The invalid switching state −100960is excluded at the final step inFIG. 9CandFIG. 9D, and the switching states970at the first vertex253of the modulation triangle can be verified by being compared with the switching states at the vertex253shown inFIG. 2B. When the modulation region classifier610is not adopted and the reference vector700is in the low-modulation region as inFIG. 9A, the invalid switching states950−100, 354, and −110 for the vertices253and913of the vertex vectors910and920are not excluded during the modification shown inFIG. 9Cbefore the final step of the modification is implemented, and the invalid switching state −100960is excluded at the final step where the first vertex253of the modulation triangle is reached. However, if the modulation region classifier610of the present invention is adopted, then the invalid switching states490454, 353, and −120 and960−100 can be excluded sequentially during the modification, as shown inFIG. 4BandFIG. 9D, respectively. Because the number of both the vertex vectors and the switching states at the vertices of the vertex vectors is reduced by adopting the modulation region classifier610when the command reference vector Vrefis locating in the low-modulation region, the modulation region classifier610decreases the processing time of the SVPWM.

FIG. 10shows example of possible origins of the remainder vector V′refas hexagons1010,1020, and1030and the center vertex300of the n-level space vector diagram that can be used by the modulation region classifier610. The number of switching states at the vertices on the smaller hexagon can be larger than the number of switching states at the vertices on the bigger hexagon. For example, the vertex253is on the hexagon1030and the vertex913is on the bigger hexagon1020, and the number of switching states at the vertex253, i.e., four, is more than the number of switching states at the vertex913, i.e., three. The reason why the invalid switching states950−100, 354, and −110 during the modification of switching states shown inFIG. 9Cis not excluded can be explained as follows. Because the vertex vector930inFIG. 9Ais from the vertex913to a vertex253with less switching states, i.e., the vertex vector930points from a bigger hexagon1020to smaller hexagon1030, the valid switching state 344980inFIG. 9Cis removed when the invalid switching state 354950is excluded during the modification, and thus all the switching states are retained until the final step of the modification. Because of the modulation region classifier610, the vertex vectors of the reference vector does not point from a bigger hexagon to a smaller hexagon as the vertex vector930inFIG. 9Adoes, and the invalid switching states, e.g.490454, 353, and −120, can be excluded sequentially during the modification as inFIG. 4B.

The rational for the first mapping is based on Equation (14). The shift of the origin of the reference vector Vref(k)at the (k+1)thstep is Vdc·ej(sk+1−1)π/3, which is determined by the order number Sk+1of the selected nested hexagon and can be substituted into Equation (1) to determine the required modification for the current switching states of phase A, B, or C.

Duty Cycles

Based on the remainder vector V′ref, the duty cycles are determined in the similar way by the duty cycles generator630, independent of the levels the inverter. As shown inFIG. 11A, any 2-level space vector diagram contains 6 vectors, V1-V6, and the corresponding duty cycles of these vectors are named as T1-T6. In the present invention, the 2-level space vector diagram is partitioned into 6 regions by those vectors, and each region is numbered with a value named reg, reg=1, 2, . . . 6. The values of vectors V1-V6are
Vreg=Vdc·ej·(reg−1)·π3, reg=1, 2, . . . 6  (16)

The selection of the vectors and the calculation of the corresponding duty cycles are done by two steps. First, determine the region containing V′refas follows:

Two vectors are selected as Vregand Vreg+1, when reg<6. When reg=6, those two vectors are V6and V1. For example, if the remainder vector V′ref340is as shown inFIG. 11A, then the region number is reg=2, and V2and V3are the selected vectors.

After the region number reg is determined, the following equation is met:
Ts·V′ref=Treg·Vreg+Treg+1·Vreg+1=Vdc·(T3·ej·(reg−1)·π/3+T4·ej·reg·π/3)  (18)
where Tsis the switching cycle and Ts=1/fswhere fsis the command switching frequency144. When reg=6, Vreg+1and Treg+1mean V1and T1, respectively.

Then substitute Equation (15) into Equation (18) and the duty cycles can be determined as

For the vectors from the center vertex300of the n-level space vector diagram to the first vertex244of the modulation triangle of the reference vector240, or called the “zero vectors” in the present invention, their total duty cycles are
T0=Ts−Treg−Treg+1,  (20)
where Tsis the switching cycle as in Equation (18). For a multilevel inverter, there are usually no less than two switching states for the first vertex244of the modulation triangle, as shown inFIG. 3B. In the SVPWM method of some embodiments, two switching states, e.g.,142and031as inFIG. 3B, for the first vertex244of the modulation triangle are used, and each switching state for the first vertex244of the modulation triangle represents a “zero vectors”. The duty cycles of the “zero vectors” are

The duty cycles of the zero vectors can be adjusted by tuning the ratio β in Equation (21). Because different zero vectors can have different influence in the voltages of the DC link capacitors112,114,116, and118, the voltage balance of the DC link capacitors112,114,116, and118can be controlled by tuning the ratio β in Equation (21).

Switching Sequence

FIGS. 11A-Bshow illustration of two switching sequence modes used by some embodiments of the invention.FIG. 11Ashows an example where mode=1 and the switching sequence is counterclockwise selected.FIG. 11Bshows an example where mode=2 and the switching sequence is clockwise selected. Based on the second mapping, as shown inFIG. 5A, the value of reg and the value of mode, the switching sequence can be determined by the switching sequence generator640.

Take “ABC↑(L)” when reg=1 and mode=1 as an example to explain the switching sequence selection method in the present invention. Because reg=1, the vectors of the first sector, i.e., the vectors V1and V2are selected, and because mode=1, the switching sequence is V0→V1→V2→V0. From V0to V1, the change of the vector is Vdc, which can be substituted into Equation (1) and means that the switching state of phase A increases by one. From V1to V2, the change of the vector is Vdc·ej2π/3, which can be substituted into Equation (1) and means that the switching state of phase B increases by one. Similarly, from V2to V0, the change of the vector is Vdc·ej4π/3, which means the switching state of phase C increases by one. All the switching sequences for other values of reg and mode can be analyzed in the similar way, and the rule of determining the switching sequence can be mapped as the second mapping.

Such mapping simplifies the determination of the switching states during the operation of the inverter, and can be used by inverter of any level, and for reference vector of any region. For example, if the reference vector Vref1210is located in the low-modulation region as shown inFIG. 12A, and1220and1230are the vertex vectors and1240is the remainder vector with the region number reg=5, then the switching sequence can be calculated as shown inFIG. 12B, which can be verified by being compared with the space vector diagram shown inFIG. 12A.

The rule of determining the switching sequence represented by the second mapping can also be extended to produce the switching sequence for other specific requirements. For example, in some applications, the switching sequence is preferred to be symmetric. In other words, if the original switching sequence is V0→V1→V2→V0, then the preferred switching sequence is V0→V1→V2→V0→V2→V1→V0. The extended rule of determining the switching sequence for these applications is summarized inFIG. 13A, in which each element of the rule of determining the switching sequence is actually a combination of the two elements of the rule summarized inFIG. 5Aaccording to the corresponding region number reg of the remainder vector. For example, when reg=1 and mode=1, the rule of determining the switching sequence is “ABC↑CBA↓(L)”. As explained for the rule of determining the switching sequence shown inFIG. 5A, the letter “L” means the first switching state at the first vertex of the modulation triangle is not the top one; the next first three sequential switching states is generated according to the rule “ABC↑” as inFIG. 5Awhen reg=1 and mode=1, and the next second three sequential switching states is generated according to the rule “CBA↓” as inFIG. 5Awhen reg=1 and mode=2. Based on the rule of determining the switching sequence shown inFIG. 13Ain the present invention, the switching sequences of the reference vector Vref1210shown inFIG. 12Aaccording to different switching sequence modes are shown inFIG. 13B, and the switching sequences can be verified by being compared with the space vector diagram shown inFIG. 12A.

It can be seen fromFIG. 12BandFIG. 13Bthat many switching sequences can be selected for some reference vectors, e.g., for the reference vector1210shown inFIG. 12A. Since different switching sequences can have different influence in the voltages of the DC link capacitors112,114,116, and118, the voltage balance of the DC link capacitors112,114,116, and118can be controlled by selecting the appropriate switching sequences in the present invention.

Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, minicomputer, or a tablet computer. Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

In this respect, the invention may be embodied as a computer readable storage medium or multiple computer readable media, e.g., a computer memory, compact discs (CD), optical discs, digital video disks (DVD), magnetic tapes, and flash memories. Alternatively or additionally, the invention may be embodied as a computer readable medium other than a computer-readable storage medium, such as a propagating signal.

The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of the present invention as discussed above.