Contact structure for improving photoresist adhesion on a dielectric layer

A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

FIELD OF THE INVENTION 
The present invention relates generally to semiconductor integrated circuit 
processing, and more specifically to improving photoresist adhesion on a 
dielectric layer. 
BACKGROUND OF THE INVENTION 
Insulators or dielectrics have widespread use in semiconductor processing. 
Silicon dioxide films are best known for their use as passivation to 
provide physical and chemical protection to the underlying devices and 
components. Silicon nitride films have also been widely used as a 
passivation layer providing additional scratch protection due in part to 
its hardness. The role of silicon dioxide films in processing has 
expanded. Deposited silicon dioxide films are now used as interlevel 
dielectrics between polysilicon and metal lines, as isolation films, as 
dopant barriers and as diffusion sources. 
Deposited silicon dioxide films have a different physical structure from 
thermally grown oxide films. Depending on the deposition temperature, the 
silicon dioxide may have, among others, a different density, dielectric 
strength and etch rate. The addition of dopants to deposited silicon 
dioxide films may change the chemical and physical properties of the 
films. Deposited silicon dioxide films may also undergo a process called 
densification. The deposition of films was started to allow for a 
low-temperature deposition to occur preventing undesirable redistribution 
of impurities in the underlying regions during the processing steps. The 
densification of the silicon dioxide after deposition forms a film with 
physical and chemical properties approximating that of thermally grown 
oxide films. 
There are several benefits of adding dopants to the silicon dioxide films. 
The moisture barrier properties of the films increase. Contaminants are 
prevented from entering the underlying layers and the viscosity of the 
films increase. This last benefit of increasing the flow property enhances 
the planarization of the surface of the film. Typically, boron and 
phosphorous are added to the silicon dioxide to enhance the flow property. 
The resultant film is known as borophosphorous silicate glass (BPSG). 
As the concentration of dopants increases in the glass film, the 
temperature at which the film will reflow decreases. The lower processing 
temperature to cause reflow will not effect the electrical performance of 
the devices and components. As additional dopants are added, however, the 
surface of the glass layer becomes dopant rich. This increased 
concentration at the surface causes adhesion problems during subsequent 
contact patterning processes. In other words, the ability of photoresist 
to adequately adhere to the doped glass layer is significantly reduced. 
After the photoresist is formed over the glass layer and patterned, the 
opening formed in the photoresist is cleaned to remove any remaining 
photoresist residue in the areas where a contact is to be etched. This 
process, called descuming, enhances the photoresist's ability to adhere to 
the underlying glass layer. However, during the process of cleaning, a 
portion of the sidewalls of the photoresist is also removed. The removal 
of any of the photoresist along the sidewalls is becoming unacceptable in 
the submicron geometries. 
It would be desirable to provide a technique which increases the adhesion 
of photoresist to the underlying dielectric layer. It would further be 
desirable for such a technique to be easily adapted for use with standard 
integrated circuit fabrication process flows without increasing the 
complexity of the process. 
SUMMARY OF THE INVENTION 
The invention may be incorporated into a method for forming a semiconductor 
device structure, and the semiconductor device structure formed thereby, 
by forming a first dielectric layer over the integrated circuit wherein 
the dielectric layer has a dopant concentration at an upper surface 
sufficient enough to allow the layer to be reflowed while partially 
inhibiting adhesion of the layer to photoresist at the upper surface. A 
second undoped dielectric layer is formed over the first dielectric layer. 
An opening is formed in the first and second dielectric layers exposing a 
portion of an underlying conductive structure wherein a portion of the 
dielectric layers has outwardly sloping sidewalls at the opening.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The process steps and structures described below do not form a complete 
process flow for manufacturing integrated circuits. The present invention 
can be practiced in conjunction with integrated circuit fabrication 
techniques currently used in the art, and only so much of the commonly 
practiced process steps are included as are necessary for an understanding 
of the present invention. The figures representing cross-sections of 
portions of an integrated circuit during fabrication are not drawn to 
scale, but instead are drawn so as to illustrate the important features of 
the invention. 
Referring to FIG. 1, an integrated circuit device is to be formed on a 
silicon substrate 10. A field oxide region 12 is formed on the substrate 
to separate active areas. A conductive structure such as a transistor gate 
is formed on the substrate by known methods comprising gate electrode 14 
disposed over a gate oxide 16. The transistor will also comprise oxide 
spacers 18 and source/drain regions 20. Another conductive structure 22, 
such as a polysilicon signal line, may be formed over the field oxide 
region 12. 
A first conformal dielectric layer 24 is formed over the integrated 
circuit. Layer 24 may typically comprise an undoped oxide or a silicon 
nitride having a thickness between approximately 100 to 2000 angstroms. A 
second dielectric layer 26 is formed over the first dielectric layer. 
Layer 26 is typically a conformal BPSG layer having a thickness of between 
approximately 3000 to 8000 angstroms. The BPSG layer may be formed by 
chemical vapor deposition. 
The BPSG layer 26 is then reflowed to form a more planar surface. The BPSG 
layer will typically have a dopant concentration of 2-4 percent boron and 
4-7 percent phosphorous. At this concentration, the BPSG layer will flow 
at a reasonably low temperature between approximately 850.degree. to 
900.degree. C. However, at this concentration, the upper surface of the 
BPSG layer 26 will become dopant rich. Any photoresist applied to the BPSG 
layer at this stage would not adequately adhere to the BPSG. Therefore, a 
third conformal dielectric layer 28 is formed over the BPSG layer. Layer 
28 is typically an oxide layer having a thickness of between approximately 
50 to 300 angstroms. The etch rate of this oxide layer should be closely 
matched to that of the BPSG layer 26. A photoresist layer 30 is then spun 
onto the oxide layer 28 and patterned to form an opening 32 where a 
contact opening will be subsequently etched through the dielectric layers. 
The oxide layer 28 is undoped allowing the photoresist layer 30 to 
adequately adhere to the oxide. 
Referring to FIG. 2, the dielectric layers 24, 26 and 28 are etched in 
opening 32 to expose an underlying conductive structure such as the 
source/drain region 20 as shown in FIG. 2. The etch process is generally a 
wet etch followed by a dry etch. The wet etch is an isotropic etch which 
forms sloped sidewalls 34. The dry etch is an anisotropic etch which forms 
the vertical sidewalls 36. The undoped oxide layer 28 provides for 
adequate adhesion of the photoresist layer 30 to the oxide layer 28. This 
adhesion prevents unwanted undercutting of the upper portion of the 
dielectric layer 28 during the wet etch step. The contact opening thus 
remains relatively constant. Moreover, the undoped oxide layer 28 has 
substantially the same etch rate as the BPSG layer 26. 
Referring to FIG. 3, the photoresist layer 30 is removed. the undoped oxide 
layer 28 does not have to be removed. Thus, at this stage, the complexity 
of the process is not increased. An alternative to the above process is to 
carry out the steps as described above up until the reflow of the BPSG 
layer 26. At this point, the BPSG layer is densified by a high temperature 
anneal process. The third dielectric layer 28 is then formed over the BPSG 
layer 26. The photoresist layer 30 is formed and patterned and the contact 
opening 32 is etched to expose the underlying conductive structure as 
described above. The reflow step is then performed to planarize the 
dielectric layers. 
The thin undoped oxide layer 28 provides a medium for the photoresist layer 
to adhere to the interlevel dielectric to insure a higher quality contact 
opening. The oxide layer 28 does not need to be removed allowing this 
technique to be used with standard integrated circuit process flows. 
As will be appreciated by those skilled in the art, the process steps 
described above can be used with nearly any conventional process flow. 
While the invention has been particularly shown and described with 
reference to a preferred embodiment, it will be understood by those 
skilled in the art that various changes in form and detail may be made 
therein without departing from the spirit and scope of the invention.