Enhancements to cell layout and fabrication techniques for MOS-gated devices

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on provisional application Ser. No. 62/653,104, filed Apr. 5, 2018, by Richard A. Blanchard et al., assigned to the present assignee and incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to insulated gate turn-off (IGTO) devices and, more particularly, to improvements in cell layouts and fabrication techniques for forming an IGTO device that includes an integrated turn-off transistor for faster removal of carriers when turning off the device.

BACKGROUND

Prior artFIG. 1is a cross-section of a small portion of an IGTO device10(similar in some respects to a thyristor) of the type described in the assignee's U.S. Pat. No. 9,391,184, incorporated herein by reference. The device10includes a plurality of cells having vertical gates12formed in insulated trenches. A 2-dimensional array of the cells may be formed in a common p-well14, and the cells are connected in parallel. The gates12are formed as a continuous rectangular mesh.

The vertical gates12are insulated from the p-well14by an oxide layer16. The narrow gates12(doped polysilicon) are connected together outside the plane of the drawing and are coupled to a gate voltage via the gate electrode18contacting the polysilicon. A patterned dielectric layer20insulates a cathode metal22(cathode electrode) from the gates12. The dielectric layer20thickness between the top of the gates12and the cathode metal22is much larger than the gate oxide16thickness.

An NPNP semiconductor layered structure is formed. There is a bipolar PNP transistor formed by a p+ substrate24, an n− epitaxial (epi) buffer layer26, a relatively thick and more lightly doped n− epi layer28, and the p− well14. There is also a bipolar NPN transistor formed by the n-epi buffer layer26, the n− epi layer28, the p-well14, the n layer30, and the n+ source32. The n-epi buffer layer26, with a dopant concentration higher than that of the n− epi layer28, reduces the injection of holes into the n− epi layer28from the p+ substrate24when the device is conducting. A bottom anode metal34(anode electrode) contacts the substrate24, and the cathode metal22contacts the n+ source32. The p-well14surrounds the gate structure.

When the anode metal34is forward biased with respect to the cathode metal22, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the PNP and NPN transistors is less than one (i.e., there is no regeneration activity). Additionally, emitter-to-base shorts are distributed throughout the device, providing an additional reduction in gains.

When the gate is forward biased, electrons from the n+ source32become the majority carriers along the gate sidewalls and below the bottom of the trenches in an inversion layer, causing the effective width of the NPN base (the portion of the p-well14between the n-layers) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This results in “breakover,” when holes are injected into the lightly doped n− epi layer28and electrons are injected into the p-well14to fully turn on the device. Accordingly, the gate bias initiates the turn-on, and the full turn-on (due to regenerative action) occurs when there is current flow through the NPN transistor as well as current flow through the PNP transistor. During this latch-up, the on-voltage across the device is desirably lower, and the device acts as a thyristor.

A p+ region36is formed on both sides of the n+ source32, adjacent the gate12, and extends below the n+ source32. The n layer30extends below the p+ region36to form a channel in a vertical p-channel MOSFET. The p+ regions36and the n+ source32are shorted together by the cathode metal22.

When the gate voltage applied to the gate electrode18is above the threshold for turn-on of the IGTO device, the vertical p-channel MOSFET is off and has no effect on the operation. When the current through the IGTO device is sufficiently high, thyristor action is initiated, and the device can be turned off simply by shorting the gate to the cathode metal22. By applying a gate voltage sufficiently lower than the cathode voltage (to exceed the threshold voltage of the p-channel MOSFET), the n layer30adjacent to the gate12inverts to create a p-channel between the p+ region36and the p-well14. This conducting p-channel MOSFET hastens turn-off by shorting the base-emitter diode of the vertical NPN transistor, forcing the NPN transistor to turn off. Therefore, there is no further regenerative action. The doping level of the n layer30determines the threshold voltage of the “enhancement mode” p-channel MOSFET. Additionally, majority carriers in the p-well14are rapidly removed from the p-well14(via the cathode metal22) when the p-channel MOSFET conducts, greatly reducing the turn-off time.

The maximum current that can be turned off using the p-channel “pull-down” MOSFET is also increased due to the p-channel MOSFET forcing the turn off of the NPN transistor by electrically connecting its base to its emitter when the p-channel MOSFET is turned on.

FIG. 2is a top down view of the rectangular area surrounded by the cell's gate12. The cathode metal22is not shown. The p+ regions36may take up any portion of the semiconductor surface. A larger area taken up by the p+ regions36, relative to the n+ source32, improves the turn-off time but undesirably increases the on-resistance. A much larger p+ region36may be continuous around the inner wall of the gate in a cell, or make up any other portion of the semiconductor surface.

FIG. 2shows a minimum-width cathode metal contact area40(an etched opening in the dielectric layer20) that results in the cathode metal directly contacting both the p+ regions36and the n+ source32.

FIG. 3is taken across the IGTO device10along line3-3inFIG. 2. When the device10is conducting, the electron flow44from the n+ source32takes a relatively short horizontal path near the surface and flows vertically near the gate12where the n layer30has the least resistance in the on-state. In the p-well14, the electron flow44spreads out.

FIG. 4is taken across the IGTO device10along line4-4inFIG. 2. InFIG. 4, due to the p+ regions36, the electron flow46must take a different path through the n layer30, which has a resistance that is higher than along the gate12shown inFIG. 3. As a result, the resistance and forward voltage (Vf) are increased due to the p+ regions36.

Therefore, a compromise must be made between the lowest on-resistance and the shortest turn-off time.

FIG. 5illustrates a normalized forward voltage (Vf) curve and a normalized turn-off time curve versus the percentage area of the pull-down MOSFET area. The Vf, related to on-resistance, increases with the percentage area of the pull-down MOSFET due to the redirected current flow shown inFIG. 4, but the turn-off time decreases with the percentage area of the pull-down MOSFET. Simulations have shown that the turn-off energy does not significantly vary once the percentage of the pull-down MOSFET exceeds about 50%.

The gate-to-gate spacing is also very relevant to Vf, since a higher density of gates results in more low-resistance vertical paths for the electrons from the n+ source32when the device is on.FIG. 6is identical toFIG. 1but identifies the gate-to-gate spacing (e.g., 1.5-2.0 microns) and the required minimum contact opening in any top dielectric layer for the cathode metal22to contact both the p+ regions36and the n+ source32. By reducing the minimum contact opening width, opposing gate walls can be closer together, improving surface utilization and, therefore, Vf.

FIG. 7illustrates the effect of gate-to-gate spacing on Vf for three cathode-anode voltages V1, V2, and V3, where V3>V2>V1. To the left of the line48, there is increasing pinch-off of the vertical conduction path due to the gate-to-gate spacing being too narrow and, to the right of the line48, conduction area is being wasted by the gate-to-gate spacing being too high. As seen, there is an optimized gate-to-gate spacing along line48. However, the shape and percentage area of the pull-down MOSFET between the gates limits the gate-to-gate spacing, since the cathode metal must contact both the p+ region36and the n+ source32.

Although the device ofFIG. 1has proven to be an improvement over other prior art MOS-gated devices, it is desirable to further improve the device by improvements in the dimensions of the cells, the shape and relative size of the pull-down MOSFET, and other characteristics.

SUMMARY

This disclosure describes a wide variety of cell designs that enable optimal gate-to-gate spacing while also optimizing the size of the pull-down MOSFET. As a result, both Vf and turn-off time are reduced. This disclosure describes cell layouts that have a higher layout efficiency compared to the layouts described in the prior art, where an improvement in layout efficiency results in a lower Vf for the same area.

Additionally, a technique for changing the threshold voltage (Vth) of the pull-down p-channel MOSFET, including even making it a depletion mode pull-down MOSFET (rather than the prior art enhancement mode pull-down MOSFET), is described. In this new technique, boron ions are implanted in the sides of the trenches at an angle, so only the upper and middle portions of the trench walls are doped with the p-type dopant. The boron ions are implanted in areas that will eventually be the channel region of the pull-down p-channel MOSFET. This additional p-type doping changes the threshold voltage (Vth) of the p-channel MOSFET to any selected degree. Therefore, the gate turn-off voltage of the IGTO device can be customized.

If the dose of the boron ions is sufficiently large, the angled implant creates a depletion channel in a depletion mode vertical pull-down MOSFET. In this instance, the pull-down MOSFET conducts at a zero gate voltage when the IGTO device is off. When the gate voltage is positive and above the threshold voltage of the IGTO device (the device is on), the depletion mode pull-down MOSFET is turned off so has no effect. By simply removing the gate voltage to turn off the IGTO device, the depletion mode pull-down MOSFET conducts to turn off the vertical NPN transistor as well as to quickly remove carriers from the p-well.

Other improvements are disclosed.

Elements that are the same or equivalent are labelled with the same numerals.

DETAILED DESCRIPTION

The novel cell designs and MOSFET structures described below can also be used in vertical devices other than the type of IGTO device shown inFIG. 1. For example, the designs and structures could also improve the performance of insulated gate bipolar transistor (IGBT) devices.

FIG. 8is a top down view of a portion of a cell of an IGTO device between two vertical gates.FIG. 9is taken across line9-9inFIG. 8, andFIG. 10is taken across line10-10inFIG. 8.

FIGS. 9 and 10do not show any part of the cell below the p-well14, but the remainder may be similar to that shown inFIG. 1, where the n-type layers26and28and p+ substrate34are below the p-well14. In another embodiment, the gate may extend completely through the p-well14(rather than terminate within the p-well14), causing the device to be similar to an IGBT. This gate extension to form an IGBT applies to all the embodiments.

One significant difference between the configurations of the p+ region52and the n+ sources54and55ofFIG. 8and the p+ region36and the n+ source32ofFIG. 2is that there is a gap between the two n+ sources54and55. Within the gap is a portion of the p+ region52. The p+ region52forms part of the pull-down MOSFET used for rapidly turning off the IGTO device. The area of the p+ region52surrounding the n+ sources54and55and abutting the gates may be made much narrower to reduce pinching off the electron flow and allow closer gate-to-gate spacing. Hence, the most relevant aspect ofFIG. 8is the horizontal layout of the p+ region52between the n+ sources54and55, which extends to the sides of the gates. The remainder of the p+ region52can even be deleted to increase the percentage area of the n+ sources54and55along the gates to improve the forward voltage Vf.

The contact opening58in the dielectric60(FIG. 9) can be very narrow since the cathode metal (over the dielectric60and in the contact opening58) only needs to directly contact a portion of the horizontal strip of the p+ region52and the n+ sources54and55. This enables the gate-to-gate spacing to be smaller to increase the cell density and reduce the Vf.

FIG. 11illustrates another design of the p+ region62of a pull-down p-channel MOSFET relative to the n+ source64.FIG. 12is taken across line12-12inFIG. 11, andFIG. 13is taken across line13-13inFIG. 11. In this embodiment, the relative size of the n+ source64is increased for improved Vf, yet the contact opening66for the cathode metal can be very narrow, allowing smaller gate-to-gate spacing for improved Vf. The p+ region62has horizontal fingers that extend into the n+ source62, where the horizontal fingers are contacted by the cathode metal. As inFIGS. 9 and 10, the layers below the p-well14are not shown but may be similar to those layers inFIG. 1or layers for forming an IGBT.

FIGS. 12 and 13illustrate that the p+ region62does not extend along the wall of one of the opposing gates12, and the n+ source64does not extend along the wall of the other one of the gates12. In this embodiment, the percentage area of the p+ region62is about 50% of the top area between the gates12. Since the n+ source64is relatively large and next to one of the gate walls, there is very low on-resistance, since electrons injected by the n+ source64do not need to flow horizontally through the higher resistance n layer30. The n layer30along the gate wall is highly conductive when the IGTO device is on. As a result, the Vf, and turn-off time are very low.

FIGS. 14-16illustrate an embodiment of an IGTO device that includes a pull-down p-channel MOSFET, where the n layer30inFIGS. 1, 9, and 12is not formed below the n+ source70.FIG. 15is taken across line15-15inFIG. 14, andFIG. 16is taken across line16-16inFIG. 14. InFIGS. 14-16, the n layer72is only formed below the p+ region74and connects to the n+ source70. Since the n+ source70extends to the gate wall, there is a very low resistance path from the n+ source70to below the gate12, due to the inversion of the p-well14next to the gate12. The narrow contact opening66is similar to that shown inFIG. 11so the gate-to-gate spacing may be small (e.g., less than 1.5 microns).

FIG. 17is a top down view of a portion of two cells between opposing gates12in an IGTO device having a pull-down p-channel MOSFET. The gates12are within trenches formed as a rectangular mesh of trenches. The rectangular cells will typically be elongated, and the horizontal regions of the gates12are not shown. The narrow rectangular contact openings76in a dielectric layer78(FIG. 18) over the gates12and over a portion of the semiconductor are shown. The cathode metal (not shown) overlies the dielectric78and directly contacts the exposed semiconductor surface.

The p+ regions80and n+ sources82are formed in strips perpendicular to the long edge of the rectangular cells.FIG. 18is a cross-section along line18-18inFIG. 17;FIG. 19is a cross-section along line19-19inFIG. 17; andFIG. 20is a cross-section along line20-20inFIG. 17.

The contact opening76can be made any width, while still allowing the cathode metal to contact all the rows of the p+ regions80and the n+ sources82, to optimize the gate-to-gate spacing for optimizing Vf and turn-off time.

In another embodiment, there is only a single row of the p+ region80per cell to increase the n+ source82area per cell.

FIGS. 21-24are process flow cross-sections across a single cell in an IGTO device to illustrate a technique to form a self-aligned cathode metal without having to form a contact opening. So there is a savings in not having to form an extra dielectric layer, aligning a contact opening mask, and then etching the contact opening. This basic process may be used to form the various IGTO devices described herein.

InFIG. 21, an n-type epitaxial (epi) layer84, forming the layers26and28inFIG. 1and in the other embodiments, is grown over a p+ substrate (e.g., substrate34inFIG. 1). An oxide layer86is formed over the surface of the n-type epi layer84. A silicon nitride layer88is then deposited over the oxide layer86. The layers86and88are then masked and etched to expose a trench area for the gates. The trenches90are then etched using reactive ion etching (RIE).

InFIG. 22, a thin gate oxide16is thermally grown over the sidewalls of the trench90. Doped polysilicon is then deposited in the insulated trenches to form the conductive gate12. Excess polysilicon is etched away. The top of the polysilicon is then oxidized to form a relatively thick oxide layer92over the gate12so the gate12potential will not be affected by the cathode metal voltage. The silicon nitride layer88is then etched away.

InFIG. 23, an implant step implants p-type boron ions into the n-epi layer84to form the p-well14. The boron dopant is then diffused. Another implant step implants n-type phosphorus ions into the surface of the n-type epi layer84to form the n layer30. The phosphorus atoms are then diffused. The surface is masked, and boron is implanted and diffused (by annealing) to form the p+ regions94for the pull-down MOSFET. The p+ region94configuration may be like any of those previously described. The surface is then masked, and arsenic is implanted and diffused (by annealing) to form the n+ source96.

InFIG. 24, a blanket etch is performed to expose the semiconductor surface between the gates12. The cathode metal22is then deposited and etched. The cathode metal22contacts the p+ region94and the n+ region96. As seen, no contact opening mask and etch are required in this area since the oxide92over the gate12is initially thick and can be etched back during the blanket etch that exposes the active area between the gates12. A mask and etch may be required to connect a metal gate electrode to the gate polysilicon.

FIGS. 25-32are directed to a technique to adjust the Vth of the pull-down p-channel MOSFET, including forming a depletion mode pull-down MOSFET, using a novel angled boron implant into the sidewalls of the trenches. Adjusting the Vth can be used to customize the gate turn-off voltage of the IGTO device.

FIG. 25is similar toFIG. 1except that a depletion mode pull-down MOSFET is formed, rather than an enhancement mode pull-down MOSFET. A depletion mode MOSFET conducts current when there is a zero gate-source voltage, since the channel98between the p-well14and the p+ region94is p-type. Therefore, the channel of the depletion mode pull-down MOSFET conducts at a zero gate voltage when the IGTO device is off. When the gate voltage is positive and above the threshold voltage of the IGTO device (the device is on), the depletion mode pull-down MOSFET is turned off so has no effect. By simply taking the gate voltage to zero volts, the pull-down MOSFET conducts to turn off the vertical NPN transistor and quickly remove carriers from the p-well14. Accordingly, no negative voltage generator is needed to generate the negative voltage that is needed to turn off the enhancement mode pull-down MOSFET of prior artFIG. 1.

FIG. 26is a cross-section of an empty trench102formed in an n-type epi layer104, such as the n-type epi layer84ofFIG. 21. The gate oxide16may or may not be present. Boron106is then implanted at an angle relative to the vertical sidewalls of the trench102, using the edge of the trench102to block the boron106from being implanted below a certain level of the trench102. An implant dose of 10e12-5e14 is used in one embodiment. For the angled implant, the wafer may be angled with respect to the boron source. The angle determines the length of the p-channel in a depletion mode MOSFET. Both sidewalls of the trench102may be subjected to separate angled implants. The boron106is then diffused by an anneal step to activate the dopants.

FIG. 27illustrates the formation of the resulting narrow p− region108that will be the channel of the depletion mode pull-down MOSFET.

InFIG. 28, the gate oxide layer16(if not already formed), the polysilicon gate12, n-epi layer28, the p-well14, n layer30, n+ source96, p+ region94, and oxide92are then formed, as described with respect toFIGS. 21-24. The p− region108forms the channel in the pull-down MOSFET between the p-well14and the p+ region94. A cathode metal is then formed over the surface, as inFIG. 24.FIG. 28shows a version of the device in which the boron is implanted along only one trench sidewall to form the p− region108.

FIG. 29illustrates one possible top down view of the active area inFIG. 28, showing the p+ region94having fingers that extend into the n+ source96. In such an embodiment, the boron is angle-implanted into only one sidewall of the trench102.

FIG. 30illustrates another embodiment of a top down view of the active area inFIG. 28showing the p+ region110and n+ source112.

FIG. 31illustrates the angled implantation of boron106into both sidewalls of the trench102to change the Vth of the pull-down p-channel MOSFET or to form a depletion mode pull-down MOSFET on both sides of a cell for improved turn-off time.

FIG. 32illustrates one possible top down view of the active area of an IGTO device having the depletion mode pull-down MOSFET on both sides of a cell, formed using the dual angled implants ofFIG. 31. The p+ regions114and116are along the gates, and the n+ source118is in the middle. A cathode metal will overlie some portions of the p+ regions114and116and the n+ source118.

The angled-implantation technique for forming a depletion mode MOSFET, whether n-channel or p-channel, can be used to form a vertical depletion mode MOSFET in any structure, whether or not the depletion mode MOSFET is used for turning off a device. An angled implant of arsenic into sidewalls of a trench would be used to form a depletion mode n-channel MOSFET.

FIGS. 33-35relate to forming a non-self-aligned contact opening for a cathode metal, where the p+ region for the pull-down MOSFET is a single horizontal strip.

FIG. 33is a top down view of the active area of an IGTO device cell, showing the n+ sources120and122and the p+ region124formed as a horizontal strip. The aligned contact opening126in a dielectric layer128(FIG. 34) allows the cathode metal to contact the n+ sources120and122and the p+ region124. The contact opening126can be made very narrow to allow small gate-to-gate spacings.

FIGS. 36-38relate to forming a self-aligned contact opening for a cathode metal, where the p+ region for the pull-down MOSFET is a single horizontal strip.

FIG. 36is a top down view of the active area of an IGTO device cell, showing the n+ sources130and132and the p+ region134formed as a horizontal strip.

After the trench is formed and filled with polysilicon to form the gate12, a relatively thick oxide136is grown over the polysilicon. A blanket etch removes any thin dielectric over the active area. The resulting exposed area between the gates12can then be contacted with a cathode metal layer without requiring the formation of a contact opening, thus saving a few process steps. This is similar to the process shown inFIGS. 21-24.

FIG. 39is a top down view of an array of four cells. The gates138are formed in trenches forming a rectangular mesh. Each cell includes the gates138(forming a mesh), and three n+ sources140,142, and144, formed as horizontal strips. Each cell also includes p+ regions146and148between the n+ sources140,142, and144. A contact opening150for the cathode metal contacts the n+ sources140,142, and144and the p+ regions146and148. Only a small portion of the cell is taken up by the p+ regions146and148, resulting in a low Vf. The p+ regions146and148along the gate walls may be the top regions of a pull-down MOSFET in each cell for turning off the cell. The gates138form fingers that extend into each cell to greatly add to the gate surface area to improve efficiency and Vf. The n+ sources140,142, and144are relatively long and narrow and are virtually surrounded by the gate138, except for the p+ region areas, so there is low on-resistance. The small area of the pull-down MOSFET is sufficient to greatly reduce the turn-off time.

FIG. 40is a top down view of a cell of an IGTO device, where the gate152and the n+ source154have interdigitated fingers for abutting along a very large surface area for high efficiency and low Vf. The p+ regions156are portions of pull-down MOSFET devices for rapidly turning off the device. A contact opening160allows the cathode metal to contact the n+ source154and p+ regions156. This concept of interdigitated fingers and the integrated pull-down MOSFET can be applied to other types of MOS-gated devices.

Any features described herein can be combined together and can be incorporated in more than one type of trench, MOS-gated power device.

The polarities of the various semiconductor regions may be reversed, depending on whether the top electrode is to be a cathode or an anode.