On-die termination circuit of semiconductor memory apparatus

An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2007-0023867, filed on Mar. 12, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

Embodiments of the present invention relate to a semiconductor memory apparatus, and more particularly, to an on-die termination circuit of a semiconductor memory apparatus.

2. Related Art

In general, when signals transmitted through a bus line having a predetermined impedance are input to another bus line having a different impedance, a signal loss occurs. Therefore, impedance matching between the two bus lines is needed to reduce the signal loss, which is referred to as on-die termination.

As shown inFIG. 1, an on-die termination apparatus according to the related art includes: an ODT input driver10that divides a power supply voltage VDDQ at a resistance ratio corresponding to a first code Pcode<0:N> and outputs a first line voltage P_out; a first comparator20that compares the first line voltage P_out with a reference voltage Vref according to a first code adjustment enable signal P_en and outputs a first comparison signal Pcmp_out; a first register30that counts the first code Pcode<0:N> according to the first comparison signal Pcmp_out; an ODT output driver40that divides the power supply voltage VDDQ at a resistance ratio corresponding to a second code Ncode<0:N> and outputs a second line voltage N_out; a second comparator50that compares the second line voltage N_out with the reference voltage Vref according to a second code adjustment enable signal N_en and outputs a second comparison signal Ncmp_out; and a second register60that counts the second code Ncode<0:N> according to the second comparison signal Ncmp_out. The ODT input driver10is modeled in the same manner as that in which a data input driver is modeled. The ODT output driver40is modeled in the same manner as that in which a data output driver is modeled.

Next, a code adjusting process according to the related art will be described below.

A process for adjusting the first code Pcode<0:N> and a process for adjusting the second code Ncode<0:N> may be performed at the same time, or they may be performed sequentially.

The process for adjusting the first code Pcode<0:N> is performed as follows.

The first code Pcode<0:N> having a predetermined value set by the first register30is input to the ODT input driver10.

The ODT input driver10divides the power supply voltage VDDQ at a resistance ratio of resistors that are connected according to the first code Pcode<0:N> and a line impedance detecting resistor and outputs the first line voltage P_out.

The first comparator20compares the first line voltage P_out and the reference voltage Vref according to the first code adjustment enable signal P_en and outputs the first comparison signal Pcmp_out.

The first register30counts the first code Pcode<0:N> according to the first comparison signal Pcmp_out.

The ODT input driver10feeds back the first line voltage P_out corresponding to the counted first code Pcode<0:N> to the first comparator20.

The first comparator20receives the first line voltage P_out and repeatedly performs the comparing operation and an operation for outputting the first comparison signal Pcmp_out.

The first code adjustment enable signal P_en is inactivated after a predetermined time.

When the first code adjustment enable signal P_en is inactivated, the first comparator20and the first register30stop, and at that time, the first code Pcode<0:N> is stored.

The process for adjusting the second code Ncode<0:N> is performed as follows.

An initial first code Ncode<0:N> set by the second register60is input to the ODT output driver40.

The ODT output driver40divides the power supply voltage VDDQ at a resistance ratio of resistors that are connected according to the first and second codes Pcode<0:N> and Ncode<0:N> and outputs a second line voltage N_out.

The second comparator50compares the second line voltage N_out and the reference voltage Vref according to the second code adjustment enable signal N_en and outputs the second comparison signal Ncmp_out.

The second register60counts the second code Ncode<0:N> according to the second comparison signal Ncmp_out.

The ODT output driver40feeds back the second line voltage N_out corresponding to the counted second code Ncode<0:N> to the second comparator50. The second comparator50repeatedly performs the comparing operation and an operation for outputting the second comparison signal Ncmp_out according to the second line voltage N_out.

The second code adjustment enable signal N_en is inactivated after a predetermined time.

When the second code adjustment enable signal N_en is inactivated, the second comparator50and the second register60stop, and at that time, the second code Ncode<0:N> is stored.

In the related art, when the reference voltage Vref is higher than the first line voltage P_out and the second line voltage N_out during the adjustment of the first and second codes Pcode<0:N> and Ncode<0:N>, the resistance value should increase. When the resistance value increases, the first code Pcode<0:N> increases, but the second code Ncode<0:N> decreases.

The first line voltage P_out and the second line voltage N_out may be considerably higher than the reference voltage Vref due to external and internal factors of the semiconductor memory apparatus. For example, when an external resistor is not connected to an external resistor connecting pin, a high impedance is generated.

When the first line voltage P_out and the second line voltage N_out are considerably higher than the reference voltage Vref, the first code Pcode<0:N> is continuously increased to reach a maximum value. As a result, the resistance value becomes infinity. Similarly, the second code Ncode<0:N> is continuously decreased to reach a minimum value. As a result, the resistance value becomes infinity.

The on-die termination circuit of the semiconductor memory apparatus according to the related art has a problem in that a code adjustment error occurs in which the first code Pcode<0:N> is adjusted to the maximum value and the second code Ncode<0:N> is adjusted to the minimum value, so that the resistance value becomes infinity, which makes it difficult to normally input and output data.

SUMMARY

An embodiment of the present invention may provide an on-die termination circuit of a semiconductor memory apparatus capable of preventing errors during the adjustment of codes.

Another embodiment of the invention may provide an on-die termination circuit of a semiconductor memory apparatus that may be capable of adjusting a code value to adapt to PVT (process, voltage, and temperature) variations.

According to an embodiment of the invention, an on-die termination circuit of a semiconductor memory apparatus includes: a comparator that may compare a voltage corresponding to a normal code with a reference voltage to output a comparison signal; and a code adjusting unit that may vary the normal code according to the comparison signal, output the varied normal code, and reset the normal code to a predetermined reset code or a variable fuse code.

DESCRIPTION OF EXEMPLARY EMBODIMENT

An on-die termination circuit of a semiconductor memory apparatus according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

As shown inFIG. 2, an exemplary on-die termination circuit of a semiconductor memory apparatus according to an embodiment of the invention may include an ODT input driver10, a first comparator20, a first control unit100, a first code adjusting unit200, an ODT output driver40, a second comparator50, a second control unit500, and a second code adjusting unit600.

The ODT input driver10may divide a power supply voltage VDDQ at a resistance ratio corresponding to a first code Pcode<0:N> and output a first line voltage P_out. The ODT input driver10may be modeled in the same manner as a data input driver.

As shown inFIG. 3, the exemplary ODT input driver10may include, for example, a plurality of transistors P0to Pn that may be coupled to a power supply terminal VDDQ and turned on in response to the first code Pcode<0:N> and a plurality of resistor NR0to NRn that may be coupled between the plurality of transistors P0to Pn and a ground terminal VSSQ, respectively.

The first comparator20may compare the first line voltage P_out with a reference voltage Vref in response to a first code adjustment enable signal P_en and output a first comparison signal Pcmp_out.

The first control unit100enables a reset signal RST that may serve as, for example, a code error determining signal when the first code Pcode<0:N> reaches a code value for which a resistance value may be the maximum (for example, when N is 4, 11111) with the first code adjustment enable signal P_en being disabled. As shown inFIG. 4, the first control unit100may include, for example, a first inverter IV1to which the first code adjustment enable signal P_en is input and a first XNOR gate XNOR1to which an output signal of the first inverter IV1and the first code Pcode<0:N> are input.

The ODT output driver40may divide the power supply voltage VDDQ at a resistance ratio, for example, that corresponds to a second code Ncode<0:N> and output a second line voltage N_out. The ODT output driver40may be modeled in the same manner as a data output driver.

As shown inFIG. 5, the ODT output driver40may include, for example, a plurality of transistors PM0to PMn that may be coupled to a power supply terminal VDDQ and are turned on in response to the first code Pcode<0:N>, a plurality of resistors RP0to RPn that may be coupled between the plurality of transistors PM0to PMn and the ground terminal VSSQ, respectively, a plurality of resistors RN0to RNn coupled to the plurality of resistors RP0to RPn, respectively, and a plurality of transistors NM0to NMn that may be coupled between the plurality of resistors RN0to RNn and the ground terminal VSSQ and are turned on in response to the second code Ncode<0:N>.

The second comparator50may compare the second line voltage N_out with the reference voltage Vref in response to a second code adjustment enable signal N_en and output a second comparison signal Ncmp_out.

The second control unit500may enable the reset signal RST that may serve as, for example, a code error determining signal when the second code Ncode<0:N>reaches a code value for which a resistance value may be the maximum (for example, when N is 4, 00000) with the second code adjustment enable signal N_en being disabled. As shown inFIG. 6, the second control unit500may include, for example, a second inverter IV2to which the second code adjustment enable signal N_en is input, a plurality of inverters IV3to IVn to which bits of the second code Ncode<0:N> are input, and a second XNOR gate XNOR2to which output signals of the inverters IV2to IVn are input.

As shown inFIG. 7, the exemplary first code adjusting unit200may include, for example, a fuse set300and a first register400. The first code adjusting unit200may count up or down the first code Pcode<0:N> in response to the first comparison signal Pcmp_out output from the first comparator20and store the first code Pcode<0:N>. When the first control unit100generates a reset signal RST, the first code adjusting unit200may reset the first code Pcode<0:N>, for example, to a predetermined reset code or a first fuse code FPcode<0:N>in response to a first fuse code enable signal FPen.

The exemplary first fuse set300may include as a code setting unit, for example, a first fuse circuit310for generating the first fuse code enable signal FPen and a plurality of second fuse circuits320for generating the first fuse code FPcode<0:N>. In the first fuse circuit310and the second fuse circuits320, a fuse F and a transistor M may be coupled between a power supply terminal Vdd and a ground terminal, and a latch LT may be coupled to a node between the fuse F and the transistor M.

The first register400may include, for example, a plurality of counters410and a selection signal generating unit420.

The plurality of counters410may receive the first fuse code FPcode<0:N>, the first code adjustment enable signal P_en, a first selection signal resetN, a second selection signal resetF, a carry Cin, and the first comparison signal Pcmp_out and output the first code Pcode<0:N> and a carry Cout.

The exemplary selection signal generating unit420may receive the reset signal RST and the first fuse code enable signal FPen and generate the first selection signal resetN and the second selection signal resetF. The first selection signal resetN may be used to reset the first code Pcode<0:N> to the reset code. The second selection signal resetF may be used to reset the first code Pcode<0:N> to the first fuse code FPcode<0:N>.

A first selection signal generating unit421may include, for example, a first inverter IV21to which a first fuse code enable signal FPen is input, a first NAND gate ND21to which an output signal of the first inverter IV21and the reset signal RST are input, and a second inverter IV22that receives an output signal of the first NAND gate ND21and outputs the first selection signal resetN.

A second selection signal generating unit422may include, for example, a second NAND gate ND22to which the reset signal RST and the first fuse code enable signal FPen are input and a third inverter IV23that receives an output signal of the second NAND gate ND22and outputs the second selection signal resetF.

As shown inFIG. 8, the exemplary counter410may include a flip-flop411, a carry output unit412, a switching unit413, and a normal code control clock generating unit414.

The flip-flop411may store and output an input signal Din in response to a normal code control clock CLKD/CLKZ. The flip-flop411may output a first fuse code FPcode<0> or the reset code according to the first selection signal resetN and the second selection signal resetF.

As shown inFIG. 9, the exemplary flip-flop411may include a fuse code control clock generating unit411-1, a fuse code processing unit411-2, a normal code processing unit411-3, and a reset code processing unit411-4.

The exemplary fuse code control clock generating unit411-1may include, for example, a plurality of inverters IV43and IV44. In the disclosed fuse code control clock generating unit411-1, the inverter IV43inverts the second selection signal resetF to generate a fuse code control clock resetFz, and the inverter IV44inverts the fuse code control clock resetFz to generate a fuse code control clock resetFd.

The exemplary fuse code processing unit411-2may include, for example, a pass gate PG41having control terminals to which the fuse code control clocks resetFz and resetFd are input and an input terminal to which the first fuse code FPcode<0> is input, and an inverter IV41to which an output signal of the pass gate PG41is input. The fuse code processing unit411-2may output the first fuse code FPcode<0> in response to the fuse code control clocks resetFz and resetFd that may be generated on the basis of the second selection signal resetF.

The exemplary normal code processing unit411-3may include, for example, a first pass gate PG42having control terminals to which the normal code control clocks CLKZ and CLKD are input and an input terminal to which an input signal Din is input as a normal code, a first latch LT41to which an output signal of the first pass gate PG42is input, and a second pass gate PG43having control terminals to which the normal code control clocks CLKD and CLKZ having opposite phases are input and an input terminal to which an output signal of the first latch LT41is input. The normal code processing unit411-3may further include a second latch LT42for synchronizing the phase and maintaining an output level. The normal code processing unit411-3may store a normal code as the input signal Din during first half of one period of each of the normal code control clocks CLKD and CLKZ, and output the normal code during the other half of one period of each of the normal code control clocks CLKD and CLKZ.

The exemplary reset code processing unit411-4may include, for example, an inverter IV42to which the first selection signal resetN is input, a first transistor M41that outputs a power supply voltage level Vdd according to the output of the inverter IV42, a first switch SW41coupled between the first transistor M41and the second latch LT42, a second transistor M42that outputs a ground level in response to the first selection signal resetN, a second switch SW42coupled between the second transistor M42and the second latch LT42, a third switch SW43coupled to a node between the first transistor M41and the first switch SW41, and a fourth switch SW44coupled between the third switch SW43and the second transistor M42. In the reset code processing unit411-4, when the first selection signal resetN is generated, the transistors M41and M42are turned on and a predetermined reset code is output by a plurality of switches SW41to SW44.

Referring toFIG. 8, the carry output unit412may include, for example, a NOR gate NR31that receives an input carry Cin and an output signal Dout of the flip-flop411or an inverted signal of the output signal Dout of the flip-flop411and generates an output carry Cout.

The exemplary switching unit413may include, for example, a plurality of inverters IV31to IV33and a plurality of pass gates PG31to PG34. In the switching unit413, the inverters IV31and IV33and the pass gates PG31and PG32allow the output signal Dout of the flip-flop411to have the original phase or an inverted phase according to the input carry Cin, and the switching unit413feeds back the output signal Dout to the flip-flop411as the input signal Din. The disclosed switching unit413may use the inverters IV32and IV33and the pass gates PG33and PG34to allow the output signal Dout of the flip-flop411to have the original phase or an inverted phase according to a first comparison signal Pcmp_out, and output the output signal Dout to the carry output unit412.

The exemplary normal code control clock generating unit414may include, for example, a plurality of inverters IV35and IV36. In the disclosed normal code control clock generating unit414, the inverter IV35inverts a first code adjustment enable signal P_en to generate the normal code control clock CLKZ, and the inverter IV36inverts the normal code control clock CLKZ to generate the normal code control clock CLKD.

Referring back toFIG. 2, the exemplary second code adjusting unit600may include a second fuse set700and a second register800. The second code adjusting unit600may count up or down the second code Ncode<0:N> according to a second comparison signal Ncmp_out output from the second comparator50and stores the second code Ncode<0:N>. When the second control unit500generates the reset signal RST, the second code adjusting unit600may reset the second code Ncode<0:N> to a predetermined reset code or the second fuse code FNcode<0:N> according to a second fuse code enable signal Fnen. The circuit configuration of the second fuse set700may be the same as that of the first fuse set300, and the circuit configuration of the second register800may be the same as that of the first register400.

Next, an example of the operation of the on-die termination circuit of the semiconductor memory apparatus according to an embodiment of the invention will be described below.

A technique for determining whether a normal code adjusting error occurs and resetting the normal code, a technique for selecting a code value for reset from a predetermined reset code or a separate fuse code, and a technique for performing a test to adjusting an error in the fuse code value due to a PVT (process, voltage, and temperature) variation are disclosed.

First, an exemplary a method of performing a test to adjusting a fuse code will be described.

A difference between a resistance value of a driver and the actual resistance value is measured when reset codes are input to an input driver and an output driver of a semiconductor memory apparatus. The reset codes are output from the first register400and the second register800shown inFIG. 2by turning on or off the plurality of switches SW41to SW44shown inFIG. 9.

Based on the measured result, when the difference between the resistance values is beyond an error range, fuses F of a plurality of second fuse circuits320in the first fuse set300or the second fuse set700are cut such that the difference between the resistance values falls within the error range. Then, the fuse F of the first fuse circuit310is cut to generate the first and second fuse code enable signals FPen and FNen. When the circuit is initialized with the fuse F of the first fuse circuit310cut and a power-up signal power-up may be generated, the first or second fuse code enable signal FPen or FNen is activated at a high level.

Based on the measured result, when there is no difference between the resistance values or when the difference between the resistance values falls within the error range, all of the fuses F of the first and second fuse circuits310and320in the first or second fuse set300or700are not cut. Even when the circuit is initialized without cutting the fuse F of the first fuse circuit310and the power-up signal power-up is generated, the first or second fuse code enable signal FPen or FNen is inactivated at a low level.

Next, a example of a process of adjusting and resetting the first code Pcode<0:N> and the second code Ncode<0:N> after the fuse code adjustment is completed will be described below.

An exemplary process of adjusting the first code Pcode<0:N> and a process of adjusting the second code Ncode<0:N> may be performed simultaneously or performed sequentially.

An exemplary process of adjusting the first code Pcode<0:N> is as follows.

The first code Pcode<0:N> set by the first register400is input to the ODT input driver10.

The ODT input driver10divides the power supply voltage VDDQ at a resistance ratio of the resistor connected according to the first code Pcode<0:N> and a line impedance detecting resistor ZQ and outputs a first line voltage P_out.

The first comparator20compares the first line voltage P_out and the reference voltage Vref according to the first code adjustment enable signal P_en and outputs the first comparison signal Pcmp_out.

The first register400counts the first code Pcode<0:N> according to the first comparison signal Pcmp_out

As shown inFIG. 7, when the reset signal RST is not activated, neither the first selection signal resetN nor the second selection signal resetF is activated. When neither the first selection signal resetN nor the second selection signal resetF is activated, the first register400counts the first code Pcode<0:N> regardless of the first fuse code FPcode<0:N> and the reset code.

The ODT input driver10feeds back the first line voltage P_out corresponding to the counted first code Pcode<0:N> to the first comparator20. The first comparator20receives the first line voltage P_out and repeatedly performs the comparing operation and an operation for outputting the first comparison signal Pcmp_out.

The first code adjustment enable signal P_en is inactivated after a predetermined time.

When the first code adjustment enable signal P_en is inactivated, the first comparator20stops, and the first code Pcode<0:N> at that time is stored.

As shown inFIG. 10, even when the first code Pcode<0:N> is continuously counted during a period for which the first code adjustment enable signal P_en is enabled, mismatching may occur between the first line voltage P_out and the reference voltage Vref. When the first comparison signal Pcmp_out is maintained at a high level, the first code Pcode<0:N> reaches a code value, for example, (11111) for which the resistance value of the input driver may be the maximum, and does not vary any longer, so that the first code adjustment enable signal P_en is disabled.

The first control unit100shown inFIG. 2receives the first code Pcode<0:N> having reached the code value, for example, (11111) and the first code adjustment enable signal P_en that has been inactivated at a low level and activates the reset signal RST at a high level.

When the first fuse code enable signal FPen is inactivated at a low level with the reset signal RST being activated at a high level, the selection signal generating unit420of the first register400shown inFIG. 7activates the first selection signal resetN at a high level and inactivates the second selection signal resetF at a low level.

When the first selection signal resetN is activated at a high level, the flip-flop411of the first register400shown inFIG. 9outputs a predetermined reset code to reset the first code Pcode<0> to the reset code. When the first selection signal resetN changes to the high level, the inverter IV42turns on the transistor M41and the switch SW44is turned on, so that a reset code having a logical value of ‘0’ is output from the latch LT42. Since the second selection signal resetF is at a low level, the pass gate PG41is turned off, and the first fuse code FPcode<0> is interrupted. Since the first code adjustment enable signal P_en is in an inactive state, the pass gate PG42is turned off according to the output of the normal code control clock generating unit414shown inFIG. 8, and the input signal Din is also interrupted. The remaining first codes Pcode<1:N> are reset to the reset code.

Meanwhile, when the first fuse code enable signal FPen is activated at a high level with the reset signal RST being activated at a high level, the selection signal generating unit420of the first register400shown inFIG. 7activates the second selection signal resetF at a high level and inactivates the first selection signal resetN at a low level.

When the second selection signal resetF is activated at a high level, the flip-flop411of the first register400shown inFIG. 9outputs the first fuse code FPcode<0> to reset the first code Pcode<0> to the first fuse code FPcode<0>. When the second selection signal resetF is activated at a high level, the fuse code control clock generating unit411-1generates fuse code control clocks resetFz and resetFd. Then, the first fuse code FPcode<0> is output through the pass gate PG41, the inverter IV41, and the latch LT42. Since the first selection signal resetN is at a low level, the inverter IV42turns off the transistor M41. Since the first code adjustment enable signal P_en is in an inactive state, the pass gate PG42is turned off according to the output of the normal code control clock generating unit414shown inFIG. 8, and the input signal Din is interrupted. The remaining first codes Pcode<1:N> are reset to the first fuse codes FPcode<1:N>.

An operation for adjusting the second code Ncode<0:N> may be performed in the same manner as that in which the operation for adjusting the first code Pcode<0:N> is performed, and an example of the operation for adjusting the second code Ncode<0:N> will be described below.

The ODT output driver40feeds back the second line voltage N_out corresponding to the counted second code Ncode<0:N> to the second comparator50. The second comparator50receives the second line voltage N_out and repeatedly performs the comparing operation and an operation for outputting the second comparison signal Ncmp_out.

As shown inFIG. 11, even when the second code Ncode<0:N> is continuously counted during a period for which the second code adjustment enable signal N_en is enabled, mismatching may occur between the second line voltage N_out and the reference voltage Vref. When the second comparison signal Ncmp_out is maintained at a low level, the second code Ncode<0:N> reaches a code value, for example, (00000) for which the resistance value of the input driver may be the maximum, and does not vary any longer, so that the second code adjustment enable signal N_en is disabled.

The second control unit500shown inFIG. 2receives the second code Ncode<0:N> having reached the code value, for example, (00000) and the second code adjustment enable signal N_en that has been inactivated at a low level and activates the reset signal RST at a high level.

When the second fuse code enable signal FNen is inactivated at a low level with the reset signal RST being activated at a high level, the second register800shown inFIG. 2resets the second code Ncode<0:N> to the reset code.

When the second fuse code enable signal FNen is activated at a high level with the reset signal RST being activated at a high level, the second register800shown inFIG. 2resets the second code Ncode<0:N> to the second fuse code FNcode<0:N> output from the second fuse set700.

It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above embodiments are not limitative, but illustrative in all aspects. The scope of the present invention is defined by the appended claims rather than by the description preceding them, and therefore all changes and modifications that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.

As described above, according to the above-mentioned embodiments of the invention, the on-die termination circuit of the semiconductor memory apparatus can prevent a code adjustment error, and variably set a code value used to prevent the code adjustment error to adapt to PVT (process, voltage, and temperature) variation. Therefore, it is possible to normally input and output data even when the PVT variation occurs, and thus further improve the performance of a semiconductor memory apparatus.