Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same

An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and particularly to an embedded bit line structure, a field effect transistor (FET) structure with the same and a method of fabricating the same.

2. Description of the Prior Art

A vertical Fin-shaped gate field effect transistor (FinFET) with an embedded (or buried) bit line is the mainstream to achieve next generation 4F2(feature) cell because of simplified middle-of-line (MOL) process. However, front-end-of-line (FEOL) process becomes more complicated accordingly. Especially, shallow trench isolation (STI) with half feature size is required. As a result, an aspect ratio of STI larger than 20 happens for thirties nm generation, and difficulty for gap fill with oxide film could be an obstacle to dynamic random access memory (DRAM) shrinkage.

Vertical surrounding gate transistors (SGT) with embedded bit lines have been proposed with enlarging isolation rule (close to 1F (feature)) to greatly reduce STI manufacturing difficulty. However, Vth(threshold voltage) stability for the memory cell array becomes much worse because of complicated fabricating process, including, for example, tedious embedded bit line formation steps, recess for spin-on-dielectric (SOD) formation steps, metal and n+ type poly defined transistor gate length. Reducing Vthvariation with longer channel length is also unfeasible under vertical dimension constraint.

Therefore, there is still a need for a novel FinFET structure and the fabrication process therefore to avoid the aforesaid problems.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide an embedded bit line structure, an FET structure with the same and a method of fabricating the same, in which aspect ratio of STI can be relatively reduced and Vthcan be stable.

According to one embodiment of the present invention, an embedded bit line structure is provided, which includes a substrate including an active area, a trench surrounding the active area, and a bit line. The substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer. A bit line is disposed within the lower portion of the trench along one side of the active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

According to another embodiment of the present invention, an FET structure with an embedded bit line, which includes a substrate including an active area, a trench, a bit line, and a word line. The FET structure includes a bit line structure similar to the aforesaid one. Additionally, an FET element is formed with the semiconductor layer of the active area. The bit line is disposed to electrically connect the FET. The word line is disposed within the substrate along another side of the active area, crosses over the bit line, and electrically connecting the FET.

According to further another embodiment of the present invention, a method of fabricating an embedded bit line structure is provided, which includes steps as follows. A substrate including an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer is provided. An active area on the substrate is provided. A trench surrounding the active area and down through the semiconductor layer and into the insulator layer is formed, A first portion of a bit line is formed within the trench at one side of the active area, wherein the first portion of the bit line is below the original top surface of the insulator layer. An insulator liner is formed on a sidewall of the trench opposite the active area above the first portion of the bit line for isolating the bit line from the semiconductor layer of the substrate. A second portion of the bit line is formed on the first portion of the bit line within the trench to electrically connect the bit line to the semiconductor layer of the active area. The trench is filled with insulator material to form an STI.

DETAILED DESCRIPTION

An FET structure with an embedded bit line is provided in the present invention. The FET structure includes an embedded bit line structure according to the present invention, and both are described in detail, referring toFIGS. 1-4showing an embodiment according to the present invention. A substrate10comprises an insulator layer14, such as an oxide layer, and a semiconductor layer16, such as a silicon layer, on the original top surface15of the insulator layer14. Optionally, a silicon substrate12may be further beneath the insulator layer14for supporting the whole structure. For example, the substrate may be a silicon-on-insulator (SOI) one. At least an active area is defined on the substrate10. A trench11is disposed to surround the active area (AA). A bit line22is disposed within the trench11along one side of the active area. The bit line22comprises a first portion18and a second portion20. The first portion18is embedded within the insulator layer14and below the original top surface15of the insulator layer14. The second portion20is disposed on the first portion18to electrically connect the semiconductor layer16of the active area. As shown inFIG. 3, an insulator liner28is disposed on the first portion18of the bit line22and between the second portion20of the bit line22and the semiconductor layer16of the substrate10opposite the active area for isolation. The insulator liner28and interlayer dielectric are not shown in some of the drawings, such asFIGS. 1 and 2, for clearly showing other elements. An STI24is disposed within the trench to surround the active area to insulate the active area from other part of the semiconductor layer of the substrate. Accordingly, the STI24may fill up the trench. The STI24may be downward through the semiconductor layer16, partially go into the insulator layer14, and partially stay on the bit line22. As a result, the bit line22is embedded and insulated except the second portion20which electrically connect the active area. The first and second portions18and20may include conductive material, such as metal and polysilicon, respectively. It is preferred that the first portion18includes metal, and the second portion20includes polysilicon. The first portion18may be in a line shape, and the second portion20may be in a line shape or just a block shape for connecting the first portion18to the active area.

A word line26is disposed within the substrate10, along another side of the active area, crossing over the bit line22, and electrically connecting the gate (not shown) of FET.

As shown inFIG. 1, the FET may comprise a pair of source/drain structures (S/D)16a,16bwhich may be disposed within the upper portion and the lower portion of the semiconductor layer of the active area respectively and a gate structure disposed between the source and the drain structures, as a vertical transistor.

According to further another embodiment of the present invention, a method of fabricating an embedded bit line structure is provided. One embodiment of the method is illustrated by a flow chart ofFIG. 5and schematic cross-sectional views ofFIGS. 6-8. In the step101, a substrate is provided. The substrate may include a silicon substrate12, an insulator layer14, and a semiconductor layer16aforesaid. In the step103, an active area (AA) is defined on the substrate. In the step105, a trench is formed to surround the active area and down through the semiconductor layer16and into the insulator layer14of the substrate. This may be accomplished by carrying out a microlithography process and an etching process using a patterned hard mask. Thereafter, in the step107, a first portion18of a bit line is formed within the trench at one side of the active area. The first portion18of the bit line is formed to obtain a height at a position below the original top surface15of the insulator layer14. In other word, the original top surface15of the insulator layer14is higher than the top surface of the first portion18. When the first portion18includes metal, it may be formed by for example chemical vapor deposition to deposit a metal layer on the lower portion of the trench. A back etching may be required to control the height of the resulting metal layer.

Thereafter, in the step109, an insulator liner28is formed on a sidewall of the trench11opposite the active area above the first portion18of the bit line for isolating the bit line from the semiconductor layer16of the substrate. The formation of the insulator liner28may be carried out by forming an insulator liner on all of the sidewalls of the trench using for example a deposition process, followed by stripping off the insulator liner on the sidewall of the active area above the first portion18of the bit line using for example an etching process in which the desired portion is protected by a mask. In the step111, a second portion20of the bit line is formed on the first portion18of the bit line within the trench11to electrically connect the bit line22to the semiconductor layer16of the active area. The second portion20may include polysilicon and may be formed by a chemical vapor deposition process. In the step113, the trench is filled with insulator material, such as oxide material, by for example a chemical vapor deposition or spin-on-dielectric process to form an STI24.

Also referring toFIGS. 1 and 8, a word line26may be further formed within the substrate along another side of the active area to cross over the bit line22and electrically connect the active area. The FET is formed at the active area. In an embodiment, the word line26may be formed within the substrate along another side of the active area to cross over the bit line22and connect the active area at a middle portion of the semiconductor layer16of the active area along a vertical direction, and implanting dopants, such as n-type dopants, into a lower portion and an upper portion of the semiconductor layer16of the active region at two sides of the middle portion to form a pair of source/drain regions16a,16b.

A conventional fin gate structure can be suitably formed based on the bit line structure of the present invention. The gate structure may comprise a fin gate structure, such as a double gate FinFET structure. Another word line may be further disposed, such that two word lines electrically connect two opposite sides of the fin gate structure respectively. Alternatively, referring toFIG. 9, the fin gate structure may be further a surrounding gate structure, and the word line30may be formed within the substrate to surround the surrounding gate and cross over the bit line22.

The thickness of the semiconductor layer, such as silicon film, of the substrate depends on the resulting device desired and decided by vertical transistor geometric sizes including sizes of junction out-diffusion, channel length, STI format capability, and the like. As the semiconductor layer is disposed on the insulator layer, the bit line having a structure according to the present invention can be well insulated within the insulator layer and the STI, the thickness of the semiconductor layer can be significantly reduced as compared with conventional one.

Since the lower portion of the embedded bit line is formed within an insulator layer, parasitic capacitance is reduced. Since the FET is constructed on an insulator layer, the STI can be relatively shallow; and thus the fabrication is relatively easy. With easy STI fill process with embedded bit lines, longer channel is possible even for feature size of 40 nm or less, resulting in a stable array Vth. Furthermore, with embedded metal bit line structure, no metal contamination is risked.