Biquad infinite impulse response system transformation

A BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected in series for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR system as a function of an addition of at least first and second signals and a subtraction of at least a third signal. The third signal includes a first delayed output sample generated by the second delay line multiplied by a first prescribed value. The first delayed output sample and the output data sample are temporally nonadjacent to one another.

FIELD OF THE INVENTION

The present invention relates generally to the electrical, electronic, and computer arts, and more particularly relates to infinite impulse response systems.

BACKGROUND

Infinite impulse response (IIR) digital filters, and in particular, biquad infinite impulse response (BIIR) filters, have been widely used in the field of communications, among other applications. For example, such digital filters are often used to remove noise, enhance communication signals, and/or synthesize communication signals. Compared to a finite impulse response (FIR) filter, an IIR filter is generally much more efficient in terms of achieving certain performance characteristics with a given filter order. This is primarily because an IIR filter incorporates feedback and is capable of realizing both poles and zeros of a system transfer function, whereas an FIR filter can only realize zeros of a transfer function. Moreover, IIR filters use a smaller number of coefficients to obtain a required impulse response of a desired filter.

Higher order IIR filters can be obtained by cascading multiple biquad IIR filters with appropriate coefficients. Another way to design higher-order IIR filters is to employ a single complex section. This latter approach is often referred to as a direct form implementation. The cascaded biquad implementation generally executes slower than the direct form implementation but generates smaller numerical errors than the direct form implementation. Another disadvantage of the direct form implementation is that the poles of such single-stage high-order polynomials get increasingly sensitive to quantization errors; second-order polynomial sections (i.e., biquads) are less sensitive to quantization effects.

One significant disadvantage of a BIIR implementation in a vector processor environment is a requirement for sequential processing of output samples. Conventional direct form implementation BIIR filter implementations utilize only a relatively small subset (e.g., three) of the total number of multipliers available. This implementation is inefficient, and is prone to execution stalls, and hence is undesirable.

SUMMARY

Principles of the invention, in illustrative embodiments thereof, advantageously provide techniques for eliminating the requirement for sequential processing of output samples in a BIIR system. In this manner, techniques of the invention advantageously optimize the processing efficiency and performance of a BIIR system, such as a BIIR filter, particularly in a vector processor environment.

In accordance with one embodiment of the invention, a BIIR system includes a first delay line for receiving at least one input data sample and generating delayed input samples as a function of the input data sample. The BIIR system further includes a second delay line including multiple delay elements connected together in a series configuration for generating delayed output samples. An input of one of the delay elements receives at least one output data sample of the BIIR system. A summation element in the BIIR system generates the output data sample of the BIIR system as a function of an addition of at least first and second signals and a subtraction of at least a third signal. The third signal includes at least a first delayed output sample generated by the second delay line multiplied by a first prescribed value. The first delayed output sample and the output data sample of the BIIR system are temporally nonadjacent to one another, whereby the BIIR system eliminates a dependency between the output data sample and a temporally adjacent delayed output sample generated by the second delay line. One or more BIIR systems can be implemented in an integrated circuit.

In accordance with another embodiment of the invention, a method of implementing a BIIR system includes the steps of: generating a plurality of delayed input samples as a function of an input data sample received by the BIIR system; generating a plurality of delayed output samples as a function of at least one output data sample of the BIIR system; generating the output data sample of the BIIR system by summing at least a first signal and a second signal and subtracting at least a third signal, the third signal comprising at least a first one of the delayed output samples multiplied by a first prescribed value, the first one of the delayed output samples and the output data sample of the BIIR system being temporally nonadjacent to one another, whereby the BIIR system is operative to eliminate a dependency between the output data sample and a temporally adjacent delayed output sample.

These and other features, objects and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION

Embodiments of the present invention will be described herein in the context of illustrative methods and apparatus for efficiently implementing a BIIR filter. It is to be appreciated, however, that the invention is not limited to the specific methods and apparatus illustratively shown and described herein. Rather, embodiments of the invention are directed broadly to techniques for eliminating the sequential processing of output samples in a BIIR system. Moreover, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the present invention. That is, no limitations with respect to the specific embodiments described herein are intended or should be inferred.

A BIIR transfer function is typically represented in one of the following forms:

IIR is a property of signal processing systems. Systems with this property are known as IIR systems or, when dealing with filter systems in particular, as IIR filters. IIR systems have an impulse response function that is non-zero over an infinite length of time. This is in contrast to finite impulse response (FIR) filters, which have fixed-duration impulse responses.

FIG. 1is a block diagram depicting at least a portion of an exemplary second order IIR filter100which can be modified to implement techniques of the invention. It is to be understood that the invention is not limited to any specific IIR filter topology, and that the coefficients and number of feedback/feedforward paths in the filter are implementation-dependent. In this example, IIR filter100includes a summation block102, a first delay block104and a second delay block106connected together in a recursive configuration. Summation block102is operative to receive an input signal (x) supplied thereto and to generate an output signal (y) of the filter via a feedforward signal path. Delayed versions of the output signal y, generated by delay blocks104and106, are fed back to summation block102, via separate feedback signal paths, and summed with the input signal x to generate the filter output signal y.

More particularly, input signal x is multiplied in block108by a coefficient (i.e., constant) b to generate the signal bx supplied to summation block102. The output signal y is fed to the first delay block104to generate a delayed output signal yz−1, which is multiplied by a coefficient a1to generate a signal a1yz−1. The signal a1yz−1is then supplied to summation block102via a first feedback signal path. Concurrently, the signal yz−1generated by the first delay block104is fed to the second delay block106to generate a delayed output signal yz−2, which is multiplied by a coefficient a0to generate a signal a0yz−2. The signal a0yz−2is then supplied to summation block102via a second feedback signal path. In this manner, the output signal y can be represented as follows:
y=bx+a0yz−1+a1yz−2(3)
Solving equation (3) for the filter transfer function H(z) yields the following derivation:

FIG. 2is a graphical illustration depicting pole locations for an exemplary BIIR filter. With reference toFIG. 2, a first pole202is located at a position of Rbon the real axis and Ibon the imaginary axis, and a second pole204is located at a position of Rbon the real axis and −Ibon the imaginary axis. As shown, the location of all poles lie within the boundary of a unit circle206, which is a fundamental requirement of any IIR filter since it assures filter stability. More particularly, the system transfer function allows one to judge whether or not the system is bounded-input, bounded-output (BIBO) stable. A BIBO stability criterion requires that a radius of convergence (ROC) of the system includes the unit circle. For example, for a causal system, all poles of the transfer function must have an absolute value smaller than one; i.e., all poles must be located within the boundary of the unit circle206in a z-plane.

As will be understood by those skilled in the art, the poles are defined as values of z which make the denominator of the transfer function H(z) equal to 0; in other words:
0=Σj=0Qajz−j,
where Q represents the IIR feedback filter order. Clearly, if ajis not equal to zero, then the poles are not located at the origin of the z-plane. This is in contrast to the FIR filter where all poles are located at the origin, and thus the ZFIR filter is always stable.

As previously stated, a significant disadvantage of a conventional BIIR filter implementation in a vector processor environment is a requirement for sequential processing of output samples. Conventional BIIR filter implementations utilize only a small subset (e.g., three) of the total number of multipliers available (e.g., 16). This implementation is inefficient, is prone to execution stalls, and is therefore undesirable.

As seen in equation (2) above, there is a direct correlation between the calculation of previous sample y[n−1] and output sample y[n]. Assume the BIIR filter is implemented in hardware (e.g., a vector processor) that is operative to execute several multiply accumulate (MAC) operations in a single cycle (e.g., 16 multipliers in the case of LSI vector processor VP16, or 32 multipliers in the case of CEVA-XC323, commercially available from CEVA, Inc., Mountain View, Calif.). Execution problems associated with this approach are illustrated in conjunction withFIG. 3.

By way of example only and without loss of generality,FIG. 3is a conceptual view depicting three consecutive processor cycles, namely, cycles T, T+1 and T+2, along with exemplary operations performed during each of the cycles in a direct implementation of the illustrative BIIR filter. The duration of each cycle in absolute time is not critical to the invention and is therefore not explicitly shown. With reference toFIG. 3, in cycle T, the following illustrative calculations are performed:
y[n−1]=a1*y[n−2]+Temp1[n−1]+Temp2[n−1];
Temp1[n]=−a2*y[n−2];
Temp2[n]=A*x[n].
In cycle T+1, the following illustrative calculations are performed:
y[n]=−a1*y[n−1]+Temp1[n]+Temp2[n];
Temp1[n+1]=−a2*y[n−1];
Temp2[n+1]=A*x[n+1].
Likewise, in cycle T+2, the following illustrative calculations are performed:
y[n+1]=−a1*y[n]+Temp1[n+1]+Temp2[n+1];
Temp1[n+2]=−a2*y[n];
Temp2[n+2]=A*x[n+2].

As seen from the above operations, direct implementation of a standard BIIR utilizes only three multipliers out of all available multipliers during any given processor cycle. Most modern vector processors include a substantially greater number of available multipliers (e.g., 16, in the illustrative case of a VP16 vector processor), and thus a standard BIIR implementation utilizing only three multipliers in a given cycle results in an inefficient approach, at least in terms of resource allocation. In addition, this direct implementation of the BIIR filter can cause execution stalls in every cycle if MAC (i.e., multiply accumulate) operations are performed in more than one pipe stage, which is a practical scenario. Thus, for efficiency purposes, it would be desirable to implement the BIIR filter (or alternative BIIR system) in a manner which beneficially utilizes all, or at least a larger subset, of the available multipliers in a given vector processor system.

In order to achieve greater processing efficiency and speed, among other advantages, embodiments of the invention provide an implementation of the BIIR filter that beneficially eliminates the above-noted dependency between y[n] and y[n−1] samples. Additionally, the novel transformation methodology preserves the stability and accuracy of the BIIR filter. While embodiments of the invention are described herein with specific reference BIIR filters, it will become apparent to those skilled in the art given the teachings herein that techniques of the invention are applicable to IIR systems in general. Additional systems that can be modified according to embodiments of the invention include, but are not limited to, generally any auto-regressive moving-average (ARMA) system. A BIIR filter represents merely one simple illustration which achieves significant benefits over conventional approaches.

As previously stated, a standard BIIR filter can be represented by at least one of the following expressions:

In accordance with an embodiment of the invention, both the numerator and denominator of the transfer function H(z) shown in equation (2) are multiplied by (1+b1z−1)*(1+b2z−1) in the following manner:

H⁡(z)=A+p1⁢z-1+p2⁢z-21+q1⁢z-2+q2⁢z-4(6)
Equation (6) above can be rewritten in regression equation form as follows:
y[n]=−q1y[n−2]−q2y[n−4]+Ax[n]+p1x[n−1]+p2x[n−2]  (7)

In a z-transform plane, the illustrative transformed BIIR filter represented by equation (7) comprises four poles and two zeros. To ensure that the transformed BIIR filter is stable, all poles must reside within the boundary of a unit circle, as previously stated.FIG. 4is a graphical illustration depicting pole and zero locations for the exemplary transformed BIIR filter, according to an embodiment of the invention. The transformed BIIR filter is represented in the z-plane as having four poles, namely, a first pole402, a second pole404, a third pole406and a fourth pole408, and two zeros, namely, a first zero410and a second zero412. As apparent fromFIG. 4, all poles402,404,406and408of the transformed BIIR filter have an absolute value smaller than one; i.e., all poles are located within the boundary of a unit circle414in the z-plane, thus satisfying the BIBO stability criterion.

As is seen in equation (7) above, there is no direct dependency between the calculation of samples y[n−1] and y[n]. A dependency exists only between the calculation of samples y[n−2] and y[n]. This approach provides enhanced calculation efficiency for a BIIR system compared to conventional methodologies.

By way of example only and without loss of generality,FIG. 5is a conceptual view depicting two consecutive processor cycles, namely, cycles T and T+1, along with exemplary operations performed during each of the cycles in an implementation of an illustrative transformed BIIR filter, according to an embodiment of the invention. The duration of each cycle in absolute time is not critical to the invention and is therefore not explicitly shown. With reference toFIG. 5, in cycle T, the following illustrative calculations are performed:
y[n−2]=−q1*y[n−4]+Temp1[n−2]+Temp2[n−2]+Temp3[n−2]+Temp4[n−2];
y[n−1]=−q1*y[n−3]+Temp1[n−1]+Temp2[n−1]+Temp3[n−1]+Temp4[n−1];
Temp1[n]=−q2*y[n−4];
Temp2[n]=A*x[n];
Temp3[n]=p1*x[n−1];
Temp4[n]=p2*x[n−2];
Temp1[n+1]=−q2*y[n−3];
Temp2[n+1]=A*x[n+1];
Temp3[n+1]=p1*x[n];
Temp4[n+1]=p2*x[n−1].
In cycle T+1, the following illustrative calculations are performed:
y[n]=−q1*y[n−2]+Temp1[n]+Temp2[n]+Temp3[n]+Temp4[n];
y[n+1]=−q1*y[n−1]+Temp1[n+1]+Temp2[n+1]+Temp3[n+1]+Temp4[n+1];
Temp1[n+2]=−q2*y[n−2];
Temp2[n+2]=A*x[n+2];
Temp3[n+2]=p1*x[n+1];
Temp4[n+2]=p2*x[n];
Temp1[n+3]=−q2*y[n−1];
Temp2[n+3]=A*x[n+3];
Temp3[n+3]=p1*x[n+2];
Temp4[n+3]=p2*x[n+1].

As seen from the above operations, implementation of the transformed BIIR filter utilizes ten multipliers during each processor cycle (one multiplier corresponding to each multiplication operation in a given processor cycle). The transformed BIIR approach thus advantageously improves calculation efficiency of the BIIR filter by about two times compared to a direct implementation of the BIIR filter shown inFIG. 3.

FIG. 6is a block diagram depicting at least a portion of an exemplary BIIR filter600, according to an embodiment of the present invention. BIIR filter600is a functional implementation of the transformed BIIR filter represented by equation (7) above. More particularly, input sample x[n] is multiplied in block602, which may be a scaling (e.g., attenuation or amplification) block, by a coefficient (i.e., constant) A to generate the signal Ax[n] supplied to a first summation block604. Concurrently, the input sample x[n] is fed to a first delay line606, which may be an input delay line, which includes first and second delay blocks608and610, respectively, connected together in series. The first delay block608, which has a delay D1associated therewith, is operative to generate a delayed input sample x[n−1] which is multiplied in block612by a coefficient p1to generate the signal p1x[n−1] supplied to a second summation block614. The second delay block610, which has a delay D2associated therewith, is operative to generate a delayed input sample x[n−2] which is multiplied in block616by a coefficient p2to generate the signal p2x[n−2] supplied to the second summation block614. It is to be appreciated that the respective delays D1and D2associated with delay blocks608and610, respectively, may be the same or different relative to one another, and the invention is not limited to any specific value of each delay. An output, p1x[n−1]+p2x[n−2], generated by summation block614is fed to summation block604where it is added to the signal Ax[n].

The output sample y[n] generated by summation block604is fed to a second delay line618, which maybe an output delay line. Delay line618includes a third delay block620having a delay D3associated therewith, a fourth delay block622having a delay D4associated therewith, a fifth delay block624having a delay D5associated therewith, and a sixth delay block626having a delay D6associated therewith. Delay block620is operative to generate a first delayed output sample y[n−1], delay block622is operative to generate a second delayed output sample y[n−2], delay block624is operative to generate a third delayed output sample y[n−3], and delay block626is operative to generate a fourth delayed output sample y[n−4].

The output sample y[n−2] generated by delay block622is multiplied in block628by a coefficient q1to generate a signal q1y[n−2] which is then supplied to a third summation block630via a first feedback signal path. Concurrently, the output sample y[n−4] generated by delay block626is multiplied in block632by a coefficient q2to generate a signal q2y[n−4] which is supplied to summation block630via a second feedback signal path. An output, q1y[n−2]+q2y[n−4], generated by summation block630is fed to summation block604where it is subtracted from the signal Ax[n]+p1x[n−1]+p2x[n−2] to generate the expression for the output sample y[n]=−q1y[n−2]−q2y[n−4]+Ax[n]+p1x[n−1]+p2x[n−2], as shown in equation (7). As will become apparent to those skilled in the art given the teachings herein, at least one of the first and second delay lines is preferably implemented using at least one shift register, digital signal processor and/or tapped delay line, although the invention is not limited to any specific delay line implementation.

The BIIR transformation according to embodiments of the invention described above can be extended in a general sense such that a dependency exists only between the calculation of samples y[n] and y[n−2k], where k is a natural number. If multiply operations are performed in several pipeline stages, a higher degree of decoupling between samples can provide greater calculation efficiency. In a general case, in order to obtain a transformed BIIR filter transfer function H(z) of stage N, a transformation of stage N−1 is preferably multiplied by the following expression:

(1+b1N⁢z-N)⁢(1+b2N⁢z-N)(1+b1N⁢z-N)⁢(1+b2N⁢z-N),(8)
where N is an integer greater than or equal to two. As will become apparent to those skilled in the art given the teachings herein, it is straightforward to show that the expression set forth in equation (8) above adds poles inside the unit circle, and thus satisfies the BIBO stability criterion of the BIIR filter.

By way of example only and without loss of generality, assuming it is desired to extend the expression above to handle possible pipeline stalls, stage 2 of the novel BIIR transformation is calculated by inserting N=2 in equation (8) to yield the following expression:

(1+b12⁢z-2)⁢(1+b22⁢z-2)(1+b12⁢z-2)⁢(1+b22⁢z-2),(9)
Both the numerator and denominator of the transfer function H(z) shown in equation (1) are multiplied by the expression in equation (9) to yield the following derivation:

FIG. 7is a graphical illustration depicting pole locations for the exemplary transformed BIIR filter of equation (11), according to another embodiment of the invention. It can be easily shown that in the z-transform plane, the transformed BIIR filter in equation (11) will be represented as eight poles and six zeros, all poles being located within the boundary of the unit circle. With reference toFIG. 7, a first pole702is located at a position of Rbon the real axis and Ibon the imaginary axis, a second pole704is located at a position of Rbon the real axis and −Ibon the imaginary axis, a third pole706is located at a position of Rb2on the real axis and Ib2on the imaginary axis, a fourth pole708is located at a position of Rb2on the real axis and −Ib2on the imaginary axis, a fifth pole710is located at a position of −Rb2on the real axis and Ib2on the imaginary axis, a sixth pole712is located at a position of −Rb2on the real axis and −Ib2on the imaginary axis, a seventh pole714is located at a position of −Rbon the real axis and Ibon the imaginary axis, an eighth pole716is located at a position of −Rbon the real axis and −Ibon the imaginary axis, a first zero718is located at a position of −Rbon the real axis and Ibon the imaginary axis, a second zero720is located at a position of −Rbon the real axis and −Ibon the imaginary axis, a third zero722is located at a position of −Rb2on the real axis and Ib2on the imaginary axis, a forth zero724is located at a position of −Rb2on the real axis and −Ib2on the imaginary axis, a fifth zero726is located at a position of Rb2on the real axis and Ib2on the imaginary axis, and a sixth zero728is located at a position of Rb2on the real axis and −Ib2on the imaginary axis. As shown, the respective locations of all poles lie within the boundary of a unit circle730, which is a fundamental requirement of any IIR filter since it assures filter stability.

FIG. 8is a block diagram depicting at least a portion of an exemplary BIIR filter circuit800, according to another embodiment of the present invention. BIIR filter800is a functional implementation of the transformed BIIR filter represented by equation (11) above. More particularly, input sample x[n] is multiplied in block802by a coefficient (i.e., constant) A to generate the signal Ax[n] supplied to a first summation block804. Concurrently, the input sample x[n] is fed to a first delay line806, which may be an input delay line, which includes a plurality of delay blocks (first through sixth)808,810,812,814,816and818connected together in series. The first delay block808, which has a delay D1associated therewith, is operative to generate a delayed input sample x[n−1] which is multiplied in block820by a coefficient c1to generate the signal c1x[n−1] supplied to a second summation block822. The second delay block810, which has a delay D2associated therewith, is operative to generate a delayed input sample x[n−2] which is multiplied in block824by a coefficient c2to generate the signal c2x[n−2] supplied to a third summation block826. The third delay block812, which has a delay D3associated therewith, is operative to generate a delayed input sample x[n−3] which is multiplied in block828by a coefficient c3to generate the signal c3x[n−3] supplied to a fourth summation block830. The fourth delay block814, which has a delay D4associated therewith, is operative to generate a delayed input sample x[n−4] which is multiplied in block832by a coefficient c4to generate the signal c4x[n−4] supplied to a fifth summation block834. The fifth delay block816, which has a delay D5associated therewith, is operative to generate a delayed input sample x[n−5] which is multiplied in block836by a coefficient c5to generate the signal c5x[n−5] supplied to a sixth summation block838. The sixth delay block818, which has a delay D6associated therewith, is operative to generate a delayed input sample x[n−6] which is multiplied in block840by a coefficient c6to generate the signal c6x[n−6] supplied to the sixth summation block838.

It is to be appreciated that the respective delays D1through D6associated with delay blocks808through818, respectively, may be the same or different relative to one another, and the invention is not limited to any specific value of each delay. An output, c1x[n−1]+c2x[n−2]+c3x[n−3]+c4x[n−4]+c5x[n−5]+c6x[n−6], generated by summation block822is fed to summation block804where it is added to the signal Ax[n].

The output sample y[n] generated by summation block804is fed to a second delay line842, which maybe an output delay line. Delay line842includes a first delay block844having a delay D1associated therewith, a second delay block846having a delay D2associated therewith, a third delay block848having a delay D3associated therewith, a fourth delay block850having a delay D4associated therewith, a fifth delay block852having a delay D5associated therewith, a sixth delay block854having a delay D6associated therewith, a seventh delay block856having a delay D7associated therewith, and an eighth delay block858having a delay D8associated therewith. Delay block844is operative to generate a first delayed output sample y[n−1], delay block846is operative to generate a second delayed output sample y[n−2], delay block848is operative to generate a third delayed output sample y[n−3], delay block850is operative to generate a fourth delayed output sample y[n−4], delay block852is operative to generate a fifth delayed output sample y[n−5], delay block854is operative to generate a sixth delayed output sample y[n−6], delay block856is operative to generate a seventh delayed output sample y[n−7], and delay block858is operative to generate an eighth delayed output sample y[n−8].

The output sample y[n−4] generated by delay block850is multiplied in block860by a coefficient d1to generate a signal d1y[n−4] which is then supplied to a seventh summation block860via a first feedback signal path. Concurrently, the output sample y[n−8] generated by delay block858is multiplied in block864by a coefficient q2to generate a signal q2y[n−8] which is supplied to summation block862via a second feedback signal path. An output, d1y[n−4]+q2y[n−8], generated by summation block862is fed to summation block804where it is subtracted from the signal Ax[n]+c1x[n−1]+c2x[n−2]+c3x[n−3]+c4x[n−4]+c5x[n−5]+c6x[n−6] to generate the expression for the output sample y[n]=−d1y[n−4]−q2y[n−8]+Ax[n]+c1x[n−1]+c2x[n−2]+c3x[n−3]+c4x[n−4]+c5x[n−5]+c6x[n−6], as shown in equation (11). As will become apparent to those skilled in the art given the teachings herein, at least one of the first and second delay lines is preferably implemented using at least one shift register, digital signal processor and/or tapped delay line, although the invention is not limited to any specific delay line implementation.

The BIIR filter transformation defined in equations (10) and (11) above, and shown inFIGS. 7 and 8, utilizes nine multipliers per output and enables four output calculations to be performed concurrently (i.e., in parallel). Thus, assuming operation in a vector processor environment with sixteen multipliers and two pipeline stages for multiplier calculations, the above transformation achieves a throughput of 16/9=1.78 output samples per cycle, compared to ½=0.5 sample per cycle achieved using a standard BIIR filter implementation. In this exemplary embodiment, therefore, performance is advantageously improved by 1.78/0.5=3.56 times.

One or more embodiments of the invention or elements thereof may be implemented in the form of an article of manufacture including a machine readable medium that contains one or more programs which when executed implement such method step(s); that is to say, a computer program product including a tangible computer readable recordable storage medium (or multiple such media) with computer usable program code stored thereon in a non-transitory manner for performing the method steps indicated. Furthermore, one or more embodiments of the invention or elements thereof can be implemented in the form of an apparatus including a memory and at least one processor (e.g., vector processor) that is coupled with the memory and operative to perform, or facilitate the performance of, exemplary method steps.

Yet further, in another aspect, one or more embodiments of the invention or elements thereof can be implemented in the form of means for carrying out one or more of the method steps described herein; the means can include (i) hardware module(s), (ii) software module(s) executing on one or more hardware processors, or (iii) a combination of hardware and software modules; any of (i)-(iii) implement the specific techniques set forth herein, and the software modules are stored in a tangible computer-readable recordable storage medium (or multiple such media). Appropriate interconnections via bus, network, and the like can also be included.

Embodiments of the invention may be particularly well-suited for use in an electronic device or alternative system (e.g., communications system). For example,FIG. 9is a block diagram depicting at least a portion of an exemplary processing system900formed in accordance with an embodiment of the invention. System900, which may represent, for example, a BIIR system or a portion thereof, may include a processor910, memory920coupled with the processor (e.g., via a bus950or alternative connection means), as well as input/output (I/O) circuitry930operative to interface with the processor. The processor910may be configured to perform at least a portion of the functions of the present invention (e.g., by way of one or more processes940which may be stored in memory920), illustrative embodiments of which are shown in the previous figures and described herein above.

It is to be appreciated that the term “processor” as used herein is intended to include any processing device, such as, for example, one that includes a CPU and/or other processing circuitry (e.g., digital signal processor (DSP), network processor, microprocessor, etc.). Additionally, it is to be understood that a processor may refer to more than one processing device, and that various elements associated with a processing device may be shared by other processing devices. For example, in the case of BIIR filter circuit600shown inFIG. 6, each of the delay elements608,610,620,622,624and626may be implemented in parallel (i.e., concurrently) using a separate corresponding DSP core, as in a distributed computing configuration. The term “memory” as used herein is intended to include memory and other computer-readable media associated with a processor or CPU, such as, for example, random access memory (RAM), read only memory (ROM), fixed storage media (e.g., a hard drive), removable storage media (e.g., a diskette), flash memory, etc. Furthermore, the term “I/O circuitry” as used herein is intended to include, for example, one or more input devices (e.g., keyboard, mouse, etc.) for entering data to the processor, and/or one or more output devices (e.g., display, etc.) for presenting the results associated with the processor.

Accordingly, an application program, or software components thereof, including instructions or code for performing the methodologies of the invention, as described herein, may be stored in a non-transitory manner in one or more of the associated storage media (e.g., ROM, fixed or removable storage) and, when ready to be utilized, loaded in whole or in part (e.g., into RAM) and executed by the processor. In any case, it is to be appreciated that at least a portion of the components shown in the previous figures may be implemented in various forms of hardware, software, or combinations thereof (e.g., one or more DSPs with associated memory, application-specific integrated circuit(s) (ASICs), functional circuitry, one or more operatively programmed general purpose digital computers with associated memory, etc). Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations of the components of the invention.

At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.

An integrated circuit in accordance with the present invention can be employed in essentially any application and/or electronic system in which BIIR systems may be employed. Suitable systems for implementing techniques of the invention may include, but are not limited to, mobile phones, personal computers, wireless communication networks, etc. Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.