Semiconductor integrated circuit using the same

A hard macro cell which prevents signal delay and quality deterioration of signal waveforms without requiring excessively long wires, and a semiconductor integrated circuit using the hard macro cell. The semiconductor integrated circuit includes the hard macro cell and other hard macro cells, which are functional blocks for performing predetermined functions. The hard macro cell is provided with input/output terminals for connecting the hard macro cell with the other hard macro cells, a repeater for overcoming signal delay and for improving the quality of signal waveforms, and an input terminal and an output terminal for connecting global wires which connect the other hard macro cells to the repeater. Signals outputted from an output terminal of one of the other hard macro cells are inputted to an input terminal of another of the other hard macro cells via the global wires and the repeater.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a hard macro cell and a semiconductor integrated circuit using the hard macro cell and, more specifically, to a hard macro cell which is incorporated into a semiconductor integrated circuit as a functional block that is a circuit for performing a predetermined function, such as that of a RAM or a ROM.

2. Description of the Related Art

A semiconductor integrated circuit is generally composed of a plurality of functional blocks. Among these functional blocks, ones having a variety of uses, such as memory blocks, are generally treated as libraries at the functional block level so that they can be used in various applications. Such functional blocks treated as libraries are referred to as hard macro cells. Aside from the hard macro cells, the functional blocks include soft macro cells, in which design content can be modified as is appropriate when the semiconductor integrated circuit is designed. As shown inFIG. 8, the semiconductor integrated circuit is typically formed by combining a plurality of functional blocks including the hard macro cells and the soft macro cells.

In recent years, mainly system LSIs onto which many large-sized hard macro cells are loaded have been used as the semiconductor integrated circuits. The size of the hard macro cells is not uncommonly 5×5 mm or greater, and the size of the LSI is generally 10×10 mm or greater.

Thus, there has been a problem in that global wires for mutually connecting the hard macro cells have been lengthened in proportion to the size of the LSI, which has resulted in increased signal delay between the wires.

Further, because voltage at a power supply for the LSI has been decreased due to advances in fine patterning (reductions in design rules), noise resistance of signals needs to be improved. Not only overcoming the signal delay, but also improving the quality of signal waveforms are important problems.

In order to solve these problems, a repeater (cell) for adjusting the signal delay and the signal waveforms has conventionally been provided at an intermediate portion of the global wires, or the global wires have been passed through the hard macro cell so as to be shortened as much as possible.

FIG. 8shows a conventional semiconductor integrated circuit100that includes functional blocks101to107for performing predetermined functions. A global wire108connecting the hard macro cell103(functional block103) and the hard macro cell105(functional block105) is formed so as to circumvent the hard macro cell104(functional block104), and a repeater109is provided at an intermediate portion of the global wire108.

In such a semiconductor integrated circuit, however, there has been a problem that signal delay and deterioration of signal waveforms cannot be effectively reduced because the global wire is disposed so as to circumvent the hard macro cell104and is thereby lengthened excessively. Alternatively, when the global wire is passed through the hard macro cell, there has been a problem that the hard macro cell may cause operational errors because the hard macro cells, such as RAMs or ROMs, which perform analog operations are easily affected by cross-talk with other signal wires and the like.

Japanese Patent Application Laid-Open No. 11-163268 discloses a semiconductor integrated circuit in which a buffer circuit for delay adjustment is provided in a functional block. In this application, however, there is a problem that circuits around the buffer circuit may be affected by cross-talk depending upon the position of the buffer circuit.

SUMMARY OF THE INVENTION

In view of the facts described above, an object of the present invention is to provide a hard macro cell which can prevent signal delay and quality deterioration of signal waveforms without requiring excessively long wires in a semiconductor integrated circuit, and a semiconductor integrated circuit using the hard macro cell.

In order to attain the above-stated object, a first aspect of the present invention is a hard macro cell comprising: a plurality of circuit blocks, the circuit blocks each having a predetermined function; and at least one repeater, which is provided in a predetermined one of the circuit blocks, for adjusting input signals so that the input signals pass through the predetermined circuit block with no significant deterioration of the signals.

The hard macro cell is a functional block which forms at least a portion of a semiconductor integrated circuit such as an LSI, and is a circuit which performs a predetermined function such as that of a CPU, a RAM or a ROM. The hard macro cell includes the plurality of circuit blocks, and each of the circuit blocks has a predetermined function. For example, when the hard macro cell is a RAM, the predetermined function is that of a memory cell array including many memory cells, an address decoder, or the like.

The repeater is provided in a predetermined one of the circuit blocks. The repeater adjusts inputted signals so that the inputted signals pass through the predetermined circuit block with no significant deterioration of the signals. For example, when signals transferred between other hard macro cells pass through the predetermined circuit block, the repeater adjusts the inputted signals so that the signals are not delayed and the waveforms thereof are not distorted. Since the hard macro cell includes the repeater in this manner, wires do not need to circumvent the hard macro cell, whereby the wires can be kept short, and signal delay and distortion of signal waveforms can be prevented.

The predetermined circuit block is less affected by noise from signals passing through the circuit block, and is preferably one for processing digital signals as in a second aspect of the present invention. When signals pass through a circuit block for processing analog signals, the circuit block may be affected by noise from the passing signals. In the present invention, however, since the signals pass through one of the circuit blocks for processing digital signals, the effects of noise can be reduced.

A third aspect of the present invention is the hard macro cell further comprising: peripheral connection terminals; connection terminals provided at the repeater; and internal wires for connecting the connection terminals of the repeater and the peripheral connection terminals. The internal wires are formed in the predetermined circuit block in a similar manner as the repeater. Thus, wires from other hard macro cells are connected to the peripheral connection terminals, whereby the wires between the hard macro cells can be designed such that the wires are prevented from passing through areas of the hard macro cell, which are easily affected by noise. Accordingly, the wires between the hard macro cells can be suitably and easily designed.

Further, since the internal wires pass through the predetermined circuit block, time constants of signal delay, which depend upon disposition of the wires, are fixed. Therefore, the timing of the semiconductor integrated circuit can be easily set.

A fourth aspect of the present invention is the hard macro cell further comprising at least another repeater, with the repeaters being disposed so that orientation directions of the repeaters are different from each other. In other words, the hard macro cell has at least two signal paths in which transmission directions of the signals are different from each other. Accordingly, a greater degree of freedom for design can be achieved.

A fifth aspect of the present invention is the hard macro cell, wherein the internal wires are not preconnected to the connection terminals of the repeater and are selectively connectable to the connection terminals of the repeater. Accordingly, a considerably greater degree of freedom for wire design can be achieved.

A sixth aspect of the present invention is a semiconductor integrated circuit comprising: a plurality of functional blocks performing predetermined functions, the functional blocks being connected to each other; a hard macro cell, which is included in one of the functional blocks and comprising a plurality of areas, which perform predetermined operations; and a repeater formed in one of the areas comprising a digital signal processing section, which adjusts delay and waveforms of signals inputted to the hard macro cell and outputs the adjusted signals to at least one of said functional blocks other than the hard macro cell.

In accordance with the present invention, since the repeater is provided within the hard macro cell, wires do not need to circumvent the hard macro cell, whereby the wires can be kept short, and signal delay and distortion of signal waveforms can be prevented. Further, since the repeater is provided in the one of the areas for processing digital signals, the effects of noise can be reduced.

A seventh aspect of the present invention is the semiconductor integrated circuit, wherein the hard macro cell is one of a RAM and a ROM having memory cells for storing data, and the digital signals processing section selects at least one memory cell corresponding to an address specifying the memory cell.

An eighth aspect of the present invention is the semiconductor integrated circuit, wherein each of the functional blocks has input/output terminals for inputting signals to the functional block and outputting signals from the functional block, with the functional blocks electrically connected to each other via external wires connecting the input/output terminals of functional blocks.

A ninth aspect of the present invention is the semiconductor integrated circuit, wherein the repeater includes connection terminals for transmitting the signals inputted to the hard macro cell and for transmitting the adjusted signals, and the hard macro cell includes internal wires for electrically connecting each connection terminal to an input/output terminal.

The internal wires are formed in the one of the areas for processing digital signals in a similar manner as the repeater. Thus, wires from other hard macro cells are connected to, for example, the input/output terminals provided at the periphery of the hard macro cell, whereby the wires between the hard macro cells can be designed such that the wires are prevented from passing through areas of the hard macro cell, which are easily affected by noise. Accordingly, the wires between the hard macro cells can be suitably and easily designed.

A tenth aspect of the present invention is the semiconductor integrated circuit, wherein the hard macro cell includes at least one input/output terminal which is not electrically connected with any of the connection terminals. In other words, the connection terminals of the repeater and the input/output terminals are not electrically connected to each other in advance. Accordingly, a considerably greater degree of freedom for wire design can be achieved.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

A first embodiment of the present invention will now be explained referring to the drawings.FIG. 1is a schematic plan view of a semiconductor integrated circuit10according to the present invention.

As shown inFIG. 1, the semiconductor integrated circuit10includes hard macro cells12to18. The hard macro cells12to18are functional blocks (circuits) for performing predetermined functions such as those of a CPU, a RAM, a ROM and the like. In this embodiment, a case in which the hard macro cell15is an SRAM will be described.

As shown inFIG. 2, the hard macro cell15is provided with input/output terminals (peripheral connection terminals)20and22for connecting the hard macro cell15with the other hard macro cells, a repeater (repeater cell)24for overcoming signal delay and for improving the quality of signal waveforms, and an input terminal26and an output terminal28for connecting the repeater24to global wires which mutually connect the hard macro cells (and which will be described later). The repeater24includes a transistor.

As shown inFIG. 1, the input/output terminal20of the hard macro cell15is connected with an input/output terminal32of the hard macro cell16via a global wire30. The input/output terminal22of the hard macro cell15is connected with an input/output terminal36of the hard macro cell16via a global wire34. As a result, signals can be transferred between the hard macro cells15and16.

An output terminal38of the hard macro cell16is connected to the input terminal26of the repeater24via a global wire40, and an input terminal42of the hard macro cell14is connected to the output terminal28of the repeater24via a global wire44. Accordingly, signals outputted from the output terminal38of the hard macro cell16are inputted to the input terminal42of the hard macro cell14via the repeater24.

Since the repeater24is provided in the hard macro cell15, which is disposed between the hard macro cell14and the hard macro cell16, in this manner, the input terminal42of the hard macro cell14and the output terminal38of the hard macro cell16can be connected over a substantially shortest distance between the input terminal42and the output terminal38, and lengths of the global wires can be thereby minimized. Therefore, as compared with a conventional case in which a wire is formed between the hard macro cells14and16so as to circumvent the hard macro cell15, signal delay and quality deterioration of the signal waveforms can be effectively prevented. Further, since an area for the repeater24does not need to be set aside in areas outside of the hard macro cells, a greater degree of freedom for wire design is possible, and enlargement of the semiconductor integrated circuit10can be prevented.

FIG. 3shows an example circuit layout of the hard macro cell15in which the hard macro cell15is divided into a plurality of circuit blocks (areas) with each having a predetermined function. The plurality of circuit blocks include memory cell arrays46and48in which many memory cells for storing information are disposed, a decoder area50in which an address decoder and an address driver for selecting memory cells corresponding to specified addresses from the many memory cells are disposed, I/O areas52and54in which sense amplifiers for detecting and amplifying signals from the memory cells and I/O buffers are disposed, and a control circuit area55in which a control circuit for controlling the decoder area50and the I/O areas52and54is disposed.

Out of these, the memory cell arrays46and48, and the I/O areas52and54include many memory cells and sense amplifiers, respectively, which handle signals for analog operations depending on minute potential differences, whereby these areas are easily affected by cross-talk with other signal wires.

Therefore, it is preferable that the repeater24is not disposed in the memory cell arrays46and48or in the I/O areas52and54, and that the global wires40and44are not disposed so as to pass through these areas.

Accordingly, it is preferable that the repeater24is disposed in an area which is at less risk of being affected by cross-talk, such as the area including the address decoder and the address driver which perform full-swing operations (i.e., digital operations) or another area in the hard macro cell disposed with power supply wire. In this embodiment, the decoder area50or the control circuit area55is a suitable location for the repeater24, and a case in which the repeater24is disposed in the control circuit area55will be described as an example. In this manner, when the repeater24and the global wires40and44are disposed in one of the areas which are not easily affected by cross-talk, the effects of cross-talk with other signal wires can be effectively prevented.

FIG. 4is a schematic cross-sectional view of the hard macro cell15. The hard macro cell15comprises a substrate layer64, which includes elements56to62such as transistors, having successively disposed thereon a first metal layer66, a second metal layer68and a third metal layer70for wiring between the elements and between the elements and the input/output terminals.

The elements56and57are transistors which form a circuit disposed in the I/O area52. The elements58to60are transistors which form a circuit disposed in the control circuit area55, and the element59is a transistor which forms the repeater24. The elements61and62are transistors which form a circuit disposed in the I/O area54.

The element59forming the repeater24is connected with the input terminal26and the output terminal28which are disposed in the third metal layer70. The element58is connected with the input/output terminal20disposed in the second metal layer68, and the element62is connected with the input/output terminal22disposed in the second metal layer68.

The elements56and57are connected via a wire72formed in the first metal layer66, and the elements60and61are connected via a wire74formed in the first metal layer66. The wires between the elements and between the elements and the input/output terminals are thus formed in the plural metal layers (wire layers).

Thus, the global wires30and34are formed in the second metal layer68, and the global wires40and44are formed in the third metal layer70.

The element59forming the repeater24is disposed in an unoccupied space or a space reserved for the repeater24in the control circuit. As shown inFIG. 4, when the wires of the hard macro cell15are formed in the first metal layer66and the second metal layer68, the input terminal26and the output terminal28are disposed in the third metal layer70, and the global wires40and44are formed in the third metal layer70. In this case, areas which may be disposed with wires and areas which may not be disposed with wires are predetermined so that the global wires40and44do not pass through the areas which are easily affected by noise when the wires between the hard macro cells are designed.

Thus, the repeater24is disposed in one of the areas which are not affected by cross-talk with other signal wires, whereby signal delay and quality deterioration of the signal waveforms can be effectively prevented.

Second Embodiment

Next, a second embodiment of the present invention will be explained. In the second embodiment, a modified example of the hard macro cell15of the first embodiment will be described. Components identical to those of the first embodiment will be referred to using the same reference numerals, and detailed description thereof will be omitted.

FIG. 5shows a hard macro cell76according to this embodiment, wherein an input terminal78is provided at a periphery of the hard macro cell76on a lower side of the repeater24inFIG. 5, and an output terminal80is provided at the periphery of the hard macro cell76on an upper side of the repeater24inFIG. 5(hereinafter, the adjectives upper, lower, left and right refer to the orientation in the drawings of elements referred to thereby).

The input terminal78provided at the periphery of the hard macro cell76and the input terminal26of the repeater24are connected via an intramacro passing wire (internal wire)82. The output terminal80provided at the periphery of the hard macro cell76and the output terminal28of the repeater24are connected via an intramacro passing wire (internal wire)84. The global wire40is connected to the input terminal78, and the global wire44is connected to the output terminal80.

When the input terminal26and the output terminal28of the repeater24are disposed in the third metal layer70, the intramacro passing wires82and84are formed in the third metal layer70. However, when the input terminal26and the output terminal28are disposed in the second metal layer68, the intramacro passing wires82and84may be formed in the second metal layer68. Further, the intramacro passing wires82and84are formed in the control circuit area55or the decoder area50which are less affected by cross-talk with other signal wires.

Thus, the input terminal78and the output terminal80are provided at the periphery of the hard macro cell76, whereby the wires between the hard macro cells can be designed such that the global wires40and44are prevented from passing through areas of the hard macro cell, which are easily affected by noise. Accordingly, the wires between the hard macro cells can be suitably and easily designed. Further, since the intramacro passing wires82and84are formed in the control circuit area55or the decoder area50, which are less affected by cross-talk with other signal wires, the effects of noise on the intramacro passing wires82and84do not need to be considered.

If the global wires40and44are formed inside the hard macro cell, time constants, which depend upon resistance components and capacitance components of the wires, will vary with the positions of the global wires40and44, whereby variation in signal delay will occur, making setting of signal timing difficult. In this embodiment, however, the intramacro passing wires82and84pass through predetermined positions, whereby the time constants of signal delay, which depend upon dispositions of the wires, are fixed. Therefore, the timing of the semiconductor integrated circuit can be easily set.

Third Embodiment

Next, a third embodiment of the present invention will be explained. In the third embodiment, a modified example of the hard macro cell76of the second embodiment will be described. Components identical to those of the second embodiment will be referred to using the same reference numerals, and detailed description thereof will be omitted.

FIG. 6shows a hard macro cell86according to this embodiment, which is provided with a plurality of repeaters24A and24B. An input terminal26A of the repeater24A is connected with an input terminal78A, disposed at a periphery of the hard macro cell86on a lower side thereof inFIG. 6, via an intramacro passing wire82A, and an output terminal28A of the repeater24A is connected with an output terminal80A, disposed at the periphery of the hard macro cell86on an upper side thereof inFIG. 6, via an intramacro passing wire84A.

An output terminal26B of the repeater24B is connected with an output terminal78B, disposed at the periphery of the hard macro cell86on the lower side thereof inFIG. 6, via an intramacro passing wire82B, and an input terminal28B of the repeater24B is connected with an input terminal80B, disposed at the periphery of the hard macro cell86on the upper side thereof inFIG. 6, via an intramacro passing wire84B.

As a result, signals from a hard macro cell disposed on the lower side of the hard macro cell86inFIG. 6can be transmitted to a hard macro cell disposed on the upper side of the hard macro cell86in FIG.6through the hard macro cell86, and signals from the hard macro cell disposed on the upper side of the hard macro cell86inFIG. 6can be transmitted to the hard macro cell disposed on the lower side of the hard macro cell86in FIG.6through the hard macro cell86.

The hard macro cell86thus has two signal paths in which transmission directions of the signals are different from each other, whereby a greater degree of freedom for design can be achieved.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be explained. In the fourth embodiment, a modified example of the hard macro cell86of the third embodiment will be described. Components identical to those of the third embodiment will be referred to using the same reference numerals, and detailed description thereof will be omitted.

FIG. 7shows a hard macro cell88according to this embodiment, in which the repeater24A is separated from (not preconnected to) the intramacro passing wires82A and84A, and the repeater24B is separated from (not preconnected to) the intramacro passing wires82B and84B. Connection terminals90to93are connected to one ends of the intramacro passing wires82A,82B,84A and84B, respectively.

Connection terminals94and95are provided at a periphery of the hard macro cell88on other sides of the hard macro cell88than those disposed with the input terminals78A and80B and the output terminals78B and80A. The connection terminal94is connected with a connection terminal96via an intramacro passing wire97, and the connection terminal95is connected with a connection terminal98via an intramacro passing wire99. In other words, the terminals for connecting with the global wires are provided on all of the sides of the hard macro cell88.

Thus, the hard macro cell88has a structure in which the repeaters24A and24B are separated from the intramacro passing wires, and the terminals for connecting with the global wires are provided on all of the sides of the hard macro cell88, whereby a considerably greater degree of freedom for wire design can be achieved. For example, when a wire is formed from a hard macro cell disposed on a left side of the hard macro cell88inFIG. 7to a hard macro cell disposed on an upper side of the hard macro cell88inFIG. 7, the wire from the hard macro cell disposed on the left side of the hard macro cell88is connected to the connection terminal94, and the connection terminal96is connected to the input terminal26A. Then, the output terminal28A is connected to the connection terminal92. In this manner, wires can be flexibly formed in accordance with the positions of the hard macro cells.

When there is no need to overcome signal delay by using the repeaters, the connection terminals may be connected to each other via the wires. Although the two repeaters are provided in this embodiment, three or more repeaters may be used. Further, an increased number of connection terminals may be provided at the periphery of the hard macro cell.