Bistable logic circuit using field effect transistors with a low voltage threshold and storage device incorporating such a circuit

The logic circuit comprises two field effect transistors in series, whose gates are connected to the supply voltage by a first load. The source of the first field effect transistor is connected to earth. The drain of the second field effect transistor is connected on the one hand to the supply voltage by a second load and to the gate of a third field effect transistor, whose drain is connected to the supply voltage and whose source is connected to the common point constituted by the drain of the first field effect transistor and the source of the second field effect transistor via a Schottky diode.

BACKGROUND OF THE INVENTION 
The invention relates to a bistable logic circuit using field effect 
transistors with a low voltage threshold and a storage device 
incorporating such a circuit. 
Static random access memories comprise matrices of active elements with two 
stable states, one corresponding to the state "0" and the other to the 
state "1". The addressing of each element, which is consequently a 
bistable circuit for reading or writing, takes place by the selection of 
the row and the column at the intersection of which the addressed element 
is located. 
The quality and advantage of each type of memory essentially depends on the 
stability and reduced size of each element. It is known to produce these 
memories in "MESFET" technology on gallium arsenide (GaAs). 
However, the high density of the memories requires a logic circuit 
technology with a very low consumption, which eliminates a logic with 
buffer store elements or buffered FET logic with "normally conductive 
MESFET" transistors, which is the only one whose technology has proved 
itself. In addition, there are logics comprising field effect transistors 
and Schottky diodes of the Schottky diode-FET logic type and high 
performance logics based on junction field effect transistors or Enhanced 
Junction FET Logics or "E.J.F.E.T.L", which indeed comply with the 
consumption criteria, but their technologies are too complex to be used 
for obtaining large-scale integration circuits (LSI). 
European Patent Application No. 0 021 858 describes a new logic based on 
MESFET transistors having a very low negative threshold voltage, which 
meets various criteria of large-scale integration circuits, namely low 
consumption, simple technology and permitting a good tolerance in 
connection with manufacture. 
BRIEF SUMMARY OF THE INVENTION 
The invention proposes the realization of bistable circuits using this 
technology. It therefore relates to store elements which can have a very 
small surface area, can be easily integrated and consequently it is 
possible to obtain memories with a high integration density. Thus, on a 
gallium arsenide substrate, it makes it possible to produce static random 
access memories with a high density (more than 256 bits) and a very high 
access speed (less than 1 nanosecond). 
The present invention therefore relates to a bistable logic circuit using 
field effect transistors with a low threshold voltage connected between 
the two terminals of a supply voltage generator, comprising two field 
effect transistors in series, whose gates are interconnected and connected 
to the first terminal of the supply voltage generator by a first load, the 
source of the first field effect transistor being connected to the second 
terminal of the supply voltage generator, the drain of the second field 
effect transistor being connected on the one hand to the first terminal of 
the supply voltage generator by a second load and on the other hand to the 
gate of a third field effect transistor, whose drain is connected to the 
first terminal of the supply voltage generator and the source to the 
common point constituted by the drain of the first transistor and by the 
source of the second transistor via a Schottky diode, said common point 
constituting the output terminal of the bistable circuit. 
The invention also relates to a storage device comprising such a bistable 
circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The circuits in question can be connected between the two terminals of a 
supply voltage generator and for simplification purposes they are 
considered to be between earth and voltage +V. 
The invention uses the technology of MESFET logic circuits with a slightly 
negative threshold voltage and which are also called "quasi-normally 
blocked" MESFET. The main element of the invention is a bistable 
flip-flop, which can be used as an elementary cell for the static random 
access memories. Generally a bistable flip-flop is implemented by 
intersecting two logic reversing switches in the manner shown in FIG. 1, 
while considering a direct coupled FET logic (DCFL). 
FIG. 2 shows a buffered FET logic (BFL) with normally conductive MESFET's. 
Transistors T.sub.25, and T.sub.26, T.sub.29 and T.sub.30, each have their 
gate connected to their source, and serve as saturable resistors. In this 
case it is ncessary to use two voltage sources having opposite signs. 
Finally FIG. 3 considers a low threshold FET logic (LTFL), making it 
possible to use only a single voltage source. In the case of MESFET's, 
they are of the quasi-normally blocked type. Hereinafter consideration 
will only be given to field effect transistors of this type. 
FIG. 4 shows the bistable circuit according to the invention. This bistable 
flip-flop has numerous advantages compared with the crossed reversing 
switches illustrated hereinbefore, i.e. its simplicity, the smaller number 
of elements and the fact that there are no crossing connections among the 
elements. These characteristics help to save space for the high density 
circuits. In addition, this cell is simple to address, which simplifies 
the access logic circuits. 
The bistable circuit comprises two field effect transistors of the 
quasi-normally blocked type T.sub.1 and T.sub.2 in series, whose gates are 
connected to +V by the same load Z.sub.1. The source of T.sub.1 is 
connected to earth. The drain of T.sub.2 is connected on the one hand to 
+V by a load Z.sub.2 and on the other to a gate of T.sub.3. The drain of 
T.sub.3 is connected to +V and its source is looped to the common point 
formed by the drain of T.sub.1 and the source of T.sub.2 by a Schottky 
diode d.sub.c2. This common point forms the output of the bistable 
circuit. These loads Z.sub.1 and Z.sub.2 are resistive loads, and can in 
particular be saturable resistors. Throughout the remainder of the 
following description when reference is made to load Z.sub.1, it is loads 
of this type which are being considered. Reference is also made 
hereinafter to "low level", which corresponds to state "0" and "high 
level" which corresponds to state "1". 
The following characteristic voltages are obtained: 
V.sub.T =threshold voltage of the field effect transistors 
V.sub.H =high level 
V.sub.B =low level 
V.sub.OS =opening voltage of the Schottky diodes 
EQU (V.sub.OS =0.7 V) 
V.sub.S =threshold switching voltage defined by 
EQU i.sub.T (V.sub.S)=i.sub.Z 
with i.sub.T (V.sub.S)=current of the field effect transistor when 
V.sub.GS =V.sub.S 
i.sub.Z =current of the load Z 
V.sub.di =failure voltage of the field effect transistors relative to load 
EQU Z(V.sub.di .perspectiveto.0.2 volt). 
For the remainder of the description, a Schottky diode d.sub.c1 is 
introduced between the source of transistor T.sub.1 and earth, as shown in 
FIG. 9. This in no way modifies the operation of this bistable circuit 
but, on considering a memory using these bistable circuits and its basic 
elements, it makes it possible to work in the blocked-saturated from with 
MESFET field effect transistors of the quasi-normally blocked type. 
On the basis of FIG. 9, Table 1 at the end of the description shows the two 
stable states of the cell. V.sub.di is the failure voltage in transistor 
T.sub.i, V.sub.OS the Schottky voltage and V.sub.S3 the voltage at point 
S.sub.3, and these descriptions will be used throughout the text. In 
addition, V.sub.D4 is the voltage at point D.sub.4 and V.sub.S3 is the 
switching threshold voltage of T.sub.3 with respect to i.sub.T.sbsb.1. 
Thus, there are two states: 
State "0":T.sub.1 and T.sub.2 conductive, T.sub.3 blocked 
State "1": T.sub.1 and T.sub.3 conductive, T.sub.2 blocked. 
This bistable flip-flop used in the memory cell functions as a "current 
mirror" between field effect transistors T.sub.1 and T.sub.2 and if 
T.sub.2 is conductive, T.sub.3 is blocked and vice versa. 
It has been shown hereinbefore that the state of the cell is linked with 
that of transistor T.sub.2. Thus, the flip-flop can be forced towards one 
of the two stable states by acting on V.sub.D.sbsb.4 : 
If 
EQU V.sub.GS.sbsb.2 =V.sub.G.sbsb.2 -V.sub.D.sbsb.4 &lt;V.sub.S.sbsb.2 
V.sub.GS.sbsb.2 being the voltage between the gate and the source of 
transistor T.sub.2. 
V.sub.S.sbsb.2 : switching threshold voltage of T.sub.2 with respect to 
Z.sub.2, T.sub.2 becoming conductive and the cell switching to state "0". 
However, if 
EQU V.sub.GS.sbsb.2 &lt;V.sub.S.sbsb.2 
T.sub.2 is blocked and the cell switches to state "1". 
This leads to the following switching point of the circuit: 
EQU V.sub.D.sbsb.4 (S)=V.sub.G.sbsb.2 -V.sub.S.sbsb.2 =2V.sub.OS 
-V.sub.S.sbsb.2 
The characteristic output levels of the flip-flop are consequently: 
EQU V.sub.D.sbsb.4 (H)=V-V.sub.S.sbsb.3 -V.sub.OS (high level) 
EQU V.sub.D.sbsb.4 (B)=V.sub.OS +V.sub.d.sbsb.1 (low level) 
EQU V.sub.D.sbsb.4 (S)=2V.sub.OS -V.sub.S.sbsb.2 (threshold) 
FIG. 5 shows the diagram of a random access memory using bistable circuits 
1 according to the invention. 
The elements are placed in rows X and columns Y. Each row X is connected to 
addressing device 2 at X, which has 2.sup.NX outputs and NX inputs, NX 
obviously being an integer, while 2.sup.NX is the number of rows. 
The 2.sup.NY columns Y are connected to addressing device 3 at Y, which has 
NY inputs and two supplementary inputs. One of these inputs E/L assigns 
the alternate write or read functions for the information of the chosen 
element, while the second input E, in writing, permits the entry of data. 
Input E/L indicates to the device whether it is to assume a read or write 
function. 
In both cases a row and a column are chosen. Thus, only the element at the 
intersection of the row chosen by addressing device 2 and the column 
chosen by addressing device 3 is able to record data "1" or "0" or to 
restore it, in accordance with the instruction received by input E/L. 
In the case where a recording instruction is given, it records state "0" or 
"1", as a function of the voltage of input E. In the case of reading, it 
supplies the data contained therein at S, after selection of the desired 
row and column. 
Thus, the elements of the static random access memory described here are as 
follows: 
bistable memory cell described hereinbefore 
addressing gate X (rows) 
addressing gate y (columns) 
half-control circuit of input X (or Y) 
read-write selection 
write selection 
reading amplifier 
FIG. 6 shows addressing device 2 at X. Each row X is controlled by a gate 
10 making it possible to select the row number as a function of the levels 
applied to its input. These levels are obtained by two identical 
half-control circuits 11 and 12, which reproduce the complementary logic 
signals for the inputs of gates 10. 
FIG. 7 shows the addressing device 3 at Y. Each column Y is controlled by a 
gate 13 making it possible to select the column number as a function of 
the levels applied to its input. These levels are obtained by means of two 
identical half-control circuits 14, 15 which reproduce the complementary 
logic signals for the inputs of gates 13. 
Circuit 16 contains the read-write selection circuit into which is fed the 
signal E/L and the signal E for the entry of data in the case of writing: 
It also contains the reading amplifier which, in the case of reading, 
supplies output signal S. 
Thus, FIG. 6 shows the diagram of addressing device 2 at X. It comprises 2 
NX logic reversing circuits 11, 12 grouped in block 25 and 2.sup.NX gates 
grouped in means 26. It is possible to take as an example NX=5, 2.sup.NX 
consequently being equal to 32. 
These half-control circuits are set up in the manner indicated in FIG. 6. 
Thus, two complementary outputs V.sub.Xi and V.sub.Xi correspond to each 
input of means 25. Means 26 comprises 32 NOR gates, whose outputs are 
respectively brought into state 1, when the five inputs are at state "0". 
Each of these gates carries a number from 0 to 31. 
However, of each line V.sub.Xi or V.sub.Xi by definition one is always 
brought to level 1. Moreover, each number from 0 to 31 in binary notation 
is a five digit number, each of which is a 1 or a 0. Number 3 is for 
example written 00011. 
To excite gate 3, it is merely necessary for it to be connected to lines 
V.sub.X1, V.sub.X2, V.sub.X3 which are at level 0 and to lines V.sub.X4 
and V.sub.X5, which are also at level 0. 
Thus, for obtaining the address of line X.sub.j, it is merely necessary to 
apply to the inputs the digits composed by the number j in order to obtain 
line X.sub.j and consequently select one line of the matrix. 
It is therefore necessary to select one element of line X.sub.j, that of 
column Y.sub.K for on the one hand writing data, or on the other hand for 
reading the data which it contains. This is the function of addressing 
device 3 at Y shown in FIG. 7. It fulfills the same function as addressing 
device 2 at X. However, it also has two inputs, namely input E/L 
controlling the writing or reading function of the data and input E, which 
in the case of writing, controls the entry of a "0" or a "1". Input E/L in 
the writing position makes it possible to obtain the data contained in the 
element addressed at output S. 
FIG. 8 shows the half-control circuits, which are the same no matter 
whether rows or columns are considered, Thus, each half-control (11, 12 or 
14, 15) reproduces the complementary logic signals making it possible to 
select the desired row and column numbers. Each half-control circuit has 
an input reversing stage constituted by a field effect transistor T.sub.16 
and a load Z.sub.16 connected in the manner indicated in FIG. 8. The 
output stage is constituted by a field effect transistor T.sub.17 with two 
independent sources, its drain being connected to the supply voltage +V. 
One of the sources is connected to earth by a diode d.sub.1 and a load 
Z.sub.15 in series and supplies output V.sub.Xi for the second identical 
half-control circuit. The other source is connected to one line of 
d.sub.xi receiving the same signal as that corresponding to V.sub.Xi. The 
second half-control circuit comprises field effect transistors T.sub.36, 
T.sub.37 and loads Z.sub.35, Z.sub.36. The second source of T.sub.37 
constutes an output for diodes d.sub.xi receiving the signal corresponding 
to V.sub.xi. These different elements are interconnected in the manner 
shown in FIG. 8. 
FIG. 9 shows a storage device produced from the bistable circuit shown in 
FIG. 4. This bistable circuit 1 acts as a random access memory cell. 
Access to the cell takes place by means of field effect transistors 
T.sub.4, T.sub.5, respectively controlled by an addressing gate X (row) 10 
and an addressing gate Y (column) 13. 
The data input E is isolated by the field effect transistor T.sub.6 
controlled by a read-write selection system. 
Each line X is controlled by a gate X 10 constituted by a field effect 
transistor T.sub.10 and loads Z.sub.6, Z.sub.7 forming a simple 
single-stage reversing switch. This gate is addressed by diodes d.sub.X1, 
d.sub.X2 . . . d.sub.Xp having a common base connected to the grid of 
transistor T.sub.10. These elements are interconnected in the manner shown 
in FIG. 9. Access to column Y is obtained by means of field effect 
transistor T.sub.5, whose gate is controlled by a gate Y 13 identical to 
the aforementioned gate X 10 with a field effect transistor T.sub.11, 
loads Z.sub.8 and Z.sub.9 and diodes d.sub.Y1, d.sub.Y2 . . . d.sub.yq. 
These different elements are interconnected in the manner shown in FIG. 9. 
Data input E is insulated by field effect transistor T.sub.6, whose gate is 
controlled by the read-write selection system constituted by a logic 
reversing switch. 
The elements of this read-write selection system are field effect 
transistors T.sub.12, T.sub.13, resistors Z.sub.10, Z.sub.11 and diode 
d.sub.EL, said elements being interconnected in the manner shown in FIG. 
9. The signals from E are supplied by a write selection system constituted 
by a logic reversing switch identical to that of the read-write selection 
system and whose elements are field effect transistors T.sub.14, T.sub.15, 
resistors Z.sub.12, Z.sub.13 and diode d.sub.E, these elements being 
interconnected in the manner shown in FIG. 9. 
The reading amplifier has two stages, the first stage being a 
following-displacing circuit, constituted by a field effect transistor 
T.sub.7, diode d.sub.A1 and resistor Z.sub.3, while the second is a logic 
reversing switch of the same type as for the write system, whose elements 
are transistors T.sub.8, T.sub.9, resistors Z.sub.4, Z.sub.5 and diode 
d.sub.A2, These elements are interconnected in the manner shown in FIG. 9. 
In the case of writing of state "0", the situation is as represented in 
Table II at the end of the description. 
In the first case considered (1), field effect transistors T.sub.6, T.sub.5 
and T.sub.4 are conductive. V.sub.D4 is brought to low levels: the sum of 
the failure voltage drops of transistors T.sub.6, T.sub.5, T.sub.4 with a 
current i.sub.T.sbsb.6 exceeding the current for maintaining state "1": 
i.sub.T.sbsb.6 -i.sub.T.sbsb.1. Thus, the cell is switched to state "0". 
In the second state (2), column Y is not addressed, transistors T.sub.4 and 
T.sub.6 are conductive and transistor T.sub.5 blocked. 
In the third considered case (3), line X is not addressed, transistors 
T.sub.5 and T.sub.6 are conductive and transistor T.sub.4 blocked. 
In these two latter cases the memory cell is not addressed. Current 
i.sub.T.sbsb.4 is equal to the sum of currents below current 
i.sub.T.sbsb.3 -i.sub.T.sbsb.1 : i.sub.T.sbsb.5 (o) and i.sub.T.sbsb.6 (o) 
being the stray currents in transistors T.sub.5 and T.sub.6 when they are 
blocked, thus the cell remains in a stable state. 
In the fourth case reading of the memory cell takes place with transistors 
T.sub.4 and T.sub.5 conductive with transistor T.sub.6 blocked. The stray 
currents are too low to change the state of the cell. 
Therefore the conditions for switching to "0" are: 
EQU V.sub.D.sbsb.4 &lt;V.sub.D.sbsb.4 (S) 
(V.sub.D.sbsb.4 being the voltage at point D.sub.4 and V.sub.D.sbsb.4 (S) 
being the threshold voltage at the same point) and 
EQU i.sub.T.sbsb.4 &gt;i.sub.T.sbsb.3 -i.sub.T.sbsb.1 
In the case of the writing of state "1", the position is as represented in 
Table III at the end of the description. 
Consideration will be given to the same four states as those studied 
hereinbefore in connection with the writing of state "0". 
In the first considered case (1), field effect transistors T.sub.6, 
T.sub.5, T.sub.4 are conductive while D.sub.4 is forced to high level with 
a current i.sub.T.sbsb.6 +i.sub.G.sbsb.4 exceeding the current 
i.sub.T.sbsb.1 for maintaining in state "0". Thus, the cell switches to 
state "1". 
In the second case (2) and third case (3), the unaddressed memory cells 
have remained stable, because the stray currents are low compared with 
i.sub.T.sbsb.1. In the fourth case (4), the reading cell remains stable 
for the same reason. 
The conditions for forcing to "1" are consequently: 
EQU V.sub.D.sbsb.4 &gt;V.sub.D.sbsb.4 (S) 
(V.sub.D.sbsb.4 being the voltage at point D.sub.4 and V.sub.D.sbsb.4 (S) 
the threshold voltage at the same point) and i.sub.T.sbsb.4 
&gt;i.sub.T.sbsb.1 
The order of magnitude of these levels is as follows: 
The reading amplifier detects levels "0" and "1", as a function of whether 
V.sub.G.sbsb.8 assumes voltages 0 or V.sub.OS. Thus, 
EQU V.sub.G.sbsb.8 =V.sub.D.sbsb.4 -V.sub.S.sbsb.7 -V.sub.OS 
This leads to the following conditions: 
##EQU1## 
These levels show that the cell is very stable and has a considerable 
immunity to noise. 
In summarizing, the different elements of the static memory described here 
have the characteristics shown in Table IV at the end of the description. 
As level V.sub.D.sbsb.2 is a following level as a function of the levels of 
the load up to 2 v (V.sub.D.sbsb.3 follows up to 3 v). 
Level F is a floating level. The single supply voltage is equal to 3 v. 
The organization of the memory is shown in FIG. 10. The cells are grouped 
into p rows X and q columns Y. The rows group gates G.sub.4 and the 
columns group sources S.sub.4, G.sub.4 and S.sub.4 being the grids and the 
sources of transistors T.sub.4 of each cell. 
Each row is controlled by an addressing gate X. Access is obtained to each 
column by a field effect transistor T.sub.5, whose gate is controlled by 
an addressing gate Y. It is also possible to replace transistors T.sub.4 
and T.sub.5 corresponding to each cell by bigate transistors, each first 
gate being connected to the addressing row and each second gate to the 
addressing column in question. 
The sources of field effect transistors T.sub.5 are connected on the one 
hand to drain D.sub.6 of field effect transistor T.sub.6, which separates 
the access from the data input E and from the input of reading amplifier 
21. Gate G.sub.6 is controlled by the aforementioned read-write system 20. 
Gates X and Y are controlled by the half-control circuits X and Y. 
The example of a 256 bit memory organized into 8 columns Y and 32 rows X is 
given in the following Table V. It is therefore possible to obtain a 256 
bit memory in a surface area of 1 mm.sup.2. On average the consumption is 
100 .mu.W, so that the total consumption is 30 mW. 
As a function of the orders of magnitude, consideration can be given to the 
production of 1024 bit memories in 2.times.2 mm.sup.2 areas with a 
consumption of only 120 mW. The access speed with respect to these 
memories can be below 1 nanosecond. 
TABLE I 
__________________________________________________________________________ 
Logic State 
V.sub.G.sbsb.2 
V.sub.G.sbsb.3 
V.sub.D.sbsb.4 
V.sub.GS.sbsb.2 
V.sub.Gs.sbsb.3 
__________________________________________________________________________ 
"0" 2V.sub.OS 
V.sub.OS + V.sub.d.sbsb.1 + V.sub.d.sbsb.2 
V.sub.OS + V.sub.d.sbsb.1 
V.sub.OS - V.sub.d.sbsb.1 
V.sub.d.sbsb.2 - V.sub.OS 
"1" 2V.sub.OS 
+V V - V.sub.S.sbsb.3 - V.sub.OS 
3V.sub.OS + V.sub.S.sbsb.3 - V 
V.sub.S.sbsb.3 
__________________________________________________________________________ 
TABLE II 
__________________________________________________________________________ 
V.sub.E 
V.sub.G.sbsb.6 
V.sub.G.sbsb.5 
V.sub.G.sbsb.4 
V.sub.D.sbsb.4 
i.sub.T.sbsb.4 
Case 
__________________________________________________________________________ 
0 V.sub.OS 
V.sub.OS + V.sub.d.sbsb.6 
V.sub.OS + V.sub.d.sbsb.6 + V.sub.d.sbsb.5 
V.sub.d.sbsb.6 + V.sub.d.sbsb.5 + V.sub.d.sbsb.4 
i.sub.T.sbsb.6 + i.sub.G.sbsb.4 
1 
0 V.sub.OS 
V.sub.d.sbsb.11 
V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 
i.sub.T.sbsb.5 (0) + i.sub.G.sbsb.4 
2 
0 V.sub.OS 
V.sub.OS + V.sub.d.sbsb.6 
V.sub.d.sbsb.10 
V.sub.D.sbsb.4 
0 3 
0 0 V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 
i.sub.T.sbsb.6 (0) + i.sub.G.sbsb.4 
4 
__________________________________________________________________________ 
TABLE III 
__________________________________________________________________________ 
V.sub.E V.sub.G.sbsb.6 
V.sub.G.sbsb.5 
V.sub.G.sbsb.4 
V.sub.D.sbsb.4 
i.sub.T.sbsb.4 
Case 
__________________________________________________________________________ 
V - V.sub.S.sbsb.15 - V.sub.OS 
V - V.sub.S.sbsb.13 - V.sub.OS 
V.sub.G.sbsb.4 + V.sub.d.sbsb.4 
V.sub.D.sbsb.4 + V.sub.OS 
V.sub.E - V.sub.d.sbsb.6 - V.sub.d.sbsb.5 - 
V.sub.d.sbsb.4 
I.sub.T.sbsb.6 
+ i.sub.G.sbsb.4 
1 
V - V.sub.S.sbsb.15 - V.sub.OS 
V - V.sub.S.sbsb.13 - V.sub.OS 
V.sub.d.sbsb.11 
V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 
i.sub.G.sbsb.4 
2 
V - V.sub.S.sbsb.15 - V.sub.OS 
V - V.sub.S.sbsb.13 - V.sub.OS 
V.sub.E + V.sub.OS 
V.sub.d.sbsb.10 
V.sub.D.sbsb.4 
0 3 
V - V.sub.S.sbsb.15 - V.sub.OS 
0 V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 + V.sub.OS 
V.sub.D.sbsb.4 
i.sub.G.sbsb.4 
4 
__________________________________________________________________________ 
TABLE IV 
__________________________________________________________________________ 
Output 
Thresh- Input 
Element 
Type High 
old Low 
High 
Low 
__________________________________________________________________________ 
Memory 
Bistable 
2 1.2 0.8 
V.sub.D.sbsb.3 
0.2 
cell flip-flop 
Gate X 
Simple re- 
V.sub.D.sbsb.3 
0.2 
1.4 
F 
versing 
switch 
Gate Y 
Simple V.sub.D.sbsb.3 
0.2 
1.4 
F 
reversing 
switch 
Half- Double 0.7 0 0.7 
0 
control 
reversing 
1.4 F 
circuit 
switch + 
X,Y double 
Memory output 
input Read- Double V.sub.D.sbsb.2 
0 0.7 
0 
controls 
write reversing 
selection 
switch 
Input Double 2 0 0.7 
0 
selection 
reversing 
switch 
Reading 
Following 
V.sub.D.sbsb.2 
0 2 0.8 
amplifier 
circuit + 
Output double 
reversing 
switch 
__________________________________________________________________________ 
TABLE V 
______________________________________ 
Unitary average 
Element Number surface area 
______________________________________ 
Cell 256 50 .times. 50 um.sup.2 
Gate X 32 -- 
Half-control 5 .times. 2 = 10 
-- 
circuit X 
Gate Y 8 -- 
Half-control 3 .times. 2 = 6 
-- 
circuit Y 
Read-write 1 -- 
selector 
Data input 1 -- 
selector 
Reading amplifier 
1 -- 
Total 315 O.75 mm.sup.2 
______________________________________