High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same

A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X−1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.

TECHNICAL FIELD

The present disclosure relates to memory design for semiconductor devices. The present disclosure is particularly applicable to spin-transfer torque magnetoresistive random-access memory (STT-MRAM).

BACKGROUND

Cell scaling is of critical importance to continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. One area of increasing demand is high-density STT-MRAM. For simplicity, density is referred herein as linear density by default. If required, areal density can be computed by squaring the linear density.

A known solution to scale and, therefore, double the density of a STT-MRAM structure is to divide the magnetic tunnel junction (MTJ) pitch (P) of a two-dimensional (2D) array of MTJs in half (P/2), e.g., scaling between a 1 gigabit (1 Gb) 28 nanometer (nm) STT-MRAM and a 2 Gb 14 nm STT-MRAM, as depicted inFIGS. 1 and 2, respectively.

Referring toFIG. 1(a cross-sectional view), a known 1 Gb (28 nm) STT-MRAM structure100includes a silicon (Si) substrate101with an active area (RX) (not shown for illustrative convenience) and an array of interconnect structures103and105. In this instance, a bottom portion of each interconnect structure103and105includes a source/drain contact (CA)107, a metal layer109(M1), a via111(V1), a metal layer113(M2), a via115(V2), and a metal layer117(M3). The STT-MRAM structure100also includes a pair of word line (WL)119over the Si substrate101between the interconnect structures103and105, a transistor common121, and a WL contact123, e.g., W0. Further, the STT-MRAM structure100includes a MTJ structure125made up of a bottom via127, a MTJ stack129, and a top via131on each of the interconnect stacks103and105, and a bit line133over the Si substrate101and on the MTJ structures125. The P of the STT-MRAM100is represented by the arrow135.

Referring toFIG. 2(a cross-sectional view) a known 2 Gb (14 nm) STT-MRAM structure200includes a Si substrate201with an RX (not shown for illustrative convenience) and an array of interconnect structures203,205,207, and209. In this instance, a bottom portion of each interconnect structure203,205,207, and209includes a CA211, a metal layer213(M1), a via215(V1), a metal layer217(M2), a via219(V2), and a metal layer221(M3). The STT-MRAM structure200also includes a pair of WL223over the Si substrate201between each pair of interconnect structures, e.g.,203and205, a transistor common225, and a WL contact227, e.g., WL2, WL1, WL0. Further, the STT-MRAM structure200includes a MTJ structure229made up of a bottom via231, a MTJ stack233, and a top via235on each of the interconnect stacks203,205,207, and209, and a bit line237over the Si substrate201and on each of the MTJ structures229. The P of the STT-MRAM structure200is represented by the arrow239. However, this known solution is problematic due to the process challenges that result from dividing the P133ofFIG. 1in half in the STT-MRAM structure200such as MTJ etching leading to partial shorts; degradation in bit error rate (BER) yield; patterning complexities; dielectric gap-fill issues; inability to scale at advanced technology nodes, e.g., 7 nm; capital and tool costs; and multiple patterning costs.

A need therefore exists for methodology enabling formation of a high-density STT-MRAM without scaling the MTJ pitch or the process challenges associated with the known solution and the resulting device.

SUMMARY

An aspect of the present disclosure is a scalable method of forming an integrated high-density STT-MRAM with a three-dimensional (3D) array of multi-level MTJs.

Another aspect of the present disclosure is a 2 Gb (14 nm) high-density STT-MRAM device with a 3D array of multi-level MTJs.

A further aspect of the present disclosure is a 4 Gb (7 nm) high-density STT-MRAM device with a 3D array of multi-level MTJs.

According to the present disclosure, some technical effects may be achieved in part by a method including: providing a Si substrate of an X-density having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X−1) defines a number of interconnect stacks between the first interconnect stack and the second interconnect stack; forming a via with a height of the MTJ structure on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.

Aspects of the present disclosure include forming the MTJ structure by: forming a bottom via on each of the first interconnect stack and the second interconnect stack; forming a MTJ stack on the bottom via; and forming a top via on the MTJ stack. Other aspects include forming the bottom via, the top via, the via, and the metal layer of copper (Cu), tungsten (W), or cobalt (Co). Further aspects include connecting the bit line to each MTJ structure by: forming a second via of Cu, W, or Co between the bit line and the metal layer. Another aspect includes connecting the bit line to each MTJ structure by: forming a second via of Cu, W, or Co with a height of the MTJ structure on each metal layer; forming a second metal layer of Cu, W, or Co on each second via; and repeating the forming of the second via and the second metal layer until each second via is on the level of the MTJ structure that equals X, only forming the second via at that level. Additional aspects include connecting the bit line to each MTJ structure by: forming a through via contact of Cu, W, or Co between each metal layer and the bit line.

Another aspect of the present disclosure is a device including: an array of interconnect stacks, laterally separated, over a Si substrate of a STT-MRAM; a first MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein the first interconnect stack and the second interconnect stack are separated by a third interconnect stack; a via with a height of the first MTJ structure on each of the third interconnect stack and a fourth interconnect stack, wherein the third interconnect stack and the fourth interconnect stack are separated by the second interconnect stack; a metal layer on each first MTJ structure and via; a second MTJ structure on the metal layer of each of the third interconnect stack and the fourth interconnect stack, wherein the third interconnect stack and the fourth interconnect stack are separated by the second interconnect stack; a second via with a height of the second MTJ structure on the metal layer of each of the first interconnect stack and the second interconnect stack; and a bit line over the substrate and on the second via and the second MTJ structure.

Aspects of the device include a pair of word lines, laterally separated, over the Si substrate between a pair of interconnect stacks of the array; a transistor common over the Si substrate between the pair of word lines; and a word line contact over the transistor common. Other aspects include a bottom portion of the interconnect stack including: a CA over the substrate; a second metal layer over the CA; a third via over the second metal layer; a third metal layer over the third via; a fourth via over the third metal layer; and a fourth metal layer over the fourth via. Further aspects include the first MTJ structure and the second MTJ structure each including: a bottom via on the fourth metal layer of each of the first interconnect stack and the second interconnect stack and on the metal layer of each of the third interconnect stack and the fourth interconnect stack, respectively; a MTJ stack on the bottom via; and a top via on the MTJ stack. Additional aspects include the via, the metal layer, the second via, the second metal layer, the third via, the third metal layer, the fourth via, the fourth metal layer, the bottom via, and the top via being Cu, W, or Co. Another aspect includes the device being a 2 Gb integrated high-density 3D STT-MRAM structure with a 3D array of multi-level MTJ interconnect structures.

A further aspect of the present disclosure is a device including: an array of a first interconnect stack through an eighth interconnect stack, laterally separated, over a Si substrate of a STT-MRAM; a first MTJ structure on each of the first interconnect stack and the fifth interconnect stack; a first via with a height of the first MTJ structure on each of a second interconnect stack, a third interconnect stack, a fourth interconnect stack, a sixth interconnect stack, a seventh interconnect stack, and the eighth interconnect stack; a first metal layer on each first MTJ structure and first via; a second MTJ structure on the first metal layer of each of the second interconnect stack and the sixth interconnect stack; a second via with a height of the second MTJ structure on each of the third interconnect stack, the fourth interconnect stack, the seventh interconnect stack, and the eighth interconnect stack; a second metal layer on each second MTJ structure and second via; a third MTJ structure on the second metal layer of each of the third interconnect stack and the seventh interconnect stack; a third via with a height of the third MTJ structure on each of the fourth interconnect stack and the eighth interconnect stack; a third metal layer on each third MTJ structure and third via; a fourth MTJ structure on the third metal layer of each of the fourth interconnect stack and the eighth interconnect stack; and a bit line over the substrate and on to the fourth pair of MTJ structures.

Aspects of the device include a pair of word lines, laterally separated, over the Si substrate between a pair of interconnect stacks of the array; a transistor common over the Si substrate between the pair of word lines; and a word line contact over the transistor common. Other aspects include a bottom portion of the interconnect stack further including: a CA over the substrate; a fourth metal layer over the CA; a fourth via over the fourth metal layer; a fifth metal layer over the fourth via; a sixth via over the fifth metal layer; and a six metal layer over the six via. Further aspects include each of the first MTJ structure, the second MTJ structure, the third MTJ structure, and the fourth MTJ structure including: a bottom via on the sixth metal layer, the first metal layer, the second metal layer, and the third metal layer, respectively; a MTJ stack on the bottom via; and a top via on the MTJ stack. Additional aspects include the first via, the first metal layer, the second via, the second metal layer, the third via, the third metal layer, the fourth via, the fourth metal layer, the fifth via, the fifth metal layer, the sixth via, the sixth metal layer, the bottom via, and the top via being Cu, W, or Co. Another aspect includes a fourth via with a height of the second MTJ structure on the first metal layer of each of the first interconnect stack and the fifth interconnect stack; a fourth metal layer on the fourth via; a fifth via with a height of the third MTJ structure on the fourth metal layer of each of the first interconnect stack and the fifth interconnect stack and on the second metal layer of each of the second interconnect stack and the sixth interconnect stack; a fifth metal layer on the fifth via; and a sixth via with a height of the fourth MTJ structure on the fifth metal layer of each of the first interconnect stack, the second interconnect stack, fifth interconnect stack, and sixth interconnect stack and on the third metal layer of each of the third interconnect stack, the fourth interconnect stack, and the seventh interconnect stack, wherein the fourth via, the fourth metal layer, the fifth via, the fifth metal layer, and the sixth via are Cu, W, or Co. Additional aspects include a through via contact on the first metal layer of each of the first interconnect stack and the fifth interconnect stack, on the second metal layer of each of the second interconnect stack and the sixth interconnect stack, and on the third metal layer of each of the third interconnect stack and the seventh interconnect stack, wherein the through via contact is Cu, W, or Co. Other aspects include the device being a 4 Gb integrated high-density 3D STT-MRAM structure with a 3D array of multi-level MTJ interconnect structures.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problems of MTJ pitch scaling limitations; MTJ etching/partial shorts; degraded BER yield; patterning complexities; dielectric gap-fill issues; inability to scale at advanced technology nodes; capital and tool costs; and multiple patterning costs attendant upon forming and scaling a high-density STT-MRAM. The problems are solved, inter alia, by forming an integrated high-density 3D STT-MRAM structure with a 3D array of multi-level MTJ interconnect structures.

Methodology in accordance with embodiments of the present disclosure includes providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks. A level of a MTJ structure is formed on each of a first interconnect stack and a second interconnect stack, wherein (X−1) defines a number of interconnect stacks between the first interconnect stack and the second interconnect stack. A via is formed with a height of the MTJ structure on each interconnect stack without a MTJ structure. A metal layer is formed on each MTJ structure and via on the level. The forming of the MTJ structure, the via, and the metal layer is repeated one interconnect stack laterally shifted until the level of the MTJ structure equals X, only the MTJ structure is formed at that level. A bit line is formed over the substrate; and the bit line is connected to each MTJ structure.

FIGS. 3 through 6schematically illustrate cross-sectional views of a process flow for forming a 2 Gb (14 nm) integrated high-density 3D STT-MRAM structure with a 3D array of multi-level MTJ interconnect structures, in accordance with an exemplary embodiment. Referring toFIG. 3, a Si substrate301of a STT-MRAM structure300is provided with an RX (not shown for illustrative convenience) and an array of interconnect structures303,305,307, and309. In this instance, a bottom portion of each interconnect structure303,305,307, and309includes a CA311, a metal layer313(M1), a via315(V1), a metal layer317(M2), a via319(V2), and a metal layer321(M3). The Si substrate301is also provided with a pair of WL323over the Si substrate301between a pair of interconnect structures, e.g.,303and305, a transistor common325, and a WL contact327, e.g., WL2, WL1, WL0. In one instance, the interconnect stacks303and305may be formed over positive n-type (N+) drains and the transistor common325may be formed over a N+ shared source (both not shown for illustrative convenience). The metal layers313,317, and321, the vias315and319, and the WL contact327may be formed, e.g., of Cu, W, or Co.

Referring toFIG. 4, a MTJ structure401is formed on each of the interconnect stacks303and307. Each MTJ structure401includes, e.g., a bottom via405, a MTJ stack407, and a top via409. The bottom via405and the top via409may be formed, e.g., of Cu, W, or Co. In this instance, the density (X) of the STT-MRAM300is 2 Gb (14 nm). Therefore, the MTJ stack407P (as depicted by the arrow403) is equal to the distance between two interconnect stacks separated by X−1 interconnect stacks. A via501with a height of the MTJ structure401is then formed on each interconnect stack without a MTJ structure401, e.g., interconnect stacks305and309, and a metal layer503is formed on each MTJ structure401and via501, as depicted inFIG. 5.

Thereafter, the forming of the MTJ structure401, the via501, and the metal layer503is repeated one interconnect structure laterally shifted (305) while maintaining the same P403until the level of the MTJ structure401equal the X−density of the STT-MRAM structure300, as depicted inFIG. 6. In this instance, only 2 levels of MTJ structures401are required. Referring toFIG. 7, a bit line701is formed over the Si substrate301and a via703is formed, e.g., of Cu, W, or Co, between the bit line701and the metal layer503, connecting the bit line701with each MTJ structure401. Consequently, whereas the known solution described above with respect toFIGS. 1 and 2divides the MTJ stack P in half (P/2) when scaling between a 1 Gb (28 nm) STT-MRAM structure (FIG. 1) and 2 Gb (14 nm) STT-MRAM structure (FIG. 2), the resultant 2 Gb (14 nm) STT-MRAM structure ofFIG. 7maintains the same P as the 1 Gb (28 nm) STT-MRAM structure ofFIG. 1.

FIGS. 8 through 13schematically illustrate cross-sectional views of a process flow for forming a 4 Gb 7 nm integrated high-density 3D STT-MRAM structure with a 3D array of multi-level MTJ interconnect structures, in accordance with an exemplary embodiment. The process flow described with respect toFIGS. 8 through 13is almost identical to the process flow described with respect toFIGS. 3 through 7because the process flow may be scaled without modifying the MTJ stack P. The only difference is that the density of the STT-MRAM is greater in this instance than the density of the STT-MRAM ofFIGS. 3 through 7, e.g., 4 Gb (7 nm) vs. 2 Gb (14 nm), and, therefore, the number of levels of the MTJ structures must be increased accordingly, e.g., 4 levels vs. 2 levels.

Referring toFIG. 8, a Si substrate801of a STT-MRAM structure800is provided with an RX (not shown for illustrative convenience) and an array of interconnect structures803,805,807,809,811,813,815, and817. Similar to the device ofFIG. 3, a bottom portion of each interconnect structure803,805,807,809,811,813,815, and817may include a CA819, a metal layer821(M1), a via823(V1), a metal layer825(M2), a via827(V2), and a metal layer829(M3). The Si substrate801is also provided with a pair of WL831between a pair of interconnect structures, e.g.,803and805, over the Si substrate601, a transistor common833, and a WL contact835, e.g., WL2, WL1, WL0, etc. In one instance, the interconnect stack, e.g.,803, may be formed over N+ drains and the transistor common833may be formed over a N+ shared source (both not shown for illustrative convenience). The metal layers821,825, and829, the vias823and827, and the WL contact831may be formed, e.g., of Cu, W, or Co.

A MTJ structure901is formed on each of the interconnect stacks803and811(level 1), as depicted inFIG. 9. Each MTJ structure901includes, e.g., a bottom via905, a MTJ stack907, and a top via909. The bottom via905and the top via909may be formed, e.g., of Cu, W, or Co. In this instance, the density (X) of the STT-MRAM structure800is 4 Gb (7 nm). Therefore, the MTJ stack907P (as depicted by the arrow903) is equal to the distance between two interconnect stacks separated by X−1 interconnect stacks. A via1001with a height of the MTJ structure901is then formed on each interconnect stack without a MTJ structure901, e.g., interconnect stacks805,807,809,813,815, and817and a metal layer1003is formed on each MTJ structure901and via1001, as depicted inFIG. 10.

Referring toFIG. 11, the forming of the MTJ structure901, the via1001, and the metal layer1003as described with respect toFIG. 10is repeated laterally shifted one interconnect stack such that the next level of MTJ structures901(level 2) is formed on the interconnect stacks805and813. In one instance, a via1001and a metal layer1003may also be formed on the metal layer1003of the interconnect stacks803and811, as depicted inFIG. 14A. Alternatively, the top of the interconnect stacks803and811(above the metal layer1003) may remain open until the subsequent formation of a through via contact, as depicted inFIG. 14B.

As described above, the forming of the MTJ structure901, the via1001, and the metal layer1003is repeated laterally shifted one interconnect stack until the level of the MTJ structure901equals the X-density of the STT-MRAM structure800, e.g., 4 Gb. Therefore, the forming of the MTJ structure901, the via1001, and the metal layer1003as described with respect toFIG. 10is once again repeated laterally shifted one interconnect stack such that the next level (level 3) of MTJ structures901is formed on the interconnect stacks807and815, as depicted inFIG. 12. In one instance, a via1001and a metal layer1003may also be formed on the metal layer1003of the interconnect stacks803,805,811, and813, as depicted inFIG. 14A. Alternatively, the top of the interconnect stacks803,805,811, and813(above the metal layer1003) may remain open until the subsequent formation of a through via contact, as depicted inFIG. 14B.

Referring toFIG. 13, the forming of the MTJ structure901, the via1001, and the metal layer1003as described with respect toFIG. 10is further repeated laterally shifted one interconnect stack such that the next level of MTJ structures901(level 4) is formed on the interconnect stacks809and817; however, in this instance, because there are now 4 levels of MTJ structures901, only the MTJ structure901is formed at this level. In one instance, a via1001may be formed on the metal layer1003of the interconnect stacks803,805,807,811,813, and815, as depicted inFIG. 14A. Alternatively, the top of the interconnect stacks803,805,807,811,813, and815(above the metal layer1003) may remain open until the subsequent formation of a through via contact, as depicted inFIG. 14B.

FIGS. 14A and 14Bschematically illustrate cross-sectional views of the resultant 3D STT-MRAM structure ofFIGS. 8 through 13, in accordance with an exemplary embodiment. Referring toFIG. 14A, in one instance, as partially described above, the forming of the via1001and the metal layer1003is repeated in synch with the formation of each level of MTJ structures901until a via1001is formed on each interconnect structure on the same level as the last level of MTJ structures901, e.g., level 4. Consequently, 3 vias1001and 2 metal layers1003would be formed on each of the interconnect stacks803and811; 2 vias1001and 1 metal layer1003would be formed on each of the interconnect stacks805and813, and 1 via1001would be formed on each of the interconnect stacks807and815. The bit line1401is then formed over the substrate801and on the vias1001and MTJ structures901(level 4) connecting the bit line1401to each MTJ structure901.

Alternatively, as partially described above, a through via contact1421can be formed on the metal layer1003of each of the interconnect stacks803,805,807,811,813, and815up to an upper surface of the MTJ structure901on the last level of the MTJ structures901, e.g., level 4, as depicted inFIG. 14B. Thereafter, the bit line1401is formed over the substrate801and on the through via contacts1221and the MTJ structures901(level 4) connecting the bit line1401to each MTJ structure901. Consequently, although the density of the resultant STT-MRAM structure ofFIG. 7was scaled from 2 Gb (14 nm) to 4 Gb (7 m) inFIGS. 14A and 14B, the MTJ stack P remained the same.

The embodiments of the present disclosure can achieve several technical effects including forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJ interconnect structures, mitigating process issues such as MTJ pitch scaling limitation, etching, patterning, and dielectric gap-fill issues, etc. associated with known solutions, a faster time to market, and eliminating the need for new tools. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types of semiconductor devices including STT-MRAM.