SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes: a substrate; a body recess in the substrate; a body dielectric layer over the body recess; an active layer extending in a direction parallel to the substrate over the substrate; a contact node over an end portion of the active layer and perpendicular to the substrate; and a conductive line coupled to the contact node and extended perpendicular to the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2022-0017586, filed on Feb. 10, 2022, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a three-dimensional structure and a method for fabricating the same.

2. Description of the Related Art

The size of a memory cell is being reduced continuously to increase the net die of a memory device. As the size of memory cells is miniaturized, it is required to reduce parasitic capacitance Cb and increase the capacitance as well. However, it is difficult to increase the net die due to the structural limitation of the memory cells.

Recently, three-dimensional semiconductor memory devices including memory cells have been suggested.

SUMMARY

Embodiments of the present invention are directed to a semiconductor device including highly integrated memory cells, and a method for fabricating the same.

In accordance with an embodiment of the present invention, a semiconductor device includes: a substrate; a body recess in the substrate; a body dielectric layer over the body recess; an active layer extending in a direction parallel to the substrate over the substrate; a contact node over an end portion of the active layer and perpendicular to the substrate; and a conductive line coupled to the contact node and extended perpendicular to the substrate.

In accordance with another embodiment of the present invention, a semiconductor device includes: a body recess in a substrate; a body dielectric layer over the body recess; a transistor extending in a direction parallel to the substrate over the substrate and including an active layer having a first end portion and a second end portion; a bit line contact node on a sidewall, an upper surface, and a lower surface of the first end portion; a bit line coupled to the bit line contact node and extended perpendicular to the substrate; a storage contact node on a sidewall, an upper surface, and a lower surface of the second end portion; and a capacitor coupled to the second end portion and the storage contact node.

In accordance with another embodiment of the present invention, a semiconductor device includes: a substrate including a peripheral circuit portion; a memory cell array including a conductive line including a contact pad side and a bonding pad side; a first bonding pad coupled to the bonding pad side of the conductive line; a second bonding pad disposed over the peripheral circuit portion and coupled to the first bonding pad; a body dielectric layer covering the contact pad side of the conductive line; and a conductive pad passing through the body dielectric layer and coupled to the contact pad side of the conductive line.

In accordance with yet another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a stack body including dielectric layers over a substrate, first sacrificial layers and second sacrificial layers between the dielectric layers, and active layers between the first sacrificial layers and the second sacrificial layers; forming an opening by etching the stack body; etching the substrate through the opening to form a body recess; forming a body dielectric layer over the body recess; replacing the first sacrificial layers and the second sacrificial layers with double word lines; exposing end portions of the active layers; and forming contact nodes coupled to the exposed end portions.

In accordance with still another embodiment of the present invention, a method for fabricating a semiconductor device includes: forming a memory cell array including a first substrate including a body dielectric layer and a vertical bit line including a contact pad side covered by the body dielectric layer and a bonding pad side disposed opposite to the contact pad side; forming a second substrate including a peripheral circuit portion; turning over the first substrate and bonding the bonding pad side of the vertical bit line to the peripheral circuit portion; selectively removing the first substrate; and forming a bit line pad coupled to a contact pad side of the vertical bit line. The body dielectric layer may include silicon oxide that covers the contact pad side of the vertical bit line.

DETAILED DESCRIPTION

According to the following embodiment of the present invention, memory cell density may be increased and parasitic capacitance may be reduced by vertically stacking memory cells.

FIG.1is a schematic perspective view illustrating a semiconductor device in accordance with an embodiment of the present invention.FIG.2is a schematic cross-sectional view illustrating a memory cell shown inFIG.1.

Referring toFIGS.1and2, the semiconductor device100in accordance with the embodiments of the present invention may include memory cells MC. Each of the memory cells MC may include a bit line BL, a transistor TR, and a capacitor CAP. The transistor TR may include active layer ACT and double word line DWL, and the double word line DWL may include first and second word lines WL1and WL2. The first word line WL1and the second word line WL2are on opposite sides of the active layer ACT. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN.

The bit line BL may be a pillar extending along a first direction D1. The active layer ACT may be a bar extending along a second direction D2perpendicular to the first direction D1. The double word line DWL may be lines extending in a third direction D3perpendicular to the first and second directions D1and D2. The plate node PN of the capacitor CAP may be coupled to a plate line PL.

The bit line BL may be vertically oriented in a first direction D1. The bit line BL may be referred to as a vertically oriented bit line or a pillar-type bit line. The bit line BL may include a conductive material. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. In an embodiment, the bit line BL may include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon doped with an N-type impurity or titanium nitride (TiN). The bit line BL may include a TiN/W stack including titanium nitride and tungsten over titanium nitride.

The double word line DWL may extend in a third direction D3, and the active layer ACT may laterally extend in a second direction D2. The active layer ACT may be laterally arranged in the second direction D2from the bit line BL. The double word line DWL may include a pair of word lines, a first word line WL1and a second word line WL2. The first word line WL1and the second word line WL2may be disposed along the first direction D1facing each other with the active layer ACT interposed therebetween. A gate dielectric layer GD may be formed on the surfaces of the active layer ACT perpendicular to the first direction D1.

The active layer ACT may include a semiconductor material or an oxide semiconductor material. For example, the active layer ACT may include monocrystalline silicon, germanium, silicon germanium, indium gallium zinc oxide (IGZO), or combinations thereof. The active layer ACT may include polysilicon or monocrystalline silicon. The active layer ACT may include a channel CH, a first source/drain region SR between the channel CH and a bit line BL, and a second source/drain region DR between the channel CH and a capacitor CAP. The channel CH may be defined between the first source/drain region SR and the second source/drain region DR.

The first source/drain region SR and the second source/drain region DR may be doped with impurities (or referred to as dopants) of the same conductivity type. The first source/drain region SR and the second source/drain region DR may be doped with an N-type impurity or a P-type impurity. The first source/drain region SR and the second source/drain region DR may include at least one impurity selected among arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source/drain region SR may contact the bit line BL, and a second side of the first source/drain region SR may contact the channel CH. A first side of the second source/drain region DR may contact the storage node SN, and a second side of the second source/drain region DR may contact the channel CH. A length of the channel CH along the second direction D2may be smaller than a length of the first and second source/drain regions SR and DR along the second direction D2. Alternatively, the length of the channel CH in the second direction D2may be greater than the lengths of the first and second source/drain regions SR and DR in the second direction D2.

The transistor TR may be a cell transistor and it may have a double word line DWL. In the double word line DWL, the first word line WL1and the second word line WL2may have the same or different potentials (or referred to as voltages or driving voltages). For example, the first word line WL1and the second word line WL2may form a pair, and the same word line driving voltage may be applied to the first word line WL1and the second word line WL2. The memory cell MC may have one or more pair(s) of word lines. For example, the memory cell MC may include a double word line DWL with the first word lines WL1and the second word line WL2disposed adjacent to one channel CH.

According to another embodiment of the present invention, the first word line WL1and the second word line WL2may have different potentials. For example, a word line driving voltage may be applied to the first word line WL1, and a ground voltage may be applied to the second word line WL2. The second word line WL2with the ground voltage may be referred to as a back word line or a shield word line. According to another embodiment of the present invention, the ground voltage may be applied to the first word line WL1, and the word line driving voltage may be applied to the second word line WL2.

The active layer ACT may have a smaller thickness than those of the first and second word lines WL1and WL2. In other words, the vertical thickness of the active layer ACT along the first direction D1may be smaller than the vertical thickness of each of the first and second word lines WL1and WL2along the first direction D1. Such a thin active layer ACT may be referred to as a thin-body active layer. The thin-body active layer ACT may include a thin-body channel CH, and the thin-body channel CH may have a thickness of approximately 10 nm or less. According to another embodiment of the present invention, the channel CH may have the same vertical thickness along the first direction D1as those of the first and second word lines WL1and WL2.

The gate dielectric layer GD may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric material or combination thereof. The gate dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof.

The double word line DWL may include a metal, a metal mixture, a metal alloy, or a semiconductor material, or combinations thereof. The double word line DWL may include titanium nitride, tungsten, polysilicon, or combinations thereof. For example, the double word line DWL may include a TiN/W stack in which titanium nitride and tungsten are sequentially stacked. The double word line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or more.

The capacitor CAP may be disposed on the opposite side of the transistor TR with respect to the bit line BL along the second direction D2. The capacitor CAP may include a storage node SN that extends laterally from the active layer ACT along the second direction D2. The capacitor CAP may further include a dielectric layer DE and a plate node PN over the storage node SN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged laterally along the second direction D2. The storage node SN may have a cylindrical shape with an axis oriented along the second direction D2. The dielectric layer DE may conformally cover the cylindrical inner wall and the cylindrical outer wall of the storage node SN. The plate node PN may extend to the cylindrical inner wall and the cylindrical outer wall of the storage node SN over the dielectric layer DE. The plate node PN may be coupled to the plate line PL. The storage node SN may be electrically connected to the second source/drain region DR.

The storage node SN may have a three-dimensional structure, and the storage node SN of the three-dimensional structure may have a lateral three-dimensional structure which is oriented in the second direction D2. As an example of the three-dimensional structure, the storage node SN may have a cylinder shape. According to another embodiment of the present invention, the storage node SN may have a pillar shape or a pylinder shape. The pylinder shape may refer to a structure in which a pillar shape and a cylinder shape are merged.

The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride/tungsten (TiN/W) stack, a tungsten nitride/tungsten (WN/W) stack, or combinations thereof. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a stack of titanium nitride/silicon germanium/tungsten nitride (TiN/SiGe/WN). In the titanium nitride/silicon germanium/tungsten nitride (TiN/SiGe/WN) stack, silicon germanium may be a gap-filling material to fill the cylindrical interior of the storage node SN over the titanium nitride, and titanium nitride (TiN) may serve as a plate node PN of a capacitor CAP, and tungsten nitride may be a low-resistivity material.

The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of approximately 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of approximately 4 or more. The high-k material may have a dielectric constant of approximately 20 or more. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) strontium titanium oxide (SrTiO3), or combinations thereof. In an alternative embodiment, the dielectric layer DE may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

The dielectric layer DE may be formed of zirconium (Zr)-based oxide. The dielectric layer DE may have a stack structure including at least zirconium oxide (ZrO2). The stack structure including zirconium oxide (ZrO2) may include a ZA (ZrO2/Al2O3) stack or a ZAZ (ZrO2/Al2O3/ZrO2) stack. The ZA stack may include aluminum oxide (Al2O3) stacked over zirconium oxide (ZrO2). The ZAZ stack may include sequentially stacked zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2). The ZA stack and the ZAZ stack may be referred to as a zirconium oxide (ZrO2)-based layer. According to an alternative embodiment of the present invention, the dielectric layer DE may be formed of hafnium (Hf)-based oxide. The dielectric layer DE may have a stack structure including at least hafnium oxide (HfO2). The stack structure including hafnium oxide (HfO2) may include an HA (HfO2/Al2O3) stack or a HAH (HfO2/Al2O3/HfO2) stack. The HA stack may include aluminum oxide (Al2O3) stacked over hafnium oxide (HfO2). The HAH stack may include sequentially stacked hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2). The HA stack and the HAH stack may be referred to as a hafnium oxide (HfO2)-based layer. In the ZA stack, ZAZ stack, HA stack, and HAH stack, aluminum oxide (Al2O3) has a greater bandgap energy (which will be, hereinafter, simply referred to as bandgap) than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Accordingly, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material, where the high-bandgap material has a greater bandgap than the high-k material. The dielectric layer DE may include silicon oxide (SiO2) as a high bandgap material other than aluminum oxide (Al2O3). Leakage current may be suppressed due to the high bandgap material included in the dielectric layer DE. The high-bandgap material may be thinner than the high-k material. According to an alternative embodiment of the present invention, the dielectric layer DE may include a laminated structure of alternately stacked high-k material and high-bandgap material. For example, it may include a ZAZA (ZrO2/Al2O3/ZrO2/Al2O3) stack, a ZAZAZ (ZrO2/Al2O3/ZrO2/Al2O3/ZrO2) stack, a HAHA (HfO2/Al2O3/HfO2/Al2O3) stack, or a HAHAH (HfO2/Al2O3/HfO2/Al2O3/HfO2) stack. In the above laminated structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

According to an alternative embodiment of the present invention, the dielectric layer DE may include a stack structure, a laminated structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

According to an alternative embodiment of the present invention, the dielectric layer DE may include a ferroelectric material or an antiferroelectric material.

According to an alternative embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), niobium oxide, niobium nitride, or combinations thereof. The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

The capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material.

The capacitor CAP may be replaced with another data storage material. For example, the data storage material may be phase change materials, magnetic tunnel junctions (MTJ), or variable resistance materials.

A bit line contact node BLC may be formed between the first source/drain region SR of the active layer ACT and the bit line BL. A storage contact node SNC may be formed between the second source/drain region DR of the active layer ACT and the storage node SN of the capacitor CAP. The storage contact node SNC and the bit line contact node BLC may extend vertically along the first direction D1. The bit line contact node BLC and the storage contact node SNC may extend to adjacent end portions of the active layers ACT, thereby covering the upper and lower surfaces (surfaces perpendicular to the first direction D1) of the end portions of both sides of the active layers ACT. The bit line contact node BLC and the storage contact node SNC may have a height that fully covers the end portions of the active layer ACT. A combination of the bit line contact node BLC and the first source/drain region SR may form a T-shape in the planes perpendicular to the third direction D3. Similarly, the storage contact node SNC and the second source/drain region DR may form a T-shape in the planes perpendicular to the third direction D3. The bit line contact node BLC and the storage contact node SNC may cover portions of the adjacent surfaces of the active layer ACT perpendicular to the first direction D1. The bit line contact node BLC and the storage contact node SNC may be doped polysilicon. For example, the bit line contact node BLC and the storage contact node SNC may be polysilicon with doped N-type impurity such as phosphorous. The first and second source/drain regions SR and DR may include an impurity diffused from the bit line contact node BLC and the storage contact node SNC.

FIG.3is a schematic perspective view illustrating a semiconductor device in accordance with an alternative embodiment of the present invention.FIG.4is a schematic cross-sectional view illustrating the semiconductor device shown inFIG.3.

Referring toFIGS.3and4, the semiconductor device110may include a memory cell array MCA. A plurality of the memory cells MC shown inFIG.1may be arranged in the first to third directions D1, D2, and D3to form the memory cell array MCA shown inFIG.3. The memory cell array MCA may include a three-dimensional array of memory cells MC, and the three-dimensional memory cell array MCA may include a vertical memory cell array MCA_C and a lateral memory array MCA_R. The vertical memory cell array MCA_C refers to an array of memory cells MC that are vertically arranged along the first direction D1. The lateral memory cell array MCA_R may refer to an array of memory cells MC that are arranged laterally along the third direction D3. The vertical memory cell array MCA_C may be alternatively referred to as a column array of memory cells MC, and the lateral memory cell array MCA_R may be alternatively referred to as a row array of memory cells MC. The bit line BL may be vertically oriented along the first direction D1and coupled to the vertical memory cell array MCA_C, and the double word line DWL may be oriented laterally along the third direction D3and coupled to the lateral memory cell array MCA_R. The bit line BL coupled to the vertical memory cell array MCA_C may be referred to as a common bit line, and the vertical memory cell arrays MCA_C that are disposed adjacent to each other in the third direction D3may be coupled to different common bit lines. The double word line DWL coupled to the lateral memory cell array MCA_R may be referred to as a common double word line Common DWL, and the lateral memory cell arrays MCA_R that are disposed adjacent to each other in the first direction D1may be coupled to different common double word lines.

The memory cell array MCA may include a plurality of memory cells MC, and each memory cell MC may include a vertically oriented (along the first direction D1) bit line BL, a laterally oriented (along the second direction D2) active layer ACT, a double word line DWL, and a laterally oriented (along the second direction D2) capacitor CAP. For example,FIG.3illustrates a three-dimensional DRAM memory cell array including four memory cells MC.

The active layers ACT that are disposed adjacent to each other in the first direction D1may contact or share the same bit line BL. Active layers ACT that are disposed adjacent to each other in the third direction D3may contact or share the same double word line DWL. The capacitors CAP may be respectively coupled to the active layers ACT. The capacitors CAP may share one plate line PL. The individual active layers ACT may be thinner than the first and second word lines WL1and WL2of the double word line DWL.

In the memory cell array MCA, a plurality of double word lines DWL may be vertically stacked along the first direction D1. Each double word line DWL may include a pair of a first word line WL1and a second word line WL2. Between the first word line WL1and the second word line WL2of each double word line DWL, a plurality of active layers ACT may be laterally disposed and spaced apart from each other along the third direction D3. The channel CH of the active layer ACT may be disposed between the first word line WL1and the second word line WL2.

The semiconductor device110may further include a lower structure LS, and the lower structure LS may include a substrate or a peripheral circuit portion. The bit line BL of the memory cell array MCA may be oriented vertically along the first direction D1with respect to the surface of the lower structure LS, and the double word line DWL may be oriented parallel to the surface of the lower structure LS along the third direction D3.

When the lower structure LS includes the peripheral circuit portion, the peripheral circuit portion may be disposed lower than the memory cell array MCA along the first direction D1. This may be referred to as a COP (Cell over PERI) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell array MCA. The at least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, and the like. At least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistors (FinFET), and the like.

According to an alternative embodiment of the present invention, the peripheral circuit portion of the semiconductor device110may be disposed higher than that of the memory cell array MCA along the first direction D1. This may be referred to as a POC (PERI over Cell) structure.

FIG.5is a schematic cross-sectional view illustrating a semiconductor device in accordance with an alternative embodiment of the present invention.

Referring toFIG.5, the semiconductor device200may be similar to the memory cell array MCA_C ofFIG.4. Hereinafter, detailed descriptions of the constituent elements also appearing inFIG.4will be omitted.

The semiconductor device200may include a lower structure LS, a bit line BL’, a transistor TR, and a capacitor CAP. The transistor TR may include a double word line DWL and an active layer ACT. A bit line contact node BLC’ may be formed between the first source/drain region SR of the active layer ACT and the bit line BL’. A storage contact node SNC’ may be formed between the second source/drain region DR of the active layer ACT and the storage node SN of the capacitor CAP. The bit line contact node BLC’ and the storage contact node SNC’ may be doped polysilicon. For example, the bit line contact node BLC’ and the storage contact node SNC’ may be polysilicon with doped N-type impurity such as phosphorous

The bit line contact node BLC’ and the storage contact node SNC’ may extend to adjacent end portions of the active layers ACT, thereby covering the surfaces perpendicular to the first direction D1of the end portions. The bit line contact node BLC’ and the storage contact node SNC’ may extend to be formed on the upper and lower surfaces of the ends of both sides of the active layers ACT. A combination of the bit line contact node BLC’ and the first source/drain region SR may form a lateral T-shape in the planes perpendicular to the third direction D3. The bit line contact node BLC’ may cover the surfaces of the active layer ACT perpendicular to the first direction D1and/or the second direction D2. The bit line contact node BLC’ may cover the upper surface, the lower surface, and one side of the ends of one side of the active layer ACT.

The bit line contact node BLC’ may include a first portion P1and second portions P2. The first portion P1may be in direct contact with the end of one side of the active layer ACT, and the second portion P2may extend from the first portion P1to partially cover the end of one side of the active layer ACT. The storage contact node SNC’ may also have the same structure as that of the bit line contact node BLC’.

The bit line BL’ may include a vertical extension P11and a protrusion P12. The protrusion P12may be disposed between the vertical extension portion P11and the bit line contact node BLC’. The vertical extension P11may be shared by the memory cells MC, and the protrusion portion P12may be independently formed based on a memory cell MC unit.

A body dielectric layer BDL may be formed in the lower structure LS, and the body dielectric layer BDL and the bit line BL’ may be in direct contact. The bit line BL’ may extend vertically along the first direction D1from the body dielectric layer BDL. The body dielectric layer BDL may include a dielectric material, such as silicon oxide.

FIGS.6to19are cross-sectional views of a semiconductor device during the intermediate stages of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.FIGS.6to19may illustrate an example method for fabricating the semiconductor device200shown inFIG.5.

Referring toFIG.6, a stack body15may be formed over the substrate10. The substrate10may include a semiconductor substrate. In the stack body15, sub-stacks may be alternately stacked. Here, the sub-stack may include dielectric layers11, sacrificial layers12and14, and active layers13. The uppermost material of the stack body15may be the dielectric layer11. The sacrificial layers12and14may include first sacrificial layers12and second sacrificial layers14. The first sacrificial layers12and the second sacrificial layers14may be disposed between the dielectric layers11, and the active layers13may be disposed between the first sacrificial layers12and the second sacrificial layers14. The dielectric layers11may include silicon oxide, and the sacrificial layers12and14may include silicon nitride. The active layers13may include a semiconductor material or an oxide semiconductor material. The active layers13may include monocrystalline silicon, polysilicon, IGZO, or combinations thereof. According to an alternative embodiment of the present invention, the stack body15may be formed by alternately stacking a monocrystalline silicon layer and a silicon germanium layer and replacing the silicon germanium layer with a stack structure of silicon nitride and silicon oxide. Here, the monocrystalline silicon layer may correspond to the active layers13, and the replaced silicon nitride may correspond to the sacrificial layers12and14, and the replaced silicon oxide may correspond to the dielectric layers11.

Subsequently, a portion of the stack body15may be etched to form a first opening16. The first opening16may be a trench that vertically penetrates the stack body15. The first opening16may extend into the substrate10. A portion of the substrate10may be etched to extend the first opening16.

Although not illustrated, a plurality of active layers13may be formed between the sacrificial layers12and14. For example, similarly to the active layer ACT shown inFIG.3, a plurality of active layers13may be laterally arranged on the same plane. For example, the step of forming the active layers13may include forming the stack body15in such a manner that the sacrificial layers12and14are disposed between the dielectric layers11and a planar semiconductor layer is disposed between the sacrificial layers12and14, forming a plurality of isolation holes by etching the stack body15, and forming a plurality of semiconductor layer patterns that are laterally arranged between the sacrificial layers12and14by recess-etching the planar semiconductor layer through the isolation holes.

Referring toFIG.7, the active layers13may be selectively etched partially or entirely to form recesses17. A portion of the sacrificial layers12and14may be exposed in the recesses17.

A body recess18may be formed in the substrate10during the recessing of the active layers13. The width of the body recess18may be greater than the width of the first opening16.

Referring toFIGS.8and9, cap layers19that fill the recesses17may be formed. For example, the cap layers19may be formed by depositing a silicon nitride layer19A in recess17and performing an etch-back process. A body spacer19B may be formed on sidewalls of the body recess18by the etch-back process of the silicon nitride19A. The body spacer19B may partially expose the bottom surface of the body recess18.

Referring toFIG.10, the dielectric layers11may be laterally recessed to a predetermined depth from the first opening16. As a result, portions of the first and second sacrificial layers12and14may be exposed in the edge recesses20.

Referring toFIG.11, a body protective layer21may be formed to partially fill the body recess18. The body protective layer21may have an etch selectivity with respect to the body spacer19B. The body protective layer21and the body spacer19B may include different materials. The body protective layer21may include silicon oxide.

A method of forming the body protective layer21may include any suitable method. For example, the body protective layer21may be formed by an oxidation process or by an Area Selective Deposition (ASD) process. In an embodiment, the body protective layer21may be formed by performing an oxidation process. In another embodiment, the body protective layer21may be formed by an ASD process. The ASD process allows for selective deposition of the body protective layer21.

Referring toFIG.12, the first and second sacrificial layers12and14may be recessed partially or entirely. As a result, gate recesses22may be formed over and below the active layers13. The body spacer19B and the cap layers19may also be removed while the sacrificial layers12and14are removed. As the cap layers19and the sacrificial layers12and14are recessed, the ends23of one side of the active layers13may be exposed. An end portion23of each of the active layers13proximal to the first opening16may be exposed in the gate recesses22.

Referring toFIG.13, gate dielectric layers24may be formed over the exposed end portions23of the active layers13. The gate dielectric layers24may be selectively formed on the surfaces of the active layers13by an oxidation process. Alternatively, the gate dielectric layers24may be formed by a deposition process. The deposition process forms the gate dielectric layers24in the gate recesses22and over the exposed portions of the active layers13.

A first body liner24A may be formed on the surface of substrate10in the body recess18while the gate dielectric layers24are formed. The first body liner24A may be formed by an oxidation process. The body protective layer21may remain on the surface of the substrate10in the body recess18.

Subsequently, each of the gate recesses22may be filled with a conductive material to form double word lines25. The double word lines25may include polysilicon, titanium nitride, tungsten, or combinations thereof. For example, the step of forming the double word lines25may include conformally depositing titanium nitride, depositing tungsten over the titanium nitride to fill the gate recesses22, and performing an etch-back process on the titanium nitride and tungsten. The double word lines25may partially fill the gate recesses22, and thus a portion of the gate dielectric layers24may be exposed in the gate recesses22. The double word lines25may align vertically and may be spaced apart by the active layer13. Alternatively, a single word line or a gate-all-around word line may be formed.

Referring toFIGS.6to13, portions of the first sacrificial layers12and portions of the second sacrificial layers14are replaced by the double word lines25.

Referring toFIG.14, liner layers26contacting one side of the double word lines25may be formed. The liner layers26may be disposed in the inside of the gate recesses22. The liner layers26may include silicon oxide or silicon nitride. The liner layers26may expose portions of the gate recesses22. In other words, a space (or an air gap) may be formed on one side of the liner layers26. For example, the liner layers26may be formed by depositing silicon oxide26A and performing an etch-back process. A second body liner26L may be formed while the liner layers26are formed.

The body dielectric layer BDL may include the body protective layer21, the first body liner24A, and the second body liner26L. The first body liner24A and the second body liner26L may include silicon oxide, and the body protective layer21may include silicon nitride.

Subsequently, a portion of the gate dielectric layer24exposed in the first opening16may be etched to expose the end portions23of the active layers13.

Referring toFIG.15, a conductive layer27A including an impurity (e.g., dopant) may be formed. The conductive layer27A may be polysilicon containing an N-type impurity such as phosphorous. A portion of the conductive layer27A may fill the space (or air gap) adjacent to the liner layers26. The conductive layer27A directly contacts the end portions23of the active layers13.

Although not illustrated, heat treatment may be performed after the formation of the conductive layer27A. Impurities may be diffused from the conductive layer27A into the end portions23of the active layers13by the heat treatment. The diffused impurities may form the first source/drain regions SR shown inFIGS.1to5.

Referring toFIG.16, the conductive layer27A may be recessed to form contact nodes27. The contact nodes27may fill the space (or air gap) adjacent to the liner layers26. The contact nodes27may extend to the upper and lower surfaces of the end portions23of the active layers13. The contact nodes27and the active layers13form a lateral T-shape. The contact nodes27may cover the upper surface, the lower surface, and the end portions23of the active layers13. Contact nodes27may be referred to as bit line contact nodes or storage contact nodes. The contact nodes27may correspond to the bit line contact nodes BLC and BLC’ shown inFIGS.1to5.

Referring toFIG.17, a conductive line28coupled to the contact nodes27may be formed in the first opening16. The conductive line28may be referred to as a vertical conductive line. The conductive line28may include a metal-based material. The conductive line28may correspond to the bit lines BL and BL’ shown inFIGS.1to5. The conductive line28may directly contact the body protective layer21and may extend vertically over the body protective layer21. The contact nodes27may be coupled to the same conductive line28. The substrate10and the conductive line28may be electrically isolated from each other by the body dielectric layer BDL, that is, the body protective layer21, the first body liner24A, and the second body liner26L.

Referring toFIG.18, portions of the stack body15at the opposite sides of the conductive line28may be etched to form second openings29. Subsequently, the first and second sacrificial layers12and14and the active layers13may be recessed through the second openings29. As a result, capacitor openings30may be formed. The sacrificial layers12and14may remain on the other sides of the double word line25.

The double word lines25may be formed with the individual active layer13interposed therebetween, and the gate dielectric layers24may be formed between the double word line25and the active layer13. The contact nodes27may be coupled to the end portions23of the active layers13. The liner layers26may be formed between the contact nodes27and the double word line25.

After the capacitor openings30are formed, polysilicon doped with an N-type impurity may be deposited over the sidewalls of the active layers13, as well as other components exposed in the capacitor openings30. A heat treatment process may be performed. As a result, impurities may diffuse into the ends of the other side of the active layers13. The diffused impurities may form the second source/drain regions DR shown inFIGS.1to5. The polysilicon doped with an N-type impurity may be etched to remain in the same shape as that of the contact nodes27ofFIG.16. The polysilicon doped with an N-type impurity may correspond to the storage contact nodes SNC and SNC’ shown inFIGS.1to5.

Referring toFIG.19, a capacitor including a storage node31, a dielectric layer32, and a plate node33may be sequentially formed.

The bit line28may include a contact pad side28A covered by a body dielectric layer BDL and a bonding pad side28B distal to the contact pad side28A.

Referring toFIGS.6to19, the semiconductor device may include a substrate10, a body recess18in the substrate10, a body dielectric layer BDL in the body recess18, an active layer13over and parallel to the substrate10, a contact node27perpendicular to the active layers13, and a bit line28coupled to the contact nodes27and extending vertically upwards from the body dielectric layer BDL.

In the above-described embodiments of the present invention, the body dielectric layer BDL is formed at the end of the bit line28in the substrate10. Such configuration of the body dielectric layer BDL helps prevent an electrical bridge between the bit line28and the substrate10and between adjacent bit lines28, thereby reducing or eliminating leakage current to the substrate10. Accordingly, it is possible to control the leakage current to the substrate10. Also, it is possible to prevent an electrical bridge between the neighboring bit lines28.

FIGS.20to24are cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with another embodiment of the present invention.FIGS.20to24illustrate a method of coupling a memory cell array and a peripheral circuit portion to each other by wafer bonding.

Referring toFIG.20, a plurality of first bonding pads BP1and a first bonding dielectric layer BP11may be formed. The first bonding pads BP1may be coupled to the bit line28and the plate node33. The first bonding dielectric layer BP11may be disposed between the first bonding pads BP1. The first bonding dielectric layer BP11may expose the surface of the first bonding pads BP1.

In the embodiment illustrated inFIG.20, the bit line28and the capacitors CAP may be disposed below the substrate10. The first bonding pads BP1and the first bonding dielectric layer BP11may be disposed below the memory cell array MCA accordingly. The memory cell array MCA may be formed according to the process ofFIGS.6to19. The substrate10may be referred to as a ‘first substrate10’. The storage node31, the dielectric layer32, and the plate node33may form a capacitor CAP.

The bit line28may include a contact pad side28A which is covered by the body dielectric layer BDL and a bonding pad side28B which faces the contact pad side28A.

Subsequently, a peripheral circuit portion PERI may be prepared. The peripheral circuit portion PERI may include a second substrate40and peripheral circuit transistors41. The peripheral circuit portion PERI may further include a multi-level metal interconnection UM, and the multi-level metal interconnection UM may be coupled to the peripheral circuit transistors41. The peripheral circuit transistors41may be part of a sense amplifier. Although not illustrated, the peripheral circuit portion PERI may further include a multi-level metal interconnection which is coupled to the plate nodes33and peripheral circuit transistors which is coupled to the multi-level metal interconnection. The peripheral circuit portion PERI may further include a multi-level metal interconnection coupled to the double word lines25and sub-word line drivers coupled to the multi-level metal interconnection.

A plurality of second bonding pads BP2and a second bonding dielectric layer BP12may be formed. The second bonding pads BP2may be coupled to the multi-level metal interconnection UM of the peripheral circuit portion PERI. The second bonding dielectric layer BP12may be disposed between the second bonding pads BP2. The second bonding pads BP2are embedded in the second bonding dielectric layer BP12with portions of the surfaces exposed beyond the second bonding dielectric layer BP12.

The first and second bonding pads BP1and BP2may include a metal-based material. The first and second bonding dielectric layers BP11and BP12may include silicon oxide, silicon nitride, or combinations thereof.

The memory cell array MCA may be disposed over the peripheral circuit portion PERI.

Referring toFIG.21, the memory cell array MCA and the peripheral circuit portion PERI may be coupled to each other by wafer bonding. In the wafer bonding process, the first bonding pads BP1and the second bonding pads BP2may be bonded together; and the first bonding dielectric layer BP11and the second bonding dielectric layer BP12may be bonded together. In an embodiment, metal-to-metal bonding, hybrid bonding, and the like may be used. Metal-to-metal bonding may refer to bonding of the first bonding pads BP1and the second bonding pads BP2. Hybrid bonding may refer to a bonding method that further includes bonding of the first bonding dielectric layer BP11and the second bonding dielectric layer BP12in addition to the metal-to-metal bonding. The bonding pad side28B of the bit line28may be coupled to the peripheral circuit portion PERI by the first bonding pads BP1and the second bonding pads BP2.

As described above, after the peripheral circuit portion PERI and the memory cell array MCA are separately formed, they may be bonded by wafer bonding. The body dielectric layer BDL may be applied as a material for protecting the bit line28during the wafer bonding.

Referring toFIG.22, the first substrate10may be selectively stripped. The stripping process of the first substrate10may use wet etching capable of selectively stripping silicon. During the wet etching of the first substrate10, the body dielectric layer BDL may serve as an etch-stopping barrier to protect the bit line28from being etched.

Referring toFIG.23, a front dielectric layer50filling the space from which the first substrate10is removed may be formed. The front dielectric layer50may include silicon oxide. The front dielectric layer50may cover (or wraps around) the entire body dielectric layer BDL.

Referring toFIG.24, a bit line pad51may be formed in the front dielectric layer50to couple with the bit line28. The bit line pad51penetrates the front dielectric layer50and the body dielectric layer BDL (e.g., through the protective layer21). The bit line pad51may include a metal-based material.

Referring toFIGS.20to24, a semiconductor device may include a second substrate40having a peripheral circuit portion PERI; a memory cell array MCA including a vertical conductive line, such as a bit line28having a contact pad side28A and a bonding pad side28B; a first bonding pad BP1coupled to the bonding pad side28B; a second bonding pad BP2disposed between and coupled to the peripheral circuit portion PERI and the first bonding pad BP1; a body dielectric layer BDL covering the contact pad side28A; and a bit line pad51penetrating the body dielectric layer BDL and coupled to the contact pad side28A.

Referring toFIGS.20to24, the method for fabricating a semiconductor device may include forming a memory cell array MCA, where the memory cell array MCA includes a body dielectric layer BDL and a bit line28, where the bit line28includes a contact pad side28A covered by (or embedded in) the body dielectric layer BDL and a bonding pad side28B distal to the contact pad side28A and where the body dielectric layer BDL may include a body protective layer21covering the contact pad side28A, a first body liner24, and a second body liner26L; forming a second substrate40including the peripheral circuit portion PERI; bonding the bonding pad side28B to the peripheral circuit portion PERI; selectively removing the first substrate10; and forming a bit line pad51coupled to the contact pad side28A.

According to the embodiments of the present invention, the body dielectric layer BDL covering the vertical conductive lines (e.g., the bit line28) may prevent electrical bridges between the neighboring vertical conductive lines, which may suppress leakage current to a substrate.

The effects desired to be obtained in the embodiments of the present invention are not limited to the effects mentioned above, and other effects not mentioned above may also be clearly understood by those of ordinary skill in the art to which the present invention pertains the description below.