Controller and operating method thereof

A controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2018-0080050 filed on Jul. 10, 2018, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Various embodiments of the present invention generally relate to a controller, and more particularly, to a controller capable of efficiently processing data, and an operating method thereof.

2. Description of the Related Art

The computer environment paradigm has shifted towards ubiquitous computing, which enables computing systems to be used anytime and anywhere. As a result, the demand for portable electronic devices, such as mobile phones, digital cameras, and laptop computers have increased rapidly. Those electronic devices generally include a memory system using a memory device as a data storage device. The data storage device may be used as a main memory unit or an auxiliary memory unit of a portable electronic device.

Since there is no mechanical driving part, a data storage device using a memory device provides advantages such as excellent stability and durability, high information access speed, and low power consumption. Also, the data storage device can have a higher data access rate and lower power consumption than a hard disk device. Non-limiting examples of the data storage device having such advantages include Universal Serial Bus (USB) memory devices, memory cards of diverse interfaces, Solid-State Drives (SSD) and the like.

SUMMARY

Various embodiments of the present invention are directed to a memory system capable of efficiently using a cache memory by compressing unmap data.

In accordance with an embodiment of the present invention, a controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.

In accordance with an embodiment of the present invention, an operating method of a controller may include: storing map data and unmap data; counting a number of the unmap data; setting offset values to each of the unmap data; and compressing the unmap data to have a predetermined compression length based on the offset values.

In accordance with an embodiment of the present invention, an operating method of a controller may include: detecting unmap data in a map table; attaching offset values to each of the unmap data; and compressing the unmap data based on the attached offset values.

DETAILED DESCRIPTION

Various examples of the disclosure are described below in more detail with reference to the accompanying drawings. The disclosure may be embodied in different other embodiments, forms and variations thereof and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and examples of the disclosure. It is noted that reference to “an embodiment,” “another embodiment” or the like does not necessarily mean only one embodiment, and different references to any such phrases are not necessarily to the same embodiment(s).

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former can be directly connected or coupled to the latter, or electrically connected or coupled to the latter via an intervening element therebetween.

As used herein, singular forms are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise. The articles ‘a’ and ‘an’ as used in this application and the appended claims should generally be construed to mean ‘one or more’ unless specified otherwise or clear from context to be directed to a singular form.

FIG. 1is a block diagram illustrating a data processing system100in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may include a host102operatively coupled to a memory system110.

The host102may include, for example, a portable electronic device such as a mobile phone, an MP3 player and a laptop computer or an electronic device such as a desktop computer, a game player, a television (TV), a projector and the like.

The memory system110may operate or perform a specific function or operation in response to a request from the host102and, particularly, may store data to be accessed by the host102. The memory system110may be used as a main memory system or an auxiliary memory system of the host102. The memory system110may be implemented with any one of various types of storage devices, which may be electrically coupled to the host102, according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like.

The storage devices for the memory system110may be implemented with a volatile memory device such, for example, as a dynamic random access memory (DRAM) and a static RAM (SRAM) and/or a nonvolatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (RRAM or ReRAM) and a flash memory.

The memory system110may include a controller130and a memory device150. The memory device150may store data to be accessed by the host102, and the controller130may control storage of data in the memory device150.

The controller130and the memory device150may be integrated into a single semiconductor device, which may be included in the various types of memory systems as exemplified above.

The memory system110may be configured as a part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage configuring a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a radio frequency identification (RFID) device, or one of various components configuring a computing system.

The memory device150may be a nonvolatile memory device and may retain data stored therein even while an electrical power is not supplied. The memory device150may store data provided from the host102through a write operation, and provide data stored therein to the host102through a read operation. The memory device150may include a plurality of memory blocks152to156, each of the memory blocks152to156may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells to which a plurality of word lines (WL) are electrically coupled.

The controller130may control overall operations of the memory device150, such as read, write, program and erase operations. For example, the controller130may control the memory device150in response to a request from the host102. The controller130may provide the data, read from the memory device150, with the host102, and/or may store the data, provided by the host102, into the memory device150.

The controller130may include a host interface (I/F)132, a processor134, an error correction code (ECC) component138, a power management unit (PMU)140, a memory interface (I/F)142, and a memory144all operatively coupled via an internal bus.

The host interface132may process commands and data provided from the host102, and may communicate with the host102through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

The ECC component138may detect and correct errors in the data read from the memory device150during the read operation. When the number of the error bits is greater than or equal to a threshold number of correctable error bits, the ECC component138may not correct error bits but may output an error correction fail signal indicating failure in correcting the error bits.

The ECC component138may perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC component138may include all or some of circuits, modules, systems or devices for performing the error correction operation based on at least one of the above described codes.

The PMU140may provide and manage power of the controller130.

The memory interface142may serve as an interface for handling commands and data transferred between the controller130and the memory device150, to allow the controller130to control the memory device150in response to a request delivered from the host102. The memory interface142may generate a control signal for the memory device150and may process data entered into or outputted from the memory device150under the control of the processor134, in a case when the memory device150is a flash memory and, in particular, when the memory device150is a NAND flash memory.

The memory144may serve as a working memory for the memory system110and the controller130, and may store temporary or transactional data for operating or driving the memory system110and the controller130. The controller130may control the memory device150in response to a request from the host102. The controller130may deliver data read from the memory device150into the host102, may store data entered through the host102within the memory device150. The memory144may be used to store data required for the controller130and the memory device150in order to perform these operations.

The memory144may be implemented with a volatile memory. The memory144may be implemented with a static random access memory (SRAM) or a dynamic random access memory (DRAM). AlthoughFIG. 1exemplifies the memory144disposed within the controller130, the disclosure is not limited thereto. That is, the memory144may be located inside or outside the controller130. For instance, the memory144may be embodied by an external volatile memory having a memory interface transferring data and/or signals transferred between the memory144and the controller130.

The processor134may control the overall operations of the memory system110. The processor134may drive or execute a firmware to control the overall operations of the memory system110. The firmware may be referred to as a flash translation layer (FTL).

The FTL may perform an operation such as interfacing between the host102and the memory device150. The host102may transmit requests for write and read operations to the memory device150through the FTL.

The FTL may manage operations of address mapping, garbage collection, wear-leveling and so forth. Particularly, the FTL may store map data. Therefore, the controller130may map a logical address, which is provided from the host102, to a physical address of the memory device150through the map data. The memory device150may perform an operation like a general device because of the address mapping operation. Also, through the address mapping operation based on the map data, when the controller130updates data of a particular page, the controller130may program new data on another empty page and may invalidate old data of the particular page due to a characteristic of a flash memory device. Further, the controller130may store map data of the new data into the FTL.

The processor134may be implemented with a microprocessor or a central processing unit (CPU). The memory system110may include one or more processors134.

A management unit (not shown) may be included in the processor134. The management unit may perform bad block management of the memory device150. The management unit may find bad memory blocks included in the memory device150, which are in unsatisfactory condition for further use, as well as perform bad block management on the bad memory blocks. When the memory device150is a flash memory, for example, a NAND flash memory, a program failure may occur during the write operation, for example, during the program operation, due to characteristics of a NAND logic function. During the bad block management, the data of the program-failed memory block or the bad memory block may be programmed into a new memory block. The bad blocks may seriously aggravate the utilization efficiency of the memory device150having a 3D stack structure and the reliability of the memory system100, and thus reliable bad block management is required.

FIG. 2is a schematic diagram illustrating the memory device150.

Referring toFIG. 2, the memory device150may include the plurality of memory blocks BLOCK0to BLOCKN−1, and each of the blocks BLOCK0to BLOCKN−1 may include a plurality of pages, for example, 2Mpages, the number of which may vary according to circuit design. The memory device150may include a plurality of memory blocks, as single level cell (SLC) memory blocks and multi-level cell (MLC) memory blocks, according to the number of bits which may be stored or expressed in each memory cell. The SLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing 1-bit data. The MLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing multi-bit data, for example, two or more-bit data. An MLC memory block including a plurality of pages which are implemented with memory cells that are each capable of storing 3-bit data may be defined as a triple level cell (TLC) memory block.

FIG. 3is a circuit diagram illustrating a memory block330in the memory device150.

Referring toFIG. 3, the memory block330may correspond to any of the plurality of memory blocks152to156included in the memory device150of the memory system110.

Referring toFIG. 3, the memory block330of the memory device150may include a plurality of cell strings340which are electrically coupled to bit lines BL0to BLm−1, respectively. The cell string340of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC0to MCn−1 may be electrically coupled in series between the select transistors DST and SST. The respective memory cells MC0to MCn−1 may be configured by single level cells (SLC) each of which may store 1 bit of information, or by multi-level cells (MLC) each of which may store data information of a plurality of bits. However, the present invention is not limited to just the SLC or MLC. The strings340may be electrically coupled to the corresponding bit lines BL0to BLm−1, respectively. For reference, inFIG. 3, ‘DSL’ denotes a drain select line, ‘SSL’ denotes a source select line, and ‘CSL’ denotes a common source line.

WhileFIG. 3only shows, as an example, that the memory block330is constituted with NAND flash memory cells, it is to be noted that the memory block330of the memory device150according to the embodiment is not limited to a NAND flash memory. The memory block330may be realized by a NOR flash memory, a hybrid flash memory in which at least two kinds of memory cells are combined, or one-NAND flash memory in which a controller is built in a memory chip. The operational characteristics of a semiconductor device may be applied to not only a flash memory device in which a charge storing layer is configured by conductive floating gates but also a charge trap flash (CTF) in which a charge storing layer is configured by a dielectric layer.

A power supply circuit310of the memory device150may provide word line voltages, for example, a program voltage, a read voltage and a pass voltage, to be supplied to respective word lines according to an operation mode and voltages to be supplied to bulks, for example, well regions in which the memory cells are formed. The power supply circuit310may perform a voltage generating operation under the control of a control circuit (not shown). The power supply circuit310may generate a plurality of variable read voltages to generate a plurality of read data, select one of the memory blocks or sectors of a memory cell array under the control of the control circuit, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and unselected word lines.

A read and write (read/write) circuit320of the memory device150may be controlled by the control circuit, and may serve as a sense amplifier or a write driver according to an operation mode. During a verification operation or a normal read operation, the read/write circuit320may operate as a sense amplifier for reading data from the memory cell array. During a program operation, the read/write circuit320may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit320may receive from a buffer (not illustrated) data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit320may include a plurality of page buffers322to326respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs), and each of the page buffers322to326may include a plurality of latches (not illustrated).

FIG. 4is a schematic diagram illustrating a 3D structure of the memory device150.

AlthoughFIG. 4shows a 3D structure, the memory device150may be embodied by a two-dimensional (2D) or three-dimensional (3D) memory device. Specifically, as illustrated inFIG. 4, the memory device150may be embodied in a nonvolatile memory device having a 3D stack structure. When the memory device150has a 3D structure, the memory device150may include a plurality of memory blocks BLK0to BLKN−1 each having a 3D structure (or a vertical structure).

As described with reference toFIG. 1, the memory144may include a map cache. The map cache may store map data therein. The map data may represent relationship between logical block address (LBA) and physical block address (PBA). The logical block address may be provided along with data from the host102and may correspond to the data. The physical block address may indicate storage location of the data within the memory device150. For example, the controller130may receive a logical block address corresponding to write data from the host102and may assign physical block address for storing the write data into the memory device150through the FTL. The memory144may store map data representing the relationship between the logical block address and the physical block address corresponding to the write data into the map cache. The memory144may further include a map table in which the map data is an entry. In the map table, the map data may be recorded by a unit of a map segment. For example, when a size of a single map segment is 1024 KB and a size of a single map data is 1 KB, 1024 number of map data may be recorded within a single map table. The memory144may store a plurality of map tables. However, this is merely an example which will not limit the scope of the present invention. The structure of the map table will be described with reference toFIGS. 6A to 6C.

The controller130may read, based on the map data recorded in the map table, data in response to a read request provided from the host102. Particularly, in response to a read request provided from the host102, the controller130may detect a logical address corresponding to the read request in the map table, may detect a physical address that indicates substantial storage location of a target data based on the map data including the detected logical address, and may read the target data stored in the storage location indicated by the detected physical address. The controller130may improve the performance of the read operation through the map table. However, the map cache for storing the map data configuring the map table has a limited capacity, and therefore the capacity of the map cache needs to be used efficiently.

In accordance with an embodiment of the present disclosure, an operating method of the controller130for efficiently using the map cache is provided.

FIG. 5is a diagram illustrating a memory system110in accordance with an embodiment of the present disclosure.

FIG. 5merely illustrates, differently from the memory system110illustrated inFIG. 1, elements relevant to an embodiment of the present disclosure. Thus, the memory system110of the present disclosure is not limited to the elements shown in the embodiment ofFIG. 5. As described with reference toFIGS. 1 to 4, the memory system110may include the controller130and the memory device150. The controller130may control the memory device150. The controller130may include the processor134, the memory interface142and the memory144.

In addition, the controller130may include a counter510, a setter530and a compressor550.

The memory144may store map data into a map cache. The memory144may store unmap data which is a kind of map data unmapped in response to an unmap command provided from the host102, into the map cache. As described above, the map data may represent the relationship between the logical addresses and the physical addresses. However, the unmap data can no longer represent the relationship between the logical addresses and the physical addresses. Thus, the unmap data is data that may not be needed on memory144, and may be deleted at a later time.

The memory144may store a map table570in which the map data and the unmap data are recorded. The map table570may include a flag field and an address field. In the flag field, a flag may be recorded to discriminate the map data from the unmap data. In the address field, the logical addresses and the physical addresses (e.g., a block number and a page number) may be recorded. The value of the address field may represent mapping relationship between the logical addresses and the physical addresses (“L2P”). Both of the map data and the unmap data may be recorded into the map table570. In the memory144, map/unmap bit may be used to discriminate the map data from the unmap data. For example, when the map/unmap bit has a value of ‘0’ to indicate the unmap data, a value of the most significant bit (MSB) may be set as ‘0’ to indicate the unmap data and may be stored into the memory144. The unmap data having the most significant bit of a value ‘0’ may correspond to a value of ‘U’ in the flag field of the map table570. In contrast, when the map/unmap bit has a value of ‘1’ to indicate the map data, a value of the most significant bit may be set as ‘1’ to indicate the map data and may be stored into the memory144. The map data having the most significant bit of a value ‘1’ may correspond to a value of ‘M’ in the flag field of the map table570. However, this is merely an example which will not limit the scope of the present invention.

The processor134may control the memory device150to store therein the map data, which is recoded in the map table570stored in the map cache of the memory144, through the memory interface142in response to the flush command provided from the host102.

In accordance with an embodiment of the present invention, the counter510may count a number of the unmap data recorded in the whole map table570stored in the memory144. In accordance with an embodiment of the present invention, the counter510may count, by a unit of a map segment, a number of the unmap data recorded in the map table570. The counter510may compare the counted number of the unmap data with a predetermined threshold value. The counter510may provide the result of the comparison to the setter530.

The setter530may set offset values to each of the unmap data when the number of the unmap data is equal to or greater than the predetermined threshold value.

In accordance with an embodiment of the present invention, the setter530may set (or attach) offset values to the logical addresses corresponding to the unmap data. The setter530may arrange, based on the map table570, the unmap data such that the offset values for the unmap data increase as the offset values increase (i.e., as the logical addresses increase).

In accordance with an embodiment of the present invention, the setter530may set (or attach) offset values to physical addresses within a read map segment or a write map segment. It is assumed that 1024 number of map data is included in the write map segment and 512 number of map data is included in the read map segment when a size of the read map segment is 512 KB, a size of the write map segment is 1024 KB and a size of a single map data is 1 KB. However, this is merely an example which will not limit the scope of the present invention. As described above, the counter510may count the number of the unmap data included in each map segment. When the number of the unmap data included in a single map segment is equal to or greater than the predetermined threshold value, the setter530may arrange the unmap data such that the offset values for the unmap data increase as the physical addresses increase. For example, when there are a first unmap data corresponding to a memory block ‘100’ and a page ‘5’ and a second unmap data corresponding to a memory block ‘100’ and a page ‘1’, the setter530may arrange the first unmap data and the second unmap data into an order of the second unmap data and the first unmap data. For example, when there are a third unmap data corresponding to a memory block ‘50’ and a page ‘5’ and a fourth unmap data corresponding to a memory block ‘70’ and a page ‘5’, the setter530may arrange the third unmap data and the fourth unmap data into an order of the third unmap data and the fourth unmap data.

In accordance with an embodiment of the present disclosure, the setter530may set offset values by performing a modulo operation on the logical addresses such that the unmap data is compressed to have a predetermined compression length. For example, when the compressor550compresses the unmap data to have a compression length of ‘100’, the setter530sets the offset values from ‘1’ to ‘100’ as the logical addresses increase. That is, when there are unmap data respectively corresponding to logical addresses LBA1to LBA100, the setter530may set the offset values of ‘1’ to ‘100’ respectively for the unmap data corresponding to the logical addresses LBA1to LBA100. Further, when there are unmap data respectively corresponding to logical addresses LBA101to LBA200, the setter530may set the offset values of ‘1’ to ‘100’ respectively for the unmap data corresponding to the logical addresses LBA101to LBA200.

The setter530may provide the set offset values to the compressor550.

The compressor550may compress the unmap data to have a predetermined compression length based on the provided offset values. For example, when the predetermined compression length is ‘50’, the compressor550may compress, based on the offset values from ‘1’ to ‘100’, the unmap data corresponding to the offset values from ‘1’ to ‘50’ and the unmap data corresponding to the offset values from ‘51’ to ‘100’ to generate two pieces of compressed unmap data. The compressed unmap data may include a start logical address or a start physical address, a start offset value corresponding to a start logical address or a start physical address and a number of pieces of the unmap data. For example, when ‘100’ pieces of the unmap data having the offset values from ‘5’ to ‘104’ are compressed into the compressed unmap data, that compressed unmap data may include a value of ‘5’ as the start offset value corresponding to a start logical address or a start physical address and a value of ‘100’ as the number of pieces of the unmap data.

The compressor550may provide the compressed unmap data to the memory144. The memory144may store the compressed unmap data into the map cache.

As describe above, in accordance with an embodiment of the present disclosure, the controller130may compress the unmap data, and thus the map cache may be effectively utilized within the memory144having the limited capacity.

FIGS. 6A to 6Care diagrams for describing an operation of setting the offset values corresponding to the unmap data in accordance with an embodiment of the present disclosure.

FIGS. 6A to 6Cillustrate a first map table610and a second map table650. For clarity of description, the first map table610and the second map table650are separately illustrated but the first map table610and the second map table650are substantially the same map table. In the embodiment shown inFIGS. 6A to 6C, it is assumed that 6 pieces of map data are recorded in the first map table610and 6 pieces of unmap data are recorded in the second map table650. It is also assumed that a unmap command for all map data recorded in the first map table610is provided, thus all map data of the first map table610become the unmap data and the unmap data are recorded into the second map table650.

Each of the first map table610and the second map table650may have fields of a flag (“Flag”), a logical address (“LBA”), a memory block number (“Block”) and a page number (“Page”) to record the map data and the unmap data. As illustrated inFIGS. 6A to 6C, all data recorded in the first map table610are map data since all the flag field corresponding to the data are recorded as a value of ‘M’. In contrast, all data recorded in the second map table650are unmap data since all the flag field corresponding to the data are recorded as a value of ‘U’.

As illustrated inFIGS. 6A to 6C, the setter530may set the offset values (“offset”) corresponding to the unmap data recorded in the second map table650.

Referring toFIG. 6A, the setter530may set offset values to the logical addresses (LBA) corresponding to the unmap data.

For example, the setter530may set an offset value of ‘1’ for the unmap data corresponding to the logical address (LBA) ‘1’; The setter530may set an offset value of ‘2’ for the unmap data corresponding to the logical address ‘2’; and the setter530may set an offset value of ‘3’ for the unmap data corresponding to the logical address ‘3’. In similar manner, the setter530may set offset values for the unmap data such that the offset values for the unmap data increase as the logical addresses corresponding to the unmap data increase.

Referring toFIG. 6B, the setter530may set offset values to the physical addresses within the read map segment or the write map segment. It is assumed that plural pieces of map data recorded in the first map table610configure a single write map segment.

For example, as illustrated inFIG. 6B, the setter530may set the offset values from a smallest memory block number among the plural pieces of unmap data recorded in the second map table650. For example, the setter530may set an offset value of ‘1’ for the unmap data having the smallest memory block number of ‘10’ among the plural pieces of unmap data recorded in the second map table650; the setter530may set an offset value of ‘2’ for the unmap data having the second smallest memory block number of ‘20’ among the plural pieces of unmap data recorded in the second map table650; and the setter530may set an offset value of ‘3’ for the unmap data having a memory block number of ‘40’ (i.e., third smallest memory block) among the plural pieces of unmap data recorded in the second map table650. When there are plural pieces of the unmap data corresponding to the same memory block number among the plural pieces of unmap data recorded in the second map table650, the setter530may set offset values for the plural pieces of the unmap data corresponding to the same memory block number based on the page number. For example, the setter530may set an offset value of ‘4’ for the unmap data having the smallest page number of ‘1’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table650; the setter530may set an offset value of ‘5’ for the unmap data having the second smallest page number of ‘2’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table650; and the setter530may set an offset value of ‘6’ for the unmap data having a page number of ‘5’ among the plural pieces of unmap data corresponding to the same memory block number of ‘100’ in the second map table650. However, this is merely an example which will not limit the scope of the present invention.

Referring toFIG. 6C, the setter530may set offset values by performing a modulo operation on the logical addresses (LBA) such that the unmap data is compressed to have a predetermined compression length. It is assumed that the predetermined compression length is ‘3’. That is, it is assumed that 3 pieces of the unmap data are compressed into the compressed unmap data.

As illustrated inFIG. 6C, the setter530may set offset values for the unmap data basically according to the logical addresses (LBA) corresponding to the unmap data. However, the maximum of the offset value may be limited to a value of ‘3’ because the predetermined compression length is ‘3’. Therefore, as described with reference toFIG. 3, the setter530may set the offset values from ‘1’ to ‘3’ for the unmap data corresponding to the logical addresses (LBA) from ‘1’ to ‘3’. Then, the setter530may set the offset values not from ‘4’ to ‘6’ but from ‘1’ to ‘3’ for the unmap data corresponding to the logical addresses from ‘4’ to ‘6’. When the offset values are set as described with reference toFIG. 6A, a single piece of compressed unmap data may be generated. However, when the offset values are set as described with reference toFIG. 6C, 2 pieces of compressed unmap data may be generated. However, this is merely an example which will not limit the scope of present invention.

FIG. 7is a flowchart for describing an operation of the controller130in accordance with an embodiment of the present disclosure. Described with reference toFIGS. 6A to 7will be the operation of the controller130.

It is assumed that an unmap command is provided from the host102to the controller130for all map data recorded in the first map table610.

At step S701, the memory144may update the first map table610into the second map table650in response to the unmap command provided from the host102.

At step S703, the counter510may count a number of pieces of the unmap data recorded in the second map table650.

At step S705, the counter510may compare the counted number of pieces of the unmap data with the predetermined threshold value. The counter510may provide the setter530with the result of the comparison.

When the counted number of pieces of the unmap data is less than the predetermined threshold value (° No′ at step S705), the process may be repeated from step S701.

When the counted number of pieces of the unmap data is equal to or greater than the predetermined threshold value (‘Yes’ at step S705), the setter530may set the offset values respectively for the unmap data at step S707. For example, the setter530may set the logical addresses corresponding to the unmap data as the offset values for the unmap data, as described with reference toFIGS. 6A to 6C. The setter530may provide the offset values to the compressor550.

At step S709, the compressor550may compress the unmap data to have the predetermined compression length based on the offset values. The compressor550may provide the compressed unmap data to the memory144.

At step S711, the memory144may store the compressed unmap data into the map cache.

In other words, the operation of the controller130in accordance with an embodiment of the present disclosure may include detecting unmap data in a map table (e.g., S703and S705); attaching offset values to each of the unmap data (e.g., S707); and compressing the unmap data based on the attached offset values (e.g., S709).

Hereinafter, a data processing system and electronic devices which may be implemented with the memory system110including the memory device150and the controller130, which have been described with reference toFIGS. 1 to 7, will be described in detail with reference toFIGS. 8 to 16.

FIGS. 8 to 16are diagrams schematically illustrating application examples of the data processing system ofFIGS. 1 to 7according to various embodiments.

FIG. 8is a diagram schematically illustrating an example of the data processing system including the memory system in accordance with an embodiment.FIG. 8schematically illustrates a memory card system6100including the memory system in accordance with an embodiment.

Referring toFIG. 8, the memory card system6100may include a memory controller6120, a memory device6130and a connector6110.

More specifically, the memory controller6120may be connected to the memory device6130, and may be configured to access the memory device6130. The memory device6130may be embodied by a nonvolatile memory (NVM). By the way of example but not limitation, the memory controller6120may be configured to control read, write, erase and background operations onto the memory device6130. The memory controller6120may be configured to provide an interface between the memory device6130and a host (not shown) and/or a drive firmware for controlling the memory device6130. That is, the memory controller6120may correspond to the controller130in the memory system110described with reference toFIGS. 1 to 7, while the memory device6130may correspond to the memory device150described with reference toFIGS. 1 to 7.

Thus, as shown inFIG. 1, the memory controller6120may include a random access memory (RAM), a processor, a host interface, a memory interface and an error correction code component. The memory controller130may further include the elements described inFIG. 1.

The memory controller6120may communicate with an external device, for example, the host102ofFIG. 1through the connector6110. For example, as described with reference toFIG. 1, the memory controller6120may be configured to communicate with an external device through one or more of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), wireless fidelity (Wi-Fi or WiFi) and Bluetooth. Thus, the memory system and the data processing system in accordance with an embodiment may be applied to wired and/or wireless electronic devices or particularly mobile electronic devices.

The memory device6130may be implemented by a nonvolatile memory. For example, the memory device6130may be implemented by various nonvolatile memory devices such as an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (SU-RAM). The memory device6130may include a plurality of dies as in the memory device150ofFIG. 1.

The memory controller6120and the memory device6130may be integrated into a single semiconductor device. For example, the memory controller6120and the memory device6130may construct a solid state driver (SSD) by being integrated into a single semiconductor device. Also, the memory controller6120and the memory device6130may construct a memory card such as a PC card (e.g., Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro and eMMC), a secured digital (SD) card (e.g., SD, miniSD, microSD and SDHC) and a universal flash storage (UFS).

FIG. 9is a diagram schematically illustrating another example of a data processing system6200including a memory system, in accordance with an embodiment.

Referring toFIG. 9, the data processing system6200may include a memory device6230having one or more nonvolatile memories (NVMs) and a memory controller6220for controlling the memory device6230. The data processing system6200may serve as a storage medium such as a memory card (CF, SD, micro-SD or the like) or USB device, as described with reference toFIG. 1. The memory device6230may correspond to the memory device150in the memory system110described inFIGS. 1 to 7, and the memory controller6220may correspond to the controller130in the memory system110described inFIGS. 1 to 7.

The memory controller6220may control a read, write, or erase operation on the memory device6230in response to a request of the host6210, and the memory controller6220may include one or more central processing units (CPUs)6221, a buffer memory such as a random access memory (RAM)6222, an error correction code (ECC) circuit6223, a host interface6224and a memory interface such as an NVM interface6225.

The CPU6221may control the operations on the memory device6230, for example, read, write, file system management and bad page management operations. The RAM6222may be operated according to control of the CPU6221, and used as a work memory, buffer memory or cache memory. When the RAM6222is used as a work memory, data processed by the CPU6221may be temporarily stored in the RAM6222. When the RAM6222is used as a buffer memory, the RAM6222may be used for buffering data transmitted to the memory device6230from the host6210or transmitted to the host6210from the memory device6230. When the RAM6222is used as a cache memory, the RAM6222may assist the memory device6230to operate at high speed.

The ECC circuit6223may correspond to the ECC component138of the controller130illustrated inFIG. 1. As described with reference toFIG. 1, the ECC circuit6223may generate an error correction code (ECC) for correcting a fail bit or error bit of data provided from the memory device6230. The ECC circuit6223may perform error correction encoding on data provided to the memory device6230, thereby forming data with a parity bit. The parity bit may be stored in the memory device6230. The ECC circuit6223may perform error correction decoding on data outputted from the memory device6230. in this case, the ECC circuit6223may correct an error using the parity bit. For example, as described with reference toFIG. 1, the ECC circuit6223may correct an error using Low Density Parity Check (LDPC) code, Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolution code, Recursive Systematic Code (RSC) or coded modulation such as Trellis-Coded Modulation (TCM) or Block coded modulation (BCM).

The memory controller6220may transmit to, and/or receive from, the host6210data or signals through the host interface6224, and may transmit to, and/or receive from, the memory device6230data or signals through the NVM interface6225. The host interface6224may be connected to the host6210through a parallel advanced technology attachment (DATA) bus, a serial advanced technology attachment (SATA) bus, a small computer system interface (SCSI), a universal serial bus (USB), a peripheral component interconnect-express (PCIe), or a NAND interface. The memory controller6220may have a wireless communication function with a mobile communication protocol such as wireless fidelity (WiFi) or Long Term Evolution (LTE). The memory controller6220may be connected to an external device, e.g., the host6210, or another external device, and then transmit and/or receive data to and/or from the external device. As the memory controller6220is configured to communicate with the external device through one or more of various communication protocols, the memory system and the data processing system in accordance with an embodiment may be applied to wired and/or wireless electronic devices or particularly a mobile electronic device.

FIG. 10is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 10schematically illustrates a solid state drive (SSD) to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 10, the SSD6300may include a controller6320and a memory device6340including a plurality of nonvolatile memories (NVMs). The controller6320may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6340may correspond to the memory device150in the memory system ofFIG. 1.

More specifically, the controller6320may be connected to the memory device6340through a plurality of channels CH1to CHi. The controller6320may include one or more processors6321, an error correction code (ECC) circuit6322, a host interface6324, a buffer memory6325and a memory interface, for example, a nonvolatile memory interface6326.

The buffer memory6325may temporarily store data provided from the host6310or data provided from a plurality of flash memories NVM included in the memory device6340, or temporarily store meta data of the plurality of flash memories NVM, for example, map data including a mapping table. The buffer memory6325may be embodied by volatile memories such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a low power DDR (LPDDR) SDRAM and a graphics RAM (GRAM) or nonvolatile memories such as a ferroelectric RAM (FRAM), a resistive RAM (RRAM or ReRAM), a spin-transfer torque magnetic RAM (STT-MRAM) and a phase-change RAM (PRAM). For the purpose of description,FIG. 10illustrates that the buffer memory6325exists in the controller6320, but the buffer memory6325may be located or arranged outside the controller6320.

The ECC circuit6322may calculate an error correction code (ECC) value of data to be programmed to the memory device6340during a program operation, perform an error correction operation on data read from the memory device6340based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device6340during a failed data recovery operation.

The host interface6324may provide an interface function with an external device, for example, the host6310, and the nonvolatile memory interface6326may provide an interface function with the memory device6340connected through the plurality of channels.

Furthermore, a plurality of SSDs6300to which the memory system110ofFIG. 1is applied may be provided to embody a data processing system, for example, a redundant array of independent disks (RAID) system. The RAID system may include the plurality of SSDs6300and a RAID controller for controlling the plurality of SSDs6300. When the RAID controller performs a program operation in response to a write command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, i.e., RAID level information of the write command provided from the host6310in the SSDs6300, and may output data corresponding to the write command to the selected SSDs6300. Furthermore, when the RAID controller performs a read operation in response to a read command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, that is, RAID level information of the read command provided from the host6310in the SSDs6300, and provide data read from the selected SSDs6300to the host6310.

FIG. 11is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 11schematically illustrates an embedded Multi-Media Card (eMMC)6400to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 11, the eMMC6400may include a controller6430and a memory device6440embodied by one or more NAND flash memories. The controller6430may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110ofFIG. 1.

More specifically, the controller6430may be connected to the memory device6440through a plurality of channels. The controller6430may include one or more cores6432, a host interface (I/F)6431and a memory interface, for example, a NAND interface (I/F)6433.

The core6432may control the operations of the eMMC6400, the host interface6431may provide an interface function between the controller6430and the host6410. The NAND interface6433may provide an interface function between the memory device6440and the controller6430. For example, the host interface6431may serve as a parallel interface, for example, MMC interface as described with reference toFIG. 1. Furthermore, the host interface6431may serve as a serial interface, for example, Ultra High Speed (UHS)-I and UHS-II interface.

FIGS. 12 to 15are diagrams schematically illustrating other examples of the data processing system including the memory system in accordance with an embodiment.FIGS. 12 to 15schematically illustrate universal flash storage (UFS) systems to which the memory system in accordance with an embodiment is applied.

Referring toFIGS. 12 to 15, the UFS systems6500,6600,6700and6800may include hosts6510,6610,6710,6810, UFS devices6520,6620,6720,6820and UFS cards6530,6630,6730,6830, respectively. The hosts6510,6610,6710,6810may serve as application processors of wired and/or wireless electronic devices or particularly mobile electronic devices, the UFS devices6520,6620,6720,6820may serve as embedded UFS devices. The UFS cards6530,6630,6730,6830may serve as external embedded UFS devices or removable UFS cards.

The hosts6510,6610,6710,6810, the UFS devices6520,6620,6720,6820and the UFS cards6530,6630,6730,6830in the respective UFS systems6500,6600,6700and6800may communicate with external devices, e.g., wired and/or wireless electronic devices or particularly mobile electronic devices through UFS protocols. The UFS devices6520,6620,6720,6820and the UFS cards6530,6630,6730,6830may be embodied by the memory system110illustrated inFIG. 1. For example, in the UFS systems6500,6600,6700,6800, the UFS devices6520,6620,6720,6820may be embodied in the form of the data processing system6200, the SSD6300or the eMMC6400described with reference toFIGS. 9 to 11, and the UFS cards6530,6630,6730,6830may be embodied in the form of the memory card system6100described with reference toFIG. 8.

Furthermore, in the UFS systems6500,6600,6700and6800, the hosts6510,6610,6710,6810, the UFS devices6520,6620,6720,6820and the UFS cards6530,6630,6730,6830may communicate with each other through an UFS interface, for example, MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface). Furthermore, the UFS devices6520,6620,6720,6820and the UFS cards6530,6630,6730,6830may communicate with each other through various protocols other than the UFS protocol, e.g., universal storage bus (USB) Flash Drives (UFDs), multi-media card (MMC), secure digital (SD), mini-SD, and micro-SD.

In the UFS system6500illustrated inFIG. 12, each of the host6510, the UFS device6520and the UFS card6530may include UniPro. The host6510may perform a switching operation to communicate with at least one of the UFS device6520and the UFS card6530. The host6510may communicate with the UFS device6520or the UFS card6530through link layer switching, e.g., L3 switching at the UniPro. In this case, the UFS device6520and the UFS card6530may communicate with each other through a link layer switching at the UniPro of the host6510. In an example, the configuration in which one UFS device6520and one UFS card6530are connected to the host6510has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the host6510, and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6520or connected in series or in the form of a chain to the UFS device6520. Herein, the form of a star means an arrangement that a single device is coupled with plural other devices or cards for centralized control.

In the UFS system6600illustrated inFIG. 13, each of the host6610, the UFS device6620and the UFS card6630may include UniPro, and the host6610may communicate with the UFS device6620or the UFS card6630through a switching module6640performing a switching operation, for example, through the switching module6640which performs link layer switching at the UniPro, for example, L3 switching. The UFS device6620and the UFS card6630may communicate with each other through link layer switching of the switching module6640at UniPro. In an example, the configuration in which one UFS device6620and one UFS card6630are connected to the switching module6640has been exemplified for convenience of description. However, a plurality of UFS devices and UFS cards may be connected in parallel or in the form of a star to the switching module6640, and a plurality of UFS cards may be connected in series or in the form of a chain to the UFS device6620.

In the UFS system6700illustrated inFIG. 14, each of the host6710, the UFS device6720and the UFS card6730may include UniPro. The host6710may communicate with the UFS device6720or the UFS card6730through a switching module6740performing a switching operation, for example, the switching module6740which performs link layer switching at the UniPro, for example, L3 switching. In this case, the UFS device6720and the UFS card6730may communicate with each other through link layer switching of the switching module6740at the UniPro, and the switching module6740may be integrated as one module with the UFS device6720inside or outside the UFS device6720. In an example, the configuration in which one UFS device6720and one UFS card6730are connected to the switching module6740has been exemplified for convenience of description. However, a plurality of modules each including the switching module6740and the UFS device6720may be connected in parallel or in the form of a star to the host6710or connected in series or in the form of a chain to each other. Furthermore, a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6720.

In the UFS system6800illustrated inFIG. 15, each of the host6810, the UFS device6820and the UFS card6830may include M-PHY and UniPro. The UFS device6820may perform a switching operation to communicate with the host6810and the UFS card6830. The UFS device6820may communicate with the host6810or the UFS card6830through a switching operation between the M-PHY and UniPro module for communication with the host6810and the M-PHY and UniPro module for communication with the UFS card6830, for example, through a target Identifier (ID) switching operation. Here, the host6810and the UFS card6830may communicate with each other through target ID switching between the M-PHY and UniPro modules of the UFS device6820. In an embodiment, the configuration in which one UFS device6820is connected to the host6810and one UFS card6830is connected to the UFS device6820has been exemplified for convenience of description. However, a plurality of UFS devices may be connected in parallel or in the form of a star to the host6810, or connected in series or in the form of a chain to the host6810, and a plurality of UFS cards may be connected in parallel or in the form of a star to the UFS device6820, or connected in series or in the form of a chain to the UFS device6820.

FIG. 16is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 16is a diagram schematically illustrating a user system6900to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 16, the user system6900may include a user interface6910, a memory module6920, an application processor6930, a network module6940, and a storage module6950.

More specifically, the application processor6930may drive components included in the user system6900, for example, an operating system (OS), and include controllers, interfaces and a graphic engine which control the components included in the user system6900. The application processor6930may be provided as a System-on-Chip (SoC).

The memory module6920may be used as a main memory, work memory, buffer memory or cache memory of the user system6900. The memory module6920may include a volatile random access memory (RAM) such as a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatile RAM such as a phase-change RAM (PRAM), a resistive RAM (ReRAM), a magneto-resistive RAM (MRAM) or a ferroelectric RAM (FRAM). For example, the application processor6930and the memory module6920may be packaged and mounted, based on Package on Package (PoP).

The network module6940may communicate with external devices. For example, the network module6940may not only support wired communication, but may also support various wireless communication protocols such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (Wimax), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), thereby communicating with wired/wireless electronic devices or particularly mobile electronic devices. Therefore, the memory system and the data processing system, in accordance with an embodiment of the present invention, can be applied to wired/wireless electronic devices. The network module6940may be included in the application processor6930.

The storage module6950may store data, for example, data received from the application processor6930, and then may transmit the stored data to the application processor6930. The storage module6950may be embodied by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash, NOR flash and 3D NAND flash, and provided as a removable storage medium such as a memory card or external drive of the user system6900. The storage module6950may correspond to the memory system110described with reference toFIG. 1. Furthermore, the storage module6950may be embodied as an SSD, eMMC and UFS as described above with reference toFIGS. 10 to 15.

Furthermore, when the memory system110ofFIG. 1is applied to a mobile electronic device of the user system6900, the application processor6930may control the operations of the mobile electronic device, and the network module6940may serve as a communication module for controlling wired and/or wireless communication with an external device. The user interface6910may display data processed by the processor6930on a display and touch module of the mobile electronic device, or support a function of receiving data from the touch panel.