Enhanced interconnect structure

The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping material. The barrier can be either partially embedded in the cap layer or completely embedded in the capping layer.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor integrated circuits (ICs), and more particularly to a back-end-of-the-line (BEOL) interconnect that has a modified structure that enhances the mechanical strength and reliability of the interconnect. The present invention is also related to a method for fabricating the semiconductor IC structure containing the modified interconnect structure.

Damascene processes are well known methods to form metal features such as lines or vias in semiconductor devices. In a typical damascene process a dielectric layer is deposited on a substrate and a portion of the dielectric is etched away in accordance with a mask pattern. The etched areas in the dielectric layer are lined with a barrier metal and then filled with a metal. Excess liner and metal deposited over the dielectric layer is removed in a planarization process.

The vias and lines may be formed in a separate damascene process known as single damascene. To form a layer of metal lines on a substrate, a dielectric layer is deposited and a portion of the dielectric layer is etched away in accordance to a mask pattern which corresponds to the desired line pattern. A metal liner is then deposited on the dielectric layer and in the etched line areas in the dielectric layer. The etched line areas are then filled with a metal and excess metal and liner on top of the dielectric layer is removed in a planarization process. A layer of vias, or vertical connections, are formed in a similar process with a mask pattern corresponding to the desired via pattern. In a single damascene process to form a layer of vias and lines requires two metal fill steps and two planarization steps.

The vias and lines may also be formed in a dual damascene process. A thicker dielectric layer is deposited on a substrate and the dielectric layer is etched according to a mask pattern which corresponds to both the desired via pattern and the desired line pattern. A liner is deposited on the dielectric layer and in the etched areas in the layer. The etched areas are filled with a metal and the excess metal and liner are removed by a planarization process.

FIGS. 1A-1Dillustrate various prior art dual damascene structures. Each of the dual damascene structures shown comprises a first dielectric100that includes a metal interconnect or line110which extends perpendicular to the plane of the paper. The interconnect110is surrounded by diffusion barrier materials(s)105, and a first patterned cap layer120is also present on a surface of the first dielectric100. A second dielectric130is located atop the first cap layer120. The second dielectric130has a dual damascene aperture, which includes a lower portion148and an upper portion150, formed therein. The lower portion148is referred to in the art as a via, while the upper portion150is referred to in the art as a line.

The dielectrics used in each of the levels are typically comprised of silicon dioxide, a thermosetting polyarylene resin, an organosilicate glass such as a carbon-doped oxide (SiCOH), or any other type of hybrid related dielectric. The via148makes contact with the underlying interconnect110, while the line150extends over a significant distance to make contact with other elements of the IC as required by the specific design layout. In the drawings, the portion of the cap layer120at the bottom of the via148has been removed, usually by a different etching chemistry than that used to etch the second dielectric130. A patterned hard mask122is located atop the second dielectric130.

It is conventional in the prior art to deposit a liner140over the entire interior of the structure before metallization. Liner140and105can be a single layer such as shown inFIG. 1AandFIG. 1C, or multiple layers140,145, and105,106as shown inFIGS. 1B and 1D. InFIGS. 1C and 1D, the liner140is not located on the bottom horizontal surface of the via148. The liner140,145is comprised of a refractory metal such as, for example, Ta, Ti, Ru, Ir and W, or a refractory metal nitride such as TaN, TiN, and WN. An optional adhesion layer, not specifically shown, can be used to enhance the bonding of the liner to the second dielectric layer130. A conductive material (not specifically shown) such as Al, W, Cu or alloys thereof is then deposited so as to completely fill the aperture providing conductively filled vias and conductively filled lines.

One problem with the prior art interconnect structures shown inFIGS. 1A-1Dis that it is difficult to obtain a good mechanical contact at normal chip operation temperatures. With continuous scaling and the introduction of low-K dielectrics in Cu interconnects, reliability issues have become a greater concern in addition to increasing process complexity. Additionally, the prior art interconnect structures oftentimes exhibit an open circuit or high resistance joint during reliability testing.

Referring toFIG. 1Ait has been observed that the liner105/cap layer120/dielectric interface100(“three point junction”) is a mechanically weak site, and is associated with reliability related problems as shown inFIG. 1E. The dielectric breakdown failure allowing copper diffusion and shorting is a reliability concern which is becoming more critical as IC dimensions become smaller. It has been observed that Cu atoms can diffuse through the Cu/cap layer interface during normal circuit operating conditions.

The weak mechanical strength at this interface can lead to Cu diffusion into the dielectric and cause circuit reliability degradation. This dielectric breakdown is getting worse as the spacing between adjacent interconnects decreases. In addition it is well known that Cu ions can easily diffuse into dielectrics in the absence of barrier materials under the influence of an electric field. It has been observed that Cu ions can diffuse into the dielectric along the Cu/capping layer interface under normal circuit operating conditions.

Therefore, there is a need for providing a new and improved interconnect structure that avoids the problems mentioned above. That is, an interconnect structure is needed that has and maintains good mechanical contact during normal chip operations and does not fail during various reliability tests such as thermal cycling and high temperature baking.

Therefore, an object of the present invention is to provide a structure that enhances the reliability of the interconnection. Another object of the present invention is to provide a novel interconnect structure with Cu diffusion barrier material embedded in the Cu cap material. Another object of the present invention is to provide fabrication methods for creating the novel interconnect structure.

BRIEF SUMMARY OF THE INVENTION

The present invention provides an interconnect structure comprising a dielectric layer with at least one conductive interconnect embedded therein; a diffusion barrier layer surrounding the conductive interconnects and in contact with the dielectric layer and conductive interconnects; a dielectric capping layer in contact with the dielectric layer and conductive interconnects, and a portion of the diffusion barrier layer extending into the dielectric capping layer.

In a preferred embodiment the portion of the diffusion barrier layer extending into the capping layer may extend into only a portion of the dielectric capping layer. In another preferred embodiment the portion of the diffusion barrier layer extending into the capping layer extends into the entire thickness of the dielectric capping layer.

The conductive interconnect features may be lines and/or vias and are preferably Cu, W, Al, or alloys thereof. The dielectric layer preferably has a thickness of approximately 500 Å to approximately 10,000 Å. The diffusion barrier layer is preferably Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN.

The diffusion barrier layer preferably has a thickness of approximately 4 nm to approximately 40 nm. The dielectric capping layer is preferably Si3N4, SiC, SiCN, SiC(N,H) or SiCH. The portion of the diffusion barrier layer extending into the dielectric capping layer preferably has a height of approximately 5 nm to approximately 100 nm.

The present invention also provides a method for forming an interconnect structure, comprising the steps of: depositing a sacrificial dielectric film on a dielectric layer; forming patterned features in the dielectric layer; depositing a diffusion barrier layer in the patterned features; depositing a conductive metal on the diffusion barrier layer to form interconnect features; removing a portion of the conductive metal; removing the sacrificial dielectric film; and depositing a dielectric capping layer thereby embedding a portion of the diffusion barrier layer in the dielectric capping layer.

The diffusion barrier layer is preferably deposited by physical vapor deposition, atomic layer deposition, or chemical vapor deposition. The conductive interconnect features are preferably deposited by plating or sputtering. The portion of the conductive metal is preferably removed with a wet etch. In a preferred embodiment the wet etch is a time controlled dip in an etch solution consisting of HNO3, HCL, H2SO4, HF and combinations thereof.

The sacrificial dielectric film is preferably removed using a wet etch. In a preferred embodiment the wet etch is a dilute HF solution. The dielectric capping layer is preferably deposited by CVD deposition.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 2there is shown a sacrificial dielectric film11(also commonly referred to as a “hardmask”) deposited on an inter-layer dielectric (ILD) layer12. In a preferred embodiment the sacrificial dielectric film11is Si3N4or SiO2. The dielectric layer12may comprise any interlevel or intralevel dielectric including inorganic dielectrics or organic dielectrics. The dielectric material12may be porous or non-porous. Some examples of suitable dielectrics that can be used as the dielectric material include, but are not limited to: SiO2, silsesquioxanes, carbon doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like. Preferably the sacrificial film11has a thickness between 100 Å and 800 Å. Preferably the ILD layer12has a thickness between 500 Å and 10,000 Å.

Referring toFIG. 3patterned features21are formed in the ILD layer12through conventional lithography and etching processes. These patterned features will correspond to the subsequent interconnect vias or lines depending on whether a single or dual damascene structure is used.

The lithographic step includes applying a photoresist to the surface of the sacrificial dielectric film11, exposing the photoresist to a desired pattern of radiation, and developing the exposed resist utilizing a conventional resist developer. The etching step may comprise a dry etching process, a wet chemical etching process or a combination thereof. The term “dry etching” is used here to denote an etching technique such as reactive-ion-etching (RIE), ion beam etching, plasma etching or laser ablation. During the etching process, the pattern is first transferred to the sacrificial dielectric film11and then into the dielectric material12. The patterned photoresist is typically, but not necessarily, removed from the structure after the pattern has been transferred into the sacrificial dielectric film11.

The patterned features21formed into the dielectric material12may comprise a line opening, via opening or a combination of a line opening and a via opening. A single damascene or dual damascene process can be used as appropriate depending on the type of opening being formed. A first via then line opening process may be used, or a first line then via opening process may be used.

Referring toFIG. 4there is illustrated the structure after deposition of diffusion barrier layer31and conductive interconnect features32, followed by a chemical-mechanical polish (CMP). The conductive interconnect features32are interconnect vias and/or lines depending on whether a single or dual damascene structure is used. The diffusion barrier layer31is typically deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) techniques. The conductive interconnect features32are preferably plated Cu.

The diffusion barrier layer31, which may comprise Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or any other material that can serve as a barrier to prevent conductive material from diffusing through, is formed by a deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, chemical solution deposition, or plating. The thickness of the diffusion barrier layer31may vary depending on the exact means of the deposition process as well as the material employed. Typically, the diffusion barrier layer31has a thickness from approximately 4 nm to approximately 40 nm, with a thickness from approximately 7 nm to approximately 20 nm being more typical.

Following the diffusion barrier layer31formation, the remaining region of each of the openings21within the dielectric material12is filled with a conductive material thereby forming conductive interconnect features32. The conductive material used in forming the conductive interconnect features32includes, for example, polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide or combination thereof. Preferably, the conductive material that is used in forming the conductive interconnect features32is a conductive metal such as Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being a preferred embodiment in the present invention. The conductive material is filled into the recess features21in the dielectric material12using a conventional deposition process including, but not limited to: CVD, PECVD, sputtering, chemical solution deposition or plating.

After deposition of the conductive material, a conventional planarization process such as chemical mechanical polishing (CMP) can be used to provide a structure in which the diffusion barrier31and the conductive interconnects32each have an upper surface that is substantially coplanar with the upper surface of the dielectric material12. The resultant structure is shown for example inFIG. 4.

Referring toFIG. 5the structure is illustrated after a wet etch resulting in the recess of the Cu interconnect features32. This is preferably a time controlled dip in the etch solution. Preferred etch solutions include HNO3, HCL, H2SO4, HF or combinations thereof. As shown inFIG. 5, only the Cu interconnect32will be etched, and not the sacrificial dielectric film11or the diffusion barrier layer31.

Referring now toFIG. 6there is illustrated the removal of the sacrificial dielectric film11. This is preferably done using a wet etch. In a preferred embodiment the wet etch is dilute HF solution. As shown in the cross section view ofFIG. 6the Cu interconnect features32will now be surrounded by a section41of the diffusion barrier layer31protruding above the ILD layer12. This protruding section41will surround either the Cu interconnect vias or lines depending on whether a single or dual damascene structure is used. In a preferred embodiment the height of the section41protruding above the ILD layer12is approximately 5 nm to approximately 100 nm, the width will equal the diffusion barrier layer31deposition thickness.

As illustrated inFIGS. 5 and 6the first wet etch is tailored to etch on the Cu interconnect. The second wet etch is tailored to etch only the sacrificial dielectric film11.

Referring now toFIG. 7there is illustrated the deposition of a dielectric capping layer61. In a preferred embodiment the dielectric capping layer61is Si3N4, SiC, SiCN, SiC(N,H) or SiCH. The dielectric capping layer61is preferably deposited by CVD deposition or spin-on techniques. As shown inFIG. 6, the thickness of the dielectric capping layer61is greater than the height of the section41protruding above the ILD layer12. This results in a portion of the diffusion barrier layer31, the section41protruding above the ILD layer12, being partially embedded in the dielectric capping layer61.

Referring now toFIG. 8there is illustrated another embodiment of the present invention. In this embodiment an optional CMP step is performed to remove some of the thickness of the dielectric capping layer61in order to bring the surface of the dielectric capping layer61flush with the section41of the diffusion barrier layer31protruding above the ILD layer12. This results in section41of the diffusion barrier layer31completely embedded in the dielectric capping layer61as shown inFIG. 8.

Referring now toFIG. 9there is illustrated the deposition of ILD layer71for the next level interconnect build.FIG. 8illustrates the embodiment where a portion of the diffusion barrier layer31, the section41protruding above the ILD layer12, is only partially embedded in the dielectric capping layer61.FIG. 10illustrates the deposition of ILD layer71for the next level interconnect build where the section41protruding above the ILD layer12is completely embedded in the dielectric capping layer61.