Transistor structure with high input impedance and high current capability

An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The subject of the present invention is a transistor structure with high input impedance and high current capability.

Such structure can be used, for example, as a selection transistor for a phase change memory cell comprising, in addition to the selection transistor, also a phase change storage element.

2. Description of the Related Art

As is known, phase change storage elements comprise storage elements made of a class of materials having the unique property of switching in a reversible way between two phases having distinct and measurable electrical characteristics, associated to each phase. For example, these materials can switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase. In addition, these materials can assume a plurality of states, comprised between the amorphous state and the polycrystalline state, each associated to different electrical characteristics (typically, different electrical resistances).

The materials that can advantageously be used in phase change cells are alloys of elements of group VI of the periodic table, such as Te or Se, referred to also as calcogenides or calcogenic materials. Hence, hereinafter, the term “calcogenic material” is used to designate all the materials that can be switched between at least two different phases in which they have different electrical properties (resistances) and consequently include the elements of group VI of the periodic table and their alloys.

The currently most promising calcogenide is formed by an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is already widely used for storing information in overwritable disks.

The use of phase change storage elements has been already proposed in memory arrays formed by a plurality of memory cells arranged in rows and columns. In order to prevent the memory cells from being disturbed by the noise caused by adjacent memory cells, in general each memory cell comprises a phase change storage element and a selection element, such as a MOS transistor, a bipolar transistor, or a diode.

For example,FIG. 1shows a memory array1formed by a plurality of memory cells2arranged in rows and columns and connected to bitlines3(parallel to the columns of the memory array1) and wordlines4(parallel to the rows of the memory array1). Each memory cell2comprises a calcogenic memory element6and a selector element5, here formed by a MOS transistor. Each selector element5has its gate region connected to the respective wordline4, its source region connected to ground, and its drain region connected to a terminal of the calcogenic memory element6. Each calcogenic memory element6is connected between the respective selection element and the respective bitline3.

In the memory array1, in particular operating conditions, for example during the programming step, the bitlines3drain high currents. The ability to drain such high currents can be met using, as selection element, a bipolar transistor with a large area. On the other hand, for optimal operation, the selection transistor should present a high input impedance, typical of MOSFETs.

This dual objective is shared also by other applications where it is desirable to have a pull-down transistor capable of driving high currents and having a high input impedance.

The need thus exists of having a transistor structure capable of combining the characteristics indicated above of bipolar and transistors MOSFETs, without requiring a large integration area.

BRIEF SUMMARY OF THE INVENTION

One embodiment of the invention is an integrated transistor device that includes an electrical-insulation region, delimiting an active area in a semiconductor chip, and a bipolar transistor and a MOSFET formed in the active area in contiguous positions. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region accommodated in the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; and a channel region arranged between the source and drain regions. An insulated-gate region extends on top of the active area and on top of the channel region; and the drain region and bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and MOSFET.

DETAILED DESCRIPTION OF THE INVENTION

InFIG. 2, a pull-down transistor10comprises a bipolar transistor11and a MOSFET12integrated so as to obtain a single component having two terminals accessible from the outside. In detail, the bipolar transistor11is a PNP transistor, and the MOSFET12is of N-channel type, the transistors being integrated so that the pull-down transistor10has two external terminals: an emitter terminal E and a gate terminal G. In addition, the pull-down transistor10has two regions (collector region C and source region S) connected to ground. The base region B of the bipolar transistor11and the drain region D of the MOSFET12are connected together and are formed by the same physical regions, as described in detail hereinafter.

Since the input terminal of the pull-down transistor10is formed by the gate terminal G of the MOSFET12, the pull-down transistor10has a high input impedance. In addition, since the current-conduction terminal is the emitter terminal E and the current flows from the latter to ground mainly through the collector region C, the pull-down transistor10has substantially the current-driving capability of the bipolar transistor11. These electrical characteristics are obtained with a very compact structure which can be produced using a process that is compatible with the standard CMOS process and uses only one to three more masks than the standard process, as explained hereinafter.

FIG. 3is a cross-section of the simplified physical structure of the pull-down transistor10. The bipolar transistor11is of vertical type and is arranged next to the MOSFET12. The MOSFET12, of planar type, has a drain region formed by the base region, or more precisely, by a more doped portion of the base region (equivalent to the base-contact region in standard bipolar transistors, even though here this region is not connected to any contact).

In detail, the pull-down transistor10ofFIG. 3is formed in an active area30, delimited by a trench-insulation region31of a semiconductor body15. The semiconductor body15comprises a substrate16of P++ type (for example, with a doping level of 1019atoms/cm3); an epitaxial region17of P− type (for example, with a doping level of 1016atoms/cm3), on top of the substrate16; a collector region18of P+ type (for example, with a doping level of 1018atoms/cm3), next to the epitaxial region17; a base region19of N+ type (for example, with a doping level of 1018atoms/cm3), on top of the collector region18; and an emitter region20of P++ type (for example, with a doping level of 1020atoms/cm3), surrounded at the bottom by the base region19and laterally by the trench-insulation region31and by a surface portion19aof the base region19.

A well region35, of P type and a doping level of approximately 1017atoms/cm3, extends on top of the epitaxial region17, next to the base region19and, in part, to the collector region18.

The well region35accommodates a source region23, and, in part, a drain region24, both of N++ type (with a doping level of 1020atoms/cm3); the drain region24extends also in part in the base region19and forms simultaneously a base-contact region.

The ensemble formed by the base region19and the drain region24thus forms a common base structure, shared by the bipolar transistor11and by the MOSFET12.

The drain region24and source region23delimit a channel region22, an insulated-gate region26extends on top of the channel region22and is separated from the surface25of the semiconductor body15by a gate-oxide region60, and insulating spacers40are formed on the sides of the insulated-gate region26. Finally, a protection region28extends on top of a surface portion19aof the base region19.

The source region23is grounded (as represented symbolically), for example through a metallization (not shown).

In the pull-down transistor10, the physical design is structured to cause the bipolar transistor11to operate in forward active region with low charge injection (JE<105A/cm2) and thus obtain high gain and reduce the current IDS flowing through the MOSFET12. Thereby, also the MOSFET12can have small dimensions, and the pull-down transistor10can have extremely reduced overall dimensions.

In addition, the design provides minimum resistance between the collector region18and the back of the wafer. In fact, in this way, a self-biasing of the collector18and hence triggering of the SCR rectifier formed between the emitter region20and the source region23are prevented.

In these conditions, the current that flows in the bipolar transistor11is supplied by the substrate16and can even be high. In addition, the dimensions both of the bipolar transistor11and of the MOSFET12can be one tenth of those necessary for separate components connected in series.

The structure ofFIG. 3is thus able to provide the high input impedance and current conduction capability, without requiring a large area of integration.

Consequently, the pull-down transistor10finds advantageous application in small memory arrays that employ high programming currents (for example, integrated fuses), since it has a much more compact structure than a single MOSFET selector and does not require a current sink for the current from the wordline, thus simplifying the design of the row decoders.

In particular, the pull-down transistor10can be used as the selection transistor5in the memory array1ofFIG. 1, or else as a leaking path for wordlines and bitlines in a compact memory array or as a pull-down transistor in generic driving circuits, by connecting a load to the emitter terminal E.

An embodiment of the pull-down transistor10with silicided regions is shown inFIGS. 4 and 5, wherein the parts in common with those ofFIG. 3are designated by the same reference numbers.

In detail, inFIG. 4, LDD source and drain regions36,37(of an N+ type and a doping level of approximately 1018atoms/cm3) surround the respective source region23and drain region24, and silicide regions38coat the surface of the source23, drain24, emitter20, and gate26regions. Spacer regions40extend alongside the gate region26, on top of the LDD regions36,37, and a gate-oxide region60insulates the gate region26from the surface25.

As may be noted, the LDD drain region37is physically connected to the base region19and, also by virtue of the similar doping level, in practice forms a continuation of the base region19as far as the channel region22. Consequently, inFIG. 4, the common base structure comprises the regions19,24and37.

FIG. 5shows the top plan view of the structure ofFIG. 4, wherein the rectangular shape of the active area30is clearly visible, surrounded by the trench-insulation region31.

FIGS. 6 and 7show a split-gate embodiment. Here, the active area is formed by a plurality of strips (one of which is shown) and the source23, drain24, and emitter20regions alternate within each strip. In detail, two drain regions24are formed within each base region19, arranged on the two sides of the emitter region20, and two twin MOSFETs12extend on the two sides of each bipolar transistor11. With this structure, active area corners are prevented, which are always a possible source of defects.

FIGS. 8 and 9show a different embodiment, with circular emitter. In detail, as visible clearly from the top plan view ofFIG. 9, the emitter region20has a circular shape and is surrounded at a distance by the drain region24, which is thus approximately shaped as a circular ring (except in the portion adjacent to the gate region26, where it has a square portion). Otherwise, the rest of the MOSFET12is identical to that ofFIGS. 4 and 5. In this way, a structure is obtained, which is able to drive higher currents without crowding of the field lines at the corners of the emitter at the expense of a just slightly wider area. Said structure could advantageously be used, for example, in electrostatic-discharge (ESD) protection circuits.

The pull-down transistor10ofFIGS. 4-9is obtained in the way described hereinafter, with reference toFIGS. 10-24. In the ensuing description, specific reference will be made to the embodiment ofFIGS. 4 and 5; however, the same process steps enable the structures ofFIGS. 6-7and8-9to be obtained, by simply modifying the shape of the masks, as is evident to a person skilled in the art.

Initially, a shallow-trench insulation (STI) is obtained. In detail (FIG. 10), on a wafer45of semiconductor material, formed by a substrate16of P++ type and by an epitaxial layer46of P− type, an active-area mask47formed by a pad-oxide layer48and by a silicon-nitride layer49is deposited and defined. Using the active-area mask47, trenches50are dug for a depth of, for example, 300 nm. In particular, in the considered area, a trench50is dug, which surrounds a rectangular region (active area30).

Next (FIG. 11), the trenches50are filled by depositing insulating material, typically oxide. Then, the structure thus obtained is planarized, for example by CMP (Chemical Mechanical Polishing), a wet etch of the projecting oxide is performed, thus forming the trench-insulation region31, and the silicon-nitride layer49is removed.

Then (FIG. 12), a collector-implantation mask53is formed, which covers approximately half of the active area30, a boron collector/subcollector implantation is carried out (represented schematically by the arrows54), and a damage-recovering annealing is performed. In this way, the collector region18is obtained, which reaches the substrate16. Then (FIG. 13), using the same collector-implantation mask53, a base implantation of arsenic is performed (represented schematically by the arrows55) to obtain the base region19.

It should be noted that the collector/subcollector implantation54ofFIG. 12can be split into different steps (for example three) so as to obtain a higher dopant concentration in the deeper areas (in the proximity of the substrate16), in order to reduce the resistance between the collector region18and the substrate16, and so as to obtain a lower dopant concentration in the proximity of the base region19, in order to reduce the junction leakages and the breakdown. In particular, using different steps, a vertical, gradually variable concentration may be obtained.

Then some standard CMOS steps follow to provide the N-channel and P-channel MOS transistors until the polysilicon gate regions and the LDD implant are defined. In detail, as regards the pull-down transistor10(seeFIG. 14), a P-well mask57is provided and a boron implantation (represented schematically by the arrows58) is carried out to obtain the well region35.

It should be noted how the doping level of the P-well region35(1017atoms/cm3) ensures that any misalignment of the P-well mask57within the base region19and the collector region18does not modify significantly the doping level of these regions. For this reason, the P-well mask57is preferably made so as not to completely cover the base region19during the P-well implantation in the area where the latter borders on the P-well region35. Thus ensures the absence of low-doping regions between the P-well region35and the base region19(or the collector region18) even in case of any misalignment between the respective masking levels.

Afterwards, only the epitaxial region17remains of the original epitaxial layer46. Furthermore, in a way not shown, the N-well implantations are performed.

Next (FIG. 15), the insulated-gate region26is formed. In detail, first cleaning is carried out of the surface25of the wafer45, with removal of the pad-oxide layer48, then a gate-oxide layer60is grown, a polycrystalline-silicon layer26is deposited, the polycrystalline-silicon layer26and the gate-oxide layer60are defined, so as to form the gate region26and the gate-oxide region60, and a thermal re-oxidation is performed, which leads to the formation of a protective oxide layer61on top and at the sides of the gate region26and on top of the surface25.

Then (FIG. 16), using an LDD mask62that covers the bipolar area, an LDD implantation with arsenic (represented schematically by the arrows63) is carried out, so as to obtain the LDD source and drain regions36,37. In particular, the LDD drain region37is formed contiguous to the base region19(thanks also to the lateral diffusion) so as to form in practice a single region with the latter, also on account of the similar doping levels of the two regions.

To this aim, preferably the LDD mask62does not cover completely the base region19in the area where the latter borders on the P-well region35. By so doing, complete electrical connection between the LDD drain region37and the base region19is ensured even in presence of any misalignment between the respective masking levels.

At this point, the spacer forming step is modified with respect to the standard process to physically separate the emitter and base contacts of the bipolar transistor11. In detail (FIG. 17), first a spacer layer is deposited, for example of silicon oxide, silicon nitride or a combination of these layers, an appropriate mask (protection mask65) is formed on top of the base region19, and the spacer layer is etched anisotropically so as to form triangular portions67alongside the gate region26as well as to form the protection region28underneath the protection mask65. The same protection mask65can be used for other regions that must be protected by silicidation (for example, to form diffused resistors or polysilicon resistors without silicide).

Next (FIG. 18), an S/D implantation mask70is provided, which covers the area where the emitter region20is to be made, and a source/drain implant of arsenic or phosphorus is carried out (represented schematically by the arrows71). In particular, the S/D implantation mask70is aligned at the center of the protection region28so as to obtain the maximum alignment tolerance. In this way, the source23and drain24regions are obtained. In particular, and as indicated above, the drain region24forms a part of the common base structure and enables reduction in the base resistance of the bipolar transistor11. Prior to or following upon S/D implant71, the source/drain implants can moreover be carried out for other possible PMOS transistors in the same chip.

Then (FIG. 19), an emitter-implantation mask72is provided, which covers the MOSFET area of the active area30(source23, drain24and gate26regions) and an emitter implant of BF2/boron (represented schematically by the arrows73) is carried out. The emitter region20is thus obtained. It may be noted how, both during implantation of the source23and drain24regions and during implantation of the emitter region20, the capability of the protection layer28for blocking these implants is advantageous.

Then, an implant activation step follows, carried out with an RTP (Rapid Thermal Process) at 900° C.-1100° C., which causes a slight diffusion of the dopants. Alternatively, a partial activation can be performed before forming the emitter-implantation mask72, and then a separate emitter activation is performed after implantation of the emitter region20. In both cases, after the annealing step, the surface25is cleaned, thereby removing the exposed portions of the protective oxide layer61(on top of the source23, drain24, emitter20and gate26regions). In this step, the remaining portions of the protective oxide layer61and the triangular portions67form the spacer regions40ofFIG. 4. Then, silicidation of said regions is performed, via deposition of cobalt or titanium and thermal treatment, so as to form the silicide regions38shown inFIG. 4. The structure ofFIG. 4is thus obtained, which then is subjected to the customary final back-end steps for providing contacts, passivation, etc.

It is stressed that the protection layer28performs as many as three different tasks. It spaces the source23and well24regions from the gate region26; it blocks the implantations of the source23, well24and emitter20regions to keep them separate; finally, it resists silicidation to maintain the correct separation of the different electrical nodes of the structure.

The advantages of the integrated transistor device and of the corresponding process of manufacturing are evident from the above description.

Finally, it is clear that numerous modifications and variations can be made to the pull-down transistor and to the manufacturing process described and illustrated herein, all falling within the scope of the invention, as defined in the attached claims.

In particular, it is stressed that the described structure can implement a transistor of a dual type, including an NPN bipolar transistor and a P-channel MOSFET and having the electrical equivalent shown inFIG. 20. As may be noted, in this case it is necessary to connect the source region to the supply voltage Vcc. In addition, in the physical implementation, it is necessary to reverse all the types of conductivity shown inFIG. 4. Furthermore, it is advantageous to use a wafer45having a substrate of an N type or provide for a contact from the surface25towards the collector region18to collect the current. In this way, a pull-up transistor is obtained, in which the collector C would be connected to VCC, it being physically shorted to the N-well of the PMOS.

In addition, as regards the manufacturing process, the base implantation55can be performed simultaneously and using the same mask as the N-well implantation (not shown in the process illustrated inFIGS. 10-19, but present in the CMOS process). In this case, the base region would be thicker as compared to the one obtained with the described process, so that sizing would not be optimal and the efficiency of the bipolar transistor would be in part degraded. Furthermore, the STI regions (which are shallower than the drain regions) may cause insulation problems and higher risks of parasitic component activation may arise. This embodiment can consequently be used only in particular applications where, on account of the operating conditions, the voltages applied, or in general the specific conditions, the risks indicated are far from significant as compared to the advantage of a lower cost.

According to another embodiment, the emitter may be obtained during the S/D implant of the PMOS envisaged by the standard CMOS process. Also this solution enables saving one mask, and thus enables further reduction in costs, against a less optimal engineering of the emitter region.