Power sequencing

Methods and arrangements to establish power rails for a computer system in accordance with a sequence requirement are disclosed. Embodiments may interconnect voltage regulators for components of a platform in accordance with a sequence requirement for establishing power rails for proper operation of the platform. The voltage regulators may comprise enable inputs for enabling the establishment of power rails and power good signal outputs to indicate establishment of power rails. Some embodiments include interconnections to couple voltage regulators in a series of stages. Power good signals output by voltage regulators in one stage may enable inputs of voltage regulators in a subsequent stage. In many embodiments, such interconnections advantageously implement power sequence requirements with little or no need for glue logic and/or programmable logic devices, reducing costs and space requirements associated with implementing the power sequence. Other embodiments are disclosed and claimed.

FIELD

The present invention is in the field of computer systems. More particularly, the present invention relates to methods and arrangements to establish power rails for a computer system in accordance with a sequence requirement.

BACKGROUND

Early computer motherboards implemented a single voltage level, typically 5 volts, for use by the processor, chipset, and other components on the motherboard. As technologies for semiconductors scale down, designers scale voltage levels to reduce heat generation and power consumption. For instance, the voltages for power rails throughout the motherboard reduced from 5 volts to 3.3 volts. Newer components such as chipsets and processors operate at even lower voltages by using what is called a dual voltage, or split power rail design, which allows the internal components to operate at different voltage levels than interfaces for external components.

The transition from a single voltage level to multiple voltage levels led to the necessity of multiple voltage regulators on modern motherboards. The voltage regulators reduce the 5 volts signal to those voltages typically utilized by components such as 3.3 volts, 2.8 volts, 2.5 volts, 1.8 volts, and/or 1.5 volts. However, designers found that the increasing complexity of the platform design has led to conflicts between and within the components if the power rails are not established in a particular sequence.

The current solution for satisfying a design-dependent sequence requirement is to design logic such as discrete logic or to program programmable logic devices (PLDs) to coordinate powering of the power rails. The logic powers the power rails in accordance with the sequence requirement by enabling voltage regulators in a pre-determined order to assure that the platform operates properly. For example, sequence requirements of modern platforms typically require the power rails of a processor's core to be established after establishing the power rails for the processor's input-output (I/O) interface so the logic transmits an enable signal to the voltage regulator for the processor's I/O interface, awaits a power good signal from the voltage regulator, which is indicative of stabilization of the power rails for the processor's I/O interface, and then enables the voltage regulator for the processor's core. Sequence requirements of modern platforms typically require the power rails for a chipset core to be established before an I/O interface for the chipset.

Motherboards may include one or more discrete logic devices and/or PLDs to implement the pre-determined order for power rails. The problems with the current solution are that adding such logic devices adds cost to the design and consumes valuable board space to mount and to form connections between the logic device(s) and the voltage regulators for the platform. Further, designers spend a significant number of man-hours designing, programming, and debugging the logic.

DETAILED DESCRIPTION OF EMBODIMENTS

Generally speaking, methods and arrangements to establish power rails for a computer system or platform in accordance with a sequence requirement are contemplated. Embodiments may interconnect voltage regulators for components of a platform in accordance with a sequence requirement for establishing power rails for proper operation of the platform. The voltage regulators may comprise enable inputs for enabling the establishment of power rails and power good signal outputs to indicate establishment of power rails. In some embodiments, interconnections are formed on a circuit board to couple voltage regulators in a series of stages. Power good signals output by voltage regulators in one stage may couple with enable inputs of a voltage regulator in a subsequent stage in an order based upon the sequence requirement. In several embodiments, stages may include two or more voltage regulators may be connected in parallel. In other embodiments, the voltage regulators may be connected in series. In many embodiments, such interconnections advantageously implement power sequence requirements with little or no need for glue logic and/or programmable logic devices, reducing costs and space requirements associated with implementing the power sequence.

Many embodiments comprise a clock driver. The clock driver may be enabled after power rails for one or more of the chipset components are established. Further embodiments generate a system power good signal after establishing power rails in accordance with the sequence requirement to initiate initial program loads (IPLs). Some of these embodiments generate the system power good signal upon expiration of a delay after establishing power rails.

While portions of the following detailed discussion describes embodiments of the invention with reference to particular orders and sequence requirements for specific platforms, persons of ordinary skill in the art will recognize that embodiments may be implemented on other platforms with different sequence requirements.

Turning now to the drawings,FIG. 1illustrates an embodiment of a system100that includes one or more circuit boards to mount and interconnect a power supply102with components such as processors114and116, a memory controller hub (MCH)111, an input-output controller hub (ICH)140, and the like to power the components in an order based upon a sequence requirement for system100. For instance, the power rails for power supply102are established prior to enabling other components of system100. Once the power rails for the power supply are established, which is typically identified by substantial stabilization of the voltages of the power rails at steady-state levels, power supply102outputs a power good signal, PS_PWRGD, to initiate a first stage of a powering sequence. The powering sequence is designed to establish power rails for components in an order, which is based upon the sequence requirement. In particular, the powering sequence involves powering sets of components in stages to enforce the sequence requirement although not every component associated with the stages may be subject to the sequence requirement.

The first stage of the powering sequence for the present embodiment establishes power rails for direct current to direct current (D2D) voltage level converters104,106, and108. More specifically, upon receipt of PS_PWRGD from power supply102, ICH D2D104is enabled and begins to establish a new power rail at a direct current (DC) voltage level that is converted from an input DC voltage. For example, power supply102may connect a 5 volt output with an input of ICH D2D104and, when enabled, ICH D2D104generates a 1.5 volt power rail for ICH140. After the 1.5 volt power rail stabilizes, ICH D2D104may output a power good signal, ICH_PWRGD. The state of ICH_PWRGD is indicative of establishment of the 1.5 volt power rail.

MCH D2D106may be a DC to DC voltage level converter that outputs a 1.5 volt power rail for MCH111. ICH_PWRGD is received by MCH D2D106at an enable input, to enable MCH D2D106in response to the power good signal from ICH D2D104. In some embodiments MCH D2D106may generate the 1.5 volt output based upon a 5 volt power rail input from power supply102. In the present embodiment, when ICH D2D104outputs the power good signal, ICH_PWRGD, MCH D2D106is enabled by the signal and begins to convert the DC voltage level of an input power rail. Upon establishing the 1.5 volt power rail for MCH111, MCH D2D106outputs a power good signal, MCH_PWRGD, to enable a 1.8 volt D2D108. 1.8 volt D2D108may then output a power good signal, PWRGD_1_8V, when a 1.8 volt power rail is established to initiate a second stage of the powering sequence.

In the second stage of the powering sequence, a central processing unit (CPU) termination voltage (VTT) voltage regulator module (VRM)110receives the power good signal, PWRGD_1_8V, and, in response, enables CPU VTT VRM110and generates a power good signal, VTT_3_3V PWRGD, to a delay circuit112.

Delay circuit112may initiate a count upon receipt of the power good signal and generate a second power good signal, VTT_PWRGD, upon expiration of the count. For example, delay circuit112may implement a 1 millisecond to 10 millisecond delay based upon an input or a setting. In other embodiments, delay circuit112may implement a fixed delay.

Delay112output VTT-PWRGD which is used, to enable voltage regulator downs (VRDs)120and124for processors114and116to initiate a third stage of the powering sequence. In the third stage, voltage regulators downs120and124may lower DC voltage levels of input power rails for use by cores of processors114and116, respectfully. For example, CPU1VRD120may reduce a 5 volt power rail input from power supply102to a 2.5 volt power rail for the core of processor114and output a power good signal, CPU1_VRD_PWRGD, upon establishing the 2.5 volt power rail. Similarly, CPU0VRD124may reduce a 5 volt power rail input from power supply102to a 2.5 volt power rail for the core of processor116and output a power good signal, CPU0_VRD_PWRGD, upon establishing the 2.5 volt power rail.

A glue logic126may receive the power good signals, CPU0_VRD_PWRGD and CPU1_VRD_PWRGD, and may generate another power good signal, CPU_VRD_PWRGD based upon the power good signals, CPU0_VRD_PWRGD and CPU1_VRD_PWRGD. In some embodiments, glue logic126may determine the number of processors actually mounted and await power good signals from each of the mounted processors prior to outputting CPU_VRD_PWRGD. In other embodiments, glue logic126may take into consideration the state of additional or other signals.

The power good signal, CPU_VRD_PWRGD, may initiate fourth and fifth stages of the powering sequence. In the fourth stage, receipt of the power good signal, CPU_VRD_PWRGD, may enable a Peripheral Component Interconnect Express (PCI-E) clock driver132, a CPU clock synthesizer134, and a chipset clock driver136. For PCI-E clock driver132may be a clock driver such as a DB800 clock driver chip to drive a clock signal for synchronizing data transfers between a graphics accelerator card (not shown) and MCH111.

CPU clock synthesizer134may be a clock synthesizer chip such as clock synthesizer chip CK410B for processors114and116to synchronize transactions across the front-side bus. And chipset clock driver136may be a clock driver chip for a chipset such as a DB1200G clock driver chip.

In the fifth stage, delay circuit128receives the power good signal, CPU_VRD_PWRGD, and, in response, initiates a delay count. Upon expiration of the delay count, delay circuit128outputs a platform power good signal, SYS_PWRGD_3_3V.

The platform power good signal, SYS_PWRGD_3_3V, may be fed to ICH140, a delay/reset logic142, and a reset logic152. Receipt of the platform power good signal by ICH140may enable ICH140. Receipt of the platform power good signal by delay/reset logic142may enable I/O slots144after a delay via a power good signal, IO_SLOT_PWRGD, in the absence of a reset signal. For instance, I/O slots144may respond to IO_SLOT_PWRGD by establishing communications from an IDE controller146, a SCSI controller148, and a PCI/PCI-E controller150to ICH140to facilitate upbound and downbound transactions with I/O devices.

FIG. 2depicts an embodiment of voltage regulators (VRs) for components of a platform200. The powering sequence for the platform is an order that starts with stage A and ends after stage F with a platform power good signal, SYS_PWRGD.FIG. 2focuses on components that establish power rails associated with a powering sequence or order that is based upon a sequence requirement for the platform200. For instance, some embodiments may include other logic in series and/or in parallel with voltage regulators depicted inFIG. 2.

The powering sequence for platform200begins with a VR210in stage A. An initial enable signal, INPUT_EN, enables VR210and, in response, VR210begins to establish a power rail. Upon establishing the power rail, VR210produces an output signal, VR_PWRGD, which is indicative of establishment of the power rail. In some embodiments, the initial enable signal may, for instance, comprise or be based upon a power good signal produced by a power supply. In further embodiments, the initial power good signal may be based upon an output from other logic.

Stage B comprises VR220and VR222through VR228. VR220and VR222through VR228all have their respective enable inputs connected in parallel to the output, VR_PWRGD of VR210. As a result of this interconnection, VR220and VR222through VR228are enabled when VR210establishes the power rail and VR_PWRGD is driven high by VR210.

The outputs of VR220and VR222through VR228are connected via a wired “OR”, which produces a power good signal VRB_PWRGD when all of the VRs220and222through228establish power rails and outputs power good signals. For example, if logical zeros are output by VR220and VR222through VR228when their corresponding power rails are established, the wired “OR” will output a logical zero once all of these power rails are established. On the other hand, for embodiments in which a logical one is output in response to establishing a power rail, the wired “OR” will output a logical one when the power rails are established. VRB_PWRGD will be high when VR220, VR222through VR228all have stable power and all power good signals are driven high.

Stage C begins in response to receipt of VRB_PWRGD. Stage C produces a power good output signal, VRC_PWRGD, once VR230establishes a power rail.

Stage D comprises VR240and VR242. Both VR240and VR242receive VRC_PWRGD at substantially the same time and responsively begin to establish power rails for platform200. Similar to stage B, the outputs of VR240and VR242electrically connect to form a wired “OR” logic that outputs a power good signal, VRD_PWRGD, based upon a power good signal output from VR240and VR242. In other embodiments, discrete logic may be utilized in place of the wired “OR” logic. In further embodiments, other logic may be implemented and/or further signals may be utilized to determine the signals to input into one or more of the stages.

In stage E, VR250receives the power good signal at an enable input and, in response, enables establishment of a power rail. Once VR250establishes the power rail, VR250produces a power good signal, VRE_PWRGD.

The power good signal, VRE_PWRGD, enables system power good logic260of stage F. System power good logic260may output a platform power good signal, SYS_PWRGD, which is indicative of establishment of at least the power rails necessary for operation of platform200. For example, the output of SYS_PWRGD may trigger the initial program loads (IPLs) to begin the process of booting platform200.

In some embodiments, system power good logic260may comprise delay circuitry to ensure that key power rails have substantially reached steady-state voltage levels. In further embodiments, system power good logic260may base the output of SYS_PWRGD signals other than and/or in addition to signal VRE_PWRGD. In other embodiments, system power good logic260may comprise logic such as AND, OR, NAND, NOR, and/or other logic.

While stages A through F may order the establishment of power rails to meet a sequence requirement, one or more of the components associated with the stages may be powered in this order for convenience rather than out of necessity. For example, the sequence requirement may force VR228to be powered prior to powering VR250and after powering VR210. In such embodiment, VR228may be powered at any stage between stage A and stage E.

As a further illustration, VR222may not be subject to the sequence requirement for platform200. For instance, the power rail(s) established by VR222may be for an auxiliary input-output device, which does not effect the operation of other components of platform200. Thus, the power rail(s) of VR222may be established before, during, or after booting platform200.

In a further embodiment, monitor logic may receive the power good signals for one or more of the stages to monitor the powering sequence. The monitor logic may output an indication of the sequence of establishing power rails, the timing for establishing the power rails, and/or the like. For instance, in the event of a failure of one of the VRs to produce a power good signal, the monitor logic may report the list of power good signals generated to indicate the location of the faulty VR.

FIG. 3depicts an embodiment of a powering sequence/timing diagram300for a platform such as platform200illustrated inFIG. 2. In this embodiment, the input enable signal is a power good signal, PS_PWRGD, generated by the power supply. As column310indicates, the power supply takes between 100 milliseconds and 1 second to establish a power rail and once the power rail is established, the power supply generates the power good signal, PS_PWRGD. The power good signal, PS_PWRGD, enables VR210to initiate stage A.

When a power rail is established by VR210after about 1 to 10 milliseconds according to column315, VR210generates a power good signal, VR_PWRGD. The power good signal, VR_PWRGD, is transmitted to VR220and VR222through VR228of stage B. Prior to establishing power rails, VR220and VR222through VR228maintain their respective power good outputs at a logical zero. Thus, the wired “OR” interconnection between the power good outputs from VR220and VR222through VR228combine to be a logical zero until all the power rails for VR220and VR222through VR228are established. Once all the power rails are established, which takes approximately 1 to 20 milliseconds in accordance with columns320and325, the wired “OR” arrangement produces a logical one output for VRB_PWRGD to enable VR230of stage C.

As indicated in column330, VR230establishes a power rail within 1 to 10 milliseconds of enablement by VRB_PWRGD and then generates a power good signal, VRC_PWRGD. The power good signal VRC_PWRGD enables VR240and VR242of stage D. VR240and VR242establish power rails within 1 to 10 milliseconds as indicated by column335and then the wired “OR” produces a combined power good signal VRD_PWRGD.

The combined power good signal, VRD_PWRGD, enables VR250to initiate stage E of the powering sequence. VR250establishes a power rail in 1 to 10 milliseconds in accordance with column340and enables logic260of stage F via a power good signal VRE_PWRGD. Within 100 milliseconds to 1 minute as indicated by column345, logic260produces a platform power good signal, SYS_PWRGD, which boots platform200.

Note that the time periods indicated in column310through345are for illustrative purposes. Time periods associated with the stages are dependent upon the components enabled in the stages and may vary significantly between various embodiments from those indicated inFIG. 3.

FIG. 4depicts a flowchart400of an embodiment to establish power rails in accordance with sequence requirement for a platform. In particular, flowchart400describes turning on a power supply of the platform (element410). The power supply may be one of a number of power supplies or may be a single power supply designed to handle the power requirements of the platform. In some embodiments, the power supply may supply one or more positive and negative voltages to power components of the platform.

When turned on, the power supply begins to convert power from an alternating current power source into one or more DC power rails such as 12 volts, 5 volts, and the like. Upon establishing, for instance, a stable 5 volt power rail, the power supply may generate a power good signal to initiate the first stage of a powering sequence to power components of the platform in an order based upon the sequence requirement for the platform (element415). For instance, in response to establishing the power rail, the power supply may transition an output for the power supply power good signal from a logical zero to a logical one.

One or more circuit boards of the platform interconnect the output for the power supply power good signal with an enable power input for one or more voltage regulators associated with a first stage of the powering sequence. As a result, when the power supply power good signal transitions from a logical zero to a logical one, the interconnections in the one or more circuit boards apply the logical one to the enable power inputs of the one or more voltage regulators (element420), which enables the one or more voltage regulators.

Upon enabling the one or more voltage regulators, the one or more voltage regulators begin to establish component power rails. When the component power rails substantially stabilize at steady-state DC voltage levels, the one or more voltage regulators generate a component power good signal (element425) and the component power good signal for the first stage of components propagates to a subsequent stage of the powering sequence to apply the component power good signal to components associated with the subsequent stage for the platform (element430).

Elements425and430repeat for additional stages, if there are more stages (element435). Once power rails associated with the stages of the powering sequence are substantially established, one or more clock drivers and/or clock synthesizers may be enabled via one of the component power good signals (element440). In other embodiments, the one or more clock drivers and/or clock synthesizers may be initiated in parallel with one or more of the stages of the powering sequence.

After at least the necessary power rails are established and the clock signals are generated for, e.g., the front-side bus, the processors, the chipset, and/or the like, system logic may generate a platform power good signal to indicate that the platform is ready to boot (element445).

FIG. 5depicts a flowchart500an embodiment to form interconnections on a circuit board to establish power rails in accordance with a powering sequence requirement. In particular, flowchart500describes forming a first set of conductors to interconnect a power supply with more than one voltage regulators, to supply power to the more than one voltage regulators (element510). Element515further describes forming a second set of conductors to interconnect power good signal outputs of the more than one voltage regulators with enable inputs of the more than one voltage regulators to enable the more than one voltage regulators to establish power rails in an order based upon a sequence required for establishment of the power rails for the platform. For instance, stand alone voltage regulators or voltage regulators integrated into components of the platform may be associated with an order based upon a sequence requirement for the platform by associating the components with stages of a powering sequence. Then, enabling each stage of the powering sequence in the appropriate order ensures that the order in which power rails are established for the components are in accord with the sequence requirement.

To enable each stage in the appropriate order, interconnections are formed on the circuit board to connect the power good output of an earlier stage in the sequence with an enable input of a voltage regulator in a latter stage of the sequence. Each stage may then be connected in this series of stages to ensure that, regardless of the timing involved with establishing power rails a particular stage, the subsequent stage will not be enabled until the power rails are sufficiently stabilized to generate a power good signal output.

In addition to forming interconnections for the voltage regulators, conductors may be formed to interconnect an output for a system power good signal with a clock circuit to enable the clock circuit (element520). The system power good signal may be indicative of the establishment of the more than one power rails associated with the sequence requirement so the clock circuit may be enabled to establish communications busses between the components such as the front-side bus or a high speed serial bus.

One or more conductors may also be formed on the circuit board to interconnect the output for the system power good signal with a delay circuit and couple with an output of the delay circuit. Such interconnections facilitate transmission of a platform power good signal responsive to the system power good signal after a delay to other components of the platform to, e.g., boot the platform.

Another embodiment of the invention is implemented as a program product for use with a system to perform processes such as the processes described in conjunction with flowcharts400and500as illustrated inFIGS. 4 and 5. The program(s) of the program product defines functions of the embodiments (including the methods described herein) and can be contained on a variety of data and/or signal-bearing media. Illustrative data and/or signal-bearing media include, but are not limited to: (i) information permanently stored on non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive); (ii) alterable information stored on writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive); and (iii) information conveyed to a computer by a communications medium, such as through a computer or telephone network, including wireless communications. The latter embodiment specifically includes information downloaded from the Internet and other networks. Such data and/or signal-bearing media, when carrying computer-readable instructions that direct the functions of the present invention, represent embodiments of the present invention.

It will be apparent to those skilled in the art having the benefit of this disclosure that the present invention contemplates systems and arrangements to establish power rails for a computer system in accordance with a sequence requirement. It is understood that the form of the invention shown and described in the detailed description and the drawings are to be taken merely as examples. It is intended that the following claims be interpreted broadly to embrace all the variations of the embodiments disclosed.