Active device divider circuit with adjustable IQ

An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

BACKGROUND

A quiescent current (IQ) of an integrated circuit (IC) is an operating current required to operate an IC's basic functionality, such as for example, powering an internal precision reference voltage, an oscillator, a thermal shutdown circuit, a state machine or other logic gates. IQ is generally defined as the current drawn by an IC in a no-load and nonswitching but enabled condition. The IQ travels inside the IC to ground. In a no load condition, typically, no current leaves the IC to an output terminal. In a nonswitching condition, typically, no power switch in the IC is on (closed). For some ICs, this means that the IC is in a high-impedance condition with a power stage that is disconnected from the output, except perhaps for certain IC components such as integrated MOSFET body diodes that cannot be turned off. In an enabled condition, typically, the IC is turned on and is not in a shutdown condition.

A voltage divider circuit includes multiple voltage load components, across which voltage drops, which are coupled in series between a first node and a second node. Voltage is measured at junctions between the voltage load components. A bias voltage is applied to the first node. A voltage at each junction is proportional to the voltage drop across the series-connected electrical components disposed between that junction and the second node.

FIG. 1is an illustrative drawing representing a resistor voltage divider circuit102that includes multiple resistors coupled in series. The exampled resistor voltage divider circuit includes resistors R1to Rkthat each acts as a resistor load voltage coupled in series between a first node and a second node. A divider output voltage is provided at a junction between two resistors coupled between the first and second nodes. The first node104is coupled to a bias voltage Vout. The second node106is coupled to ground. For example, a third node108is shown at a junction between resistors Rk-xand Rk-x-1. The divider output voltage at the third node is equals the voltage drop across the k-x-1resistors coupled between Rk-xand ground divided by a total voltage drop across all k resistors. Typically, a resistor voltage divider in an IC includes diffused resistors coupled in series to provide divided voltage outputs at junctions between the resistors. Unfortunately, such a structure ordinarily requires a relatively surface large area, which is not preferred in an IC.

FIG. 2is an illustrative drawing representing an active device voltage divider circuit202that includes multiple active devices coupled in series. Active voltage divider circuits have been provided that include multiple active field effect transistor (FET) devices Mn1-Mnk, each having its gate coupled to its drain. The multiple FET devices are coupled in series form a chain of FET devices to provide divided voltage outputs at junctions between them. The function of each series-connected FET device is the same as a resistor in a resistor voltage divider although its I-V curve is not linear and typically its area is much less than resistor to realize the same IQ. For example, a divider voltage output voltage at the drain of FET device Mn2equals the voltage drop across the FET devices coupled between the drain of Mn2and ground divided by a total voltage drop across all k FET devices. An active device voltage divider typically occupies less IC area to realize a given IQ than would a resistor divider. However, IQ for an active device voltage divider circuit can vary significantly with semiconductor manufacturing process corner changes.

SUMMARY

In one aspect, an active voltage divider circuit is provided. Multiple FET load devices are coupled in series between the first node and the second node. Multiple first switches, each associated with a different FET load device are configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device. Second switch circuitry is configured to selectably couple a drain of a FET load device from among the multiple FET load devices to the third node. Multiple second switches, each associated with a different FET load device, are configured to selectably couple a drain of its associated FET load device to the third node.

In another aspect, a method is provided to configure an active divider circuit that includes a series-connected chain of FET load devices to produce a target value for a quiescent current (IQ) in response to the first node being coupled to a first voltage value (V1) and the second node being coupled to a voltage value (V2). A number of respective bypass circuits are coupled between source and drain of associated FET load devices of the chain so as to electrically remove those associated FET load devices from the divider circuit so as to configure the series-connected chain of FET load devices to produce the target value for the quiescent current (IQ), when the first node is coupled to the first voltage value (V1) and the second node is coupled to the voltage value (V2). A drain of a FET load device, selected from among one or more of the k FET load devices, is coupled to target divider voltage value (V3) to the third node.

DESCRIPTION OF EMBODIMENTS

The following description is presented to enable any person skilled in the art to create and use an active device divider circuit with adjustable IQ. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Moreover, in the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention might be practiced without the use of these specific details. In other instances, well-known processes are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. Identical reference numerals may be used to represent different views of the same or similar item in different drawings. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

FIG. 3is an illustrative transistor level diagram of an active voltage divider circuit302in accordance with some embodiments. Multiple field effect transistor (FET) devices are coupled in a series-connected chain of FET devices303between a first node304and a second node306. Each FET device of the series-connected chain has its drain coupled to its gate. In accordance with some embodiments, the drain has a short circuit coupling to its gate. A FET device with its drain coupled to its gate is referred to herein as a FET load device. During design each FET load device is implemented as an individual design cell. Assuming that the voltage divider circuit302includes k FET load devices coupled in series, a kth FET load device Mk of the series has its drain coupled to the first node304. A first FET load device M1of the series has its source coupled to the second node306. Each of a second FET load device M2to a (k−1)thFET load device M(k−1) of the series has its drain coupled to a source of an adjacent FET load device of the series that is closer to the first node304and has its source coupled to a drain of an adjacent FET load device of the series that is closer to the second node306.

In operation, the first node304is coupled to receive a first voltage (V1) and the second node306is coupled to receive a second voltage (V2). A total voltage drop across the voltage divider circuit is V1−V2. Assuming that the voltage divider circuit includes k FET load devices, a portion of the total voltage drop across each individual FET load device in the voltage divider circuit is,
(V1−V2)/k(1)

More specifically, the voltage drop across each FET load device, having its drain coupled to its gate, is the gate-to-source voltage drop across the device, Vgs-cell, which in some embodiments, is identical for each FET device coupled in series in voltage divider circuit. Therefore,
Vgs-cell=(V1−V2)/k(2)

The voltage divider circuit302includes first switch circuitry S1configured to selectably operatively electrically insert or electrically remove individual FET devices from the series. In operation, each FET load device contributes its gate-to-source voltage drop to the overall voltage drop (V1−V2). The larger the number of FET load devices inserted in series, the smaller the voltage drop across each individual FET device. Conversely, the smaller the number of FET load devices inserted in series, the larger the voltage drop across each individual FET load device.

The first switch circuitry S1, in accordance with some embodiments, includes multiple individual first switches, S11-S1k, each associated with a different FET load device of the series-coupled FET load devices. Each individual first switch is configured to selectably switch between a first switch state and a second switch state. In some embodiments, each individual first switch includes at least one FET device (not shown), which is selectably controlled using a signal provided to its gate terminal. In some embodiments, switching an individual first switch between first and second states includes providing a control signal to a gate of the first device. In the first switch state, an individual first switch electrically inserts its associated FET load device in series with the other series-coupled FET load devices by open circuiting a bypass circuit current path between the source and drain of the associated FET load device. In a second switch state, the individual first switch electrically removes its associated FET load device from series coupling with the other series-coupled FET devices by closing a bypass current path that provides a short circuit current path between the source and drain of the associated FET load device.

The voltage divider circuitry302includes second switch circuitry S2to selectably operatively electrically couple a third node308to a drain of a selectable one of the first through kth FET load devices of the series-coupled FET load devices. In operation, assuming that the second switch circuitry couples a drain of device Mk-x coupled to the third node308, a divider output equals a voltage drop (V3) between the drain of the (k−x)thFET load device of the series-connected FET devices and V2, which is,
V3=(V1−V2)(k−x)/k(3)
The larger the value of x, the farther the nthFET device of the series-coupled FET load devices is from the first node, and the closer the xthFET load device in the series-coupled FET load devices is to the first node, and the smaller the voltage drop between the third node and the second node. Conversely, the smaller the value of n, the closer the xthFET load device of the series-coupled FET load devices is to the first node, and the farther the xthFET load device in the series-coupled FET devices is from the first node, and the larger the voltage drop between the third node and the second node.

The second switch circuitry S2, in accordance with some embodiments, includes multiple individual second switches S21-S2k-1, each associated with a different FET load device of the series-coupled FET load devices. Each second switch is controllable to switch between a first switch state and a second switch state. In some embodiments, each individual second switch includes at least one FET load device (not shown), which is selectably controlled using a signal provided to its gate terminal. In some embodiments, switching an individual second switch between first and second states includes providing a control signal to a gate of the second device. In some embodiments, the second switch circuitry S2includes a multiplex circuit that includes multiple input terminals each coupled to a drain of a different FET load device and including an output terminal coupled to the third node308. In the first switch state, an individual second switch operatively electrically coupled to a drain of its associated FET load device with the third node308. In the second switch state, the individual second switch operatively electrically decouples the drain of its associated FET load device from the third node308.

The value of IQ that flows between the series-coupled FET load devices of the active divider circuit302ofFIG. 3is represented by the following expression.

IQ=μn⁢VT2⁡(n-1)⁢Cox⁢W/L*ⅇVgs-cell-VthnVT(4)
The parameter to represents charge mobility; VT=kT/q, (where k is Boltzmann's constant, T is temperature and q is unit charge); W represents gate width; L represents gate length; n represents sub-threshold region coefficient; Coxrepresents the gate oxide capacitor; gate-to-source voltage drop across the device, Vgs-cellrepresents gate-to-source voltage drop; and Vthrepresents threshold voltage.

The value of a threshold voltage Vthof a FET load device can vary with changes in semiconductor manufacturing process corners. Persons skilled in the art will appreciate that a FET load device having a smaller threshold voltage value Vthgenerally switches faster than a similar FET device having a larger threshold voltage value Vth. Series-coupled FET load devices within a given active divider circuit ordinarily have about the same threshold voltages in accordance with some embodiments.

FIG. 4is an illustrative graph representing simulation of IQ values over a range of temperatures for an active device divider circuit302shown inFIG. 3in accordance with some embodiments. The “nominal” curve represents a voltage divider circuit with series-coupled FET load devices each having a nominal threshold voltage. A nominal threshold voltage is a threshold voltage that a manufacturing process is designed to produce, as contrasted with a threshold voltage at a manufacturing process corner. The “fast” curve represents a voltage divider circuit with series-coupled FET load devices each having lower than nominal threshold voltage. The “slow” curve represents a voltage divider circuit with series-coupled FET load devices each having higher than nominal threshold voltage. At all temperatures, IQ is highest for the fast, low Vth, devices, is lowest for the slow, high Vth, devices and is in between the two for the nominal, nominal Vth, devices. Thus, semiconductor manufacturing process variations can result in manufacture-related variations of threshold voltage Vth, from one voltage divider to the next, which in turn, can result in manufacture-related variation of IQ, from one voltage divider to the next. Often, however, it is desirable to maintain target IQ, such as a nominal value IQ, that is sufficient provide sufficient power to provide basic functionality and that is low so as to conserve power, for example.

FIG. 5is an illustrative graph representing simulation of divider output values over a range of temperatures for an active device divider circuit of the general type shown inFIG. 3in accordance with some embodiments. The fast, low Vth, divider circuit has the least variation of divider output voltage V3with temperature. The slow, high Vth, divider circuit has the greatest variation of divider output voltage V3with temperature. The nominal, nominal Vthdivider circuit has a variation of divider output voltage V3with temperature that falls between the other two. The marked region of the graph near −40 degrees C. indicates that too small an IQ at low temperature will damage the accuracy of divider due to the influence of leakage current as described with reference toFIG. 7.

FIG. 6is an illustrative transistor level diagram representing coupling among terminals of a FET load device in accordance with some embodiments. Each FET load device includes an isolated MOSFET, which includes an NMOS device in a deep nwell. Alternatively, a PMOS device can be used in some embodiments. A body (B) of the FET is coupled to the source terminal. In accordance with some embodiments, the isolation (ISO) is coupled to a voltage, such as the highest voltage in the circuit so as to avoid forward bias of Dib. For an isolated NMOS device, the ISO is a deep nwell, and body is a pwell. The electrical coupling between body (B) and source results in a diode Dbdbetween body and drain, a diode Dsbbetween body and source, a diode Dibbetween body and ISO, and diode Digis the diode between ISO and substrate and substrate is usually connected to ground.

FIG. 7is an illustrative transistor level diagram diagrams representing the series-connected chain303of FET load devices ofFIG. 3showing IQ and leakage currents in accordance with some embodiments. Each FET load device has a first leakage current Leak′, which is a drain to source leakage current. Each FET load device also has a second leakage current ILeak2, from the ISO to the source. The second leakage currents ILeak2in the series-connected devices accumulate as current flows from one the FET load device to the next. For example, the kth FET load device has a source current of I(k)=IQ+ILeak1+ILeak2. However, the first FET load device has a source current of I(k)=IQ+ILeak1+K*ILeak2. Thus, the second leakage current ILeak2has accumulates by a factor of approximately k as current flows through the k series-connected FET load devices from device Mk to device M1.

Referring again to equation (4), it will be appreciated that since IQ is larger for fast, lower Vth, devices and that IQ is smaller for slow higher Vth, devices, leakage current is larger relative to IQ slow, higher Vth, devices than it is relative to fast, lower Vthdevices. Thus, leakage current has a larger value relative to IQ for slow, higher Vthdevices, which can result in current of bottom cell (M1) being larger than current of the top cell Mk, which can result in the V3being larger than its target value, for example.

Also, it will be appreciated from equation (4) that, for a given threshold voltage value Vth, IQ increases with an increasing value of Vgs-celland decreases with a decreasing value of Vgs-cell. Moreover, it will be appreciated that Vgs-cell per FET load device varies with the number of FET load devices coupled in series between V1and V2. The total voltage drop across all series-connected FET load devices is (V1−V2), and the voltage drop across each FET load device is,
Vgs-cell=(V1−V2)/NS1(5)

The parameter NS1is the number of FET load devices electrically inserted in series in the active divider circuit by switch circuitry S1.

FIGS. 8A-8Care illustrative transistor circuit diagrams representing the series-connected chain303of FET load devices ofFIG. 3configured with different example switch states of individual first switches, S11-S145, to insert different numbers of FET load devices in series so as to achieve substantially the same IQ for active divider circuits having FET load devices with different threshold voltages, in accordance with some embodiments. The different threshold voltage, Vth, values for different divider circuits may result from different process corners during IC fabrication, for example. In the examples ofFIGS. 8A-8CandFIGS. 9A-9C, it is assumed that the target IQ is 1.4 nA; V1=3V; V2=ground; target V3=1.2V; W/L=40 μm/0.5 μm; and mvt 3V NMOS as the unit FET load device. In accordance with some embodiments, mvt 3V means a medium VthmosFET for 3V maximum voltage. Since 3V is the smallest Vthdevice that can be obtained for some manufacturing processes, it is the value used to get best resolution in the divider structure for some embodiments.

In the examples ofFIGS. 8A-8C, the switch states of the individual first switches S11-S145, which are coupled in series, are selected during a trimming operation. One or more individual first switches may be switched to a second switch state to electrically couple respective short circuit bypass paths between source and drain of their associated FET load devices to thereby trim, i.e. electrically remove, their associated FET load devices from the active divider circuit. Other individual first switches are switched to the first switch state to open-circuit respective short circuit bypass paths between source and drain of their associated FET load devices to thereby electrically insert their associated FET load devices in the active divider circuit. In order to determine which FET load devices to trim, i.e. remove, and which to insert, In some embodiments, an active divider circuit is tested at normal operating temperature to determine the states of first switch circuitry and second switch circuitry. More particularly, in accordance with some embodiments, a voltage source and a current meter are connected to the active divider circuit to test the IQ in normal temperature to determine how many cells are electrically inserted in the series-connected chain303and how many are electrically removed from the series-connected chain303.

FIG. 8Ais an illustrative transistor circuit diagram representing switch states of individual first switches to insert a first number of FET load devices in series so as to achieve a target IQ for an example active divider circuit having FET load devices with nominal threshold voltage, in accordance with some embodiments. Example simulation results were obtained for 25 degrees C. The example simulation results show, for example, that switching first switches S11-S130to the first state to electrically insert thirty FET load devices M1-M30in series, and switching first switches S131-S145to the second state to remove FET load devices M31-M45from the series, results in IQ=1.4 nA, which matches the target IQ. It is noted, for example, that first switch S131associated with FET load device M31is in the second switch state, which is closed state in some embodiments, to thereby couple a short circuit bypass path80231between source and drain of M31to thereby electrically remove M31preventing it from acting as a load during operation of the active divider circuit.

FIG. 8Bis an illustrative transistor circuit diagram representing switch states of individual first switches to insert a second number of FET load devices in series so as to achieve the target IQ for an example active divider circuit having “fast” FET load devices with lower than nominal threshold voltage, in accordance with some embodiments. Example simulation results were obtained for 25 degrees C. The example simulation results show, for example, in which process corner performance is set so that results are that in the fast corner simulation, which is the worst case. In the example fast FET devices, first switches S11-S145are switched to the first state to electrically insert forty-five FET load devices M1-M45in series, and none of the first switches S11-S145is switched to the second state to remove none of the FET load devices M1-M45from the series, results in IQ=1.3 nA, which within an acceptable tolerance range in this example. It is noted, for example, that first switch S130associated with FET load device M30is in the first switch state, which is an open state in some embodiments, to thereby open-circuit to decouple a bypass path80230from between source and drain of M30to thereby electrically insert M30so that it acts as a load during operation of the active divider circuit.

FIG. 8Cis an illustrative transistor circuit diagram representing switch states of individual first switches to insert a third number of FET load devices in series so as to achieve the target IQ for an example active divider circuit having “slow” FET load devices with higher than nominal threshold voltage, in accordance with some embodiments. Example simulation results were obtained for 25 degrees C. The example simulation results show, for example, in which process corner performance is set so that results are that in the slow corner simulation, which is the worst case. In the example slow FET devices, first switches S11-S123are switched to the first state to electrically insert twenty-three FET load devices M1-M23in series, and twenty-one of the first switches S124-S145are switched to the second state to remove twenty-one of the FET load devices M24-M45from the series, results in IQ=1.2 nA, which is within an acceptable tolerance range in this example.

Referring toFIG. 8Aand equation (4), it will be appreciated that in the “nominal” example, with thirty FET devices M1-M30coupled in series, the Vcg-cellfor each device is (V2−V1)/30. Referring toFIG. 8Band equation (4), it will be appreciated that, in the “fast” example, with forty-five FET devices M1-M45coupled in series, the Vcg-cellfor each device is (V2−V1)/45. Thus, the lower value of Vcg-cellfor each device resulting from the first switch configuration ofFIG. 8Bcompensates for the lower threshold voltage Vthof each device relative to the nominal threshold voltage. Conversely, referring toFIG. 8Cand equation (4), it will be appreciated that, in the “slow” example, with twenty-three FET devices M1-M23coupled in series, the Vcg-cellfor each device is (V2−V1)/23. Thus, the larger value of Vcg-cellcell for each device resulting from the first switch configuration ofFIG. 8Ccompensates for the higher threshold voltage Vthof each device relative to the nominal threshold voltage.

FIG. 9A-9Care illustrative transistor circuit diagrams representing the series-connected chain303of FET load devices ofFIG. 3configured with different example switch states of individual second switches, S21-S245, which are coupled in parallel, to electrically couple the drain of different selected FET load devices the third node308to achieve a target V3value for active divider circuits having FET load devices with different threshold voltages, in accordance with some embodiments. The switch states for the second switch circuitry S2are selected following determination of switch states for the first switch circuitry S1in accordance with some embodiments. More particularly, in accordance with some embodiments, switch states of the second switch circuitry are selected to achieve a target V3value as a function of the number of FET load devices electrically inserted in series using the first switch devices in accordance with the following relationship.
V3=(V2−V1)*NS2/NS1(6)
The parameter NS2is the number of FET load devices electrically coupled in series to the third node.

FIG. 9Ais an illustrative transistor circuit diagram representing switch states of individual second switches to insert a first number of FET load devices in series to the third node so as to achieve a target V3value for the first switch configuration for the “nominal” example ofFIG. 8A, in accordance with some embodiments. Specifically, S212is in the first switch state, which acts to couple a drain of device M12to the third node. All other second switches are in the second switch state. Thus, for the nominal example, V3=(3V)*12/30=1.2V.

FIG. 9Bis an illustrative transistor circuit diagram representing switch states of individual second switches to insert a second number of FET load devices in series to the third node so as to achieve a target V3value for the first switch configuration for the “fast” example ofFIG. 8B, in accordance with some embodiments. Specifically, S218is in the first switch state, which acts to couple a drain of device M18to the third node. All other second switches are in the second switch state. Thus, for the fast example, V3=(3V)*18/45=1.2V.

FIG. 9Cis an illustrative transistor circuit diagram representing switch states of individual second switches to insert a third number of FET load devices in series to the third node so as to achieve a target V3value for the first switch configuration for the “slow” example ofFIG. 8C, in accordance with some embodiments. Specifically, S29is in the first switch state, which acts to couple a drain of device M9to the third node. All other second switches are in the second switch state. Thus, for the fast example, V3=(3V)*9/23=1.17V, which is assumed to be within an acceptable tolerance range in this example.

The foregoing description and drawings of embodiments in accordance with the present invention are merely illustrative of the principles of the invention. Therefore, it will be understood that various modifications can be made to the embodiments by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.