Current limiting surge protection device

A current-limiting surge protection device is provided. The current-limiting surge protection device includes a pair of series connected normally on MOSFET's and a pair of voltage controlled normally off switches that are disposed to monitor a voltage across the normally on MOSFET pair. Here, the voltage controlled normally off switches close according to an excess threshold voltage across the MOSFET pair and reduces a gate drive potential of the normally on MOSFET pair to limit a current through the normally on MOSFET pair.

FIELD OF THE INVENTION

The invention relates generally to electronic devices. More particularly, the invention relates to current-limiting surge protection devices using series connected normally on MOSFET's and voltage controlled normally off switches.

BACKGROUND

In most electrical protection applications, it is essential for the protecting device to switch to a state where current flow into the protected equipment is substantially blocked or limited. This general observation holds for various protection approaches, such as fuses, circuit breakers, and transient blocking units (TBUs).

Current limiters can be utilized when the resulting power dissipation during a fault protection condition is limited to a level that is insufficient to cause damage to the current limiting device.

In VDSL applications100, such as inFIG. 1a, the driver102is AC coupled by virtue of the transformer, and hence long term short circuit currents at the line side cannot cause sustained DC currents in the driver. A current limiting protection device can therefore be advantageously used to protect the driver.

Whereas a TBU will drastically reduce the output current when the current rises above a certain threshold, a current limiter will limit the current at a particular level, thus preventing excessive currents in the driver in the event of a transient. As the transient is short lived, by virtue of the AC coupling, a sustained fault due to lightning or power cross cannot cause problems of over dissipation in the current limiter.

FIG. 1bshows a graph of a generally poor linearity of a prior art current limiting device, where it is known that a changing gate drive to both the forward and reversed transistor elements causes modulation of the transistor resistances. Consequently, the linearity error may become significant at currents above about 50% of the required limiting threshold.

What is needed is a current limiting device that provides area savings, cost reduction and improvement in resistance compared to the use of a standard TBU. Further, there is a need for a solution for protecting low voltage drivers in the VDSL application for example, where low resistance, good linearity and fast response is key.

SUMMARY OF THE INVENTION

To overcome the shortcomings in the art, the present invention provides a current-limiting surge protection device having a pair of series connected normally on MOSFET's and a pair of voltage controlled normally off switches that are disposed to monitor a voltage across the normally on MOSFET pair. Here, the voltage controlled normally off switches close according to an excess threshold voltage across the MOSFET pair and reduces a gate drive potential of the normally on MOSFET pair to limit a current through the normally on MOSFET pair.

According to one embodiment of the invention, the current-limiting surge protection device further includes gate protection of the pair of voltage controlled normally off switches, where the gate protection has a first diode clamp disposed between a first normally off voltage controlled switch and a first terminal and a second diode clamp disposed between a second normally off voltage controlled switch and a second terminal.

According to one aspect of the invention, the normally on MOSFET is a depletion mode MOSFET. Here, the depletion mode MOSFET can be an NMOS or a PMOS.

In another aspect, the voltage controlled normally off switch is at least one enhancement mode MOSFET. Here, the enhancement mode MOSFET can be an enhancement mode NMOS or an enhancement mode PMOS, selected in accordance to the depletion mode device.

According to another embodiment, a drain of a first normally on MOSFET is connected to a first terminal and a drain of a second normally on MOSFET is connected to a second terminal, where a gate of the first normally on MOSFET is resistively connected to the first terminal and a gate of the second normally on MOSFET is resistively connected to the second terminal. Here, the gate of the first normally on MOSFET is further connected to a source of a first normally off enhancement mode MOSFET and the gate of the second normally on MOSFET is further connected to a source of a second normally off enhancement mode MOSFET. Additionally, a gate of the first normally off enhancement mode MOSFET is resistively connected to the first terminal and a drain of the first normally off enhancement mode MOSFET is connected to the second terminal and a gate of the second normally off enhancement mode MOSFET is resistively connected to the second terminal and a drain of the second normally off enhancement mode MOSFET is connected to the first terminal.

In one aspect of this embodiment, the gate of the first normally off enhancement mode MOSFET is further connected to the second terminal by a first diode clamp and the gate of the second normally off enhancement mode MOSFET is further connected to the first terminal by a second diode clamp.

In another aspect of this embodiment, the normally on MOSFET is a depletion mode MOSFET, where the depletion mode MOSFET can be an NMOS or a PMOS.

In yet another aspect of the current embodiment, the voltage controlled normally off switch is an enhancement mode MOSFET, where the enhancement mode MOSFET can be an enhancement mode NMOS or an enhancement mode PMOS.

According to another embodiment of the invention, the voltage controlled normally off switch is a pair of series connected enhancement mode MOSFET's, where a drain of a first normally on MOSFET is connected to a first terminal and a drain of a second normally on MOSFET is connected to a second terminal, and a gate of the first normally on MOSFET is resistively connected to the first terminal and a gate of the second normally on MOSFET is resistively connected to the second terminal. Here, the gate of the first normally on MOSFET is further connected to a drain of a first normally off enhancement mode MOSFET and a source of the first normally off enhancement mode MOSFET is connected to a source of a second normally off enhancement mode MOSFET and a drain of the second normally off enhancement mode MOSFET is connected to the second terminal, where the gate of the second normally on MOSFET is further connected to a drain of a third normally off enhancement mode MOSFET and a source of the second normally off enhancement mode MOSFET is connected to a source of a fourth normally off enhancement mode MOSFET and a drain of the fourth normally off enhancement mode MOSFET is connected to the first terminal. Additionally, a gate of the first normally off enhancement mode MOSFET is resistively connected to the first terminal and further connected to a gate of the second normally off enhancement mode MOSFET and the gate of the second normally off enhancement mode MOSFET is further connected to the second terminal comprising a first diode clamp, where a gate of the third normally off enhancement mode MOSFET is resistively connected to the second terminal and further connected to a gate of the fourth normally off enhancement mode MOSFET and the gate of the fourth normally off enhancement mode MOSFET is further connected to the first terminal by a second diode clamp. Further, a substrate of the first normally off enhancement mode MOSFET is connected to a substrate of the second normally off enhancement mode MOSFET and further connected to the source of the first normally on MOSFET and a substrate of the third normally off enhancement mode MOSFET is connected to a substrate of the fourth normally off enhancement mode MOSFET and further connected to a source of the second normally on MOSFET.

According to one aspect of this embodiment, the normally on MOSFET is a depletion mode MOSFET, where the depletion mode MOSFET can be an NMOS or a PMOS.

According to another aspect of this embodiment, the enhancement mode MOSFET can be an enhancement mode NMOS or an enhancement mode PMOS.

DETAILED DESCRIPTION OF THE INVENTION

Although the following detailed description contains many specifics for the purposes of illustration, anyone of ordinary skill in the art will readily appreciate that many variations and alterations to the following exemplary details are within the scope of the invention. Accordingly, the following preferred embodiment of the invention is set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.

A current limiter is a device that limits the flow of current through it to be less than some predetermined value. Thus, the main difference between a current limiter and more typical protection devices is that a current limiter doesn't actually turn off when its threshold is reached or exceeded.

The present invention is a new type of current limiting device for blocking short duration transients. It is particularly useful in low cost data-line protection applications, such as VDSL.

According to one embodiment, the current limiting device is a simple, lowest cost device, suitable for many applications where linearity is not a critical concern. The devices of the current invention provide better linearity, at only minimal cost in area and process complexity compared to what is known in the art, utilizing a reversed enhancement mode NMOS to detect the voltage across the limiter, and then reducing gate drive, hence providing a limited ‘trip’ function. The invention also provides better control of the depletion mode gate voltage, and hence results in better linearity, at only minimal cost in area and process complexity compared to prior art versions. According to one embodiment, using a composite of a normally connected and a reverse connected NMOS devices makes no special requirement for the NMOS design, and can use standard LDMOS type designs with source connected to substrate. This design provides the best peak current to high voltage current, and is lowest cost to manufacture. It is understood that NMOS devices are used as exemplary devices, where these devices are MOSFET devices that can be an NMOS or a PMOS devices.

The invention provides area savings, cost reduction and improvement in resistance compared to the use of a standard TBU, for example.

FIG. 2shows a generic current-limiting surge protection device200according to the current invention, having a pair of series connected normally on MOSFET's202and a pair of voltage controlled normally off switches204that are disposed to monitor a voltage across the normally on MOSFET pair202. Here, the voltage controlled normally off switches204close according to an excess threshold voltage across the MOSFET pair202and reduces a gate drive potential of the normally on MOSFET pair202to limit a current through the normally on MOSFET pair202.

As opposed to the poor performance of the prior art current limiting device shown inFIG. 1b, the current limiting function of the current invention provides perfect protection for the driver, as the output current is limited to well within the capabilities of the output driver.

The current limiter of the current invention offers advantages over the conventional TBU protection because the total resistance is only controlled by the two MOSFET's, rather than the NMOS and a series PJFET—more than 40% of the typical low voltage TBU resistance. It can be seen therefore that the current limiter allows a device that is smaller, lower resistance, and lower cost than the existing protection devices.

For some applications involving analog-based signal transmission, linearity is a critical concern. An improved limiter circuit300suitable for these applications is shown inFIG. 3a, and with additional gate protection inFIG. 3b. In this implementation, two small enhancement mode devices302and304are connected in such a way that enhancement mode NMOS304is normally off when a positive voltage is applied across the device300. Note that302is reverse biased across its source and drain, and is initially off.

As shown inFIGS. 3aand3b, a drain302of a first normally on MOSFET304is connected to a first terminal306and a drain308of a second normally on MOSFET310is connected to a second terminal312, where a gate314of the first normally on MOSFET304is resistively connected to the first terminal306and a gate316of the second normally on MOSFET310is resistively connected to the second terminal312. Here, the gate314of the first normally on MOSFET304is further connected to a source318of a first normally off enhancement mode MOSFET320and the gate316of the second normally on MOSFET310is further connected to a source322of a second normally off enhancement mode MOSFET324. Additionally, a gate326of the first normally off enhancement mode MOSFET320is resistively connected to the first terminal306and a drain328of the first normally off enhancement mode MOSFET320is connected to the second terminal312and a gate330of the second normally off enhancement mode MOSFET324is resistively connected to the second terminal312and a drain332of the second normally off enhancement mode MOSFET324is connected to the first terminal306.

As shown inFIG. 3b, the gate326of the first normally off enhancement mode MOSFET320is further connected to the second terminal312by a first diode clamp334and the gate330of the second normally off enhancement mode MOSFET324is further connected to the first terminal306by a second diode clamp336. It is understood that the embodiments of current limiter of the present invention can be bi-directional as shown, or unidirectional (not shown).

For example, when a surge occurs, the voltage dropped across the two normally-on depletion mode NMOS,304and310, due to the surge current, rises such that it turns on the reversed NMOS320. This causes this reverse NMOS320to turn on, thus reducing the gate drive to306. This results in an increase in resistance of304, and hence a drop of around 30% in the current compared to the peak402, as shown inFIG. 4, where also shown is a constant current404level controlled by a DM device.

This enhanced current limiter achieves a significant degree of current reduction, thus further reducing stress on the application. In addition, in normal use, the gate drive to the NMOS304is such that the resistance change of the NMOS304is minimal with increased current, considerably improving the linearity of the device for sensitive analog applications, as shown inFIG. 5, where shown, the linearity at 70% of the limiting current is seen to be only 2%, compared to the prior art having 15% shown inFIG. 1b.

The circuits shown inFIGS. 3a-3bperform the function of the improved current limiter, but in practice may be difficult to realize due to the possible interactions through the resistive substrate connection in a monolithic device. SOI techniques may be used to provide isolation, but this may be an undesirable additional cost to the device.

To overcome this problem, the current limiter circuit600shown inFIG. 6having enhancement mode devices in series with control transistors can be used.

As shown, the voltage controlled normally off switch is a pair of series connected enhancement mode MOSFET's, where a drain602of a first normally on MOSFET604is connected to a first terminal606and a drain608of a second normally on MOSFET610is connected to a second terminal612, and a gate614of the first normally on MOSFET604is resistively connected to the first terminal606and a gate616of the second normally on MOSFET610is resistively connected to the second terminal612. Here, the gate614of the first normally on MOSFET604is further connected to a drain618of a first normally off enhancement mode MOSFET620and a source622of the first normally off enhancement mode MOSFET620is connected to a source624of a second normally off enhancement mode MOSFET626and a drain619of the second normally off enhancement mode MOSFET620is connected to the second terminal, where the gate616of the second normally on MOSFET610is further connected to a drain628of a third normally off enhancement mode MOSFET630and a source632of the second normally off enhancement mode MOSFET630is connected to a source634of a fourth normally off enhancement mode MOSFET636and a drain638of the fourth normally off enhancement mode MOSFET636is connected to the first terminal606. Additionally, a gate640of the first normally off enhancement mode MOSFET620is resistively connected to the first terminal606and further connected to a gate642of the second normally off enhancement mode MOSFET626and the gate642of the second normally off enhancement mode MOSFET624is further connected to the second terminal612by a first diode clamp644, where a gate646of the third normally off enhancement mode MOSFET630is resistively connected to the second terminal612and further connected to a gate648of the fourth normally off enhancement mode MOSFET636and the gate648of the fourth normally off enhancement mode MOSFET636is further connected to the first terminal606by a second diode clamp650. Further, a substrate652of the first normally off enhancement mode MOSFET620is connected to a substrate654of the second normally off enhancement mode MOSFET626and further connected to the source656of the first normally on MOSFET604and a substrate658of the third normally off enhancement mode MOSFET630is connected to a substrate660of the fourth normally off enhancement mode MOSFET636and further connected to a source662of the second normally on MOSFET.

For example, in this implementation, additional enhancement mode NMOS602and604are used in series with the control transistors606and608. The enhancement mode transistors602and604may use floating source type process e.g. such as an SOI type as before.

Alternatively, and preferably for cost and ease of processing, the NMOS602and604may all be of a more conventional LDMOS (not shown) design, where the substrate and source are connected. In this case, there is a simple requirement that the substrate must be of sufficiently high resistivity that the current drawn through the substrate connection to606causes negligible voltage drop across606when it turns on. This requirement is easily accommodated by appropriately sizing the devices606and608with substrates that are used in typical NMOS-type process designs.

As before, gate protection to the enhancement mode devices provided by the resistor/Zener diode clamp.

The addition of the 2 NMOS602and604now allows greater control of the gate of depletion mode device, as the positive extreme of the gate voltage (of say610) is not limited by the diode action of the reversed enhancement mode NMOS606. This results in higher trip current to high voltage current, as shown inFIG. 7. It is understood that though the above exemplary embodiments are bi-directional, embodiments unidirectional are within the scope of the current invention.

The present invention has now been described in accordance with several exemplary embodiments, which are intended to be illustrative in all aspects, rather than restrictive. Thus, the present invention is capable of many variations in detailed implementation, which may be derived from the description contained herein by a person of ordinary skill in the art.

All such variations are considered to be within the scope and spirit of the present invention as defined by the following claims and their legal equivalents.