Integrated low noise amplifier

An integrated circuit (IC) low noise amplifier includes an on-chip balun and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single-ended signal into a differential signal. The on-chip differential amplifier is operably coupled to amplify the differential signal.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to communication systems and more particularly to radio receivers used within such communication systems.

BACKGROUND OF THE INVENTION

For each wireless communication device to participate in wireless communications, it includes a built-in radio transceiver (i.e., receiver and transmitter) or is coupled to an associated radio transceiver (e.g., a station for in-home and/or in-building wireless communication networks, RF modem, etc.). As is known, the receiver receives RF signals, demodulates the RF carrier frequency from the RF signals via one or more intermediate frequency stages to produce baseband signals, and demodulates the baseband signals in accordance with a particular wireless communication standard to recapture the transmitted data. The transmitter converts data into RF signals by modulating the data in accordance with the particular wireless communication standard to produce baseband signals and mixes the baseband signals with an RF carrier in one or more intermediate frequency stages to produce RF signals.

To recapture data from RF signals, a receiver includes a low noise amplifier, down conversion module and demodulation module. For radio frequency integrated circuits, it is desirable to provide the low noise amplifier with differential RF signals instead of single ended RF signals to improve noise performance and common mode rejection. To convert received single ended RF signals into differential RF signals, a receiver includes a balun (i.e., a balanced/unbalanced transformer).

Until very recently, the baluns were off-chip, i.e., on the printed circuit board, and were typically implemented in the form of micro-strip lines. Recent attempts to integrate a balun onto a radio frequency integrated circuit have had limited success. For example, parallel winding, inter-wound winding, overlay winding, single planar, square wave winding, and concentrical spiral winding on-chip baluns have been tried with limited success. Each of these on-chip baluns suffers from one or more of: low quality factor, (which causes the balun to have a relatively large noise figure); too low of a coupling coefficient (which results in the inductance value of the balun not significantly dominating the parasitic capacitance making impedance matching more complex); asymmetrical geometry (which results in degradation of differential signals); and a relatively high impedance ground connection at the operating frequency.

Therefore, a need exists for an integrated low noise amplifier that includes a symmetrical balun that has a low noise figure, low ground impedance at the operating frequency and has an inductance value that is dominant at the operating frequency.

SUMMARY OF THE INVENTION

The integrated circuit low noise amplifier disclosed herein substantially meets these needs and others. In one embodiment, an integrated circuit (IC) low noise amplifier includes an on-chip balun and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single-ended signal into a differential signal. The on-chip differential amplifier is operably coupled to amplify the differential signal.

In another embodiment, an integrated circuit (IC) radio receiver includes a low noise amplifier, a down conversion module, and a filtering module. The low noise amplifier is operably coupled to amplify a radio frequency (RF) signal to produce an amplified RF signal. The down conversion module is operably coupled to convert the amplified RF signal into a baseband signal. The filtering module is operably coupled to filter the baseband signal. The low noise amplifier includes an on-chip balun operably coupled to convert a single-ended signal into a differential signal and an on-chip differential amplifier operably coupled to amplify the differential signal.

DETAIL DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1illustrates a schematic block diagram of a communication system10that includes a plurality of base stations and/or access points12–16, a plurality of wireless communication devices18–32and a network hardware component34. The wireless communication devices18–32may be laptop host computers18and26, personal digital assistant hosts20and30, personal computer hosts24and32and/or cellular telephone hosts22and28. The details of the wireless communication devices will be described in greater detail with reference toFIG. 2.

The base stations or access points12are operably coupled to the network hardware34via local area network connections36,38and40. The network hardware34, which may be a router, switch, bridge, modem, system controller, et cetera provides a wide area network connection42for the communication system10. Each of the base stations or access points12–16has an associated antenna or antenna array to communicate with the wireless communication devices in its area. Typically, the wireless communication devices register with a particular base station or access point12–14to receive services from the communication system10. For direct connections (i.e., point-to-point communications), wireless communication devices communicate directly via an allocated channel.

Typically, base stations are used for cellular telephone systems and like-type systems, while access points are used for in-home or in-building wireless networks. Regardless of the particular type of communication system, each wireless communication device includes a built-in radio and/or is coupled to a radio. The radio includes an integrated low noise amplifier as disclosed herein to enhance performance of radio frequency integrated circuits.

FIG. 2illustrates a schematic block diagram of a wireless communication device that includes the host device18–32and an associated radio60. For cellular telephone hosts, the radio60is a built-in component. For personal digital assistants hosts, laptop hosts, and/or personal computer hosts, the radio60may be built-in or an externally coupled component.

As illustrated, the host device18–32includes a processing module50, memory52, radio interface54, input interface58and output interface56. The processing module50and memory52execute the corresponding instructions that are typically done by the host device. For example, for a cellular telephone host device, the processing module50performs the corresponding communication functions in accordance with a particular cellular telephone standard.

Radio60includes a host interface62, a receiver section, a transmitter section, local oscillation module74, an antenna switch73, and an antenna86. The receiver section includes a digital receiver processing module64, analog-to-digital converter66, filtering/gain module68, down conversion module70, receiver filter module71, low noise amplifier72, and at least a portion of memory75. The transmitter section includes a digital transmitter processing module76, digital-to-analog converter78, filtering/gain module80, up-conversion module82, power amplifier84, transmitter filter module85, and at least a portion of memory75. The antenna86may be a single antenna that is shared by the transmit and receive paths via the antenna switch73or may include separate antennas for the transmit path and receive path and omit the antenna switch. The antenna implementation will depend on the particular standard to which the wireless communication device is compliant.

The digital receiver processing module64and the digital transmitter processing module76, in combination with operational instructions stored in memory75, execute digital receiver functions and digital transmitter functions, respectively. The digital receiver functions include, but are not limited to, digital intermediate frequency to baseband conversion, demodulation, constellation demapping, decoding, and/or descrambling. The digital transmitter functions include, but are not limited to, scrambling, encoding, constellation mapping, modulation, and/or digital baseband to IF conversion. The digital receiver and transmitter processing modules64and76may be implemented using a shared processing device, individual processing devices, or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions. The memory75may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing module64and/or76implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the corresponding operational instructions is embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry.

In operation, the radio60receives outbound data94from the host device via the host interface62. The host interface62routes the outbound data94to the digital transmitter processing module76, which processes the outbound data94in accordance with a particular wireless communication standard (e.g., IEEE 802.11a, IEEE 802.11b, Bluetooth, et cetera) to produce digital transmission formatted data96. The digital transmission formatted data96will be a digital base-band signal or a digital low IF signal, where the low IF will be in the frequency range of zero to a few megahertz.

The digital-to-analog converter78converts the digital transmission formatted data96from the digital domain to the analog domain. The filtering/gain module80filters and/or adjusts the gain of the analog signal prior to providing it to the up-conversion module82. The up-conversion module82directly converts the analog baseband or low IF signal into an RF signal based on a transmitter local oscillation provided by local oscillation module74. The power amplifier84amplifies the RF signal to produce outbound RF signal98. The antenna86transmits the outbound RF signal98to a targeted device such as a base station, an access point and/or another wireless communication device.

The radio60also receives an inbound RF signal88via the antenna86, which was transmitted by a base station, an access point, or another wireless communication device. The antenna86provides the inbound RF signal88to the low noise amplifier72, which amplifies the signal88in accordance with the teachings of the present invention, which will be described in greater detail with reference toFIGS. 3–5, to produce an amplified inbound RF signal. The low noise amplifier72provide the amplified inbound RF signal to the down conversion module70, which directly converts the amplified inbound RF signal into an inbound low IF signal based on a receiver local oscillation provided by local oscillation module74. The down conversion module70provides the inbound low IF signal to the filtering/gain module68, which filters and/or adjusts the gain of the signal before providing it to the analog to digital converter66.

The analog-to-digital converter66converts the filtered inbound low IF signal from the analog domain to the digital domain to produce digital reception formatted data90. The digital receiver processing module64decodes, descrambles, demaps, and/or demodulates the digital reception formatted data90to recapture inbound data92in accordance with the particular wireless communication standard being implemented by radio60. The host interface62provides the recaptured inbound data92to the host device18–32via the radio interface54.

As one of average skill in the art will appreciate, the radio may be implemented a variety of ways to receive RF signals and to transmit RF signals and may be implemented using a single integrated circuit or multiple integrated circuits. Further, at least some of the modules of the radio60may be implemented on the same integrated circuit with at least some of the modules of the host device18–32. Regardless of how the radio is implemented, the concepts of the present invention are applicable.

FIG. 3illustrates a schematic block diagram of an integrated circuit low noise amplifier72that includes a line impedance matching circuit100, an on-chip balun102, and an on-chip differential amplifier104. The line impedance matching circuit100, which will be described in greater detail with reference toFIG. 4, receives a single ended signal106(e.g., a singled ended RF signal88) via an input line108from the antenna. The line impedance matching circuit100provides an impedance, in conjunction with the primary winding of the balun102, to substantially match the impedance of the antenna at the operating frequency, or frequencies, of the antenna. Typically, an antenna will have a 50 OHM impedance at the operating frequencies. Correspondingly, the line impedance matching circuit100in conjunction with the primary of the on-chip balun102will have an impedance of approximately 50 OHMS at the same frequencies.

The on-chip balun102, which may be a symmetrical on-chip balun as described in co-pending patent application BP 2095 entitled ON-CHIP TRANSFORMER BALUN, having a filing date of Jan. 23, 2002, and a Ser. No. of 10/055,425. The primary winding of the on-chip balun is operably coupled to the line impedance matching circuit100to receive the single ended signal106. The secondary is center tapped to produce a differential signal110from the single ended signal106. The center tap connection is tied to one node of the primary, which in turn is coupled to the ground of the integrated circuit low noise amplifier72, which may be done through a ground circuit that may be in the line impedance matching circuit or a separate circuit. While the on-chip balun102may have a noise figure that is greater than an off-chip balun, the noise figure of the on-chip balun102is reduced to more than acceptable levels by providing gain within the on-chip balun102. For example, the on-chip balun may have a turns ratio of 2:9, where the center tap splits the nine turns of the secondary. To further improve the performance of the on-chip balun102, the primary may include three shunted primary windings to minimize Ohmic losses.

The on-chip differential amplifier104is operably coupled to receive the differential signal110via AC coupling capacitors C1and C2, which are sized to block low frequency signals and to pass high frequency signals. The on-chip differential amplifier104includes resistor R3, inductors L1, L2, L3and L4, and transistors T1, T2, T3and T4. Transistors T3and T4provide the differential input for the on-chip differential amplifier104and are biased in the linear region via resistors R1and R2to a low noise amplifier bias value114. The design of transistor T3in conjunction with the inductance of L3is tuned to provide impedance matching with the output of the on-chip balun102. Similarly, transistor T4and inductor L4are designed to provide impedance matching with the output of balun102. Further, the inductors L3and L4have a relatively low Q, while transistors T3and T4have a large transconductance (Gm) value to provide a wide frequency range of operation while maintaining a relatively constant impedance. Still further, the parasitic capacitances of transistors T3and T4are sized with respect to the inductance values of L3and L4to have an insignificant contribution to the impedance of the input of the differential amplifier104at the operating frequencies. Transistors T1and T2are biased via a bias voltage116. As configured, the on-chip differential amplifier104produces an amplified differential signal112from the differential signal110.

FIG. 4illustrates a schematic block diagram of the line impedance matching circuit100and the on-chip balun102. As shown, the line impedance matching circuit100includes capacitors C3and C4and a ground circuit122. The ground circuit122may be implemented utilizing a capacitor C5. The capacitors C3and C4are tuned with respect to the inductance value of the on-chip balun to provide the desired input impedance at a particular operating frequency range for the IC low noise amplifier and, in addition, to provide gain. The particular operating frequency range may be from 2.4 gigahertz plus or minus 10%, 5.2–5.75 gigahertz plus or minus 10% and/or any other operating range that is used to transceive RF signals.

To simplify the impedance matching to include two capacitors, the on-chip balun102is designed such that its impedance at the operating frequencies is primarily determined by its inductances and not its parasitic capacitance. This is achieved by providing a sufficient coupling coefficient as further described in co-pending patent application entitled ON-CHIP TRANSFORMER BALUN, having a filing date of Jan. 23, 2002, and a Ser. No. of 10/055,425. If, however, the parasitic capacitance of the on-chip balun102is a significant factor at the operating frequencies, the line impedance matching circuit100would need to account for the impedance contributions of the parasitic capacitance.

The ground circuit122, which includes capacitor C5, has a capacitance value such that, when coupled in series with the equivalent circuit120of the package and bond wire (which includes an inductor and resistor), the impedance at the operating frequencies is minimized. In particular, the capacitance value in combination with the inductance value of the bond wire and package provides a bandpass filter at the operating frequencies. As one of average skill in the art will appreciate, the ground circuit122may be implemented in a variety of ways to provide a low impedance path for the primary of the on-chip balun to ground.

FIG. 5illustrates an alternate schematic block diagram of an integrated circuit low noise amplifier72. In this embodiment, the integrated circuit low noise amplifier72includes an on-chip balun102and the differential amplifier104. The on-chip balun102may be modified to include a ground circuit such that inductance and resistance of packaging and bond wires are compensated for such that a low impedance ground path is obtained. In addition, the on-chip balun102may be modified to include a line impedance matching circuit that includes a pair of capacitors, one coupled in series with the single ended signal102and another in parallel with the primary winding of the on-chip balun to provide impedance matching.

The preceding discussion has presented an integrated circuit low noise amplifier and applications within a radio receiver. By incorporating an on-chip balun with a differential amplifier, an integrated circuit low noise amplifier that provides a low impedance ground path, symmetrical differential signaling, a low noise figure, substantial gain, and impedance matching is obtained. As one of average skill in the art will appreciate, other embodiments may be derived from the teaching of the present invention, without deviating from the scope of the claims.