Display apparatus including clock wiring overlapping shielding pattern and gate pattern for reducing bezel area

A display apparatus includes: a display panel; a driving circuit which provides a driving signal to the display panel and includes at least one driving transistor; and a clock signal wiring for providing a clock signal to the driving circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern, the gate pattern overlaps the active pattern in a plan view, a major surface plane of the source pattern is disposed in a layer different from a layer the active pattern is disposed in, the source pattern is electrically connected to the active pattern, the shielding pattern is disposed between the gate pattern and the clock signal wiring and applied with a constant voltage, and the clock signal wiring overlaps the gate pattern in the plan view and is disposed on the source pattern.

This application claims priority to and benefits of Korean Patent Application No. 10-2020-0030753, filed on Mar. 12, 2020 and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND

1. Technical Field

Embodiments are directed to a display apparatus. More particularly, embodiments are directed to a display apparatus including shielding pattern.

2. Description of the Related Art

Until now, conventional cathode ray tube (“CRT”) have been widely used in display apparatus with many advantages in terms of performance and price. However, a display apparatus having advantages such as miniaturization or portability overcoming the shortcomings of CRT and having advantages such as miniaturization, weight reduction, and low power consumption has attracted attention. For example, plasma display, liquid crystal display, organic light emitting display, and the like are attracting attention.

Attempts have been made to reduce the bezel area of the display apparatus. For example, a bezel-less display apparatus, a display apparatus including a notch, and the like have been developed. Wirings existing in the bezel area may be rearranged to reduce the bezel area.

SUMMARY

Embodiments provide a display apparatus including a shielding pattern.

According to example embodiment, a display apparatus includes: a display panel; a driving circuit which provides a driving signal to the display panel and includes at least one driving transistor; and a clock signal wiring which provides a clock signal to the driving circuit. The driving circuit includes an active pattern, a gate pattern, a source pattern, and a shielding pattern, the gate pattern overlaps the active pattern in a plan view, a major surface plane of the source pattern is disposed in a layer different from a layer the active pattern is disposed in, the source pattern is electrically connected to the active pattern, the shielding pattern is disposed between the gate pattern and the clock signal wiring and applied with a constant voltage, and the clock signal wiring overlaps the gate pattern in the plan view and is disposed on the source pattern.

In an embodiment, the shielding pattern may be disposed under the major surface plane of the source pattern.

In an embodiment, the shielding pattern may entirely overlap an entire region in which the gate pattern overlaps the clock signal wiring in the plan view.

In an embodiment, the display apparatus may further include a connection wiring disposed in the same layer as the clock signal wiring and which transmits the constant voltage to the shielding pattern.

In an embodiment, the display apparatus may further include a connection wiring disposed between the shielding pattern and the clock signal wiring, and which transmits the constant voltage to the shielding pattern.

In an embodiment, the connection wiring may not overlap each of the clock signal wiring and the gate pattern in the plan view.

In an embodiment, the gate pattern may include a first sub gate pattern and a second sub gate pattern.

In an embodiment, the first sub gate pattern and the second sub gate pattern may be disposed under the major surface plane of the source pattern.

In an embodiment, the first sub gate pattern and the second sub gate pattern may overlap the shielding pattern in the plan view.

In an embodiment, only one of the first sub gate pattern and the second sub gate pattern may overlap the shielding pattern in the plan view.

In an embodiment, the first sub gate pattern and the second sub gate pattern may be disposed in the same layer.

In an embodiment, the driving circuit may further include a drain pattern disposed between the first sub gate pattern and the second sub gate pattern and electrically connected to the active pattern.

In an embodiment, only one of the first sub gate pattern and the second sub gate pattern may overlap the shielding pattern in the plan view.

In an embodiment, the shielding pattern may include a first sub shielding pattern and a second sub shielding pattern.

In an embodiment, the first sub gate pattern and the second sub gate pattern may overlap the first sub shielding pattern and the second sub shielding pattern, respectively, in the plan view.

In an embodiment, the shielding pattern may be disposed on the source pattern.

In an embodiment, the driving circuit may include a p-type transistor.

In an embodiment, the driving circuit may include an n-type transistor.

In an embodiment, the driving circuit includes a dual-gate transistor.

The display apparatus according to an embodiment may include a display panel, a driving circuit providing a driving signal to the display panel and including at least one driving transistor and a clock signal wiring for providing a clock signal to the driving circuit, the driving circuit includes an active pattern, a gate pattern overlapping the active pattern, a source pattern disposed on a layer different from the active pattern and electrically connected to the active pattern, and a shielding pattern disposed between the gate pattern and the clock signal wiring applied with a constant voltage, and the clock signal wiring overlaps the gate pattern and is disposed on the source pattern. Accordingly, a bezel area of the display apparatus may be reduced. In addition, a coupling phenomenon that may occur between the gate pattern and the clock signal wiring can be effectively prevented.

DETAILED DESCRIPTION

A display apparatus according to embodiments of the invention will be described hereinafter with reference to the accompanying drawings, in which embodiments are shown. Same or similar reference numerals may be used for same or similar elements in the drawings.

The invention may have various modifications and may be embodied in different forms, and embodiments will be explained in detail with reference to the accompany drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, all modifications, equivalents, and substituents which are included in the spirit and technical scope of the invention should be included.

In the drawings, the dimensions of structures are exaggerated for clarity of illustration. It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element without departing from the teachings of the invention. Similarly, a second element could be termed a first element. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. In the specification and the claims, the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or”.

The phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” When preceding a list of elements, the term, “at least one of,” modifies the entire list of elements and does not modify the individual elements of the list.

It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, numerals, steps, operations, elements, parts, or the combination thereof, but do not preclude the presence or addition of one or more other features, numerals, steps, operations, elements, parts, or the combination thereof.

It will also be understood that when a layer, a film, a region, a plate, etc. is referred to as being “on” or “above” another part, it can be “directly on” the other part, or intervening layers may also be present. It will also be understood that when a layer, a film, a region, a plate, etc. is referred to as being “under” or “below” another part, it can be “directly under” the other part, or intervening layers may also be present. When an element is referred to as being disposed “on” another element, it can be disposed under the other element.

FIG.1is a plan view illustrating a display apparatus according to an embodiment of the present invention,FIG.2is a diagram illustrating an embodiment of the structure of a scan driver (FIG.2is a plan view),FIG.3is a diagram illustrating an embodiment of a scan driving circuit built into a scan shift register,FIG.4is a diagram illustrating an embodiment of the structure of an emission driver (FIG.4is a plan view),FIG.5is a diagram illustrating an embodiment of an emission driving circuit built into an emission shift register, andFIG.6is a cross-sectional view taken along line I-I′ ofFIG.1.

Referring toFIGS.1to6, A display apparatus1000may include a display panel120including a plurality of pixels400and a driving circuit130for driving the display panel120. The driving circuit130may include a data driver100providing data signals110to the plurality of pixels400, a scan driver200providing scan signals210to the plurality of pixels400, and an emission driver300providing emission signals310to the plurality of pixels400.

The display panel120may include the plurality of pixels400connected to a plurality of data wirings and a plurality of scan wirings. The pixels400may be arranged in a matrix form over the entire area of the display panel120. However, this is exemplary, and the arrangement in which the pixels400are arranged according to the invention is not limited thereto. Each pixel400may include at least two transistors, at least one capacitor, and an organic light emitting diode580. The display panel120may be an organic light emitting display panel. The pixel400may be a Hybrid Oxide Polycrystalline (“HOP”) pixel suitable for low-frequency driving to reduce power consumption. The HOP pixel may include at least one Low-temperature polycrystalline silicon (“LTPS”) PMOS transistor and at least one oxide NMOS transistor. However, this is exemplary and the invention is not limited thereto.

InFIG.1, the scan driver200and the emission driver300are illustrated to be positioned on both sides of the display panel120, respectively, but this is exemplary and the invention is not limited thereto. In another embodiment, for example, the positions of the scan driver200and the emission driver300may be changed. Also, both the scan driver200and the emission driver300may be located on the same side of the display panel120.

As illustrated inFIG.2, the scan driver200may include a plurality of scan shift registers220and a plurality of clock signal wirings CLK connected to the plurality of scan shift registers220. In an embodiment, the plurality of clock signal wirings CLK may be disposed to overlap the scan shift registers220in a plan view. When the plurality of clock signal wirings CLK are disposed to overlap the plurality of scan shift registers220in a plan view, a bezel area of the display apparatus1000may decrease.

The scan shift register220may include a scan driving circuit10. In an embodiment, the scan driving circuit10may include first to eighth scan driving transistors T1to T8, and first and second capacitors C1and C2. A coupling phenomenon may occur in some transistors T2, T4, T6, and T7to which a plurality of clock signals CLK1and CLK2is not directly applied as a turned-on signal and a constant voltage (i.e., a first constant voltage VGH, a second constant voltage VGL) is not directly applied as a turned-on signal. When a coupling phenomenon occurs, a glitch may occur in a scan output. As a result, performance of the display apparatus1000may deteriorate. In the scan driving circuit10inFIG.3, the clock signal CLK1is applied to the transistor T3as a gate-on signal, the clock signal CLK2is applied to the transistors T1and T5as a gate-on signal, the second constant voltage VGL may be applied to the transistors T8as a gate-on signal, and an output signal Scan corresponds to an output signal OUT<n> of n-th scan shift register220. Here, n is a natural number. Output signals OUT<n−1> to OUT<n+2> correspond to output signals of n−1-th to n+2-th scan shift registers220, respectively.

The scan driving circuit10ofFIG.3is illustrated as including a p-type transistor, but the invention is not limited thereto. In another embodiment, the scan driving circuit10may include an n-type transistor.

As illustrated inFIG.4, the emission driver300may include a plurality of emission shift registers320and a plurality of clock signal wirings CLK connected to the plurality of emission shift registers320. In an embodiment, the plurality of clock signal wirings CLK may be disposed to overlap the plurality of emission shift registers320in a plan view. When the plurality of clock signal wirings CLK are disposed to overlap the plurality of emission shift registers320in a plan view, the bezel area of the display apparatus1000may be reduced.

The emission shift register320may include an emission driving circuit20. In an embodiment, the emission driving circuit20may include ninth to twentieth emission driving transistors T9to T20, and third to fifth capacitors C3, C4, C5. A coupling phenomenon may occur in some transistors T9, T10, T13, T14, T17, T18, T20to which a plurality of clock signals CLK1and CLK3is not directly applied as a gate-on signal and a constant voltage (i.e., a first constant voltage VGH, a second constant voltage VGL) is not directly applied as a gate-on signal. In the emission driving circuit20inFIG.5, the clock signal CLK1may be applied to the transistors T15and T19as a gate-on signal, the clock signal CLK3may be applied to the transistor T16as a gate-on signal, the second constant voltage VGL may be applied to the transistors T11and T12as a gate-on signal and an output signal EM corresponds to an output signal OUT1<n> of n-th emission shift register320. Output signals OUT1<n−1> to OUT1<n+2> correspond to output signals of n−1-th to n+2-th emission shift registers320, respectively.

The emission driving circuit20ofFIG.5is illustrated to include a p-type transistor, but is the invention not limited thereto. In another embodiment, the emission driving circuit20may include an n-type transistor.

As illustrated inFIG.6, the display panel120may include a substrate510, a buffer layer515, a gate insulating layer520, a display panel transistor598, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a capacitance electrode536, a first via-insulating layer540, a connection electrode556, a second via-insulating layer550, a pixel defining layer560, and an organic light emitting diode580. The display panel transistor598may include an active pattern591, a source pattern594, a drain pattern595, and a gate pattern596. The organic light emitting diode580may include a lower electrode555, an intermediate layer565, and an upper electrode570.

The substrate510may include or be formed of various materials such as quartz, synthetic quartz, calcium fluoride, fluorine-doped quartz, soda lime glass, non-alkali glass, polyethylene terephthalate (“PET”), polyethylen naphthalate (“PEN”), polyimide and the like.

The buffer layer515may be disposed on the substrate510. The buffer layer515may prevent diffusion of metal atoms or impurities from the substrate510to the pixel400. The buffer layer515may obtain a substantially uniform active pattern591by controlling a heat transfer rate during the crystallization process for forming the active pattern591. Also, when a top surface of the substrate510is not uniform, the buffer layer515may serve to improve the flatness of the top surface of the substrate510. Two or more buffer layers515may be provided on the substrate510according to the type of the substrate510. Alternatively, the buffer layer515may not be disposed on the substrate510That is, buffer layer515may be omitted. In an embodiment, the buffer layer515may include an organic material or an inorganic material. For example, the buffer layer515may have a single layer or multilayer structure including or formed of an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride.

The active pattern591may be disposed on the buffer layer515. The active pattern591may include a metal oxide semiconductor, an inorganic semiconductor, or an organic semiconductor and the like. The active pattern591may include a channel region, a source region, and a drain region.

The gate insulating layer520may be disposed on the buffer layer515. The gate insulating layer520may cover the active pattern591on the buffer layer515and have a flat top surface without forming a level difference around the active pattern591. Optionally, the gate insulating layer520may be disposed on the buffer layer515to have substantially the same thickness along the profile of the active pattern591. The gate insulating layer520may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer520may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), Aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), or the like. In an embodiment, the gate insulating layer520may have a multilayer structure including a plurality of insulating layers. The insulating layers may have different materials and different thicknesses. These may be used alone or in combination with each other.

The gate pattern596may be disposed on the gate insulating layer520. The gate pattern596may be disposed on a portion of the gate insulating layer520where the active pattern591is positioned below. The gate pattern596may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the gate pattern596may be formed of one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), Nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multi-layer.

The first interlayer-insulating layer530may be disposed on the gate insulating layer520. The first interlayer-insulating layer530may cover the gate pattern596on the gate insulating layer520and may have a flat top surface without forming a level difference around the gate insulating layer520. Optionally, the first interlayer-insulating layer530may be disposed on the gate insulating layer520to have substantially the same thickness along the profile of the gate pattern596. The first interlayer-insulating layer530may include a silicon compound, a metal oxide, or the like. For example, the first interlayer-insulating layer530may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), Aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), or the like. In an embodiment, the first interlayer-insulating layer530may have a multilayer structure including a plurality of insulating layers. The insulating layers may have different materials and different thicknesses. These may be used alone or in combination with each other.

The capacitance electrode536may be disposed on the first interlayer-insulating layer530. The capacitance electrode536may be disposed on a portion of the first interlayer-insulating layer530where the gate pattern596is positioned below. The capacitance electrode536may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the capacitance electrode536may include or be formed of one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), Nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multi-layer.

The second interlayer-insulating layer535may cover the capacitance electrode536on the first interlayer-insulating layer530and may have a flat top surface without forming a level difference around the capacitance electrode536. Optionally, the second interlayer-insulating layer535may be disposed on the first interlayer-insulating layer530to have substantially the same thickness along the profile of the capacitance electrode536. The second interlayer-insulating layer535may include a silicon compound, a metal oxide, or the like. For example, the second interlayer-insulating layer535may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC) silicon carbonitride (SiCN), aluminum oxide (AlO), Aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), and the like. In an embodiment, the second interlayer-insulating layer535may have a multilayer structure including a plurality of insulating layers. The insulating layers may have different materials and different thicknesses. These may be used alone or in combination with each other.

The source pattern594and the drain pattern595may be disposed on the second interlayer-insulating layer535. The source pattern594may be connected to the source region of the active pattern591through a contact hole penetrating the first interlayer-insulating layer530, the second interlayer-insulating layer535, and the gate insulating layer520. In an embodiment, the source pattern594and the source regions of the active pattern591may constitute a source electrode. The drain pattern595may be connected to the drain region of the active pattern591through a contact hole penetrating the first interlayer-insulating layer530, the second interlayer-insulating layer535, and the gate insulating layer520. In an embodiment, the drain pattern595and the drain region of the active pattern591may constitute a drain electrode. The source pattern594and the drain pattern595may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the source pattern594and the drain pattern595may include or be formed of one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), Nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multi-layer.

The first via-insulating layer540may be disposed on the second interlayer-insulating layer535and may cover the source pattern594and the drain pattern595. The first via-insulating layer540may be disposed to have a relatively thick thickness to sufficiently cover the source pattern594and the drain pattern595, and in this case, the first via-insulating layer540may have a substantially flat top surface. In order to implement such the flat top surface of the first via-insulating layer540, a planarization process may be added to the first via-insulating layer540. Optionally, the first via-insulating layer540may cover the source pattern594and the drain pattern595and may be disposed along the profiles of the source pattern594and the drain pattern595with a uniform thickness. The first via-insulating layer540may be made of an organic material or an inorganic material. In an embodiment, the first via-insulating layer540may be formed of an organic material such as acrylic, benzocyclobutene (“BCB”), polyimide, or hexamethyldisiloxane (“HMDSO”).

The connection electrode556may be disposed on the first via-insulating layer540. The connection electrode556may be connected to the source pattern594or the drain pattern595through a contact hole penetrating the first via-insulating layer540. The connection electrode556may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the connection electrode556may be formed of one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), Nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed as a single layer or a multi-layer.

The second via-insulating layer550may be disposed on the first via-insulating layer540and may cover the connection electrode556. The second via-insulating layer550may be disposed to have a relatively thick thickness to sufficiently cover the connection electrode556, and in this case, the second via-insulating layer550may have a substantially flat top surface. In order to implement such the flat top surface of the second via-insulating layer550, a planarization process may be added to the second via-insulating layer550. Optionally, the second via-insulating layer550may cover the connection electrode556and may be disposed along the profiles of the connection electrode556with a uniform thickness. The second via-insulating layer550may be made of an organic material or an inorganic material. In an embodiment, the second via-insulating layer550may include a material that is substantially the same as or similar to the first via-insulating layer540.

The lower electrode555may be disposed on the second via-insulating layer550. The lower electrode555may include a transparent electrode, a reflective electrode, or a transflective electrode. The lower electrode555may be connected to the connection electrode556through a contact hole penetrating the second via-insulating layer550. In an embodiment, the lower electrode555may be one of an anode electrode or a cathode electrode.

A pixel defining layer560exposing a portion of the upper surface of the lower electrode555may be disposed on the second via-insulating layer550. The pixel defining layer560may include an organic material.

The intermediate layer565may be disposed on the lower electrode555in which a portion of the upper surface is exposed by the pixel defining layer560. The intermediate layer565may have a structure in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, or the like are stacked in a single or complex structure.

The upper electrode570may be disposed on the intermediate layer565. The upper electrode570may include a translucent electrode or a reflective electrode. In one embodiment, the upper electrode570may be one of the cathode electrode or the anode electrode.

FIG.7is a plan view illustrating an embodiment of a driving transistor, andFIG.8is a cross-sectional view taken along line II-II′ ofFIG.7.

Referring toFIGS.7and8, the transistor ofFIG.7may be a transistor disposed in the scan driver200or the emission driver300ofFIG.1. The transistor ofFIG.7may correspond to a transistor to which a clock signal is not directly applied as a turned-on signal and a constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) is not directly applied as a turned-on signal among the transistors in the scan driving circuit10ofFIG.3and the emission driving circuit20ofFIG.5. In an embodiment, the transistor ofFIG.7may correspond to one of the second, fourth, sixth, and seventh transistors T2, T4, T6, and T7ofFIG.3. In an embodiment, the transistor ofFIG.7may correspond to one of the ninth, tenth, thirteenth, fourteenth, seventeenth, eighteenth, and twentieth transistors T9, T10, T13, T14, T17, T18, and T20ofFIG.5. This may be the same for the transistors ofFIGS.9,11,13,15,17,19, and21.

The driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, a driving transistor528a, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating A layer540, a second via-insulating layer550, a shielding pattern527, and a clock signal wiring545. The driving transistor528amay include an active pattern521, a source pattern524, a drain pattern525, and a gate pattern526. In an embodiment, the source pattern524and a source region of the active pattern521may constitute a source electrode, and the drain pattern525and a drain region of the active pattern521may constitute a drain electrode.

The second interlayer-insulating layer535may cover the shielding pattern527which is disposed on the first interlayer-insulating layer530and may have a flat top surface without forming a level difference around it. Optionally, the second interlayer-insulating layer535may be disposed on the first interlayer-insulating layer530to have substantially the same thickness along the profile of the shielding pattern527.

The clock signal wiring545may be disposed on the first via-insulating layer540. The clock signal may be supplied to the scan shift register220ofFIG.2and the emission shift register320ofFIG.4through the clock signal wiring545. In an embodiment, the clock signal wiring545may be disposed in the same layer as the connection electrode556ofFIG.6. The clock signal wiring545may be simultaneously formed of the same material as the connection electrode556ofFIG.6. In an embodiment, the clock signal wiring545may be disposed on the source pattern524and the drain pattern525. The clock signal wiring545may be disposed to overlap the gate pattern526in a plan view. As the clock signal wiring545and the gate pattern526are disposed to overlap each other in a plan view, parasitic capacitance may occur between the clock signal wiring545and the gate pattern526. A coupling phenomenon may occur between the clock signal wiring545and the gate pattern526due to the parasitic capacitance. When the coupling phenomenon occurs, malfunction of the scan driver200and the emission driver300may be caused. The coupling phenomenon may cause a glitch phenomenon in the scan signal and the emission signal. Due to the occurrence of a glitch phenomenon, a short circuit may occur, which may increase power consumption. According to the invention, the shielding pattern527may be disposed to prevent such a coupling phenomenon.

The shielding pattern527may be disposed on the first interlayer-insulating layer530. In an embodiment, the shielding pattern527may be disposed in the same layer as the capacitance electrode536ofFIG.6. The shielding pattern527may be simultaneously formed of the same material as the capacitance electrode536ofFIG.6.

The shielding pattern527may be disposed between the source pattern524and the drain pattern525so as not to overlap with any of the source pattern524and the drain pattern525in a plan view. The shielding pattern527may be disposed between the gate pattern526and the clock signal wiring545. The shielding pattern527may be disposed to overlap the gate pattern526and the clock signal wiring545in a plan view. The constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the shielding pattern527. Since the constant voltage has a constant polarity and magnitude, the shielding pattern527to which the constant voltage is applied may shield the gate pattern526and the clock signal wiring545by located between the gate pattern526and the clock signal wiring545. Since the shielding pattern527shields the gate pattern526and the clock signal wiring545, a coupling phenomenon that may occur between the gate pattern526and the clock signal wiring545can be effectively prevented.

The second via-insulating layer550may be disposed on the clock signal wiring545. The second via-insulating layer550may include or be made of an organic material or an inorganic material. In an embodiment, the first via-insulating layer540may be formed of an organic material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

FIG.9is a plan view illustrating an embodiment of a driving transistor, andFIG.10is a cross-sectional view taken along line III-III′ ofFIG.9.

Referring toFIGS.9and10, the driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, an active pattern521and a gate pattern526of a driving transistor, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating layer540, a second via-insulating layer550, a shielding pattern527, a clock signal wiring545, and a connection wiring546. The active pattern521may electrically contact the source pattern524and the drain pattern525when turned on.

In an embodiment, the connection wiring546may be disposed in the same layer as the clock signal wiring545. The connection wiring546may be disposed to be spaced apart from the clock signal wiring545. The connection wiring546may be connected to the shielding pattern527through a contact hole penetrating the first-via-insulating layer540and the second interlayer-insulating layer535. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the connection wiring546. The constant voltage applied to the connection wiring546may be transmitted to the shielding pattern527through the contact hole. The shielding pattern527may effectively prevent a coupling phenomenon between the clock signal wiring545and the gate pattern526by using the constant voltage. The connection wiring546may be disposed in the same layer as the clock signal wiring545. The connection wiring546may be simultaneously formed of the same material as the clock signal wiring545. In an embodiment, the connection wiring546and the clock signal wiring545may be disposed on the source pattern524.

FIG.11is a plan view illustrating an embodiment of a driving transistor, andFIG.12is a cross-sectional view taken along line IV-IV′ ofFIG.11.

Referring toFIGS.10and11, the driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, an active pattern521and a gate pattern526of a driver transistor, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating layer540, a second via-insulating layer550, a shielding pattern527, a clock signal wiring545, and a connection wiring547. The active pattern521may electrically contact the source pattern524and the drain pattern525when turned on.

The gate pattern526may partially overlap the active pattern521in a plan view, and be disposed on the gate insulating layer520. The shielding pattern527may partially overlap the gate pattern526in a plan view and be disposed on the first interlayer-insulating layer530. The shielding pattern527may be disposed between the clock signal wiring545and the gate pattern526to prevent a coupling phenomenon between the clock signal wiring545and the gate pattern526. The clock signal wiring545may be disposed to overlap the shielding pattern527within a range where the gate pattern526and the shielding pattern527overlap in a plan view.

The connection wiring547may be disposed on the second interlayer-insulating layer535. The connection wiring547may be connected to the shielding pattern527through a contact hole penetrating the second interlayer-insulating layer535. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the connection wiring547. The constant voltage applied to the connection wiring547may be transmitted to the shielding pattern527through the contact hole. The shielding pattern527may effectively prevent a coupling phenomenon between the clock signal wiring545and the gate pattern526by using the constant voltage.

In an embodiment, the connection wiring547may be disposed in the same layer as the source and drain patterns524and525. The connection wiring547may include or be formed of the same material as the source and drain patterns524and525. In an embodiment, the clock signal wiring545may be disposed on the source pattern524, the drain pattern525, and the connection wiring547.

FIG.13is a plan view illustrating an embodiment of a driving circuit dual gate transistor, andFIG.14is a cross-sectional view taken along line V-V′ ofFIG.13.

Referring toFIGS.13and14, the driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, a driving transistor528b, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating layer540, a second via-insulating layer550, a shielding pattern527, and a clock signal wiring545. The driving transistor528bmay include an active pattern521, a source pattern524, a drain pattern525, and a gate pattern526.

The gate pattern526may be disposed on the gate insulating layer520. The gate pattern526may be a dual-gate including a first sub-gate pattern526aand a second sub-gate pattern526b. In a plan view, the first sub-gate pattern526aand the second sub-gate pattern526bmay be disposed between the source pattern524and the drain pattern525. In an embodiment, the shielding pattern527may shield both the first sub-gate pattern526aand the second sub-gate pattern526bto prevent a coupling phenomenon. Further, the shielding pattern527may be disposed under the major surface plane (which is disposed on the second interlayer-insulating layer535) of the source pattern524and the drain pattern525. The clock signal wiring545may be disposed on the source pattern524and the drain pattern525.

The shielding pattern527may be disposed to overlap the first sub-gate pattern526aand the second sub-gate pattern526bin a plan view. The shielding pattern527may prevent a coupling phenomenon between the first and second sub-gate patterns526aand526b, and the clock signal wiring545.

FIG.15is a plan view illustrating an embodiment of a driving circuit dual gate transistor, andFIG.16is a cross-sectional view taken along line VI-VI′ ofFIG.15.

As illustrated inFIGS.15and16, the shielding pattern527may overlap one of the first sub-gate pattern526aand the second sub-gate pattern526bin a plan view.

FIG.17is a plan view illustrating an embodiment of a driving circuit dual gate transistor,FIG.18is a cross-sectional view taken along line VII-VII′ ofFIG.17.

Referring toFIGS.17and18, the driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, a driving transistor528c, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating layer540, a second via-insulating layer550, a shielding pattern527, and a clock signal wiring545. The driving transistor528cmay include an active pattern521, a source pattern524, a drain pattern525, and a gate pattern526. The source pattern524may include a first sub-source pattern524aand a second sub-source pattern524b.

The gate pattern526may be disposed on the gate insulating layer520. The gate pattern526may be a dual-gate including a first sub-gate pattern526aand a second sub-gate pattern526b. The first sub-gate pattern526aand the second sub-gate pattern526bmay be disposed between the first sub-source pattern524aand the second sub-source pattern524b.

The shielding pattern527may be disposed on the first interlayer-insulating layer530. The shielding pattern527may include a first sub shielding pattern527aand a second sub shielding pattern527b. The shielding pattern527may be disposed to overlap the gate pattern526in a plan view. In an embodiment, the first sub-shielding pattern527amay be disposed to overlap the first sub-gate pattern526ain a plan view, and the second sub-shielding pattern527bmay be disposed to overlap the second sub-gate pattern526bin a plan view. Through this, a coupling phenomenon between the clock signal wiring545and each of the first sub-gate pattern526aand the second sub-gate pattern526bmay be effectively prevented.

The first sub-source pattern524a, the second sub-source pattern524b, and the drain pattern525may be disposed on the second interlayer-insulating layer535. The first and second sub-source patterns524aand524bmay be connected to first and second source regions of521of the active pattern521through contact holes penetrating the gate insulating layer520, the first interlayer-insulating layer530, and the second interlayer-insulating layer535. The drain pattern525may be connected to a drain region of the active pattern521through a contact hole penetrating the gate insulating layer520, the first interlayer-insulating layer530, and the second interlayer-insulating layer535. In an embodiment, a clock signal wiring545may be disposed on the first and second sub-source patterns524aand524b, and the drain pattern525.

FIG.19is a plan view illustrating an embodiment of a driving circuit dual gate transistor,FIG.20is a cross-sectional view taken along line VIII-VIII′ ofFIG.19.

As illustrated inFIGS.19and20, the shielding pattern527may overlap one of the first sub-gate pattern526aand the second sub-gate pattern526bin a plan view.

FIG.21is a plan view illustrating an embodiment of a driving transistor, andFIG.22is a cross-sectional view taken along line IX-IX′ ofFIG.21.

Referring toFIGS.21and22, the driving circuit130may include a substrate510, a buffer layer515, a gate insulating layer520, a driving transistor528a, a first interlayer-insulating layer530, a second interlayer-insulating layer535, a first via-insulating layer540, a second via-insulating layer550, a clock signal wiring548, and a shielding pattern549. The driving transistor528amay include an active pattern521, a source pattern524, a drain pattern525, and a gate pattern526.

The shielding pattern549may be disposed on the first via-insulating layer540. The shielding pattern549may be disposed to overlap the gate pattern526in a plan view. The shielding pattern549may not overlap the source pattern524and the drain pattern525in a plan view. A constant voltage (e.g., a first constant voltage VGH, a second constant voltage VGL) may be applied to the shielding pattern549. As the constant voltage is applied to the shielding pattern549, the shielding pattern549may shield the gate pattern526. In an embodiment, the shielding pattern549may be disposed in the same layer as the connection wiring546ofFIG.10. That is, the shielding pattern549may be disposed on the source pattern524and the drain pattern525.

The clock signal wiring548may be disposed on the second via-insulating layer550. The clock signal wiring548may be disposed on the shielding pattern549. Clock signals may flow through the clock signal wiring548. As the shielding pattern549is disposed to overlap the gate pattern526in a plan view, a coupling phenomenon between the gate pattern526and the clock signal wiring548can be effectively prevented. The shielding pattern549may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other.

The present inventive concept may be applied to a display apparatus and an electronic apparatus including the display apparatus. For example, the present inventive concept may be applied to a smart phone, a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a television, a computer monitor, a laptop, a head mounted display apparatus, MP3 player, etc.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of embodiments and is not to be construed as limited to the example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.