Method of manufacturing silicide contacts for CMOS devices

In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

BACKGROUND OF THE INVENTION 
The present invention is directed to providing connections between 
polysilicon wiring and source and drain diffusions in CMOS technology. 
In conventional NMOS technology, a buried contact is frequently used to 
provide a contact from polysilicon wiring to the source and drain 
diffusions. After the gate oxide has been formed, but before the 
polysilicon wiring is deposited, contact holes are etched in the gate 
oxide to selectively allow the polysilicon to be deposited directly on the 
silicon substrate. During the drive-in of the dopant into the polysilicon, 
the doping impurities in the polysilicon diffuse through the contact hole 
into the silicon substrate. Thus, when the conductivity type of the 
polysilicon wiring is the same as that of the source and drain diffusions, 
a self-aligned interconnect may easily be formed. 
However, in a CMOS device which uses n-type polysilicon to form the gate of 
both p channel and n channel devices, this technique would not permit 
formation of a buried contact to a p+ source or drain diffusion. The n+ 
dopant diffusing out of the polysilicon would not form a connection to the 
p-type source or drain diffusion, but would form a short circuit to the 
n-type substrate or n-type well. This inability to form a buried contact 
to a p-type source or drain diffusion places a serious constraint on CMOS 
design, since the possibility of making direct contacts to both p-type and 
n-type source or drain areas would permit greatly increased efficiency of 
utilization of silicon real estate in CMOS design. 
It is of course known, from Schottky TTL technology, to provide silicide 
strap connectors across p and n regions. However, in this technology 
Schottky barrier contacts, and not ohmic contacts, are formed to the n 
regions. It is also known to use platinum silicide to form ohmic source 
contacts, but it is believed to be novel to use silicides for ohmic 
contacts from poly to both p and n regions, according to the present 
invention. 
Thus, it is an object of the present invention to provide a technology 
which permits direct formation of first contacts between a polysilicon 
gate-level interconnect and a source or drain region of either 
conductivity type. 
It is a further object of the present invention to provide a technology 
which permits easy formation of ohmic contacts between polysilicon 
gate-level interconnects and source or drain regions of either 
conductivity type. 
It is a further object of the present invention to provide a technology, 
for forming ohmic contacts to source or drain regions of either 
conductivity type, which is a self-aligned process. 
It is a further object of the present invention to provide a technology, 
for forming connections between gate-level interconnects and source or 
drain regions of either conductivity type, which provides contacts which 
are as compact as those produced by a buried contact connection between an 
n+ doped polysilicon interconnect and an n-type source or drain region. 
SUMMARY OF THE INVENTION 
According to the present invention, there is provided a process for forming 
contacts between gate-level interconnects, comprising doped polysilicon, 
and either n- or p-type source or drain regions formed in a silicon 
substrate which is covered by a gate insulator layer, comprising the steps 
of: etching regions of the gate insulator layer where the contacts are to 
be formed, the etching step also partially undercutting the gate-level 
interconnects by eroding the gate insulator beneath the gate-level 
interconnects at the edges thereof where the contacts are to be formed; 
conformally depositing undoped polysilicon on the resulting composite 
surface; etching the undoped polysilicon, so as to remove the undoped 
polysilicon from all areas where the gate-level interconnects are undercut 
by the first-mentioned etching step; and siliciding exposed areas of the 
silicon substrate, the gate-level interconnects, and the conformally 
deposited undoped polysilicon layer, whereby silicide contacts are formed 
between the gate-level interconnects and the respective exposed regions of 
the substrate. 
Thus, according to the present invention, first contacts are easily formed 
to connect source or drain regions to polysilicon gate-level 
interconnects, regardless of the conductivity type of the source or drain 
regions involved. Moreover, since the silicide first contacts are formed 
directly from the exposed regions of silicon, the contacts thus provided 
are self-aligned. Thus, compact connections between gate-level 
interconnects and CMOS circuit elements are easily formed, so that very 
compact circuit design can be easily attained in CMOS technology. In 
addition, the contacts thus formed are ohmic, so that unwanted junction or 
Schottky barrier effects are easily avoided. 
In addition, by undercutting the gate-level polysilicon interconnect, and 
conformally depositing a small amount of polysilicon to fill the undercut 
region, continuity of the silicide connection grown between the gate-level 
interconnect and the exposed silicon of the source or drain region is 
assured. 
Moreover, since the siliciding step according to the present invention may 
be performed at a very late stage of IC fabrication, temperature 
constraints required by silicide processes and materials may be easily 
satisfied, by performing the siliciding step after earlier high 
temperature steps.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows a portion of a partially formed CMOS device to which the 
process of the present invention is to be applied. For compact 
presentation, the horizontal dimensions are not drawn to scale. A p-type 
region 10 is separated from an n-type region 12 by a thick field region 
14. The n-type region 12 may, for example, be an n well. Alternatively, 
interconnects according to the present invention could be formed where the 
p-type region 10 is a p well, since the present invention is equally 
applicable to n well or p well CMOS technology. One n channel transistor 
16 is shown within the p region 10, and one p channel transistor 18 is 
shown within the n region 12. The n channel transistor 16 includes a 
source 20, a gate 22, and a drain 24. The p channel transistor 18 includes 
a drain 26, a gate 28, and a source 30. The gates 22 and 28 are formed of 
polysilicon, and a gate-level interconnect 32 is also formed of 
polysilicon at the same time as the gates. An oxide layer 34 is provided 
to insulate the gates 22 and 28, and the gate-level interconnect 32. 
Thus, at the stage shown in FIG. 1, the gates and gate-level interconnects 
(such as 22, 28 and 32) have been patterned, the sidewall oxide 34 has 
been grown, and the source and drain regions (such as 20, 24, 26, and 30) 
have been implanted and annealed, before the next step of the process of 
the present invention is to be applied. 
FIG. 2 shows the next step in preparation of first contacts according to 
the present invention. As an example, assume that the particular CMOS 
circuit which is to be manufactured by the process of the present 
invention requires connection of the gate-level interconnect 32 to the 
n-type drain region 24 and the p-type drain region 26. A photoresist layer 
36 is applied selectively, providing exposed regions 38 where first 
contacts are to be formed between the gate-level interconnect 32 and the 
drain 24 and drain 26 respectively. 
A wet etch is now used to etch away the oxide 34 in the regions 38 
uncovered by photoresist 36, i.e. from the sidewalls of the gate level 
interconnect 32 and from above portions of the regions 24 and 26. This wet 
etch also undercuts the gate level interconnect 32, so that the resulting 
pattern, after the etch and after the photoresist is removed, is as shown 
in FIG. 3. In applying the wet etch, care must be taken that the depth of 
the undercut region 40 does not exceed the distance of sideways diffusion 
of the p+ doped region 26 beneath the gate level interconnect 32. In the 
present embodiment, where it is assumed that the polysilicon of the gate 
level interconnect 32 is n type doped, this restriction does not apply to 
the undercut region 40 above the n-type drain diffusion 24, since the 
doping type of region 24 is the same as that of the gate. 
If the undercut regions 40 formed by the wet etch, as described above, 
extend beyond the lateral diffusion of the p-type region 26 beneath the 
gate-level interconnect 32, a second implant of p-type impurities is 
applied. The hazard to be avoided here is that, where it is desired to 
form a ohmic silicide contact to a p-type region, the formation of ohmic 
contact to the n-type substrate 12 must be avoided, since such a contact 
would short circuit the device. The second implant would lower the 
conductivity of the n+ regions, e.g. 20 and 24, but recent experiments 
have indicated that this lowered conductivity could be tolerated. 
Next, as shown in FIG. 4, a thin layer 42 of high resistivity polysilicon 
is conformally deposited. This layer 42 must be at least half the 
thickness of the gate oxide 34. Thus a typical value for the thickness of 
the polysilicon layer 42 would be from 200 to 500 Angstroms of 
polysilicon. Polysilicon layer 42 is anisotropically etched, to leave a 
remnant of polysilicon layer 42 filling the undercut region 40 beneath the 
gate-level interconnect 32, as shown in FIG. 4. Thus, after this 
processing step, a continuous layer of polysilicon or silicon exists 
between the respective drain regions 24 and 26 and the gate-level 
interconnect 32. If siliciding of other regions on the device is desired, 
the oxide in those other desired regions can be appropriately etched, so 
that exposed silicon is left on all areas to be silicided. 
An appropriate metal can be deposited on the exposed silicon areas, and 
reacted to form silicide. In the presently preferred embodiment, platinum 
or titanium is used, but any metal which will form a silicide having a low 
sheet resistance may be used. The resulting structure is as shown in FIG. 
5. Note that a continuous layer of silicide 44 has been formed, which 
connects the gate level interconnect 32 to the n and p type regions 24 and 
26. 
The step of producing the undercut region 40, described above, ensures that 
the silicide layer 44 is continuous. If process parameters permit reliable 
production of a continuous and unbroken silicide layer 44 across the 
thickness of the gate oxide 34, without inserting the polysilicon layer 
42, then the additional step of preparing the undercut regions 40 and 
conformally applying the polysilicon layer 42 could be omitted. 
Further modifications of the above-described preferred embodiment are also 
possible. For example, instead of forming the gates and gate-level 
interconnects entirely of polysilicon, it would also be possible to form 
them of a layered structure comprising a layer 46 of silicide atop a layer 
48 of polysilicon, as shown in FIG. 6. 
It is also possible to combine the formation of first contacts according to 
the present invention with simultaneous formation of a 
silicide-over-polysilicon wiring structure, since the method of the 
present invention is easily adapted to provide a method for siliciding 
polysilicon gate-level interconnects outside of the regions where active 
devices are found. As discussed above, the oxide on the sidewalls of the 
gate-level interconnects is normally somewhat thinner than the oxide on 
top of them. This is normally due to the oxide layer which was grown 
before the gate-level polysilicon structures were formed. However, by 
further etching after the structure of FIG. 3 has been formed, or by 
reducing the thickness of the oxide initially grown over the polysilicon, 
oxide could be cleared from the top as well as from the sidewalls of the 
gate-level interconnects. Thus, all polysilicon gate-level interconnects, 
outside of the regions where active devices exist, are formed to include a 
further layer of silicide in parallel with the polysilicon conductors, so 
that conductivity is improved without affecting the integrity of the 
active devices. Normally, such siliciding of polysilicon wiring requires 
an additional masking step. However, when such a structure is formed 
within the context of the present invention, no additional process steps 
are required. Merely by changing the structure of the photoresist masking 
layer 36 from that shown in FIG. 2, so that the tops of the gate-level 
interconnects are not masked, the desired silicide-strapped wiring 
structure is achieved. 
In practice, further economies may be realized by implementing the 
generation of the appropriate masks algorithmically. FIG. 8a shows an 
example of the drawn images for a portion of a CMOS device. The drawn 
image 52 indicates the moat regions where active devices are to be formed, 
the drawn image 54 indicates the polysilicon gate-level structures, and 
the drawn image 56 indicates the regions where first contacts are to be 
formed. From these drawn images, the masking reticle which is to be used 
to form the first contacts may be easily formed. As shown in FIG. 8b, 
which exactly corresponds to FIG. 8a, a first contact reticle 58 has been 
algorithmically regenerated by a simple logical operation on the drawn 
images. First, the moat drawn image is slightly expanded horizontally. 
Second, the first contact reticle is algorithmically generated, by 
exposing all regions which are either: within the drawn first contact 
image 56, or outside the expanded moat region. 
In FIG. 7, the silicide structure 50 indicates the additional silicide 
wiring layer which is achieved by this embodiment of the present 
invention. 
Alternatively, if the process parameters and the thermal sensitivity of 
silicides do not permit silicide to be used for wiring, first contacts 
according to the present invention are formed at a very late stage of 
device formation, after all high-temperature stages have been completed. 
Alternatively, a relatively thick layer of metallic tungsten is deposited, 
and only partially reacted to form tungsten silicide. Thus, the advantages 
of ohmic contact formation and self-aligned contacts by siliciding, as 
disclosed above, are obtained, and the high conductivity of metallic 
tungsten, which shunts the silicide wiring thus formed, is also used to 
advantage. 
It should be noted that, since the silicide layer 44 together with the 
gate-level interconnect 32 straps across p- and n-type regions, no pn 
diode is formed, since all contacts are ohmic and no junction contacts are 
created. 
It will be obvious to those skilled in the art that further modifications 
and variations of the present invention may be instituted without 
destroying the scope of the inventive concepts contained therein.