The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.

FIELD OF THE INVENTION

The present invention may relate to a digital memory circuit including registers in which a bit may be individually addressable, for example, to be set, cleared (reset) or otherwise modified, without affecting the values of other bits in the same register. Such a register may be referred to herein as a read/modify/write (RMW) register, or as a bit addressable register. The present invention may be especially suitable for use in an integrated circuit, but it is not limited to such an implementation.

BACKGROUND OF THE INVENTION

RMW registers are registers with internal logic circuitry useable to provide a convenient way of directly changing the state of one or more bits in the register without affecting the other bits in the register. Data can be written directly to the register in one of various operating modes including: (i) an overwrite mode in which existing bit values are overwritten; (ii) a set mode in which selected bits are set while other bits are left unchanged, according to the data written; and (iii) a clear mode in which selected bits are cleared (reset) while leaving other bits unchanged, according to the data written. RMW registers find use in processor controlled systems, especially, module resets, interrupt enables, power enables, and input/output interfaces, providing bit-addressable modification (set/clear) functionality at the register to reduce processing burden at the processor, and to reduce traffic on shared busses.

A conventional RMW register includes dedicated logic circuitry for implementing the bit-modification functionality internally within the register. However, such logic circuitry increases the physical size of the register significantly. Where multiple RMW registers are used in an integrated circuit, a large amount of die area is consumed. Especially, when compared to the area occupied for simpler registers without built in bit-modification functionality.

SUMMARY OF THE INVENTION

The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be common to the plurality of multi-bit registers and may be responsive to data received through the memory circuit interface to writing a new bit value to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.

Advantages, features and objects of the present invention may include: (i) enabling RMW functionality to be implemented for multiple registers without each register having internal bit-modification circuitry and/or (ii) reducing the amount of die area occupied by multiple registers while still providing RMW bit-modification functionality for the multiple registers. Other advantages, features and objects of the invention will be apparent from the following description, claims and/or drawings.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Referring toFIG. 1, an integrated circuit10is shown in accordance with a preferred embodiment of the present invention. The circuit10may include a processor core12coupled by a bus16to a digital memory circuit14. The circuit14may be implemented as a read/modify/write (RMW) register bank. The bus16may be a shared bus which may also be coupled to other functional parts (not shown) of the integrated circuit10. For example, the bus16may be coupled to other memory circuitry (not shown), external interface circuitry (not shown), signal processing circuitry (not shown), etc. The bus16may be implemented as (i) an asynchronous bus in which there may be no clock, (ii) a synchronous bus where information may be transferred in time with a clock or (iii) a synchronous pipelined bus where multiple transactions may overlap to make use of internal latencies. The RMW register bank14may permit one or more individual bits of an addressed register in the register bank14to be set to a new value by a modify (or bit-modify) operation. The modify operation may comprise setting a bit value to a predetermined value, toggling the bit value, or any other operation on the bit value to meet the design criteria of a particular application.

Referring toFIG. 2, a more detailed block diagram of the RMW register bank14ofFIG. 1is shown. The RMW register bank14generally comprises a plurality of multi-bit registers18(only two registers18aand18bbeing shown for the sake of illustration), bit-modification logic20, a bus interface (or memory circuit interface)28communicating with the bus16, and decode/control logic30. The bit-modification logic20may be coupled to each of the plurality of registers18in the bank14. The bit-modification logic20may be configured to selectively write a predetermined logic value (e.g., 1 or 0) to at least one bit of a register18while leaving a state of at least one other bit of the register18unchanged. The predetermined logic value may be, in one example, a logic-1 for a “set” operation or a logic-0 for a “clear” operation. The bit-modification logic may also be configured to selectively modify at least one bit while leaving the state of at least one other bit unchanged. For example, a bit may be modified by a toggling operation. Each of the registers18may be implemented without internal modification (set/clear) circuitry. The bit-modification functionality may be provided for the bank14as a whole by the common bit-modification logic20. The implementation of a common bit-modification logic20for the bank14may be extremely advantageous (e.g., by enabling each register18, and hence the register bank14as a whole, to be generally more compact than conventional RMW registers in which each register includes its own dedicated bit-modification logic). Also, since a single register18is generally accessed at any one time, the common bit-modification logic20may efficiently be coupled to a particular register18to be accessed, and may read, modify and write data to the accessed register to implement the bit-modification functionality within the register bank14, but outside the individual register18.

Each register18may generally comprise a plurality of flip/flops22, for example, one flip/flop22for each bit position in the register18. Each register18may thus comprise “n” flip/flops (22a,22b, . . .22n), where “n” is the number of bits in a data word stored in the register18. An output23from each register18may be coupled to inputs of an output multiplexer24. Each output23may generally comprise “n” data lines, and the output multiplexer24may comprise “n” multiplexer channels (or sub-multiplexers) for providing an n-bit “read” signal26. The signal26may be presented to the bus interface28. The bit-modification logic20may generally be coupled on a data input path32from the bus interface28to inputs of the registers18. The data input path32may include “n” data lines, and the bit-modification logic20may include “n” channels or sub-circuits (20a,20b, . . .20n). The bit-modification logic20may also receive the n-bit “read” signal26, for use in performing bit-modification operations, as described in more detail below.

The decode/control logic30may receive address data on one or more address lines34from the bus interface28. The decode/control logic30may be configured to decode the address data to select a register18from the plurality of registers in the bank14corresponding to an address received from the bus16. The registers18may be arranged logically or physically in a multi-dimensional array and/or in groups. The address received from the bus16may be decoded appropriately to select a particular register18from the array and/or group. The decode/control logic30may be configured to generate one or more register select signals36for enabling the appropriate register18. The decode/control logic30may also generate one or more control signals38. The control signals38may control the registers18, the output multiplexer24, the bit-modification logic20and the bus interface28in accordance with an operating mode of the register bank14. The register bank14may be operable in one or more of the following modes:

(i) A read mode in which data may be read from an addressed register18and outputted to the bus16, without changing the data in the register18. For example, the addressed register18may be enabled by one or more appropriate select signals36, and the decode/control logic30may enable the output multiplexer24and the bus interface28to present the bit values from the addressed register18to the bus16.

(ii) An overwrite mode in which data received from the bus16may be written into an addressed register18overwriting the existing data in the register18. For example, the addressed register18may be enabled by one or more appropriate select signals36, and the decode/control logic30may control the set/clear logic20to pass the received data, without modification, from the bus interface28to the addressed register18.

(iii) A set mode in which data received from the bus16may be used to selectively set at least one “first” bit in an addressed register18, according to the data, without changing the states of at least one other “second” bit in the register. For example, the addressed register18may be enabled by one or more appropriate select signals36. The decode/control logic30may control the output multiplexer24to read out the current bit values from the addressed register18. The bit values may be presented to the bit-modification logic20. The bus interface28may be controlled to block output of the data to the bus16, where the bus is bidirectional (as otherwise a conflict with data being received on the bus16may occur). The decode/control logic30may control the bit-modification logic20to combine the read-out current bit values with the data received from the bus16to perform a set operation. For example, a set operation may be implemented as a logical-OR of the current bit values and the received data. For each bit position, when the received data is a logical-1, the bit may be written (set) as a logical-1 in the register18regardless of the current state of that bit in the register18; when the received data is a logical-0, the current bit state may be preserved (e.g., written back to the register18without any change).

(iv) A clear mode in which data received from the bus16may be used to selectively clear (e.g., set to zero, or reset) at least one “first” bit in an addressed register18, according to the data, without changing the states of at least one other “second” bit in the register18. For example, the addressed register18may be enabled by one or more appropriate select signals36. The decode/control logic30may control the output multiplexer24to read out the current bit values from the addressed register18to the bit-modification logic20. The bus interface28may be controlled to block output of the read out data to the bus16, where the bus is bidirectional (as otherwise a conflict with data being received on the bus16may occur). The decode/control logic30may control the bit-modification logic20to combine the read-out current bit values with the data received from the bus16to perform a clear (reset) operation. For example, a clear operation may be implemented as a logical-AND of the current bit values and an inversion (or complement) of the received data. For each bit position, when the received data is a logical-1, the bit may be written (cleared) as a logical-0 in the register18, regardless of the current state of the bit in the register18; when the received data is a logical-0, the current bit state may be preserved (e.g., written back to the register18without any change).

(v) A toggle mode in which data received from the bus16may be used to selectively toggle or invert the logic state of at least one “first” bit in an addressed register18, according to the data, without changing the state of at least one other “second” bit in register. For example, the addressed register18may be enabled by the one or more appropriate select signals36. The decode/control logic30may control the output multiplexer24to read out the current bit values from the addressed register18to the bit-modification logic20. The bus interface28may be controlled to block output of the data to the bus16, where the bus16is bi-directional (as otherwise a conflict with data being received on the bus16may occur). The decode/control logic30may control the bit-modification logic20to combine the read-out current bit values with the data received from the bus16to perform the toggle operation. For example, the toggle operation may be implemented as a logical-XOR of the current bit values and the received data. For each bit position, when the received data is a logic-1, the current bit state may be inverted (toggled) by the XOR operation, and the inverted state written to the register18; when the received data is a logic-0, the current bit state may be preserved (e.g., written back to the register18without any change).

In the above, the term “first” bits may refer generally to those bits which are forced (e.g., during a set or clear operation) to a certain value irrespective of their previous state or which are modified (e.g., during a toggle operation), and the term “second” bits may refer generally to those bits that retain the current bit value. The terms “first” and “second” are not limited to specific bit positions.

As described above, the bit-modification functionality may be provided by reading the current bit values of a register18, and providing the current bit values as an input to the bit-modification logic20in time for combination with write data received from the bus interface28. The bit-modification functionality may be provided, in one example, by a loop for cycling the contents of the register18through the bit-modification logic20. The timing of the loop may be controlled such that the current bit values may be read out and presented to the bit-modification logic20before the end of a bus cycle for writing data to the register bank14. Additionally or alternatively, one or more buffers (not shown) may be included for storing the data from the multiplexer24until the current bit values are provided to the bit-modification logic20.

As illustrated inFIG. 3, the register bank14may be especially useful when the bus16is implemented as a pipelined bus. InFIG. 3, bus cycles40may be generally represented by intervals. Address and control information42may generally precede corresponding data44on the bus16by one or more bus cycles40. During a first bus cycle40a, address and control information42amay be received from the bus16indicating an address of a register18and a type of operation. When the operation is a read operation or a modify operation (e.g., a set, clear or toggle operation), current bit values43of the addressed register18may be read out from the register18during a second bus cycle40bfollowing the first bus cycle40a. In the case of a read operation, the current bit values43may be outputted through the bus interface28to the bus16in the second bus cycle40b. In the case of an overwrite or modify operation, incoming data44amay be received from the bus16in the second bus cycle40b, by which time the current bit values43of the register18may already be available as an input to the bit-modification logic20if needed for a modify operation during the second bus cycle40b. Modified bit values45may be written to the register at the end of the second bus cycle40b. Therefore, the technique of looping of the current bit-values43through the bit-modification logic20which may be used in this embodiment to implement the bit-modification functionality, may be especially suitable for the signal timing of a pipelined bus.

Referring toFIG. 4, an alternative addressing technique is shown. The alternative technique may be especially useful when the bus16is implemented as an asynchronous bus. The alternative technique may reduce timing constraints in the register bank14. In an asynchronous bus, address/control information48and associated data49generally occupy the same bus cycle46. A “read and modify” operation48amay be carried out to read current bit values43from the register18. This may facilitate addressing the current bit values43prior to the data being needed for a modify part of the operation. The modify part of the operation48may be carried out following a first part of the bus cycle46by combining at the bit-modification logic20, the data49received from the bus16and the bit values43already read out during the cycle. This alternative technique may involve a bus cycle46that is longer than for a simple write operation. However, even doubling the cycle length, the alternative technique may remain considerably more efficient than the number of bus cycles and processor overhead for performing the same bit-modification functionality at the processor12.

FIGS. 5 and 6illustrate examples of sub-circuits (for example20a) of the bit-modification logic20. In general, a similar circuit may be repeated for each of the “n” bit positions. Portions of the circuits20aand20a′ may be simplified by omitting portions associated with bit-modification functionality that is not to be implemented.

Referring toFIG. 5, the sub-circuit20amay generally comprise a four-input multiplexer50controlled by a four-way control signal38from the decode/control logic30. A first input to the multiplexer50may be provided by a direct signal path52for the input signal32from the bus interface28. A second input to the multiplexer may be provided by an OR-gate54which may receive as inputs the input signal32and the read-out signal26from the output multiplexer24. The OR-gate54may perform the logical-OR combination described above for a set operation. A third input to the multiplexer may be provided by an AND-gate56which may receive as an inverted input the input signal32and as a non-inverted input the read-out signal26from the output multiplexer24. The AND-gate56may perform the logical AND combination described above for a clear operation. A fourth input to the multiplexer may be provided by an XOR-gate57which may receive as inputs the input signal32and the read-out signal26from the output multiplexer24. The XOR-gate57may perform the logical XOR combination described above for a toggle operation. The control signal38may control the multiplexer50to select the first input for an overwrite operation, the second input for a set operation, the third input for a clear operation, and/or the fourth input for a toggle operation.

Referring toFIG. 6, an alternative sub-circuit20a′ is shown. The sub-circuit20a′ may generally implement bit-modification limited to a set/clear functionality. The sub-circuit20a′ may generally comprise a first two-way multiplexer60and a second two-way multiplexer62. For this example, the control signal38may comprise two sub-signals38aand38b. The signal38amay have, in one example, a first state indicating an overwrite operation, and a second state indicating a modify operation. The signal38bmay, in one example, distinguish between the modify operation being a set operation or a clear operation. For example, the signal38bmay have a first state (e.g., a logic-1) for a set operation and a second state (e.g., a logic-0) for a clear operation. The first multiplexer60may be controlled by the first signal38ato select either a direct input path64for the input signal32(e.g., for an overwrite operation), or a modified input signal66from the second multiplexer62(e.g., for a modify operation). The second multiplexer62may provide the modify functionality by selecting between either the read-out signal26from the output multiplexer24, or the signal38b(which may be a logical-1 for a set operation or a logical-0 for a clear operation). The second multiplexer62may be controlled, in one example, by the input signal32.

Generally, in the circuit ofFIG. 2, the overwrite, and modify (e.g., set, clear and/or toggle) modes may be different forms of a general write mode in which data may be written into the addressed register18. The operating mode of the register bank14may be controlled (i) by the decode/control logic30in accordance with address data, or (ii) by separate mode control input signals from the bus16, or (iii) by a combination of both. In one example, a read/write mode signal received from the bus16may control whether data is to be outputted to the bus16(in response to a “read” control signal), or received from the bus16(in response to a “write” control signal). In the case of a “write” control signal, the particular mode (e.g., overwrite, set, clear or toggle) may be controlled by address mapping. Thus each register18may appear multiple times in an address map, having multiple addresses selected from: a first address corresponding to an overwrite operation; a second address corresponding to a set operation; a third address corresponding to a clear operation; and a fourth address corresponding to a toggle operation.

During a modify operation, the above circuits may be configured to treat the data from the bus interface28in a first manner, such that a logical-1indicates a bit position to be modified (e.g., set, cleared or toggled), and a logical-0 indicates a bit position to remain unmodified. However, it will be appreciated that the circuits may be configured treat the data from the bus interface28in a second manner such that a logical-1 indicates a bit position to remain unmodified, and a logical-0 indicates a bit position to be modified. Alternatively, the circuit may be configured to interpret the data from the bus interface28differently according to a particular modify operation. For example, the data may be treated in the first manner for a set operation and in the second manner for a clear operation. However, other configurations may be implemented accordingly to meet the design criteria of a particular application.

The foregoing description is merely illustrative of a preferred, non-limiting embodiment of the invention, and many modifications and equivalents will occur to the skilled man using the principles of the invention. Accordingly, the appended claims are intended to be construed broadly to cover all such modifications and equivalents.