THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A thin film transistor includes a semiconductor layer, a gate, a source and a drain. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridge region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridge region and the first channel region. The second lightly doped region connects the bridge region and the second channel region. The doping concentration of the bridge region is greater than that of the first lightly doped region and the second lightly doped region. The gate overlaps the bridge region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source and the drain are electrically connected to the first heavily doped region and the second heavily doped region respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 112105442, filed on Feb. 15, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The present invention relates to a thin film transistor and a manufacturing method thereof.

Description of Related Art

With the continuous advancement of modern information technology, display panels with various specifications have found widespread applications in consumer electronic products, including but not limited to mobile phones, notebook computers, digital cameras, and personal digital assistants (PDAs). Currently, thin-film transistors are extensively employed in the display field. In an effort to enhance the drain current of thin-film transistors, it is common practice to reduce the channel length. However, this approach often leads to the susceptibility of the drain current to the kink effect, resulting in an elevation of the saturation current. Moreover, the reduction in channel length may give rise to issues related to leakage current.

SUMMARY

The present invention offers a thin film transistor and an associated manufacturing method designed to alleviate the resistance of the semiconductor layer by means of the bridging region. Simultaneously, it aims to mitigate issues arising from the horizontal electric field within the bridging region by incorporating a first lightly doped region and a second lightly doped region.

At least one embodiment of the present invention provides a method for manufacturing a thin film transistor, including the following steps. Using a mask layer as a mask, the semiconductor material layer is doped once or twice to form a first lightly doped region, a second lightly doped region, a bridging region, a first intrinsic semiconductor region and a second intrinsic semiconductor in the semiconductor material layer, wherein the doping concentration of the bridging region is greater than the doping concentrations of the first lightly doped region and the second lightly doped region. An insulation layer is formed on the first lightly doped region, the second lightly doped region, the bridging region, the first intrinsic semiconductor region and the second intrinsic semiconductor region. Forming a gate electrode material layer on the insulation layer, wherein the gate electrode material layer overlaps the first lightly doped region, the second lightly doped region and the bridging region, and the gate electrode material layer partially overlaps the first intrinsic semiconductor region and the second intrinsic semiconductor region. Using the gate electrode material layer as a mask, another doping process is performed on the first intrinsic semiconductor region and the second intrinsic semiconductor region to form a first heavily doped region and a second heavily doped region in the first intrinsic semiconductor region and the second intrinsic semiconductor region, respectively. The gate electrode material layer is etched to form a gate electrode. Using the gate electrode as a mask, the portions of the first intrinsic semiconductor region and the second intrinsic semiconductor region that have not been doped in the aforementioned another doping process are doped to form the third lightly doped region and the fourth lightly doped region in the first intrinsic semiconductor region and the second intrinsic semiconductor region, respectively, wherein the first intrinsic semiconductor region between the first lightly doped region and the third lightly doped region is the first channel region, and the second intrinsic semiconductor region between the second lightly doped region and the fourth lightly doped region is the second channel region, wherein the first lightly doped region connects the bridging region and the first channel region, and the second lightly doped region connects the bridging region and the second channel region, and the doping concentrations of the first lightly doped region and the second lightly doped region are greater than that of the first channel region and the second channel region. A source electrode and a drain electrode are formed, wherein the source electrode and the drain electrode are electrically connected to the first heavily doped region and the second heavily doped region, respectively.

At least one embodiment of the present invention provides a thin film transistor. The thin film transistor includes a semiconductor layer, a gate electrode, a source electrode and a drain electrode. The semiconductor layer includes a first heavily doped region, a second heavily doped region, a bridging region, a first channel region, a second channel region, a first lightly doped region and a second lightly doped region. The first lightly doped region connects the bridging region and the first channel region. The second lightly doped region connects the bridging region and the second channel region. The bridging region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region are located between the first heavily doped region and the second heavily doped region. The doping concentration of the bridging region is greater than that of the first lightly doped region and the second lightly doped region. The doping concentrations of the first lightly doped region and the second lightly doped region are greater than the that of the first channel region and the second channel region. The gate electrode overlaps the bridging region, the first channel region, the second channel region, the first lightly doped region and the second lightly doped region. The source electrode and the drain electrode are electrically connected to the first heavily doped region and the second heavily doped region respectively.

DESCRIPTION OF THE EMBODIMENTS

FIG.1Ais a schematic top view of a thin film transistor10A according to an embodiment of the present invention.FIG.1Bis a schematic cross-sectional view taken along the line A-A′ ofFIG.1A. Referring toFIGS.1A and1B, the thin film transistor10A includes a semiconductor layer200, a gate electrode310, a source electrode322and a drain electrode324. In this embodiment, the thin film transistor10A further includes a substrate100, a first insulation layer110, a second insulation layer120and a third insulation layer130.

The substrate100is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (for example: conductive material, metal, wafer, ceramic or other suitable materials) or other suitable materials. However, the present invention is not limited thereto. In other embodiments, the substrate100may also be a flexible substrate or a stretchable substrate. For example, materials of the flexible substrate and the stretchable substrate may include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane (PU) or other suitable materials.

The first insulation layer110is located on the substrate100and covers the substrate100. The first insulation layer110has a single-layer structure or a multi-layer structure. In some embodiments, the material of the first insulation layer110includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulation materials, combinations of the foregoing materials, or other suitable insulation materials.

The semiconductor layer200is formed on the first insulation layer110. In some embodiments, the material of the semiconductor layer200includes amorphous silicon, polysilicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide or other suitable materials, or combinations of the above materials) or other suitable materials, or combinations of the above materials.

The semiconductor layer200has been doped to include a first lightly doped region212, a bridging region214, a second lightly doped region216, a first heavily doped region222, a third lightly doped region232, a second heavily doped region226, a fourth lightly doped region236, a first channel region242and a second channel region246. The first lightly doped region212, the bridging region214, the second lightly doped region216, the first channel region242and the second channel region246are located between the first heavily doped region222and the second heavily doped region226. The first lightly doped region212connects the bridging region214and the first channel region242. The second lightly doped region216connects the bridging region214and the second channel region246. The third lightly doped region232connects the first heavily doped region222and the first channel region242. The fourth lightly doped region236connects the second heavily doped region226and the second channel region246.

The doping concentrations of the bridging region214, the first heavily doped region222, and the second heavily doped region226are greater than those of the first lightly doped region212, the second lightly doped region216, the third lightly doped region232, and the fourth lightly doped region236(e.g., exceeding by 1 to 2 orders of magnitude). The doping concentrations of the first lightly doped region212, the second lightly doped region216, the third lightly doped region232and the fourth lightly doped region236are greater than those of the first channel region242and the second channel region246.

In some embodiments, the doping concentrations of the first lightly doped region212and the second lightly doped region216are the same or different from the doping concentrations of the third lightly doped region232and the fourth lightly doped region236. In some embodiments, the doping concentration of the bridging region214is the same as or different from the doping concentrations of the first heavily doped region222and the second heavily doped region226.

In some embodiments, the sum of the length L1of the first channel region242and the length L2of the second channel region246is less than 3 microns.

The second insulation layer120is located on the first insulation layer110and the semiconductor layer200, and covering the semiconductor layer200. The second insulation layer120has a single-layer structure or a multi-layer structure. In some embodiments, the material of the second insulation layer120includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulation materials, combinations of the foregoing materials, or other suitable insulation materials.

The gate electrode310is located on the second insulation layer120and overlaps the first lightly doped region212, the bridging region214, the second lightly doped region216, the first channel region242and the second channel region246in the normal direction ND of the top surface of the substrate100. In this embodiment, the gate electrode310does not overlap the first heavily doped region222, the second heavily doped region226, the third lightly doped region232and the fourth lightly doped region236in the normal direction ND of the top surface of the substrate100.

In some embodiments, the gate electrode310has a single-layer structure or a multi-layer structure, and the material of the gate electrode310includes gold, silver, copper, aluminum, molybdenum, titanium, tantalum, other metals or alloys of the foregoing metals.

The third insulation layer130is located on the second insulation layer120and the gate electrode310, and covering the gate electrode310. The third insulation layer130has a single-layer structure or a multi-layer structure. In some embodiments, the material of the third insulation layer130includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, organic insulation materials, combinations of the foregoing materials, or other suitable insulation materials.

The source electrode322and the drain electrode324are located on the third insulation layer130and are electrically connected to the first heavily doped region222and the second heavily doped region226, respectively. For example, the source electrode322and the drain electrode324are respectively electrically connected to the first heavily doped region222and the second heavily doped region226through conductive vias passing through the third insulation layer130and the second insulation layer120.

In some embodiments, the source electrode322and the drain electrode324have a single-layer structure or a multi-layer structure, and the materials of the source electrode322and the drain electrode324include gold, silver, copper, aluminum, molybdenum, titanium, tantalum, other metals or alloys of the foregoing metals.

In this embodiment, the thin film transistor10A is a top gate thin film transistor, but the invention is not limited thereto. In other embodiments, the thin film transistor10A is a bottom gate thin film transistor or a double gate thin film transistor.

Based on the above, arranging the bridging region214within the semiconductor layer200can reduce the resistance of the semiconductor layer, resulting in an increased drain current for the thin film transistor10A. Additionally, the strategic placement of the first lightly doped region212, the second lightly doped region216, the third lightly doped region232, and the fourth lightly doped region236helps suppress the generation of the horizontal electric field. This suppression, in turn, enhances the kink effect on the drain current and addresses issues related to leakage current.

FIG.2Ais a schematic top view of a thin film transistor10B according to an embodiment of the present invention.FIG.2Bis a schematic cross-sectional view taken along the line A-A′ ofFIG.2A. It should be noted herein that, in embodiments provided inFIG.2AandFIG.2B, element numerals and partial content of the embodiments provided inFIG.1AtoFIG.1Bare followed, the same or similar reference numerals being used to represent the same or similar elements, and description of the same technical content being omitted. For a description of an omitted part, reference may be made to the foregoing embodiment, and the descriptions thereof are omitted herein.

The main difference between the thin film transistor10B inFIG.2Band the thin film transistor10A inFIG.1Bis that the thin film transistor10B includes two gate electrodes.

Referring toFIGS.2A and2B, the thin film transistor10B includes a semiconductor layer200, a gate electrode310, a gate electrode330, a source electrode322and a drain electrode324. In this embodiment, the thin film transistor10B further includes a substrate100, a first insulation layer110, a second insulation layer120and a third insulation layer130.

The gate electrode310is a top gate electrode, and the gate electrode330is a bottom gate electrode. The gate electrode330is located between the substrate100and the first insulation layer110, and the semiconductor layer200is located between the gate electrode310and the gate electrode330. In this embodiment, the bridging region214, the first channel region242, the second channel region246, the first lightly doped region212and the second lightly doped region216of the semiconductor layer200are located between the gate electrode310and the gate electrode330. In this embodiment, the gate electrode310and the gate electrode330have the same length, but the invention is not limited thereto. In other embodiments, the gate electrode310and the gate electrode330include different lengths. For example, in some embodiments, the length of the gate electrode330is greater than the length of the gate electrode310, so that the gate electrode330partially overlaps the third lightly doped region232and/or the fourth lightly doped region236in the normal direction ND of the top surface of the substrate100.

In some embodiments, the gate electrode330has a single-layer structure or a multi-layer structure, and the material of the gate electrode330includes gold, silver, copper, aluminum, molybdenum, titanium, tantalum, other metals or alloys of the foregoing metals.

FIG.3Ais a schematic top view of a thin film transistor10C according to an embodiment of the present invention.FIG.3Bis a schematic cross-sectional view taken along the line A-A′ ofFIG.3A. It should be noted herein that, in embodiments provided inFIG.3AandFIG.3B, element numerals and partial content of the embodiments provided in FIG.2A toFIG.2Bare followed, the same or similar reference numerals being used to represent the same or similar elements, and description of the same technical content being omitted. For a description of an omitted part, reference may be made to the foregoing embodiment, and the descriptions thereof are omitted herein.

The main difference between the thin film transistor10C inFIG.3Band the thin film transistor10A inFIG.1Bis that the thin film transistor10C is a bottom gate thin film transistor.

Referring toFIGS.3A and3B, the thin film transistor10C includes a semiconductor layer200, a gate electrode330, a source electrode322and a drain electrode324. In this embodiment, the thin film transistor10C further includes a substrate100, a first insulation layer110, a second insulation layer120and a third insulation layer130.

The gate electrode330is a bottom gate electrode and is located between the substrate100and the first insulation layer110. The gate electrode330overlaps the first lightly doped region212, the bridging region214, the second lightly doped region216, the first channel region242and the second channel region246in the normal direction ND of the top surface of the substrate100. In this embodiment, the gate electrode330does not overlap the first heavily doped region222, the second heavily doped region226, the third lightly doped region232and the fourth lightly doped region236in the normal direction ND of the top surface of the substrate100, but the present invention is not limited thereto. In other embodiments, the gate electrode330partially overlaps the third lightly doped region232and/or the fourth lightly doped region236in the normal direction ND of the top surface of the substrate100.

FIGS.4A to4Iare schematic cross-sectional views of a manufacturing method of a thin film transistor10A according to an embodiment of the present invention. Referring toFIG.4A, a first insulation layer110is formed on the substrate100. A semiconductor material layer200′ is formed on the first insulation layer110.

Referring toFIG.4B, a mask layer PR is formed on the semiconductor material layer200′ and the first insulation layer110. The mask layer PR is, for example, cured photoresist, and the mask layer PR includes a first opening H1. In this embodiment, the sidewall S1of the first opening H1is a curved surface or an inclined surface, resulting in a reduction in the thickness of the mask layer PR as it approaches the first opening H1.

Referring toFIG.4C, a doping process HD1is performed on the semiconductor material layer200′ using the mask layer PR as a mask to form a first lightly doped region212, a second lightly doped region216, a bridging region214, a first intrinsic semiconductor region242′ and a second intrinsic semiconductor region246within the semiconductor material layer200′. The first lightly doped region212, the second lightly doped region216, and the bridging region214are located between the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′.

In this embodiment, the sidewall S1of the first opening H1is relatively gentle, and the thickness of the mask layer PR decreases as it approaches the first opening H1. During the doping process HD1applied to the semiconductor material layer200′ at the bottom of the first opening H1, the thinner section of the mask layer PR is easily removed, causing outward expansion of the first opening H1. The position where the first lightly doped region212and the second lightly doped region216are scheduled to form in the semiconductor material layer200′ at least partially overlaps with the sidewall S1of the first opening H1before outward expansion occurs.

Since the first lightly doped region212and the second lightly doped region216are only doped after the outward expansion of the first opening H1, the duration of doping for the first lightly doped region212and the second lightly doped region216in the doping process HD1is shorter than the duration of doping for the bridging region214in the doping process HD1. As a result, the doping concentration of the bridging region214is higher than the doping concentrations of the first lightly doped region212and the second lightly doped region216.

In some embodiments, the dopant used in the doping process HD1is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), and the first lightly doped region212, the second lightly doped region216and the bridging region214include P-type semiconductor layer, and the doping dosage of the doping process HD1is greater than 1E15 atom/cm2.

In some embodiments, the dopant used in the doping process HD1is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), and the first lightly doped region212, the second lightly doped region216and the bridging region214include N-type semiconductor layer, and the doping dosage of the doping process HD1is greater than 1E14 atom/cm2.

In this embodiment, by adjusting the type of the mask layer PR, the thickness of the mask layer PR, the slope of the sidewall S1, the energy of the doping process HD1, and/or the doping dosage of the doping process HD1, the outward expansion of the first opening H1during the doping process HD1can be achieved. Consequently, the mask layer PR can be utilized to form the first lightly doped region212, the second lightly doped region216, and the bridging region214having different doping concentrations.

In some embodiments, the dopant used in the doping process HD1is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), and the first lightly doped region212and the second lightly doped region216include a P-type semiconductor layer, and the doping dosage is 4E14 atom/cm2to 5E12 atom/cm2.

In some embodiments, the dopant used in the doping process HD1is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), and the first lightly doped region212and the second lightly doped region216include an N-type semiconductor layer, and the doping dosage is 4E13 atom/cm2to 6E12 atom/cm2.

The first lightly doped region212and the second lightly doped region216serve to suppress the generation of horizontal electric fields, thereby improving the impact of the kink effect on the drain current. Additionally, they contribute to the amelioration of current leakage issues.

Referring toFIG.4D, the mask layer PR is removed. The second insulation layer120is formed on the first lightly doped region212, the second lightly doped region216, the bridging region214, the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′.

Referring toFIG.4E, a gate electrode material layer310′ is formed on the second insulation layer120. The gate electrode material layer310′ overlaps the first lightly doped region112, the second lightly doped region116and the bridging region114in the normal direction ND of the top surface of the substrate100, and the gate electrode material layer310′ is partially overlaps the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′ in the normal direction ND of the top surface of the substrate100.

Referring toFIG.4F, using the gate electrode material layer310′ as a mask, another doping process HD2is applied to the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′ to form a first heavily doped region222and a second heavily doped region226, respectively. Since the portion of the first intrinsic semiconductor region242′ overlapped with the gate electrode material layer310′ and the portion of the second intrinsic semiconductor region246′ overlapped with the gate electrode material layer310′ are covered by the gate electrode material layer310′, the portion of the first intrinsic semiconductor region242′ and the portion of the second intrinsic semiconductor region246′ are not subjected to be dopped during the doping process HD2.

In some embodiments, the dopant used in the doping process HD2is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), and the first heavily doped region222and the second heavily doped region226include a P-type semiconductor layer, and the doping dosage of the doping process HD2is greater than 1E15 atoms/cm2.

In some embodiments, the dopant used in the doping process HD2is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), and the first heavily doped region222and the second heavily doped region226include an N-type semiconductor layer, and the doping dosage of doping process HD2is greater than 1E14 atoms/cm2.

In some embodiments, the doping dosage of the doping process HD2is the same as or different from the doping dosage of doping process HD1(referring toFIG.4C).

Referring toFIG.4G, the gate electrode material layer310′ is etched to form the gate electrode310. Using the gate electrode310as a mask, another doping process LD2is performed on the portions of the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′ that have not been doped in the doping process HD2to respectively form a third lightly doped region232and a fourth lightly doped region236in the first intrinsic semiconductor region242′ and the second intrinsic semiconductor region246′. The first intrinsic semiconductor region242′ between the first lightly doped region212and the third lightly doped region232is the first channel region242, and the second intrinsic semiconductor region246′ between the second lightly doped region216and the fourth lightly doped region236is the second channel region246.

In some embodiments, the doping dosage of the doping process LD2is less than the doping dosage of the doping process HD1(referring toFIG.4C) and the doping dosage of the doping process HD2(referring toFIG.4F).

In some embodiments, the dopant used in the doping process LD2is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), and the third lightly doped region232and the fourth lightly doped region236include a P-type semiconductor layer, and the doping dosage of the doping process LD2is 4E14 atom/cm2to 5E12 atom/cm2.

In some embodiments, the dopant used in the doping process LD2is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), and the third lightly doped region232and the fourth lightly doped region236include an N-type semiconductor layer, and the doping dosage of the doping process LD2is 4E13 atom/cm2to 6E12 atom/cm2.

In some embodiments, when the first channel region242and the second channel region244are P-type semiconductors, the doping dosage of the first channel region242and the second channel region244is less than 5E12 atoms/cm2; when the first channel region242and the second channel region244are N-type semiconductors, the doping dosage of the first channel region242and the second channel region244is less than 6E12 atoms/cm2.

Referring toFIG.4H, a third insulation layer130is formed on the second insulation layer120and the gate electrode310.

Referring toFIG.4I, an etching process is performed to form a first through hole TH1and a second through hole TH2passing through the second insulation layer120and the third insulation layer130. The first through hole TH1and the second through hole TH2respectively expose the first heavily doped region222and the second heavily doped region226.

Finally, returning toFIG.1B, the source electrode322and the drain electrode324are formed on the third insulation layer130. The source electrode322and the drain electrode324are respectively filled into the first through hole TH1and the second through hole TH2, respectively establishing electrical connections to the first heavily doped region222and the second heavily doped region226. At this point, the thin film transistor10A is roughly completed.

FIGS.5A to5Jare schematic cross-sectional views of a manufacturing method of a thin film transistor10B (referring toFIG.2B) according to an embodiment of the present invention. In this embodiment, a gate electrode330is formed on the substrate100, as shown inFIG.5A. Next, the steps ofFIG.5BtoFIG.5Jare performed. The steps inFIGS.5B to5Jare similar to the steps inFIGS.4A to4I, where the same or similar reference numerals are used to represent the same or similar elements, and description of the same technical content being omitted. For a description of an omitted part, reference may be made to the foregoing embodiment, and the descriptions thereof are omitted herein.

FIGS.6A to6Care schematic cross-sectional views of a manufacturing method of a thin film transistor according to an embodiment of the present invention. Continuing from the step inFIG.4A,FIG.6Ainvolves the formation of a mask layer PR on the semiconductor material layer200′ and the first insulation layer110. The mask layer PR, for example, is a cured photoresist and includes a first opening H1. In this embodiment, the first opening H1features steep sidewalls S1.

Using the mask layer PR as a mask, a first doping process HD1is performed on the semiconductor material layer200′ to form the bridging region214. In this embodiment, since the portion of the mask layer PR near the first opening H1is thick, the first opening H1is less prone to outward expansion during the initial doping process HD1. Consequently, the first portion242″ and the second portion246″ in the semiconductor material layer200′, which were not doped during the first doping process HD1, are positioned on either side of the bridging region214.

In some embodiments, the dopant used in the doping process HD1is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), the bridging region214includes a P-type semiconductor layer, and the doping dosage of the doping process HD1is greater than 1E15 atoms/cm2.

In some embodiments, the dopant used in the doping process HD1is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), the bridging region214includes an N-type semiconductor layer, and the doping dosage of doping process HD1is greater than 1E14 atoms/cm2.

Referring toFIG.6B, after the first doping process HD1, the mask layer PR is subjected to an ashing process AS so that the first opening H1expands outward and exposes the first portion242″ and the second portion246″.

Referring toFIG.6C, following the outward expansion of the first opening H1, a second doping process LD1is carried out, using the mask layer PR as a mask. This forms the first lightly doped region212and the first intrinsic semiconductor region242′ in the first portion242′, which remained undoped during the initial doping process HD1. Additionally, it results in the formation of the second lightly doped region216and the second intrinsic semiconductor region246′ in the second portion246′.

In some embodiments, the dopant used in the doping process LD1is a P-type dopant (such as boron, aluminum, gallium or other suitable elements), and the first lightly doped region212and the second lightly doped region216include a P-type semiconductor layer, and the doping dosage of the doping process LD1is 4E14 atom/cm2to 5E12 atom/cm2.

In some embodiments, the dopant used in the doping process LD1is an N-type dopant (such as phosphorus, arsenic, tellurium or other suitable elements), and the first lightly doped region212and the second lightly doped region216include an N-type semiconductor layer, and the doping dosage of the doping process LD1is 4E13 atom/cm2to 6E12 atom/cm2.

In the embodiments ofFIGS.6A to6C, there is no gate electrode between the first insulation layer110and the substrate100. However, the present invention is not limited thereto.

In other embodiments, as illustrated inFIGS.7A to7C, there is a gate electrode330between the first insulation layer110and the substrate100.

In summary, the thin-film transistor of the present invention, with a portion of the semiconductor layer overlapping with the gate electrode forming a bridging region, reduces the resistance of the semiconductor layer and enhances the drain current of the thin-film transistor. Additionally, by setting the first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region, the generation of horizontal electric fields is suppressed, thereby improving the impact of the kink effect on the drain current and addressing current leakage issues.