Semiconductor device and manufacturing method

To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon. The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium.

The contents of the following Japanese patent application are incorporated herein by reference:

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device and a manufacturing method.

2. Related Art

Conventionally, in a semiconductor element formed on a semiconductor substrate such as SiC, a structure is known in which a barrier film made of titanium or the like is formed below an electrode made of aluminum or the like, as shown in Patent Document 1, for example. By absorbing hydrogen atoms or hydrogen ions with the barrier film, it is possible to protect the gate insulating film and restrict fluctuation in the threshold value of the semiconductor element.

Patent Document 1: Japanese Patent Application Publication No. 2015-109474

There are cases where, as a result of thermal processing performed when forming the electrode or after formation of the electrode, the barrier film forms an alloy with the electrode and part of the barrier film is lost.

SUMMARY

According to a first aspect of the present invention, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon.

The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium.

The semiconductor device may further include an alloy layer that is formed between the first layer and the second layer and includes the first metal and the second metal. The Si-containing layer may be arranged between the first layer and the alloy layer.

A silicon concentration distribution of the semiconductor device may include a peak in a depth direction of the Si-containing layer. The silicon concentration on the second layer side of the peak may decrease more gradually than on the first layer side of the peak.

A mass ratio of the silicon at a position of the peak may be greater than or equal to 10%. The Si-containing layer may have a thickness that is greater than or equal to 10 nm. The Si-containing layer may have a thickness that is less than or equal to 150 nm. The first layer may a thickness that is greater than or equal to 10 nm. The first layer may a thickness that is less than or equal to 1.0 μm.

According to a second aspect of the present invention, provided is a manufacturing method of a semiconductor device. The manufacturing method may include first layer formation of forming a first layer above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The manufacturing method may include second layer formation of forming a second layer above the first layer. The second layer may contain a second metal differing from the first metal. The manufacturing method may include Si-containing layer formation of forming an Si-containing layer that contains silicon between the first layer and the second layer.

In the second layer formation, there may be an argon atmosphere inside a deposition chamber. Pressure within the chamber may be greater than or equal to 0.1 Pa. The pressure in the chamber may be less than or equal to 0.5 Pa. Temperature of a semiconductor substrate may be greater than or equal to 190° C. The temperature of the semiconductor substrate may be less than or equal to 400° C. In the second layer formation, silicon may be segregated between the first layer and the second layer by forming the second layer, to form the Si-containing layer.

In the second layer formation, the temperature of the semiconductor substrate may be greater than or equal to 250° C. The temperature of the semiconductor substrate may be less than or equal to 270° C.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a cross-sectional view of a semiconductor substrate100according to one embodiment of the present invention. The semiconductor substrate100includes a semiconductor substrate10. A semiconductor element such as a power MOSFET is formed on the semiconductor substrate10. The semiconductor substrate10is formed of a semiconductor such as SiC, for example. The semiconductor substrate10in the present example is N-type.

An N-type drift layer12is formed on the top surface of the semiconductor substrate10in the present example. The drift layer12is formed by epitaxially growing a semiconductor such as SiC, for example, on the semiconductor substrate10. A drain electrode26is formed on the bottom surface of the semiconductor substrate10.

A P-type base region14is formed in a partial region of the top surface of the drift layer12. The base region14is formed by injecting P-type impurities such as aluminum into a partial region of the top surface of the drift layer12, for example.

A P-type top surface region18is formed on a top surface of the base region14. The top surface region18is formed by epitaxially growing a semiconductor such as SiC, for example, on the base region14. A (P+)-type contact region16is formed in a partial region of the top surface region18, and reaches from the top surface to the bottom surface of the top surface region18. The contact region16is formed by ion-injecting P-type impurities such as aluminum into the partial region of the top surface region18, for example.

An (N+)-type source region20is formed in a partial region of the top surface region18. The source region20is formed by injecting N-type impurities such as phosphorous into a partial region of the top surface region18, for example. An N-type region is formed between divided portions of the top surface region18and between divided portions of the base region14, and this N-type region is connected to the drift layer12. In this Specification, this N-type region is also referred to as the drift layer12. After the impurities have been injected into the source region20and the contact region16, the impurities may be activated by annealing the semiconductor layers in an atmosphere of inert gas, such as argon.

On the top surface of the semiconductor layer, the top surface region18is formed in a manner to be sandwiched by the source region20and the drift layer12. A gate electrode24is formed above the top surface region18that is between the source region20and the drift layer12. The gate electrode24is formed of polysilicon into which impurities have been injected, for example. The gate electrode24may also be formed above the source region20and the drift layer12.

The gate insulating film22insulates the gate electrode24from the semiconductor layers such as the drift layer12. An insulating material such as SiO2, for example, is formed as the gate insulating film22using a method such as CVD. The gate insulating film22leaves portions of the source region20and the contact region16exposed.

A barrier layer34is formed on the gate insulating film22. The barrier layer34is formed to cover the gate insulating film22. The barrier layer34is formed of titanium nitride, for example. A silicide layer32is formed on the top surfaces of the source region20and the contact region16that are not covered by the gate insulating film22. The silicide layer32is a nickel silicide layer, for example.

A lower hydrogen-absorbing layer36is formed on the barrier layer34and the silicide layer32. The lower hydrogen-absorbing layer36is formed of a hydrogen-absorbing metal such as titanium. A nitride layer38is formed on the lower hydrogen-absorbing layer36. The nitride layer38is formed of titanium nitride, for example.

An upper hydrogen-absorbing layer40, which is an example of a first layer, is formed on the nitride layer38. The upper hydrogen-absorbing layer40contains a first metal that absorbs hydrogen. The first metal is titanium, for example. The upper hydrogen-absorbing layer40may be formed of the same material as the lower hydrogen-absorbing layer36.

A source electrode30containing a second metal that is different from the first metal is formed above the upper hydrogen-absorbing layer40. The second metal is aluminum, for example. The source electrode30may include a substance other than the second metal. For example, the source electrode30is an AlSi alloy containing silicon.

An Si-containing layer42containing silicon is formed between the upper hydrogen-absorbing layer40and the source electrode30. The Si-containing layer42refers to a region with a higher silicon concentration than the source electrode30. The silicon concentration of the source electrode30refers to the mass ratio of silicon relative to the entire source electrode30. A substance other than silicon may be included in the Si-containing layer42. For example, the first metal such as titanium is included in the Si-containing layer42.

By providing the Si-containing layer42between the upper hydrogen-absorbing layer40and the source electrode30, it is possible to restrict formation of an alloy between the source electrode30and the upper hydrogen-absorbing layer40. Therefore, a prescribed thickness of the upper hydrogen-absorbing layer40remains, and it is possible to maintain the hydrogen absorbing function. Accordingly, hydrogen is restricted from reaching the gate insulating film22, and it is possible to restrict the fluctuation of the threshold value of the semiconductor substrate100.

An alloy layer44including the first metal and the second metal may be formed between the upper hydrogen-absorbing layer40and the source electrode30. The alloy layer44in the present example is an alloy including aluminum and titanium. The Si-containing layer42may also include the second metal, but the mass ratio of the second metal in the Si-containing layer42is less than the mass ratio of the second metal in the source electrode30. At least a partial region of the Si-containing layer42preferably does not include the second metal. At least the interface with the upper hydrogen-absorbing layer40preferably does not include the second metal. The upper hydrogen-absorbing layer40does not include the second metal.

The Si-containing layer42may be formed between the upper hydrogen-absorbing layer40and the alloy layer44. In this way, it is possible to efficiently restrict the formation of an alloy between the second metal included in the alloy layer44and the first metal of the upper hydrogen-absorbing layer40. Furthermore, a portion of the Si-containing layer42may be formed in a portion of the alloy layer44. In other words, at least a partial region of the alloy layer44on the upper hydrogen-absorbing layer40side may include an alloy of the first metal, the second metal, and silicon.

The Si-containing layer42may be formed using sputtering or the like, after formation of the upper hydrogen-absorbing layer40and before formation of the source electrode30. Furthermore, the Si-containing layer42may be formed by segregating silicon above the upper hydrogen-absorbing layer40by performing thermal processing during or after the step of forming the source electrode30containing silicon. The segregation of the silicon can be controlled according to the concentration of silicon included in the source electrode30, the temperature and time used when forming the source electrode30, the thermal processing temperature and time after formation of the source electrode30, and the like.

FIG. 2is a schematic view of measurement results obtained by measuring the silicon concentration distribution in a cross section near the gate insulating film22. The Si-containing layer42in this example was formed by segregating the silicon contained in the source electrode30above the upper hydrogen-absorbing layer40during the step of forming the source electrode30or the like. InFIG. 2, the silicon concentration is shown schematically using dot density.

As shown inFIG. 2, the Si-containing layer42in the present example is formed in a region contacting the top end of the upper hydrogen-absorbing layer40. In this way, it is possible to restrict the formation of an alloy between the upper hydrogen-absorbing layer40provided under the Si-containing layer42and each of the metals that are farther upward than the Si-containing layer42.

FIG. 3shows an exemplary silicon concentration distribution in a depth direction of the Si-containing layer42shown inFIG. 2. The depth direction refers to the direction of a straight line connecting the upper hydrogen-absorbing layer40and the source electrode30across the shortest distance. InFIG. 3, the vertical axis indicates the silicon concentration, and the horizontal axis indicates the position in the depth direction. The vertical axis inFIG. 3uses the silicon concertation of the source electrode30as the origin.

In the Si-containing layer42formed by segregating the silicon included in the source electrode30, the silicon concentration is not uniform and there is a silicon concentration peak43at a prescribed depth position. Since the silicon concentration is high at the peak43, it is possible to restrict the diffusion of the metal such as aluminum that is farther downward than the peak43.

The silicon concentration on the source electrode30side of the peak43decreases more gradually than the silicon concentration on the upper hydrogen-absorbing layer40side of the peak43. In other words, the silicon concentration on the upper hydrogen-absorbing layer40side of the peak43decreases sharply. Therefore, it is possible to form the upper hydrogen-absorbing layer40up to a region near the peak43, and the film thickness of the upper hydrogen-absorbing layer40can be easily ensured.

For example, the silicon mass ratio at the peak43is greater than or equal to 10%. Therefore, it is possible to efficiently restrict the formation of an alloy between the first metal such as titanium and the second metal such as aluminum at positions farther downward than the peak43. The silicon mass ratio at the peak43may be greater than or equal to 5 times the silicon mass ratio in the source electrode30, or may be greater than or equal to 10 times the silicon mass ratio in the source electrode30.

If the source electrode30is an AlSi alloy, the silicon mass ratio in the source electrode30may be approximately 1%, greater than or equal to 2%, or greater than or equal to 3%. There are cases where it is possible to increase the silicon concentration segregated in the Si-containing layer42by increasing the silicon concertation in the source electrode30. Therefore, it is possible to effectively restrict the formation of an alloy between the first metal such as titanium and the second metal such as aluminum.

FIG. 4is a cross-sectional view of an exemplary step for forming each metal layer from the upper hydrogen-absorbing layer40to the source electrode30in a semiconductor substrate100manufacturing method. InFIG. 4, each metal layer is shown schematically as a flat layer.

In the semiconductor substrate100, the lower hydrogen-absorbing layer36made of titanium, the nitride layer38made of titanium nitride, the upper hydrogen-absorbing layer40made of titanium, and the source electrode30made of an AlSi alloy may be continuously deposited through sputtering without being exposed to the outside atmosphere. For example, these components were deposited continuously with a deposition chamber pressure of 0.3 Pa, using a magnetron sputtering apparatus.

First, in a first layer formation stage S400, the upper hydrogen-absorbing layer40is formed above the semiconductor substrate10. In the present example, the upper hydrogen-absorbing layer40is formed on the nitride layer38. As an example, the film thickness of the lower hydrogen-absorbing layer36is approximately 75 nm and the film thickness of the nitride layer38is approximately 75 nm. The initial film thickness T1of the upper hydrogen-absorbing layer40is approximately 75 nm, for example. As an example, the upper hydrogen-absorbing layer40is deposited while controlling the temperature of the semiconductor substrate10within a range from 150° C. to 250° C. using lamp heating, in an argon atmosphere inside the deposition chamber.

Next, in a second layer formation stage S402, the source electrode30is deposited on the upper hydrogen-absorbing layer40. The initial film thickness of the source electrode30is approximately 5 μm, for example. As an example, the source electrode30is deposited while controlling the temperature of the semiconductor substrate10within a range from 190° C. to 400° C. using lamp heating, in an argon atmosphere inside the deposition chamber. Furthermore, a protective film such as polyimide is formed above the source electrode30. After the formation of the protective film, annealing is performed at a temperature of approximately 380° C.

In the annealing performed during the formation of the source electrode30or after the formation of the protective film, the silicon included in the source electrode30is segregated and the Si-containing layer42is formed between the upper hydrogen-absorbing layer40and the source electrode30. Titanium, which is a portion of the upper hydrogen-absorbing layer40, and aluminum, which is a portion of the source electrode30, form an alloy together, thereby forming the alloy layer44.

It should be noted that the formation of the alloy layer44is restricted at positions farther downward than the peak43of the Si-containing layer42. In this way, even when the source electrode30is formed above the upper hydrogen-absorbing layer40, at least a portion of the upper hydrogen-absorbing layer40does not form an alloy and maintains its hydrogen-absorbing function. In the present example, the thickness T2of the remaining upper hydrogen-absorbing layer40was approximately 45 nm.

Furthermore, it is possible to restrict the formation of an alloy between the aluminum or the like included in the source electrode30and the titanium or the like included in the upper hydrogen-absorbing layer40by using the Si-containing layer42, and therefore it is possible for a portion of the upper hydrogen-absorbing layer40to remain even when the source electrode30is formed at a high temperature. Therefore, the source electrode30can be formed at a high rate and the coverage of the source electrode30can be improved.

The chamber pressure in the second layer formation stage S402may be greater than or equal to 0.1 Pa and less than or equal to 0.5 Pa. Furthermore, the substrate temperature in the second layer formation stage S402may be controlled to be a target value greater than or equal to 250° C., or greater than or equal to 270° C. Under such conditions, the Si-containing layer42can be formed efficiently.

The thickness of the Si-containing layer42may be greater than or equal to 10 nm and less than or equal to 150 nm. The thickness of the Si-containing layer42may be greater than or equal to 50 nm and less than or equal to 100 nm. If the Si-containing layer42is too thin, the effect of restricting alloy formation becomes small. Furthermore, if the Si-containing layer42is too thick, the resistance value between the source electrode30and the source region20or the like becomes undesirably large. The thickness of the Si-containing layer42can be adjusted using the concentration of the silicon contained in the source electrode30, the deposition temperature of the source electrode30, the pressure inside the deposition chamber, and the like.

The thickness T2of the remaining upper hydrogen-absorbing layer40is preferably greater than or equal to 10 nm and less than or equal to 1.0 μm. If the upper hydrogen-absorbing layer40is too thin, the hydrogen-absorbing effect becomes small. Furthermore, since the hydrogen-absorbing metal such as titanium is a relatively hard material, if the upper hydrogen-absorbing layer40is too thick, the upper hydrogen-absorbing layer40becomes easily breakable. The thickness T2of the upper hydrogen-absorbing layer40may be less than or equal to 100 nm. The thickness T2of the remaining upper hydrogen-absorbing layer40can be adjusted using the initial thickness T1, the deposition temperature of the source electrode30, the annealing temperature after formation of the source electrode30, and the like. The thickness of the alloy layer44may be greater than or equal to 10 nm and less than or equal to 50 nm.

FIG. 5shows results obtained by measuring the threshold value fluctuation of the semiconductor substrate100. In the present example, the fluctuation of the threshold voltage Vth relative to the application time was measured when a gate voltage of −30 V was applied in an environment where the surrounding temperature was 200° C.

FIG. 5also shows the measurement results for semiconductor devices that do not include an Si-containing layer42, serving as comparative examples. One comparative example includes a metal film formed by layering Ti/TiN/Ti/Al, and another comparative example includes a metal film formed by layering UAL The deposition conditions for the Ti and Al in these comparative examples are equivalent to the deposition conditions of the upper hydrogen-absorbing layer40and the source electrode30. In the comparative example, all of the Ti formed under the Al formed an alloy with the Al.

As shown inFIG. 5, the threshold voltage of the semiconductor substrate100barely fluctuates even after 1000 hours have passed. In contrast, the threshold voltages of the apparatuses according to the comparative examples decrease as the application time increases. By providing the Si-containing layer42, it was confirmed that the semiconductor substrate100is able to maintain the hydrogen-absorbing effect and to restrict the fluctuation of the threshold voltage.

In the semiconductor substrate100used in the measurements ofFIG. 5, the (000-1) plane (C plane) was used as the main plain of the semiconductor substrate10, but the same results are exhibited for a semiconductor substrate100using the semiconductor substrate10with the (0001) plane (Si plane) as the main plane.

FIG. 6is a cross-sectional view of another exemplary structure of the semiconductor substrate100. The semiconductor substrate100shown inFIG. 1includes a planar gate structure, but the semiconductor substrate100in the present example includes a trench gate structure.

The gate insulating film22in the present example is formed covering the side walls of the trench formed in the top surface of the semiconductor layer. Furthermore, the top surface of the trench is covered by the insulating film23. The gate electrode24is covered by the gate insulating film22within the trench. This trench is formed penetrating through the source region20and the base region14. The gate electrode24is formed at least in a range opposite the base region14. By applying a prescribed ON voltage to the gate electrode24, a channel is formed in the base region14opposite the gate electrode24.

The semiconductor substrate100in the present example also has a layered structure of metal films in the same manner as the semiconductor substrate100shown inFIG. 1. In other words, the Si-containing layer42is provided between the upper hydrogen-absorbing layer40and the source electrode30. With the semiconductor substrate100of the present example as well, it is possible to restrict the fluctuation of the threshold value.

Furthermore, the semiconductor substrate100may be an IGBT (Insulated Gate Bipolar Transistor). In this case, a (P+)-type collector region is formed on the bottom surface side of the semiconductor substrate10.

In this Specification, terms such as “up,” “down,” “above,” and “below” are not limited to up-down orientation in the direction of gravity. These terms refer to relative direction on an arbitrary axis.

LIST OF REFERENCE NUMERALS