Generating capacitance look-up tables for wiring patterns in the presence of metal fills

A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.

TECHNICAL FIELD

The present invention relates to generating capacitance look-up tables for wiring patterns in the presence of metal fills. More particularly, the present invention relates to using a charge neutrality principle of floating metal fill conductors in order to reduce capacitance computations for use in device simulation.

BACKGROUND

An electronic design layout, such as for an integrated circuit or printed circuit board, includes many substrate layers. Part of an electronic design's development process is to simulate the electronic design while taking into account the electronic design's layout. Some layers are “conductor” layers that include metal tracks for coupling portions of the electronic design, while other layers are “insulation” layers that isolate the conductor layers from each other. “Metal fills” are included on an electronic design layout in order to mitigate the impact of chemical mechanical polishing (CMP) on the insulation layers during device fabrication by prohibiting the CMP from etching too much into an insulation layer.

SUMMARY

A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.

DETAILED DESCRIPTION

Certain specific details are set forth in the following description and figures to provide a thorough understanding of various embodiments of the disclosure. Certain well-known details often associated with computing and software technology are not set forth in the following disclosure, however, to avoid unnecessarily obscuring the various embodiments of the disclosure. Further, those of ordinary skill in the relevant art will understand that they can practice other embodiments of the disclosure without one or more of the details described below. Finally, while various methods are described with reference to steps and sequences in the following disclosure, the description as such is for providing a clear implementation of embodiments of the disclosure, and the steps and sequences of steps should not be taken as required to practice this disclosure. Instead, the following is intended to provide a detailed description of an example of the disclosure and should not be taken to be limiting of the disclosure itself. Rather, any number of variations may fall within the scope of the disclosure, which is defined by the claims that follow the description.

The following detailed description will generally follow the summary of the disclosure, as set forth above, further explaining and expanding the definitions of the various aspects and embodiments of the disclosure as necessary. To this end, this detailed description first sets forth a computing environment inFIG. 8that is suitable to implement the software and/or hardware techniques associated with the disclosure.

FIG. 1is a diagram showing an electronic design layout, such as an integrated circuit layout or a printed circuit board layout, that includes signal conductors and metal fills. Layout190includes signal conductors A100and B110, which are metal tracks that carry signals from one portion of a circuit to another portion of a circuit. During device operation, these circuits apply electronic signals to signal conductors A110and/or B110corresponding to either a logical value of “1” or “0.” Capacitance induced on the signal conductors (e.g., self capacitance and coupling capacitance) plays a role in determining the speed at which the electronic signals propagate along the signal conductors. In order to properly simulate a design, layout considerations are taken into account and, therefore, signal conductor capacitance values are computed in order to effectively simulate how capacitances effect signal propagation along the signal conductors.

Layout190also includes metal fills A120, B125, and C130. The metal fills are not utilized in a device's actual design to propagate signals but, instead, are inserted into a device layout for fabrication purposes. Metal fills control metal density on VLSI chips and, therefore mitigate the impact of a chemical mechanical polishing (CMP) process on metal thickness. Since metal fills are not signal-carrying conductors, this disclosure treats metal fills A120, B125, and C130as electrostatically floating conductors.

Capacitance value computations involve overlaying grid points onto the device layout and computing charge values for each grid point.FIG. 1shows that some grid points reside on the signal conductors (grid points140); some grid points reside on the metal fills (grid points180); and some grid points reside on non-conducting surfaces (grid points150). As those skilled in the art can appreciate, grid point layouts may be non-symmetrical in nature and have a much finer granularity than what is shown inFIG. 1.

Grid points that are adjacent to a signal conductor are referred to herein as “neighboring signal conductor grid points” (e.g., grid point160). Charges computed on these grid points play a key role in computing the capacitance values for the signal conductors (seeFIG. 5and corresponding text for further details). Grid points adjacent to metal fills are referred to herein as “neighboring metal fill grid points” (e.g., grid point170).

A “system of equations” are generated based upon the grid points, which include 1) grid point potential equations and 2) zero charge equations. Grid point potential equations are generated for each non-conducting grid point, which utilize a 5-point finite difference equation that factors in dielectric constants and directional potential differences between adjacent grid points (seeFIG. 3Band corresponding text for further details). Zero charge equations are generated for each metal fill, which is based on the premise that the total charge on a metal fill is zero due to the fact that metal fills are not signal-carrying conductors, but rather floating conductors (seeFIG. 4Cand corresponding text for further details).

FIG. 2Ais a diagram showing potentials (voltage potentials) assigned to signal conductors along with metal fill surface potential variables assigned to metal fills during capacitance computations. Boundary conditions are established for computing capacitances, which include assigning a potential of “1” to a particular signal conductor, and assigning a potential of “0” to the remaining signal conductors. This boundary condition represents a logical 1 on one signal conductor and a logical 0 on the other signal conductors.FIG. 2Ashows that signal conductor A100is assigned a signal conductor surface potential (SCSP) of “1,” and signal conductor B110is assigned an signal conductor surface potential of “0.”

Metal fills A120, B125, and C130will have a surface potential somewhere between “1” and “0” because they are physically between signal conductor A100and signal conductor B110. Their surface potential, however, is unknown at this point. As such, each metal fill is assigned a metal fill surface potential (MFSP) variable. As can be seen, metal fills A120, B125, and C130are assigned metal fill surface potential variables MFSPA, MSFPB, and MFSPC, respectively. The metal fill surface potentials are subsequently related to metal fill grid points that, in turn, are factored into grid point potential equations (seeFIG. 2B-3Band corresponding text for further details).

FIG. 2Bis a diagram showing grid point potentials residing on a metal fill. When signal conductor A100is assigned a potential of “1” and signal conductor B110is assigned a potential of “0,” the potential values on grid points between the signal conductors decreases as they are farther away from signal conductor A100and closer to signal conductor110. For example, the potential at neighboring signal conductor grid point200is higher than the potential at neighboring metal fill grid point210.

Grid points residing on metal fill A120, however, all have the same potential due to the fact that metal fill A120is a conducting surface. As such, grid point220has the same grid point potential as grid point230. Since this grid point potential is unknown at this point, each of grid points220and230are assigned a metal fill grid point potential (MFGP) variable. The metal fill grid point potential variable is the same as the metal fill surface potential variable as discussed inFIG. 2Adue to the conducting properties of metal fill A120. As a result, grid point potential equations are generated for neighboring metal fill grid points that include the metal fill grid point potential variables (seeFIG. 3Aand corresponding text for further details).

FIG. 3Ais a diagram showing a relationship between a neighboring metal fill grid point and adjacent grid points in order to generate a grid point potential equation. Grid point210is the same as that shown inFIG. 2B, and is adjacent to metal fill A120. Grid point210's potential is derived by the potential value of its adjacent grid points (310,340,220, and300). Grid point210is located at position “i,j,” which positions its adjacent grid points at “i, j+1,” “i, j−1,” “i+1, j,” and i−1, j.” Since one of grid point210's adjacent grid points resides on metal fill A120(grid point220), the grid point potential equation for grid point210includes grid point220's corresponding metal fill grid point potential variable (MFGPA, seeFIG. 3Band corresponding text for further details).

FIG. 3Bshows a grid point potential equation that is generated for each non-conducting surface grid point. Grid point potential equation340is a 5-point finite difference equation that factors in dielectric constants (epsilons) and directional potential differences between adjacent grid points.FIG. 3Bshows that, when generating a grid point potential equation for grid point210shown inFIG. 3A, grid point220's corresponding metal fill grid point potential variable (MFGPA) is included as the potential for grid point “i+1, j.”

Each metal fill adds a variable (e.g., MFGPA) to its neighboring grid point potential equations. Meaning, the variable MFGPAis added to grid point potential equations for neighboring grid points around metal fill A120, and the variable MFGPBis added to grid point potential equations for neighboring grid points around metal fill B125(seeFIG. 6and corresponding text for further details).

In addition, a zero charge equation is added to the system of equations for each metal fill (seeFIGS. 4A-4Cand corresponding text for further details). As a result, by adding the same number of zero charge equations as the number of metal fill grid point potential variables to the system of equations, the system of equations in terms of the capacitances of the signal-carrying conductors remains solvable.

FIG. 4Ais a diagram showing potential differences between metal fill grid points and neighboring grid points. As discussed earlier, due to the fact that the total charge on a metal fill (metal fill400) is zero, the sum of the potential differences between all of the metal fill grid points and neighboring grid points is zero. For example, although the potential between FIG.4A's grid point A and grid point1may have a value, the sum of all of the potentials (arrows), and thus the charge induced on the surface, around metal fill400(boundary) is equal to zero. In simple formula terms where Pxyis the potential difference between grid point x and grid point y:
Total Boundary Charge=0=PA1+PA2+PA8+PA9+PA10+PB3+PB4+PB5+PB6+PB7

Since the metal fill grid point potentials are the same and equal to the surface potential of the metal fill (discussed previously), a zero charge equation may be generated for each metal fill, which includes the summation of the potential differences between all of the metal fill grid points and neighboring grid points (seeFIG. 4Cand corresponding text for further details).

FIG. 4Bshows a grid point layout that includes closely spaced grid points for computing capacitance values. For simplification purposes,FIG. 4Ashowed that grid points are separated in a manner such that only two grid points resided on metal fill400. As those skilled in the art can appreciate, grid point layouts may have finer granularity than that shown inFIG. 4A. Regardless of the grid point layout granularity, the total charge around a metal fill equals zero. For example, metal fill410includes18grid points and22neighboring grid points (includes neighboring metal fill grid point420). Neighboring metal fill boundary430results in a total boundary charge of zero and, therefore, a zero charge equation may be written to encompass the summation of the potential differences between the metal fill grid points and neighboring grid points.

FIG. 4Cshows an example of zero charge equation that is generated for each metal fill. Zero charge equation440is similar to grid point potential equation340shown inFIG. 3B, with the exception that zero charge equation440factors in each neighboring grid point around a metal fill (summation) and the neighboring boundary's total charge equaling zero.

Note that zero-charge equation440does not imply that a metal fill's capacitance is zero. Rather, zero-charge equation440implies that the metal fill's unknown surface potential is neither 0 nor 1 as with signal-carrying conductors. In terms of the computational grid used for computing the grid point potentials, the unknown surface potential of each metal fill is assigned to each grid point on the metal fill surface. Zero-charge equation440, therefore, becomes an equation relating the unknown surface potential to the grid point potentials of all the grid points in the immediate neighborhood of the metal fill. A zero charge equation is generated for each metal fill, and the zero charge equations are subsequently added to the system of equations for computation (seeFIG. 6and corresponding text for further details).

FIG. 5is a flowchart showing steps taken in computing capacitance values that are utilized during device simulation. Processing commences at500, whereupon processing selects a signal conductor from a layout file included in layout store508(step505). The layout file includes layout information pertaining to signal conductors and metal fills, such as for an integrated circuit or printed circuit board. At step510, processing assigns a potential (voltage potential) of “1” to the selected signal conductor, and assigns a “0” potential to the other, non-selected signal conductors. For example, assuming the layout includes 100 signal conductors, processing assigns a “1” to the first signal conductor and assigns a “0” to the remaining 99 signal conductors. Note that the metal fills included in the layout file are not included in voltage potential assignments. Layout store508may be stored on a nonvolatile storage area, such as a computer hard drive.

At step515, processing identifies the metal fills in the layout file and assigns a metal fill surface potential variable to each metal fill. For example, assuming there are50metal fills, processing assigns a different metal fill surface potential variable to each of the 50 metal fills, resulting in 50 metal fill surface potential variables.

Next, at step520, processing overlays a grid point grid; identifies the grid points residing on the metal fills; and assigns a corresponding metal fill grid point potential variable to each metal fill grid point. For example, the first two metal fills may have a metal fill surface potential variable assigned, such as surface potential variable1and surface potential variable2. In this example, each grid point residing on metal fill1will have a grid point potential (grid point potential1) that equals surface potential variable1, and each grid point residing on metal fill2will have a grid point potential (grid point potential2) that equals surface potential2.

Processing generates grid point potential equations for each non-conducting grid point at step525. For those grid points adjacent to a metal fill, processing includes the metal fill grid point potential variables in their grid point potential equations (seeFIGS. 3A,3B, and corresponding text for further details). The grid point potential equations are stored in system of equations store528. System of equations store528may be stored on a volatile or nonvolatile storage area, such as computer memory or a computer hard drive.

Next, processing generates zero charge equations for each metal fill at step530. A zero charge equation takes into account that the total charge on a metal fill's surface is equal to zero. Meaning, the charge induced on the metal fill surface by the total potential difference between the metal fill grid points and neighboring grid points is zero (seeFIGS. 4A-4Cand corresponding text for further details). The zero charge equations, for each metal fill, are stored in systems of equations store528at step535. At this, point, the system of equations includes grid point potential equations for each non-conducting grid point and zero charge equations for each metal fill (seeFIG. 6and corresponding text for further details).

Processing solves the system of equations at step540, which includes solving for the non-conducting grid point potentials (grid points not residing on a signal conductor or a metal fill), as well as solving for metal fill surface potentials (since the metal fill grid point potentials equal their corresponding metal fill surface potentials). At step545, processing identifies neighboring grid point potential values that are adjacent to the signal conductors (e.g., neighboring signal conductor grid point160shown inFIG. 1), and computes an electrostatic charge for each neighboring grid point based upon the solutions from step540.

Due to the fact that, in step510, boundary conditions were set at 1 and 0, the electrostatic charges of the neighboring signal conductor grid points are the same as a signal conductor's self and coupling capacitances (Capacitance=Charge/Voltage, where Voltage=1 from the boundary conditions). Therefore, processing stores the computed electrostatic charges as capacitance values for each signal conductor in capacitance table store555(step550).

A determination is made as to whether there are more signal conductors to select and assign a potential of 1 (decision560). For example, assuming 100 signal conductors, processing loops through steps510through550100 times, each time assigning a potential of 1 to a different signal conductor. If more signal conductors need to be selected, decision560branches to “Yes” branch562, whereupon processing loops back to select a different signal conductor (step565), and compute more capacitance values. This looping continues until each signal conductor has been assigned a 1, at which point decision560branches to “No” branch568. Processing simulates the design at step569utilizing the capacitance values stored in capacitance table store555, and processing ends at570.

Note that the number of times the system of equations is solved is equal to the number of signal-carrying conductors, and is independent of the number of metal fills. The incremental computational cost of augmenting the system of equations with variables describing the surface potentials of the metal fills is negligible when compared with the savings that result from reducing the number of system solutions and the elimination of an inversion of the metal fills own capacitance matrix. (seeFIG. 6and corresponding text for further details).

FIG. 6is a diagram showing a system of equations for computing capacitances that are utilized to simulate a device. System of equations600includes a number of grid point equations, such as that shown inFIG. 3B, for each grid point on a device layout. Grid points that are adjacent to, or neighboring, a metal fill will include the metal fill's corresponding metal fill grid point potential variable (discussed inFIGS. 3A and 3B). As can be seen, system of equations600includes grid point potential equations610, which correspond to grid points that neighbor metal fill A120. System of equations600also includes grid point potential equations620, which correspond to grid points that neighbor metal fill B125. And, system of equations600includes grid point potential equations630, which correspond to grid points that neighbor metal fill C130.

In addition, system of equations600includes zero charge equations640for each of metal fills A120, B125, and C130. The zero charge equations take into account that the total charge on a metal fill is equal to zero (seeFIG. 4A-Cand corresponding text for further details).

FIG. 7Ais a diagram showing a “third” dimension (3D) to a device layout.

An integrated circuit or printed circuit board typically includes multiple substrate layers in order to effectively route signal conductors. The disclosure described herein accounts for capacitance effects between signal conductors and metal fills residing on different substrate layers.FIG. 7shows three substrate layers A700, B710, and C720. As those skilled in the art can appreciate, a device's circuit board may include more or less layers than what is shown inFIG. 7A.

Substrate layers A700and C720include signal conductors730and750, respectively. Between these layers, substrate layer B710includes metal fill740. During capacitance computations, in addition to computing capacitances on a “planar,” top-substrate layer as discussed previously, the disclosure described herein computes capacitance values between substrates using the same approach, thus taking into account coupling capacitances resulting from signal conductors “above” and “below” a particular signal conductor.

FIG. 7Bis a diagram showing an embodiment that groups metal fills together for computing capacitance values.FIG. 7Bshows metal fill grouping boundary780, which groups15metal fills placed between signal conductors760and770. This embodiment may be preferred in situations when metal fills are in close proximity to each other.

In this embodiment, metal fill grouping boundary780is considered as a single metal fill for generating grid point potential equations and zero charge equations. Meaning, each of the grid points within metal fill grouping boundary780are assigned the same “metal fill grouping grid point potential variable.” The zero charge equation assumes that the total charge around metal fill grouping boundary780is zero, resulting in a single zero charge equation for the metal fills included in metal fill grouping boundary780.

FIG. 8illustrates information handling system800, which is a simplified example of a computer system capable of performing the computing operations described herein. Information handling system800includes one or more processors810coupled to processor interface bus812. Processor interface bus812connects processors810to Northbridge815, which is also known as the Memory Controller Hub (MCH). Northbridge815connects to system memory820and provides a means for processor(s)810to access the system memory. Graphics controller825also connects to Northbridge815. In one embodiment, PCI Express bus818connects Northbridge815to graphics controller825. Graphics controller825connects to display device830, such as a computer monitor.

Northbridge815and Southbridge835connect to each other using bus819.

In one embodiment, the bus is a Direct Media Interface (DMI) bus that transfers data at high speeds in each direction between Northbridge815and Southbridge835. In another embodiment, a Peripheral Component Interconnect (PCI) bus connects the Northbridge and the Southbridge. Southbridge835, also known as the I/O Controller Hub (ICH) is a chip that generally implements capabilities that operate at slower speeds than the capabilities provided by the Northbridge. Southbridge835typically provides various busses used to connect various components. These busses include, for example, PCI and PCI Express busses, an ISA bus, a System Management Bus (SMBus or SMB), and/or a Low Pin Count (LPC) bus. The LPC bus often connects low-bandwidth devices, such as boot ROM896and “legacy” I/O devices (using a “super I/O” chip). The “legacy” I/O devices (898) can include, for example, serial and parallel ports, keyboard, mouse, and/or a floppy disk controller. The LPC bus also connects Southbridge835to Trusted Platform Module (TPM)895. Other components often included in Southbridge835include a Direct Memory Access (DMA) controller, a Programmable Interrupt Controller (PIC), and a storage device controller, which connects Southbridge835to nonvolatile storage device885, such as a hard disk drive, using bus884.

ExpressCard855is a slot that connects hot-pluggable devices to the information handling system. ExpressCard855supports both PCI Express and USB connectivity as it connects to Southbridge835using both the Universal Serial Bus (USB) the PCI Express bus. Southbridge835includes USB Controller840that provides USB connectivity to devices that connect to the USB. These devices include webcam (camera)850, infrared (IR) receiver848, keyboard and trackpad844, and Bluetooth device846, which provides for wireless personal area networks (PANs). USB Controller840also provides USB connectivity to other miscellaneous USB connected devices842, such as a mouse, removable nonvolatile storage device845, modems, network cards, ISDN connectors, fax, printers, USB hubs, and many other types of USB connected devices. Removable nonvolatile storage device845, in one embodiment, stores computer program product893, which includes functional descriptive material894. While removable nonvolatile storage device845is shown as a USB-connected device, removable nonvolatile storage device845could be connected using a different interface, such as a Firewire interface, etcetera.

Wireless Local Area Network (LAN) device875connects to Southbridge835via the PCI or PCI Express bus872. LAN device875typically implements one of the IEEE 802.11 standards of over-the-air modulation techniques that all use the same protocol to wireless communicate between information handling system800and another computer system or device. Optical storage device890connects to Southbridge835using Serial ATA (SATA) bus888. Serial ATA adapters and devices communicate over a high-speed serial link. The Serial ATA bus also connects Southbridge835to other forms of storage devices, such as hard disk drives. Audio circuitry860, such as a sound card, connects to Southbridge835via bus858. Audio circuitry860also provides functionality such as audio line-in and optical digital audio in port862, optical digital output and headphone jack864, internal speakers866, and internal microphone868. Ethernet controller870connects to Southbridge835using a bus, such as the PCI or PCI Express bus. Ethernet controller870connects information handling system800to a computer network, such as a Local Area Network (LAN), the Internet, and other public and private computer networks.

WhileFIG. 8shows one information handling system, an information handling system may take many forms. For example, an information handling system may take the form of a desktop, server, portable, laptop, notebook, or other form factor computer or data processing system.