Semiconductor device

A semiconductor device includes a drain layer, a drift layer, a base region, a source region, trenches, base contact region, gate regions, and field plate electrodes. The drain layer extends in a first and a second direction. The drift layer is on the drain layer. The base region is on the drift layer. The source region is on the base region. The trenches are in an array and each trench reaches the drift layer from the source region. The base contact region is along the second direction in a region in which the trenches do not contiguously exist along the second direction and electrically connects the source region to the base region. Each gate regions is along an inner wall of the trenches. Each field plate electrodes is in an inside of the gate regions and is longer than the gate regions in the third direction.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2017-179484, filed on Sep. 19, 2017, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments of the present invention relate to a semiconductor device.

BACKGROUND

To secure a breakdown voltage of a low breakdown voltage metal-oxide-semiconductor field-effect-transistor (MOSFET) with a field plate structure, it is necessary to deepen a trench and increase a thickness of a field plate insulating film, and it is necessary to increase a volume of the trench. For this reason, a current path of a drift layer is narrowed due to the trench, and movement of carriers is prevented, so that a trade-off occurs in which on-resistance increases. To avoid this problem, it is an important task to reduce the on-resistance of the drift layer by making the trench as narrow as possible. For example, research has been conducted to reduce a width of a source electrode to secure a width of the drift layer.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a drain layer, a drift layer, a base region, a source region, trenches, base contact region, gate regions, field plate electrodes, first source contacts, second source contacts, and gate contacts. The drain layer of a first conductivity type extends in a first direction and a second direction crossing the first direction. The drift layer of the first conductivity type is formed on a surface that is one surface in a third direction crossing the first direction and the second direction of the drain layer. The base region of a second conductivity type is formed on a surface of the drift layer. The source region of the first conductivity type is formed on a surface of the base region. The plurality of trenches are formed in an array in the first direction and the second direction and the each of the trenches reaches the drift layer through the base region along the third direction from a surface of the source region. The base contact region of the second conductivity type is formed along the second direction in a region in which the trenches do not contiguously exist along the second direction between the trenches along the first direction and the base contact region is formed in the source region to electrically connect the source region to the base region being separate from the trenches. Each of the plurality of gate regions is formed along an inner wall of corresponding one of the trenches, via an insulating film, inside the corresponding one of the trenches. Each of the plurality of field plate electrodes is formed in an inside of corresponding one of the gate regions, via the insulating film, inside the corresponding one of the trenches along the third direction, and is formed longer than the corresponding one of the gate regions in the third direction Each of the plurality of first source contacts is formed on the base contact region and the source region along the second direction between the trenches along the first direction and the first source contacts electrically connect the base contact region to the source region. The plurality of second source contacts on each of the field plate electrode are connected the corresponding field plate electrode. The plurality of gate contacts on the corresponding gate region are electrically connected the gate region.

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the drawings, a ratio, a scale and the like are not accurate, and a portion indicated by a straight line or a flat surface is not necessarily a straight line or a flat surface, and may have unevenness at a degree not departing from a function and effect of a present embodiment. For simplicity of explanation, it is assumed that a drain layer is in a lower side, and a metal layer and a semiconductor layer such as a drift layer are formed above the drain layer.

Positions in a plan view of a gate region, a source region and the like will be described.FIG. 1is a plan view schematically illustrating a semiconductor device1according to the present embodiment. The semiconductor device1is, for example, an n-type power MOSFET. A drain layer and a drift layer of the semiconductor device1are not illustrated, and each metal layer that applies a voltage to the gate region, the source region, and a field plate region is indicated by a broken line or a solid line.

A first direction and a second direction are defined as illustrated inFIG. 1. The first direction and the second direction are illustrated to be orthogonal to each other; however, not limited thereto, the first direction and the second direction may cross at an angle other than a right angle.

The semiconductor device1includes a plurality of trenches50in the semiconductor layer including a base region, the source region, and a base contact region on the upper surface of the drift layer. The trenches50are provided, for example, in a rectangular lattice along the first direction and the second direction. For convenience of explanation, the trenches50each configures a rectangular region that has sides parallel to the first direction and the second direction and in which the sides parallel to the second direction are longer than the sides parallel to the first direction. The configuration of each of the trenches50is not limited thereto, and may be, for example, a square shape. In this case, an arrangement of the trenches50in the semiconductor layer may also be a square lattice.

Between the two trenches50formed along the first direction, the base contact region for applying a voltage to the base region is formed in the source region so as not to be adjacent to the trenches50. A first source contact26for applying a voltage to the base contact region and the source region is placed along the second direction between the trenches50formed along the first direction. The first source contact26is further connected, on the upper surface thereof, to a first metal layer30.

In this way, each of the trenches50is separated from the other trenches50in the first direction and the second direction, and each of the trenches50is independently formed.

In each of the trenches50, a field plate electrode along the second direction is provided. A second source contact28connects the field plate electrode and the first metal layer30. That is, the second source contact28is connected, on the lower surface thereof, to the field plate electrode, and is connected, on the upper surface, to the first metal layer30.

Around the field plate electrode, the gate region is formed to go around the inner wall of each of the trenches50. Two gate contacts32for applying a voltage to the gate region are formed in each of the trenches50along the first direction. Each of the gate contacts32is connected, on the lower surface thereof, to the gate region, and connected, on the upper surface, to a second metal layer34.

In the above description, it is described that each contact and metal are separate; however, they may be integrally formed. That is, the first source contact26and the second source contact28may be formed integrally with the first metal layer30, or the gate contact32may be formed integrally with the second metal layer34.

The above is a description of an arrangement of the trenches50in a plan view of the semiconductor device1. Subsequently, a structure of the semiconductor device1will be described with reference to cross-sectional views.

FIG. 2Ais an A-A cross-sectional view inFIG. 1, andFIG. 2Bis a B-B cross-sectional view inFIG. 1. Each figure illustrates a connection between the gate region and the metal, and a connection between the source region and the metal. The structure along the first direction will be described with reference to these two figures. A third direction is a direction substantially orthogonal to the first direction and the second direction; however, not limited thereto, the third direction may have an angle other than a right angle. Hereinafter, as for a vertical direction and a height direction, with reference to the third direction, a direction in which a drain layer10is provided is referred to as a lower side, and a direction in which the metal layer is provided is referred to as an upper side.

The semiconductor device1includes the drain layer10, a drift layer12, a base region14, a source region16, a base contact region18, an insulating film20, a field plate electrode22, a gate region24, the first source contact26, the second source contact28, the first metal layer30, the gate contact32, the second metal layer34, an interlayer insulating film36, and a third metal layer38. Among these, the field plate electrode22and the gate region24are provided in each of the trenches50via the insulating film20.

The drain layer10is a layer that forms the drain of the semiconductor device1. The drain layer10is formed of a semiconductor of a first conductivity type, for example, an n+-type semiconductor. The drain layer10is connected, on the lower surface thereof, to a drain electrode (not illustrated), and a carrier flow is formed from the source to the drain by applying a potential difference between the source and the drain.

The drift layer12is a layer for adjusting a voltage applied to the semiconductor device1. The drift layer12is formed of the semiconductor of the first conductivity type, for example, an n−-type semiconductor. The drift layer12is formed such that the lower surface thereof is in contact with the upper surface of the drain layer10.

The base region14is arranged such that the lower surface thereof is in contact with the upper surface of the drift layer12. The base region14is formed of a semiconductor of a second conductivity type, for example, a p−-type semiconductor. The base region14is a region that forms a channel and enables carriers to flow from the source region16to the drain layer10in a case where a voltage is applied to the gate region24.

The source region16is arranged such that the lower surface is in contact with the upper surface of the base region14. The source region16is formed of the semiconductor of the first conductivity type, for example, the n+-type semiconductor. The carriers flow from the source region16to the drain layer10by a potential difference between the source region16and the drain layer10in a case where a voltage is properly applied to the gate region24.

The base contact region18is arranged adjacent to the source region16for applying a voltage to the base region14, and such that the lower surface thereof is in contact with the base region14. The base contact region18is formed of the semiconductor of the second conductivity type, for example, a p+-type semiconductor.

The insulating film20includes a field plate insulating film that insulates the field plate electrode22from other regions, an interlayer insulating film that insulates the gate region24from other regions, and an interlayer insulating film that insulates the source region16from other regions, and is appropriately insulates these electrodes or regions from other regions. The insulating film20is provided in the trenches50and between the semiconductor layer and the metal layer.

The field plate electrode22is arranged in each of the trenches50via the insulating film20along a direction of each of the trenches50in a direction from the drain layer10to the source region16, that is, in the vertical direction. The field plate electrode22is formed, for example, with polysilicon. The field plate electrode22may be connected to an electrode for applying a voltage to the source region.

The gate region24is a region for forming a channel or a depletion layer in the base region14in accordance with an applied voltage. The gate region24is arranged via the insulating film20to go around the field plate electrode22along the inner wall of each of the trenches50. The gate region24is formed, for example, with polysilicon.

The first source contact26is arranged such that the lower surface thereof is in contact with the upper surfaces of the source region16and the upper surface of the base contact region18, and to cover the base contact region18. The first source contact26is formed, for example, with the same metal as the first metal layer30.

The second source contact28is arranged such that the lower surface thereof is in contact with the upper surface of the field plate electrode22. Similarly to the first source contact26, the second source contact28is also formed, for example, with the same metal as the first metal layer30.

The first metal layer30is a layer including a metal functioning as an electrode for applying a voltage to the source. The first metal layer30is arranged on the upper surface of the gate region24via the insulating film20, is arranged on the upper surfaces of the source region16and the base contact region18via the first source contact26, and is arranged on the upper surface of the field plate electrode22via the second source contact28. As described above, the first metal layer30may be integrally formed with the first source contact26and the second source contact28. As illustrated in the figure, the first metal layer30may be partially provided with the source region16, the base contact region18, and the field plate electrode22via the insulating film20.

The gate contact32is arranged such that the lower surface thereof is in contact with the upper surface of the gate region24. The gate contact32is formed, for example, with the same metal as the second metal layer34.

The second metal layer34is a layer including a metal functioning as an electrode for applying a voltage to the gate. The second metal layer34is arranged on the upper surface of the gate region24via the gate contact32, and is arranged on the upper surfaces of the source region16and the base contact region18via the insulating film20. As described above, the second metal layer34may be integrally formed with the gate contact32. As illustrated in the figure, the second metal layer34may be partially arranged on the gate region24via the insulating film20. As illustrated inFIG. 1, the second metal layer34may be formed not to cover the upper surface of the field plate electrode22.

As illustrated inFIGS. 2A and 2B, the first metal layer30and the second metal layer34may be formed to be insulated from each other in the same layer such that distances from the drain layer10are equal to each other.

The interlayer insulating film36is an insulating film selectively arranged on the upper surface of the second metal layer34and the upper surface of the insulating film20around the second metal layer34in a metal layer formed of the first metal layer30and the second metal layer34. The interlayer insulating film36has a function of insulating the second metal layer34from the third metal layer38.

The third metal layer38is arranged in the metal layer formed of the first metal layer30and the second metal layer34. The third metal layer38is in contact with the upper surface of the first metal layer30, and is arranged on the upper surface of the second metal layer34via the interlayer insulating film36. As can be seen from this structure, the third metal layer38is selectively connected to the first metal layer30. That is, the third metal layer38has a function as an electrode for applying a voltage to the first metal layer30, and consequently the source region and the like.

As described above, in the semiconductor device1, the drift layer12is formed on the upper surface of the drain layer10, and the base region14is formed on the upper surface of the drift layer12. On the upper surface of the base region14, the source region16is formed, and the base contact region18is selectively formed. In the semiconductor layer formed of these, the plurality of trenches50is formed along the third direction to reach the drift layer12through the base region14from the upper surface of the source region16, in a lattice with respect to the first direction and the second direction.

In the inside of each of the trenches50, along the inner wall thereof, the gate region24is formed via the insulating film20, and in the inside of the gate region24, the field plate electrode22is formed via the insulating film20. As illustrated inFIG. 2B, the gate region24is formed shorter than the length in which the field plate electrode22is formed in the third direction. Further, the gate region24may be formed deeper in a direction to the drain layer10than the base region14.

InFIGS. 2A to 14D, the source region16and the gate region24are formed such that the upper surfaces thereof have equivalent heights; however, the present invention is not limited thereto. For example, to avoid increasing capacitance between the source and the gate, the upper surface of the gate region24may be formed to be positioned at the height equivalent to the lower surface of the source region16, or the position of the upper surface of the gate region24may be shifted further downward than the lower surface of the source region16.

The insulating film20is formed on the upper surfaces of the source region16, the base contact region18, the field plate electrode22, and the gate region24, and contacts are selectively formed in the insulating film20for applying voltages to respective regions in which the regions and the electrode exist.

As illustrated inFIG. 1, the first metal layer30is formed to be in contact with the lower surface of the third metal layer38serving as a source electrode for applying a voltage to the source, and the upper surfaces of the contacts connected to the source region16, the base contact region18, and the field plate electrode22. Meanwhile, the second metal layer34serving as a gate electrode for applying a voltage to the gate is formed under the third metal layer38to be in contact with the upper surface of the gate contact32, and not to be electrically connected to the third metal layer38via the interlayer insulating film36.

FIGS. 3A and 3Bare views respectively illustrating a C-C cross-sectional view and a D-D cross-sectional view inFIG. 1. That is,FIG. 3Ais a view illustrating a cross section including the gate contact32, andFIG. 3Bis a view illustrating a cross section including the second source contact28.

As illustrated inFIGS. 2A and 3A, the gate region24is provided on the upper side of the inner wall of each of the trenches50via the insulating film20to go around the inside of each of the trenches50. The second metal layer34is arranged along the first direction to be electrically connected to the gate contact32and, via the insulating film, to be insulated from the first metal layer30and the third metal layer38.

As illustrated inFIGS. 2B and 3B, the field plate electrode22is arranged via the insulating film20to extend in the second direction, in the inside of the gate region24. The insulating film20is arranged on the upper surface of the field plate electrode22, and the second source contact28is selectively arranged in the insulating film20. The first metal layer30is arranged to be contiguous in the first direction, and, in the second direction, to be insulated from the second metal layer34in a region where the second metal layer34exists, and the upper surface of the first metal layer30is connected to the third metal layer38.

As illustrated inFIGS. 2A, 2B, 3A, and 3B, on the upper surface of the drift layer12, the base region14is arranged in a region other than a region where each of the trenches50is provided, and on the upper surface of the base region14, the source region16is provided. In the source regions16in the first direction between the regions in which two trenches50are arranged, the base contact region18is arranged to selectively extend in the second direction.

In a region between the trenches50existing along the second direction, similarly to a region between the trenches50existing along the first direction, the base region14and the source region16are formed. For example, compared to a case where each of the trenches50contiguously extends along the second direction, regions of the base region14and the source region16can be made wider by a region where each of the trenches50is not contiguous.

FIGS. 4A and 4Bare cross-sectional views for explaining a structure inside each of the trenches50in more detail, and are views respectively illustrating an E-E cross section and an F-F cross section inFIG. 2A.

In the E-E cross section, as described above, the gate region24is formed via the insulating film20along the inner wall of each of the trenches50, and the field plate electrode22is formed via the insulating film20, in the inside of the gate region24that goes around. In the F-F cross section, the gate region24does not exist, so that the field plate electrode22is formed via the insulating film20, inside each of the trenches50.

As described above, according to the present embodiment, in the semiconductor device1, while the field plate electrode22is included and the vertical trench structure is maintained in which depletion of the drift layer12is facilitated, the plurality of trenches50is arranged in a dot pattern (that is, in a lattice pattern), whereby each of the drift layer12, the base region14, and the source region16can be widened in a plan view. In particular, the drift layer12is integrally formed without being partitioned by each of the trenches. As a result, an effect can be obtained of reducing on-resistance by the field plate electrode22, and the region of the drift layer can be increased, so that resistance in the drift layer12can be further reduced. This is because the base region14can be provided also in the region between the trenches50along the second direction, and a channel through which the carriers flow can be formed also in the region

Considering about a layout, for example, assuming that each of the trenches50is a rectangular parallelepiped region, a pitch between the trenches50along the first direction is 3.0 μm, a distance between the trenches50is 1.2 μm, a pitch between the trenches50along the second direction is 4.0 μm, and a distance between the trenches50is 1.2 μm. An area in a plan view of the drift layer12is (1.2×4.0+(3.0−1.2)×1.2)/(1.2×4.0)=1.45 times, per unit cell of 3.0×4.0, in comparison with a case where each of the trenches50is contiguously exists along the second direction. The resistance in the drift layer12is 0.69 times that is the reciprocal of 1.45 times. Assuming that the resistance in the drift layer12is 68% of the on-resistance, resistance of the semiconductor device1as a whole is 0.68×(1−0.69)=0.21 times, and the on-resistance can be reduced by about 21%.

Further, as described above, a volume of the trench can be reduced, so that a warp of a wafer can be reduced.

In the above description, it is described that the first conductivity type is an n-type; however, the first conductivity type may be a p-type. In this case, the second conductivity type is the n-type. In a case of the n-type, examples of impurities include arsenic (As), phosphorus (P), and the like. In a case of the p-type, examples of impurities include boron (B), boron fluoride (BF2+), and the like.

In either case, main components of the drain layer10, the drift layer12, the base region14, and the source region16are, for example, silicon (Si). Main components of the field plate electrode22and the gate region24are, for example, polysilicon containing impurities of the first conductivity type, amorphous silicon, and the like. A main component of the insulating film20is, for example, silicon oxide (SiO2).

The structure as described above can be confirmed by examining the cross section by a method that can investigate the sample at a high magnification, such as SEM or TEM. As for the cross section, for example, a cross section obtained by cutting off the metal layer, that is, a cross section obtained by cutting off the metal layer and the insulating film20by a plane horizontal to the first direction and the second direction is confirmed, whereby the arrangement of the trenches50can be confirmed. In addition, a cross section cut by a plane horizontal to the first direction and the third direction, or the second direction and the third direction is confirmed, whereby the structure inside each of the trenches50can be confirmed.

Hereinafter, a manufacturing process of the semiconductor device1according to the present embodiment will be described. Hereinafter, inFIGS. 5A to 14D, Fig. xA is a cross-sectional view illustrating an A-A cross section, Fig. xB is a cross-sectional view illustrating a B-B cross section, Fig. xC is a cross-sectional view illustrating a C-C cross section, and Fig. xD is a cross-sectional view illustrating a D-D cross section.

First, a semiconductor substrate is prepared in which the n-type drift layer12having an impurity concentration lower than that of the drain layer10is formed on the upper surface of the n+-type drain layer10. Then, resist is formed on the upper surface of the drift layer12, and etching is performed to selectively form the trenches50. The trenches50are formed by dry etching, for example. Thereafter, the resist is removed, whereby the trenches50are formed in the drift layer12, as illustrated inFIGS. 5A to 5D. A method for forming and removing the resist is not particularly limited.

ComparingFIGS. 5A and 5BwithFIGS. 5C and 5D, the width in the first direction of each of the trenches50and the width in the second direction have a large difference; however, the embodiments are not limited thereto, and the trenches50can be adopted each having an equivalent width. In the present embodiment, since the field plate electrode22is formed in each of the trenches50, the width in the second direction is larger than the width in the first direction.

Next, as illustrated inFIGS. 6A to 6D, an insulating film60is formed on the inner wall of each of the trenches50and the upper surface of the drift layer12. The insulating film60is formed by, for example, a thermal oxidation method or chemical vapor deposition (CVD). Then, on the upper surface of the insulating film60formed, a semiconductor film62is formed including polysilicon to be the field plate electrode22via the insulating film60in the trenches50.

The semiconductor film62is formed by, for example, forming polysilicon on the inner wall and the upper surface of the insulating film60by CVD, and then diffusing impurities such as phosphorus (P) into the polysilicon formed. For example, by diffusing impurities into the polysilicon by thermal diffusion or ion implantation, the semiconductor film62is formed.

As illustrated inFIGS. 6A to 6D, through this process, the semiconductor film62is formed via the insulating film60, selectively along the second direction, inside each of the trenches50.

Next, as illustrated inFIGS. 7A to 7D, the semiconductor film62is etched, and etched back, whereby the field plate electrode22formed from the semiconductor film62is formed, via the insulating film60, in each of the trenches50. This etching is performed by, for example, reactive ion etching (RIE), chemical dry etching (CDE), or chemical mechanical polishing (CMP).

Next, as illustrated inFIGS. 8A to 8D, the insulating film60is etched to form a space for the gate region24. This etching is performed, for example, by selectively etching the insulating film60by wet etching. By etching the insulating film60, the field plate electrode22protrudes from the insulating film60, as illustrated inFIGS. 8B and 8D.

Next, as illustrated inFIGS. 9A to 9D, the insulating film is formed again by the thermal oxidation method or the like, whereby the region of the insulating film60is expanded. The drift layer12including the inner wall of each of the trenches50and the field plate electrode22are covered with the newly formed insulating film, and the drift layer12and the field plate electrode22are insulated from the gate region24.

On the insulating film60, a semiconductor film64including polysilicon to be the gate region24is formed. The semiconductor film64is formed by CVD, for example. Further, impurities such as phosphorus (P) are diffused into the polysilicon forming the semiconductor film64by, for example, thermal diffusion or ion implantation.

Next, as illustrated inFIGS. 10A to 10D, the semiconductor film64is etched, and etched back, whereby the gate region24is formed, via the insulating film60, between the inner wall of each of the trenches50and the field plate electrode22, inside each of the trenches50. This etching is performed by, for example, RIE, CDE or CMP.

Next, as illustrated inFIGS. 11A to 11D, each diffusion region is formed. First, the base region14is formed by ion implantation, for example. On the upper surface of the drift layer12, p-type impurities (B+, BF2+and the like) whose concentration exceeds a concentration of n-type impurities of the drift layer12are implanted to the depth at which the base region14is formed.

Subsequently, above the upper surface of the base region14formed, n-type impurities (P+, As+and the like) whose concentration exceeds the concentration of the p-type impurities in the base region14are implanted to the depth at which the source region16is formed. In this way, the p-type base region14and the n+-type source region16are formed. Subsequently, selectively above the upper surface of the source region16formed, p-type impurities (B+, BF2+and the like) whose concentration exceeds the concentration of the n-type impurity in the source region16is implanted to the depth at which the base region14is reached. As a result, the p+-type base contact region18that reaches the base region14is formed, selectively inside the source region16. As illustrated inFIGS. 11A to 11D, the base contact region18is formed along the second direction selectively inside the source region16between the trenches50along the first direction. When the base contact region18is formed, implantation may be performed by forming resist in a portion other than a portion to be formed, or ion implantation may be performed selectively in a region where the base contact region18is formed without forming the resist.

Next, as illustrated inFIGS. 12A to 12D, the insulating film20and a contact region to each region are formed. First, an insulating film is newly deposited on the insulating film60by CVD, thermal oxidation method, or the like, and the insulating film20is formed.

Subsequently, a hole is formed in the insulating film20for forming a contact to each region to which a voltage is applied. This hole is formed, for example, by selectively forming a mask on the insulating film20, and selectively etching the insulating film20. The mask is formed by photolithography, for example. The etching is performed by, for example, dry etching such as RIE. Then, the mask is removed, whereby holes66,68, and70for forming contacts are formed, as illustrated inFIGS. 12A to 12D.

As illustrated inFIG. 12B, the hole66is formed in the insulating film20, such that the upper surface of the base contact region18and a part of the upper surface of the source region16adjacent thereto are exposed. As illustrated inFIGS. 12B and 12D, the hole68is formed in the insulating film20, such that a part of the field plate electrode22is exposed. As illustrated inFIGS. 12A and 12C, the hole70is formed in the insulating film20, such that a part of the gate region24is exposed.

Next, as illustrated inFIGS. 13A to 13D, after forming each hole for contact, the first metal layer30and the second metal layer34are formed. First, thin films of titanium (Ti) and titanium nitride (TiN) are formed by sputtering on the lower surfaces of the holes66,68, and70, that is, the upper surfaces of various semiconductor layers. For example, after forming the titanium thin film by sputtering, the titanium nitride thin film is formed by sputtering to cover the titanium thin film formed. After that, these titanium/titanium nitride films are subjected to a silicide reaction at an appropriate timing to form titanium silicide (TiSi) on the surfaces of various semiconductor films, and barrier metal is formed of titanium nitride. This silicide is formed, whereby low resistance is achieved between the metal (contact metal) and the field plate electrode22, the base contact region18, the source region16and the gate region24. This silicide may be formed of, for example, salicide.

Subsequently, metal to be each contact is formed. The metal forming the contact is, for example, tungsten (W). This metal is formed by CVD, for example. Then, this metal is etched back by, for example, dry etching to form various contacts. In this way, the first source contact26, the second source contact28, and the gate contact32are formed in the holes66,68, and70, respectively.

Subsequently, metal to be the first metal layer30and the second metal layer34is formed. This metal is, for example, aluminum (Al) or copper (Cu), and is formed by sputtering.

Subsequently, as illustrated inFIGS. 13C and 13D, a space72for forming an insulating film is formed by selectively removing the above metal, to separate the first metal layer30from the second metal layer34. A mask is selectively formed in a region to be the first metal layer30and a region to be the second metal layer34, and the metal is etched, whereby the formation is performed. The mask is formed by photolithography, for example. After forming the mask, the metal is etched by RIE, for example. Then, the space72is formed by removing the mask.

The above metal forming and etching processes may be reversed. That is, it is also possible to perform the formation of the space72that separates the first metal layer30and the second metal layer34as illustrated inFIGS. 13A to 13D, by forming the mask for the region to form the interlayer insulating film36, then forming the metal, and thereafter removing the mask.

Next, as illustrated inFIGS. 14A to 14D, the interlayer insulating film36is selectively formed on the upper surface of the second metal layer34. First, an insulating film is formed on the upper surfaces of the first metal layer30and the second metal layer34by CVD, for example. Next, the insulating film formed on the first metal layer30is selectively removed such that the interlayer insulating film36remains on the upper surface of the second metal layer34. For example, a mask is formed by photolithography on the second metal layer34and on the surface of its peripheral region on the interlayer insulating film36, and then the insulating film formed on the first metal layer30is etched by RIE or the like. In this way, the interlayer insulating film36is selectively formed on the upper surface of the second metal layer34and its peripheral region, and between the first metal layer30and the second metal layer34.

Finally, as illustrated inFIGS. 2A, 2B, 3A and 3B, the third metal layer38is formed, and then the semiconductor device1is formed. First, a metal to be the third metal layer38is formed on the upper surfaces of the interlayer insulating film36and the second metal layer34by sputtering, for example. Thereafter, planarization is performed by CMP, for example. Subsequently, unnecessary metal for the subsequent process may be masked by photolithography and removed by RIE or wet etching. The unnecessary metal means, for example, a metal existing around a chip or the like that is preferably removed at the time of dicing in a post-process subsequent to the preceding process.

Hereinafter, a modification of the arrangement of the trenches50and the like will be described.

FIG. 15illustrates an example in which one gate contact32is formed connecting the gate region24in each of the trenches50and the second metal layer34. In this way, there is no need for multiple gate contacts32, and the one gate contact32may be used. In addition, the example is illustrated in which the gate contact32and the second source contact28are on the same straight line along the second direction; however, the present invention is not limited thereto. For example, the gate contact32may be formed at a position deviated from the second source contact28not to be on the same straight line in the second direction

InFIG. 16, the arrangement of the trenches50is not a rectangular lattice but a rhombic lattice. With this configuration, it is possible to secure a region of the drift layer12similar to the case in the rectangular lattice described above. Further, the arrangement of the semiconductor layers including the drift layer12, the base region14, and the source region16is smoothed compared to the arrangement ofFIG. 1. This is because, in the arrangement ofFIG. 1, there are four portions where the semiconductor layers cross each other around each of the trenches50, but in this modification, such a crossed portion does not exist. With such an arrangement, as a whole of the semiconductor device1, the channel and the depletion layer can be more uniformly formed, and there is a possibility that the effect of reducing the resistance can be obtained more.

InFIG. 17, the arrangement of the trenches50is equivalent to that inFIG. 16, and in the trenches50adjacent in the second direction, the gate contacts32are arranged to line up on a straight line. With this configuration, it is possible to obtain the same effect as inFIG. 16, and to simplify the shapes of the first metal layer30and the second metal layer34.

FIGS. 18A to 18Care views illustrating other examples of the arrangement of the trenches50and the shapes of the trenches50. As illustrated inFIG. 18A, the shape of each of the trenches50may be a hexagonal shape. With this shape, for example, as illustrated in the figure, when the trenches are arranged in a rhombic lattice, the area where the drift layer12and the like exist depending on the region can be made more uniform. As illustrated inFIG. 18A, hexagons having the same orientation may be arranged in all columns, or alternatively, the orientation of the trenches50may be changed by 30° instead.

InFIG. 18B, the shape of each of the trenches50is circular. By making the shape circular like this, it is possible to increase the degree of freedom of arrangement. In this case, the field plate electrode22may also be formed in a circular shape. Since the field plate electrode22is formed in a circular shape, a distance between the field plate electrode22and the inner wall in each of the trenches50can be kept substantially uniform, so that influence of the field plate electrode22applied to the drift layer12can be made more even. In addition, the shape is not necessary to be exactly circular, and may be elliptical.

InFIG. 18C, each of the trenches50has a chamfered rectangular shape. In this way, the shape need not be exactly rectangular. It is not necessary to accurately form a rectangular shape by a process or the like, and the yield can be further increased. In addition, the chamfered portion makes it possible to equalize a distance between the field plate electrode22and the drift layer12as compared with the rectangular case, as in the case of the circular shape. The hexagonal shape illustrated inFIG. 18Amay be chamfered.

The shapes described above are examples, and the shape of each of the trenches50is not limited thereto. As long as each of the trenches50is formed independently from the other trenches50and the field plate electrode22, the gate region24, the source contact, and the like are similarly formed, it does not exceed the embodiment of the present invention.