Sigma-delta modulator with DAC resolution less than ADC resolution and increased dynamic range

A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator, and further providing increased dynamic range.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to sigma-delta modulators, and in particular, to sigma-delta modulators in which the resolution of the feedback digital-to-analog converter (DAC) is less than the resolution of the analog-to-digital converter (ADC) used in the modulator loop.

2. Related Art

Sigma-delta analog-to-digital modulators are often used in a sigma-delta ADC or sigma-delta DAC for providing shaping (filtering) of quantization noise. As the order of the sigma-delta modulator increases, the quantization noise is pushed further away in the frequency band from the signal being converted. Accordingly, sigma-delta ADCs and DACs, as well as their associated modulators, have become widely used in high precision applications.

A key design issue is the choice between a single-bit or a multi-bit quantizer, and in the case of a multi-bit quantizer, the number of bits to be used. With a single bit, the quantizer is binary and interpolation between its two output levels provides a linear response. Accordingly, single-bit architectures are often used since they provide high resolution without requiring accurate analog circuit elements.

However, since the resolution of the sigma-delta modulator relies on the oversampling ratio and the order of the modulator, obtaining a high signal-to-noise ratio (SNR) with relatively large signal bandwidths is problematic since the stability of higher order modulators costs a gain factor in the noise transfer function (NTF) and matching is critical in designing basic circuit blocks for cascaded architectures at high SNRs, e.g., above 90 dB.

A single-bit modulator also has a number of design requirements. Since both signal and quantization noise contribute to the output swing of the integrators, a large quantization step causes a large swing in the output voltage of the operational amplifiers. This requires using a small reference voltage relative to the power supply voltage.

A multi-bit quantizer increases the SNR (i.e., an improvement of SNR of approximately 6 dB for each additional bit). Also, using a multi-bit modulator reduces limits of a single-bit implementation, such as constraints on the reference voltage or demanding slew rate specifications, but does not provide the important characteristic of intrinsic linearity. Since the linearity of the noise-shaping elements depend upon the linearity of the DAC, it is necessary to use well-matched components to provide a DAC with the required linearity. Normally, such matching of integrated components is not adequate for high resolutions (e.g., more than 10-12 bits). Further, with a multi-bit architecture, the input of the downstream digital filter is a high-speed, multi-bit signal that requires complex processing prior to the first decimation. Further still, a multi-bit DAC is more difficult to fabricate in a very large scale integration (VLSI) environment with sufficient linearity needed for the high resolution quantized signal y1and low resolution (truncated) signal y2.

Referring toFIG. 1, reducing the number of levels, or bits, in the internal DAC of a sigma-delta modulator has been implemented in the form of post-processing of the quantized y1and truncated y2signals. In this implementation, represented by its linear model, a classic second order sigma-delta modulator10includes adder circuits12a,12b, integrators14a,14b, a high resolution (i.e., multi-bit) a quantizer16(with quantization error εQ), a truncation circuit18(with truncation error εT), and a feedback DAC20. A post-processor22processes the quantized y1and truncated y2signals.

The truncation of the quantized signal y1adds truncation error εTand provides a lower resolution output signal y2. These signals y1, y2can be expressed as follows:
y1=p+εQ(1)
y2=p+εQ+εT=p+εQT(2)

The truncated signal y2is fed back to the adders12a,12b. Accordingly, this signal can be expressed as follows (where STF is the signal transfer function and NTF is the noise transfer function):
y2=x*STF+εQT*NTF  (3)

The analog input signal p to the quantizer16can be expressed as follows:
p=y1−εQ=y2−εQT(4)

Substituting Equation (4) into Equation (3), the truncated signal y2can be expressed as follows:
y2=x*STF+(y2−y1+εQ)*NTF  (5)

Rearranging this produces the following expression:
y2*(1−NTF)+y1*NTF=x*STF+εQ*NTF  (6)

Accordingly, it can be seen that signal processing is required to obtain shaping of the quantization error εQinstead of the larger truncation error εT. However, a problem associated with this technique is the post-processing22required must be done using a significantly larger number of bits due to the need to process both the quantized y1and truncated y2signals.

Other implementations have been proposed in which the digital feedback signal is truncated through a digital sigma-delta modulator that shapes the truncation error. However, since the resulting error is injected at the input of the modulator, its shaping must be of a higher order than the order of the analog modulator. Moreover, the number of bits at the output of the modulator (see, e.g., U.S. Pat. No. 6,980,144, the disclosure of which is incorporated herein by reference) correspond to the resolution of the quantizer, and the first stage of the digital filter used in the decimation is complex as it operates with a long input word. The order of sigma delta modulator used for the truncation must be higher than the order of the modulator as the corresponding error is injected at the input of the quantizer. Therefore, for a second order modulator the truncation must be done by at least a third order scheme with the additional request to have zero delay. This problem is limited by a cancellation of the effect of the truncation error in the analog domain (see, e.g., U.S. Pat. No. 6,967,608, the disclosure of which is incorporated herein by reference). Combining these techniques (e.g., as disclosed in U.S. Pat. Nos. 6,980,144 and 6,967,608) enables the use of a lower order in the truncation generator, although it must still be at least an order of two to ensure suitable shaping and accounting for mismatch between the analog and digital transfer functions used in the cancellation mechanism.

SUMMARY OF THE INVENTION

In accordance with the presently claimed invention, a sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator, and further providing increased dynamic range.

In accordance with one embodiment of the presently claimed invention, a multiple order sigma-delta modulator includes:

an input electrode to convey an analog input signal;

one or more output electrodes to convey one or more digital output signals;

a plurality of analog adder circuits including first and last analog adder circuits, wherein the first analog adder circuit is coupled to the input electrode to receive the analog input signal and a first one of a plurality of analog feedback signals and provide a first one of a plurality of analog added signals, and each remaining one of the plurality of analog adder circuits is to receive a respective upstream one of a plurality of analog integrated signals and a respective additional one of the plurality of analog feedback signals and provide a respective downstream one of the plurality of analog added signals;

a plurality of analog integrator circuits including first and last analog integrator circuits, wherein the first analog integrator circuit is coupled to the first analog adder circuit to receive the first one of the plurality of analog added signals and provide a first one of the plurality of analog integrated signals, and each remaining one of the plurality of analog integrator circuits is coupled to a respective upstream one of the plurality of analog adder circuits to receive a respective upstream one of the plurality of analog added signals and provide a respective downstream one of the plurality of analog integrated signals;

analog-to-digital converter (ADC) circuitry coupled to the last analog integrator circuit to receive a last one of the plurality of analog integrated signals and provide an N-bit digital signal;

a digital adder circuit coupled to the ADC circuitry to receive the N-bit digital signal and a last one of a plurality of digital integrated signals and provide a digital added signal;

an output truncation circuit coupled between the digital adder circuit and the one or more output electrodes to receive the digital added signal and provide the one or more digital output signals including an M-bit digital signal, wherein N>M;

a plurality of feedback truncation and saturation protection circuits coupled to the one or more output electrodes to receive the M-bit digital signal and including first and last feedback truncation and saturation protection circuits to provide first and last ones of a plurality of truncated and saturation protected signals, to provide corresponding first and last ones of a plurality of truncation and saturation error feedback signals, and to provide corresponding first and last ones of a plurality of digital feedback signals, having M1 and M2 bits, respectively, whereinM≧M1 and M≧M2,the first one of the plurality of digital feedback signals comprises the first one of the plurality of truncated and saturation protected signals, andeach one of the plurality of feedback truncation and saturation protection circuits downstream from the first feedback truncation and saturation protection circuit is further to combine an upstream one of the plurality of digital integrated signals with an associated one of the plurality of truncated and saturation protected signals to provide a respective downstream one of the plurality of digital feedback signals;

a plurality of digital integrator circuits including first and last digital integrator circuits, wherein the first digital integrator circuit is coupled to the first feedback truncation and saturation protection circuit to receive the first one of the plurality of truncation and saturation error feedback signals and provide a first one of the plurality of digital integrated signals, and each remaining one of the plurality of digital integrator circuits is coupled to a respective upstream one of the plurality of feedback truncation and saturation protection circuits to receive a respective upstream one of the plurality of truncation and saturation error feedback signals and provide a respective downstream one of the plurality of digital integrated signals; and

a plurality of digital-to-analog converter (DAC) circuits including first and last DAC circuits to receive the plurality of digital feedback signals and provide the plurality of analog feedback signals.

In accordance with another embodiment of the presently claimed invention, a multiple order sigma-delta modulator includes:

a plurality of analog adder means including first and last analog adder means, wherein the first analog adder means is for adding an analog input signal and a first one of a plurality of analog feedback signals to provide a first one of a plurality of analog added signals, and each remaining one of the plurality of analog adder means is for adding a respective upstream one of a plurality of analog integrated signals and a respective additional one of the plurality of analog feedback signals to provide a respective downstream one of the plurality of analog added signals;

a plurality of analog integrator means including first and last analog integrator means, wherein the first analog integrator means is for integrating the first one of the plurality of analog added signals to provide a first one of the plurality of analog integrated signals, and each remaining one of the plurality of analog integrator means is for integrating a respective upstream one of the plurality of analog added signals to provide a respective downstream one of the plurality of analog integrated signals;

analog-to-digital converter (ADC) means for converting a last one of the plurality of analog integrated signals to provide an N-bit digital signal;

digital adder means for adding the N-bit digital signal and a last one of a plurality of digital integrated signals to provide a digital added signal;

output truncation means for truncating the digital added signal to provide the one or more digital output signals including an M-bit digital signal, wherein N>M;

a plurality of feedback truncation and saturation protection means for truncating and protecting the M-bit digital signal from saturation and including first and last feedback truncation and saturation protection means for providing first and last ones of a plurality of truncated and saturation protected signals, for providing corresponding first and last ones of a plurality of truncation and saturation error feedback signals, and for providing corresponding first and last ones of a plurality of digital feedback signals, having M1 and M2 bits, respectively, whereinM≧M1 and M≧M2,the first one of the plurality of digital feedback signals comprises the first one of the plurality of truncated and saturation protected signals, andeach one of the plurality of feedback truncation and saturation protection means downstream from the first feedback truncation and saturation protection means is further for combining an upstream one of the plurality of digital integrated signals with an associated one of the plurality of truncated and saturation protected signals to provide a respective downstream one of the plurality of digital feedback signals;

a plurality of digital integrator means including first and last digital integrator means, wherein the first digital integrator means is for integrating the first one of the plurality of truncation and saturation error feedback signals to provide a first one of the plurality of digital integrated signals, and each remaining one of the plurality of digital integrator means is for integrating a respective upstream one of the plurality of truncation and saturation error feedback signals to provide a respective downstream one of the plurality of digital integrated signals; and

a plurality of digital-to-analog converter (DAC) means including first and last DAC means for converting the plurality of digital feedback signals to provide the plurality of analog feedback signals.

In accordance with another embodiment of the presently claimed invention, a multiple order sigma-delta modulator includes:

an input electrode to convey an analog input signal;

one or more output electrodes to convey one or more digital output signals;

a plurality of analog adder circuits including first and last analog adder circuits, wherein the first analog adder circuit is coupled to the input electrode to receive the analog input signal and a first one of a plurality of analog feedback signals and provide a first one of a plurality of analog added signals, and each remaining one of the plurality of analog adder circuits is to receive a respective upstream one of a plurality of analog integrated signals and a respective additional one of the plurality of analog feedback signals and provide a respective downstream one of the plurality of analog added signals;

a plurality of analog integrator circuits including first and last analog integrator circuits, wherein the first analog integrator circuit is coupled to the first analog adder circuit to receive the first one of the plurality of analog added signals and provide a first one of the plurality of analog integrated signals, and each remaining one of the plurality of analog integrator circuits is coupled to a respective upstream one of the plurality of analog adder circuits to receive a respective upstream one of the plurality of analog added signals and provide a respective downstream one of the plurality of analog integrated signals;

analog-to-digital converter (ADC) circuitry coupled to the last analog integrator circuit to receive a last one of the plurality of analog integrated signals and provide an N-bit digital signal; and

digital signal processing (DSP) circuitry coupled between the ADC circuitry and the one or more output electrodes and programmed to:add the N-bit digital signal and a last one of a plurality of digital integrated signals to provide a digital added signal;truncate the digital added signal to provide the one or more digital output signals including an M-bit digital signal, wherein N>M;truncate and protect the M-bit digital signal from saturation and provide first and last ones of a plurality of truncated and saturation protected signals, provide corresponding first and last ones of a plurality of truncation and saturation error feedback signals, and provide corresponding first and last ones of a plurality of digital feedback signals, having M1 and M2 bits, respectively, whereinM≧M1 and M≧M2,the first one of the plurality of digital feedback signals comprises the first one of the plurality of truncated and saturation protected signals, andeach one of the plurality of feedback truncation and saturation protection means downstream from the first feedback truncation and saturation protection means is further for combining an upstream one of the plurality of digital integrated signals with an associated one of the plurality of truncated and saturation protected signals to provide a respective downstream one of the plurality of digital feedback signals;perform a plurality of digital integrations including first and last digital integrations, wherein the first digital integration integrates the first one of the plurality of truncation and saturation error feedback signals to provide a first one of the plurality of digital integrated signals, and each remaining one of the plurality of digital integrations integrates a respective upstream one of the plurality of truncation and saturation error feedback signals to provide a respective downstream one of the plurality of digital integrated signals; andperform a plurality of digital-to-analog (DA) conversions including first and last DA conversions to convert the plurality of digital feedback signals to provide the plurality of analog feedback signals.

DETAILED DESCRIPTION

The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention.

Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed.

Referring toFIG. 2, in a conventional second order sigma-delta modulator20, the usual equations describing its operation are as follows:
{(x−y)H1−y}H2+εQ=y(7)
y=x*z−1+εQ(1−z−1)2(8)

For an N-bit quantizer16, the word length of its output signal y is N-bits and it adds a quantization error εQcaused by the N-bit quantization. When the output y is reduced from N-bits to M-bits, this corresponds to the injection of an additional noise in the form of truncation noise εTdue to the truncation operation that reduces the resolution from N-bits to M-bits as if the modulator20used an M-bit quantizer.

Referring toFIG. 3A, in accordance with the presently claimed invention, it is intended to retain the benefit of the higher N-bit quantization by processing the truncation error εTin accordance with a filtering function HT, thereby introducing a processed truncation error εT*HTrather than the conventional truncation error εT. The truncated output signal y′ has a shorter word length of M-bits, and the operation of this modulator30acan be expressed as follows:
{(x−y′)H1−y′}H2+εQ+εTHT=y′(9)
y=x*z−1+(εQ+εTHT)(1−z−1)2(10)

The filter transfer functions H1, H2as respective functions of z are not specified here with particularity since a number of types of integrators (e.g., with and without delays as desired) can be used in accordance with the presently claimed invention. Nonetheless, it will be readily appreciated by one of ordinary skill in the art that Equation (10) is derived from Equation (9).

From these equations, it can be seen that the truncation error εTis shaped by the same transfer function as the quantization error εQ, but is also filtered by the filtering function H1. Filtering the truncation error εTwith a moderate high pass component is enough because, as shown by equation (10), the modulator already provides a shaping equal to the order of the modulator. The order of the extra shaping depends on the specific truncation level used.

While the modulator30aofFIG. 3Ais depicted as being of second order with first12aand last12badders and first14aand last14bintegrators, it will be readily appreciated by one of ordinary skill in the art that a first order modulator can also be implemented in accordance with the presently claimed invention. Such a sigma-delta modulator would include one adder (therefore both the first and last adder) and one integrator (therefore both the first and last integrator).

In the modulator30aofFIG. 3A, all M bits of the truncated output signal y′ are shown as being converted and provided as the same feedback signal to each of the adders12a,12b. However, referring toFIG. 3B, it will be readily appreciated by one of ordinary skill in the art that an additional output truncation circuit118bcan be used to provide multiple truncated output signals with a different number of quantization bits, which are converted by a corresponding feedback DAC for summing in a respective one of the adders. For example, in the second order modulator30bofFIG. 3B, the first output truncation circuit118aprovides truncated output signal y′1with M1 quantization bits while a second output truncation circuit118bprovides a second truncated output signal y′2with M2 quantization bits, each of which is converted by its own corresponding feedback DAC20a,20bfor summing in adders12aand12b, respectively. As a result, the truncation error εT1*HT1injected at the first output truncation circuit118ais shaped with an order equal to that of the modulator, while the truncation error εT2*HT2injected at the second output truncation circuit118bis shaped by a lower order.

Referring toFIG. 4, since the truncation error εTis a signal in the digital domain, it can be processed by filtering with a filtering function HA44, with the filtered result45summed with the quantized signal y, the result43aof which is further summed with the truncation error εTto produce the truncated output signal y′.

It can be seen by inspection that the output signal y′ can be expressed as follows:
y+HAεT+εT=y′(11)

Solving this for the truncation error filtering function HAproduces the following:
HA=HT−1  (12)

By way of example, if it is desired to provide an extra second order shaping, the truncation error filtering function HTcan expressed be as follows:
HT=(1−z−1)2(13)

As a result, the internal filtering function HAwill be:
HA=−2z−1+z−2(14)

As should be recognized from this example, other implementations of filtering can be used for processing the truncation error εT, including the introduction of additional zeroes in the z-plane at z=1. Additionally, zeroes can be introduced at other points of the z-plane for optimizing the dynamic range of the operational amplifiers used in the sigma-delta modulator. For example, it may be desirable to have a zero at z=1 and two complex conjugate zeros at less than (e.g., ⅔ of) the Nyquist frequency. As a result, the truncation error filtering function HTcan expressed be as follows:
HT(z)=(1−z−1)*(1+z−1+z−2)=1−z−3(15)

Accordingly the feedback filtering function HAbecomes a simple delay −z−3.

Referring toFIG. 5A, one example embodiment118aof the truncation stage includes a bit splitter circuit52(which can be implemented in accordance with well-known techniques), the internal filtering function44and the summation circuitry42, interconnected substantially as shown. The quantized signal y from the quantizer16is received, summed with the filtered truncation error ET, and split by the bit splitter circuit52. The (N-M)-bit truncation error εTis filtered by the filter circuit44(e.g., a simple delay −z−3, as discussed above) for summing with the N-bit quantizer signal.

Referring toFIG. 5B, one example embodiment of the bit splitter circuit52ofFIG. 5Aincludes a truncation circuit52aand adder52binterconnected substantially as shown. The M-bit truncated output signal y′ is differentially summed with the N-bit input signal43to produce the truncation error εT.

Based upon the foregoing discussion, it should be recognized that a number of significant benefits are provided by a DAC resolution reduction technique in accordance with the presently claimed invention. One benefit is a reduction in the word length of the output signal y′, which simplifies the internal feedback DAC (due to the reduced feedback word length), as well as further processing downstream (e.g., simplifying the first stage of the decimation filter). A second benefit is minimum additional processing in the form of the truncation error filtering function HA. A third benefit is the shaping of the truncation error εT by a noise transfer function having an order increased by the order of the truncation filtering function HA over the order of the host sigma-delta modulator, thereby minimizing, if not eliminating, a need for cancellation of the error. (For example, with a second order sigma-delta modulator and a k-order truncation error filtering function HA, the truncation error εT is shaped by a noise transfer function having an order of 2+k.) This last benefit is fully realized when the same truncated output signal y′ is fed back as in the circuitry ofFIG. 3A; however, when differently truncated output signals y′1, y′2are fed back as in the circuitry ofFIG. 3, the second truncated output signal y′2will experience a lower order shaping.

More particularly, with the presently claimed invention, the minimum modulator need only be first order, unlike the prior art (see, e.g., U.S. Pat. No. 6,980,144) which also requires the digital truncation to be of an order higher than that of the modulator (e.g., a second order modulator would require a digital truncation of at least third order). Indeed, in accordance with the presently claimed invention, additional zeros at frequencies other than zero (i.e., z=0) can be introduced as desired, e.g., to further reduce noise outside of the signal band.

Further, modulator designs of third order or higher often suffer from problems with circuit stability, and are generally matched with a lower order digital truncation (see, e.g., U.S. Pat. No. 6,967,608). For example, with a second order modulator and a second order truncation, the quantization error and truncation error are shaped with the same function and appear in the output with similar weights. With the truncation error higher than the quantization, the SNR is dominated by the truncation error, with the result being that the output can appear to have a lower number of bits.

Prior techniques have sought to avoid using digital modulators with orders higher than two and zero delay by estimating the effect of the truncation error after the first analog integrator and to inject at the input of the second integrator a digital signal converted by a DAC for canceling the truncation error that was passed through the first analog integrator. Such a technique can be successful if the estimate of the transfer function of the first analog integrator is accurate. Such designs can be reasonably stable with a large number of truncated bits but tend to become unstable with fewer truncated bits. Also, limitations exist due to mismatches among the various capacitors and finite gain or slew-rate of the operational amplifier which cause the transfer function of the first integrator to be different from the ideal z−1/(1−z−1) or 1/(1−z−1), with Such difference tending to reduce the effects of the cancellation. In contrast thereto, as noted above, a modulator in accordance with the presently claimed invention is not affected by stability issues because a lower order modulator (e.g., second order) can be used while still benefiting from the truncation error filter, i.e., resulting in k+2-order digital shaping for a second order modulator with a k-order truncation error filter.

Referring toFIG. 6, in addition to the output signal truncation circuitry118a, additional truncation circuitry128a,128bcan be used, along with digital integration circuits114a,114b, to provide increased tolerance of non-ideal operating characteristics of the analog integration circuits14a,14b. (In accordance with a preferred embodiment, the digital circuits12c,118a,128a,114a,128b,114bare implemented in the form of a digital signal processing (DSP) circuit120, which is well known in the art.) In accordance with an alternative embodiment, the incoming analog signal x can also be fed forward to the second adder12bas well as the quantizer16, thereby reducing signal gain requirements within the integration circuits14a,14b.

In accordance with a preferred embodiment of this sigma-delta modulator60a, the truncated output signal y′, which is provided to the downstream decimation filter, has M bits, as discussed above, while the further truncated signals y1and y2have M1 and M2 bits, respectively, such that N>M, M≧M1 and M≧M2, and preferably M2≧M1.

In accordance with this system architecture, the output signal S13bof the second adder12b, in terms of the output signals S21a, S21bof the feedback DACs20a,20bcould be expressed as follows.
S13b=H1a*(x−S21a)−S21b(16)

In terms of the digital input signals y1, y2to the DACs20a,20b, this can be written as follows.
S13b=H1a*(x−y1)−y2(17)

Further expanded in terms of the filtered truncation signals and the analog and digital integrator transfer functions, this can be written as follows.
S13b=H1a*(x−y′)−y′+ET1*HT1*(H1d−H1a)−ET2*HT2(18)

Solving this for the output signal y′, this becomes:

If the transfer functions of the corresponding analog14a,14band digital114a,114bintegrators are substantially equal, i.e., H1ais ≈H1dand H2a≈H2d, then this simplifies to the following:

If the filter function HTis chosen such that within the signal bandwidth of interest the equalization error εQis much greater than the filtered truncation error ET*HT(EQ>>ET*HT), then this can be further approximated as follows.

Referring also toFIG. 6A, in accordance with one example embodiment, the output quantizer16was implemented as a 5-bit quantizer and an oversampling ratio (OSR) of 128, output signal y′ had three bits, feedback signals y1and y2had two and three bits, respectively, and the output truncation error filter HTand denominator terms of equation 21 were selected as follows.

In order to minimize the effects of the truncation error ETwithin the signal bandwidth as compared to the quantization error εQ, i.e., so the transfer function within the signal bandwidth can be approximated according to equation 21, the order of the noise shaping of the truncation error ETmust be greater than the order of the noise shaping of the quantization error εQ. With reference to the truncation error ETterm in equation 23, it can be seen that this criteria is met. First, it can be seen that this term has three zeros at DC, which minimize the truncation error ETrelative to the quantization error εQwithin the signal bandwidth. Second, this term also has two complex conjugate zeros at one-fourth of the sampling frequency (Fs/4), and a zero at one-half of the sampling frequency (Fs/2, i.e., the Nyquist frequency), which further attenuate the truncation error ET, thereby reducing the required signal range of the quantizer16.

Another advantage of the architecture of such sigma-delta modulators60ais the ability to compensate for mismatches between the transfer functions of the corresponding analog14a,14band digital114a,114bintegration circuits. (In accordance with a preferred embodiment, corresponding transfer functions of the analog14a,14band digital114a,114bintegration circuits are at least approximately equal, i.e., the first analog14aand digital114aintegration circuit transfer functions are at least approximately equal, the second analog14band digital114bintegration circuit transfer functions are at least approximately equal, etc. However, depending upon the desired operating characteristics or system requirements, such approximate equalities among corresponding transfer functions may not be sufficient.) When their functions are not equal, i.e., H1a≠H1dand H2a≠H2d, the terms within equation 19 containing the truncation errors ET1, ET2cannot be disregarded since the differences between the respective transfer functions, i.e., H1a-H1dand H2a-H2d, are non-zero. However, equation 19 within the signal bandwidth of interest can be approximated by equation 21 if we can achieve the following relationships between the quantization error εQand truncation errors ET1, ET2:
EQ>>HT1*HT2*(H1d−H1a)*ET1(24)
EQ>>HT2*(H2d−H2a)*ET2(25)

Outside the signal bandwidth of interest, filters can be used to reduce errors in the digital domain.

For example, mismatches between the analog14a,14band digital114a,114bintegrators can result from mismatches among the capacitors used to establish the integrators signal gain, as well as finite signal gains within the operational amplifiers which can cause integrator leakage.

Referring back to equation 22, the mismatches between the analog and digital integrator transfer functions can be expressed as follows:
H1d−H1a=E1*H1a&H2d−H2a=E2*H2a(26)

Substituting these into equation 19 produces the following expressions:
y′≈x+HT1*E1*ET1+2*(1−z−1)*HT2*E2*ET2+2*(1−z−1)2*EQ−2*(1−z−1)3*(1+z−2)*(1+z−1)*ET(27)
y′≈x+HT1+*E1*ET1+2*(1−z−1)*HT2*E2*ET2+2*(1−z−1)2*EQ(28)

Focusing on the signal bandwidth of interest, i.e.:
y′x+2*(1−z−1)2*EQ(29)

From these expressions, the following general relationships can be seen:
HT1=(1−z−1)n, n≧2  (33)
HT2=(1−z−1)m, m≧1  (34)

Accordingly, for an Nth order sigma-delta modulator, the orders of noise shaping for the truncation filters should be as follows:
HT1:≧N,HT2:≧N−1,HT3:≧N−2, . . .  (35)

As should be readily understood, as depicted inFIGS. 6 and 6A, the digital circuitry128bproviding truncation for the second feedback loop (as well as any similar such circuitry further downstream for additional feedback loops in the case of higher order SDMs) includes an adder for combining the truncated signal with the upstream digital integrated signal115a(e.g., differentially summing in which the upstream digital integrated signal115ais subtracted from the truncated signal).

Referring toFIG. 7, a sigma-delta modulator60bin accordance with another embodiment of the presently claimed invention provides for effectively extending the dynamic range by compensating for saturation errors. As is well known, noise includes quantization noise, truncation noise and noise from other non-ideal operating characteristics, and when added to the maximum expected signal can result in saturation. Further, such saturation errors can be inconsistent since every integrator will have an at least slightly different maximum signal range. Accordingly, the truncation circuits128as,128bsin the feedback loops also include saturation protection circuitry. These circuits128as,128bsprovide truncation, i.e., removal of one or more of the least significant bits (LSBs), plus saturation protection by removing one or more of the most significant bits (MSBs). The associated truncation ET1, ET2and saturation ES1, ES2errors are summed and integrated before being carried over to the next feedback stage for compensation, as shown.

Referring toFIGS. 8A,8B and8C, using the first truncation and saturation protection circuit128asas an example, truncation and saturation protection can be implemented as shown. As shown inFIG. 8A, similar to the circuitry ofFIG. 5B, the bit splitter circuit152includes a truncation circuit152a(to truncate one or more LSBs) and adder152bplus a limiter (to truncate one or more MSBs) interconnected substantially as shown. The M1-bit truncated output signal y1is differentially summed with the M-bit input signal y′119to produce the truncation and saturation error ET+ES153b. The circuits128asa,128asbofFIGS. 8B and 8Coperate in a manner similar to those as described above forFIGS. 4 and 5A, but with the additional operation of saturation protection by the removal of one or more MSBs, as discussed above.