SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a circuit board, at least one semiconductor chip mounted on the circuit board, a spacer disposed on the at least one semiconductor chip, the spacer having a thickness of about 5 μm to about 110 μm, and an upper surface of the spacer exposed externally; and an encapsulant covering the at least one semiconductor chip. The semiconductor package may have a small thickness and may prevent incomplete molding that causes exposure of an active surface of a semiconductor chip.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the inventive concepts will be described in detail by explaining example embodiments with reference to the attached drawings. The inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concepts to one of ordinary skill in the art. In the drawings, like reference numerals denote like elements. Furthermore, various elements and regions are schematically illustrated. Accordingly, the inventive concepts are not limited to relative sizes or distances in the drawings.

Unless defined differently, all terms used in the description including technical and scientific terms have the same meaning as generally understood by one of ordinary skill in the art. Terms as defined in a commonly used dictionary should be construed as having the same meaning as in an associated technical context, and unless defined in the description, the terms are not ideally or excessively construed as having formal meaning.

As used herein, the team “and/or” includes any and all combinations of one or more of the associated listed items.

FIGS. 1A and 1Bare a perspective view and a cross-sectional view of a semiconductor package100according to an example embodiment, respectively.FIG. 1Bis a cross-sectional view taken along the line B-B′ ofFIG. 1A.

Referring toFIGS. 1A and 1B, the semiconductor package100may include at least one semiconductor chip110mounted on a circuit board101, and a spacer140disposed on the semiconductor chip110. The semiconductor chip110may be electrically connected to the circuit board101via connectors120, and may be encapsulated with an encapsulant150to protect the package100from, for example, external impact, temperature, and moisture.

The circuit board101may be an insulating substrate, on which conductive circuits are formed, for example, a rigid printed circuit board (RPCB), a flexible printed circuit board (FPCB), or a tape substrate.

The semiconductor chip110may be one semiconductor chip or may include a plurality of stacked semiconductor chips, for example, first through fourth semiconductor chips110athrough110d,as illustrated inFIG. 1B. Although the first through fourth semiconductor chips110athrough110dare vertically aligned inFIG. 1B, in some cases, the first through fourth semiconductor chips110athrough110dmay be stacked offset.

The semiconductor chip110may be connected to the circuit board101via the connectors120. The connectors120may be any means for electrically connecting two connection terminals, and may be, but not limited to, bonding wires as illustrated inFIG. 1B, solder balls, or solder bumps. In the semiconductor package100, bonding wires, solder balls, solder bumps, or a combination thereof may be used as the connectors120. For example, where the first semiconductor chip110athat is a top semiconductor chip is connected to the circuit board101via bonding wires, the bonding wires may extend from the first semiconductor chip110aupward to a desired (or alternatively, predetermined) height and then may extend downward to be bonded to a plurality of bonding pads132on the circuit board101.

The spacer140may be formed on the semiconductor chip110. The spacer140may be disposed at the center of an upper surface of the semiconductor chip110. For example, the spacer140may be disposed before a molding process of the semiconductor chip110. Thus, during the molding process, a burden to flow the encapsulant150to reach the center of the upper surface of the semiconductor chip110in a mold for the molding process may be substantially relieved. For example, at a given feeding pressure, the encapsulant does not have to be fed to reach the center of the upper surface of the semiconductor chip110because the encapsulation completes when the encapsulant reaches side surfaces of the spacer140. Detailed descriptions thereof will be provided below.

The spacer140may be formed of, for example, silicon, metal, or plastic. For example, the spacer140may be formed of epoxy resin. Also, the spacer140may be formed of a single material, or a composite of silicon, metal, and/or plastic. If the spacer140is formed of a composite of two or more different materials, the materials may be stacked on one another or the material may be formed such that powder of one material is dispersed in a matrix of the other material.

A thickness d of the spacer140may be, for example, about 5 μm to about 110 μm Alternatively, the thickness d of the spacer140may be, for example, about 20 μm all to about 70 μm.

The spacer140is not limited to a certain size. For example, the size of the spacer140may be determined such that a horizontal distance w between an edge of the spacer140and an edge of the first semiconductor chip110aon which the spacer140is disposed is equal to or less than about 200 μm. Alternatively, the size of the spacer140may be determined such that the horizontal distance w is, for example, equal to or less than about 150 μm, or equal to or less than about 100 μm.

A bonding layer for bonding the spacer140onto the semiconductor chip110may be further formed between the spacer140and the semiconductor chip110. The bonding layer may be formed of, for example, a non-conductive film (NCF), an anisotropic conductive film (ACF), an ultraviolet (UV)-sensitive film, an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, an ultrasound-curable adhesive, or non-conductive paste (NCP).

The encapsulant150may be formed of a polymer such as resin. For example, the encapsulant150may be, but not limited to, an epoxy molding compound (EMC). The encapsulant150may encapsulate lateral and upper surfaces of the semiconductor chip110.

Also, a level of an upper surface of the encapsulant150may be substantially the same as the level of an upper surface of the spacer140. Here, the fact that the upper surface of the encapsulant150and the upper surface of the spacer140have substantially the same level means that the difference between the highest level on the upper surface of the encapsulant150and the highest level on the upper surface of the spacer140is within about 2 μm.

The bonding pads132on an upper surface of the circuit board101may be electrically connected via circuits to a plurality of bump pads134on a lower surface of the circuit board101. The bump pads134may be connected to solder bumps160, which may be connected to, for example, an external device.

FIG. 2is a flowchart of a method of manufacturing the semiconductor package100illustrated inFIGS. 1A and 1B, according to an example embodiment.FIGS. 3A through 3Care sequential cross-sectional views for describing a method of manufacturing the semiconductor package100illustrated inFIGS. 1A and 1B, according to an example embodiment.

Referring toFIGS. 2 and 3A, the semiconductor chip110is mounted on the circuit board101(S110). The semiconductor chip110may be mounted on the circuit board101by using various methods, for example, a method using a bonding member such as an NCF, an ACF, a UV-sensitive film, an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, an ultrasound-curable adhesive, or NCP.

The semiconductor chip110may be a single semiconductor chip or may include the first through fourth semiconductor chips110athrough110das illustrated inFIG. 3A. Also, at least one of the first through fourth semiconductor chips110athrough110dmay be mounted in the form of a flip-chip of which an active surface faces downward.

The circuit board101may include a metal pattern and vias for interlayer connection. Here, the metal pattern may include a single layer or a plurality of layers. The circuit board101may be an RPCB, an FPCB, or a tape substrate.

The bonding pads132electrically connected to the metal pattern may be formed on the upper surface of the circuit board101.

The bump pads134electrically connected to the bonding pads132may be formed on the lower surface of the circuit board101. The bump pads134may be electrically connected to an external device via a plurality of connection terminals (e.g., the solder bumps160illustrated inFIG. 1B). The external device may be, but not limited to, for example, another substrate such as a main board.

Referring toFIGS. 2 and 3B, the semiconductor chip110is electrically connected to the circuit board101via the connectors120(S120). Here, although bonding wires are illustrated as the connectors120inFIG. 3B, the connectors120are not limited thereto. For example, the semiconductor chip110may be connected to the circuit board101via through silicon vias (TSV). Detailed descriptions thereof will be provided below.

After that, the spacer140may be disposed and bonded onto the semiconductor chip110(S130). Although it has been described that the spacer140is bonded onto the semiconductor chip110after the semiconductor chip110has been electrically connected to the circuit board101inFIG. 2, it is not necessary to do so. However, the process of bonding the spacer140onto the semiconductor chip110is not limited thereto as long as the process is performed before an encapsulation process (S140). For example, the spacer140may be bonded onto the semiconductor chip110before the semiconductor chip110is electrically connected to the circuit board101. Alternatively, the spacer140may be bonded onto the semiconductor chip110and then the semiconductor chip110may be mounted on the circuit board101.

In order to bond the spacer140onto the semiconductor chip110, a bonding layer142may be further formed between the spacer140and the semiconductor chip110. The bonding layer142may be formed of, for example, an NCF, an ACF, a UV-sensitive film, an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, an ultrasound-curable adhesive, or NCP. As described above referring toFIGS. 1A and 1B, the thickness d of the spacer140may be, for example, about 5 μm to about 110 μm. Alternatively, the thickness d of the spacer140may be, for example, about 20 μm to about 70 μm.

Referring toFIGS. 2 and 3C, the encapsulant150encapsulates the side surfaces and an exposed portion of the upper surface of the semiconductor chip110(S140). For this, the circuit board101on which the semiconductor chip110is mounted may be disposed in an encapsulation mold10. For example, the encapsulation mold10may include an upper mold10aand a lower mold10b,and the upper mold10amay be configured to closely contact the upper surface of the spacer140.

In order to encapsulate the semiconductor chip110, a polymer resin such as an EMC may be injected into the encapsulation mold10. Although the encapsulation mold10accommodates only one semiconductor chip110including a single chip or a plurality of stacked chips according toFIG. 3C, a plurality of semiconductor chips110may be aligned in a horizontal direction in the encapsulation mold10. In this case, a process of individualizing a plurality of semiconductor packages after they are completely molded may be further included.

As described above, because the upper mold10aclosely contacts the upper surface of the spacer140, although a pressure applied to the encapsulant150in a molding process is not considerably high, the encapsulant150may sufficiently cover the upper surface of the semiconductor chip110in cooperation with the spacer140. If the spacer140does not exist, the encapsulant150has to solely cover the entire upper surface of the semiconductor chip110. For example, the encapsulant150has to flow to the center of the upper surface of the semiconductor chip110, and thus a considerably high pressure is required to apply the encapsulant150. For example, if a distance between the upper mold10aand the semiconductor chip110is very small, for example, equal to or less than about 200 μm, due to a viscosity and a surface tension of the encapsulant150, considerably high pressure may be required to be applied to the encapsulant150so that the encapsulant150uniformly covers the entire upper surface of the semiconductor chip110.

Where a plurality of semiconductor chips110are aligned in a horizontal direction in the encapsulation mold10, near an inlet of the encapsulant150, the encapsulant150has a relative low viscosity and thus may easily and sufficiently cover the upper surface of the semiconductor chip110. However, because the viscosity of the encapsulant150increases as time passes, e.g., as the encapsulant progresses in to the mold10, the entire upper surface of the semiconductor chip110that is placed away from the inlet of the encapsulant150may not be easily and/or uniformly covered by the encapsulant150. By providing the spacer140, the encapsulant150may easily cover the entire upper surface of the semiconductor chip110in cooperation with the spacer140.

In the event that the horizontal distance w between an edge of the semiconductor chip110and an edge of the spacer140is excessively large, an excessive pressure may be required to allow the encapsulant150to flow to reach the edge of the spacer140. In this case, the encapsulant150may be hardened during the flow and fail to reach the spacer140in a horizontal direction. As a result, the upper surface of the semiconductor chip110may be partially exposed. Accordingly, the horizontal distance w between an edge of the semiconductor chip110and an edge of the spacer140needs to be appropriate, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

The upper mold10amay tightly contact the entire upper surface of the spacer140or, in some cases, may not fully contact a partial region of the upper surface of the spacer140. In the event that the upper mold does not fully contact the partial region of the upper surface of the spacer140, the encapsulant150may flow between the upper mold10aand the spacer140, and may be hardened and may remain as flash on the upper surface of the spacer.FIG. 4is a perspective view of the semiconductor package100illustrated inFIG. 3C, when flash155remains on the upper surface of the spacer140.

FIG. 5Ais a cross-sectional view of a semiconductor package100aaccording to an example embodiment.FIGS. 5B and 5Care conceptual cross-sectional views for describing a method of forming a spacer140ato be used in the semiconductor package100aillustrated inFIG. 5A. Except for the spacer140a,the semiconductor package100aillustrated inFIG. 5Ais the same as the semiconductor package100illustrated inFIGS. 1B, and3A through3C, and thus detailed descriptions of elements other than the spacer140aare not provided here.

Referring toFIG. 5A, as inFIG. 1B, the spacer140ais formed on the semiconductor chip110. The spacer140amay have a transverse width that varies in a direction away from the semiconductor chip110.

In more detail, the spacer140amay have a transverse width that decreases in a direction away from the semiconductor chip110. For example, side surfaces of the spacer140amay be inclined by a certain angle with respect to the upper surface of the semiconductor chip110. For example, the side surfaces of the spacer140amay be inclined inward in a direction away from the semiconductor chip110.

Furthermore, although the side surfaces of the spacer140aare flat inFIG. 5A, the side surfaces of the spacer140ado not have to be flat and may be curved. For example, the side surfaces of the spacer140amay be convex outward. Also, although portions where upper and side surfaces of the spacer140ameet each other are cornered inFIG. 5A, the portions may be curved.

A method of forming the above-described spacer140ais not limited to a particular method. For example, as illustrated inFIG. 5B, the spacer140amay be formed by punching a flat panel148of a material. For example, the spacer140ahaving a desired size may be obtained by fixing the flat panel148with dies22, which includes upper and lower dies22aand22b,and then lowering a punch24along side surfaces of the dies22to punch the flat panel148.

The side surfaces of the spacer140amay not be vertically straight, but may be inclined as illustrated inFIG. 5Cdue to shear stress applied to the flat panel148when it is punched by the punch24. In order to form the spacer140ain large quantities, for example, a plurality of stacked flat panels148may be fixed between the upper and lower dies22aand22band punched together.

However, a forming process of the spacer140ais not limited to the above method and may be formed by using other methods.

According to a process of forming the spacer140a,at least a portion of the side surfaces of the spacer140amay be roughened. For example, at least a portion of the side surfaces of the spacer140amay be formed rougher than the upper surface of the spacer140a.For example, burrs may be formed on the side surfaces of the spacer140a.

As represented by T inFIG. 5D, an edge of a spacer140a′ may be slightly bent downward. For example, at least a portion of the edge of the spacer140a′ may be slightly bent toward the semiconductor chip110. This deformation may be intended or may be caused by the above-described shear stress.

When the transverse width of a spacer varies in a direction away from the semiconductor chip110, the edge of the spacer is defined as the edge position of a surface of the spacer, where the spacer contacts the semiconductor chip110. For example, referring to the spacer140aillustrated inFIG. 5A, because the edge of a lower surface of the spacer140a,which contacts the semiconductor chip110, is defined as the edge of the spacer140a,a horizontal distance between the edge of the spacer140aand the edge of the semiconductor chip110may be represented by w as denoted inFIG. 5A. The horizontal distance w between the edge of the semiconductor chip110and the edge of the spacer140ainFIG. 5Amay be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

FIG. 6Ais a cross-sectional view of a semiconductor package100baccording to an example embodiment.FIGS. 6B and 6Care conceptual cross-sectional views for describing a method of forming a spacer140bto be used in the semiconductor package100billustrated inFIG. 6A. Except for the spacer140b,the semiconductor package100billustrated inFIG. 6Ais the same as the semiconductor package100illustrated inFIGS. 1B, and3A through3C, and thus detailed descriptions of elements other than the spacer140bare not provided here.

Referring toFIG. 6A, as inFIG. 1B, the spacer140bis formed on the semiconductor chip110. The spacer140bmay be stepped or may have a transverse width that varies in a direction away from the semiconductor chip110. Although the spacer140bis stepped once inFIG. 6A, the spacer140bmay be stepped a plurality of times.

In more detail, the spacer140bmay have a certain width constantly maintained to a predetermined thickness in a direction away from the semiconductor chip110. Also, the spacer140bmay have a width less than the certain width from the predetermined thickness to an upper surface of the spacer140b.

The edge of the spacer140b,for a purpose of defining the horizontal distance w between the edge of the spacer140band the edge of the semiconductor chip110, may be defined as the edge of a lower surface of the spacer140bwhich contacts the semiconductor chip110. The horizontal distance w between the edge of the semiconductor chip110and the edge of the spacer140binFIG. 6Amay be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

A method of forming the above-described spacer140bis not limited to a particular method. For example, as illustrated inFIG. 6B, the flat panel148of a material for forming the spacer140bmay be sawn to a desired (or alternatively, predetermined) first depth by using a first blade32having a first width t1. As a result, a recess having the first width t1may be foamed in the flat panel148.

Further, as illustrated inFIG. 6C, the flat panel148may be sawn at the center of the recess having the first width t1by using a second blade34having a second width t2and thus the flat panel148may be separated to form the spacers140b.However, the spacer140bis not limited to the above method and may be formed by using other methods.

Like the spacer140a,according to a process of forming the spacer140b,at least a portion of side surfaces of the spacer140bmay be roughened or may have burrs. For example, at least a portion of the side surfaces of the spacer140bmay be formed rougher than the upper surface of the spacer140b.

FIG. 7Ais a cross-sectional view of a semiconductor package100caccording to an example embodiment.FIGS. 7B and 7Care conceptual cross-sectional views for describing a method of forming a spacer140cto be used in the semiconductor package100cillustrated inFIG. 7A. Except for the spacer140c,the semiconductor package100cillustrated inFIG. 7Ais the same as the semiconductor package100illustrated inFIGS. 1B, and3A through3C, and thus detailed descriptions of elements other than the spacer140care not provided here.

Referring toFIG. 7A, as inFIG. 1B, the spacer140cis formed on the semiconductor chip110. The spacer140cmay have a first portion where a transverse width of the spacer140cis reduced in a direction away from the semiconductor chip110to a first thickness. The spacer140cmay also have a second portion above the first portion where a transverse width of the spacer140cis increased in a direction away from the semiconductor chip110. For example, at least a portion of the spacer140cmay be recessed inward. At least a portion of the spacer140cmay be curved and concave inward.

The edge of the spacer140c,for a purpose of defining the horizontal distance w between the edge of the spacer140cand the edge of the semiconductor chip110, may be defined as the edge of a lower surface of the spacer140c,which contacts the semiconductor chip110. The horizontal distance w between the edge of the semiconductor chip110and the edge of the spacer140cinFIG. 7Amay be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

A method of forming the above-described spacer140cis not limited to a particular method. Referring toFIG. 7B, etching masks42may be symmetrically formed on upper and lower surfaces of the flat panel148of a material to form the spacer140c.The etching masks42may be photo-lithographically formed by using a photoresist material, or may be formed by using a tape bonding method. A material forming the etching masks42may be a material having an etch selectivity against the flat panel148with respect to an etchant to be applied later, and is not limited to a particular material.

Further, referring toFIG. 7C, the etchant may be applied to the flat panel148onto which the etching masks42are bonded. The etchant may be applied by using a wet etching method. In the event that the flat panel148may be immersed in the wet etchant, the flat panel148may be etched and individualized into the spacers140cand side surfaces of the spacer140cmay be curved and concaved inward.

Thereafter, the spacer140cmay be obtained by removing the etching masks42formed on upper and lower surfaces of the spacer140c.However, a method of forming the spacer140cis not limited to the above method and may be formed by using other methods.

Like the spacer140a,according to a process of forming the spacer140c,at least a portion of the side surfaces of the spacer140cmay be formed to be relatively rough or may have burrs. For example, at least a portion of the side surfaces of the spacer140cmay be formed to be relatively roughen than the upper surface of the spacer140c.

FIGS. 8A through 8Care plan views of semiconductor packages100d,100e,and100faccording to an example embodiments.

At least a portion of the spacer140dmay protrude from the edge of the semiconductor chip110. For example, a horizontal distance w1between the edge of the semiconductor chip110and the edge of the spacer140din a direction in which the spacer140ddoes not protrude may be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm, as described above referring toFIG. 1B. A horizontal distance w2between the edge of the semiconductor chip110and the edge of the spacer140din a direction in which the spacer140dprotrudes may also be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm, to prevent an excessive side effect due to overhang.

A plurality of bonding pads112may be formed along only one edge of the semiconductor chip110. For example, the spacer140emay protrude from the edge of the semiconductor chip110, along which the bonding pads112are not formed. For example, as described above referring toFIG. 8A, each of the horizontal distances w1and w2between the edge of the semiconductor chip110and the edge of the spacer140emay be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

The entire edge of the spacer140fmay protrude from the edge of the semiconductor chip110. For example, to ensure a space where the connectors120connect the bonding pads112formed on an active surface of the semiconductor chip110to the bonding pads132formed on the circuit board101, the spacer140fmay include an opening144. Although the bonding pads112are formed along only one edge of the semiconductor chip110inFIG. 8C, it would be understood by one of ordinary skill in the art that the bonding pads112may be additionally formed along an another edge of the semiconductor chip110, and thus the spacer140fmay include another opening.

For example, an area of a lower surface of the spacer140fmay be greater than the area of the upper surface of the semiconductor chip110that is an individual semiconductor die on which the spacer140fis disposed.

FIGS. 9A through 9Dare cross-sectional views of semiconductor packages according to example embodiments.

Referring toFIG. 9A, the first and second semiconductor chips110aand110bmay be mounted on the circuit board101. For example, the second semiconductor chip110bmay be directly mounted on the circuit board101in the form of a flip-chip. The second semiconductor chip110bmay be connected via a plurality of solder bumps110b-1to a plurality of bump pads136formed on the circuit board101.

The first semiconductor chip110amay be provided on the second semiconductor chip110b.The first semiconductor chip110amay be bonded onto the second semiconductor chip110by using, for example, a bonding member114, such that an active surface of the first semiconductor chip110afaces upward. The bonding member114may be, for example, an NCF, an ACF, a UV-sensitive film, an instant adhesive, a thermosetting adhesive, a laser-curable adhesive, an ultrasound-curable adhesive, or NCP.

The bonding pads112may be formed on the active surface of the first semiconductor chip110a,and may be electrically connected via the connectors120to the bonding pads132on the circuit board101. The connectors120may be, for example, bonding wires.

The spacer140may be formed on the first semiconductor chip110a.The semiconductor chip110may be encapsulated with the encapsulant150. For example, the upper surface of the spacer140may be exposed externally. Also, a level of the upper surface of the spacer140may be substantially the same as the level of the upper surface of the encapsulant150.

Referring toFIG. 9B, elements other than the first through third semiconductor chips110athrough110cmounted on the circuit board101are the same as those illustrated inFIG. 9A, and thus detailed descriptions thereof are not provided here.

The semiconductor chip110may include a plurality of semiconductor chips stacked in the form of chip-on-chip (CoC). Referring toFIG. 9B, the semiconductor chip110may include the first through third semiconductor chips110athrough110c.The second and third semiconductor chips110band110cmay be connected to each other in the form of CoC via the solder bumps110b-1and a plurality of bump pads116. An underfill118may be further formed between the second and third semiconductor chips110band110c.

Referring toFIG. 9C, elements other than first through seventh semiconductor chips110athrough110gmounted on the circuit board101are the same as those illustrated inFIG. 9A, and thus detailed descriptions thereof are not provided here.

The first through seventh semiconductor chips110athrough110gmay be stacked on one another and may be offset from each other by a predetermined distance to expose the bonding pads112. For example, an offset direction may be only one direction or may be two opposite directions as illustrated inFIG. 9C. However, the offset direction is not limited thereto and may include two or more arbitrary directions.

For example, each of the horizontal distances w1and w2between the edge of the spacer140and the edge of the first semiconductor chip110a,which is a top semiconductor chip may be, for example, equal to or less than about 500 μm, equal to or less than about 200 μm, or equal to or less than about 150 μm.

If the active surface of the first semiconductor chip110a,which is a top semiconductor chip, faces upward and is connected to the circuit board101via bonding wires as illustrated inFIGS. 9A through 9C, due to loops of the bonding wires, the thickness of the spacer140may not be easily reduced.

FIG. 9Dis a cross-sectional view showing an example using TSVs. Although the active surface of the first semiconductor chip110athat is a top semiconductor chip faces upward, it may be electrically connected via TSVs to the second through fifth semiconductor chips110bthrough110eunder the first semiconductor chip110a.Because loops of bonding wires do not need to be formed, the spacer140may be formed to have an extremely small thickness.

As another example of achieving a very small thickness of the spacer140, side interconnection may be used as illustrated inFIG. 10.FIG. 10is a perspective view of the first through sixth semiconductor chips110athrough110fstacked and electrically connected to each other by using side interconnections130, before being encapsulated with the encapsulant150, according to an example embodiment.

Referring toFIG. 10, the first through sixth semiconductor chips110athrough110fare stacked and mounted on the circuit board101. Among the first through sixth semiconductor chips110athrough110f,the active surface of the first semiconductor chip110a,which is a top semiconductor chip, may face upward.

On an upper surface of the first semiconductor chip110a,which is a top semiconductor chip, connection terminals116electrically connected to semiconductor devices in the first semiconductor chip110amay be formed along an edge of the first semiconductor chip110a.Also, on an upper and/or lower surface of each of the second through sixth semiconductor chips110bthrough110f,the connection terminals116electrically connected to semiconductor devices in each of the second through sixth semiconductor chips110bthrough110fmay be formed along an edge of each of the second through sixth semiconductor chips110bthrough110f.The connection terminals116of the first through sixth semiconductor chips110athrough110fmay be electrically connected to each other by using the side interconnections130.

Furthermore, the side interconnections130may be electrically connected to the bonding pad132formed on the upper surface of the circuit board101. The bonding pad132formed on the upper surface of the circuit board101may be electrically connected to additional connection terminals formed on the lower surface of the circuit board101.

Because the first semiconductor chip110a,which is a top semiconductor chip, may be electrically connected to the second through sixth semiconductor chips110bthrough110fand/or the circuit board101without using bonding wires inFIG. 10, the spacer140may have an extremely small thickness.

InFIG. 9Dand/orFIG. 10, the thickness of the spacer140may be about 5 μm to about 30 μm, or about 5 μm to about 20 μm.

FIG. 11is a block diagram of a memory card200including the above semiconductor package, according to an example embodiment.

The memory card200includes a memory controller220for generating command and address (C/A) signals, and a memory module210such as a flash memory including one or a plurality of flash memory devices. The memory controller220includes a host interface223for transmitting or receiving the C/A signals to or from a host, and a memory interface225for transmitting or receiving the C/A signals to or from the memory module210. The host interface223, a controller224, and the memory interface225communicate via a common bus260with a controller memory221, e.g., static random-access memory (SRAM), and a processor222, e.g., a central processing unit (CPU).

The memory module210receives the C/A signals from the memory controller220, and, as a response, stores or searches for data in at least one of memory devices of the memory module210. Each memory device includes a plurality of addressable memory cells and a decoder for receiving the C/A signals and generating row and column signals to access at least one of the addressable memory cells in programming and read operations.

At least one of the components of the memory card200, e.g., the electronic devices (221,222,223,224, and225) included in the memory controller220and the memory module210, may include a semiconductor package according to an example embodiment.

FIG. 12is a conceptual view of a system300according to an example embodiment.

Referring toFIG. 12, the system300may include a control unit321, an input/output (I/O) unit322, a memory unit323, and an interface unit324.

The system300may be a mobile system or a system for transmitting or receiving information. The mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card.

The control unit321may execute a program and may control the system300. The control unit321may be, for example, a microprocessor, a digital signal processor, a micro controller, or the like. The control unit321may include a semiconductor package according to an example embodiment.

The I/O unit322may be used to input or output data of the system300. The system300may be connected to an external apparatus such as a personal computer (PC) or a network and may exchange data with the external apparatus by using the I/O unit322. The I/O unit322may be, for example, a keypad, a keyboard, or a display.

The memory unit323may store codes and/or data for operating the control unit321, and/or may store data processed by the control unit321. The memory unit323may include a semiconductor package according to an example embodiment.

The interface unit324may function as a data path between the system300and an external apparatus. The control unit321, the I/O unit322, the memory unit323, and the interface unit324may communicate with each other via a bus325. For example, the system300may be used in a mobile phone, an MP3player, a navigator, a portable multimedia player (PMP), a solid state disk (SSD), or a household appliance.