PoDL system with active dV/dt and dI/dt control

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

FIELD OF THE INVENTION

This invention relates to Power over Data Line (PoDL) systems, where DC power is transmitted over a pair of differential data lines. The invention more particularly relates to techniques for actively limiting the power signal's dV/dt coupled to the wire pair, which will reduce the passive filtering requirements at the PHY terminals.

BACKGROUND

In PoDL, DC power from Power Sourcing Equipment (PSE) is transmitted over a single twisted wire pair. The same twisted wire pair also transmits/receives differential data signals. In this way, the need for providing any external power source for the Powered Devices (PDs) can be eliminated. The standards for PoDL are set out in IEEE 802.3 and are well-known.

A conventional PoDL system uses a coupling network to couple the DC power and AC data to the twisted wire pair at the output of the PSE and uses an identical network to decouple the DC power and AC data from the twisted wire pair at the PD.

FIG. 1illustrates conventional coupling/decoupling networks between a PSE10and a PD12in an Ethernet PoDL system. The PSE10includes a DC voltage source13and may include a differential data transceiver. The differential data may also be generated by any other circuit. The differential data is applied to differential terminals of the physical layer (PHY)14for application to the twisted wire pair16. The data portion of the PoDL system is not relevant to the present invention so is not described in detail.

The PD12includes a differential data portion that receives data from the PHY18terminals and processes the data accordingly. Such a data processing portion is not relevant to the invention. The PD load that receives the DC voltage and the data is represented by a resistor RPD. A capacitor CPDhelps smooth the voltage into the PD load. A DC-DC converter may be used in the PD to convert the received PoDL voltage to a target voltage for the PD load.

In the example ofFIG. 1, DC power is delivered from the PSE10to the PD12through the single twisted wire pair16via a coupling network that conducts DC (or low frequency current), for power, between the DC voltage source13and the wire pair16, while simultaneously blocking the differential AC data (or high frequency current) from the DC voltage source13. Similarly, the PD12uses a decoupling network that decouples the transmitted DC voltage for powering the PD load, while conducting only the PHYs' AC data to data terminals in the PD12. The ability of the coupling/decoupling networks to block the PHYs' AC data over a very broad range of frequencies is a key requirement for PoDL Ethernet applications where the data rates may vary from 100 Mbps to 1 Gbps. In the example ofFIG. 1, the capacitors C1-C4are intended to block DC in the data path, while the inductors L1-L4are intended to block AC in the power path.

InFIG. 1, inductors L1-L4are used to couple/decouple the DC flowing between the PSE10voltage source13and the PD12load to/from the wires16. The inductors L1-L4are AC blocking devices whose impedance is proportional to frequency. The constant of proportionality is referred to as the inductance L. The ability of a single inductor to impede AC over a broad range of frequencies depends on the magnitude of inductance, the inductor's ability to conduct DC current without losing its inductance, and its parasitic capacitance.

It is desirable to make the inductors L1-L4the minimum size necessary to pass the power signal but block the AC data signals. Similarly, it is desirable to make the capacitors C1-C4the minimum size necessary to block the power signal but pass the AC data signals. However, dV/dt noise in the power signal must also be blocked, and such dV/dt noise is fairly unpredictable. The dV/dt noise may affect data integrity. Therefore, the inductors L1-L4and capacitors C1-C4are typically larger than required to adequately pass or block the DC voltage and pass or block the AC data signals. Noise in the power signal may arise while the PSE being turned on, or from other equipment on the power supply bus, or from other sources.

Similarly, a rapid change in the PD load current (dl/dt) affects the voltage delivered by the PSE, where a high positive dl/dt will cause a rapid temporary decrease in the voltage, and where a high negative dl/dt will cause a rapid temporary increase in the voltage. Such dV/dt changes in voltage may affect data integrity.

Thus, what is needed in the field of PoDL is an improved network that combines or separates the power signal and the wide bandwidth AC data while limiting noise in the power signal caused by dV/dt or dI/dt.

SUMMARY

Various circuits, in either the PSE or the PD or both, are described that limit the time rate of change of the voltage in the power signal to reduce the possibility of adverse effects of noise in the power signal. The circuits are separate from the PSE's or PD's passive LC coupling/decoupling network. This eases the requirements for the inductors and capacitors in the PSE and PD coupling/decoupling networks, enabling much smaller passive components to be used (which are typically discrete components), resulting in reduced sizes and costs of the networks.

Accordingly, a PSE and/or a PD in a 1-Pair PoDL system is described that minimizes PHY transients, such as resulting from PSE start-up and/or PD load current changes, by actively controlling the time rate of change of the power signal. A PSE/PD with this feature results in a circuit that requires substantially smaller LC filters in order to deliver an equivalent level of performance.

Elements that are the same or equivalent are labeled with the same numeral.

DETAILED DESCRIPTION

FIG. 2illustrates the power generating portion of a PSE20in a PoDL system. The PD (not shown) may be similar to the conventional PD12inFIG. 1, although the filter requirements in the PD's decoupling network of the PD are eased by the present invention. The differential data portion of the PoDL system is not relevant to the present invention and may be conventional.

An analysis of the PHYs' terminal voltage response to a change in the PSE voltage dVPsE/dt can assume one of three forms depending on the circuit's damping ratio: under-damped, critically damped, or over-damped, but at steady state it can be shown that:

VPHY=ⅆVPSEⅆt×50⁢⁢Ω×CPHY2,
where the impedance of the PHY is assumed to be 2×50Ω, and CPHYis the capacitance of the PHY's DC blocking capacitors C1-C4.

Hence a slew rate limitation on dVPSE/dt is required in order to constrain the magnitude of voltage perturbations at either PHY.

For the PSE, various circuit topologies may be used to limit the dVPSE/dt as needed in order to ensure that the magnitude of the resulting voltage transients at the PHY terminals are limited.

FIG. 2illustrates circuit architecture in a PSE20where a low-side N-channel MOSFET M3is enhanced with a pull-up current I1by current source22only during start-up of the PSE20, when variations in the power signal voltage occur. During start-up, the switch24is opened to allow the current I1to pull-up the gate of the MOSFET M3to ramp up its conductivity between ground and the bottom terminal of inductor L2. At start-up, the dV/dt at the drain of the MOSFET M3is fairly large so current will be conducted by the capacitor C5between the drain and the gate to reduce the percentage of the current from the current source22applied to the gate. This limits the turn on time of the MOSFET M3. As dV/dt is reduced (and the current into the capacitor C5is reduced), the percentage of the current from the current source22applied to the gate is increased until the MOSFET M3is completely turned on (i.e., VPSE−is approximately ground). Thus, capacitor C5provides feedback from the drain of MOSFET M3to the gate in order to limit dV/dt to less than approximately I(I1)/C5. This technique uses the well-known Miller effect for MOSFETs. The current source22or capacitor C5can be selected to ramp up the conductivity of the MOSFET M3at any desired rate to limit dV/dt. Limiting dV/dt preserves data integrity and eases the filtering requirements of the coupling/decoupling networks.

At the end of the start-up ramp, the switch24remains open and the current I1fully turns on the MOSFET M3to cause it to operate in its linear region. The capacitor C5then acts as an open circuit. The closing of the switch24is for discharging the gate to turn off the MOSFET M3to terminate the power signal to the PD. The added components may be fabricated on the same chip as the PSE controller, since capacitor C5can be small.

Many other types of circuits may be used in place of the limiting circuit ofFIG. 2to limit the time rate of change of VPSE−or VPSE+during start-up or during any other time.

Further, if noise generated by the DC voltage source13is an issue, a voltage regulator may be included to smooth the voltage applied to the VPSE+and VPSE−terminals.

FIGS. 3A and 4show circuits that limit dV/dt at the PD, caused by rapid changes in the PD load current during or after start-up.

For a PD, the relationship between VPD(i.e., PD voltage after filtering by the decoupling network) and VPHY(i.e., voltage across the wire pair) is the same as for the VPSEand VPHY. Ignoring the effects of parasitic resistance, the steady state relationship between dVPD/dt and PD current IPDis:

Hence, the second derivative of the PD current should be constrained in order to limit the magnitude of voltage transients seen at the PHYs' terminals.

Circuit architectures that limit the time rate of change in PD current offer a means of limiting PHY voltage transients.

FIG. 3Aillustrates a circuit architecture where dVPD/dt in the PD30is limited. A PD load (not shown) is connected to the Vout terminals of a DC-DC converter. The converter converts the incoming PoDL voltage to a regulated target voltage (e.g., 5 volts) used by the PD load. Such a load may automatically go into or come out of a standby mode and quickly change its current. Such a rapid change in load current typically causes a rapid change in the PoDL voltage.

InFIG. 3A, an input capacitor CINpartially smoothes the voltage across the VPD+and VPD−lines. A differentiator circuit32detects the voltage across the VPD+and VPD−lines and outputs a voltage proportional to dV/dt. A common differentiator circuit is shown inFIG. 3B. The values of R and C in the circuit ofFIG. 3Bare adjustable to obtain the desired ratio of Vout vs dV/dt.

The output of the differentiator circuit32is differenced with respect to a fixed slew limit reference voltage (a threshold voltage) by a difference amplifier34. The output of the amplifier34is fed into a negative input of a control amplifier36for a voltage-mode buck DC-DC converter, thus limiting the time rate of change of the converter's duty cycle so that the dV/dt of VPD) does not exceed the threshold.

A fixed reference voltage REF is applied to the positive input of the control amplifier36. The output voltage VOUTof the converter is applied to another negative input of the control amplifier36.

The analog output of the control amplifier36acts as a control signal for a pulse width modulator (PWM)38. The PWM38may be conventional and may compare the control voltage to a sawtooth waveform. When the PWM38output is low, the NMOS transistor M1turns off and the PMOS transistor M2turns on to start a new charging cycle for the inductor L5. An output capacitor COUTsmoothes the output of the converter for the PD load. By limiting the change in duty cycle, such as when the PD load comes out of a standby mode to draw more current, there will be a smoother ramp-up of current into the load, at the expense of rapid output voltage regulation, as the converter tries to increase the charging time of the inductor L5. This smoother ramp-up of current dynamically reduces dV/dt across the VPD+and VPD−lines so that the dV/dt of the VPD+and VPD−lines does not exceed a threshold limit. This limits the dI/dt (and d2IPD/dt2) of the PD load current. Thus, changes in the PD load (e.g., going in or out of a standby mode) will have a limited effect on the dV/dt so that the filtering requirements for the decoupling components C3, C4, L3, and L4are reduced.

Many other types of DC-DC converters may be used instead of the buck type shown inFIG. 3A.

As shown inFIG. 4, another approach to limiting d2IPD/dt2involves directly limiting the slew rate of the DC-DC converter's control voltage in order to limit the time rate of change of the PWM duty cycle. Assuming that changes in VPD) are small due to changes in IPD), the relationship between d2IPD/dt2and a buck DC-DC converter's duty cycle is approximately:

Hence, it can be seen that directly limiting the time rate of change of the converter's duty cycle may be sufficient for limiting the magnitude of voltage transients at the PHYs.

FIG. 4illustrates a voltage-mode buck converter where the loop amplifier's control voltage slew rate is limited by a slew rate limited amplifier44in order to limit the time rate of change of the PWM duty cycle, where the duty cycle is proportional to the control voltage. The output voltage VOUTis applied to the negative input of the difference amplifier46, and a fixed reference voltage REF is applied to the positive input. The output of the difference amplifier46represents the deviation of VOUTfrom a target voltage. The slew rate limited amplifier44is a transconductance amplifier that feeds back its output to its negative input terminal, and a slew capacitor CSLEWdetermines the maximum rate of change at the output. The output supplies the control voltage to the PWM38to determine the duty cycle of the DC-DC converter. By controlling the time rate of change of the duty cycle, the dV/dt of the power signal is limited. Thus, data integrity is maintained by the lowered dV/dt in the power signal not being passed by the DC blocking capacitors C3and C4.

Many other types of circuits may be used to limit the slew rate of the duty cycle of the DC-DC converter in the PD to prevent sudden changes in the PD load from resulting in a problematic dV/dt in the power signal.

The terms PSE and PD are used throughout this disclosure to identify equipment that supplies power and equipment that receives the power, and such equipment/devices are not limited to Ethernet equipment/devices unless specified.