Methods and apparatuses for variable length encoding

Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

FIELD OF THE INVENTION

The invention relates to data processing systems using vector processing and Very Long Instruction Word (VLIW) architecture, more particularly to variable length encoding.

BACKGROUND OF THE INVENTION

A frame of image can be represented by a matrix of points referred to as pixels. Each pixel has one or more attributes representing the color associated with the pixel. Video streams are represented by consecutive frames of images. To efficiently store or transport image and video information, it is necessary to use data compression technologies to compress the data representing the attributes of each pixel of each frame of the images.

Various standards have been developed for representing image or video information in compressed formats, which includes Digital Video (DV) formats, MPEG2 or MPEG4 formats from Moving Picture Expert Group, ITU standards (e.g., H.261 or H.263) from International Telecommunication Union, JPEG formats from Joint Photographic Expert Group, and others.

Many standard formats (e.g., DV, MPEG2 or MPEG4, H.261 or H.263) use block based transform coding techniques. For example, 8×8 two-dimensional blocks of pixels are transformed into frequency domain using Forward Discrete Cosine Transformation (FDCT). The transformed coefficients are further quantized and coded using zero run length encoding and variable length encoding.

Zero run length encoding is a technique for converting a list of elements into an equivalent string of run-level pairs, where each non-zero element (level) in the list is associated with a zero run value (run) which represents the number of consecutive elements of zero immediately preceding the corresponding non-zero element in the list. After zero run length encoding, strings of zeros in the list are represented by zero run values associated with non-zero elements. For example, the non-zero elements and their associated zero run values can be interleaved into a new list to represent the original list of elements with strings of zeros.

Variable length coding is a coding technique often used for lossless data compressing. Codes of shorter lengths (e.g., Huffman codewords) are assigned to frequently occurring fixed-length data (or symbols) to achieve data compression. Variable length encoding is widely used in compression video data.

After the Forward Discrete Cosine Transformation and quantization, the frequency coefficients are typically reordered in a zigzag order so that the zero coefficients are grouped together in a list of coefficients, which can be more effectively encoded using a zero run length encoding technique. The energy of a block of pixels representing a block of image is typically concentrated in the lower frequency area. When the coefficients are reordered in a zigzag order, the coefficients for the lower frequencies are located relatively before those for higher frequencies in the reordered list of coefficients. Thus, non-zero coefficients are more likely to concentrate in the front portion of the reordered coefficient list; and zero coefficients are more likely to concentrate in the end portion of the reordered list.

Since compressing images is a computational intensive operation, it is desireable to have highly efficient methods and apparatuses to perform run length encoding and variable length encoding.

SUMMARY OF THE DESCRIPTION

Methods and apparatuses for variable length encoding using a vector processing unit are described here.

In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding including: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

In one example according to this aspect, the plurality of parameters includes a plurality of indices; and to generate concurrently the plurality of first codewords, a plurality of entries are looked up simultaneously from a plurality of look up tables, which are configured from a plurality of look up units to function as the plurality of look up tables. Each of the look up tables utilizes more than one of the plurality of look up units. Each entry of the plurality of entries includes a first bit segment representing a second codeword and a second bit segment representing a bit length of the second codeword.

The plurality of parameters further includes a plurality of sign indicators, each of which indicates the value of a sign bit of a corresponding one of the plurality of symbols. Each of the plurality of entries further includes a third bit segment indicating whether or not to append a sign bit of a corresponding one of the plurality of symbols. A sign bit of a first symbol in the plurality of symbols, which corresponds to a first entry in the plurality of entries, is appended to the second codeword represented by the first bit segment of the first entry when the third bit segment of the first entry indicates to append the sign bit.

The plurality of parameters further includes a plurality of type indicators for the plurality of symbols respectively; and the plurality of parameters and the plurality of entries are combined to generate the plurality of first codewords.

When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a first value, a zero is generated as one of the plurality of first codewords to represent the first symbol.

The plurality of parameters further includes a plurality of third codewords, each of the plurality of third codewords corresponding to one of the plurality of symbols.

When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a second value, one of the plurality of third codewords is used as one of the plurality of first codewords to represent the first symbol.

When one of the plurality of type indicators, which corresponds to a first symbol in the plurality of symbols, has a third value, one of the plurality of first codewords that represents the first symbol is generated from concatenating one of the plurality of third codewords that corresponds to the first symbol and the second codeword represented by the first bit segment of a first entry in the plurality of entries, which entry corresponds to the first symbol.

The present invention includes apparatuses which perform these methods, including data processing systems which perform these methods, and computer readable media which when executed on data processing systems cause the systems to perform these methods.

DETAILED DESCRIPTION

The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of the present invention. However, in certain instances, well known or conventional details are not described in order to avoid obscuring the description of the present invention.

FIG. 1shows a configuration of a computer system, which may be used by the present invention. Note that whileFIG. 1illustrates various components of a computer system, it is not intended to represent any particular architecture or manner of interconnecting the components as such details are not germane to the present invention. It will also be appreciated that network computers and other data processing systems which have fewer components or perhaps more components may also be used with the present invention.

As shown inFIG. 1, the computer system100, which is a form of a data processing system, includes bus110which interconnects PCI (Peripheral Component Interface) interfaces107and109, host interface103, and memory interface105. System core logic140, known as north bridge, interconnects host processor(s)125, host memory127, graphics controller (or display controller)121, and Input/Output (I/O) controller111through host interface103, memory interface105and PCI interfaces107and109respectively. Cache memory123is coupled to host processor(s)125to provide fast access to frequently used data to host processor(s)125. I/O controller111may include additional system logic, known as south bridge, which further provides connectivity to various devices, such as I/O devices112(e.g., mouse, keyboard, modem, or printer), nonvolatile memory114(e.g., hard drive, floppy drive, CD/DVD/CD-R/CD-RW drive), network device113(e.g., Ethernet interface), universal serial bus (USB)115, and FireWire117. Various devices in accordance with USB or IEEE-1394 (FireWire) standards may be attached to USB115or FireWire117; and various display devices may be attached to graphics controller121. FireWire is one of the standards that support very fast communications for peripheral devices and is very suitable for connecting multimedia peripheral devices (e.g., video camcorders) and other high-speed devices (e.g., hard disk drives and printers). WhileFIG. 1shows that the non-volatile memory is a local device coupled directly to the rest of the components in the data processing system, it will be appreciated that the present invention may utilize a non-volatile memory which is remote from the system, such as a network storage device which is coupled to the data processing system through a network interface such as a modem or Ethernet interface.

In one embodiment of the present invention, system core logic140further includes media processor101; and the components of system core logic140are integrated in a single-chip chipset. More details of a media processor integrated in a system core logic chip are described in a co-pending U.S. patent application, Ser. No. 10/038,700 entitled “Bus Controller Chipset” by Joseph P. Bratt, et al, which application is hereby incorporated here by reference. In another embodiment, a single-chip system logic chipset further includes interfaces to other system logics, such as universal serial bus (USB), Ethernet device, etc. However, in other embodiments, media processor101is not integrated in a system core logic chip, or not used (in which case the methods and apparatuses of the present invention can be implemented in at least one host processor).

InFIG. 1, media processor101communicates with host processor(s)125through host interface103. Media processor101processes data autonomously and asynchronously to host processor(s)125. An interrupt mechanism controlled by software is used for the communication between media processor101and host processor(s)125. Alternatively, a media processor may process data as a co-processor and be synchronized to the host processor(s).

Various methods and apparatuses of the present invention can be implemented in either media processors (e.g., media processor101) or in host processors (e.g., host processor125).

It will be apparent from this description that aspects of the present invention may be embodied, at least in part, in software. That is, the techniques may be carried out in a computer system or other data processing system in response to its processor, such as a microprocessor, executing sequences of instructions contained in a memory, such as memory127, non-volatile memory114, cache123, local memory located inside media processor101or a remote storage device. In various embodiments, hardwired circuitry may be used in combination with software instructions to implement the present invention. Thus, the techniques are not limited to any specific combination of hardware circuitry and software nor to any particular source for the instructions executed by the data processing system. In addition, throughout this description, various functions and operations are described as being performed by or caused by software code to simplify description. However, those skilled in the art will recognize what is meant by such expressions is that the functions result from execution of the code by a processor, such as host processor(s)125or media processor101.

FIG. 2shows a Very Long Instruction Word (VLIW) processing engine according to one embodiment of the present invention. The processing engine inFIG. 2can be viewed as a VLIW processor. Media processor101(or a host processor) may contain one or more such VLIW processing engines. In additional to the instructions of the present invention, the processing engine shown inFIG. 2can execute a set of instructions, which, for example, includes a subset of AltiVec instruction sets for PowerPC processors by Motorola.

The processing engine inFIG. 2contains a set of execution units including: integer arithmetic/logical unit (IALU)201, integer shift unit (ISHU)202, floating-point unit (FPU)203, load/store unit (LSU)211, vector permute unit (VPU)205, vector simple integer unit (VSIU)206, vector complex integer unit (VCIU)207, vector look-up table unit (VLUT)208, vector floating-point unit (VFPU)209, and branch/instruction unit (BRU)240. Storage elements in the processing engine include: general purpose register file (GPR)221, vector register file (VR)231, look-up memory (LUM)251(located inside VLUT208), local memory213, instruction cache243, and special purpose registers (SPR)227. An entry in the vector register file is a vector register; and an entry in the general purpose register file is a scalar register. It is useful to note that a processing engine may contain more or less execution units as shown inFIG. 2. More than one functional unit of a kind may be included. For example,. in one embodiment, a processing engine may contain one IALU, two ISHU, one LSU, and one BRU units.

Load/Store Unit (LSU)211is coupled to register selectors223and233for saving data from registers files221and231to local memory213and coupled to destination selectors225and235for loading data from local memory213to register files221and231. Direct Memory Access (DMA) controller215is coupled to local memory213for transporting data between local memory213and host memory (e.g., host memory127inFIG. 1) through input/output (I/O) interface228. Special purpose register (SPR)227is coupled to destination selectors to store results from the execution of certain instructions. I/O interface228provides a communication channel for accessing the fields in the special purpose register by a host processor, for transporting data between the local memory and the host memory, and for loading instructions from the host memory into the instruction cache, etc. Branch/instruction unit240decodes groups of instructions and sends instructions from dispatcher241to various execution units for execution.

Scalar execution units, e.g., IALU, ISHU, or FPU, generally receive data from and store the results of the execution into the general purpose register (GPR) file. Similarly, vector execution units, e.g., VPU, VSIU, VCIU, VLUT, or VFPU, generally receive data from and store the results of the execution into the vector register (VR) file. However, some instructions may cause a vector execution unit to read the general purpose register (GPR) file and set fields in the special purpose register (SPR).

Typically, an integer arithmetic/logic unit (e.g., IALU221) executes simple scalar integer arithmetic (e.g., addition and subtraction, etc.), complex scalar arithmetic instructions (e.g., multiplication and division), and logical operations; an integer shift unit (e.g., ISHU202) executes scalar bit shift and rotate operations; a floating-point unit (e.g., FPU203) performs arithmetic operations on floating point numbers; a vector permute unit (e.g., VPU205) executes vector permute instructions and vector byte shift/rotate instructions; a vector simple integer unit (e.g., VSIU206) executes vector addition, subtraction and bit shifting instructions; a vector complex integer unit (e.g., VCIU2810) executes vector multiplication, multiplication-addition, and summation (e.g., addition of more than two values) instructions; and a vector floating-point unit (e.g., VFPU209) performs arithmetic operations on vectors of floating point numbers. Most vector operations are performed on bytes (8-bit), half-words (16-bit), or words (32-bit) stored in vector registers.

A vector look-up table unit (e.g., VLUT208) can look up a vector of data items from a number of look-up tables simultaneously using a vector of indices. Some details of a vector look-up table unit, as well as more details of a VLIW processing engine, are described in a co-pending U.S. patent application, Ser. No. 10/038,351 entitled “Apparatus for Parallel Table Look-Up” by Joseph P. Bratt, et al, which application is hereby incorporated here by reference.

FIG. 3shows a flow diagram illustrating the general steps used by a processor to manipulate data in executing an instruction according to one embodiment of the present invention. In operation301, an instruction decoder (e.g., instruction dispatcher241inFIG. 2) receives an instruction (e.g., from instruction cache243inFIG. 2) and decodes the instruction to determine the operations to be performed.

In operation303, register files (e.g., general purpose register file221, vector register file231, special purpose register file227inFIG. 2) or memory (e.g., local memory213, or host memory127) are accessed to retrieve data required by the instruction. Direct Memory Access (DMA) controller (e.g., DMA controller215) may be used to transfer data from (or to) host memory in operation303.

In operation305, the execution unit (e.g., Vector Simple Integer Unit (VSIU)206, Vector Look up Table Unit (VLUT)208, or Vector Complex Integer Unit (VCIU)207) is enabled to perform the operation on the data accessed in operation303. The result is stored into the register file (e.g., vector register file231, special purpose register227) or into memory (e.g., local memory213, or host memory127) according to the requirements of the instruction in operation307.

In one embodiment of the present invention, data to be processed are first loaded into local memory213. Vectors of data are loaded from the local memory into the vector register file before the execution of an instruction. After the execution of the instruction, the results in the vector register are transferred into the local memory.

At least one embodiment of the present invention seeks to compute a zero run value for each of a vector of numbers by using a single instruction in a vector execution unit such that a plurality of run values can be evaluated using a single instruction.

FIG. 4shows a block diagram representation of a circuit for the execution of a method to compute zero run values for a vector of numbers. Vector register401(vA) contains a vector of bit. The bit segments in vA are selected as numbers410-417(A0-A7). Numbers405(Bx) and407(Cx) are received from other vector registers (or from general purposed registers) to provide a reference point for the computation of run values for A0-A7in a list, where Cx represents the run value of Bx in the list, in which A0-A7immediately succeeds Bx. If Bx is not zero, multiplexer440selects zero (451) into D0(420) as the run value for A0; otherwise, the result of adder430, which is the sum of Cx (407) and one (453), is selected by multiplexer440into D0(420) as the run value for A0. Multiplexer441then determines the run value for A1(441) from the value of A0and the run value of A0. If A0is zero, adder431increase D0by one, and the result is selected by multiplexer441into D1(421) as the run value for A1; otherwise, multiplexer441selects zero into D1. In this fashion, adders431-437and multiplexers441-447compute run values D1-D7for A1-A7respectively. The run values in D0-D7are stored into vector register403(vD) after the computation.

When number A0is the first element in a list, an arbitrary non-zero number can be used as Bx so that the run value of A0is zero.

Numbers Bx and Cx can be received from the last elements of two vector registers so that, when run values of the list of elements are evaluated using more than two vector operations for computing run values, input and output vectors in a previous operation can be used directly as input vectors for the next operation, as illustrated in the examples below.

Alternatively, since A7is not used in the computation of the run values (D0-D7), the circuit may be modified such that Bx (405) and A0-A6(410-416) are received from vector register401(vA). In such an embodiment, vector register vA contains Bx and A0-A6, instead of A0-A7.

FIG. 5illustrates data representations for the execution of an instruction for computing run values for a vector of elements in a list of elements according to one embodiment of the present invention. Instruction veczrun500contains bit segments501-507for specifying the vector registers (vA, vB, vC) that contain the input data and the vector register (vD) for storing the vector of computed run values. Vector register file550contains entries510,520,530and540(vector registers vA, vD, vB and vC). Bit segments501,503,505and507specify respectively the locations of vector registers vD, vA, vB and vC in the vector register file. Vector register vA contains in bit segments511-518a vector of numbers from a list, for which the run values are computed after the execution of the instruction; and vector register vD is for storing the resulting run values. Number Bx, which immediately precedes A0(511) in the list, is stored in bit segment531; and its run value (Cx) is stored in bit segment541. After the execution of the instruction, the locations of vA(510) and vD(520) can be used in the next veczrun instruction for specifying a reference point for the computation of the next vector of run values, and the data in vector registers vA and vD (e.g., bit segments518and528) can be directly used to provide the reference point without further manipulation. In one embodiment of the present invention, the zero run value computing instruction is implemented using a vector simple integer unit (e.g., VSIU206).

FIG. 6illustrates an example to compute zero run values. The run values of the list of numbers in vectors vA0(671), vA1(673), . . . , vA7(677) are computed and stored in vectors vD0(681), vD1(683), . . . , vD7(687). To compute the first vector of run values vD0, a non-zero number is used as a reference (e.g., Bx) such that the first element601has a run value of zero (631). It is seen that vD0contains a run value for each of the elements in vA0, including those which are equal to zero. For example, element606, which is zero, has a run value of two, which indicates that there are two consecutive zero elements (elements604and605) immediately preceding element606. To compute run values in vD1, elements608and638are used as the reference point (Bx and Cx). Since element608is zero, one is added to run value638to obtain run value641for element611. Thus, the run value (643) of element613is three, which indicates that there are three consecutive zero elements (elements608,611and612) immediately preceding element613in the list. Since each of the elements has a run value indicating the number of consecutive zero elements immediately preceding it in the list, an index indicating the location of the last non-zero element in the list can be determined from the number of elements in the list and the run value of the last element in the list. For example, the last element (651) in the list of elements stored in vectors vA0-vA7is zero. The run value (655) of element651is 10. Thus, the last non-zero element is ten elements ahead of the last element (651) in the list. Since the number of elements in the list is 64, the index for element651is 63 (assuming the indices start from 0). Thus, the index for the last non-zero element (653) is 63−10−1 =52.

FIG. 7shows a flow diagram for a method to compute zero run values for a vector of elements according to one embodiment of the present invention. In operation701, information about a reference point is received in terms of number X and value R, where value R represents the run value of number X in a list of numbers. Number X and value R can be received from vector registers (e.g., vB and vC in vector register file550inFIG. 5) in one embodiment of the present invention, or be received from general purpose registers in alternative embodiments. In operation703, a vector of numbers, which follows immediately after number X in the list of numbers, are received from a vector register. In operation705, a run value is computed for each of the vector of numbers to indicate the number of consecutive elements of a specific value (e.g., zero) immediately preceding the corresponding element of the vector in the list. The computed run values are stored into a vector register in operation707. In one embodiment, the computed run values can be saved into the same vector register that is used to provide value R.

FIG. 8shows a flow diagram for a method to zero run length encode a list of elements according to one embodiment of the present invention. In operation801, a run value is generated for each of a list of elements (e.g., using vector operations as illustrated inFIGS. 4-7or the method inFIG. 9). An index pointing to the last non-zero element in the list can then be computed from the number of elements in the list and the run value of the last element of the list in operation803. The elements in the list can be zero run length encoded using the computed run values. If operation805determines that an element being encoded is equal to zero, operation813is used to skip this element and to process the next element in the list; otherwise, operation807is used to encode the element with its corresponding run value. In some embodiments, operation807includes variable length encoding for the non-zero element and its run value. If operation809determines that the element encoded in operation807is the last non-zero element, operation811is used to finish encoding the list of elements without going through the remaining elements in the list, since the remaining elements are all zeros. For example, a symbol for end-of-block (EOB) may be used to terminate the encoded list. If operation809determines that the element encoded in operation807is not the last non-zero element, operation813proceeds to process the next element in the list. The method shown inFIG. 8can be used to run length encode image data in accordance with JPEG, MPEG2, MPEG4, DV, H.261, H.263, or other formats with zero run length.

FIG. 9shows a flow diagram for a method to compute zero run values for a list of elements according to one embodiment of the present invention. The list of numbers is broken into a number of vectors. Operation901initializes a vector register vB such that the last element of vB (e.g., Bx531inFIG. 5) is not zero in order to force the first element of the list to have a run value of zero. Operation903loads the first vector of numbers into vector register vA using load/store unit (LSU). While operation905generates a vector of run values in vector register vD using a vector simple integer unit (e.g., VSIU206), operation907concurrently loads a second vector of numbers in a vector register using LSU. While operation909generates a next vector of run values using VSIU, LSU concurrently stores the vector of run values, generated in operation905, into memory (e.g., local memory213) in operation911and loads a next vector of numbers from memory in operation913. If operation915determines that the vector processed in operation907is the last vector of elements, operation917is used to store the run values for the last vector of elements into memory; otherwise, operations909,911and913are repeated to computer the run values for the next vector of numbers. Note that when operation909is used to computes the run values for the last vector of elements, operation913is not necessary.

FIG. 10shows a flow diagram for a method to compute an index pointing to the last non-zero element in a list of elements according to one embodiment of the present invention. If operation1001determines that the last element in the list is equal to zero, operation1003is used to compute the index pointing to the last non-zero element from the index of the last number; otherwise, operation1005is used to compute the index pointing to the last non-zero element from the result of subtracting the run value of the last element from the index of the last element. A1ternatively, a number of zeros can be appended to a given list of elements such that the last element of the expanded list is always zero. When such an expanded list is used, only operation1005is necessary.

Thus, the present invention provides methods and apparatuses for efficiently perform run length encoding, which can be used for compressing images and video streams of in a variety of formats, including those in accordance with DV, MPEG2, MPEG4, H.261, H.263, and other standards.

At least one embodiment of the present invention seeks to variable length encode a plurality of symbols using a single instruction in a vector execution unit such that a plurality of codewords can be generated using a single instruction.

Zero run length encoding converts a list of elements into an equivalent string of run-level pairs. Each of the run-level pairs is a symbol, which can be converted into a variable length codeword for further lossless data compression. In video/image compression, a symbol from run length encoding with a large run value or a large absolute value for the non-zero element statistically has a low frequency of occurrence. Thus, variable length encoding can be used to further compress the run length encoded data. Most of the video/image compression standards used the run value and the absolute value of the non-zero element of a symbol to first define a codeword; and the sign bit of the non-zero element is then appended to the variable length codeword to generate the codeword for the symbol.

In the MPEG and H.26x standards, the statistical distribution of the symbols resulting from the inter-mode compression for reducing temporal redundancy in video image data is different from that for the symbols resulting from the intra-mode compression for reducing spatial redundancy in the video image data. Thus, two different variable length codeword tables are used for variable length encoding.

FIG. 11shows a block diagram representation of a circuit for the execution of a method to variable length encode a plurality of symbols according to one embodiment of the present invention. Vector register vB (1103) contains bit segments representing index0(1111) and index1(1121). Index0and index1are generated from symbols to be variable length encoded so that the codewords corresponding to these symbols may be looked up from the look up tables in VLC coding logic 0 and VLC coding logic 1 (1131and1141) respectively. However, some symbols must be encoded using escape codes. To accommodate various escape code formats, Type0and Type1(1113and1123) from vector register vB are used to specify the types of coding operations to be performed by VLC coding logic 0 and 1. Level0and Level1(1115and1125) from the bit segments of vector register vA (1101) indicate the values of the sign bits of the corresponding symbols to be encoded. ESC0and ESC1(1117and1127) from the bit segments of vector register vC (1105) are the special codewords (e.g., escape codeword header, or escape codeword); and LESC0and LESC1are the bit lengths of ESC0and ESC1respectively. While VLC coding logic 0 (1131) processing the input parameters1111-1119to generate Codeword0(1133) and its bit length Length0(1135), VLC coding logic 1 (1141) concurrently processes the input parameters1121-1129to generate Codeword1(1143) and its bit length Length0(1145). The results (e.g., Codeword01133and Length01135) are stored into vector register vD (1151).

In one embodiment of the present invention, a VLC coding logic performs one of four coding operations according the value specified for the type parameter (e.g., Type01113or Type11123). These four coding operations are: i) outputting a codeword looked up from a look up table; ii) outputting the special codeword (e.g., ESC01117or ESC11127as the escape codeword); iii) outputting a resulting codeword from appending the codeword looked up from the look up table to the special codeword (e.g., using ESC01117or ESC11127as the escaped codeword header to form an escape codeword); and iv) outputting a zero as the resulting codeword.

FIG. 12shows a detailed block diagram for variable length coding logic according to one embodiment of the present invention. Index0(1211) is used in a look up table (1220) to look up an entry containing bit segments representing Code1251, Len1253and AddSign1255. In one embodiment of the present invention, the look up table is configured from a plurality of look up units. Each look up unit is a memory unit that can be individually addressed and accessed. For example, look up unit (LUT)0is a memory unit that has 256 8-bit entries. A number of look up units are combined to function as a single look up table. For example, LUT0, LUT1and LUT2(1221-1223) are combined to store the first, second, and third bytes of the first 256 24-bit entries of a look up table; and LUT3, LUT4and LUT5(1224-1226) are combined to store the first, second, and third bytes of the second 256 24-bit entries of the look up table. Thus, look up units0-5are combined to form a look up table with 512 entries. The lower 8-bit of Index0(1211) is used as index B0(1201) to simultaneously look up data items1241-1246from look up units1221-1226. The higher 8-bit of Index0(B11201) controls multiplexer1205to choose an entry according to whether or not Index0(1211) is larger than 255.

Tester1207compares Level0(1215) to zero to determine the state of the sign bit (Sign1257) of the symbol to be coded. The sign bit is right shifted by shifter1261and appended to Code1251by logic OR unit1263. AddSign (1255) causes multiplexer1265to select a codeword with a sign bit appended after Code (1251) when AddSign is one and to select Code (1251) from the look up table (without appending the sign bit) when AddSign is zero. Thus, multiplexer1265produces a codeword with or without appending the sign bit to the codeword looked up from table1220according to the value of AddSign1255. Similarly, multiplexer1269outputs the bit length of the codeword produced by multiplexer1265. Righter shifter1271and logic Or unit1273append to ESC01217the codeword produced by multiplexer1265; and adder1277computes the bit length of codeword produced by logic OR unit1273by summing LESC01217and the bit length of the codeword produced by multiplexer1265. Type0(1213) controls multiplexer1275to select as Codeword0(1233) from i) zero; or ii) ESC0(e.g., using the special codeword ESC0as the escape codeword, or a symbol for EOB); or iii) ESC0appended with Code1251looked up from table1220with or without the sign bit appended according to AddSign (e.g., using the special codeword ESC0as a escape header); or iv) Code1251looked up from table1220with or without the sign bit appended according to AddSign (e.g., using the look up table only). Similarly, multiplexer1279selects the bit length of Codeword0(1233) as Length0(1235).

FIG. 13illustrates data representations for the execution of an instruction to variable length encode a plurality of symbols according to one embodiment of the present invention. Instruction vecvlc1300contains bit segments1301-1307for specifying the vector registers (vA, vB, vC) that contain the input data and the vector register (vD) for storing the results. Vector register file1350contains entries1310,1320,1330, and1340(vector registers vA, vB, vC, and vD). Bit segments1301,1303,1305and1307specify respectively the locations of vector registers vD, vA, vB and vC in the vector register file. Vector register vA contains in bit segments1311-1314the vector of levels, which contains the values of the sign bits of the four symbols to be encodes. Vector register vB contains in bit segments1321-1324the vector of indices for looking up codewords from look up tables, as well as the vectors of types (in bit segments1326-1329) for specifying the types of the coding operations, for encoding the four symbols. In one embodiment of the present invention, an execution unit contains 16 look up units; and each of the codeword look up tables contains 512 24-bit entries and, thus, requires 6 look up units. Therefore, only two symbols can be processed concurrently. Vector register vC contains bit segments1331and1333for specifying two special codewords (e.g., Escape codeword header, or Escape codeword) and bit segments1332and1334for specifying the bit lengths of the corresponding special codewords. Vector register vD contains bit segments1341and1343for storing the resulting codewords and bit segments1342and1344for storing the bit lengths of the corresponding codewords. One instruction is used for computing codewords using Level0(1311), Level1(1312), Index0(1321), Index1(1322), Type0(1326) and Type1(1327) from vector registers vA and vB with the input parameters in vC to generate variable length codewords for the first two symbols; and another instruction is used for computing codewords using Level2(1313), Level3(1314), Index2(1323), Index3(1324), Type2(1328) and Type3(1329) from vector registers vA and vB with the input parameters in vC to generate variable length codewords for the next two symbols (after the parameters in vC are updated for the next two symbols to be encoded when necessary). Since a 56-bit bit segment in input vector register vC is allocated for the storage of each of the special codewords, various formats of escape codes, end-of-block codewords, etc, can be used with instruction vecvlc.

FIG. 14illustrates data representations of a codeword look up table which can be used with the instructions to variable length encode a plurality of symbols according to one embodiment of the present invention. Each entry of the look up table contains 16 bits for storing a codeword (bits [0:15]), 4 bits for storing a codeword length (bits [16:19]) and 1 bit for an AddSign bit. When a look up table is configured from six look up units (LUT0-LUT5), each of which contains 256 8-bit entries, bits [0:7] of entries 0-255 are stored in LUT0; bits [8:15] of entries 0-255 are store in LUT1; and bits [16:20] of entries 0-255 are stored in LUT2; bits [0:7] of entries 256-511 are stored in LUT3; bits [8:15] of entries 256-511 are store in LUT4; and bits [16:20] of entries 256-511 are stored in LUT5. Such a look up table can hold variable length codeword tables for both the inter-mode compression and the intra-mode compression in accordance with MPEG (or H.26x) standard. It can hold reversible variable length codeword table for compression in accordance with MPEG4 as well. Thus, it can hold variable length codeword tables to perform variable length encoding in accordance with DV, MPEG2, MPEG4, H.261, H.263, and other standards.

FIG. 15shows a flow diagram for a method to variable length encode a plurality of symbols according to one embodiment of the present invention. Operation1501receives from vector registers input parameters (e.g., indices for look up tables, types of coding operations, special codewords and their lengths, sign bit indicators, etc) for a plurality of symbols to be variable length encoded. Operation1503configures a plurality of look up units to function as a plurality of look up tables for looking up codewords for the plurality of symbols respectively. Each of the look up tables may utilize more than one look up tables. Operation1505looks up simultaneously a plurality of entries from the plurality of look up tables respectively. When more than one look up units are combined to function as a look up table, look-up results from these look up units are combined to form a entry looked up from the look up table. The plurality of entries and the input parameters are combined to generate a plurality of variable length codewords for the plurality of symbols respectively in operation1507. The plurality of variable length codewords are output into a vector register in operation1509.

FIG. 16shows a detailed flow diagram for a method to variable length encode a symbol according to one embodiment of the present invention. Operation1601receives a type of the code operation (e.g., Type0inFIG. 12). Operation1603receives a special codeword (escape codeword, escape codeword header, EOB, or others) and the bit length of the special codeword (e.g., ESC0and LESC0inFIG. 12). Operation1605determines whether or not the type (e.g., Type0) is for using the special codeword directly. When the type is for using the special codeword directly, operation1607outputs the special codeword and its bit length as the result. When the type is not for using the special codeword directly, operation1609receives an index for a codeword look up table. Operation1611performs look up operations simultaneously in a number of look up units to obtain results, which are combined as an entry from a look up table. The entry contains a first codeword, the bit length of the first codeword, and an AddSign bit for determining whether or not to append the sign bit of the symbol to the first codeword. When operation1613determines the AddSign bit is equal to 1, operation1615receives a first number indicating the value of the sign bit of the symbol to be encoded; operation1617obtains the sign bit of the symbol to be encoded from the first number; and operation1619appends the sign bit to the first codeword and increases the bit length of the first codeword by one to include the appended sign bit. Then, operation1621determines whether or not the type of operation is for using a standard look up operation. When the type is for using the codeword from a standard look up operation, operation1625outputs the first codeword and its bit length as the result; otherwise, operation1623determines whether or not the type is for using the special codeword as an escape header. When the type is for using the special codeword as an escape header, operation1631appends the first codeword after the special codeword to obtain a second codeword and sums the bit lengths of the special codeword and the first codeword to obtain the bit length of the second codeword; and operation1629outputs the second codeword and its bit length as the result. Otherwise, the type is for generating a zero as the result; and operation1627outputs a zero.

FIG. 17illustrates a flow diagram for a method to variable length encode a plurality of symbols according to one embodiment of the present invention. Operation1701preprocesses a list of symbols to be variable length encoded to generate indices for the corresponding symbols. Operation1703detects symbols that require special codewords, for example, an escape codeword, an escape codeword header, a symbol for EOB, or others; and operation1705generates the special codewords for the corresponding symbols. Operation1707generates variable length codewords for the list of symbols (e.g., using vector variable length encoding instructions vecvlc) using a vector execution unit. In one embodiment of the present invention, indices and sign indicators for four symbols to be encoded are loaded into vector registers (e.g., vA1310and vB1320inFIG. 13). The special codewords for the first two of the symbols are loaded in another vector register (e.g., vC1330); and one variable length encoding instruction is used to encode the first two of the symbols. Then, the special codewords for the second two of the symbols are loaded in a vector register; and another variable length encoding instruction is used to encode the second two of the symbols. Operation1709packs the generated variable length codewords for the list of symbols into a bit stream. More details about packing variable length codewords into a bit stream are described further below.

Thus, the present invention provides methods and apparatuses for efficiently perform variable length encoding using a vector execution unit, which can be used for compressing images and video streams of in a variety of formats, including those in accordance with DV, MPEG2, MPEG4, H.261, H.263, and other standards.

At least one embodiment of the present invention seeks to concatenate a plurality of variable length codewords using a single instruction in a vector execution unit such that a plurality of codewords can be concatenated into a bit stream in a vector register using a single instruction.

FIG. 18shows a block diagram representation of a circuit for the execution of a method to concatenate a plurality of variable length codewords according to one embodiment of the present invention. Vector register vA (1801) contains bit segments representing Codeword0(1803), Codeword1(1807) and their bit lengths (Length01805and Length11809). While right shifter1811and logic Or Unit1813append Codeword1(1807) after Codeword0(1813) to concatenate the two codewords into bit stream1833, concurrently, adder1815sums the bit lengths of Codeword0and Codeword1(Length01805and Length11809) to compute the bit length (Length1835) of the resulting bit stream (1833); and testers1817and1819determine whether the bit lengths of the input codewords (Codeword0and Codeword1) are larger than zero. When Length0(1805) for Codeword0(1803) is zero, bit CCR0(1823) in a condition register (e.g., special purpose register227inFIG. 2) is set to zero, otherwise, CCR0(1823) is set to one. Similarly, bit CCR1(1821) in the condition register is set to indicate whether or not Length1(1809) is zero. The resulting bit stream (1833) and its bit length are stored in vector register vD (1831).

FIG. 19illustrates data representations for the execution of an instruction to concatenate a plurality of variable length codewords according to one embodiment of the present invention. Instruction veccat1900contains bit segments1903and1901for specifying the vector register (vA) that contains the input data and the vector register (vD) for storing the results. Vector register file1950contains entries1910and1920(vector registers vA and vD). Bit segments1901and1903specify respectively the locations of vector registers vD and vA in the vector register file. Vector register vA contains bit segments1911and1913for the codewords (Codeword01911and Codeword11913) to be concatenated and bit segments1912and1914for specifying the bit lengths of the codewords (Length0and Length1) respectively. Vector register vD contains bit segments1921for storing the bit stream resulting from concatenating the codewords (Codeword0and Codeword1) and bit segment1922for storing the bit length of resulting bit stream. In condition register1930, bits1931and1932are used to store the indicators, each which indicates whether or not the bit length of a corresponding input codeword is non-zero.

Since each codeword (e.g., Codeword01911or Codeword11913) to be concatenated has a bit length smaller than 57, the bit length of the resulting bit stream (e.g., Bitstream1921) is always smaller than113, which can be entirely stored in bit segment1921. No overflow will occur.

It is apparent from above description that the method and apparatus illustrated inFIGS. 18 and 19cannot only be used to concatenate codewords from variable length encoding, but also be used to concatenate bit streams of variable lengths into a single fragment of bit stream. Thus, it is understood that codewords include bit streams in general and variable length codewords generated from variable length encoding in particular.

FIG. 20shows a detailed flow diagram for a method to concatenate a plurality of variable length codewords according to one embodiment of the present invention. Operation2001receives a plurality of codewords and their bit lengths from a vector register. Operation2003concatenates the plurality of codewords to generate a bit stream; Operation2005sums the bit lengths of the codewords to generate the bit length of the bit stream; and operation2007generates a plurality of indicators, each of which indicates whether or not the bit length of a corresponding one of the plurality of codewords is larger than zero. Note that operation2003,2005and2007can be performed in a different order other than that shown inFIG. 20. In one embodiment of the present invention, operations2003,2005and2007are performed concurrently. Operation2009outputs the bit stream and its bit length into a vector register and sets a plurality of bits in a special register according to the plurality of indicators.

FIG. 21shows a flow diagram for a method to concatenate a plurality of variable length codewords according to one embodiment of the present invention. Operation2101loads a plurality of codewords and their bit lengths in vector register vA; and operation2103performs a codeword concatenation operation (e.g., using instruction veccat) and saves the result in vector register vD. According to one embodiment of the present invention, the variable length codewords generated using instruction vecvlc inFIG. 13are stored in the vector register (vD1340inFIG. 13) in a format that is the same as that for the input vector (vA1910inFIG. 19). Thus, a plurality of codewords generated in a vector register by using an instruction for variable length encoding can be used directly for concatenation without further manipulation.

Thus, the present invention provides methods and apparatuses for efficiently concatenating codewords of variable lengths into a single bit stream, which can be used to concatenating vectors of variable length codewords generated using various methods according to the present invention for packing variable length codewords into a bit stream.

At least one embodiment of the present invention seeks to efficiently pack bit streams of variable lengths into a continuous stream of bits such that a plurality of bit streams of variable lengths can be concatenated into a single bit stream.

To concatenate a plurality of bit streams into a single stream of bits, a vector register is used to collect the bits from these bit streams. When the space in the vector register for collecting bits of data is completely filled, the resulting bit segment in the space for collecting bits is stored into memory. The size of space for collecting bits is such that when stored into memory the resulting bit segment is properly aligned in memory (e.g., aligned to a byte boundary, to a halfword boundary, or to a word boundary). Therefore, after repeatedly filling the space with bits from the bit streams to be packed and consecutively storing the resulting bit segments in the space into memory, these bit streams can be packed into a single stream of bits.

FIG. 22illustrates various scenarios of packing bit streams according to one embodiment of the present invention. In scenario2200, bit stream2203in vector vB is packed into vector vA in an initial condition. Bit stream2203is copied as bit segment2205in the resulting vector vD. Since the bit stream2203does not fill up the space provided for the resulting bit stream, resulting vector vD is in an underflow condition, which indicates that more bits of data can be packed into vector vD.

In scenario2210, bit stream2213in vector vB is packed into vector vA which is in an underflow condition. Since the sum of the bit lengths of the bit streams2211and2213is smaller than the space provided in the resulting vector vD, the bit stream resulting from concatenating bit stream2211and2213are stored in the resulting vector vD (2215and2217), which is in an underflow condition.

In scenario2220, bit stream2223in vector vB is packed into vector vA which is in an underflow condition. Since the sum of the bit lengths of the bit streams2221and2223is equal to the space provided in the resulting vector vD, the bit stream resulting from concatenating bit stream2221and2223are stored in the resulting vector vD (2225and2227), which is in an equal condition. When a vector is in an equal condition, no more bits of data can be packed into the vector; and the fully packed bit segment can be stored away into memory.

In scenario2230, empty bit stream2233in vector vB is packed into vector vA which is in an underflow condition. Since the empty bit stream (a bit stream of a zero bit length) is used to indicate the end of a string of bit streams to be packed, bits of zeros are appended to bit stream2231to fill up the space in the resulting vector vD (2235), which is in an end condition, so that the packed bit segment can be stored away. When a vector is in an end condition, the process for packing a new string of bit streams can be started.

In scenario2240, a bit stream (2243and2244) in vector vB is packed into vector vA which is in an underflow condition. Since the sum of the bit lengths of the bit stream in vB and the bit stream2241is larger than the space provided in the resulting vector vD, only a portion of the bit stream in vB can be packed into the resulting vector vD. Thus, the bit stream resulting from concatenating bit stream2241and2243are stored in the resulting vector vD (2245and2247), which is in an overflow condition. When a vector is in an overflow condition, no more bits of data can be packed into the vector; and remaining bits2244in vB, which can not be fitted in the resulting vector, must be packed in the next packing operation. Since the resulting vector vD is fully packed, the fully packed bit segment can be stored away into memory.

In scenario2260, a bit stream (2263and2264) in vector vB is packed into vector vA which is in an overflow condition. Since bit segment2263is packed in a previous operation, it is necessary to pack only bit segment2264. Since the bit streams2261and2262have been stored away, they are ignored. Thus, the resulting bit stream2265contains only a copy of bit segment2264. The resulting vector is in an underflow condition.

In scenario2250, bit stream2253in vector vB is packed into vector vA which is in an equal condition. Since the bit streams2251and2252have been stored away, they are ignored. Thus, the resulting bit stream2255contains only a copy of bit segment2253. The resulting vector is in an underflow condition.

In scenario2270, empty bit stream2273in vector vB is packed into vector vA which is in an equal condition. Since the bit streams2271and2272have been stored away, they are ignored. Thus, the resulting bit stream2275contains no valid bits; and the resulting vector is in an end condition.

Thus, in packing a string of bit streams, a vector (e.g., vA or vD) may change from an initial condition to an underflow condition (2291), from an underflow condition to an underflow condition (2292), or to an equal condition (2293), or to an end condition (2294), or to an overflow condition (2295), from an overflow condition to an underflow condition (2297), from an equal condition to an underflow condition (2296), or to an end condition (2298), or from an end condition to an initial condition (2298).

FIG. 23shows a state diagram of packing bit streams according to one embodiment of the present invention. In one embodiment of the present invention, the bit length of an input bit stream to be packed (e.g., bit stream2203inFIG. 22) is always smaller than the space available for packing in a vector in an initial condition. Thus, a packing operation can change a vector from initial state2301only to underflow state2303(assuming that no empty stream is used as the first bit stream to be packed). Depending on the bit length of the input bit stream and the bit length of the bit stream already packed in a vector that is in an underflow condition, a packing operation changes the vector from underflow state2303to overflow state2309, or to equal state2305, or to end state2307(when the input bit stream is an empty stream), or to underflow state2303. A packing operation can change a vector from overflow state2309only to underflow state2303, since the bit length of the remaining bit stream that is not packed in the previous operation is always smaller than the size of the space available for packing (see, for example, scenario2260inFIG. 22). Equal state2305can switch to either underflow state2303when the input bit stream is not an empty stream or end state2307when the input bit stream is an empty stream.

Alternative, when the bit length of an input bit stream to be packed can be larger than the space available for packing in a vector in an initial condition, more transition paths among various states are possible, which are not illustrated inFIG. 23. For example, initial state2301may switch to overflow state2309or equal state2305; overflow state2309may switch to equal state2305or overflow state2309; and equal state2305may switch to overflow state2309or equal state2305.

Various parameters about the current state of the packing operations can be stored in the vector for packing to facilitate the state switching (e.g., along the paths illustrated inFIG. 23).

FIG. 24shows a block diagram representation of a circuit for the execution of a method to pack bit streams according to one embodiment of the present invention. Vector register vB (2403) contains bit segments for specifying an input bit stream2418(BitStream) and it bit length2419(Length). Vector register vA (2401) contains bit segments for a bit stream2411(BitStream1) that has been packed in a previous packing operation and flags2412(Flag1) that indicate the state of the previous packing operation. Vector register vA (2401) also contains bit segments for storing parameters2413-2416(SrcStart1, SrcEnd1, DestStart1, DestEnd1) from the previous packing operation that can be used to compute the parameters required to perform the current packing operation (e.g., the available space and location for packing the bits from BitStream (2418), and others). More details about these parameters are described further below. Bit stream packing logic2410appends the bits from BitStream (2418) after BitStream1(2411) within the available space for packing to generate BitStream2(2421). Flags2422(Flag2) are set to indicate the state of the current packing operation; and updated parameters2423-2426(SrcStart2, SrcEnd2, DestStart2, DestEnd2) are generated from the current packing operation. In one embodiment of the present invention, bits in a condition register (CCR0and CCR1) are set to indicate whether or not all bits in BitStream (2418) are packed into BitStream2(2421) and whether or not BitStream2(2421) is fully packed (reached required bit length).

In one embodiment of the present invention, parameters SrcStart2(2423) and SrcEnd2(2424) are used to indicate in BitStream (2418) the locations of the starting and ending bits of the bit segment of BitStream (2418) that is packed into BitStream2(2421); and parameters DestStart2(2425) and DestEnd2(2426) are used to indicate in BitStream2(2421) the locations of the starting and ending bits of the bit segment of BitStream that is packed into BitStream2(2421). Similarly, SrcStart1(2413) and SrcEnd1(2414) are used to indicate in the input stream the position of the input bit segment that is packed into BitStream1(2411) in the previous packing operation; and DestStart1(2415) and DestEnd1(2416) are used to indicate in the BitStream1(2411) the position of the packed input bit segment in the previous packing operation. More details about such an embodiment are described below with the description ofFIG. 25.

In an alternative embodiment of the present invention, parameters SrcStart1(2413) and SrcEnd1(2414) are used to indicate in BitStream (2418) the locations of the starting and ending bits of the input bit segment of BitStream (2418) to be packed by bit stream packing logic2410in the current packing operation; and parameters DestStart1(2415) and DestEnd1(2416) are used to indicate the locations of the starting and ending bits of the bit segment in a resulting bit stream that may be used to pack the bits from BitStream by bit steam packing logic2410in the current packing operation. Similarly, SrcStart2(2423), SrcEnd2(2424), DestStart2(2425), DestEnd2(2426) are updated by bit stream packing logic2410to indicate the remaining bits in BitStream (2418) that needs to be packed in the next packing operation, if any, and the available space in vD (2405) for the next packing operation. More details about such an embodiment are described below with the description ofFIG. 26.

FIG. 25shows a detail block diagram representation of bit stream packing logic according to one embodiment of the present invention. In one embodiment of the present invention, Flag1(2512) contains bits PreEqual (2501), PreOverflow (2502) and PreUnderflow (2503). PreOverflow is one when the previous packing operation is in the state of overflow and zero when otherwise. PreUnderflow is one when the previous packing operation is in the state of underflow and zero when otherwise. PreEqual is one when the previous packing operation is in the state of equal. DestEnd1(2516) is the index for the last bit in BitStream1; and adder2536increases DestEnd1by one to compute a candidate for DestStart2(2525), which is the index of the first bit in BitStream2for packing the bits from BitStream. When the previous operation is in an underflow condition, BitStream1has at least one bit of data; and multiplexer2537selects the result from adder2535. When the previous operation is not in an underflow condition, multiplexer2537selects zero so that the bits from BitStream is packed from the beginning of BitStream2.

SrcEnd1(2514) is the index for the last bit of the bit segments from BitStream that is packed into BitStream1in the previous packing operation. Adder2531increases SrcEnd1by one to compute a candidate for SrcStart2(2523), which is the index of the first bit in BitStream to be packed into BitStream2. When the previous operation is in an overflow condition, BitStream contains remaining bits to be packed into BitStream2; and multiplexer2533selects the result from adder2531. When the previous operation is not in an overflow condition, multiplexer2533selects zero so that the first bit to be packed is the first bit of BitStream.

Length (2519) is the total bit length of BitStream (2518). When the previous operation is not in an overflow condition, all the bits in BitStream2518must be packed; and multiplexer2509selects Length2519as InputBitLength, which is the total number of bits to be packed from the input bit stream2518. When the previous operation is in an overflow condition, only the remaining bits in BitStream need to be packed; and multiplexer2509selects the result from substractor2507, which reduces Length (2519) by the number of bits packed in the previous operation (the result from adder2531). In one embodiment of the present invention, the space for storing packed bit stream is 64 bits. Substractor2539produces the bit length of the available space for packing in the resulting bit stream the bits from BitStream. Multiplexer2549and tester2547select the smaller one of InputBitLength (2551) and AvailSpace (2553) as BitLength (2555), which is the number of bits to be packed into BitStream2in the current packing operation. Since BitLength2555is computed from comparing the available space for packing and the total input bits for packing, various state transition paths can be processed, including the paths not shown inFIG. 23(e.g., from overflow to equal, or from equal to equal, or from initial to overflow). Adders2567and2569computes SrcEnd2(2567) and DestEnd2(2569), the indices of the ending bits in BitStream and BitStream2respectively for the bit segment packed in the current packing operation.

When Length (2519) is not zero (i.e., the input bit stream is not an empty one), multiplexer2573selects the result of tester2547as the flag for the underflow flag in Flag2(2522). When the input bit stream is an empty one, the underflow flag in Flag2(2522) is set to zero by multiplexer2573. Thus, when all the three flags are set to zero, it is an indication that an empty bit stream is detected (the bit length of the input bit stream is zero); and the current packing operation is in an end condition; otherwise, one of the three flags is set to one, indicating the packing operation is in a state of overflow, or equal, or underflow.

Logic units2575,2577and2541produce CCR1(2507), which indicate whether or not the BitStream2fully packed. When the previous operation is in an underflow condition and the current input bit stream is an empty one, CCR1is set to one in order to flush out the bits in BitStream1(or BitStream2); otherwise, the resulting bit stream is fully packed only if InputBitLength (2551) is not smaller than AvailSpace (2553).

Testers2561and2563produce the results for the overflow and equal flags in Flag2for the current packing operation to indicate whether or not the current operation is in an overflow condition and whether or not the current operation is in an equal condition. Logic unit2571sets CCR0(2509) to zero only when an overflow condition occurs.

Shifters2543and2545and logic OR unit2579shift BitStream (2518) and appends BitStream (2518) to BitStream1(2511) to produce the resulting bit stream (BitStream22521).

FIG. 26shows a detail block diagram representation of bit stream packing logic according to another embodiment of the present invention. In this embodiment of the present invention, DestStart1(2615) and DestEnd1(2616) represent the indices of the beginning and ending bits of the available space for the current packing operation; and SrcStart1(2613) and SrcEnd1(2614) are the indices of the beginning and ending bits in the bit stream to be packed (BitStream), when SrcEnd1is not zero. Thus, adder2602and substractor2601compute the available space2631(AvailSpace) from DestEnd1(2616) and DestStart1(2615). When tester2605determines that SrcEnd1is zero, multiplexer2606selects Length (2619) as InputBitLength (2633), which is the total number of bits to be packed from the input bit stream2618; otherwise, adder2604and substractor2603computes InputBitLength (2633) from SrcEnd1(2614) and SrcStart1(2613).

Multiplexer2641and tester2643select the smaller one from AvailSpace (2631) and InputBitLength (2633) as BitLength (2635), which is the number of bits to be packed in the current packing operation. Tester2643produces Underflow2637, which indicates whether or not InputBitLength (2633) is smaller than AvailSpace (2631). When Underflow (2637) is one, multiplexer2653selects the sum of DestStart1(2615) and BitLength (2635) as DestStart2(2625) to indicate that the start point for packing the next bit stream is after the last bit packed in this operation; otherwise, multiplexer2653selects zero as DestStart2. DestEnd1is saved as DestEnd2without any modification.

Tester2645produces Overflow2639, which indicates whether or not the current packing operation is in an overflow condition. Logic unit2647inverses2637to generate Full (2649), which indicates whether or not the resulting bit stream (BitStream22621) is fully packed. Overflow2639and Full2649set the corresponding bits in Flag2(2622).

When the current packing operation is in an overflow condition (Overflow2639is one), adder2657and substractor2655compute SrcStart2(2623) and SrcEnd2(2661), the indices of the first and last bits of the remaining bits in BitStream to be packed in the next packing operation; otherwise, zeros are selected by multiplexer2663and2661as SrcStart2(2623) and SrcEnd2(2661) to indicate that the first and last bits of the next input stream must be determined from the bit length of the next input stream.

FIG. 27illustrates data representations for the execution of an instruction to pack bit streams according to one embodiment of the present invention. Instruction vecbpack2700contains bit segments2701-2705for specifying the vector registers (vA and vB) that contain the input data and the vector register (vD) for storing the results. Vector register file2750contains entries2710,2720and2730(vector registers vA, vB and vD). Bit segments2701,2703and2705specify respectively the locations of vector registers vD, vA and vB in the vector register file. Vector register vA contains bit segment2711for storing the bit stream packed in the previous packing operation (BitStream1), bit segment2712for storing the flags (Flag1), which indicate the state of the previous packing operation, and bit segments2713-2716for storing SrcStart1, SrcEnd1, DestStart1, and DestEnd1respectively. Vector register vB contains bit segment2721for storing the input bit stream to be packed (BitStream2721) and bit segment2722for storing the bit length of the input bit stream (Length2722). After the execution of instruction vecbpack, vector register vD contains bit segment2731for storing the bit stream resulting from the current packing operation (BitStream2), bit segment2732for storing the flags (Flag2), which indicate the state of the current packing operation, and bit segments2723-2726for storing updated parameters SrcStart2, SrcEnd2, DestStart2, and DestEnd2respectively. In one embodiment of the present invention, bits2711and2712(CCR0and CCR1) in a condition register (2740) are used to report whether or not all bits in BitStream (2721) are packed into bit segment2731and whether or not bit segment2731is fully packed.

FIG. 28shows a flow diagram for a method to pack bit streams according to one embodiment of the present invention. Operation2801receives a first bit segment from a vector register. Operation2803receives a second bit segment to be packed with the first bit segment. When operation2805determines that the sum of the bit lengths of the first and second bit segments is larger than the required length, operation2811concatenates the first bit segment and the beginning portion of the second bit segment to generate a third bit segment such that the bit length of the third bit segment is equal to the required length; and operation2813computes the parameters to specify the ending portion of the second bit segment that is not packed into the third bit segment and that must be packed in the next packing operation. When the operation2805determines that the sum of the bit lengths of the first and second bit segments is not larger than the required length, operation2807concatenates the first and second bit segments to generate a third bit segment. The third bit segment is output into a vector register in operation2809.

FIG. 29shows a detailed flow diagram for a method to pack bit streams according to one embodiment of the present invention. When operation2901determines that the state of the previous packing operation is overflow, operation2931receives a second bit segment which is the ending portion of the bit segment not packed in the previous packing operation. Operation2933generates a third bit segment from the second bit segment. Operation2935indicates that: i) the bit length of the third bit segment is not equal to the required length (partially packed and not ready to be saved as a fully packed bit segment); ii) the state of the current operation is underflow (there are valid bits of data in the resulting bit stream to be packed with the next input bit stream); and iii) the second bit segment is completely consumed (completely packed into the third bit segment).

When operation2901determines that the state of the previous packing operation is not overflow, operation2903receives a second bit segment to be packed. When operation2905determines that the previous packing operation is not underflow and operation2917determines that the length of the second bit segment is not zero, no valid bits of data are available to pack with the second bit segment; and operations2933and2935generates a third bit segments for the second bit segment. When operation2905determines that the previous packing operation is not underflow and operation2917determines that the length of the second bit segment is zero, no valid bits of data need to be packed; operation2919generates a third bit segment with bits of zero; and operation2937indicates that: i) the bit length of the third bit segment is not equal to the required length; ii) the state of the current operation is end (an empty input bit stream is encountered); and iii) the second bit segment is completely consumed (new input bit stream is required).

When operation2905determines that the previous packing operation is underflow, operation2907receives a first bit segment, with which the second bit segment is to be packed together. If operation2909determines that the second bit segment is an empty stream, operation2921appends the first bit segments with bits of zero to generate a third bit segment such that the third bit segment has a bit length equal to the require length; and operation2939indicates that: i) the bit length of the third bit segment is equal to the required length (ready as a fully packed bit stream); ii) the state of the current operation is end; and iii) the second bit segment is completely consumed.

When the second bit segment is not an empty stream, operation2923concatenates the first and second bit streams to generate a third bit segment, if operation2911determines that the sum of the bit lengths of the first and second bit segments is not larger than the required length. If operation2925determines that the sum of the bit lengths of the first and second bit segments is equal to the required length, operation2941indicates that: i) the bit length of the third bit segment is equal to the required length (ready to be saved as a fully packed bit segment); ii) the state of the current operation is equal; and iii) the second bit segment is completely consumed. Otherwise, operation2935is performed.

If operation2911determines that the sum of the bit lengths of the first and second bit segments is larger than the required length, operation2913concatenates the first bit segment and the beginning portion of the second bit segment to generate a third bit segment such that the bit length of the third bit segment is equal to the required length; operation2915computes the parameters to specify the ending portion of the second bit segment that is not packed into the third bit segment and that needs be packed in the next packing operation; and operation2943indicates that: i) the bit length of the third bit segment is equal to the required length (ready to be saved as a fully packed bit segment); ii) the state of the current operation is overflow (there are remaining bits in the second bit segment to be packed in the next packing operation); and iii) the second bit segment is not completely consumed.

Finally, operation2945outputs the third bit segment to a vector register (or memory).

FIG. 30shows a flow diagram for a method to pack bit streams according to one embodiment of the present invention. Operation3001initializes vector register vA to represent a vector in an initial condition. Operation3003loads a first bit stream to be packed and its bit length in vector register vB. Operation3005performs a bit stream packing operation (e.g., using instruction vecbpack) and saves the result in vector register vA. If operation3007determines that the bit length of the resulting bit stream in vA is equal to the required length, operation3009saves the resulting bit stream from vA to memory. If operation3011determines that the previous packing operation (3005) is in a state of overflow, the data in vector vB is reused as input without any modification to perform the next packing operation (3005); otherwise, operation3017determines whether or not an end condition is encountered (e.g., an empty input stream is detected in vector register vB). If no end condition is encountered, operation3015loads the next bit stream to be packed and its bit length in vector register vB; and operation3005is used to pack the next bit stream.

Thus, the present invention provides methods and apparatuses for efficiently packing bit streams of variable lengths into a single segment stream of bits, which can be used to concatenating variable length codewords generated using various methods according to the present invention into a single stream of bits.