Spacer layer for embedding semiconductor die

A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

BACKGROUND

The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

While many varied packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted and interconnected on a small footprint substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound which provides a protective package.

A cross-sectional side view and a top view of a conventional semiconductor package20are shown inFIGS. 1 and 2(without molding compound inFIG. 2). Typical packages include a plurality of semiconductor die, such as flash memory die22and a controller die24, affixed to a substrate26. A plurality of die bond pads28may be formed on the semiconductor die22,24during the die fabrication process. Similarly, a plurality of contact pads30may be formed on the substrate26. Die22may be affixed to the substrate26, and then die24may be mounted on die22. All die may then be electrically coupled to the substrate by affixing wire bonds32between respective die bond pad28and contact pad30pairs. Once all electrical connections are made, the die and wire bonds may be encapsulated in a molding compound34to seal the package and protect the die and wire bonds.

In order to most efficiently use package footprint, it is known to stack semiconductor die on top of each other, either completely overlapping each other, or with an offset as shown inFIGS. 1 and 2. In an offset configuration, a die is stacked on top of another die so that the bond pads of the lower die are left exposed. An offset configuration provides an advantage of convenient access of the bond pads on each of the semiconductor die in the stack. While two memory die are shown in the stack inFIG. 1, it is known to provide more memory die in the stack, such as for example four or eight memory die.

In order to increase memory capacity in semiconductor packages while maintaining or reducing the overall size of the package, the size of the memory die has become large compared to the overall size of the package. As such, it is common for the footprint of the memory die to be almost as large as the footprint of the substrate.

The controller die24is generally smaller than the memory die22. Accordingly, the controller die24is conventionally placed at the top of the memory die stack. This configuration has certain drawbacks. For example, is difficult to form a large number of wire bonds from the die bond pads on the controller die down to the substrate. It is known to provide an interposer or redistribution layer beneath the controller die so that wire bonds are made from the controller die to the interposer, and then from the interposer down to the substrate. However, this adds cost and complexity to the semiconductor device fabrication. Moreover, the relatively long length of the wire bonds from the controller die to the substrate slows down operation of the semiconductor device.

DETAILED DESCRIPTION

The present technology will now be described with reference toFIGS. 3 through 34, which in embodiments, relate to a semiconductor device including a semiconductor die, such as a controller, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate. In one embodiment, the substrate-mounted semiconductor die may fit within an aperture formed through first and second opposed surfaces of the spacer layer. In a further embodiment, the substrate-mounted semiconductor die they fit within a notch formed through a portion of an edge of the spacer layer. The spacer layer of either embodiment may be formed and cut from a semiconductor wafer in embodiments of the present technology. Once a spacer layer is affixed to the substrate, one or more additional semiconductor die may be mounted on top of the spacer layer.

It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.

The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal” as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the invention inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±0.25%.

An embodiment of the present invention will now be explained with reference to the flowcharts ofFIGS. 3 and 7, and the views ofFIGS. 4-6 and 8-22. Although the figures show an individual semiconductor device100, or a portion thereof, it is understood that the device100may be batch processed along with a plurality of other devices100on a substrate panel to achieve economies of scale. The number of rows and columns of semiconductor devices100on the substrate panel may vary.

The substrate panel may begin with a plurality of substrates102(again, one such substrate is shown inFIGS. 4-5for example). The substrate102may be a variety of different chip carrier mediums, including a printed circuit board (PCB), a leadframe or a tape automated bonded (TAB) tape. The substrate may include a plurality of vias104, electrical traces106and contact pads108. The substrate102may include many more vias104, traces106and pads108(only some of which are numbered in the figures), and they may be in different locations than are shown in the figures.

Referring to the flowchart ofFIG. 3, passive components112may be affixed to the substrate102in a step200. The one or more passive components may include for example one or more capacitors, resistors and/or inductors, though other components are contemplated. The passive components112shown (only one of which is numbered in the figures) are by way of example only, and the number, type and position may vary in further embodiments. The passive components112may extend above the surface of the substrate102. As such they may be mounted outside of the footprint of the spacer layer explained below. Alternatively, the passive components may be positioned on the substrate102so as to fit within the aperture of the spacer layer mounted on the substrate as is also explained below.

In step204, a semiconductor die114may be mounted on a surface of the substrate102. The semiconductor die114may also be positioned on the substrate102so as to fit within the aperture of the spacer layer when the spacer layer is mounted on the substrate. The semiconductor die114may be a controller ASIC. However, die114may be other types of semiconductor die, such as a DRAM or NAND.

FIG. 5shows the semiconductor die114mounted on the substrate102. The semiconductor die114includes die bond pads116, one of which is labeled for example inFIG. 5. The number of die bond pads116shown is for clarity only, and it is understood that there may be more contact pads108and die bond pads116in further embodiments. Moreover, while semiconductor die114is shown with die bond pads116on two sides inFIG. 5, it is understood that semiconductor die114may have die bond pads116on all four sides of the semiconductor die114in further embodiments, for example as shown inFIG. 6. The semiconductor die114may alternatively have die bond pads116on one side or three sides in further examples.

In accordance with the present technology, a spacer layer120may next be mounted to the substrate102in step208. The spacer layer120is formed with an aperture122extending through the spacer layer, between opposed top and bottom major surfaces124a,124bof the spacer layer120. The spacer layer120may be mounted on the substrate102so that the semiconductor die114(and possibly other structures on the surface of substrate102) sit within the aperture122.

It is a feature of the present technology that the spacer layer120may be a semiconductor die formed from a semiconductor wafer. One advantage of this feature is that the spacer layer may be made of the same material as other semiconductor die mounted on top of the spacer layer as explained hereinafter, thereby avoiding thermal mismatch. A further advantage is that the fabrication facilities that make the semiconductor device100typically have tools and processes for handling semiconductor wafers. Thus, formation of the spacer layers120from a semiconductor wafer involves minimal additional cost and processing steps for the fabrication facility.

Referring now toFIGS. 7-10, spacer layers120may be formed from semiconductor wafer300. A semiconductor wafer300may start as an ingot of wafer material which may be formed in step250. In one example, the ingot may be polycrystalline silicon. However, in further embodiments, it is contemplated that the ingot from which the wafers300are formed may be monocrystalline silicon grown according to either a Czochralski (CZ) or floating zone (FZ) process.

In addition to silicon, it is understood that wafer300may be formed of any other semiconductor element or compound including but not limited to Group IV elemental semiconductors, Group IV compound semiconductors, Group VI elemental semiconductors, III-V semiconductors, II-VI semiconductors, I-VII semiconductors, IV-VI semiconductors, V-VI semiconductors, and II-V semiconductors. Additionally, as the wafer300is used to form a mechanical spacer layer120, the spacer layer120may be a variety of materials beyond semiconductor elements or compounds.

In step252, the semiconductor wafer300may be cut from an ingot and polished on both major surfaces to provide smooth surfaces. Wafer300may have a first major surface304(FIG. 8) and an opposite second major surface305(FIG. 9). In step254, a grinding wheel may be applied to the second major surface305to backgrind the wafer300from, for example, 780 μm to 280 μm, though these thicknesses are by way of example only and may vary in different embodiments. This step is shown in dashed lines as this step may be skipped in embodiments. It is also conceivable that the backgrind step254be performed later in the process, for example after the apertures122are cut and removed as explained below.

A layer of die attach film (DAF) may be applied to a surface of the wafer300in step256. The DAF layer will be used to attach the spacer layers120to the substrates102once the spacer layers120are diced from wafer300as explained below.

In step258, the positions of the apertures122to be formed (some of which are numbered inFIGS. 8-10) are aligned to the wafer. For example, the positions of the apertures122may be set so as to align with the known finished positions of the semiconductor die that are to be diced from the wafer. This alignment may be done by a number of different methods. In one example, reference positions may be defined on the wafer300and all positions of semiconductor die and apertures122may be defined in relation to these reference points.

For example, wafer300typically includes a flat310(FIGS. 8-10) for identifying and orienting the crystalline structure of the wafer for processing. The flat310ends at points, referred to as cleave points, where the rounded portion of the wafer300meets the flat310. The first and second major surfaces304,305have cleave points312and314(they are shown flipped with respect to each other in the views ofFIGS. 8 and 9as the wafer300is flipped over in the view ofFIG. 9relative toFIG. 8).

The positions of the semiconductor die as diced may be defined relative to one or both cleave points312,314. Thereafter, the positions of the apertures322may be aligned to the positions of the semiconductor die by positioning them at known distances along the x- and y-axes relative to the cleave points312and/or314. Thus, apertures322may be precisely positioned within each semiconductor die, for example centered within each die when the die are diced from the wafer300.

In step260, apertures122are formed through the wafer300with either the first or second major surfaces304,305facing upwards. The dimensions of the apertures122may vary, depending on the size of the semiconductor die114(and possibly other components) that are to seat within the apertures. In one example including a semiconductor die114having wire bonds extending off of all four sides of the die114as explained below, apertures122may be sized so that there is at least a 250 μm space between the sidewalls of the apertures122and the contact pads108on the substrate102that receive the wire bonds from the die114. These dimensions are by way of example only and may vary. Moreover, the dimensions of the apertures122may be smaller where there are wire bonds extending from less than all four sides of the die114.

In embodiments, the apertures may be spaced apart from each other such that, once the wafer300is diced as explained below, each aperture122is positioned in the same location in the resultant spacer layers120. As noted above, the apertures122may be centered in each spacer layer in one embodiment. Alternatively, apertures122may instead be closer to one edge than the opposed edge along the length and/or width of the spacer layers120in further embodiments. Two examples of this are shown inFIGS. 19 and 20.

The aperture122may be formed by a variety of different technologies. In one example, the apertures122may be formed with a laser306(FIG. 10). The laser306may for example be a high power CO2laser using repetitive short frequency pulses to cut successively deeper through the wafer300and the DAF layer. In one embodiment, the laser wavelength may be between 335 nm and 395 nm, and the pulses may cycle on and off at a frequency of 80 KHz to 130 KHz. It is understood that this wavelength range and frequency range are by way of example only, and one or both may vary above or below these ranges in further embodiments. The wafer300may be mounted on a chuck within a table that controllably translates in the X and Y directions while the laser is held stationary to form the apertures122with desired dimensions. A single laser may be used to form each of the apertures122in the wafer300, or more than one laser may be used simultaneously to improve throughput.

In a further embodiment, the apertures122may be etched out of the wafer300. The apertures may be etched in a variety of different processes, including for example using a liquid etchant, a dry plasma etchant or a vapor etchant. In one example, a photoresist (not shown) is applied across the entire first major surface304(though it may be the second major surface305in further examples). After aligning an aperture mask (not shown) over the photoresist on the first major surface304, the photoresist and aperture mask may be exposed to an ultra violet light. The photoresist is then developed which results in the optical pattern of the aperture mask being transferred as open windows (not shown) in the photoresist. The entire first major surface304of the wafer300is then exposed to a selective etch that cuts the apertures through the wafer300without affecting the photoresist. The photoresist is removed in a stripping process to yield the apertures122through the wafer300.

In one embodiment, the process for etching apertures122may be an anisotropic etch which can result in apertures122having rectangular or approximately rectangular sidewalls. In further embodiments, the process may be an isotropic etch which can result in apertures122having more rounded sidewalls (rounded in a plane parallel to major surfaces304,305, and/or rounded in a cross-sectional view through the wafer300).

After the apertures122are formed, the wafer300may be diced in step262into individual semiconductor die to be used as spacer layers120. The wafer300may be diced using a saw blade in a known dicing process.

In the dicing step, the wafer300may be held on a wafer chuck with the second major surface305including the DAF layer held against the wafer chuck so that the respective semiconductor die remain in position on the chuck after dicing. Thereafter, in step264, a pick and place robot having a first vacuum tip may remove the wafer portions from the interior of the apertures122that were cut as explained above. In further embodiments, it is possible that the material from the interior of the apertures be removed before the wafer300is diced.

In step266a pick and place robot having a second vacuum tip may remove the semiconductor die, now comprising finished spacer layers, from the vacuum chuck and place them on the substrate as explained below. An example of a vacuum tip320for removing the spacer layers120from the vacuum chuck is shown from a bottom view inFIG. 11. The vacuum tip320includes vacuum holes322connected to a negative pressure source. The vacuum tip320also includes an opening324which overlies the aperture122when vacuum tip320picks the spacer layer120from the vacuum chuck. Other configurations of vacuum tip320are contemplated.

FIGS. 12 and 13show top and perspective views of a finished spacer layer120including aperture122. Referring again to the flowchart ofFIG. 3and perspective view ofFIG. 14, a spacer layer120may be mounted to the substrate102in step208by curing the DAF layer. The spacer layer is positioned on the substrate102so that the semiconductor die114is positioned within the aperture.

In embodiments, the semiconductor die114may have a thickness of 46 μm. The die attach film attaching the semiconductor die114may have a thickness of 10 μm. The spacer layer120may have a thickness so that the semiconductor die114, and any wire bonds off of the semiconductor die114, are completely contained within the aperture122(i.e., do not extend above a plane of the top surface124aof the spacer layer120). In embodiments, the spacer layer120may have a thickness of 102 μm, and the DAF layer affixing the spacer layer120to the substrate102may have a thickness of 20 μm. Each of these dimensions may vary in further embodiments with the provision that the semiconductor die114and any wire bond from die114are contained within the aperture122.

In step210, the die bond pads116on semiconductor die114may be electrically coupled to contact pads108on the substrate102via wire bonds118, one of which is numbered inFIG. 14. Wire bonding may be performed by a wire bond capillary (not shown) forming the wire bonds118while extending through the aperture122. The space between the contact pads108and the side walls of the aperture122may be sufficiently large as explained above to allow the capillary to form the wire bonds without contacting the side walls of the aperture122.

It is understood that the semiconductor die114may be electrically coupled to the substrate102using technologies other than wire bonding. For example, semiconductor die114may be a flip-chip which is soldered onto contact pads of the substrate102. As a further example, conductive leads may be printed by known printing processes between the die bond pads and contact pads to electrically couple the semiconductor die114to the substrate102.

It is understood that order of the steps of mounting the semiconductor die114(step204), mounting the spacer layer120(step208) and wire bonding the semiconductor114(step210) may be performed in different orders in further embodiments. For example, the spacer layer may be mounted first, and the semiconductor die114may then be mounted and wire bonded. As a further example, the semiconductor die114may be mounted and wire bonded, and thereafter, the spacer layer120may be mounted.

In step212, the aperture122may be filled with a liquid compound126as shown inFIG. 15. The liquid compound126may be applied as an A-stage compound, and thereafter cured to either a B-stage or C-stage. In one example, the liquid compound126may be an epoxy sold under the product number Dover DE109H from Shenzhen Dover Technology Co., Ltd having a place of business in Shenzhen, China. Other epoxies and compounds may be used. In one embodiment, the liquid compound126may have a coefficient of thermal expansion approximating that of the spacer layer126. This may prevent separation between the liquid compound126and spacer layer120, or cracking of the spacer layer, upon heating of those components for example by the semiconductor die114. The coefficient of thermal expansion of the liquid compound126and spacer layer120may be different in further embodiments.

The liquid compound126may protect the semiconductor die114, and prevent delamination of the memory die stack mounted on the spacer layer120as explained below. In particular, if the aperture122were left open, air in the aperture may heat upon heating of semiconductor die114and expand, thereby possibly delaminating the memory die stack. However, in further embodiments, it is contemplated that liquid compound126be omitted, and the aperture122left open.

In step214, one or more semiconductor die140may be stacked on top of the spacer layer120and liquid compound126as shown inFIGS. 16 and 17. The semiconductor die140may be stacked in stepped configuration. While two such semiconductor die140are shown, there may be a single semiconductor die140or more than two semiconductor die in the die stack in further embodiments. Semiconductor die140may include integrated circuits142functioning for example as memory die and more preferably NAND flash memory die, but other types of semiconductor die are contemplated.

In step216, the semiconductor die140may be wire bonded to contact pads108on the substrate102via wire bonds144in a known wire bonding process, using for example a wire bond capillary (not shown).

After the die stack is formed and wire bonded to contact pads108on the substrate102, the semiconductor device100may be encased within the molding compound150in step220, and singulated from the panel in step224, to form a finished semiconductor device100as seen inFIG. 18. Molding compound150may be a known epoxy such as for example available from Sumitomo Corp. and Nitto Denko Corp., both having headquarters in Japan. Thereafter, the device100may undergo electrical test and burn-in in step226. In some embodiments, the finished semiconductor device100may optionally be enclosed within a lid (not shown) in step228.

The semiconductor device100may be used as an LGA (land grid array) package so as to be used as removable memory within a host device. In such embodiments, contact fingers (not shown) may be formed on a lower surface of the substrate102for mating with pins in a host device upon insertion of the semiconductor device100in the host device. Alternatively, the semiconductor device100may be used as a BGA (ball grid array) package so as to be permanently affixed to a printed circuit board within a host device. In such embodiments, solder balls (not shown) may be formed on contact pads on a lower surface of the substrate102for being soldered onto a printed circuit board of a host device.

The spacer layers120including apertures122allow the semiconductor die114, for example a controller, to be mounted on the surface of the substrate102, while providing a large, flat surface for mounting of additional semiconductor die, for example memory die.

Moreover, forming the spacer layer from a semiconductor wafer provides further advantages. For example, as mentioned above, semiconductor device fabrication facilities typically have resources for handling and processing semiconductor wafers. The vacuum chucks used to hold the wafer300as it is processed, the equipment for applying the die attach film to the surface of wafer300, the wafer dicing equipment to cut the wafer300into respective spacer layers120, and the pick and place robots for transferring the diced spacer layers onto the substrate102all commonly exist in a semiconductor device fabrication facility for handling other semiconductor wafers. This allows easy fabrication of the spacer layers120with little additional cost to the facility.

Additionally, by forming the spacer layers120from a semiconductor wafer, the spacer layers120may be made from the same material as the semiconductor die140. For example, semiconductor die114may generate heat when operating, and this heat may cause the spacer layer120and semiconductor die140to expand. As the spacer layer120and semiconductor die140may be of the same material, they may have the same coefficient of thermal expansion. Thus, when the semiconductor die114heats the spacer layer and semiconductor die on the spacer layer, they will expand to the same degree. It is understood that spacer layer120may be formed of materials other than semiconductor materials. Some of these materials may have a coefficient of thermal expansion which is the same as or similar to semiconductor materials to prevent thermal mismatch.

In the description above, spacer layer120is not processed to include integrated circuits. However, in further embodiments, the spacer layer120may be a semiconductor die with integrated circuits, but one which is not functioning as an electrical component. For example, it may happen that a semiconductor wafer is determined to be defective after forming the integrated circuits, or at any stage in the processing of integrated circuits, for a variety of reasons. Some defects adversely impact the electronic function of the semiconductor die on the wafer, while other defects are catastrophic so that the semiconductor die on the wafer cannot be used for their electronic function.

For example, memory die may be classified in bins, depending on the degree of electronic functionality. Known good die (Bin1) have full electronic functionality, while other memory die (e.g., Bin AA or ZZ) have partial functionality due to some defect, but still may be used as memory die, albeit with reduced storage capacity. Semiconductor die which have electronic functionality (full or partial) are referred to herein as “functioning semiconductor die,” as opposed to completely defective semiconductor die. At present, the yield of semiconductor wafers with completely defective semiconductor die is somewhere around 5%. Given the millions of wafers that are fabricated, this results in a large number of semiconductor wafers and die that are unusable for their electronic function.

In accordance with embodiments of the present technology, instead of discarding wafers with completely defective semiconductor die, the semiconductor die of these wafers may be reclaimed and used as spacer layers120. These semiconductor die are referred to herein as reclaimed semiconductor die.FIG. 19illustrates a completely defective semiconductor die130, andFIG. 20illustrates the same die, used as a reclaimed semiconductor die132.FIGS. 19 and 20illustrate a single semiconductor die from wafer300, but some or all of the remaining semiconductor die on wafer300may also be completely defective and used as reclaimed semiconductor die132. The illustrated reclaimed semiconductor die132includes integrated circuits134and die bond pads136, but due to some catastrophic defect, the reclaimed semiconductor die132is not usable as an electronic component.

Where semiconductor die from a wafer are determined to be completely defective, they may be reclaimed and used as spacer layers120which need not be wire bonded to the substrate102.FIG. 20illustrates a wafer300including a reclaimed semiconductor die132having an aperture122. Apertures122may be formed through the respective reclaimed semiconductor die132of the wafer300as explained above, and the wafer diced into spacer layers120. Reclaimed semiconductor die132may include the unused integrated circuits134when used as spacer layers120. In a further embodiment, the integrated circuits134may be sanded off of a defective wafer before or after formation of the apertures122, and then the wafer diced into spacer layers120and used as explained above. WhileFIGS. 19 and 20show formed integrated circuits134, it is understood that a wafer may be determined to be completely defective at any stage in the fabrication of integrated circuits134, and thereafter reclaimed as spacer layers120.

In embodiments, the wafer as a whole may be determined to be completely defective, and all of the semiconductor die in that wafer may be reclaimed as spacer layers120. However, in further embodiments, after fabrication of the integrated circuits134on the wafer300is completed, it may be determined that some of the semiconductor die are completely defective, while others are functioning semiconductor die. In such an embodiment, the functioning semiconductor die may be used as electronic components in accordance with their proper electronic functionality. On the other hand, those semiconductor die in the wafer300determined to have failed integrated circuits may be reclaimed and used as spacer layers120.

In this embodiment, a wafer map may be developed having a map of the positions of functioning semiconductor die and completely defective semiconductor die. Using the wafer map, apertures122may be formed in the completely defective semiconductor die, while no apertures122are formed in the functioning semiconductor die. As noted above, the positions all die on the wafer are known, and the positions of the apertures (for example for those die to receive apertures) have been aligned to the semiconductor die. Accordingly, using the known positions of completely defective die from the wafer map, and using the known alignment of the apertures122within those semiconductor die, apertures122may be formed in the completely defective semiconductor die using techniques described above. The functioning semiconductor die may be left without apertures. In some embodiments, the functioning semiconductor die may be shielded with a protective layer while the apertures are formed in the completely defective semiconductor die, which protective layer is removed after formation of the apertures.

After formation of the apertures122in the completely defective die, the wafer may be diced as explained above. Upon dicing of the wafer, a pick and place robot may remove the functioning semiconductor die for use as electronic components, and a pick and place robot may remove the reclaimed semiconductor die for use as spacer layers120. In a further alternative embodiment, the functioning semiconductor die may be removed from the wafer before apertures are formed in the completely defective die. In this embodiment, the wafer may be diced, and then, using the known positions of functioning semiconductor die, a pick and place robot may remove the functioning semiconductor die. Thereafter, the apertures may be formed in the remaining, completely defective semiconductor die as explained above. A pick and place robot may then remove those die for use as spacer layers120. Using the reclaimed semiconductor die132of the above-described embodiments, spacer layers120may be formed with no additional material costs and minimal additional processing costs.

In embodiments described above, a single semiconductor die114such as a controller may be mounted to the substrate102, and then enclosed within the aperture122of the spacer layer120. However, it is understood that different semiconductor die (including for example DRAM, NAND or other smaller memory die) and/or other electronic components may be mounted on the substrate and positioned within aperture122in further embodiments. As noted, other semiconductor die and/or other components may be mounted within the aperture122in addition to semiconductor die114in further embodiments.

FIGS. 23-34relate to an alternative embodiment of the present technology.FIGS. 23-26show a conventional state of the art. In particular, a conventional, generally rectangular spacer layer50may be mounted on the substrate26. As noted above, the substrate26may also include a substrate-mounted semiconductor die24such as a controller. As seen for example in prior artFIG. 24, the width of the conventional spacer layer50is limited by the semiconductor die24and its wire bonds to the substrate.

The design of this conventional spacer layer50is problematic in that, when semiconductor die22such as memory die are mounted on top of the spacer layer50, the bottommost semiconductor die22overhangs the edge of the spacer layer50by a distance L, as shown in prior artFIG. 26. As loads are exerted downward on the die stack, such as for example during encapsulation, this overhang of the bottommost semiconductor die creates a cantilevered effect on the bottom most semiconductor die. This cantilevered effect generates stresses in the bottommost semiconductor die at the line where it overhangs the spacer50, which stresses can damage or crack the bottommost semiconductor die.

FIG. 27illustrates a substrate102including vias104, traces106contact pads108and passive components112as described above. Substrate102further includes a semiconductor die114surface mounted to the substrate102as described above.FIG. 27further shows a spacer layer180according to a further embodiment of the present technology. Spacer layer180includes a notch182formed in one edge of the spacer layer180defining arm portions184extending from a base portion186.

With the exception of having a notch182instead of an aperture122, spacer layer180may be similar in all other respects to any of the embodiments of spacer layer120described above. As described above, spacer layer180and be formed of semiconductor material, such as for example from the wafer300described above, in accordance with aspects of the present technology.

As shown inFIGS. 28 and 29, one or more semiconductor die140may be stacked on top of the spacer layer180. A single semiconductor die is shown inFIGS. 28 and 29, but maybe more than one in further embodiments.FIG. 30shows embodiment including eight semiconductor die140. The semiconductor die140may be stacked in stepped configuration. As above, semiconductor die140may include integrated circuits functioning for example as memory die and more preferably NAND flash memory die, but other types of semiconductor die are contemplated.

As shown inFIG. 29, the footprint of the spacer layer180(i.e., the length and width of the spacer layer180without the notch182) may be the same as the footprint of the bottommost semiconductor die140. Thus, the cantilever effect and stress found in prior art designs is alleviated by spacer layer180.

FIG. 30illustrates a finished semiconductor package100fabricated using a spacer layer180. Semiconductor die140added on top of the spacer layer180are shown wire bonded to the substrate102and the semiconductor device100is encapsulated in a molding compound150, all as described above.

FIG. 31illustrates a wafer300including notches182which may be cut therefrom according to any of the embodiments described above with respect to the manner in which aperture122is cut.FIG. 32illustrates an enlarged portion of wafer300showing two semiconductor die with notches182cut at an edge of the semiconductor die.

Given that the notches182are formed in the edge of respective semiconductor die, two notches182may be cut in a single cutting process, where the notch in a first semiconductor die is at the bottom of the die, and the notch in a below-adjacent semiconductor die is at a top of the die. Such an embodiment is shown in the views ofFIGS. 33 and 34.FIG. 33illustrates a wafer300where cuts can be made to form the notches in two adjacent die at the same time.FIG. 34illustrates an enlarged portion of way for300showing a first semiconductor die having a notch182in a bottom portion of the die, and a second semiconductor die having a notch182in a top portion of the die. This process allows for more efficient cutting of the notches through the wafer300.

In summary, an example of the present technology relates to spacer layer for a semiconductor device, the spacer layer comprising: a first major surface; a second major surface opposite the first major surface; and one of an aperture and a notch formed through the spacer layer between the first and second major surfaces; wherein a material from which the spacer layer is formed is from a group consisting of a monocrystalline semiconductor element or compound and a polycrystalline semiconductor element or compound.

In another example, the present technology relates to semiconductor device, comprising: a substrate; a first semiconductor die mounted to a surface of the substrate; and a second semiconductor die forming a spacer layer mounted to the surface of the substrate, the spacer layer including an aperture through first and second major opposed surfaces, the first semiconductor die fitting within the aperture of the spacer layer.

In a further example, the present technology relates to a semiconductor device, comprising: a substrate; a first semiconductor die mounted directly to a surface of the substrate; a second, reclaimed semiconductor die comprising at least a portion of an integrated circuit, the reclaimed semiconductor die having a first major surface mounted directly to the surface of the substrate, and the reclaimed semiconductor die including an aperture through the first major surface and a second major surface opposed to the first major surface, the first semiconductor die fitting within the aperture in the reclaimed semiconductor die; and a group of one or more third semiconductor die mounted on the reclaimed semiconductor die.

In another example, the present technology relates to a semiconductor device, comprising: a substrate; a first semiconductor die mounted to a surface of the substrate; and a second semiconductor die forming a spacer layer mounted to the surface of the substrate, the spacer layer including a notch formed in an edge of the second semiconductor die, through first and second major opposed surfaces, the first semiconductor die fitting at least partially within the notch of the spacer layer.