Display substrate and method of manufacturing the same

A display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 2011-0079612, filed on Aug. 10, 2011, which is incorporated herein by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Exemplary embodiments of the present invention relate to a display substrate and a method of manufacturing the display substrate. More particularly, exemplary embodiments of the present invention relate to a display substrate used for a display apparatus and a method of manufacturing the display substrate.

2. Discussion of the Background

A display panel typically includes a first display substrate on which a switching element to drive a pixel, signal lines, and a pixel electrode are formed. The display panel also includes a second display substrate facing the first display substrate, and a display element disposed between the first and second display substrates. The display element may be a liquid crystal layer capable of controlling a transmission rate of light beams passing therethrough based on an applied control voltage.

A display apparatus these days is required to provide faster signal transmission with a higher resolution. This trend makes a resistance-capacitance (“RC”) signal delay in the display apparatus even more significant. To cope with the RC signal delay issue, a display apparatus may be fabricated to have thicker signal lines and electrodes. However, at the same time, an area that the signal lines and the switching elements occupy should be also reduced to increase an aperture ratio of the display apparatus.

In order to reduce the RC signal delay, the thickness of the signal lines and the electrodes should be increased while, at the same time, the widths of the signal lines and the electrodes are decreased to reduce the occupied area. However, thicker signal lines and electrodes make it harder to manufacture thin films uniformly on the substrate in the subsequent manufacturing processes.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a display substrate capable of increasing reliability in manufacturing a metal pattern.

Exemplary embodiments of the present invention also provide a method of manufacturing the display substrate.

As an aspect of the present invention, an exemplary display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate.

As another aspect of the present invention, an exemplary method of manufacturing a display substrate includes forming a first metal pattern on a base substrate, the first metal pattern comprising a first signal line and a first electrode electrically connected to the first signal line; and forming a buffer pattern at a corner between a sidewall surface of the first metal pattern and the base substrate.

According to the exemplary embodiments of the present invention, a buffer pattern is formed at a corner formed between a sidewall surface of a first metal pattern and a base substrate, so that a second metal pattern is less likely to be disconnected at the corner in the subsequent manufacturing processes. Thus, the first metal pattern having is formed with a relatively narrow width and a relatively thick thickness, so that a RC signal delay may be reduced and reliability of manufacturing the second metal pattern may be improved by the buffer pattern.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. In contrast, It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “beneath” another element, it can be directly beneath the other element or intervening elements may also be present. Meanwhile, when an element is referred to as being “directly beneath” another element, there are no intervening elements present.

FIG. 1is a plan view that illustrates a display substrate according to an exemplary embodiment of the present invention.FIG. 2is a cross-sectional view of the display substrate taken along a line I-I′ ofFIG. 1.

Referring toFIGS. 1 and 2, a display substrate101may include a first metal pattern MP1, a buffer pattern BP, a first insulating layer130, an active pattern AP, a dummy pattern DP, a second metal pattern MP2, a second insulating layer160and a pixel electrode PE, on a base substrate110.

The first metal pattern MP1may include a first signal line GL along a certain direction and a first electrode GE. For example, the first signal line GL may be a gate line to apply a gate driving signal and the first electrode GE may be a gate electrode connected to the gate line. A thickness of the first metal pattern MP1may be greater than or equal to about 5,000 Å. When the thickness of the first metal pattern MP1is less than about 5,000 Å, patterns such as the first insulating layer130and/or the second metal pattern MP2may be slightly and stably formed on the first metal pattern MP1without including the buffer pattern BP. In contrast, when the thickness of the first metal pattern MP1is greater than or equal to about 5,000 Å, the patterns may be difficult to be stably formed on the first metal pattern MP1. Therefore, when the thickness of the first metal pattern MP1is greater than or equal to about 5,000 Å, the buffer pattern BP may be more effective. A cross-sectional shape of the first metal pattern MP1may be a trapezoid whose width decreases as it goes upwards from a surface of the base substrate110. For example, an area of a lower surface of the first metal pattern MP1in contact with the base substrate110may be greater than an area of an upper surface of the first metal pattern MP1opposite to the lower surface.

The buffer pattern BP may be disposed at a corner formed between a sidewall surface of the first metal pattern MP1and the base substrate110. The buffer pattern BP may be disposed along a boundary of the first metal pattern MP1. For example, the buffer pattern BP may be disposed along the boundaries of the first signal line GL and the first electrode GE. Thus, the buffer pattern BP may have a shape substantially the same as the boundary of the first metal pattern MP1when viewed in a plan. The buffer pattern BP may include a silsesquioxane-based compound. Compared to a thin film including silicon nitride or silicon oxide, the buffer pattern BP including a silsesquioxane may reduce deterioration in a characteristic of the buffer pattern BP at a relatively high temperature over about 300°.

A relation between the buffer pattern BP and the first electrode GE is substantially the same as a relation between the buffer pattern BP and the first signal line GL. Thus, any further explanation concerning the relation between the buffer pattern BP and the first signal line GL will be omitted.

In the exemplary embodiment, the buffer pattern BP is in contact with the first metal pattern MP1and the base substrate110. For example, the buffer pattern BP is in contact with a sidewall surface of the first electrode GE and the base substrate110. An inclination of the sidewall surface of the first electrode GE may be decreased by the buffer pattern BP. The buffer pattern BP will be illustrated in detail with reference toFIGS. 3A and 3B.

The first insulating layer130may be disposed on the base substrate110on which the first metal pattern MP1and the buffer patter BP are disposed. A lower surface of the first insulating layer130is in contact with the first metal pattern MP1and the buffer pattern BP.

The active pattern AP may overlap with the first electrode GE and be disposed on the first insulating layer130. The active pattern AP may include a semiconductor layer140aand an ohmic contact layer140b. Alternatively, the semiconductor layer140amay include, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, and so on.

The second metal pattern MP2may include a second signal line DL crossing the first signal line GL, a second electrode SE partially overlapping with the first electrode GE and a third electrode DE partially overlapping with the first electrode GE. The second signal line DL may be a data line to apply a data signal, the second electrode SE may be an input electrode connected to the data line, and the third electrode DE may be an output electrode spaced apart from the input electrode. In the second metal pattern MP2, the active pattern AP may be disposed under the second electrode SE and the third electrode DE. The dummy pattern DP having a multilayered structure substantially the same as the active pattern AP may be disposed under the second signal line DL.

A thin film transistor SW may include the first electrode GE of the first metal pattern MP1, the second electrode SE of the second metal pattern MP2, the third electrode DE of the second metal pattern MP2and the active pattern AP. The thin film transistor SW is electrically connected to the pixel electrode PE. The thin film transistor SW is electrically connected to both of the first signal line GL and the second signal line DL. Thus, both of the first signal line GL and the second signal line DL are electrically connected to the pixel electrode PE.

Due to the existence of the buffer pattern BP, the second signal line DL may stably cross the first signal line GL. Furthermore, the second electrode SE may stably extend at a first edge portion of the first electrode GE and the third electrode DE may stably extend at a second edge portion of the first electrode GE where each of the second electrode SE and the third electrode DE partially overlaps with the first electrode GE. For example, by the buffer pattern BP, the second metal pattern MP2may be stably disposed on the base substrate110on which the first metal pattern MP1is disposed, which means that by the buffer pattern BP, the second metal pattern MP2may stably cover the corner of the first metal pattern MP1.

The second insulating layer160may be disposed on the base substrate110on which the second metal pattern MP2is disposed, and may include a contact hole CNT through which the third electrode DE is partially exposed. The pixel electrode PE is electrically connected to the third electrode DE via the contact hole CNT.

Although not shown in the drawings, the display substrate101may further include a planarizing layer disposed on the second insulating layer160. In this case, the contact hole CNT may be formed in both of the second insulating layer160and the planarizing layer. The pixel electrode PE may be disposed on the planarizing layer.

The pixel electrode PE is disposed on the second insulating layer160. The pixel electrode PE is in contact with the third electrode DE and is electrically connected to the first signal lines GL and the second signal lines DL via the thin film transistor SW.

FIGS. 3A and 3Bare enlarged cross-sectional views of the display substrate that illustrate a portion ‘A’ inFIG. 2to explain the inclined patterns inFIG. 2.

Referring toFIG. 3A, the buffer pattern BP is disposed at a corner formed between a surface SF1of the base substrate110and a sidewall surface SWP of the first electrode GE. The buffer pattern BP is in contact with the surface SF1of the base substrate110and the sidewall surface SWP. Thus, the buffer pattern BP may have a structure to fit into the corner. For example, the buffer pattern BP may have a triangular prism shape to fit into the corner.

For example, the buffer pattern BP may include a first side portion P1, a second side portion P2and an inclined portion P3. The first side portion P1faces the sidewall surface SWP. The second side portion P2is connected to the first side portion P1and faces the surface SF1of the base substrate110.

The side portion P3connects the first side portion P1to the second side portion P2, and has an inclination less than the sidewall surface SWP with respect to the surface SF1of the base substrate110. An inclined angle θais an acute angle of the inclined portion P3inclined with respect to the surface SF1of the base substrate110. An inclined angle θgis an acute angle of the sidewall surface SWP inclined with respect to the surface SF1of the base substrate110. The inclined angle θais less than the inclined angle θg. The inclination of the inclined portion P3may be uniform across the inclined portion P3. For example, the inclined portion P3may be an inclined plane having a uniform inclination with respect to the surface SF1of the base substrate110. Hereinafter, the term “inclined angle” is defined with respect to the surface SF1of the base substrate110.

When the first side portion P1, the second side portion P2and the inclined portion P3are connected to each other to form a triangle cross-section, the inclined angle θaof the inclined portion P3is substantially the same as an angle between the second side portion P2and the inclined portion P3. When the buffer pattern BP is in contact with the base substrate110and the sidewall surface SWP, an acute angle θbof the sidewall surface SWP inclined with respect to a reference line extending along the inclined portion P3may be at least greater than about 0°. Since the inclined angle θaof the inclined portion P3is substantially the same as a difference between the inclined angle θgof the sidewall surface SWP and the acute angle θb, the inclined angle θaof the inclined portion P3is less than the inclined angle θbof the sidewall surface SWP. When the inclined angle θaof the inclined portion P3is substantially about 0°, the buffer pattern BP may be not substantially formed, and thus the inclined angle θais preferably greater than about 0°. Further, when the inclined angle θaof the inclined portion P3is greater than about 50°, the buffer pattern BP may be unnecessarily formed on a surface of the first electrode GE parallel to a surface of the base substrate110as well as the sidewall surface SWP. Furthermore, when the inclined angle θaof the inclined portion P3is greater than about 50°, the inclined angle θaof the inclined portion P3may be not greatly different from the inclined angle θgof the sidewall surface SWP. When the inclined angle θaof the inclined portion P3is less than or equal to about 50°, the buffer pattern BP may further mitigate the effect of the inclined angle θgof the sidewall surface SWP. Thus, the inclined angle θaof the inclined portion P3may be greater than about 0° and less than or equal to about 50°.

A protruded length Ltis defined as a length of the buffer pattern BP protruding from an edge between the first sidewall surface P1and the second sidewall surface P2. When the protruded length Ltis too long, an aperture ratio may be decreased by the buffer pattern BP or the buffer pattern BP may not mitigate the effect of the inclined angle θgof the sidewall surface SWP. Thus, a difference between the inclined angle θaof the inclined portion P3and the inclined angle θgof the sidewall surface SWP may be in a range of about 10° to about 40°. A difference between the inclined angle θaand the inclined angle θgmay be substantially the same as the acute angle θbof the sidewall surface SWP inclined with respect to the reference line extending along the inclined portion P3.

A height Tbof the buffer pattern BP is a distance between the surface SF1of the base substrate110and a peak of the buffer pattern BP. The height Tbmay be substantially the same as or lower than a height Tgof the first electrode GE. The height Tgof the first electrode GE is a distance from the surface SF1of the base substrate110to an upper surface SF2of the first electrode GE. The upper surface SF2of the first electrode GE is a surface opposite to the surface SF1of the base substrate110. However, the height Tbof the buffer pattern BP may depend on the protruded length Ltof the buffer pattern BP. Thus, the height Tbof the buffer pattern BP may be greater than about 0% and less than or equal to about 80% of the height Tgof the first electrode GE, to control the protruded length Ltof the buffer pattern BP.

As described above, the buffer pattern BP is disposed at the corner in the exemplary embodiment, and thus the effect of the inclined angle θgof the sidewall surface SWP may be mitigated by the acute angle θbof the sidewall surface SWP inclined with respect to a reference line extending along the inclined portion P3. Accordingly, the effect of the inclination of the sidewall surface SWP may be distributed between the inclined angle θaof the inclined portion P3and the acute angle θbformed by the reference line and the sidewall surface SWP, and thus the potentially adverse impact of a stepped portion formed by the base substrate110and the upper surface SF2of the first electrode GE may be diminished.

Referring toFIG. 3B, the buffer pattern BP may include a plurality of inclinations at the inclined portion P3. In addition, the protruded length Ltof the buffer pattern BP, a height Tbof the buffer pattern BP, the height tgof the first electrode GE and the inclined angle θgof the sidewall surface SWP are substantially the same as described inFIG. 3A, and thus any repetitive descriptions will be omitted.

The inclination of the inclined portion P3may increase from the surface SF1of the base substrate110toward the sidewall surface SWP. In that case, the inclined portion P3has a concave shape, around a position in which the first side portion P1and the second side portion P2cross each other.

For example, an inclined angle θ1of the inclined portion P3at a first point, which is the farthest from the sidewall surface SWP, is a tangential angle of the first point inclined with respect to the surface SF1of the base substrate110. An inclined angle θnof the inclined portion P3at second first point, which is the farthest from the base substrate110, is a tangential angle of the second point inclined with respect to the surface SF1of the base substrate110. The inclined angle θ1is less than the inclined angle θn. An inclined angle θkof the inclined portion P3at a third point, which is somewhere between the first and the second points, is in a range between the inclined angle θ1of the first point and the inclined angle θn of the second point.

An average of the inclined angles of tangent lines at various points of the inclined portion P3with respect to the surface SF1of the base substrate110may be greater than about 0° and less than or equal to about 50° considering the protruded length Ltof the buffer pattern BP.

As described above, the buffer pattern BP may be formed at the corner to mitigate the effect of the inclination of the sidewall surface SWP by the inclination of the inclined portion P3, so that the impact of a stepped portion formed by the base substrate110and the upper surface SF2of the first electrode GE may be diminished. In addition, the inclined portion P3may include a concave portion to gradually decrease the stepped portion.

FIGS. 4A,4B and4C are cross-sectional views that illustrate a method of manufacturing a display substrate inFIG. 2.

Referring toFIG. 4Atogether withFIG. 1, the first metal pattern MP1including the first electrode GE is formed on the base substrate110. The first metal pattern MP1may be formed by forming a first metal layer on the base substrate110and patterning the first metal layer. A thickness of the first metal layer may be about 5,000 Å.

A coating layer120is formed on the base substrate110on which the first metal pattern MP1has been formed. The coating layer120is formed throughout the base substrate110to cover the first metal pattern MP1.

In order to form the coating layer120, a coating material may be dropped on the base substrate110and the coating material is slit-coated. Alternatively, the coating layer120may be formed using a spin-coating or both of slit-coating and the spin-coating. The coating material may include a silsesquioxane-based compound. To fill the corner between the first metal pattern MP1and the base substrate110with the coating material sufficiently, a viscosity of the silsesquioxane-based compound may be in a range of 1 cP to 5 cP.

The coating layer120has a first thickness t1on the surface of the base substrate110and a second thickness t2on an upper surface of the first metal pattern MP1. The upper surface of the first metal pattern MP1is the surface at the opposite side of the base substrate110. In this case, the first thickness t1may be substantially the same as the second thickness t2. A maximum thickness t3of the coating layer120formed at the corner may be greater than the first and second thicknesses t1and t2. The maximum thickness t3may be defined as a length from the corner between the first and second side portions P1and P2to the surface of the coating layer120perpendicular to the surface of the coating layer120. When the coating layer120is formed by chemical vapor deposition (CVD), the thickness of the coating layer120is formed with a uniform thickness in general, so that the maximum thickness t3tends to be greater than the first and second thicknesses t1and t2. In such case, the coating layer120may be formed by the spin-coating or the slit-coating.

Thereafter, the coating layer120is partially removed by a dry-etching. For example, the coating layer120may be etched using an etching gas including sulfur fluoride (SF6) and nitrogen (N2). During an anisotropic dry-etching, the coating layer120becomes thinner. The dry-etching is continued until the coating layer120is removed to expose the upper surface of the first metal pattern MP1and the surface of the base substrate110. Alternatively, the coating layer120may be partially removed by an ashing process using, for example, an oxygen gas.

Since the maximum thickness t3of the coating layer120formed at the corner tends to be greater than the first and second thicknesses t1and t2, the coating layer120may partially remain at the corner although the upper surface of the first metal pattern MP1and the surface of the base substrate110are exposed. Thus, the buffer pattern BP is formed as illustrated inFIG. 2.

Referring toFIG. 4B, the first insulating layer130, the ohmic contact layer140a, the semiconductor layer140band a second metal layer150are sequentially formed on the base substrate110on which the buffer pattern BP has been formed.

The first insulating layer130formed directly on the first metal pattern MP1has only to cover the stepped portion formed by the first metal pattern MP1and the surface of the base substrate110, whereas the second metal layer150should cover a stepped portion formed by the semiconductor layer140band the surface of the base substrate110as well. When the metal pattern MP1is formed on the base substrate110with a thickness greater than about 5,000 Å, the stepped portion covered by the second metal layer150may be excessively thick. In the present exemplary embodiment, the buffer pattern BP is formed before the second metal layer150is formed, so that the second metal layer150is deposited on both a flat area and a stepped area at a substantially uniform rate during the deposition process of the second metal layer150. Thus, the second metal layer150is substantially uniformly deposited on the stepped area compared to the flat area, and a density of the second metal layer150is uniformed maintained on both areas.

Thereafter, a photoresist pattern200is formed on the base substrate on which the second metal layer150has been formed. The photoresist pattern200includes a first thickness portion210and a second thickness portion220thinner than the first thickness portion210. The first thickness portion210is formed on an area where the second metal pattern MP2has been formed and the second thickness portion220is formed on a separate area between the second electrode SE and the third electrode DE.

During a first etching process, the second metal layer150, the ohmic contact layer140band the semiconductor layer140bare etched using the photoresist pattern200as an etch-stopping layer.

Referring toFIG. 4Ctogether withFIG. 2, the second thickness portion220of the photoresist pattern200is removed to form a residual photo pattern201. The residual photo pattern201is formed on an area where the second metal pattern MP2has been formed. The second metal layer150and the ohmic contact layer140bin the separate area are secondly etched using the residual photo pattern201as an etch-stopping layer. Thus, the second metal pattern MP2, the active pattern AP and the dummy pattern DP are formed.

Thereafter, the residual photo pattern201is removed to form the thin film transistor SW, the first signal lines GL and the second signal lines DL on the base substrate110.

The second insulating layer160is formed on the base substrate110on which the second metal pattern MP2has been formed, and the second insulating layer160formed on the third electrode DE is partially removed, so that the contact hole CNT is formed through the second insulating layer160.

The pixel electrode PE is formed on the base substrate110on which the contact hole CNT has been formed. For example, the pixel electrode PE may include indium zinc oxide (IZO) and indium tin oxide (ITO).

As described above, the buffer pattern BP is disposed at the corner, and the impact of the inclination of the sidewall surface SWP of the first metal pattern MP1may be mitigated by the inclination of the inclined portion P3of the buffer pattern BP. Thus, the impact of a stepped portion formed by the base substrate110and the first metal pattern MP1may be diminished, so that the second metal layer150may be formed with a uniform thickness throughout the base substrate110. For example, when the thickness of the first metal pattern MP1is greater than or equal to about 5,000 Å or the second metal layer150is formed on the base substrate110on which the first insulating layer120, the semiconductor layer140aand the ohmic contact layer140bhave been formed, the impact of a stepped portion may be diminished further by the buffer pattern BP. Thus, reliability in forming the second metal layer150and in manufacturing the second metal pattern MP2is increased and thus reliability of the display substrate101may be more increased.

In the present exemplary embodiment as illustrated inFIG. 1 to 4, a bottom gate type structure in which the first metal pattern MP1is a gate pattern and the second metal pattern MP2is a data pattern has been disclosed. Alternatively, in a top gate type structure in which a data line, a source electrode and a drain electrode are formed on the base substrate110and a gate electrode is formed on both of the source electrode and the drain electrode, a pattern having a structure substantially the same as illustrated inFIG. 3Aor3B may be formed in sidewall surfaces of each of the data line, the source electrode and the drain electrode

FIG. 5is a plan view that illustrates a display substrate according to another exemplary embodiment of the present invention.

A plan view of a display substrate102according to the present exemplary embodiment is substantially the same as the plan view of the display substrate as illustrated inFIG. 1. In addition, a cross-sectional view of the display substrate102according to the present exemplary embodiment is substantially the same as the cross-sectional view of the display substrate101as illustrated inFIG. 2except that the display substrate102further includes the capping pattern CP. Thus, the display substrate102according to the present exemplary embodiment will be described referring toFIG. 5together withFIGS. 1 and 2and any repetitive descriptions will be omitted.

Referring toFIG. 5together withFIGS. 1 and 2, the display substrate102includes a first metal pattern MP1, a capping pattern CP, a buffer pattern BP, a first insulating layer130, an active pattern AP, a dummy pattern DP, a second metal pattern MP2, a second insulating layer160and a pixel electrode which are formed on the base substrate110.

The capping pattern CP may be disposed at a corner formed between a sidewall surface of the first metal pattern MP1and the base substrate110. The first metal pattern MP1may include a first electrode GE and a first signal line GL. The capping pattern CP is in contact with each of the sidewall surface of the first metal pattern MP1and the surface of the base substrate110. The capping pattern CP may have a uniform thickness. Due to the capping pattern CP, the likelihood of a metallic component of the first metal pattern MP1being diffused into the buffer pattern BP in forming the buffer pattern BP may be reduced. The capping pattern CP may include silicon nitride (SiNx) or silicon oxide (SiO2).

The buffer pattern BP is formed on the capping pattern CP. For example, the buffer pattern BP may be disposed on the capping pattern CP on the base substrate110and the capping pattern CP on the sidewall surface. Thus, the capping pattern CP is disposed between the base substrate110and the buffer pattern BP. In addition, the capping pattern CP is disposed between the first metal pattern MP1and the buffer pattern BP. Hereinafter, referring toFIGS. 6A and 6B, the buffer pattern BP and the capping pattern CP are illustrated in detail.

Referring toFIG. 6A, the thickness of the capping pattern disposed on the base substrate110is substantially the same as the thickness of the capping pattern CP in contact with the sidewall surface SWP of the first electrode GE. In addition, the thickness of the capping pattern CP disposed at a corner between the sidewall surface SWP of the first electrode GE and the base substrate110is substantially the same as the thickness of the capping pattern CP in contact with the sidewall surface SWP of the first electrode GE. Thus, the thickness of the capping pattern CP is substantially uniform. Since the thickness of the capping pattern CP is substantially uniform, the inclined angle θgof the first electrode GE may be less decreased by the capping pattern CP although the capping pattern CP is formed before the buffer pattern BP has been formed.

The capping pattern CP partially covers the sidewall surface SWP of the first electrode GE. Alternatively, the capping pattern CP may completely cover the sidewall surface SWP and expose an upper surface of the first electrode GE depending on manufacturing conditions.

Each of a first side portion P1and a second side portion P2of the buffer pattern BP is in contact with the capping pattern CP. The inclined portion P3of the buffer pattern BP connects the first side portion P1to the second side portion P2. The inclined portion P3is inclined with respect to a surface of the base substrate110by a certain angle. The inclined angle θaof the inclined portion P3is less than the inclined angle θgof the first electrode GE. A buffer pattern BP illustrated inFIG. 6Ais substantially the same as the buffer pattern BP as illustrated inFIG. 3A. Thus, any repetitive descriptions will be omitted. However, since the buffer pattern BP is formed on the capping pattern CP, a protruded length Ltof the buffer pattern BP is decided considering the thickness tcof the capping pattern CP.

Referring toFIG. 6B, both the capping pattern CP and the buffer pattern BP may have a structure as illustrated inFIG. 6B. The inclined portion P3of the buffer pattern BP has a concave shape. The buffer pattern BP is disposed on the capping pattern CP. A shape of the buffer pattern BP is substantially the same as the shape of the buffer pattern BP as illustrated inFIG. 3B. A relation between the buffer pattern BP and the capping pattern CP is substantially the same as that illustrated inFIG. 6A. Thus, any repetitive descriptions will be omitted.

FIG. 7is a cross-sectional view that illustrates a method of manufacturing the display substrate illustrated inFIG. 5.

A method of manufacturing a display substrate according to the present exemplary embodiment is substantially the same as the method as illustrated with reference toFIGS. 4A to 4Cexcept that the method further includes forming the capping pattern CP before forming the first insulating layer130. Thus, in the method of manufacturing the display substrate according to the present exemplary embodiment, forming the first metal pattern MP1, the capping pattern CP and the buffer pattern BP are explained with reference toFIG. 7, and the processes subsequent to forming the first metal pattern MP1, the capping pattern CP and the buffer pattern BP are substantially the same as the processes as illustrated inFIGS. 4B and 4Cand thus any repetitive descriptions will be omitted.

Referring toFIG. 7, the first metal pattern MP1including the first electrode GE is formed on the substrate. Thereafter, a capping layer CP and a coating layer120are sequentially formed on the base substrate110on which the first metal pattern MP1has been formed.

The capping layer CL may be formed by deposition using plasma. For example, the capping layer CL may be formed by chemical vapor deposition (CVD). The capping layer CL may be formed with a uniform thickness on the base substrate110on which the first metal pattern MP1has been formed.

Thereafter, a coating material is slit-coated on the base substrate110on which the capping layer CL has been formed to form the coating layer120. The coating layer120formed at a corner between the first metal pattern MP1and the base substrate110may be thicker than the coating layer120formed on the surface of the base substrate110MP1or the coating layer120formed on the upper surface of the first metal pattern MP1.

Referring toFIGS. 5 and 7, the base substrate110on which the capping layer CL and the coating layer120have been formed is dry-etched using an etching gas. In dry-etching, the capping layer CL and the coating layer120formed on the surface of the base substrate110or the upper surface of the first metal pattern MP1are removed by the etching gas, and the coating layer120is partially remained on the corner. Thus, the buffer pattern BP is formed and the capping layer CL covered by the buffer pattern BP partially remains to form the capping pattern CP.

Thereafter, the first insulating layer130, the active pattern AP, the dummy pattern DP, the second metal pattern MP2, the second insulating layer160and the pixel electrode PE are sequentially formed on the base substrate110on which the first metal pattern MP1, the capping pattern CP and the buffer pattern BP have been formed.

As described above, the impact of the inclined angle θgof the first metal pattern MP1is mitigated by the buffer pattern BP. The capping pattern CP is formed before forming the buffer pattern BP. This reduces the likelihood of a metallic component of the first metal pattern MP1being diffused into the buffer pattern BP.

FIG. 8is a cross-sectional view that illustrates a display substrate according to another exemplary embodiment of the present invention.

The plan view of a display substrate103according to the present exemplary embodiment is substantially the same as that as illustrated inFIG. 1. In addition, the cross-sectional view of the display substrate according to the present exemplary embodiment is substantially the same as the structure of the display substrate102as illustrated inFIG. 5except that a capping layer CL is formed throughout a base substrate110unlike the capping pattern CP. Thus, any repetitive descriptions will be omitted.

Referring toFIG. 8, the display substrate103may include a first metal pattern MP1, the capping layer CL, a buffer pattern BP, a first insulating layer130, an active pattern AP, a dummy pattern DP, a second metal pattern MP2, a second insulating layer160and a pixel electrode PE. The display substrate103according to the present exemplary embodiment as illustrated inFIG. 8is formed throughout the base substrate110on which the first metal pattern MP1has been formed except that the capping layer CL is formed throughout the base substrate110. The capping layer CL covers a sidewall surface of the first metal pattern MP1and an upper surface of the first metal pattern MP1. The thickness of the capping layer CL is substantially uniform. Due to the capping layer CL, the likelihood of a metallic component of the first metal pattern MP1being diffused into the buffer pattern BP is reduced. The capping layer CL is substantially the same as the capping pattern CP as illustrated inFIG. 5except that the entire upper surface of the first metal pattern MP1and the surface of the base substrate110are covered. Thus, any repetitive descriptions will be omitted.

For example, when the first metal pattern MP1includes copper (Cu), the capping layer CL may include silicon nitride (SiNx). In addition, when the first metal pattern MP1includes aluminum (Al), the capping layer CL may include silicon oxide (SiO2) and silicon nitride (SiNx). The buffer pattern BP is formed on the capping layer CL.

A method of manufacturing the display substrate103according to the present exemplary embodiment as illustrated inFIG. 8is substantially the same as the method of manufacturing the display substrate102as illustrated inFIG. 7except that the capping layer CL is not etched in etching the coating layer120. Thus, any repetitive descriptions will be omitted. Referring toFIG. 8together withFIG. 7, when the etching gas is provided to the base substrate110on which the capping layer CL and the coating layer120have been formed, the coating layer120formed upper than the capping layer CP is first etched. The coating layer120formed on the upper surface of the first metal pattern MP1and on the surface of the base substrate110is removed, and the etching process is finished when the coating layer120partially remains on the corner between the first metal pattern MP1and the base substrate110. Thus, the buffer pattern BP may be formed on the capping layer CL. The capping layer CL is removed by the etching gas by a certain thickness, so that the capping layer CL may finally have a thickness smaller than an initial thickness of the capping layer CL formed under the coating layer120.

Thereafter, the insulating layer130, the active pattern AP, the dummy pattern DP, the second metal pattern MP2, the second insulating layer160and the pixel electrode PE are sequentially formed on the base substrate110on which the first metal pattern MP1, the capping pattern CP and the buffer pattern BP have been formed.

As described above, the impact of the inclined angle θgof the first metal pattern MP1is mitigated by the buffer pattern BP, and the capping layer CL is formed before forming the buffer pattern BP. This reduces the likelihood of a metallic component of the first metal pattern MP1being diffused into the buffer pattern BP.

FIG. 9is a cross-sectional view that illustrates a display substrate according to another exemplary embodiment of the present invention.

Referring toFIG. 9, a display substrate104may include a first metal pattern, a second metal pattern, a second insulating layer160and a pixel electrode PE formed on the base substrate110. The first metal pattern may include an active pattern AP, a data line DL, a source electrode SE and a drain electrode DE. The second metal pattern may include a buffer pattern BP, a first insulating layer130, a dummy pattern DP and a gate electrode GE. For example, a thin film transistor may have a top-gate type structure. The thin film transistor may include the gate electrode GE, the source electrode SE, the drain electrode DE and the active pattern AP.

The active pattern AP may include a semiconductor layer111and an ohmic contact layer113. The semiconductor layer111may include an amorphous silicon or an oxide semiconductor. The ohmic contact layer113may be omitted. A structure of the dummy pattern DP is a layer structure substantially the same as the active pattern AP.

The first metal pattern is formed on the base substrate110on which the active pattern AP has been formed. The source electrode SE is spaced apart from the drain electrode DE on the active pattern AP. The dummy pattern DP is formed under the data line DL

The buffer pattern BP is formed at a corner between the first metal pattern and the active pattern AP or at a corner between the base substrate110and both of the first metal pattern and the active pattern AP. The buffer pattern BP may be formed at a corner formed by the first metal pattern and the buffer pattern BP with the base substrate110. The buffer pattern BP gradually connects an upper surface of the first metal pattern with a surface of the base substrate, so that the first insulating layer130formed on the first metal pattern is less likely to be disconnected at the corner. The particular shapes and functions of the buffer pattern BP according to the present exemplary embodiment are substantially the same as those illustrated inFIGS. 3A and 3B. Alternatively, a capping pattern CP substantially the same as that illustrated inFIGS. 6A and 6Bmay be formed between the buffer pattern BP and the first metal pattern. Thus, any repetitive descriptions will be omitted.

The gate electrode GE is formed on the first insulating layer130and the gate electrode GE is covered by the second insulating layer160. The drain electrode DE is in contact with the pixel electrode PE through a contact hole CNT which are formed through the first insulating layer130and the second insulating layer160.

In a method of manufacturing the display substrate104according to the present exemplary embodiment, the semiconductor layer111, the ohmic contact layer113and the first metal layer are sequentially formed on the base substrate110and are patterned using a mask, so that the source electrode SE, the drain electrode DE, the data line DL, the active pattern AP and the dummy pattern DP are formed.

Thereafter, a coating layer is formed on the base substrate110on which the first metal pattern, the active pattern AP and the dummy pattern DP have been formed. Then, the buffer pattern BP is formed to pattern the coating layer. The process of forming the buffer pattern BP is substantially the same as that illustrated inFIGS. 4A and 4B. Thus, any repetitive descriptions will be omitted.

After the buffer pattern BP has been formed, the first insulating layer130is formed. The second metal layer is formed on the base substrate110on which the first insulating layer130has been formed, and the second metal layer is patterned to form the gate electrode GE.

The second insulating layer160is formed on the base substrate110on which the gate electrode GE has been formed, and the first and second insulating layers130and160are patterned to form the contact hole CNT through which the drain electrode DE is partially exposed.

The pixel electrode PE is formed on the base substrate on which the contact hole CNT has been formed, and then the display substrate104illustrated inFIG. 9is formed.

According to the exemplary embodiments, a buffer pattern is formed at a corner formed between a sidewall surface of a first metal pattern and a base substrate, so that a second metal pattern is less likely to be disconnected at the corner in the subsequent manufacturing processes. Thus, the first metal pattern having relatively narrow width and relatively large thickness is formed, so that a RC signal delay may be solved and reliability of manufacturing the second metal pattern may be improved by the buffer pattern.