Auto-biasing circuit for current mirrors

In accordance with the present invention, an auto-biased cascode current circuit capable of improved range in headroom is disclosed. In one embodiment, the current circuit includes a current mirror and a bias circuit, where the current mirror contains a reference leg and an output leg. A reference current flows within the reference leg. Included in the output leg is an output terminal, a first output transistor and a second output transistor. The output terminal operates at an output potential. The bias circuit regulates the reference leg of the current mirror such that the output potential is substantially equal to a drain-to-source saturation voltage of the first output transistor plus a drain-to-source saturation voltage of the second output transistor plus a predetermined overdrive voltage. The predetermined overdrive voltage is a design parameter which is less than a threshold voltage. Even as the reference current changes, the bias circuit regulates the reference leg so that the reference current may change significantly while the bias circuit still maintains a proper output potential. In another embodiment, a method for auto-biasing a cascode current circuit is disclosed. The method detects at least one voltage potential from the reference leg and uses this information generate a cascode potential to bias the reference leg.

FIELD OF THE INVENTION 
 The present invention relates to current mirror circuits, and in 
 particular, to bias circuits for current mirror circuits. 
 BACKGROUND OF THE INVENTION 
 Current circuits of various configurations are a common building block of 
 electronic circuits. Typically, current circuits are used to form a 
 current mirror. Current mirrors either sink or source current in such a 
 way as to respectively receive or provide a substantially constant current
 to a load. 
 With reference to FIG. 1, a conventional two-transistor current mirror 100 
 is shown in schematic form. A reference current I.sub.refl is provided to 
 a diode-connected reference transistor MN.sub.1 which is mirrored by an 
 output transistor MN.sub.2 to produce an output current I.sub.out1. 
 Characteristic of current mirrors, the output current I.sub.out1 is 
 substantially equal to the reference current I.sub.ref1 long as the 
 geometry of the reference transistor MN.sub.1 is substantially the same as
 the geometry of the output transistor MN.sub.2. Those skilled in the art 
 can appreciate however, that the ratio of the output current I.sub.out1 to
 the reference current I.sub.ref1 may be modified by changing the ratio of 
 the geometry of the output transistor MN.sub.2 to the reference transistor
 MN.sub.1. 
 The simple current mirror 100 allows for low-swing operation of an output 
 voltage V.sub.out1 of a load, but suffers from poor output resistance. 
 FIG. 2 is a graph which shows the relationship between the output current 
 I.sub.out1 along the ordinate direction and the output voltage V.sub.out1 
 along the abscissa. The response graph of the current mirror 100 is 
 divided between a triode region 200 and a saturation region 204. The 
 saturation region 204 is defined as the output voltage V.sub.out1 being 
 larger then a saturation voltage V.sub.DS(sat)2 of the output transistor 
 MN.sub.2. In general, the saturation voltage V.sub.DS(sat) is defined as 
 the drain-to-source voltage of a transistor necessary to begin operation 
 of that transistor in the saturation region which is shown as the "knee" 
 of the curve in FIG. 2. While operating in the saturation region 204, 
 changes in output voltage V.sub.out1 at the load have little effect on the
 output current I.sub.out1. However, while operating in the triode region 
 200, changes in output voltage V.sub.out1 at the load have great effect on
 the output current I.sub.out1. In other words, the output voltage 
 V.sub.out1 can swing as low as the saturation voltage V.sub.DS(sat)2 
 before the output resistance becomes unacceptably affected. Although the 
 simple current mirror 100 provides for a low-swinging output voltage, 
 those skilled in the art can appreciate, that the output resistance is 
 still undesirably low while operating in the saturation region 204. 
 With reference to FIG. 3, a conventional cascode current mirror 300 is 
 drawn in schematic form. A first reference transistor MN.sub.3 and second 
 reference transistor MN.sub.4, which are diode connected, form the 
 reference leg 308 of the cascode current mirror while a first output 
 transistor MN.sub.5 and second output transistor MN.sub.6 form the output 
 leg 312. The second output transistor MN.sub.6 is known as a cascode 
 transistor and serves to buffer output voltage V.sub.out2 swings from the 
 first output transistor MN.sub.5 such that the first output transistor 
 MN.sub.5 is more likely to remain operating in saturation. 
 Conventional cascode current mirrors 300 provide excellent output 
 resistance at the expense of a lower swing on the output voltage 
 V.sub.out2 (i.e., the ability of the output voltage V.sub.out2 to swing 
 low while maintaining a high output resistance). With reference to FIG. 4,
 a graph of the relationship between output current I.sub.out2 along the 
 ordinate direction and output voltage V.sub.out2 along the abscissa is 
 shown. When both the first and second output transistors MN.sub.5, 
 MN.sub.6 are in the saturation region 408, the output current I.sub.out2 
 remains nearly constant as the output voltage V.sub.out2 changes. In other
 words, the output resistance is extremely high while the output 
 transistors MN.sub.5, MN.sub.6 are saturated. However, as the second 
 output transistor MN.sub.6 passes into the triode region 404 the output 
 resistance decreases. The output resistance decreases further when both 
 the first and second output transistors MN.sub.5, MN.sub.6 pass into the 
 triode region 400. For both output transistors MN.sub.5, MN.sub.6 to 
 remain in saturation 408, Equation 1 must be satisfied: 
EQU V.sub.out(min)2 &gt;V.sub.t +V.sub.DS(sat)5 +V.sub.DS(sat)6 (1) 
 Equation 1 merely states the minimum output voltage V.sub.out(min)2 cannot 
 fall below the sum of a threshold voltage V.sub.t, the saturation voltage 
 V.sub.DS(sat)5 of the first output transistor MN.sub.5 and the saturation 
 voltage V.sub.DS(sat)6 of the second output transistor MN.sub.6. Where the
 voltage threshold term V.sub.t is a process variable which is generally 
 the same for all NMOS transistors for a particular semiconductor process 
 and can be defined by the following Equation 2: 
EQU V.sub.t =V.sub.GS -V.sub.DS(sat) (2) 
 Where V.sub.GS is the gate-to-source voltage of a transistor. Stated 
 another way, the threshold voltage V.sub.t defines the gate-to-source 
 voltage V.sub.GS at which a conduction channel forms between the drain and
 source. If however, the output voltage falls below the point defined by 
 Equation 1, at least one of the output transistors MN.sub.5, MN.sub.6 will
 begin operating in the triode region which significantly decreases the 
 output resistance. It should be noted, that although the output resistance
 of the cascode current mirror 300 is greater than that of the simple 
 current mirror 100, the low-swing of the cascode current mirror 300 is 
 considerably higher than the low-swing of the simple current mirror 100. 
 Output resistance of a current mirror is important because it defines how 
 the output current will change as the output voltage changes. Operating 
 the transistors of the output leg MN.sub.2, MN.sub.5, MN.sub.6 of a 
 current mirror 100, 300 in the saturation region significantly increases 
 the output resistance. Additionally, the use of the cascode current mirror
 300 increases the output resistance when compared to the simple current 
 mirror 100. 
 Headroom is important because it defines the range in which the output 
 voltage V.sub.out2 may operate. The lowest swing of the output voltage 
 V.sub.out(min)2 defines the lower limit of the headroom, while the 
 positive power supply V.sub.DD generally defines the upper limit of the 
 headroom (i.e., V.sub.out(max)2 =V.sub.DD). Any load circuit which uses 
 the current mirror generally operates within the range defined by the 
 headroom to assure adequate output resistance. Recently, there has been a 
 trend toward lower voltage power supplies V.sub.DD, because of their 
 reduced power consumption. However, reducing the power supply V.sub.DD 
 impinges upon the upper range of the headroom V.sub.out(max)2 available to
 the load circuit utilizing the current mirror. Accordingly, there is a 
 need to increase headroom for current mirrors without reducing output 
 resistance. 
 SUMMARY OF THE INVENTION 
 In accordance with the present invention, an auto-biased cascode current 
 circuit capable of improved range in headroom is disclosed. In one 
 embodiment, the current circuit includes a current mirror and a bias 
 circuit, where the current mirror contains a reference leg and an output 
 leg. A reference current flows within the reference leg. Included in the 
 output leg is an output terminal, a first output transistor and a second 
 output transistor. The output terminal operates at an output potential. 
 The bias circuit regulates the reference leg of the current mirror such 
 that the output potential is substantially equal to a drain-to-source 
 saturation voltage of the first output transistor plus a drain-to-source 
 saturation voltage of the second output transistor plus a predetermined 
 overdrive voltage. The predetermined overdrive voltage is a design 
 parameter which is less than a threshold voltage. Even as the reference 
 current changes, the bias circuit regulates the reference leg so that the 
 reference current may change significantly while the bias circuit still 
 maintains a proper output potential. 
 In another embodiment, a method for auto-biasing a cascode current circuit 
 is disclosed. The method detects at least one voltage potential from the 
 reference leg and uses this information to generate a cascode potential to
 bias the reference leg. In this way, low-swing operation of the cascode 
 current circuit is maintained even if the reference current changes. 
 Based upon the foregoing summary, a number of important advantages of the 
 present invention are readily discerned. A high output resistance is 
 achieved because of the cascode configuration of the current mirror while 
 still allowing the output voltage to swing low. The ability to swing low 
 provides additional range in headroom for the load. Additionally, the 
 current mirror is auto-biased such that a large range of reference 
 currents are supported without needing to redesign the bias circuitry. 
 Additional advantages of the present invention will become readily apparent
 from the following discussion, particularly when taken together with the 
 accompanying drawings.

DETAILED DESCRIPTION 
 With reference to FIG. 5, a cascode current mirror 500 with a high output 
 resistance and a low swing output voltage is shown in schematic form. The 
 first and second reference transistors MN7, MN8, which form a reference 
 leg 508, are configured such that the output voltage V.sub.out(min)3 can 
 swing lower than a conventional cascode current mirror 300 (see FIG. 3). 
 More specifically, so long as the minimum output voltage V.sub.out(min)3 
 is such that Equation 3 is satisfied, a first and second output 
 transistors MN.sub.9, MN.sub.10 of a output leg 512 will remain in 
 saturation V.sub.DS(sat)9, V.sub.DS(sat)10. 
EQU V.sub.out(min)3 &gt;V.sub.DS(sat)9 +V.sub.DS(sat)10 (3) 
 By operating the first and second output transistors MN.sub.9, MN.sub.10 in
 the saturation region, the output resistance advantageously remains large.
 Comparison of Equation 3 with Equation 1, which define the minimum output 
 voltage V.sub.out(min) for their respective circuits, reveals the low 
 swing current mirror 500 can tolerate a lower output voltage 
 V.sub.out(min) than the convention current mirror 300 by an additional 
 voltage threshold V.sub.t while maintaining the same large output 
 resistance. By lowering the swing of the output voltage V.sub.out(min)3 
 for the low-swing current mirror 500, the range of headroom available to 
 the load is increased accordingly. 
 FIG. 6 shows a graph of an output current I.sub.out3 in the ordinate 
 direction and the output voltage V.sub.out3 along the abscissa for the 
 low-swing cascode current source 500. As can be seen from the graph, the 
 output current I.sub.out3 remains substantially constant as the output 
 voltage V.sub.out3 varies, so long as a first output transistor MN.sub.9 
 and a second output transistor MN.sub.10 both operate in saturation mode 
 608. That as to say, operating the transistors MN.sub.9, MN.sub.10 in the 
 output leg 512 of the current mirror advantageously provides a large 
 output resistance while both transistors operate in saturation mode 608. 
 The output resistance decreases when either one 604 or both 600 of the 
 output transistors MN.sub.9, MN.sub.10 operate in the triode region. 
 Although providing lower swing on the output voltage V.sub.out(min)3 and a 
 large output resistance, the cascode current mirror 500 shown in FIG. 5 
 requires a manual bias circuit 504 to provide a cascode voltage V.sub.cas1
 to the gate terminal of each of the cascode transistors MN.sub.8, 
 MN.sub.10. The optimal minimum value for the cascode voltage 
 V.sub.cas1(min) (i.e., producing the most headroom for the output voltage 
 V.sub.out3) is the saturation voltage V.sub.DS(sat)7 for the first 
 reference transistor MN.sub.7 plus the saturation voltage V.sub.DS(sat)8 
 for the second reference transistor MN.sub.8 plus the threshold voltage 
 V.sub.t for the second reference transistor MN.sub.8, as defined by the 
 following Equation 4: 
EQU V.sub.cas1(min) =V.sub.DS(sat)7 +V.sub.DS(sat)8 +V.sub.t (4) 
 To produce the cascode voltage V.sub.cas1, a bias current I.sub.bias is 
 provided to a diode connected transistor MN.sub.11 so that the cascode 
 voltage V.sub.cas1 properly biases the cascode transistors MN.sub.8, 
 MN.sub.10. The bias current I.sub.bias flowing through the diode connected
 transistor MN.sub.11 forces a proportional gate potential V.sub.G11 which 
 is used as the cascode voltage V.sub.cas1. Biasing in this way, allows 
 achieving the low swing of the output voltage V.sub.out(min)3 defined by 
 Equation 3 which maximizes the headroom available to the load. 
 To provide a proper bias current I.sub.bias a designer must provide a 
 current source circuit. Generally, these circuits are static. This means 
 they provide a single bias current I.sub.bias which cannot respond to 
 changing needs of the cascode voltage V.sub.cas1. As those skilled in the 
 art can appreciate however, if the reference current I.sub.ref3 changes, 
 the saturation voltage V.sub.DS(sat)7 must also change to maintain maximum
 headroom for the output voltage V.sub.out3. As shown in Equation 4 above, 
 the cascode voltage V.sub.cas1 should be adjusted when the saturation 
 voltage V.sub.DS(sat)7 changes which also means the current source circuit
 providing the bias current I.sub.bias should change accordingly. It should
 be noted however, that some applications require accommodation of 
 especially large current swings on the output leg 512 of tune current 
 mirror (i.e., large swings in output current I.sub.out3) such as switching
 loads. Large variances in output current I.sub.out3 require large swings 
 in reference current I.sub.ref3 which require large swings in bias current
 I.sub.bias. 
 As those skilled in the art can appreciate, choosing the proper cascode 
 voltage V.sub.cas1 can be an arduous task since the saturation voltage 
 V.sub.DS(sat)7 is not only affected by changes in the reference current 
 I.sub.ref3 (as discussed above), but also semiconductor process variables,
 operating temperature, and other factors. Designers typically raise the 
 bias current I.sub.bias to compensate for changes in the reference current
 I.sub.ref3, semiconductor process variables, operating temperature, and 
 other factors which may affect the saturation voltage V.sub.DS(sat)7 and 
 also raise the cascode voltage V.sub.cas1. By raising the cascode voltage 
 V.sub.cas1 however, the minimum swing available to the output voltage 
 V.sub.out(min)3 also undesirably raises which affects the range of 
 headroom available to the load. This reduction in the headroom is becoming
 less acceptable as the power supply voltage V.sub.DD is lowered to 
 conserve power. Accordingly, there is a need to provide a low-swing 
 cascode current source which automatically compensates for such factors as
 the reference current I.sub.ref3, semiconductor process variables and 
 operating temperature. 
 With reference to FIG. 7, an embodiment of an auto-biased low-swing current
 mirror is shown in schematic form. This embodiment generally includes a 
 cascode current mirror 700 having a reference leg 708 and an output leg 
 712, but also includes an auto-biasing circuit 704 which compensates for 
 the factors which require adjusting a cascode voltage Vcas2 to maintain 
 the maximum range of headroom on the output voltage V.sub.out4. In brief, 
 a first through fourth bias transistors MN.sub.16, MP.sub.1, MP.sub.2, 
 MN.sub.17 of the auto-biasing circuit 704 cooperate to provide feedback 
 which dynamically compensates for such factors as reference current 
 I.sub.ref4, semiconductor process variables and operating temperature in 
 order to properly bias a current mirror 700 portion of the circuit. Use of
 feedback in this way generally allows for providing the maximum range of 
 headroom to the output voltage V.sub.out4 of the load. 
 The goal of the bias circuit 704 is to maintain a minimum headroom voltage 
 V.sub.out(min)4, while factors which affect a saturation voltage 
 V.sub.DS(sat)14, V.sub.DS(sat)15 of a first output transistor MN.sub.14 
 and a second output transistor MN.sub.15 change. The minimum output 
 voltage V.sub.out(min)4 which assures the first and second output 
 transistors MN.sub.14 MN.sub.15 remain in saturation V.sub.DS(sat)14, 
 V.sub.DS(sat)15 is described in Equation 5: 
EQU V.sub.out(min)4 &gt;V.sub.DS(sat)14 +V.sub.DS(sat)15 (5) 
 As described more fully above, keeping the first and second output 
 transistors MN.sub.14, MN.sub.15 in saturation desirably creates a large 
 output resistance for the load. 
 To maintain the condition defined in Equation 5 while the factors which 
 affect the saturation voltages V.sub.DS(sat)14, V.sub.DS(sat)15 change, a 
 cascode voltage V.sub.cas2 and a bias voltage V.sub.bias must also change.
 If the following Equations 6, 7 and 8 are satisfied, the minimum output 
 voltage defined by Equation 5 is generally maintained: 
EQU V.sub.bias =V.sub.t +V.sub.DS(sat)12 (6) 
EQU V.sub.cas2(min) =V.sub.DS(sat)12 +V.sub.DS(sat)13 +V.sub.t (7) 
EQU V.sub.D12 =V.sub.DS(sat)12 (8) 
 Where V.sub.DS(sat)12 is the saturation voltage of a first reference 
 transistor MN.sub.12 for particular reference current I.sub.ref4, and 
 V.sub.D12 is the voltage on the drain of MN.sub.12. The bias circuit 704 
 generally satisfies the conditions expressed in Equations 6, 7 and 8 while
 allowing the reference current I.sub.ref4 to preferably change by orders 
 of magnitude. As can be appreciated by those skilled in the art, the auto 
 biasing circuit 704 avoids having to redesign the current source needed to
 supply a bias current I.sub.bias to the manual bias circuit 504 (see FIG. 
 5) to accommodate different reference currents I.sub.ref3. 
 The auto bias circuit 704 is comprised of a first through fourth bias 
 transistors MN.sub.16, MP.sub.1, MP.sub.2, MN.sub.17. The gate of a first 
 bias transistor MN.sub.16 is attached to the drain of the second reference
 transistor MN.sub.13 and to the gate of the first reference transistor 
 MN.sub.12. The source of the first bias transistor MN.sub.16 is attached 
 to the source of the second reference transistor MN.sub.13 and to the 
 drain of the first reference transistor MN.sub.12. A NMOS transistor 
 threshold V.sub.t is produced across the gate and source of the first bias
 transistor MN.sub.16 (i.e., V.sub.GS =V.sub.t). Consequently, the 
 interconnections between the first bias transistor MN.sub.16 and the first
 and second reference transistors, MN.sub.13 assure a positive transistor 
 threshold +V.sub.t will also exist across the drain and source of the 
 second reference transistor (i.e., V.sub.DS13 =V.sub.t), while a negative 
 transistor threshold -V.sub.t wilt exist across the gate and drain of the 
 first transistor (i.e., V.sub.GD12=-V.sub.t). The first bias transistor is
 matched to the first reference transistor MN.sub.12 (i.e., has 
 substantially the same layout and geometry). 
 The second and third bias transistors MP.sub.1, MP.sub.2, are PMOS 
 transistors which form a simple current mirror to source current. The 
 second bias transistor MP.sub.1 is diode connected. Because of the nature 
 of the current mirror, the current through the first bias transistor 
 MN.sub.16 is substantially equal too the current through a fourth bias 
 transistor MN.sub.17. 
 The fourth bias transistor MN.sub.17 is diode connected. A cascode voltage 
 V.sub.cas2 is produced at the gate of the fourth bias transistor MN.sub.17
 which is proportional to the current flowing through the fourth bias 
 transistor MN.sub.17. The cascode voltage V.sub.cas2 is provided to the 
 gates of the second reference transistor MN.sub.13 and the second output 
 transistor MN.sub.15. In this way, the current which flows through the 
 first bias transistor MN.sub.16 affects the cascode voltage V.sub.cas2. 
 The bias circuit 704 uses feedback sensed by the first bias transistor 
 MN.sub.16 to set the cascode voltage V.sub.cas2. There are two modes of 
 operation for the bias circuit 704 in which the loop gain of the feedback 
 loop is different. When the drain-to-source voltage V.sub.DS13 of the 
 second reference transistor MN.sub.13 is less that the voltage threshold 
 V.sub.t, the first bias transistor MN.sub.16 allows less current to flow, 
 limits the feedback and decreases the cascode voltage V.sub.cas2. 
 Alternatively, when the drain-to-source voltage V.sub.DS13 of the second 
 reference transistor MN.sub.13 is more that the voltage threshold V.sub.t,
 the first bias transistor MN.sub.16 allows more current to flow, increases
 the feedback and increases the cascode voltage V.sub.cas2. The cascode 
 voltage V.sub.cas2 applied to the second reference transistor MN.sub.13 
 affects the drain-to-source voltage V.sub.DS13 of the second reference 
 transistor MN.sub.13 such that the feedback loop as complete. 
 As those skilled in the art can appreciate, a current mirror may be 
 configured as a voltage amplifier. With reference to FIG. 8, an embodiment
 of a voltage amplifier leg 800 which utilizes the present invention is 
 shown. Changes on the input voltage V.sub.in are reflected in the output 
 voltage V.sub.out5 and output current I.sub.out5 such that the amplifier 
 leg 800 is characterized as having a gain. It should be noted, the same 
 reference 708 and bias circuitry 704 are used to properly bias he 
 amplifier leg 800. The ability to auto-bias this amplifier allows 
 low-swing operation of the amplifier leg 800. 
 With reference to FIG. 9, the bias circuit 704 is represented as block 
 diagram of a feedback loop. The feedback loop receives the drain-to-source
 voltage V.sub.DS13 of the second reference transistor MN.sub.13 as an 
 input 900 to produce the cascode voltage V.sub.cas2 as an output 904. A 
 dual mode gain block 908 is applied to the input 904. As explained above, 
 the value of the drain-to-source voltage V.sub.DS13 of the second 
 reference transistor MN.sub.13 dictates whether the first bias transistor 
 MN.sub.16 passes a large current or a small current which is represented 
 as the dual mode gain block 908. A feedback block 912 reflects changes in 
 the cascode voltage V.sub.cas2 as changes in the drain-to-source voltage 
 V.sub.DS13 of the second reference transistor MN.sub.13. As can be 
 appreciated by those skilled in the art, changes in the gate-to-source 
 potential of a transistor will cause changes in the drain-to-source 
 voltage. In this way, the output of the feedback loop 904 settles into 
 supplying the saturation voltage V.sub.DS(sat)12 of the first reference 
 transistor MN.sub.13 to the gate of the second reference transistor 
 MN.sub.13 even if the reference current I.sub.ref4 changes the saturation 
 voltage V.sub.DS(sat)12. 
 Often designers wish to provide excess bias to the drain of the first 
 reference transistor MN.sub.12. This concept is sometime referred to by 
 those skilled in the art as saturation voltage overdrive V.sub.overdrive. 
 When a transistor is biased at the "knee" of the saturation region it is 
 said to be at the saturation voltage V.sub.DS(sat), however, applying an 
 extra amount of bias to the drain (i.e., applying voltage overdrive 
 V.sub.overdrive) will insure that the transistor is biased beyond the 
 "knee" and will likely remain in the saturation region. Reference current 
 I.sub.ref4 changes, semiconductor process variances, operating temperature
 changes, and other factors can be additionally compensated for by 
 providing for saturation voltage overdrive V.sub.overdrive. 
 The bias circuit 704 is capable of providing extra bias V.sub.overdrive to 
 the cascode voltage V.sub.cas2 such that the first reference transistor 
 MN.sub.12 is more likely to remain in saturation as conditions change. 
 Providing saturation voltage overdrive V.sub.overdrive is accomplished by 
 making the fourth bias transistor MN.sub.17 weak with respect to the first
 bias transistor MN.sub.16. Since the current flowing in each leg of the 
 current source of the bias circuit 704 is generally equal because of the 
 current mirror defined by the second and third bias transistors MP.sub.1, 
 MP.sub.2, the gate voltage V.sub.G17 of the fourth bias transistor 
 MN.sub.17 must increase to accommodate the current, if the device is made 
 weaker. By increasing the gate voltage V.sub.G17, the cascode voltage 
 V.sub.cas2 also increases which provides saturation voltage overdrive 
 V.sub.overdrive to the first reference transistor MN.sub.12. 
 Although the above discussion is generally limited to current mirrors 
 configured as current sinks, those skilled in the art can appreciate the 
 principals are equally applicable to current sources as well. 
 Additionally, while the embodiments disclosed use CMOS transistors, the 
 concepts are equally applicable to other transistor types. 
 The forgoing description of the invention has been presented for the 
 purposes of illustration and description and is not intended to limit the 
 invention. Variations and modifications commensurate with the above 
 description, together with the skill or knowledge of the relevant art, are
 within the scope of the present invention. The embodiments described 
 herein are further intended to explain the best mode known for practicing 
 the invention and to enable those skilled in the art to utilize the 
 invention in such best mode or other embodiments, with the various 
 modifications that may be required by the particular application or use of
 the invention. It is intended that the appended claims be construed to 
 include alternative embodiments to the extent permitted by the prior art.