Length and rate compatible LDPC encoder and decoder

A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data.

BACKGROUND

Field

The present method and system relates generally to a digital communication system and more particularly to the use of error correcting codes in digital communications systems, and particularly relates to the use of LDPC (low density parity check) codes in digital communications systems. Examples of such systems include digital television broadcast systems, cellular telephone systems and the like.

Description of the Related Art

Like all linear block codes, an LDPC (low density parity check) code can be described in terms of a matrix. In the case of an LDPC code the matrix contains a first portion consisting of information bits and a second portion containing parity bits, the matrix commonly being referred to as an H-matrix, or a parity check matrix. The LDPC code gets its name from the H-matrix which contains relatively few 1's in comparison to the number of 0's.

Many modern communications systems require the use of error correction codes that can accommodate different code rates and different lengths of information bits. It is well known that longer code lengths improve error correcting performance, while shorter code lengths are characterized by reduced processing delays. Likewise it is known that increasing code rates improves the data rate and bandwidth efficiency, while reducing code rates increases information robustness in noisy channels. However, designing separate error correction codes for each different code length and code rate that may be used in a particular communications system is a very complicated process and often not practical.

It would therefore be highly desirable to provide a novel error correction system using error correction codes capable of adapting to different information lengths and different code rates. Such a system would be designed with the goal of providing performance that is equal or close to the performance of systems using separately designed codes and would inherently be of low complexity since it would obviate the need to design a separate code for each condition and would employ encoder and decoder hardware that can be reused in different situations without extra cost.

SUMMARY

The present invention achieves these and other objects by specially modifying a first LDPC code H matrix, referred to a “mother code,” to become a smaller size LDPC code H matrix, referred to as a daughter code, and using the daughter code to encode and decode the information bits of transmitted and received digital signals. Another aspect of the invention employs code puncturing to improve code error correcting performance.

DETAILED DESCRIPTION

FIG. 1is a block diagram showing an embodiment of an encoder10according to a certain embodiment of the present invention. The encoder10may be provided in a transmitter of a digital communication system, for example. The encoder10comprises a shortening and puncturing sets allocator12which largely controls the operation of the encoder10. The allocator12includes four outputs; a first output14connected to the input of a mother LDPC (low density parity check) code shortening unit16, a second output18connected to an information bits puncturing unit20, a third output22connected to a parity bits puncturing unit24, and a fourth output26connected to a combiner28. The allocator12also includes an input30for receiving a control signal reflecting a target SNR (signal to noise ratio) for the transmitted signal and the payload length of the transmitted information bits. The control signal on the control signal input30may be generated by another piece of equipment or may be manually inserted by the user on the encoder10. The allocator12, in response to the control signal supplied on the control signal input30, derives and provides a first message on the first output14defining an information shortening set, a second message on the second output18defining an information puncturing set and a third message on the third output22defining a parity puncturing set. The allocator12also provides the control signal at the fourth output26for application to the combiner28.

The purpose of the information shortening set provided on the output14of the allocator12is to shorten as necessary the mother LDPC H matrix stored in the code shortening unit16to match the length of the data payload supplied over an input32to a daughter LDPC code encoder34. The information shortening set in certain embodiments identifies portions of the mother matrix to be removed to obtain the daughter matrix. Taking for example the simple case where the payload data is 800 bits and the mother LDPC code H matrix is 1000 bits, the information shortening set would instruct the shortening unit16to shorten the mother LDPC code H matrix by 200 bits and supply the resulting shortened daughter LDPC code H matrix for storage in the encoder34. The daughter LDPC code matrix thus corresponds to the size of the data payload to be encoded and the daughter matrix may be used to encode the payload data for transmission in a digital communication system, for example.

More realistic parameters for the operation just described above are shown inFIGS. 3aand 3b.FIGS. 3aand 3billustrate a practical mother LDPC code H matrix80comprising an information bits portion82and a parity bits portion84. Each value in the information bits portion82of the chart80defines a unique smaller matrix of 1's and 0's characterized by a quasi-cyclic variation from one small matrix to the next. Each “0” value in the parity bits portion84of the chart80defines a smaller matrix of 1's and 0's characterized in that it consists of a single diagonal through the matrix. Although the H matrix80illustrated inFIG. 3aand 3bis relatively complex, it is treated similar to the simple example given above. Thus, the mother LDPC code H matrix80illustrated inFIG. 3aand 3bis shortened by reducing the number of bits comprising the matrix to match the number of bits in the data payload. Shortening is achieved in this example by dropping the bits in each column of the mother H matrix80identified by an “S” in the third row86of the matrix80(which corresponds to columns 2, 3, 7, 15, 21 and 27 in the illustrated example). The information shortening set on the output14as derived by the allocator12, the first message, therefore comprises the set {2, 3, 7, 15, 21, 27}, which identifies the columns to be removed. The allocator12also supplies the control signal reflecting the information on the input30to the output26for application to the combiner28for transmission to the decoder, which will be described in more detail hereinafter.

The illustrated example shows removal of columns to achieve shortening of the mother matrix. It is possible that other portions of the matrix may be removed for shortening, such as rows, a combination of columns and rows, or other arrangements or patterns for shortening to form the daughter matrix.

The shortened daughter LDPC H matrix is supplied from the code shortening unit16to the encoder34where the shortened matrix is used to process the input data payload, for example to provide encoded data. Referring back to the simple example where both the data payload and shortened LDPC code H matrix are 800 bits, the encoder34will output800information bits on an output36and, for example, 1000 parity bits on an output38. The parity bits on the output38are supplied to the input of the parity bits puncturing unit24and the information bits on the output36are supplied to the information bits puncturing unit20.

Referring toFIGS. 4aand 4b, which illustrates the same mother LDPC code H matrix80asFIG. 3aand 3b, in response to the second message comprising the information puncturing set {1, 4, 5}, identified by the letter “P” in row 88 at the top of the respective columns in the chart80, on the output18of the allocator12, the puncturing unit20will puncture the information bits supplied on the output36of the encoder34by dropping columns 1, 4, and 5 from the H matrix. In the case of the simple example, if 100 information bits are thus punctured from the 800 information bits provided, 700 punctured information bits are supplied from the information bits puncturing unit20to the combiner28.

With reference now toFIGS. 5aand 5b, which also illustrates the same mother LDPC code H matrix80as shown inFIGS. 3aand 3b, in response to the third message comprising the parity puncturing set {1, 4, 5, 13, 18}, identified by the letter “P” in row 90 at the top of the respective columns in the parity portion of the chart80, on the output22of the allocator12, the puncturing unit24will puncture the parity bits supplied on the output38of the encoder34by dropping (or removing) columns 1, 4, 5, 13 and 18 from the H matrix. The person of skill in this art understands how to select portions of the matrix for puncturing. In the case of the simple example, if 1000 parity bits are supplied on the output38and 300 bits are punctured by the puncturing unit24, 700 parity bits are supplied by the parity bits puncturing unit24to the combiner28.

The illustrated example shows removal of columns to achieve puncturing of the matrix. It is possible that other portions of the matrix may be removed for puncturing, such as rows, combinations of rows and columns, or other arrangements or patterns for forming the punctured matrix.

Referring back toFIG. 1, the allocator12also supplies the control signal on the output26, from which the first, second and third messages are derived, for application to the combiner28. The combiner28, which may comprise a conventional multiplexer, combines the (700) punctured information bits from the information bits puncturing unit20, the (700) punctured parity bits from the parity bits puncturing unit24and the control signal from of the allocator12. The combined signal is applied to a modulator40and other appropriate transmission equipment for transmission to the decoder, such as a decoder at a receiver, for example.

It should be noted that in operation the encoder has adapted itself to encode a shorter payload than the mother LDPC code H matrix is configured to handle and has punctured (performed a data puncturing process on) both the shortened information bits as well as the parity bits, thereby improving bandwidth efficiency and improving robustness of the transmitted signal.

FIG. 2is a block diagram showing an embodiment of a decoder50according to the present invention. The decoder50may be provided in a receiver of a digital communication system, for example. The decoder50, which may be implemented, for example, in the form of a field programmable gate array (FPGA), comprises a receiving unit52for receiving the signal transmitted from encoder10. Other implementations are of course possible within the scope of the invention. The receiving unit52comprises a tuner, a demodulator and other receiving circuits for providing a digital signal on an output54representing the bits provided in the signal transmitted from the encoder10. Continuing with the previously used example, 1400 bits are therefore supplied from the receiving unit52to a splitter56over the output54.

It will be recalled that the transmitted signal included a control signal (representing a target SNR for the transmitted signal and the payload length of the transmitted information bits) from which the information shortening set (the first message), the information puncturing set (the second message) and the parity puncturing set (the third message) are obtained by an allocator. The splitter56extracts the control signal from the signal supplied on the output54and supplies it to a shortening and puncturing allocator58. The splitter56also supplies a first portion of the bits on the output54containing the punctured information bits (700 bits in the example) to a first depuncturing unit60and supplies a second portion of the bits on the output54containing the parity bits (also 700 bits in the example) to a second depuncturing unit62. The allocator58derives the information shortening set (the first message), the information puncturing set (the second message) and the parity puncturing set (the third message) from the received control signal and supplies them on outputs68,64and66, respectively. The allocator58is operationally identical to the allocator12at the encoder, so that the same information shortening set, information puncturing set and parity puncturing set are derived from the same control signal (that includes the SNR and payload length, in the illustrated example). The depuncturing units60and62are controlled by the second and third messages representing the information and parity puncturing sets supplied by the allocator58to the depuncturing units60and62on the respective outputs64and66. The third message representing the information shortening set is supplied by the allocator58over the output68to a shortening LDPC mother code H matrix unit70. The output of the shortening LDPC mother code H matrix unit70comprises a shortened H matrix supplied over a line72for storage in a memory of a daughter LDPC code decoder74which provides the recovered payload data on a decoder output76. The mother code matrix is shortened to provide the smaller daughter code matrix, the daughter code matrix corresponding in size to the received data payload so that the data can be decoded using the daughter matrix.

It will be understood that much of the operation of the decoder50is reverse that of the operation of the encoder10. Thus, with reference again to the simplified example, 700 punctured bits of the received 1400 bits are depunctured by the first depuncturing unit60so that 800 expanded bits are provided thereby to the decoder74. The depuncturing operation performed by the depuncturing unit60adds a number of 0's (100 in the case of the simplified example) in the correct locations as defined by the second message corresponding to the information puncturing set supplied on the output64of the allocator58. A similar operation is performed by the depuncturing unit62which expands the 700 punctured parity bits supplied by the splitter56to 1000 expanded parity bits with 0's inserted in the correct locations as defined by the third message corresponding to the parity puncturing set supplied on the output66of the allocator58.

The 800 expanded information bits and 1000 expanded parity bits are supplied by the depuncturing units60and62to the daughter LDPC code decoder74. The decoder74comprises an H matrix corresponding in size to the supplied 800 expanded information bits (i.e. 800 bits) which is responsive to the expanded information bits together with the 1000 expanded parity bits to recover 800 error corrected payload data bits on the output76. Advantageously, the H matrix used in the decoder74is derived from the H matrix stored in the shortening LDPC mother code H matrix unit70. In particular, the H matrix stored in the matrix unit70is shortened by the matrix unit70in response to the first message corresponding to the information shortening set supplied on the output68of the allocator58from 1000 bits to 800 bits (matching the 800 expanded information bits in size) and supplied over the output72for storage in and use by the decoder74.

Of course, both the encoder portion and the decoder portion may be shortened to accommodate data payloads of different sizes by shortening the mother code matrix as needed to provide daughter code matrices of corresponding sizes. In this way the operation of the decoder50is compatible with different length LDPC codes by appropriately varying the first message corresponding to the information shortening set supplied to the shortening LDPC mother code H matrix unit70.

As in the case of the encoder10, more realistic parameters for the operation of the decoder50are shown inFIGS. 3a-5bwhich were previously described in connection with the operation of the encoder and will therefore not be described in detail again. Thus, it will be recalled thatFIGS. 3aand 3billustrate a practical mother LDPC code H matrix80used by the matrix unit70to create the daughter LDPC code H matrix contained in the decoder74,FIGS. 4aand 4billustrate the use of the information puncturing set by the first depuncturing unit60to form the expanded information bits andFIGS. 5aand 5billustrate the use of the parity puncturing set by the second depuncturing unit62to form the expanded parity bits.

Thus, there is shown and described a certain embodiment of a method and system for modifying the size of an encoding and decoding matrix to correspond to different sizes of data payloads. Other embodiments for modifying an encoding and/or decoding means and method to accommodate different sizes or characteristics of data payloads are within the scope of the present invention.

There is also shown and described a certain embodiment of a method and system for reducing data by puncturing both the information bits and the parity bits and for recovering the data by depuncturing the information bits and the parity bits. Other embodiments of a data reducing and data recovering means and method are within the scope of the present invention.