Method and system for reducing radiated energy emissions in computational devices

A method and system for reducing the release of high frequency electromagnetic energy into the environment is disclosed, wherein local regions of distributed capacitance are embedded within a printed circuit board (PCB) and adjacent the PCB conductive traces act as low pass filters and thus increase the rise and/or fall times occurring on such traces. The present invention increases very short rise and/or fall times (e.g., 200 picoseconds or less) without degrading or detrimentally affecting other signal characteristics. The present invention does not substantially affect the voltage amplitude and does not affect the bit period when lengthening the rise and/or fall time. Also, the present invention does not induce any timing jitter that may cause synchronization problems within the system.

RELATED FIELD OF THE INVENTION

The present invention is related to a method and apparatus for reducing high frequency electromagnetic radiation from a computational device, and in particular, reducing the emission of such radiation from a conductive trace of a circuit board.

BACKGROUND

There are radiated emission regulatory requirements that must be satisfied by any commercial product. One of these requirements is called the electromagnetic compatibility (or EMC) requirement, which requires that products must not radiate excessive electromagnetic radiation into their intended environment. For electronic products having computational devices therein, electromagnetic radiation may be difficult to restrict from the product's intended environment since there are typically ventilation openings or ducts for air circulation in order to dissipate heat. In particular, such computational devices may generate high frequency electromagnetic radiation, which is characterized by short wavelengths, wherein such radiation is easier to leak through, e.g., ventilation openings.

One source of high frequency electromagnetic radiation generated by computational devices is the voltage oscillations along conductive traces within such devices. In particular, the voltage changes associated with the rise and fall times of the waveforms of bits transmitted along such traces can radiate high frequency electromagnetic radiation. For example, it is known that decreases in the rise and/or fall times increases high frequency energy being radiated. Assuming the rise and fall times are approximately the same, the highest frequency of the radiated energy, in some circumstances, can be roughly characterized as one over twice the rise time. Accordingly, very short rise and/or fall times (e.g., on the order of about 200 picoseconds or less) for digital voltage waveforms can result in unacceptably high frequency energy being radiated from a computational device. However, as computational devices become increasingly faster, bit periods tend to decrease, and accordingly, the corresponding rise and fall times within such bit periods tend to decrease thereby generating increasingly more radiated high frequency electromagnetic energy. Thus, as the computational processing speed increases, additional measures must be taken to make sure that an undesirable amount of high frequency radiation is not released into the environment where it may harm people and/or affect other devices.

One way to reduce the release of such high frequency radiation can be to reduce the number or size of the apertures through which such radiation may exit a housing for a computational device and thereby enter the environment. However, as mentioned above, such a technique could require sophisticated ducting, more powerful ventilation fans, more electromagnetic shielding in the housing, and/or greater attention during manufacturing to properly seal small unintended openings where such radiation could exit.

An alternative approach to reduce the release of such high frequency radiation is to lengthen the rise and fall times of the digital signals by using a signal filtering mechanism. The most straightforward mechanism is a low pass filter that increases the rise and/or fall times. However, conventional techniques for implementing such low pass filters do not perform well when the rise and fall times are very small (e.g., on the order of about 200 picoseconds or less). For example, commercially available discrete resistors, discrete capacitors, discrete conductors operate substantially differently when exposed to such rapid voltage changes of very small rise and/or fall times. In particular, parasitic effects are generated by such components so that a presumed low pass filter circuit having such discrete components will not properly lengthen the rise and/or fall times. For example, a commercial capacitor will generally only behave as a capacitor up to a frequency range of about 25 to 30 megahertz. Beyond this frequency range, such a capacitor will behave as an inductor.

Thus, it would be desirable to be able to effectively attenuate the release of high frequency electromagnetic radiation in a high-speed computational device in a straightforward manner, and without instituting elaborate measures for trapping such high frequency electromagnetic radiation within the confines of a housing for the device.

SUMMARY

The present invention is a method and system for reducing the release of high frequency electromagnetic energy into the environment, wherein local regions of distributed capacitance are embedded within printed circuit boards (PCBs) adjacent the PCB conductive traces. The local regions of capacitance act as low pass filters and thus increase the rise and/or fall times occurring on such adjacent traces. In particular, the present invention increases very short rise and/or fall times (e.g., 200 picoseconds or less) without degrading or detrimentally affecting other signal characteristics. More particularly, the present invention does not substantially affect the voltage amplitude, and does not affect the bit period when lengthening the rise and/or fall time. In addition, the present invention does not induce any timing jitter that may cause synchronization problems within the system.

Embodiments of the local regions of capacitance may be embedded within a PCB circuit board adjacent to a conductive trace (also simply denoted “trace” herein) on which rise and/or fall times are to be increased. Such local regions of capacitance (also denoted as LROCs herein) may be distributed electrically isolated metallic structures, wherein each such structure includes one or more small electrically isolated copper plates or pads (although other conductive materials may be used such as aluminum, silver, or gold). The electrically isolated metallic structures (also denoted as floating metallic structures herein) are not electrically connected to their adjacent traces. However, for a given trace on which the rise and/or fall times are to be increased, the distributed floating metallic structures are positioned adjacent to the trace (also referred to as the “corresponding trace” hereinbelow) so that: (a) their extent along the trace (e.g., overlapping or covering), (b) their distance from the trace, and (c) the distance between the floating capacitive structures are determined such that each such structure operates as a low pass filter on the signals transmitted along the trace.

In one embodiment of the invention, each LROC may be only a single floating metallic plate or pad. In other embodiments, one or more LROCs may each include a plurality of floating metallic plates or pads oriented relative to one another, and to their corresponding trace, for increasing the capacitance of the LROC, and thus increasing the effectiveness of its low pass filtering affects.

Other features and benefits of the present invention will become evident from the accompanying drawing and the Detailed Description hereinbelow.

DETAILED DESCRIPTION

Without being bound by a particular theoretical basis, the laws of physics state that all currents within a circuit must return to their source(s). For printed circuit boards (PCBs) such current return paths are known to be generally immediately above and/or immediately below the trace on which the current is transmitted. Additionally, such return paths are generally near the surfaces of the PCB circuit boards, such surfaces commonly referred to as “reference planes”. The present invention induces high frequency currents, being transmitted along a PCB trace, to be re-routed by a local region of capacitance (LROC) adjacent to the trace and returned to the current source via the current return paths near the reference planes. As a result, there is a reduction in high frequency radiation emitted from the PCB circuit board. Said differently, since an LROC presents a low-impedance path back to the current source for high-frequency currents, it is believed that such an LROC captures high frequency noise currents occurring on the trace, and returns them to their source.

FIG. 1illustrates the above described theoretical basis for the invention, wherein a PCB circuit board20cross section has a trace24embedded therein (the trace extending perpendicularly to the plane ofFIG. 1), and the return currents28and32are represented by the cross-hatched areas adjacent the PCB surfaces or reference planes36and40.

FIGS. 2 and 3show one embodiment of the present invention, wherein LROCs44are distributed underneath the trace24. In particular, each LROC44is simply a single floating metallic structure (e.g., a pad)48underneath another metallic structure (i.e., the trace), wherein each of the structures48and the trace24includes a respective surface52and56, these surfaces being parallel to one another over a predetermined (short) distance60(i.e., the length of the floating structure48). Thus, for each of the metallic structures48, when a current flows along the trace24, a capacitance (C1) may be induced between the metallic structure48and the trace24over the local region (of distance60) in which the structures are adjacent. In particular, as described hereinabove, the present invention contemplates the lower metallic structure48being “floating”, meaning that it is not conductively attached to another conductive structure. Additionally, for each of the metallic structures48, a capacitance (C2) between the floating structure48(e.g., a piece of copper) and its nearest reference plane (i.e., reference plane36,FIG. 2) may be induced. Accordingly, when a current on the trace24passes by the floating conductive structure48, then depending upon: (a) the capacitance C1associated with the corresponding induced capacitor64(FIG. 2), (b) the capacitance C2associated with the corresponding induced capacitor68, and additionally depending upon (c) the frequencies associated with this current floating through the trace, the local total capacitance of the series combination of C1and C2can be configured to behave as a capacitor without parasitic effects. In other words, the impedance of the combination of the capacitors64and68should be substantially 1/(2·π·f·C), where f is the frequency and C is the total capacitance of the capacitors C1and C2. Thus as the frequency f of the trace current gets very high (e.g., above 2 gigahertz), the impedance gets very small and so this current tends to take the path of smaller impedance back to its source. Accordingly, the present invention is directed to attenuating the noise currents corresponding to such very high frequencies, wherein such noise currents tend to take an alternative path through the floating structure(s)48back to the source and thus high frequency radiated emissions are attenuated.

An alternative embodiment of the invention is illustrated inFIGS. 4 and 5, wherein each LROC44includes two of the floating metallic structures48(identified for clarity here as48aand48b), one such structure above the trace24and another below the trace24. In this embodiment, the additional floating metallic structures48a(e.g., floating pieces of copper) can be used to further improve high frequency noise signal attenuation. In particular, there is a structure48a, which is a mirror image of the lower metallic structure48b, provided above the trace24as shown inFIGS. 4 and 5so that the trace is substantially midway between both reference planes36and40and midway between the floating structures48aand48b(FIG. 4) that are above and below the trace. Of course, structures24,48a, and48bcould be placed asymmetrically between the reference planes36and40, as one skilled in art will understand.

Assuming the corresponding capacitances for the capacitors72and76of upper floating metallic structure48aare identical with capacitances C1and C2described above for the capacitances of the lower structure48b, the total capacitance of the LROC44ofFIG. 4(i.e., in a local region adjacent the trace24) is the series capacitance C1and C2in parallel with the series capacitance C1and C2, i.e., CT=2((C1*C2)/(C1+C2)). Of course, capacitors72,76,64, and68can have different values as one skilled in the art will understand.

There are certain geometric attributes of such floating metallic structures48that the present invention contemplates providing values (or ranges of values) for enhancing the filtering of very high frequencies. For example, the length60of such floating metallic structures48along the length of the trace24is one such attribute (discussed at (b) below). In particular, such floating metallic structures48should satisfy certain geometric conditions that allow each local (LROC) capacitance to be modeled as substantially a discrete capacitor. For instance, the conditions described in (a) through (e) immediately below are satisfied in a preferred embodiment of the invention:(a) In order for such a floating metallic structure48to be effective for providing at least a portion of a local region of capacitance44, the floating structure must be close to its corresponding trace24. For example, the distance between reference planes36and40is typically about 10-20 thousandths of an inch (mils) for very high-speed devices. The distance between a floating metallic structure48(or48a,48b), and its corresponding trace24should be about half the distance between the trace24and the reference plane nearest the floating metallic structure. This distance will typically be between about 1.4 mils and 6.2 mils, for any PCB dielectric material.(b) In order for such a floating metallic structure48to operate substantially as a pure capacitor (i.e., with substantially no parasitic effects), the floating metallic structure must be relatively short in the direction of the length of its corresponding trace24(i.e., in the direction of arrow2ofFIG. 3, and/or arrow4ofFIG. 5) since otherwise, the floating metallic structure has an undesirable inductive component as well. Said another way, the greater the extent of such a floating metallic structure48along the length of its corresponding trace, the more inductive it becomes, and accordingly, the floating structure acts less like a capacitor, as one skilled in the art will understand. In particular, it is preferred that the extent60(FIGS. 3 and 5) of such a floating metallic structure48along its corresponding trace24: (i) be between 10 mils and 50 mils long, and/or (ii) less than approximately 0.25 of the required distance along the trace24for propagating the rise time (or fall time). For example, letting LTrdenote the required distance along the trace24for propagating the rise time (or fall time), if the trace24provides a signal propagation delay of 160 picoseconds/inch and the rise time Tr is approximately 10 picoseconds (as it is likely to be in the near future), then LTris approximately 1/16 inches (=62.5 mils), and if a floating metallic structure48is to be 0.20 of LTr, then the extent of floating metallic structure along the trace is 1/80 inches (=12.5 mils). It is further believed that the range in the extent60of such a floating metallic structure along its corresponding trace24should be approximately between 10 mils and 50 mils in order to provide an effective local (LROC) capacitance for most devices having signal rise times less than about 200 picoseconds. Moreover, in at least one embodiment, it is believed that the extent of such a floating metallic structure should be less than or equal to 5.1 percent of the length LTr.(c) Typically, it is preferred that a floating metallic structure48extend beyond the width of the adjacent face the corresponding trace24. That is, referring toFIGS. 4 and 5, the faces80and84of the respective floating metallic structures48aand48bshould extend beyond the width “w” (FIG. 5) of the trace24. The reason for this is that any fringing fields that may exist on the edges of the trace24can be also used to increase the capacitance related to the floating metallic structure48. In particular, it is believed that in at least one embodiment, such a floating metallic structure48should extend beyond the width w of the corresponding trace by about 2 w or 200% of w; e.g., the width of the floating metallic structure would be about 300% of w, with an extent approximately equal to w extending on either side of the trace beyond the trace's width. Moreover, in at least one embodiment, such a floating metallic structure48should be approximately 2 to 5 mils from the corresponding trace.(d) It is believed that the floating metallic structures48can be variously shaped, and in fact, it is believed that the shape and thickness “t” (FIG. 5) of such a floating structure (i.e., “t” extending in a direction proceeding substantially orthogonally away from the signal conducting direction along the corresponding trace) can vary significantly. However, it is also believed that the more of the surface area of a trace that is covered or overlapped by the surface(s) of such a floating metallic structure48, the more capacitance will be generated. Thus, floating metallic structures48having square and/or rectangular surfaces facing and extending along their corresponding trace24(e.g.,FIGS. 3 and 5) may provide more capacitance than, e.g., a diamond, circular, or an oval shaped floating metallic structure when, e.g., the trace is has substantially straight sides.(e) As specified earlier, there may be LROCs44distributed adjacently along the length of a trace24. However, the distance L (FIGS. 3 and 5) between two consecutive LROCs44is important for obtaining the desired low pass filtering effects of the present invention. In particular, the distance L between the consecutive local regions of capacitance44must be such that the total signal delay time along the corresponding trace24between the two LROCs is much larger than, e.g., the rise time (and/or fall time).When the total signal delay time along a trace24between two LROCs44is much larger than, e.g., the rise time (and/or fall time), then the interconnecting portion of the trace24corresponding to the length L may be considered a transmission line between these two LROCs. This implies that when an entire signal pulse is transmitted on the interconnecting portion (e.g., L inFIG. 5), the corresponding voltage will be different at different points along the interconnecting portion; i.e., the voltage is distributed along the interconnecting portion L thereby making it a distributed circuit or transmission line, as one skilled in the art will understand. Thus, assuming the rise and fall times are approximately the same (which in general is the case), it is preferred that the total time delay (TdTOTAL) for signal transmission across an interconnection portion should be at least 100% of the rise time.Additionally, assuming that the signal propagation delay along the interconnection portion is TL (e.g., in units of picoseconds/inch), then Tr/TLprovides a minimal bound on the distance L between such local regions of capacitance44, wherein the interconnection portion is just long enough to fully contain the signal for at least, e.g., the rise time. However, in some embodiments, L may be reduced to be greater than or equal to 52% of L. The following example is illustrative for determining a value for L. For most commercially available PCB circuit boards, the substrate for these boards is composed of the dielectric commonly identified as FR-4 as one skilled in the art will understand, wherein a plurality of traces24are provided therein.

However, other substrate materials are within the scope of the present invention, such as a dielectric material that is characterized with a real relative dielectric permittivity greater than or equal to about 4.0 at a signal frequency 1/(2tr) Hertz, wherein tris the signal rise time. Note that there are generally two types of traces provided in such PCB circuit boards: microstrips and striplines. The signal propagation delay for a microstrip is approximately 160 picoseconds/inch, and the signal propagation delay for a stripline is approximately 180 picoseconds/inch. Assuming a rise time Tr in extremely high speed circuits in the range of, e.g., 40 picoseconds on a one inch microstrip trace24, and assuming that each LROC44has relatively negligible extent60(e.g., 10 mils), then the one inch of microstrip trace, would be able to contain approximately 4 (=160/40) rise times, or equivalently, the length between LROCs44should be at least ¼ of an inch. A simulated example illustrating the undesirability of the length L being too short is shown inFIG. 10and described hereinbelow.

Accordingly, by combining the geometric characteristics of a floating metallic structure48as recited in (a) through (e) above, various geometric embodiments of the floating metallic structures can be obtained, such as an embodiment wherein each LROC44along a trace24is spaced apart from other LROCs along the trace by at least ⅛ of an inch, and each floating metallic structure of the LROCs has a substantially rectangular extent facing the trace24(as shown inFIGS. 3 and 5), wherein each floating metallic structure: (i) is about 2 mils from the trace, (ii) extends about 50 mils along the trace, and (iii) extends about 10 mils beyond the width w of the trace on either side. However, as stated above, various other embodiments are also possible such as oval or elliptical embodiments of the floating metallic structures48as is shown inFIG. 26.

Note that the number of distributed LROCs44depends on the amount of capacitance needed to lengthen very short rise and/or fall times generated by the computational device so that the radiated electromagnetic emissions are reduced. For example,FIGS. 19-20illustrate the needed LROC capacitances as well as the number of LROCs to achieve a given increase in the rise/fall times of the input signal. In fact, in some embodiments, only one such LROC44adjacent to a trace24may be needed.

In yet other embodiments of the invention, additional floating metallic structures48may be provided adjacent to a trace24as shown inFIG. 6.

Viewing eye patterns of a device (i.e., a PCB circuit board) are well known in the art as a visual technique for assessing the stability of a computational device, and accordingly may be used to demonstrate various benefits of the present invention. In particular, eye patterns, as one skilled in the art will understand, are simply the superposition of all possible transitions of 1 s and 0 s in a data stream; i.e., a 0 to 1, a 1 to 0, a 1 to 1, a 0 to 0, a 00 to 0, a 00 to 1, and so on superimposed on top of each other. Thus, eye patterns determine the response of a digital system to these kinds of pattern transitions, and provide visual information indicative of the timing jitter occurring in the computational device as well as the duration and amplitude of the rise and fall times.FIGS. 7 and 8show graphs of eye patterns of an input 2 Gb/sec signal with a 175 picosecond rise time, and the output signal after propagation through twenty 0.5 picofarad LROCs, respectively. In particular,FIG. 7shows the eye patterns for a trace24that does not have the local regions of capacitance44of the present invention adjacent thereto (and/or surrounding). Thus,FIG. 7shows a rise time of approximately 175 picoseconds. On the other hand,FIG. 8shows the eye patterns for a trace24having the local regions of capacitance44according to the present invention adjacent thereto (or surrounding a portion of the trace). More precisely, the trace24forFIG. 8has twenty such local regions of capacitance44adjacent thereto according to the present invention, wherein these regions of capacitance are 0.054 inches in length along the trace, and are spaced apart by 0.505 inches, wherein each such local region of capacitance44generates a leakage capacitance of 0.5 picofarads from the trace. Accordingly,FIG. 8shows a rise time of approximately 232 picoseconds, which is a 32.6% increase in rise time without substantially affecting the bit period, noise margin, or timing jitter. Moreover, note that the amplitude of the signals shown inFIG. 8are only trivially reduced from those ofFIG. 7(more precisely,FIG. 7shows a total signal amplitude of two volts as the noise margin, whereasFIG. 8shows a noise margin of approximately 1.95). Additionally, since the crossings of the rising and falling portions of the graphs inFIG. 8are substantially at zero voltage, this illustrates that the present invention is not likely to add any appreciable timing jitter to the computational device.

FIG. 9shows superimposed graphs of simulations of the corresponding energy emissions from the traces providing the eye patterns ofFIGS. 7 and 8. In particular, graph100A is for the trace corresponding toFIG. 7, and graph100B is for the trace24corresponding toFIG. 8, which utilizes the present invention. As can be seen, the invention acts as low pass filter, wherein as the frequency increases, the energy radiated (in the present case, simulated by the magnitude of the Fourier transform, as one skilled in the art will understand) is progressively attenuated.

FIG. 10shows the results of a simulation when the distance between two adjacent LROCs is too small. In particular,FIG. 10simulates two consecutive LROCs44provided along a trace24, wherein the distance between the LROCs is 78 mils, and wherein a signal having a rise time of 1.0 nanoseconds is transmitted on the trace. Additionally, each of the two LROCs44has the following characteristics: a trace leakage capacitance of 0.35 picofarads, resistance of 0.078 Ohms, inductance of 0.9 nano-Henries. Graph110ofFIG. 10shows the input voltage to the portion of the trace having the two LROCS44during the rise time. Graph114ofFIG. 10shows a simulation of the voltage at the output of the first LROC along the trace. Note that the output voltage is substantially distorted, emphasizing the importance of maintaining the proper distance between adjacent LROCs44. This simulation, as well as all other simulations described herein (e.g., the graphs ofFIGS. 11-25) were performed using Mathcad, a mathematical simulation program.

FIGS. 11-18show additional input and output eye patterns for embodiments of the invention having different simulated LROC44capacitances and different numbers of LROCs. These figures show the impact of these variations in LROC capacitance and numbers on an input 175 picosecond rise time. Each of these figures is further described in the Brief Description of the Drawings hereinabove. Note that for these figures the following geometric conditions were assumed: (a) the distance L between LROC44was assumed to be 505 mils, (b) the spacing the floating metallic structures48and the trace (i.e., “h” inFIG. 26) was assumed to be 4 mils, and (c) the overlap with a facing side of the trace24was assumed to be 54 mils.

FIG. 19shows the increase in the 175 picosecond input rise time as a function of the number of LROCs44for LROC capacitances of 0.4 picofarads, 0.283 picofarads, and 0.184 picofarads, wherein the same geometric conditions as forFIGS. 11-18were assumed.

FIG. 20shows the increase in the rise times for 0 picosecond, 20 picosecond, 60 picosecond, 100 picosecond, 145 picosecond, and 200 picosecond input rise times, as a function of the number of LROCs44along a trace24having a length in the range of 12.5 inches, and for each LROC, an LROC capacitance of 0.4 picofarads, wherein the same geometric conditions as forFIGS. 11-18were assumed. Note the graphs ofFIG. 20show that for very fast rise times at least five LROCs44yield the most dramatic increase in rise time, and as the number of LROCs substantially increases, the increase in rise time slowly reduces. Accordingly, it is believed that, at least in some embodiments, at least five LROCs should be spaced adjacent to the trace24, and 25 to 35 RLOCs are likely to be the range for an upper limit on the number of LROCs along such a trace24.

FIG. 21shows the percentage increase of an input 175 picosecond rise time as a function of the number of LROCs44for LROC capacitances of: 0.4 picofarads, 0.283 picofarads, and 0.184 picofarads, wherein the same geometric conditions as forFIGS. 11-18were assumed.

FIG. 22shows the percentage increase of 60 picosecond, 100 picosecond, 145 picosecond, and 200 picosecond input rise times as a function of the number of LROCs44for an LROC capacitance of 0.4 picofarads, wherein the same geometric conditions as forFIGS. 11-18were assumed.

FIG. 23shows the achievable maximum Non-Return-To-Zero (NRZ) bit rates, as a function of the number of LROCs, for input NRZ pulses characterized with rise times of 0 picoseconds, 20 picoseconds, 60 picoseconds, 100 picoseconds, 145 picoseconds, and 200 picoseconds. Since the number of LROCs will limit the achievable maximum bit rate, this design information is important. The maximum achievable bit rate is defined to be the maximum bit rate that maintains the input noise margin at the output of the last LROC.

FIG. 24shows the achievable LROC44capacitances for three different LROC configurations, as a function of the extent60(FIGS. 3 and 5) between LROCs. Curve C ofFIG. 24is for the LROC44configuration ofFIG. 2, in which the single floating structure48is square shaped. Curve B ofFIG. 24is for an LROC44configuration whose components include those ofFIG. 2, with the addition of two identical square floating structures48, one on each side of the trace24(as opposed to the above and below the trace as inFIG. 4), and wherein each floating structure48is located 5 mils from the outer edge of trace24. Curve A corresponds to an LROC whose components are shown inFIG. 6, wherein all floating structures48are square shaped and each floating structure is 5 mils from its nearest floating structure.

FIG. 25shows the minimum distance between adjacent LROCs, as a function of the input rise time, in order for the present invention to operate in a best mode.

FIG. 26shows a different embodiment of the proposed invention. In particular, the trace24includes expanded regions120that are adjacent and parallel to a corresponding one of the floating metallic structures48for thereby increasing the capacitance at each LROC44. More particularly, there may be one of the expanded regions120adjacent to each (or most) of the floating metallic structures48. Additionally, the integration of the expanded regions120into the trace24ofFIG. 26may substantially reduce the number of floating structures needed to achieve a given LROC44capacitance. In fact, each of these expanded regions120may only be adjacent to one of the reference planes20or36, as shown inFIG. 1, and have no adjacent floating structures48whatsoever. In this later case, the LROC44capacitance is between each expanded region120and one of the reference planes20or36. That is, the expanded regions120are effective for inducing a capacitance with at least one of the reference planes20or36so that high frequency noise signals do not continue on the trace24, but instead migrate to the return currents28or32(FIG. 1) at the expanded regions.

Manufacturing of the present invention can be performed using currently available conventional PCB circuit board manufacturing techniques. In PCB circuit boards with a small number of layers (e.g., less than 6), the present invention may require the addition of at least one extra layer to provide the floating metallic structures48therein as in shown inFIG. 3. Moreover, additional layers may be needed to provide LROCs44as shown inFIGS. 5or6. In most PCB circuit boards that generate high frequency signals (e.g., above 2 gigahertz), there are likely to be a sufficient number of PCB layers (e.g., from 10 to 16 layers) already provided so that the LROCs44and their floating metallic structures48can be manufactured into pre-existing PCB layers.