Resistive memory cell accessed using two bit lines

An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application claims priority to European Patent Application No. 09000936.6-1233, filed on Jan. 23, 2009, and incorporated herein by reference.

BACKGROUND

One type of memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. Typically, the resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element.

One type of resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as the amorphous state and the crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state. Also, some phase change materials exhibit multiple crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state, which have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity and the crystalline state generally refers to the state having the lower resistivity.

Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state—“set”—and from the crystalline state to the amorphous state—“reset”—in response to temperature changes. The temperature changes of the phase change material may be achieved by driving current through the phase change material itself or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material.

A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change memory cell. The temperature in the phase change material in each memory cell generally corresponds to the applied level of current and/or voltage to achieve the heating.

To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states, where the multi-bit or multilevel phase change memory cell can be written to more than two states. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. To program a phase change memory cell to an intermediate resistance value, the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy.

SUMMARY

One embodiment provides an integrated circuit. The integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.

DETAILED DESCRIPTION

FIG. 1is a block diagram illustrating one embodiment of a system90. System90includes a host92and a memory device100. Host92is communicatively coupled to memory device100through communication link94. Host92includes a microprocessor, computer (e.g., desktop, laptop, handheld), portable electronic device (e.g., cellular phone, personal digital assistant (PDA), MP3 player, video player, digital camera), or any other suitable device that uses memory. Memory device100provides memory for host92. In one embodiment, memory device100includes a phase change memory device or another suitable resistive or resistivity changing material memory device.

FIG. 2is a diagram illustrating one embodiment of memory device100. In one embodiment, memory device100is an integrated circuit or part of an integrated circuit. Memory device100includes a write circuit124, a controller120, a memory array101, and a sense circuit126. Memory array101includes a plurality of resistive memory cells104a-104d(collectively referred to as resistive memory cells104), a plurality of first bit lines (BL1s)112a-112b(collectively referred to as first bit lines112), a plurality of second bit lines (BL2s)113a-113b(collectively referred to as second bit lines113), and a plurality of word lines (WLs)110a-110b(collectively referred to as word lines110). In one embodiment, resistive memory cells104are phase change memory cells.

In one embodiment, each memory cell104includes a phase change element and a heater. The heater is thermally coupled to the phase change element for programming the phase change element. A first bit line is electrically coupled to each phase change element for reading the state of each phase change element. A second bit line is electrically coupled to each heater for writing a desired state to each phase change element.

As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.

Memory array101is electrically coupled to write circuit124through signal path125, to controller120through signal path121, and to sense circuit126through signal path127. Controller120is electrically coupled to write circuit124through signal path128and to sense circuit126through signal path130. Each phase change memory cell104is electrically coupled to a word line110, a first bit line112, a second bit line113, and a common or ground114. Phase change memory cell104ais electrically coupled to first bit line112a, second bit line113a, word line110a, and common or ground114. Phase change memory cell104bis electrically coupled to first bit line112a, second bit line113a, word line110b, and common or ground114. Phase change memory cell104cis electrically coupled to first bit line112b, second bit line113b, word line110a, and common or ground114. Phase change memory cell104dis electrically coupled to first bit line112b, second bit line113b, word line110b, and common or ground114.

Each phase change memory cell104includes a phase change element106, a heater107, and a transistor108. While transistor108is a field-effect transistor (FET) in the illustrated embodiment, in other embodiments, transistor108can be another suitable access device such as a bipolar transistor, a thyristor, or a 3D transistor structure. In other embodiments, a diode or diode-like structure is used in place of transistor108. In this case, a diode and phase change element106is coupled in series between each cross point of word lines110and first bit lines112, and the diode and heater107are coupled in series between each cross point of word lines110and second bit lines113.

Phase change memory cell104aincludes phase change element106a, heater107a, and transistor108a. One side of phase change element106ais electrically coupled to first bit line112a. The other side of phase change element106ais electrically coupled to one side of the source-drain path of transistor108aand one side of heater107a. The other side of the source-drain path of transistor108ais electrically coupled to common or ground114. The gate of transistor108ais electrically coupled to word line110a. The other side of heater107ais electrically coupled to second bit line113a.

Phase change memory cell104bincludes phase change element106b, heater107b, and transistor108b. One side of phase change element106bis electrically coupled to first bit line112a. The other side of phase change element106bis electrically coupled to one side of the source-drain path of transistor108band one side of heater107b. The other side of the source-drain path of transistor108bis electrically coupled to common or ground114. The gate of transistor108bis electrically coupled to word line110b. The other side of heater107bis electrically coupled to second bit line113a.

Phase change memory cell104cincludes phase change element106c, heater107c, and transistor108c. One side of phase change element106cis electrically coupled to first bit line112b. The other side of phase change element106cis electrically coupled to one side of the source-drain path of transistor108cand one side of heater107c. The other side of the source-drain path of transistor108cis electrically coupled to common or ground114. The gate of transistor108cis electrically coupled to word line110a. The other side of heater107cis electrically coupled to second bit line113b.

Phase change memory cell104dincludes phase change element106d, heater107d, and transistor108d. One side of phase change element106dis electrically coupled to first bit line112b. The other side of phase change element106dis electrically coupled to one side of the source-drain path of transistor108dand one side of heater107d. The other side of the source-drain path of transistor108dis electrically coupled to common or ground114. The gate of transistor108dis electrically coupled to word line110b. The other side of heater107dis electrically coupled to second bit line113b.

In one embodiment, each phase change element106includes a phase change material that may be made up of a variety of materials. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase change material of phase change element106is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe, or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Bi, Se, and S.

Each phase change element106may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under the influence of temperature change. The amount of crystalline material coexisting with amorphous material in the phase change material of one of the phase change elements106a-106dthereby defines two or more states for storing data within memory device100. In the amorphous state, a phase change material exhibits significantly higher resistivity than in the crystalline state. Therefore, the two or more states of phase change elements106a-106ddiffer in their electrical resistivity.

In one embodiment, the two or more states are two states and a binary system is used, wherein the two states are assigned bit values of “0” and “1”. In another embodiment, the two or more states are three states and a ternary system is used, wherein the three states are assigned bit values of “0”, “1”, and “2”. In another embodiment, the two or more states are four states that can be assigned multi-bit values, such as “00”, “01”, “10”, and “11”. In other embodiments, the two or more states can be any suitable number of states in the phase change material of a phase change element.

Each heater107includes a resistive material for generating heat in response to a current or voltage applied to the heater. In one embodiment, each heater107includes TiN, TaN, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, or other suitable material. Each heater107is thermally coupled to a phase change element106. Each heater107provides the heat for programming the phase change element to an amorphous state, to a crystalline state, or to a partially amorphous and partially crystalline state.

Controller120includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of memory device100. Controller120controls read and write operations of memory device100including the application of control and data signals to memory array101through write circuit124and sense circuit126. In one embodiment, write circuit124provides voltage pulses through signal path125and second bit lines113to heaters107to program phase change elements106. In other embodiments, write circuit124provides current pulses through signal path125and second bit lines113to heaters107to program phase change elements106.

Sense circuit126reads each of the two or more states of memory cells104through first bit lines112and signal path127. In one embodiment, to read the resistance of one of the memory cells104, sense circuit126provides current that flows through one of the phase change elements106. Sense circuit126then reads the voltage across that one of the phase change elements106. In another embodiment, sense circuit126provides voltage across one of the phase change elements106and reads the current that flows through that one of the phase change elements106.

During a reset operation of phase change memory cell104a, word line110ais selected to activate transistor108a. With word line110aselected, a reset current or voltage pulse is selectively enabled by write circuit124and sent through second bit line113ato heater107a. The reset current or voltage quickly heats heater107a, which quickly heats phase change element106aabove its melting temperature. After the current or voltage pulse is turned off, phase change element106aquickly quench cools into the amorphous state or a partially amorphous and partially crystalline state.

During a set operation of phase change memory cell104a, word line110ais selected to activate transistor108a. With word line110aselected, one or more set current or voltage pulses are selectively enabled by write circuit124and sent through second bit line113ato heater107a. The set current or voltage pulses heats heater107a, which heats phase change element106aabove its crystallization temperature (but usually below its melting temperature). In this way, phase change element106areaches the crystalline state or a partially crystalline and partially amorphous state during this set operation.

During a read operation of phase change memory cell104a, word line110ais selected to activate transistor108a. In one embodiment with word line110aselected, a read current is applied to phase change element106aby sense circuit126through first bit line112a. Sense circuit126then reads the voltage across phase change element106ato sense the state of phase change element106a. In another embodiment with word line110aselected, a read voltage is applied to phase change element106aby sense circuit126through first bit line112a. Sense circuit126then reads the current through phase change element106ato sense the state of phase change element106a. Phase change memory cells104b-104dand other phase change memory cells104in memory array101are set, reset, and read similarly to phase change memory cell104ausing similar current or voltage pulses.

FIG. 3Aillustrates a cross-sectional view of one embodiment of a memory cell200a. In one embodiment, memory cell200aprovides each memory cell104previously described and illustrated with reference toFIG. 2. Memory cell200aincludes an electrode202, a heater204, a phase change element206, a first bit line208, a second bit line210, and dielectric material212,214,216,218, and220.

Electrode202includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, Cu, C, or other suitable electrode material. The top of electrode202contacts the bottom of heater204and the bottom of phase change element206. In one embodiment, heater204is pipe-shaped and phase change element206is cylindrical-shaped. In other embodiments, heater204and phase change element206have other suitable configurations. Heater204includes TiN, TaN, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, or other suitable heater material. Phase change element206includes a chalcogenide compound material or another suitable resistance changing material. The top of heater204contacts the bottom of first bit line208. First bit line208includes W, Cu, Al, or other suitable bit line material. The top of phase change element206contacts the bottom of second bit line210. Second bit line210includes W, Cu, Al, or other suitable bit line material.

Phase change element206provides a storage location for storing one or more bits of data. The active or phase change region indicated at226of phase change element206is at or near the center of heater204. During operation of memory cell200a, current or voltage pulses are applied between electrode202and first bit line208to heat heater204to program phase change element206. During a set operation of memory cell200a, one or more set current or voltage pulses are selectively enabled by write circuit124and sent to first bit line208. From first bit line208, the one or more set current or voltage pulses pass through heater204thereby heating heater204. The heat from heater204heats the phase change material of phase change element206above its crystallization temperature (but usually below its melting temperature). In this way, the phase change material reaches a crystalline state or a partially crystalline and partially amorphous state during the set operation.

During a reset operation of memory cell200a, a reset current or voltage pulse is selectively enabled by write circuit124and sent to first bit line208. From first bit line208, the reset current or voltage pulse passes through heater204thereby heating heater204. The heat from heater204quickly heats the phase change material of phase change element206above its melting temperature. After the current or voltage pulse is turned off, the phase change material quickly quench cools into an amorphous state or a partially amorphous and partially crystalline state.

FIG. 3Billustrates a cross-sectional view of another embodiment of a memory cell200b. In one embodiment, memory cell200bprovides each memory cell104previously described and illustrated with reference toFIG. 2. Memory cell200bis similar to memory cell200apreviously described and illustrated with reference toFIG. 3A, except that the location of the heater and the phase change element are reversed. Memory cell200bincludes phase change element205and heater207.

The top of electrode202contacts the bottom of phase change element205and the bottom of heater207. In one embodiment, phase change element205is pipe-shaped and heater207is cylindrical-shaped. In other embodiments, phase change element205and heater207have other suitable configurations. The top of phase change element205contacts the bottom of first bit line208. The top of heater207contacts the bottom of second bit line210. Dielectric material216laterally surrounds heater207and contacts the sidewalls of first bit line208and phase change element205. Dielectric material214laterally surrounds phase change element205.

Phase change element205provides a storage location for storing one or more bits of data. The active or phase change region of phase change element205is indicated at226. During operation of memory cell200b, current or voltage pulses are applied between electrode202and second bit line210to heat heater207to program phase change element205. During a set operation of memory cell200b, one or more set current or voltage pulses are selectively enabled by write circuit124and sent to second bit line210. From second bit line210, the one or more set current or voltage pulses pass through heater207thereby heating heater207. The heat from heater207heats the phase change material of phase change element205above its crystallization temperature (but usually below its melting temperature). In this way, the phase change material reaches a crystalline state or a partially crystalline and partially amorphous state during the set operation.

During a reset operation of memory cell200b, a reset current or voltage pulse is selectively enabled by write circuit124and sent to second bit line210. From second bit line210, the reset current or voltage pulse passes through heater207thereby heating heater207. The heat from heater207quickly heats the phase change material of phase change element205above its melting temperature. After the current or voltage pulse is turned off, the phase change material quickly quench cools into an amorphous state or a partially amorphous and partially crystalline state.

FIG. 3Cillustrates a cross-sectional view of another embodiment of a memory cell200c. In one embodiment, memory cell200cprovides each memory cell104previously described and illustrated with reference toFIG. 2. Memory cell200cis similar to memory cell200apreviously described and illustrated with reference toFIG. 3A, except that memory cell200cincludes a capping material222. Capping material222caps phase change element206. Capping material222includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, Cu, C, or other suitable electrically conductive material. The bottom of capping material222contacts the top of phase change element206. The top of capping material222contacts the bottom of second bit line210. Capping material222is laterally surrounded by dielectric material216. Memory cell200coperates similarly to memory cell200a.

FIG. 3Dillustrates a cross-sectional view of another embodiment of a memory cell200d. In one embodiment, memory cell200dprovides each memory cell104previously described and illustrated with reference toFIG. 2. Memory cell200dis similar to memory cell200apreviously described and illustrated with reference toFIG. 3A, except that memory cell200dincludes an encapsulation material224. Encapsulation material224encapsulates first bit line208. Encapsulation material224includes SiN or another suitable dielectric material. Encapsulation material224laterally surrounds first bit line208and a portion of dielectric material216. Encapsulation material224is laterally surrounded by dielectric material218. Memory cell200doperates similarly to memory cell200a.

The followingFIGS. 4-19Billustrate embodiments of a method for fabricating an array of memory cells, such as memory cells200a-200dpreviously described and illustrated with reference toFIGS. 3A-3D, respectively. For simplicity, the following description will reference a single memory cell.

FIG. 5Aillustrates a cross-sectional view of one embodiment of preprocessed wafer230and a first dielectric material214a. A dielectric material, such as SiO2, SiOx, SiN, SiON, AlOx, FSG, BPSG, BSG, SiCN, SiCOH, or other suitable dielectric material is deposited over preprocessed wafer230to provide a dielectric material layer. The dielectric material layer is deposited using chemical vapor deposition (CVD), high density plasma-chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), plasma vapor deposition (PVD), jet vapor deposition (JVD), spin-on, or other suitable deposition technique. Portions of the dielectric material layer are then etched to provide opening232exposing at least a portion of electrode202and to provide first dielectric material214a. In one embodiment, lithography using a double patterning technique is used to define opening232.

FIG. 5Billustrates a cross-sectional view of one embodiment of preprocessed wafer230, a first dielectric material214, and a second dielectric material234. In this embodiment, a first dielectric material, such as SiN or another suitable dielectric material is deposited over preprocessed wafer230to provide a first dielectric material layer. The first dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.

A second dielectric material, such as SiO2or another suitable dielectric material is deposited over the first dielectric material layer to provide a second dielectric material layer. The second dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. Portions of the second dielectric material layer and underlying portions of the first dielectric material layer are then etched to provide opening232exposing at least a portion of electrode202and to provide first dielectric material214and second dielectric material234. First dielectric material214acts as an etch stop layer in subsequent processing steps.

While the followingsFIGS. 6-10illustrate embodiments using first dielectric material214aas previously described and illustrated with reference toFIG. 5A, the embodiments are also applicable if using first dielectric material214and second dielectric material234as previously described and illustrated with reference toFIG. 5B.

FIG. 6illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214a, a heater (or phase change) material layer236a, and a second dielectric material layer216a. In one embodiment for fabricating memory cell200a,200c, or200dpreviously described and illustrated with reference toFIGS. 3A,3C, and3D, respectively, a heater material, such as TiN, TaN, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, or other suitable heater material is deposited over exposed portions of first dielectric material214aand electrode202to provide heater material layer236a. In another embodiment for fabricating memory cell200bpreviously described and illustrated with reference toFIG. 3B, a phase change material, such as a chalcogenide compound material or other suitable phase change material is deposited over exposed portions of first dielectric material214aand electrode202to provide phase change material layer236a. Heater (or phase change) material layer236ais deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.

A dielectric material, such as SiN, Al2O3, or other suitable dielectric material is deposited over heater (or phase change) material layer236ato provide second dielectric material layer216a. Second dielectric material layer216ais deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.

FIG. 7illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214a, heater (or phase change) material236b, and second dielectric material216. Heater (or phase change) material layer236aand second dielectric material layer236aare spacer etched to expose the top of first dielectric material214aand the top of electrode202to provide heater (or phase change) material236band second dielectric material216.

FIG. 8illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214a, heater (or phase change) material236b, second dielectric material216, and a phase change (or heater) material layer238a. In one embodiment, where material236bis heater material, a phase change material, such as a chalcogenide compound material or other suitable phase change material is deposited over exposed portions of first dielectric material214a, heater material236b, second dielectric material216, and electrode202to provide phase change material layer238a. In another embodiment, where material236bis phase change material, a heater material, such as TiN, TaN, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, or other suitable heater material is deposited over exposed portions of first dielectric material214a, phase change material236b, second dielectric material216, and electrode202to provide heater material layer238a. Phase change (or heater) material layer238ais deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.

FIG. 10illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214a, heater (or phase change) material236b, second dielectric material216, phase change (or heater) material239, and a capping material240. In this embodiment, phase change (or heater) material238is recess etched to provide phase change (or heater) material239. In one embodiment, where the capping material is removed in subsequent processing steps, a dielectric material, such as SiN or another suitable dielectric material is deposited over exposed portions of first dielectric material214a, heater (or phase change) material236b, second dielectric material216, and phase change (or heater) material239to provide a dielectric material layer. The dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The dielectric material layer is then planarized to expose first dielectric material214a, heater (or phase change) material236b, and second dielectric material216to provide capping material240. The dielectric material layer is planarized using CMP or another suitable planarization technique.

In another embodiment, where the capping material is removed or left in place in subsequent processing steps, an electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, WN, Cu, C, or other suitable electrically conductive material is deposited over exposed portions of first dielectric material214a, heater (or phase change) material236b, second dielectric material216, and phase change (or heater) material239to provide an electrically conductive material layer. The electrically conductive material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The electrically conductive material layer is then planarized to expose first dielectric material214a, heater (or phase change) material236b, and second dielectric material216to provide capping material240. The electrically conductive material layer is planarized using CMP or another suitable planarization technique.

While the followingFIGS. 11A-19Billustrate embodiments using phase change (or heater) material238as previously described and illustrated with reference toFIG. 9, the embodiments are also applicable if using phase change (or heater) material239and capping material240as previously described and illustrated with reference toFIG. 10.

FIG. 11Aillustrates a top view andFIG. 11Billustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236b, second dielectric material216, and phase change (or heater) material238after etching first dielectric material214a. Dielectric material214ais recess etched to expose a portion of the sidewalls of heater (or phase change) material236band to provide first dielectric material214. In another embodiment, where first dielectric material214and second dielectric material234are used as previously described and illustrated with reference toFIG. 5B, second dielectric material234is etched to expose first dielectric material214.

FIG. 12illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, and the phase change (or heater) material238after etching heater (or phase change) material236b. Heater (or phase change) material236bis etched to expose a portion of the sidewalls of second dielectric material216and to provide heater (or phase change) material236. In one embodiment heater (or phase change) material236bis etched using an isotropic wet etch or another suitable etch.

FIG. 13illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, and a first bit line material layer208a. A bit line material, such as W, Cu, Al, or other suitable bit line material is deposited over exposed portions of first dielectric material214, heater (or phase change) material236, second dielectric material216, and phase change (or heater) material238to provide a bit line material layer. The bit line material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The bit line material layer is then planarized to expose second dielectric material216and phase change (or heater) material238to provide first bit line material layer208a. The bit line material layer is planarized using CMP or another suitable planarization technique.

FIG. 14Aillustrates a top view andFIG. 14Billustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, and lines of first bit line material208bafter etching first bit line material layer208a. Portions of first bit line material layer208aare etched to expose portions of first dielectric material214and to provide lines of first bit line material208b. In one embodiment, line lithography is used to define lines of first bit line material208b. Lines of first bit line material208bcontact the top of heater (or phase change) material236.

FIG. 15illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, and first bit lines208after etching lines of first bit line material208b. Lines of first bit line material208bare recess etched to expose portions of the sidewalls of dielectric material216and to provide first bit lines208.

FIG. 16illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, first bit lines208, and an encapsulation material layer224a. In one embodiment, an encapsulation material, such as SiN or another suitable dielectric material is deposited over exposed portions of first dielectric material214, second dielectric material216, phase change (or heater) material238, and first bit lines208to provide encapsulation material layer224a. Encapsulation material layer224ais deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique.

FIG. 17illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, first bit lines208, and encapsulation material224after etching encapsulation material layer224a. Encapsulation material layer224ais spacer etched to expose the top of second dielectric material216and phase change (or heater) material238to provide encapsulation material224.

While the followingFIGS. 18-19Billustrate embodiments without encapsulation material224following the process previously described and illustrated with reference toFIG. 15, the embodiments are also applicable when using encapsulation material224following the process previously described and illustrated with reference toFIG. 17.

FIG. 18illustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, first bit lines208, and third dielectric material218. A dielectric material, such as SiO2, SiOx, SiN, SiON, AlOx, FSG, BPSG, BSG, SiCN, SiCOH, or other suitable dielectric material is deposited over exposed portions of first dielectric material214, second dielectric material216, phase change (or heater) material238, and first bit lines208to provide a dielectric material layer. The dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The dielectric material layer is then planarized to expose the top of second dielectric material216and phase change (or heater) material238to provide third dielectric material218. The dielectric material layer is planarized using CMP or another suitable planarization technique. In one embodiment, where capping material240is used as previously described and illustrated with reference toFIG. 10, the dielectric material layer, second dielectric material216, and capping layer240are planarized to expose phase change (or heater) material239and to provide third dielectric material layer218.

FIG. 19Aillustrates a top view andFIG. 19Billustrates a cross-sectional view of one embodiment of preprocessed wafer230, first dielectric material214, heater (or phase change) material236, second dielectric material216, phase change (or heater) material238, first bit lines208, third dielectric material218, second bit lines210, and fourth dielectric material220. In one embodiment, a bit line material, such as W, Cu, Al, or other suitable bit line material is deposited over exposed portions of second dielectric material216, phase change (or heater) material238, and third dielectric material218to provide a bit line material layer. The bit line material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. Portions of the bit line material layer are then etched to expose portions of third dielectric material218and to provide second bit lines210. In one embodiment, second bit lines210are defined using line lithography.

A dielectric material, such as SiO2, SiOx, SiN, SiON, AlOx, FSG, BPSG, BSG, SiCN, SiCOH, or other suitable dielectric material is deposited over exposed portions of third dielectric material218and second bit lines210to provide a dielectric material layer. The dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The dielectric material layer is then planarized to expose the top of second bit lines210to provide fourth dielectric material220. The dielectric material layer is planarized using CMP or another suitable planarization technique.

In another embodiment, a dielectric material, such as SiO2, SiOx, SiN, SiON, AlOx, FSG, BPSG, BSG, SiCN, SiCOH, or other suitable dielectric material is deposited over exposed portions of second dielectric material216, phase change (or heater) material238, and third dielectric material218to provide a dielectric material layer. The dielectric material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. Portions of the dielectric material layer are then etched to expose the top of second dielectric material216and phase change (or heater) material238and to provide fourth dielectric material220.

A bit line material, such as W, Cu, Al, or other suitable bit line material is deposited over exposed portions of second dielectric material216, phase change (or heater) material238, third dielectric material218, and fourth dielectric material220to provide a bit line material layer. The bit line material layer is deposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The bit line material layer is then planarized to expose the top of fourth dielectric material220and to provide second bit lines210. In one embodiment, where capping layer240is used as previously described and illustrated with reference toFIG. 10, the capping layer is removed prior to depositing the bit line material or the dielectric material.

Embodiments provide resistive memory cells including phase change elements programmed using a heater. The memory cells are accessed using a first bit line electrically coupled to a phase change element of each memory cell and a second bit line electrically coupled to a heater of each memory cell. In each memory cell, the heater is thermally coupled to the phase change element. The heater effectively heats phase change materials having low resistivity. In addition, since the programming signals are applied to the heater and not to the phase change element, there is no voltage threshold of the phase change element to overcome during programming. Further, since the heater is not in series with the phase change element, low resistance (set) states of the phase change element are easily sensed. The current density through each phase change element is also low and the temperature distribution in the phase change material is uniform, thereby improving the endurance of the phase change element.

While the specific embodiments described herein substantially focused on using phase change memory elements, the embodiments can be applied to any suitable type of resistance or resistivity changing memory elements.