SELF-ALIGNED BACKSIDE CONNECTIONS FOR TRANSISTORS

Provided is a semiconductor device. The semiconductor device comprises a plurality of logic devices. The logic devices have frontside wiring. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a logic device. The connection is self-aligned on at least two sides.

BACKGROUND

The present invention relates in general to semiconductor fabrication methods and resulting structures. More specifically, the present invention relates to backside interconnects providing power delivery to field-effect-transistors of semiconductor devices and methods of forming the same.

In an integrated circuit, transistors such as metal oxide semiconductor field effect transistors (MOSFETs) have a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode via a power distribution network.

SUMMARY

Embodiments of the present invention include fabrication methods and the corresponding structures. Some embodiments of the present disclosure include a semiconductor device. The semiconductor device comprises a plurality of logic devices. The logic devices have frontside wiring. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a logic device. The connection is self-aligned on at least two sides.

Further embodiments of the present disclosure include another semiconductor device. The semiconductor device comprises a plurality of nanosheet transistors. Each nanosheet transistor includes a source/drain epitaxy. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a nanosheet transistor. The connection is self-aligned on at least two sides. The semiconductor device further comprises a back-end-of-line (BEOL) structure. The semiconductor device further comprises one or more BEOL contacts. Each BEOL contact connects a source-drain epitaxy of a nanosheet transistor to the BEOL

Additional embodiments of the present disclosure include a fabrication method, system, and computer program product. The fabrication method comprises forming a BOX layer on top of a substrate. The method further comprises forming an etch stop layer in the BOX layer. The method further comprises patterning fin regions and filling with dielectric composite stack to create one or more isolation regions. The one or more isolation regions define a pattern for one or more self-aligned backside connections that are to be formed. The method further comprises forming one or more nanosheet transistors in the dielectric composite stack. The method further comprises removing the substrate to expose the one or more isolation regions. The method further comprises selectively removing the BOX layer to expose the bottom of a source/drain epitaxy of at least one nanosheet transistor. The method further comprises forming metal rails with connections to the bottom of the source/drain epitaxy in the region opened up by removal of the portion of the BOX layer.

DETAILED DESCRIPTION

Embodiments of the present invention are generally directed to semiconductor fabrication methods and resulting structures, and more particularly to backside interconnects providing power delivery to field-effect-transistors of semiconductor devices and methods of making the same. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

For purposes of the description hereinafter, when a first surface is referred to as being arranged “opposite” to a second surface, the first surface is different from the second surface, and the first surface is spaced apart from the second surface. For instances in which the surfaces are substantially planar, the first surface is substantially parallel to the second surface.

It is to be understood that as used herein, “an embodiment” means one or more embodiments that share a common aspect. For example, “a first embodiment” may include one or more embodiments that are related in that they all share a first common aspect, function, and/or feature. Likewise, “a second embodiment” may include one or more embodiments that are related in that they all share a second common aspect, function, and/or feature. Furthermore, a particular embodiment that has both the first common aspect, function, and/or feature and the second common aspect, function, and/or feature may be considered to be both a first embodiment and a second embodiment.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography.

Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (“RTA”). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present disclosure, an integrated circuit (IC) is a set of electronic circuits on one small flat piece (or “chip”) of semiconductor material. More specifically, large numbers of tiny transistors can be integrated into a small chip, and interconnects can be used to connect two or more circuit elements (such as transistors) on the chip together electrically. Interconnects can also be used to provide power to the transistors through a power distribution network (PDN) that utilizes buried power rails and via-to-buried power rails (VBPRs). This results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components.

The field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current in a semiconductor. FETs are devices with three terminals: a source, a gate, and a drain. FETs control the flow of current by the application of a voltage to the gate, which in turn alters the conductivity between the drain and source. More specifically, the FET controls the flow of electrons (or holes) from the source to drain by affecting the size and shape of a conductive channel created and influenced by voltage (or lack of voltage) applied across the gate and source terminals. (For simplicity, this discussion assumes that the body and source are connected.) This conductive channel is the stream through which electrons flow from source to drain.

FETs are also known as unipolar transistors since they involve single-carrier-type operation. In other words, a FET uses either electrons or holes as charge carriers in its operation, but not both. The source/drain of a FET is doped to produce either an n-type semiconductor (in which case the FET can be referred to as an NFET) or a p-type semiconductor (in which case the FET can be referred to as a PFET). When the voltage applied to the gate of the FET is larger than the threshold voltage, the charge carriers in the channel region of the FET are built up, which activates the FET (e.g., allowing current to flow between the source and the drain).

Many different types of field effect transistors exist. A gate-all-around (GAA) FET is a non-planar (3D) transistor designed such that the gate material surrounds the channel region on all sides. Accordingly, the contact between the gate and the channel is increased, which provides better electrical control over the channel. A GAAFET can be a PFET or an NFET. A gate-all-around n-type semiconductor may also be referred to herein as a GAA NFET. Similarly, a gate-all-around p-type semiconductor may also be referred to herein as a GAA PFET.

A nanosheet transistor is a type of GAA transistor in which one or more sheets of semiconductor material (e.g., Si) are used to create the transistor channels which are surrounded by the gate. As such, the gate is able to surround each sheet on all sides, thereby increasing the contact between the gate and the channel. Furthermore, the more nanosheets used by a transistor, the more contact surface area the gate has with the channel. This provides excellent control of current leakage within the transistor. Nanosheet transistors may be vertically aligned, with a bottom source/drain disposed below the nanosheets (e.g., between the nanosheets and the substrate) and a top source/drain disposed on the top of the nanosheets (opposite the bottom source/drain), or they may be horizontally aligned (e.g., a horizontal-transport GAAFET), where the current travels from the source to the drain in a horizontal direction.

In some embodiments, nanosheets of opposite polarity are horizontally arranged side-by-side. For example, a GAA PFET can be arranged next to a GAA NFET. Once arranged, a pair including a GAA PFET and an GAA NFET can be functionally interconnected and utilized as a complementary metal-oxide-semiconductor (CMOS) cell. In a CMOS cell, complementary pairs of PFETs and NFETs are used for logic functions.

In integrated circuits, interconnects are structures that connect two or more circuit elements together electrically. In addition to providing the electrical connection to the front end devices (such as transistors), interconnects also go all the way back to the power delivery networks. Thus, interconnects, and their surrounding support components, may be considered back-end-of-line (BEOL) components. One common type of interconnect is a power rail.

In standard logic cells, power to the devices (e.g., transistors) is supplied to the source/drain contacts through power rails in BEOL metal layers. Power rails typically run across multiple adjacent cells. Accordingly, since power rails are typically used to supply power to a number of cells, the power rails are often implemented with much larger sizes (specifically, larger widths) compared to standard routing tracks/signal lines that are used within the cells. For example, a power rail can be up to three to four times larger than a normal routing line. Thus, power rails often take up significant amounts of area within cell design. The larger critical dimension of power rails is necessary to maintain an adequate resistance through the power rail to maintain adequate power distribution targets, including IR drop and frequency, within the device

Embodiments of the present disclosure include a semiconductor device comprising one or more logic devices (e.g., a complementary FET (CFET)). The logic device(s) includes frontside wiring. The semiconductor device further comprises a backside power delivery (or distribution) network (BSPDN). The semiconductor device further comprises a self-aligned (on at least two sides) connection from the BSPDN to the source/drain epitaxy bottom of the logic device(s).

In some embodiments, the self-aligned connection from the BSPDN to the source/drain epitaxy bottom is a power or ground rail (e.g., a buried power rail) that is connected to multiple source/drain epitaxy regions in the same library track. Additionally, or alternatively, the power or ground rails may be connected to multiple source/drain epitaxy regions in adjacent library tracks. The rail perimeter edges of the power or ground rail may be defined by frontside patterned isolation regions.

In some embodiments, the self-aligned connection from the BSPDN to the source/drain epitaxy bottom is a backside contact. Two sides of the contact may be defined by the frontside patterned isolation regions. A pre-formed BOX layer may separate contacts on two sides from the frontside patterned isolation regions.

In some embodiments, a pre-formed etch stop layer is on top of the power and ground rails. The location of the etch stop layer within the BOX can be optimized for capacitance vs. integration challenges, as needed.

In some embodiments, a bottom dielectric isolation (BDI) layer is formed below the gate. The BDI may be any suitable dielectric material including, for example, SiO2, SiOCN, SiOC, or SiBCN. The BDI may help protect against gate metal damage during the backside Si removal.

In some embodiments, the semiconductor device further comprises a bulk semiconductor region below the logic device region. The bulk semiconductor region may be at the same or similar level as the power and/or ground rails.

With the above in mind, numerous embodiments of the present disclosure are provided for illustrative purposes only. Each embodiment varies as to one or more stages of the semiconductor fabrication process, though the resulting semiconductor devices are functionally similar. In a first embodiment of the present disclosure, the backside contact metallization layers (i.e., the backside rails) of adjacent NFETs (and/or PFETs) are isolated from each other. The adjacent NFETs are nevertheless connected to the BSPDN using a single backside wire/via that bridges the adjacent metallization layers.FIGS.2A-2Killustrate a process of fabricating an example of the first embodiment, with a completed FET in accordance with the first embodiment being shown inFIG.2K.

In a second embodiment of the present disclosure, the backside contact metallization layers (i.e., the backside rails) of adjacent FETs of the same polarity (e.g., adjacent NFETs and/or adjacent PFETs) are merged. Accordingly, the N-N and P-P regions of adjacent transistors have a shared backside rail. This may be done by utilizing shallow isolation regions during fabrication. The second embodiment may have a better process because of the connected N-N and P-P regions, but it is a more expensive process due to the additional masking step(s) required.FIGS.3A-3Cillustrate a few steps in the process of fabricating an example of the second embodiment, which otherwise follows a similar process to that shown with respect toFIGS.2A-2K, with a completed FET in accordance with the second embodiment being shown inFIG.3C.

In a third embodiment of the present disclosure, the backside contacts in the source/drain epitaxy regions are isolated from each other. This may be done by selectively removing a portion of the backside BOX layer and temporary fill material, as opposed to removing all of the backside BOX layer per the first and second embodiments.FIGS.4A-4Billustrate portions of a process of fabricating an example of the third embodiment, starting from an intermediate state. The intermediate state of the third embodiment is also an intermediate state of the first embodiment. In particular, the intermediate state for the third embodiment is the state shown inFIG.2H.

In a fourth embodiment of the present disclosure, the semiconductor device comprises a bulk substrate.FIGS.5A-5Iillustrate a process of fabricating an example of the fourth embodiment.FIG.6illustrates an example of the fourth embodiment in which the etch stop is completely removed.

In a fifth embodiment of the present disclosure, the etch stop of the semiconductor device is at least partially removed to create a larger opening for the backside metal fill. Otherwise, the fifth embodiment is substantially similar to the first embodiment.FIGS.7A-7Dillustrate a process of fabricating an example of the fifth embodiment.

It is to be understood that as used herein, “an embodiment” means one or more embodiments that share a common aspect. For example, “a first embodiment” may include one or more embodiments that are related in that they all share a first common aspect, function, and/or feature. Likewise, “a second embodiment” may include one or more embodiments that are related in that they all share a second common aspect, function, and/or feature. Furthermore, a particular embodiment that has both the first common aspect, function, and/or feature and the second common aspect, function, and/or feature may be considered to be both a first embodiment and a second embodiment.

Embodiments of the present disclosure further include a method of manufacturing a semiconductor device. The method comprises forming a substrate with an embedded etch stop layer in BOX. The method further comprises patterning fin regions and filling the trenches with dielectric to create a composite stack and define the pattern for self-aligned backside connections. The method further comprises etching the source/drain regions. The method further comprises patterning and etching below the source/drain regions in selected areas below the etch stop layer (for future backside connection). The method further comprises backfilling the etched regions with temporary material in selected regions below the active channels. The method further comprises forming the source/drain epitaxy, gates, middle-of-line (MOL), and back-end-of-line (BEOL).

The method further comprises flipping and bonding a carrier wafer to the semiconductor device. The method further comprises removing the top substrate material to expose the frontside defined isolation regions. The method further comprises selectively removing the BOX region and temporary fill material to expose the source/drain bottom. The method further comprises forming metal rails with connections to the source/drain bottom. The method further comprises forming the BSPDN with connection to the rails and finish wafer processing.

Embodiments of the present disclosure provide a number of advantages over current technologies. For example, the frontside defined backside power and ground rails are connected to the bottom of the source/drain epitaxy without any critical patterning on the backside. This direct contact, utilizing an etch stop layer, provides self-aligned connections, has better process margin, reduces the complexity by requiring no critical level backside patterning, improves source/drain etch and fill aspect ratio, and enables full backside merged power rails for reduced resistance and increased performance. For example, the direct connection to the bottom of the source/drain epitaxy can shrink the library height by approximately 30-40 nm.

Turning now to the figures,FIG.1depicts a plan view of an example semiconductor device100indicating a Y cross-section location and an X cross section location for the following figures, in accordance with embodiments of the present disclosure. The semiconductor device100includes a NFET region disposed next to a PFET region. Metal gates108cross the NFET and PET regions. The NFET region includes two NFET nanosheet transistors102and a backside power rail (BPR)104. Likewise, the PFET region includes two PFET nanosheet transistors106and a BPR104. As such,FIG.1shows four nanosheet transistors (2 PFET and 2 NFET transistors).

Furthermore, complementary pairs of PFET nanosheet transistors and NFET nanosheet transistors may be coupled together to create one or more CMOS cells. For example, the NFET transistor at the top of the NFET region may be paired with the PFET transistor at the bottom of the PFET region to create a CMOS cell.

The BPRs104may lie on a different level of the semiconductor device100and substantially overlap the NFET nanosheet transistors102and the PFET nanosheet transistors106. In other words, the BPR104may be below (for example) the NFETs and PFETs, as is illustrated by the dashed-and-dotted lines representing the edges of the BPR104substantially overlapping with the nanosheet transistors102,106.

FIG.1also shows the location of the cross-sectional cuts that are illustrated inFIGS.2A-7D. Cut Y runs across the nanosheet transistors in the gate region, and cut X runs along a length of a single nanosheet102and crosses three gates108. The subsequent figures show cross-sectional views along these cuts Y and X after particular fabrication operations.

Turning now toFIGS.2A-7D, shown are fabrication processes for fabricating a semiconductor device having a self-aligned backside contact integration, in accordance with various embodiments. In particular,FIGS.2A-7Dshow the semiconductor device at various stages in the process and in different embodiments. For example,FIGS.2A-2Kshow the semiconductor device100ofFIG.1during fabrication in accordance with a first embodiment, with each figure building on the previous (e.g.,FIG.2Bshows the semiconductor device ofFIG.2Aafter one or more additional fabrication operations have been performed). Additionally, figures that share the same number (e.g.,FIG.2A,FIG.2B, andFIG.2C) show the semiconductor device according to the same embodiment.

Furthermore, each figure shows two different regions associated with the two cuts discussed above. In particular, each figure has a cross-sectional view of the across-gate, or nanosheet, region (e.g., across-gate region201, which follows cut X) shown on the left and a cross-section view of the gate region (e.g., gate region299, which follows cut Y) shown on the right.

Referring now toFIG.2A, illustrated is a cross-sectional view of an example semiconductor device200at an intermediate stage in the fabrication process, in accordance with embodiments of the present disclosure. In particular,FIG.2Aillustrates the semiconductor device200after the formation of an initial, or starting, semiconductor stack on a wafer. The semiconductor stack comprises a BOX SiO2layer204deposited on top of a substrate202. The thickness of the BOX layer can be varied depending on the desired process margins. An etch stop is embedded within the BOX layer204uniformly across the wafer. The etch stop206can be positioned within the BOX layer204based on the desired process/performance tradeoff (e.g., higher performance, with worse process or vice versa).

A first sacrificial layer208is deposited on top of the BOX layer204. The first sacrificial layer208may be, for example, a sacrificial high-Ge % SiGe such as, for example, SiGe55%. Alternating layers of a second sacrificial material210and a semiconductor (e.g., Si)212may then be stacked on top of the first sacrificial material layer208. The second sacrificial layer210may be a sacrificial low-Ge % SiGe layer such as, for example, SiGe25%. The layers of the semiconductor212will end up being the nanosheet layers that make up the semiconductor channel for the semiconductor device200.

After creating the nanosheet stack, a hardmask may be deposited on a portion of the stack. After depositing the hardmask on the semiconductor device200, the nanosheet stack may be patterned. This is shown inFIG.2B. Patterning the nanosheet stack may include performing, for example, an extreme ultraviolet lithography (EUV) and/or an RIE operation to create a plurality of nanosheet structures (referred to herein as fins) separated by trenches214in the nanosheet region201.

Additionally, backside contact isolation regions (also referred to herein simply as “isolation regions”) may be formed for guiding the self-aligned backside contacts. The isolation regions may be formed in both the nanosheet region201and the gate region299of the semiconductor device200. The isolation regions may comprise a liner material216with an oxide fill218. The liner may be, for example, SiN. The isolation regions may further act as shallow trench isolation (STI) layers in portions of the BOX layer204that are lateral to the patterned fins. The STI may prevent electric current leakage between the adjacent semiconductor components (e.g., between adjacent nanosheet FETs).

After forming the fins and the isolation regions, dummy gates220may be formed on the semiconductor device200. This is shown inFIG.2C. The dummy gates220may be made of any suitable material as would be recognized by a person of ordinary skill in the art. In some embodiments, the dummy gates220are a thin layer of SiO2 followed by bulk amorphous silicon (a-Si). A hardmask222may also be formed on top of the dummy gates220. The dummy gates may be patterned using the hardmask, as shown inFIG.2C.

Referring now toFIG.2D, after forming the dummy gates220and hardmask222, spacers224are deposited on top of the semiconductor device200. The spacers224are then etched (e.g., using RIE) so that the spacers224are removed from the substantially horizontal surfaces (e.g., removed from the top of the hardmask222and the top of the top semiconductor layer212) while remaining deposited along the sidewalls of the dummy gates220and the hardmask222.

Additionally, the first sacrificial layer208may be selectively removed and replaced with the spacer material224. In particular, the first sacrificial layer208may be selectively removed without removing the second sacrificial layers210, and the first sacrificial layer208may be replaced with the spacer material224to create a bottom dielectric isolation (BDI) layer. The BDI layer may be that part of the spacer layers224that sit between the BOX layer204and the fins. As shown inFIG.2D, the first sacrificial layer208may be removed from the entire semiconductor device200, including the nanosheet region201and the gate region299.

The spacer layers224may be made out of, for example, SiO2, SiOCN, SiOC, SiBCN. The spacer layers224may be deposited on the semiconductor device200after removal of the first sacrificial layer208. In some embodiments, a spacer RIE operation may be performed to remove the spacer layer414from on top of the STIs218except along the sidewalls of the dummy gates220.

After forming the one or more spacer layers224, a nanosheet recess operation may be performed. This is shown inFIG.2E. The nanosheet recess operation may include performing a selective etching operation that removes the portions of the second sacrificial layers210, the semiconductor layers212, and the BDI layer (e.g., bottom spacer224layer) that are not below the hardmask or spacers224, resulting in a plurality of trenches226. However, the spacer sidewalls224and the STI218are largely unaffected by the selective etching operation, though the spacer material may be etched such that it is slightly shorter and/or thinner than prior to etching. A result of the selective etching is that the top of the BOX layer204between the spacer sidewalls in the gate region299are exposed.

InFIG.2E, the hardmask222and the spacer layers224act to largely protect the semiconductor stack below the hardmask222and the spacer layers224, while the portion of the semiconductor stack between the spacer layers224are etched down into the BOX layer204.

Referring now toFIG.2F, an organic planarization layer (OPL)228is deposited on top of the semiconductor device200. A self-aligned backside etch stop patterning is then performed to remove a portion of the BOX layer204and the etch stop206at the bottoms of the trenches226. The etch stop206allows for reduced and well-controlled self-aligned etch depth.

Referring now toFIG.2G, a temporary contact fill242is deposited into the trenches226. The temporary contact fill242may be, for example, an oxide. In some embodiments, the temporary contact fill242is selected from a low-k dielectric material, SiN, or SiGe. A subsequent SiGe indentation operation is performed, resulting in exposed portions of the second sacrificial layers210in the trenches226being partially etched back. An inner spacer is then formed where the second sacrificial layers210were etched back. The inner spacer may be made out of, for example, SiO2, SiOCN, SiOC, SiBCN.

Next, a source/drain epitaxy232is grown in the trenches226. The source/drain epitaxy232may be grown in the trenches226between the spacer sidewalls224in the gate region299. A cyclic epi-etch back process may be used to ensure that the epi growth from exposed sidewalls of nanosheets can be suppressed. As shown inFIG.2G, the source/drain epitaxy232extends above the top of the nanosheet stack. In other words, the top surface of the source-drain epitaxy232is above the top of the uppermost Si layer212.

After growing the source/drain epitaxy232, the second sacrificial layers210are released, a gate cut may be performed, and the HKMG layer230is formed on top of and around the remaining semiconductor material212in the gate region299. In other words, during this stage, a replacement high-k metal gate is formed in place of each dummy gate220and SiGe layers210. The HKMG layer230includes the high-k dielectric such as HfO2, ZrO, HfLaOx, HfAlOx, etc, and workfunction metal (WFM) such as TiN, TiC, TiAlC, TiAl, etc and it may further comprise optional low resistance conducting metals such as W, Co and Ru.

Those skilled in the art will recognize that a “replacement metal gate” refers to a gate, which replaces a previously formed dummy gate (also referred to herein as a sacrificial gate, a non-active gate, or a non-gate) and becomes an active component of the semiconductor structure being formed. The work function metal can comprise a metal selected so as to have a specific work function appropriate for a given type FET (e.g., an N-type FET or a P-type FET). For example, for a silicon-based N-type FET, the work function metal can comprise hafnium, zirconium, titanium, tantalum, aluminum, or alloys thereof, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide, so that the work function metal has a work function similar to that of N-doped polysilicon. For a silicon-based P-type FET, the work function metal can comprise, for example, ruthenium, palladium, platinum, cobalt, or nickel, or a metal oxide (e.g., aluminum carbon oxide or aluminum titanium carbon oxide) or a metal nitride (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, or tantalum aluminum nitride) so that the work function metal has a work function similar to that of P-doped polysilicon.

Next, the middle-of-line (MOL) and back-end-of-line (BEOL)236structures may be formed. The semiconductor device200may then be bonded to a carrier wafer238. The MOL structures may include one or more epitaxy and/or gate contacts240, as well as an inter-layer dielectric (ILD)234deposited on top of the semiconductor device200(e.g., as shown inFIG.2G, in which an ILD234is on top of the metal gate230). The epitaxy contact240may be made out of any suitable material including, for example, a silicide liner at bottom of the contact such as Ti, Ni, NiTi, NiPt, and a conductive metal such as Ru or W, or Co, with a thin adhesion metal liner such as TiN. The BEOL236may include a number of interconnects or other structures.

It is to be understood that the dimensions of the MOL and BEOL236structures, as well as the carrier wafer238, are not necessarily drawn to scale. The MOL and BEOL236structures and the carrier wafer238may be formed using any suitable processes, as would be recognized by a person of ordinary skill in the art. In some embodiments, BEOL236and carrier wafer238may be pre-fabricated and then bonded with the semiconductor device200.

The ILD234may surround and cover the source/drain epitaxy232, the STI218, the liner216, the spacer sidewalls224, and the metal gate230in the gate region299, as shown inFIG.2G. The ILD234can include any suitable material(s) known in the art, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. The ILD234can be formed using any method known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

Next, the wafer is flipped and the substrate202is removed. This is shown inFIG.2H. The substrate202may be removed through a selective etching process that stops on the BOX layer204, which acts as an etch stop. After flipping the wafer, the BOX layer204that is below (above in the flipped image) the etch stop206is removed, thereby exposing the etch stop. Additionally, the temporary fill242is removed. This is shown inFIG.2I.

Backside contact metallization is then performed. This is shown inFIG.2J. the backside contact metallization operation may comprise a precontact clean followed by depositing a conductive backside contact243and performing a CMP process. The CMP process may planarize the top of the semiconductor device200such that the top of the conductive backside contact243is coplanar with the top of the liner216.

The conductive backside contact243may be formed of any suitable conductive material such as, for example, a silicide liner at the bottom of the contact such as Ti, Ni, NiTi, NiPt, and a conductive metal fill such as Ru or W, or Co, with a thin adhesion metal liner such as TiN.

Next, an ILD248may be formed on top of the conductive backside contact243. This is shown inFIG.2K. Backside vias and wires are then formed in the ILD248. In particular, BPRs244may then be formed in the ILD248. The BPRs244may include a Vss and a Vdd BPR. The Vdd BPR may be formed at least partially on top of the conductive backside contact243. In particular, the BPR244is formed such that it is in contact with two of the conductive backside contacts243in the nanosheet region201. For example, the BPR244may bridge the conductive backside contacts243for adjacent NFETs, as shown inFIG.2K. The BSPDN246is then formed on top of the BPRs244.

As shown inFIG.2K, the backside contacts243are self-aligned. In particular, the backside contacts have a self-aligned contact250with the source/drain epitaxy and a self-alignment252with the STIs218.

Turning now toFIGS.3A-3C, shown are cross-sectional views of a semiconductor device300at various stages in the fabrication process, in accordance with some embodiments of the present disclosure. As withFIGS.2A-2K,FIGS.3A-3Cshow cross-section views of the nanosheet region301and the gate region399of the semiconductor device300. The fabrication process shown inFIGS.3A-3Care substantially similar to those shown inFIGS.2A-2K. Accordingly, only operations or structures that differ from those shown inFIGS.2A-2Kare illustrated inFIGS.3A-3C.

Following the formation of the nanosheet stack (e.g., as shown inFIG.2A), the backside contact isolation regions (also referred to herein simply as “isolation regions”) may be formed for guiding the self-aligned backside contacts. This is shown inFIG.3A. The isolation regions may be formed in both the nanosheet region301and the gate region399of the semiconductor device300. The isolation regions may comprise a liner material216with an oxide fill218. The liner may be, for example, SiN. The isolation regions may further act as shallow trench isolation (STI) layers in portions of the BOX layer204that are lateral to the patterned fins. The STI may prevent electric current leakage between the adjacent semiconductor components (e.g., between adjacent nanosheet FETs).

The isolation regions shown inFIG.3Amay be formed in substantially the same way as the isolation regions were formed inFIG.2B. In other words, the semiconductor device300shown inFIG.3Amay be an alternative embodiment from the semiconductor device200shown inFIG.2B. The difference between the semiconductor device300and the semiconductor device200is that some of the isolation regions of the semiconductor device300do not extend all the way down to the substrate. In particular, the isolation regions separating adjacent NFETs may only extend partially into the BOX layer204. Similarly, the isolation regions separating adjacent PFETs may only extend partially into the BOX layer204. Meanwhile, the isolation regions separating an NFET from an adjacent PFET may extend all the way through the BOX layer204to the substrate202, as shown inFIG.3A.

Referring now toFIG.3B, shown is the semiconductor device300after backside contact metallization has been performed. In other words, the semiconductor device300shown inFIG.3Bis at substantially the same stage as the semiconductor device200shown inFIG.2J. However, as shown inFIG.3B, the metallization operation results in conductive backside contacts243that are shared/merged in the nanosheet region301. This occurs because the isolation regions did not extend all the way through the BOX layer204inFIG.3A. In particular, as shown inFIG.3B, the conductive backside contacts243for adjacent NFETs are merged in the nanosheet region301, as are the conductive backside contacts243for adjacent PFETs.

Next, an ILD248may be formed on top of the conductive backside contact243. This is shown inFIG.3C. BPRs244may then be formed in the ILD248. The BPRs244may include a Vss and a Vdd BPR. The BPR244may be formed at least partially on top of the conductive backside contact243. The BSPDN246is then formed on top of the BPRs244.

Turning now toFIGS.4A-4B, shown are cross-sectional views of a semiconductor device400at various stages in the fabrication process, in accordance with some embodiments of the present disclosure. As withFIGS.2A-2K,FIGS.4A-4Bshow cross-section views of the nanosheet region401and the gate region499of the semiconductor device400. The fabrication process shown inFIGS.4A-4Bis substantially similar to the fabrication process shown inFIGS.2A-2K. Accordingly, only operations or structures that differ from those shown inFIGS.2A-2Kare illustrated inFIGS.4A-4B.

Following the wafer flip and removal of the substrate202(e.g., as shown inFIG.2H), the BOX layer204may be selectively etched above the temporary contact fill242and the temporary contact fill242may be removed to create trenches402. This is shown inFIG.4A. The semiconductor device400shown inFIG.4Ais an alternative to the semiconductor device200shown inFIG.2I, with the difference relating to the amount of the BOX layer that is removed. In other words, unlike the semiconductor device200shown inFIG.2I, in which the entire BOX layer204was removed along with the temporary contact fill242, in the semiconductor device400shown inFIG.4A, only portions of the BOX layer204are removed.

Next, the backside contact metallization is performed to create backside contacts404in the trenches402. This is shown inFIG.4B. Following the creation of the backside contacts404, the BPRs244and BSPDN246may be formed in substantially the same manner described above.

Turning now toFIGS.5A-5I, shown are fabrication processes for fabricating a semiconductor device500having a self-aligned backside contact integration, in accordance with various embodiments. In particular,FIGS.5A-5Ishow the semiconductor device500at various stages in the process and in different embodiments. The semiconductor device500and the process shown inFIGS.5A-5Iis substantially similar to the semiconductor device200and process shown inFIGS.2A-2J. However, the semiconductor device500shows an embodiment where there is a bulk substrate (e.g., Si layer504) with the etch stop506on top of the bulk substrate.

Referring now toFIG.5A, illustrated is a cross-sectional view of an example semiconductor device500at an intermediate stage in the fabrication process, in accordance with embodiments of the present disclosure. In particular,FIG.5Aillustrates the semiconductor device500after the formation of an initial, or starting, semiconductor stack on a wafer. The semiconductor stack comprises a Silayer504deposited on top of a substrate502. The thickness of the Si layer can be varied depending on the desired process margins. An etch stop layer506is deposited on top of the Si layer504uniformly across the wafer. The etch stop layer506can be a BDI.

A first sacrificial layer508is deposited on top of the etch stop layer506. The first sacrificial layer508may be, for example, a sacrificial high-Ge % SiGe such as, for example, SiGe55%. Alternating layers of a second sacrificial material510and a semiconductor (e.g., Si)512may then be stacked on top of the first sacrificial material layer508. The second sacrificial layer510may be a sacrificial low-Ge % SiGe layer such as, for example, SiGe25%. The layers of the semiconductor512will end up being the nanosheet layers that make up the semiconductor channel for the semiconductor device500.

Referring now toFIG.5B, after creating the nanosheet stack, additional fabrication processes that are substantially similar to those described with reference toFIGS.2B-2Eare performed. For the sake of brevity, the specifics of these steps are omitted. The resulting semiconductor device500includes backside contact isolation regions for guiding the self-aligned backside contacts. The isolation regions may be formed in both the nanosheet region501and the gate region599of the semiconductor device500. The isolation regions may comprise a liner516with an oxide fill518. The liner may be, for example, SiN. The isolation regions may further act as shallow trench isolation (STI) layers in portions of the Si layer504that are lateral to the patterned fins. The STI may prevent electric current leakage between the adjacent semiconductor components (e.g., between adjacent nanosheet FETs).

The semiconductor device500may further include dummy gates520. The dummy gates520may be made of any suitable material as would be recognized by a person of ordinary skill in the art. In some embodiments, the dummy gates520are a thin layer of SiO2 followed by bulk amorphous silicon (a-Si). A hardmask522may also be formed on top of the dummy gates520. The dummy gates may be patterned using the hardmask.

The semiconductor device500further includes spacers524. The spacers524may be deposited on top of the semiconductor device500and then etched (e.g., using RIE) so that the spacers524are removed from the substantially horizontal surfaces (e.g., removed from the top of the hardmask522and the top of the top semiconductor layer512) while remaining deposited along the sidewalls of the dummy gates520and the hardmask522.

Additionally, the first sacrificial layer508may be selectively removed and replaced with the spacer material524. In particular, the first sacrificial layer508may be selectively removed without removing the second sacrificial layers510, and the first sacrificial layer508may be replaced with the spacer material524to create a BDI layer. The BDI layer may be that part of the spacer layers524that sit between the Si layer504and the fins.

The spacer layers524may be made out of, for example, SiO2, SiOCN, SiOC, SiBCN. The spacer layers524may be deposited on the semiconductor device500after removal of the first sacrificial layer508. In some embodiments, a spacer RIE operation may be performed to remove the spacer layer524from on top of the STIs518except along the sidewalls of the dummy gates520.

After forming the one or more spacer layers524, a nanosheet recess operation may be performed. The nanosheet recess operation may include performing a selective etching operation that removes the portions of the second sacrificial layers510, the semiconductor layers512, the BDI layer (e.g., bottom spacer524layer), and the Si layer504that are not below the hardmask or spacers524, resulting in a plurality of trenches526. However, the spacer sidewalls524and the STI518are largely unaffected by the selective etching operation, though the spacer material may be etched such that it is slightly shorter and/or thinner than prior to etching. A result of the selective etching is that the top of the substrate502between the spacer sidewalls in the gate region599is exposed.

Additionally, as shown inFIG.5B, an organic planarization layer (OPL)528is deposited on top of the semiconductor device500. A self-aligned backside etch stop patterning is then performed to remove a portion of the Si layer504and the etch stop506at the bottoms of the trenches526. In particular, the Si layer504is removed down to the substrate502.

Referring now toFIG.5C, shown in the semiconductor device500after performance of additional fabrication operation, which are substantially similar to those discussed above with respect toFIGS.2A-2Kand have been omitted for brevity. The semiconductor device500includes temporary contact fill542deposited at the bottom of the trenches526(shown inFIG.5B). The temporary contact fill542may be, for example, an oxide. In some embodiments, the temporary contact fill542is selected from a low-k dielectric material, SiN, or SiGe. A subsequent SiGe indentation operation is performed, resulting in exposed portions of the second sacrificial layers510in the trenches526being partially etched back. An inner spacer524is then formed where the second sacrificial layers510were etched back. The inner spacer may be made out of, for example, SiO2, SiOCN, SiOC, SiBCN.

Next, a source/drain epitaxy540is grown in the trenches526. The source/drain epitaxy540may be frown in the trenches526between the spacer sidewalls524in the gate region599. A cyclic epi-etch back process may be used to ensure that the epi growth from exposed sidewalls of nanosheets can be suppressed. As shown inFIG.5C, the source/drain epitaxy540extends above the top of the nanosheet stack. In other words, the top surface of the source-drain epitaxy540is above the top of the uppermost Si layer512.

After growing the source/drain epitaxy540, the second sacrificial layers510are released, a gate cut is performed, and the HKMG layer530is formed on top of and around the remaining semiconductor material512in the gate region599. In other words, during this stage, a replacement high-k metal gate is formed in place of each dummy gate520and SiGe layers510. The HKMG layer530includes the high-k dielectric such as HfO2, ZrO, HfLaOx, HfAlOx, etc, and workfunction metal (WFM) such as TiN, TiC, TiAlC, TiAl, etc and it may further comprise optional low resistance conducting metals such as W, Co and Ru.

Those skilled in the art will recognize that a “replacement metal gate” refers to a gate, which replaces a previously formed dummy gate (also referred to herein as a sacrificial gate, a non-active gate, or a non-gate) and becomes an active component of the semiconductor structure being formed. The work function metal can comprise a metal selected so as to have a specific work function appropriate for a given type FET (e.g., an N-type FET or a P-type FET). For example, for a silicon-based N-type FET, the work function metal can comprise hafnium, zirconium, titanium, tantalum, aluminum, or alloys thereof, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide, so that the work function metal has a work function similar to that of N-doped polysilicon. For a silicon-based P-type FET, the work function metal can comprise, for example, ruthenium, palladium, platinum, cobalt, or nickel, or a metal oxide (e.g., aluminum carbon oxide or aluminum titanium carbon oxide) or a metal nitride (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, or tantalum aluminum nitride) so that the work function metal has a work function similar to that of P-doped polysilicon.

Next, the middle-of-line (MOL) and back-end-of-line (BEOL)534structures may be formed. The semiconductor device500may then be bonded to a carrier wafer536. The MOL structures may include one or more epitaxy and/or gate contacts538, as well as an inter-layer dielectric (ILD) layer532deposited on top of the semiconductor device500. The epitaxy contact538may be made out of any suitable material including, for example, a silicide liner at bottom of the contact such as Ti, Ni, NiTi, NiPt, and a conductive metal such as Ru or W, or Co, with a thin adhesion metal liner such as TiN. The BEOL534may include a number of interconnects or other structures.

It is to be understood that the dimensions of the MOL and BEOL534structures, as well as the carrier wafer536, are not necessarily drawn to scale. The MOL and BEOL534structures and the carrier wafer536may be formed using any suitable processes, as would be recognized by a person of ordinary skill in the art. In some embodiments, BEOL534and carrier wafer536may be pre-fabricated and then bonded with the semiconductor device500.

The ILD532may surround and cover the source/drain epitaxy540, the STI518, the liner516, the spacer sidewalls524, and the metal gate530in the gate region599, as shown inFIG.5C. The ILD532can include any suitable material(s) known in the art, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. The ILD532can be formed using any method known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

Next, the wafer is flipped and the substrate502is removed. This is shown inFIG.5D. The substrate502may be removed through a selective etching process that stops on the Si layer504, which acts as an etch stop. After flipping the wafer, a lithography mask544is deposited on top of the semiconductor device500. This is shown inFIG.5E. In particular, the lithography mask544is deposited over the Si layer504and the liner516. However, the temporary fill542remains exposed (e.g., uncovered) by the lithography mask544.

After the lithography mask544is deposited on the semiconductor device500, the temporary fill542is removed. This is shown inFIG.5F. The resulting semiconductor device500has trenches546formed directly below (above in the figure) the source/drain epitaxy540. Next, backside contacts548are formed in the trenches546left behind by the temporary fill542. This is shown inFIG.5G. The backside contacts548are formed by a backside contact metallization operation that may comprise a precontact clean followed by depositing a conductive backside contact548on the source/drain epitaxies540and performing a CMP process. The CMP process may planarize the top of the semiconductor device500such that the top of the conductive backside contact548is coplanar with the top of the liner516and the remaining Si layer504. The conductive backside contacts548may be formed of any suitable conductive material such as, for example, a silicide liner at the bottom of the contact such as Ti, Ni, NiTi, NiPt, and a conductive metal fill such as Ru or W, or Co, with a thin adhesion metal liner such as TiN.

Following formation of the backside contacts548, the Si layer504is recessed. This is shown inFIG.5H. A low-k dielectric550is then formed where the Si layer504previously existed. This is shown inFIG.5I. In some embodiments, the low-k dielectric550is deposited such that air gaps552are formed in at least a portion of the low-k dielectric550as well. In some embodiments, the etch stop layer is removed prior to deposition of the low-k dielectric550. This is shown inFIG.6. The etch stop layer may be removed using any suitable etching technique, as would be understood by a person of ordinary skill in the art.

Turning now toFIGS.7A-7D, shown are cross-sectional views of a semiconductor device700at various stages in the fabrication process, in accordance with some embodiments of the present disclosure. As withFIGS.2A-2K,FIGS.7A-7Dshow cross-section views of the nanosheet region701and the gate region799of the semiconductor device700. The fabrication process shown inFIGS.7A-7Dare substantially similar to those shown inFIGS.2A-2K. Accordingly, only operations or structures that differ from those shown inFIGS.2A-2Kare illustrated inFIGS.7A-7D.

Referring first toFIG.7A, shown in the semiconductor device700after the formation of the BEOL236and binding of the carrier wafer238. In other words,FIG.7Ashows the semiconductor device700following performance of the operations discussed with respect toFIGS.2A-2G. As such,FIG.7Ais substantially similar toFIG.2G, with the only difference being that the temporary fill702shown inFIG.7Ahas a different shape than the temporary fill242shown inFIG.2G. In particular, the temporary fill702has a trapezoidal shape, as opposed to the rectangular shape of the temporary fill242, due to real-world limitations of the etching process used to create the region occupied by the temporary fill702.

The shape of the temporary fill702may not be suitable for backside metal fill (e.g., metallization). Accordingly, after flipping the wafer and removing the substrate202, the BOX layer204may be selectively etched (e.g., using RIE) to remove portions of the BOX layer204below the temporary fill702. This is shown inFIG.7B. The selective etching of the BOX layer204results in trenches704disposed above the now exposed source/drain epitaxies. The RIE may be selective to (i.e., stop at) the etch stop206.

Next, the exposed portions of the etch stop206are removed. This is shown inFIG.7C. As can be seen inFIG.7C, only those portions of the etch stop206that were exposed by the etching of the BOX layer204may be removed. After removal of a portion of the etch stop206, the backside contacts706are formed. This is shown inFIG.7D. The partial removal of the etch stop206may result in an easier metal fill by increasing the width of the trench in which the backside contacts706are formed.

It is to be understood that the aforementioned advantages are example advantages and should not be construed as limiting. Embodiments of the present disclosure can contain all, some, or none of the aforementioned advantages while remaining within the spirit and scope of the present disclosure.

Detailed embodiments of the structures of the present invention are described herein. However, it is to be understood that the embodiments described herein are merely illustrative of the structures that can be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features can be exaggerated to show details of particular components. Therefore, specific structural and functional details described herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present description

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiN, SiCN, SiCO, or SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe(1-x)where x is less than or equal to 1, and the like. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

It should be noted that not all masking, patterning, and lithography processes are shown because a person of ordinary skill in the art would recognize where masking and patterning processes are utilized to form the identified layers and openings, and to perform the identified selective etching processes, as described herein.

As discussed herein, embodiments of the present disclosure include a method. The method may be performed by, for example, a computer system that controls semiconductor fabrication machinery. As such, the method may be embodied as a computer program product having software instructions on a storage medium. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

When different reference numbers comprise a common number followed by differing letters (e.g.,100a,100b,100c) or punctuation followed by differing numbers (e.g.,100-1,100-2, or100.1,100.2), use of the reference character only without the letter or following numbers (e.g.,100) may refer to the group of elements as a whole, any subset of the group, or an example specimen of the group.