Feedforward limited switch dynamic logic circuit

The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.

CROSS REFERENCE TO RELATED APPLICATION

The present invention is related to U.S. patent application Ser. No. 10/116,612, filed Apr. 4, 2002, entitled “CIRCUITS AND SYSTEMS FOR LIMITED SWITCH DYNAMIC LOGIC,” which is incorporated by reference herein.

TECHNICAL FIELD

The present invention relates in general to metal oxide silicon (MOS) dynamic logic circuits.

BACKGROUND INFORMATION

Modem data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock on each cycle may consume power even when the logical value of the output is otherwise unchanged.

This may be appreciated by referring toFIG. 1.1illustrating an exemplary three-input OR dynamic logic gate, and the accompanying timing diagram,FIG. 1.2. Dynamic logic100includes three inputs a, b and c coupled to a corresponding gate of NFETs102a–102c. During an evaluate phase N1(116) of clock104, NFET106is active, and if any of inputs a, b or c are active, dynamic node108is pulled low, and the output OUT goes “high” via inverter110. Thus, referring toFIG. 1.2, which is illustrative, at t1, input a goes high during a precharge phase N2of clock104. During the precharge phase N2of clock104, dynamic node108is precharged via PFET112. Half-latch PFET114maintains the charge on dynamic node108through the evaluate phase, unless one or more of inputs a, b or c is asserted. In the illustrative timing diagrams inFIG. 1.2, input a is “high” having a time interval t1through t2that spans approximately 2½ cycles of clock104, which includes evaluation phases,116and118. Consequently, dynamic node108undergoes two discharge-precharge cycles,124and126. The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase,124and126. Because the output is discharged during the precharge phase of dynamic node108, even though the Boolean value of the logical function is “true” (that is, “high” in the embodiment of OR gate100) the dynamic logic dissipates power even when the input signal states are unchanged.

Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.

Limited switching dynamic logic (LSDL) circuits produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Co-pending U.S. patent application entitled, “CIRCUITS AND SYSTEMS FOR LIMITED SWITCH DYNAMIC LOGIC,” Ser. No. 10/116,612 filed Apr. 4, 2002 and commonly owned, recites such circuits. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement.

A logic buffer is a logic circuit that isolates or “buffers” a logic signal. It may be used to increase the fan-out of a logic signal. In some cases, a buffer also inverts the logic signal, thus a logic inverter may be thought of as an inverting buffer. As with standard logic functions, there may be static and clocked buffers. The LSDL logic technology uses both static devices and LSDL logic devices. In standard LSDL, a buffer is realized by replacing the logic tree with a single device. In this way, a logic signal coupled to the data input is clocked into the LSDL buffer and a latched output and its inversion are generated. Because there are a large number of buffers used in any modern integrated circuit (IC) design, buffers are key and perhaps the primary power contributors in any logic design. This is equally true for LSDL designs.

There is, therefore, a need for an LSDL buffer design that maintains all of the LSDL circuit advantages over other dynamic logic while reducing the dynamic power dissipated.

SUMMARY OF THE INVENTION

The pull down device in inverting data output stage of an LSDL gate is split into a large NFET and a small NFET. The large NFET is gated by a feedforward pulse that is generated only when the logic state of the inverting data output is a logic zero and the dynamic node evaluates to a logic zero. The dynamic node is coupled to a gated inverter that inverts the state of the dynamic node. If the inverting data output is a logic one, then an inverter inverts this state and enables the gated inverter. The output of the gated inverter generates a logic one feedforward pulse when the inverting data output is a logic one and the dynamic node evaluates to a logic zero. The logic one feedforward pulse turns ON the large NFET which quickly pulls the inverting data output to a logic zero. The small NFET acts as a keeper and is turned ON through the normal LSDL logic path. When the inverting data output is a logic zero, then the large NFET remains OFF reducing switching power and leakage power. Since the largest NFET in the feedforward LSDL logic gate is pulse driven, the remaining FET devices may be scaled down in size further reducing power as they in turn drive smaller devices. Even though additional circuitry is added for the gated inverter and the inverting stage there is a net reduction in device area and thus power savings.

DETAILED DESCRIPTION

FIG. 2.1illustrates a standard limited switch dynamic logic (LSDL) device200. In general, LSDL device200receives a plurality, n, of inputs202a. . .202fprovided to logic tree204, and outputs a Boolean combination of the inputs. The particular Boolean function performed by LSDL device200is reflected in the implementation of logic tree204(accounting for the inversion performed by the inverter formed by n-channel field effect transistor (NFET)206and p-channel field effect transistor (PFET)208). Logic tree204is coupled between the drain of PFET212and the drain of NFET214, node216. The junction of the logic tree204and the drain of PFET212forms dynamic node210.

For example, FIG.2.2.1illustrates logic tree230including three parallel connected NFETs,231,233and235. Logic tree230may be used to provide a logic device generating the logical NOR of the three input signals coupled to corresponding ones of the gates of NFETs231,233and235, a, b and c (as indicated by the Boolean expression250in FIG.2.2.1) and accounting for the inversion via NFET206and PFET208. Similarly, FIG.2.2.2illustrates a logic tree240including three serially connected NFETs237,239and241. Logic tree240may be used in conjunction with the logic device200to generate the logical NAND of the three input signals a, b and c (as indicated by the Boolean expression260in FIG.2.2.2).

Returning to FIG.2.2.1, dynamic node210is coupled to the common junction of the gates of NFET206and PFET208which invert the signal on dynamic node210. The inversion of the signal on dynamic node210is provided on Out218a. The transistor pair,206and208, is serially coupled to parallel NFETs220and222. NFET220is switched by clock signal224. Thus, during the evaluate phase of clock signal224, the inverter pair, NFET206and PFET208, are coupled between the supply rails by the action of NFET220.

The operation of LSDL device200during the evaluate phase, N1, may be further understood by referring toFIG. 2.3illustrating an exemplary timing diagram corresponding to the dynamic logic circuit ofFIG. 2.1in combination with a logic tree embodiment230of FIG.2.2.1. In this way, for purposes of illustration, the timing diagram inFIG. 2.3is the counterpart to the timing diagram inFIG. 1.2for the three-input OR gate100depicted inFIG. 1.1. As shown, input a is “high” or “true” between t1and t2. In the evaluate phase, N1of clock signal224, dynamic node210is pulled down (intervals T1). In these intervals, Out218ais held high by the action of the inverter formed by transistors206and208, which inverter is active through the action of NFET220as previously described. In the intervening intervals, T2, dynamic node210is pulled up via the action of the precharge phase, N2of clock signal224, and PFET212. In these intervals, the inverter is inactive as NFET220is off. Out218ais held “high” by the action of inverter226and PFET228. Note also that the output of inverter226may provide a complementary output, Out N218b. (Thus, with respect to the three-input logic trees in FIGS.2.2.1and2.2.2, the corresponding logic device represents a three-input OR gate and a three-input AND gate, respectively.)

Returning toFIG. 2.1, if the logic tree evaluates “high”, that is the Boolean combination of inputs202a. . .202drepresented by logic tree204, evaluate high, whereby dynamic node210maintains its precharge, Out218ais discharged via NFET206and NFET220. In the subsequent precharge phase, N2, of clock signal224, Out218ais latched via the action of inverter226and NFET222. Thus, referring again toFIG. 2.3, corresponding to the three input OR embodiment of logic device200and logic tree230(FIG.2.2.1) at t2input a falls, and in the succeeding evaluate phase of clock signal224, dynamic node210is held high by the precharge. The inverter pair, NFETs206and208, are active in the evaluate phase of N1, of clock signal224because of the action of NFET220. Consequently, Out218afalls (t3). In the succeeding precharge phase, N2of clock signal224, Out218ais latched in the “low” state, as previously described.

In this way, LSDL device200inFIG. 2.1, may provide a static switching factor on Out218a, and likewise with respect to the complementary output Out N218b. It would also be recognized by artisans of ordinary skill that although LSDL device200,FIG. 2.1, has been described in conjunction with the particular logic tree embodiments of FIG.2.2.1and FIG.2.2.2, the principles of the present invention apply to alternative embodiments having other logic tree implementations, and such alternative embodiments fall within the spirit and the scope of the present invention.

Note too, as illustrated in the exemplary timing diagram inFIG. 2.3, the duty factor of the clock signal may have a value that is less than fifty percent (50%). In such an embodiment, the evaluate phase, N1, of the clock signal may be shorter in duration than the precharge phase, N2. A clock signal having a duty factor less than fifty percent (50%) may be referred to as a pulse (or pulsed) clock signal. Note that a width of the evaluate phase may be sufficiently short that leakage from the dynamic node may be inconsequential. That is, leakage does not affect the evaluation of the node.

In such a clock signal embodiment, the size of the precharge device (PFET212in the embodiment ofFIG. 2.1) may be reduced. It would be recognized by those of ordinary skill in the art that a symmetric clock signal has a fifty percent (50%) duty cycle; in an embodiment in which the duty cycle of the clock signal is less than fifty percent (50%), the size of the precharge device may be reduced concomitantly. In particular, an embodiment of the present invention may be implemented with a clock signal duty cycle of approximately thirty percent (30%). Additionally, while logic device200has been described from the perspective of “positive” logic, alternative embodiments in accordance with the present inventive principles may be implemented in the context of “negative” logic and such embodiments would also fall within the spirit and scope of the present invention.

FIG. 3.1illustrates a portion300of a data processing system incorporating LSDL circuits in accordance with the present inventive principles. System portion300may be implemented using a two-phase clock signal (denoted clock1and clock2). A timing diagram which may be associated with system portion300will be discussed in conjunction withFIG. 3.2. LSDL blocks302bthat may be clocked by a second clock signal phase, clock2, alternates with LSDL block302aclocked by the first clock signal phase, clock1. Additionally, system portion300may include static logic elements304between LSDL blocks. Typically, static circuit blocks304may include gain stages, inverters or static logic gates. Static circuit blocks304are differentiated from LSDL blocks302aand302bas they do not have dynamic nodes that have a precharge cycle. However, alternative embodiments may include any amount of static logic. Additionally, as previously mentioned, an embodiment of system portion300may be implemented without static circuit blocks304.

FIG. 3.2illustrates a timing diagram which may correspond to a logic system employing a two-phase, pulsed clock signal, such as system portion300,FIG. 3.1, in accordance with the present inventive principles. The LSDL circuits evaluate during the LSDL evaluate, or drive, portion306of their respective clock signals. As previously described, the duty factor of each of clock1and clock2may be less than fifty percent (50%). The width of the LSDL drive portions306of the clock signals need only be sufficiently wide to allow the evaluate node (such as dynamic node210,FIG. 2.1) to be discharged through the logic tree (e.g., logic tree204,FIG. 2.1). As previously described, the duration of the drive portion may be sufficiently narrow that leakage from the evaluation may be inconsequential. Consequently, LSDL circuits are not particularly sensitive to the falling edge of the clock signals, and inFIG. 3.2, the falling portion of the evaluate phase306of the clock signals has been depicted with cross-hatching. As noted herein above, the duty factor of clock1and clock2may be approximately thirty percent (30%) in an exemplary embodiment of the present invention. (It would be appreciated, however, that the present inventive principles may be incorporated in alternative embodiments which have other duty factors.) During the precharge portion308of the clock signals, the dynamic node (for example, dynamic node210,FIG. 2.1) is precharged, as previously discussed. Clock2is 180° (π radians) out of phase with clock1(shifted in time one-half of period T). Thus as shown, the evaluate portion306of clock2occurs during the precharge phase308of clock1. Because in LSDL circuits, the output states may not change during the evaluate phase of the driving clock signal; the inputs to LSDL blocks, for example, LSDL blocks302b,FIG. 3.1, are stable during the evaluate phase of the corresponding driving clock signal, clock2. The time interval, between the end of the evaluate portion306of clock1and the rising edge of clock2may be established by the setup time of the LSDL, and the evaluation time of the static blocks, if any (for example, static blocks304,FIG. 3.1). The time, Tau301, together with duty factor may determine the minimum clock signal period for a particular LSDL circuit implementation. Thus, a system portion300,FIG. 3.1having a two-phase clock signal effects two dynamic evaluations per period, T1of the driving clock signals. It would be further appreciated by those of ordinary skill in the art that, in general, the present inventive principles may be incorporated in alternative embodiments of an LSDL system having a plurality, n, of clock signal phases. Such alternative embodiments would fall within the spirit and scope of the present invention.

An LSDL system in accordance with the principles of the present invention, such as system300,FIG. 3.1, may be used, in an exemplary embodiment, in an arithmetic logic unit (ALU). A typical ALU architecture requires a significant number of exclusive-OR (XOR) operations. The XOR of two Boolean values requires having both senses of each of the Boolean values, that is, both the value and its complement (a⊕b=ab′+a′b). As previously described, use of dual rail dynamic logic to implement such functionality obviates the advantages in area and power otherwise obtained by dynamic logic. A data processing system including an ALU embodying the present inventive principles is illustrated inFIG. 4.

FIG. 4is a high level functional block diagram of selected operational blocks that may be included in a central processing unit (CPU)400. In the illustrated embodiment, CPU400includes internal instruction cache (I-cache)440and data cache (D-cache)442which are accessible to memory (not shown inFIG. 4) through bus412, bus interface unit444, memory subsystem438, load/store unit446and corresponding memory management units: data MMU450and instruction MMU452. In the depicted architecture, CPU400operates on data in response to instructions retrieved from I-cache440through instruction dispatch unit448. Dispatch unit448may be included in instruction unit454which may also incorporate fetch unit456and branch processing unit458which controls instruction branching. An instruction queue460may interface fetch unit456and dispatch unit448. In response to dispatched instructions, data retrieved from D-cache442by load/store unit446can be operated upon by one of fixed point unit (FXU)460, FXU462or floating point execution unit (FPU)464. Additionally, CPU400provides for parallel processing of multiple data items via vector execution unit (VXU)466. VXU466includes vector permute unit468which performs permutation operations on vector operands, and vector arithmetic logic unit (VALU)470which performs vector arithmetic operations, which may include both fixed-point and floating-point operations on vector operands. VALU470may be implemented using feedforward LSDL gates in accordance with the present inventive principles, and in particular may incorporate LSDL logic systems, of which LSDL system300,FIG. 3.1is exemplary.

A representative hardware environment500for practicing the present invention is depicted inFIG. 5, which illustrates a typical hardware configuration of a data processing system in accordance with the subject invention having CPU400, incorporating the present inventive principles, and a number of other units interconnected via system bus550. The data processing system shown inFIG. 5includes random access memory (RAM)514, read only memory (ROM)516, and input/output (I/O) adapter518for connecting peripheral devices such as disk units520to bus550, user interface adapter522for connecting keyboard524, mouse526, and/or other user interface devices such as a touch screen device (not shown) to bus550, communication adapter534for connecting the system to a data processing network, and display adapter536for connecting bus550to display device538. Note that CPU400may reside on a single integrated circuit.

FIG. 6is the circuit for a standard LSDL logic gate with clock602and Data Inputs601. PFET603is the pull-up used to pre-charge dynamic node606when the clock is logic zero. Logic tree604logically combines the Data Inputs601generating a logic state and NFET605asserts this logic state on dynamic node606when clock602is a logic one. The logic state of the dynamic node is inverted by PFET608and NFET609. If the dynamic node asserts to a logic zero, PFET608turns ON and Data Out612transitions to a logic one and Data Out—B transitions to a logic zero. When Data Inputs601is a logic one, the logic one state at Data Out612is latched by action of PFET611and the logic zero state of Data Out—B615. When Data In601is a logic zero, dynamic node606asserts to a logic one and this logic state is inverted to a logic zero at Data Out612by the action of NFET609and NFET610when clock602transitions to a logic one. Data Out—B transitions to a logic one and the logic zero of Data Out612is latched by the action of NFET613and the logic one state of Data Out—B.

FIG. 7is the circuit of the improved LSDL logic gate (LSDL)700with reduced power according to embodiments of the present invention. In this embodiment, Data Inputs701are coupled to logic tree704which performs a logic combination of Data Inputs701and generates a logic state. Clock702is coupled to PFET703and to the gates of NFET705and NFET710. Dynamic node706is pre-charged to a logic one when Clock702is a logic zero.

The logic state of the dynamic node is inverted by PFET708and NFET709. If the dynamic node706asserts to a logic zero, PFET708turns ON and Data Out712transitions to a logic one and Data Out—B715transitions to a logic zero. When Data Inputs701is a logic one, the logic one state at Data Out712is latched by action of PFET711and the logic zero state of Data Out—B715. When Data In701is a logic zero, dynamic node706asserts to a logic one and this logic state is inverted to a logic zero at Data Out712by the action of NFET709and NFET710when clock702transitions to a logic one. Data Out—B715transitions to a logic one and the logic zero of Data Out712is latched by the action of NFET713and the logic one state of Data Out—B715.

This embodiment of the present invention adds NFET721, inverter720, PFETs717and718and NFET719. LSDL700splits out a portion of the function of NFET716into NFET721. NFET716functions to pull down Data Out—B715to a logic zero whenever dynamic node706evaluates to a logic zero. LSDL700implements NFET716as a small device which acts as a keeper and NFET721as a large device which quickly pulls Data Out—B715when the dynamic node706transitions to a logic zero. When dynamic node evaluates to a logic zero, the inverting stage comprising PFETs717and718and NFET719generate a logic one Feedforward pulse (FFP)722if Data Out—B is a logic one. Therefore large NFET721only turns ON when Data Out—B715is transitioning to a logic zero. If Data Out—B715is already a logic zero, it is held at this logic zero state by small NFET716. Since NFET721is mostly OFF and NFET716is very small, the gate leakage is minimized. Since PFET714works against small NFET716its size may also be reduced in LSDL circuit700. Correspondingly, the remaining devices in LSDL700can also be reduced in size. PFET708and NFET709drive a smaller PFET714and NFET716and can be reduced in size. A smaller PFET708and NFET709lead to smaller NFETs710and713.

Adding the inverting stages comprising PFETs717and718and NFET719and inverter720used to generate FFP722results in a relatively small increase in power compared to the savings resulting from making large NFET721pulse driven.

FIG. 8is a timing diagram of cycles of signals of the embodiment ofFIG. 7. Initially, Data Out—B715is a logic one. If the states of Data Inputs701generate a logic true condition, then when clock702transitions to a logic one (pulse801), dynamic node706evaluates to a logic zero (pulse802). Since Data Out—B715was a logic one, inverter720turns PFET717ON and PFET718and NFET719generate a positive pulse on FFP722which turns ON NFET721quickly pulling Data Out—B715to a logic zero. When dynamic node706transitions to a logic zero, Data Out712transitions to a logic one which turns ON keep NFET716holding Data Out—B715a logic zero. Half latch PFET711turns ON holding Data Out712at a logic one. When clock702again transitions to a logic one (pulse803), dynamic node706again evaluates to a logic zero (pulse804). However, on this cycle Data Out—B715is a logic zero and inverter720keeps PFET717from turning ON and no FFP722pulse is generated. On the fourth cycle (pulse805) of clock702, dynamic node706evaluates to a logic one and Data Out712transitions to a logic zero turning NFET716OFF and turning ON PFET714. Data Out—B715transitions to a logic one. Since Data Out—B715is a logic one, the next time dynamic node706evaluates to a logic zero another FFP722pulse will be generated.