Method of making two-phase buried channel planar gate CCD

The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.

FIELD OF THE INVENTION 
The present invention relates to a method of making a planar gate 
charge-coupled device (CCD) having a single level gate electrode, and, 
more particularly, to a method of making a two-phase CCD having a planar 
gate electrode. 
BACKGROUND OF THE INVENTION 
In general a CCD comprises a body of a semiconductor material, such as 
single crystalline silicon, having a channel region in and along a surface 
of the body. A layer of an insulating material, typically silicon dioxide, 
is on the surface of the body and over the channel region. A plurality of 
conductive gate electrodes, typically of doped polycrystalline silicon, 
are on the insulating layer and extend across the channel region. The gate 
electrodes are positioned along the entire length of the channel region. 
In a two-phase CCD, the gate electrodes are arranged in two sets which 
alternate along the channel region. The gate electrodes of one set are 
connected to a first phase potential, and the gate electrodes of the other 
set are connected to a second phase potential. Such a two-phase CCD also 
typically includes in the body a barrier region under an edge of each of 
the gate electrodes and extending across the channel region. The barrier 
regions prevent the charge from moving backwards along the channel region. 
The two sets of gate electrodes could be formed from a single layer of the 
conductive material by depositing the single layer and defining it by 
photolithography and etching to form the spaced gates electrodes along the 
channel region. However, using commercial type photolithographic and 
etching techniques and equipment, it is difficult to form the gate 
electrodes having very narrow submicron gaps therebetween with the gaps 
being uniform across the entire width of the gate electrodes. Since 
relatively wide and/or non-uniform gaps can form potential barriers and/or 
wells between the gate electrodes, they can interfere with the transfer of 
charge from one gate electrode to the next. Therefore, it has been the 
practice to form the gate electrodes from two separate levels (layers) of 
the conductive material. 
For a two level system, a first layer of the conductive material is 
deposited and defined to form one set of the gate electrodes, the first 
set of gate electrodes are covered with a layer of an insulating material, 
typically silicon dioxide. A second layer of the conductive material is 
then deposited over the first set of gate electrodes and the gaps between 
the first set of gate electrodes. The second layer of the conductive 
material is then defined to form the second set of gate electrodes which 
are between the gate electrodes of the first set. Also, each of the gate 
electrodes of the second set overlaps the adjacent gate electrodes of the 
first set. Since the gate electrodes overlap each other, there are no gaps 
therebetween which can form undesirable potential barriers and/or wells. 
However, the two level gate electrode system is non-planar since portions 
of the second set of electrodes extend over the first set of electrodes. 
Also, there is provided undesirable capacitance between the two sets of 
gate electrodes where they overlap. 
Heretofore, submicron-gap, planar gate CCD structures have been reported, 
but they have been primarily three or four-phase devices. A two-phase 
submicron gap CCD is described in an article by V. J. Kapoor, published in 
IEEE Electron Device Letters, Vol EDL-2, No. 4, page 92, April 1981. 
However, the structure described in this article suffers from formation of 
potential wells and/or barriers between the barrier and storage regions 
within each phase resulting in low transfer efficiency. This is because 
this device is not a true two-phase structure, but has separate electrodes 
for the individual barrier and storage regions within each phase. 
Therefore, it would be desirable to have a method of making a true 
two-phase CCD having a single level of the gate electrodes so as to be 
planar, and having submicron gaps between the gate electrodes. 
SUMMARY OF THE INVENTION 
The present invention is directed to a method of making a CCD having a 
single layer (level) of gate electrodes which comprises forming a layer of 
a conductive material over and insulated from a surface of a body of a 
semiconductor material having a channel region therein. Masking layers 
having submicron lengths of the bottom portion are formed spaced along the 
conductive layer with each masking layer being between two additional 
masking layers of silicon dioxide. The submicron length masking layers are 
removed to expose narrow portions of the conductive layer. The conductive 
layer is etched therethrough at each of the exposed portions to divide the 
conductive layer into gate electrodes spaced apart by submicron width 
gaps. 
Viewed from another aspect, the present invention is directed to a method 
of making a planar CCD which comprises the steps of forming a layer of a 
conductive material on a surface of a body of a semiconductor material of 
one conductivity type. Sections of a first masking layer are formed on the 
conductive layer with the sections being spaced apart along the conductive 
layer. A second masking layer is formed at one end of each of the first 
masking layer sections with the second masking layers all being at the 
same end of their respective first masking layer section. Each of the 
second masking layers has a portion extending across the space between its 
respective first masking layer section and the adjacent first masking 
layer section. A third masking layer is formed on the surface of the 
conductive layer in the space between the second masking layer and the 
adjacent first masking layer section. The second masking layers are 
removed to expose a narrow portion of the conductive layer between each 
first masking layer section and the adjacent third masking layer. The 
exposed portions of the conductive layer are then removed to divide the 
conductive layer into gate electrodes having gaps therebetween. 
The invention will be better understood from the following more detailed 
description and claims taken with the accompanying drawings.

DETAILED DESCRIPTION 
Referring now to FIG. 1, there is shown a sectional view of a two-phase 
charge coupled device (CCD) 10 in an initial stage of fabrication in 
accordance with a method of the present invention. CCD 10 comprises a 
substrate body 12 of a semiconductor material of one conductivity type, 
such as p-type conductivity single crystalline silicon. The body 12 is 
provided with a region 14 therein of the opposite conductivity type, such 
as n-type conductivity, which extends to and along a surface 16 of the 
body 12. The region 14 forms the buried channel of the CCD 10. The region 
14 may be formed by ion implanting an n-type conductivity dopant into the 
body 12 through the surface 16. On the surface 16 of the body 12 is a 
layer 18 of an insulating material, typically silicon dioxide. On the 
insulating material layer 18 is a layer 20 of a conductive material. 
Although the CCD 10 will be described with the conductive layer 20 being 
of deposited silicon, it can be of various other conductive materials, 
such as an optically transparent conductor, a metal, a metal alloy or a 
metal silicide. If an optically transparent conductor, a metal, metal 
alloy or a metal silicide is used for the conductive layer 20, it is 
covered with a layer of polycrystalline or amorphous silicon to permit the 
carrying out of the method of the present invention. On the conductive 
layer 20 is a first masking layer 22. The first masking layer 22 is of 
silicon dioxide deposited by a low temperature deposition technique. On 
the first masking layer 22 is a second masking layer 24 of a photoresist. 
Referring now to FIG. 2, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The photoresist second masking layer 24 is defined, using 
standard photolithographic techniques, to form openings 26 therethrough. 
The openings 26 are spaced periodically along the channel region 14. The 
portions of the silicon dioxide first masking layer 22 at the bottom of 
the openings 26 are then removed using a suitable etchant for silicon 
dioxide. This provides openings 28 in the first masking layer 22 which are 
periodically spaced along the channel region 14 to divide the first 
masking layer 22 into a plurality of sections. As indicated by the arrows 
30 a dopant of the opposite conductivity type as the channel region 14, 
i.e., p-type conductivity, are now implanted through the openings 26 and 
28 into the channel region 14. This forms p-type conductivity barrier 
regions 32 in the channel region 14 which are spaced periodically along 
the channel region 14. Alternatively, storage regions may be implanted by 
using an implant of the same conductivity type as the channel region 14. 
Referring now to FIG. 3, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The photoresist second masking layer 24 is removed. A thin 
third masking layer 34 of conformal silicon nitride is deposited over the 
sections of the silicon oxide first masking layer 22 and the surface of 
the conductive layer 20 exposed by the openings 28 in the first masking 
layer 22. A thicker fourth masking layer 36 of conformal silicon dioxide 
is then deposited over the third masking layer 34 and fills the openings 
28 in the first masking layer 22. 
Referring now to FIG. 4, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The fourth masking layer 36 is now etched with an anisotropic 
etch, such as a plasma etch. The anisotropic etch etches vertically to 
remove the silicon oxide fourth masking layer 36 down to the silicon 
nitride third masking layer 34. However, the vertical etching leaves 
spacers 38 of the fourth masking layer 36 extending along the portions of 
the third masking layer 34 which extend along the ends of the first 
masking layer 22 at the openings 28. However, the portions of the third 
masking layer 34 which extend over the first masking layer 22 and the 
surface of the conductive layer 20 between the spacers 38 are exposed. 
Referring now to FIG. 5, there is shown a sectional view of the CCD 10 in a 
next step of fabrication in accordance with the method of the present 
invention. The exposed portions of the silicon nitride third masking layer 
34 are now removed with a suitable etchant. This leaves L-shaped pieces 40 
of the silicon nitride third masking layer 34 under the spacers 38. The 
L-shaped pieces 40 extend along the ends of the sections of the first 
masking layer 22 at the openings 28 and along a short portion of the 
surface of the conductive layer 20 in the openings 28. 
Referring now to FIG. 6, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The silicon dioxide spacers 38 are removed with a suitable 
etchant, such as a wet chemical etching. This leaves the L-shaped pieces 
40 exposed. Part or all of the first masking layer 22 is also removed in 
this process. The length of the bottom portions of the L-shaped pieces 40 
is short, on the order of 0.1 to 0.2 microns. This length determines the 
width of the gap between the gate electrodes to be formed. 
Referring now to FIG. 7, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. A fifth masking layer 42 of silicon oxide is formed over a 
portion of each section of any of the remaining first masking layer 22 and 
the L-shaped pieces 40 at only one end of each of each of the sections. 
The L-shaped pieces 40 which are covered by the fifth masking layer 42 are 
all at the same end of their respective section of the remaining first 
masking layer 22. The fifth masking layer 42 is formed by deposited by a 
low temperature deposition technique a layer of silicon dioxide over all 
of the sections of the remaining first masking layer 22, all of the 
L-shaped pieces 40 and the surface of the conductive layer 20 between the 
L-shaped pieces 40. The layer is then defined using standard 
photolithographic techniques and etching to form the fifth masking layer 
42. 
Referring now to FIG. 8, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The exposed L-shaped pieces 40 are now removed using a suitable 
wet etchant for silicon nitride. This leaves the L-shaped pieces 40 which 
are under the fifth masking layer 42. 
Referring now to FIG. 9, there is shown a sectional view of the CCD 10 in a 
next stage of fabrication in accordance with the method of the present 
invention. The fifth masking layer 42 is now removed with a suitable wet 
etching for silicon dioxide. Since the first masking layer 22 is also of 
silicon dioxide, this will also remove the portions of the section of the 
first masking layer 22 which were not covered by the fifth masking layer 
42. If desired, another implant of p-type conductivity dopants may be made 
into the portions of the channel region 14 not covered by the first 
masking layer 22 to form a staircase barrier region (not shown), or an 
n-type implant for staircase storage regions. Alternatively, all of the 
silicon dioxide may be etched off, including the regions 22, leaving on 
the silicon nitride L-shaped pieces 40. 
Referring now to FIG. 10, there is shown a sectional view of the CCD 10 in 
the next stage of fabrication in accordance with the method of the present 
invention. A sixth masking layer 44 of silicon dioxide is now formed on 
the portions of the conductive layer 20 not covered by the first masking 
layer 22 and the L-shaped portions 40. Since the conductive layer 20 is of 
polycrystalline or amorphous silicon, the sixth masking layer 44 is formed 
by heating the device in an atmosphere of oxygen to covert the surface of 
the exposed portions of the conductive layer 20 to silicon dioxide. 
Referring now to FIG. 11, there is shown a sectional view of the CCD 10 in 
the next stage of fabrication in accordance with the method of the present 
invention. The L-shaped pieces 40 are removed using a suitable wet etchant 
for silicon nitride. This leaves a narrow gap 46 between each of the sixth 
masking layers 44 and an adjacent first masking layer 22. This gap 46 is 
used to define a gap between adjacent gate electrodes to be formed. 
Referring now to FIG. 12, there is shown a sectional view of the CCD 10 in 
the next stage of fabrication in accordance with the method of the present 
invention. Using an anisotropic etch, such as a plasma etch, the portions 
of the conductive layer 20 exposed by the gaps 46 are etched down to the 
insulating layer 18. This forms grooves 48 through the conductive layer 20 
which separates the conductive layer 20 into individual gate electrodes 
50. The individual gate electrodes 50 are spaced apart by the grooves 48 
which are submicron gaps. The gate electrodes 50 are positioned so that 
each has an edge thereof which is over a barrier region 32. The first and 
sixth masking layers 22 and 44 respectively, may now be removed with a 
suitable etchant, and the CCD 10 completed in the usual manner. To form a 
two-phase CCD 10, alternate gate electrodes 50 are connected to a first 
source of potential, and the other alternate gate electrodes 50 are 
connected to a second source of potential. 
Thus, there is provided by the present invention a method of forming a 
two-phase CCD 10 in which all of the gate electrodes 40 are formed from a 
single layer (level) of a conductive material so as to provide a planar 
structure. The gate electrodes 50 are spaced apart by a narrow gap which 
is of relatively uniform width. The gap is defined by the L-shaped pieces 
40, the bottom of which can be easily made of submicron length. This 
permits the gaps between the gate electrodes to be of submicron width. 
It is to be appreciated and understood that the specific embodiments of the 
invention are merely illustrative of the general principles of the 
invention. Various modifications may be made consistent with the 
principles set forth. For example, the conductive layer which forms the 
gate electrodes may be made of various materials, such as doped 
polycrystalline silicon, an optically transparent conductor, such as tin 
oxide, a metal, metal alloy or a metal silicide. If an optically 
transparent conductor, such as tin oxide, a metal, metal alloy or metal 
silicide is used, a layer of polycrystalline or amorphous silicon must be 
provided thereover to permit the forming of the sixth masking layer 44 of 
grown silicon dioxide.