Memory device including bitline sense amplifier and operating method thereof

Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0088720 filed on Jul. 17, 2020 and Korean Patent Application No. 10-2021-0028193 filed on Mar. 3, 2021, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated by reference herein in their entirety.

BACKGROUND

Embodiments of the inventive concept described herein relate to a memory device and an operating method thereof, and more particularly, relate to a memory device including a bitline sense amplifier and an operating method thereof.

A memory cell array included in a memory device implemented as a dynamic random access memory (DRAM) may be connected to a bitline sense amplifier through a bitline and a complementary bitline. The bitline sense amplifier may sense a voltage difference between the bitline and the complementary bitline and may amplify the sensed voltage difference. Data stored in the memory cell array may be read based on the sense and amplification operation of the bitline sense amplifier.

When the bitline sense amplifier senses a voltage difference between the bitline and the complementary bitline, a noise may occur at memory cells not targeted for sensing. This noise may cause an error in data stored in the memory cells not targeted for sensing. As such, the reliability of the DRAM may be reduced.

SUMMARY

Embodiments of the inventive concept provide a memory device including a bitline sense amplifier and an operating method thereof.

According to an exemplary embodiment, a memory device may include a bitline sense amplifier that is connected to a bitline and a complementary bitline connected to a memory cell and senses and amplifies a difference between a voltage of the bitline and a voltage of the complementary bitline, and a sense amplifier driver circuit. The sense amplifier driver circuit may adjust a level of a bitline low-level voltage of the bitline sense amplifier in response to a command received from a host, so as to be higher than a level of a ground voltage.

According to an exemplary embodiment, a memory device may include a bitline sense amplifier that is connected to a bitline and a complementary bitline connected to a memory cell and senses and amplifies data stored in the memory cell, and a sense amplifier driver circuit. The sense amplifier driver circuit may generate a first pull-up pulse and a pull-down pulse based on a command received from a host and may adjust a level of a bitline low voltage to be developed by the bitline sense amplifier in response to the first pull-up pulse and the pull-down pulse. The level of the bitline low voltage may be higher than a ground voltage as much as a delta voltage when a read operation is performed on the memory cell and may be equal to the ground voltage when a write operation is performed on the memory cell.

According to an exemplary embodiment, an operating method of a memory device which includes a bitline sense amplifier connected to a bitline and a complementary bitline. The bitline and the complementary bitline are connected to a plurality of memory cells. The method may include sensing and amplifying data stored in a target memory cell of the plurality of memory cells, applying a voltage of a first node of the bitline sense amplifier to one of the bitline and the complementary bitline, restoring the data stored in the target memory cell and then increasing a voltage level of the first node of the bitline sense amplifier from a ground voltage, or writing a first data in the target memory cell and then increasing the voltage level of the first node of the bitline sense amplifier from the ground voltage, and decreasing the voltage level of the first node of the bitline sense amplifier to the ground voltage. Each of the plurality of memory cells may include a transistor of a floating body structure.

DETAILED DESCRIPTION

Below, embodiments of the inventive concept may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the inventive concept.

Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to accompanying drawings. With regard to the description of the inventive concept, to make the overall understanding easy, similar components will be marked by similar reference signs/numerals in drawings, and thus, additional description will be omitted to avoid redundancy.

FIG. 1illustrates a block diagram of a memory device according to an embodiment of the inventive concept. Referring toFIG. 1, a memory device10may include a control logic11, a memory cell array12, a row decoder13, a column decoder14, an input/output buffer15, a voltage generator16, and a sense amplifier unit100. In an embodiment, the memory device10may be implemented as a dynamic random access memory (DRAM).

The control logic11may receive a command/address CA and a clock CK from an external device (referred to as a “host”, a “central processing unit (CPU)”, a “memory controller”, or the like). The command/address CA may include a command indicating an operation to be performed by the memory device10, a row address ADDR_R indicating a row of a memory cell targeted (hereinafter referred to as a “target memory cell”) for the operation to be performed by the memory device10, and a column address ADDR_C indicating a column of the target memory cell. The control logic11may transmit the row address ADDR_R to the row decoder13and may transmit the column address ADDR_C to the column decoder14.

The control logic11may decode the received command/address CA. For example, the control logic11may include a decoder that decodes the received command/address CA. The control logic11may receive an active command, a read/write command, a precharge command, or the like from the host and may decode the received command. The control logic11may generate a wordline active signal WLACT, a write enable signal WREN, or a precharge signal PRCG based on the decoding result and may transmit the generated signal to the sense amplifier unit100. For example, the wordline active signal WLACT may be generated in response to the active command, the write enable signal WREN may be generated in response to the write command, and the precharge signal PRCG may be generated in response to the precharge command.

The memory cell array12may include a plurality of memory cells (e.g., MC1, MC2, and MC3ofFIG. 2). For example, the memory cells included in the memory cell array12may be arranged at points where a plurality of wordlines WL and a plurality of bitlines BL intersect. Each of the memory cells may be connected to the corresponding wordline among the plurality of wordlines WL. Each of the memory cells may be connected to the corresponding bitline of the plurality of bitlines BL and the corresponding complementary bitline of a plurality of complementary bitlines BLB. The memory cells may be provided in the form of a matrix. In this case, the plurality of wordlines WL may be connected to rows of the memory cells, and the plurality of bitlines BL and the plurality of complementary bitlines BLB may be connected to columns of the memory cells. The memory cell array12will be more fully described with reference toFIG. 2.

The row decoder13may receive the row address ADDR_R from the control logic11. The row decoder13may be connected to the memory cell array12through the plurality of wordlines WL. By decoding the received row address ADDR_R, the row decoder13may select one wordline of the plurality of wordlines WL connected to the memory cell array12. The row decoder13may activate the selected wordline by applying a voltage to the selected wordline.

The column decoder14may receive the column address ADDR_C from the control logic11. The column decoder14may be connected to the sense amplifier unit100through a column select line CSL. By decoding the received column address ADDR_C, the column decoder14may select a bitline(s) and a complementary bitline(s) corresponding to a read unit from among the plurality of bitlines BL connected to the memory cell array12. The column decoder14may select a bitline and a complementary bitline by applying a voltage to the column select line CSL.

When the memory device10performs a write operation in response to the command/address CA, the input/output buffer15may receive data DQ from the external device. The input/output buffer15may temporarily store the received data DQ. The input/output buffer15may transmit the stored data DQ to the sense amplifier unit100.

When the memory device10performs a read operation in response to the command/address CA, the input/output buffer15may receive data from the memory cell array12after sensing by the sense amplifier unit100and may temporarily store the received data. As data stored in the memory cell array12, the data temporarily stored in the input/output buffer15may be output to the external device in response to a request of the external device.

The voltage generator16may generate various voltages capable of being used in the memory device10. For example, the voltage generator16may receive an external voltage VEXT from the outside of the memory device10, that is, the external device. The voltage generator16may generate an internal voltage VINTA and a pull-up reference voltage VREF_PU, based on the external voltage VEXT. For example, the internal voltage VINTA may be applied to the memory cell array12.

The sense amplifier unit100may sense data stored in the memory cell array12, may amplify a voltage corresponding to the sensed data, and may output data corresponding to the amplified voltage to the external device in response to a request of the external device. For example, the sense amplifier unit100may sense data stored in a target memory cell, based on the signals WLACT, WREN, and PRCG received from the control logic11and the voltages VINTA and VREF_PU received from the voltage generator16. An operation of the sense amplifier unit100will be more fully described later.

FIG. 2is a diagram illustrating a portion of a memory device ofFIG. 1in detail according to example embodiments. Referring toFIGS. 1 and 2, the memory device10may include the memory cell array12in which a plurality of memory cells are arranged, the sense amplifier unit100connected to the memory cell array12, a plurality of transistors CST connected to the column select line CSL, and the input/output buffer15. Some components of the memory device10are illustrated inFIG. 2, and components included in the memory device10are not limited to the example ofFIG. 2.

Each of the memory cells included in the memory cell array12may include a transistor and a capacitor. For example, a first memory cell MC1may include a transistor TR1having a gate connected to a wordline WL0, a first end connected to a bitline BL, and a second end connected to a capacitor CS1. The first memory cell MC1may include the capacitor CS1having a first end connected to the second end of the transistor TR1and a second end connected to a ground voltage (e.g., a voltage VSS ofFIG. 3or a voltage GND ofFIG. 5) or connected to a plate voltage Vp (e.g., ½ VINTA or a certain (or preset) voltage). As in the above description, a second memory cell MC2may include a transistor TR2and a capacitor CS2connected to a wordline WL1and the bitline BL, and a third memory cell MC3may include a transistor TR3and a capacitor CS3connected to a wordline WL2and the bitline BL.

Memory cells connected to the complementary bitline BLB may have the same structures as the memory cells connected to the bitline BL. To prevent a drawing from being unnecessarily complicated, memory cells of the bitline BL and memory cells of the complementary bitline BLB are illustrated as disposed adjacent to each other. However, the bitline BL may be disposed in a first array, and the complementary bitline BLB may be disposed in a second array. The sense amplifier unit100may be interposed between the first array and the second array. The bitline BL may extend toward the first array and may be connected to memory cells, and the complementary bitline BLB may extend toward the second array and may be connected to memory cells.

The data DQ input from the external device may be stored in each of the plurality of memory cells, based on the command/address CA received from the external device. For example, in the case where the external device intends to write data “1” in the first memory cell MC1, the external device may transmit the command/address CA, which includes the row address ADDR_R and the column address ADDR_C indicating the first memory cell MC1and a write command, and the data DQ including data “1” to the memory device10. The memory device10may charge a voltage corresponding to data “1” in the capacitor CS1included in the first memory cell MC1, in response to the received command/address CA and the received data DQ.

Memory cells connected to the complementary bitline BLB may store data complementary to data stored in the memory cells connected to the bitline BL. When data “1” are stored in a specific memory cell of the bitline BL, data “0” may be stored in the corresponding memory cell of the complementary bitline BLB. Likewise, when data “0” are stored in the specific memory cell of the bitline BL, data “1” may be stored in the corresponding memory cell of the complementary bitline BLB.

In the embodiment that is illustrated inFIG. 2, a pair of bitline BL and complementary bitline BLB is illustrated by way of example. However, a plurality of pairs of bitlines BL and complementary bitlines BLB may be provided and may be connected to a plurality of memory cells.

In the embodiment that is illustrated inFIG. 2, the memory cell array12may further include a device isolation layer TRENCH. The device isolation layer TRENCH may isolate the plurality of memory cells included in the memory cell array12from each other. For example, the first memory cell MC1may be electrically isolated from the second memory cell MC2by the device isolation layer TRENCH. The device isolation layer TRENCH may be implemented with an isolator.

In the embodiment that is illustrated inFIG. 2, a transistor included in each of the plurality of memory cells may have a floating body structure. For example, a body (alternatively referred to as a “substrate” or a “bulk”) of the transistor TR1included in the first memory cell MC1may not be biased. For example, the body of the transistor TR1may be electrically floated. However, the invention is not limited to the embodiment illustrated inFIG. 2. Unlike the embodiment illustrated inFIG. 2, a body of a transistor included in a memory cell may be biased.

The sense amplifier unit100may include a bitline sense amplifier driver circuit110, a bitline sense amplifier120, and a voltage equalization circuit130. Under control of the bitline sense amplifier driver circuit110, the bitline sense amplifier120may sense and amplify a voltage corresponding to data stored in a capacitor of a target memory cell among a plurality of memory cells. For example, under control of the bitline sense amplifier driver circuit110, the bitline sense amplifier120may read data stored in the memory cell array12, may amplify the read data, and may temporarily store the amplified data. Operations of the bitline sense amplifier120and the bitline sense amplifier driver circuit110will be more fully described later.

The voltage equalization circuit130may equalize voltages applied to a pair of bitline BL and complementary bitline BLB before a sensing operation of the bitline sense amplifier120. For example, when the precharge command is received from the external device, the voltage equalization circuit130may transfer a precharge voltage (e.g., half the driving voltage supplied to the memory device10) to the bitline BL. As such, the bitline BL may be precharged with the precharge voltage.

The column select line CSL may be connected to gates of the plurality of transistors CST. When the command/address CA is received from the external device, the column select line CSL may turn on the transistor CST corresponding to a column (or a bitline) connected to a target memory cell. As such, a voltage that is sensed and amplified by the bitline sense amplifier120(i.e., data stored in the target memory cell) may be transmitted to the input/output buffer15through the turned-on transistor CST.

In an embodiment, inFIG. 2, when the command/address CA is received, the wordline WL0may be activated, and the wordlines WL1and WL2may not be activated. For example, a voltage large enough to turn on the transistor TR1may be supplied to the wordline WL0, and a smaller voltage (i.e., a voltage not large enough to turn on the transistors TR2and TR3) may be supplied to the wordlines WL1and WL2. As such, the transistor TR1connected to the wordline WL0may be turned on, and the transistors TR2and TR3may not be turned on.

After the wordline WL0is activated, the bitline BL and the complementary bitline BLB may be developed by the sense amplifier unit100. For example, a voltage of each of the bitline BL and the complementary bitline BLB may be set to a power supply voltage or a ground voltage. In an embodiment, assuming that the second memory cell MC2stores data “0” and the third memory cell MC3stores data “1”, the capacitor CS2may be charged with a voltage corresponding to data “0” (or may not be charged), and the capacitor CS3may be charged with a voltage corresponding to data “1”.

Because the transistors TR2and TR3are not turned on, channels of the transistors TR2and TR3may not be formed. In this case, the capacitor CS3may be in a state of being charged with the voltage corresponding to data “1”, for example, the power supply voltage, and a voltage of the wordline WL2may be smaller than a threshold voltage of the transistor TR3. A gate induced drain leakage (GIDL) may occur under the above bias condition, In this case, holes may be generated on a surface or a curved surface of a drain of the transistor TR3and may be injected into the body of the transistor TR3.

In the embodiment that is illustrated inFIG. 2, the transistors TR2and TR3may be of a floating body structure. Accordingly, the holes generated by the GIDL may be accumulated in the floating body of the transistor TR3. The accumulated holes may cause a potential (or a voltage) of the body of the transistor TR3to increase. In the case where the ground voltage is applied to a source of the transistor TR3(e.g., one end of the transistor TR3connected to the bitline BL, in the embodiment illustrated inFIG. 2), due to the increased body potential, a forward-biased PN junction may occur between the source and the drain of the transistor TR3.

In the case where the voltage corresponding to data “1” is applied to the drain of the transistor TR3by the capacitor CS3and a voltage smaller than a threshold voltage of the transistor TR3is applied to the gate of the transistor TR3, a reverse-biased PN junction may occur between the drain and the body of the transistor TR3. A parasitic BJT condition may be satisfied by the forward-biased PN junction between the source and the body of the transistor TR3and the reverse-based PN junction between the drain and the body of the transistor TR3. For example, a first end of the transistor TR3connected to the capacitor CS3may operate as an emitter, the body of the transistor TR3may operate as a base, and a second end of the transistor TR3connected to the bitline BL may operate as a collector. As such, the transistor TR3may operate as an NPN bipolar junction transistor (BJT). In this case, in the transistor TR3, charges may move from the emitter to the collector through the base. As a result, as charges being stored in the capacitor CS3connected to the source of the transistor TR3are leaked, data “1” stored in the capacitor CS3may be lost.

A memory device according to an embodiment of the inventive concept may make a voltage of a low level developed by a bitline sense amplifier greater than the ground voltage during a given time while the bitline sense amplifier is operating. As a potential of a source of a transistor included in a memory cell is maintained to be greater than the ground voltage, the above GIDL phenomenon may become better. Also, the amount of holes accumulated in a body of a transistor with the floating body structure may decrease, and a reverse-biased PN junction may be maintained between one end of the transistor connected to a bitline and the body. As a result, the amount of leakage current of the memory cells in the memory cell array12may decrease, and data stored in the memory cells in the memory cell array12may be prevented from being lost. Accordingly, the reliability of the memory device10may be improved.

FIG. 3illustrates a block diagram of a sense amplifier unit ofFIG. 1according to example embodiments. Referring toFIGS. 1 to 3, the sense amplifier unit100may include the bitline sense amplifier120and the bitline sense amplifier driver circuit110. For convenience of illustration, the remaining components (e.g., the voltage equalization circuit130) of the sense amplifier unit100described with reference toFIG. 2and peripheral components (e.g., the column decoder14) are omitted inFIG. 3.

The bitline sense amplifier driver circuit110may include a regulator111, a pull-up circuit112, a pull-down circuit113, and a pulse generator114. The bitline sense amplifier driver circuit110may be connected to a node LAB of the bitline sense amplifier120. The bitline sense amplifier driver circuit110may provide a voltage VLAB to the node LAB, based on the internal voltage VINTA, the pull-up reference voltage VREF_PU, the wordline active signal WLACT, the write enable signal WREN, and the precharge signal PRCG. As such, a voltage (i.e., VLAB) of the node LAB may be equal to a ground voltage VSS or may be greater than the ground voltage VSS. For example, the bitline sense amplifier driver circuit110may pull up the voltage VLAB of the node LAB to be greater than the ground voltage VSS or may pull down the voltage VLAB of the node LAB to be equal to the ground voltage VSS.

In the embodiment that is illustrated inFIG. 3, the bitline sense amplifier driver circuit110may include the pull-down circuit113. However, another embodiment of the inventive concept may not include the pull-down circuit113. In this case, the bitline sense amplifier driver circuit110may not pull down the voltage VLAB of the node LAB. Alternately, the voltage VLAB may be pulled down to the ground voltage VSS based on an operation of a transistor MLAB1to be described later.

The bitline sense amplifier120may include transistors MP, MN, MSP1, MSP2, MSN1, MSN2, and MLAB1. The bitline sense amplifier120may include a first sensing unit PSA and a second sensing unit NSA. The first sensing unit PSA may include the transistors MSP1and MSP2. The second sensing unit NSA may include the transistors MSN1and MSN2. The transistors MSP1and MSP2of the first sensing unit PSA may be implemented with PMOS transistors. The transistors MSN1and MSN2of the second sensing unit NSA may be implemented with NMOS transistors.

The transistor MN may include a first end (e.g., a drain) to which the internal voltage VINTA from the voltage generator16is applied, a gate to which a bitline sense amplifier enable signal BLSA_EN from the pulse generator114is applied, and a second end (e.g., a source) connected to a node LA. In the embodiment that is illustrated inFIG. 3, the transistor MN may be implemented with an NMOS transistor.

The transistor MSP1may include a first end (e.g., a source) connected to the node LA, a gate connected to the complementary bitline BLB, and a second end (e.g., a drain) connected to the bitline BL. The transistor MSP2may include a first end (e.g., a source) connected to the node LA, a gate connected to the bitline BL, and a second end (e.g., a drain) connected to the complementary bitline BLB. The transistor MSN1may include a first end (e.g., a drain) connected to the bitline BL, a gate connected to the complementary bitline BLB, and a second end (e.g., a source) connected to the node LAB. The transistor MSN2may include a first end (e.g., a drain) connected to the complementary bitline BLB, a gate connected to the bitline BL, and a second end (e.g., a source) connected to the node LAB.

The first sensing unit PSA and the second sensing unit NSA may sense data stored in a memory cell with which a bitline pair BL and BLB is connected. Operations of the first sensing unit PSA and the second sensing unit NSA will be more fully described later.

A voltage level of the bitline BL may be changed from the precharge voltage charged by the voltage equalization circuit130through the charge sharing between the bitline BL and the first memory cell MC1. The first sensing unit PSA and the second sensing unit NSA may sense a change of the voltage level of the bitline BL.

The transistor MP may include a first end (e.g., a source) to which the internal voltage VINTA from the voltage generator16is applied, a gate to which a develop signal LAPG from the pulse generator114is applied, and a second end (e.g., a drain) connected to the node LA. In the embodiment that is illustrated inFIG. 3, the transistor MP may be implemented with a PMOS transistor.

The transistor MLAB1may include a first end (e.g., a drain) connected to the node LAB of the bitline sense amplifier120, a gate to which a develop signal LANG from the pulse generator114is applied, and a second end (e.g., a source) to which the ground voltage VSS is applied.

The regulator111of the bitline sense amplifier driver circuit110may adjust a level of a voltage (e.g., a pull-up gate voltage PU_N ofFIG. 4) to be supplied to the pull-up circuit112, based on the internal voltage VINTA and the pull-up reference voltage VREF_PU. The pull-up circuit112may pull up a level of the voltage VLAB, based on a voltage supplied from the regulator111and a signal applied from the pulse generator114. The pull-down circuit113may pull down a level of the voltage VLAB to the same level as the ground voltage VSS, based on a signal applied from the pulse generator114. The pulse generator114may generate various signals (e.g., the bitline sense amplifier enable signal BLSA_EN and the develop signals LAPG and LANG) to be used in the sense amplifier unit100, based on the signals WLACT, WREN, and PRCG received from the control logic11. Operations of the regulator111, the pull-up circuit112, the pull-down circuit113, and the pulse generator114will be more fully described later.

FIG. 4illustrates a circuit diagram of a bitline sense amplifier driver circuit ofFIG. 3according to example embodiments. Referring toFIGS. 1 to 4, the bitline sense amplifier driver circuit110may include the regulator111, the pull-up circuit112, and the pull-down circuit113. For convenience of illustration, the pulse generator114is omitted.

The regulator111may include an amplifier AMPR and a transistor MREF. The transistor MREF may include a first end (e.g., a source) to which the internal voltage VINTA from the voltage generator16is applied, a gate to which an output terminal of the amplifier AMPR is connected, and a second end (e.g., a drain) connected to the pull-up circuit112. In the embodiment that is illustrated inFIG. 4, the transistor MREF may be implemented with a PMOS transistor.

The amplifier AMPR may include a first input terminal to which the pull-up reference voltage VREF_PU from the voltage generator16is applied, a second input terminal connected to the pull-up circuit112, and the output terminal connected to the gate of the transistor MREF. The pull-up reference voltage VREF_PU may be a DC voltage.

Unlike the embodiment illustrated inFIG. 4, according to another embodiment of the inventive concept, a voltage having a level different from that of the internal voltage VINTA may be applied to the first end of the transistor MREF from the voltage generator16. For example, the voltage generator16may apply the received external voltage VEXT to the first end of the transistor MREF.

In an embodiment, a level of the pull-up reference voltage VREF_PU may be determined based on a characteristic of a die (or a chip) in which the memory cell array12is implemented. For example, a level of the pull-up reference voltage VREF_PU may be determined such that, due to the process, voltage and temperature variation, differences between physical characteristics of one or more dies where the memory cell array12is implemented cancel out. For another example, a level of the pull-up reference voltage VREF_PU may be determined to cancel out, in one die, a process error, which occurs during a process of manufacturing the die, such as an irregular surface or height or the like of a substrate.

The pull-up circuit112may include inverters INV1and INV2, pull-up transistors MPU1, MPU2, and MLAB2a, and a delta voltage generator112_1. The inverter INV2may receive a pull-up pulse PU_PULSE from the pulse generator114. The inverter INV2may output a voltage to the inverter INV1in response to the pull-up pulse PU_PULSE. The inverter INV1may output the pull-up gate voltage PU_N to a gate of the transistor MPU2in response to the voltage received from the inverter INV2and a voltage received from the second end of the transistor MREF.

The pull-up transistor MPU1may include a first end (e.g., a drain) to which the internal voltage VINTA from the voltage generator16is applied, a gate to which a pull-up pulse PLABUP is applied, and a second end (e.g., a source) connected to a first end (e.g., a drain) of the pull-up transistor MPU2. In the embodiment that is illustrated inFIG. 4, the pull-up transistor MPU1may be implemented with an NMOS transistor.

When the pull-up pulse PLABUP is not applied to the gate of the pull-up transistor MPU1, a current may not flow from the first end to the second end of the pull-up transistor MPU1. Accordingly, during a time interval where the pull-up pulse PLABUP is not applied from the pulse generator114, a current may be prevented from being leaked from the pull-up transistor MPU1to the pull-up transistor MPU2. As a result, when the pull-up pulse PLABUP is not applied, a current based on the internal voltage VINTA may be prevented from being leaked to the bitline sense amplifier120through the pull-up transistors MPU1and MPU2.

The pull-up transistor MPU2may include a first end (e.g., a drain) connected to the second end of the pull-up transistor MPU1, a gate to which the pull-up gate voltage PU_N is applied, and a second end (e.g., a source) connected to a first end (e.g., a drain) of the pull-up transistor MLAB2aand the node LAB. When a magnitude of the pull-up gate voltage PU_N is greater than a magnitude of a threshold voltage of the pull-up transistor MPU2, the pull-up transistor MPU22may be turned on. In the embodiment that is illustrated inFIG. 4, the pull-up transistor MPU22may be implemented with an NMOS transistor.

The pull-up transistor MLAB2amay include the first end (e.g., a drain) connected to the second end of the pull-up transistor MPU2and the node LAB, a gate to which the pull-up pulse PLABUP is applied, and a second end (e.g., a source) connected to the delta voltage generator112_1.

The delta voltage generator112_1may provide the voltage VLAB, which is greater than the ground voltage VSS as much as a delta voltage (e.g., dVLABa ofFIG. 6Aor dVLABb ofFIG. 6B), to the node LAB through the pull-up transistor MLAB2a. As a result, the pull-up circuit112may pull up the voltage VLAB of the node LAB from the ground voltage VSS to a voltage greater than the ground voltage VSS by supplying a voltage generated from the delta voltage generator112_1to the node LAB in response to the pull-up pulses PU_PULSE and PLABUP. An operation of the delta voltage generator112_1will be more fully described with reference toFIGS. 6A and 6B.

The pull-down circuit113may include a pull-down transistor MPD. The pull-down transistor MPD may include a first end (e.g., a drain) connected to the node LAB, a gate to which a pull-down pulse PLABDN from the pulse generator114is applied, and a second end (e.g., a source) connected to the ground voltage VSS.

FIG. 5illustrates a timing diagram of waveforms of a signal applied to a bitline sense amplifier driver circuit, signals used in the bitline sense amplifier driver circuit, a voltage of a bitline, and a voltage of a complementary bitline, according to example embodiments.FIG. 5will be described with reference toFIGS. 1 to 4.

In a first phase Phase1 or in a charge sharing operation mode, the control logic11may generate the wordline active signal WLACT in response to the command/address CA requesting the activation of a wordline (e.g., WL0). In the embodiment that is illustrated inFIG. 5, a high level of the wordline active signal WLACT may be maintained during a time period tCgShr. As the wordline active signal WLACT is activated, the voltage VBL precharged at the bitline BL may be shared with a voltage charged in a capacitor (e.g., CS1) of a memory cell (e.g., MC1) connected to the wordline WL0and the bitline BL through the process of charge sharing.

For example, as illustrated inFIG. 2, the memory device10may receive an access request for the wordline WL0connected to the first memory cell MC1from the external device. In this case, the memory device10may receive the command/address CA including the row address ADDR_R of the first memory cell MC1and the active command. As the command/address CA is received, a voltage, the level of which is equal to or higher than that of a sum of a driving voltage of the memory device10and a turn-on voltage of a transistor in a memory cell, may be supplied to the wordline WL0. As such, transistors (e.g., TR1) connected to the wordline WL0may be turned on.

Assuming that data “1” is stored in the first memory cell MC1, as the transistor TR1is turned on, a voltage (corresponding to data “1”) stored in the capacitor CS1may be transferred to the bitline BL through the transistor TR1. In contrast, assuming that data “0” is stored in the first memory cell MC1(i.e., assuming that the capacitor CS1is not charged), as the transistor TR1is turned on, a voltage charged at the bitline BL may be transferred to the capacitor CS1. In other words, as the wordline WL0is activated, charges of the capacitor CS1of the first memory cell MC1may be shared with charges of the bitline BL, the charges which were charged by the voltage equalization circuit130, through the process of charge sharing.

In a second phase Phase2, or in a sensing operation mode, after the time period tCgShr from a time when the wordline active signal WLACT transitions to the high level, the bitline sense amplifier enable signal BLSA_EN and the develop signal LANG may transition to the high level, and the develop signal LAPG may transition to a low level.

The transistor MP of the bitline sense amplifier120may be turned on in response to the low level of the develop signal LAPG. For example, as illustrated inFIG. 3, when the develop signal LAPG is applied to the gate of the transistor MP, the internal voltage VINTA may be supplied to the first sensing unit PSA of the bitline sense amplifier120through the transistor MP. As such, a voltage level of the bitline BL may increase. In this case, the voltage level of the bitline BL may be a voltage level corresponding to data “1”. For example, the bitline sense amplifier120may develop the voltage of the bitline BL to the voltage corresponding to data “1” in response to the develop signal LAPG.

The transistor MN may be turned on in response to the high level of the bitline sense amplifier enable signal BLSA_EN. For example, as illustrated inFIG. 3, when the bitline sense amplifier enable signal BLSA_EN is applied to the gate of the transistor MN, the internal voltage VINTA may be supplied to the bitline sense amplifier120through the transistor MN. As such, the bitline sense amplifier120may be driven.

The transistor MLAB1may be turned on in response to the develop signal LANG. As such, the voltage VBL of the bitline BL may increase, and a voltage VBLB of the complementary bitline BLB may decrease (corresponding to data “1”).

In a third phase Phase3, the pull-up pulses PLABUP and PU_PULSE may transition from the low level to the high level, and the develop signal LANG may transition from the high level to the low level. In response to the pull-up pulse PU_PULSE, the pull-up gate voltage PU_N may be applied to the pull-up transistor MPU2. For example, a read operation or a write operation may be performed in the third phase Phase3.

For example, as illustrated inFIG. 4, when the pull-up pulse PLABUP is applied to the pull-up transistor MLAB2a, the pull-up transistor MLAB2amay be turned on. As such, the voltage VLAB generated by the delta voltage generator112_1may be provided to the node LAB through the pull-up transistor MLAB2a.

In an embodiment, the pull-up pulses PLABUP and PU_PULSE may transition to the high level after at least a time tRCD from a time when the pulse generator114receives the wordline active signal WLACT from the control logic11. The time tRCD may be between the issuing of the active command and the read/write command. The time tRCD may be a time necessary for the sense amplifier unit100to sense and amplify data stored in the first memory cell MC1. The wordline active signal WLACT (e.g., the selected word line WL0) may be transited to a high level in response to the active command ACT. As such, the time tRCD may be sufficiently secured. The pull-up pulse PU_PULSE may have the high level during a time period tA. The time period tA may be an adjusted delay time delayed by an adjustable delay circuit DA (refer toFIG. 7).

The transistor MLAB1may be turned off in response to the low level of the develop signal LANG. The pull-up transistors MPU1, MPU2, and MLAB2amay be turned on in response to the pull-up pulses PU_PULSE and PLABUP and the pull-up gate voltage PU_N. As such, the voltage VBLB of the complementary bitline BLB may be pulled up from the ground voltage GND by the delta voltage generator112_1as much as a delta voltage dVLAB.

When the pull-up pulse PU_PULSE again transitions to the low level after the time period to passes, a magnitude of the pull-up gate voltage PU_N may decrease. As such, the pull-up transistor MPU22may be turned off. When the pull-up transistor MPU2is turned off, the delta voltage dVLAB may not be supplied to the bitline sense amplifier120. As such, the voltage VBLB of the complementary bitline BLB may again decrease to the ground voltage VSS after a given time passes.

In an example embodiment, the control logic11may generate the write enable signal WREN in response to the command/address CA for writing data in a memory cell (e.g., MC1) connected to a wordline (e.g., WL0) activated by the wordline active signal WLACT and the bitline BL. A write column select signal WRITE_CSL may be applied to the column select line CSL in response to the write enable signal WREN. The sense amplifier unit100may write new data in a target memory cell in response to the write column select signal WRITE_CSL. For example, the sense amplifier unit100may charge a voltage corresponding to the new data in a capacitor (e.g., CS1) of a memory cell (e.g., MC1) connected to a bit line (e.g., BL) corresponding to the write column select signal WRITE_CSL from among a plurality of bitlines.

Alternatively, the sense amplifier unit100may restore data stored in respective memory cells connected to the wordline (e.g., WL0) activated by the wordline active signal WLACT in the respective memory cells. For example, the sense amplifier unit100may again charge voltages corresponding to data sensed by the bitline sense amplifier120in capacitors in the memory cells, respectively.

To perform a write operation on new data as the write column select signal WRITE_CSL transitions to the high level, there may be a need to pull down a level of a voltage VBL/VBLB of the bitline BL/complementary bitline BLB to a level of the ground voltage VSS during a given time. In the embodiment that is illustrated inFIG. 5, a level of the voltage VBLB of the complementary bitline BLB may be pulled down to the level of the ground voltage VSS.

After a time tWRITE passes from a time when the write column select signal WRITE_CSL transitions to the high level, the pull-up pulse PU_PULSE may have the high level during a time period tB. The time tWRITE may be a time necessary for the sense amplifier unit100to write new data in a target memory cell. The time period tB may be an adjusted delay time delayed by the adjustable delay circuit DA (refer toFIG. 7).

In response to the pull-up pulse PU_PULSE, the pull-up gate voltage PU_N may be applied to the pull-up transistor MPU2. The pull-up transistor MPU22may again be turned on in response to the pull-up gate voltage PU_N. As such, the delta voltage dVLAB may be supplied to the bitline sense amplifier120by the delta voltage generator112_1, and thus, the voltage VBLB of the complementary bitline BLB may again be pulled up as much as the delta voltage dVLAB.

In an example embodiment, in the third phase Phase3, the memory device10may perform a read operation in response to the command/address CA. For example, the external device may transmit the command/address CA, which includes the column address ADDR_C indicating the first memory cell MC1and a read command. For example, the memory device10may perform a read operation in response to the command/address CA. In a read operation, the sense amplifier unit100may transmit the amplified data of a difference between a voltage of the bitline BL and a voltage of the complementary bitline BLB to the input/output buffer15.

The control logic11may transmit the precharge signal PRCG to the sense amplifier unit100in response to the command/address CA requesting the precharge operation.

In a fourth phase Phase4, or in a precharge operation mode, the pull-up pulse PLABUP may transition to the low level, and the develop signal LANG and the pull-down pulse PLABDN may transition to the high level. The transistor MLAB1may be turned on in response to the high level of the develop signal LANG. The transistor MPD may be turned on in response to the high level of the pull-down pulse PLABDN. For example, when the pull-down pulse PLABDN is applied to the pull-down transistor MPD, the pull-down transistor MPD may be turned on. As such, the voltage VLAB of the node LAB may be pulled down to the ground voltage GND. For example, the pull-down circuit113may pull down the voltage VLAB in response to the pull-down pulse PLABDN received from the pulse generator114. As the transistors MLAB1and MPD are turned on, the voltage VLAB of the complementary bitline BLB may be pulled down to the level of the ground voltage VSS.

In the embodiment that is illustrated inFIG. 5, the develop signal LANG and the pull-down pulse PLABDN may have the high level during a time tWR. As such, the time tWR necessary for the memory device10to perform a write restore operation may be sufficiently secured.

After the time tWR passes from a time when the develop signal LANG and the pull-down pulse PLABDN transition to the high level, the bitline sense amplifier enable signal BLSA_EN, the develop signal LANG, and the pull-down pulse PLABDN may transition to the low level, and the develop signal LAPG may transition to the high level. As such, the internal voltage VINTA may not be supplied to the bitline sense amplifier120. For example, the bitline sense amplifier120may be deactivated. The voltage equalization circuit130may equalize the voltages VBL and VBLB of the bitline BL and the complementary bitline BLB to the precharge voltage in response to the precharge signal PRCG.

FIG. 6Aillustrates a pull-up circuit ofFIG. 4in detail, according to an embodiment of the inventive concept.FIG. 6Billustrates a pull-up circuit ofFIG. 4in detail, according to another embodiment of the inventive concept. Referring toFIGS. 1 to 4, 6A, and 6B, the pull-up circuit112may include delta voltage generators112_1aand1121b.

in the embodiment that is illustrated inFIG. 6A, the delta voltage generator112_1amay include transistors MLAB2nand MLAB2pand amplifiers AMPn and AMPp. In the embodiment that is illustrated inFIG. 6A, the transistor MLAB2nmay be implemented with an NMOS transistor, and the transistor MLAB2pmay be implemented with a PMOS transistor. In the embodiment that is illustrated inFIG. 6A, the amplifiers AMPn and AMPp may be implemented with a class AB amplifier or a class B amplifier.

The transistor MLAB2nmay include a first end (e.g., a drain) connected to the second end of the pull-up transistor MLAB2a, a gate connected to an output terminal of the amplifier AMPn, and a second end (e.g., a source) connected to the ground voltage VSS. The transistor MLAB2pmay include a first end (e.g., a source) connected to a voltage VDD1, a gate connected to an output terminal of the amplifier AMPp, and a second end (e.g., a drain) connected to the second end of the pull-up transistor MLAB2a. In an embodiment, the internal voltage VINTA may be applied to the first end of the transistor MLAB2pinstead of the voltage VDD1.

The amplifier AMPn may include a first input terminal to which a reference voltage VREF_VLAB is applied, a second input terminal connected to the second end of the pull-up transistor MLAB2a, and an output terminal connected to the gate of the transistor MLAB2n. The amplifier AMPp may include a first input terminal to which the reference voltage VREF_VLAB is applied, a second input terminal connected to the second end of the pull-up transistor MLAB2a, and an output terminal connected to the gate of the transistor MLAB2p.

In the embodiment that is illustrated inFIG. 6A, the reference voltage VREF_VLAB may be generated by the voltage generator16and may be supplied to the amplifiers AMPn and AMPp. The amplifiers AMPn and AMPp may amplify the delta voltage dVLABa based on the reference voltage VREF_VLAB and may output the amplified voltage. When a level of the voltage amplified by the amplifiers AMPn and AMPp is great enough to turn on the transistors MLAB2nand MLAB2p, the transistors MLAB2nand MLAB2pmay be turned on. As such, a magnitude of the delta voltage dVLAB ofFIG. 4applied to the second end of the pull-up transistor MLAB2amay change. For example, the magnitude of the delta voltage dVLAB may be adjusted based on the operations of the amplifiers AMPn and AMPp. The adjusted delta voltage dVLAB may be supplied to the node LAB of the bitline sense amplifier120through the pull-up transistor MLAB2ain response to the pull-up pulses PU_PULSE and PLABUP. In the embodiment that is illustrated inFIG. 6B, the delta voltage generator112_1bmay include a transistor MLAB2b. The transistor MLAB2bmay be implemented with an NMOS transistor. The transistor MLAB2bmay include a first end (e.g., a drain) connected to the second end of the pull-up transistor MLAB2a, a gate connected to the second end of the pull-up transistor MLAB2a, and a second end (e.g., a source) connected to the ground voltage VSS. In this case, the transistor MLAB2bmay be diode-connected.

In the embodiment that is illustrated inFIG. 6B, when the pull-up transistors MPU1and MLAB2aare turned on in response to the pull-up pulse PLABUP and the pull-up transistor MPU2is turned on in response to the pull-up pulse PU_PULSE, that is, the pull-up gate voltage PU_N, a current based on the internal voltage VINTA may be transferred to the transistor MLAB2bthrough the pull-up transistors MPU1, MPU2, and MLAB2a. In this case, the delta voltage dVLABb applied to the gate and the first end of the transistor MLAB2bmay be equal to the threshold voltage of the transistor MLAB2b. As a result, the delta voltage dVLABb greater than the ground voltage VSS as much as the threshold voltage of the transistor MLAB2bmay be supplied to the node LAB of the bitline sense amplifier120through the transistor MLAB2ain response to the pull-up pulses PU_PULSE and PLABPU.

In the embodiment that is illustrated inFIG. 6B, a level of the pull-up gate voltage PU_N may be equal to a level of the pull-up reference voltage VREF_PU. The pull-up reference voltage VREF_PU may be smaller than the internal voltage VINTA. Levels of the pull-up reference voltage VREF_PU and the internal voltage VINTA may be adjusted by the voltage generator16. For example, the voltage generator16may adjust a level of the pull-up gate voltage PU_N to be supplied from the regulator111to the pull-up circuit112by adjusting levels of the pull-up reference voltage VREF_PU and the internal voltage VINTA transmitted to the regulator111.

As the level of the pull-up gate voltage PU_N is adjusted, a magnitude of the voltage VLAB to be pulled up by the pull-up circuit112may be adjusted. For example, as illustrated inFIG. 4, the voltage generator16may adjust a level of a voltage to be output from the amplifier AMPR to the gate of the transistor MREF by adjusting a level of the pull-up reference voltage VREF_PU. As such, whether to turn on the transistor MREF may be determined. When the transistor MREF is turned on, a voltage that is determined based on the internal voltage VINTA and the pull-up reference voltage VREF_PU may be supplied to the pull-up circuit112through the transistor MREF. A voltage that is supplied from the regulator111to the pull-up circuit112may be applied to the gate of the pull-up transistor MPU2through the inverters INV2and INV1. A configuration of the delta voltage generator112_1is not limited to the embodiments illustrated inFIGS. 6A and 6B. Accordingly, the voltage VLAB may be pulled up to a voltage of an appropriate level in a manner different from those of the embodiment illustrated inFIGS. 6A and 6Bin consideration of the performance of the memory device10.

FIG. 7illustrates a block diagram of a pulse generator ofFIG. 4according to example embodiments. Referring toFIGS. 1 to 5 and 7, the pulse generator114may include delay circuits D1to D3, latches SR1to SR3, a flip-flop DFF1, XOR gates XOR1and XOR2, and the adjustable delay circuit DA.

In the embodiment that is illustrated inFIG. 7, the latches SR1to SR3may be implemented with an SR latch. In the embodiment that is illustrated inFIG. 7, the flip-flop DFF1may be implemented with a D flip-flop. In an embodiment, each of the delay circuits D1to D3may include one or more buffers connected in series. In this case, the number of buffers included in each of the delay circuits D1to D3may be determined based on a length of a time to be delayed by each of the delay circuits D1to D3. The embodiment illustrated inFIG. 7is exemplary, and a configuration of the pulse generator114according to an embodiment of the inventive concept is not limited thereto.

The delay circuit D1may receive the wordline active signal WLACT from the control logic11. After the time period tCgShr passes from a time when the delay circuit D1receives the wordline active signal WLACT, the delay circuit D1may output the received wordline active signal WLACT as a signal BLSA_ST to the latch SR1and the delay circuit D3. In an embodiment, the time period tCgShr may be a time necessary for the charge sharing between the bitline BL and a capacitor (e.g., CS1ofFIG. 2) included in a memory cell (e.g., MC1ofFIG. 2) connected to an activated word line (e.g., WL0ofFIG. 2) and the bitline BL when the wordline is activated.

The delay circuit D2may receive the precharge signal PRCG from the control logic11. After the time tWR passes from a time when the delay circuit D2receives the precharge signal PRCG, the delay circuit D2may output the received precharge signal PRCG as a signal BLSA_END to the latch SR1. In an embodiment, the time tWR may be a write recovery time.

The delay circuit D3may receive the signal BLSA_ST from the delay circuit D1. After at least the tRCD passes from a time when the delay circuit D1receives the wordline active signal WLACT, the delay circuit D3may output the received signal BLSA_ST as a signal BLSA_STD to the latch SR2and the XOR gate XOR2. In an embodiment, the time tRCD may be a RAS-to-CAS delay.

The latch SR1may receive the signal BLSA_ST from the delay circuit D1. The latch SR1may receive the signal BLSA_END from the delay circuit D2. The latch SR1may output the bitline sense amplifier enable signal BLSA_EN and the develop signal LAPG based on the received signals BLSA_ST and BLSA_END.

In the embodiment that is illustrated inFIG. 7, the latch SR1may use the signal BLSA_ST as a set signal and may use the signal BLSA_END as a reset signal. The latch SR1may latch the received signals BLSA_ST and BLSA_END and may output the bitline sense amplifier enable signal BLSA_EN to the XOR gate XOR1. The latch SR1may output the develop signal LAPG by inverting the bitline sense amplifier enable signal BLSA_EN. The develop signal LAPG may be transmitted to the bitline sense amplifier120.

The latch SR2may receive the signal BLSA_STD from the delay circuit D3. The latch SR2may receive the precharge signal PRCG from the control logic11. The latch SR2may output the pull-up pulse PLABUP based on the received signals BLSA_STD and PRCG.

In the embodiment that is illustrated inFIG. 7, the latch SR2may use the signal BLSA_STD as a set signal and may use the precharge signal PRCG as a reset signal. The latch SR2may output the pull-up pulse PLABUP by latching the received signals BLSA_STD and PRCG. The pull-up pulse PLABUP may be transmitted to the XOR gate XOR1and the pull-up circuit112.

The XOR gate XOR1may receive the bitline sense amplifier enable signal BLSA_EN from the latch SR1. The XOR gate XOR1may receive the pull-up pulse PLABUP from the latch SR2. The XOR gate XOR1may output the develop signal LANG to the bitline sense amplifier120based on the bitline sense amplifier enable signal BLSA_EN and the pull-up pulse PLABUP.

The flip-flop DFF1may receive the bitline sense amplifier enable signal BLSA_EN from the latch SR1. The flip-flop DFF1may receive the write enable signal WREN from the control logic11. The flip-flop DFF1may receive a signal SNORD from the adjustable delay circuit DA. In an embodiment, the flip-flop DFF1may be a negative edge-triggered flip-flop. The flip-flop DFF1may output a signal WRENEDGE to the XOR gate XOR2based on the signals BLSA_STD, WREN, and SNORD.

In the embodiment that is illustrated inFIG. 7, the flip-flop DFF1may use the signal BLSA_EN as a data input. The flip-flop DFF1may use the write enable signal WREN as a clock input. The flip-flop DFF1may use the signal SNORD as a reset signal. In response to a falling edge of the write enable signal WREN, the flip-flop DFF1may output the signal WRENEDGE to the XOR gate XOR2based on the signals BLSA_EN and SNORD.

The XOR gate XOR2may receive the signal BLSA_STD from the delay circuit D3. The XOR gate XOR2may receive the signal WRENEDGE from the flip-flop DFF1. The XOR gate XOR2may output a signal SNOR to the latch SR3and the adjustable delay circuit DA based on the signals BLSA_STD and WRENEDGE.

The adjustable delay circuit DA may receive the signal SNOR. After an adjusted delay time from a time when the adjustable delay circuit DA receives the signal SNOR, the adjustable delay circuit DA may output the signal SNOR as the signal SNORD to the latch SR3. In this case, a level of the voltage VLAB may depend on a length of the adjusted delay time.

In an embodiment, the adjusted delay time delayed by the adjustable delay circuit DA may be determined based on a characteristic of a die where the memory cell array12is implemented. For example, the adjusted delay time may be determined in a manner similar to a manner to determine a level of the pull-up reference voltage VREF_PU described above.

In the embodiment that is illustrated inFIG. 7, the adjustable delay circuit DA may include a plurality of delay circuits “D” connected in series and a multiplexer MUX. A manner where the adjustable delay circuit DA is capable of being implemented is not limited to the embodiment illustrated inFIG. 7.

Each of the delay circuits “D” in the adjustable delay circuit DA may output a received signal to the multiplexer MUX and the delay circuit “D” connected to an output terminal of each thereof after a given time passes. For example, the delay circuit “D” receiving the signal SNOR from among the delay circuits “D” may output the received signal SNOR to the multiplexer MUX and the delay circuit “D” connected to the output terminal of the delay circuit “D” receiving the signal SNOR after a given time passes. For another example, the delay circuit “D”, the output terminal of which is not connected to the delay circuit “D”, from among the delay circuits “D” may output a received signal to the multiplexer MUX after a given time passes.

The multiplexer MUX may receive a selection signal SEL from the control logic11. The multiplexer MUX may select one of the signals received from the delay circuits “D” based on the selection signal SEL. The multiplexer MUX may output the selected signal as the signal SNORD to the latch SR3. In an embodiment, the control logic11may adjust a length of an adjusted delay time delayed by the adjustable delay circuit DA by using the selection signal SEL.

The latch SR3may receive the signal SNOR from the XOR gate XOR2. The latch SR3may receive the signal SNORD from the adjustable delay circuit DA. The latch SR3may output the pull-up pulse PU_PULSE based on the received signals SNOR and SNORD.

In the embodiment that is illustrated inFIG. 7, the latch SR3may use the signal SNOR as a set signal and may use the signal SNORD as a reset signal. The latch SR3may output the pull-up pulse PU_PULSE to the pull-up circuit112by latching the signals SNOR and SNORD.

In an embodiment, the pulse generator114may further include a pull-down pulse generating circuit (not illustrated) that generates the pull-down pulse PLABDN. The pull-down pulse generating circuit may receive the precharge signal PRCG from the control logic11. The pull-down pulse generating circuit may generate the pull-down pulse PLABDN in response to the received precharge signal PRCG. In this case, the pull-down pulse PLABDN may be generated to have a level corresponding to logic “1” as much as the time tWR from a time when the pull-down pulse generating circuit receives the precharge signal PRCG. The pull-down pulse PLABDN may be transmitted to the pull-down circuit113.

FIG. 8illustrates a flowchart of an operating method of a memory device according to an embodiment of the inventive concept. Referring toFIGS. 1 to 4 and 8, the memory device10may perform operation S100to operation S300.

In operation S100, the memory device10may activate a target wordline. For example, the memory device10may select a wordline corresponding to the command/address CA received from the external device and may supply the selected wordline with a voltage capable of turning on transistors connected to the selected wordline.

In operation S200, the memory device10may restore data of the memory cell array12or may write data in the memory cell array12, and may pull up a voltage of the node LAB in the bit line sense amplifier120. For example, the memory device10may sense data stored in the memory cells connected to the target wordline activated in operation S100. When data to be stored in a target memory cell of the memory cells connected to the target wordline are not input to the memory device10, the memory device10may restore data to the memory cells connected to the target wordline. If not (i.e., when new data are input to the memory device10), the memory device10may write the new data to the target memory cell. In this case, a data restore operation may be performed on the remaining memory cells of the memory cells connected to the target wordline except for the target memory cell. The memory device10may pull up the voltage VLAB of the node LAB in response to the wordline active signal WLACT and the write enable signal WREN.

In operation S300, the memory device10may pull down the voltage VLAB of the node LAB to the ground voltage VSS in response to the precharge signal PRCG. For example, the memory device10may pull down the voltage VLAB of the node LAB to the ground voltage VSS during a given time in response to the precharge signal PRCG. Afterwards, the memory device10may set voltages of the bitline BL and the complementary bitline BLB to the precharge voltage (e.g., ½ VINTA).

FIG. 9illustrates a flowchart of an operating method of a system including a memory device according to an embodiment of the inventive concept. Referring toFIGS. 1 to 4 and 7 to 9, the external device of the memory device10may perform operation S1101, operation S1104, and operation S1106, and the memory device10may perform operation S1102, operation S1103, operation S1105, operation S1107, and operation S1108.

In operation S1101, the external device may transmit a first command/address CA1to the memory device10. For example, the first command/address CA1may include the row address ADDR_R corresponding to a wordline target for activation (i.e., a target wordline) and an active command for activating the target wordline.

In operation S1102, the memory device10may generate the develop signals LAPG and LANG and may activate the bitline sense amplifier120. For example, the memory device10may activate the target wordline in response to the first command/address CA1thus received. The memory device10(i.e., the bitline sense amplifier120of the memory device10) may develop the voltage VBL of the bitline BL and the voltage VBLB of the complementary bitline BLB, based on the develop signals LAPG and LANG and the bitline sense amplifier enable signal BLSA_EN.

In the embodiment that is illustrated inFIG. 9, the memory device10may perform operation S1102after the time period tCgShr passes from a time when the first command/address CA1is received. For example, the memory device10may generate the wordline active signal WLACT in response to the first command/address CA1. After the time period tCgShr passes, the memory device10may generate the develop signals LANG and LAPG and the bitline sense amplifier enable signal BLSA_EN.

In operation S1103, the memory device10may generate a first pull-up pulse PU_PULSE1and may pull up a voltage level of the node LAB. In the embodiment that is illustrated inFIG. 9, the memory device10may perform operation S1103after the time tRCD passes from a time when the first command/address CA1is received. For example, after the time tRCD passes from a time when the wordline active signal WLACT is generated, the memory device10may generate the first pull-up pulse PU_PULSE1. In response to the first pull-up pulse PU_PULSE1, the bitline sense amplifier driver circuit110of the memory device10may pull up the voltage VLAB of the node LAB from the ground voltage VSS as much as the delta voltage dVLAB. In an embodiment, the first pull-up pulse PU_PULSE1may correspond to the pull-up pulse PU_PULSE having the high level during the time period tA, in the third phase Phase3 ofFIG. 7.

In operation S1104, the external device may transmit a second command/address CA2to the memory device10. For example, the second command/address CA2may include a write command and the column address ADDR_C indicating a target memory cell targeted for the write operation.

In operation S1105, the memory device10may generate a second pull-up pulse PU_PULSE2and may pull up a voltage level of the node LAB. For example, the memory device10may write data in the target memory cell in response to the second command/address CA2. Next, the memory device10may generate the second pull-up pulse PU_PULSE2. In response to the second pull-up pulse PU_PULSE2, the bitline sense amplifier driver circuit110may pull up the voltage VLAB of the node LAB from the ground voltage VSS as much as the delta voltage dVLAB. In an embodiment, the second pull-up pulse PU_PULSE2may correspond to the pull-up pulse PU_PULSE having the high level during the time period tB, in the third phase Phase3 ofFIG. 7.

In operation S1106, the external device may transmit a third command/address CA3to the memory device10. For example, the third command/address CA3may include a precharge command for requesting the memory device10to perform the precharge operation on the bitline BL and the complementary bitline BLB.

In operation S1107, the memory device10may generate the pull-down pulse PLABDN and may pull down a voltage level of the node LAB to the ground voltage GND. For example, the memory device10may generate the precharge signal PRCG in response to the third command/address CA3thus received. The memory device10may generate the pull-down pulse PLABDN based on the precharge signal PRCG. In response to the pull-down pulse PLABDN, the bitline sense amplifier driver circuit110may pull down the voltage VLAB of the node LAB to the ground voltage VSS.

In operation S1108, the memory device10may set the bitline BL and the complementary bitline BLB to the precharge voltage. In the embodiment that is illustrated inFIG. 9, the memory device10may perform operation S1108after the time tWR passes from a time when the precharge signal PRCG is generated.

According to an embodiment of the inventive concept, a low level of a voltage to be developed by a bitline sense amplifier may be adjusted based on a command received from an external device so as to be greater than a ground voltage or equal to the ground voltage. As such, the amount of leakage current of a memory cell array due to an operation of the bitline sense amplifier may decrease. Also, data stored in the memory cell array may be prevented from being lost.