Nonvolatile memory device with simultaneous read/write

A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile memory device with simultaneous read/write.

2. Description of the Related Art

To optimize read/write performance of nonvolatile memory devices, it is extremely important to be able to execute parallel read/write operations on more than one cell. Various solutions are known to the art which enable increase of the number of memory cells that are selected simultaneously to be read or written (page read/write or “burst mode”). The same type of operation, either read or write, is usually performed on all of the cells selected.

During reading, in practice, the selected cells are connected to respective sense amplifiers, which compare the threshold voltages of the cells with the threshold voltages of respective reference cells.

During writing, which may envisage programming or erasing of the selected cells, a cycle comprising two steps is executed at least once. Initially, the selected cells are biased with preset voltages and/or biasing currents so as to modify their threshold voltages. Then, reading is performed to verify the value actually reached by the threshold voltages. If this value is insufficient, the cycle is repeated. Moreover, in the case of multilevel memories, it is in any case necessary to execute more than one cycle.

Writing cannot in general be performed simultaneously with reading. In fact, during verifying of the threshold voltages, the cells must be connected to the sense amplifiers, which thus are not available for reading other cells. In addition, verifying is performed synchronously with an internal timing signal of the memory devices, while ordinary reading is asynchronous. It is consequently evident that also the driving signals and reference signals are different for verifying and reading.

To overcome the described drawbacks, architectures of nonvolatile memories have been proposed which enable simultaneous reading on a first set of cells and writing on a second set of cells (dual working). According to these solutions, in practice, the memory array is divided into sections, and associated to each section is a set or bank of sense amplifiers and a column decoder circuit. The banks of sense amplifiers are independent of one another and thus may be driven simultaneously in different ways. More precisely, while a first bank of sense amplifiers is driven in a synchronous way (verify), a second bank may be driven in an asynchronous way (read). In this way, it is therefore possible to perform simultaneously read and write operations, provided that cells are selected belonging to distinct sections of the memory.

Also this solution presents evident limits in so far as the memory array cannot be divided into a large number of sections. In fact, since each section should be associated to a respective bank of sense amplifiers, fractioning of the memory also entails an increase in the overall dimensions of the device; the more the memory is fractioned, the greater the overall dimensions. Consequently, the memory arrays normally comprise two or at the most four sections. On the other hand, the low fractioning of the memory causes simultaneous access to reading and writing to be relatively infrequent and thus far from effective. In any case, in fact, it is not possible to simultaneously read and write cells belonging to the same section.

BRIEF SUMMARY OF THE INVENTION

The aim of the present invention is to provide a memory device free from the limitations outlined above.

According to the present invention a nonvolatile memory device with simultaneous read/write is provided as defined in claim1.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIG. 1, a nonvolatile memory device1comprises a memory array2, a read column decoder3, a verify column decoder4, a read circuit5, an address bus6, and a control unit9.

The memory array2comprises a plurality of cells7, divided into a plurality of memory banks8and organized into rows and columns; by way of example, the memory banks8are sixteen. In greater detail, within a same memory bank8, cells7arranged on a same column have respective drain terminals connected to a same local bitline10and cells arranged on a same row have respective gate terminals connected to a same wordline11. In addition, each of the memory banks8has a first set of outputs, connected to the read column decoder3through respective global read bitlines12, and a second set of outputs, connected to the verify column decoder4through respective global verify bitlines13(in one embodiment as described herein, the number of global read bitlines12is equal to the number of global verify bitlines13, but they may be different in number if desired). The wordlines11are connected to a row decoder (of a known type and not illustrated herein for simplicity). The global verify bit lines are used during the writing operation.

The memory array2moreover has: first and second address inputs2a,2b, connected to the address bus6and receiving a plurality of first-level address signals Y1and second-level address signals Y2, respectively; and a plurality of read/write selection inputs2c, which receive read/write selection signals RWSEL0, RWSEL1, . . . , RWSELK, which indicate the operative access modality to the cells7. In particular, K is the number of read/write selection inputs2cand is equal to the number of global read bitlines12.

The read circuit5comprises a plurality of read sense amplifiers15and a plurality of verify sense amplifiers16. In particular, the read sense amplifiers15are connected to respective outputs of the read decoder3, while the verify sense amplifiers16are connected to respective outputs of the verify decoder4. In addition, the read column decoder3and the column decoder4have respective inputs3a,4aconnected to the data bus6and receiving a plurality of third-level address signals Y3. In addition, the control unit9has: read driving outputs9a, which are connected to respective driving inputs15aof the read sense amplifiers15and supply read driving signals SDR; read reference outputs9b, which are connected to respective reference inputs15bof the read sense amplifiers15and supply read reference signals SREFR; verify driving outputs9c, which are connected to respective driving inputs16aof the verify sense amplifiers16and supply verify driving signals SDV; verify reference outputs9d, which are connected to respective reference inputs16bof the verify sense amplifiers16and supply verify reference signals SREFV; and a timing output9e, which supplies a timing signal CK. In particular, the verify driving signals SDVare synchronous with the timing signal CK, while the read driving signals SDRare asynchronous.

In practice, whenever a read/write operation is required, the read column decoder3selects a set of global read bitlines12on the basis of the third-level address signals Y3and connects them to a respective read sense amplifier15; likewise, the verify column decoder4selects a set of global verify bitlines13on the basis of the third-level address signals Y3and connects them to respective verify sense amplifiers16.

As illustrated in detail inFIG. 2, in addition to the respective cells7and local bitlines10, each memory bank8comprises a plurality of first-level local decoders18, second-level local decoders19and read/write selectors, which, hereinafter, are referred to as R/W selectors20.

Each of the first-level local decoders18, of a per se known type, has a plurality of selection inputs, connected to respective local bitlines10, and a plurality of control inputs, which form the first address inputs2aof the memory array2; consequently, each of the first-level local decoders18receives the first-level address signals Y1.

Each of the second-level local decoders19, which are also of a known type, has a plurality of selection inputs, connected to outputs18aof respective first-level local decoders18, and a plurality of control inputs, which form the second address inputs2bof the memory array2; consequently, each of the second-level local decoders19receives the second-level address signals Y2.

In practice, each memory bank8comprises a plurality of local decoding branches23, each of which comprises a second-level local decoder19and the local bitlines10and the first-level local decoders18dependent upon this second-level local decoder19. At each read/write operation, each local decoding branch23selects a local bitline10on the basis of the values of the first-level and second-level address signals Y1, Y2.

Each R/W selector20has an input, connected to an output19aof a respective second-level local decoder19; a first output, connected to a respective global read bitline12; a second output, connected to a respective global verify bitline13; and a control terminal, connected to a respective read/write selection input2cof the memory array2and receiving a respective of the read/write selection signals RWSEL0, RWSEL1, . . . , RWSELK. The R/W selectors20are consequently associated to respective sets of cells7and can be controlled individually and independently of one another.

In greater detail, each R/W selector20preferably comprises a read selector24and a write selector25, for example made of MOS transistors. The read selector24and write selector25of each R/W selector20have respective first terminals in common, connected to the output19aof the respective second-level local decoder19, and second terminals, one of which forms the first output and the other the second output of the R/W selector20. In addition, the read selector24and the write selector25are controlled in phase opposition according to the value of the respective read/write selection signal RWSEL0, RWSEL1, . . . , RWSELK. In practice, when the read/write selection signal RWSEL0, RWSEL1, . . . , RWSELKsupplied to one of the R/W selectors20assumes a read value, for example, a high value, the corresponding read selector24is closed, while the write selector25is open; instead, When the read/write selection signal RWSEL0, RWSEL1, . . . , RWSELKhas a write value (low), the read selector24is open and the write selector25is closed. In this way, the output19aof each second-level local decoder19is alternately connectable to a global read bitline12and to a global verify bitline13through the respective R/W selector20, according to the operative access modality indicated by the respective read/ write selection signal RWSEL0, RWSEL1, . . . , RWSELK.

As mentioned previously, when a read/write operation of the memory array2is required, each local decoding branch23of the memory banks8addresses a respective local bitline10according to the first-level and second-level address signals Y1, Y2and connect it to the respective R/W selector20. In turn, the R/W selector20connects the respective addressed local bitline10(and the cells7associated thereto) to a global read bitline12or a to a global verify bitline13according to the value of the respective read/write selection signal RWSEL0, RWSEL1, . . . , RWSELK.

In greater detail, when it is necessary to execute a normal reading operation of the cells7addressed by one of the local decoding branches23, the corresponding read/write selection signal RWSEL0, RWSEL1, . . . , RWSELKis set at the read value. In this case, in practice, the addressed cells7are connected to the read column decoder3through the global read bitlines12; furthermore, according to the third-level address signals Y3, the read column decoder3selects and connects a preset number of global read bitlines12to respective read sense amplifiers15.

When the cells7addressed by one of the local decoding branches23is to be verified after programming or erasing, the respective read/write selection signal RWSEL0, RWSEL1, . . . , RWSELKis set at the write value. The addressed cells7are consequently connected to the verify column decoder4through the global verify bitlines13. On the basis of the third-level address signals Y3, the verify column decoder4selects and connects a preset number of global verify bitlines13to respective verify sense amplifiers16. At a same instant, the read/write selection signals RWSEL0, RWSEL1, . . . , RWSELKmay clearly assume values different from one another, and consequently normal reading operations or verifying operations after writing are altogether independent and may be executed simultaneously.

From the above, it is evident that the invention enables simultaneous read/write access to be exploited in an extremely effective and flexible way. In fact, each local decoding branch23can be connected both to the global read bitlines12and to the global verify bitlines13, independently of the other local decoding branches23. Consequently, it is always possible to gain access simultaneously to cells7belonging to distinct local decoding branches23for reading and writing, even if the cells7belong to the same memory bank8. In addition, the overall dimensions of the device1are contained and are substantially independent of the fractioning level of the memory array2. In fact, the described memory device1comprises just one bank of read sense amplifiers15and just one bank of verify sense amplifiers16, whatever the number of memory banks8and of local decoding branches23.

A different embodiment of the invention is illustrated inFIG. 3, where parts equal to those already illustrated are designated by the same reference numbers. In this case, in a nonvolatile memory device1′, each memory bank8is provided with a respective read/write selection input8a, to which a respective read/write selection signal RWSEL is supplied; furthermore, all the control terminals of the R/W selectors20of a same memory bank8are connected to its read/write selection input8aand thus receive the same signal. All the R/W selectors20of a same memory bank8are thus controlled in phase. In this way, all the cells7addressed by the local decoding branches23of a same memory bank8are connected either to the global read bitlines12, for a read operation, or to the global verify bitlines13, for a verify operation after writing. However, while the global read bitlines12are used by the cells7of a memory bank8, the global verify bitlines13may be connected to cells7belonging to a different memory bank8(supplied to the memory banks8are, in fact, read/write selection signals RWSEL which are independent of one another).

Also in this case, then, it is advantageously possible to gain access simultaneously for reading and writing the memory array2, with the sole constraint that the cells7to be read and those to be verified belong to distinct memory banks8. Since the memory array2may be easily fractioned into a large number of memory banks8(sixteen, in the examples described), the device1′ maintains in any case a considerable flexibility in the simultaneous access for reading and writing. In other words, dual working can be exploited in an efficient way. In addition, the number of inputs of the memory array2is reduced and the generation of the read/write selection signals is simplified.

Finally, it is clear that modifications and variations may be made to the memory device described herein, without thereby departing from the scope of the present invention.