Semiconductor memory device and memory system including the same

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority under 35 USC § 119 to Korean Patent Application No. 10-2021-0051584, filed on Apr. 21, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

The present disclosure relates to memories, and more particularly to semiconductor memory devices to perform relocking operation of a quadrature error correction circuit and memory systems including the same.

A semiconductor memory device may be classified as a volatile memory device or a nonvolatile memory device. A volatile memory device refers to a memory device that loses data stored therein at power-off. As an example of a volatile memory device, a dynamic random access memory (DRAM) may be used in various devices such as a mobile system, a server, or a graphic device.

A semiconductor memory device may operate in synchronization with a clock applied from an outside. When the externally applied clock is used in the semiconductor memory device, a time delay (or a clock skew) may occur due to an internal circuit of the semiconductor memory device. A circuit may be used to compensate for the time delay and correcting duty error.

SUMMARY

Example embodiments may provide a semiconductor memory device capable of performing a relocking operation of a quadrature error correction circuit.

Example embodiments may provide a memory system including a semiconductor memory device capable of performing a relocking operation of a quadrature error correction circuit.

According to example embodiments, a semiconductor memory device includes a data clock buffer, a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from a memory controller. The quadrature error correction circuit receives the first through fourth clock signals, performs a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data input/output (I/O) buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to the memory controller.

According to example embodiments, a memory system includes a semiconductor memory device and a memory controller to control the semiconductor memory device. The semiconductor memory device includes a data clock buffer, a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from the memory controller. The quadrature error correction circuit receives the first through fourth clock signals, performs a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data input/output (I/O) buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to the memory controller.

According to example embodiments, a semiconductor memory device includes a data clock buffer, a quadrature error correction circuit, a duty cycle monitor, a clock generation circuit and a data input/output (I/O) buffer. The data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from a memory controller. The quadrature error correction circuit receives the first through fourth clock signals, performs a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode. The duty cycle monitor monitors duty cycles of the first corrected clock signal and the second corrected clock signal in the second operation mode and configured to provide the relock signal to the quadrature error correction circuit based on a result of the monitoring. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data input/output (I/O) buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to the memory controller.

Accordingly, the quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. Therefore, the semiconductor memory device may quickly response to change of operating condition and may enhance performance.

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

FIG.1is a block diagram illustrating a memory system20according to example embodiments.

Referring toFIG.1, the memory system20may include a memory controller100and a semiconductor memory device200.

The memory controller100may control overall operation of the memory system20. The memory controller100may control overall data exchange between an external host and the semiconductor memory device200. For example, the memory controller100may write data in the semiconductor memory device200or read data from the semiconductor memory device200in response to a request from the host.

In addition, the memory controller100may issue operation commands to the semiconductor memory device200for controlling the semiconductor memory device200.

In some example embodiments, the semiconductor memory device200is a memory device including dynamic memory cells such as a dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or a LPDDR5 SDRAM.

The memory controller100transmits a clock signal CK (the clock signal CK may be referred to as a command clock signal), a command CMD, and an address (signal) ADDR to the semiconductor memory device200. The memory controller100may transmit a data clock signal WCK to the semiconductor memory device200when the memory controller100transmits a write data signal DQ to the semiconductor memory device200or when the memory controller100receives a data signal DQ from the semiconductor memory device200. The memory controller100may apply a reset command RST corresponding to transmitting an initialization command to the semiconductor memory device200. The semiconductor memory device200may transmit data strobe signal DQS along with the data signal DQ to the memory controller100when the semiconductor memory device200transmits the data signal DQ to the memory controller100.

The semiconductor memory device200includes a memory cell array (MCA)300that stores the data signal DQ, a control logic circuit210, a quadrature error correction circuit (QEC)400and a clock generation circuit (CGC)600.

The control logic circuit210may control operations of the semiconductor memory device200. The quadrature error correction circuit400may generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least a skew and a duty error of at least some of first through fourth clock signals which are generated based on the data clock signal WCK. The clock generation circuit600may generate an output clock signal and the strobe signal DQS based on the first corrected clock signal and the second corrected clock signal.

The quadrature error correction circuit400may perform a locking operation to generate the first corrected clock signal and the second corrected clock signal by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and may perform a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode during a normal operation. The normal operation may refer to one of a read operation and a write operation. The normal operation condition may be predetermined by users or standard specifications.

The memory controller100may include a duty cycle detector (DCD)110. The duty cycle detector110may detect a duty cycle of the strobe signal DQS periodically or non-periodically and may transmit, to the semiconductor memory device200, a command including a relock signal RLK1designating the relocking operation based on the detected duty cycle.

The semiconductor memory device200may perform the relocking operation based on the relock signal RLK1or a relock signal (e.g., RLK2and RLK3) generated internally in the semiconductor memory device200.

FIG.2is a block diagram illustrating the semiconductor memory device200inFIG.1according to example embodiments.

Referring toFIG.2, the semiconductor memory device200may include the control logic circuit210, an address register220, a bank control logic230, a refresh counter245, a row address multiplexer240, a column address latch250, a row decoder260, a column decoder270, the memory cell array300, a sense amplifier unit285, an I/O gating circuit290, an error correction code (ECC) engine390, a clock buffer225, a data clock buffer235, the quadrature error correction circuit400, a clock generation circuit600, a duty cycle monitor (DCM)680and a data I/O buffer320.

The memory cell array300includes first through eighth bank arrays310a˜310h. The row decoder260includes first through eighth row decoders260a˜260hrespectively coupled to the first through eighth bank arrays310a˜310h, the column decoder270includes first through eighth column decoders270a˜270hrespectively coupled to the first through eighth bank arrays310a˜310h, and the sense amplifier unit285includes first through eighth sense amplifiers285a˜285hrespectively coupled to the first through eighth bank arrays310a˜310h.

The first through eighth bank arrays310a˜310h, the first through eighth row decoders260a˜260h, the first through eighth column decoders270a˜270hand first through eighth sense amplifiers285a˜285hmay form first through eighth banks. Each of the first through eighth bank arrays310a˜310hincludes a plurality of memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-line BTL.

The address register220may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from the memory controller100. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, may provide the received row address ROW_ADDR to the row address multiplexer240, and may provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to the bank address BANK_ADDR. One of the first through eighth row decoders260a˜260hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the first through eighth column decoders270a˜270hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and may receive a refresh row address REF ADDR from the refresh counter245. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh row address REF ADDR as a row address RA. The row address RA that is output from the row address multiplexer240is applied to the first through eighth row decoders260a˜260h.

The refresh counter245may sequentially increase or decrease the refresh row address REF ADDR under control of the control logic circuit210.

The activated one of the first through eighth row decoders260a˜260h, by the bank control logic230, may decode the row address RA that is output from the row address multiplexer240, and may activate a word-line corresponding to the row address RA. For example, the activated bank row decoder applies a word-line driving voltage to the word-line corresponding to the row address.

The column address latch250may receive the column address COL_ADDR from the address register220, and may temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch250may generate column address COL_ADDR′ that increments from the received column address COL_ADDR. The column address latch250may apply the temporarily stored or generated column address COL_ADDR′ to the first through eighth column decoders270a˜270h.

The activated one of the first through eighth column decoders270a˜270hactivates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit290.

The I/O gating circuit290may include a circuitry for gating input/output data, and may further include input data mask logic, read data latches for storing data that is output from the first through eighth bank arrays310a˜310h, and write drivers for writing data to the first through eighth bank arrays310a˜310h.

Codeword CW read from one bank array of the first through eighth bank arrays310a˜310his sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and is stored in the read data latches. The codeword CW stored in the read data latches may be provided to the data I/O buffer320as data DTA after ECC decoding is performed on the codeword CW by the ECC engine390. The data I/O buffer320may convert the data DTA into the data signal DQ based on output clock signals OCLK and may transmit the data signal DQ along with the strobe signal DQS to the memory controller100.

The data signal DQ to be written in one bank array of the first through eighth bank arrays310a˜310hmay be provided to the data I/O buffer320from the memory controller100. The data I/O buffer320may convert the data signal DQ to the data DTA and may provide the data DTA to the ECC engine390. The ECC engine390may perform an ECC encoding on the data DTA to generate parity bits, and the ECC engine390may provide the codeword CW including data DQ and the parity bits to the I/O gating circuit290. The I/O gating circuit290may write the codeword CW in a sub-page in one bank array through the write drivers.

The data I/O buffer320may provide the data signal DQ from the memory controller100to the ECC engine390by converting the data signal DQ to the data DTA in a write operation of the semiconductor memory device200and may convert the data DTA to the data signal DQ from the ECC engine390based on the output clock signals OCLK from the clock generation circuit600, and may transmit the data signal DQ and the strobe signal DQS to the memory controller100in a read operation of the semiconductor memory device200. The data I/O buffer320may output the data signal DQ to the outside based on the output clock signals OCLK in the read operation.

The ECC engine390may perform an ECC encoding and an ECC decoding on the data DTA based on a first control signal CTL1from the control logic circuit210.

The clock buffer225may receive the clock signal CLK, may generate an internal clock signal ICK by buffering the clock signal CLK, and may provide the internal clock signal ICK to circuit components processing the command CMD and the address ADDR.

The data clock buffer235may receive the data clock signal WCK including differential clock signal pair WCK_t and WCK_c, may generate first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB based on the data clock signal WCK and may provide the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB to the quadrature error correction circuit400.

The quadrature error correction circuit400may perform a locking operation to generate a first corrected clock signal CCLKI and a second corrected clock signal CCLKQ which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB in a first operation mode corresponding to the initialization command and may provide the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ to the clock generation circuit600. The quadrature error correction circuit400may perform a relocking operation to lock the second corrected clock signal CCLKQ to the first corrected clock signal CCLKI by correcting a skew between the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ and duty errors of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ based on a relock signal RLK1, RLK2, or RLK3in a second operation mode during a normal operation.

The clock generation circuit600may generate the output clock signal OCLK and the strobe signal DQS based on the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ and may provide the output clock signal OCLK and the strobe signal DQS to the data I/O buffer320.

The control logic circuit210may control operations of the semiconductor memory device200. For example, the control logic circuit210may generate control signals for the semiconductor memory device200in order to perform a write operation or a read operation. The control logic circuit210includes a command decoder211that decodes the command CMD received from the memory controller100and a mode register212that sets an operation mode of the semiconductor memory device200.

For example, the command decoder211may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit210may generate the first control signal CTL1to control the ECC engine390, a second control signal CTL2to control the quadrature error correction circuit400and a third control signal CTL3to control the clock generation circuit600. The command decoder211, in response to the command CMD designating the relocking operation, may apply the relock signal RLK1to the quadrature error correction circuit400in the second operation mode. The command decoder211may apply the relock signal RLK1to the quadrature error correction circuit400periodically or non-periodically in the second operation mode.

The duty cycle monitor680may monitor duty cycles of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ in the second operation mode and may provide the relock signal RLK2to the quadrature error correction circuit400based on a result of the monitoring. The duty cycle monitor680may apply the relock signal RLK2to the quadrature error correction circuit400periodically or non-periodically in the second operation mode.

The quadrature error correction circuit400may perform the locking operation based on the second control signal CTL2in the first operation mode and may perform the relocking operation based on the relock signals RLK1and RLK2.

FIG.3illustrates an example of the first bank array310in the semiconductor memory device ofFIG.2.

Referring toFIG.3, the first bank array310includes a plurality of word-lines WL1˜WLm (m is a natural number greater than two), a plurality of bit-lines BTL1˜BTLn (n is a natural number greater than two), and a plurality of memory cells MCs disposed at intersections between the word-lines WL1˜WLm and the bit-lines BTL1˜BTLn. Each of the memory cells MCs includes a cell transistor coupled to each of the word-lines WL1˜WLm and each of the bit-lines BTL1˜BTLn and a cell capacitor coupled to the cell transistor.

The word-lines WL1˜WLm coupled to the plurality of memory cells MCs may be referred to as rows of the first bank array310and the bit-lines BTL1˜BTLn coupled to the plurality of memory cells MCs may be referred to as columns of the first bank array310.

FIG.4is a block diagram illustrating an example of the data clock buffer235in the semiconductor memory device ofFIG.2according to example embodiments.

Referring toFIG.4, the data clock buffer235may include a current mode logic (CML) driver237and a CIVIL to complementary metal-oxide semiconductor (CMOS) level (C2C) converter239.

The CML driver237may drive the data clock signal WCK, which includes differential clock signal pair WCK_t and WCK_c having a CML level, to generate internal clock signals CKI, CKQ, CKIB and CKQB which have a phase difference of 90 degrees with respect to one another. The C2C converter239may generate, based on the internal clock signals CKI, CKQ, CKIB and CKQB, the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB which have a phase difference of 90 degrees with respect to one another, and which also have a CMOS level. The C2C converter239may provide first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB to the quadrature error correction circuit400inFIG.2.

FIG.5illustrates an example of the data I/O buffer320in the semiconductor memory device ofFIG.2according to example embodiments.

Referring toFIG.5, the data I/O buffer320may include a data input circuit330and a data output circuit340. The data output circuit340may include a balanced multiplexer350, an output driver360and a strobe (DQS) driver370.

The data input circuit330may receive the data signal DQ from the memory controller100, may convert the data signal DQ to the data DTA, and may provide the data DTA to the ECC engine390. The data output circuit340may convert data DTA from the ECC engine390to the data signal DQ and provide the data signal DQ to the memory controller30.

The balanced multiplexer350may receive the data DTA and the output clock signal OCLK, may generate a pull-up driving signal PUDS and a pull-down driving signal PDDS based on the data DTA and the output clock signal OCLK, and may provide the pull-up driving signal PUDS and the pull-down driving signal PDDS to the output driver360. The balanced multiplexer350may generate the pull-up driving signal PUDS and the pull-down driving signal PDDS by sampling the data DTA based on the output clock signal OCLK. The output clock signal OCLK may include first through fourth output clock signals pairs OCLK1and OCLKB1, OCLK2and OCLKB2, OCLK3and OCLKB3and OCLK4and OCLKB4. Each of the first through fourth output clock signals pairs OCLK1and OCLKB1, OCLK2and OCLKB2, OCLK3and OCLKB3and OCLK4and OCLKB4may have a phase difference of 180 degrees with respect to each other.

For example, when the data DTA is at a high level, the balanced multiplexer350may generate the pull-up driving signal PUDS and the pull-down driving signal PDDS for turning off all transistors included in a pull-down driver (such as a pull-down driver363shown inFIG.6) of the output driver360. Contrarily, when the data DTA is at a low level, the balanced multiplexer350may generate the pull-down driving signal PDDS and the pull-up driving signal PUDS for turning off all transistors included in a pull-up driver (such as a pull-up driver361shown inFIG.6) of the output driver360.

FIG.6illustrates a circuit diagram of an output driver360in the data I/O buffer inFIG.5according to example embodiments.

Referring toFIG.6, the output driver360may include the pull-up driver361and the pull-down driver363.

The pull-up driver361may include first through r-th (r is a natural number greater than one) pull-up transistors NU1through NUr connected between the power supply voltage VDDQ and an output node ON1. Each of the first through r-th pull-up transistors NU1through NUr may be an n-channel metal oxide semiconductor (NMOS) transistor. The pull-down driver363may include first through r-th pull-down transistors ND1through NDr connected between the output node ON1and a ground voltage VSS. Each of the first through r-th pull-down transistors ND1through NDr may be an NMOS transistor.

When the data DTA is at the high level, the pull-up driver361may receive the pull-up driving signal PUDS (e.g., PUDS[1] through PUDS[r]) corresponding to a pull-up control code PUCD from the balanced multiplexer350and may generate the current determined by the pull-up control code PUCD. The pull-down transistors ND1through NDr included in the pull-down driver363may all be turned off according to the pull-down driving signal PDDS (e.g., PDDS[1] through PDDS[r]).

At this time, when the data DTA is at the high level, the current generated by the pull-up driver361may be transmitted to an on-die termination (ODT) resistor RODT_MC in the memory controller100via the data I/O (or DQ) pad301. The data signal DQ that the ODT resistor RODT_MC receives is determined by the current generated by the pull-up driver361and the ODT resistor RODT_MC.

When the data DTA is at the low level, the pull-up transistors NU1through NUr included in the pull-up driver361may all be turned off according to the pull-up driving signal PUDS. The pull-down driver363may receive the pull-down driving signal PDDS corresponding to the pull-down control code PDCD from the balanced multiplexer350and may have a resistance determined by the pull-down control code PDCD.

At this time, when the data DTA is at the low level, no current is generated by the pull-up driver361, and therefore, the data signal DQ that the ODT resistor RODT_MC receives has an output low level voltage (VOL) voltage which is substantially the same as the ground voltage VSS.

According to example embodiments, the total resistance, e.g., a termination resistance (RTT), of the pull-up driver361or the pull-down driver363may be changed in response to a particular pull-up or pull-down driving signal PUDS or PDDS.

FIG.7is a block diagram illustrating an example of the quadrature error correction circuit400in the semiconductor memory device ofFIG.2according to example embodiments.

Referring toFIG.7, the quadrature error correction circuit400may include a delay circuit410, a clock selector430, a first multiplexer (MUX1)470a, a second multiplexer (MUX2)470b, a phase interpolator (PI)500, a phase detector (PD)480, a digital loop filter490and a delay control circuit491.

The delay control circuit491may include a first delay controller DCON1493, a second delay controller DCON2494, a third delay controller DCON3495and a fourth delay controller DCON4496.

The delay circuit410may receive the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB and may generate first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB by adjusting delays of (or delaying) the second through fourth clock signals CLKQ, CLKIB and CLKQB based on the first clock signal CLKI, a first control code set DCC1, a second control code set DCC2, and a third control code set DCC3.

The delay circuit410may include a first delay line (DL1)410a, a second delay line (DL2)410b, a third delay line (DL3)410cand a fourth delay line (DL4)410d.

The first delay line410amay output the first adjusted clock signal ACLKI by delaying the first clock signal CLKI by a fixed delay amount. The second delay line410bmay output the second adjusted clock signal ACLKQ by delaying the second clock signal CLKQ based on the first control code set DCC1. The third delay line410cmay output the third adjusted clock signal ACLKIB by delaying the third clock signal CLKIB based on the second control code set DCC2. The fourth delay line410dmay output the fourth adjusted clock signal ACLKQB by delaying the fourth clock signal CLKQB based on the third control code set DCC3.

The clock selector430may select two of the first through fourth adjusted clock signals as the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ based on a fourth selection signal SS4, and may provide the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ to the clock generation circuit600inFIG.2. The selected two of the first through fourth adjusted clock signals may have a phase difference of 90 degree.

The first multiplexer470amay receive the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB and may select a first one of the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB as a first selected clock signal SCLK1based on a first selection signal SS1. The second multiplexer470bmay receive the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB and may select a second one of the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB as a second selected clock signal SCLK2based on a second selection signal SS2. The second one may have a phase lead of 90 degrees with respect to the first selected clock signal SCLK1.

For example, when the first multiplexer470aselects the second adjusted clock signal ACLKQ as the first selected clock signal SCLK1, the second multiplexer470bmay select the first adjusted clock signal ACLKI as the second selected clock signal SCLK2.

The phase interpolator500may generate a delayed selected clock signal SCLKD2by delaying the second selected clock signal SCLK2based on a fourth control code set CDCC and FDCC. The phase interpolator500may generate the delayed selected clock signal SCLKD2by delaying a phase of the second selected clock signal SCLK2by 90 degrees. The fourth control code set CDCC and FDCC may include a first sub control code set CDCC and a second sub control code set FDCC.

The phase detector480may detect a phase difference between the first selected clock signal SCLK1and the delayed selected clock signal SCLKD2, and may generate an up/down signal UP/DN based on the detected phase difference and may provide the up/down signal UP/DN to the digital loop filter490.

For example, when the first multiplexer470aselects the second adjusted clock signal ACLKQ as the first selected clock signal SCLK1, the second multiplexer470bmay select the first adjusted clock signal ACLKI as the second selected clock signal SCLK2and a skew and a duty error do not occur between the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ, a phase of the delayed selected clock signal SCLKD2may be the same as a phase of the second adjusted clock signal ACLKQ. When the phase of the delayed selected clock signal SCLKD2is not the same as the phase of the second adjusted clock signal ACLKQ, at least one of the skew and the duty error occurs between the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ.

The phase detector480, in the second operation mode, may generate a relock signal RLK3based on a phase difference between the first selected clock signal SCLK1and the delayed selected clock signal SCLKD2and may apply the relock signal RLK3to the delay control circuit491.

The digital loop filter490may filter the up/down signal UP/DN and in response to a third selection signal SS3, may provide the filtered up/down signal to the fourth delay controller496and one of the first through third delay controllers493,494and495, which is associated with the first selected clock signal SCLK1. In this case, the associated one is the first delay controller493.

The first delay controller493may adjust code values of the first control code set DCC1based on the up/down signal UP/DN to provide the first control code set DCC1to the second delay line410b. The second delay line410bmay generate the second adjusted clock signal ACLKQ by adjusting the delay of the second clock signal CLKQ based on the first control code set DCC1.

The first multiplexer470aselects the first adjusted clock signal ACLKI as the first selected clock signal SCLK1in response to the first selection signal SS1, the second multiplexer470bselects the fourth adjusted clock signal ACLKQB as the second selected clock signal SCLK2, the third delay controller495may adjust code values of the third control code set DCC3based on the up/down signal UP/DN to provide the third control code set DCC3to the fourth delay line410d.

While these processes are repeated, the delay circuit410may output the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB by adjusting delays of the second through fourth clock signals CLKQ, CLKIB and CLKQB with respect to the first clock signal CLKI.

The delay control circuit491may adjust code values of the first through fourth control codes DCC1, DCC2, DCC3and CDCC and FDCC in response to the relock signal RLK in the second operation mode and may provide the first through fourth control codes DCC1, DCC2, DCC3and CDCC and FDCC to the delay circuit410and the phase interpolator500.

In example embodiments, a binary to thermometer (i.e., unary) code converter may be disposed between the delay control circuit491and the duty cycle adjusting circuit410. The binary to thermometer code converter may convert the first through third control code sets DCC1, DCC2and DCC3to thermometer codes to provide the thermometer codes to the delay circuit410.

The first selection signal SS1, the second selection signal SS2, the third selection signal SS3and the fourth selection signal SS4may be included in the second control signal CTL2inFIG.2.

FIG.8Ais a circuit diagram illustrating an example of the second delay line410bin the quadrature error correction circuit400ofFIG.7according to example embodiments.

Referring toFIG.8A, the second delay line410bmay include a plurality of inverters411,412,413and414and a plurality of unit cells UC11, UC12, UC13and UC14.

The plurality of inverters411,412,413and414are cascaded-connected, and invert the second clock signal CLKQ four times to output the second adjusted clock signal ACLKQ.

The plurality of unit cells UC11, UC12, UC13and UC14are cascaded-connected between the inverters412and413, and may adjust a delay amount of an output of the inverter412. The unit cell UC11may include a p-channel metal-oxide semiconductor (PMOS) transistor421connected between a power supply voltage VDD and a node N11and a n-channel metal-oxide semiconductor (NMOS) transistor422connected between the node N11and a ground voltage VSS. The unit cell UC12may include a PMOS transistor423connected between the power supply voltage VDD and the node N11and an NMOS transistor424connected between the node N11and the ground voltage VSS. The unit cell UC13may include a PMOS transistor425connected between the power supply voltage VDD and the node N11and an NMOS transistor426connected between the node N11and the ground voltage VSS. The unit cell UC14may include a PMOS transistor427connected between the power supply voltage VDD and the node N11and an NMOS transistor428connected between the node N11and the ground voltage VSS.

Each gate of the PMOS transistors421,423,425and427and each gate of the NMOS transistors422,424,426and428may receive respective one of bits of the first control code set DCC1.

Each configuration of the first delay line410a, the third delay line410cand the fourth delay line410dinFIG.7may be similar with a configuration of the second delay line410binFIG.8A.

FIG.8Billustrates an example operation of delay circuit410in the quadrature error correction circuit400ofFIG.7according to example embodiments.

Referring toFIGS.7and8B, the delay circuit410may adjust delay of the second clock signal CLKQ with respect to the first clock signal CLKI based on the first control code set DCC1as a reference numeral406indicates.

FIG.9is a circuit diagram illustrating an example of the first multiplexer470ain the quadrature error correction circuit400ofFIG.7according to example embodiments.

Referring toFIG.9, the first multiplexer470amay include first through fourth transmission gates TG1, TG2, TG3and TG4and an NMOS transistor473. The first through fourth transmission gates TG1, TG2, TG3and TG4may be connected to a node N21in parallel with respect to each other, may receive the first adjusted clock signal ACLKI, the third adjusted clock signal ACLKIB, the second adjusted clock signal ACLKQ and the fourth adjusted clock signal ACLKQB respectively, and may be selectively turned-on in response to selection bits SS11and SS11b, SS12and SS12b, SS13and SS13B and SS14and SS14B of the first selection signal SS1respectively to provide one of the first adjusted clock signal ACLKI, the third adjusted clock signal ACLKIB, the second adjusted clock signal ACLKQ and the fourth adjusted clock signal ACLKQB as the first selected clock signal SCLK1. The NMOS transistor473may be connected between the node N21and the ground voltage VSS and may have a gate coupled to the ground voltage VSS.

A configuration of the second multiplexer470binFIG.7may be substantially the same as a configuration of the first multiplexer470aofFIG.9.

FIG.10is a circuit diagram illustrating an example of the phase detector480in the quadrature error correction circuit400ofFIG.7according to example embodiments.

Referring toFIG.10, the phase detector480may include a first flip-flop481, a second flip-flop482, an AND gate483, a relock signal (RLK) generator484and a lock flag generator485.

The first flip-flop481may be synchronized with the first selected clock signal SCLK1. Similarly, the second flip-flop482may be synchronized with the delayed selected clock signal SCLKD2. A data input D of each of the first and second flip-flops481and482may be connected to the power supply voltage VDD. That is, the data input D may be connected to a logic “1”. The first flip-flop481may output an output Q as logic “1” at a rising edge of the first selected clock signal SCLK1. Similarly, the second flip-flop482may output an output Q as logic “1” at a rising edge of the delayed selected clock signal SCLKD2. The output Q of the first flip-flop481may become a first up signal UP and the output Q of the second flip-flop482may become a first down signal DN.

The AND gate483performs an AND operation on the output Q of the first flip-flop481and the output Q of the second flip-flop482and may output a reset signal RST. The reset signal RST may be provided to the first and second flip-flops481and482.

When a phase of the first selected clock signal SCLK1is earlier than a phase of the delayed selected clock signal SCLKD2, the first up signal UP may become logic “1” from the rising edge of the first selected clock signal SCLK1and may become logic “0” from the rising edge of the delayed selected clock signal SCLKD2. Similarly, when a phase of the delayed selected clock signal SCLKD2is earlier than a phase of the first selected clock signal SCLK1, the first down signal DN may become logic “1” from the rising edge of the delayed selected clock signal SCLKD2and may become logic “0” from the rising edge of the first selected clock signal SCLK1.

The relock signal generator484may provide the delay control circuit481with the relock signal RLK3based on the up/down signal UP/DN when a phase difference between the first selected clock signal SCLK1and the delayed selected clock signal SCLKD2is equal to or greater than a reference value.

The lock flag generator485, based on the up/down signal UP/DN may generate a lock flag LFG with a low level in response to the phase difference between the first selected clock signal SCLK1and the delayed selected clock signal SCLKD2being equal to or greater than the reference value, and generate the lock flag LFG with a low level in response to the phase difference between the first selected clock signal SCLK1and the delayed selected clock signal SCLKD2being smaller than the reference value.

FIG.11is a block diagram illustrating an example of the phase interpolator500in the quadrature error correction circuit400ofFIG.7according to example embodiments.

Referring toFIG.11, the phase interpolator500may include a coarse delay line510and a fine delay line550.

Hereinafter, the coarse delay line510will be referred to as a first delay circuit and the fine delay line550will be referred to as a second delay circuit.

The first delay circuit510may delay the second selected clock signal SCLK2based on a first sub control code set CDCC to generate a first delayed clock signal CLKF and a second delayed clock signal CLKS. The second delay circuit550may interpolate phases of the first delayed clock CLKF signal and the second delayed clock signal CLKS based on a second sub control code set FDCC to generate the delayed selected clock signal SCLKD2. A phase of the delayed selected clock signal SCLKD2may be delayed by 90 degrees with respect to the second selected clock signal SCLK2.

FIG.12is a block diagram illustrating an example of the first delay circuit510in the phase interpolator500ofFIG.11according to example embodiments.

Referring toFIG.12, the first delay circuit510may include a plurality of cascade-connected delay cells (DC1, DC2, . . . , DCk)520a,520b, . . . ,520k(k is a natural number equal to or greater than three). The plurality of cascade-connected delay cells520a,520b, . . . ,520kmay be referred to as first through k-th delay cells.

The plurality of delay cells520a,520b, . . . ,520kmay delay the second selected clock signal SCLK2based on the first sub control code set to output the first delayed clock signal CLKF and the second delayed clock signal CLKS having a fixed delay amount.

The first delay cell520amay receive a first control code CDCC1. The second delay cell520bmay receive a second control code CDCC2. The k-th delay cell520kmay receive a k-th control code CDCCk.

FIG.13is a circuit diagram illustrating an example of the first delay cell520aof the plurality of delay cells inFIG.12according to example embodiments.

Each of the delay cells520b, . . . ,520kmay have the same configuration as a configuration of the first delay cell520a. That is, the plurality of delay cells520a,520b, . . . ,520kmay have the same configuration with respect to one another.

Referring toFIG.13, the first delay cell520amay include a plurality of NAND gates521˜528.

The NAND gate521performs a NAND operation on the second selected clock signal SCLK2and a first control bit CDCC11. The NAND gate522performs a NAND operation on an output of the NAND gate521and second control bit CDCC12. The NAND gate523performs a NAND operation on the output of the NAND gate521and a third control bit CDCC13. The NAND gate525performs a NAND operation on a transfer signal TS11from the second delay cell520band a fifth control bit CDCC15. The NAND gate524performs a NAND operation on the output of the NAND gate523and an output of the NAND gate525to output the first delayed clock signal CLKF.

The NAND gate526performs a NAND operation on the output of the NAND gate522and a fourth control bit CDCC14. The NAND gate527performs a NAND operation on a transfer signal TS12from the second delay cell520band the output of the NAND gate526. The NAND gate528performs a NAND operation on the output of the NAND gate527and a sixth control bit CDCC16to output the second delayed clock signal CLKS.

The second through fifth control bits CDCC12, CDCC13, CDCC14and CDCC15may determine delay amounts of the first delayed clock signal CLKF and the second delayed clock signal CLKS. The second delayed clock signal CLKS may be delayed by a delay amount corresponding to two NAND gates with respect to the first delayed clock signal CLKF.

FIG.14is a block diagram illustrating an example of the second delay circuit550in the phase interpolator500ofFIG.11according to example embodiments.

Referring toFIG.14, the second delay circuit550may include a delayed clock signal generator550aand a phase interpolator block560.

The delayed clock signal generator550amay delay the first delayed clock signal CLKF and the second delayed clock signal CLKS to generate first through third sub delayed clock signals CLKFD, CLKFS and CLKSD. The phase interpolator block560may finely adjust delay amounts of the first through third sub delayed clock signals CLKFD, CLKFS and CLKSD based on the second control code set FDCC to output the first delayed output clock signal CLKD1. The phase interpolator block560may divide each phase of the first through third sub delayed clock signals CLKFD, CLKFS and CLKSD, and may interpolate the divided phases to output the delayed selected clock signal SCLKD2, in response to the second sub control code set FDCC.

FIG.15is a block diagram illustrating an example of the delayed clock signal generator550ain the second delay circuit550ofFIG.14according to example embodiments.

Referring toFIG.15, the delayed clock signal generator550amay include a plurality of inverters551˜559.

Each of the inverters551,552and553inverts the first delayed clock signal CLKF. Each of the inverters554,555and556inverts the second delayed clock signal CLKS. The inverter557inverts outputs of the551and552to output the first sub delayed clock signal CLKFD. The inverter558inverts outputs of the553and554to output the second sub delayed clock signal CLKFS. The inverter559inverts outputs of the555and556to output the third sub delayed clock signal CLKSD.

Therefore, the first sub delayed clock signal CLKFD is delayed by a delay amount of two inverters with respect to the first delayed clock signal CLKF, the second sub delayed clock signal CLKFS is delayed by a delay amount correspond to sum of a delay amount of two inverters and a delay amount between the first delayed clock signal CLKK and the second delayed clock signal CLKS with respect to the first delayed clock signal CLKF, and the third sub delayed clock signal CLKDD is delayed by a delay amount of two inverters with respect to the second delayed clock signal CLKS.

FIG.16is a block diagram illustrating an example of the phase interpolator block560in the second delay circuit550ofFIG.14according to example embodiments.

Referring toFIG.16, the phase interpolator block560may include a plurality of phase interpolators560a,560b,560cand560dand an inverter569.

The phase interpolator560amay include PMOS transistors561a˜564aand NMOS transistors565a˜568a. The PMOS transistors561aand563aand the NMOS transistors565aand567aare cascade-connected between the power supply voltage VDD and the ground voltage VSS, and the PMOS transistors562aand564aand the NMOS transistors566aand568aare cascade-connected between the power supply voltage VDD and the ground voltage VSS.

Gates of the PMOS transistor561aand the NMOS transistor567areceive the first sub delayed clock signal CLKFD, gates of the PMOS transistor562aand the NMOS transistor568areceive the second sub delayed clock signal CLKFS, gates of the PMOS transistor563aand the NMOS transistor566areceive a second control bit FDCC2of the second sub control code set FDCC and gates of the PMOS transistor564aand the NMOS transistor565areceive a first control bit FDCC1of the second sub control code set FDCC. The PMOS transistor564aand the NMOS transistor566amay be connected to each other at a node N31.

A configuration of the phase interpolator560bmay be the same as a configuration of the phase interpolator560a.

The phase interpolator560cmay include PMOS transistors561c˜564cand NMOS transistors565c˜568c. The PMOS transistors561cand563cand the NMOS transistors565cand567care cascade-connected between the power supply voltage VDD and the ground voltage VSS, and the PMOS transistors562cand564cand the NMOS transistors566cand568care cascade-connected between the power supply voltage VDD and the ground voltage VSS.

Gates of the PMOS transistor561cand the NMOS transistor567creceive the third sub delayed clock signal CLKSD, gates of the PMOS transistor562cand the NMOS transistor568creceive the second sub delayed clock signal CLKFS, gates of the PMOS transistor563cand the NMOS transistor566creceive the second control bit FDCC2of the second sub control code set FDCC and gates of the PMOS transistor564cand the NMOS transistor565creceive the first control bit FDCC1of the second sub control code set FDCC. The PMOS transistor564cand the NMOS transistor566cmay be connected to each other at a node N32.

A configuration of the phase interpolator560dmay be the same as a configuration of the phase interpolator560c.

The node N31and the node N32are coupled to each other, and the inverter569averages voltage levels of the node N31and the node N32to output the delayed selected clock signal SCLKD2.

FIG.17is a block diagram illustrating an example of the clock generation circuit600in the semiconductor memory device200ofFIG.2according to example embodiments.

Referring toFIG.17, the clock generation circuit600may include a first phase splitter610, a second phase splitter615, a strobe signal (DQS) generator605and first through fourth clock multiplexers620,650,655and660.

The first phase splitter610may split a phase of the first corrected clock signal CCLKI to output a first adjusted clock signal ACLKI and a third adjusted clock signal ACLKIB having a phase difference of 180 degrees with respect to each other. The second phase splitter615may split a phase of the second corrected clock signal CCLKQ to output a second adjusted clock signal ACLKQ and a fourth adjusted clock signal ACLKQB having a phase difference of 180 degrees with respect to each other. The strobe signal generator605may generate the strobe signal DQS based on the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB.

Each of the first through fourth clock multiplexers620,650,655and660may receive the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB and may generate the first through fourth output clock signal pairs OCLK1and OCLKB1, OCLK2and OCLKB2, OCLK3and OCLKB3and OCLK4and OCLKB4by combining the first through fourth adjusted clock signals ACLKI, ACLKQ, ACLKIB and ACLKQB.

FIG.18illustrates operation states of the quadrature error correction circuit400according to example embodiments.

Referring toFIGS.7and18, in a first operation mode corresponding to the initialization operation, the quadrature error correction circuit400may perform the locking operation QEC LOCKING to store code values of the control code sets in each of the first through fourth delay controllers493,494,495and496.

After the initialization operation is completed, the quadrature error correction circuit400may be in a standby state. When the access operation is performed on the semiconductor memory device400, the quadrature error correction circuit400may perform relocking operation QEC RELOCKING in the second operation mode to update code values of each of the control code sets and may store the updated code values of each of the control code sets in each of the first through fourth delay controllers493,494,495and496.

When the quadrature error correction circuit400performs the relocking operation, the quadrature error correction circuit400may perform the relocking operation based on the code values stored in the first operation mode.

FIG.19is a block diagram illustrating the first delay controller493inFIG.7according to example embodiments.

Each configuration of the second, third and fourth delay controllers494,495and496may have substantially the same configuration of the first delay controller493inFIG.19.

Referring toFIG.19, the first delay controller493may include a code generator493aand a code storage493b. The code generator493amay start an operation of generating the first control code set DCC1based on the up/down signal UP/DN depending on an initialization command INIT. The initialization command INIT may be a command received from the memory controller100for the initialization operation. The code generator493amay store the first control code set DCC1in the code storage493b.

FIG.20illustrates that the first delay controller493ofFIG.19generates the first control code set DCC1based on a binary search or a linear search.

Referring toFIGS.19and20, the code generator493amay generate the first control code set DCC1based on a binary search BS using a successive approximate register or a linear search LS and a delay amount of the second clock signal CLKQ is adjusted based on the first control code set DCC1. When the code generator493agenerates the first control code set DCC1based on the binary search BS, the code generator493amay select a most significant bit (MSB) from which the binary search is started.

FIG.20illustrates that the code generator493aperforms the binary search BS and the linear search BS and it is noted that the second clock signal CLKQ reaches a target duty of 50% faster when the code generator493aperforms the binary search BS than when the code generator493aperforms the linear search LS.

FIG.21illustrates the first delay controller493inFIG.7in a second operation mode.

Referring toFIG.21, when the relock signal RLK is applied to the first delay controller493, the code generator493amay generate the first control code set DCC1based on the up/down signal UP/DN. The code storage493bmay provide the code generator493awith a stored control code set S_DCC1therein in response to the relock signal RLK. The stored control code set S_DCC1may be a control code set generated in the first operation mode.

The code generator493amay generate the first control code set DCC1based on the stored control code set S_DCC1from the code storage493b. Since the control code set S_DCC1is a control code set generated in the locking operation, a difference between values of the first control code set DCC1to be newly generated in the relocking operation and code values of the provided control code set S_DCC1may not be large. Accordingly, in the case of using the provided control code set S_DCC1, the code generator493amay quickly perform the relocking operation. In addition, since a difference between values of the first control code set DCC1to be newly generated in the relocking operation and code values of the provided control code set S_DCC1is not large, the code generator493amay perform the relocking operation based on the linear search.

FIG.22illustrates an example operation of the code storage493binFIG.21.

Referring toFIGS.21and22, the code storage493bmay include a multiplexer493c. The multiplexer439cmay receive the relock signal RLK as a control input and may select one of first control code sets DCC1a, DCC1band DCC1cand may output the selected one as the provided control code set S_DCC1to the code generator493a.

FIG.23Ais a flowchart illustrating an operation of the quadrature error correction circuit400ofFIG.7according to example embodiments andFIG.23Bis a timing diagram illustrating an operation of the quadrature error correction circuit400ofFIG.7.

Referring toFIGS.1,2,7,23A and23B, the semiconductor memory device200may receive an initialization command from the memory controller100(operation S110) at a timing point t1and may perform an initialization operation until a timing point t2.

From the timing point t2and to a timing point t3, the quadrature error correction circuit400performs the locking operation to generate first code (operation S120) and stores the first code in each of the first through fourth delay controllers493,494,495and496(operation S130). A duty error occurs in the data clock signal WCK and the strobe signal DQS between the timing points t1and t2, and a duty error does not occur in the data clock signal WCK and the strobe signal DQS between timing points t3and t4. A duty error occurs in the data clock signal WCK and the strobe signal DQS between the timing points t4and t5due to change of operation environment of the semiconductor memory device200, the duty cycle monitor680or the duty cycle detector110detects a duty error and provides a relock signal RLK to the quadrature error correction circuit400(operation S140). During timing point t5and t6, the quadrature error correction circuit400performs relocking operation in response to the relock signal RLK to generate a second code (operation S150) and stores the second code in each of the first through fourth delay controllers493,494,495and496(operation S160). Therefore, a duty error does not occur in the data clock signal WCK and the strobe signal DQS after timing point t6.

The first code may refer to the first through fourth control code sets in the first operation mode and the second code may refer to the first through fourth control code sets in the second operation mode.

The locking flag LFG has a low level when the quadrature error correction circuit400performs the locking operation and the relocking operation and the locking flag LFG has a high level when the quadrature error correction circuit400completes the locking operation and the relocking operation such that the second corrected clock signal CCLKQ is locked to the first corrected clock signal CCLKI.

FIG.24illustrates the quadrature error correction circuit400ofFIG.7performs the relocking operation periodically.

Referring toFIG.24, the quadrature error correction circuit400may perform the locking operation QLO in the first operation mode corresponding to the initialization operation, and may perform the relocking operation QRLO periodically in response to the relock signal RLK that is periodically activated in the normal mode. Intervals INT11and INT12between the relock signal RLK may be the same with respect to each other.

FIG.25is a flow chart illustrating an operation of the quadrature error correction circuit400according to example embodiments.

Referring toFIGS.1,2,7and25, the semiconductor memory device200may receive an initial power-up signal (operation S210). The quadrature error correction circuit400performs the locking operation (operation S220) to generate the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB in a first operation mode corresponding to the initialization command. During a normal operation of the semiconductor memory device200, the duty cycle monitor680monitors a duty cycle of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ (operation S225) and determines whether a duty error of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ is greater than a reference value (for example, 5%) (operation S230).

When the duty error of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ is greater than a reference value (YES in operation S230), the duty cycle monitor680generates the relock signal RLK (operation S240) and the quadrature error correction circuit400performs the relocking operation to lock the second corrected clock signal CCLKQ to the first corrected clock signal CCLKI in response to the relock signal (operation S220). When the duty error of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ is not greater than a reference value (NO in operation S230), the semiconductor memory device200performs a normal operation (operation S250).

FIG.26is a block diagram illustrating the memory system20ofFIG.1according to example embodiments.

FIG.26illustrates components associated with the locking operation and the relocking operation.

Referring toFIG.26, the memory controller100may include a clock generator120, a transmitter125, a receiver130, the duty cycle detector110and a transmitter135.

The clock generator120may generate the data clock signal WCK and the transmitter125may transmit the data clock signal WCK to the semiconductor memory device200. The receiver130may receive the strobe signal DQS from the semiconductor memory device200. The duty cycle detector110may receive the strobe signal DQS from the receiver, may detect the duty cycle of the strobe signal DQS and may transmit, to the semiconductor memory device200, the command designating the relock operation through the transmitter135when the duty error of the strobe signal DQS is greater than a reference value.

The semiconductor memory device200may include the control logic circuit210, the data clock buffer235, the quadrature error correction circuit400, the clock generation circuit600, the duty cycle monitor680and a transmitter205.

The data clock buffer235may generate the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB based on the data clock signal WCK, and the quadrature error correction circuit400may perform the locking operation to generate the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals CLKI, CLKQ, CLKIB and CLKQB in a first operation mode.

The clock generation circuit600may generate the strobe signal DQS based on the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ and may transmit the strobe signal DQS to the memory controller100through the transmitter205.

The control logic circuit210may generate the relock signal RLK1based on the command CMD designating the relocking operation and may provide the relock signal RLK1to the quadrature error correction circuit400. The duty cycle monitor680may monitor duty cycles of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ during the normal mode and may provide the relock signal RLK2to the quadrature error correction circuit400in response to the duty error of the first corrected clock signal CCLKI and the second corrected clock signal CCLKQ being greater than a reference value.

The quadrature error correction circuit400may perform the relocking operation to lock the second corrected clock signal CCLKQ to the first corrected clock signal CCLKI in response to the relock signal RLK1or the relock signal RLK2. The quadrature error correction circuit400may also perform the relocking operation to lock the second corrected clock signal CCLKQ to the first corrected clock signal CCLKI in response to the relock signal RLK3which is generated in the quadrature error correction circuit400.

FIG.27is a block diagram illustrating a semiconductor memory device800according to example embodiments.

Referring toFIG.27, the semiconductor memory device800may include at least one buffer die810and a plurality of memory dies820-1to820-p(p is a natural number equal to or greater than three) providing a soft error analyzing and correcting function in a stacked chip structure.

The plurality of memory dies820-1to820-pare stacked on the buffer die810and convey data through a plurality of through silicon via (TSV) lines (e.g., L1, L2, . . . , Lp, and L10. . . Lq).

At least one of the memory dies820-1to820-pmay include a cell core821to store data and a cell core ECC engine823which generates transmission parity bits (i.e., transmission parity data) based on transmission data to be sent to the at least one buffer die810. The cell core821may include a plurality of memory cells having DRAM cell structure.

The buffer die810may include a via ECC engine812which corrects a transmission error using the transmission parity bits when a transmission error is detected from the transmission data received through the TSV lines and generates error-corrected data.

The buffer die810may further include a clock management unit (CMU)814and a data I/O buffer816. The CMU814may employ the quadrature error correction circuit400ofFIG.7and the clock generation circuit600ofFIG.17, may generate corrected clock signals whose phases are locked by performing a locking operation in a first operation mode and by performing a relocking operation based on the data clock signal WCK and may generate the output clock signal OCLK based on the corrected clock signals. The data I/O buffer816may generate the data signal DQ by sampling the data DTA from the via ECC engine812and may output the data signal DQ.

The semiconductor memory device800may be a stack chip type memory device or a stacked memory device which conveys data and control signals through the TSV lines. The TSV lines may be also called ‘through electrodes’.

The cell core ECC engine823may perform error correction on data which is outputted from the memory die820-pbefore the transmission data is sent.

A data TSV line group832which is formed at one memory die820-pmay include 128 TSV lines L1to Lp, and a parity TSV line group834may include 8 TSV lines L10to Lq. The TSV lines L1to Lp of the data TSV line group832and the parity TSV lines L10to Lq of the parity TSV line group834may be connected to micro bumps MCB which are correspondingly formed among the memory dies820-1to820-p.

The semiconductor memory device800may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host through a data bus B10. The buffer die810may be connected with the memory controller through the data bus B10.

According to example embodiments, as illustrated inFIG.27, the cell core ECC engine823may be included in the memory die and the via ECC engine812may be included in the buffer die. Accordingly, it may be possible to detect and correct soft data fail (or a soft error). The soft data fail may include a transmission error which is generated due to noise when data is transmitted through TSV lines.

FIG.28is a configuration diagram illustrating a semiconductor package900including stacked memory devices910according to example embodiments.

Referring toFIG.28, the semiconductor package900may include one or more stacked memory devices910and a graphic processing unit (GPU)920.

The stacked memory devices910and the GPU920may be mounted on an interposer930, and the interposer on which the stacked memory device910and the GPU920are mounted may be mounted on a package substrate940mounted on solder balls950.

The GPU920may correspond to a semiconductor device which may perform a memory control function, and for example, the GPU920may be implemented as an application processor (AP).

The stacked memory device910may be implemented in various forms, and the stacked memory device910may be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. The stacked memory device910may include a buffer die and a plurality of memory dies and the buffer die may include the above-mentioned quadrature error correction circuit400and a clock generation circuit600. Accordingly, the configuration of the stacked memory device910may be substantially the same as the configuration of the semiconductor memory device800.

The plurality of stacked memory devices910may be mounted on the interposer930, and the GPU920may communicate with the plurality of stacked memory devices910. For example, each of the stacked memory devices910and the GPU920may include a physical region, and communication may be performed between the stacked memory devices910and the GPU920through the physical regions. Meanwhile, when the stacked memory device910includes a direct access region, a test signal may be provided into the stacked memory device910through conductive means (e.g., solder balls950) mounted under package substrate940and the direct access region.

Aspects of the present inventive concept may be applied to systems using semiconductor memory devices that employ volatile memory cells and data clock signals. For example, aspects of the present inventive concept may be applied to systems such as be a smart phone, a navigation system, a notebook computer, a desk top computer and a game console that use the semiconductor memory device as a working memory.