Bipolar transistor structure having split collector region and method of making the same

A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

BACKGROUND

Technological advances in semiconductor integrated circuit (IC) materials, design, processing, and manufacturing have enabled ever-shrinking IC devices, where each generation has smaller and more complex circuits than the previous generation.

Bipolar transistors are used to selectively connect electrically separate devices in an integrated circuit. Performance of a bipolar transistor is measured using a turn-off time, a time period between the bipolar transistor receiving a turn off signal and the bipolar transistor becoming non-conductive. Performance of a bipolar transistor is also measured by a voltage drop across the bipolar transistor, which is determined, in some instance, by an on-state resistance.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting.

FIG. 1is a cross-sectional view of a bipolar transistor100having a split collector region150in accordance with one or more embodiments. Bipolar transistor100includes a substrate102. A deep n-well104is in substrate102. A field oxide110is over the deep n-well104and a gate140is partly overlying field oxide110. An emitter region130and split collector region150are on opposite sides of gate140. Emitter region130includes a pair of oppositely doped, i.e., one p-doped and one n-doped, regions132and134contained in a p-well106. Split collector region150includes a highly doped central region152surrounded by a lightly doped peripheral region154contained in an n-well108.

In some embodiments, bipolar transistor100is a lateral insulated gate bipolar transistor (LIGBT). In some embodiments, bipolar transistor100is a bipolar junction transistor (BJT) or another type of bipolar transistor.

In some embodiments, substrate102is a lightly doped substrate having a first type of conductivity. Bipolar transistor100is an n-type transistor, and thus, the substrate102includes a p-type silicon substrate (p-substrate) or an SOI (silicon on isolator) substrate. In some embodiments, bipolar transistor100is a p-type transistor and substrate102includes an n-type dopant (n-substrate) or an SOI (silicon on isolator) substrate. In some embodiments, substrate102is a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate102includes other semiconductors, such as germanium, silicon carbide, gallium arsenic, indium arsenide, and indium phosphide, in some embodiments. In some embodiments, substrate102includes an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide.

Deep n-well104is in substrate102. In some embodiments, deep n-well104is formed using an SOI wafer. In some embodiments, deep n-well104is formed using an implantation process. In some embodiments, deep n-well104is formed in substrate102using a doped epitaxial process. In some embodiments, the dopant is added during the epitaxial process. In some embodiments, the dopant is implanted following the epitaxial process. In some embodiments, the n-type dopants include arsenic, phosphorous or other suitable n-type dopants.

P-well106is in substrate102over deep n-well104. In some embodiments, p-well106is formed using an implantation process. In some embodiments, p-well is formed in substrate102using a doped epitaxial process. In some embodiments, the dopant is added during the epitaxial process. In some embodiments, the dopant is implanted following the epitaxial process. In some embodiments, the p-type dopants include boron, boron difluoride, gallium or other suitable p-type dopants.

N-well108is in substrate102above deep n-well104. In some embodiments, n-well108is formed using an implantation process. In some embodiments, p-well is formed in substrate102using a doped epitaxial process. In some embodiments, the dopant is added during the epitaxial process. In some embodiments, the dopant is implanted following the epitaxial process. In some embodiments, the n-type dopants include arsenic, phosphorous or other suitable n-type dopants. In some embodiments, a dopant species in n-well108is a same dopant species as in deep n-well104. In some embodiments, the dopant species in n-well108is different from the dopant species in deep n-well104.

Field oxide110is over a top surface of substrate102. In some embodiments, field oxide110includes a dielectric, such as silicon oxide, nitride, or other suitable insulating materials. In some embodiments, field oxide110is formed by a thermal oxide process. Substrate102is patterned to protect regions where field oxide110is undesirable and the substrate is subjected to a high temperature, for example, about 800 degrees Celsius, in the presence of oxygen.

Emitter region130is formed in a top surface of p-well106, across gate140from split collector region150. Emitter region130has two oppositely doped regions132and134, both formed in the top surface of p-well106. A first region132of emitter region130has a first type of conductivity. In some embodiments, the conductivity type of first region132is the same as that of substrate102. A second region134of emitter region130has a second type of conductivity, which is the same as deep n-well104. For example inFIG. 1, first region132includes p-type dopants such as boron, boron difluoride, gallium or other suitable p-type dopants. In some embodiments, a dopant species of first region132is a same dopant species as substrate102. In some embodiments, the dopant species of first region132is different from the dopant species of substrate102. Second region134includes n-type dopants, such as arsenic, phosphorous, or other suitable n-type dopants. In some embodiments, a dopant species of second region134is a same dopant species as deep n-well104. In some embodiments, the dopant species of second region134is different from the dopant species of deep n-well104. In some embodiments, first region132includes n-type dopants and second region134includes p-type dopants. In some embodiments, emitter region130is formed using ion implantation, diffusion, or another suitable formation method. A rapid thermal annealing (RTA) process is used to activate the implanted dopants, in some embodiments.

Gate140has a first portion overlying the p-well106and a second portion overlying field oxide110. In some embodiments, gate140includes a gate dielectric and a gate electrode formed on the gate dielectric. The gate dielectric includes a silicon oxide layer suitable for high voltage applications, in some embodiments. Alternatively, the gate dielectric includes a high-k dielectric material, silicon oxynitride, other suitable materials, or combinations thereof, in some embodiments. In some embodiments, the high-k material is selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, hafnium oxide, or combinations thereof. In some embodiments, the gate dielectric has a multilayer structure, such as one layer of silicon oxide and another layer of high-k material. In some embodiments, the gate dielectric is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or combinations thereof.

The gate electrode is disposed overlying the gate dielectric. In some embodiments, the gate electrode includes a doped or non-doped polycrystalline silicon (or polysilicon). Alternatively, the gate electrode layer include a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof, in some embodiments. In some embodiments, the gate electrode is formed by CVD, PVD, ALD, plating, or other processes. In some embodiments, the gate electrode has a multilayer structure and is formed in a multiple-step process.

Split collector region150is formed in a top surface of n-well108, across gate140from emitter region130. Split collector region150has highly doped central region152surrounded by lightly doped peripheral region154. Highly doped central region152has a same dopant type as lightly doped peripheral region154. For example inFIG. 1, highly doped central region152and lightly doped peripheral region154include p-type dopants such as boron, boron difluoride, gallium or other suitable p-type dopants. In some embodiments, a dopant species of highly doped central region152is a same dopant species as lightly doped peripheral region154. In some embodiments, the dopant species of highly doped central region152is different from the dopant species of lightly doped peripheral region154.

A dopant concentration in highly doped central region152is about 50 times to about 200 times greater than a dopant concentration in lightly doped peripheral region154. In some embodiments, the dopant concentration in highly doped central region152is about 100 times greater than the dopant concentration in lightly doped peripheral region154. In some embodiments, the dopant concentration of lightly doped peripheral region154ranges from about 5×1012ions/cm3to about 5×1013ions/cm3.

In some embodiments, emitter region130is formed using ion implantation, diffusion, or another suitable formation method. A rapid thermal annealing (RTA) process is used to activate the implanted dopants, in some embodiments.

FIG. 2is a cross-sectional view of split collector region150for a bipolar transistor in accordance with one or more embodiments. Split collector region150includes highly doped central portion152surrounded by lightly doped peripheral portion154. Split collector region150has a length L. In some embodiments, length L ranges from about 10 microns (μm) to about 30 μm. Highly doped central region152has a length X parallel to length L. In some embodiments, a ratio between length X and length L ranges from about 0.8 to about 0.9. Lightly doped peripheral region154has a same width on both sides of highly doped central region152. A length of lightly doped peripheral region154on each side of highly doped central region152is equal to (L−X)/2.

FIG. 3Ais a top view of a bipolar transistor100having a split collector region150in accordance with one or more embodiments. Bipolar transistor100includes emitter region130on a first side of gate140and split collector region150on a second side of the gate opposite the emitter region. Bipolar transistor100also includes contacts310electrically connected to emitter region130, gate140and split collector region150to connect the bipolar transistor to other devices in an integrated circuit.

FIG. 3Bis a top view of split collector region150for a bipolar transistor in accordance with one or more embodiments. Split collector region150includes highly doped central portion152surrounded by lightly doped peripheral portion154. Lightly doped peripheral portion154completely surrounds highly doped central portion152, and the highly doped central portion is centered in the lightly doped peripheral portion.

Split collector region150provides an advantage of a collector region having a uniform dopant concentration throughout. In comparison with a uniform dopant concentration collector region, split collector region150has a decreased turn-off time. A decrease in turn-off time means that when a signal applied to gate140indicates bipolar transistor100should transition from a conductive state to a non-conductive state, the transition occurs faster in structures which include split collector region150. Table I below indicates that a turn-off time for a bipolar transistor having a split collector region is approximately as must as 52% faster than a bipolar transistor having a uniform dopant concentration collector region. The decreased turn-off time is provided for different combinations of direct current voltage and current levels. By decreasing the turn-off time, power consumption of the bipolar transistor is decreased and artificial signal delays to other devices within a current connected to bipolar transistor100are able to be reduced, thereby increasing an overall speed of the circuit.

Decreasing an overall dopant concentration of a collector region would result in a decreased conductivity of the bipolar transistor in comparison with a bipolar transistor having a higher dopant concentration in the collector region. The decreased conductivity results in an increased resistance to charge transfer from the emitter region to the collector region. Increased resistance in turn increases power consumption by the bipolar transistor. Decreasing an overall size of collector region will also reduce turn-off time, but the bipolar transistor will suffer similar negative results as decreasing the dopant concentration. However, bipolar transistor100including split collector region150experiences a minor increase in resistance to charge transfer. In comparison with a bipolar transistor having a collector region having a uniform high dopant concentration, bipolar transistor exhibits merely a 15% increase in resistance. The significant decrease in turn-off time combined with the small increase in resistance, increases applicability of bipolar transistor100to a wide variety of circuits.

FIG. 4is flow chart of a method400of making a split collector region in accordance with one or more embodiments. Method400begins with operation402in which a first photoresist is patterned over a collector region of a bipolar transistor. The first photoresist is formed by a suitable process, such as spin-on coating, and then patterned to form a patterned photoresist feature by a proper lithography patterning method. In some embodiments, the pattern of the photoresist is developed by a dry etching process, a wet etching process or another suitable developing process. In some embodiments, a hard mask layer is formed between underneath the photoresist. The patterned photoresist layer is formed on the hard mask layer. The pattern of the photoresist layer is transferred to the hard mask layer. In some embodiments, the hard mask layer includes silicon nitride, silicon oxynitride, silicon carbide, and/or other suitable dielectric materials, and is formed using a method such as CVD or PVD.

In some embodiments, the first photoresist is patterned to define a lightly doped peripheral region, e.g., lightly doped peripheral region154(FIG. 1), of the collector region. In some embodiments, the lightly doped peripheral region has a length ranging from about 0.5 μm to about 3 μm. In some embodiments, the first photoresist is patterned to define a highly doped central region, e.g., highly doped central region152, of the collector region. In some embodiments, the highly doped peripheral region has a length ranging from about 8 μm to about 27 μm. In some embodiments, the first photoresist is patterned to define an entirety of the collector region, e.g., split collector region150. In some embodiments, the collector region has a length ranging from about 10 μm to about 30 μm.

Method400continues with operation404in which a first implant process is performed. In some embodiments, the first implant process includes an ion implantation process followed by an anneal process to active implanted dopants. In some embodiments, the implantation process implants p-type dopants, such as boron, boron difluoride, gallium or other suitable p-type dopants, into the bipolar transistor. In some embodiments, the implantation process implants n-type dopants, such as arsenic, phosphorous or other suitable n-type dopants, into the bipolar transistor.

In some embodiments where the first photoresist is patterned to define the lightly doped peripheral region or the entirety of the collector region, the implantation process implants a dopant concentration ranging from about 5×1012ions/cm3to about 5×1013ions/cm3. In some embodiments where the first photoresist is patterned to define the highly doped central region, the implantation process implants a dopant concentration ranging from about 5×1014ions/cm3to about 5×1015ions/cm3.

In some embodiments, the first photoresist is removed following the first implant process. In some embodiments, the first photoresist is removed using an ashing process, an etching process or another suitable removal process.

FIG. 5Ais a cross-sectional view of a split collector region550following operation404in accordance with one or more embodiments. Split collector region550is similar to split collector region150, similar elements have a same reference number increased by 400. In the embodiment ofFIG. 5A, a first photoresist560is patterned to define a lightly doped peripheral region554. In some embodiments, first photoresist560is patterned to define an entirety of split collector region550. In some embodiments, first photoresist560is patterned to define a highly doped central region552(FIG. 5B).

Method400continues with operation406in which a second photoresist is patterned over the collector region. The second photoresist is formed by a suitable process, such as spin-on coating, and then patterned to form a patterned photoresist feature by a proper lithography patterning method. In some embodiments, the second photoresist is formed using a same process as the first photoresist. In some embodiments, the second photoresist is formed using a different process from the first photoresist. In some embodiments, the pattern of the second photoresist is developed by a dry etching process, a wet etching process or another suitable developing process. In some embodiments, the second photoresist is developed using a same process as the first photoresist. In some embodiments, the second photoresist is developed using a different process from the first photoresist. In some embodiments, a hard mask layer is formed between underneath the second photoresist. The patterned second photoresist is formed on the hard mask layer. The pattern of the second photoresist layer is transferred to the hard mask layer. In some embodiments, the hard mask layer includes silicon nitride, silicon oxynitride, silicon carbide, and/or other suitable dielectric materials, and is formed using a method such as CVD or PVD.

In some embodiments, the second photoresist is patterned to define a lightly doped peripheral region, e.g., lightly doped peripheral region154(FIG. 1), of the collector region. In some embodiments, the lightly doped peripheral region has a length ranging from about 0.5 μm to about 3 μm. In some embodiments, the second photoresist is patterned to define a highly doped central region, e.g., highly doped central region152, of the collector region. In some embodiments, the highly doped peripheral region has a length ranging from about 8 μm to about 27 μm.

In some embodiments where the first photoresist defines the lightly doped peripheral region or the entirety of the collector region, the second photoresist defines the highly doped central region. In some embodiments where the first photoresist defines the highly doped central region, the second photoresist defines the lightly doped peripheral region.

Method400continues with operation408in which a second implant process is performed. In some embodiments, the second implant process includes an ion implantation process followed by an anneal process to active implanted dopants. In some embodiments, the second implantation process implants p-type dopants, such as boron, boron difluoride, gallium or other suitable p-type dopants, into the bipolar transistor. In some embodiments, the second implantation process implants n-type dopants, such as arsenic, phosphorous or other suitable n-type dopants, into the bipolar transistor.

In some embodiments where the second photoresist is patterned to define the lightly doped peripheral region, the implantation process implants a dopant concentration ranging from about 5×1012ions/cm3to about 5×1013ions/cm3. In some embodiments where the second photoresist is patterned to define the highly doped central region, the implantation process implants a dopant concentration ranging from about 5×1014ions/cm3to about 5×1015ions/cm3.

In some embodiments, the second photoresist is removed following the second implant process. In some embodiments, the second photoresist is removed using an ashing process, an etching process or another suitable removal process.

FIG. 5Bis a cross-sectional view of split collector region550following operation408in accordance with one or more embodiments. In the embodiment ofFIG. 5B, a second photoresist570is patterned to define highly doped central region552. In some embodiments, second photoresist570is patterned to define a lightly doped peripheral region554(FIG. 5A).

One of ordinary skill in the art would recognize that additional operations before or after the described operations of method400are used to form a functional bipolar transistor. One of ordinary skill in the art would also recognize that back end processes are also possible to provide connection between the bipolar transistor and other devices within a circuit.

The back end process include forming interconnect structures over the bipolar transistor. In some embodiments, the interconnect structure connects to an emitter region and the split collector region. In some embodiments, the interconnect structure connects to a gate structure.

In some embodiments, the interconnect structure includes an interlayer dielectric (ILD) and a multilayer interconnect (MLI) structure in a configuration such that the ILD separates and isolates each metal layer from other metal layers. In furtherance of the example, the MLI structure includes contacts, vias and metal lines formed on the substrate. In one example, the MLI structure may include conductive materials, such as aluminum, aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof, being referred to as aluminum interconnects. Aluminum interconnects may be formed by a process including physical vapor deposition (or sputtering), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques to form the aluminum interconnect may include photolithography processing and etching to pattern the conductive materials for vertical connection (via and contact) and horizontal connection (conductive line). Alternatively, a copper multilayer interconnect is used to form the metal patterns. The copper interconnect structure may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The copper interconnect may be formed by a technique including CVD, sputtering, plating, or other suitable processes.

The ILD material includes silicon oxide. Alternatively or additionally, the ILD includes a material having a low dielectric constant, such as a dielectric constant less than about 3.5. In one embodiment, the dielectric layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), polyimide, and/or other suitable materials. The dielectric layer may be formed by a technique including spin-on, CVD, or other suitable processes.

An aspect of this description relates to a bipolar transistor. The bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Another aspect of this description relates to a lateral insulation gate bipolar transistor (LIGBT). The LIGBT includes a substrate; a first well in the substrate, the first well having a first dopant type; and a second well in the substrate, the second well having a second dopant type opposite the first dopant type. The LIGBT further includes a field oxide over a top surface of the substrate; an emitter region in the second well; and a gate structure partially overlapping the field oxide. The LIGBT further includes a split collector region in the first well. The split collector region includes a highly doped central region having the second dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region.

Still another aspect of this description relates to a method of making a bipolar transistor. The method includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.