LCD with integrated switches for DC restore

An AC-coupled display driver circuit includes one or more DC-restore switches that are integrated within a liquid crystal display. A liquid crystal display system includes a coupling capacitor coupled at one end to a system input video signal, the coupling capacitor providing a display input video signal having a DC level offset. A liquid crystal display device coupled to another end of the coupling capacitor receives the first display input video signal at a video input for driving the display device. A switch integrated within the display device provides DC restore to the coupling capacitor.

BACKGROUND

Generally, liquid crystal displays (LCDs) do not work well with direct current (DC) voltages. A graph of transmission versus voltage of an LCD is shown inFIG. 1, showing high transmission with zero voltage and low transmission with either positive or negative voltage. To drive the LCD to black, a positive voltage cannot be placed on the LCD. A steady state DC voltage may damage the display by, for example, causing contaminants to plate one side or the other of the liquid crystal cell. To preserve zero (0) DC (DC restore) and prevent damage, generally the voltage applied to the LCD is flipped back and forth (alternated) between high-black, low-black, high-black, low-black.

There are different scenarios for preserving zero (0) DC, as shown in the series of succeeding frames ofFIGS. 2A–2D. One scenario uses column inversion as shown inFIG. 2A, where one frame is written with all the columns having alternating polarity, positive-negative, positive-negative. In the next frame all the columns are written negative-positive, negative-positive. In the succeeding frame, all the columns are again written positive-negative, positive-negative. As shown inFIG. 2B, frame inversion can be used where the first frame is written with all positives and the next frame is written with all negatives. The succeeding frame is again written with all positives. As shown inFIG. 2C, pixel inversion can be used which produces a checkerboard like effect in the first frame and an inverted effect in the second frame. In the third frame, the checkerboard like effect matches that of the first frame. Lastly, as shown inFIG. 2D, row inversion can be used where all the rows are alternating polarity, positive-negative, positive-negative. In the next frame all the rows are written negative-positive, negative-positive. In the third frame, the rows are again written positive-negative, negative-negative.

SUMMARY

Suitable DC-coupled display driver circuits require high supply voltages. Some AC-coupled display driver approaches have an advantage of being able to use lower voltage amplifiers. However, external switches required for DC restore in such systems still must handle higher voltages. Thus, there is a need for improvement in display systems that avoids both additional higher voltage processes and increased parts count.

The present invention provides a more desirable approach for AC-coupled display driver circuitry. For embodiments in accordance with the present approach, one or more DC-restore switches are integrated within a liquid crystal display. In this manner, the integrated switches can be implemented in the same high-voltage process used for the display's internal circuits. An advantage is that no external integrated circuit is needed for the DC-restore switches, and system input amplifiers can be integrated with other components on a low-voltage integrated circuit.

Accordingly, a liquid crystal display system includes a coupling capacitor coupled at one end to a system input video signal, the coupling capacitor providing a display input video signal having a DC level offset. A liquid crystal display device coupled to another end of the coupling capacitor receives the first display input video signal at a video input for driving the display device. A switch integrated within the display device provides DC restore to the coupling capacitor.

In another embodiment, a second coupling capacitor coupled at one end to the system input video signal provides a second display input video signal having a second DC level offset. The liquid crystal display device includes a second video input coupled to another end of the second coupling capacitor to receive the second display input video signal for driving the display device. A second switch integrated within the display device provides DC restore to the second coupling capacitor.

The integrated switches are operable to provide DC restore to the coupling capacitors when operated during a retrace interval of the system input video signal.

According to another aspect, a liquid crystal display system features a single system input video signal. An amplifier having switchable gain polarity coupled to the system input video signal provides an amplified system input video signal. A first coupling capacitor coupled at one end to the amplifier provides a first display input video signal having a first DC level offset. A second coupling capacitor coupled at one end to the amplifier provides a second display input video signal having a second DC level offset. A liquid crystal display device receives the first and second display input video signals for driving the display device. First and second switches provide DC restore to the first and second coupling capacitors, respectively. The first and second switches may be external to the display device or integrated into the display device.

DETAILED DESCRIPTION

FIG. 3Ashows a DC-coupled driver circuit10with two video signals, video high (VIDH) and video low (VIDL), coupled to a liquid crystal display device30. Generally, the signals VIDH and VIDL are complementary signals that drive an active matrix of pixel elements not shown for clarity. To alleviate the use of negative voltages, the signals are centered around 5 volts, which is the voltage applied to the common electrode (VCOM) of all pixels. Thus, 5 volts applied to the VIDH signal puts 0 volts across the pixel, driving it to the white state. When VIDH is 8 volts, the pixel voltage is +3 volts (black). VIDL ranges from 5 volts white to 2 volts black. The input video signal swing is typically 1 volt, therefore positive and negative amplifiers20are needed with matching gains of +3 and −3 volts.FIG. 3Bis a waveform diagram of video signals applied in the circuit10ofFIG. 3Ausing row inversion.

The system just discussed, with separate VIDH and VIDL signals (FIG. 3A), is well-suited for use with column and pixel inversion, because every row of the display contains pixels of both positive and negative polarity. (A representative display is disclosed in U.S. Pat. No. 6,476,784, which is incorporated herein by reference in its entirety.) Therefore, both amplifiers are in nearly continuous use. However, when row inversion or frame inversion drive is used, then all pixels of a given row are the same polarity, and the VIDH and VIDL signals cannot be used at the same time. One of the two amplifiers (+A or −A) will always be idle.

To avoid underutilized amplifiers in the situation just described, row inversion displays typically use a driver circuit such as that shown inFIG. 4A. In the circuit12, a single video signal (VID) is driven by a single amplifier22coupled to display32. The amplifier polarity is switched for positive or negative gain. When writing a row of positive pixels, VID swings from white to high black (as does VIDH inFIG. 3A). For a negative row, the opposite amplifier polarity is used so that VID swings from white to low black. The amplifier is fully utilized, but the VID signal swing (8−2=6V) is twice that of VIDH (8−5=3V) or VIDL (5−2=3V).FIG. 4Bis a waveform diagram of video signals applied in the circuit ofFIG. 4Ausing row inversion.

One widely-used technique for reducing the VID signal swing is to drive the common electrode VCOM with an AC signal. This AC-common drive scheme is shown in the waveform diagram ofFIG. 5. The VCOM level is reduced to 2 volts when writing positive rows, so that the +3V black level is written with VID at 5 volts. Negative rows drive VCOM to 5 volts, so that 3V black is written with VID at 2 volts. In both cases, the VID signal swing is only (5−2=3V). One disadvantage of AC-common drive is that it requires additional circuitry to switch the VCOM level. Another disadvantage is incompatibility with some pixel designs and scanner circuits.

In some cases, the required video bandwidth may be greater than can be practically supplied on a single VID signal or pair of VIDH and VIDL signals. Examples include higher resolution displays with a large number (>˜300 k) pixels, and displays intended to operate at unusually high frame rates (>˜60 Hz). These displays may use multiple VID inputs or pairs of VIDH and VIDL inputs to achieve the necessary bandwidth. Color displays may also use multiple video inputs for separate red, green, and blue component signals. For clarity, the following discussion continues to refer to single inputs or input pairs, but the ideas and techniques described may be readily scaled for displays with multiple inputs.

A disadvantage of the DC-coupled systems is their high supply voltage. If VCOM is held at a DC level, then at least one amplifier will require a supply exceeding the high black level of 8 volts. Even with AC-common drive, the maximum video voltage level of 5 volts is significantly greater than the actual 3-volt swing, because of the 2-volt minimum level imposed by the display's circuits. The high supply voltages increase the system power dissipation, and also limit the technologies available for implementing the video amplifiers. For example, an 8-volt video amplifier may require a relatively expensive BiCMOS process. A 5-volt amplifier may be implemented in a specialized analog CMOS process. A more desirable solution would be a rail-to-rail amplifier driving 3-volt video with a 3.3-volt supply and implemented in a conventional CMOS logic process. Such CMOS processes are widely available and relatively inexpensive. Moreover, the 3.3-volt CMOS solution may lead to higher integration, since the amplifier may be integrated on the same chip as other system components.

FIG. 6Ashows a circuit14with low-voltage amplifiers20and AC-coupled drive for column inversion. Capacitors CHand CLare used to shift the DC level. The outputs of both amplifier swing 0–3 volts on the left side of the capacitors, but on the right side of the capacitors the display30sees 5–8 volts on VIDH and 2–5 volts on VIDL. For proper operation, the voltage offsets across CHand CLmust be maintained at +5 and +2 volts, respectively. These offsets are periodically refreshed by driving the input video to black and closing DC-restore switches SWH2, SWL2. Upon operation of the switches SWH2, SWL2, the left plate of CHwill be at +3V and the right plate at +8V, resulting in the desired +5V offset. Similarly, capacitor CLwill be restored to a 2-volt offset. This refresh may be performed during the horizontal retrace time between rows, so it does not interfere with display operation.

FIG. 6Bshows a similar AC-coupled circuit16, but with both DC restore switches SWH1, SWL1connected to the 5-volt common level. The offset voltages across CHand CLare the same as inFIG. 6A, but in this case, the input signal is driven to white to perform the refresh.

Any convenient level may be used for this DC-restore technique: black, white, gray, or perhaps the sync level. One advantage of resetting to white is that a single +5V reference supply may be used for both switches. However, reset-to-black may be preferred when using standard video signals which already provide a black “blanking period” during horizontal retrace.

As mentioned previously, when row inversion is used then all pixels in a given row have the same polarity, and therefore only a single amplifier is needed.FIGS. 7Aand7C show AC-coupled circuits18and40, respectively, for use with row inversion in accordance with the principles of the present invention. As in the DC-coupled circuit ofFIG. 4A, the amplifier polarities in the circuits ofFIGS. 7A and 7Care switchable. However, in these AC-coupled embodiments the minimum and maximum signal levels are the same for both polarities. The two switches (SWH1, SWL1inFIG. 7A; SWH2, SWL2inFIG. 7C) are operated independently, and the VIDH and VIDL signals are reset at different times. The circuit ofFIG. 7Aresets to the white level. As shown in the waveform diagram ofFIG. 7B, capacitor CHis reset by closing SWH1to connect VIDH to +5V while the amplifier output is low (0V), and CLis reset by closing SWL1to connect VIDL to +5V while the amplifier output is high (3V). The circuit ofFIG. 7Cresets to the black levels. As shown in the waveform diagramFIG. 7D, capacitor CHis reset by closing SWH2to connect VIDH to +8V while the amplifier output is high (3V), and CLis reset by closing SWL2to connect VIDL to +2V while the amplifier output is low (0V).

One problem encountered with AC-coupled drive circuits described inFIGS. 6A,6B,7A and7C is that inputs in the display are not purely high impedance inputs. To illustrate this point,FIG. 8shows a video line VIDH/L switched through switches SW1–SW5to several capacitors C1–C5, representing the capacitive loads of all columns driven from that video line. The switches SW1–SW5represent transmission gates that switch video voltage onto column capacitance. As each transmission gate switch SW1–SW5is closed, a small charge is transferred from the column capacitance and an error signal accumulates on the external coupling capacitor. The error increases as the scan proceeds further across the display. Therefore, on one side of the image everything is correct but the gray scale values may be different on the opposite side of the image. The magnitude of the error will depend on how much charge was dumped off in the previously scanned portion of the image. This can lead to a horizontal bleeding effect.FIG. 9illustrates a display30A that includes an image area32having a gray image portion (B) and a black image portion (A). While scanning the black image portion (A), the area (AA) to the right is slightly a different shade of gray than the gray image above it. This is likely because a different charge was transferred onto the capacitors in that area. A solution is to make the capacitors larger so that they can absorb whatever charge is transferred. The same amount of charge on a larger capacitor results in a smaller error signal voltage, thereby preventing this bleeding effect. The AC-coupled drive approaches (FIGS. 6A,6B,7A and7C) permit the use of lower voltage amplifiers, because no signals on the left side of the capacitors exceed 3.3V. However, the DC-restore switches (SWH1, SWL1, SWH2, SWL2) are on the right side of the capacitors, and hence must handle higher voltages.

One might consider integrating the DC-restore switches and video amplifiers on the same chip, but then the chip would require a higher voltage process to implement the switches, and an important advantage of the AC-coupled drive might be lost. A second alternative is to implement the switches externally, with a separate chip, discrete MOSFETs, or similar devices, but this will increase the parts count and hence most probably the cost of the system.

FIGS. 10A–10Fshow several embodiments of a more desirable approach for AC-coupled drive circuitry in accordance with the present invention. With this approach, one or more DC-restore switches are integrated inside the LCD. Thus, no external IC is needed for the switches, and the amplifiers may be integrated with other components on a low-voltage integrated circuit. In addition, the switches can be implemented in the same high-voltage process used for the display's internal circuits.

In particular,FIGS. 10A–10Cillustrate embodiments of AC-coupled drive circuits that feature two display inputs and have two integrated switches that are independently operated.FIG. 10Aillustrates a circuit42that includes a display50with integrated switches ISWH1, ISWL1configured for DC restore while resetting the display to white.FIG. 10Bshows a circuit44that is similar to the display diagram ofFIG. 10Abut with integrated switches ISWH2, ISWL2configured for a 5 volt voltage shift at display52. The circuit46ofFIG. 10Cincludes integrated switches ISWH3, ISWL3that are configured for DC restore while resetting the display54to black.

FIGS. 10D–10Eillustrate AC-coupled drive circuits48,70that feature a single system input, a single display input, and integrated switching. The output voltage swing of amplifier22A is 6V, the same as in the DC-coupled case ofFIG. 4A. However, the maximum amplifier output voltage is reduced from 8V inFIG. 4Ato 6V inFIGS. 10D and 10E. The reduced output voltage may allow the amplifier22A to be operated at a lower supply voltage, thereby saving power. The circuit48ofFIG. 10Dhas a single integrated switch ISW1configured for DC restore with display56reset to white. The switch ISW1is closed periodically with the input video at the white level. The circuit70ofFIG. 10Eincludes two integrated switches ISWH4, ISWL4configured for DC restore with display58reset to black. One or both of the switches ISWH4and ISWL4may be used. The switches are operated independently, with ISWH4closed when the amplifier output is at the high black level (6V), and/or with ISWL4closed when the amplifier output is at the low black level (0V). If both switches are used, then the +8V and +2V references should be well matched to the limits of the amplifier output swing.

FIG. 10Fillustrates a display drive circuit72with AC-coupled video, an AC-common signal, and integrated switching. The VCOM signal levels are the same as in the DC-coupled case ofFIG. 5. The use of AC-coupled video reduces the maximum voltage level required at the amplifier output. DC restore is performed by closing switch ISW2integrated within display60while the input video signal is at the white level (1V).

FIG. 10Gillustrates a display drive circuit74with AC-coupled video, an AC-common signal, and integrated switching for both video and VCOM signals at display62. The video signal is reset to the white level by closing switch ISW3and connecting VID to VCOM. The VCOM level is restored by closing ISW4and connecting VCOM to a (+2V) reference level.

Note that the external switches (SWH1, SWL1, SWH2, SWL2) in the AC-coupled drive circuits ofFIGS. 7A and 7Ccan be integrated into the display in accordance with the principles of the present invention, as shown inFIGS. 10H and 10I, respectively.FIG. 10Hillustrates display driver circuit76with integrated switches ISWH5, ISWL5at display64.FIG. 10Iillustrates display driver circuit78with integrated switches ISWH6, ISWL6at display66.

It should be understood that in other embodiments in accordance with the principles of the present invention, there can be configurations in which there are no amplifiers. For example, in bi-level video systems (i.e., black and white, but no gray), the system input may be driven with switches but without an amplifier.

Operation of the integrated switches for the embodiments ofFIGS. 10A–10Gwill now be described.FIG. 11Ais a diagram of an NMOS switch80for use with a video high display input signal in any of the embodiments ofFIGS. 10A–10B. The diagram ofFIG. 11Ashows the NMOS switch coupled to display input signal VIDH and common voltage VCOM. In this case, VIDH>=VCOM. The switch is controlled by gate voltage VGH. The NMOS switch is gated off when (VGH−VCOM)<VTN, where VTN (˜1–2V) is the threshold voltage, and is therefore gated off when VGH=VCOM. The switch80is gated on when (VGH−VCOM)>VTN. To achieve adequate conductance, the switch needs to have VGH−VCOM−VTN=several volts (˜1–3V).

Similarly,FIG. 11Bis a diagram of a PMOS switch82for use with a video low display input signal in the embodiments ofFIGS. 10A–10B. The PMOS switch is shown coupled to display input signal VIDL and common voltage VCOM. In this instance, VIDL<=VCOM. The switch82is controlled by gate voltage VGL. The PMOS switch is gated off when (VGL−VCOM)>VTP, where VTP (˜−1 to −2V) is the threshold voltage, and is therefore gated off when VGL=VCOM. The switch is gated on when (VGL−VCOM−VTP)=several negative volts (˜−1 to −3V).

FIG. 11Cis a diagram of an NMOS switch84for use with a single video display input signal in the embodiments ofFIG. 10DorFIG. 10F. In this case, the switch is shown coupled to display input VID and common voltage VCOM, with VMAX>VCOM and VMIN<VCOM. The switch84is controlled by gate voltage VG. The switch is gated off when VG<VMIN+VTN, which will be less than VCOM+VTN. The switch is gated on when VG>VMAX+VTN.

FIG. 11Dis a diagram of a pair of NMOS and PMOS switches86,88for use with video high and video low input signals in the embodiment ofFIG. 10C. The NMOS switch88is shown coupled to display input VIDL and the low black reference level (+2V), and the PMOS switch86is shown coupled to the display input VIDH and the high black reference level (+8V). In this case VIDH is less than the high black reference (+8V), and VIDL is greater than the low black reference level (+2V). The PMOS switch is controlled by gate voltage VGH, and the NMOS switch is controlled by gate voltage VGL.FIG. 11Eis similar toFIG. 11Dwith switches90,92, but with a single video input as in the embodiment ofFIG. 10E.

It is noted that for single display input embodiments, there needs to be more voltage swing on VG than for the voltage swing on VGH. VGL in case of two display input embodiments. However, in either case, it is desirable in general to have a greater voltage swing available on VG, VGH, and VGL. It is generally known that for MOS circuits, the current ˜(W/L)(VGS−VT) in the linear region of operation, where VGS is the gate voltage and W and L are the width and length of the channel. Thus, by increasing VGS, a smaller FET can be used, thereby reducing size, power and cost. To provide for greater voltage swing at the gate voltage, a bootstrapping circuit approach can be implemented for the embodiments ofFIGS. 10A–10Gthat include integrated switches.

FIG. 12Ais a schematic circuit diagram of a bootstrapping circuit102for use with the embodiments ofFIGS. 10A–10B.FIG. 12Bis a waveform diagram of control signals for the bootstrapping circuit ofFIG. 12A.FIG. 13Ais a schematic circuit diagram of a bootstrapping circuit110for use with the embodiments ofFIG. 10DorFIG. 10F.FIG. 13Bis a waveform diagram of control signals for the bootstrapping circuit ofFIG. 13A.

The bootstrapping circuit102(FIG. 12A) includes switches104,106,108. The timing diagram ofFIG. 12Bbegins with gate voltage g held at the VCOM level, and the NMOS switch therefore open. Signal s* is then driven low to disconnect g from VCOM. Signal u* is then pulsed low, pulling gate Voltage g up toward VDD through diode D1. When signal p is then pulsed high, gate voltage g is capacitively coupled to a voltage higher than VDD, thereby increasing the switch conductance. The dual of circuitFIG. 12Amay be used to drive a PMOS switch.

The circuit110ofFIG. 13Aperforms a bootstrap function similar to that ofFIG. 12A, while also allowing the gate voltage g to be driven below VCOM, as is required for the embodiments ofFIG. 10DorFIG. 10F. Node g is driven by two inverters109,111which have their negative supplies connected to signal p. Signal y is an un-boosted input signal. The circuit configuration ensures that no transistor's drain-to-source voltage VDSexceeds (VDD−VSS), which may avoid transistor breakdown and improve circuit reliability.

FIG. 14is a schematic diagram of a charge injection cancellation circuit120for use with the integrated switches of the embodiments ofFIGS. 10A–10G. When switch transistor122of size (W/L) turns off, its channel charge is injected onto the source and drain nodes VCOM and VID. Assuming that each node receives half of the charge, the charge may be cancelled by a compensation transistor124of size ((W/2)/L). The gate of the cancellation circuit is driven by the inverse signal of the switch gate, so that the cancellation FET turns on soon after the switch transistor turns off.

An embodiment of an integrated circuit active matrix display200is shown schematically inFIG. 15. The circuit200includes data scanners202and204, select scanner206, active matrix pixel array208, a plurality of transmission gates210and212, control logic216, integrated switches217and219, level shift218, and power control220.

The integrated scanners drive the active matrix pixel array208. The pixel array208has a plurality of pixel elements214. The RGT input selects one of the two data scanners for left-to-right (202) or right-to-left (204) horizontal scanning. The select scanner206scans vertically from top to bottom. The data scanners202,204accept logic-level clock inputs directly from the input pads, thereby reducing the power dissipation and skew otherwise associated with internal clock drivers. Complementary video signals are accepted on the AC-coupled VIDH and VIDL inputs, with internal switches217and219, respectively, restoring DC levels during the horizontal retrace interval. The VIDH and VIDL signals carry video signals to the transmission gates210and212.