An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

BACKGROUND

The present disclosure relates to integrated circuits, and more specifically, to a non-planar silicided semiconductor electrical fuse.

Different parts of an integrated circuit (IC) may be coupled using an electrical fuse (e-fuse). E-fuses can be ‘programmed’ to change interconnections within the IC. More particularly, metal within the fuse link can be caused to migrate by application of a prescribed current controlled by a transistor. Once sufficient metal has migrated, the fuse link is open or blown, stopping current from passing through the fuse. One challenge presented by electrical fuses is that they occupy a large footprint in ICs due to the size of the fuse and the associated current source needed to program them. Electrical fuses also include a planar fuse link that has a large footprint. Typically, the size of the e-fuse is limited by the size of the gate conductors within a particular technology node. Accordingly, one approach to reduce the size of e-fuses includes reducing the fuse link size to the minimum gate conductor length allowed by a technology node.

SUMMARY

An aspect of the disclosure includes an electrical fuse (e-fuse), comprising: a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer is non-planar; a first terminal electrically coupled to a first end of the fuse link; and a second terminal electrically coupled to a second end of the fuse link.

An aspect of the disclosure related to an integrated circuit (IC), comprising: a bipolar transistor including an intrinsic base and an extrinsic base; a complementary metal-oxide semiconductor (CMOS) transistor; and an electrical fuse (e-fuse), including: a non-planar fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor, wherein the silicided semiconductor layer extends orthogonally over the gate conductor; a first terminal electrically coupled to a first end of the non-planar fuse link; and a second terminal electrically coupled to a second end of the non-planar fuse link, wherein the silicided semiconductor layer is a same layer as at least one of the intrinsic base and the extrinsic base of the bipolar transistor.

Another aspect of the disclosure is directed to a method, comprising: forming a semiconductor layer for at least one of an intrinsic base and an extrinsic base for a bipolar transistor, and over a dielectric layer over a gate conductor; patterning the semiconductor layer to extend orthogonally over the gate conductor; forming a fuse link for an electrical fuse by siliciding the semiconductor layer over the dielectric layer over the gate conductor, wherein the silicided semiconductor layer is non-planar over the gate conductor; and forming the electrical fuse by forming a first terminal electrically coupled to a first end of the fuse link, and a second terminal electrically coupled to a second end of the fuse link.

The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide an electrical fuse (e-fuse) that includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. Hence, the fuse link is electrically isolated from the gate conductor therebelow. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. The non-planar fuse link provides greater length in a smaller footprint compared to conventional planar e-fuses. Additionally, the length of the fuse link can be customized based on, for example, the height of the gate conductor and dielectric layer, how many gate conductors it passes over, and the number of times it passes over the gate conductor(s). A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The semiconductor fuse link may be conveniently formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor during bipolar complementary metal-oxide semiconductor (BiCMOS) fabrication, thus requiring no additional processing steps to build. The gate conductor may be part of a transistor that controls a current source for programming the e-fuse, which further reduces the footprint compared to conventional e-fuses by placing the control transistor at least partially under the fuse link. The e-fuse also requires less programming energy compared to conventional e-fuses.

FIGS.1and2show enlarged cross-sectional views of a method of forming parts of an IC102including an electrical fuse (e-fuse)100, according to embodiments of the disclosure. As illustrated, in one embodiment, IC102includes a bipolar transistor region110and a complimentary metal-oxide semiconductor (CMOS) transistor region112. E-fuse100will be built in CMOS transistor region112, but may be built simultaneously with parts of bipolar transistor region110. Alternatively, where IC102does not include bipolar transistor region110, e-fuse100may be built exclusively within a CMOS transistor region112. A substrate114upon which the regions are built may include any now known or later developed semiconductor substrate, e.g., a bulk substrate, or a semiconductor-on-insulator (SOI) substrate.

At this stage, bipolar transistor region110includes n-type or p-type implant region115to form the various parts of a bipolar transistor, like a collector in this example. As this structure and the methods of forming it are known in the art, no further description is warranted. CMOS transistor region112may include source/drain regions118formed in substrate114in any known fashion, e.g., implanting of any appropriate dopants. In one example, source regions118S for gate conductors116have drain region118D separated therefrom by respective channel regions (not numbered for clarity—under gate conductors116). Any necessary trench isolations119may also be provided and may be formed in any now known or later developed fashion, e.g., etching holes in substrate114prior to gate conductor116formation and filling with a dielectric such as oxide.

Etching generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases, which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as trench isolation trenches.

CMOS transistor region112includes a number of gate conductors116formed thereon. In the example shown inFIGS.1-4, two gate conductors116are illustrated. As will be described herein, more or less gate conductors116are also possible. In the example shown inFIGS.1-2, gate conductors116are in an active region of CMOS transistor region112, and thus are used as active gates. In this case, in one non-limiting example, gate conductor(s)116may include polysilicon. In another example, gate conductor(s)116may include a metal gate. Although shown as a single material for clarity, metal gates may include one or more conductive components for providing a gate terminal of a transistor. For example, metal gates may include a high dielectric constant (high-K) layer, a work function metal layer and a conductor layer (not all shown for clarity). The high-K layer may include any now known or later developed high-K material typically used for metal gates such as but not limited to: metal oxides such as tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3) or metal silicates such as hafnium silicate oxide (HfA1SiA2OA3) or hafnium silicate oxynitride (HfA1SiA2OA3NA4), where A1, A2, A3, and A4 represent relative proportions, each greater than or equal to zero and A1+A2+A3+A4 (1being the total relative mole quantity). The work function metal layer may include various metals depending on whether for an NFET or PFET device, but may include, for example: aluminum (A1), zinc (Zn), indium (In), copper (Cu), indium copper (InCu), tin (Sn), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), TiAlC, TiAl, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), polycrystalline silicon (poly-Si), and/or combinations thereof. The conductor layer may include any now known or later developed gate conductor such as copper (Cu). A gate cap (not shown) of, for example, a nitride may also be formed over the gate region. Gate conductor116may also include a spacer (not shown) thereabout, e.g., of silicon nitride. Gate conductor116may be formed using any now known or later developed IC fabrication technique over substrate114, e.g., material deposition, photolithographic patterning using masks and etching, etc. In other embodiments, as will be described, gate conductor(s)116may not be active gate(s), and may include other materials than listed above.

FIG.1also shows forming a semiconductor layer122over gate conductor(s)116for CMOS transistor region112and, if bipolar transistor region110is present, for creating at least one of an intrinsic base and an extrinsic base (within dashed box124) for bipolar transistor region110.FIG.1also shows forming a dielectric layer120over gate conductor(s)116. Semiconductor layer122and dielectric layer120may be formed by any appropriate deposition technique. “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. Semiconductor layer122and dielectric layer120may be formed, for example, by ALD. A mask may be used to block deposition of dielectric layer120over bipolar transistor region110, or dielectric layer120may be etched off region110. It will recognized that the processing illustrated for CMOS transistor region112can be performed without the processing shown relative to bipolar transistor region110, i.e., where no bipolar transistors are present in IC102.

Semiconductor layer122may include, for example, silicon (Si) or silicon germanium (SiGe). As noted, semiconductor layer122may be the same layer as that is used to form an intrinsic base and/or an extrinsic base (in dashed box124) of bipolar transistor region110. In this case, semiconductor layer122may include a dopant concentration of greater than 5E18 atoms/cm3. The dopant may be any appropriate element for the polarity type of the base(s) of a bipolar transistor158(FIG.2) to be formed in region110. N-type dopants are elements introduced to semiconductor to generate free electron (by “donating” electron to semiconductor), and must have one more valance electron than semiconductor; common donors in silicon (Si): phosphorous (P), arsenic (As), antimony (Sb) and in gallium arsenic (GaAs): sulphur (S), selenium (Se), tin (Sn), silicon (Si), and carbon (C). P-type dopants are elements introduced to semiconductor to generate free hole (by “accepting” electron from semiconductor atom and “releasing” hole at the same time); acceptor atom must have one valence electron less than host semiconductor. P-type dopants: may include but are not limited to: boron (B), indium (In) and gallium (Ga).

Dielectric layer120may include any suitable dielectric material including but not limited to: carbon-doped silicon dioxide materials; fluorinated silicate glass (FSG); organic polymeric thermoset materials; silicon oxycarbide; SiCOH dielectrics; fluorine doped silicon oxide; spin-on glasses; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics, and any silicon-containing low-k dielectric. Examples of spin-on low-k films with SiCOH-type composition using silsesquioxane chemistry include HOSP™ (available from Honeywell), JSR 5109 and 5108 (available from Japan Synthetic Rubber), Zirkon™ (available from Shipley Microelectricals, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silicon dioxide materials, or organosilanes, include Black Diamond™ (available from Applied Materials) and Coral™ (available from Lam Research). An example of an HSQ material is FOx™ (available from Dow Corning). Here, for example, dielectric layer120may include a high temperature oxide (HTO). It is noted that, regardless of form, gate conductor116is covered by dielectric layer120, and therefore generally electrically isolated from structure thereover.

FIG.2shows patterning semiconductor layer122to extend orthogonally over gate conductor(s)116—see also, the plan view ofFIG.4. This step is shown after a number of intervening steps to form emitter128in bipolar transistor region110. These intervening steps may include any now known or later developed techniques, and thus will be not be described in further detail. As shown, a mask130may be formed and patterned to allow patterning of semiconductor layer122. Where bipolar transistor region110is provided, mask130may also be used to pattern parts of intrinsic and/or extrinsic base (within dashed box124). Any appropriate masking and etching process may be used to pattern semiconductor layer122, e.g., a silicon nitride hardmask and etching.FIG.4shows one embodiment of fuse link140including the semiconductor layer (after silicidation) extending orthogonally over gate conductor(s)116. Here, a RIE may be used, for example, to pattern the semiconductor layer.

FIG.3shows a cross-sectional view of forming a fuse link140for e-fuse100by siliciding semiconductor layer122over dielectric layer120over gate conductor(s)116.FIG.4shows a schematic plan view of e-fuse100with a view line3-3indicating the cross-sectional view provided byFIG.3.FIGS.3and4omit bipolar transistor region110(FIGS.1-2) for clarity. The silicidation process forms a silicided semiconductor layer142including semiconductor layer122of silicon (Si) or silicon germanium (SiGe), having silicide layer144thereon. Hence, fuse link140includes silicided semiconductor layer142with semiconductor layer122and silicide layer144. Silicide layer144may be formed using any now known or later developed technique, e.g., performing an in-situ pre-clean, depositing a metal such as titanium, nickel, cobalt, etc., annealing to have the metal react with semiconductor layer122, and removing unreacted metal. While shown along all of the length of fuse link140, silicide layer144may be only along a portion of fuse link140.FIG.3also shows silicided semiconductor layer142(fuse link140) is non-planar over gate conductor(s)116. That is, it includes peaks and valleys as the layer extends over gate conductor(s)116.

FIGS.3and4also show forming (finalizing) e-fuse100by forming a first terminal150electrically coupled to a first end152of fuse link140, and a second terminal154electrically coupled to a second end156of fuse link140. Terminals150,154are on opposite sides of gate conductor(s)116. Terminals150,154may be formed using any now known or later developed electrical interconnect forming processes. In one non-limiting example, an interlayer dielectric (ILD)148(FIG.3) may be deposited (e.g., using ALD). ILD148may include any dielectric listed previously herein for dielectric layer120. Terminals150,154may be formed by patterning a mask, and etching terminal openings to the respective ends152,156of fuse link140, e.g., using a RIE. Ends152,156, as shown inFIG.4, may be patterned during semiconductor layer122patterning, as described herein, to be enlarged compared to the rest of fuse link140to provide a landing area for terminals150,154. A conductor can then be formed in the terminal openings. The conductor may include refractory metal liner, and a terminal metal. The refractory metal liner (not labeled for clarity) may include, for example, ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), iridium (Jr), rhodium (Rh) and platinum (Pt), etc., or mixtures thereof. The terminal metal may include any now known or later developed conductor such as but not limited to copper (Cu) or tungsten (W).

E-fuse100includes fuse link140including silicided semiconductor layer142over dielectric layer120covering gate conductor116. E-fuse100also includes first terminal150electrically coupled to first end152of fuse link140, and second terminal154electrically coupled to second end156of fuse link140. As noted, silicided semiconductor layer142may be in a same layer as at least one of an intrinsic base and an extrinsic base (dashed box124(FIG.2)) of bipolar transistor158(FIG.2). Gate conductor(s)116is covered by dielectric layer120and is free of silicide under dielectric layer120under silicided semiconductor layer122.

Fuse link140is configured, i.e., shaped and/or dimensioned, to allow metal or metal alloy migration upon application of the appropriate current applied through terminals150,154to open fuse link140, i.e., to control a programing energy to open or blow the fuse. For example, fuse link140may be formed to have any desired length WL(FIG.4), e.g., during patterning of semiconductor layer122(FIG.2).

A length of fuse link140can also be controlled in a number of ways during fabrication to generate e-fuse100with a desired programming energy. Since silicided semiconductor layer142of fuse link140extends orthogonally over gate conductor(s)116, the silicided semiconductor layer142and fuse link140are non-planar and a length thereof can be controlled by controlling a length and/or height of gate conductor(s)116and/or dielectric layer120. For example, the height of gate conductor(s)116and a thickness of dielectric layer120can be controlled to customize the length of fuse link140required to pass thereover. Alternatively, a length Lg(FIG.3) of gate conductor(s)116can be controlled to change the length of fuse link140.

The number of gate conductors116may also be selected to customize the length of fuse link140. InFIGS.3and4, two gate conductors116are illustrated. However, any number of gate conductors116may be provided. Thus, fuse link140may include silicided semiconductor layer142over dielectric layer120covering a plurality of gate conductors116such that the non-planar fuse link includes any number of peaks and valleys. One gate conductor116or more than two gate conductors116may be used.FIG.5shows a cross-sectional view andFIG.6shows a schematic plan view (with view line5-5indicating the cross-sectional view line ofFIG.5) of e-fuse100with one gate conductor116. Here, for example, a length Lg and/or height of gate conductor116and dielectric layer120can be fabricated to control a length of fuse link140.FIG.7shows a cross-sectional view andFIG.8shows a schematic plan view (with view line7-7indicating the cross-sectional view ofFIG.7) of e-fuse100with more than two gate conductors116. A length Lg and/or a height of each gate conductor116and/or dielectric layer120can also be selected to control a length of fuse link140. Any number of a number of peaks and valleys in fuse link140can be formed in this manner.

As shown inFIGS.9-11, a length of fuse link140can also be controlled by providing fuse link140with at least one lateral turn160therein. In this manner, the length of fuse link140can be selected by the number of times fuse link140passes over gate conductor(s)116, and the additional length provided by turn(s)160. Here, fuse link140generally extends orthogonally over gate conductor(s)116more than once, but can have some extent that may not be orthogonal. For example,FIG.9shows a plan view of fuse link140extending orthogonally over gate conductor(s)116twice, e.g., with one or two turns160therein.FIGS.10and11show plan views of two other alternative embodiments including various turns160therein.FIG.10shows e-fuse100with non-planar fuse link140having a laterally sinusoidal configuration, andFIG.11shows e-fuse100with non-planar fuse link140having a curved central portion. Turns160may be in any desired number, and/or may take any conceivable shape(s), to attain the desired programming energy. As illustrated inFIGS.10and11, in certain embodiments, fuse link140may extend at a non-orthogonal angle over gate conductor(s)116. Turn(s)160allow for the area of fuse link140to be minimized.

Referring toFIGS.7,8and12, plan views of alternative embodiments are illustrated. In certain embodiments, gate conductor(s)116may not act as part of active device(s). For example, as shown inFIGS.7,8and12, gate conductor(s)116may be non-operational, meaning they do not have any source/drain regions nor any active device connections thereto. In this case, gate conductor(s)116may include in addition to the materials listed previously herein, any dummy gate material, e.g., amorphous silicon, or any other appropriate dummy gate material. In other embodiments, gate conductor(s)116may be a resistor(s)162(see e.g.,FIG.12). In this case, gate conductor(s)116may act to heat e-fuse100to control the programming energy. When connected to a supply, gate conductor(s)116will generate heat depending on the resistance value, which may reduce the programming energy needed for the fuse.

Referring toFIGS.13-14, schematic plan views of other embodiments of e-fuse100are illustrated. A position of fuse link140relative to gate conductor(s)116may also be varied to control programming energy. For example, one may select the location of fuse link140over gate conductor(s)116to obtain a lowest programming energy. The selected location might not be a center of gate conductor(s)116. For example, inFIG.13, fuse link140is adjacent an active transistor168A and not at a center of gate conductor(s)116. InFIGS.4,9and14, fuse link140is between active transistors168B, C that share gate conductors116, and is generally centered along gate conductor(s)116. In another embodiment, where other structure does not prohibit, for example as inFIG.8, fuse link140can be anywhere along lengths of gate conductors116.

Referring toFIGS.13-14, in certain embodiments, gate conductor116may be part of a control transistor170configured to electrically couple a current source172to first terminal150for programming e-fuse100with second terminal154electrically coupled to ground. In one embodiment, gate conductor(s)116may be part of a CMOS control transistor170, and the CMOS transistor may be configured to electrically couple current source172to non-planar fuse link140for programming e-fuse100. In the examples shown inFIGS.13-14, drain region118D of control transistor170is coupled to first (cathode) terminal150of e-fuse100via any form of IC interconnect180, and second terminal154is coupled to current source172. A source region118S of control transistor170is coupled to ground. In this manner, upon activation of control transistor170, current flows from current source172through e-fuse100to ground, causing programming of e-fuse100, i.e., opening of fuse link140. A bipolar transistor158(FIG.2) can be similarly arranged to be control transistor170. In other embodiments, a bipolar transistor158(FIG.2) can be used as the programming source for e-fuse100instead of a CMOS transistor in CMOS region112.

FIG.15shows a cross-sectional view of IC102including bipolar transistor region110and CMOS transistor region112. Here, IC102includes bipolar transistor158including an intrinsic base and/or an extrinsic base (dashed box124), and a CMOS transistor168. IC102also includes e-fuse100including non-planar fuse link140including silicided semiconductor layer142over dielectric layer120covering gate conductor(s)116. As illustrated in, for example,FIGS.4,6,8,9and12-14, silicided semiconductor layer142extends orthogonally over gate conductor(s)116. E-fuse100also includes first terminal150electrically coupled to first end152of non-planar fuse link140, and second terminal154electrically coupled to second end156of non-planar fuse link140. Silicided semiconductor layer142is a same layer as at least one of intrinsic base and extrinsic base (dashed box124) of bipolar transistor158. In this case, silicided semiconductor layer142may include a dopant, which may have a dopant concentration of greater than 5E18 atoms/cm3, to accommodate the bases of bipolar transistor158. Silicided semiconductor layer142may include, for example, silicon (Si) or silicon germanium (SiGe). In certain embodiments, e.g.,FIGS.13-14, gate conductor(s)116is part of CMOS control transistor170that is configured to electrically couple current source172to non-planar fuse link140for programming e-fuse100. In other embodiments, e.g.,FIG.12, gate conductor(s) is a resistor162, capable of heating fuse link140to control a programming energy. In other embodiments, non-planar fuse link140may include at least one turn160therein, as inFIGS.9-11. Non-planar fuse link140may extend orthogonally over gate conductor(s)116more than once, as inFIG.9. Non-planar fuse link140, including silicided semiconductor layer122over dielectric layer120, may cover a plurality of gate conductors116such that non-planar fuse link140includes a plurality of peaks and valleys. Any of the embodiments described herein can be mixed and matched to control the attributes of e-fuse100.

Embodiments of the disclosure provide an e-fuse that may reduce the programming energy by, for example, 25-30%. The e-fuse also reduces the size of a programming current source172, which will reduce the overall circuitry footprint by, for example, approximately 10-25%, compared to conventional planar e-fuses. As described, e-fuse100does not require any additional masks to implement, and a minimum size is not dependent on gate length. Where the gate conductors are used as part of the control transistor, the heat from the transistor may also potentially result in lower current for the e-fuse blow resulting in further reduction in area.