Process for manufacturing an integrated CMOS circuit

In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention is based on the problem of specifying an improved 
method for producing an integrated CMOS circuit using dual work function 
gate technology in which lateral dopant diffusion is suppressed and which 
can be carried out with reduced process complexity compared with known 
solutions. 
2. Description of the Prior Art 
Both n-channel MOS transistors and p-channel MOS transistors are used in 
CMOS logic circuits; for example, in inventors. Electrical connections 
between gate electrodes of p-channel MOS transistors and n-channel MOS 
transistors are, in this case, very often realized in a gate plane which 
is formed by structuring a layer and which comprises, in addition to the 
gate electrodes, connection elements between the gate electrodes. It is 
very often the case that the gate electrodes and the connection elements 
between the gate electrodes are formed as a continuous gate line. In CMOS 
circuits which are operated with a supply voltage of 5 volts, the gate 
structure is usually formed from n.sup.+ -doped polysilicon or polycide. 
In CMOS circuits for low-voltage/low-power applications which are operated 
with a supply voltage of &lt;3 volts, the MOS transistors are optimized such 
that they have threshold voltages .vertline.V.sub.th .vertline.&lt;0.5 volt 
in conjunction with low leakage currents. The associated high requirements 
on the short-channel behavior of the MOS transistors are satisfied by the 
use of dual work function gate technology with an optimized gate work 
function. Dual work function gate technology is understood to mean the 
fact that the gate electrode of the n-channel MOS transistors is n.sup.+ 
-doped and the gate electrode of the p-channel MOS transistors is p.sup.+ 
-doped. Owing to this different doping in the gate electrodes for the 
n-channel MOS transistors and the p-channel MOS transistors, there is the 
risk of lateral dopant diffusion in the case of a gate structure having a 
continuous gate line which connects differently doped gate electrodes 
(see, for example, L. C. Parrillo, IEDM '85, p. 398). 
The electrical properties, for example the threshold voltage V.sub.t h, of 
the MOS transistors depend on the gate doping. Lateral dopant diffusion 
leads to a change in the gate doping and thus to undesirable, 
uncontrollable parameter shifts. In the extreme case, it is possible for 
reverse doping of the gate electrodes to occur, and hence total failure of 
the components. Furthermore, in the connection between n.sup.+ -doped gate 
electrodes and p.sup.+ -doped gate electrodes, it is necessary, with 
regard to a low bulk resistance, that n.sup.+ -doped regions and p.sup.+ 
-doped regions adjoin one another directly since otherwise a space charge 
zone forms. 
In order to suppress lateral dopant diffusion in dual work function gate 
technology, it has been proposed (see, for example, D. C. H. Yu et al., 
Int. J. High Speed Electronics and Systems, Vol. 5, p. 135, 1994) not to 
use any continuous connections made of polysilicon between differently 
doped gate electrodes in the gate plane. Instead, the gate line made of 
polysilicon is interrupted and is electrically conductively connected via 
a metal bridge made of aluminum, for example. As an alternative, after the 
interruption of the gate line, a suitable metallic conductor (TiN, WI 
WSi.sub.2) is deposited and structured. This solution is complicated and 
in some instances requires additional space for contact-making and 
metallization. 
Furthermore, it has been proposed (see C. Y. Wong et al., IEDM '88, p. 238) 
to produce, in dual work function gate technology, planar source/drain 
regions and the correspondingly doped gate electrodes by implantation with 
the same dopant. For this purpose, the implantations are carried out 
before the structuring of the gate electrodes. With regard to planar 
source/drain regions, limitations must be observed in the case of the 
implantation doses and the thermal loading. However, this leads to a 
narrow process window; for example, during dopant activation in the gate 
electrode and during planarization reflow. 
SUMMARY OF THE INVENTION 
In a method according to the present invention, a polysilicon layer 
produced for the purpose of forming the gate structure. The average grain 
diameter in the polysilicon layer is greater than the minimum extent in 
the gate plane. The invention makes use of the insight that lateral dopant 
diffusion in the gate structure is principally caused by grain boundary 
diffusion in the polycrystalline silicon. This grain boundary diffusion is 
extremely rapid. For example, boron diffusion in monocrystalline silicon 
is less than along the silicon grain boundaries in polycrystalline silicon 
by a factor of 100 to 1000. 
By using a polysilicon layer having an average grain diameter greater than 
the minimum dimensions in the gate structure, the grain boundary density 
in the region of the minimum dimensions in the polysilicon layer is 
drastically reduced in the method according to the present invention. In 
this region, diffusion takes place only in the silicon grains at a 
diffusion rate similar to that in monocrystalline silicon. The polysilicon 
layer is preferably produced by deposition of an amorphous silicon layer 
and subsequent solid phase crystallization, as is disclosed for example in 
S. Takenaka et al., SSDM '90, p. 955. The minimum dimension may be the web 
width of the connection between two gate electrodes, for example. 
A further improvement with regard to the suppression of lateral dopant 
diffusion is obtained by a design measure in the gate structure. When the 
polysilicon layer is structured, a constriction is created in the 
connection between gate electrodes of n-channel and p-channel MOS 
transistors. The width of the connection in the region of the constriction 
is smaller than outside the latter and less than the average grain 
diameter of the polysilicon layer. The constriction is preferably situated 
in the region in which n.sup.+ -doped polysilicon adjoins p.sup.+ -doped 
polysilicon. 
The invention utilizes the fact that the diffusion in the silicon grains 
takes place in a manner corresponding to the diffusion in monocrystalline 
silicon, and is thus greatly reduced in comparison with diffusion via 
grain boundaries. Since the average grain size of the polysilicon layer is 
greater than the smallest dimension in the gate structure, diffusion can 
take place only in the silicon grains at this location of the smallest 
dimension, since there is no grain boundary here. 
The integrated CMOS circuit is preferably formed in a semiconductor 
substrate having monocrystalline silicon at least in the region of the 
CMOS circuit. In this case, the semiconductor substrate may be either a 
monocrystalline silicon wafer or a monocrystalline silicon layer of an SOI 
substrate. 
Insulation structures for defining the active regions for the n-channel MOS 
transistor and the p-channel MOS transistor are formed in the 
semiconductor substrate. These insulation structures are formed using a 
LOCOS method with regard to customary logic processes. However, the 
insulation structures can also be formed in a different way, for example 
by means of a trench filled with insulating material. 
It lies within the scope of the present invention to produce a p-doped well 
in the active region for accommodating the n-channel MOS transistor and an 
n-doped well in the active region for accommodating the p-channel MOS 
transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
In a substrate 1 made of monocrystalline silicon, for example, field oxide 
regions 2 which define an active region 4a for a p-channel MOS transistor 
and an active region 4b for an n-channel MOS transistor are produced using 
a LOCOS method, (see FIG. 1). An n-doped well 3a is produced in the active 
region 4a for the p-channel MOS transistor. A p-doped well 3b is produced 
in the active region 4b for the n-channel MOS transistor. The field oxide 
regions 2 and the wells 3a, 3b are produced according to process steps 
which are customary in CMOS technology. A dopant concentration of 
1.times.10.sup.17 P/cm.sup.3, for example, is set in the n-doped well 3a, 
and a dopant concentration of 1.times.10.sup.17 B/cm.sup.3, for example, 
is set in the p-doped well 3b. 
A gate oxide 5 is grown to a thickness of 3 to 10 nm, for example, by means 
of thermal oxidation at 900.degree. C., (see FIG. 2). An amorphous silicon 
layer 6a is subsequently deposited over the whole area. The amorphous 
silicon layer 6a is deposited using low temperature deposition at a 
temperature of below 500.degree. C., preferably in the range of 0.1-10 
torr using disilane (Si.sub.2 H.sub.6). This low temperature deposition 
process has the advantage over an SiH.sub.4 process in that the amorphous 
silicon layer 6a exhibits an improved crystallization behavior. The 
amorphous silicon layer 6a is produced either without doping or with a 
slight doped with a dopant concentration of less than 5.times.10.sup.19 
cm.sup.-3 with a layer thickness of 50 to 500 nm. 
The amorphous silicon layer 6a is subsequently converted into a polysilicon 
layer 6b by crystallization at a low temperature, preferably between 
600.degree. and 800.degree. C. (see FIG. 3). The polycrystalline silicon 
layer 6b is composed of large-grain polysilicon with an average grain size 
&lt;L&gt; of preferably &gt;200 nm. The average grain size &lt;L&gt; can be set by way of 
the heat-treatment conditions, that is to say temperature and duration of 
the crystallization. With heat-treatment conditions of 600.degree. C., 8 
hours, it is possible to obtain an average grain size of several .mu.m. 
The polysilicon layer 6b is structured with the aid of a 
photolithographically produced mask and an etching technique; for example 
by means of anisotropic etching using HBr/Cl.sub.2 gas. A gate structure 
6c, which includes, in addition to undoped gate electrodes 7 for the 
p-channel MOS transistor and the n-channel MOS transistor, a connection 70 
between the two gate electrodes 7, is formed in the process. The 
connection 70 includes a constriction 89 at which the width of the 
connection 70 is reduced. The width 8 is 250 nm, for example, in the 
region of the constriction 89. Outside the constriction 89, the width of 
the connection 70 corresponds to the width 7a, 7b of the gate electrodes 
7, which is equal to the gate length of the p-channel MOS transistor and 
of the n-channel MOS transistor, respectively (see FIG. 4). 
The width 8 of the constriction 89 is set such that it is smaller, 
preferably significantly smaller, than the average grain size &lt;L&gt;. The 
length 9 of the constriction 89, on the other hand, is set such that it is 
greater than the average grain size &lt;L&gt; of the polysilicon. It is ensured 
in this way that lateral dopant diffusion takes place almost exclusively 
in the silicon grains in the region of the constriction 89. The width 8 
and the length 9 of the constriction 89 are set in dependence on the 
polysilicon grain size, the thermal budget as well as on boundary 
conditions relating to design and lithography. At an average grain size 
&lt;L&gt; of 400 nm, for example, the width 8 is 250 nm, the length 9 is 800 nm 
and the gate length 7a, 7b is 1 .mu.m, 
The undoped gate electrodes 7 are subsequently provided with SiO.sub.2 
spacers 10 by means of conformal deposition of an SiO.sub.2 layer and 
anisotropic etching back of the SiO.sub.2 layer using CHF.sub.3 /Ar, for 
example. A thermal oxide layer 11 is produced to a thickness of 15 nm on 
exposed silicon surfaces by means of thermal oxidation at 900.degree. C., 
for example (see FIG. 6). 
A photoresist mask 12, which covers the active region 4b for the n-channel 
MOS transistor, is subsequently produced with the aid of photolithographic 
process steps (see FIG. 7). In this case, the photoresist mask 12 reaches 
as far as the adjacent field oxide regions 2. The photoresist mask 12 
reaches right into the region of the constriction 89 (see FIG. 8). A 
p.sup.+ -doped gate electrode 14 and also p-doped source/drain regions 15a 
are produced for the p-channel mass transistor by means of ion 
implantation 13 with boron or BF.sub.2 with a dose of 5.times.10.sup.15 
at/cm.sup.2, for example, and an energy of, for example, 15 and 40 keV, 
respectively. At the same time, that part of the connection 70 which is 
not covered by the photoresist mask 12 is p.sup.+ -doped. 
After the removal of the resist mask 12, a photoresist mask 16 is produced 
which covers the region for the p-channel MOS transistor (see FIG. 9). In 
the region of the connection 70, the photoresist mask 16 reaches as far as 
the constriction 89 (see FIG. 10). An n.sup.+ -doped gate electrode 18a 
and also n-doped source/drain regions 19a are formed by means of 
implantation 17 with arsenic or phosphorus with a dose of 
5.times.10.sup.15 at/cm.sup.2 and an energy of 60 and 120 keV, 
respectively. During the implantation 17, that part of the connection 70 
and of the constriction 89 which is not covered by the photo-resist mask 
16 is n.sup.+ -doped. 
The photoresist mask 16 is subsequently removed. 
The implanted dopant is electrically activated by subjecting the substrate 
1 to a heat treatment. p-doped source/drain diffusion regions 15b and 
n-doped source/drain diffusion regions 19b are formed in the process. 
Furthermore, a p-doped gate 14b is produced for the p-channel MOS 
transistor and an n-doped gate 18b is produced for the n-channel MOS 
transistor (see FIG. 11 and FIG. 12). 
The thermal SiO.sub.2 layer 11 is removed by wet-chemical means, for 
example using HF/HNO.sub.3. Afterwards, a metallic conductor 20 is applied 
selectively to exposed silicon areas, that is to say on the surface of the 
n-doped and, respectively, p-doped source/drain diffusion regions 15b, 19b 
and on the n-doped and, respectively, p-doped gate 18b, 14b. The metallic 
conductor 20 may be formed from TiSi.sub.2 using a salicide method, for 
example. Furthermore, the metallic conductor 20 may be applied by 
selective deposition of tungsten using a CVD method. The metallic 
conductor 20 also extends over the connection 70 with the constriction 89. 
n.sup.+ -doped and p.sup.+ -doped regions of the connection 70 adjoin one 
another in the region of the constriction 89. The metallic conductor 20 
runs over this boundary and connects the n.sup.+ -doped regions of the 
connection 70 to the p.sup.+ -doped regions. 
Owing to the grain size of the polysilicon layer, no appreciable lateral 
diffusion occurs during the heat treatment for activating the dopant in 
the region of the constriction 89. A well-defined boundary between n.sup.+ 
-doped and p.sup.+ -doped regions of the connection 70 is preserved in the 
region of the constriction 89. The p.sup.+ -doped gate 14b is connected to 
the n.sup.+ -doped gate 18b. The structure constitutes an invertor. 
The circuit arrangement is completed by the deposition of a layer of 
borophosphorus silicate glass and planarization, also by etching contact 
holes and metallization (not specifically illustrated). 
Although the present invention has been described with reference to 
specific embodiments, those skilled in the art will recognize that changes 
may be made thereto without departing from the spirit and scope of the 
invention as set forth in the hereafter appended claims.