Power management based on real time platform power sensing

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

BACKGROUND

Power management in a computing system is a complex task. Usually, power management is handled by software, which may provide updated power budget at periodic intervals of about 25 milliseconds or longer.

DETAILED DESCRIPTION

In some embodiments, a computing platform (also referred to as computing device, or merely as a device) may comprise multiple processor sockets, where each socket may include corresponding processing cores. The device may further comprise multiple sensors corresponding to the multiple processor sockets, such that a sensor may measure power consumption of a corresponding socket. Furthermore, a system power sensor may measure total platform input power. A power control unit (PCU, also referred to as controller herein) may be implemented in a socket. The PCU may receive measurements from various sensors. The PCU may also access power limits of various sockets, as well as power limits of various other components, which may be stored in corresponding registers.

In some embodiments, the PCU may allocate power budgets to various components of the device, based on the measurements of the total platform input power, measurements of power consumption of various sockets, power limits of various components, etc. The allocation of power budget may be dynamic. For example, if a component does not fully use the allocated power budget, the power budget of the component may be reduced and power budgets of one or more other components may be correspondingly increased.

In some embodiments, the PCU may be implemented in hardware and/or firmware, and may execute Pcodes. In an example, the sensing may be done in a relatively high frequency, such as every 80 to 100 microseconds merely as an example. Merely as an example, the PCU may update its power allocation decision every at most 5 milliseconds.

During normal operation, the sensor measuring the total platform input power may transmit the analog measurement information to the PCU via an ADC. However, in an event of power spike, the sensor measuring the total platform input power may directly transmit the power spike information to the PCU, e.g., by bypassing the ADC. In another example, the ADC may transmit the power spike information to the PCU, e.g., even before the analog-to-digital conversion in completed. The PCU may immediately throttle one or more processing cores, thereby mitigating or reducing the power spike. Other technical effects will be evident from the various embodiments and figures.

FIG.1schematically illustrate a computing device100(also referred to henceforth as device100, or computing platform100) that measures in real time platform input power, and that allocates power budget to various components based at least in part on the platform input power, according to some embodiments. In some embodiments, the device100may be any appropriate computing device or computing platform, e.g., a server system, a server rack, a laptop, a desktop, a mobile computing device, a cellular phone, and/or the like.

The device100may comprise multiple processor sockets (also referred to as sockets)108a,108b. Although the device100may comprise multiple sockets, the example ofFIG.1illustrates merely two sockets108a,108bfor purposes of illustrative clarity—the device100may include more than two sockets. Individual sockets may include multiple processing cores. For example, the socket108amay comprise cores110a1and110a2, and the socket108bmay comprise cores110b1, and110b2. Although individual sockets are illustrated to include merely two corresponding cores, such a number of cores is merely an example, and a socket may include any appropriate number of cores.

Elements referred to herein with a common reference label followed by a particular number or alphabet may be collectively referred to by the reference label alone. For example, sockets108a,108bmay be collectively and generally referred to as sockets108in plural, and socket108in singular. Similarly cores110a1,110a2may be collectively and generally referred to as cores110ain plural, and core110ain singular.

In some embodiments, the socket108acomprises, in addition to the cores110a, a sensor114a; and the socket108bcomprises, in addition to the cores110b, a sensor114b. Although the sensors114a,114bare illustrated to be included in the corresponding sockets108a,108b, in some examples the sensors114a,114bmay be external to the sockets108a,108b.

A sensor114may measure power consumed by a corresponding socket108. For example, the sensor114amay measure power consumed by the socket108a, and the sensor114bmay measure power consumed by the socket108b. In some embodiments, any appropriate type of sensors114may be used.

In some embodiments, a socket108may be included in a corresponding die (where the die is not labeled inFIG.1). For example, a die may comprise a System on a Chip (SOC), including a corresponding socket108. A sensor114may measure power consumed by the corresponding die, including by the corresponding socket108. An on-die power measurement sensor114may be used to measure the power consumption.

In some embodiments, a socket108may include a corresponding controller112. For example, the socket108amay include a corresponding controller112a, and the socket108bmay include a corresponding controller112b. The controller112may be a Power Control Unit (PCU) to control power of the corresponding socket, and/or to control power of one or more components of the device100, as will be discussed in further details herein.

In some embodiments, the device100may comprise memory132a,132bassociated with the socket108a, and memory132c,132cassociated with the socket108b. For example, the memory132a,132bmay primarily be accessed by the cores110a1,110a2of the socket108a, and the memory132c,132dmay primarily be accessed by the cores110b1,110b2of the socket108b(although the socket108bmay also access the memory132a,132b, and the socket108amay also access the memory132c,132d).

The device100may comprise other components, e.g., fan130a, drivers130b, and one or more other components that are generally labeled as components130c,130d. The fan130a, drivers130b, and the components130c,130dare generally referred to as components130in plural, and component130in singular.

In some embodiments, the device100comprises a power supply unit (PSU)102that may transmit input power to the device100. For example, the PSU102may be an Alternating Current (AC) adapter that is to receive external AC power (indicated as external power inFIG.1) and to supply Direct Current (DC) power to the device100. In another example, the PSU102may receive external DC power, and supply the DC power to the device100. Thus, in an example, the PSU102may supply input power to the device100.

In the example ofFIG.1, it is assumed that the device100does not include a battery, although the device100may include a battery. For example,FIG.2illustrates the computing device100ofFIG.1including a battery103, according to some embodiments. Although not illustrated inFIGS.1-2, the PSU102and/or the battery103supplies power to various components of the device100.

In some embodiments, input power (e.g., power supplied by the PSU1-2and/or the battery103) is a finite resource. The nature of the input power limits may be as simple as capacity of input power supplies, and as complex as imposed power limits dependent on a cost of the power company rates at the time of implementation.

Referring toFIGS.1and2, in some embodiments, the device100may further comprise a sensor116that is to measure an input power to the device100, which may be a total power consumed by the device100. The power measured by the sensor116may also be referred to as platform power, total DC system power, total system power, platform input power, and/or the like. In the example ofFIG.1, the sensor116may measure the power supplied by the PSU102. In the example ofFIG.2, the sensor116may measure the power supplied by the combination of the PSU102and the battery103. The sensor116may measure DC system power of the device100.

In an example, a sensor116may be included in an Integrated Circuit (IC) chip that measures total DC input power (e.g., generated by the PSU102), and converts the measurement to a current proportional, noise immune analog signal129.

In some embodiments, the output signal129of the sensor116may be analog, which may be a noise immune analog signal. In some embodiments, the analog signal129output by the sensor116may be converted in a digital form by an ADC120. In the example ofFIGS.1and2, the ADC120is implemented as a part of a Voltage Regulator (VR)118. For example, the VR118of the device100may include one or more ADCs. The analog output of the sensor116may be converted in the digital form using the ADC120of the one or more ADCs of the VR118. Thus, the ADC120used to convert the output of the sensor116may be shared with the VR118.

However, in some other examples, the ADC120may not be associated with, or included in, the VR118. For example,FIG.3illustrates the computing device100ofFIG.1, where the sensor116is used to measure system input power, and where an analog input of the sensor116is converted in digital form using the ADC120that is not associated with, or included in, a VR, according to some embodiments. Thus, in the example ofFIG.3and unlikeFIGS.1and2, the ADC120is not included in, or associated with, the VR118.

In some embodiments (e.g., inFIGS.1and/or2), the sensor116may be integrated within the VR118. In an example and as discussed herein, the output of the sensor116may be noise immune analog signal that indicates the system power. In an example, the sensor116may be placed relatively close to the power source input (e.g., PSU102), e.g., to a point in the power supply line before the power gets distributed to various subsystems or components of device100.

InFIGS.1-3, the ADC120generates a digital signal132that is representative of the analog output of the sensor116, and the VR118transmits the signal132to the socket108a(e.g., to the controller112a). Thus, the signal132is representative of a total system input power of the device100.

The socket108amay transmit Voltage Identifications (VIDs) to the VR118, where a VID may indicate a desired output voltage of the VR118. In an example, the socket108amay transmit the VIDs to the VR118over a Serial VID (SVID) bus or SVID interface, or over another appropriate high-speed communication bus (e.g., a Power Management Bus (PMBus)). In some embodiments, the VR118may transmit the signal132as a SVID payload to the socket108a(e.g., to the controller112a) over the SVID interface (or over another appropriate high-speed communication bus between the VR118and the socket108a, such as the PMBus). The signal132, which may be the SVID payload, may be indicative of the total system input power of the device100. The VR118outputs the SVID payload signal132over, for example, a SVID channel. The SVID channel may be a standard interface used to communicate the VIDs from the socket108ato the VR118, as well as power telemetry (e.g., signal132) from the VR118to the socket108a.

Thus, voltage IDs output by the VR118for voltage regulation purposes, as well as the SVID signal132, may share the same SVID channel between the VR118and the socket108a. As the SVID channel is a relatively fast data transmission channel, the SVID channel may be reused for transmission of the digital conversion of the analog output of the sensor116(e.g., reused for transmission of the signal132).

In the example ofFIG.3where the ADC120is not part of a VR, the output signal132of the ADC120may be an ID signal comprising one or more bits that are indicative of the total system input power of the device100.

Referring toFIGS.1-3, the controller112amay be based on hardware and/or firmware of one or more of the cores110aof the socket108a. In some embodiments, the controller112areceives the digital signal132. The controller112amay also receive outputs of the sensors114aand114b(e.g., in case of more than two sockets in the device100, the controller112amay receive measurements of power consumed by individual ones of the various sockets). In some embodiments, the controller112amay allocate power budget or power limit of various components of the device100, based on the received measurement of the total system power (e.g., as indicated in the signal132) and the received measurements of the power consumption of individual sockets108(e.g., as measured by the sensors114). For example, the controller112amay calculate available frequency headroom, while meeting programmed power limits.

In some embodiments, the socket108amay comprise a plurality of registers133a,133b, . . . ,13N. Individual ones of the registers133may be programmed with a corresponding power limit. For example, a first register133amay be programmed with a first socket power limit of a socket108a(e.g., a maximum amount of power that may be consumed by the socket108a), a second register133bmay be programmed with a first memory power limit of a memory132a(e.g., a maximum amount of power that may be consumed by the memory132a), a third register133cmay be programmed with a second socket power limit of a socket108b(e.g., a maximum amount of power that may be consumed by the socket108b), and so on.

In an example, the multiple registers133may be programmed by one or more agents (not specifically labeled inFIG.1) of the device100using, for example, an out of band mechanism. In another example, the multiple registers133may be programmed using in band mechanism, such as software. The controller112amay honor the programmed power limits of the registers133, while allocating power budget (e.g., while setting voltage, frequency, etc.) to one or more components of the device100. The power limits in the registers133may be changed dynamically, in some examples.

In some embodiments, the controller112areceives the signal132indicative of the total system power, compares the total system power to the configured power limits stored in the registers133, takes into account the power consumption of the various sockets108, and runs a control loop feedback mechanism (e.g., a proportional, integral and derivative (PID) control loop) to calculate power budgets to manage system power. The output of this process may be the resolved or allocated power budgets for various components of the device (e.g., sockets108, memory132, components130, etc.). The allocated power budgets can be in terms of power, current, voltage, frequency, and/or the like. The socket108a, which may run the control loop, may adhere to these budgets and the controller112amay guarantee the same. In the case of multi-socket system (e.g., as the device100comprises more than one socket), the controller112aof the socket108amay communicate the new budgets to all other sockets (e.g., socket108b) and/or other components. In some embodiments, the transmission of the allocated power budgets of the socket108b(e.g., as allocated by the controller112aof the socket108a) may be transmitted from the socket108ato the socket108bvia an Ultra-Path Interconnect (UPI) Peer-to-Peer (P2P) Mailbox Interface, or any other appropriate interface between two sockets.

The controller112areceives measurement of power consumed by various sockets108of the device100. Also, as the controller112areceives measurement of the total system power (e.g., using the sensor116) and also receives measurement of the power consumed by various sockets108, the controller112amay also estimate the power consumed by other components (e.g., components130, memory132, etc.) of the device100. Thus, the controller112amay be aware of the power budget allocated to various components of the device100, as well as be aware of the actual power consumed by the various components of the device100. Thus, in some embodiments, the controller112amay detect any unused power budget of a component (e.g., a socket108a).

In some embodiments, the controller112amay detect any unused power budget of a component and may re-direct such unused power budget towards other components. For example, if there is unused power budget from a memory subsystem, it may be redirected by the controller112atowards a socket108a, e.g., which may allow one or more of the cores110ato operate at higher frequency limits.

In some embodiments, the sensing of the total system power using the sensor116, the ADC120(e.g., which may be included in the VR118), and the controller112may be implemented using hardware and/or firmware. For example, using the SVID interface (or another appropriate high speed interface between the VR118and the socket108a) for the signal132and using the ADC120within the VR118(where the VR118and the SVID channel is to operate at relatively fast speed) may allow relatively fast sampling of the measurement of total system power.

The sensing by the sensor116may be updated and the corresponding digital signal132may be updated, for example, every 80 microseconds. Thus, for example, the controller112amay receive updated measurement of the total system power every 80 microseconds. In another example, the controller112amay receive updated measurement of the total system power every 100 microseconds, between every 80-120 microseconds, once every at most 200 microseconds, or the like. In some embodiments, the sampling of the total system power may be sufficiently fast such that the controller112amay relatively quickly detect any sudden variation or fluctuation in the total system power. The sampling of the total system power may be sufficiently fast such that the controller112amay detect substantially all spectral energy content of the total system power. In some embodiments, the controller112amay receive the sampling at a frequency of about 5 KHz. In an example, fast sampling of the total system power may be possible due to the use of the fast SVID channel, as discussed with respect toFIGS.1-2.

In some embodiments, the control loop may be executed by the controller112aat a continuous basis. For example, the controller112amay reevaluate the power budgets for various components at, for example, every 1 millisecond, every 2 milliseconds, every at most 5 milliseconds, or the like.

FIG.4illustrates an example implementation of the sensor116used to measure total system power of the device100ofFIG.1, according to some embodiments. Although the sensor166inFIG.4is illustrated to measure output of the PSU102(e.g., as discussed with respect toFIGS.1-3), the sensor116(or another similar sensor) may also be used to measure output power of the battery103(e.g., as discussed with respect toFIGS.2-3).

In some embodiments, the PSU102supplies power to the socket108, the memory132, the components130, etc. of the device100. The sensor116may comprise a resistor401at the output of the PSU102(e.g., the resistor401may be a shunt resistor). A comparator405may detect a voltage drop across the resistor401, to generate I_sys411, which is an estimate of the output current of the PSU102. Also, voltage V_sys409at a terminal of the resistor401may be indicate the voltage at the PSU output.

A circuitry410of the sensor116may receive the measurements of I_sys411and V_sys409. In some embodiments, based on the measurements of I_sys411and V_sys409, the circuitry410may estimate a power output Psys of the PSU102(e.g., which may be based on a product of the measurements of I_sys411and V_sys409). The circuitry410may output the signal129, which may be indicative of the power output Psys of the PSU102. For example, the signal129may be a current (e.g., a noise immune analog current) that is proportional to the power output Psys of the PSU102. In some other embodiments, the circuitry410may output the I_sys411and V_sys409(e.g., instead of determining the power Psys)—the determination of the power may be performed, for example, at the controller112a.

FIG.5illustrates an example implementation of the ADC120of the device100ofFIGS.1-3and illustrates issuance of a critical power signal, according to some embodiments. As discussed with respect toFIG.4, the sensor116may generate the analog signal129, which may be a current signal proportional to the power output Psys of the PSU102. The ADC120comprises circuitries520and522to convert the signal129to a digital signal132(which may be, for example, a SVID signal), which is then transmitted to the controller112a. The circuitries520,522may be two stages of the ADC120.

In some examples, the power level of the output of the PSU102may reach a critically high level (e.g., may be higher than a threshold), which may be a critical event for the device. Such high level of the output power of the PSU102may be due to sudden and rapid increase in power consumption of one or more components of the device100, due to a fault in the device100, etc. It may be desired to immediately throttle (e.g., reduce voltage and/or frequency) one or more components (e.g., one or more cores110of a socket108), in response to such a critical event. It may take some time for the controller112ato be aware of such a critical event, e.g., due to the time taken by the ADC120to digitalize the analog signal129. In some embodiments, to avoid such delay in the identification of the critical event by the controller112a, the ADC120may issue a power_critical signal510a, which may be a critical power event alert to indicate a critical event (e.g., may indicate that the output power of the device100is higher than a threshold).

In some embodiments, the ADC120may issue the power_critical signal510abefore completion of the analog-to-digital conversion of the critical power level. Merely as an example, while converting the analog signal129, if the ADC120senses that the signal129is higher than a threshold, the ADC120may immediately issue the power_critical signal510a(e.g., without waiting for the completion of the analog-to-digital conversion). Merely as an example, while converting the analog signal129to the digital signal132, if the ADC120senses that one or more Most Significant Bits (MSB) of the digital signal132indicates a high value of the signal129, the ADC120may immediately issue the power_critical signal510a(e.g., without waiting for determining all the bits, including the least significant bits (LSBs), of the digital signal132).

In some embodiments, instead of, or in addition to, the ADC120issuing the power_critical signal510a, the sensor116may also issue a power_critical signal510bto the controller112a, e.g., to convey that the sensed output power of the PSU102is critically high (e.g., higher than a threshold value, for example, for at least a threshold period of time). For example, if the sensor116senses that the Psys is higher than the threshold, the sensor116may also issue the power_critical signal510bto the controller112a.

Thus, for example, the power_critical signals510a,510bmay indicate a power spike in the output of the PSU102. In case of critical event such as a power spike, the controller112is alerted by the ADC120and/or by the sensor116using the power_critical signals510a,510b. The controller112may cause an immediate response (e.g., within few microseconds) by, for example, throttling one or more cores110of the socket108aand/or socket108b. For example, the controller112may throttle the one or more cores110in a manner so as to bring total system power to lower levels (e.g., within the platform prescribed limits), thereby protecting the device100from being damaged.

In some embodiments, use of the controller112amay enable migration of the task of power management from software to Central Processing (CPU) hardware or firmware. For example, the controller112amay be implemented in hardware or firmware, and may use Pcode. This may provide significantly faster response time to mitigate power spikes and/or to ensure faster power control. For example, a software-based solution may have a power peak intercept time of about 25 milliseconds, whereas the controller112amay have a power peak intercept time of about 1 millisecond, about 3 to 5 milliseconds, or the like.

In some embodiments, use of the controller112amay enable total device power budget sharing between different device components. For example, the controller112amay allow dynamic detection and redirection of any residual unused power budget from one or more components to one or more other components, while staying within existing total device power envelope, thereby improving system performance.

In some embodiments, use of the controller112amay allow for potentially higher CPU core peak frequencies (such as P0n) in some cases. In some embodiments, standardizing the flow of information across device components and the power measurement hardware itself may provide for a more accurate power sensing method.

In some embodiments, use of the controller112amay increase server rack density and utilization in a server-based system. For example, tighter control over power consumption of the servers may allow for higher server rack density. Server platforms that implement the various features discussed herein for power capping may be able to operate under a tighter peak power envelope. This in turn may allow data center operators to proportionately increase the node density in the server rack or blade designs.

In some embodiments, as the controller112amay detect power peak relatively fast (e.g., by using the power_critical signals510a,510b), redundant capacity of the PSU102may be reduced (e.g., as the power peak is detected almost immediately and the cores throttled, long duration of critical power peaks may be avoided).

In some embodiments, dynamic detection and redirection of unused power budget between components of the device100(e.g., while staying within the total platform power envelope) may allow achieving higher frequencies for the components to which the unused power is redirected towards. For example, due to the redirection of unused power from a memory132to a CPU core110, the CPU core110may operate at a higher frequency, which might even be higher than a rated frequency of the core.

For example, new, higher advertised values of frequencies of the cores110may be achieved (e.g., due to dynamic detection and redirection of unused power budget between components of the device100). For example, the registers133(or other storage devices, such as one or more fuses, not illustrated in the figures) may have higher frequency limits for the cores110. The controller112amay read these higher frequency limits of the cores110, which may allow the controller112ato opportunistically grant permission to the cores110to operate at those higher programmed frequencies. In an example, the types of frequency related fuses or registers to be programmed and their associated values may be statically determined during design phase (e.g., using bin-split analysis), taking device power delivery and other constraints (e.g., such as silicon reliability and platform cost) into consideration.

FIG.6illustrates a flowchart depicting a method600for operating the device100ofFIGS.1-5, according to some embodiments. Although the blocks in the flowchart with reference toFIG.6are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed inFIG.6may be optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

The method600comprises, at604, receiving (e.g., by the controller112a) measurements from at least one or more of the sensors116,114a,114b. As discussed with respect toFIGS.1-5, the sensors114a,114bmay respectively measure power consumption of the sockets108a,108b, and the sensor116may measure total power input to the device100. Thus, the controller112amay be aware in real time power consume by various components of the device100. The controller112amay also access power limits of various components, which may be stored in the registers133.

At604, the controller112amay allocate or reallocate power budgets to various components of the device100, based at least in part on the measurements from the sensors114a,114b,116and the power limits. For example, if a component does not consume its allocated power, the controller112amay reallocate the unused power budget from the component to another component.

At612, the controller112amay decide if a power spike is detected. For example, the controller112amay receive power spike detection information via the power_critical signal510aand/or510b, as discussed with respect toFIG.5.

If a power spike is detected (e.g., if “Yes” at612), then at616, the controller112amay throttle one or more cores110, and then the method600may loop back to block604. If no power spike is detected (e.g., if “No” at612), then the method600may loop back from block612to block604.

Although inFIG.6the block612is illustrated to occur after block608, the detection of power spike at612and subsequent throttling action based on such detection may be a continuous or ongoing process. For example, at any time in the method600(e.g., while receiving the measurements, while allocation power budgets, etc.) if a power spike is detected, the controller112amay almost immediately (e.g., within 1 to 5 milliseconds, or even less) throttle the one or more cores110.

FIG.7illustrates a computer system, a computing device or a SoC (System-on-Chip)2100, where a controller (e.g., controller112a) may receive system power consumption information (e.g., from sensor116) and also power consumption information of one or more components (e.g., from sensors114a,114b), and allocate power budget accordingly, according to some embodiments. It is pointed out that those elements ofFIG.7having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In some embodiments, computing device2100represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an IOT device, a server, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device2100.

In some embodiments, computing device2100includes a first processor2110. The various embodiments of the present disclosure may also comprise a network interface within2170such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processor2110can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor2110include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device2100to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device2100includes audio subsystem2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device2100, or connected to the computing device2100. In one embodiment, a user interacts with the computing device2100by providing audio commands that are received and processed by processor2110.

Display subsystem2130represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device2100. Display subsystem2130includes display interface2132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface2132includes logic separate from processor2110to perform at least some processing related to the display. In one embodiment, display subsystem2130includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller2140represents hardware devices and software components related to interaction with a user. I/O controller2140is operable to manage hardware that is part of audio subsystem2120and/or display subsystem2130. Additionally, I/O controller2140illustrates a connection point for additional devices that connect to computing device2100through which a user might interact with the system. For example, devices that can be attached to the computing device2100might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller2140can interact with audio subsystem2120and/or display subsystem2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device2100. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem2130includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller2140. There can also be additional buttons or switches on the computing device2100to provide I/O functions managed by I/O controller2140.

Connectivity2170includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device2100to communicate with external devices. The computing device2100could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Connectivity2170can include multiple different types of connectivity. To generalize, the computing device2100is illustrated with cellular connectivity2172and wireless connectivity2174. Cellular connectivity2172refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface)2174refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections2180include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device2100could both be a peripheral device (“to”2182) to other computing devices, as well as have peripheral devices (“from”2184) connected to it. The computing device2100commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device2100. Additionally, a docking connector can allow computing device2100to connect to certain peripherals that allow the computing device2100to control content output, for example, to audiovisual or other systems.

In some embodiments, the computing device2100may comprise multiple sockets, e.g., sockets108a,108bofFIGS.1-3. For example, various processors of the computing device2100may be included in corresponding sockets. The computing device2100may also include sensor116to measure total system power, ADC120to convert the analog measurement of the sensor116to corresponding digital measurements, sensors114a,114bto measure power consumption of the sockets108a,108b, respectively, and the controller112ato allocate power budgets to various components, e.g., as discussed with respect toFIGS.1-6of this disclosure.

All optional features of the apparatus described herein may also be implemented with respect to a method or process.