CMOS TRANSISTOR AND FABRICATION METHOD

Exemplary embodiments provide transistors and methods for forming the transistors. An exemplary CMOS transistor can be formed by epitaxially forming a first stress layer in/on a semiconductor substrate having a first region including a first gate structure and a second region including a second gate structure. A barrier layer can be formed to cover the second region and to expose the first region. The barrier layer can be used as a mask to remove a portion of the first stress layer from the first region. A second stress layer can be formed in a groove formed in the semiconductor substrate on sides of the first gate structure in the first region. The fabrication method can be simplified and the formed CMOS transistors can have high carrier mobility.

DETAILED DESCRIPTION

During formation of CMOS transistors, a stress layer is often formed in source and drain regions of the CMOS transistors. Photoresist layers are often required respectively in an NMOS region and a PMOS region as a mask for etching semiconductor substrate and for filling stress materials into the etched semiconductor substrate. Photoresist layers as etching masks are thus required for multiple times and each time the photoresist layer has to be formed first and removed later after certain processes have been performed. For this reason, multiple steps and complicated processes are used during formation of CMOS transistors.

The disclosed methods for forming CMOS transistors can involve a single time use of a mask (e.g., a barrier layer) to achieve formation of different stress layers in an NMOS region and a PMOS region. In addition, the exemplary barrier layer may or may not need to be removed. Manufacturing processes can thus be simplified with reduced manufacturing time.

FIGS. 6-10depict cross-sectional views of an exemplary CMOS transistor at various stages during its formation, whileFIG. 11depicts an exemplary method for forming a CMOS transistor at various stages during its formation in accordance with various disclosed embodiments. Note that althoughFIGS. 6-10depict structures corresponding to the method depicted inFIG. 11, the structures and the method are not limited to each other in any manner.

In Step110ofFIG. 11and referring toFIG. 6and, a semiconductor substrate200can be provided. The semiconductor substrate200can include a first region I′ and a second region II′. The first region I′ and the second region II′ can be adjacent to each other. A first gate structure201can be formed on the semiconductor substrate200in the first region I′ and a second gate structure211can be formed on the semiconductor substrate200in the second region II′.

The semiconductor substrate200can provide a platform for subsequent formation of the exemplary CMOS device. The semiconductor substrate200can be, e.g., a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, or other suitable substrates. The semiconductor substrate200can have a crystal orientation <110>, <100>, etc. The first region I′ and second region II′ can be used to form an NMOS transistor and a PMOS transistor, respectively, or vice versa.

The first region I′ and second region II′ can be isolated from each other by, e.g., a shallow trench isolation structure202. The shallow trench isolation structure202can be made of a material including, e.g., silicon oxide or other suitable materials. In one embodiment, the semiconductor substrate200can be a silicon substrate, the first region I′ can be used to form a PMOS transistor, and the second region II′ can be used to form an NMOS transistor.

The first gate structure201in the first region I′ can include a first gate dielectric layer203formed on the semiconductor substrate200and a first gate electrode layer205formed on the first gate dielectric layer203. The first gate dielectric layer203can be made of a material including, but not limited to, a silicon oxide, a high-K dielectric material, and/or other suitable materials. For example, the high-K dielectric material can include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium Hafnium oxide, etc. The first gate electrode layer205can be made of a material including, e.g., a polysilicon or a metal such as tungsten and/or aluminum.

In one embodiment, to protect the first gate electrode layer205, the first gate structure201can further include a protective layer207covering the first gate electrode layer205. The first protective layer207can be made of a material including, for example, silicon nitride, silicon oxynitride, silicon oxide, etc.

A first sidewall spacer209can be formed on the sidewall of each of the first gate dielectric layer203, the first gate electrode layer205, and the first protective layer207. The first sidewall spacer209can be made of a material including, for example, silicon nitride, silicon oxynitride, silicon oxide, etc. In some embodiments, materials used for the first protective layer207and the first sidewall spacer209can be different to facilitate a subsequent removal of the first protective layer207. For example, the first protective layer207can be made of silicon nitride, while the first sidewall spacer209can be made of silicon oxide. In other embodiments, the first protective layer207and the first sidewall spacer209can be made of a same material.

The second gate structure211in the second region II′ can include a second gate dielectric layer213formed on the semiconductor substrate200and a second gate electrode layer215formed on the second gate dielectric layer213. The second gate dielectric layer213can be made of a silicon oxide, a high-K dielectric material, and/or other suitable materials. For example, the high-K dielectric material can include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium Hafnium oxide, etc. The second gate electrode layer215can be made of a material including, for example, a polysilicon or a metal such as tungsten and/or aluminum.

In one embodiment, the second gate structure211can further include a second protective layer217covering the second gate electrode layer215. A second sidewall spacer219can be formed on the sidewall of each of the second gate dielectric layer213, the second gate electrode layer215, and the second protective layer217. Each of the second protective layer217and second sidewall spacer219can be made of a material including, e.g., silicon nitride, silicon oxynitride, or silicon oxide. In some embodiments, the second protective layer217and second sidewall spacer219can be made of a same material. In other embodiments, the second protective layer217and second sidewall spacer219can be made of a different material. For example, the second protective layer217is made of silicon nitride, while the second sidewall spacer219is made of silicon oxide.

In Step120ofFIG. 11and referring toFIG. 7, a first stress layer221can be formed on the semiconductor substrate200on both sides of each of the first gate structure201and the second gate structure211. The first stress layer221can be used to increase stress generated in the channel region of the second region II′.

The first stress layer221can be formed by a deposition process, e.g., a chemical vapor deposition, a selective epitaxial deposition, etc. In one embodiment, the first stress layer221can be formed using a selective epitaxial deposition process. For example, the selective epitaxial deposition can be performed at a temperature ranging from about 550° C. to about 800° C. under a pressure ranging from about 5 torr to about 20 torr. The selective epitaxial deposition can use: a SiH4flow rate ranging from about 30 sccm (standard cubic centimeter per minute) to about 300 sccm; a volume ratio of SiH4to SiH2Cl2of at least about 3:2; a HCl flow rate ranging from about 50 sccm to about 200 sccm, and a H2flow rate ranging from about 5 sccm to about 50 sccm. The first stress layer221can be selectively formed on surface of the semiconductor substrate200and is not formed on the first gate structure201and/or the second gate structure211. Accordingly, no subsequent removal steps are needed. In an exemplary embodiment, the selective epitaxial deposition can be used to form the first stress layer221including single crystal silicon.

In various embodiments, the first stress layer221can be made of a material depending on specific semiconductor devices to be formed in the second region II′. For example, when the second region II′ is used to form an NMOS transistor, the first stress layer221can be made of single crystal silicon carbide or single crystal silicon. When the second region II′ is used to form a PMOS transistor, the first stress layer221can be made of single crystal silicon germanium.

In one embodiment, the second region II′ can be used to form an NMOS transistor and the first stress layer221can be made of, e.g., silicon carbide. A portion of the first stress layer221in the first region I′ can be subsequently removed, and the remaining portion of the first stress layer221in the second region II′ can be used to increase tensile stress in the channel region to enhance carrier mobility of the subsequently-formed NMOS transistor.

The first stress layer221can have a thickness over the surface of the semiconductor substrate200ranging from about 200 Å to about 600 Å. A bottom surface of the first stress layer221can be flush with the surface of the semiconductor substrate200. However, in other embodiments, the first stress layer221can be formed in the semiconductor substrate200. For example, a shallow opening (not shown) can be formed in the semiconductor substrate200by an etching process to remove portions of the semiconductor material. The first stress layer can then be formed in the shallow opening.

The shallow opening can have a depth of about 1000 Å or less, i.e., a lower surface of the first stress layer221filled in the shallow opening can be about 1000 Å or less to the surface of the semiconductor substrate200. In other words, a lower surface of the first stress layer in the semiconductor substrate can be about 0 Å to about 1000 Å to the surface of the semiconductor substrate and/or an upper surface of the first stress layer can be about 200 Å to about 600 Å over the surface of the semiconductor substrate. In this manner, the stress generated in the channel region of the corresponding semiconductor device in the second region II′ can be increased. Device performance of the subsequently formed CMOS transistor can be improved.

The first stress layer221can thus be formed on the surface of the semiconductor substrate200and on the sides of the first gate structure201and the second gate structure211. Subsequently, a portion of the first stress layer221in one region can be removed, while remaining portion(s) of the first stress layer221can be retained in the other region. Therefore, a second stress layer can be formed on the one region after thefirst stress layer is removed from the first region I and only one mask is needed in such process in accordance with various embodiments. The manufacturing process can be significantly simplified.

In Step130ofFIG. 11and referring toFIG. 8, a barrier layer223can be formed to cover the second gate structure211and the first stress layer221in the second region II′ and to expose the first gate structure201and a portion of the first stress layer221in the first region I′.

The barrier layer223can protect the first stress layer221in the second region II' in subsequent etching process(s). The barrier layer223can be made of a material having an etching selectivity greater than the semiconductor substrate200. For example, the barrier layer223can be made of a material such as silicon dioxide or silicon nitride. In one embodiment, the barrier layer223can be made of silicon nitride. The barrier layer223can be used as a mask for a subsequent removing process performed in the first region I′. Depending on selection of the process parameters, the barrier layer223of silicon nitride can be used to increase stress generated in the channel region of semiconductor device(s) formed in the second region II′. Device performance can be enhanced.

The barrier layer223can be formed by, e.g., a plasma deposition process using a reaction gas including ammonia, nitrogen and/or silane. Among them, ammonia can be about 10% to about 15% by volume of the total reaction gas, nitrogen can be about 2% to about 6% by volume of the total reaction gas, and silane can be about 79 to about 88% by volume of the total reaction gas. The barrier layer223can be formed, e.g., under a reaction pressure ranging from about 0.08 Pa to about 0.2 Pa at a reaction temperature ranging from about 300° C. to about 400° C., and using a RF power ranging from about 50 watt to about 100 watt at a RF frequency ranging from about 10 mHz to about 20 mHz. The formed barrier layer223can be used to provide tensile stress to the subsequently-formed NMOS transistors.

In one embodiment, to ensure protection performance of the barrier layer223over the first stress layer221in the second region II′, the barrier layer223can have a thickness ranging from about 200 Å to about 500 Å. Other thickness may also be used.

The barrier layer223can be formed by a process including, for example, forming a thin barrier film (not shown) to cover the first gate structure201, the second gate structure211, and the semiconductor substrate200; forming a photoresist layer (not shown) to cover the thin barrier film in the second region II′ and to expose the first region I′; and using the photoresist layer as a mask to remove a portion of the thin barrier film in the first region I′ and to form the barrier layer223in the second region II′.

In Step140ofFIG. 11and referring toFIG. 9, the barrier layer223can be used as a mask to remove portion(s) of the first stress layer221in the first region I′ and to etch semiconductor substrate200to form a groove225, as depicted in Step150ofFIG. 11, on both sides of the first gate structure201in the first region I′.

The groove225can allow a second stress layer to be subsequently filled in such that the second stress layer can be formed close to the channel region to increase stress generated in the channel region of corresponding semiconductor device(s) formed in the first region I′. In various embodiments, the groove225formed in the first region I′ can have a cross-sectional shape including, for example, a U-shaped, sigma-shaped, polycrystalline-surface shaped, or any suitably shaped cross-section. In one embodiment, the groove225is sigma-shaped.

For example, a sigma-shaped groove can be formed at a temperature ranging from about 40° C. to about 60° C. using a power ranging from about 200 watts to about 400 watts at a bias voltage ranging from about 50 volts to about 200 volts. CF4and/or HBr can be used to etch the semiconductor substrate for about 10 seconds to about 20 seconds to form a bowl-shaped recess (not shown). This can be followed by a wet etching of the bowl-shaped recess with tetramethylammonium hydroxide (TMAH) solution having a volume concentration of from about 2% to about 20% for about 100 seconds to about 300 seconds at a temperature ranging from about 30° C. to about 60° C. A sigma-shaped groove can then be formed as shown inFIG. 9.

TMAH solution can provide high etching rate and is non-toxic, non-polluting, and easy to use. In addition, TMAH solution can have a high etching selectivity over different crystal orientations. For example, an etching rate in crystal orientation <100> and <110> can be faster than that in other orientations, for example, in direction <111>. Therefore, the formed groove225can be, e.g., sigma-shaped and can be close to the channel region in the first region I′ to further increase the stress generated in the channel region. In various embodiments, the sigma-shaped groove can have a depth ranging from about 400 Å to about 2000 Å in the semiconductor substrate200to provide suitable stress level in the channel region of the semiconductor device(s) to be formed in the first region I′.

In other embodiments where the above-mentioned shallow opening(s) (not shown) are formed in the semiconductor substrate200in the first and second regions and the first stress layer221is formed in these shallow opening(s), the groove225can be formed having a dimension at least the same as the corresponding shallow opening, e.g., larger than or equal to the corresponding shallow opening. This can allow the first stress layer221to be completely removed from the first region I′ without leaving any residues in the first region I′ and without affecting the stress generated in the channel region of the subsequently-formed semiconductor devices.

In Step160ofFIG. 11and referring toFIG. 10, a second stress layer227can be formed in the groove225in the first region I′. The second stress layer227can be used to increase stress generated in the channel region of the semiconductor device(s) located in the first region I′. The second stress layer227can be made of a material depending on specific semiconductor device(s) to be formed in the first region I′. When the first region I′ is used to form a PMOS transistor, materials used for the second stress layer227can include, e.g., silicon germanium. When the first region I′ is used to form an NMOS transistor, materials used for the second stress layer227can include, e.g., silicon carbide or silicon.

In an exemplary embodiment where the second stress layer227is made of silicon germanium, the second stress layer227can include a germanium content (or concentration) distribution in the second stress layer227. For example, the germanium content can be gradually increased from an upper surface and/or a lower surface of the second stress layer227towards/to a middle portion of the second stress layer227to generate a large stress in adjacent channel region. In one embodiment, the upper surface of the second stress layer227can be about 200 Å to about 400 Å over the surface of the semiconductor substrate200, e.g., to form a raised SiGe, while the lower surface of the second stress layer227can be about 400 Å to about 2000 Å under the surface of the semiconductor substrate200.

The second stress layer227can be formed by a deposition process, e.g., a chemical vapor deposition, a selective epitaxial deposition, etc. In one embodiment, the second stress layer227can be formed using a selective epitaxial deposition process, for example, at a temperature ranging from about 550° C. to about 800° C. under a pressure ranging from about 5 torr to about 20 torr. The selective epitaxial deposition can use a SiH4flow rate ranging from about 30 sccm (standard cubic centimeter per minute) to about 300 sccm; a volume ratio of SiH4to SiH2Cl2of at least about 3:2; a GeH4flow rate ranging from about 50 sccm to about 500 sccm, a HCl flow rate ranging from about 50 sccm to about 200 sccm, and a H2flow rate ranging from about 5 sccm to about 50 sccm.

In other embodiments, to further increase the stress generated in the channel region of the semiconductor devices formed subsequently in the first region I′, a single crystal silicon layer (not shown) can be formed to cover the second stress layer227. As crystal lattice structures of the single crystal silicon layer and the second stress layer227are different, more stress can be generated in the second stress layer227, which may further increase the stress generated in the channel region of corresponding semiconductor devices.

The second stress layer227can be used as source/drain regions of the subsequently-formed semiconductor devices in the first region I′. The second stress layer227can be doped with suitable impurity ions.

Note that although the CMOS transistor depicted inFIGS. 6-10is illustrated having planar structures, one of ordinary skill in the art would appreciate that CMOS transistors, for example, a fin field-effect transistor (FinFET), having three dimensional (3D) structures can be encompassed in accordance with various disclosed embodiments.

In this manner, an exemplary CMOS transistor can be formed by first forming a first stress layer, e.g., using a selective epitaxial deposition process, in and/or on the semiconductor substrate in a first region and a second region. This can be followed by forming a barrier layer on surface of the first stress layer in the second region. The barrier layer can be used as a mask to etch and remove a portion of the first stress layer from the first region, while the remaining portion of the first stress layer in the second region can be retained and used in the second region. The semiconductor substrate in the first region can then be etched to form a groove in the semiconductor substrate. A second stress layer can then be formed in the groove. As disclosed, only one barrier layer is needed for forming the first stress layer (e.g., in and/or on the semiconductor substrate in the first region) and for forming the second stress layer (e.g., in and/or on the semiconductor substrate in the second region). The manufacturing process is therefore significantly simplified. In addition, the formed CMOS transistors can provide desired large stress generated in the channel region to increase carrier mobility and provide stable device performance.

During fabrication of the CMOS transistor, the first stress layer can be formed and used to cover the surface of the semiconductor substrate on both sides of each of the first gate structure and second gate structure. A barrier layer can be formed to cover the first stress layer and the second gate structure in the second region. The barrier layer can also be used as a mask to remove a portion of the first stress layer from the first region while the remaining portion of the first stress layer in the second region can be retained to increase the stress generated in the channel region of the semiconductor substrate in the second region. The barrier layer can be used as a mask to etch the semiconductor substrate in the first region to form groove(s), where the second stress layer can be formed to increase the stress generated in the channel region of the semiconductor devices in the first region. In various embodiments, the first stress layer can be formed in the semiconductor substrate. For example, a shallow opening can be formed in the semiconductor substrate by an etching process and the first stress layer can be formed in the shallow opening. The first stress layer formed in the semiconductor substrate can then be close to the channel region of the semiconductor devices in the second region to further increase the stress in the channel region of the semiconductor devices. Carrier mobility and device performance can thus be enhanced.

Other applications, advantages, alternations, modifications, or equivalents to the disclosed embodiments are obvious to those skilled in the art.