Semiconductor memory device with multiple sub-memory cell arrays and memory system including same

A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2013-0074016 filed on Jun. 26, 2013, the subject matter of which is hereby incorporated by reference.

BACKGROUND

The inventive concept relates generally to semiconductor memory devices and memory systems. More particularly, the inventive concept relates to semiconductor memory devices having different constituent memory cell arrays that are accessed by a processor according to certain data characteristics.

Many contemporary memory systems include an increasing number of semiconductor memory devices. Quite often, different memory types, each type being characterized by respective performance capabilities, are used in memory systems in order to accommodate different data types and data requirements. This increasing complexity notwithstanding, contemporary memory systems must meet ever increasing demands for data access speed and data accuracy. Accordingly, the demands placed upon memory system and memory device designers to provide memory systems capable of providing efficient data access of data having different characteristics remain constant.

SUMMARY

According to certain embodiments of the inventive concept, there is provided a semiconductor memory device comprising; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

According to certain other embodiments of the inventive concept, there is provided a memory system comprising; a semiconductor memory device and a memory controller configured to control operation of the semiconductor memory device, wherein the semiconductor memory device comprises; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

DETAILED DESCRIPTION OF EMBODIMENTS

The inventive concept will now be described in some additional detail with reference to the accompanying drawings. This inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements and features.

FIG. 1is a general block diagram of an electronic system1according to certain embodiments of the inventive concept. The electronic system1includes a host20and a memory system30, where the memory system30includes a memory controller200and a memory module10. Those skilled in the art will appreciate that the electronic system1may be implemented within a mobile device, smart phone, notebook, laptop or desktop computer, appliance, television, display, etc.

The host20may communicate with the memory system30using one or more interface protocol(s), such as the peripheral component interconnect express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), serial attached SCSI (SAS), universal serial bus (USB), multimedia card (MMC), enhanced small disk interface (ESDI), integrated drive electronics (IDE), etc.

The memory controller200may be used to control the overall operation of the memory system30, and in particular the data and information exchanges between the host20and memory module10.

The memory module10is assumed to include a number of semiconductor memory devices100,100′, and100″. For purposes of the description that follows, it is further assumed that the semiconductor memory devices100,100′, and100″ are Dynamic Random Access Memory (DRAM) including a memory cell array (not shown) configured from a plurality of memory cells arranged in a matrix of rows and columns Of course, others types of semiconductor memory might be used in certain embodiments of the inventive concept in place of, or in addition to the illustrated DRAM.

However, assuming the semiconductor memory devices100,100′, and100″ are respective DRAM, the memory module10may be configured as an un-buffered dual in-line memory module (UDIMM), registered DIMM (RDIMM), load reduced DIMM (LR-DIMM), etc. In certain embodiments, the memory module10may further include one or more buffer memor(ies) or register(s) as will be conventionally appreciated.

FIG. 2is a block diagram further illustrating in one embodiment (30′) the memory system30ofFIG. 1. Here, only a single memory device100is illustrated in associated with the memory controller200in order to avoid confusing repetition of description. Here, memory controller200may provide write data or receive read data (DQ), and provide one or more command(s) (CMD), and/or one or more address(es) (ADD) to the semiconductor memory device100using a competent interface protocol. In response to the one or more command(s) provided by the memory controller200, the memory device100will execute one or more operation(s) related to the identified data (DQ) and/or address(es) (ADD) (e.g., a read operation, a write operation, a data refresh operation, etc.).

FIG. 3is a block diagram further illustrating the semiconductor memory device100ofFIGS. 1 and 2according to certain embodiments of the inventive concept. Referring toFIG. 3, the memory device100includes a memory cell array110, a row decoder120, a sense amplifier130, a column decoder140, a refresh control circuit150, a command decoder160, a mode register set/extended mode register set (MRS/EMRS) circuit170, and address buffer180, and a data input/output (I/O) circuit190.

The memory cell array110includes a large number of memory cells arranged at the respective intersections of columnar bit lines and row-wise word lines. Consistent with certain embodiments of the inventive concept, the memory cell array110include at least two “sub-memory cell arrays”, wherein each sub-memory cell array is operationally associated with one or more data types—that is data having one or more designated characteristics. In this regard, each sub-memory cell array may include hetero memory cells having different structures or homo memory cells having the same structure.

The sense amplifier130may be used to sense and amplify “read data” retrieved from, or to temporarily store “write data” being written to identified memory cells of the memory cell array110. Consistent with the foregoing, the sense amplifier130will include at least two sense amplifier circuits, each respectively and operationally associated with one of the at least two sub-memory cell arrays. Exemplary structures for the memory cell array110and sense amplifier130are set forth in relation toFIGS. 4, 5, 6, 7, 8, 9 and 10(FIGS. 4 through 10) hereafter.

Write data received via the data I/O circuit190is written to locations in the memory cell array110designated by an associated address (ADD). Read data retrieved from the memory cell array110is also identified by an associated address signal (ADD) and is provided to external circuitry, such as the memory controller200, via the data I/O circuit190. In this regard, various address(es) received from the memory controller200may be temporarily stored in the address buffer180.

The row decoder120may be used to decode a row address portion of an address signal provided by the address buffer180in order to select a word line connected to a “target memory cell” to which write data will be written, or from which read data will be read. That is, the row decoder120may be used to decode a row address provided by the address buffer180and enable a corresponding word line during a read/write operation. The row decoder120may also be used to select a word line to be refreshed based on a row address received from the refresh control circuit150.

In similar manner, the column decoder140may be used to decode a column address portion of an address signal received from the address buffer180in order to select a bit line connected to the target memory cell.

The command decoder160receives the one or more command(s) from the memory controller200, decodes the command(s), and internally generates one or more decoded command signal(s), such as an active signal, a read signal, a write signal, a refresh signal, etc. The refresh control circuit150receives the refresh signal from the command decoder160and outputs an internal row address to the row decoder120so that the memory cells connected to one or more selected word lines may be refreshed.

The MRS/EMRS circuit170may be used to set an internal mode register in response to an MRS command. In this manner, different operating modes (often respectively related to one of a number of different operations) may be operatively defined within the memory device100.

Although not shown inFIG. 3, those skilled in the art will recognize that the memory device100may also include a clock circuit capable of generating one or more clock signal(s), and a voltage generator capable of receiving at least one external power supply voltage and generating a number of internal power supply voltage(s).

FIG. 4is a block diagram further illustrating in one example (300) the memory device100ofFIGS. 1, 2 and 3. Here, the memory device300includes a first sub-memory cell array311that is used to store “first data” having a first characteristic, and a second sub-memory cell array313that used to store “second data” having a second characteristic different from the first characteristic. Those skilled in the art will understand that many different data “characteristics” may be used, for example, to indicate the relative importance of the corresponding data or the presumed (or verified) reliability of the corresponding data. Other characteristics indicate a particular quantitative nature of the corresponding data, such as random data, consecutive data, data of a certain size, etc. Still other characteristics indicate data properties associated with computational use, such data from a particular source, or data intended for a particular destination, etc. Still other characteristics indicate a particular quality of memory cell chosen to store the identified data, such as access latency, refresh properties, etc.

The memory device300also includes a bit line sense amplifier (BLSA)331and a first peripheral circuit351operatively associated with the first sub-memory cell array311, as well as an offset cancelling (OFC) BLSA333and a second peripheral circuit353operatively associated with the second sub-memory cell array313. Thus, the BLSA331may be said to access the first data from the first sub-memory cell array using a first data access approach (or technique), while the OFC BLSA333may be said to access the second data from the second sub-memory cell array using a second data access approach different from the first data access approach.

In certain embodiments, the first peripheral circuit351comprises a first voltage generator (VG1)352and the second peripheral circuit353comprises a second voltage generator (VG2)354, wherein the first and second voltage generators are respectively configured to receive an external power supply voltage and generate different first and second core voltages, respectively applied to the first and second sub-memory cell arrays and their associated first and second sense amplifiers.

In certain embodiments of the inventive concept, each one of the first peripheral circuit351and second peripheral circuit353may generally include the elements described in relation toFIG. 3that are used to control the operation of the memory device100, except for the sense amplifier130. The first peripheral circuit351and second peripheral circuit353are separately illustrated inFIG. 4for clarity of description. However, these circuits may share one or more physical circuits and/or logic blocks.

The first peripheral circuit351is used to generate and provide various control signals and/or related voltages necessary to control the operation of the first sub-memory cell array311and BLSA331, while the second peripheral circuit353is used to generate and provide various control signals and/or related voltages necessary to control the operation of the second sub-memory cell array313and OFC BLSA333. Thus, the BLSA331amplifies a sensed voltage on a selected bit line in order to read data from a target memory cell, while the OFC BLSA333amplifies a sensed voltage on a selected bit line while also compensating for an offset voltage between an input terminal and an output terminal in order to read data from a target memory cell. In this manner, the operation of the OFC BLSA333, as compared with similar operation of the BLSA331, will reduce overall power consumption by the memory device300. Further, the operation of particular sense amplifier circuitry (e.g., BLSA331verses OFC BLSA333) may be decided on the basis of one or more characteristic(s) of the data being read, wherein the data having been differentiated according to the one or more characteristics was previously stored in one of the two sub-memory cell arrays using either the first peripheral circuit351or second peripheral circuit353.

FIG. 5is a block diagram further illustrating in another example (300′) the memory device100ofFIGS. 1, 2 and 3. The memory device300′ includes the first sub-memory cell array311and BLSA331associated with the first peripheral circuit351. However, memory device300′ also includes a third sub-memory cell array315that is used to stores data having a third characteristic different from the first characteristic, and a direct sense amplifier (SA)335, collectively associated with a third peripheral circuit355that may be used to particularly control the operation of the third sub-memory cell array315.

In this context, it is assumed that the direct SA335is capable of directly communicating data sensed from a selected bit line directly to a data I/O line. Thus, unlike the BLSA331which restores the data read from a target memory cell, the direct SA335only reads/write data from/to the target memory cell. Accordingly, data may be read from and written to a target memory cell of the third sub-memory cell array315using the direct SA335at speeds greater than those provided by the BLSA331and the memory cells of the first sub-memory cell array311.

The semiconductor memory devices300and300′ described above in relation toFIGS. 4 and 5are assumed to differentiate write data according to only a single characteristic (e.g., read operation power consumption (FIG. 4) or read/write speed (FIG. 5)). However, those skilled in the art will recognize that other embodiments of the inventive concept will be capable of differentially writing data to different sub-memory cell arrays or differentially reading data from different sub-memory cell arrays using different types of data access circuitry (e.g., sense amplifiers) in accordance with two or more characteristics. Further, more than two different types of sub-memory cell array and associated access circuitry may be implemented within a single semiconductor memory device.

FIG. 6is a circuit diagram further illustrating in one example (331-1) the BLSA331ofFIG. 4. The BLSA331-1is cross-coupled between a pair of bit lines BL and BLB of the first sub-memory cell array311, and includes P-channel metal oxide semiconductor (PMOS) transistors MP1and MP2connected to a sense amplifier voltage VintA, the bit line BL, and the complementary bit line BLB. The BLSA331-1also includes N-channel MOS (NMOS) transistors MN1and MN2connected to the bit line BL, the complementary bit line BLB, and a power supply voltage VSS.

FIG. 7is a circuit diagram further illustrating in one example (333-1) the OFC BLSA333ofFIG. 4. The OFC BLSA333-1is connected between the bit line BL and the complementary bit line BLB, and includes first and second PMOS transistors MP21and MP22and first through sixth NMOS transistors MN21, MN22, MN23, MN24, MN25, and MN26. The OFC BLSA333-1amplifies a sensing voltage received from the second sub-memory cell array313through the bit line BL and the complementary bit line BLB while compensating for an offset voltage between an input terminal and an output terminal of the OFC BLSA333-1in response to a first switching control signal SN1and a second switching control signal SN2.

FIG. 8is a circuit diagram further illustrating in one example (335-1) the direct SA335ofFIG. 5. The direct SA335-1corresponding to a single pair of bit lines BL and BLB included in the third sub-memory cell array315connects the bit line BL to a second data I/O line IOB through a transistor MN33, and connects complementary bit line BLB to a first data I/O line IO through a transistor MN32. In addition, the bit line BL is connected to the first data I/O line IO through a transistor MN34and the complementary bit line BLB is connected to the second data I/O line IOB through a transistor MN35.

During a read operation directed to a target memory cell of the third sub-memory cell array315, a logically “high” read enable signal CSLR is applied to turn ON a transistor MN31and logically “low” write enable signal CSLW is applied to turn OFF the transistors MN34and MN35. As a result, data apparent on the bit lines BL and BLB is directly output to the first and second data I/O lines IO and IOB.

During a write operation directed to a target memory cell of the third sub-memory cell array315, a low read enable signal CSLR is applied to turn OFF the transistor MN31and a high write enable signal CSLW is applied to turn ON the transistors MN34and MN35. As a result, data is provided to the pair of the bit lines BL and BLB through the first and second data I/O lines IO and IOB.

FIG. 9is a block diagram further illustrating in another example (400) the memory device100ofFIGS. 1, 2 and 3.FIG. 10is a circuit diagram further illustrating how a voltage may be applied to the memory cell array and sense amplifier ofFIG. 9. Only single memory cell410and a single BLSA430corresponding to the memory cell410are illustrated inFIG. 10.

The memory device400includes first and second sub-memory cell arrays411and413that are respectively used to store data having given characteristic(s), and first and second BLSAs431and433that may be respectively used in operative association with the first and second sub-memory cell arrays411and413. The memory device400also includes a first peripheral circuit451operatively associated with the first sub-memory cell array411and the first BLSA431, and a second peripheral circuit453operatively associated with the second sub-memory cell array413and the second BLSA433.

Each of the first and second peripheral circuits451and453may include a voltage generator (not shown) that receives an external power supply voltage and generates core voltages applied to the sub-memory cell array411or413and the corresponding BLSA431or433. The voltage generator included in the first peripheral circuit451may apply a first core voltage set to the first sub-memory cell array411and the first BLSA431. The voltage generator included in the second peripheral circuit453may apply a second core voltage set to the second sub-memory cell array413and the second BLSA433.

The core voltages include a word line voltage VPP, an array power supply voltage VSS, and the sense amplifier voltage VintA, as shown inFIG. 10. The core voltages may include all internal voltages used for the operation of the semiconductor memory device400.

The voltage generator included in each of the first and second peripheral circuits451and453generates a different core voltage according to the characteristic of data corresponding to a memory cell based on the control of the memory controller200, thereby controlling tRCD.

FIG. 11is a timing chart illustrating one method of controlling an AC parameter using any one of the various sense amplifiers described in relation toFIGS. 4 through 10.

When an MRS command (MC) is received from the memory controller200, the MRS/EMRS circuit170sets at least one internal mode register in the memory device100. Thereafter, an active command (ACT) is applied to activate a selected word line, and then a write command (WR) is applied to perform a write operation.

After a selected bit line is activated in response to the write command (WR), a precharge command (PRE) is applied to perform a precharge operation. Thereafter, the active command (ACT) is applied to activate the selected word line, and then a read command (RD) is applied to perform a read operation.

The period between application of the active command (ACT) and application of the write command (WR) may be referred to as “tRCD_WR”. The period between completion of the write operation and application of the precharge command (PRE) may be referred to as “tWR”. The period between application of the precharge command (PRE) and application of the active command (ACT) may be referred to as “tRP”, and the period between application of the active command (ACT) and application of the read command (RD) may be referred to as “tRCD_RD”.

In these context, the timing of certain “AC parameters” such as tRCD_WR, tWR, tRP, and tRCD_RD may be particularly controlled by the memory devices300,300′, and400. For instance, the clock cycle of tRCD_WR and tRCD_RD and the clock cycle of tWR may be reduced by increasing the word line voltage VPP, as illustrated inFIG. 10. The clock cycle of tRCD_WR and tRCD_RD may be reduced while the clock cycle of tWR may be extended by increasing the sense amplifier voltage VintA.

Certain AC parameters understood by those skilled in the art, such as tRCD_WR, tWR, tRP, and tRCD_RD described above, have been defined in a standardized manner by the Joint Electron Device Engineering Council (JEDEC). Related publications may be obtained from JEDEC describing such parameters. However, in addition to certain standardized AC parameters, application of system performance specific AC parameters for each one of a number of sub-memory cell arrays may be defined in various embodiments of the inventive concept.

FIG. 12is a timing chart illustrating operation of a sense amplifier like the ones described in relation toFIGS. 4 through 10according to certain embodiments of the inventive concept. A case is assumed wherein a first command CMD1and a second command CMD2are provided by the memory controller200.

Referring toFIG. 12, tRCD_RD1, i.e., tRCD corresponding to the first command CMD1is longer than tRCD_RD2, i.e., tRCD corresponding to the second command CMD2in the read operation of the semiconductor memory device. The first command CMD1may correspond to the first sub-memory cell array311and the BLSA331and the second command CMD2may correspond to the third sub-memory cell array315and the direct SA335.

As described above, the direct SA335performs only the read or write operation of data corresponding to a memory cell, and therefore, the memory cells included in the third sub-memory cell array315may have more improved tRCD than the memory cells included in the first sub-memory cell array311. In other words, data stored in the memory cells of the third sub-memory cell array315may be read out faster than data stored in the memory cells of the first sub-memory cell array311.

FIG. 13is a block diagram further illustrating in another example (500) the semiconductor memory device100ofFIGS. 1, 2 and 3. The memory device500may selectively include an error correction code (ECC) block as operatively associated with each one of a number of sub-memory cell arrays510,531,551, and571. The semiconductor memory device500also includes peripheral circuits515,535,555, and575respectively corresponding to the sub-memory cell arrays510,531,551, and571.

Based on one or more data characteristic(s), data that does not need application of an ECC function may be stored in the first sub-memory cell array510, while other data variously requiring one of several different ECC functions may be stored in the second through fourth sub-memory cell arrays531,551, and571. The memory controller200provide externally provided write data to one of the first through fourth sub-memory cell arrays510,531,551, and571according to the one or more data characteristic(s). In order to accomplished this select data writing functionality, the memory controller200may detect and store the configuration of the semiconductor memory device500upon memory system power-up.

As shown inFIG. 13, the second through fourth sub-memory cell arrays531,551, and571respectively include first through third ECC blocks533,553, and573which may include memory cells designated to store “parity data” corresponding to (e.g., derived from) “normal data” stored in the second through fourth sub-memory cell arrays531,551, and571. Here, each of the second through fourth peripheral circuits535,555, and575may include an ECC engine that performs error detection and/or correction on the normal read/write data based on the parity data stored in the ECC block533,553, or573. Conventionally understood ECC engines include, as examples, those that use a Hamming code, a Bose-Chaudhuri-Hocquenghen (BCH) code, or a Reed-Solomon (RS) code. However, the ECC circuitry incorporated by various embodiments of the invention concept is not restricted to these examples.

Thus, when data requires a fast operation, the memory controller200may control the semiconductor memory device500to store the data in the first sub-memory cell array510. In addition, when data is one that is frequently accessed, the memory controller200may control the semiconductor memory device500to store the data in one of the second through fourth sub-memory cell arrays531,551, and571. Accordingly, memory cells in the first sub-memory cell array510may have a higher refresh frequency than memory cells in the second through fourth sub-memory cell arrays531,551, and571. It follows that when the semiconductor memory device100is differently configured and differently operated in view of one or more data characteristic(s) for the data being stored, overall memory system performance increases.

As described above, according to certain embodiments of the inventive concept, a semiconductor memory device includes multiple sub-memory cell arrays, each being used to store data having different characteristic(s) to thereby increase memory system performance while potentially decreasing power consumption. It should be noted that a constituent “unitary” memory cell array (i.e., a physically bounded matrix of memory cells) may be logically divided into two or more sub-memory cell arrays, where each sub-memory cell array is thereafter functionally operated in a manner consistent with one or more different data characteristics. Alternately or additionally, physically separate sub-memory cell arrays may be provided in a single semiconductor memory device. Similarly, it should be noted that physically separate first and second peripheral circuits may be operatively associated with two or more sub-memory cell arrays. Alternately, the first and second peripheral circuits may share one or more resources (e.g., register, memory, voltage generator, clock circuitry, power supply, etc.).

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in forms and details may be made therein without departing from the scope of the inventive concept as defined by the following claims.