Methods and apparatus for CMOS sensors

Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.

BACKGROUND

Complementary metal-oxide semiconductor (CMOS) sensors are gaining in popularity over traditional charged-coupled devices (CCDs). A CMOS sensor typically comprises an array of pixels formed in a pixel region and logic circuits in a logic region on the sensor. A pixel region may comprise a light-sensitive CMOS circuit to convert photons into electrons. The light-sensitive CMOS circuit may comprise a photo-sensitive element, such as a photo-diode, formed in a silicon substrate. As the photo-sensitive element is exposed to light, an electrical charge is induced in the photo-sensitive element. Each pixel may generate electrons proportional to the amount of light that falls on the pixel when light is incident on the pixel from a subject scene. The electrons are converted into a voltage signal in the pixel region and further transformed into a digital signal and processed by logic circuits in the logic region on the sensor.

In addition to the photo-sensitive element, the pixel region may comprise a plurality of transistors such as a transfer transistor, a reset transistor, a source follower transistor, or a select transistor, connected to the photo-sensitive element. The logic region may comprise a plurality of transistors as well. A transistor comprises a gate made of electrically conductive materials surrounded by insulative materials such as spacers alongside the gate to insulate the gate from other conductive materials. Various features of a transistor such as the gate and the spacer may be made using photolithography techniques, where photoresist materials may be deposited and patterned to produce the intended features.

With the increasing shrinkage of the sizes of the devices such as the gates of the transistors, the thickness of the photoresist materials used in the photolithography process may be reduced as well. Photoresist materials with reduced thickness can cause damages to spacers of transistors in a pixel region during the etching process after the photoresist materials have been patterned. New methods and apparatus are needed to reduce damages to spacers of transistors in a pixel region, which can efficiently reduce the pixel width, while improving dark current and white pixel problems for the pixels.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present disclosure discloses methods and apparatus for a sensor. According to the embodiments, an oxide layer is formed on a substrate, covering a pixel region and a logic region of the substrate. A spacer layer is formed on the oxide layer, and a buffer layer is formed on the spacer layer. A photoresist layer is formed on the buffer layer over the pixel region, wherein the photoresist layer has an opening exposing a first part of the buffer layer. The photoresist layer may be of insufficient thickness in current technology due to the shrinking sizes of the devices. The buffer layer under the photoresist layer can reduce the damages to the spacer layer under the buffer layer from etchings performed subsequently. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the exposed first part of the spacer layer, the remaining buffer layer over a second part of the spacer layer, and partially remove the second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end. Such shaped spacer layer can efficiently reduce the pixel width for the sensor.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.

FIG. 1illustrates a cross-sectional view of a sensor100comprising a pixel region200and a logic region300. The sensor100may comprise a grid or array of pixels in the pixel region200. The pixel region200and the logic region300are formed in a substrate102. A first area101is formed in the substrate within the pixel region200. A first source/drain area104and a second source/drain area104are formed within the substrate102in the logic region300. The logic region300further comprises a gate106formed above a channel between the first source/drain area104and the second source/drain area104. The gate106, the first source/drain area104, and the second source/drain area104form a transistor in the logic region300. An oxide layer103is formed on the substrate102, covering the first area101within the pixel region200, and also covering the gate106within the logic region300. A spacer layer105is formed on the oxide layer103over the pixel region200and the logic region300. A buffer layer107is formed on the spacer layer105. Finally, a photoresist layer109is formed on the buffer layer107over the pixel region200, wherein the photoresist layer109has an opening111exposing a first part121of the buffer layer107over the first area101.

The substrate102may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. The substrate102may be doped with a p-type dopant, such as boron, aluminum, gallium, or the like, although the substrate may alternatively be doped with an n-type dopant, as is known in the art.

The substrate102may comprise a plurality of isolation areas, which will be shown inFIG. 6, to separate and isolate various devices formed on the substrate102, and also to separate the pixel region200from the logic region300of a sensor. The isolation areas may be shallow trench isolations generally formed by etching the substrate102to form a trench and filling the trench with dielectric material as is known in the art.

The substrate102may comprise a photo-sensitive element in the pixel region200. The photo-sensitive element may be simply referred as a photo-diode, which may generate a signal related to the intensity or brightness of light that impinges on the photo-sensitive element. The photo-sensitive element may be connected to a plurality of transistors such as a transfer transistor, a reset transistor, a source follower transistor, or a select transistor, which will be shown inFIG. 6. The substrate102may comprises a first region101within the substrate102. The first region101may be a floating node in the pixel region200, or a part of some other devices.

The substrate102may comprise a plurality of active or passive devices, such as a plurality of transistors. One such transistor is shown inFIG. 1. The substrate102comprises a first source/drain area104and a second source/drain area104within the substrate102in the logic region300. The logic region300further comprises a gate106formed above a channel between the first source/drain area104and the second source/drain area104. The gate106, the first source/drain area104, and the second source/drain area104form a transistor in the logic region300. Other transistors may be formed in the pixel region200as well, not shown.

An oxide layer103is formed on the substrate102, covering the first area101within the pixel region200, and covering the gate106within the logic region300. The oxide layer103may comprise tetraethylorthosilicate (TEOS) silicon oxide thin film, which may be deposited using plasma enhanced chemical vapor deposition (PECVD) method or other suitable methods, under the pressure around 1 Torr, and temperature around 375° C., or other suitable environments. The oxide layer103may have a thickness in a range from about 300 to about 500 Angstroms(Å).

A spacer layer105is formed on the oxide layer103. The spacer layer105may be on the oxide layer103in both the pixel region200and the logic region300. The spacer layer105may cover the side and the top of the gate106in the logic region300. The spacer layer105may comprise silicon nitride material, and formed by chemical vapor deposition, and with an exemplary thickness from about 300 to about 500 Angstroms(Å).

A buffer layer107is formed on the spacer layer105. The buffer layer107may be formed with similar material as the oxide layer103. The buffer layer107may comprise tetraethylorthosilicate (TEOS) silicon oxide thin film, which may be deposited using plasma enhanced chemical vapor deposition (PECVD) method or other suitable methods, under the pressure around 1 Torr, and temperature around 375° C., or other suitable environments. The buffer layer107may have a thickness in a range from about 300 to about 500 Angstroms(Å).

A photoresist layer109is formed on the buffer layer107over the pixel region200. The photoresist layer109has an opening111exposing a first part121of the buffer layer107over the first area101. The photoresist layer109may comprise benzene-based polymers or other similar materials. The formation methods include spin coating or other commonly used methods. The thickness of photoresist layer109may be between about 5 μm and about 200 μm. The dimensions recited throughout the description are merely examples, and will change with the down-scaling of integrated circuits. The opening111of the photoresist layer109may be formed using photolithography techniques.

As illustrated inFIG. 2, the first part121of the buffer layer107shown inFIG. 1may be removed by a first etching, to expose a first part123of the spacer layer105over the first area101, while leaving a remaining part of the buffer layer107covered by the photoresist layer109intact. The first etching may also remove the buffer layer107over the logic region300, to expose the spacer layer105over the first gate106. The first etching may be a wet etching. The wet etching may be performed by using wet etching solutions containing an oxidizing agent and a complex agent. In addition, the etching solutions may optionally include one or more pH adjustors. The sensor100may be in contact with the wet etching solution, including but not limited to by spraying the etching solution on the sensor100, or by immersing the sensor100into the etching solution.

As illustrated inFIG. 3, the photoresist layer109may be stripped from the pixel region200. After the stripping, second etching is performed on the remaining part of the buffer layer107over the pixel region200. The second etching removes the first part123of the spacer layer105to expose a first part125of the oxide layer103on the first area101. The second etching may also remove the spacer layer105over the first gate106to expose the oxide layer103on the first gate106, while keeping the spacer layer105around the first gate106. The second etching may be a dry etching, performed using chemicals such as, CF4, or CHF3. Any existing etching technology or future developed etching technology may be used.

The remaining part of the buffer layer107over the pixel region200acts as a buffer for the second etching process, to reduce the first part123of the spacer layer105been removed by the second etching. The reaming part of the spacer layer105has a higher remaining height compared to the result if the second etching would be performed on the spacer layer105without the buffer layer107. Similarly, the first part123of the spacer layer105been removed has a smaller width compared to the first part123would have been removed without the buffer layer107. The remaining part of the spacer layer105comprises a first end127over one side of the first area101, and a second end over another side of the first area101. As illustrated inFIG. 3, the first end127may have a shape substantially similar to a triangle, a height H of the first end127may be in a substantially same range as a length L of the first end127. The larger remaining part of the spacer layer105can efficiently reduce the pixel width, while improving dark current and white pixel problems for the pixels.

As illustrated inFIG. 4, the first part125of the oxide layer103may be removed by a third etching, to expose the first area101. The third etching may also remove the oxide layer103on the first gate106to expose the first gate106. The third etching may be a wet etching. The wet etching may be done by using wet etching solutions containing an oxidizing agent and a complex agent. In addition, the etching solutions may optionally include one or more pH adjustors. The sensor100may be in contact with the wet etching solution, including but not limited to by spraying the etching solution on the sensor100, or by immersing the sensor100into the etching solution.

As illustrated inFIG. 5, a doped area131may be formed within the exposed first area101. The doped area131may be a p+ type doped area formed by doping with boron or BF2, for example. In one embodiment, boron is implanted using 500 eV-20 KeV, of energy and a dopant concentration of 5e14 ions/cm2to 5e16 ions/cm2. Other implant energies and dopant concentrations may also be used, depending upon specific desired device characteristics and other design considerations. The doped area131may be done during an insitu doping process.

As illustrated inFIG. 6, an inter-layer dielectric (ILD) layer230may be formed on the spacer layer105and in contact with the first area101and the doped area131. A contact231may be formed through the ILD layer230and in contact with the first area101and/or the doped area131. The ILD layer230may comprise a material such as boron phosphorous silicate glass (BPSG), although any suitable dielectrics may be used for either layer. Contacts231may be formed through the ILD layer230with suitable photolithography and etching techniques. The contacts231may comprise a barrier/adhesion layer, not shown, to prevent diffusion and provide better adhesion for the contacts231.

As illustrated inFIG. 6, the substrate102may further comprise a photo-sensitive element297within the pixel region200. The first area101may be a floating node, and a transfer transistor299with a second gate287is above a channel between the floating node101and the photo-sensitive element297. The substrate210may comprise a plurality of isolation areas294to separate and isolate various devices formed on the substrate210, and also to separate the pixel regions200from other logic regions of the sensor.

The photosensitive element297may be a pinned photodiode, comprising a p-type doped region283formed in the substrate102. It also may comprise a heavily doped n-type region281(referred to as the pinned layer) formed on the surface of the p-type doped region283to form a n-p-n junction. As one of ordinary skill in the art will recognize, the pinned layer photodiode described above is merely one type of photosensitive diode297that may be used in the embodiments. For example, a non-pinned layer photodiode, partially pinned photodiode, photogate, or photocapacitor, may alternatively be used. Any suitable photodiode may be utilized with the embodiments, and all of these photodiodes are intended to be included within the scope of the embodiments.

The substrate210may comprise a plurality of isolation areas294to separate and isolate various devices formed on the substrate210, and also to separate the pixel region200from other logic regions of the sensor. The isolation areas294may be shallow trench isolations generally formed by etching the substrate210to form a trench and filling the trench with dielectric material as is known in the art. Optionally, an oxide liner may be formed along the sidewalls of the isolation areas294.

A transfer transistor299having a transfer gate287is used to transfer the signal output by the photodiode297to the floating node101, which may further be connected to other transistors such as an amplification transistor through the contact231. The transfer gate287may be connected to a contact231as well. In operation, during an integration period (also referred to as an exposure or accumulation period), the photodiode297generates charge (in response to incident light) that is held in the n− layer281of the photodiode297. After the integration period, the transfer gate287is turned on to transfer the charge held in the n− layer281to the floating node101. After the signal has been transferred to the floating node101, the transfer gate287is turned off again for the start of a subsequent integration period. The signal on the floating node101may then be used to modulate the amplification transistor, which is not shown.

A method of forming a sensor is disclosed. An oxide layer is formed on a substrate, covering a first area within a pixel region of the substrate, and covering a first gate of a first transistor within a logic region of the substrate, wherein the substrate comprises the pixel region and the logic region. A spacer layer is formed on the oxide layer, a buffer layer is formed on the spacer layer, and a photoresist layer is formed on the buffer layer over the pixel region, wherein the photoresist layer has an opening exposing a first part of the buffer layer over the first area. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer over the first area, and to remove the buffer layer to expose the spacer layer over the first gate, while leaving a remaining part of the buffer layer covered by the photoresist layer intact. The photoresist layer is then removed. A second etching is performed to remove the remaining part of the buffer layer, remove the first part of the spacer layer to expose a first part of the oxide layer on the first area, while leaving a second part of the spacer layer over the pixel region, and remove the spacer layer over the first gate to expose the oxide layer on the first gate, while keeping the spacer layer around the first gate. A third etching is performed to remove the first part of the oxide layer to expose the first area, and remove the oxide layer on the first gate to expose the first gate.

A device for a sensor is disclosed. The device comprises a substrate comprising a pixel region and a logic region, wherein the pixel region comprises a first area, and the logic region comprises a source and a drain. A first gate of a first transistor is above a first channel between the source and the drain. An oxide layer is on the substrate, wherein the oxide layer covers the substrate with an opening to expose the first area in the pixel region, and the oxide layer surrounds a sidewall of the first gate of the first transistor. A spacer layer is on the oxide layer, wherein the spacer layer covers the oxide layer over the pixel region, with an end next to the opening of the oxide layer, the end has a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end, and the spacer layer surrounds the sidewall of the first gate in the logic region.

A device for a sensor is disclosed. The device comprises a substrate comprising a pixel region and a logic region. The pixel region comprises a photo-sensitive element, and a floating node, while the logic region comprises a source and a drain. A first gate of a first transistor is above a first channel between the source and the drain, and a second gate of a transfer transistor is above a second channel between the floating node and the photo-sensitive element. An oxide layer is on the substrate, wherein the oxide layer covers the substrate with an opening to expose the floating node, and the oxide layer surrounds a sidewall of the first gate of the first transistor. A spacer layer is on the oxide layer, wherein the spacer layer covers the oxide layer over the pixel region, with an end next to the opening of the oxide layer. The end of the spacer layer has a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end, and the spacer layer surrounds the sidewall of the first gate in the logic region.