Segmented supply rail configuration for a digital integrated circuit

An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail.

PRIORITY CLAIM

This application claims priority from French Application for Patent No. 1151526 filed Feb. 25, 2011, the disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD

The invention relates to the field of microelectronics and, more particularly, to digital integrated circuits. The invention relates in particular to a specific structure for supply rails that are used to supply the functional cells of an integrated circuit with the power they require in order to operate.

BACKGROUND

Digital integrated circuits perform various logic operations using elementary functional cells. Each one of these cells performs elementary operations and transfers the results of these operations to the adjacent cells to which it is connected. These elementary cells comprise various logic gate structures or structures derived therefrom.

The electric power supplied to the various cells is applied to each of the cells through supply rails that are located at metallization levels that are close to the functional areas of each cell. These rails are generally assembled in pairs and are brought to reference potentials which are generally ground (GND) and a reference voltage that is generally positive but depends on the particular technology used.

It has been observed that reliability problems may affect components because of electromigration phenomena that occur in the conductors that transport currents which have a significant current density.

In fact, electromigration phenomena cause the displacement of atoms inside the metallic conductors due to the impact of electrons. This displacement of atoms can result, in the long-term, in the appearance of areas that are devoid of material within a conductor.

In this case, the useful cross-sectional area of the conductors is therefore reduced and this increases the current density in the remaining cross-section and consequently increases the risks of electromigration. Conduction can, in extreme cases, be limited to the periphery of the conductor in barrier regions with a consequent significant increase in electrical resistance and associated temperature rises.

When electromigration phenomena occur directly above or below connection vias with upper and/or lower metallization levels, conduction can be totally interrupted if the cavity that is created covers the entire interface area between the conductor and the connection via.

SUMMARY

The trend towards increasingly dense component integration is resulting in a reduction in the cross-sectional area of metallic conductors without any real decrease in the overall power consumption of components. In other words, observed current densities are tending to rise and, concomitantly, so are the risks associated with electromigration.

The need to limit the impact of electromigration phenomena and to improve the reliability of digital components has therefore made itself felt.

Thus, according to one aspect, a digital integrated circuit is provided which contains an array of functional cells, whereof a subset is powered by at least one supply rail to which each cell of the subset is connected and wherein the rail comprises a plurality of segments located on two separate metallization levels and at least one conductor element that extends between said two metallization levels and connects two successive segments of said rail.

Thus, the supply rails are divided up into different segments so that the length of the segments at a single metallization level is limited. This limited length makes it possible to reduce the risks associated with electromigration in accordance with the Blech effect which states that, below a predetermined conductor length, electromigration phenomena cannot occur in a line.

Various architectures can be used in relation to different aspects of the invention. Thus, in one embodiment of the invention, the conductor element may extend between the overlapping areas of two successive segments located on two separate metallization levels.

In practice, several conductor elements can connect two successive segments in parallel. In other words, the connection between two metallization levels can be made by several vias or pillars.

According to one aspect, some of the segments extend inside a single cell. Thus, the rail comprises segments located on the first metallization level that are shorter than the others and are confined to a single cell.

Obviously, the dimensions and ratios between the various elements shown in the Figures have been chosen to make the invention easier to understand and may differ from real values.

DETAILED DESCRIPTION OF THE DRAWINGS

As shown inFIG. 1, a digital integrated circuit comprises a plurality of elementary functional cells2produced on a semiconductor substrate which includes metal layers.

These various cells2are spatially arranged in the form of an array; only a single row of this array is shown inFIG. 1. These cells2are arranged relative to each other in a way that ensures that their inputs and outputs are connected in order to obtain the desired logic functions.

Conventionally, the substrate is covered by a plurality of superposed metallization levels that are separated by insulating layers. Generally speaking, the upper metallization level comprises a number of conductors6-9which are connected to reference potentials and designed to carry the power supply current that is needed in order for the various cells2to operate.

In the example shown, these conductors6-9are of two types, some of them6,8being connected to ground (GND) and others7,9being connected to a positive reference potential (VDD). Obviously, it is possible to carry other positive or negative reference potentials depending on the particular application.

As shown inFIG. 1, these main supply conductors6-9are connected to the lower metallization levels by conductive columns10,11that are formed by a stack of metals12-15deposited on the metallization levels between which there are interposed interconnect vias16-20which pass through the insulating layers that separate the metallization levels.

In order to make the invention easier to understand, only the conductive parts are shown inFIG. 1, the insulating parts of the metallization levels and the insulating layers have been omitted.

As shown inFIG. 1, the various cells2in a row are powered by two rails30,40which are positioned at right angles to main supply conductors6-9.

In the embodiment shown, these rails30,40are formed by different segments31-35which are located on two separate metallization levels. More precisely, rail30comprises segments32,34located on metallization level M1which rests directly on the active part of functional cells2, and segments31,33,35which are located on upper metallization layer M2.

Successive segments33,34have overlapping areas36,37shown in the top view. In these overlapping areas36,37conductor elements38are designed to ensure electrical connection between successive segments33,34. The useful cross-sectional area of conductor elements38is preferably chosen so that it is roughly the same as the useful cross-sectional area of segments31-35of the rail. In practice, conductor elements38can be made in the same way as interconnect vias16-20which electrically connect the different metallization levels.

It is also possible to create several parallel conductor elements and as many vias as are needed to carry the supply current at a current density that is compatible with the particular technological constraints.

Thus, as shown inFIG. 2, it is possible to produce one or more vias39that connect the lower face of one end36of a first segment33to the upper face of end37of a second segment34located on lower metallization level M1. The number and the shape of the vias can obviously be adapted depending on the materials used and the thicknesses of the various layers involved.

It is also possible, as shown inFIG. 2a, to ensure that shorter segments42are located on upper metallization level M2. In this case, the longer segments41,43of the supply rail are located closest to the cells on lower metallization level M1. In one particular embodiment, one can ensure that column10which is connected to main supply conductors6is located in vertical alignment with shorter segments42.

Returning toFIG. 1, it is apparent that supply rail30is therefore split and longer segments31,33,35are shown on the upper metallization level which has a given length. This length is limited so that the Blech effect comes into play and the segment in question therefore cannot be the site of electromigration phenomena or such phenomena are at least considerably reduced.

In practice, it has been noticed that, thanks to this splitting up of supply rails30,40, it is possible to increase the current density by a factor of several times or more while retaining a limited risk of electromigration phenomena occurring. This way, it is possible to reduce the dimensions (thickness, width) of the conductors that form the rail in order to achieve higher packing densities.

By way of example, for rails that have a useful width of 0.01 μm and are designed to carry a current of 1 mA, equivalent to a current density of 100 mA/μm, the critical length in order for the Blech effect to cancel or very significantly limit the risk of electromigration phenomena occurring is around 6 μm, which is substantially equivalent to the length of two elementary functional cells each having an average length of around 3 μm. Obviously, these values are indicated merely by way of example and may vary depending, in particular, on the technology used, the nature of the materials used and operating conditions, especially temperature.

Various geometries can be used without extending beyond the scope of the spirit of the invention.

Thus, as shown inFIG. 3which corresponds to the configuration inFIG. 1, the various segments31-35of rail30are produced on two metallization levels, keeping the shortest segments32,34bounded by a single cell2. In order to facilitate visualization, segments32,34on the lower metallization levels are shown as wider than segments31,33,35which are located on the upper metallization level but this does not imply that this is a technically mandatory or real feature.

In other words, all the cells, apart from those that comprise a portion of the rail, have sections that are continuous with the supply rail and therefore have a traditional design. The number of cells over which longer segments31,33,35extend may vary depending on the prospective current density. Thus, this number of cells may vary from several units to one or more dozen units depending on the particular application. In other words, resistance to electromigration phenomena can be improved by using libraries of existing cells in which only a reduced number of cells need to be rerouted due to displacement of the metallization level of the supply rail.

Obviously, in all the variants shown, the shorter segments are shown on lower metallization level M1which is closest to the functional cells and the longer segments are shown on upper metallization level M2, but this configuration can be reversed without going beyond the scope of the invention.

Similarly, in the embodiment shown inFIG. 3, the two rails30,40of the supply circuit are shown as symmetrical relative to the median plane that separates them. Nevertheless, alternative configurations, such as those shown inFIG. 4in which only one rail60of the two rails has a split configuration, can be used. The other rail69can be subject to less exacting constraints in terms of current density and can, as appropriate, have a continuous traditional geometry.

Likewise, one variant shown inFIG. 5can make provision for two portions of rails74,84being located on two separate metallization levels within a single cell2. In other words, one metallization level is only occupied by a single supply rail in a given cell.

The above descriptions show that splitting the supply rails, even though it makes the design slightly more complex, has the major advantage of cancelling, or at least considerably limiting, electromigration problems.