METHODS AND APPARATUS FOR INTEGRATING CARBON NANOFIBER INTO SEMICONDUCTOR DEVICES USING W2W FUSION BONDING

A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application contains subject matter related to a concurrently-filed U.S. Pat. Application by Wei Zhou et al., entitled “METHODS AND APPARATUS FOR INTEGRATING CARBON NANOFIBER INTO SEMICONDUCTOR DEVICES USING W2W FUSION BONDING”. The related application, of which the disclosure is incorporated by reference herein, is assigned to Micron Technology, Inc., and is identified by attorney docket number 010829-9698.US00.

TECHNICAL FIELD

The present technology is directed to semiconductor device packaging. More particularly, some embodiments of the present technology relate to techniques for improving the resilience and thermal conductivity of semiconductor devices and device assemblies.

BACKGROUND

Semiconductor dies, including memory chips, microprocessor chips, logic chips, and imager chips, can be assembled by mounting a plurality of semiconductor dies, individually or in die stacks, on a substrate in a grid pattern. Memory chips can be fabricated in a device wafer and then singulated. The assemblies and chips can be used in mobile devices, computing, and/or automotive products. A significant thermal issue can result from stacking many dies together and/or including multiple dies/chips in a small package or device. A robust and efficient thermal dispenser is needed to prevent overheating of semiconductor devices.

DETAILED DESCRIPTION

In general, carbon nanofibers (CNFs) have high thermal conductivity, i.e., higher than copper. CNFs are also extremely strong and thus have excellent mechanical performance. Further, CNFs can carry very high current density. These advantageous properties of CNFs make it an ideal material to incorporate into semiconductor packages. However, in order to have a reliable and aligned growth, the process to grow CNFs requires a high temperature, i.e., at least or greater than 400° C. Therefore, conventional techniques do not allow the CNFs to be grown directly on a chip such as a dynamic random access memory (DRAM) as the chip cannot sustain such a high process temperature.

To overcome the limitations of the conventional techniques, methods and apparatus are described herein for growing CNFs on currently available semiconductor materials and within dimensions that will facilitate the incorporation of CNFs into semiconductor packages. In some embodiments, the CNFs can be grown in a layer on semiconductors substrates, such as, but not limited to, silicon substrates. The silicon substrate can withstand the extreme heat required to grow the CNFs. The silicon substrate can be a standard wafer size and shape, providing the advantage of creating a CNF layer that can easily be attached to other wafers.

An expected advantage of the embodiments discussed below include improved mechanical properties that are realized by providing a strong structure that includes both the CNFs and a molding compound. The molding compound impregnates or flows between individual adjacent CNFs to enhance strength, structural support, and stabilization. The encapsulated CNF layer can be thinned to a desired thickness and to expose upper edges of the CNFs. Further, the mixed thermal conductivity of the CNFs and the molding compound can still be as high as 600 W/MK, thus approximately two-times higher than copper and five-times higher than silicon.

A further advantage is that the encapsulated CNF layer can be attached directly to a DRAM or other wafer, such as with fusion bonding or other bonding processing (e.g., bonding of silicon layers, oxide to oxide layers, etc.). After any carrier wafer(s) are removed, the chips can be singulated to form DRAM or other controllers, memory devices, device assemblies, etc., that include an encapsulated CNF layer that provides improved thermal dissipation.

Another expected advantage of the embodiments discussed herein include forming die stacks that include the CNF layer. A plurality of die stacks can be formed on a reconstituted wafer, i.e., a wafer that includes a plurality of memory or other chips. The wafer-sized and shaped encapsulated CNF can be attached directly to top chips of the die stacks, and then the die stacks can be singulated.

Numerous specific details are disclosed herein to provide a thorough and enabling description of embodiments of the present technology. A person skilled in the art, however, will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details of the embodiments described below with reference toFIG.1A-9. For example, some details of semiconductor devices and/or packages well known in the art have been omitted so as not to obscure the present technology. In general, it should be understood that various other devices and systems in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below,” “top,” and “bottom” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper,” “uppermost,” or “top” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. Also, as used herein, features that are, can, or may be substantially equal are within 10% of each other, or within 5% of each other, or within 2% of each other, or within 1% of each other, or within 0.5% of each other, or within 0.1% of each other, according to various embodiments of the disclosure.

FIGS.1A and1Billustrate an overview of the present technology, whileFIGS.2-9illustrate further details of the present technology. Like reference numbers relate to similar components and features inFIGS.1A,1B,3A-3E,5A-5G, and7A-8. The present technology addresses the technical problem of thermal performance, which can cause overheating of individual chips, dies, and/or device assemblies, resulting in complete or partial failure of component(s). A CNF layer, directly attached to or integrated with chips and device assemblies can improve thermal dissipation and prevent overheating.

FIGS.1A and1Bare side cross-sectional views of semiconductor device assemblies that include a carbon nanofiber (CNF) layer that is encapsulated with a molding compound in accordance with the present technology.FIG.1Ashows a device assembly100athat has been formed using wafer-to-wafer (W2W) processing, such as fusion bonding, and then singulated, whileFIG.1Bshows device assemblies102a,102bthat have been formed using chip-to-wafer (C2W) processing. The CNF layer in both of the assemblies100,102can be grown and encapsulated as discussed below inFIGS.2and3A-3Ebefore being included within the assemblies100,102, as discussed further below inFIG.4-7D.

Turning first toFIG.1A, partial device assemblies104a,104bare shown to either side of the device assembly100a, indicating that the assemblies104a,100a,104bcan be singulated from the same wafer. The device assembly100awill be discussed in further detail. A memory device106(e.g., singulated from a DRAM device wafer) can have a silicon oxide (SiO) layer108aover its upper surface110. An encapsulated CNF layer112a, which was grown from seed layer114a(discussed further below inFIG.2-3B), can be attached (e.g., fusion bonded) to an outer surface109of the SiO layer108awith an SiO layer116a. Solder balls118a,118b,118c,118dcan be attached to a bottom surface120of the memory device106. Other attachments can be used. As discussed further below, the fusion bonding can occur prior to singulation.

The semiconductor device assemblies102a,102bshown inFIG.1Bcan be singulated from the same wafer, such as a reconstituted wafer. In some embodiments, device assemblies102a,102bcan be hybrid memory cubes (HMC) that use through-silicon vias (not shown) and microbumps (not shown), along with, in some cases, adhesive layers to interconnect a plurality of dies130a,130b,130c,130d, and top die132a(e.g., memory cell arrays) together in a die stack134a. The die stack134acan be attached to a upper surface138of a memory device136. The solder balls118e,118fcan be attached to a bottom surface140of the memory device136. Molding compound142a,142bencapsulates side edges144a,144bof the die stack134a(only two side edges144are shown). The encapsulated CNF layer112b, grown from the seed layer114b, can be attached (e.g., fusion bonded or other bonding method) with the SiO layer116bto a polymer layer146a.

In other embodiments, different chips can be used instead of memory chips. The embodiments ofFIGS.1A and1Bapply equally to Flip Chip processes, fanout processes, etc. Because the encapsulated CNF layer112is formed separately from the device wafer and/or die stacks, the encapsulated CNF layer112can be used together with any chip where thermal conduction is desired.

FIG.2is a flow chart of a method200for growing a CNF layer on a blanket wafer (e.g., semiconductor substrate) in accordance with the present technology.FIGS.3A-3Eillustrate side cross-sectional views of the growth and fabrication of the CNF layer using the method200ofFIG.2to form a semiconductor device assembly, referred to herein as a CNF assembly. The method200provides the ability to grow CNFs on a surface and within dimensions that are easily integrated into current semiconductor packaging processes. Only a portion of the wafer and CNF layer is shown inFIGS.5A-5D.

First turning toFIGS.2and3A, the SiO layer116ccan be grown on or applied to an upper surface150of a substrate152(block202). In other embodiments, a layer of silicon nitride (SiN), silicon carbon nitride (SiCN), or polymer can be used in place of the SiO layer116c. By way of example, the SiO layer116c(or other material) can be very thin, such as approximately 0.1 micron, less than 0.2 micron, or approximately 0.2 micron. The SiO layer116ccan provide an isolation or passivation layer on the upper surface150, and therefore the CNFs will not be in direct contact with the substrate152. In some embodiments, the substrate152can be made of silicon, but the technology is not so limited and other materials that can withstand high temperature are also contemplated. The substrate can be a 12-inch (e.g., 300 cm) diameter wafer, and therefore only a small portion of the substrate152is shown in theFIGS.3A-3E. An expected advantage is that the SiO layer116ccan be exposed later in the assembly process when the substrate152is removed, providing a mounting surface suitable for fusion bonding to another surface, as discussed below in at leastFIGS.3E,5E, and7D.

A titanium and copper (Ti/Cu) seed layer114ccan be applied to the SiO layer116con the substrate152(block204) as shown inFIG.3B. Other metals can be used as allowed and appropriate to the technology. In some embodiments, the seed layer114cextends across a surface area of the SiO layer116c. CNFs154a,154b,154c(not all individual CNFs154are indicated) are grown on the substrate152(block206) at a high temperature such as at least or greater than 400° C. It should be understood that many CNFs154are grown to form a CNF layer158, and that the CNFs154are shown as simple lines for ease of illustration and description only. In some embodiments, the CNFs154can be grown to a height H1 of at least 200 microns. The height H1 may be determined based at least on the height restrictions of the final device, such as semiconductor device assemblies100,102ofFIGS.1A and1B.

Using a wafer level molding process or other molding process, the CNFs154extending across the upper surface150of the substrate152can be encapsulated with a molding compound156a,156b,156c(block208) as shown inFIG.3C. For example, the molding compound156can impregnate and/or penetrate into the CNF layer158(FIG.3B), flowing and/or extending between at least some of the individual adjacent CNFs154, to provide strength, structural support, and stabilization of the CNF layer158. A variety of different materials and/or application methods (e.g., dipped, dispensed, deposited, etc.) can be used for the molding compound156, such as an epoxy-based liquid compound with or without granules (e.g., particulate), a granular compound, thin-film based underfill or compound, resin-based encapsulant, polymer, etc. As inFIG.3B, the CNFs154and the encapsulant there-between (e.g., molding compound156) are shown and described as simple lines and/or blocks for ease of description only.

After the molding compound156has cured and/or hardened, the encapsulated CNF layer112ccan be thinned to a desired thickness T1 (block210). The desired thickness T1 can be in a range of less than 100 microns, between 100 microns and 200 microns, around 200 microns, etc., depending, in some cases, upon the height restrictions of the final device. An upper surface160of the encapsulated CNF layer112ccan be ground, such as pulse grinding, to expose upper edges162a,162b(e.g., tips or ends) of the CNFs154and to create a smooth bonding surface. In some embodiments, the thickness T1 the encapsulated CNF layer112can be approximately equivalent to the height H1 of the CNFs154.

A bottom surface184of a carrier wafer164can be mounted on and/or joined to the upper surface160of the encapsulated CNF layer112c(block212) with an adhesive166as shown inFIG.3D. The molding compound156within the encapsulated CNF layer112cprovides the further advantage of allowing the CNFs154to be securely attached to the carrier wafer164and to be handled while attached to the substrate152and/or after the substrate152is removed.

The substrate152can then be removed, such as by grinding/etching to expose the SiO layer116c(block214), resulting in a CNF assembly168that includes the encapsulated CNF layer112cand the carrier wafer164as shown inFIG.3E. The SiO layer116cprovides a mounting surface180that will be adhered to a mounting surface of another layer as discussed below inFIGS.5E and7D.

FIG.4is a flow chart of a method400for using wafer-to-wafer technology to fabricate a wafer of memory dies (or other chips) that includes the encapsulated CNF layer112in accordance with the present technology. Although the discussion herein is directed to a wafer of memory dies, it should be understood that the method to include the encapsulated CNF layer112can be applied to any type of die fabricated within a wafer.FIGS.5A-5Gillustrate side cross-sectional views of the fabrication of the wafer of memory dies with the encapsulated CNF layer112and will be discussed together withFIG.4. Only a portion of the wafers and the encapsulated CNF layer112is shown.

A plurality of the solder balls118g,118h,118i,118jcan be attached/applied, such as by a wafer bumping process, on the bottom surface120c(e.g., active surface) of a semiconductor wafer that includes a plurality of semiconductor devices, such as a memory wafer170, (block402).FIG.5Ashows the memory wafer170, such as a DRAM wafer, having a thickness T2. Interconnections other than the solder balls118can be used.

The bottom surface120cof the memory wafer170can be directly mounted to a surface172(e.g., backside) of a carrier wafer174, such as with an adhesive176(block404), as shown inFIG.5B.

The memory wafer170can be thinned to a thickness T3, exposing the upper surface138c(block406). The thickness T3 of the memory wafer170as shown inFIG.5Cis less than the thickness T2 inFIG.5A. In some embodiments, the memory wafer170can be thinned to be about 50 microns or less, but the embodiments are not so limited.

A coating or layer, such as the SiO layer108b, can be applied to or adhered to the upper surface138cof the memory wafer170(block408) to form a memory wafer assembly182as shown inFIG.5D.

Turning toFIG.5E, the memory wafer assembly182ofFIG.5Dhas been rotated such that a mounting surface178of the SiO layer108bfaces the mounting surface180of the CNF assembly168ofFIG.3E. Referring also toFIG.4, the mounting surface178of the SiO layer108b(of the memory wafer assembly182) and the mounting surface180of the encapsulated CNF layer112c(of the CNF assembly168) can be prepared for fusion bonding (block410). For example, a sanding process or other process, such as a plasma treatment, can be accomplished on one or both of the mounting surfaces178,180, such as to improve adhesion.

Fusion bonding can be accomplished (block412) to join the memory wafer assembly182and the CNF assembly168(seeFIG.5F). For example, silicon oxide layer bonding (e.g., covalent bonding) can be used. Accordingly, in some embodiments when the memory wafer assembly182and the CNF assembly168are pressed together, chemical bonds are formed between the two mounting surfaces178,180, securely holding the layers together. In other embodiments, the memory wafer assembly182and the CNF assembly168can be pressed together, and in some cases, heat can be applied. In yet further embodiments, polymer (not shown) could be used instead of one or both of the SiO layers108b,116c. However, when using polymer, thermal conduction can diminish compared to using SiO.

The carrier wafers164,174can then be removed (block414), resulting in a semiconductor device assembly100bthat includes the embedded heatsink functionality of the encapsulated CNF layer112dwith the memory wafer170as shown inFIG.5G.

Individual memory dies can then be singulated (block416). Referring toFIG.1A, the device assembly100acan include one of the singulated memory dies.

FIG.6is a flow chart of a method600for using chip-to-wafer technology to fabricate a plurality of semiconductor device assemblies102that include the encapsulated CNF layer112in accordance with the present technology.FIGS.7A-7Dillustrate side cross-sectional views of the fabrication of the semiconductor device assemblies102using chip-to-wafer technology and will be discussed together withFIG.6.

A plurality of the die stacks134b,134c(not all are shown) can be formed across a width W1 of a device wafer190using chip-to-wafer technology and/or techniques (block602), as shown inFIG.7A. Only a small portion of the device wafer190is shown and thus width W1 simply represents the entire width of the device wafer190(e.g., 12 inches or 300 cm). The device wafer190can be a reconstituted structure having many memory dies or logic dies therein that are not yet singulated. For example, the dies130e,130f,130g,130h, and the top die132b, can be attached to the device wafer190and/or to each other using adhesive or other techniques to form the die stack134b.

The die stacks134can be molded with molding compound142c(block604). The molding compound142cand the top die(s)132can then be thinned to thin the top die(s)132to a thickness T4 and/or the die stack(s)134to a thickness T5 as shown inFIG.7B(block606). An upper surface194, which includes upper surfaces of the top dies132and the molding compound, can be exposed.

A thin polymer layer146bcan be applied to the upper surface194(block608) as shown inFIG.7Cto form device wafer assembly198. Polymer materials such as polybenzoxazoles (PBO) can be used, but the embodiments are not so limited. The polymer layer146bcan be polished to smooth the mounting surface196and/or thin the polymer layer146bif needed. In some embodiments, the polymer layer146bcan be thinner than the encapsulated CNF layer112c, such as approximately one micron, approximately two microns, greater than two microns, within a range of a half micron to two microns, or within a range of one micron to two microns, i.e., thick enough to provide reasonable bonding while allowing the thermal conductivity.

The mounting surface180of the CNF assembly168(FIG.3E) can be attached to the mounting surface196of the device wafer assembly198(block610) as shown inFIG.7D. For example, the CNF assembly168and the device wafer assembly198can be joined, in some embodiments, by cold welding (e.g., by pushing the mounting surfaces180,196together and adding heat). In other embodiments fusion bonding, hybrid bonding, oxide to oxide bonding, or dielectric to dielectric bonding can be used. In yet other cases, an additional adhesive (not shown) can be used. In the configurations including an adhesive such as polymer (e.g., the polymer layer146b), there can be a thermal tradeoff as the thermal conduction from the cube structure of the die stack134to the encapsulated CNF layer112can be reduced.

Although not shown inFIG.7D, in some embodiments the carrier wafer164(FIG.3E) can also be used when attaching the CNF assembly168. In that case, the carrier wafer164can be subsequently removed after the CNF assembly168and the device wafer assembly198are joined.

The dies stacks134are then singulated (block612) to form the semiconductor device assembly(s)102as shown inFIG.1B.

FIG.8shows an example of a die stack134dthat can be an HMC that has a heat spreader122attached over the encapsulated CNF layer112e. A layer of material124, such as SiO or polymer, can be used to join an upper surface126of the encapsulated CNF layer112eand the heat spreader122. The heat spreader122can also be attached to a surface129of wafer128. In some embodiments, the heat spreader122can be attached prior to applying the molding compound (not shown). The heat spreader122can provide improved mechanical and thermal performance for standalone HMC applications.

Any one of the semiconductor devices, assemblies, and/or packages described above with reference toFIG.1A-8can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system900shown schematically inFIG.9. The system900can include a semiconductor device assembly910, a power source920, a driver930, a processor940, and/or other subsystems or components950. The semiconductor device assembly910can include features generally similar to those of the semiconductor device assemblies described above. The resulting system900can perform any of a wide variety of functions such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems900can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, and other machines and appliances. Components of the system900may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system900can also include remote devices and any of a wide variety of computer readable media.

This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “some embodiment,” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. The present technology is not limited except as by the appended claims.