Soft saturation detection for power amplifiers

A soft saturation detection circuit for a radio frequency (“RF”) power amplifier is configured to detect the onset of soft saturation in an unambiguous and accurate manner. The circuit compares the time derivative of a voltage signal indicative of the RF output power to the time derivative of a control voltage signal for the RF power amplifier. The circuit also employs a gating mechanism that ensures that a soft saturation indication signal is generated under appropriate operating conditions.

TECHNICAL FIELD

The present invention relates generally to radio frequency (“RF”) power amplifiers. More particularly, the present invention relates to soft saturation detection techniques for RF power amplifiers.

BACKGROUND

The prior art is replete with RF power amplifiers suitable for use with numerous practical applications. For example, mobile telephones and other wireless communication devices are common applications for RF power amplifiers. In mobile telephone applications, the RF output power level for the transmit signal may vary over time due to operating conditions and/or output power modulation schemes. An RF power amplifier becomes saturated when the change in output power decreases to zero with an increase in a control variable (e.g., an output power control voltage). Operation in a saturated condition may result in distortion and can compromise the operation of a closed loop control scheme for the RF power amplifier.

The term “soft saturation” refers to operation of an RF power amplifier in a region that precedes the actual saturation point. A number of detection techniques have been developed to detect the onset of soft saturation before serious distortion or control issues arise. For example, prior art techniques rely on the detection of a maximum triggering level of a control voltage signal in the RF power amplifier, below which the amplifier operation is unaffected by the effects of saturation. In practice, however, the triggering level for a given RF power amplifier can vary from unit to unit and even within a given unit over different operating conditions. Consequently, a fixed triggering level may not correspond to optimal soft saturation detection in all cases and these soft saturation detection techniques may rely on ambiguous detection thresholds. Such ambiguity may cause the detection scheme to overshoot or undershoot the actual onset of soft saturation in the RF power amplifier. Although undershooting the onset of soft saturation will not adversely affect the operation of the RF power amplifier, undershooting results in inefficient use of available output power. Undershooting in this manner will result from very conservative threshold levels, which require excessive headroom with lower battery efficiency for mobile applications. Otherwise, substantial amounts of calibration are required (e.g., phasing) during manufacture of the device. In contrast, overshooting the onset of soft saturation may result in actual hard saturation of the RF power amplifier and the associated distortion and control issues mentioned above.

Accordingly, it is desirable to have a soft saturation detection technique, suitable for use with RF power amplifiers, that unambiguously measures the amount of saturation occurring in the amplifier using signals available in the amplifier circuit. In addition, it is desirable to have a soft saturation detection circuit that provides an accurate and device independent measure of approaching saturation in an RF power amplifier. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

The invention may be described herein in terms of functional and/or logical block components and various processing steps. It should be appreciated that such block components may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of the invention may employ various circuit components, e.g., transistors, logic elements, discrete components, or the like, which may carry out a variety of functions under the control of suitable control devices. In addition, those skilled in the art will appreciate that the present invention may be practiced in conjunction with any number of practical circuits, subsystems, or systems, and that the RF power amplifier deployment described herein is merely one exemplary application for the invention.

For the sake of brevity, conventional techniques related to RF power amplifier design, RF signal coupling, RF signal detection, analog circuit design, digital circuit design, and other functional aspects of the circuits (and the individual operating components of the circuits) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in a practical embodiment.

The following description may refer to nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one node/feature is directly joined to (or directly communicates with) another node/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one node/feature is directly or indirectly coupled to (or directly or indirectly communicates with) another node/feature, and not necessarily mechanically. Thus, although the schematics shown in the figures depict example arrangements of elements, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the circuit is not adversely affected).

A soft saturation detection circuit for an RF power amplifier is described in detail herein. The detection circuit can detect the onset of soft saturation in an RF power amplifier without excessive calibration and in a manner that is more robust to parametric and/or environmental changes (e.g., variation in temperature, voltage, input drive, input frequency, output loading, or the like). The soft saturation detection circuit is configured to directly sense the saturation mechanism that is to be controlled in a practical manner using changes in voltage signals that are readily available from the RF power amplifier circuit itself. In other words, the detection circuit can measure or detect the actual quantity related to saturation of the RF power amplifier, as opposed to a signal or quantity at which saturation is supposed to occur. In contrast, prior art techniques sense a voltage level that must be correlated with the saturation and which varies with changing operating conditions and from unit to unit. Practical implementations of the detection circuit can be realized in either the analog domain or the digital domain. For example, the circuits described herein may be utilized in RF power amplifiers and front end modules for GSM or GSM/EDGE mobile devices to prevent clipping and to ensure compliance with specified transmit burst time mask and switching specifications. In particular, the circuits described herein can be employed in connection with a variety of bursted transmission communication systems that use output power control schemes.

FIG. 1is a schematic representation of an RF power amplifier circuit100configured in accordance with an example embodiment of the invention. Circuit100generally includes an RF power amplifier102and an output power control architecture104coupled to RF power amplifier102. In this example, which is suitable for use with a wireless communication device, RF power amplifier102receives an input signal106and generates an RF output signal108having desired output characteristics. In practice, the frequency, amplitude, phase, and other characteristics of RF output signal108are dictated by the particular application. RF power amplifier102drives an RF antenna110for transmission of RF output signal108.

RF power amplifier circuit100preferably includes an RF coupler112, which is suitably configured to obtain a coupled incident signal116for output power control architecture104. In practice, coupled incident signal116is based upon a forward incident component of RF output signal108. RF coupler112can be realized as a directional coupler having an incident port. In a practical implementation, RF coupler112can be integrated into an output harmonic filter for RF power amplifier102, thus minimizing insertion loss and conserving physical space. RF coupler112may incorporate an RF transmission line that provides a suitable amount of coupling relative to RF output signal108. For example, RF coupler112may be realized as a −20 dB coupler using any suitable construction.

Briefly, output power control architecture104is configured to adjust operating characteristics of RF power amplifier102in response to coupled incident signal116. Although not depicted inFIG. 1, output power control architecture104may include or communicate with suitable control or processing logic that influences its operation, sets initial parameter settings, or the like. Output power control architecture104is suitably configured to generate at least one control signal118for RF power amplifier102, where the control signal(s)118have characteristics influenced by coupled incident signal116. As depicted inFIG. 1, output power control architecture104can generate any number (N) of control signals118, where the actual number depends upon the particular application. Furthermore, a given control signal118may be a bias voltage, a bias current, a supply voltage, a supply current, or a digital control signal that influences bias or supply voltages or currents, and a given control signal118may be applied to any number of amplifier stages associated with RF power amplifier102. As described in more detail below, output power control architecture104is preferably configured to obtain an output voltage signal that is indicative of RF output signal108.

FIG. 2is a schematic representation of an electronic circuit200configured in accordance with an example embodiment of the invention. Circuit200is suitable for use in transmitters of cell phones supporting, for example, EDGE/GSM standards. The input RF signal to be amplified includes amplitude envelope and phase constituents. As illustrated inFIG. 2, the RF carrier without amplitude modulation, VINejwt, is applied at the input of the RF power amplifier. The amplitude constituent, VENV, is applied through a summing junction to modulate the biases of the amplifier stages, thereby reconstituting the envelope on the phase modulated signal. Preserving the envelope characteristics is achieved via the power control techniques described in more detail herein.

Circuit200generally includes an RF power amplifier202, an RF antenna203, an RF coupler204, an RF attenuator/gain element206, an amplitude detector208, a summer210, an integrator212, and a soft saturation detection circuit214. In a practical embodiment, summer210and integrator212may be realized as a single element or component. RF attenuator/gain element206, amplitude detector208, summer210, and integrator212collectively may be considered to be an output power control architecture as described above in connection with circuit100. The output power control architecture (more specifically, amplitude detector208) is suitably configured to obtain an output voltage signal (VOUT), where VOUTis indicative of the RF output power signal.

RF power amplifier202may be a full polar amplifier that operates in the manner described above. As depicted inFIG. 2, the amplitude constituent of the RF input signal (VENV) serves as one input to summer210, and the phase constituent of the RF input signal (VINejwt) serves as an input to RF power amplifier202. RF power amplifier202is suitably configured to generate an RF output power signal (VOUTejwt), which is utilized to drive RF antenna203in this example. In practice, RF power amplifier202generates the RF output power signal in response to an output power control signal (VC) applied to RF power amplifier202. In this example, VCcorresponds to VAPC, which represents an output of integrator212; alternatively, the output power control signal can be a signal that is derived from an output of integrator212, any signal generated by circuit200, or any signal that is otherwise appropriate for the particular application. Due to the loop arrangement of circuit200, VAPCis generated in response to VOUT.

RF coupler204, which may be configured to operate as described above in connection with RF coupler112, obtains a coupled incident signal associated with the RF output power signal. This coupled incident signal may serve as an input to RF attenuator/gain element206. RF attenuator/gain element206, which has an input coupled to RF coupler204, is suitably configured to adjust the magnitude of the coupled incident signal to a level appropriate for the current operating conditions. RF attenuator/gain element206adjusts the level of the coupled incident signal to increase the dynamic range of amplitude detector208. In a practical embodiment, circuit200may utilize a suitable control scheme to initialize RF attenuator/gain element206in accordance with the desired level for the RF output power signal. Thereafter, the initial settings can be altered as the desired level for the RF output power signal changes to suit the dynamic needs of the particular application.

In a practical embodiment of circuit200, RF attenuator/gain element206is realized as an adjustable or programmable component having a suitable adjustment range for varying the average power level of the coupled incident signal. In one example embodiment, RF attenuator/gain element206provides 28 dB of programmable attenuation/gain. In operation, RF attenuator/gain element206is controlled to attenuate or amplify the coupled signal as needed to set the loop parameters of circuit200. Thus, RF attenuator/gain element206produces an attenuated/amplified RF signal216.

Amplitude detector208has an input coupled to the output of RF attenuator/gain element206. Amplitude detector208is suitably configured to quantify the amplitude of attenuated/amplified RF signal216. Moreover, amplitude detector208is preferably configured to generate the output voltage signal (VOUT), which is indicative of the detected amplitude of attenuated/amplified RF signal216. In the example embodiment, amplitude detector208is a linear amplitude detector that is capable of detecting amplitude levels corresponding to attenuated/amplified RF signal216, where the output voltage signal (VOUT) is indicative of the particular amplitude level. Alternatively, amplitude detector208may be realized as a logarithmic detector. In practice, the output voltage signal (VOUT) is a varying signal, where the particular voltage level represents the current detected amplitude of attenuated/amplified RF signal216.

Summer210compares the amplitude constituent of the RF input signal (VENV) with VOUT. In this example, the output of summer210corresponds to VENVminus VOUT. The output of summer210may serve as an input to integrator212, which is suitably configured to perform averaging or filtering of its input to obtain an average power level indication. In practice, integrator212can be realized as a gain stage that is also configured to provide a suitable amount of loop gain for circuit200.

Although not depicted inFIG. 2, circuit200may include a suitably configured bias signal generator that is configured to generate at least one bias control signal for RF power amplifier202. As described above, such bias control signal(s) influence the output power of RF power amplifier202, and the bias control signal(s) may be realized as a bias voltage, a bias current, a supply voltage, a supply current, a digital control signal that influences bias or supply voltages or currents, or the like. Furthermore, multiple bias control signals may be utilized to independently control separate stages of a practical RF power amplifier202. In this example embodiment, the functionality of the bias signal generator may be incorporated into integrator212, and the VAPCsignal represents a bias control signal for RF power amplifier202.

Soft saturation detection circuit214is coupled to the output power control architecture to obtain the VOUTsignal and the VAPCsignal (or respective signals derived or otherwise associated with the VOUTsignal and the VAPCsignal). Soft saturation detection circuit214is generally configured to process the VOUTsignal and the VAPCsignal to determine the onset of soft saturation of RF power amplifier202. In practical embodiments, soft saturation detection circuit214generates a soft saturation indication signal218upon detection of soft saturation. Soft saturation detection indication signal218may then trigger a limiting action by the transmitter power control algorithm and hardware to ensure that RF power amplifier202is not driven further into saturation. Soft saturation detection circuit218may be controlled by a reset signal220, which is activated to reset the operation of soft saturation detection circuit218between transmit bursts. For example, reset signal220may clear a flip-flop that indicates a soft saturation detection from a previous iteration.

FIG. 3is a schematic representation of a soft saturation detection circuit300configured in accordance with an example embodiment of the invention. Soft saturation detection circuit300may be deployed in the context of circuit200. The functional components of soft saturation detection circuit300may be realized using analog circuit techniques and/or digital circuit techniques.

Soft saturation detection circuit300generally includes a gain element302, a differentiator (depicted as two time derivative elements304/306), a voltage comparator308, a derivative comparator310, a ramp detector312, and a gating mechanism314. Circuit300is suitably configured to obtain VAPCand VOUTas inputs, and to produce a soft saturation indication signal316as an output. In this example embodiment, voltage comparator308, derivative comparator310, ramp detector312, and gating mechanism314collectively may be considered to be a soft saturation signal generator for circuit300.

As mentioned above, conventional soft saturation detection solutions rely on a fixed limiting voltage threshold, which may routinely vary depending upon may factors, including process variation, temperature, supply voltage, output VSWR, frequency, input power, and the like. In this regard,FIG. 4is a graph of VOUTversus VAPCfor different output loading conditions. This graph illustrates the onset of soft saturation for the RF power amplifier under different operating conditions. Plot402corresponds to a “worst case” VSWR condition, plot404corresponds to a nominal 50 ohm load condition, and plot406corresponds to a “best case” VSWR condition. The vertical marks on the plots roughly indicate the onset of soft saturation for the depicted operating conditions. Notably, the optimum soft saturation trigger value of VAPCvaries by more than 0.5 volts over this example range of different conditions, and the variation of VAPCcan vary by more than 1.5 volts in a practical implementation. Consequently, use of a single fixed VAPCvalue as the soft saturation indication point can produce ambiguous results.

Soft saturation detection circuit300overcomes the limitations of conventional techniques by directly sensing the root cause of the problem: the reduction in output voltage change with associated control voltage change. This is succinctly stated as triggering a soft saturation limit when the derivative of VOUTwith respect to VAPC(also known as the gain control slope) falls below a set limit, or:

ⅆVOUTⅆVAPC<K⁡(V/V),
where K is a constant that is selected according to the particular application to facilitate the enhanced soft saturation detection techniques described herein. The quantity

ⅆVOUTⅆVAPC
is known as the gain control slope. In this regard,FIG. 5is a graph of gain control slope versus VAPCfor different output loading conditions. Plot502corresponds to the worst case VSWR condition, plot504corresponds to the nominal 50 ohm load condition, and plot506corresponds to the best case VSWR condition. Assume, for example, that circuit300limits power on a minimum gain control slope value of 5.0 (FIG. 5includes dots on the plots corresponding to this value). The value of 5.0 approximates the 95% capability level of an example RF power amplifier, and the value of 5.0 captures the range of different VAPCvalues corresponding to onset of soft saturation. Thus, the use of this parameter as a soft saturation trigger captures an appropriate limiting value of VAPC, regardless of frequency, power, or VSWR. In practice, the actual value of this parameter may be empirically determined via bench testing, simulations, or other techniques.

Practical implementations of circuit300take advantage of the following methodology. The expression

ⅆVOUTⅆVAPC<1A
can be rewritten as

A⁢ⅆVOUTⅆt<ⅆVAPCⅆtifⅆVAPCⅆt>0,
where A is constant over time. Accordingly, circuit300can be realized with: a gain element (the gain A, although constant over time, is variable in that it can be adjusted and set as needed at phasing); a source of time change in VAPCand/or VOUTwith known polarity (either increasing or decreasing); a computation of the time derivative of VAPCand VOUT; and a comparator to compare

A⁢ⅆVOUTⅆttoⅆVAPCⅆt.
Referring again toFIG. 3, gain element302is easily accomplished using known techniques, the source of time change can be provided by the rising edge of the transmit burst with well known and repeatable characteristics, time derivative elements306and308can be provided by active high pass filtering, and derivative comparator310is easily accomplished using known voltage comparator techniques.

Circuit300preferably employs gating mechanism314(e.g., an AND gate function) to gate soft saturation indication signal316such that: (1) low gain control slope on initial burst turn-on is not detected as soft saturation; and (2) opposite polarity derivatives on burst turn-off is not detected as soft saturation. Condition (1) is easily detected by a non-critical threshold on the VAPCsignal that arms soft saturation detection circuit300only when the burst power exceeds a threshold, such as one-quarter to one-half of the maximum range. This is feasible because typical gain control slopes for RF power amplifiers are very low only at initial turn-on and when approaching power saturation. Condition (2) can be set by the baseband transmitter logic, which has access to the timing of the transmit burst. In alternative implementations, circuit300could be provided with an RF power amplifier control block and the appropriate burst gating could be separately applied in the baseband transmitter logic as part of the response to the soft saturation detection.

Accordingly, gain element302is suitably configured to multiply VOUTby a constant (A) to obtain a scaled output voltage signal (AVOUT). In this example, A is less than one for consistency with the above expressions. The differentiator for circuit300includes an input for VAPCand an input for AVOUT. In this example, AVOUTserves as an input to time derivative element304and VAPCserves as an input to time derivative element306. Time derivative element304is configured to calculate/generate a time derivative of AVOUT, and the output of time derivative element304corresponds to

A⁢ⅆVOUTⅆt.
Time derivative element306is configured to calculate/generate a time derivative of VAPC, and the output of time derivative element306corresponds to

Circuit300employs a soft saturation signal generator that is suitably configured to determine the onset of soft saturation based upon

A⁢ⅆVOUTⅆtandⅆVAPCⅆt.
In this example, the soft saturation signal generator includes voltage comparator308, derivative comparator310, ramp detector312, and gating mechanism314. Briefly, circuit300may be configured to indicate soft saturation if

ⅆVOUTⅆt/ⅆVAPCⅆt<1A.
Alternatively, and as illustrated inFIG. 3, circuit300may be configured to indicate soft saturation if

A⁢ⅆVOUTⅆt<ⅆVAPCⅆt,
and if

In this example, voltage comparator308compares VAPCto a voltage reference (VREF), where the voltage reference is a minimum level that corresponds to a time following initial burst turn-on. VREFis preferably chosen such that it marks a point that occurs after the initial steep increase in the gain control slope plots for the RF power amplifier. Voltage comparator308is configured to generate a logic high signal as an output if VAPCis greater than VREF, and to otherwise generate a logic low signal as an output. Derivative comparator310, which may also be realized as a voltage comparator, compares

A⁢ⅆVOUTⅆttoⅆVAPCⅆt.
Derivative comparator310is configured to generate a logic high signal as an output if

A⁢ⅆVOUTⅆt
is greater than

ⅆVAPCⅆt,
and to otherwise generate a logic low signal as an output. Ramp detector312is suitably configured to determine whether VAPCis increasing. Alternatively (or additionally), circuit300may employ a ramp detector that determines whether VOUTis increasing. In practical embodiments, ramp detector312may be realized as a voltage comparator or provided by external means (the dashed line inFIG. 3indicates that the depicted configuration for ramp detector312is optional). Ramp detector312generates a logic high signal as an output if VAPCis increasing, and otherwise generates a logic low signal as an output.

Gating mechanism314functions to generate a logic high soft saturation indication signal316when all of the necessary conditions are met, i.e., when all of the inputs to gating mechanism314are logic high. In other words, circuit300disables generation of an actionable soft saturation indication signal if VAPCis less than VREF, and disables generation of an actionable soft saturation indication signal if VAPC(and/or VOUT) is not increasing with time. Accordingly, gating mechanism314is configured to enable generation of an active or actionable soft saturation indication signal316if:

Operation of a soft saturation detection circuit as described herein is depicted inFIG. 6, which is a graph depicting the difference of the inputs to derivative comparator310for different output loading conditions. Plot602corresponds to the worst case VSWR condition, plot604corresponds to the nominal 50 ohm load condition, and plot606corresponds to the best case VSWR condition. The zero point on the vertical scale represents the onset of power limiting caused by soft saturation detection. Values less than zero correspond to no power limiting, and values greater than zero correspond to power limiting.

A soft saturation detection circuit as conceptually described above can be implemented in a number of different practical ways. For example,FIG. 7is a schematic diagram of a soft saturation detection circuit700configured in accordance with one practical implementation of the invention. Circuit700is suitable for use in GSM applications where the amplitude of the RF output signal is not modulated beyond transmission burst ramp-up and ramp-down. Some of the elements, features, and functions of circuit700have been described above in connection withFIG. 2andFIG. 3; such common elements, features, and functions will not be redundantly described in the context of circuit700.

Circuit700generally includes analog circuit components that form a gain element702, analog circuit components that form a differentiator704, analog circuit components that form a low pass filter706, a reference voltage comparator708, a time derivative voltage comparator710, and an AND gate712. Circuit700obtains VAPCand VOUTsignals as inputs, and generates a soft saturation indication signal714as an output. The output of circuit700(which may be routed to the transmitter baseband logic) is a logic high value when soft saturation is detected, and is otherwise a logic low value.

Gain element702may be realized with at least one variable resistance that enables the selection of the constant, A. In practice, gain element702considers the maximum power detector loss and A is selected in an appropriate manner. The values of the resistances and capacitances in differentiator704are selected such that the RC time constant matches the transmit ramp time constant, which is desirable to best utilize dynamic range. Differentiator704is configured such that its output (labeled716inFIG. 7) represents the quantity

A⁢ⅆVOUTⅆt
subtracted from the quantity

ⅆVAPCⅆt.
The voltage (VO) represents a slight constant voltage offset, which may be necessary to ensure proper operation of differentiator704in practical embodiments. In practice, differentiator704may be realized with any combination of components, circuits, and elements, and differentiator704need not be conveniently “packaged” in an easily discernable topology as depicted inFIG. 7.

Low pass filter706is utilized in practical embodiments because differentiator704effectively functions as a high pass filter, which can generate unwanted noise (low pass filter706attenuates the noise components). In this example, low pass filter706is configured such that its RC time constant is well above that of the applicable modulation. The voltage (VO) represents a slight constant voltage offset, which may be necessary to ensure proper operation of comparator710in practical embodiments. The output of low pass filter706(labeled718inFIG. 7) is therefore proportional to

Time derivative comparator710compares the voltage represented by the expression

(ⅆVAPCⅆt-A⁢ⅆVOUTⅆt)+VO
to the VOvoltage. In this example, comparator710generates a logic high value if the quantity

(ⅆVAPCⅆt-A⁢ⅆVOUTⅆt)+VO
is greater than the VOvoltage, and a logic low value otherwise. In other words, comparator710effectively generates a logic high value if

A⁢ⅆVOUTⅆt<ⅆVAPCⅆt.
Reference voltage comparator708compares VAPCto VREF(this reference voltage is described in more detail above), generates a logic high value if VAPCis greater than VREF, and otherwise generates a logic low value. The VRAMPsignal is a logic high value when a transmission burst is starting and the output is known to be increasing, and is otherwise a logic low value. As mentioned above, the VRAMPsignal can be an external input or it can be created by ramp detector312(seeFIG. 3).

AND gate712receives the output of reference voltage comparator708, the output of time derivative comparator710, and the VRAMPsignal as inputs. If all three of these inputs are logic high values, then AND gate712generates a logic high value as an output for soft saturation indication signal714. Otherwise, AND gate712will generate a logic low value as an output for soft saturation indication signal714.

In a practical embodiment, the resistances and capacitances in differentiator704can be selected in a manner that obviates the need for gain element702. In other words, the constant A set forth in the above expressions can be realized by tuning the RC time constants in differentiator704. In such an embodiment, gain element702need not be utilized.

FIG. 8is a schematic diagram of a soft saturation detection circuit800configured in accordance with another practical implementation of the invention. Circuit800is suitable for use in EDGE applications where the amplitude of the RF output signal is modulated. Thus, circuit800provides soft saturation detection for the rising edge of the transmit burst, along with early warning of distortion for amplitude modulated signals, which allows the transmitter to avoid generating spurious out-of-band signals due to modulation as well as burst transients. In this regard, circuit800is suitably configured to detect the onset of soft saturation that might be caused by modulation peaks of the RF output signal. Some of the elements, features, and functions of circuit800have been described above in connection withFIG. 2,FIG. 3, andFIG. 7; such common elements, features, and functions will not be redundantly described in the context of circuit800.

Circuit800generally includes analog circuit components that form a gain element802, analog circuit components that form a differentiator804, analog circuit components that form a low pass filter806, a reference voltage comparator808, a time derivative voltage comparator810, a voltage comparator811, and an AND gate812. Circuit800obtains VAPCand VOUTsignals as inputs, and generates a soft saturation indication signal814as an output. The output of circuit800(which may be routed to the transmitter baseband logic) is a logic high value when soft saturation is detected, and is otherwise a logic low value.

Gain element802may be realized with at least one variable resistance that enables the selection of the constant, A. In this example, differentiator804is realized with two separate time derivative circuits: one for the VAPCsignal and one for the VOUTsignal. The values of the resistances and capacitances in differentiator804are selected such that the RC time constant matches the transmit ramp time constant. A first output816of differentiator804represents the quantity

ⅆVAPCⅆt+VO,
and a second output818of differentiator804represents the quantity

A⁢ⅆVOUTⅆt+VO.
The voltage (VO) represents a slight constant voltage offset, which may be necessary to ensure proper operation of differentiator804in practical embodiments. In practice, differentiator804may be realized with any combination of components, circuits, and elements, and differentiator804need not be conveniently “packaged” in an easily discernable topology as depicted inFIG. 8.

In this example, low pass filter806is realized with two separate filter circuits (one for each “branch” of circuit800). As mentioned above in connection with circuit700, low pass filter806is configured such that the RC time constants of the filter circuits are each well above that of the applicable modulation.

Time derivative comparator810compares the voltage represented by the expression

ⅆVAPCⅆt+VO
to the voltage represented by the expression

A⁢ⅆVOUTⅆt+VO.
In this example, comparator810generates a logic high value if the quantity

ⅆVAPCⅆt+VO
is greater than the quantity

A⁢ⅆVOUTⅆt+VO,
and a logic low value otherwise. In other words, comparator810effectively generates a logic high value if

ⅆVAPCⅆt+VO
to the voltage represented by the expression VO+δV, where δV is a constant and arbitrary voltage offset that is utilized to ensure that circuit800triggers at a slope that is slightly greater than zero, which avoids false triggering. In this example, voltage comparator811generates a logic high value if the quantity

ⅆVAPCⅆt+VO
is greater than the quantity VO+δV, and otherwise generates a logic low value. In other words, voltage comparator811effectively generates a logic high value if

ⅆVAPCⅆt
is greater than δV, which ensures that VAPCis actually increasing. Thus, circuit800can utilize increasing levels of the modulated RF output power signal as a gating mechanism for the soft saturation indication signal814(in contrast to the ramp signal indicator signal utilized by circuit700).

AND gate812receives the output of reference voltage comparator808, the output of time derivative comparator810, and the output of voltage comparator811as inputs. If all three of these inputs are logic high values, then AND gate812generates a logic high value as an output for soft saturation indication signal814. Otherwise, AND gate812will generate a logic low value as an output for soft saturation indication signal814.

In a practical embodiment, the resistances and capacitances in differentiator804and/or the resistances and capacitances in low pass filter806can be selected in a manner that obviates the need for gain element802. In other words, the constant A set forth in the above expressions can be realized by tuning RC time constants. In such an embodiment, gain element802need not be utilized.

In summary, systems, devices, and methods configured in accordance with example embodiments of the invention relate to:

A method for detecting soft saturation of an RF power amplifier, said method comprising: obtaining an output voltage signal, VO, indicative of output power of the RF power amplifier; obtaining an output power control voltage signal, VC, for the RF power amplifier; calculating a time derivative of said output voltage signal,

ⅆVOⅆt;
calculating a time derivative of said output power control voltage signal,

ⅆVCⅆt;
and determining onset of soft saturation based upon

ⅆVOⅆt⁢⁢and⁢⁢ⅆVCⅆt.
The output power control voltage signal may comprise an error control signal for the RF power amplifier. The output power control voltage signal may be generated in response to said output voltage signal. The method may further comprise indicating soft saturation if

ⅆVOⅆt/ⅆVCⅆt<1A,
where A is constant over time. In one embodiment, A is less than one. The method may further comprise indicating soft saturation if

A⁢ⅆVOⅆt<ⅆVCⅆt,⁢and⁢⁢if⁢⁢ⅆVCⅆt<0,
where A is constant over time. The method may further comprise generating a soft saturation indication signal upon onset of soft saturation. The method may further comprise disabling generation of said soft saturation indication signal if said output power control voltage signal is less than a threshold voltage. The method may further comprise disabling generation of said soft saturation indication signal if said output voltage signal is not increasing with time.

A soft saturation detection circuit for an RF power amplifier, said circuit comprising: a gain element configured to multiply an output voltage signal, VO, by a constant, A, to obtain a scaled output voltage signal, AVO, said output voltage signal being indicative of output power of the RF power amplifier; a differentiator having a first differentiator input for an output power control voltage signal, VC, for the RF power amplifier, and a second differentiator input for said scaled output voltage signal, said differentiator being configured to generate a time derivative of said scaled output voltage signal,

A⁢ⅆVOⅆt,
and a time derivative of said output power control voltage signal,

ⅆVCⅆt;
and a soft saturation signal generator configured to determine onset of soft saturation based upon

A⁢ⅆVOⅆt⁢⁢and⁢⁢ⅆVCⅆt.
In one embodiment, A is less than one. The output power control voltage signal may comprise an error control signal for the RF power amplifier. The output power control voltage signal may be generated in response to said output voltage signal. The soft saturation signal generator may be configured to indicate soft saturation if

ⅆVOⅆt/ⅆVCⅆt<1A.
The soft saturation signal generator may be configured to indicate soft saturation if

A⁢ⅆVOⅆt<ⅆVCⅆt,⁢and⁢⁢if⁢⁢ⅆVCⅆt>0.
The soft saturation signal generator may comprise a gating mechanism configured to enable generation of a soft saturation indication signal if:

A⁢ⅆVOⅆt<ⅆVCⅆt;⁢and⁢⁢if⁢⁢VC>VREF,
where VREFis a fixed threshold voltage; and if

An electronic circuit comprising: a radio frequency (“RF”) power amplifier configured to generate an RF output power signal in response to an output power control voltage signal, VC; an output power control architecture coupled to said RF power amplifier, said output power control architecture being configured to obtain an output voltage signal, VO, indicative of said RF output power signal; and a soft saturation detection circuit coupled to said output power control architecture, said soft saturation detection circuit being configured to process VOand VCto determine onset of soft saturation of said RF power amplifier. The soft saturation detection circuit may be configured to determine onset of soft saturation of said RF power amplifier in response to a time derivative of said output voltage signal,

ⅆVOⅆt,
and a time derivative of said output power control voltage signal,

ⅆVCⅆt.
The soft saturation detection circuit may be configured to indicate soft saturation of said RF power amplifier if

A⁢ⅆVOⅆt<ⅆVCⅆt,⁢and⁢⁢if⁢⁢ⅆVCⅆt<0,
where A is constant over time.