Semiconductor device

Power cycle life of an intelligent power module that includes an IGBT is estimated by an abnormality detection circuit(s) while a chip temperature detection circuit or a case temperature detection circuit is outputting a chip overheating warning signal or a case overheating warning signal. Once the estimated power cycle life has reached a prescribed value, the abnormality detection circuit outputs an abnormality detection signal to forcedly and permanently stop operation of a driver circuit that drives an IGBT. The abnormality detection circuit may include a prescribed period calculation circuit that calculates the duration of the warning signal, a prescribed count calculation circuit that calculates the number of times the warning signal has been generated, and/or a cumulative time calculation circuit that calculates that the cumulative duration of periods in which the warning signal has been generated so as to estimate the power cycle life of the intelligent power module.

BACKGROUND OF THE INVENTION

Technical Field

The present invention relates to a semiconductor device including a power semiconductor device for power conversion and a control integrated circuit (IC) which drives the power semiconductor device and has a feature for protecting the power semiconductor device during abnormal operation thereof.

Background Art

Semiconductor devices known as intelligent power modules (IPMs), in which a power semiconductor device and a control IC are integrated together into the same package, are one known type of device for converting power. Depending on the use case, IPMs sometimes include a plurality of power semiconductor devices. For example, an IPM for driving a three-phase motor includes six power semiconductor devices. Each power semiconductor device is driven and controlled by the control IC.

Moreover, the control IC includes a protection circuit which, upon detecting an abnormality such as overcurrent, overheating, an abnormal decrease in supply voltage, or overheating of the package case, stops the switching operation of the power semiconductor device in order to protect the power semiconductor device from being damaged. There are also protection circuits that not only stop the switching operation of the power semiconductor device upon detecting an abnormality but also have features for detecting that an abnormality may soon occur and sending a notification to the exterior in advance (see Patent Document 1, for example).

The IPM disclosed in Patent Document 1 includes an insulated-gate bipolar transistor (IGBT) as the power semiconductor device, and the IGBT chip includes a diode for detecting temperature. If the temperature of the IGBT chip reaches a warning temperature, the control IC outputs a warning signal to the exterior. If the temperature of the IGBT chip reaches a protection temperature that is higher than the warning temperature, the control IC outputs a protection signal to stop the switching operation of the IGBT and also sends a notification to the exterior. In this way, when the control IC outputs a warning signal, measures such as reducing the drive capacity of the IGBT can be taken to inhibit temperature increases in the IGBT chip and make it possible to continue the switching operation of the IGBT without interruption.

In an IPM, if IGBT temperatures increase and decrease significantly due to the operating conditions, aluminum wire bonds on the surface of the IGBT chip experience heat stress, which results in fatigue on and promotes deterioration of the aluminum wire bonds and sometimes causes defects such as detachment to occur in the bonds. Also, significant increases and decreases in IGBT temperatures cause solder joints between the IGBT chip and insulating substrate as well as solder joints between the insulating substrate and case (copper base) to deteriorate, which can cause malfunctions to occur due to cracking or the like. This lifespan that is determined by heat stress is known as “power cycle life”, and as long as the IPM is used within the limits of this power cycle life, IPM reliability can be maintained.

RELATED ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

In a conventional IPM, the switching operation of the IGBT is not stopped even when the control IC outputs a warning signal, and therefore the switching operation of the IGBT is sometimes continued until immediately prior to when a protection signal is output. With this approach, the temperature of the IGBT sometimes increases and decreases while the warning signal is being output, which results in a corresponding increase in the number of heat stress events and a decrease in the power cycle life, thus negatively impacting reliability.

The present invention was made in view of these problems and aims to provide a semiconductor device in which reliability is improved by taking power cycle life during output of warning signals into account.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a semiconductor device, including: a power semiconductor device; a control IC including a driver circuit to drive the power semiconductor device and a protection circuit to protect the power semiconductor device; a case that houses the power semiconductor device and the control IC; a chip temperature detector connected to the control IC to measure a chip temperature of the power semiconductor device; and a case temperature detector connected to the control IC to measure a case temperature that is defined as a temperature at a portion of the semiconductor device other than the power semiconductor device, wherein the protection circuit in the control IC includes: a chip temperature detection circuit that, when the chip temperature rises and exceeds a first threshold, outputs a chip overheating warning signal so that a warning is communicated to a user, and, when the chip temperature further rises and exceeds a second threshold higher than the first threshold, outputs a chip overheating protection signal to the driver circuit so as to cause the driver circuit to stop switching operation of the power semiconductor device until the chip temperature returns to normal; a case temperature detection circuit that, when the case temperature rises and exceeds a third threshold, outputs a case overheating warning signal so that a warning is communicated to the user, and, when the case temperature further rises and exceeds a fourth threshold higher than the third threshold, outputs a case overheating protection signal to the driver circuit so as to cause the driver circuit to stop switching operation of the power semiconductor device until the case temperature returns to normal; and an abnormality detection circuit connected to one of the chip temperature detection circuit and the case temperature detection circuit to receive the chip overheating warning signal or the case overheating warning signal, the abnormality detection circuit estimating power cycle life of semiconductor device by processing the received chip or case overheating warning signal, and, when the estimated power cycle life has reached a prescribed threshold, generates and outputs an abnormality detection signal to the driver circuit so as to cause the driver circuit to forcedly and permanently stop the switching operation of the power semiconductor device.

In the semiconductor device configured as described above, including the abnormality detection circuit makes it possible to ascertain a degree of deterioration that would be accelerated by continuing to operate the power semiconductor device at high temperatures prior to when any damage occurs, thereby making it possible to improve reliability.

DETAILED DESCRIPTION OF EMBODIMENTS

Next, an embodiment of the present invention as exemplarily applied to an IPM that uses an IGBT as a power semiconductor device will be described in detail with reference to figures. Note that in the figures, portions that have the same reference characters represent the same components. Moreover, in the following description, the same reference characters are sometimes used both to label terminals and to indicate voltages, signals, or the like present at those terminals.

FIG. 1is a circuit diagram illustrating an example configuration of an IPM which constitutes a semiconductor device according to an embodiment of the present invention.FIG. 2illustrates an example configuration of an abnormality detection circuit.FIG. 3is a timing chart illustrating the operation of the IPM.

The IPM illustrated inFIG. 1includes an IGBT1, a control IC10, and a case temperature detector2. Note that although in this IPM a single IGBT1and control IC10set is illustrated, the IPM may include a plurality of sets of IGBTs1and control ICs10.

The IGBT1includes an IGBT chip1aand a chip temperature detector1barranged on that IGBT chip1a. Here, a diode is used as the chip temperature detector1b.

The case temperature detector2detects the temperature at a portion of the IPM other than the IGBT chip1a, such as the temperature of a case that houses the IPM and the control IC10, and here, a diode is used. Alternatively, a thermosensor such as a thermistor may be used as the case temperature detector2.

The control IC10includes a driver circuit11. The driver circuit11includes an input terminal IN to which an input signal is input, a protection signal input terminal STOP to which a switching stop signal is input, and an output terminal OUT from which a drive signal is output. The output terminal OUT of the driver circuit11is connected to a gate terminal of the IGBT chip1a, and an emitter terminal of the IGBT chip1ais connected to ground.

The control IC10further includes a protection circuit. This protection circuit of the control IC10includes a chip temperature detection circuit12, a case temperature detection circuit13, a chip abnormality detection circuit14, a case abnormality detection circuit15, and OR circuits16,17, and18.

The chip temperature detection circuit12includes a constant current circuit12a, comparators12band12c, and reference voltage sources12dand12e. One terminal of the constant current circuit12ais connected to an internal power supply Vcc, while the other terminal of the constant current circuit12ais connected to an anode terminal of the chip temperature detector1band to the inverting input terminals of the comparators12band12c. A cathode terminal of the chip temperature detector1bis connected to ground. The non-inverting input terminals of the comparators12band12care respectively connected to the positive terminals of the reference voltage sources12dand12e, and the negative terminals of the reference voltage sources12dand12eare connected to ground.

Moreover, the comparators12band12cexhibit hysteresis. Therefore, the reference voltage source12dhas both a protection detection threshold voltage Vthph and a protection deactivation threshold voltage Vthpl, and the reference voltage source12ehas both a warning detection threshold voltage Vthwh and a warning deactivation threshold voltage Vthwl.

The output terminal of the comparator12bis connected to one input terminal of the OR circuit16, and the output terminal of the comparator12cis connected to an input terminal of the chip abnormality detection circuit14and to an output terminal Wtoh which outputs a chip overheating warning signal. The other input terminal of the OR circuit16is connected to an output terminal of the chip abnormality detection circuit14, and the output terminal of the OR circuit16is connected to an output terminal Ptoh which outputs a chip overheating protection signal as well as to one input terminal of the OR circuit18. The output terminal of the OR circuit18is connected to the protection signal input terminal STOP of the driver circuit11.

The case temperature detection circuit13has the same circuit configuration as the chip temperature detection circuit12, and therefore the specific internal circuit configuration will not be described here. In other words, an input terminal of the case temperature detection circuit13is connected to an anode terminal of the case temperature detector2, and a cathode terminal of the case temperature detector2is connected to ground. An output terminal of the case temperature detection circuit13that outputs a case overheating protection signal is connected to one input terminal of the OR circuit17. An output terminal of the case temperature detection circuit13that outputs a case overheating warning signal is connected to an input terminal of the case abnormality detection circuit15and to an output terminal Wcoh which outputs the case overheating warning signal. The other input terminal of the OR circuit17is connected to an output terminal of the case abnormality detection circuit15, and the output terminal of the OR circuit17is connected to an output terminal Pcoh that outputs a case overheating protection signal as well as to the other input terminal of the OR circuit18.

The abnormality detection circuit estimates the power life cycle of the IPM by detecting one or more kinds of abnormalities. As illustrated inFIG. 2, the abnormality detection circuit14of this embodiment includes a prescribed period calculation circuit14a, a prescribed count calculation circuit14b, a cumulative time calculation circuit14c, and an OR circuit14d. The input terminals of the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14care connected to the output terminal of the comparator12cof the chip temperature detection circuit12. The output terminals of the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14care respectively connected to input terminals of the OR circuit14d, and the output terminal of the OR circuit14dis connected to the other input terminal of the OR circuit16.

Here, the prescribed period calculation circuit14aoutputs a chip overheating protection signal (abnormality detection signal) upon detecting that the chip overheating warning signal has continued for a prescribed period of time. The prescribed count calculation circuit14boutputs a chip overheating protection signal when the number of times that the chip overheating warning signal has been input reaches a prescribed number of times. Moreover, the cumulative time calculation circuit14coutputs a chip overheating protection signal when the cumulative duration of periods during which the chip overheating warning signal was input reaches a prescribed amount of time.

In the present embodiment, the abnormality detection circuit14includes the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14c. However, the abnormality detection circuit14may, as necessary, include only the prescribed period calculation circuit14a, only the prescribed count calculation circuit14b, or only the cumulative time calculation circuit14c. In this case, the OR circuit14dis unnecessary. Moreover, the abnormality detection circuit14may include any combination of two circuits among the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14c.

The abnormality detection circuit15can have the same configuration as the abnormality detection circuit14. Alternatively, the abnormality detection circuit15may include a combination of calculation circuits different from that of the abnormality detection circuit14.

Next, the operation of the IPM configured as described above will be described with reference toFIG. 3. When the IPM begins to be used, the driver circuit11receives an input signal and outputs a pulse signal to the output terminal OUT to switch the IGBT1ON and OFF. At this time, the constant current circuit12aof the chip temperature detection circuit12passes a constant current through the chip temperature detector1b, and the junction temperature Tj of the IGBT chip1ais monitored by detecting changes in the forward voltage of the chip temperature detector1bresulting from changes in the temperature of the IGBT chip1a.

When the junction temperature Tj of the IGBT chip1ais low, a detected voltage Vtj from the chip temperature detector1bis higher than the warning detection threshold voltage Vthwh of the reference voltage source12d, and therefore the comparator12coutputs a low (L) level signal. As a result, none of the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14ccalculate power cycle life, and therefore the abnormality detection circuit14outputs an L-level signal. At this time, the comparator12bis also outputting an L-level signal, and therefore no high (H) level switching stop signal is input to the protection signal input terminal STOP of the driver circuit11, and normal switching operation is continued on the basis of the input signal.

When the junction temperature Tj of the IGBT chip1aincreases and a detected voltage Vtj that is lower than the warning detection threshold voltage Vthwh is input to the inverting input terminal of the comparator12c, the output signal of the comparator12cinverts, and an H-level signal is output to the output terminal Wtoh. In this way, the control IC10sends a chip overheating warning signal to an external unit via the output terminal Wtoh to provide notification to the external unit that the junction temperature Tj of the IGBT chip1ahas increased to a warning level. At this time, the abnormality detection circuit14receives the H-level signal as input and begins calculating power cycle life.

When the junction temperature Tj of the IGBT chip1aincreases further and the detected voltage Vtj that is input to the inverting input terminal of the comparator12bdecreases and reaches the protection detection threshold voltage Vthph, the output signal of the comparator12bis inverted, and an H-level chip overheating protection signal is output to the output terminal Ptoh. This chip overheating protection signal is also input via the OR circuit18to the protection signal input terminal STOP of the driver circuit11as a switching stop signal, thereby causing the driver circuit11to force-stop the switching operation. During this protection period in which switching operation is stopped, the driver circuit11does not output any pulse signal to the output terminal OUT.

Due to the switching operation of the IGBT1having been stopped, the junction temperature Tj of the IGBT chip1adecreases, and when the detected voltage Vtj that is input to the inverting input terminal of the comparator12bincreases and reaches the protection deactivation threshold voltage Vthpl, the output signal of the comparator12bis inverted. As a result, the outputs of the OR circuits16and18take the L level, and the driver circuit11resumes the switching operation.

When the junction temperature Tj of the IGBT chip1adecreases further and the detected voltage Vtj that is input to the inverting input terminal of the comparator12cincreases and reaches the warning deactivation threshold voltage Vthwl, the output signal of the comparator12cis inverted and takes the L level, thus causing the output terminal Wtoh to also take the L level. At this time, the abnormality detection circuit14receives this L-level signal as input and ends or suspends calculation of power cycle life.

Meanwhile, if during the overheating warning period in which the comparator12cis outputting the H-level chip overheating warning signal the abnormality detection circuit14calculates (estimates) that the power cycle life has been reached, the abnormality detection circuit14outputs an H-level chip overheating protection signal (abnormality detection signal). This chip overheating protection signal is input to the driver circuit11via the OR circuits16and18, and therefore regardless of whether the overheating warning period is still ongoing, the driver circuit11force-stops (i.e., overrides the chip temperature detection circuit and permanently stops) the switching operation.

The chip overheating warning and chip overheating protection operations performed for the IGBT chip1acan be applied in a similar manner to case overheating warning and case overheating protection operations performed using the case temperature detector2, the case temperature detection circuit13, the abnormality detection circuit15, and the OR circuit17. Therefore, a description of the case overheating warning and case overheating protection operations will be omitted here.

In this way, if the abnormality detection circuits14and15calculate that the power cycle life has been reached during the overheating warning period, the driver circuit11force-stops the switching operation, thereby making it possible to further improve the reliability of the IPM.

Next, specific example configurations for the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14cincluded in the abnormality detection circuits14and15will be described.

FIG. 4is a circuit diagram illustrating an example configuration of the prescribed period calculation circuit.FIG. 5shows the logical values at relevant parts for explaining the operation of the prescribed period calculation circuit.FIG. 6is a timing chart illustrating the operation of the prescribed period calculation circuit.

As illustrated inFIG. 4, the prescribed period calculation circuit14aincludes a counter circuit21, an oscillator circuit22, a NOT circuit23, an XOR circuit24, and an AND circuit25. An input terminal of the prescribed period calculation circuit14ais connected to the output terminal of the comparator12cof the chip temperature detection circuit12, and the output terminal of the prescribed period calculation circuit14ais connected to one of the input terminals of the OR circuit14d.

In the prescribed period calculation circuit14a, the counter circuit21includes n units of D flip-flops DFF0to DFFn−1, which are cascade-connected. In other words, in the D flip-flops DFF0to DFFn−1, each inverted output terminal (QB) is connected to the respective input terminal (D), while the clock input terminal (CLK) is used as a data input terminal and the output terminal (Q) is used as a data output terminal. The clock input terminal of the first-stage D flip-flop DFF0is connected to an output terminal of the oscillator circuit22, and the output terminal (Q) of the last-stage D flip-flop DFFn−1 is connected to one input terminal of the XOR circuit24. The reset input terminal (RST) of each of the D flip-flops DFF0to DFFn−1 is connected to an output terminal of the NOT circuit23, and an input terminal of the NOT circuit23is connected to the input terminal of the prescribed period calculation circuit14a. In the present embodiment, this NOT circuit23functions as a reset circuit. The input terminal of the prescribed period calculation circuit14ais further connected to the other input terminal of the XOR circuit24and to one input terminal of the AND circuit25, and the other input terminal of the AND circuit25is connected to an output terminal of the XOR circuit24. The output terminal of the AND circuit25constitutes the output terminal of the prescribed period calculation circuit14a. Here, the prescribed period that is calculated by the prescribed period calculation circuit14ais determined by the oscillation frequency of the oscillator circuit22and by the value of n (the number of stages in the counter circuit21).

As illustrated inFIGS. 5 and 6, in the prescribed period calculation circuit14a, during low-temperature operation in which the junction temperature Tj of the IGBT chip1ais lower than a warning threshold temperature that corresponds to the warning detection threshold voltage Vthwh, the chip overheating warning signal output by the comparator12cis at the L level. Therefore, the AND circuit25, in which this L-level chip overheating warning signal is input to the one input terminal, outputs an L-level overheating protection signal.

When the junction temperature Tj of the IGBT chip1areaches the warning threshold temperature that corresponds to the warning detection threshold voltage Vthwh and the comparator12coutputs an H-level chip overheating warning signal, the NOT circuit23to which this H-level chip overheating warning signal is input outputs an L-level signal. As a result, the D flip-flops DFF0to DFFn−1 that receive this L-level signal at the reset input terminals (RST) thereof are reset, an L-level signal is output at the output terminals (Q), and an H-level signal is output at the inverted output terminals (QB).

Next, when the first-stage D flip-flop DFF0receives at the clock input terminal (CLK) thereof an output signal from the oscillator circuit22, at the timing of the rising edge of that signal, the H-level signal from the inverted output terminal (QB) is loaded into the input terminal (D) and stored. As a result, the D flip-flop DFF0outputs an H-level signal at the output terminal (Q) thereof and supplies this signal to the clock input terminal (CLK) of the second-stage D flip-flop DFF1. Therefore, the second-stage D flip-flop DFF1performs the same operation as the first-stage D flip-flop DFF0, this same operation is repeated up through the last-stage D flip-flop DFFn−1, and this last-stage D flip-flop DFFn−1 outputs an H-level signal. Note that although there is a certain amount of delay time from when all of the D flip-flops DFF0to DFFn−1 are reset until when the H-level signals are output from the output terminals (Q), here, the effects of this delay time are treated as being negligible.

At this time, the XOR circuit24takes as input the H-level chip overheating warning signal and the output signal of the D flip-flops DFF0to DFFn−1 and therefore outputs an L-level signal. As a result, the AND circuit25which receives this L-level signal at the other input terminal thereof outputs an L-level signal.

Then, in synchronization with the timing of the rising edges of the output signal of the oscillator circuit22, the D flip-flops DFF0to DFFn−1 progressively performs frequency divisions on the output signal of the oscillator circuit22. Once a prescribed period of time elapses from when the chip overheating warning signal was input, the counter circuit21completes its count-up operation and the last-stage D flip-flop DFFn−1 outputs an L-level signal. As a result, the XOR circuit24takes as input the H-level chip overheating warning signal and the L-level signal from the D flip-flop DFFn−1 and outputs an H-level signal. This H-level signal is input to the AND circuit25along with the H-level chip overheating warning signal, and therefore the AND circuit25outputs an H-level overheating protection signal (abnormality detection signal).

Note that if the chip overheating warning signal takes the L level before the prescribed period of time elapses, at that point the D flip-flops DFF0to DFFn−1 are reset and the control IC10resumes low-temperature operation.

FIG. 7is a circuit diagram illustrating an example configuration of the prescribed count calculation circuit.FIG. 8shows the logical values at relevant parts for explaining the operation of the prescribed count calculation circuit.FIG. 9is a timing chart illustrating the operation of the prescribed count calculation circuit. Note that inFIG. 7, the D flip-flops that form a counter circuit are given the same reference characters as the D flip-flops DFF0to DFFn−1 in the counter circuit21inFIG. 4, and a detailed description of these D flip-flops will be omitted here.

As illustrated inFIG. 7, the prescribed count calculation circuit14bincludes a counter circuit31, a reset circuit32, a D flip-flop DFF, a NOT circuit33, and an AND circuit34. An input terminal of the prescribed count calculation circuit14bis connected to the output terminal of the comparator12cof the chip temperature detection circuit12, and the output terminal of the prescribed count calculation circuit14bis connected to one of the input terminals of the OR circuit14d.

In the prescribed count calculation circuit14b, the reset circuit32includes a resistor35, a capacitor36, and a NOT circuit37. One terminal of the resistor35is connected to the internal power supply Vcc, while the other terminal of the resistor35is connected to one terminal of the capacitor36and to an input terminal of the NOT circuit37, and the other terminal of the capacitor36is connected to ground. An output terminal of the NOT circuit37is connected to the reset input terminals of the D flip-flop DFF and the D flip-flops DFF0to DFFn−1 of the counter circuit31. An output terminal of the counter circuit31is connected to the clock input terminal (CLK) of the D flip-flop DFF and to an input terminal of the NOT circuit33. The output terminal (Q) of the D flip-flop DFF and an output terminal of the NOT circuit33are connected to input terminals of the AND circuit34, and an output terminal of the AND circuit34constitutes the output terminal of the prescribed count calculation circuit14b. Here, the prescribed count that is calculated by the prescribed count calculation circuit14bis determined by the value of n (the number of stages in the counter31).

In the prescribed count calculation circuit14b, when the power is turned on, the capacitor36of the reset circuit32is charged via the resistor35by the internal power supply Vcc. Once the charge voltage of the capacitor36exceeds the threshold voltage of the NOT circuit37, the reset circuit32outputs an L-level reset signal. This L-level reset signal is supplied to the reset input terminals (RST) of the D flip-flop DFF and the D flip-flops DFF0to DFFn−1 of the counter circuit31. As a result, the D flip-flop DFF and the D flip-flops DFF0to DFFn−1 of the counter circuit31are each reset. At this time, the AND circuit34takes an L-level signal from the D flip-flop DFF as input and therefore outputs an L-level overheating protection signal.

As illustrated inFIGS. 8 and 9, here, during low-temperature operation in which the junction temperature Tj of the IGBT chip1ais lower than a preset threshold temperature that corresponds to the warning detection threshold voltage Vthwh, the chip overheating warning signal output by the comparator12cis at the L level. The D flip-flop DFF and the D flip-flops DFF0to DFFn−1 of the counter circuit31that receive this L-level chip overheating warning signal respectively remain in the reset state.

When the junction temperature Tj of the IGBT chip1areaches the prescribed temperature that corresponds to the warning detection threshold voltage Vthwh and the comparator12coutputs an H-level chip overheating warning signal, this chip overheating warning signal is input to the prescribed count calculation circuit14b. In the prescribed count calculation circuit14b, the chip overheating warning signal is input to the clock input terminal (CLK) of the D flip-flop DFF0of the counter circuit31. In the D flip-flop DFF0, at the timing of the rising edge of the chip overheating warning signal, an H-level signal from the inverted output terminal (QB) is loaded into the input terminal (D) and stored. As a result, the D flip-flop DFF0outputs an H-level signal at the output terminal (Q) thereof and supplies this signal to the clock input terminal (CLK) of the second-stage D flip-flop DFF1. Therefore, the second-stage D flip-flop DFF1performs the same operation as the first-stage D flip-flop DFF0, and this same operation is repeated up through the D flip-flop DFF that is connected to the output terminal of the counter circuit31. As a result, the counter circuit31and the D flip-flop DFF each output an H-level signal.

At this time, the NOT circuit33logically inverts the output signal from the counter circuit31and inputs the resulting L-level signal to one input terminal of the AND circuit34, which therefore outputs an L-level overheating protection signal.

Then, when the junction temperature Tj of the IGBT chip1adecreases to below the prescribed temperature that corresponds to the warning detection threshold voltage Vthwh, the comparator12coutputs an L-level signal. In this case, even when this L-level signal is input to the prescribed count calculation circuit14b, there is no change in the operation of the prescribed count calculation circuit14b.

Next, when the junction temperature Tj of the IGBT chip1aonce again reaches the prescribed temperature that corresponds to the warning detection threshold voltage Vthwh and the comparator12coutputs an H-level chip overheating warning signal, this chip overheating warning signal is input to the prescribed count calculation circuit14b. In the prescribed count calculation circuit14b, in synchronization with the timing of the rising edge of this chip overheating warning signal that was input for the second time, just the output of the first-stage D flip-flop DFF0is inverted.

After this, each time that the junction temperature Tj of the IGBT chip1aexceeds the preset threshold temperature that corresponds to the warning detection threshold voltage Vthwh, the counter circuit31takes the resulting chip overheating warning signal as input as a CLK signal and counts the number of times that the chip overheating warning signal has been input.

When the number of times that the chip overheating warning signal has been input reaches a prescribed count N, the counter circuit31outputs an L-level signal. As a result, the H-level signal from the D flip-flop DFF and an H-level signal from the NOT circuit33that has inverted the output signal of the counter circuit31are input to the AND circuit34, which therefore outputs an H-level overheating protection signal (abnormality detection signal).

FIG. 10is a circuit diagram illustrating an example configuration of the cumulative time calculation circuit.FIG. 11shows the logical values at relevant parts for explaining the operation of the cumulative time calculation circuit.FIG. 12is a timing chart illustrating the operation of the cumulative time calculation circuit.

As illustrated inFIG. 10, the cumulative time calculation circuit14chas a configuration in which an oscillator circuit45and an AND circuit46have been added to the prescribed count calculation circuit14b. In other words, the cumulative time calculation circuit14cincludes a counter circuit41, a reset circuit42, a D flip-flop DFF, a NOT circuit43, and an AND circuit44which are configured the same as in the prescribed count calculation circuit14b, as well as the oscillator circuit45and the AND circuit46. An input terminal of the cumulative time calculation circuit14cis connected to the output terminal of the comparator12cof the chip temperature detection circuit12, and the output terminal of the cumulative time calculation circuit14cis connected to one of the input terminals of the OR circuit14d.

The input terminal of the cumulative time calculation circuit14cis connected to one input terminal of the AND circuit46, while the other input terminal of the AND circuit46is connected to an output terminal of the oscillator45, and an output terminal of the AND circuit46is connected to the clock input terminal (CLK) of the first-stage D flip-flop DFF0of the counter circuit41. Here, the cumulation time that is calculated by the cumulative time calculation circuit14cis determined by the oscillation frequency of the oscillator circuit45and by the value of n (the number of stages in the counter circuit41).

In the cumulative time calculation circuit14c, when the power is turned on, an L-level chip overheating warning signal is input from the comparator12cof the chip temperature detection circuit12, and therefore the AND circuit46prevents an output signal from the oscillator circuit45from being supplied to the counter circuit41. The reset circuit42outputs an L-level reset signal after a prescribed period of time has elapsed from when the power was turned on, thereby resetting the D flip-flop DFF and the D flip-flops DFF0to DFFn−1 of the counter circuit41. As a result, the counter circuit41and the D flip-flop DFF each output an L-level signal. At this time, the AND circuit44takes the L-level signal from the D flip-flop DFF as input and therefore outputs an L-level overheating protection signal.

Here, during low-temperature operation in which the junction temperature Tj of the IGBT chip1ais lower than the prescribed temperature that corresponds to the warning detection threshold voltage Vthwh, the chip overheating warning signal output by the comparator12cremains at the L level. Therefore, as illustrated inFIGS. 11 and 12, the output signals of the D flip-flop DFFn−1 of the counter circuit41, the D flip-flop DFF, and the AND circuit44are at the L level at this time.

When the junction temperature Tj of the IGBT chip1areaches the prescribed temperature that corresponds to the warning detection threshold voltage Vthwh and the comparator12coutputs an H-level chip overheating warning signal, this chip overheating warning signal is input to the one input terminal of the AND circuit46. As a result, the output signal of the oscillator circuit45is input to the counter circuit41, and the counter circuit41begins counting the output signal of the oscillator circuit45. This counting of the output signal of the oscillator circuit45is continued for the duration of the overheating warning period during which the H-level chip overheating warning signal is being input.

Next, when the junction temperature Tj of the IGBT chip1aexceeds the prescribed temperature, the AND circuit46allows the output signal of the oscillator circuit45to pass through, and the counter41resumes counting by adding to the previous count value.

In this way, by counting the output signal of the oscillator circuit45only during the overheating warning period in which an H-level chip overheating warning signal is being input, it is possible to calculate the cumulative overheating warning period.

Here, if a prescribed cumulative time elapses while counting the output signal of the oscillator circuit45, the last-stage D flip-flop DFFn−1 of the counter circuit41outputs an L-level signal. As a result, an H-level signal from the D flip-flop DFF and an H-level signal from the NOT circuit43that has inverted the output signal of the D flip-flop DFFn−1 are input to the AND circuit44, which therefore outputs an H-level overheating protection signal (abnormality detection signal).

Although the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14cas described above are part of the abnormality detection circuit14for protecting against chip overheating, the abnormality detection circuit15for protecting against case overheating has the same configuration.

Moreover, although in the embodiment of the semiconductor device described above the counter circuits21,31, and41of the prescribed period calculation circuit14a, the prescribed count calculation circuit14b, and the cumulative time calculation circuit14care constituted by rising edge-triggered D flip-flops, the present invention is not limited to this configuration. For example, the counter circuits21,31, and41may be constituted by falling edge-triggered D flip-flops, JK flip-flops, or the like.

Moreover, in this semiconductor device, the abnormality detection circuits14and15do not necessarily need to include all of the prescribed period calculation circuit, the prescribed count calculation circuit, and the cumulative time calculation circuit; and any of these circuits can be freely selected and used as necessary. Furthermore, although this semiconductor device includes both of the abnormality detection circuits14and15, either one of these circuits may be included alone.