Semiconductor device and semiconductor device examination method

A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2021-147753 filed on Sep. 10, 2021; the entire contents of which are incorporated herein by reference.

FIELD

The present embodiment relates to a semiconductor device and a semiconductor device examination method.

BACKGROUND

A scan test using a scan circuit is known as one of semiconductor device examination methods. In the scan circuit, flip-flops (hereinafter referred to as FFs) in the circuit are replaced with scan FFs and a scan chain is configured by serially connecting the scan FFs.

In the scan test using the scan circuit, since all the scan FFs under test are simultaneously switched during scan shift operation, influence of switching noise becomes large.

A possible way to reduce the influence of switching noise is to decrease the number of scan data that transition simultaneously. This method however increases the test time period as the number of scan patterns increases.

DETAILED DESCRIPTION

A semiconductor device of the present embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.

An embodiment will be described below with reference to the accompanying drawings.

FIG.1is a block diagram illustrating an example of a configuration of a semiconductor device according to the embodiment.

The semiconductor device1of the present embodiment includes a shift-in terminal2, a scan shift enable terminal3, a scan clock terminal4, a scan-in terminal5, a shift-out terminal6, a scan-out terminal7, a shift clock control circuit8, an FF9, an AND circuit10, a decompressor11, a scan chain12, a compressor13, and an FF14. The semiconductor device1is subjected to a scan test by an examination device such as a large-scale tester.

The scan chain12includes a plurality of scan chains SC1, SC2, . . . , SCm. Note that any one scan chain or every scan chain among the plurality of scan chains SC1to SCm is also referred to as a scan chain SC. The scan chain SC is configured as a shift register by serially connecting a plurality of scan FFs20in the semiconductor device1. Note that the number of scan chains SC may be two or more.

The shift clock control circuit8supplies, in accordance with shift-in data input through the shift-in terminal2, a control signal for controlling non-inversion/inversion of a scan clock to a TE_IV terminal of each scan FF20of the scan chain SC.

A scan shift enable signal is input from the scan shift enable terminal3to the FF9. The FF9holds a state of the scan shift enable signal at a rising edge of a scan clock signal and outputs the scan shift enable signal to the AND circuit10.

The AND circuit10performs AND calculation of the scan shift enable signal input from the scan shift enable terminal3and a signal output from the FF9, and supplies a test enable signal as a result of the calculation to a TE terminal of each scan FF20of the scan chain SC. In other words, the AND circuit10synchronizes the scan shift enable signal with the scan clock signal and supplies the synchronized signal as a test enable signal to each scan FF20of the scan chain SC.

A compressed test pattern is input from the examination device to the decompressor11through the scan-in terminal5. The decompressor11decompresses (expands) the compressed test pattern and supplies the decompressed test pattern to a TI terminal of a leading scan FF20of each of the scan chains SC1to SCm. The scan chains SC1to SCm perform scan shift operation in accordance with the non-inverted or inverted scan clock signal as described later.

The compressor13compresses data output from the scan chains SC1to SCm and outputs the compressed data to the FF14. The FF14sequentially acquires the data output from the compressor13at every rising edge of the scan clock signal and outputs the acquired data to the examination device through the scan-out terminal7. The examination device compares the data input from the scan-out terminal7with an expectation value and determines whether or not failure has occurred to the semiconductor device1.

FIG.2is a circuit diagram illustrating an example of a circuit configuration of each scan FF.

As illustrated inFIG.2, each scan FF20includes a selector21, an AND circuit22, an XOR circuit23, and an FF24.

For example, normal data from a combination circuit is input to one of terminals of the selector21, and scan test data from the decompressor11or a scan FF20at a previous stage is input to the other terminal. The selector21outputs one of the pieces of data to the FF24based on the test enable signal from the AND circuit10. Specifically, the selector21outputs the normal data to the FF24when the test enable signal is at L level, or outputs the scan test data to the FF24when the test enable signal is at H level.

The AND circuit22calculates AND (logical conjunction) of the control signal from the shift clock control circuit8and the test enable signal from the AND circuit10and outputs a result of the calculation to the XOR circuit23. The test enable signal is at H level during execution of a scan test. Thus, an L-level signal is output from the AND circuit22to the XOR circuit23when the control signal from the shift clock control circuit8is at L level, or an H-level signal is output from the AND circuit22to the XOR circuit23when the control signal from the shift clock control circuit8is at H level.

The output signal from the AND circuit22is input to one of terminals of the XOR circuit23, and the scan clock signal from the scan clock terminal4is input to the other terminal. The XOR circuit23calculates XOR (exclusive disjunction) of the output signal from the AND circuit22and the scan clock signal from the scan clock terminal4and outputs a scan shift clock signal (non-inverted scan clock signal or inverted scan clock signal) as a result of the calculation to the FF24.

Specifically, when the output signal from the AND circuit22is at H level, the XOR circuit23outputs, to the FF24, an inverted scan clock signal obtained by inverting the scan clock signal. When the output signal from the AND circuit22is at L level, the XOR circuit23intactly outputs the scan clock signal, namely, outputs a non-inverted scan clock signal to the FF24.

In this manner, a shift clock generation circuit configured to generate a scan shift clock signal is constituted by the AND circuit22and the XOR circuit23, the AND circuit22being configured to perform AND calculation of the control signal and the test enable signal, the XOR circuit23being configured to perform XOR calculation of the output signal from the AND circuit22and the scan clock signal.

The FF24acquires the scan test data at every rising edge of the non-inverted scan clock signal or inverted scan clock signal from the XOR circuit23and outputs the acquired scan test data to a scan FF20at a next stage.

FIG.3is a waveform diagram illustrating an operation waveform of each scan FF when the control signal is at H level, andFIG.4is a waveform diagram illustrating an operation waveform of each scan FF when the control signal is at L level.

As illustrated inFIG.3, AND calculation of the control signal and the test enable signal is performed at the AND circuit22. An H-level signal is output from the AND circuit22to the XOR circuit23when the control signal is at H level and the test enable signal is at H level.

XOR calculation of the scan clock signal and the output signal from the AND circuit22is performed at the XOR circuit23. Thus, the scan clock signal is inverted and output from the XOR circuit23in a duration in which the output signal from the AND circuit22is at H level.

As illustrated inFIG.4, an L-level signal is output from the AND circuit22to the XOR circuit23even when the test enable signal is at H level while the control signal is at L level.

XOR calculation of the scan clock signal and the output signal from the AND circuit22is performed at the XOR circuit23, and the scan clock signal is intactly output from the XOR circuit23.

In this manner, each scan FF20generates the non-inverted scan clock signal or the inverted scan clock signal in accordance with the control signal from the shift clock control circuit8. Then, the scan FF20performs scan shift operation in accordance with the generated non-inverted scan clock signal or inverted scan clock signal.

The shift clock control circuit8individually outputs the control signal to the scan chains SC1to SCm. For example, the shift clock control circuit8outputs the control signal at L level to the scan chain SC1, and outputs the control signal at H level to the scan chain SC2.

In this case, each scan FF20of the scan chain SC1performs scan shift operation in accordance with the non-inverted scan clock signal, and each scan FF20of the scan chain SC2performs scan shift operation in accordance with the inverted scan clock signal.

More specifically, the shift clock control circuit8generates the control signal and outputs the generated control signal to the plurality of scan chains SC so that a ratio of scan chains SC that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan chains SC is substantially equal to a ratio of scan chains SC that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan chains SC.

When the plurality of scan chains SC each include a different number of scan FFs20, the shift clock control circuit8generates the control signal and outputs the generated control signal to the plurality of scan chains SC so that a ratio of scan FFs20that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan FFs20is substantially equal to a ratio of scan FFs20that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan FFs20.

Accordingly, the semiconductor device1of the present embodiment controls a ratio of simultaneously switched scan FFs20.

Subsequently, a process of examination of the semiconductor device1thus configured will be described below.FIG.5is a flowchart illustrating an example of the process of the semiconductor device examination.

First, the shift clock control circuit8outputs, to each of the plurality of scan chains SC, a control signal that non-inverts or inverts a scan clock signal (S1). Subsequently, each scan FF20generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal (S2). Lastly, the scan FF20performs scan shift operation in accordance with the non-inverted scan clock signal or the inverted scan clock signal (S3), and ends processing.

As a result of the above-described processing, scan shift operation can be performed for each scan chain SC in accordance with the non-inverted scan clock signal or the inverted scan clock signal.

FIG.6is a waveform diagram illustrating a waveform of switching noise when all scan FFs are simultaneously switched, andFIG.7is a waveform diagram illustrating a waveform of switching noise when a ratio of simultaneously switched scan FFs is controlled.

As illustrated inFIG.6, when the control signal at L level is input to the scan chains SC1to SCm, non-inverted scan clock signals are generated at all scan FFs20of the scan chains SC1to SCm.

Thus, the FFs24of all scan FFs20of the scan chains SC1to SCm are switched at every rising edge of the scan clock signal. As a result, switching noise having a large peak at every rising edge of the scan clock signal is generated.

As illustrated inFIG.7, when the control signal at L level and the control signal at H level are alternately input to the scan chains SC1to SCm, non-inverted scan clock signals are generated at the scan FFs20of the scan chains SC1, SC3, . . . to which the control signal at L level is input, and inverted scan clock signals are generated at the scan FFs20of the scan chains SC2, SC4, . . . to which the control signal at H level is input.

Thus, the FFs24of the scan FFs20of the scan chains SC1, SC3, . . . are switched at every rising edge of the scan clock signal. The FFs24of the scan FFs20of the scan chains SC2, SC4, . . . are switched at every falling edge of the scan clock signal. As a result, switching noise generation is dispersed to the rising edge and falling edge of the scan clock signal, and switching noise having a peak smaller than the peak inFIG.6is generated.

As described above, each scan FF20has a function to non-invert/invert the scan clock signal in accordance with the control signal when the test enable signal is at H level. The shift clock control circuit8can control the control signal for each scan chain SC. For example, the shift clock control circuit8outputs the control signal at H level to the scan chains SC1, SC3, . . . and outputs the control signal at L level to the scan chains SC2, SC4, . . . .

Influence of switching noise can be dispersed to every rising edge and falling edge of the scan clock signal by controlling, with the shift clock control circuit8, a ratio of scan FFs20that operate in accordance with a non-inverted/inverted scan clock signal, in other words, by controlling the number of simultaneously switched scan FFs20. Accordingly, without increasing the number of scan patterns, it is possible to lower a switching noise peak generated due to simultaneous switching, thereby stably executing a scan test.

Thus, according to the semiconductor device1of the present embodiment, it is possible to reduce influence of switching noise without increase in a test time period.