Feed-forward control system with current estimator

A method and apparatus for estimating capacitor current in a feed-forward control system includes a circuit that conducts a current through an output capacitor to ground and estimates a current magnitude for the current in an output current estimator. The current estimator generates a voltage that corresponds to the estimated current magnitude by creating a voltage drop across an estimator circuit capacitor that equals a voltage drop across the output capacitor, by creating a voltage drop across an output of an RC network of the estimator circuit that equals or is proportional to a voltage drop across the output capacitor due to parasitic inductance and parasitic resistance of the output capacitor. The voltage drop across the output of the RC network of the estimator circuit is proportional to current flowing through the parasitic inductance and resistance of the output capacitor.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to control circuits and systems and, more particularly, feed-forward control circuits and systems.

BACKGROUND

It is commonplace for digital integrated circuits to operate at higher frequencies that can create parasitic impedances for the various circuit elements. As the operating frequencies increase, the effects of parasitic impedances of the capacitors should often be considered when fine-tuning or designing a circuit or system. The effects of equivalent series resistance (ESR) and equivalent series inductance (ESL) in a typical digital application should be considered to properly predict circuit performance in design because the ESR and ESL of chip capacitors can dramatically alter the voltage drops across the integrated circuit (IC). The use of capacitors in digital circuitry is not new, but as microprocessor clock speeds increase, the parasitic effects of capacitors within integrated circuits (ICs) become more important.

As the ESR of a device increases, an increase in the ripple voltage for a given parasitic impedance of a capacitor. Additionally, increases in ESR can create unwanted voltage drops that affect circuit operation. Parasitic inductance also affects circuit operation by adding unwanted noise and undesired voltage drops. An increase in inductance results in an increase in the ripple voltage from switching and an increase in undesired voltage drops that should be accounted for in circuit design. Accounting for parasitic impedances (resistance and inductance) of a capacitor can be difficult especially when a fast response is needed in a feedback loop to support high frequency operations. While there are existing systems and/or circuit designs that provide fast feedback despite the parasitic impedances, such solutions are often complex and consume integrated circuit real estate and power.

The use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION

FIG. 1is a partial schematic and partial block diagram of a prior art feed-forward control system. Near-optimum dynamic regulation of a DC-DC converter is obtained by adding a feed-forward response of an output current to a current-mode controller. The results are near zero output impedance with reduced magnitude, duration, and energy content of the output-voltage transient after a transient change of output current.FIG. 1illustrates the basic concept of load-current feed-forward circuit.

As may be seen, a DC-DC voltage generator10is connected to an output node Vout. Output node Vout is connected to an output capacitor12, a load resistor Rload and an input of a first differential transconductance amplifier16. A resistor18shown in dashed lines represents parasitic resistance (ESR) of capacitor12(Cout). First differential transconductance amplifier16is also connected to receive a reference voltage Vref. An output of first differential transconductance amplifier16is connected to a summing node20or circuit as well as to a capacitor22(Ccomp). Capacitor22is also connected to a resistor24(Rcomp) that is further connected to ground. The summing node20or circuit is also connected to load current and produces a sum of load current and the output of differential transconductance amplifier16to an input of a comparator26that is further connected at a second input to DC-DC voltage generator10output current.

DC-DC voltage generator10produces an output voltage at Vout to differential transconductance amplifier16that compares the output voltage to a reference voltage and produces an output error signal based on the difference of the two input signals. The result of the comparison is added to the load current that is then compared with DC-DC voltage generator10output current. By summing the voltage error signal and signal proportional to load current and feeding it to current mode comparator, the control loop will follow load current variation.

FIG. 2illustrates a current mode control circuit with a capacitor feed-forward configuration wherein the feed-forward signal is the current of output capacitor rather that load current. The connections inFIG. 2are substantially similar toFIG. 1except that the second input of the second comparator26is connected to the output capacitor12current. One advantage of this circuit is that implementation is simpler. Adding a sense resistor or small current transformer in capacitor filter network is not practical, however, with complex output filter networks. Furthermore, the sense resistor adds complexity and impacts ripple performance. Accordingly, the embodiment ofFIG. 2may be advantageous for limited circumstances.

FIG. 3is a schematic showing a capacitor model with parasitic inductance and resistance. The capacitor model includes a capacitor12that is in series with an inductor19and a resistor18. The parasitic elements, namely, inductor19and a resistor18introduce parasitic inductance ESL and parasitic resistance ESR, respectively. For higher frequencies, parasitic impedance has inductive and resistive elements for a capacitor that should be accounted for in evaluating circuit performance.

FIG. 4is a partial schematic and partial block diagram illustrating an embodiment of a voltage regulator in a feed-forward control system. One aspect of the prior approaches shown inFIGS. 1 and 2is that a current is being measured. According to the various embodiments including the embodiment ofFIG. 4, the capacitor current of the output capacitor is estimated. By estimating the capacitor current, circuit complexity and problems associated with direct capacitor current measurements are reduced.FIG. 4illustrates such an approach by using a measured output voltage feedback signal, already available in current mode control, to estimate the output capacitor current. Essentially, a fast feed-forward control loop using lossless capacitor current sensing is used to estimate the output capacitor current to generate a feedback signal to the voltage regulator.

Referring toFIG. 4, DC-DC voltage generator10produces an output signal to output node Vout. Output node Vout is connected to output capacitor12(Cout) and load resistor14(Rload) as well as to a first input of first linear amplifier16and to Icap estimator28. A second input of first differential transconductance amplifier16is connected to receive a reference voltage Vref. First linear amplifier16produces an output signal based on a difference in two input signals. An output of the differential amplifier16is produced to a first input of a comparator26. A voltage signal representing an estimated output capacitor current through capacitor12is produced to a second input of second linear amplifier26by Icap estimator28. Comparator26produces an output to DC-DC voltage generator10to adjust the output voltage produced by DC-DC voltage generator10.

Output terminal Vout is further connected to an output capacitor12and to a load resistor14. A resistor18is shown in dashed lines to represent parasitic resistance of capacitor12. A current proportional to the difference between the two voltages produced to first linear amplifier16is produced to a first terminal of a second linear amplifier26as well as to a capacitor22. Capacitor22is further connected to a resistor24that is also connected to ground.

Icap Estimator28is connected between a second terminal of comparator26and the output terminal Vout. Icap estimator28is configured to generate a voltage that corresponds to an estimated current flowing through output capacitor12. The voltage produced by Icap Estimator22is compared with a voltage that appears across capacitor22and resistor24due to a current output produced by first differential amplifier16. The output voltage of the comparator26comprises a feedback signal (error signal) that is produced to generator10to adjust the voltage produced by generator10.

In operation, a current that flows from Vout through output capacitor12is a function of frequency and parasitic impedance of output capacitor12as well as an AC magnitude of Vout. Accordingly, for a given frequency, the current through output capacitor12will vary with the output voltage Vout. Accordingly, Icap estimator28, which is connected to receive Vout, is able to estimate the current through output capacitor12based on a magnitude of Vout and to produce a voltage signal that corresponds to the estimated value of the current through output capacitor12. This corresponding signal is then compared to a voltage across capacitor22and resistor24generated by differential transconductance amplifier16. The output of comparator26then is produced to DC-DC voltage generator10to adjust the output voltage produced by DC-DC voltage generator10.

FIG. 5is a partial schematic and a partial block diagram illustrating additional details of an embodiment of a voltage generator and regulator that includes a current estimator in a feed-forward control system. As disclosed in relation toFIG. 4, the system ofFIG. 5includes the DC-DC voltage generator10, linear amplifier16and comparator26, Icap current estimator28, output capacitor12and load resistor14. Comparator26produces a first error signal to DC-DC voltage generator10based on a difference of a voltage signal produced by Icap estimator28and a voltage signal that is based on a second error signal produced by linear amplifier16in the form of a current signal. The second error signal is based upon a difference between Vout and a reference voltage.

As may further be seen, DC-DC voltage generator10comprises a pulse generator block30that further includes a pulse generator32and a driver34that is connected to receive the output of pulse generator32. Pulse generator module30, and more specifically, driver34is connected to deliver switch control signals to switches36and38. Switch36connects a DC voltage source40to Vout. An inductor42and a resistance44represent parasitic inductance and resistance of the generator10and are thus shown in dashed lines. Switch38is also connected to ground. Pulse generator32generates pulses at a frequency based upon the first error signal magnitude to drive switches36and38. Driver34sends control signals to open and close switches36and38based on the logical value of the pulses received from pulse generator32.

Essentially, the DC voltage produced by DC voltage source40is delivered to inductor42and resistor44based on the logical state of the pulses produced by pulse generator32. The characteristics of the pulses of pulse generator32(e.g., frequency, period, etc.) affect the timing of the operation of switches36and38and therefore affect the magnitude of the output voltage produced at Vout.

FIG. 5thus illustrates a fast acting feed-forward control system with a high-bandwidth response that includes a pulse generator module that produces switch control signals based on a first error signal, first and second switches connected selectively charge and discharge inductor42wherein the first switch is also connected to a DC voltage source and the second switch is also connected to create a connection to ground. The first and second switches are configured to open and close based on the switch control signals and an output node connected to an output capacitor and a load resistor.

A current estimator connected to the output node in a feedback path generates an estimator output signal that corresponds to an estimated current flowing through the output capacitor. A first differential transconductance amplifier that produces a second error signal based on a difference between a reference voltage and output voltage at the output node. A comparator that compares the estimated output signal to a second error signal to produce the first error signal.

FIG. 6is a functional schematic diagram of a current estimator that estimates a current through an output capacitor. Referring toFIG. 6, an output capacitor is modeled by a capacitor12(C), an inductive element19that represents parasitic inductance ESL of the output capacitor and a resistive element18that represents parasitic resistance ESR of the output capacitor. A current estimator includes a capacitive element40(Csns) having a parasitic inductive element42and a parasitic resistive element44that generate inductance (ESLsns) and resistance (ESRsns) as well as a resistor46(R2) and a capacitor48(C2). Adding an RC circuit with the same time constant as ESL/ESR can generates a voltage proportional to ESR voltage (which is proportional to capacitor current—exactly as done with inductor current sensing).FIG. 7illustrates a sense network having a buffered amplifier50to eliminate loading concerns and provide gain. As withFIG. 6,FIG. 7includes resistor46(R2) and a capacitor48(C2) to generate the same time constant as ESL/ESR of the output capacitor12(C).

FIG. 8is a partial schematic and partial block diagram that illustrates a current estimator according to one embodiment. An input node of a current estimator, labeled regulator Vout, is connected to receive the output of a regulator. The input node is connected to a capacitor60(C5) then to a first input node of a differential amplifier62(E11) and to a first input of current controlled current source66(F5). A second input of amplifier62is connected to ground. A first output of amplifier62is connected to a resistor46(R2) that is, at its other end, connected to a capacitor48(C2) that is also connected at its other end to ground. A second output of amplifier62is connected to ground.

The node that connects resistor46and capacitor46is further connected to a first input terminal of a voltage controlled current source64(G1). A second input terminal of voltage controlled current source64is connected to ground. A first “output” node of voltage controlled current source64is connected to a second “input” of current controlled current source66. A first input of current controlled current source66is connected to capacitor60then to the input node of current estimator22labeled “regulator Vout”. A first output of current controlled current source66is connected to ground while a second output of current controlled current source66is connected to resistor68(R5) and output node “estimator Vout”. The other end of resistor68is connected to ground.

The current estimator ofFIG. 8includes amplifier62, capacitor60(C5), resistor46(R2) and capacitor (C2) as did the circuit ofFIG. 5. Here, however, amplifiers66(F5) and64(G1) are included to emulate current of the output capacitor. Amplifier66is a current controlled current source and amplifier64is a voltage controlled current source.

In operation, the output of amplifier62is produced to the RC circuit comprising resistor46and capacitor48. The output of the RC circuit is produced as an input to voltage controlled current source amplifier64. Amplifier64conducts current, therefore, based on the received voltage across capacitor48of the RC circuit. The current conducted by amplifier64charges capacitor60and drives current controller current source amplifier66that, in turn, drives an output current into a resistor68. The resulting voltage across capacitor60corresponds to delta voltage across capacitive component of the output capacitor network while the voltage across resistor68is the output voltage signal that corresponds to the output current estimate through the output capacitor. This output voltage signal is produced as the estimator output voltage signal. In the described embodiment, the circuit may be tuned by tuning or adjusting gain elements of the amplifiers62,64and66, as well as the resistive and capacitive values of capacitors48and60and resistors46and68.

FIG. 9is a partial schematic and partial block diagram that illustrates a current estimator according to one embodiment. An input node of a current estimator, labeled regulator Vin, is connected to receive the output of a regulator. The input node is connected to a first input node of a differential amplifier62. A second input of amplifier62is connected to node V1. A first output of amplifier62is connected to a resistor46that is, at its other end, is connected to a capacitor70(C6) that is also connected at its other end to ground. A second output of amplifier62is connected to ground. A voltage V3appearing at the node that connects resistor46and capacitor70is the input voltage of voltage controlled current source amplifier64. A second input terminal of voltage controlled current source amplifier64is connected to ground. A first “output” node of amplifier64is connected to a first “input” of current controlled current source amplifier66F5. A second output of amplifier64is connected to ground. A second input of amplifier66is connected to node V1and to the second input of amplifier62. A first output of amplifier66is connected to ground while a second output of amplifier66is connected to resistor68(R5). The other end of resistor68is connected to ground.

The current estimator ofFIG. 9includes amplifier62and resistor46and capacitor70(similar toFIG. 7) as well resistors68and72and capacitors60and70, all of which are configured to be adjustable in one embodiment. Amplifiers64and66are included to emulate current information of the output capacitor.

In operation, the output of amplifier62is produced to the RC circuit comprising46and capacitor70. The output of the RC circuit is produced as an input to voltage controlled current source amplifier64. Amplifier64conducts current, therefore, based on the received voltage across capacitor70of the RC circuit. The current conducted by amplifier64drives current controller current source amplifier66that, in turn, drives an output current into a resistor68. The resulting voltage across resistor68then is the output voltage signal that corresponds to the output current estimate through the output capacitor. This output voltage signal is produced as the estimator output voltage signal. In the described embodiment, the circuit may be tuned by tuning or adjusting, via one or more of amplifiers62-66, and/or the resistive and capacitive values of resistors46,68and72and capacitive values60and66.

FIG. 10is a functional schematic diagram that illustrates a capacitor equivalent circuit of the current estimator. As may be seen, a capacitor80(C1) is connected in series with inductor82(Lcf1) and resistor84(Rcf1). The equations that correspond to the equivalent circuit ofFIG. 10for Zoutare as follows:
Zout=ESR+SESL+1/(SCout)  (1)

As may be seen from formula (1), the output impedance of the output capacitor varies according to the parasitic impedances ESL and ESR. Formula (2) illustrates an alternative expression for Zout. Cout_total inFIG. 8is the total output capacitance. ESL_cf_total is the equivalent series inductance and ESR_cf_total is the equivalent series resistance. Referring back toFIG. 7, therefore, the inverse of Zoutmay be expressed as follows:
1/Zout=Vout/Vin=SCout/(1+S2Cout*ESL+SCout*ESR)  (3)

G1is equal to 1/ESR_cf_total, R2=1/ESR_cf_total, C6=ESL_cf_total, C5=Cout_total, RL=1 and R1=0 for the above expression. Since capacitor current is bidirectional, both positive and negative voltages are required in a practical estimator. Accordingly, the amplifier outputs are biased at a level above ground. The estimator circuit with the described embodiment does not affect closed-loop poles or zeroes of the system when there is perfect matching of the estimator and power train capacitor filter parameters.

Referring again toFIG. 9, if the effects of resistor72(R1) are ignored, and if it is assumed that the voltage across capacitor60(C5) is equal to Cf1, the difference between capacitor60(C5) and Vin is equal to the voltage across LCf1and RCf1. The voltage at V2is equal to the voltage across LCf1and RCf1and the output of the RC network (resistor46and capacitor70) is proportional to current flowing through LCf1and RCf1and, therefore, to current flowing through Cf1if resistor46and capacitor70have the same time constant as LCf1/RCf1.

Scaling of C5to the output capacitor of the circuit (e.g., Cout=capacitor12) can be done in conjunction with scaling of amplifier64. This is independent of scaling of resistor46and capacitor70. The current estimator topology feeds a current proportional to the capacitor60voltage into capacitor60until the capacitor60voltage equals the Cf1voltage. Though the estimator does have a feedback loop, it does not require high gain. Low fixed gain buffers in a Thevenin loop decouple the impedance of capacitor60from the resistor46and capacitor70impedance. One advantage, therefore, is that the sense C and value of the RC impedance may be set independently due to the decoupling provided by the combination of buffers and feedback. The amplifiers do not need high gain or bandwidth.

FIG. 11is a flow chart illustrating a method according to one embodiment for generating an equivalent series inductance (ESL) of an output capacitor and an equivalent series resistance (ESR) of an output capacitor. The method commences with a circuit, e.g., a voltage regulator among others types of circuits, conducting a current through output capacitor (102). In the described embodiment, a feedback loop is utilized in which a current estimator estimates a current through an output capacitor to generate a feedback signal to the regulator circuit. Accordingly, the next step includes estimating a current magnitude in the output capacitor (104) and generating a corresponding voltage (106).

In one embodiment, the corresponding voltage is compared to a reference voltage (108) and generating an error signal (110) based on the comparison between the reference voltage and the corresponding voltage. Accordingly, the method includes adjusting an output voltage based upon the error signal (112). One aspect of the embodiment of the invention is that the current estimator generates an equivalent series resistance (ESR) of an output capacitor and an equivalent series inductance (ESL) of the output capacitor (114). Optionally, the method further includes adjusting at least one of a resistive value or a capacitive value within the capacitor current estimator to adjust a capacitor current estimator time constant to match that of the output capacitor (116).

FIG. 12is a flow chart illustrating a method according to one embodiment. The method commences with a circuit, and more particularly, a current estimator circuit generating an equivalent series resistance (ESR) of an output capacitor and an equivalent series resistor (ESR) of the output capacitor (120). The method further includes adjusting at least one of a resistive value or a capacitive value within the capacitor current estimator to adjust a capacitor current estimator time constant to match that of the output capacitor (122). Additionally, the method includes the current estimator circuit adjusting a current flow magnitude of a voltage controlled current source current output magnitude to generate an output voltage that is proportional to the output capacitor current (124). Finally, the method includes adjusting a current flow magnitude of a current controlled current source current output magnitude to generate an output voltage that is proportional to the output capacitor current (126).