Lateral electric field display panel and display apparatus having the same

A display panel includes a first substrate including a plurality of pixels, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first and second substrates. Each pixel includes a data line, a gate line insulated from the data line, a first signal line insulated from the data line, a second signal line insulated from the data line, a switching device connected to the data line and the gate line, a first pixel electrode connected to the switching device, and a second pixel electrode connected either the first signal line or the second signal line. The display panel displays an image according to an electric field generated between the first and second pixel electrodes.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2010-0096503 filed on Oct. 4, 2010, the contents of which are herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a display panel and more particularly, the present invention relates to a display panel using a lateral electric field method and a display apparatus having the display panel.

2. Discussion of the Related Art

In general, a liquid crystal display includes a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.

A liquid crystal display may utilize a vertical electrical field method for applying an electric field to the liquid crystal layer. According to this method, an electric field is applied through electrodes arranged in each of the first substrate and the second substrate. Alternatively, a liquid crystal display may utilize a lateral electric field method in which an electric field is applied through electrodes arranged on one of the first substrate or the second substrate.

When compared to the vertical electric field method, the lateral electric field method requires that a relatively high voltage be applied to the liquid crystal layer.

SUMMARY

Exemplary embodiments of the present invention provide a display panel using a lateral electric field method and having a high display quality.

Exemplary embodiments of the present invention also provide a display apparatus having the display panel.

According to the exemplary embodiments, a display panel includes a first substrate having a plurality of pixels, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first and second substrates.

Each of the plurality of pixels includes a data line, a gate line that is insulated from the data line over a region in which the gate line crosses the data line, a first signal line that is insulated from the data line over a region in which the first signal line crosses the data line and is spaced apart from the gate line, a second signal line that is insulated from the data line over a region in which the second signal line crosses the data line is and spaced apart from the gate line and the first signal line, a switching device connected to the data line and the gate line, a first pixel electrode connected to the switching device, and a second pixel electrode connected to either the first signal line or the second signal line.

The display panel displays an image according to an electric field generated between the first and second pixel electrodes formed on the liquid crystal layer.

According to exemplary embodiments, a display apparatus includes a driving circuit and a display panel.

The driving circuit receives an external signal and generates an image signal and a control signal. A display panel includes a plurality of pixels and receives the image signal and the control signal.

Each of the plurality of pixels includes a data line, a gate line that is insulated from the data line over a region in which the gate line crosses the data line, a first signal line that is insulated from the data line over a region in which the first signal line crosses the data line and is spaced apart from the gate line, a second signal line that is insulated from the data line over a region in which the second signal line crosses the data line and is spaced apart from the gate line and the first signal line, a switching device connected to the data line and the gate line, a first pixel electrode connected to the switching device, and a second pixel electrode connected to either the first signal line or the second signal line.

The display panel displays an image according to an electric field generated between the first and second pixel electrodes formed on the liquid crystal layer.

According to exemplary embodiments, a display panel includes a first substrate having a plurality of pixels, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first and second substrates.

Each of the plurality of pixel includes a data line, a gate line that is insulated from the data line over a region in which the gate line crosses the data line, a signal line that is insulated from the data line over a region in which the signal line crosses the data line and is spaced apart from the gate line, a switching device connected to the data line and the gate line, a first pixel electrode connected to the switching device, and a second pixel electrode connected to the signal line.

The display panel displays an image according to an electric field generated between the first and second pixel electrodes formed on the liquid crystal layer.

According to the above, a voltage is effectively applied to the first and second pixel electrodes, and thus, a display panel may have a high aperture ratio and may be manufactured with relatively low cost.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a block diagram showing a display apparatus according to an exemplary embodiment of the present invention.

Referring toFIG. 1, a display apparatus100includes a display panel110, a gate driver120, a data driver130, a signal driver140, and a timing controller150.

The timing controller150receives an image signal RGB and a control signal CS from the exterior of the display apparatus100. The timing controller150converts a data format of the image signal RGB into a data format appropriate to an interface between the data driver130and the timing controller150and provides converted image signals R′G′B′ to the data driver130. The timing controller150provides a data control signal DCS, for example, a vertical synchronization signal V_sync, an output start signal, a horizontal start signal, a polarity inversion signal, etc., to the data driver130.

The timing controller150provides a gate control signal GCS, for example, a vertical start signal, a vertical clock signal, a vertical clock bar signal, etc., to the gate driver120. The timing controller150provides a signal control signal SCS, for example, a vertical start signal, a vertical clock signal, etc., to the signal driver140.

The gate driver120sequentially outputs gate signals G1through Gn in response to the gate control signal GCS applied from the timing controller150.

The data driver130converts the image signals R′G′B into data voltages D1through Dm in response to the data control signal DCS applied from the timing controller150. The data driver130outputs the data voltages D1through Dm and applies them to the display panel110.

The signal driver140receives the signal control signal SCS from the timing controller150and sequentially outputs first line signals SA1through SAn, second line signals SB1through SBn, first switching signals CTSA1through CTSAn−1, and second switching signals CTSB1through CTSBn−1.

The display panel110includes a plurality of gate lines GL1through GLn, a plurality of data lines DL1through DLm crossing the gate lines GL1through GLn, and pixels PX. The gate lines GL1through GLn, the data lines DL1through DLm, and the pixels PX may be arranged on a first substrate101(FIG. 3).

Since each of the pixels PX have the same structure and function, one pixel has been shown inFIG. 1as a representative example, and detailed descriptions of the pixel will be described with reference toFIGS. 2 to 8.

Although not shown inFIG. 1, each pixel PX includes a thin film transistor and a liquid crystal capacitor. The thin film transistor includes a gate electrode connected to a corresponding gate line among the gate lines GL1through GLn, a source electrode connected to a corresponding data line among the data lines DL1through DLm, and a drain electrode connected to the liquid crystal capacitor.

The gate lines GL1through GLn are connected to the gate driver120and the data lines DL1˜DLm are connected to the data driver130. The gate lines GL1through GLn receive the gate signals G1through Gn provided from the gate driver120, and the data lines DL1through DLm receive the data voltages D1through Dm provided from the data driver130.

The thin film transistor of each pixel PX is turned on in response to a gate signal provided through the corresponding gate line, and a data voltage applied through the corresponding data line is input to the source electrode of the turned-on thin film transistor and is output from the drain electrode of the turned-on thin film transistor.

Although not shown in the figures, a backlight unit may be positioned adjacent to the display panel110to provide light to the display panel110.

FIG. 2is a plan view showing the display panel ofFIG. 1,FIG. 3is a cross-sectional view taken along a line I-I′ ofFIG. 2, andFIG. 4is a circuit diagram corresponding to the display panel ofFIG. 2.

For the convenience of explanation, two pixel areas have been described as an example inFIG. 2, and it is to be understood that these the two pixel areas are repeatedly arranged in column and row directions in the display panel110to provide the desired number of pixel areas.

Referring toFIG. 2, the display panel110includes a gate line GLi extended in a first direction D1, a first data line DLk, and a second data line DLk+1 that are spaced apart from each other and extended in a second direction D2. The first and second data lines DLk and DLk+1 each cross the gate line GLi. A first signal line SLAi is spaced apart from the gate line GLi and extends in the first direction D1. A second signal line SLBi is spaced apart from the gate line GLi and the first signal line SLAi and extends in the first direction D1.

The display panel110further includes a first thin film transistor TR1connected to the first data line DLk and the gate line GLi and a second thin film transistor TR2connected to the second data line DLk+1 and the gate line GLi.

The first thin film transistor TR1includes a gate electrode GE branched from the gate line GLi, a source electrode SE insulated from the gate electrode GE and branched from the first data line DLk, and a drain electrode DE spaced apart from the source electrode SE.

The second thin film transistor TR2includes a gate electrode GE branched from the gate line GLi, a source electrode SE insulated from the gate electrode GE and branched from the second data line DLk+1, and a drain electrode DE spaced apart from the source electrode SE.

The drain electrode DE of the first thin film transistor TR1is connected to a first pixel electrode PE1through a first contact hole CH1and the drain electrode DE of the second thin film transistor TR2is connected to a fourth pixel electrode PE4through a seventh contact hole CH7.

The first signal line SLAi is connected to a second pixel electrode PE2through a second contact hole CH2. The second signal line SLBi is connected to a fifth pixel electrode PE5through an eighth contact hole CH8. Thus, the second pixel electrode PE2and the fifth pixel electrode PE5of the pixels arranged in one row may be alternately connected to the first signal line SLAi or the second signal line SLBi. Also, the second pixel electrode PE2of the pixels arranged in one column may be alternately connected to the first signal line SLAi or the second signal line SLBi.

Although not shown inFIG. 2, the connection of the second pixel electrodes or the fifth pixel electrodes arranged in one row or one column may be changed according to various embodiments.

The display panel110may further include a first shielding electrode SE1, a second shielding electrode SE2, a third shielding electrode SE3, a fourth shielding electrode SE4, a fifth shielding electrode SE5, and a sixth shielding electrode SE6. The shielding electrodes SE1through SE5may prevent the signals of the first and second data line DLk and DLk+1 from exerting influence on the liquid crystal layer117.

The first shielding electrode SE1is connected to the first pixel electrode PE1through a third contact hole CH3, and the first shielding electrode SE1is connected to a third pixel electrode PE3through a fourth contact hole CH4. The second shielding electrode SE2is connected to the second pixel electrode PE2through a fifth contact hole CH5, and the third shielding electrode SE3is connected to the second pixel electrode PE2through a sixth contact hole CH6.

The first shielding electrode SE1receives the same signal as the first and third pixel electrodes PE1and PE3and an electric field is prevented from being applied to the liquid crystal layer117due to the signals applied to the first and second data lines DLk and DLk+1 and the gate line GLi. The second and third shielding electrodes SE2and SE3receive the same signal as the second pixel electrode PE2and an electric field is prevented from being applied to the liquid crystal layer117due to the signals applied to the first and second data lines DLk and DLk+1.

The fourth shielding electrode SE4is connected to the fourth pixel electrode PE4through a ninth contact hole CH9, and the fourth shielding electrode SE4is connected to a sixth pixel electrode PE6through a tenth contact hole CH10. The fifth shielding electrode SE5is connected to the fifth pixel electrode PE5through an eleventh contact hole CH11, and the sixth shielding electrode SE6is connected to the fifth pixel electrode PE5through a twelfth contact hole CH12.

The fourth shielding electrode SE4receives the same signal as the fourth and sixth pixel electrodes PE4and PE6and an electric field is prevented from being applied to the liquid crystal layer117due to the signals applied to the second data line DLk+1 and the gate line GLi. The fifth and sixth shielding electrodes SE5and SE6receives the same signal as the fifth pixel electrode PE5and an electric field is prevented from being applied to the liquid crystal layer117due to the signals applied to the second data line DLk+1 and the gate line GLi.

InFIG. 2, the first and third pixel electrodes PE1and PE3are connected to each other through the first shielding electrode SE1. The fourth and sixth pixel electrodes PE4and PE6are connected to each other through the fourth shielding electrode SE4. However, according to various embodiments, the pattern of the pixel electrodes may be changed from what is shown and described above. For example, the first pixel electrode PE1may be directly connected to the third pixel electrode PE3without using the first fielding electrode SE1, and, for example, the fourth pixel electrode PE4may be directly connected to the sixth pixel electrode PE6without using the fourth shielding electrode SE4. Similarly, the second, third, fifth, and sixth shielding electrodes SE2, SE3, SE5, and SE6may be omitted according to various embodiments.

Referring toFIG. 3, the display panel110includes a first substrate101, a second substrate102facing the first substrate101, and the liquid crystal layer117disposed between the first and second substrates101and102.

The first substrate101includes a first base substrate111. A gate electrode GE and a first shielding electrode SE1are arranged on the first base substrate111. Although not shown inFIG. 3, the second to sixth shielding electrodes SE2through SE6are arranged on the first base substrate111in the same manner as the first shielding electrode SE1.

A gate insulating layer112is disposed on the first base substrate111. The gate electrode GE, the first shielding electrode SE1, the source electrode SE, and the drain electrode DE are disposed on the gate insulating layer112. A semiconductor layer SL is disposed between the gate electrode GE and the source and drain electrodes SE and DE. An organic protective layer113is disposed on the first thin film transistor TR1.

The first and second pixel electrodes PE1and PE2are disposed on the organic protective layer113. A first alignment layer114is disposed on the organic protective layer113and the first and second pixel electrodes PE1and PE2. Liquid crystal molecules of the liquid crystal layer117may be aligned in accordance with the first alignment layer114.

The first pixel electrode PE1is connected to the drain electrode DE through the first contact hole CH1formed through the organic protective layer113. The second pixel electrode PE2is connected to the first signal line SLAi through the second contact hole CH2formed through the organic protective layer113and the gate insulating layer112.

A column spacer118is disposed between the first and second substrates101and102and maintains a uniform distance between the first and second substrates101and102.

The second substrate102includes a second base substrate115and a second alignment layer116arranged under the second base substrate115. Although not shown in the figures, the second substrate102may include a color filter, such as a red color filter, a green color filter, and/or a blue color filter.

Referring toFIG. 4, the drain electrode DE of the thin film transistor TR1is connected to the first and third pixel electrodes PE1and PE3. The drain electrode DE of the second thin film transistor TR2is connected to the fourth and sixth pixel electrodes PE4and PE6.

The second pixel electrode PE2is connected to the first signal line SLAi and forms a first liquid crystal capacitor CLC1using the first and third pixel electrodes PE1and PE3and the liquid crystal layer117as a dielectric substance. The fifth pixel electrode PE5is connected to the second signal line SLBi and forms a second liquid crystal capacitor CLC2using the fourth and sixth pixel electrodes PE4and PE6and the liquid crystal layer117as a dielectric substance. Thus, the display panel110varies an orientation phase of liquid crystal molecules in the liquid crystal layer117according to a voltage applied to the first and second liquid crystal capacitors CLC1and CLC2and displays a grayscale.

FIG. 5is a circuit diagram showing the display panel ofFIG. 1. Although not shown inFIG. 5, the display panel110includes pixel areas arranged in n rows and m columns. However, for the convenience of explanation, only the first signal lines SLA1through SLAn, the second signal lines SLB1through SLBn, the first switching devices CTA1thorough CTAn−1, the second switching devices CTB1through CTBn−1, first switching lines CTLA1through CTLAn−1, and second switching lines CTLB1through CTLBn−1 have been shown inFIG. 5.

The first signal lines SLA1through SLAn respectively receive the first line signals SA1through SAn, and the second signal lines SLB1through SLBn respectively receive the second line signals SB1though SBn.

First and second electrodes of each of the first switching devices CTA1through CTAn−1 are connected to between the two first signal lines adjacent to each other. First and second electrodes of each of the second switching devices CTB1through CTBn−1 are connected to between the two second signal lines adjacent to each other. Third electrodes of the first switching devices CTA1through CTAn−1 are respectively connected to the first switching lines CTLA1through CTLAn−1, and the first switching devices CTA1through CTAn−1 respectively receive the first switching signals CTSA1through CTSAn−1. In addition, third electrodes of the second switching devices CTB1through CTBn−1 are respectively connected to the second switching lines CTLB1through CTLBn−1, and the second switching devices CTB1through CTBn−1 respectively receive the second switching signals CTSB1thorough CTSBn−1.

The first switching devices CTA1through CTAn−1 connect two first signal lines adjacent to each other. The second switching devices CTB1through CTBn−1 connect two second signal lines adjacent to each other. However, according to various embodiments, the first switching device connecting two first signal lines respectively included in two pixel rows and the second switching device connecting two second signal lines respectively included in the two pixel rows may be connected to the same switching line to receive the same signal.

InFIG. 5, the first and second switching devices CTA1through CTAn−1 and CTB1through CTBn−1 are arranged in a non-display area outside the display area DA in which the pixels PX are arranged. However, an arrangement position of the first and second switching devices CTA1through CTAn−1 and CTB1through CTBn−1 may be changed according to various embodiments.

A voltage applied to the first and second signal lines SLA1through SLAn and SLB1through SLBn is influenced by voltages applied to the data lines DL1through DLm, the gate lines GL1through GLn, and the first to sixth pixel electrodes PE1through PE6. However, the stability of the voltage applied to the first and second signal lines SLA1through SLAn and SLB1through SLBn may be increased by connecting the first signal lines SLA1through SLAn to each other and connecting the second signal lines SLB1through SLBn to each other.

More detailed descriptions of the signals applied to the first signal lines SLA1through SLAn, the second signal lines SLB1through SLBn, the first switching lines CTLA1through CTLAn−1, and the second switching lines CTLB1through CTLBn−1 are described below with reference toFIG. 8.

FIG. 6is a block diagram showing the signal driver ofFIG. 1. Since the signal driver may have the same circuit configuration in every row, for the convenience of explanation, a circuit configuration of the signal driver according to an i-th pixel row will be described inFIG. 6.

The signal driver140includes a first voltage selection circuit141and a second voltage selection circuit142. Each of the first and second voltage selection circuits141and142receives a first voltage Vmax corresponding to a maximum grayscale value of positive polarity with respect to a predetermined reference voltage and a second voltage Vmin corresponding to a maximum grayscale value of negative polarity with respect to the predetermined reference voltage. The first and second voltages Vmax and Vmin have different polarities from each other with respect to the predetermined reference voltage and have the same voltage level.

As an example, the first voltage Vmax may have a voltage level of about 15V, the second voltage Vmin may have a voltage level of about 0V, and the predetermined reference voltage may have a voltage level of about 7.5V.

The first voltage selection circuit141receives a first selection signal SSAi to select either the first voltage Vmax or the second voltage Vmin according to the first selection signal SSAi and outputs the selected signal to an i-th first signal line SLAi corresponding to an i-th pixel row as a first line signal SAi. The second voltage selection circuit142receives a second selection signal SSBi to select either the first voltage Vmax or the second voltage Vmin according to the second selection signal SSBi and outputs the selected signal to an i-th second signal line SLBi corresponding to the i-th pixel row as a second line signal SBi.

A first stage146receives a first stage signal SRAi and outputs the first selection signal SSAi to the first voltage selection circuit141. A second stage147receives a second stage signal SRBi and outputs the second selection signal SSBi to the second voltage selection circuit142. Although not shown inFIG. 6, the first and second stage signals146and147may be directly applied from the timing controller150, may be applied from a shift register included in the gate driver120, or may be applied from a shift register in the signal driver40.

FIG. 7is a circuit diagram showing the first voltage selection circuit ofFIG. 6.

The first voltage selection circuit141includes a first selection transistor STR1, a second selection transistor STR2, a third selection transistor STR3, and a capacitor CA.

When a gate-on voltage is applied as the first stage signal SSAi to turn on the third selection transistor STR3, the second voltage Vmin is output to the first signal line SLAi as the first line signal SAi. Meanwhile, when a gate-off voltage is applied as the first stage signal SSAi to turn off the third selection transistor STR3, the first and second selection transistors STR1and STR2are turned on in response to the first voltage Vmax, and the first voltage Vmax is output to the first signal line SLAi as the first line signal SAi.

FIG. 8is a timing diagram showing the signals ofFIG. 5.

Referring toFIG. 8, when a high period of a vertical synchronization signal V_sync indicating a start of one frame is input, a gate-on voltage is sequentially input to the gate lines GL1through GLn. For the convenience of explanation, in an order from a top of the display panel110, first, second, (i−1)-th, i-th, (i+1)-th, and n-th gate lines GL1, GL2, Gli−1, GLi, GLi+1, and GLn will be described with reference toFIG. 8.

Either the first voltage Vmax or the second voltage Vmin is repeatedly applied to the first signal lines SLA1through SLAn at each frame. The i-th first signal line SLAi arranged corresponding to the i-th gate line GLi receives either the first voltage Vmax or the second voltage Vmin before the gate-on voltage is input to the i-th gate line GLi. The input voltage is maintained at a constant voltage level until a next gate-on voltage is input to the i-th gate line GLi.

In addition, the second signal lines SLB1through SLBn repeatedly receive either the first voltage Vmax or the second voltage Vmin at each frame, and the voltage applied to the second signal lines SLB1through SLBn is different from the voltage applied to the first signal lines SLA1through SLAn.

As an example, when the first voltage Vmax is input to the first signal lines SLA1through SLAn, the second voltage Vmin is input to the second signal lines SLB1through SLBn respectively corresponding to the first signal lines SLA1through SLAn. Then, when the second voltage Vmin is input to the first signal lines SLA1through SLAn after the lapse of one frame period, the first voltage Vmax is input to the second signal lines SLB1through SLBn corresponding to the first signal lines SLA1through SLAn, respectively.

An i-th second signal line SLBi arranged corresponding to the i-th gate line GLi receives either the first voltage Vmax or the second voltage Vmin before the gate-on voltage is input to the i-th gate line GLi. The input voltage is maintained at a constant voltage level until a next gate-on voltage is applied to the i-th gate line GLi.

Each of the first switching lines CTLA1through CTLAn−1 and the second switching lines CTLB1through CTLBn−1 receives the gate-on voltage turning on the first and second switching devices CTA through CTAn−1 and CTB1through CTBn−1 and connects two first signal lines adjacent to each other and two second signal lines adjacent to each other. However, since the signals applied to the first signal lines SLA1through SLAn are sequentially inverted from the top of the display panel110, the gate-off voltage that turns off the first switching device is input to the first switching device that connects the adjacent two first signal lines when the signals having different polarities are applied to the two first signal lines adjacent to each other.

Meanwhile, similar to the first signal lines SLA1through SLAn, since the signals applied to the second signal lines SLB1through SLBn are sequentially inverted from the top of the display panel110, the gate-off voltage that turns off the second switching device is input to the second switching device that connects the adjacent two second signal lines when the two second signal lines adjacent to each other receive the signals having different polarities.

Referring toFIG. 8, since the i-th first switching device CTAi connects the i-th first signal line SLAi and the (i+1)-th first signal line SLAi+1, the gate-off voltage that turns off the i-th first switching device CTAi may be input to the i-th first switching line CTLAi from the time the gate-on voltage is applied to the (i−1)-th gate line GLi-1 to the time the gate-on voltage is applied to an (i+1)-th gate line GLi+1.

Since the i-th second switching device CTBi connects the i-th second signal line SLBi and the (i+1)-th second signal line SLBi+1, the gate-off voltage that turns off the i-th second switching device CTBi may be input to the i-th second switching line CTLBi from the time the gate-on voltage is applied to the (i−1)-th gate line GLi-1 to the time the gate-on voltage is applied to the (i+1)-th gate line GLi+1.

However, a period during which the gate-off voltage is applied to the i-th first and second switching lines CTLAi and CTLBi may be different according to various embodiments.

FIG. 9is a plan view showing the display panel ofFIG. 1according to an exemplary embodiment of the present invention andFIG. 10is a circuit diagram corresponding to the display panel ofFIG. 9. InFIGS. 9 and 10, the same reference numerals denote the same elements as inFIGS. 2 and 4, and thus the detailed descriptions of the same elements will be omitted. In addition, for the convenience of explanation, two pixel areas will be described inFIG. 9. The two pixel areas are repeatedly arranged in column and row directions in the display panel to achieve the desired number of pixel areas.

Referring toFIGS. 9 and 10, the display panel110includes the gate line GLi, the first and second data lines DLk and DLk+1, and the first signal line SLAi. Here, the display panel110does not include the second signal line SLBi unlike the display panel110described above with reference toFIGS. 2 and 4.

The first signal line SLAi is connected to the second pixel electrode PE2through the second contact hole CH2and the first signal line SLAi is connected to the fifth pixel electrode PE5through the eighth contact hole CH8.

The first signal lines SLA1through SLAn are extended in the second direction D2and may alternatively receive the first voltage Vmax or the second voltage Vmin.

The signals applied to the signal lines shown inFIGS. 9 and 10may be understood with reference to the timing diagram ofFIG. 8.