Array substrate, manufacturing method thereof and display device

The present disclosure provides an array substrate, manufacturing method thereof and a display device. A method of manufacturing an array substrate includes: sequentially forming a common electrode line, a first insulating layer, a pixel electrode, and a second insulating layer, and forming a via that is in communication with the common electrode line. The method further comprises, after forming the via, forming a common electrode that covers the via through a patterning process, wherein the patterning process includes etching a portion of the via covered with the common electrode to form an isolated region. The isolated region includes a region at an inner side of a first edge of the via. The first edge is an edge of the via adjacent to or stacked with the pixel electrode. The via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Chinese Patent Application No. 201710042420.X, filed on Jan. 20, 2017, which is incorporated herein by reference in its entirety and used for all purposes.

TECHNICAL FIELD

The present disclosure relates generally to the technical field of an array substrate, and in particular to an array substrate manufacturing method thereof and a display device.

BACKGROUND

For liquid crystal display devices in a HADS mode, pixel electrodes and common electrodes are both provided in an array substrate. However, the conventional array substrates are liable to result in display abnormalities due to an offset of a pixel electrode.

SUMMARY

Some embodiments of the present disclosure are directed to a method of manufacturing an array substrate, comprising: sequentially forming a common electrode line, a first insulating layer, a pixel electrode, and a second insulating layer, forming a via in communication with the common electrode line; and after forming the via, forming a common electrode that covers the via by a patterning process. The patterning process includes etching a portion of the via covered with the common electrode to form an isolated region. The isolated region includes a region at an inner side of a first edge of the via. The first edge being an edge of the via adjacent to or stacked with the pixel electrode. The via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode.

In some embodiments, the pixel electrode is provided at a portion of the via.

In some embodiments, the isolated region is a strip-shaped region distributed along the inner side of the first edge of the via.

In some embodiments, the common electrode line includes a strip-shaped body and a projection provided on one side of the body, and the via is in communication with the projection.

In further embodiments, the via covers the projection.

In further embodiments, an edge of the projection away from one side of the body is adjacent to or stacked with the pixel electrode; and the first edge of the via corresponds to the edge of the projection away from the one side of the body.

Another embodiment of the present disclosure is directed to an array substrate, comprising a base, and a common electrode line, a first insulating layer, a pixel electrode, a second insulating layer, and a common electrode provided sequentially in a direction away from the base. The array substrate further comprises a via in communication with the common electrode line and covered with the common electrode. A first edge of the via is adjacent to or stacked with the pixel electrode, and the via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode. The common electrode is provided with an opening in an isolated region, and the isolated region includes a region at an inner side of the first edge of the via.

In some embodiments, a portion of the pixel electrode is located within the via, the pixel electrode is provided with a trench at a position corresponding to the isolated region, and the portion of the pixel electrode within the via is separated from a portion of the pixel electrode outside the via by the trench.

In some embodiments, the isolated region is a strip-shaped region distributed along the inner side of the first edge of the via.

In some embodiments, the common electrode line includes a strip-shaped body and a projection provided on one side of the body, the via being in communication with the projection.

A further embodiment of the present disclosure is directed to a display device, which comprises any of the array substrates described above.

DETAILED DESCRIPTION

In order to provide those skilled in the art a better understanding of the technical solutions of the present disclosure, a detailed description of some embodiments of the present disclosure is further provided below with reference to the accompanying drawings and detailed implementations.

For liquid crystal display devices in a HADS mode, a pixel electrode2and a common electrode12are both provided in an array substrate. As shown inFIG. 1andFIG. 2, a common electrode line11and a gate line3are provided in the same layer, and located on a base9of the array substrate, which is covered with a gate insulating layer91(a first insulating layer); a plate-like pixel electrode2is provided over the gate insulating layer91, covered with a passivation layer92(a second insulating layer); a slit common electrode12is provided over the passivation layer92, and needs to be connected to the common electrode line11via a via5through the gate insulating layer91and the passivation layer92to obtain signals. To prevent the common electrode12from conducting with the pixel electrode2, the via5is provided between adjacent pixel electrodes2.

With the improvement of resolution, a distance between the adjacent pixel electrodes2is getting smaller, and a distance between the via5and the pixel electrode2adjacent thereto is also getting smaller (e.g., only 3 μm). However, in the practical manufacturing process, the location of the pixel electrode2may have some deviations, and as shown inFIG. 3andFIG. 4, if the pixel electrode2is offset and partially overlaps the via5, the pixel electrode2will be caused to be exposed at the via5, and the gate insulating layer91beneath the pixel electrode2cannot be removed; moreover, when the common electrode12is subsequently formed, the common electrode12will come into contact and conduct with the pixel electrode2within the via5. As a consequence, the pixel electrode2connects to a common voltage, and the display of the corresponding pixel is abnormal.

At least one embodiment of the present disclosure at least partially solves a problem that the conventional array substrates are liable to result in display abnormalities due to an offset of a pixel electrode, and provides an array substrate, manufacturing method thereof, and a display device that are capable of avoiding display abnormalities.

In a method of manufacturing an array substrate according to at least one embodiment of the present disclosure, when the common electrode is formed, etching is to be performed at the inner side of the first edge of the via adjacent to the pixel electrode so as to form an opening. When the via overlaps the pixel electrode, there will be the pixel electrode at the inner side of the first edge of the via. Since the pixel electrode is made of the same material as the common electrode, the pixel electrode at the opening will also be removed at the time of etching the common electrode, so that a portion of the pixel electrode connected to the common electrode is cut off from other portions of the pixel electrode, thereby preventing the pixel electrode that actually performs a display function from conducting with the common electrode, and eliminating display abnormalities. In the present disclosure, that two structures are “provided in the same layer” means that both of them are formed by subjecting the same material layer to a patterning process, so they are located in the same layer in terms of a lamination relationship, which however does not necessarily mean that both of them must have an equal distance from the base.

In the present disclosure, a “photolithography process”, which is a specific form of a patterning process, is a process of forming a specific pattern structure using a complete material layer, which specifically includes one or more forming a material layer, applying a photoresist, exposing, developing, etching, stripping the photoresist, and so on.

As shown inFIG. 5toFIG. 10, some embodiments of the present disclosure provide a method of manufacturing an array substrate, comprising: sequentially forming a common electrode line11, a first insulating layer (a gate insulating layer91), a pixel electrode2, and a second insulating layer (a passivation layer92), forming a via5which is in communication with the common electrode line11; and after forming the via5, forming a common electrode12that covers the via5by a patterning process, the patterning process including etching a portion of the via5covered with the common electrode12to form an isolated region4. The isolated region4includes a region at an inner side of a first edge of the via5, the first edge being an edge of the via5adjacent to or stacked with the pixel electrode2, and the via5further includes a second edge that is neither adjacent to nor stacked with the pixel electrode2.

Herein, one side of the via5is adjacent to the pixel electrode2, so an edge at this side of the via5(the first edge) may be adjacent to the pixel electrode2. When the pixel electrode2is offset, or when the pixel electrode2is deliberately designed to partially overlap the via5, the first edge will overlap the pixel electrode2, and therefore there will be the pixel electrode2in a portion of the region at the inner side of the first edge of the via5. Meanwhile, between the other side of the via5and the pixel electrode2is provided a gate line3and the like, so an edge at this side of the via5(the second edge) will not be adjacent to a pixel electrode2. Moreover, even if the pixel electrode2is offset, the second edge will not overlap the pixel electrode2(because the pixel electrode2will not be offset too much). That is, there will not be the pixel electrode2in a portion of the region at an inner side of the second edge of the via5.

In a method of manufacturing the array substrate according to some embodiments of the present disclosure, when the common electrode12is formed (for example, a slit in the common electrode12is etched), it is required to also perform etching at the inner side (the isolated region4) of the first edge of the via5adjacent to the pixel electrode2to form an opening121. When there is an overlap of the via5with the pixel electrode2, there will be the pixel electrode2at the inner side (the isolated region4) of the first edge of the via5. Since the pixel electrode2is made of the same material as the common electrode12, when the common electrode12is etched to form the opening121, the pixel electrode2at the opening121(the isolated region4) will also be removed, so that a portion of the pixel electrode2connected to the common electrode12is cut off from other portions of the pixel electrode2. Therefore, the pixel electrode2that actually performs a display function will not connect to the common electrode12, which can avoid display abnormalities. Meanwhile, since the via5further has the second edge that is not adjacent to the pixel electrode2, there will be no pixel electrode2at the inner side of the second edge thereof. Therefore, the common electrode12can still connect to the common electrode line11at the inner side of the second edge, thereby ensuring normal transmission of common electrode signals.

The method of manufacturing an array substrate according to some embodiments of the present disclosure will be described in detail in the following.

A pattern that includes a common electrode line11on a base9is formed through a photolithography process.

That is, the common electrode line11is formed from materials such as metal or the like, on the base9of glass or the like.

In some embodiments, a gate electrode (not shown) and a gate line3can also be formed at the same time of forming the common electrode line11, that is, the common electrode line11can be provided in the same layer as the gate line3.

In some embodiments, the common electrode line11includes a strip-shaped body and a projection provided on one side of the body, and a via5formed subsequently is in communication with the projection.

As shown inFIG. 5, generally, in order to enlarge a connection area of the via5and the common electrode line11, a projection (e.g. a trapezoid projection) can be provided in the common electrode line11, and the via5can connect to that projection.

In some embodiments, prior to forming the common electrode line11, the method may further comprise forming a buffer layer (not shown) or the like, which is not detailed herein.

A first insulating layer (i.e., a gate insulating layer91, which is taken as an example hereinafter) is formed on the base9upon which the foregoing steps are completed.

That is, the gate insulating layer91, which covers the common electrode line11, the gate line3, and the gate electrode, is formed from materials such as silicon oxide and silicon nitride, etc.

A pattern that includes an active region is formed on the base9upon which the foregoing steps are completed through a photolithography process.

That is, an active region of a thin-film transistor (not shown) is formed from semiconductor material.

A pattern that includes a data line, a source electrode, and a drain electrode is formed on the base9upon which the foregoing steps are completed through the photolithography process.

That is, the data line, the source electrode, and the drain electrode (not shown) are formed from a metal or the like, thereby constituting a thin-film transistor, wherein the data line is connected to the source electrode, and the source and drain electrodes are both connected to the active region.

A pattern that includes the pixel electrode2is formed on the base9upon which the foregoing steps are completed through a photolithography process.

That is, the pixel electrode2is formed from a transparent conductive material such as indium tin oxide (ITO). The pixel electrode2is block-like, and a pixel electrode2of each pixel is connected to a drain electrode of a thin-film transistor of the corresponding pixel, and pixel electrodes2of different pixels are provided at an interval.

A second insulating layer (i.e., a passivation layer92, which is taken as an example hereinafter) is formed on the base9upon which the foregoing steps are completed through a photolithography process.

That is, the passivation layer92, which covers the pixel electrode2, the data line, the source electrode, the drain electrode, and the active region, is formed from material such as silicon oxide and silicon nitride, etc.

The via5that is in communication with the common electrode line11is formed on the base9upon which the foregoing steps are completed, wherein the via5has a first edge that is adjacent to or stacked with the pixel electrode2, and a second edge that is neither adjacent to nor stacked with the pixel electrode2.

That is, the gate insulating layer91and the passivation layer92above a particular position (e.g., the projection) of the common electrode line11are etched, thereby forming the via5that goes through the gate insulating layer91and the passivation layer92and is in communication with the common electrode line11, for realizing connection of a common electrode12to the common electrode line11.

In some embodiments, the pixel electrode2is provided at a portion of the via5.

In other words, as shown inFIG. 7andFIG. 8, when the pixel electrode2is offset, the via5will come into connection with the pixel electrode2. That is, there will be a pixel electrode2at a portion of the via5. Of course, since only the first edge of the via5is adjacent to the pixel electrode2while the second edge is not adjacent to the pixel electrode2, even if the pixel electrode2is offset, it will be offset at most to the inner side of the first edge and will not fill the whole via5.

Alternatively, the pixel electrode2may be designed to extend to the inner side of the first edge of the via5, that is, an edge portion of the pixel electrode2is made deliberately to enter the via5(the effect produced thereby is the same as the effect from an offset). Of course, in this case, it should be ensured that the pixel electrode2does not fill the whole via5.

In some embodiments, the via5is connected to a projection of the common electrode line11. In other embodiments, the via5covers the projection. In further embodiments, an edge of the projection away from one side of the body is adjacent to or stacked with the pixel electrode2; the first edge of the via5corresponds to the edge of the projection away from the one side of the body.

In other words, as shown inFIG. 5andFIG. 7, in some embodiments, the via5is connected to the projection described above. Moreover, due to a method according to some embodiments of the present disclosure, even if the pixel electrode2is offset, display abnormalities can be avoided. Therefore, the via5can be larger to completely cover the projection. In other embodiments, the one side of the projection away from the body of the common electrode line11overlap the first edge of the via5, that is, the via5has the same shape as the projection.

A common electrode12is formed through a patterning process (which may specifically be a photolithography process) on the base9upon which the foregoing steps are completed. The patterning process includes etching a portion of the via5covered with the common electrode12to form the isolated region4; wherein the isolated region4includes a region at the inner side of the first edge of the via5.

That is, a transparent conductive material (such as indium tin oxide, etc.) layer is formed first; then the steps of applying a photoresist and performing exposure and development are carried out, such that the photoresist at a slit of the common electrode12is removed so as to expose the transparent conductive material layer at the corresponding position; after that, etching is performed to remove the exposed transparent conductive material layer, thereby forming the common electrode12having the slit; finally, the photoresist is stripped.

Different from conventional steps of forming the common electrode12, in the steps of performing exposure and development described above, the photoresist corresponding to the position of the isolated region4is also removed. As such, as shown inFIG. 5andFIG. 6, in the process of etching, the transparent conductive material layer in the isolated region4will also be etched, thereby removing the common electrode12at this position to form an opening121. As shown inFIG. 7andFIG. 8, if the pixel electrode2is offset or is deliberately designed to partially overlap the via5, the region at the inner side of the first edge of the via5will be provided with the pixel electrode2, and the pixel electrode2at this position is connected the common electrode12upward. Thus, at the time of forming the opening121in the common electrode12, the pixel electrode2therebeneath is also removed, thereby forming a “trench21” distributed in the pixel electrode2along the first edge.

As shown inFIG. 8andFIG. 9, the common electrode12covers the via. Hence, although the opening121is formed therein, a portion of the common electrode12that is connected to the common electrode line11(i.e., the portion of the common electrode12that is located at the inner side of the second edge of the via5) is still integrally connected to other portions of the common electrode12, such that signals of the common electrode line11can still be transferred to the entire common electrode12.

Still, as shown inFIG. 8andFIG. 10, the pixel electrode2only overlaps the first edge without extending to the second edge. Hence, the “trench21” described above can “split” the pixel electrode2into two non-interconnected separate portions, wherein one portion is located within the via5and connected to the common electrode12, while the other is located outside the via5and not connected to the common electrode12. Since the pixel electrode2that is actually used for generating a drive voltage is the portion outside the via, the trench21described above can prevent signals of the common electrode12from being transferred to the pixel electrode2that actually performs a display function, such that display abnormalities can be avoided.

In other embodiments, the isolated region4is a strip-shaped region distributed along the inner side of the via5.

That is, in the other embodiments, the isolated region4is an elongated region provided at the inner side of the first edge of the via5, thereby forming the opening121and the trench21described above. Such an isolated region4has a smaller area, which can make a contact area of the common electrode12within the via5and the common electrode line11as large as possible, thereby improving the electrical connection condition.

Of course, the isolated region4described above may also be in other forms, as long as it includes the region at the inner side of the first edge of the via5. For example, the isolated region4may be one half region within the via5that is adjacent to the first edge. In this case, the pixel electrode2in this region may not be isolated by the trench, but will be completely removed. Meanwhile, the common electrode12may be connected to the common electrode line11through the other half region within the via5. As such, display abnormalities may also be avoided.

Herein, if an offset of the pixel electrode2occurs, or if the pixel electrode2is deliberately designed to partially overlap the via5, the gate insulating layer91beneath a position within the via5where the pixel electrode2is located may not be removed, and this position has a relatively large height. As such, a segment difference between the common electrode12and the pixel electrode2at this position (when connected) is smaller, which can decrease resistance and avoid the breakage of the common electrode12or the like.

Some embodiments of the present disclosure further provide an array substrate manufactured with the aforementioned method, which comprises a base9, and a common electrode line11, a first insulating layer (a gate insulating layer91), a pixel electrode2, a second insulating layer (a passivation layer92), and a common electrode12that are provided sequentially in a direction away from the base9, wherein the array substrate further comprises a via5in communication with the common electrode line11and covered by the common electrode12.

A first edge of the via5is adjacent to or stacked with the pixel electrode2, and the via5further includes a second edge that is neither adjacent to nor stacked with the pixel electrode2.

The common electrode12is provided with an opening121in an insolated region4, and the isolated region4includes a region at the inner side of the first edge of the via5.

The array substrate according to some embodiments of the present disclosure is manufactured with the aforementioned method, in which the common electrode12is provided with the opening121in the isolated region4. Thus, even if the pixel electrode2is offset, the common electrode12in the array substrate product will not conduct with the pixel electrode2that actually performs a display function.

In some embodiments, a portion of the pixel electrode2is located within the via5, and the pixel electrode2is provided with a trench21at a position corresponding to the isolated region4, and the portion of the pixel electrode2within the via5is separated from a portion of the pixel electrode2outside the via5by the trench21.

That is, if an offset of the pixel electrode2occurs, or if the pixel electrode2is deliberately designed to partially overlap the via5, the pixel electrode2may be formed with the trench21in the isolated region4. The trench21separates the pixel electrode2within the via5from the pixel electrode outside the via5, thereby preventing the common electrode12from conducting with the pixel electrode2that actually performs a display function.

In some embodiments, the isolated region4is a strip-shaped region distributed along the inner side of the first edge.

In some embodiments, the common electrode line11includes a strip-shaped body and a projection provided on one side of the body, and the via5is in communication with the projection.

As is noted above, in some embodiments, the isolated region4in the array substrate is a strip-shaped region, and the common electrode line11can also be provided with the projection described above for connecting to the via5.

Some embodiments of the present disclosure provide a display device, comprising an array substrate according to any of the embodiments of the present disclosure, wherein the display device may be any product or means having a display function such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or the like.

It will be appreciated that, the embodiments described above are exemplary embodiments adopted merely for illustrating the principles of the present disclosure, but the present disclosure is not limited thereto. For those skilled in the art, various variations and modifications can be made without departing from the spirit and essence of the present disclosure, and these variations and modifications are also considered to be within the scope of protection of the present disclosure.