Symbol processing system

A symbol processing system incorporated in an NMOS/LSI chip separates valid data from invalid data all generated by scanning a bar-coded symbol. The signals representing the bars and spaces of the symbol are decoded by a pattern recognition array, and the decoded data is clocked into a storage unit. When valid data is discovered, such data is captured within the storage unit. The valid data is then clocked out of the storage unit to a utilization device for further processing.

CROSS REFERENCE TO RELATED APPLICATIONS 
The present invention is related to the following U.S. Pat. Applications, 
all of which have been filed on even date herewith, and assigned to NCR 
Corporation: 
SYMBOL DECODING SYSTEM, co-pending application Ser. No. 043,933, filed May 
30 1979, by Amacher et al., now U.S. Pat. No. 4,253,018; 
SLOT SCANNING SYSTEM, co-pending application Ser. No. 043,928, by Naseem et 
al.; 
TOPOGRAPHY FOR I.C. PATTERN RECOGNITION ARRAY, co-pending application Ser. 
No. 043,929, by James et al.; 
TOPOGRAPHY FOR I.C. FRAME CONTROL CHIP, co-pending application Ser. No. 
043,930, by Gardner et al. 
BACKGROUND OF THE INVENTION 
The present invention relates to a novel method and means for decoding a 
high density multiple bar code from a record medium at a high rate of 
speed and more particularly, relates to an NMOS/LSI chip which receives 
both valid and invalid data from a pattern recognition chip and extracts 
only the data which is valid. This valid data is then transmitted to a 
microprocessor for assembling into a readable form. 
The use of bar coded symbols or labels intended to be read by optical 
scanning equipment as a means for identifying new data useful in 
processing items sold in the retail industry has been widely accepted to 
the point that a particular bar code known as the Universal Product Code 
(UPC) has been established as the industry standard for the grocery and 
other related retail industries. In the multiple bar code, such as the 
UPC, each decimal number or character is represented by two pairs of 
vertical bars and spaces within a 7-bit pattern wherein a binary 1 bit 
represents a dark module or bar of a predetermined width and a binary 0 
represents a light module or space. Thus, the decimal or character 1 may 
be represented in the UPC code by the 7-bit pattern 0011001. In keeping 
with the format, the decimal 1 would be comprised of an initial space of a 
2-bit width, followed by a 2-bit wide bar, another 2-bit space and a 1-bit 
wide bar. For each character or decimal of the system there are two bars 
and two spaced which have a total width of seven modules or bits. The 
width of each of the bars or spaces which comprise a character may be 1, 
2, 3 or 4 modules wide as long as the sum of the bars and spaces is seven 
bits or modules wide. 
A multiple bar code, such as the UPC, is normally read by an optical 
scanner whih may take the form of a hand-held wand or a scanner mechanism 
located in a check-out counter. The optical scanner will scan the bar code 
pattern and generate signals representing the bafs and space for 
transmission to the processing apparatus which determines the character 
represented by the bar code pattern. 
Prior optical readers generally store the electrical signals generated as a 
result of scanning the bar code pattern until the accumulated signals 
stored are sufficient to allow the processing apparatus to initiate a 
recognition operation to determine the character represented by the 
scanned bar code pattern. Because of the speed in which the scanning 
operation is performed, the cost of the prior optical readers in 
processing the electrical signals has been unduly expensive, which in many 
instances has prevented the readers from reaching the marketplace. It is 
therefore the principal object of this invention to provide a low-cost 
optical character reader. It is another object of this invention to 
provide a low-cost optical character reader system which operates at a 
relatively high rate of speed without a loss of recognition efficiency. It 
is a further object of this invention to provide a system for filtering 
out invalid data embodied in an NMOS/LSI chip. 
SUMMARY OF THE INVENTION 
In order to carry out these objects, there is provided a high speed optical 
character reader system which includes a slot scanner mechanism for 
scanning the bar pattern of a symbol or coded tag which bar pattern 
includes a plurality of bars and spaces. The data obtained by scanning the 
tag is decoded by a pattern recognition array incorporated in an NMOS/LSI 
chip, and then transmitted to a second NMOS/LSI chip which includes a 
plurality of buffers, flip-flops, shift registers, and discrete logic 
elements. This chip receives the data, much of which is invalid, and 
separates it into four groups. When the data stored in one of the groups 
is determined to be valid, it is sent to a microprocessor chip. From this 
valid data, the microprocessor can determine: in which direction the tag 
was scanned; the type of tag being scanned; wheter the segment read is a 
left half or right half of a tag; and if a valid read operation has 
occurred. Other features and advantages of the present invention will be 
apparent from the preferred embodiment hereinafter set forth and 
illustrated in the accompanying drawings.

DESCRIPTION OF THE PRESENT EMBODIMENT 
Referring now to FIG. 1, there is shown a graphical representation of a UPC 
symbol or coded label. The UPC symbol is made up of a series of light and 
dark parallel bars which comprise twelve characters. Among the twelve 
characters, two characters are the industry code and a modulo check 
character, the remaining ten characters are the main code representing 
data associated with a merchandise item. As shown in FIG. 1, included is a 
readable number printed in OCR-B font. In addition to the series of light 
and dark parallel bars, the UPC symbol includes spaces on both sides which 
are referred to as the left and right margins. Other characteristics of 
the UPC symbol include the following: 
(1) The overall shape of the symbol is rectangular; 
(2) Each character of a UPC code is represented by two dark bars and two 
light spaces; 
(3) Each character is comprised of seven equal data elements called 
modules; 
(4) Each module can be light or dark; 
(5) Each bar may be composed of 1, 2, 3, or 4 dark modules. Light spaces 
may also be composed of 1, 2, 3, or 4 modules; 
(6) Each character is independent; 
(7) The right-most character of the symbol is a modulo check character 
while the left-most digit of the symbol indicates a system in which this 
symbol is encoded; 
(8) The size of the UPC symbol is variable, that is, it may be large or 
small without affecting its readability. The UPC symbol may consist of 
only six characters having the same arrangement as shown in FIG. 1; 
(9) The series of light and dark parallel bars are separated from the 
margins on each side by left and right guard bar patterns and includes a 
center band pattern located at the center of the UPC symbol. 
Referring now to FIG. 2 there is shown a graphical representation of the 
character structure of the UPC symbol. As shown, each encoded UPC 
character is made up of two dark bars and two light spaces each composed 
of a differing number of modules. By assigning a 1 which corresponds to 
the black module and a 0 to a white module, the lefthand character 
represents (0101111) which denotes the character 6 and the right hand 
character represents (0001101) which denotes the character 0. The 
structure of the character code is not uniquely determined by each 
character, but is different according to which side of the center band 
pattern the character is located on. It is thus arranged that the light 
modules and the black modules are reversed as the character is located on 
the right or left sides, and as a result an odd number of black modules is 
included in each character code on the left hand side and an even number 
of black modules is included in each character code on the right hand side 
as indicated in FIG. 3. This parity relation provides information for 
determining the read-out direction of the codes. With this arrangement, 
the left-hand characters always start with light bars and the right-hand 
characters always start with dark bars (reading left to right). The whole 
structure of the character codes is as shown in the Table in FIG. 3. It 
should be noted that the number of dark modules in the left side digit is 
always 3 or 5 while the number is always 2 or 4 for the right hand digit. 
These characteristics are used as a parity check. The left side digits 
have odd parity while the right side digits have even parity. 
After a character is scanned, each module is assigned a binary value. Thus, 
as shown in FIGS. 4A and 4B, scanning of the modules in the direction as 
noted, a binary 1 signal is generated upon the sensing of a black bar, 
while a binary 0 signal is generated upon the sensing of a light bar or 
space. Because of problems in printing, it is uncommon for the width of 
the light bar and the black bar to be of the ideal value. Therefore, in 
decoding the UPC symbol, this condition must be taken into consideration. 
In addition, the tolerances for a UPC symbol or tag are larger for the 
space that starts or ends a character. Because of the print condition of 
the bar and space alluded to above, it has been found that the dimension 
tolerances between similar edges are better than between dissimilar edges, 
that is measuring the distance between trailing edges of adjacent bars and 
spaces or measuring the distance between the leading edges of adjacent 
bars and spaces produces data which gives high recognition efficiency to 
the system. 
Referring now to FIG. 5, there is illustrated the present method for 
recognizing the characters represented by the pattern of the UPC bar code 
as shown in FIG. 1. As previously described, each character comprises two 
dark bars and two white bars or spaces. Representing each bar and space as 
an interval, it will be seen that each character is composed of four 
intervals, where each interval is composed of the same background, either 
dark or white. To represent the most recent interval that has been sensed 
by the scanner, the designation I.sub.N is used with the designation 
V.sub.N representing the bar for that interval. The designation I.sub.N is 
an 11 bit binary number generated in a manner to be described hereinafter. 
To designate the interval preceding the current interval, the notation 
I.sub.N-1 and V.sub.N-1 is used. For the interval before that, the 
notation I.sub.N-2 and V.sub.N-2 is used and so on. The sum of the four 
consecutive intervals scanned by the scanner is shown in FIG. 5 by the 
notation S.sub.N where S.sub.N equals I.sub.N plus I.sub.N-1 plus 
I.sub.N-2 and I.sub.N-3. For each interval scanned, the system examines 
the three preceding scanned intervals together with the current scanned 
interval and assignal a hexadecimal value. Each interval that is scanned 
is then classified as a bar (binary 1) or a space (binary 0). If V.sub.N 
is a binary 1 (bar), then I.sub.N +I.sub.N-1 and I.sub.N-1 +I.sub.N-2 are 
compared to one half S.sub.N, 23/64 S.sub.N and 41/64 S.sub.N. From this 
comparison two sets of weights can be found. Each of these weights will be 
either 2, 3, 4 or 5. From these weights the system will determine if a 
character is odd or even parity. Further utilizing these weights, the 
system will establish the characters 0, 3, 4, 5, 6, and 9. However, two 
sets of ambiguous characters are found. The characters 1 and 7 are 
ambiguous, that is, both have the same apparent configuration, and also 
the characters 2 and 8. To distinguish between the characters 2 and 8 
requires finding if the interval I.sub.N-1 of each character is greater 
than the interval I.sub.N-2 . If it is greater, the character is 2. Odd 
parity 1 and 7 can be separated by determining if intervals I.sub.N is 
greater than the interval I.sub.N-1. If in this case it is greater, the 
character is a 1. Even parity 1 and 7 requires that the term 21/32 
I.sub.N-2 is greater than I.sub.N-1 . In this latter case, if the term is 
greater, the character is a 1. In all of these cases, the single intervals 
were all used to determine the ambiguous characters. 
Upon the scanning of each interval, the system will sum the three previus 
intervals together with the current scanned interval and then compare the 
sum of those four intervals S.sub.N (FIG. 5) with the previous sum S.sub.N 
generated to determine if they are equal within a predetermined limit. 
Thus, a signal EQUAL indicating equality will be generated if 27/32 
S.sub.N is less than S.sub.N-4 and S.sub.N is greater than 27/32 S.sub.N-4 
and no error is detected. An error condition exists where the width of an 
inerval exceeds the predetermined count. 
Referring to FIG. 1, it will be seen that the bar code symbol has left and 
right margins and the center band portion of the code. When scanning from 
left to right as viewed in FIG. 1, the left margin will be characterized 
as the in margin while the right margin will be characterized as the out 
margin. Similarly, the left portion of the center band will be 
characterized as the in center band and the right portion of the center 
band will be characterized as the out center band. These characteristics 
are reversed where the scanning takes place from a right to left 
direction. In order to identify this condition, the hexadecimal number 
being generated as a result of scanning each interval will indicate 
whether the interval scanned is a part of the in or out margin or the in 
or out center band is generated. The in margin is detected if there is a 
wide space interval adjacent to a guard bar. Thus, if (I.sub.N-6 
+I.sub.N-7) 5/16 is greater than I.sub.N-4 +I.sub.N-5 and S.sub.N is less 
than 27/32 S.sub.N-4 and V.sub.N-4 and V.sub.N-5, the interval is part of 
the in margin and a bit in the hexadecimal output number will indicate 
such a condition. With respect to the out margin, if (I.sub.N +I.sub.N-1) 
5/16 is greater than I.sub.N-1 +I.sub.N-2 and S.sub.N-4 is less than 27/32 
S.sub.N and V.sub.N-3 and V.sub.N-2, the interval is part of the out 
margin and the hexadecimal number generated by the system will indicate 
such a condition. The out center band will be detected if an ambiguous 
character (1, 7, 2 or 8) is detected and if S.sub.N is less than 27/32 
S.sub.N-4 and V.sub.N of the current inteval together with the V.sub.N-1 
together with the next interval scanned being any ambiguous character and 
the in margin is not detected, the hexadecimal number being outputted by 
the system will indicate the interval is part of the out center band. The 
in center band will be detected if any ambiguous character is detected and 
S.sub.N-4 is less than 27/32 S.sub.N and V.sub.N -5 and V.sub.N-4 together 
with the finding of the previous interval is an ambiguous character and if 
the out margin had not been detected, the hexadecimal output number will 
indicate that the inverval is a portion of the in center band. It will 
thus be seen that upon the scanning of each interval, the system will 
apply in parallel the above-cited logic test to determine the 
characteristics of the scanned interval, which characteristics are 
embodied as part of the binary hexadecimal number together with the 
additional binary bits generated for use in recognizing the character 
contained in the hexadecimal number being outputted at that time. As 
pointed out previously, each interval scanned will result in the 
outputting of a hexadecimal number which contains four binary-coded 
decimal (BCD) bits with only a portion of the hexadecimal numbers 
outputted being valid. 
Referring now to FIG. 6 there is shown a block diagram of the character 
recognition system in which the present embodiment is utilized including a 
slot scanner 20 which causes a laser beam to be reflected to produce a 
scanned pattern above and in front of a slot or opening adjacent the 
laser. If a UPC symbol or tag is placed such that the laser beam crosses 
the tag thereby reflecting the light from the bars and spaces which 
compose the UPC tag, a photodetector receiving the reflected light will 
transform the reflected light into an electrical signal. A video amplifier 
(not shown) located in the scanning unit generates, in response to the 
generated electrical signals, digital pulses STV (Set Video) indicating a 
space-to-bar transition and RTV (Reset Video) indicating a bar-to-space 
transition. The time interval between these pulses is a function of the 
width of the bar or space. The pulse width of the signals STV and RTV can 
be from 25 ns. to 2 us sec. Valid signals alternate are never closer 
together than 350 ns. This means that following a valid STV or RTV, 
multiple pulses may occur during this 350 ms. time period. 
These time intervals are transmitted to a counter control chip 22 (FIG. 6) 
in which the inervals are converted to a binary number by an interval 
counter (not shown) and then transmitted to a FIFO (First-In, First-Out) 
IC array (not shown). The FIFO time averages the time between intervals to 
an acceptable period. Either of the signals STV and RTV will stop the 
interval counter and cause that interval count along with the state of a 
VIDEO flip-flop (not shown) to be stored in a FIFO shift register (not 
shown). The VIDEO flip-flop will be true for a bar. The interval counter 
at this point is reset and the next interval count is started. If the 
output of the interval counter is greater than 1280 counts (32us.), an 
overflow condition is created. In the overflow state, ever 800 ns. of the 
count of 1280 and the last state of the VIDEO flip-flop will be loaded 
into the FIFO shift register. The occurence of the next STV or RTV signal 
will result in the loading of an additional 1280 count into the FIFO shift 
register. This condition will cause an error signal to be generated which, 
as will be described more fully hereinafter, will be sensed by the system 
at this time. Using this error signal, the system will disregard the data 
that is being generated by the slot scanner unit 20 and the counter 
control chip 22. The data contained in the FIFO shift registers located in 
the counter control chip 22 will be outputted to a decoder chip 24 under 
the control of clock pulses generated by a 40 Mhz. oscillator 26. The FIFO 
shift registers will output 11 bits of binary data representing the width 
of the interval being scanned over bus 23 (FIG. 6) together with a VIDEO 
signal indicating whether the interval is a bar or a space. Also outputted 
from the counter control chip 22 to the decoder chip 24 are clock pulses 
CLK. 
The decoder chip 24 (FIG. 6) contains a number of binary adders, 
comparators, shift registers and discrete logic elements which are used to 
decode the data being scanned by the slot scanner unit 20. The decoder 
chip 24 will output a hexadecimal number which includes four BCD bits 
representing a decimal character in addition to indicating margins, center 
bands and error. Three additional binary bits are outputted by the decoder 
chip 24 which represent the signal MARK to indicate the interval is a bar 
or a space, the signal EQUAL indicating that the current interval taken 
together with the three previous intervals are either equal or not equal 
in width to the previous four intervals and the signal ITY indicating 
that the interval is odd parity if true or even parity if false, thereby 
locating the interval on the left or right side of the center band. 
The output signals from the decoder chip 24 are transmitted to a frame 
control chip 28 (FIG. 6) which is the subject of the present invention and 
which separates the valid data from the invalid data being outputted by 
the decoder chip 24. The frame control chip 28 filters out this valid data 
by checking for framing character, that is , in and out margins, in and 
out center bands, and character equality to identify the valid characters 
being decoded by the decoder chip 24. A good segment of valid data is then 
transmitted over bus 29 to a microprocessor chip 30 for further 
processing. The frame control chip 28 functions also as a communication 
adapter for transmitting data to be sent from the microprocessor through 
an interface adapter 32 to a host terminal 34 over bus 33. The 
microprocessor chip 30 monitors photodetectors in the slot scanner unit 20 
to determine when an item is in position to be read by the slot scanner. 
This data is transmitted to the microprocessor 30 over a bus 36 coupled to 
a scanner control unit 38. Upon receiving the required control signals, 
the microprocessor will then start monitoring the frame control chip 28 
for information. The microprocessor does correlation analysis and modulo 
ten check to determine if it has a valid tag. Once a valid tag is 
assembled, the data is transmitted to the host terminal through the 
interface adapter 32. Reference should be made to the previously cited 
co-pending applications of Amacher et al., Ser. No. 043,933, filed May 30, 
1979, now U.S. Pat. No. 4,253,018 and Janes et al., Ser. No. 043,929, 
filed May 30, 1979, for a full disclosure of the decoder chip 24, Gardner 
et al., Ser. No. 043,930, filed May 30, l979, for a full disclosure of the 
frame control chip 28, and Naseem et al., Ser. No. 043,928, filed May 30, 
1979, for a full disclosure of the microprocessor chip 30, each assigned 
to the assignee of the present application, which disclosures are fully 
incorporated into this application by reference. 
The basic circuit configuration of the present invention is illustrated in 
FIGS. 7A and 7B. The input logic interface 80 receives data from the 
pattern recognition array located in the decoder chip 24 (FIG. 6). The 
input interface logic 80 includes an input latch, a BCD function decoder, 
a frame decoder, and a shift register data latch. 
Four binary coded hexadecimal data bits plus a parity bit which are 
received from the decoder chip 24 (FIG. 6) are outputted from the input 
logic interface 80 to each of a group of twelve shift registers 81a-c, 
82a-c, 83a-c and 84a-c, (FIG. 7A) which are used to capture valid data. 
The capture of the data by the shift registers is controlled by four frame 
state counters 85a-d. These four counters use the data generated by the 
BCD function and frame decoders transmitted from the input interface logic 
80 to decide which segments of data are valid and should be captured. The 
shift register in which the valid data is contained notifies the 
mcroporcessor 30 (FIG. 7B) when a valid segment is captured. 
The valid data is transmitted over the SR data bus 88 (FIG. 7A and 7B) to 
the command decode logic 90 (FIG. 7B), which also contains bus drivers. 
This interface sends the valid data to the microprocessor 30 over the 
microprocessor data bus DB 29. 
The SR data bus 88 also connects the command decode logic 90 with a host 
communication interface 94. This interface is necessary to couple the 
microprocessor with a peripheral device, such as a terminal 34. The 
terminal is linked to the communication interface 94 via an optically 
coupled interface adapter (OCIA) 32 over bus 33. When the microprocessor 
30 wishes to send data to the terminal 34, the data travels over the DB 
bus 29 to the host communication interface 94, which in turn signals the 
terminal 34. 
The terminal 34 sends data to the microprocessor 30 in a similar manner. 
The terminal 34 clocks the data via the OCIA 32 to the host communication 
interface 94, which notifies the microprocessor 30 that there is data 
waiting. The microprocessor 30 then transmits a signal to the interface 94 
which loads the data onto the SR data bus 88 for transmission to the 
command decode interface 90. The interface 90 transfers the data from the 
SR bus 88 to the DB bus 29 and sends the data to the microprocessor 30. 
The parity bit of the valid data segment appearing on the SR bus 88 is 
detected by a parity decode ROM 99. The ROM 99 receives the parity data 
from the SR bus 88 and sends the decoded information to the command decode 
logic 90, which sends the information to the processor 30 via the DB bus 
29. 
The data outputted from the pattern recognition array in the decoder chip 
24 (FIG. 6) consists of seven bits: four bits define a hexadecimal number, 
one bit detects parity, one bit detects equality, and one bit, called a 
MARK bit, tells whether the data represented is a space or a bar. As shown 
in FIG. 8, the four hexadecimal data bits (2.sup.0 -2.sup.3) plus the 
ITY bit P and the EQUAL bit EQ are transmitted through a line driver 
100 and are clocked into a flip-flop 102 by CLK1. CLK1 is generated by 
transmitting a clocking signal CLK through a gate 104 and a line driver 
106. The four hexadecimal data bits (2.sup.0 -2.sup.3) are inputted to a 
NAND gate 108 whose output signal NEXTERR is inverted by a gate 110. The 
signal NEXT ERR, outputted from gate 110, is present when all four data 
bits are present, and it indicates that an error has been detected by the 
pattern recognition array. 
The MARK bit M (FIG. 89 is transmitted through a driver 106 and is coupled 
with a signal NEXTERR outputted from NAND gate 108 via a NAND gate 112. 
The output of gate 112 is connected to the inverted input of an OR gate 
114. The output of gate 114 enables a flip-flop 116, which, together with 
a flip-flop 118, comprise a two binary counter 119. As each interval of 
data is received from the pattern recognition array, the counter 
increments once, generating a total of four states. The output signals ML 
and ML (Mark Latch) of flip-flop 16, and the output signals IDF and IDF 
(ID flip-flop) of flip-flop 18, are decode by gates 120-126 (FIG. 9) whose 
output decoded signals are latched into flip-flop 140. The four output 
signals of the flip-flop 140 indicated in FIG. 9 are the decoded reference 
frames FR.phi., FR1, FR2, and FR3, which clock the input data from the 
pattern recognition array into the proper shift registers. 
Any time the input data being read corresponds to a bar or space located in 
the symbol (FIG. 1) between the in margin and the center band, there will 
always be either a frame 1 or a frame 3 capture. When the bar of space is 
between the center band and the out margin, there will always be either a 
frame .phi. or a frame 2 capture. As shown in FIG. 8, the signal ML which 
appears on the Q output of flip-flop 116 is coupled with the signal 
NEXTERR appearing on the output of the inverter 110 (FIG. 8) by a NAND 
gate 142, whose output is connected to the second inverted input of an OR 
gate 114 which gate enables the counter 119 to advance one count upon the 
occurrence of the signal NEXTERR going low when the signal ML is high. 
As shown in FIG. 8, the 2.sup.0, 2.sup.1, and 2.sup.2 bits of the BCD data 
being outputted from flip-flop 102 are inverted by gates 144-148. The 
EQUAL bit EQ appearing on the Q.sub.5 output of flip-flop 102 is 
transmitted to a flip-flop 149. The 2.sup.0, 2.sup.1, and 2.sup.2 bits 
from flip-flop 102, the 2.sup.0, 2.sup.1, and 2.sup.2 bits, appearing on 
the output of the inverters 144-148 inclusive, and the 2.sup.3 bit are 
decoded by AND gates 150-158 (FIG. 10) whose output signals are latched 
into a flip-flop 164. The output signals of flip-flop 164 indicate whether 
a segment of data transmitted from the pattern recognition array 
represents an out margin (OUTMARG), in margin (INMARG), out center band 
(OUTCB), in center band (INCB), or error (ERR). 
Each of the output signals FR.phi., FR1, FR2, and FR3 from the flip-flop 
140 (FIG. 9) is applied to one of the frame state counters 85a--d (FIG. 
7A). The operation of the FR.phi. counter 85(a) and the FR1 counter 85 (b) 
will be described here, with the understanding that the FR2 counter 85(c) 
operates in a similar manner to FR.phi., and the FR3 counter 858(d) 
similar to FR1. 
As shown in FIG. 11, the output signal FR.phi. is applied to one input of a 
NAND gate 166. The signals INCB, from flip-flop 164 (FIG. 10), and EQL, 
from flip-flop 149 (FIG. 8), are applied to the inverted inputs of an OR 
gate 168, whose output is connected to the second input of gate 166. The 
output of gate 166 is coupled to the inverted input of an OR gate 169, as 
are the signals ERR and OUTMARG, from flip-flop 164 (FIG. 10). The output 
signal FR.phi. is also coupled with a signal CLK SR, a system clock, via a 
NAND gate 170 (FIG. 12). The output of gate 170 is a clock for a flip-flop 
172. The input to flip-flop 172 is the signal INCB, which is generated by 
transmitting the signal INCB from flip-flop 164 (FIG. 10) through an 
inverter 174 (FIG. 12). The purpose of flip-flop 172 is to generate a four 
interval buffer of the INCB signal. The flip-flop 172 is cleared by the 
signals OUTMARG and ERR, both transmitted from flip-flop 164 (FIG. 10). 
These two signals are applied to the inverted inputs of an OR gate 176 
whose output is coupled with the signal DVAL, a system clock, via an AND 
gate 178. The output signal .phi. MARGERR of gate 178 is connected to the 
master reset of flip-flop 172. 
Referring again to FIG. 11, the output of OR gate 169 is coupled with the 
system clock signal CLK SR via a NAND gate 180, whose output signal is 
transmitted to an inverted input of AND gates 182 and 184. The signal 
INCB.phi. transmitted from flip-flop 172 (FIG. 12) is applied to the 
second inverted input of AND gate 182, while the inverted signal output 
INCB.phi. of flip-flop 172 is applied to the second inverted input of gate 
184. The output of gate 182 is connected to the master reset of flip-flop 
188, and is used to clear flip-flop 188. The output of gate 184 is 
connected to the master set of flip-flop 188 for setting the flip-flop in 
a manner that will now be described. 
When the data from the pattern recognition array in the decoder chip 24 
(FIG. 6) indicates that in center band is being scanned, the signal 
INCB.phi. will go low four clock pulses later, and the output of gate 184 
will cause an eight bit binary counter 193, comprised of flip-flops 188, 
190, and 192, to be set to 1. When flip-flop 188 is set to 1, flip-flops 
190 and 192 are set to zero, since the output of gate 180 is inverted by a 
gate 194, and the output of gate 194 is connected to the master reset of 
flip-flops 190 and 192. Flip-flop 188, which is the least significant bit 
of the counter, is clocked by a four input NAND gate 195. Three of the 
inputs to gate 195 are signals EQL, from flip-flop 149 (FIG. 8), FR.phi., 
from flip-flop 140 (FIG. 9), and CLK SR. The fourth input is connected to 
the output of an OR gate 196. The three inverted inputs of gate 196 are 
taken from the inverted outputs of flip-flops 188 (Q.phi.1), 190 
(Q.phi.2), and 192 (Q.phi.3). 
The signal appearing on the inverted output of flip-flop 188 is fed back to 
its input and is also connected to the clock input of flip-flop 190. The 
signal appearing on the inverted output of 190 is fed back to its input, 
and is also connected to the clock input of flip-flop 192. The signal 
appearing on the inverted output of flip-flop 192 is fed back to its 
input, allowing the flip-flops 188-192 inclusive to function as an eight 
bit binary counter. 
In operation, the frame state counter FR.phi. 85(a) (FIG. 7A and 11) is 
initially set to 1 by the output signal of gate 184 (FIG. 11) and is 
clocked by the system clock signal CLK SR via gate 195, each time the EQL 
and FR.phi. signals are present and the counter is not a zero. When the 
counter is counted up to 6, indicating that six characters have been 
stored in the FR.phi. shift registers 81a-81c inclusive (FIG. 7A), (or 
when the counter has counted to four in the case of a four character 
symbol), the frame state counter 85a signals the shift registers that a 
segment has been captured in a manner that will now be described. 
Referring now to FIG. 13, the frame capture signal FR.phi.CAP is generated 
by a four input NAND gate 198 whose output is inverted by a gate 200. The 
FR.phi. output signal of flip-flop 140 (FIG. 9) is connected to one input 
of gate 198, while the system clock signal DVAL, is connected to another 
input. A third input is connected to the output of an AND gate 202, on 
whose inverted inputs appear the signals Q.phi.1 from flip-flop 188 (FIG. 
11), and Q.phi.3 from flip-flop 192 (FIG. 11). The fourth input to gate 
198 is a signal OUTMARG.phi., which is generated by a combination of 
several gates in the following manner. The signal OUTMARG.phi. appears on 
the output of an OR gate 204 which as applied to one of its inputs the 
signal OUTMARG, appearing on the output of an inverter 206, whose input 
signal OUTMARG is generated by flip-flop 164 (FIG. 10). The second input 
to gate 204 is connected to the output of a two input OR gate 208. 
One input of gate 208 is enabled when a four character segment is read by 
the scanner, and the other input is enabled by a six character segment in 
a manner that will now be described. A two input AND gate 210 has inputs 
of EQ, which is generated by the signal EQL from flip-flop 149 (FIG. 8) 
transmitted through an inverter 212, and the signal NOMARG, a 
microprocessor command. When a four character segment is scanned, EQ and 
NOMARG are both high, enabling AND gate 210. The output of AND gate 210 
enables gates 208 and 204, causing the signal OUTMARG.phi. to go high. 
An AND gate 214 has appearing on its inputs the signals NOMARG, a 
microprocessor command, Q.phi.2 from flip-flop 190 (FIG. 11), and Q.phi.3 
from flip-flop 192 (FIG. 11). When a six character segment is read, all 
three of these signals go high, enabling gates 214 (FIG. 13), 208, and 
204, thereby causing OUTMARG.phi. to go high. The NOMARG command is used 
to capture data from a symbol which does not have margins. When the symbol 
being read contains margins, the data capture is controlled by the signal 
OUTMARG at gate 204. This signal goes low, causing OUTMARG.phi., from gate 
204, to go high. When the eight bit binary counter 193 shown in FIG. 11 is 
counted to either 4 or 6, the output signals Q.phi.1 and Q.phi.3 are both 
low, enabling gate 202 (FIG. 13). Since the OUTMARG.phi. signal goes high 
and FR.phi. is also high, the system clock signal DVAL toggles gate 198, 
causing FR.phi.CAP to go high. This signal is used by the shift registers 
81a-81c inclusive (FIG. 7A) to capture the valid data. 
Referring now to FIG. 14, there is shown the logic associated with the 
frame 1 state counter 85(b) (FIG. 7A) in which the signal FR1 from the 
flip-flop 140 (FIG. 9) is applied to the frame state counter at an input 
to a NAND gate 166a. The signals INMARG, transmitted from flip-flop 164 
(FIG. 10), and EQL, transmitted from flip-flop 149 (FIG. 8), are applied 
to the inverted inputs of an OR gate 168a, whose output is connected to 
the second input of gate 166a. The output of 166a is connected to an 
inverted input of an OR gate 169a, as do the signals ERR and OUTMARG, from 
flip-flop 164 (FIG. 10). The signal FR1 is also coupled with the system 
clock CLK SR via a NAND gate 170a (FIG. 15). The output of gate 170a is a 
clock input for a flip-flop 172a, whose data input is the signal IN MARG, 
which is generated by transmitting signals INAMARG and NOMARG to the 
inverted inputs of an OR gate 174a. The purpose of flip-flop 172a is to 
generate a four interval buffer of the INMARG signal. Flip-flop 172a is 
cleared by the signal .phi.MARGERR from AND gate 178a via an OR gate 176a. 
Referring to FIG. 14, the output of OR gate 169a is coupled with the system 
clock signal CLKSR via a NAND gate 180a, whoe output signal is transmitted 
to an inverted input of AND gates 182a and 184a. The signal INMARG1 
transmitted from flip-flop 172a (FIG. 15) is applied to the second 
inverted input of gate 182a, together with the signal INMARG1 (FIG. 15) 
being applied to the second inverted input of gate 184a. the output of 
gate 182a is connected to the master reset of the flip-flop 188a, and is 
used to clear the flip-flop 188a. The output of gate 184a is connected to 
the master set of flip-flop 188a. When the data from the pattern 
recognition array in the decoder chip 24 indicates that an in margin is 
being scanned, the signal IMMARG1 will go low four clock pulses late, and 
the output of 184a will cause an eight bit binary counter 193a comprised 
of flip-flops 188a, 190a, and 192a, to be set to 1. When flip-flop 188a is 
set to 1, flip-flops 190a and 192a are set to zero, since the output of 
gate 180a is inverted by a gate 194a, and the output of 194a is connected 
to the master reset of flip-flops 190a and 192a. 
Flip-flop 188a, which is the least significant bit of the counter, is 
clocked by a four input NAND gate 195a. Appearing on three of the inputs 
to gate 195a are the signals EQL from flip-flop 149 (FIG. 8), FR1, from 
flip-flop 40 (FIG. 9), and the system clock CLK SR. The fourth input is 
connected to the output of an OR gate 169a. The three inverted inputs of 
gates 196a are taken from the inverted outputs of flip-flops 188a (Q11), 
190a, (Q12), and 192a (Q13). As shown in FIG. 14, the signal appearing on 
the inverted output of flip-flop 188a is fed back to the input and is also 
connected to the clock input of flip-flop 190a. The signal appearing on 
the inverted output of 190a is fed back to the input, and is also 
connected to the clock input of flip-flop 192a. The signal appearing on 
the inverted output of flip-flop 192a is fed back to its input. 
In operation, the frame state counter FR1 85(b) (FIG. 7A) is initially set 
to 1 and is clocked by the CLK SR signal via gate 195a each time the EQL 
and FR1 signals are present and the counter is not at zero. When the 
counter has counted up to 6, indicating that six characters have been 
stored in the FR1 shift registers 82a-82c (FIG. 7A) (or when the counter 
has counted to 4 in the case of a four character symbol) the frame state 
counter 85(b) signals the shift registers that a segment has been 
caputred. 
Referring now to FIG. 16, the frame capture signal FR1CAP is generated by a 
four input NAND gate 198a whose output is inverted by an inverter 200a. 
The FR1 signal is connected to one input of gate 198a, and the system 
clock signal DVAL is connected to another input. A third input to the gate 
198a is connected to the output of an AND gate 202a, whose inverted inputs 
are connected to Q11 tramsmitted from flip-flop 188a (FIG. 14), and to Q13 
from flip-flop 192a (FIG. 14). The fourth input to gate 198a is the signal 
OUTCB, which is the output of an inverter 204a, whose input OUTCB is 
generated by flip-flop 164 (FIG. 10). When the eight bit binary counter 
193a (FIG. 14) is counted to either 4 or 6, the output signals Q11 and Q13 
are both low, enabling gate 202a (FIG. 16). When an OUTCB signal is 
present along with signal FR1, the system clock signal DVAL toggles gate 
198a, causig the signal FR1CAP to go high. This signal is used by the 
shift registers 82a-82c (FIG. 7A) to capture the valid data. 
Referring now to FIG. 7A, there will be descirbed the operation of the 
shift register in capturing the valid data being outputted from the 
pattern recognition array located in the decoder chip 24 (FIG. 6). As 
shown in FIG. 8, the outputs of flip-flop 102 which comprise the 
hexadecimal bits 2.sup.0 -2.sup.3, and the parity bit P transmitted 
through a line driver 220 to flip-flop 149. The outputs of flip-flop 149 
are connected to the input of each of the twelve shift registers 81a-c, 
82a-c, 83a-c, and 84a-c (FIG. 7A). The twelve shift registers are divided 
into four groups, with three shift registers associated with each frame 
state counter 85a-85d. For ease of explanation, the operation of only one 
shift register will be discussed, it being understood that such operation 
is similar in the other shift registers. 
The circuit configuration of shift register 81a is shown in FIG. 17A and 
17B. Each shift register is a 5.times.6 bit shift register composed of 
five 1.times.6 flip-flops 222-230. Each hexadecimal bit of the data plus 
the ITY bit is inputted into one of the flip-flops. The data is clocked 
into the flip-flops via a NAND gate 232. The inputs to gate 232 are the 
signal FR.phi., from flip-flop 140 (FIG. 9), which is high during frame 
.phi., the signal F.phi.A, which is initially high, and the system clock 
signal CLK SR. The data is clocked into the ITY shift register 222 as 
the signal CLK SR toggles, while the hexadecimal data is clocked into the 
flip-flops 224-230 via a NOR gate 234. The NAND gate 232 also clocks a 
shift register 236 (FIG. 17A). The output of shift register 236 is 
connected to the input of a flip-flop 238 which is clocked by the signal 
FR.phi.CAP transmitted from gate 200 (FIG. 13). In operation, when the 
sixth character is clocked into the flip-flops 222-230, the output of 
shift register 236 goes high. This output is transmitted to the input of 
flip-flop 238, and is clocked into the flip-flop, since the signal 
FR.phi.CAP goes high when a segment is captured. The Q output signal 
F.phi.A of flip-flop 238 goes high, while the Q output, F.phi.A, goes low, 
thereby disabling gate 232, and removing the clocking signal from 
flip-flops 222-230. 
The output signal F.phi.A of flip-flop 238 is also used to clock a 
flip-flop 239 (FIG. 17B). When the segment captured by the shift register 
is a four character segment, the input signal Q.phi.2 to flip-flop 239 
goes high. When the other input signal F.phi.A to the flip-flop 239 goes 
high, the output signal 4.phi.A of flip-flop 239 also goes high. This 
output signal is used to tell the microprocessor that the segment captured 
is a four character segment. 
The output signal F.phi.A is also inputted to a four input NAND gate 240 
(FIG. 17A). Another input to gate 240 is the signal SYMCAP, which 
comprises the load signals from all twelve shift registers and goes to a 
low level if data is captured in any one of the shift registers. The third 
input signal, FR.phi., is high during frame .phi. , and the fourth input 
signal, CLK SR, is the system clock signal. When a segment is captured in 
the shift register, the output of gate 240 will enable the inverted input 
of an OR gate 242 (FIG. 17A) which, together with OR gate 244, forms a 
latch 241. 
The output signal LDF.phi.A of gate 242, when going high, enables a NOR 
gate 246 (FIG. 18), and also a NOR gate 247 with inverted inputs, causing 
the output signal SYMCAP of gate 247 to go low. Signals similar to 
LDF.phi.A transmitted from shift register 81b nd 81c (FIG. 7A) are also 
inputted to gate 246. Similar signals from shift registers 82a-c, 83a-c, 
and 84a-c are transmitted to gate 247 via NOR gates 248 and 249. The 
output signal SYMCAP is transmitted through a gate 250 directly to the 
microprocessor 30 (FIG. 6) as an interrupt, alerting it that a valid data 
segment has been captured. 
The output signals of gates 246 and 249 are also transmitted to the input 
of a NAND gate 251, as shown in FIG. 19. The output of gate 251 is 
connected to an inverted input of an OR gate 252. The other input to gate 
252 is normally high, and goes low only during the caputure of periodical 
data. The output of gate 252 is connected to an input of a tri-state 
buffer 253. When the load signal of one of the shift registers, such as 
LDF.phi.A, goes high, the output of gate 251 goes high, causing the input 
to buffer 253 to go low. When the microprocessor 30 (FIG. 6) is ready to 
read the shift register, it generates a clocking signal SR RD (the 
generation of the microprocessor command signals is described later). The 
signal SR RD goes low, enabling buffer 253 and causing the output line SR6 
of the SR data bus to go low. This signal aids the microprocessor in 
determining the type of segment which is captured in the shift register. 
Referring again to FIG. 17A, the signal SR RD generated by the 
microprocessor 30 (FIG. 6) is transmitted to one input of a NAND gate 254. 
Appearing on the other input to gate 254 is the signal LDF.phi.A, 
transmitted from gate 242. Appearing on the output of gate 254 is the 
signal LD.phi.A, which enables a tri-state buffer 255 to load the data 
from flip-flops 244-230 onto the SR data bus. The signal SR RD toggles 
gates 254 and 234 until it has clocked out the stored characters in 
parallel from flip-flops 244-230 over the SR bus and through the level 
converters 256 and 257 and the tri-state driver 258 (FIG. 24B) to the 
microprocessor. The signal SR RD from the microprocessor is used to clock 
data into a flip-flop 259 (FIG. 20) from the data lines SR4 and SR5, this 
data being used by the microprocessor in interpreting the type of symbol 
read. 
The parity bits P of the segment captured in the flip-flop 222 can be read 
by the microprocessor at this time. At this time, the flip-flop 222 has 
outputted all six bits in parallel to a tri-state buffer 260. The buffere 
260 is controlled by a NAND gate 261, which is enabled by the signals 
LDF.phi.A and TY transmitted from the OR gate 242 (FIG. 17A) and the 
microprocessor 30 (FIG. 6) respectively. Since the signal LDF.phi.A is 
already high, TY, which is a microprocessor controlled signal, must go 
high to transmit the data, over lines SR.phi.-5, onto the SR bus. When the 
microprocessor 30 is ready to read the parity data, it sends a command 
which is decoded by the command decode array 90 (FIG. 7B), transmitting 
the TY signal to gate 261 and also to an inverting gate 263, which is 
shown in FIG. 20. 
Referring to FIG. 20, the data appearing on lines SR.phi.-SR5 inclusive is 
latched into a flip-flop 264 and the signals converted by a level 
converter 265, enabling the signals to address a ROM 99. The signal 
DEC, which is another microprocessor based command, controls the chip 
select input to the ROM. When it is activated, it causes the address 
corresponding to the parity data to read out from the ROM 99 data to the 
microprocessor which indicates whether the segment read from the symbol is 
a left or a right half, whether it is rom one of a number of different 
type symbols or a symbol located on a periodical, and whether it was read 
forward or backward. This method of decoding saves approximately 200-300 
bytes of ROM in the microprocessor, in addition to saving time. 
Referring again to FIG. 17A, after the six characters and the parity data 
have been read into the microprocessor, a frame reset occurs in the 
following manner. A signal FR RST is generated by the microprocessor 30 
(FIG. 6) and sent to a NAND gate 268, which receives the signal LDF.phi.A 
from the OR gate 242 at another input. When the signal LDF.phi.A is high, 
the signal FR RST enables gate 268 and also an inverted input to an OR 
gate 270. The output signal F.phi.ARST of gate 270, is connected to the 
master reset of flip-flop 238 and 239, causing the output signal F.phi.A 
to go low, and also enabling the output signal LDF.phi.A of gate 244 to go 
high. This, in turn, allows the signal SYMCAP to return to its high state, 
via gates 246 and 247 (FIG. 18). With the signal SYMCAP high, the 
microprocessor is now able to read another shift register which has 
captured a valid segment. The signal F.phi.ARST is also connected to the 
parallel load input to shift register 236, allowing it to begin a new 
count. 
The reading of a UPC multi-symbol, such as occurs on a periodical, is 
accomplished in a similar manner to the reading of the other symbols. A 
UPC multi-symbol such as the type found on periodicals is shown in FIG. 
30. The first symbol 296 can be of the type shown in FIG. 1. Following the 
first symbol is a six module wide blank space. The second symbol 298, 
smaller than the first, follows the blank area. This symbol begins with a 
bar one module wide, then a space one module wide, and next a bar two 
modules wide. Following this, there may be either two or five characters. 
The multi-symbol or periodical symbol is scanned in the same manner as a 
regular UPC symbol. 
The capture of a periodical symbol is done only the F.phi.C shift register 
81(c) (FIG. 7A). The periodical latch, as will be described more fully 
hereinafter, is set by a command from the microprocessor. The output 
signal, PERIOD, generated by the latch is transmitted to a NAND gate 300 
(FIG. 17B). The signal FR.phi.CAP (FIG. 13) is also transmitted to gate 
300. The third input to gate 300 is connected to the output of an AND gate 
302. The six bits of data from flip-flop 222 (FIG. 17B) and the signal 
GO.phi.B (FIG. 17A) from an OR gate 304 are all transmitted to the 
inverted inputs of gate 302. When the scanner is scanning the area between 
the two symbols on a periodical, the output of gate 302 will go high. The 
signals PERIOD and FR.phi.CAP are also high, causing the output of gate 
300 to go low. This output signal L2R.phi., is connected to a latch, 305, 
formed by OR gated 306 and 308 (FIG. 17B). When the signal L2R.phi. goes 
low, latch 305 sets, and the output signal L2R of gate 306, goes high. 
Another input to gate 306 of the latch 305 is the signal L2R2. This signal 
is the equivalent of L2R.phi., except that it is generated at frame 2 
rather then frame .phi.. L2R2 is generated by a NAND gate 310. One input 
to the gate 310 is the signal PERIOD, and the other input is generated by 
an OR gate 312 via a NAND gate 314, using signals generated by frame 2 
(not shown). 
Referring to FIG. 21, there is shown the signals L2R and PERIOD being 
transmitted to a NAND gate 320. The signal START P, transmitted from the 
inverted output of a flip-flop 322, is also inputted to gate 320. When the 
scanner is in the area between the two tags during the scanning of a 
periodical label, all of these signals are high, enabling the system clock 
signal, CLK1, to toggle gate 320 thereby clocking the flip-flop 322. The 
data input to flip-flop 322 is the signal F.phi.C, which is high when no 
data is captured in the F.phi.C shift register 81c (FIG. 7). When the 
flip-flop 322 is clocked by gate 320, the output signal START P, goes 
high, and START P, the inverted output goes low, disabling gate 320. The 
signal START P is transmitted to the data input of a shift register 324 
which is clocked into the shift register 324 by the system clock signal 
CLK1. After six CLK1 clock pulses, the Q.sub.5 output of shift register 
324 goes high, which signal is transmitted to the master set input of a 
flip-flop 326, causing the output signal LOAD P of flip-flop 326 to go 
high. The high signal LOAD P is then transmitted to a NAND gate 328, where 
it is combined with the system clock signal DVAL. The output of gate 328 
is connected to an inverted input of an OR gate 330 on whose other input 
will appear a signal F.phi.CRST, which is the reset signal for the F.phi.C 
shift register 81c. The signal F.phi.CRST is similar to the reset signal 
F.phi.ARST (shown in FIG. 17A). The output signal of gate 330 is inverted 
by a gate 332, and then transmitted to the master reset input of shift 
register 324. 
In operation, as long as signal START P is present, the flip-flop 324 will 
produce an output at Q.sub.5 after six pulses of CLK1, generating the 
signal LOAD P from flip-flop 326, which clears flip-flop 324 via gated 
328, 330 and 332. This operation will cycle continuously until flip-flop 
322, which generates START P, is cleared by a signal transmitted through 
an OR gate 334 and a NAND gate 336. The input signals to gate 336 are PER, 
a signal generated by the flip-flop 338, and the logic voltage supply 
V.sub.DD. The output of gate 336 is connected to an inverted input to gate 
334. The other input to gate 334 is F.phi.CRST. The output of gate 334 is 
connected to the master reset input to flip-flop 322. 
The Q.sub.1 output of flip-flop 324 is connected to a NAND gate 340, while 
the Q.sub.2 output is connected to an inverted input of an AND gate 342. 
The other inverted input to gate 342 is connected to the Q.sub.0 output of 
flip-flop 338. In operation, after receiving the second clock pulse CLK1, 
the Q.sub.1 output from flip-flop 324 will be high, and the Q.sub.2 output 
low. The Q.sub.0 output from flip-flop 338 is also low at this time, 
enabling gate 342, whose output signal enables gate 340, since Q.sub.1 of 
flip-flop 324 is also high at this time. The output signal of gate 340 is 
inverted by the inverter 343 to generate a signal 1ST which is high for 
only one clock pulse of CLK1, since the next clock pulse causes Q.sub.2 of 
flip-flop 324 to go high, disabling gates 342 and 340. 
The signal 1ST is transmitted to the input of a NOR gate 334 (FIG. 22). The 
other input to gate 344 is LOAD P transmitted from flip-flop 326 (FIG. 
21). The output of gate 344 is connected to an inverted input of a four 
input OR gate 346, on whose other three inputs appear the signals ERR, 
OUTMARG, and INMARG, from flip-flop 164 (FIG. 10). The output of gate 346 
is connected to one input of a NAND gate 348 on whose other inputs appear 
the signals START P, from flip-flop 322 (FIG. 21), and the system clock 
signal CLK SR. The output of gate 348 is the signal CLK P, which is used 
to clock the shift register 338 (FIG. 21). When the signal 1ST pulses, it 
enables gates 344 and 346, which allows the signal CLK SR to toggle gate 
348, thereby generating the CLK P signal which in turn causes the shift 
register 338 to activate. After the 1ST signal is removed, CLK P can be 
generated by the LOAD P signal, or by the ERR, OUTMARG, or INMARG signals. 
Referring again to FIG. 21, it will be seen that when the signal CLK P has 
pulsed six times, the Q.sub.5 output signal PER of shift register 338, 
goes high. The signal PER is transmitted to gate 336 (FIG. 21), which 
causes the flip-flop 322 to clear, disabling CLK P (FIG. 22) in the manner 
described previously. 
The signal CLK P is transmitted to an inverted input of a NOR gate 350 
(FIG. 22), the output of which is the signal CP.phi.C, used to clock the 
periodical data into the flip-flop 352-358 (FIG. 23A) via an inverter 360. 
The signal CP.phi.C can also be clocked for normal operation by a NAND 
gate 362, the operation of which is similar to gate 240 of FIG. 17A. The 
signal CLK P is also transmitted to an OR gate 364 (FIG. 22), the output 
of which is the signal CP.phi., used to clock the parity data from the 
periodical symbol into a shift register 366 (FIG. 23B). The signal 
CP.phi.is also used to clock shift register 368 (FIG. 23A) in normal 
operation, the operation of which is similar to shift register 236 of FIG. 
17A. The signal CLK P (FIG. 22) can also be generated by the output of 
gate 362, which operation is similar to gate 232 of FIG. 17A. 
Referring to FIG. 23A and 23B, the signal PER is also transmitted to the 
master set input of a flip-flop 370 (FIG. 23A). When the signal PER goes 
high, the output signal F.phi.C of flip-flop 370, also goes high. The AND 
gates 372 and 374 are used to set flip-flop 370 during normal operation 
while the signal F.phi.C is connected to a flip-flop 376 (FIG. 23B), used 
to designate a four character capture in normal operation, and which 
operates in a similar manner to flip-flop 239 of FIG. 17B. The gate 378 is 
an inverter which is used to reset flip-flop 376. The signal F.phi.C is 
also transmitted to an AND gate 377 (FIG. 23A) whose other input is taken 
from the output of an AND gate 377, which has signals F.phi.A and F.phi.B 
appearing at its inputs. When the F.phi.C register 81(c) (FIG. 7A) has 
captured some data, the output signal of gate 377 goes high which is 
transmitted to a NAND gate 380 on whose other inputs include the signal 
FR.phi. and SYMCAP which when high allow the input clock signal CLK SR to 
toggle gate 380, causing a latch 381 formed by OR gates 382 and 384 to be 
set. The output signal LDF.phi.C of gate 382, also goes high, which causes 
the SYMCAP signal to go low via gates 246 and 247 (FIG. 18), signalling 
the microprocessor that a segment has been captured. 
The signal LDF.phi.C (FIG. 23A) is also transmitted to a NAND gate 385 
(FIG. 19), where it is combined with the PER signal (FIG. 21) to generate 
the signal PERRD which enables gate 252, and causes the SR6 line to go 
high when buffer 253 is clocked by the microprocessor generated signal SR 
RD, and thus aids the microprocessor in interpreting the type of symbol 
being read. The signal PERRD is also transmitted to an OR gate 386 (FIG. 
20). Since the signal PERRD is low at this time, it causes the D.sub.1 
input of flip-flop 259 to go low, and it is clocked into flip-flop 259 by 
SR RD, also helping the microprocessor in interpreting the type of symbol 
being read. 
Referring now to FIG. 22, the microprocessor 30 (FIG. 6) will generate the 
SR RD signal when it is ready to receive the data segment, sending that 
signal to a NAND gate 387. The load output signal LD.phi.C of gate 387, 
going low, enables a tri-state buffer 388 (FIG. 23B) to load the data onto 
the SR data bus, and also causes CP.phi.C to clock the data from 
flip-flops 352-358 to buffer 388. The microprocessor then clocks the 
parity data onto the SR data bus by generating the TY signal, which is 
combined with the signal LDF.phi.C (FIG. 23A) at an AND gate 390 whose 
output signal enables a tri-state buffer 392 (FIG. 23B) to load the parity 
data onto the SR bus comprising the bus lines SR0-SR5 inclusive. 
The F.phi.C register 81(c) (FIG. 7A) is reset when the microprocessor 
generates the FR RST signal, causing flip-flop 370 (FIG. 23A) to clear via 
an AND gate 394 and an OR gate 396. The clearing of flip-flop 370 causes 
the LDF.phi.C latch 381 to clear, allowing SYMCAP to return to the high 
state (FIG. 18), and allowing the shift register F.phi.C to capture more 
data. 
Referring now to FIG. 24A-24C inclusive, the microprocessor DB data bus 29 
(FIG. 7B) contains eleven bus lines: data lines DB0-DB7, ALE (Address 
Latch Enable), WR (Write), and RD (Read). The bus lines are connected to 
buffers 400 and 402. The data lines DB2 through DB7 are connected to the 
inverted inputs of an AND gate 404 whose output signal COMND, is used to 
decode the microprocessor read (RD) and write (WR) memory commands into 
special chip commands. The DB.phi. and DB1 data lines from buffer 402 are 
inverted by gates 406 and 408, and the four signals DB1, DB1, DB0, 
DB.phi.together with the COMND signal are decoded by NAND gates 410-416 
(FIG. 24C) to generate the command signals , SRD, COM, and RES which 
are clocked into a flip-flop 418 by the signal ALE from buffer 400, which 
is inverted by a gate 420 (FIG. 24A). The bus lines DB.phi., DB1, and DB3 
through DB7 are combined with the bus line DB2 outputted from an inverter 
gate 422, by an AND gate 424 and an inverter 426 to generate the signal 
CMND.phi.4, which is also stored in flip-flop 418. The command signal 
CMND.phi.4, , SRD, COM, and RES are combined with the WR and RD signals 
from the microprocessor to generate the command functions for the frame 
control chip. 
Referring now to FIG. 25, the RD signal is transmitted along with the 
signal from flip-flop 418 to the inverted inputs of an AND gate 428 to 
generate the signal TY (microprocessor command .phi..phi.RD). This 
signal, which is the parity read command, causes a valid parity segment 
which is captured in a shift register to be sent to the parity decode ROM 
99 (FIG. 7B) via the SR data bus 88. The RD signal is also transmitted 
along with the SRD signal from flip-flop 418 (FIG. 24C) to the inverted 
inputs of an AND gate 430 (FIG. 25) to generate the signal SR RD (.phi.1 
RD). This signal, which is the shift register read command, causes a valid 
captured data segment from a currently active shift register to be clocked 
onto the SR data bus and sent to the microprocessor. The SR RD signal is 
then transmitted through an inverter gate 432 to generate SR RD. The RD 
signal is also transmitted along with CMND.phi.4 from flip-flop 418 to the 
inverted inputs of an AND gate 434 (FIG. 26) to generate the signal DEC 
(.phi.4 RD), which is the parity decode command, and allows the 
microprocessor to read the parity bit information from the parity decode 
ROM 99 (FIG. 7B). This signal is also transmitted through an inverter 436 
(FIG. 26) to generate the DEC signal. 
The WR signal generated by the microprocessor 30 is transmitted along with 
the SRD signal to the inverted inputs of an AND gate 438 (FIG. 25) to 
generate the FR RST signal (.phi.1 WR). This signal, which is the frame 
reset command, allows a shift register that has previously stored data to 
start collecting new data. The WR signal is also transmitted along with 
the CMND.phi.4 signal to the inverted inputs of an AND gate 440 (FIG. 26) 
whose output is connected to a latch 441 formed by gates 442 and 444 (FIG. 
26). The output signal NOMARG (.phi.4 WR) of gate 444 allows segment 
captures by the shift registers without a margin requirement. The latch 
441 is cleared by transmitting the signal RESET to an input to gate 444. 
A pair of microprocessor command signals are used to control the reading of 
periodical symbols. These signals include the RD signal which is 
transmitted aong with the RES signal from flip-flop 418 (FIG. 24C) to the 
inverted inputs of an AND gate 446 (FIG. 25) whose output is connected to 
a latch 447 formed by NOR gates 448 and 450. The output of gate 448, the 
PERIOD signal (.phi.3 RD), is the set periodical command, which enables 
the F.phi.C shift register 81c (FIG. 7A) to capture a periodical tag. The 
latch 447 is reset by receiving the WR signal along with the RES signal 
applied to the inverted inputs of an AND gate 452. The output of gate 452 
(FIG. 25) is connected to one input of gate 448 of the latch 447, and is 
also connected to one input of a NOR gate 454. The output signal (RESET 
(.phi.3 WR)), is the chip reset command, which causes a general reset of 
the logic contained on the chip. The other input to gate 454 is connected 
to the output of an inverter 456 on whose input appears the PWRRST signal. 
This signal also causes a general reset of the chip logic via the RESET 
signal. The RESET signal is transmitted to an inverter 458 which outputs 
the signal RESET. The RESET signal sets the frame counter to FR.phi., 
resets the data captures of all twelve shift registers, and clears the 
send and receive logic of the host communication/OCIA interface in the 
manner previously described. 
A pair of memory command signals are used to enable the microprocessor 30 
(FIG. 7B) to communicate with the terminal 34 via the OCIA 31 and host 
communication interface 94. THe RD signal is transmitted along with the 
COM signal from flip-flop 418 (FIG. 24C) to the inverted inputs of an AND 
gate 460 (FIG. 25). The output signal RD COM (.phi.2 RD) of gate 460, 
allows the microprocessor to read data from the terminal which has been 
stored in a register in the OCIA. The WR signal is transmitted over the 
bus along with the COM signal from flip-flop 418 to the inverted inputs of 
an AND gate 462 (FIG. 25) to generate the WR COM signal (.phi.2 WR). This 
signal allows the microprocessor to send data to the terminal via the 
OCIA. 
The READ signal (FIG. 24B) which controls the tristate driver 258 that 
regulates the SR bus is generated by microprocessor memory command signals 
and CMND.phi.4 which are transmitted from the flip-flop 418 (FIG. 24C) 
to the inputs of a NAND gate 464. The output of gate 464 is inverted by an 
inverting gate 466 whose output is connected to an inverted input of an OR 
gate 468. The other signals which are transmitted to the inverted inputs 
of gate 468 from the flip-flop 418 are SRD and COM. The output of gate 468 
is inverted by an inverting gate 470 whose output signal READ, is coupled 
to an inverted input of a NAND gate 472. The other input of gate 472 
contains the signal RD. The output of gate 472 is connected to the 
enabling input of tri-state driver 258 enabling data to be transmitted to 
the microprocessor. Both RD and READ must be low in order for data to 
travel from the SR data bus to the microprocessor. 
The terminal 34 (FIG. 7B) is able to communicate with the microprocessor 30 
via the OCIA 32 and host communication interface 94. Data which is to be 
sent from the microprocessor 30 to the terminal 32 enters a shift register 
500 (FIG. 27) from the DB data bus lines DB0-DB7 inclusive. The 
microprocessor outputs a signal WR COM to the parallel load input of shift 
register 500 to allow the data to be loaded from the lines DB0-DB7. The 
signal WR COM is also transmitted to the master set input of a flip-flop 
502. The output of flip-flop 502 is connected to an inverted input of an 
AND gate 504, with the signal WR COM appearing on the other inverted 
input. The output signal R DATA of gate 504 notifies the terminal 34 that 
there is data at the hose communication interface 94. The signal WR COM is 
also transmitted to the master clear input of a flip-flop 506 whose Q 
output is inverted by a gate 508. The output signal SENT of inverter 508, 
notifies the microprocessor 30 (FIG. 29) when the data has been clocked 
out of the host communication interface 94 to the terminal. When the WR 
COM signal goes high, it causes the SENT signal to go high, indicating 
that the data is ready to be sent. 
The signal WR COM is also transmitted to the parallel load input of a shift 
register 510 (FIG. 27). This shift register counts the clocking pulses 
CLKIN, which clock the data from the host communication interface to the 
terminal. When the terminal is ready to receive the data, it transmits a 
series of pulses on the CLKIN line to shift registers 500 and 510 and 
flip-flops 502 and 506, via an inverter 512. The first eight CLK IN pulses 
clock the data from the DB data lines DB0-DB7 inclusive (FIG. 27) through 
shift register 500, flip-flop 502, and gate 504, over the R DATA line and 
through the OCIA to the terminal. The ninth CLKIN pulse causes the output 
of flip-flop 506 to go high, forcing the SENT signal to go low, indicating 
that all the data has been sent to the terminal. 
When the terminal has data to send to the microprocessor, it sends the data 
to the host communication interface serially via the SDATA line (FIG. 28). 
The data is transmitted to shift registers 514 and 516 via an inverter 
512. The terminal clocks the data into the shift registers with a CLK 0 
signal, which is inverted by a gate 518 and is transmitted to shift 
registers 514, 516, and 520. When a byte of data has been clocked into 
shift registers 514 and 516, the output of shift register 520, which 
counts the CLK 0 clock pulses, goes high. This output signal R COMM is 
transmitted to a NOR gate 522 (FIG. 18) whose output is connected to the 
inverted input of NOR gate 247. The output signal SYMCAP of gate 247 goes 
low when R COMM goes high, signalling the microprocessor to read the SR 
data bus. 
The signal R COMM is also transmitted to the tri-state buffer 253 (FIG. 
19). When the microprocessor reads the SR data bus, by generating the SR 
RD signal, the R COMM signal is transferred to the SR7 of the SR data bus 
line via buffer 253. Since the R COMM signal is high, the microprocessor, 
seeing that line SR7 is high, knows that there is data from the terminal 
waiting to be read. The microprocessor now generates a RD COM signal, 
which enables the tri-state buffers 526 and 528 (FIG. 28), sending the 
terminal data onto the SR data bus and over to the microprocessor. Signal 
RD COM is also transmitted to an OR gate 530 via an inverter 532. Gate 530 
causes a reset of shift register 520. 
As shown in FIG. 29, the microprocessor 30 has four output lines available 
for the slot scanner which include line 534 for tone, line 536 for good 
light, line 538 for bad light, and line 540 for laser on. The tone signal 
controls an audible signal which sounds whenever a label is read. The good 
light signal lights a light indicating the label read was valid. The bad 
light signal lights a light indicating the label read was invalid, while 
the LASER ON signal controls the window shutter, which allows the laser 
beam to come out. 
While the invention has been described in detail and with reference to a 
specific embodiment thereof, it will be understood by those skilled in the 
art that various changes and modifications can be made therein without 
departing from the spirit and scope of the invention. Therefore, it is to 
be understood that the present invention is not to be limited beyond that 
as required by the appended claims.