SEMICONDUCTOR MANUFACTURING APPARATUS, MEMORY DEVICE, AND METHOD OF MANUFACTURING THE MEMORY DEVICE

Provided is a semiconductor manufacturing apparatus including a transfer chamber, a first process chamber connected to the transfer chamber, and a second process chamber connected to the transfer chamber. The transfer chamber may be configured to transfer a substrate. The first process chamber may be configured to perform a first oxidation process for oxidizing a metal layer on the substrate at a first temperature. The second process chamber may be configured to perform a second oxidation process for oxidizing a metal layer on the substrate at a second temperature higher than the first temperature.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2017-0138456, filed on Oct. 24, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Inventive concepts relate to a memory device, and more particularly, to a variable resistance memory device including a magnetic tunnel junction structure including magnetic transition metal.

As electronic products operate at higher speeds and consume lower power, fast read/write operations and low operating voltages are desired for semiconductor devices embedded in the electronic products. Research is actively being conducted into a variable resistance memory device using magnetic resistance characteristics of a magnetic tunnel junction. Particularly, the variable resistance memory device is non-volatile and thus is regarded as a next-generation memory device. Currently, research is actively being conducted into spin transfer torque-magnetic random access memory (STT-MRAM), which may be capable of increasing a recording density.

SUMMARY

Inventive concepts provide a memory device and a method of manufacturing the memory device.

Inventive concepts also provide a semiconductor manufacturing apparatus for manufacturing the memory device.

According to an aspect of inventive concepts, a semiconductor manufacturing apparatus may include a transfer chamber, a first process chamber, and a second process chamber. The transfer chamber may be configured to transfer a substrate. The first process chamber may be connected to the transfer chamber and may be configured to perform a first oxidation process for oxidizing a metal layer on the substrate at a first temperature. The second process chamber may be connected to the transfer chamber and may be configured to perform a second oxidation process for oxidizing a metal layer on the substrate at a second temperature higher than the first temperature.

According to another aspect of inventive concepts, a semiconductor manufacturing apparatus may include a first process chamber, a second process chamber, and a transfer chamber. The first process chamber may be configured to operate at a first temperature. The second process chamber may be configured to operate at a second temperature that may be higher than the first temperature. A transfer chamber may be connected to the first process chamber and the second process chamber. The first process chamber may be configured to perform a first oxidation process for oxidizing a first metal layer on a substrate by injecting an oxygen gas into the first process chamber. The transfer chamber may be configured to transfer the substrate from the first process chamber to the second process chamber. The second process chamber may be configured to perform a second oxidation process for oxidizing a second metal layer provided on the oxidized first metal layer by injecting an oxygen gas into the second process chamber. The second metal layer may include a same material as the first metal layer.

According to another aspect of inventive concepts, a method of manufacturing a memory device may include forming a first magnetic layer on a substrate, forming a first metal layer on the first magnetic layer, oxidizing the first metal layer at a first temperature to form an oxidized first metal layer, forming a second metal layer on the oxidized first metal layer, and oxidizing the second metal layer at a second temperature higher than the first temperature. The second metal layer and the first metal layer may include a same material.

According to another aspect of inventive concepts, a memory device may include a lower magnetic layer, a tunnel barrier layer on the lower magnetic layer, and an upper magnetic layer on the tunnel barrier layer. The tunnel barrier layer may include a metal oxide layer and may have an oxygen density gradient along a thickness direction.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, inventive concepts will be described in detail by explaining embodiments of inventive concepts with reference to the attached drawings. Like reference numerals in the drawings denote like elements, and thus repeated descriptions thereof will be omitted.

FIG. 1is a cross-sectional view of a magnetic tunnel junction layer10of a memory device, according to some embodiments of inventive concepts.

Referring toFIG. 1, the magnetic tunnel junction layer10may include a first magnetic layer20, a second magnetic layer40, and a tunnel barrier layer30disposed between the first and second magnetic layers20and40.

The first magnetic layer20may include a pinned layer having a fixed magnetization direction. For example, the pinned layer may have perpendicular magnetic anisotropy indicating that the magnetization direction is fixed in any perpendicular direction, e.g., a direction perpendicular to an extension direction of the pinned layer, or in-plane magnetic anisotropy indicating that the magnetization direction is fixed in any in-plane direction, e.g., a direction parallel to the extension direction of the pinned layer.

The second magnetic layer40may include a free layer having a variable magnetization direction. The magnetization direction of the free layer may vary depending on a magnetic field applied thereto. The free layer may have perpendicular magnetic anisotropy or in-plane magnetic anisotropy.

A resistance value may be determined based on whether the magnetization direction of the free layer and the magnetization direction of the pinned layer are parallel or antiparallel to each other. When the magnetic field that is externally applied to the second magnetic layer40is gradually increased to a switching field corresponding to a threshold value for magnetization reversal, the resistance value may be instantaneously changed due to a magnetization reversal phenomenon.

The free layer and the pinned layer may have the same type of magnetic anisotropic. For example, when the free layer has in-plane magnetic anisotropy, the pinned layer may also be made of a material having in-plane magnetic anisotropy. Otherwise, when the free layer has perpendicular magnetic anisotropy, the pinned layer may also be made of a material having perpendicular magnetic anisotropy.

The tunnel barrier layer30may be disposed between the first and second magnetic layers20and40and a quantum tunneling phenomenon may occur therein. The tunnel barrier layer30may include metal oxide having insulating properties. For example, the tunnel barrier layer30may include magnesium oxide (MgO) or aluminum oxide (AlOx). The tunnel barrier layer30may have a small thickness of about 1 Å to about 100 Å, but is not limited thereto.

In some embodiments, the tunnel barrier layer30may be made of metal oxide and may have an oxygen density gradient, which indicates a variation in oxygen density, in a thickness direction thereof, e.g., a direction perpendicular to an extension direction of the tunnel barrier layer30. For example, the tunnel barrier layer30may have a lower part30L in contact with the first magnetic layer20and an upper part30U in contact with the second magnetic layer40, and an oxygen density of the upper part30U may be greater than the oxygen density of the lower part30L.

FIG. 2is a schematic view showing the configuration of a memory device including the magnetic tunnel junction layer10ofFIG. 1.

Referring toFIG. 2, a unit memory cell MC configured as spin transfer torque-magnetic random access memory (STT-MRAM) is shown.

The unit memory cell MC may include the magnetic tunnel junction layer10and a cell transistor CT. A gate of the cell transistor CT may be connected to a word line WL. Any electrode of the cell transistor CT may be connected through the magnetic tunnel junction layer10to a bit line BL, and the other electrode thereof may be connected to a source line SL.

The magnetic tunnel junction layer10may include the first magnetic layer20including a pinned layer having a fixed magnetization direction and the second magnetic layer40including a free layer having a variable magnetization direction depending on a condition. A resistance value of the magnetic tunnel junction layer10may vary depending on the magnetization direction of the free layer. When the magnetization direction of the free layer and the magnetization direction of the pinned layer are parallel to each other, the magnetic tunnel junction layer10may have a relatively low resistance value and may store data ‘0’. Otherwise, when the magnetization direction of the free layer and the magnetization direction of the pinned layer are antiparallel to each other, the magnetic tunnel junction layer10may have a relatively high resistance value and may store data ‘1’.

In some embodiments, for a write operation of the STT-MRAM, the unit memory cell MC may apply a logic high voltage to the word line WL to turn on the cell transistor CT, and apply a write current WC1or WC2between the bit line BL and the source line SL. The magnetization direction of the free layer may be determined based on a direction of the write current WC1or WC2. The magnetization direction of the free layer in the magnetic tunnel junction layer10may be changed due to spin transfer torque. That is, the magnetic tunnel junction layer10may perform a memory function by using a spin transfer torque phenomenon in which a magnetization direction of a magnetic substance is variable depending on an input current.

In some embodiments, for a read operation of the STT-MRAM, the unit memory cell MC may apply a logic high voltage to the word line WL to turn on the cell transistor CT, and apply a read current from the bit line BL toward the source line SL to read data stored in the magnetic tunnel junction layer10. Since an intensity of the read current is much less than the intensity of the write current WC1or WC2, the magnetization direction of the free layer is not changed due to the read current.

Although the first magnetic layer20has a pinned layer and the second magnetic layer40has a free layer inFIG. 2, unlike this, the first magnetic layer20may have a free layer and the second magnetic layer40may have a pinned layer.

FIG. 3is a flowchart of a method of manufacturing a magnetic tunnel junction layer10of a memory device, according to some embodiments of inventive concepts, andFIGS. 4A to 4Fare cross-sectional views for describing the method of manufacturing the magnetic tunnel junction layer10of the memory device, according to some embodiments of inventive concepts.

Referring toFIGS. 3 and 4A, the first magnetic layer20is formed on a substrate11(S110). To form the first magnetic layer20, a seed layer21and a pinned layer23may be sequentially formed on the substrate11.

The seed layer21may include at least one of tantalum (Ta), ruthenium (Ru), and/or alloys thereof. For example, the seed layer21may be formed by using one of the above-mentioned materials or by stacking two or more of the above-mentioned materials. The seed layer21may aid growing of the pinned layer23, and may promote crystallization of the pinned layer23.

The pinned layer23may include a magnetic material including transition metal. The pinned layer23may include at least one of palladium (Pd), cobalt (Co), platinum (Pt), iron (Fe), ruthenium (Ru), tantalum (Ta), nickel (Ni), boron (B), manganese (Mn), antimony (Sb), aluminum (Al), chromium (Cr), molybdenum (Mo), silicon (Si), copper (Cu), iridium (Ir), and/or alloys thereof. Materials usable for the pinned layer23may include, for example, cobalt-iron (CoFe), nickel-iron (NiFe), and/or cobalt-iron-boron (CoFeB), but are not limited thereto. The pinned layer23may be formed by using one of the above-mentioned materials or by stacking two or more of the above-mentioned materials.

Referring toFIGS. 3 and 4B, after the first magnetic layer20is formed, a first metal layer31is formed on the first magnetic layer20(S120). The first metal layer31may include a metal for forming a tunnel barrier layer and may be made of, for example, magnesium (Mg) or aluminum (Al). In some embodiments, the first metal layer31may be formed to have a thickness between 1 Å and 5 Å.

To form the first metal layer31, a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process may be used. In some embodiments, the first metal layer31may be formed by a sputtering process.

Referring toFIGS. 3 and 4C, after the first metal layer (31ofFIG. 4B) is formed, the first metal layer is oxidized at a first temperature (S130). As the first metal layer is oxidized, a first interlayer31aincluding metal oxide obtained due to oxidation of a part of the metal included in the first metal layer may be formed.

The first temperature may be in a range that is greater than or equal to 20° C. and less than 50° C., but is not limited thereto. For example, the first temperature may be room temperature. The oxidation process for oxidizing the first metal layer may be performed in a certain oxidation atmosphere71including an oxygen gas and an inert gas for controlling a pressure of the oxidation process. In some embodiments, in the oxidation process for oxidizing the first metal layer, the oxygen gas may be supplied into a chamber for the oxidation process at a flow rate between 0.01 sccm and 10 sccm.

Since the first metal layer is oxidized at the oxidation atmosphere71having a relatively low temperature and a relatively low oxygen flow rate, only a part of the metal included in the first metal layer may be oxidized. For example, when the first metal layer is made of magnesium (Mg), the first interlayer31amay include magnesium (Mg) and magnesium oxide (MgO).

Referring toFIGS. 3 and 4D, a second metal layer35is formed on the oxidized first metal layer, e.g., the first interlayer31a(S140). The second metal layer35may be made of, for example, magnesium (Mg) and/or aluminum (Al). In some embodiments, the second metal layer35may be made of a material that is the same as the material of the first metal layer (31ofFIG. 4B). The second metal layer35may be formed to have a thickness greater than the thickness of the first metal layer31, e.g., a thickness between 10 Å and 100 Å.

To form the second metal layer35, a PVD process or a CVD process may be used. In some embodiments, the second metal layer35may be formed by a sputtering process.

Referring toFIGS. 3 and 4E, after the second metal layer (35ofFIG. 4D) is formed, the second metal layer35is oxidized at a second temperature higher than the first temperature (S150). As the second metal layer (35ofFIG. 4D) is oxidized, a second interlayer35aincluding metal oxide obtained due to oxidation of a part of the metal included in the second metal layer35may be formed. The second interlayer35aand a first interlayer31bmay form a tunnel barrier layer30.

The second temperature may be, for example, between 50° C. and 400° C. In some embodiments, the second temperature may be between 100° C. and 200° C. For example, to perform the oxidation process for oxidizing the second metal layer35at the second temperature, heat83may be applied to the substrate11.

The oxidation process for oxidizing the second metal layer35may be performed in a certain oxidation atmosphere81including an oxygen gas and an inert gas for controlling a pressure of the oxidation process. In the oxidation process for oxidizing the second metal layer35, the oxygen gas may be supplied into a chamber for the oxidation process at a flow rate between 0.1 sccm and 100 sccm.

The second metal layer35may be oxidized at the oxidation atmosphere81having a relatively high temperature and a relatively high oxygen flow rate. Accordingly, a rate by which the metal included in the second metal layer35is oxidized into metal oxide due to the oxidation process for oxidizing the second metal layer35may be higher than the rate by which the metal included in the first metal layer (31ofFIG. 4B) is oxidized into metal oxide due to the oxidation process in S130.

In the oxidation process for oxidizing the second metal layer35, oxygen may be diffused to the first interlayer31bunder the second metal layer35. Accordingly, during the oxidation process for oxidizing the second metal layer35, non-oxidized metal in the first interlayer31aofFIG. 4Dmay be oxidized into metal oxide. Since the first interlayer31bmay be further oxidized during the high-temperature oxidation process, crystallinity of the tunnel barrier layer30may be increased and tunneling magnetoresistance ratio (TMR) characteristics may be enhanced.

According to inventive concepts, by forming the first interlayer (31aofFIG. 4C) having a low oxygen density before the high-temperature oxidation process for increasing crystallinity of the tunnel barrier layer30, diffusion of oxygen to the first magnetic layer20during the high-temperature oxidation process may be reduced and/or prevented. That is, the first interlayer may serve as an oxidation barrier capable of reducing and/or preventing diffusion of oxygen to the first magnetic layer20in the high-temperature oxidation process for oxidizing the second metal layer (35ofFIG. 4D). Accordingly, oxidation of the first magnetic layer20in the high-temperature oxidation process may be reduced and/or prevented and thus dispersion between different memory devices on the substrate11may be reduced and/or prevented.

Referring toFIGS. 3 and 4F, after the oxidation process for oxidizing the second metal layer (35ofFIG. 4D) is performed, the second magnetic layer40is formed on the oxidized second metal layer, e.g., the second interlayer35a(S160). The first magnetic layer20, the tunnel barrier layer30, and the second magnetic layer40may form the magnetic tunnel junction layer10.

The second magnetic layer40may be a free layer and may include a magnetic material including transition metal. The free layer may include at least one of palladium (Pd), cobalt (Co), platinum (Pt), iron (Fe), ruthenium (Ru), tantalum (Ta), nickel (Ni), boron (B), manganese (Mn), antimony (Sb), aluminum (Al), chromium (Cr), molybdenum (Mo), silicon (Si), copper (Cu), iridium (Ir), and/or alloys thereof. Materials usable for the free layer may include, for example, cobalt-iron (CoFe), nickel-iron (NiFe), and cobalt-iron-boron (CoFeB). The free layer may be formed by using one of the above-mentioned materials or by stacking two or more of the above-mentioned materials.

FIGS. 5A and 5Bare cross-sectional views for describing a part of a method of manufacturing a magnetic tunnel junction layer of a memory device, according to other embodiments of inventive concepts.

Referring toFIG. 5A, the first magnetic layer20is formed on the substrate11by using the method described above in relation toFIG. 4A, and a first sub interlayer31sais formed on the first magnetic layer20. The first sub interlayer31samay be formed by forming a first sub metal layer similarly to the method described above in relation toFIG. 4Bto form the first metal layer (31ofFIG. 4B), and then oxidizing the first sub metal layer similarly to the method described above in relation toFIG. 4Cto oxidize the first metal layer.

After the first sub interlayer31sais formed, a second sub metal layer33smay be formed on the first sub interlayer31sa.The second sub metal layer33smay be formed similarly to the method described above in relation toFIG. 4Bto form the first metal layer (31ofFIG. 4B).

Referring toFIG. 5B, a second sub interlayer33samay be formed by oxidizing the second sub metal layer (33sofFIG. 5A) in a certain oxidation atmosphere71. The oxidation process for oxidizing the second sub metal layer may be performed under a condition similar to that of the oxidation process for forming the first interlayer31aofFIG. 4C. The first and second sub interlayers31saand33samay form a first interlayer31a′ for reducing and/or preventing diffusion of oxygen to the first magnetic layer20during a subsequent high-temperature oxidation process.

By repeatedly performing a metal layer deposition process and a metal layer oxidation process at least two times to form the first interlayer31a′, diffusion of oxygen in a high-temperature oxidation process may be effectively blocked.

Herein, a metal layer deposition process and a metal layer oxidation process are sequentially and repeatedly performed two times to form the first interlayer31a′. However, a metal layer deposition process and a metal layer oxidation process may be sequentially and repeatedly performed three or more times.

After the first interlayer31ais formed, a second interlayer and a second magnetic layer may be formed by using the method described above in relation toFIGS. 4D to 4F, thereby forming the magnetic tunnel junction layer.

FIGS. 6A and 6Bare cross-sectional views for describing a part of a method of manufacturing a magnetic tunnel junction layer of a memory device, according to other embodiments of inventive concepts.

Referring toFIG. 6A, the first magnetic layer20and an oxidized metal layer are formed on the substrate11by using the method described above in relation toFIGS. 4A to 4C, and a third sub interlayer35sais formed on the oxidized metal layer. The third sub interlayer35samay be formed by forming a third sub metal layer similarly to the method described above in relation toFIG. 4Dto form the second metal layer (35ofFIG. 4D), and oxidizing the third sub metal layer similarly to the method described above in relation toFIG. 4Eto oxidize the second metal layer35. During the oxidation process for oxidizing the third sub metal layer, oxygen may be diffused to below the third sub metal layer and the oxidized metal layer may be further oxidized to form the first interlayer31b.

After the third sub interlayer35sais formed, a fourth sub metal layer37smay be formed on the third sub interlayer35sa.The fourth sub metal layer37smay be formed similarly to the method described above in relation toFIG. 4Dto form the second metal layer (35ofFIG. 4D).

Referring toFIG. 6B, a fourth sub interlayer37samay be formed by oxidizing the fourth sub metal layer (37sofFIG. 6A) in a certain oxidation atmosphere81. The oxidation process for oxidizing the fourth sub metal layer may be performed under a condition similar to that of the oxidation process described above in relation toFIG. 4Eto form the second interlayer (35aofFIG. 4E). During the oxidation process for oxidizing the fourth sub metal layer, oxygen may be diffused to below the fourth sub metal layer, the third sub interlayer35saofFIG. 6Amay be further oxidized to form a third sub interlayer35sb,and the first interlayer31bofFIG. 6Amay be further oxidized to form a first interlayer31c.The third and fourth sub interlayers35sband37samay form a second interlayer35a′.

Herein, a metal layer deposition process and a metal layer oxidation process are sequentially and repeatedly performed two times to form the second interlayer35a.However, a metal layer deposition process and a metal layer oxidation process may be sequentially and repeatedly performed three or more times.

After the second interlayer35a′ is formed, a second magnetic layer may be formed by using the method described above in relation toFIG. 4F, thereby forming the magnetic tunnel junction layer.

FIGS. 7A to 7Fare cross-sectional views for describing a method of manufacturing a memory device, according to some embodiments of inventive concepts.

Referring toFIG. 7A, an active region ACT and word lines WL may be formed in a substrate101. The substrate101may include silicon (Si), e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon. Otherwise, the substrate101may include at least one of a semiconductor element such as germanium (Ge), Silicon germanium (SiGe), Silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and/or indium phosphide (InP). Alternatively, the substrate101may include a silicon on insulator (SOI) structure. Alternatively, the substrate101may include a conductive region, e.g., a well doped with impurities or a structure doped with impurities.

The active region ACT may be defined by forming an isolation layer102in the substrate101. The isolation layer102may be made of an insulating material. The isolation layer102may be formed by, for example, a shallow trench isolation (STI) process. The isolation layer102may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The active region ACT may include first and second impurity regions110aand110bformed by ion-injecting impurities into upper parts of the active region ACT to a certain depth. The first and second impurity regions110aand110bmay be formed to a depth smaller than that to bottom surfaces of the word lines WL. The first and second impurity regions110aand110bmay serve as, for example, source/drain regions of a transistor formed by the word lines WL.

Then, the word lines WL may be formed in the active region ACT. A plurality of trenches103T may be formed in the substrate101, and then a gate insulating layer104and the word line WL made of a conductive material may be sequentially formed in each trench103T. A gate capping layer105may be formed on the word line WL to fill a remaining space of the trench103T. The word line WL may be formed in the trench103T, and a level of a top surface of the word line WL may be lower than that of the top surface of the active region ACT.

Herein, a buried channel array transistor (BCAT) including buried word lines WL is described as an example. However, in other embodiments, the transistor structure may be modified into a planar transistor, a recess channel array transistor (RCAT), a sphere-shaped recess channel array transistor (SRCAT), or the like, but is not limited thereto.

Then, a first interlayer dielectric layer120and first and second contact plugs123and125may be formed on the substrate101in which the active region ACT and the word lines WL are formed.

By removing parts of the first interlayer dielectric layer120by an exposure process and an etching process, contact holes penetrating through the first interlayer dielectric layer120may be formed. Thereafter, a conductive material may be formed on the first interlayer dielectric layer120to fill the contact holes, and may be partially removed by a planarization process such as a chemical mechanical polishing process or an etch-back process so that a top surface of the first interlayer dielectric layer120is exposed, thereby forming the first and second contact plugs123and125contacting the first and second impurity regions110aand110b.The first and second contact plugs123and125may include at least one of, for example, doped silicon, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and/or metal silicide.

Then, a source line SL may be formed by forming a conductive material on the first interlayer dielectric layer120to contact the first contact plug123and patterning the conductive material. The conductive material may include at least one of doped poly silicon, metal silicide, metal, and/or metal nitride.

Then, a second interlayer dielectric layer130may be formed on the first interlayer dielectric layer120to cover the source line SL. The second interlayer dielectric layer130may be made of a material that is the same as or similar to that of the first interlayer dielectric layer120. Contact holes may be formed to expose at least parts of top surfaces of the second contact plugs125by removing parts of the second interlayer dielectric layer130. Third contact plugs135may be formed to contact the second contact plugs125by forming a conductive material in the contact holes and performing a planarization process. The third contact plugs135may be made of a material that is the same as or similar to that of the second contact plugs125.

Then, a lower electrode145may be formed to cover the third contact plugs135and the second interlayer dielectric layer130. The lower electrode145may include a conductive material such as at least one of titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W). In some embodiments, the lower electrode145may have a double layer structure of ruthenium/titanium, ruthenium/tantalum, ruthenium/titanium nitride, ruthenium/tantalum nitride, titanium nitride/tungsten, or the like. The lower electrode145may be formed by an atomic layer deposition (ALD) process, a CVD process, or the like.

Then, a magnetic tunnel junction layer150and a capping electrode layer160may be sequentially formed on the lower electrode145. The magnetic tunnel junction layer150may be formed by using the method described above in relation toFIGS. 4A to 4F, the method described above in relation toFIGS. 5A and 5B, or the method described above in relation toFIGS. 6A and 6B.

In some embodiments, after the magnetic tunnel junction layer150is formed, a heat treatment process may be performed on the magnetic tunnel junction layer150to set a single desired magnetization direction of the magnetic tunnel junction layer150. For example, the heat treatment process may be performed in a pressure range equal to or less than 0.1 mTorr and in a temperature range of 300° C. to 400° C. The heat treatment process may be performed in a gas atmosphere including at least one gas among hydrogen, oxygen, and/or nitrogen. In addition, an inert gas may be injected to control a pressure of the heat treatment process.

Referring toFIG. 7B, mask patterns165P may be formed on the capping electrode layer (160ofFIG. 7A) to correspond to locations of the third contact plugs135. The capping electrode layer (160ofFIG. 7A), a second magnetic layer (155ofFIG. 7A), a tunnel barrier layer (153ofFIG. 7A), a first magnetic layer (151ofFIG. 7A), and the lower electrode layer (145ofFIG. 7A) may be sequentially patterned by using the mask patterns165P as an etching mask. Due to the patterning process, magnetic tunnel junction structures150P including second magnetization patterns155P, tunnel barrier patterns153P, and first magnetization patterns151P may be formed.

The mask patterns165P may include silicon oxide, silicon nitride, silicon oxynitride, or the like. The patterning process may be performed by a dry etching process. Specifically, the patterning process may be performed by an ion beam etching process or a reactive ion etching process. During the etching process, parts of a top surface of the second interlayer dielectric layer130, which are exposed between the magnetic tunnel junction structures150P, may be recessed. Herein, the magnetic tunnel junction structures150P have an etching profile having a constant cross-sectional area. In other embodiments, the magnetic tunnel junction structures150P may have an etching profile having a gradually increasing cross-sectional area from an upper part to a lower part thereof.

Referring toFIG. 7C, a passivation layer170may be formed to cover lower electrode patterns145P, the magnetic tunnel junction structures150P, capping electrode patterns160P, the mask patterns165P, and the second interlayer dielectric layer130. The passivation layer170may include, for example, metal oxide obtained due to oxidation of metals included in the magnetic tunnel junction structures150P. The passivation layer170may be formed by an oxidation process, a CVD process, or the like.

The passivation layer170covering outer walls of the magnetic tunnel junction structures150P may limit and/or prevent oxidation of the first and second magnetization patterns151P and155P.

Referring toFIG. 7D, an isolation insulation layer180may be formed on the passivation layer170to entirely fill spaces between the magnetic tunnel junction structures150P. The isolation insulation layer180may be made of a material that is the same as or similar to that of the first interlayer dielectric layer120.

Referring toFIG. 7E, isolation insulating patterns180P and passivation patterns170P may be formed and top surfaces of the capping electrode patterns160P may be exposed by performing a planarization process to remove parts of the isolation insulation layer (180ofFIG. 7D) and the passivation layer (170ofFIG. 7D).

The planarization process may be performed by a chemical mechanical polishing process or an etch-back process. Due to the planarization process, the top surfaces of the capping electrode patterns160P and top surfaces of the isolation insulating patterns180P may have the same height. That is, the capping electrode patterns160P may serve as an etch stop layer.

Referring toFIG. 7F, after the planarization process is completed, a top capping layer185and a third interlayer dielectric layer190may be sequentially formed to cover both of the top surfaces of the capping electrode patterns160P and the top surfaces of the isolation insulating patterns180P.

Subsequently, line-shaped mask patterns may be formed on the third interlayer dielectric layer190, and then the third interlayer dielectric layer190and the top capping layer185may be partially etched, thereby forming line-shaped openings to expose the capping electrode patterns160P.

Then, a conductive material may be formed to fill the openings and bit lines BL may be formed by a planarization process. A level of top surfaces of the bit lines BL may be the same as that of a top surface of the third interlayer dielectric layer190. The bit lines BL may be made of metal having a low resistivity, e.g., copper (Cu).

Ultimately, the variable resistance memory device100may include the substrate101, the isolation layer102in the substrate101, the active region ACT defined in the substrate101by the isolation layer102, the word lines WL buried in the substrate101, and the source line SL and the magnetic tunnel junction structures150P provided above the substrate101.

The variable resistance memory device100may further include the first contact plug123for connecting the source line SL to the active region ACT, the second contact plugs125for connecting the active region ACT to the magnetic tunnel junction structures150P, the lower electrode patterns145P and the capping electrode patterns160P provided in contact with the magnetic tunnel junction structures150P, the third contact plugs135for connecting the lower electrode patterns145P to the second contact plugs125, and the bit lines BL connected to the capping electrode patterns160P. The magnetic tunnel junction structures150P may include the first magnetization patterns151P, the tunnel barrier patterns153P, and the second magnetization patterns155P.

FIG. 8is a graph for describing characteristics of a memory device manufactured using a memory device manufacturing method according to some embodiments of inventive concepts.

Referring toFIG. 8, TMR characteristics of memory devices according to comparative example 1, comparative example 2, and an embodiment are shown. Herein, the comparative example 1 indicates a memory device including a tunnel barrier layer formed by only an oxidation process at a first temperature corresponding to a relatively low temperature, and the comparative example 2 indicates a memory device including a tunnel barrier layer formed by only an oxidation process at a second temperature corresponding to a relatively high temperature. For example, the memory device according to the embodiment may be manufactured through manufacturing method described above with reference toFIGS. 3 to 7F. It is shown that the memory device according to the embodiment has improved TMR characteristics compared to the comparative examples1and2.

FIG. 9is a schematic diagram of a semiconductor manufacturing apparatus1000according to some embodiments of inventive concepts.

Referring toFIG. 9, a cluster-type semiconductor manufacturing apparatus1000capable of processing a plurality of substrates S is shown. The cluster-type semiconductor manufacturing apparatus1000may refer to a multi-chamber substrate processing system including a transfer robot (or a handler) and a plurality of substrate processing modules provided around the transfer robot.

The semiconductor manufacturing apparatus1000may include a load port1100, an equipment front end module1200, and manufacturing process equipment1300.

The load port1100may include a container1113provided at a front end of the equipment front end module1200, and a container holder1111for supporting the container1113. The container1113serves as a vessel for accommodating the substrates S, and an enclosed front opening unified pod (FOUP) may be used to protect the substrates S from foreign substances in the air or chemical contamination.

The equipment front end module1200may include a first transfer robot1210which operates at an atmospheric pressure. The first transfer robot1210may transfer each substrate S between the container1113and the manufacturing process equipment1300.

The manufacturing process equipment1300may include a load lock chamber1310, a transfer chamber1320, and a plurality of process chambers (e.g., first to third process chambers1410,1420, and1430).

The transfer chamber1320may include a second transfer robot1321which operates in a vacuum atmosphere and rotates freely. The transfer chamber1320may transfer the substrate S among the first to third process chambers1410,1420, and1430, and transfer the substrate S between the first to third process chambers1410,1420, and1430and the load lock chamber1310. The first to third process chambers1410,1420, and1430and the load lock chamber1310may be connected to sides of the transfer chamber1320.

The load lock chamber1310may maintain a pressure by autonomously switching between a vacuum state and an atmospheric pressure in order to limit and/or prevent variations in a pressure state of the transfer chamber1320. Although not shown inFIG. 9, a buffer stage for temporarily holding the substrate S may be mounted in the load lock chamber1310. The load lock chamber1310may form a vacuum atmosphere equal to or close to that of the transfer chamber1320and receive an unprocessed substrate S from the equipment front end module1200when the second transfer robot1321of the transfer chamber1320loads or unloads the substrate S. Alternatively, the load lock chamber1310may maintain an atmospheric pressure state when a processed substrate S is transferred to the equipment front end module1200. The substrate S processed by the manufacturing process equipment1300may be transferred into the load lock chamber1310of a vacuum state by the second transfer robot1321of the transfer chamber1320. The substrate S transferred into the load lock chamber1310may be transferred into the container1113by using the first transfer robot1210.

The first to third process chambers1410,1420, and1430may perform various semiconductor processes for manufacturing a memory device, and may be provided in a plural number.

The first process chamber1410may operate at a first temperature and may perform an oxidation process for oxidizing the substrate S. The first process chamber1410may include an oxidation unit1411for performing the oxidation process, and the oxidation unit1411may perform one of oxidation processes such as plasma oxidation, radical oxidation, and/or natural oxidation. For example, the oxidation unit1411may include a plasma generating device such as magnetron for generating O2 plasma.

The first process chamber1410may be configured to perform the oxidation process described above in relation toFIG. 4Cto oxidize the first metal layer (31ofFIG. 4B). To perform the oxidation process for oxidizing the first metal layer, the first process chamber1410may form a temperature atmosphere of a first temperature (e.g., a temperature in range that is greater than or equal to 20° C. and less than 50° C.). The first temperature may be, for example, room temperature.

The first process chamber1410may include a first gas supplier (for example, see1540ofFIG. 12) for supplying a process gas into the first process chamber1410. In some embodiments, the first gas supplier may supply an oxygen gas into the first process chamber1410at a flow rate between 0.01 sccm and 10 sccm to perform the oxidation process for oxidizing the first metal layer.

The second process chamber1420may operate at a second temperature higher than the first temperature and may perform an oxidation process for oxidizing the substrate S. The second process chamber1420may include an oxidation unit1421for performing the oxidation process, and the oxidation unit1421may perform one of oxidation processes such as plasma oxidation, radical oxidation, and/or natural oxidation. For example, the oxidation unit1421may include a plasma generating device such as magnetron for generating O2 plasma.

The second process chamber1420may be configured to perform the oxidation process described above in relation toFIG. 4Eto oxidize the second metal layer (35ofFIG. 4D). That is, to perform the oxidation process for oxidizing the second metal layer35, the second process chamber1420may form a temperature atmosphere of a second temperature. The second temperature may be higher than the first temperature and may be, for example, between 50° C. and 400° C. In some embodiments, the second temperature may be between 100° C. and 200° C.

The second process chamber1420may include a heater (for example, see1520ofFIG. 12) for forming a high-temperature atmosphere in the second process chamber1420or heating the substrate S. The heater may be provided, for example, in a chuck device for supporting the substrate S.

The second process chamber1420may include a second gas supplier (for example, see1540ofFIG. 12) for supplying a process gas into the second process chamber1420. In some embodiments, the second gas supplier may supply an oxygen gas into the second process chamber1420at a flow rate between 0.1 sccm and 100 sccm to perform the oxidation process for oxidizing the second metal layer35.

The third process chamber1430may be configured to perform a deposition process for manufacturing a memory device. The third process chamber1430may deposit a metal layer on the substrate S and may perform a deposition process, e.g., a PVD process or a CVD process. The third process chamber1430may include a plurality of chambers for forming various types of material layers. In some embodiments, the third process chamber1430may include a sputtering device for performing a direct current (DC) sputtering process.

The third process chamber1430may be configured to perform, for example, the deposition process described above in relation toFIG. 4Bto deposit the first metal layer (31ofFIG. 4B) and/or the deposition process described above in relation toFIG. 4Dto deposit the second metal layer (35ofFIG. 4D). In some embodiments, when the third process chamber1430includes a sputtering device, the sputtering device may include a Mg target.

A magnetic tunnel junction layer manufacturing process using the semiconductor manufacturing apparatus1000may be performed as an in-situ process. That is, in the semiconductor manufacturing apparatus1000which maintains a vacuum atmosphere, the substrate S may be transferred among the first to third process chambers1410,1420, and1430by the transfer chamber1320.

In some embodiments, to form a tunnel barrier layer, the substrate S may be moved sequentially to the third process chamber1430, the first process chamber1410, the third process chamber1430, and the second process chamber1420by the transfer chamber1320. Based on a path of the substrate S, the deposition process for depositing the first metal layer (31ofFIG. 4B) in the third process chamber1430, the oxidation process for oxidizing the first metal layer in the first process chamber1410, the deposition process for depositing the second metal layer (35ofFIG. 4D) in the third process chamber1430, and the oxidation process for oxidizing the second metal layer35in the second process chamber1420may be performed as in-situ processes.

According to inventive concepts, the oxidation process for oxidizing the first metal layer at a relatively low temperature and the oxidation process for oxidizing the second metal layer35at a relatively high temperature may be performed in different chambers. Since the low-temperature oxidation process and the high-temperature oxidation process are performed in different chambers each maintaining a uniform temperature, dispersion between different memory devices on the substrate S due to a non-uniform temperature of an oxidation process may be reduced and/or prevented. In addition, compared to a case when the low-temperature oxidation process and the high-temperature oxidation process are performed in the same chamber, since heating and cooling processes for controlling the temperature in a chamber are not necessary, productivity of equipment may be increased.

FIG. 10is a schematic diagram of a semiconductor manufacturing apparatus1000aaccording to other embodiments of inventive concepts. Except for the configuration of a first process chamber1410a,the semiconductor manufacturing apparatus1000aillustrated inFIG. 10may have the same or similar configuration as that of the semiconductor manufacturing apparatus1000illustrated inFIG. 9. InFIG. 10, the descriptions given above in relation toFIG. 9will be omitted or briefly provided.

Referring toFIG. 10, the first process chamber1410amay operate at a first temperature and may perform a deposition process for depositing a metal layer on the substrate S and an oxidation process for oxidizing the substrate S. The first process chamber1410amay include the oxidation unit1411for performing the oxidation process and a deposition unit1413for performing the deposition process. In some embodiments, the deposition unit1413may perform a DC sputtering process.

The first process chamber1410amay be configured to perform the deposition process described above in relation toFIG. 4Bto deposit the first metal layer (31ofFIG. 4B) and the oxidation process described above in relation toFIG. 4Cto oxidize the first metal layer. That is, the deposition process for depositing the first metal layer and the oxidation process for oxidizing the first metal layer may be performed in the same chamber. Furthermore, the first process chamber1410amay be configured to perform the deposition process described above in relation toFIG. 4Dto deposit the second metal layer (35ofFIG. 4D).

In some embodiments, to form a tunnel barrier layer, the transfer chamber1320may move the substrate S sequentially to the first process chamber1410aand the second process chamber1420. Based on a path of the substrate S, the deposition process for depositing the first metal layer, the oxidation process for oxidizing the first metal layer, and the deposition process for depositing the second metal layer35in the first process chamber1410aand the oxidation process for oxidizing the second metal layer35in the second process chamber1420may be performed as in-situ processes.

FIG. 11is a schematic diagram of a semiconductor manufacturing apparatus1000baccording to other embodiments of inventive concepts. Except for the configuration of a second process chamber1420a,the semiconductor manufacturing apparatus1000billustrated inFIG. 11may have the same or similar configuration as that of the semiconductor manufacturing apparatus1000aillustrated inFIG. 10. InFIG. 11, the descriptions given above in relation toFIG. 10will be omitted or briefly provided.

Referring toFIG. 11, the second process chamber1420amay operate at a second temperature and may perform a deposition process for depositing a metal layer on the substrate S and an oxidation process for oxidizing the substrate S. The second process chamber1420amay include an oxidation unit1421for performing the oxidation process and a deposition unit1423for performing the deposition process. In some embodiments, the deposition unit1423may perform a DC sputtering process.

The second process chamber1420amay be configured to perform the deposition process described above in relation toFIG. 4Dto deposit the second metal layer (35ofFIG. 4D) and the oxidation process described above in relation toFIG. 4Eto oxidize the second metal layer35. That is, the deposition process for depositing the second metal layer35and the oxidation process for oxidizing the second metal layer35may be performed in the same chamber.

Since each of the first and second process chambers1410aand1420ais configured to perform a deposition process and an oxidation process, a footprint of the semiconductor manufacturing apparatus1000may be reduced.

In some embodiments, to form a tunnel barrier layer, the transfer chamber1320may move the substrate S sequentially to the first process chamber1410aand the second process chamber1420a.Based on a path of the substrate S, the deposition process for depositing the first metal layer (31ofFIG. 4B) and the oxidation process for oxidizing the first metal layer in the first process chamber1410aand the deposition process for depositing the second metal layer35and the oxidation process for oxidizing the second metal layer35in the second process chamber1420amay be performed as in-situ processes.

In some embodiments, as described above in relation toFIGS. 5A and 5B, the first process chamber1410amay form a first interlayer by repeatedly performing a metal layer deposition process and a metal layer oxidation process at least two times.

In some embodiments, as described above in relation toFIGS. 6A and 6B, the second process chamber1420amay form a second interlayer by repeatedly performing a metal layer deposition process and a metal layer oxidation process at least two times.

FIG. 12is a cross-sectional view of a process chamber1500of a semiconductor manufacturing apparatus, according to some embodiments of inventive concepts.

Referring toFIG. 12, the process chamber1500may include a processing vessel1501, a substrate holder1510, a heater1520, a metal target1530, and a gas supplier1540. The process chamber1500may be the first process chamber1410or1410adescribed above in relation toFIGS. 9 to 11, or the second process chamber1420or1420adescribed above in relation toFIGS. 9 to 11.

The processing vessel1501may provide a processing space therein, and a gate1503through which the substrate S to be processed enters may be provided in a side wall of the processing vessel1501.

The substrate holder1510may be provided in the processing space and may support the substrate S. The substrate holder1510may include a base1511and a chuck1513provided on the base1511to support the substrate S. The chuck1513may be configured as an electrostatic chuck for adsorbing the substrate S thereon by using electrostatic force.

The substrate holder1510may be configured to be rotated or lifted in connection with a driving mechanism1515. The driving mechanism1515may include a driving shaft1517and a driving motor1519connected to an end of the driving shaft1517to generate driving force for rotating or lifting the driving shaft1517.

The heater1520may be provided in the processing space and may heat the substrate S. The heater1520may be provided in the substrate holder1510. The heater1520may be configured to heat the substrate S based on, for example, lamp radiation, Joule resistance heating, induction heating, or microwave heating. For example, the heater1520may include an electric circuit for resistive heating. For example, the heater1520may be configured to heat the substrate S in the oxidation process described above in relation toFIG. 4Eto oxidize the second metal layer (35ofFIG. 4D). The heater1520may be omitted in some cases, for example, when the substrate S is processed at room temperature as in the first process chamber1410aillustrated inFIG. 11.

The metal target1530may be provided above the substrate holder1510. The metal target1530may be selected based on a metal layer to be deposited. For example, the metal target1530may be used to form a tunnel barrier layer of a magnetic tunnel junction layer and may include, for example, a Mg target. The number of metal targets1530is not limited to two and one or more metal targets1530may be provided.

The metal target1530may be electrically connected to a target electrode1531. A power supply1533may be connected to the target electrode1531and may be a direct current (DC) power supply. A magnet1535capable of generating a magnetic field may be provided at a side of the target electrode1531opposite to the metal target1530, and may be connected to a magnet driver1537.

The gas supplier1540may supply a gas into the processing vessel1501through an inlet port1505provided on the processing vessel1501. The gas supplier1540may include a gas source1541and a flow rate controller1543such as a mass flow controller. The gas of the gas source1541may be supplied through the flow rate controller1543to the inlet port1505.

In some embodiments, the gas supplier1540may supply a certain gas into the processing vessel1501to perform a sputtering process. The gas supplier1540may supply a gas, e.g., an inert gas, which may be excited in the processing vessel1501during the sputtering process. When the gas is supplied into the processing vessel1501by the gas supplier1540and a voltage is applied to the metal target1530by the power supply1533, the gas supplied into the processing vessel1501may be excited. In addition, when the magnet1535is driven by the magnet driver1537, a magnetic field may be generated around the metal target1530and thus plasma may be concentrated near the metal target1530. As cations in plasma collide with the metal target1530, a material of the metal target1530may be released. The metal target1530and/or the material released from the metal target1530may be deposited on the substrate S.

In some embodiments, the gas supplier1540may supply a certain gas into the processing vessel1501to perform an oxidation process. The gas supplier1540may supply an oxygen gas and an inert gas for controlling a pressure of the oxidation process, into the processing vessel1501.

Although not illustrated, each of the semiconductor manufacturing apparatuses1000,1000a,and/or1000bmay further include a controller and a memory connected through a bus. The memory may be a nonvolatile memory, such as a flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferro-electric RAM (FRAM), or a volatile memory, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM). The controller may be, a central processing unit (CPU), a processor, an application-specific integrated circuit (ASIC), or another suitable hardware processing unit, that when, executing instructions stored in the memory, configures the controller as a special purpose controller for controlling the semiconductor manufacturing apparatuses1000,1000a,and/or1000band process chamber1500to perform one or more of the above-described magnetic tunnel junction layer manufacturing processes described above in relation to the semiconductor manufacturing apparatuses1000,1000a,and/or1000band the process chamber1500inFIG. 12.