Switching regulator with advanced slope compensation

A switching regulator circuit with improved slope compensation for providing a regulated voltage to a load. The regulator circuit includes a power source and a switch circuit configured to control the coupling of the power source to the load. The operation of the switch circuit is controlled by a control signal generated by a control circuit. A feedback circuit is provided for generating a feedback signal indicative of the regulated voltage provided by the switching regulator circuit to the load. A circuit is provided to generate a sensed signal indicative of the current supplied by the power source. The regulator circuit further includes a timing signal generator for generating a timing signal, a ramp signal generator for generating a ramp signal, and a current source controlled by the ramp signal for generating a compensation signal indicative of the ramp signal. The control circuit generates the control signal based on the compensation signal, the timing signal, the sensed signal and the feedback signal.

FIELD OF DISCLOSURE

This disclosure generally relates to improved switching regulator circuits, and more specifically, to methods and circuits to effectively implement slope compensation in switching regulator circuits with reduced cost and design complexity.

BACKGROUND OF THE DISCLOSURE

A voltage regulator provides a predetermined and substantially constant output voltage to a load from a voltage source that may be poorly-specified or fluctuating. One type of commonly used regulator is a switching regulator, which supplies a flow of current from a voltage source to a load in the form of discrete current pulses. To create the discrete current pulses, switching regulators usually employ a switch, such as a power transistor, to control the current supply. The current pulses are then converted into a steady load current with an inductive storage element. By controlling the duty cycle of this switch, i.e., the percentage of time that the switch is ON relative to the total period of the switching cycle, the switching regulator can regulate the load voltage.

In current-mode switching voltage regulators, i.e., a switching regulator that is controlled by a current-derived signal in the regulator, there is an inherent instability when the duty cycle exceeds 50% with fixed frequency and continuous current mode, and 67% with fixed frequency and discontinuous current mode (i.e., when the switch is ON for more than 50% or 67% of a given switching period). In order to maintain stability of such current-mode switching regulators, the current-derived signal used to control the regulator is adjusted by, for example, applying a slope compensation signal.

One method of producing such a slope compensation signal is to use a portion of an oscillator signal as the compensation signal. The oscillator signal may be, for example, a ramp signal that is used to generate a clock signal that controls the switching of the regulator. The slope compensation signal can be applied by either adding the ramp signal to the current-derived signal, or by subtracting it from a control signal.

FIG. 1shows an example of a current-mode switching regulator100utilizing slope compensation. Voltage regulator100generally comprises an output circuit110and a control circuit130. A switch timing circuit112that is capable of producing substantially in-phase ramp and clock signals supplies a control signal SW ON that sets a latch114. While latch114is set, it provides a signal to output circuit110that causes a switch108to turn ON and provide current from an input voltage source VIN to an output node109. Latch114remains set until an output signal from a current comparator122causes latch114to reset. When reset, latch114turns switch108OFF so that current is no longer drawn from VIN. Current comparator122determines when to reset latch114by comparing a signal that is indicative of the current supplied to output circuit110with a signal representing a current threshold value, i.e., a voltage across resistor128, generated by an error amplifier124and a slope compensation signal ISC.

The primary purpose of output circuit110is to provide current pulses as directed by control circuit130, and to convert those current pulses into a substantially constant output current. Output circuit110includes power switch108coupled to VIN(through a sensing resistor132) and a node107, a catch diode102coupled from node107to ground, an inductor104coupled from node107to output node109, and a capacitor106coupled from output node109to ground. Although switching element108is depicted as a bipolar junction transistor (BJT), any other suitable switching element may be used if desired.

The operation of output circuit110can be divided into two periods. The first is when power switch108is ON, and the second is when power switch108is OFF. During the ON period, current passes from VINthrough switch108and flows through inductor104to output node109. During this period, catch diode102is reverse-biased. After power switch108turns OFF, however, inductor104still has current flowing through it. The former current path from VINthrough switch108is now open-circuited, causing the voltage at node107to drop such that catch diode102becomes forward-biased and starts to conduct. This maintains a closed current loop through the load. When power switch108turns ON again, the voltage at node107rises such that catch diode102becomes reverse-biased and again turns OFF.

As shown inFIG. 1, error amplifier124senses the output voltage of regulator100via a feedback signal VFB. Error amplifier124, which is preferably a transconductance amplifier, compares VFBwith a reference voltage116(VREF) that is also connected to amplifier124. A control signal, VC, is generated in response to this comparison. The VCcontrol signal is filtered by a capacitor127and coupled to the emitter of PNP transistor118and the base of NPN transistor126. The VCsignal controls transistor126. When the value of VCis large enough to turn transistor126ON, current flows through resistor128and a voltage across resistor128is developed. Generally speaking, the value of this voltage is dependent on VC. As VCincreases, so does the voltage across resistor128and vice versa.

The value of the voltage across resistor128establishes the threshold point at which current comparator122trips. Therefore, as the voltage across resistor128increases, the current threshold at which switch108turns off also increases to maintain a substantially constant output voltage. However, as mentioned above, current-mode voltage regulators can become unstable when the duty cycle exceeds 50% with fixed frequency and continuous current mode. To prevent this instability, a duty cycle proportional slope compensation signal may be subtracted from the feedback signal, i.e., the voltage across resistor128, to increase the rate of current rise perceived by comparator122. This is accomplished inFIG. 1by applying the ramp signal from switch timing circuit112to a node between the emitter of transistor126and a resistor125(through a circuit generally depicted as controlled current source113). As the ramp signal progresses toward its peak, the current injected at the emitter of transistor126increases, reducing its collector current, which causes the voltage across resistor128to decrease. Current comparator122interprets this as an increase in the rate of current rise in inductor104. This causes the perceived rate of current rise in inductor104to be greater than the rate of current fall, which allows regulator100to operate at duty cycles greater than 50% without the duty cycle becoming unstable.

To prevent damage to switch108, the maximum operating current of regulator100is limited to a certain level by placing a voltage clamp on the VCsignal. Such a voltage clamp is typically implemented as shown inFIG. 1using a PNP transistor118and a fixed voltage source120. As long as the value of VCremains within a permissible operating range, voltage source120keeps the emitter-base junction of transistor118reverse-biased so that it acts as an open circuit. However, when VCattempts to rise above a preset maximum value, transistor118turns ON and starts to conduct. This diverts excess current away from the loop filter so that the voltage VCalways remains at or below the preset maximum.

One undesirable consequence of slope compensation is that the true maximum current that can pass through switch108decreases proportionally as the duty cycle increases. This is because as the duty cycle increases, the effective magnitude of the slope compensation signal (ISC) also increases, causing a significant decrease in voltage across resistor128during the latter ON portion of the duty cycle. This phenomenon is of concern to circuit designers because it prevents the full current supplying capabilities of regulator100from being utilized at higher duty cycles.

One way to correct this problem is to let VCrise above the maximum level imposed by the voltage clamp when slope compensation is used. This allows the maximum value of voltage across resistor132to remain substantially constant rather than decrease as the amount of slope compensation increases. Merely increasing the clamp voltage directly (e.g., by increasing the value of voltage source120with a signal varying at the compensation ramp rate) is not a viable solution because the large time constant of capacitor127will not allow the peak value of VCto respond to a changing clamp threshold fast enough. Moreover, simply adding the compensation voltage directly to VCnulls the effect of slope compensation.

An alternative approach to maintain the same value of maximum current that can pass through switch108is to dynamically adjust the value of the limiter so that the effective maximum value of the supplied current to the inductor remains the same as when no compensating ramp is used, but the voltage Vc on the filter127is not changed at the clock rate. An exemplary circuit that dynamically adjusts the value of the limiter is shown inFIG. 2. Similar to the circuit ofFIG. 1, the regulator ofFIG. 2includes output circuit110, switch timing circuit112, latch114, reference voltage116, comparator122, error amplifier124, resistors125,128,132, transistor126, and capacitor127. InFIG. 2, regulator200has been modified by adding buffer circuit140, adjustable voltage clamp circuit150, and slope compensation circuit160. With the addition of buffer140, the VCclamp threshold can be adjusted by the slope compensation signal without changing the instantaneous value of Vc so that a substantially constant maximum current limit can be maintained at greater duty cycles. Detailed discussions of regulators with adjustable clamp circuit can be found in, for example, U.S. Pat. No. 6,498,466, titled “CANCELLATION OF SLOPE COMPENSATION EFFECT ON CURRENT LIMIT.”

However, the additional components, such as the buffer circuit140and the adjustable voltage clamp circuit150, that are needed to implement an adjustable limiter voltage as shown inFIG. 2increase cost and design complexity. Furthermore, the use of two compensation currents, ISC1and ISC2in the circuit shown inFIG. 2also add design complexity. The additional circuits needed in the circuit210shown inFIG. 2also increase the die size of the part, which is undesirable in integrated circuit or semiconductor component designs. Moreover, the use of additional components, especially active components such as amplifiers, would increase consumption of power. Therefore, there is a need for a simpler circuit design for switching regulators with effective slope compensation.

SUMMARY OF THE DISCLOSURE

This disclosure presents improved switching regulators having simplified circuit design that provides slope compensation without changing the maximum current passing through a switch that controls the supply of power from a power source to a load.

An exemplary switching regulator circuit according to this disclosure provides a regulated voltage to a load. The regulator circuit comprises a power source and a switch circuit configured to control the supply of power from the power source to the load. A feedback circuit is provided for generating a feedback signal indicative of the regulated output voltage provided by the switching regulator circuit. The regulator circuit further includes a timing signal generator for generating a timing signal, a ramp signal generator for generating a ramp signal, and a current source controlled by the ramp signal, such as a current-controlled current source or a voltage-controlled current source, for generating a compensation signal indicative of the ramp signal. A sense signal circuit is also provided for generating a sensed signal indicative of the current supplied by the power source. A control circuit, coupled to the feedback circuit, the timing signal generator, the sensed signal circuit, the switch circuit and the current source, is provided to generate a control signal to control the operation of the switch circuit. The control circuit generates the control signal based on the timing signal, the compensation signal, the sensed signal and the feedback signal. The ramp signal is synchronized to the timing signal, such as a pulse clock signal.

In one embodiment, the compensation signal is subtracted from a signal varying with the difference between the feedback signal and a reference signal. The reference signal may be provided by a reference voltage source. For example, an error amplifier may be provided to compare the feedback signal with the reference signal. The resulting signal is passed through an amplifier with a reference voltage source, to generate an output signal proportional to the difference between the resulting signal and the reference voltage. The output signal is then passed through a limit circuit. A comparator is provided to compare the output of the limit circuit and a sensed signal indicative of the current passing to the load. The output of the comparator controls the operation of the latch. If the sensed signal is larger than the limit circuit output signal, the latch generates a control signal to control the switch circuit to stop supplying power from the power source to the load.

In one embodiment, an exemplary switching regulator circuit according to this disclosure includes a circuit to perform loop filtering and to couple the compensation signal to the output of the error amplifier which generates the signal varying with the difference between the feedback signal and the reference signal. The circuit may be implemented as a capacitor and a resistor connected in series. One end of the capacitor is coupled to the output of the error amplifier, and the other end of the capacitor is coupled to the resistor, which in turn couples to a DC voltage source referenced to the ground. The output of the current source controlled by the ramp signal is coupled to the resistor, such that the output voltage of the error amplifier is modified by the compensation signal provided by the current source without changing the voltage across the loop filter capacitor, and no further amplifier is needed.

Still other advantages of the presently disclosed methods and systems will become readily apparent from the following detailed description, simply by way of illustration of the invention and not limitation. As will be realized, the capacity planning method and system are capable of other and different embodiments, and their several details are capable of modifications in various obvious respects, all without departing from the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

DETAILED DESCRIPTIONS OF ILLUSTRATIVE EMBODIMENTS

FIG. 3depicts an exemplary block diagram of an exemplary switching regulator300with improved slope compensation according to this disclosure. Switching regulator300provides a predetermined and substantially constant output voltage to a load32from a voltage source30. Switching regulator300includes a control circuit50that generates a control signal22to control the operation of a switch circuit25, which in turn controls the coupling of load32to voltage source30or ground. Control signal22is slope-compensated to maintain operation stability of the duty cycle of switching regulator300. Switch circuit25may be implemented by using bipolar junction transistor (BJT) or any other suitable switching element known to people skilled in the art. A timing signal generator1, such as a clock generator, is provided to generate a clock signal20and a ramp signal3. Ramp signal3is synchronized to clock signal2. Current source35is controlled by ramp signal3to generate a compensation signal6that is indicative of the ramp signal3. The compensation signal is applied to control circuit50for providing slope compensation to maintain stability of switching regulator300(discussed in more detail below). Current source35may be implemented as a current-controlled current source or a voltage-controlled current source controlled by ramp signal3. The regulator300further includes a feedback loop to provide a feedback signal28to control circuit50. Feedback signal28is indicative of the regulated voltage provided by switching regulator300to load32. Regulator300further includes a sensed signal circuit coupled to control circuit50, for generating a sensed signal indicative of the current supplied by voltage source30. The sensed circuit may be implemented simply by providing a signal line to couple the current supplied by voltage source30to control circuit50. Control circuit50generates control signal22based on sensed signal16, compensation signal6, feedback signal28and clock signal20.

FIG. 4is a detailed circuit diagram of the exemplary switching regulator300shown inFIG. 3. Switch circuit25is implemented, for example, using a SPDT (Single Pole, Double Throw) switch. The operation of the switching regulator300is controlled by control signal22, and can be divided into two periods. The first period is when the upper contact of switch circuit25is ON and the lower contact is OFF; and the second period is when the upper contact of switch circuit25is OFF and the lower contact is ON. As shown inFIG. 4, control circuit50uses a latch21to generate control signal22to control the operation of switch circuit25as described above. A clock signal20is connected to the “set” input of latch21. A falling edge of clock signal20sets latch21, which in turn sets control signal22to logical “H”. Control signal22, when at logical “H”, controls switch circuit25to turn ON the upper contact of switch circuit25, and turn OFF the lower contact. As discussed earlier, this causes supply current24to flow from voltage source30through the upper contact of switch circuit25and inductor26to load32. On the other hand, when control signal22is at logical “L”, it controls switch circuit25to turn OFF the upper contact and turn ON the lower contact, which creates a closed current loop from ground through inductor26and load32. The use of SPDT switch and specific logical operation modes described herein are for illustration purposes only. Other types or variations of switches and logical states well-known to people skilled in the art can be used to implement the features described herein.

Regulator output voltage at load32is sensed by a feedback loop that generates a feedback signal28feeding to an error amplifier10. The output terminal of error amplifier10is coupled to an R-C filter comprising capacitor Cc and resistor Rc. Resistor Rc couples to ground via a DC voltage source Vterm. Error amplifier10may be implemented using a transconductance amplifier or other types of amplifiers known to people skilled in the art. Error amplifier10compares feedback signal28with a reference signal, such as a reference voltage provided by a fixed reference voltage42, and generates an output current proportional to the voltage difference between the feedback signal28and fixed reference voltage42.

As previously illustrated inFIG. 3, a current source35is controlled by ramp signal3, and is provided to generate a compensation signal6indicative of ramp signal3. Current source35may be implemented as a current-controlled current source or a voltage-controlled current source. For instance, a current-controlled current source is a device in which the output current mirrors or reflects the input current. The input current is supplied by a source and the output current is generated by a sink, or vice-versa, the input current is supplied by a sink and the output current is generated by a source. An example of a current-controlled current source is a current mirror shown as element35inFIG. 4. A current mirror may be implemented with either bipolar or field effect transistors. The simplest form of a current mirror may be implemented with an input device connected as a diode and a matched (but possibly area ratioed) output device connected to it so that the input device has the same control voltage (Vbase-emitteror Vgate-source) as the output device. As shown inFIG. 4, current-controlled current source35is connected to the R-C filter at a node between capacitor Cc and Resistor Rc. According to another embodiment, the output of current-controlled current source35is applied to Resistor Rc.

As discussed earlier, the R-C filter connects to ground via a DC voltage source Vterm, instead of connecting to ground directly. The connection to DC voltage source Vterm raises the voltage appearing at the node between capacitor Cc and resistor Rc. The DC value of VTERMis blocked from output signal11by loop filter capacitor Cc. It is noted that the voltage at the output of the R-C loop filter can be dynamically changed with a grounded current sink such as the compensation ramp without changing the charge on capacitor Cc and without the need of a negative power supply.

In operation, ramp signal3is applied through current-controlled current source35to generate a compensation signal6, which is a sink current that reflects ramp signal3, to the node between capacitor Cc and resistor Rc of the loop filter. Compensation signal6creates a compensation voltage proportional to the product of compensation signal6times the value of resistor Rc, which is effectively subtracted from the output voltage of error amplifier10to create an output signal11. Since compensation signal6reflects ramp signal3, the subtraction of the compensation voltage from the output of error amplifier10implements slope compensation as known in the art. Output signal11is then applied to an amplifier13. Amplifier13generates an output current signal14proportional to the voltage difference between output signal11and the voltage of a reference voltage source Vref2. Output signal14is applied to a limit circuit18to generate an output voltage signal15. An example of limit circuit18may comprise a resistor and parallel zener diode connected between node voltage15and ground (or similar clamp circuit known in the art).

As shown inFIG. 4, switching regulator300further includes a comparator17having a “+” input and a “−” input, and an output signal19coupled to the reset input of latch21. A sensed signal16and limit output signal15are applied to the “−” input and “+” input of comparator17, respectively. Sensed signal16is a signal changing with, or indicative of, supply current24supplied by voltage source30. For example, a sensed signal may be a voltage proportional to supply current24generated by using a suitable sense resistor and level shifter or other means known to the art. As supply current24increases with time, sensed signal16also increases. When the voltage of sensed signal16exceeds that of output signal15, comparator17generates an output signal19that changes from logical “H” to logical “L”, which resets latch21and changes control signal22from logical “H” to logical “L”. The state change of control signal22from logical “H” to logical “L” opens the top contact and closes the bottom contact of switch circuit25. In response, current flows from ground through the bottom contact of switch circuit25and inductor26to load32. Since the voltage at node9is greater than the zero voltage of ground, the current in inductor26decreases until the time of the next clock pulse falling edge of clock signal20, which sets latch21and repeats the next cycle.

The slope compensation implemented according to this disclosure has several advantages over prior art implementations such as that shown inFIG. 2. For instance, the slope compensation described herein does not require additional buffer device140, adjustable voltage clamp circuit150, or a second compensation current, as required in the circuit shown inFIG. 2. The limit circuit18, together with comparator17and latch21, prevent supply current24from exceeding a preset value unaffected by the presence or absence of the stabilizing ramp signal3. Also note that ramp signal3is pulled to ground through a transistor7after latch21has been reset and the level of signal23becomes logical “H”. Pulling ramp signal3to ground when latch21is reset does not change function. Rather, it reduces the dynamic range required to output signal11. A switching regulator according to this disclosure provides slope compensation by obtaining ramp signal3having waveform2, from clock signal20having waveform4, which has a level of zero for the first approximately 45% for the clock cycle and then rises until the end of the cycle at the falling edge of waveform4. As a result, the incremental gain from node voltage9to current signal24is reduced. Thus, instability of switching regulator300is prevented.

FIG. 5shows a modified circuit configuration that can be used to replace amplifier13, limit circuit18and comparator17as shown inFIG. 4. InFIG. 5, a second comparator30and an OR gate31are added. In this configuration, output signal11directly feeds to the “+” input of comparator17, and sensed signal16is fed to the “−” inputs of comparator17and comparator30. The respective output of comparator17and comparator30are coupled to the input of OR gate31, which in turn generates an output signal19′ that connects to the reset input of latch22. The performance of the circuit shown inFIG. 5is identical to that described inFIG. 4, but amplifier13and the resistor and clamp diode of limit circuit18are eliminated.

If the switching regulator is implemented as an integrated circuit and the R-C loop filter is located external to the integrated circuit, the switching regulator may be implemented using another modified circuit configuration as shown inFIG. 6, at the cost of an added circuit90including a buffer amplifier40and resistor R1. An I/O pin is provided to couple to the output of error amplifier10to an R-C loop filter (Ccx and Rcx) outside the integrated circuit. Components and constituents of the circuit shown inFIG. 6are identical to those of the circuit shown inFIG. 4, except for the added circuit90. If the value of resistor R1is identical to that of the resistor Rc shown inFIG. 4, then the output signal11′ inFIG. 6would be the same as the output signal11inFIG. 4.

It is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. It is also to be understood that the following claims are intended to cover all generic and specific features herein described and all statements of the scope of the various inventive concepts which, as a matter of language, might be said to fall there-between.