Programmable stitch chaining of die-level interconnects for reliability testing

A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.

BACKGROUND

Field of the Disclosure

The present disclosure relates generally to integrated circuit (IC) packaging and, more particularly, to IC package testing.

Description of the Related Art

Integrated circuit (IC) devices are modeled and tested throughout the fabrication process in order to assure that the components of the IC device are meeting both industry standards and customer requirements. While it is common in the industry to test and gather board level reliability (BLR) test net data for ball grid array (BGA) interconnects and other board-level interconnects using production parts, BLR data for die-level interconnect test nets conventionally has been difficult to obtain on production parts, and thus manufacturers typically have to resort to the design and fabrication of a function specific IC test vehicle and component package to enable daisy chain testing of the die-level interconnects of the IC package design. Designing a special test vehicle chip solely for die-level daisy chain testing can be impractical in view of the expense and resources involved, but the lack of this test data can place the manufacturer at a disadvantage relative to its competitors.

DETAILED DESCRIPTION

FIGS. 1-6illustrate embodiments of an integrated circuit (IC) device implementing a die that is designed and fabricated to operate in either a production mode or a test mode. When in production mode, the IC device operates according to its production design and function (that is, for use in a non-test environment). When in test mode, the die reconfigures the connections between certain die pads so as to form pad-to-pad links that, in conjunction with links formed between pads on the substrate on which the die is disposed, form a stitch chain that routes back and forth between the die and substrate through the die-substrate interconnects, and thus facilitates board level reliability (BLR) testing of the die-level interconnects of the IC device.

Accordingly, rather than requiring the design and fabrication of a separate test vehicle die, the techniques described herein provide an ability to convert a distributable, or saleable, production die to a test die. This feature can be designed into each production die design, and one or more of the production-run die therefore may be selected and repurposed as test dies for use in test IC devices by reprogramming the production-run die from the production mode to the test mode.

In at least one embodiment, the programmability of the die for the default production and optional test modes is achieved through the use of fuse elements that, when in the production mode, selectively couple certain die pads to their respective power or signal busses and decouple certain die pads from each other, and when in the test mode, decouple certain die pads from their respective power or signal busses and couple certain die pads together to form links in a corresponding stitch chain that is then formed between the die and the substrate through the corresponding die-substrate interconnects. Depending on the state of the connection between pads or between pad and power bus in the corresponding mode formed by each fuse element, the fuse element may be operate as a fuse (fabricated as conductive but can be programmed to be non-conductive) or as an anti-fuse (fabricated as non-conductive but can be programmed to be conductive). The fuse elements can be implemented as sacrificial fuses and anti-fuses (e.g., metal or polysilicon strips), as electronic fuses (e-fuses) and anti-electronic fuses (anti-e-fuses), or combinations thereof. The programming of the fuse elements can be performed by a variety of techniques. For example, sacrificial fuses are programmed to be non-conductive by “blowing” the sacrificial fuse element by the use of over-current or the use of laser trimming while electronic fuses are programmed to be conductive or non-conductive by the use of a programming signal. For ease of reference, the term “anti-fuse” refers to either a sacrificial anti-fuse or an anti-e-fuse unless otherwise noted, and the term “fuse” refers to either a sacrificial fuse or an e-fuse, unless otherwise noted.

To reduce the complexity of forming the stitch chain, in at least one embodiment the test mode feature involves only the use of pads connected to power busses or are otherwise used for conducting power rather than signaling. For ease of illustration, various example implementations are described below in the context of pads connected to power busses. However, these techniques are not limited to this context, and in some embodiments the techniques described herein may be used for pads connected to signal busses or otherwise connected signal I/O, or for a combination of signal bus pads and power bus pads.

Circumstances of the IC to package assembly process often render the die-level interconnects at the periphery of a die the least reliable die-level interconnects in an IC device or package. In at least some embodiments, the implementation of the stitch chain for testing purposes is focused on the power pads at the periphery of the die, specifically at the corners of the die. To illustrate, one stitch chain may be designed to incorporate the power pads formed at one corner of the die, while another stitch chain may be designed to incorporate the power pads formed at the opposite corner of the die. Alternatively, a stitch chain may involve power pads disposed along one or more edges of the die. Further, as the involved die pads are at the periphery of the die, in some embodiments, some or all of the fuse elements used to enable the test mode programmability may be disposed in corner regions or other keep-out zones (i.e., those areas of the die in which the circuit layout design otherwise is prevented from using due to constraints related to singulation, thermal management, mounting, etc.) at the periphery of the die and in which circuitry typically is not formed due to reliability concerns on the part of the fabrication plant. By using a keep-out zone of the die for fabricating the fuse elements used to implement this programmability, the programmability circuitry can use floorplan space on the die that otherwise would go unused. The programmability circuitry therefore can be implemented in a manner that does not substantially displace other circuitry in the floorplan of the die, and thus does not impact the die size appreciably.

FIG. 1illustrates a cross-sectional view of an integrated circuit (IC) device100configurable into either a production mode for distribution purposes, such as sale, or other use for its designed purposes, or a test mode for use in die-level interconnect and other BLR testing in accordance with some embodiments. The IC device100comprises a die102disposed on a substrate104in a flip-chip, or controlled collapse chip connection (C4), configuration, whereby die-level interconnects105are formed between the die102and the substrate104. Each die-level interconnect105comprises a die pad106disposed at a top metal layer110of the die102, a substrate pad107disposed at a top metal layer111of the substrate104, and a solder bump108(also commonly referred to as a C4bump) electrically and mechanically coupling the pads106and107together. The substrate104, in turn, is connected to a printed circuit board (PCB)112via board-level interconnects114. Each board-level interconnect114comprises a substrate pad115disposed at a surface117of the substrate104opposite the top metal layer111, a PCB pad116disposed at a surface118of the PCB112, and a solder ball120or other package-level pin electrically and mechanically coupling the pads115and116together. Note that while the embodiments detailed herein are described with respect to a flip-chip configuration, the following techniques can be implemented utilizing wirebond technology or other interconnect methods.

The die102implements fuse elements that permit the die102to be configured according to a production mode or a test mode. In the production mode, the fuse elements are configured such that the die pads106are connected to respective power busses or signaling busses/interconnects per the intended saleable production design of the die102. In the test mode, the fuse elements are reconfigured such that certain die pads106are reconnected in pairs so as to form corresponding links in a daisy chain, and a test version of the substrate104is implemented such that certain substrate pads107are connected in pairs so as to form corresponding intervening links in the daisy chain, such that when the die102(programmed for the test mode) and the test version of the substrate104are connected, an electrically-continuous daisy chain is formed in the IC device100such that the daisy chain stitches between the links in die pads106and links in substrate pads107via the die-level interconnects105.

To illustrate, the cross-section view ofFIG. 1depicts an example configuration whereby the die102is programmed for this test mode and mounted on a test version of the substrate104. A stitch chain130is formed that may be used during board level testing to test the reliability of the die-level interconnects105. Reliability testing can include monitoring for changes in resistance across the stitch chain130as the test IC device100is repeatedly heated and cooled. In the depicted example, the stitch chain130routes through metal layers of the PCB112into the substrate104via a board-level interconnect132(an instance of the board-level interconnect114), and then stitches multiple times between the die102and the substrate104via die-level interconnects134,136,138, and140(instances of the die-level interconnects105). The stitch chain130then routes back to the PCB112from the substrate104via board-level interconnect142(another instance of the board-level interconnect114). For ease of illustration, the interconnects involved in this stitch chain130are in the same plane as that represented by the cross-section view ofFIG. 1. However, as described in greater detail below, the interconnects involved in a stitch chain often are clustered in the corners of the die or otherwise clustered along the periphery of the die.

This test configuration of the die102for forming part of the stitch chain130is achieved through the use of fuse elements formed at one or more layers of the die102. The fuse elements may be implemented as sacrificial fuses or sacrificial anti-fuses, as e-fuses or anti-e-fuses, or combinations thereof, depending on the connection to be formed by the particular fuse element during test mode and during production mode. To illustrate, programming the die102for test mode causes anti-fuses152and154to be rendered conductive, and fuse156to be rendered non-conductive. With anti-fuse152rendered conductive, the die pad106of the die-level interconnect134is electrically connected to the die-pad106of the die-level interconnect136, and thus the illustrated link162in the stitch chain130is formed. With anti-fuse154rendered conductive, the die pad106of the die-level interconnect138is electrically connected to the die-pad106of the die-level interconnect140, and thus the illustrated link164in the stitch chain130is formed. With fuse156rendered non-conductive, a conductive link is severed between the die pads106of the die-level interconnects136and138, thereby permitting the implementation of the illustrated link166of the stitch chain130between the pads107of the die-level interconnects136and138in the substrate104. Fuse elements, such as fuse element168, also may be implemented in the substrate104to permit the substrate104to be programmed for test mode in the same manner.

FIGS. 2-4together illustrate the process of reconfiguring a die from the production mode to the test mode using sacrificial fuse elements in accordance with some embodiments.FIG. 2depicts a top view of a die202(corresponding to the die102,FIG. 1) programmed for the production mode. The top metal layer of the die202implements die pads201and206that are coupled to respective VDD power buses226and234via a plurality of fuses208and212, as well as die pad204that is coupled to VDD power bus230through conventional metal wiring in the die not requiring the use of a fuse element. As die pads201,204, and206are connected to the VDD power busses226,230, and234in this mode, the die pads201,204, and206also are referred to herein as “power pads”201,204, and206. The top metal layer of the die202further implements die pads214and216that are coupled to respective VSS power busses228and232by a plurality of fuses218and220. As die pads214and216are connected to the VSS power busses228and232in this mode, the die pads214and216also are referred to herein as “ground pads”214and216. The die202further implements anti-fuse222connected between power pad201and ground pad214and anti-fuse224connected between power pad206and ground pad216. The top metal layer202is generally reserved for die pads with the VDD and VSS power busses being implemented in the metal layers of the die.

In the mode illustrated inFIG. 2, the fuses208,212,218, and220are “unprogrammed” and thus conductive, and thereby couple the die pads202,206,214, and216to their respective power busses. Further, the anti-fuses222and224are likewise “unprogrammed,” and thus non-conductive, thereby preventing connectivity between the power pad201and the ground pad214and preventing connectivity between the power pad206and the ground pad216.

Turning toFIG. 3, a top-view of the die202during the process of programming the die202to enter the test mode is illustrated. As the fuse elements of this example are sacrificial fuses and sacrificial anti-fuses, their programming is achieved by applying a current to the fuse element via probe pins applied to the corresponding pads connected to the fuse element. Thus, application of a threshold voltage to the power pad201via probe pin238“programs” the fuse208so as to render the fuse208non-conductive, thereby electrically isolating the power pad201from the VDD bus226. Likewise, application of a threshold voltage to the ground pad214via probe pin240“programs” the fuse218so as to render the fuse218non-conductive, thereby electrically isolating the ground pad214from the VSS bus228. Further, a voltage differential between the power pad201and the ground pad214caused by the probe pins238and240“programs” the anti-fuse222so as to render the anti-fuse222conductive, thereby electrically connecting the power pad201and the ground pad214. Similarly, applications of voltages to the power pad206and the ground pad216via probe pins242and244, respectively, “programs” fuses212and220and anti-fuse224, which in turn electrically isolates power pad206and ground pad216from VDD power bus234and VSS power bus232, respectively, while electrically connecting power pad206and ground pad216. Alternatively, laser trimming can be used to ablate the metal or polysilicon material of the fuses so as to create an electrical discontinuity and thus program these fuses. The timing of the “programming” can be either staggered or simultaneous. Power pad204, not being coupled to a fuse element, remains coupled to VDD power bus230after programming of the surrounding die pads. Power pad204remains linked to the remainder of pads located on the die that are not electrically isolated for testing purposes.

FIG. 4illustrates, via a top view of the die202, a stitch chain, or daisy chain,400formed in die202after it has been programmed for the test mode (as shown inFIG. 3) and bonded to a test substrate, such as the substrate104ofFIG. 1. A substrate-level link402of the stitch chain400is created by a conductive path formed through a PCB and the test substrate, and through a die-level interconnect (for example, a solder bump) incorporating the pad201and the corresponding pad in the substrate. The substrate-level link402is followed in the stitch chain400by a die-level link404formed between the power pad201and the ground pad214via the programmed anti-fuse222. The die-level link404is followed in the stitch chain400by a substrate-level link406formed as an electrical path from the ground pad214to corresponding substrate pad through a solder bump, and from this substrate pad to another substrate pad through one or more metal interconnects in the metal layers in the substrate, and from this other substrate pad up to the ground pad216through a corresponding solder bump. The next link, die-level link408, is formed as a conductive path between the ground pad216and the power pad206due to the programmed anti-fuse224. The die-level link408is then followed by a substrate-level link410formed by the die-level interconnect connecting the power pad206to a corresponding pad of the substrate and then on to another stitch in the chain (not shown), or out through the test substrate and to a PCB.

When the stitch chain400is completed with the bonding of the die202to the corresponding substrate and the resulting IC device package mounted on a PCB, a test apparatus can drive a current through the stitch chain400through the PCB while repeatedly heating and cooling the test apparatus in a thermal cycling environment, and observe the stitch chain for changes in resistance or a complete open during the test process. From the information obtained from this test, BLR data can be generated for the die-level interconnects involved in the stitch chain, and thus the die-level interconnects for the IC device can be characterized. Thus, in this manner, BLR data for die-level interconnects can be provided to customers without requiring the design and fabrication of separate test die merely for testing purposes, as opposed to the die described herein that are manufactured as part of a standard production run.

FIGS. 5 and 6together illustrate a process to reconfigure the die from the production mode to the test mode using sacrificial fuse elements in accordance with some embodiments.FIG. 5depicts a top view of a die502(corresponding to the die102,FIG. 1) programmed for the production mode in which the fuse elements are disposed in a corner keep-out zone503of the die502, with the connections between the pads of the die502and the fuse elements of the keep-out zone503depicted by pairs of letters A-M, wherein each pair of letters indicates a portion of the connection coupling the pad and its respective bus line or fuse element. The top metal layer of the die502implements die pads501and504that are coupled to respective VDD power buses524and532through a plurality of fuses512and522, with die pad501coupled to fuse512and VDD power bus524through connection pair A-B and die pad504coupled to fuse522and VDD power bus532through connection pair K-L. As die pads501and504are connected to the VDD power busses524and532in this mode, the die pads501and504also are referred to herein as “power pads”501and504. The top metal layer of the die502further implements die pads508and510that are coupled to respective VSS power busses526and530by a plurality of fuses516and518, with die pad508coupled to fuse516and VDD power bus526through connection pair E-F and die pad510coupled to fuse518and VDD power bus530through connection pair G-H. As die pads508and510are connected to the VSS power busses526and530in this mode, the die pads508and510also are referred to herein as “ground pads”508and510. The die502further implements anti-fuse514connected between power pad501and ground pad508and anti-fuse520connected between power pad504and ground pad510, with power pad501and ground pad508being coupled through connection pair C-D and power pad504and ground pad510being coupled through connection pair I-J.

As noted, the fuse elements in the example ofFIGS. 5 and 6comprise electronic fuses and electronic anti-fuses, and thus are “programmed” via application of a programming signal. To provide this programming signal to all of the fuse elements to be included in a resulting stitch chain, the top metal layer of the die502further implements a die pad506that is coupled to fuses512,514,516,518,520, and522through connection M. The die pad506serves to program all of the fuses and anti-fuses located in the keep-out zone503by distributing an activation signal received through a probe applied to the die pad506, and thus the die pad506is also referred to herein as “activation pad506.”

In the production mode, illustrated inFIG. 5, the fuses512,516,518, and522are “unprogrammed” and thus conductive, thereby coupling the die pads501,504,508, and510to their respective power busses. Further, the anti-fuses516and520are likewise “unprogrammed,” and thus non-conductive, thereby preventing connectivity between the power pad501and the ground pad508and preventing connectivity between the power pad504and the ground pad510.

Turning toFIG. 6, a top-view of the die502during the process of programming the die502to enter the test mode is illustrated. This test mode programming is achieved by applying an activation signal to the fuse elements through a probe pin602applied to the activation pad506connected to the fuse elements disposed in the keep-out zone503, thus forming a stitch chain600formed in an IC device implementing the die502after it has been programmed for the test mode. The fuse elements are shown in their programmed state inFIG. 6with the fuses having been rendered non-conductive and the anti-fuses having been rendered conductive by probe pin602.

For example, application of the activation signal to the activation pad506via probe pin602“programs” the fuse512so as to render the fuse512non-conductive, thereby electrically isolating the power pad501from the VDD bus524. Likewise, application of the activation signal to the activation pad506through probe pin602“programs” the fuse516so as to render the fuse516non-conductive, thereby electrically isolating the ground pad508from the VSS bus526. Further, the activation signal introduced by the probe pin602“programs” the anti-fuse514so as to render the anti-fuse514conductive, thereby electrically connecting the power pad501and the ground pad508. Similarly, applications of the activation signal to the activation pad506through probe pin602“programs” fuses518and522and anti-fuse520, which in turn electrically isolates ground pad510from VSS bus530and power pad504from VDD bus532, respectively, while electrically connecting ground pad510and power pad504.

Upon programming of the fuses and anti-fuses by probe pin602for test mode, a stitch chain600is formed in an IC device implementing the die502after it has been bonded to a test substrate, such as the substrate104ofFIG. 1. A substrate-level link604of the stitch chain600is formed by a conductive path formed through a PCB and the test substrate, and through a solder bump or other die-level interconnect incorporating the pad501. The substrate-level link604is followed in the stitch chain600by a die-level link606formed between the power pad501and the ground pad508through the programmed anti-fuse514. The die-level link606is followed in the stitch chain600by a substrate-level link608formed as an electrical path from the ground pad508through a solder bump to corresponding substrate pad, and from this substrate pad to another substrate pad through one or more metal interconnects in the metal layers in the substrate, and from this other substrate pad up to the ground pad510through a corresponding solder bump. The next link, die-level link610, is formed as a conductive path between the ground pad510and the power pad504due to the programmed anti-fuse520. The die-level link610is then followed by a substrate-level link612formed by the substrate-level interconnect connecting the power pad504through a solder bump to a corresponding substrate pad of the substrate then on to another stitch in the chain (not shown) or out through the test substrate and to a PCB.

When the stitch chain600is completed with the bonding of the die502to the corresponding test substrate, and the resulting IC device mounted on a PCB, data regarding changes in resistance across the stitch change can be observed during testing of the die. With testing data obtained, BLR data can be generated regarding the die-level interconnects to provide to customers. While all of the die fabricated in a standard production run according to the design illustrated inFIGS. 5 and 6can likewise be programmed for testing as described above, only a subset of the die will be programmed and tested with the remaining die being implemented into IC devices that are sold or distributed to customers.