Semiconductor device

A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2014-221289, filed on Oct. 30, 2014, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to a semiconductor device, and an embodiment disclosed herein relates to a structure and a layout of a semiconductor device.

BACKGROUND

Recently, a driving circuit of a display device, a personal computer or the like includes a semiconductor device such as a transistor, a diode or the like as a microscopic switching element. Especially in a display device, a semiconductor device is used as a selective transistor that supplies a voltage or a current in accordance with the gray scale of each of pixels and also used in a driving circuit that selects a pixel that supplies the voltage or the current. The characteristics required of a semiconductor vary in accordance with the use thereof. For example, a semiconductor used as a selective transistor is required to have a low off-current or little variance from another selective semiconductor. A semiconductor used in a driving circuit is required to have a high on-current.

To be used in a display device as described above, a semiconductor device including a channel formed of amorphous silicon, low-temperature polysilicon or single crystalline silicon has been conventionally developed. A semiconductor device including a channel formed of amorphous silicon can be formed with a simpler structure and in a low-temperature process of 400° C. or lower, and therefore can be formed by use of a large glass substrate referred to as an eighth-generation glass substrate (2160×2460 mm). However, such a semiconductor device including a channel formed of amorphous silicon has a low mobility and is not usable in a driving circuit.

A semiconductor device including a channel formed of low-temperature polysilicon or single crystalline silicon has a higher mobility than the semiconductor device including a channel formed of amorphous silicon, and therefore is usable as a selective transistor and also in a driving circuit. However, such a semiconductor device including a channel formed of low-temperature polysilicon or single crystalline silicon has a complicated structure and needs a complicated process to be manufactured. In addition, such a semiconductor device needs to be formed in a high temperature process of 500° C. or higher, and therefore cannot be formed by use of a large glass substrate as described above. A semiconductor device including a channel formed of amorphous silicon, low-temperature polysilicon or single crystalline silicon has a high off-current. In the case where such a semiconductor device is used as a selective transistor, it is difficult to keep the applied voltage for a long time.

For the above-described reasons, a semiconductor device including a channel formed of an oxide semiconductor, instead of amorphous silicon, low-temperature polysilicon or single crystalline silicon, has been progressively developed recently (e.g., Japanese Laid-Open Patent Publication No. 2010-062229). It is known that a semiconductor device including a channel formed of an oxide semiconductor can be formed with a simple structure and in a low-temperature process like a semiconductor device including a channel formed of amorphous silicon, and has a mobility higher than that of a semiconductor device including a channel formed of amorphous silicon. It is also known that such a semiconductor device including a channel formed of an oxide semiconductor has a very low off-current.

However, the mobility of the semiconductor device including a channel formed of an oxide semiconductor is lower than that of the semiconductor device including a channel formed of low-temperature polysilicon or single crystalline silicon. Therefore, in order to provide a higher on-current, the semiconductor device including a channel formed of an oxide semiconductor needs to have a shorter channel length (L length). In order to shorten the channel length of the semiconductor device described in Japanese Laid-Open Patent Publication No. 2010-062229, a distance between a source and a drain needs to be shortened.

The distance between a source and a drain is determined by a photolithography step and an etching step. In the case where patterning is performed by photolithography, size reduction is restricted by the size of a mask pattern of an exposure device. Especially in the case where patterning is performed on a glass substrate by photolithography, the minimum size of a mask pattern is about 2 μm, and the reduction in the channel length of the semiconductor device is restricted by such a size of the mask pattern. The channel length of the semiconductor device is restricted by photolithography, and therefore, is influenced by the in-plane variance of the substrate in the photolithography step.

SUMMARY

A semiconductor device in an embodiment according to the present invention includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with a first portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with a second portion of the oxide semiconductor layer.

A semiconductor device in an embodiment according to the present invention includes a first insulating layer having a first side wall having a tapered inclining surface tending to close upward, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, a gate electrode located on the gate insulating layer, a first electrode located below the oxide semiconductor layer and connected with a first portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with a second portion of the oxide semiconductor layer.

A semiconductor device in an embodiment according to the present invention includes a first insulating layer having a first side wall, a first electrode located above the first insulating layer, an oxide semiconductor layer located on the first side wall and the first electrode, a first portion of the oxide semiconductor layer being connected with the first electrode, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a second electrode located below the oxide semiconductor layer and connected with a second portion of the oxide semiconductor layer, and a third electrode located above the first electrode and connected with the first electrode.

A semiconductor device in an embodiment according to the present invention includes a first insulating layer having a first side wall having a tapered inclining surface tending to close upward, a first electrode located above the first insulating layer, an oxide semiconductor layer located on the first side wall and the first electrode, a first portion of the oxide semiconductor layer being connected with the first electrode, a gate insulating layer located on the oxide semiconductor layer, a gate electrode located on the gate insulating layer, a second electrode located below the oxide semiconductor layer and connected with a second portion of the oxide semiconductor layer, and a third electrode located above the first electrode and connected with the first electrode.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The disclosure is merely exemplary, and alternations and modifications easily conceivable by a person of ordinary skill in the art without departing from the gist of the present invention are duly encompassed in the scope of the present invention. In the drawings, components may be shown schematically regarding the width, thickness, shape and the like, instead of being shown in accordance with the actual sizes, for the sake of clear illustration. The drawings are merely exemplary and do not limit the interpretations of the present invention in any way. In the specification and the drawings, components that are substantially the same as those shown in a previous drawing(s) bear the identical reference signs thereto, and detailed descriptions thereof may be omitted. The following embodiments are presented for the purpose of providing a semiconductor device capable of increasing the on-current or providing a semiconductor device capable of suppressing the in-plane variance of the channel length.

With reference toFIG. 1, an overview of a semiconductor device10in embodiment 1 according to the present invention will be described. The semiconductor device10in embodiment 1 is usable in a pixel or a driving circuit of a liquid crystal display device (LCD), a spontaneous light-emitting device using an organic light-emitting diode (OLED) such as an organic EL element, a quantum dot or the like for a display unit, or a reflection-type display device such as an electronic paper or the like.

It should be noted that a semiconductor device according to the present invention is not limited to being used in a display device, and may be used in, for example, an integrated circuit (IC) such as a microprocessing unit (MPU) or the like. The semiconductor device10in embodiment 1 is described as having a structure including a channel formed of an oxide semiconductor. The semiconductor device10in embodiment 1 is not limited to having such a structure, and may include a channel formed of, for example, a semiconductor such as silicon or the like, a compound semiconductor such as Ga—As or the like, or an organic semiconductor such as pentacene, tetracyanoquinodimethane (TCNQ) or the like. In embodiment 1, the semiconductor device10is a transistor. This does not limit the semiconductor device according to the present invention to a transistor.

[Structure of the Semiconductor Device10]

FIG. 1is a cross-sectional view showing an overview of the semiconductor device10in embodiment 1 according to the present invention. As shown inFIG. 1, the semiconductor device10includes a substrate100, an underlying layer110located on the substrate100, a lower electrode120located on the underlying layer110, a first insulating layer130located on the lower electrode120and having a first side wall131, a first assisting electrode190located above the first insulating layer130, and an oxide semiconductor layer140located on the first assisting electrode190and the first side wall131and connected with the lower electrode120located therebelow. The first assisting electrode190may be described as being held, at a position above the first insulating layer130, between the first insulating layer130and the oxide semiconductor layer140.

The semiconductor device10also includes a gate insulating layer150located opposite to the first insulating layer130while having the oxide semiconductor layer140therebetween, and a gate electrode160facing the oxide semiconductor layer140located at least on the first side wall131, with the gate insulating layer150being located between the oxide semiconductor layer140and the gate electrode160. The semiconductor device10further includes an interlayer insulating layer170located on the gate electrode160, and upper electrodes180located in openings171formed in the interlayer insulating layer170. The upper electrodes180specifically include upper electrodes180a,180band180c, but may be collectively referred to as the “upper electrodes180” in the case where the upper electrodes180a,180band180care not specifically distinguished from each other. The upper electrodes180a,180band180care respectively connected with the lower electrode120, the oxide semiconductor layer140and the gate electrode160. The openings171specifically include openings171a,171band171c, but may be collectively referred to as the “openings171” in the case where the openings171a,171band171care not specifically distinguished from each other. A part of the upper electrodes180is located above the oxide semiconductor layer140. The oxide semiconductor layer140includes a portion (first portion) thereof connected with the lower electrode120in a region132and another portion (second portion) thereof connected with the upper electrode180band the first assisting electrode190in a region192. In the case where a source voltage is applied to the upper electrode180aand a drain voltage is applied to the upper electrode180b, the region132may be referred to as a “source region” and the region192may be referred to as a “drain region”. The upper electrode180bis connected with the oxide semiconductor layer140on a side opposite to the first assisting electrode190.

The first side wall131may have a tapered inclining surface tending to close upward. Such a shape may be referred to as “forward tapered”. In this case, the oxide semiconductor layer140may be described as being located on the first side wall131. The gate insulating layer150may be described as being located on the oxide semiconductor layer140. The gate electrode160may be described as being located on the gate insulating layer150. InFIG. 1, the first assisting electrode190is located so as to cover a top surface of the first insulating layer130. The first assisting electrode190does not need to be formed on the entirety of the top surface of the first insulating layer130. It is sufficient that the first assisting electrode190is formed on at least a part of the top surface of the first insulating layer130. The first assisting electrode190may be formed on a part of the first side wall131in addition to on the first insulating layer130.

The substrate100may be formed of glass. Alternatively, the substrate100may be formed of a light-transmissive insulating material such as quartz, sapphire, a resin or the like. In the case where the semiconductor device10is used in an integrated circuit, not in a display device, the substrate100may be formed of a light-non-transmissive material, for example, a semiconductor such as silicon, silicon carbide, a compound semiconductor or the like, or a conductive material such as stainless steel or the like.

The underlying layer110may be formed of a material that suppresses diffusion of impurities from the substrate100into the oxide semiconductor layer140. For example, the underlying layer110may be formed of silicon nitride (SiNx), silicon nitride oxide (SiNxOy), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), aluminum nitride (AlNx), aluminum nitride oxide (AlNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), or the like (x and y each represent an arbitrary value). Alternatively, the underlying layer110may have a structure including a stack of films of such materials.

SiOxNyand AlOxNyare respectively a silicon compound and an aluminum compound containing nitrogen (N) at a lower content than oxygen (O). SiNxOyand AlNxOyare respectively a silicon compound and an aluminum compound containing oxygen at a lower content than nitrogen.

The underlying layer110described above may be formed of a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the usable PVD method include sputtering, vacuum vapor deposition, electron beam vapor deposition, plating, molecular beam epitaxy, and the like. Examples of the usable CVD method include thermal CVD, plasma CVD, catalyst CVD (catalytic-CVD or hot-wire CVD), and the like. A method other than the above-listed vapor deposition methods may be used as long as the film thickness can be controlled by a nanometer order (range less than 1 μm).

The lower electrode120may be formed of a common metal material or a common conductive semiconductor material. For example, the lower electrode120may be formed of aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), or the like. Alternatively, the lower electrode120may be formed of an alloy of such materials or a nitride of such materials. Still alternatively, the lower electrode120may be formed of a conductive oxide semiconductor such as ITO (indium tin oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), GZO (zinc oxide containing gallium as a dopant), or the like. The lower electrode120may have a structure including a stack of films of such materials.

Preferably, the material used for the lower electrode120is resistant to a heat treatment in a manufacturing process of a semiconductor device including a channel formed of an oxide semiconductor, and has a low contact resistance with the oxide semiconductor layer140. As a material having a good electric contact with the oxide semiconductor layer140, a metal material having a work function smaller than that of the oxide semiconductor layer140is usable.

The first insulating layer130may be formed of an inorganic insulating material such as SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like, like the underlying layer110. Alternatively, the first insulating layer130may be formed of an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, a siloxane resin, or the like. The first insulating layer130may be formed by substantially the same method as that of the underlying layer110. The first insulating layer130and the underlying layer110may be formed of the same material as, or different materials from, each other.

In the example shown inFIG. 1, the first insulating layer130has a cross-section with the forward tapered first side wall131being linear. The structure of the first insulating layer130is not limited to having this structure. The forward tapered first side wall131may be curved as protruding outward or curved as protruding inward. Instead of being forward tapered, the first side wall131may be vertical with respect to the surface of the substrate100, or reverse tapered, namely, incline while tending to close downward.

In the example shown inFIG. 1, the first insulating layer130is formed of a single layer. The first insulating layer130is not limited to having this structure, and may include a stack of a plurality of layers. In the case where the first insulating layer130includes a stack structure, the tapering angle and the shape of the first side wall131may be different layer by layer. Alternatively, the first insulating layer130may include a stack of layers of different properties (e.g., SiNxand SiOx) such that different portions, along the first side wall131, of the oxide semiconductor layer140have different properties. Namely, the semiconductor device10may have a channel formed of portions of the oxide semiconductor layer140that are of different characteristics and are connected to each other in series.

The oxide semiconductor layer140may be formed of a metal oxide material having the characteristics of a semiconductor. For example, the oxide semiconductor layer140may be formed of an oxide semiconductor containing indium (In), gallium (Ga), Zinc (Zn) and oxygen (O). Especially, the oxide semiconductor layer140may be formed of an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. It should be noted that the oxide semiconductor used in the present invention and containing In, Ga, Zn and O is not limited to having the above-described composition ratio. An oxide semiconductor having a different composition ratio is also usable. For example, in order to improve the mobility, the ratio of In may be increased. In order to increase the bandgap and thus decrease the influence of light, the ratio of Ga may be increased.

The oxide semiconductor containing In, Ga, Zn and O may contain another element added thereto. For example, a metal element such as Al, Sn or the like may be added. Instead of the above-described oxide semiconductor, zinc oxide (ZnO), nickel oxide (NiO), tin oxide (SnO2), titanium oxide (TiO2), vanadium oxide (VO2), indium oxide (In2O3), strontium titanate (SrTiO3), or the like may be used. The oxide semiconductor layer140may be amorphous or crystalline. Alternatively, the oxide semiconductor layer140may have a mixed phase of an amorphous phase and a crystalline phase.

The gate insulating layer150may be formed of an inorganic insulating material such as SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like, like the underlying layer110and the first insulating layer130. Alternatively, the gate insulating layer150may have a structure including a stack of insulating films of such materials. The gate insulating layer150may be formed by substantially the same method as that of the underlying layer110. The gate insulating layer150, the underlying layer110and the first insulating layer130may be formed of the same material as, or different materials from, each other.

The gate electrode160may be formed of any of substantially the same materials as those described above regarding the lower electrode120. The gate electrode160may be formed of the same material as, or a different material from, that of the lower electrode120. Preferably, the material used for the gate electrode160is resistant to a heat treatment in a manufacturing process of a semiconductor device including a channel formed of an oxide semiconductor, and has a work function with which the transistor is of an enhancement type that is turned off when the gate electrode is of 0 V.

The interlayer insulating layer170may be formed of an inorganic insulating material such as SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like, like the underlying layer110, the first insulating layer130and the gate insulating layer150. The interlayer insulating layer170may be formed by substantially the same method as that of the underlying layer110. Instead of the above-listed inorganic insulating materials, the interlayer insulating layer170may be formed of a TEOS layer or an organic insulating material. The TEOS layer refers to a CVD layer formed of TEOS (Tetra Ethyl Ortho Silicate), and has an effect of alleviating the steps of, and thus flattening, a layer therebelow. Examples of the usable organic insulating material include a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, a siloxane resin, and the like. The interlayer insulating layer170may be formed of a single layer or a stack of films of such materials. For example, the interlayer insulating layer170may include a stack of an inorganic insulating material and an organic insulating material.

The upper electrodes180and the first assisting electrode190may be formed of any of substantially the same materials as those described above regarding of the lower electrode120and the gate electrode160. The upper electrodes180and the first assisting electrode190may be formed of the same material as, or a different material from, that of the lower electrode120and the gate electrode160. The upper electrodes180and the first assisting electrode190may be formed of the same material as, or different materials from, each other. Alternatively, the upper electrodes180and the first assisting electrode190may be formed of copper (Cu), silver (Ag), gold (Au), or the like instead of the above-listed materials regarding the lower electrode120and the gate electrode160.

Preferably, the material used for each of the upper electrodes180and the first assisting electrode190is resistant to a heat treatment in a manufacturing process of a semiconductor device including a channel formed of an oxide semiconductor, and has a low contact resistance with the oxide semiconductor layer140. As a material having a good electric contact with the oxide semiconductor layer140, a metal material having a work function smaller than that of the oxide semiconductor layer140is usable for the upper electrodes180and the first assisting electrode190. The upper electrodes180and the first assisting electrode190may be formed of the same material as, or different materials from, each other. The portion of the oxide semiconductor layer140that is held between the upper electrode180band the first assisting electrode190may have a conductivity higher than that of the other portion of the oxide semiconductor layer140.

[Operation of the Semiconductor Device10]

An operation of the semiconductor device10shown inFIG. 1will be described. The semiconductor device10is a transistor including a channel formed of the oxide semiconductor layer140. A gate voltage is applied to the upper electrode180celectrically connected with the gate electrode160, a drain voltage is applied to the upper electrode180aelectrically connected with the lower electrode120, and a source voltage is applied to the upper electrode180belectrically connected with the oxide semiconductor layer140. The source voltage and the drain voltage may be applied oppositely. The source voltage applied to the upper electrode180bis supplied to the first assisting electrode190via the oxide semiconductor layer140.

When the gate voltage is applied to the gate electrode160, an electric field in accordance with the gate voltage is formed, via the gate insulating layer150, in the portion of the oxide semiconductor layer140facing the gate electrode160. The electric field generates carriers in the oxide semiconductor layer140. When a potential difference is caused between the lower electrode120and the first assisting electrode190in the state where the carriers are generated in the oxide semiconductor layer140, the carriers generated in the oxide semiconductor layer140are moved in accordance with the potential difference. Namely, electrons are moved from the first assisting electrode190to the lower electrode120.

The lower electrode120and the first assisting electrode190have a conductivity higher than that of the oxide semiconductor layer140in which the carriers are generated. Therefore, the electrons are supplied to the oxide semiconductor layer140in the source region192and are transferred to the lower electrode120in the drain region132. Namely, in the semiconductor device10, the portion of the oxide semiconductor layer140that is located on the first side wall131of the first insulating layer130acts as a channel. The channel length of the semiconductor device10is determined by the thickness of the first insulating layer130and the tapering angle of the first side wall131.

As described above, in the semiconductor device10in embodiment 1 according to the present invention, the portion of the oxide semiconductor layer140that is located on the first side wall131of the first insulating layer130acts as a channel. Therefore, the channel length of the semiconductor device10may be controlled by controlling either the thickness of the first insulating layer130or the tapering angle of the first side wall131, or by controlling both of the thickness of the first insulating layer130and the tapering angle of the first side wall131. As suggested above, the thickness of the first insulating layer130formed by a PVD method or a CVD method may be controlled by a nanometer order. Therefore, the semiconductor device10may have a channel length shorter than the limit of patterning by photolithography, by which variance is of a micrometer order. As a result, the semiconductor device10is capable of increasing the on-current.

The thickness of the first insulating layer130may be controlled by a nanometer order. Therefore, the in-plane variance of the thickness may also be controlled by a nanometer order. The tapering angle of the first side wall131may be controlled by the etching rate and the retraction amount of the resist for the first insulating layer130. The variance of the etching rate and the retraction amount of the resist for the first insulating layer130may also be controlled by substantially the same order as the variance of the thickness of the first insulating layer130. Therefore, the in-plane variance of the thickness of the first insulating layer130and the tapering angle of the first side wall131is smaller than the in-plane variance of the patterning precision by photolithography, which is of a micrometer order. As a result, the semiconductor device10is capable of suppressing the in-plane variance of the channel length. A top portion of the channel region formed of the oxide semiconductor layer140is covered with the gate electrode160, and a bottom portion thereof is covered with the lower electrode120. Therefore, in the case where the gate electrode160and the lower electrode120are formed of a light-non-transmissive metal material, the oxide semiconductor layer140is prevented from being irradiated with external light. As a result, the semiconductor device10has the characteristics thereof change little even in an environment where the semiconductor device10is irradiated with light.

[Manufacturing Method of the Semiconductor Device10]

With reference to plan views and cross-sectional views provided inFIG. 2throughFIG. 7, a manufacturing method of the semiconductor device10in embodiment 1 according to the present invention will be described.FIG. 2AandFIG. 2B(FIG. 2) are respectively a plan view and a cross-sectional view showing a step of forming the lower electrode120in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 2B, the underlying layer110and a film for the lower electrode120are formed on the substrate100, and patterning is performed as shown inFIG. 2Aby photolithography and etching to form the lower electrode120. Preferably, the etching is performed to form the lower electrode120under the condition that the etching rate ratio of the lower electrode120with respect to the underlying layer110is high. In this and the following descriptions of manufacturing methods of semiconductor devices in embodiments according to the present invention, an assembly of the substrate100and the film(s) formed thereon at each step will be referred to as the “substrate” for the sake of convenience.

FIG. 3AandFIG. 3B(FIG. 3) are respectively a plan view and a cross-sectional view showing a step of forming the first insulating layer130and the first assisting electrode190in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 3B, a film for the first insulating layer130and a film for the first assisting electrode190are formed on the entirety of the substrate shown inFIG. 2B, and patterning is performed as shown inFIG. 3Aby photolithography and etching to form the first insulating layer130and the first assisting electrode190. The first insulating layer130and the first assisting electrode190may be etched together or in separate steps. For example, after the first insulating layer130is formed by patterning, the film for the first assisting electrode190may be formed on a top surface and a side surface of the first insulating layer130and patterned to form the first assisting electrode190by photolithography and etching.

Preferably, the etching is performed to form the first insulting layer130under the condition that the etching rate ratio of the first insulting layer130with respect to at least the lower electrode120is high. More preferably, the etching is performed to form the first insulting layer130under the condition that the etching rate ratio of the first insulting layer130with respect to both of the lower electrode120and the underlying layer110is high. In the case where it is difficult to guarantee a high etching rate ratio of the first insulating layer130with respect to the underlying layer110, for example, in the case where the first insulating layer130and the underlying layer110are formed of the same material, an etching stopper layer may be formed on the underlying layer110. In the example shown inFIG. 3A, the pattern of the first insulating layer130is square. The first insulating layer130is not limited to being square, and may be of any of various shapes, for example, circular, elliptical, polygonal, curved or the like.

Now, an etching method for forming the first side wall131of the first insulating layer130to be tapered will be described. The tapering angle of the first side wall131may be controlled by the etching rate of the first insulating layer130and the etching rate, in a horizontal direction, of a resist used as a mask for etching the first insulating layer130(hereinafter, referred to as the “retraction amount of the resist”). In the case where, for example, the retraction amount of the resist is smaller than the etching rate of the first insulating layer130, the tapering angle of the first side wall131is large (close to vertical). In the case where the retraction amount of the resist is zero, the first side wall131is vertical. By contrast, in the case where the retraction amount of the resist is larger than the etching rate of the first insulating layer130, the tapering angle of the first side wall131is small (close to horizontal). The retraction amount of the resist may be adjusted by the tapering angle of an end of the resist and the etching rate of the resist.

FIG. 4AandFIG. 4B(FIG. 4) are respectively a plan view and a cross-sectional view showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 4B, a film for the oxide semiconductor layer140is formed on the entirety of the substrate shown inFIG. 3B, and patterning is performed as shown inFIG. 4Aby photolithography and etching to form the oxide semiconductor layer140. The oxide semiconductor layer140may be formed by sputtering. The etching performed to form the oxide semiconductor layer140may be dry etching or wet etching. In the case where the oxide semiconductor layer140is formed by wet etching, an etchant containing oxalic acid may be used.

In the example shown inFIG. 4AandFIG. 4B, the oxide semiconductor layer140is formed on one side surface of the first insulating layer130. The oxide semiconductor layer140is not limited to having this structure. For example, the oxide semiconductor layer140may be formed so as to cover the first insulating layer130, namely, may be formed on the entirety of the first side wall131of the first insulating layer130.

FIG. 5AandFIG. 5B(FIG. 5) are respectively a plan view and a cross-sectional view showing a step of forming the gate insulating layer150and the gate electrode160in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 5B, the gate insulating layer150and a film for the gate electrode160are formed on the entirety of the substrate shown inFIG. 4B, and patterning is performed as shown inFIG. 5Aby photolithography and etching to form the gate electrode160. In the example shown inFIG. 5B, the gate insulating layer150acts as an etching stopper for the gate electrode160, and only the film for the gate electrode160is etched. Alternatively, both of the gate insulating layer150and the gate electrode160may be formed together by etching.

As shown inFIG. 5A, the gate electrode160is formed so as to cover an end, in a channel width direction (W length direction; namely, direction perpendicular to A-B direction inFIG. 5A), of the oxide semiconductor layer140. In other words, the gate electrode160of the semiconductor device10is longer in the W length direction than the channel provided by the oxide semiconductor layer140. In still other words, the gate electrode160is longer in the W length direction than the oxide semiconductor layer140on the first side wall131. During the etching performed to form the oxide semiconductor layer140, the end of the oxide semiconductor layer140may possibly have properties thereof changed. The gate electrode160formed in the pattern as shown inFIG. 5Asuppresses a leak path from being formed at the end of the oxide semiconductor layer140even when the end of the oxide semiconductor layer140has many defects by the influence of the etching.

FIG. 6AandFIG. 6B(FIG. 6) are respectively a plan view and a cross-sectional view showing a step of forming the interlayer insulating layer170and also forming the openings171in the interlayer insulating layer170and the gate insulating layer150in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 6B, the interlayer insulating layer170is formed on the entirety of the substrate shown inFIG. 5B, and patterning is performed as shown inFIG. 6Aby photolithography and etching to form the openings171. The opening171aexposes the lower electrode120, the opening171bexposes the oxide semiconductor layer140, and the opening171cexposes the gate electrode160. Preferably, the etching rate ratio of the gate insulating layer150and the interlayer insulating layer170with respect to the lower electrode120, the oxide semiconductor layer140and the gate electrode160is high.

FIG. 7AandFIG. 7B(FIG. 7) are respectively a plan view and a cross-sectional view showing a step of forming the upper electrodes180in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 7B, a film for the upper electrodes180is formed on the entirety of the substrate shown inFIG. 6B, and patterning is performed as shown inFIG. 7Aby photolithography and etching to form the upper electrodes180.

The semiconductor device10in embodiment 1 according to the present invention is manufactured by the manufacturing method described above. Referring toFIG. 7B, the portion of the oxide semiconductor layer140that is located on the first side wall131is a channel region141(FIG. 7A). Namely, as shown inFIG. 7A, the channel region141is formed in an area of the oxide semiconductor layer140that is covered with the gate electrode160, and the end of the oxide semiconductor layer140is included in the channel region141.

Modifications of Embodiment 1

With reference toFIG. 8throughFIG. 10, modifications of embodiment 1 will be described. A semiconductor device11in modification 1 of embodiment 1 is similar to the semiconductor device10in embodiment 1. In the following description, the identical elements to, or the elements having the identical functions to, those of the semiconductor device10will bear the identical reference numerals thereto, and detailed descriptions thereof will be omitted.

FIG. 8is a cross-sectional view showing an overview of the semiconductor device11in modification 1 of embodiment 1 according to the present invention. As shown inFIG. 8, in the semiconductor device11, unlike in the semiconductor device10shown inFIG. 1, the upper electrode180bis connected with the first assisting electrode190, not with the oxide semiconductor layer140. In the semiconductor device11, it is sufficient that the oxide semiconductor layer140is in contact with the first assisting electrode190and does not need to overlap the upper electrode180bas seen in a plan view. Namely, unlike in the semiconductor device10shown inFIG. 1, the upper electrode180bdoes not need to be located above the oxide semiconductor layer140.

As described above, in the semiconductor device11in modification 1 of embodiment 1, the upper electrode180bis in contact with the first assisting electrode190. Therefore, the contact resistance is further decreased. As a result, the semiconductor device11is capable of further increasing the on-current.

FIG. 9is a cross-sectional view showing an overview of a semiconductor device12in modification 2 of embodiment 1 according to the present invention. As shown inFIG. 9, in the semiconductor device12, unlike in the semiconductor device10shown inFIG. 1, the gate insulating layer150and the gate electrode160have ends thereof flush. Although not shown, in the semiconductor device12, the gate insulating layer150and the gate electrode160have substantially the same pattern as seen in a plan view. The semiconductor device12may be manufactured by, for example, forming the gate electrode160and the gate insulating layer150at the same time by etching in the step shown inFIG. 5B, or by performing etching to form the gate insulating layer150using, as a mask, the gate electrode160that is patterned as shown inFIG. 5B.

As described above, in the semiconductor device12in modification 2 of embodiment 1, the openings171aand171bare formed in the same layer structure as the opening171cin the step of forming the openings171shown inFIG. 6B. Therefore, the condition of etching performed to form the openings171is adjusted easily.

FIG. 10is a cross-sectional view showing an overview of a semiconductor device13in modification 3 of embodiment 1 according to the present invention. As shown inFIG. 10, in the semiconductor device13, unlike in the semiconductor device10shown inFIG. 1, the oxide semiconductor layer140is located above the first insulating layer130, without the first assisting electrode190being provided. Namely, the upper electrode180bis connected at a position above the first insulating layer130, with the oxide semiconductor layer140. In the semiconductor device13, an offset region in which no electric field is formed by the gate voltage applied to the gate electrode160is present between an end161of the gate electrode160and an end181of the upper electrode180b. In order to provide a higher on-current, the oxide semiconductor layer140having a conductivity higher than that of the channel may be provided in the offset region. The oxide semiconductor layer140having such a high conductivity may be formed by, for example, implanting impurities that generate carriers into the oxide semiconductor layer140from above using the gate electrode160as a mask in the step shown inFIG. 5B, or by incorporating hydrogen into the interlayer insulating layer170to form an inorganic insulating film of SiNxor the like.

As described above, in the semiconductor device13in modification 3 of embodiment 1, the first assisting electrode190does not need to be formed above the first insulating layer130. This eliminates the step of forming the film for the first assisting electrode190and performing the patterning to form the first assisting electrode190. This shortens the manufacturing process. Since the first assisting electrode190is not located above the first insulating layer130, the shape of the first insulating layer130is adjusted easily.

With reference toFIG. 11, an overview of a semiconductor device20in embodiment 2 according to the present invention will be described. The semiconductor device20in embodiment 2 is usable in a display device or a driving circuit, like the semiconductor layer10in embodiment 1. The semiconductor device20in embodiment 2 is described as having a structure including a channel formed of an oxide semiconductor. The semiconductor device20in embodiment 2 is not limited to having such a structure, and may include a channel formed of, for example, a semiconductor such as silicon or the like, a compound semiconductor such as Ga—As or the like, or an organic semiconductor such as pentacene, tetracyanoquinodimethane (TCNQ) or the like. In embodiment 2, the semiconductor device20is a transistor. This does not limit the semiconductor device according to the present invention to a transistor.

[Structure of the Semiconductor Device20]

FIG. 11is a cross-sectional view showing an overview of the semiconductor device20in embodiment 2 according to the present invention. As shown inFIG. 11, the semiconductor device20includes a substrate100, an underlying layer110located on the substrate100, a lower electrode120located on the underlying layer110, a first insulating layer130located on the lower electrode120and having a first side wall131, a first assisting electrode190located above the first insulating layer130, and an oxide semiconductor layer140located on the first assisting electrode190, the first side wall131, the underlying layer110and the lower electrode120and connected with the lower electrode120in a region121. At a position between the first insulating layer130and the lower electrode120, the oxide semiconductor layer140is in contact with the underlying layer110.

The semiconductor device20also includes a gate insulating layer150located opposite to the underlying layer110, the lower electrode120and the first insulating layer130while having the oxide semiconductor layer140therebetween, and a gate electrode160facing portions of the oxide semiconductor layer140while having the gate insulating layer150therebetween. The portions of the oxide semiconductor layer140facing the gate electrode160are located on a portion of the underlying layer120that is between the first insulating layer130and the lower electrode120, and on the first side wall131. The semiconductor device20further includes an interlayer insulating layer170located on the gate electrode160, and upper electrodes180located in openings171formed in the interlayer insulating layer170. The upper electrodes180are respectively connected with the lower electrode120, the oxide semiconductor layer140and the gate electrode160. Namely, a part of the upper electrodes180is located above the oxide semiconductor layer140. The oxide semiconductor layer140includes a portion (first portion) thereof connected with the lower electrode120in the region121and another portion (second portion) thereof connected with the upper electrode180band the first assisting electrode190. In other words, the upper electrode180bis connected with the oxide semiconductor layer140on a side opposite to the first assisting electrode190.

The substrate100, the underlying layer110, the lower electrode120, the first insulating layer130, the oxide semiconductor layer140, the gate insulating layer150, the gate electrode160, the interlayer insulating layer170, the upper electrodes180, and the first assisting electrode190may each be formed of any of the materials described in embodiment 1.

Regarding the oxide semiconductor layer140, the portion thereof located on the first side wall131and the portion thereof located on the underlying layer110may have different properties from each other. Namely, the semiconductor device20may have a channel formed of portions of the oxide semiconductor layer140that are of different characteristics connected to each other in series. For example, in the case where the portion of the oxide semiconductor layer140located on the first side wall131has few defects and a low off-current (leak current), the portion of the oxide semiconductor layer140located on the underlying layer110may have many defects and a high off-current (leak current). Namely, the specific electrical resistance of the portion of the oxide semiconductor layer140located on the underlying layer110may be smaller than the specific electrical resistance of the portion of the oxide semiconductor layer140located on the first side wall131. In other words, the portions of the oxide semiconductor layer140that are different in the level of the off-current (leak current) caused by the defects of the oxide semiconductor or in the specific electrical resistance in accordance with the layer therebelow may be connected to each other in series. Needless to say, the portion of the oxide semiconductor layer140located on the first side wall131may have many defects and a low specific electrical resistance, whereas the portion of the oxide semiconductor layer140located on the underlying layer110may have few defects and a low off-current.

As described above, in the semiconductor device20in embodiment 2 according to the present invention, the portions of the oxide semiconductor layer140located on the first side wall131and the underlying layer110act as a channel. Therefore, the channel length of the semiconductor device20is controlled easily, which provides substantially the same effect as that of embodiment 1. The lower electrode120and the first insulating layer130do not need to be stacked, which allows the semiconductor device20to have any of various layouts. Namely, the degree of designing freedom is improved.

[Manufacturing Method of the Semiconductor Device20]

With reference to plan views and cross-sectional views provided inFIG. 12throughFIG. 17, a manufacturing method of the semiconductor device20in embodiment 2 according to the present invention will be described. The manufacturing method of the semiconductor device20shown inFIG. 11is similar to the manufacturing method of the semiconductor device10shown inFIG. 1, and thus will not be described in detail.FIG. 12AandFIG. 12B(FIG. 12) are respectively a plan view and a cross-sectional view showing a step of forming the lower electrode120in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. First, referring toFIG. 12B, the underlying layer110and a film for the lower electrode120are formed on the substrate100, and patterning is performed as shown inFIG. 12Aby photolithography and etching to form the lower electrode120. In the case where the specific electrical resistance of the oxide semiconductor layer140that is to be located on the underlying layer110in a later step is to be made small, the underlying layer110may be formed of an inorganic insulating material such as hydrogen-containing SiNxor the like.

FIG. 13AandFIG. 13B(FIG. 13) are respectively a plan view and a cross-sectional view showing a step of forming the first insulating layer130and the first assisting electrode190in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. Referring toFIG. 13B, a film for the first insulating layer130and a film for the first assisting electrode190are formed on the entirety of the substrate shown inFIG. 12B, and patterning is performed as shown inFIG. 13Aby photolithography and etching to form the first insulating layer130and the first assisting electrode190. The lower electrode120is separate from the first insulating layer130and the first assisting electrode190. Therefore, in the case where the first insulating layer130and the underlying layer110are formed of the same material and thus it is difficult to guarantee a high etching rate ratio of the first insulating layer130with respect to the underlying layer110, the patterning to form the lower electrode120may be performed after the patterning to form the first insulating layer130and the first assisting electrode190is performed, unlike according to the method shown inFIG. 12andFIG. 13.

FIG. 14AandFIG. 14B(FIG. 14) are respectively a plan view and a cross-sectional view showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. Referring toFIG. 14B, a film for the oxide semiconductor layer140is formed on the entirety of the substrate shown inFIG. 13B, and patterning is performed as shown inFIG. 14Aby photolithography and etching to form the oxide semiconductor layer140.

FIG. 15AandFIG. 15B(FIG. 15) are respectively a plan view and a cross-sectional view showing a step of forming the gate insulating layer150and the gate electrode160in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. Referring toFIG. 15B, the gate insulating layer150and a film for the gate electrode160are formed on the entirety of the substrate shown inFIG. 14B, and patterning is performed as shown inFIG. 15Aby photolithography and etching to form the gate electrode160. The gate electrode160extends over an end, in a direction of the L length, of the oxide semiconductor layer140and faces the lower electrode120in a region162while having the gate insulating layer150therebetween. Namely, the region162may act as a capacitor using the gate insulating layer150as a dielectric element.

FIG. 16AandFIG. 16B(FIG. 16) are respectively a plan view and a cross-sectional view showing a step of forming the interlayer insulating layer170and also forming the openings171in the interlayer insulating layer170and the gate insulating layer150in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. Referring toFIG. 16B, the interlayer insulating layer170is formed on the entirety of the substrate shown inFIG. 15B, and patterning is performed as shown inFIG. 16Aby photolithography and etching to form the openings171. The opening171aexposes the lower electrode120, the opening171bexposes the oxide semiconductor layer140, and the opening171cexposes the gate electrode160.

FIG. 17AandFIG. 17B(FIG. 17) are respectively a plan view and a cross-sectional view showing a step of forming the upper electrodes180in the manufacturing method of the semiconductor device20in embodiment 2 according to the present invention. Referring toFIG. 17B, a film for the upper electrodes180is formed on the entirety of the substrate shown inFIG. 16B, and patterning is performed as shown inFIG. 17Aby photolithography and etching to form the upper electrodes180.

The semiconductor device20in embodiment 2 according to the present invention is manufactured by the manufacturing method described above. Portions of the oxide semiconductor layer140that are located on the underlying layer110and the first side wall131inFIG. 17B, namely, regions142aand142bof the oxide semiconductor layer140inFIG. 17A, act as a channel. The materials of the underlying layer110and the first insulating layer130may be selected such that the regions142aand142bof the oxide semiconductor layer140have different properties from each other.

Modification of Embodiment 2

With reference toFIG. 18, a modification of embodiment 2 according to the present invention will be described. A semiconductor device21in the modification of embodiment 2 is similar to the semiconductor device20in embodiment 2. In the following description, the identical elements to, or the elements having the identical functions to, those of the semiconductor device20will bear the identical reference numerals thereto, and detailed descriptions thereof will be omitted.

FIG. 18is a cross-sectional view showing an overview of the semiconductor device21in the modification of embodiment 2 according to the present invention. As shown inFIG. 18, the semiconductor device21is similar to the semiconductor device20shown inFIG. 11. However, in the semiconductor device21, unlike in the semiconductor device20shown inFIG. 11, the lower electrode120is located on a part of the first side wall131of the first insulating layer130. In the semiconductor device21, an end of the lower electrode120and an end of the first insulating layer130(i.e., end of the first side wall131) generally match each other. Namely, the lower electrode120is located so as not to be higher than the current height on the first side wall131. The lower electrode120is not limited to having the structure shown inFIG. 18, and may be higher than the current height on the first side wall131as long as the lower electrode120does not each the first assisting electrode190.

As described above, in the semiconductor device21in the modification of embodiment 2, a distance of a portion of the first side wall131that is between the end of the lower electrode120and the end of the first assisting electrode190is the channel length. Namely, the channel length may be adjusted by the thickness of the first insulating layer130and the thickness of the lower electrode120.

With reference toFIG. 19AandFIG. 19B(FIG. 19), an overview of a semiconductor device30in embodiment 3 according to the present invention will be described. The semiconductor device30in embodiment 3 is usable in a display device or a driving circuit, like the semiconductor layer10in embodiment 1. The semiconductor device30in embodiment 3 is described as having a structure including a channel formed of an oxide semiconductor. The semiconductor device30in embodiment 3 is not limited to having such a structure, and may include a channel formed of, for example, a semiconductor such as silicon or the like, a compound semiconductor such as Ga—As or the like, or an organic semiconductor such as pentacene, tetracyanoquinodimethane (TCNQ) or the like. In embodiment 3, the semiconductor device30is a transistor. This does not limit the semiconductor device according to the present invention to a transistor.

[Structure of the Semiconductor Device30]

FIG. 19Ais a plan view showing an overview of the semiconductor device30in embodiment 3 according to the present invention.FIG. 19Bis a cross-sectional view showing an overview of the semiconductor device30in embodiment 3 according to the present invention. The semiconductor device30shown inFIG. 19has the same cross-sectional structure as that of the semiconductor device10shown inFIG. 7, but have a layout different from that of the semiconductor device10. Specifically, in the semiconductor device30, unlike in the semiconductor device10, the oxide semiconductor layer140is located so as to cover the first insulating layer130(seeFIG. 20A) and the gate electrode160is located in a ring shape around the upper electrode180bso as to cover the first side wall131(seeFIG. 21A) as seen in a plan view. Namely, as shown inFIG. 19A, a channel region143of the semiconductor device30is formed to have a ring shape, and an end of the oxide semiconductor layer140is not included in the channel region143. Since the channel region143has a ring shape, this structure is called the “surround type”.

In the example shown inFIG. 19B, the oxide semiconductor layer140is formed to cover the first side wall131and a top surface of the first insulating layer130. The oxide semiconductor layer140is not limited to having such a structure. For example, it is sufficient that the oxide semiconductor layer140is formed on at least the first side wall131. Namely, the oxide semiconductor layer140does not need to cover the top surface of the first insulating layer130.

In the example shown inFIG. 19, the surround-type semiconductor device30has the structure of embodiment 1 shown inFIG. 1. Alternatively, a surround-type semiconductor device may have the structure of any of modifications 1 through 3 of embodiment 1 shown inFIG. 8throughFIG. 10. Still alternatively, a surround-type semiconductor device may have the structure of embodiment 2 shown inFIG. 11or the modification of embodiment 2 shown inFIG. 18.

As described above, in the semiconductor device30in embodiment 3 according to the present invention, the gate electrode160is located in a ring shape while facing the first side wall131, and the channel region143is located in a ring shape. Therefore, the end of the oxide semiconductor layer140is not included in the channel region143. Because of this structure, no leak path is generated by the end of the oxide semiconductor layer140. Namely, the semiconductor device30is capable of further decreasing the off-current in addition to providing the effect of embodiment 1.

[Manufacturing Method of the Semiconductor Device30]

With reference to plan views and cross-sectional views provided inFIG. 20throughFIG. 22, a manufacturing method of the semiconductor device30in embodiment 3 according to the present invention will be described. The manufacturing method of the semiconductor device30shown inFIG. 19is similar to the manufacturing method of the semiconductor device10shown inFIG. 1, and thus will not be described in detail. The manufacturing method of the semiconductor device30is the same as that of the manufacturing method of the semiconductor device10up to the step of forming the first insulating layer130and the first assisting electrode (same as inFIG. 2andFIG. 3). This part of the manufacturing method will not be described.

FIG. 20AandFIG. 20B(FIG. 20) are respectively a plan view and a cross-sectional view showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device30in embodiment 3 according to the present invention. Referring toFIG. 20B, a film for the oxide semiconductor layer140is formed on the entirety of the substrate shown inFIG. 3B, and patterning is performed as shown inFIG. 20Ato form the oxide semiconductor layer140. In the example shown inFIG. 20, the oxide semiconductor layer140is formed so as to cover the first insulating layer130. It is sufficient that the oxide semiconductor layer140is located in a ring shape around the first side wall131, which is ring-shaped, and is partially connected with the lower electrode120and the first assisting electrode190. Namely, the oxide semiconductor layer140does not need to cover a top surface of the first assisting electrode190.

FIG. 21AandFIG. 21B(FIG. 21) are respectively a plan view and a cross-sectional view showing a step of forming the gate insulating layer150and the gate electrode160in the manufacturing method of the semiconductor device30in embodiment 3 according to the present invention. Referring toFIG. 21B, the gate insulating layer150and a film for the gate electrode160are formed on the entirety of the substrate shown inFIG. 20B, and patterning is performed as shown inFIG. 21Ato form the gate electrode160.

FIG. 22AandFIG. 22B(FIG. 22) are respectively a plan view and a cross-sectional view showing a step of forming the interlayer insulating layer170and also forming the openings171in the interlayer insulating layer170and the gate insulating layer150in the manufacturing method of the semiconductor device30in embodiment 3 according to the present invention. Referring toFIG. 22B, the interlayer insulating layer170is formed on the entirety of the substrate shown inFIG. 21B, and patterning is performed as shown inFIG. 22Ato form the openings171. The opening171aexposes the lower electrode120, the opening171bexposes the oxide semiconductor layer140, and the opening171cexposes the gate electrode160. Then, a film for the upper electrodes180is formed on the entirety of the substrate shown inFIG. 22B, and patterning is performed to form the upper electrodes180as shown inFIG. 19. In this manner, the semiconductor device30shown inFIG. 19is manufactured.

Modifications of Embodiment 3

With reference toFIG. 23throughFIG. 32, modifications of embodiment 3 according to the present invention will be described. Semiconductor devices31and32in modifications 1 and 2 of embodiment 3 each have the same cross-sectional structure as that of the semiconductor device10shown inFIG. 7, but have a layout different from that of the semiconductor device10. Hereinafter, the layouts in each modification will be described in detail.

[Structure of the Semiconductor Device31]

FIG. 23AandFIG. 23B(FIG. 23) are respectively a plan view and a cross-sectional view showing an overview of the semiconductor device31in modification 1 of embodiment 3 according to the present invention. As shown inFIG. 23, the semiconductor device31in modification 1 of embodiment 3 includes a plurality of the surround-type semiconductor devices30shown inFIG. 19that are coupled to each other in series. Namely, the semiconductor devices30each including the ring-shaped channel region143are located adjacent to each other. The first electrodes120of the plurality of the semiconductor devices30are provided as one integral first electrode120, the gate electrodes160of the plurality of the semiconductor devices30are provided as one integral gate electrode160, and the upper electrodes180of the plurality of the semiconductor devices30are provided as one integral gate electrode180. Therefore, the plurality of semiconductor devices30are supplied with the same source-drain voltage at the same time and with the same gate voltage at the same time.

In the example shown inFIG. 23, the surround-type semiconductor devices30each have the structure of embodiment 1 shown inFIG. 1. Alternatively, surround-type semiconductor devices may each have the structure of any of modifications 1 through 3 of embodiment 1 shown inFIG. 8throughFIG. 10. Still alternatively, surround-type semiconductor devices may each have the structure of embodiment 2 shown inFIG. 11or the modification of embodiment 2 shown inFIG. 18.

As described above, in the semiconductor device31, the ring-shaped channel regions143of the plurality of semiconductor devices30are turned on/off at the same time. Therefore, the W length of the semiconductor device31is substantially increased. As a result, the semiconductor device31is capable of increasing the on-current.

[Manufacturing Method of the Semiconductor Device31]

In order to more clarify the structure of the semiconductor device31shown inFIG. 23, a manufacturing method of the semiconductor device31will be described with reference to plan views and cross-sectional views provided inFIG. 24throughFIG. 27. Each of the semiconductor devices30included in the semiconductor device31shown inFIG. 23are the same as the semiconductor device30shown inFIG. 19, and thus will not be described in detail.

FIG. 24AandFIG. 24B(FIG. 24) are respectively a plan view and a cross-sectional view showing a step of forming the first insulating layers130and the first assisting electrodes190on the lower electrode120in the manufacturing method of the semiconductor device31in modification 1 of embodiment 3 according to the present invention. As shown inFIG. 24, a plurality of the first insulating layers130and a plurality of the first assisting electrodes190are formed adjacent to each other on one lower electrode120. In the example shown inFIG. 24, three first insulating layers130and three first assisting electrode190are formed on one lower electrode120. The semiconductor device31is not limited to having such a structure, and the number of the first insulating layers130and the number of the first assisting electrode190located on one lower electrode120may be smaller or larger than three.

FIG. 25AandFIG. 25B(FIG. 25) are respectively a plan view and a cross-sectional view showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device31in modification 1 of embodiment 3 according to the present invention. Referring toFIG. 25B, a film for the oxide semiconductor layer140is formed on the entirety of the substrate shown inFIG. 24B, and patterning is performed as shown inFIG. 25Ato form the oxide semiconductor layer140. In the example shown inFIG. 25, the oxide semiconductor layer140covers the first insulating layers130. It is sufficient that the oxide semiconductor layer140is located in a ring shape around the first side walls131, which are ring-shaped, and is partially connected with the lower electrode120and the first assisting electrodes190. Namely, the oxide semiconductor layer140does not need to cover the top surfaces of the first assisting electrodes190.

FIG. 26AandFIG. 26B(FIG. 26) are respectively a plan view and a cross-sectional view showing a step of forming the gate insulating layer150and the gate electrode160in the manufacturing method of the semiconductor device31in modification 1 of embodiment 3 according to the present invention. Referring toFIG. 26B, the gate insulating layer150and a film for the gate electrode160are formed on the entirety of the substrate shown inFIG. 25B, and patterning is performed as shown inFIG. 26Ato form the gate electrode160.

FIG. 27AandFIG. 27B(FIG. 27) are respectively a plan view and a cross-sectional view showing a step of forming the interlayer insulating layer170and also forming the openings171in the interlayer insulating layer170and the gate insulating layer150in the manufacturing method of the semiconductor device31in modification 1 of embodiment 3 according to the present invention. Referring toFIG. 27B, the interlayer insulating layer170is formed on the entirety of the substrate shown inFIG. 26B, and patterning is performed as shown inFIG. 27Ato form the openings171. The openings171respectively expose portions of the oxide semiconductor layer140that are located on the plurality of first insulating layers130. Then, a film for the upper electrode180is formed on the entirety of the substrate shown inFIG. 27B, and patterning is performed to form the upper electrode180as shown inFIG. 23. In this manner, the semiconductor device31shown inFIG. 23is manufactured.

[Structure of the Semiconductor Device32]

FIG. 28AandFIG. 28B(FIG. 28) are respectively a plan view and a cross-sectional view showing an overview of the semiconductor device32in modification 2 of embodiment 3 according to the present invention. As shown inFIG. 28, the semiconductor device32in modification 2 of embodiment 3 includes a plurality of the surround-type semiconductor devices30shown inFIG. 19that are coupled parallel to each other, such that the ring-shaped channel regions are multiplexed. Namely, a semiconductor device30bincluding a second ring-shaped channel region145, which is an outer channel region, is located so as to surround a semiconductor device30aincluding a first ring-shaped channel region144, which is an inner channel region.

As shown also inFIG. 29AandFIG. 29B(FIG. 29), the semiconductor device32includes a first insulating layer133having a first side wall135and a second insulating layer134having a second side wall136. The second insulating layer134is located around the first insulating layer133. The first side wall135and the second side wall136face each other as seen in a plan view. The first electrodes120of the semiconductor devices30aand30bare provided as one integral first electrode120, the gate electrodes160of the semiconductor devices30aand30bare provided as one integral gate electrode160, and the upper electrodes180of the semiconductor devices30aand30bare provided as one integral upper electrode180. Namely, one integral electrode160is provided on the first side wall135and the second side wall136. Therefore, the semiconductor devices30aand30bare supplied with the same source-drain voltage at the same time and with the same gate voltage at the same time.

In the example shown inFIG. 28, the surround-type semiconductor devices30aand30beach have the structure of embodiment 1 shown inFIG. 1. Alternatively, surround-type semiconductor devices may each have the structure of any of modifications 1 through 3 of embodiment 1 shown inFIG. 8throughFIG. 10. Still alternatively, surround-type semiconductor devices may each have the structure of embodiment 2 shown inFIG. 11or the modification of embodiment 2 shown inFIG. 18.

As described above, in the semiconductor device32, the ring-shaped channel region144of the semiconductor device30aand the ring-shaped channel region145of the semiconductor device30bare turned on/off at the same time. Therefore, the W length of the semiconductor device32is substantially increased. As a result, the semiconductor device32is capable of increasing the on-current.

[Manufacturing Method of the Semiconductor Device32]

In order to more clarify the structure of the semiconductor device32shown inFIG. 28, a manufacturing method of the semiconductor device32will be described with reference to plan views and cross-sectional views provided inFIG. 29throughFIG. 32. The cross-sectional structure of each of the semiconductor devices30aand30bincluded in the semiconductor device32shown inFIG. 28is the same as that of the semiconductor device30shown inFIG. 19, and thus will not be described in detail.

FIG. 29AandFIG. 29B(FIG. 29) are respectively a plan view and a cross-sectional view showing a step of forming the first insulating layer133, the second insulating layer134, a first assisting electrode193and a second assisting electrode194on the lower electrode120in the manufacturing method of the semiconductor device32in modification 2 of embodiment 3 according to the present invention. As shown inFIG. 29, the first insulating layer133and the first assisting electrode193, and also the second insulating layer134and the second assisting electrode194, which are ring-shaped, are formed on one lower electrode120. The second insulating layer134and the second assisting electrode194are located around the first insulating layer133and the first assisting electrode193. In the semiconductor device32, a channel is formed between the first side wall135of the first insulating layer133and the second side wall136of the second insulating layer134.

FIG. 30AandFIG. 30B(FIG. 30) are respectively a plan view and a cross-sectional view showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device32in modification 2 of embodiment 3 according to the present invention. Referring toFIG. 30B, a film for the oxide semiconductor layer140is formed on the entirety of the substrate shown inFIG. 29B, and patterning is performed as shown inFIG. 30Ato form the oxide semiconductor layer140. In the example shown inFIG. 30, the oxide semiconductor layer140covers the first insulating layer133, and has an outer perimeter that is located outer to an inner perimeter of the second insulating layer134and inner to the outer perimeter of the second insulating layer134. It is sufficient that the oxide semiconductor layer140is located in a ring shape along the first side wall135and the second side wall136and is at least partially connected with the lower electrode120, the first assisting electrode193and the second assisting electrode194.

FIG. 31AandFIG. 31B(FIG. 31) are respectively a plan view and a cross-sectional view showing a step of forming the gate insulating layer150and the gate electrode160in the manufacturing method of the semiconductor device32in modification 2 of embodiment 3 according to the present invention. Referring toFIG. 31B, the gate insulating layer150and a film for the gate electrode160are formed on the entirety of the substrate shown inFIG. 30B, and patterning is performed as shown inFIG. 31Ato form the gate electrode160.

FIG. 32AandFIG. 32B(FIG. 32) are respectively a plan view and a cross-sectional view showing a step of forming the interlayer insulating layer170and also forming openings173and174in the interlayer insulating layer170and the gate insulating layer150in the manufacturing method of the semiconductor device32in modification 2 of embodiment 3 according to the present invention. Referring toFIG. 32B, the interlayer insulating layer170is formed on the entirety of the substrate shown inFIG. 31B, and patterning is performed as shown inFIG. 32Ato form the openings173and174. The opening173exposes a portion of the oxide semiconductor layer140that is located on the first insulating layer133, and the openings174each expose a portion of the oxide semiconductor layer140that is located on the second insulating layer134. Then, a film for the upper electrode180is formed on the entirety of the substrate shown inFIG. 32B, and patterning is performed to form the upper electrode180as shown inFIG. 28. In this manner, the semiconductor device32shown inFIG. 28is manufactured.

The present invention is not limited to any of the above-described embodiments, and the embodiments may be modified appropriately without departing from the gist of the present invention.