Non-volatile memory cell with enhanced filament formation characteristics

Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

BACKGROUND

Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices utilize a semiconductor array of solid-state memory cells to store individual bits of data. Such memory cells can be volatile (e.g., DRAM, SRAM) or non-volatile (RRAM, STRAM, flash, etc.).

As will be appreciated, volatile memory cells generally retain data stored in memory only so long as operational power continues to be supplied to the device, while non-volatile memory cells generally retain data storage in memory even in the absence of the application of operational power.

In these and other types of data storage devices, it is often desirable to increase efficiency and accuracy during operation, particularly with regard to the reading of data from the storage array.

SUMMARY

Various embodiments of the present invention are generally directed to a method and apparatus for constructing a non-volatile memory cell with improved filament formation characteristics, such as but not limited to a modified RRAM memory cell.

In accordance with various embodiments, a resistive storage layer is disposed between a first electrode layer and a second electrode layer. The resistive storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

In other embodiments, a memory cell is formed with a localized region of decreased thickness in a resistive storage layer that is positioned between a first electrode layer and a second electrode layer. The localized region of decreased thickness facilitates formation of a conductive filament through the storage layer from the first electrode to the second electrode.

These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1provides a functional block representation of a data storage device100constructed and operated in accordance with various embodiments of the present invention. The data storage device is contemplated as comprising a portable non-volatile memory storage device such as a PCMCIA card or USB-style external memory device. It will be appreciated, however, that such characterization of the device100is merely for purposes of illustrating a particular embodiment and is not limiting to the claimed subject matter.

Top level control of the device100is carried out by a suitable controller102, which may be a programmable or hardware based microcontroller. The controller102communicates with a host device via a controller interface (I/F) circuit104and a host I/F circuit106. Local storage of requisite commands, programming, operational data, etc. is provided via random access memory (RAM)108and read-only memory (ROM)110. A buffer112serves to temporarily store input write data from the host device and readback data pending transfer to the host device.

A memory space is shown at114to comprise a number of memory arrays116(denoted Array0-N), although it will be appreciated that a single array can be utilized as desired. Each array116comprises a block of semiconductor memory of selected storage capacity. Communications between the controller102and the memory space114are coordinated via a memory (MEM) I/F118. As desired, on-the-fly error detection and correction (EDC) encoding and decoding operations are carried out during data transfers by way of an EDC block120.

While not limiting, in some embodiments the various circuits depicted inFIG. 1are arranged as a single chip set formed on one or more semiconductor dies with suitable encapsulation, housing and interconnection features (not separately shown for purposes of clarity). Input power to operate the device is handled by a suitable power management circuit122and is supplied from a suitable source such as from a battery, AC power input, etc. Power can also be supplied to the device100directly from the host such as through the use of a USB-style interface, etc.

Any number of data storage and transfer protocols can be utilized, such as logical block addressing (LBAs) whereby data are arranged and stored in fixed-size blocks (such as 512 bytes of user data plus overhead bytes for ECC, sparing, header information, etc). Host commands can be issued in terms of LBAs, and the device100can carry out a corresponding LBA-to-PBA (physical block address) conversion to identify and service the associated locations at which the data are to be stored or retrieved.

FIG. 2provides a generalized representation of selected aspects of the memory space114ofFIG. 1. Data are stored as an arrangement of rows and columns of memory cells124, accessible by various row (word) and column (bit) lines. The actual configurations of the cells and the access lines thereto will depend on the requirements of a given application. Generally, however, it will be appreciated that the various control lines will generally include enable lines that selectively enable and disable the respective writing and reading of the value(s) of the individual cells.

Control logic126receives and transfers data, addressing information and control/status values along multi-line bus paths128,130and132, respectively. X and Y decoding circuitry134,136provide appropriate switching and other functions to access the appropriate cells124. A write circuit138represents circuitry elements that operate to carry out write operations to write data to the cells124, and a read circuit140correspondingly operates to obtain readback data from the cells124. Local buffering of transferred data and other values can be provided via one or more local registers144. At this point it will be appreciated that the circuitry ofFIG. 2is merely exemplary in nature, and any number of alternative configurations can readily be employed as desired depending on the requirements of a given application.

Data are written to the respective memory cells124as generally depicted inFIG. 3. Generally, a write power source146applies the necessary input (such as in the form of current, voltage, magnetization, etc.) to configure the memory cell124to a desired state. It can be appreciated thatFIG. 3is merely a representative illustration of a bit write operation. The configuration of the write power source146, memory cell124, and reference node148can be suitably manipulated to allow writing of a selected logic state to each cell.

As explained below, in some embodiments the memory cell124takes a modified RRAM configuration, in which case the write power source146is characterized as a current driver connected through a memory cell124to a suitable reference node148, such as ground. The write power source146provides a stream of power that is spin polarized by moving through a magnetic material in the memory cell124. The resulting rotation of the polarized spins creates a torque that changes the magnetic moment of the memory cell124.

Depending on the magnetic moment, the cell124may take either a relatively low resistance (RL) or a relatively high resistance (RH). While not limiting, exemplary RLvalues may be in the range of about 100 ohms (Ω) or so, whereas exemplary RHvalues may be in the range of about 100 KΩ or so Other resistive memory type configurations (e.g., RRAMs) are supplied with a suitable voltage or other input to similarly provide respective RLand RHvalues. These values are retained by the respective cells until such time that the state is changed by a subsequent write operation. While not limiting, in the present example it is contemplated that a high resistance value (RH) denotes storage of a logical 1 by the cell124, and a low resistance value (RL) denotes storage of a logical 0.

The logical bit value(s) stored by each cell124can be determined in a manner such as illustrated byFIG. 4. A read power source150applies an appropriate input (e.g., a selected read voltage) to the memory cell124. The amount of read current IRthat flows through the cell124will be a function of the resistance of the cell (RLor RH, respectively). The voltage drop across the memory cell (voltage VMC) is sensed via path152by the positive (+) input of a comparator (sense amplifier)154. A suitable reference (such as voltage reference VREF) is supplied to the negative (−) input of the comparator154from a reference source156.

The voltage reference VREFcan be selected from various embodiments such that the voltage drop VMCacross the memory cell124will be lower than the VREFvalue when the resistance of the cell is set to RL, and will be higher than the VREFvalue when the resistance of the cell is set to RH. In this way, the output voltage level of the comparator154will indicate the logical bit value (0 or 1) stored by the memory cell124.

FIG. 5generally illustrates a conventional filament-based memory cell157, which may be characterized as an RRAM cell as discussed above. A resistive storage layer158is disposed between a bottom electrode layer160and a top electrode layer162. The memory cell has a naturally high resistive value due to the composition and properties of the storage layer158, which can be an oxide (such as magnesium oxide, MgO) with normally high electrical resistance.

However, a low resistive value is created when a predetermined write voltage of selected polarity is applied across the cell157so that an amount of current passes through the storage layer158and one or more filaments164are formed therein to electrically interconnect the top electrode layer162and the bottom electrode layer160. The filament formation process will generally depend on the respective compositions of the layers, but generally, a filament such as164can be formed through the controlled metal migration (e.g., Ag, etc.) from a selected electrode layer into the oxide storage layer.

The subsequent application of a voltage of opposite polarity across the cell157will generally drive the metal from the storage layer157back into the associated electrode layer160or162, removing the filament164from the cell and returning the cell to the initial high resistance state. The reading of the filament-based cell157with distinctive high and low resistance states can be carried out as described byFIG. 4.

A memory cell157A constructed and operated in accordance with various embodiments of the present invention is shown inFIG. 6. The memory cell157A is generally similar in overall construction and operation to the memory cell157ofFIG. 6, except as detailed below.

Generally, the memory cell157A has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer. A resistive storage layer158is disposed between a bottom electrode layer160and a top electrode layer162. The localized area of decreased thickness is denoted at166and effectively shortens the length of any filament that forms to connect the electrode layers160and162. The shortened filament requirement allows for smaller required write current as well as optimized power consumption during read operations.

It will be appreciated that the decreased thickness166of the intermediate storage area158corresponds to localized increases in the associated thicknesses (projections) of the electrode layers160and/or162. With a predetermined amount of current flowing through the cell, a filament164has electrically connected the top electrode layer162with the bottom electrode layer160and effectively lowered the resistance of the memory cell in the process.

It should be noted that the layers and connections shown herein do not denote the only possible formations capable of operating in accordance with the embodiments of the present invention. In fact, the various layers can be limited to predetermined areas or not extend the complete dimensions of the memory cell. In configuring a given cell with a reduced storage layer thickness as discussed herein, it may be desirable to ensure that the cell retains adequate high electrical resistance in the non-filament state sufficient to provide low leakage current and reliable resistance sensing levels are obtained.

A cross-sectional view of an alternative memory cell structure157B is shown inFIG. 7A. The structure157B is generally similar to the structure157A and similar reference numerals are used for both structures. A top plan view of the bottom electrode layer160ofFIG. 7Ais shown inFIG. 7B.

FIG. 7Cprovides a cross-sectional view of an alternative memory cell structure157B. The structure157C is generally similar to the structure157A and similar reference numerals are used for both structures. InFIG. 7C, a plurality of reduced thickness areas166A in storage layer158are formed between respective pairs of opposing projections166B,166C in respective electrode layers160,162. A top plan view of the bottom electrode layer160is shown inFIG. 7Dto denote one possible pattern of said projections166B. It is contemplated that filaments may be formed between all or less than all of the respective sets of projections in a given write operation.

In other embodiments, different localized thicknesses of the storage layer158can be used as desired, such as but not limited to, greater thicknesses in one area (such as in a medial extent of the cell) and lesser thicknesses in other areas (such as near a boundary of the cell). Other alternative configurations will readily occur to the skilled artisan in view of the present discussion.

Another alternative memory cell structure is generally represented at157D inFIG. 8. A resistive storage layer158is disposed between two sides of a bottom electrode layer160A and160B. The structure157D is generally similar to the structure157A and similar reference numerals are used for both structures. The electrode layers are configured to provide a localized region of decreased connection length167that shortens the required length a filament164needed to connect the electrode layers. The localized region of decreased connection length167is adjacent to the sides of the bottom electrode layer160A and160B as well as an insulating layer168.

Furthermore, the insulating layer168extends below the electrode layer160A and160B as shown by the cross-sectional view ofFIG. 9. The filament164is optimally formed in the localized region of decreased connection length167of the resistive storage layer158, as shown. The existence of an electrical path from one side of the bottom electrode layer160A to the opposing side of the bottom electrode layer160B creates a low resistance value for the memory cell that can be read as a logical state by a read operation ofFIG. 4.

A manufacturing procedure to form a memory cell operated in accordance with the various embodiments of the present invention is generally illustrated inFIGS. 10A-10F. Initially, a bottom electrode layer160is formed and a predetermined amount of hard mask material174is formed at a predetermined location on the electrode layer, as shown inFIG. 10A. It can be appreciated that the hard mask material174can comprise a variety of compositions and physical configurations. The hard mask material174can include, but is not limited to, a diamond-like carbon. In addition, the hard mask material174can be formed anywhere on the bottom electrode layer160and does not necessarily have to extend to any outside dimension of the electrode layer.

FIG. 10Bdisplays the bottom electrode layer160after undergoing an ion milling process to shape one half of a localized region of decreased thickness166. Alternatively, ion milling can be substituted for reactive ion beam etching (RIBE) or inductively coupled plasma (ICP) etching to create a predetermined shape of the localized region of decreased thickness166. In addition, various shapes can be milled or etched to create a localized region of decreased thickness including, but not limited to, intersecting lines, curvilinear lines, and conical dimensions.

FIG. 10Cshows the deposition of the resistive storage layer158adjacent to the bottom electrode layer160. Subsequently, a second hard mask layer176is deposited onto the resistive storage layer158. Both the resistive storage layer158and the second hard mask layer176take the shape of the bottom electrode layer160.

A second ion milling operation is performed on the second hard mask layer176to at least partially expose a portion of the resistive storage layer158is displayed inFIG. 10D. In some embodiments, the exposed section of the resistive storage layer158is the area with the largest elevation. Further in some embodiments, the entire second hard mask layer176is milled or etched to a reduced thickness.

FIG. 10Eshows a third ion milling operation to create a localized area of decreased thickness166in the resistive storage layer158. The ion milling operation can be substituted for RIBE or ICP etching to remove sections of the second hard mask layer176and resistive storage layer158. While the third ion milling procedure can form a shape of the localized region of decreased thickness that mirrors the bottom electrode layer160, a unique shape can alternatively be milled or etched in the resistive storage layer158.

FIG. 10Fdisplays a completed memory cell157D after the deposition of a top electrode layer162adjacent to the second hard mask layer176and the resistive storage layer158. Further when a predetermined amount of current is applied to the memory cell, a filament164forms to connect the top electrode layer162to the bottom electrode layer160and provide a low resistance state.

A flow diagram of a forming operation180performed in accordance with the various embodiments of the present invention is shown inFIG. 11. A hard mask is first patterned on the bottom electrode layer160at step182. The deposited hard mask is then milled to a predetermined shape that becomes part of the bottom electrode layer in step184. In step186, the resistive storage layer158is deposited adjacent to the bottom electrode layer160. Further, a second hard mask layer176is deposited onto the resistive storage layer158at step188. The second hard mask layer176and resistive storage layer158undergo a milling operation to form a localized region of decreased thickness166in the resistive storage layer158at step190. Finally at step192, the top electrode layer162is deposited adjacent to the second hard mask layer176and the resistive storage layer158to form a shortened distance from the top electrode layer162to the bottom electrode layer160.

As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantages in both memory cell efficiency and complexity. The ability to use smaller write currents and/or write voltages can provide reduced overall power consumption for an array of memory cells. Moreover, the simplicity of manufacturing operations for the embodiments of the present invention allows for improved memory device structure with decreased numbers of errors. However, it will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.