Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer

Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

CLAIM OF PRIORITY

This application claims priority from Korean Patent Application No. 2003-081078, filed on Nov. 17, 2003, in the Korean Intellectual Property Office, the contents of which are hereby incorporated by reference in their entirety as if set forth fully herein.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods of fabricating the same, and specifically, to semiconductor devices with a source/drain formed on an isolation layer and methods of fabricating the same.

BACKGROUND OF THE INVENTION

Integrated circuit semiconductor devices may include combinations of transistors having differing characteristics to satisfy a user's particular application. The transistors typically have differing characteristics depending on their function and may be formed in several structures to provide the desired characteristic.

As a particular example, to provide high-integration memory cell arrays, the dimensions of transistors have been reduced. As transistors become smaller, short-channel effects (e.g., a sub-threshold swing or punch-through) may become more frequent or problematic. In order to reduce or prevent punch-through caused by an extension of a depletion region and/or leakage current through the source/drain junction of transistors, transistors on SOI (Silicon-On-Insulator) substrates have been suggested.

FIG. 1is a cross-sectional view showing a structure of a conventional transistor formed on an SOI (Silicon-On-Insulator) substrate. Referring toFIG. 1, the SOI substrate includes a silicon substrate10, a buried oxide14on the silicon substrate10and an SOI layer16formed on the buried oxide14. A gate pattern18is formed over the SOI layer16, and source/drain region20is formed in the SOI layer16at both sides of the gate pattern18. If the junction depth of the source/drain region20and the thickness of the SOI layer16are adequately controlled, the source/drain region20is isolated in the SOI layer16. As shown inFIG. 1, because the junction of the source/drain20is in contact with the buried oxide14, it is possible to isolate a leakage current path and to reduce or even prevent a depletion region from being extended. In addition, a transistor may be fully isolated by the buried oxide14and a device isolation layer, which may reduce the occurrence of or even prevent latch-up in a CMOS structure.

However, in the conventional transistor structure formed on the SOI substrate as illustrated inFIG. 1, it may be difficult to disperse Joule heating generated by drain voltage and current. Furthermore, it may also be difficult to reduce floating body effect where a threshold voltage of the transistor varies as a result of the storage of charge in an isolated SOI layer. These problems may result in the transistor not operating as desired or suffering physical damage.

SUMMARY OF THE INVENTION

Some embodiments of the present invention provide semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

In further embodiments of the present invention, the active region of the substrate has a sidewall that protrudes beyond a top surface of a portion of the device isolation layer adjacent the active region.

In some embodiments of the present invention, the source/drain regions are provided on the active region and the device isolation layer such that an area of a portion of the source/drain regions on the device isolation layer is greater than an area of a portion of the source/drain regions on the active region. In further embodiments of the present invention, the source/drain regions are provided only on the device isolation layer. The source/drain regions may also be provided on the active region and the device isolation layer such that an area of a portion of the source/drain regions on the device isolation layer is smaller than an area of a portion of the source/drain regions on the active region.

In additional embodiments of the present invention, the active region includes an upper portion and a lower portion. A width of the upper portion is less than a width of the lower portion such that the active region has stepped sidewalls. The active region may also include an upper portion and a lower portion that provide a hetero-junction therebetween. The device isolation layer may extend onto the lower portion of the active region to a sidewall of the upper portion of the active region. The sidewall of the upper portion of the active region may protrude beyond a top surface of the device isolation layer adjacent the upper portion of the active region.

In still other embodiments of the present invention, semiconductor devices and methods of fabrication of semiconductor devices include a substrate having first and second regions, a first device isolation layer on the substrate that defines a first active region in the first region and has a vertically protruding portion, a second device isolation layer on the substrate that defines a second active region in the second region and has a vertically protruding portion, a first epitaxial layer on the first active region and the first device isolation layer and that is spaced apart from a sidewall of the vertically protruding portion of the first device isolation layer, a second epitaxial layer on the second active region and the second device isolation layer and that is spaced apart from a sidewall of the vertically protruding portion of the first device isolation layer, a first gate pattern disposed to cross over the first epitaxial layer at the first region, a second gate pattern disposed to cross over the second epitaxial layer at the second region, first source and drain regions in the first epitaxial layer at opposite sides of the first gate pattern on the first device isolation layer adjacent to the first active region and second source and drain regions in the second epitaxial layer at opposite sides of the second gate pattern and that extend over the second active region and the second device isolation layer adjacent to the second active region are provided. An area of portions of the second source and drain regions on the second active region is greater than an area of portions of the second source and drain regions on the second device isolation layer. In certain embodiments of the present invention, the first source and drain regions are provided only on the first device isolation layer.

In additional embodiments of the present invention, the first and second active regions of the substrate have sidewalls that protrude beyond a top surface of a portion of the respective first and second device isolation layer adjacent the first and second active regions. The first source and the first drain regions may be provided on the first active region and the first device isolation layer such that an area of a portion of the first source and drain regions on the first device isolation layer is greater than an area of a portion of the first source and drain regions on the first active region.

In still further embodiments of the present invention, the first and second active regions each include an upper portion and a lower portion. A width of the upper portion is less than a width of the lower portion Such that the first and second active regions have stepped sidewalls. The upper portion and the lower portion may provide a hetero-junction therebetween. The first and second device isolation layers may extend onto the lower portion of the respective first and second active regions to a sidewall of the upper portion of the first and second active regions. The sidewalls of the upper portion of the first and second active regions may protrude beyond a top surface of the respective first and second device isolation layers adjacent the upper portion of the first and second active regions.

In yet additional embodiments of the present invention, semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer extends beyond a surface of the substrate and has a recess adjacent the active region that extends to a depth greater than a distance that the device isolation layer extends beyond the surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extending onto the recess in the device isolation layer, the epitaxial layer being spaced apart from at least a portion of a sidewall of the recess. A gate pattern is provided on the epitaxial layer. A source region and a drain region are provided in the epitaxial layer at opposite sides of the gate pattern.

In some embodiment of the present invention, the gate pattern is substantially a same width as the active region. In further embodiments of the present invention, the source region and the drain region are provided in portions of the epitaxial layer on the device isolation layer. The source and drain regions may be provided only in portions of the epitaxial layer on the device isolation layer. Portions of the source region and the drain region may be provided in portions of the epitaxial layer on the active region of the substrate. The portions of the source region and the drain region provided in portions of the epitaxial layer on the active region may have a smaller area than portions of the source region and the drain region provided in portions of the epitaxial layer on the device isolation layer. The portions of the source region and the drain region provided in portions of the epitaxial layer on the active region may have a larger area than portions of the source region and the drain region provided in portions of the epitaxial layer on the device isolation layer.

In additional embodiments of the present invention, the active region includes an upper portion and a lower portion. The upper portion and the lower portion may be different semiconductor materials and provide a heterojunction. The upper portion may have a smaller dimension than the lower portion so as to provide a step between a sidewall of the lower portion and a sidewall of the upper portion. The device isolation layer may extend onto the step of the lower portion to the sidewall of the upper portion. The source and drain regions may extend into the upper portion of the active region.

In further embodiments of the present invention, the epitaxial layer has a thickness and wherein the epitaxial layer extends laterally onto the recess a distance corresponding to the thickness of the epitaxial layer.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.

FIG. 2is a cross-sectional view illustrating semiconductor devices according to some embodiments of the present invention. Referring toFIG. 2, the semiconductor device includes first and second regions A and B where transistors with different driving characteristics are provided. Transistors for which short-channel effect is a concern are formed in the first region A. For example, region A may correspond to a cell array region of a memory device. In the second region B, transistors having relatively large dimensions and high driving capacity may be provided. In the second region B, transistors may be provided where Joule heating dispersion and floating-body effect may be concerns, rather than short-channel effects. For example, a high voltage or high current driving transistor of a memory device and/or a high-frequency and/or power transistor of a logic circuit may be formed in the second region B.

A device isolation layer54is formed on a semiconductor substrate50to define a first active region53ain the first region A. The device isolation layer54has a protruding portion having a sidewall54sand that extends vertically beyond a first surface53sof the first active region53aand provides a recess adjacent the first active region53a. An epitaxial layer56is formed on the first surface53sof the first active region53a. The epitaxial layer56has a portion that extend from the first active region53aonto the device isolation layer54. A sidewall of the epitaxial layer56is spaced a distance D from the sidewall54sof the protruding portion of the device isolation layer54. In particular embodiments of the present invention, the distance D is sufficiently large so as to reduce and/or minimize stress caused by the formation of the epitaxial layer56on the device isolation layer54. The distance D should also be large enough to provide isolation of the epitaxial layer from the sidewall54sof the device isolation layer54, for example, taking into account manufacturing tolerances. However, in some embodiments of the present invention, the distance D is not so large as to significantly increase the overall size of the devices.

A first gate pattern58ais disposed crossing over the epitaxial layer56. A first source/drain region60ais formed in the epitaxial layer56at both sides of the first gate pattern58a. In order to reduce or even minimize punch-through due to extension of a depletion region of the first source/drain60aand junction leakage current, in some embodiments of the present invention, the lower junction of the first source/drain60acontacts only the device isolation layer54. Accordingly, in some embodiments of the present invention, the width of the first gate pattern58ais the same as or wider than that of the first active region53a.

In embodiments of the present invention where the lower junction of the first source/drain60acontacts the active region53aand the device isolation layer54, the first source/drain60amay still suppress punch-through resulting from an extension of a depletion region. For example, punch-through may still be suppressed if the dimension of the portion of the first source/drain60aon the device isolation layer54is larger than the dimension of portion of the first source/drain60aon the first active region53a. In this case, a part of the first source/drain60amay be formed on the first active region53aand the first active region53ahas a sidewall that extends past a top surface of the device isolation layer54adjacent the first active region53a. Because the epitaxial layer56is grown on a sidewall of the first active region53a, the thickness of the epitaxial layer56may be uniform vertically and laterally. If the epitaxial layer56is in contact with the sidewall54sof the protruding portion of the device isolation layer54, a defect due to stress may arise near the contact portion. As a result, this may induce leakage current in the transistor. Therefore, in some embodiments of the present invention, the sidewall of the epitaxial layer56is spaced apart a distance D from the protruding sidewall54sof the isolation layer54.

As is further illustrated inFIG. 2, a transistor may also be formed in a wide active region of the second region B. Accordingly, transistors having a relatively high current driving capacity may be formed on the second region B. A device isolation layer54is formed on the second region B to define a second active region53b. The device isolation layer54has a protruding portion that extends vertically beyond a first surface53tof the second active region53band provides a recess adjacent the first active region53b. An epitaxial layer56is formed on the first surface53tof the second active region53b. The epitaxial layer56has a portion that extends onto the device isolation layer54that defines the second active region53b. A sidewall of the epitaxial layer56is spaced a distance D apart from a vertical sidewall54sof the vertically protruding portion of the device isolation layer54. A second gate pattern58bis formed on the epitaxial layer56, and a second source/drain60bis formed in the epitaxial layer56at both sides of the second gate pattern58b.

To efficiently disperse Joule heating generated in operating a transistor, in some embodiments of the present invention, the second active region53bis wider than a channel of the transistor. Accordingly, in some embodiments of the present invention, the dimension of the second active region53bis larger than that of the second gate pattern58b. Furthermore, a part of the second source/drain60bmay be formed in the second active region53b.

FIGS. 3 to 8are cross-sectional views illustrating methods of fabricating semiconductor devices according to some embodiments of the present invention. Referring toFIG. 3, first and second mask patterns52aand52bare formed on first and second regions A and B, respectively, of the substrate50. The first and second mask patterns52aand52bmay include silicon nitride.

Referring toFIG. 4, trenches respectively defining the first and second active regions53aand53bon the first and second regions A and B are formed using the first and second mask patterns52aand52bas etching masks. An insulation layer is formed in the trenches to form device isolation layers54in the first and second regions A and B. The device isolation layers54may be formed in, and in some embodiments, to fill the trenches. In some embodiments, the device isolation layers54are formed after a thermal oxide and a silicon nitride liner are formed on inner walls of the trenches. The device isolation layers54have an upper sidewall in contact with the first and second mask patterns52aand52b.

Referring toFIG. 5, the first and second mask patterns52aand52bare removed. The device isolation layers54may have an upper sidewall54sthat protrudes from the top surface of the substrate50. The upper sidewall54sof the device isolation layers54may be recessed laterally during a sacrificial oxidation process or a cleaning process.

Referring toFIG. 6, the device isolation layers54sare recessed to partially expose a portion of the sidewalls of the first and second active regions53aand53b. The device isolation layers54may be recessed using an isotropic etching process. The protruding sidewall54sis laterally recessed to provide a space between boundaries of the active region and the protruding sidewall54of the device isolation layer.

Referring toFIG. 7, epitaxial layers56are formed on the first and second active regions53aand53busing a selective epitaxial growth method. The epitaxial layers56are grown upward and laterally on the first and second active regions53aand53b. The epitaxial layers56extend laterally to an upper portion of the isolation layers54adjacent the active regions53aand53b. Thus, the epitaxial layers56grown in the direction of the protruding sidewalls54sof the device isolation layers54. If a growth interface of an epitaxial layer56is in contact with a protruding sidewall54sof the device isolation layer54, a defect due to compressive stress may result. Accordingly, in some embodiments of the present invention, the epitaxial layer is spaced apart from the protruding sidewall54s, for example, a distance D may be provided between the protruding sidewall54sof the device isolation layer54and the epitaxial layer56.

In some embodiments, a ratio of the dimension of the portion of the epitaxial layer that extends onto the isolation layer and the total dimension of the epitaxial layer is inverse to the dimension of an active region. Therefore, the desired characteristics and, therefore, the dimensions, of a transistor should be taken into account in defining a location of the first and second active regions53aand53b. In other words, an active region with a small dimension may be defined in a region where transistors requiring the suppression of short-channel effect will be formed. An active region with a large dimension may be defined in a region where transistors requiring Joule heating dispersion and suppression of floating-body effect will be formed.

Referring toFIG. 8, a first gate pattern58acrossing over an epitaxial layer56of the first region A is formed, and a second gate pattern58bcrossing over an epitaxial layer56of the second region B is formed. In some embodiments, the width of the first gate pattern58ais the same as or wider than that of the first active region53a. The width of the second gate pattern58bmay be narrower than that of the second active region53b. The width of gate patterns is closely related with characteristics of the transistor. Accordingly, the first active region53amay be defined narrower than the first gate pattern58a, and the second active region53bmay be defined wider than the second gate pattern58b.

Impurities are implanted into epitaxial layer56on both sides of the first and second gate patterns58aand58bto form first and second source/drains (see60aand60binFIG. 2). To suppress short-channel effects, in some embodiments of the present invention, a lower junction of the first source/drain (see60binFIG. 2) only contacts the device isolation layer54, and/or a region of the first source/drain on the device isolation layer54is wider than a region of the first source/drain on the first active region53a. In addition, in some embodiments, to improve Joule heat dispersion and suppress floating-body effect, an upper region of second source/drain on the second active region53bis wider than the region of the second source/drain on the device isolation layer54(see60binFIG. 2).

Operational characteristics of transistors typically depend on dimensions of the source/drain regions and the width and length of the gate pattern. Accordingly, in view of the dimensions of the source/drain regions and the width and length of the gate pattern, the dimensions of the first and second active regions53aand53band the dimensions of the extension of the epitaxial layer56onto the device isolation layer54can be defined. As a result, it is possible to respectively control a ratio of a region of the first and second source/drains (see60aand60binFIG. 2) on the device isolation layer54.

FIG. 9is a cross-sectional view illustrating semiconductor devices according to further embodiments of the present invention. Referring toFIG. 9, semiconductor devices according to further embodiments of the present invention may include first and second regions A and B, at which transistors with different driving characteristics may be formed. In the first region A, transistors that may be affected by short-channel effects may be formed. For example, a cell array region of a memory device may correspond to the first region A. In the second region B, transistors having a relatively high current driving capacity may be formed. In this case, the transistors may be affected by Joule heat dispersion and floating-body effects rather than short-channel effects. For example, a high-voltage or current driving transistor of the memory device or a high-frequency or power transistor of a logic circuit may be formed on the second region B.

A device isolation layer74is formed on a semiconductor substrate70to respectively define first and second active regions73aand73bon the first and second regions A and B. The first and second active regions73aand73bhave stepped sidewalls at which the width of the upper portion is narrower than that of the lower portion. If upper and lower portions of the first and second active regions73aand73bare formed with different semiconductors, the stepped sidewalls may be formed in a fabricating process for the different semiconductors. For example, lower portions of the first and second active regions73aand73bmay be a silicon substrate70, and upper portions of the first and second active regions73aand73bmay be silicon-germanium71. Accordingly, the first and second active regions73aand73bare divided into an upper portion and a lower portion having a hetero-junction.

The device isolation layer74has a protruding portion that extends vertically past the top surface of the first and second active regions73aand73band provides a recess adjacent the first and second active regions73aand73b. The sidewall of the device isolation layer74extends along a sidewall of the active region and is in contact with an upper sidewall71sof the respective active regions73aand73b.

Epitaxial layers76are formed on the first and second active regions73aand73b. The epitaxial layers76have a portion extended onto an upper portion of the adjacent device isolation layer74. First and second gate patterns78aand78bare disposed crossing over the respective epitaxial layers76on the first and second regions A and B. A first source/drain80ais formed in the epitaxial layer76at both sides of the first gate pattern78aand a second source/drain80bis formed in the epitaxial layer76at both sides of the second gate pattern78b.

To reduce or even minimize junction leakage current of the first source/drain80aand punch-through by an extension of a depletion region, in some embodiments of the present invention, a lower junction of the first source/drain80acontacts only the device isolation layer74. Therefore, the width of the first gate pattern78amay be the same as or wider than that of the first active region73a. However, in some embodiments of the present invention where the lower junction of the first source/drain80acontacts more than the device isolation layer74, the first source/drain80acan sufficiently suppress punch-through due to an extension of an extension of depletion region and leakage current by the dimension of the portion of the first source/drain80aon the device isolation layer74being larger than the dimensions of the portion of the first source/drain80aon the first active region73a. In this case, a part of the first source/drain80amay be formed in the semiconductor layer71of the first active region73a.

To efficiently disperse Joule heat generated in operating a transistor, in some embodiments of the present invention, the second active region73bmay be wider than a channel of the transistor. Accordingly, the dimensions of the second active region73bmay be larger than that of the second source/drain80b. A part of the second source/drain80bmay be formed in the semiconductor layer71of the second active region73b.

The first and second active regions73aand73bmay have an upper sidewall protruding from the adjacent device isolation layer74. Because the epitaxial layer76is grown on the protruding sidewall, its thickness may be uniform vertically and laterally. If the epitaxial layer76is in contact with the vertically protruding sidewall of the device isolation layer, a defect due to stress may arise near the contact portion. As a result, this may induce leakage current in the transistor. Therefore, in some embodiments of the present invention, the sidewall of the epitaxial layer76is isolated at a distance D′ from the vertically protruding sidewall74sof the adjacent isolation layer74.

FIGS. 10 to 15are cross-sectional views illustrating methods of fabricating semiconductor devices according to further embodiments of the present invention. Referring toFIG. 10, a semiconductor layer71having an etch selectivity with respect to a substrate70is formed. First and second regions A and B are defined on the substrate70. First and second mask patterns72aand72bare formed on the semiconductor layer71. The first and second mask patterns72aand72bmay include silicon nitride. The semiconductor substrate70may be a silicon substrate. The semiconductor layer71has an etch selectivity with respect to silicon and, for example, may be formed of silicon-germanium. Silicon-germanium has a high etch rate in comparison with silicon in an isotropic or anisotropic etching process.

Referring toFIG. 11, trenches that respectively define the first and second active regions73aand73bon the first and second regions A and B are formed using the first and second mask patterns72aand72bas an etching mask. While the trench is formed, sidewalls71sbecome recessed. As a result, the trench has an under-cut region under the first and second mask patterns72aand72b. Accordingly, the first and second active regions73aand73bare divided into an upper portion and a lower portion, and have stepped sidewalls at the heterojunction between the substrate70and the semiconductor layer71. An insulation layer is provided in the trench and, in some embodiments, fills the trench to form device isolation layers74on the first and second regions A and B. The device isolation layers74may be formed by filling the trench with an insulation layer after a thermal oxide layer and a silicon nitride liner are formed in the trench. The device isolation layers74extend into and, in some embodiments, fill in the under-cut region located under the first and second mask patterns72aand72b. As a result, the device isolation layers74have upper sidewalls whose shape is along the upper sidewalls of the mask patterns72aand72band the active regions73aand73b.

Referring toFIG. 12, the first and second mask patterns72aand72bare removed. An upper sidewall74sof the device isolation layers74protrudes from the semiconductor layer71. The upper sidewall74sof the device isolation layers74may be recessed laterally by a sacrificial oxidation and/or cleaning processes. Because the under-cut region is formed under the first and second mask patterns72aand72b, an upper portion of the device isolation layer74can be divided into a horizontal portion corresponding to the portion extending into the undercut and a vertical portion corresponding to the portion that protrudes vertically.

Referring toFIG. 13, a part of the sidewalls of the first and second active regions73aand73bmay be further exposed by recessing the device isolation layers74. The device isolation layers74may be recessed by an isotropic etch process. The protruding sidewall74sis recessed laterally so that a predetermined distance is provided at the boundaries of the active regions73aand73band the protruding sidewalls74sof the device isolation layers74.

Referring toFIG. 14, an epitaxial layer76is grown on the first and second active regions73aand73busing a selective epitaxial growth method. The epitaxial layer76may be grown vertically and laterally on the first and second active regions73aand73b. The epitaxial layer76is grown laterally to extend onto an upper portion of the adjacent device isolation layer74. If a growth portion of the epitaxial layer is in contact with the vertically protruding sidewall74sof the device isolation layer, a defect may result from compressive stress. Accordingly, in some embodiments of the present invention, the sidewall74sof the vertically protruding portion of the device isolation layer74is spaced apart a distance D′ from the epitaxial layer76.

In particular embodiments of the present invention, the distance D′ is sufficiently large so as to reduce and/or minimize stress caused by the formation of the epitaxial layer76on the device isolation layer74. The distance D′ should also be large enough to provide isolation of the epitaxial layer from the sidewall74sof the device isolation layer74, for example, taking into account manufacturing tolerances. However, in some embodiments of the present invention, the distance D′ is not so large as to significantly increase the overall size of the devices.

In some embodiments, a ratio of the dimension of the portion of the epitaxial layer that extends onto the isolation layer and the total dimension of the epitaxial layer is inverse to the dimension of an active region. Therefore, the desired characteristics and, therefore, the dimensions, of a transistor should be taken into account in defining a location of the first and second active regions73aand73b. In other words, an active region with a small dimension may be defined in a region where transistors requiring the suppression of short-channel effect will be formed. An active region with a large dimension may be defined in a region where transistors requiring Joule heating dispersion and suppression of floating-body effect will be formed.

Referring toFIG. 15, a first gate pattern78acrossing over an epitaxial layer76of the first region A is formed, and a second gate pattern78bcrossing over an epitaxial layer76of the second region B is formed. In some embodiments of the present invention, the width of the first gate pattern78ais the same as or wider than that of the first active region73a. The width of the second gate pattern78bmay be narrower than that of the second active region73b. The width of the gate patterns78aand78bmay be closely related to characteristics of the transistors. Accordingly, to provide the desired characteristics of the transistors, the width of the gate patterns78aand78bmay be established and the first active region73amay be defined narrower than the first gate pattern78aand the second active region73bmay be defined wider than the second gate pattern78b.

Impurities are implanted into the epitaxial layer76adjacent the first and second gate patterns78aand78bto form first and second source/drains (see80aand80binFIG. 9). To suppress short-channel effect, in some embodiments of the present invention, the lower junction of the first source/drain (see80binFIG. 9) contacts only the device isolation layer74or a portion of the first source/drain that contacts a region on the device isolation layer74that is wider than the portion of the first source/drain that contacts an upper region of the first active region73a. In addition, to improve Joule heat dispersion and/or suppress floating-body effect, in some embodiments of the present invention, the portion of the second source/drain that contacts the upper region of the second active region73bis wider than the portion of the second source/drain that contacts the device isolation layer74(see80binFIG. 9).

Operational characteristics of the transistors may depend on dimensions of the source/drain and the width and length of the gate pattern. Accordingly, to provide transistors with the desired characteristics, the dimensions of the source/drain and the width and length of the gate pattern may be established and the dimensions of the first and second active regions73aand73band the extension of the epitaxial layer76onto the device isolation layer74defined to provide such dimensions. As a result, it is possible to respectively control a ratio of the portion of the first and second source/drains (see80aand70binFIG. 9) on the device isolation layer74to the total size of the first and second source/drains to provide transistors having particular desired characteristics.

As previously mentioned, in some embodiments of the present invention, an epitaxial layer extends onto an upper portion of a device isolation layer on an active region. Source/drain regions are formed on the epitaxial layer over the device isolation layer. As a result, in some embodiments of the present invention, it may be possible to reduce or suppress short-channel effects. Furthermore, according to some embodiments of the present invention, in a transistor with high current driving capacity, Joule heat dispersion may be improved and floating-body effect may be reduced or suppressed. In a transistor requiring suppression of short-channel effects, it may be possible to suppress short-channel effects as well as Joule heating dispersion and/or floating-body effect at the same time.

Furthermore, suppressing short-channel effects, improving Joule heat dispersion and floating-body effects may be adequately controlled depending on a size of a transistor. A ratio of an dimension of an epitaxial layer and a portion of the epitaxial layer on a device isolation layer may be inversely related to the width of an active region. Accordingly, it may be possible to suppress short-channel effects, improve Joule heat dispersion and/or suppress floating-body effects in a transistor with high current driving capacity.

While embodiments of the present invention have been described with reference to two different sizes of active regions, as will be appreciated by those of skill in the art, each of the different size active regions may be provided individually or with other size active regions. Accordingly, embodiments of the present invention may provide combination and/or sub-combinations of devices as illustrated inFIGS. 1 through 15.