BATTERY BALANCING FOR MULTI-BATTERY SYSTEMS

A closed loop control system actively regulates the battery current paths of physically separated circuits so that the current is approximately the same for each of the circuits regardless of the various system loads. The closed loop control system modulates the current paths by either modulating a high side transistor used to independently limit each battery's current path or by modulating a DC/DC converter's output voltage to independently boost each battery's current path. The closed loop control system is also designed to handle undervoltage lockout (UVLO) situations when one of the batteries is nearing empty to tilt the power balance in the chance that there is an existing battery charge mismatch to support system load bursts and to turn off the circuit when the system current draw is exceptionally low. A tilting circuit also identifies and discharges the battery with the higher charge until the charge states are substantially equal.

TECHNICAL FIELD

Examples set forth herein generally relate to battery systems for mobile electronic devices and, in particular, to a battery balancing system for balancing charging and discharging of multi-battery systems in mobile electronic devices.

BACKGROUND

Mobile electronic devices such as electronic eyewear devices may have electronics disposed in physically separated portions of the devices. For example, electronic eyewear devices may have electronics, such as circuit boards and batteries, disposed in the temples or arms of the electronic eyewear devices. In such cases, the electronics and batteries in the temples or arms are physically separated by the front eyeglass frame and may charge/discharge at different rates, which may cause potential issues with battery health, reliability, and safety.

DETAILED DESCRIPTION

The circuits in mobile devices may have varying loads that are powered by different batteries operating independently even though the circuits are part of the same system providing various functionality for the mobile devices. For example, a main processor may be disposed on one side of an electronic eyewear device and consume power according to its load, while a co-processor may be disposed on the other side of the electronic eyewear device and turn on/off independently. Also, because of the electrical resistance separating the left and right sides of the electronic eyewear device, the current supplied by the batteries on the respective sides of the eyewear may vary. This arrangement poses a problem as it is desired to charge and discharge the batteries for the physically displaced electronics in the mobile electronic devices substantially equally to avoid potential issues with battery health, reliability, and safety. Also, while short-term mismatch or a slight mismatch may be acceptable, long-term mismatch and gross errors are not acceptable.

Mobile electronic devices such as electronic eyewear devices may use multiple boards and batteries in various parts of the device in order to optimize for space, heat dissipation, and the like. To ensure good battery health, it is desired to charge and discharge all the batteries used in such devices at substantially the same rate. This becomes challenging because the system loads change dynamically and can become unbalanced, coupled with the added resistance from being physically separated. The circuits described herein measure and modulate the individual battery current paths in order to actively balance their discharge currents.

The circuits described herein measure the high side currents of the batteries and feed the measured currents into a closed loop control system. The closed loop control system actively regulates the battery current paths of the physically separated circuits so that the currents are approximately the same for each of the circuits regardless of the various system loads. The closed loop control system modulates the current paths by either modulating a high side transistor used to independently limit each battery's current path or by modulating a DC/DC converter's output voltage to independently boost the voltage in each battery's current path. The closed loop control system is also designed to prevent undervoltage lockout (UVLO) situations when one of the batteries is nearing empty, to adjust the power balance when there is an existing battery charge mismatch, and to turn off the circuit when the system current draw is exceptionally low. A tilting circuit also may identify and discharge the battery with the higher charge until the charge states of the batteries are substantially equal.

The methods and systems described herein thus relate to a device including physically separated circuits where each circuit includes a battery, a load, and a resistance along the current path to the load. The device (e.g., an electronic eyewear device with circuitry in respective arms or temples separated by the frame) includes a battery balancing control loop that balances charges of the batteries of each circuit. The battery balancing control loop includes current measuring circuits (e.g., current sensing amplifiers) that measure the currents through the resistances of the circuits, at least one differential amplifier that compares the measured currents to generate an adjustment signal, and current modulating means for modulating the current in the current paths between the batteries and the loads in response to the adjustment signal. The current modulating means modulates a first current in a first current path of a first circuit by at least one of (a) increasing a resistance or decreasing a battery voltage in the first current path or (b) boosting the battery voltage or decreasing the resistance in the first current path. The current modulating means may similarly modulate a second current in a second current path of a second circuit.

The current modulating means may include a transistor in the first current path of the first circuit that dynamically limits the first current in the first current path by adjusting the first resistance in the first current path in response to the adjustment signal until the first currents in the first current path and a second current in the second current path are approximately the same. Alternatively, the current modulating means may include a DC/DC converter responsive to the adjustment signal to increase current in the first current path to balance the first current and the second current. The battery balancing control loop may further include a tilting circuit that checks a charge state of the first and second batteries to determine a charge mismatch and discharges the battery with a higher charge until the charge state of the batteries are substantially equal. The tilting circuit may include a transistor in one or more of the current paths that, when activated, causes the current in the current path to appear smaller. The battery balancing control loop may also include an undervoltage lockout control loop that regulates a battery voltage of the circuits above an undervoltage lockout point. The undervoltage lockout control loop may include a comparator in each circuit that compares a voltage applied to the load to a reference voltage and, when the voltage applied to the load is below the reference voltage, the comparator triggers the current modulating means to override its current modulation and to add current to the current path.

A detailed description will now be provided with reference toFIGS.1-10. Although this description provides a detailed description of possible implementations, it should be noted that these details are intended to be exemplary and in no way delimit the scope of the inventive subject matter. For example, while the description below is with respect to physically separated circuits in the temples or arms of an electronic eyewear device, it will be appreciated that the circuits and techniques described herein may be applied to any electronic device with circuits having different battery sources.

In sample configurations, the power management system described herein may be used in mobile devices including physically separated circuits powered by different batteries.FIG.1Ais a block diagram of a mobile device having circuits110and120that are physically separated from each other and powered independently. By way of example,FIGS.1B and1Cillustrate an electronic eyewear device100having electronic circuits110and120in respective temples or arms thereof.

FIG.1Bis an illustration depicting a side view of an example hardware configuration of a mobile device in the form of an eyewear device100including an optical assembly130for each eye, each optical assembly including an image display135and a visible light camera140that together with a visible light camera for the other eye forms a stereo camera. The visible light camera140is located on a right temple150and a second visible light camera is located on a left temple of the eyewear device100. In the illustrated example, the optical assembly130is located on the right side of the eyewear device100. The optical assembly130also can be located on the left side or other locations of the eyewear devices100.

The visible light camera140of each optical assembly130may include an image sensor that is sensitive to the visible light range wavelength. Each of the visible light cameras140has a different frontward facing angle of coverage. The angle of coverage is an angle range in which the respective image sensors of the visible light cameras140detect incoming light and generate image data. Examples of such visible lights cameras140include a high-resolution complementary metal-oxide-semiconductor (CMOS) image sensor and a video graphic array (VGA) camera, such as 640p (e.g., 640×480 pixels for a total of 0.3 megapixels), 720p, 1080p, 4K, or 8K. Image sensor data from the visible light cameras140may be captured along with geolocation data, digitized by an image processor, and stored in a memory.

To provide stereoscopic vision, visible light cameras140may be coupled to an image processor (not shown) for digital processing and adding a timestamp corresponding to the scene in which the image is captured. The image processor may include circuitry to receive signals from the visible light cameras140and to process those signals from the visible light cameras140into a format suitable for storage in a memory. The timestamp may be added by the image processor or other processor that controls operation of the visible light cameras140. Visible light cameras140allow the stereo camera to simulate human binocular vision. Stereo cameras also provide the ability to reproduce three-dimensional images of a three-dimensional scene based on two captured images from the visible light cameras140, respectively, having the same timestamp. Such three-dimensional images allow for an immersive virtual experience that feels realistic, e.g., for virtual reality or video gaming. For stereoscopic vision, a pair of images may be generated at a given moment in time—one image for each of the visible light cameras140for each optical assembly130of each eye. When the pair of generated images from the frontward facing field of view (FOV) of the visible light cameras140are stitched together (e.g., by the image processor), depth perception is provided by the optical assemblies130for each eye.

In an example, the eyewear device100includes a frame160, a right rim170, a right temple150extending from a right lateral side180of the frame160, and a see-through image display135comprising optical assembly130to present a graphical user interface (GUI) or other image to a user. The eyewear device100includes the first visible light camera140connected to the frame160or the right temple150to capture a first image of the scene. Eyewear device100further includes a second visible light camera (not shown) connected to the frame160or a left temple (not shown) to capture (e.g., simultaneously with the first visible light camera140) a second image of the scene which at least partially overlaps the first image. Although not shown inFIG.1B, an image processor is coupled to the eyewear device100and is connected to the visible light cameras140and a memory accessible to the processor, and programming in the memory may be provided in the eyewear device100itself.

Although not shown inFIG.1B, the eyewear device100also may include a head movement tracker (element190ofFIG.1C) or an eye movement tracker (not shown). Execution of programming by the processor configures the eyewear device100to perform functions, including functions to present, via the see-through image display135, an initial displayed image of the sequence of displayed images, the initial displayed image having an initial field of view corresponding to an initial head direction or an initial eye gaze direction as determined by the eye movement tracker.

FIG.1Cis a top cross-sectional view of optical components and electronics in a portion of the eyewear device illustrated inFIG.1Bdepicting the first visible light camera140, a head movement tracker190, and a circuit board145. Construction and placement of the second visible light camera is substantially similar to the first visible light camera140, except the connections and coupling are on the other lateral side of the eyewear device100. As shown, the eyewear device100includes the first visible light camera140and a circuit board145, which may be a flexible printed circuit board. A hinge155connects the right temple150to a hinged arm165of the eyewear device100. In some examples, components of the first visible light camera140, the flexible PCB145, or other electrical connectors or contacts may be located on the right temple150or the hinge155.

As shown inFIG.1C, a right temple includes temple body175that is configured to receive a temple cap, with the temple cap omitted in the cross-section ofFIG.1C. Disposed inside the right temple150are various interconnected circuit boards, such as PCBs or flexible PCBs145, that include controller circuits for the visible light camera145, microphone(s)185, speaker(s)195, low-power wireless circuitry (e.g., for wireless short-range network communication via BLUETOOTH®), high-speed wireless circuitry (e.g., for wireless local area network communication via WI-FI®), and a power source.

The first visible light camera140is coupled to or disposed on the flexible PCB145and covered by a visible light camera cover lens, which is aimed through opening(s) formed in the right temple150. In some examples, the frame160connected to the right temple150includes the opening(s) for the visible light camera cover lens. The frame160may include a front-facing side configured to face outwards away from the eye of the user. The opening for the visible light camera cover lens may be formed on and through the front-facing side. In the example, the visible light camera140has an outward facing angle of coverage with a line of sight or perspective of the right eye of the user of the eyewear device100. The visible light camera cover lens also can be adhered to an outward facing surface of the right temple150in which an opening is formed with an outward facing angle of coverage, but in a different outwards direction. The coupling can also be indirect via intervening components.

Flexible PCB145may be disposed inside the right temple150and coupled to one or more other components housed in the right temple150. Although shown as being formed on the circuit boards145of the right temple150, the visible light camera140can be formed on another circuit board (not shown) in one of the left temple, the hinged arm155, the hinged arm165, or the frame160.

As illustrated inFIG.1A, the circuit110in a left temple or arm of the electronic eyewear device100may be generally represented as a battery112, a charger114, a temple resistance116, and a load118. Similarly, circuit120in a right temple150or arm165of the electronic eyewear device100may be generally represented as a battery122, a charger124, a temple resistance126, and a load128. The circuit110and the right circuit120are physically separated by the frame160of the glasses, which is represented inFIG.1Aas a frame resistance160.

FIG.2illustrates the current flow in the system ofFIG.1Awhere the load118in the circuit110in the left temple or arm of the electronic eyewear device100is dominant. In this case, the load118draws a large current from battery112as indicated by arrow200and also draws some current from battery122of the circuit120in the right temple or arm as indicated by arrow210. Such current drawn by the load118causes a mismatch between the discharge rates of the batteries112and122.

Different options for addressing this mismatch between the discharge rates of the batteries112and122will be described below with respect toFIGS.3-10. The configurations reduce (or substantially minimize) the discharge mismatch by increasing the resistance or decreasing the battery voltage on the side of the electronic eyewear device100experiencing the higher battery discharge rate, boosting the voltage or decreasing the resistance on the other side of the electronic eyewear device100to balance the loads, or both. In other words, using Ohms law I=V/R, the current I may be decreased on one side of the electronic eyewear device100by decreasing the voltage V, by increasing the resistance R, or both, and the current I may be increased on one side of the electronic eyewear device100by increasing the voltage V, by decreasing the resistance R, or both, as appropriate to balance the loads on the respective sides of the electronic eyewear device100. The circuits described with respect toFIGS.3-10function to continuously match the DC current provided by the batteries112and122to improve battery health, reliability and safety. The described techniques do so with minimal software interaction and with a reduced electrical circuit design complexity.

In the circuit configurations described herein, the high side current of each battery on respective sides of the electronic eyewear device100is measured and fed into a closed loop control system that performs functions including:actively regulating the battery current paths so that the battery current is approximately the same on each side based on the load (FIG.3);tilting the balance between the circuits if there is an existing battery discharge mismatch (FIG.4);managing UVLO situations when either battery is nearing empty (almost completely discharged) (FIG.5);disabling features when the system current is exceptionally high (i.e., higher than an upper threshold) and turning off the circuit when system current is exceptionally low (i.e., lower than a lower threshold) (FIG.6); anddisabling a single side's set of battery balancing features when it is predicted that one side will have the dominant load (FIG.7).

The battery current paths are modulated to achieve a balanced current by modulating transistors used to independently limit the current in the left/right battery current paths (FIGS.3-9), or by modulating the voltage output of DC/DC converters (e.g., boost circuits) to independently boost the current in the left/right battery baths (FIG.10). Each of these configurations will be described below.

FIG.3is a block diagram of a power management system including a current balancing control loop300including elements310L,320L, and330Lin circuit110and elements310R,320R, and330Rin circuit120that actively regulate the battery current paths of the circuits110and120so that the currents through circuits110and120are substantially equal. The electrical currents through the circuits110and120change according to the respective loads118and128in the circuits110and120. As illustrated, the circuit110(120) includes a current sensing amplifier (CSA)310L(310R) that measures the current through the resistance116(126). The output of the CSA310L(310R) is provided to the differential amplifier320L(320R) to provide adjustment signals via circuit330L(330R) based on the differences in the measured currents. As illustrated, the circuit330Lincludes power field effect transistor (PFET)332L, forward directed diode334L, and resistors336Land338L, and the circuit330Rincludes PFET332R, forward directed diode334R, and resistors336Rand338R. In particular, the differential amplifier320L(320R) modulates the PFET332L(332R) in the current path to dynamically limit the current by dynamically adjusting the resistance. For example, when the circuit310Lis “ON,” the PFET332L(332R) is open and the resistance through the PFET332L(332R) is low. However, when differences are detected between the measured currents through the temple resistances116and126, the differential amplifier320L(320R) modulates the PFET332L(332R) to dynamically increase the resistance in the circuit110(120) that has a larger measured current, thus aligning the resistances and currents on both sides of the electronic eyewear device100.

During operation, when the left circuit110has a dominant load, the PFET332Ron the side opposite the dominant load is ON while the PFET332Lon the side of the dominant load limits the current by increasing resistance to match the other side. It will be recognized that there is an inherent offset (Delta_IBatt) with this solution. The inherent offset (Delta_IBatt) depends on the voltage (VBattery) of the battery112and122, the voltage (Vth) across the PFETs332Land332R, the gain (Amp Gain) of the differential amplifiers320Land320R, the voltage outputs (Amp Vos) of the differential amplifiers320Land320R, and the respective tolerances. The response time is limited by the CSAs310Land310Rand the differential amplifiers320Land320R(pending stability). When the loads118and128are very similar or equal, up to Delta_IBatt, both PFETs332Land332Rwill be ON, while above Delta_IBatt, the balancing provided by increasing the resistance in one circuit110or120will be effective.

FIG.4is a block diagram of a power management system including the current balancing control loop400where the current balancing control loop300ofFIG.3is modified to include tilting circuits410L(including FET412L, reverse directed diode414L, and resistor416L) and410R(including FET412R, reverse directed diode414R, and resistor416R) that periodically check the batteries112and122for any significant mismatch and prioritize the side with the lighter load until the charges of the batteries112and122are substantially equalized. During operation, a CPU420Lor420Rmay periodically check the state of charge of the batteries112and122as provided by the chargers114and124to determine any significant mismatch. If there is a mismatch, the TILT_FET412Lor412Rwill be enabled on the side with higher state of charge. This will cause the measured current through the corresponding temple resistance116or126to appear smaller, thereby tricking the CSAs310Land310Rand causing the balance circuits330Land330Rto prioritize the side with the higher state of charge. For example, if the left battery112is more discharged, the CPU420Rturns on the TILT FET412R, which tricks the CSAs310Land310Rinto thinking that the current is lower through temple resistance126than through temple resistance116, causing differential amplifier320Lto restrict the current through PFET332L. Once the charges of the batteries112and122are substantially equalized, the CPU420Rdetermines that the state of charge is balanced and the enabled TILT_FET412Ris turned off. CPU420Lmay also perform these functions, as appropriate, or a single CPU420may be provided to perform these functions.

The tilt accuracy of the current balancing control loop400depends on tolerances of the measured resistances (Rds_on, Rsense, Rseries). For example, when Rsense=10 m, Rseries=20 m, and 7.3 m<Rds_on<12.6 m, the tilt range is 23%-27%.

FIG.5is a block diagram of a power management system including the current balancing control loop300ofFIG.3modified to include an undervoltage lockout (UVLO) circuit control loop500to regulate the battery voltage of circuits110and120above the UVLO point. As illustrated, a second control loop including differential amplifiers (comparators)510Land510R, FETs520Land520R, diodes522Land522R, and resistances512L,514L,512R, and514Rare added to regulate the battery voltage of each circuit110and120above the UVLO point. For the left circuit110, the battery voltage is measured at the load118through resistors512Land514Land compared to a reference voltage (PP1V8) by comparator510L. If the voltage is too low, the comparator510Lwill trigger BATT_FET520Lto be ON to pull down the gate of PFET332Las necessary to override the balancing by balance circuit330Las well as the tilt circuit410L(FIG.4). If the resistance is too high, current is added instead of more resistance in order to keep the circuit110alive as long as possible. Limiting the peak load in this manner lowers the voltage to temporarily provide a higher current. The same process is applied to the right circuit120using elements510R,520R,522R,512R, and514R. The UVLO control loop500thus keeps the circuits110and120alive as long as possible.

It will be appreciated that, just like with current balancing, there is an inherent current mismatch with the UVLO control loop500. Fortunately, the UVLO point may be varied to add enough margin to provide balancing. For example, high/low thresholds may be set that are 5-10% from the minimum/maximum voltages, as appropriate for the implementation. These thresholds may be set by a processor, such as CPUs420Lor420R(FIG.4). The response time is limited by the differential amplifier510Lor510R, which may operate at, for example, 0.2 MHz, and by any low pass filtering used to provide stability. The UVLO control loop500further may act as a safety net for any instability or slow response time in the balancing circuity330L. On the other hand, the UVLO control loop500knowingly adds mismatch to the batteries112and122.

FIG.6is a block diagram of a power management circuit including a disabling circuit600for disabling all features during exceptionally high or low load power consumption. During exceptionally high or low load power consumption, at least one of the CPUs420Lor420Rcan disable all features by opening PFET332Lor PFET332Rto turn off all control loops. In high power cases, this will disable any battery current limiting, while in low power cases, this will reduce standby power consumption. Thus, for an exceptionally low load, there is no need to balance, while for an exceptionally high load, there is a need to disable battery current limiting.

In certain circuit implementations, it will be easy to predict which circuit110or120will have the dominant load.FIG.7is a block diagram of a power management system including the current balancing control loop300ofFIG.3modified to disable the set of battery balancing features of circuit120when it is predicted that the circuit110always will have the dominant (peak) load. In this case, the CPU420R(not shown) can disable the set of battery balancing features of the circuit120to reduce standby power consumption and to improve the control loop stability margins. The control loop features700may be maintained for the circuit110, as shown inFIG.7.

FIG.8is a block diagram of a power management system combining the features ofFIGS.3-7in one circuit800. In particular,FIG.8includes the current balancing control loop300ofFIG.3, the tilting circuit410ofFIG.4, the UVLO control loop500ofFIG.5, the disabling circuit600ofFIG.6, and the load mismatch circuit700ofFIG.7.FIG.8also includes CPUs420Land420Rthat are used to control the tilting circuit410and the disabling circuit600. The modes of operation of the circuit800are controlled by the CPUs420Land420R, based on the state machines810Land810R, which are implemented by each CPU420Land420Ras described below with respect toFIGS.9A and9B.

For simplicity, the state machines810Land8108implemented by CPUs420Land420Rmay be divided into a state machine900for battery balancing (FIG.9A) and a state machine950(FIG.9B) for battery tilting. The state machines900and950may be controlled by a low-power microcontroller (not shown) which is separate from the CPUs420Land420R.FIGS.9A and9Buse CPUs420Land420Rto demonstrate that dynamic loads may be operated independently on either side of electronic eyewear device100in the examples.

FIG.9Aillustrates a state machine900for the different modes of operation of battery balancing by the current balancing control loop800described with respect toFIG.8. As illustrated, when both CPUs420Land420Rare OFF, the CPUs420Land420Rare in state910, and battery balancing is OFF. On the other hand, when both CPUs420Land420Rare ON, the CPUs420Land420Rare in state920, and battery balancing is ON. When only the left CPU420Lis ON, the CPUs420Land420Rare in state930where the left battery balancing is ON. Similarly, when only the right CPU420Ris ON, the CPUs420Land420Rare in state940where the right battery balancing is ON. The battery balancing features are enabled accordingly.

FIG.9Billustrates a state machine950for the different modes of operation of the battery tilting feature of the tilting circuit410ofFIG.8. In accordance with the state machine950, the battery tilting feature is OFF at state960when the state of charge of one battery is no more than 1.2 times the state of charge of the other battery. When the state of charge of the left battery112exceeds 1.2 times the state of charge of the right battery122, the left battery tilting feature is turned ON at state970. The left battery tilting feature is then turned OFF when the state of charge of the left battery112is less than 1.1 times the state of charge of the right battery122and the state machine returns to state960. Similarly, when the state of charge of the right battery122exceeds 1.2 times the state of charge of the left battery112, the right battery tilting feature is turned ON at state980. The right battery tilting feature is then turned OFF when the state of charge of the right battery122is less than 1.1 times the state of charge of the left battery112and the state machine returns to state960.

In an alternative configuration, the left or right battery voltage may be independently boosted as opposed to limiting the battery voltage as in the configurations ofFIGS.3-9.FIG.10is a block diagram of a power management system including a boost converter circuit1000that independently boosts the left or right battery voltages as opposed to limiting the voltages as inFIGS.3-9. The boost converter circuit1000inFIG.10includes a boost circuit1010Lfor the left circuit110and a boost circuit1010Rfor the right circuit120. Each boost circuit1010Land1010Rincludes a voltage adjustment pin1012Lor1012Rthat is used to modulate the voltage output by the boost circuit1010Lor1010Rin response to any voltage imbalances measured by differential amplifiers320Land320R. As illustrated, the boost converter circuit1000may include FET1020L, diode1022L, and resistance1024Lthat provide a voltage modulation signal to boost circuit1010Lthat increases the current applied to the load118to match the current applied to the load128by increasing the voltage output by the boost circuit1010L. The boost converter circuit1000also may include FET1020R, diode1022R, and resistance1024Rthat provide a voltage modulation signal to boost circuit1010Rthat increases the current applied to the load128to match the current applied to the load118by increasing the voltage output by the boost circuit1010R.

In the configuration ofFIG.10, the differential amplifiers320Land320Rmodulate the voltage adjustment pin1012Lor1012Rof the boost circuits1010Land1010Rto dynamically boost the voltage applied to the loads118or128. In a sample configuration, the boost circuits1010Land1010Rmay be DC/DC converters configured to boost the output voltage in response to the inputs provided at the voltage adjustment pins1012Lor1012R. By boosting the voltages, any electrical resistance160seen through the frame between the left temple circuit110and the right temple circuit120may be overcome.

It will be appreciated that the control loop approach used inFIG.10is inherently safe as it can never cut off the battery current path by accident. The control loop approach used inFIG.10also can be more efficient depending on the application. It will be further appreciated that the control loop approach used inFIG.10can better handle high power use cases by boosting both batteries. The control loop approach used inFIG.10also is better suited to handle UVLO use cases due to the superior Vin requirements of the boost circuits1010Land1010R.

However, it also will be appreciated that the control loop approach used inFIG.10may severely limit stability and response time because of the internal control loops of the DC/DC converters used in the boost circuits1010Land1010R. Thus, the control loop approach used inFIG.10also can be less efficient depending on the application. The closed loop approach used inFIG.10also may have an increased size and cost as compared to the configurations ofFIGS.3-8.

Those skilled in the art will appreciate that the circuitry described herein may be analog or digital circuitry. However, digital circuitry is potentially more expensive and may require the control loops to be implemented using software that could add to the cost, complexity, and response time.

While various implementations have been described above, it should be understood that they have been presented by way of example only, and not limitation. For example, any of the elements associated with the systems and methods described above may employ any of the desired functionality set forth hereinabove. Thus, the breadth and scope of a preferred implementation should not be limited by any of the above-described sample implementations.

The logic, commands, or instructions that implement aspects of the methods described herein may be provided in a computing system including any number of form factors for the computing system such as desktop or notebook personal computers, mobile devices such as tablets, netbooks, and smartphones, client terminals and server-hosted machine instances, and the like. Another embodiment may include the incorporation of the techniques discussed herein into other forms, including into other forms of programmed logic, hardware configurations, or specialized components or modules, including an apparatus with respective means to perform the functions of such techniques. The respective algorithms used to implement the functions of such techniques may include a sequence of some or all of the electronic operations described herein, or other aspects depicted in the accompanying drawings and detailed description below. Such systems and computer-readable media including instructions for implementing the methods described herein also constitute sample embodiments.

Accordingly, the term “module” is understood to encompass a tangible hardware and/or software entity, be that an entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transitorily) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples in which modules are temporarily configured, each of the modules need not be instantiated at any one moment in time. For example, where the modules comprise a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as respective different modules at different times. Software may accordingly configure a hardware processor, for example, to constitute a particular module at one instance of time and to constitute a different module at a different instance of time.

Those skilled in the art will appreciate that while the disclosure contained herein pertains to electronic eyewear devices having separately powered circuits in physically separate portions of the electronic eyewear device, it should be understood that this is only one of many possible applications, and other configurations are possible. Accordingly, all such applications are included within the scope of the following claims.