Method for etching vertical contact holes without substrate damage caused by directional etching

A method of etching vias without directional etching damage to the substrate. A pattern image is formed on an insulating layer of known thickness over a substrate. A conformal layer is formed on the pattern image. A vertical contact hole through the conformal layer and into the insulating layer is produced by directional etching. The directional etch also leaves conformal sidewall spacers of a defined width. The depth of the vertical contact hole is equal to the thickness of the insulating layer minus the width of the conformal spacer. The insulating layer is then removed by an isotropic wet etch to achieve a near vertical edge contact hole without directional etching damage to the substrate. The sidewall spacers may also be removed by etching prior to removal of the insulating layer.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention generally relates to a method of making vertical 
contact holes through an insulator to a silicon substrate, and, more 
particularly, to a method of etching vertical contact holes without 
substrate damage caused by directional etching. 
2. Description of the Related Art 
In the semiconductor industry, there is a need to create vertical contact 
holes through an insulator to the silicon or other semiconductor substrate 
to minimize image size. A typical technique employs an appropriate mask 
positioned over an insulator to define the contact holes. This is followed 
by a directional etch, such as an anisotropic reactive ion etch (RIE) that 
etches the underlying insulator to form the vertical contact holes. 
However, vertical contact processing using a directional or reactive ion 
etch (RIE) generally damages (etches) the underlying silicon substrate as 
well, since the RIE etch is not selective enough to stop on the silicon 
substrate. The damage--caused by chemical and/or ion bombardment 
attack--limits precise definition of shallow emitters, especially for 
bipolar technologies. 
Wet etching of contact holes through the insulator is extremely selective 
and does not damage the silicon substrate. The wet etch, however, results 
in contact holes having curved edges through the insulator to the 
substrate, which undesirably increases the contact hole size. 
In an effort to overcome such difficulties, shallow emitter technologists 
and designers have employed an etch stop in the vertical RIE contact 
process, followed by a subsequent isotropic wet etch of the etch stop. 
While the wet etch leaves the silicon surface undamaged, it also undercuts 
the etch stop in the vertical contact hole since the isotropic wet etch 
etches equally in all directions. This causes a problem for subsequent 
metal coverage and/or proper contact only to the emitter. 
In light of the foregoing, there exists a need for a method of creating 
vertical contact holes or vias without directional etching damage to the 
underlying substrate and without the undercutting problem associated with 
isotropic wet etches. 
SUMMARY OF THE INVENTION 
The present invention is directed to method of maintaining a near vertical 
edge in a contact hole, without directional etching damage to the silicon 
substrate, which substantially obviates one or more of the problems due to 
the limitations and disadvantages of the related art. 
In addition, the present invention eliminates the etch stop contact 
undercut normally associated with wet etch methods. 
To achieve these and other advantages and in accordance with the purpose of 
the invention, as embodied and broadly described, the invention provides 
for a method of etching vertical contact holes in a semiconductor device 
having an insulating layer of known thickness `X` formed over a substrate, 
the method comprising the steps of: (1) forming a pattern image on the 
insulating layer; (2) forming a conformal layer on the pattern image; (3) 
etching the conformal layer by directional etching to produce sidewall 
spacers, each of width `W` and having a vertical contact hole 
therebetween, the etching continuing to the insulating layer to a depth 
equal to the thickness `X` of the insulating layer minus the width `W` of 
the sidewall spacer; and (4) isotropically removing the insulating layer 
to achieve a near vertical edge contact hole without directional etching 
damage to the substrate. 
In another aspect, the method of the present invention may comprise the 
additional step of removing the sidewall spacers prior to removing the 
insulating layer. 
It is to be understood that both the foregoing general description and the 
following detailed description are exemplary and explanatory and are 
intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION 
Forming vertical contact holes or vias is an integral part of the 
semiconductor manufacturing process. Accordingly, it would be understood 
by those or ordinary skill in the art that the method of the present 
invention may be used in a wide variety of integrated circuit 
applications. Moreover, the inventive method disclosed below may be 
practiced at any point in the semiconductor manufacturing process. 
Referring now to the drawings, and more particularly to FIG. 1, there is 
shown an insulator layer 110 formed over a silicon substrate wafer 100. By 
way of example, and not by limitation, the insulating layer 110 may be 
comprised of silicon glasses such as silicon dioxide (SiO.sub.2) or 
silicon nitride (Si.sub.3 N.sub.4), or other suitable oxide materials such 
as aluminum trioxide (Al.sub.2 O.sub.3). SiO.sub.2 may be grown by any 
conventional means, including for example, either a wet or dry oxygen 
ambient at temperatures between 800.degree. C.-1200.degree. C. 
Likewise, Si.sub.3 N.sub.4 may be formed by any conventional means, 
including for example, chemical vapor deposition (CVD). There is a wide 
variance in the processing conditions for CVD. A typical reaction is the 
combination of silane (SiH.sub.4) and ammonia (NH.sub.3) in an inert 
atmosphere, usually nitrogen (N.sub.2), argon (Ar), or hydrogen (H.sub.2), 
at a typical temperature range of 750.degree. C.-850.degree. C. 
Conventional low-pressure (LPCVD) or plasma enhanced (PECVD) techniques 
may also be utilized. 
In general, the insulating layer could be composed of any material, so long 
as an image could be patterned thereon for subsequent etching. The 
appropriate thickness `X` of the insulating layer would depend on the 
material chosen, and the desired depth of the trench. A suitable mask 120, 
composed of resist or other suitable material, is positioned over the 
insulator 110 to define the contact or via holes where required. 
In FIG. 2, a conformal layer of material 130 is deposited over the mask. 
The conformal layer should have similar etch characteristics to that of 
the insulator material 110. Examples of suitable conformal materials 
include, but are not limited to, insulators, paralyne, SiO.sub.2, Si.sub.3 
N.sub.4, or Al.sub.2 O.sub.3. 
As shown in FIG. 3, the conformal layer 130 is then directionally etched, 
using a reactive ion etch (RIE) for example, to form sidewall spacers 135. 
It is understood that other conventional directional etching techniques, 
such as planar plasma (or diode) etching for example, may be utilized in 
the practice of this invention. 
In FIG. 4, the directional or RIE etch continues through to the insulating 
layer 110 to a depth `D` equal to the thickness `X` of the insulating 
material 110 minus the width `W` of the spacer 135, that is, D=X-W. 
In FIG. 5 the dashed lines illustrate that a portion of the insulating 
layer 110 and/or the conformal layer 130 (defined by remaining spacers 
135) may be removed. The conformal layer may be, but need not be removed 
prior to removing the insulating layer. 
If the particular semiconductor device application required removal of the 
conformal layer, composed of paralyne for example, the sidewall spacers 
135 may be removed by an isotropic O.sub.2 plasma etch. The insulating 
layer 110 is then removed by an appropriate isotropic wet etch, such as 
buffered hydrogen fluoride (BHF) for etching silicon dioxide. Note that 
the wet etch--which etches equally in all direction--does not undercut the 
image under the mask 120. This is because the thickness or width of the 
insulating material 110 that is etched is equal to the width of the spacer 
material 135. 
In the final step, the mask 120 may be removed by conventional means. What 
remains is a contact or via hole 150 with a near vertical edge without 
directional etching or RIE damage to the underlying substrate and without 
the undercutting problem associated with isotropic wet etches. 
While the invention has been described in terms of the embodiments 
described above, those skilled in the art will recognize that the 
invention can be practiced with modification within the spirit and scope 
of the appended claims.