METHOD FOR PERFORMING PROGRAM INHIBIT OPERATION WITH CELL DISTURBANCE ALLEVIATION, MEMORY DEVICE AND CONTROLLER

A method for performing a program inhibit operation with cell disturbance alleviation, a memory device and a controller are provided. The method includes the following steps. A verify operation is performed on a cell string of a cell array. A power pulse is applied on the cell string. The program inhibit operation is performed on the cell string. The step of applying the power pulse is performed before the step of performing the program inhibit operation.

TECHNICAL FIELD

The disclosure relates in general to an operation method, a memory device and a controller, and more particularly to a method for performing a program inhibit operation with cell disturbance alleviation, a memory device and a controller.

BACKGROUND

Along with the development of memory technology, various memories are invented. Each cell in the memory can be programed or erased to record data as “0” or “1,” For example, NAND memory is programmed via Fowler-Nordheim tunneling (FN-tunneling). When some cells are programmed via hot-electrons, other cells are performed the program inhibit operation to prevent from being programming via the FN-tunneling. For example, the channel potential is increased to reduce the voltage difference between the program voltage of the word line and the channel. However, when some of the cells are performed the program inhibit operation, a hot-electrons environment is created in some programming pattern, and the hot-electrons mode disturbance is happened during the program inhibit operation.

SUMMARY

The disclosure is directed to a method of a method for performing a program inhibit operation with cell disturbance alleviation, a memory device and a controller. A power pulse is applied before performing the program inhibit operation, such that the down-coupling phenomenon could be suppressed. Because the down-coupling phenomenon is suppressed, the channel potential waveform is stable during the program inhibit operation without inducing any hot electron disturbance on the cells.

According to one embodiment, a method for performing a program inhibit operation is provided. The method includes the following steps. A verify operation is performed on a cell string of a cell array. A power pulse is applied on the cell string. The program inhibit operation is performed on the cell string. The step of applying the power pulse is performed before the step of performing the program inhibit operation.

According to another embodiment, a memory device is provided. The memory device includes a cell array, a word line decoder, a bit line decoder and a controller. The word line decoder is connected to a plurality of word lines of the cell array. The bit line decoder is connected to a plurality of bit lines of the cell array. The controller is connected to the word line decoder and the bit line decoder for performing a verify operation on a cell string of the cell array, applying a power pulse on the cell string, and performing a program inhibit operation on the cell string. The controller applies the power pulse before the program inhibit operation is performed.

According to an alternative embodiment, a controller is provided. The controller is connected to a word line decoder and a bit line decoder. The word line decoder is connected to a plurality of word lines of a cell array. The bit line decoder is connected to a plurality of bit lines of the cell array. The controller is used for performing a verify operation on a cell string of the cell array, applying a power pulse on the cell string, and performing a program inhibit operation on the cell string. The controller applies the power pulse before the program inhibit operation is performed.

DETAILED DESCRIPTION

Please refer toFIG. 1, a memory device100is shown. The memory device100includes a cell array110, a word line decoder120, a bit line decoder130and a controller140. The cell array110may be a 3D NAND memory, a floating gate memory, a nitride-trapping memory, a gate-all-around (GAA) memory or a vertical channel memory. The word line decoder120is connected to a plurality of word lines WL of the cell array110and the bit line decoder130is connected to a plurality of bit lines BL of the cell array110.

Please refer toFIG. 2, one cell string111of the cell array110is shown. The cell string111is connected to word lines WLn−2, WLn−1, WLn, WLn+1, WLn+2. When the word line WLn is applied a program voltage, a program inhibit operation is needed to be performed on the cells in the cell string111which are not needed to be programed.

Please refer toFIG. 3toFIG. 5D.FIG. 3shows a flowchart of a method for performing the program inhibit operation,FIG. 4illustrates the waveforms of the word line voltage VWLn, the pass voltage Vpass, the power voltage PW, the string select line voltage VSSL and the bit line voltage VBL, andFIGS. 5A to 5Dillustrate the channel potential waveforms CT1to CT6in the cell string111. In step S110, the controller140performs a verify operation on the cell string111from the time point T0to the time point T1. In the verify operation, the word line voltage VWLn is increased to be 7V, the pass voltage Vpass is increased to be 7V, the power voltage PW is kept at 0V, the string select line voltage VSSL is increased to be 7V and the bit line voltage VBL is increased to be 0.6V. Refer toFIG. 5A, which illustrates the channel potential waveform CT1of the cell string111at the time point T1. As the verify operation is just finished, the cell CLn coupled to the word line WLn is turned off and its channel potential falls to −4V due to the down-coupling phenomenon DC. There would be some channel potential difference PD between the cell CLn and the cell CLn+1 coupled to the word line WLn+1.

Next, in step S130, the controller140performs a pre-program operation on the cell string111. In the pre-program operation, the word line voltage VWLn is kept at 0V, the pass voltage Vpass is kept at 0V, the power voltage PW is kept at 0V, the string select line voltage VSSL is increased to be 4V and the bit line voltage VBL is increased to be 4V. Refer toFIG. 56, which illustrates the channel potential waveform CT2of the cell string111at the time point T2. During the charging of the string select line voltage VSSL and the bit line voltage VBL, the cells CLn+1 to CL31coupled to the word lines WLn+1 to WL31are pre-charged. Instead, the cells CL0to CLn−1 coupled to the word lines WL0to WLn−1 remain unchanged because the cell CLn−1 isolates the upper channel.

In step S140, the controller140performs a program inhibit operation on the cell string111. At the beginning of the pre-program operation (time point T3), the word line voltage VWLn is increased to be 8V, the pass voltage Vpass is increased to be 8V, the power voltage PW is kept at 0V, the string select line voltage VSSL is kept at 0V and the bit line voltage VBL is kept at 0V. Refer toFIG. 5C, which illustrates the channel potential waveform CT3of the cell string111at the time point T3. As the pass voltage Vpass is applied to all of the cells, the electrons are supplied to the upper cells and their channel potentials are boosted by capacitive coupling. At this time, the channel potential of cell CLn is boosted according to the pass voltage Vpass while maintaining the turned-off state.

During the program inhibit operation (from the time point T3to the time point T6), the word line voltage VWLn is increased from 8V to 24V, the pass voltage Vpass is kept at 8V, the power voltage PW is kept at 0V, the string select line voltage VSSL is kept at 0V and the bit line voltage VBL is kept at 0V. Refer toFIG. 5D, which illustrates the channel potential waveforms CT3to CT6of the cell string111from the time point T3to the time point T6respectively. Along with the increasing of the word line voltage VWLn, the channel potential difference PD is decreased. The transient current will flow through the cell CLn to the cell CLn+1 due to the annihilation of the electron barrier. The hot electron disturbance on the cell CLn+1 will be consequently induced.

Please refer toFIG. 6showing an E-trapped charge pattern CE of the cell CLn+1 which is injected the transient current. A hot electron signal is detected in the cell CLn+1. As shown in the E-trapped charge pattern CE, the accumulated trapped charge in nitride is increased along with the time. Therefore, the cell CLn+1 is disturbed during the program inhibit operation.

Please refer toFIG. 7toFIG. 9.FIG. 7shows a flowchart of a method for performing the program inhibit operation with cell disturbance alleviation,FIG. 8illustrates the waveforms of the word line voltage VWLn′, the pass voltage Vpass′, the power voltage PW′, the string select line voltage VSSL′ and the bit line voltage VBL′, andFIG. 9illustrates the channel potential waveforms CT1′, CT1′A in the cell string111at the time points T1′, T1′A respectively.

In step S110′, the controller140performs a verify operation on the cell string111from the time point T0′ to the time point T1′. In the verify operation, the word line voltage VWLn′ is increased to be 7V, the pass voltage Vpass' is increased to be 7V, the power voltage PW′ is kept at 0V, the string select line voltage VSSL′ is increased to be 7V and the bit line voltage VBL′ is increased to be 0.6V. Referring toFIG. 9, the channel potential waveforms CT1′ of the cell string111at the time point T1′ is shown. As the verify operation is just finished, the cell CLn is turned off and its channel potential falls to −4V due to the down-coupling phenomenon DC. There would be some channel potential difference PD between the cell CLn and the cell CLn+1.

Afterwards, in step S120′, the controller140applies a power pulse PP (shown inFIG. 8) on the cell string111. In this step, the word line voltage VWLn′ is kept at 0V, the pass voltage Vpass' is kept at 0V, the power voltage PW′ is increased to be 0.5V to 1V, the string select line voltage VSSL′ is kept at 0V and the bit line voltage VBL′ is kept at 0V. In one embodiment, the power pulse PP is applied for 5 to 15 micro seconds and is applied to all of a plurality cells of the cell string111. Referring toFIG. 9, the channel potential waveforms CT1′A of the cell string111at the time point T1′A is shown. After the power pulse PP is applied, the down-coupling phenomenon DC could be suppressed, and the channel potential difference PD between the cell CLn and the cell CLn+1 could be eliminated.

Next, in step S130′, the controller140performs a pre-program operation on the cell string111. In the pre-program operation, the word line voltage VWLn′ is kept at 0V, the pass voltage Vpass' is kept at 0V, the power voltage PW is kept at 0V, the string select line voltage VSSL′ is increased to be 4V and the bit line voltage VBL′ is increased to be 4V.

In step S140′, the controller140performs a program inhibit operation on the cell string111. At the beginning of the pre-program operation (time point T3′), the word line voltage VWLn′ is increased to be 8V, the pass voltage Vpass' is increased to be 8V, the power voltage PW is kept at 0V, the string select line voltage VSSL′ is kept at 0V and the bit line voltage VBL′ is kept at 0V.

Refer toFIG. 10, which illustrates a comparison between the channel potential waveform CT3′ of the cell string111at the time points T3′ and the channel potential waveform CT3of the cell string111at the time points T3. As shown inFIG. 10, the large channel potential difference PD between the cell CLn and the cell CLn+1 would be vanished at the time point T3′.

During the program inhibit operation (from the time point T3′ to the time point T6′), the word line voltage VWLn′ is increased from 8V to 24V, the pass voltage Vpass' is kept at 8V, the power voltage PW is kept at 0V, the string select line voltage VSSL′ is kept at 0V and the bit line voltage VBL′ is kept at 0V. Because the down-coupling phenomenon DC is suppressed, the channel potential waveforms CT3′ is stable from the time point T3′ to the time point T6′ without inducing any hot electron disturbance on the cell CLm+1.

Please refer toFIG. 11, which illustrates the comparison between an E-trapped charge pattern CE′ of the cell CLn+1 which is not injected the transient current and the E-trapped charge pattern CE ofFIG. 6. As shown in the E-trapped charge pattern CE′, the accumulated trapped charge in nitride is kept at low level along with the time. Therefore, the cell CLn+1 is not disturbed during the program inhibit operation.

According to the embodiment described above, the extra power pulse PP can suppress the hot electron disturbance as the word line WLn being turned on. In this embodiment, the power pulse PP is applied between the verify operation and the program inhibit operation to suppress the down-coupling phenomenon DC, and alleviate the potential risk for hot electron disturbance.