SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

Disclosed is a silicon carbide power semiconductor device and, more particularly, a silicon carbide power semiconductor device capable of improving on-resistance characteristics by contacting at least one lowermost surface of a base or a source with an underlying JFET region.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean Patent Application No. 10-2023-0070955, filed Jun. 1, 2023, the entire contents of which are incorporated herein for all purposes by this reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a silicon carbide power semiconductor device and, more particularly, to a silicon carbide power semiconductor device capable of improving on-resistance characteristics by having at least one lowermost surface of a base or a source in contact with a junction field effect transistor (JFET) region therebelow.

Description of the Related Art

Silicon carbide (SiC) power semiconductor devices have a higher band gap, thermal conductivity, and breakdown field strength than Si devices. Owing to features such as high-temperature operation, low resistance at the same rating, and high current density, SiC power semiconductor devices have electrical properties suitable for power electronics applications. However, a major drawback of SiC power semiconductor devices in terms of applications is that the gate threshold voltage (VGS) to obtain the same rated current as a Si power semiconductor device is relatively high because of poor channel mobility and trans-conductance characteristics, due to traps and low electron concentration at a SiO2/SiC interface.

FIGS.1A and1Bare cross-sectional views of a conventional silicon carbide (SiC) power semiconductor device. Hereinafter, the structure and problems of the conventional device will be described in detail with reference toFIGS.1A and1B.

Referring toFIG.1A, a conventional SiC power semiconductor device9may be or include an inversion mode MOSFET. The power semiconductor device9comprises a source910having a second conductivity type, a base930having a first conductivity type, and a drift region950having the second conductivity type. The base930between the source910and the drift region950is controlled by a gate970. When a positive bias is applied to the gate970, the base930below the gate970is inverted (e.g., acquires a negative charge), and an electric current may be conducted. In the case of such an inversion mode MOSFET, there is a problem in that on-resistance (Ron) characteristics of the device9decrease due to relatively low channel mobility.

Referring toFIG.1B, a conventional SiC power semiconductor device9′ relates to an accumulation mode MOSFET (ACCUFET). Unlike the power semiconductor device9ofFIG.1A, in this power semiconductor device9′, a base930′ has the second conductivity type instead of the first conductivity type. Accordingly, a source910′, the base930′, and a drift region950′ have the second conductivity type (e.g., N-type). Despite its advantage of improving channel mobility compared to the inversion mode MOSFET, the accumulation mode MOSFET has disadvantages such as poor breakdown voltage (BV) and current leakage, and safety problems due to a low threshold voltage. Thus, an ACCUFET structure with improved characteristics is desired.

DOCUMENT OF RELATED ART

Korean Patent No. 10-2414729, entitled “HIGH VOLTAGE MOSFET DEVICE AND METHOD OF MANUFACTURING SAME.”

SUMMARY OF THE INVENTION

Accordingly, the present disclosure has been made keeping in mind the above problems occurring in the related art, and the present disclosure is directed to providing a silicon carbide power semiconductor device capable of improving on-resistance characteristics by having at least one lowermost surface of a base or a source contact a junction field effect transistor (JFET) region therebelow.

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device capable of improving the resistance characteristics of the JFET region according to an increase in the cross-sectional area or volume of the JFET region, and thereby improving the on-resistance characteristics of the device by including an opening in a shield region below a gate (e.g., of the silicon carbide power semiconductor device).

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device in which the opening(s) have an island-type shape (e.g., they are disconnected from each other along a length direction).

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device in which the JFET region in the opening is completely depleted to achieve the normally-off characteristics of the device. In such a device, the JFET region and the shield region may alternate laterally along a width direction.

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device capable of improving the on-resistance characteristics (e.g., of the silicon carbide power semiconductor device) according to the increase in the cross-sectional area or volume of the JFET region. In such a device, the shield region may have a varying width, and the base may have a lowermost surface, for example, that alternatingly contacts the shield region and the JFET region along the length direction.

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device in which the JFET region in a recess (e.g., of the silicon carbide power semiconductor device) is fully depleted to achieve the normally-off characteristics of the device. In such a device, shield region and the JFET region may include a plurality of alternating protrusions (e.g., along a predetermined direction).

In addition, the present disclosure is directed to providing a silicon carbide power semiconductor device that improves the on-resistance characteristics (e.g., of the silicon carbide power semiconductor device) by smooth current flow. In such a device, the JFET region may surround a lower side or lowermost surface of the shield region.

The disclosure may be implemented by embodiments having the following configurations in order to achieve the above-described objectives.

According to an embodiment of the present disclosure, there is provided a silicon carbide power semiconductor device, including a substrate; a drift region having a second conductivity type on the substrate; a JFET region having the second conductivity type on the drift region; a shield region having a first conductivity type on the drift region; a source having the second conductivity type on the shield region; a base having the second conductivity type, on the shield region, between the source and the JFET region; a gate including a gate insulating layer on the JFET region and a gate electrode on the gate insulating layer, a source metal on the source; and a drain metal on a surface of the substrate opposite from the drift region, wherein the shield region may have one or more openings therein.

According to another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the openings may be under the source.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the openings may be spaced apart from each other (e.g., along a length direction).

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the JFET region may contact a lowermost surface of the source and/or the base through the openings.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the JFET region may have a lowermost surface at a position deeper than that of the shield region.

According to still another embodiment, the silicon carbide power semiconductor device according to the present disclosure may further include a highly doped region having the first conductivity type on the shield region, adjacent to or in contact with the source.

According to still another embodiment, a silicon carbide power semiconductor device according to the present disclosure includes a substrate; a drift region having a second conductivity type on the substrate; a JFET region having the second conductivity type above the drift region; a shield region having a first conductivity type on the drift region; a base having the second conductivity type, on the shield region and having a sidewall in contact with the JFET region; a source having the second conductivity type on the shield region; and a gate including a gate insulating layer on the JFET region and a gate electrode on the gate insulating layer, wherein the base may have at least one lowermost surface in contact with the JFET region.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may have a varying width as the shield region extends along a length direction.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may be continuous along a width direction.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may have a sidewall below the gate a with a plurality of alternating protrusions and recesses.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the protrusion may be in contact with lowermost surfaces of the source and the base along the width direction.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the lowermost surface of the base may contact the JFET region in the recesses.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the JFET region may include a subregion immediately below the gate; and a carrier storage layer in contact with a lowermost surface of the shield region.

According to still another embodiment, the silicon carbide power semiconductor device according to the present disclosure may comprise first and second shield regions on opposite sides of the gate having sidewalls that are symmetrical or asymmetrical to each other with respect to a central plane of the gate along a length direction.

According to still another embodiment, a silicon carbide power semiconductor device according to the present disclosure includes a substrate; a drift region on the substrate; a JFET region on the drift region; a shield region on the drift region; a source on the shield region; a base on the shield region, between the source and the JFET region; and a gate on the JFET region, wherein the base and/or the source may have a lowermost surface that contacts the JFET region.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may include an opening, and the JFET region may be in contact with the source and/or the base through the opening.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the source, the base, and the drift region may have a same conductivity type.

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may comprise a plurality of openings spaced apart from each other (e.g., along a length direction).

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the shield region may have a sidewall spaced apart from a sidewall of the base under the gate (e.g., along a width direction).

According to still another embodiment, in the silicon carbide power semiconductor device according to the present disclosure, the base may have a lowermost surface at a position higher or shallower than that of the source.

By the above configurations, the present disclosure has the following effects.

According to the present disclosure, it is possible to improve on-resistance characteristics (e.g., of the silicon carbide power semiconductor device) by having at least one lowermost surface of a base or a source in contact with a JFET region therebelow.

In addition, according to the present disclosure, it is possible to improve the resistance characteristics of the JFET region according to the increase in the cross-sectional area or volume of the JFET region, and thereby improve the on-resistance characteristics of the device by including one or more openings in a shield region below a gate (e.g., of the silicon carbide power semiconductor device).

In addition, according to the present disclosure, the openings may have an island-type shape (e.g., disconnected from each other along the length direction).

In addition, according to the present disclosure, it is possible to achieve the normally-off characteristics of the device as the JFET region in the opening is completely depleted, as the shield region and the JFET region may repeatedly alternate along the width direction.

In addition, according to the present disclosure, it is possible to improve the on-resistance characteristics (e.g., of the silicon carbide power semiconductor device) according to the increase in the cross-sectional area or volume of the JFET region when the lowermost surface of the base is over the opening(s).

In addition, according to the present disclosure, it is possible to achieve the normally-off characteristics of the device as the JFET region in a recess (e.g., in the shield region) is fully depleted when the shield region has a plurality of alternating protrusion and recesses along a predetermined direction.

In addition, according to the present disclosure, it is possible to improve the on-resistance characteristics (e.g., of the silicon carbide power semiconductor device) by smooth current flow when the JFET region surrounds the lowermost surface of the shield region.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The embodiments of the present disclosure may be modified in various forms, and the scope of the present disclosure should not be construed as being limited to the following embodiments, but should be construed based on the matters described in the claims. In addition, the embodiments are provided only for reference, in order to more completely explain the present disclosure to those skilled in the art.

As used herein, the singular form may include the plural form, unless the context clearly indicates otherwise. In addition, as used herein, the terms “comprise” and “comprising” specify the presence of the recited shapes, numbers, steps, operations, members, elements, and/or groups thereof, but do not exclude the presence or addition of one or more other shapes, numbers, steps, operations, members, elements, and/or groups thereof.

Hereinafter, it should be noted that when one component (or layer) is described as being on another component (or layer), the one component may be directly on the other component, or one or more third components or layers may be between the one component and the other component. In addition, when one component is expressed as being directly on or above another component, no other components are between the one component and the other component. Moreover, being located on “top”, “upper”, “lower”, “above”, “below” or “one (first) side” or “an opposite side” of a component refers to a relative positional relationship.

Hereinafter, a first conductivity type impurity region will be understood as, for example, a “P-type” or “N-type” doped region, and a second conductivity type impurity region will be understood as a doped region having the other type (i.e., N-type or P-type). In some cases, the first conductivity type impurity region may be a “P-type” region and the second conductivity type impurity region may be an “N-type” doped region, but there is no limitation thereto.

In addition, in the Figures showing a plan view, the x-axis direction is referred to as the “width direction” and the y-axis direction is referred to as the “length direction”. It should be noted that for convenience of description and to show a clear structure of a shield region in the plan view, only portions of the gate electrode, the shield region and the JFET region are specifically expressed.

A silicon carbide power semiconductor device1to be described below is preferably an accumulation mode MOSFET (hereinafter referred to as “ACCUFET”).

FIG.2is a plan view of a silicon carbide power semiconductor device according to a first embodiment of the present disclosure;FIG.3is a cross-sectional view along the line A-A′ inFIG.2; andFIG.4is a cross-sectional view along the line B-B′ inFIG.2andFIGS.5-6are alternative embodiments of the silicon carbide power semiconductor device shown inFIG.4. For convenience of description, it should be noted that components omitted from the plan view ofFIG.2are shown in the cross-sectional views ofFIGS.3-6.

Hereinafter, a silicon carbide power semiconductor device1according to a first embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

Referring toFIGS.2to6, the present disclosure relates to a silicon carbide power semiconductor device1and, more particularly, to a silicon carbide power semiconductor device1capable of improving on-resistance characteristics of the device by including a shield region (or well region)140below a gate160with an opening therein.

First, referring toFIGS.2to4, the silicon carbide power semiconductor device1according to a first embodiment of the present disclosure may include a substrate101. The substrate101may include, for example, a silicon carbide (SiC) wafer doped with a high concentration of impurities having a second conductivity type. To be specific, the substrate101may be or comprise, for example, a4H-SiC or6H-SiC substrate. In addition, the second conductivity-type impurity in the substrate101may include, for example, phosphorus.

A drift region110may be on the substrate101. The drift region110may include, for example, a SiC epitaxial layer grown on the upper surface of the SiC single crystal substrate101, while maintaining a specific crystal orientation relationship with the crystal orientation of the substrate101, but the scope of the present invention is not limited thereto. In addition, the drift region110may comprise a polytype silicon carbide layer, and may comprise a low-concentration impurity doped region having the second conductivity type. The drift region110may be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto and may be formed by various processes such as molecular beam epitaxy (MBE), sublimation epitaxy, and liquid phase epitaxy.

A JFET region130may be in or on the drift region110. The JFET region130comprises a highly doped region having the second conductivity type and may be formed by epitaxial growth or an ion implantation process. The JFET region130may have a uniform or non-uniform impurity doping concentration. To describe the structure of the JFET region130in detail, the JFET region130may be between a pair of adjacent bases151and shield regions140(e.g., along the width direction) and surround the lowermost surface of the shield region140.

That is, at least part of the JFET region130may be deeper than the lowermost surfaces of the shield region140and a heavily doped region153to surround the regions140and153in the drift region110or on the drift region110. By forming the JFET region130in this way, when a current flows from a drain metal180to a source metal170, which will be described later, the corresponding current may move through not only a region131immediately below the gate160but also a lower region133contacting the lowermost surface of the shield region140, current distribution due to the addition of the current movement path may be possible. Accordingly, an effect of improving the on-resistance characteristics of the device may be obtained. That is, the region133of the JFET region130may comprise a carrier storage layer (hereinafter referred to as “CSL”) function.

However, in some cases, the JFET region130may include the region131immediately below the gate160, separate from the lower region133contacting the lowermost surface of the shield region140. As such, when the CSL is not formed, in the gate turn-on state, that is, the switch-on state, the current may flow below the shield region140and may spread at about 45 degrees, thereby avoiding the shield region140, and thus the entire current flow may be hindered, causing an increase in on-resistance.

The shield region140may be in or on the drift region110or the JFET region130. The shield region140may comprise an impurity-doped region having a first conductivity type. In general, the ACCUFET has a structure in which the source150having the second conductivity type, the base151having the second conductivity type, and the drift region110having the second conductivity type are all conductive, so that during low-current forward operation, current flows through the second conductivity type (e.g., N-Type) conduction regions, instead of a PN diode.

In addition, although it is common that, during reverse operation, the second conductivity type source150, base151, and drift region110from the drain metal180to the source metal170are conductive and are not normally off, current does not flow due to a depletion layer in the junction region between the second conductivity type base151, the shield region140having the first conductivity type, and the JFET region130therebetween, a detailed description of which will be described later. In this case, the ability of the device1to withstand or tolerate high voltages (e.g., >1000 V) may be achieved by depletion between the shield region140and the drift region110.

However, as described above, in the switch-on state, since the current may flow below the shield region140and spread at about 45 degrees to avoid the shield region140, the entire current flow is hindered, causing an increase in on-resistance. Thus, in terms of the on-resistance of the device1, it is preferable that the shield region140is minimized.

The source150and the base151may be in the shield region140or on the shield region140. The source150is a region doped with a high concentration of second conductivity type impurities, and may have a higher impurity concentration than the drift region110. The base151is an impurity-doped region having the second conductivity type, and preferably contains a lower concentration of impurities than the source150. In addition, one side of the base151may be in contact with the source150. Preferably, the base151does not completely cover the JFET region130below the gate160. The base151may have a shallower depth than the source150, but the scope of the present disclosure is not limited thereto.

Referring toFIGS.2and4to6, the aforementioned shield region140may have an opening145along the width direction below the source150and/or the base151. Referring toFIG.4, for example, the shield region140may include a first part141under the source150and the heavily doped region153; and a second part143under the base151. the first region141and the second part143may be spaced apart from each other along the width direction by the opening145. The JFET region130, which is an impurity-doped region having the second conductivity type, may be in the opening145. That is, the JFET region130in the opening145may be in direct contact with the source150and/or the base151.

A plurality of openings145may be spaced apart from each other along the length direction and may have an island-type shape or arrangement. The openings145may be disconnected along the length direction (seeFIG.2). By contrast, when the opening145has a stripe or rectangular shape extending along the length direction, the second part143may not be connected to the first part141, and thus, may be floating in the JFET region130, which is not preferable. The term “island-type” should be understood to include not only the openings145having the same width and separation distance from each other along the length direction, but also different widths and separation distances from each other. A connection portion147connecting the first part141and the second part143may be formed between the pair of adjacent openings145along the length direction. The connection portion147is a part of the shield region140and may be an impurity-doped region having the first conductivity type (seeFIG.2). The first part141, the second part143and the connection portion147may have identical chemical compositions and identical thicknesses.

As previously described, when the opening(s)145have an island-type shape, between adjacent openings145along the length direction, the shield region140(or connection portion147) may be continuous along the width direction (seeFIG.3) so that the lowermost surfaces of the source150and the base151thereon do not contact the JFET region130in the location(s) of the connection portion147.

Hereinafter, the structure of the shield region140including the opening145(FIG.4) will be described in detail.

Referring toFIG.4, for example, the first part141may contact the entire lowermost surfaces of the source150and the heavily doped region153to be described later (e.g., along the width direction), while the second part143may contact only part of the total area of the lowermost surface of the base151(e.g., along the width direction). Thus, the base151may contact the JFET region130by way of the opening145.

Alternatively, referring toFIG.5, the first part141may contact only part of the total area of the lowermost surface of the source150(e.g., along the width direction), while the second part143may contact the entire lowermost surface of the base151(e.g., along the width direction). Due to this, the source150may contact the JFET region130by way of the opening145.

In a further alternative, referring toFIG.6, the first part141and the second part143may both contact only parts of the total areas of the lowermost surfaces of the source150and the base151(e.g., in the width direction), respectively, so that part of the source150and part of the base151may both contact the JFET region130through the opening145.

Referring back toFIG.3, as previously mentioned, when the opening145has an island type shape or arrangement, for example, the shield region140may contact the entire lowermost surfaces of the source150and the base151between adjacent openings145(e.g., along the length direction), or be continuous along the width direction.

As such, the shield region140may be discontinuous along a direction from the source150to the base151, so that the cross-sectional area or volume of the JFET region130may be relatively large (e.g., in comparison with an otherwise identical device in which the shield region140does not contain any openings), and thus the on-resistance characteristics of the JFET region130may improve.

In addition, during the reverse operation of the device1, the opening145may result in a PNP structure (e.g., a “sandwich” structure) comprising the first part141of the shield region140(having the first conductivity type), the JFET region130(having the second conductivity type) in the opening145, and the second part143of the shield region140(having the first conductivity type) along the width direction. Due to built-in field resulting from such a sandwich structure, the JFET region130in the opening145is completely depleted, so that the normally-off characteristics of the device1may achieved. In this case, the device1may be able to withstand or tolerate high voltages as a result of the depletion between the shield region140and the drift region110therebelow.

Referring again toFIGS.2to4, the heavily doped region153may be adjacent to or in contact with the source150and on a side of the source150opposite from the base151. The heavily doped region153may be on or in the drift region110or the JFET region130, and may comprise, for example, a region heavily doped with impurities having the first conductivity type.

In addition, the gate160may be on the drift region110or the JFET region130. The gate160may at least partially overlap the shield region140and the source150.

The gate160may include a gate oxide layer161on the JFET region140and a gate electrode163on the gate oxide layer161. The gate oxide layer161may also be on the base151and at least part of the source150. The gate electrode163may comprise, for example, a polysilicon layer doped with impurities. In addition, an insulating layer165may surround the gate electrode163and the gate oxide layer161. The insulating layer165covers sidewalls of the gate electrode163and may at least partially cover an upper surface of the gate electrode163(e.g., the insulating layer165may have an opening therein for a conductive contact or via to contact the gate electrode163). The gate160may have a stripe (e.g., rectangular) and/or planar shape, but the scope of the present disclosure is not limited thereto.

The source metal170may be on or over the substrate101, the JFET region130, the source150, and/or the heavily doped region153. The source metal170may cover the insulating layer165, and may include nickel (Ni) or aluminum (Al), but is not limited thereto. The source metal170may make ohmic contact with the source150and the heavily doped region153.

The drain metal180may be on the lowermost surface of the substrate101. The drain metal180may be electrically connected to a drain terminal (not shown). For example, the drain metal180may include nickel (Ni) or silver (Ag), but is not limited thereto.

FIG.7is a plan view of a silicon carbide power semiconductor device according to a second embodiment of the present disclosure;FIG.8is a cross-sectional view of the silicon carbide power semiconductor device ofFIG.7along the line CC ‘inFIG.7; andFIG.9is a cross-sectional view of the silicon carbide power semiconductor device ofFIG.7along the line D-D’ inFIG.7.

Hereinafter, a silicon carbide power semiconductor device2according to a second embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. For the structures in the silicon carbide power semiconductor device2according to the second embodiment that are substantially the same as in the device1according to the first embodiment, a “2” is written at the beginning of the identification number in the drawings, instead of the number “1”, and additional explanations related to this will be omitted. In the silicon carbide power semiconductor device2according to the second embodiment, only the shield region240, which is different from that of the first embodiment, will be described in detail.

Referring toFIGS.7to9, the present disclosure relates to a silicon carbide power semiconductor device2and, more particularly, to the silicon carbide power semiconductor device2including a continuous shield region240(e.g., that is continuous along the width direction), but which exposes parts of the lowermost surface of the base251, thereby improving the on-resistance characteristics of the device2.

Referring toFIG.7, the shield region240according to the second embodiment may have at least one sidewall with a concave-convex or sawtooth shape, or that contains a series of alternating square or rectangular projections and recesses, along the length direction. it may be preferable that the entire sidewall of the shield region240has the concavo-convex shape or the series of alternating square or rectangular projections and recesses. That is, the shield region240may have a plurality of protrusions240aand a plurality of recesses240balong the length direction, and for example, the protrusions240aand the recesses240bmay alternate and repeat. At this time, the term “protrusion” refers to a structure protruding or extending toward a central axis or plane of the gate260along the length direction in a plan view (e.g.,FIG.7), and “recess” refers to a structure that complements the protrusion along the length and/or width direction in the plan view. At this time, the shield regions240on opposite sides of the gate160inFIG.7may be symmetrical or asymmetrical along the central axis or plane of the gate160in the length direction. In the asymmetrical case, the shield regions240may be offset so that the protrusions240aon one side face the recesses240bon the other side along the length direction. In addition, although inFIG.7, the sidewalls having the protrusions240aand the recesses240bare shown, some or all of the sidewalls may have a curved shape, and the scope of the present disclosure is not limited by a specific shape.

Referring toFIGS.7and8, the protrusion240amay contact the entire lowermost surfaces of the source250and the base251along the width direction. That is, the protrusion240amay extend to a boundary or interface between the base251and the JFET region230or to a point adjacent to the boundary or interface. Accordingly, the protrusion240amay contact the entire lower potion of the base251along the width direction, but may contact only a part of the lowermost surface of the base251in some cases. That is, it is sufficient that the sidewall of the protrusion240ais closer to the center of the gate260than the sidewall of the recess240b.

Referring toFIGS.7and9, the shield region240adjacent to the recess240balong the width direction generally contacts the entire lowermost surface of the source250, but the recess240bexposes at least part of the lowermost surface of the base251to the JFET region130. Since the shield region240according to the second embodiment is continuous along the width direction, the lowermost surface of the base251adjacent to the JFET region230along the width direction may be exposed to the JFET region230thereunder.

In this way, as the shield region240has recesses240btherein, the cross-sectional area or volume of the JFET region230may be relatively large, and thus, the on-resistance of the JFET region230may improve.

Furthermore, during the reverse operation of the device2, a PNP structure comprising the shield region240(specifically, the protrusion240ahaving the first conductivity type), the JFET region130(having the second conductivity type), and another part of the shield region240(specifically, another protrusion240ahaving the first conductivity type) may be along the length direction. Due to a built-in field resulting from such a PNP structure, the JFET region130between the adjacent protrusions240ain the length direction is completely depleted, to achieve the normally-off characteristics of the device2. In this case, the device2may be able to withstand or tolerate high voltages as a result of the depletion between the shield region240and the drift region210therebelow.

The above detailed description is illustrative of the present disclosure. In addition, the above description shows and describes various embodiments of the present disclosure, and the present disclosure can be used in various other combinations, modifications, and environments. In other words, changes or modifications are possible within the scope of the concept of the disclosure herein, the scope equivalent to the disclosure, and/or within the scope of skill or knowledge in the art. The above-described embodiments describes various states for implementing the technical idea of the present disclosure, and various changes for specific applications or fields of use of the present disclosure are possible. Accordingly, the detailed description of the present disclosure is not intended to limit the present disclosure to the disclosed embodiments.