TERNARY QUANTUM STATE READOUT USING BINARY-OUTCOME MID-CIRCUIT MEASUREMENTS

A device comprises memory that is configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to measure a quantum state of a quantum bit. In performing the process, the processing circuitry is configured to: cause a sequence of operations to be performed on the quantum bit, the sequence of operations comprising at least a first binary-outcome measurement operation, a quantum state-inverting gate operation, and a second binary-outcome measurement operation; and determine a ternary measurement outcome, as the quantum state, based at least in part on discriminated binary-outcome measurements that result from the first binary-outcome measurement operation and the second binary-outcome measurement operation.

BACKGROUND

This disclosure relates generally to quantum computing and, in particular, techniques for readout of ternary states of quantum information-storing units such as superconducting quantum bits (qubits). A quantum computing system can be implemented using a superconducting quantum processor which comprises an array of superconducting qubits, such as transmon qubits, to generate and process quantum information. Various types of quantum information processing operations (e.g., gate operations) can be performed in which superconducting qubits can be coherently controlled, placed into quantum superposition states (via, e.g., single-gate operations), exhibit quantum interference effects and become entangled with one another (via, e.g., entanglement gate operations).

Typically, quantum computing systems are configured to process quantum information that is encoded in a computational basis (|0or |1) of the qubits, wherein gate operations are performed using the two lowest energy levels of a qubit including a ground state |0and a first excited state |1. A single qubit can have a basis state of |0or 1, or a linear combination of such basis states, which is known as a superposition state. In addition, quantum information can be encoded through entangled basis states of multiple qubits. On the other hand, some quantum systems are specifically configured to operate with quantum ternary digits (alternatively, quantum trits (qutrits)), wherein each qubit comprises a unit of quantum information having three states, including the ground state |0, the first excited state |1, and a second excited state |2, or a superposition of the three states |0, |1, |2.

While a two-level quantum system of qubits is typically designed and calibrated to operate in the computational subspace |0and |1there are instances where it may be desirable to measure the quantum state probability in a higher energy substrate (e.g., second excited state |2) for purposes of characterizing system error (e.g., characterizing leakage to the second excited state |2resulting from gate operations in the computational subspace), or otherwise implementing a ternary quantum computation which fully utilizes the three states of |0, |1, |2. However, a standard measurement instruction provided by a quantum computing system only distinguishes probabilities in the computational subspace |0and |1, where readout control circuit of the quantum system is calibrated to readout and discriminate between |0and |1states. On the other hand, in order to process ternary measurement outcomes, e.g., measuring |0, |1, and |2state probabilities would require a modification of the existing microarchitecture and instruction set of a standard quantum computer that is configured to perform computations and measurements in the computational basis. The basic measurement instruction set for a quantum computer includes measurements only at the end of a circuit, however, more advanced sets include partial measurements (i.e., measurements of a subset of qubits) inside the quantum circuit, which are known as mid-circuit measurements.

SUMMARY

Exemplary embodiments of the disclosure include techniques for measuring ternary quantum states of quantum information-storing units, such as quantum bits, using binary-outcome measurements. For example, an exemplary embodiment includes a device which comprises memory that is configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to measure a quantum state of a quantum bit. In performing the process, the processing circuitry is configured to: cause a sequence of operations to be performed on the quantum bit, the sequence of operations comprising at least a first binary-outcome measurement operation, a quantum state-inverting gate operation, and a second binary-outcome measurement operation; and determine a ternary measurement outcome, as the quantum state, based at least in part on discriminated binary-outcome measurements that result from the first binary-outcome measurement operation and the second binary-outcome measurement operation.

Advantageously, the processing circuitry is configured to measure ternary outcomes (e.g., readout of |0, |1, and |2states) in a quantum system that is configured for binary-outcome measurement and readout of, e.g., a quantum bit in a computational basis of binary states (e.g., |0and |1states), while enabling measurements of a higher energy level (e.g., excited state |2of the quantum bit for purposes of computation and/or determining leakage, without modifying the existing microarchitecture and instruction set of the standard quantum computer which is utilized by the processing circuit to perform computations and measurements in the computational basis.

Another exemplary embodiment includes a system which comprises a quantum processing unit, and a computing system. The quantum processing unit comprise a quantum processor comprising an array of quantum bits, and a control system configured to control operation of the quantum processor. The computing system is configured to utilize the quantum processing unit to perform quantum computing algorithms. The computing system comprises memory that is configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to measure a quantum state of a quantum bit of the quantum processor. In performing the process, the processing circuitry is configured to: generate control signals that are applied to the control system of the quantum processing unit to cause the control system to perform a sequence of operations on the quantum bit, the sequence of operations comprising at least a first binary-outcome measurement operation, a quantum state-inverting gate operation, and a second binary-outcome measurement operation; and determine a ternary measurement outcome, as the quantum state, based at least in part on discriminated binary-outcome measurements that result from the first binary-outcome measurement operation and the second binary-outcome measurement operation.

Another exemplary embodiment includes a computer program product for performing a process to measure a quantum state of a quantum bit. The computer program product comprises one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media. The program instructions comprise: program instructions to cause a sequence of operations to be performed on the quantum bit, the sequence of operations comprising at least a first binary-outcome measurement operation, a quantum state-inverting gate operation, and a second binary-outcome measurement operation; and program instructions to determine a ternary measurement outcome, as the quantum state, based at least in part on discriminated binary-outcome measurements that result from the first binary-outcome measurement operation and the second binary-outcome measurement operation.

In another exemplary embodiment, as may be combined with the preceding paragraphs, the quantum state-inverting gate operation comprises a quantum X gate operation that is configured to flip a state the quantum bit in a computational state spanned by a ground state |0and a first excited state |1, and the first binary-outcome measurement operation and the secondbinary-outcome measurement operation are each performed using a mid-circuit measurement operation.

In another exemplary embodiment, as may be combined with the preceding paragraphs, the processing circuitry is configured to: receive a ternary measurement instruction; and translate the ternary measurement instruction into the sequence of operations to be performed on the quantum bit.

In another exemplary embodiment, as may be combined with the preceding paragraphs, the processing circuitry is configured to: cause the sequence of operations to be repeated for a specified number of times; for each sequence of operations that is performed, determine an associated single-shot ternary measurement outcome based on discriminated binary-outcome measurements that result from the sequence of operations; and determine the ternary measurement outcome based on a plurality of single-shot ternary measurement outcomes obtained as a result of the repeated sequence of operations.

In another exemplary embodiment, as may be combined with the preceding paragraphs, for each sequence of operations that is performed, the processing circuitry is configured to determine the associated single-shot ternary measurement outcome by performing a statistical analysis of the discriminated binary-outcome measurements to estimate the single-shot ternary measurement outcome.

In another exemplary embodiment, as may be combined with the preceding paragraphs, for each sequence of operations that is performed, the processing circuitry is configured to determine the associated single-shot ternary measurement outcome by utilizing a hardware-based sequential logic circuit to process the discriminated binary-outcome measurements.

Other embodiments will be described in the following detailed description of exemplary embodiments, which is to be read in conjunction with the accompanying figures.

DETAILED DESCRIPTION

Exemplary embodiments of the disclosure will now be described in further detail with regard to quantum computing systems which are configured to enable readout of ternary states of quantum information-storing units such as superconducting qubits or trapped-ion qubits. More specifically, exemplary embodiments as described herein include techniques for implementing ternary state readout (e.g., readout of |0, |1, and |2states) in a quantum system that is configured for qubit state readout of qubits in the computational basis (e.g., |0and |1states), while enabling measurements of the second excited state12) for purposes of computation and/or determining leakage, without modifying the existing microarchitecture and instruction set of the standard quantum computer configured to perform computations and measurements in the computational basis.

It is to be understood that the various features shown in the accompanying drawings are schematic illustrations that are not drawn to scale. Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. Further, the term “exemplary” as used herein means “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not to be construed as preferred or advantageous over other embodiments or designs.

Further, it is to be understood that the phrase “configured to” as used in conjunction with a circuit, structure, element, component, or the like, performing one or more functions or otherwise providing some functionality, is intended to encompass embodiments wherein the circuit, structure, element, component, or the like, is implemented in hardware, software, and/or combinations thereof, and in implementations that comprise hardware, wherein the hardware may comprise quantum circuit elements (e.g., quantum bits, coupler circuitry, etc.), discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), one or more integrated circuits, and/or combinations thereof. Thus, by way of example only, when a circuit, structure, element, component, etc., is defined to be configured to provide a specific functionality, it is intended to cover, but not be limited to, embodiments where the circuit, structure, element, component, etc., is comprised of elements, processing devices, and/or integrated circuits that enable it to perform the specific functionality when in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving an input, and/or producing an output), as well as cover embodiments when the circuit, structure, element, component, etc., is in a non-operational state (e.g., not connected nor otherwise deployed in a system, not powered on, not receiving an input, and/or not producing an output) or in a partial operational state.

As is known in the art, quantum computing provides a computing paradigm which utilizes fundamental principles of quantum mechanics to perform computations. Quantum computing algorithms and applications are defined using quantum circuits. A quantum circuit is a computational routine which defines coherent quantum operations that are performed on quantum data that is stored in quantum bits, in conjunction with operations that are performed using classical computation. Quantum circuits are utilized to define complex algorithms and applications in an abstract manner, which can be executed on a quantum computer. In a quantum computer, primitive operations comprise gate operations (e.g., single-qubit gate operations, two-qubit gate operations, multi-qubit gate operations (e.g., 3 or more qubits) that are applied to qubits, to perform quantum computing operations for a given application. The quantum circuits allow a quantum computer to receive classical data, perform quantum operations based on the received data, and output a classical solution.

As noted above, a single qubit can have a basis state of |0or |1, or a linear combination of such basis states, which is known as a superposition state. As is known in the art, the state of a qubit can be graphically represented as a point on unit sphere (radius=1), which is called the Bloch sphere, with X, Y, and Z axes. The basis state |0(referred to as ground state) of a qubit is represented at a point (north pole) on a positive Z-axis of the Bloch sphere, while the basis state or |1(referred to as first excited state) of a qubit is represented at a point (south pole) on a negative Z-axis of the Bloch sphere. A superposition state |ψof the qubit can be represented as a point on the Bloch sphere as follows:

where the terms

correspond to the amplitude probabilities associated with the respective states |0and |1, and wherein the term eiϕcorresponds to a relative phase between the states |0and |1. The position of a point on the Bloch sphere representing a superposition state of a qubit is determined based on the angles θ and ϕ. The angle θ influences the probability of observing a qubit state of |0or |1when the qubit is read, wherein the probability of reading a qubit state of |1increases as θ increases. The angle ϕ influences the relative phase between the states |0and |1. For example, when θ=0, the qubit is in the ground state |0, which provides a 100% probability of observing a qubit state of |0when the qubit state is read. In addition, when θ=π, the qubit is in the first excited state |1), which provides a 100% probability of observing a qubit state of |1when the qubit state is read. On the other hand, when

and ϕ=0, the qubit is in a state at point on the positive X-axis of the Bloch sphere, and when

the qubit is in a state at a point on the positive Y-axis of the Bloch sphere.

The state of a given qubit can be changed by applying a single-qubit gate operation to the given qubit, which causes the current state of the qubit to rotate around, e.g., the X-axis, Y-axis, and/or Z-axis, etc., depending on the given gate operation. A rotation about the Z-axis results in a change in the angle ϕ. In addition, qubits can be controlled using entanglement gate operations to entangle the states of two or more qubits and, thereby, generate a combined state of two or more qubits, which contains more information than the individual states of the qubits. Entanglement allows multiple qubits in a superposition to be correlated with each other in a way that the state of one qubit can depend on the state of another qubit such that more information can be encoded with multiple entangled qubits as compared to encoding the qubits individually. Accordingly, quantum information processing, based on principles of superposition and entanglement states of qubits, allows quantum computers to solve difficult problems that are intractable using conventional computers.

Furthermore, as noted above, a qutrit is a quantum system which consists of three levels (states) spanned by e.g., the |0, |1, and |2states. The quantum state of a qutrit system may be represented by |ψ=a0|0+a1|1+a2|2, where the coefficients a0, a1, and a2are complex probability amplitudes, where the sum of squares of such coefficients is unity (normalization): |a0|2+|a1|2+|a2|2=1. Ternary quantum computing systems using superconducting qutrits are considered to be promising alternatives to binary quantum computing systems for various reasons. A ternary quantum computing system, however, is specifically designed with a measurement instruction set and microarchitecture that is configured to execute qutrit measurement instructions and processes ternary measurement outcomes.

Furthermore, to implement high-fidelity single-shot qutrit readout operations, the qutrit readout signal (readout stimulus signal) and readout signal chain for the ternary quantum computing system is specifically engineered to readout and discriminate the |0, |1, and |2states with small assignment error. For example, a ternary state discrimination process can be implemented using a computationally expensive math library to determine nonlinear classification boundaries. In this instance, raw phasor signals (IQ data), which are obtained by performing multiple single shot qutrit readout operations, are transmitted from the control circuitry of quantum processing unit to a host processor of the ternary quantum computing system, where the processor executes a software-based ternary state discriminator process to discriminate the |0, |1, and |2states. Such software-based state discrimination is time consuming (as compared to hardware-based state discriminator) and consumes a significant amount of communication bandwidth to transmit the IQ data to the host processor.

On the other hand, as noted above, quantum computing systems are commonly configured to process quantum information that is encoded in a computational subspace that spans the |0and |1states, wherein the two lowest energy levels of qubits spanned by the |0and |1states are utilized for gate operations. In this regard, a binary quantum computing system is specifically designed with a measurement instruction set and microarchitecture that is configured to execute qubit measurement instructions and processes binary measurement outcomes. For example, a standard measurement instruction and microarchitecture of a binary quantum computing system is only configured to measure and distinguish qubit state probabilities in the computational basis states |0and |1.

Currently, in superconducting quantum computing systems, a transmon is a type of quantum information-storing unit that is commonly used to implement superconducting quantum processors. A transmon comprises a superconducting Josephson junction connected in parallel with a capacitor. The Josephson junction functions as a non-linear inductor which, when shunted with the capacitor, forms an anharmonic LC oscillator with individually addressable energy levels (e.g., two lowest energy level corresponding to the ground state |0and the first excited state |1). While transmons are typically operated as two-level systems (qubits), transmons have readily addressable higher energy levels as a result of their anharmonicity characteristics, which allows the transmons to be operated as three-level systems (qutrits). In this regard, transmons can be utilized to implement a ternary quantum computing platform which can perform qutrit quantum computations in the computational subspace that spans the |0, |1, and |2states.

On the other hand, in a two-level quantum computing system where superconducting qubits (e.g., transmon qubits) are configured to operate in the computational subspace that that spans the |0and |1states, the ability to measure higher energy state probabilities is important to characterize errors of the two-level quantum system. For example, measuring quantum information in the |2state population is crucial to detect leakage errors that occur as a result of gate calibration operations and the execution of quantum algorithms. Indeed, gate operations that are performed on qubits in the computational subspace spanned by the |0and |1states can actually cause energy leakage to the |2state and, consequently, the measurement of |2state probabilities is important to characterize leakage errors. In this regard, to measure the |2state probability in a two-level quantum computing system that is specifically configured to distinguish state probabilities in the computational basis states of |0and |1, the two-level quantum computing system would typically need to be reconfigured to implement a custom measurement instruction and modified microarchitecture to execute ternary state readout operations and process ternary measurement outcomes, which is undesirable.

As noted above, exemplary embodiments of the disclosure include techniques to enable ternary state readout and measurement operations (e.g., readout and measurement of |0, |1and |2states) in a two-level quantum computing system without having to modify the existing microarchitecture and instruction set of the two-level quantum computer system. Such techniques generally include a process to determine a ternary state of a qubit by performing a ternary state readout process that generally includes performing a sequence of operations comprising (i) performing two or more binary-outcome measurements operations using mid-circuit measurement techniques, with an X-gate operation (alternatively referred to as “quantum NOT gate operation”) perform between two binary-outcome measurements to flip (invert) the state of the qubit between the ground |0and first excited |1states, or flip a superposition of the |0and |1states, and (ii) analyzing the two or more binary-outcome measurements to determine a ternary measurement outcome. As explained in further detail below, the exemplary ternary measurement protocols as discussed herein generated bit sequences that contain ternary state information in a format that is efficiently handled and processed using a standard micro-architecture of a commercial quantum computer.

It is to be noted that the term “binary-outcome measurement” as used herein denotes a measurement for an outcome M=E, 1−E, where E is some observable. For example, in some embodiments, a binary-outcome measurement instruction is configured to implement a positive operator-valued measure (POVM) of {|00|1−|0|}, wherein a state discriminator is calibrated to classify a given measurement outcome as a |0state or a NOT |0state, in which a given classification of NOT |0classifies a |1state and |2state into a same outcome classification (e.g., a |1state). In other embodiments, a binary-outcome measurement instruction is configured to implement a POVM of {|11|, 1−|1|}, wherein a state discriminator is calibrated to classify a given measurement outcome as a |1state or a NOT |1state, in which the NOT |1state classifies a |0state and |2state into a same outcome classification (e.g., a |0state).

In addition, the term “mid-circuit measurement” is a specification of a type of measurement which enables the quantum system to measure an outcome in the middle of a quantum circuit. In particular, a mid-circuit measurement is a unique feature that allows qubits to be selectively measured at some point other than the end of a quantum circuit. This is identical to the standard measurement from a viewpoint of measurement theory, but utilizes high-speed control electronics to process the readout measurement signals in real time.

In addition, in the context of the exemplary embodiments discussed herein, a “mid-circuit measurement” is performed using a quantum non-demolition (QND) measurement, which preserves the physical integrity of the system, wherein the a given state of a qubit can be measured (and thus preserved) without collapsing the state of the qubit as a result of the measurement. In a typical superconducting processor, a QND measurement is implemented using a dispersive readout scheme, where the quantum state of a give qubit is indirectly measured by generating and applying a readout control signal to stimulate a readout resonator that is coupled to the given qubit, and then analyzing a readout signal that is returned from the readout resonator to indirectly characterize the qubit state from the resonator transfer function. The readout signal that is returned from the stimulated readout resonator comprise a state-dependent phasor response (which is represented by a I and Q signal components of a complex phasor vector), in which the quantum state of the given qubit can be discriminated by analyzing the amplitude and phase of the readout signal. However, this amplitude and phase have broad distribution because of the noise in the amplifiers, and this sometime leads to the assignment error due to an overlap of signal distributions of different states.

FIG.1schematically illustrates a system that is configured to measure ternary quantum states using binary-outcome mid-circuit measurement operations, according to an exemplary embodiment of the disclosure. In particular,FIG.1schematically illustrates a quantum computing system100which comprises a client110(e.g., user laptop computer, desktop computer, or other user computing device) that generates program instructions120(alternatively, input quantum circuit120) to perform quantum information processing, a quantum compiler130, a quantum processing unit (QPU)140, and a shot controller150. The shot controller150is configured to control the execution of a compiled quantum circuit160using the quantum processing unit140. The shot controller150comprises a ternary outcome estimator module170, a multi-shot outcomes aggregation module180, and an optional error mitigation module190, the function of which will be described in further detail below.

As schematically shown inFIG.1, the program instructions120are depicted as an input quantum circuit which comprises a single qubit q, a single classical bit c, and an ordered sequence of operations that are performed on the qubit q including a U gate operation122and a measurement operation124. The measurement operation124comprises a qutrit measurement instruction MQUTRIT, and the qutrit measurement is mapped to the classical bit (c). The program instructions further specify run-time execution parameters including, but not limited to, a first parameter N which specifies a number of times to repeat a mid-circuit measurement (MCM) associated with the qutrit measurement instruction MQUTRIT, and a second parameter NSwhich specifies a number of single-shot ternary outcome measurements to perform in connection with the qutrit measurement operation, the details of which will be explained in further detail below.

The U gate operation122is a gate that performs a rotation around the Bloch sphere with three Euler angles, which are denoted θ, λ, and ϕ. The operation of the U gate can be described with the following matrix:

The parameters of the U gate can be selected to replicate any other single qubit gate operation. For example, the U gate can be configured to replicate a Pauli-X gate by setting the parameters of the U matrix to be: θ=π, ϕ=π, and

As another example, the U gate can be configured to replicate a Hadamard gate by setting the parameters of the U matrix to be:

ϕ=0, and λ=π. In this regard, the U gate operations shown inFIG.1are meant to generically represent any type of single gate operation performed on the qubit q, depending on the parameters of the U matrix.

The quantum compiler130comprises a quantum circuit compiler which is configured to translate the input quantum circuit120(or program instructions) into an optimized quantum circuit using, e.g., a native set of gates that are supported by a backend quantum computing service, e.g., computer simulator, or a quantum computing system comprising the quantum processing unit140. In some embodiments, the quantum compiler130implements a transpilation process that is configured to rewrite a given input circuit to match the topology of a specific quantum device, and/or to optimize the circuit for execution by the quantum processing unit140. For example, in the context of the exemplary embodiments discussed herein, the quantum compiler130is configured to decompose or otherwise translate the qutrit measurement instruction MQUTRITof the input quantum circuit120into a sequence of Mmcm(N)=[μ·X01]N·μ, wherein μ denotes a binary outcome measurement instruction with, a positive operator-valued measure (POVM) of {|00|, 1−|0|}, and wherein X91denotes an X gate instruction to flip (invert) the state of the qubit between the ground |0and first excited |1states, or flip a superposition of the |0and |1states. In other words, an X gate instruction performs a quantum state-inverting gate operation (or quantum X gate operation) that is configured to flip a state a quantum bit in a computational state spanned by a ground state |0and a first excited state |1.

More specifically, as illustrated inFIG.1, the quantum compiler130translates the input quantum circuit120(program instructions) into the compiled quantum circuit160which is executed under control of the shot controller150to perform the qutrit measurement using binary-outcome mid-circuit measurement operations. The compiled quantum circuit160comprises a sequence of quantum operations161that are performed on the qubit q, and a classical bit register, denoted cregO, to store measurement results. The sequence of quantum operations161comprises an initial U gate operation162, binary-outcome measurement (BOM) operations1641,1642, . . . ,164N+1, and X gate operations1661, . . . ,166N. For ease of explanation, it is assumed that the U gate operation162of the compiled quantum circuit160is the same as the U gate operation122of the input quantum circuit120. On the other hand, the measurement instruction124of the input quantum circuit120is compiled into the sequence of binary-outcome measurement operations1641,1642, . . . ,164N,164N+1, and X gate operations1661, . . . ,166N, as shown. The binary-outcome measurement operations1641,1642, . . . ,164N,164N+1are mapped to respective classical bits c0, c1, . . . , cN−1, cNof the bit register cregO.

In the exemplary embodiment ofFIG.1, the binary-outcome measurement operations1641,1642, . . . ,164Ncomprise binary-outcome mid-circuit measurement operations which are followed by respective X gate operations1661, . . . ,166N, while the binary-outcome measurement operation164N+1represents a final binary-outcome measurement for the given single-shot ternary measurement iteration.FIG.1schematically illustrates an exemplary embodiment in which the compiled quantum circuit160comprises N instances of the sequence [μ·X01] of operations, i.e., [1641·1661], . . . [164N·166N], which is followed by the final binary-outcome measurement164N+1. In an exemplary embodiment where N=1 the sequence of operations for qutrit state readout would include the sequence: mid-circuit binary-outcome measurement operation1641→X gate operation1661→final mid-circuit binary-outcome measurement operation1642, and the classical bit register cregOwould include only classical bits c0and c1to store the results of the binary-outcome measurement operations1641and1642, respectively.

The shot controller150runs the compiled quantum circuit160by, e.g., generating and applying control signals to the quantum processing unit140to perform the U gate operation162, the X gate operations1661, . . . ,166N, and the binary-outcome measurement operations1641,1642, . . . ,164N,164N+1, The quantum processing unit140is essentially a quantum computer which comprises one or more quantum chips which comprise an array of interconnected qubits and other quantum devices and components, e.g., qubit couplers, qubit control lines, qubit readout resonators, etc., and control circuitry (e.g., CMOS ASICS), which is coupled to the quantum chips via input signal chains and readout signal chains readout lines. The control circuitry is configured to generate qubit control signals and qubit readout control pulses in response to instructions from the shot controller150to perform qubit gate operations and qubit state readout operations, etc., the details of which will be explained in further detail below in conjunction withFIGS.3and4.

As noted above, each binary-outcome measurement operation1641,1642, . . . ,164N,164N+1is performed using a quantum non-demolition measurement operation (via a dispersive readout of the qubit state) to measure the state of the qubit q and obtain a binary outcome measurement, wherein the state of the qubit q is measured as either |0or not |0(e.g., either |1or |2). Each binary-outcome mid-circuit measurement results in the assignment of a label “0” for a measured ground state |0or a label “1” for a measurement that is “not” the ground state |0, e.g., the first excited state |1or the second excited state |2. In other words, measurement of the second excited state |2is assigned a label of “1”.

Further, each X gate operation1661, . . . ,166Nis performed using a standard X gate operation in the computational basis for the |0and |1states. The X gate operation is a quantum NOT gate operation that essentially mirrors the qubit around the X-axis of the Bloch sphere, wherein the qubit is rotated 180 degrees round the X axis. In this regard, the X gate operation swaps the ground state |0and the first excited state |1, while preserving the population of the second excited state |2. For example, with regard to the compiled quantum circuit160shown inFIG.1, assume that following the U gate operation162, the quantum state of the qubit q is in the second excited state |2. In this instance, the initial binary-outcome measurement operation1641will ideally result in a measurement of “1” due to the qubit q state being in the second excited state |2). In this state, applying the first X gate operation1661to the qubit q will not flip the state of the qubit q. As such, the next binary-outcome measurement operation1642will ideally result in a measurement of “1” such that the initial 1, 1 measurement indicates that the quantum state of the qubit q (following the U gate operation162) was in the second excited state |2.

On the other hand, assume that following the U gate operation162, the quantum state of the qubit q is in the first excited state |1. In this instance, the initial binary-outcome measurement operation1641will ideally result in a measurement of “1” due to the qubit q state being in the first excited state |1. In this state, applying the first X gate operation1661to the qubit q will flip the state of the qubit q from the first excited state |1to the ground state |0. As such, the next binary-outcome measurement operation1642will ideally result in a measurement of “0” such that the initial 1, 0 measurements indicate that the quantum state of the qubit q (following the U gate operation162) was in the first excited state |1.

Similarly, assume that following the U gate operation162, the quantum state of the qubit q is in the ground state |0. In this instance, the initial binary-outcome measurement operation1641will ideally result in a measurement of “0” due to the qubit q state being in the ground state |0. In this state, applying the first X gate operation1661to the qubit q will flip the state of the qubit q from the ground state |0to the first excited state |1. As such, the next binary-outcome measurement operation1642will ideally result in a measurement of “1” such that the initial 0,1 measurements indicate that the quantum state of the qubit q (following the U gate operation162) was in the ground state |1.

The execution of a single iteration of the compiled quantum circuit160using quantum non-demolition measurements to obtain a sequence of mid-circuit measurement outcomes with a flip of the qubit state (via the X gate) between the ground and first excited states, results in the generation of a bitstream of discriminated binary outcomes BN={0,1}N+1which is represented by the logic states of the bits c0, c1, . . . , cN, cN+1in the classical bit register cregO. For a given iteration of the ternary measurement, the bitstream of discriminated binary outcomes stored in the bit c0, c1, . . . , cN, cN+1are read into and processed by the ternary outcome estimator module170.

The ternary outcome estimator module170is configured to estimate a single-shot ternary outcome O ∈{0,1,2}1based on the bitstream of discriminated binary outcomes BN={0,1}N+1that are generated from a single iteration of execution of the compiled quantum circuit160. In some embodiments, the ternary outcome estimator module170is implemented using sequential logic circuitry that is implemented in, e.g., a hardware accelerator, an exemplary embodiment of which will be discussed below in conjunction withFIG.3. In some embodiments, the ternary outcome estimator module170is implemented at least in part as a software module that implements a statistical analysis process to analyze the bitstream of discriminated binary outcomes to estimate a quantum state of the qubit q as being one of the |0, |1, and |2states.

For example, in some embodiments, the ternary outcome estimator module170implements any suitable statistical inference process, such as a maximum likelihood estimation (MLE) method, to estimate the quantum state of the qubit q based on the bitstream of discriminated binary outcomes. In general, MLE is a method of estimating the parameters of an assumed probability distribution, given some observed data, by maximizing a likelihood function so that, under the assumed statistical model, the observed data (i.e., bitstream of discriminated binary outcomes) is most probable. The MLE method selects the state estimate that gives the observed results with the highest probability.

The shot controller150performs multiple iterations of the execution of the compiled quantum circuit160based on the specified shot number NS. In some embodiments, the shot number shot NSis on the order of thousands (e.g., NS=1000, or 2000, etc.). For each iteration i=1, . . . , NS, the ternary outcome estimator module170determines the single-shot ternary outcome Oi. The multi-shot outcomes aggregation module180is configured to receive and aggregate the single-shot ternary outcomes [O1, O2, O3, . . . , ONS] into a probability distribution representation (e.g., histogram) of the ternary outcome (denoted, distribution of P[O]), i.e., the probability distribution P[O] of the possible quantum states |0, |1, and |2of the qubit q as determined over the NSsingle-shot iterations. For example, the probability distribution can be represented by the number of the single-shot ternary outcomes that estimated each of the possible quantum states |0, |1), and |2of the qubit q, e.g., {0: no, 1: n1, 2: n2}, where nodenotes a number single-shot ternary outcomes that were estimated to be the ground state |0, where n1denotes a number single-shot ternary outcomes that were estimated to be the first excited state |1, and where n2denotes a number single-shot ternary outcomes that were estimated to be the second excited state |2.

In some embodiments, the distribution of P[O] generated by the multi-shot outcomes aggregation module180is returned to the client110as the result of the ternary measurement. On the other hand, in some embodiments, to provide more precise results, the error mitigation module190is utilized to perform readout error mitigation with a pre-calibrated assignment matrix using known techniques. For example, a three-state assignment matrix can be constructed and utilized to perform error mitigation using the probability distribution P[O] of the single-shot ternary outcomes [O1, O2, O3, . . . , ONS] of the measured ternary quantum state. In some embodiment, a readout error mitigation is performed by measuring an assignment matrix A with quantum detector tomography. The quantum state preparation and measurement errors can then be mitigated by applying the inverse of the assignment matrix to the measurement results, and then the most probable physical state is acquired using any suitable process. In particular, a mitigated probability p is derived by p′=A−1·pnoisy, where an invalid probability p00MXMcan be considered by the assignment matrix. The term p00MXMdenotes a probability of measuring a “0” from both mid-circuit measurements in the sequence mid-circuit measurement→X gate→mid-circuit measurement (MXM) with N=1.

As noted above, in some embodiments, the ternary outcome estimator module170can be implemented in hardware using sequential logic circuitry. For example, in an exemplary embodiment in which the ternary measurement operation comprises N=1 instance of the sequence [μ·X01] of measurement and state flip operations, and wherein the classical bit register cregOcomprises two bits, c0and c1, a sequential logic circuit such as shown inFIG.2can be utilized to determine the single-shot ternary outcome Oifor each ternary measurement iteration performed by the shot controller150. For example,FIG.2schematically illustrates a system that is configured to measure quantum states of a ternary quantum system, according to another exemplary embodiment of the disclosure. In particular,FIG.2schematically illustrates a quantum computing system200which is similar to the quantum computing system100ofFIG.1, except that theFIG.2illustrates an exemplary embodiment where the qutrit measurement instruction MQUTRITof the input quantum circuit120is translated/decomposed into a sequence of Mmcm(N)=[μ·X01]N. μ, where N=1, and where the shot controller140implements a ternary outcome estimator logic circuit270(e.g., implemented by a hardware accelerator) that is configured to determine a single-shot ternary outcome Oifor each ternary measurement iteration performed by the shot controller150.

FIG.2schematically illustrates a compiled quantum circuit260which comprises a sequence of quantum operations261that are performed on the qubit q, and a classical bit register, denoted cregO, to store measurement results. The sequence of quantum operations261comprises an initial U gate operation262, binary-outcome measurement operations2641and2642and an X gate operation266(alternatively, quantum NOT gate operation266), which perform the same functions/operations as discussed above. The binary-outcome measurement operation2641is mapped to the classical bit c0, and the binary-outcome measurement operation2642is mapped to the classical bit c1. For a given iteration of the ternary measurement performed by the shot controller150, the bitstream of discriminated binary outcomes stored in the bit c0and c1are read out and input to the ternary outcome estimator logic circuit270.

The ternary outcome estimator logic circuit270comprises a plurality of AND logic gates271,272, and273, and a plurality of NOT logic gates274and275(or inverters). As schematically illustrated inFIG.2, the AND gate271comprises a first input that receives the logic level of the first bit c0, and a second input that receives the logic level of the second bit c1. The AND gate272comprises a first input that receives the logic level of the first bit c0, and a second input that is coupled to an output of the NOT gate274such that the second input of the AND gate272receives an inverted logic level of the second bit c1. The AND gate273comprises a first input that is coupled to an output of the NOT gate275and receives an inverted logic level of the first bit c0, and a second input which receives the logic level of the second bit c1.

In this exemplary configuration, the AND gate271is configured to output a logic “1” level when the first and second bits c0and c1both have a logic “1” level, wherein the logic “1” level at the output of the AND gate271indicates a measured quantum state |2. The AND gate272is configured to output a logic “1” level when the first bit c0has a logic “1” level and the second bit c1has a logic “0” level, wherein the logic “1” level at the output of the AND gate272indicates a measured quantum state |1. Further, the AND gate273is configured to output a logic “1” level when the first bit c0has a logic “0” level and the second bit c1has a logic “1” level, wherein the logic “1” level at the output of the AND gate273indicates a measured quantum state |0. In the event that the first and second bits c0and c1both have a logic “0” level, the single-shot ternary outcome Oiis classified as having an unknown state.

The hardware-based ternary outcome estimator logic circuit270is configured to provide accelerated computation of each single-shot ternary outcome Oiand is particularly suited for instances where N=1, or possible some low number, e.g., N=2. In principle, N=1 is sufficient to determine the quantum state for each single-shot ternary measurement iteration. On the other hand, a mid-circuit binary-outcome measurement is not always accurate due to, e.g., quantum noise, or some error associated with the quantum state measurement operation. In this regard, increasing the number of instances of the [μ·X01]Nwhere N>1 serves to mitigate or otherwise eliminate noise contribution associated with the mid-circuit binary-outcome measurements. As noted above, when N>1, statistical analysis methods are preferable used to enable a more precise estimate of the measurement outcomes.

It is to be appreciated that performing a single-shot ternary measurement using a minimal sequence of operations, such as shown inFIG.2, comprising a first mid-circuit binary-outcome measurement operation2641, an X gate operation266, and a second mid-circuit binary-outcome measurement operation2642(referred to herein as an MXM sequence) serves to reduce the standard error or variance of the ternary measurement outcome, as compared to a measurement process based on combining two independent binary outcome measurement instances, i.e., a first circuit of [U-measure] and a second circuit of [U-X-measure]. The reduction in the standard deviation error or variance is based primarily on the fact that the first mid-circuit binary-outcome measurement operation2641results in measured state that collapses to a measured |0state or a measured |1state (which may be the first excited state |1or the second excited state |2, and that the second mid-circuit binary-outcome measurement operation2642, which is performed after applying the quantum NOT gate operation266on the qubit, provides a deterministic outcome. This deterministic feature serves to reduce the standard deviation or variance of the measurement based on one MXM sequence. By increasing the number of shots of the MXM sequence, a further decrease in the standard error variance is achieved. For example, it is to be noted that computer simulations have shown that a standard deviation of about 0.01 can be achieved by performing 1000 single-shot ternary measurements using the MXM sequence, while the same standard deviation of about 0.01 would be achieved by performing about 4500 single-shot ternary measurements using a single ternary measurement operation.

FIG.3schematically illustrates a quantum processing system comprising control circuitry that is utilized to measure ternary quantum states using binary-outcome mid-circuit measurements, according to an exemplary embodiment of the disclosure. More specifically,FIG.3schematically illustrates a quantum processing system300comprising qubit control circuitry302and qubit readout control circuitry304, which are configured to generate radio frequency (RF) control pulses to control the operation (gate operations, readout operation) of a superconducting qubit306(e.g., transmon qubit). The qubit control circuitry302and qubit readout control circuitry304implements a quadrature arbitrary waveform generator (AWG) system which is configured to generate control pulses using quadrature signals, wherein a quadrature signal comprises an in-phase (I) signal component, and a quadrature-phase (Q) signal component.

In some embodiments, the quantum processing system300schematically illustrates an exemplary architecture of the quantum processing unit140(FIGS.1and2) at least with respect to a portion of the control circuitry that is utilized to control the operation of one fixed-frequency superconducting qubit (e.g., qubit q inFIGS.1). In an exemplary implementation, the quantum processing unit140would have an array of qubits and qubit couplers to control/modulate exchange interaction between adjacent qubits to enable, e.g., entanglement operations, as well as additional control circuitry to control the operation (readout operations, gate operations) of the individual qubits, and control circuitry to generate flux bias control signal (e.g., static and dynamic flux bias control signal) to control operations of the qubit couplers, and tuning of flux-tunable qubits, etc., as is understood by one of ordinary skill in the art.

The qubit control circuitry302is configured to generate RF control pulses (denoted RF_Q) to control the operation, e.g., gate operations, state changes, etc., of the superconducting qubit306. In an exemplary embodiment, the qubit control circuitry302would receive and process qubit control signals from the shot controller process150(FIGS.1and2) to perform the U gate and X gate operations for a ternary state readout process. In particular, the qubit control circuitry302comprises a waveform generator310(or pulse envelope generator), digital-to-analog converter (DAC) circuitry311, low-pass filter circuitry312, an I/Q mixer313(upconverter mixer), a local oscillator (LO) signal generator314, and an RF signal chain315that couples the RF output of the I/Q mixer313to the qubit306. The RF signal chain315comprises one or more signal attenuators, a high pass filter, and transmission lines (e.g., coaxial cables, planar (printed) transmission lines, etc.). A capacitor316represents a qubit drive line that capacitively couples an RF control signal RF_Q from the RF signal chain315to the superconducting qubit306.

The waveform generator310is configured to receive a qubit control signal and generate digital I and Q signals having a given type of pulse envelope (e.g., Gaussian pulse envelope) for qubit control, in response to the qubit control signal. The DAC circuitry311is configured to convert the digital I and Q pulses into analog I and Q control pulses which are filtered by the low-pass filter circuitry312. The filtered analog control I and Q control pulses are applied to the I/Q mixer313, along with an LO signal (LINQ) that is generated by the LO signal generator314, to generate an RF control pulse RF_Q for qubit control. In particular, the I/Q mixer313is configured mix the analog I and Q control pulses with the LO_Q signals of a given LO frequency (e.g., 5 GHz) to perform I/Q modulation and upconversion using known techniques (e.g., single sideband modulation) to generate the RF qubit control signal RF_Q.

It is to be noted that the RF qubit control signal (RF_Q) for the superconducting qubit306comprises an RF control pulse which has a center frequency equal to a transition frequencies (denoted f01) of the superconducting qubit306, wherein the transition frequency f01corresponds to an energy difference between the ground state |0and excited state |1of the qubit. The RF_Q control signal comprises a shaped control pulse (e.g., Gaussian pulse) that is calibrated to drive f01transitions of the qubits, while suppressing f12and higher transitions. In addition, pulse-shaping techniques such as DRAG (derivative removal by adiabatic gate) correction pulses can be used in conjunction with shaped pulses (such as Gaussian pulses, cosine pulses, or hyperbolic secant pulses) to further suppress unwanted state transitions, while maintaining a same pulse envelope area (or integral of pulse envelope).

The RF qubit control signal RF_Q is applied to the superconducting qubit306to change the qubit state to perform single-qubit gate operations on the superconducting qubit306or otherwise modify the computational state of the superconducting qubit306as needed when performing certain operations, e.g., performing X gate operations to perform ternary measurements, as discussed above. The RF control signal RF_Q is configured to change the state of the superconducting qubit306by rotating the state of the qubit306about an axis in the Bloch sphere. Such rotations include X-axis rotations, Y-axis rotations, and/or rotations about any axis in the X-Y plane of the Bloch sphere, wherein the axis of rotation about a given axis of the Bloch sphere and the amount (angle) of such rotation are based, respectively, on the phase of the RF control signal RF_Q, and the amplitude and duration of the RF control signal RF_Q.

The qubit readout control circuitry304is configured to generate an RF readout control signal (RF_RO) to readout the state of the superconducting qubit306using a dispersive readout scheme which enables a quantum non-demolition measurement of the state of the superconducting qubit306to preserve the state of the superconducting qubit306. In an exemplary embodiment, the qubit readout control circuitry304would receive and process readout control signals from the shot controller process150(FIGS.1and2) to perform mid-circuit measurements for a ternary state readout process. The qubit readout control circuitry304comprises a waveform generator320(or pulse envelope generator), DAC circuitry321, low-pass filter circuitry322, a first I/Q mixer323(upconverter mixer), an LO signal generator324, an RF circulator325, a readout resonator326, and a readout signal chain which comprises a quantum-limited amplifier327, one or more filter and isolator components328, a second I/Q mixer329, analog-to-digital converter (ADC) circuitry330, and a discriminator331.

It is to be understood thatFIG.3is an exemplary non-limiting embodiment which schematically illustrates a two transmission (TX) port architecture having one TX port for qubit control (e.g., XY control) and one TX port for qubit readout. In other embodiments, the qubit control circuitry302and qubit readout control circuitry304can be implemented with a single TX port in which, e.g., the outputs of the I/Q mixers313and323are applied to inputs of a signal combiner circuit, and an output of the signal combiner circuit is coupled to a single transmission path which transmits RF_Q and RF_RO signals to the superconducting qubit306.

The waveform generator320is configured to receive and process and readout control signal to generate digital I and Q signals with a given type of pulse envelope (e.g., Gaussian square pulse envelope) for qubit state readout, in response to the readout control signal. The DAC circuitry321is configured to convert the digital I and Q pulses into analog I and Q control pulses which are filtered by the low-pass filter circuitry322. The filtered analog control I and Q control pulses are applied to the I/Q mixer323, along with an LO signal (LO_RO) that is generated by the LO signal generator324, to generate an RF readout control pulse RF_RO. In particular, the I/Q mixer323is configured mix the analog I and Q control pulses with the LO_Q signals of a given LO frequency (e.g., 7 GHz) to perform I/Q modulation and upconversion using known techniques (e.g., single sideband modulation) to generate the RF readout control pulse RF_RO.

The RF readout control signal RF_RO is applied to an input port of the RF circulator325, and then coupled to the readout resonator326. The readout resonator326is capacitively coupled to the superconducting qubit306, thereby providing a qubit/resonator system. In some embodiments, the readout resonator326comprises, e.g., a half-wavelength coplanar waveguide resonator, having a resonant frequency that is the same or similar to a center frequency of the RF readout control signal RF_RO. The resonant frequency of the readout resonator326is detuned from the transition frequency of the superconducting qubit306. In the dispersive regime of qubit-resonator coupling (with non, the RF readout control signal RF_RO (with the requisite frequency tone, pulse envelope shape, and pulse duration) interacts with the given qubit/resonator system in manner which result in the generation of a resulting readout signal RO that is reflected out from the readout resonator326, wherein the readout signal RO comprises information (e.g., phase and/or amplitude) that is qubit-state dependent. In other words, the dispersive readout process yields an RF readout signal RO having a state-dependent phasor response, which is analyzed to discriminate the quantum state of the superconducting qubit306. Again, the dispersive readout process provides a quantum non-demolition measurement which does not perturb or otherwise collapse the quantum state of the superconducting qubit306.

The readout signal RO that is returned from the readout resonator326is input to the RF circulator325, and then coupled out to the readout signal chain where the readout signal RO is amplified by the quantum-limited amplifier327, and then transmitted along a signal chain comprising the filter and isolator components328, and applied to an input of the second I/Q mixer329. The second I/Q mixer329mixes the RF readout signal RO with the LO_RO signal to perform a downconversion operation where the RF readout signal RO is downconverted and split into analog I and Q signals. The analog I and Q signals are input to the ADC circuitry330and sampled by the ADC circuitry330to generate respective digital I and Q signals that are indicative of the amplitude and phase of the readout signal RO. The discriminator331analyzes the digital I and Q signals to discriminate the measured quantum state of the superconducting qubit306based on the amplitude and phase components of the readout signal RO.

In some embodiments, the discriminator331comprises a hardware discriminator that is configured to discriminate binary-outcome measurements in the computational basis, e.g., discriminate between measured |1and |1states. In some embodiments, in the context of ternary state measurements, the discriminator331is calibrated to distinguish between a |0state and a NOT |0state (e.g., |1and |2states). For example,FIG.4schematically illustrates a process of discriminating between ternary states based on voltage levels of readout signals, according to an exemplary embodiment of the disclosure. In particular,FIG.4illustrates an exemplary two-dimensional (2D) scatter plot diagram400which shows different distributions401,402, and403of scatter points that represent single-shot readout signals in an IQ plane.

In the 2D scatter plot diagram400, for each single-shot readout signal, the X-axis represents in I-phase component (amplitude), and the Y-axis represent the Q-phase component (phase) of the single-shot readout signal. The distribution of scatter points401represents a plurality single-shot readout signals in the IQ plane with a qubit prepared in a |0state. The distribution of scatter points402represents a plurality single-shot readout signals in the IQ plane with the qubit prepared in a |1state. The distribution of scatter points403represent a plurality single-shot readout signals in the IQ plane with the qubit prepared in a |2state. As shown, different distributions of scatter points are obtained depending on the quantum state of the qubit.

In addition,FIG.4schematically illustrates a classification process410for a binary outcome measurement, which is performed by the hardware discriminator331based on a calibrated discrimination plane412(e.g., threshold voltage). The discrimination plane412represent a threshold digitizer voltage level (on the X-axis) of the ADC circuitry330to distinguish between |0state and a NOT |0state (e.g., |1and |2states), wherein single-shot readout signal having an I-component with a voltage level less than the threshold voltage412is classified as a “0” (e.g., classical bit set to a logic “0” level), and wherein a single-shot readout signal having an I-component with a voltage level greater than the threshold voltage412is classified as a “1” (e.g., classical bit set to a logic “1” level). With this exemplary configuration, a measurement outcome of a |0state is classified as “0” and a measurement outcome of a |1state or a |2state is classified as “1”, thereby providing the basis of a binary-outcome measurement to measure a ternary state of a qubit.

It is to be noted that in practice, a given distribution of scatter points will have outliers which result from some finite measurement error. For example, assuming a qubit is in a |1or a |2state, while a majority of the single-shot readout signals will fall within the expected distribution of scatter points, there can be some outliers of single-shot readout signals that are classified to be in the |0state. Such outliers can be discarded from consideration using an error mitigation protocol as discussed above. Indeed, an error mitigation protocol utilizes prepared quantum states for the |0, |1and |2states within a three-state assignment matrix. After performing a ternary state readout process (as discussed above) and obtain distributions of actual measurement outcomes, the actual measured state can be compared against the prepared state, and an inverse of the assignment matrix is computed to collect the actual (correct) distribution of the measurement outcomes, with the knowledge of what outliers are expected to be obtained statistically.

It is be appreciated thatFIG.4illustrates an exemplary embodiment in which a quantum computer can be calibrated to perform quantum operations in the computational basis comprising the basis states |0and |1, while reusing such calibration to perform ternary measurements using binary-outcome mid-circuit measurements as discussed above. In particular, the control circuitry of a quantum computer can be calibrated so that (i) the amplitude and/or phase of the single microwave tone of the readout control signal RF_RO is tuned to obtain good separation of scatter points between the ground state |0and the first excited state |1, and (ii) the hardware discriminator is optimally calibrated to discriminate between the ground state |0and the first excited state |1.

This is in contrast to a conventional embodiment for ternary state readout in which the control circuitry of the quantum computer would need to be calibrated by tuning the measurement stimulus (e.g., frequency, amplitude and/or phase of the readout control signal RF_RO) to obtain good separation of scatter points between the ground state |0, the first excited state |1, and the second excited state |2. In addition, a software-based discriminator process would be utilized to process the distribution of scatter points of measurement outcomes obtained for a given ternary state readout operation to precisely determine the state of the ternary system. This would require the quantum computing system to return the measured single-shot IQ data points to a host processor to calibrate a ternary state discriminator by using a computationally expensive mathematical software (e.g., sklearn in Python), and then for each set of measurement outcomes for a given ternary measurement, return the associated IQ data points to the host system for processing by the software-based discriminator process to determine the measured state (e.g., |0, |1)or |2). This process consumes a relatively large amount of communication bandwidth for the downstream traffic of a large complex array representing IQ data points, which limits scaling. Overall, the need to calibrate an additional and separate measurement operation for a ternary readout, in addition to a binary readout, would add cost to the quantum computing system.

Advantageously, the exemplary binary-outcome mid-circuit measurement techniques as discussed herein allow the quantum computing system to be calibrated for binary outcome measurements, while being reusable for ternary outcome measurements. The exemplary ternary state readout techniques as discussed herein rely on standard binary qubit readout operations, which are computationally inexpensive and may be implemented using an embedded system with a hardware-based discriminator, which does not require the raw IQ data to be returned to a host processor for processing by a software-based discriminator of the quantum operating system for ternary state discrimination. Instead, the exemplary ternary state readout techniques as discussed herein enable, e.g., a measurement of the probability of the second excited state |2to evaluate the leakage from the computational basis after a given operation by utilizing a ternary state readout instruction to measure the second excited state using a standard quantum computer that is calibrated for the computational basis without having to modify (or integrate another measurement scheme for the readout system) or upgrade the microarchitecture of the quantum computing system.

FIG.5schematically illustrates a quantum computing system that is configured to measure ternary quantum states using binary-outcome mid-circuit measurements, according to an exemplary embodiment of the disclosure. In particular,FIG.5schematically illustrates a quantum computing system500which comprises a quantum computing platform510(more generally, computing system), a control system520, and a quantum processor530. In some embodiments, the quantum computing platform510implements a software platform that is configured to program a quantum computer to execute quantum computing algorithms512which are implemented using, e.g., quantum circuits which define computational routings consisting of coherent quantum operations on quantum data, such as qubits. The quantum computing platform510comprises a quantum compiler514which adapts quantum circuits to conform to a specific device topology of a given quantum computer system and/or optimizing for execution on a noisy quantum computing system. As noted above, the quantum compiler514is configured to decode a ternary measurement instruction into a sequence of binary-outcome mid-circuit measurements to enable ternary state readout in a quantum processing system having a standard micro-architecture that is configured for the computational basis states of |0and |1, and which supports a dispersive readout architecture.

In addition, in some embodiments, the control system520comprises a multi-channel arbitrary waveform generator522, and a quantum bit readout control system524. The quantum processor530comprises at least one quantum chip having a superconducting qubit array532and a network534of qubit drive lines, coupler flux-bias control lines, and qubit state readout lines, and other circuit QED components that may be needed for a given application or quantum system configuration. In some embodiments, the superconducting qubit array532comprises a quantum system comprising an array of superconducting data qubits, superconducting auxiliary qubits, and superconducting flux-tunable couplers, arranged in a heavy hexagonal lattice topology or square lattice topology.

In some embodiments, the control system520and the quantum processor530are disposed in a dilution refrigeration system540which can generate cryogenic temperatures that are sufficient to operate components of the control system520for quantum computing applications. For example, the quantum processor530may need to be cooled down to near-absolute zero, e.g., 10-15 millikelvin (mK), to allow the superconducting qubits to exhibit quantum behaviors. In some embodiments, the dilution refrigeration system540comprises a multi-stage dilution refrigerator where the components of the control system520can be maintained at different cryogenic temperatures, as needed. For example, while the quantum processor530may need to be cooled down to, e.g., 20 mK or below (e.g., 10-15 mK) the circuit components of the control system520may be operated at cryogenic temperatures greater than 10-15 mK (e.g., cryogenic temperatures in a range of 3K-4K), depending on the configuration of the quantum computing system. In other embodiments, some or all of components of the multi-channel arbitrary waveform generator522and/or quantum bit readout control system524can be implemented in a room temperature environment, while the signal chains (for control signal input, and read signal output) extend from a room temperature environment through different temperature stages (e.g., five temperature stages: 20 millikelvin (mK), 100 mK, 1K, 3-4K, 40K) of the dilution refrigeration system540.

The network534of qubit drive lines, coupler flux bias control lines, and qubit state readout lines, etc., is coupled to the control system520through a suitable hardware input/output (I/O) interface, which couples I/O signals between the control system520and the quantum processor530. For example, the hardware I/O interface may comprise various types of hardware and components, such as RF cables, wiring, RF elements, optical fibers, heat exchanges, filters, amplifiers, isolators, etc.

The quantum computing platform510comprises a software and hardware platform which comprises various software layers that are configured to perform various functions, including, but not limited to, generating and implementing various quantum applications using suitable quantum programming languages, configuring and implementing various quantum gate operations, compiling quantum programs into a quantum assembly language, implementing and utilizing a suitable quantum instruction set architecture (ISA), performing calibration operations to calibrate the quantum circuit elements and gate operations, etc. In addition, the quantum computing platform510comprises a hardware architecture of processors, memory, etc., which is configured to control the execution of quantum applications, and interface with the control system520to (i) generate digital control signals that are converted to analog microwave control signals by the control system520, to control operations of the quantum processor530when executing a given quantum application, and (ii) to obtain and process digital signals received from the control system520, which represent the processing results generated by the quantum processor530when executing various gate operations for a given quantum application.

The quantum computing platform510comprises a software and hardware platform which comprises various software layers that are configured to perform various functions, including, but not limited to, generating and implementing various quantum applications using suitable quantum programming languages, configuring and implementing various quantum gate operations, compiling quantum programs into a quantum assembly language, implementing and utilizing a suitable quantum instruction set architecture (ISA), performing calibration operations to calibrate the quantum circuit elements and gate operations, etc. In addition, the quantum computing platform510comprises a hardware architecture of processors, memory, etc., which is configured to control the execution of quantum applications, and interface with the control system520to (i) generate digital control signals that are converted to analog microwave control signals by the control system520, to control operations of the quantum processor530when executing a given quantum application, and (ii) to obtain and process digital signals received from the control system520, which represent the processing results generated by the quantum processor530when executing various gate operations for a given quantum application. In some exemplary embodiments, the quantum computing platform510of the quantum computing system500may be implemented using any suitable computing system architecture (e.g., as shown inFIG.6) which is configured to implement methods to support quantum computing operations by executing computer readable program instructions that are embodied on a computer program product which includes a computer readable storage medium (or media) having such computer readable program instructions thereon for causing a processor to perform control methods as discussed herein.

In some embodiments, the quantum computing platform510comprises a quantum computing service and programming model that implements the Open-Source Quantum Development Qiskit platform. As is known in the art, Qiskit is an open-source software development kit (SDK) for programming and working with quantum computers at the level of pulses, circuits, and application modules. In this instance, the quantum circuit compiler514is configured to translate Qiskit code into an optimized circuit using a native gate set of a given backend for a given quantum process, wherein the backend comprises either a simulator or real quantum computer. The Qiskit platform library can implement the ternary readout instruction for use with a standard commercial quantum computer that supports only binary state readout, and which supports mid-circuit measurement using dispersive readout techniques. This allows a user to implement and develop quantum algorithms which incorporate qutrits, such as quantum random access coding in a qutrit space, with standard commercial quantum computers that only support qubit readout.

The exemplary ternary readout techniques as discussed herein can be combined with the existing experiment library in Qiskit, currently referred to as Qiskit Experiments. For example, combining this technique promotes the standard randomized benchmarking (RB) experiment to a leakage RB to support an experimental method for measuring the average error rates of leakage from the computational basis to the second excited state of quantum computing hardware platforms. In some embodiments, the ternary (qutrit) measurement instruction can be implemented to allow an internal experimentalist to natively write experiments to characterize leakage error and allow a monitoring agent running on the quantum operating system to continuously monitor the leakage for self-diagnosis to realize robust quantum computing system. It is feasible to support parallel execution of such a monitoring task on huge number of qubits thanks to the capability of hardware-integration of the binary-outcome mid-circuit measurement.

Computing environment600ofFIG.6contains an example of an environment for the execution of at least some of the computer code involved in performing the inventive methods, such as program code for performing quantum computing algorithms and for implementing quantum circuit compiler process which is configured to, e.g., decode a ternary measurement instruction into a sequence of binary-outcome mid-circuit measurements to enable ternary state readout in a quantum processing system having a standard micro-architecture that is configured for the computational basis states of |0and |1as discussed above. In addition to block626, computing environment600includes, for example, computer601, wide area network (WAN)602, end user device (EUD)603, remote server604, public cloud605, and private cloud606. In this embodiment, computer601includes processor set610(including processing circuitry620and cache621), communication fabric611, volatile memory612, persistent storage613(including operating system622and block626, as identified above), peripheral device set614(including user interface (UI), device set623, storage624, and Internet of Things (IoT) sensor set625), and network module615. Remote server604includes remote database630. Public cloud605includes gateway640, cloud orchestration module641, host physical machine set642, virtual machine set643, and container set644.

Processor set610includes one, or more, computer processors of any type now known or to be developed in the future. Processing circuitry620may be distributed over multiple packages, for example, multiple, coordinated integrated circuit chips. Processing circuitry620may implement multiple processor threads and/or multiple processor cores. Cache621is memory that is located in the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores running on processor set610. Cache memories are typically organized into multiple levels depending upon relative proximity to the processing circuitry. Alternatively, some, or all, of the cache for the processor set may be located “off chip.” In some computing environments, processor set610may be designed for working with qubits and performing quantum computing.

Volatile memory612is any type of volatile memory now known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, the volatile memory is characterized by random access, but this is not required unless affirmatively indicated. In computer601, the volatile memory612is located in a single package and is internal to computer601, but, alternatively or additionally, the volatile memory may be distributed over multiple packages and/or located externally with respect to computer601.

End user device (EUD)603is any computer system that is used and controlled by an end user (for example, a customer of an enterprise that operates computer601), and may take any of the forms discussed above in connection with computer601. EUD603typically receives helpful and useful data from the operations of computer601. For example, in a hypothetical case where computer601is designed to provide a recommendation to an end user, this recommendation would typically be communicated from network module615of computer601through WAN602to EUD603. In this way, EUD603can display, or otherwise present, the recommendation to an end user. In some embodiments, EUD603may be a client device, such as thin client, heavy client, mainframe computer, desktop computer and so on.

Remote server604is any computer system that serves at least some data and/or functionality to computer601. Remote server604may be controlled and used by the same entity that operates computer601. Remote server604represents the machine(s) that collect and store helpful and useful data for use by other computers, such as computer601. For example, in a hypothetical case where computer601is designed and programmed to provide a recommendation based on historical data, then this historical data may be provided to computer601from remote database630of remote server604.

Private cloud606is similar to public cloud605, except that the computing resources are only available for use by a single enterprise. While private cloud606is depicted as being in communication with WAN602, in other embodiments a private cloud may be disconnected from the internet entirely and only accessible through a local/private network. A hybrid cloud is a composition of multiple clouds of different types (for example, private, community or public cloud types), often respectively implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technology that enables orchestration, management, and/or data/application portability between the multiple constituent clouds. In this embodiment, public cloud605and private cloud606are both part of a larger hybrid cloud.