High voltage output buffer using low voltage transistors

An apparatus comprising a first circuit configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pullup signal and a second circuit configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal, wherein said first and second circuits are implemented with transistors that normally can only withstand said second supply voltage.

FIELD OF THE INVENTION

The present invention relates to a method and/or architecture for implementing a high voltage output buffer generally and, more particularly, to a method and/or architecture for implementing a high voltage output buffer with low voltage transistors.

BACKGROUND OF THE INVENTION

Traditional output buffer circuits have used high voltage transistors for implementing I/Os on the same integrated circuit (IC) as low voltage transistors. Such an approach increases the technology complexity as well as the cost of implementing such a circuit.

For dual-voltage technologies, the I/Os run off a high voltage supply and the internal circuitry off a low voltage supply. Due to gate-oxide stress, low voltage transistors cannot be used in the I/Os with conventional circuits.

As transistor dimensions decrease, supply voltages have to decrease in order to prevent gate-oxide breakdown. However, in order to reduce die cost and improve performance, it is often desirable to migrate a high voltage device into a technology which is smaller, but cannot cope with the gate-oxide stress of the high voltage. A way to avoid this problem is to develop a dual voltage technology. The internals of the chip use the low voltage transistors running off a regulated power supply. The I/Os use high voltage transistors running off the high voltage main supply.

It would be desirable to implement a method and/or architecture that uses low-voltage transistors for an output buffer arranged such that the gate oxide (Gox) is not stressed above the low-voltage threshold.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pullup signal. The second circuit may be configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal. The first and second circuits may be implemented with transistors that normally can only withstand the second supply voltage.

The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a high voltage output buffer comprising low voltage transistors that may (i) have a maximum voltage stress across gate oxide that is within the tolerance of low voltage transistors, (ii) provide an integral voltage translation from an internal low voltage stage to a high voltage output stage, (iii) be driven from a high voltage supply; and/or (iv) contain integral voltage translation from internal low voltage to external high voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 , a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. In one example, the circuit 100 may be implemented as a buffer circuit. More specifically, the circuit 100 may be implemented as an output buffer circuit. The circuit 100 may be implemented as a high voltage (e.g., 3.3V) output buffer that only requires low voltage (e.g., 2.5V) transistors. The circuit 100 may have an input 102 that may receive a first supply voltage (e.g., HIGHVCC), an input 104 that may receive a control signal (e.g., PU), an input 106 that may receive a second supply voltage (e.g., LOWVCC), an input 108 that may receive a control signal (e.g., PD) and an output 110 that may present a signal (e.g., OUT) to a pad block (or circuit) 112 . The supply voltage HIGHVCC may be at a higher voltage level than the supply voltage LOWVCC. In one example, the signal PU may be implemented as a pullup signal and the signal PD may be implemented as a pulldown signal. The pad circuit 112 may provide an interface to the lead frame of an integrated circuit.

Referring to FIG. 2 , a more detailed diagram of the circuit 100 is shown. The circuit 100 generally comprises a circuit 120 and a circuit 122 . The circuit 120 may be a high supply voltage stage. The circuit 122 may be a low supply voltage stage. The circuit 120 generally receives the signal HIGHVCC and the signal PU. The circuit 122 generally receives the signal LOWVCC and the signal PD. An output 124 of the circuit 120 is combined with an output 126 of the circuit 122 to present the signal OUT to the output 110 .

Referring to FIG. 3 , a schematic diagram of the circuit 100 is shown. The circuit 120 generally comprises a transistor P 1 , a transistor P 2 , a transistor P 3 , a transistor P 4 , a transistor P 5 , a transistor P 6 , a transistor N 1 and a transistor N 2 . The transistors P 1 -P 6 are generally implemented as p-channel (or PMOS) transistors. The transistors N 1 and N 2 are generally implemented as n-channel (or NMOS) transistors. The signal PU is generally presented (i) to an inverter 130 and (ii) directly to the gate of the transistor N 2 . The inverter 130 may present a signal (e.g., PUb) to the gate of the transistor N 1 . A source of the transistor P 1 generally receives the signal HIGHVCC. A drain of the transistor P 4 is generally presented at the output 124 .

The gate of the transistor P 3 is generally connected between the drain of the transistor P 2 and the source of the transistor P 5 . The connection is generally referred to as a node (e.g., PGATEB). The gate of the transistor P 2 is generally connected to the gate of the transistor P 4 as well as to the drain of the transistor P 3 and the source of the transistor P 6 . The connection is generally referred to as a node (e.g., PGATE). The source of the transistor P 2 and the source of the transistor P 3 are generally connected to the gate of the transistor P 1 as well as to the source of the transistor P 4 . This connection is referred to as a node (e.g., PDIODE).

The circuit 122 generally comprises a transistor N 3 and a transistor N 4 . The transistors N 3 and N 4 are generally implemented as n-channel (or NMOS) transistors. A gate of the transistor N 3 generally receives the supply voltage LOWVCC. A gate of the transistor N 4 generally receives the signal PD. A node between the transistor N 3 and N 4 will be referred to as an internal pulldown voltage (e.g., PDINT). The source of the transistor N 3 generally presents the output 126 .

The following description assumes a 3.3V supply using 2.5V transistors. However, other supply voltages may be implemented accordingly to meet the design criteria of a particular implementation. The p-channel threshold voltage is Vtp 0.8V, the n-channel threshold voltage is Vtn 0.8V and the gate oxide breakdown is Gox>2.5V.

The circuit 122 generally comprises a pulldown structure implemented using cascaded NMOS devices N 3 and N 4 . The device N 3 has a gate driven by the internal low voltage supply LOWVCC (e.g., 2.5V). The device N 3 is permanently on when the circuit 100 is powered up. A maximum gate-substrate voltage stress of 2.5V occurs when the pad 122 is driven to 0V, since the device N 3 is operating at 2.5V. When the pad 122 is driven to 3.3V, the gate-drain voltage stress is 0.8V

When the pulldown signal PD is low, the pull-down device N 4 is off. The Gox stress is 0V between gate and substrate. The node PDINT can generally only rise to 2.5V maximum due to the device N 3 . Therefore, the maximum stress across the drain of the transistor N 4 is 2.5V. When the pulldown signal PD is high, the device N 4 is on and the node PDINT is pulled low. The gate-drain and gate-substrate stress on the device N 4 are both 2.5V. Since the gate voltage of 2.5V is above the threshold voltage Vtn of the device N 4 , no voltage translation is required.

In the circuit 120 , the device P 1 provides a diode drop from the 3.3V supply (e.g., the supply HIGHVCC). The device P 1 may be implemented as a number of devices greater than 1. Implementing more devices may lessen the impact of the level translator. The device P 2 and the devices P 5 and P 6 are generally implemented in a latch configuration. Such a configuration reduces the voltage on the node PDIODE to Vcc Vtp, or 2.5V in this example. The device P 4 is used to implement the pull-up device. The gate of the device P 4 (e.g., PGATE) is controlled by a cross-coupled latch formed by the devices P 2 and P 3 which also incorporates a voltage translation stage.

When the pull-up device P 4 is off, the signal PU is low, ensuring the device N 2 is off. If the signal PUb is high, the device N 1 is turned on. Due to the PMOS device P 5 , the node PGATE is pulled to Vss Vtp, or 0.8V in this example. The voltage may turn on the device P 3 and the node PGATE is pulled to 2.5V. The device P 2 and the device P 4 now have 0V gate to source voltages and are therefore off. As the node PGATEb approaches 0.8V, the gate-source and gate-substrate voltage stress on the device P 3 is restricted to 1.7V.

If the pad 112 is pulled to ground when the pull-up device P 4 is off, the node PGATE is at 2.5V and the gate-drain stress on the device P 4 is 2.5V. When the PAD 112 is pulled high, the device P 4 is high and the signal PU low. The device N 1 is then off and the device N 2 on. Due to the PMOS device P 6 , the node PGATE is pulled to Vss Vtp (0.8V in this example). This restricts the gate-source and gate-substrate stress on the device P 4 to 1.7V. When the node PGATE is low, the device P 2 is on, the device P 3 is off and the node PGATE is at 2.5V. The gate-source and gate-substrate stress on the device P 2 is then restricted to 1.7V.

The circuit 100 provides integral voltage translation from the internal low voltage stage 122 to the high voltage output stage 120 . Specifically, the circuit 100 may contain integral voltage translation from internal low voltage to external high voltage. The circuit 100 may be implemented as a high voltage output buffer that uses low voltage transistors. The circuit 100 may use low-voltage transistors arranged in such a way that the voltage stress across the gate-oxide is within low-voltage transistor tolerances, thus preventing gate oxide Gox breakdown. Therefore, the circuit 100 may be driven from a high voltage supply. Additionally, the circuit 100 may allow maximum voltage stress across gate oxide may be limited to within low voltage transistor tolerance.

The supply voltage HIGHVCC and LOWVCC may be implemented as a variety of voltages. For example, the supply voltage HIGHVCC may be 3.3 V and the supply voltage LOWVCC may be 2.5 V. In another example, the voltage could be scaled down so that the supply voltage HIGHVCC is 2.5 V and the supply voltage LOWVCC is 1.8 V. While not as useful, the voltage could be scaled up so that the supply voltage HIGHVCC is 5.0 V and the supply voltage LOWVCC is 3.3 V. Additionally, 3.3 V high and 1.8 V low could add more diodes.

The various signals of the present invention are generally on (e.g., a digital HIGH, or 1) or off (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation.