Temperature compensated FET constant current source

A constant current source comprises a FET, a bandgap reference voltage source coupled to its gate terminal and a resistor coupled to its source terminal. The width and length of the FET are configured so that the temperature coefficient (TEMPCO) of Vgs of the transistor offsets the TEMPCO of the resistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to FET constant current sources and, more particularly, to temperature compensation in such circuits.

2. Discussion of the Related Art

Integrated circuits (ICs) often require a constant current source; that is, a current reference that is both accurate and stable with respect to temperature and variations in manufacturing process. In the prior art, the ICs that implement such a constant current source are typically both complex and inefficient; that is, wasteful in terms of chip area utilized and power consumed. Constant current sources that are illustrative of prior art approaches include D. A. Badillo,IEEE Symp. on Circuits and Systems-III, Vol. 3, pp. 197–200 (May 2002) and R. Dehghani et al.,IEEE Symp. on Circuits and Systems-II, Vol. 50, No. 12, pp. 928–932 (December 2003), both of which are incorporated herein by reference. The Badillo paper describes a CMOS current reference circuit that places a level shift stage between a feedback amplifier and a bandgap reference (BGR) voltage source in order to increase the temperature operating range. The Dehghani et al. paper also describes a CMOS current reference circuit based on a BGR voltage source and a CMOS circuit similar to a beta amplifier but modified by the inclusion of an NMOS transistor that functions as a resistor. The NMOS transistor is operated in the triode region to achieve a current that has a negative temperature coefficient and only oxide thickness dependence. The BGR voltage has a positive temperature coefficient that cancels the negative temperature coefficient of the beta amplifier.

Thus, a need remains in the art for an accurate, stable constant current source, which can be implemented in MOS technology without the complexity and inefficiency typified by prior art designs.

BRIEF SUMMARY OF THE INVENTION

In accordance with one aspect of my invention, a constant current source comprises a field effect transistor (FET), a constant voltage source coupled to its gate terminal, and a resistor coupled to its source terminal. The width and length of the FET are configured so that the temperature coefficient (TEMPCO) of Vgsof the transistor offsets the TEMPCO of the resistor.

DETAILED DESCRIPTION OF THE INVENTION

With reference now toFIG. 1, an IC constant current source10, in accordance with one embodiment of my invention, comprises an NMOS FET M0having its drain terminal coupled to a source of reference potential (e.g., ground10.1) through an on-chip resistor R0. Resistor R0is depicted as a single element, but in practice it may be a resistive network including a combination of resistors connected in series or parallel with one another. Likewise, M0is depicted as an NMOS FET, but in practice could alternatively be a PMOS FET. The drain terminal of M0is coupled to a source of supply voltage (e.g., Vcc) and delivers an output current I01. The gate terminal of M0is coupled to a source of input voltage (e.g., Vin), which is essentially constant with changes in temperature over the operating range of the current source; that is the TEMPCO of Vinis essentially equal to zero. Preferably, Vinis a bandgap reference (BGR) source, which is well known in the art. Since a BGR source is frequently found on-chip in many ICs, it is a convenient choice for Vin.

In order to render the output current I01relatively constant with changes in temperature, the width and length of the M0are configured to produce a negative TEMPCO that offsets the positive TEMPCO of R0, or conversely the size of M0is configured to produce a positive TEMPCO that offsets the negative TEMPCO of R0. The theory upon which this form of temperature compensation is predicated is as follows. The gate-to-source voltage Vgsof M0is the sum of the FET's on-voltage (Von) and its threshold voltage (Vt). Thus,
Vgs=Von+Vt(1)
where
Von=[(2LiD)/(WμnCox)]0.5(2)
where L and W are the length and width, respectively, of M0, iDis the drain current, Coxis the capacitance associated with the gate oxide of M0, and μn, the mobility of the n-type semiconductor of M0, is given by
μn=KμT−1.5(3)
where Kμis a well known constant determined empirically and T is temperature in degrees Kelvin.

On the other hand, the threshold voltage (Vt) is related to temperature as follows:
Vt(T)=Vt(T0)−α(T−T0).  (4)
where T0is the initial temperature at which Vtis evaluated and α is the temperature coefficient of Vt.

From these equations, it is apparent that as temperature increases, for example, Vtand μndecrease. Since μnis in the denominator of Von, as μndecreases, Vonincreases. Therefore, Vonhas a positive TEMPCO. But Vthas a negative TEMPCO, so that Vgs, and hence its TEMPCO (both its sign and magnitude) depends on the relative magnitudes of the Vonand Vtterms in equation (1). In addition, however, and in accordance with one aspect of my invention, the size of M0is designed so that Vgshas a negative TEMPCO of sufficient magnitude to offset the positive TEMPCO of R0. The offset is preferably such that these two TEMPCOs are equal in magnitude and opposite in sign. Of course, those skilled in the art will appreciate that precise equality is not essential inasmuch as considerable benefit, in terms of output current stability, can be achieved even when the two TEMPCOs are nearly equal to one another.

More specifically, the width (W) and length (L) of M0are tuned (i.e., designed) so that the desired Von, and hence a desired TEMPCO of Vgsthat offsets the TEMPCO of R0, is attained over the operating temperature range of the constant current source.FIG. 2illustrates how the normalized output current I01varies with temperature from 0° C. to 125° C. for various ratios W/L. The output current is most stable in two cases: W/L=10, where 0.999<I01<1.020 from 0° C. to about 60° C. and 0.995>I01>1.020 from about 60° C. to about 125° C. Comparable stability is demonstrated for the case W/L=15.

For the case W/L=15,FIG. 3shows how Vgsand R0vary with temperature and how the output current I01remains constant at about 50 μA for a constant input voltage Vin=1.2 V.

It is to be understood that the above-described arrangements are merely illustrative of the many possible specific embodiments that can be devised to represent application of the principles of the invention. Numerous and varied other arrangements can be devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention. In particular, in an alternative embodiment of my invention, as shown inFIG. 1, a conventional current mirror20is coupled between the drain terminal of M0and the supply voltage source, thereby generating the constant current I02=mI01, where the multiplier m is any real number. In the illustration discussed above in conjunction with FIGS.3–5, I01=50 μA and I02=25 μA. Therefore, m=0.5. In general, mirrored current such as I02may be supplied to as many other circuits on the chip that require a stable and accurate current.

In practice, standard IC technology (e.g., well known silicon semiconductor processing) is employed to fabricate my constant current source10on the same chip as other circuit components, including for example a BGR input voltage source Vinand the optional current mirror20. The particular W/L ratio that gives a temperature independent constant current output I01of M0is implemented primarily by properly designing the IC masks that are used to pattern the width and length of M0. Once M0is tuned in this fashion, the temperature characteristics of I01remain relatively stable notwithstanding manufacturing process variations. Then, the magnitude of I01may be adjusted, if necessary, by trimming R0(typically by means of well known automatic test equipment).