Waveguide launcher in package based on high dielectric constant carrier

A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to circuit waveguide interfaces for packaged integrated circuit devices.

Description of the Related Art

Semiconductor device fabrication techniques for making integrated circuit devices typically form multiple copies of an integrated circuit in semiconductor wafers that are then singulated into individual dies, each including one or more integrated circuits or other comparable devices. The singulated dies are then mounted in a package substrate that provides external terminations or conductors in the form of leads that electrically connect each die to external assemblies such as circuit boards. After mounting a die onto a package substrate, a molding compound is typically formed on the package substrate to cover and protect the integrated circuit die. In applications that require the ability to make additional high frequency connections, such as millimeter wave systems, the external terminations may also include also waveguides to facilitate high frequency communication. In order to achieve such high frequency communication, an appropriate interface between the waveguides and packaged integrated circuit die is needed. Such interfaces can require precise manufacturing that may be not possible with conventional semiconductor manufacturing processes. Thus, the addition of such high frequency capability can add significant cost and complexity to the design and fabrication of such devices. Thus, there remains a need to provide improved techniques and structures for providing circuit waveguide interfaces to packaged integrated circuit devices.

It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.

DETAILED DESCRIPTION

A method and apparatus are described for fabricating circuit waveguide interfaces during a wafer-scale die packaging (WSDP) processes which integrates a differential pair to waveguide launcher in package (LIP) structure within the glass or ceramic carrier formed with a material having a high dielectric constant (e.g., k=5.8-6.8) and including an air cavity structure formed in the waveguide short back that is designed and constructed to provide waveguide matching and to reduce insertion loss (e.g., to approximately 0.95-1.05 dB). Specifically, during the packaging process, a high-k glass carrier substrate is processed to form one or more ceramic regions in an intended waveguide region and to form an air cavity in the one or more ceramic regions. Either before or after forming the air cavity, conductive layers are formed defining a differential pair radiating element located on a first carrier substrate surface adjacent to the air cavity, a reflector interface layer located on a second carrier substrate surface, and a conductive via wall or ring structure located in the one or more ceramic regions that surrounds the intended waveguide region and connects the reflecting element to the first carrier substrate surface. After covering the air cavity with a substrate cap sheet, a singulated die is attached on the high-k glass carrier substrate and a molding compound is applied to over the die, substrate cap sheet, and differential pair radiating element. As needed, a conductive via wall or ring structure is formed in the molding compound to surround the intended waveguide region and to electrically connect to the conductive via wall or ring formed in the one or more ceramic regions. In this way, a circuit waveguide interface is formed from the conductive via wall or ring structures formed in the molding compound and one or more ceramic regions around the intended waveguide region. In addition or in the alternative, an electro-magnetic interference (EMI) O-ring gasket formed with metallic or metal-coated particles in EMI silicones can be bonded between the molding compound and circuit waveguide interface. By forming the differential pair radiating element on the first carrier substrate surface (instead of in the circuit waveguide interface), the LIP transition loss may be significantly reduced to 1.0 dB while also relaxing tolerance control requirements for alignment of critical elements. The embodiments described herein use WSDP processes to both form the package and form a circuit waveguide interface integrated with the package, and thus can facilitate the formation of the circuit waveguide interface with both relatively high precision and relatively low cost and complexity.

In WSDP processes, singulated die are arranged on a wafer-like carrier panel for processing and packaging. The singulated die on the carrier panel are then covered with molding compound that will harden to provide the bodies of the packages of the die on the carrier panel. Photolithography and other wafer-type processing techniques are used to form one or more metallization layers (e.g., copper) that provide connections from the die to outside the package. In WSDP processing, these connections can be formed on the top and bottom sides of the molded die, and can include interconnects between metallization layers. For example, metallization layers on one side can be formed for die-to-die connections, and metallization layers on the other side can be formed to provide landing pad arrays. The molded die on the panel is then singulated into discrete packages. As will be described in greater detail below, the embodiments herein provide a technique for forming a circuit waveguide interface during such a wafer-scale die packaging process.

Turning now toFIGS.1A and1B, a top view10A and cross-sectional side view1B (through lineFIG.1B-FIG.1BofFIG.1A) are illustrated of a glass wafer11with one or more first patterned ceramic regions12A-D at a first stage of a package fabrication process in accordance with selected embodiments of the present disclosure. The glass wafer11may be initially formed as a “photo-structurable glass” with a high-k dielectric material having a high dielectric constant (e.g., k>3.9). In selected embodiments, the glass wafer11may be formed with an APEX® Glass wafer containing special sensitizers that allow unique anisotropic3D features to be formed through a simple exposure step. Using standard IC processing tools, patterned ceramic regions12may be formed in the glass wafer11at predetermined locations. For example, the glass wafer11may be exposed to a first mask pattern and then baked to convert the exposed regions of the glass11into patterned ceramic regions12which extend through the glass wafer11. By defining the locations of the mask openings, a first set of patterned ceramic regions12A may be positioned outside of the intended die region13and a second set of patterned ceramic regions12B-C may be positioned inside the intended die region13. In addition, a third set of patterned ceramic regions12D may be positioned around the periphery of an intended wave guide region14.

Turning now toFIGS.2A and2B, a top view20A and cross-sectional side view20B (through lineFIG.2B-FIG.2BofFIG.2A) are illustrated of a glass wafer11with one or more patterned openings21at a stage of a package fabrication process afterFIG.1. While any suitable etch process may be used, the patterned openings21may be formed by applying a wet etch to remove the patterned ceramic regions12, thereby leaving the patterned openings21which extend through the glass wafer11. As formed, the patterned openings21may include a first set of patterned openings21A positioned outside of the intended die region13and a second set of patterned openings21B-C positioned inside the intended die region13. In addition, a third set of patterned openings21D may be positioned around the periphery of an intended wave guide region14.

Turning now toFIGS.3A and3B, a top view30A and cross-sectional side view30B (through lineFIG.3B-FIG.3BofFIG.3A) are illustrated of a glass wafer11with one or more second patterned ceramic regions31for the intended waveguide region14at a stage of a package fabrication process afterFIG.2. At this point in the fabrication process when the glass wafer11already has the patterned openings21D formed in the intended waveguide region14, the patterned ceramic region(s)31may be formed by exposing the glass wafer11to a second mask pattern and then applying a second bake process to convert the exposed region(s) of the glass11into one or more second patterned ceramic regions31which extend through the glass wafer11. By defining the locations of the openings in the second mask, the second patterned ceramic region(s)31may be positioned to encompass and include the intended wave guide region14and to extend into the intended die region13.

Turning now toFIGS.4A and4B, a top view40A and cross-sectional side view40B (through lineFIG.4B-FIG.4BofFIG.4A) are illustrated of a glass wafer11with patterned conductive vias41formed at a stage of a package fabrication process afterFIG.3. At this point in the fabrication process when patterned openings21are already formed in the glass wafer11, the patterned conductive vias41may be formed with one or more conductive layers, such as by depositing (e.g., vapor deposition, electroplating, sputtering) one or more conductive materials (e.g., copper) to fill the patterned openings21and then applying a polish or etch process to remove the conductive layer(s) from the first and second carrier substrate surfaces. As formed, the patterned conductive vias41may include a first set of patterned conductive vias41A positioned outside of the intended die region13and a second set of patterned conductive vias41B-C positioned inside the intended die region13. In addition, a third set of patterned conductive vias41D may be positioned around the periphery of an intended wave guide region14except for any location which will overlap with a subsequently-formed differential pair to waveguide launcher in package (LIP) structure.

Turning now toFIGS.5A and5B, a top view50A and cross-sectional side view50B (through lineFIG.5B-FIG.5BofFIG.5A) are illustrated of a glass wafer11with patterned redistribution layers (RDLs)51,52, including a radiating element51B-C in the intended waveguide region14, at a stage of a package fabrication process afterFIG.4. At this point in the fabrication process, the patterned top RDLs51and bottom RDLs52may be formed directly on the first and second carrier substrate surfaces using any suitable process for depositing and patterning one or more conductive layers. For example, the patterned top RDLs51may be formed by sputter depositing a seed layer over the glass/ceramic carrier11, forming a patterned photoresist mask with defined RDL openings corresponding to the desired RDL features, electroplating one or more conformal conductive layers in the RDL openings, stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the glass/ceramic carrier11to define the top RDLs51. As formed, the top RDLs may include one or more IC connection lines or routing lines51A which are positioned to overlap with and connect selected patterned conductive vias41A (positioned outside of the intended die region13) with selected patterned conductive vias41B-C (positioned inside the intended die region13). In addition, the top RDLs may include a separately defined loop layer which includes a pair of parallel waveguide lines51B (which are positioned to extend from the intended die region13to the intended waveguide region14) and a radiating element51C (which is positioned in the intended waveguide region14to connect the pair of parallel waveguide feed lines51B in a loop). In addition, the top RDLs may include a separately defined outer waveguide ring layer51D which has an open interior space and which is positioned around the periphery of the intended waveguide region14except for a gap where the waveguide feed lines51B are located. Thus formed, the waveguide feed lines51B and radiating element51form a differential pair to waveguide launcher in package (LIP) structure on the top carrier substrate surface which is positioned to extend from the intended die region13to the interior location surrounded of the intended waveguide region by the waveguide ring layer51D while leaving space for a subsequently-formed air cavity.

In similar fashion, the patterned bottom RDLs52may be formed (including a waveguide short metal plane in the waveguide region) by using any suitable process for depositing and patterning one or more conductive layers on the bottom carrier substrate surface. As formed, the bottom RDL layer(s) may define a waveguide reflector interface layer which is positioned on the bottom carrier substrate surface to overlap with the outer waveguide ring layer51D, including its interior space so as to cover the entire area of the intended waveguide region14. InFIG.5B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.5B-FIG.5B) at the intended die region13, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.5B-FIG.5B) is positioned in alignment with the underlying waveguide lines51B.

Turning now toFIGS.6A and6B, a top view60A and cross-sectional side view60B (through lineFIG.6B-FIG.6BofFIG.6A) are illustrated of a glass wafer11with a partially etched air cavity61in the intended waveguide region at a stage of a package fabrication process afterFIG.5. While any suitable recess etch process may be used, the air cavity61may be formed by applying a solder mask to cover the first and second carrier substrate surfaces except for an exposed area in the patterned ceramic region31where the air cavity61will be formed, and the performing a recess etch of the exposed ceramic region31using a timed anisotropic etch to form the air cavity61. The process parameters and timing of the recess etching should be controlled to etch a specified depth which leaves a thin layer of the patterned ceramic region31below the air cavity61at the bottom ceramic carrier substrate surface, thereby defining a waveguide short back below the differential pair to waveguide LIP structure51B/C. In addition, a patterned mask and etch process may be controlled so that the air cavity61is positioned inside the intended waveguide region14and adjacent to the differential pair to waveguide LIP structure51B/C. As will be appreciated, the recess etching control process parameters may require a specified minimum thickness of the glass/ceramic carrier11in order to guarantee the required thickness parameters for the waveguide back short. InFIG.6B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.6B-FIG.6B) at the intended die region13, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.6B-FIG.6B) is positioned in alignment with the underlying waveguide lines51B.

Turning now toFIGS.7A and7B, a top view70A and cross-sectional side view70B (through lineFIG.7B-FIG.7BofFIG.7A) are illustrated of a glass wafer11with one or more attached die72at a stage of a package fabrication process afterFIG.6. In accordance with the embodiments described herein, the fabricated IC die72may include one or more radio frequency (RF) devices that are to be coupled to a waveguide through a waveguide interface. As will be appreciated, the die72may include an active side on the bottom where fabricated electronic circuits and electrical contacts are formed, and an inactive side on the top side opposite to the active side. Using any suitable bonding or attachment mechanism, a plurality of contact pads71is used to electrically connect the electrical contacts on the bottom active side of the die72over the top RLD layers51A and to the underlying patterned conductive vias41A-C. In WSDP processes, a plurality of singulated die are arranged for placement and attachment over a corresponding plurality of intended die regions13of the glass/ceramic carrier11for processing and packaging. InFIG.7B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.7B-FIG.7B) at the intended die region13, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.7B-FIG.7B) is positioned in alignment with the underlying waveguide feed lines51B.

Turning now toFIGS.8A and8B, a top view80A and cross-sectional side view80B (through lineFIG.8B-FIG.8BofFIG.8A) are illustrated of a glass wafer11with an attached substrate cavity cap sheet81covering the air cavity61at a stage of a package fabrication process afterFIG.7. In accordance with the embodiments described herein, the substrate cavity cap sheet81may be formed with any suitable laminate or non-conductive bonding attachment process for forming a low loss dielectric to reduce the transition loss. For example, Rogers Corporation makes RT/duroid 5880 laminates having low dielectric constant and low dielectric loss properties that are well suited for high frequency/broadband applications. As attached, the substrate cavity cap sheet81will prevent the air cavity61from being filled by molding compound material. However, in embodiments where an air cavity is formed internally within the patterned ceramic region31, then there is no need for the protective substrate cavity cap sheet81. InFIG.8B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.8B-FIG.8B) at the intended die region13, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.8B-FIG.8B) is positioned in alignment with the underlying waveguide feed lines51B.

Turning now toFIGS.9A and9B, a top view90A and cross-sectional side view90B (through lineFIG.9B-FIG.9BofFIG.9A) are illustrated of a glass wafer11with a mold compound91formed over the die72and cavity cap sheet81at a stage of a package fabrication process afterFIG.8. Formed with any suitable molding compound deposit process, the molding compound91has a first (top) side and a second (bottom) side which is attached to the first (top) side of the glass/ceramic carrier11to encapsulate and cover the RDL layers51, die72, and cavity cap sheet81. For example, in WSDP processing, the molding compound is typically applied in a liquid or semi-liquid state to cover the arrangement of IC die72and associated other components on the glass/ceramic carrier11. The applied molding compound may then be subjected to vacuum to extract bubbles that could otherwise create voids in the molding compound, and then cured and (optionally) planarized after curing. As indicated above, the cavity cap sheet81prevents the molding compound material81from filling the air cavity61in the intended waveguide region14. InFIG.9B, it is noted that the patterned conductive vias41A-D are depicted at the intersection with the through line (FIG.9B-FIG.9B) at the intended die region13, and that there is no patterned conductive via41D depicted at the interior side of the intended waveguide region14(adjacent the intended die region13) where the through line (FIG.9B-FIG.9B) is positioned in alignment with the underlying waveguide lines51B.

Turning now toFIGS.10A and10B, a top view100A and cross-sectional side view100B (through lineFIG.10B-FIG.10BofFIG.10A) are illustrated of a glass wafer11with conductive vias101and wall rings102formed in the molding compound91around the intended waveguide region at a stage of a package fabrication process afterFIG.9. As a preliminary step, a patterned array of via openings positioned around the periphery of an intended wave guide region14may be formed in the molding compound92using any suitable processing steps (e.g., pattern and etch, laser drilling, etc.), and then filled with one or more conductive layers and optionally polished or planarized. Thus constructed, the filled vias form a first array of conductive vias101that will define a waveguide interface perimeter in the molding compound91which is positioned around the periphery of the intended wave guide region14except for a gap where the waveguide lines51B are located. Alternatively the first array of conductive vias101can be formed with a single conductive ring which is positioned around the periphery of the intended wave guide region14except for a gap where the waveguide lines51B are located.

After forming the first array of conductive vias101in the mold compound91, a patterned wall ring102may be formed on the molding compound91to make direct electrical connect to the conductive vias101using any suitable process for depositing and patterning one or more conductive layers. For example, the patterned wall ring102may be formed by sputter depositing a seed layer over the molding compound91, forming a patterned photoresist mask with defined mask openings corresponding to the desired ring pattern, electroplating one or more conformal conductive layers in the mask opening, stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the molding compound91to define the patterned wall ring102which has an open interior space and which is positioned around the periphery of the intended wave guide region14.

Having formed the conductive vias101by etching vias and filling the vias with conductive material, the conductive vias101each extend from a first (bottom) side of the molding compound91to a second (top) side of the molding compound91, thereby defining a first waveguide interface perimeter surrounding a first waveguide interface interior. The patterned wall ring102is also formed on the upper surface of the molding compound91in alignment with the conductive vias101to further define the first waveguide interface perimeter surrounding the first waveguide interface interior. InFIG.10B, it is noted that the patterned conductive vias41A-D,101are depicted at the intersection with the through line (FIG.10B-FIG.10B) at the intended die region13, and while there are no patterned conductive vias41D,101in alignment with the underlying waveguide feed lines51B, the positions of the next adjacent patterned conductive vias41D,101at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity.

As disclosed herein, the conductive vias101may be formed by depositing and curing the molding compound, etching vias in the molding compound, and then filling the vias with conductive materials. However, this this is just one example technique. In other embodiments, the conductive vias101can be formed by arranging pre-formed conductive studs on the glass/ceramic carrier and then covering the conductive studs with molding compound. In such embodiments, the conductive studs would typically be placed on the glass/ceramic carrier concurrently with the placement of the die72, either before or after attaching the cavity cap sheet81. Then, the deposited molding compound91would cover both the die72and the conductive studs. Thus, this technique can simplify the formation of the conductive vias101that are used to define the waveguide interface perimeter. In other embodiments, the conductive vias101can be formed with a conductive ring. In this embodiment, the conductive ring would typically be placed on the glass/ceramic carrier concurrently with the placement of die. Then, the deposited molding compound would cover both the die72and the ring.

Turning now toFIGS.11A and11B, a top view110A and cross-sectional side view110B (through lineFIG.11B-FIG.11BofFIG.11A) are illustrated of a glass/ceramic wafer11and mold compound91with an external waveguide113at a stage of a package fabrication process afterFIG.10. While any suitable package terminations or connections may be attached to the packaged mold compound91, selected embodiments of the present disclosure may be implemented by adding electrical leads to the package. For example, a ball grid array (BGA)111or other leads can be attached to the patterned wall ring102around the perimeter of the circuit waveguide interface for use in connecting the circuit waveguide interface to a waveguide or other element. Specifically, a ball grid array (BGA) of balls111is shown attached to the patterned wall ring102on the top surface of the mold compound91. In general, the conductor balls111are coupled to the patterned wall ring102to overlap and follow the perimeter of the circuit waveguide interface that surrounds the first waveguide interface interior, thereby extending the circuit waveguide interface to outside the molding compound91for use in coupling the circuit waveguide interface to an external waveguide113. Though not required, an additional structural layer112, such as an area underfill in the BGA region, is shown as being formed on the mold compound91with a non-conductive material to surround and support the BGA111and to enable stable attachment of an external waveguide113.

In accordance with selected embodiments of the present disclosure, the external waveguide113may be formed with an external waveguide metal layer113that is formed in a ring or cylinder to define and surround an external waveguide opening114. In addition or in the alternative, the external waveguide113may be attached to the package waveguide interface with solder material. InFIG.11B, it is noted that the patterned conductive vias41A-D,101are depicted at the intersection with the through line (FIG.11B-FIG.11B) at the intended die region13, and while there are no patterned conductive vias41D,101in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D,101at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity.

Turning now toFIGS.12A and12B, a top view120A and cross-sectional side view120B (through lineFIG.12B-FIG.12BofFIG.12A) are illustrated of a glass/ceramic wafer11and mold compound91with a conformal electromagnetic isolation (EMI) gasket ring121at a stage of a package fabrication process afterFIG.10. Formed to provide an attachment mechanism for an external waveguide, the conformal EMI gasket ring121may be implemented as a thin layer of conductive material that is bonded onto the molding compound91at the waveguide interface location to make electrical contact with the patterned wall ring102. In such embodiments, the conformal EMI gasket ring121may be attached using compression to maintain contact with mating surfaces of the patterned wall ring102. In addition, the conformal EMI gasket ring121may be formed with metallic or metal-coated particles in EMI silicones that conduct electricity to/from the patterned wall ring102. In other embodiments, the conformal EMI gasket ring121may be implemented as a3D printed EMI O-ring formed with a conductive silicone to provide conductive contact between interfaces under compression. In such embodiments, the EMI O-ring “bounces back” when the force is removed. In general, the conformal EMI gasket ring121is coupled to the patterned wall ring102to overlap and follow the perimeter of the circuit waveguide interface that surrounds the first waveguide interface interior, thereby extending the circuit waveguide interface to outside the molding compound91for use in coupling the circuit waveguide interface to an external waveguide. As disclosed herein, the conformal EMI gasket ring121is formed in a rectangular ring, cylinder or box to define and surround an external waveguide opening122. InFIG.12B, it is noted that the patterned conductive vias41A-D,101are depicted at the intersection with the through line (FIG.12B-FIG.12B) at the intended die region13, and while there are no patterned conductive vias41D,101in alignment with the underlying waveguide lines51B, the positions of the next adjacent patterned conductive vias41D,101at the interior side of the intended waveguide region14(adjacent the intended die region13) are illustrated in semi-transparent form (dotted lines) for clarity.

To further illustrate selected embodiments of the present disclosure, reference is now made toFIG.13which is a simplified flow chart130illustrating an example fabrication method for forming a packaged semiconductor device. In describing the fabrication methodology, the description is intended merely to facilitate understanding of various exemplary embodiments and not by way of limitation. Unless otherwise indicated, the steps may be provided in any desired order. Since the steps illustrated inFIG.13and described below are provided by way of example only, it will be appreciated that the sequence of illustrated steps may be modified, reduced or augmented in keeping with the alternative embodiments of the disclosure so that the method may include additional steps, omit certain steps, substitute or alter certain steps, or perform certain steps in an order different than that illustrated inFIG.13. Thus, it will be appreciated that the methodology of the present invention may be thought of as performing the identified sequence of steps in the order depicted, though the steps may also be performed in parallel, in a different order, or as independent operations that are combined.

Once the methodology starts, a blank glass wafer is exposed with a first mask and baked to form glass/ceramic carrier having a first patterned set of one or more ceramic regions at step131. For example, a blank APEX® glass wafer may be patterned to form ceramic regions by coating, exposing, and developing a layer of photoresist material over the glass wafer to define PR mask openings over areas where the first patterned set of one or more ceramic regions is to be formed. After forming the PR mask with any suitable photoresist pattern process, the masked glass wafer layer may be baked at a suitable temperature to alter the properties of exposed glass wafer to form the first patterned set of one or more ceramic regions which extend through the entire width of the glass/ceramic wafer.

At step132, an etch process is applied to remove the first patterned set of one or more ceramic regions from the glass wafer, thereby forming patterned openings that extend through the entire width of the glass wafer. While any suitable etch process may be used, an example process may remove the first patterned set of one or more ceramic regions by using a plasma-based ash process and/or wet etch chemistry which selectively removes the patterned ceramic regions without etching the remaining glass wafer. The resulting patterned openings may be used to form through glass vias (TGV) which provide thermal and/or conductive structures through the glass/ceramic wafer.

At step133, the glass/ceramic carrier is exposed with a second mask and baked to form a second patterned set of one or more ceramic regions using any suitable steps, such as coating, exposing, and developing a layer of photoresist material over the glass/ceramic carrier to define PR mask openings over areas where the second patterned set of one or more ceramic regions is to be formed. Subsequently, the masked glass/ceramic carrier may be baked at a suitable temperature to form the second patterned set of one or more ceramic regions which extend through the entire width of the glass/ceramic wafer. By defining the locations of the openings in the second mask, the second patterned set of one or more ceramic regions may be positioned to encompass at least the intended wave guide region, and may also extend into the intended die region.

At step134, the patterned openings in the glass/ceramic carrier are filled with conductive material to form patterned conductive vias. In selected embodiments, the patterned openings are plated and filled with a metal, such as copper, to form the patterned conductive vias, and may optionally also be planarized or polished to remove excess metal. So constructed, the filled patterned openings form conductive vias (e.g., vias41inFIGS.4A-B), including a first array of conductors41D that will define a waveguide interface perimeter in the glass/ceramic carrier.

At step135, redistribution lines (RDL) layers are formed on the top and bottom of the glass/ceramic carrier, including a differential radiating element extending partway into the intended waveguide area. In selected embodiments, the RDL layers may be formed by depositing, patterning, and etching top and bottom RDL layers top differential radiating element extending partway into waveguide area. For example, one or more top RDL layers (e.g.,51inFIG.5B) may be formed by sputter depositing a seed layer over the glass/ceramic carrier, forming a patterned photoresist mask with one or more RDL openings which overlap with the patterned conductive vias, electroplating one or more conformal conductive layers in the RDL opening(s), stripping the patterned photoresist mask, and then etching the exposed seed layer from the surface of the glass/ceramic carrier to define the top RDL layers. While a single RDL layer is described and depicted, it will be appreciated that multiple layers or levels of RDL layers may be formed within successive dielectric layers. For example, a multi-layer build up of RDL layers may include a metal layer, dielectric layer and micro vias. The resulting top RDL layers may include one or more IC routing lines or traces which are positioned to overlap with and connect to selected patterned conductive vias. The resulting top RDL layers may also include a separately defined loop layer which includes a pair of parallel waveguide feed lines and a radiating element to connect the pair of parallel waveguide feed lines in a loop. The loop layer is connected as an excitation element that is positioned in the intended waveguide region. In addition, the resulting top RDL layers may include a separately defined outer waveguide ring layer which has an open interior space and which is positioned around the periphery of the intended wave guide region. Thus formed, the waveguide lines and radiating element form a differential pair to waveguide launcher in package (LIP) structure on the top glass/ceramic carrier surface which is positioned to extend from the intended die region to the interior location of the intended waveguide region surrounded by the waveguide ring layer while leaving space for a subsequently-formed air cavity. In similar fashion, the resulting bottom RDL layers may be formed by using any suitable process for depositing, patterning, and etching one or more conductive layers on the bottom surface of the glass/ceramic carrier. As formed, the bottom RDL layer(s) may define a waveguide reflector interface layer which is positioned on the bottom carrier substrate surface to overlap with the intended waveguide region.

At step136, a solder mask layer is applied to cover the top and bottom glass/ceramic carrier surfaces with an air cavity opening over area in the second patterned ceramic region(s) of the glass/ceramic carrier where the air cavity will be formed.

At step137, an air cavity is formed in or on top of the second patterned ceramic regions(s) so as to be positioned adjacent to the differential radiating element and within the intended waveguide region. While any suitable process may be used to form the air cavity, the air cavity may be formed by performing a recess etch of the second patterned ceramic region exposed by the solder mask layer using a timed anisotropic etch to partially etch the second patterned ceramic region. The process parameters and timing of the recess etch process should be controlled to etch a specified depth which leaves a thin layer of the second patterned ceramic region below the air cavity at the bottom glass/ceramic carrier surface, thereby forming a waveguide short back that is defined by the bottom metal plane of the patterned waveguide region. In addition, a patterned mask and etch process may be controlled so that the air cavity is positioned inside the intended waveguide region and adjacent to the differential pair to waveguide LIP structure.

At step138, one or more die are attached with their active sides facing the top of the glass/ceramic carrier. While any suitable die attach process may be used, the die may be attached as a flip-chip integrated circuit die to the pattern of conductive bumps or pillars formed on the top surface of the glass/ceramic carrier. Thus, the die may be attached and electrically connected to the top RDL layers forming the IC lines and the parallel waveguide lines using any suitable die attach technique for making electrical connection therebetween. Thus connected, the die may be connected over the waveguide lines to the radiating element to control the differential pair to waveguide launcher in package (LIP) structure on the top glass/ceramic carrier surface. In addition, the die may be attached and electrically connected to control the waveguide ring layer formed on the on the top surface of the glass/ceramic carrier to define the intended waveguide region.

At step139, a substrate cap sheet may be attached to the glass/ceramic carrier to cover the air cavity. In selected embodiments, the substrate cavity cap sheet may be formed with any suitable laminate or non-conductive bonding attachment process for forming a low loss dielectric to reduce the transition loss. For example, a laminate sheet having low dielectric constant and low dielectric loss properties may be attached to cover the air cavity and prevent it from being filled by molding compound material. However and as indicated with the dashed lines, the substrate cap sheet is an optional step in embodiments where an air cavity is formed internally within the glass/ceramic carrier so that then there is no need for the protective substrate cavity cap sheet.

At step140, a mold compound is deposited to encapsulate the die and other elements formed on the top surface of the glass/ceramic carrier in a protective package. In WSDP processing, the molding compound is typically applied in a liquid or semi-liquid state to cover the arrangement of attached dies and associated other components. A vacuum may then be applied to the molding compound to extract bubbles that could otherwise create voids in the molding compound. The molding compound would then be cured, and optionally planarized after curing.

At step141, via openings are formed in the molding compound to define a perimeter of the circuit waveguide interface. As disclosed herein, the via openings can be formed with any suitable processing, including selective or patterned etching and laser drilling.

At step142, the via openings are filled with conductive layers, such as metal, to form a waveguide wall or ring. The waveguide wall or ring may be formed with one or more electroplating layers, diffusion barrier layers, adhesion layers, conductive layers, and the like. In selected embodiments, the conductive layers are formed by first depositing conductive liners formed of titanium, titanium nitride, tantalum, tantalum nitride, or other alternatives. On the conductive liner layers, conductive layers may be formed with any suitable conductive material, such as copper, a copper alloy, silver, gold, tungsten, aluminum, or the like. In selected embodiments, the conductive layers may be formed by blanket depositing a liner in the via openings, followed by depositing a thin seed layer of copper or copper alloy over the liner, and filling the rest of via openings with metallic material, such as by using electro-plating, electro-less plating, deposition, or the like. A planarization process, such as chemical mechanical planarization (CMP) may then be performed to level the surface of conductive lines and to remove excess conductive materials from the top surface of the mold compound. Subsequently, a masked etch process may be applied to pattern the conductive layers. As constructed, the conductive layers form a perimeter array of conductors around the waveguide interface that will define a waveguide interface perimeter in the molding compound. In addition or in the alternative, the conductive layers may form a conductive ring structure around the waveguide interface that will define a waveguide interface perimeter in the molding compound.

At step143, an external waveguide is attached with package terminations or connections to the waveguide wall or ring formed in the mold compound of the packaged semiconductor device. In selected embodiments, a ball grid array (BGA) or other leads can be attached to the waveguide wall or ring formed in the mold compound around the perimeter of the waveguide interface. In other embodiments, a conformal conductive attachment ring can be attached to the waveguide wall or ring formed in the mold compound around the perimeter of the waveguide interface. These package terminations around the perimeter of the circuit waveguide interface effectively extend the circuit waveguide interface outside the package, and thus can be used to connect the circuit waveguide interface to a waveguide or other element.

At step144, one or more additional backend of line (BEOL) and/or package processing steps are performed on the glass/ceramic carrier wafer/die. In selected embodiments, the processing at step144includes processing and singulating the molded compound, dies, and circuit waveguide interfaces into individual molded packages. This would typically be accomplished using a suitable sawing or scribing technique. So constructed, each package could include one or more IC dies and one or more associated circuit waveguide interfaces. After completion of the BEOL and/or package processing steps, the fabrication method ends.

The fabrication method130illustrates an example technique that facilitates the formation of a circuit waveguide interface during a WSDP process that is used to package a semiconductor device. The use of the WSDP process can allow the integration of a radiating element having short feed line with an adjacent air cavity formed in the high-k glass/ceramic carrier to address millimeter design challenges and to maximize the performance enhancement by providing an air cavity structure in waveguide short back that is designed to provide electrical matching and to reduce insertion loss to 1.0 dB or lower. Additionally, the use of the WSDP process can allow the formation of a packaged die and circuit waveguide interface with relatively little cost and process complexity (e.g., without requiring additional machining of the waveguide interface or an external waveguide adapter). Examples of embodiments and applications for the waveguide interface include millimeter wave (mmW) and radio frequency (RF) applications.

The embodiments described herein can provide circuit waveguide interfaces for semiconductor devices with both relatively high performance and low cost. In general, the embodiments described herein provide a differential pair to waveguide exciting element with a short feed line formed on the glass/ceramic carrier to connect to the attached die, thereby significantly reducing insertion loss. And by forming the waveguide interface with a high-k ceramic region of a glass/ceramic carrier which includes an air cavity that is adjacent to the waveguide exciting element, high frequency performance is improved for millimeter wave and radio frequency applications. Specifically, during the packaging process, photolithography and other wafer-type processing techniques are used to form one or more metallization layers (e.g., copper) in a wafer-like glass/ceramic panel, including a radiating element that is connected over a short feed line to a die attach area and a surrounding conductive via/ring pattern at the periphery of a circuit waveguide region. Subsequently, singulated die are arranged and attached on the wafer-like glass/ceramic panel, either before or after forming a partially recessed air cavity adjacent to the radiating element in the circuit waveguide region. After covering air cavity with a laminate sheet, a molding compound is injected or deposited over the die and radiating element to form an encapsulating package. A circuit waveguide interface is formed in the encapsulating package and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

By now it should be appreciated that there has been provided a method for making a package assembly, such as a wafer-scale die packaging device (WSDP) device. In the disclosed method, a glass carrier substrate is provided that is formed with a high-k dielectric material. In selected embodiments, the glass carrier substrate is provided as a class wafer formed with a material having a dielectric constant k that is greater than or equal to approximately k=5.8. The disclosed method also includes forming a ceramic region in the glass carrier substrate which includes a defined waveguide area and which extends to a defined die attach area. In selected embodiments, the ceramic region is formed by exposing the glass carrier substrate to a mask pattern having a mask opening over at least the defined waveguide area, and then baking the glass carrier substrate to convert any region of the glass carrier substrate exposed by the mask opening to ceramic, thereby forming the ceramic region. In addition, the disclosed method includes forming a plurality of conductive patterns on a first surface of the glass carrier substrate. The conductive patterns include a differential waveguide launcher disposed over the ceramic region and formed with a radiating element connected to a pair of signal lines extending from the defined waveguide area to the defined die attach area. In addition, conductive patterns include a patterned array of one or more conductors disposed over the ceramic region in a waveguide conductor ring positioned in the defined waveguide area to surround the radiating element on at least three sides. In selected embodiments, the conductive patterns may be formed by electroplating one or more conformal conductive layers over the first surface of the glass carrier substrate, and then selectively etching the one or more conformal conductive layers to form the differential waveguide launcher and the patterned array of one or more conductors as coplanar layers on the first surface of the glass carrier substrate. The disclosed method also includes forming an air cavity in the ceramic region that is positioned in the defined waveguide area to be adjacent to the radiating element and surrounded on at least three sides by the patterned array of one or more conductors. In selected embodiments, the air cavity may be formed by partially etching the ceramic region using a timed anisotropic etch to form the air cavity having a predetermined depth which leaves a thin layer of the ceramic region below the air cavity, and then covering the air cavity with a cap sheet comprising a laminate or non-conductive bonding layer of a low loss dielectric material. In addition, the disclosed method includes attaching a semiconductor die to the glass carrier substrate at the defined die attach area to make electrical connection to the differential waveguide launcher. The disclosed method also includes forming a molding compound that covers the semiconductor die and the plurality of conductive patterns, the molding compound having a first side attached to the glass carrier substrate and a second side opposite the first side. In addition, the disclosed method includes forming a first array of conductors in the molding compound that are aligned for connection with the plurality of conductive patterns, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior. In selected embodiments, the first array of conductors are formed by forming vias in the molding compound, and then filling the vias with conductive material. In selected embodiments, the disclosed method also includes physically coupling the first array of conductors to an external waveguide with an array of conductive balls. In other embodiments, the disclosed method also includes physically coupling the first array of conductors to an external waveguide with a conformal conductive electromagnetic interference O-ring gasket.

In another form, there is provided a wafer-scale packaged semiconductor device and associated method of manufacture. The disclosed semiconductor device includes a high-k dielectric carrier substrate having first and second carrier surfaces, where the high-k dielectric carrier substrate includes a glass layer surrounding a ceramic layer that defines a waveguide region and that extends partially into a die region formed in the glass layer. In selected embodiments, the high-k dielectric carrier substrate is formed with a material having a dielectric constant k of at least approximately k=5.8. In addition, the disclosed semiconductor device includes a first array of conductors formed on the first carrier surface to define a plurality of integrated circuit connection lines positioned in the die region, a separate waveguide ring positioned to substantially surround the waveguide region, and a separate excitation element positioned to extend from the die region to a first interior side of the waveguide region to be substantially surrounded by the separate waveguide ring waveguide region. In selected embodiments, the separate excitation element is a differential pair to waveguide launcher in package structure which may include one or more waveguide feed lines positioned to extend from the die region to the first interior side of the waveguide region, and a radiating element connected to the one or more waveguide feed lines and positioned on the first interior side of the waveguide region to be substantially surrounded by the separate waveguide ring. The disclosed semiconductor device also includes a semiconductor die attached to the plurality of integrated circuit connection lines and the separate excitation element on the first carrier surface of the high-k dielectric carrier substrate. In addition, the disclosed semiconductor device includes a first air cavity formed to extend partially into the ceramic layer from the first carrier surface and positioned on a second exterior side of the waveguide region to be substantially surrounded by the separate waveguide ring. The disclosed semiconductor device also includes a cavity cap sheet formed on the first carrier surface to cover the first air cavity. In addition, the disclosed semiconductor device includes a molding compound that encapsulates the semiconductor die and cavity cap sheet on the first carrier surface without filling the first air cavity. In selected embodiments, the disclosed semiconductor device may also include a second array of conductors extending from bottom to top surfaces of the molding compound and positioned to define a first waveguide interface perimeter surrounding a first waveguide interface interior. In such embodiments, the semiconductor device may include an array of conductive balls attached to the second array of conductors at the top surface of the molding compound, and an external waveguide physically coupled to the array of conductive balls. In other embodiments, the semiconductor device may include a conformal conductive electromagnetic interference O-ring gasket attached to the second array of conductors at the top surface of the molding compound, and an external waveguide physically coupled to the conformal conductive electromagnetic interference O-ring gasket. In selected embodiments, the disclosed semiconductor device may also include a conductive layer formed at the second carrier surface of the high-k dielectric carrier substrate to define a waveguide reflector interface layer.

In yet another form, there is provided a method for making a packaged semiconductor device, such as a wafer-scale die packaging device (W SDP) device. The disclosed method includes providing a high-k dielectric carrier substrate having first and second carrier substrate surfaces, where the high-k dielectric carrier substrate includes a glass layer surrounding a ceramic layer that defines and surrounds a millimeter waveguide region. The disclosed method also includes forming a first array of conductors on the first carrier substrate surface to define a plurality of integrated circuit connection lines positioned in a die region, a separate waveguide ring positioned to substantially surround the millimeter waveguide region, and a separate excitation element positioned to extend from the die region to the millimeter waveguide region with a peripheral end of the separate excitation element substantially surrounded by the separate waveguide ring. In selected embodiments, the formation of the first array of conductors includes forming the separate excitation element as a differential pair to waveguide launcher in package structure which includes one or more waveguide feed lines positioned to extend from the die region to the millimeter waveguide region, and a radiating element connected to the one or more waveguide feed lines and positioned in the millimeter waveguide region to be substantially surrounded by the separate waveguide ring. In addition, the disclosed method includes partially etching the ceramic layer to form a first air cavity positioned adjacent to the peripheral end of the separate excitation element in the millimeter waveguide region to be substantially surrounded by the separate waveguide ring. The disclosed method also includes attaching a semiconductor die including an integrated circuit to the plurality of integrated circuit connection lines and the separate excitation element on the first carrier surface of the high-k dielectric carrier substrate. In addition, the disclosed method includes attaching a laminate cap sheet on the first carrier substrate surface to cover the first air cavity. The disclosed method also includes encapsulating the semiconductor die, first array of conductors, and laminate cap sheet with a molding compound layer having a first side attached to the first carrier substrate surface and a second side opposite the first side. In selected embodiments, the disclosed method also includes forming a second array of conductors in the molding compound layer that are aligned for connection with the separate waveguide ring, the second array of conductors extending from the first side of the molding compound layer to the second side of the molding compound layer, thereby defining a first waveguide interface perimeter surrounding the millimeter waveguide region.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematics shown in the figures depict several exemplary arrangements of elements, additional intervening elements, devices, features, or components may be present in other embodiments of the depicted subject matter.