Wafer-level stacked chip assembly and chip layer utilized for the assembly

Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).

FIELD OF THE INVENTION

The present invention relates to a 3D IC chip stacking assembly of semiconductor chips and more specifically to a wafer-level stacked chip assembly and a chip layer utilized for the assembly.

BACKGROUND OF THE INVENTION

The purpose of the development of 3D IC for semiconductor chips is to dispose more chips on the limited footprint of a printed circuit board. The conventional fabrication processes of 3D IC chip stacking assembly is to acquire Known Good Dice (KGD) firstly, then vertically stack these KGDs to be a 3D IC assembly. However, if there is a failed chip in a 3D IC assembly, the whole 3D IC is discarded since the existing chip codes cannot be changed and the failed chip is included during operation leading to errors.

In a conventional 2D package of semiconductor chips, chips are selected and activated by a controller through Chip Select (CS) which has been designated for individual chips. Therefore, when the control signal CS1is sent by the controller for the first chip, only the first chip can react, operate, and function. When the control signal CS2is sent by the controller for the second chip, only the second chip can react, operate, and function.

As the development of 3D IC, chips are vertically stacked on each other and are electrically interconnected by Through Silicon Via (TSV). In order to control the vertically stacked chips with perpendicular electrical interconnection, the conventional control methodology is to implement staggered method to interconnect adjacent chips so that the controller can send commands to a certain chip for certain operations. The signals sent by the controller including commands, addresses, data, etc. are always transmitted from the top chip layer or from the bottom chip layer where the original CS command is designated and sent along with other signals to all chip layers, however, only the selected chip would accept the CS command from the controller and react accordingly. Gillingham taught one of conventional 3D IC chip assemblies referring to US Patent Publication No. US 2011/0050320 A1 for more detail. As described in this patent, the left-side first TSV of the first chip layer is electrically connected to the left-side second TSV of the second chip layer; the left-side second TSV of the first chip layer is electrically connected to the left-side third TSV of the second chip layer. In order to avoid floating of the left-side first TSVs of all chip layers except for the first chip layer which are not connected to any components, the left-side first TSV of each chip layer is not only connected to left-side second TSV of an upper chip layer but also connected to the left-side first TSVs of the upper chip layer. Through the interconnection arrangement, all vertically stacked chip layers with the corresponding array can clearly be defined and signal floating can be avoided.

The about mentioned CS is implemented in 3D IC assembly through staggered interconnection of CS signals achieved by physical 3D IC package structure. An alternative is developed by the coding methodology to replace the corresponding CS signals, i.e., to give each chip layer a corresponding array, an implementation of ID concept, through a sequence generator. Then, the specific ID array is decoded by a decoder to generate an activated signal where the corresponding I/O gates are activated to receive the corresponding signals sent from the controller so that the CS signal sent by the controller is accepted by a certain corresponding chip layer then to accept further commands for further operation.

Basically, the logic of a sequence generator always generates N output values when there are N input values. For example, if there are N input values to input nodes (in0, in1, in2, in3, . . . inN), there are N corresponding output values from output nodes (out0, out1, out2, out3, . . . outN), i.e., the input values and the output values are one-to-one corresponded. Furthermore, each output value is a function sequence of one corresponding input value, for example, output values (out0, out1, out2, out3, . . . outN)=F input values (in0, in1, in2, in3; . . . inN) and not every input value is equal to the corresponding output value, for example, output values (out0, out1, out2, out3, . . . outN)≠input values (in0, in1, in2, in3, . . . inN).

Since the function and the operation of a sequence generator is well-known in the field, therefore, only simple examples are illustrated as follows.

Basically, no matter it is a binary sequence generator or a triplet sequence generator, . . . or even N-bit sequence generator, the desired array is acquired by digital assembly algorithm. An example of input values and output values of a sequence generator is shown in Table 1 as follows.

A binary sequence generator can be referred to US Patent Publication No. US 2011/0050320 A1 for more detail.

Furthermore, the triplet sequence generator is illustrated by a ring counter to be used by I/O gates, where input values and output values of the triplet sequence generator are shown in Table 2 as follows.

The specific array generated either by binary sequence generator or by triplet sequence generator is gone through a decoder with a set of corresponding I/O gates to decide which chip layer is corresponding to the CS command.

As shown inFIG. 1, a chip layer200in a conventional 3D IC assembly has a conventional decoder260and a plurality of I/O gates231. The array generated by a binary sequence generator is input into the decoder260where the input values are sent through input nodes C0and C1. The output values sent through output nodes (G0, G1, G2, and G3) from the decoder260are corresponding to specific arrays to activate the I/O gates231. For example, when the input values to the decoder260of the first chip layer are (0, 0), then the corresponding array of the first chip layer sent from the decoder260are (G0, G1, G2, G3)=(1, 0, 0, 0).

Therefore, after decoding by the decoder260, only the I/O gates231of the first chip layer are activated and the rest of the I/O gates of other chip layers are not activated so that only CS1enters the allocated chip layer to be CS for the first chip layer and accept and react all signals from the controller with the corresponding functions and operation.

Similarly, when the input values are (1, 0) and sent to the decoder260of the second chip layer, then the corresponding array of the second chip layer sent from the corresponding decoder260are (G0, G1, G2, G3)=(0, 1, 0, 0). After decoding by the decoder260, only the I/O gate231of the second chip layer are activated and the rest of the I/O gates of other chip layers are not activated so that only CS2enters the second chip layer to be CS for the second chip layer and accept and react all signals from the controller with the corresponding functions and operation. In the same way with the same algorithm, the third chip layer and the fourth chip layer only accept CS3and CS4as CS commands to accept and react all signals from the controller with the corresponding functions and operation.

This above mentioned algorithm with the control methodology is quite different from the one using staggered interconnection of CS signals achieved by physical 3D IC package structure. However, no matter I/O gates signals (G0, G1, G2, G3) are selected either by direct assignment or by a sequence generator, the existing control methodology is to assign a group of CS signals to each chip layer activated by the commands sent by the controller to the corresponding chip layer for the corresponding functions and operation where the chip coding sequence has to be strictly corresponding to the stacking sequence of 3D IC. Once there is a failed chip layer or failed chip layers among the 3D IC, the whole 3D IC would be malfunctioned and discarded leading to poor overall yield issues.

FIG. 2is an illustration of 3D IC fabrication processes of a conventional wafer-level stacked chip assembly where it is clearly illustrated that all the individual chip layers200have to be tested first to be KGD and only can be vertically stacked after singulation including vertically stacking a plurality of chip layers200on a substrate40with a controller30adjacent to the stacked chip assembly to drive the desired chip layer200. Once there are one or several failed chip layers, the whole stacked chip assembly is malfunctioned and discarded.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide a wafer-level stacked chip assembly and chip layers utilized for the assembly to resolve packaging yield issues of the conventional chip stacked assembly when involving a failed chip layer or failed chip layers in the stacked chip assembly after packaging and testing where the conventional whole chip stacked assembly has to be discarded to realize the mass production and implementation of wafer-level stacked chip assembly.

The second purpose of the present invention is to provide a wafer-level stacked chip assembly and chip layers utilized for the assembly to provide chip stacking flexibility either in packaging processes or in testing processes for the wafer-level stacked chip assembly.

According to the present invention, a wafer-level stacked chip assembly is revealed, comprising two or more stacked chip layers where each chip layer includes a switching mechanism for selectively bypassing chip coding sequence, a plurality of vertical download terminals, a plurality of upload terminals, and an IC circuitry area. The switching mechanism is built inside each corresponding chip layer where the switching mechanism comprises a plurality of vertically interconnected input terminals and output terminals, a sequence generator, a decoder, a plurality of multiplexers, and a chip shutter. Each transmitting path between the input terminals and the output terminals can be divided into a coding path and a non-coding bypass. The sequence generator is connected to the coding paths to define the corresponding identification code of an allocated one of the chip layers. The decoder is connected to a plurality of I/O gates between the sequence generator and the IC circuitry area wherein the decoder has a plurality of first input nodes to receive a corresponding identification code generated by the corresponding sequence generator. The multiplexers are connected between the output terminals and the input terminals wherein each multiplexer has a second input node connected to the sequence generator through the coding path and a third input node connected to the non-coding bypass respectively, an output node of each multiplexer is connected to the corresponding one of the output terminals. The chip shutter is disposed inside the chip layer for closing the I/O gates of the corresponding IC circuitry area with a closing priority comparing to the decoder, wherein the chip shutter is also connected to a selected node of each multiplexer to switch the selection of the multiplexers between the coding paths and the non-coding bypasses.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the attached drawings, the present invention is described by means of the embodiment(s) below where the attached drawings are simplified for illustration purposes only to illustrate the structures or methods of the present invention by describing the relationships between the components and assembly in the present invention. Therefore, the components shown in the figures are not expressed with the actual numbers, actual shapes, actual dimensions, nor with the actual ratio. Some of the dimensions or dimension ratios have been enlarged or simplified to provide a better illustration. The actual numbers, actual shapes, or actual dimension ratios can be selectively designed and disposed and the detail component layouts may be more complicated.

According to the first embodiment of the present invention, a wafer-level stacked chip assembly is illustrated inFIG. 3for a partial circuit diagram. The wafer-level stacked chip assembly10comprises two or more vertically stacked chip layers100where each chip layer100comprises a switching mechanism110for selectively bypassing chip coding sequence, a plurality of vertical download terminals121, a plurality of vertical upload terminals122, and an IC circuitry area130. The switching mechanism110is built inside each corresponding chip layer100. The vertical download terminals121and the vertical upload terminals122have the vertical corresponding relationship. In the present embodiment, for example, the vertical download terminals121are electrically connected to the vertical upload terminals122by TSVs as signal I/O pins. The IC circuitry area130specifically is a non-volatile memory area such as NAND flash but without limitation, the IC circuitry area130also can be various memory such as DRAM, NOR flash, FPGA, etc. The switching mechanism110has the function of skipping one-time chip code sequence and shutting down the corresponding IC circuitry area130of a failed chip layer100which can be within the same stacked chip assembly or any adjacent chip layers according to the chip coding sequence. InFIG. 3, only two chip layers100have been illustrated for easy comprehension. In the actual product, the number of the stacked chip layer100of a wafer-level stacked chip assembly10can be four or above or even up to eight or sixteen.

The switching mechanism110comprises a plurality of vertically interconnected input terminals141and output terminals142, a sequence generator150, a decoder160, a plurality of multiplexers170, and a chip shutter180. There are a plurality of transmitting paths connect the input terminals141with the corresponding output terminals142where the input terminals141and the output terminals142are located at the opposing surfaces of the same chip layer100. As shown inFIG. 3, the input terminals141can be located at D0and D1positions and the output terminals142can be located at E0and E1positions. The input terminals141and the output terminals142are specifically conducted bumps such as copper pillar bumps or gold bumps whereFIG. 4illustrates when the chip shutter180is deactivated and theFIG. 5illustrates when the chip shutter180is activated.

Each transmitted path between the input terminals141and the corresponding output terminals142is divided into a coding path143and a non-coding bypass144where the sequence generator150is connected to the coding paths143to define the corresponding identification code of an allocated one of the chip layers100. The allocated chip layer is one of the chip layers100having the sequence generator150or another adjacent good chip layer stacked on the one of the chip layers100having the sequence generator150. In this embodiment, the allocated chip layer is another chip layer, that is to say, the corresponding identification code generated from the sequence generator150is assigned to next stacked good chip layer. The non-coding bypasses144do not connected to the sequence generator150but directly connected to the multiplexers170. As shown inFIG. 3again, after the input values at the input terminals In0, In1go through the sequence generator150, another set of logic array is generated to be the specific identification code for next stacked chip layer. According to different interconnection, identification code for each stacked chip layer generated by the sequence generator150can be corresponding to an adjacent good chip layer100. Even an adjacent failed chip layer100has the same identification code, the chip function of the failed chip layer100is closed and its sequence is stopped by the chip shutter180. Therefore, every good chip layer100must correspond to one counted identification code in sequence. Since there is possible that failed chip layer can be located on the same level, the circuitry design can be much easier without complication. The failed chip layer may include the following causes such as IC damage, poor vertical interconnection of the download and upload terminals, excessive lower threshold operation frequency, or algorithm mistakes caused by IC circuitry inside chip layers.

FIG. 6is to illustrate the interconnection between the decoder160and the I/O gates131. The decoder160is connected to a plurality of I/O gates131disposed between the sequence generator150and the IC circuitry area130. Therein, the decoder160has a plurality of first input nodes C0, C1to receive a corresponding identification code generated by the corresponding sequence generator150. In this embodiment, the corresponding identification code is generated by a sequence generator150of a pre-stacked lower good chip layers100. The output nodes (G0, G1, G2, G3) of the decoder160are connected to the I/O gates131of the IC circuitry area130. According to the interconnection, one set of the decoder160and the corresponding sequence generator150can be located at two adjacent good chip layers100. Alternatively, the decoder160and the corresponding sequence generator150are located within the same chip layer100. As shown inFIG. 3, the first input nodes (C0, C1) of the decoder160are connected to the connected points (C0, C1) of the transmitted paths before the input nodes (In0, In1) of the sequence generator150where the output nodes (out0, out1) from the sequence generator150are connected and uploaded to the adjacent chip layer100through the multiplexers170. And the output nodes (out0, out1) from the sequence generator150may not be connected to the decoder160on the same chip layer100. In the present embodiment, the interaction between the decoder160and the corresponding sequence generator150are located at two adjacent chip layers100respectively. The sequence generator150of the lower good chip layer100provides an identification code for the decoder160of the adjacent, upper, and good chip layer100above which is under the condition that the chip shutter180of the upper good chip layer100above is deactivated. When the chip shutter180of an adjacent failed chip layer100above is activated, the identification code provided by the lower chip layer100skips the upper stacked failed chip layer100and keep the same identification code until connecting to the decoder160of the next stacked good chip layer100one or more layers above. In a preferred embodiment, the decoder160has a deselect node161where the chip shutter180is connected to the deselect node161of the decoder160to obtain the closing priority. Moreover, the decoder160selectively operates the appropriate I/O gates according to the commands sent by the controller where the decoding methodology is not described in detail herein.

The multiplexers170are connected between the output terminals142and the input terminals141where wherein each multiplexer170has a second input node A connected to the sequence generator150through the coding path143and a third input node B connected to the non-coding bypass144respectively, an output node of each multiplexer170is connected to the corresponding one of the output terminals142as shown inFIG. 3. The input signals of the multiplexers170are chosen either from the coding path143or from the non-coding bypass144according to the definition of SEL signal line.

The chip shutter180is disposed inside the corresponding chip layer100. The major function of the chip shutter180is for closing the I/O gates131of the IC circuitry area130with a closing priority comparing to the decoder160so that the closed I/O gates131are completely isolated with the download terminals121when the chip shutter180is activated. The chip shutter180is also connected to a select node of each multiplexer170by a SEL line to switch the selection of the multiplexers170between the coding paths143and the non-coding bypasses144through the control of the open/short conditions of the second input nodes A and the third input nodes B. Either the third input nodes B of the multiplexers170connected to the non-coding bypasses144or the second input nodes A of the multiplexers170connected to the coding paths143are selected according to the chip shutter180is activated or not. When the chip shutter180is activated, the I/O gates131are closed whatever the decoder160is worked or not. Preferably, the chip shutter180specifically includes a fuse181to provide an activating command from the chip shutter180when the fuse181is broken so that the third input nodes B of the multiplexers170are selected to allow the input terminals141are connected with the corresponding output terminals142through the non-coding bypasses144by skipping the sequence generator150. In a different embodiment, a chip layer activating command can be provided by the open/short status of the fuse181. In other words, the status of the IC circuitry area130on the same chip layer100can be acquired by the fuse181to send a deactivating command or an activating command to the multiplexers170through SEL signal line. Based on the command, the multiplexers170select to go through non-coding bypass144or to go through coding path143according to the pre-defined algorithm to let the output signal from the latch circuits190to be the input signal of the lower or upper chip layer100or to let the logic array generated by the sequence generator150to enter the decoder160of the lower or upper chip layer100.

To be more specific, the switching mechanism110further comprises a plurality of latch circuits190connected to the multiplexers170, the sequence generator150and the decoder160and also connected to the input terminals141where the contact points S of the latch circuits190as shown inFIG. 3are the input points from the input terminals141. The contact points Q of the latch circuits190are the output points to the multiplexers170, the sequence generator150, and the decoder160. Therefore, the latch circuits190can provide an initial value to the sequence generator150and the decoder160so that the output signals from the latch circuits190are transmitted to the third input nodes B of the multiplexers170, to the first input nodes C0, C1of the decoder160and to the sequence generator150as shown inFIG. 3. Furthermore, the switching mechanism110further comprises a reset circuit182connected the chip shutter180with the latch circuits190where the reset circuit182can connect to the contact point R of the latch circuits190as shown inFIG. 3. The latch circuits190are able to latch the input signal from the input terminal141or the reset signal from the reset circuit182to provide an initial value. In the present embodiment, for example, since the decoder160of the bottom chip layer100cannot receive an identification code from the sequence generator150of the chip layer100further below, the latch circuits190on the same chip layer100provide an initial value and is transmitted to the first input nodes C0, C1of the decoder160where the initial values from the output terminals Q of the latch circuits190also become the input values In0, In1of the sequence generator150to generate a logic array as identification code to be the output values out0, out1from the sequence generator150. When the multiplexers170accepts the command from the SEL signal line, the logic array from the sequence generator150, and the output signals from the latch circuits190, the multiplexers170select one type of transmitted paths through the second input nodes A or through the third input nodes B according to the command definition. When the allocated chip layer100is good, the multiplexers170select the second input nodes A and let the logic array of the sequence generator150go through to enter the next chip layer100. Moreover, the output signal from the latch circuits190or the logic array from the sequence generator150can be input values of different decoder160to be CS to the corresponding chip layer100.

As shown inFIG. 4andFIG. 5, the fuse181is composed by connecting a current limiting resistor to VDD. When the reset signal is sent, the logic values from the contact point D are latched at the contact point Q. Through the selection of SEL signal lines, the fuse181can be connected to the multiplexers170and to be controlled by the reset signal. When one of the stacked chip layer100has a good chip function, the inside fuse181is conducted. As shown inFIG. 4, the chip shutter180is not activated so that the signals from the rest circuit182are conducted to the GND without activating the chip shutter180. Therefore, the input signals for the multiplexers170are connected to the coding paths143so that the KGD chip layer100can be normally coding where the IC circuitry area130can be driven, i.e., the second input nodes A is open and the contact point B is close according to the definition when a chip layer is normally activated or a chip layer is under no command. Furthermore, the reset signal is sent to the latch circuits190to generate the initial values mentioned above.

As shown inFIG. 5, when a chip layer100is a failed chip, the fuse181can be broken by either high voltage or by laser. The signal from the reset circuit182can be sent to activate the chip shutter180. When the chip shutter180is activated, a shutting command is sent to the multiplexers170through the corresponding SEL signal lines so that the input signal of the multiplexers170connect to the non-coding bypasses144, i.e., the third input nodes B are connected and the second input nodes A do not be selected as shown inFIG. 3. At the same time, the shutting command is sent to the deselect node161of the decoder160to close the I/O gates131. When the chip shutter180is not activated, a deactivated or no command is sent to the decoder160through one of the SEL signal lines connected to the deselect node161of the decoder160, the decoder160does not make any deselect action where the corresponding I/O gates131to the corresponding IC circuitry area130can be selectively close or open. In other words, the shutting command orders the output signals of the decoder160along with the connected I/O gates131all to be compulsory closed and accept no command from the controller. However, in the present invention, it is not limited that the fuse181of the KGD is conducted so that the chip shutter180does not be activated. The alternative is to interchange the multiplexers170so that the chip shutter180is activated when the chip layer is KGD and change the deactivating command into activating command. Through the SEL signal lines given to the multiplexers170, the input signals of the multiplexers170can be connected to the coding path143to normally perform coding and driving the IC circuitry area130of the KGD chip layer100. Furthermore, in a different embodiment, the fuse181can be replaced by a memory device or any control circuit with memory.

FIG. 7is to illustrate that the wafer-level stacked chip assembly10can be achieved by wafer-level stacking technology where the wafer-level stacked chip assembly10is fabricated by stacking whole wafers instead of by individual chips. With the function of the switching mechanism110, any failed chip layer100is regarded as a dummy chip where the coding sequence of the chip is skipped to avoid the activation of the failed IC circuitry area130. Therefore, even if there are failed chip layers100in the wafer-level stacked chip assembly10, the coding sequence and the good IC circuitry area130do not be affected. In the present invention, no matter there are good chip layers or failed chip layers, the wafer-level stacking technology still can be implemented even with failed chip layers existing in the wafer-level stacked chip assembly10where the coding sequence of the failed chip layer100and the failed IC circuitry area130are skipped to achieve more flexibility in the wafer-level stacking technology. For example, all wafers can be stacked then followed by singulation and functional test can be performed after chip stacking so when there are failed chip layers100in the wafer-level stacked chip assembly10, the failed chip layers100can be skipped or shut down. The wafer-level stacked chip assembly10is not discarded due to some failed chip layers100.

FIG. 8is a cross-sectional view of a wafer-level stacked chip assembly10joined on a controller30where the controller30is SMT on a substrate40where the wafer-level stacked chip assembly10is joined to a controller30where the controller30is SMT on a substrate40such as a printed circuit broad to reduce the overall footprint.

Therefore, a wafer-level stacked chip assembly and chip layers utilized for the assembly is revealed in the present invention where the coding sequence of the stacked chip layers100is not necessary the same as the chip stacking sequence. In a stacked assembly with four stacked chips, if the second chip layer is failed, then the first chip layer can be coded as 1 or a corresponding carrying number. The second failed chip layer is not coded or coded as X which is not included in the coding sequence and regarded as a dummy chip and being skipped. The third chip layer can be coded as 3 or the corresponding carrying number and the fourth chip layer can be coded as 4 or the corresponding carrying number where specific chip layers can be skipped or shut down according to the desired purpose to resolve packaging yield issues of the conventional chip stacked assembly when involving a failed chip layer or failed chip layers in the stacked chip assembly10after packaging and testing where the whole chip stacked assembly10has to be discarded to realize the mass production and implementation of wafer-level stacked chip assembly. Furthermore, the wafer-level stacked chip assembly10can provide chip stacking flexibility either in packaging processes or in testing processes. The wafer-level technology can be implemented in the chip stacking technology and the functional test can be performed after chip stacking where the deactivation of the failed chip layer100can be controlled.

According to the second embodiment of the present invention, another wafer-level stacked chip assembly10is illustrated inFIG. 9for a partial circuit diagram where the technology contents of the second embodiment is similar to the content of the first embodiment. The wafer-level stacked chip assembly10comprises a plurality of two or more vertically stacked chip layers100where each chip layer100comprises a switching mechanism110for selectively bypassing chip coding sequence, a plurality of vertical download terminals121, a plurality of vertical upload terminals122, and an IC circuitry area130. The switching mechanism110is built inside each corresponding chip layer100where the switching mechanism110comprises a plurality of vertically interconnected input terminals141and output terminals142, a sequence generator150, a decoder160, a plurality of multiplexers170, and a chip shutter180.

Each transmitted path between the input terminals141and the corresponding output terminals142can be divided into a coding path143and a non-coding bypass144where the sequence generator150is connected to the coding paths143to define the corresponding identification code of an allocated one of the corresponding chip layers100. The sequence generator150is connected to the coding paths143to define the corresponding identification code of an allocated one of the corresponding chip layers100. The decoder160is connected to a plurality of I/O gates131disposed between the sequence generator150and the IC circuitry area130, and the decoder160has a plurality of first input nodes C0, C1to receive a corresponding identification code generated by the corresponding sequence generator150. The multiplexers170are connected between the output terminals142and the input terminals141wherein each multiplexer170has a second input node A connected to the sequence generator150through the coding path143and a third input node B connected to the non-coding bypass144respectively, an output node of each multiplexer170is connected to the corresponding one of the output terminals142. The chip shutter180is disposed inside the corresponding chip layer100. The major function of the chip shutter180is to shut the I/O gates131of the IC circuitry area130with a closing priority where the chip shutter180is also connected to a select node of each multiplexer170through a signal line SEL to switch the selection of the multiplexers between the coding paths and the non-coding bypasses. In the present embodiment, the switching mechanism110further comprises a plurality of NOR logic gates132connected between the decoder160and the I/O gates of the IC circuitry area130where the chip shutter180is connected to the NOR logic gates132.

The above description of embodiments of this invention is intended to be illustrative but not limited. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure which still will be covered by and within the scope of the present invention even with any modifications, equivalent variations, and adaptations.