DIFFERENTIAL AMPLIFIER

A differential amplifier includes a first input terminal, second input terminals, output terminals, differential amplification circuits, and a current source circuit. The first input terminal is one of an inverting input terminal and a non-inverting input terminal. Each of the second input terminals is another of the inverting input terminal and the non-inverting input terminal. The output terminals output voltages respectively corresponding to the second input terminals. The differential amplification circuits are connected to the first input terminal and the second input terminals and are provided corresponding to the second input terminals. The current source circuit is connected to the differential amplification circuits. Each of the differential amplification circuits outputs an output voltage corresponding to a combination of a voltage inputted to the first input terminal and a voltage inputted to one of the second input terminals from a corresponding one of the output terminals.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Japan application serial no. 2022-134054, filed on Aug. 25, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a differential amplifier.

Related Art

Conventionally, in a large-scale system mounted with microcontrollers, AD/DA converters, motors, various communication systems, various sensors, etc., a regulator of a stabilized power supply circuit is generally used as a power supply of such a large-scale system.

The regulator is generally composed of an operational amplifier, an output transistor, and a feedback resistor.

Further, the operational amplifier is used as various types of amplifiers such as an inverting amplifier and a non-inverting amplifier composed of an input resistor and a feedback resistors, as an output buffer such as a voltage follower, and also as a component of various analog circuits such as a comparator taking an inverter as an output.

Patent Document 1 (Japanese Patent Application Laid-Open No. 2014-92869) discloses a configuration in which an operational amplifier, an output transistor, and a voltage dividing circuit are provided for a regulator.

Patent Document 2 (Japanese Patent Application Laid-Open No. 2021-18657) discloses a technique of controlling two output transistors respectively with different operational amplifiers for a series regulator.

Generally, the regulator uses an operational amplifier composed of a differential amplifier as in Patent Document 1. In a large-scale system, a plurality of regulators are required as in Patent Document 2. In other words, in the case where a plurality of regulators are provided as in a large-scale system, it is required to provide a plurality of differential amplifiers along with the regulators.

Furthermore, in a regulator, an amplifier, an output buffer, etc., since characteristics may deteriorate due to an overshoot of output, an undershoot, noise, or output distortion depending on the circuit connected to an output terminal, there may be cases where it cannot be connected in combination with other circuits to the same output terminal. For this reason, it is required to prepare individual regulators, amplifiers, and output buffers for these circuits. Thus, the circuit scale may increase.

SUMMARY

A differential amplifier according to an embodiment of the disclosure includes a first input terminal, a plurality of second input terminals, a plurality of output terminals, a plurality of differential amplification circuits, and a current source circuit. The first input terminal is one of an inverting input terminal and a non-inverting input terminal. Each of the plurality of second input terminals is another of the inverting input terminal and the non-inverting input terminal. The plurality of output terminals output voltages respectively corresponding to the plurality of second input terminals. The plurality of differential amplification circuits are connected to the first input terminal and the plurality of second input terminals and are provided corresponding to the plurality of second input terminals. The current source circuit is connected to the plurality of differential amplification circuits. Each of the plurality of differential amplification circuits outputs an output voltage corresponding to a combination of a voltage inputted to the first input terminal and a voltage inputted to one of the plurality of second input terminals from one of the plurality of output terminals.

A regulator according to an embodiment of the disclosure includes the above differential amplifier, and a plurality of output transistors connected to the plurality of output terminals. A plurality of feedback nodes connected to the plurality of output transistors are connected to the plurality of second input terminals. A reference voltage is inputted to the first input terminal.

An operational amplifier according to an embodiment of the disclosure includes the above differential amplifier, and a plurality of amplification circuits connected to the plurality of output terminals.

A comparator according to an embodiment of the disclosure includes the above differential amplifier, and a plurality of inverter circuits connected to the plurality of output terminals.

A differential amplifier according to an embodiment of the disclosure includes a first differential stage circuit, a second differential stage circuit, a first load circuit, a second load circuit, and a current source circuit. A reference voltage and a first input voltage are inputted to the first differential stage circuit. The reference voltage and a second input voltage are inputted to the second differential stage circuit. The first load circuit is provided between the first differential stage circuit and a first potential. The second load circuit is provided between the second differential stage circuit and the first potential. The current source circuit is provided between a second potential, which is different from the first potential, and the first differential stage circuit and the second differential stage circuit.

A differential amplifier according to an embodiment of the disclosure includes a differential stage circuit, a load circuit, and a current source circuit. The differential stage circuit includes a first transistor to which a reference voltage is inputted, a second transistor to which a first input voltage is inputted, and a third transistor to which a second input voltage is inputted. The load circuit is provided between the differential stage circuit and a first potential. The current source circuit is connected to the first transistor, the second transistor, and the third transistor. The differential stage circuit forms a first differential pair with the first transistor and the second transistor, and forms a second differential pair with the first transistor and the third transistor.

According to the embodiments of the disclosure, a differential amplifier capable of suppressing an increase in the circuit scale by realizing multiple inputs and multiple outputs, and a regulator, an operational amplifier, and a comparator including the differential amplifier are provided.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the disclosure provide a differential amplifier capable of suppressing an increase in the circuit scale by realizing multiple inputs and multiple outputs, and a regulator, an operational amplifier, and a comparator including the differential amplifier.

Hereinafter, embodiments of the disclosure will be described with reference to the drawings. In each drawing, substantially identical or equivalent constituent elements or parts will be labeled with the same reference signs.

Overview of Embodiments of Disclosure

FIG.18andFIG.19show differential amplifiers used in examples of related art.

The differential amplifier shown inFIG.18includes a current mirror circuit including a PMOS transistor P0and a PMOS transistor P1, a differential stage circuit including an NMOS transistor N0and an NMOS transistor N1having gates to which input terminals are connected, and a current source circuit including an NMOS transistor N4, an NMOS transistor N5having a gate connected to the gate of the NMOS transistor N4, and a bias current source ibp. A voltage of a feedback node fb is inputted to the NMOS transistor N0of the differential stage circuit, and a reference voltage Vref is inputted to the NMOS transistor N1. In the differential amplifier shown inFIG.18, a current is generated at the current mirror circuit according to a difference between the voltage of the feedback node fb and the reference voltage Vref inputted to the differential stage circuit. A voltage based on this current is outputted from an output terminal O as an output voltage.

Compared to the differential amplifier shown inFIG.18, the differential amplifier shown inFIG.19further includes an output stage circuit including a PMOS transistor P2having a gate connected between the PMOS transistor P1and the NMOS transistor N1, and a bias current source ibn. With the output stage circuit included, the differential amplifier shown inFIG.19may output any output voltage.

Thus, in the related art, since one differential amplifier corresponds to one output, to realize multiple inputs and multiple outputs, a plurality of differential amplifiers with identical characteristics are individually provided, which increases the circuit area.

Thus, in the embodiments of the disclosure, it is intended to realize multiple inputs and multiple outputs while suppressing an increase in the circuit area.

First Embodiment

FIG.1is a circuit block diagram showing a configuration of a differential amplifier10according to a first embodiment of the disclosure.

The differential amplifier10includes a first input terminal I1which is an inverting input terminal, second input terminals I21and I22which are non-inverting input terminals, output terminals O1and O2corresponding to the second input terminals I21and I22, differential amplification circuits12A and12B provided corresponding to the second input terminals I21and I22, and a current source circuit14connected to the differential amplification circuits12A and12B. A reference voltage Vref is inputted to the first input terminal I1, a voltage of a feedback node fb1is inputted to the second input terminal I21, and a voltage of a feedback node fb2is inputted to the second input terminal I22.

The differential amplification circuits12A and12B are configured to share the current source circuit14.

The differential amplification circuit12A outputs, from the output terminal O1, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit12B outputs, from the output terminal O2, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

Specifically, the differential amplification circuit12A includes a load circuit16A connected to a power supply potential having a power supply voltage, and a differential stage circuit17A connected to the first input terminal I1, the second input terminal I21, and the current source circuit14. The differential amplification circuit12B includes a load circuit16B connected to the power supply potential, and a differential stage circuit17B connected to the first input terminal I1, the second input terminal I22, and the current source circuit14.

The load circuit16A is a current mirror circuit including a PMOS transistor P0and a PMOS transistor P1. The source of the PMOS transistor P0and the source of the PMOS transistor P1are connected to the power supply potential, and the drain of the PMOS transistor P0and the drain of the PMOS transistor P1are connected to the differential stage circuit17A. The gate of the PMOS transistor P0and the gate of the PMOS transistor P1are connected to a node neg1at which the drain of the PMOS transistor P0and the differential stage circuit17A are connected.

The load circuit16A is a circuit that serves as a load of the differential stage circuit17A. The current flowing through the load circuit16A is determined according to a difference in voltages inputted to the differential stage circuit17A. Specifically, the current flowing through the PMOS transistor P0is determined according to the difference in the voltages inputted to the differential stage circuit17A, and the current flowing through the PMOS transistor P1is determined according to the current flowing through the PMOS transistor P0.

The differential stage circuit17A includes an NMOS transistor N1having a gate to which the first input terminal I1is connected, and an NMOS transistor N0having a gate to which the second input terminal I21is connected. The drain of the NMOS transistor N0is connected to the drain of the PMOS transistor P0of the load circuit16A, and the drain of the NMOS transistor N1is connected to the drain of the PMOS transistor P1of the load circuit16A. The source of the NMOS transistor N0and the source of the NMOS transistor N1are connected to the current source circuit14via a node top. Further, the differential stage circuit17A may be said to include a differential pair composed of the NMOS transistor N0and the NMOS transistor N1as one pair.

The differential stage circuit17A is connected to the first input terminal I1and the second input terminal I21, and is a circuit that receives the voltages inputted to the differential amplification circuit12A. The differential stage circuit17A operates according to a difference in the inputted voltages.

The section between the drain of the PMOS transistor P1and the drain of the NMOS transistor N1is connected to the output terminal O1.

The load circuit16B is a current mirror circuit including a PMOS transistor P2and a PMOS transistor P3. The source of the PMOS transistor P2and the source of the PMOS transistor P3are connected to the power supply potential, and the drain of the PMOS transistor P2and the drain of the PMOS transistor P3are connected to the differential stage circuit17B. The gate of the PMOS transistor P2and the gate of the PMOS transistor P3are connected to a node neg2at which the drain of the PMOS transistor P2and the differential stage circuit17B are connected.

The load circuit16B is a circuit that serves as a load of the differential stage circuit17B. The current flowing through the load circuit16B is determined according to a difference in voltages inputted to the differential stage circuit17B. Specifically, the current flowing through the PMOS transistor P2is determined according to the difference in the voltages inputted to the differential stage circuit17B, and the current flowing through the PMOS transistor P3is determined according to the current flowing through the PMOS transistor P2.

The differential stage circuit17B includes an NMOS transistor N3having a gate to which the first input terminal I1is connected, and an NMOS transistor N2having a gate to which the second input terminal I22is connected. The drain of the NMOS transistor N3is connected to the drain of the PMOS transistor P3of the load circuit16B, and the drain of the NMOS transistor N2is connected to the drain of the PMOS transistor P2of the load circuit16B. The source of the NMOS transistor N2and the source of the NMOS transistor N3are connected to the current source circuit14via the node top. Further, the differential stage circuit17B may be said to include a differential pair composed of the NMOS transistor N3and the NMOS transistor N2as one pair.

The differential stage circuit17B is connected to the first input terminal I1and the second input terminal I22, and is a circuit that receives voltages inputted to the differential amplification circuit12B. The differential stage circuit17B operates according to a difference in the inputted voltages.

The section between the drain of the PMOS transistor P3and the drain of the NMOS transistor N3is connected to the output terminal O2.

The current source circuit14includes an NMOS transistor N4and an NMOS transistor N5having gates connected to each other, and a bias current source ibp. The drain of the NMOS transistor N4is connected to the differential stage circuit17A and the differential stage circuit17B, and the source of the NMOS transistor N4is connected to a ground potential having a ground voltage. The drain of the NMOS transistor N5, the gate of the NMOS transistor N4, and the gate of the NMOS transistor N5are connected to a node vbn, and the source of the NMOS transistor N5is connected to the ground potential. One terminal of the bias current source ibp is connected to the power supply potential, and the other terminal of the bias current source ibp is connected to the drain of the NMOS transistor N5.

The current source circuit14is a circuit that supplies a current to the differential amplification circuits12A and12B. The NMOS transistor N4and the NMOS transistor N5form a current mirror circuit. With this current mirror circuit, it is possible to supply a current generated at a bias current source ibp to the differential amplification circuits12A and12B.

Compared to the differential amplifier in the related art ofFIG.18, the differential amplifier10inFIG.1differs in that the differential amplification circuit12B and the output terminal O2are additionally provided. In other words, in the differential amplifier in the related art ofFIG.18, two differential amplifiers are required for two outputs; in contrast, the differential amplifier10inFIG.1can provide two outputs with one differential amplifier sharing the current source circuit14. Thus, compared to the differential amplifier in the related art ofFIG.18, it is possible to suppress an increase in the circuit scale in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that there are one first input terminal, two second input terminals, and two output terminals, but the disclosure is not limited thereto. In the case where there are N (N being 2 or more) second input terminals, N output terminals may be provided. In the case where there are N second input terminals and N output terminals, the quantity of the differential amplification circuit inFIG.1becomes N, and the quantity of the differential amplification circuits is determined according to the required quantity of the second input terminals and the output terminals.

In the differential amplifier10, the differential amplification circuits12A and12B operate individually. Specifically, the differential amplification circuit12A outputs, from the output terminal O1, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit12B outputs, from the output terminal O2, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

In the differential amplification circuit12A, a current is generated at the load circuit16A according to a difference between the reference voltage Vref and the voltage of the feedback node fb1inputted to the differential stage circuit17A. A voltage based on this current is outputted from the output terminal O1as an output voltage. Similarly, in the differential amplification circuit12B, a current is generated at the load circuit16B according to a difference between the reference voltage Vref and the voltage of the feedback node fb2inputted to the differential stage circuit17B. A voltage based on this current is outputted from the output terminal O2as an output voltage.

As described above, according to the differential amplifier10of the first embodiment of the disclosure, each of the differential amplification circuits outputs, from the corresponding output terminal, an output voltage corresponding to a combination of the voltage inputted to the first input terminal and the voltage inputted to the corresponding second input terminal. Thus, by realizing multiple inputs and multiple outputs, it is possible to suppress an increase in the circuit scale.

In the above embodiment, as an example, it has been described that the first input terminal is an inverting input terminal, and the plurality of second input terminals are non-inverting input terminals, but the disclosure is not limited thereto. The first input terminal may also be a non-inverting input terminal, and the plurality of second input terminals may also be inverting input terminals.

Second Embodiment

FIG.2is a circuit block diagram showing a configuration of a differential amplifier20according to a second embodiment of the disclosure.

The differential amplifier20includes a first input terminal I1which is an inverting input terminal, second input terminals I21and I22which are non-inverting input terminals, output terminals O1and O2corresponding to the second input terminals I21and I22, a differential amplification circuit22, output stage circuits28A and28B provided corresponding to the output terminals O1and O2, and a current source circuit24connected to the differential amplification circuit22. A reference voltage Vref is inputted to the first input terminal I1, a voltage of a feedback node fb1is inputted to the second input terminal I21, and a voltage of a feedback node fb2is inputted to the second input terminal I22.

The differential amplification circuit22is configured to share a partial circuit corresponding to the second input terminals I21and I22and connected to the first input terminal I1. In other words, the differential amplification circuit22may also be said to be a plurality of differential amplification circuits sharing a partial circuit connected to the first input terminal I1. Furthermore, the differential amplification circuit22is configured to share the current source circuit24.

The differential amplification circuit22outputs, from the output terminal O1, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit22outputs, from the output terminal O2, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

Specifically, the differential amplification circuit22includes a load circuit26connected to a power supply potential having a power supply voltage, and a differential stage circuit27connected to the first input terminal I1, the second input terminals I21and I22, and the current source circuit24.

The load circuit26is equivalent to two current mirror circuits sharing a PMOS transistor P0, and includes a PMOS transistor P0, a PMOS transistor P1, and a PMOS transistor P2. The source of the PMOS transistor P0, the source of the PMOS transistor P1, and the source of the PMOS transistor P2are connected to the power supply potential, and the drain of the PMOS transistor P0, the drain of the PMOS transistor P1, and the drain of the PMOS transistor P2are connected to the differential stage circuit27. The gate of the PMOS transistor P0, the gate of the PMOS transistor P1, and the gate of the PMOS transistor P2are connected to a node neg1at which the drain of the PMOS transistor P0and the differential stage circuit27are connected.

The load circuit26is a circuit that serves as a load of the differential stage circuit27. The current flowing through the load circuit26is determined according to a difference in voltages inputted to the differential stage circuit27. Specifically, the current flowing through the PMOS transistor P0is determined according to the difference in the voltages inputted to the differential stage circuit27, and the currents flowing through the PMOS transistor P1and the PMOS transistor P2are determined according to the current flowing through the PMOS transistor P0.

The differential stage circuit27is equivalent to two differential stage circuits sharing an NMOS transistor N0, and includes an NMOS transistor N0having a gate to which the first input terminal I1is connected, an NMOS transistor N1having a gate to which the second input terminal I21is connected, and an NMOS transistor N2having a gate to which the second input terminal I22is connected. The drain of the NMOS transistor N0is connected to the drain of the PMOS transistor P0of the load circuit26, the drain of the NMOS transistor N1is connected to the drain of the PMOS transistor P1of the load circuit26, and the drain of the NMOS transistor N2is connected to the drain of the PMOS transistor P2of the load circuit26. The source of the NMOS transistor N0, the source of the NMOS transistor N1, and the source of the NMOS transistor N2are connected to the current source circuit24via a node top. Further, the differential stage circuit27may be said to include a first differential pair composed of the NMOS transistor N0and the NMOS transistor N1as one pair, and a second differential pair composed of the NMOS transistor N0and the NMOS transistor N2as one pair.

The differential stage circuit27is connected to the first input terminal I1and the second input terminals I21and I22, and is a circuit that receives voltages inputted to the differential amplification circuit22. The differential stage circuit27operates according to a difference in the inputted voltages.

A node pos1, at which the drain of the PMOS transistor P1and the drain of the NMOS transistor N1are connected, is connected to the output terminal O1via the output stage circuit28A. A node pos2, at which the drain of the PMOS transistor P2and the drain of the NMOS transistor N2are connected, is connected to the output terminal O2via the output stage circuit28B.

The current source circuit24includes an NMOS transistor N4and an NMOS transistor N5having gates connected to each other, and a bias current source ibp. The drain of the NMOS transistor N4is connected to the differential stage circuit27, and the source of the NMOS transistor N4is connected to a ground potential having a ground voltage. The drain of the NMOS transistor N5, the gate of the NMOS transistor N4, and the gate of the NMOS transistor N5are connected to a node vbn, and the source of the NMOS transistor N5is connected to the ground potential. One terminal of the bias current source ibp is connected to the power supply potential, and the other terminal of the bias current source ibp is connected to the drain of the NMOS transistor N5.

The current source circuit24is a circuit that supplies a current to the differential amplification circuit22. The NMOS transistor N4and the NMOS transistor N5form a current mirror circuit. With this current mirror circuit, it is possible to supply a current generated at the bias current source ibp to the differential amplification circuit22.

The output stage circuit28A includes a PMOS transistor P3having a gate connected to the node pos1between the PMOS transistor P1and the NMOS transistor N1, and a bias current source ibn1. The source of the PMOS transistor P3is connected to the power supply potential, and the drain of the PMOS transistor P3is connected to the bias current source ibn1. One terminal of the bias current source ibn1is connected to the drain of the PMOS transistor P3, and the other terminal of the bias current source ibn1is connected to the ground potential. The section between the PMOS transistor P3and the bias current source ibn1is connected to the output terminal O1.

The output stage circuit28B includes a PMOS transistor P4having a gate connected to the node pos2between the PMOS transistor P2and the NMOS transistor N2, and a bias current source ibn2. The source of the PMOS transistor P4is connected to the power supply potential, and the drain of the PMOS transistor P4is connected to the bias current source ibn2. One terminal of the bias current source ibn2is connected to the drain of the PMOS transistor P4, and the other terminal of the bias current source ibn2is connected to the ground potential. The section between the PMOS transistor P4and the bias current source ibn2is connected to the output terminal O2.

The output stage circuit28A and the output stage circuit28B are circuits for supplying a desired voltage. By providing the output stage circuit, it is possible to change the set values of the PMOS transistor and the bias current source that form the output stage circuit to adjust the output voltage.

Compared to the differential amplifier in the related art ofFIG.19, the differential amplifier20inFIG.2differs in that the PMOS transistor P2, the NMOS transistor N2, the output stage circuit28A, and the output terminal O2are additionally provided. In other words, two differential amplifiers are required for two outputs in the conventional differential amplifier inFIG.19; in contrast, the differential amplifier20inFIG.2can provide two outputs with one differential amplifier sharing the current source circuit24, and the PMOS transistor P0of the load circuit26and the NMOS transistor N0of the differential stage circuit27, which are a partial circuit connected to the first input terminal I1. Thus, compared to the differential amplifier in the related art ofFIG.19, it is possible to suppress an increase in the circuit scale in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that there are one first input terminal, two second input terminals, and two output terminals, but the disclosure is not limited thereto. In the case where there are N (N being 2 or more) second input terminals, there may be N output terminals. In the case where there are N second input terminals and N output terminals, the quantity of a part of the differential stage circuit connected to the second input terminal and a part of the load circuit connected to the part of the differential stage circuit inFIG.2becomes N, and the quantity of the part of the differential stage circuit connected to the second input terminal and the part of the load circuit connected to the part of the differential stage circuit is determined according to the required quantity of the second input terminals and the output terminals.

In the differential amplifier20, the differential amplification circuits of the differential amplification circuit22that share the partial circuit connected to the first input terminal I1operate individually. Specifically, the differential amplification circuit22outputs, from the output terminal O1via the output stage circuit28A, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit22outputs, from the output terminal O2via the output stage circuit28B, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

In the differential amplification circuit22, a current is generated at the PMOS transistor P0and the PMOS transistor P1of the load circuit26according to a difference between the reference voltage Vref and the voltage of the feedback node fb1respectively inputted to the NMOS transistor N0and the NMOS transistor N1of the differential stage circuit27. A voltage based on this current is outputted from the output terminal O1via the output stage circuit28A as an output voltage. Similarly, in the case of the NMOS transistor N0and the NMOS transistor N2of the differential stage circuit27, a current is generated at the PMOS transistor P0and the PMOS transistor P2of the load circuit26according to a difference between the reference voltage Vref and the voltage of the feedback node fb2respectively inputted to the NMOS transistor N0and the NMOS transistor N2of the differential stage circuit27. A voltage based on this current is outputted from the output terminal O2via the output stage circuit28B as an output voltage.

As described above, according to the differential amplifier20of the second embodiment of the disclosure, each of the differential amplification circuits sharing the partial circuit connected to the first input terminal outputs, from the corresponding output terminal, an output voltage corresponding to a combination of the voltage inputted to the first input terminal and the voltage inputted to the corresponding second input terminal. Thus, by realizing multiple inputs and multiple outputs, it is possible to suppress an increase in the circuit scale.

In the above embodiment, as an example, it has been described that the first input terminal is an inverting input terminal, and the plurality of second input terminals are non-inverting input terminals, but the disclosure is not limited thereto. The first input terminal may also be a non-inverting input terminal, and the plurality of second input terminals may also be inverting input terminals.

Third Embodiment

FIG.3is a circuit block diagram showing a configuration of a differential amplifier30according to a third embodiment of the disclosure. The differential amplifier30according to the third embodiment of the disclosure is configured by inverting the polarity of the differential amplifier10according to the first embodiment. Furthermore, the differential amplifier30according to the third embodiment of the disclosure further includes output stage circuits.

The differential amplifier30includes a first input terminal I1which is an inverting input terminal, second input terminals I21and I22which are non-inverting input terminals, output terminals O1and O2corresponding to the second input terminals I21and I22, differential amplification circuits32A and32B provided corresponding to the second input terminals I21and I22, a current source circuit34connected to the differential amplification circuits32A and32B, and output stage circuits38A and38B provided corresponding to the output terminals O1and O2. A reference voltage Vref is inputted to the first input terminal I1, a voltage of a feedback node fb1is inputted to the second input terminal I21, and a voltage of a feedback node fb2is inputted to the second input terminal I22.

The differential amplification circuits32A and32B are configured to share the current source circuit34.

The differential amplification circuit32A outputs, from the output terminal O1via the output stage circuit38A, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit32B outputs, from the output terminal O2via the output stage circuit38B, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

Specifically, the differential amplification circuit32A includes a load circuit36A connected to a ground potential, and a differential stage circuit37A connected to the first input terminal I1, the second input terminal I21, and the current source circuit34. The differential amplification circuit32B includes a load circuit36B connected to the ground potential, and a differential stage circuit37B connected to the first input terminal I1, the second input terminal I22, and the current source circuit34.

The load circuit36A is a current mirror circuit including an NMOS transistor N0and an NMOS transistor N1. The source of the NMOS transistor N0and the source of the NMOS transistor N1are connected to the ground potential, and the drain of the NMOS transistor N0and the drain of the NMOS transistor N1are connected to the differential stage circuit37A. The gate of the NMOS transistor N0and the gate of the NMOS transistor N1are connected to a node neg1at which the drain of the NMOS transistor N1and the differential stage circuit37A are connected.

The load circuit36A is a circuit that serves as a load of the differential stage circuit37A. The current flowing through the load circuit36A is determined according to a difference in voltages inputted to the differential stage circuit37A. Specifically, the current flowing through the NMOS transistor N1is determined according to the difference in the voltages inputted to the differential stage circuit37A, and the current flowing through the NMOS transistor N0is determined according to the current flowing through the NMOS transistor N1.

The differential stage circuit37A includes a PMOS transistor P1having a gate to which the first input terminal I1is connected, and a PMOS transistor P0having a gate to which the second input terminal I21is connected. The drain of the PMOS transistor P0is connected to the drain of the NMOS transistor N0of the load circuit36A, and the drain of the PMOS transistor P1is connected to the drain of the NMOS transistor N1of the load circuit36A. The source of the PMOS transistor P0and the source of the PMOS transistor P1are connected to the current source circuit34via a node top. Further, the differential stage circuit37A may be said to include a differential pair composed of the PMOS transistor P0and the PMOS transistor P1as one pair.

The differential stage circuit37A is connected to the first input terminal I1and the second input terminal I21, and is a circuit that receives voltages inputted to the differential amplification circuit32A. The differential stage circuit37A operates according to a difference in the inputted voltages.

A node pos1, at which the drain of the NMOS transistor N0and the drain of the PMOS transistor P0are connected, is connected to the output terminal O1via the output stage circuit38A.

The load circuit36B is a current mirror circuit including an NMOS transistor N2and an NMOS transistor N3. The source of the NMOS transistor N2and the source of the NMOS transistor N3are connected to the ground potential, and the drain of the NMOS transistor N2and the drain of the NMOS transistor N3are connected to the differential stage circuit37B. The gate of the NMOS transistor N2and the gate of the NMOS transistor N3are connected to a node neg2at which the drain of the NMOS transistor N3and the differential stage circuit37B are connected.

The load circuit36B is a circuit that serves as a load of the differential stage circuit37B. The current flowing through the load circuit36B is determined according to a difference in voltages inputted to the differential stage circuit37B. Specifically, the current flowing through the NMOS transistor N3is determined according to a difference in voltages inputted to the differential stage circuit37B, and the current flowing through the NMOS transistor N2is determined according to the current flowing through the NMOS transistor N3.

The differential stage circuit37B includes a PMOS transistor P3having a gate to which the first input terminal I1is connected, and a PMOS transistor P2having a gate to which the second input terminal I22is connected. The drain of the PMOS transistor P3is connected to the drain of the NMOS transistor N3of the load circuit36B, and the drain of the PMOS transistor P2is connected to the drain of the NMOS transistor N2of the load circuit36B. The source of the PMOS transistor P2and the source of the PMOS transistor P3are connected to the current source circuit34via the node top. Further, the differential stage circuit37B may be said to include a differential pair composed of the PMOS transistor P3and the PMOS transistor P2as one pair.

The differential stage circuit37B is connected to the first input terminal I1and the second input terminal I22, and is a circuit that receives voltages inputted to the differential amplification circuit32B. The differential stage circuit37B operates according to a difference in the inputted voltages.

A node pos2, at which the drain of the NMOS transistor N2and the drain of the PMOS transistor P2are connected, is connected to the output terminal O2via the output stage circuit38B.

The current source circuit34includes a PMOS transistor P4and a PMOS transistor P5having gates connected to each other, and a bias current source ibn. The drain of the PMOS transistor P4is connected to the differential stage circuit37A and the differential stage circuit37B, and the source of the PMOS transistor P4is connected to a power supply potential having a power supply voltage. The drain of the PMOS transistor P5, the gate of the PMOS transistor P4, and the gate of the PMOS transistor P5are connected to a node vbp, and the source of the PMOS transistor P5is connected to the power supply potential. One terminal of the bias current source ibn is connected to the ground potential, and the other terminal of the bias current source ibn is connected to the drain of the PMOS transistor P5.

The current source circuit34is a circuit that supplies a current to the differential amplification circuits32A and32B. The PMOS transistor P4and the PMOS transistor P5form a current mirror circuit. With this current mirror circuit, it is possible to supply a current generated at the bias current source ibn to the differential amplification circuits32A and32B.

The output stage circuit38A includes an NMOS transistor N4having a gate connected to the node pos1at which the PMOS transistor P0and the NMOS transistor N0are connected, and a bias current source ibp1. The source of the NMOS transistor N4is connected to the ground potential, and the drain of the NMOS transistor N4is connected to the bias current source ibp1. One terminal of the bias current source ibp1is connected to the drain of the NMOS transistor N4, and the other terminal of the bias current source ibp1is connected to the power supply potential. The section between the NMOS transistor N4and the bias current source ibp1is connected to the output terminal O1.

The output stage circuit38B includes an NMOS transistor N5having a gate connected to the node pos2at which the PMOS transistor P2and the NMOS transistor N2are connected, and a bias current source ibp2. The source of the NMOS transistor N5is connected to the ground potential, and the drain of the NMOS transistor N5is connected to the bias current source ibp2. One terminal of the bias current source ibp2is connected to the drain of the NMOS transistor N5, and the other terminal of the bias current source ibp2is connected to the power supply potential. The section between the NMOS transistor N5and the bias current source ibp2is connected to the output terminal O2.

The output stage circuit38A and the output stage circuit38B are circuits for supplying a desired voltage. By providing the output stage circuit, it is possible to change the set values of the NMOS transistor and the bias current source that form the output stage circuit to adjust the output voltage.

Compared to a differential amplifier configured by inverting the polarity of the differential amplifier in the related art ofFIG.19, the differential amplifier30inFIG.3differs in that the differential amplification circuit32B, the output stage circuit38B, and the output terminal O2are provided. In other words, two differential amplifiers are required for two outputs in the differential amplifier configured by inverting the polarity of the differential amplifier in the related art ofFIG.19; in contrast, the differential amplifier30inFIG.3can provide two outputs with one differential amplifier sharing the current source circuit34. Thus, compared to the differential amplifier configured by inverting the polarity of the differential amplifier in the related art ofFIG.19, it is possible to suppress an increase in the circuit scale in the case where multiple outputs are required.

In the above embodiment, as an example, it has described that there are one first input terminal, two second input terminals, and two output terminals, but the disclosure is not limited thereto. In the case where there are N (N being 2 or more) second input terminals, N output terminals may be provided. In the case where there are N second input terminals and N output terminals, the quantity of the differential amplification circuits inFIG.3becomes N, and the quantity of the differential amplification circuits is determined according to the required quantity of the second input terminals and the output terminals.

In the differential amplifier30, the differential amplification circuits32A and32B operate individually. Specifically, the differential amplification circuit32A outputs, from the output terminal O1via the output stage circuit38A, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit32B outputs, from the output terminal O2via the output stage circuit38B, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

In the differential amplification circuit32A, a current is generated at the load circuit36A according to a difference between the reference voltage Vref and the voltage of the feedback node fb1inputted to the differential stage circuit37A. A voltage based on this current is outputted from output terminal O1as an output voltage. Similarly, in the differential amplification circuit32B, a current is generated at the load circuit36B according to a difference between the reference voltage Vref and the voltage of the feedback node fb2inputted to the differential stage circuit37B. A voltage based on this current is outputted from the output terminal O2as an output voltage.

As described above, according to the differential amplifier30of the third embodiment of the disclosure, each of the differential amplification circuits outputs, from the corresponding output terminal, an output voltage corresponding to a combination of the voltage inputted to the first input terminal and the voltage inputted to the corresponding second input terminal. Thus, by realizing multiple inputs and multiple outputs, it is possible to suppress an increase in the circuit scale.

In the above embodiment, as an example, it has been described that the first input terminal is an inverting input terminal, and the plurality of second input terminals are non-inverting input terminals, but the disclosure is not limited thereto. The first input terminal may also be a non-inverting input terminal, and the plurality of second input terminals may also be inverting input terminals.

Fourth Embodiment

FIG.4is a circuit block diagram showing a configuration of a differential amplifier40according to a fourth embodiment of the disclosure. The differential amplifier40according to the fourth embodiment of the disclosure is configured by inverting the polarity of the differential amplifier20according to the second embodiment.

The differential amplifier40includes a first input terminal I1which is an inverting input terminal, second input terminals I21and I22which are non-inverting input terminals, output terminals O1and O2corresponding to the second input terminals I21and I22, a differential amplification circuit42, output stage circuits48A and48B provided corresponding to the output terminals O1and O2, and a current source circuit44connected to the differential amplification circuit42. A reference voltage Vref is inputted to the first input terminal I1, a voltage of a feedback node fb1is inputted to the second input terminal I21, and a voltage of a feedback node fb2is inputted to the second input terminal I22.

The differential amplification circuit42is configured to share a partial circuit corresponding to the second input terminals I21and I22and connected to the first input terminal I1. In other words, the differential amplification circuit42may also be said to be a plurality of differential amplification circuits sharing a partial circuit connected to the first input terminal I1. Furthermore, the differential amplification circuit42is configured to share the current source circuit44.

The differential amplification circuit42outputs, from the output terminal O1via the output stage circuit48A, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit42outputs, from the output terminal O2via the output stage circuit48B, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

Specifically, the differential amplification circuit42includes a load circuit46connected to a ground potential, and a differential stage circuit47connected to the first input terminal I1, the second input terminals I21and I22, and the current source circuit44.

The load circuit46is equivalent to two current mirror circuits sharing an NMOS transistor N0, and includes an NMOS transistor N0, an NMOS transistor N1, and an NMOS transistor N2. The source of the NMOS transistor N0, the source of the NMOS transistor N1, and the source of the NMOS transistor N2are connected to the ground potential, and the drain of the NMOS transistor N0, the drain of the NMOS transistor N1, and the drain of the NMOS transistor N2are connected to the differential stage circuit47. The gate of the NMOS transistor NO, the gate of the NMOS transistor N1, and the gate of the NMOS transistor N2are connected to a node neg1at which the drain of the NMOS transistor N0and the differential stage circuit47are connected.

The load circuit46is a circuit that serves as a load of the differential stage circuit47. The current flowing through the load circuit46is determined according to a difference in voltages inputted to the differential stage circuit47. Specifically, the current flowing through the NMOS transistor N0is determined according to the difference in the voltages inputted to the differential stage circuit47, and the currents flowing through the NMOS transistor N1and the NMOS transistor N2are determined according to the current flowing through the NMOS transistor N0.

The differential stage circuit47is equivalent to two differential stage circuits sharing a PMOS transistor P0, and includes a PMOS transistor P0having a gate to which the first input terminal I1is connected, a PMOS transistor P1having a gate to which the second input terminal I21is connected, and a PMOS transistor P2having a gate to which the second input terminal I22is connected. The drain of the PMOS transistor P0is connected to the drain of the NMOS transistor N0of the load circuit46, the drain of the PMOS transistor P1is connected to the drain of the NMOS transistor N1of the load circuit46, and the drain of the PMOS transistor P2is connected to the drain of the NMOS transistor N2of the load circuit46. The source of the PMOS transistor P0, the source of the PMOS transistor P1, and the source of the PMOS transistor P2are connected to the current source circuit44via a node top. Further, the differential stage circuit47may be said to include a first differential pair composed of the PMOS transistor P0and the PMOS transistor P1as one pair, and a second differential pair composed of the PMOS transistor P0and the PMOS transistor P2as one pair.

The differential stage circuit47is connected to the first input terminal I1and the second input terminals I21and I22, and is a circuit that receives voltages inputted to the differential amplification circuit42. The differential stage circuit47operates according to a difference in the inputted voltages.

A node pos1, at which the drain of the PMOS transistor P1and the drain of the NMOS transistor N1are connected, is connected to the output terminal O1via the output stage circuit48A. A node pos2, at which the drain of the PMOS transistor P2and the drain of the NMOS transistor N2are connected, is connected to the output terminal O2via the output stage circuit48B.

The current source circuit44includes a PMOS transistor P4and a PMOS transistor P5having gates connected to each other, and a bias current source ibn. The drain of the PMOS transistor P4is connected to the differential stage circuit47, and the source of the PMOS transistor P4is connected to a power supply potential having a power supply voltage. The drain of the PMOS transistor P5, the gate of the PMOS transistor P4, and the gate of the PMOS transistor P5are connected to a node vbp, and the source of the PMOS transistor P5is connected to the power supply potential. One terminal of the bias current source ibn is connected to the ground potential, and the other terminal of the bias current source ibn is connected to the drain of the PMOS transistor P5.

The current source circuit44is a circuit that supplies a current to the differential amplification circuit42. The PMOS transistor P4and the PMOS transistor P5form a current mirror circuit. With this current mirror circuit, it is possible to supply a current generated at the bias current source ibn to the differential amplification circuit42.

The output stage circuit48A includes an NMOS transistor N3having a gate connected to the node pos1at which the NMOS transistor N1and the PMOS transistor P1are connected, and a bias current source ibp1. The source of the NMOS transistor N3is connected to the ground potential, and the drain of the NMOS transistor N3is connected to the bias current source ibp1. One terminal of the bias current source ibp1is connected to the drain of the NMOS transistor N3, and the other terminal of the bias current source ibp1is connected to the power supply potential. The section between the NMOS transistor N3and the bias current source ibp1is connected to the output terminal O1.

The output stage circuit48B includes an NMOS transistor N4having a gate connected to the node pos2at which the NMOS transistor N2and the PMOS transistor P2are connected, and a bias current source ibp2. The source of the NMOS transistor N4is connected to the ground potential, and the drain of the NMOS transistor N4is connected to the bias current source ibp2. One terminal of the bias current source ibp2is connected to the drain of the NMOS transistor N4, and the other terminal of the bias current source ibp2is connected to the power supply potential. The section between the NMOS transistor N4and the bias current source ibp2is connected to the output terminal O2.

The output stage circuit48A and the output stage circuit48B are circuits for supplying a desired voltage. By providing the output stage circuit, it is possible to change the set values of the NMOS transistor and the bias current source that form the output stage circuit to adjust the output voltage.

Compared to a differential amplifier configured by inverting the polarity of the differential amplifier in the related art ofFIG.19, the differential amplifier40inFIG.4differs in that the NMOS transistor N2, the PMOS transistor P2, the output stage circuit48B, and the output terminal O2are additionally provided. In other words, two differential amplifiers are required for two outputs in the differential amplifier configured by inverting the polarity of the conventional differential amplifier inFIG.19; in contrast, the differential amplifier40inFIG.4can provide two outputs with one differential amplifier sharing the current source circuit44, and the NMOS transistor N0of the load circuit46and the PMOS transistor P0of the differential stage circuit47, which are the partial circuit connected to the first input terminal I1. Thus, compared to the differential amplifier configured by inverting the polarity of the differential amplifier in the related art ofFIG.19, it is possible to suppress an increase in the circuit scale in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that there are one first input terminal, two second input terminals, and two output terminals, but the disclosure not limited thereto. In the case where there are N (N being 2 or more) second input terminals, there may be N output terminals. In the case where there are N second input terminals and N output terminals, the quantity of a part of the differential stage circuit connected to the second input terminal and a part of the load circuit connected to the part of the differential stage circuit inFIG.4becomes N, and the quantity of the part of the differential stage circuit connected to the second input terminal and the part of the load circuit connected to the differential stage circuit is determined according to the required quantity of the second input terminals and the output terminals.

In the differential amplifier40, the differential amplification circuits of the differential amplification circuit42that share the partial circuit connected to the first input terminal I1operate individually. Specifically, the differential amplification circuit42outputs, from the output terminal O1via the output stage circuit48A, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I21. The differential amplification circuit42outputs, from the output terminal O2via the output stage circuit48B, an output voltage corresponding to a combination of the voltage inputted to the first input terminal I1and the voltage inputted to the second input terminal I22.

In the differential amplification circuit42, a current is generated at the NMOS transistor N0and the NMOS transistor N1of the load circuit46according to a difference between the reference voltage Vref and the voltage of the feedback node fb1respectively inputted to the PMOS transistor P0and the PMOS transistor P1of the differential stage circuit47. A voltage based on this current is outputted from the output terminal O1via the output stage circuit48A as an output voltage. Similarly, in the case of the PMOS transistor P0and the PMOS transistor P2of the differential stage circuit47, a current is generated at the NMOS transistor N0and the NMOS transistor N2of the load circuit46according to a difference between the reference voltage Vref and the voltage of the feedback node fb2respectively inputted to the PMOS transistor P0and the PMOS transistor P2of the differential stage circuit47. A voltage based on this current is outputted from the output terminal O2via the output stage circuit48B as an output voltage.

As described above, according to the differential amplifier40of the fourth embodiment of the disclosure, each of the differential amplification circuits sharing the partial circuit connected to the first input terminal outputs, from the corresponding output terminal, an output voltage corresponding to a combination of the voltage inputted to the first input terminal and the voltage inputted to the corresponding second input terminal. Thus, by realizing multiple inputs and multiple outputs with one differential amplifier, it is possible to suppress an increase in the circuit scale.

In the above embodiment, as an example, it has been described that the first input terminal is an inverting input terminal, and the plurality of second input terminals are non-inverting input terminals, but the disclosure is not limited thereto. The first input terminal may also be a non-inverting input terminal, and the plurality of second input terminals may also be inverting input terminals.

Fifth Embodiment

FIG.5is a circuit block diagram showing a configuration of a regulator50according to a fifth embodiment of the disclosure.

As an example, the regulator50will be described to include the differential amplifier10described in the first embodiment. A reference voltage Vref is applied to the first input terminal I1of the differential amplifier10. The output terminal O1of the differential amplifier10is connected to the gate of a PMOS transistor P10. The regulator50includes a series circuit52including the PMOS transistor P10and feedback resistors R0and R1.

The source of the PMOS transistor P10is connected to a power supply potential having a power supply voltage, and the drain of the PMOS transistor P10is connected to the feedback resistor R0. One terminal of the feedback resistor R0is connected to the drain of the PMOS transistor P10, and the other terminal of the feedback resistor R0is connected to the feedback resistor R1. One terminal of the feedback resistor R1is connected to the other terminal of the feedback resistor R0, and the other terminal of the feedback resistor R1is connected to a ground potential having a ground voltage.

The section between the drain of the PMOS transistor P10and the one terminal of the feedback resistor R0is connected to an output terminal O10. The output terminal O10is connected to the ground potential via a capacitor Cout1. A feedback node fb1between the feedback resistors R0and R1is connected to the second input terminal I21of the differential amplifier10.

The output terminal O2of the differential amplifier10is connected to the gate of a PMOS transistor P20. The regulator50includes a series circuit54including the PMOS transistor P20and feedback resistors R2and R3.

The source of the PMOS transistor P20is connected to the power supply potential, and the drain of the PMOS transistor P20is connected to the feedback resistor R2. One terminal of the feedback resistor R2is connected to the drain of the PMOS transistor P20, and the other terminal of the feedback resistor R2is connected to the feedback resistor R3. One terminal of the feedback resistor R3is connected to the other terminal of the feedback resistor R2, and the other terminal of the feedback resistor R3is connected to the ground potential.

The section between the drain of the PMOS transistor P20and the one terminal of the feedback resistor R2is connected to an output terminal O20. The output terminal O20is connected to the ground potential via a capacitor Cout2. A feedback node fb2between the feedback resistors R2and R3is connected to the second input terminal I22of the differential amplifier10.

The regulator50inputs the reference voltage Vref to the first input terminal I1, which is a non-inverting terminal of the differential amplifier10, inputs the voltage of the feedback node fb1to the second input terminal I21, which is an inverting terminal of the differential amplifier10, and keeps an output voltage Vout1of the output terminal O10constant.

Further, the regulator50inputs the reference voltage Vref to the first input terminal I1, which is the non-inverting terminal of the differential amplifier10, inputs the voltage of the feedback node fb2to the second input terminal I22, which is an inverting terminal of the differential amplifier10, and keeps an output voltage Vout2of the output terminal O20constant.

At this time, in the differential amplifier10, the differential amplification circuits12A and12B operate individually. Further, by making the voltage division ratio of the feedback resistors R0and R1different from the voltage division ratio of the feedback resistors R2and R3, it is possible to generate individual output voltages Vout1and Vout2.

FIG.6shows a characteristics diagram of the output voltage of the regulator50. It is learned that the regulator50generates individual output voltages Vout1and Vout2according to a power supply voltage VDD.

As described above, according to the regulator50of the fifth embodiment, since multiple inputs and multiple outputs can be provided with one regulator, it is possible to suppress an increase in the circuit scale compared to the conventional art in which multiple regulators are provided in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that the regulator50is formed using the differential amplifier10described in the first embodiment, but the disclosure is not limited thereto. As shown inFIG.5, the regulator50may also be formed using the differential amplifier20,30, or40described in the second embodiment to the fourth embodiment.

Sixth Embodiment

FIG.7is a circuit block diagram showing a configuration of an operational amplifier80according to a sixth embodiment of the disclosure.

The operational amplifier80is connected to input terminals in+, in1−, and in2−, and output terminals out1and out2.

FIG.8is a circuit block diagram showing a specific configuration of the operational amplifier80according to the sixth embodiment shown inFIG.7. As an example, the operational amplifier80will be described to include the differential amplifier20described in the second embodiment.

The first input terminal I1of the differential amplifier20is connected to the input terminal in+, and the second input terminals I21and I22are connected to the input terminals in1− and in2−.

The output terminal O1of the differential amplifier20is connected to the gate of a PMOS transistor P10. The operational amplifier80includes an amplification circuit82A which is a series circuit including the PMOS transistor P10and a bias current source ibn10. The source of the PMOS transistor P10is connected to a power supply potential having a power supply voltage, and the drain of the PMOS transistor P10is connected to the bias current source ibn10. One terminal of the bias current source ibn10is connected to the drain of the PMOS transistor P10, and the other terminal of the bias current source ibn10is connected to a ground potential having a ground voltage. The section between the drain of the PMOS transistor P10and the one terminal of the bias current source ibn10is connected to the output terminal out1.

The output terminal O2of the differential amplifier20is connected to the gate of a PMOS transistor P20. The operational amplifier80includes an amplification circuit82B which is a series circuit including the PMOS transistor P20and a bias current source ibn20. The source of the PMOS transistor P20is connected to the power supply potential, and the drain of the PMOS transistor P20is connected to the bias current source ibn20. One terminal of the bias current source ibn20is connected to the drain of the PMOS transistor P20, and the other terminal of the bias current source ibn20is connected to the ground potential. The section between the drain of the PMOS transistor P20and the one terminal of the bias current source ibn20is connected to the output terminal out2.

An inverting amplifier90as shown inFIG.9, for example, is formed using the operational amplifier80.

For example, a reference voltage Vref is applied to the input terminal in+ of the operational amplifier80in the inverting amplifier90. Further, the input terminal in1− of the operational amplifier80is connected to an input voltage Vin and the output terminal out1via feedback resistors R0and R1. Further, the input terminal in2− of the operational amplifier80is connected to the input voltage Vin and the output terminal out2via feedback resistors R2and R3.

One terminal of the feedback resistor R0is connected to the input terminal in1− of the operational amplifier80, and the other terminal of the feedback resistor R0is connected to the output terminal out1of the operational amplifier80. One terminal of the feedback resistor R1is connected to the input voltage Vin, and the other terminal of the feedback resistor R1is connected to the one terminal of the feedback resistor R0and the input terminal in1− of the operational amplifier80. One terminal of the feedback resistor R2is connected to the input terminal in2− of the operational amplifier80, and the other terminal of the feedback resistor R2is connected to the output terminal out2of the operational amplifier80. One terminal of the feedback resistor R3is connected to the input voltage Vin and the one terminal of the feedback resistor R1, and the other terminal of the feedback resistor R3is connected to the one terminal of the feedback resistor R2and the input terminal in2− of the operational amplifier80.

The inverting amplifier90generates an output voltage Vout1of “−N times” the input voltage Vin according to the resistance ratio of the feedback resistors R0and R1, and generates an output voltage Vout2of “−N times” the input voltage Vin according to the resistance ratio of the feedback resistors R2and R3. At this time, in the differential amplifier20, the differential amplification circuit22sharing a partial circuit connected to the first input terminal I1operates individually. Further, by making the resistance ratio of the feedback resistors R0and R1different from the resistance ratio of the feedback resistors R2and R3, the inverting amplifier90can generate output voltages of “−N times” individually as the output voltages Vout1and Vout2.

FIG.10shows a characteristics diagram of the output voltage of the inverting amplifier90. It is learned that, by making the resistance ratio of the feedback resistors R0and R1different from the resistance ratio of the feedback resistors R2and R3, output voltages Vout1and Vout2of “−N times” (e.g., N=0.25, 0.5, 2, 4) the input voltage Vin are generated individually.

Further, a non-inverting amplifier100as shown inFIG.11, for example, is formed using the operational amplifier80.

For example, an input voltage Vin is applied to the input terminal in+ of the operational amplifier80in the non-inverting amplifier100. Further, the input terminal in1− of the operational amplifier80is connected to a reference voltage Vref and the output terminal out1via feedback resistors R0and R1. Further, the input terminal in2− of the operational amplifier80is connected to the reference voltage Vref and the output terminal out2via the feedback resistors R2and R3.

The non-inverting amplifier100generates an output voltage Vout1of “N times” the input voltage Vin according to the resistance ratio of the feedback resistors R0and R1, and generates an output voltage Vout2of “N times” the input voltage Vin according to the resistance ratio of the feedback resistors R2and R3. At this time, in the differential amplifier20, the differential amplification circuit22sharing a partial circuit connected to the first input terminal I1operates individually. Further, by making the resistance ratio of the feedback resistors R0and R1different from the resistance ratio of the feedback resistors R2and R3, the non-inverting amplifier100can generate output voltages of “N times” individually as the output voltages Vout1and Vout2.

FIG.12shows a characteristics diagram of the output voltage of the non-inverting amplifier100. It is learned that, by making the resistance ratio of the feedback resistors R0and R1different from the resistance ratio of the feedback resistors R2and R3, output voltages Vout1and Vout2of “N times” (e.g., N=1.25, 1.5, 2, 4) the input voltage Vin are generated individually.

Further, a voltage follower110as shown inFIG.13, for example, is formed using the operational amplifier80.

For example, an input voltage Vin is applied to the input terminal in+ of the operational amplifier80in the voltage follower110. Further, the input terminal in1− of the operational amplifier80is connected to the output terminal out1of the operational amplifier80by a feedback node. Further, the input terminal in2− of the operational amplifier80is connected to the output terminal out2of the operational amplifier80by a feedback node.

The voltage follower110generates output voltages of “1 time” the input voltage Vin.

At this time, in the differential amplifier20, the differential amplification circuit22sharing a partial circuit connected to the first input terminal I1operates individually. Further, the voltage follower110can generate output voltages of “1 time” individually as output voltages Vout1and Vout2.

FIG.14shows a characteristics diagram of the output voltage of the voltage follower110. It is learned that output voltages Vout1and Vout2of “1 time” the input voltage Vin are generated individually.

As described above, according to the operational amplifier80of the sixth embodiment, it is possible to form an inverting amplifier, a non-inverting amplifier, and a voltage follower of multiple inputs and multiple outputs with one operational amplifier. Thus, it is possible to suppress an increase in the circuit scale compared to the conventional art in which a plurality of these circuits are provided in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that the operational amplifier80is formed using the differential amplifier20described in the second embodiment, but the disclosure is not limited thereto. As shown inFIG.8, the operational amplifier80may also be formed using the differential amplifier30or40described in the third embodiment or the fourth embodiment.

Seventh Embodiment

FIG.7described above is a circuit block diagram showing a configuration of a comparator150according to a seventh embodiment of the disclosure.

The comparator150is connected to input terminals in+, in1−, and in2−, and output terminals out1and out2.

FIG.15is a circuit block diagram showing a specific configuration of the comparator150according to the seventh embodiment shown inFIG.7. As an example, the comparator150will be described to include the differential amplifier20described in the second embodiment.

The first input terminal I1of the differential amplifier20is connected to the input terminal in+, and the second input terminals I21and I22are connected to the input terminals in1− and in2−.

The output terminal O1of the differential amplifier20is connected to the output terminal out1via an inverter circuit X1.

The output terminal O2of the differential amplifier20is connected to the output terminal out2via an inverter circuit X2.

Further, a comparison device160as shown inFIG.16, for example, is formed using the comparator150.

For example, an input voltage Vin is applied to the input terminal in+ of the comparator150in the comparison device160. Further, a reference voltage Vref1is applied to the input terminal in1− of the comparator150. Further, a reference voltage Vref2is applied to the input terminal in2− of the comparator150.

An output voltage Vout1is outputted from the output terminal out1of the comparator150. Further, an output voltage Vout2is outputted from the output terminal out2of the comparator150.

The comparison device160generates an output voltage according to a result of comparing the input voltage Vin and the reference voltage Vref1, and generates an output voltage according to a result of comparing the input voltage Vin and the reference voltage Vref2. At this time, in the differential amplifier20, the differential amplification circuit22sharing a partial circuit connected to the first input terminal I1operates individually. Further, by setting any reference voltages Vref1and Vref2with respect to the input voltage Vin, output voltages according to the comparison results are outputted individually as the output voltages Vout1and Vout2.

Upper and lower parts ofFIG.17respectively show characteristics diagrams of the output voltage of the comparison device160. It is learned that output voltages Vout1and Vout2are generated individually according to the comparison results in the case where Vref1/Vref2=A and A<B<C<D.

As described above, according to the comparator150of the seventh embodiment, it is possible to form a comparison device of multiple inputs and multiple outputs with one comparator. Thus, it is possible to suppress an increase in the circuit scale compared to the conventional art in which a plurality of these circuits are provided in the case where multiple outputs are required.

In the above embodiment, as an example, it has been described that the comparator150is formed using the differential amplifier20described in the second embodiment, but the disclosure is not limited thereto. As shown inFIG.15, the comparator150may also be formed using the differential amplifier30or40described in the third embodiment or the fourth embodiment.

In each of above embodiments, as an example, it has been described that there are two second input terminals, but the disclosure is not limited thereto. There may also be three or more second input terminals. In that case, the output terminals and the differential amplification circuits may be provided in a same quantity as the second input terminals. In the differential amplifier having the same configuration as in the second embodiment and the fourth embodiment, the differential amplifier may be configured to be equivalent to the plurality of differential amplification circuits sharing a partial circuit connected to the first input terminal.

Further, in each of the above embodiments, as an example, it has been described that the load circuit is formed using a current mirror circuit, but the disclosure is not limited thereto. The load circuit may also be a cascode connection circuit or a circuit using diode connection.

Further, a phase compensation circuit may be further provided in each of the above embodiments.

Further, it is possible to use the above-described circuits in a bipolar process and a Bi-CMOS process. Further, it is also possible to use the above-described circuits as discrete components.