Low latency inter-die trigger serial interface for ADC

A packaged controller for closed-loop control applications includes two dice packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.

TECHNICAL FIELD

The present disclosure relates generally to controllers for closed-loop control applications, and more particularly relates to controllers for low-cost closed-loop control applications.

BACKGROUND INFORMATION

In microcontroller-based closed-loop control applications such as cost sensitive motor control and multi-channel power conversion applications, the microcontroller typically includes an Analog-to-Digital Converter (ADC) and a processor. The ADC is used to sample voltages and/or currents existing in the system being controlled. In some applications, these samples need to be taken at the same time or nearly at the same time because relationships between the quantities being measured are important. Accordingly, a set of related samples is taken, processing is then performed on the samples to calculate a control output, and then the control output is provided back to the system in order to control the system. This entire closed-loop sequence may need to be performed at a relatively rapid rate such as, for example, once every fifty microseconds or less.

In one conventional approach, several ADCs are provided so that the several ADCs can measure the required voltages and currents in parallel at the same time. This is generally a quite expensive solution due to the cost of providing multiple ADCs.

In another conventional approach, the microcontroller includes a single but relatively fast ADC. This ADC takes samples at the rate of, for example, one sample every microsecond. Samples are taken one at a time in series but due to the speed of the ADC the time delay between samples is acceptable. Due to the serial sampling, however, there remains less time for the processor to do the necessary processing on the samples before the end of the control loop cycle. In addition, the processor is generally interrupted after each ADC conversion is performed. In response to being interrupted, the processor switches contexts, reads the result of the ADC, stores the result, then starts the ADC in performing the next analog to digital conversion, and then switches contexts back in order to resume the processing task that it was performing before it was interrupted. Because these interruptions consume processing cycles, a relatively fast processor may be required in order to perform the processor's computational tasks in the time remaining. Providing the fast ADC and the fast processor may be undesirably expensive for some cost sensitive applications.

In another conventional approach, a DMA controller is provided in a Von Neumann architecture in order to offload the processor of the task of having to service the ADC. The DMA controller, however, competes with the processor for use of the main bus. Bus contention introduces unwanted complexities into the design of the control loop software. In addition, the DMA controller is often a large circuit and providing the DMA controller along with any necessary bus arbiter increases the size of the microcontroller die. A Harvard architecture can be employed so that the DMA controller can service the ADC over a second bus while the processor has uncontested use of the main bus, but providing such a Harvard architecture with the extra bus is also undesirably expensive.

SUMMARY

A packaged controller includes a first semiconductor die and a second semiconductor die that are packaged together in a semiconductor package. The first semiconductor die is manufactured using a first semiconductor fabrication process that is particularly suited to making digital logic and digital circuits, whereas the second semiconductor die is fabricated using a second semiconductor fabrication process that is particularly suited to making analog circuitry. The first die (the digital die) includes a processor, a first terminal (ASIG), a second terminal (SDATA), an analog-to-digital converter (ADC), a serial bus interface, and a sequencer. The second die (the analog die) includes a serial bus interface, a first terminal (ASIG), a plurality of sample/hold circuits, an analog multiplexer, and a second terminal (SDATA).

In response to a trigger signal, the sequencer on the first die causes a multi-bit value to be communicated in serial fashion across a low latency unidirectional serial link from the serial bus interface of the first die, across the second terminal (SDATA) of the first die, across the second terminal (SDATA) of the second die, and to the serial bus interface on the second die. The serial bus interface of the first die also outputs a serial bus clock SCLK to the serial bus interface of the second die to control the clocking of individual bits of the multi-bit value into a set of flip-flops in the second bus interface.

The system is programmable by the processor so that in response to receiving at least part of the multi-bit value onto the second die, the serial bus interface of the second die causes a sample/hold signal (S/H) supplied to the plurality of sample/hold circuits to be asserted. The multi-bit value also controls the analog multiplexer on the second die so that a voltage output by a selected one of the sample/hold circuits on the second die is coupled through the analog multiplexer onto the first terminal (ASIG) of the second die, and over to the first terminal (ASIG) of the first die, and onto an input lead of the ADC in the first die. Once the analog multiplexer is properly set by this mechanism, the sequencer causes the ADC to perform an analog-to-digital conversion, thereby generating an ADC output value. The AC output value is then written under control of the sequencer into a data buffer. By sending multiple such multi-bit values across the serial bus to the second die, multiple sample voltages that were captured at one time in the set of sample/hold circuits can be coupled, one by one, onto the input lead of the ADC in the first die for analog-to-digital conversion. The resulting set of ADC output values is stored into the data buffer. The sequencer may be programmed so that after these ADC output values have been stored in the data buffer, the sequencer then outputs an interrupt signal. The processor, once interrupted, can then read the ADC output values out of the data buffer in one efficient read process.

A latency period between the time when the trigger signal is asserted until the time when the sample/hold signal is asserted is less than eight periods of the serial bus clock signal SCLK. A latency period between the time when the trigger signal is asserted until the first bit value of the multi-bit value is output from the first die is less than approximately two periods of SCLK. These two low latency periods and the offloading of the processor of the task of having to manage a sequence of analog-to-digital conversions allows a relatively lower performance and lower cost processor to be employed and simplifies the writing of control loop software.

The sequencer includes a set of sequencer registers that are writable by the processor. The contents of each such sequencer register contains control and configuration information that determines how an associated ADC sample is to be taken. For example, one field of a sequencer register contains the multi-bit value that will be sent across the low latency serial bus interface to the second die in order to set up the analog multiplexer in the analog die and in order to assert the sample/hold signal as desired for the ADC conversion to be done. Once triggered, the sequencer steps through these sequencer registers and causes the indicated operations to be performed, one by one, until the last sequencer register that stores a legitimate sequencer register value has been handled. After the last sequencer register value has been handled, then the sequencer asserts the interrupt signal.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently is it appreciated that the summary is illustrative only. Still other methods, and structures and details are set forth in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.

DETAILED DESCRIPTION

FIG. 1is a simplified top-down conceptual diagram of a packaged power management controller circuit1in accordance with one novel aspect. Packaged controller1includes a first integrated circuit die2and a second integrated circuit die3that are disposed within an integrated circuit package4. The integrated circuit package4may be any suitable type of package. In the illustrated example, package4is a quad flat pack package that has no leads. Package4has package terminals disposed in a ring that extends around the periphery of the package. Reference numeral5identifies one such package terminal. Reference numeral6identifies a bond wire that connects a bond pad7on first die2to package terminal5. Bond pads such as bond pad7are also referred to as die terminals. The diagram ofFIG. 1is a simplification. Details of the lead frame and how the bond wires connect to the lead frame are not shown.

Each of the first die2and the second die3is pad limited. The dice are pad limited in that the size of each die is limited by the bond pads disposed around the periphery of the die and not by the semiconductor surface area occupied by the functional circuitry within the peripheral ring of pads. Although the pad limited problem could be avoided by employing flip-chip attach methods, conventional bond pads and wire bonds are employed in order to use more conventional and less expensive processes.

First die2is fabricated using a first semiconductor fabrication process that is particularly suited to making digital logic and digital circuits and memories. Second die3is fabricated using a second semiconductor fabrication process that is particularly suited to making analog circuitry. Although a single semiconductor fabrication process such as a BiCDMOS process could be used to realize the circuitry of both dice onto a single die, a single die solution using such a process is not used. Cost and performance advantages associated with using the first semiconductor fabrication process to make most of the digital circuitry of the controller are exploited by segregating most of the digital circuitry onto the first die and then manufacturing that die using a fabrication process better suited to making digital circuitry. Similarly, cost and performance advantages associated with using the second semiconductor fabrication process to make most of the analog circuitry of the controller are exploited by segregating most of the analog circuitry onto the second die and then manufacturing that die using a fabrication process better suited to making analog circuitry.

Due to the pad limited nature of the dice2and3of packaged controller1, a novel low latency serial bus is employed to reduce the number of connections between the first and second dice. First circuitry8on the first die2sends control information serially via die terminal9, bond wire10, and die terminal11to second circuitry12on second die3. First circuitry8also sends a serial bus clock signal via die terminal13, bond wire14, and die terminal15to the second circuitry12. The control information communicated from the first die to the second die via this serial bus is used on the second die to control when the sample/hold circuitry on the second die performs sampling, and to control how an analog multiplexer on the second die multiplexes analog sample signals onto a single terminal of the second die for communication back to an ADC on the first die. In the illustration ofFIG. 1, the analog sample signals are communicated back through die terminal16, through bond wire17, through die terminal18, and to the ADC in first circuitry8.

FIG. 2is a simplified diagram that illustrates the packaged controller1ofFIG. 1in a motor control application involving a fifty microsecond control loop cycle. Detail of digital die2is omitted so that more detail of analog die3can be shown. Packaged controller1controls currents that are driven through the three windings19,20and21of motor22as appropriate to drive the motor. A first pair of high-side and low-side external field effect transistors (FETs)23and24is coupled to common node25and motor terminal26. A second pair of high-side and low-side external FETs27and28is coupled to common node29and motor terminal30. A third pair of high-side and low-side external FETs31and32is coupled to common node33and motor terminal34. High-side driver circuits35,36and37drive the external high-side FETs23,27and31, respectively. Low-side driver circuits38,39and40drive the external low-side FETs24,28and32, respectively. A processor41(seeFIG. 3) on digital die2controls the high-side and low-side circuit circuits by writing digital values into an associated register (not shown) on the second die. The digital bit values stored in the various bit positions of the associated register determine whether the associated high-side and low-side drivers are driving their external FETs to be on or off. Current can be made to flow from the +48 volt supply conductor, into a selected motor terminal, through two windings of the motor, and out of a selected other motor terminal, and to a ground conductor.

The currents flowing out of the motor terminals26,30and34are made to flow across corresponding sense resistors42,43and44. The voltage drop across resistor42is sensed using package terminals45and46and differential amplifier47. The voltage drop across resistor43is sensed using package terminals48and49and differential amplifier50. The voltage drop across resistor44is sensed using package terminals51and52and differential amplifier53.

In addition to sensing currents, the packaged controller1senses the voltages on the three motor terminals26,30and34. The voltage on motor terminal26is divided down by resistive voltage divider54and56, with the resulting divided down voltage being sensed on package terminal56. The voltage on motor terminal30is divided down by resistive voltage divider57and58, with the resulting divided down voltage being sensed on package terminal59. The voltage on motor terminal34is divided down by resistive voltage divider60and61, with the resulting divided down voltage being sensed on package terminal62.

Analog die3includes a sample/hold circuit for sampling the voltage output by each of the differential amplifiers47,50and53. Similarly, there is a sample/hold circuit for sampling the voltage on each of package terminals56,59and62. Reference numerals63-69identify these six sample/hold circuits. All six sample/hold circuits are controlled by a common sample/hold signal69that is supplied to the sample/hold circuits via the same conductor70. When the sample/hold signal69has a digital logic low level, then the analog voltage signal on the input lead of a sample/hold circuit passes through the sample/hold circuit to the output lead of the sample/hold circuit. When the sample/hold signal69transitions from a digital logic low level to a digital logic high level, then the sample/hold circuit captures and holds the voltage present on its input lead. The voltage being output from the sample/hold circuit does not change until the sample/hold signal69returns to the digital logic low level. This circuitry is used to capture simultaneously six voltages: three voltages indicative of the currents flowing through the three windings of the motor, and three voltages indicative of the voltages on the three winding terminals of the motor. These six captured voltages are output simultaneously by the six sample/hold circuits63-68onto six corresponding data input leads of analog multiplexer71. Analog multiplexer71is usable to couple a selected one of these captured voltage signals back to an ADC on the first die via a single terminal16(ASIG) of the second die, via a bond wire connection17, and via a single terminal18(ASIG) of the first die.

FIG. 3shows the first circuitry8of first die2and the second circuitry12of second die3in more detail. First circuitry8includes a serial bus interface72, a first sequencer73, a second sequencer74, an analog multiplexer (denoted DMUX because it is a multiplexer on the digital die)75, an analog-to-digital converter76, a data buffer77, die terminals9,13,18and78, a sequencer mode control register79, and multiplexing circuits80-85. Processor41is the only master of a local bus involving an address bus86and a data bus87. Processor41fetches and executes instructions of control loop software92stored in processor-readable memory88. In this Von Neumann architecture, there is only one bus (the local bus86,87) coupling processor41, program and data memory88, and first circuitry8. Moreover, processor41is the only master of the local bus. Processor41can read from and write to memory88, timer/PWM block89, interrupt controller90, data buffer77, sequencer mode control register79, sequencers73and74, serial bus interface72, and a second serial bus interface91(for example, I2C or SPI) across the local bus86,87.

Second circuitry12includes a serial bus interface93, analog multiplexer71(denoted AMUX because it is the multiplexer on the analog die), and die terminals11,15,16and95. In addition to second circuitry12, the second die3includes the high-side and low-side drivers35-40, the sample/hold circuits63-68, the differential amplifiers47,50and53, numerous other die terminals (not numbered), analog die control logic96, and a second serial bus interface97. The second serial bus interface91of digital die2and the second serial bus interface97of analog die3together provide a second serial link across terminals98and99between dice2and3. This second serial link employs a standard serial protocol such as, for example, I2C or SPI. Inter-die connections are provided by bond wires17,101,10,14and100. In another example, the inter-die connections are not bond wires but rather are conductors that are part of package4.

FIG. 4is a more detailed circuit diagram of the serial bus interface72of the first die2and of the serial bus interface93of the second die3(the circuit diagram ofFIG. 4includes simplifications and is presented here in simplified form for instructional and illustrative purposes). Serial bus interface72of first die2includes a shift register102and a state machine103. One of the sequencers73or74can write an 8-bit DATAIN value in parallel into the shift register102synchronously with respect to the clock signal CLK. If the write enable signal WE is high at the time of a rising edge of CLK, then the 8-bit DATAIN value is parallel-loaded into the shift register regardless of the signal being received onto the shift enable SREN input lead. If WE is low, then the shift register will shift on a rising edge of the clock CLK if SREN is asserted high at the time of the rising edge of the clock CLK. In the illustration, the eight bits of the shift register102are shifted left to right, with the rightmost bit being output from the shift register onto die terminal9. The state machine103supplies a associated serial bus clock signal SCLK to the second die3via die terminal13, wire bond connection14, and die terminal15.

In the simplified illustration ofFIG. 4, the serial bus interface93of the second die3includes eight flip-flops (denoted D1through D8in the illustration), an inverter104, a 3-bit counter RXCNTR105, a decoder DEC106and logic block LOGIC107. If counter105is in the 000 state then decoder106supplies an enable signal to flip-flop D1but to no others of the flip-flops. Likewise, if counter105is in the 001 state then decoder106supplies an enable signal to flip-flop D2but to no others of the flip-flops. Similarly, if counter105is in the 010 state then decoder106supplies an enable signal to flip-flop D3but to no others of the flip-flops, and so forth. Flip-flops D1-D8do not form a shift register and SDATA bits are not shifted into the second die, but rather the individual flip-flops D1-D8are individually enabled and loaded with data one at a time depending on the state of RXCNTR105.

Initially, the RXCNTR counter is in the 000 state (state1) but SCLK is not clocking so none of the flip-flops D1-D2is loading any data. The serial bus interface72of the first die2then outputs a data bit value from the rightmost bit of shift register102. This bit is supplied to the data input leads of all the flip-flops D1-D8via conductor108. Only flip-flop D1is, however, enabled. On the falling edge of signal CLK, the serial bus interface72asserts the SCLK signal high that in turn clocks the data bit value into flip-flop D1. The next rising edge of CLK causes the next data bit to be shifted out of shift register102. On this rising edge of signal CLK, the serial bus interface72deasserts the SCLK signal low which in turn causes the RXCNTR counter105to increment to the 001 state (state2). This incrementing causes decoder106to enable the second flip-flop D2. Accordingly, on the next rising edge of SCLK, the second data bit is clocked into the second flip-flop D2. In this way, each successive bit of the 8-bit DATAIN value is shifted out of shift register102, through the second die terminal (SDATA)9of the first die, across inter-die connection10, through the second die terminal (SDATA)11of the second die, and is clocked into a corresponding one of the flip-flops D1-D8on second die3. The state machine103stops toggling the SCLK signal once all eight bits have been clocked into the flip-flops of the second die3.

FIG. 5is a more detailed diagram of the logic block107ofFIG. 4. The values stored in the first two bits (in the D1and D2flip-flops) indicate the meanings of the remaining six bit values of DATAIN. As indicated in the table ofFIG. 6, in the illustrated example the only used combination of bit values for D1and D2is 01. The other combinations of D1and D2are reserved and unused in this example.

If the values of these two bits D1and D2are 01, then the value of the third bit of the DATAIN value is to be supplied onto conductor70as the S/H signal69. If the value stored in flip-flop D3is a digital logic high then the S/H signal69is to have a digital logic high value, whereas if the value stored in flip-flop D3is a digital logic low then the S/H signal69is to have a digital logic low value. The values of the last four bits of the DATAIN value are to be output from logic block107as multiplexer control signal AMUXSEL[1:4]. AMUXSEL[1:4] is supplied onto the four conductors118that extend to the four select input leads of AMUX multiplexer71. To prevent unwanted glitching of the S/H signal69, the operation indicated by the first two bits D1and D2is decoded to be valid at the time of the third rising edge of SCLK. The third rising edge of SCLK occurs after the D1and D2flip-flops have both clocked in their respective bit values of the DATAIN value. The value of the third bit in D3is latched and output onto the S/H conductor70on the fifth rising edge of SCLK. Decoders109and110and flip-flops111and112ensure that the S/H signal69can only change at one time during the serial communication operation after the value stored in the corresponding D3flip-flop is stable.

One of the sequencers73or74can use this low latency serial bus interface to cause S/H signal69to be asserted so that all six sample/hold circuits63-68simultaneously perform sample and hold operations. If initially the logic value of S/H signal69is low, then the sequencer can load the serial bus interface72with a DATAIN value whose third bit value is a digital logic high. When the third bit of the DATAIN value is clocked into the third flip-flop D3of the second die, then the S/H signal69will transition from low to high, thereby causing the six sample/hold circuits63-68to hold.

In addition, a sequencer can change the value of AMUXSEL[1:4]. The sequencer may, for example, send multiple 8-bit DATAIN values to analog die3, where the last four bit values of the DATAIN values change so that one by one the analog sample voltages held in the various sample/hold circuits are multiplexed out through terminal ASIG16, across inter-die connection17, through terminal ASIG18, and to the ADC76in the digital die. The analog sample voltages passing between the dice across inter-die connection17are single-ended signals, whose voltages are relative to analog ground potential AGND on die terminals95and78.

As indicated inFIG. 7, each of the sequencers73and74has its own set of eight associated sequencer registers. InFIGS. 3 and 7, reference numeral113identifies the eight sequencer registers of sequencer73. Reference numeral114identifies the eight sequencer registers of sequencer74. Each sequencer registers has multiple fields as indicated inFIG. 7. In operation, a sequencer steps through its sequencer registers one at a time, using the contents of the sequencer register to set DMUX75and to set AMUX71. Note that the first 3-bit field of a sequencer register holds a 3-bit DMUX setting value for controlling DMUX75. Note that the last eight bits of a sequencer register hold an 8-bit DATAIN value (of which the last four bits are an AMUXSEL[1:4] setting value for controlling analog multiplexer71as described above). The level of the S/H signal is determined by the value of the third bit of the DATAIN value.

After the S/H signal has been changed as desired and after the select signals supplied to the DMUX and AMUX multiplexers have been set up as desired, then the sequencer initiates ADC76in performing an analog-to-digital conversion by asserting a start converter signal START ADC115on conductor116. In response, ADC76converts the analog voltage signal present on its analog input lead117into a corresponding multi-bit digital ADC output value on conductors118. ADC76has its own sample and hold circuit so once START ADC signal115has transitioned, the analog signal on the ADC input lead117can be changed without affecting the ongoing analog-to-digital conversion being performed by the ADC. After the analog-to-digital conversion has been completed, the sequencer then causes the ADC output value on conductors131to be written into the appropriate 10-bit location in data buffer77. In the representation of the table ofFIG. 7, the ADC output value that results from using the settings of an entry in a sequencer register is written into the 10-bit location in the data buffer that is on the same row as the sequencer register. The sequencer registers and the 10-bit locations in the data buffer are in a one-to-one relation. The processor41can set up the contents of the sequencer registers by writing across data bus86,87into the sequencers and thereafter starting the sequencers by sending them appropriate trigger signals. Because processor41programs the sequencer registers in this way, and because the corresponding 10-bit locations in the data buffer where the ADC output values will be written are predetermined and known to processor41, the processor41can later read the ADC output values from the data buffer via data bus86,87.

FIG. 8is a diagram that illustrates the various fields of a sequencer control register. Each of the two sequencers has one such sequencer control register. Sequencer control register119is the sequencer control register for sequencer73. Sequencer control register120is the sequencer control register for sequencer74. The value stored in field121indicates how many of the sequencer registers113of the first sequencer73contain legitimate entries. Similarly, the value stored in field122indicates how many of the sequencer registers114of the second sequencer74contain legitimate entries. After being triggered by a trigger signal, a sequencer proceeds through its sequencer registers, one by one, until all its sequencer registers that store legitimate values have been serviced. When all sequencer registers have been serviced, then the sequencer asserts an interrupt signal to interrupt controller90. The first sequencer73sends its interrupt signals via conductor124and the second sequencer743sends its interrupt signals via conductor125. Upon being interrupted by a sequencer, the processor41reads the associated locations in data buffer77via data bus86,87, thereby retrieving the ADC output values written there by the sequencer.

FIG. 9is a diagram that shows the three fields of the sequencer mode control register79ofFIG. 3. For example, if the first 3-bit field of the sequencer mode control register79stores the value 000, then only the first sequencer73is operational and that sequencer proceeds through its sequencer register values in response to receiving a trigger signal. Values in the sequencer control register119for the first sequencer73determine which one of multiple timer/PWM output signals will be used as the trigger signal. Another bit value in the sequencer control register119determines whether a rising edge of the trigger signal will start the sequencer or whether a falling edge of the trigger signal will start the sequencer. In the example ofFIG. 3, sequencer73is configured to trigger on a rising edge of trigger signal123. Trigger signal123is one of twelve signals output by the timers and PWM block89.

FIG. 10is a simplified waveform diagram illustrating an operation involving sequencer register contents where the 3-bit “TX-BUS TRANSMISSION WE START OPTIONS” field bits are set to the “SEND DATATIN AT BEGINNING OF SAMPLE SEQUENCE” option. In the illustrated example, the sequencer register is the first sequencer register for sequencer73. The sequencer mode control register79is set so that only sequencer73is used. Sequencer control register119for sequencer73is set so that the sequencer will trigger on the rising edge of trigger signal123. CLK is 50 MHz and the period of SCLK is 20 ns. Within one SCLK period of the timer block89asserting the trigger signal123high, a rising edge of CLK occurs. In response, sequencer73asserts its BUSY signal on conductor126, enters its sequence count “1” state, outputs the DMUXSEL values to DMUX75, starts a delay timer, supplies the 8-bit DATAIN value to serial bus interface72, and asserts the write enable signal WE high. On the next rising edge of the signal CLK, the DATAIN value is loaded in parallel fashion into shift register102. The state machine103transitions from its S9state to its S1state and asserts the shift enable SREN signal. Due to the DATAIN value being present in shift register102, the D1bit of the DATAIN value is output by the shift register102onto second die terminal (SDATA)9. The latency period between the asserting of the trigger signal69and the outputting of the D1bit onto second die terminal9is less than two periods of the serial bus clock signal SCLK.

Half a CLK period later, the state machine103asserts the SCLK signal high for the first time. This rising edge of SCLK causes the digital value D1on terminals9and11to be written into flip-flop D1in the analog die3. On the next rising edge of CLK, the shift register shifts, the D2value of DATAIN is present on terminal9. One half clock period later the D2value is clocked into flip-flop D2. After the first two bit values of DATAIN have been clocked into the flip-flops D1and D2in this way, the output of decoder109(seeFIG. 5) stabilizes. On the next falling edge of CLK, the decoder output value is clocked into flip-flop111. This is indicated in the waveform diagram ofFIG. 10by the changing of the operation signal OP half a clock cycle after rising CLK edge CA5. Similarly, after the loading of the third and fourth bit values of DATAIN into D3and D4, the output of decoder110(seeFIG. 5) stabilizes. On the next falling edge of CLK, the decoder output value is clocked into flip-flop112. This is indicated in the waveform diagram ofFIG. 10by the changing of the S/H signal half a clock cycle after CLK edge CA7. After all eight bit values are loaded into flip-flops D1-D8, then the AMUXSEL[1:4] values are stable. In the waveform ofFIG. 10, this occurs approximately half a clock cycle after rising CLK edge CA10. State machine103advances from state to state as the bit values of DATAIN are shifted out of shift register102, but once the last bit value has been shifted out then the state machine103deasserts the shift enable signal SREN. Similarly, after the last bit value has been clocked into flip-flop D8, then the state machine103stops the SCLK signal from changing levels. Accordingly, both the shift register102stops shifting and none of flip-flops D1-D8is enabled to clock in new data. The signals being output by flip-flops D1-D8do not change.

The internal signal DELAY transitions low after a number of clock cycles determined by the 4-bit DELAY SETTING field of the sequencer register value. The sequencer detects this internal signal being a low value, and in response on the next rising edge of CLK asserts ADC START signal115. As described above, this starts the ADC performing an analog-to-digital conversion. Whether the DATAIN value resulted in the asserting of the S/H signal (such that the sample/hold circuits captured new samples) is determined by whether the value of the S/H signal was made to transition high. How DMUX75is set is determined by the value of the DMUX setting field of the sequencer register value. How the analog multiplexer71is set is determined by the values of last four bits of DATAIN.

After a number of clock cycles amounting to about one microsecond, the ADC outputs an ADC output value onto conductors131. On rising CLK edge CB9the sequencer asserts the WR DATA BUF signal along with an associated address value. These signals are provided to the data buffer77via multiplexers82and83. As a result, the ADC output value is written into the 10-bit location in the data buffer that corresponds to the first sequencer register for sequencer73. Because in this example there is a second sequencer register value stored in the second sequencer register, the sequencer count advances to “2” and the next sequencer register value is serviced starting on the next rising CLK edge CB11.

Of importance, note that the level of the S/H signal69can be changed (for example, the S/H signal can be asserted in a low-to-high transition) in a latency period129of less than eight SCLK periods after the rising edge of trigger signal123. The S/H signal69can be asserted in this way even though all the DATAIN bit values have not yet been transferred to the analog die. In addition, within a latency period130of approximately two SCLK periods from the time of the asserting of the trigger signal, the first bit of DATAIN is being output from the digital die2onto SDATA terminal9.

In the illustrated example, there are no parity bits or error detection and correction for the S/H signal bit. Delays associated with error detection functionality are therefore avoided. If counter105on the analog die becomes desynchronized with respect to the state of state machine103on the digital die, then the circuitry on the analog die can be reset under the control of processor41by sending a reset command127to the analog die across the second serial bus. Analog die control96detects the reset command127and outputs a reset signal128that resets counter105and flip-flops D1-D8. After this resetting, the serial bus interface72on the digital die can send another complete DATAIN value with the serial bus interfaces on the digital and analog dice being properly synchronized with respect to one another. The reset command127is communicated across a higher latency bus, but the delay in the resetting of the serial bus interface93is acceptable. Such resetting occurs only very seldom and is an error condition.

FIG. 11is a simplified waveform diagram illustrating an operation involving sequencer register contents where the 3-bit “TX-BUS TRANSMISSION WE START OPTIONS” field bits are set to the “SEND DATATIN AFTER ADC START” option. In response to the trigger signal123being asserted high at the time of a rising edge of CLK, the sequencer73asserts its BUSY signal on conductor126, enters its sequence count “1” state, outputs the DMUXSEL values to DMUX75, and starts a delay timer as in the example ofFIG. 10, but in the example ofFIG. 11the sequencer73does not supply an 8-bit DATAIN value at rising CLK edge CA2. The 4-bit delay setting of the sequencer register value determines a number of clock cycles until the internal DELAY signal transitions low. At the end of the delay period, in response to the DELAY signal being a digital low, the sequencer73asserts the ADC START signal on the next rising CLK edge CB1. As mentioned above, ADC76has its own sample and hold circuitry, so once the ADC START signal115has transitioned high the analog voltage on the signal input lead of the ADC can be changed without affecting operation of the ADC. In the example ofFIG. 11, sequencer73asserts the write enable signal WE and outputs the DATAIN value starting at clock edge CB1. Accordingly, the DATAIN value bits are shifted out of the digital die and are loaded into the analog die at the same time that the ADC is performing an analog-to-digital conversion.

FIG. 12is a simplified waveform diagram illustrating an operation involving sequencer register contents where the 3-bit “TX-BUS TRANSMISSION WE START OPTIONS” field bits are set to the “DO NOT SEND DATATIN” option. The delay determined by the 4-bit delay setting transpires, and an analog-to-digital conversion occurs, but no DATAIN value is transferred from the digital die to the analog die. Accordingly, the AMUX setting and the S/H signal values are not changed.

Although the waveform examples ofFIGS. 10,11and12as shown starting with a pulsing high of a trigger signal, the pulsing of a trigger signal is generally only used to start a sequencer making a pass through its sequencer register entries. After handling one sequencer register entry, the sequencer automatically proceeds to the next sequencer register entry. A second trigger is not supplied. Once the sequencer has handled its last sequencer register entry (as determined by the applicable one of fields121and122that indicates the number of legitimate sequencer entries present), then the sequencer returns to an idle state and asserts an interrupt signal. The interrupt signal alerts processor41that the ADC output values are present in data buffer77.

There are two sequencers in the specific embodiment described. If one sequencer is busy as indicated by the BUSY signal it supplies to the other sequencer, then the other sequencer does not start a transaction across the low latency serial bus but rather waits a cycle of CLK and then retests the BUSY signal.

FIG. 13is a flowchart of a method1000in accordance with one novel aspect. In response to a trigger signal being asserted on a first die, a sequencer supplies (step1001) a multi-bit value to a serial bus interface. The sequencer and the serial bus interface are parts of the first die. The multi-bit value is then communicated (step1002) in serial fashion from the first die to a serial bus interface of a second die. The serial bus interface of the first die also supplies an associated serial bus clock (SCLK) to the second die. The multi-bit value includes a sample/hold value and an analog multiplexer setting value. In response to receiving the sample/hold value, a sample/hold signal on the second die is asserted (step1003) to a plurality of sample/hold circuits on the second die. In one example, this asserting of the sample/hold signal is a low-to-high transition of the sample/hold signal. A latency between the time when the trigger signal is asserted and the time when the sample/hold signal is asserted is less than eight periods of SCLK. The analog multiplexer setting value is used (step1004) on the second die to control an analog multiplexer on the second die such that a signal from a selected one of the sample/hold circuits is supplied through the analog multiplexer, through a single terminal of the second die, through a single terminal of the first die, and to an input load of an ADC on the first die. The sequencer then initiates (step1005) an analog-to-digital conversion such that the ADC outputs an ADC output value. The sequencer then causes (step1006) the ADC output value to be stored into a data buffer on the first die.

In one example, after the steps ofFIG. 13have been carried out, the sequencer on the first die causes a second multi-bit value to be communicated serially to the second die so that a second selected one of the sample/hold circuits is coupled through the analog multiplexer to the input lead of the ADC. The sequencer then initiates a second ADC conversion, and causes the resulting second ADC output value to be written into the data buffer. The sequencer repeats this process multiple times so that the that the voltage samples held in each of the various sample/hold circuits is multiplexed out of the second die and is digitized, one by one, by the ADC on the first die. After all the sample voltages held in the sample/hold circuits have been digitized as directed by the sequencer, the sequencer interrupts the processor. The processor can then read the ADC output values out of the data buffer in a single efficient read operation.