Method and apparatus for de-embedding on-wafer devices

A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

BACKGROUND

Integrated circuits (ICs) formed on semiconductor substrates include multiple active and passive components, such as resistors, inductors, capacitors, transistors, amplifiers, etc. Such components are fabricated to a design specification that defines the ideal physical/electrical characteristics the component will exhibit (e.g., resistance, inductance, capacitance, gain, etc.). Though it is desirable to verify that each component fabricated complies with its specific design specification, typically, after integration into a circuit, an individual component cannot be readily tested. Thus, “stand-alone” copies of the individual IC components, components fabricated with the same process and with the same physical/electrical characteristics as the IC components, are fabricated on the wafer; and it is assumed that the physical/electrical properties measured for the “stand-alone” copies represent those of the non-tested individual IC components.

During testing, the “stand-alone” copy, referred to as the “device-under-test” (DUT), is electrically connected to leads and test pads, which are further connected to external testing equipment. Though the physical/electrical properties measured should accurately represent those of the DUT (and the individual IC component represented), the test pads and leads contribute physical/electrical characteristics, known as “parasitics” (e.g., resistance, capacitance, and inductance from the test pads and leads), that contribute to the measured characteristics of the DUT. The parasitics are factored out or extracted by a process known as “de-embedding” to reveal the intrinsic characteristics of the DUT alone.

Thus, accurate de-embedding methods are required to eliminate the parasitic contributions and accurately describe the intrinsic characteristics of the DUT (and ultimately, the individual IC component represented). Currently, on-wafer de-embedding methods referred to as “open-short,” “open-thru,” and “thru-reflect-line” (“TRL”) have been widely used to subtract parasitics such as resistance, inductance, and capacitance arising from the test pads and leads at high frequencies (up to the GHz level). However, each of these methods presents problems: (1) the open-short method results in over de-embedding of the inductance parasitics from the lead metal lines; (2) the open-thru method accuracy depends on model fitting quality, often resulting in inaccurate parasitics extracted; (3) the TRL method requires at least three DUTs to cover a wide frequency range; and (4) all current methods use an approximate open pad.

Accordingly, what is needed is a test structure and method for improving the accuracy of de-embedding parasitics.

DETAILED DESCRIPTION

The present disclosure relates generally to the field of integrated circuits testing, and more particularly, to a system and method for de-embedding parasitics for on-wafer devices.

With reference toFIGS. 1 through 4B, a test structure100and a method400for accurately de-embedding parasitics for on-wafer devices are collectively described below. It is understood that additional features can be added in the test structure100, and some of the features described below can be replaced or eliminated, for additional embodiments of the test structure. It is further understood that additional steps can be provided before, during, and after the method400described below, and some of the steps described below can be replaced or eliminated, for additional embodiments of the method. The present embodiment of test structure100and method400significantly improves de-embedding accuracy of test structure parasitics, such as resistance, inductance, and capacitance.

Referring toFIG. 1, the test structure100comprises a first dummy component102, a second dummy component104, a first transmission line106, a second transmission line108, test pads110and112, and connecting lines114.

The first dummy component102is coupled with the second dummy component104. The first dummy component102comprises the first transmission line106. The second dummy component104comprises the second transmission line108. In the present embodiment, the second transmission line108has length L and the first transmission line106has length 2L (i.e., the first transmission line is two times longer than the second transmission line). The first and second transmission lines106,108also comprise the same width and lie on or within the same semiconductor wafer. It is understood that the first dummy structure106may comprise the first transmission line106with length L, and the second dummy structure108may comprise the second transmission line108with length 2L (i.e., the second transmission line is two times longer than the first transmission line). Further, in alternate embodiments, the first and second transmission lines106,108may comprise varying widths.

In test structure100, the first transmission line106and the second transmission line108are co-linear and may comprise any conducting material, such as aluminum, copper, aluminum-copper alloys, aluminum alloys, copper alloys, other metals, polysilicon, any other material, and/or combinations thereof. In alternate embodiments, the first and second transmission line may not be co-linear.

Both the first and second dummy components102,104further comprise the test pads110,112and connecting lines114. In the preferred embodiment, the test pads110and112are implemented in a ground-signal-ground (GSG) test configuration; and the test pads110comprise ground test pads, and the test pads112comprise signal test pads. However, it is understood that, in alternate embodiments, the test structure100may comprise other testing configurations, such as ground-signal (GS), ground-signal-ground-signal-ground (GSGSG), and/or any other suitable testing configurations. The ground test pads110are electrically connected to one another via connecting lines114. The signal test pads112are electrically connected via the first transmission line106and the second transmission line108. Further, the test pads110,112and connecting lines114may comprise any conducting material, such as aluminum, copper, aluminum-copper alloys, aluminum alloys, copper alloys, other metals, polysilicon, any other material, and/or combinations thereof. In alternate embodiments, the ground test pads110and signal test pads112may be electrically connected in other configurations, such as the ground test pads electrically connected via the first and second transmission lines, the signal test pads connected via connecting lines, and/or the ground and signal test pads electrically connected via the first and second transmission lines.

FIG. 2provides a top view of the test structure100coupled with a device-under-test (DUT)200. InFIG. 2, the first dummy component102couples with the second dummy component104, and the second dummy component couples with the DUT200. In the preferred embodiment, the test structure100is coupled with a co-planar wave guide (CPW). In alternate embodiments, the DUT200may be any other suitable DUT, such as a resistor, capacitor, diode, inductor, any other device on/in an integrated circuit, other co-planar wave guides, combinations thereof, and/or the integrated circuit itself. Further, as noted above, in alternate embodiments, the arrangement of the first dummy component102and second dummy component104may be reversed, where the first dummy component102(comprising the first transmission line106of length 2L) may be coupled with the DUT200and then further coupled with the second dummy component104(comprising the second transmission line108of length L). In addition, thoughFIG. 2shows the test structure100coupled with the DUT200in one location, in alternate embodiments, the test structure100may be coupled at multiple locations to the DUT200. Also, in the present embodiment, only one test structure100couples with the DUT200; however, in alternate embodiments, multiple test structures100may be coupled with the DUT200.

The test structure100couples with the DUT200in order to determine the intrinsic characteristics of the DUT200. In the present embodiment, during testing, the DUT200is coupled with the first dummy component102and the second dummy component104, which are further connected to external testing equipment. Though the measured physical/electrical properties should accurately represent those of the DUT200alone, the test structure100contributes physical/electrical characteristics, known as “parasitics” (e.g., resistance, capacitance, and inductance from the transmission lines and test pads), that ultimately contribute to the measured characteristics of the DUT. In the present embodiment, the first and second transmission lines106,108and signal test pads112of the first and second dummy components102,104contribute parasitics to the measured characteristics of the DUT200. In alternate embodiments, the ground test pads110and connecting lines114may also contribute parasitics to the overall measured physical/electrical characteristics of the DUT200.

FIG. 3provides a simple block diagram reflecting each portion that contributes physical/electrical characteristics to the measured characteristics of the DUT200. Block300represents the measured characteristics of the DUT200. The external measurements from the DUT200may include parasitics from the signal test pads112, the first transmission line106, and the second transmission line108, and physical/electrical characteristics of the DUT200. InFIG. 3, block302represents the parasitics contributed by the test pads112; block304represents the parasitics contributed by the transmission lines106,108; and block306represents the intrinsic characteristics of the DUT200. In alternate embodiments, block302may include parasitics contributed by test pads110, and/or block304may include parasitics contributed by connecting lines114. To obtain the intrinsic characteristics of the DUT200alone, the characteristics of block306alone, the contributions from blocks302and304must be factored out or extracted (i.e., de-embedded) from the measured characteristics of the DUT (block300). In other words, the parasitics from the signal test pads112, the first transmission line106, and the second transmission line108must be de-embedded. It is understood that in alternate embodiments the parasitics from the ground test pads110and connecting lines114may also contribute to the measured electrical characteristics of the DUT200and may need to be de-embedded.

FIG. 4Ais a flow diagram of one embodiment of a de-embedding process for accurately obtaining the intrinsic characteristics of the DUT200alone. In operation, the test structure100utilizes the method400to determine the intrinsic characteristics of the DUT200alone by de-embedding the parasitics (i.e., the resistance, capacitance, inductance, etc. arising from the test pads110,112and transmission lines106,108).

Referring toFIGS. 1-4B, the method400begins with step402, which involves coupling the test structure100, comprising at least two dummy components102,104, at least two transmission lines106,108, and at least one test pad110,112, to the DUT200. Once the test structure100is coupled with the DUT200, the characteristics of the DUT200are measured. As noted above, parasitics from the test structure100contribute to the measured characteristics of the DUT200. Accordingly, such parasitics contributed by the test structure100must be determined and extracted to obtain an accurate measurement for the intrinsic characteristics of the DUT200.

In step404, the intrinsic characteristics of the test structure are represented and decomposed into ABCD matrix components, which requires decomposing the parasitics contributed by the first dummy component102and second dummy component104into ABCD matrix components. The parasitics of the first dummy component102, which comprises the first transmission line106of length 2L, may be represented by [2L]. The parasitics of the second dummy component104, which comprises the second transmission line108of length L, may be represented by [L]. In alternate embodiments, the first dummy component102may comprise a transmission line of length L and be represented by [L], and the second dummy component104may comprise a transmission line of length 2L and be represented by [2L].

With reference toFIG. 4B, the test structure100is divided into separate portions that contribute to the overall parasitics arising from the first and second dummy components102,104. As noted above, the intrinsic characteristics of the test structure100arise from the signal test pads112, the first transmission line106, and the second transmission line108, which must be factored out or extracted (i.e., de-embedded). In the present embodiment, the parasitics contributed by a single test pad are represented by the matrix [PAD], and the parasitics contributed by a transmission line of length L are represented by the matrix [TLine]. In alternate embodiments, [PAD] may represent parasitics contributed by multiple test pads, and [TLine] may represent parasitics contributed by multiple transmission lines of length L or a transmission line of a length other than L.

In the present embodiment, the parasitics contributed from the first and second dummy components102,104arise from the first and second transmission lines106,108and the signal test pads112. So, with reference toFIG. 4B, the parasitics resulting from the second dummy component104, [L], comprise the parasitics of the first signal test pad112([PAD]), the second transmission line108of length L ([TLine]), and the second signal test pad112([PAD]); and the parasitics resulting from the first dummy component102, [2L], comprise the parasitics of the first signal test pad112([PAD]), the first transmission line106of length 2L ([TLine][TLine]), and the second signal test pad112([PAD]). It is understood that, in alternate embodiments, parasitics may arise from the ground test pads110and connecting lines114and may similarly be represented by matrices [PAD] or [TLine]. Thus, when the first and second dummy components102,104are decomposed into ABCD matrix components, the following formulas represent the contributed parasitics:
[L]=[PAD][TLine][PAD]; and  (1)
[2L]=[PAD][TLine][TLine][PAD],  (2)
where [PAD] is a matrix in ABCD matrix components representing the parasitics contributed by one test pad and [TLine] is a matrix in ABCD matrix components representing the parasitics contributed by a transmission line of length L.

In step406, the intrinsic characteristics of the test structure, the parasitics, are determined. By manipulating equations (1) and (2) above, [PAD] and [TLine] may be solved for and represented by the following equations:
[PAD][PAD]=[[L]−1[2L][L]−1]−1(3)
[TLine]=[PAD]−1[L][PAD]−1(4)
From equation (3), [PAD] is easily calculated by plugging in measurable data. Then, [TLine] is determined. When equations (3) and (4) are solved, all parasitics of the test structure100contributing to the measured characteristics of the DUT200(measured in step402) are known.

In step408, the intrinsic characteristics of the DUT are determined. This may be accomplished by factoring out or extracting the intrinsic characteristics of the test structure100, determined in step406, from the measured characteristics of the DUT200that were determined in step402. For example, with reference toFIG. 3, blocks302and304, the parasitics contributed by the test pads and transmission lines of the test structure100, are extracted from block300, the measured characteristics of the DUT200, to obtain block306, the intrinsic characteristics of the DUT200alone.

Overall, the disclosed embodiments provide one or more of the following advantages: (1) in the preferred embodiment, only two transmission lines are required; (2) ABCD matrix components effectively solve all parasitics (e.g., resistance, inductance, and capacitance); (3) the layout size required by test structures is minimized (in the preferred embodiment, the test structure comprises only two dummy components); (4) model fitting to obtain the parasitics (or de-embedding parameters) is no longer required; (5) unlike the open-thru, open-short, and TRL de-embedding methods, an approximate open pad is not required for de-embedding purposes; (6) the proposed method is easy to use and the de-embedding results are essentially displayed right after experimental measurements are taken; and (7) the proposed method and system provides very good de-embedding accuracy, specifically when de-embedding parasitics contributed by test pads and transmission lines of a test structure.

In summary, a method and system are provided for de-embedding an on-wafer device. This method and system effectively determines the parasitics contributed by a test structure to measured characteristics of a DUT. Ultimately, this results in improved accuracy in determining intrinsic characteristics of a DUT.

In one embodiment, a wafer comprises at least one die comprising a plurality of devices; and at least one test structure for de-embedding at least one of the plurality of devices, wherein the at least one test structure further comprises: a first dummy component comprising a first transmission line; a second dummy component comprising a second transmission line, wherein the second dummy component is coupled with the first dummy component; and at least one test pad electrically connected to the first transmission line and at least one test pad electrically connected to the second transmission line. In some embodiments, the first dummy component and the second dummy component each further comprise at least one connecting line and at least one test pad electrically connected to the at least one connecting line.

In some embodiments, the second dummy component coupled with the first dummy component is further coupled with a device-under-test (DUT). In some embodiments, the first transmission line has length 2L and the second transmission line has length L; and/or the first transmission line and the second transmission line are the same width. In some embodiments, the first transmission line and the second transmission line are on the same substrate. And, in some embodiments, the first transmission line and the second transmission line comprise conducting material.

In some embodiments, the at least one test pad electrically connected to the first transmission line comprises two signal test pads electrically connected to the first transmission line; and/or the at least one test pad electrically connected to the second transmission line comprises two signal test pads electrically connected to the second transmission line. In some embodiments, the at least one test pad electrically connected to the at least one connecting line comprises two ground test pads electrically connected to the at least one connecting line.

In one embodiment, a method for de-embedding an on-wafer device comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

In some embodiments, representing the intrinsic characteristics of a test structure comprises representing intrinsic characteristics of a first dummy component and a second dummy component in ABCD matrix components, wherein the first dummy component and the second dummy component each comprise at least one test pad and at least one transmission line.

In some embodiments, determining the intrinsic characteristics arising from the test structure comprises determining the intrinsic characteristics arising from the at least one test pad of the first dummy component and the second dummy component; and determining the intrinsic characteristics arising from the at least one transmission line of the first dummy component and the second dummy component.

In some embodiments, determining the intrinsic characteristics arising from the at least one test pad comprises representing the intrinsic characteristics of the at least one test pad by matrix [PAD] in ABCD matrix components; and/or determining the intrinsic characteristics arising from the at least one transmission line comprises representing the intrinsic characteristics of the at least one transmission line by matrix [TLine] in ABCD matrix components, wherein [TLine] represents the intrinsic characteristics of a transmission line comprising length L.

In some embodiments, representing the intrinsic characteristics of the first dummy component and the second dummy component in ABCD matrix components comprises representing the intrinsic characteristics of the first dummy component by matrix [2L], wherein [2L]=[PAD][TLine][TLine][PAD] and the at least one transmission line of the first dummy component is two times longer than the at least one transmission line of the second dummy component; and representing the intrinsic characteristics of the second dummy component by matrix [L], wherein [L]=[PAD][TLine][PAD] and the at least one transmission line of the second dummy component comprises length L.

In some embodiments, determining the intrinsic characteristics arising from the at least one test pad further comprises manipulating matrices [2L] and [L], wherein [PAD][PAD]=[[L]−1[2L][L]−1]−1; and/or determining the intrinsic characteristics arising from the at least one transmission line further comprises manipulating matrices [2L] and [L], wherein [TLine]=[PAD]−1[L][PAD]−1.

In some embodiments, using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”) comprises factoring out the determined intrinsic characteristics arising from the at least one test pad and the at least one transmission line of the first dummy component and the second dummy component from measured characteristics of the DUT.

In yet another embodiment, a test structure for de-embedding an on-wafer device comprises a first dummy component, wherein the first dummy component comprises a first transmission line of length L; a second dummy component coupled with the first dummy component, wherein the second dummy component comprises a second transmission line of length 2L; and a device-under-test coupled with the first dummy component and/or the second dummy component.