IMAGING DEVICE

An imaging device includes a pixel region and a first peripheral region. The pixel region includes a pixel substrate portion and a pixel transistor located in the pixel substrate portion. The first peripheral region includes a first peripheral substrate portion and at least one first peripheral transistor located in the first peripheral substrate portion. Signals are transmitted between the first peripheral region and the pixel region. A gate length of the at least one first peripheral transistor is less than a gate length of the pixel transistor. The at least one first peripheral transistor further includes, in the first peripheral substrate portion, a first source, a first drain, a first channel region located between the first source and the first drain, and a first strain-introducing layer that brings a strain to the first channel region.

BACKGROUND

1. Technical Field

The present disclosure relates to an imaging device.

2. Description of the Related Art

Image sensors are used in digital cameras or other devices. Examples of image sensors include CCD (charge-coupled device) image sensors and CMOS (complementary metal-oxide semiconductor) image sensors.

An image sensor according to one example has a photodiode provided in a semiconductor substrate. An image sensor according to another example has a photoelectric conversion layer provided above a semiconductor substrate.

An imaging device according to one specific example produces signal charge through photoelectric conversion. The signal charge thus produced is accumulated in a charge accumulation node. A signal corresponding to the amount of charge accumulated in the charge accumulation node is read out via a CCD or CMOS circuit formed in a semiconductor substrate.

International Publication No. 2021/152943 discloses an imaging device. The imaging device of International Publication No. 2021/152943 includes a pixel region and a peripheral region. Japanese Patent No. 5235486, Japanese Patent No. 3426573, and U.S. Pat. No. 7,141,477 describe examples of transistors.

SUMMARY

In one general aspect, the techniques disclosed here feature an imaging device including a pixel region and a first peripheral region. The pixel region includes a pixel substrate portion and a pixel transistor located in the pixel substrate portion. The first peripheral region includes a first peripheral substrate portion and at least one first peripheral transistor located in the first peripheral substrate portion. Signals are transmitted between the first peripheral region and the pixel region. The pixel transistor and the at least one first peripheral transistor each include a gate. A gate length of the at least one first peripheral transistor is less than a gate length of the pixel transistor. The at least one first peripheral transistor further includes, in the first peripheral substrate portion, a first source, a first drain, a first channel region located between the first source and the first drain, and a first strain-introducing layer that brings a strain to the first channel region.

DETAILED DESCRIPTIONS

Brief Overview of an Aspect According to the Present Disclosure

An imaging device according to a first aspect of the present disclosure includes a pixel region and a first peripheral region. The pixel region includes a pixel substrate portion and a pixel transistor located in the pixel substrate portion. The first peripheral region includes a first peripheral substrate portion and at least one first peripheral transistor located in the first peripheral substrate portion.

Signals are transmitted between the first peripheral region and the pixel region.

The pixel transistor and the at least one first peripheral transistor each include a gate.

A gate length of the at least one first peripheral transistor is less than a gate length of the pixel transistor.

The at least one first peripheral transistor further includes, in the first peripheral substrate portion, a first source, a first drain, a first channel region located between the first source and the first drain, and a first strain-introducing layer that brings a strain to the first channel region. Carriers may migrate through the first channel region.

The technique according to the first aspect is suitable to improving the performance of an imaging device.

In a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, the first strain-introducing layer may be a single-crystal layer.

The technique according to the second aspect is suitable to improving the performance of an imaging device.

In a third aspect of the present disclosure, for example, in the imaging device according to the first or second aspect, the first strain-introducing layer may be an epitaxial layer.

The technique according to the third aspect is suitable to improving the performance of an imaging device.

In a fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects, the first strain-introducing layer may be a crystal layer of silicon germanium, germanium, a Group III-V compound, silicon carbide, transition metal dichalcogenide, or carbon nanotubes.

The crystal layer of silicon germanium, germanium, a Group III-V compound, silicon carbide, transition metal dichalcogenide, or carbon nanotubes may bring a strain to the first channel region.

In a fifth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fourth aspects,the first strain-introducing layer may be a crystal layer of Si1-xGex, andX may be greater than 0 and less than 1.

The technique according to the fifth aspect is suitable to improving the performance of an imaging device.

In a sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifth aspects,the first strain-introducing layer may be a crystal layer of Si1-xGex, andX may be greater than or equal to 0.1 and less than or equal to 0.8.

The technique according to the sixth aspect is suitable to improving the performance of an imaging device.

In a seventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to sixth aspects,the first peripheral substrate portion may include a first foundation layer that is adjacent to the first strain-introducing layer, anda lattice constant of a crystal lattice of the first strain-introducing layer may be different from a lattice constant of a crystal lattice of the first foundation layer.

The technique according to the seventh aspect is suitable to improving the performance of an imaging device.

In an eighth aspect of the present disclosure, for example, in the imaging device according to the seventh aspect, the first foundation layer may be a single-crystal layer of silicon.

The technique according to the eighth aspect is suitable to improving the performance of an imaging device.

In a ninth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eighth aspects,the first peripheral substrate portion may include a supporting substrate,the at least one first peripheral transistor may include a first cap layer in the first peripheral substrate portion,the supporting substrate, the first strain-introducing layer, and the first cap layer may be arranged in an order from lower to upper parts of the imaging device,the first cap layer may include an upper surface of the first peripheral substrate portion, anda concentration of a conductive impurity of the first cap layer may be less than a concentration of a conductive impurity of the supporting substrate.

The technique according to the ninth aspect is suitable to improving the performance of an imaging device.

In a tenth aspect of the present disclosure, for example, in the imaging device according to the ninth aspect, the first cap layer may be a non-doped epitaxial layer.

The technique according to the tenth aspect is suitable to improving the performance of an imaging device.

In an eleventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to tenth aspects, the first channel region may include the first strain-introducing layer.

The configuration of the eleventh aspect is an example of a configuration of the imaging device.

In a twelfth aspect of the present disclosure, for example, in the imaging device according to any one of the first to eleventh aspects,the first source may include the first strain-introducing layer, andthe first drain may include the first strain-introducing layer.

The configuration of the twelfth aspect is an example of a configuration of the imaging device.

In a thirteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twelfth aspects,the pixel transistor may further include a pixel gate insulator film,the at least one first peripheral transistor may further include a first peripheral gate insulator film, andthe first peripheral gate insulator film may be thinner than the pixel gate insulator film.

The configuration of the thirteenth aspect is an example of a configuration of the imaging device.

In a fourteenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to thirteenth aspects,when at least one type of impurity that suppresses transient enhanced diffusion of a conductive impurity is defined as a diffusion-suppressing species, the at least one first peripheral transistor may further include a first specific layer that is located in the first peripheral substrate portion and that contains the diffusion-suppressing species, andthe diffusion-suppressing species may contain at least one selected from the group consisting of carbon, nitrogen, and fluorine.

The technique according to the fourteenth aspect is suitable to improving the performance of an imaging device.

In a fifteenth aspect of the present disclosure, for example, in the imaging device according to the fourteenth aspect,the first channel region may include the first strain-introducing layer,the at least one first peripheral transistor may further include a first pocket diffusion layer,the first pocket diffusion layer may be adjacent to the first source or the first drain, andthe first specific layer may be included in at least one selected from the group consisting of (a) the first pocket diffusion layer and (b) a region between the first pocket diffusion layer and the first strain-introducing layer.

In other words, in the imaging device according to the fourteenth aspect, at least one selected from the group consisting of the following (a) and (b) may hold:(a) the first pocket diffusion layer may include the first specific layer; and(b) a region between the first pocket diffusion layer and the first strain-introducing layer may include the first specific layer.

The technique according to the fifteenth aspect is suitable to improving the performance of an imaging device.

In a sixteenth aspect of the present disclosure, for example, in the imaging device according to the fourteenth or fifteenth aspect,at least one selected from the group consisting of the first source and the first drain may include the first strain-introducing layer,the first peripheral substrate portion may include a first foundation layer,a conductive impurity in the at least one selected from the group consisting of the first source and the first drain may spread in a first region of the first foundation layer astride an interface between the first foundation layer and the first strain-introducing layer included in the at least one selected from the group consisting of the first source and the first drain, andthe first region may include the first specific layer.

In other words, in the imaging device according to the fourteenth or fifteenth aspect,the first source may include the first strain-introducing layer,the first drain may include the first strain-introducing layer,the first peripheral substrate portion may have a first foundation layer, andat least one selected from among the following (c) and (d) may hold:(c) there may be a first interface between the first foundation layer and the first strain-introducing layer included in the first source,a conductive impurity of the first source may spread in a first predetermined region of the first foundation layer astride the first interface, andthe first predetermined region may include the first specific layer; and(d) there may be a second interface between the first foundation layer and the first strain-introducing layer included in the first drain, anda conductive impurity of the first drain may spread in a second predetermined region of the first foundation layer astride the second interface.

The technique according to the sixteenth aspect is suitable to improving the performance of an imaging device.

In a seventeenth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to sixteenth aspects,when at least one type of impurity that induces amorphization of a region into which the at least one type of impurity has been implanted is defined as an amorphizing species, the first specific layer may contain the amorphizing species, andthe amorphizing species may contain at least one selected from the group consisting of germanium, silicon, and argon.

The amorphizing species may be a trace of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by a diffusion-suppressing species.

In an eighteenth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to seventeenth aspects,the pixel region may further include a charge accumulation region in which a charge generated by photoelectric conversion is accumulated and that is an impurity region, anda concentration of carbon in the first specific layer may be greater than a concentration of carbon in the charge accumulation region.

Only a high-performance imaging device can have the feature of the eighteenth aspect.

In a nineteenth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to eighteenth aspects,the pixel transistor may further include a source, a drain, and a channel region located between the source and the drain,carriers may migrate through the channel region, anda concentration of carbon in the first specific layer may be greater than a concentration of carbon in the channel region of the pixel transistor.

Only a high-performance imaging device can have the feature of the nineteenth aspect.

In a twentieth aspect of the present disclosure, for example, in the imaging device according to any one of the first to nineteenth aspects,when at least one type of impurity that suppresses transient enhanced diffusion of a conductive impurity is defined as a diffusion-suppressing species, the at least one first peripheral transistor may further include a first specific layer that is located in the first peripheral substrate portion and that contains the diffusion-suppressing species,the at least one first peripheral transistor may comprise two first peripheral transistors,the first peripheral region may further include a shallow trench isolation structure,the shallow trench isolation structure may provide device isolation of the two first peripheral transistors from each other,the shallow trench isolation structure may include a trench, anda range of distribution of the diffusion-suppressing species in the first specific layer of at least either of the two first peripheral transistors may be shallower than a bottom of the trench.

The configuration of the twentieth aspect is an example of a configuration of the imaging device.

In a twenty-first aspect of the present disclosure, for example, the imaging device according to any one of the first to twentieth aspects may further comprise a second peripheral region including a second peripheral substrate portion and a second peripheral transistor located in the second peripheral substrate portion,the signals may be transmitted between the first peripheral region and the pixel region via the second peripheral region,the second peripheral transistor may include a gate,the gate length of the at least one first peripheral transistor may be less than a gate length of the second peripheral transistor,the gate length of the pixel transistor may be greater than the gate length of the second peripheral transistor, andthe second peripheral transistor may further include, in the second peripheral substrate portion, a second source, a second drain, a second channel region located between the second source and the second drain, and a second strain-introducing layer that brings a strain to the second channel region, andcarriers may migrate through the second channel region.

The technique according to the twenty-first aspect is suitable to improving the performance of an imaging device.

In a twenty-second aspect of the present disclosure, for example, in the imaging device according to the twenty-first aspect,the second peripheral substrate portion may include a second foundation layer that is adjacent to the second strain-introducing layer, anda lattice constant of a crystal lattice of the second strain-introducing layer may be different from a lattice constant of a crystal lattice of the second foundation layer.

The technique according to the twenty-second aspect is suitable to improving the performance of an imaging device.

In a twenty-third aspect of the present disclosure, for example, in the imaging device according to the twenty-first or twenty-second aspect, at least one selected from the group consisting of the second channel region, the second source, and the second drain may include the second strain-introducing layer.

The configuration of the twenty-third aspect is an example of a configuration of the imaging device.

In a twenty-fourth aspect of the present disclosure, for example, in the imaging device according to any one of the twenty-first to twenty-third aspects,the pixel transistor may further include a pixel gate insulator film,the at least one first peripheral transistor may further include a first peripheral gate insulator film,the second peripheral transistor may further include a second peripheral gate insulator film,the first peripheral gate insulator film may be thinner than the second peripheral gate insulator film, andthe pixel gate insulator film may be thicker than the second peripheral gate insulator film.

The configuration of the twenty-fourth aspect is an example of a configuration of the imaging device.

In a twenty-fifth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twenty-fourth aspects,the first peripheral region may be located outside the pixel region, andthe pixel substrate portion and the first peripheral substrate portion may be included in a single semiconductor substrate.

The configuration of the twenty-fifth aspect is an example of a configuration of the imaging device.

In a twenty-sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to twenty-fourth aspects, the pixel substrate portion and the first peripheral substrate portion may be stacked on top of each other.

The configuration of the twenty-sixth aspect is an example of a configuration of the imaging device.

The techniques of the first to twenty-sixth aspects may be combined as appropriate, provided no contradictory arises.

The following describes embodiments of the present disclosure in detail with reference to the drawings. It should be noted that the embodiments to be described below each illustrate a comprehensive and specific example. The numerical values, shapes, materials, constituent elements, placement and topology of constituent elements, steps, orders of steps, or other features that are shown in the following embodiments are just a few examples and are not intended to limit the present disclosure. The various aspects described herein may be combined with each other, provided no contradiction arises. Further, those of the constituent elements in the following embodiments which are not recited in an independent claim reciting the most superordinate concept are described as optional constituent elements.

In the following description, constituent elements having substantially the same functions are denoted by common reference signs, and a description of such constituent elements may be omitted. Further, for the avoidance of an overly complex drawing, an illustration of some elements may be omitted. Regarding various elements of an imaging device, dimensions, outward appearances, or other features depicted in the drawings may be different from the dimensions and outward appearances of an actual imaging device. That is, the accompanying drawings are only schematic views for understanding of the present disclosure and do not necessarily rigorously reflect the scale or other features of an actual imaging device.

The term “plan view” herein means a view as seen from a direction perpendicular to a first semiconductor substrate, a second semiconductor substrate, a third semiconductor substrate, a pixel substrate portion, a first peripheral substrate portion, or a second peripheral substrate portion. Terms such as “above”, “below”, “top”, and “bottom” herein are used to designate the mutual arrangement of members, and are not used to limit the attitude of the imaging device during use.

The expression “substrate”, as in “supporting substrate”, “semiconductor substrate”, or the like, is sometimes used herein. The substrate is not limited to a particular structure or manufacturing method. The substrate may have a single-layer structure or may have a stacked structure. The stacked structure may include, for example, a semiconductor layer, an insulating layer, or other layers. The substrate may be a wafer obtained by slicing an ingot, may be a film deposited by sputtering or other processes, or may be a film grown by epitaxial growth. The substrate may be a plate-like body that is used in a chip stack structure. Further, the substrate may be a plate-like body that is used in a stacked structure that is manufactured by a three-dimensional stacking technology 3DSI (3D Sequential Integration) so called Sequential 3D. The term “direction parallel with the depth of a substrate” can be read as “direction parallel with the thickness of a substrate”.

The term “carrier mobility” herein means an index that represents the ease with which charged carriers migrate. The carrier mobility μ is given by μ=v/E, where E is an electric field that is applied to carriers and v is a component of the average velocity of the carriers in the direction of this electric field. The carriers are electrons or holes.

The term “single crystal” herein means a crystal all portions of which have a common crystal axis.

The term “epitaxial layer” herein means a layer formed by epitaxial growth.

Expressions such as “crystal layer of silicon germanium”, “crystal layer of germanium”, “crystal layer of a Group III-V compound”, “crystal layer of silicon carbide”, “crystal layer of transition metal dichalcogenide”, “crystal layer of carbon nanotubes, and “a single crystal layer of silicon” may be used herein. A crystal layer of silicon germanium is a crystal layer in which silicon germanium accounts for 90 wt % or more of the material total mass. The same applies to the crystal layer of germanium, the crystal layer of a Group III-V element, the crystal layer of silicon carbide, the crystal layer of transition metal dichalcogenide, the crystal layer of carbon nanotubes, the single crystal layer of silicon, or other crystal layers.

The expression “crystal layer of Si1-xGex” may be used herein. The crystal layer of Si1-xGexis a crystal layer in which silicon germanium accounts for 90 wt % or more of the material total mass and the molar ratio of silicon to germanium in silicon germanium is 1−X:X.

A threshold voltage of a transistor herein refers to a gate-source voltage of the transistor at which a drain current starts to flow through the transistor.

There is herein an expression “the gate length of a peripheral transistor is shorter than the gate length of a pixel transistor”. This expression may be supplemented with “at least one”, as in “the gate length of at least one peripheral transistor is shorter than the gate length of at least one pixel transistor”. In the expression thus supplemented, all peripheral transistors and pixel transistors that are present in an imaging device satisfy this magnitude relationship. The same applies to an expression regarding a magnitude relationship between the sizes of other elements. The same also applies to a magnitude relationship between the concentrations of impurities such as carbon. The same also applies to a magnitude relationship between an element of a first peripheral transistor and a second peripheral transistor.

There is herein an expression “conductive impurity”. The conductive impurity is an impurity having a conductivity type. That is, the conductive impurity is a p-type or n-type impurity. The conductive impurity may be a p-type impurity. Examples of p-type impurities include boron (B), gallium (Ga), and indium (In). Further, the conductive impurity may be an n-type impurity. Examples of n-type impurities include phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

There is herein an expression “concentration of a conductive impurity”. In a case where the conductive impurity is constituted by plural types of impurity, the concentration of the conductive impurity refers to the total concentration of those plural types of impurity. In this respect, the same applies to the concentration of a diffusion-suppressing species, an amorphizing species, or other species.

There are herein expressions “first conductivity type” and “second conductivity”. A conductive impurity of the first conductivity type is an n-type impurity or a p-type impurity. A conductive impurity of the second conductivity type is an impurity that is opposite in conductivity type to the conductive impurity of the first conductivity type. The conductive impurity of the second conductivity type is a p-type impurity or an n-type impurity. A transistor of the first conductivity type is an N-channel transistor or a P-channel transistor. A transistor of the second conductivity type is a transistor that is opposite in conductivity type to the transistor of the first conductivity type. The transistor of the second conductivity type is a P-channel transistor or an N-channel transistor.

The expression “an element A includes an element B” may be used herein. This expression is an expression intended to encompass an aspect in which the element A includes part of the element B and an aspect in which the element A includes all of the element B.

As in the case of an analog processor, a digital processor, or other processors, the expression “processor” may be used herein. The processor may be a processing circuit.

The following describes Embodiment 1 of the present disclosure with reference toFIGS.1to33.

FIG.1schematically shows an exemplary configuration of an imaging device100A according to Embodiment 1 of the present disclosure. The imaging device100A shown inFIG.1has a plurality of pixels110arrayed, for example, in a plurality of rows and columns. In the configuration illustrated inFIG.1, the pixels110are arrayed in m rows and n columns and form a pixel region R1having a substantially rectangular shape. Note here that m and n each independently represent an integer greater than or equal to 1.

In Embodiment 1, each of the plurality of pixels110has a photoelectric converter and a readout circuit. The photoelectric converter is supported by a semiconductor substrate130. The readout circuit is formed in the semiconductor substrate130and electrically connected to the photoelectric converter. Each of the plurality of pixels110includes an impurity region, provided in the semiconductor substrate130, that functions as part of a charge accumulation region that temporarily retains signal charge generated by the photoelectric converter. It is possible to, instead of providing such a photoelectric converter, provide a photodiode as a photoelectric converter in the semiconductor substrate.

The imaging device100A further has a peripheral circuit120A. The peripheral circuit120A drives the plurality of pixels110. In the example shown inFIG.1, the peripheral circuit120A includes a vertical scanning circuit122, a horizontal signal readout circuit124, a voltage supply circuit126, and a control circuit128. In Embodiment 1, some or all of these circuits are formed in the semiconductor substrate130as is the case with the readout circuit of each pixel. As schematically shown inFIG.1, the peripheral circuit120A is located in a first peripheral region R2of the semiconductor substrate130. The first peripheral region R2is located outside a pixel region R1including the plurality of pixels110.

The imaging device100A further has a blocking region200A. The blocking region200A is provided between the pixel region R1and the first peripheral region R2. As schematically shown inFIG.1, the blocking region200A includes an impurity region131and a plurality of contact plugs211. The impurity region131is provided in the semiconductor substrate130. The plurality of contact plugs211are provided over the impurity region131. The impurity region131is typically a P-type diffusion region.

By being provided over the impurity region131, the plurality of contact plugs211are electrically connected to the impurity region131. As will be mentioned later, by being connected to a power source (not illustrated inFIG.1), the plurality of contact plugs211are configured such that a predetermined voltage can be supplied to the impurity region131. That is, during operation of the imaging device100A, the impurity region131is in a state in which a predetermined voltage is applied to the impurity region131via the contact plugs211.

Further, the blocking region200A has a device isolation220. The device isolation220is a structure formed in the semiconductor substrate130, for example, by a STI (shallow trench isolation) process. The device isolation220has a portion of the semiconductor substrate130located at least between ones of the plurality of pixels110located on the outermost periphery of the pixel region R1and a digital circuit, such as the vertical scanning circuit122, that operates in accordance with a digital clock. In this example, the device isolation220is located between pixels110located on the outermost periphery of the pixel region R1and the vertical scanning circuit122and between pixels110located on the outermost periphery of the pixel region R1and the horizontal signal readout circuit124. A will be mentioned later, the device isolation220may be provided in the semiconductor substrate130so as to surround the pixel region R1in a top view. The device isolation220is equivalent to the shallow trench isolation structure in the present disclosure.

In a configuration in which a peripheral circuit including a circuit that operates in accordance with a digital clock is formed in a semiconductor substrate provided with an impurity region that temporarily retains signal charge that is obtained by photoelectric conversion, the circuit that operates on a digital clock may become a noise source that generates noise every time an input pulse rises and falls. More specifically, the potential of a signal line through which a digital clock is supplied to a digital circuit typified by a CMOS logic circuit fluctuates according to the digital clock. The fluctuations in potential of the signal line due to the digital clock may become a factor for causing fluctuations in substrate potential and, as a result, generating excess charge in a well inside the semiconductor substrate. If the excess charge attributed to the fluctuations in substrate potential flows into an impurity region in a pixel that retains signal charge, there will be a decline in S/N ratio, causing a deterioration in a resulting image.

On the other hand, in the imaging device100A shown inFIG.1, the blocking region200A, which includes the impurity region131configured to be connectable to a power source such as a ground by being provided with the plurality of contact plugs211, is disposed between the pixel region R1, which includes the plurality of pixels110, and a digital circuit. During operation of the imaging device100A, the potential of the impurity region131of the blocking region200A can be fixed by connecting a predetermined voltage source to the plurality of contact plugs211. For example, the potential of the impurity region131of the blocking region200A may be grounded via the plurality of contact plugs211. At this point in time, the blocking region200A functions as a low-impedance path through which excess charge generated inside the semiconductor substrate130is discharged. That is, electrostatic coupling between an impurity region in a pixel that retains signal charge and the peripheral circuit120A can be suppressed. This makes it possible to advantageously reduce dark current whose noise source is a signal line through which a digital clock is supplied. Note, however, that the blocking region200A is not essential.

Details of the circuits constituting the peripheral circuit120A are given here. The vertical scanning circuit122has connections with a plurality of address signal lines34. These address signal lines34are provided separately in correspondence with each of the rows of pixels110. Each address signal line34is connected to one or more pixels110belonging to the corresponding row. The vertical scanning circuit122controls the timing of readout of signals from the pixels110to the after-mentioned vertical signal lines35by applying row selecting signals to the address signal lines34. The vertical scanning circuit122is also called “row scanning circuit”. It should be noted that the address signal lines34are not the only signal lines that are connected to the vertical scanning circuit122. Plural types of signal line may be connected to the vertical scanning circuit122for each row of pixels110.

As schematically shown inFIG.1, the imaging device100A also has a plurality of vertical signal lines35. The vertical signal lines35are provided separately for each of the columns of pixels110. Each vertical signal line35is connected to one or more pixels110belonging to the corresponding column. These vertical signal lines35are connected to the horizontal signal readout circuit124. The horizontal signal readout circuit124sequentially output signals read out from the pixels110to output lines (not illustrated inFIG.1). The horizontal signal readout circuit124is also called “column scanning circuit”.

The control circuit128exercises overall control of the imaging device100A upon receiving command data, clocks, or other signals that are supplied, for example, from outside the imaging device100A. The control circuit128typically has a timing generator and supplies driving signals to the vertical scanning circuit122, the horizontal signal readout circuit124, the after-mentioned voltage supply circuit126, or other circuits. InFIG.1, arrows extending from the control circuit128schematically express the flow of output signals from the control circuit128. The control circuit128may be implemented, for example, by a microcontroller including one or more processors. The functions of the control circuit128may be implemented by a combination of a general-purpose circuit and software, or may be implemented by hardware specialized in such processing.

In Embodiment 1, the peripheral circuit120A includes the voltage supply circuit126, which is electrically connected to each pixel110in the pixel region R1. The voltage supply circuit126supplies a predetermined voltage to a pixel110via a voltage line38. The voltage supply circuit126is not limited to a particular power-supply circuit. The voltage supply circuit126may be a circuit that converts a voltage supplied from a power source such as a battery into a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit126may be part of the aforementioned vertical scanning circuit122. As schematically shown inFIG.1, these circuits constituting the peripheral circuit120A are disposed in the first peripheral region R2outside the pixel region R1.

It should be noted that the number and placement of the pixels110are not limited to the illustrated example. For example, the number of pixels110that are included in the imaging device100A may be 1. Although, in this example, the center of each pixel110is located at a lattice point of a tetragonal lattice, the plurality of pixels110may be placed so that the center of each pixel110is located at a lattice point of a triangular lattice, a hexagonal lattice, or other lattices. For example, the pixels110may be arrayed one-dimensionally, and in this case, the imaging device100A may be utilized as a line sensor.

FIG.2is a diagram schematically showing an exemplary circuit configuration of the imaging device100A shown inFIG.1. For the avoidance of an overly complex drawing,FIG.2illustrates only four of the plurality of pixels110arrayed in two rows and two columns. Each of these pixels110includes a photoelectric converter10supported by the semiconductor substrate130and a readout circuit20electrically connected to the photoelectric converter10. As will be described in detail later with reference to the drawings, the photoelectric converter10includes a photoelectric conversion layer disposed above the semiconductor substrate130. The photoelectric converter10may also be referred to as “photoelectric conversion structure”.

By having a connection with the voltage line38, which is connected to the voltage supply circuit126, the photoelectric converter10of each pixel110is configured such that a predetermined voltage can be applied via the voltage line38during operation of the imaging device100A. For example, in a case where of positive and negative charge generated by photoelectric conversion, the positive charge is utilized as signal charge, a positive voltage of, for example, approximately 10 V may be applied to the voltage line38during operation of the imaging device100A. The following illustrates a case where a hole is utilized as signal charge.

In the configuration illustrated inFIG.2, the readout circuit20includes an amplifying transistor22, an address transistor24, and a reset transistor26. The amplifying transistor22, the address transistor24, and the reset transistor26are typically field-effect transistors formed in the semiconductor substrate130. Unless otherwise noted, the following describes an example involving the use of N-channel MOSFETs (metal-oxide semiconductor field-effect transistors) as the transistors.

As schematically shown inFIG.2, the amplifying transistor22has its gate electrically connected to the photoelectric converter10. A hole can for example be accumulated as signal charge in a charge accumulation node FD by applying a predetermined voltage to the photoelectric converter10of each pixel110from the voltage supply circuit126via the voltage line38during operation. Note here that the charge accumulation node FD is a node at which the gate of the amplifying transistor22is connected to the photoelectric converter10. The charge accumulation node FD has a function of temporarily retaining charge generated by the photoelectric converter10. The charge accumulation node FD includes as part thereof an impurity region formed in the semiconductor substrate130. A charge accumulation region Z ofFIG.3, which will be described later, corresponds to the impurity region included in the charge accumulation node FD.

As shown inFIG.2, the amplifying transistor22of each pixel110has its drain connected to a power-supply wire32. The power-supply wire32supplies a power-supply voltage VDD to the amplifying transistor22during operation of the imaging device100A. The power-supply voltage VDD is for example approximately 3.3 V. On the other hand, the amplifying transistor22has its source connected to a vertical signal line35via the address transistor24. By having its drain supplied with the power-supply voltage VDD, the amplifying transistor22outputs a signal voltage corresponding to the amount of signal charge accumulated in the charge accumulation node FD.

The address transistor24is connected between the amplifying transistor22and the vertical signal line35. The address transistor24has its gate connected to an address signal line34. The vertical scanning circuit122controls the turning on and turning off of the address transistor24by applying a row-selecting signal to the address signal line34. That is, by controlling a row-selecting signal, the vertical scanning circuit122allows an output from the amplifying transistor22of a selected pixel110to be read out to the corresponding vertical signal line35. Without being limited to the example shown inFIG.2, the address transistor24may be disposed between the drain of the amplifying transistor22and the power-supply wire32.

Each of the vertical signal lines35is connected to a load circuit45and a column signal processing circuit47. The load circuit45forms a source-follower circuit with the amplifying transistor22. The column signal processing circuit47executes noise suppression signal processing, analog-digital conversion, or other processing. The noise suppression signal processing is for example correlated double sampling. The column signal processing circuit47is also called “row signal accumulation circuit”. The horizontal signal readout circuit124sequentially reads out signals from a plurality of the column signal processing circuits47to a horizontal common signal line49. The column signal processing circuit47may be part of the horizontal signal readout circuit124. The load circuit45and the column signal processing circuit47may be part of the aforementioned peripheral circuit120A.

In this example, the readout circuit20includes the reset transistor26in addition to the amplifying transistor22and the address transistor24. A first one of a drain and a source of the reset transistor26is part of the charge accumulation node FD. A second one of the drain and the source is connected to a reset voltage line39. The first one of the drain and the source of the reset transistor26corresponds to the charge accumulation region Z ofFIG.3and, specifically, to an impurity region60n. The reset voltage line39has a connection with a reset voltage supply circuit (not illustrated inFIG.2). As a result of this, a predetermined reset voltage Vref may be supplied to the reset transistor26of each pixel110during operation of the imaging device100A. The reset voltage Vref is for example a voltage of 0 V or nearly 0 V. As is the case with the aforementioned voltage supply circuit126, the reset voltage supply circuit needs only be able to apply the reset voltage Vref to the reset voltage line39, and is not limited in specific configuration to a particular power-supply circuit. The reset voltage supply circuit may be part of the vertical scanning circuit122. The voltage supply circuit126and the reset voltage supply circuit may be independent separate circuits, or may be in the form of a single voltage supply circuit disposed in the imaging device100A. The reset voltage supply circuit too may be part of the aforementioned peripheral circuit120A.

The reset transistor26has its gate connected to a reset signal line36. As is the case with the address signal lines34, these reset signal lines36are provided separately for each of the rows of pixels110and, in this example, are connected to the vertical scanning circuit122. As mentioned above, by applying row-selecting signals to the address signal lines34, the vertical scanning circuit122can select, on a row-by-row basis, pixels110to which signals are to be read out. Similarly, by applying reset signals to the gates of the reset transistors26via the reset signal lines36, the vertical scanning circuit122can turn on a selected row of reset transistors26. The turning on of the reset transistors26causes the potentials of the charge accumulation nodes FD to be reset.

Pixels and Blocking Region

FIG.3schematically shows a cross-section including the pixel region R1, the first peripheral region R2, and the blocking region200A. This is a cross-section of two representative ones of the plurality of pixels110located near the blocking region200A.

First, attention is focused on the pixel region R1. The pixel region R1is provided with a photoelectric conversion layer12. The photoelectric conversion layer12is supported by the semiconductor substrate130. Over the photoelectric conversion layer12, a counter electrode13having translucency is disposed. As shown inFIG.3, the photoelectric conversion layer12and the counter electrode13are each typically successively provided above the semiconductor substrate130across the plurality of pixels110.

The pixels110are unit structures that constitute the pixel region R1. The pixels110each include a photoelectric converter10. The photoelectric converter10has part of the photoelectric conversion layer12, part of the counter electrode13, and a pixel electrode11. The pixel electrode11of the photoelectric converter10is located between the photoelectric conversion layer12and the semiconductor substrate130. The pixel electrode11is formed from metal such as aluminum or copper, a metal nitride, polysilicon given electrical conductivity by being doped with an impurity, or other substances. As schematically shown inFIG.3, the pixel electrode11of each pixel110is electrically separated from the pixel electrode11of another adjacent pixel by spatial separation of one pixel from another.

The photoelectric conversion layer12of the photoelectric converter10is formed from an organic material or an inorganic material. Examples of inorganic materials include amorphous silicon and quantum dots. The photoelectric conversion layer12generates positive and negative charge through photoelectric conversion upon receiving incident light via the counter electrode13. That is, the photoelectric converter10has a function of converting light into charge. The photoelectric conversion layer12may include a layer composed of an organic material and a layer composed of an inorganic material.

The counter electrode13of the photoelectric converter10is formed from a transparent conducting material such as ITO (indium tin oxide). The term “translucency” herein means allowing passage of at least a portion of light of a wavelength that the photoelectric conversion layer12can absorb, and it is not essential to allow passage of light across the whole range of wavelengths of visible light. Although not illustrated inFIG.3, the counter electrode13has a connection with the aforementioned voltage line38. During operation of the imaging device100A, the potential of the voltage line38is controlled so that the potential of the counter electrode13becomes for example higher than the potential of the pixel electrode11. As a result of this, of positive and negative charge generated by photoelectric conversion, the positive charge can be selectively collected by the pixel electrode11. Forming the counter electrode13in the shape of a single layer extending across the plurality of pixels110makes it possible to apply a predetermined potential to the counter electrode13of the plurality of pixels110en bloc via the voltage line38.

Each of the plurality of pixels110further includes part of the semiconductor substrate130. As schematically shown inFIG.3, the semiconductor substrate130has a plurality of the impurity regions60nas first impurity regions near a surface thereof. The impurity region60nfunctions as a first one of the drain and the source of the reset transistor26, which is included in the aforementioned readout circuit20. Further, the semiconductor substrate130also has an impurity region61nserving as a second one of the drain and the source of the reset transistor26. As schematically shown inFIG.3, the impurity region61nis connected to the aforementioned reset voltage line39via a polysilicon plug or other plugs. In this example, the impurity region60nand the impurity region61nhave an n-type conductivity type. These impurity regions60nand61nare typically n-type diffusion regions.

As can be understood from the foregoing, in the semiconductor substrate130, a plurality of the readout circuits20are formed in correspondence with the plurality of pixels110. The readout circuit20of each pixel is electrically separated from the readout circuit20of another pixel by a device isolation220provided in the semiconductor substrate130.

As shown inFIG.3, an interlayer insulating layer90covering the semiconductor substrate130is located between the photoelectric converter10and the semiconductor substrate130. The interlayer insulating layer90generally includes a plurality of insulating layers and a plurality of wiring layers. The plurality of wiring layers disposed in the interlayer insulating layer90may include a wiring layer having the address signal lines34, the reset signal lines36, or other wires as part thereof, a wiring layer having the vertical signal line35, the power-supply wire32, the reset voltage line39, or other wires as part thereof, or other wiring layers. The numbers of insulating layers and wiring layers in the interlayer insulating layer90are not limited to this example but may be arbitrarily set.

The interlayer insulating layer90has provided therein a conducting structure89electrically connecting the pixel electrode11of the photoelectric converter10to the readout circuit20, which is formed in the semiconductor substrate130. As schematically shown inFIG.3, the conducting structure89includes a wire and a via that are disposed in the interlayer insulating layer90. The wire and the via are typically formed from metal such as copper or tungsten or a metal compound such as a metal nitride or a metal oxide. The conducting structure89also includes a contact plug cx connected to the aforementioned impurity region60n. The contact plug cx, which is connected to the impurity region60n, is typically a polysilicon plug, and is doped with an impurity such as phosphorus for superior electrical conductivity. Although not illustrated inFIG.3, the conducting structure89also has an electrical connection with the gate electrode of the amplifying transistor22. A plug cy is connected to the contact plug cx. Examples of metal that the plug cy may contain include tungsten and copper.

Attention is focused on the semiconductor substrate130. The semiconductor substrate130includes a supporting substrate140and one or more semiconductor layers formed over the supporting substrate140. In the example shown inFIG.3, the semiconductor substrate130has an n-type impurity layer62provided over the supporting substrate140. The following takes a p-type silicon substrate as an example of the supporting substrate140. The supporting substrate140may have a lower electric resistivity than the impurity layer62. It should be noted that the semiconductor substrate130may be an SOI (silicon-on-insulator) substrate, a substrate having an epitaxial layer provided on a surface thereof by epitaxial growth or other processes, or other substrates.

Attention is focused on the pixel region R1first in the configuration illustrated inFIG.3. The semiconductor substrate130has an n-type semiconductor layer62anand a p-type semiconductor layer63p. The n-type semiconductor layer62anis provided over the supporting substrate140. The p-type semiconductor layer63pis provided over the n-type semiconductor layer62an. The n-type semiconductor layer62an, which is located between the supporting substrate140and p-type semiconductor layer63p, is part of the aforementioned impurity layer62. During operation of the imaging device100A, the potential of the impurity layer62is controlled via a well contact (not illustrated inFIG.3). The impurity layer62includes the n-type semiconductor layer62an, which is located in the pixel region R1, as part thereof and is provided inside the semiconductor substrate130. This makes it possible to reduce the flow of a small number of carriers from the supporting substrate140or the peripheral circuit into a charge accumulation region that accumulates signal charge.

In the configuration illustrated inFIG.3, the semiconductor substrate130further has a p-type semiconductor layer66pand a p-type impurity region65p. The p-type semiconductor layer66pis located over the p-type semiconductor layer63p. The p-type impurity region65pis provided in the p-type semiconductor layer66p. In this example, the aforementioned impurity region60n, which has a connection with the conducting structure89, is provided in the p-type impurity region65p. A junction capacitor that is formed by a p-n junction between the impurity region60nand the p-type impurity region65p, which serves as a p well, functions as a capacitor that stores at least a portion of signal charge that is collected by the pixel electrode11. That is, the impurity region60nconstitutes a charge accumulation region that temporarily retains signal charge. On the other hand, the impurity region61nis provided in the p-type semiconductor layer66p. In this example, the p-type impurity region65pis lower in impurity concentration than the p-type semiconductor layer66p.

Further, the semiconductor substrate130has a plurality of p-type regions64. The plurality of p-type regions64are provided in such a way as to pass completely through the impurity layer62. The p-type regions64have a comparatively high impurity concentration. Providing the p-type regions64makes it possible to electrically connect two regions of the same conductivity type separated from each other by the impurity layer62.

In this example, the plurality of p-type regions64include a plurality of p-type regions64aand one or more p-type regions64b. The p-type regions64aare located in the pixel region R1when seen from a direction normal to the semiconductor substrate130. The p-type region64bis located below the plurality of contact plugs211of the blocking region200A. The p-type regions64aare formed between the p-type semiconductor layer63pand the supporting substrate140in such a way as to pass completely through the n-type semiconductor layer62an, and electrically connect the p-type semiconductor layer63pto the supporting substrate140. On the other hand, the p-type region64bis electrically connected to the impurity region131of the blocking region200A by having one end reaching the impurity region131, and electrically connects the impurity region131to the supporting substrate140.

Accordingly, in this example, an electrical path leading from the impurity region131of the blocking region200A to the p-type semiconductor layer63pvia the p-type region64b, the supporting substrate140, and the p-type regions64ais formed in the semiconductor substrate130. As mentioned above, the plurality of contact plugs211are connected to the impurity region131of the blocking region200A, and these contact plugs211are configured to be connectable to a power source (not illustrated) such as a ground. For example, the potential of the impurity region131of the blocking region200A can be grounded via the plurality of contact plugs211. Connecting an appropriate power source to the plurality of contact plugs211of the blocking region200A makes it possible to control the potentials of the p-type impurity region65pand the p-type semiconductor layer66pvia the p-type semiconductor layer63pby utilizing an electrical path including the impurity region131, the p-type region64b, the supporting substrate140, and the p-type regions64a.

In the example shown inFIG.3, an impurity region131athat is relatively high in impurity concentration is formed in a portion of the impurity region131located near the surface of the semiconductor substrate130. The contact plugs211are typically formed from metal. Providing the impurity region131a, which is relatively high in impurity concentration in the impurity region131, and connecting the plurality of contact plugs211to the impurity region131abrings about an effect of reducing contact resistance between the plurality of contact plugs211and the impurity region131.

Furthermore, in this example, a silicide layer131sis formed between the plurality of contact plugs211and the impurity region131. Providing the silicide layer131sin a portion of the impurity region131anear the surface of the semiconductor substrate130and connecting the plurality of contact plugs211to the silicide layer131smakes it possible to further reduce the contact resistance.

Next, attention is focused on the first peripheral region R2of the semiconductor substrate130. As mentioned above, a circuit for driving the plurality of pixels110and a circuit for processing signals read out from the plurality of pixels110are formed in the first peripheral region R2. The first peripheral region R2includes, for example, a plurality of transistors25and a first peripheral transistor27that constitute a logic circuit such as a multiplexer. As schematically shown inFIG.3, in this example, an n-type semiconductor layer62bnthat is another part of the impurity layer62is formed over the supporting substrate140, and an n-type impurity region81nand a p-type impurity region82pare formed as wells over the n-type semiconductor layer62bn. Each of the transistors25has its drain and source located in the p-type impurity region82p, and the first peripheral transistor27has its drain and source located in the n-type impurity region81n. It should be noted that the n-type semiconductor layer62bnis separated by the mediation of part of the supporting substrate140from the n-type semiconductor layer62anall around the pixel region R1. The n-type semiconductor layer62bnis supplied with a predetermined voltage by being connected to a power source (not illustrated). In the following, the n-type impurity region81nis sometimes referred to as “n-type well”. The p-type impurity region82pis sometimes referred to as “p-type well”.

The depth of the n-type semiconductor layer62anof the pixel region R1and the depth of the n-type semiconductor layer62bnof the first peripheral region R2may be equal to or different from each other.

In the configuration illustrated inFIG.3, contact plugs cp are connected to the drain, source, and gate electrodes of peripheral transistors such as the transistors25and the first peripheral transistor27.

In the example shown inFIG.3, the blocking region200A further includes an n-type impurity region83nlocated near a boundary with the first peripheral region R2. The n-type impurity region83nis located over the n-type semiconductor layer62bnof the impurity layer62, and has an electrical connection with the n-type semiconductor layer62bn. The n-type impurity region83nmay be provided with a plug. Connecting an appropriate power source to the plug connected to the n-type impurity region83nmakes it possible to control the potentials of the n-type impurity region83nand the n-type semiconductor layer62bn.

Each of the impurity layers and impurity regions located above the supporting substrate140is formed by ion implantation of an impurity into an epitaxial layer obtained by epitaxial growth over the supporting substrate140. It should be noted that the p-type regions64a, which is located in the pixel region R1, of the p-type region64may be formed in places that do not overlap the device isolation in the pixels in a plan view.

In the present embodiment, the blocking region200A is formed between the pixel region R1and the first peripheral region R2. As mentioned above, the blocking region200A includes the device isolation220, which is located between the pixel region R1and the first peripheral region R2, and the impurity region131, over which the plurality of contact plugs211are disposed. Since the blocking region200A includes at least the impurity region131, a so-called gettering effect can be exerted by utilizing a dopant contained in the impurity region131. For example, it is known that diffusion of a metal impurity into a region in a semiconductor substrate supporting a photoelectric conversion layer in which pixels are disposed causes degradation in image quality. By causing the dopant contained in the impurity region131to function as a gettering center, the diffusion of a metal impurity into the charge accumulation region is suppressed, so that degradation in image quality due to the diffusion of the metal impurity may be avoided.

Examples of p-type impurities, i.e. dopants, for silicon substrates include boron, indium, and gallium, and examples of n-type dopants include phosphorus, arsenic, antimony, and bismuth. Of these substances, the p-type dopants are known to be able to exert a gettering effect on most metals and, accordingly, are suitable as dopants for the impurity region131. In a typical embodiment of the present disclosure, the p type is selected as the conductivity type of the impurity region131of the blocking region200A. For example, disposing the blocking region200A, which has its impurity region131doped with a p-type impurity, between the pixel region R1and the first peripheral region R2makes it possible to effectively suppress the diffusion of a metal impurity into the pixel region R1. That is, the diffusion of a metal impurity into the charge accumulation regions of the pixels110is suppressed, so that a deterioration in image quality due to the diffusion of the metal impurity can be reduced.

FIG.4shows another example of the shape of a blocking region. An imaging device100B shown inFIG.4differs from the imaging device100A shown inFIG.1in that instead of the blocking region200A, the imaging device100B has a blocking region200B surrounding the pixel region R1in the shape of a rectangle. As compared with the aforementioned blocking region200A, the impurity region131of the blocking region200B surrounds the pixel region R1in seamless manners in a circular pattern in a plan view. As schematically shown inFIG.4, in this example too, the plurality of contact plugs211are connected to the impurity region131. In this example, the device isolation220of the blocking region200B too surrounds the pixel region R1in seamless manners in a circular pattern inside the impurity region131. In such a configuration, it may be said that a boundary between the pixel region R1and the first peripheral region R2is defined by the device isolation220.

In this example, a peripheral circuit120B provided in the first peripheral region R2includes a second vertical scanning circuit129and a second horizontal signal readout circuit127in addition to the vertical scanning circuit122, the horizontal signal readout circuit124, the voltage supply circuit126, and the control circuit128. The vertical scanning circuit129is disposed to face the vertical scanning circuit122across the pixel region R1. As illustrated, to the vertical scanning circuit129too, address signal lines34provided separately in correspondence with each of the rows of pixels110are connected. Similarly, the horizontal signal readout circuit127is disposed to face the horizontal signal readout circuit124across the pixel region R1, and to the horizontal signal readout circuit127, vertical signal lines35provided separately in correspondence with each of the columns of pixels110are connected.

For example, the vertical scanning circuit122is responsible for a row-selecting operation on pixels in the left half of the pixel; region R1, and the vertical scanning circuit129is responsible for a row-selecting operation on pixels in the right half of the pixel region R1. Further, the horizontal signal readout circuit124is responsible for processing of signals read out from pixels in the lower half of the pixel region R1, and the horizontal signal readout circuit127is responsible for processing of signals read out from pixels in the upper half of the pixel region R1. By thus partitioning the pixel region R1and executing a readout of signals through a plurality of vertical scanning circuits and horizontal signal readout circuits, the speeding up of operations, such as the shortening of frame rates, can be achieved.

In the configuration illustrated inFIG.4, the vertical scanning circuits122and129and the horizontal signal readout circuits124and127are disposed along the four sides of the rectangular shape of the pixel region R1. In other words, in this example, the blocking region200B is interposed between the vertical scanning circuit122and a set of pixels110, between the vertical scanning circuit129and a set of pixels110, between the horizontal signal readout circuit124and a set of pixels110, and between the horizontal signal readout circuit127and a set of pixels110.

Forming the blocking region200B in the semiconductor substrate130in a shape that surrounds the pixel region R1, which includes an array of pixels110, in a plan view makes it possible to effectively suppress migration of charge between charge accumulation regions of the pixels and the circuits formed in the first peripheral region R2. It is not essential in the embodiment of the present disclosure that in a case where as in the case of the example shown inFIG.4, a group of circuits constituting a peripheral circuit is disposed, for example, to surround a rectangular pixel region R1, a blocking region surround the pixel region R1in seamless manners in a circular pattern in a plan view. For example, a blocking region may include a plurality of portions each including a device isolation220and an impurity region131, and the plurality of portions may be disposed as a whole to surround the pixel region R1. Such a configuration too is expected to bring about effects which are similar to those which are brought about in a case where a blocking region is provided in such a way as to surround the pixel region R1in seamless manners in a circular pattern in a plan view. Further, the blocking region200B is not indispensable.

Transistor of First Peripheral Region R2

As noted above, the first peripheral region R2includes the first peripheral transistor27. The following describes a configuration example of the first peripheral transistor27according to the embodiment with reference toFIGS.5A to15.

First Configuration Example

FIG.5Ashows a cross-sectional configuration of a first peripheral transistor27according to a first configuration example.FIG.5Bis a schematic cross-sectional view for explaining a region in the first peripheral transistor27according to the first configuration example where carbon is distributed. The following describes the first configuration example with reference toFIGS.5A and5B. It should be noted thatFIG.5Bomits to illustrate elements such as first side walls308Aa and308Ab and offset spacers309aand309b.

The first peripheral transistor27according to the first configuration example is specifically a MIS transistor, more specifically a MOSFET. Further, this first peripheral transistor27is a P-channel transistor.

As shown inFIGS.5A and5B, for example, a gate insulator film301composed of silicon oxide (SiO2) is interposed between a principal surface of a semiconductor substrate130and a gate electrode302composed of polysilicon or gate metal and formed over the principal surface. The semiconductor substrate130has formed in an upper part thereof an N-channel diffusion layer303in which, for example, arsenic (As) is diffused and the N-type impurity region81n, which is an N-type well in which, for example, arsenic (As) and phosphorus (P) are diffused and that is greater in junction depth than the N-type channel diffusion layer303. In the semiconductor substrate130, the supporting substrate140, the n-type semiconductor layer62bn, and the impurity region81n, which is an N-type well, are stacked in this order.

In regions in the N-type channel diffusion layer303along a gate length, first extension diffusion layers306aand306band first pocket diffusion layers307aand307bunder the first extension diffusion layers306aand306bare formed, respectively. The first extension diffusion layers306aand306bare P-type extension high-concentration diffusion layers in which a P-type impurity such as boron (B) is diffused and that have comparatively shallow junctions. The first pocket diffusion layers307aand307bare N-type pocket diffusion layers in which an N-type impurity such as arsenic (As) is diffused.

In regions in the semiconductor substrate130outside the first extension diffusion layers306aand306b, a p-type source diffusion layer313aand a p-type drain diffusion layer313bare formed. The p-type source diffusion layer313aand the p-type drain diffusion layer313bare connected to the first extension diffusion layers306aand306b, and are greater in junction depth than the first extension diffusion layers306aand306b.

The supporting substrate140is a silicon substrate. Specifically, the supporting substrate140is a p-type silicon substrate.

A first epitaxial layer135is formed over the supporting substrate140. In this example, the first epitaxial layer135is a silicon (Si) layer.

A second epitaxial layer136is formed over the first epitaxial layer135. The second epitaxial layer136is a silicon-germanium (SiGe) layer.

A third epitaxial layer137is formed over the second epitaxial layer136. The third epitaxial layer137constitutes a surface of the semiconductor substrate130. The third epitaxial layer137is a silicon (Si) layer. The third epitaxial layer137may be referred to as “cap layer”.

The supporting substrate140, the first epitaxial layer135, the second epitaxial layer136, and the third epitaxial layer137are stacked in this order. In this example, the second epitaxial layer136is thinner than the first epitaxial layer135. The third epitaxial layer137is thinner than the second epitaxial layer136.

The first epitaxial layer135includes the n-type semiconductor layer62bnand the n-type impurity region81n. The first epitaxial layer135includes the N-type channel diffusion layer303. The first epitaxial layer135includes the first pocket diffusion layer307aand the first pocket diffusion layer307b. The first epitaxial layer135includes the p-type source diffusion layer313aand the p-type drain diffusion layer313b.

The second epitaxial layer136includes the N-type channel diffusion layer303. A portion of the second epitaxial layer136included in the N-type channel diffusion layer303constitutes a cSiGe (channel SiGe) layer. The second epitaxial layer136includes the first extension diffusion layer306aand the first extension diffusion layer306b. The second epitaxial layer136includes the p-type source diffusion layer313aand the p-type drain diffusion layer313b.

The third epitaxial layer137includes the N-type channel diffusion layer303. The third epitaxial layer137includes the first extension diffusion layer306aand the first extension diffusion layer306b. The third epitaxial layer137includes the p-type source diffusion layer313aand the p-type drain diffusion layer313b.

As can be understood from the foregoing description, in the N-type channel diffusion layer303according to the first configuration example, the first epitaxial layer135, which is made of silicon, and the second epitaxial layer136, which is made of silicon germanium, are bonded to each other. Silicon and silicon germanium have different lattice constants. Specifically, the lattice constant of the silicon-germanium layer is greater than the lattice constant of the silicon layer, and a compression strain is applied to the silicon substrate. This causes a compression strain on the N-type channel diffusion layer303. The compression strain brings about improvement in the carrier mobility of the P-channel transistor. This may improve the driving force of the first peripheral transistor27and increase the speed of operation of the first peripheral transistor27. This brings about improvement in the characteristics of the first peripheral transistor27. Further, this is advantageous from the point of view of reducing the area of the first peripheral region R2. In the first configuration example, the second epitaxial layer136is equivalent to a first strain-introducing layer.

The compression strain is further described. The first epitaxial layer135is a Si layer obtained by epitaxially growing Si. In this Si layer, Si is a constituent element of a crystal lattice. The second epitaxial layer136is a cSiGe layer obtained by epitaxially growing SiGe. In this cSiGe layer, SiGe is a constituent element of a crystal lattice. For this reason, the difference in material of the layers between Si and SiGe causes the difference in lattice constant between the layers. The difference in lattice constant brings about the compression strain.

Furthermore, in the first configuration example, a quantum-confined effect based on the second epitaxial layer136may be expressed. This quantum-confined effect too may bring about improvement in the characteristics of the first peripheral transistor27. The improvement in the characteristics by the quantum-confined effect is easily seen in a case where the second epitaxial layer136is thin and the concentration of germanium in the second epitaxial layer136is high.

The first extension diffusion layers306aand306bmay contain carbon (C). Carbon (C) may suppress induced transient enhanced diffusion (hereinafter abbreviated as “TED”) of boron. This makes it possible to keep shallow impurity concentration profiles in the first extension diffusion layers306aand306b. This is advantageous from the point of view of achieving the first peripheral transistor27with increased driving force.

Carbon also makes it possible to suppress phosphorus-induced TED. For example, the N-type channel diffusion layer303and the first pocket diffusion layers307aand307bmay contain phosphorus and carbon. In this configuration example, TED of phosphorus may be suppressed by carbon in the N-type channel diffusion layer303and the first pocket diffusion layers307aand307b. This is advantageous from the point of view of achieving the first peripheral transistor27with reduced variation in threshold voltage.

Incidentally, in the process of manufacturing an imaging device, heat treatment may be executed for the purpose of heating the pixel region R1. This heat treatment may cause the first peripheral region R2to be heated too. However, the aforementioned diffusion-suppressing action derived from carbon suppresses the redistribution of the impurity in the first peripheral transistor27of the first peripheral region R2even in a case where the first peripheral region R2is heated by such heat treatment. For example, in a case where the first extension diffusion layers306aand306bcontain boron and carbon, the redistribution of boron is suppressed by carbon, whereby the shallow junctions may be maintained. Further, in a case where the N-type channel diffusion layer303contains phosphorus and carbon, the redistribution of phosphorus may be suppressed by carbon.

Further, the inclusion of carbon in the first extension diffusion layers306aand306balso brings about an effect of reducing the occurrence of residual defects in the first extension diffusion layers306aand306b. Examples of residual defects include EOR (end-of-range) defects. The term “EOR defect” here refers to a defect layer that is formed in a region directly below an amorphous/crystal (a/c) interface before thermal processing in a case where the semiconductor substrate130, which is composed of silicon, is subjected to thermal processing in an amorphized state.

TED is suppressed by carbon implantation through the following mechanism. That is, carbon forms, for example, carbon-lattice silicon or carbon-vacancy complexes or clusters with enhanced point defects, which induce TED, and thereby reduces enhanced point defects. Further, in consideration of the fact that enhanced point defects may grow to generate secondary defects such as dislocation loops, it can be said that carbon reduces crystal defects. For example, by using, in extension formation regions of the semiconductor substrate130, crystal layers with reduced generation of residual defect layers such as secondary defects, even the occurrence of junction leaks due to residual defect layers can be reduced.

When variations in the threshold voltage of the first peripheral transistor27are small, it is not necessary to secure a wide design margin of the first peripheral transistor27. In addition, a Pelgrom coefficient can be reduced. Note here that variations in the threshold voltage of a transistor can be expressed by σvt=Avt/√(Lg·Wg), and are proportionate to the reciprocal of the square root of the product of the gate length (Lg) and the gate width (Wg). The tilt Avt at this point in time is known as a Pelgrom coefficient. This makes it possible to select a small-size (specifically, small-area) transistor with a small gate length (Lg) and/or a small gate width (Wg).

When variations in the threshold voltage of the first peripheral transistor27are small, it is easy to reduce the number of variations in size differences that the first peripheral transistor27should include. Think of, for example, a case in which variations in the threshold voltage of the first peripheral transistor27are small and other characteristics of the first peripheral transistor27are satisfactory. Sizes of transistor that make the characteristics of a transistor suitable vary from one characteristic to another. For example, a size of transistor for achieving a suitable Pelgrom coefficient, a size of transistor for achieving a suitable mutual conductance (gm), and a size of transistor for achieving a suitable drain conductance (gds) are different from one another. However, in the aforementioned case, it is not highly necessary for the first peripheral transistor27to include variations that vary in size from characteristic to characteristic. This makes it possible to reduce the number of first peripheral transistors27that are disposed in the first peripheral region, thereby making it possible to reduce the area of the first peripheral region.

It should be noted that carbon, fluorine, and nitrogen are easily segregated in an EOR defect. In the present configuration example, EOR defects are present in portions directly below the first extension diffusion layers306aand306b, and carbon is segregated in the EOR defects.

The suppression of TED by carbon (C) in the first configuration example is further described.

As mentioned above, the second epitaxial layer136of the first configuration example is a cSiGe layer obtained by epitaxially growing SiGe. A SiGe layer is less prone to TED mediated by interstitial silicon than a Si layer. TED mediated by interstitial silicon is for example TED of a p-type impurity such as boron (B). On the other hand, a SiGe layer is more prone to TED mediated by atomic vacancy than a Si layer. TED mediated by atomic vacancy is for example TED of an n-type impurity such as arsenic (As). The likelihood of TED mediated by atomic vacancy in a SiGe layer increases as the content of Ge in the SiGe layer increases.

In an example of the first configuration example, such a cSiGe layer is formed in the first peripheral transistor27, and a n-type impurity such as arsenic (As) is present in the first peripheral transistor27. Specifically, the first pocket diffusion layers307aand307bcontain arsenic. In this case, when heat treatment is performed for the purpose of heating the pixel region R1, the first peripheral region R2too is heated. This may cause arsenic to diffuse by TED. Specifically, the diffusion tends to occur in a direction toward the SiGe layer. This may cause an increase in the concentration of arsenic in the cSiGe layer.

However, in the first configuration example, carbon is contained in a region near the cSiGe layer. This makes it difficult for an n-type impurity such as arsenic (As) from diffusing into the cSiGe layer by TED.

The region near the cSiGe layer may include the first extension diffusion layers306aand306b. The region near the cSiGe layer may include the first pocket diffusion layers307aand307b. InFIG.5B, carbon-implanted layers311are exemplarily indicated by dotted circles. A similar effect may be brought about in a case where the impurity contained in the first pocket diffusion layers307aand307bis an n-type impurity other than arsenic.

In the present configuration example, the p-type source diffusion layer313aand the p-type drain diffusion layer313bcontain carbon (C). Note, however, that either or both of the p-type source diffusion layer313aand the p-type drain diffusion layer313bmay not contain carbon (C).

On both side surfaces of the gate electrode302, offset spacers309aand309bhaving insulation properties are formed. The offset spacers309aand309bcontain elements implanted in the step of implanting an impurity for forming the first extension diffusion layers306aand306band/or the step of implanting an impurity for forming the first pocket diffusion layers307aand307b. Examples of elements that are implanted into the offset spacers309aand309binclude boron, arsenic, and carbon. Furthermore, first side walls308Aa and308Ab with L-shaped cross-sections are formed over the semiconductor substrate130. The first side walls308Aa and308Ab extend from over outer side surfaces of the offset spacers309aand309bto upper portions of inner ends of the p-type source diffusion layer313aand the p-type drain diffusion layer313b, respectively. Further, second side walls308Ba and308Bb having insulation properties are formed on outer sides of the first side walls308Aa and308Ab, respectively.

In the first configuration example, arsenic ions are used as an impurity of the N-type channel diffusion layer303. Note, however, that the N-type channel diffusion layer303may contain phosphorus ions instead of or in combination with arsenic ions. Further, the N-type channel diffusion layer303may contain, instead of or in combination with arsenic ions, ions of an element that is larger in atomic number than arsenic and that exhibits an n type. Examples of elements that are larger in atomic number than arsenic and that exhibit an n type include antimony and bismuth.

An impurity that can be employed as an impurity of the N-type channel diffusion layer303may be employed as an impurity of the first pocket diffusion layers307aand307b. Further, an impurity that can be employed as an impurity of the first pocket diffusion layers307aand307bmay be employed as an impurity of the N-type channel diffusion layer303. Examples of impurities that the N-type channel diffusion layer303and the first pocket diffusion layers307aand307bmay contain include phosphorus, arsenic, antimony, and bismuth.

Further, carbon is not the only impurity that contributes to suppression of TED. Instead of or in combination with carbon, at least one selected from the group consisting of nitrogen, fluorine, germanium, silicon, and argon may be used. Nitrogen, fluorine, germanium, silicon, argon, or other impurities may contribute to suppression of TED. Specifically, as is the case with carbon, impurities such as nitrogen and fluorine form, for example, impurity-lattice silicon or impurity-vacancy complexes or clusters with enhanced point defects, which induce TED, and thereby reduce enhanced point defects. Specifically, enhanced point defects are reduced by the formation of, for example, carbon-lattice silicon, nitrogen-lattice silicon, fluorine-lattice silicon, carbon-vacancy, nitrogen-vacancy, and fluorine-vacancy complexes. Germanium, silicon, argon, or other impurities contribute to suppression of TED through the pre-amorphization action. Besides, at least one selected from among non-conducting elements in the group consisting of elements in groups14,17, and18may be used as an impurity that contributes to suppression of TED.

Further, in the first configuration example, the first peripheral transistor27is a P-channel MIS transistor. Note, however, that a configuration in which the first peripheral transistor27is an N-channel MIS transistor may be adopted too. In a case where the first peripheral transistor27is an N-channel MIS transistor, arsenic (As) ions, ions of a Group V element that are larger in atomic number than arsenic ions, such as phosphorus (P) ions, antimony (Sb) ions, or bismuth (Bi) ions, or a combination thereof can be used as n-type impurity ions that constitute an n-type extension diffusion layer. Further, in a case where the first peripheral transistor27is an N-channel MIS transistor, boron (B) ions or indium (In) ions, ions of a Group III element that are larger in atomic number than boron ions, such as gallium (Ga) ions, or a combination thereof can be used in a p-type pocket diffusion layer. In this configuration too, TED of the p-type pocket diffusion layer may be suppressed. For example, TED of boron may be suppressed by causing the p-type pocket diffusion layer to contain carbon or other substances in combination with boron. Further, indium too is prone to TED mediated by interstitial silicon, albeit to a lesser degree than boron. This makes it possible to suppress TED of indium by co-implanting carbon or other substances in combination with indium. Suppression of TED makes it possible to reduce variations in threshold voltage attributed to pocket profiles. For example, in a case where the first peripheral transistor27is a P-channel MIS transistor, boron (B) ions or indium (In) ions, ions of a Group III element that are larger in atomic number than boron ions, such as gallium (Ga) ions, or a combination of two or more thereof may be used as p-type impurity ions that constitute a p-type extension diffusion layer. Arsenic (As) ions, ions of a Group V element that are larger in atomic number than arsenic ions, such as phosphorus (P) ions, antimony (Sb) ions, or bismuth (Bi) ions, or a combination thereof can be used as n-type impurity ions that constitute an n-type pocket diffusion layer.

Second Configuration Example

FIG.6Ashows a cross-sectional configuration of a first peripheral transistor27according to a second configuration example.FIG.6Bis a schematic cross-sectional view for explaining a region in the first peripheral transistor27according to the second configuration example where carbon is distributed. The following describes the second configuration example with reference toFIGS.6A and6B. It should be noted thatFIG.6Bomits to illustrate elements such as first side walls308Aa and308Ab and offset spacers309aand309b. A description of configurations that the second configuration example has in common with the first configuration example may be omitted.

As shown inFIG.6C, a first recessed portion133and a second recessed portion134are formed in the first epitaxial layer135. As shown inFIG.6D, a fourth epitaxial layer138is formed over the first recessed portion133. As shown inFIG.6D, a fifth epitaxial layer139is formed over the second recessed portion134. The fourth epitaxial layer138and the fifth epitaxial layer139are silicon-germanium (SiGe) layers.FIG.6Cis a schematic cross-sectional view showing the first recessed portion133and the second recessed portion134, which are formed in the first epitaxial layer135.FIG.6Comits to illustrate the fourth epitaxial layer138, the fifth epitaxial layer139, or other layers.

The fourth epitaxial layer138has an embedded portion138cand a raised portion138r. The embedded portion138eis a portion embedded in the first recessed portion133. The raised portion138ris a portion raised from the embedded portion138c. Further, the raised portion138ris a portion projecting out of the first recessed portion133.

The fifth epitaxial layer139has an embedded portion139eand a raised portion139r. The embedded portion139eis a portion embedded in the second recessed portion134. The raised portion139ris a portion raised from the embedded portion139c. Further, the raised portion139ris a portion projecting out of the second recessed portion134.

FIG.6Dis a schematic cross-sectional view for explaining the embedded portion138c, the raised portion138r, the embedded portion139e, and the raised portion139r.

The first epitaxial layer135includes the N-type channel diffusion layer303. The first epitaxial layer135includes the first extension diffusion layer306aand the first extension diffusion layer306b. The first epitaxial layer135includes the first pocket diffusion layer307aand the first pocket diffusion layer307b.

The p-type source diffusion layer313ais formed using the fourth epitaxial layer138. The p-type drain diffusion layer313bis formed using the fifth epitaxial layer139.

As can be understood from the foregoing description, in the second configuration example, the N-type channel diffusion layer303is disposed between the p-type source diffusion layer313aand the p-type drain diffusion layer313b. The N-type channel diffusion layer303is formed using the first epitaxial layer135of silicon. The p-type source diffusion layer313ais formed using the fourth epitaxial layer138of silicon germanium. The p-type drain diffusion layer313bis formed using the fifth epitaxial layer139of silicon germanium. According to this configuration, the N-type channel diffusion layer303is pushed in from the p-type source diffusion layer313aand the p-type drain diffusion layer313b. This causes a compression strain on the N-type channel diffusion layer303. The compression strain brings about improvement in carrier mobility. This may improve the driving force of the first peripheral transistor27and increase the speed of operation of the first peripheral transistor27. This brings about improvement in the characteristics of the first peripheral transistor27. Further, this is advantageous from the point of view of reducing the area of the first peripheral region R2. In the second configuration example, the p-type source diffusion layer313aand the p-type drain diffusion layer313bare equivalent to a first strain-introducing layer.

In the second configuration example too, as in the first configuration example, suppression of TED by carbon (C) may be expressed. The following further describes the suppression of TED by carbon (C) in the second configuration example.

As mentioned above, in the second configuration example, the fourth epitaxial layer138and the fifth epitaxial layer139are an esiGe layer and an rSiGe layer having boron as an impurity. Specifically, the fourth epitaxial layer138and the fifth epitaxial layer139are layers formed by in-situ-dope epitaxial growth. The in-situ-dope epitaxial growth is a technique for performing epitaxial growth while performing impurity doping. The impurity here is boron. When based on boron as an impurity, the in-situ-dope epitaxial growth makes it possible to achieve high boron concentrations in the fourth epitaxial layer138and the fifth epitaxial layer139. That is, high boron concentrations in the p-type source diffusion layer313aand the p-type drain diffusion layer313bcan be achieved. High boron concentrations are advantageous from the point of view of reducing the values of resistance of the p-type source diffusion layer313aand the p-type drain diffusion layer313b.

Note, however, that when heat treatment is performed for the purpose of heating the pixel region R1, the first peripheral region R2too is heated. This causes boron to exude or diffuse from the p-type source diffusion layer313a, which is constituted using the eSiGe layer and the rSiGe layer, to the Si layer derived from the first epitaxial layer135. This also causes boron to exude or diffuse from the p-type drain diffusion layer313b, which is constituted using the eSiGe layer and the rSiGe layer, to the Si layer derived from the first epitaxial layer135. When boron having exuded to the Si layer diffuses by TED in the Si layer, a short channel effect may be brought about in the first peripheral transistor27. The short channel effect may change the threshold voltage of a transistor from a desired value and invite a decrease in performance of the first peripheral transistor27. Since a SiGe layer is higher in solid solubility of boron than a Si layer, a high concentration of boron may be present in a SiGe layer. From the point of view of reducing the values of resistance of the p-type source diffusion layer313aand the p-type drain diffusion layer313b, it is possible to increase concentrations of doped-boron in the SiGe layers used to constitute these diffusion layers. In such a situation, the aforementioned exudation may become obvious. A higher content of Ge in a SiGe layer leads to higher solid solubility of boron in the SiGe layer.

However, in the second configuration example, carbon is contained in regions near the eSiGe layer and the rSiGe layer. This suppresses boron from diffusing by TED in the Si layer even if boron exudes from the eSiGe layer and the rSiGe layer to the Si layer. This may suppress the short channel effect and reduce deterioration of the performance of the first peripheral transistor27. InFIG.6B, carbon-implanted layers311are exemplarily indicated by dotted circles.

First Modification of First Configuration Example

FIG.7shows a cross-sectional configuration of a transistor according to a first modification of the first configuration example.FIG.7omits to illustrate the first epitaxial layer135, the second epitaxial layer136, and the third epitaxial layer137.

In the transistor according to the first modification, as shown inFIG.7, the impurity concentration profiles of the first extension diffusion layers306aand306b, which are P-type extension high-concentration diffusion layers, are bilaterally asymmetric with respect to the gate electrode302. Making a source region shallower and steeper in extension profile than a drain region as shown inFIG.7effect an increase in carrier concentration gradient between the source region and a channel region, bringing about improvement in driving force in the MIS transistor. Further, since the drain region is deeper in extension profile than the source region, less hot carriers are generated than in a symmetrical, shallow, and steep profile structure. It should be noted that a transistor having the configuration ofFIG.7may be fabricated, for example, with reference to Japanese Patent No. 5235486.

In the example shown inFIG.7, the first extension diffusion layer306ais shallower than the first extension diffusion layer306b. Note, however, that a configuration in which the first extension diffusion layer306bis shallower than the first extension diffusion layer306amay be adopted.

In the second configuration example too, the bilaterally asymmetric impurity concentration profiles of the first extension diffusion layers306aand306bcan be applied.

Second Modification of First Configuration Example

FIG.8shows a cross-sectional configuration of a transistor according to a second modification of the first configuration example.FIG.8omits to illustrate the first epitaxial layer135, the second epitaxial layer136, and the third epitaxial layer137.

As shown inFIG.8, the transistor according to the second modification has a P-type extension high-concentration diffusion layer beside only either the p-type source diffusion layer313aor the p-type drain diffusion layer313b.

In the example shown inFIG.8, the transistor according to the second modification has the first extension diffusion layer306aas a p-type extension high-concentration diffusion layer that is adjacent to the p-type source diffusion layer313aand, meanwhile, does not have a first extension diffusion layer that is adjacent to the p-type drain diffusion layer313b. Note, however, that a configuration in which the transistor does not have a first extension diffusion layer that is adjacent to the p-type source diffusion layer313aand, meanwhile, has the first extension diffusion layer306badjacent to the p-type drain diffusion layer313bmay be adopted.

Further, as shown inFIG.8, the transistor according to the second modification has an n-type pocket diffusion layer beside only either the p-type source diffusion layer313aor the p-type drain diffusion layer313b. Specifically, the transistor according to the second modification has the first pocket diffusion layer307aadjacent to the p-type source diffusion layer313aand, meanwhile, does not have a first pocket diffusion layer that is adjacent to the p-type drain diffusion layer313b. Note, however, that a configuration in which the transistor does not have a first pocket diffusion layer that is adjacent to the p-type source diffusion layer313aand, meanwhile, has the first pocket diffusion layer307badjacent to the p-type drain diffusion layer313bmay be adopted.

It is also possible to adopt a configuration of the second configuration example in which either the first extension diffusion layer306aor the first extension diffusion layer306bis absent. It is also possible to adopt a configuration of the second configuration example in which either the first pocket diffusion layer307aor the first pocket diffusion layer307bis absent.

Third Modification of First Configuration Example

In a third modification of the first configuration example, the p-type source diffusion layer313aand the p-type drain diffusion layer313bcontain fluorine (F) and carbon (C). Fluorine may bring about partial amorphization of the semiconductor substrate130. Further, fluorine may suppress transient enhanced diffusion (TED) of impurities.FIG.9shows examples of impurity concentration distributions in regions along a straight line passing through the p-type source diffusion layer313aand extending in a direction parallel with the depth of the semiconductor substrate130. The vertical axis represents the concentrations of fluorine (F), carbon (C), boron (B), and germanium (Ge) on a log scale. The concentration distributions ofFIG.9relate to a case where fluorine is implanted for amorphization and suppression of the diffusion of the impurities and diffused during annealing. In the examples shown inFIG.9, the concentration distribution of fluorine has segregation near the original position of the a/c interface. In this example, impurity concentration distributions in regions along a straight line passing through p-type drain diffusion layer313band extending in a direction parallel with the depth of the semiconductor substrate130too are distributions shown inFIG.9.

According to the third modification, the diffusion of the impurities is suppressed after the aforementioned annealing. Further, even if the first peripheral region R2is heated during thermal processing for the pixel region R1, redistributions of the impurities may fall within narrow ranges.

In the second configuration example too, impurity concentration distributions such as those shown inFIG.9are applicable.

Fourth Modification of First Configuration Example

As described with reference toFIGS.5A and5B, in the first configuration example, the first peripheral transistor27has the third epitaxial layer137, i.e. the cap layer. As can be understood from the following description of a manufacturing method with reference toFIGS.10to13, in the first configuration example, the cap layer is an impurity-doped layer. In the fourth modification, the third epitaxial layer137, i.e. the cap layer, is a non-doped layer. The cap layer of the fourth modification can be prepared by adjusting the range of implantation of an impurity.

Fifth Modification of First Configuration Example

As described with reference toFIGS.5A and5B, in the first configuration example, the first peripheral transistor27has the third epitaxial layer137, i.e. the cap layer. Specifically, in the first configuration example, the cap layer constitutes the surface of the semiconductor substrate130. Note, however, that this is not essential. In the fifth modification, the third epitaxial layer137, i.e. the cap layer, is not present. The second epitaxial layer136, i.e. the cSiGe layer, constitutes the surface of the semiconductor substrate130.

In addition, the features of the first configuration example described with reference toFIGS.5A and5Band the features of the second configuration example described with reference toFIGS.6A to6Dmay be combined. For example, the surface of the semiconductor substrate130in the second configuration example may be constituted by the third epitaxial layer137, i.e. the cap layer. Further, the first peripheral transistor27may have the first epitaxial layer135, the second epitaxial layer136, the third epitaxial layer137, the fourth epitaxial layer138, and the fifth epitaxial layer139.

Method for Manufacturing First Peripheral Transistor According to First Configuration Example

The following describes, with reference toFIGS.10A to13C, a method for manufacturing a first peripheral transistor27according to the first configuration example shown inFIGS.5A and5B.FIGS.10A to13Care cross-sectional views showing the method for manufacturing a first peripheral transistor27according to the first configuration example.

FIGS.10Ato E,FIGS.11A to11E,FIGS.12A to12D, andFIGS.13A to13Cshow cross-sectional configurations in the order of steps of a method for manufacturing a MIS transistor according to the first configuration example.

First, as shown inFIG.10A, silicon (Si) is epitaxially grown over a supporting substrate140. As a result of this, a first epitaxial layer135is formed over the supporting substrate140. In the example ofFIGS.10A to10E, the first epitaxial layer135is formed by epitaxially growing silicon over the supporting substrate140in both the pixel region R1and the first peripheral region R2. As one example, the first epitaxial layer135has a film thickness falling within a range of 3 μm to 10 μm. It should be noted that the semiconductor substrate130may be an SOI (silicon-on-insulator) substrate, a substrate having an epitaxial layer provided on a surface thereof by epitaxial growth or other processes, or other substrates.

Next, as shown inFIG.10B, a portion27rof the first epitaxial layer135in which a first peripheral transistor27is to be formed is recessed. As a result of this, a recessed portion135cis formed in the first epitaxial layer135. The depth of the recessed portion135cis shallower than the depth of the N-type channel diffusion layer303to be formed. Specifically, the recessed portion135cis formed by etching involving the use of a mask having an opening in a portion corresponding to the portion27rin which the first peripheral transistor27is to be formed.

Next, as shown inFIG.10C, silicon germanium (SiGe) is epitaxially grown in the recessed portion135c. This epitaxial growth is performed with the aforementioned mask kept provided. As a result of this, a second epitaxial layer136is formed in the recessed portion135c. The second epitaxial layer136constitutes a cSiGe layer. The thickness of the cSiGe layer is for example less than or equal to 10 nm. Specifically, the thickness of the cSiGe layer may be greater than or equal to 5 nm and less than or equal to 7 nm. When silicon germanium of the cSiGe layer is denoted by Si1-xGex, X is larger than 0 and smaller than 1. In one example, X is greater than or equal to 0.1 and less than or equal to 0.8. X may be greater than or equal to 0.1 and less than or equal to 0.65. As mentioned above, the second epitaxial layer136may cause a quantum-confined effect to be expressed. Improvement in the characteristics by the quantum-confined effect is easily seen in a case where the second epitaxial layer136is thin and the concentration of germanium in the second epitaxial layer136is high. In one example, the second epitaxial layer136is smaller in film thickness than the first epitaxial layer135.

Next, as shown inFIG.10D, silicon (Si) is epitaxially grown on the second epitaxial layer136in the recessed portion135c. This epitaxial growth is performed with the aforementioned mask kept provided. As a result of this, a third epitaxial layer137is formed over the second epitaxial layer136. The third epitaxial layer137constitutes a cap layer. The thickness of the cap layer is for example greater than or equal to 1 nm and less than or equal to 2 nm. In a case where the cap layer is formed in the first peripheral region R2, there may be a difference in level with respect to the pixel region R1.

In the present embodiment, the pixel region R1and the first peripheral region R2are isolated from each other by a device isolation220such as an STI structure. Further, in the first peripheral region R2, an N-channel transistor and a P-channel transistor are isolated from each other by a device isolation220such as an STI structure. In the second configuration example too, a device isolation220such as an STI structure can be formed in a similar fashion.FIG.10Eillustrates a structure in which a device isolation220is formed.

A device isolation220may be formed by any method. An STI structure serving as a device isolation220may be formed by an STI process. In a specific example of the present embodiment, the first epitaxial layer135is recessed after the structure shown inFIG.10Dhas been obtained. As a result of this, a trench (groove) is formed. The trench can be formed, for example, by etching involving the use of a mask. After that, the trench is filled with a filler such as an oxide. This filling can be performed by chemical vapor deposition (CVD) or other processes. This way makes it possible to form an STI structure serving as a device isolation220. In these respects, the same applies to not only a case where a first peripheral transistor27according to the first configuration example is manufactured according toFIGS.10A to13Cbut also a case where a first peripheral transistor27according to the second configuration example is manufactured according toFIGS.15A to15Cor other drawings.

Further, a device isolation220may be formed at any timing. As mentioned above, an STI structure serving as a device isolation220may be formed by an STI process. In an example of this case, an STI structure is formed by an STI process after the structure shown inFIG.10Ahas been obtained. After that, the region in which the second epitaxial layer136is to be formed, i.e. the portion27rin which the first peripheral transistor27is to be formed, is selectively etched. As a result of this, the recessed portion135cshown inFIG.10Bis formed. After that, the second epitaxial layer136is formed by epitaxially growing SiGe. In another example an STI structure is formed by an STI process after the structure shown inFIG.10Dhas been obtained. It should be noted that the STI structure may be shaped such that its width becomes narrower toward the bottom and its side surfaces are inclined at angles. The depth of the STI structure may be deeper than the bottom of the recessed portion135cor may be deeper than the depth of the charge accumulation region Z of the pixel region R1.

InFIG.10E, the device isolation220includes a projecting portion projecting upward from an upper surface of the first epitaxial layer135. Note, however, that the device isolation220may not include the projecting portion. In this respect, the same applies to not only a case where a first peripheral transistor27according to the first configuration example is manufactured but also the second configuration example.

InFIG.10E, the device isolation220is in contact with the second epitaxial layer136and the third epitaxial layer137. Note, however, that the device isolation220may not be in contact with the second epitaxial layer136and the third epitaxial layer137. In a case where a first peripheral transistor27according to the second configuration example is manufactured according toFIGS.15A to15Cor other drawings, the device isolation220may or may not be in contact with the fifth epitaxial layer139.

The following further describes, with reference toFIGS.11A to11Eor other drawings, the method for manufacturing a first peripheral transistor27according to the first configuration example.FIGS.11A to11Eor other drawings may omit to illustrate the first epitaxial layer135, the second epitaxial layer136, the third epitaxial layer137, or other layers. Further,FIGS.11A to11Eor other drawings intensively illustrate the portion27rin which the first peripheral transistor27is to be formed.

After the formation of the structure ofFIG.10D, as shown inFIG.11A, impurity ions are implanted into the semiconductor substrate130. This ion implantation phosphorus (P) ion implantation involving an implantation energy of 1000 keV and an implantation dose amount of 3×1012/cm2. This implantation results in the formation of an n-type injection layer62bnA.

Next, as shown inFIG.11A, an n-type well impurity-implanted layer304A is formed by implanting impurity ions into the semiconductor substrate130. This ion implantation includes, for example, a first stage and a second stage. The first stage of ion implantation is phosphorus (P) ion implantation involving an implantation energy of 600 keV and an implantation dose amount of 5×1012/cm2. The second stage of ion implantation is phosphorus (P) ion implantation involving an implantation energy of 260 keV and an implantation dose amount of 7×1012/cm2. The first and second stages of ion implantation result in the formation of the n-type well impurity-implanted layer304A.

After that, arsenic (As) ions are implanted into the semiconductor substrate130with an implantation energy of approximately 85 keV and in an implantation dose amount of approximately 5×1012/cm2. As a result of this, an N-type channel impurity-implanted layer303A is formed on top of the n-type well impurity-implanted layer304A.

The ion implantation by which the n-type injection layer62bnA, the n-type well impurity-implanted layer304A, and the n-type channel impurity-implanted layer303A are formed may be preceded by deposition of a silicon oxide film on a surface of the semiconductor substrate130. The n-type injection layer62bnA, the n-type well impurity-implanted layer304A, and the n-type channel impurity-implanted layer303A may be formed in any order.

Next, as shown inFIG.11B, the semiconductor substrate130thus ion-implanted is subjected to first rapid thermal processing (RTA) that raises the temperature to approximately to 850° C. to 1050° C. at a temperature rise rate higher than or equal to approximately 100° C./sec. e.g. approximately 200° C./sec, and keeps the peak temperature for a maximum of approximately ten seconds or does not keep the peak temperature. This first rapid thermal processing causes the N-type channel diffusion layer303and N-type wells, namely the n-type impurity region81nand the n-type semiconductor layer62bn, to be formed in the upper part of the semiconductor substrate130. It should be noted that the rapid thermal processing that does not keep the peak temperature refers to thermal processing in which the thermal processing temperature drops at the same time as it reaches the peak temperature.

Next, as shown inFIG.11C, a gate insulator film301composed of silicon oxide with a film thickness of approximately 1.5 nm is selectively formed on top of the semiconductor substrate130, and a gate electrode302composed of polysilicon with a film thickness of approximately 100 nm is selectively formed on top of the gate insulator film301. Although the gate insulator film301is composed of silicon oxide here, the gate insulator film301may be a high-K insulator film composed of silicon oxynitride (SiON), hafnium oxide (HfOx), hafnium-silicon-oxynitride (HfSiON), or other substances. Further, instead of being composed of polysilicon, the gate electrode302may be composed of a metal gate, a film stack of polysilicon and a metal gate, silicide-topped polysilicon, or fully silicided polysilicon.

Next, as shown inFIG.11D, an insulator film composed of silicon oxide with a film thickness of approximately 8 nm is deposited, and then the offset spacers309aand309bare formed by anisotropic etching on both side surfaces of the gate electrode302and the gate insulator film301with a finish thickness of approximately 4 nm. Although the offset spacers309aand309bare composed of silicon oxide here, the offset spacers309aand309bmay be high-K insulator films composed of silicon nitride (SiN), HfO2, or other substances.

Next, as shown inFIG.11E, an N-type impurity, e.g. phosphorus (P) ions, is implanted into the semiconductor substrate130with an implantation energy of approximately 40 keV and in an implantation dose amount of approximately 2×1013/cm2with the offset spacer309aand309band the gate electrode302as masks. Then, N-type pocket impurity-implanted layers307Aa and307Ab are formed by angularly implanting an N-type impurity, e.g. arsenic (As) ions, with an implantation energy of approximately 80 keV and in an implantation dose amount of approximately 1×1013/cm2. Implanting arsenic, which is heavy in mass number, first causes implantation damage that brings about an effect of suppressing a channeling tail. Note, however, that the P ions and the As ions may be implanted in any order.

In this example, both the P ions and the As ions are implanted into the n-type pocket impurity-implanted layers307Aa and307Ab. Note, however, that only either the P ions or the As ions may be implanted into the n-type pocket impurity-implanted layers307Aa and307Ab.

Next, as shown inFIG.12A, amorphous layers310aand310bare selectively formed in the semiconductor substrate130by implanting germanium (Ge) ions into the semiconductor substrate130with an implantation energy of approximately 10 keV and in an implantation dose amount of approximately 5×1014/cm2with the offset spacer309aand309band the gate electrode302as masks.

Although the amorphous layers310aand310bare formed of germanium here, they may be formed of silicon (Si), argon (Ar), krypton (Kr), xenon (Xe), carbon (C), or other substances.

Next, as shown inFIG.12B, with the amorphous layers310aand310bformed, carbon-implanted layers311Aa and311Ab are formed by implanting carbon (C) ions into the semiconductor substrate130with an implantation energy of approximately 5 keV and in an implantation dose amount of approximately 1×1015/cm2with the offset spacer309aand309band the gate electrode302as masks. It should be noted that the carbon ions need only be implanted, for example, with the implantation energy falling within a range of 1 keV to 10 keV and with the implantation dose amount falling within a range of 1×1014/cm2to 3×1015/cm2. At this point in time, molecular ions of carbon-containing molecules such as C5H5or C7H7may be used instead of the carbon ions. Further, nitrogen ions, fluorine ions, or other ions may be used instead of the carbon ions, which are impurity ions for use in the prevention of diffusion. Further, in a case where carbon or carbon-containing molecular ions are used instead of germanium in the formation of the amorphous layers310aand310b, the step of forming the amorphous layers310aand310band the step of forming the carbon-implanted layers311Aa and311Ab may be executed simultaneously. Further, the semiconductor substrate130may be amorphized during pocket implantation by using ions with a comparatively large mass number, such as antimony (Sb), in n-type pocket impurity implantation.

Next, as shown inFIG.12C, first p-type impurity-implanted layers306Aa and306Ab are formed on top of the carbon-implanted layers311Aa and311Ab by implanting a p-type impurity, e.g. boron (B) ions, into the semiconductor substrate130with an implantation energy of approximately 0.5 keV and in an implantation dose amount of approximately 8×1014/cm2with the offset spacer309aand309band the gate electrode302as masks. Instead of boron, boron difluoride (BF2), boron clusters such as B18Hxor B10Hx, or indium (In) may be used.

FIGS.14A and14Bare graphs showing impurity concentration profiles in regions along a straight line passing through the extension formation regions according toFIGS.5A and5Band extending in a direction parallel with the depth of the semiconductor substrate130. The extension formation regions here are regions in which the extension diffusion layers306aand306bare to be formed or have been formed.FIG.14Ashows, on a log scale, concentration distributions (impurity profiles) of impurities (boron (B), carbon (C), and germanium (Ge)) immediately after boron ion implantation in a direction parallel with the depth of the semiconductor substrate130. As shown inFIG.14A, the amorphous layers310aand310bare approximately 30 nm deep under the condition of implantation of germanium according to the present manufacturing method example.

Next, the semiconductor substrate130is subjected to second rapid thermal processing that heats the substrate to a temperature of 1200° C. to 1350° C., for example, by laser annealing and keeps the substrate near the peak temperature for approximately 1 ms. As shown inFIG.12D, this second rapid thermal processing causes the first extension diffusion layers306aand306band the first pocket diffusion layers307aand307b, which are n-type pocket diffusion layers, to be formed in regions in the semiconductor substrate130lateral to the gate electrode302, respectively. The first extension diffusion layers306aand306bare diffusion layers having boron ions diffused therein and have comparatively shallow junction planes. The first pocket diffusion layers307aand307bare diffusion layers having diffused therein phosphorus ions and arsenic ions contained in the n-type pocket impurity-implanted layers307Aa and307Ab. Although laser annealing is used in the second rapid thermal processing, which is on the millisecond time scale, here, a so-called millisecond annealing (MSA) method such as flash lamp annealing may be used. Furthermore, the second rapid thermal processing may involve the use of annealing that heats the semiconductor substrate130to a temperature of approximately 850° C. to 1050° C. at a temperature rise rate of approximately 200° C./sec and keeps the peak temperature for a maximum of approximately ten seconds or does not keep the peak temperature, e.g. low-temperature spike-RTA.

FIG.14Bshows, on a log scale, concentrations distributions of impurities (B, C, and Ge) in the first extension diffusion layers306aand306b, which are p-type extension high-concentration diffusion layers formed by the second rapid thermal processing, in a direction parallel with the depth of the semiconductor substrate130. After the second rapid thermal processing has been executed, the amorphous layers310aand310b, formed during germanium ion implantation, recover to crystal layers. Boron is diffused to have a peak at a slightly greater depth than it does immediately after ion implantation. Carbon has a first peak composed of a carbon cluster near a concentration peak position during ion implantation, and also has a segregated second peak near the original amorphous/crystal (a/c) interface. Germanium has almost the same concentration distribution as it does immediately after ion implantation.

The concept “pre-amorphization” is explained here. Let it be assumed that amorphization of a certain region in a semiconductor substrate and implantation into that region of an impurity having a polarity, i.e. a conductivity type, (e.g. implantation of B ions or other ions) are executed. In this case, it is conceivable that the amorphization and the impurity implantation may be executed in this order. In this case, the amorphization may be referred to as “pre-amorphization”. Doing ion implantation after amorphizing a substrate causes channeling during the ion implantation to be suppressed, so that a shallow implantation distribution may be formed. Specifically, an implantation distribution whose so-called tailing is small may be formed. Then, executing annealing later effects solid-phase epitaxial regrowth by which an amorphous layer recovers to a crystal layer, bringing about a high activation rate of an impurity and a shallow junction depth. In the present manufacturing method example, it can be said that pre-amorphization preceding B ion implantation for forming the first extension diffusion layers306aand306bis done.

Next, a first insulator film composed of silicon oxide with a film thickness of approximately 10 nm and a second insulator film composed of silicon nitride with a film thickness of approximately 40 nm are sequentially deposited all over the surface of the semiconductor substrate130including the offset spacers309aand309band the gate electrode302, for example, by a chemical vapor deposition (CVD) method. After that, the first and second insulator films thus deposited are subjected to anisotropic etching, whereby as shown inFIG.13A, the first side walls308Aa and308Ab are formed from the first insulator film and the second side walls308Ba and308Bb are formed from the second insulator film over side surfaces of the gate electrode302in a direction parallel with a gate length. Note here that the second side walls308Ba and308Bb may be composed of silicon oxide instead of silicon nitride or, furthermore, may be formed by a film stack composed of silicon oxide and silicon nitride.

Next, as shown inFIG.13B, second p-type impurity-implanted layers313Aa and313Ab are formed by implanting a p-type impurity, i.e. boron ions, into the semiconductor substrate130with an implantation energy of approximately 3 keV and in an implantation dose amount of approximately 3×1015/cm2with the gate electrode302, the offset spacers309aand309b, the first side walls308Aa and308Ab, and the second side walls308Ba and308Bb as masks.

Next, as shown inFIG.13C, the semiconductor substrate130is subjected to third rapid thermal processing that heats the substrate to a temperature of 1200° C. to 1350° C., for example, by laser annealing and keeps the substrate near the peak temperature for approximately 1 ms. This third rapid thermal processing causes the p-type source diffusion layer313aand the p-type drain diffusion layer313b, which are p-type high-concentration impurity diffused layers, to be formed in regions in the semiconductor substrate130lateral to the first side walls308Aa and308Ab and the second side walls308Ba and308Bb. The p-type source diffusion layer313aand the p-type drain diffusion layer313bare diffusion layers having boron ions diffused therein, are connected to the first extension diffusion layers306aand306b, and have deeper junction planes than the first extension diffusion layers306aand306b. Although laser annealing is used in the millisecond rapid thermal processing here, a so-called millisecond annealing (MSA) method such as flash lamp annealing may be used. Further, the third rapid thermal processing may involve the use of annealing that raises the temperature to approximately 850° C. to 1050° C. at a temperature rise rate of approximately 200° C./sec to 250° C./sec and keeps the peak temperature for a maximum of approximately ten seconds or does not keep the peak temperature, e.g. spike-RTA.

The second rapid thermal processing, which is shown inFIG.12D, may be omitted. In that case, the third rapid thermal processing also serves as the second rapid thermal processing.

Thus, according to the present manufacturing method example, before ion implantation for use in the formation of extension diffusion layers is executed with low energy in the step of forming the first p-type impurity-implanted layers306Aa and306Ab as shown inFIG.12C, the semiconductor substrate130is amorphized by germanium in the step shown inFIG.12Aand then carbon is implanted as an impurity for use in the prevention of diffusion in the step shown inFIG.12B. Carbon has an effect of suppressing transient enhanced diffusion (TED) of impurity atoms. Carbon is effective in the formation of the respective shallow diffusion layers of a p-type field-effect transistor (pFET) and an n-type field-effect transistor (nFET), as carbon greatly suppresses the diffusion of boron and phosphorus.

As mentioned above, in the p-type first extension diffusion layers306aand306b, indium (In) may be diffused instead of or in combination with boron (B). Further, in a case where n-type first extension diffusion layers306aand306bare employed, phosphorus may be diffused. Carbon is effective in the formation of the respective shallow diffusion layers of a p-type field-effect transistor (pFET) and an n-type field-effect transistor (nFET), as carbon greatly suppresses the diffusion of boron and phosphorus.

Co-implanting carbon into the regions of formation of the first extension diffusion layers306aand306b, carbon may eliminate enhanced point defects in the semiconductor substrate130during heat treatment. This may reduce enhanced point defects introduced by ion implantation. This is advantageous from the point of view of suppressing TED of impurities to keep the junction depth of each diffusion layer shallow. This action is useful especially in the case of impurities such as boron and phosphorus.

It can be understood from the foregoing description that implanting carbon makes it possible to form low-resistance first extension diffusion layers306aand306bwith shallow junctions, reduced junction leaks, and suppressed increases in value of resistance due to dose loss.

As noted above, heat treatment for heating the pixel region R1is executed, and the first peripheral region R2may be heated too by that heat treatment. However, even in a case where such heat treatment is executed, a diffusion-suppressing effect based on carbon implantation and an associated effect are brought about.

In one specific example, an interlayer film is deposited in both the pixel region R1and the first peripheral region R2after the activation thermal processing ofFIG.13C. The interlayer film is for example an NSG (non-doped silicate glass) film. Next, an opening is formed in the interlayer film in the pixel region R1. After the formation of the opening, implantation of, for example, a impurity region that constitutes the charge accumulation region Z may be executed in the pixel region R1. Next, open plug portions are embedded in the pixel region R1by depositing polysilicon so that the opening is filled. The polysilicon may be doped with phosphorus. Next, the pixel region R1, including the plug portions, is subjected to heat treatment. This heat treatment is executed, for example, for approximately ten minutes at 700° C. to 850° C. This heat treatment causes the first peripheral region R2to be heated too. However, in the first peripheral region R2, the diffusion-suppressing effect based on carbon implantation suppresses the redistribution of the impurity, making it possible to maintain the shallow junction.

Even with attention focused only on the manufacture of the first peripheral transistor27of the first peripheral region R2, the diffusion-suppressing effect based on carbon implantation is effective. Furthermore, as noted above, even in a case where the first peripheral region R2is heated by an additional step of heat treatment for heating the pixel region R1, the diffusion-suppressing effect based on carbon implantation may be exerted.

It should be noted that only phosphorus (P) may be used in the first pocket diffusion layers307aand307b, which are N-type pocket diffusion layers. Using phosphorus is more effective in preventing the diffusion of carbon ions than using arsenic (As).

Amorphization may occur during implantation of arsenic for the first pocket diffusion layers307aand307b. For example, such a phenomenon tends to occur in a case where the implantation dose amount of arsenic is larger than or equal to 5×1013/cm2.

Method for Manufacturing First Peripheral Transistor According to Second Configuration Example

The following describes, with reference toFIGS.15A to15C, a method for manufacturing a first peripheral transistor27according to the second configuration example shown inFIGS.6A and6B.FIGS.15A to15Care cross-sectional views showing the method for manufacturing a first peripheral transistor27according to the second configuration example. A description of configurations that the second configuration example has in common with the first configuration example may be omitted.

In a case where a first peripheral transistor27according to the second configuration example is manufactured, as described with reference toFIG.10A, silicon (Si) is epitaxially grown over a supporting substrate140. As a result of this, a first epitaxial layer135is formed over the supporting substrate140. Note, however, that the subsequent steps described with reference toFIG.10B to10Dare omitted. That is, the formation of a recessed portion135c, the formation of a second epitaxial layer136, and the formation of a third epitaxial layer137are not performed. On the structure in which the first epitaxial layer135is formed over the supporting substrate140, the steps described with reference toFIGS.11A to13Aare executed. As a result of this, a structure shown inFIG.15Ais obtained.

In the structure shown inFIG.15A, the first epitaxial layer135includes the N-type channel diffusion layer303, the first extension diffusion layers306aand306b, and the first pocket diffusion layers307aand307b. The first side walls308Aa and308Ab, and the second side walls308Ba and308Bb are provided over the first epitaxial layer135.

Next, as shown inFIG.15B, regions of the first epitaxial layer135lateral to the first side walls308Aa and308Ab, and the second side walls308Ba and308Bb are recessed, whereby a first recessed portion133and a second recessed portion134are formed. Specifically, the first recessed portion133and the second recessed portion134are formed by anisotropic etching or other processes. More specifically, the first recessed portion133and the second recessed portion134are formed by anisotropic etching or other processes with the gate electrode302, the offset spacers309aand309b, the first side walls308Aa and308Ab, and the second side walls308Ba and308Bb as masks.

Next, as shown inFIG.15C, silicon germanium (SiGe) is subjected to in-situ-dope epitaxial growth in the first recessed portion133and the second recessed portion134. In this example, the in-situ-dope epitaxial growth involves the use of boron as an impurity. As a result of this, a fourth epitaxial layer138is formed over the first recessed portion133. Further, the p-type source diffusion layer313ais formed of the fourth epitaxial layer138. A fifth epitaxial layer139is formed over the second recessed portion134. Further, the p-type drain diffusion layer313bis formed of the fifth epitaxial layer139.

The carbon-implanted layers311shown inFIG.6Bmay be formed at any timing. This timing may precedes the formation of the first recessed portion133and the second recessed portion134shown inFIG.15Bor may follow the formation of the first recessed portion133and the second recessed portion134.

As mentioned above with reference toFIG.6D, the fourth epitaxial layer138has an embedded portion138cand a raised portion138r. The fifth epitaxial layer139has an embedded portion139eand a raised portion139r. The embedded portion138eand the embedded portion139econstitute an eSiGe (embedded SiGe) layer. The raised portion138rand the raised portion139rconstitute an rSiGe (raised SiGe) layer.

When silicon germanium of the fourth epitaxial layer138is denoted by Si1-xGex, X is larger than 0 and smaller than 1. In one example, X is greater than or equal to 0.1 and less than or equal to 0.8. In one specific example, X is greater than or equal to 0.1 and less than or equal to 0.65.

When silicon germanium of the fifth epitaxial layer139is denoted by Si1-xGex, X is larger than 0 and smaller than 1. In one example, X is greater than or equal to 0.1 and less than or equal to 0.8. In one specific example, X is greater than or equal to 0.1 and less than or equal to 0.65.

In this example, a first combination of the embedded portion138eand the raised portion138rand a second combination of the embedded portion139eand the raised portion139rare formed. The N-type channel diffusion layer303is pushed in from the first combination and the second combination. This causes a compression strain on the N-type channel diffusion layer303. The compression strain brings about improvement in hole mobility. This may improve the driving force of the first peripheral transistor27and increase the speed of operation of the first peripheral transistor27.

The raised portion138rand the raised portion139rmay not be formed. In this case, N-type channel diffusion layer303is pushed in from the embedded portion138eand the embedded portion139e. This causes a compression strain on the N-type channel diffusion layer303.

The embedded portion138eand the embedded portion139emay not be formed. In this case, the N-type channel diffusion layer303suffers from a compression strain based on the difference in lattice constant between a SiGe layer constituting the raised portion138rand the raised portion139rand a Si layer constituting the first epitaxial layer135.

As can be understood from the foregoing description, in the first configuration example, the N-type channel diffusion layer303has a cSiGe layer. In the second configuration example, the p-type source diffusion layer313ais formed of at least one selected from the group consisting of eSiGe and rSiGe, and the p-type drain diffusion layer313bis formed of at least one selected from the group consisting of eSiGe and rSiGe.

The first configuration example and the second configuration example may be combined. Specifically, the N-type-channel diffusion layer303may have a cSiGe layer, the p-type source diffusion layer313amay be formed of at least one selected from the group consisting of eSiGe and rSiGe, and the p-type drain diffusion layer313bmay be formed of at least one selected from the group consisting of eSiGe and rSiGe.

A transistor according to the present disclosure and a method for manufacturing the same can achieve reductions in junction depth and resistance of an extension diffusion layer along with miniaturization, and are effective in a MIS transistor having high driving force and a method for manufacturing the same.

Transistors of Pixel Region R1and First Peripheral Region R2

The following further describes the transistors of the pixel region R1and the first peripheral region R2with reference toFIGS.16to27.FIGS.16,17,19,20,21,22,24, and25are schematic plan views illustrating transistors of pixel regions and transistors of peripheral regions.FIGS.18,23,26, and27illustrate schematic cross-sectional views showing transistors of pixel regions and transistors of peripheral regions. It should be noted thatFIGS.16to27omit to illustrate the blocking regions200A and200B.

In the following, the previously-used terms are sometimes replaced by different terms. For example, one of the p-type source diffusion layer313aand the p-type drain diffusion layer313bis sometimes referred to as “source”, and the other as “drain”. The N-type channel diffusion layer303is sometimes referred to as “channel region”. Note, however, that the following source may be referred to as “source diffusion layer”, the drain as “drain diffusion layer”, and the channel region as “channel diffusion layer”. It should be noted that the channel region may include part or the whole of a pocket diffusion layer.

In the following, the source of the first peripheral transistor27is sometimes referred to as “first source”. The drain of the first peripheral transistor27is sometimes referred to as “first drain”. The channel region of the first peripheral transistor27is sometimes referred to as “first channel region”.

As shown inFIGS.21and22, the imaging device may include a second peripheral region R3. In each of the examples shown inFIGS.21and22, the second peripheral region R3is located between the pixel region R1and the first peripheral region R2in a plan view.

One semiconductor substrate130may spread over both the pixel region R1and the first peripheral region R2, or the pixel region R1may be constituted using one semiconductor substrate and the first peripheral region R2may be constituted using another semiconductor substrate. One semiconductor substrate130may spread astride three regions, namely the pixel region R1, the first peripheral region R2, and the second peripheral region R3, or the pixel region R1may be constituted using one semiconductor substrate, the first peripheral region R2may be constituted using another semiconductor substrate, and the second peripheral region R3may be constituted using still another semiconductor substrate. One semiconductor substrate130may spread astride the pixel region R1and the first peripheral region R2, and the second peripheral region R3may be constituted using another semiconductor substrate. Further, the pixel region R1may be constituted using one semiconductor substrate, and one semiconductor substrate130may spread astride the first peripheral region R2and the second peripheral region R3. Thus, the imaging device may have at least one semiconductor substrate.

In the following, the terms “pixel substrate portion”, “first peripheral substrate portion”, and “second peripheral substrate portion” are sometimes used. The term “pixel substrate portion” refers to a portion of at least one semiconductor substrate130that belongs to the pixel region R1. The term “first peripheral substrate portion” refers to a portion of at least one semiconductor substrate130that belongs to the first peripheral region R2. The term “second peripheral substrate portion” refers to a portion of at least one semiconductor substrate130that belongs to the second peripheral region R3.

The pixel substrate portion may be referred to specifically as “pixel semiconductor substrate portion”. The first peripheral substrate portion may be referred to specifically as “first semiconductor substrate portion”. The second peripheral substrate portion may be referred to specifically as “second semiconductor substrate portion”.

The term “pixel transistor” is described. A pixel transistor is a transistor that the pixel region R1has. For example, an amplifying transistor22, an address transistor24, and a reset transistor26may fall under the category of pixel transistors.FIGS.16to33illustrate an amplifying transistor22as a pixel transistor. Further, the following describes a case where a pixel transistor is an amplifying transistor22. Note, however, that unless otherwise noted, the term “amplifying transistor22” can be read as “pixel transistor, “address transistor24”, or “reset transistor26” in the following description. Elements, such as a source and a drain, that a transistor has and elements, such as wires, associated with a transistor may be read as appropriate. In these respects, the same applies toFIGS.35to48B.

The gate insulator film of a pixel transistor may be referred to as “pixel gate insulator film”. The gate insulator film of a first peripheral transistor may be referred to as “first peripheral gate insulator film”. The gate insulator film of a second peripheral transistor may be referred to as “second peripheral gate insulator film”.

FIG.16schematically shows an amplifying transistor22in the pixel region R1and a first peripheral transistor27in the first peripheral region R2in a case where the configuration ofFIG.1is adopted.FIG.17schematically shows an amplifying transistor22in the pixel region R1and a first peripheral transistor27in the first peripheral region R2in a case where the configuration ofFIG.4is adopted.

In each of the examples shown inFIGS.16and17, the first peripheral region R2is located outside the pixel region R1. Specifically, the first peripheral region R2is located outside the pixel region R1in a plan view.

The first peripheral region R2may be provided with elements such as an image signal processor (ISP) and a memory. In the first peripheral region R2, elements such as an ISP and a memory may be stacked in multiple layers.

FIG.18shows configurations that the amplifying transistor22in the pixel region R1and the first peripheral transistor27in the first peripheral region R2may have in each of the examples shown inFIGS.16and17. In the example shown inFIG.18, the amplifying transistor22is an N-channel MOSFET, and the first peripheral transistor27is a P-channel MOSFET. Note, however, that as mentioned above, these transistors are not limited to particular conductivity types. In this respect, the same applies to the after-mentioned first and second peripheral transistors427,727, and827.

In the example shown inFIG.18, the first peripheral transistor27is similar to that described with reference toFIGS.5A and5B.FIG.18omits to illustrate the first epitaxial layer135, the second epitaxial layer136, and the third epitaxial layer137. Note, however, that in the example shown inFIG.18, another transistor may be employed instead of the first peripheral transistor27ofFIGS.5A and5B. For example, the transistor described with reference toFIGS.6A to6Dmay be employed. Further, the transistor according to the modification described with reference toFIG.7,8, or9may be employed. In these respects, the same applies to the examples shown inFIGS.23,26, and27or other drawings.

In the example shown inFIG.18, a contact plug cp is connected to the p-type source diffusion layer313a, which serves as the first source of the first peripheral transistor27. A contact plug cp is connected to the p-type drain diffusion layer313b, which serves as the first drain of the first peripheral transistor27. A contact plug cp is connected to the gate electrode302of the first peripheral transistor27.

In one example, the contact plugs cp are metal plugs. Examples of metal that the contact plugs cp may contain include tungsten and copper.

In the example shown inFIG.18, the amplifying transistor22has a source67a, a drain67b, and a gate electrode67c. The source67ais an n-type impurity region. The drain67bis an n-type impurity region. The gate electrode67cis made, for example, of a polysilicon material.

A channel region68is formed between the source67aand the drain67b. The channel region68is an n-type impurity region.

A gate insulator film69is formed between the gate electrode67cand the pixel substrate portion. Specifically, the gate insulator film69is an oxide film. In one example, the gate insulator film69contains silicon oxide, and in one specific example, the gate insulator film69contains silicon dioxide.

An offset spacer70is formed over the gate electrode67cand the gate insulator film69. In one example, the offset spacer70contains silicon oxide, and in one specific example, the offset spacer70contains silicon dioxide.

A first side wall71ais formed on a portion of the offset spacer70beside the source67a. In the example shown inFIG.18, the first side wall71ahas an L-shaped cross-section. A second side wall72ais formed on an outer side of the first side wall71a.

A first side wall71bis formed on a portion of the offset spacer70beside the drain67b. In the example shown inFIG.18, the first side wall71bhas an L-shaped cross-section. A second side wall72bis formed on an outer side of the first side wall71b.

In one example, the first side wall71acontains silicon oxide, and in one specific example, the first side wall71acontains silicon dioxide. In this respect, the same applies to the first side wall71b. In one example, the second side wall72ahas a stacked structure including a plurality of insulating layers, and in one specific example, the second side wall72aincludes a silicon dioxide layer and a silicon nitride layer. In this respect, the same applies to the second side wall72b.

The offset spacer70has a through-hole formed over the gate electrode67c. A contact plug cx is connected to the gate electrode67cvia the through-hole. The gate insulator film69and the offset spacer70have through-holes formed over the drain67b. A contact plug cx is connected to the drain67bvia the through-holes.

The contact plugs cx are for example polysilicon plugs. The contact plugs cx may be doped with an impurity such as phosphorus for higher electric conductivity.

It should be noted that an embodiment in which a contact plug cx is connected to the source67amay be adopted. Specifically, the gate insulator film69and the offset spacer70have through-holes formed over the source67a, and a contact plug cx is connected to the source67avia the through-holes.

The contact plug cx connected to the gate electrode67cis connected to a plug cy. The contact plug cx connected to the drain67bis connected to a plug cy. In a case where a contact plug cx connected to the source67ais present, the contact plug cx may be connected to a plug cy.

In one example, the plugs cy are metal plugs. Examples of metal that the contact plugs cy may contain include tungsten and copper.

As can be understood from the description with reference toFIGS.1to18, an imaging device according to the present embodiment includes a pixel region R1and a first peripheral region R2. The pixel region R1has a pixel substrate portion. The first peripheral region R2has a first peripheral substrate portion. Signals are transmitted between the pixel region R1and the first peripheral region R2. Specifically, the first peripheral region R2is located outside the pixel region R1. More specifically, the first peripheral region R2is located outside the pixel region R1in a plan view.

The pixel region R1has an amplifying transistor22. The amplifying transistor22is provided in the pixel substrate portion. The first peripheral region R2has a first peripheral transistor27. The first peripheral transistor27is provided in the first peripheral substrate portion. In one example, the first peripheral transistor27is a logic transistor. The first peripheral transistor27may be a planar transistor, or may be a three-dimensional structural transistor. A first example of a three-dimensional structural transistor is a FinFET (fin field-effect transistor). A second example of a three-dimensional structural transistor is a GAA (gate all around) such as a nanowire FET. A third example of a three-dimensional structural transistor is a nanosheet FET.

In the present embodiment, the amplifying transistor22outputs a signal voltage corresponding to signal charge obtained by photoelectric conversion. The photoelectric conversion is carried out in a photoelectric conversion layer12. Specifically, there are provided a path that leads the signal charge from the photoelectric conversion layer12to a charge accumulation region Z and a path that leads the signal charge from the charge accumulation region Z to a gate electrode67cof the amplifying transistor22. In the example shown inFIG.3, the charge accumulation region Z corresponds to an impurity region60n. As mentioned above, the charge accumulation region Z is included in a charge accumulation node FD.

As shown inFIG.18, in the present embodiment, the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22.

The ratio L27/L22of the gate length L27of the first peripheral transistor27to the gate length L22of the amplifying transistor22is for example lower than or equal to 0.8, or may be lower than or equal to 0.34. This ratio is for example higher than or equal to 0.01, or may be higher than or equal to 0.05.

The term “gate length” here refers to a dimension of a gate electrode in a direction from a source to a drain or from the drain to the source. The term “gate width” refers to a dimension of a gate electrode in a direction orthogonal to a direction parallel with a gate length in a plan view. The direction orthogonal to a direction parallel with a gate length in a plan view may also be referred to as “depth direction”.

In the present embodiment, the gate insulator film301of the first peripheral transistor27is thinner than the gate insulator film69of the amplifying transistor22.

The ratio T301/T69of the thickness T301of the gate insulator film301of the first peripheral transistor27to the thickness T69of the gate insulator film69of the amplifying transistor22is for example lower than or equal to 0.7, or may be lower than or equal to 0.36. This ratio is for example higher than or equal to 0.1, or may be higher than or equal to 0.2.

In the present embodiment, the first peripheral transistor27has the p-type source diffusion layer313a, which serves as the first source, the p-type drain diffusion layer313b, which serves as the first drain, and the N-type channel diffusion layer303, which serves as the first channel region, within the first peripheral substrate portion.

The first channel region is located between the first source and the first drain. Further, the first channel region is located in a region including an area under the gate of the first peripheral transistor27. The term “area under the gate of the first peripheral transistor27” refers to a portion of a path of charge between the first source and the first drain that overlaps the gate electrode302in a plan view.

In the present embodiment, the first peripheral transistor27has a first strain-introducing layer within the first peripheral substrate portion. The first strain-introducing layer brings a strain to the N-type channel diffusion layer303, which serves as the first channel region. The strain brings about improvement in the carrier mobility of the first channel region. This configuration is suitable to improving the performance of an imaging device. The strain that the first strain-introducing layer brings to the first channel region may be a compression strain or may be a tensile strain.

For example, the first peripheral substrate portion has a first foundation layer. The first foundation layer is adjacent to the first strain-introducing layer. The first foundation layer is a foundation of the first strain-introducing layer. The lattice constant of a crystal lattice of the first strain-introducing layer and the lattice constant of a crystal lattice of the first foundation layer are different from each other. The first channel region has a strain attributed to this difference. This strain brigs about improvement in the carrier mobility of the first channel region. In a typical example, the first foundation layer is a single-crystal layer of silicon.

In one example, the first foundation layer is the first epitaxial layer135. In another example, the first foundation layer is the supporting substrate140. In still another example, the first foundation layer is a well in the first peripheral substrate portion. This well may or may not be one that the first peripheral substrate portion and the pixel substrate portion share with each other.

Specifically, the first strain-introducing layer and the first foundation layer may be epitaxial layers. Further, the first strain-introducing layer may be thinner than the first foundation layer. A configuration in which the first strain-introducing layer is thin is expected to express a quantum-confined effect.

For example, the first strain-introducing layer is a crystal layer. Specifically, in the crystal layer, a crystal lattice is constituted by atoms or molecules in the layer being regularly and periodically arrayed.

For example, the first strain-introducing layer is a crystal layer of silicon germanium (SiGe), a crystal layer of germanium (Ge), a crystal layer of a Group III-V compound, a crystal layer of silicon carbide (SiC), a crystal layer of transition metal dichalcogenide (TMD), or a crystal layer of carbon nanotubes (CNTs). Examples of Group III-V compounds include InGaAs, InP, GaAs, InAs, InSb, InGaSb, and AlGaSb.

Examples of the first strain-introducing layer in a case where the first peripheral transistor27is a P-channel transistor include a crystal layer of silicon germanium, a crystal layer of germanium, a crystal layer of transition metal dichalcogenide, a crystal layer of carbon nanotubes, and a crystal layer of a Group III-V compound. Examples of the first strain-introducing layer in a case where the first peripheral transistor27is an N-channel transistor include a crystal layer of silicon carbide, a crystal layer of transition metal dichalcogenide, and a crystal layer of carbon nanotubes.

In one specific example, the first strain-introducing layer is a crystal layer of Si1-xGex. X is larger than 0 and smaller than 1. X may be greater than or equal to 0.1 and less than or equal to 0.8. X may be greater than or equal to 0.1 and less than or equal to 0.65.

In the present embodiment, the first strain-introducing layer is a single-crystal layer. Further, the first strain-introducing layer is an epitaxial layer.

In the present embodiment, the conductivity type of the first peripheral transistor27is different from the conductivity type of the amplifying transistor22.

In the first peripheral transistor27according to the first configuration example, the N-type channel diffusion layer303, which serves as the first channel region, includes a first strain-introducing layer.

In one specific example, the first peripheral transistor27according to the first configuration example has the configuration described with reference toFIGS.5A and5B. The first strain-introducing layer is constituted using the second epitaxial layer136. In the first channel region, an interface between the first epitaxial layer135and the second epitaxial layer136is formed. The first epitaxial layer135and the second epitaxial layer136are different in lattice constant from each other. This causes a strain on the first channel region. The strain brings about improvement in carrier mobility. This may improve the driving force of the first peripheral transistor27and increase the speed of operation of the first peripheral transistor27. This brings about improvement in the characteristics of the first peripheral transistor27. Further, this is advantageous from the point of view of reducing the area of the first peripheral region R2.

In the first peripheral transistor27according to the second configuration example, the p-type source diffusion layer313a, which serves as the first source, includes a first strain-introducing layer. The p-type drain diffusion layer313b, which serves as the first drain, includes a first strain-introducing layer. That is, the first peripheral transistor27includes a plurality of the first strain-introducing layers. The first strain-introducing layer included in the first source and the first strain-introducing layer included in the first drain are different from each other.

In one specific example, the first peripheral transistor27according to the second configuration example has the configuration described with reference toFIGS.6A to6D. The first strain-introducing layer included in the first source is constituted using the fourth epitaxial layer138. The first strain-introducing layer included in the first drain is constituted using the fifth epitaxial layer139. The N-type channel diffusion layer303, which serves as the first channel region, is pushed in from the first source and the first drain. This causes a strain on the first channel region. The strain brings about improvement in carrier mobility. This may improve the driving force of the first peripheral transistor27and increase the speed of operation of the first peripheral transistor27. This brings about improvement in the characteristics of the first peripheral transistor27. Further, this is advantageous from the point of view of reducing the area of the first peripheral region R2.

In one example, the first peripheral substrate portion has the supporting substrate140. The first peripheral transistor27has a first cap layer within the first peripheral substrate portion. The supporting substrate140, the first strain-introducing layer, and the first cap layer are arranged in an order from lower to upper parts of the first peripheral transistor27. The first cap layer includes an upper surface of the first peripheral substrate portion. The concentration of a conductive impurity of the first cap layer is lower than the concentration of a conductive impurity of the supporting substrate140. This configuration is suitable to improving the performance of an imaging device. The first cap layer may correspond to the aforementioned third epitaxial layer137.

In the first configuration example and the second configuration example, in a case where the first peripheral transistor27is a P-channel transistor, the carrier mobility in the first channel region may be improved by applying a compression strain to the first channel region. In a case where the first peripheral transistor27is an N-channel transistor, the carrier mobility of the first channel region may be improved by applying a tensile strain to the first channel region.

According to a first definition, the phrase “concentration of the conductive impurity” in the expression “the concentration of the conductive impurity of the first cap layer is lower than the concentration of the conductive impurity of the supporting substrate140” is a maximum value of concentration. According to a second definition, the phrase “concentration of the conductive impurity” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of the conductive impurity of the first cap layer is lower than the concentration of the conductive impurity of the supporting substrate140” is treated as a case where “the concentration of the conductive impurity in the first cap layer is lower than the concentration of the conductive impurity in the supporting substrate140”.

The first cap layer may be the third epitaxial layer137described with reference toFIGS.5A and5B. The first cap layer may be a single-crystal layer. The first cap layer may be a non-doped epitaxial layer. Note here that the term “non-doped” means that the concentration of an impurity is lower than 5×1016atoms/cm3.

In one example, the first peripheral transistor27has a first specific layer. The first specific layer is located within the first peripheral substrate portion.

Note here that at least one type of impurity that suppresses transient enhanced diffusion of a conductive impurity is defined as “diffusion-suppressing species”. In the present embodiment, the first specific layer contains a diffusion-suppressing species. This configuration is suitable to improving the performance of an imaging device. Specifically, this configuration is suitable to improving the performance of the imaging device in consideration of the presence of the first peripheral transistor27in the first peripheral region R2. The diffusion-suppressing species may contain at least one selected from the group consisting of carbon, nitrogen, and fluorine.

Note here that at least one type of impurity that induces amorphization of a region into which the at least one type of impurity has been implanted is defined as “amorphizing species”. In the present embodiment, the first specific layer contains an amorphizing species. This configuration is suitable to improving the performance of an imaging device. Specifically, this configuration is suitable to improving the performance of the imaging device in consideration of the presence of the first peripheral transistor27in the first peripheral region R2. The amorphizing species may contain at least one selected from the group consisting of germanium, silicon, and argon. The amorphizing species may be a trace of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon.

In one example, at least either the first source or the first drain may include the first specific layer.

In one example, the first channel region may include the first specific layer.

In one example, the first peripheral transistor27has first extension diffusion layers306aand306b. The first extension diffusion layers306aand306bare adjacent to the first source or the first drain. The first extension diffusion layers306aand306bare shallower than the first source and the first drain. The first extension diffusion layers306aand306binclude the first specific layer.

The expression “an extension layer and a source are adjacent to each other” specifically means that the extension diffusion layer and the source are connected to each other. The same applies to similar expressions such as the expression “an extension diffusion layer and a drain are adjacent to each other”, the expression “a pocket diffusion layer and a source are adjacent to each other”, and the expression “a pocket diffusion layer and a drain are adjacent to each other”, each of which specifically means that those elements are connected to each other.

The sentence “the first extension diffusion layers306aand306bare shallower than the first source and the first drain” means that the deepest portions of the first extension diffusion layers306aand306bare at a shallower depth than the deepest portions of the first source and the first drain in a direction parallel with the depth of the first peripheral substrate portion. In this context, the word “shallow” can also be referred to as “shallow in junction depth”. Boundaries of an extension diffusion layer, a source, and a drain are junctions. A junction is a place where the concentration of an n-type impurity and the concentration of a p-type impurity are equal to each other.

The expression “the first extension diffusion layers306aand306binclude the first specific layer” is intended to encompass an embodiment in which the first specific layer falls within the first extension diffusion layers306aand306band an embodiment in which the first specific layer protrudes from the first extension diffusion layers306aand306b. The same applies to similar expressions such as the expression “the first pocket diffusion layers307aand307binclude the first specific layer”.

In the illustrated example, the first peripheral transistor27has the first extension diffusion layer306aand the first extension diffusion layer306b. The first extension diffusion layer306ais adjacent to the first source. The first extension diffusion layer306ais shallower than the first source and the first drain. The first extension diffusion layer306bis adjacent to the first drain. The first extension diffusion layer306bis shallower than the first source and the first drain. The first extension diffusion layer306aand the first extension diffusion layer306bmay include the first specific layer.

In one example, the first peripheral transistor27has the first pocket diffusion layers307aand307b. The first pocket diffusion layers307aand307bare adjacent to the first source or the first drain. The first pocket diffusion layers307aand307bmay include the first specific layer.

In the illustrated example, the first peripheral transistor27has the first pocket diffusion layer307aand the first pocket diffusion layer307b. The first pocket diffusion layer307ais adjacent to the first source. The first pocket diffusion layer307bis adjacent to the first drain. The first pocket diffusion layer307aand the first pocket diffusion layer307bmay include the first specific layer.

Only one selected from among the first channel region, the first source, the first drain, the first extension diffusion layers, and the first pocket diffusion layers may include the first specific layer. Specifically, only one selected from among the first channel region, the first source, the first drain, the first extension diffusion layer306a, the first extension diffusion layer306b, the first pocket diffusion layer307a, and the first pocket diffusion layer307bmay include the first specific layer.

Two or more selected from among the first channel region, the first source, the first drain, the first extension diffusion layers, and the first pocket diffusion layers may include the first specific layer. Specifically, two or more selected from among the first channel region, the first source, the first drain, the first extension diffusion layer306a, the first extension diffusion layer306b, the first pocket diffusion layer307a, and the first pocket diffusion layer307bmay include the first specific layer. In a case where these selected two or more include the first specific layer, these may include the same or different types of first specific layer. For example, the diffusion-suppressing species of the first source may be carbon, and the diffusion-suppressing species of the first extension diffusion layers306aand306bmay be nitrogen and fluorine. Further, in this case, these may include the same or different conductivity types of conductive impurity. For example, either the first source or the first pocket diffusion layers307aand307bmay contain boron whose conductivity type is a p type, and the other may contain phosphorus whose conductivity type is an n type.

As can be understood from the foregoing description, the imaging device may have one or more first specific layers.

Examples of the position of a first specific layer are further described.

As mentioned above, in the first configuration example, the first channel region includes a first strain-introducing layer. In one specific example of the first configuration example, at least one selected from among a configuration (a) and a configuration (b) holds.

In the configuration (a), the first pocket diffusion layers307aand307binclude the first specific layer. In the configuration (b), regions between the first pocket diffusion layers307aand307band the first strain-introducing layer include the first specific layer.

According to the configuration (a) and/or the configuration (b), possible diffusion of a conductive impurity by TED in directions from the first pocket diffusion layers307aand307btoward the first channel region can be suppressed. It should be noted that the regions between the first pocket diffusion layers307aand307band the first strain-introducing layer are for example the first extension diffusion layers306aand306b. Specific examples of regions in which the first specific layer may be distributed in the configuration (a) and the configuration (b) are regions that are similar to the regions of the carbon-implanted layers311ofFIG.5B.

As mentioned above, in the second configuration example, the first source includes a first strain-introducing layer. The first drain includes a first strain-introducing layer. In one specific example of the second configuration example, the first peripheral substrate portion has a first foundation layer. At least one selected from among a configuration (c) and a configuration (d) holds.

In the configuration (c), there is a first interface between the first foundation layer and the first strain-introducing layer included in the first source. A conductive impurity of the first source spreads in a first region of the first foundation layer astride the first interface. The first region includes the first specific layer.

In the configuration (d), there is a second interface between the first foundation layer and the first strain-introducing layer included in the first drain. A conductive impurity of the first drain spreads in a second region of the first foundation layer astride the second interface. In the configuration (d), the second region includes the first specific layer.

According to the configuration (c), even in a situation where a conductive impurity spreads in the first region of the first foundation layer astride the first interface from the first strain-introducing layer included in the first source, diffusion of the conductive impurity by TED in the first foundation layer can be suppressed. According to the configuration (d), even in a situation where a conductive impurity spreads in the second region of the first foundation layer astride the second interface from the first strain-introducing layer included in the first drain, diffusion of the conductive impurity by TED in the first foundation layer can be suppressed. This may suppress the short channel effect and reduce deterioration of the performance of the first peripheral transistor27. Specific examples of regions in which the first specific layer may be distributed in the configuration (c) and the configuration (d) are regions that are similar to the regions of the carbon-implanted layers311ofFIG.6B.

The following describes an example of a situation in which a technique involving the use of a first specific layer may contribute to such improvement in performance as that noted above.

In the process of manufacturing the imaging device, heat treatment may be executed. The heat treatment may reduce detects in the pixel substrate portion in the pixel region R1. Reducing defects may reduce dark current in the imaging device. Meanwhile, in the first peripheral region R2, the necessity to reduce defects is not necessarily great. On the contrary, in the first peripheral region R2, there is a case where it is necessary to reduce deterioration in performance of the first peripheral transistor27attributed to the diffusion of the conductive impurity entailed by the heat treatment. The deterioration in performance is for example an undesirable change in threshold voltage of the first peripheral transistor27.

In particular, in the present embodiment, the first peripheral transistor27includes at least either a first feature or a second feature. The first feature is such a feature that the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. The second feature is such a feature that the gate insulator film301of the first peripheral transistor27is thinner than the gate insulator film69of the amplifying transistor22. In a case where the first peripheral transistor27includes at least either the first feature or the second feature, the performance of the first peripheral transistor27is susceptible to diffusion redistribution of the conductive impurity due to thermal processing.

Specifically, let thought be given to a first example in which the first specific layer is included in the first extension diffusion layers306aand306band the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. In the process of manufacturing the imaging device, heat treatment may be executed. The heat treatment may reduce detects in the pixel substrate portion in the pixel region R1. Reducing defects may reduce dark current in the imaging device. Meanwhile, in a case where L27<L22, the heating more easily exert a short channel effect in the first peripheral transistor27than in the amplifying transistor22. The short channel effect may change the threshold voltage of a transistor from a desired value and invite a decrease in performance of the transistor. Thus, the heat treatment may bring about an advantage in that dark current is reduced in the pixel region R1and, on the other hand, bring about an disadvantage in that the short channel effect becomes obvious in the first peripheral region R2.

In this respect, in the first example, the first extension diffusion layers306aand306bcontain the conductive impurity and the diffusion-suppressing species. The diffusion-suppressing species may contribute to the suppression of the diffusion of the conductive impurity. This diffusion-suppressing action may suppress the short channel effect in the first peripheral transistor27. This makes it possible to, while enjoying the aforementioned advantage called “dark-current reduction”, mitigate the aforementioned disadvantage called “short channel effect”.

As noted above, in the first example, the diffusion-suppressing action expressed in the first extension diffusion layers306aand306bsuppresses the short channel effect of the first peripheral transistor27attributed to thermal processing. This means that a margin of a thermal budget of thermal processing becomes wider than in the absence of the diffusion-suppressing action. Therefore, increasing the duration, temperature, or other conditions of thermal processing makes it possible to reduce dark current in the pixel region R1without making the short channel effect obvious in the first peripheral transistor27.

Let thought be given to a second example in which the first specific layer is included in at least either the first source or the first drain and the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. In the second example too, as in the case of the first example, increasing the duration, temperature, or other conditions of thermal processing makes it possible to reduce dark current in the pixel region R1without making the short channel effect obvious in the first peripheral transistor27.

Let thought be given to a third example in which the first specific layer is included in the first pocket diffusion layers307aand307band the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. In the third example, variations in the threshold voltage of the first peripheral transistor27may be reduced by the diffusion-suppressing action expressed in the first pocket diffusion layers307aand307b. For this reason, according to the third example, as in the case of the first example, increasing the duration, temperature, or other conditions of thermal processing makes it possible to reduce dark current in the pixel region R1without making the variations in the threshold voltage of the first peripheral transistor27obvious.

Let thought be given to a fourth example in which the first specific layer is included in the first channel region and the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. In the fourth example too, as in the case of the first example, increasing the duration, temperature, or other conditions of thermal processing makes it possible to reduce dark current in the pixel region R1without making the short channel effect obvious in the first peripheral transistor27.

As mentioned above, the semiconductor substrate130may be a substrate having a semiconductor layer provided on a surface thereof by epitaxial growth. The same applies to the pixel substrate portion, the first peripheral substrate portion, and the second peripheral substrate portion. In a epitaxial layer, unintended inclusion of carbon is easily reduced. This may contribute to reduction of dark current in the pixel region R1. This also makes it easy to make a difference in concentration of the diffusion-suppressing species, such as carbon, between the pixel region R1and the first peripheral region R2.

As mentioned above, the semiconductor substrate130may be a p-type silicon substrate. Note, however, that the semiconductor substrate130may be an n-type silicon substrate. The same applies to the pixel substrate portion, the first peripheral substrate portion, and the second peripheral substrate portion.

In one example, the photoelectric conversion layer12is stacked over the pixel substrate portion. In a typical example, in a case where a pixel region R1having such a configuration is fabricated, such thermal processing as noted above is executed. For this reason, an imaging device including a pixel region R1having this configuration may enjoy the effect of reducing dark current while reducing the deterioration in performance of the first peripheral transistor27. It should be noted that the concept “the photoelectric conversion layer12is stacked over the pixel substrate portion” encompasses an embodiment in which an element such as an insulating layer is interposed between the photoelectric conversion layer12and the pixel substrate portion. It can also be said that the photoelectric conversion layer12is supported by the pixel substrate portion.

In one example, the pixel substrate portion and the first peripheral substrate portion are included in a single semiconductor substrate130. In an imaging device having such a configuration, the first peripheral region R2is easily heated by heat treatment for heating the pixel region R1. An imaging device having such a configuration easily enjoys the effect of reducing dark current while reducing the deterioration in performance of the first peripheral transistor27. Typically, in an imaging device having such a configuration, the first peripheral region R2is heated simultaneously during heat treatment for heating the pixel region R1.

The photoelectric conversion layer12may be a panchromatic film. Alternatively, the photoelectric conversion layer12may be a film, such as an orthochromatic film, that does not have sensitivity to light in a certain range of wavelengths.

The first source, the first drain, and the first extension diffusion layers306aand306bmay have a conductive impurity of a first conductivity type. On the other hand, the first pocket diffusion layers307aand307band the first channel region may have a conductive impurity of a second conductivity type.

In one specific example, the first peripheral transistor27is a logic transistor. The first peripheral transistor27can perform a digital operation. In such a first peripheral transistor27, priority may be placed on speed. In order for a transistor to operate at high speed, it is advantageous for the transistor to be a fine transistor. Further, from the point of view of securing the transistor high driving force too, it is advantageous for the transistor to be a fine transistor. In this respect, in this specific example, the gate length L27of the first peripheral transistor27is shorter than the gate length L22of the amplifying transistor22. Further, the gate insulator film301of the first peripheral transistor27is thinner than the gate insulator film69of the amplifying transistor22. From the point of view of causing the first peripheral transistor27to operate at high speed and with high driving force, it may be advantageous for the gate length L27to be short and for the gate insulator film301to be thin. This advantage brought by the gate length L27being short and the gate insulator film301being thin may be exerted, for example, in a case where the first peripheral transistor27is a planar transistor. Further, the first peripheral transistor27of this specific example is located, for example, between a controller and a pixel driver.

The first peripheral transistor27performs a digital operation, for example, in the following manner. That is, a signal from the pixel region R1is amplified, for example, via a load cell, a column amplifier, or other devices. The signal thus amplified is converted by an analog-digital (AD) converter. The first peripheral transistor27receives the digital signal thus obtained and performs a digital operation.

In one example, the first specific layer contains germanium. As can be understood from the foregoing description, in the process of manufacturing the first peripheral transistor27, germanium may pre-amorphize the inside of the first peripheral substrate portion. In a pre-amorphized region, the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon is easily enhanced. In this example, germanium may be a trace of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon.

The first specific layer may contain silicon, argon, krypton, or xenon instead of or in addition to germanium. More generally, the first specific layer may contain at least one element selected from the group consisting of germanium, silicon, argon, krypton, and xenon. These elements may be traces of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon.

In one example, the first peripheral transistor27includes an end-of-range (EOR) defect. At least part of the first specific layer is located above the EOR defect and overlaps the EOR detect in a plan view. In this context, the phrase “above the EOR defect” means a side, as seen from the EOR defect, of a surface of the first peripheral substrate portion over which the gate electrode302is provided. As noted above, in a pre-amorphized region in the first peripheral substrate portion, the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon is easily enhanced. As can be understood from the foregoing description, in a case where in the process of manufacturing the first peripheral transistor27, thermal processing is executed with the first peripheral substrate portion in an amorphized state, an EOR defect may be formed in a region directly below the amorphous/crystal (a/c) interface before the thermal processing. In this example, the EOR defect may be a trace of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon. The first specific layer in its entirety may be located above the EOR defect and overlaps the EOR defect in a plan view.

In one example, the first peripheral transistor27includes a first segregated portion in which the diffusion-suppressing species is segregated in a direction parallel with the depth of the first peripheral substrate portion. At least part of the first specific layer is located above the first segregated portion and overlaps the first segregated portion in a plan view. As noted above, in a pre-amorphized region in the first peripheral substrate portion, the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon is easily enhanced. In a case where in the process of manufacturing the first peripheral transistor27, thermal processing is executed with the first peripheral substrate portion in an amorphized state, a first segregated portion may be formed in a region directly below the amorphous/crystal (a/c) interface before the thermal processing. In this example, the first segregated portion may be a trace of pre-amorphization that may enhance the diffusion-suppressing action on the conductive impurity by an impurity exemplified by carbon. The first specific layer in its entirety may be located above the first segregated portion and overlaps the segregated portion in a plan view. In the expression “first segregated portion in which the diffusion-suppressing species is segregated”, the word “segregated” means that the diffusion-suppressing species unevenly distributed, and is not intended to limit the process of forming the first segregated portion.

The first segregated portion is described with reference to a concentration profile serving as a relationship of the concentration of the diffusion-suppressing species with a depth in the first peripheral substrate portion. In a case where the first segregated portion is present, the concentration in the concentration profile takes on a minimal value at a first depth substantially corresponding to the depth of the amorphous/crystal (a/c) interface before thermal processing. The concentration in the concentration profile takes on a maximal value at a second depth that is deeper than the first depth. The first segregated portion refers to a portion of the first peripheral substrate portion that is deeper than the first depth and in which the concentration of the diffusion-suppressing species is higher than the minimal value. In the profile of carbon shown inFIG.14B, the legend “ORIGINAL a/c INTERFACE” substantially corresponds to the first depth, and an upwardly-sticking portion directly below the legend “ORIGINAL a/c INTERFACE” corresponds to the first segregated portion.

In the present embodiment, the pixel region R1includes a charge accumulation region Z. In the charge accumulation region Z, charge generated by photoelectric conversion is accumulated. The charge accumulation region Z is an impurity region. In the example shown inFIG.3, the charge accumulation region Z corresponds to the impurity region60n. Specifically, photoelectric conversion is carried out in the photoelectric converter10, and the charge thus generated is sent to the charge accumulation region Z via a plug cy and a contact plug cx and accumulated in the charge accumulation region Z.

In one example, the first segregated portion is shallower than the charge accumulation region Z. The clause “the first segregated portion is shallower than the charge accumulation region Z” means that the deepest portion of the first segregated portion is at a shallower depth than the deepest portion of the charge accumulation region Z in a direction parallel with the depth of the pixel substrate portion or the first peripheral substrate portion.

In one example, the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z. Carbon in the first specific layer may suppress the diffusion of the conductive impurity. Meanwhile, the presence of carbon in the charge accumulation region Z may cause dark current. Therefore, only a high-performance imaging device can have such a feature that the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z. In the expression “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z”, the concentration of carbon in the charge accumulation region Z may be zero, or may be higher than zero.

Note here that a boundary of the charge accumulation region Z is a junction. As mentioned above, a junction is a place where the concentration of an n-type impurity and the concentration of a p-type impurity are equal to each other.

According to a first definition, the phrase “concentration of carbon” in the expression “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z” is a maximum value of concentration. According to a second definition, the phrase “concentration of carbon” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z” is treated as a case where “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the charge accumulation region Z”.

Let thought be given to a case where the diffusion-suppressing species is carbon. The ratio C2/C1of the concentration C2of carbon in the first specific layer to the concentration C1of carbon in the charge accumulation region Z is for example higher than or equal to 1×105. This ratio is for example lower than or equal to 1×1011.

Let thought be given to a case where the diffusion-suppressing species is carbon and the first specific layer is included in a first extension diffusion layer. The concentration of the conductive impurity in the first extension diffusion layer is for example higher than or equal to 1×1017atoms/cm3. The concentration of carbon in the first extension diffusion layer is for example higher than or equal to 1×1017atoms/cm3. The concentration of the conductive impurity in the first extension diffusion layer is for example lower than or equal to 1×1022atoms/cm3. The concentration of carbon in the first extension diffusion layer is for example lower than or equal to 1×1022atoms/cm3. These descriptions may be applied to both the first extension diffusion layers306aand306b.

In one example, the concentration of carbon in the charge accumulation region Z is substantially zero. The clause “the concentration of carbon in the charge accumulation region Z is substantially zero” here means, for example, that the concentration of carbon in the charge accumulation region Z is lower than 5×1016atoms/cm3. Intentionally-given carbon does not need to be present in the charge accumulation region Z. The concentration of carbon in the charge accumulation region Z may be 0 atoms/cm3.

In one example, the concentration of the diffusion-suppressing species in the first specific layer is for example higher than or equal to 5×1016atoms/cm3. The ratio of the concentration of the diffusion-suppressing species in the first specific layer to the concentration of the diffusion-suppressing species in the charge accumulation region Z is for example higher than or equal to 1×105. This ratio is for example lower than or equal to 1×1011.

In the present embodiment, the amplifying transistor22has a source67a, a drain67b, and a channel region68within the first peripheral substrate portion.

The channel region68is located between the source67aand the drain67b. Further, the channel region68is located in a region including an area under the gate of the amplifying transistor22. The term “area under the gate of the amplifying transistor22” refers to a portion of a path of charge between the source67aand the drain67bthat overlaps the gate electrode67cin a plan view.

In one example, the concentration of carbon in the first specific layer is higher than the concentration of carbon in the channel region68. This configuration is advantageous from the point of view of reducing dark current. In the expression “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the channel region68”, the concentration of carbon in the channel region68may be zero, or may be higher than zero.

According to a first definition, the phrase “concentration of carbon” in the expression “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the channel region68” is a maximum value of concentration. According to a second definition, the phrase “concentration of carbon” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the channel region68” is treated as a case where “the concentration of carbon in the first specific layer is higher than the concentration of carbon in the channel region68”.

The ratio of the concentration of the diffusion-suppressing species in the first specific layer to the concentration of the diffusion-suppressing species in the channel region68is for example higher than or equal to 1×105. This ratio is for example lower than or equal to 1×1011.

In one example, the amplifying transistor22has a pixel specific layer. The pixel specific layer is located within the pixel substrate portion. The pixel specific layer contains a conductive impurity.

The conductive impurity of the pixel specific layer and the conductive impurity of the first specific layer may be identical or different in composition to or from each other.

In one example, at least either the source67aor the drain67bof the amplifying transistor22includes the pixel specific layer.

In one example, the channel region68may include the pixel specific layer.

In one example, the amplifying transistor22does not have an extension diffusion layer.

Incidentally, the gate electrode302of the first peripheral transistor27may be made, for example, of phosphorus-doped polysilicon. In that case, however, phosphorus may exude to the first peripheral substrate portion when the first peripheral region R2is heated by heat treatment for heating the pixel region R1. In this respect, an imaging device according to one example has a high-K metal gate constructed in the first peripheral transistor27. This makes it possible to reduce or avoid the exudation of the impurity from the gate electrode302to the first peripheral substrate portion. This may contribute to the suppression of the short channel effect in the first peripheral transistor27. Specifically, the high-K metal gate can be constructed by the gate electrode302, which is made of metal, and the gate insulator film301, which is made of a high-κ material. The term “high-κ material” refers to a material having a higher dielectric constant than silicon dioxide. Examples of high-κ materials include hafnium (Hf), zirconium (Zr), and aluminum (Al). High-κ materials are also referred to as “high-dielectric-constant materials”.

The first peripheral region R2may include one or more first peripheral transistors27.

FIG.19schematically shows an amplifying transistor22in the pixel region R1and a plurality of the first peripheral transistors27in the first peripheral region R2in a case where the configuration ofFIG.1is adopted.FIG.20schematically shows an amplifying transistor22in the pixel region R1and a plurality of the first peripheral transistors27in the first peripheral region R2in a case where the configuration ofFIG.4is adopted.

In each of the examples shown inFIGS.19and20, a plurality of the first peripheral transistors27are present in the first peripheral region R2. The plurality of first peripheral transistors27include a first direction transistor27aand a second direction transistor27b. The first direction transistor27ais located in a first direction X1from the pixel region R1in a plan view. The second direction transistor27bis located in a second direction X2from the pixel region R1in a plan view. It should be noted that the expression “a plurality of the first peripheral transistors27are present” is not intended to mean that those transistors are completely identical. The same applies to the after-mentioned “two first peripheral transistors”.

The first direction X1and the second direction X2are different from each other. In each of the examples shown inFIGS.19and20, the first direction X1and the second direction X2are orthogonal to each other.

As shown inFIGS.21and22, the imaging device may include a second peripheral region R3. Transmission of signals between the first peripheral region R2and the pixel region R1is done via the second peripheral region R3. In each of the examples shown inFIGS.21and22, the second peripheral region R3is located between the pixel region R1and the first peripheral region R2in a plan view. Specifically, the second peripheral region R3is located outside the pixel region R1. More specifically, the second peripheral region R3is located outside the pixel region R1in a plan view.

In each of the examples shown inFIGS.21and22, the second peripheral region R3has a second peripheral transistor427. The second peripheral transistor427is provided in the second peripheral substrate portion. In one example, the second peripheral transistor427is a logic transistor. The second peripheral transistor427may be a planar transistor, or may be a three-dimensional structural transistor. A first example of a three-dimensional structural transistor is a FinFET (fin field-effect transistor). A second example of a three-dimensional structural transistor is a GAA (gate all around) such as a nanowire FET. A third example of a three-dimensional structural transistor is a nanosheet FET.

In the example shown inFIG.21, the first peripheral region R2and the second peripheral region R3are L-shaped in a plan view. In the example shown inFIG.22, the first peripheral region R2surrounds the second peripheral region R3in a plan view, and the second peripheral region R3surrounds the pixel region R1in a plan view.

FIG.23shows a configuration that the second peripheral transistor427in the second peripheral region R3may have in each of the examples shown inFIGS.21and22. In the example shown inFIG.23, the second peripheral transistor427is a P-channel MOSFET.

In the example shown inFIG.23, the second peripheral transistor427of the second peripheral region R3have similarities to the first peripheral transistor27of the first peripheral region R2. Specifically, as is the case with the first peripheral transistor27, the second peripheral transistor427is a MIS transistor. As is the case with the first peripheral transistor27, the second peripheral transistor427includes a gate electrode402, a second source413a, a second drain413b, second extension diffusion layers406aand406b, second pocket diffusion layers407aand407b, a second channel layer403, a gate insulator film401, offset spacers409aand409b, first side walls408Aa and408Ab, and second side walls408Ba and408Bb. As for these constituent elements, the description of the first peripheral transistor27can be invoked in the description of the second peripheral transistor427, provided no contradiction arises.

In one example, the second peripheral transistor427has a second specific layer. The second specific layer is located within the second peripheral substrate portion. The second specific layer contains a conductive impurity.

The conductive impurity of the second specific layer and the conductive impurity of the first specific layer may be identical or different in composition to or from each other.

The second specific layer may contain a diffusion-suppressing species. The diffusion-suppressing species that the second specific layer has may be the same as or different from the diffusion-suppressing species that the first specific layer has. For example, the diffusion-suppressing species of the first specific layer may be carbon, and the diffusion-suppressing species of the second specific layer may be nitrogen and fluorine.

In one example, the second peripheral transistor427has the second source413aand the second drain413b. At least either the second source413aor the second drain413bincludes the second specific layer.

In the present embodiment, the second peripheral transistor427incudes a second source413a, a second drain413b, and a second channel region403within the second peripheral substrate portion.

The second channel region403is located between the second source413aand the second drain413b. Further, the second channel region403is located in a region including an area under the gate of the second peripheral transistor427. The term “area under the gate of the second peripheral transistor427” refers to a portion of a path of charge between the second source413aand the second drain413bthat overlaps the gate electrode402in a plan view.

In the present embodiment, the second peripheral transistor427has a second strain-introducing layer within the second peripheral substrate portion. The second strain-introducing layer brings a strain to the second channel region403. The strain brings about improvement in the carrier mobility of the second channel region403. This configuration is suitable to improving the performance of an imaging device. The strain that the second strain-introducing layer brings to the second channel region403may be a compression strain or may be a tensile strain.

In the present embodiment, the second strain-introducing layer is a crystal layer. Specifically, in the crystal layer, a crystal lattice is constituted by atoms or molecules in the layer being regularly and periodically arrayed.

For example, the second strain-introducing layer is a crystal layer of silicon germanium (SiGe), a crystal layer of germanium (Ge), a crystal layer of a Group III-V compound, a crystal layer of silicon carbide (SiC), a crystal layer of transition metal dichalcogenide (TMD), or a crystal layer of carbon nanotubes (CNTs). Examples of Group III-V compounds include InGaAs, InP, GaAs, InAs, InSb, InGaSb, and AlGaSb.

Examples of the second strain-introducing layer in a case where the second peripheral transistor427is a P-channel transistor include a crystal layer of silicon germanium, a crystal layer of germanium, a crystal layer of transition metal dichalcogenide, a crystal layer of carbon nanotubes, and a crystal layer of a Group III-V compound. Examples of the second strain-introducing layer in a case where the second peripheral transistor427is an N-channel transistor include a crystal layer of silicon carbide, a crystal layer of transition metal dichalcogenide, and a crystal layer of carbon nanotubes.

In one specific example, the second strain-introducing layer is a crystal layer of Si1-xGex. X is greater than or equal to 0.1 and less than or equal to 0.85. X may be greater than or equal to 0.1 and less than or equal to 0.65.

In the present embodiment, the second strain-introducing layer is a single-crystal layer. Further, the second strain-introducing layer is an epitaxial layer.

In one example, the first strain-introducing layer and the second strain-introducing layer are crystal layers. In this example, a material of the crystal layer that constitutes the first strain-introducing layer and a material of the crystal layer that constitutes the second strain-introducing layer may be the same as or different from each other. In one specific example, both the first strain-introducing layer and the second strain-introducing layer are silicon-germanium crystal layers. In another specific example, the first strain-introducing layer is a silicon-germanium crystal layer, and the second strain-introducing layer is a germanium crystal layer.

For example, the second peripheral substrate portion has a second foundation layer. The second foundation layer is adjacent to the second strain-introducing layer. The second foundation layer is a foundation of the second strain-introducing layer. The lattice constant of a crystal lattice of the second strain-introducing layer and the lattice constant of a crystal lattice of the second foundation layer are different from each other. The second channel region403has a strain attributed to this difference. This strain brigs about improvement in the carrier mobility of the second channel region403. In a typical example, the second foundation layer is a single-crystal layer of silicon.

In one example, the second foundation layer is the first epitaxial layer135. In another example, the second foundation layer is the supporting substrate140. In still another example, the second foundation layer is a well in the second peripheral substrate portion. This well may or may not be one that the second peripheral substrate portion and the first peripheral substrate portion share with each other. This well may or may not be one that the second peripheral substrate portion and the pixel substrate portion share with each other.

Specifically, the second strain-introducing layer and the second foundation layer may be epitaxial layers. Further, the second strain-introducing layer may be thinner than the second foundation layer. A configuration in which the second strain-introducing layer is thin is expected to express a quantum-confined effect.

In the present embodiment, the second strain-introducing layer is a single-crystal layer. Further, the second strain-introducing layer is an epitaxial layer.

In the present embodiment, the conductivity type of the second peripheral transistor427is different from the conductivity type of the amplifying transistor22.

At least one selected from the group consisting of the second channel region403, the second source413a, and the second drain413bmay include the second strain-introducing layer.

In the second peripheral transistor427according to the first configuration example, the second channel region403includes a second strain-introducing layer.

In one specific example, the second peripheral transistor427according to the first configuration example has the configuration described with reference toFIGS.5A and5B.

In the second peripheral transistor427according to the second configuration example, the second source413aincludes a second strain-introducing layer. The second drain413bincludes a second strain-introducing layer. That is, the second peripheral transistor427includes a plurality of the second strain-introducing layers. The second strain-introducing layer included in the second source413aand the second strain-introducing layer included in the second drain413bare different from each other.

In one specific example, the second peripheral transistor427according to the second configuration example has the configuration described with reference toFIGS.6A to6D.

In one example, the second peripheral substrate portion has the supporting substrate140. The second peripheral transistor427has a second cap layer within the second peripheral substrate portion. The supporting substrate140, the second strain-introducing layer, and the second cap layer are arranged in an order from lower to upper parts of the second peripheral transistor427. The second cap layer includes an upper surface of the second peripheral substrate portion. The concentration of a conductive impurity of the second cap layer is lower than the concentration of a conductive impurity of the supporting substrate140.

The second cap layer may be an epitaxial layer that is similar to the third epitaxial layer137described with reference toFIGS.5A and5B. The second cap layer may be a single-crystal layer. The second cap layer may be a non-doped epitaxial layer.

In one example, the second channel region403may include the second specific layer.

In one example, the second peripheral transistor427has second extension diffusion layers406aand406b. The second extension diffusion layers406aand406bare adjacent to the second source413aor the second drain413b. The second extension diffusion layers406aand406bare shallower than the second source413aand the second drain413b. The second extension diffusion layers406aand406bmay include the second specific layer.

The sentence “a second extension diffusion layer is shallower than the second source413aand the second drain413b” means that the deepest portion of the second extension diffusion layer is at a shallower depth than the deepest portions of the second source413aand the second drain413bin a direction parallel with the depth of the second peripheral substrate portion. In this context, the word “shallow” can also be referred to as “shallow in junction depth”.

In the illustrated example, the second peripheral transistor427has the second extension diffusion layer406aand the second extension diffusion layer406b. The second extension diffusion layer406ais adjacent to the second source413a. The second extension diffusion layer406ais shallower than the second source413aand the second drain413b. The second extension diffusion layer406bis adjacent to the second drain413b. The second extension diffusion layer406bis shallower than the second source413aand the second drain413b. The second extension diffusion layer406aand the second extension diffusion layer406bmay include the second specific layer.

In one example, the second peripheral transistor427has second pocket diffusion layers407aand407b. The second pocket diffusion layers407aand407bare adjacent to the second source413aor the second drain413b. The second pocket diffusion layers407aand407bmay include the second specific layer.

In the illustrated example, the second peripheral transistor427has the second pocket diffusion layer407aand the second pocket diffusion layer407b. The second pocket diffusion layer407ais adjacent to the second source413a. The second pocket diffusion layer407bis adjacent to the second drain413b. The second pocket diffusion layer407aand the second pocket diffusion layer407bmay include the second specific layer.

Only one selected from among the second channel region403, the second source413a, the second drain413b, the second extension diffusion layer, and the second pocket diffusion layers may include the second specific layer. Specifically, only one selected from among the second channel region403, the second source413a, the second drain413b, the second extension diffusion layer406a, the second extension diffusion layer406b, the second pocket diffusion layer407a, and the second pocket diffusion layer407bmay include the second specific layer.

Two or more selected from among the second channel region403, the second source413a, the second drain413b, the second extension diffusion layer, and the second pocket diffusion layers may include the second specific layer. Specifically, two or more selected from among the second channel region403, the second source413a, the second drain413b, the second extension diffusion layer406a, the second extension diffusion layer406b, the second pocket diffusion layer407a, and the second pocket diffusion layer407bmay include the second specific layer. In a case where these selected two or more include the second specific layer, these may include the same or different types of diffusion-suppressing species. For example, the diffusion-suppressing species of the second source413amay be carbon, and the diffusion-suppressing species of the second extension diffusion layers406aand406bmay be nitrogen and fluorine. Further, in this case, these may include the same or different conductivity types of conductive impurity. For example, either the second source413aor the second pocket diffusion layers407aand407bmay contain boron whose conductivity type is a p type, and the other may contain phosphorus whose conductivity type is an n type.

As can be understood from the foregoing description, the imaging device may have one second specific layer or may have a plurality of second specific layers.

Examples of the position of a second specific layer are further described.

In the first configuration example, the second channel region403includes a second strain-introducing layer. In one specific example of the first configuration example, at least one selected from among a configuration (A) and a configuration (B) holds.

In the configuration (A), the second pocket diffusion layers407aand407binclude the second specific layer. In the configuration (B), regions between the second pocket diffusion layers407aand407band the second strain-introducing layer include the second specific layer.

According to the configuration (A) and/or the configuration (B), possible diffusion of a conductive impurity by TED in directions from the second pocket diffusion layers407aand407btoward the second channel region403can be suppressed. It should be noted that the regions between the second pocket diffusion layers407aand407band the second strain-introducing layer are for example the second extension diffusion layers406aand406b. Specific examples of regions in which the second specific layer may be distributed in the configuration (A) and the configuration (B) are regions that are similar to the regions of the carbon-implanted layers311ofFIG.5B.

In the second configuration example, the second source413aincludes a second strain-introducing layer. The second drain413bincludes a second strain-introducing layer. In one specific example of the second configuration example, the second peripheral substrate portion has a second foundation layer. At least one selected from among a configuration (C) and a configuration (D) holds.

In the configuration (C), there is a third interface between the second foundation layer and the second strain-introducing layer included in the second source413a. A conductive impurity of the second source413aspreads in a third region of the second foundation layer astride the third interface. The third region includes the second specific layer.

In the configuration (D), there is a fourth interface between the second foundation layer and the second strain-introducing layer included in the second drain413b. In the configuration (D), a conductive impurity of the second drain413bspreads in a fourth region of the second foundation layer astride the fourth interface. In the configuration (D), the fourth region includes the second specific layer.

According to the configuration (C), even in a situation where a conductive impurity spreads in the third region of the second foundation layer astride the third interface from the second strain-introducing layer included in the second source413a, diffusion of the conductive impurity by TED in the second foundation layer can be suppressed. According to the configuration (D), even in a situation where a conductive impurity spreads in the fourth region of the second foundation layer astride the fourth interface from the second strain-introducing layer included in the second drain413b, diffusion of the conductive impurity by TED in the second foundation layer can be suppressed. This may suppress the short channel effect and reduce deterioration of the performance of the second peripheral transistor427. Specific examples of regions in which the second specific layer may be distributed in the configuration (C) and the configuration (D) are regions that are similar to the regions of the carbon-implanted layers311ofFIG.6B.

In one example, the concentration of the conductive impurity in the second extension diffusion layer is lower than the concentration of the conductive impurity in the first extension diffusion layer. The second extension diffusion layer is deeper than the first extension diffusion layer. As mentioned above, the first extension diffusion layer is the first extension diffusion layer306aor the first extension diffusion layer306b. Further, the second extension diffusion layer is the second extension diffusion layer406aor the second extension diffusion layer406b.

The sentence “the second extension diffusion layer is deeper than the first extension diffusion layer” means that the deepest portion of the second extension diffusion layer is at a greater depth than the deepest portion of the first extension diffusion layer in a direction parallel with the depth of the first peripheral substrate portion or the second peripheral substrate portion. In this context, the word “deep” can also be referred to as “great in junction depth”.

According to a first definition, the phrase “concentration of the conductive impurity” in the expression “the concentration of the conductive impurity in the second extension diffusion layer is lower than the concentration of the conductive impurity in the first extension diffusion layer” is a maximum value of concentration. According to a second definition, the phrase “concentration of the conductive impurity” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of the conductive impurity in the second extension diffusion layer is lower than the concentration of the conductive impurity in the first extension diffusion layer” is treated as a case where “the concentration of the conductive impurity in the second extension diffusion layer is lower than the concentration of the conductive impurity in the first extension diffusion layer”. Further, in this expression, the type of the conductive impurity in the first extension diffusion layer and the type of the conductive impurity in the second extension diffusion layer may be the same as or different from each other. For example, the conductive impurity in the first extension diffusion layer may be boron, and the conductive impurity in the second extension diffusion layer may be indium.

In the illustrated example, the second peripheral transistor427has the second extension diffusion layer406aand the second extension diffusion layer406b. The second extension diffusion layer406ais adjacent to the second source413a. The second extension diffusion layer406ais shallower than the second source413aand the second drain413b. The second extension diffusion layer406ahas a conductive impurity. The second extension diffusion layer406bis adjacent to the second drain413b. The second extension diffusion layer406bis shallower than the second source413aand the second drain413b. The second extension diffusion layer406bhas a conductive impurity. The concentration of the conductive impurity in the second extension diffusion layer406ais lower than the concentration of the conductive impurity in the first extension diffusion layer306a. The second extension diffusion layer406ais deeper than the first extension diffusion layer306a. The concentration of the conductive impurity in the second extension diffusion layer406bis lower than the concentration of the conductive impurity in the first extension diffusion layer306b. The second extension diffusion layer406bis deeper than the first extension diffusion layer306b.

In one example, the gate length L27of the first peripheral transistor27is shorter than the gate length L427of the second peripheral transistor427. In terms of miniaturization of the first peripheral transistor27and from the point of view of causing the first peripheral transistor27to operate at high speed, it is advantageous for the gate length L27of the first peripheral transistor27to be short. In one specific example, the second peripheral transistor427is included in an analog processor, and the first peripheral transistor27is included in a digital processor. In this specific example, employing the first peripheral transistor27and the second peripheral transistor427with different gate lengths allows the digital processor to achieve digital processing making use of the high-speed operation of the first peripheral transistor27, whose gate length L27is short. Since the first peripheral transistor27is finer, the speeding up of digital processing in the digital processing becomes possible. Meanwhile, since the gate length L427is relatively long, variations in the threshold voltage of the second peripheral transistor427may be reduced. This makes it also possible to improve the analog characteristics of the second peripheral transistor427in the analog processor.

The ratio L27/L427of the gate length L27of the first peripheral transistor27to the gate length L427of the second peripheral transistor427is for example lower than or equal to 0.8, or may be lower than or equal to 0.34. This ratio is for example higher than or equal to 0.01, or may be higher than or equal to 0.05.

In one example, the gate length L22of the amplifying transistor22is longer than the gate length L427of the second peripheral transistor427. In terms of improvement in the characteristics of the amplifying transistor22, it may be advantageous for the gate length L22of the amplifying transistor22to be long. In one specific example, the amplifying transistor22is included in the analog processor. In this specific example, the gate length L22is increased, and variations in the threshold voltage of the amplifying transistor22are reduced, so that it is easy to improve a Pelgrom coefficient. This allows the analog processor to achieve analog processing making use of the favorable analog characteristics of the amplifying transistor22based on this case of improvement.

The ratio L427/L22of the gate length L427of the second peripheral transistor427to the gate length L22of the amplifying transistor22is for example lower than or equal to 0.95, or may be lower than or equal to 0.9. This ratio is for example higher than or equal to 0.1, or may be higher than or equal to 0.36.

In one example, the gate insulator film301of the first peripheral transistor27is thinner than the gate insulator film401of the second peripheral transistor427. In terms of miniaturization of the first peripheral transistor27and from the point of view of causing the first peripheral transistor27to operate at high speed, it is advantageous for the gate insulator film301of the first peripheral transistor27to be thin. In one specific example, the second peripheral transistor427is included in the analog processor, and the first peripheral transistor27is included in the digital processor. In this specific example, employing the first peripheral transistor27and the second peripheral transistor427with different insulator film thicknesses allows the digital processor to achieve digital processing making use of the high-speed operation of the first peripheral transistor27, whose gate insulator film301is thin. Since the first peripheral transistor27is finer, the speeding up of digital processing in the digital processing becomes possible. Meanwhile, since the gate insulator film401is relatively thick, variations in the threshold voltage of the second peripheral transistor427may be reduced. This makes it also possible to improve the analog characteristics of the second peripheral transistor427in the analog processor.

The ratio T301/T401of the thickness T301of the gate insulator film301of the first peripheral transistor27to the thickness T401of the gate insulator film401of the second peripheral transistor427is for example lower than or equal to 0.7, or may be lower than or equal to 0.36. This ratio is for example higher than or equal to 0.1, or may be higher than or equal to 0.22.

In one example, the gate insulator film69of the amplifying transistor22is thicker than the gate insulator film401of the second peripheral transistor427. In terms of improvement in the characteristics of the amplifying transistor22, it may be advantageous for the gate insulator film69of the amplifying transistor22to be thick. In one specific example, the amplifying transistor22is included in the analog processor. In this specific example, the gate insulator film69is thickened, and variations in the threshold voltage of the amplifying transistor22are reduced, so that it is easy to improve a Pelgrom coefficient. This allows the analog processor to achieve analog processing making use of the favorable analog characteristics of the amplifying transistor22based on this case of improvement.

The ratio T401/T69of the thickness T401of the gate insulator film401of the second peripheral transistor427to the thickness T69of the gate insulator film69of the amplifying transistor22is for example lower than 1. This ratio is for example higher than or equal to 0.68.

In one specific example, the second peripheral transistor427is a logic transistor. The second peripheral transistor427can perform an analog operation in a state of being incorporated in a pixel driver, a load cell, a column amplifier, a comparator, or other devices. In the analog operation, it may be advantageous for a dynamic range to be wide. In order to secure a wide dynamic range, it is advantageous for a transistor to have a high operating voltage and a wide voltage range. For example, in the case of a pixel voltage of approximately 3 V to 3.5 V, it may be advantageous for the operating voltage to be 3.3 V. In this respect, in this specific example, the gate length L427of the second peripheral transistor427is longer than the gate length L27of the first peripheral transistor27. The gate insulator film401of the second peripheral transistor427is thicker than the gate insulator film301of the first peripheral transistor27. From the point of view of raising the operating voltage of the second peripheral transistor427, it is advantageous from the gate length L427to be long and for the gate insulator film401to be thick. In the aforementioned context, the operating voltage is the drain voltage of a transistor when the transistor is on. The pixel voltage is the voltage of a charge accumulation node in a pixel.

In this specific example, the operating voltage of the second peripheral transistor427is higher than the operating voltage of the first peripheral transistor27. The operating voltage of the second peripheral transistor427is for example 3.3 V. The operating voltage of the first peripheral transistor27is for example 1.2 V.

In this specific example, variations in the threshold voltage of the second peripheral transistor427are small, as the second peripheral transistor427is longer in gate length and greater in gate insulator film thickness than the first peripheral transistor27. Small variations in threshold voltage are a favorable feature. Further, in this specific example, the threshold voltage of the second peripheral transistor427is higher than the threshold voltage of the first peripheral transistor27. The threshold voltage of the second peripheral transistor427is for example approximately 0.5 V. The threshold voltage of the first peripheral transistor27is for example approximately 0.3 V.

In one example, the concentration of the diffusion-suppressing species in the first specific layer is higher than the concentration of the diffusion-suppressing species in the second specific layer. In the expression “the concentration of the diffusion-suppressing species in the first specific layer is higher than the concentration of the diffusion-suppressing species in the second specific layer”, the concentration of the diffusion-suppressing species in the second specific layer may be zero, or may be higher than zero.

According to a first definition, the phrase “concentration of the specific layer” in the expression “the concentration of the diffusion-suppressing species in the first specific layer is higher than the concentration of the diffusion-suppressing species in the second specific layer” is a maximum value of concentration. According to a second definition, the phrase “concentration of the diffusion-suppressing species” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of the diffusion-suppressing species in the first specific layer is higher than the concentration of the diffusion-suppressing species in the second specific layer” is treated as a case where “the concentration of the diffusion-suppressing species in the first specific layer is higher than the concentration of the diffusion-suppressing species in the second specific layer”. Further, in this example, the type of the diffusion-suppressing species in the first specific layer and the type of the diffusion-suppressing species in the second specific layer may be the same as or different from each other. For example, the diffusion-suppressing species in the first specific layer may be carbon, and the diffusion-suppressing species in the second specific layer may be nitrogen and fluorine.

The concentration of carbon in the first specific layer may be higher than the concentration of carbon in the second specific layer. The concentration of nitrogen in the first specific layer may be higher than the concentration of nitrogen in the second specific layer. The concentration of fluorine in the first specific layer may be higher than the concentration of fluorine in the second specific layer. The concentration of germanium in the first specific layer may be higher than the concentration of germanium in the second specific layer. The concentration of silicon in the first specific layer may be higher than the concentration of silicon in the second specific layer. The concentration of argon in the first specific layer may be higher than the concentration of argon in the second specific layer.

In one example, the concentration of carbon in the second specific layer is higher than the concentration of carbon in the channel region68of the amplifying transistor22. In the expression “the concentration of carbon in the second specific layer is higher than the concentration of carbon in the channel region68of the amplifying transistor22”, the concentration of carbon in the channel region68of the amplifying transistor22may be zero, or may be higher than zero.

The concentration of the diffusion-suppressing species in the second specific layer is for example higher than or equal to 5×1016atoms/cm3. The ratio of the concentration of the diffusion-suppressing species in the second specific layer to the concentration of the diffusion-suppressing species in the charge accumulation region Z is for example higher than or equal to 1×105. This ratio is for example lower than or equal to 1×1011.

According to a first definition, the phrase “concentration of carbon” in the expression “the concentration of carbon in the second specific layer is higher than the concentration of carbon in the channel region68of the amplifying transistor22” is a maximum value of concentration. According to a second definition, the phrase “concentration of carbon” in this expression is an average concentration. In the aforementioned example, a case where it can be said on the basis of at least either the first definition or the second definition that “the concentration of carbon in the second specific layer is higher than the concentration of carbon in the channel region68of the amplifying transistor22” is treated as a case where “the concentration of carbon in the second specific layer is higher than the concentration of carbon in the channel region68of the amplifying transistor22”.

The ratio of the concentration of the diffusion-suppressing species in the second specific layer to the concentration of the diffusion-suppressing species in the channel region68is for example higher than or equal to 1×105. This ratio is for example lower than or equal to 1×1011.

In one example, the second extension diffusion layer contains nitrogen.

In the illustrated example, the second extension diffusion layer406acontains nitrogen. The second extension diffusion layer406bcontains nitrogen.

The nitrogen of the second extension diffusion layer may be derived from ion implantation of nitrogen (N) ions, or may be derived from implantation of nitrogen molecules N2. In the illustrated example, the nitrogen of the second extension diffusion layer406amay be derived from ion implantation of nitrogen (N) ions, or may be derived from implantation of nitrogen molecules N2. The nitrogen of the second extension diffusion layer406bmay be derived from ion implantation of nitrogen (N) ions, or may be derived from implantation of nitrogen molecules N2. The same applies to the carbon in the first extension diffusion layers306aand306bin that the carbon may be derived from ion implantation.

Of course, a transistor other than the transistors shown inFIGS.21to23may be provided. In each of the examples shown inFIGS.24to27, the first peripheral region R2has a first peripheral transistor27and a first peripheral transistor727. A device isolation220is disposed between the first peripheral transistor27and the first peripheral transistor727. The second peripheral region R3has a second peripheral transistor427and a second peripheral transistor827. The device isolation220is disposed between the second peripheral transistor427and the second peripheral transistor827. It should be noted thatFIG.27simplistically illustrates the first peripheral transistor27, the second peripheral transistor427, and the amplifying transistor22and omits to illustrate the device isolation220.

In each of the examples shown inFIGS.24to27, the first peripheral transistor727has similarities to the first peripheral transistor27. Specifically, as is the case with the first peripheral transistor27, the first peripheral transistor727is a MIS transistor. As is the case with the first peripheral transistor27, the first peripheral transistor727includes a gate electrode702, a second source713a, a second drain713b, extension diffusion layers706aand706b, pocket diffusion layers707aand707b, a channel region703, a gate insulator film701, offset spacers709aand709b, first side walls708Aa and708Ab, and second side walls708Ba and708Bb.

Note, however, that the first peripheral transistor27and the first peripheral transistor727are opposite in polarity to each other. Specifically, the first peripheral transistor27is a P-channel transistor, and the first peripheral transistor727is an N-channel transistor. The p-type source diffusion layer313a, which serves as the first source, is of a p type, and the source713ais of an n type. The p-type drain diffusion layer313b, which serves as the first drain, is of a p type, and the source713bis of an n type. The first extension diffusion layer306ais of a p type, and the extension diffusion layer706ais of an n type. The first extension diffusion layer306bis of a p type, and the extension diffusion layer706bis of an n type. The first pocket diffusion layer307ais of an n type, and the pocket diffusion layer707ais of a p type. The first pocket diffusion layer307bis of an n type, and the pocket diffusion layer707bis of a p type. The N-type channel diffusion layer303, which serves as the first channel region, is of an n type, and the channel region703is of a p type. InFIG.27, the first peripheral transistor727includes the n-type impurity region81n, which is an n-type well.

In the following, the ordinal numeral “first” may be added to the constituent elements of the first peripheral transistor727. For example, the source713amay be referred to as “first source”. Further, the drain713bmay be referred to as “first drain”.

In the illustrated example, the device isolation220is an STI structure. The STI structure has a trench (groove) and a filler filling the trench. The filler is for example an oxide. The depth of the trench is for example approximately 500 nm. The STI structure may be formed in the semiconductor substrate130by an STI process.

In the illustrated example, the first peripheral region R2has two first peripheral transistors27and727and a device isolation220that is an STI structure. The device isolation220, which is the STI structure, provides device isolation of the two first peripheral transistors27and727from each other. The device isolation220, which is the STI structure, has a trench.

In the illustrated example, a range of distribution of the diffusion-suppressing species in the first specific layer of at least either of the two first peripheral transistors27and727is shallower than the bottom of the trench. In this context, the phrase “range of distribution of the diffusion-suppressing species” refers to a region in which the concentration of the diffusion-suppressing species is higher than or equal to 5×1016atoms/cm3. The same applies to a range of distribution of carbon or other substances. The term “bottom of the trench” means the deepest portion of the trench in a direction parallel with the depth of the first peripheral substrate portion.

A range of distribution of carbon in the first specific layer of at least either of the two first peripheral transistors27and727may be shallower than the bottom of the trench. A range of distribution of nitrogen in the first specific layer of at least either of the two first peripheral transistors27and727may be shallower than the bottom of the trench. A range of distribution of fluorine in the first specific layer of at least either of the two first peripheral transistors27and727may be shallower than the bottom of the trench.

Specifically, the two first peripheral transistors27and727are opposite in polarity to each other. In a plan view, the device isolation220, which is the STI structure, is disposed between the two first peripheral transistors27and727and, more specifically, on a segment connecting the two first peripheral transistors27and727with each other. As illustrated inFIG.26, the STI structure may project upward from a portion of the first peripheral substrate portion that is present around the STI structure.

It should be noted that the device isolation220may be an implantation isolation region.

In each of the examples shown inFIGS.24to27, the second peripheral transistor827has similarities to the second peripheral transistor427. Specifically, as is the case with the second peripheral transistor427, the second peripheral transistor827is a MIS transistor. As is the case with the second peripheral transistor427, the second peripheral transistor827includes a gate electrode802, a source813a, a drain813b, extension diffusion layers806aand806b, pocket diffusion layers807aand807b, a channel region803, a gate insulator film801, offset spacers809aand809b, first side walls808Aa and808Ab, and second side walls808Ba and808Bb.

Note, however, that the second peripheral transistor427and the second peripheral transistor827are opposite in polarity to each other. Specifically, the second peripheral transistor427is a P-channel transistor, and the second peripheral transistor827is an N-channel transistor. The second source413ais of a p type, and the source813ais of an n type. The second drain413bis of a p type, and the drain813bis of an n type. The second extension diffusion layer406ais of a p type, and the extension diffusion layer806ais of an n type. The second extension diffusion layer406bis of a p type, and the extension diffusion layer806bis of an n type. The second pocket diffusion layer407ais of an n type, and the pocket diffusion layer807ais of a p type. The first pocket diffusion layer407bis of an n type, and the pocket diffusion layer807bis of a p type. The second channel diffusion layer403is of an n type, and the channel region803is of a p type.

The ordinal numeral “second” may be added to the constituent elements of the second peripheral transistor427. For example, the source813amay be referred to as “second source”. Further, the drain813bmay be referred to as “second drain”.

Let it be emphatically said that the second peripheral region R3is not essential. Of course, the second peripheral transistors427and827are not essential. Further, in the first peripheral region R2, at least either of the first peripheral transistors27and727may be used in analog processing. In one specific example, in the first peripheral region R2, one first peripheral transistor is used in digital processing, and another first peripheral transistor is used in analog processing.

The description of the first peripheral transistor27and elements thereof can be invoked in the description of the first peripheral transistor727and elements thereof, provided no contradiction arises. The description of the second peripheral transistor427and elements thereof can be invoked in the description of the second peripheral transistor827and elements thereof, provided no contradiction arises. The description of a relationship among the first peripheral transistor27, the second peripheral transistor427, and the amplifying transistor22can be invoked in the description of a relationship among the first peripheral transistor727, the second peripheral transistor827, and the amplifying transistor22, provided no contradiction arises.

For example, the gate length L727of the first peripheral transistor727may be shorter than the gate length L22of the amplifying transistor22. The gate length L727of the first peripheral transistor727may be shorter than the gate length L827of the second peripheral transistor827. The gate length L827of the second peripheral transistor827may be shorter than the gate length L22of the amplifying transistor22. The extension diffusion layer706amay be shallower than the source713aand the drain713b. The extension diffusion layer706bmay be shallower than the source713aand the drain713b. The extension diffusion layer806amay be shallower than the source813aand the drain813b. The extension diffusion layer806bmay be shallower than the source813aand the drain813b. The extension diffusion layer706amay contain a conductive impurity and a diffusion-suppressing species. The extension diffusion layer706bmay contain a conductive impurity and a diffusion-suppressing species. The extension diffusion layer806amay contain nitrogen. The nitrogen of the extension diffusion layer806amay be derived from ion implantation of nitrogen (N) ions, or may be derived from implantation of nitrogen molecules N2. The extension diffusion layer806bmay contain nitrogen. The nitrogen of the extension diffusion layer806bmay be derived from ion implantation of nitrogen (N) ions, or may be derived from implantation of nitrogen molecules N2.

As can be understood from the foregoing description, in the imaging device, at least either the extension diffusion layer806aor the extension diffusion layer806bof the second peripheral transistor827, which is an N-channel transistor, may contain nitrogen. This nitrogen affects not only the distribution of impurities in the second peripheral substrate portion but also the interface characteristics of the gate insulator film of the second peripheral transistor827, thereby bringing about improvement in the reliability of the imaging device. At least either the extension diffusion layer806aor the extension diffusion layer806bthat contains the aforementioned nitrogen may be a so-called LDD diffusion layer.

In an example in which at least either the extension diffusion layer806aor the extension diffusion layer806bof the second peripheral transistor827, which is an N-channel transistor, contains nitrogen, the second extension diffusion layer706aof the first peripheral transistor727, which is a P-channel transistor, may or may not contain nitrogen. In this example, the second extension diffusion layer706bof the first peripheral transistor727, which is a P-channel transistor, may or may not contain nitrogen.

In one example, in a plan view, the amplifying transistor22, the second peripheral transistor427, the second peripheral transistor827, the first peripheral transistor27, and the first peripheral transistor727are arranged in this order. In another example, in a plan view, the amplifying transistor22, the second peripheral transistor827, the second peripheral transistor427, the first peripheral transistor727, and the first peripheral transistor27are arranged in this order. In a plan view, the amplifying transistor22, the second peripheral transistor427, the second peripheral transistor827, the first peripheral transistor727, and the first peripheral transistor27may be arranged in this order. In a plan view, the amplifying transistor22, the second peripheral transistor827, the second peripheral transistor427, the first peripheral transistor27, and the first peripheral transistor727may be arranged in this order.

The matters described with reference toFIGS.24to27can be applied to the examples shown inFIGS.16to20, provided no contradiction arises.

The foregoing description has taken a front-side illumination (FSI) imaging device as an example. Note, however, that the foregoing description is also applicable to a back-side illumination (BSI) imaging device.

FIG.28is a schematic view of a back-side illumination imaging device100C according to one example.

In the imaging device100C shown inFIG.28, the semiconductor substrate130has a front surface130aand a back surface130b. The back surface130bis a surface on which light falls. The front surface130ais a surface opposite to the surface on which light falls.

On the back surface130b, a photoelectric converter10is stacked. On the photoelectric converter10, a color filter84is stacked. On the color filter84, an on-chip lens85is stacked. In a typical example, the semiconductor substrate130and the photoelectric converter10are joined to each other by joining the photoelectric converter10to the back surface130bwith the back surface130bpolished. The color filter84and the on-chip lens85may be omitted. At least either between the photoelectric converter10and the color filter84or between the color filter84and the on-chip lens85, an interlayer insulator film intended for planarization, protection, or other purposes may be provided.

On the front surface130a, a wiring layer86is stacked. The wiring layer86has a plurality of wires87provided inside an insulator. The plurality of wires87are used for electrical connections to the amplifying transistor22, the first peripheral transistor27, and the second peripheral transistor427. For example, a wire87constitutes part of an electrical pathway88electrically connecting the pixel electrode11of the photoelectric converter10to the gate electrode67cof the amplifying transistor22. Specifically, in this example, the electrical pathway88includes a through-silicon via (TSV) provided in the semiconductor substrate130.FIG.28omits to illustrate the through-silicon via. InFIG.28, the dotted line representing the electrical pathway88is schematic, and is not intended to limit the position or other features of the electrical pathway88. Instead of the TSV connection, a Cu—Cu connection may be employed.

Although not illustrated in detail inFIG.28, the amplifying transistor22, the first peripheral transistor27, and the second peripheral transistor427may have the features described with reference toFIGS.1to27. The same applies to other elements such as the photoelectric converter10. Specifically, in this example, the first peripheral transistor27and the second peripheral transistor427include sources, drains, extension diffusion layers, pocket diffusion layers, or other elements. The semiconductor substrate130includes a supporting substrate140.

The imaging device100C further includes a photodiode80and a transfer transistor29. The photodiode80and the transfer transistor29are provided in the semiconductor substrate130. Specifically, the pixel region R1has the photodiode80provided in the pixel substrate portion. As mentioned above, the term “pixel substrate portion” refers to a portion of at least one semiconductor substrate130located in the pixel region R1.

As is the case with the photoelectric converter10, the photodiode80falls under the category of photoelectric converters. The photodiode80generates signal charge through photoelectric conversion. The transfer transistor29transfers this signal charge to a charge accumulation region (not illustrated).

According to the back-side illumination configuration shown inFIG.28, the irradiation of the photodiode80with light from the on-chip lens85and the color filter84is not prevented by a wire87of the wiring layer86. This enables the photodiode80to carry out efficient photoelectric conversion.

FIGS.29to32are schematic views showing shapes that the pixel region R1, first peripheral region R2, and second peripheral region R3of the imaging device100C shown inFIG.28may take.

In the example shown inFIG.29, the second peripheral region R3surrounds the pixel region R1in a plan view. The first peripheral region R2surrounds the second peripheral region R3in a plan view. Specifically, in the example shown inFIG.29, the second peripheral region R3exhibits a square shape outside the pixel region R1in a plan view. The first peripheral region R2exhibits a square shape outside the second peripheral region R3in a plan view.

In the example shown inFIG.30, the second peripheral region R3exhibits a U-shape outside the pixel region R1in a plan view. The first peripheral region R2exhibits a U-shape outside the second peripheral region R3in a plan view.

In the example shown inFIG.31, the second peripheral region R3exhibits an L-shape outside the pixel region R1in a plan view. The first peripheral region R2exhibits an L-shape outside the second peripheral region R3in a plan view.

In the example shown inFIG.32, the second peripheral region R3extends straight outside the pixel region R1in a plan view. The first peripheral region R2extends straight outside the second peripheral region R3in a plan view.

The shapes of the pixel region R1, the first peripheral region R2, and the second peripheral region R3shown inFIGS.29to32are also applicable to the imaging device100C shown inFIG.28. Further, these shapes are also applicable to the imaging devices100A and100B shown inFIGS.1to27.

The foregoing description has taken, as an example, an imaging device including a single semiconductor substrate. Note, however, that the foregoing description is also applicable to a so-called chip stack imaging device in which a plurality of semiconductor substrates are stacked on top of each other. The chip stack imaging device may also be referred to as “stacked chip imaging device”.

FIG.33is a schematic view of a chip stack imaging device100D according to one example.

In the imaging device100D shown inFIG.33, a semiconductor substrate130A and a semiconductor substrate130B are stacked on top of each other. The semiconductor substrate130A is provided with a pixel region R1and a first peripheral region R2. The semiconductor substrate130B is provided with a peripheral circuit120C. The peripheral circuit120C may include some or all of circuits that are equivalent to the peripheral circuit120A or the peripheral circuit120B.

Although not illustrated, at least either a TSV connection or a Cu—Cu connection may be utilized as an electrical connection between a device provided in the semiconductor substrate130A and a device provided in the semiconductor substrate130B.

The pixel region R1has an amplifying transistor22. The first peripheral region R2has a first peripheral transistor27.

In one example, in the imaging device100D, the first peripheral transistor27is a load transistor. The pixel region R1is connected to the load transistor via a vertical signal line35. Specifically, the amplifying transistor22is connected to the load transistor via the vertical signal line35.

In one specific example, the aforementioned load transistor functions as a constant current source. A constant current determined by the load transistor flows through the amplifying transistor22, the vertical signal line35, and the load transistor in this order. The amplifying transistor22and the load transistor form a source follower. For this reason, a voltage corresponding to the gate voltage of the amplifying transistor22, i.e. the voltage of a charge accumulation region Z, appears in the vertical signal line35. This state continues as long as the address transistor24is on. The load transistor may be included in the load circuit45shown inFIG.2. It should be noted that the load transistor may also be referred to as “load cell transistor”.

In the imaging device100D, the first peripheral transistor27may be included in at least either a comparator or a driver.

In the example shown inFIG.33, the first peripheral transistor27may or may not be included in the peripheral circuit120C. In the example shown inFIG.33, a second peripheral region R3may be provided outside the first peripheral region R2.

In each of the examples shown inFIGS.28to33too, the first peripheral transistor27includes a strain-introducing layer. This brings a strain to the first channel region303, bringing about improvement in the mobility of the N-type channel diffusion layer303, which serves as the first channel region. Further, the first specific layer contains a diffusion-suppressing species. This brings about a diffusion-suppressing action. This may reduce dark current in the pixel region R1while reducing the deterioration in performance of the first peripheral transistor27attributed to thermal processing.

In each of the examples shown inFIGS.28to33, the pixel region R1, the first peripheral region R2, and the second peripheral region R3may have the features described with reference toFIGS.1to27. For example, the pixel region R1may include an address transistor24, a reset transistor26, or other devices in addition to the amplifying transistor22. The first peripheral region R2may include a first peripheral transistor727in addition to the first peripheral transistor27. The second peripheral region R3may include a second peripheral transistor827in addition to the second peripheral transistor427.

The following describes another embodiment. Elements that are common to the embodiment already described and the embodiment to be described later are given the same reference signs, and a description of the elements may be omitted. The description of one embodiment can be applied to the other embodiment, provided no technical contradiction arises. One embodiment may be combined with the other embodiment, provided no technical contradiction arises.

The following describes Embodiment 2 of the present disclosure with reference toFIGS.34to48B. In Embodiment 2, the semiconductor substrate130is denoted by “semiconductor substrate130A”. The supporting substrate140is denoted by “supporting substrate140A”.

In Embodiment 2, any part or the whole of the peripheral circuit120A is formed in the semiconductor substrate130B. The peripheral circuit120A is located in a first peripheral region R2provided in the semiconductor substrate130B. The semiconductor substrate130A and the semiconductor substrate130B are stacked on top of each other.

FIG.34is a schematic cross-sectional view showing a pixel region R1, a first peripheral region R2, and a blocking region. This is a cross-section of two representative ones of the plurality of pixels110. The semiconductor substrates130A and the semiconductor substrate130B are stacked on top of each other. Specifically, the semiconductor substrates130A and the semiconductor substrate130B are stacked with an insulating part90B, which is an interlayer insulating layer, sandwiched therebetween.

The semiconductor substrate130B may have features that are similar to features that the semiconductor substrate130A may have. The same applies to the after-mentioned semiconductor substrate130C.

The semiconductor substrate130B has a supporting substrate140B. The supporting substrate140B may have features that are similar to features that the supporting substrate140A may have. For example, as in the case of the supporting substrate140A, each of the impurity layers and impurity regions located above the supporting substrate140B is formed by ion implantation of an impurity into an epitaxial layer obtained by epitaxial growth over the supporting substrate140B. In these respects, the same applies to a supporting substrate of the semiconductor substrate130C. The following takes a p-type silicon substrate as an example of the supporting substrate140B.

Transistors of Pixel Regions and Peripheral Regions

The following further describes transistors of pixel regions and transistors of peripheral regions with reference toFIGS.35to42.FIGS.35,36,37,38,39,40,41, and42are schematic perspective views illustrating transistors of pixel regions and transistors of peripheral regions. It should be noted thatFIGS.35to42omit to illustrate the blocking regions200A and200B.

As shown inFIGS.39and40, the imaging device may include a second peripheral region R3.

The pixel region R1may be constituted using one semiconductor substrate, and the first peripheral region R2may be constituted using another semiconductor substrate. The pixel region R1may be constituted using one semiconductor substrate, the first peripheral region R2may be constituted using another semiconductor substrate, and the second peripheral region R3may be constituted using still another semiconductor substrate. The pixel region R1may be constituted using one semiconductor substrate, and the first peripheral region R2and the second peripheral region R3may be constituted using another semiconductor substrate. The pixel region R1and the second peripheral region R3may be constituted using one semiconductor substrate, and the first peripheral region R2may be constituted using another semiconductor substrate. Thus, in the present embodiment, the imaging device may have a plurality of semiconductor substrates.

In the following, the terms “pixel substrate portion”, “first peripheral substrate portion”, and “second peripheral substrate portion” are sometimes used. The pixel substrate portion may be a portion of a plurality of semiconductor substrates included in the pixel region R1. The first peripheral substrate portion may be a portion of a plurality of semiconductor substrates included in the first peripheral region R2. The second peripheral substrate portion may be a portion of a plurality of semiconductor substrates included in the second peripheral region R3.

The pixel substrate portion may be included in one semiconductor substrate, the first peripheral substrate portion may be included in another semiconductor substrate, and the second peripheral substrate portion may be included in still another semiconductor substrate. The pixel substrate portion may be included in one semiconductor substrate, and the first peripheral substrate portion and the second peripheral substrate portion may be included in another semiconductor substrate. The pixel substrate portion and the second peripheral substrate portion may be included in one semiconductor substrate, and the first peripheral substrate portion may be included in another semiconductor substrate.

In each of the examples shown inFIGS.35and36, the first peripheral region R2and the pixel region R1are stacked on top of each other. The pixel region R1is constituted using the semiconductor substrate130A. The first peripheral region R2is constituted using the semiconductor substrate130B.

FIG.35schematically shows an amplifying transistor22in the pixel region R1and a first peripheral transistor27in the first peripheral region R2in a case where the first peripheral region R2is in the shape of a rectangle in a plan view.FIG.36schematically shows an amplifying transistor22in the pixel region R1and a first peripheral transistor27in the first peripheral region R2in a case where the first peripheral region R2is in the shape of a frame in a plan view. Specifically, inFIG.36, the first peripheral region R2is in the shape of a square in a plan view. The first peripheral region R2may be in the shape of letter L or in the shape of letter U in a plan view.

As can be understood from the description with reference toFIGS.34to36, an imaging device according to the present embodiment includes a pixel region R1and a first peripheral region R2. The pixel region R1has a pixel substrate portion. The first peripheral region R2has a first peripheral substrate portion. The pixel substrate portion and the first peripheral substrate portion are stacked on top of each other. The expression “the pixel substrate portion and the first peripheral substrate portion are stacked on top of each other” is intended to encompass both an embodiment in which an inclusion is interposed between the pixel substrate portion and the first peripheral substrate portion and an embodiment in which no inclusion is interposed between the pixel substrate portion and the first peripheral substrate portion. Typically, the pixel substrate portion and the first peripheral substrate portion are stacked with an insulating part sandwiched therebetween. The insulating part may correspond to the insulating layer90B which is an interlayer insulating layer, ofFIG.34.

The following describes an example of a situation in Embodiment 2 where a technique involving the use of a first specific layer may contribute to such improvement in performance as that noted above.

In the imaging device of the present embodiment, the pixel substrate portion included in the pixel region R1and the first peripheral substrate portion included in the first peripheral region R2are stacked on top of each other. In the process of manufacturing an imaging device, the first peripheral region R2may be heated for the following reasons. First, the first peripheral region R2may be heated by heat that is supplied in forming the first peripheral region R2. Second, in a case where the first peripheral region R2and the pixel region R1are separately formed and then those regions are joined to each other, the first peripheral region R2may be heated by heating for the joining. Third, in a case where the pixel region R1is subjected to heat treatment after a stacked structure including the first peripheral region R2and the pixel region R1has been formed, the first peripheral region R2may be heated too by the heat treatment. Heating the first peripheral transistor27of the first peripheral region R2may cause diffusion of a conductive impurity. The diffusion of the conductive impurity may cause deterioration in performance of the first peripheral transistor27. The deterioration in performance of the first peripheral transistor27may cause deterioration in performance of the imaging device as a whole. However, in one example of the present embodiment, the first specific layer contains the diffusion-suppressing species. The diffusion-suppressing species may contribute to the suppression of the diffusion of the conductive impurity. This diffusion-suppressing action may reduce the deterioration in performance of the first peripheral transistor27.

The heat treatment stated as the third reason why the first peripheral region R2may be heated is further described. The heat treatment may reduce defects in the pixel substrate portion in the pixel region R1. Reducing defects may reduce dark current in the imaging device. Meanwhile, in the first peripheral region R2, the necessity to reduce defects is not necessarily great. On the contrary, in the first peripheral region R2, there is a case where it is necessary to reduce deterioration in performance of the first peripheral transistor27attributed to the diffusion of the conductive impurity entailed by the heat treatment. The deterioration in performance is for example an undesirable change in threshold voltage of the first peripheral transistor27.

In one example, the pixel region R1has t the photoelectric conversion layer12. The photoelectric conversion layer12, the pixel substrate portion, and the first peripheral substrate portion are stacked on top of each other. In a typical example, in a case where a pixel region R1having such a configuration is fabricated, such heat treatment as noted above is executed. For this reason, an imaging device including a pixel region R1having this configuration may enjoy the effect of reducing dark current while reducing the deterioration in performance of the first peripheral transistor27.

In one example, a method for manufacturing the imaging device includes, in this order, the step of fabricating a stacked structure including the pixel substrate portion and the first peripheral substrate portion and the step of heating the pixel substrate portion in the stacked structure. In such a manufacturing method, heating of the pixel substrate portion may cause the first peripheral substrate portion to be heated too. In this case, the effect of reducing dark current while reducing the deterioration in performance of the first peripheral transistor27can be enjoyed. In one specific example, the second step involves thermal processing for recovery of various crystal defects and defect levels in the pixel substrate portion, particularly the vicinity of a charge accumulation portion. Such heating intended for the pixel substrate portion may cause the first peripheral substrate portion to be heated too. The imaging device may also be manufactured by another manufacturing method.

In each of the examples shown inFIGS.37and38, there are a plurality of first peripheral transistors27in the first peripheral region R2. The first peripheral region R2and the pixel region R1are stacked on top of each other. The pixel region R1is constituted using the semiconductor substrate130A. The first peripheral region R2is constituted using the semiconductor substrate130B.

FIG.37schematically shows an amplifying transistor22in the pixel region R1and a plurality of first peripheral transistors27in the first peripheral region R2in a case where the first peripheral region R2is in the shape of a rectangle in a plan view.FIG.38schematically shows an amplifying transistor22in the pixel region R1and a plurality of first peripheral transistors27in the first peripheral region R2in a case where the first peripheral region R2is in the shape of a frame in a plan view. Specifically, inFIG.38, the first peripheral region R2is in the shape of a square in a plan view. The first peripheral region R2may be in the shape of letter L or in the shape of letter U in a plan view.

In each of the examples shown inFIGS.37and38, a plurality of the first peripheral transistors27are present in the first peripheral region R2. The plurality of first peripheral transistors27include a first direction transistor27aand a second direction transistor27b.

As shown inFIGS.39and40, the imaging device may include a second peripheral region R3. The second peripheral region R3has a second peripheral transistor427.

In each of the examples shown inFIGS.39and40, the first peripheral region R2and the pixel region R1are stacked on top of each other. The second peripheral region R3and the pixel region R1are stacked on top of each other. The pixel region R1is constituted using the semiconductor substrate130A. The first peripheral region R2and the second peripheral region R3are constituted using the semiconductor substrate130B. In a plan view, the second peripheral region R3is located outside the first peripheral region R2. In the example shown inFIG.39, the second peripheral region R3is in the shape of letter L in a plan view. In the example shown inFIG.40, the second peripheral region R3is in the shape of a frame in a plan view and surrounds the first peripheral region R2. Specifically, inFIG.40, the second peripheral region R3is in the shape of a square in a plan view. The second peripheral region R3may be in the shape of letter U in a plan view.

As can be understood from the foregoing description, the imaging device according to each of the examples shown inFIGS.39and40includes a second peripheral region R3. The second peripheral region R3has a second peripheral substrate portion and a second peripheral transistor427. The second peripheral transistor427is provided in the second peripheral substrate portion. The first peripheral substrate portion and the second peripheral substrate portion are included in the semiconductor substrate130B. In each of the examples shown inFIGS.39and40, the second peripheral region R3is located outside the first peripheral region R2.

Of course, a transistor other than the transistors shown inFIGS.39and40may be provided. In each of the examples shown inFIGS.41and42, the first peripheral region R2has a first peripheral transistor27and a first peripheral transistor727. A device isolation220is disposed between the first peripheral transistor27and the first peripheral transistor727. The second peripheral region R3has a second peripheral transistor427and a second peripheral transistor827.

In a plan view, the second peripheral region R3is located outside the first peripheral region R2. In the example shown inFIG.41, the second peripheral region R3is in the shape of letter L in a plan view. In the example shown inFIG.42, the second peripheral region R3is in the shape of a frame in a plan view and surrounds the first peripheral region R2. Specifically, inFIG.42, the second peripheral region R3is in the shape of a square in a plan view. The second peripheral region R3may be in the shape of letter U in a plan view.

The device isolation220is disposed between the second peripheral transistor427and the second peripheral transistor827.

The matters described with reference toFIGS.41and42can be applied to the examples shown inFIGS.35to38, provided no contradiction arises.

The foregoing description has taken a front-side illumination imaging device as an example. Note, however, that the foregoing description is also applicable to a back-side illumination imaging device.

FIG.43is a schematic view of a back-side illumination imaging device100E according to one example.

In the imaging device100E shown inFIG.43, the semiconductor substrate130A has a front surface130aand a back surface130b. The back surface130bis a surface on which light falls. The front surface130ais a surface opposite to the surface on which light falls.

On the back surface130b, a photoelectric converter10is stacked. On the photoelectric converter10, a color filter84is stacked. On the color filter84, an on-chip lens85is stacked. In a typical example, the semiconductor substrate130A and the photoelectric converter10are joined to each other by joining the photoelectric converter10to the back surface130bwith the back surface130bpolished. The color filter84and the on-chip lens85may be omitted. Further, at least either between the photoelectric converter10and the color filter84or between the color filter84and the on-chip lens85, an interlayer insulator film intended for planarization, protection, or other purposes may be provided.

On the front surface130a, a wiring layer86is stacked. The wiring layer86has a plurality of wires87provided inside an insulator. The plurality of wires87are used for electrical connections to the amplifying transistor22, the first peripheral transistor27, and the second peripheral transistor427. For example, a wire87constitutes part of an electrical pathway88electrically connecting the pixel electrode11of the photoelectric converter10to the gate electrode67cof the amplifying transistor22. Specifically, in this example, the electrical pathway88includes a through-silicon via (TSV) provided in the semiconductor substrate130A.FIG.43omits to illustrate the through-silicon via. InFIG.43, the dotted line representing the electrical pathway88is schematic, and is not intended to limit the position or other features of the electrical pathway88. Instead of the TSV connection, a Cu—Cu connection may be employed.

FIG.49is a schematic view of a back-side illumination imaging device100F according to another example.

In the imaging device100F shown inFIG.49, the semiconductor substrate130A has a front surface130aand a back surface130b. The back surface130bis a surface on which light falls. The front surface130ais a surface opposite to the surface on which light falls.

As in the case of the imaging device100E shown inFIG.43, on the back surface130b, a photoelectric converter10is stacked. On the photoelectric converter10, a color filter84is stacked. On the color filter84, an on-chip lens85is stacked. In a typical example, the semiconductor substrate130A and the photoelectric converter10are joined to each other by joining the photoelectric converter10to the back surface130bwith the back surface130bpolished. The color filter84and the on-chip lens85may be omitted. Further, at least either between the photoelectric converter10and the color filter84or between the color filter84and the on-chip lens85, an interlayer insulator film intended for planarization, protection, or other purposes may be provided.

On the front surface130a, a wiring layer86is stacked. The wiring layer86has a plurality of wires87provided inside an insulator. The plurality of wires87are used for electrical connections to the amplifying transistor22, the first peripheral transistor27, and the second peripheral transistor427. For example, a wire87constitutes part of an electrical pathway88electrically connecting the pixel electrode11of the photoelectric converter10to the gate electrode67cof the amplifying transistor22. Specifically, in this example, the electrical pathway88includes a through-silicon via (TSV) provided in the semiconductor substrate130A.FIG.49omits to illustrate the through-silicon via. InFIG.49, the dotted line representing the electrical pathway88is schematic, and is not intended to limit the position or other features of the electrical pathway88. Instead of the TSV connection, a Cu—Cu connection may be employed.

In the imaging device100F, the wiring layer86, a wiring layer186, and the semiconductor substrate130B are stacked in this order. The wiring layer186has a plurality of wires187provided inside an insulator. The wiring layer86and the wiring layer186are electrically connected to each other. The electrical connection between the wiring layer86and the wiring layer186may be a Cu—Cu connection or may be a TSV connection.

Although not illustrated in detail inFIGS.43and49, the amplifying transistor22, the first peripheral transistor27, and the second peripheral transistor427may have the features described earlier. The same applies to other elements such as the photoelectric converter10. Specifically, in this example, the first peripheral transistor27and the second peripheral transistor427include sources, drains, extension diffusion layers, pocket diffusion layers, or other elements. The semiconductor substrate130A includes a supporting substrate140A. The semiconductor substrate130B includes a supporting substrate140B.

In the following, imaging devices according to specific examples of the present disclosure are described with reference toFIGS.44A to48B.FIGS.44A to48Bomit to illustrate the photoelectric conversion layer12, the channel region, the first epitaxial layer135, the second epitaxial layer136, the third epitaxial layer137, or other components. In each ofFIGS.44A,45A,46A,47A, and48A, the solid or dotted lines in the semiconductor substrates130A,130B, or130C schematically represent the boundaries of a region in which an impurity spreads. The dotted lines schematically represent the boundaries of a region in which a diffusion-suppressing species spreads. In each ofFIGS.44A,45A,46A,47A, and48A, a carbon-implanted layer311Aa or a carbon-implanted layer311Ab are illustrated by dotted lines. The insulating parts90A to90C may correspond to the interlayer insulating layers described earlier.

FIG.44Ais a schematic cross-sectional view of an imaging device according to a first specific example.FIG.44Bis a schematic perspective view of the imaging device according to the first specific example.FIG.44Aomits to illustrate the second peripheral transistor427. In the imaging device according to the first specific example, the pixel region R1is constituted using a semiconductor substrate130A. The first peripheral region R2and the second peripheral region R3are constituted using a semiconductor substrate130B. The first peripheral region R2is surrounded by the second peripheral region R3. In the first specific example, the semiconductor substrate130B, the insulating part90B, the semiconductor substrate130A, the insulating part90A, and the photoelectric conversion layer12are stacked in this order. An output section that outputs a pixel signal is provided near a peripheral edge of the pixel region R1. This makes it possible to shorten the length of a wire that leads a pixel signal from the pixel region R1to the second peripheral region R3. This is advantageous from the point of view of securing transfer speed.

In a modification (not illustrated) of the first specific example, the semiconductor substrate130A, the insulating part90A, the semiconductor substrate130B, the insulating part90B, and the photoelectric conversion layer12are stacked in this order. In this modification, a transistor that can be manufactured by a low-temperature process may be utilized as at least one selected from the group consisting of the first peripheral transistor27and the second peripheral transistor427. The low-temperature process may contribute to the securement of the performance of a peripheral transistor, as the low-temperature can better suppress the diffusion of a conductive impurity than a high-temperature process. Examples of transistors that can be manufactured by the low-temperature process include silicon transistors, germanium transistors, carbon nanotube transistors, TMD (transition metal dichalcogenide) transistors, and oxide semiconductor transistors. Examples of oxide semiconductors of oxide semiconductor transistors include IGZO constituted by In—Ga—Zn—O, IAZO constituted by In—Al—Zn—O, and ITZO constituted by In—Sn—Zn—O. Examples of TMD transistors include molybdenum sulfide (MoS2) transistors and tungsten sulfide (WS2) transistors. In a case where a silicon transistor is utilized, it is also possible to use a low-temperature diffusion process, such as solid-phase epitaxial regrowth (SPER), by which an amorphized diffusion layer regrows in a solid phase in a range of approximately 400° C. to 650° C.

FIG.45Ais a schematic cross-sectional view of an imaging device according to a second specific example.FIG.45Bis a schematic perspective view of the imaging device according to the second specific example.FIG.46Ais a schematic cross-sectional view of an imaging device according to a third specific example.FIG.46Bis a schematic perspective view of an imaging device according to the third specific example. In each of the imaging devices according to the second and third specific examples, the pixel substrate portion included in the pixel region R1, the first peripheral substrate portion included in the first peripheral region R2, and the second peripheral substrate portion included in the second peripheral region R3are stacked on top of each other. In each of the second and third specific examples, the pixel region R1is constituted using a semiconductor substrate130A. The first peripheral region R2is constituted using a semiconductor substrate130B. The second peripheral region R3is constituted using a semiconductor substrate130C. The pixel substrate portion, the first peripheral substrate portion, and the second peripheral substrate portion are isolated by insulator films or other films, are electrically joined, for example, via plugs, and can exchange signals.

In the second specific example shown inFIGS.45A and45B, the first peripheral substrate portion included the first peripheral region R2, the second peripheral substrate portion included in the second peripheral region R3, and the pixel substrate portion included in the pixel region R1are stacked in this order. The semiconductor substrate130B, the semiconductor substrate130C, and the semiconductor substrate130A are stacked in this order. The gate length of the second peripheral transistor427of the second peripheral region R3is longer than the gate length of the first peripheral transistor27of the first peripheral region R2. This makes it easy to keep the first peripheral transistor27, which is relatively short in gate length and susceptible to noise, distant from the pixel region R1. This makes it hard for pixel characteristics to be affected by noise from the first peripheral transistor27. Further, the second peripheral transistor427, which is relatively long in gate length, can be easily held close to the pixel region R1. This makes it easy to secure the transfer speed of signal charge from the pixel region R1to the second peripheral transistor427.

Specifically, in the second specific example, the semiconductor substrate130B, the insulating part90B, the semiconductor substrate130C, the insulating part90C, the semiconductor substrate130A, the insulating part90A, and the photoelectric conversion layer12are stacked in this order.

In the third specific example shown inFIGS.46A and46B, the second peripheral substrate portion included in the second peripheral region R3, the first peripheral substrate portion included in the first peripheral region R2, and the pixel substrate portion included in the pixel region R1are stacked in this order. The semiconductor substrate130C, the semiconductor substrate130B, and the semiconductor substrate130A are stacked in this order. The first peripheral transistor27of the first peripheral region R2has a first extension diffusion layer that is shallow in junction depth. In the first extension diffusion layer, which is shallow in junction depth, diffusion of a conductive impurity of the first extension diffusion layer by heat easily causes variations in characteristic of the first peripheral transistor27. However, in the third specific example, in which the second peripheral region R3, the first peripheral region R2, and the pixel region R1are stacked in this order, the second peripheral region R3, the first peripheral region R2, and the pixel region R1can be formed in this order in the process of manufacturing the imaging device. This makes it hard for the first peripheral region R2to be affected by heat in the formation of the second peripheral region R3. This makes it possible to suppress the diffusion layer redistribution of the conductive impurity of the first extension diffusion layer and reduce variations in characteristic of the first peripheral transistor27.

Specifically, in the third specific example, the semiconductor substrate130C, the insulating part90C, the semiconductor substrate130B, the insulating part90B, the semiconductor substrate130A, the insulating part90A, and the photoelectric conversion layer12are stacked in this order.

FIG.47Ais a schematic cross-sectional view of an imaging device according to a fourth specific example.FIG.47Bis a schematic perspective view of the imaging device according to the fourth specific example.FIG.48Ais a schematic cross-sectional view of an imaging device according to a fifth specific example.FIG.48Bis a schematic perspective view of the imaging device according to the fifth specific example. In each of the imaging devices according to the fourth and fifth specific examples, the pixel substrate portion included in the pixel region R1is included in a semiconductor substrate130A. The first peripheral substrate portion included in the first peripheral region R2and the second peripheral substrate portion included in the second peripheral region R3each have a portion included in a semiconductor substrate130B. The first peripheral transistor27and the second peripheral transistor427, which are N-channel transistors, are provided in the semiconductor substrate130B. The first peripheral substrate portion included in the first peripheral region R2and the second peripheral substrate portion included in the second peripheral region R3each have a portion included in a semiconductor substrate130C. The first peripheral transistor727and the second peripheral transistor827, which are P-channel transistors, are provided in the semiconductor substrate130C. The semiconductor substrate130A, the semiconductor substrate130B, and the semiconductor substrate130C are stacked on top of each other. Specifically, in both the semiconductor substrate130B and the semiconductor substrate130C, the second peripheral region R3is located outside the first peripheral region R2in a plan view. More specifically, in both the semiconductor substrate130B and the semiconductor substrate130C, the second peripheral region R3is in the shape of a frame surrounding the first peripheral region R2in a plan view.

In each of the fourth and fifth specific examples, the N-channel transistors and the P-channel transistors are provided in semiconductor substrates that are different from each other. This configuration makes it easy to optimize a process step such as a stacking order of semiconductor substrates in consideration of a change in thermal stability due to diffusion of a p-type impurity and a change in thermal stability due to diffusion of an n-type impurity. Further, in each of the fourth and fifth specific examples, the N-channel transistors and the P-channel transistors are provided not in one semiconductor substrate spreading in the same plane but in stacked semiconductor substrates that are different from each other. This configuration makes it easy to reduce the area of a CMOS circuit. For example, this configuration makes it possible to, as in the case of a CFET (complementary FET), form a CMOS by vertically stacking an NFET and a PFET that constitute the CMOS. This makes it easy to reduce the area of a CMOS circuit. The term “vertically stacking” here means staking along a direction parallel with the thickness of a semiconductor substrate. Furthermore, it is also possible to provide the first peripheral transistors and the second peripheral transistors in semiconductor substrates that are different from each other. This makes it easier to reduce the area.

Specifically, in each of the fourth and fifth specific examples, the first peripheral transistor727is provided in the first peripheral region R2in the semiconductor substrate130B. The second peripheral transistor827is provided in the second peripheral region R3in the semiconductor substrate130B. The first peripheral transistor27is provided in the first peripheral region R2in the semiconductor substrate130C. The second peripheral transistor427is provided in the second peripheral region R3in the semiconductor substrate130C. The first peripheral transistor727is an N-type transistor, and an operating voltage of the first peripheral transistor727is a first voltage. The second peripheral transistor827is an N-type transistor, and an operating voltage of the second peripheral transistor827is a second voltage. The first peripheral transistor27is a P-type transistor, and an operating voltage of the first peripheral transistor27is the first voltage. The second peripheral transistor427is a P-type transistor, and an operating voltage of the second peripheral transistor427is the second voltage. The first voltage is lower than the second voltage. The first voltage is for example 1.2 V. The second voltage is for example 3.3 V.

The transistors may contain boron (B) as a p-type impurity. The transistors may contain arsenic (As) as an n-type impurity. Boron (B) is more prone to transient enhanced diffusion than arsenic (As). In the fifth specific example shown inFIGS.48A and48B, the semiconductor substrate130B, the semiconductor substrate130C, and the semiconductor substrate130A are stacked in this order. For this reason, in the fifth specific example, the semiconductor substrate130C, which has a p-type impurity, can be formed after the semiconductor substrate130B, which has an n-type impurity, has been formed. This makes it hard for the first peripheral transistor27and the second peripheral transistor427, which are P-channel transistors, to be affected by heat in the formation of the semiconductor substrate130B. This configuration is advantageous from the point of view of suppressing transient enhanced diffusion of a conductive impurity.

Meanwhile, in the fourth specific example shown inFIGS.47A and47B, the semiconductor substrate130C, the semiconductor substrate130B, and the semiconductor substrate130A are stacked in this order. In a case where this configuration is adopted, the action of the suppression of transient enhanced diffusion expressed in the first specific layer is easily made use of.

In each of the first to fifth specific examples, the first specific layer may be provided in both the first peripheral transistor27and the first peripheral transistor727or only either the first peripheral transistor27or the first peripheral transistor727. The first specific layer may be provided in neither the first peripheral transistor27nor the first peripheral transistor727. The second specific layer may be provided in both the second peripheral transistor427and the second peripheral transistor827or only either the second peripheral transistor427or the second peripheral transistor827. The second specific layer may be provided in neither the second peripheral transistor427nor the second peripheral transistor827.

In each of the first to fifth specific examples, the first peripheral transistor27has a configuration according to the first configuration example described with reference toFIGS.5A and5B. Note, however, in each of the first to fifth specific examples, the first peripheral transistor27may have a configuration according to the second configuration example described with reference toFIGS.6A and6D. The same applies to the second peripheral transistor427, the first peripheral transistor727, and the second peripheral transistor827.

Various changes are applicable to the techniques disclosed here. For example, the pocket diffusion layer707aand pocket diffusion layer707bof the first peripheral transistor727and the pocket diffusion layer807aand pocket diffusion layer807bof the second peripheral transistor827may be omitted. Further, the blocking regions200A and200B may be omitted. Further, a silicide layer may be formed over the drain, source, and gate electrode of the first peripheral transistor27.

Features connected with the second peripheral region R3may be applied to the first peripheral region R2. For example, the features of the second peripheral transistors427and827may be applied to the first peripheral transistors27and727.

Features connected with the first peripheral region R2may be applied to the second peripheral region R3. For example, the features of the first peripheral transistors27and727may be applied to the second peripheral transistors427and827.

Some of the plurality of transistors included in the pixel region R1may be vertically stacked in a vertical direction. This makes it possible to increase the area of each element. Further, substrates including stacked transistors may be bonded together to form the pixel region R1.

An imaging device disclosed here is useful, for example, in an image sensor, a digital camera, or other devices. The imaging device disclosed here can be used, for example, in a camera for medical use, a camera for use in a robot, a security camera, a car-mounted camera, or other cameras.