Memory device and manufacturing method for the same

A memory device and a manufacturing method for the same are provided. The memory device includes a stacked body structure and a staircase structure. The stacked body structure includes a first sub-stacked body structure and a second sub-stacked body structure. The staircase structure is electrically connected to the stacked body structure. The staircase structure includes a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure includes a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

BACKGROUND

Technical Field

The disclosure relates to a memory device and a manufacturing method for the same.

Description of the Related Art

With development of the semiconductor technology, semiconductor devices have become smaller in size. In the semiconductor technology, shrinking of feature sizes, and improving operation speed, efficiency, density, and cost per Integrated circuit are important objectives. For satisfy customer need and the market demand, it is important to shrink devices in size and also to maintain the electricity of devices.

SUMMARY

The present disclosure relates to a memory device and a manufacturing method for the same.

According to an embodiment, a memory device is provided. The memory device comprises a stacked body structure and a staircase structure. The stacked body structure comprises a first sub-stacked body structure and a second sub-stacked body structure. The staircase structure is electrically connected to the stacked body structure. The staircase structure comprises a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure comprises a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

According to another embodiment, a manufacturing method for a memory device is provided. The method comprises the following steps. Conductive layers and insulating layers are stacked alternately along a vertical direction to form a stacked structure. The stacked structure comprises a first stacked portion, a second stacked portion and another first stacked portion disposed along a first direction. The first stacked portion and the another first stacked portion are respectively on opposing sides of the second stacked portion. The first stacked portion and the another first stacked portion are in a staircase contact region. The second stacked portion is in a memory array region. The first stacked portion and the another first stacked portion are etched with using photoresist layers to form a staircase structure. In the staircase contact region, sizes of the photoresist layers in the first direction and/or a second direction are different from each other. The first direction, the second direction and the vertical direction are perpendicular to each other. The memory device comprises a stacked body structure and the staircase structure. The stacked body structure comprises a first sub-stacked body structure and a second sub-stacked body structure. The first sub-stacked body structure and the second sub-stacked body structure comprise the second stacked portion. The staircase structure is electrically connected to the stacked body structure, and comprises a first sub-staircase structure and a second sub-staircase structure. Each of the first sub-staircase structure and the second sub-staircase structure comprises a first staircase portion and a second staircase portion. The first sub-stacked body structure and the second sub-stacked body structure are respectively connected to the first staircase portion of the first sub-staircase structure and the first staircase portion of the second sub-staircase structure.

The above and other embodiments of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

DETAILED DESCRIPTION

The illustrations may not be necessarily drawn to scale, and there may be other embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. Moreover, the descriptions disclosed in the embodiments of the disclosure such as detailed construction, manufacturing steps and material selections are for illustration only, not for limiting the scope of protection of the disclosure. The steps and elements in details of the embodiments could be modified or changed according to the actual needs of the practical applications. The disclosure is not limited to the descriptions of the embodiments. The illustration uses the same/similar symbols to indicate the same/similar elements.

FIG.1is referred to, which is a top view diagram of a memory device according to an embodiment. The memory device comprises a stacked body structure100and a staircase structure200. The staircase structure200is electrically connected with the stacked body structure100. The staircase structure200and the stacked body structure100comprise conductive layers and insulating layers stacked alternately along a vertical direction Z. The conductive layers of the staircase structure200and the stacked body structure100are electrically connected with each other. The vertical direction Z, a first direction D1and a second direction D2may be perpendicular to each other.

In an embodiment, the staircase structure200and the stacked body structure100have the conductive layers of an amount of 96 layers. The conductive layers of the staircase structure200have conductive stair layers of 96 levels disposed as a staircase, as shown inFIG.1. The conductive layers of the staircase structure200comprise, from a bottom level to a top level, a conductive stair layer1in 1stlevel (bottom level), a conductive stair layer2in the 2ndlevel, a conductive stair layer3in the 3rdlevel . . . , to a conductive stair layer94in the 94thlevel, a conductive stair layer95in the 95thlevel, and a conductive stair layer96in the 96thlevel (top level). The staircase structure200has 96 stair units respectively having the conductive stair layer1, the conductive stair layer2, the conductive stair layer3, to the conductive stair layer94, the conductive stair layer95and the conductive stair layer96. The stair unit has a stair size E in the first direction D1, and has a stair size F in the second direction D2. However, the present disclosure is not limited thereto.

The stacked body structure100may comprise a first sub-stacked body structure110, a second sub-stacked body structure120, a third sub-stacked body structure130and a fourth sub-stacked body structure140. The first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140are in a memory array region M. The first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140may be arranged along the second direction D2. In this embodiment, each of the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140has a uniform size T1in the second direction D2. For example, the sub-stacked body structure (such as the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140) comprises a first stacked body portion101. In other words, the first sub-stacked body structure110comprises a first stacked body portion111. The second sub-stacked body structure120comprises a first stacked body portion121. The third sub-stacked body structure130comprises a first stacked body portion131. The fourth sub-stacked body structure140comprises a first stacked body portion141. The first stacked body portion101(the first stacked body portion111the first stacked body portion121, the first stacked body portion131, the first stacked body portion141) may have the uniform the size T1in the second direction D2.

Memory cells are defined in the first stacked body portions101of the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140. For example, pillar elements300may be formed in the stacked body structure100. The pillar elements300are extended through the stacked body structure100along the vertical direction Z. In an embodiment, the pillar element300comprises a channel pillar. A memory material layer is disposed between the channel pillar and the conductive layer. The memory cells of NAND flash memory array are defined in the memory material layer at intersections between the channel pillars and the conductive layers. The conductive layers are functioned as word lines. The channel pillars are electrically connected to bit lines. In an embodiment, a NAND chip is trapping layer design. In an embodiment, a NAND chip is floating gated design. In an embodiment, a NAND chip is circuit-under-array design.

The staircase structure200may comprise a first sub-staircase structure210, a second sub-staircase structure220, a third sub-staircase structure230and a fourth sub-staircase structure240. The first sub-staircase structure210, the second sub-staircase structure220, the third sub-staircase structure230and the fourth sub-staircase structure240are in a staircase contact region C. The first sub-staircase structure210comprises a first staircase portion211and a second staircase portion212. Stair levels (i.e. the 49thlevel to the 96thlevel) of the first staircase portion211are higher than stair levels (i.e. the 1stlevel to the 48thlevel) of the second staircase portion212. The first sub-stacked body structure110is connected to the first staircase portion211of the first sub-staircase structure210. The first staircase portion211of the first sub-staircase structure210is electrically connected between the second staircase portion212of the first sub-staircase structure210and the first sub-stacked body structure110.

The second sub-staircase structure220comprises a first staircase portion221and a second staircase portion222. Stair levels (i.e. the 49thlevel to the 96thlevel) of the first staircase portion221are higher than stair levels (i.e. the 1stlevel to the 48thlevel) of the second staircase portion222. The second sub-stacked body structure120is connected to the first staircase portion221of the second sub-staircase structure220. The first staircase portion221of the second sub-staircase structure220is electrically connected between the second staircase portion222of the second sub-staircase structure220and the second sub-stacked body structure120.

The first sub-stacked body structure110is between the first staircase portion211of the first sub-staircase structure210and the second staircase portion222of the second sub-staircase structure220. The second sub-stacked body structure120is between the second staircase portion212of the first sub-staircase structure210and the first staircase portion221of the second sub-staircase structure220. A size H1of the first sub-staircase structure210in the second direction D2may be smaller than the size T1of the first sub-stacked body structure110. For example, the size H1may be about the double of the size T1.

The relations among the third sub-stacked body structure130, the fourth sub-stacked body structure140, the third sub-staircase structure230and the fourth sub-staircase structure240are similar with the relations among the first sub-stacked body structure110, the second sub-stacked body structure120, the first sub-staircase structure210and the second sub-staircase structure220. For example, the third sub-staircase structure230may comprise a first staircase portion231and a second staircase portion232. The fourth sub-staircase structure240may comprise a first staircase portion241and a second staircase portion242. The third sub-stacked body structure130is connected to the first staircase portion231of the third sub-staircase structure230. The fourth sub-stacked body structure140is connected to the first staircase portion241of the fourth sub-staircase structure240. Other structural characteristics can be realized by the analogy.

The conductive layers of the first sub-stacked body structure110and the first sub-staircase structure210may be electrically insulated from the conductive layers of the second sub-stacked body structure120and the second sub-staircase structure220an insulating element410. The insulating element410is between the first sub-stacked body structure110and the second staircase portion222of the second sub-staircase structure220, between the first sub-stacked body structure110and the second sub-stacked body structure120, and between the second sub-stacked body structure120and the second staircase portion212of the first sub-staircase structure210. The relation of the insulating element420relative to the third sub-stacked body structure130, the fourth sub-stacked body structure140, the third sub-staircase structure230and the fourth sub-staircase structure240can be realized by the analogy. The insulating element410and the insulating element420may have a shape of.

The conductive layers of the first sub-staircase structure210, the second sub-stacked body structure120and the second sub-staircase structure220may be electrically insulated from the conductive layers of the third sub-staircase structure230, the third sub-stacked body structure130and of the fourth sub-staircase structure240by a dielectric element500. The dielectric element500may be between the second staircase portion212of the first sub-staircase structure210and the first staircase portion231of the third sub-staircase structure230, between the insulating element410and the third sub-stacked body structure130, between the second sub-stacked body structure120and the third sub-stacked body structure130, between the second sub-stacked body structure120and the insulating element420, and between the first staircase portion221of the second sub-staircase structure220and the second staircase portion242of the fourth sub-staircase structure240.

The conductive layers (word lines) of the first sub-stacked body structure110and the first sub-staircase structure210may be electrically connected to a word line driver610through the conductive stair layers1-96of the first sub-staircase structure210and conductive plugs (not shown) on which. The conductive layers (word lines) of the second sub-stacked body structure120and the second sub-staircase structure220may be electrically connected to a word line driver620through the conductive stair layers1-96of the second sub-staircase structure220and conductive plugs (not shown) on which. The conductive layers (word lines) of the third sub-stacked body structure130and the third sub-staircase structure230may be electrically connected to a word line driver630through the conductive stair layers1-96of the third sub-staircase structure230and conductive plugs (not shown) on which. The conductive layers (word lines) of the fourth sub-stacked body structure140and the fourth sub-staircase structure240may be electrically connected to a word line driver640through the conductive stair layers1-96of the fourth sub-staircase structure240and conductive plugs (not shown) on which. In other words, the first sub-staircase structure210, the second sub-staircase structure220, the third sub-staircase structure230and the fourth sub-staircase structure240may be referred to as effective staircase structures. In embodiments, there is no dummy staircase structure (conductive layers of which is electrically floating) disposed between the first sub-staircase structure210and the third sub-staircase structure230. Also, there is no dummy staircase structure disposed between the second sub-staircase structure220and the fourth sub-staircase structure240. Therefore, a density of effective devices on a wafer can be increased. One block of the memory cells defined in each of the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140may be selected or controlled, or erased at the same time by corresponding one of the word line driver610, the word line driver620, the word line driver630, and the word line driver640.

FIG.2is referred to, which is a top view diagram of a memory device according to another embodiment. The memory device ofFIG.2is different from the memory device ofFIG.1with the following description. Each of the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140further comprises a second stacked body portion102connected with the first stacked body portion101. The first stacked body portion111and a second stacked body portion112of the first sub-stacked body structure110are connected with each other. The first stacked body portion121and a second stacked body portion122of the second sub-stacked body structure120are connected with each other. The first stacked body portion131and a second stacked body portion132of the third sub-stacked body structure130are connected with each other. The first stacked body portion141and a second stacked body portion142of the fourth sub-stacked body structure140are connected with each other.

For example, the second stacked body portion112of the first sub-stacked body structure110is between the first stacked body portion121of the second sub-stacked body structure120and the second staircase portion212of the first sub-staircase structure210. The second stacked body portion122of the second sub-stacked body structure120is between the first stacked body portion111of the first sub-stacked body structure110and the second staircase portion222of the second sub-staircase structure220. The second stacked body portion112of the first sub-stacked body structure110is connected to the second staircase portion212of the first sub-staircase structure210, and therefore can provide a shorter electrical connection path and a lower resistance to the first sub-staircase structure210. The second stacked body portion122of the second sub-stacked body structure120is connected to the second staircase portion222of the second sub-staircase structure220, and therefore can provide a shorter electrical connection path and a lower resistance to the second sub-staircase structure220. The relations among the third sub-stacked body structure130, the fourth sub-stacked body structure140, the third sub-staircase structure230and the fourth sub-staircase structure240are similar with the relations among the first sub-stacked body structure110, the second sub-stacked body structure120, the first sub-staircase structure210and the second sub-staircase structure220. Therefore, the other structural characteristics of the second stacked body portion132of the third sub-stacked body structure130and the second stacked body portion142of the fourth sub-stacked body structure140, and relations of which relative to other elements can be realized by the analogy.

Each of the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140has a varied size in the second direction D2. For example, the first sub-stacked body structure110, the second sub-stacked body structure120, the third sub-stacked body structure130and the fourth sub-stacked body structure140individually have a L shape. A portion of the first sub-stacked body structure110away from the first sub-staircase structure210has a size T11in the second direction D2(equal to a size T1of the first stacked body portion111in the second direction D2) is smaller than a size T12of another portion of the first sub-stacked body structure110in the second direction D2adjacent to the first sub-staircase structure210(i.e. the sum of the size T1of the first stacked body portion111in the second direction D2and a size of the second stacked body portion112in the second direction D2). The size H1of the first sub-staircase structure210in the second direction D2may be smaller than the size T11of the portion of the first sub-stacked body structure110away from the first sub-staircase structure210in the second direction D2. For example, the size H1may be about the double of the size T11. The size H1of the first sub-staircase structure210may be equal to the size T12of the another portion of the first sub-stacked body structure110adjacent to the first sub-staircase structure210. Similarly, a portion of the second sub-stacked body structure120away from the second sub-staircase structure220has a size T21in the second direction D2(equal to the size T1of the first stacked body portion121in the second direction D2) is smaller than a size T22of another portion of the second sub-stacked body structure120in the second direction D2adjacent to the second sub-staircase structure220(i.e, the sum of the size T1of the first stacked body portion121in the second direction D2and a size of the second stacked body portion122in the second direction D2). A size H2of the second sub-staircase structure220in the second direction D2may be smaller than the size T21of the portion of the second sub-stacked body structure120away from the second sub-staircase structure220in the second direction D2. For example, the size H2may be about the double of the size T21. The size H2of the second sub-staircase structure220may be equal to the size T22of the another portion of the second sub-stacked body structure120adjacent to the second sub-staircase structure220in the second direction D2. Size characteristics for the third sub-stacked body structure130and the fourth sub-stacked body structure140can be realized by the analogy.

In this embodiment, stair levels (i.e. the 49thlevel to the 96thlevel) of the first staircase portion211are higher than stair levels (i.e. the 1stlevel to the 48thlevel) of the second staircase portion212of the first sub-staircase structure210. Stair levels (i.e. the 1stlevel to the 48thlevel) of the first staircase portion221are lower than stair levels (i.e. the 49thlevel to the 96thlevel) of the second staircase portion222of the second sub-staircase structure220. Stair levels (i.e. the 49thlevel to the 96thlevel) of the first staircase portion231are higher than stair levels (i.e. the 1stlevel to the 48thlevel) of the second staircase portion232of the third sub-staircase structure230. Stair levels (i.e. the 1stlevel to the 48thlevel) of the first staircase portion241are lower than stair levels (i.e. the 49thlevel to the 96thlevel) of the second staircase portion242of the fourth sub-staircase structure240. However, the present disclosure is not limited thereto. The amount and disposition for the stair levels may be varied according to actual demands for process and product.

The insulating element410is between the first stacked body portion111of the first sub-stacked body structure110and the second stacked body portion122of the second sub-stacked body structure120, between the first stacked body portion111of the first sub-stacked body structure110and the first stacked body portion121of the second sub-stacked body structure120, and between the second stacked body portion112of the first sub-stacked body structure110and the first stacked body portion121of the second sub-stacked body structure120. The relations of the insulating element420relative to the third sub-stacked body structure130and the fourth sub-stacked body structure140can be realized by the analogy.

The conductive layers of the first sub-staircase structure210, the first sub-stacked body structure110, the second sub-stacked body structure120and the second sub-staircase structure220may be electrically insulated from the conductive layers of the third sub-staircase structure230, the third sub-stacked body structure130, the fourth sub-stacked body structure140and the fourth sub-staircase structure240by the dielectric element500. The dielectric element500may be between the second staircase portion212of the first sub-staircase structure210and the first staircase portion231of the third sub-staircase structure230, between the second stacked body portion112of the first sub-stacked body structure110and the first stacked body portion131of the third sub-stacked body structure130, between the insulating element410and the first stacked body portion131of the third sub-stacked body structure130, between the first stacked body portion121of the second sub-stacked body structure120and the first stacked body portion131of the third sub-stacked body structure130, between the first stacked body portion121of the second sub-stacked body structure120and the insulating element420, between the first stacked body portion121of the second sub-stacked body structure120and the second stacked body portion142of the fourth sub-stacked body structure140, and between the first staircase portion221of the second sub-staircase structure220and the second staircase portion242of the fourth sub-staircase structure240.

FIG.3AtoFIG.3Tillustrate a manufacturing method for memory device in an embodiment. The manufacturing method comprises manufacturing steps for forming a staircase structure by performing photolithography etching processes utilizing photoresist layers of different profiles to a stacked structure700.

FIG.3Ais referred to. Conductive layers707and insulating layers708may be alternately stacked on a substrate (not shown) along the vertical direction Z to form the stacked structure700. In this embodiment, the stacked structure700may comprise the conductive layers707of an amount of 96 layers, insulated from each other by the insulating layers708. The stacked structure700comprises a first stacked portion701and a second stacked portion702arranged in the first direction D1. The first stacked portion701comprises a first stacked portion701-1and a first stacked portion701-2respectively on opposing sides of the second stacked portion702. The first stacked portion701-1and the first stacked portion701-2are in the staircase contact region C. The second stacked portion702is in the memory array region M. The second stacked portion702may be stacked body structure100. In an embodiment, a photoresist layer (not shown) may be formed to cover on the insulating layer708(such as a top insulating layer) of the second stacked portion702, and an etching step using this photoresist layer (not shown) as an etching mask may be performed to remove the exposed the insulating layer708(such as the top insulating layer) of the first stacked portion701so as to expose the conductive layer707of the 96thlevel (such as a conductive stair layer96) of the first stacked portion701. The photoresist layer may be removed then.

FIG.3Bis referred to. A photoresist layer PR1is formed on the stacked structure700. The photoresist layer PR1covers the second stacked portion702and a first sub-stacked portion7011of the first stacked portion701(comprising the first stacked portion701-1and the first stacked portion701-2), and exposes the conductive layer of the 96thlevel (i.e. the conductive stair layer96) of a second sub-stacked portion7012of the first stacked portion701. With using the photoresist layer PR1as an etching mask, the second sub-stacked portion7012is etched downward from the conductive layer of the 96thlevel (i.e. the conductive stair layer96) through 48 levels so as to expose the conductive layer of the 48thlevel (i.e. a conductive stair layer48) of the second sub-stacked portion7012. The photoresist layer PR1may be removed then. As such, a semiconductor structure as shown inFIG.3Cis formed.

Referring toFIG.3D, a photoresist layer PR2is formed on the stacked structure700. The photoresist layer PR2covers the second stacked portion702, and extends along the first direction D1to cover a portion of the first stacked portion701. That is, the photoresist layer PR2covers an inner stacked portion701G1of the first stacked portion701adjacent to the second stacked portion702, and exposes an outer stacked portion701K1of the first stacked portion701away from the second stacked portion702. With using the photoresist layer PR2as an etching mask, the outer stacked portion701K1is etched downward from the exposed the conductive layer of the 96thlevel (i.e. the conductive stair layer96) and the exposed conductive layer of the 48thlevel (i.e. the conductive stair layer48) through 4 levels so as to expose the conductive layer of the 92thlevel (i.e. a conductive stair layer92) and the conductive layer of the 44thlevel (i.e. a conductive stair layer44), respectively. Then the photoresist layer PR2(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR3(subsequent photoresist layer) shown inFIG.3E. A size of the photoresist layer PR2in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR3in the second direction D2may be identical with a size of the photoresist layer PR2in the second direction D2.

Referring toFIG.3E, a photoresist layer PR3is formed on the stacked structure700. The photoresist layer PR3covers the second stacked portion702, and an inner stacked portion701G2of the first stacked portion701, and exposes an outer stacked portion701K2of the first stacked portion701. With using the photoresist layer PR3as an etching mask, the outer stacked portion701K2is etched downward from the exposed the conductive layers (i.e. the conductive stair layer96, the conductive stair layer92, the conductive stair layer48and the conductive stair layer44) through 4 levels. As such, a semiconductor structure as shown inFIG.3Fmay be formed. Then the photoresist layer PR3(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR4(subsequent photoresist layer) shown inFIG.3G. A size of the photoresist layer PR3in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR4in the second direction D2may be identical with a size of the photoresist layer PR3in the second direction D2.

Referring toFIG.3G, a photoresist layer PR4is formed on the stacked structure700. The photoresist layer PR4covers the second stacked portion702, and an inner stacked portion701G3of the first stacked portion701, and exposes an outer stacked portion701K3of the first stacked portion701. With using the photoresist layer PR4as an etching mask, the outer stacked portion701K3is etched downward from the exposed the conductive layers (such as the conductive stair layers96,92,88,48,44and40as shown inFIG.3F) through 4 levels so as to form the conductive stair layers92,88,84,44,40and36of the outer stacked portion701K3as shown inFIG.3G. Then the photoresist layer PR4(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR5(subsequent photoresist layer) shown inFIG.3H. A size of the photoresist layer PR4in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR5in the second direction D2may be identical with a size of the photoresist layer PR4in the second direction D2.

Referring toFIG.3H, a photoresist layer PR5is formed on the stacked structure700. The photoresist layer PR5covers the second stacked portion702, and an inner stacked portion701G4of the first stacked portion701, and exposes an outer stacked portion701K4of the first stacked portion701. With using the photoresist layer PR5as an etching mask, the outer stacked portion701K4is etched downward from the exposed the conductive layers (i.e. the conductive stair layers96,92,88,84,48,44,40and36) through 4 levels so as to form the conductive stair layers92,88,84,80,44,40,36and32of the outer stacked portion701K4as shown inFIG.3H. Then the photoresist layer PR5(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR6(subsequent photoresist layer) shown inFIG.3I. A size of the photoresist layer PR5in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR6in the second direction D2may be identical with a size of the photoresist layer PR5in the second direction D2.

Referring toFIG.3I, a photoresist layer PR6is formed on the stacked structure700. The photoresist layer PR6covers the second stacked portion702, and an inner stacked portion701G5of the first stacked portion701, and exposes an outer stacked portion701K5of the first stacked portion701. With using the photoresist layer PR6as an etching mask, the outer stacked portion701K5is etched downward from the exposed the conductive layers (i.e the conductive stair layers96,92,88,84,80,48,44,40,36and32) through 4 levels so as to form the conductive stair layers92,88,84,80,76,44,40,36,32and28of the outer stacked portion701K5as shown inFIG.3I. Then the photoresist layer PR6(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR7(subsequent photoresist layer) shown inFIG.3J. A size of the photoresist layer PR6in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR7in the second direction D2may be identical with a size of the photoresist layer PR6in the second direction D2.

Referring toFIG.3J, a photoresist layer PR7is formed on the stacked structure700. The photoresist layer PR7covers the second stacked portion702, and an inner stacked portion701G6of the first stacked portion701, and exposes an outer stacked portion701K6of the first stacked portion701. With using the photoresist layer PR7as an etching mask, the outer stacked portion701K6is etched downward from the exposed the conductive layers (i.e. the conductive stair layers92,88,84,80,76,44,40,36,32and28) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,44,40,36,32,28and24of the outer stacked portion701K6as shown inFIG.3J. Then the photoresist layer PR7(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR8(subsequent photoresist layer) shown inFIG.3K. A size of the photoresist layer PR7in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR8in the second direction D2may be identical with a size of the photoresist layer PR7in the second direction D2.

Referring toFIG.3K, a photoresist layer PR8is formed on the stacked structure700. The photoresist layer PR8covers the second stacked portion702, and an inner stacked portion701G7of the first stacked portion701, and exposes an outer stacked portion701K7of the first stacked portion701. With using the photoresist layer PR8as an etching mask, the outer stacked portion701K7is etched downward from the exposed the conductive layers (i.e, the conductive stair layers92,88,84,80,76,72,44,40,36,32,28and24) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,68,44,40,36,32,28,24and20of the outer stacked portion701K7as shown inFIG.3K. Then the photoresist layer PR8(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR9(subsequent photoresist layer) shown inFIG.3L. A size of the photoresist layer PR8in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR9in the second direction D2may be identical with a size of the photoresist layer PR8in the second direction D2.

Referring toFIG.3L, a photoresist layer PR9is formed on the stacked structure700. The photoresist layer PR9covers the second stacked portion702, and an inner stacked portion701G8of the first stacked portion701, and exposes an outer stacked portion701K8of the first stacked portion701. With using the photoresist layer PR9as an etching mask, the outer stacked portion701K8is etched downward from the exposed the conductive layers (i.e. the conductive stair layers92,88,84,80,76,72,68,44,40,36,32,28,24and20) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,68,64,44,40,36,32,28,24,20and16of the outer stacked portion701K8as shown inFIG.3L. Then the photoresist layer PR9(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR10(subsequent photoresist layer) shown inFIG.3M. A size of the photoresist layer PR9in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR10in the second direction D2may be identical with a size of the photoresist layer PR9in the second direction D2.

Referring toFIG.3M, a photoresist layer PR10is formed on the stacked structure700. The photoresist layer PR10covers the second stacked portion702, and an inner stacked portion701G9of the first stacked portion701, and exposes an outer stacked portion701K9of the first stacked portion701. With using the photoresist layer PR10as an etching mask, the outer stacked portion701K9is etched downward from the exposed the conductive layers (i.e. the conductive stair layers92,88,84,80,76,72,68,64,44,40,36,32,28,24,20and16) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,68,64,60,44,40,36,32,28,24,20,16and12of the outer stacked portion701K9as shown inFIG.3M. Then the photoresist layer PR10(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR11(subsequent photoresist layer) shown inFIG.3N. A size of the photoresist layer PR10in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR11in the second direction D2may be identical with a size of the photoresist layer PR10in the second direction D2.

Referring toFIG.3N, a photoresist layer PR11is formed on the stacked structure700. The photoresist layer PR11covers the second stacked portion702, and an inner stacked portion701G10of the first stacked portion701, and exposes an outer stacked portion701K10of the first stacked portion701. With using the photoresist layer PR11as an etching mask, the outer stacked portion701K10is etched downward from the exposed the conductive layers (i.e. the conductive stair layers92,88,84,80,76,72,68,64,60,44,40,36,32,28,24,20,16and12) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,68,64,60,56,44,40,36,32,28,24,20,16,12and8of the outer stacked portion701K10as shown inFIG.3N. Then the photoresist layer PR11(previous photoresist layer) may be trimmed by the stair size E in the first direction D1to form a photoresist layer PR12(subsequent photoresist layer) shown inFIG.3O. A size of the photoresist layer PR11in the second direction D2may be not trimmed, and therefore a size of the photoresist layer PR12in the second direction D2may be identical with a size of the photoresist layer PR11in the second direction D2.

Referring toFIG.3O, a photoresist layer PR12is formed on the stacked structure700. The photoresist layer PR12covers the second stacked portion702, and an inner stacked portion701G11of the first stacked portion701, and exposes an outer stacked portion701K11of the first stacked portion701. With using the photoresist layer PR12as an etching mask, the outer stacked portion701K11is etched downward from the exposed the conductive layers (i.e. the conductive stair layers92,88,84,80,76,72,68,64,60,56,44,40,36,32,28,24,20,16,12and8) through 4 levels so as to form the conductive stair layers92,88,84,80,76,72,68,64,60,56,52,44,40,36,32,28,24,20,16,12,8and4of the outer stacked portion701K11as shown inFIG.3O. The photoresist layer PR12may be removed then. As such, a semiconductor structure as shown inFIG.3Pmay be formed.

Referring toFIG.3Q, a photoresist layer PR13is formed on the stacked structure700. The photoresist layer PR13covers the second stacked portion702, and extends along the first direction D1to cover a portion of the first stacked portion701. That is, the photoresist layer PR13covers a stacked part701P1of the first sub-stacked portion7011and the second sub-stacked portion7012of the first stacked portion701, and exposes a stacked part70101of the first sub-stacked portion7011and the second sub-stacked portion7012. With using the photoresist layer PR13as an etching mask, the stacked part70101is etched downward from the exposed conductive layers through1level so as to form the stacked part70101having the conductive stair layers of an arrangement as shown inFIG.3Q. Then the photoresist layer PR13(previous photoresist layer) may be trimmed by the stair size E in the second direction D2to form a photoresist layer PR14(subsequent photoresist layer) shown inFIG.3R. A size of the photoresist layer PR13in the first direction D1may be not trimmed, and therefore a size of the photoresist layer PR14in the first direction D1may be identical with a size of the photoresist layer PR13in the first direction D1.

Referring toFIG.3R, a photoresist layer PR14is formed on the stacked structure700. The photoresist layer PR14covers the second stacked portion702, and a stacked part701P2of the first sub-stacked portion7011and the second sub-stacked portion7012of the first stacked portion701, and exposes a stacked part70102of the first sub-stacked portion7011and the second sub-stacked portion7012. With using the photoresist layer PR14as an etching mask, the stacked part70102is etched downward from the exposed conductive layers through1level so as to form the stacked part701Q2having the conductive stair layers of an arrangement as shown inFIG.3R. Then the photoresist layer PR14(previous photoresist layer) may be trimmed by the stair size E in the second direction D2to form a photoresist layer PR15(subsequent photoresist layer) shown inFIG.3S. A size of the photoresist layer PR14in the first direction D1may be not trimmed, and therefore a size of the photoresist layer PR15in the first direction D1may be identical with a size of the photoresist layer PR14in the first direction D1.

Referring toFIG.3S, a photoresist layer PR15is formed on the stacked structure700. The photoresist layer PR15covers the second stacked portion702, and a stacked part701P3of the first sub-stacked portion7011and the second sub-stacked portion7012of the first stacked portion701, and exposes a stacked part70103of the first sub-stacked portion7011and the second sub-stacked portion7012. With using the photoresist layer PR15as an etching mask, the stacked part70103is etched downward from the exposed conductive layers through1level so as to form the stacked part70103having the conductive stair layers of an arrangement as shown inFIG.3S. The photoresist layer PR15may be removed then. As such, a semiconductor structure as shown inFIG.3Tmay be formed, which comprises the stacked body structure100and the staircase structure200similar with those described with referring toFIG.1.

According to the manufacturing method described above, the staircase structure200is formed by etching the first stacked portion701through utilizing the photoresist layers of different profiles as etching masks. For example, in the staircase contact region C, sizes of the photoresist layers in the first direction D1and/or the second direction D2are different from each other. The photoresist layer PR1inFIG.3B, the photoresist layer PR13inFIG.3Q, the photoresist layer PR14inFIG.3R, and the photoresist layer PR15inFIG.3Shave photoresist portions having the same size in the first direction D1in the staircase contact region C, and having the different sizes in the second direction D2in the staircase contact region C. The photoresist layer PR2inFIG.3D, the photoresist layer PR3inFIG.3EandFIG.3F, the photoresist layer PR4inFIG.3G, the photoresist layer PR5inFIG.3H, the photoresist layer PR6inFIG.3I, the photoresist layer PR7inFIG.3J, the photoresist layer PR8inFIG.3K, the photoresist layer PR9inFIG.3L, the photoresist layer PR10inFIG.3M, the photoresist layer PR11inFIG.3Nand the photoresist layer PR12inFIG.3Ohave photoresist portions having the same size in the second direction D2in the staircase contact region C, and having the different sizes in the first direction D1in the staircase contact region C. Other possible interpretations for the photoresist layers of the different profiled may be understood with referring to the figures.

The present disclosure is not limited to the manufacturing method described above. For example, other process parameters such as an arrangement for photoresist layer, an etching sequence, and so on may be used according to actual process experiences.