Imaging apparatus

An imaging apparatus includes a solid-state imaging element and a substrate. The solid-state imaging element includes a pixel array having a plurality of pixels in a two-dimensional matrix and pads that correspond to pixel columns of the pixel array and output signals of pixels in the pixel columns. Signal output terminal groups having a plurality of pads arranged in a line in a column direction of the pixel array are arranged in a row direction of the pixel array. A substrate includes a laminated wire being a laminate of a plurality of wiring layers and provided for each of the signal output terminal groups to extend in the column direction of the pixel array. The laminated wire includes a first terminal portion at a position facing each pad in the signal output terminal group. The pad and first terminal portion are connected to each other by a bump.

TECHNICAL FIELD

The present invention relates to an imaging apparatus which captures an image of an object.

Priority is claimed on Japanese Patent Application No. 2010-251980, filed Nov. 10, 2010, the content of which is incorporated herein by reference.

BACKGROUND

In recent years, a large sensor chip which is used in, for example, a so-called digital single-lens reflex camera has been required to operate at a high speed. A/D converters are provided for each column of a pixel array provided on the same chip and perform signal processing in parallel, which makes it possible to reduce the processing speed of the A/D converters to a relatively small value and thus reduce power consumption. However, in order to improve the processing speed, a sensor unit with low noise, a wide dynamic range, and a high power supply voltage, and a digital circuit which includes a micro transistor and operates at a very high speed at a low power supply voltage are configured to be incorporated into one chip. Therefore, the manufacturing process becomes complicated and the yield is reduced. In addition, when a high-speed operation is performed, the amount of heat generated from the chip, particularly, from the A/D converter increases, and an adverse effect, such as a reduction in image quality, due to an increase in temperature is likely to occur in the pixel array.

In some cases, in order to shield the transmission of heat from the A/D converter to the pixel array and improve the yield, a so-called multi-chip mounting structure is used in which the signal processing unit including the AID converter and the pixel array are formed by individual chips and are mounted on one glass chip.

A structure has become known in which a laminated wire obtained by alternately laminating a plurality of leads and insulating layers is connected to the solid-state imaging element which is used in the imaging apparatus, such as a digital still camera (for example, see Patent Document 1). The laminated wire and the solid-state imaging element are connected to each other by wire bonding.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

In the imaging apparatus such as a digital still camera, it is required to increase the number of pixels in the pixel array. In the related art, the signal lines of the solid-state imaging element extending from the pixel array are provided in parallel in the column direction. Therefore, when the width of the solid-state imaging element is constant, a space for arranging pad portions with a width more than that of the signal line is insufficient with an increase in the number of pixels.

In addition, it is necessary to form electrodes for connection to the solid-state imaging element or the signal processing chip on, for example, printed wires on a substrate which connect the solid-state imaging element and the signal processing chip. There is a limitation in increasing the density of the printed wires. In contrast, for example, when the laminated wire is used to connect the solid-state imaging element and the signal processing chip, it is possible to increase the density of the wires. However, when the pad of the solid-state imaging element is connected to the laminated wire by wire bonding, it is necessary to arrange the pad and the laminated wire so as to be separated from each other in the horizontal direction for the wire bonding and a certain space needs to be formed between the laminated wires.

While, when the pad of the solid-state imaging element and the laminated wire are connected to each other by a via connection method using a through hole, the width of, for example, a land or the like, which is a via-connected portion, increases.

Therefore, it is difficult to increase the number of laminated wires, without an increase in the size of the solid-state imaging element or the substrate.

An object of aspects of the present invention is to provide an imaging apparatus capable of ensuring a space for arranging a pad portion of a solid-state imaging element, increasing the density of laminated wires, and increasing the number of pixels in a pixel array, without an increase in the size of the solid-state imaging element or a substrate.

Solution to Problem

According to an aspect of the invention, an imaging apparatus includes: a solid-state imaging element including a pixel array in which a plurality of pixels are arranged in a two-dimensional matrix and signal output terminals which are provided so as to correspond to pixel columns of the pixel array and output signals of pixels in the pixel columns, a plurality of signal output terminal groups, each of which includes a plurality of the signal output terminals arranged in a line in a column direction of the pixel array, being arranged in a row direction of the pixel array; and a substrate including a laminated wire which is a laminate of a plurality of wiring layers and is provided for each of the signal output terminal groups so as to extend in the column direction of the pixel array. The laminated wire includes a first terminal portion which is provided at a position facing each signal output terminal in the signal output terminal group. The signal output terminal and the first terminal portion are connected to each other by a bump.

Advantages

According to the aspect of the invention, since the signal output terminal groups each of which includes a plurality of signal output terminals arranged in the column direction of the pixel array are arranged in the row direction of the pixel array, the signal output terminals can be arranged such that the gap therebetween is more than that between the pixel columns of the pixel array. Therefore, it is possible to increase the number of signal output terminals arranged in the same width range as that in the solid-state imaging element of the imaging apparatus according to the related art.

In addition, the signal output terminal of the solid-state imaging element is arranged so as to face the first terminal portion of the laminated wire, and the signal output terminal and the first terminal portion are connected to each other by the bump. Therefore, it is possible to reduce the size of the connection portion, as compared to wire bonding or via connection using the through hole. As a result, it is possible to increase the number of laminated wires arranged in the same width range and thus increase the density of the laminated wires.

Therefore, it is possible to ensure a space for arranging the signal output terminals of the solid-state imaging element and increase the density of wires, while preventing an increase in the width of the solid-state imaging element or the substrate. Therefore, it is possible to increase the number of pixels in the pixel array.

DESCRIPTION OF EMBODIMENTS

Hereinafter, an imaging apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1shows an imaging apparatus1according to this embodiment. The imaging apparatus1is a so-called digital single-lens reflex camera. In the imaging apparatus1, a lens barrel3is removably attached to a lens mount (not shown) of a camera body2and light which passes through a lens4of the lens barrel3is focused on a sensor chip (solid-state imaging element)5of a multi-chip module7arranged on the rear surface of the camera body2. The sensor chip5is, for example, a bare chip of a so-called CMOS image sensor.

As shown inFIG. 2, the multi-chip module7includes the sensor chip5, an upper signal processing chip50a, and a lower signal processing chip50b.

The sensor chip5includes a pixel array20in which a plurality of pixels which output signals (hereinafter, simply referred to as pixel signals) corresponding to incident light are two-dimensionally arranged in a lattice shape along the column direction and the row direction, a pixel driver21which drives the pixel array20, two column pre-amplifiers22aand22bwhich amplify an output from the pixel array20, and a sensor bias circuit23which mainly supplies bias reference voltage and current to the column pre-amplifiers22aand22bof the sensor chip5on the basis of a control signal (Vref-pix) from the outside. The sensor chip5further includes a driving control bus24for the pixel driver21. The driving control bus24is connected to the upper signal processing chip50aand the lower signal processing chip50b.

Of the column pre-amplifiers22aand22b, the column pre-amplifier22aamplifies pixel signals of each of the odd-numbered columns of the pixel array20in parallel and outputs the amplified pixel signals to the upper signal processing chip50a. The column pre-amplifier22bamplifies pixel signals of each of the even-numbered columns of the pixel array20in parallel and outputs the amplified pixel signals to the lower signal processing chip50b.

The upper signal processing chip50ais a signal processing circuit which processes an input signal and includes a plurality of analog digital converters (hereinafter, simply referred to as column ADCs)25awhich convert analog electric signals for each column output from the column pre-amplifier22aof the sensor chip5into digital signals in parallel, a digital output bus26afor the digital signal output from the column ADCs25a, a digital small-amplitude differential output circuit27awhich reduces the amplitude of the signal from the digital output bus26aand differentially transmits (data-out-A) the signal to the outside of the chip, a bias circuit28afor the column ADCs25a, and a control circuit (CONT.-N)29awhich controls the column ADCs25a, the digital output bus26a, the digital small-amplitude differential output circuit27a, and the bias circuit28a.

Similarly, the lower signal processing chip50bis a signal processing circuit which processes an input signal and includes a plurality of column ADCs25bwhich convert analog electric signals for each column output from the column pre-amplifier22bof the sensor chip5into digital signals in parallel, a digital output bus26bfor the digital signal output from the column ADCs25b, a digital small-amplitude differential output circuit27bwhich reduces the amplitude of the signal from the digital output bus26band differentially transmits (data-out-B) the signal to the outside of the chip, a bias circuit28bfor the column ADCs25b, and a control circuit (CONT.-S)29bwhich controls the column ADCs25b, the digital output bus26b, the digital small-amplitude differential output circuit27b, and the bias circuit28b.

A control signal (Pix-test i/o) for testing the operation of the multi-chip module7can be input to the control circuits29aand29b, the pixel driver21, and the column pre-amplifiers22aand22bfrom the outside.

Next, the operation of the multi-chip module7having the above-mentioned chip structure will be described. The description of an operation in the operation test will be omitted.

First, control signals are input to the multi-clip module7from the outside through two control lines (which are represented by ‘cont.-A-i/o’ and ‘cont.-B-i/o’ inFIG. 2). Then, the control signals are input to the pixel driver21through the driving control bus24by at least one of the control circuit29aof the upper signal processing chip50aand the control circuit29bof the lower signal processing chip50b. Then, the pixel driver21drives the pixel array20and the pixel signals for each selected row are input to the column pre-amplifiers22aand22bfor each column in parallel. The pixel signals input to the column pre-amplifiers22aand22bare amplified at a necessary gain and are then output from the sensor chip5. The pixel signals output from the sensor chip5are input to each of the upper signal processing chip50aand the lower signal processing chip50bthrough laminated wires32(wires indicated inFIG. 2by surrounding with a one-dot chain line) (which will be described below) which are formed in the column direction.

The upper signal processing chip50aand the lower signal processing chip50bhave the same structure and the same operation except that one of them receives the output signals from the even-numbered columns of the pixel array20while the other receives the output signals from the odd-numbered columns of the pixel array20. Therefore, hereinafter, only the upper signal processing chip50awill be described and the description of the lower signal processing chip50bwill be omitted.

The pixel signals input to the upper signal processing chip50aare input to the column ADCs25afor each column in parallel and are analog-digital converted into digital pixel signals on the basis of the control signal from the control circuit29a. The analog-digital converted digital pixel signals are input to the digital small-amplitude differential output circuit27athrough the digital output bus26aon the basis of the control signal from the control circuit29a. The amplitude of the digital pixel signals is reduced and the digital pixel signals are differentially output (represented by ‘data-out-A’ inFIG. 2). Here, the digital pixel signals (‘data-out-A’ and ‘data-out-B’) are output from the upper signal processing chip50aand the lower signal processing chip50bin a predetermined order. The digital pixel signals output from the upper signal processing chip50aand the lower signal processing chip50bare transmitted to the outside of the multi-chip module7through a flexible printed circuit board F (seeFIG. 3).

In the above description, the digital small-amplitude differential output circuits27aand27bare provided in the upper signal processing chip50aand the lower signal processing chip50b, respectively. Alternatively, a plurality (a plurality of lanes) of digital small-amplitude differential output circuits27ato27nmay be provided according to a necessary pixel output speed and an output order may be changed by the control circuit29aor the control circuit29bto transmit the digital pixel signals. In the above description, the column ADCs25aand25bperform only analog-digital conversion. Alternatively and/or additionally, the column ADCs25aand25bmay include a signal processing circuit which performs an advanced digital operation, if necessary, and perform a process of adding the offset value of data, a process of reducing and correcting fixed pattern noise (FPN), and a process of correcting a variation in error for each of the column ADCs25aand25b.

The multi-chip module7is a COG-type (Chip On Glass type) module in which the sensor chip5, the upper signal processing chip50a, and the lower signal processing chip50bare directly mounted on a glass substrate6in a bare chip mounting manner. The sensor chip5is, for example, a relatively large sensor chip with a so-called full size of 35 mm or the like and is attached with a light receiving surface8facing the glass substrate6.

The glass substrate6is formed in, for example, a transparent plate with a substantially rectangular shape in which the longitudinal direction is the column direction of the pixel array20(seeFIG. 2). The sensor chip5is mounted substantially at the center of the glass substrate6in the longitudinal direction. In addition, the upper signal processing chip50aand the lower signal processing chip50bare each formed in a substantially rectangular shape along the width direction of the glass substrate6in a top view. The upper signal processing chip50ais mounted on the upper side of the sensor chip5in the longitudinal direction of the glass substrate6and the lower signal processing chip50bis mounted on the lower side of the sensor chip5in the longitudinal direction of the glass substrate6.

FIG. 4shows the connection structure between the sensor chip5and the upper signal processing chip50aof the multi-chip module7. The connection structure between the sensor chip5and the lower signal processing chip50bis the same as that between the sensor chip5and the upper signal processing chip50a, and the description thereof will be omitted.

As shown inFIG. 4, a plurality of signal lines52which are connected to each pixel column of the pixel array20are arranged substantially in parallel in the sensor chip5. A pad51, which is a signal output terminal, is formed at the end of the signal line52. The pad51has a substantially rectangular shape with a width larger than that of the signal line52and is exposed from the lower surface of the sensor chip5.

A plurality of (for example, four) pads51are arranged in the column direction of the pixel array20with a gap d therebetween. A set of the plurality of pads51forms a signal output terminal group51G. A plurality of sets of the signal output terminal groups51G are arranged in the row direction of the pixel array20. The number of sets of the signal output terminal groups51G is a value obtained by dividing the number of signal lines52by the number of pads51provided in each signal output terminal group51G. That is, the signal output terminal groups51G can be arranged in the row direction of the pixel array20at an interval which is a value obtained by multiplying the pitch between the pixels in the pixel column by the number of pads51in each signal output terminal group51G.

Similarly, pads53which are exposed from the lower surface of the upper signal processing chip50aare formed in the upper signal processing chip50aat positions which are symmetrical to the pads51provided at the edge of the sensor chip5. Each pad53is connected to the column ADC25athrough a signal line (not shown). A plurality of (for example, four) pads53are arranged in the column direction of the pixel array20, with the gap d therebetween. A set of the plurality of pads53forms a signal input terminal group53G A plurality of sets of the signal input terminal groups53G are arranged in the row direction of the pixel array20.

Next, the gap between the pixels on the sensor chip5and the gap between the signal lines will be described.

FIGS. 6A and 6Bshow the gap between the pixels on the sensor chip according to the related art and the gap between the signal lines52. InFIGS. 6A and 6B, the pixel provided in the pixel array20is represented by ‘◯’ and the pixel pitch in the row direction of the pixel array20is represented by ‘PP’ (similarly shown inFIG. 7). Each pixel outputs a signal to the signal line52arranged in the column direction.

FIG. 6Ashows a ‘single-column arrangement’ type in which connection terminals151of the sensor chip5are arranged in parallel in the row direction, similarly to the signal lines52, and are arranged at the same position in the column direction. In the case of the ‘single-column arrangement’ type, the direction in which the signal is output from the odd-numbered pixel column is opposite to the direction in which the signal is output from the even-numbered pixel column and the number of signals output in the same direction is half the number of all signals output in only one direction. Therefore, a gap distance CP1 between the connection terminals151can be made to be two times more (2PP) than the pixel pitch. In addition, reference numeral132indicates a wiring pattern on the glass substrate6which is connected to the connection terminal151.

On the other hand,FIG. 6Bshows a ‘zigzag arrangement’ type in which the connection terminals151shown inFIG. 6Aare arranged to be alternately displaced in the column direction. In the case of the ‘zigzag arrangement’ type, a gap distance CP2 between the connection terminals151which are adjacent to each other in the row direction can be made to be four times (4PP) more than the pixel pitch and it is possible to ensure the gap distance that is two times more than that in the ‘single-column arrangement’ type. The lower limit of the gap distance CP1 or the gap distance CP2 between the connection terminals151is restricted depending on the limit of the accuracy of adjusting and arranging the glass substrate6and the sensor chip5provided on the glass substrate6at predetermined positions. In addition, the lower limit of the pitch between the pixels arranged on the pixel array20of the sensor chip5is restricted by the limit of the accuracy of a semiconductor manufacturing process.

In contrast, as shown inFIG. 7, in the imaging apparatus1according to this embodiment, the direction in which the signal is output from the odd-numbered column is opposite to the direction in which the signal is output from the even-numbered column in the pixel array20and four pads51are arranged in the column direction with the gap d therebetween. Therefore, the gap distance CP3 between the pads51in the row direction can be made to be eight times (=2×4) (8PP) more than the pixel pitch.

As shown inFIG. 4, first terminal portions61, which are electrodes, are formed on the upper surface of the glass substrate6at positions facing each pad51of the sensor chip5so as to be exposed from the upper surface of the glass substrate6. In addition, second terminal portions63, which are electrodes, are formed on the upper surface of the glass substrate6at positions facing each pad53of the upper signal processing chip50aso as to be exposed from the upper surface of the glass substrate6. The first terminal portion61and the second terminal portion63form a portion of the laminated wire32. The pad51and the pad53are electrically connected to each other by the laminated wire32. InFIG. 4, for convenience of illustration, bumps9which are interposed between the pad51and the first terminal portion61and between the pad53and the second terminal portion63are not shown. In addition, for convenience of illustration, the gap between the glass substrate6and the upper signal processing chip50aand the gap between the glass substrate6and the sensor chip5are enlarged.

Next, the connection configuration between the sensor chip5and the upper signal processing chip50awill be described with reference toFIGS. 5A and 5B. The connection configuration between the sensor chip5and the upper signal processing chip50ais the same as that between the sensor chip5and the lower signal processing chip50b. Therefore, only the connection configuration between the sensor chip5and the upper signal processing chip50awill be described.

FIG. 5Ashows a connection portion between the pad51and the first terminal portion61. The laminated wire32is formed by alternately laminating a plurality of wiring layers71which are made of a conductor and a plurality of insulating layers72which are made of an insulating material. Specifically, the laminated wire32is formed by alternately laminating four wiring layers71whose number is equal to the number of pads51in one signal input terminal group53G and four insulating layers72which are provided between the wiring layers71. The end of the laminated wire32is formed in a step shape such that the upper surfaces of the ends of each wiring layer71and each insulating layer72are alternately exposed. An exposed portion of the end of the wiring layer71is the first terminal portion61and is formed to have a width that is slightly more than that of a body portion32aof the laminated wire32.

In the case of via connection, the length of one side of the terminal portion is at least about 50 μm. In contrast, the first terminal portion61can be formed such that the length of one side is about 30 μm. In this embodiment, it is possible to effectively use a space, as compared to via connection. For example, it is possible to reduce the gap between the laminated wires32, or it is possible to increase the width of the wire to reduce resistance.

The first terminal portions61and the pads51which are arranged so as to face the first terminal portions61are connected to each other by the bumps9with different heights. The bump9is a so-called micro bump which is made of a metal material, such as Au, and a thermo-compression process using, for example, a flip chip bonder (not shown) is performed for the bump9to electrically connect the pad51and the first terminal portion61which face each other. The material forming the bump9is not limited to the metal material, but, for example, a resin bump may be used. In addition, for example, a plated bump or a stud bump may be used as the bump9.

The first terminal portion61which is provided in the lowermost layer of the laminated wire32is bonded by the bump to the innermost pad51of the sensor chip5in the column direction. Since the gap between the first terminal portion61provided in the lowermost layer and the pad51is the largest, the height of the bump9which connects the first terminal portion61and the pad51is the largest. The first terminal portion61provided in the second lowermost layer of the laminated wire32is bonded by the bump to the second innermost pad51of the sensor chip5in the column direction. Similarly, the first terminal portion61provided in the higher layer of the laminated wire32is bonded by the bump to the more outer pad51of the sensor chip5in the column direction. At that time, as the layer in which the first terminal portion61is provided becomes higher, the gap between the first terminal portion61and the pad51is reduced. Therefore, in accordance with the increase in the thickness of the layer, the height of the bump9is sequentially reduced.

As shown inFIG. 5B, in an embodiment, the uppermost wiring layer71connects the pad51of the sensor chip5and the pad53of the upper signal processing chip50awhich are arranged with the closest gap therebetween. The second wiring layer71from the upper side connects the pad51and the pad53which are arranged with the second closest gap therebetween. Similarly, the third wiring layer71from the upper side connects the pad51and the pad53which are arranged with the third closest gap therebetween and the lowermost wiring layer71from the upper side connects the pad51and the pad53which are furthest away from each other. For convenience of illustration, the insulating layer72is not shown inFIG. 5B.

Therefore, according to the imaging apparatus of the above-described embodiment, in the sensor chip5, the signal output terminal groups51G, each having the plurality of pads51arranged in the column direction of the pixel array20, are arranged in the row direction of the pixel array20. Therefore, the pads51can be arranged such that the gap therebetween is more than the gap between the pixel columns of the pixel array20. As a result, it is possible to increase the number of pads51arranged in the same width range as that of the sensor chip of the imaging apparatus according to the related art.

Moreover, in this embodiment, the pads51of the sensor chip5and the first terminal portions61of the laminated wire32are arranged so as to face each other and are bonded to each other by the bumps. Therefore, it is possible to reduce the size of the connection portion, as compared to wire bonding or via connection using a through hole. As a result, it is possible to increase the number of laminated wires32in the same width range as that in the related art and thus increase the density of the laminated wires32.

Therefore, in this embodiment, it is possible to ensure a space for arranging the pads51of the sensor chip5and increase the density of the laminated wires32, while preventing an increase in the width of the sensor chip5or the glass substrate6. Therefore, it is possible to increase the number of pixels in the pixel array20.

In addition, in this embodiment, similarly in the upper signal processing chip50aand the lower signal processing chip50b, the signal input terminal groups53G; each having the plurality of pads53arranged in the column direction, are arranged in the row direction. Therefore, the pads53can be arranged such that the gap distance therebetween is more than the gap distance between the pixel columns. As a result, it is possible to prevent an increase in the size of the upper signal processing chip50aand the lower signal processing chip50b.

Furthermore, in this embodiment, the pads53of the upper signal processing chip50aand the lower signal processing chip50bare arranged so as to face the second terminal portions63of the laminated wires32, and the pads53and the second terminal portions63are bonded to each other by the bumps. Therefore, it is possible to reduce the size of each of the pads51and61, the first connection portion53, and the second terminal portion63, as compared to wire bonding or via connection using a through hole. As a result, it is possible to increase the number of laminated wires32arranged in the same width range as that in the related art and thus increase the density of the laminated wires32.

The invention is not limited to the structure of the above-described embodiment, but the design can be changed without departing from the scope of the invention.

For example, in the above-described embodiment, an example of the multi-chip mounting structure in which the sensor chip5, the upper signal processing chip50a, and the lower signal processing chip50bare individually formed has been described. However, the invention can be applied to a case in which the sensor chip5including the upper signal processing chip50aand the lower signal processing chip50bformed integrally therewith is mounted on the glass substrate6.

Moreover, in the above-described embodiment, a case where the sensor chip5is mounted on the glass substrate6has been described. However, the substrate on which the sensor chip5is mounted is not limited to the glass substrate6, but may be, for example, a silicon substrate or an interposer.

In addition, in the above-described embodiment, a case where the imaging apparatus1is a digital single-lens reflex camera has been described. However, the imaging apparatus is not limited to the digital single-lens reflex camera, but the invention can be applied to, for example, an imaging apparatus, such as a video camera or a digital compact camera.

The substrate is not limited to the glass substrate41, but a transparent substrate other than the glass substrate may be used.

DESCRIPTION OF REFERENCE SYMBOLS

51G: SIGNAL OUTPUT TERMINAL GROUP

61: FIRST TERMINAL PORTION

63: SECOND TERMINAL PORTION