Fan-out package structure and method for forming the same

Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and/or higher degrees of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.

A chip package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein. Packaging technologies can be divided into multiple categories. In one of the categories of packaging, dies are sawed from wafers before they are packaged onto other wafers, and “known-good-dies” are packaged. An advantage of this packaging technology is the possibility of forming fan-out chip packages, which means that I/O pads on a die can be redistributed to a greater area than the die itself. Therefore, the number of I/O pads packed on the surfaces of the dies can be increased.

New packaging technologies have been developed to further improve the density and functions of semiconductor dies. These relatively new types of packaging technologies for semiconductor dies face manufacturing challenges, and they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

FIGS. 1A-1Lare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. The package structure may be applied to wafer level package (WLP).

As shown inFIG. 1A, a semiconductor substrate100is provided, in accordance with some embodiments. The semiconductor substrate100may be a wafer substrate. For a better understanding of the structure, the semiconductor substrate100is partially shown in figures. In some embodiments, the semiconductor substrate100includes silicon or another elementary semiconductor material such as germanium. In some other embodiments, the semiconductor substrate100includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.

In some embodiments, the semiconductor substrate100includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof.

Various active elements (not shown) are formed in and/or over the semiconductor substrate100, in accordance with some embodiments. Examples of the various active elements include transistors, diodes, another suitable element, or a combination thereof. The transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc. Various passive elements (not shown) may also be formed in and/or over the semiconductor substrate100. Examples of the various passive elements include capacitors, inductors, resistors, another suitable passive element, or a combination thereof.

Active and/or passive elements may be formed in and/or over the semiconductor substrate100using front-end semiconductor fabrication processes, which may be referred to as front end of line (FEOL) processes. Subsequently, an interconnection structure may be formed over the semiconductor substrate100using back-end semiconductor fabrication processes, which may be referred to as back end of line (BEOL) processes.

For example, a dielectric layer110is formed over the surface100A of the semiconductor substrate100, as shown inFIG. 1Ain accordance with some embodiments. The dielectric layer110covers active and/or passive elements over the semiconductor substrate100. The dielectric layer110may be a multi-layer structure (not shown), which includes an interlayer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. Multiple conductive features (not shown) are formed in the ILD layer and IMD layers and electrically connected to active or passive elements in and/or over the semiconductor substrate100. Examples of the conductive features include conductive contacts, conductive lines and/or conductive vias.

In some embodiments, the dielectric layer110includes or is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-K material, porous dielectric material, another suitable dielectric material, or a combination thereof. The material of the dielectric layer110is selected to minimize size, propagation delays, and crosstalk between nearby conductive features.

As shown inFIG. 1A, conductive pads120are formed over the dielectric layer110, in accordance with some embodiments. The conductive pads120are electrically connected to active or passive elements in and/or over the semiconductor substrate100through the conductive features in the dielectric layer110. The conductive pads120may be wider portions of some conductive lines formed on the dielectric layer110or embedded in the dielectric layer110. Therefore, the active or passive elements may be electrically connected to other elements through the conductive pads120. In some embodiments, the conductive pads120include aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), another suitable material, or a combination thereof.

As shown inFIG. 1A, a passivation layer130is formed over the dielectric layer110, in accordance with some embodiments. The passivation layer130partially covers the conductive pads120so that the conductive pads120are embedded in the passivation layer130. The conductive pads120have a top surface120A partially exposed through openings of the passivation layer130.

AlthoughFIG. 1Ashows that the passivation layer130is a single layer, embodiments of the disclosure are not limited thereto. In some other embodiments, the passivation layer130is a multi-layer structure including sub-layers (not shown). In some embodiments, the passivation layer130includes or is made of silicon nitride, silicon oxide, silicon oxynitride, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), another suitable dielectric material, or a combination thereof.

As shown inFIG. 1B, a protection layer150is deposited over the passivation layer130, in accordance with some embodiments. The protection layer150fills up the openings of the passivation layer130. As a result, the protection layer150adjoins the passivation layer130and the conductive pads120. In some embodiments, the protection layer150is in direct contact with the top surface120A of the conductive pads120. The protection layer150may be referred to as a sacrificial layer, which will be removed in a subsequent process. The protection layer150can provide the conductive pads120with sufficient protection during subsequent processes.

In some embodiments, the protection layer150includes or is made of PI, PBO, BCB, resin, epoxy, a photoresist material, another suitable organic material, or a combination thereof. In some embodiments, the protection layer150and the passivation layer130include or are made of different materials. For example, the protection layer150is an organic material layer while the passivation layer130is a non-organic material layer (such as a silicon nitride layer). However, embodiments of the disclosure are not limited thereto. The protection layer150and the passivation layer130may include the same material. In some embodiments, the protection layer150is deposited using a spray coating process, a spin-on process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof.

Afterwards, a thinning process is performed over the surface100B of the semiconductor substrate100to thin down the semiconductor substrate100, in accordance with some embodiments. The thinning process may include a grinding process, a chemical mechanical polishing (CMP) process, another applicable process, or a combination thereof.

Subsequently, the thinned semiconductor substrate100is attached or bonded to a substrate200through an adhesive layer190, as shown inFIG. 1Cin accordance with some embodiments. As a result, the surface100B of the semiconductor substrate100faces the adhesive layer190and the substrate200. The adhesive layer190is sandwiched between the surface100B and the substrate200. In some embodiments, the substrate200is a dicing frame or another suitable substrate. In some embodiments, the adhesive layer190includes a die attach film (DAF), another suitable adhesive material, or a combination thereof.

Afterwards, a singulation process is performed over the substrate200to form multiple semiconductor dies300, as shown inFIG. 1Din accordance with some embodiments. In some embodiments, the singulation process includes a dicing process or another applicable process. For example, the protection layer150, the passivation layer130, the dielectric layer110and the semiconductor substrate100are sawed or cut along the scribe lines210using a blade or laser. As a result, separated semiconductor dies300are formed and then picked up from the substrate200.

In some embodiments, the semiconductor dies300are logic dies, central processing unit (CPU) dies, memory dies (e.g., static random access memory dies, SRAM dies), sensor dies, or other suitable dies. Each of the semiconductor dies300includes the semiconductor substrate100, the dielectric layer110, the conductive pads120, the passivation layer130, the protection layer150and the adhesive layer190, in accordance with some embodiments. In some embodiments, each of the semiconductor dies300does not include conductive connectors (e.g., conductive bumps or pillars) covering the conductive pads120.

As shown inFIG. 1E, a carrier substrate310is provided, in accordance with some embodiments. In some embodiments, the carrier substrate310is used as a temporary substrate. The temporary substrate provides mechanical and structural support during subsequent processing steps, such as those described in more detail later. In some embodiments, the carrier substrate310is made of a glass material, semiconductor material, ceramic material, polymer material, metal material, another suitable material, or a combination thereof. In some embodiments, the carrier substrate310is a wafer substrate.

As shown inFIG. 1E, an adhesive layer320is deposited over the carrier substrate310, in accordance with some embodiments. In some embodiments, the adhesive layer320is used as a temporary adhesive layer. The adhesive layer320may be made of glue, or may be a lamination material, such as a foil. In some embodiments, the adhesive layer320is photosensitive and is easily detached from the carrier substrate310by light irradiation. For example, shining ultra-violet (UV) light or laser light on the carrier substrate310is used to detach the adhesive layer320. In some embodiments, the adhesive layer320is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the adhesive layer320is heat-sensitive and is easily detached from the carrier substrate310when it is exposed to heat.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, a base layer (not shown) is deposited or laminated over the adhesive layer320. The base layer may be a polymer layer or a polymer-containing layer. For example, the base layer may be a PBO layer, a PI layer, a solder resist (SR) layer, an Ajinomoto buildup film (ABF), a die attach film (DAF), another suitable layer, or a combination thereof.

As shown inFIG. 1E, multiple conductive features330are formed over the adhesive layer320, in accordance with some embodiments. Alternatively, the conductive features330may be formed over the base layer (not shown) covering the adhesive layer320. In some embodiments, the conductive features330are conductive pillars or other suitable features. The conductive features330may be referred to as through integrated fan-out vias (TIVs) or through package vias (TPVs).

In some embodiments, each of the conductive structures330has a vertical sidewall. In some embodiments, the conductive structures330are substantially as high as each other. However, embodiments of the disclosure are not limited thereto. One or more of these conductive structures330may have a different height than that of other conductive structures330. In some embodiments, each of the conductive structures330is substantially circular from a top view.

In some embodiments, the conductive features330are made of a metal material. The metal material may include Cu, Ti, Au, Co, Al, W, another suitable material, or a combination thereof. In some embodiments, the conductive features330are made of a solder material that includes Sn. In some other embodiments, the conductive features330are made of a metal material that does not include Sn.

In some embodiments, the conductive features330are formed using a plating process. The plating process may include an electroplating process, an electroless plating process, another applicable process, or a combination thereof. However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the conductive features330are formed using a CVD process, a PVD process, a spin-on process, an electrochemical deposition (ECD) process, a molecular beam epitaxy (MBE) process, an ALD process, another applicable process, or a combination thereof.

For example, a mask layer (not shown) is formed over the adhesive layer320. The mask layer has openings that define the positions where the conductive features330will be formed. In some embodiments, the mask layer is made of a photoresist material. The openings of the mask layer may be formed by a photolithography process, which includes exposure and development operations. A conductive material is deposited to completely or partially fill the openings in the mask layer. The conductive material and the mask layer may be planarized and thinned using a grinding process, a CMP process, an etching process, another applicable process, or a combination thereof. Afterwards, the mask layer is removed, and the deposited conductive material forms the conductive features330.

AlthoughFIG. 1Eshows that multiple conductive features330are formed over the adhesive layer320, embodiments of the disclosure are not limited thereto. In some other embodiments, the conductive features330are not formed.

Subsequently, the semiconductor dies300with the protection layer150are mounted to the carrier substrate310, as shown inFIG. 1Ein accordance with some embodiments. The adhesive layer190of the semiconductor dies300is attached to the adhesive layer320so that the surface100B of the semiconductor substrate100faces the adhesive layer320and the carrier substrate310. One of the semiconductor dies300is positioned between two of the conductive features330, as shown inFIG. 1E. The semiconductor dies300may be discontinuously surrounded by multiple conductive features330from a top view.

AlthoughFIG. 1Eshows two semiconductor dies300bonded to the carrier substrate310, embodiments of the disclosure are not limited thereto. In some other embodiments, fewer or more semiconductor dies300are bonded to the carrier substrate310.

As shown inFIG. 1F, an encapsulation layer (or a package layer)340is deposited over the adhesive layer320, in accordance with some embodiments. As a result, the conductive features330and the semiconductor dies300are embedded in the encapsulation layer340. In some embodiments, the encapsulation layer340adjoins the sidewall150C of the protection layer150and the sidewall100C of the semiconductor substrate100.

In some embodiments, the encapsulation layer340exposes (or does not cover) the top surface330A of the conductive features330and the top surface150A of the protection layer150. In some embodiments, the conductive features330penetrate through the encapsulation layer340. In some embodiments, the top surface330A of the conductive features330, the top surface150A of the protection layer150, and the top surface340A of the encapsulation layer340are substantially coplanar with one another. Accordingly, a redistribution structure, which will be described in more detail later, can be formed over a flat and even surface.

In some embodiments, the encapsulation layer340includes a polymer material, such as an organic polymer material. In some embodiments, the encapsulation layer340includes a molding compound material, ABF, or another suitable encapsulating material. The encapsulation layer340may be a molding compound layer, which includes an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the encapsulation layer340and the protection layer150include different materials. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the encapsulation layer340and the protection layer150include substantially the same material. For example, the encapsulation layer340and the protection layer150include an organic material.

In some embodiments, the encapsulation layer340is deposited using a molding process. In some embodiments, a molding compound material is deposited over the adhesive layer320. In some embodiments, a thermal process is then performed to cure and harden the molding compound material and to transform it into the encapsulation layer340. As a result, the conductive features330and the semiconductor dies300are surrounded and encapsulated by the deposited encapsulation layer340.

In some embodiments, during or after the deposition of the encapsulation layer340, the encapsulation layer340does not cover the top surface330A of the conductive features330and/or the top surface150A of the protection layer150. As a result, it is not necessary for the encapsulation layer340to be thinned since the conductive features330have been exposed without being covered by the encapsulation layer340. Accordingly, the fabrication cost and process time are reduced. Damage due to a thinning process may also be prevented.

However, embodiments of the disclosure are not limited thereto. In some other embodiments, the encapsulation layer340covers the top surface330A of the conductive features330and/or the top surface150A of the protection layer150. In these embodiments, the encapsulation layer340will be partially removed in a subsequent process until the conductive features330and/or the conductive pads120are exposed. This subsequent process may or may not be a thinning process, such as a grinding process, a CMP process, another applicable process, or a combination thereof.

As shown inFIG. 1G, the protection layer150is removed, in accordance with some embodiments. As a result, the passivation layer130and the conductive pads120are exposed. For example, the top surface120A of the conductive pads120is partially exposed. After the removal of the protection layer150, the semiconductor dies300become thinner and have a height H1. The height H1may be less than the height H2of the conductive features330, as shown inFIG. 1G.

As mentioned above, the protection layer150is used as a sacrificial layer. The protection layer150prevents the conductive pads120from being covered by the material of the encapsulation layer340during the deposition of the encapsulation layer340. After the deposition of the encapsulation layer340, the protection layer150is removed. More specifically, if the protection layer150is not formed, the encapsulation layer340covers the conductive pads120. As a result, it may be difficult to expose the conductive pads120by partially removing the encapsulation layer340. Alternatively, the conductive pads120may be damaged when the encapsulation layer340is partially removed to expose the conductive pads120.

In some embodiments, the encapsulation layer340is partially removed during the removal of the protection layer150. As a result, the encapsulation layer340becomes thinner. In some embodiments, an etching process is used to remove the protection layer150. The etching process may be an anisotropic dry etching process, another applicable process, or a combination thereof. In some embodiments, the encapsulation layer340is etched during the etching process for removing the protection layer150.

As mentioned above, in some other embodiments, the encapsulation layer340covers the top surface330A of the conductive features330and/or the top surface150A of the protection layer150. In these embodiments, the encapsulation layer340is partially removed and the protection layer150is completely removed using the same process (such as an etching process) at the same stage until the conductive features330and/or the conductive pads120are exposed. As a result, no thinning process to the encapsulation layer340is required. The fabrication cost and process time are reduced. Damage due to a thinning process may also be prevented.

Many variations and/or modifications can be made to embodiments of the disclosure. For example, the protection layer150may not be a sacrificial layer. In some other embodiments, the protection layer150is not removed and remains in the package structure. Afterwards, openings (not shown) may be formed in the protection layer150to provide the conductive pads120with electrical connection paths to a redistribution structure, which will be described in more detail later. For example, a redistribution layer may be formed over the protection layer150and fill the openings of the protection layer150to be electrically connected to the conductive pads120.

As shown inFIG. 1H, the conductive features330are partially removed and become shorter after the removal of the protection layer150, in accordance with some embodiments. As a result, the conductive features330have a reduced height H2′ that is substantially equal to the height H1of the semiconductor dies300. In some embodiments, the top surface330A of the conductive features330becomes substantially coplanar with the top surface340A of the encapsulation layer340and the top surface120A of the conductive pads120. The encapsulation layer340covers (or does not expose) the sidewall300C of the conductive features330.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the conductive features330become shorter but remain higher than the semiconductor dies300. In some other embodiments, the conductive features330are recessed in the encapsulation layer340. As a result, the conductive features330may have a reduced height that is less than the height H1of the semiconductor dies300.

In some embodiments, an etching process is used to shorten the conductive features330. The etching process may be a wet etching process, another applicable process, or a combination thereof.

Subsequently, a redistribution structure is formed over the encapsulation layer340, the conductive features330and the semiconductor dies300, in accordance with some embodiments. The redistribution structure includes one or more dielectric layers and one or more conductive layers. For example, the redistribution structure includes dielectric layers350,380,400and420and conductive layers370,390and410, as shown inFIGS. 1I-1Kin accordance with some embodiments. The conductive layers370,390and410may be referred to as redistribution layers (RDLs).

As shown inFIG. 1I, a dielectric layer350is deposited over the encapsulation layer340and the semiconductor dies300, in accordance with some embodiments. The dielectric layer350covers the conductive features330in the encapsulation layer340. The dielectric layer350also covers the passivation layer130and the conductive pads120of the semiconductor dies300. In some embodiments, the dielectric layer350extends in the passivation layer130to adjoin the top surface120A of the conductive pads120. In some embodiments, the dielectric layer350is in direct contact with the encapsulation layer340, the conductive features330, the passivation layer130and the conductive pads120. In some embodiments, a part of the passivation layer130is longitudinally sandwiched between the dielectric layer350and the dielectric layer110. In some embodiments, another part of the passivation layer130is longitudinally sandwiched between the dielectric layer350and the conductive pads120.

In some embodiments, the dielectric layer350is made of a polymer material. The dielectric layer350may be made of PBO, PI, BCB, silicone, acrylates, siloxane, another suitable material, or a combination thereof. In some other embodiments, the dielectric layer350is made of non-organic materials. The non-organic materials include silicon oxide, un-doped silicate glass, silicon oxynitride, SR, silicon nitride, silicon carbide, hexamethyldisilazane (HMDS), another suitable material, or a combination thereof. In some embodiments, the dielectric layer350is deposited using a spin-on process, a spray coating process, a CVD process, an ALD process, a PVD process, another applicable process, or a combination thereof.

As shown inFIG. 1I, multiple openings360are formed in the dielectric layer350, in accordance with some embodiments. Some of the openings360partially expose the conductive pads120and other openings360partially expose the conductive features330. The openings360provide further electrical connection paths, which will be described in more detail later.

In some embodiments, the dielectric layer350is patterned to form the openings360. In some embodiments, the openings360are formed using photolithography and etching processes, a laser drilling process, another applicable process, or a combination thereof. However, embodiments of the disclosure are not limited thereto. In some other embodiments, the dielectric layer350is photopatternable, and the openings360are formed in the dielectric layer350using a photolithography process including exposure and developing stages.

As shown inFIG. 1J, a patterned conductive layer370is formed over the dielectric layer350, in accordance with some embodiments. The conductive layer370fills the openings360of the dielectric layer350to be electrically connected to the conductive pads120and the conductive features330. In some embodiments, the conductive layer370is in direct contact with (or is physically connected to) the top surface120A of the conductive pads120and the top surface330A of the conductive features330. In some embodiments, a part of the dielectric layer350is longitudinally sandwiched between the conductive layer370and the passivation layer130. In some embodiments, another part of the dielectric layer350is longitudinally sandwiched between the conductive layer370and the conductive pads120.

In some embodiments, the passivation layer350has a portion355laterally sandwiched between the conductive layer370and the passivation layer130. As shown inFIG. 1J, in some embodiments, the distance between the conductive layer370and the passivation layer130is substantially equal to the thickness T of the dielectric layer350.

In some embodiments, the conductive layer370is made of a metal material. Examples of the metal material include Cu, Al, W, Ti, Ta, another suitable material, or a combination thereof. In some embodiments, the conductive layer370is formed by an electroplating process, an electroless plating process, a sputtering process, a CVD process, or another applicable process.

Afterwards, multiple dielectric layers380,400and420and multiple conductive layers390and410are alternately stacked over the dielectric layer350and the conductive layer370, as shown inFIG. 1Kin accordance with some embodiments. In some embodiments, a part of the conductive layer370is longitudinally sandwiched between the dielectric layer380and the conductive pads120. The materials and/or formation methods of the dielectric layers380,400and420are the same as or similar to those of the dielectric layer350, and therefore are not repeated. The materials and/or formation methods of the conductive layers390and410are the same as or similar to those of the conductive layer370, and therefore are not repeated.

As shown inFIG. 1K, under bump metallization (UBM) layer440is formed over the dielectric layer420, in accordance with some embodiments. The UBM layer440fills openings430of the dielectric layer420to be electrically connected to the conductive layer410. The UBM layer440may have a multi-layer structure including an adhesion layer, a diffusion barrier layer, and/or a wetting layer. In some embodiments, the adhesion layer includes or is made of Cr, TiW, Ti, Al, or a combination thereof. In some embodiments, the diffusion barrier layer includes or is made of Ni, CrCu, TiN, or TiW, or a combination thereof. In some embodiments, the wetting layer includes or is made of Cu, Au, Ag, or a combination thereof.

As shown inFIG. 1K, multiple connectors450are formed over the UBM layer440, in accordance with some embodiments. In some embodiments, the connectors450are electrically connected to the conductive layer410through the UBM layer440. The connectors450include solder bumps (or solder balls), metal pillars, other suitable connectors, or a combination thereof. In some embodiments, the connectors450include Sn, Pb, Ni, Au, Ag, Cu, another suitable conductive material, an alloy thereof, or a combination thereof. In some embodiments, the connectors450are formed by evaporation, electrolytic plating, electroless plating, and/or screen printing one or more conductive materials over the UBM layer440.

Afterwards, the structure shown inFIG. 1Kis placed upside down on a support substrate (not shown), in accordance with some embodiments. Then, the carrier substrate310and the adhesive layer320are removed. Suitable light may be provided to remove the adhesive layer320so as to lift off the carrier substrate310as well. Subsequently, a singulation process (or a dicing process) is performed to form multiple package structures including a package structure500A, as shown inFIG. 1L. Each of the package structures includes one semiconductor die300or multiple semiconductor dies300.FIG. 1Lshows that the package structure500A includes one semiconductor die300as an example.

In some embodiments, one or more elements (not shown) are stacked on or bonded to the structure as shown inFIG. 1L. A reflow process may be performed to bond the elements to the structure as shown inFIG. 1L. As a result, multiple package on package (PoP) structures are formed. Each of the PoP structures includes one semiconductor die300or multiple semiconductor dies300. Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the elements are bonded before the singulation process. In some other embodiments, the elements are bonded after the singulation process.

The elements are electrically connected to the conductive features330. Electrical connections between the elements and the semiconductor dies300may therefore be established. In some embodiments, the elements include a chip package, a semiconductor die, one or more passive devices, another suitable structure, or a combination thereof. For example, the elements may include a dynamic random access memory (DRAM) die or other suitable dies.

Many variations and/or modifications can be made to embodiments of the disclosure. Although the embodiments described inFIGS. 1A-1Lrelate to a fan-out PoP structure, embodiments of the disclosure are not limited thereto. In some other embodiments, no element is bonded to the structure as shown inFIG. 1Land the conductive features330are not formed. A singulation process is performed to separate this structure into multiple package structures including one semiconductor die300or multiple semiconductor dies300.

In accordance with some embodiments, no connector is formed over the conductive pads120of the semiconductor dies300, as shown inFIG. 1D. No connector is formed between the conductive pads120and the conductive layer370of the package structure500A, as shown inFIG. 1L. The connector may be a conductive bump, a conductive via, a conductive pillar or another suitable connector. The fabrication of the package structure500A becomes simpler. Therefore, the fabrication cost and process time are reduced. Also, more package structures of good quality and high performance can be fabricated.

More specifically, in some cases, a mask layer (such as a photoresist layer) having multiple openings is used to form connectors, which are physically and electrically coupled to conductive pads. The openings of the mask layer expose conductive pads and define the positions where connectors will be formed. The openings of the mask layer may be formed by a photolithography process including exposure and development operations. However, as the size of a package structure continues to reduce, the openings of the mask layer for forming connectors face manufacturing challenges. There are limitations for a photolithography process to pattern a mask layer and form openings of a small size (width) and a small pitch. Therefore, it may be difficult to further shrink a package structure and electronic products made therefrom.

According to some embodiments of the disclosure, the package structure500A does not include connectors that are physically and electrically coupled to the conductive pads120. The package structure500A becomes thinner. Also, no mask layer for forming connectors and no photolithography process to form openings in a mask layer are required. The pitch between the conductive pads120can be reduced according to requirements without being limited by manufacturing challenges of the photolithography process. As a result, the area of the package structure500A is reduced. The package structure500A is allowed to shrink even further.

Since the fabrication processes of the package structure500A have become simpler, the fabrication cost and process time are greatly reduced. Damage to a package structure during the fabrication processes of connectors may also be prevented. Furthermore, there is no need to control the height of connectors and the co-planarity or uniformity of connectors (such as the height difference between connectors). Therefore, the fabrication processes of the package structure500A can have better control. It becomes easier to form more package structures with enhanced reliability.

Many variations and/or modifications can be made to embodiments of the disclosure. For example,FIGS. 1G and 1Hshow that the top surface340A of the encapsulation layer340is substantially coplanar with the top surface120A of the conductive pads120and the top surface130A of the passivation layer130. However, embodiments of the disclosure are not limited thereto.FIGS. 2A-2Care cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. The materials and/or formation methods of the structure shown inFIGS. 2A-2Care the same as or similar to those of the structure shown inFIGS. 1A-1L, as illustrated in the aforementioned embodiments, and therefore are not repeated.

As shown inFIG. 2A, the protection layer150is removed after the deposition of the encapsulation layer340. In some embodiments, the top surface340A of the encapsulation layer340becomes lower during and after the removal of the protection layer150. In some embodiments, the top surface340A of the encapsulation layer340is lower than the top surface120A of the conductive pads120, the top surface130A of the passivation layer130, and/or the top surface330A of the conductive features330.

In some embodiments, the top surface340A of the encapsulation layer340is non-coplanar with the top surface120A of the conductive pads120and the top surface130A of the passivation layer130. The top surface330A of the conductive features330may be substantially coplanar with the top surface120A of the conductive pads120and the top surface130A of the passivation layer130. As a result, the top surface340A of the encapsulation layer340may be non-coplanar with the top surface330A of the conductive features330. For example, the conductive features330protrude from the top surface340A of the encapsulation layer340. The conductive features330may be higher than the semiconductor dies300.

Afterwards, the steps described inFIG. 1Iare performed over the structure shown inFIG. 2A. As a result, the dielectric layer350including the openings360is formed over the encapsulation layer340and the semiconductor dies300, as shown inFIG. 2Bin accordance with some embodiments. Since the top surface340A of the encapsulation layer340is lower than the top surface130A of the passivation layer130, the passivation layer130is surrounded by the dielectric layer350covering the encapsulation layer340. Since the top surface340A of the encapsulation layer340is lower than the top surface330A of the conductive features330, an upper part of the conductive features330is surrounded by the dielectric layer350covering the encapsulation layer340. In some embodiments, the dielectric layer350is in direct contact with the sidewall330C of the conductive features330. In some embodiments, a part of the dielectric layer350is laterally sandwiched between the passivation layer130and the conductive features330.

The steps described inFIGS. 1J-1Lare performed sequentially over the structure shown inFIG. 2Bto continue the fabrication of a package structure500B, as shown inFIG. 2C.

Many variations and/or modifications can be made to embodiments of the disclosure. For example,FIG. 1Hshows that the encapsulation layer340exposes the top surface330A of the conductive features330after the removal of the protection layer150. However, embodiments of the disclosure are not limited thereto.FIGS. 3A-3Dare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. The materials and/or formation methods of the structure shown inFIGS. 3A-3Dare the same as or similar to those of the structure shown inFIGS. 1A-1L, as illustrated in the aforementioned embodiments, and therefore are not repeated.

In accordance with some embodiments, the top surface330A of the conductive features330is covered by the encapsulation layer340. As shown inFIG. 3A, in some embodiments, the top surface330A of the conductive features330remain covered by the encapsulation layer340after the removal of the protection layer150. In these embodiments, the top surface340A of the encapsulation layer340is non-coplanar with the top surface130A of the passivation layer130.

As shown inFIG. 3B, multiple openings335are formed in the encapsulation layer340to partially expose the top surface330A of the conductive features330, in accordance with some embodiments. In some embodiments, the encapsulation layer340is partially removed to form the openings335using a laser drilling process, another applicable process, or a combination thereof.

Afterwards, the steps described inFIG. 1Iare performed over the structure shown inFIG. 3B. As a result, the dielectric layer350including the openings360is formed over the encapsulation layer340and the semiconductor dies300, as shown inFIG. 3Cin accordance with some embodiments. In some embodiments, the dielectric layer350extends in the encapsulation layer340to fill up the openings335of the encapsulation layer340. Subsequently, the dielectric layer350in the openings335is partially removed to form some of the openings360exposing the top surface330A of the conductive features330. In some embodiments, a part of the encapsulation layer340is laterally sandwiched between the dielectric layer350in the openings335and the passivation layer130.

The steps described inFIGS. 1J-1Lare performed sequentially over the structure shown inFIG. 3Cto continue the fabrication of a package structure500C, as shown inFIG. 3D.

Embodiments of the disclosure provide package structures and methods for forming the same. A package structure includes a semiconductor die surrounded by an encapsulation layer, and a redistribution structure over the semiconductor die and the encapsulation layer. The semiconductor die include conductive pads but does not include connectors (such as bumps, vias, or pillars) that are physically coupled to the conductive pads. No connector is formed between the conductive pads and the redistribution structure. As a result, the package structure becomes thinner. Also, the pitch between the conductive pads is allowed to be reduced without being limited by manufacturing challenges of connectors. The size of the package structure is reduced even further. Furthermore, since the fabrication processes of the package structure have become simpler, the fabrication cost and process time are greatly reduced. More package structures of improved reliability can be fabricated.

In accordance with some embodiments, a package structure is provided. The package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.

In accordance with some embodiments, a package structure is provided. The package structure includes a semiconductor substrate in an encapsulation layer. The package structure also includes a passivation layer over the semiconductor substrate. The package structure further includes a conductive pad in the passivation layer. In addition, the package structure includes a conductive pillar in the encapsulation layer. The package structure also includes a first dielectric layer covering the passivation layer and the encapsulation layer. The first dielectric layer adjoins the conductive pad and the conductive pillar. The package structure further includes a redistribution layer covering the first dielectric layer. The redistribution layer extends in the first dielectric layer to be physically connected to the conductive pad and the conductive pillar.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes forming a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The semiconductor die further includes a protection layer covering the conductive pad. The method also includes forming an encapsulation layer surrounding the semiconductor die. The method further includes removing the protection layer to expose the conductive pad after the formation of the encapsulation layer. In addition, the method includes forming a dielectric layer covering the conductive pad, the passivation layer and the encapsulation layer. The method also includes partially removing the dielectric layer to form a first opening exposing the conductive pad. The method further includes forming a redistribution layer over the dielectric layer. The redistribution layer fills the first opening to be electrically connected to the conductive pad.