Self-tuning of signal path delay in circuit employing multiple voltage domains

Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to timing of one or more signal paths in a multiple voltage domain circuit. The technology of the disclosure also relates to timing of one or more signal paths in memory circuits.

Circuits are increasingly being designed with conservation of power in mind. This is particularly the case for portable electronic devices that are battery-powered. Common examples include mobile phones and laptop computers among others. Increased power consumption undesirably results in faster battery drain and shorter battery life. One method of conserving power is to lower the operating frequency of the circuit according to the active power equation P=CV2f. However, reducing operating frequency results in lower circuit performance (i.e., speed). Another method of conserving power is to lower the operating voltage level since generally, active power reduces quadratically for a given reduction in operating voltage level. However, lowering the operating voltage level in a circuit lowers speed performance, which may also be undesirable. Further, certain cells or components of a circuit may have a minimum operating voltage below which they will not operate properly.

To address the tradeoff between performance and power consumption, multiple operating voltage domains (“voltage domains”) are increasingly being provided in circuits. Circuit paths are provided which pass through the multiple voltage domains to provide different operating voltages to different components of a circuit. Providing multiple voltage domains allows a lower voltage domain to provide power to components that do not require minimum voltage levels to conserve power. Components that either have a minimum operating voltage level for proper operation or provide critical paths where performance cannot be sacrificed may be powered by the higher voltage domain. Providing multiple voltage domains also allows the lower voltage domain to be scaled-down to conserve power during a power conservation mode, or scaled-up to provide for increased performance (i.e., hyper-performance), without affecting the operation of the components in the higher voltage domain.

Examples of circuits where multiple voltage domains are commonly employed are memory circuits and memory systems. One example is static random access memory (SRAM). SRAM may be used on cache memory. SRAM cells have a minimum operating voltage level to retain stability and properly retain data. Further, the minimum operating voltage is higher to address minimum operating voltage level issues for SRAM cells provided in deep sub-micron geometries less than one-hundred (100) nanometers (nm), such as sixty-five (65) nm and forty-five (45) nm geometries as examples. One example of an SRAM system employing multiple voltage domains is illustrated inFIG. 1. Therein, an exemplary SRAM memory system10(referred to as “memory system10”) is provided. Input lines12and output lines14are coupled to the memory system10. The input lines12and output lines14carry signals to allow command and data communication between the memory system10and other system components that write or read data to and from an SRAM cell array16, which operates as a mass memory device. A control system18controls the operation of the SRAM cell array16.

The memory system10contains two signal paths, labeled “access path”20and “sense path”22. The access path20transfers access signals from the control system18to word line drivers26(i.e., row selector), possibly through intermediary logic24. In response, the word line drivers26activate a specific row of memory cells within the SRAM cell array16in response to address information from the control system18. The address information identifies a specific row in the SRAM cell array16to be selected. The row may be selected for either a read or write operation. In response, data from the selected row in the SRAM cell array16is placed on bit lines28. In order to read the data placed on the bit lines28, the control system18, and possibly intermediary logic30, communicates a sense signal to sense amplifiers32to perform a read on the bit lines28. The sense amplifiers32sense the data from the bit lines28and place the data on output lines14.

In the memory system10, the timing for signals to traverse the access path20and the sense path22are compatible. Specifically, the memory system10is designed so that a sense pulse signal communicated by the control system18over the sense path22does not cause the sense amplifiers32to sense data on the bit lines28before access signals are communicated by the control system18over the access path20to cause the SRAM cell array16to assert data on the bit lines28. Otherwise, the sense amplifiers32will sense data on the bit lines28before the SRAM cell array16has asserted valid data on the bit lines28. It is acceptable for access signals communicated over the access path20to reach the SRAM cell array16before sense signals reach the sense amplifiers32over the sense path22. In this scenario, data on the bit lines28will be present before the sense amplifiers32are activated to sense data on the bit lines28. The delay of the access path20in the memory system10provides the minimum delay for which sense signals should traverse the sense path22to the sense amplifiers32.

The memory system10ofFIG. 1operates in a higher voltage domain VHprovided at the minimum voltage level VMINsufficient to provide stable operation and data storage in the SRAM cell array16. The input lines12and output lines14come from components that are provided in a lower voltage domain VL. In this regard, one or more level shifters34are provided to convert the signals on the input lines12from the lower voltage domain VLto the higher voltage domain VH. Signals communicated from the sense amplifiers32to the output lines14may be converted from the higher voltage domain VHto the lower voltage domain VLwith or without one or more level shifters36.

It may be desirable to power certain components or portions of the memory system10in a lower voltage domain VL. Providing multiple voltage domains in a circuit allows scaling of a voltage domain to conserve power without affecting the operation of the components powered by other voltage domain(s). However, because different voltage domains operate independently, the voltage level differential between them can vary. Variations in voltage levels between different voltage domains can cause discrepancies in delays of signal paths in a circuit. Large discrepancies may render the circuit non-functional.

SUMMARY OF THE DISCLOSURE

Embodiments disclosed in the detailed description include circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path. In this regard, a plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be suited for use in circuits and methods where it is desired to control the delay of a first signal path relative to a second signal path, and the timings in the paths can vary with respect to each other due to delay variations caused by voltage level variations among multiple voltage domains.

In certain embodiments disclosed herein, a first path is provided that traverses a first portion of the plurality of voltage domains. The first portion is a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A second path is provided that traverses a second portion of the plurality of voltage domains. The second portion is also a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A delay circuit is coupled to the first path. The delay circuit includes at least one first delay element whose voltage is configured to be supplied by a first voltage supplied by the first portion among the plurality of voltage domains and at least one second delay element whose voltage is configured to be supplied by a second voltage supplied by the second portion among the plurality of voltage domains. In this manner, the delay circuit, by including delay elements being supplied with voltage from both the first and second portions among the plurality of voltage domains, will track delay changes in the second portion caused by variations among the plurality of voltage domains. The delay circuit generates a delay output in response to the greater delay between the first portion and the second portion among the plurality of voltage domains.

The circuits and methods disclosed herein may be employed in memory systems where the timing or delay of an access path and sense path are controlled to access memory. These memory systems include those included in processor-based systems. For example, the circuits and methods disclosed herein may be employed in a memory system employing static random access memory (SRAM). The memory system may be designed such that certain components are included in a lower voltage domain to conserve power, while the SRAM is included in a higher voltage domain to provide a minimum operating voltage level for cell operation. The memory system includes an access path to cause the SRAM to assert data onto bit lines and a sense path to control when sense amplifiers sense the bit lines. Changes in voltage levels between the higher and lower voltage domains can change the delay of the access path and the sense path. In this regard, at least one delay element whose voltage is supplied by both the higher voltage domain and the lower voltage domain is provided in the sense path. In this manner, the at least one delay element adjusts or self-tunes the delay of the sense path according to the path having the greater delay among the lower and higher voltage domains so that the sense amplifiers do not sense the bit lines before the SRAM asserts valid data on the bit lines.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

Embodiments disclosed in the detailed description include circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path. In this regard, a plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be suited for use in circuits and methods where it is desired to control the delay of a first signal path relative to a second signal path, and the timings in the paths can vary with respect to each other due to delay variations caused by voltage level variations among multiple voltage domains.

In certain embodiments disclosed herein, a first path is provided that traverses a first portion of the plurality of voltage domains. The first portion is a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A second path is provided that traverses a second portion of the plurality of voltage domains. The second portion is also a subset of the plurality of voltage domains that may consist of any number or combination of the plurality of voltage domains. A delay circuit is coupled to the first path. The delay circuit includes at least one first delay element whose voltage is configured to be supplied by a first voltage supplied by the first portion among the plurality of voltage domains and at least one second delay element whose voltage is configured to be supplied by a second voltage supplied by the second portion among the plurality of voltage domains. In this manner, the delay circuit, by including delay elements being supplied with voltage from both the first and second portions among the plurality of voltage domains, will track delay changes in the second portion caused by variations among the plurality of voltage domains. The delay circuit generates a delay output in response to the greater delay between the first portion and the second portion among the plurality of voltage domains.

The circuits and methods disclosed herein may be employed in memory systems where the timing or delay of an access path and a sense path are controlled to access memory. Such memory systems may include processor-based systems. In this regard,FIG. 2illustrates an exemplary memory system44that may employ at least one delay element to adjust the delay of a signal path to the path having the greater delay among multiple voltage domains. The memory system44employs static random access memory (SRAM), but any type of memory can be employed. Input lines46and output lines48are coupled to the memory system44. The input lines46and output lines48carry signals to allow command and data communication between the memory system44and other system components that read data from and write data to an SRAM cell array50. The SRAM cell array50operates as a mass memory device in this embodiment.

The memory system44contains two signal paths: an access path54and a sense path56. A control system52is provided to communicate an access signal over the access path54to word line drivers58(i.e., row selectors). The access signals may pass through intermediary logic60in the access path54. In response, the word line drivers58operate to activate a specific row of memory cells within the SRAM cell array50in response. The row in the SRAM cell array50may be selected for either a read or write operation. In response, data from the selected row in the SRAM cell array50is asserted on bit lines62. In order to read data asserted on the bit lines62by the SRAM cell array50, the control system52communicates a sense signal to one or more sense amplifiers66over the sense path56. The sense signal may pass through intermediary logic61,64in the sense path56. In response to receipt of the sense signal, the sense amplifiers66perform a read on the bit lines62to sense the data from the bit lines62. The sense amplifiers66direct the sensed data to the output lines48to be passed to other components or systems outside of the memory system44.

In the memory system44, the delay for signals to traverse the access path54and the sense path56are compatible. Specifically, the components of the memory system44are tuned such that a sense signal communicated over the sense path56does not cause the sense amplifiers66to sense data on the bit lines62before the SRAM cell array50asserts data on the bit lines62. Otherwise, the sense amplifiers66will sense data on the bit lines62before the SRAM cell array50has asserted valid data on the bit lines62. It is acceptable for access signals communicated over the access path54to reach the SRAM cell array50before sense signals reach the sense amplifiers66within a certain margin of delay. In this scenario, the data on the bit lines62will be present when the sense amplifiers66are activated. The delay of the access path54in the memory system44provides the minimum delay for which a sense signal can traverse the sense path56to the sense amplifiers66.

In order to conserve power and/or to improve voltage scaling for memory system44, two voltage domains are provided in the memory system44. A lower voltage domain VLin a first portion45of the memory system44and a higher voltage domain VHin a second portion47of the memory system44are provided. Both the lower voltage domain VLand higher voltage domain VHare supplied with voltages from first and second voltage supplies, respectively. A lower voltage domain VLis a voltage domain that generally provides a lower voltage level than a higher voltage domain VH. As an example, a standard voltage level provided by the lower voltage domain VLmay be 0.75 Volts, and the standard voltage level provided by the higher voltage domain VHmay be 1.1 Volts. In this example, the first portion45traverses in the lower voltage domain VLexclusively, and the second portion47traverses the higher voltage domain VHexclusively. However, a first portion and/or a second portion of the memory system44could be provided that traverse both the lower voltage domain VLand the higher voltage domain VH. Alternatively, the first portion45may traverse both the lower voltage domain VLand the higher voltage domain VHand the second portion47may only traverse the higher voltage domain VH, or vice versa. The first and second portions45,47can be provided to traverse any combination of multiple voltage domains.

The voltage domains can be adjusted during operation, such as to provide voltage scaling for either hyper-performance or reduced power consumption, as examples. In this example, the input lines46and output lines48come from components provided in a lower voltage domain VL. The control system52and intermediary logic60,61are powered by the lower voltage domain VLto conserve power. Thus, components in both the access path54and the sense path56are powered by the lower voltage domain VL. Thus, the delay in the access path54and the sense path56are affected by the voltage level of the lower voltage domain VL. In this example, components in the access path54and the sense path56are also powered by the higher voltage domain VHin the memory system44ofFIG. 2. The higher voltage domain VHis provided to operate the SRAM cell array50. The SRAM cell array50is provided in the higher voltage domain VHto provide a minimum operating voltage level, VMIN, independent of the lower voltage domain VL, for proper SRAM cell operations. For example, VMINmay be 0.95 Volts. The word line drivers58, the intermediary logic64, and the sense amplifiers66are also provided in the higher voltage domain VHto enhance their performance. One or more level shifters68,70,73are provided to convert signals carried from components in the lower voltage domain VLto the higher voltage domain VH. In this regard, signals from the control system52and passing through the intermediary logic60,61in the access path54and the sense path56, respectively, are level shifted from the lower voltage domain VLto the higher voltage domain VHvia the one or more level shifters68,70,73. Intermediary logic64is located in the higher voltage domain VHand thus does not need to be level shifted. Another level shifter72is provided to shift the output lines48from the higher voltage domain VHback to the lower voltage domain VL.

Providing an independent lower voltage domain VLand higher voltage domain VHallows the lower voltage domain VLto be dynamically adjusted, such as via dynamic voltage scaling (DVS) techniques for example, to either conserve power or allow hyper-performance. The lower voltage domain VLmay be scaled down or collapsed during standby modes to conserve standby power. If further performance enhancements are desired, the higher voltage domain VHcan be raised to provide a higher operating voltage level than VMIN.

The performance (i.e., speed) of components are affected by their operating voltage level. Generally, a higher operating voltage level results in less delay and faster performance. Generally, a lower operating voltage level results in more delay and slower performance. Thus, the timing of the access path54and the sense path56is designed with the voltage domains in mind so that the access path54has the same or less delay than the sense path56. Otherwise, the sense amplifiers66will sense data on the bit lines62before valid data is asserted on the bit lines62by the SRAM cell array50. Because the voltage level in a voltage domain can undergo variations due to variations in a power supply, the delay in the access path54and the sense path56can change during operation as a result. When providing multiple voltage domains, voltage level variations in either the lower voltage domain VL, the higher voltage domain VH, or both can contribute to delay variations in the access path54and the sense path56. Natural tolerances between level shifters68,70, and/or73can also cause additional variations in delays that contribute to overall delay variations in the access path54and the sense path56.

If voltage level variations occur in the access path54and/or the sense path56such that the delay of the sense path56increases relative to the delay of the access path54, the memory system44still operates properly. In this case, the SRAM cell array50will still place data on the bit lines62before the sense amplifiers66sense the data on the bit lines62. However, if voltage level variations occur such that the delay of the sense path56decreases relative to the delay of the access path54, the memory system44may be inoperable. In this case, the sense amplifiers66may be activated to sense data on the bit lines62before valid data is placed on the bit lines62by the SRAM cell array50. For this reason, the memory system44is designed to provide a delay margin for the sense path56. A delay margin is an amount of delay by which the delay of the sense path56can decrease relative to the access path54and the memory system44still property function (i.e., valid data is present on bit lines62when the sense amplifiers66sense data on the bit lines62). Delay margin comes with a trade off. Delay margin decreases performance of the memory system44by increasing the delay of the sense path56. Performance is decreased for all operating conditions even though voltage level variations may cause decrease in the delay of the sense path56at certain limited times or conditions. Thus, it is desirable to limit the delay margin for the sense path56as much as possible to maximize performance of the memory system44without rendering the memory system10inoperable.

Even with delay margin provided for the sense path56, the voltage levels in the lower voltage domain VLor the higher voltage domain VHmay still vary such that the delay of the sense path56relative to the access path54decreases greater than the delay margin. In these cases, the memory system44will be inoperable. The decreased delay of the sense path54will cause the sense amplifiers66to sense data on the bit lines62before valid data is asserted on the bit lines62by the SRAM cell array50. Delay margin of the sense path56can be increased, but performance is sacrificed as a result. It may not be possible to provide enough delay margin to allow for proper operation of the memory system44in all operating conditions while achieving acceptable performance.

To address this issue, one or more delay circuits74are provided in the sense path56, as illustrated inFIG. 2. One or more delay circuits74are configured to self-tune the delay in the sense path56. By self-tune, it is meant that the delay in the sense path56is self-adjusting. The delay in the sense path56is prevented from being less than the delay in the access path54. Otherwise, the sense amplifiers66may sense data from the bit lines62before the SRAM cell array50asserts valid data on the bit lines62in certain operating circumstances. One or more delay circuits74are configured to adjust delay dynamically during operation of the memory system44.

FIG. 3illustrates one example of a delay circuit74A that may be coupled inline in the sense path56of the memory system44ofFIG. 2. The memory system44ofFIG. 2shows two possible locations for delay circuits74in the sense path56. The delay circuits74can be provided in the sense path56before intermediary logic64, after intermediary logic64, or before and after intermediary logic64. However, the delay circuits74may be provided anywhere in the sense path56. As illustrated inFIG. 3, the delay circuit74A includes a delay element which is exemplified by buffer76. An input signal78configured to carry a sense signal in the higher voltage domain VHin the sense path56is coupled to the input of the buffer76. The buffer76adds delay to the sense signal passing through the sense path56. The operating voltage powering the buffer76is provided by a voltage supply powering the lower voltage domain VL. In this manner, the delay circuit74A is configured to generate a delay output80from the buffer76, and thus the delay of the sense path56, that is only gated by the path having the greater delay in the lower voltage domain VL. One or more level shifters79may be provided to shift the voltage level of the output of the buffer76to the higher voltage domain VH. The path of greater delay is often in the lower voltage domain VL. Thus, if a delay or slow down occurs due to variances in the lower voltage domain VLduring operation of the memory system44, the delay output80of the buffer76will be dynamically gated to the path of greater delay in the lower voltage domain VL. Thus, the delay of the sense path56will be increased according to the delay or slow down caused by the lower voltage domain VL. This prevents exhaustion of the delay margin in the sense path56, wherein the delay in the sense path56is lower than the delay in the access path54.

The delay circuit74A illustrated inFIG. 3can adjust the delay of the sense path56in response to a delay or slow down caused by the lower voltage domain VL. However, the delay circuit74A cannot increase the delay of the sense path56in response to a delay or slow down caused by the higher voltage domain VH. An effective slow down can occur in the higher voltage domain VHeven if the voltage level of the higher voltage domain VHdoes not decrease. In some situations, the lower voltage domain VLmay provide a higher voltage level than the higher voltage domain VH. Thus, the higher voltage domain VHmay be slower than the lower voltage domain VLin this instance depending on the design of a given circuit.

The delay circuit74B inFIG. 4adjusts for situations where either the path of greater delay is caused by either the lower voltage domain VLor the higher voltage domain VH. As illustrated inFIG. 4, a delay circuit74B is coupled inline in the sense path56and configured to dynamically adjust or self-tune delay in the sense path56. The delay circuit74B is configured to generate a delay output87to dynamically adjust or self-tune delay in the sense path56due to a delay or slow down caused by either the lower voltage domain VLor the higher voltage domain VH. In the delay circuit74B ofFIG. 4, first and second delay elements exemplified as first buffer82and second buffer84, respectively, are coupled in parallel. The input signal78configured to carry a sense signal is coupled to inputs of the first and second buffers82,84. The first buffer82is powered by a first voltage supply providing power to the lower voltage domain VLjust as provided in the delay circuit74A ofFIG. 3. One or more level shifters83may be provided to shift the voltage level of the output of the first and second buffers82,84to the higher voltage domain VH. However, the second buffer84is powered by a second voltage supply providing power to the higher voltage domain VH. The outputs of the first and second buffers82,84are input into a combining circuit exemplified as combining gate86, which in one embodiment may be an AND gate. The delay output87of the combining gate86carries a sense signal provided on the input signal78to the sense amplifiers66in the sense path56. By providing first and second buffers82,84that are powered by both voltage domains, the delay output87of the first and second buffers82,84, and thus the delay of the sense path56, will be gated by the path of greater delay caused by either the lower voltage domain VLor the higher voltage domain VH. Thus, the delay circuit74B is capable of dynamically adjusting or self-tuning the delay in the sense path56regardless of whether the lower voltage domain VLcaused the path of greater delay relative to the higher voltage domain VH, or the higher voltage domain VHcaused the path of greater delay relative to the lower voltage domain VL.

FIG. 5illustrates another example of a delay circuit74. Therein, a delay circuit74C is provided that is similar to the delay circuit74B illustrated inFIG. 4, except that additional buffers are provided to further increase delay in the sense path56. A first set of delay elements exemplified as buffers88coupled in a series chain is provided and powered by the lower voltage domain VLto provide delay buffers. A second set of delay elements exemplified as buffers90coupled in a series chain and powered by the higher voltage domain VHis coupled in parallel to the first set of buffers88. The input signal78configured to carry a sense signal on the sense path56is coupled to inputs of the first set of buffers88and the second set of buffers90. The outputs of the first and second sets of buffers88,90are coupled to the inputs of a combining circuit exemplified by combining gate92, which in one embodiment may be an AND gate. One or more level shifters89may be provided to shift the voltage level of the output of the first and second sets of buffers88,90to the higher voltage domain VH. A delay output91of the combining gate92carries a sense signal provided on the input signal78to the sense amplifiers66in the sense path56. As provided in the delay circuit74B ofFIG. 4, by providing the first and second sets of buffers88,90that are powered by both voltage domains, the delay output91of the first and second sets of buffers88,90, and thus the delay of the sense path56, will be gated by the path of greater delay caused by either the lower voltage domain VLor the higher voltage domain VH. Thus, the delay circuit74C is capable of dynamically adjusting or self-tuning the delay in the sense path56regardless of whether the lower voltage domain VLcaused the path of greater delay relative to the higher voltage domain VH, or the higher voltage domain VHcaused the path of greater delay relative to the lower voltage domain VL.

FIG. 6illustrates another example of a delay circuit74that may be provided in the sense path56. A delay circuit74D generates a delay output93according to the slowest delay among a plurality of voltage domains. The delay circuit74D illustrated inFIG. 6is configured to provide for mixing delay between more than two voltage domains; however, this delay circuit74D may be provided in a dual voltage domain system, such as the memory system44illustrated inFIG. 2. A plurality of delay elements94,96,98to provide a plurality of delay chains (i.e., one delay elements, or a plurality of delay elements provided in series), each powered by a different voltage domain, are each driven by the input signal78. The resulting delay chains are then level shifted via level shifters95,97,99to the higher voltage domain VHand each provide an input to a combining circuit exemplified by combining gate100, which in one embodiment may be an AND gate. In this manner, the voltage domains are mixed with the delay of the slowest delay gating the output of the combining gate100. The delay output93of the combining gate100controls and adjusts the delay of the sense signal according to the path having the greater delay among the voltage domains.

The self-tuning delay circuit and related methods described herein may be used in any circuit or system, including but not limited to a memory circuit or system. If employed in a memory circuit or system, the memory circuit or system may employ any type of memory. Examples include, without limitation, SRAM, dynamic RAM (DRAM), synchronous DRAM (SDRAM), data-double-rate (DDR) SDRAM, data-double-rate-two (DDR2) SDRAM, data-double-rate-three (DDR2) SDRAM, Mobile DDR (MDDR) SDRAM, low-power (LP) DDR SDRAM, and LP DDR2 SDRAM. Any of the components of a memory circuit or system employing the self-tuning delay circuit may be provided in any voltage domain among a plurality of voltage domains as long as the memory is powered by a voltage domain providing a sufficient voltage level to keep the memory cell functional, if required by the technology and/or design of the memory.

FIG. 7illustrates a processor-based system120that may employ the circuits and systems described above. The processor-based system120may be included in an electronic device121. The processor-based system120includes a central processing unit (CPU)122that includes a processor124and an integrated cache system126. The cache system126includes a cache management unit127controls access to a cache memory128accessible to the processor124for rapid access to temporary storage for frequently accessed data. The cache memory128may employ the circuits and methods described above. The CPU122is coupled to the system bus129, which interconnects the other devices included in the processor-based system120. As is well known, the CPU122communicates with these other devices by exchanging address, control, and data information over the system bus129. These devices may include any types of devices. As illustrated inFIG. 7, these devices may include system memory130, one or more input devices132, one or more output devices134, a network interface device136, and a display controller138, as examples.

The input devices132may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices134may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device136may be any device configured to allow exchange of data to and from a network140. The network140may be any type of network, including but not limited to a wired or wireless network, private or public network, a local area network (LAN), a wide local area network (WLAN), and the Internet. The network interface device136may support any type of communication protocol desired.

The CPU122may also access system memory130over the system bus31. The system memory130may include circuits and methods previously described above to access the system memory130. The system memory130may include static memory141and/or dynamic memory142. The system memory130may include a program store144and a data store146for the CPU122. The CPU122may also access the display controller138over the system bus31to control information sent to a display154. The display controller138may include a memory controller148and memory150to store data to be sent to the display154in response to communications with the CPU122. The display controller138sends information to the display154to be displayed via a video processor152, which processes the information to be displayed into a format suitable for the display154. The display154may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

A circuit according to embodiments disclosed herein may also be provided in any electronic device for controlling a signal path, including but not limited to a signal path for access memory. Such electronic devices may employ a processor-based system like or including one or more components of the processor-based system120ofFIG. 7. Examples of such electronic devices include, without limitation, mobile phones, cellular phones, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, digital music players, portable music players, digital video players, digital video disc (DVD) players, and portable digital video players.