Liquid crystal display

A pixel electrode and a direction control electrode capacitively coupled to the pixel electrode are provided in a pixel. A pixel thin film transistor is connected to a gate line, a data line, and the pixel electrode. A direction control electrode thin film transistor is connected to a previous gate line, a previous data lines or a next data line, and the direction control electrode. The gate lines are supplied with scanning signals, and each scanning signal includes first and second pulses in a frame. The first pulse of a scanning signal is synchronized with the second pulse of a previous scanning signal.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display.

(b) Description of the Related Art

A typical liquid crystal display (“LCD”) includes an upper panel provided with a common electrode and an array of color filters, a lower panel provided with a plurality of thin film transistors (“TFTs) and a plurality of pixel electrodes, and a liquid crystal layer is interposed therebetween. The pixel electrodes and the common electrode are applied with electric voltages and the voltage difference therebetween causes electric field. The variation of the electric field changes the orientations of liquid crystal molecules in the liquid crystal layer and thus the transmittance of light passing through the liquid crystal layer. As a result, the LCD displays desired images by adjusting the voltage difference between the pixel electrodes and the common electrode.

The LCD has a major disadvantage of its narrow viewing angle, and several techniques for increasing the viewing angle have been developed. Among these techniques, the provision of a plurality of cutouts or a plurality of projections on the pixel electrodes and the common electrode opposite each other along with the vertical alignment of the liquid crystal molecules with respect to the upper and the lower panels is promising.

The cutouts provided both at the pixel electrodes and the common electrode give wide viewing angle by generating fringe field to adjust the tilt directions of the liquid crystal molecules.

The provision of the projections both on the pixel electrode and the common electrode distorts the electric field to adjust the tilt directions of the liquid crystal molecules.

The fringe field for adjusting the tilt directions of the liquid crystal molecules to form a plurality of domains is also obtained by providing the cutouts at the pixel electrodes on the lower panel and the projections on the common electrode on the upper panel.

Among these techniques for widening the viewing angle, the provision of the cutouts has problems that an additional mask for patterning the common electrode is required, an overcoat is required for preventing the effect of the pigments of the color filters on the liquid crystal material, and severe disclination is generated near the edges of the patterned electrode. The provision of the projections also has a problem that the manufacturing method is complicated since it is required an additional process step for forming the projections or a modification of a process step. Moreover, the aperture ratio is reduced due to the projections and the cutouts.

SUMMARY OF THE INVENTION

A liquid crystal display is provided, which includes: a first substrate; a plurality of first signal lines formed on the first substrate and supplied with scanning signals; a plurality of second signal lines formed on the first substrate and supplied with data voltages; a plurality of pixel electrodes formed on the first substrate; a plurality of direction control electrodes formed on the first substrate; a plurality of first thin film transistors, each first thin film transistor connected to a relevant one of the first signal lines, a relevant one of the second signal lines, and a relevant one of the pixel electrodes; a second thin film transistors, each second thin film transistor connected to a previous one of the first signal lines, a previous one or a next one of the second signal lines, and a relevant one of the direction control electrodes; a second substrate facing the first substrate; and a common electrode formed on the second substrate.

Preferably, the liquid crystal display is subjected to a dot inversion and each scanning signal has first and second pulses in a frame. The first pulse in a scanning signal preferably synchronized with the second pulse in a previous scanning signal.

Each pixel electrode may have a cutout overlapping one of the direction control electrodes at least in part.

A liquid crystal display is provided, which includes: a plurality of first signal lines transmitting scanning signals; a plurality of second signal lines transmitting data voltages; and a plurality of first and second pixels connected to the first and the second signal lines, wherein each of the first pixels has a pixel electrode, a direction control electrode, a first thin film transistor having a gate electrode connected to a relevant first signal line, a source electrode connected to a relevant second signal line, and a drain electrode connected to the pixel electrode, and a second thin film transistor having a gate electrode connected to a previous first signal line or a next first signal line, a source electrode connected to a next second signal line, and a drain electrode connected to the direction control electrode; and wherein each of the second pixels has a pixel electrode, a direction control electrode, a first thin film transistor having a gate electrode connected to a relevant first signal line, a source electrode connected to a relevant second signal line, and a drain electrode connected to the pixel electrode, and a second thin film transistor having a gate electrode connected to a previous first signal line, a source electrode connected to a relevant second signal line, and a drain electrode connected to the direction control electrode.

Preferably, the liquid crystal display is subjected to a double-dot inversion and each scanning signal has first and second pulses in a frame.

The first pixels form a plurality of first pixel rows and the second pixels form a plurality of second pixel rows, and the first pixel rows and the second pixel rows may be alternately arranged.

It is preferable that adjacent two of the first and the second pixel rows are supplied with data voltages having equal polarity in pairs and a first pixel row in each pair is supplied with a scanning signal prior to a second pixel row in the pair.

A liquid crystal display is provided, which includes: a first substrate; a plurality of first signal lines formed on the first substrate and supplied with scanning signals; a plurality of second signal lines formed on the first substrate and intersecting the first signal lines; a plurality of pixel electrodes formed on the first substrate; a plurality of direction control electrodes formed on the first substrate; a plurality of first thin film transistors, each first thin film transistor connected to a relevant one of the first signal lines, a relevant one of the second signal lines, and a relevant one of the pixel electrodes; a plurality of second thin film transistor, each second thin film transistor connected to a previous one of the first signal lines, a relevant one of the second signal lines, and a relevant one of the direction control electrodes; a second substrate facing the first substrate; and a common electrode formed on the second substrate.

Preferably, the liquid crystal display is subjected to a column inversion and each scanning signal has first and second pulses in a frame.

A liquid crystal display is provided, which includes: a first substrate; a plurality of first signal lines formed on the first substrate and supplied with scanning signals, each scanning signal having first and second pulses in a frame; a plurality of second signal lines formed on the first substrate and intersecting the first signal lines; a plurality of third signal lines formed on the first substrate, intersecting the second signal lines, and supplied with a common voltage; a plurality of pixel electrodes formed on the first substrate; a plurality of direction control electrodes formed on the first substrate; a plurality of first thin film transistors, each first thin film transistor connected to a relevant one of the first signal lines, a relevant one of the second signal lines, and a relevant one of the pixel electrodes; a plurality of second thin film transistor, each second thin film transistor connected to a previous one of the first signal lines, a relevant one of the third signal lines, and a relevant one of the direction control electrodes; a second substrate facing the first substrate; and a common electrode formed on the second substrate.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

Now, LCDs according to embodiments of this invention will be described in detail with reference to the accompanying drawings.

FIG. 1is an equivalent circuit diagram of an LCD according to a first embodiment of the present invention.

An LCD according to a first embodiment of the present invention includes a TFT array panel, a color filter array panel opposite the TFT array panel, and a liquid crystal layer interposed therebetween. The TFT array panel is provided with a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixels, and a plurality of storage electrode lines extending parallel to the gate lines. The gate lines transmit scanning signals and the data lines transmit image signals. A common voltage Vcom is applied to the storage electrode lines. Each pixel is provided with a pixel TFT for a pixel electrode and a direction-control-electrode TFT DCETFT for a direction control electrode (“DCE”). The pixel TFT includes a gate electrode connected to one of the gate lines, a source electrode connected to one of the data lines, and a drain electrode connected to one of a plurality of pixel electrodes, while the DCE TFT includes a gate electrode connected to a previous gate line, a source electrode connected to one of the storage electrode lines, and a drain electrode connected to one of a plurality of direction control electrodes.

The DCE and the pixel electrode are capacitively coupled, and the capacitor therebetween or its capacitance is represented by CDP. The pixel electrode and a common electrode provided on the color filter array panel form a liquid crystal capacitor, and the liquid crystal capacitor or its capacitance is represented by CLC. The pixel electrode and a storage electrode connected to one of the storage electrode lines form a storage capacitor, and the storage capacitor or its capacitance is represented by CST.

Although it is not shown in the circuit diagram, the pixel electrode according to an embodiment of the present invention has a cutout overlapping the DCE such that the electric field due to the DCE flows out through the cutout. The electric field flowing out through the cutout makes the liquid crystal molecules have pretilt angles. The pretilted liquid crystal molecules are rapidly aligned without dispersion along predetermined directions upon the application of the electric field due to the pixel electrode.

In order to obtain the pretilted liquid crystal molecules using the electric field generated by the DCE, the potential of the DCE relative to the potential of the common electrode (referred to as the “DCE voltage” hereinafter) is larger than the potential of the pixel electrode relative to the potential of the common electrode (referred to as the “pixel voltage” hereinafter) by a predetermined value. The LCD according to an embodiment of the present invention easily satisfies this requirement by isolating the DCE after applying the potential applied to the storage electrode lines to the DCE. The reason will be described now.

The pixel TFT and the DCE TFT are in off state before applying a gate-on voltage to the previous gate line Gi−1. Upon application of the gate-on voltage to the previous gate line Gi−1, the common voltage is applied to the DCE. Accordingly, the voltage Vp of the pixel electrode becomes to have a value lower than the voltage VDCEof the DCE. When the DCE TFT is turned off after charging, the DCE floats to make the voltage charged in the DCE capacitor CDPconstant. Accordingly, the voltage VDCEof the floating DCE is always larger than the voltage Vp of the pixel electrode irrespective of the potential change of the pixel electrode. For example, when the voltage Vp of the pixel electrode is increased when the pixel TFT is turned on, the voltage VDCEof the DCE follows the voltage increase of the pixel electrode in order to maintain the potential difference between the DCE and the pixel electrode.

This is described in terms of a circuital relation.

A voltage across a capacitor in an electrical circuit is given by

A floating electrode is equivalent to an electrode connected to a resistor having infinite resistance (R=∞). Therefore, i=0 and V—C=V—0, that is, the initial voltage across the capacitor is maintained. In other words, the potential of a floating electrode increases or decreases coupled with the potential of the other electrode.

Similarly, the voltage VDCEof the floating DCE maintains lower than the negative voltage Vp of the pixel electrode regardless of the voltage Vp of the pixel electrode.

According to an embodiment of the present invention, the DCE TFT is connected to the storage electrode lines such that the common voltage is applied to the DCE. Hence, the potentials of the two electrodes increases or decreases to have substantially the same polarity irrespective of the polarity of the potential applied to the pixel electrode in the next frame. As a result, the present invention is applied any inversion type such as line inversion and dot inversion.

For the same gray, there is no variation of the potential difference between the DCE and the pixel electrode irrespective of the grays of previous and next frames, thereby ensuring stability of image quality.

The disconnection of the DCE TFTs from the data lines prevents the increase of the load of the data lines.

Now, a detailed embodiment of the present invention is described with reference toFIGS. 2A to 2C.

FIG. 2Ais a layout view of an LCD according to an embodiment of the present invention, andFIGS. 2B and 2Care sectional views of the LCD shown inFIG. 2Ataken along the lines IIB-IIB′ and IIC-IIC′.

An LCD according to a first embodiment of the present invention includes a lower panel, an upper panel facing the lower panel, and a vertically (or homeotropically) aligned liquid crystal layer interposed between the lower panel and the upper panel.

The lower panel will now be described more in detail.

A plurality of gate lines121are formed on an insulating substrate110and a plurality of data lines171are formed thereon. The gate lines121and the data lines171are insulated from each other and intersect each other to define a plurality of pixel areas.

Each pixel area is provided with a pixel TFT, a DCE TFT, a DCE and a pixel electrode. The pixel TFT has three terminals, a first gate electrode123a, a first source electrode173aand a first drain electrode175awhile the DCE TFT has three terminals, a second gate electrode123b, a second source electrode173band a second drain electrode175b. The pixel TFT is provided for switching the signals transmitted to the pixel electrode190while the DCE TFT is provided for switching the signals entering the DCE178. The gate electrode123a, the source electrode173aand the drain electrode175of the pixel TFT are connected to corresponding one of the gate lines121, one of the data lines171and the pixel electrode190, respectively. The gate electrode123b, the source electrode173band the drain electrode175bof the DCE TFT are connected to previous one of the gate lines121, corresponding one of the storage electrode lines131and the DCE178, respectively. The DCE178is applied with a direction-controlling voltage for controlling the pre-tilts of the liquid crystal molecules to generate a direction-controlling electric field between the DCE178and the common electrode270. The DCE178is formed in a step for forming the data lines171.

The layered structure of the lower panel will be described in detail.

A plurality of gate lines121extending substantially in a transverse direction are formed on an insulating substrate110, and a plurality of first and second gate electrodes123aand123bare connected to the gate lines121. A plurality of storage electrode lines131and a plurality of sets of first to fourth storage electrodes133a-133dare also formed on the insulating substrate110. The storage electrode lines131extend substantially in the transverse direction, and the first and the second storage electrodes133aand133bextend from the storage electrode line131in a longitudinal direction. The third and the fourth storage electrodes133cand133dextend in the transverse direction and connect the first storage electrode133aand the second storage electrode133b.

The gate wire121,123aand123band the storage electrode wire131and133a-133dare preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the gate wire121,123aand123band the storage electrode wire131and133a-133dinclude a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

A gate insulating layer140is formed on the gate wire121,123aand123band the storage electrode wire131and133a-133d.

A semiconductor layer151,154a,154band155preferably made of amorphous silicon is formed on the gate insulating layer140. The semiconductor layer151,154a,154band155includes a plurality of first and second channel semiconductors154aand154bforming channels of TFTs, a plurality of data-line semiconductors151located under the data lines171, and a plurality of intersection semiconductors155located near the intersections of DCEs178and the storage electrodes133cand133dfor ensuring insulation therebetween.

An ohmic contact layer161,163a,163b,165aand165bpreferably made of silicide or n+ hydrogenated amorphous silicon heavily doped with n type impurity is formed on the semiconductor layer151,154a,154band155.

A data wire171,173a,173b,175aand175bis formed on the ohmic contact layer161,163a,163b,165aand165band the gate insulating layer140. The data wire171,173a,173b,175aand175bincludes a plurality of data lines171extending in the longitudinal direction and intersecting the gate lines121to form a plurality of pixels, a plurality of first source electrodes173abranched from the data lines171and extending onto portions163aof the ohmic contact layer, a plurality of first drain electrodes175adisposed on portions165aof the ohmic contact layer, located opposite the first source electrodes173awith respect to the first gate electrodes123aand separated from the first source electrodes173a, and a plurality of second source electrodes173band a plurality of second drain electrodes175bdisposed on respective portions163band165bopposite each other with respect to the second gate electrodes123b. One end portion of each data line171is widened for connection to an external circuit.

A plurality of DCEs178are formed in the pixel areas defined by the intersections of the gate lines121and the data lines171. Each DCE178includes a plurality of X-shaped metal pieces connected to one another and is connected to the second drain electrode175b. The data wire171,173a,173b,175aand175band the DCEs178are preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the data wire171,173a,173b,175aand175band the DCEs178include a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

A passivation layer180preferably made of silicon nitride or organic insulator is formed on the data wire171,173a,173b,175aand175b.

The passivation layer180is provided with a plurality of contact holes181exposing the first drain electrodes175a, a plurality of contact holes182extending to the gate insulating layer140and exposing the storage electrode lines131, and a plurality of contact holes183exposing the second source electrodes173b.

A plurality of pixel electrodes190are formed on the passivation layer180. Each pixel electrode190is connected to the first drain electrode175athrough the contact hole181and has a plurality of X-shaped cutouts191and a plurality of linear cutouts192. The X-shaped cutouts191overlap the X-shaped portions of the DCE178while the linear cutouts192overlap the third and the fourth storage electrodes133cand133d. The DCE178broadly overlaps peripheries of the cutouts191as well as the cutouts191themselves to form a storage capacitance along with the pixel electrode190.

A plurality of bridges92connecting the storage electrode lines131and the second source electrodes173bthrough the contact holes182and183are also formed on the passivation layer. Furthermore, a plurality of contact assistants (not shown) connected to the end portions of the gate lines121and the data lines171are formed on the passivation layer180. The pixel electrodes190, the bridges92, and the contact assistants are preferably formed of indium zinc oxide (“IZO”). Alternatively, the pixel electrodes190, the bridges92, and the contact assistants are preferably made of indium tin oxide (“ITO”).

To summarize, each pixel electrode190has the plurality of cutouts191and192for partitioning a pixel region into a plurality of domains, and the first cutouts191overlap the DCE178while the second cutouts192overlap the storage electrodes133cand133d. The DCE178and the first cutouts191are aligned such that the DCE178is exposed through the first cutouts191to be seen in front view. The storage electrode line131and the DCE178are connected via the DCE TFT while the data line171and the pixel electrode190are connected via the pixel TFT, and the pixel electrode190and the DCE178are aligned to form a storage capacitance.

According to another embodiment of the present invention, the DCEs178include substantially the same layer as the gate wire121,123aand123b. The portions of the passivation layer180on the DCEs178may be removed to form a plurality of openings.

The upper substrate210will no be described in detail.

A black matrix220for preventing light leakage, a plurality of red, green and blue color filters230, and a common electrode270preferably made of a transparent conductor such as ITO or IZO are formed on an upper substrate210preferably made of transparent insulating material such glass.

A plurality of liquid crystal molecules contained in the liquid crystal layer3is aligned such that their director is perpendicular to the lower and the upper substrates110and210in absence of electric field. The liquid crystal layer3has negative dielectric anisotropy.

The lower substrate110and the upper substrate210are aligned such that the pixel electrodes190exactly match and overlap the color filters230. In this way, a pixel region is divided into a plurality of domains by the cutouts191and192. The alignment of the liquid crystal layer3in each domain is stabilized by the DCE178.

This embodiment illustrates the liquid crystal layer3having negative dielectric anisotropy and homeotropic alignment with respect to the substrates110and210. However, the liquid crystal layer3may have positive dielectric anisotropy and homogeneous alignment with respect to the substrates110and210.

A method of manufacturing a TFT array panel of an LCD having the above-described structure will be described.

FIGS. 3A to 3Dare sectional views of a TFT array panel for an LCD sequentially illustrating a manufacturing method thereof according to a first embodiment of the present invention.

First, as shown inFIG. 3A, a conductive layer preferably made of metal is deposited by sputtering and either dry-etched or wet-etched by a first photo-etching step using a mask to form a gate wire and a storage electrode wire on a substrate110. The gate wire includes a plurality of gate lines121and a plurality of gate electrodes123, and the storage wire includes a plurality of storage electrode lines131and a plurality of storage electrodes133a-133d.

As shown inFIG. 3B, a gate insulating layer 140 with 1,500-5,000 Å thickness, a hydrogenated amorphous silicon layer with 500-2,000 Å thickness, and a doped amorphous silicon layer with 300-600 Å thickness are sequentially deposited by chemical vapor deposition (“CVD”). The doped amorphous silicon layer and the amorphous silicon layer are patterned by a photo-etching step using a mask to form an ohmic contact layer160a,160band161and an amorphous silicon layer151,154aand154b.

Thereafter, as shown inFIG. 3C, a conductive layer with 1,500-3,000 Å thickness preferably made of metal is deposited by sputtering and patterned by a photo-etching step using a mask to form a data wire and a plurality of DCEs178. The data wire includes a plurality of data lines171, a plurality of source electrodes173aand173b, and a plurality of drain electrodes175aand175b.

Then, portions of the ohmic contact layer160aand160b, which are not covered by the source electrodes173aand173band the drain electrodes175aand175b, are removed such that an ohmic contact layer163a,163b,165aand165bincluding a plurality of separated portions is formed and portions of the semiconductor layer151between the source electrodes173aand173band the drain electrodes175aand175bare exposed.

As shown inFIG. 3D, a passivation layer180is formed by coating an organic insulating material having low dielectric constant and good planarization characteristic or by CVD of low dielectric insulating material such as SiOF or SiOC having a dielectric constant equal to or less than 4.0. The passivation layer180together with the gate insulating layer140is patterned by a photo-etching step using a mask to form a plurality of contact holes181,182and183.

Finally, as shown inFIG. 2A, an ITO layer or an IZO layer with thickness of 1500-500 Å is deposited and photo-etched using a mask to form a plurality of pixel electrodes190, a plurality of connecting bridges92, and a plurality of contact assistants (not shown).

This technique is applied to a manufacturing method using five masks as described above. However, the technique may be well adapted for a method of a TFT array panel for an LCD using four masks. It is described in detail with reference to the drawings.

FIG. 4is a layout view of a TFT array panel for an LCD according to a second embodiment of the present invention, andFIG. 5is a sectional view of the TFT array panel shownFIG. 4taken along the lines V-V′ and V′-V″.

A TFT array panel for an LCD according to a second embodiment of the present invention is manufactured by using four masks and has a feature compared with a TFT array panel manufactured by using five masks, which will be described now.

An ohmic contact layer161,163a,163b,165aand165bformed under a plurality of DCEs178and a data wire including a plurality of data lines171, a plurality of source electrodes173aand173b, and a plurality of the drain electrodes175aand175bhas substantially the same shape as the data wire171,173a,173b,175a,175band179and the DCEs178. An amorphous silicon layer151,154a,154band158has substantially the same shape as the data wire and the DCEs178except that channel portions between the source electrodes173aand173band the drain electrodes175aand175bare connected. Remaining structure is substantially the same as a TFT array panel manufactured by a five-mask process.

FIG. 4illustrates an expanded end portion125of the gate line121, an expanded end portion135of the storage electrode line131, and an expanded end portion179of the data line171as well as contact assistants95,99and97.

A method of manufacturing a TFT array panel will be now described.

FIGS. 6A to 11Bare layout views and sectional views of a TFT array panel for an LCD sequentially illustrating a manufacturing method thereof.

First, as shown inFIGS. 6A and 6B, Al, Ag, their alloys or the like is deposited and photo-etched to form a gate wire including a plurality of gate lines121and125and a plurality of gate electrodes123, and a storage electrode wire131and133a-133d. (First Mask)

As shown inFIG. 7, a silicon nitride gate insulating layer140with 1,500-5,000 Å thickness, an amorphous silicon layer150with 500-2,000 Å thickness, and a contact layer160with 300-600 Å thickness are sequentially deposited by CVD. A conductive layer170preferably made of Al, Ag or their alloys is deposited by preferably sputtering, and a photoresist film PR with thickness of 1-2 microns is coated thereon.

Thereafter, the photoresist film PR is exposed to light through a mask and is developed to form a photoresist pattern PR as shown inFIGS. 8A and 8B. Each portion of the photoresist pattern PR located on a channel area C of a TFT, which is placed between a source electrode173aor173band a drain electrode175aor175b, is thicker than each portion of the photoresist pattern PR located on a data area A where a data wire will be formed. All portions of the photoresist film PR on the remaining areas B are removed. Here, the ratio of the thickness of the photoresist pattern PR on the channel area C and on the data area A is adjusted depending on process conditions of subsequent etching steps described later, and it is preferable that the thickness of the former is equal to or less than a half of that of the latter, for example, equal to or less than 4,000 Å. (Second Mask)

The position-dependent thickness of the photoresist pattern is obtained by several techniques. A slit pattern, a lattice pattern or a translucent film is provided on the mask in order to adjust the light transmittance in the area C.

When using a slit pattern, it is preferable that width of the slits and a gap between the slits is smaller than the resolution of an exposer used for the photolithography. In case of using a translucent film, thin films with different transmittances or different thickness may be used to adjust the transmittance on the masks.

When a photoresist film is exposed to light through such a mask, polymers of a portion directly exposed to the light are almost completely decomposed, and those of a portion exposed to the light through a slit pattern or a translucent film are not completely decomposed because the amount of a light irradiation is small. The polymers of a portion of the photoresist film blocked by a light-blocking film provided on the mask are hardly decomposed. After the photoresist film is developed, the portions containing the polymers, which are not decomposed, is left. At this time, the thickness of the portion with less light exposure is thinner than that of the portion without light exposure. Since too long exposure time decomposes all the molecules, it is necessary to adjust the exposure time.

The small thickness of the photoresist film may be obtained using reflow. That is, the photoresist film is made of a reflowable material and exposed to light through a normal mask having opaque and transparent portions. The photoresist film is then developed and subject to reflow such that portions of the photoresist film flows down onto areas without photoresist, thereby forming thin portions.

Next, the photoresist pattern PR and the underlying layers including the conductive layer170, the contact layer160and the semiconductor layer150are etched such that the data wire and the underlying layers are left on the data areas A, only the semiconductor layer is left on the channel areas C, and all the three layers170,160and150are removed to expose the gate insulating layer140on the remaining areas B.

First, as shown inFIG. 9, the exposed portions of the conductive layer170on the other areas B are removed to expose the underlying portions of the contact layer160. Both dry etch and wet etch are selectively used in this step and preferably performed under the condition that the conductive layer170is easily etched and the photoresist pattern PR are hardly etched. However, since it is hard to identify the above-described condition for dry etch, and the dry etch may be performed under the condition that the photoresist pattern PR and the conductive layer170are etched simultaneously. In this case, the portions of the photoresist pattern PR on the channel areas C for dry etch are preferably made to be thicker than those for the wet etch to prevent the removal of the portions of the photoresist pattern PR on the channel areas C and thus the exposure of the underlying portions of the conductive layer170.

As a result, as shown inFIG. 9, only the portions171,170aand170bof the conductive layer170on the channel areas C and the data areas A are left and the portions of the conductive layer170on the remaining areas B are removed to expose the underlying portions of the contact layer160. Here, the data-wire conductors171,170aand170bhave substantially the same planar shapes as the data wire171,173a,173b,175a,175band179except that the source electrodes173aand173band the drain electrodes175aand175bare not disconnected from but connected to each other. When using dry etch, the thickness of the photoresist pattern PR is reduced to an extent.

Next, as shown inFIG. 9, the exposed portions of the contact layer160and the underlying portions of the amorphous silicon layer150on the areas B as well as the portions of the photoresist pattern PR on the channel areas C are removed by dry etch. The etching is performed under the conduction that the photoresist pattern PR, the contact layer160and the semiconductor layer150are easily etched and the gate insulating layer140is hardly etched. (It is noted that etching selectivity between the intermediate layer and the semiconductor layer is nearly zero.) In particular, it is preferable that the etching ratios for the photoresist pattern PR and the semiconductor layer150are nearly the same. For instance, the etched thicknesses of the photoresist pattern PR and the semiconductor layer150can be nearly the same by using a gas mixture of SF6and HCl, or a gas mixture of SF6and O2. When the etching ratios for the photoresist pattern PR and for the semiconductor pattern150are the same, the initial thickness of the portions of the photoresist pattern PR on the channel areas C is equal to or less than the sum is of the thickness of the semiconductor layer150and the thickness of the contact layer160.

Consequently, as shown inFIG. 10, the portions of the photoresist pattern PR on the channel areas C are removed to expose the underlying portions of source/drain (“S/D”) conductors170aand170b, and the portions of the contact layer160and the semiconductor layer150on the remaining areas B are removed to expose the underlying portions of the gate insulating layer140. In the meantime, the portions of the photoresist pattern PR on the data areas A are also etched to become thinner. Moreover, the semiconductor pattern151,154a,154band158is completed in this step. A plurality of ohmic contacts161,160a,160band168are formed on the semiconductor pattern151,154a,154band158.

Then, photoresist remnants left on the surface of the S/D conductors170aand170bon the channel areas C are removed by ashing.

Next, as shown inFIGS. 11A and 11B, portions of the S/D conductors170aand170band the underlying portions of the S/D ohmic contacts160aand160bon the channel areas C are etched to be removed. Here, the etching of both the S/D conductors170aand170band the S/D ohmic contacts160aand160bmay be done using only dry etching. Alternatively, the S/D conductors170aand170bare etched by wet etching and the S/D ohmic contacts160aand160bare etched by dry etching. In the former case, it is preferable to perform the etching under the condition that etching selectivity between the S/D conductors170aand170band the S/D ohmic contacts160aand160bis high. It is because the low etching selectivity makes the determination of the etching finish point difficult, thereby causing the adjustment of the thickness of the portions of the semiconductor pattern154aand154bleft on the channel areas C to be difficult. In the latter case alternately applying wet etching and dry etching, a stepwise lateral sidewall is formed since the wet etch etches the lateral sides of the S/D conductors170aand170b, while the dry etch hardly etches the lateral sides of the S/D ohmic contacts160aand160b. Examples of etching gases used for etching the S/D ohmic contacts160aand160bare a gas mixture of CF4and HCl and a gas mixture of CF4and O2. Use of the gas mixture of CF4and O2enables to obtain uniform thickness of etched portions of the semiconductor pattern154aand154b. In this regard, the exposed portions of the semiconductor pattern154aand154bare etched to have a reduced thickness, and the portions of the photoresist pattern PR on the data-wire areas A are also etched to have a reduced thickness. This etching is performed under the condition that the gate insulating layer140is not etched, and it is preferable that the photoresist pattern PR is thick enough to prevent the portions of the photoresist pattern PR on the data-wire areas A from being removed to expose the underlying portions of the data wire171,173a,173b,175a,175band179.

Accordingly, the source electrodes173aand173band the drain electrodes175aand175bare separated from each other, and, simultaneously, the data wire171,173a,173b,175a,175band179and the ohmic contact pattern161,163a,163b,165aand165bthereunder are completed.

Finally, the portions of the photoresist pattern PR left on the data areas A are removed. Alternatively, the portions of the photoresist pattern PR on the data areas A are removed after the portions of the S/D conductors170aand170bon the channel areas C are removed and before the underlying portions of the S/D ohmic contacts160aand160bare removed.

As described above, wet etching and dry etching may be performed one after the other, but only dry etching may be used. The latter is relatively simple but it is not easy to find a proper etching condition compared with the former. On the contrary, it is easy to find a proper etching condition for the former case but the former is relatively complicated compared with the latter.

Thereafter, as shown inFIGS. 4 and 5, a passivation layer180is formed by growing a-Si:C:O or a-Si:O:F by CVD, by depositing silicon nitride, or by coating an organic insulating material such as acryl-based material. When forming an a-Si:C:O layer, SiH(CH3)3, SiO2(CH3)4, (SiH)4O4(CH3)4, Si(C2H5O)4or the like used as basic source, oxidant such as N2O or O2, and Ar or He are mixed in gaseous states to flow for the deposition. For an s-Si:O:F layer, the deposition is performed with flowing a gas mixture including SiH4, SiF4or the like and an additional gas of O2. CF4may be added as a secondary source of fluorine.

As shown inFIGS. 4 and 5, the passivation layer180together with the gate insulating layer140is photo-etched to form a plurality of contact holes181,182,183,184,185and186exposing the first drain electrodes175a, the second source electrodes173b, the storage electrode lines131, the expanded end portions125of the gate lines121, the expanded end portions135of the storage electrode lines131, and the expanded end portions179of the data lines171. It is preferable that the area of the contact holes184,185and186exposing the end portions125,179and135is equal to or larger than 0.5 mm×15 μm and not larger than 2 mm×60 μm. (Third Mask)

Finally, an ITO layer or an IZO layer with a thickness of 1500-500 Å is deposited and photo-etched to form a plurality of pixel electrodes190connected to the drain electrodes175, a plurality of contact assistants95connected to the expanded end portions125of the gate lines121, a plurality of contact assistants97connected to the expanded end portions179of the data lines171, and a plurality of bridges92connecting the second source electrodes173band the storage electrode lines131. (Fourth Mask)

Since Cr etchant can be used as an etchant for an IZO layer, the exposed portions of the metal for the data wire and the gate wire through the contact holes are not corroded in the photo-etching step for forming the pixel electrodes190, the contact assistants95and97and the bridges92from the IZO layer. An example of the Cr etchant is (HNO3/(NH4)2Ce(NO3)6/H2O). The IZO layer is deposited at temperature preferably in a range from a room temperature to 200° C. for minimizing the contact resistance at the contacts. A preferred example of a target for the IZO layer includes In2O3and ZnO. The content of ZnO is preferably in a range between 15 atm % and 20 atm %.

Meanwhile, nitrogen gas is preferably used for the pre-heating process before the deposition of the ITO layer or the IZO layer. This is to prevent the formation of metal oxides on portions of the metallic layers exposed through the contact holes181,182,183,184,185and186.

FIG. 12is a schematic diagram of the TFT array panels for an LCD shown inFIGS. 2A and 4according to an embodiment of the present invention.

A TFT T1connected to a data line171switches signals transmitted to a pixel electrode190while a TFT T2connected to a storage electrode line switches signals entering a DCE178. The pixel electrode190and the DCE178is capacitively coupled. For the same gray, there is no variation of the potential difference between the DCE178and the pixel electrode190. Therefore, stability of image quality is ensured irrespective of inversion types such as line inversion, dot inversion or the like.

A source electrode of a DCE TFT according to the first and the second embodiments of the present invention is connected to a storage electrode line. However, the source electrode may be connected to a previous data line, which has some problems.

First, the application of the gate-on voltage to a previous gate line (represented as Gate N-1inFIG. 1) causes a pixel electrode located diagonal to a relevant pixel applied with a gray voltage and a DCE of the relevant pixel applied with an initial voltage. The initial voltage of the DCE is equal to the gray voltage of the diagonally-located pixel electrode. Accordingly, the potential difference VDPbetween the DCE and a pixel electrode of the relevant pixel is determined by the gray voltage of the diagonally-located pixel electrode. For example, a low gray voltage such as a black voltage applied to the diagonally-located pixel electrode causes the low initial voltage of the DCE, thereby resulting in a low VDP. A low VDPmeans that the potential difference between the DCE and the pixel electrode is small, and thus lateral field due to the DCE is weak. Accordingly, the arrangement of the liquid crystal molecules is unstable, thereby causing unstable texture. In order to short response time, the texture is preferably stable, which is obtained by the potential difference VDPhigher than about 5 V.

Next, the VDPis defined by a voltage across a capacitor CDP, which is serially connected to an equivalent capacitor of CLCand CST. Accordingly, the value of VDPincreases as the capacitance CDPdecreases. For reducing the capacitance CDP, the overlapping area between the pixel electrode and the DCE is designed to be minimized. However, this may cause image quality to be sensitively varied by misalignment of a mask during a manufacturing process and light leakage near the DCE. For the former case, the mask misalignment changes the overlapping area of the pixel electrode and the DCE, and this directly affect on the image quality. The latter case occurs when the initial voltage of the DCE is high (that is, the gray voltage applied to the diagonally-located pixel electrode is high) and a black voltage is applied to the relevant pixel. The high voltage of the DCE forces to move the liquid crystal molecules to yield light leakage, which may not be blocked by the narrow DCE. The light leakage decreases contrast ratio.

A third embodiment for solving these problems will be described now.

FIG. 13is an equivalent circuit diagram of an LCD according to a third embodiment of the present invention.

An LCD according to an embodiment of the present invention includes a TFT array panel, a color filter array panel opposite the TFT array panel, and a liquid crystal layer interposed therebetween. The TFT array panel is provided with a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixels, and a plurality of storage electrode lines extending parallel to the gate lines. The gate lines transmit scanning signals and the data lines transmit image signals. A common voltage Vcom is applied to the storage electrode lines. Each pixel is provided with a pixel TFT for a pixel electrode and first and second DCE TFTs DCETFT1and DCETFT2for a DCE. The pixel TFT includes a gate electrode connected to a relevant gate line, a source electrode connected to a relevant data line, and a drain electrode connected to a relevant pixel electrode. The first DCE TFT includes a gate electrode connected to a previous gate line, a source electrode connected to a previous data line, and a drain electrode connected to a relevant DCE, while the second DCE TFT includes a gate electrode connected to the previous gate line, a source electrode connected to the relevant data line, and a drain electrode connected to the relevant pixel electrode.

The DCE is capacitively coupled with the pixel electrode, and the capacitor therebetween or its capacitance is represented by CDP. The pixel electrode and a common electrode provided on the color filter array panel form a liquid crystal capacitor, and the liquid crystal capacitor or its capacitance is represented by CLC. The pixel electrode and a storage electrode connected to one of the storage electrode lines form a storage capacitor, and the storage capacitor or its capacitance is represented by CST.

Although it is not shown in the circuit diagram, the pixel electrode according to an embodiment of the present invention has a cutout overlapping the DCE such that the electric field due to the DCE flows out through the cutout. The electric field flowing out through the cutout makes the liquid crystal molecules have pretilt angles. The pretilted liquid crystal molecules are rapidly aligned without dispersion along predetermined directions upon the application of the electric field due to the pixel electrode.

The LCD is assumed to be subject to dot inversion. The application of a gate-on signal to the previous gate line Gate N-1turns on both the DCE TFTs DCETFT1and DCETFT2to make the DCE have a (+) gray voltage and to make the pixel electrode have a (−) gray voltage. The initial voltage of the DCE is the difference between the positive gray voltage and the negative gray voltage from the data lines Data A and Data B, respectively, which is twice or more the initial voltage of the DCE without the second DCE TFT DCETFT2. When the pixel TFT is turned on and the DCE TFTs DCETFT1and DCETFT2are turned off upon application of the gate-on signal to the relevant gate line Gate N, the DCE floats and thus the potential of the DCE also increases with maintaining the potential difference VDPfrom the potential of the pixel electrode. Accordingly, the structure according to the third embodiment ensures higher VDPto enhance the stability of the arrangement of the liquid crystal molecules, thereby stabilizing the texture.

Furthermore, since the VDPis determined by the gray voltages of two adjacent previous pixels and is rarely affected by the capacitance CDP, the capacitance CDPneed not be reduced to allow the DCE to have a sufficient width for overlapping the pixel electrode. Accordingly, the light leakage near the DCE is blocked and the image quality is not considerably affected by the mask misalignment.

In addition, the high VDP improves the response time and the afterimage.

The structure shown inFIG. 13is suitable for dot inversion and line inversion, while other structures having modified connections of three TFTs may be adapted for other types of inversion.

Now, an exemplary TFT array panel for an LCD according to the third embodiment of the present invention is described in detail with reference toFIGS. 14 to 17.

FIG. 14is a layout view of an LCD according to the third embodiment of the present invention,FIG. 15is a sectional view of the LCD shown inFIG. 14taken along the line XV-XV′,FIG. 16is a sectional view of the LCD shown inFIG. 14taken along the line XVI-XVI′,FIG. 17is a sectional view of the LCD shown inFIG. 14taken along the lines XVII-XVII′ and XVII′-XVII″.

An LCD according to a third embodiment of the present invention includes a lower panel, an upper panel facing the lower panel, and a vertically aligned liquid crystal layer interposed between the lower panel and the upper panel.

The lower panel will now be described more in detail.

A plurality of gate lines121are formed on an insulating substrate110and a plurality of data lines171are formed thereon. The gate lines121and the data lines171are insulated from each other and intersect each other to define a plurality of pixel areas.

Each pixel area is provided with a pixel TFT, a first DCE TFT, a second DCE TFT, a DCE and a pixel electrode. The pixel TFT has three terminals, a first gate electrode123a, a first source electrode173aband a first drain electrode175a. The first DCE TFT has three terminals, a second gate electrode123b, the first source electrode173aband a second drain electrode175bwhile the second DCE TFT has three terminals, a third gate electrode123c, a second source electrode173cand a third drain electrode175c. The first source electrode173abis used both for the pixel TFT and the first DCE TFT. The pixel TFT and the first DCE TFT are provided for switching the signals transmitted to the pixel electrode190while the second DCE TFT is provided for switching the signals entering the DCE178. The gate electrode123a, the source electrode173aand the drain electrode175of the pixel TFT are connected to relevant one of the gate lines121, relevant one of the data lines171and the pixel electrode190, respectively. The gate electrode123b, the source electrode173band the drain electrode175bof the first DCE TFT are connected to previous one of the gate lines121, the relevant data line171and the pixel electrode190, respectively. The gate electrode123c, the source electrode173cand the drain electrode175cof the second DCE TFT are connected to the previous gate line121, previous one of the data lines171and the DCE178, respectively. The DCE178is applied with a direction-controlling voltage for controlling the pre-tilts of the liquid crystal molecules to generate a direction-controlling electric field between the DCE178and the common electrode270. The DCE178is formed in a step for forming the data lines171.

The layered structure of the lower panel will be described in detail.

A plurality of gate lines121extending substantially in a transverse direction are formed on an insulating substrate110, and a plurality of first to third gate electrodes123a-123care connected to the gate lines121. One end portion125of each gate line121is widened.

A plurality of first and second storage electrode lines131aand131band a plurality of sets of first to fourth storage electrodes133a,133b,133cand133dare also formed on the insulating substrate110. The first and the second storage electrode lines131aand131bextend substantially in the transverse direction. The first and the second storage electrodes133aand133bextend from the first and the second storage electrode lines131aand131bin a longitudinal direction and are curved to extend in an oblique direction while the third and the fourth storage electrodes134aand134bextend in the longitudinal direction. A first storage wire including the first storage electrode lines131aand the first and the third electrodes133aand134aand a second storage wire including the second storage electrode lines131band the second and the fourth electrodes133band134bhave inversion symmetry.

The gate wire121,123a-123cand125and the storage electrode wire131,133a,133b,134aand134bare preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the gate wire121,123aand123band the storage electrode wire131and133a-133dinclude a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

A gate insulating layer140is formed on the gate wire121,123a-123cand125and the storage electrode wire131,133a,133b,134aand134b.

A semiconductor layer151,154aband154cpreferably made of amorphous silicon is formed on the gate insulating layer140. The semiconductor layer151,154aband154cincludes a plurality of first and second channel semiconductors154aband154cforming channels of TFTs and a plurality of data-line semiconductors151located under the data lines171.

An ohmic contact layer161,163ab,163cand165a-165cpreferably made of silicide or n+ hydrogenated amorphous silicon heavily doped with n type impurity is formed on the semiconductor layer151,154aband154c.

A data wire171,173ab,173c,175a-175cand179is formed on the ohmic contact layer161,163ab,163cand165a-165cand the gate insulating layer140. The data wire171,173ab,173c,175a-175cand179includes a plurality of data lines171extending in the longitudinal direction and intersecting the gate lines121to form a plurality of pixels, a plurality of first source electrodes173abbranched from the data lines171and extending onto portions163abof the ohmic contact layer, a plurality of first and second drain electrodes175aand175bdisposed on portion165aand165bof the ohmic contact layer, located opposite the first source electrodes173aband separated from the first source electrodes173ab, and a plurality of second source electrodes173cand a plurality of third drain electrodes175cdisposed on respective portions163cand165copposite each other with respect to the third gate electrodes123c. One end portion of each data line171is widened for connection to an external circuit.

A plurality of DCEs178and178a-178care formed in the pixel areas defined by the intersections of the gate lines121and the data lines171. Each DCE178and178a-178cincludes a V-shaped stem178and a chevron-shaped branch178a-178cand is connected to the third drain electrode175c. The data wire171,173ab,173c,175a-175cand179and the DCEs178and178a-178care preferably made of Al, Cr or their alloys, Mo or Mo alloy. If necessary, the data wire171,173ab,173c,175a-175cand179and the DCEs178and178a-178cinclude a first layer preferably made of Cr or Mo alloys having excellent physical and chemical characteristics and a second layer preferably made of Al or Ag alloys having low resistivity.

A passivation layer180preferably made of silicon nitride or organic insulator is formed on the data wire171,173ab,173c,175a-175cand179.

The passivation layer180is provided with a plurality of first and second contact holes181and182exposing the first and the second drain electrodes175aand175b, a plurality of third contact holes183extending to the gate insulating layer140exposing the end portions125of the gate lines121, and a plurality of fourth contact holes184exposing the end portions179of the data lines171. The contact holes exposing the end portions125and179may have various shapes such as polygon or circle. The area of the contact hole is preferably equal to or larger than 0.5 mm×15 μm and not larger than 2 mm×60 μm.

A plurality of pixel electrodes190are formed on the passivation layer180. Each pixel electrode190is connected to the first and the second drain electrode175aand175bthrough the first and the second contact holes181and182, respectively. The pixel electrode190has a transverse cutout191and a plurality of oblique cutouts192a,192b,193a,193b,194a,194b,195aand195b. The transverse cutout191bisects the pixel electrode190into upper and lower halves, and the oblique cutouts192a,192b,193a,193b,194a,194b,195aand195bhave inversion symmetry with respect to the transverse cutout191. Some cutouts191,192a,192b,194a,194b,195aand195boverlap the DCE178and178a-178cwhile the other cutouts193aand193boverlap the storage electrodes133aand133b.

Furthermore, a plurality of contact assistants95and97are formed on the passivation layer180. The contact assistants95and97are connected to the end portions125and179through the contact holes183and184, respectively. The pixel electrodes190and the contact assistants95and97are preferably formed of IZO. Alternatively, the pixel electrodes190and the contact assistants95and97are preferably made of ITO.

To summarize, each pixel electrode190has the plurality of cutouts191,192a,192b,193a,193b,194a,194b,195aand195bfor partitioning a pixel region into a plurality of domains, and the cutouts191,192a,192b,194a,194b,195aand195boverlap the DCE178and178a-178c. The DCE178and178a-178cand the cutouts191,192a,192b,194a,194b,195aand195bare aligned such that the DCE178and178a-178cis exposed through the cutouts191,192a,192b,194a,194b,195aand195bto be seen in front view. The DCE178and178a-178cis connected to the second DCE TFT while the pixel electrode190is connected to the first DCE TFT the pixel TFT, and the pixel electrode190and the DCE178are aligned to form a storage capacitance.

According to another embodiment of the present invention, the DCEs178and178a-178cinclude substantially the same layer as the gate wire121,123a-123cand125. The portions of the passivation layer180on the DCEs178and178a-178cmay be removed to form a plurality of openings.

The upper substrate210will no be described in detail.

A black matrix220for preventing light leakage, a plurality of red, green and blue color filters230, and a common electrode270preferably made of a transparent conductor such as ITO or IZO are formed on an upper substrate210preferably made of transparent insulating material such glass.

A plurality of liquid crystal molecules contained in the liquid crystal layer3is aligned such that their director is perpendicular to the lower and the upper substrates110and210in absence of electric field. The liquid crystal layer3has negative dielectric anisotropy.

The lower substrate110and the upper substrate210are aligned such that the pixel electrodes190exactly match and overlap the color filters230. In this way, a pixel region is divided into a plurality of domains by the cutouts191,192a,192b,193a,193b,194a,194b,195aand195b. The alignment of the liquid crystal layer3in each domain is stabilized by the DCE178and178a-178c.

This embodiment illustrates the liquid crystal layer3having negative dielectric anisotropy and homeotropic alignment with respect to the substrates110and210. However, the liquid crystal layer3may have positive dielectric anisotropy and homogeneous alignment with respect to the substrates110and210.

A TFT array panel according to the third embodiment of the present invention may be manufactured using four photo-etching steps. In this case, a data wire and DCEs have a triple-layered structure including an amorphous silicon layer, an ohmic contact layer and a metal layer, and the triple layers have substantially the same planar shape, which is resulted from the patterning of the amorphous silicon layer, the ohmic contact layer and the metal layer using a photoresist film. Since such a manufacturing method is described in detail in the description about the second embodiment of the present invention, the manufacturing method is understood in view of the fact that the patterns made of the same layer(s) are formed in the same step and thus the detailed description thereof is omitted.

The third embodiment provides three TFTs in each pixel for improve the low voltage difference VDPin case of connecting the source electrode of the DCE TFT to the previous data line, the sensitive change of image quality due to misalignment of the mask during the manufacturing process, the light leakage near the DCE, and so on.

However, the increase of the number of the TFTs in each pixel decreases the aperture ratio and makes it difficult to providing a repairing mechanism for repairing wire defects in the manufacturing process.

The following embodiments suggest driving mechanisms that make two TFTs comparing with three TFTs.

FIG. 18is a circuit diagram of an LCD according to a fourth embodiment of the present invention,FIG. 19illustrates polarity of the pixels of the LCD according to the fourth embodiment of the present invention, andFIG. 20shows waveforms of scanning signals of the LCD according to the fourth embodiment of the present invention.

An LCD according to a fourth embodiment of the present invention also includes a TFT array panel, a color filter array panel opposite the TFT array panel, and a liquid crystal layer interposed therebetween. The TFT array panel is provided with a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixels. The gate lines transmit scanning signals and the data lines transmit image signals. Each pixel is provided with a pixel TFT T1for a pixel electrode and a DCE TFT T2for a DCE. The pixel TFT T1includes a gate electrode connected to a relevant gate line Gn, a source electrode connected to a relevant data line Dm, and a drain electrode connected to a relevant pixel electrode. The DCE TFT T2includes a gate electrode connected to a previous gate line Gn−1, a source electrode connected to a next data line Dm+1, and a drain electrode connected to a relevant DCE. The source electrode of the DCE TFT T2may be connected to a previous data line Dm−1.

The DCE is capacitively coupled with the pixel electrode, and the capacitor therebetween or its capacitance is represented by Cdp. The pixel electrode and a common electrode provided on the color filter array panel form a liquid crystal capacitor, and the liquid crystal capacitor or its capacitance is represented by Clc. The pixel electrode and a storage electrode, which is indicated as a ground, form a storage capacitor, and the storage capacitor or its capacitance is represented by Cst. The DCE forms capacitors along with the common electrode and the storage electrode, and the capacitors or their capacitances are represented by Cld and Cdg, respectively.

Although it is not shown in the circuit diagram, the pixel electrode according to this embodiment of the present invention has a cutout overlapping the DCE such that the electric field due to the DCE flows out through the cutout. The electric field flowing out through the cutout makes the liquid crystal molecules tilt along predetermined directions like the previous embodiments.

A dot inversion shown inFIG. 19and dual-pulse gate signals shown inFIG. 20can make the LCD shown inFIG. 18function like the LCD according to the third embodiment.

A dual-pulse gate signal has two consecutive gate-on pulses in a frame, the first pulse for charging the DCE and the second pulse for applying data voltages to the pixel electrode. The first pulse of a gate signal is synchronized with the second pulse of a gate signal for a previous gate line.

The charging of the LCD shown inFIGS. 18-20is described in detail.

Let us assume that a pixel electrode and a DCE of a pixel in the n-th row and the m-th column are charged with −5V and −15V, respectively. Now, the pixel electrode will be refreshed by a voltage +5V.

The voltage Vp of the pixel electrode and the voltage Vdce of the DCE are
Vp=−5V andVdce=−15V.(1)

When the pixels in the (n−2)-th row are refreshed, the gate line Gn−2is supplied with the second pulse, while the gate line Gn−1is supplied with the first pulse. In addition, the data line Dm+1is supplied with −5V under the dot inversion. Then, the DCE TFT T2of the pixel in the n-th row and the m-th column having a gate electrode and a source electrode respectively connected to the gate line Gn−1and the data line Dm+1is turned on to supply a voltage of −5V to the DCE, thereby charging the capacitor Cdp and the capacitors Clc and Cst in series.
Vp>−5VandVdce=−5V.(2)

When the pixels in the (n−1)-th row are refreshed, the gate line Gn−1is supplied with the second pulse, while the gate line Gnis supplied with the first pulse. In addition, the data lines Dm+1, and Dmare supplied with +5V and −5V, respectively, under the dot inversion. Then, both the pixel TFT T1and the DCE TFT T2of the pixel in the n-th row and the m-th column are turned on to supply a voltage of −5V to the pixel electrode and a voltage of +5V to the DCE.
Vp=−5VandVdce=+5V.(3)

When the pixels in the n-th row are refreshed, the gate line Gnis supplied with the second pulse, while the gate line Gn−1is supplied with no pulse. In addition, the data lines Dmare supplied with +5V. Then, only the pixel TFT T1of the pixel in the n-th row and the m-th column are turned on to supply a voltage of +5V to the pixel electrode. If Cld+Cdg<<Cdp, the voltage of the DCE, which is floating to maintain the voltage difference from the pixel electrode, increases along that of the pixel electrode to have a value of +15V.
Vp=+5VandVdce=+15V.(4)

To summarize, the dual-pulse gate signals enables two TFTs to function as three TFTs. That is, it is possible to obtain a sufficiently high voltage difference Vdp regardless of the capacitance Cdp.

The fourth embodiment facilitates the charging of the DCE by providing stepwise charging as well as reducing a TFT. That is, the second charging step (2) that is not obtained in the third embodiment may enable the smooth charging of the DCE.

FIG. 21is a circuit diagram of an LCD according to a fifth embodiment of the present invention, andFIG. 22illustrates polarity of the pixels of the LCD according to the fifth embodiment of the present invention.

An LCD according to a fifth embodiment of the present invention also includes a TFT array panel, a color filter array panel opposite the TFT array panel, and a liquid crystal layer interposed therebetween. The TFT array panel is provided with a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixels.

Each pixel is provided with two TFTs, and the pixels are classified into two kinds depending on the connection of the TFTs.

A first pixel includes a pixel TFT T1ahaving a gate electrode connected to a relevant gate line Gn, a source electrode connected to a relevant data line Dm, and a drain electrode connected to a relevant pixel electrode and a DCE TFT T2ahaving a gate electrode connected to a previous gate line Gn−1, a source electrode connected to a next data line Dm+1, and a drain electrode connected to a relevant DCE.

A second pixel includes a pixel TFT T1bhaving a gate electrode connected to a relevant gate line Gn−1a source electrode connected to a relevant data line Dm, and a drain electrode connected to a relevant pixel electrode and a DCE TFT T2bhaving a gate electrode connected to a previous gate line Gn−1, a source electrode connected to the relevant data line Dm, and a drain electrode connected to a relevant DCE.

The first pixels and the second pixel are alternately arranged along a column direction.

Although it is not shown in the circuit diagram, the pixel electrode according to this embodiment of the present invention has a cutout overlapping the DCE such that the electric field due to the DCE flows out through the cutout. The electric field flowing out through the cutout makes the liquid crystal molecules tilt along predetermined directions like the previous embodiments.

A double-dot inversion shown inFIG. 22and the dual-pulse gate signals shown inFIG. 20can make the LCD shown inFIG. 21function like the LCD according to the fourth embodiment.

In adjacent rows of the first and the second pixels supplied with the data voltages having the same polarity, the first pixels are supplied with the scanning signal prior to the second pixels.

FIG. 23is a circuit diagram of an LCD according to a sixth embodiment of the present invention, andFIG. 24illustrates polarity of the pixels of the LCD according to the sixth embodiment of the present invention.

An LCD according to a sixth embodiment of the present invention also includes a TFT array panel, a color filter array panel opposite the TFT array panel, and a liquid crystal layer interposed therebetween. The TFT array panel is provided with a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixels.

Each pixel is provided with a pixel TFT T1for a pixel electrode and a DCE TFT T2for a DCE. The pixel TFT T1includes a gate electrode connected to a relevant gate line Gn, a source electrode connected to a relevant data line Dm, and a drain electrode connected to a relevant pixel electrode. The DCE TFT T2includes a gate electrode connected to a previous gate line Gn−1, a source electrode connected to the relevant data line Dm+1, and a drain electrode connected to a relevant DCE.

Although it is not shown in the circuit diagram, the pixel electrode according to this embodiment of the present invention has a cutout overlapping the DCE such that the electric field due to the DCE flows out through the cutout. The electric field flowing out through the cutout makes the liquid crystal molecules tilt along predetermined directions like the previous embodiments.

A column inversion shown inFIG. 24and the dual-pulse gate signals shown inFIG. 20can make the LCD shown inFIG. 23function like the LCD according to the fourth embodiment.

The dual-pulse gate signals can be applied to cases that the DCE is supplied with a voltage from a storage electrode line, which will be described hereinafter.

FIG. 25is a circuit diagram of an LCD according to a seventh embodiment of the present invention.

Each pixel of an LCD according to a seventh embodiment of the present invention is provided with a pixel TFT T1for a pixel electrode and a DCE TFT T2for a DCE. The pixel TFT T1includes a gate electrode connected to a relevant gate line Gn, a source electrode connected to a relevant data line Dm, and a drain electrode connected to a relevant pixel electrode. The DCE TFT T2includes a gate electrode connected to a previous gate line Gn−1, a source electrode connected to a common voltage, and a drain electrode connected to a relevant DCE.

This configuration is substantially the same as those according to the first and the second embodiments since the common voltage is transmitted to the TFT array panel by the storage electrode line.

The dual-pulse gate signals shown inFIG. 20can make the LCD shown inFIG. 25function like the LCD according to the fourth to the sixth embodiments. Any of the dot inversion, the double-dot inversion, the column inversion, etc., will have an effect.

The charging of the LCD shown inFIG. 25is described in detail. For descriptive convenience, the inversion type is limited to the dot inversion.

Let us assume that a pixel electrode and a DCE of a pixel in the n-th row and the m-th column are charged with −5V and −15V, respectively. Now, the pixel electrode will be refreshed by a voltage +5V.

The voltage Vp of the pixel electrode and the voltage Vdce of the DCE are
Vp=−5VandVdce=−15V.(5)

When the pixels in the (n−2)-th row are refreshed, the gate line Gn−2is supplied with the second pulse, while the gate line Gn−1, is supplied with the first pulse. Then, the DCE TFT T2of the pixel in the n-th row and the m-th column having a gate electrode connected to the gate line Gn−1is turned on to supply the common voltage of 0V (for convenience) to the DCE, thereby charging the capacitor Cdp and the capacitors Clc and Cst in series.
Vp>−5VandVdce=0V.(6)

When the pixels in the (n−1)-th row are refreshed, the gate line Gn−1is supplied with the second pulse, while the gate line Gnis supplied with the first pulse. In addition, the data line Dmis supplied with −5V under the dot inversion. Then, both the pixel TFT T1and the DCE TFT T2of the pixel in the n-th row and the m-th column are turned on to supply a voltage of −5V to the pixel electrode and the common voltage of 0V to the DCE.
Vp=−5VandVdce=0V.(7)

When the pixels in the n-th row are refreshed, the gate line Gnis supplied with the second pulse, while the gate line Gn−1is supplied with no pulse. In addition, the data lines Dmare supplied with +5V. Then, only the pixel TFT T1of the pixel in the n-th row and the m-th column are turned on to supply a voltage of +5V to the pixel electrode. The voltage of the DCE, which is floating to maintain the voltage difference from the pixel electrode, increases along that of the pixel electrode to have a value of +10V.
Vp=+5VandVdce=+10V.(8)

To summarize, the dual-pulse gate signals enables to obtain a sufficiently high voltage difference Vdp regardless of the capacitance Cdp when the DCE is supplied with the common voltage through the storage electrode line.

As described above, a DCE TFT switching the signals transmitted to a DCE and a pixel electrode to generate initial direction-control voltage, thereby ensuring stable brightness.