Dynamic gate-overdrive voltage boost receiver

In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.

BACKGROUND

Field

Aspects of the present disclosure relate generally to receivers, and more particularly, to receivers with gate-overdrive voltage boosting.

Background

A chip may include a receiver to receive an input signal from an off-chip device via a link. In some cases, the voltage swing of the input signal exceeds a voltage rating of transistors in the receiver. This can damage the transistors in the receiver. To prevent overvoltage damage to the transistors, split receivers have been developed. A split receiver may include a first receiver and a second receiver. To prevent overvoltage damage, the split receiver splits the voltage swing of the input signal between the first receiver and the second receiver, which reduces the voltage stress on the transistors in each of the first receiver and the second receiver.

SUMMARY

A first aspect relates to a receiving circuit. The receiving circuit includes a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output. The receiving circuit also includes a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter, and a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter. The receiving circuit further includes a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver.

A second aspect relates to a receiving circuit. The receiving circuit includes a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output. The receiving circuit also includes a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter, and a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter. The receiving circuit also includes a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver. The receiving circuit further includes a second boost circuit having a first input, a second input, and an output, wherein the first input of the second boost circuit is coupled to the input of the first receiver, the second input of the second boost circuit is coupled to the input of the second receiver, and the output of the second boost circuit is coupled to a supply terminal of the first receiver.

A third aspect relates to a method of receiving an input signal. The method includes splitting the input signal into a first signal and a second signal, inputting the first signal to a first receiver, inputting the second signal to a second receiver, and shifting a supply voltage of the second receiver based on the first signal and the second signal.

DETAILED DESCRIPTION

A chip may include a receiver to receive an input signal from an off-chip device via a link. The input of the receiver may be coupled to the link via an input/output (I/O) pad on the chip. In some cases, the voltage swing (e.g., 1.8V) of the input signal exceeds a voltage rating (e.g., 1.2V) of transistors in the receiver. The voltage rating of a transistor is a maximum voltage that the transistor is designed to tolerate between two terminals (e.g., gate-to-source). A transistor may be damaged (e.g., suffer a gate-oxide breakdown) when a voltage across the transistor exceeds the voltage rating of the transistor. As used herein, a “voltage swing” of a signal is the difference between the maximum voltage of the signal and the minimum voltage of the signal.

In certain aspects, a receiver may include transistors having a voltage rating below the voltage swing of an input signal received by the receiver. To prevent the input signal from damaging the transistors, split receiver designs have been developed. In this regard,FIG.1shows an example of a split receiver110configured to receive a high-voltage input signal without damaging the transistors in the split receiver110.

In the example inFIG.1, the split receiver110includes a splitter120, a first receiver130, a second receiver150, and a logic decision circuit170. The splitter120has an input122, a first output124, and a second output126. The input122of the splitter120is coupled to an I/O pad112to receive the input signal (labeled “PADSIG”). The input signal may be transmitted from an off-chip device (not shown) coupled to the I/O pad112via a link (not shown).

The splitter120is configured to split the input signal into a first signal (labeled “SIG_LV”) and a second signal (labeled “SIG_HV”). The first signal is output at the first output124and the second signal is output at the second output126. In certain aspects, the input signal has a first voltage swing (e.g., 1.8 V), the first signal has a second voltage swing (e.g., 0.9 V), and the second signal has a third voltage swing (e.g., 0.9 V), in which each one of the second voltage swing and the third voltage swing is less than the first voltage swing. Thus, in this example, the splitter120splits the voltage swing of the input signal between the first signal and the second signal. As discussed further below, the lower voltage swings of the first signal and the second signal provide overvoltage protection for transistors in the first receiver130and the second receiver150.

FIG.2shows exemplary voltage waveforms for the input signal (labeled “PADSIG”), the first signal (labeled “SIG_LV”) and the second signal (labeled “SIG_HV”). In this example, the input signal has a voltage swing of 1.8 V, the first signal has a voltage between 0 V to 0.9 V, and the second signal has a voltage between 0.9 V to 1.8 V. However, it is to be appreciated that the present disclosure is not limited to this example.

As shown in the example inFIG.2, the first signal includes the portion of the input signal between 0 V and 0.9 V, and the second signal includes the portion of the input signal between 0.9 V and 1.8 V. Also, the voltage of the first signal is 0.9 V when the voltage of the input signal is above 0.9 V, and the voltage of the second signal is 0.9 V when the voltage of the input signal is below 0.9 V. In other words, the first signal chops off the portion of the input signal above 0.9 V, and the second signal chops off the portion of the input signal below 0.9 V. In this example, the voltage swing of the first signal is 0.9 V and the voltage swing of the second signal is 0.9 V (i.e., 1.8 V-0.9 V). Assuming the voltage rating (e.g., 1.2 V) of transistors in the split receiver110is above 0.9 V, the voltage swing of each one of the first signal and the second signal is below the voltage rating of the transistors in the split receiver110, which protects the transistors from overvoltage damage. As also shown inFIG.2, the voltage of the second signal SIG_HV is higher than the voltage of the first signal SIG_LV.

Returning toFIG.1, the first receiver130has an input132and an output134. The input132of the first receiver130is coupled to the first output124of the splitter120to receive the first signal SIG_LV. In this example, the first receiver130includes an inverter including a first transistor142and a second transistor144. In the example inFIG.1, the first transistor142is implemented with a p-type field effect transistor (PFET) and the second transistor144is implemented with an n-type field effect transistor (NFET). The inverter is coupled between an upper rail136and a lower rail138. The lower rail138provides a supply voltage vssx and the upper rail136provides a supply voltage vddix. In one example, the supply voltage vssx is 0 V (e.g., the lower rail138is coupled to ground) and the supply voltage vddix is 0.9 V. Thus, in this example, the output134of the first receiver130swings between 0 V and 0.9 V.

The second receiver150has an input152and an output154. The input152of the second receiver150is coupled to the second output126of the splitter120to receive the second signal SIG_HV. In this example, the second receiver150includes an inverter including a first transistor162and a second transistor164. In the example inFIG.1, the first transistor162is implemented with an NFET and the second transistor164is implemented with a PFET. The inverter is coupled between an upper rail156and a lower rail158. The lower rail158provides a supply voltage vssix and the upper rail156provides a supply voltage vddpx. In one example, the supply voltage vssix is 0.9 V and the supply voltage vddpx is 1.8 V. Thus, in this example, the output154of the second receiver150swings between 0.9 V and 1.8 V. In certain aspects, the supply voltages vssix and vddix are approximately equal (e.g., 0.9 V).

The logic decision circuit170has a first input172, a second input174, and an output176. The first input172of the logic decision circuit170is coupled to the output134of the first receiver130, the second input174of the logic decision circuit170is coupled to the output154of the second receiver150, and the output176of the logic decision circuit170provides the output (labeled “RX_OUT”) of the split receiver110. In certain aspects, the logic decision circuit170is configured to output a logic one or logic zero based on both the output134of the first receiver130and the output154of the second receiver150.

In certain aspects, the logic decision circuit170is configured to output a first logic value when the output134of the first receiver130and the output154of the second receiver150are both low. In the example discussed above, the first receiver130has a low output voltage of 0 V and the second receiver150has a low output voltage of 0.9 V. The logic decision circuit170is configured to output a second logic value when the output134of the first receiver130and the output154of the second receiver150are both high. In the example discussed above, the first receiver130has a high output voltage of 0.9 V and the second receiver150has a high output voltage of 1.8 V. The first logic value may be zero and the second logic value may be one, or vice versa. In certain aspects, the output176of the logic decision circuit170may have a low voltage of vssx (e.g., 0 V) and a high voltage of vddix (e.g., 0.9 V). However, it is to be appreciated that the logic decision circuit170is not limited to this example. For example, in other aspects, the output176of the logic decision circuit170may have a low voltage of vssix (e.g., 0.9 V) and a high voltage of vddpx (e.g., 1.8 V). It is also to be appreciated that the logic decision circuit170may be coupled to the outputs134and154of the first receiver130and the second receiver150via one or more additional components (e.g., one or more buffers, one or more voltage-level shifters, etc.) not shown inFIG.1.

Exemplary operations of the split receiver110will now be described according to certain aspects. When the input signal transitions from low to high210(e.g., transitions from 0 V to 1.8 V), the output134of the first receiver130switches from high to low since the first receiver130includes an inverter in this example. The output154of the second receiver150then switches from high to low when the voltage of the input signal reaches an input high voltage (VIH), an example of which is shown inFIG.2. In this example, the VIH is the input voltage at which the output154of the second receiver150switches from high to low, which causes the logic decision circuit170to switch to the first logic value discussed above. The VIH may also be referred to as a switch voltage or switch point since the VIH is the input voltage at which the output154of the second receiver150switches logic states.

In the example inFIG.1, the VIH is equal to the sum of the supply voltage vssix (e.g., 0.9 V) and the threshold voltage of the first transistor162. This is because the first transistor162turns on when the input voltage is equal to the sum of the supply voltage vssix and the threshold voltage of the first transistor162. The turning on of the first transistor162switches the output154of the second receiver150low. In this example, the low output voltage of the second receiver150is vssix (e.g., 0.9 V).

The threshold voltage of the first transistor162may vary due to process, voltage, and temperature (PVT) variations with a worst-case threshold voltage of vthn_worst. In this example, the worst-case VIH of the split receiver110is equal to vssix+vthn_worst. A problem with this is that the worst-case VIH may exceed a maximum allowable VIH specified by a standard (e.g., a JEDEC standard), which makes the split receiver110unsuitable for a system intended to comply with the standard. For example, for a worst-case threshold voltage of 0.4 V, the worst-case VIH may be 1.3 V (i.e., 0.9 V+0.4 V), which exceeds a maximum allowable VIH of 1.17 V specified by a JEDEC standard for an input voltage swing of 1.8 V. A similar non-compliance issue may also arise when the input signal transitions from high to low220(e.g., from 1.8 V to 0 V), as discussed further below.

When the input signal transitions from high to low220, the output154of the second receiver150switches from low to high since the second receiver150includes an inverter in this example. The output134of the first receiver130then switches from low to high when the voltage of the input signal falls to an input low voltage (VIL), an example of which is shown inFIG.2. In this example, the VIL is the input voltage at which the output134of the first receiver130switches from low to high, which causes the logic decision circuit170to switch to the second logic value discussed above.

In the example inFIG.1, the VIL is equal to the supply voltage vddix (e.g., 0.9 V) minus the threshold voltage of the first transistor142. This is because the first transistor142turns on when the input voltage is equal to the supply voltage vddix minus the threshold voltage of the first transistor142. The turning on of the first transistor142switches the output134of the first receiver130high. In this example, the high output voltage of the first receiver130is vddix (e.g., 0.9 V).

The threshold voltage of the first transistor142may vary due to process, voltage, and temperature (PVT) variations with a worst-case threshold voltage of Vthp_worst. In this example, the worst-case VIL of the split receiver110is equal to vddix−Vthp_worst. A problem with this is that the worst-case VIL may be below a minimum allowable VIL specified by a standard (e.g., a JEDEC standard), which makes the split receiver110unsuitable for a system intended to comply with the standard. For example, for a worst-case threshold voltage of 0.4 V, the worst-case VIL may be 0.5 V (i.e., 0.9 V-0.4 V), which is below a minimum allowable VIL of 0.63 V specified by a JEDEC standard for an input voltage swing of 1.8 V.

Thus, the split receiver110illustrated inFIG.1prevents overvoltage damage to the transistors (e.g., the transistors142,144,162, and164) in the split receiver110by splitting the voltage swing of the input signal between the first receiver130and the second receiver150. However, the split receiver110may violate the maximum allowable VIH and/or the minimum allowable VIL specified by a standard (e.g., JEDEC standard), which makes the split receiver110unsuitable for a system intended to comply with the standard.

To address this, aspects of the present disclosure provide a split receiver with dynamic gate-overdrive voltage boosting to dynamically shift the VIH and/or the VIL (e.g., to comply with a standard). In certain aspects, a gate-overdrive voltage of a transistor in the second receiver150is temporarily boosted (i.e., increased) when the input signal transitions from low to high. The gate-overdrive voltage boost lowers the VIH during the transition such that the VIH is below the maximum allowable VIH specified by a standard, and therefore complies with the standard. In certain aspects, the gate-overdrive voltage boosting of the transistor in the second receiver150is controlled using the first signal (“SIG_LV) and the second signal (“SIG_HV), which allows the split receiver to operate at a higher frequency and lower power consumption compared with using the output of the logic decision circuit170to control the gate-overdrive voltage boosting, as discussed further below. Since the gate-overdrive voltage boosting is not controlled using feedback from the output of the logic decision circuit170, the potential instability and/or oscillations caused by a feedback loop is eliminated.

In certain aspects, a gate-overdrive voltage of a transistor in the first receiver130is temporarily boosted (i.e., increased) when the input signal transitions from high to low. The gate-overdrive voltage boost increases the VIL during the transition such that the VIL is above the minimum allowable VIL specified by a standard, and therefore complies with the standard. In certain aspects, the gate-overdrive voltage boosting of the transistor in the first receiver130is controlled using the first signal SIG_LV and the second signal SIG_HV, which allows the split receiver to operate at a higher frequency and lower power consumption compared with using the output of the logic decision circuit170to control the gate-overdrive voltage boosting, as discussed further below. Since the gate-overdrive voltage boosting is not controlled using feedback from the output of the logic decision circuit170, the potential instability and/or oscillations caused by a feedback loop is eliminated. The above aspects and other aspects of the present disclosure are discussed in further detail below.

FIG.3shows an exemplary split receiver305with gate-overdrive boosting according to certain aspects of the present disclosure. The split receiver305includes the splitter120, the first receiver130, the second receiver150, and the logic decision circuit170discussed above. For brevity, a description of the splitter120, the first receiver130, the second receiver150, and the logic decision circuit170is not repeated here. The split receiver305also includes a first boost circuit310and a second boost circuit320.

The first boost circuit310has a first input312, a second input314, and an output316. The first input312is coupled to the input132of the first receiver130, and the second input314is coupled to the input152of the second receiver150. Thus, the first input312receives the first signal SIG_LV and the second input314receives the second signal SIG_HV. The output316is coupled to a supply terminal318of the second receiver150. In the example inFIG.3, the supply terminal318is coupled to the source of the first transistor162in the second receiver150. As discussed further below, the output316of the first boost circuit310provides the supply voltage vss_out to the supply terminal318of the second receiver150. Thus, in this example, the source of the first transistor162is coupled to the output316of the first boost circuit310instead of the lower rail158shown inFIG.1.

In certain aspects, the first boost circuit310is configured to boost (i.e., increase) a gate-overdrive voltage of the first transistor162in the second receiver150based on the first signal SIG_LV and the second signal SIG_HV when the input signal transitions from low to high. In these aspects, the gate-overdrive voltage of the first transistor162corresponds to the gate-to-source voltage of the first transistor162. The larger the gate-to-source voltage of the first transistor162, the larger the gate-overdrive voltage.

In certain aspects, the first boost circuit310boosts the gate-overdrive voltage of the first transistor162in the second receiver150by shifting (i.e., changing or modifying) the supply voltage vss_out. In one example, the first boost circuit310may be configured to set the supply voltage vss_out to a voltage of vssix (e.g., 0.9 V) when the gate-overdrive voltage is not boosted, and shift the supply voltage vss_out lower to a voltage of vssix—Δvss to boost the gate-overdrive voltage (i.e., lower the supply voltage vss_out by Δvss). By shifting the supply voltage vss_out lower, the first boost circuit310lowers the source voltage of the first transistor162, which increases (i.e., boosts) the gate-overdrive voltage of the first transistor162in the second receiver150. The gate-overdrive voltage boost shifts the VIH lower, which helps the VIH meet the maximum allowable VIH specified by a standard.

Exemplary operations of the first boost circuit310will now be described according to certain aspects with reference toFIG.4.FIG.4shows an example of the input voltage (labeled “PADSIG”), the first signal SIG_LV, the second signal SIG_HV, and the supply voltage vss_out.FIG.4shows an example of a transition410of the input signal from low to high. In the example inFIG.4, the input signal has a low voltage of vssx (e.g., 0 V) and a high voltage of vddpx (e.g., 1.8 V). The transition410of the input signal from low to high causes the first signal SIG_LV to transition from low to high, and the second signal SIG_HV to transition from low to high. In the example inFIG.4, the first signal SIG_LV has a low voltage of vssx (e.g., 0 V) and a high voltage of vddix (e.g., 0.9 V), and the second signal SIG_HV has a low voltage of vssix (e.g., 0.9 V) and a high voltage of vddpx (e.g., 1.8 V).

During the transition of the input signal from low to high, the first boost circuit310monitors the voltage of the first signal SIG_LV and the voltage of the second signal SIG_HV. When the voltage of the first signal SIG_LV crosses a first voltage threshold (labeled “Th_start_VIH”), the first boost circuit310starts boosting the gate-overdrive of the first transistor162in the second receiver150. As shown inFIG.4, the first boost circuit310starts the gate-overdrive boost by shifting (i.e., changing or modifying) the supply voltage vss_out lower by Δvss. This shifts the VIII lower by Δvss, which helps the VIH meet the maximum allowable VIH (labeled “VIH_max”) specified by a standard.

When the voltage of the second signal SIG_HV crosses a second voltage threshold (labeled “Th_end_VIH”), the first boost circuit310ends (i.e., stops) boosting the gate-overdrive voltage of the first transistor162in the second receiver150. As shown inFIG.4, the first boost circuit310ends the gate-overdrive boost by returning the supply voltage vss_out to vssix.

In certain aspects, the first threshold Th_start_VIH is set to a voltage below the maximum allowable VIH, and the second threshold Th_end_VIH is set to a voltage above the VIH without gate-overdrive boosting (i.e., unshifted VIH). This helps ensure that the first boost circuit310boosts the gate-overdrive voltage when needed to lower the VIH to meet the maximum allowable VIH.

The first boost circuit310controls the gate-overdrive voltage boosting of the first transistor162in the second receiver150based on the first signal SIG_LV (which is input to the first receiver130) and the second signal SIG_HV (which is input to the second receiver150). Thus, the first boost circuit310controls the gate-overdrive voltage boosting based on the input signals (i.e., the first signal SIG_LV and second signal SIG_HV) to the first receiver130and the second receiver150. This allows the first boost circuit310to control the gate-overdrive voltage boost more quickly in response to changes in the voltages of the input signals to the first receiver130and the second receiver150compared with using the output134of the first receiver130and/or the output176of the logic decision circuit170to control the gate-overdrive voltage boost. The faster gate-overdrive voltage control allows the split receiver305to operate at faster operating frequencies (e.g., for higher data rates). In addition, using the input signals to the first receiver130and the second receiver150to control the gate-overdrive voltage boost instead of the output176of the logic decision circuit170helps avoid potential feedback stability and/or oscillation issues that may arise when feeding back the output of the logic decision circuit170to the first boost circuit310. Also, the DC current drawn by the first boost circuit310may be reduced since the first boost circuit310provides complete control over the amount of time that the gate-overdrive voltage is boosted by setting the first threshold Th_start_VIH and the second threshold Th_end_VIH accordingly.

The second boost circuit320has a first input322, a second input324, and an output326. The first input322is coupled to the input132of the first receiver130, and the second input324is coupled to the input152of the second receiver150. Thus, the first input322receives the first signal SIG_LV and the second input324receives the second signal SIG_HV. The output326is coupled to a supply terminal328of the first receiver130. In the example inFIG.3, the supply terminal328is coupled to the source of the first transistor142in the first receiver130. As discussed further below, the output326of the second boost circuit320provides the supply voltage vdd_out to the supply terminal328of the first receiver130. Thus, in this example, the source of the first transistor142is coupled to the output326of the second boost circuit320instead of the upper rail136shown inFIG.1.

In certain aspects, the second boost circuit320is configured to boost (i.e., increase) a gate-overdrive voltage of the first transistor142in the first receiver130based on the first signal SIG_LV and the second signal SIG_HV when the input signal transitions from high to low. In these aspects, the gate-overdrive voltage of the first transistor142corresponds to the source-to-gate voltage of the first transistor142. The larger the source-to-gate voltage of the first transistor142, the larger the gate-overdrive voltage.

In certain aspects, the second boost circuit320boosts the gate-overdrive voltage of the first transistor142by shifting (i.e., changing or modifying) the supply voltage vdd_out. In one example, the second boost circuit320may be configured to set the supply voltage vdd_out to a voltage of vddix (e.g., 0.9 V) when the gate-overdrive voltage is not boosted, and shift the supply voltage vdd_out higher to a voltage of vddix+Δvdd to boost the gate-overdrive voltage (i.e., raise the supply voltage vdd_out by Δvdd). By shifting the supply voltage vdd_out higher, the second boost circuit320raises the source voltage of the first transistor142, which increases (i.e., boosts) the gate-overdrive voltage of the first transistor142. The gate-overdrive voltage boost shifts the VIL higher, which helps the VIL meet the minimum allowable VIL specified by a standard.

Exemplary operations of the second boost circuit320will now be described according to certain aspects with reference toFIG.4.FIG.4shows an example of a transition420of the input signal from high to low. The transition420of the input signal from high to low causes the second signal SIG_HV to transition from high to low, and the first signal SIG_LV to transition from high to low.

During the transition of the input signal from high to low, the second boost circuit320monitors the voltage of the first signal SIG_LV and the voltage of the second signal SIG_HV. When the voltage of the second signal SIG_HV crosses a first voltage threshold (labeled “Th_start_VIL”), the second boost circuit320starts boosting the gate-overdrive of the first transistor142in the first receiver130. As shown inFIG.4, the second boost circuit320starts the gate-overdrive boost by shifting (i.e., changing or modifying) the supply voltage vdd_out higher by Δvdd. This shifts the VIL high by Δvdd, which helps the VIL meet the minimum allowable VIL (labeled “VIL_min”) specified by a standard.

When the voltage of the first signal SIG_LV crosses a second voltage threshold (labeled “Th_end_VIL”), the second boost circuit320ends (i.e., stops) boosting the gate-overdrive voltage of the first transistor142in the first receiver130. As shown inFIG.4, the second boost circuit320ends the gate-overdrive boost by returning the supply voltage vdd_out to vddix.

In certain aspects, the first threshold Th_start_VIL is set to a voltage above the minimum allowable VIL, and the second threshold Th_end_VIL is set to a voltage below the VIL without gate-overdrive boosting (i.e., unshifted VIL). This helps ensure that the second boost circuit320boosts the gate-overdrive voltage when needed to raise the VIL to meet the minimum allowable VIL.

The second boost circuit320controls the gate-overdrive voltage boosting of the first transistor142in the first receiver130based on the first signal SIG_LV (which is input to the first receiver130) and the second signal SIG_HV (which is input to the second receiver150). Thus, the second boost circuit320controls the gate-overdrive voltage boosting based on the input signals (i.e., the first signal SIG_LV and second signal SIG_HV) to the first receiver130and the second receiver150. This allows the second boost circuit320to control the gate-overdrive voltage quickly in response to changes in the voltages of the input signals to the first receiver130and the second receiver150, allowing the split receiver305to operate at faster operating frequencies (e.g., for higher data rates).

FIG.5shows an exemplary implementation of the first boost circuit310according to certain aspects. In this example, the first boost circuit310includes a first control circuit510and a first voltage circuit520. The first control circuit510has a first input512, a second input514, and an output516. The first input512of the first control circuit510is coupled to the first input312to receive the first signal SIG_LV, and the second input514of the first control circuit510is coupled to the second input314to receive the second signal SIG_HV.

The first voltage circuit520has a control input522coupled to the output516of the first control circuit510, and an output524coupled to the supply terminal318of the second receiver150. The first voltage circuit520is configured to output the supply voltage vss_out at the output524. In certain aspects, the first voltage circuit520is configured to receive a shift-control signal from the first control circuit510at the control input522. When the shift-control signal is disabled, the first voltage circuit520is configured to set the supply voltage vss_out to the voltage vssix (e.g., 0.9 V). When the shift-control circuit is enabled, the first voltage circuit520is configured to shift the supply voltage vss_out lower by a voltage shift of Δvss. In this case, the supply voltage vss_out is equal to vssix−Δvss. As discussed above, shifting the supply voltage vss_out lower boosts the gate-overdrive voltage of the first transistor162in the second receiver150.

In one example, the shift-control signal may have a first logic value when disabled and a second logic value when enabled. The first logic value may be zero and the second logic value may be one, or vice versa. In this example, the first voltage circuit520is configured to set the supply voltage vss_out to vssix when the shift-control has the first logic value, and to shift the supply voltage vss_out lower by Δvss when the shift-control signal has the second logic value. However, it is to be appreciated that the present disclosure is not limited to this example.

When the input signal transitions from low to high, the first control circuit510may cause the first voltage circuit520to shift the supply voltage vss_out lower by Δvss (e.g., enable the shift-control signal) between the time that the first signal SIG_LV crosses the first threshold Th_start_VIH and the time that the second signal SIG_HV crosses the second threshold Th_end_VIH. In this example, the first control circuit510starts the gate-overdrive boost (e.g., enables the shift-control signal) when the first signal SIG_LV crosses the first threshold Th_start_VIH and ends the gate-overdrive boost (e.g., disables the shift-control signal) when the second signal SIG_HV crosses the second threshold Th_end_VIH. The first control circuit510may cause the first voltage circuit520to set the supply voltage vss_out to vssix (e.g., disable the shift-control signal) before the first signal SIG_LV reaches the first threshold Th_start_VIH and after the second signal SIG_HV rises above the second threshold TH_end_VIH during a transition of the input signal from low to high. The first control circuit510may cause the first voltage circuit520to set the supply voltage vss_out to vssix (e.g., disable the shift-control signal) when the input signal is not transitioning or when the input signal transitions from high to low.

FIG.6shows an exemplary implementation of the first voltage circuit520according to certain aspects. In this example, the first voltage circuit520includes a first transistor610, a second transistor620, a third transistor630, and a resistor640. In the example inFIG.6, the first transistor610is implemented with a PFET and each of the second transistor620and the third transistor630is implemented with a respective NFET. The source of the first transistor610is coupled to the output524, the gate of the first transistor610is coupled to the output516of the first control circuit510, and the drain of the first transistor610is coupled to the voltage vssix (e.g., 0.9 V). The source of the second transistor620is coupled to the voltage vssx (e.g., 0 V), and the gate of the second transistor620is coupled to the output516of the first control circuit510. The drain of the third transistor630is coupled to the voltage vddpx (e.g., 1.8 V), and the gate of the third transistor630is biased by the voltage vssix. The resistor640is coupled between the source of the third transistor630and the drain of the second transistor620. Also, the output524is coupled to a node635located between the source of the third transistor630and the resistor640.

In this example, the first control circuit510sets the supply voltage vss_out to vssix by turning on the first transistor610and turning off the second transistor620. For example, the first control circuit510may set the shift-control signal low (e.g., vssx) to turn on the first transistor610since the first transistor610is implemented with a PFET in this example. In this example, the first control circuit510outputs a logic zero to disable the shift-control signal (e.g., the first logic value discussed above is zero). In this case, the first transistor610couples the output524of the first voltage circuit520to the voltage vssix through the first transistor610.

The first control circuit510causes the first voltage circuit520to shift the supply voltage vss_out lower by turning on the second transistor620and turning off the first transistor610. For example, the first control circuit510may set the shift-control signal high (e.g., vddpx) to turn on the second transistor620since the second transistor620is implemented with a NFET in this example. In this example, the first control circuit510outputs a logic one to enable the shift-control signal (e.g., the second logic value discussed above is one). When the second transistor620is turned on, the second transistor620pulls the supply voltage vss_out below the voltage vssix through the resistor640, which shifts the supply voltage vss_out lower. The voltage shift Δvss depends on the voltage drop across the resistor640, which, in turn, depends on the resistance of the resistor640. Thus, the voltage shift Δvss may be set to a desired value, for example, by choosing the resistance of the resistor640accordingly.

FIG.7shows an exemplary implementation of the first control circuit510according to certain aspects of the present disclosure. In this example, the first control circuit510includes first inverting logic710, second inverting logic730, non-inverting logic720, a logic circuit740, and a NOR gate750.

The first inverting logic710has an input712and an output714. The input712is coupled to the first input512of the first control circuit510, and therefore receives the first signal SIG_LV. The first inverting logic710is coupled between supply voltages vddix and vssx. Thus, the output714swings between vssx and vddix with a low voltage of vssx and a high voltage of vddix. The first inverting logic710may be implemented with an inverter. In operation, the first inverting logic710is configured to switch the output714from high to low when the voltage of the first signal SIG_LV at the input712rises above a trigger voltage of the first inverting logic710. For the example where the first inverting logic710is implemented with a complementary inverter including a PFET and an NFET, the trigger voltage may be set, for example, by setting a P/N ratio of the first inverting logic710, in which P is the channel width of the PFET and N is the channel width of the NFET.

The second inverting logic730has an input732and an output734. The input732is coupled to the first input512of the first control circuit510, and therefore receives the first signal SIG_LV. The second inverting logic730is coupled between supply voltages vddix and vssx. Thus, the output734swings between vssx and vddix with a low voltage of vssx and a high voltage of vddix. The second inverting logic730may be implemented with an inverter (e.g., a complementary inverter including a PFET and an NFET). In operation, the second inverting logic730is configured to switch the output734from high to low when the voltage of the first signal SIG_LV at the input732rises above a trigger voltage of the second inverting logic730. In certain aspects, the first inverting logic710and the second inverting logic730may have the same or substantially the same structure and/or approximately the same trigger voltage.

The non-inverting logic720has an input722and an output724. The input722is coupled to the second input514of the first control circuit510, and therefore receives the second signal SIG_HV. The non-inverting logic720is coupled between supply voltages vddpx and vssix. Thus, the output724swings between vssix and vddpx with a low voltage of vssix and a high voltage of vddpx. In operation, the non-inverting logic720is configured to switch the output724from low to high when the voltage of the second signal SIG_LV at the input722rises above a trigger voltage of the non-inverting logic720.

The logic circuit740has a first input742, a second input744, and an output746. The first input742is coupled to the output714of the first inverting logic710, and the second input744is coupled to the output724of the non-inverting logic720. In this example, the first input742swings between vssx and vddix since the output714of the first inverting logic710swings between vssx and vddix, and the second input744swings between vssix and vddpx since the output724of the non-inverting logic720swings between vssix and vddpx. The output746of the logic circuit740swings between vssx and vddix. The logic circuit740is configured to perform logic operations to generate one of the input signals for the NOR gate750, as discussed further below. The logic circuit740may also perform voltage-level shifting to shift the voltage from the output724of the non-inverting logic720from between vssix and vddpx to between vssx and vddix.

The NOR gate750has a first input752, a second input754, and an output756. The first input752is coupled to the output746of the logic circuit740, and the second input754is coupled to the output734of the second inverting logic730. The output756is coupled to the output516of the first control circuit510, and hence provides the shift-control signal of the first control circuit510. The NOR gate750is coupled between the supply voltages vssx and vddix, and hence the output756of the NOR gate750swings between vssx and vddix with a low voltage of vssx and a high voltage of vddix. In the example inFIG.7, the output756of the NOR gate750is coupled to the gates of the first transistor610and the second transistor620of the first voltage circuit520.

When the input signal is low, the output714of the first inverting logic710and the output734of the second inverting logic730are both high, and the output724of the non-inverting logic720is low. The logic circuit740may be configured to make the output746high (i.e., logic one) when the output714of the first inverting logic710is high and the output724of the non-inverting logic720is low. In this case, the output756of the NOR gate750is low, which turns on the first transistor610and turns off the second transistor620.

When the input signal transitions from low to high, the output714of the first inverting logic710transitions from high to low when the first signal SIG_LV crosses the trigger voltage of the first inverting logic710, and the output734of the second inverting logic730transitions from high to low when the first signal SIG_LV crosses the trigger voltage of the second inverting logic730. The logic circuit740may be configured to make the output low (i.e., logic zero) when the output714of the first inverting logic710transitions from high to low and the output724of the non-inverting logic720is low. In this case, both inputs752and754of the NOR gate750become low (i.e., logic zero), which causes the output756of the NOR gate750to transition from low to high. As a result, the NOR gate750turns on the second transistor620and turns off the first transistor610, which starts gate-overdrive boosting of the first transistor162in the second receiver150. Thus, gate-overdrive boosting starts when the first signal SIG_LV crosses the trigger voltages of the first inverting logic710and the second inverting logic730. Assuming the first inverting logic710and the second inverting logic730have approximately the same trigger voltage, the trigger voltage of the first inverting logic710and the second inverting logic730sets the first threshold Th_start_VIH discussed above with reference toFIG.4.

As the voltage of the input signal continues to rise during the transition from low to high, the second signal SIG_HV eventually crosses the trigger voltage of the non-inverting logic720causing the output724of the non-inverting logic720to transition from low to high. The logic circuit740may be configured to make the output746high (i.e., logic one) when the output714of the first inverting logic710is low and the output724of the non-inverting logic720transitions from low to high. In this case, the first input752of the NOR ate750becomes high which causes the output756of the NOR gate750to transition from high to low. As a result, the NOR gate750turns off the second transistor620and turns on the first transistor610, which ends gate-overdrive boosting of the first transistor162in the second receiver150. Thus, gate-overdrive boosting ends when the second signal SIG_LH crosses the trigger voltage of the non-inverting logic720. In this example, the trigger voltage of the non-inverting logic720sets the second threshold Th_end_VIH. Note that the trigger voltage of the non-inverting logic720is between vssix and vddpx in this example since the non-inverting logic720is coupled between vssix and vddpx.

It is to be appreciated that the first control circuit510is not limited to the example shown inFIG.7, and that the first control circuit510may be implemented using various combinations of logic circuits to perform the functions discussed above with reference toFIG.4. In other words,FIG.7shows one example of the many different ways the first control circuit510may be implemented.

FIG.8shows an exemplary implementation of the second boost circuit320according to certain aspects. In this example, the second boost circuit320includes a second control circuit810and a second voltage circuit820. The second control circuit810has a first input812, a second input814, and an output816. The first input812of the second control circuit810is coupled to the first input322to receive the first signal SIG_LV, and the second input814of the second control circuit810is coupled to the second input324to receive the second signal SIG_HV.

The second voltage circuit820has a control input822coupled to the output816of the second control circuit810, and an output824coupled to the supply terminal328of the first receiver130. The second voltage circuit820is configured to output the supply voltage vdd_out at the output824. In certain aspects, the second voltage circuit820is configured to receive a shift-control signal from the second control circuit810at the control input822. When the shift-control signal is disabled, the second voltage circuit820is configured to set the supply voltage vdd_out to the voltage vddix (e.g., 0.9 V). When the shift-control circuit is enabled, the second voltage circuit820is configured to shift the supply voltage vdd_out higher by a voltage shift of Δvdd. In this case, the supply voltage vdd_out is equal to vddix+Δvdd. As discussed above, shifting the supply voltage vdd_out higher boosts the gate-overdrive voltage of the first transistor142in the first receiver130.

In one example, the shift-control signal may have a first logic value when disabled and a second logic value when enabled. The first logic value may be zero and the second logic value may be one, or vice versa. In this example, the second voltage circuit820is configured to set the supply voltage vdd_out to vddix when the shift-control has the first logic value, and to shift the supply voltage vdd_out higher by Δvdd when the shift-control signal has the second logic value. However, it is to be appreciated that the present disclosure is not limited to this example.

When the input signal transitions from high to low, the second control circuit810may cause the second voltage circuit820to shift the supply voltage vdd_out higher by Δvdd (e.g., enable the shift-control signal) between the time that the second signal SIG_HV crosses the first threshold Th_start_VIL and the time that the first signal SIG_LV crosses the second threshold Th_end_VIL. In this example, the second control circuit810starts the gate-overdrive boost (e.g., enables the shift-control signal) when the second signal SIG_HV crosses the first threshold Th_start_VIL and ends the gate-overdrive boost (e.g., disables the shift-control signal) when the first signal SIG_LV crosses the second threshold Th_end_VIL. The second control circuit810may cause the second voltage circuit820to set the supply voltage vdd_out to vddix (e.g., disable the shift-control signal) before the second signal SIG_HV reaches the first threshold Th_start_VIL and after the first signal SIG_LV falls below the second threshold TH_end_VIL during a transition of the input signal from high to low. The second control circuit810may cause the second voltage circuit820to set the supply voltage vdd_out to vddix (e.g., disable the shift-control signal) when the input signal is not transitioning or transitioning from low to high.

FIG.9shows an exemplary implementation of the second voltage circuit820according to certain aspects. In this example, the second voltage circuit820includes a first transistor910, a second transistor920, a third transistor930, and a resistor940. In the example inFIG.9, the first transistor910is implemented with a NFET and each of the second transistor920and the third transistor930is implemented with a respective PFET. The source of the first transistor910is coupled to the output824, the gate of the first transistor910is coupled to the output816of the second control circuit810, and the drain of the first transistor910is coupled to the voltage vddix (e.g., 0.9 V). The source of the second transistor920is coupled to the voltage vddpx (e.g., 1.8 V), and the gate of the second transistor920is coupled to the output816of the second control circuit810. The drain of the third transistor930is coupled to the voltage vssx (e.g., 0 V), and the gate of the third transistor930is biased by the voltage vddix. The resistor940is coupled between the source of the third transistor930and the drain of the second transistor920. Also, the output824is coupled to a node935located between the source of the third transistor930and the resistor940.

In this example, the second control circuit810sets the supply voltage vdd_out to vddix by turning on the first transistor910and turning off the second transistor920. For example, the second control circuit810may set the shift-control signal high (e.g., vddpx) to turn on the first transistor910since the first transistor910is implemented with an NFET in this example. In this case, the first transistor910couples the output824of the second voltage circuit820to the voltage vddix through the first transistor910.

The second control circuit810causes the second voltage circuit820to shift the supply voltage vdd_out higher by turning on the second transistor920and turning off the first transistor910. For example, the second control circuit810may set the shift-control low (e.g., vssix) to turn on the second transistor920since the second transistor920is implemented with a PFET in this example. When the second transistor920is turned on, the second transistor920pulls the supply voltage vdd_out above the voltage vddix through the resistor940, which shifts the supply voltage vdd_out higher. The voltage shift Δvdd depends on the voltage drop across the resistor940, which, in turn, depends on the resistance of the resistor940. Therefore, the voltage shift Δvdd may be set to a desired value, for example, by choosing the resistance of the resistor940accordingly.

One skilled in the art will appreciate that the second control circuit810may be implemented using various combinations of logic circuits configured to perform the functions of the second control circuit810discussed above with reference toFIG.4.

It is to be appreciated that the split receiver305may include more than one logic decision circuit170. In this regard,FIG.10shows an example of a split receiver1010including the splitter120, the first receiver130, the second receiver150, the first boost circuit310, and the second boost circuit320discussed above. The split receiver1010also includes a first logic decision circuit1020and a second logic decision circuit1030. In certain aspects, the first logic decision circuit1020and the second logic decision circuit1030output logic values in different voltage domains to subsequent circuits (not shown).

The first logic decision circuit1020has a first input1022, a second input1024, and an output1026. The first input1022of the first logic decision circuit1020is coupled to the output134of the first receiver130, the second input1024of the first logic decision circuit1020is coupled to the output154of the second receiver150, and the output1026of the first logic decision circuit1020provides a first output (labeled “RX_OUT_LV”) of the split receiver1010. In certain aspects, the first logic decision circuit1020is configured to output a logic one or logic zero based on both the output134of the first receiver130and the output154of the second receiver150.

In certain aspects, the first logic decision circuit1020is configured to output a first logic value when the output134of the first receiver130and the output154of the second receiver150are both low, and output a second logic value when the output134of the first receiver130and the output154of the second receiver150are both high. The first logic value may be zero and the second logic value may be one, or vice versa. In certain aspects, the output1026of the first logic decision circuit1020may have a low voltage of vssx (e.g., 0 V) and a high voltage of vddix (e.g., 0.9 V). However, it is to be appreciated that present disclosure is not limited to this example.

The second logic decision circuit1030has a first input1032, a second input1034, and an output1036. The first input1032of the second logic decision circuit1030is coupled to the output134of the first receiver130, the second input1034of the second logic decision circuit1030is coupled to the output154of the second receiver150, and the output1036of the second logic decision circuit1030provides a second output (labeled “RX_OUT_HV”) of the split receiver1010. In certain aspects, the second logic decision circuit1030is configured to output a logic one or logic zero based on both the output134of the first receiver130and the output154of the second receiver150.

In certain aspects, the second logic decision circuit1030is configured to output a first logic value when the output134of the first receiver130and the output154of the second receiver150are both low, and output a second logic value when the output134of the first receiver130and the output154of the second receiver150are both high. The first logic value may be zero and the second logic value may be one, or vice versa. In certain aspects, the output1036of the second logic decision circuit1030may have a low voltage of vssix (e.g., 0.9 V) and a high voltage of vddpx (e.g., 1.8 V). However, it is to be appreciated that present disclosure is not limited to this example.

Thus, in this example, the first logic decision circuit1020and the second logic decision circuit1030may output signals in different voltage domains, in which the output1026of the first logic decision circuit1020swings between vssx and vddix in a first voltage domain, and the output1036of the second logic decision circuit1030swings between vssix and vddpx in a second voltage domain. This may be done, for example, when the system including the split receiver1010includes circuits operating in the first voltage domain and circuits operating in the second voltage domain. In this example, the circuits operating in the first voltage domain may be coupled to the output1026of the first logic decision circuit1020, and the circuits operating in the second voltage domain may be coupled to the output1036of the second logic decision circuit1030.

It is to be appreciated that, in some implementations, one of the first boost circuit310and the second boost circuit320may be omitted from the split receiver305or1010. For example, for cases in which meeting a minimum allowable VIL is not an issue, the split receiver305or1010may include the first boost circuit310with the second boost circuit320omitted. For cases in which meeting a maximum allowable VIH is not an issue, the split receiver305or1010may include the second boost circuit320with the first boost circuit310omitted.

FIG.11illustrates a method1100of receiving an input signal according to certain aspects.

At block1110, the input signal is split into a first signal and a second signal. For example, the input signal may be split into the first signal (e.g., SIG_LV) and the second signal (e.g., SIG_HV) by the splitter120. In certain aspects, the input signal has a first voltage swing (e.g., 1.8 V), the first signal has a second voltage swing (e.g., 0.9 V), the second signal has a third voltage swing (e.g., 0.9 V), and each one of the second voltage swing and the third voltage swing is less than the first voltage swing.

At block1120, the first signal in input to a first receiver. For example, the first receiver may correspond to the first receiver130.

At block1130, the second signal is input to a second receiver. For example, the second receiver may correspond to the second receiver150.

At block1140, a supply voltage of the second receiver is shifted based on the first signal and the second signal. For example, the supply voltage (e.g., vss_out) may be shifted by the first boost circuit (e.g., first boost circuit310). In certain aspects, the supply voltage is shifted during a transition of the input signal from low to high (e.g., transition410). In certain aspects, the supply voltage is shifted lower.

In certain aspects, shifting the supply voltage of the second receiver during the transition of the input signal from low to high includes shifting the supply voltage of the second receiver between a time that the first signal crosses a first threshold (e.g., Th_start_VIH) and a time that the second signal crosses a second threshold (e.g., Th_end_VIH).

In certain aspects, the method includes shifting a supply voltage (e.g., vdd_out) of the first receiver based on the first signal and the second signal. In certain aspects, shifting the supply voltage of the first receiver includes shifting the supply voltage of the first receiver during a transition of the input signal from high to low (e.g., transition420). In certain aspects, shifting the supply voltage of the first receiver during the transition of the input signal from high to low includes shifting the supply voltage of the first receiver between a time that the second signal crosses a first threshold (Th_start_VIL) and a time that the first signal crosses a second threshold (e.g., Th_end_VIL). In certain aspects, shifting the supply voltage of the first receiver includes shifting the supply voltage higher.

It is to be appreciated that a split receiver may also be referred to as a receiving circuit or another term.

It is also to be appreciated that the first threshold Th_start_VIL and the second threshold Th_end_VIL may also be referred to as the third threshold and the fourth threshold, respectively, for a receiving circuit including both the first boost circuit310and the second boost circuit320.

Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

It is to be appreciated that an n-type field effect transistor may also be referred to as an n-channel field effect transistor and a p-type field effect transistor may also be referred to as a p-channel field effect transistor. It is to be appreciated that the source and the drain of a transistor may each also be referred to as a terminal, and that the gate of a transistor may also be referred to as a control terminal.

a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output;

a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter;

a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter; and

a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver.

2. The receiving circuit of clause 1, wherein the first boost circuit is configured to shift a supply voltage of the second receiver based on the first signal and the second signal.

3. The receiving circuit of clause 2, wherein the first boost circuit is configured to shift the supply voltage of the second receiver during a transition of the input signal from low to high.

4. The receiving circuit of clause 2 or 3, wherein the first boost circuit is configured to shift the supply voltage of the second receiver between a time that the first signal crosses a first threshold and a time that the second signal crosses a second threshold.

5. The receiving circuit of any one of clauses 2 to 4, wherein the first boost circuit is configured to shift the supply voltage of the second receiver lower.

6. The receiving circuit of any one of clauses 1 to 5, further comprising a second boost circuit having a first input, a second input, and an output, wherein the first input of the second boost circuit is coupled to the input of the first receiver, the second input of the second boost circuit is coupled to the input of the second receiver, and the output of the second boost circuit is coupled to a supply terminal of the first receiver.

7. The receiving circuit of clause 6, wherein the second boost circuit is configured to shift a supply voltage of the first receiver based on the first signal and the second signal.

8. The receiving circuit of clause 7, wherein the second boost circuit is configured to shift the supply voltage of the first receiver during a transition of the input signal from high to low.

9. The receiving circuit of clause 7 or 8, wherein the second boost circuit is configured to shift the supply voltage of the first receiver between a time that the second signal crosses a first threshold and a time that the first signal crosses a second threshold.

10. The receiving circuit of any one of clauses 7 to 9, wherein the second boost circuit is configured to shift the supply voltage of the first receiver higher.

11. The receiving circuit of any one of clauses 1 to 10, further comprising a first logic decision circuit having a first input, a second input, and an output, wherein the first input of the first logic decision circuit is coupled to the output of the first receiver, and the second input of the first logic decision circuit is coupled to the output of the second receiver.

12. The receiving circuit of clause 11, wherein the first logic decision circuit is configured to:

output a first logic value when both the first receiver and the second receiver output a logic zero; and

output a second logic value when both the first receiver and the second receiver output a logic one.

13. The receiving circuit of clause 11 or 12, further comprising a second logic decision circuit having a first input, a second input, and an output, wherein the first input of the second logic decision circuit is coupled to the output of the first receiver, and the second input of the second logic decision circuit is coupled to the output of the second receiver,

wherein the output of the first logic decision circuit is configured to output a signal in a first voltage domain, and the output of the second logic decision circuit is configured to output a signal in a second voltage domain that is different from the first voltage domain.

14. The receiving circuit of any one of clauses 1 to 13, wherein:

the first boost circuit comprises a control circuit and a voltage circuit;

the control circuit has a first input, a second input, and an output;

the voltage circuit has an input and an output,

the first input of the control circuit is coupled to the input of the first receiver, the second input of the control circuit is coupled to the input of the second receiver, and the output of the control circuit is coupled to the input of the voltage circuit; and

the output of the voltage circuit is coupled to the supply terminal of the second receiver.

15. The receiving circuit of clause 14, wherein the voltage circuit comprises:

a first transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the supply terminal of the second receiver, the second terminal is coupled to a first supply voltage, and the control terminal is coupled to the output of the control circuit;

a second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second supply voltage, and the control terminal is coupled to the output of the control circuit;

a third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third supply voltage, the second terminal is coupled to the supply terminal of the second receiver, and the control terminal is coupled to the first supply voltage; and

a resistor coupled between the supply terminal of the second receiver and the second terminal of the second transistor.

16. The receiving circuit of clause 6, wherein:

the second boost circuit comprises a control circuit and a voltage circuit;

the control circuit has a first input, a second input, and an output;

the voltage circuit has an input and an output,

the first input of the control circuit is coupled to the input of the first receiver, the second input of the control circuit is coupled to the input of the second receiver, and the output of the control circuit is coupled to the input of the voltage circuit; and

the output of the voltage circuit is coupled to the supply terminal of the first receiver.

17. The receiving circuit of clause 16, wherein the second circuit comprises:

a first transistor having a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the supply terminal of the first receiver, the second terminal is coupled to a first supply voltage, and the control terminal is coupled to the output of the control circuit;

a second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a second supply voltage, and the control terminal is coupled to the output of the control circuit;

a third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a third supply voltage, the second terminal is coupled to the supply terminal of the first receiver, and the control terminal is coupled to the first supply voltage; and

a resistor coupled between the supply terminal of the first receiver and the second terminal of the second transistor.

18. The receiving circuit of any one of clauses 1 to 17, wherein the input signal has a first voltage swing, the first signal has a second voltage swing, the second signal has a third voltage swing, and each one of the second voltage swing and the third voltage swing is less than the first voltage swing.

19. The receiving circuit of any one of clauses 1 to 18, wherein a voltage of the second signal is higher than a voltage of the first signal.

a splitter having a first output and a second output, wherein the splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal at the first output, and output the second signal at the second output;

a first receiver having an input and an output, wherein the input of the first receiver is coupled to the first output of the splitter;

a second receiver having an input and an output, wherein the input of the second receiver is coupled to the second output of the splitter;

a first boost circuit having a first input, a second input, and an output, wherein the first input of the first boost circuit is coupled to the input of the first receiver, the second input of the first boost circuit is coupled to the input of the second receiver, and the output of the first boost circuit is coupled to a supply terminal of the second receiver; and

a second boost circuit having a first input, a second input, and an output, wherein the first input of the second boost circuit is coupled to the input of the first receiver, the second input of the second boost circuit is coupled to the input of the second receiver, and the output of the second boost circuit is coupled to a supply terminal of the first receiver.

21. The receiving circuit of clause 20, wherein:

the first boost circuit is configured to output a first supply voltage to the supply terminal of the second receiver, and to shift the first supply voltage based on the first signal and the second signal; and

the second boost circuit is configured to output a second supply voltage to the supply terminal of the first receiver, and to shift the second supply voltage based on the first signal and the second signal.

22. The receiving circuit of clause 21, wherein:

the first boost circuit is configured to shift the first supply voltage during a transition of the input signal from low to high; and

the second boost circuit is configured to shift the second supply voltage during a transition of the input signal from high to low.

23. The receiving circuit of clause 21 or 22, wherein:

the first boost circuit is configured to shift the first supply voltage between a time that the first signal crosses a first threshold and a time that the second signal crosses a second threshold; and

the second boost circuit is configured to shift the supply voltage of the second supply voltage between a time that the second signal crosses a third threshold and a time that the first signal crosses a fourth threshold.

24. The receiving circuit of any one of clauses 21 to 23, wherein:

the first boost circuit is configured to shift the first supply voltage lower; and

the second boost circuit is configured to shift the second supply voltage higher.

25. The receiving circuit of any one of clauses 20 to 24, further comprising a logic decision circuit having a first input, a second input, and an output, wherein the first input of the logic decision circuit is coupled to the output of the first receiver, and the second input of the logic decision circuit is coupled to the output of the second receiver.

26. The receiving circuit of clause 25, wherein the logic decision circuit is configured to:

output a first logic value when both the first receiver and the second receiver output a logic zero; and

output a second logic value when both the first receiver and the second receiver output a logic one.

27. The receiving circuit of any one of clauses 20 to 27, wherein the input signal has a first voltage swing, the first signal has a second voltage swing, the second signal has a third voltage swing, and each one of the second voltage swing and the third voltage swing is less than the first voltage swing.

28. A method of receiving an input signal, comprising:

splitting the input signal into a first signal and a second signal;

inputting the first signal to a first receiver;

inputting the second signal to a second receiver; and

shifting a supply voltage of the second receiver based on the first signal and the second signal.

29. The method of clause 28, wherein shifting the supply voltage of the second receiver comprises shifting the supply voltage of the second receiver during a transition of the input signal from low to high.

30. The method of clause 29, wherein shifting the supply voltage of the second receiver during the transition of the input signal from low to high comprises shifting the supply voltage of the second receiver between a time that the first signal crosses a first threshold and a time that the second signal crosses a second threshold.

31. The method of any one of clauses 28 to 30, wherein shifting the supply voltage of the second receiver comprises shifting the supply voltage of the second receiver lower.

32. The method of any one of clauses 28 to 31, further comprising shifting a supply voltage of the first receiver based on the first signal and the second signal.

33. The method of clause 32, wherein shifting the supply voltage of the first receiver comprises shifting the supply voltage of the first receiver during a transition of the input signal from high to low.

34. The method of clause 33, wherein shifting the supply voltage of the first receiver during the transition of the input signal from high to low comprises shifting the supply voltage of the first receiver between a time that the second signal crosses a first threshold and a time that the first signal crosses a second threshold.

35. The method of any one of clauses 32 to 34, wherein shifting the supply voltage of the first receiver comprises shifting the supply voltage of the first receiver higher.

36. The method of any one of clauses 28 to 35, wherein the input signal has a first voltage swing, the first signal has a second voltage swing, the second signal has a third voltage swing, and each one of the second voltage swing and the third voltage swing is less than the first voltage swing.

Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “approximately”, as used herein with respect to a stated value or a property, is intended to indicate being within 10% of the stated value or property.