High-side power device and manufacturing method thereof

A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

BACKGROUND OF THE INVENTION

Field of Invention

The present invention relates to a high-side power device and a manufacturing method thereof; particularly, it relates to such a high-side power device having a reduced conduction resistance, and a manufacturing method thereof.

Description of Related Art

FIG. 1Ashows a schematic diagram of a typical switching regulator10. The switching regulator10has a high-side switch UG and a low-side switch LG as shown in the figure. A high-side gate driver circuit13and a lower gate driver14drive the high-side switch UG and the low-side switch LG respectively. A control circuit11controls the high-side gate driver circuit13(through a level shifter circuit12) and the lower gate driver circuit14. The level shifter circuit12is required when the input voltage Vin is a relatively high voltage, such as 400V; in this case, the level shifter circuit12provides the required signal level to the high-side gate driver circuit13so as to properly drive the high-side switch UG. Although the voltage drops between the operation terminals of the high-side switch UG, such as its source, drain, and gate, are not high relatively to the input voltage Vin, the high-side switch UG is still required to withstand a high voltage drop between the input voltage Vin and the ground level GND, because the high-side switch UG and the low-side switch LG are typically formed in a same substrate, and the substrate is usually electrically connected to the ground level GND.

FIG. 1Bshows a schematic diagram of a cross-section view of a prior art high-side power device100, for use as the high-side switch UG. As shown inFIG. 1B, the high-side power device100includes a substrate101, an isolation oxide region103, a high voltage well105, a body region106, a source108, a drain109, and a gate111. The high voltage well105has an N-type conductive type and is formed in the substrate101which has a P-type conductive type. The isolation oxide region103is a local oxidation of silicon (LOCOS) structure, which defines an operation region103aas a major active region of the high-side power device100. The operation region103ais shown inFIG. 1Bas a region defined by two arrows. When the high-side power device100is used as the high-side switch UG, the substrate101of the high-side power device100is electrically connected to the ground level GND, and the high voltage well102is at a relatively high electric level; in a conduction operation, the high voltage well102in the operation region103ais completely depleted, and therefore the conduction resistance is high, restricting the operation speed and operation performance of the high-side power device100.

In view of the above, to overcome the drawbacks in the prior art, the present invention proposes a high-side power device having a reduced conduction resistance, and a manufacturing method thereof.

SUMMARY OF THE INVENTION

In one perspective, the present invention provides a high-side power device. The high-side power device includes: a substrate having a first conductive type, which includes a top surface and a bottom surface opposite to the top surface in a vertical direction; an epitaxial layer, which is formed on the substrate, and has an epitaxial surface opposite to the top surface in the vertical direction, wherein the epitaxial layer is stacked on and in contact with at least a portion of the top surface of the substrate; a high voltage well having a second conductive type, which is formed in the epitaxial layer, and is in contact with the top surface in the vertical direction; a body region having the first conductive type, which is formed in the epitaxial layer beneath the epitaxial surface, and connects the epitaxial surface in the vertical direction, wherein the body region and the high voltage well form a channel junction in a channel direction; a gate, which is formed on the epitaxial layer, and is stacked on and in contact with the epitaxial surface in the vertical direction, wherein the gate covers at least a part of the channel junction from a top view; a source having the second conductive type, which is formed in the epitaxial layer, and is beneath and connects the epitaxial surface in the vertical direction, wherein the source is located in the body region from the top view; a drain having the second conductive type, which is formed in the epitaxial layer, and is beneath and connects the epitaxial surface, wherein the drain and the source are located at different sides of the channel junction in the channel direction, wherein the drain and the gate are separated by the high voltage well from the top view; and a buried region having the second conductive type, which is formed in the substrate and the epitaxial layer, wherein a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer in the vertical direction, wherein an inner boundary of the buried region is located between the drain and the channel junction in the channel direction, and the buried region is not located vertically under the source and does not overlap the source from the top view; wherein a concentration of the second conductive type impurities of the buried region is higher than a predetermined threshold to prevent the high voltage well between the channel junction and the drain from being completely depleted in a conductive operation.

In one perspective, the present invention also provides a manufacturing method of a high-side power device. The manufacturing method includes: providing a substrate having a first conductive type, which includes a top surface and a bottom surface opposite to the top surface in a vertical direction; forming an epitaxial layer on the substrate, wherein the epitaxial layer has an epitaxial surface opposite to the top surface in the vertical direction, and is stacked on and in contact with at least a portion of the top surface of the substrate; forming a high voltage well having a second conductive type in the epitaxial layer, wherein the high voltage well is stacked on and in contact with the top surface in the vertical direction; forming a body region having the first conductive type in the epitaxial layer, wherein the body region is beneath the epitaxial surface and connects the epitaxial surface in the vertical direction, and wherein the body region and the high voltage well form a channel junction in a channel direction; forming a gate on the epitaxial layer, wherein the gate is stacked on and in contact with the epitaxial surface in the vertical direction, and wherein the gate covers at least a part of the channel junction from a top view; forming a source having the second conductive type in the epitaxial layer, wherein the source is beneath and connects the epitaxial surface in the vertical direction, and wherein the source is located in the body region from the top view; forming a drain having the second conductive type in the epitaxial layer, the drain being beneath and connecting the epitaxial surface, wherein the drain and the source are located at different sides of the channel junction in the channel direction, and wherein the drain and the gate are separated by the high voltage well from the top view; and forming a buried region having the second conductive type in the substrate and the epitaxial layer, wherein a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer in the vertical direction, wherein an inner boundary of the buried region is located between the drain and the channel junction in the channel direction, and the buried region is not located vertically under the source and does not overlap the source from the top view; wherein a concentration of the second conductive type impurities of the buried region is higher than a predetermined threshold to prevent the high voltage well between the channel junction and the drain from being completely depleted in a conductive operation.

In one preferable embodiment, a distance between the inner boundary and the drain in the channel direction is longer than a quarter of a drift length between the channel junction and the drain in the channel direction.

In one preferable embodiment, the high-side power device further includes an isolation oxide region, which is formed on the epitaxial layer, for defining an operation region, wherein the body region, the source, and the drain are all located in the operation region from the top view.

In the aforementioned embodiment, the high-side power device preferably further includes a drift oxide region, which is formed in the operation region on the epitaxial layer, and is stacked on and in contact with the high voltage well in the vertical direction, wherein the drift oxide region is located between the channel junction and the drain in the channel direction.

In one preferable embodiment, the high-side power device further includes a contact region having the first conductive type, which is formed in the epitaxial layer, and is stacked beneath and connects the epitaxial surface, wherein the contact region is located in the body region from the top view.

In one perspective, the present invention also provides a high-side power device. The high-side power device includes: a substrate having a first conductive type, which includes a top surface and a bottom surface opposite to the top surface in a vertical direction; a high voltage well having a second conductive type, which is formed in the substrate, and is beneath the top surface in the vertical direction; a body region having the first conductive type, which is formed in the substrate beneath the top surface, wherein the body region and the high voltage well form a channel junction in a channel direction; a gate, which is formed on the substrate, and is stacked on and in contact with the top surface in the vertical direction, wherein the gate covers at least a part of the channel junction from a top view; a source having the second conductive type, which is formed in the substrate, and is beneath and connects the top surface in the vertical direction, wherein the source is located in the body region from the top view; a drain having the second conductive type, which is formed in the substrate, and is beneath and connects the top surface, wherein the drain and the source are located at different sides of the channel junction in the channel direction, and wherein the drain and the gate are separated by the high voltage well from the top view; and a buried region having the second conductive type, which is formed in the substrate, and is located below the drain in the vertical direction, wherein an inner boundary of the buried region is located between the drain and the channel junction in the channel direction, and the buried region is not located vertically under the source and does not overlap the source from the top view; wherein a concentration of the second conductive type impurities of the buried region is higher than a predetermined threshold to prevent the high voltage well between the channel junction and the drain from being completely depleted in a conductive operation.

In one perspective, the present invention also provides a manufacturing method of a high-side power device. The manufacturing method includes: forming a substrate having a first conductive type, which includes a top surface and a bottom surface opposite to the top surface in a vertical direction; forming a high voltage well having a second conductive type in the substrate, wherein the high voltage well is beneath the top surface in the vertical direction; forming a body region having the first conductive type in the substrate beneath the top surface, wherein the body region and the high voltage well forma channel junction in a channel direction; forming a gate on the substrate, wherein the gate is stacked on and in contact with the top surface in the vertical direction, wherein the gate covers at least a part of the channel junction from a top view; forming a source having the second conductive type in the substrate, wherein the source is beneath and connects the top surface in the vertical direction, and wherein the source is located in the body region from the top view; forming a drain having the second conductive type in the epitaxial layer, the drain being beneath and connecting the epitaxial surface, wherein the drain and the source are located at different sides of the channel junction in the channel direction, and wherein the drain and the gate are separated by the high voltage well from the top view; and forming a buried region having the second conductive type in the substrate, wherein the buried region is located below the drain in the vertical direction, wherein an inner boundary of the buried region is located between the drain and the channel junction in the channel direction, and the buried region is not located vertically under the source and does not overlap the source from the top view; wherein a concentration of the second conductive type impurities of the buried region is higher than a predetermined threshold to prevent the high voltage well between the channel junction and the drain from being completely depleted in a conductive operation.

In one preferable embodiment, a distance between the inner boundary and the drain in the channel direction is longer than a quarter of a drift length between the channel junction and the drain in the channel direction.

In one preferable embodiment, the high-side power device further includes an isolation oxide region, which is formed on the substrate, for defining an operation region, wherein the body region, the source, and the drain are all located in the operation region from the top view.

In the aforementioned embodiment, the high-side power device preferably further includes a drift oxide region, which is formed in the operation region on the substrate, and is stacked on and in contact with the high voltage well in the vertical direction, wherein the drift oxide region is located between the channel junction and the drain in the channel direction.

In one preferable embodiment, the high-side power device further includes a contact region having the first conductive type, which is formed in the substrate, and is stacked beneath and connects the top surface, wherein the contact region is located in the body region from the top view.

The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The drawings as referred to throughout the description of the present invention are for illustration only, to show the interrelations between the regions and the process steps, but not drawn according to actual scale.

Please refer toFIGS. 2A and 2Bfor a first embodiment according to the present invention.FIG. 2Ashows a schematic diagram of a cross-section view of a high-side power device200.FIG. 2Bshows a schematic diagram of a top view of the high-side power device200. As shown inFIG. 2A, The high-side power device200includes: a substrate201, an epitaxial layer202, an isolation oxide region203, a high voltage well205, a body region206, a contact region206a, a buried region207, a source208, a drain209, and a gate211.

The substrate201having a first conductive type (for example but not limited to P-type) includes a top surface201aand a bottom surface201bopposite to the top surface201ain a vertical direction (as shown by the dash arrow in the figure). The epitaxial layer202is formed on the substrate201by an epitaxial process step; the epitaxial layer202is stacked on and in contact with the top surface201aof the substrate201. The epitaxial layer202includes an epitaxial top surface202aopposite to the top surface201a. The isolation oxide region203is for example but not limited to a local oxidation of silicon (LOCOS) structure, and is formed on the epitaxial layer202, for defining an operation region203aas a major active region when the high-side power device200operates, wherein the body region206, the source208, and the drain209are all located in the operation region203afrom the cross-section viewFIG. 2Aand the top viewFIG. 2B. The high voltage well205having a second conductive type (for example but not limited to N-type) is formed in the epitaxial layer202, and is stacked on and in contact with the top surface201aof the substrate201in the vertical direction.

The body region206having the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer202beneath the epitaxial surface202a, and connects the epitaxial surface202ain the vertical direction, wherein the body region206and the high voltage well205form a channel junction JN (as indicated by thick solid lines shown inFIGS. 2A and 2B) in a channel direction (as indicated by solid arrows inFIGS. 3A and 3B). The gate211is formed on the epitaxial layer202, and is stacked on and in contact with the epitaxial surface202ain the vertical direction, wherein the gate211covers at least a part of the channel junction JN as shown in the cross-section viewFIG. 2Aand a top viewFIG. 2B; in this embodiment, the gate211covers all the channel junction JN. The source208having the second conductive type (for example but not limited to the N-type) is formed in the epitaxial layer202, and is stacked beneath and connects the epitaxial surface202ain the vertical direction, wherein the source208is located in the body region206as shown in the cross-section viewFIG. 2Aand the top viewFIG. 2B. The drain209having the second conductive type (for example but not limited to the N-type) is formed in the epitaxial layer202, and is beneath and connects the epitaxial surface202a. The drain209and the source208are located at different sides of the channel junction JN in the channel direction. The drain209and the gate211are separated by the high voltage well205as shown in the cross-section viewFIG. 2Aand the top viewFIG. 2B.

The contact region206ahaving the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer202, and is stacked beneath and connects the epitaxial surface202a, wherein the contact region206ais located in the body region206as shown in the cross-section viewFIG. 2Aand the top viewFIG. 2B. The buried region207having the second conductive type (for example but not limited to the N-type) is formed in the substrate201and the epitaxial layer202, wherein a part of the buried region207(in this embodiment, for example the lower part) is located in the substrate201and another part (in this embodiment, for example the upper part) of the buried region207is located in the epitaxial layer202in the vertical direction, wherein an inner boundary IB of the buried region207is located between the drain209and the channel junction JN in the channel direction, and the buried region207is not located vertically under the source208as shown inFIG. 2A(that is, the buried region207does not overlap the source from the top viewFIG. 2B). A concentration of the second conductive type impurities (N-type impurities in this embodiment) of the buried region207is sufficient (i.e., higher than a predetermined level) to prevent the high voltage well205between the channel junction JN and the drain209from being completely depleted in a conductive operation of the high-side power device200.

The “operation region203a”, as understood by those skilled in this art, indicates a range in the high-side power device200wherein charged carriers are formed and/or moved to generate a current by applying a voltage which forms an electric field, during a normal operation (i.e., when the high-side power device200are controlled to be conductive and not conductive).

Besides, in a preferably embodiment, in the channel direction, a distance d between the inner boundary IB and the drain209in the channel direction is longer than a quarter of a drift length L between the channel junction JN and the drain209in the channel direction as shown inFIG. 2A.

Please refer toFIGS. 3A and 3Bfor a second embodiment according to the present invention.FIG. 3Ashows a schematic diagram of a cross-section view of a high-side power device300.FIG. 3Bshows a schematic diagram of a top view of the high-side power device300. As shown inFIG. 3A, The high-side power device300includes: a substrate301, an epitaxial layer302, an isolation oxide region303, a drift oxide region304, a high voltage well305, a body region306, a contact region306a, a buried region307, a source308, a drain309, and a gate311.

The substrate301having the first conductive type (for example but not limited to the P-type) includes a top surface301aand a bottom surface301bopposite to the top surface301ain a vertical direction (as shown by the dash arrow in the figure). The epitaxial layer302is formed on the substrate301by an epitaxial process step, i.e., the epitaxial layer302is stacked on and in contact with the top surface301aof the substrate301. The epitaxial layer302includes an epitaxial top surface302aopposite to the top surface201a. The isolation oxide region303is for example but not limited to the LOCOS structure, and is formed on the epitaxial layer302, for defining an operation region303aas a major active region when the high-side power device300operates, wherein the body region306, the source308, and the drain309are all located in the operation region303aas shown in the cross-section viewFIG. 3Aand the top viewFIG. 3B. The high voltage well305having the second conductive type (for example but not limited to N-type) is formed in the epitaxial layer302, and is stacked on and in contact with the top surface301aof the substrate301in the vertical direction.

The body region306having the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer302beneath the epitaxial surface302a, and connects the epitaxial surface302ain the vertical direction, wherein the body region306and the high voltage well305form a channel junction JN (as indicated by thick solid lines shown inFIGS. 3A and 3B) in a channel direction (as indicated by solid arrows inFIGS. 3A and 3B). The gate311is formed on the epitaxial layer302, and is stacked on and in contact with the epitaxial surface302ain the vertical direction, wherein the gate311covers at least a part of the channel junction JN as shown in the cross-section viewFIG. 3Aand the top viewFIG. 3B; in this embodiment, the gate311covers all the channel junction JN. The source308having the second conductive type (for example but not limited to the N-type) is formed in the epitaxial layer302, and is stacked beneath and connects the epitaxial surface302ain the vertical direction, wherein the source308is located in the body region306as shown in the cross-section viewFIG. 3Aand the top viewFIG. 3B. The drain309having the second conductive type (for example but not limited to the N-type) is formed in the epitaxial layer302, and is beneath and connects the epitaxial surface302a. The drain309and the source308are located at different sides of the channel junction JN in the channel direction. The drain309and the gate311are separated by the high voltage well305as shown in the cross-section viewFIG. 3Aand the top viewFIG. 3B.

The contact region306ahaving the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer302, and is stacked beneath and connects the epitaxial surface302a, wherein the contact region306ais located in the body region306as shown in the cross-section viewFIG. 3Aand the top viewFIG. 3B. The buried region307having the second conductive type (for example but not limited to the N-type) is formed in the substrate301and the epitaxial layer302, wherein a part of the buried region307(in this embodiment, for example the lower part) is located in the substrate301and another part (in this embodiment, for example the upper part) of the buried region307is located in the epitaxial layer302in the vertical direction, wherein an inner boundary IB of the buried region307is located between the drain309and the channel junction JN in the channel direction, and the buried region307is not located vertically under the source308as shown inFIG. 3A(that is, the buried region307does not overlap the source308from the top viewFIG. 3B). A concentration of the second conductive type impurities (N-type impurities in this embodiment) of the buried region307is sufficient (i.e., higher than a predetermined level) to prevent the high voltage well305between the channel junction JN and the drain309from being completely depleted in a conductive operation of the high-side power device300.

The “operation region303a”, as understood by those skilled in this art, indicates a range in the high-side power device300wherein charged carriers are formed and/or moved to generate a current by applying a voltage which forms an electric field, during a normal operation (i.e., when the high-side power device200are controlled to be conductive and not conductive).

Besides, in a preferably embodiment, in the channel direction, a distance d between the inner boundary IB and the drain309in the channel direction is longer than a quarter of a drift length L between the channel junction JN and the drain309in the channel direction as shown inFIG. 3A.

The drift oxide region304is formed in the operation region303aon the epitaxial layer302, and is stacked on and in contact with the high voltage well305in the vertical direction, wherein the drift oxide region304is located between the channel junction JN and the drain309in the channel direction.

Please refer toFIGS. 4A and 4Bfor a third embodiment according to the present invention.FIG. 4Ashows a schematic diagram of a cross-section view of a high-side power device400.FIG. 4Bshows a schematic diagram of a top view of the high-side power device400. As shown inFIG. 4A, The high-side power device400includes: a substrate401, an isolation oxide region403, a high voltage well405, a body region406, a contact region406a, a buried region407, a source408, a drain409, and a gate411.

The substrate401having the first conductive type (for example but not limited to the P-type) includes a top surface401aand a bottom surface401bopposite to the top surface401ain a vertical direction (as shown by the dash arrow in the figure). The isolation oxide region403is for example but not limited to the LOCOS structure, and is formed on the substrate401, for defining an operation region403aas a major active region when the high-side power device400operates, wherein the body region406, the source408, and the drain409are all located in the operation region403aas shown in the cross-section viewFIG. 4Aand the top viewFIG. 4B. The high voltage well405having the second conductive type (for example but not limited to the N-type) is formed in the substrate401.

The body region406having the first conductive type (for example but not limited to the P-type) is formed in the substrate401beneath the top surface401a, and connects the top surface401ain the vertical direction, wherein the body region406and the high voltage well405form a channel junction JN (as indicated by thick solid lines shown inFIGS. 4A and 4B) in a channel direction (as indicated by solid arrows inFIGS. 4A and 4B). The gate411is formed on the substrate401, and is stacked on and in contact with the top surface401ain the vertical direction, wherein the gate411covers at least a part of the channel junction JN as shown in the cross-section viewFIG. 4Aand the top viewFIG. 4B; in this embodiment, the gate411covers all the channel junction JN. The source408having the second conductive type (for example but not limited to the N-type) is formed in the substrate401, and is stacked beneath and connects the top surface401ain the vertical direction, wherein the source408is located in the body region406as shown in the cross-section viewFIG. 4Aand the top viewFIG. 4B. The drain409having the second conductive type (for example but not limited to the N-type) is formed in the substrate401, and is beneath and connects the top surface401a. The drain409and the source408are located at different sides of the channel junction JN in the channel direction. The drain409and the gate411are separated by the high voltage well405as shown in the cross-section viewFIG. 4Aand the top viewFIG. 4B.

The contact region406ahaving the first conductive type (for example but not limited to the P-type) is formed in the substrate401, and is stacked beneath and connects the top surface401a, wherein the contact region406ais located in the body region406as shown in the cross-section viewFIG. 4Aand the top viewFIG. 4B. The buried region407having the second conductive type (for example but not limited to the N-type) is formed in the substrate401, and is located vertically below the drain409in the vertical direction, wherein an inner boundary IB of the buried region407is located between the drain409and the channel junction JN in the channel direction, and the buried region407is not located vertically under the source408as shown inFIG. 4A(that is, the buried region407does not overlap the source408from the top viewFIG. 4B). A concentration of the second conductive type impurities (N-type impurities in this embodiment) of the buried region407is sufficient (i.e., higher than a predetermined level) to prevent the high voltage well405between the channel junction JN and the drain409from being completely depleted in a conductive operation of the high-side power device400.

The “operation region403a”, as understood by those skilled in this art, indicates a range in the high-side power device200wherein charged carriers are formed and/or moved to generate a current by applying a voltage which forms an electric field, during a normal operation (i.e., when the high-side power device400are controlled to be conductive and not conductive).

Besides, in a preferably embodiment, in the channel direction, a distance d between the inner boundary IB and the drain409in the channel direction is longer than a quarter of a drift length L between the channel junction JN and the drain409in the channel direction as shown inFIG. 4A.

Please refer toFIGS. 5A and 5Bfor a fourth embodiment according to the present invention.FIG. 5Ashows a schematic diagram of a cross-section view of a high-side power device500.FIG. 5Bshows a schematic diagram of a top view of the high-side power device500. As shown inFIG. 5A, The high-side power device500includes: a substrate501, an isolation oxide region503, a drift oxide region504, a high voltage well505, a body region506, a contact region506a, a buried region507, a source508, a drain509, and a gate511.

The substrate501having the first conductive type (for example but not limited to the P-type) includes a top surface501aand a bottom surface501bopposite to the top surface501ain a vertical direction (as shown by the dash arrow in the figure). The isolation oxide region503is for example but not limited to the LOCOS structure, and is formed on the substrate501, for defining an operation region503aas a major active region when the high-side power device500operates, wherein the body region506, the source508, and the drain509are all located in the operation region503aas shown in the cross-section viewFIG. 5Aand the top viewFIG. 5B. The high voltage well505having the second conductive type (for example but not limited to the N-type) is formed in the substrate401.

The body region506having the first conductive type (for example but not limited to the P-type) is formed in the substrate501beneath the top surface501a, and connects the top surface501ain the vertical direction, wherein the body region506and the high voltage well505form a channel junction JN (as indicated by thick solid lines shown inFIGS. 5Aand5B) in a channel direction (as indicated by solid arrows inFIGS. 5A and 5B). The gate511is formed on the substrate501, and is stacked on and in contact with the top surface501ain the vertical direction, wherein the gate511covers at least a part of the channel junction JN as shown in the cross-section viewFIG. 5Aand the top viewFIG. 5B; in this embodiment, the gate511covers all the channel junction JN. The source508having the second conductive type (for example but not limited to the N-type) is formed in the substrate501, and is stacked beneath and connects the top surface501ain the vertical direction, wherein the source508is located in the body region506as shown in the cross-section viewFIG. 5Aand the top viewFIG. 5B. The drain509having the second conductive type (for example but not limited to the N-type) is formed in the substrate501, and is beneath and connects the top surface501a. The drain509and the source508are located at different sides of the channel junction JN in the channel direction. The drain509and the gate511are separated by the high voltage well505as shown in the cross-section viewFIG. 5Aand the top viewFIG. 5B.

The contact region506ahaving the first conductive type (for example but not limited to the P-type) is formed in the substrate501, and is stacked beneath and connects the top surface501a, wherein the contact region506ais located in the body region506as shown in the cross-section view FIG.5A and the top viewFIG. 5B. The buried region507having the second conductive type (for example but not limited to the N-type) is formed in the substrate501, and is located vertically below the drain509in the vertical direction, wherein an inner boundary IB of the buried region507is located between the drain509and the channel junction JN in the channel direction, and the buried region507is not located vertically under the source508as shown inFIG. 5A(that is, the buried region507does not overlap the source508from the top viewFIG. 5B). A concentration of the second conductive type impurities (N-type impurities in this embodiment) of the buried region507is sufficient (i.e., higher than a predetermined level) to prevent the high voltage well505between the channel junction JN and the drain509from being completely depleted in a conductive operation of the high-side power device500.

The “operation region503a”, as understood by those skilled in this art, indicates a range in the high-side power device500wherein charged carriers are formed and/or moved to generate a current by applying a voltage which forms an electric field, during a normal operation (i.e., when the high-side power device200are controlled to be conductive and not conductive).

Besides, in a preferably embodiment, in the channel direction, a distance d between the inner boundary IB and the drain509in the channel direction is longer than a quarter of a drift length L between the channel junction JN and the drain509in the channel direction as shown inFIG. 5A.

The drift oxide region504is formed in the operation region503aon the substrate501, and is stacked on and in contact with the high voltage well505in the vertical direction, wherein the drift oxide region504is located between the channel junction JN and the drain509in the channel direction.

FIGS. 6A-6Lshow a fifth embodiment of the present invention. This embodiment shows an example of a manufacturing method of the high-side power device300of the second embodiment according to the present invention from top views and cross-section views. For better understanding, top views and cross-section views of the high-side power device300are shown in parallel at left and right sides.

As shown in the top viewFIG. 6Aand cross-section viewFIG. 6B, the substrate301is provided, wherein the substrate301is for example but not limited to a P-type silicon substrate (or a P-type semiconductor substrate of another material). The substrate301includes a top surface301aand a bottom surface301bopposite to the top surface301ain the vertical direction (as shown by the dash arrow inFIG. 6B). Next, as shown inFIGS. 6A and 6B, the epitaxial layer302is formed on the substrate301, which has an epitaxial surface302aopposite to the top surface301ain the vertical direction, and is stacked on and in contact with at least a portion of the top surface301aof the substrate301. Next, for example an ion implantation process step is taken to implant second conductive type impurities in the form of accelerated ions, as indicated by the dash arrow lines shown inFIG. 6B. The high voltage well305having the second conductive type (for example but not limited to the N-type) is formed in the epitaxial layer302, and is stacked on and in contact with the top surface301aof the substrate301in the vertical direction.

The buried region307having the second conductive type (for example but not limited to the N-type) is formed in the substrate301and in the epitaxial layer302, wherein a part of the buried region307(in this embodiment, for example the lower part) is located in the substrate301and another part (in this embodiment, for example the upper part) of the buried region307is located in the epitaxial layer302in the vertical direction. The buried region307can be formed for example by the following steps. First, the location of the buried region307is defined by for example but not limited to a photoresist mask formed by a lithography process step (not shown), and an ion implantation process step implants for example but not limited to N-type impurities to the defined region in the form of accelerated ions. An implantation region of the buried region307is formed in the substrate301. Next, the photoresist mask is removed, and next, after the epitaxial layer302is formed, an anneal process step thermally diffuses a part of the N-type impurities in the implantation region of the buried region307to the epitaxial layer302, such that the buried region307is formed to be located partially in the substrate301and partially in the epitaxial layer302.

Next, as shown in the top viewFIG. 6Cand cross-section viewFIG. 6D, the isolation oxide region303is formed on the epitaxial layer302, for defining the operation region303a, and the drift oxide region304is formed in the operation region303aon the epitaxial layer302concurrently with or after the formation of the isolation oxide region303, wherein the drift oxide region304is stacked on and in contact with the high voltage well305in the vertical direction. The isolation oxide region303and the drift oxide region304are for example but not limited to the LOCOS structure as shown in the figure; in another embodiment, the isolation oxide region303and the drift oxide region304may be a shallow trench isolation (STI) structure instead.

Next, as shown in the top viewFIG. 6Eand cross-section viewFIG. 6F, the body region306having the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer302beneath the epitaxial surface302a, and connects the epitaxial surface302ain the vertical direction, wherein the body region306and the high voltage well305form a channel junction JN (as indicated by thick solid lines shown inFIGS. 6E and 6F) in a channel direction (as indicated by solid arrows inFIG. 6F).

The body region306is defined by for example but not limited to a photoresist mask306bformed by a lithography process step, and an ion implantation process step implants for example but not limited to P-type impurities to the defined region in the form of accelerated ions. An implantation region of the body region306is formed in the substrate301. Next, the photoresist mask306bis removed.

Next, as shown in the top viewFIG. 6Gand cross-section viewFIG. 6H, the gate311is formed on the epitaxial layer302, which is stacked on and in contact with the epitaxial surface302aof the epitaxial layer302in the vertical direction, wherein the gate311covers at least a part of the channel junction JN as shown in the cross-section viewFIG. 6Hand the top viewFIG. 6G; in this embodiment, the gate311covers all the channel junction JN.

Next, as shown in the top viewFIG. 6Iand cross-section viewFIG. 6J, the source308and the drain309having the second conductive type (for example but not limited to the N-type) are formed in the epitaxial layer302, and are stacked beneath and connect the epitaxial surface302ain the vertical direction, wherein the source308is located in the body region306and the drain309is formed in the epitaxial layer302as shown in the cross-section viewFIG. 6Jand the top viewFIG. 6I. The source308and the drain309are located at different sides of the channel junction JN in the channel direction. The drain309and the gate311are separated by the high voltage well305as shown in the cross-section viewFIG. 6Jand the top viewFIG. 6I. In a conductive operation of the N-type high-side power device300, for example, a current flows from the N-type drain309through the high voltage well305and the body region306to the source308. By applying a positive voltage to the gate311, a channel is formed around a junction between the P-type body region306and the gate311, and thus in the conductive operation, the conductive current flows from the drain309to the source308.

The source308and the drain309are formed by for example but not limited to a same lithography process step and a same ion implantation process step. As shown inFIG. 6J, the N-type source308and the drain309are defined by for example but not limited to the gate311together with a photoresist mask308aformed by the lithography process step, and the ion implantation process step implants for example but not limited to N-type impurities to the defined regions in the form of accelerated ions as indicated by the dash arrow lines shown inFIG. 6J. The N-type source308and the N-type drain309are formed beneath and connect the epitaxial surface302a.

Next, as shown in the top viewFIG. 6Kand cross-section viewFIG. 6L, the contact region306ahaving the first conductive type (for example but not limited to the P-type) is formed in the epitaxial layer302, and is stacked beneath and connects the epitaxial surface302a. The contact region306ais defined by for example but not limited to a photoresist mask306bformed by a lithography process step, and an ion implantation process step implants for example but not limited to P-type impurities to the defined region in the form of accelerated ions. An implantation region of the contact region306ais formed in the epitaxial layer302. Next, the photoresist mask306bis removed, and next, an anneal process step anneals the P-type impurities in the implantation region of the contact region306a, to form the contact region306a.

FIGS. 7A and 7Bshow simulation diagrams of a depleted region of the prior art high-side power device100when different voltages are applied thereto.FIG. 7Ashows the simulation result when 0.1V is applied to the drain109, 5V is applied to the gate111, and the substrate101is electrically connected to 0V. As shown in the figure, a depleted region is formed around a lower boundary of the high voltage well105of the high-side power device100, wherein the depleted region is shown as an area between an upper and a lower dash lines. A conductive resistance of the high-side power device100shown inFIG. 7Ais 231 mOhm-mm2.FIG. 7Bshows the simulation result when 0.1V is applied to the drain109, 5V is applied to the gate111, and the substrate101is electrically connected to −80V. As shown in the figure, a depleted region is formed around a lower boundary of the high voltage well105of the high-side power device100, wherein the depleted region is shown as an area between an upper and a lower dash lines. A conductive resistance of the high-side power device100shown inFIG. 7Bis 1284 mOhm-mm2. Typically, it is required to connect the substrate of a high-side power device to a high voltage, for example but not limited to the aforementioned voltage −80V.FIG. 7Bshows that under such circumstance, the channel of the high-side power device100is almost completely pinched off, resulting in the high conductive resistance 1284 mOhm-mm2, which is more than five times of the conductive resistance 231 mOhm-mm2 shown inFIG. 7Aand is greatly undesired.

FIGS. 8A and 8Bshow simulation diagrams of a depleted region of the high-side power device300according to the present invention when different voltages are applied thereto.FIG. 8Ashows the simulation result when 0.1V is applied to the drain309, 5V is applied to the gate311, and the substrate301is electrically connected to 0V. As shown in the figure, a depleted region is formed around a lower boundary of the high voltage well305of the high-side power device300, wherein the depleted region is shown as an area between an upper and a lower dash lines. A conductive resistance of the high-side power device300shown inFIG. 8Ais 226 mOhm-mm2.FIG. 8Bshows the simulation result when 0.1V is applied to the drain309, 5V is applied to the gate311, and the substrate301is electrically connected to −80V. A conductive resistance of the high-side power device300shown inFIG. 8Bis 413 mOhm-mm2. In the normal operation of the high-side power device300, the substrate301can be electrically connected to a high voltage, for example but not limited to the aforementioned voltage −80V.FIG. 8Bshows that when the high-side power device300operates in the normal operation, the channel is not completely pinched off, and the conductive resistance is as low as 413 mOhm-mm2, not even twice the conductive resistance 226 mOhm-mm2 shown inFIG. 8A. The present invention is apparently advantageous over the prior art because of the relatively lower conductive resistance, and the application range of the high side power device of the present invention is much broader.

The present invention has been described in considerable detail having reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, other process steps or structures which do not affect the primary characteristic of the device, such as a threshold voltage adjustment region, etc., can be added; for another example, the lithography step described in the above can be replaced by electron beam lithography or other lithography techniques. For another example, the conductive types of the P-type and the N-type of all the embodiments are interchangeable, with corresponding modifications in the conductive types and/or impurity concentrations in corresponding regions. In view of the foregoing, the spirit of the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents. An embodiment or a claim of the present invention does not need to achieve all the objectives or advantages of the present invention. The title and abstract are provided for assisting searches but not for limiting the scope of the present invention.