Low voltage high gain amplifier circuits

In one embodiment, the present invention provides an amplifier circuit including a cascode input stage coupled to a differential stage. In another embodiment, an amplifier includes a differential stage coupled to a common gate stage. Embodiments of the present invention also include an improved low voltage amplifier using a 3-stage topology including a wide-swing folded-cascode input stage followed by a differential gain stage which provides improved gain and output compliance. Embodiments of the present invention improve the available cascode stage headroom and reject process and temperature induced parametric variations.

BACKGROUND

This invention relates to electronic circuits, and more particularly, to amplifier circuits useful in low power supply voltage applications.

Amplifier circuits are used in a variety of electronic systems for increasing the voltage, current, or power of a signal.FIG. 1shows one example of an amplifier100configured to receive an input voltage, Vin, and provide an amplified voltage, Vout. Amplifier100includes a positive input terminal101(“V+”), a negative input terminal102(“V−”), an output terminal103(“Vout”), a positive supply terminal104, and a negative supply terminal105. Input voltage, Vin, is received on terminal101, and the amplified voltage, Vout, is provided on terminal103. Amplifier100includes feedback resistors106(“R1”) and107(“R2”), which are connected in a “closed loop” to provide negative feedback. The output voltage, Vout, of amplifier100is related to the inputs according to the following well-known equation:
Vo=G(V+−V−),
where “G” is the “open loop” gain of amplifier100. If the open loop gain “G” of amplifier100is sufficiently large, then the “closed loop” gain of the present configuration is approximately given by the following:
Vo/Vin=(1+R2/R1)

In some applications, an amplifier must maintain its input-output relationship with a high level of accuracy across a substantial portion of the output voltage range. However, in many actual implementations, the accuracy of an amplifier can be impaired by non-linearities in the open loop gain. To solve this problem, it is possible to utilize a closed loop configuration, such as the one illustrated inFIG. 1, with an amplifier that has a high open loop gain to achieve a closed loop system with high accuracy. Accordingly, it is desirable to have an amplifier circuit with a high open loop gain.

One trend in integrated circuit technology that has created challenges for amplifier circuit designers is the continuing reduction in the power supply voltages used in electronic systems. As power supply voltages are decreased, an amplifier's open loop gain can become constrained by the maximum and minimum voltages allowable on the amplifier's internal nodes. The difference between a maximum and minimum allowable voltage on a given node is referred to herein as “headroom.” As the headroom of an amplifier's internal nodes is constrained by reductions in supply voltage, the gain of the amplifier may also have to be reduced so that intermediate signals do not exceed allowable levels.

FIGS. 2A and 2Bshow common amplifier circuits known in the art in order to illustrate the headroom limitations discussed above. Amplifier200shown inFIG. 2Ais one example of a cascaded common source stage and common gate stage referred to as a “cascode” stage. The term cascode stage refers a variety of circuit structures that include one or more cascode transistors. In the present example, a simple two transistor structure is shown. In amplifier200, NMOS transistor211is the input device and NMOS transistor212is the cascode device (i.e., the cascode transistor). Amplifier200also includes a current source230. Transistor211receives an input signal Vin and generates a current proportional to the input voltage. Cascode transistor212is biased by a fixed voltage Vb1, and routes the current to the output while simultaneously increasing the output impedance of the circuit. The approximate gain of amplifier200is given by the following equation:
Vout/Vin≈gm1ro2(1+gm2ro2)
Where gm1and gm2are transconductances and ro1and ro2are output impedances of transistors211and212, respectively.

Cascode circuits are useful because they provide very high gain. However, cascode circuits achieve higher gains at the expense of headroom. The loss in headroom may be illustrated by first noting that both transistors211and212should remain in saturation to achieve optimum gain performance. Therefore, the minimum output voltage can be expressed as follows:
Vout≧VGS1−VTH1+VGS2−VTH2
Where VGS1and VGS2are the gate to source voltages and VTH1and VTH2are the threshold voltages of transistors211and212, respectively.

FIG. 2Bshows a cascode circuit250including a cascode current source which limits the maximum allowable output voltage. In cascode circuit250, the ideal current source has been replaced with a cascode current source comprising PMOS transistors213and214biased by voltages Vb2and Vb3, respectively. A cascode current source is useful because the high output impedance associated with such structures yields a current source closer to an ideal current source. However, for optimum operation the maximum output voltage is limited as follows:
Vout≦VS−|VGS3−VTH3|−|VGS4−VTH4|
Where VGS3and VGS4are the gate to source voltages and VTH3and VTH4are the threshold voltages of transistors213and214, respectively.

Accordingly, known cascode circuits are advantageous because they provide large gain. On the other hand, known cascode circuits are disadvantageous for low power supply applications because they have limited headroom. This limited headroom can impact the ability of the circuit to amplify currents or voltages at the output or at intermediate nodes. More particularly, at low power supply voltages, headroom limitations constrain the ability of cascode stages to drive inputs of transistors in an output stage across wide voltage ranges. These limitations result in output stages that cannot provide accurate output voltages across wide voltage ranges. What is needed is an amplifier circuit that provides high gain that can operate effectively at low power supply voltage levels.

SUMMARY

Embodiments of the present invention include amplifier circuits that may be useful for low power supply voltage applications. Amplifier circuits according to embodiments of the present invention may include a plurality of stages for processing signals. In one embodiment, the present invention provides an amplifier circuit including a cascode input stage and a differential stage having an input coupled to an output terminal of the cascode input stage. In another embodiment, a differential stage has a first input coupled to the output of a cascode transistor in the input stage, and a second input coupled to a cascode node (i.e., a node between cascaded or series connected devices).

In another embodiment, the present invention includes an amplifier having a differential stage with an output node coupled to a voltage dependent load having an impedance dependent on the voltage on the output terminal. The impedance of the load increases as the voltage on the differential stage output node increases from a negative power supply, reaches a maximum when the voltage on the differential output node is in a first voltage range between the negative power supply and a positive power supply, and decreases as the voltage on the differential output node increases toward the positive power supply.

Embodiments of the present invention may use a current mirror disclosed herein. In one embodiment, the current mirror comprises a first transistor having an current input terminal, a current output terminal, and a control terminal, a second transistor having a current input terminal, a current output terminal, and a control terminal, wherein the current input terminal of the second transistor is coupled to the current output terminal of the first transistor, a third transistor having a current input terminal, a current output terminal, and a control terminal, wherein the control terminal of the third transistor is coupled to the control terminal of the first transistor, a fourth transistor having a current input terminal, a current output terminal, and a control terminal, wherein control terminal of the fourth transistor is coupled to the control terminal of the second transistor and the current input terminal of the fourth transistor is coupled to the current output terminal of the third transistor, and a differential amplifier having a first input coupled to the current input terminal of the first transistor, a second input coupled to a node having an associated voltage approximately equal to the voltage on the current output terminal of the third transistor, and an output coupled to the control terminal of the second and fourth transistors.

DETAILED DESCRIPTION

FIG. 3illustrates two stages of an amplifier circuit300according to one embodiment of the present invention. Amplifier300includes a cascode input stage301and differential stage302implemented in a MOS technology. The MOS transistors shown include a gate control terminal, source terminal, and drain terminal. When the circuit is operating, supply voltages are applied to power supply terminals370and371. Cascode input stage301includes input PMOS transistors310and311. The gates of PMOS transistors310and311are coupled to input terminals350(“IN+”) and351(“IN−”), respectively. The sources of transistors310and311are both connected to a current source340. Accordingly, when a differential voltage is applied across the input terminals, a differential current will be generated in the drain terminals of the PMOS transistors.

The drain of transistor310is coupled to cascode node307formed between cascaded transistor313and cascode transistor315, and the drain of transistor311is coupled to cascode node306formed between cascaded NMOS transistors312and314. NMOS transistors312and313function as active loads for the cascode stage. The sources of transistors312and313are coupled to a low supply potential371(e.g., ground), and their gates are connected together. Additionally, a bias voltage Vb3is connected to the gates of transistors314and315. In one exemplary embodiment particularly suited for low voltage applications, the gates of NMOS transistors312and313may be connected to the drain of transistor314, and bias voltage Vb3may be set at a voltage level such that transistors314and315are in saturation and transistors312and313are on the border of the saturation-triode regions of operation (i.e., Vds is very close Vdsat).

Transistors312-315receive substantially equal currents at nodes304and305from a cascode current source comprising PMOS transistors316-319. The gates of PMOS transistors318and319are both connected to bias voltage Vb1, and the gates of PMOS transistors316and317are both connected to a bias voltage Vb2. The sources of transistors318and319are connected to power supply terminal370(“Vs”), and the drains of transistors318and319are connected to the sources of transistors316and317, respectively. The drains of transistors316and317are high impedance outputs of the cascode current source. If the dimensions of transistors318and316are equal to the dimensions of transistors319and317, respectively, then the cascode current source generates substantially equal currents from the drains of transistors316and317into nodes304and305. Accordingly, when the input terminals350and351are at equal voltages, the current through transistor312is equal to one-half the current through current source340plus the drain current of transistor316. Likewise, the current through transistor313is equal to one-half the current provided by current source340plus the drain current of transistor317. When a differential voltage is applied to the input terminals, a differential current is generated by transistors310and311into cascode nodes306and307. This differential current produces a change in voltage at node305, the output of the cascode input stage.

Those skilled in the art will recognized that transistors310-315are configured within amplifier circuit300in a “folded cascode” configuration. A folded cascode configuration is shown here only as one example of the present invention. Those skilled in the art will understand that the features and advantages of the present invention can be used in other amplifier circuit configurations.

Output node305of input stage301is coupled to an input of differential stage302.FIG. 3illustrates a differential stage according to one embodiment of the present invention. Differential stage302in amplifier300may include PMOS differential input transistors320and321and NMOS load transistors322and323. The gate of transistor320is coupled to node305for receiving the output of input stage301. Additionally, the gate of transistor321is coupled to the cascode node306. The sources of PMOS transistors320and321are both connected to current source341, and the drains of PMOS transistors320and321are connected to the drains of NMOS load transistors322and323, respectively. NMOS load transistors322and323are configured as a current mirror. Accordingly, the gates of transistors322and323are connected together and further connected to the drain of transistor322at node308. The output352of differential stage302may be taken from the drain of transistor323at node309.

As mentioned previously, low power supply voltage levels constrain the performance of amplifiers in a number of ways. In particular, there is a limited voltage budget that each stacked device may consume across intermediate nodes between the negative supply and positive supply. Low power supply voltage-induced constraints are compounded by the desire to increase the bias voltages on particular devices to minimize non-idealities such as noise and offsets. To address low power supply-induced limitations, one embodiment of the present invention utilizes an induced (i.e., designed-in) offset voltage in differential stage302to control the operating points of transistors in the preceding stages. For example, differential stage302may be designed to include an inherent offset voltage. In one embodiment, an offset voltage may be induced by intentionally mismatching the parameters of transistors in the gain stage (e.g., intentionally designing the gain stage transistors to have different physical characteristics). For example, transistors320and321may have different width to length ratios (“W/L”). Of course, it is to be understood that other techniques of inducing an offset may also be used. A resistive element could be coupled to the source of an input transistor, for example.

When amplifier300is in a closed loop configuration, the offset voltage will appear as a voltage difference between the gate voltages of input transistors320and321. This voltage may be used to set the operating point of transistors in the input stage. For example, in one embodiment, the input of transistor321is coupled to cascode node306to control the operating point of transistor315. The voltage on cascode node306is approximately equal to the voltage on cascode node307because both cascode nodes are a Vgs below bias voltage Vb3, and moreover, because the gates and sources of transistors312and313are connected together (i.e., the drain currents are equal). In this configuration, the drain to source voltage of cascode transistor315may be controlled by the offset of differential stage302. In other words, the induced voltage difference between the inputs of the differential stage302controls the voltage difference between the drain and source of cascode transistor315.

Other embodiments of the present invention may couple the input of transistor321to other nodes having associated voltages approximately equal to the source voltage of cascode transistor315. In particular, alternate embodiments where the input of transistor321is coupled to a voltage a Vgs below the voltage on the gate of transistor315may be used. For example, the gate of transistor321may be coupled to a bias circuit including a transistor having a gate coupled to the gate of cascode transistor315, wherein the Vgs of the bias circuit transistor is approximately equal to the Vgs of cascode transistor315. In one embodiment, the gate of transistor321may be coupled directly to the source of cascode transistor315.

In some embodiments of the present invention it may be desirable to use weak devices (i.e., devices where gmis intentionally lowered relative to other devices in the circuit) for transistors312and313in order to reduce deleterious noise and offset voltages. In such instances, the voltages at nodes306and307should be high enough to bias the devices into saturation. Therefore, it is desirable to minimize the bias values of other devices in the cascode stage to accommodate lower supply voltages. In one embodiment of the present invention, the differential stage is designed to generate an offset voltage across the inputs so that transistor315operates in saturation very close to the triode region (i.e., very close to Vdsat). Accordingly, the voltage drop between the drain and source of transistor315can be minimized, thereby further increasing the headroom of input stage301.

For example, in one embodiment using a 2.3V supply and weak transistors312and313, nodes306and307are biased at approximately 800 mV. Additionally, an offset voltage of approximately 200 mV is introduced in the inputs of the differential stage. Accordingly, when amplifier300is in a closed loop configuration, this voltage is established between the drain of transistor315and cascode node306. As a result, the drain to source voltage of transistor315is approximately 200 mV, which is very close to Vdsat (i.e., just above the edge of the saturation-triode boundary). Of course, while the above example illustrates the advantages of various aspects of the present invention, it is to be understood that other voltages and transistor configurations could also be used that embody the concepts described herein.

Features and advantages of the present invention include generating an offset voltage in a first stage that tracks changes in the characteristics of devices in prior stages, and using the offset voltage to tightly control the bias of devices in the prior stages as the characteristics of the devices change. For example, one particular advantage of amplifier300is that the offset voltage generated by differential stage302will track changes in Vdsat of transistor315caused by process variations or temperature variations. Generally, the variation in Vdsat with process and temperature would require that the voltage between the drain and source of transistor315be sufficiently large to ensure that the transistor does not inadvertently enter the triode region as a result of process or temperature changes. The extra voltage required to ensure that a device remains in saturation across changing process and temperature may be referred to as a margin voltage, or just margin. However, both Vdsat and the input offset voltage of input transistors320and321have a positive temperature coefficient. Additionally, Vdsat and the offset voltage will track across process. Therefore, because these parameters track, a differential stage offset voltage very close to the value of Vdsat can be introduced for controlling transistor315, and less margin is required. Accordingly, this technique translates into a larger headroom for the output of input stage301.

FIG. 4illustrates two stages of an amplifier circuit400according to another embodiment of the present invention. Amplifier400includes a differential stage402and output stage403. Differential stage402includes PMOS differential input transistors420and421and an active load comprising NMOS load transistors422and423. The gate of transistor420is coupled to input node450and the gate of transistor421is coupled to input node451. The sources of PMOS transistors420and421receive a differential stage bias current from current source441. Additionally, the drains of PMOS transistors420and421are connected to the drains of NMOS load transistors422and423, respectively. NMOS load transistors422and423are configured as a current mirror. Accordingly, the gates of transistors422and423are connected together and further connected to the drain of transistor422at node408. The output of differential stage402may be taken from the drain of transistor423at node409.

Embodiments of the present invention may include a differential stage402coupled to a common gate stage (or common base stage if implemented in bipolar) having an input impedance dependent on the differential stage output voltage. Together, the differential stage and common base stage operate to reduce the output impedance, and hence the gain, of the differential stage as the voltage on output node409approaches either the positive or negative supplies.

In one embodiment, output node409of differential stage402is coupled to a common gate stage comprising an NMOS transistor430. The input impedance of a common gate stage is approximately given by the following equation:
Rin=1/gm
On the other hand, gmis approximately given by the following equations:
gm(sat)=μoCox(W/L)(Vgs−Vth); and
gm(triode)==μoCox(W/L)Vds
When the voltage on output node409of differential stage402is at the lower supply, the input impedance of the common gate stage is low and dominates the output impedance of the differential stage402. The gain of differential stage402is approximately given by the following:
Av=GmRo
Where Gmis the total transconductance of the differential stage, and Rois the combined output impedance of the differential stage and the common gate stage. Accordingly, when the voltage on node409is near the negative supply, the composite gain is reduced.

As the voltage on output node409of differential stage402increases, gmof the common gate stage will decrease, and the input impedance of common gate stage430will increase. Consequently, as the voltage on output node409moves away from the negative supply, Rowill increase because the input impedance of the common gate stage increases. Therefore, the gain of differential stage402will increase. However, as the voltage on output node409approaches the positive supply, transistor421will enter the triode region of operation. Consequently, the output impedance of the differential stage will decrease, thereby reducing the gain of the differential stage at the positive supply.

The embodiment shown inFIG. 4illustrates one advantageous application of the above described technique. An output stage403including a common gate stage is coupled to receive the output of differential stage402. In the present embodiment, the output of differential stage402is coupled to the gate of NMOS output transistor432and to the source of common gate NMOS transistor430. The gate of transistor430is coupled to a bias voltage Vb4, and the drain is coupled to both the gate of PMOS output transistor431and bias current source442. In this configuration, the output of differential stage402is coupled to the gates of both PMOS transistor431and NMOS transistor432to generate an output at terminal452(“OUT”). When the differential stage output voltage decreases, the drain current of PMOS transistor431increases and the drain current of NMOS transistor432decreases. Accordingly, the voltage on output terminal452will increase. On the other hand, when the differential stage output voltage increases, the drain current of NMOS transistor432increases and the drain current of PMOS transistor431decreases. Accordingly, the voltage on output terminal452will decrease.

The technique discussed above is especially advantageous for low voltage supply applications because many prior low voltage circuits cannot drive the gates of the output devices maximally. For example, in a circuit which uses an NMOS source follower to drive the gate of the NMOS output transistor, the output transistor gate cannot rise above VCC-VGS. This severely constrains the current-carrying capability of the output device at low supply voltages. However, according to the embodiments of the present invention, the voltage at the input of NMOS transistor432can increase all the way to the supply voltage, and the transistor can thereby sink current more effectively.

Embodiments of the invention may include a first transistor in the active load that is sized to receive a first portion of the bias current from current source441, and a second transistor in the active load sized to receive a second portion of the bias current in addition to the bias current of the common base stage. For example, load transistors422and423may be dimensioned differently in order to enhance interoperability between differential stage402and output stage403. Each transistor422and423may have a drain current equal to one-half the current provided by current source441. However, transistor423may be dimensioned such that its drain current is equal to the combination of one-half the current from source441, and additionally, the bias current received from the source of common gate transistor430.

FIG. 5illustrates an amplifier circuit500that may incorporate the above described techniques according to another embodiment of the present invention. Amplifier500includes a cascode input stage501, differential stage502, and output stage503. Cascode input stage501includes input PMOS transistors510and511. The gates of PMOS transistors510and511are coupled to input terminals550(“IN+”) and551(“IN−”), respectively. The sources of transistors510and511are both connected to bias current source540. When a differential voltage is applied across the input terminals, a differential current will be generated into cascode nodes506and507. This current will result in an amplified output voltage at node505as a result of the action of NMOS transistors512-515and PMOS transistors516-519.

A first input of differential stage502is coupled to node505for receiving the output of cascode input stage501, and a second input of differential stage502may be coupled to cascode node506or any other node having a voltage approximately equal to the source voltage of cascode transistor515for controlling the bias of transistor515. Differential stage502may include an offset voltage for biasing transistor515very close to the saturation-triode region boundary. Differential stage502comprises differential input transistors520and521and NMOS load transistors522and523. The sources of PMOS transistors520and521are both connected to bias current source541, and the drains of PMOS transistors520and521are connected to the drains of NMOS load transistors522and523, respectively. The output of differential stage502may be taken from the drain of transistor523at node509.

Output stage503of amplifier500is coupled to receive the output of differential stage502. The output of differential stage502is coupled to the gate of NMOS output transistor532and to the source of NMOS transistor530, which is configured as a common gate stage. The gate of transistor530is coupled to a bias voltage Vb4, and the drain is coupled to both the gate of PMOS output transistor531and bias current source542. Finally, the drain terminals of both PMOS transistor531and NMOS transistor532are coupled to output terminal552.

Embodiments of amplifier500may also include compensation circuits such as feed forward circuits (“FF”)590and591. Feed forward circuit590may be coupled between the cascode stage output node505and the gate of PMOS transistor531. Feed forward circuit591may be coupled between cascode stage output node505and the output of gain stage502at node509. Feed forward circuits590and591may be included to stabilize amplifier500by allowing high frequency signal components to bypass delay elements in the circuit, thereby preserving phase margin.

Amplifier500is capable of providing high gain at low power supply voltages. Amplifier500also improves the amplifier's current sinking ability via NMOS transistor532over prior art techniques. For example, if a large negative differential input is applied to terminals550and551, the output of differential stage502will drive node509, and the gate of NMOS transistor532, toward the power supply terminal570(“Vs”). As the voltage on node509increases from the negative supply terminal, the gain of the differential pair will increase because the input impedance of transistor530will increase. As a result, the increase in composite gain of stages501and502will increase the gate drive to transistor532.

Moreover, as the differential input is further increased into the extreme range of operation, both the source and drain voltages of transistor521will become greater than the gate voltage of transistor521. Therefore, Vds approaches zero and transistor521will enter the deep triode region of operation. Accordingly, node509and the gate of transistor532will rise to a maximum voltage of:
V509—max=VS−VDSAT,
where VDSATis the minimum voltage drop of current source541, which may be the drain to source saturation voltage for a current carrying transistor in current source541. Additionally, the output of the cascode stage will rise to:
V505—max=VS−VDSAT−VGS,
where VDSATis again typically the drain to source saturation voltage for the current carrying transistor in current source541, and VGSis the gate to source voltage of transistor520. Therefore, at the extreme range of operation the gate of NMOS transistor532is driven by a source follower comprising PMOS transistor520and current source541. Accordingly, because output node505of cascode input stage501does not have to rise all the way to the power supply voltage Vs, the input stage retains more gain across a wider range of operation. At extreme voltage ranges, this additional gain can be coupled though source follower transistor520to drive the gate of NMOS transistor532. This results in an improved ability to sink currents at low power supply voltages.

FIG. 6illustrates an amplifier circuit600that may incorporate the above described techniques according to another embodiment of the present invention. Amplifier600also includes a cascode input stage601, differential stage602, and output stage603. Cascode input stage601includes input NMOS transistors610and611. The gates of NMOS transistors610and611are coupled to input terminals650(“IN+”) and651(“IN−”), respectively. The sources of transistors610and611are both connected to bias current source640. When a differential voltage is applied across the input terminals, a differential current will be generated into cascode nodes606and607. This current will result in an amplified output voltage at node605as a result of the action of PMOS transistors612-615and NMOS transistors616-619. Those skilled in the art will recognized that transistors610-615are configured within amplifier circuit600in a “folded cascode” configuration.

A first input of differential stage602is coupled to node605for receiving the output of cascode input stage601, and a second input of differential stage602is coupled to cascode node606for controlling the bias of transistor615. Differential stage602may include an offset voltage for biasing transistor615very close to the saturation-triode region boundary. Differential stage602comprises differential NMOS input transistors620and621and PMOS load transistors622and623. The sources of NMOS transistors620and621are both connected to bias current source641, and the drains of NMOS transistors620and621are connected to the drains of PMOS load transistors622and623, respectively. The output of differential stage602may be taken from the drain of transistor623at node609.

Output stage603of amplifier600is coupled to receive the output of differential stage602. The output of differential stage602is coupled to the gate of PMOS output transistor632and to the source of PMOS transistor630, which is configured as a common gate stage. The gate of transistor630is coupled to a bias voltage Vb4, and the drain is coupled to both the gate of NMOS output transistor631and bias current source642. Finally, the drain terminals of both NMOS transistor631and PMOS transistor632are coupled to output terminal652.

FIG. 7illustrates an amplifier circuit700that may incorporate the above described techniques according to another embodiment of the present invention. Amplifier700also includes a cascode input stage701, differential stage702, and output stage703. Cascode input stage701includes input PMOS transistors710and711. The gates of PMOS transistors710and711are coupled to input terminals750(“IN+”) and751(“IN−”), respectively. The sources of transistors710and711are both connected to bias current source740. When a differential voltage is applied across the input terminals, a differential current will be generated into cascode nodes706and707. This current will result in an amplified output voltage at node705as a result of the action of NMOS transistors712-715and PMOS transistors716-719. Those skilled in the art will recognized that transistors710-715are configured within amplifier circuit700in a “folded cascode” configuration.

A first input of differential stage702is coupled to node705for receiving the output of cascode input stage701, and a second input of differential stage702is coupled to cascode node704for controlling the bias of transistor717. Differential stage702may include an offset voltage for biasing transistor717very close to the saturation-triode region boundary. Differential stage702comprises differential NMOS input transistors720and721and PMOS load transistors722and723. The sources of NMOS transistors720and721are both connected to bias current source741, and the drains of NMOS transistors720and721are connected to the drains of PMOS load transistors722and723, respectively. The output of differential stage702may be taken from the drain of transistor723at node709.

Output stage703of amplifier700is coupled to receive the output of differential stage702. The output of differential stage702is coupled to the gate of PMOS output transistor732and to the source of PMOS transistor730, which is configured as a common gate stage. The gate of transistor730is coupled to a bias voltage Vb4, and the drain is coupled to both the gate of NMOS output transistor731and bias current source742. Finally, the drain terminals of both NMOS transistor731and PMOS transistor732are coupled to output terminal752.

FIG. 8illustrates an amplifier circuit800according to yet another embodiment of the present invention. Amplifier800includes a cascode input stage801, gain stage802, and output stage803. Cascode input stage801includes input PMOS transistors810and811and bias current source840. The gates of PMOS transistors810and811are coupled to input terminals850(“IN+”) and851(“IN−”), respectively, and the sources of transistors810and811are both connected to bias current source840. Cascode input stage801also includes NMOS transistors812-815and PMOS transistors816-819for generating an amplified output voltage at node805in response to a differential input voltage on terminals850and851. The drains of transistors810and811are coupled to cascode nodes807and806, respectively.

Gain stage802is coupled to node805to receive the output of cascode input stage801. Gain stage802includes first and second complementary differential stages for generating a differential output at nodes809A and809B. Gain stage802may also include an offset voltage for biasing transistor815very close to the saturation-triode region boundary. Additionally, amplifier800may further include a feed forward circuit for providing a portion of the signal from the output of cascode input stage801to output stage803.

The first differential stage comprises transistors820-823. The gate of PMOS transistor820is coupled to the cascode output node805, and the gate of PMOS transistor821is coupled to cascode node806. The sources of PMOS transistors820and821are both connected to bias current source841, and the drains of PMOS transistors820and821are connected to the drains of NMOS load transistors822and823, respectively. A first output of differential stage802is produced at node809A.

A second differential stage comprising transistors824-829is also included in gain stage802for providing a complementary output at node809B. The gates of PMOS transistors828and829are coupled to the cascode output node805and cascode node806, respectively. The sources of PMOS transistors828and829are coupled to bias current sources844and843, respectively. These transistors provide level shifting of the input signals received from cascode input stage801. The gates of NMOS transistors824and825are coupled to the sources of the level shift devices828and829for receiving the input signals to be amplified. The sources of transistors824and825are both coupled to bias current source842, and the drains of transistors824and825are coupled to an active load comprising PMOS load transistors826and827. A second output of gain stage802is produced at node809B.

In one embodiment, both the first and second differential stages include a designed-in offset voltage for setting the operating points of transistors in the cascode input stage. For example, the second differential stage may have an offset which matches the offset of the first differential stage. P-channel transistors828and829may be designed so that the current densities match the current densities of N-channel transistors820and821, respectively. In this way the offsets of the first and second differential stages are produced by the same type of devices, which may be laid out such that the geometries match (828with820, and829with821). Furthermore, as the offset of the first differential stage varies due to process and temperature variations, the offset of the second differential stage will track the first. The feature is beneficial because it minimizes variability in the quiescent current of the output stage as these parameters vary. In this topology, the first and second differential stages share responsibility for biasing the cascode transistor815.

As previously mentioned, amplifier800may also include a feed forward circuit for providing a portion of the signal from the output of cascode input stage801to the input of output stage803. The feed forward circuit includes PMOS transistor831, bias current source845, and feed forward capacitors860(“Cff2”) and861(“Cff1”). The gate of PMOS transistor831is coupled to the cascode output node805. Additionally, the source of PMOS transistor831is coupled to bias current source845so that the combination will act as a source follower. Feed forward capacitors860and861are coupled between the source of PMOS transistor831and the gates of output transistors832and833, respectively. The capacitance values of feed forward capacitors860and861may be selected to stabilize the circuit by bypassing delay elements in the circuit at high frequencies.

Output stage803of amplifier800is coupled to receive the outputs of the differential amplifiers in gain stage802. Also coupled to the outputs of the differential amplifiers are common gate devices830and834. Thus, the drain of transistor821is coupled to the gate of NMOS output transistor832, and the drain of transistor825is coupled to the gate of PMOS output transistor833. The gate of NMOS transistor830is coupled to a bias voltage Vb5, and the source of transistor830is coupled to the gate of NMOS output transistor832and to node809A. Similarly, the gate of PMOS transistor834is coupled to a bias voltage Vb4, and the source of transistor834is coupled to the gate of PMOS output transistor833and to node809B. Finally, the drain terminals of both PMOS transistor833and NMOS transistor832are coupled to output terminal852.

FIG. 9Aillustrates a current mirror900A that may be used in embodiments of the present invention. The performance of a current mirror may be improved by coupling the inputs of a differential amplifier901A to nodes of the current mirror, and thereby use the amplifier to control the behavior of the current mirrors transistors. Current mirror900A may be used as a low-voltage current mirror with high output impedance and improved input headroom. The current mirror900A illustrated inFIG. 9Amay be used in many applications. While current mirror900A may be beneficially used in embodiments of the amplifier circuits disclosed herein, current mirror900A is not limited to amplifier applications.

In one embodiment, current mirror900A includes a transistor902A having a source coupled to a negative supply voltage (e.g., ground) and a drain coupled to the source of a cascode transistor904A. Similarly, transistor903A has a source coupled to the negative supply and a drain coupled to the source of another cascode transistor905A. The gate of transistor902A is coupled to the gate of transistor903A, and the gate of transistor904A is coupled to the gate of transistor905A. The gates of transistors904A and905A are coupled to a bias voltage Vb3. A current source907A is coupled to the drain of transistor904A, and a load906A is coupled to the drain of transistor905A. Current mirror900A includes a differential amplifier901A having a first input991A coupled to the drain of transistor904A and a second input990A coupled to the source of transistor905A.

An offset voltage908A is included to control the voltage difference between the differential amplifier inputs990A and991A. The feedback action of differential amplifier901A maintains the first input node991A at an approximately fixed voltage above the second input node990A. The voltage difference between the input nodes990A and991A is equal to the designed-in offset voltage908A, which may be advantageously set to bias transistor904A on the edge of the saturation region of operation.

During operation, current mirror900A is coupled between a positive supply909A and a negative supply911A. Current from current source907A flows into the drain terminal of transistor904A and out of the source terminal. Current from the source terminal of transistor904A flows into the drain terminal of transistor902A. Current from the load906A flows into the drain terminal of transistor905A and out of the source terminal. Current from the source terminal of transistor905A flows into the drain of transistor903A. Amplifier901A is in a closed loop because the output is coupled to the control terminals of transistors902A and903A, which control the current in the mirror. Feedback action will maintain a voltage difference between the amplifier input terminals that is approximately equal to the designed-in offset voltage. Thus, embodiments of the present invention allow the current in transistors902A and903A to be controlled to maintain the cascode device904A on the edge of the saturation region of operation, thereby improving the input headroom of the circuit. In particular, the voltage at input node991A need not exceed 2VDSATplus a small margin.

Current mirror900A may be implemented in different technologies. While current mirror900A is shown inFIG. 9Aas comprising NMOS transistors, it is to be understood that opposite polarity PMOS devices could be substituted. Alternatively, current mirror900A may be implemented in bipolar by substituting NPN or PNP devices. In a bipolar implementation, base currents would advantageously cancel. Moreover, a bipolar implementation would have high accuracy and high output impedance together with wide output swing and improved input headroom.

FIGS. 9B and 9Cillustrate other embodiments of the current mirror of FIG.9A. Current mirror900B ofFIG. 9Billustrates the circuit for amplifier901A ofFIG. 9Aaccording to one embodiment of the present invention. The differential amplifier in current mirror900B includes a differential pair comprising transistors920B and921B and an active load comprising transistors922B and923B. The source terminals of differential transistors920B and921B are coupled together and to current source925B. In a MOS implementation, the offset voltage may be achieved by mismatching the width to length ratios of transistors920B and921B.

FIG. 9Cillustrates another embodiment of the current mirror circuit. The first input of the differential amplifier is coupled to the drain terminal of transistor904C and the second input of the differential amplifier is coupled to a node having an associated voltage approximately equal to the voltage on the source terminal of transistor905C. For example, in current mirror900C, the second input to the differential amplifier is coupled to a voltage generated by a bias circuit. The bias circuit includes transistors930C and931C and current source932C. Transistors930C and931C have gates coupled to the drain of transistor931C. The drain of transistor931C is coupled to current source932C and to the control terminals of transistors904C and905C. Consequently, the source of transistor931C is a Vgs below the control terminal of transistor905C, and has an associated voltage approximately equal to the voltage on the source terminal of transistor905C. Of course, other equivalent circuit configurations could be used to generate the voltage on the second input terminal.

Current mirror900C further illustrates another technique for generating the offset voltage in the differential amplifier. A predetermined offset voltage may be achieved by coupling a properly sized resistor924C to the source of transistor920C. Of course, for a bipolar implementation, a resistor would be coupled to the emitter of a differential input transistor.

FIG. 9Dillustrates an amplifier circuit900D utilizing the current mirror ofFIG. 9Aaccording to one embodiment of the present invention. Amplifier900D includes a cascode stage901, differential stage902, and output stage903. Cascode stage901, differential stage902, and output stage903are substantially the same as described for amplifier500ofFIG. 5, except that cascode stage901includes a current mirror as described inFIGS. 9A-Bincluding an amplifier comprising transistors960-963. The gate of PMOS transistor960is coupled to node904, and the gate of PMOS transistor961is coupled to cascode node907. The sources of transistors960and961are coupled to bias current source943, and the drains of transistors960and961are coupled to NMOS load transistors962and963, respectively. Transistors960and961may have different width to length ratios to create a designed-in offset voltage as described above. Amplifier transistors960-963maintain node904at a fixed voltage above node907. The voltage difference between node904and907is equal to the designed-in offset voltage. Amplifier900D may be configured so that transistors914and915have nominally equal Vds. To achieve this result, the designed-in offset in transistors920and921, which controls Vds of transistor915, should be matched with the designed-in offset in transistors960and961, which controls the Vds of transistor914. Matching offsets will control differential unbalance caused by Early Voltage effects of transistors914and915. Thus, the circuit will exhibit very low systemic input referred offset voltages.

FIG. 10illustrates an amplifier1000according to another embodiment of the present invention. Amplifier1000includes a folded cascode input stage (i.e., transistors1010-1019), differential stage (i.e., transistors1020-1023), common gate stage (i.e., transistor1030), and output transistors1031-1032, the operation of which was described for amplifier500of FIG.5. Amplifier1000illustrates biasing and bypass techniques according to one embodiment of the present invention. Biasing in amplifier1000is provided by current source1040and transistors1041,1042A-D,1043A-G,1044A-B,1045A-B,1046, and1047A-B, and1030A-B. Embodiments of the invention may include coupling the gate of transistor1021to cascode node1006,1007, or1008(i.e., the sources of transistors1014,1015, or1044A) because each of these nodes has an associated voltage approximately equal to the voltage on the source terminal of cascode transistor1015. In particular, these nodes are all a Vgs below the voltage on the gate of transistor1015. With regard to transistor1044A, this is evident because transistor1044A has a diode connected drain and gate coupled to the gate of cascode transistor1015.

Amplifier1000includes a feed forward circuit comprising transistor1090and capacitors C11091and C21092. Transistor1090and load transistor1043D are configured as a source follower that receives an input from the cascode stage output (node1005) and drive capacitors1091and1092. The source follower and capacitor1091are coupled to the cascode stage output and the output of common gate transistor1030. The source follower stage and capacitor1092are coupled to the cascode stage output and the output of the differential stage.

Amplifier1000further includes transistor1033, which may be included for clamping the gate of output transistor1031such that it cannot completely turn off. Moreover, resistor R11093, capacitor1094, resistor R21095may be coupled between the output of the cascode stage and output for additional stabilization. Finally, resistor R31096and C41097may also be included for compensating transistor1032. The combination of R1, R2, R3, C3and C4is called “Nested Miller Compensation” and is well known in the art.

FIG. 11illustrates an amplifier1100according to another embodiment of the present invention. Amplifier1100includes a folded cascode input stage (i.e., transistors1110-1119), differential stage (i.e., transistors1120-1123), common gate stage (i.e., transistor1130), and output transistors1131-1132, the operation of which was described for amplifier500of FIG.5. Amplifier1100illustrates techniques for fine tuning amplifier performance according to one embodiment of the present invention. When the output of amplifier1100swings from the positive supply toward the negative supply, PMOS output transistor1131must be shut off quickly as NMOS transistor1132begins to conduct current. If the current in transistor1131is not turned off fast, both transistors will be conducting current at the same time, leading to problematic “shoot through” currents. Consequently, transistors1133,1180-1184and1160-1162are included to charge node1195and turn off output transistor1131when the voltage at the output of the differential stage increases, signaling the activation of output transistor1132.

During steady state operation, current source1141is equal to the sum of the drain current in transistor1130and the source current in transistor1160. Transistor1180senses the drain current in transistor1130, which is a function of the voltage at the output of the differential stage. Transistor1184produces a scaled version of the current in transistor1180into node1185. Current mirror transistors1161and1162produce a scaled version of the source current in transistor1160. The scaled versions of the currents in transistors1130and1160are then summed at node1185. If the sum is less than a current threshold set by current source1141C, then the voltage on node1185increases. Consequently, NMOS transistor1133sources current into the gate of output transistor1131, acting in concert with current source1141to increase the gate voltage of transistor1131, thereby turning transistor1131off and reducing “shoot through” currents.

Another characteristic improved by amplifier1100relates to improving the high frequency gain when the output voltage of amplifier1100is near the positive supply. Transistors1134and1190-1192are provided to improve stability in such a situation. As the voltage on the output of amplifier1100increases toward the positive supply, the voltage on node1195is decreasing. As the voltage on node1195decreases, the gate-to-drain voltage of transistor1131becomes more negative, and transistor1131will enter the triode region of operation. PMOS transistor1134is designed to turn on as transistor1131enters the triode region. PMOS transistor1134turns on and begins to increase the current through transistors1191-1192, which reduces the current in transistor1190. Thus, the current from the differential stage is reduced as the output voltage increases by the action of transistors1134and1190-1192. Consequently, as the output voltage increases toward the positive supply, the bandwidth of the amplifier is reduced because gmdecreases as the current into the differential stage is reduced. Therefore, the high frequency gain is reduced when the voltage on the output of the amplifier is near the positive supply, thereby providing improved stability.

Having fully described alternative embodiments of the present invention, other equivalent or alternative techniques for providing high gain at low supply voltage levels according to the present invention will be apparent to those skilled in the art. For example, embodiments of the present invention may be implemented using different technologies, such as at least bipolar, MOS, or BiCMOS. Consequently, other transistor structures may be substituted for some or all of the MOS transistors shown above. In particular, bipolar transistors may be used. Bipolar transistors include a base terminal, emitter terminal, and collector terminal. The base is typically the input control terminal corresponding to the gate in MOS circuits as is well known in the art. In other embodiments, opposite polarity devices (i.e., N-type vs. P-type) may be substituted to arrive at equivalent circuits according to well-understood circuit principles. In yet other embodiments, particular transistors may be added or removed from the particular embodiments disclosed above to arrive at equivalent circuits that practice the concepts disclosed herein. These equivalents and alternatives along with the understood obvious changes and modifications are intended to be included within the scope of the present invention as defined by the following claims.