Chip arrangement, wafer arrangement and method of manufacturing the same

Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure.

TECHNICAL FIELD

Various embodiments relate generally to a chip arrangement, a wafer arrangement and a method of manufacturing the same.

BACKGROUND

Power semiconductor components can be encapsulated or packaged with an organic polymer material, press mass or a laminate on component level.

In some conventional approaches, a semiconductor component (device) is packaged with an inorganic or organic carrier material or a cover (lid) material, which is simultaneously used for passivation and hermetic sealing. However, the encapsulation using a polymer material may result in a high moisture reception and a coefficient of thermal expansion (CTE) which is not adjusted to the semiconductor device. This may cause reliability problems during operation.

The combination of various electrically active structure is realized by doping, re-distributing and patterning of one single silicon wafer.

FIG. 1shows a diagram100, in which a circuit110is realized in a leadframe package120having two separated semiconductor devices, e.g. an IGBT (insulated gate bipolar transistor)102and a diode104, which have been contacted with each other using conventional bonding techniques.

SUMMARY

Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure extending from the at least one contact of the second chip from the first chip side of the second chip through the second chip and through the first chip to the first chip side of the first chip.

DESCRIPTION

FIG. 2shows a diagram200illustrating a plurality of chip structure.

A diode wafer210may have a plurality of diodes therein, wherein two diodes are shown inFIG. 2. The diodes may be formed in a semiconductor substrate212, e.g. a silicon substrate, on which electrical contacts216of the diodes may be formed. The semiconductor substrate212may be covered with a layer of insulating material214, e.g. a silicon oxide layer214, to insulate the electrical contacts216from each other. The diode wafer210may be singularized into a plurality of diode chips.

An IGBT (insulated gate bipolar transistor) wafer220may have one or a plurality of IGBTs therein, wherein two IGBTs are shown inFIG. 2. The IGBTs may be formed in a semiconductor substrate222, e.g. a silicon substrate, on which electrical contacts of the IGBTs, e.g. gate electrodes and emitter electrodes, may be formed. Electrical contacts of the IGBTS, e.g. collector electrodes, may also be formed within the semiconductor substrate222, e.g. by doping. The semiconductor substrate222may be covered with a layer of insulating material224, e.g. a silicon oxide layer224, to insulate the gate electrodes and emitter electrodes from each other. The IGBT wafer220may be singularized into a plurality of IGBT chips.

A FET (field effect transistor) wafer230may have one or a plurality of FETs therein, wherein two FETs are shown inFIG. 2. The FETs may be formed in a semiconductor substrate232, e.g. a silicon substrate, on which electrical contacts of the FETs, e.g. gate electrodes and source electrodes, may be formed. Electrical contacts of the FETS, e.g. drain electrodes, may also be formed within the semiconductor substrate232, e.g. by doping. The semiconductor substrate232may be covered with a layer of insulating material234, e.g. a silicon oxide layer234, to insulate the gate electrodes and source electrodes from each other. The FET wafer230may be singularized into a plurality of FET chips.

According to various embodiments, a chip arrangement may be provided including two or more chips or wafers, e.g. the various chips or wafers shown inFIG. 2above.

FIG. 3shows a chip arrangement300according to various embodiments.

The chip arrangement300may include a first chip310and a second chip320. The first chip310may have a first chip (main) side312and a second chip (main) side314opposite the first chip (main) side312, and at least one contact316on its second chip (main) side314. The second chip320may have a first chip (main) side322and a second chip (main) side324opposite the first chip (main) side322, and at least one contact326on its first chip (main) side322. The second chip (main) side314of the first chip310and the second chip (main) side324of the second chip320may face each other.

The chip arrangement300may include a first electrically conductive structure332extending from the at least one contact316of the first chip310from the second chip side314of the first chip310through the first chip310to the first chip side312of the first chip310. The chip arrangement300may further include a second electrically conductive structure334extending from the at least one contact326of the second chip320from the first chip side322of the second chip320through the second chip320and through the first chip310to the first chip side312of the first chip310.

In various embodiments, the first electrically conductive structure332may extend through via holes through the first chip310, wherein the sidewalls of the via holes may be covered by an insulating layer. In various embodiments, the second electrically conductive structure334may extend through via holes through the first chip310and the second chip320, wherein the sidewalls of the via holes may be covered by an insulating layer.

A layer302of insulating material, e.g. a silicon oxide layer302may be arranged between the second side314of the first chip310and the second side324of the second chip320.

In various embodiments, at least one of the first chip310and the second chip320may include at least one electric circuit. In various embodiments, at least one of the first chip310and the second chip320may include at least one power semiconductor device. Examples of the power semiconductor devices may include but are not limited to power MOSFETs (metal oxide semiconductor field effect transistor), JFETs (junction field effect transistor), IGBTs (insulated gate bipolar transistor), power bipolar transistors, diodes, and the like.

In various embodiments, the first chip310may include a diode, e.g. a diode in the diode wafer210ofFIG. 2. In various embodiments, the second chip320may include a power transistor, such as an IGBT (e.g. an IGBT in the IGBT wafer220ofFIG. 2), or a power MOSFET (e.g. a MOSFET in the FET wafer230ofFIG. 2).

According to various embodiments, the chip arrangement300may be configured as a half bridge circuit, e.g. by electrically coupling the respective contacts of the first chip310and the second chip320accordingly to form a half bridge circuit.

According to various embodiments, the second chip side314of the first chip310and the second chip side324of the second chip320may be bonded to each other. In various embodiments, the second chip side314of the first chip310and the second chip side324of the second chip320may be bonded to each other by means of wafer bonding, e.g. by means of anodic bonding.

According to various embodiments, the chip arrangement300may further include a re-distribution layer (not shown) disposed over the first chip side312of the first chip310, wherein at least one of the second electrically conductive structure334and the at least one contact of the first chip310is electrically coupled to the re-distribution layer.

In various embodiments, the first chip310may further include at least one contact on its first chip side312. A third electrically conductive structure (not shown) may be disposed over the first chip side312of the first chip310.

In various embodiments as will be described with reference toFIG. 10below, the first chip310may be a power transistor, wherein its gate electrode and source electrode may be formed on its first chip side312, and a third electrically conductive structure may be disposed over the first chip side312for the gate electrode and source electrode.

According to various embodiments, the second chip320may include at least one further contact (not shown) on its second chip side324. The at least one contact316on the second chip side314of the first chip310and the at least one further contact on the second chip side324of the second chip320may be arranged relative to each other such that they physically contact each other.

In various embodiments, the chip arrangement300may further include a coupling structure (not shown) between the first chip310and the second chip320. The coupling structure may include a first structure side and a second structure side opposite the first structure side, and at least one contact on its first structure side and at least one further contact on its second structure side. The at least one contact on the first structure side may be electrically coupled to the at least one contact on the second chip side of the first chip310; and the at least one further contact on the second structure side may be electrically coupled to the at least one further contact on the second chip side of the second chip320.

In various embodiments, the at least one contact on the first structure side and the at least one further contact on the second structure side may be electrically coupled with each other via the coupling structure.

In various embodiments, the coupling structure may include at least one conductor track.

Various embodiments of the chip arrangement300described above will be illustrated in more detail below with reference to the figures.

The wafer arrangement400may include a first wafer410having a first wafer side412and a second wafer side414opposite the first wafer side412, and a plurality of first chips310. Each first chip310may include at least one contact316on the second wafer side414of the first wafer410. The first chips310may have the similar structure as inFIG. 3.

The wafer arrangement400may include a second wafer420having a first wafer side422and a second wafer side424opposite the first wafer side422, and a plurality of second chips320. Each second chip320may include at least one contact326on the first wafer side422of the second wafer420.

The second wafer side414of the first wafer410and the second wafer side424of the second wafer420may face each other.

The wafer arrangement400may further include a first electrically conductive structure332extending from the respective at least one contact316of the first chip310from the second wafer side414of the first wafer410through the first chip310to the first wafer side412of the first wafer410. The wafer arrangement400may further include a second electrically conductive structure334extending from the respective at least one contact326of the second chip320from the first wafer side422of the second wafer420through the second chip320and through the first chip310to the first wafer side412of the first wafer410.

The wafer arrangement400inFIG. 4shows two first chips310in the first wafer410and two second chips320in the second wafer420, but it is understood that various number (e.g., three, four, five, . . . etc.) of first chips and second chips may be included in the first wafer410and the second wafer420. The wafer arrangement400, after being singularized, may form individual chip arrangements, e.g. a plurality of chip arrangements300ofFIG. 3.

Various embodiments described with reference to the chip arrangement300ofFIG. 3above are analogously valid for the wafer arrangement400.

In various embodiments, a method of manufacturing a chip arrangement, e.g., the chip arrangement300ofFIG. 3, may include providing a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; providing a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; arranging the first chip and the second chip such that the second chip side of the first chip and the second chip side of the second chip are facing each other; forming a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and forming a second electrically conductive structure extending from the at least one contact of the second chip from the first chip side of the second chip through the second chip and through the first chip to the first chip side of the first chip.

In various embodiments, a method of manufacturing a wafer arrangement, e.g., the wafer arrangement400ofFIG. 4, may include providing a first wafer having a first wafer side and a second wafer side opposite the first wafer side and a plurality of first chips, each first chip including at least one contact on the second wafer side of the first wafer; providing a second wafer having a first wafer side and a second wafer side opposite the first wafer side and a plurality of second chips, each second chip having at least one contact on the first wafer side of the second wafer; arranging the first wafer and the second wafer such that the second wafer side of the first wafer and the second wafer side of the second wafer are facing each other; forming a first electrically conductive structure extending from the respective at least one contact of the first chip from the second wafer side of the first wafer through the first chip to the first wafer side of the first wafer; and forming a second electrically conductive structure extending from the respective at least one contact of the second chip from the first wafer side of the second chip through the second chip and through the first chip to the first wafer side of the first wafer.

FIGS. 5A to 5Ibelow illustrates various process stages for manufacturing a wafer arrangement or a chip arrangement according to various embodiments.

FIG. 5Ashows a diagram501, wherein a first wafer510and a second wafer520are provided.

The first wafer510may have a first wafer side512and a second wafer side514opposite the first wafer side512, and a plurality of first chips. Each first chip may include at least one contact516on the second wafer side514of the first wafer510.

The second wafer520may have a first wafer side522and a second wafer side524opposite the first wafer side522, and a plurality of second chips. Each second chip may include at least one contact526on the first wafer side522of the second wafer520.

In various embodiments, at least one of the first chips and the second chips may include at least one electric circuit. At least one of the first chips and the second chips may include at least one power semiconductor device. Examples of the power semiconductor devices may include but are not limited to power MOSFETs (metal oxide semiconductor field effect transistor), JFETs (junction field effect transistor), IGBTs (insulated gate bipolar transistor), power bipolar transistors, diodes, and the like.

In various embodiments, at least one of the first chips may include a diode, e.g. a diode in the diode wafer210ofFIG. 2. In various embodiments, at least one of the second chips may include a power transistor, such as an IGBT (e.g. an IGBT in the IGBT wafer220ofFIG. 2), or a power MOSFET (e.g. a MOSFET in the FET wafer230ofFIG. 2).

Each of the first wafer510and the second wafer520may be covered with a layer of insulating material. For example, a silicon oxide layer518may be provided at the second wafer side514of the first wafer510, and a silicon oxide layer528may be provided at the second wafer side524of the second wafer520, similar to the wafer structure210,220,230ofFIG. 2.

For illustrative purposes, in various embodiments ofFIGS. 5A to 5I, the first chips may be diode chips and the first wafer510may have the structure of the diode wafer210as shown inFIG. 2; the second chips may be IGBT chips and the second wafer520may have the structure of the IGBT wafer220as shown inFIG. 2. It is understood that each of the first wafer510and the second wafer520may be one of the diode wafer210, IGBT wafer220, or FET wafer230ofFIG. 2, or other types of wafer including other types of chips or electric circuit.

According to various embodiments, at least one second chip of the second chip520may include at least one further contact542,544on the second wafer side524of the second wafer520. In an example wherein the second chips are IGBT chips, the further contacts may include emitter contact542and gate contacts544.

FIG. 5Bshows a diagram502, in which the first wafer510and the second wafer520are arranged such that the second wafer side514of the first wafer510and the second wafer side524of the second wafer520face each other.

In various embodiments, the second wafer side514of the first wafer510and the second wafer side524of the second wafer520may be bonded to each other. In various embodiments, the second wafer side514of the first wafer510and the second wafer side524of the second wafer520may be bonded to each other by means of wafer bonding, e.g. by means of anodic bonding. In this manner, an active silicon wafer (e.g. the IGBT wafer520) may be anodic coupled with a doped silicon wafer (e.g. the diode wafer510), using the doped silicon wafer510as a carrier (e.g. an inactive carrier wafer) and encapsulation medium. Accordingly, the active wafer520is encapsulated and coupled with the inactive carrier wafer510. In various embodiments, metallic coupling between the first wafer510and the second wafer520may be provided, e.g. by means of diffusion soldering.

According to various embodiments, the at least one contact516on the second wafer side514of the first wafer510and the at least one further contact on the second wafer side524of the second wafer520, e.g. the emitter contacts542of the second IGBT chips, may be arranged relative to each other such that they physically contact each other. In various embodiments, the at least one contact516of the first wafer510may be electrically coupled with the at least one further contact542of the second wafer520by diffusion soldering of contact pads.

FIG. 5Cshows a diagram503, in which contact holes may be formed.

In various embodiments, contact holes546,548may be etched into the first wafer510using an etch process, such as an anisotropic etch process, e.g. Bosch process. An etch stop structure (not shown) may be provided on the first wafer510, e.g. on the first wafer side512of the first wafer510, e.g., by means of ion implantation.

The contact holes546,548may be formed as through holes or via holes through the first wafer510. In various embodiments, the contact holes546may be formed through the first wafer such that they are located on and contacting one or more of the contacts of the first wafer510and the second wafer520, e.g. the at least one contact516on the second wafer side514of the first wafer510, and/or the at least one further contact542,544on the second wafer side524of the second wafer520. In an illustrative embodiment, the contact holes546are formed on and contacting with the emitter contacts542and the gate contacts544of the second wafer520.

In various embodiments, contact holes546,548having different depth may be formed. For example, a first group of contact holes546may be formed as through holes or via holes through the first wafer510, and a second group of contact holes548may be formed through the first wafer510and at least part of the second wafer520. For example, the second group of contact holes548may be formed such that they extends into the second wafer520to contact with the at least one contact526(e.g. the collector contact526) at the first wafer side of the second wafer520. In various embodiments, the second group of contact holes548may be formed by forming a plurality of contact holes having a first depth, and providing an etch stop structure (e.g., by means of ion implantation) on the surface of the contact holes corresponding to the first group of contact holes546, and etching the remaining contact holes to a second depth to form the second group of contact holes548.

In various embodiments, at least one of the first wafer510and the second wafer520may have a thickness in the range from about 500 μm to about 1000 μm, e.g. in the range from about 600 μm to about 800 μm, e.g. in the range from about 700 μm to about 750 μm.

FIG. 5Dshows a diagram504, in which a sidewall insulation552is formed.

A layer of insulating material552, e.g. a layer of silicon oxide (SiO2), may be deposited at the sidewalls of the contact holes546,548for electrical isolation of the sidewalls. In various embodiments, the sidewall insulation552may be formed by means of a chemical vapor deposition (CVD), or by thermal oxidation of the silicon (e.g. the silicon wafer510), or by chemical isolation.

FIG. 5Eshows a diagram505, in which the first wafer510is thinned.

The thinning of the first wafer510may be carried out from the first wafer side512down to a desired thickness of the first wafer510, e.g. to a thickness of equal to or smaller than 100 μm. In various embodiments, the first wafer510may be thinned to the desired thickness, e.g. a thickness in the range from about 20 μm to about 80 μm, e.g. a thickness in the range from about 30 μm to about 60 μm, e.g. to a thickness in the range from about 40 μm to about 50 μm, etc.

In various embodiments, the first wafer510may be thinned before the contact holes546,548are etched inFIG. 5Cand/or before the sidewall isolation552are formed inFIG. 5D.

In various embodiments, the second wafer520may be thinned instead of the first wafer510, e.g. before the contact hole etch ofFIG. 5Cand/or before the side wall isolation ofFIG. 5D, or after the side wall isolation ofFIG. 5D.

FIG. 5Fshows a diagram506, in which metallic seeding of the first wafer and the sidewalls of contact holes546,548is carried out.

A seed layer554, e.g. a metallic seed layer, may be deposited and activated on the first wafer510, e.g. on the top surface of the first wafer510and the bottom surface of the contact holes546,548. In an embodiment, the seed layer554may or may not be deposited on the sidewalls of the contact holes546,548.

FIG. 5Gshows a diagram507, in which an electrically conductive structure556, e.g. a metallization layer, may be formed over the first wafer510. may be deposited on the top surface of the first wafer510and in the contact holes546,548.

In various embodiments, electrically conductive material556, e.g., metal or metal alloy, may be deposited onto the top surface of the first wafer510and in the contact holes546,548, e.g. through galvanic deposition, to form metallic contacts therein for electrical coupling of the chips within the first wafer510and the second wafer520.

FIG. 5Hshows a diagram508, in which thinning of the second wafer520is carried out.

The thinning of the second wafer520may be carried out from the first wafer side522, i.e. the back side of the second wafer520. The back side thinning of the second wafer520may be carried out down to a desired thickness of the second wafer520. e.g. to a thickness of equal to or smaller than 100 μm. In various embodiments, the second wafer520may be thinned to the desired thickness, e.g. a thickness in the range from about 20 μm to about 80 μm, e.g. a thickness in the range from about 30 μm to about 60 μm, e.g. to a thickness in the range from about 40 μm to about 50 μm, etc.

FIG. 5Ishows a diagram509, in which the metallization layer556on the top side surface of the first wafer510may be patterned and a metallization layer558may be deposited on the back side surface of the second wafer520.

In various embodiments, the metallization layer556on the top side surface of the first wafer510may be patterned, e.g. lithographically through a photolithography process, so as to form a first electrically conductive structure532and a second electrically conductive structure534.

The first electrically conductive structure532, formed by the first group of contact holes546and the conductive material deposited therein, may extend from the respective at least one contact516from the second wafer side514of the first wafer510through the first chip to the first wafer side512of the first wafer510. In an embodiment, the first electrically conductive structure532may extend from the at least one further contact544,542(e.g. the gate contact542and the source contact544of the IGBT chips) on the second wafer side524of the second wafer520through the first chip to the first wafer side512of the first wafer510. In an embodiment, the source contact544of the IGBT chips physically contact the at least one contact516of the diode chips on the second wafer side514of the first wafer510, and accordingly the first electrically conductive structure532may be electrically coupled to the contact516of the first wafer510through the further contact542of the second wafer520.

The second electrically conductive structure534, formed by the second group of contact holes548and the conductive material deposited therein, may extend from the respective at least one contact526of the second chip from the first wafer side522of the second wafer520through the second chip and through the first chip to the first wafer side512of the first wafer510.

A wafer arrangement600according to various embodiment described above is formed as shown inFIG. 5I.

FIG. 6shows a wafer arrangement600and a chip arrangement650according to various embodiments.

As shown inFIG. 6, the wafer arrangement600ofFIG. 5Iis further singularized through a singulation process to form individual chip arrangements650.

Each chip arrangement650may include a first chip610having a first chip side and a second chip side opposite the first chip side and at least one contact516on its second chip side; and a second chip620having a first chip side and a second chip side opposite the first chip side and at least one contact526on its first chip side; wherein the second chip side of the first chip610and the second chip side of the second chip620are facing each other. Each chip arrangement650may further include a first electrically conductive structure532extending from the at least one contact of the first chip610from the second chip side of the first chip610through the first chip610to the first chip side of the first chip610; and a second electrically conductive structure534extending from the at least one contact526of the second chip620from the first chip side of the second chip620through the second chip620and through the first chip610to the first chip side of the first chip610.

In an illustrative embodiment, the chip arrangement650may form a circuit110as shown inFIG. 1, including a diode chip and an IGBT chip. The first electrically conductive structure532and the second electrically conductive structure534are connected with the gate contact544, the emitter contact542and the collector contact526of the IGBT chip, respectively. The contact516may be the anode contact of the diode chip, which is electrically coupled with the emitter contact542of the IGBT chip; and the cathode contact (e.g. in the substrate of the first chip610) of the diode chip is electrically coupled with the collector contact526of the IGBT chip through the second electrically conductive structure534. In accordance with various embodiments, a diode circuit device may be combined with an IGBT circuit device by means of “encapsulation” using the wafer material (e.g. silicon).

According to various embodiments, the wafer arrangement600may further include a re-distribution layer (not shown) disposed over the first wafer side of the first wafer, wherein at least one of the second electrically conductive structure534and the at least one contact516of the first chip610is electrically coupled to the re-distribution layer. After singulation, the chip arrangement600may also include a re-distribution layer (not shown) disposed over the first chip side of the first chip610, wherein at least one of the second electrically conductive structure534and the at least one contact516of the first chip610is electrically coupled to the re-distribution layer

In various embodiments, the chip arrangement650may be further connected to a printed circuit board or a leadframe after the singulation process, or after deposition of a solderable surface (i.e. plating or finish) over the chip arrangement650. The leadframe may be a pre-structured leadframe or a post-structured leadframe. In various embodiments, a plurality of chip arrangements650, i.e. a plurality of singularized chips, may be attached on one or more leadframes.

In various embodiments, an isolating structure, e.g. an isolating foil or isolating adhesive (e.g. polymer matrix material), may be dispended on the chips, for example, on the chips of the chip arrangement650.

In various embodiments, an isolating structure may be disposed between the chip arrangement and the leadframe. For example, a plurality of through holes may be provided in the isolating structure which adheres the chip arrangement to the leadframe, to provide electrical coupling between the contact of the chip arrangement and the leadframe.

The chip arrangement650can be cooled from both sides. In various embodiments, one side of the chip arrangement650, e.g. the front side, may be cooled via a printed circuit board, which may optionally be provided with thermal vias, for example. The backside of the chip arrangement650, e.g. the backside of the IGBT chip620may be coupled to a cooling structure or cooling body, e.g. a heatsink plate.

FIGS. 7A to 7Cbelow illustrates various process stages for manufacturing a wafer arrangement or a chip arrangement according to various embodiments.

FIG. 7Ashows a diagram701, wherein a first wafer510and a second wafer520, e.g. the first wafer510and the second wafer520shown inFIG. 5A, are provided.

Similar to the embodiments ofFIG. 5A, the first wafer510may have a first wafer side512and a second wafer side514opposite the first wafer side512, and a plurality of first chips. Each first chip may include at least one contact516on the second wafer side514of the first wafer510. The second wafer520may have a first wafer side522and a second wafer side524opposite the first wafer side522, and a plurality of second chips. Each second chip may include at least one contact526on the first wafer side522of the second wafer520.

In various embodiments, at least one of the first chips and the second chips may include at least one electric circuit. At least one of the first chips and the second chips may include at least one power semiconductor device, such as a power MOSFET, a JFET, an IGBT, a power bipolar transistor, a diode, and the like.

For illustrative purposes, as shown inFIGS. 7A to 7C, the first chips may be diode chips and the first wafer510may have the structure of the diode wafer210as shown inFIG. 2; the second chips may be IGBT chips and the second wafer520may have the structure of the IGBT wafer220as shown inFIG. 2. It is understood that each of the first wafer510and the second wafer520may be one of the diode wafer210, IGBT wafer220, or FET wafer230ofFIG. 2, or other types of wafer including other types of chips or electric circuit.

According to various embodiments, at least one second chip of the second chip520may include at least one further contact542,544on the second wafer side524of the second wafer520. In an example wherein the second chips are IGBT chips, the further contacts may include emitter contact542and gate contacts544.

Different fromFIG. 5A, a coupling structure710(also referred to as a connector) is provided. The coupling structure may be arranged between the first wafer510and the second wafer520.

The coupling structure710may include a first structure side712and a second structure side714opposite the first structure side712, and at least one contact716on its first structure side714and at least one further contact718on its second structure side714.

In various embodiments, the at least one contact716on the first structure side712and the at least one further contact718on the second structure side714may be electrically coupled with each other via the coupling structure710, e.g. via through holes filled with electrically conductive material connecting the at least one contact716and the at least one further contact718.

In various embodiments, the coupling structure710may be an insulating layer embedded with at least one conductor track.

FIG. 7Bshows a diagram702, in which the first wafer510and the second wafer520are joined through the coupling structure710.

In various embodiments, the first wafer510and the second wafer520may be bonded to each other through the coupling structure710, for example, by bonding the coupling structure710using at least one of anodic bonding, diffusion soldering, solder connection, active metal brazing, or the like. In various embodiments, metallic coupling between the first wafer510and the coupling structure710and between the second wafer520and the coupling structure710may be provided, e.g. by means of diffusion soldering.

In various embodiments, the first wafer510and the second wafer520may be arranged such that the second wafer side514of the first wafer510and the second wafer side524of the second wafer520face each other, with the coupling structure710arranged inbetween. In various embodiments, the at least one contact716on the first structure side712of the coupling structure710may be electrically coupled to the at least one contact516on the second wafer side514of the first wafer510; and the at least one further contact718on the second structure side714of the coupling structure710may be electrically coupled to the at least one further contact542,544on the second wafer side524of the second wafer520.

In an illustrative embodiment, the contact516of the first wafer510may be electrically coupled to the further contact542(e.g. the emitter contact) of the second wafer520through the coupling structure710.

FIG. 7Cshows a diagram703, in which a thinning process and a metallization process may be carried out.

In various embodiments, at least one of the first wafer510and the second wafer520may be thinned to a desired thickness, e.g. to a thickness of equal to or smaller than 100 μm, e.g. a thickness in the range from about 20 μm to about 80 μm, e.g. a thickness in the range from about 30 μm to about 60 μm, e.g. to a thickness in the range from about 40 μm to about 50 μm, etc. The thinning of the first wafer510may be carried out from the first wafer side512of the first wafer510, and the thinning of the second wafer520may be carried out from the first wafer side522of the second wafer520.

In various embodiments, a respective electrically conductive layer720, e.g. a metal layer, may be formed over the first wafer side512of the first wafer510and the first wafer side522of the second wafer520. The electrically conductive layer720may be used for electrical coupling, and/or for cooling purposes.

The structure of a wafer arrangement800formed according to various embodiment is shown inFIG. 7C.

FIG. 8shows a wafer arrangement800and a chip arrangement850according to various embodiments.

As shown inFIG. 8, the wafer arrangement800ofFIG. 7Cis further singularized through a singulation process to form individual chip arrangements850.

Each chip arrangement850may include a first chip810having a first chip side and a second chip side opposite the first chip side and at least one contact516on its second chip side; and a second chip820having a first chip side and a second chip side opposite the first chip side and at least one contact526on its first chip side.

A coupling structure710(also referred to as a connector) described in various embodiments above may be arranged between the first chip810and the second wafer820, wherein the second chip side of the first chip810and the second chip side of the second chip820are facing each other. The contact516of the first chip810may be electrically coupled with the contact542of the second chip820through the coupling structure710.

In an illustrative embodiment, the chip arrangement850may form a circuit110as shown inFIG. 1, including a diode chip810and an IGBT chip820. The contact516may be the anode contact of the diode chip810, which is electrically coupled with the emitter contact542of the IGBT chip820through the coupling structure710. The terminal to the coupling structure710, e.g. to the gate contact544of the IGBT chip820, may be provided laterally at the lateral side of the coupling structure710.

In accordance with various embodiments, a diode circuit device may be combined with an IGBT circuit device by means of “encapsulation” using the wafer material (e.g. silicon).

In the chip arrangement850and the wafer arrangement800, the edge structures of the chips, e.g. the power semiconductor chips, may be shielded from the environment by the semiconductor material of the wafers810,820and by the isolating coupling structure710. In various embodiments, the conductor tracks in the coupling structure710may also be configured as shields, and thus the in-diffusion of impurities may be efficiently prevented. These impurities, which are in particular contained in the package materials or which may advance to the semiconductor top side due to delaminations, often result in a drift of edge structures, which makes it necessary to configure the chip arrangement in a more elaborate manner and in a wider and thus more expensive structure. The structure of the chip arrangement850of various embodiments, without package materials, may allow simpler and more insensitive semiconductor devices. The metallization of the front side and the back side of the wafer arrangement800having large areas may also simplify the Double Side Cooling.

In various embodiments, the chip arrangement850may be further connected to a printed circuit board or a leadframe. The leadframe may be a pre-structured leadframe or a post-structured leadframe. In various embodiments, a plurality of chip arrangements850, i.e. a plurality of singularized chips, may be attached on one or more leadframes.

An isolating structure, e.g. an isolating foil or isolating adhesive (e.g. polymer matrix material), may be dispended on the chips, for example, on the chips of the chip arrangement850.

In various embodiments, an isolating structure may be disposed between the chip arrangement and the leadframe. For example, a plurality of through holes may be provided in the isolating structure which adheres the chip arrangement to the leadframe, to provide electrical coupling between the contact of the chip arrangement and the leadframe.

The embodiments described with reference toFIGS. 5A-5I,FIG. 6,FIGS. 7A-7CandFIG. 8above combines a diode wafer/chip with an IGBT wafer/chip. In the following, various embodiments are described in which two wafers having power transistor chips are combined.

A first wafer910and a second wafer920are shown, wherein each wafer may include power semiconductor chips. Each wafer910,920may include transistor chips, e.g. power MOSFET chips.

The first wafer910may be used as low side transistors in a half bridge circuit, and is also referred to as a low side wafer. The second wafer920may be used as high side transistors in the half bridge circuit, and is also referred to as a high side wafer.

In various embodiments, each of the first and the second wafers910,920may have a plurality of MOSFETs therein, wherein two MOSFETs are shown in each wafer inFIG. 9. The MOSFETs may be formed in a semiconductor substrate902, e.g. a silicon substrate, on which electrical contacts of the MOSFETs, e.g. gate electrodes and source electrodes, may be formed. Electrical contacts of the MOSFETS, e.g. drain electrodes, may also be formed within the semiconductor substrate902, e.g. by doping. The semiconductor substrate902may be covered with a layer of insulating material904, e.g. a silicon oxide layer904, to insulate the gate electrodes and source electrodes from each other. The MOSFET wafer910,920may be singularized into a plurality of FET chips.

In various embodiments, the first MOSFET wafer910and the second MOSFET wafer920may be used to form a wafer arrangement according to various processes described inFIGS. 5A-5I, or according to various processes described inFIGS. 7A-7Cabove. The thus formed wafer arrangement may be singularized to form individual chip arrangement, e.g. according to the singulation ofFIG. 6orFIG. 8.

FIG. 10shows a wafer arrangement1000formed using the MOSFET wafer910,920ofFIG. 9according to various embodiments above.

The wafer arrangement1000is singularized to form a plurality of chip arrangement1050, wherein two chip arrangements1050are shown inFIG. 10.

The chip arrangement1050may include a first chip1010and a second chip1020. The first chip1010may have a first chip side (e.g. the top side inFIG. 10) and a second chip side (e.g. the bottom side inFIG. 10) opposite the first chip side, and at least one contact1012on its second chip side. The second chip1020may have a first chip side (e.g. the bottom side inFIG. 10) and a second chip side (e.g. the top side inFIG. 10) opposite the first chip side, and at least one contact1022on its first chip side. The second chip side of the first chip1010and the second chip side of the second chip1020may face each other.

In an embodiment, the first chip1010is a low side MOSFET chip, and the second chip1020is a high side MOSFET chip.

The chip arrangement1050may include a first electrically conductive structure1032extending from the at least one contact1012of the first chip1010from the second chip side of the first chip1010through the first chip1010to the first chip side of the first chip1010. The chip arrangement1050may further include a second electrically conductive structure1034extending from the at least one contact1022of the second chip1020from the first chip side of the second chip1020through the second chip1020and through the first chip1010to the first chip side of the first chip1010.

In various embodiments, the first electrically conductive structure1032may extend through via holes through the first chip1010, wherein the sidewalls of the via holes may be covered by an insulating layer. In various embodiments, the second electrically conductive structure1034may extend through via holes through the first chip1010and the second chip1020, wherein the sidewalls of the via holes may be covered by an insulating layer.

In various embodiments, the first chip1010may further include at least one contact on its top chip side. The at least one contact on its top chip side may include a gate contact1014and a source contact1016.

In various embodiment, a third electrically conductive structure1036may be disposed over the top chip side of the first chip1010. The third electrically conductive structure1036may be coupled to the gate contact10104and the source contact1016to form a low side gate terminal G-LS and a low side source terminal S-LS of the chip arrangement1050.

According to various embodiments, the second chip1020may include at least one further contact, e.g. a gate contact1024and a source contact1026, on its second chip side, i.e. the top chip side inFIG. 10. The drain contact1012on the bottom chip side of the first chip1010and the at least one further contact, e.g. the source contact1026, on the second chip side324of the second chip1020may be arranged relative to each other such that they physically contact each other.

In various embodiments, the first electrically conductive structure1032may be coupled with the drain contact1012of the low side chip1010and the source contact1026of the high side chip1020, to form a terminal for low side drain D-LS and high side source S-HS of the chip arrangement1050. In various embodiments, the first electrically conductive structure1032may be coupled with the gate contact1024of the high side chip1020, to form a high side gate terminal G-HS of the chip arrangement1050.

In various embodiments, the second electrically conductive structure1034may be coupled with the drain contact1022of the high side chip1020, to form a high side drain terminal D-HS of the chip arrangement1050.

According to various embodiments, the chip arrangement1050may be configured as a half bridge circuit, e.g. by electrically coupling the respective contacts of the low side chip1010and the high side chip1020accordingly to form a half bridge circuit.

A top view of the chip arrangement1050showing the respective terminals G-LS, S-LS, D-LS and S-HS, G-HS, D-HS described above is illustrated inFIG. 11.

FIG. 12shows a circuit diagram1200, wherein a half bridge circuit corresponding to the chip arrangement1050ofFIG. 10andFIG. 11is shown. The half bridge circuit may include a low side transistor1210, e.g. the low side chip1010ofFIG. 10, and a high side transistor1220, e.g. the high side chip1020ofFIG. 10, connected serially.

Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure extending from the at least one contact of the second chip from the first chip side of the second chip through the second chip and through the first chip to the first chip side of the first chip.

In various embodiments, the first electrically conductive structure may extend through via holes through the first chip, wherein the sidewalls of the via holes may be covered by an insulating layer. In various embodiments, the second electrically conductive structure may extend through via holes through the first chip and the second chip, wherein the sidewalls of the via holes may be covered by an insulating layer.

In various embodiments, at least one of the first chip and the second chip may include at least one electric circuit. At least one of the first chip and the second chip may include at least one power semiconductor device. Examples of the power semiconductor devices may include but are not limited to power MOSFETs (metal oxide semiconductor field effect transistor), JFETs (junction field effect transistor), IGBTs (insulated gate bipolar transistor), power bipolar transistors, diodes, and the like.

In various embodiments, the first chip may include a diode. In various embodiments, the second chip may include a power transistor, such as an IGBT, or a power MOSFET.

According to various embodiments, the second chip side of the first chip and the second chip side of the second chip may be bonded to each other. In various embodiments, the second chip side of the first chip and the second chip side of the second chip may be bonded to each other by means of wafer bonding, e.g. by means of anodic bonding.

According to various embodiments, the chip arrangement may further include a re-distribution layer disposed over the first chip side of the first chip, wherein at least one of the second electrically conductive structure and the at least one contact of the first chip is electrically coupled to the re-distribution layer.

In various embodiments, the first chip may further include at least one contact on its first chip side. In various embodiments, a third electrically conductive structure may be disposed over the first chip side of the first chip.

In an exemplary embodiment, the first chip may be a power transistor, wherein its gate electrode and source electrode may be formed on its first chip side, and a third electrically conductive structure may be disposed over the first chip side for electrical coupling with the gate electrode and source electrode.

According to various embodiments, the second chip may include at least one further contact on its second chip side. The at least one contact on the second chip side of the first chip and the at least one further contact on the second chip side of the second chip may be arranged relative to each other such that they physically contact each other.

In various embodiments, the chip arrangement may further include a coupling structure between the first chip and the second chip. The coupling structure may include a first structure side and a second structure side opposite the first structure side, and at least one contact on its first structure side and at least one further contact on its second structure side. The at least one contact on the first structure side may be electrically coupled to the at least one contact on the second chip side of the first chip; and the at least one further contact on the second structure side may be electrically coupled to the at least one further contact on the second chip side of the second chip.

In various embodiments, the at least one contact on the first structure side and the at least one further contact on the second structure side may be electrically coupled with each other via the coupling structure.

In various embodiments, the coupling structure may include at least one conductor track. In various embodiments, the coupling structure may include an isolating layer with at least one conductor track embedded therein.

According to various embodiments, the chip arrangement may be configured as a half bridge circuit, e.g. by electrically coupling the respective contacts of the first chip and the second chip accordingly to form a half bridge circuit.

Various embodiments provide a wafer arrangement. The wafer arrangement may include a first wafer having a first wafer side and a second wafer side opposite the first wafer side, and a plurality of first chips. Each first chip may include at least one contact on the second wafer side of the first wafer.

The wafer arrangement may include a second wafer having a first wafer side and a second wafer side opposite the first wafer side, and a plurality of second chips. Each second chip may include at least one contact on the first wafer side of the second wafer.

The second wafer side of the first wafer and the second wafer side of the second wafer may face each other.

The wafer arrangement may further include a first electrically conductive structure extending from the respective at least one contact of the first chip from the second wafer side of the first wafer through the first chip to the first wafer side of the first wafer. The wafer arrangement may further include a second electrically conductive structure extending from the respective at least one contact of the second chip from the first wafer side of the second wafer through the second chip and through the first chip to the first wafer side of the first wafer.

In various embodiments, the first electrically conductive structure may extend through via holes through the first wafer, wherein the sidewalls of the via holes may be covered by an insulating layer. In various embodiments, the second electrically conductive structure may extend through via holes through the first wafer and the second wafer, wherein the sidewalls of the via holes may be covered by an insulating layer.

In various embodiments, at least one of the plurality of first chips and the plurality of second chip may include at least one electric circuit. In various embodiments, at least one of the plurality of first chips and the plurality of second chips may include at least one power semiconductor device. Examples of the power semiconductor devices may include but are not limited to power MOSFETs (metal oxide semiconductor field effect transistor), JFETs (junction field effect transistor), IGBTs (insulated gate bipolar transistor), power bipolar transistors, diodes, and the like.

In various embodiments, at least one first chip may include a diode. In various embodiments, at least one second chip may include a power transistor, such as an IGBT, or a power MOSFET.

According to various embodiments, the second wafer side of the first wafer and the second wafer side of the second wafer may be bonded to each other. In various embodiments, the second wafer side of the first wafer and the second wafer side of the second wafer may be bonded to each other by means of wafer bonding, e.g. by means of anodic bonding.

According to various embodiments, the wafer arrangement may further include a re-distribution layer disposed over the first wafer side of the first wafer, wherein at least one of the second electrically conductive structure and the at least one contact of the respective first chip is electrically coupled to the re-distribution layer.

At least one first chip may further include at least one contact on the first wafer side of the first wafer. A third electrically conductive structure may be disposed over the first wafer side of the first wafer.

The first chip may be a power transistor, wherein its gate electrode and source electrode may be formed on the first wafer side of the first wafer, and a third electrically conductive structure may be disposed over the first wafer side of the first wafer for electrical coupling with the gate electrode and source electrode.

According to various embodiments, at least one second chip may include at least one further contact on the second wafer side of the second wafer. The at least one contact on the second wafer side of the first wafer and the at least one further contact on the second wafer side of the second wafer may be arranged relative to each other such that they physically contact each other.

In various embodiments, the wafer arrangement may further include a coupling structure between the first wafer and the second wafer. The coupling structure may include a first structure side and a second structure side opposite the first structure side, and at least one contact on its first structure side and at least one further contact on its second structure side. The at least one contact on the first structure side may be electrically coupled to the at least one contact on the second wafer side of the first wafer; and the at least one further contact on the second structure side may be electrically coupled to the at least one further contact on the second wafer side of the second wafer.

In various embodiments, the at least one contact on the first structure side and the at least one further contact on the second structure side may be electrically coupled with each other via the coupling structure.

In various embodiments, the coupling structure may include at least one conductor track. In various embodiments, the coupling structure may include an isolating layer with at least one conductor track embedded therein.

According to various embodiments, the wafer arrangement may be configured as a plurality of half bridge circuits, e.g. by electrically coupling the respective contacts of the respective first chip and the respective second chip accordingly to form the respective half bridge circuit.

Various embodiments provide a method of manufacturing a chip arrangement. The method may include providing a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; providing a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; arranging the first chip and the second chip such that the second chip side of the first chip and the second chip side of the second chip are facing each other; forming a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and forming a second electrically conductive structure extending from the at least one contact of the second chip from the first chip side of the second chip through the second chip and through the first chip to the first chip side of the first chip.

In various embodiments, the method may include bonding the second chip side of the first chip and the second chip side of the second chip to each other, e.g. by means of anodic bonding.

In various embodiments, the method may include disposing a third electrically conductive structure over the first chip side of the first chip, wherein the first chip includes at least one contact on its first chip side.

In various embodiments, the method may include forming a coupling structure between the first chip and the second chip, the coupling layer including a first structure side and a second structure side opposite the first structure side and at least one contact on its first structure side and at least one further contact on its second structure side. The second chip may include at least one further contact on its second chip side. The at least one contact on the first structure side may be electrically coupled to the at least one contact on the second chip side of the first chip; and the at least one further contact on the second structure side may be electrically coupled to the at least one further contact on the second chip side of the second chip.

Various embodiments provide a method of manufacturing a wafer arrangement. The method may include providing a first wafer having a first wafer side and a second wafer side opposite the first wafer side and a plurality of first chips, each first chip including at least one contact on the second wafer side of the first wafer; providing a second wafer having a first wafer side and a second wafer side opposite the first wafer side and a plurality of second chips, each second chip having at least one contact on the first wafer side of the second wafer; arranging the first wafer and the second wafer such that the second wafer side of the first wafer and the second wafer side of the second wafer are facing each other; forming a first electrically conductive structure extending from the respective at least one contact of the first chip from the second wafer side of the first wafer through the first chip to the first wafer side of the first wafer; and forming a second electrically conductive structure extending from the respective at least one contact of the second chip from the first wafer side of the second chip through the second chip and through the first chip to the first wafer side of the first wafer.