Systems and methods for a centralized command address input buffer

An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.

BACKGROUND

The present disclosure relates generally to memory devices and, more particularly, to memory devices implementing synchronous semiconductor memory techniques.

Generally, a computing system may include an electronic device that, in operation, communicates information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device implemented on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor, by means of command and/or address signals (CA signals). These CA signals may be supplied to a common bonding pad, for example, a pin, an external terminal, or the like.

In synchronous semiconductor memory, CA signals are provided to the memory device in synchronism with an external clock signal. In other words, the external clock signal and the CA signals are validated together with a change of a signal, such as a chip select signal, from, for example, a disabled state to an enabled state (e.g., logical low to logical high, or vice versa, based on logical components implemented in the memory device). In the memory device, these CA signals are latched by latching circuitry in response to an enabled latch control signal. A system controller may produce this latch control signal during a set-up time during the change of the chip select signal from the disabled state to the enabled state. Thus, delay circuitry may be provided to delay the arrival of the CA signals to the latch to match an arrival time of the enabled latch control signal from the system controller. However, this delay circuitry may consume an undesired amount of power while the memory device is unselected (e.g., disabled chip select signal), for example, due to power consumed in response to logical state changes of the CA signal transmitted through delay circuitry while the chip select signal is disabled.

DETAILED DESCRIPTION

Generally, a computing system may include electronic devices that, in operation, communicate information via electrical signals. For example, electronic devices in a computing system may include a processor communicatively coupled to memory. In this manner, the processor may communicate with memory to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor via issuing command and/or address (CA) signals to the memory. The CA signals facilitate access operations with respect to memory cell arrays included in a channel of the memory. For purposes of this disclosure, the CA signals should be understood to mean command signal(s), address signal(s), or both, command and address signal(s).

A channel of the memory may receive the CA signals at a common bonding pad, such as a pin, an external terminal, or the like. These CA signals are provided in synchronism with an external clock signal. The external clock signal and the CA signals are validated together in response to the enabling of a chip select (CS) signal, for example, by a memory controller enabling access to that memory device. To do this, logical states of the CA signals are latched by latching circuitry in response to a latch clocking signal that causes the latching to occur. However, this latching occurs in response to the enabling of the chip select signal, thus delay occurs between the enabling of the chip select signal and the timings of the latch clocking signal. To compensate, delay circuitry is provided between the common bonding pad receiving the CA signals and the latching circuitry. However, the delay circuitry may consume undesired amounts of power while the chip select signal is disabled and the memory device is not selected.

To improve memory power consumption, the present disclosure provides techniques for implementing circuitry in the memory device to reduce power consumed while providing the delay used to synchronize (“sync”) the received CA signals and the latching circuitry to perform memory operations. Through use of logic circuitry and additional delay circuitry, power consumption of the memory device during a disabled state may be reduced. More specifically, the logic circuitry may stop CA signals being transmitted to all of the delay circuitry enabling only a subset of delay circuitry to consume power while the memory device is disabled, for example, by securing a setup margin. Furthermore, the present disclosure provides techniques for adjusting driving capabilities of the input buffers, thus enabling a memory device to adjust for timing differences through input buffer design, in addition to delay circuitry, providing the additional benefit of design flexibility and improved power consumption.

In some embodiments, these power reducing techniques may be applied to a DIMM device having a DRAM that uses centralized input buffers to receive chip select signals. Implementing centralized input buffers may reduce a physical distance between a chip select signal path and a CA signal path, potentially reducing power used to drive signal values (e.g., logical high and/or logical low voltage levels). Furthermore, this described embodiment may secure a setup margin for CA signal gating by the chip select signal, meaning that a subset of the delay circuitry consumes power while the memory device is disabled. In addition, a clock signal may transmit through an improved transmission path having a direct path architecture, rather than through a clock tree coupling architecture, thereby minimizing a route of the clock path and/or simplifying a complexity of the clock path.

Turning now to the figures,FIG. 1is a simplified block diagram illustrating certain features of a memory device10included in an electronic, or semiconductor, device. In some embodiments, the memory device10may be disposed in (physically integrated into or otherwise connected to) a host device or otherwise coupled to a host device. The host device may include any one of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, and the like. The host device may also be a network node, such as a router, a server, and/or a client (e.g., one of the previously-described types of computers). The host device may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. It is noted that the terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.

The host device may, thus, be a processor-based device, which may include a processor, such as a microprocessor, that controls the processing of system functions and requests in the host device. Further, any host processor may comprise a plurality of processors that share system control. The host processor may be coupled directly or indirectly to additional system elements of the host device, such that the host processor controls the operation of the host device by executing instructions that may be stored within the host device or external to the host device.

In some embodiments, the electronic device may include a DDR5 (Double Data Rate 5) SDRAM (synchronous dynamic random access memory) integrated on a semiconductor chip, a LPDDR4 (Low Power Double Data Rate 4) type DRAM (dynamic random access memory) integrated on a single semiconductor chip, and the like. Each electronic device is provided with a memory device10coupled to an external terminal. It should be understood that these external terminals may be bonding pads, inputs, pins, terminals, and the like, but are referred to as pads for ease of discussion herein. The memory device10may facilitate read and/or write operations based at least in part on a CA signal and/or external clock signals (Clk and ClkF) supplied from a processing core of the electronic device.

The CA signals and the external clock signals may be supplied to CA pads16and clock pads18of the electronic device, for example, via a CA bus and a clock bus, or any suitable communicative coupling from a controller or host processor. The CA signals and the external clock signals are supplied to the memory device10, thereby facilitating access operations with respect to memory cell arrays included in the memory device10. In addition, the memory device10may receive additional signals, such as chip select (CS) signals, from a controller, and these signals may be individually supplied to one or more memory devices10of the electronic device. As depicted, the memory device10receives a chip select signal at a chip select pad20. The chip select signal may enable the memory device10for memory operations.

Memory device data (DQ) may be read from or written to the memory device10at data pads24via a communicative coupling. In some embodiments, a memory device10may not permit both reading and writing actions, such as in the case of a read only memory (ROM) based electronic device.

A memory device10may include one or more memory cell arrays26(or memory banks BANK-0to Bank-7), which each respectively may include word lines (WL) and bit lines (BL, inverse BL as BLB). A row decoder/driver28may select word lines, while a column decoder/driver30may select bit lines. The bit lines may be paired and coupled to a sense amplifier32(SA) of a memory cell array26. The sense amplifier32may amplify a voltage difference generated between the bit lines BL and BLB. The sense amplifier32may also supply read data based at least in part on the voltage difference generated between the bit lines BL and BLB to complementary local input/output lines (LIOT/B), where the local input/output line may represent a pair of line (e.g., normal and inverted lines). The read data supplied to the local input/output lines may be transferred to complementary main input/output lines (MIOT/B) via a switch circuit (TG)34. The read data on the main input/output lines may be converted to single ended signals and transmitted to a data input/output circuit36via a read/write amplifier38(RW AMP) that acts to translate electrical signal values (e.g., voltage levels) between values interpretable at the pads and values interpretable by the internal memory cell array26.

As described previously, the memory device10may include the CA pads16, the clock pads18, the data pads24, and one or more chip select pads20. The memory device10may also include a voltage pad40to receive a first amount of voltage and a voltage pad42to receive a second amount of voltage, for example, the first and second amounts of voltage corresponding to logical high and low voltage values (VDD and VSS), respectively. The CA signals are received at the CA pads16and may be transmitted to a CA input circuitry (CA INPUT CIRCUITRY)44. The memory device10may include any suitable number of CA pads16, and as depicted, the memory device10includes m-number of CA pads16.

As previously described, the CA signals may include address signals and command signals. The address signals may transmit to an address decoder46and the command signals may transmit to a command decoder48. The address decoder46may supply row addresses to a row decoder/driver28and column addresses to a column decoder/driver30. The command decoder48may generate internal commands by decoding the command signals, and may transmit the internal commands to an internal control signal generator50. For example, the command decoder48may generate active signals, read signals, write signals, and the like to transmit to the internal control signal generator50. In response to the output from the command decoder48the internal control signal generator50may enable and/or disable a variety of control signals to operate memory device10circuitry, for example, mode registers, delay circuitry, reset control circuitry, the column decoder/driver30, and the row decoder/driver28, and the like, to perform operations according to the internal commands, such as resetting operations, reading operations, and/or writing operations. For example, in response to an activate command, the command decoder48and the internal control signal generator50may operate to enable a word line responsive to a row address transmitted to the memory device10. The CA input circuitry44, the address decoder46, the command decoder48, the column decoder/driver30, and the row decoder/driver28may constitute a CA control circuit and may access the memory cell array26.

The external clock signals may transmit to the memory device10at clock pads18. The external clock signal Clk and the external clock signal ClkF may be mutually complementary signals (e.g., ClkF is inverse of Clk), and may both be supplied to a clock input circuitry and internal clock generator, herein referred to as clock input circuitry52. The clock input circuitry52may generate one or more internal clock signals, such as a latch clocking signal (Latch Clk) used as a timing signal that defines operation of one or more latching circuits of the memory device10. The clock input circuitry52may also generate various other clocking signals, such as a phase-controller internal clock signal. In some embodiments, the clock input circuitry52may include clock distribution circuitry and/or delay locked loop (DLL) circuitry, where data associated with the data input/output circuit36is used to determine output timing of the read data (DQ). As depicted, the clock used to time read/written data (DQ) at the data input/output circuit36is a data strobe (DQS) signal, which may be accessed at data strobe pad54. In addition, the data input/output circuit36may reference a data high voltage (VDDR) via voltage pad60and/or a data low voltage (VSSQ) via voltage pad62to facilitate data transfer.

The voltage pad40and the voltage pad42may receive power-source potentials for a system high voltage (VDD) and for a system low voltage (VSS). The power-source potentials may be supplied to power circuitry56. The power circuitry56generates various internal potentials based at least in part on the power-source potentials. The internal potentials may transmit to the row decoder28, the sense amplifiers32, and the like to facilitate operation of the memory device10. Furthermore, the voltage pad40and the voltage pad42may operatively couple to a power-on detector to determine if electrical signals (e.g., current) are flowing at the voltage pad40and/or the voltage pad42. In response to this determination, a memory device10may change operation, for example, may act to reset its own circuitry to prepare for a next memory operation.

In addition, the chip select pad20may receive a chip select signal to activate the memory device10for memory operations. The chip select signal transmits from the chip select pad20to a chip select input circuitry58(CS INPUT CIRCUITRY). The chip select input circuitry58includes a variety of circuitry to enable the CA input circuitry44to permit transmission of CA signals into the memory device10.

The CA input circuitry44may also include delay circuitry and latching circuitry, for example, to enable the external clock signal and the CA signals to validate together on the same rising and/or falling edge. In response to the enabling of a chip select signal, the chip select signal may act to activate combinational logic circuitry such that the CA signals are permitted to transmit from a first delay circuit to a second delay circuit. By utilizing the chip select signal to mediate transmission of the CA signals from the CA input circuitry44, the memory device10consumes less power while continuing to provide the same delay to cause proper latching of the CA signals. Thus, the memory device10power consumption improves while the CA signals are delayed to cause timing of the CA signal data to align with the latch clocking signal (e.g., the latch pulse to operate the latch), enabling the latching circuitry to store the actual data of the CA signal.

To help illustrate,FIG. 2depicts an example of CA input circuitry44, chip select input circuitry58, and clock input circuitry52. As discussed above, a delay time between each CA signal received and the activating edge of the latch clocking signal (e.g., a rising edge) may correspond to any suitable time duration, in particular, a set-up time. For a particular embodiment, the set-up time is the duration of time between the change of the chip select signal from disabled to enabled and the activating edge of the latch clocking signal—that is, the edge of the latch clocking signal that permits latching circuitry to latch a data value (e.g., a rising edge or a falling edge). It should be appreciated that the depicted circuitry is merely intended to be illustrative and not limiting. For example, any number of delay-causing elements may be used in the CA input circuitry44to cause a variety of delay lengths to input CA signals to match a variety of set-up times or time durations.

As depicted, the CA input circuitry44may include one or more CA input buffers120(CA IB), one or more delay blocks122(Delay-1(D1)) (e.g., delay-causing element), one or more logic gates124, one or more delay blocks126(Delay-2(D2)), and one or more latches128, where the one or more latches128may be included in output circuitry of the memory device10and/or of the CA input circuitry44to manage transmission of the CA input signal to the rest of the memory device10. Each of the CA pads16are operably coupled to a respective CA input buffer120. Upon receiving one or more CA signals at CA pad16, the CA signals transmit to respective CA input buffers120. From the CA input buffer120, the CA signals transmit to delay block122. It is noted that the delay circuitry between each CA input buffer120and latches128is divided into two portions included in two separate signal propagation paths separated by the logic gate124, where the first signal propagation path has a first delay value and the second signal propagation path has a second delay value based on the total timing delay caused by the components of the separate paths. As illustrated, the delay block122is an inverting logic gate that causes a first time delay smaller than a second time delay caused by the delay block126. For the purposes of this disclosure, the delay block122is shown as having one inverting logic gate and the delay block126is shown as having two inverting logic gates. It should be understood, however, that any number of inverting logic gates and/or delay-causing circuitry may be used to delay the CA signals to cause any variety of delays including the case where the delay block122causes a delay shorter than the delay caused by the delay block126.

The logic gate124is shown as a NAND gate with a first input receiving the output from the delay block122and a second input receiving a control signal from the chip select input circuitry58. When the control signal is disabled, the NAND gate is closed to stop the delay block122output from being transmitted to the delay block126. When the control signal is enabled, the NAND gate is open and permits the delay block122output to be transmitted to the delay block126input. Accordingly, the delay block122responds to changes in voltage levels of the CA signal (e.g., data values, logic levels), and thus the delay block122consumes power while the control signal is disabled. More importantly, because the output from the delay block122is stopped from being transmitted to the delay block126, the delay block126does not consume a substantial, or significant, amount of power while the control signal is disabled (e.g., while the memory device10is not selected and inactive).

In some embodiments, the logic gate124is to be opened prior to the logic gate124receiving the CA signal. In these embodiments, a chip select input buffer130(CS IB) that receives the chip select signal is selected to have a stronger and/or larger driving capability than the CA input buffer120. Thus, the logic gate124receives the enabled control signal before the CA signal. It is noted that in some instances, the CA input buffer120provides a delay to the CA signal such that delay block122may be designed to provide no delay because the CA input buffer120provides sufficient delay.

In addition the chip select input circuitry58may include a pulse extender132and a logic gate134to create the control signal from the chip select signal. The pulse extender132may be any suitable circuitry to permit a state of the chip select signal to be extended. The pulse extender132may extend the duration of an enabled chip select signal to cause the latches128to be enabled for enough time to store data of the CA signals in response to the latch clocking signal (LATCH CLK). In this embodiment, the logic gate134is shown as an OR gate. Furthermore, as depicted, the clock input circuitry52may include a clock input buffer136and clock distribution circuitry138. These circuits are used to generate various internal clock signals, including the latch clocking signal, based at least in part on the clock signal received at clock pads18. The internal clock signals are used in data read and write operations, as discussed earlier.

To elaborate further on the operation of CA input circuitry44, chip select input circuitry58, and clock input circuitry52,FIG. 3depicts a timing diagram150including various memory device10signals and arrows indicating a progression of overall delay experienced by the various memory device10signals. It should be understood thatFIG. 3is merely intended to be illustrative and not limiting—for example more or less signals may be used to operate the CA input circuitry44, the chip select input circuitry58, and/or the clock input circuitry52.

As illustrated, the timing diagram150includes an external clock signal152(EXT. CLK), a chip select signal154(CS), a CA signal156A (CA), a chip select input buffer output signal158(CS IB_OUT), an OR gate output signal160(OR_OUT), a CA input buffer output signal156B (CA IN_OUT), a NAND gate input signal156C (NAND_IN), a NAND gate output signal156D (NAND_OUT), a latch input signal156E (LATCH_IN), and a latch clocking signal170(LATCH CLK). The external clock signal152, the chip select signal154, and the CA signal156A may be provided to the memory device10from an external device, for example, an external memory controller, to the clock pads18, the CA pads16, and the chip select pad20.

To elaborate, the external clock signal152may be a periodic signal received by the memory device10. The chip select signal154and the CA signal156A are provided to the memory device10before a next rising edge of the external clock signal152, where the next rising edge is set to occur a time duration (TC) after the enabled chip select signal154. The duration of time between the enabling of the chip select signal154(T1) and the enabling of the LATCH CLK signal170(T2) corresponds to a set-up time (TSU), and thus, the CA signal156A data172A (VALID) arrival to the latch128is delayed (e.g., data172E) an appropriate amount of time (T3) for correct latching. As depicted, the data172A, through the various circuits of the CA input circuitry44, is delayed to become the data172E. It should be appreciated that the CA signal156A data172A, the CA IN_OUT signal156B data172B, the NAND_IN signal156C data172C, the NAND_OUT signal156D data172D, and the LATCH_IN signal156E data172E are the same received CA signal156A (having the data172A) but with each iteration of delay added, the CA signal156A becomes the LATCH_IN signal156E. The timing delay progression of the CA signal156A is shown by arrows173.

Referring toFIG. 3in tandem withFIG. 2, the CA input circuitry44may receive the CA signal156A at CA pad16. From the CA pad16, the CA signal156A transmits to the CA input buffer120, and transmits from the CA input buffer120as the CA IN_OUT signal156B, where the beginning of the data172B is delayed a time duration174(CAM D), as indicated by arrow173B. The CA IN_OUT signal156B transmits through the delay block122and to the logic gate124. After transmitting through the delay block122, the CA IN_OUT signal156B becomes the NAND_IN signal156C, where the beginning of the data172C is delayed a time duration176(D1_D) from the previous beginning of the data172B, indicated by arrow173C. Upon transmission through the logic gate124(e.g., permitted by the chip select signal154and the CS IB_OUT signal158activating, or opening, the logic gate124before reception of the NAND_IN signal156C), the NAND_IN signal156C becomes the NAND_OUT signal156D and may be delayed a negligible amount by the logic gate124, indicated by arrow173D. The NAND_OUT signal156D may be transmitted through delay block126thus experiencing a third delay. Upon the NAND_OUT signal156D reaching the latch128input, the signal is delayed by a time duration178and becomes the LATCH_IN signal156E with data172E (e.g., delayed data172A), indicated by arrow173E. Thus, the data172E is delayed to the point where the LATCH CLK signal170captures its true value by activating the latch128at T2occurring at the middle of the data172E transmission.

In addition, the chip select input circuitry58receives the chip select signal154at the chip select pad20, and the chip selected signal154is transmitted to the chip select input buffer130. Upon transmission from the chip select input buffer130, the chip select signal154transmits to the logic gate134(e.g. an OR gate), the pulse extender132, and the clock distribution circuitry138to activate the memory device10for use in memory operations. The pulse extender132, in combination with the logic gate134, operates to create an enabled signal for a duration of time longer than the enabled signal of the chip select signal154, where this enabled signal may be the OR_OUT signal160. The duration of time that the chip select signal154is extended may equal a total time used to latch the CA signal156data172in the latches128(e.g., equal to the delay caused by the delay block122, the delay block126, the CA input buffer120, the logic gate124, and transmission between components). The chip select signal154may be extended to keep components of the memory device10in operation. For example, the clock distribution circuitry138may be enabled during the memory device10operation to create internal clock signals used to perform operations of the memory device10.

To better explain how a chip select input buffer130may have a stronger driving ability than a CA input buffer120,FIG. 4depicts an example embodiment of an input buffer200having an inverting logic gate204and one or more transistors202. It should be appreciated that the input buffer200is merely intended to be illustrative and not limiting. For example, an input buffer may include a variety of circuitry and/or switching elements capable of activating in response to one or more control signals.

As depicted, the input buffer200is a parallel p-type (p-channel) and n-type (n-channel) metal-oxide-semiconductor field-effect transistor (MOSFET) differential amplifier of an inverting type. It is to be noted that a transistor with a circle at a gate represents a p-type (p-channel) MOSFET and a transistor without a circle at a gate represents an n-type (n-channel) MOSFET. A chip select input buffer130may have a similar structure to a CA input buffer120, where both may follow layouts and configurations depicted with the input buffer200. However, the chip select input buffer130may use transistors202(M1202A, M2202B, M3202C, M4202D) larger in size than those same transistors202used in the CA input buffer120. By making the transistors202larger in the chip select input buffer130, the chip select input buffer130may have an increased driving ability compared to the CA input buffer120.

Elaborating on operation of the input buffer200, an input signal (IN), for example, the chip select signal154and/or the CA signal156A, is received at a pad205. After transmission through the input buffer200, the input signal is amplified and delayed for a particular amount of time to comply with circuitry propagation delays. Enable signals (EN, ENF) received at control lines206and208may activate transistors202, causing buffering of the input signal to occur. The input buffer200may amplify the input signal based at least in part on the voltage difference between the input signal (IN) and a reference voltage (Vr). Prior to outputting at output node210, the amplified and/or delayed input signal may be transmitted through the inverting logic gate204. Thus, an amplified, delayed, and/or inverted input signal may be transmitted from the input buffer200from output node210. In operation, this output signal may be transmitted to the delay blocks122from CA input buffer120, or to the logic gate134and/or the pulse extender132from the chip select input buffer130.

These described techniques may be implemented in a variety of memory devices.FIG. 5depicts an additional embodiment of the memory device10, such as a DRAM device, a memory device10A including the CA input circuitry44, the chip select input buffer130, and the clock input circuitry52. It should be appreciated that the depicted circuitry is merely intended to be illustrative and not limiting. For example, any number of delay-causing elements may be used in the CA input circuitry44to cause a variety of delay lengths to input CA signals to match a variety of set-up times or time durations.

As highlighted in the depicted embodiment of the memory device10A, the CA input buffers120may be disposed in a centralized location, or a centrally-situated location, on the memory device10A, as opposed to disposed in a distributed layout as shown inFIG. 2, wherein the CA input buffers120are located near the CA pads16. Using a centralized location for the CA input buffers120may minimize, or relatively decrease, a physical distance between the chip select input buffer130and the CA input buffers120. This minimized physical distance may reduce power used by the memory device10A, for example, because generally weaker signals may be used to transmit the same data than the signals carrying data over longer distances. Furthermore, using a higher powered input buffer200(e.g., an input buffer200with larger transistors) for the chip select input buffer130may facilitate in boosting relative speeds of the chip select input buffer130when compared to the CA input buffers120. Increasing the relative speed of the chip select input buffer130may help to expand a setup margin for command and/or address gating.

ViewingFIG. 5in conjunction with signals described with reference toFIG. 3, to operate the depicted portion of the memory device10A, one or more CA signals156A are respectively received at CA pads16. As a reminder, these CA signals156A are latched by the latches128in response to an enabled LATCH CLK signal170. A system controller, such as clock input circuitry52, may generate this latch control signal during a set-up time following the change of the chip select signal (e.g., chip select signal154) from a disabled state to an enabled state. Thus, delay circuitry, such as delay blocks122and delay blocks126, may be used to delay the arrival of the CA signals156A to the latches128to match an arrival time of the enabled latch control signal from the system controller. From the CA pads16, the CA signals156A transmit to CA input buffers120. Because each CA pad16respectively couples to a CA input buffer120, a number of the CA pads16equals a number of centralized CA input buffer120, such that a CA pad16A couples to a CA input buffer120A while not coupling to a CA input buffer120B. The CA input buffer120may amplify and/or delay the CA signals156A and may transmit the CA IN_OUT signal156B, as a modified CA signal156A, to a respective of the delay blocks122, such that the CA IN_OUT signal156B from CA input buffer120A transmits to delay block122A. The CA IN_OUT signal156B may be transmitted through the respective delay blocks122to delay the data172B.

The NAND_IN signal156C transmitted from the delay blocks122may be received by logic gates124. As depicted, the logic gates124are NAND gates that activate in response to inputs from the delay blocks122and from the chip select input buffer130. To describe the illustrated NAND gate operation, if both the input from the delay block122and the input from the chip select input buffer130equal one (e.g., Boolean 1, logical high voltage), the NAND gate outputs a zero. However, if either the input from the delay block122and/or the input from the chip select input buffer equal zero (e.g., Boolean 0, logical low voltage), the NAND gate outputs a one. It is noted that any suitable logic gate may be used as the logic gate124, and that the NAND gate is described for ease of discussion.

Since the logical gates124operate independently, a logical gate124A may output a different value from a logical gate124B based at least in part on the input received from the delay blocks122. In addition, since the data transmitted by the NAND_IN signal156C is essentially stopped at the logical gate124until transmission is permitted by the chip select signal154, only components coupled between the CA pads16and the logical gates124consume electrical power while the chip select signal154is disabled and not permitting the NAND_IN signal156C from transmitting to the delay blocks126.

Upon the chip select signal154, via the OR_OUT signal160, permitting the NAND_IN signal156C to transmit from the logical gates124, the NAND_OUT signal156D transmits through the delay blocks126and may be delayed a second amount of time. The total value of the time delay (T3) applied to the CA signal156A to create the LATCH_IN signal156E approximately equals the set-up time duration (TSU) minus the time duration (TC) after the enabled chip select signal154described in discussions associated withFIG. 3. Thus, upon transmission from the delay blocks126to the centralized latches128, the latch input signal data172E may be correctly latched by the latches128on the rising edge of the LATCH CLK signal170transmitted via the depicted communicative coupling (LATCH CLK PATH).

The depicted clock distribution circuitry138may generate internal clock signals, including the LATCH CLK signal170transmitted to control latching operations of the latches128, based at least in part on the external clock signal152received by the memory device10A at the clock pads18. It is noted that one benefit of using centralized latches128and centralized CA input buffers120is that a clock tree (e.g., clock tree architecture) to disburse the LATCH CLK signal170may be optionally implemented. Implementation of the clock tree may be optionally used because delays caused by the path length between the clock distribution circuitry138and the latches128is negligible in this arrangement of components following a direct path architecture.

Accordingly, the technical effects of the present disclosure include techniques for improving power consumption of inactive (e.g., unselected) portions of a memory device and/or power consumption of an inactive memory device. The techniques include systems and methods for including, in a command and/or address input circuit, one or more delay blocks before and after a logic gate. The logic gate may be controlled by a chip select signal to arbitrate transmission of command and/or address signal inputs. Because the logic gate arbitrates transmission of the command and/or address signal inputs, only components coupled in-between a command and/or address pad and the logic gate consume power while the memory device is inactive, thus stopping power consumption by additional delay blocks of the command/address input circuit. Furthermore, implementing the arbitrating logic gate may enable input buffers and latches of the command/address input circuit to be disposed in a centralized location on the memory device, enabling direct communication of the latch clocking signal to the centralized latches as opposed to using a clock tree to transmit the latch clocking signal.

While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following appended claims.