Methods to reshape spacer profiles in self-aligned multiple patterning

Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

BACKGROUND

The present disclosure relates to methods for the manufacture of microelectronic workpieces including the formation of patterned structures on microelectronic workpieces.

Device formation within microelectronic workpieces typically involves a series of manufacturing techniques related to the formation, patterning, and removal of a number of layers of material on a substrate. To meet the physical and electrical specifications of current and next generation semiconductor devices, processing flows are being requested to reduce feature size while maintaining structure integrity for various patterning processes.

Self-aligned multiple patterning (SAMP) processes, such as self-aligned double patterning (SADP) processes and self-aligned quadruple patterning (SAQP), have been developed to reduce feature sizes beyond what is directly achievable by lithography processes. For some SAMP processes and particularly for SADP processes, spacers are typically formed as side wall structures adjacent cores on a substrate being processed, and the core material is later removed. This core removal process is typically called a mandrel pull and is often performed by a plasma etch process such as a reactive ion etch (RIE) process.

For prior SAMP processes, the height of the spacers after the mandrel pull process are typically different with respect to the portions of the spacers adjacent to the cores and the portions of the spacers adjacent the gaps between the cores. This asymmetric shape of the spacers degrades etch uniformity and introduces gouging differences during later etch processes. For example, these asymmetric shapes often cause gouging differences to form between portions of an underlying material layer below the removed cores and portions of the underlying material layer below the gaps between the cores. This degradation occurs, for example, when the patterned formed by the spacers is transferred through an etch process to an underlying layer, such as a hard mask layer.

FIG.1(Prior Art) provides a cross-section view of an example embodiment100for prior solutions where degradation of etch uniformity is caused in subsequent pattern transfer due to the asymmetric shape of the top portions of spacers104that remain after the mandrel pull within a SAMP process. The asymmetric shape of the spacers104and resulting degradation in etch uniformity can introduce deterioration of line edge roughness (LER) and line width roughness (LWR) parameters. The asymmetric spacer shape also tends to cause pitch walking due to the deterioration of gouging depth within the underlying layers.

Looking to example embodiment100, cores have been removed from between spacers104using a mandrel pull process. The spacers104were previously formed on a substrate102, which can include one or more material layers. The mandrel pull process leaves core sites106and space sites108associated with the spacers104. An example core site106is shown to the left of dashed line110, and an example space site108is shown to the right of dashed line110. As shown, the spacers104left after the mandrel pull process have asymmetric top portions. In particular, the edges of the spacers104on the sides adjacent a core site106where a core has been pulled are higher than the edges of the spacers104on the sides adjacent a space site108where there were gaps between the cores.

During subsequent etch processing, such as plasma etch processing, particles112associated with the etch chemistry are delivered to the substrate102. However, the delivery of these particles112to the substrate102will be affected by the asymmetric top portions of the spacers104. For example, particles112delivered to the space site108will be redirected into the region between the spacers104, and particles delivered to the core site106will be redirected away from the region between the spacers104. As such, the surface for an underlying layer within the substrate102associated with the space site108will be etched more quickly than the surface for an underlying layer associated with a core site106. This uneven etching will lead to undesired variations in etch profiles.

FIGS.2A-D(Prior Art) provide cross-section views of an example embodiment where asymmetric spacers lead to lack of etch uniformity in prior solutions.

FIG.2A(Prior Art) provides a cross-section view of an example embodiment200after a spacer material layer204has been deposited over cores202. The cores202were previously formed over the substrate102, which can include one or more material layers. The spacer material layer204can be an oxide layer (SiO2), a nitride layer (SiN), and/or other protective material layer that is formed over the cores202. For one example embodiment, the spacer material layer204is deposited using atomic layer deposition (ALD) and/or other deposition techniques. The cores202can be formed as an organic planarization layer (OPL), an amorphous silicon layer, and/or another material layer.

FIG.2B(Prior Art) provides a cross-section view of an example embodiment210after an etch back process has been performed. For example, an etch back process is performed to etch the spacer material layer204and form spacers104along the side walls of the cores202. The etch back process can be, for example, a plasma etch process.

FIG.2C(Prior Art) provides a cross-section view of an example embodiment220after a mandrel pull process has been performed. As shown, the mandrel pull process, such as an ash process where the cores202are formed from an OPL, is used to remove the cores202shown inFIG.2B(Prior Art). After this mandrel pull process, spacers104are left that have asymmetric top portions. In particular, the edges of the spacers104on the sides adjacent to core sites106where cores202were pulled are higher than the edges of the spacers104on the sides adjacent to space sites108where there were gaps between the cores202as shown inFIG.2B(Prior Art).

FIG.2D(Prior Art) provides a cross-section view of an example embodiment230after an etch process has been applied to transfer the pattern for the spacers104to the substrate102between the spacers104. The asymmetric shapes of the spacers104cause degradation in etch uniformity and uneven gouging in the underlying material layer within the substrate102as described with respect toFIG.1(Prior Art). As shown inFIG.2D(Prior Art), differences in etch uniformity leaves surfaces associated with core sites106having different resulting etch levels as compared to surfaces associated with the space sites108. Thus, etch uniformity is degraded giving rise to various potential problems as described above.

SUMMARY

Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. The reshaping is providing by depositing additional spacer material to corners of spacers adjacent cores and/or corners of a spacer material layer that covers cores that have formed, for example, as part of a SAMP process. For one example embodiment, one or more directional deposition processes, such as oblique physical vapor deposition (PVD) processes, are used to reshape the spacer profiles. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes. Different or additional features, variations, and embodiments can also be implemented, and related systems and methods can be utilized as well.

For one embodiment, a method to reshape spacer profiles is disclosed including forming cores on a material layer for a substrate of a microelectronic workpiece, forming a spacer material layer over the cores, and forming symmetric spacers adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps.

In additional embodiments, the symmetric spacers are formed as part of a self-aligned multiple patterning (SAMP) process. In further embodiments, the symmetric spacers are formed by depositing, with the one or more directional deposition processes, additional spacer material to corners of the spacer material layer where the spacer material layer covers corners of the cores and by etching, with the one or more etch processes, the spacer material layer and the additional spacer material to leave symmetric spacers adjacent the cores. In still further embodiments, the corners of the spacer material layer are rounded corners.

In additional embodiments, the symmetric spacers are formed by etching the spacer material layer to form asymmetric spacers adjacent the cores, by depositing additional spacer material to corners of the spacers with the one or more directional deposition processes, and by etching the additional spacer material to leave symmetric spacers adjacent the cores with the one or more etch processes. In further embodiments, the corners of the asymmetric spacers have rounded corners.

In additional embodiments, the method includes using a planarization process at least in part to form the symmetric spacers. In further embodiments, the spacer material layer and the additional spacer material are a common material. In still further embodiments, the spacer material layer and the additional spacer material are different materials.

In additional embodiments, the one or more directional deposition processes include one or more oblique physical vapor deposition (PVD) processes. In further embodiments, the one or more oblique PVD processes apply the additional spacer material at an angle of 30 to 60 degrees. In further embodiments, the one or more oblique PVD processes apply the additional spacer material at an angle of 45 degrees.

In additional embodiments, the one or more oblique PVD processes are used to deposit additional spacer material simultaneously in two different directions. In further embodiments, a first set of one or more oblique PVD processes is used to deposit additional spacer material in a first direction and a second set of one or more oblique PVD processes is used to deposit additional spacer material in a second direction. In still further embodiments, oblique PVD processes from the first set are alternated with oblique PVD processes from the second set.

In additional embodiments, a plurality of oblique physical vapor deposition (PVD) processes are used having at least one of a same process chemistry, a different process chemistry, or a combination thereof. In further embodiments, a plurality of oblique physical vapor deposition (PVD) processes are used having at least one of a same target material, a different target material, or a combination thereof.

In additional embodiments, the method also includes removing the cores to leave the symmetric spacers. In further embodiments, the method includes transferring a pattern for the symmetric spacers to the material layer. In still further embodiments, a target level of etch uniformity is achieved in the transferring of the pattern.

In additional embodiments, he spacer material layer includes at least one of an oxide or a nitride, and the additional spacer material includes at least one of an oxide or a nitride. In further embodiments, the cores are formed from at least one of an organic planarization layer or an amorphous silicon layer. In still further embodiments, the spacer material layer is formed using atomic layer deposition.

Different or additional features, variations, and embodiments can also be implemented, and related systems and methods can be utilized as well.

DETAILED DESCRIPTION

As described herein, etch uniformity is improved for the manufacture of microelectronic workpieces by reshaping spacer profiles with additional spacer material using one or more directional deposition processes. Embodiments include depositing additional spacer material to corners of spacers adjacent cores, to corners of a spacer material layer that covers cores formed as part of a SAMP process, and/or other implementations that reshape spacer profiles using directional deposition processes. For one embodiment, the one or more directional deposition processes include oblique physical vapor deposition (PVD) processes that are used to deposit the additional spacer material. Once the spacer profiles are reshaped, an etch back process is performed to etch back the spacer material layers and/or the additional spacer material in order to leave symmetric spacers adjacent the cores. A planarization process can also be used in the formation of the symmetric spacers. After cores are pulled, these symmetric spacers are used to transfer a pattern to underlying layers without suffering from the etch uniformity degradation experienced by prior solutions. The reshaping embodiments described herein are able to achieve a target level of etch uniformity and/or a target level of gouging in this pattern transfer to one or more underlying material layers. Other advantages and implementations can also be achieved while still taking advantage of the process techniques described herein.

FIGS.3A-3Eprovide cross-section views of an example embodiment where spacer material layers are reshaped to reduce or eliminate degradation in etch uniformity experienced by prior solutions. For this example embodiment, the spacer material layers are reshaped by depositing additional spacer material to corners of a spacer material layer using one or more directional deposition processes, such as oblique PVD processes. This reshaping then allows for the formation of symmetric spacers thereby reducing or eliminating degradation in etch uniformity experienced by prior solutions.

FIG.3Aprovides a cross-section view of an example embodiment300after a spacer material layer204has been formed over cores202, which were previously formed over a substrate102. The substrate102can include one or more material layers. The spacer material layer204can be an oxide layer (SiO2), a nitride layer (SiN), and/or other protective material layer that is formed over the cores202. For one example embodiment, the spacer material layer204is formed using atomic layer deposition (ALD) and/or other deposition techniques. The cores202can be formed from an OPL, an amorphous silicon layer, and/or another material layer.

FIG.3Bprovides a cross-section view of an example embodiment310after one or directional deposition processes have been performed to deposit additional spacer material314. This additional spacer material314is deposited on the corners of the spacer material layer204where it covers the corners on one side of the cores202. For embodiment310, the additional spacer material314is being deposited on the top right corners of the spacer material layer204as indicated by arrows312. As shown for embodiment310, these corners where the additional spacer material314is deposited can be rounded corners. The additional spacer material314can be the same material as the spacer material layer204or can be a different material from the spacer material layer204.

FIG.3Cprovides a cross-section view of an example embodiment315after one or directional deposition processes have been performed to deposit additional spacer material316. This additional spacer material316is deposited on the corners of the spacer material layer204where it covers the corners one the other side of the cores202. For embodiment315, the additional spacer material316is deposited on the top left corners of the spacer material layer204as indicated by arrows317. As shown for embodiment315, these corners where the additional spacer material316is deposited can be rounded corners. The additional spacer materials314/316can be, for example, oxide, nitride, and/or other protective material. The additional spacer material316can be the same material as the spacer material layer204or can be a different material from the spacer material layer204. Further, directional deposition processes used to form the additional spacer materials314/316can be implemented using the same process chemistry, using different processing chemistry, or combinations thereof. Still further, the target material of the deposition processes used to form the additional spacer materials314/216can also be the same, different, or combinations thereof. Other variations can also be implemented while still taking advantage of the techniques described herein.

It is noted that the additional spacer material314is shown as being formed before the additional spacer material316inFIGS.3B-C. It is further noted that additional spacer material316can be formed before the additional spacer material314. In addition, additional spacer materials314/316can be deposited using directional deposition processes that alternate directions. For example, a first set of directional deposition processes are used to deposit the additional spacer material314using one angle, and a second set of directional deposition processes are used to deposit the additional spacer material316. In addition, deposition processes within the first set and with the second set are alternated to build the additional spacer materials314/316over multiple alternating process cycles. This alternating technique helps to avoid shadowing that can occur, for example, if one of the spacer materials314/316is fully formed before the other is formed.

For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used as the directional deposition processes to deposit the additional spacer material314shown inFIG.3Band the additional spacer material316shown inFIG.3C. For example, one or more oblique PVD processes can be used to apply additional spacer material314to the top right corners of the spacer material layer204, and one or more similar oblique PVD processes can also be used to apply additional spacer material316to the top left corners of the spacer material layer204. The oblique PVD processes can deposit the additional spacer materials314/316, for example, at an angle of 30 to 60 degrees and preferably at an angle of 45 degrees. Although separate oblique PVD processes are shown with respect toFIG.3BandFIG.3C, it is noted that one or more oblique PVD processes could also be used to apply the additional spacer materials314/316simultaneously to both corners of the spacer material layer204. Further, as indicated above, oblique PVD processes can be used that alternate directions to build the additional spacer materials314/316in with an alternating technique over multiple, alternating process cycles. In addition, the oblique PVD processes can be implemented using the same process chemistry, using different processing chemistry, or combinations thereof. Further, the target material of the PVD processes used to form the additional spacer materials314/216can also be the same, different, or combinations thereof. Still further, other directional deposition processes could also be used instead of or in addition to one or more oblique PVD processes. Other variations can also be implemented while still taking advantage of the techniques described herein.

FIG.3Dprovides a cross-section view of an example embodiment320after a portion of the spacer material layer204and the additional spacer materials314/316has been removed to form symmetric spacers324adjacent the cores202. For example, an etch back process can be performed to etch back the spacer material layer204and the additional spacer materials314/316in order to leave symmetric spacers324along the side walls of the cores202. For one example embodiment, a planarization process is performed to planarize the spacer material layer204along with the top surface of the cores202and the additional spacer material314as part of the formation of the symmetric spacers324. It is also noted that an etch back process and a planarization could be used in combination. Different and/or additional processes could also be used to form the symmetric spacers324after the reshaping provided inFIGS.3B-C.

FIG.3Eprovides a cross-section view of an example embodiment330after a mandrel pull process has been performed. As shown, the mandrel pull process, such as an ash process where the cores202are formed from an OPL, is used to remove the cores202shown inFIG.3D. After this mandrel pull process, symmetric spacers324are left. In particular, the edges of the symmetric spacers324on the sides adjacent to core sites346where cores202were pulled have similar or matching levels as compared to the edges of the symmetric spacers324on the sides adjacent to space sites348where there were gaps between the cores202as shown inFIG.3D. In contrast with prior solutions, these symmetric spacers324are uniform and provide symmetric top portions.

FIG.3Fprovides a cross-section view of an example embodiment340after an etch process has been applied to transfer the pattern for the symmetric spacers324to the substrate102between the symmetric spacers324. The substrate102can include one or more material layers upon which the cores202were previously formed as shown inFIG.3A. The symmetric shapes of the spacers324alleviate the problems associated with the asymmetric spacers generated by prior solutions, thereby improving etch uniformity. In particular, as shown in embodiment340, etch uniformity is improved so that surfaces associated with core sites346have similar or matching etch levels as compared to surfaces associated with space sites348. Thus, etch uniformity is improved thereby reducing or eliminating problems experienced in prior solutions. Further, the reshaping embodiments described herein are able to achieve a target level of etch uniformity and/or a target level of gouging in the pattern transfer to one or more underlying material layers as shown inFIG.3Fdue to the reshaping of spacer profiles and formation of symmetric spacers as described herein.

FIGS.4A-4Dprovide cross-section views of an additional example embodiment where spacer material layers are reshaped to reduce or eliminate degradation in etch uniformity experienced by prior solutions. For this example embodiment, the spacer material layers are reshaped by depositing additional spacer material to corners of spacers using one or more directional deposition processes such as oblique PVD processes. This reshaping then allows for the formation of symmetric spacers thereby reducing or eliminating degradation in etch uniformity experienced by prior solutions.

FIG.4Aprovides a cross-section view of an example embodiment400after a spacer material layer204has been formed over cores202, which were previously formed over a substrate102. The substrate102can include one or more material layers. The spacer material layer204can be an oxide layer (SiO2), a nitride layer (SiN), and/or other protective material layer that is formed over the cores202. For one example embodiment, the spacer material layer204is formed using atomic layer deposition (ALD) and/or other deposition techniques. The cores202can be formed from an OPL, an amorphous silicon layer, and/or another material layer. It is noted that embodiment400matches embodiment300ofFIG.3A.

FIG.4Bprovides a cross-section view of an example embodiment410after an etch back process has been performed. For example, an etch back process is performed to etch the spacer material layer204shown inFIG.4Aand to form spacers104along the side walls of the cores202as shown for example embodiment410inFIG.4B. The etch back process can be, for example, a plasma etch process.

FIG.4Cprovides a cross-section view of an example embodiment420after one or directional deposition processes have been performed to deposit additional spacer material422. This additional spacer material422is deposited on the corners of the spacers104that are adjacent the cores202. For embodiment420, these corners are rounded corners. As described above the one or more directional deposition processes can be one or more oblique PVD processes. For some embodiments as described above, the one or more oblique PVD processes can be used to deposit additional spacer material simultaneously in two different directions to deposit the additional spacer material422on spacers on both sides of the cores at the same time. For additional embodiments, a first set of one or more oblique PVD processes can be used to deposit additional spacer material422in a first direction for a first set of corners, and a second set of one or more oblique PVD processes can be used to deposit additional spacer material in a second direction for a second set of corners. Other variations can also be implemented.

FIG.4Dprovides a cross-section view of an example embodiment430after the additional spacer material422has been etched to form symmetric spacers324adjacent the cores202. For example, an etch back process can be performed to etch back the additional spacer material422as well as the spacer material layer204as needed in order to leave symmetric spacers324along the side walls of the cores202. For one example embodiment, a planarization process can also performed to planarize the spacer material layer204along with the top surface of the cores202and the additional spacer material422in order to form or facilitate the formation of the symmetric spacers324. It is also noted that an etch back process and a planarization could be used in combination. Different and/or additional processes could also be used to form the symmetric spacers324after the reshaping provided inFIG.4C. It is also noted that embodiment430matches embodiment320ofFIG.3D, and the processes ofFIGS.3E-Fcan similarly be used to further process embodiment430inFIG.4D.

FIG.5Ais a process flow diagram of an example embodiment500that provides reshaping of spacer profiles by depositing additional spacer material using direction deposition processes. In block502, cores are formed on a material layer for a substrate of a microelectronic workpiece. In block504, a spacer material layer is formed over the cores. In block506, symmetric spacers are formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. It is noted that additional and/or different steps could also be used while still taking advantage of the techniques described herein.

FIG.5Bis a process flow diagram of an example embodiment510that provides reshaping of spacer profiles by depositing additional spacer material to corners of a spacer material layer using direction deposition processes. Blocks502and504are the same as inFIG.5A. For block502, cores are formed on a material layer for a substrate of a microelectronic workpiece. For block504, a spacer material layer is formed over the cores. For embodiment510, the symmetric spacers are formed in blocks512and514. For block512, additional spacer material is deposited to corners of the spacer material layer where the spacer material layer covers corners of the cores using one or more directional deposition processes. In block514, a portion of the spacer material layer and the additional spacer material are removed to leave symmetric spacers adjacent the cores. It is noted that additional and/or different steps could also be used while still taking advantage of the techniques described herein.

FIG.5Cis a process flow diagram of an example embodiment520that provides reshaping of spacer profiles by depositing additional spacer material to corners of spacers using direction deposition processes. Blocks502and504are the same as inFIG.5A. For block502, cores are formed on a material layer for a substrate of a microelectronic workpiece. For block504, a spacer material layer is formed over the cores. For embodiment520, the symmetric spacers are formed in blocks522,524, and526. In block522, the spacer material layer is etched to form asymmetric spacers adjacent the cores. In block524, additional spacer material is deposited to corners of the spacers using one or more directional deposition processes. In block526, the additional spacer material is etched to leave symmetric spacers adjacent the cores. It is noted that additional and/or different steps could also be used while still taking advantage of the techniques described herein.

It is noted that one or more deposition processes can be used to form the material layers described herein. For example, one or more depositions can be implemented using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other deposition processes. For a plasma deposition process, a precursor gas mixture can be used including but not limited to hydrocarbons, fluorocarbons, or nitrogen containing hydrocarbons in combination with one or more dilution gases (e.g., argon, nitrogen, etc.) at a variety of pressure, power, flow and temperature conditions. Lithography processes with respect to PR layers can be implemented using optical lithography, extreme ultra-violet (EUV) lithography, and/or other lithography processes. The etch processes can be implemented using plasma etch processes, discharge etch processes, and/or other desired etch processes. For example, plasma etch processes can be implemented using plasma containing fluorocarbons, oxygen, nitrogen, hydrogen, argon, and/or other gases. In addition, operating variables for process steps can be controlled to ensure that CD (critical dimension) target parameters for vias are achieved during via formation. The operating variables may include, for example, the chamber temperature, chamber pressure, flowrates of gases, frequency and/or power applied to electrode assembly in the generation of plasma, and/or other operating variables for the processing steps. Variations can also be implemented while still taking advantage of the techniques described herein.

“Microelectronic workpiece” as used herein generically refers to the object being processed in accordance with the invention. The microelectronic workpiece may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor substrate or a layer on or overlying a base substrate structure such as a thin film. Thus, workpiece is not intended to be limited to any particular base structure, underlying layer or overlying layer, patterned or unpatterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description below may reference particular types of substrates, but this is for illustrative purposes only and not limitation.

The term “substrate” as used herein means and includes a base material or construction upon which materials are formed. It will be appreciated that the substrate may include a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or different structures in them, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semi-conductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

Systems and methods for processing a microelectronic workpiece are described in various embodiments. One skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the described systems and methods are not limited by these example arrangements. It is to be understood that the forms of the systems and methods herein shown and described are to be taken as example embodiments. Various changes may be made in the implementations. Thus, although the inventions are described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present inventions. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present inventions. Further, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.