Semiconductor chip with anti-reverse engineering function

A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

BACKGROUND

The present invention relates to the field of integrated circuits; more specifically, it relates to semiconductor chips with anti-reverse engineering functions and methods of fabricating semiconductor chips with anti-reverse engineering functions.

Semiconductor chips often contain intellectual property or sensitive structures that can be reverse-engineered resulting in the potential loss of such information or the disclosure of sensitive information. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.

SUMMARY

A first aspect of the present invention is a structure, comprising: a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

A second aspect of the present invention is a structure, comprising: a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a first trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; a second trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a first chemical agent filling the first trench and a second chemical agent filling the second trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to a reaction product of the first chemical agent and the second chemical agent or can be physically damaged by the reaction product.

A third aspect of the present invention is a method, comprising: providing a semiconductor substrate; forming a stack of wiring levels from a first wiring level to an intermediate wiring level, the first wiring level closest to the semiconductor substrate and the intermediate wiring level furthest from the semiconductor substrate; forming active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; forming one or more trenches extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; (i) filling the one or more trenches with a first chemical agent that can cause damage to or destroy portions of at least one wiring level of the stack of wiring levels or (ii) filling a first group of the one or more trenches with a second chemical agent and a filling a second group of the one more trenches a third chemical agent, a mixture of the second chemical agent and the third chemical agent generating a fourth chemical agent that can cause damage to or destroys portions of at least one wiring level of the stack of wiring levels; forming caps on the one or more trenches; and forming one or more additional wiring levels on top of the intermediate wiring level.

These and other aspects of the invention are described below.

DETAILED DESCRIPTION

The anti-reverse engineering structures according to the embodiments of the present invention comprise sealed trenches completely within the active and wiring levels of a semiconductor chip. The sealed trenches contain chemical agents that will damage or destroy one or more of the materials in the various layers of the semiconductor chip and/or the semiconductor substrate by chemical attack or physical or thermal stress when the seal around the trench is broken, thereby preventing reverse engineering or making reverse engineering very difficult.

The anti-reverse engineering structures according to embodiments of the present invention are not formed above the wiring levels of the chip and are not formed in the bottom side of the semiconductor substrate (the side opposite from the top side of the semiconductor chip where active devices such as transistors are formed). Rather the sealed trenches containing the chemical agents are contained completely within the active and wiring levels of a semiconductor chip making them difficult to detect as they not visible. One or more of the materials of the semiconductor chip are not chemically inert to chemical agents or are not chemically inert to chemical agents generated by the reaction of the chemical agent with air, oxygen or water, or are not chemically inert to a chemical agent generated by the mixing of two different chemical agents contained in different trenches. The anti-reverse engineering structures according to embodiments of the present invention are passive in that they do not require heat or electrical ignition to activate.

FIG. 1is a cross-section of an exemplary integrated circuit containing an anti-reverse engineering structure according embodiments of the present invention. InFIG. 1, semiconductor chip100includes a semiconductor substrate (i.e., a silicon or silicon on insulator) and first dielectric layer110. First dielectric layer110may itself be formed from two or more dielectric layers examples of which silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), plasma-enhanced silicon nitride (PSiNx) and Borophosphosilicate glass (BPSG). Formed in substrate105and first dielectric layer110are field effect transistors (FETs)106which comprise source/drains107and108and gates109. FETs106are electrically contacted by wires115in first dielectric layer110.

Formed in a stack on first dielectric layer110are a series of wiring levels containing electrically conductive wires embedded in corresponding dielectric layers. Second dielectric layer120contains wires125, third dielectric layer130contains wires135, fourth dielectric layer140contains wires145, fifth dielectric layer150contains wires155, sixth dielectric layer160contains wires165, seventh dielectric layer170contains wires175, eighth dielectric layer180contains wires185and ninth dielectric layer190contains electrically conductive pads195. Formed on top of ninth dielectric layer is a dielectric passivation layer200. An electrically conductive pad limiting metallurgy (PLM) layer205is formed in openings in passivation layer200and electrically conductive solder bumps210are formed on PLM layers205. Wires110,120,130,140,150,160,170,180and pads195interconnect FETs106into integrated circuits and provide input/output (I/O) and power connections to semiconductor chip100through solder bumps210.

Formed in semiconductor substrate105and extending through dielectric layers110,120,130,140,150and160, but not extending into dielectric layer170, is a trench215. Formed on the sidewalls217and bottom218of trench215is a liner220. Liner220may be formed from one or more layers. (SeeFIG. 9and description infra for an example). Formed in dielectric layer is a cap225that seals the top of trench215. Cap225may extend into trench215. Cap225may be formed from one or more layers. Cap225may be formed from the same materials as liner220. In one example, liner220and cap225independently comprise one or more layers of gold (Au), platinum (Pt), Ti, Ta, Si3N4, a stress absorption layer and TEOS oxide5. Remaining space (that space not taken up by liner220) in trench is either completely filled or partially filled (to line230) with an agent235. Partially filling trench215allows for expansion of agent235when integrated circuit chip is subjected to heat during fabrication, in one example, up to 430° C. Agent235will (i) chemically attack one or more of the materials in the various layers of the semiconductor chip and/or the semiconductor substrate or (ii) generate an agent that will chemically attack one or more of the materials in the various layers of the semiconductor chip and/or the semiconductor substrate when exposed to air (i.e., the oxygen in air) or water. Liner220and cap225are not attacked by agent235.

In one example, agent235comprises a material that reacts with oxygen. In one example, agent235comprises a material that reacts with water. In one example, agent235comprises boron trichloride (BCl3) which reacts with water to form HCl. In one example, agent235comprises trichlorosilane (SiCl3H) which reacts with air to form HCl. In one example, agent235comprises iron (Fe) or aluminum (Al) in an oxygen free slurry which will reacts with air exothermically. In one example, agent235comprises hydrofluoric acid (HF) or buffered HF (BHF), hydrochloric acid (HCl), phosphoric acid (H3PO4), nitric acid (HNO3) or potassium hydroxide (KOH). In one example, agent235comprises sodium polyacrylate.

While nine wiring levels are illustrated inFIG. 1, there may be less than nine or more than nine. While trench215is illustrated extending from within substrate105up through dielectric layer170, trench215may extend into layers above dielectric layer160or only to a layer below dielectric layer160. The terms above and below are defined in the frame of reference where silicon substrate105is the bottom of the semiconductor chip and passivation layer200is the top of the semiconductor chip. While one filled and capped trench215is illustrated inFIG. 1, there may be multiple filled and capped trenches distributed throughout the semiconductor chip. Multiple filled and capped trenches may be disturbed individually or in groups of tens to hundreds. Groups of filled and capped trenches may be distributed throughout the semiconductor chip or in specific regions of the semiconductor chip that are deemed sensitive.

FIG. 2is a cross-section of an exemplary integrated circuit containing a binary anti-reverse engineering structure according embodiments of the present invention. Semiconductor chip100A ofFIG. 2is similar to semiconductor chip100ofFIG. 1. InFIG. 2, trench215ofFIG. 1is replaced with a pair of trenches, a first trench215A and a second trench215B. First trench215A includes a first liner220A, a first cap225A and a first agent235A that either completely fills remaining space (that space not taken up by liner220A) in trench215A or fills the remaining space in trench215A to line230A. Second trench215B includes a second liner220B, a second cap225B and a second agent235B that either completely fills remaining space (that space not taken up by liner220B) in trench215B or fills the remaining space in trench215B to line230B. First liner220A and first cap225A are not attacked by agent235A. Second liner220B and second cap225B are not attacked by agent235B. The materials of first liner220A and second liner220B are the same as for liner220ofFIG. 1described supra. The materials of first cap225A and second cap225B are the same as for cap225ofFIG. 1described supra.

First agent235A and second agent235B form a binary system that generate, when mixed together, a reaction product that will (i) generate a chemical agent that will chemically attack one or more of the materials in the various layers of the semiconductor chip and/or the semiconductor substrate or (ii) physically or thermally damage the semiconductor chip when exposed, for example, by a increase in volume. In one example, first agent235A comprises an isocyanate and second agent235B comprises a polyol. In one example, first agent235A comprises BCl3and second agent235B is water. In one example, first agent235A comprises sodium polyacrylate and second agent235B is water or a water containing gel.

FIG. 3is a cross-section of an exemplary integrated circuit containing a nested binary anti-reverse engineering structure according embodiments of the present invention. Semiconductor chip100B ofFIG. 3is similar to semiconductor chip100ofFIG. 1. InFIG. 3, trench215ofFIG. 1is replaced with a pair of trenches, a third trench215C and a fourth annular trench215D surrounding third trench215C. Third trench215C is separated from fourth trench215D by a ring of stacked semiconductor substrate105, first dielectric layer110, second dielectric layer120, third dielectric layer130, fourth dielectric layer150and sixth dielectric layer160. Third trench215C includes a third liner220C, a third cap225C and a third agent235C that either completely fills remaining space (that space not taken up by liner220C in trench215C or fills the remaining space in trench215C to line230C. Fourth trench215D includes a fourth liner220D, a fourth cap225D and a fourth agent235D that either completely fills remaining space (that space not taken up by liner220D) in trench215D or fills the remaining space in trench215D to line230D. Third liner220C and third cap225C are not attacked by agent235C. Fourth liner220D and fourth cap225D are not attacked by agent235D. The materials of third liner220C and fourth liner220D are the same as for liner220ofFIG. 1described supra. The materials of third cap225C and fourth cap225D are the same as for cap225ofFIG. 1described supra.

Third agent235C and fourth agent235D form a binary system that generate, when mixed together, a material a material will (i) generate an agent that will chemically attack one or more of the materials in the various layers of the semiconductor chip and/or the semiconductor substrate or (iii) physically or thermally damage the semiconductor chip when exposed, for example, by a increase in volume. In one example, third agent235C comprises an isocyanate and fourth agent235D comprises a polyol. In one example, third agent235C comprises BCl3and fourth agent235D is water. In one example, third agent235C comprises sodium polyacrylate and fourth agent235D is water or a water containing gel.

FIG. 5is cross-section through line5-5ofFIG. 2. InFIG. 5, trench215A has a diameter D2and trench215B has a diameter D3. Liner220A has a thickness T2and liner220B has a thickness T3. In one example, D2is between 1 um and 10 um. In one example, D3is between 1 um and 10 um. In one example, T2is between 10 nm and 100 nm In one example, T3is between 10 nm and 100 nm.

FIG. 6is a cross-section through line6-6ofFIG. 3. InFIG. 6, trench215C has a diameter D4and trench215D has an inside diameter D5and an outside diameter D6. Liner220C has a thickness T4and liner220D has a thickness T5. In one example, D4is between 0.5 um and 5 um. In one example, D5is between 1 um and 10 um. In one example, D6is between 2 um and 20 um. In one example, T4is between 10 nm and 100 nm. In one example, T5is between 10 nm and 100 nm.

FIGS. 7A through 7Dillustrate a method of fabricating an integrated circuit containing an anti-reverse engineering structure according embodiments of the present invention. InFIGS. 7A through 7B, the structure illustrated inFIG. 1is used as an example. InFIG. 7A, semiconductor chip100is formed through dielectric layers160and a trench215is formed through dielectric layers110,120,130,140,150,160into substrate105. There were no wires115,125,135,145,155,165in the dielectric layers in the regions of the dielectric layers that trench215was formed in. InFIG. 7B, liner220is formed. In one example, liner220is also formed on the top surface of dielectric layer160. InFIG. 7C, liner220is removed from the top surface of dielectric layer160using, for example, a directional etch. InFIG. 7D, trench215is filled with agent235and cap225formed. The additional layers, wires and structures on top of layer dielectric160illustrated inFIG. 1are next formed.

FIGS. 8A and 8Billustrate alternative steps forming the trench ofFIG. 7A. InFIG. 8A, semiconductor chip100is completed only through dielectric layer110and a trench245formed from the top surface of dielectric layer110into substrate105. There are no wires115or FETs106(or other devices) in the region of dielectric layer110and substrate105in which trench245is formed. InFIG. 8B, semiconductor chip is completed through dielectric layer160. Trench245is filled with dielectric material from one or more subsequent layers (not shown) subsequently removed when trench215is formed through dielectric layers120,130,140,150,160into substrate105. There were no wires125,135,145,155,165in the dielectric layers in the regions of the dielectric layers that trench215was formed in. The method next proceeds toFIG. 7B.

FIG. 9is an exemplary cross-section of the sidewall layer of the trenches ofFIGS. 1, 2 and 3according to embodiments of the present invention. InFIG. 9liner220comprises a buffer layer250on sidewall217of trench215. A stress absorption layer255is formed on buffer layer250, a water barrier layer260is formed on stress absorption layer255, an adhesion layer265is formed on water barrier layer260and a chemically resistive layer270is formed on adhesion layer265. Chemically resistive layer270is not attacked by agent235. One or more of layers250,255,260and265are optional, but layer270must be present. In the example that agent235is corrosive, chemically resistive layer270comprises Au or Pt or alloys of Au or alloys of Pt. In one example, adhesion layer265comprises Ti or Ta. In one example, water barrier layer260comprises Si3N4. In one example, stress absorption layer260comprises HSQ, MSQ, polyphenylene oligomer, SiOx(CH3)yor SiCxOyHyor SiOCH, SiCOH), or porous SiCOH. In one example, buffer layer250comprises TEOS oxide.

FIG. 10is a cross-section illustrating the action of anti-reverse engineering structures according to embodiments of the present invention when the semiconductor chip is delayered from the top surface down. InFIG. 10semiconductor chip100will be used as an example. Upon delayering from the top of semiconductor chip100to dielectric layer160, cap225(seeFIG. 1) will be removed and agent235will be released into regions275. In regions275, one or more of dielectric layers110,120,130,140,150and160are not chemically inert to chemical agent235(or are not chemically inert to chemical agent generated by the reaction of chemical agent235and air, oxygen or water) will be damaged or destroyed, one or more of wires115,125,135,145,155and165are not chemically inert to chemical agent235(or are not chemically inert to chemical agent generated by the reaction of chemical agent235and air, oxygen or water) will be damaged or destroyed, or both one or more of dielectric layers110,120,130,140,150and160and one or more of wires115,125,135,145,155and165will be damaged or destroyed rending reverse engineering difficult or impossible.

FIG. 11is a cross-section illustrating the action of anti-reverse engineering structures according to embodiments of the present invention when the semiconductor chip is cross-sectioned. InFIG. 11semiconductor chip100will be used as an example. Upon cross-sectioning from the side of semiconductor chip100liner220will be breached and agent235will be released into regions280. In regions280, one or more of dielectric layers110,120,130,140,150,160and170are not chemically inert to chemical agent235(or are not chemically inert to chemical agent generated by the reaction of chemical agent235and air, oxygen or water) and will be damaged or destroyed, one or more of wires115,125,135,145,155,165and175will be damaged or destroyed, or both one or more of dielectric layers110,120,130,140,150,160and170and one or more of wires115,125,135,145,155,165and175are not chemically inert to chemical agent235(or are not chemically inert to chemical agent generated by the reaction of chemical agent235and air, oxygen or water) will be damaged or destroyed rending reverse engineering difficult or impossible.

Thus the embodiments of the present invention provide structures that comprise sealed trenches containing agents that will damage or destroy one or more of the materials in the various layers of the semiconductor chip (and/or the semiconductor substrate) by chemical attack physical or thermally stress when the seal around the trench is broken, thereby preventing reverse engineering or making reverse engineering very difficult.