Display panel

A display panel including a plurality of pixels. Each pixel includes: a light emitting element; a pixel circuit having a driving transistor connected to the light emitting element in series; a data line to which a data current is supplied through the pixel circuit; a scanning line for selecting the pixel circuit; a first insulation film to cover the data line; and a second insulation film made of a material different from the first insulation film, to cover the data line and the first insulation film, wherein the following expression is satisfied.Ctotal: parasitic capacitance of whole path to data line through pixel circuit; ∈0: vacuum dielectric constant; ∈a: relative dielectric constant of first insulation film; Da: first insulation film thickness; ∈b: relative dielectric constant of second insulation film; Db: second insulation film thickness.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-286449 filed on Sep. 30, 2005 and the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display panel including pixels each provided with a light emitting element.

2. Description of Related Art

An organic electroluminescence element has a laminated structure, for example, of an anode, an organic compound layer and a cathode stacked on a substrate. When a voltage is applied between the anode and the cathode, positive holes and electrons are injected into the organic compound layer to generate an electric field, thereby to emit light.

In a display panel of an active matrix driving type, a plurality of thin film transistors are provided for each pixel or dot, which allow the organic electroluminescence element to emit light. For example, in the display panel disclosed in JP-H8-330600A, two thin film transistors are provided for each pixel. A plurality of organic electroluminescence elements are formed and disposed in a matrix arrangement by a patterning process, and also in the patterning process, anodes are formed independently from each other in a bottom layer side which is connected to the thin film transistors. Meanwhile, the cathode is formed as a single film of a counter electrode to all pixels.

In order to drive the display panel, there are provided a plurality of scanning lines and signal lines on the display panel. When the display panel is driven, a signal is sequentially sent to the scanning lines to sequentially select the scanning lines, and signals corresponding to gradients are output while the scanning lines are selected, whereby a gradient signal is written on the pixel locating at the cross point of the selected scanning line and the signal line.

With respect to the driving system of the display panel, there are two systems: one is a voltage designating system for performing control according to a voltage value of a gradient signal to be output to the signal lines, and the other is a current designating system performing control according to a current value of a gradient signal to be output to the signal lines. In the voltage designating system, since the signal to be applied to the signal lines is a voltage, a signal reaches a predetermined potential in a certain time when a parasitic capacitance exists in the signal lines in some measure. Such a delay due to a parasitic capacitance exerts a large influence to a display of the current designating system, in particular. That is, in the current designating system, since the light emitting element itself can emit light with a weak current, a weak current flowing through the signal lines is enough, however, when the parasitic capacitance associated with lines is large, the current takes a time to reach a predetermined current value.

SUMMARY OF THE INVENTION

The present invention has been developed to solve the above problem. Therefore, an object of the invention is to provide a display panel in which the current delay caused by parasitic capacitance is reduced to the minimum.

According to one aspect of the present invention, the display panel includes a plurality of pixels, each of the pixels comprising:

a light emitting element;

a pixel circuit having a driving transistor connected to the light emitting element in series;

a data line to which a data current is supplied through the pixel circuit;

a scanning line for selecting the pixel circuit;

a first insulation film to cover the data line; and

a second insulation film made of a material different from the first insulation film, to cover the data line and the first insulation film,

wherein the following expression is satisfied:

Ctotal20≦ɛ0⁢ɛa⁢ɛbɛa⁢Db+ɛb⁢Da≦Ctotal5
where Ctotaldenotes a parasitic capacitance of a whole path to the data line through the pixel circuit, ∈0denotes a vacuum dielectric constant, ∈adenotes a relative dielectric constant of the first insulation film, Dadenotes a thickness of the first insulation film, ∈bdenotes a relative dielectric constant of the second insulation film, and Dbdenotes a thickness of the second insulation film.

Preferably, the second insulation film has a relative dielectric constant of 2.6 to 3.4, and has a thickness of 2.0 to 17.7 μm.

In the above-described display panel, the first insulation film may include the gate insulation film of the driving transistor, or may include an overcoat insulation film to cover the driving transistor, or may include a protection film which is formed together with a channel protection film by patterning a layer which comes to be the channel protection film of the driving transistor.

Further, in the above-described display panel, the first insulation film may have at least two of a gate insulation film, an overcoat insulation film and a channel protection film, and the at least two of a gate insulation film may have the same relative dielectric constant.

In the above-described display panel, the first insulation film may have at least two of a gate insulation film, an overcoat insulation film and a channel protection film, and the at least two of a gate insulation film may be made of the same material.

In the display panel, the light emitting element may have an organic compound layer, and the second insulation film may form a partition wall to divide the organic compound layer into lines of the pixels.

In the above-described display panel, a counter electrode may be formed on the second insulation film.

Preferably, in the above-described display panel, the pixel circuit is one of a current-drive type which supplies a driving current having a current value on the basis of the current value of the data current flowing through the data line.

According to the display panel of the invention, it is possible to suppress delay in the data line by setting a thickness of the partition wall.

THE PREFERRED EMBODIMENT OF THE INVENTION

Preferred embodiments of the invention will be described with reference to the accompanying drawings. The embodiments of the invention refer various technical limitations preferred to carry out the invention, however do not restrict the scope of the invention to the embodiments and examples illustrated in the drawings below. Throughout the description below, an abbreviated expression “EL” stands for “Electro Luminescence”.

FIG. 1is a circuit diagram of a plurality of pixels in an EL display panel1of an active-matrix driving type, employing a current-writing system. In FIG.1, only pixels of 2 rows by 3 columns is shown for simplicity, however, a practical display panel has a larger number of pixels disposed in rows and columns.

As shown inFIG. 1, the EL display panel1is provided with a plurality of scanning lines2disposed in parallel with each other, and a plurality of data lines3disposed so as to intersect the scanning lines2, and further provided with supply lines4each disposed in parallel with the scanning line2and between the adjacent scanning lines2. A pixel is formed in a rectangular area defined by the adjacent two scanning lines2and two data lines3. The EL display panel1includes a plurality of pixels which are disposed in a matrix arrangement.

Each pixel comprises a pixel circuit9which includes thin film transistors5,6and7and a capacitor8; and an organic EL element10. Hereinafter, the thin film transistor5is referred to as a switch transistor5, the thin film transistor6as a hold transistor6, and the thin film transistor7as a driving transistor7. Each of the switch transistor5, the hold transistor6and the driving transistor7may be an n-channel type of amorphous silicon transistor.

In each pixel, a gate of the switch transistor5is connected to the scanning line2, and one of the drain and the source of the switch transistor5is connected to the data line3, and the other of the drain and the source of the switch transistor5is connected to an anode of the organic EL element10, to one of electrodes of the capacitor8, and also to one of the source and the drain of the driving transistor7. The other of the source and drain of the driving transistor7is connected to the supply line4. The gate of the driving transistor7is connected to the other electrode of the capacitor8and further to one of the drain and source of the hold transistor6. The other of the drain and source of the hold transistor6is connected to the supply line4, and a gate of the hold transistor6is connected to the scanning line2.

Each of the organic EL elements10of the pixels has a cathode as a counter electrode, which is kept at a constant voltage Vcom, for example, ground potential. Concerning emission colors of the organic EL elements10, the organic EL elements10in the same row are disposed to have colors of red, green and blue, in this order. The organic EL elements10disposed in the same column has the same color. It is preferable for the cathode to have a laminated structure of an electron injection layer made of Ba having a thickness of not larger than 10 nm and a protection conductive layer, e.g., aluminum, for covering the electron injection layer, which has a higher work function than the electron injection layer. When applied with a predetermined voltage, among a thickness of Ba layer of 10 nm, 50 nm and 100 nm, the organic EL element10shows the maximal brightness at a thickness of 10 nm and shows the lowest brightness at a thickness of 100 nm.

As shown inFIG. 9, in a peripheral area of the EL display panel1, the scanning lines2are connected to a first scanning-line driver21for controlling a voltage, and the supply lines4are connected to a second scanning-line driver22for controlling a voltage, and the data lines3are connected to a data-line driver23for controlling a current. The EL display panel1is driven by these drivers in the active matrix driving manner.

FIG. 2is a timing chart showing signals to be supplied to a plurality of adjacent pixels, that is, one pixel locating at an intersection of a certain row out of a plurality of rows and a certain column out of a plurality of columns, and another pixel locating at another intersection of a row next to the above row and the above column. As shown inFIG. 2, the first scanning-line driver21applies a voltage of an ON-level, i.e., a voltage of a constant high level, to the scanning lines2successively, thereby selecting the switching transistors5and the hold transistors6successively. Meanwhile, the second scanning-line driver22applies a write voltage of a constant low level, i.e., not higher than the voltage Vcomsupplied to the cathodes of the organic EL elements, to the supply lines4successively in synchronism with an output of ON-level from the first scanning-line driver21, and thereby all the pixel circuits9on a column connected with the supply line4are successively selected every row. While the first scanning-line driver21selects the switching transistors5and the hold transistors6on each row, the data-line driver23controls a data current flow so as to allow current of current values corresponding to respective gradients to flow between the drain-source of the driving transistor7, through the data lines3in each column. Data current is a pull-out current flowing from the data lines3to the data-line driver23. The data current is a sink current which flows to the data-line driver23through the data lines3. Hereinafter, a period during which the scanning line2in a row is kept at ON-level is referred to as a “selection period” of the row, and a period during which the scanning line2in a row is kept at an OFF-level (a constant low level) is referred to as “light emitting period” of the row.

In the selection period of a row, since the scanning line2of the row is kept at ON-level, the switching transistors5and the hold transistors6of all the pixels on the row remain in an ON-state. At this time, the write voltage of the supply line4is kept at a low level, and the data-line driver23keeps a potential lower than the write voltage of the supply line4so as to allow data currents of desired current values corresponding to gradients to flow through the data lines3. Therefore, the driving transistor7is supplied with voltages such that the gate-source and the drain-source are brought in an ON state. As a result, data currents of current values corresponding to respective gradients are supplied to the data lines3from the supply lines4through the drain-source of the driving transistor7and the drain-source of the switching transistor5, thereby data currents flow in each of pixels on the row toward the data lines3. The current value of the data current is unambiguously adjusted by the data-line driver23. At this time, the potential difference between the gate and the source of the driving transistor7becomes equal to the potential difference between the drain and the source of the driving transistor7, that is, the current value is automatically set so as to correspond to the current value of the data current set by the data-line driver23to flow through the drain-source of the driving transistor7. The electric charge with a level due to the potential difference is charged in the capacitor8.

Thereafter, in the light emitting period, the scanning line2in the row is kept at OFF-level, i.e., in a constant low level, and the switching transistors5and the hold transistors6are brought in an off state. However, the potential difference between the both ends of the capacitor8is kept because of the hold transistors6being in an off state, and the potential difference between the gate and the source of the driving transistor7, which was applied in the selection period, is kept as it is. Therefore, the potential difference between the gate and the source of the driving transistor7is memorized so as to allow a current corresponding to the current value of the data current to flow during the light emitting period. During the light emitting period, even though the voltage of the supply line4is switched to a light emission voltage of a constant high level from the low level and raised to a voltage which is higher than the constant voltage Vcomat the cathode of the organic EL element10, despite the current value of the data current, the voltage between the drain and the source of the driving transistor7is set to a voltage that allows a saturation current to flow through the drain-source of the driving transistor7. Accordingly, a current value of a driving current for driving the organic EL element10is decided only by the voltage between the gate and the source of the driving transistor7. Since the voltage between the drain and the source of the driving transistor7is held as a voltage corresponding to the current value of the data current which flow between the drain and the source of the driving transistor7in the selection period, the current value of the driving current to flow to the organic EL element10in the light emitting period depends on the current value of the data current in the selection period. Thus, the driving current is supplied from the supply line4to the organic EL element10through the driving transistor7, thereby to make the organic EL element10emit light. Preferably, the current value of the driving current in the light emitting period is substantially equivalent to the current value of the data current in the selection period just before the light emitting period. As described above, the driving transistor7is connected in series with the organic EL element10, to supply the driving current to the organic EL element10.

In each pixel circuit9, there exists parasitic capacity associated with a path of the data current from the supply line4to the data line3, and therefore a certain time is required before the data current actually flowing through the pixel circuit9reaches the level of data current adjusted by the data-line driver23. When the certain time is shorter than the selection period, no trouble is caused. Meanwhile, when the certain time is longer than the selection period, the data current actually flowing through the pixel circuit9does not reach the level adjusted by the data-line driver23, and the voltage which is lower than a predetermined voltage is applied between the gate and the source of the driving transistor7, whereby the current value of the current flowing through the organic EL element10is reduced, making the organic EL element emit light only at a brightness less than a predetermined one. Therefore, the embodiment of the invention provides the optimal structure of EL display panel1.

The structure of EL display panel1will be described in particular.

FIG. 3is a schematic plan view of EL display panel1including pixels disposed in 2 rows by 6 columns. As shown inFIG. 3, between the scanning line2and the supply line4in the same row, the same number of pixel electrodes as the number of columns are disposed. Pixel electrodes as a whole are disposed in a matrix arrangement. Between data lines3adjacent to each other, pixel electrodes are disposed in the column direction. On each data line3, there is provided a partition wall20so as to coat the data line3. As shown inFIG. 9, the partition wall20has a continuous snaking structure. On a plurality of pixel electrodes12disposed between portions of the partition wall20in the column direction, an organic compound layer14is continuously formed. The organic compound layers14adjacent to each other, disposed in the row direction are separated by the partition wall20running in the column direction. The organic compound layer14includes an organic EL light emission layer which emits light when a current flows through the layer, or one or a plurality of carrier transporting layers. The organic compound layer14is formed by pouring a solution which is prepared by dissolving a material for the organic compound layer14in a solvent, or by pouring a dispersion liquid in which a material for the organic compound layer14is dispersed, between the adjacent partition wall portions20and20and thereafter by drying them. The partition wall20has an electric insulation property and is made of a photosensitive organic resin such as polyimide. In the case where the partition wall20is made of an organic resin, a liquid repellent finishing is subjected to the outermost surface of the partition wall20by replacing C—H bonding among constituent elements of the partition wall20with C—F bonding to enhance the liquid repellency of the partition wall20, resulting in that the partition wall20shows a low relative dielectric constant.

FIG. 4is a plan view illustrating electrodes for one pixel.FIG. 5is a cross sectional view taken along the line V-V ofFIG. 4. As shown inFIGS. 4 and 5, the pixel electrode12which is an anode of the organic EL element10is formed under the organic compound layer14, and the counter electrode16which is a cathode of the organic EL element10is formed above the organic compound layer14. That is, the organic EL element10comprises a laminated structure of the pixel electrode12, the organic compound layer14and the counter electrode16, which are stacked in the above order from bottom. The pixel electrodes12for respective pixels are formed independently from one another and arranged in a matrix arrangement. The counter electrode16is one electrode provided commonly to all the pixels and formed all over the panel surface, with covering also partition walls20. Further, the counter electrode16is covered with the protection insulating film18. InFIG. 4, illustration of the pixel electrodes12are omitted for simplicity, however, the pixel electrode12is formed in a region including a rectangular frame portion at the left to the capacitor8and a portion corresponding to the capacitor8.

Each of the pixel electrodes12has a transparent conductive film made of tin doped indium oxide (ITO), zinc doped indium oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (znO), and/or cadmium-tin oxide (CTO).

The organic compound layer14has, for example, a double layer structure formed on the pixel electrodes12, including a hole carrying layer and a light emission layer stacked on the hole carrying layer. The hole carrying layer is made of a conductive polymer such as PEDDOT (polyethylenedioxythiophene) and a dopant such as PSS (polystyrene sulfone acid). Conjugate double bond polymer luminescence materials such as polyphenylene vinylene luminescence materials and polyfruorene luminescence materials are preferably used to form the light emission layer. The organic compound layer14may have a single layer structure or a laminated structure of more than two layers.

The counter electrode16is made of a material having a work function lower than the pixel electrode12. For example, the counter electrode16is made of a material such as indium, magnesium, calcium, lithium, valium or a rare-earth metal, or an alloy including at least one sort of the above materials. Further, the counter electrode16may have a laminated structure of layers made of the above material, or the laminated structure with an alloy layer-stacked on top of the above laminated structure. More specifically, the counter electrode16may have the laminated structure comprising a layer of high purity valium having a low work function, formed on the surface boundary of the organic compound layer14and a layer of aluminum coating over the valium layer, or the laminated structure comprising lithium layer and aluminum layer stacked on top of the lithium layer.

On the front surface of a transistor array panel30, The scanning lines2, data lines3, supply lines4, switching transistors5, hold transistors6, driving transistors7capacitors8, pixel electrodes12and partition walls20are formed.

The switching transistor5, the hold transistor6and the driving transistor7are produced to form a reverse stagger structure. More particularly, each of the switching transistor5, the hold transistor6and the driving transistor7comprises a gate G formed on the insulating substrate32, a gate insulating film34covering the gate G, a semiconductor film SC to face the gate G with respect to the gate insulating film34, a channel protection film BL formed at the central portion of the semiconductor film SC, impurity semiconductor films ISC formed separately from each other on both sides of the semiconductor films SC, a drain D formed on one of the impurity semiconductor films ISC, and a source S formed on the other of the semiconductor films ISC. The gate insulating film34is formed all over the area of the data lines3and supply lines4, as shown inFIG. 9. Bumps of the data-line driver23are connected to terminals of the data lines3which are exposed through contact holes provided in the gate insulating film34. The counter electrode16covers the whole area of the partition wall20and is formed so that the peripheral portions16asurround the partition wall20. Therefore, as shown inFIG. 5, even if the counter electrode16is ruptured at the edges20aof the partition wall20, since the peripheral portions16aof the counter electrode16where no partition wall20are provided, are continuous, the voltage level throughout the counter electrode16can be equalized.

The gates of the switching transistor5, the hold transistor6and the driving transistor7are formed by patterning a whole area conductive film formed on the insulating substrate32. Not only the gates but also data lines3and one electrode of the capacitor8are formed by patterning the whole area conductive film.

The gate insulating film34is formed to cover all over the surface of the insulating substrate32. The gates of the switching transistors5, hold transistors6, and driving transistors7; the data lines3; and the one electrode of the capacitor8are covered with common gate insulating film34.

The sources and drains of the switching transistors5, the hold transistors6and the driving transistors7are formed by patterning the conductive film formed all over the surface of the gate insulating film34. In addition to the gates and the drains, the scanning lines2and supply lines4and the other electrode of the capacitor8are also formed by patterning the conductive film. Therefore, the gate insulating film34is held between the data lines3and the scanning lines2, and the gate insulating film34is held between the data lines3and the supply lines4. The switching transistors5, the hold transistors6, the driving transistors7, the scanning lines2, supply lines4and the other electrodes of the capacitors8are covered with a common overcoat insulating film36. The upper surface of the overcoat insulating film36forms the upper surface of the transistor array panel30. On the upper surface of the over coat insulating film36, a planarizing film made of a resin or the like may be formed to smooth an uneven surface caused by the scanning lines2, the supply lines4, the switching transistors5, the hold transistors6, the driving transistors7and the capacitors8. In this case, the smoothed surface of the planarizing film forms the surface of the transistor array panel30.

In each pixel, the gates of the switching transistor5and the hold transistor6are connected to the scanning line2through a contact hole44formed in the gate insulating film34, and one of the drain and the source of the switching transistor5is connected to the data line3through a contact hole38formed in the gate insulating film34, and further one of the drain and the source of the hold transistor6is connected to one electrode of the capacitor8through a contact hole40formed in the gate insulating film34. The other electrode of the capacitor8is connected to the pixel electrode12through a contact hole42formed in the over coat insulating film36.

The gate insulating film34and the over coat insulating film36are made of the same insulation material, preferably of silicon nitride or oxide silicon. The partition wall20is formed above the data line3, and further the counter electrode16is formed so as to cover the partition wall16. As a result, the partition wall20and the over coat insulating film36are held between the counter electrode16and data lines3, whereby a parasitic capacitance Cpdis produced.

The parasitic capacitance Cpdis represented by the following equation (1).

where ∈0denotes the vacuum dielectric constant, ∈adenotes a relative dielectric constant of the gate insulating film34and the over coat insulating film36, Dadenotes the over all film thickness of the gate insulating film34and over coat insulating film36, ∈bdenotes a relative dielectric constant of the partition wall20, and Dbdenotes a thickness of the partition wall20. In the case where the gate insulating film34and over coat insulating film36are made of the same material and the channel protection film BL is held between the counter electrode16and data lines3, Dawill be the over all film thickness of the gate insulating film34, over coat insulating film36and channel protection film BL.

The lower the parasitic capacitance Cpdis, the more preferable. When assuming that, within the selection period, the parasitic capacitance associated with the whole circuit for data current from the supply lines4to the data lines3is expressed by Ctotal, in view of the condition that the parasitic capacitance Cpdgives no serious effect to design of the transistors5,6and7, it is preferable for the data lines3not to cause considerable delay that the parasitic capacitance Cpdis not larger than 20% of the parasitic capacitance Ctotal. When the thicknesses of the respective gate insulating film34, the over coat insulating film36and the channel protection film BL of the transistors5,6and7are changed, a characteristic of TFT is so seriously affected that the whole circuit design have to be changed. Therefore, it is preferable that the thicknesses of the respective gate insulating film34, over coat insulating film36and channel protection film BL of the transistors5,6and7are kept constant. Similarly, when insulation materials of the gate insulating film34, over coat insulating film36and channel protection film BL are changed, that is, the relative dielectric constant of the insulation material is changed, it is required to change the design of the whole circuit. Therefore, it is preferable not to change the insulation material of the insulation films34,36and BL. The equation (1) shows that a parameter which can be varied without inviting a serious problem is the thickness Dbof the partition wall20. In order to keep the parasitic capacitance Cpdless than 5% of the parasitic capacitance Ctotal, it is necessary to use a partition wall of layers stacked to a considerable thickness, and usage of such a thick partition wall is not preferable in view of a production process of the partition wall. As a result, the thickness Dbof the partition wall20is set so as to meet the following expression (2).

The parasitic capacitance Ctotalincludes capacitance components such as parasitic capacitance at an overlapping potion of the data lines3and scanning lines2, parasitic capacitance at an overlapping potion of the data lines3and supply lines4, parasitic capacitance relating to the product of parasitic capacitance between the gate and source of the switching transistors5corresponding to the number of the scanning lines2(i.e. capacitance between one of the data lines3and the switching transistors5connected to supply lines4), parasitic capacitance at the gates of the driving transistors7, and capacitance of the pixels12and capacitors8.

Other setting conditions of the EL display panel1are set as follows: a width of the pixel (or a pitch of the pixels including the width of the partition wall20) is not less than 330 μm (in the case of VGA, where a size of EL display panel1is 10.4″) and not larger than 600 μm (in the case of WXGA, where a size of EL display panel1is 37″), the number of the scanning lines2is 768 (in the case of WXGA, where a screen is divided into upper and lower half portions, each including 384 scanning lines), 480 (VCA), or 1080 (in the case of a full UD, where a screen is divided into upper and lower half portions, each including 540 lines), a pixel capacitance is 0.252 fF/μm2, an aperture ratio (a ratio of a light emitting area against a pixel area) is 30%, the selection period is not longer than 43.4 μsec. (in the case of the longest selection period at 60 Hz drive, that is, in the case of the minimum number of scanning lines2, WXGA where the screen divided into upper and lower half portions, each including 384 lines), the minimum luminance current is not less than 5.2 nA/dot (where a size of EL display panel1is 10.4″, VGA, and a gradient is 8 bits, the maximum luminance is from 300 nit to 500 nit, and a characteristic of pixel is set to 12.0 cd/A).

When the pixel can take 256 luminance gradients, the maximum luminance gradient is set to the 255thgradient with the no light emission state being set to the 0thgradient. For well-balanced display with no gradient reversed every gradient, it is preferable to limit the parasitic capacitance Cpdsuch that a writing ratio will be larger than 20% at the second gradient and the writing ratio will be larger than 90% at 255thgradient, where the writing ratio is the measure of a ratio of the driving current actually flowing through the organic EL element10to the data current flowing through the data line3controlled by the data-line driver23. The reasons for setting the writing ratio at the second gradient, not at the first gradient, which is the lowest gradient except the 0thgradient (the no light emitting state) resides in that a feed through voltage has too large an effect, and is not appropriate as a condition for the writing ratio caused by the parasitic capacitance.

When polyimide is used to make the partition wall20, the relative dielectric constant ∈bof the partition wall20falls within the range from 2.6 to 3.4. For example, when the relative dielectric constant ∈bof the partition wall20is 3.0, a relationship between the parasitic capacitance Cpdand the thickness Dbof the partition wall20is shown in the graph ofFIG. 6.

Assuming that various conditions are set as given in TABLE 1 with respect to EL display panel, where each threshold voltage Vthof the switching transistor5, the hold transistor6and the driving transistor7is set to 0.5 V, each component of the parasitic capacitance Ctotalhas been calculated with respect to the whole current flow circuit covering the supply lines4and the data lines3during the selection period, where the gate insulation film34, channel protection film BL and over coat insulation film36are made of silicon nitride, their relative dielectric constant has been set to 6.4, and the gate insulation film34and channel protection file BL are 420 nm thick in total, and further the over coat insulation film36is 200 nm thick. The calculation results are given in TABLE 2.

In TABLE 2, “C1” denotes parasitic capacitance at an overlapping portion of the data lines3and supply lines4, “C2” denotes parasitic capacitance at an overlapping portion of the data lines3and scanning lines2, “C3” denotes parasitic capacitance relating to the product of the number of the scanning lines and the switching transistors5, “C4” denotes parasitic capacitance at the gate of the driving transistor7, and “C5” denotes capacitance of the pixel electrodes12and the capacitor8. Further, in TABLE 2, “UPPER LIMIT OF Cpd” denotes parasitic capacitance Cpdat which the thickness of the partition wall20calculated using the expression (2) and capacitances C1to C5can reach the lower limit, and “LOWER LIMIT OF Cpd” denotes parasitic capacitance Cpdat which the thickness of the partition wall20calculated using the expression (2) and capacitances C1to C5can reach the upper limit. Further, in TABLE 2, “LOWER LIMIT OF Ctotal,” denotes parasitic capacitance Ctotalwhere the parasitic capacitance Cpdis at the lower limit, and “UPPER LIMIT OF Ctotal” denotes parasitic capacitance Ctotalwhere the parasitic capacitance Cpdis at the upper limit.

Output gradient characteristics of the display panel1of various sizes are shown inFIG. 7, where the parasitic capacitance Cpdhas been set to the lower limit. Writing ratios at the second gradient and 255 gradient are given in TABLE 3. InFIG. 7, the lateral axis of “Input data” represents in units of 8 bits gradients of data current controlled by the data-line driver23to flow through the data lines3, and the longitudinal axis of “Output data” represents in units of 8 bits gradients of the driving current flowing through the organic EL elements10. In each case, data takes not less than 256 as a matter of convenience for easy review, but in the case of 8 bits, data reaches up to 255 in effect. It will be understood from TABLE 3 that the writing ratio is not less than 20% at the second gradient and the writing ratio is not less than 90% at 255thgradient or at the maximum luminance.

In TABLE 4 are given the lower limits of the thicknesses Db, i.e. the thicknesses Dbof the partition wall20at which the parasitic capacitance Cpdis not larger than 20% of the parasitic capacitance Ctotal, and in TABLE 5 are given the upper limits of the thicknesses Db, i.e. the thicknesses Dbof the partition wall20at which the parasitic capacitance Cpdis not less than 5% of the parasitic capacitance Ctotat.

As will be understood in TABLE 4, thicknesses of the partition wall20having the minimum required relative dielectric constant ∈bof 2.6 to 3.4 fall within the range of 2.0 to 3.5 μm. Further, it will be understood from TABLE 5 that the upper limits of the thicknesses of the partition wall20having the relative dielectric constant ∈bof 2.6 to 3.4 limited by parasitic capacitance fall within the range of 10.1 to 17.7 μm.

In the above embodiment of the invention, the thicknesses of the partition wall20are optimized based on the parasitic capacitance relating to the data lines3. Hereinafter, it will be described that the thicknesses of the partition wall20are optimized based on properties of films of the organic EL compound layers of the organic EL element10. The organic compound layers14are formed by pouring into portions defined by the partition wall20and20solution of a material to be used to make the organic compound layer14or fluid dispersion of the material to be used to make the organic compound layer14. In the case where the organic compound layer14is made by an ink jet method, one to several tens of droplets are discharged every pixel depending on a volume of droplet. The thickness of the partition wall20can be expressed by an expression (3), which is required to prevent the droplets form running over the partition wall20to the adjacent pixel. Relationships between heights of droplets and widths of the pixel are shown inFIG. 8. In the expression (3), a reference W denotes a width of the partition wall20, L denotes a length of a pixel, P a pitch of pixels, and a reference ρ denotes a droplet volume. In short, a volume ρ for involving droplet for one pixel will be given by the following equation: volume ρ=width (P−W)×length L×height H. If the thickness Dbof the partition wall20is larger than the height H calculated from the above equation, the droplets do not run over the partition wall20to the adjacent pixel, which is expressed by the following expression:
Db>ρ/(P−W)·L  (3)

Droplets for forming the organic compound layers14are applied between the partition walls20,20. The droplets each have a volume of 60 pl, and reach a height as shown inFIG. 8. InFIG. 8, the lateral axis represents a width of the pixel and the longitudinal axis represents a height of the droplets. In VGA of 10.4″, a width of three RGB pixels is 330 μm. In WXGA of 32″, a width of three RGB pixels is 510 μm. In WXGA of 37″, a width of three RGB pixels is 600 μm. As will be understood fromFIG. 8, one droplet may be enough for forming the organic compound layer14for each pixel in VGA, but since the partition wall20requires its thickness of 2.0 μm at the minimum, which is three times the width of a pixel, the partition wall20needs to have the thickness of 6.0 μm finally to obtain a layer having an even thickness allover the surface by dropping one droplet to each of three pixels.

In the embodiments of the invention described above, since the thickness Dbof the partition wall20is set so as to satisfy the expression (2), the delay of data current caused by the parasitic capacitance between the counter electrode16and data lines3can be suppressed.