SRAM WITH DIPOLE DOPANT THRESHOLD VOLTAGE MODULATION FOR GREATER READ STABILITY

Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

BACKGROUND

Integrated circuit (IC) devices often include static random-access memory (SRAM). Microprocessor chips, for example, dedicate a significant amount of chip area to SRAM arrays as a lowest level cache storing bits for processing by arithmetic logic units (ALUs). An SRAM array includes a plurality of SRAM bit cells.FIG.1illustrates a conventional six-transistor (6T) SRAM bit-cell100that includes six transistors comprising two p-channel load or “pull-up” transistors120and four n-channel transistors that further comprise two drive or “pull-down” transistors125and two pass-gate transistors130.

During operation of bit-cell100, when a bitline (BL) is driven to Vcc and bitline bar (BLB) is drive to Vss, inverter node N1is exposed to BLB, which can induce a read disturbance. Accordingly, many SRAM implementations include read assist circuitry (not depicted inFIG.1) coupled to SRAM bit-cell100. Such read assist circuitry may have various topologies but is generally operable to lower the wordline (WL) voltage, and thereby weaken the N1node exposure to BL/BLB. Such read assist circuitry can occupy significant chip area. Accordingly, improvements to an SRAM bit-cell architecture that can reduce the overhead of SRAM read assist circuitry is advantageous.

DETAILED DESCRIPTION

As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any possible combinations of one or more of the associated listed items.

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or layer over or under another may be directly in contact or may have one or more intervening materials or layers. Moreover, one material between two materials or layers may be directly in contact with the two materials/layers or may have one or more intervening materials/layers. In contrast, a first material or layer “on” a second material or layer is in direct contact with that second material/layer. Similar distinctions are to be made in the context of component assemblies.

The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.

Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent (e.g., <50 at. %). The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent. The term “substantially” means there is only incidental variation. For example, composition that is substantially a first constituent means the composition may further include <1% of any other constituent. A composition that is substantially first and second constituents means the composition may further include <1% of any constituent substituted for either the first or second constituent.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.

Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” or “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value.

In accordance with embodiments herein, integrated circuit (IC) static random-access memory (SRAM) comprises access or pass-gate transistors with a different threshold voltage (Vt) than pull-down transistors. For exemplary embodiments where pass-gate transistors have a higher Vtthan pull-down transistors, drive current of the pass-gate transistors is reduced relative to that of the pull-down transistors for a reference bit-cell design where pull-down and pass-gate transistor architectures are otherwise substantially identical. Accordingly, read instability of a bit-cell, and/or overhead associated with read assist circuitry that would otherwise be needed to modulate the wordline voltage, may be reduced.

FIG.2is a plan view of a 6T-SRAM bit-cell layout200with a dipole dopant-based threshold voltage modulation or contrast between pull-down transistor125and pass-gate transistor130, in accordance with some embodiments. Pull-down transistor125includes a gate insulator291surrounding a channel region of nanoribbons260. Pass-gate transistor130includes a gate insulator292surrounding a channel region of nanoribbons260. Gate insulator291includes an amount of a Vt-shifting dipole dopant that differs from an amount of Vt-shifting dipole dopant within gate insulator292. Dipole dopant threshold voltage modulation between the two transistors may be utilized, for example, to lower the threshold voltage of the pull-down transistor relative to that of the pass-gate transistor.

In some exemplary embodiments where the Vt-shifting dipole dopant is an N-dipole dopant that reduces the magnitude of transistor threshold voltage of an NMOS transistor, an amount of the Vt-shifting N-dipole dopant within gate insulator291is greater than the amount of N-dipole dopant within gate insulator292. In some further embodiments, gate insulator292lacks any of the Vt-shifting N-dipole dopant present within gate insulator291. In other embodiments, both gate insulators291and292have a non-zero amount of the Vt-shifting N-dipole dopant, for example where the threshold voltage of both the pull-down and pass-gate transistors125,130have threshold voltages that are reduced relative to other NMOS transistors of an IC, which may either be within bit-cell105, or external to bit-cell105.

An N-dipole dopant that reduces transistor threshold voltage of an NMOS transistor will increase the magnitude of transistor threshold voltage of an PMOS transistor. Similarly a P-dipole dopant that reduces transistor threshold voltage of a PMOS transistor will increase the magnitude of transistor threshold voltage of an NMOS transistor. Accordingly, in alternative embodiments where the Vt-shifting dipole dopant is a P-dipole dopant, an amount of the Vt-shifting P-dipole dopant within gate insulator292is greater than the amount of P-dipole dopant within gate insulator291. In some further embodiments, gate insulator291lacks any of the Vt-shifting P-dipole dopant present within gate insulator292. In other embodiments, both gate insulators291and292have a non-zero amount of the Vt-shifting P-dipole dopant, for example where the threshold voltage of both the pull-down and pass-gate transistors125,130have threshold voltages magnitudes that are increased (albeit by different amounts) relative to other NMOS transistors of an IC, which may either be within bit-cell105, or external to bit-cell105.

In the exemplary 6-T SRAM layout200, pull-down transistor125and pass-gate transistor130include separate regions of a nanoribbon260that is continuous over a length spanning one side of a bit-cell105. Over this length, nanoribbon260has substantially the same transverse width Wi to illustrate advantageous embodiments where area of bit-cell105(i.e., cell height) and/or layout complexity is minimized However, the dipole threshold voltage tuning embodiments described herein may be readily applied to SRAM bit-cell layouts other than 6-T SRAM layout200. For example, in some other bit-cell layouts, ribbon width may be modulated between pull-down transistor125and pass-gate transistor130in conjunction with the dipole dopant-based threshold voltage modulation described in detail below. However, in contrast to nanoribbon width modulation, which may impact the cell height of bit-cell105, the illustrated embodiment represents an advantageously volumeless implementation.

As further illustrated inFIG.2, pull-down transistor125and pass-gate transistor130include impurity doped semiconductor275of a first conductivity type (e.g., n-type), which extends an epitaxial width WEbeyond a sidewall of nanoribbons260. In the exemplary embodiment, epitaxial width WEis substantially the same for both pull-down transistor125and pass-gate transistor130. A first semiconductor terminal (e.g., source) of pull-down transistor125comprising impurity doped semiconductor275is coupled to Vss through a contact metallization280. A first semiconductor terminal (e.g., source) of pass-gate transistor130comprising impurity doped semiconductor275is coupled to a bitline BL through contact metallization280.

A gate electrode285of pull-down transistor125is coupled to load/pull-up transistors120. The gate electrode285of pass-gate transistor130is coupled to a wordline WL. A second semiconductor terminal (e.g., drain) of pull-down transistor125is in direct contact with a second semiconductor terminal (e.g., drain) of pass-gate transistor130, each of which comprises impurity doped semiconductor275that is further coupled through contact metallization280to pull-up transistors120.

Bit-cell105includes a second pull-down transistor125that comprises a portion of another stack of nanoribbons260and another instance of gate insulator291. Another pass-gate transistor130couples an output of the inverters to a bitline bar BLB. This second instance of pass-gate transistor130comprises another portion of the stack of nanoribbons260, which is coupled to another wordline WL through another instance of gate insulator292. In some examples where pass-gate transistors130and pull-down transistors125are both n-type/n-channel devices, pull-up transistors120are p-type/p-channel transistors comprising impurity-doped semiconductor material265of a second, complementary conductivity type (e.g., p-type). Transistors UO and130form two cross-coupled inverters where the output of one inverter is the input to the other Inverter.

Pull-up transistors120comprise nanoribbons260, also of a ribbon width Wi. Pull-up transistor ribbon width may however also vary with implementation. For example, pull-up transistor ribbon width may be greater or smaller than either pull-down transistor ribbon width or pass-gate transistor ribbon width. Pull-up transistors120comprise a gate insulator290, which either includes a Vt-shifting dipole dopant, or not. If gate insulator290does include a Vt-shifting dipole dopant, it may include an amount that is either more than or less than that in either gate insulator291or292and that Vt-shifting dipole dopant may be either of the same type (e.g., N-dipole), or not (e.g., P-dipole). In some embodiments where gate insulator291comprises more N-dipole than gate insulator292, and the drive strength of pull-up transistors120is less than that of pull-down transistors125, gate insulator290has more of the Vt-shifting N-dipole dopant than gate insulator292and may have substantially the same Vt-shifting N-dipole dopant as gate insulator291. In other embodiments where gate insulator291comprises more N-dipole than gate insulator292, gate insulator290has substantially the same amount of Vt-shifting N-dipole dopant as gate insulator292so that the drive strength of pull-up transistors120is less than that of pass-gate transistors130.

In still other embodiments where gate insulator291comprises less P-dipole dopant than gate insulator292, gate insulator290has more Vt-shifting P-dipole dopant than gate insulator291, for example so that the drive strength of pull-up transistors120may be greater than that of pass-gate transistors130and/or pull-down transistor125.

FIG.3is an isometric sectional view of an SRAM structure portion300further illustrating a gate-all-around stacked nanoribbon structure of pull-down and pass-gate transistors125,130, in accordance with some nanoribbon embodiments. The features illustrated inFIG.3may be present in any of the embodiments illustrated inFIG.2, for example. Likewise, the features illustrated inFIG.2may be present in any of the embodiments illustrated inFIG.3.

As shown inFIG.3, transistors125and130each have a stacked, gate-all-around transistor architecture. Nanoribbons260include an uppermost nanoribbon260N stacked in vertical alignment with a lowest nanoribbon260A. The exemplary ribbon-or-wire (RoW) transistor stack structure is illustrated as including three nanoribbons, but such a transistor stack structure may include any integer number of channel regions (e.g., 2, 3, 4, 5 . . . 10 . . . 20, etc.) as embodiments herein are not limited in this respect.

Within pull-down transistor125, a channel region of nanoribbons260A-260N is surrounded by a gate stack that includes gate insulator291. Gate insulator291is, in-turn, further surrounded by a gate electrode285. Impurity-doped semiconductor275is at terminal ends of nanoribbons260A-260N, on opposite sides of the gate stack. Pass-gate transistor130includes the same number of nanoribbons260A-260N surrounded by a gate stack that includes gate insulator292. Gate insulator292is further surrounded by a gate electrode285. In accordance with the illustrated embodiment, all nanoribbons260A-260N are coupled together in electrical parallel. The cumulative cross-sectional channel area is therefore a function of ribbon thickness (e.g., z-dimension) and ribbon width (e.g., x-dimension), which are both substantially the same in the illustrated embodiment.

In some embodiments, nanoribbons260are crystalline semiconductor. Although the crystalline semiconductor includes polycrystalline thin film material, the crystalline semiconductor may be advantageously substantially monocrystalline In some such embodiments, the crystallinity of nanoribbons260is cubic with the top surfaces having crystallographic orientation of (100), (111), or (110), for example. Other crystallographic orientations are also possible. In some embodiments, nanoribbons260are a substantially monocrystalline group IV semiconductor material, such as, but not limited to substantially pure silicon (e.g., having only trace impurities), silicon alloys (e.g., SiGe), germanium alloys (GeSn), or substantially pure germanium (e.g., having only trace impurities).

Nanoribbons260may also have any of these same exemplary compositions in alternative polycrystalline or amorphous embodiments, for example where the stack of nanoribbons260A-260N has been fabricated from a stack of thin film semiconductor material layers. Polycrystalline or amorphous embodiments of nanoribbons260may also include semiconducting metal oxides, such as IGZO. Although nanoribbons260are illustrated as having a substantially homogenous composition, they may alternatively comprise one or more semiconductor heteroj unctions that, for example further include a first semiconductor material adjacent to a second semiconductor material.

Sub-channel material301is under the stack of nanoribbons260. Sub-channel material301may have any composition and/or microstructure. For example, in some embodiments where nanoribbons260are of a Group IV material (e.g., silicon), sub-channel material301is also a Group IV material (e.g., silicon). In some further embodiments where nanoribbons260are substantially monocrystalline, sub-channel material301is also substantially monocrystalline, and has the same crystallinity and/or crystal orientation as that of nanoribbons260. In alternative embodiments, sub-channel material301is a buried insulator layer (e.g., SiO2), for example of a semiconductor-on-insulator (SOI) substrate.

Impurity doped semiconductor275is electrically and physically coupled to opposite sides of channel regions of nanoribbons260A-260N. In this example, impurity doped semiconductor275comprises faceted epitaxial material that has been grown, for example laterally from an end portion of channel regions embedded within gate electrode285, and/or from cantilevered source/drain ends of nanoribbons260A-260N, and/or from sub-channel material301. Impurity doped semiconductor275need not be epitaxial material, in which case the facets shown inFIG.3may not be present. Impurity doped semiconductor275also need not merge into a unitary body, in which case cantilevered source/drain nanowire ends may be individually in contact with contact metallization280.

Impurity-doped semiconductor275may comprise one or more electrically active impurities. In some embodiments, for example, impurity-doped semiconductor275is a Group IV semiconductor material (e.g., Si, Ge, SiGe or GeSn alloy). For exemplary embodiments where pull-down and pass-gate transistors125and130are both NMOS, impurity doped semiconductor275comprises an n-type impurity such as phosphorus, arsenic, or antimony.

Gate electrode285co-axially clads the insulator-clad channel regions of nanoribbons260to provide gate-all-around control of channel conductivity. Gate electrode285may include any suitable workfunction metal, such as n-type workfunction metal, and is advantageously substantially the same for both pull-down transistor125and pass-gate transistor130. Suitable n-type work function metals include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides that include these elements (e.g., titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide and aluminum carbide).

Gate insulators291and292may have any composition, and may, for example, include a high-k material (e.g., with a bulk relative permittivity greater than 8). As described further below, a composition of gate insulator291is distinct from that of gate insulator292by an amount of Vt-shifting dipole dopant. In exemplary embodiments, the Vt-shifting dipole dopant includes a metal species distinct from any other within gate insulators291,292. The dipole dopant may be diffused within gate insulators291and/or292, to be in close proximity to a channel region of nanoribbons260. During manufacture, gate insulators291and292may be exposed to differing amounts, or types of the dipole dopant to provide a Vtcontrast between pull-down transistor125(e.g., with a lower Vt) and gate-pass transistor130(e.g., with a higher

In exemplary embodiments, the metal species of a Vt-shifting dipole dopant is a rare earth and may be introduced into at least gate insulator291, which alters the pull-down transistor threshold voltage from a reference threshold voltage the transistor would otherwise have in absence of the Vt-shifting dipole dopant. In exemplary embodiments where pull-down transistor125is an n-channel device, an N-type Vtshifting dipole is present within gate insulator291. Accordingly, the threshold voltage of pull-down transistor125is a result of both a metal-semiconductor work function difference of gate electrode285and nanoribbons260, and the amount of Vtshifting N-dipole dopant within gate insulator291. For embodiments where gate insulator292lacks such a Vtshifting N-dipole material, the threshold voltage pass-gate transistor130is primarily the result of the metal-semiconductor work function difference of gate electrode285and nanoribbons260.

In other embodiments where pull-down transistor125is an n-channel device, a P-type Vtshifting dipole is absent from gate insulator291, but present within gate insulator292. Hence, gate insulator292may be dipole doped with the same P-dipole dopant that may be similarly introduced into a PMOS pull-up transistor, for example as a means of achieving a desired Vtfor the PMOS pull-up transistor while concurrently providing a threshold voltage contrast between NMOS pull-down transistor125and pass-gate transistor130described herein.

InFIG.3, planes A, B C are demarked by dashed lines. Plane A is a “gate-cut” plane that passes through a transverse width of gate electrode285and through a longitudinal length of nanoribbons260. Plane B is a “ribbon-cut” plane that passes through a transverse width of nanoribbons260and through a longitudinal length of gate electrode285of pull-down transistor125. Plane C is a another “ribbon-cut” plane that passes through a transverse width of nanoribbons260and through a longitudinal length of gate electrode285of pass-gate transistor130.

FIG.4Aillustrates a cross-sectional view of transistors125,130along the A plane introduced inFIG.3, in accordance with some embodiments.FIG.4Billustrates a cross-sectional view of pull-down transistor125along the B plane introduced inFIG.3, in accordance with some embodiments.FIG.4Cillustrates a cross-sectional view of pass-gate transistor130along the C plane introduced inFIG.3, in accordance with some embodiments.

Referring first toFIG.4A, nanoribbons260are bodies of semiconductor material that extend through channel regions of both transistors125and130. Along the pull-down and pass-gate channel lengths, gate electrode285clads each of gate insulator291and gate insulator292. Gate insulators291and292further clad nanoribbons260. In this example, nanoribbons260also extend through a dielectric spacer411. In some embodiments, nanoribbons260may also extend through impurity-doped semiconductor275as denoted by dashed lines inFIG.4A. In alternative embodiments, nanoribbons260may be completely absent beyond dielectric spacer411with impurity-doped semiconductor275then being a unitary body intervening between two separate stacks of nanoribbons260.

As further shown inFIG.4BandFIG.4C, nanoribbons260may have been patterned from a fin of a substrate material layer, for example having the dashed nanoribbon sidewalls460. The slightly positive slope of sidewalls460results in each of nanoribbons260A-260N having a trapezoidal slab profile representative of structural asymmetry associated with front-side transistor fabrication. Such asymmetry may be a result of nanoribbon sidewall460evolving during subtractive patterning of a fin into a stack of semiconductor materials, for example. Although nanoribbons260are illustrated as having a transverse (x) width greater than their vertical thickness, nanoribbons260may instead have a vertical (z) thickness greater than, or substantially equal to, their transverse width.

Although gate insulator stack thicknesses may vary with technology generation, in some exemplary embodiments where an SRAM bit-cell is operable at voltages under 1V (e.g., 0.6 V-0.8V), gate insulator291and292have a thickness less than 3 nm (e.g., 1.5-3.0 nm). Gate insulators291and292may include any number of material layers. In some exemplary embodiments, both of gate insulators291and292include a thermal (chemical) oxide in addition to a high-k material. The chemical oxide may be present only on interfaces with nanoribbons260. In some embodiments where nanoribbons are substantially pure silicon, the chemical oxide layer comprises predominantly silicon and oxygen. The chemical oxide may have any thickness, but in some examples is at least 1.0 nm. Gate insulators291and292may therefore be considered a stack of both a chemical oxide and a high-k material.

Both gate insulators291and292may have a high-k material of substantially the same chemical composition. The high-k material composition(s) may be any known to be suitable for a transistor gate insulator and that has a bulk relative permittivity greater than 8. One exemplary high-k material has a composition of MlOx where M1is a transition or rare earth metal. Examples include a metal oxide comprising predominantly hafnium (e.g., HfOx), a metal oxide comprising predominantly aluminum (e.g., AlOx), a metal oxide comprising predominantly magnesium (e.g., MgO), a metal oxide comprising predominantly lanthanum (e.g., LaOx), or a metal oxide comprising predominantly zirconium (e.g., ZrOx). In other examples, the high-k material is an alloyed metal oxide comprising primarily two or more metals (e.g., HfAlOx, HfZrOX) In some further embodiments, the high-k material further includes silicon. For example, metal silicates, such as, but not limited to HfSiOx, or ZrSiOx, may also be suitable a high-k material for insulators291and292.

While both gate insulators291and292may include the same chemical oxide and same high-k material, the two gate insulators differ compositionally at least in the amount of a Vtshifting dipole present. In exemplary embodiments, the Vtshifting dipole comprises a metal M2and may advantageously be an oxide of a rare earth metal that is distinct from any other metal present gate insulators291and292. The chemical compositions of gate insulator291and292are therefore different by at least the amount (concentration) of this dipole dopant metal species.

As noted above, in some embodiments dipole dopant metal M2is substantially absent from gate insulator292. However, in other embodiments dipole dopant metal M2is present in gate insulator292, but at lower concentration than within gate insulator291. In still other embodiments where a dipole dopant metal is associated with a dipole of complementary type, M2may be present in gate insulator292, but absent from, or present at a lower concentration in, gate insulator291. Any of these embodiments may accordingly provide the Vtthreshold contrast between pass-gate and pull-down transistors described herein. Whether associated with an N-dipole or P-dipole, the contrasting amounts of dipole dopant metal M2may be determined through chemical analysis of the gate insulators291and292, for example by STEM-EELS (electron energy-loss spectroscopy)/EDS (energy dispersive x-ray spectroscopy), or 2.5D TOF-SIMS (time-of-flight secondary ion mass spec spectroscopy).

Within at least insulator291, an exemplary dipole dopant metal M2may be present within a chemical oxide layer, and therefore in very close proximity (e.g., within 1.0 nm) to nanoribbons260. For such embodiments, gate insulators291and292have chemical oxides that differ by the amount of metal M2present. The dipole dopant metal M2may be substantially absent from the high-k material or may be present within high-k material in addition to (or instead of) being within chemical oxide. In some embodiments of gate insulator291where dipole dopant metal M2is present within high-k material, the concentration of the dipole dopant metal M2within the high-k material is less than the concentration of high-k metal M1within the high-k material. Hence, the high-k material may still be considered primarily M1Oxwith some dipole metal M2present as a dipole dopant. In some examples where the metal species M2is associated with an N-dipole, the concentration of the metal species M2to the concentration of the metal species M1within gate insulator291is between 0.1 and 0.2. As a further example, a ratio of the concentration of the metal species M2to the concentration of the metal species M1within gate insulator292is between 0 and 0.1.

Dipole dopant metal M2may be present within insulator291as non-ionic oxide (e.g., M2Ox) or as an ionic oxide. Exemplary ionic oxides may further comprise silicon (e.g., as a silicate) when dipole dopant metal M2is within the chemical oxide, or may further comprise metal M1(e.g., as a hafnate) when M2is within the high-k material (e.g., HfOx). The dipole metal M2may be any metal that forms a stable dipole compound, including metals known to be suitable as high-k dielectric materials as well as metals that form compounds having somewhat lower dielectric constants. For example, any of the metals listed above as suitable choices for the high-k material may also be suitable as dipole dopant metal M2. Dipole dopant metal M2may be selected based on dipole properties of compounds it forms within the chemical oxide and/or high-k material to achieve a particular transistor threshold voltage modulation for a given transistor conductivity type.

In alternative embodiments where pull-down transistor125and pass-gate transistor are N-channel devices, a P-dipole dopant metal M2preferentially incorporated into gate insulator291is at least one of Al (e.g., forming a dipole as AlOx, AlSiOx, or AlHfOx, etc.), Ga (e.g., forming a dipole species Ga0x, GaSiOx, or GaHfOx, etc.), Mo (e.g., forming a dipole species MoOx, MoSiOx, or MoHfOx, etc.), or Co (e.g., forming a dipole species CoOx, CoSiOx, or CoHfOx, etc.), or Ni (e.g., forming a dipole species NiOx, NiSiOx, or NiHfOX, etc.), or Nb (e.g., forming a dipole species NbOx, NbSiOx, or NbHfOx, etc.).

Regardless of the polarity of the specific dipole dopant, dipole dopant-based Vtcontrast provided between pull-down and pass-gate transistors may be implemented by introducing the Vtshifting dipole dopant metal M2from a solid state dipole dopant source material deposited during the practice of any IC fabrication process suitable for fabricating stacked GAA transistor structures.FIG.5is a flow diagram of methods500for fabricating an SRAM bit-cell with gate insulators of contrasting dipole dopant content, in accordance with some embodiments.

Methods begin at input505where a workpiece is received. In some embodiments, the workpiece received at input505is a wafer suitable for IC die fabrication. The workpiece may, for example, further include part of a workpiece substrate (e.g., a large format semiconductor wafer) that is to become an IC chip. At block510, a nanoribbon material stack is formed. The nanoribbon material stack may advantageously include a plurality of bi-layers comprising a sacrificial material and ribbon material. In some embodiments, the sacrificial material layers include more germanium than the ribbon material. For example, where the ribbon material is predominantly silicon, the sacrificial layers are Sii,Gex.

At block520, the ribbon material stack is patterned into one or more fins including a portion where a pull-down transistor will be fabricated and a portion where a pass-gate transistor will be fabricated. Any patterning process, such as an extreme ultraviolet (EUV) lithography process, may be practiced at block520to define a fin mask. Any subtractive etch may be practiced at block520to delineate features (e.g., fins) into the nanoribbon material stack. In some embodiments, a plasma etch process may be utilized to define such features.

At block530, channel portions of the features patterned at block520are protected with a channel mask. In some embodiments, the channel mask formed over exposed portions of the fin includes a sacrificial gate stack. At block540, source and drain regions are formed adjacent to the channel mask, for example by epitaxially growing impurity-doped semiconductor with a low pressure CVD (LPCVD) process. In exemplary embodiments where pull-down and pass-gate transistors a N-channel devices, source and drain regions grown at block540may include predominantly silicon, and one or more n-dopants such as phosphorus, arsenic, or antimony.

At block550, the channel mask and sacrificial material is removed to expose channel regions of the nanoribbons. At block560gate insulators with different amounts of Vt-shifting dipole dopant is formed around pull-down and pass-gate transistors. Methods600(FIG.6) then continue at block570where a gate electrode is formed around the gate insulators of each of pull-down and pass-gate transistors. Methods500then end at output580where any known fabrication techniques may be practiced to complete an IC including the SRAM bit-cell. For example, any number of levels of interconnect metallization may be fabricated according to any back-end-of-line (BEOL) processes known to be suitable for integrated circuits (ICs).

FIG.6is a flow diagram illustrating methods600for dipole dopant Vtmodulation, in accordance with some embodiments where the pass-gate and pull-down transistors are both NMOS and the dipole dopant is an N-dipole dopant. Methods600may be practiced, for example, at block560of methods500.FIG.7A-7Dillustrate cross-sectional views of an NMOS pull-down transistor structure and an NMOS pass-gate transistor structure evolving as methods600are practiced, in accordance with some embodiments. The cross-sectional views in7A-7D are along the same B and C planes introduced inFIG.4B and4C.

Referring first toFIG.6, methods600begin at block610where a gate insulator including an N-dipole dopant source material is formed around channel regions of one or more nanoribbons. Block610may include any of thermal oxidation, plasma-assisted oxidation, UV-assisted oxidation, chemical vapor deposition, or thermal atomic layer deposition (ALD) processes. Each of these techniques may form a chemical oxide selectively upon surfaces of the channel regions of nanoribbons. As one example, a thermal ALD process may include a co-reactant phase where an oxygen precursor, such as ozone is introduced. The thermal ALD cycle may also include a deposition phase during which a silicon precursor (e.g., an amino silane) is introduced. One or more such cycles may be performed to form one or more layers of chemical oxide (e.g., SiO2) upon channel regions of the nanoribbons. Depending on the deposition technique, various trace levels of impurities, such as hydrogen and/or carbon, may be unintentionally introduced into the chemical oxide, but the material may be otherwise substantially pure (e.g., SiO2).

Any of the high-k dielectric materials described above may be further formed at block610, for example with a CVD or ALD process. An ALD half-reaction precursor may, for example, include a first metal. A co-reactant half-reaction precursor may, for example, include oxygen. Any number of ALD cycles may be performed at block610to reach a desired high-k dielectric material thickness (e.g., 1.0-2.0 nm).

An N-dipole dopant source material is further formed at block610. The N-dipole dopant source material may be deposited by another CVD or cyclic ALD process. In an ALD process, a deposition half-reaction precursor may comprise a second metal (i.e., the dipole metal M2), while the co-reactant half-reaction precursor includes oxygen. Any number of such ALD cycles may be performed at block610to reach a desired thickness of dipole dopant source material. In exemplary embodiments, one to five such cycles are performed, for example to deposit 0.5-2.0 nm of dipole dopant source material.

In the example illustrated inFIG.7A, both pull-down transistor125and pass-gate transistor130include an N-dipole dopant source material711on gate insulator292. As described above, gate insulator292may include both chemical oxide and high-k dielectric material. N-dipole dopant source material711may vary, but may be any of those listed above, for example. In some exemplary embodiments, N-dipole dopant source material711comprises La (e.g., LaOx).

Returning toFIG.6, methods600continue at block615where the pull-down transistor channel region is masked with any suitable mask material to protect the dipole dopant source material from an etchant (e.g., wet chemical) that removes the N-dipole dopant source material from the pass-gate transistor at block620.FIG.7Bfurther illustrates an embodiment where a protective mask material720, such as diamond-like carbon (DLC), protects pull-down transistor125. As further shown, in an absence of mask material720, N-dipole dopant source material711is removed from pass-gate transistor130, exposing gate insulator292.

Returning toFIG.6, methods600continue at block625where N-dipole dopants are thermally driven from the dipole dopant source material toward the channel region of pull-down transistor125and/or pass-gate transistor130. The mask material may be removed before or after the drive/activation. In exemplary embodiments, diffusion of the Vtshifting N-dipole dopant is driven by elevated temperature processing. One or more thermal processes may be performed at block625to diffuse the N-dipole toward the channel regions until it comes to rest, for example, within a chemical oxide layer between the high-k dielectric material layer and the channel material. Block625may, for example, include a heat cycle during which the transistor stack structures reach a temperature of over 500° C. (e.g., 700° C., 750° C., 800° C., or 850° C.) for a predetermined time in the presence of any suitable ambient, such as, but not limited to, nitrogen (N2), or forming gas (N2:H2)

Following the thermal drive/activation, methods600continue at block630where the N-dipole dopant source material is removed from the pull-down transistor channel region (and anywhere else it was retained). Any suitable etch process (e.g., wet chemical) may be practiced at block630. In some embodiments, the etch process performed at block620is repeated at block630. In the example further illustrated inFIG.7C, gate insulator291is formed where gate insulator292has been doped with the N-dipole dopant. In the absence of any dipole dopant source material around pass-gate transistor130, gate insulator292remains substantially unchanged.

Returning toFIG.6, methods600complete at block635where a gate electrode including a material (e.g., metal) with a suitable workfunction, such as one of those described above, is deposited around each of gate insulators291,292. Any deposition process suitable for the material may be practiced at block635. In some embodiments, a gate electrode workfunction metal is deposited with an ALD process. In the example shown inFIG.7D, the gate stacks of both pull-down transistor125and pass-gate transistor130are substantially complete with gate electrode285surrounding each of gate insulator291and gate insulator292.

FIG.8is a flow diagram illustrating methods800for dipole dopant Vt modulation, in accordance with some alternative embodiments where both pull-down and pass-gate transistors receive some N-dipole dopant-based threshold voltage tuning.FIG.9A-9Dillustrate cross-sectional views of a pull-down transistor structure and a pass-gate transistor structure evolving as methods800are practiced, in accordance with some embodiments. The cross-sectional views in9A-9D are along the same B and C planes illustrated inFIG.7A-7D.

Referring first toFIG.8, methods800again begin with block610where a gate insulator including N-dipole dopant source material is formed around at least the NMOS pull-down and pass-gate transistors of an SRAM bit-cell. Other transistors in the SRAM bit-cell (e.g., pull-up transistors), or external to the bit-cell (e.g., logic core) may also have the same gate insulator at this point in the manufacturing process.

Methods800continue at block810where supplemental N-dipole dopant source material is formed around channel regions around at least the pull-down and pass-gate transistors of an SRAM bit-cell. Any of the dipole dopant source materials described above may be deposited as a supplement at block810. The supplemental N-dipole dopant source material may be another layer of the same source material deposited at block610, for example increasing the source material layer thickness. Alternatively, a second N-dipole dopant source material of a different composition that that deposited at block610may be deposited at block810.FIG.9Aillustrates an example where both pull-down transistor125and pass-gate transistor130initially have substantially the same gate insulator material stack including an insulator material910, N-dipole dopant source material711on insulator material910, and an N-dipole dopant source material911on N-dipole dopant source material711. In some exemplary embodiments where N-dipole dopant source material711is a La source material (e.g., LaOx), N-dipole dopant source material911is the same La source material (LaOx).

Returning toFIG.8, methods800continue at block615where the pull-down transistor channel region is again masked, for example substantially as described above. At block820the supplemental dipole dopant source material is removed from the unmasked pass-gate channel region, for example with any wet-chemical etch suitable for the supplemental dipole dopant source material. In some embodiments, an etch is performed at block615for a predetermined time to remove only a thickness of dipole dopant source material associated with the supplemental dipole dopant source material. In the example illustrated inFIG.9B, N-dipole dopant source material911has been removed, leaving N-dipole dopant source material711over the channel regions of pass-gate transistor130.

Returning toFIG.8, methods800continue at block625where the N-dipole dopant is thermally diffused and/or activated, for example substantially as described above. With a greater amount of N-dipole dopant source material being present around channel regions of the pull-down transistor, more of the N-dipole dopant diffuses toward the channel regions of the pull-down transistor than for the pass-transistor. Following the dipole dopant drive/activation, the source material(s) may be removed at block630, for example substantially as described above. In the example illustrated inFIG.9C, the thermal process has doped insulator material910of pass-gate transistor130with a lesser amount of N-dipole dopant to form gate insulator292, and doped insulator material910of pull-down transistor125with a greater amount of N-dipole dopant to form gate insulator291.

Methods800(FIG.8) are then completed at block635where the gate electrode is formed, for example substantially as described above, to arrive at the gate stack substantially as further illustrated inFIG.9D.

Notably, methods600and800may be modified as described above in the context ofFIG.2-5to implement dipole-based Vt contrast in pull-down and pass-gate transistors with P-dipole dopants. For such embodiments, the treatments of the pull-down and pass-gate transistors described in the context of methods600and800are reversed to account for the complementary effect of on threshold voltage of the P-dipole dopant.

SRAM bit-cells with pull-down and pass-gate transistors having a dipole dopant-based threshold voltage contrast may be integrated into a wide variety of ICs and computing systems that include such ICs.FIG.10illustrates a mobile computing platform1005and a data server computing platform1006employing a packaged IC including an SRAM with dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein. The server platform1006may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged IC1050including an SRAM with including an SRAM with dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein.

The mobile computing platform1005may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform1005may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system1010, and a battery1015. At least one IC of chip-level or package-level integrated system1010includes packaged IC with an SRAM that has dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein.

In the example shown in the expanded view, integrated system1010includes a microprocessor1001that includes an SRAM with dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein. Microprocessor1001may be further coupled to a host substrate1060. One or more of a power management integrated circuit (PMIC)1030or an RF (wireless) integrated circuit (RFIC)1025including a wideband RF (wireless) transmitter and/or receiver (TX/RX) may be further coupled to host substrate1060.

Functionally, PMIC1030may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery1015and with an output providing a current supply to other functional modules (e.g., microprocessor1001). As further illustrated, in the exemplary embodiment, RFIC1025has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 4G, 5G, and beyond.

FIG.11is a functional block diagram of an electronic computing device1100, in accordance with an embodiment of the present invention. Computing device1100may be found inside platform1005or server platform1006, for example. Device1100further includes a host substrate1102hosting a number of components, such as, but not limited to, a processor1104(e.g., an applications processor with an arithmetic logic unit). Processor1104may be physically and/or electrically coupled to host substrate1102. In some examples, processor1104includes an SRAM with dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein. In general, the term “processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips1106may also be physically and/or electrically coupled to the host substrate1102. In further implementations, communication chips1106may be part of processor1104. Depending on its applications, computing device1100may include other components that may or may not be physically and electrically coupled to host substrate1102. These other components include, but are not limited to, volatile memory (e.g., DRAM1132), non-volatile memory (e.g., ROM1135), flash memory (e.g., NAND or NOR), magnetic memory (MRAM1130), a graphics processor1122, a digital signal processor, a crypto processor, a chipset1112, an antenna1125, touchscreen display1115, touchscreen controller1165, battery1116, audio codec, video codec, power amplifier1121, global positioning system (GPS) device1140, compass1145, accelerometer, gyroscope, speaker1120, camera1141, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In some exemplary embodiments, at least one of the functional blocks noted above include SRAM with dipole dopant-based modulated threshold voltages, for example substantially as described elsewhere herein.

Communication chips1106may enable wireless communications for the transfer of data to and from the computing device1100. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips1106may implement any of many wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device1100may include a plurality of communication chips1106. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

It will be recognized that the invention is not limited to the exemplary embodiments described in detail but can be practiced with modification and alteration without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features as further provided below.

In first examples, a static random-access memory (SRAM) bit-cell structure comprises a first transistor comprising a first gate electrode around a channel region of a first stack of nanoribbons, and a first gate insulator between the first gate electrode and the channel region of the first stack of nanoribbons. The first gate insulator comprises a high-k gate material layer comprising oxygen and a first metal species. The bit-cell structure comprises a second transistor of a same conductivity type as the first transistor. The second transistor comprises a second gate electrode around a channel region of a second stack of nanoribbons, a second gate insulator between the second gate electrode and the channel region of the second stack of nanoribbons. The second gate insulator comprises the high-k material layer. An amount of a dipole dopant comprising a second metal species differs between the first or second gate insulators.

In second examples, for any of the first examples the first and second transistors are NMOS device structures, the dipole dopant is an N-dipole dopant, and the second gate insulator comprises more of the dipole dopant than the first gate insulator.

In third examples, for any of the first through second examples the first metal species is a first of Hf, Al, Zr, or Y,the second metal species is Mg, Ca, Sr, La, Sc, Ba, Gd, Er, Yb, Lu, Ga, Mo, Co, Ni, Nb, or a second of Hf, Al, Zr, or Y.

In fourth examples, for any of the first through second examples within the second gate insulator, a ratio of a concentration of the second metal species to a concentration of the first metal species is between 0.1 and 0.2. Within the second gate insulator, a ratio of a concentration of the second metal species to a concentration of the first metal species is between 0 and 0.1.

In fifth examples for any of the first through second examples the first gate insulator also comprises the dipole dopant but at a lower concentration than that of the second gate insulator.

In sixth examples, for any of the first through second examples the dipole dopant is absent from the first gate insulator.

In seventh examples, for any of the first examples the first and second transistors are NMOS device structures the dipole dopant is a P-dipole dopant, and the second gate insulator comprises less of the dipole dopant than the first gate insulator.

In eighth examples, for any of the first through seventh examples the first transistor is a pass-gate transistor, the second transistor is a pull-down transistor and the SRAM bit-cell structure further comprises a pair of pull-up transistors. Each of the pull-up transistors further comprises a third stack of nanoribbons, a third gate electrode around a channel region of the third stack of nanoribbons, and a third gate insulator between the third gate electrode and the channel region of the third stack of nanoribbons, wherein the third gate insulator comprises the high-k gate material layer and lacks the dipole dopant.

In ninth examples, for any of the first through eighth examples the first stack of nanoribbons and the second stack of nanoribbons have substantially the same composition, the first gate electrode and the second gate electrode have substantially the same composition, the first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, different than the first threshold voltage.

In tenth examples for any of the ninth examples a magnitude of the first threshold voltage is higher than the magnitude of the second threshold voltage.

In eleventh examples, a device comprises a microprocessor comprising an arithmetic logic unit, a cache memory comprising an SRAM array, and a power supply coupled to power the microprocessor. The SRAM array comprises a plurality of bit-cells and each bit cell comprises a first NMOS transistor, comprising a first stack of nanoribbons, a first gate electrode around a channel region of the first stack of nanoribbons, and a first gate insulator between the first gate electrode and the channel region of the first stack of nanoribbons. The first gate insulator comprises a high-k gate material layer comprising oxygen and a first metal species. Each bit-cell comprises a second NMOS transistor comprising a second stack of nanoribbons, a second gate electrode around a channel region of the second stack of nanoribbons, and a second gate insulator between the second gate electrode and the channel region of the second stack of nanoribbons. The second gate insulator comprises the high-k material layer and an N-dipole dopant comprising a second metal species.

In twelfth examples, for any of the eleventh examples the device further comprises a battery coupled to the power supply.

In thirteenth examples, a method of fabricating a static random-access memory (SRAM) structure comprises forming a transistor material stack including a plurality of bilayers comprising sacrificial material and channel material, patterning the transistor material stack into a fin. The method comprises forming a first gate insulator comprising a first metal species and a first amount of second metal species around a pull-down transistor region of the channel material, and forming a second gate insulator comprising the first metal species and a second amount of the second metal species, different than the first amount, around a pass-gate transistor region of the channel material. The method comprises forming a gate electrode material around the first gate insulator, and forming the gate electrode material around the second gate insulator.

In fourteenth examples, for any of the thirteenth examples forming the first gate insulator and the second gate insulator comprises forming a gate insulator material including an N-dipole dopant source material comprising the second metal species around the pull-down and pass-gate transistor regions, removing more of the N-dipole dopant source material from the pass-gate transistor region than from the pull-down transistor region, and thermally annealing the structure.

In fifteenth examples, for any of the fourteenth examples the method comprises removing substantially all of the N-dipole dopant source material from the pull-down transistor region, and depositing the gate electrode material.

In sixteenth examples for any of the fourteenth examples removing more of the N-dipole dopant source material from the pass-gate transistor region than from the pull-down transistor region comprises masking the pull-down transistor region, and removing substantially all of the N-dipole dopant source material from the pass-gate transistor region.

In seventeenth examples, for any of the fourteenth examples forming a gate insulator material including the N-dipole dopant source material comprising the second metal species around the pull-down and pass-gate transistor regions further comprises depositing a first layer of the dipole N-dopant source material around both the pull-down and pass-gate transistor regions, and depositing a second layer of the N-dipole dopant source material around only the pull-down transistor region.

In eighteenth examples, for any of the seventeenth examples removing more of the N-dipole dopant source material from the pass-gate transistor region than from the pull-down transistor region further comprises masking the pull-down transistor region, and removing the second layer of the N-dipole dopant source material from the pass-gate transistor region without removing all of the first layer of the N-dipole dopant source material.

In nineteenth examples, for any of the thirteenth through eighteenth examples the first metal species is a first of Hf, Al, Zr, or Y, and wherein the second metal species is Mg, Ca, Sr, La, Sc, Ba, Gd, Er, Yb, Lu, Ga, Mo, Co, Ni, Nb, or a second of Hf, Al, Zr, or Y.

In twentieth examples, for any of the thirteenth through nineteenth examples the second amount of the second metal species is less than the first amount and the pass-gate transistor has a first threshold voltage, the pull-down transistor has a second threshold voltage, and a magnitude of the first threshold voltage is higher than the magnitude of the second threshold voltage.