A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

FIELD

The present invention generally relates to semiconductors structures, and more particularly to semiconductor structures including an integrated passive device (IPD) such as a ferrite bead inductor and methods for forming the same.

BACKGROUND

The present major trend in semiconductor fabrication is integration of 2.5D and 3D IC chip or die packages having vertically stacked chips and direct electrical inter-chip connections in lieu of other interconnect techniques such as wire bonds and chip edge interconnects. The dies in such IC chip packages may include fine (small) pitch vertical through substrate vias (TSVs) which may be used to form a direct electrical connection to an adjoining stacked die. TSVs offer higher density interconnects and shorter signal paths creating the possibility of forming die packages having smaller form factors and thin die stacks. The TSVs in top dies may be terminated on the back side with very fine pitch microbump arrays for final interconnection to and mounting on a semiconductor substrate. The compact die stacks in 2.5D/3D IC chip packages provide a small form factor consistent with the goal of producing smaller semiconductor devices.

In 2.5D/3D IC chip packages, interposers may be used to make electrical connections between adjoining dies or between die packages and another semiconductor substrate which may include various electrically conductive interconnects such as redistribution layer (RDL) structures in some embodiments that may be used to increase or decrease the pitch spacing of the electrical contacts to aid with eventual final mounting of the chip package on another substrate, which may be a package printed circuit board (PCB), packaging substrate, high-density interconnect, or other.

Some semiconductor structures incorporating 2.5D/3D IC technology may include various passive devices. One such passive device is a board-level SMD (surface mount device) ferrite bead inductor. Ferrite bead inductors (“ferrite beads”) generally include input and output terminals, and conductive metallic leads or traces combined with an associated magnetic core material such as ferrite. Ferrite beads function as passive low-pass noise suppression filters or shields that attenuate high frequency EMI/RFI (electromagnetic interference or radio frequency interference) noise from internal or external sources that may interfere with the proper performance of circuits and devices formed in a semiconductor package. Board level SMD ferrite beads are discrete devices which are fabricated separately and then mounted on a semiconductor package substrate or PCB (printed circuit board). Accordingly, SMD ferrite beads have a relatively large form factor and consume valuable real estate when mounted on the PCB. SMD ferrite beads are not compatible for integration with the silicon-based CMOS (complementary metal-oxide semiconductor) chip fabrication processes.

An integrated passive device (IPD) chip-level or “on-chip” ferrite bead inductor with small form factor is desired that can be integrated with the silicon-based chip semiconductor fabrication process.

All drawings are schematic and are not drawn to scale.

DETAILED DESCRIPTION

FIG. 1shows a first embodiment of a semiconductor structure100such as a chip including an in situ chip level or “on-chip” ferrite bead inductor105(also referred to as “ferrite bead” herein for brevity) according to the present disclosure. The semiconductor structure100with ferrite bead105may be formed by BEOL (back-end-of-line) semiconductor fabrication processes as are well known to those in the art. Accordingly, such a ferrite bead inductor105may be considered an integrated passive device (IPD) or thin film CMOS IPD being integrated within the chip as opposed to a board level SMD.

Semiconductor structure100includes, in sequence, a substrate110, a first dielectric layer120formed thereon, a first lower ferrite layer130formed thereon, a first metal layer140formed thereon, a second dielectric layer150formed thereon, a second metal layer160formed thereon, a second upper ferrite layer170formed thereon, and a third top dielectric layer180formed thereon. In some embodiments, substrate110may be formed of silicon or a high-resistivity (Hi-R) silicon and contain active discrete CMOS devices. In other embodiments, substrate110may be a silicon or H-R silicon interposer without active devices. Semiconductor structure100above substrate110with alternating metal and dielectric layers may be an interconnect metal layer of a chip in some embodiments containing interconnect circuits consisting of trenches, vias, plugs, etc. Accordingly, in some embodiments the ferrite bead inductor105may be integrated with and formed in a portion of the metal layer.

Substrate110may have any suitable thickness. In one example, without limitation, substrate110may have a representative thickness of about 700 microns. Other suitable thicknesses, however, may be used. In one embodiment, an H-R silicon may be used with a relative permittivity (∈r) of about 11.9.

Dielectric layers120,150, and180may be any suitable type of dielectric material used in semiconductor fabrication processes. In one exemplary embodiment, without limitation, the dielectric material used may be silicon dioxide (SiO2) having a relative permittivity (∈r) of about 3.9. Any kind of dielectric material with other relative permittivities may be used as appropriate. In some exemplary embodiments, dielectric layers120and180may have a thickness of about 1 micron in some embodiments. Dielectric layer150disposed between metal layers140and160may have a thickness of about 3 microns in some embodiments, or may be the same as dielectric layers120and180. Accordingly, any thicknesses for dielectric layers120,150, and180may be used as appropriate.

Dielectric layers120,150, and180may be deposited by any suitable method, such as without limitation CVD (chemical vapor deposition) or PVD (physical vapor deposition).

In some embodiments, ferrite layers130and170may be a solid or continuous and unpatterned. Ferrite layers130,170may be substantially flat or planar as shown inFIG. 1, and in one embodiment may have a horizontal width and depth dimensioned to extend at least as wide and deep as the conductive leads formed in their corresponding respective adjacent metal layer140or160. In some embodiments, ferrite layers130,170may be patterned by photolithography and etching to have a pattern that is identical or nearly identical to the pattern of the conductive leads formed in adjacent metal layers140or160, respectively. In one embodiment, ferrite layers130,170do not extend vertically through or beyond their respective adjacent metal layers140or160which are sandwiched between the ferrite layers as shown inFIG. 1.

Ferrite layers130,170may have a representative thickness, without limitation, of about 3 microns in some embodiments. Ferrite layers130,170may have a permeability of about 50. The ferrite layers130,170may be disposed above/below and adjacent to metal layers140and160as shown. The ferrite layers may be deposited or formed by any suitable method, such as without limitation CVD or PVD in some embodiments.

Ferrite layers130and170may be made of any suitable type of ferrite. In some embodiments, the ferrite used may have a permeability ranging from about 1-1000

With continuing reference toFIG. 1, metal layers140and160may be deposited and formed in direct contact with the ferrite layers130,170. Metal layers140and160may be deposited by any suitable method, including sputtering, plating, and others.

In some embodiment, metal layer160may be patterned and include solid conductor areas forming conductive leads142and open areas144between the leads, as shown for example inFIGS. 2 and 5. Leads142may have any suitable configuration including one or more straight segments which may be conjoined and arranged at an angle to an adjoining segment as shown to form a continuous conductive lead having numerous configurations.

In one embodiment, individual adjoining leads142may be arranged at a 90 degree angle to each other and form a rectilinear spiral pattern having multiple angular “turns” to form a metal coil220as shown inFIGS. 2 and 5. In some embodiments, an open central area may be formed at the center of the coiled or spiral pattern as best shown inFIGS. 2 and 5. Any suitable number of turns may be provided depending on the particular design parameters and intended application for the inductor. The spiral leads142may be symmetrically and concentrically arranged around the open center of the spiral metal pattern. Leads142may be rectangular in cross-sectional shape in some embodiments as best shown inFIG. 5.

Patterned leads142may be formed by any suitable BEOL (back end of line) process used in the art, including damascene and dual damascene processes involving patterned photolithography, etching, and film deposition.

Metal layers140and160may be made of any suitable conductive material amenable for formation by BEOL process. In some embodiments, without limitation, metal layers140and160may be made of copper or aluminum. Metal layers140and160may have representative thicknesses of about 6 microns in some embodiments and conductivities of about 5.8×107.

FIG. 2is a top view of the ferrite bead inductor105shown in cross-section inFIG. 1. The upper metal layer160that defines leads142forms a coiled or spiral pattern which defines an input terminal141for connection to the next wiring level and circuit formed above in semiconductor structure100or a lateral circuit at the same level. The lower metal layer140forms a straight lead168to bring the output terminal166back outside from inside the spiral for connection to the next wiring level and circuit formed below in semiconductor structure100or a lateral circuit at the same level. Lead168may be electrically connected to lead142at a different level in the semiconductor structure by a conductive via146which may be made of any suitable conductive material including copper, aluminum, tungsten, and other conductive metals or alloys.

The inventors fabricated and tested the chip-level IPD ferrite bead inductor105shown inFIGS. 1 and 2for comparison of performance with board-level surface mounted device (SMD) ferrite beads. The graph inFIG. 3shows the performance of ferrite bead inductor105according to the present disclosure. At a frequency of 100 MHz, the impedance was found to be approximately 56 ohm as shown in the graph which compares favorably with the performance of a SMD ferrite bead.

Accordingly, the IPD ferrite bead inductor105according to the present disclosure advantageously can provide the same performance as a board-level SMD inductor, but with a much smaller form factor (i.e. physical size). One typical SMD inductor, for example, may have a form factor of 0.054 mm3(0.6 mm×0.3 mm×0.3 mm). By contrast, the IPD ferrite bead inductor105shown inFIGS. 1 and 2has a smaller form factor of about 0.018 mm3(0.98 mm×0.88 mm×0.021 mm). The IPD ferrite bead inductor105therefore consumes less available space in the semiconductor structure allowing for construction of smaller device packages consistent with current shrinking 2.5/3D chip packaging technologies.

FIGS. 4 and 5show a semiconductor structure200having an alternative embodiment of ferrite bead inductor205comprising more than one interconnected conductive coils220disposed at different spaced apart levels within the structure. The structure of ferrite bead inductor205is similar to ferrite bead inductor105shown inFIGS. 1 and 3, but instead is a three-layer inductor205(i.e. three coiled metal layers defining coils220) semiconductor structure as opposed to a single layer inductor105(single coiled metal layer). An additional dielectric layer162and metal layer164are formed between the ferrite layers130,170with the ferrite layers remaining outboard (i.e. above and below) metal layers140,160, and162. The ferrite and dielectric layers are omitted inFIG. 5for clarity in showing the three coils220of ferrite bead inductor205.

With continuing reference toFIGS. 4 and 5, the metal layers140,160,164each defining a conductive coil220are interconnected by vias146as shown. An input terminal210is formed in the spiral of the uppermost coiled metal layer164for connection to the next wiring level and circuit formed above in semiconductor structure100or a lateral circuit at the same level. The lowermost coiled metal layer140forms an output terminal214which is disposed at the center of the spiral for connection to the next wiring level and circuit formed below. A via146may be provided that extends below ferrite layer130and enters dielectric layer120in semiconductor structure200. In some embodiments, this via146may be connected to a straight lead216disposed in dielectric layer120having a terminal end212for connection to a lateral or other circuit in the semiconductor structure.

It will be appreciated that any number of inductor layers may be constructed employing the same approach as in the semiconductor structures described herein and shown inFIGS. 1-2and4-5. If an even number of coiled metal layers are used, both the input and output terminals will be positioned on the outside of the coils facilitating connection to other circuits in the semiconductor structure without additional vias or straight conductive leads.

An exemplary method for forming an in situ chip-level ferrite bead inductor105will now be briefly described with reference toFIGS. 1,2, and6.FIG. 6is a flow chart showing the basic process steps. The process may be a BEOL process in some embodiments.

Referring specifically toFIG. 6, the method begins by providing a substrate110and depositing dielectric layer120thereon. Ferrite layer130is next deposited on dielectric layer120(step310). In some embodiments, ferrite layers130and170may be solid flat layers. In other possible embodiments, ferrite layers130,170may be photoresist patterned and etched to have a pattern that may match or complement the configuration of the patterned metal layers described herein.

The first metal layer140is then deposited on ferrite layer130. A patterned photoresist is next formed on metal layer140to produce the intended metal configuration desired. In this embodiment, a straight lead168will be produced (seeFIG. 2). The patterned photoresist step is a photolithography process used in the art including sub-steps that may comprise depositing a photoresist material, positioning a reticle mask above the photoresist having the inverse of the desired final metal pattern formed therein, photo exposure involving exposing the unprotected portions of the photoresist to a light such as UV in some embodiments shined through the mask, and developing and removing portions of the photoresist exposed to the light leaving portions of the photoresist material in place to protect the intended final metal pattern from being etched.

With the patterned photoresist remaining on metal layer140, this metal layer is next etched using a suitable wet etching or dry gas plasma etching having an etch selectively selected for preferentially removing the exposed portions of metal layer140material not protected by the photoresist. It is well within the abilities of one skilled in the art to select a suitable etching chemistry and process. After metal layer140is etched, the photoresist is completely removed by any suitable wet or dry ashing process. The protected metal remaining in metal layer140will be configured as straight lead168.

With continuing reference toFIGS. 1,2, and6, the method for forming ferrite bead inductor105continues by depositing dielectric layer150on etched metal layer140. The second metal layer160is next deposited on dielectric layer150. A patterned photoresist is next formed on metal layer160in a similar manner described above to produce the intended metal configuration desired. In this embodiment, a coiled or spiral metal lead142will be produced (seeFIG. 2). Metal layer160is next etched in a similar manner described above. After metal layer160is etched, the photoresist is completely removed by any suitable wet or dry ashing process. The protected metal remaining in metal layer160will be configured as the coiled lead142.

The method continues by next depositing ferrite layer170on metal layer160, and then finally depositing the dielectric layer180thereon.

During the foregoing method, it will be appreciated that metal vias146may be formed at appropriate times during the basis process by any means commonly used in the art. This may involve etching or milling the via hole(s) in dielectric layer150(seeFIG. 1) after that layer is deposited, and then filling the hole with a suitable metal conductor material by any appropriate process used in the art including plating. In some embodiments, the via hole(s) may be filled at the same time metal layer160is deposited if the same material is used for the via146and layer160. This process may be used to produce any number or configuration of vias146as will be understood by those in the art.

The ferrite bead inductor205ofFIGS. 4 and 5may be produced by a similar method to that described above.

In one embodiment according to the present disclosure, a semiconductor structure with chip-level ferrite bead inductor includes a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer and an upper ferrite layer spaced vertically apart from the lower ferrite layer, a first metal layer formed above the lower ferrite layer, a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration, and at least one second dielectric layer disposed between the first and second metal layers.

In another embodiment, a semiconductor chip with in situ ferrite bead inductor includes a substrate, a first dielectric layer formed on the substrate, a planar lower ferrite layer formed on the first dielectric layer, a first metal layer formed on the first ferrite layer, a second dielectric layer formed on the first metal layer, a second metal layer formed on the second dielectric layer, the second metal layer being patterned to define a first conductive coil comprising multiple turns, a via electrically connecting the first conductive coil to the first conductive lead, and a planar upper ferrite layer disposed above the first conductive coil.

In one embodiment, a method for forming an in situ chip-level ferrite bead inductor includes: depositing a first dielectric layer on a substrate; depositing a lower ferrite layer on the first dielectric layer; depositing a first metal layer on the lower ferrite layer; patterning the first metal layer to form a first conductive lead having a configuration; depositing a second dielectric layer on the patterned first metal layer; depositing a second metal layer on the second dielectric layer; patterning the second metal layer to form a conductive coil having multiple turns; and forming an upper ferrite layer above the patterned second metal layer. In some embodiments, the upper ferrite layer is formed directly onto the patterned second metal layer. The method may further include: depositing a third dielectric layer on the patterned second metal layer; depositing a third metal layer on the third dielectric layer; and patterning the third metal layer to form a conductive coil having multiple turns.

While the foregoing description and drawings represent exemplary embodiments of the present disclosure, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope and range of equivalents of the accompanying claims. In particular, it will be clear to those skilled in the art that embodiments according to the present disclosure may be include other forms, structures, arrangements, proportions, sizes, and with other elements, materials, and components, without departing from the spirit or essential characteristics thereof. One skilled in the art will further appreciate that the embodiments may be used with many modifications of structure, arrangement, proportions, sizes, materials, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. In addition, numerous variations in the exemplary methods and processes described herein may be made without departing from the spirit of the present disclosure. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being defined by the appended claims and equivalents thereof, and not limited to the foregoing description or embodiments.