SEMICONDUCTOR PACKAGE WITH SUBSTRATE RECESS AND METHODS FOR FORMING THE SAME

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

BACKGROUND

As semiconductor packages have become more complex, ensuring mechanical integrity of the package has become more difficult. Package defects, such as delamination, cracking and other defects, may negatively affect package yields and device performance.

DETAILED DESCRIPTION

Various embodiments disclosed herein may be directed to semiconductor devices, and in particular to semiconductor packages and methods of fabricating semiconductor packages having a package substrate that may include one or more recesses in a surface of the package substrate.

Typically, in a semiconductor package a number of semiconductor integrated circuit (IC) dies (i.e., “chips”) may be mounted onto a common substrate, which may also be referred to as a “package substrate.” In some packages, such as in a fan out wafer level package (FOWLP) and/or fan-out panel level package (FOPLP), a plurality of semiconductor IC dies may be mounted to an interposer, such as an organic interposer or a semiconductor (e.g., silicon) interposer, that may include interconnect structures extending therethrough. The resulting package structure, including the interposer and the semiconductor IC dies mounted thereon, may then be mounted onto a surface of a package substrate using solder connections. An underfill material portion may be provided in the space between the interposer and the package substrate to encapsulate the solder connections and improve the structural coupling between the interposer and the package substrate.

In order to improve electrical performance of the package, some package designs may include additional structures located between the interfacing surfaces of the interposer and the package substrate. For example, one or more semiconductor devices, which may be composed of silicon, may be located over portions of the surface of the interposer that is mounted to the package substrate. In some embodiments, the semiconductor devices may function as a capacitor and may help to improve the signal integrity of the active IC devices of the package. However, the presence of these structures between the interposer and the package substrate may negatively affect the integrity of the structural coupling between the interposer and the package substrate.

In particular, in instances in which a semiconductor device located over the surface of the interposer contacts the package substrate, or in instances when the gap between the semiconductor device and the package substrate is too small to permit adequate flow of the underfill material between the semiconductor device and the package substrate, void areas may be present in the underfill material portion between the interposer and the package substrate. These void areas may lead to package defects, such as delamination of the interposer from the package substrate, cracking of the underfill material portion, and/or moisture-induced “popcorn” defects, which may negatively effect package yields and performance.

Various embodiments disclosed herein include semiconductor packages and methods of fabricating semiconductor packages utilizing a package substrate having one or more recesses formed in a surface of the package substrate and at least one channel in a bottom surface of each of the recesses. Each of the recesses formed in the surface of the package substrate may be configured to accommodate a semiconductor device located over a surface of an interposer that may be bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate. The minimum gap distance may encourage sufficient underfill material to flow between the semiconductor device and the package substrate and within the at least one channel formed in the bottom surface of each of the recesses. This may improve the integrity of the structural coupling between the interposer and the package substrate, and may significantly reduce the likelihood of package defects, such as delamination, cracking, and/or popcorn defects, thereby improving package yields and performance.

FIG.1is a vertical cross-section view of an exemplary intermediate structure during a process of forming a semiconductor package according to various embodiments of the present disclosure. Referring toFIG.1, the exemplary intermediate structure includes a first carrier substrate101and an interposer103formed and mounted over a front side surface of the first carrier substrate101. The first carrier substrate101may provide mechanical support to the interposer103, and may be formed of a suitable substrate material, such as glass material, a ceramic material (e.g., a sapphire substrate), a semiconductor material (e.g., a silicon substrate), or the like. Other suitable materials for the first carrier substrate101are within the contemplated scope of disclosure. In some embodiments, the first carrier substrate101may be formed of an optically transparent material.

In some embodiments, a first release layer117may be located over the front side surface of the first carrier substrate101, and the interposer103may be located over the first release layer117. The first release layer117may include an adhesive material that may adhere the interposer103to the front side surface of the first carrier substrate101. In some embodiments, the first release layer117may include an adhesive material that may be subsequently treated to cause the adhesive material of the first release layer117lose its adhesive properties, such that the first carrier substrate101may be separated from the interposer103. In some embodiments, the adhesive material of the first release layer117may lose its adhesive properties when subjected to treatment using an energy source, such as a thermal, optical (e.g., UV, laser, etc.) and/or sonic (e.g., ultrasonic) energy source. In one non-limiting example, the first release layer117may include a light-to-heat conversion (LTHC) material that may selectively absorb optical radiation in certain wavelength range(s), such as ultraviolet radiation, causing the LTHC material to heat up and thereby lose adhesion. In other embodiments in which the first carrier substrate101is formed of an optically transparent material, the application of an optical energy source may cause the first release layer117to lose its adhesive property. Alternatively, the first release layer117may include an adhesive material, such as an acrylic pressure-sensitive adhesive material, that may decompose when subjected to an elevated temperature. Other suitable materials for the first release layer117are within the contemplated scope of disclosure.

Referring again toFIG.1, the interposer103may include a first side surface102and a second side surface104opposite the first surface103. The second side surface104of the interposer103may face the front side surface of the first carrier substrate101. A plurality of conductive interconnect structures108(e.g., metal lines and vias) may extend within the interposer103between the first side surface102and the second side surface104of the interposer103. The conductive interconnect structures108may be formed in and surrounded by an insulating matrix that may be formed of a dielectric material118. The conductive interconnect structures108of the interposer103may be configured to route electrical signals between semiconductor integrated circuit (IC) dies and a package substrate in a semiconductor package to be subsequently formed. Thus, the conductive interconnect structures108of the interposer103may also be referred to as “redistribution structures.”

In some embodiments, the interposer103may be an organic interposer. The organic interposer103may be formed on the first carrier substrate101. In one non-limiting example, the interposer103may be formed by sequentially depositing layers of a dielectric material118, such as a dielectric polymer material, over the front side surface of the first carrier substrate101(and over the first release layer117, if present). Each of the layers of dielectric material118may be lithographically patterned and etched to form open regions (e.g., trenches and/or via openings), and a metallization process may then be used to fill the open regions and form conductive interconnect structures108(e.g., metal lines and vias) within each successive layer of dielectric material118. In this manner, the interposer103may be built layer-by-layer over the front side surface of the first carrier substrate101.

In some embodiments, each of the layers of dielectric material118of the interposer103may include a suitable dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplated scope of disclosure. The layers of dielectric material118of the interposer103may be formed using a suitable deposition process, such as a spin coating and drying process. Other suitable deposition processes are within the contemplated scope of disclosure.

The conductive interconnect structures108of the interposer103may be formed of a suitable conductive material, such as Cu, Ni, W, Cu, Co, Mo, Ru, etc., including alloys and combinations of the same. In some embodiments, the conductive interconnect structures108may include a metallic barrier layer, such as a layer of Ti, TiN, TaN, or WN, contacting the dielectric material118, and a metallic fill material, which may include an elemental metal (e.g., Cu, Ni, etc.) or an alloy or a combination thereof. Other suitable materials for the conductive interconnect structures108of the interposer103are within the contemplated scope of disclosure. The conductive interconnect structures108of the interposer103may be formed using any suitable deposition process. For example, suitable deposition processes may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof.

Referring again toFIG.1, an instance of an interposer103located over the front side surface of the first carrier substrate101may be referred to as a unit area (UA) of the first carrier substate101. A single unit area (UA) is illustrated inFIG.1, although it will be understood that the first carrier substrate101may include a plurality of unit areas (UAs), where each unit area (UA) may include a separate instance of an interposer103over the front side surface of the first carrier substrate101. For example, the first carrier substrate101may include a periodic two-dimensional array (such as a rectangular array) of unit areas (UAs), where each unit area (UA) of the array may include a separate instance of an interposer103over the front side surface of the carrier substrate101. In some embodiments, each interposer103within a unit area (UA) of the array may have an identical structure. The plurality of interposers103over the first carrier substrate101may be continuous with one another, such that a continuous layer of dielectric material118may extend over the front side surface of the first carrier substrate101, with separate instances of conductive interconnect structures108formed within the continuous layer of dielectric material118in each unit area (UA).

FIG.2is a vertical cross-section view of the exemplary intermediate structure showing interposer bonding structures106located over the first side surface102of the interposer103according to various embodiments of the present disclosure. Referring toFIG.2, the interposer bonding structures106may include a plurality of metallic bumps. The interposer bonding structures106may be formed by depositing one or more layers of a metal material and patterning the one or more layers of metal material to form the plurality of interposer bonding structures106over the first side surface102of the interposer103. Each bonding structure106may be electrically coupled to an underlying conductive interconnect structure108of the interposer103. In some embodiments, the interposer bonding structures106may form at least one periodic two-dimensional array (such as a rectangular array) of interposer bonding structures106within the unit area (UA). In some embodiments, a plurality of interposer bonding structures106may be formed over the first side surface102of the interposer103in each unit area (UA) of the first carrier substrate101.

In various embodiments, the interposer bonding structures106may be configured for subsequent microbump bonding (i.e., C2 bonding) to corresponding bonding structures formed on semiconductor integrated circuit (IC) dies. In some embodiments, the interposer bonding structures106may include a plurality of metal pillars. The metal pillars may include copper or a copper-containing alloy. In some embodiments, the bonding structures may include a plurality of metal stacks, such as a plurality of Cu—Ni—Cu stacks. In some embodiments, the interposer bonding structures106may include a solder material, such as tin or a tin-containing alloy, on an upper surface of the interposer bonding structures106. Other suitable materials and/or configurations for the interposer bonding structures106are within the contemplated scope of disclosure.

FIG.3is a vertical cross-section view of the exemplary intermediate structure showing a plurality of semiconductor integrated circuit (IC) dies105mounted over the first side surface102of the interposer103according to various embodiments of the present disclosure. In some embodiments, the plurality of IC semiconductor dies105may include at least one system-on-chip (SoC) die. An SoC die may include, for example, an application processor die, a central processing unit die, and/or a graphic processing unit die. In some embodiments, the plurality of IC semiconductor dies105may include at least one memory die. The at least one memory die may include a high bandwidth memory (HBM) die. In some embodiments, a HBM die may include a vertical stack of interconnected memory dies. In some embodiments, the plurality of semiconductor IC dies105may be homogeneous, meaning that all of the semiconductor IC dies105may be of the same type (e.g., all SoC dies, all HBM dies, etc.). Alternatively, the plurality of semiconductor IC dies105may be heterogeneous, meaning that the plurality of semiconductor IC dies105may include different types of semiconductor IC dies105(e.g., at least one SoC die and at least one HBM die). In some embodiments, the plurality of semiconductor IC dies105may include one or more SoC dies and a plurality of HBM dies. The one or more SoC dies may be located in a central portion of the unit area (UA) and the plurality of HBM dies may laterally surround the one or more SoC dies. Further, although two semiconductor IC dies105are shown mounted over the first side surface102of the interposer103in the exemplary embodiment ofFIG.3, it will be understood that in various embodiments more than two semiconductor IC dies105may be mounted over the first side surface102of the interposer103.

Referring again toFIG.3, each of the semiconductor IC dies105may include a plurality of semiconductor die bonding structures119located over a lower surface of the semiconductor IC die105. The semiconductor die bonding structures119on the semiconductor IC dies105may have a similar or identical configuration as the interposer bonding structures106over the first side surface102of the interposer103described above with reference toFIG.2. For example, the semiconductor die bonding structures119on the lower surfaces of the semiconductor IC dies105may include a plurality of metallic bumps, such as metal pillars and/or metal stacks. In some embodiments, the semiconductor die bonding structures119on the semiconductor IC dies105may include a solder material, such as tin or a tin-containing alloy, on the lower surface of the semiconductor die bonding structures119. The semiconductor die bonding structures119on the lower surfaces of each semiconductor IC die105may be configured for microbump bonding (i.e., C2 bonding) to corresponding interposer bonding structures106on the first side surface102of the interposer103.

The semiconductor IC dies105may be mounted over the first side surface102of the interposer103by placing each of the semiconductor IC dies105over the first side surface102of the interposer103(e.g., using a pick-and-place apparatus). The semiconductor IC dies105may be aligned over the first side surface102of the interposer103such that the semiconductor die bonding structures119on the lower surfaces of the semiconductor IC dies105contact corresponding interposer bonding structures106over the first side surface102of the interposer103. A reflow process may be used to bond the semiconductor die bonding structures119on the lower surfaces of the semiconductor IC dies105to the corresponding interposer bonding structures106over the first side surface102of the interposer103, thereby providing a mechanical and electrical connection between each of the semiconductor IC dies105and the interposer103. In various embodiments, a plurality of semiconductor IC dies105may mounted over the first side surface102of the interposer103within each unit area (UA) of the first carrier substrate101.

FIG.4is a vertical cross-section view of the exemplary intermediate structure showing a first underfill material portion107located between the lower surfaces of the semiconductor IC dies105and the first side surface102of the interposer103, and a molding portion109around the outer periphery of the plurality of semiconductor IC dies105according to various embodiments of the present disclosure. Referring toFIG.4, the first underfill material portion107may be applied into the spaces between the first side surface102of the interposer103and the plurality of semiconductor IC dies105mounted to the interposer103. The first underfill material portion107may laterally surround and contact each of the interposer bonding structures106and semiconductor die bonding structures119that bond the respective semiconductor IC dies105to the interposer103. The first underfill material portion107may also be located between adjacent semiconductor IC dies105of the plurality of semiconductor IC dies105mounted to the interposer103.

The first underfill material portion107may include any underfill material known in the art. For example, the first underfill material portion107may be composed of an epoxy-based material, which may include a composite of resin and filler materials. Other suitable materials for the first underfill material portion107are within the contemplated scope of disclosure. Any known underfill material application method may be used to apply the first underfill material portion107.

Referring again toFIG.4, a molding portion109may laterally surround the plurality of semiconductor IC dies105mounted to the interposer103. The molding portion109may contact lateral side surfaces of at least some of the semiconductor IC dies105and may also contact the first underfill material portion107. In various embodiments, the molding portion109may include an epoxy material. For example, the molding portion109may include an epoxy mold compound (EMC) that may include epoxy resin, a hardener (i.e., a curing agent), silica or other filler material(s), and optionally additional additives. The EMC may be applied around the periphery of the semiconductor IC dies105in liquid or solid form, and may be hardened (i.e., cured) to form a molding portion109having sufficient stiffness and mechanical strength surrounding the plurality of semiconductor IC dies105. Portions of the molding portion109that extend above a horizontal plane including the top surfaces of the semiconductor IC dies105may be removed using a planarization process, such as a chemical mechanical planarization (CMP) process.

In various embodiments, each unit area (UA) of the first carrier substrate101may include a first underfill material portion107located between the first side surface102of the interposer103and the undersides of the plurality of semiconductor IC dies105mounted to the interposer103, and a molding portion109around the outer periphery of the plurality of semiconductor IC dies105. In some embodiments, the molding portion109may form a continuous matrix extending between the unit areas (UAs) of the first carrier substrate101and laterally surrounding and embedding the respective sets of semiconductor IC dies105within each of the unit areas (UAs) of the first carrier substrate101.

FIG.5is a vertical cross-section view of the exemplary intermediate structure showing a second release layer121located over the upper surfaces of the plurality of semiconductor dies105, the exposed upper surface of the first underfill material portion107and the exposed upper surface of the molding portion109, and a second carrier substrate111over the second release layer121according to various embodiments of the present disclosure. Referring toFIG.5, the second release layer121may include an adhesive material that may adhere the second carrier substrate111to the upper surfaces of the plurality of semiconductor dies105, the first underfill material portion107and the molding portion109. As with the first release layer117described above, the second release layer121may also be configured to lose its adhesive properties when subjected to a treatment using an energy source, such as a thermal, optical (e.g., UV, laser, etc.) and/or sonic (e.g., ultrasonic) energy source. In some embodiments, the first release layer117and the second release layer121may be composed of the same material(s). Alternatively, the first release layer117and the second release layer121may be composed of different material(s).

Referring again toFIG.5, the second carrier substrate111may be formed of a suitable substrate material, such as the materials described above with reference to the first carrier substrate101shown inFIG.1. In some embodiments, the second carrier substrate111may be composed of the same material(s) as the first carrier substrate101. Alternatively, the second carrier substrate111and the first carrier substrate101may be composed of different material(s). In various embodiments, the second carrier substrate111may extend over each of the unit areas (UAs) of the first carrier substrate101such that each unit area (UA) of the first carrier substrate101may correspond to an equivalent unit area (UA) of the second carrier substrate111.

FIG.6is a vertical cross-section view of the exemplary intermediate structure showing the first carrier substrate101removed according to various embodiments of the present disclosure. Referring toFIG.6, the first carrier substrate101may be removed using any suitable method known in the art. In embodiments in which the first carrier substrate101is adhered to the interposer103by a first release layer117, the first release layer117may be subjected to a treatment that causes the first release layer117to lose its adhesive properties. This may enable the first carrier substrate101to be separated from the exemplary intermediate structure. For example, the first release layer117may include a light-to-heat conversion (LTHC) material that may be irradiated by optical radiation in a specified wavelength range, such as ultraviolet radiation, causing the LTHC material to heat up and thereby lose adhesion. The first release layer117may optionally be irradiated through the first carrier substrate101in embodiments in which the first carrier substrate101is composed of an optically-transparent material. Alternatively, the first release layer117may include a thermally-decomposing adhesive material. The exemplary intermediate structure be subjected to a thermal anneal process at a debonding temperature sufficient to cause the first release layer117to decompose and thereby enable the first carrier substrate101to be detached from the exemplary intermediate structure. In embodiments in which a thermal anneal process is used to remove the first carrier substate101, the debonding temperature used to thermally decompose the first release layer117may not be sufficient cause the second release layer121to lose its adhesive properties.

Referring again toFIG.6, the exemplary intermediate structure may be inverted (i.e., flipped over), either prior to or following the removal of the first carrier substrate101, such that the interposer103may be located over and supported by the second carrier substrate111.

FIG.7Ais a vertical cross-section view of the exemplary intermediate structure showing a plurality of bonding pads115and semiconductor devices112located over the second side surface104of the interposer103according to various embodiments of the present disclosure.FIG.7Bis a top view of the exemplary intermediate structure ofFIG.7A. The vertical cross-section view of the exemplary intermediate structure ofFIG.7Ais taken along line A-A′ inFIG.7B.

Referring toFIGS.7A and7B, the bonding pads115may be formed by depositing one or more layers of a metal material and patterning the one or more layers of metal material to form the plurality of bonding pads115over the second side surface104of the interposer103. Each bonding pad115may be electrically coupled to an underlying conductive interconnect structure108of the interposer103. The bonding pads115may have a rectangular or square horizontal cross-sectional shape as shown inFIGS.7A and7B. Other suitable horizontal cross-sectional shapes of the bonding pads115, such as polygonal, circular, elliptical, and/or irregular shapes, are within the contemplated scope of disclosure. The bonding pads115may be formed of a suitable metallic material, such as copper, aluminum, nickel, titanium, etc., including combinations and alloys thereof. Other suitable metallic materials for the bonding pads115are within the contemplated scope of disclosure. In some embodiments, the plurality of bonding pads115may form a periodic two-dimensional array (such as a rectangular array) of bonding pads115within the unit area (UA). The array of bonding pads115may be non-contiguous over the unit area (UA). In particular, the array of bonding pads115may include one or more gaps corresponding to the location(s) of one or more semiconductor devices112located over the second side surface104of the interposer103. In various embodiments, the array of bonding pads115within the unit area (UA) may extend over a greater areal extent within a horizontal plane parallel to the first horizontal direction hd1and the second horizontal direction hd2than the corresponding areal extent of the array(s) of interposer bonding structures106used to mount the plurality of semiconductor IC dies105to the interposer103. In such embodiments, the bonding pads115may also be referred to as “fan-out” bonding pads115. In some embodiments, the bonding pads115may be configured for subsequent mounting of a unit area (UA) of the exemplary intermediate structure to a package substrate, such via a plurality of C4 (i.e., controlled collapse) solder connections.

Referring again toFIGS.7A and7B, at least one semiconductor device112may be located over the second side surface104of the interposer103. Each of the semiconductor devices112may be mounted to the second side surface104of the interposer by a plurality of semiconductor device bonding structures113. In some embodiments, the semiconductor device bonding structures113may have a similar or identical configuration as the interposer bonding structures106located over the first side surface102of the interposer103described above with reference toFIG.2. For example, the semiconductor device bonding structures113may include a plurality of metallic bumps, such as metal pillars and/or metal stacks, formed over the second side surface104of the interposer103. The semiconductor devices112may be mounted to respective sets of semiconductor device bonding structures113on the second side surface104of the interposer103via microbump (e.g., C2) bonding connections. Each of the semiconductor device bonding structures113may be electrically coupled to an underlying conductive interconnect structure108of the interposer103. Accordingly, each of the semiconductor devices112may be electrically coupled to one or more semiconductor IC dies105via the interposer103.

In one non-limiting example, the semiconductor devices112may be mounted over the second side surface104of the interposer103by placing each of the semiconductor devices112over the first side surface102of the interposer103such that the lower surfaces of the respective semiconductor devices112contact semiconductor device bonding structures113located over the second side surface104of the interposer103. A reflow process may be used to bond the semiconductor devices112to respective semiconductor device bonding structures113over the second side surface104of the interposer103, thereby providing a mechanical and electrical connection between each of the semiconductor devices112and the interposer103.

The at least one semiconductor device112may be composed of a suitable semiconductor material. In some embodiments, the at least one semiconductor device112may include silicon. Other suitable semiconductor materials are within the contemplated scope of disclosure. In some embodiments, each of the semiconductor devices112may have electronic circuit elements, such as conductive interconnect structures, located on and/or within the semiconductor device112. Additional electronic circuit elements, such as transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices, may also be located on and/or within the semiconductor devices112in various embodiments. In some embodiments, the at least one semiconductor device112may function as a capacitor and may help to improve signal integrity of the one or more semiconductor IC dies105to which the respective semiconductor device112is electrically coupled. The at least one semiconductor device112mounted on the semiconductor device bonding structures113located over the second side surface104of the interposer103together with the interposer103and semiconductor dies105(along with other elements as discussed with reference toFIG.10below) may form the package structure150.

In the embodiment shown inFIGS.7A and7B, each of the semiconductor devices112may have a rectangular horizontal cross-sectional shape. Other suitable horizontal cross-sectional shapes of the semiconductor devices112, such as polygonal, circular, elliptical, and/or irregular shapes, are within the contemplated scope of disclosure. Each of the semiconductor devices112may have a first maximum length dimension, LS1, along a first horizontal direction hd1and a second maximum length dimension, LS2, along a second horizontal direction hd2that is orthogonal to the first horizontal direction hd1. Each of the semiconductor devices112may have an identical size and shape, or may have different (i.e., non-uniform) sizes and/or shapes. For example, in the embodiment shown inFIGS.7A and7B, the semiconductor devices112have non-uniform first and second maximum length dimensions, LS1and LS2. In some embodiments, the first and second maximum length dimensions, LS1and LS2, of the semiconductor devices112may be between about 300 μm and about 5 mm, although greater and lesser maximum length dimensions, LS1and LS2, are within the contemplated scope of disclosure. In various embodiments, a height dimension, H, between the upper surfaces of the semiconductor devices112and the second side surface104of the interposer103may be greater than 10 μm, such as between 50 μm and 150 μm, including about 100 μm.

In various embodiments, a plurality of bonding pads115may be formed over the second side surface104of the interposer103and at least one semiconductor device112may be mounted over the second side surface104of the interposer103within each unit area (UA) of the second carrier substrate111.

FIG.8Ais a vertical cross-section view of a package substrate201according to various embodiments of the present disclosure.FIG.8Bis a top view of the package substrate201ofFIG.8A. Referring toFIGS.8A and8B, the package substrate201may include any suitable substrate material(s), such as polymer, glass, epoxy resin, ceramic and/or semiconductor substrate materials. The package substrate201may include a first side surface202(which, for convenience, may also be referred to as a “front” side surface202of the package substrate201) and a second side surface203(which, for convenience, may also be referred to as a “rear” side surface203of the package substrate) that is opposite the first side surface202.

The package substrate201may be configured such that a plurality of semiconductor IC dies105may be mounted over the front side surface202of the package substrate201to provide a semiconductor package. In various embodiments, the plurality of semiconductor IC dies105may be mounted to an interposer103, such as an interposer103as described above with reference toFIGS.1-7B, and the interposer103having the plurality of semiconductor IC dies105mounted thereon may be mounted over the front side surface202of the package substrate201to provide the semiconductor package. The interposer103may be mounted over a bonding region206of the package substrate201.

In various embodiments, the package substrate201may include redistribution structures204(e.g., metal lines, vias, bonding regions, etc.) extending within the package substrate201. In some embodiments, the rear side surface203of the package substrate201may be configured to be mounted to a supporting substrate, such as a printed circuit board (PCB). Electrical connections between the supporting substrate (e.g., a PCB) and the semiconductor package may be made via the redistribution structures204within the package substrate201.

In some embodiments, the package substrate201may include a multi-layer structure including a substrate core213, at least one redistribution layer214, and at least one outer coating layer215. For example, the package substrate201may include a pair of redistribution layers214located above and below the substrate core213, and a pair of outer coating layers215located above and below the respective redistribution layers214. The outer coating layers215may form the front side surface202and rear side surface203of the package substrate201. The substrate core213may be a plate-like member composed of a suitable material such as an epoxy resin, glass, and/or ceramic material. The substrate core213may include a plurality of conductive via structures216extending through the substrate core213. The redistribution layers214may include conductive interconnect structures217, such as metal lines, vias and bonding regions, embedded in a dielectric material matrix218. In some embodiments, the dielectric material matrix218may include multiple layers of a dielectric material, such as a photosensitive epoxy material. Each layer of dielectric material may be lithographically patterned to form open regions (e.g., trenches and via openings) within the respective layers of dielectric material. A metallization process may be used to fill the open regions with a suitable conductive material, such as copper or a copper-alloy, within each layer of dielectric material to form the conductive interconnect structures217embedded within the dielectric material matrix218. The outer coating layers215of the package substrate201may include a layer of solder resist material formed over the respective redistribution layers214. Each of the layers of solder resist material may provide a protective coating for the package substrate201and the underlying redistribution structures204within the package substrate101. The solder resist material may also inhibit solder material from adhering to the front side surface202and rear side surface203of the package substrate201during a subsequent solder reflow process. An outer coating layer215formed of solder resist material may also be referred to as a “solder mask.” Other suitable configurations for the package substrate201are within the contemplated scope of disclosure.

In various embodiments, the package substrate201may have a total thickness, T, between the front side surface202and the rear side surface203of the package substrate201that is between about 600 μm and about 1,500 μm, although greater and lesser thicknesses for the package substrate201are within the contemplated scope of disclosure.

FIG.9Ais a vertical cross-section view of the package substrate201showing a plurality of recesses205formed in the first side surface202of the package substrate201according to various embodiments of the present disclosure.FIG.9Bis a top view of the package substrate ofFIG.9A. The vertical cross-section view of the package substrate201ofFIG.9Ais taken along line B-B′ inFIG.9B.

Referring toFIGS.9A and9B, at least one recess205may be formed in the first side surface202of the package substrate201. Each recess205may correspond to the location of a semiconductor device112over the second side surface104of an interposer103to be subsequently mounted over the first side surface202of the package substrate201. In various embodiments, each recess205may have a vertical depth, D, from the first side surface202of the package substrate201of at least 5 μm, which may be sufficient to accommodate the thickness of the semiconductor device112as well as the height of the semiconductor bonding structures113that bond the semiconductor device112to the second side surface104of the interposer103when the interposer103is mounted over the first side surface of the package substrate201as described in further detail below. In some embodiments, the depth, D, of each recess205may be greater than or equal to 10 μm and less than or equal to 100 μm, although greater and lesser depth dimensions, D, of the recesses205are within the contemplated scope of disclosure. In some embodiments, a ratio of the depth dimension D of each recess205to the total thickness T of the package substrate201may be between about and 0.16, such as between 0.015 and 0.1. This may provide sufficient clearance to enable an adequate flow of underfill material between the semiconductor device112and the bottom surface of the recess205without compromising the performance or mechanical integrity of the package substrate201.

In various embodiments, the total area of each recess205within a horizontal plane parallel to the first horizontal direction hd1and the second horizontal direction hd2may be greater than the total area of the corresponding semiconductor device112within a horizontal plane parallel to the first horizontal direction hd1and the second horizontal direction hd2. In some embodiments, the total area of the recess205may be greater than the total area of the corresponding semiconductor device112by at least about 2%. In various embodiments, the maximum length dimensions, LR1and LR2, of each recess along the first horizontal direction hd1and the second horizontal direction hd2, respectively, may be greater than the maximum length dimensions, LS1and LS2, of the corresponding semiconductor device112along the first horizontal direction hd1and the second horizontal direction hd2, respectively. In some embodiments, the maximum length dimensions, LR1and LR2, of the recess205may be greater than the than the maximum length dimensions, LS1and LS2, of the corresponding semiconductor device112by at least about 50 μm. This may enable sufficient underfill material to flow around the sides of the semiconductor devices112. In some embodiments, at least one length dimension of the recess205may be 350 μm or more.

Each of the recesses205may have a suitable horizontal cross-sectional shape, such as a polygonal, circular, elliptical, and/or irregular shape.FIGS.9A and9Billustrate a pair of recesses205having a rectangular horizontal cross-sectional shape.FIG.9Cis a top view of a package substrate201having recesses205with an elliptical horizontal cross-section shape according to another embodiment of the present disclosure.FIG.9Dis a top view of a package substrate201having recesses205with an irregular horizontal cross-section shape according to yet another embodiment of the present disclosure. Other suitable shapes for the recesses205are within the contemplated scope of disclosure. In some embodiments, the horizontal cross-sectional shape of each recess205may be the same as the horizontal cross-sectional shape of the corresponding semiconductor device112. Alternatively, a recess205may have a different horizontal cross-sectional shape than the shape of the corresponding semiconductor device112, so long as the recess205is large enough to encompass the corresponding semiconductor device112. In the embodiment shown inFIGS.9A and9B, the recesses205are shown having vertically-extending sidewalls and sharp, squared corners, although it will be understood that various embodiments may include recesses205having tapered or curved sidewalls and/or angled or rounded corners.

The one or more recesses205may be formed in the front side surface202of the package substrate201using any suitable technique. In some embodiments, the one or more recesses205may be formed using a lithographic process. For example, a layer of photoresist may be applied over the front side surface202of the package substrate201and exposed to radiation through an optical mask to transfer the pattern of the one or more recesses205to the photoresist layer. The photoresist layer may then be developed to form a patterned mask having openings through the patterned mask corresponding to the locations of the one or more recesses205to be subsequently formed. One or more etching processes may be performed through the patterned mask to selectively remove material from the package substrate201to a desired depth, D, thereby forming the one or more recesses205on the front side surface202of the package substrate201. The patterned mask may then be removed using a suitable process, such as via ashing or dissolution using a solvent.

In other embodiments, the one or more recesses205may be formed using a machining technique, such as using computer numerical control (CNC) machining of the front side surface202of the package substrate201. Other known machining techniques, such as drilling or physical etching techniques, may be utilized. In some embodiments, the one or more recesses205may be formed using an ablation technique, such as via laser ablation of select portions of the front side surface202of the package

In some embodiments, the one or more recesses205may be formed in the front side surface202of the package substrate201during the process of manufacturing the package substrate201. Alternatively, the one or more recesses205may be formed after the package substrate201is manufactured using post-processing techniques. In embodiments in which the package substrate201includes a multilayer structure including a redistribution layer214and an outer coating layer215(e.g., a solder mask) surrounding a substrate core213, the one or more recesses205may be formed through the outer coating layer215and may optionally extend partially or completely through the redistribution layer214.FIG.10Ais a vertical cross-section view of the package substrate201showing a plurality of recesses205formed in the first side surface202of the package substrate201extending partially into the redistribution layer214of the package substrate201according to an embodiment of the present disclosure. The recesses205may be formed by depositing a whole layer of the outer coating layer215and then etch the outer coating layer215.

In some embodiments, the depth, D, of a recess205may extend to and/or into the substrate core213of the package substrate201.FIG.10Bis a vertical cross-section view of the package substrate201showing a plurality of recesses205formed in the first side surface202of the package substrate201extending partially into the substrate core213of the package substrate201according to an embodiment of the present disclosure.

In some embodiments, one or more recesses205may be formed by depositing an outer coating layer215over a surface of a package substrate201, and performing an etching process to remove select portions of the outer coating layer215to form one or more recesses205in the first side surface202of the package substrate201. The outer coating layer215may be a solder resist (i.e., solder mask) material as described above. Other suitable materials for the outer coating layer215are within the contemplated scope of disclosure. In various embodiments, the etching process may be performed through a lithographically-pattered mask that may expose the outer coating layer215in portions corresponding to the one or more recesses205and may protect the remaining portions of the outer coating layer215from being etched.

In embodiments in which underlying redistribution structures204of the package substrate201are exposed on the bottom and/or side surfaces of a recess205, such as shown inFIGS.10A and10B, the redistribution structures may optionally electrically connect to a semiconductor device112over the second side surface104of an interposer103to be subsequently mounted over the first side surface202of the package substrate201.

FIG.11Ais a vertical cross-section view of the package substrate201showing a channel260formed in each recess205in the first side surface202of the package substrate201according to various embodiments of the present disclosure.FIG.11Bis a top view of the package substrate ofFIG.11A. The vertical cross-section view of the package substrate201ofFIG.11Ais taken along line B-B′ inFIG.11B. Referring toFIGS.11A and11B, a channel260may be formed within the bottom surface of each of the recesses205in the first side surface202of the package substrate201. Each channel260may have an elongated shape including a width dimension, WC, and a length dimension, LCthat is greater than the width dimension, WC. The width dimension WCof each channel260may be less than the corresponding width of the recess205in which the channel260is located. The length dimension, LC, of each channel may be less than, equal to or greater than the corresponding length of the recess205in which the channel is located. In the embodiment shown inFIG.11B, for example, the length dimension LCof the channel260on the left-hand side ofFIG.11Bis less than the corresponding length dimension (i.e., LR2) of the recess205in which the channel260is located, whereas the length dimension LCof the channel260on the right-hand side ofFIG.11Bis greater than the corresponding length dimension (i.e., LR2) of the recess205in which the channel260is located. In some embodiments, the widths WCof each channel260may be between about 5 μm and about 500 μm, although greater and lesser width dimensions are within the contemplated scope of disclosure. Each channel260may have a uniform width WCalong its length, or may have a width dimension that varies along the length of the channel260. In some embodiments, the lengths LCof each channel260may be between about 10 μm and about 5 mm, although greater and lesser length dimensions are within the contemplated scope of disclosure. Each channel260may follow a straight-line path along its length LCas shown inFIG.11B. Alternatively, one or more channels260may follow a curved or angled (e.g., zig-zag) path along its length LC.

Referring toFIG.11A, each of the channels260may have a depth dimension, Dc, with respect to the bottom surface of the recess205within which the channel260is located. In various embodiments, a maximum depth dimension Dc of each channel may be between about 3 μm and about30μm, although greater and lesser maximum depth dimensions are within the contemplated scope of disclosure.

The channels260may be formed using any of the techniques described above for forming the at least one recess205. For example, the channels260may be formed via an etching process through a lithographically-patterned mask, via a machining technique, such as CNC machining, milling, drilling, physical etching, etc., or using an ablation technique, such as laser ablation. In some embodiments, the channels260may be formed in a separate step following the formation of the one or more recesses205. Alternatively, the channels260may be formed simultaneous with the formation of the one or more recesses205. In other embodiments, the channels260may be formed in an initial step, and the one or more recesses205may be formed around the channels260in subsequent processing steps.

FIGS.11C-11Hare a tops views of a package substrate201illustrating various configurations of recesses205and channels260as described above with reference toFIGS.11A and11B.FIG.11Cis a top view of a package substrate201having recesses205with an elliptical cross-section shape and a channel260located within each recess205according to an embodiment of the present disclosure. In the recess205on the left-hand side, the channel260extends along the second horizontal direction hd2, and in the recess on the right-hand side, the channel260extends along the first horizontal direction hd1.

FIG.11Dis a top view of a package substrate201having recesses205with an irregular horizontal cross-section shape and a channel260located within each recess205according to yet another embodiment of the present disclosure. In this embodiment, each of the channels260extends at an oblique angle with respect to the first horizontal direction hd1and the second horizontal direction hd2.

FIG.11Eis a top view of a package substrate201having recesses205with multiple channels260located within each recess205according to yet another embodiment of the present disclosure. Although the embodiment shown inFIG.11Eincludes three channels260located within each recess205, it will be understood that the recesses205may include a greater or lesser number of channels260. Further, each of the channels260located within a recess205may have a uniform size, shape and orientation, or may have non-uniform sizes, shaped and/or orientations.

FIG.11Fis a top view of a package substrate201having recesses205with multiple irregularly-shaped channels260located within each recess205according to yet another embodiment of the present disclosure.

FIG.11Gis a is a top view of a package substrate201having recesses205with at least one channel260extending outside of the boundaries of each recess205according to yet another embodiment of the present disclosure.FIG.11His a top view of a package substrate having recesses205and at least one channel260extending between multiple recesses205according to yet another embodiment of the present disclosure.

In various embodiments, the channels260formed in the recesses205on the first side surface202of the package substrate201may help to release air and balance the amount of underfill material within the recesses205when an interposer103including one or more semiconductor devices112over the second side surface104of an interposer103is subsequently mounted over the first side surface202of the package

FIG.12is a vertical cross-section view of an exemplary intermediate structure during a process of forming a semiconductor package showing a package structure150mounted over the front side surface202of a package substrate201according to various embodiments of the present disclosure. Referring toFIG.12, the second carrier substrate111may be removed from the exemplary intermediate package structure150shown inFIGS.7A and7B. The second carrier substrate111may be removed using any suitable method known in the art, such as any of the methods described above for removal of the first carrier substrate101. In embodiments in which the second carrier substrate111is adhered to the semiconductor IC dies105, the first underfill material portion107and the molding portion109using a second release layer121, the second release layer121may be subjected to a treatment that causes the second release layer121to lose its adhesive properties, such as a thermal anneal and/or an optical irradiation treatment process as described above with reference toFIG.6.

A dicing process may be used to separate each unit area (UA) of the exemplary intermediate structure to provide a plurality of discrete package structures150. Each package structure150may include an interposer103, a plurality of semiconductor IC dies105mounted over a first side surface102of the interposer103, a first underfill material portion107located in the gaps between the first side surface102of the interposer103and each of the semiconductor IC dies105, and a molding portion109laterally surrounding the plurality of semiconductor IC dies105. The interposer103may include a plurality of bonding pads115and at least one semiconductor device112located over a second side surface104of the interposer103.

Referring again toFIG.12, an etching process may be used to selectively remove portions of the outer coating layer215(e.g., solder mask) from the front side surface202of the package substrate201and expose underlying redistribution structures204(e.g., bonding pads). In some embodiments, the same etching process that is used to expose the redistribution structures204through the front side surface202of the package substrate201may also be used to form the at least one recess205and/or channel260in the package substrate201as described above with reference toFIGS.9A-11H. Alternatively, the at least one recess205and/or channel260may be formed in a separate process than the etching process(es) used to expose the redistribution structures204. For example, a machining process as discussed above may be used to form the at least one recess205and/or channel260within the at least one recess205. The pattern of the redistribution structures204exposed through the front side surface202of the package substrate201may correspond to the pattern of bonding pads115located over the second side surface104of the interposer103.

Referring again toFIG.12, the package structure150may be inverted relative to the orientation shown inFIGS.7A and7Band aligned over the package substrate201such that the second side surface104of the interposer103faces the front side surface202of the package substrate201. The package structure150may be disposed over the front side surface202of the package substrate201such that an array of solder material portions207are located between the redistribution structures204exposed through the front side surface202of the package substrate201and the bonding pads115over the second side surface104of the interposer103. Each of the semiconductor devices112mounted over the second side surface104of the interposer103may be located over a corresponding recess205in the front side surface202of the package substrate201. Each of the recesses205in the front side surface202may include at least one channel260in a bottom surface of the recess205.

A reflow process may be performed to reflow the solder material portions207, thereby inducing bonding between the interposer103of the package structure150and the package substrate201. Each of the solder material portions207may be bonded to a respective one of the bonding pads115over the second side surface104of the interposer103and to a respective one of redistribution structures204(e.g., bonding pads) of the package substrate201. In some embodiments, the solder material portions207may include C4 solder balls, and the package structure150may be bonded to the substrate package201through an array of C4 solder balls.

Referring again toFIG.12, following the bonding of the package structure150to the package substrate201, each of the semiconductor devices112may be located over a corresponding recess205in the front side surface202of the semiconductor package201. In various embodiments, each of the semiconductor devices112may be spaced away from and may not be in contact with the semiconductor package201. As shown inFIG.12, a gap209may be present between the bottom surface of each recess205in the package substrate201and the lower surface of the overlying semiconductor device112. In various embodiments, a height of the gap209between the bottom surface of the recess205and the lower surface of the overlying semiconductor device112may be at least 5 μm. In addition, the peripheral edges of the semiconductor devices112may be offset from the sidewalls of the adjacent recess205in the package substrate201such that no portion of the overlying semiconductor device112may extend to or beyond a vertical boundary defined by the peripheral sidewalls of the recess205. Each of the semiconductor devices112may overlie at least one channel260formed in a bottom surface of a recess205.

FIG.13is a vertical cross-section view of a semiconductor package100including a second underfill material portion211located between the front side surface202of the package substrate201and the second side surface104of the interposer103according to various embodiments of the present disclosure. Referring toFIG.13, the second underfill material portion211may be applied into the space between the front side surface202of the package substrate201and the second side surface104of the interposer103. The second underfill material portion211may laterally surround and contact each of the solder material portions207that bond the interposer103to the package substrate201and may also laterally surround and contact each of the semiconductor device bonding structures113that bond the respective semiconductor devices112to the second side surface104of the interposer103. The second underfill material portion211may flow into each of the recesses205in the front side surface202of the package substrate201and may also flow into the gaps209between the bottom surface of each recess205in the package substrate201and the lower surface of the overlying semiconductor device112. The second underfill material portion211may also flow into channels260in the bottom surface of each recess205. Accordingly, each semiconductor device112may be surrounded by and contact the second underfill material portion211over the upper, lower and lateral side surfaces of the respective semiconductor device112. In various embodiments, the portions of the second underfill material portion211located within the gaps209between the bottom surface of each recess205in the package substrate201and the lower surface of the overlying semiconductor device112may have a thickness of at least 5 μm.

In various embodiments, by providing recesses205in the front side surface202of the package substrate201corresponding to the locations of semiconductor devices112, a minimum gap distance may be maintained between the semiconductor devices112and the package substrate201. This may ensure that a sufficient amount of the second underfill material portion211may flow between each semiconductor device112and the front side surface202of the package substrate201. The one or more channels260in the bottom surfaces of each of the recesses205may help to release air and balance the amount of the second underfill material portion211within the recesses205. This may improve the integrity of the structural coupling between the interposer103and the package substrate201in the semiconductor package100, and may significantly reduce the likelihood of package defects, such as delamination, cracking, and/or popcorn defects, thereby improving package yields and performance.

The second underfill material portion211may include any underfill material known in the art. For example, the second underfill material portion211may be composed of an epoxy-based material, which may include a composite of resin and filler materials. Other suitable materials for the second underfill material portion211are within the contemplated scope of disclosure. Any known underfill material application method may be used to apply the second underfill material portion211.

In some embodiments, electrical connections to the semiconductor package100may be made by mounting the rear side surface203of the semiconductor package200onto a support substrate containing electrical interconnects, such as a printed circuit board (PCB).

FIG.14is a vertical cross-section view of a semiconductor package200including a semiconductor material interposer230according to an alternative embodiment of the present disclosure. Referring toFIG.14, the semiconductor package200according to the alternative embodiment may be similar to the semiconductor package100shown inFIG.13, and may include a package structure150having interposer230, a plurality of semiconductor IC dies105mounted over a first side surface102of the interposer230, a first underfill material portion107located in the gaps between the first side surface102of the interposer230and each of the semiconductor IC dies105, and a molding portion109laterally surrounding the plurality of semiconductor IC dies105. The interposer230may include a plurality of bonding pads115and at least one semiconductor device112located over a second side surface104of the interposer230. The package structure150may be bonded to the front side surface202of a package substrate201via a plurality of solder material portions207. The front side surface202of the package substrate201may include at least one recess205, where each recess205in the package substrate201corresponds to the location of a semiconductor device112mounted to the second side surface104of the interposer230. Each of the recesses205in the front side surface202may include at least one channel260in a bottom surface of the recess205.

A second underfill material portion211may be located in the space between the front side surface202of the package substrate201and the second side surface104of the interposer103, including within the gap(s)209between the bottom surface of each recess205and the lower surface of the overlying semiconductor device112, and within each of the channels260in a bottom surface of the respective recesses205.

The semiconductor package200ofFIG.12may differ from the semiconductor package100ofFIG.11in that the semiconductor package200ofFIG.12includes a semiconductor material interposer230as opposed to an organic interposer103. Referring toFIG.12, the semiconductor material interposer230may include a semiconductor device231, such as a silicon member, having a plurality of conductive through-vias233(e.g., through-silicon vias) extending therethrough. The conductive through-vias233may carry electrical signals between the plurality of semiconductor IC dies105mounted to the first side surface102of the interposer230and the package substrate201. In some embodiments, the semiconductor material interposer230may include at least one redistribution layer235including interconnect structures embedded in a dielectric material matrix located above and/or below the semiconductor device231.

FIG.15is a flowchart illustrating a method300of fabricating a semiconductor package100,200according to various embodiments of the present disclosure. Referring toFIGS.1-3and15, in step301of embodiment method300, at least one semiconductor integrated circuit (IC) die105may be mounted over a first side surface102of an interposer103,230. Referring toFIGS.7A,7B and15, in step303of embodiment method300, at least one semiconductor device112may be mounted over a second side surface104of the interposer103,230. Referring toFIGS.9A-10B and15, in step305of embodiment method300, at least one recess205may be formed in a front side surface202of a package substrate201. Referring toFIGS.11A-11H and15, in step307of embodiment method300, at least one channel260may be formed in a bottom surface of a recess205in the front side surface202of the package substrate201. Referring toFIGS.12and15, in step309of embodiment method300, the second side surface104of the interposer103,230may be bonded to the front side surface202of the package substrate201such that each semiconductor device112overlies a recess205in the front side surface202of the package substrate201. Referring toFIGS.13-15in step311of embodiment method300, an underfill material portion211may be provided between the front side surface202of the package substrate201and the second side surface104of the interposer103,230such that the underfill material portion211is located between a lower surface of each semiconductor device112and a bottom surface of a recess205in the front side surface202of the package substrate201underlying the respective semiconductor device112, and the underfill material portion211is located in the at least one channel260.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor package100,200may include an interposer103,230, at least one semiconductor integrated circuit (IC) die105mounted over a first side surface102of the interposer103,230, a semiconductor device112mounted over a second side surface104of the interposer103,230that is opposite the first side surface102of the interposer103,230, and a package substrate201including a recess205in a front side surface202of the package substrate201and at least one channel260in a bottom surface of the recess205, the second side surface104of the interposer103,230bonded to the front side surface202of the package substrate201such that the semiconductor device112overlies the recess205and the at least one channel260in the front side surface202of the package substrate201.

In an embodiment, the semiconductor package100,200includes an underfill material portion211between the front side surface202of the package substrate201and the second side surface104of the interposer103,230and within a gap209between a lower surface of the semiconductor device112and the bottom surface of the recess205in the front side surface202of the package substrate201and within the at least one channel260in the bottom surface of the recess205. In another embodiment, a height of the gap209between the lower surface of the semiconductor device112and the bottom surface of the recess205in the front side surface202of the package substrate201is at least 5 μm. In another embodiment, the semiconductor device112is spaced from the package substrate201. In another embodiment, a depth of the recess205from the front side surface202of the package substrate201is at least 5 μm. In another embodiment, the depth of the recess205from the front side surface202of the package substrate201is equal to or greater than 10 μm and less than or equal to 100 μm. In another embodiment, a ratio of the depth of the recess205to a total thickness of the package substrate201is between 0.0067 and 0.16. In another embodiment, the semiconductor device112has a length dimension along a first horizontal direction that is at least 300 μm, and the recess205has a length dimension along the first horizontal direction that is at least 50 μm greater than the length dimension of the semiconductor device112along the first horizontal direction. In another embodiment, a plurality of semiconductor IC dies105are bonded to the first side surface102of the interposer103,230via semiconductor die bonding structures119, a plurality of semiconductor devices112are bonded to the second side surface104of the interposer via second semiconductor device bonding structures113, each of the plurality of semiconductor devices112including at least one circuit element located on or in the semiconductor device112, and each of the plurality of semiconductor devices112is electrically coupled to at least one semiconductor IC die via interconnect structures extending through the interposer103,230, the package substrate201includes a plurality of recesses205in the front side surface202of the package substrate201, each recess205of the plurality of recesses205including at least one channel260in a bottom surface of the recess205, where each semiconductor device112of the plurality of semiconductor devices112bonded to the second side surface104of the interposer103,230overlies a respective recess205and at least one channel260on the front side surface202of the package substrate201, the package substrate comprises a plurality of solder material portions207located between respective bonding pads115of the second side surface104of the interposer103,230and interconnect structures204of the package substrate201, and the underfill material portion211laterally surrounds and contacts the solder material portions207and the semiconductor device bonding structures113and is located within each gap209between a lower surface of a semiconductor device112of the plurality of semiconductor devices112and a bottom surface of a recess205of the plurality of recesses205in the front side surface202of the package substrate201. In another embodiment, the plurality of semiconductor IC dies105includes at least one of a system-on-chip (SoC) die and a high bandwidth memory (HBM) die, and wherein at least one semiconductor device112of the plurality of semiconductor devices112functions as a capacitor to improve signal integrity of the one or more semiconductor IC dies105. In another embodiment, the at least one channel260has a width dimension WC that is less than a corresponding width dimension of the recess205in the front side surface202of the package substrate201, has a length dimension LC that is less than, equal to, or greater than a corresponding length dimension of the recess205in the front side surface202of the package substrate201, and has a maximum depth dimension DC with respect to the bottom surface of the recess205in the front side surface202of the package substrate201that is at least 3 μm. In another embodiment, the at least one channel260extends outside of the boundaries of the recess205in the front side surface202of the package substrate201.

An additional embodiment is drawn to a substrate201for a semiconductor package including a front side surface202, a rear side surface203, a plurality of redistribution structures204located between the front side surface202and the rear side surface203of the substrate201, at least one recess205in the front side surface202of the substrate201, the at least one recess205having a depth of at least 5 μm and a length dimension along at least one horizontal direction of at least 350 μm, and at least one channel260in a recess205in the front side surface202of the substrate201, wherein a long axis direction of the at least one channel260is parallel with the front side surface202of the substrate201in a cross-section view. In an embodiment, the at least one channel260extends outside of the boundaries of the recess205in the front side surface202of the package substrate201in a top view. In an embodiment, a total thickness of the substrate201between the front side surface202and the rear side surface203is between 600 μm and 1,500 μm, and a ratio of a depth of the at least one recess205to a total thickness of the substrate201is between 0.0067 and 0.16. In another embodiment, the substrate201includes a substrate core213, a redistribution layer214over the substrate core213, and an outer coating layer215over the redistribution layer214that forms the front side surface202of the substrate201, and the at least one recess205extends at least through the outer coating layer215and into the redistribution layer214.

An additional embodiment is drawn to a method of fabricating a semiconductor package100,200that includes mounting at least one semiconductor integrated circuit (IC) die105over a first side surface102of an interposer103,230, mounting at least one semiconductor device112over a second side surface104of the interposer103,230that is opposite the first side surface102, forming at least one recess205in a front side surface of a package substrate201, forming at least one channel260in a bottom surface of each recess205of the at least one recess205in the front side surface202of the package substrate201, bonding the second side surface104of the interposer103,230to the front side surface202of the package substrate201such that each semiconductor device112overlies a recess205of the at least one recess205in the front side surface202of the package substrate201, and providing an underfill material portion211between the front side surface202of the package substrate201and the second side surface104of the interposer103,230such that the underfill material portion211is located between a lower surface of each semiconductor device112and a bottom surface of a recess205of the at least one recess205in the front side surface of the package substrate underlying the respective semiconductor device112, and the underfill material portion211is located in the at least one channel260. In an embodiment, the method further includes forming the interposer103,230over a first carrier substrate101, forming a plurality of interposer bonding structures106over the first side surface102of the interposer103,230, wherein a plurality of semiconductor IC dies105are mounted over the first side surface102of the interposer103,230via the plurality of first interposer bonding structures106, providing a first underfill material portion107between the first side surface102of the interposer103,230and the underside surfaces of the plurality of semiconductor IC dies105and between the respective semiconductor IC dies105, and forming a molding portion109laterally surrounding the plurality of semiconductor IC dies105.

In another embodiment, the method further includes providing a second carrier substrate111over upper surfaces of the plurality of semiconductor IC dies105, the first underfill material portion107and the molding portion109, removing the first carrier substrate101from the second side surface104of the interposer103,230, forming semiconductor device bonding structures113over the second side surface104of the interposer103,230, where the at least one semiconductor device112is mounted over the second side surface104of the interposer103,230via the semiconductor device bonding structures113, forming a plurality of bonding pads115over the second side surface104of the interposer103,230, where the second side surface104of the interposer103,230is bonded to the front side surface202of the package substrate201via a plurality of solder material portions207located between respective bonding pads115over the second side surface104of the interposer103,230and redistribution structures204exposed through the front side surface202of the package substrate201, and removing the second carrier substrate111from over the upper surfaces of the plurality of semiconductor IC dies105, the first underfill material portion107and the molding portion109.

In another embodiment, forming the at least one recess205in the front side surface202of the package substrate includes forming each recess205of the at least one recess205to have a greater horizontal cross-sectional area than a horizontal cross-section area of a semiconductor device112overlying the respective recess205of the at least recess205upon bonding of the second side surface104of the interposer103,230to the front side surface202of the package substrate201, and where forming the at least one channel260in a bottom surface of each recess of the at least one recess205in the front side surface202of the package substrate201includes forming the at least one channel260having a width dimension WC that is less than a corresponding width dimension of the recess205in which the at least one channel260is formed, a length dimension LC that is less than, equal to, or greater than a corresponding length dimension of the recess205in which the at least one channel260if formed, and a maximum depth dimension DC with respect to the bottom surface205of the recess205in which the at least one channel260is formed that is at least 3 μm.