IMAGE SENSOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. The doped region is between the first pair of sidewalls. The first photodetector and a first gate partially form a first transistor. The second photodetector and a second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

BACKGROUND

Complementary metal-oxide semiconductor (CMOS) image sensors are used in a wide range of modern-day electronic devices, such as, for example, cameras, tablets, smart phones, and so on. CMOS image sensors may be front-side illuminated (FSI) or back-side illuminated (BSI).

Compared to FSI image sensors, BSI image sensors have better sensitivity, better angular response, and greater metal routing flexibility.

DETAILED DESCRIPTION

An integrated chip includes an image sensor. The image sensor includes a pixel along a semiconductor substrate. The pixel includes a first photodetector and a first floating diffusion region in the substrate. The pixel further includes a second photodetector and a second floating diffusion region in the substrate. A first transfer gate is over the first photodetector and a second transfer gate is over the second photodetector. The first photodetector, the first floating diffusion region, and the first transfer gate partially form a first transfer transistor. The second photodetector, the second floating diffusion region, and the second transfer gate partially form a second transfer transistor. The pixel further includes pixel transistors (e.g., a reset transistor, a source-follower transistors, and a select transistor) along the substrate and beside the transfer transistors. For example, source/drain regions of the pixel transistors are in the substrate and beside the photodetectors. The pixel transistors are coupled to one or more of the transfer transistors.

Because the pixel transistors are in the substrate and beside the transfer transistors, a performance of the integrated chip may be reduced. For example, the source/drain regions of the pixel transistors take up space in the substrate, thereby reducing an available space for the first and second photodetectors. Consequently, a photosensitive area of the pixel may be reduced. Further, because the pixel transistors are arranged along the substrate, reducing the pitch of the pixel may be challenging.

In various embodiments of the present disclosure, the pixel transistors are spaced over the substrate to increase the space available for the photodetectors in the substrate. For example, the photodetectors are disposed in a first substrate, the transfer transistors are arranged along the first substrate, and the pixel transistors are arranged along a second substrate. The second substrate is bonded over the first substrate.

By disposing the pixel transistors along a separate substrate than the transfer transistors and the photodetectors, a performance of the integrated chip can be improved. For example, because the pixel transistors are arranged along the second substrate, separate from the first substrate, an area of the photodetectors can be increased. Thus, the photosensitive area of the pixel can be increased. Further, because less transistors are arranged along the first substrate, the pitch of the pixel can be more easily reduced.

FIG.1illustrates a top view100of some embodiments of an integrated chip comprising a pixel102along a first semiconductor substrate104.FIG.2illustrates a first cross-sectional view200of some embodiments of the integrated chip ofFIG.1.FIG.3illustrates a second cross-sectional view300of some embodiments of the integrated chip ofFIG.1andFIG.2. In some embodiments, cross-sectional view200ofFIG.2may, for example, be taken across line A-A′ ofFIG.1. In some embodiments, cross-sectional view300ofFIG.3may, for example, be taken across line B-B′ ofFIG.1.

Referring toFIGS.1-3, the integrated chip includes a first chip138. The first chip138includes the pixel102. The pixel102includes a first photodetector106and a second photodetector108in the first substrate104. For example, the first substrate104includes a first photodiode region110, a second photodiode region112, and a bulk region114. The first photodiode region110and the second photodiode region112are arranged along a frontside104aof the first substrate104. The bulk region114of the first substrate104surrounds the first and second photodiode regions110,112. The bulk region114of the first substrate104has a first doping type (e.g., p-type). The first and second photodiode regions110,112have a second doping type (e.g., n-type), different than the first doping type. The first photodetector106is formed by a first p-n junction between the first photodiode region110and the bulk region114of the first substrate104. The second photodetector108is formed by a second p-n junction between the second photodiode region112and the bulk region114of the first substrate104.

The pixel102may be referred to as a dual photodetector pixel because the pixel102includes the first and second photodetectors106,108in the same pixel. In some instances, dual photodetectors pixels have improved performance (e.g., focusing speed) compared to single photodetector pixels.

A first transfer gate118and a second transfer gate120are over the first photodetector106and the second photodetector108, respectively. A gate dielectric layer119is between the first and second transfer gates118,120and the first substrate104. The first transfer gate118, the gate dielectric layer119, and the first photodetector106partially form a first transfer transistor122. The second transfer gate120, the gate dielectric layer119, and the second photodetector108partially form a second transfer transistor124.

The first chip138further includes a first dielectric structure130over the first substrate104. A first metal interconnect structure132is disposed within the first dielectric structure130and coupled to various features of the pixel102(e.g., the floating diffusion region116, the transfer gates118,120, and/or some other features). The first metal interconnect structure132includes metal contacts156, metal lines158, metal vias160, and metal pads162. A color filter134and a micro-lens136(through which photons may impinge on the photodetectors106,108) are arranged along a backside104bof the first substrate104.

A second chip140is over the first chip138. The second chip140includes a second semiconductor substrate144. Pixel transistors are arranged along the second substrate144. For example, a first pixel transistor146(e.g., a reset transistor), a second pixel transistor148(e.g., a source-follower transistor), and a third pixel transistor150(e.g., a select transistor) are arranged along the second substrate144. Because the pixel transistors146,148,150are arranged along a different substrate than the photodetectors106,108, there is more space available in the first substrate104for the photodetectors106,108. As a result, a photosensitive area of the pixel102can be increased.

A second dielectric structure152is under the second substrate144(e.g., along a frontside of the second substrate144) and a second metal interconnect structure154is within the second dielectric structure152. The second metal interconnect structure154includes metal contacts164, metal lines166, metal vias168, and metal pads170. A first backside dielectric layer142is over the second substrate144(e.g., along a backside of the second substrate144). The first chip138and the second chip140are bonded together along the dielectric structures130,152and the metal interconnect structures132,154. For example, in some embodiments, the dielectric structures130,152and the metal interconnect structures132,154include bonding interface layers (e.g., bonding layers2102,3202ofFIG.35) along which the first and second chips138,140are bonded.

In some embodiments, metal contact(s)156, metal line(s)158, metal via(s)160, and metal pad(s)162of the first metal interconnect structure132are over and coupled to the transfer gates118,120for controlling the voltage at the transfer gates118,120. For example, a first set of metal interconnects of the first metal interconnect structure132are coupled to the first transfer gate118and a second set of metal interconnects of the first metal interconnect structure132, separate and isolated from the first set, are coupled to the second transfer gate120so the transfer transistors122,124can be individually controlled to separately access the first and second photodetectors106,108. The transfer gates118,120are coupled to the second chip140through the first and second metal interconnect structures132,154.

A trench isolation layer126laterally surrounds the first photodetector106and the second photodetector108in a closed path along a boundary of the pixel102. In addition, the trench isolation layer126extends directly between the first photodetector106and the second photodetector108. Because the trench isolation layer126surrounds the first photodetector106and the second photodetector108along the boundary of the pixel102, the trench isolation layer126can isolate the pixel102from neighboring pixels (not shown), thereby reducing a cross-talk between the pixel102and the neighboring pixels. Further, because the trench isolation layer126extends directly between the first photodetector106and the second photodetector108, cross-talk between the first and second photodetectors can be reduced. Furthermore, isolating the pixels using the trench isolation layer126may improve a full well capacity (FWC) of the pixels.

The trench isolation layer126has an opening128therein. The opening128is delimited by a pair of sidewalls126aof the trench isolation layer126. In some embodiments, the opening128is further delimited by an upper surface126bof the trench isolation layer126. The opening128(e.g., the sidewalls126athat delimit the opening128) is directly between the first photodetector106and the second photodetector108. The first substrate104extends continuously from the first photodetector106, between the pair of sidewalls126aand over the upper surface126bof the trench isolation layer126, to the second photodetector108.

The first substrate104further includes a floating diffusion region116. The floating diffusion region116is laterally spaced between the first photodetector106and the second photodetector108. The floating diffusion region116has the second doping type (e.g., n-type). The floating diffusion region116is arranged in the opening128. For example, the floating diffusion region116is directly between the pair of sidewalls126aand directly over the upper surface126bof the trench isolation layer126.

Because the trench isolation layer126has the opening128therein, the floating diffusion region116can be disposed in the first substrate104directly between the first and second photodetectors106,108. Thus, the floating diffusion region116can be shared between the first and second transfer transistors122,124. For example, the first transfer gate118, the gate dielectric layer119, the first photodetector106, and the floating diffusion region116form the first transfer transistor122while the second transfer gate120, the gate dielectric layer119, the second photodetector108, and the floating diffusion region116form the second transfer transistor124. Because the transfer transistors122,124share the floating diffusion region116, a performance of the integrated chip can be improved. For example, by sharing a single floating diffusion region between the transfer transistors122,124(instead of the transfer transistors122,124having individual floating diffusion regions), the number of individual floating diffusion regions in the first substrate104can be reduced. As a result, a floating diffusion capacitance of the image sensor may be reduced and a conversion gain of the image sensor may be improved.

In some embodiments, the first photodiode region110and the floating diffusion region116form source/drain regions of the first transfer transistor122. Similarly, the second photodiode region112and the floating diffusion region116form source/drain regions of the second transfer transistor124. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. In some embodiments, the bulk region114of the first substrate104forms channel regions of the transfer transistors122,124.

Metal interconnects of the first and second metal interconnect structures132,154couple a source/drain region147of the first pixel transistor146, a gate149of the second pixel transistor148, and the floating diffusion region116. For example, metal contact(s)156, metal line(s)158, metal via(s)160, and metal pad(s)162of the first metal interconnect structure132and metal contact(s)164, metal line(s)166, metal via(s)168, and metal pad(s)170of the second interconnect structure154couple the floating diffusion region116to the source/drain region147of the first pixel transistor146and to the gate149of the second pixel transistor148. The second pixel transistor148is coupled to the third pixel transistor150.

In some embodiments, a third chip172is over the second chip140. The third chip172includes a third semiconductor substrate176. The third chip172may be or comprise an application-specific integrated chip (ASIC) or the like. In some embodiments, the third chip comprises circuitry such as, for example, a transistor178along the third substrate176. A third dielectric structure180is under the third substrate176(e.g., along a frontside of the third substrate176) and a third metal interconnect structure182is within the third dielectric structure180.

The second chip140and the third chip172are bonded together along the third dielectric structure180, the first backside dielectric layer142, and the second and third metal interconnect structures154,182. In some embodiments, the second metal interconnect structure154includes a metal through-substrate via (TSV)171extending through the second substrate144and the first backside dielectric layer142to couple the second metal interconnect structure154to the third metal interconnect structure182.

In some embodiments, the third chip172includes a second backside dielectric layer174over the third substrate176(e.g., along a backside of the third substrate176). In some embodiments, the third metal interconnect structure182includes a TSV184extending through the third substrate176and a metal bump186over the second backside dielectric layer174and coupled to the TSV184.

In some embodiments, the substrates104,144,176may for example, comprise silicon or some other suitable semiconductor. In some embodiments, the trench isolation layer126may for example, comprise silicon dioxide, some other suitable dielectric, tungsten, or some other suitable metal. In some embodiments, the gate dielectric layer119may for example, comprise silicon dioxide, some high-k dielectric, or some other suitable material. In some embodiments, the transfer gates118,120may for example, comprise polysilicon, metal, or some other suitable material. In some embodiments, the dielectric layers of the dielectric structures130,152,180and the backside dielectric layers142,174may for example, comprise silicon dioxide, silicon nitride, or some other suitable materials. In some embodiments, the metal interconnects of the metal interconnect structures132,154,182may for example, comprise tungsten, copper, aluminum, or some other suitable material.

FIG.4illustrates a circuit diagram400of some embodiments of the integrated chip ofFIGS.1-3.

The first chip138includes the first and second transfer transistors122,124. The second chip140includes the pixel transistors146,148,150. The first transfer transistor122and the second transfer transistor124share the floating diffusion region116. The first photodetector106and the second photodetector108are selectively coupled to the floating diffusion region116by the first transfer transistor122and the second transfer transistor124, respectively. The floating diffusion region116is coupled to the source/drain region147of the first pixel transistor146and the gate149of the second pixel transistor148. The second pixel transistor148and the third pixel transistor150are serially coupled. In some embodiments, the second chip140further includes pixel circuitry402coupled to the third pixel transistor150. The pixel circuitry402may for example, comprise additional transistors, diodes, resistors, capacitors, inductors, or some other suitable circuitry. In some embodiments, the pixel circuitry402is coupled to ASIC circuitry404of the third chip172. The ASIC circuitry404may for example, comprise transistors (e.g., transistor178ofFIG.2), diodes, resistors, capacitors, inductors, or some other suitable circuitry.

FIG.5illustrates a top view500of some embodiments of the integrated chip ofFIG.1in which a plurality of pixels are arranged along the first substrate104.FIG.6illustrates a cross-sectional view600of some embodiments of the integrated chip ofFIG.5. In some embodiments, cross-sectional view600ofFIG.6may, for example, be taken across line C-C′ ofFIG.5.

Referring toFIG.5andFIG.6, a first pixel102, a second pixel502, a third pixel504, and a fourth pixel506are arranged along the first substrate104. In some embodiments, each of the pixels102,502,504,506include a pair of photodetector regions forming a pair of photodetectors, a floating diffusion region, a pair of transfer gates forming a pair of transfer transistors that share the floating diffusion region, a color filter, and a micro-lens. For example, the first pixel102includes the first and second photodiode regions110,112forming the first and second photodetectors106,108, the first floating diffusion region116, the first and second transfer gates118,120forming the first and second transfer transistors122,124, the first color filter134, and the first micro-lens136. Similarly, the second pixel502includes third and fourth photodiode regions508,510forming third and fourth photodetectors512,514, a second floating diffusion region516, third and fourth transfer gates518,520forming third and fourth transfer transistors522,524, a second color filter526, and a second micro-lens528.

In some embodiments, the transfer gates (e.g., the first and second transfer gates118,120) are symmetric about the floating diffusion regions (e.g., the first floating diffusion region116). In some other embodiments, the transfer gates are asymmetric about the floating diffusing regions (e.g., as shown by dashed features538,540,542,544representing shifted transfer gates).

The trench isolation layer126surrounds, and extends between, each of the pixels102,502,504,506. The trench isolation layer126electrically and/or optically isolates the pixels from each other, thereby reducing cross-talk between the pixels. The trench isolation layer126has openings therein between each of the pairs of photodetectors. For example, a first pair of sidewalls126aof the trench isolation layer126delimit a first opening128in the trench isolation layer126and a second pair of sidewalls126cdelimit a second opening530in the trench isolation layer126. In some embodiments (e.g., as illustrated inFIG.2), the trench isolation layer126extends directly under the first and second openings128,530so the first and second openings128,530are further delimited by upper surfaces (e.g., upper surface126bofFIG.2) of the trench isolation layer126.

In some other embodiments (e.g., as shown inFIG.6), the first substrate104further comprises first and second implant regions546,548in the first and second openings128,530, respectively (e.g., directly between the pairs of sidewalls126a,126cof the trench isolation layer126that delimit the first and second openings128,530, respectively). The implant regions have the first doping type (e.g., p-type). The implant regions provide electrical isolation between the photodetectors. For example, the first implant region546provides isolation between the first photodetector106and the second photodetector108. The second implant region548provides isolation between the third photodetector512and the fourth photodetector514.

The floating diffusion regions are arranged in the openings. For example, the first and second floating diffusion regions116,516are between the sidewalls of the trench isolation layer126that delimit the first and second openings128,530, respectively. In some embodiments, the floating diffusion regions116,516are over the upper surfaces (e.g., upper surface126bofFIG.2) of the trench isolation layer126. In some other embodiments, the floating diffusion regions are over the implant regions (e.g., the first and second implant regions546,548).

In some embodiments, pixel transistors are disposed over, and coupled to, each of the transfer transistors. For example, in some embodiments, the first pixel transistor146, the second pixel transistor148, and the third pixel transistor150are over and coupled to the first floating diffusion region116. Similarly, a fourth pixel transistor532, a fifth pixel transistor534, and a sixth pixel transistor536are over and coupled to the second floating diffusion region516.

FIG.7illustrates a top view700of some embodiments of the integrated chip ofFIG.1in which four transfer transistors share a floating diffusion region.FIG.8illustrates a first cross-sectional view800of some embodiments of the integrated chip ofFIG.7.FIG.9illustrates a second cross-sectional view900of some embodiments of the integrated chip ofFIG.8.FIG.10illustrates a circuit diagram1000of some embodiments of the integrated chip ofFIGS.7-9. In some embodiments, cross-sectional view800ofFIG.8may, for example, be taken across line D-D′ ofFIG.7. In some embodiments, cross-sectional view900ofFIG.9may, for example, be taken across line E-E′ ofFIG.7.

Referring toFIGS.7-10, the integrated chip includes a first pixel102, a second pixel702, a third pixel704, and a fourth pixel706arranged along the first substrate104. The first pixel102includes the first and second photodiode regions110,112forming the first and second photodetectors106,108, the first and second transfer gates118,120forming the first and second transfer transistors122,124, the first color filter134, and the first micro-lens136. Similarly, the second pixel702includes third and fourth photodiode regions708,710forming third and fourth photodetectors712,714, third and fourth transfer gates716,718forming third and fourth transfer transistors720,722, a second color filter724, and a second micro-lens726.

A first opening728is in the trench isolation layer126between the first pixel102and the second pixel502. The first opening728is formed by a first pair of sidewalls126dand a second pair of sidewalls126eof the trench isolation layer126. In some embodiments, the first opening728is further delimited by a first upper surface126fof the trench isolation layer126. The first substrate104extends continuously through the first opening728(e.g., between the first pair of sidewalls126d, between the second pair of sidewalls126e, and over the first upper surface126fof the trench isolation layer126) between each of the photodetectors106,108,712,714of the first and second pixels102,702. The floating diffusion region116is disposed in the first opening728(e.g., between the first pair of sidewalls126d, between the second pair of sidewalls126e, and over the first upper surface126fof the trench isolation layer126).

The floating diffusion region116is shared by the first pixel102and the second pixel702. For example, the first transfer transistor122, the second transfer transistor124, the third transfer transistor720, and the fourth transfer transistor722share the floating diffusion region116. By sharing a single floating diffusion region116between the four transfer transistors, the number of individual floating diffusion regions in the first substrate104can be further reduced. As a result, a floating diffusion capacitance of the image sensor may be further reduced and a conversion gain of the image sensor may be further improved. The first pixel transistor146, the second pixel transistor148, and the third pixel transistor150are over and coupled to the first floating diffusion region116.

In some embodiments, a second opening734is in the trench isolation layer126between the first photodetector and the second photodetector108. The second opening734is delimited by a third pair of sidewalls126gof the trench isolation layer126. In some embodiments, the second opening734is further delimited by a second upper surface126hof the trench isolation layer126. The first substrate104extends continuously through the second opening734(e.g., between the third pair of sidewalls126gand over the second upper surface126hof the trench isolation layer126) between the first and second photodetectors106,108. Similarly, a third opening736is in the trench isolation layer126between the third photodetector712and the fourth photodetector714. The third opening736is delimited by a fourth pair of sidewalls126iof the trench isolation layer126. In some embodiments, the third opening736is further delimited by a third upper surface (not shown) of the trench isolation layer126. The first substrate104extends continuously through the third opening736(e.g., between the fourth pair of sidewalls126iand over the third upper surface (not shown) of the trench isolation layer126) between the third and fourth photodetectors712,714.

In some embodiments, the first substrate104includes a first implant region730in the second opening734and a second implant region732in the third opening736. The first implant region730and the second implant region732have the first doping type (e.g., p-type). In some embodiments, the implant regions provide isolation between the neighboring photodetectors (e.g.,106,108and712,714). In some other embodiments, the implant regions (e.g.,730,732) are body contact regions for coupling to the bulk region114of the first substrate104.

FIG.11illustrates a top view1100of some other embodiments of an integrated chip comprising a pixel102along a first substrate104.FIG.12illustrates a cross-sectional view1200of some embodiments of the integrated chip ofFIG.11. In some embodiments, cross-sectional view1200ofFIG.12may, for example, be taken across line F-F′ ofFIG.11.

The integrated chip includes a first pixel102, a second pixel1102, a third pixel1104, and a fourth pixel1106arranged along the first substrate104. Each pixel includes a pair of floating diffusion regions. For example, the first pixel102includes first and second floating diffusion regions1110,1112. The first photodetector106, the first floating diffusion region1110, and the first transfer gate118form the first transfer transistor122. The second photodetector108, the second floating diffusion region1112, and the second transfer gate120form the second transfer transistors122,124

The trench isolation layer126has openings therein between each of the pairs of photodetectors. For example, a first opening1116in the trench isolation layer126is delimited by a first pair of sidewalls126gof the trench isolation layer126. The first substrate104comprises implant regions in the openings. For example, a first implant region1114is in the first opening1116. The implant regions have the first doping type (e.g., p-type). In some embodiments, the implant regions isolate the photodetectors from each other. In some other embodiments, the first implant region1114is a body contact region. Because the pixels share a single implant region, a performance of the pixels may be improved.

In some embodiments, a first set of pixel transistors (e.g., the first pixel transistor146, the second pixel transistor148, and the third pixel transistor150) are over and coupled to the first floating diffusion region1110, a second set of pixel transistors (not shown) are over and coupled to the second floating diffusion region1112.

FIGS.13-36illustrate views1300-3600of some embodiments of a method for forming an integrated chip comprising a pixel along a first semiconductor substrate. AlthoughFIGS.13-36are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.13-36are not limited to such a method, but instead may stand alone as structures independent of the method.

FIGS.13-30illustrate views1300-3000of some embodiments of a method for forming a first chip138including a pixel102along a first substrate104.

As shown in top view1300ofFIG.13and corresponding cross-sectional view1400ofFIG.14, a first photodetector106and a second photodetector108are formed in a first semiconductor substrate104. For example, a first photodiode region110and a second photodiode region112are formed in the first substrate104along a frontside104aof the first substrate104. A bulk region114of the first substrate104surrounds the photodiode regions110,112. The bulk region114of the first substrate104has a first doping type (e.g., p-type) and the photodiode regions110,112have a second doping type (e.g., n-type), different than the first doping type. The photodiode regions110,112and the bulk region114of the first substrate104form the photodetectors106,108.

In some embodiments, the photodiode regions110,112are formed in the first substrate104by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a masking layer1402is formed over the frontside104aof the first substrate104and the photodiode regions110,112are formed in the first substrate104according to openings in the masking layer1402. In some embodiments, the masking layer1402may, for example, comprise photoresist, a dielectric hard mask, or some other suitable material. The masking layer1402is not shown in top view1300ofFIG.13.

As shown in top view1500ofFIG.15and corresponding cross-sectional view1600ofFIG.16, a gate dielectric layer119is deposited over the frontside104aof the first substrate104and a gate layer1502is deposited over the gate dielectric layer119. In some embodiments, the gate dielectric layer119may for example, comprise silicon, some high-k dielectric, or some other suitable material. In some embodiments, the gate layer1502may, for example, comprise polysilicon, metal, or some other suitable material. In some embodiments, the gate dielectric layer119and/or the gate layer1502may be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

As shown in top view1700ofFIG.17and corresponding cross-sectional view1800ofFIG.18, the gate layer (e.g.,1502ofFIG.15andFIG.16) and the gate dielectric layer119are patterned to form a first transfer gate118and a second transfer gate120from the gate layer1502. In some embodiments, the patterning comprises forming a masking layer1802over the gate layer1502and etching the gate layer1502and the gate dielectric layer119according to the masking layer1802.

In some embodiments, the etching comprises a dry etching process (e.g., plasma etching, reactive ion etching, ion beam etching, or the like) or some other suitable etching process. In some embodiments, the masking layer1802may, for example, comprise photoresist, a dielectric hard mask, or some other suitable material. The masking layer1802is not shown in top view1700ofFIG.17.

As shown in top view1900ofFIG.19and corresponding cross-sectional view2000ofFIG.20, a floating diffusion region116is formed in the first substrate104along a frontside104aof the first substrate104and between the transfer gates118,120. The floating diffusion region116has the second doping type (e.g., n-type). By forming the floating diffusion region116in the first substrate104between the transfer gates118,120, a first transfer transistor122and a second transfer transistor124(which share the floating diffusion region116) are formed along the first substrate104.

In some embodiments, the floating diffusion region116is formed in the first substrate104by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a masking layer2002is formed over the first substrate104and over portions of the transfer gates118,120. The floating diffusion region116is formed in the first substrate104according to an opening in the masking layer2002and according to sidewalls of the transfer gates118,120. In some embodiments, the masking layer2002does not cover portions the transfer gates118,120so the floating diffusion region116can be “self-aligned” to the transfer gates118,120. In some embodiments, the masking layer2002may, for example, comprise photoresist, a dielectric hard mask, or some other suitable material. The masking layer2002is not shown in top view1900ofFIG.19.

As shown in cross-sectional view2100ofFIG.21, a first dielectric structure130and a first metal interconnect structure132are formed over the transfer transistors122,124. In some embodiments, the first dielectric structure130is formed by depositing a plurality of dielectric layers over the first substrate104. In some embodiments, the first metal interconnect structure132is formed by forming a plurality of metal contacts156, metal lines158, metal vias160, and metal pads162within the first dielectric structure130. In some embodiments, a top dielectric layer of the first dielectric structure130and the metal pads162of the first metal interconnect structure132form a first bonding layer2102.

In some embodiments, the dielectric layers of the first dielectric structure130comprise silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the dielectric layers of the first dielectric structure130may be deposited by CVD processes, PVD processes, ALD processes, or some other suitable processes. In some embodiments, the metal interconnects of the first metal interconnect structure132may comprise copper, aluminum, tungsten, or some other suitable material. In some embodiments, the metal interconnects of the first metal interconnect structure132may be formed by etching the dielectric layers of the first dielectric structure130and depositing metal over the etched dielectric layers.

FIG.22illustrates top view2200andFIG.23illustrates corresponding cross-sectional views2300of some embodiments of a first method for forming a trench2302in the first substrate104.

As shown in top view2200ofFIG.22and corresponding cross-sectional view2300ofFIG.23, a backside104bof the first substrate104, opposite the frontside104a, is etched to form a trench2302in the first substrate104. The trench2302is delimited by sidewalls104c,104d,104e,104f,104h,104iof the first substrate104, a bottom surface130aof the first dielectric structure130, and a lower surface104gof the first substrate104. The trench2302surrounds, and extends between, the first and second photodetectors106,108. In some embodiments, the trench2302extends through the first substrate104to the first dielectric structure130except directly over the floating diffusion region116. Directly over the floating diffusion region116, the trench2302extends to a depth2306below the backside104bof the first substrate104that is less than the thickness2308of the first substrate104. Thus, the trench2302does not extend through the floating diffusion region116.

In some embodiments, a masking layer2304is formed over the backside104bof the first substrate104and the etching is performed according to the masking layer2304. In some embodiments, the etching comprises a dry etching process (e.g., plasma etching, reactive ion etching, ion beam etching, or the like) or some other suitable etching process. In some embodiments, the masking layer2304may, for example, comprise photoresist, a dielectric hard mask, or some other suitable material. The masking layer2304is not shown in top view2200ofFIG.22.

FIGS.24-27illustrate views2400-2700of some embodiments of a second method for forming a trench2502in the first substrate104.

As shown in top view2400ofFIG.24and corresponding cross-sectional view2500ofFIG.25, the backside104bof the first substrate104is etched to form the trench2502in the first substrate104. The trench2502is delimited by sidewalls104c,104f,104j,104kof the first substrate104and a bottom surface130aof the first dielectric structure130. The trench2502does not extend into the first substrate104directly over the floating diffusion region116.

In some embodiments, a masking layer2504is formed over the backside104bof the first substrate104and the etching is performed according to the masking layer2504. The masking layer2504is not shown in top view2400ofFIG.24.

As shown in top view2600ofFIG.26and corresponding cross-sectional view2700ofFIG.27, an implant region546is formed in the first substrate104along the backside104bof the first substrate104and between the photodetectors106,108. The implant region546has the first doping type (e.g., p-type). In some embodiments, the implant region546is formed in the first substrate104by an ion implantation process, a diffusion process, or some other suitable process. In some embodiments, a masking layer2702is formed over the first substrate104and the implant region546is formed in the first substrate104according to an opening in the masking layer2702.

As shown in top view2800ofFIG.28and cross-sectional view2900ofFIG.29, a trench isolation layer126is formed in the trench (e.g.,2302ofFIG.23or2502ofFIG.27). In some embodiments, forming the trench isolation layer126in the trench includes depositing the trench isolation layer126over the backside104bof the first substrate104and in the trench, and performing a planarization process (e.g., a chemical mechanical planarization (CMP) or some other suitable process) on the trench isolation layer126. In some embodiments, the planarization process removes the trench isolation layer126from the backside104bof the first substrate104.

In some other embodiments (not shown), a portion of the trench isolation layer126remains on the backside104bof the first substrate104.

In some embodiments, the trench isolation layer126comprises silicon dioxide, tungsten, or some other suitable material. In some embodiments, the trench isolation layer126may be deposited a CVD process, a PVD process, an ALD process, or some other suitable process.

As shown in cross-sectional view3000ofFIG.30, a color filter134and a micro-lens136are formed over the backside104bof the first substrate104.

FIGS.31-34illustrate views3100-3400of some embodiments of a method for forming a second chip140.

As shown in cross-sectional view3100ofFIG.31, a plurality of pixel transistors are formed along a second semiconductor substrate144. For example, a first pixel transistor146, a second pixel transistor148, and a third pixel transistor150are formed along a frontside of the second substrate144.

As shown in cross-sectional view3200ofFIG.32, a second dielectric structure152and a second metal interconnect structure154are formed over the pixel transistors146,148,150. In some embodiments, forming the second dielectric structure152includes depositing a plurality of dielectric layers over the second substrate144. In some embodiments, forming the second interconnect structure154includes forming a plurality of metal contacts164, metal lines166, metal vias168, and metal pads170within the second dielectric structure152. In some embodiments, a top dielectric layer of the second dielectric structure152and the metal pads170of the second interconnect structure154form a second bonding layer3202.

In some embodiments, the dielectric layers of the second dielectric structure152may comprise silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the dielectric layers of the second dielectric structure152may be deposited by CVD processes, PVD processes, ALD processes, or some other suitable processes. In some embodiments, the metal interconnects of the second metal interconnect structure154may comprise copper, aluminum, tungsten, or some other suitable material.

As shown in cross-sectional view3300ofFIG.33, a first backside dielectric layer142is formed along a backside of the second substrate144. In some embodiments, the first backside dielectric layer142may comprise silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the first backside dielectric layer142may be deposited by CVD processes, PVD processes, ALD processes, or some other suitable processes.

As shown in cross-sectional view3400ofFIG.34, a TSV171is formed in the second chip140. In some embodiments, the TSV171is formed by etching the first backside dielectric layer142, the second substrate144, and the second dielectric structure152, depositing metal over the etched layers, and planarizing the metal.

As shown in cross-sectional view3500ofFIG.35, the first chip138and the second chip140are bonded together along the first dielectric structure130, the second dielectric structure152, the first metal interconnect structure132, and the second metal interconnect structure154. For example, the first chip138and the second chip140are bonded together along the first and second bonding layers2102,3202. The bonding couples the metal interconnect structures132,154so that the floating diffusion region116of the first chip138is coupled to the pixel transistors146,148,150of the second chip140by the first and second metal interconnect structures132,154. In some embodiments, the bonding comprises a fusion bonding process or some other suitable process.

As shown in cross-sectional view3600ofFIG.36, a third chip172is bonded over the backside of the second chip140. The third chip172comprises a third semiconductor substrate176, a transistor178along the third substrate176, a third dielectric structure180along a front side of the third substrate176, a third metal interconnect structure182in the third dielectric structure180, and a second backside dielectric layer174along a backside of the third substrate176. In some embodiments, the third chip172is bonded to the second chip140along the first backside dielectric layer142and the third dielectric structure180of the third chip172. In some embodiments, the bonding comprises a fusion bonding process or some other suitable process.

At block3702, form a first photodetector and a second photodetector in a first semiconductor substrate along a first side of the first semiconductor substrate.FIG.13illustrates a top view1300andFIG.14illustrates a corresponding cross-sectional view1400of some embodiments corresponding to block3702.

At block3704, form a first transfer gate over the first photodetector and a second transfer gate over the second photodetector.FIG.17illustrates a top view1700andFIG.18illustrates a corresponding cross-sectional view1800of some embodiments corresponding to block3704.

At block3706, form a floating diffusion region in the first semiconductor substrate between the first photodetector and the second photodetector.FIG.19illustrates a top view1900andFIG.20illustrates a corresponding cross-sectional view2000of some embodiments corresponding to block3706.

At block3708, form a first metal interconnect structure over the first side of the first semiconductor substrate.FIG.21illustrates a cross-sectional view2100of some embodiments corresponding to block3708.

At block3710, etch a second side of the first semiconductor substrate, opposite the first side, to form a trench in the first semiconductor substrate.FIG.22andFIG.24illustrate top views2200,2400of some embodiments corresponding to block3710.FIG.23andFIG.25illustrate corresponding cross-sectional views2300,2500of some embodiments corresponding to block3710.

At block3712, deposit a trench isolation layer in the trench, the trench isolation layer having an opening therein between the first photodetector and the second photodetector, the first semiconductor substrate extending through the opening from the first photodetector to the second photodetector.FIG.28illustrates a top view2800andFIG.29illustrates a corresponding cross-sectional view2900of some embodiments corresponding to block3712.

At block3714, form a color filter and a micro-lens directly over the first photodetector and the second photodetector.FIG.30illustrates a cross-sectional view3000of some embodiments corresponding to block3714.

At block3716, form a first pixel transistor along a first side of a second semiconductor substrate.FIG.31illustrates a cross-sectional view3100of some embodiments corresponding to block3716.

At block3718, form a second metal interconnect structure over the first side of the second semiconductor substrate.FIG.32illustrates a cross-sectional view3200of some embodiments corresponding to block3718.

At block3720, bond the second semiconductor substrate over the first side of the first semiconductor substrate so the first metal interconnect structure is coupled to the second metal interconnect structure.FIG.35illustrates a cross-sectional view3500of some embodiments corresponding to block3720.

At block3722, bond a third semiconductor substrate over a second side of the second semiconductor substrate.FIG.36illustrates a cross-sectional view3600of some embodiments corresponding to block3722.

Thus, the present disclosure relates to an integrated chip and a method for forming the integrated chip, the integrated chip including a dual photodetector pixel along a first substrate and pixel transistors along a second substrate that is spaced over the first substrate.

Accordingly, in some embodiments, the present disclosure relates to an integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. The second photodetector is laterally spaced from the first photodetector. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls between the first photodetector and the second photodetector. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls of the trench isolation layer, to the second photodetector. The doped region is between the first pair of sidewalls of the trench isolation layer. A first gate and a second gate are over the first photodetector and the second photodetector, respectively. The first photodetector and the first gate partially form a first transistor. The second photodetector and the second gate partially form a second transistor. A first metal interconnect and a second metal interconnect are over the first gate and the second gate, respectively. The first metal interconnect is coupled to the first gate. The second metal interconnect is coupled to the second gate. A second semiconductor substrate is over and spaced from the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

In other embodiments, the present disclosure relates to an integrated chip including a first semiconductor substrate, the first semiconductor substrate including a shared floating diffusion region. A first photodetector and a second photodetector are in the first semiconductor substrate. The first photodetector and the second photodetector are on opposite sides of the shared floating diffusion region. A first transfer gate and a second transfer gate are over the first photodetector and the second photodetector, respectively. The first photodetector, the shared floating diffusion region, and the first transfer gate partially form a first transfer transistor. The second photodetector, the shared floating diffusion region, and the second transfer gate partially form a second transfer transistor. A first metal interconnect and a second metal interconnect are over the first transfer gate and the second transfer gate, respectively. The first metal interconnect is coupled to the first transfer gate. The second metal interconnect is coupled to the second transfer gate. A second semiconductor substrate is over and spaced from the first transfer transistor and the second transfer transistor. A first pixel transistor is along the second semiconductor substrate. A third metal interconnect is between the first pixel transistor and the shared floating diffusion region. The third metal interconnect is coupled to the first pixel transistor and the shared floating diffusion region. A trench isolation layer laterally surrounds the first photodetector and the second photodetector. The trench isolation layer extending between the first photodetector and the second photodetector. A first pair of sidewalls of the trench isolation layer delimit an opening in the trench isolation layer and between the first photodetector and the second photodetector. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls of the trench isolation layer, to the second photodetector. The shared floating diffusion region is between the first pair of sidewalls of the trench isolation layer.

In yet other embodiments, the present disclosure relates to a method for forming an integrated chip. The method includes forming a first photodetector and a second photodetector in a first semiconductor substrate along a first side of the first semiconductor substrate. A first transfer gate and a second transfer gate are formed over the first photodetector and the second photodetector, respectively. A floating diffusion region is formed in the first semiconductor substrate between the first photodetector and the second photodetector. A first metal interconnect is formed over and coupled to the first transfer gate. A second metal interconnect is formed over and coupled to the second transfer gate. A third metal interconnect is formed over and coupled to the floating diffusion region. A trench isolation layer is formed surrounding the first photodetector and the second photodetector and extending between the first photodetector and the second photodetector. The trench isolation layer has an opening therein between the first photodetector and the second photodetector. The first semiconductor substrate extends through the opening from the first photodetector to the second photodetector. A first pixel transistor is formed along a first side of a second semiconductor substrate. A fourth metal interconnect is formed over and coupled to the first pixel transistor. The second semiconductor substrate is bonded over the first side of the first semiconductor substrate so the third metal interconnect is coupled to the fourth metal interconnect.