Method and structure for forming MOSFET with reduced parasitic capacitance

A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.

BACKGROUND

The present invention relates to MOSFET devices, and more specifically, the formation of an ultra low-k film between the gate and source/drain contacts reduces the gate-source and gate-drain parasitic capacitances.

FIG. 1shows exemplarily a finFET (Fin Field Effect Transistor)100, a type of non-planar transistor used in many modern processor designs. It can be fabricated on an SOI (silicon on insulator) substrate or on a Si (silicon) substrate and is characterized by one or more fin structures102that form the conductive channel controlled by the gate structure104. This fin-shaped structure permits multiple gates to operate on a single transistor, such as demonstrated by structure110, and permits devices that are smaller, faster, and more energy efficient.

The present inventors have recognized that the shrinking of the finFET structure results in an undesired relatively high parasitic capacitance between the gate and source/drain contacts and have identified various factors in the conventional fabrication of finFET devices that contribute to this high parasitic capacitance, as follows. First, the shrinking of the gate pitch limits the spacer thickness, and a thinner spacer provides a capacitor structure with higher capacitance. Additionally, an etchant that is selective to the material used for the spacer limits the options for the spacer material. Finally, the spacer is often damaged during the contact open stage of fabrication, which is the fabrication stage during which the source and drain regions are exposed for metal deposition for contacts.

The present invention discloses a novel flow and unique structure to resolve the above-identified issues. Although the following discussion uses the finFET for purpose of explanation, the present invention is not intended as limited specifically to finFET structures since it is equally applicable to any MOSFET-like structure having a gate structure with spacers to separate the gate from the source/drain structures.

SUMMARY

FIG. 2shows an exemplary conventional finFET structure200, from a plan view202and from a cross-sectional view204, after the post gate cap polish (CMP). As shown in the cross-sectional view204, the conventional structure includes SiBCN (Silicon-Boron-Carbon-Nitride) thin film gate spacers206, which material has a high-k characteristic, as does the high-k film (e.g., high impedance film layer)214underlying the gate structure208and comprising HfO2. The present inventors have recognized that such high-k material inherently results in a higher parasitic capacitance between the gate structure208and source/drain structures210,212(source/drain epitaxial regions) than would result if the spacer material had different characteristics. However, SiBCN is conventionally used because its thermal characteristics support the initial formation of the gate structures.

Accordingly, the present invention teaches to modify the conventional gate spacers206having high-k composition to at least partially replace this film with a material having an ultra low-k characteristic. Such modification decreases the dielectric characteristic so that this modified gate spacer can no longer serve as efficiently as a capacitor, thereby decreasing its parasitic capacitance.

DETAILED DESCRIPTION

With reference now beginning withFIG. 3, two exemplary embodiments will now be explained for finFETs. As mentioned above, the present invention is also applicable in other devices, such as MOS-like devices, having spacer elements separating a gate structure from the source/drain.FIG. 3shows a cross-sectional view300and plan view302at the stage that the oxide layer214of conventional device shown inFIG. 2has been etched in preparation for the the source/drain contact open mask304, using, for example, an oxide RIE (reactive ion etch).

A first exemplary embodiment will be explained beginning withFIG. 4. A characteristic feature of this first exemplary embodiment is that a top of a residual of the SiBCN spacer402extends below the top of epi layer404. As shown inFIG. 4, the first step of this first embodiment is an etch of the exposed SiBCN spacer (306inFIG. 3), so as to create a divot406(e.g., a cavity or space) between the gate and source/drain at the epi layer404, by over-etch. The etch of the SiBCN can be implemented either as an isotropic etch or as an RIE (reactive ion etch). A portion of the SiBCN layer remains above the fin in order to protect the gate structure during the downstream processes described shortly by inadvertently permitting the fin to contact either the gate dielectric or metal gate.

The divot406is a high-aspect-ratio structure. Therefore, during spacer material deposition using an ultra low-k material and as exemplarily shown inFIG. 5, it is easy to pinch off the divot on its top area to trap an air gap inside the divot space. This pinch-off characteristic, with its associated air pocket remaining inside the divot cavity, is intentional in the first exemplary embodiment, since it avoids having to use additional steps to completely fill in the etched-out space, while providing an ultra low-k value for this vacated region between the gate and the source/drain epi regions, since air also provides an ultra low-k value close to 1.

FIG. 5shows the structure500after the ultra low-k film502deposition, including air spacer504resultant from the divot pinch-off effect. Unlike the original SiBCN spacer (k-value is around 5), ultra low-k material, for example SiCOH (a thin film comprising silicon Si, carbon C, oxygen O, and hydrogen H and having a k-value of approximately 2.5), is deposited as a partial substitute spacer material502. Such ultra low-k materials can be used because there is no more high thermal budget (e.g., source/drain dopant and activation anneal) required for the BEOL (Back End of the Line) processing of the devices, nor is any more aggressive cleaning (epi preclean) needed.

The first embodiment is characterized by air spacers504between the epi layer and the gate, and the combination of the air space with k≈1 and SiCOH with k≈2.5 provides an ultra low-k gate spacer that reduces the gate/source/drain parasitic capacitance. Other possible (non-limiting) examples of ultra low-k materials would be organosilica glasses (OSG), porous xerogel, or mesoporous silica films (MCM). InFIG. 6, an RIE (reactive ion etch)602provides a vertical etch to remove the top surface of the ultra low-k film while retaining the vertical components of the film on the sidewalls of the gates.

InFIG. 7, tungsten702is deposited for the source/drain metal, to be followed by routine planarization, resulting in a finFET structure having ultra low-k spacers704with air spacers, as well as portions706of the original SiBCN spacer.

FIG. 8shows an exemplary second embodiment800, which differs from the first exemplary embodiment700by reason that the SiBCN spacer802is not over-etched as in the first embodiment. Thus, in the second embodiment the original underlying SiBCN spacer film is retained to be at the same height as the source/drain epi804top surface. As shown inFIG. 8, again, an etch (either isotropic or RIE) is used to remove the original SiBCN spacer layer (see306,FIG. 3) from the gate structure.

Typically, the exposed SiBCN can first be removed rapidly, which was followed in the first embodiment by an additional etch to additionally remove the SiBCN spacer between the gate and epi layer. Thus, the etch of the original SiBCN spacer film306is faster in the second embodiment because no additional etch time is required to over-etch SiBCN film material below the top of the source/drain epi regions. As in the first embodiment, a portion of SiBCN again remains above the fin so that the downstream processes will not damage the gate stack.

FIG. 9shows the fabrication structure900of the second embodiment after the ultra low-k film902deposition, and, similar to exemplary embodiment1, the ultra low-k material902can be used because there is no more high thermal budget required.FIG. 10shows the vertical etch (e.g., RIE1002) used to remove tops of the ultra low-k film902from the top of the gate structures and the source/drain epi areas, leaving ultra low-k film as the vertical sidewall spacers of the gates.FIG. 11shows the tungsten metal deposition1102for the source/drain contacts and further planarization, resulting in the finFET structure1100with ultra low-k spacers1104and portions1106of the original SiBCN spacer material.

In comparingFIG. 7withFIG. 11, it should be clear that the exemplary second embodiment does not include the air spacer present in the first exemplary embodiment.

In the first exemplary embodiment, the gate spacer comprises the ultra low-k spacer as a top portion, the air gap as a middle portion, and the original SiBCN layer as a bottom portion. In the second exemplary embodiment, the spacer comprises the ultra low-k spacer as a top portion and the original SiBCN spacer layer as a bottom portion. Therefore, because of the low-k effect of the air spacer, the first exemplary embodiment has an advantage of providing a lower parasitic capacitance than that of the second embodiment. However, the first embodiment has the disadvantage that the divot height is not easy to control precisely.

FIG. 12shows in flowchart format1200processing steps related to the two exemplary embodiments. In step1202, the device is fabricated in the conventional manner for the Front-End-of-Line (FEOL) and Middle-of-Line (MOL) processings, meaning that the fabrication stages for fabricating the pattern of components in the substrate uses conventional FEOL processing and the gate structure fabrication uses conventional MOL processing, including SiBCN material for gate spacers. In step1204the conventional S/D Open Mask step etches the oxide layer. In step1206, the conventional SiBCN spacer is etched partially from the vertical walls of the gate structures, leaving a lower portion to protect against subsequent damage at the gate/channel interface. In step1208, the ultra low-k material is formed on the vertical gate structure walls, and, in step1210, the source/drain contacts are completed.

FIG. 13shows a planar MOSFET configuration that exhibits an exemplary embodiment described above, having source/drain1302,1304and an upper portion of ultra low-k spacer material1306. A portion1308remains of the original SiBCN spacer, to protect against damage at the gate/channel interface.