Integrated circuits with metal-titanium oxide contacts and fabrication methods

Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly, to integrated circuits with metal-titanium oxide contacts and fabrication methods.

BACKGROUND OF THE INVENTION

Semiconductor devices may be fabricated to have one or more different device characteristics, such as contact resistance, interface layer thickness, threshold voltage, leakage power consumption, etc. Multiple different designs may each allow for optimization of one or more of the semiconductor device characteristics to optimize performance of specific functions. For instance, a nickel silicide contact may have a low contact resistivity but may cause source/drain shorts and static random access memory (SRAM) yield loss. While titanium silicide contacts may have a relatively high contact resistivity so the defect of nickel silicide contacts isn't formed, but device performance is degraded due to the high contact resistivity. Thus, each characteristic of a semiconductor device must be optimized in order to obtain the desired semiconductor devices characteristics.

BRIEF SUMMARY

The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, a device is provided which includes, for instance: a substrate; at least one field-effect transistor disposed on the substrate; a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric; and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. The first contact region is provided which includes, for instance: at least one first opening positioned between the spacer and interlayer dielectric; a first layer on a bottom portion of the at least one first opening; at least one barrier layer over the first layer and two sides of the at least one first opening; a first metal layer over the at least one barrier layer; and a second metal layer over the first metal layer.

In another aspect, a method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device which includes, for instance: etching at least one opening in the intermediate semiconductor device; depositing a chemical oxide into the at least one opening; applying at least one barrier layer over the intermediate semiconductor device; depositing at least one dielectric layer over the barrier layer; and annealing the intermediate semiconductor device. The intermediate semiconductor device is provided which includes, for instance: a substrate; a dielectric layer over the substrate; at least one spacer over the substrate; and at least one field-effect transistor disposed on the substrate.

DETAILED DESCRIPTION

Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.

Generally stated, disclosed herein are certain integrated circuits, including conventional planar complementary metal-oxide semiconductors (CMOS) devices and field-effect transistors (FETs), which provide advantages over the above noted, existing semiconductor devices and fabrication processes. Advantageously, the integrated circuit device fabrication processes disclosed herein provide for CMOS and FET devices with lower minimum contact resistance and an increase in contact resistance with increasing interface.

In one aspect, in one embodiment, as shown inFIG. 1A, integrated circuit device formation in accordance with one or more aspects of the present invention may include, for instance: obtaining an intermediate semiconductor device100and forming at least one contact on the intermediate semiconductor device110.

The process shown inFIG. 1Ais inherent in the more detailed integrated circuit structure formation processes shown inFIGS. 1B and 1C. Specifically, the integrated circuit formation process ofFIG. 1Bis in accordance with one or more aspects of the present invention and may include, for instance: obtaining an intermediate semiconductor device100and forming at least one contact on the intermediate semiconductor device110. The forming at least one contact on the intermediate semiconductor device110may include, for instance: forming at least one opening in the intermediate semiconductor device112; applying a chemical oxide in the at least one opening114; depositing a barrier layer116; depositing at least one dielectric layer118; annealing the intermediate semiconductor device120; applying a photo resist layer122; etching the dielectric layer(s) from at least one first set of openings124; removing the photo resist layer126; depositing a first metal layer128; applying an organic planar layer over the device130; etching the dielectric layer(s) from at least one second set of openings132; removing the organic planar layer134; depositing a second metal layer136; depositing a third metal layer138; and planarizing the device to form contacts140.

Further, the integrated circuit formation process ofFIG. 1Cis in accordance with one or more aspects of the present invention and may include, for instance: obtaining an intermediate semiconductor device100and forming at least one contact on the intermediate semiconductor device110. The forming at least one contact on the intermediate semiconductor device110may include, for instance: depositing a stop layer150; forming at least one first set of contacts152; planarizing the device to the stop layer154; depositing additional stop layer material over the device156; forming at least one second set of contacts158; and planarizing the device to remove the stop layer and expose a first set of contacts and a second set of contacts160.

FIGS. 2A-14depict, by way of example only, one detailed embodiment of a portion of a FinFET device formation process and a portion of an intermediate FinFET structure, in accordance with one or more aspects of the present invention. Note again that these figures are not drawn to scale in order to facilitate understanding of the invention, and that the same reference numerals used throughout different figures designate the same or similar elements.

FIG. 2Ashows one embodiment of a portion of an integrated circuit200with varying gate structures204disposed over a substrate structure202. The substrate202may be made of, for example, a semiconductor material, e.g., silicon (Si), germanium (Ge), a compound semiconductor material, and a layered semiconductor material. The integrated circuit200may also include at least one source region205,206and at least one drain region207,208, which may be epitaxially grown in the substrate202. The at least one source region205and at least one drain region207may be, for example, embedded silicon germanium (eSiGe) for pFETs. While the at least one source region206and at least one drain region208may be, for example, embedded silicon phosphorus (eSiP) for nFETs. The gate structures204, at least one source205,206, and at least one drain207,208may form at least one field-effect transistor. The integrated circuit200may also include at least one fin210with the at least one gate structure204positioned over the fins210and the fins210connecting the at least one source205,206and at least one drain207,208. The integrated circuit device200may also include various isolation regions, doped regions, and/or other device features. A portion of the intermediate circuit structure200obtained during circuit fabrication is shown inFIG. 2Band includes a first portion212and a second portion214.

FIGS. 3-14show two portions212,214of the integrated circuit device200during the fabrication process. The device200may have been processed through initial device processing steps in accordance with the design of the device200being fabricated, for example, gate stack formation, such as, replacement gate. As shown inFIG. 3, the openings216are formed in at least a portion of the intermediate device200, for example, between the spacers218and interlayer dielectric220of the intermediate device200. A chemical oxide layer for first layer222may be formed in the openings216, for example, in the bottom of the openings216. Then a barrier layer224may be deposited over the entire integrated circuit device200and may cover the chemical oxide layer222and the sidewalls of the openings216. The barrier layer224may be, for example, titanium nitride (TiN), tantalum nitride (TaN), or strontium titanium nitride (SrTiN), which may be deposited by, for example, atomic layer deposition (ALD). For a 7 nm to 10 nm device, the barrier layer224may range from, for example, approximately 0.5 nm to approximately 1.5 nm. The barrier layer224may assist in preventing bonds from forming between elements in the layers below the barrier layer224and the layers applied over the barrier layer224. For example, the barrier layer224may assist in preventing titanium and silicon from bonding.

As depicted inFIG. 4A, a first dielectric layer226may be applied over the barrier layer224and a second dielectric layer228may be applied over the first dielectric layer226. The first dielectric layer226may be, for example, a high K dielectric, such as, aluminum oxide (Al2O3), which may be applied by, for example, ALD. The first dielectric layer226may act as, for example, an etch stopper during contact formation. For a 7 nm to 10 nm device, the first dielectric layer226may range from, for example, approximately 1 nm to approximately 2 nm. The second dielectric layer228may be, for example, silicon dioxide (SiO2), which may be applied by, for example, chemical vapor deposition (CVD). As shown inFIG. 4B, the bottom of the openings216may include a substrate portion202, a chemical oxide layer222, a barrier layer224, a first dielectric layer226, and a second dielectric layer228.

After the dielectric layers226,228are applied, the device200may be annealed to drive oxygen from the dielectric layer228through the dielectric layer226and the barrier layer224and into the chemical oxide layer222to form a metal layer230, for example, titanium dioxide (TiO2), as shown inFIG. 4C. The anneal may be, for example, a low temperature anneal with a temperature ranging from, for example, approximately 400° C. to approximately 600° C. and more preferably with a temperature of approximately 500° C. The oxygen atoms may be driven from, for example, a SiO2dielectric layer228into the chemical oxide layer222to form the TiO2metal layer230. After the anneal the device200, as shown inFIG. 5, may include a substrate202, openings216positioned between spacers218and interlayer dielectric220, and the openings216may include a metal layer230, a barrier layer224, a first dielectric layer226, and a second dielectric layer228.

A photo resist layer232may then be applied over at least a portion of the device200, as shown inFIG. 6. The photo resist layer232may be applied over, for example, the nFET trench contact regions of the device200design. Next, etching may be performed to remove the first and second dielectric layers226,228from a first set of openings234, leaving the barrier layer224. The etching may be, for example, a diluted hafnium (Hf) etch to remove the second dielectric layer228. To remove the first dielectric layer226, the etching may be a selective etch, for example, ammonium hydroxide solution (NH4OH:H2O) or diluted tetra-methyl-ammonium hydroxide (TMAH or C4H13NO). The first set of openings234may be, for example, the pFET trench contact regions of the device200, as shown inFIG. 7.

After the first set of openings234is formed, the photo resist layer232may be removed and a first metal layer236may be applied over the device200, as shown inFIG. 8. The first metal layer236may be, for example, a p-metal, such as, molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), and the like as known by one of ordinary skill in the art. The first metal236may be applied by, for example, physical layer deposition (PVD). For a 7 nm to 10 nm device, the first metal layer236may have a thickness ranging from, for example, approximately 5 nm to approximately 10 nm.

After applying the first metal layer236, an organic planar layer238may be applied over the first set of openings234, as shown inFIG. 9. The organic planar layer238may, for example, protect the first set of openings234during formation of a second set of openings240, as shown inFIG. 10. The second set of openings240may be formed by etching the first metal layer236and the first and second dielectric layers226,228. The first metal layer236may be etched using, for example, a p-metal wet etch chemical, such as, HCl:H2O2for Mo, HCl:NHO3for Ru, HCl:H2O2for Co, HF:NHO3for Ni, and like solutions for other p-metals as known by one of ordinary skill in the art. The first and second dielectric layers226,228may be etched as discussed above with reference toFIGS. 6 and 7and which will not be discussed again here for brevity sake.

As shown inFIG. 11, after etching the first metal layer236and the first and second dielectric layers226,228, the organic planar layer238may be removed. Next, a second metal layer242may be deposited over the device200, as shown inFIG. 12. The second metal layer242may be, for example, a n-metal, such as hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), aluminum (Al), niobium (Nb), and the like as known by one of ordinary skill in the art. The second metal layer242may be applied by, for example, PVD. For a 7 nm to 10 nm device, the second metal layer242may have a thickness ranging from, for example, approximately 5 nm to approximately 10 nm.

As depicted inFIG. 13, in one embodiment, after a second metal layer242is deposited onto the device, an adhesion layer244may optionally be applied over the second metal layer242. The adhesion layer244may be, for example, titanium nitride (TiN). Next, a third metal layer246may be deposited over the device200. The third metal layer246may be, for example, a low resistivity metal, such as, tungsten (W), cobalt (Co), or another low resistivity metal known by one of ordinary skill in the art. The device200may then be planarized by, for example, chemical mechanical planarization (CMP). As shown inFIG. 14, the CMP may remove at least a portion of the third metal layer246, the adhesion layer244, the second metal layer242, and the first metal layer236to form at least one first contact248and at least one second contact250. The at least one first contact248may be, for example, a p-metal contact, and the at least one second contact250may be, for example, an n-metal contact. It is also contemplated that the n-metal contact may be formed first and then the p-metal contact could be formed, as described in greater detail above.

A portion of the intermediate circuit structure300obtained during circuit fabrication is shown inFIG. 15and may include a substrate structure302, gate structures304, at least one source region305,306, at least one drain region307,308, and at least one fin310. As shown inFIG. 15the substrate302may include a first portion312and a second portion314. The substrate structure302, gate structures304, at least one source region305,306, at least one drain region307,308, at least one fin310, first portion312, and second portion314may be of the type described above with reference to the substrate structure202, gate structures204, at least one source region205,206, at least one drain region207,208, at least one fin210, first portion212, and second portion214as described above with reference toFIGS. 2A-2B, which will not be described again here for brevity sake.

FIGS. 16-33show the two portions312,314of the integrated circuit device300during the fabrication process. The device300may have been processed through initial device processing steps in accordance with the design of the device300being fabricated, for example, gate stack formation, such as, replacement gate. As shown inFIG. 16, an interlayer dielectric layer320may be deposited over the portions312,314of the device300. In addition, a stop layer316may be deposited over the interlayer dielectric layer320. The stop layer316may be deposited by, for example, CMP. In addition, the stop layer316may be, for example, silicon nitride (SiN), silicon oxy-nitride (SiON), or another stop material as know by one of ordinary skill in the art.

Next, at least one first opening322may be etched into the stop layer316and interlayer dielectric layer320, as shown inFIG. 17. The at least one first opening322may be etched by, for example, reactive ion etching (RIE), and the at least one first opening322may be, for example, an nFET trench contact opening. A chemical oxide layer or first layer324may then be formed in the at least one first opening322. The chemical oxide layer324may be formed by, for example, wet chemicals, and may be formed on the bottom of the openings322. As shown inFIG. 18, a barrier layer326may then be applied over the entire device300including, for example, over the chemical oxide layer324, the sidewalls of the openings322, and the entire surface of the device300. The barrier layer326may be, for example, ALD titanium nitride (TiN), which may have a thickness ranging from, for example, approximately 0.5 nm to approximately 1.5 nm for a 7 nm to 10 nm device.

As depicted inFIG. 19, at least one dielectric layer, for example, a first dielectric layer328and a second dielectric layer330, may be applied over the barrier layer326. The first dielectric layer328may be, for example, ALD Al2O3, and the second dielectric layer330may be, for example, CVD SiO2, as described in greater detail above with respect to first and second dielectric layers226,228and which will not be described again here for brevity sake. After application of the first and second dielectric layers328,330, the device300may be annealed to drive oxygen from the second dielectric layer330through the first dielectric layer328and the barrier layer326and into the chemical oxide layer324to form a metal layer332, for example, titanium dioxide (TiO2), as shown inFIG. 20. The anneal may be, for example, a low temperature anneal with a temperature ranging from, for example, approximately 400° C. to approximately 600° C. and more preferably with a temperature of approximately 500° C. The oxygen atoms may be driven from, for example, a SiO2dielectric layer330into the chemical oxide layer324to form the TiO2metal layer332. After annealing the device300, as shown inFIG. 20, the at least one opening322of the device300may include a metal layer332, a barrier layer326, a first dielectric layer328, and a second dielectric layer330.

Next, etching may be performed to remove the first and second dielectric layers328,330from the at least one first opening322, leaving the barrier layer326, as shown inFIG. 21. The etching may be, for example, a diluted hafnium (Hf) etch to remove the second dielectric layer330. To remove the first dielectric layer328, the etching may be a selective etch, for example, ammonium hydroxide solution (NH4OH:H2O) or diluted tetra-methyl-ammonium hydroxide (TMAH or C4H13NO). As shown inFIG. 22, a first metal layer334may be deposited onto the device300by, for example, PVD. The first metal layer334may be, for example, a n-metal, such as, magnesium (Mg), manganese (Mn), Hf, Ti, Zr, Ta, Al, Nb, and the like as known by one of ordinary skill in the art. The first metal layer334may have a thickness of, for example, approximately 5 nm to approximately 10 nm for a 7 nm to 10 nm device.

As shown inFIG. 23, in one embodiment, an adhesion layer336may optionally be deposited over the first metal layer334and a second metal layer338may be deposited over the adhesion layer336. The adhesion layer336may be, for example, TiN, and the second metal layer338may be, for example, a low resistivity metal, such as, W, Co, or another low resistivity metal known by one of ordinary skill in the art. Next, as shown inFIG. 24, a CMP may be performed to remove at least a portion of the second metal layer338, a portion of the adhesion layer336, a portion of the first metal layer334, and a portion of the barrier layer326to form at least one first contact340. The at least one first contact340may be, for example, at least one n-metal contact.

After the at least one first contact340is formed, additional stop layer material may be applied to the stop layer316over the device300to cover the at least one first contact340, as shown inFIG. 25. Then the device300may be etched to form at least one second opening342in the stop layer316and interlayer dielectric layer320, as depicted inFIG. 26. The at least one second opening342may be etched by, for example, reactive ion etching (RIE) and the at least one second opening342may be, for example, a pFET trench contact opening. A chemical oxide layer or first layer344may then be formed in the at least one second opening342, for example, on a bottom surface, as depicted inFIG. 26. The chemical oxide layer344may be formed by using, for example, wet chemicals. As shown inFIG. 27, a barrier layer346may then be applied over the device300, as described in greater detail above with reference toFIG. 18, and which will not be described again here for brevity sake. The barrier layer346may be, for example, ALD TiN, which may have a thickness ranging from, for example, approximately 0.5 nm to approximately 1.5 nm for a 7 nm to 10 nm device.

As depicted inFIG. 28, at least one dielectric layer, for example, a first dielectric layer348and a second dielectric layer350, may be applied over the barrier layer346. Although only two dielectric layers348,350are shown in the depicted embodiments any number of dielectric layers is contemplated. The first dielectric layer348may be, for example, ALD Al2O3, and the second dielectric layer350may be, for example, CVD SiO2, as described in greater detail above with respect to first and second dielectric layers226,228,328,330, and which will not be described again here for brevity sake. After the application of the first and second dielectric layers348,350, the device300may be annealed to drive oxygen from the second dielectric layer350through the first dielectric layer348and the barrier layer346and into the chemical oxide layer344to form a metal layer352, for example, TiO2, as shown inFIG. 29. The anneal may be, for example, a low temperature anneal as described above with reference toFIG. 20and which will not be described again here for brevity sake. After annealing the device300, as shown inFIG. 29, the at least one second opening342may include a metal layer352, a barrier layer346, a first dielectric layer348, and a second dielectric layer350.

Next, etching may be performed to remove the first and second dielectric layers348,350from the at least one second opening342, down to the barrier layer346, as shown inFIG. 30. The etching may be, for example, a diluted Hf etch to remove the second dielectric layer350and a selective etch, for example, NH4OH:H2O or diluted TMAH or C4H13NO to remove the first dielectric layer348, as described in greater detail above and which will not be described again here for brevity sake. As shown inFIG. 31, a third metal layer354may be deposited onto the device300by, for example, PVD. The third metal layer354may, for example, line the at least one second opening342over the barrier layer346. The third metal layer354may be, for example, a p-metal, such as, Mo, Ru, Co, Ni, and the like as known by one of ordinary skill in the art. The third metal layer354may have a thickness of, for example, approximately 5 nm to approximately 10 nm for a 7 nm to 10 nm device.

As depicted inFIG. 32, in one embodiment, an adhesion layer356may optionally be deposited over the third metal layer354and a fourth metal layer358may be deposited over the adhesion layer356. The adhesion layer356may be, for example, TiN, and the fourth metal layer358may be, for example, a low resistivity metal, such as, W, Co, or another low resistivity metal known by one of ordinary skill in the art. Next, as shown inFIG. 33, a CMP may be performed to remove at least a portion of the fourth metal layer358, the adhesion layer356, the third metal layer354, and the barrier layer346to form at least one second contact360. The at least one second contact360may be, for example, at least one p-metal contact. After the contact formation process is complete, the device300may include at least one first contact340and at least one second contact360. As described in greater detail above, the at least one first contact340may be, for example, an n-metal contact, and the at least one second contact360may be, for example, a p-metal contact.

FIGS. 34-50show an alternative fabrication process or method of the integrated circuit device300including two portions312,314. As described in greater detail above, the device300may have been processed through initial device processing steps in accordance with the design of the device300being fabricated, for example, gate stack formation, such as, replacement gate. The fabrication process shown inFIGS. 34-50begins with the portions312,314ofFIG. 16, described in greater detail above and which will not be described again here for brevity sake.FIG. 34shows at least one first opening322etched into the stop layer316and interlayer dielectric layer320of the first portion312. The at least one first opening322may be etched by, for example, RIE, and the at least one first opening322may be, for example, a pFET trench contact opening. A chemical oxide layer324may then be formed in the at least one first opening322, as described in greater detail above with reference toFIGS. 17 and 26, and which will not be described again here for brevity sake.

As depicted inFIG. 35, a barrier layer326may then be applied over the device300. The barrier layer326is as described above with reference toFIG. 18and will not be described again here for brevity sake.FIG. 36shows at least one dielectric layer, for example, a first dielectric layer328and a second dielectric layer330, applied over the barrier layer326. The first dielectric layer328may be, for example, ALD Al2O3, and the second dielectric layer330may be, for example, CVD SiO2, as described in greater detail above with respect toFIGS. 19 and 28, and which will not be described again here for brevity sake.

After application of the first and second dielectric layers328,330, the device300may be annealed to drive oxygen from the second dielectric layer330through the first dielectric layer328and the barrier layer326and into the chemical oxide layer324to form a metal layer332, for example, TiO2, as shown inFIG. 37. The anneal may be as described above with reference toFIGS. 20 and 29, and which will not be described again here for brevity sake. After annealing the device300, the at least one opening322may include a metal layer332, a barrier layer326, a first dielectric layer328, and a second dielectric layer330.

Next, etching may be performed to remove the first and second dielectric layers328,330from the at least one first opening322, leaving the barrier layer326, as shown inFIG. 38. The etching may include, for example, diluted Hf etching to remove the second dielectric layer330and selective etching, such as, NH4OH:H2O or diluted TMAH or C4H13NO to remove the first dielectric layer328, as described in greater detail above. As shown inFIG. 39, a first metal layer334may be deposited onto the device300by, for example, PVD. The first metal layer334may be, for example, a p-metal, such as, Mo, Ru, Co, Ni, and the like as known by one of ordinary skill in the art. The first metal layer334may have a thickness of, for example, approximately 5 nm to approximately 10 nm for a 7 nm to 10 nm device.

As shown inFIG. 40, in one embodiment, an adhesion layer336may optionally be deposited over the first metal layer334and a second metal layer338may be deposited over the adhesion layer336. The adhesion layer336and the second metal layer338may be of the type described above with reference toFIGS. 23 and 32. Next, as shown inFIG. 41, a CMP may be performed to remove at least a portion of the second metal layer338, a portion of the adhesion layer336, a portion of the first metal layer334, and a portion of the barrier layer326to form at least one first contact340. The at least one first contact340may be, for example, at least one p-metal contact.

After the at least one first contact340is formed, additional stop layer material may be applied to the stop layer316over the device300to cover the at least one first contact340, as shown inFIG. 42. Then the device300may be etched to form at least one second opening342in the stop layer316and interlayer dielectric layer320of the second portion314, as depicted inFIG. 43. The at least one second opening342may be etched by, for example, RIE and the at least one second opening342may be, for example, an nFET trench contact opening. A chemical oxide layer344may then be formed in the at least one second opening342, for example, on a bottom surface of the openings342, as depicted inFIG. 43. The chemical oxide layer344may be formed by using, for example, wet chemicals, as described in greater detail above with reference toFIGS. 17 and 26. As shown inFIG. 44, a barrier layer346may then be applied over the device300, as described above with reference toFIG. 18and which will not be described again here for brevity sake. The barrier layer346may be, for example, ALD TiN, which may have a thickness ranging from, for example, approximately 0.5 nm to approximately 1.5 nm for a 7 nm to 10 nm device.

As depicted inFIG. 45, at least one dielectric layer, for example, a first dielectric layer348and a second dielectric layer350, may be applied over the barrier layer346. Although only two dielectric layers348,350are shown in the depicted embodiments any number of dielectric layers are contemplated. The first dielectric layer348may be, for example, ALD Al2O3, and the second dielectric layer350may be, for example, CVD SiO2, as described in greater detail above with respect toFIGS. 19 and 28, and which will not be described again here for brevity sake. After the application of the first and second dielectric layers348,350, the device300may be annealed to drive oxygen from the second dielectric layer350through the first dielectric layer348and the barrier layer346and into the chemical oxide layer344to form a metal layer352, for example, TiO2, as shown inFIG. 46. The anneal may be, for example, a low temperature anneal as described above with reference toFIG. 20and which will not be described again here for brevity sake. After annealing the device300, as shown inFIG. 46, the at least one second opening342may include a metal layer352, a barrier layer346, a first dielectric layer348, and a second dielectric layer350.

Next, etching may be performed to remove the first and second dielectric layers348,350from the at least one second opening342, down to the barrier layer346, as shown inFIG. 47. The etching may be, for example, a diluted Hf etch to remove the second dielectric layer350and a selective etch, for example, NH4OH:H2O or diluted TMAH or C4H13NO to remove the first dielectric layer348, as described in greater detail above and which will not be described again here for brevity sake. As shown inFIG. 48, a third metal layer354may be deposited onto the device300by, for example, PVD. The third metal layer354may, for example, line the at least one second opening342over the barrier layer346. The third metal layer354may be, for example, an n-metal, such as, Mg, Mn, Hf, Ti, Zr, Ta, Al, Nb, and the like as known by one of ordinary skill in the art. The third metal layer354may have a thickness of, for example, approximately 5 nm to approximately 10 nm for a 7 nm to 10 nm device.

As depicted inFIG. 49, in one embodiment, an adhesion layer356may optionally be deposited over the third metal layer354and a fourth metal layer358may be deposited over the adhesion layer356. The adhesion layer356may be, for example, TiN, and the fourth metal layer358may be, for example, a low resistivity metal, such as, W, Co, or another low resistivity metal known by one of ordinary skill in the art. Next, as shown inFIG. 50, a CMP may be performed to remove at least a portion of the fourth metal layer358, a portion of the adhesion layer356, a portion of the third metal layer354, and a portion of the barrier layer346to form at least one second contact360. The at least one second contact360may be, for example, at least one n-metal contact. After the contact formation process is complete, the device300may include at least one first contact340and at least one second contact360. As described in greater detail above, the at least one first contact340may be, for example, a p-metal contact, and the at least one second contact360may be, for example, a n-metal contact.

Although only described with examples of 7 nm to 10 nm devices, the above noted fabrications methods and processes may also be used with other size integrated circuit devices. In addition, certain deposition and etching processes are described in the example embodiments, alternative deposition and etching processes as known by one of ordinary skill in the art to obtain the same resultant structure are also contemplated and may replace the above described deposition and etching processes.