PERFORMING SIMULATIONS USING MACHINE LEARNING

To assist a machine learning environment in modelling a complex physical simulation (such as a numerical simulation or physics simulation), a correlation between input coordinates is determined. For example, a discrete solution (e.g., the correlation between the plurality of input coordinates) may be obtained from a non-discrete (e.g., continuous) physics space by performing a conversion from the physics space to a grid space. This correlation is input along with the coordinates into a machine learning environment to obtain results from the simulation. As a result, instead of implementing resource and power-intensive simulations to solve these computation problems, a machine learning environment implemented using less power and computing resources may solve these computation problems in a faster and more efficient manner.

FIELD OF THE INVENTION

The present invention relates to physical systems modelling, and more particularly to modelling complex physical systems utilizing a machine learning environment.

BACKGROUND

The modelling of physical systems through simulations (such as numerical simulations, physics simulations, etc.) has enabled significant advancements in engineering and scientific discovery. However, as the complexity of these simulations increases, so does a required amount of computational hardware resources, power, and time to implement them.

To help address this, machine learning has been applied to the domain of physical system modelling by approximating traditional simulations with faster, less resource-intensive machine learning implementations. However, current machine learning approaches can only address physical systems with low dimensionality and time-independent physics, and systems with high dimensionality and time dependence still require traditional (non-ML) simulations.

There is therefore a need to improve the computational abilities of machine learning implementations so that they may solve complex (e.g., high-dimensionality, time-dependent) computation problems instead of using traditional simulations.

DETAILED DESCRIPTION

To assist a machine learning environment in modelling a complex physical simulation (such as a numerical simulation or physics simulation), a correlation between input coordinates is determined. For example, a discrete solution (e.g., the correlation between the plurality of input coordinates) may be obtained from a non-discrete (e.g., continuous) physics space by performing a conversion from the physics space to a grid space. This correlation is input along with the coordinates into a machine learning environment to obtain results from the simulation. As a result, instead of implementing resource and power-intensive simulations to solve these computation problems, a machine learning environment implemented using less power and computing resources may solve these computation problems in a faster and more efficient manner.

FIG.1illustrates a flowchart of a method100for performing simulations using machine learning, in accordance with an embodiment. Although method100is described in the context of a processing unit, the method100may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method100may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processing element. Furthermore, persons of ordinary skill in the art will understand that any system that performs method100is within the scope and spirit of embodiments of the present invention.

As shown in operation102, a correlation between a plurality of input coordinates is determined. In one embodiment, the plurality of input coordinates may be associated with a simulation. For example, the plurality of input coordinates may include position information within the simulation (e.g., a physics simulation, etc.). In another example, the plurality of input coordinates may be two-dimensional. For instance, the plurality of input coordinates may include an X value indicative of a first dimension, a Y value indicative of a second dimension different from the first dimension, etc. In another embodiment, a physics simulation may include a mathematical model having variables that define a state of a system at a predetermined time, where each variable within the model represents a position or velocity of some part of the system.

Additionally, in one embodiment, the correlation may be determined by querying the input coordinates within a physics space. For example, the physics space may include a multi-resolution latent context grid. In another embodiment, the correlation may be determined by performing interpolation within the physics space. For example, queried points (e.g., the input coordinates) are interpolated from neighboring points within the multi-resolution latent context grid. In this way, a discrete solution (e.g., the correlation and the plurality of input coordinates) may be obtained from a non-discrete (e.g., continuous) physics space by performing a conversion from the physics space to a grid space. In another example, the correlation may include an interpolated context vector.

Further, in one embodiment, the physics space may be created utilizing a machine learning environment. For example, the machine learning environment may include a first machine learning environment that performs latent context generation. In another example, the first machine learning environment may be different from a second machine learning environment that takes the correlation and input coordinates as input and outputs a result.

Further still, in one embodiment, the machine learning environment may take an initial condition (IC) and a boundary condition (BC) as inputs. For example, the initial condition may include a first timestep (at time t=0). In another example, the initial condition may include a first state at the first timestep (t=0). In yet another example, the boundary condition may include boundary areas within a predetermined space (e.g., in x, y coordinates).

Also, in one embodiment, the machine learning environment may include a latent grid network. In another embodiment, the latent grid network may perform one or more operations in a spatial domain, and one or more operations in a frequency domain. In yet another embodiment, within the spatial domain, the machine learning environment may perform recurrent neural network (RNN) propagation on a single initial condition input to create additional states. For example, the initial condition may be input into a convolutional gated recurrent unit (GRU). In another example, the GRU may create one or more states at subsequent timesteps (e.g., a second timestep at time t=1, a third timestep at time t=2, etc.).

In addition, in one embodiment, within the spatial domain, a linear transformation may be performed on these additional states, utilizing the boundary condition. For example, additional variables (e.g., W and B variables) may be created from the boundary condition input utilizing convolutional layers of the machine learning environment. In another example, the boundary condition input may be transformed into the additional variables, utilizing the machine learning environment. In yet another example, these variables may be used to perform a linear transformation on each of the additional states. In still another embodiment, this linear transformation may bound each of the additional initial conditions to fit within the boundary condition.

Furthermore, in one embodiment, the spatial domain results may include IC and BC values for each of a plurality of timesteps. In another embodiment, within the frequency domain, the machine learning environment may transform IC and BC input utilizing a discrete cosine transform (DCT). For example, the DCT may convert the IC and BC input from the spatial domain to the frequency domain. In another example, both the IC and BC input may be divided into patches (e.g., spatial patches). In yet another embodiment, a DCT may be applied to these patches to obtain DCT patches. In yet another example, the DCT patches may be reordered and truncated to remove redundant/unnecessary patches. In still another example, the transformed input may include the reordered/truncated DCT patches.

Further still, in one embodiment, within the frequency domain, recurrent neural network (RNN) propagation may be performed on the transformed input to create additional states, and a linear transformation may be performed on these additional states, utilizing the transformed boundary condition. For example, the RNN propagation may be the same as that performed within the spatial domain. In another embodiment, an inverse discrete cosine transform (IDCT) may be applied to the results of the RNN propagation. This transform may convert the results from the frequency domain back to the spatial domain.

Also, in one embodiment, the frequency domain results may include IC and BC values for each of a plurality of timesteps. In another embodiment, the spatial domain results and the frequency domain results may then be combined. In yet another embodiment, additional layers of the machine learning environment (e.g., convoluted neural network (CNN) layers, etc.) may decode the combined domain results. In still another embodiment, results of the decoding may be upsampled by additional layers of the machine learning environment to determine the physics space (e.g., the multi-resolution latent context grid). For example, the upsampling may be performed over multiple stages to create the multiple resolutions for the multi-resolution latent context grid.

Additionally, as shown in operation104, the plurality of input coordinates as well as the correlation are input into a machine learning environment to obtain a result. In one embodiment, the plurality of input coordinates and the correlation may be input into a trained machine learning environment (e.g., a neural network, etc.). In another embodiment, the machine learning environment may be trained utilizing one or more physics model loss functions.

For example, the loss functions may be constructed based on a predetermined physics model. In another example, the loss functions may be minimized based on partial differential equations (PDEs), ICs, and BCs. In yet another example, weights within the machine learning environment may be learned utilizing the one or more physics model loss functions.

Further, in one embodiment, the trained machine learning environment may take the plurality of input coordinates and the correlation as input and may output a solution as the result. For example, the solution may include one or more values (e.g., pressure, velocity, temperature, etc.) indicated within the physics model being implemented via the machine learning environment.

In this way, results may be determined for complex computation problems (e.g., multi-variable time-dependent physics problems, etc.) using a machine learning environment instead of one or more complex hardware-implemented simulations. Determining the correlation between the input coordinates (e.g., according to time, etc.) may allow for knowledge about dimensionality and interrelationships between the input coordinates to be considered as input by the machine learning environment, which may simplify the analysis being performed by the machine learning environment, thereby enabling the machine learning environment to understand and solve complex computation problems. As a result, instead of implementing resource and power-intensive simulations to solve these computation problems, a machine learning environment implemented using less power and computing resources may solve these computation problems in a faster and more efficient manner, which may improve a performance of computing hardware tasked with solving such computation problems.

In yet another embodiment, the aforementioned operations may be performed utilizing a parallel processing unit (PPU) such as the PPU200illustrated inFIG.2.

Parallel Processing Architecture

FIG.2illustrates a parallel processing unit (PPU)200, in accordance with an embodiment. In an embodiment, the PPU200is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU200is a latency hiding architecture designed to process many threads in parallel. A thread (i.e., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU200. In an embodiment, the PPU200is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU200may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more PPUs200may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU200may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown inFIG.2, the PPU200includes an Input/Output (I/O) unit205, a front end unit215, a scheduler unit220, a work distribution unit225, a hub230, a crossbar (Xbar)270, one or more general processing clusters (GPCs)250, and one or more partition units280. The PPU200may be connected to a host processor or other PPUs200via one or more high-speed NVLink210interconnect. The PPU200may be connected to a host processor or other peripheral devices via an interconnect202. The PPU200may also be connected to a local memory comprising a number of memory devices204. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device.

The NVLink210interconnect enables systems to scale and include one or more PPUs200combined with one or more CPUs, supports cache coherence between the PPUs200and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink210through the hub230to/from other units of the PPU200such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink210is described in more detail in conjunction withFIG.4B.

The I/O unit205is configured to transmit and receive communications (i.e., commands, data, etc.) from a host processor (not shown) over the interconnect202. The I/O unit205may communicate with the host processor directly via the interconnect202or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit205may communicate with one or more other processors, such as one or more the PPUs200via the interconnect202. In an embodiment, the I/O unit205implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect202is a PCIe bus. In alternative embodiments, the I/O unit205may implement other types of well-known interfaces for communicating with external devices.

The I/O unit205decodes packets received via the interconnect202. In an embodiment, the packets represent commands configured to cause the PPU200to perform various operations. The I/O unit205transmits the decoded commands to various other units of the PPU200as the commands may specify. For example, some commands may be transmitted to the front end unit215. Other commands may be transmitted to the hub230or other units of the PPU200such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit205is configured to route communications between and among the various logical units of the PPU200.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU200for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (i.e., read/write) by both the host processor and the PPU200. For example, the I/O unit205may be configured to access the buffer in a system memory connected to the interconnect202via memory requests transmitted over the interconnect202. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU200. The front end unit215receives pointers to one or more command streams. The front end unit215manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU200.

The front end unit215is coupled to a scheduler unit220that configures the various GPCs250to process tasks defined by the one or more streams. The scheduler unit220is configured to track state information related to the various tasks managed by the scheduler unit220. The state may indicate which GPC250a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit220manages the execution of a plurality of tasks on the one or more GPCs250.

The scheduler unit220is coupled to a work distribution unit225that is configured to dispatch tasks for execution on the GPCs250. The work distribution unit225may track a number of scheduled tasks received from the scheduler unit220. In an embodiment, the work distribution unit225manages a pending task pool and an active task pool for each of the GPCs250. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC250. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs250. As a GPC250finishes the execution of a task, that task is evicted from the active task pool for the GPC250and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC250. If an active task has been idle on the GPC250, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC250and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC250.

The work distribution unit225communicates with the one or more GPCs250via XBar270. The XBar270is an interconnect network that couples many of the units of the PPU200to other units of the PPU200. For example, the XBar270may be configured to couple the work distribution unit225to a particular GPC250. Although not shown explicitly, one or more other units of the PPU200may also be connected to the XBar270via the hub230.

The tasks are managed by the scheduler unit220and dispatched to a GPC250by the work distribution unit225. The GPC250is configured to process the task and generate results. The results may be consumed by other tasks within the GPC250, routed to a different GPC250via the XBar270, or stored in the memory204. The results can be written to the memory204via the partition units280, which implement a memory interface for reading and writing data to/from the memory204. The results can be transmitted to another PPU200or CPU via the NVLink210. In an embodiment, the PPU200includes a number U of partition units280that is equal to the number of separate and distinct memory devices204coupled to the PPU200. A partition unit280will be described in more detail below in conjunction withFIG.3B.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU200. In an embodiment, multiple compute applications are simultaneously executed by the PPU200and the PPU200provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (i.e., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU200. The driver kernel outputs tasks to one or more streams being processed by the PPU200. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction withFIG.4A.

FIG.3Aillustrates a GPC250of the PPU200ofFIG.2, in accordance with an embodiment. As shown inFIG.3A, each GPC250includes a number of hardware units for processing tasks. In an embodiment, each GPC250includes a pipeline manager310, a pre-raster operations unit (PROP)315, a raster engine325, a work distribution crossbar (WDX)380, a memory management unit (MMU)390, and one or more Data Processing Clusters (DPCs)320. It will be appreciated that the GPC250ofFIG.3Amay include other hardware units in lieu of or in addition to the units shown inFIG.3A.

In an embodiment, the operation of the GPC250is controlled by the pipeline manager310. The pipeline manager310manages the configuration of the one or more DPCs320for processing tasks allocated to the GPC250. In an embodiment, the pipeline manager310may configure at least one of the one or more DPCs320to implement at least a portion of a graphics rendering pipeline. For example, a DPC320may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM)340. The pipeline manager310may also be configured to route packets received from the work distribution unit225to the appropriate logical units within the GPC250. For example, some packets may be routed to fixed function hardware units in the PROP315and/or raster engine325while other packets may be routed to the DPCs320for processing by the primitive engine335or the SM340. In an embodiment, the pipeline manager310may configure at least one of the one or more DPCs320to implement a neural network model and/or a computing pipeline.

The PROP unit315is configured to route data generated by the raster engine325and the DPCs320to a Raster Operations (ROP) unit, described in more detail in conjunction withFIG.3B. The PROP unit315may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

Each DPC320included in the GPC250includes an M-Pipe Controller (MPC)330, a primitive engine335, and one or more SMs340. The MPC330controls the operation of the DPC320, routing packets received from the pipeline manager310to the appropriate units in the DPC320. For example, packets associated with a vertex may be routed to the primitive engine335, which is configured to fetch vertex attributes associated with the vertex from the memory204. In contrast, packets associated with a shader program may be transmitted to the SM340.

The SM340comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM340is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the SM340implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (i.e., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM340implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM340will be described in more detail below in conjunction withFIG.4A.

The MMU390provides an interface between the GPC250and the partition unit280. The MMU390may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU390provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory204.

FIG.3Billustrates a memory partition unit280of the PPU200ofFIG.2, in accordance with an embodiment. As shown inFIG.3B, the memory partition unit280includes a Raster Operations (ROP) unit350, a level two (L2) cache360, and a memory interface370. The memory interface370is coupled to the memory204. Memory interface370may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU200incorporates U memory interfaces370, one memory interface370per pair of partition units280, where each pair of partition units280is connected to a corresponding memory device204. For example, PPU200may be connected to up to Y memory devices204, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage.

In an embodiment, the memory interface370implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU200, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory204supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs200process very large datasets and/or run applications for extended periods.

In an embodiment, the PPU200implements a multi-level memory hierarchy. In an embodiment, the memory partition unit280supports a unified memory to provide a single unified virtual address space for CPU and PPU200memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU200to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the PPU200that is accessing the pages more frequently. In an embodiment, the NVLink210supports address translation services allowing the PPU200to directly access a CPU's page tables and providing full access to CPU memory by the PPU200.

In an embodiment, copy engines transfer data between multiple PPUs200or between PPUs200and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit280can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.

Data from the memory204or other system memory may be fetched by the memory partition unit280and stored in the L2 cache360, which is located on-chip and is shared between the various GPCs250. As shown, each memory partition unit280includes a portion of the L2 cache360associated with a corresponding memory device204. Lower level caches may then be implemented in various units within the GPCs250. For example, each of the SMs340may implement a level one (L1) cache. The L1 cache is private memory that is dedicated to a particular SM340. Data from the L2 cache360may be fetched and stored in each of the L1 caches for processing in the functional units of the SMs340. The L2 cache360is coupled to the memory interface370and the XBar270.

The ROP unit350performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The ROP unit350also implements depth testing in conjunction with the raster engine325, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine325. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ROP unit350updates the depth buffer and transmits a result of the depth test to the raster engine325. It will be appreciated that the number of partition units280may be different than the number of GPCs250and, therefore, each ROP unit350may be coupled to each of the GPCs250. The ROP unit350tracks packets received from the different GPCs250and determines which GPC250that a result generated by the ROP unit350is routed to through the Xbar270. Although the ROP unit350is included within the memory partition unit280inFIG.3B, in other embodiment, the ROP unit350may be outside of the memory partition unit280. For example, the ROP unit350may reside in the GPC250or another unit.

FIG.4Aillustrates the streaming multi-processor340ofFIG.3A, in accordance with an embodiment. As shown inFIG.4A, the SM340includes an instruction cache405, one or more scheduler units410(K), a register file420, one or more processing cores450, one or more special function units (SFUs)452, one or more load/store units (LSUs)454, an interconnect network480, a shared memory/L1 cache470.

As described above, the work distribution unit225dispatches tasks for execution on the GPCs250of the PPU200. The tasks are allocated to a particular DPC320within a GPC250and, if the task is associated with a shader program, the task may be allocated to an SM340. The scheduler unit410(K) receives the tasks from the work distribution unit225and manages instruction scheduling for one or more thread blocks assigned to the SM340. The scheduler unit410(K) schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit410(K) may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (i.e., cores450, SFUs452, and LSUs454) during each clock cycle.

A dispatch unit415is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit410(K) includes two dispatch units415that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit410(K) may include a single dispatch unit415or additional dispatch units415.

Each SM340includes a register file420that provides a set of registers for the functional units of the SM340. In an embodiment, the register file420is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file420. In another embodiment, the register file420is divided between the different warps being executed by the SM340. The register file420provides temporary storage for operands connected to the data paths of the functional units.

Each SM340comprises L processing cores450. In an embodiment, the SM340includes a large number (e.g., 128, etc.) of distinct processing cores450. Each core450may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores450include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the cores450. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each SM340also comprises M SFUs452that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs452may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs452may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory204and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM340. In an embodiment, the texture maps are stored in the shared memory/L1 cache370. The texture units implement texture operations such as filtering operations using mip-maps (i.e., texture maps of varying levels of detail). In an embodiment, each SM240includes two texture units.

Each SM340also comprises N LSUs454that implement load and store operations between the shared memory/L1 cache470and the register file420. Each SM340includes an interconnect network480that connects each of the functional units to the register file420and the LSU454to the register file420, shared memory/L1 cache470. In an embodiment, the interconnect network480is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file420and connect the LSUs454to the register file and memory locations in shared memory/L1 cache470.

The shared memory/L1 cache470is an array of on-chip memory that allows for data storage and communication between the SM340and the primitive engine335and between threads in the SM340. In an embodiment, the shared memory/L1 cache470comprises 128 KB of storage capacity and is in the path from the SM340to the partition unit280. The shared memory/L1 cache470can be used to cache reads and writes. One or more of the shared memory/L1 cache470, L2 cache360, and memory204are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache470enables the shared memory/L1 cache470to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown inFIG.2, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit225assigns and distributes blocks of threads directly to the DPCs320. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM340to execute the program and perform calculations, shared memory/L1 cache470to communicate between threads, and the LSU454to read and write global memory through the shared memory/L1 cache470and the memory partition unit280. When configured for general purpose parallel computation, the SM340can also write commands that the scheduler unit220can use to launch new work on the DPCs320.

The PPU200may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU200is embodied on a single semiconductor substrate. In another embodiment, the PPU200is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs200, the memory204, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the PPU200may be included on a graphics card that includes one or more memory devices204. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU200may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.

Exemplary Computing System

FIG.4Bis a conceptual diagram of a processing system400implemented using the PPU200ofFIG.2, in accordance with an embodiment. The exemplary system465may be configured to implement the method100shown inFIG.1. The processing system400includes a CPU430, switch410, and multiple PPUs200each and respective memories204. The NVLink210provides high-speed communication links between each of the PPUs200. Although a particular number of NVLink210and interconnect202connections are illustrated inFIG.4B, the number of connections to each PPU200and the CPU430may vary. The switch410interfaces between the interconnect202and the CPU430. The PPUs200, memories204, and NVLinks210may be situated on a single semiconductor platform to form a parallel processing module425. In an embodiment, the switch410supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink210provides one or more high-speed communication links between each of the PPUs200and the CPU430and the switch410interfaces between the interconnect202and each of the PPUs200. The PPUs200, memories204, and interconnect202may be situated on a single semiconductor platform to form a parallel processing module425. In yet another embodiment (not shown), the interconnect202provides one or more communication links between each of the PPUs200and the CPU430and the switch410interfaces between each of the PPUs200using the NVLink210to provide one or more high-speed communication links between the PPUs200. In another embodiment (not shown), the NVLink210provides one or more high-speed communication links between the PPUs200and the CPU430through the switch410. In yet another embodiment (not shown), the interconnect202provides one or more communication links between each of the PPUs200directly. One or more of the NVLink210high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink210.

In an embodiment, the signaling rate of each NVLink210is 20 to 25 Gigabits/second and each PPU200includes six NVLink210interfaces (as shown inFIG.4B, five NVLink210interfaces are included for each PPU200). Each NVLink210provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLinks210can be used exclusively for PPU-to-PPU communication as shown inFIG.4B, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU430also includes one or more NVLink210interfaces.

In an embodiment, the NVLink210allows direct load/store/atomic access from the CPU430to each PPU's200memory204. In an embodiment, the NVLink210supports coherency operations, allowing data read from the memories204to be stored in the cache hierarchy of the CPU430, reducing cache access latency for the CPU430. In an embodiment, the NVLink210includes support for Address Translation Services (ATS), allowing the PPU200to directly access page tables within the CPU430. One or more of the NVLinks210may also be configured to operate in a low-power mode.

FIG.4Cillustrates an exemplary system465in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system465may be configured to implement the method100shown inFIG.1.

As shown, a system465is provided including at least one central processing unit430that is connected to a communication bus475. The communication bus475may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system465also includes a main memory440. Control logic (software) and data are stored in the main memory440which may take the form of random access memory (RAM).

The system465also includes input devices460, the parallel processing system425, and display devices445, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices460, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system465. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

Further, the system465may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface435for communication purposes.

Computer programs, or computer control logic algorithms, may be stored in the main memory440and/or the secondary storage. Such computer programs, when executed, enable the system465to perform various functions. The memory440, the storage, and/or any other storage are possible examples of computer-readable media.

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system465may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

Machine Learning

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU200is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications.

Exemplary Simulation Environment

FIG.5illustrates a simulation solution environment500, according to one exemplary embodiment. As shown, a plurality of input coordinates502are queried within a physics space504. In one embodiment, the input coordinates may be associated with a simulation. In another embodiment, the physics space504may include a multi-resolution latent context grid created utilizing a machine learning environment.

Additionally, in response to the querying of the input coordinates502, the physics space504returns a correlation506between the plurality of input coordinates502. In one embodiment, the correlation may be determined by performing interpolation within the physics space504.

Further, both the input coordinates502and correlation506are provided as input into a machine learning environment508. In one embodiment, the machine learning environment508may be trained utilizing one or more physics model loss functions. In response to the input, the machine learning environment508produces a result510(e.g., a solution to the simulation at the plurality of input coordinates502, etc.).

In this way, the machine learning environment508may be used to implement a simulation (instead of performing a complete implementation of the simulation itself). As a complete implementation of the simulation utilized more power and hardware computing resources than the machine learning implementation, an amount of power and computing resources necessary to implement the simulation may be reduced.

Physics Space Creation Environment

FIG.6illustrates a machine learning environment600for creating a physics space, according to one exemplary embodiment. As shown, an initial condition (IC) input602and a boundary condition (BC) input604are sent to both a spatial domain606and a frequency domain608. In one embodiment, the machine learning environment600may include one or more convolutional neural networks (CNNs) that take the IC input602, BC input604, an IC DCT610, and a BC DCT612and return extracted low-resolution features.

Within the spatial domain606, a machine learning environment may perform recurrent neural network (RNN) propagation on the initial condition input602to create additional states. A linear transformation may be performed on these additional states, utilizing the boundary condition input604. Results of this transformation may include IC and BC values for each of a plurality of timesteps.

The IC input602and the BC input604may be transformed utilizing respective discrete cosine transforms (DCTs)610and612. The transformed input may then be sent to the frequency domain608, where a machine learning environment may perform RNN propagation on the transformed input to create additional initial conditions, and a linear transformation may be performed on these additional initial conditions, utilizing the transformed boundary condition input, to obtain IC and BC values for each of a plurality of timesteps in the frequency domain608. An inverse DCT transform614may then be applied to these IC and BC values in the frequency domain to convert the values back to the spatial domain.

Further, a summation module616may combine results of the spatial domain606and the frequency domain608, and these combined results may be decoded and upsampled to obtain a physics space618(e.g., a multi-resolution latent context grid).

In this way, a physics space618may be created that may be queried to obtain a correlation between a plurality of input coordinates. It should be noted that the machine learning environment600may include, but is not limited to, any combination of hardware and/or software that is or is not part of the aforementioned non-transitory memory, instructions, hardware processors, and/or devices, etc.

Physics Informed RNN-DCT Networks for Time-Dependent Partial Differential Equations

Physics-informed neural networks allow models to be trained by physical laws described by general nonlinear partial differential equations. However, traditional architectures struggle to solve more challenging time-dependent problems. In one embodiment, a physics-informed framework is provided for solving time-dependent partial differential equations. This framework utilizes discrete cosine transforms to encode spatial frequencies and recurrent neural networks to process the time evolution, achieving improved performance relative to other physics-informed baseline models.

Numerical simulations have become an indispensable tool for modeling physical systems, which in turn drive advancements in engineering and scientific discovery. However, as the physical complexity or spatio-temporal resolution of a simulation increases, the computational resources and run times required to solve the governing partial differential equations (PDEs) often grow drastically.

Machine learning approaches may be applied to the domain of physical simulation to ameliorate these issues by approximating traditional solvers with faster, less resource-intensive ones. These methods may include data-driven supervision or physics-informed neural networks (PINNs). PINN-based solvers parameterize the solution function directly as a neural network. This is typically done by passing a set of query points through a feed-forward fully-connected neural network (or multilayer perceptrons (MLPs)) and minimizing a loss function based on the governing PDEs, initial conditions (ICs) and boundary conditions (BCs). This allows the simulation to be constrained by physics alone and does not require any training data.

However, the accuracy of traditional PINN-based approaches is limited to problems in low dimensions and with simpler time-independent physics. Although PINNs provide a well-principled machine learning approach that promises to revolutionize numerical simulations, their current constraints to problems with simple geometries and short times severely limits their real-world impact. These shortcomings are addressed by introducing a design that improves the simulation accuracy and efficiency of PINN solvers on more challenging problems, particularly in the regime of long time evolution where current PINNs severely struggle.

Exemplary contributions are as follows: (1) A new approach is provided for generating a grid of latent context vectors to condition the spatio-temporal query points entering the MLP. This method requires no additional data and enables PINNs to learn complex time-dependent physics problems. (2) This approach is the first to directly address space-time-dependent physics end-to-end in PINNs with RNNs.

Unlike previous approaches, the current model does not need a separate method to handle the time dimension. This is achieved by utilizing convolutional gated recurrent units (ConvGRUs) for learning the spatio-temporal dynamics of simulations. (3) The spatial and frequency domains may be separated, which may increase flexibility for the network to learn more diverse physical problems. (4) This model demonstrates improved accuracy and performance when compared to earlier implementations.

In one embodiment, a new model is provided that enables PINN-based neural solvers to learn temporal dynamics in both the spatial and frequency domains. Using no additional data, this architecture may generate a latent context grid that efficiently represents more challenging spatio-temporal physical problems. The architecture includes latent context generation, decoding, and physics-informing.

Latent Grid Network

In one embodiment, a latent grid network may generate context grids which efficiently represent the entire spatio-temporal domain of a physical problem without the need for additional data.

This network may require two inputs for the problem-specific constraints: ICs and BCs. The ICs are defined as u0=u(x1, . . . , N; t=0) for each PDE solution function u over N spatial dimensions. The BCs are defined based on the geometry of the problem for each spatial dimension. An additional spatial weighting by signed distance functions (SDFs) can also be applied to avoid discontinuities at, e.g., physical boundaries, but may not be necessary for, e.g., periodic BCs. Each tensor undergoes an encoding step in either the frequency or spatial domain.

After compression, the representations enter the RNN propagation stage, in which the BCs are split into an additive (Bbc) and multiplicative (Wbc) components and combined with an IC-informed state matrix (Ht). The final output at each timestep is computed as St=WbcHt+Bbc. This implementation offers flexibility and efficiency in learning the dynamics of compressed simulations.

To predict the simulation state at each successive timestep, the previous hidden state Ht−1is passed through a convolutional GRU (ConvGRU) along with the previous output St−1; for timestep 0, the initial state H0is set to zero and ICs are used as inputs. This occurs in a recurrent manner until the final time T. Thus, for each timestep, the RNN propagation stage outputs Stwhich is then sent to a decoding step corresponding to the original frequency or spatial encoding:

The RNN propagation stage is duplicated across two branches: frequency and spatial. The frequency branch transforms the spatial inputs to frequencies via the discrete cosine transform (DCTs). When implementing a patch-wise DCT encoding step, first, the ICs and BCs are separately split into spatial patches of size p×p. DCTs are performed on each patch to yield the corresponding p×p frequency coefficient array. The tensor is then reshaped such that the same coefficient across all patches forms each channel, and the channels are reordered by increasing coefficient (i.e., decreasing energy). After the reordering, the channels are truncated by n %, so the lowest n % of frequency coefficients (largest energies) are kept. This outputs highly compressed representations for the ICs and BCs, which are used as inputs for an RNN propagation branch that occurs completely in the frequency domain.

The spatial branch may include a ResNet architecture, in which the ICs and BCs each pass through separate convolutional encoders consisting of sets of convolutional blocks with residual connections. The inputs are downsampled with strided convolutions before entering the RNN propagation stage in the spatial domain.

After RNN propagation, the outputs are combined to form the latent grid. In the frequency branch, the output state at each timestep from the RNN is converted back into the spatial domain. This is done by reshaping the frequencies from coefficients to patches, performing IDCTs, and then merging the patches to reconstruct the spatial domain. The output of the frequency branch is denoted as Otf.

The representation in the spatial domain Otsis then added with learnable weights Wto. Thus, the final output is computed as:

These combined outputs Otfor each timestep are used to form the spatio-temporal latent context grids. Finally, grids at multiple resolutions are generated by upsampling the outputs Otusing transpose convolutional blocks.

Decoding Step

The multi-resolution latent context grids generated from the previous step are then used to query points input to the MLP. Given a random query point x:=(x,y,t), k neighboring vertices of the query point at each dimension are selected. Using these neighboring vertices, the final values of the context vector are then interpolated using Gaussian interpolation. This process is repeated for each of the multi-resolution grids allowing the PINN framework to learn multi-scale spatio-temporal quantities.

The MLP outputs predictions that are subject to a loss function determined by the ICs, BCs, and the PDEs. The losses are backpropagated through the entire combined decoding and latent grid network and minimized via stochastic gradient descent. This end-to-end training allows the two-branch convGRU model to learn accurate time-evolution of the spatial and frequency domains in complex physical problems.