Hybrid TFET-MOSFET circuit design

A circuit includes a hybrid switch, which includes a Tunnel Field-Effect Transistor (TFET) having a first source, a first drain, and a first gate. The hybrid switch further includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected to the TFET in parallel, with the MOSFET including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate.

BACKGROUND

Metal-oxide-semiconductor (MOS) devices are key components of integrated circuits. A MOS device can work in three regions, depending on gate voltage Vgand source-drain voltage Vds, linear, saturation, and sub-threshold regions. The sub-threshold region is a region where Vgis smaller than the threshold voltage Vt. A parameter known as Sub-threshold Swing (SS) represents the easiness of switching the transistor current off and thus is an important factor in determining the speed of a MOS device. The sub-threshold swing can be expressed as a function of m*kT/q, where m is a parameter related to capacitance. The sub-threshold swing of a typical MOS device has a limit of about 60 mV/decade (kT/q) at room temperature, which in turn sets a limit for further scaling of operation voltage VDD and threshold voltage Vt. This limitation is due to the diffusion transport mechanism of carriers. For this reason, existing MOS devices typically cannot switch faster than 60 mV/decade at room temperatures. The 60 mV/decade sub-threshold swing limit also applies to FinFETs or ultra thin-body MOSFETs on silicon-on-insulator (SOI) devices. However, even with better gate control over the channel, an ultra thin body MOSFET on SOI or a FinFET can only achieve close to, but not below, the limit of 60 mV/decade. With such a limit, faster switching at low operation voltages for future nanometer devices cannot be achieved.

To solve the above-discussed problem, Tunnel Field Effect Transistors (TFETs) have been explored. TFETs can improve both of these parameters by changing the carrier injection mechanism. In a MOSFET, the SS is limited by the diffusion of carriers over the source-to-channel barrier where the injection current is proportional to kT/q. Hence at room temperature, the SS is 60 mV/dec. In a TFET, injection is governed by the band-to-band tunneling from the valence band of the source to the conduction band of the channel. Accordingly, much lower sub-threshold swing can be achieved. Since the TFETs are often designed to have a p-i-n diode configuration, much lower leakage currents are achieved. Also, the TFETs are more resistant to short-channel effects commonly seen on MOSFETs.

DETAILED DESCRIPTION

Hybrid switches including both Tunnel Field-Effect Transistors (TFETs) and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and the circuits adopting the hybrid switches are provided in accordance with various exemplary embodiments. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

Throughout the description, when two FETs (including TFETs and MOSFET) are referred to as connected in parallel, the sources of the two FETs are connected to each other, the drains of the two FETs are connected to each other, and the gates of the two FETs are connected to each other. Hence, the two parallel connected FETs act as a single FET. When the parallel connected FETs include a TFET and a MOSFET, the TFET and a MOSFET are in combination referred to as a hybrid FET or a hybrid switch.

FIG. 1illustrates a schematic circuit diagram of Static Random Access Memory (SRAM) circuit20having hierarchical bit lines in accordance with some embodiments of the present disclosure. SRAM circuit20includes one or a plurality of SRAM arrays22(including22A and22B), each including an array of SRAM cells24, which are arranged as a plurality of rows and columns. SRAM arrays22may be the sub-arrays of the same SRAM array.FIG. 1illustrates one SRAM cell24in each of SRAM arrays22as an example, although more SRAM cells24are included. Also, the structure of SRAM cell24is schematically illustrated, and SRAM cells24in accordance with the embodiments of the present disclosure may have any suitable structure the same as or different from illustrated. For example,FIG. 5illustrates an exemplary SRAM cell24that may be used in SRAM circuit20.

Each of SRAM arrays22includes a plurality of Local Bit Lines (LBLs), each connected to one column of SRAM cells in the respective SRAM array.FIG. 1schematically illustrates one of local bit-lines for each of the SRAM arrays22, wherein the local bit-lines are marked as LBL1and LBL2.

Local bit lines LBL1and LBL2(and other un-illustrated local bit lines) are connected to global bit line GBL. In the following discussion, the read operation of the SRAM cell24in SRAM array22A is discussed as an example. The operation of other SRAM cells is also similar, and hence is not repeated. In accordance with some embodiments of the present disclosure, the connection between global bit line GBL and local bit lines LBL1and LBL2are through hybrid switches26(including26A and26B). In a read operation to read the value in SRAM cell24that is in SRAM array22A, the read word line RWL is provided with a logic high voltage, and hence the value stored in the illustrated SRAM cell24is provided to local bit line LBL1.

Hybrid switch26A includes TFET28and MOSFET30connected in parallel. TFET28is a PFET in accordance with some exemplary embodiments. TFET28has an asymmetric structure, wherein source128is an n-type region, and the drain328is a p-type region. MOSFET30is also a PFET in accordance with some exemplary embodiments. MOSFET30, on the other hand, has a symmetric structure, with both source130and drain330being p-type regions. Gate228of TFET28is connected (shorted) to gate230of MOSFET30, with both being connected to local bit line LBL1. Source128of TFET28and source130of MOSFET30are connected to power supply voltage VDD. Drain328of TFET28and drain330of MOSFET30are connected to global bit line GBL. Throughout the description, sources128and130are in combination referred to as source128/130of hybrid switch26A, drains328and330are in combination referred to as drain328/330of hybrid switch26A, and gates228and230are in combination referred to as gate228/230of hybrid switch26A.

Local bit line LBL1is connected to gate228of TFET28and gate230of MOSFET30. In a read operation, global bit line GBL is pre-charged to have a low voltage. When local bit line LBL1has a logic-low voltage, hybrid switch26A is turned on, so that global bit line GBL is connected to, and charged by, power supply voltage VDD. The voltage on global bit line GBL thus rises. When local bit line LBL1has a logic-high voltage, hybrid switch26A is turned off, so that global bit line GBL remains to have the low voltage. Accordingly, the voltage on global bit line GBL is determined by the voltage of local bit line LBL1, which is further determined by the value stored in SRAM cell24. Accordingly, the value stored in SRAM cell24may be read onto global bit line GBL.

The performance of hybrid switch26A determines the performance of the SRAM circuit20in the read operations.FIG. 2illustrates some simulation results of SRAM circuit20(FIG. 1) in accordance with some embodiments of the present disclosure, wherein voltages VGBLon global bit lines GBL and voltages VLBL1on local bit line LBL1are illustrated as a function of time (in nano seconds). Solid line402illustrates the voltage on local bit line LBL1as a function of time, and solid line406illustrates the voltage on global bit line GBL as a function of time. Time point 0 (nsec) is the time when word line RWL (FIG. 1) is provided with a logic high voltage. At which time, a logic-high voltage is connected to local bit line LBL1, and the voltage on local bit line LBL1starts to drop (line402). In the meantime, the voltage on local bit line GBL starts to rise (line406).

Lines404and408are provided as a comparison. Lines404and408are the voltages on local bit line LBL1and global bit line GBL, respectively, when the hybrid switch26A inFIG. 1is replaced with a single p-type TFET. It is observed that the voltage reflected by line408(the voltage on global bit line) rises significantly slower than line406. This result indicates that the performance (the read speed) of the SRAM circuit20adopting hybrid switch26A (FIG. 1) is better than the performance of the SRAM circuit adopting the p-type TFET switch.

One of the reasons that the SRAM circuit adopting the hybrid switch has the improved performance over the SRAM circuit adopting the p-type TFET switch is that in the hybrid switch, a MOSFET is added, which compensates for the delayed saturation of the TFET that is connected in parallel to the MOSFET. Accordingly, the charging of the global bit line GBL is expedited, and the performance of SRAM circuit20is improved.

FIG. 3illustrates SRAM circuit20having hierarchical bit lines in accordance with alternative embodiments of the present disclosure. SRAM arrays22A and22B in these embodiments are essentially the same as shown inFIG. 1, and hence the details are not discussed herein. In these embodiments, hybrid switches26are also used to connect local bit lines LBL1and LBL2to global bit line GBL. The scheme of the connection, however, is different from what is shown inFIG. 1.

As shown inFIG. 3, hybrid switch26A has its source128/130connected to global bit line GBL, drain328/330connected to local bit line LBL1, and gate228/230connected to global word line GWL. In a read operation, global bit line GBL may be pre-charged to have a low voltage (or a high voltage in alternative embodiments). When global word line GWL is provided with a logic-low voltage, hybrid switch26A is turned on, and local bit line LBL1and global bit line GBL start sharing charges. The voltages on local bit line LBL1and global bit line GBL thus are adjusted according to their voltage levels. For example, when global bit line GBL is pre-charged to a high voltage, and when local bit line LBL1has a low voltage, the voltage on global bit line GBL is brought down due to the charge sharing. Conversely, when local bit line LBL1has a high voltage, after the charge sharing, the voltage on global bit line GBL remains high. Accordingly, the voltage on global bit line GBL is determined by the voltage of local bit line LBL1, which is further determined by the value stored in SRAM cell24. Hence, the value stored in SRAM cell24may be read onto global bit line GBL.

In these embodiments, the performance of hybrid switch26A determines the performance of the SRAM circuit20in the read operations since the performance of hybrid switch26A determines how fast the charge sharing is.FIG. 4illustrates some simulation results obtained from SRAM circuits20as shown inFIG. 3, wherein the voltages on global bit line GBL and local bit line LBL1are illustrated as a function of time. Line420represents the voltage on global word line GWL. Solid line412illustrates the voltage on local bit line LBL1as a function of time, and solid line416illustrates the voltage on global bit line GBL as a function of time. At time point 0 (nsec), both global word line GWL (FIG. 1) and local bit line LBL1have high voltages. When the voltage on global word line GWL becomes low (line420), both global bit line GBL and local bit line LBL1share charge with SRAM cell24(FIG. 3), which provides a low voltage. Accordingly, the voltages on both global bit line GBL (line416) and local bit line LBL1(line412) start to drop.

Lines414and418are provided as a comparison. Lines414and418are the voltages on local bit line LBL1and global bit line GBL, respectively, when the hybrid switch26A inFIG. 3is replaced with a single p-type TFET. It is observed that the voltage reflected by line418(the voltage on global bit line) drops significantly slower than line416. This result indicates that the performance (the read speed) of the SRAM circuit adopting hybrid switch26A (FIG. 3) is significantly better than the performance of the SRAM circuit adopting the p-type TFET switch.

FIGS. 1 and 3illustrate that the hybrid switches, which connect local bit lines to the respective global bit lines, include p-type TFETs and p-type MOSFETs. In accordance with alternative embodiments of the present disclosure, hybrid switch26inFIGS. 1 and 3are replaced with other hybrid switches, each including an n-type TFET and an n-type MOSFET connected in parallel. For example, hybrid switch28-1inFIG. 8may be used to replace hybrid switches26inFIGS. 1 and 3.

FIG. 5illustrates the circuit diagram of SRAM cell24in accordance with some exemplary embodiments. As shown inFIG. 5, SRAM cell24includes pass-gate transistors26(including26A and26B, also denoted as PG-1and PG-2), pull-up transistors PU-1and PU-2, which are p-type TFETs, and pull-down transistors PD-1and PD-2, which are n-type TFETs in accordance with some embodiments of the present disclosure. In accordance with alternative embodiments, pull up transistors PU-1and PU-2and pull-down transistors PD-1and PD-2are all MOSFETs rather than TFETs. Pass-gate transistors26A and26B are hybrid switches in accordance with some embodiments of the present disclosure. The gates of pass-gate transistors26A and26B are connected to, and controlled by, word-line WL that determines whether SRAM cell24is selected or not. A latch formed of pull-up transistors PU-1and PU-2and pull-down transistors PD-1and PD-2stores a bit. The stored bit can be written into, or read from, SRAM cell24through complementary bit lines BL and BLB, wherein BL and BLB may carry complementary bit-line signals. Bit lines BL and BLB may be local bit lines in accordance with some embodiments, which are also the local bit lines inFIGS. 1 and 3. Accordingly, the SRAM cell24as show inFIG. 5may be used in the hierarchical bit line structure as shown inFIGS. 1 and 3to replace the illustrated SRAM cell24inFIGS. 1 and 3. SRAM cell24is powered through a positive power supply node VDD that has a positive power supply voltage. SRAM cell24is also connected to power supply voltage VSS, which may be an electrical ground.

Hybrid switches26A and26B are alternatively referred to as hybrid pass-gate transistors26A and26B throughout the description. Since hybrid switches26A and26B have a same structure, the structure and the operation of hybrid switch26A is discussed, and the discussion also applies to hybrid switch26B. Hybrid switch26A also includes TFET28and MOSFET30connected in parallel. In accordance with some embodiments of the present disclosure, TFET28and MOSFET30are PFETs. In alternative embodiments, TFET28and MOSFET30are NFETs, as illustrated inFIG. 5. The source region of hybrid switch26A is connected to bit line BL. The drain region of hybrid switch26A is connected to the gates of pull-up transistor PU-2and pull-down transistor PD-2. The gate of hybrid switch26A is connected to word line WL. Similarly, the source of hybrid switch26B is connected to bit line bar BLB. The drain of hybrid switch26B is connected to the gates of pull-up transistor PU-1and pull-down transistor PD-1. The gate of hybrid switch26B is connected to word line WL.

The SRAM cell24including the hybrid pass-gate transistors26have improved writing static noise margin over the SRAM cells that only use TFETs as pass-gate transistors. For example,FIGS. 6 and 7illustrate some simulated curves obtained from some exemplary SRAM cells. The X-axis and the Y-axis are input voltages and output voltages of the cross-coupled latches in the SRAM cells. Dashed lines424and426are obtained from the SRAM cell24shown inFIG. 5. Solid lines428and430are obtained from a SRAM cell wherein all of its transistors are TFETs, and the respective SRAM cell is referred to as an all-TFET SRAM cell throughout the description. Rectangle432illustrates how the static noise margin of SRAM cell24(FIG. 5) is obtained, wherein the static noise margin of SRAM cell24is SNM1. Rectangle433illustrates how the static noise margin of the all-TFET SRAM cell is obtained, wherein the static noise margin of the all-TFET SRAM cell is SNM2.FIG. 6illustrates that static noise margin SNM1is significantly greater than static noise margin SNM2, indicating that the static noise margin of the SRAM cell having the hybrid pass-gate transistors has a much higher static noise margin than the all-TFET SRAM cell.

The simulation results shown inFIG. 6are obtained when the power supply voltage VDD (FIG. 5) is equal to 0.3 V. When power supply voltage VDD is increased, the static noise margin of the SRAM cells in accordance with the embodiments of the present disclosure can be further improved.FIG. 7illustrates the results similar to the results shown inFIG. 6, except that the results inFIG. 7are obtained when power supply voltage VDD is increased to 0.5 V. The results inFIG. 7indicate that with the increase of power supply voltage VDD, the static noise margin SNM3of SRAM cell24is further improved over static noise margin SNM4of the all-TFET SRAM cell. This is because the extra MOSFET in SRAM cell24(compared to the all-TFET SRAM cell) provides a current for enhancing the write margin. In addition, MOSFETs have bi-directional behavior, and their currents can flow in opposite directions. TFETs, however, have the uni-directional behavior, and their currents can only flow in a single direction in each TFET. Accordingly, the bi-directional MOSFET (and the corresponding hybrid switch) facilitates a push-pull action to improve the static noise margin.

FIG. 8illustrates multiplexer50in accordance with some embodiments of the present disclosure. Multiplexer50includes channels52(including52A and52B) between inputs54(including54A and54B) and output56. Channel52A is configured to interconnect and disconnect input54A and output56. Channel52B is configured to interconnect and disconnect input54B and output56. Selection nodes58A and58B are connected to the gates of the transistors in multiplexer50to control the selection of one of inputs54A and54B, whose datum is passed to output56when the respective input is selected. For example, when selection node58A has a high voltage (“1”), and selection node58B has a low voltage (“0”), input54A is selected, and its datum is passed to output56. Conversely, when selection node58A has a low voltage (“0”), and selection node58B has a high voltage (“1”), input54B is selected, and its datum is passed to output56.

Each of channels52A and52B includes n-type hybrid switch26A and p-type hybrid switch26C parallel connected with hybrid switch26A. In accordance with some embodiments of the present disclosure, in channel52A, n-type hybrid switch26A includes n-type TFET28-1and n-type MOSFET30-1connected in parallel, wherein the gates of n-type TFET28-1and n-type MOSFET30-1are connected to selection node58A. P-type hybrid switch26C includes p-type TFET28-2and p-type MOSFET30-2connected in parallel, wherein the gates of p-type TFET28-2and p-type MOSFET30-2are connected to selection node58B. It is noted that in the same channel52A (or52B), all four transistors28-1,28-2,30-1, and30-2are connected in parallel.

In accordance with some embodiments, as shown inFIG. 8, the source regions of the TFETs28-1and28-2connected to input node54, and the drain regions of TFETs28-1and28-2are connected to output node56.

The multiplexer50in accordance with the embodiments of the present disclosure have improved performance over the all-TFET multiplexers include TFETs only. For example, in an all-TFET multiplexer, each of the channels is formed of two TFETs, with the source and drain of one TFET connected to the drain and source, respectively, of the other TFET.FIG. 9illustrates simulated voltages on the outputs of exemplary multiplexers as a function of time. InFIG. 9, line434represents the voltage at the selection node58A, line436represents the output voltage of the all-TFET multiplexer, and line435represents the output voltage of multiplexer50inFIG. 8. In the simulations, value “0” (a logic low voltage) is to be passed from inputs to outputs. It is observed that line435drops much faster than line436. Accordingly,FIG. 9illustrates that when a datum “0” is passed from input54to output56, the multiplexer50inFIG. 8has better performance than the all-TFET multiplexer. Alternatively stated, the delay caused by the multiplexers50(FIG. 8) is lower compared to the delay caused by the all-TFET multiplexer since the output voltage in multiplexer50(FIG. 8) can drop much faster than the all-TFET multiplexers.

FIG. 10illustrates the simulated voltages on the outputs of multiplexers as a function of time. The voltages illustrated inFIG. 10are obtained when datum “1” is passed from the inputs to the respective outputs. InFIG. 10, line434again represents the voltage at the selection node58A, line437represents the output voltage of the all-TFET multiplexer, and line438represents the output voltage of multiplexer50inFIG. 8. It is observed that line438rises much faster than line437. In addition, line437saturates at a low voltage (about 0.42V) much lower than the power supply voltage (0.5V). Accordingly,FIG. 10illustrates that when datum “1” is passed from input to output, the multiplexer in accordance with the embodiments of the present disclosure has better performance than the all-TFET multiplexer. Alternatively stated, the delay caused by the multiplexers50(FIG. 8) in the passing of datum “1” is lower compared to the delay caused by the all-TFET multiplexer since the output voltage in multiplexer50(FIG. 8) can rise much faster than the all-TFET multiplexers.

The embodiments of the present disclosure have some advantageous features. TFETs have much lower sub-threshold swing and reduced leakage currents. Accordingly, TFETs are preferred in some circuits over MOSFETs. The circuits adopting TFETs only, however, are not satisfactory due to the delayed saturation and unidirectional behavior of the TFETs. In the embodiments of the present disclosure, hybrid switches/transistors are used, wherein the MOSFETs in the hybrid switches compensate for the delayed saturation and the unidirectional behavior of the TFETs. Accordingly, the circuits including the hybrid switches have the advantageous features of the TFETs, with the disadvantageous features of the TFETs eliminated or at least reduced.

In accordance with some embodiments of the present disclosure, a circuit includes a hybrid switch, which includes a TFET having a first source, a first drain, and a first gate. The hybrid switch further includes a MOSFET connected to the TFET in parallel, with the MOSFET including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate.

In accordance with alternative embodiments of the present disclosure, a circuit includes a first SRAM cell and a second SRAM cell, a first and a second local bit line coupled to the first SRAM cell and the second SRAM cell, respectively, a global bit line, and a first hybrid switch and a second hybrid switch. Each of the first and the second hybrid switches includes a TFET and a MOSFET connected to the TFET in parallel. The TFET has a first source, a first drain, and a first gate. The MOSFET includes a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate. The first hybrid switch and the second hybrid switch connect the first local bit line and the second local bit line, respectively, to the global bit line.

In accordance with yet alternative embodiments of the present disclosure, a circuit includes a multiplexer, which includes an input node, an output node, and a hybrid switch. The hybrid switch includes a TFET and a MOSFET connected to the TFET in parallel. Each of the TFET and the MOSFET has a source region connected to the input node, and a drain region connected to the output node.