Drain sharing for memory cell thin film access transistors and methods for forming the same

A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

BACKGROUND

Thin film transistors (TFT) made of oxide semiconductors are an attractive option for BEOL integration since TFTs may be processed at low temperatures and thus, will not damage previously fabricated devices. For example, the fabrication conditions and techniques may not damage previously fabricated FEOL devices.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Elements with the same reference numerals refer to the same element, and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise.

Generally, the structures and methods of the present disclosure may be used to form a semiconductor structure including at least two dynamic random access memory cells such as a two-dimensional array of dynamic random access memory cells. Specifically, a semiconducting metal oxide plate may be used to provide a pair of semiconducting channels for a pair of access transistors. A pair of source electrodes and a common drain electrode may be formed on a top surface of the semiconducting metal oxide plate to efficiently use the area of the semiconducting metal oxide plate. Thus, the source electrodes may be formed at end portions of the semiconducting metal oxide plate, and the common drain electrode may be formed at a center portion of the semiconducting metal oxide plate. A pair of capacitor structures may be subsequently formed, and may be subsequently electrically connected to a respective one of the source electrodes. Peripheral circuits for driving word lines and bit lines may be formed directly on a single crystalline silicon layer in an underlying silicon substrate. Metal interconnect structures formed within in dielectric material layers may be provided between the silicon substrate and the dynamic random access memory cells to provide electrical connection between the peripheral circuits and the dynamic random access memory cells.

Referring toFIG.1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated. The first exemplary structure includes a substrate8, which may be a semiconductor substrate such as a commercially available silicon substrate. The substrate8may include a semiconductor material layer9at least at an upper portion thereof. The semiconductor material layer9may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon. In one embodiment, the substrate8may include a single crystalline silicon substrate including a single crystalline silicon material.

Shallow trench isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures720. Field effect transistors701may be formed over the top surface of the semiconductor material layer9. For example, each field effect transistor701may include a source electrode732, a drain electrode738, a semiconductor channel735that includes a surface portion of the substrate8extending between the source electrode732and the drain electrode738, and a gate structure750. The semiconductor channel735may include a single crystalline semiconductor material. Each gate structure750may include a gate dielectric layer752, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal-semiconductor alloy region742may be formed on each source electrode732, and a drain-side metal-semiconductor alloy region748may be formed on each drain electrode738.

The first exemplary structure may include a memory array region100in which an array of ferroelectric memory cells may be subsequently formed. The first exemplary structure may further include a peripheral region200in which metal wiring for the array of ferroelectric memory devices is provided. Generally, the field effect transistors701in the CMOS circuitry700may be electrically connected to an electrode of a respective ferroelectric memory cell by a respective set of metal interconnect structures.

Devices (such as field effect transistors701) in the peripheral region200may provide functions that operate the array of ferroelectric memory cells to be subsequently formed. Specifically, devices in the peripheral region may be configured to control the programming operation, the erase operation, and the sensing (read) operation of the array of ferroelectric memory cells. For example, the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer9may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry700.

One or more of the field effect transistors701in the CMOS circuitry700may include a semiconductor channel735that contains a portion of the semiconductor material layer9in the substrate8. If the semiconductor material layer9includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel735of each field effect transistor701in the CMOS circuitry700may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a plurality of field effect transistors701in the CMOS circuitry700may include a respective node that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed. For example, a plurality of field effect transistors701in the CMOS circuitry700may include a respective source electrode732or a respective drain electrode738that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be subsequently formed.

In one embodiment, the CMOS circuitry700may include a programming control circuit configured to control gate voltages of a set of field effect transistors701that are used for programming a respective ferroelectric memory cell and to control gate voltages of thin film transistors to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a respective ferroelectric dielectric material layer in a selected ferroelectric memory cell into a first polarization state in which electrical polarization in the ferroelectric dielectric material layer points toward a first electrode of the selected ferroelectric memory cell, and to provide a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state in which the electrical polarization in the ferroelectric dielectric material layer points toward a second electrode of the selected ferroelectric memory cell.

In one embodiment, the substrate8may include a single crystalline silicon substrate, and the field effect transistors701may include a respective portion of the single crystalline silicon substrate as a semiconducting channel. As used herein, a “semiconducting” element refers to an element having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant.

According to an aspect of the present disclosure, the field effect transistors701may be subsequently electrically connected to drain electrodes and gate electrodes of access transistors including semiconducting metal oxide plates to be formed above the field effect transistors701. In one embodiment, a subset of the field effect transistors701may be subsequently electrically connected to at least one of the drain electrodes and the gate electrodes. For example, the field effect transistors701may comprise first word line drivers configured to apply a first gate voltage to first word lines through a first subset of lower-level metal interconnect structures to be subsequently formed, and second word line drivers configured to apply a second gate voltage to second word lines through a second subset of the lower-level metal interconnect structures. Further, the field effect transistors701may comprise bit line drivers configured to apply a bit line bias voltage to bit lines to be subsequently formed, and sense amplifiers configured to detect electrical current that flows through the bit lines during a read operation.

Various metal interconnect structures formed within dielectric material layers may be subsequently formed over the substrate8and the semiconductor devices thereupon (such as field effect transistors701). In an illustrative example, the dielectric material layers may include, for example, a first dielectric material layer601that may be a layer that surrounds the contact structure connected to the source and drains (sometimes referred to as a contact-level dielectric material layer601), a first interconnect-level dielectric material layer610, and a second interconnect-level dielectric material layer620. The metal interconnect structures may include device contact via structures612formed in the first dielectric material layer601and contact a respective component of the CMOS circuitry700, first metal line structures618formed in the first interconnect-level dielectric material layer610, first metal via structures622formed in a lower portion of the second interconnect-level dielectric material layer620, and second metal line structures628formed in an upper portion of the second interconnect-level dielectric material layer620.

Each of the dielectric material layers (601,610,620) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612,618,622,628) may include at least one conductive material, which may be a combination of a metallic liner (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures622and the second metal line structures628may be formed as integrated line and via structures by a dual damascene process. The dielectric material layers (601,610,620) are herein referred to as lower-lower-level dielectric material layers. The metal interconnect structures (612,618,622,628) formed within in the lower-level dielectric material layers are herein referred to as lower-level metal interconnect structures.

While the present disclosure is described using an embodiment in which an array of memory cells may be formed over the second line-and-via-level dielectric material layer620, embodiments are expressly contemplated herein in which the array of memory cells may be formed at a different metal interconnect level.

An array of thin film transistors and an array of ferroelectric memory cells may be subsequently deposited over the dielectric material layers (601,610,620) that have formed therein the metal interconnect structures (612,618,622,628). The set of all dielectric material layer that are formed prior to formation of an array of thin film transistors or an array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (601,610,620). The set of all metal interconnect structures that is formed within the lower-level dielectric material layers (601,610,620) is herein referred to as first metal interconnect structures (612,618,622,628). Generally, first metal interconnect structures (612,618,622,628) formed within at least one lower-level dielectric material layer (601,610,620) may be formed over the semiconductor material layer9that is located in the substrate8.

According to an aspect of the present disclosure, thin film transistors (TFTs) may be subsequently formed in a metal interconnect level that overlies that metal interconnect levels that contain the lower-level dielectric material layers (601,610,620) and the first metal interconnect structures (612,618,622,628). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower-level dielectric material layers (601,610,620). The planar dielectric material layer is herein referred to as an insulating matrix layer635. The insulating matrix layer635includes a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer635may be in a range from 20 nm to 300 nm, although lesser and greater thicknesses may also be used.

Generally, interconnect-level dielectric layers (such as the lower-level dielectric material layer (601,610,620)) containing therein the metal interconnect structures (such as the first metal interconnect structures (612,618,622,628)) may be formed over semiconductor devices. The insulating matrix layer635may be formed over the interconnect-level dielectric layers.

Referring toFIGS.2A-2C, a portion of a memory array region of the first exemplary structure is illustrated, which corresponds to the area of four unit cells UC of a two-dimensional array of dynamic random access memory cells. Instances of the unit cell UC may be repeated along the first horizontal direction hd1and along the second horizontal direction hd2. Each unit cell UC may have an area for forming a pair of dynamic random access memory cells, each of which includes a series connection of a respective access transistor and a respective capacitor.

A photoresist layer (not shown) may be applied over a top surface of the insulating matrix layer635, and may be lithographically patterned to form line-shaped openings that may be laterally spaced apart along a first horizontal direction hd1and laterally extend along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. An anisotropic etch process may be performed to transfer the pattern of the line-shaped openings in the photoresist layer into an upper portion of the insulating matrix layer635. Line trenches may be formed in an upper portion of the insulating matrix layer635. The line trenches are herein referred to as bottom gate trenches19, which include first bottom gate trenches19A (which are first line trenches) and second bottom gate trenches19B (which are second line trenches) that alternate along the first horizontal direction hd1. A first bottom gate trench19A and a second bottom gate trench19B extends through each unit cell UC. The first bottom gate trench19A and the second bottom gate trench19B laterally extend along the second horizontal direction hd2, and are laterally spaced apart along the first horizontal direction hd1.

In one embodiment, the width of each of the bottom gate trenches19along the first horizontal direction hd1may be in a range from 20 nm to 300 nm, although lesser and greater widths may also be used. The depth of each of the bottom gate trenches19may be in a range from 20 nm to 150 nm, although lesser and greater depths may also be used. The width-to-height ratio of each bottom gate trench19may be in a range to 0.5 to 4, such as from 1 to 2, although lesser and greater ratios may also be used. The photoresist layer may be subsequently removed, for example, by ashing.

Referring toFIGS.3A-3E, at least one conductive material may be deposited in the bottom gate trenches19. The at least one conductive material may include, for example, a metallic barrier liner material (such as TiN, TaN, and/or WN) and a metallic fill material (such as Cu, W, Mo, Co, Ru, etc.). Other suitable metallic liner and metallic fill materials within the contemplated scope of disclosure may also be used. Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the insulating matrix layer635by a planarization process, which may include a chemical mechanical polishing (CMP) process and/or a recess etch process. Bottom word lines15may be formed in the bottom gate trenches19. The bottom word lines15may include first bottom word lines15A that may be formed in the first bottom gate trenches19A and second bottom word lines15B that may be formed in the second bottom gate trenches19B. Each of the bottom word lines15may include a lower metallic barrier liner16and a lower metallic gate material portion17. Each lower metallic barrier liner16comprises a remaining portion of the metallic barrier liner material. Each lower metallic gate material portion17comprises a remaining portion of the metallic fill material. Generally, at least one conductive material may be deposited and planarized in the first line trenches19A and the second line trenches19B. Remaining portions of the at least one conductive material in the first line trenches19A and the second line trenches19B comprise first bottom word lines15A and second bottom word lines15B. Each first bottom word line15A includes first gate electrodes, which are portions of a respective first bottom word line15A that overlap with semiconducting metal oxide plates to be subsequently formed. Each second bottom word line15A may include second gate electrodes, which are portions of a respective second bottom word line15A that overlap with semiconducting metal oxide plates that may be subsequently formed.

Referring toFIGS.4A-4E, a continuous bottom gate dielectric layer10C, a continuous semiconducting metal oxide layer20C, and a continuous top gate dielectric layer30C may be sequentially deposited over the insulating matrix layer635and the bottom word lines15.

The continuous bottom gate dielectric layer10C may be formed over the insulating matrix layer635and the bottom word lines15by deposition of at least one gate dielectric material. The gate dielectric material may include, but is not limited to, silicon oxide, silicon oxynitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or a stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. The gate dielectric material may be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the continuous bottom gate dielectric layer10C may be in a range from 1 nm to 12 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses may also be used.

The continuous semiconducting metal oxide layer20C may be deposited over the continuous bottom gate dielectric layer10C. In one embodiment, the semiconducting material includes a material providing electrical conductivity in a range from 1.0 S/m to 1.0×105S/m upon suitable doping with electrical dopants (which may be p-type dopants or n-type dopants). Exemplary semiconducting materials that may be used for the continuous semiconducting metal oxide layer20C include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconducting materials are within the contemplated scope of disclosure. In one embodiment, the semiconducting material of the continuous semiconducting metal oxide layer20C may include indium gallium zinc oxide.

The continuous semiconducting metal oxide layer20C may include a polycrystalline semiconducting material, or an amorphous semiconducting material that may be subsequently annealed into a polycrystalline semiconducting material having a greater average grain size. The continuous semiconducting metal oxide layer20C may be deposited by physical vapor deposition although other suitable deposition processes may be used. The thickness of the continuous semiconducting metal oxide layer20C may be in a range from 1 nm to 100 nm, such as from 2 nm to 50 nm and/or from 4 nm to 15 nm, although lesser and greater thicknesses may also be used.

The continuous top gate dielectric layer30C may be formed over the continuous semiconducting metal oxide layer20C by deposition of at least one gate dielectric material. The gate dielectric material may include, but is not limited to, silicon oxide, silicon oxynitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or a stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. The gate dielectric material may be deposited by atomic layer deposition or chemical vapor deposition although other suitable deposition processes may be used. The thickness of the continuous top gate dielectric layer30C may be in a range from 1 nm to 12 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses may also be used.

Referring toFIGS.5A-5E, a photoresist layer43may be applied over the continuous top gate dielectric layer30C, and may be lithographically patterned to form discrete patterned photoresist material portion. Each patterned portion of the photoresist layer43may be located within the area of a respective one of the unit cells UC. The area of each patterned portion of the photoresist layer43may define the area of a semiconducting metal oxide portion to be subsequently patterned from the continuous semiconducting metal oxide layer20C. In one embodiment, each patterned portion of the photoresist layer43may have a horizontal cross-sectional shape of a rectangle or a rounded rectangle.

The pattern in the photoresist layer43may be transferred through the continuous top gate dielectric layer30C, the continuous semiconducting metal oxide layer20C, and the continuous bottom gate dielectric layer10C by performing an anisotropic etch process. Patterned portions of the continuous top gate dielectric layer30C may comprise a two-dimensional array of top gate dielectric layers30′. Patterned portion of the continuous semiconducting metal oxide layer20C comprise a two-dimensional array of semiconducting metal oxide plates20. Patterned portion of the continuous bottom gate dielectric layer10C comprise a two-dimensional array of bottom gate dielectric layers10. A two dimensional array of layer stacks of a bottom gate dielectric layer10, a semiconducting metal oxide plate20, and a top gate dielectric layer30′ may be formed. Sidewalls of the bottom gate dielectric layer10, the semiconducting metal oxide plate20, and the top gate dielectric layer30′ within each layer stack may be vertically coincident, i.e., may be located within a same vertical plane. The photoresist layer43may be subsequently removed, for example, by ashing.

In one embodiment, each semiconducting metal oxide plate20may have a horizontal cross-sectional shape of a rectangle or a rounded rectangle. In one embodiment, each semiconducting metal oxide plate20may have a lateral dimension along the first horizontal direction hd1in a range from 60 nm to 1,000 nm, such as from 100 nm to 300 nm, although lesser and greater lateral dimensions may also be used. In one embodiment, each semiconducting metal oxide plate20may have a lateral dimension along the second horizontal direction hd2in a range from 20 nm to 500 nm, such as from 40 nm to 250 nm, although lesser and greater lateral dimensions may also be used. The ratio of the lateral dimension along the first horizontal direction hd1to the lateral dimension along the second horizontal direction hd2in each semiconducting metal oxide plate20may be in a range from 0.5 to 4, such as from 1 to 2, although lesser and greater ratios may also be used.

Generally, at least one continuous gate dielectric layer (10C,30C) and a continuous semiconducting metal oxide layer20C may be formed over first gate electrodes comprising portions of the first bottom word lines15A and over second gate electrodes comprising portions of the second bottom word lines15B. The at least one continuous gate dielectric layer (10C,30C) and the continuous semiconducting metal oxide layer20C may be patterned into gate dielectric layers (10,30′) and semiconducting metal oxide plates20. Each bottom gate dielectric layer10may include a first gate dielectric having an areal overlap with an underlying first bottom word line15A and a second gate dielectric having an areal overlap with an underlying second bottom word lines15B. Generally, a first gate dielectric a second gate dielectric may be provided as portions of a bottom gate dielectric layer10that have an areal overlap with a first bottom word line15A or with a second bottom word line15B.

Generally, a semiconducting metal oxide plate20may be formed over lower-level dielectric material layers (601,610,620) that overlies a substrate8. A first gate dielectric (comprising a first portion of a bottom gate dielectric layer10) may contacts a first portion of a bottom surface of the semiconducting metal oxide plate20. A first gate electrode (comprising an aerial portion of a first bottom word line15A) contacts a bottom surface of the first gate dielectric. A second gate dielectric (comprising a second portion of the bottom gate dielectric layer10) may contacts a second portion of the bottom surface of the semiconducting metal oxide plate20. A second gate electrode (comprising a portion of a second bottom word line15B) contacts a bottom surface of the second gate dielectric.

The first gate electrode comprises a portion of a first bottom word line15A having an areal overlap with the semiconducting metal oxide plate20in a plan view, and the second gate electrode comprises a portion of a second bottom word line15B having an areal overlap with the semiconducting metal oxide plate20in the plan view. The first bottom word line15A and the second bottom word line15B laterally extend along the second horizontal direction hd2that is perpendicular to the first horizontal direction hd1.

Referring toFIGS.6A-6E, a photoresist layer45may be applied over the first exemplary structure, and may be lithographically patterned to form line-shaped photoresist material portions that laterally extend along the second horizontal direction hd1an laterally spaced apart along the first horizontal direction hd1. The areas of the line-shaped photoresist material portions may overlap with the area of the first bottom word line15A and the second bottom word line15B, and may be located entirely within the areas of the first bottom word line15A and the second bottom word line15B. In one embodiment, the line-shaped photoresist material portions may have a lesser width along the first horizontal direction hd1than the first bottom word line15A and the second bottom word line15B.

An etch process may be performed to remove unmasked portions of the top gate dielectric layers30′ without removing the material of the semiconducting metal oxide plates20. An anisotropic etch process or an isotropic etch process may be used. A patterned portions of a top gate dielectric layer30′ that overlies a first bottom word line15A comprises a first top gate dielectric30A, and a patterned portion of a top gate dielectric layer30′ that overlies a second bottom word line15B comprises a second top gate dielectric30B. The first top gate dielectrics30A and the second top gate dielectrics30B are collectively referred to as top gate dielectrics30. The photoresist layer45may be subsequently removed, for example, by ashing.

Referring toFIGS.7A-7E, a dielectric material layer may be deposited over a two-dimensional array of combinations of a bottom gate dielectric layer10, a semiconducting metal oxide plate20, a first top gate dielectric30A, and a second top gate dielectric30B. The dielectric material layer is herein referred to as a thin-film-transistor-level (TFT-level) dielectric material layer40, i.e., a dielectric material layer that is located at the level of thin film transistors. The TFT-level dielectric material layer40includes a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, or a stack thereof. Optionally, the TFT-level dielectric material layer40may be planarized to provide a flat top surface. The thickness of the TFT-level dielectric material layer40, as measured from an interface with the insulating matrix layer635, may be in a range from 100 nm to 1,000 nm, such as from 200 nm to 500 nm, although lesser and greater thicknesses may also be used.

A photoresist layer47may be applied over the TFT-level dielectric material layer40, and may be lithographically patterned to form line trenches and discrete openings therein. The pattern of the line trenches and the discrete openings in the photoresist layer47may be transferred through the TFT-level dielectric material layer40to form top gate trenches34, source cavities51, and drain cavities59.

The top gate trenches34may laterally extend along the second horizontal direction hd2and may straddle over multiple top gate dielectrics30that are located on multiple semiconducting metal oxide plates20. The top gate trenches34may have a respective uniform width along the first horizontal direction hd1, which may be, for example, in a range from 10 nm to 250 nm, such as from 30 nm to 150 nm, although lesser and greater widths may also be used. The width of the top gate trenches34may be less than the width of the top gate dielectrics30to avoid physical exposure of a top surface of a semiconducting metal oxide plate20underneath the top gate trenches34. Each top gate trench34may be formed over a respective one of the bottom word lines15. For example, first top gate trenches34may be formed over first bottom word lines15A, and second top gate trenches34may be formed over second bottom word lines15B. Thus, a pair of top gate trenches34straddle each semiconducting metal oxide plate20along the second horizontal direction hd2. Top surfaces of a row of top gate dielectrics30may be physically exposed at the bottom of each top gate trench34.

A pair of source cavities51may be formed over each semiconducting metal oxide plate20. Specifically, the pair of source cavities51may be formed at end portions of a respective one of the semiconducting metal oxide plates20that are laterally spaced apart along the first horizontal direction hd1. Thus, the pair of source cavities51may be laterally spaced apart by a pair of top gate trenches34that straddle the respective one of the semiconducting metal oxide plates20. The area of each source cavity51may be entirely within the area of an underlying semiconducting metal oxide plate20. A portion of a top surface of a semiconducting metal oxide plate20may be physically exposed at the bottom of each source cavity51.

A drain cavity59may be formed over each semiconducting metal oxide plate20between a respective pair of top gate trenches34. A portion of a top surface of a semiconducting metal oxide plate20may be physically exposed at the bottom of each drain cavity59.

Generally, a set of cavities (51,34,59) may be formed through the TFT-level dielectric material layer40down to a top surface of each semiconducting metal oxide plate20. The set of cavities (51,34,59) may comprise, from one side to another along the first horizontal direction hd1, a first source cavity51, a first top gate trench34, a drain cavity59, a second top gate trench34, and a second source cavity51. The photoresist layer47may be subsequently removed, for example, by ashing.

Referring toFIGS.8A-8E, at least one conductive material may be deposited in the cavities (51,34,59) and over the TFT-level dielectric material layer40. The at least one conductive material may include a metallic liner material and a metallic fill material. The metallic liner material may include a conductive metallic nitride or a conductive metallic carbide such as TiN, TaN, WN, TiC, TaC, and/or WC. The metallic fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplated scope of disclosure may also be used.

Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the TFT-level dielectric material layer40by a planarization process, which may use a CMP process and/or a recess etch process. Other suitable planarization processes may be used. Each remaining portion of the at least one conductive material filling a source cavity51constitutes a source electrode52. Each remaining portion of the at least one conductive material filling a drain cavity59constitutes a drain electrode56. Each remaining portion of the at least one conductive material filling a top gate trench34constitutes a top word lines35including top gate electrodes for underlying semiconducting metal oxide plates20.

In one embodiment, each source electrode52may include a source metallic liner53that is a remaining portion of the metallic liner material, and a source metallic fill material portion54that is a remaining portion of the metallic fill material. Each drain electrode56may include a drain metallic liner57that is a remaining portion of the metallic liner material, and a drain metallic fill material portion58that is a remaining portion of the metallic fill material. Each top word line35may include a gate metallic liner36that is a remaining portion of the metallic liner material, and a gate metallic fill material portion37that is a remaining portion of the metallic fill material.

Generally, a first source electrode52, a first top word line35including a first top gate electrode, a drain electrode56, a second top word line35including a second top gate electrode, and a second source electrode52may be formed on a respective portion of a top surface of each semiconducting metal oxide plate20. The drain electrode56is formed between a first gate structure (which may comprise a combination of a first bottom gate dielectric and a first bottom gate electrode, or as a combination of a first top gate dielectric30A and a first top gate electrode including a portion of a first top word line35) and a second gate structure (which may comprise a combination of a second bottom gate dielectric and a second bottom gate electrode, or as a combination of a second top gate dielectric30B and a second top gate electrode including a portion of a second top word line35). The first source electrode52is laterally spaced from the drain electrode56by the first gate structure {(15A,10) or (30,35)}, and the second source electrode52is laterally spaced from the drain electrode56by the second gate structure {(15A,10) or (30,35)}.

Generally, a first thin film transistor and a second thin film transistor may be formed in each unit cell UC. The first thin film transistor and the second thin film transistor comprise a semiconducting metal oxide plate20located over a substrate8as a continuous material portion, and a set of electrode structures (52,15,35,56) located on the semiconducting metal oxide plate20and comprising, from one side to another along a first horizontal direction hd1, a first source electrode52, a first gate electrode (15or35), a drain electrode56, a second gate electrode (15or35), and a second source electrode52. The first gate electrode (15or35) and the second gate electrode (15or35) may be spaced from the semiconducting metal oxide plate20by a first gate dielectric (which may be a first portion of a bottom gate dielectric layer10or a first top gate dielectric30A) and a second gate dielectric (which may be a second portion of the bottom gate dielectric layer10or a second top gate dielectric30B), respectively. A first portion of the semiconducting metal oxide plate20laterally extending between the first source electrode52and the drain electrode56comprises a first semiconductor channel, and a second portion of the semiconducting metal oxide plate20laterally extending between the second source electrode52and the drain electrode56comprises a second semiconductor channel.

The semiconducting metal oxide plate20and the set of electrode structures (52,15,35,56) may be formed within a TFT-level dielectric material layer40. Top surfaces of the first source electrode52, the drain electrode56, and the second source electrode52may be located within a horizontal plane (i.e., co-planar) including a top surface of the TFT-level dielectric material layer40.

In one embodiment, the bottom word lines15may be omitted and the top word lines35may be present. In this embodiment, the bottom gate dielectric layers10may also be omitted. In another embodiment, the top word lines35may be omitted and the bottom word lines15may be present. In this embodiment, the top gate dielectrics30may also be omitted. In yet another embodiment, the bottom word lines15and the top word lines35may be present.

In embodiments in which the bottom word lines15and the top word lines35are present, the bottom gate dielectric layers10and the top gate dielectrics30are present. In this embodiment, first gate dielectrics may be provided as first portions of a respective bottom gate dielectric layer10having an areal overlap with first bottom word lines15A, and second gate dielectrics may be provided as portions of a respective bottom gate dielectric layer10having an areal overlap with second bottom word lines15B. An additional first gate dielectric and an additional second gate dielectric may be provided for each semiconducting metal oxide plate20. The additional first gate dielectric comprise a first top gate dielectric30A, and the additional second gate dielectric may comprise a second top gate dielectric30B. The additional first gate dielectric contacts a first portion of a top surface of the semiconducting metal oxide plate20, and an additional first gate electrode (comprising a portion of a first top word line35) may contact a top surface of the additional first gate dielectric. The additional second gate dielectric contacts a second portion of a top surface of the semiconducting metal oxide plate20, and an additional second gate electrode (comprising a portion of a second top word line35) may contact a top surface of the additional second gate dielectric.

In one embodiment, each of the first source electrode52, the first additional gate electrode (such as a portion of a first top word line35), the drain electrode56, the second additional gate electrode (such as a portion of a second top word line35), and the second source electrode52may have a respective top surface located within a horizontal plane including the top surface of a TFT-level dielectric material layer40that has formed therein the semiconducting metal oxide plate20. In one embodiment, each of the first source electrode52, the first additional gate electrode (such as a portion of a first top word line35), the drain electrode56, the second additional gate electrode (such as a portion of a second top word line35), and the second source electrode52may comprise a combination of a respective metallic barrier liner (53,36,57) having a first material composition and a respective metallic fill material portion (54,37,58) having a second material composition.

Generally, a contiguous combination of a gate dielectric and a gate electrode comprising a portion of a word line constitutes a gate structure. A first gate structure and a second gate structure may be formed prior to, and/or after, formation of the semiconducting metal oxide plate20within each unit cell UC. The first gate structure and the second gate structure are laterally spaced apart along the first horizontal direction hd1. The first gate structure comprises a first gate dielectric (comprising a first portion of a bottom gate dielectric layer10or as a first top gate dielectric30) and a first gate electrode (comprising a portion of a bottom word line15or a top word line35), and the second gate structure comprises a second gate dielectric (comprising a second portion of a bottom gate dielectric layer10or as a second top gate dielectric30) and a second gate electrode (comprising a portion of a bottom word line15or a top word line35).

Referring toFIGS.9A-9E, at least one first upper-level dielectric material layer70and first upper-level metal interconnect structures (72,74,76,78) may be formed over the TFT-level dielectric material layer40. The at least one first upper-level dielectric material layer70may include a first via-level dielectric material layer having formed therein source contact via structures72and drain contact via structures76, and a first line-level dielectric material layer having formed therein first source connection pads74and bit lines78. In this embodiment, the first via-level dielectric material layer may be formed first, and the source contact via structures72and the drain contact via structures76may be formed through the first via-level dielectric material layer. The first line-level dielectric material layer may be subsequently formed over the first via-level dielectric material layer, and the first source connection pads74and the bit lines78may be subsequently formed through the first line-level dielectric material layer on a respective one of the source contact via structures72and the drain contact via structures76.

Alternatively, the first via-level dielectric material layer and the first line-level dielectric material layer may be formed as a single dielectric material layer, and a dual damascene process may be performed to form integrated line and via structures. The integrated line and via structures include source-side integrated line and via structures including a respective combination of a source contact via structure72and a first source connection pad74, and drain-side integrated line and via structures including a respective combination of drain contact via structures72and a bit line78that is integrally formed within the drain contact via structures72. Generally, each bit line78laterally extends along the first horizontal direction hd1and may be electrically connected to a set of drain electrodes56that are arranged along the first horizontal direction hd1.

Referring toFIGS.10A-10E, at least one second upper-level dielectric material layer80and second upper-level metal interconnect structures (82,84) may be formed over the at least one first upper-level dielectric material layer70. The at least one second upper-level dielectric material layer80may include a second via-level dielectric material layer having formed therein source connection via structures82, and a second line-level dielectric material layer having formed therein second source connection pads84. In this embodiment, the second via-level dielectric material layer may be formed, and the source contact via structures82may be formed through the second via-level dielectric material layer. The second line-level dielectric material layer may be subsequently formed over the second via-level dielectric material layer, and the second source connection pads84may be subsequently formed through the second line-level dielectric material layer on a respective one of the source connection via structures82.

Alternatively, the second via-level dielectric material layer and the second line-level dielectric material layer may be formed as a single dielectric material layer, and a dual damascene process may be performed to form integrated line and via structures. The integrated line and via structures include source-side integrated line and via structures including a respective combination of a source connection via structure82and a second source connection pad84.

Generally, upper-level dielectric material layers (70,80) may be formed over the TFT-level dielectric material layer40. Source-connection metal interconnect structures (72,74,82,84) may be formed within the upper-level dielectric material layers (70,80), which may be used to electrically connect each of the source electrodes52to a conductive node of a respective capacitor structure to be subsequently formed. Within each unit cell UC, first source-connection metal interconnect structures (72,74,82,84) may be used to provide electrical connection between a first source electrode52to a first conductive node of a first capacitor structure to be subsequently formed, and second source-connection metal interconnect structures (72,74,82,84) may be used to provide electrical connection between a second source electrode52and a second conductive node of a second capacitor structure to be subsequently formed.

Referring toFIGS.11A-11E, capacitor structures98formed within a capacitor-level dielectric material layer90may be formed. For example, first capacitor plates92may be formed on top surfaces of the second source connection pads84by deposition and patterning a first conductive material, which may be a metallic material or a heavily doped semiconductor material. Optionally, a dielectric etch stop layer89may be formed on a top surface of the second upper-level dielectric material layer80. A node dielectric94may be formed on each first capacitor plate92by deposition of a node dielectric material such as silicon oxide and/or a dielectric metal oxide (e.g., aluminum oxide, lanthanum oxide, and/or hafnium oxide). A second capacitor plate96may be formed on physically exposed surfaces of the node dielectric by deposition and pattering of a second conductive material, which may be a metallic material or a heavily doped semiconductor material.

Each contiguous combination of a first capacitor plate92, a node dielectric94, and a second capacitor plate96may constitute a capacitor structure98. A pair of capacitor structures98may be formed within each unit cell UC. Thus, a first capacitor structure98and a second capacitor structure98may be formed within each unit cell UC. A first conductive node (such as a first capacitor plate92) of the first capacitor structure98is electrically connected to an underlying first source electrode52, and a second conductive node (such as another first capacitor plate92) of the second capacitor structure98is electrically connected to an underlying second source electrode92.

Generally, the field effect transistors701located on the substrate8may be electrically connected to the various nodes of the thin film transistors formed within the TFT-level dielectric material layer40. A subset of the field effect transistors701may be electrically connected to at least one of the drain electrodes56, the first gate electrodes (comprising portions of bottom word lines15and/or as portions of top word lines35), and the second gate electrodes (comprising portions of bottom word lines15and/or as portions of top word lines35). A bottom surface of a first conductive node of a first capacitor structure98may contact a top surface of a respective one of the first source-connection metal interconnect structures (72,74,82,84). A bottom surface of a second conductive node of a second capacitor structure98may contact a top surface of a respective one of the second source-connection metal interconnect structures (72,74,82,84).

The capacitor-level dielectric material layer90may be formed over the capacitor structures98. Each of the capacitor structures98may be formed within, and laterally surrounded by, the capacitor-level dielectric material layer90, which is one of the upper-level dielectric material layers (70,80,90).

In one embodiment, each of the first capacitor plates92may be electrically connected to (i.e., electrically shorted to) a respective one of the source electrodes52. Each of the second capacitor plates96may be electrically grounded, for example, by forming an array of conductive via structures (not shown) that contact the second capacitor plates96and connected to an overlying metallic plate (not shown).

Referring toFIGS.12A-12E, a memory array region of an alternative configuration of the first exemplary structure is illustrated after formation of capacitor structures according to the first embodiment of the present disclosure. The alternative configuration of the first exemplary structure may be derived from the first exemplary structure illustrated inFIGS.12A-12Eby modifying the patterning process illustrated inFIGS.5A-5E. Specifically, a set of multiple semiconducting metal oxide plates20that are laterally spaced apart along the second horizontal direction hd2may be formed in each unit cell UC in lieu of a single semiconducting metal oxide plate20. Each semiconducting metal oxide plate20within a set of multiple semiconducting metal oxide plates20may have a respective horizontal cross-sectional shape of a rectangle or a rounded rectangle.

Thus, each source electrode52may contact end portions of top surfaces of the set of semiconducting metal oxide plates20, and each drain electrode56may contact middle portions of top surfaces of the set of semiconducting metal oxide plates20. Each gate electrode (which may comprise a portion of a bottom word line15or as a portion of a top word line35) may straddle each semiconducting metal oxide plate20within the set of semiconducting metal oxide plates20.

Referring toFIG.13, the first exemplary structure is illustrated after formation of a two-dimensional array of memory cells99over the insulating matrix layer635. Various additional metal interconnect structures (632,668) may be formed in the insulating matrix layer635, the TFT-level dielectric material layer40, and the upper-level dielectric material layers (70,80,90). The additional metal interconnect structures (632,668) may include, for example, second metal via structures632that may be formed through the insulating matrix layer635and the TFT-level dielectric material layer40on a top surface of a respective one of the second metal line structures628. Further, the additional metal interconnect structures (632,668) may include, for example, metal line structures that are formed in upper portions of the capacitor-level dielectric material layer90, which are herein referred to as sixth metal line structures668.

Additional interconnect-level dielectric material layer and additional metal interconnect structures may be subsequently formed. For example, a seventh interconnect-level dielectric material layer670embedding seventh metal line structures678and sixth metal via structures672may be formed above the capacitor-level dielectric material layer90. While the present disclosure is described using an embodiment in which seven levels of metal line structures are used, embodiments are expressly contemplated herein in which a lesser or greater number of interconnect levels are used.

Referring toFIGS.14A-14E, a second exemplary structure according to a second embodiment of the present disclosure may be derived from the first exemplary structure illustrated inFIGS.4A-4Eby omitting formation of the continuous top gate dielectric layer30C.

Referring toFIGS.15A-15E, the processing steps ofFIGS.5A-5Emay be performed in the absence of the continuous top gate dielectric layer30C to form a two-dimensional array of layer stacks of a bottom gate dielectric layer10and a semiconducting metal oxide plate20.

Referring toFIGS.16A-16E, the processing steps ofFIGS.7A-7Emay be performed with a modification in the pattern in the photoresist layer47. Specifically, the pattern in the photoresist layer47may be modified to remove the pattern of the top gate trenches34. The pattern in the photoresist layer47may be transferred through the TFT-level dielectric material layer40to form source cavities51and drain cavities59.

A pair of source cavities51may be formed over each semiconducting metal oxide plate20. Specifically, the pair of source cavities51may be formed at end portions of a respective one of the semiconducting metal oxide plates20that are laterally spaced apart along the first horizontal direction hd1. The area of each source cavity51may be entirely within the area of an underlying semiconducting metal oxide plate20. A portion of a top surface of a semiconducting metal oxide plate20may be physically exposed at the bottom of each source cavity51.

A drain cavity59may be formed over each semiconducting metal oxide plate20between the areas of a pair of bottom word lines15. A portion of a top surface of a semiconducting metal oxide plate20may be physically exposed at the bottom of each drain cavity59.

Generally, a set of cavities (51,59) may be formed through the TFT-level dielectric material layer40down to a top surface of each semiconducting metal oxide plate20. The set of cavities (51,59) may comprise, from one side to another along the first horizontal direction hd1, a first source cavity51, a drain cavity59, and a second source cavity51. The photoresist layer47may be subsequently removed, for example, by ashing.

Each portion of a first bottom word line15A having an areal overlap with an overlying semiconducting metal oxide plate20constitutes a first gate electrode, and each portion of a bottom gate dielectric10having an areal overlap with an underlying first gate electrode constitutes a first gate dielectric. Each contiguous combination of a first gate electrode and a first gate dielectric constitutes a first gate structure. Each portion of a second bottom word line15B having an areal overlap with an overlying semiconducting metal oxide plate20constitutes a second gate electrode, and each portion of a bottom gate dielectric10having an areal overlap with an underlying second gate electrode constitutes a second gate dielectric. Each contiguous combination of a second gate electrode and a second gate dielectric constitutes a second gate structure. In this embodiment, a first gate structure and a second gate structure may be formed below each semiconducting metal oxide plate20. The first gate structure and the second gate structure are laterally spaced apart along the first horizontal direction hd1. The first gate structure comprises a first gate dielectric and a first gate electrode, and the second gate structure comprises a second gate dielectric and a second gate electrode.

Referring toFIGS.17A-17E, the processing steps ofFIGS.8A-8Emay be performed to form source electrodes52and drain electrodes56. In one embodiment, each source electrode52may include a source metallic liner53and a source metallic fill material portion54. Each drain electrode56may include a drain metallic liner57and a drain metallic fill material portion58.

Generally, a first source electrode52, a drain electrode56, and a second source electrode52may be formed on a respective portion of a top surface of each semiconducting metal oxide plate20. The drain electrode56may be formed between a first gate structure (which may comprise a combination of a first bottom gate dielectric and a first bottom gate electrode), and a second gate structure (which may comprise a combination of a second bottom gate dielectric and a second bottom gate electrode). The first source electrode52is laterally spaced from the drain electrode56by the first gate structure (15A,10), and the second source electrode52is laterally spaced from the drain electrode56by the second gate structure (15A,10).

Generally, a first source electrode52, a drain electrode56, and a second source electrode52may be formed on a respective portion of a top surface of a semiconducting metal oxide plate20within each unit cell UC. The drain electrode56is formed between the first gate structure and the second gate structure. The first source electrode52is laterally spaced from the drain electrode56by the first gate structure, and the second source electrode52is laterally spaced from the drain electrode56by the second gate structure.

Referring toFIGS.18A-18E, the processing steps ofFIG.9A-9Emay be performed to form at least one first upper-level dielectric material layer70and first upper-level metal interconnect structures (72,74,76,78) over the TFT-level dielectric material layer40.

Referring toFIGS.19A-19E, the processing steps ofFIGS.10A-10Emay be performed to form at least one second upper-level dielectric material layer80and second upper-level metal interconnect structures (82,84) over the at least one first upper-level dielectric material layer70.

Generally, upper-level dielectric material layers (70,80) may be formed over the TFT-level dielectric material layer40. Source-connection metal interconnect structures (72,74,82,84) may be formed within the upper-level dielectric material layers (70,80), which may be used to electrically connect each of the source electrodes52to a conductive node of a respective capacitor structure to be subsequently formed. Within each unit cell UC, first source-connection metal interconnect structures (72,74,82,84) may be used to provide electrical connection between a first source electrode52to a first conductive node of a first capacitor structure to be subsequently formed, and second source-connection metal interconnect structures (72,74,82,84) may be used to provide electrical connection between a second source electrode52and a second conductive node of a second capacitor structure to be subsequently formed.

Referring toFIGS.20A-20E, the processing steps ofFIGS.11A-11Emay be performed to form capacitor structures98formed within a capacitor-level dielectric material layer90. Optionally, a dielectric etch stop layer89may be formed on a top surface of the second upper-level dielectric material layer80. Each contiguous combination of a first capacitor plate92, a node dielectric94, and a second capacitor plate96constitutes a capacitor structure98. A pair of capacitor structures98may be formed within each unit cell UC. Thus, a first capacitor structure98and a second capacitor structure98may be formed within each unit cell UC. A first conductive node (such as a first capacitor plate92) of the first capacitor structure98is electrically connected to an underlying first source electrode52, and a second conductive node (such as another first capacitor plate92) of the second capacitor structure98is electrically connected to an underlying second source electrode52.

Generally, the field effect transistors701located on the substrate8may be electrically connected to the various nodes of the thin film transistors formed within the TFT-level dielectric material layer40. A subset of the field effect transistors701is electrically connected to at least one of the drain electrodes56, the first gate electrodes (comprising portions of bottom word lines15and/or as portions of top word lines35), and the second gate electrodes (comprising portions of bottom word lines15and/or as portions of top word lines35). A bottom surface of a first conductive node of a first capacitor structure98may contact a top surface of a respective one of the first source-connection metal interconnect structures (72,74,82,84). A bottom surface of a second conductive node of a second capacitor structure98contacts a top surface of a respective one of the second source-connection metal interconnect structures (72,74,82,84).

The capacitor-level dielectric material layer90may be formed over the capacitor structures98. Each of the capacitor structures98may be formed within, and are laterally surrounded by, the capacitor-level dielectric material layer90, which is one of the upper-level dielectric material layers (70,80,90). In one embodiment, each of the first capacitor plates92may be electrically connected to (i.e., electrically shorted to) a respective one of the source electrodes52. Each of the second capacitor plates96may be electrically grounded, for example, by forming an array of conductive via structures (not shown) that contact the second capacitor plates96and connected to an overlying metallic plate (not shown).

Referring toFIGS.21A-21E, a memory array region of an alternative configuration of the second exemplary structure is illustrated after formation of capacitor structures according to the second embodiment of the present disclosure. The alternative configuration of the second exemplary structure may be derived from the second exemplary structure illustrated inFIGS.20A-20Eby modifying the patterning process illustrated inFIGS.15A-15E. Specifically, a set of multiple semiconducting metal oxide plates20that are laterally spaced apart along the second horizontal direction hd2may be formed in each unit cell UC in lieu of a single semiconducting metal oxide plate20. Each semiconducting metal oxide plate20within a set of multiple semiconducting metal oxide plates20may have a respective horizontal cross-sectional shape of a rectangle or a rounded rectangle.

Thus, each source electrode52may contact end portions of top surfaces of the set of semiconducting metal oxide plates20, and each drain electrode56may contact middle portions of top surfaces of the set of semiconducting metal oxide plates20. Each gate electrode (which may comprise a portion of a bottom word line15or as a portion of a top word line35) may straddle each semiconducting metal oxide plate20within the set of semiconducting metal oxide plates20.

Referring toFIGS.22A-22E, a memory array region of an alternative configuration of an exemplary structure is illustrated after formation of capacitor structures according to an embodiment of the present disclosure. The alternative configuration of the exemplary structure may be derived from any of the exemplary structures described above by forming air gaps (87,97) in dielectric material layers. For example, second upper-level metal interconnect structures (82,84) may be formed over the at least one first upper-level dielectric material layer70, and the at least one second upper-level dielectric material layer80may be subsequently deposited using at least one anisotropic dielectric material deposition process to form second upper-level air gaps87embedded within the second upper-level dielectric material layer80. Further, the capacitor-level dielectric material layer90may be formed by anisotropic deposition of a dielectric material. In this embodiment, capacitor-level air gaps97may be formed within the capacitor-level dielectric material layer90between neighboring pairs of capacitor structures98. Additional air gaps (not illustrated) may be formed in additional metal interconnect levels such as the level of the at least one first upper-level dielectric material layer70, any overlying metal interconnect level, and/or any underlying metal interconnect level.

FIG.23is a flowchart that illustrates the general processing steps for manufacturing the semiconductor device of the present disclosure. Referring to step2310andFIGS.1-5E,12A-12E, and14A-15E, a semiconducting metal oxide plate20may be formed over a substrate8.

Referring to step2320andFIGS.2A-3E,7A-8E,12A-12E, and16A-17E, a first gate structure {(15A,10) or (30A,35)} and a second gate structure {(15B,10) or (30B,35)} may be formed below or above the semiconducting metal oxide plate20. The first gate structure {(15A,10) or (30A,35)} and the second gate structure {(15B,10) or (30B,35)} are laterally spaced apart along a first horizontal direction hd1. The first gate structure {(15A,10) or (30A,35)} comprises a first gate dielectric and a first gate electrode, and the second gate structure {(15B,10) or (30B,35)} comprises a second gate dielectric and a second gate electrode.

Referring to step2330andFIGS.7A-8E,12A-12E, and16A-17E, a first source electrode52, a drain electrode56, and a second source electrode52may be formed on a respective portion of a top surface of the semiconducting metal oxide plate20. The drain electrode56is formed between the first gate structure {(15A,10) or (30A,35)} and the second gate structure {(15B,10) or (30B,35)}. The first source electrode52is laterally spaced from the drain electrode56by the first gate structure {(15A,10) or (30A,35)}, and the second source electrode52is laterally spaced from the drain electrode56by the second gate structure {(15B,10) or (30B,35)}.

Referring to step2340, a bit line78laterally extending along the first horizontal direction hd1and electrically connected to the drain electrode56may be formed.

Referring step2350, a first capacitor structure98and a second capacitor structure98may be formed. A first conductive node (such as a first capacitor plate92) of the first capacitor structure98is electrically connected to the first source electrode52, and a second conductive node (such as another first capacitor plate92) of the second capacitor structure98is electrically connected to the second source electrode52.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor device is provided, which comprises: a first thin film transistor and a second thin film transistor comprising a semiconducting metal oxide plate20located over a substrate8as a continuous material portion, and a set of electrode structures (52,15,35,56) located on the semiconducting metal oxide plate20and comprising, from one side to another along a first horizontal direction hd1, a first source electrode52, a first gate electrode (15,35), a drain electrode56, a second gate electrode (15,35), and a second source electrode52, wherein the first gate electrode (15,35) and the second gate electrode (15,35) are spaced from the semiconducting metal oxide plate20by a first gate dielectric (10or30A) and a second gate dielectric (10or30B), respectively, wherein a first portion of the semiconducting metal oxide plate20laterally extending between the first source electrode52and the drain electrode56comprises a first semiconductor channel, and wherein a second portion of the semiconducting metal oxide plate20laterally extending between the second source electrode52and the drain electrode56comprises a second semiconductor channel; a bit line78overlying the semiconducting metal oxide plate20, electrically connected to the drain electrode56, and laterally extending along the first horizontal direction hd1; a first capacitor structure98comprising a first conductive node (such as a first capacitor plate92) that is electrically connected to the first source electrode52; and a second capacitor structure98comprising a second conductive node (such as another first capacitor plate92) that is electrically connected to the second source electrode52.

In one embodiment, the substrate8comprises a single crystalline silicon substrate; lower-level dielectric material layers (601,610,620) embedding lower-level metal interconnect structures (612,618,622,628) are located between the single crystalline silicon substrate and the semiconducting metal oxide plate20; and the semiconductor device comprises field effect transistors701including a respective portion of the single crystalline silicon substrate as a channel and electrically connected to at least one of the drain electrode56, the first gate electrode (15,35), and the second gate electrode (15,35).

In one embodiment, the first gate electrode comprises a portion of a first word line (15or35) having an areal overlap with the semiconducting metal oxide plate20in a plan view (i.e., a view along the vertical direction); the second gate electrode comprises a portion of a second word line (15or35) having an areal overlap with the semiconducting metal oxide plate20in the plan view; and the first word line (15or35) and the second word line (15or35) laterally extend along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1.

In one embodiment, the field effect transistors701comprise: a first word line driver configured to apply a first gate voltage to the first word line (15or35) through a first subset of the lower-level metal interconnect structures (612,618,622,628); and a second word line driver configured to apply a second gate voltage to the second word line (15or35) through a second subset of the lower-level metal interconnect structures (612,618,622,628).

In one embodiment, the field effect transistors701comprise: a bit line driver configured to apply a bit line bias voltage to the bit line78; and a sense amplifier configured to detect electrical current that flows through the bit line78during a read operation.

In one embodiment, the semiconducting metal oxide plate20and the set of electrode structures (52,15,35,56) are formed within a TFT-level dielectric material layer40; and top surfaces of the first source electrode52, the drain electrode56, and the second source electrode52are located within a horizontal plane including a top surface of the TFT-level dielectric material layer40.

In one embodiment, the semiconductor device comprises: upper-level dielectric material layers (70,80,90) located over the TFT-level dielectric material layer40; first source-connection metal interconnect structures (72,74,82,84) formed within in the upper-level dielectric material layers (70,80,90) and electrically connecting the first source electrode52to the first conductive node (such as a first capacitor plate92) of the first capacitor structure98; and second source-connection metal interconnect structures (72,74,82,84) formed within the upper-level dielectric material layers (70,80,90) and electrically connecting the second source electrode52to the second conductive node (such as another first capacitor plate92) of the second capacitor structure98.

In one embodiment, a bottom surface of the first conductive node contacts a top surface of the first source-connection metal interconnect structures (72,74,82,84) (such as a second source connection pad84); a bottom surface of the second conductive node contacts a top surface of the second source-connection metal interconnect structures (72,74,82,84) (such as another second source connection pad84); and the first capacitor structure98and the second capacitor structure98are formed within, and are laterally surrounded by, one of the upper-level dielectric material layers (70,80,90) (such as a capacitor-level dielectric material layer90).

In one embodiment, the first gate dielectric (comprising a portion of a bottom gate dielectric layer10) contacts a first portion of a bottom surface of the semiconducting metal oxide plate20; the first gate electrode (comprising a portion of a bottom word line15) contacts a bottom surface of the first gate dielectric; the second gate dielectric (comprising another portion of a bottom gate dielectric layer10) contacts a second portion of the bottom surface of the semiconducting metal oxide plate20; and the second gate electrode (comprising portion of another bottom word line15) contacts a bottom surface of the second gate dielectric.

In one embodiment, the semiconductor device comprises: an additional first gate dielectric (such as a first top gate dielectric30A) contacting a first portion of a top surface of the semiconducting metal oxide plate20; an additional first gate electrode (such as a portion of a top word line35) contacting a top surface of the additional first gate dielectric; an additional second gate dielectric (such as a second top gate dielectric30B) contacting a second portion of the top surface of the semiconducting metal oxide plate20; and an additional second gate electrode (such as a portion of another top word line35) contacting a top surface of the additional second gate dielectric.

In one embodiment, each of the first source electrode52, the first additional gate electrode35, the drain electrode56, the second additional gate electrode35, and the second source electrode52has a respective top surface located within a horizontal plane including a top surface of a TFT-level dielectric material layer40that has formed therein the semiconducting metal oxide plate20; and each of the first source electrode52, the first additional gate electrode35, the drain electrode56, the second additional gate electrode35, and the second source electrode52comprises a combination of a respective metallic barrier liner (53,36,57) having a first material composition and a respective metallic fill material portion (54,37,58) having a second material composition.

According to an aspect of the present disclosure, a semiconductor device is provided, which comprises: a two-dimensional array of access transistor pairs located over a substrate8, wherein each of the access transistor pairs comprises a first thin film transistor and a second thin film transistor comprising a semiconducting metal oxide plate20, and a set of electrode structures (52,15,35,56) located on the semiconducting metal oxide plate20and comprising, from one side to another along a first horizontal direction hd1, a first source electrode52, a first gate electrode (comprising a portion of a first word line (15or35)), a drain electrode56, a second gate electrode (comprising a portion of a second word line (15or35)), and a second source electrode52, wherein the first gate electrode (15or35) and the second gate electrode (15or35) are spaced from the semiconducting metal oxide plate20by a first gate dielectric (10or30A) and a second gate dielectric (10or30B), respectively, wherein a first portion of the semiconducting metal oxide plate20laterally extending between the first source electrode52and the drain electrode56comprises a first semiconductor channel, and wherein a second portion of the semiconducting metal oxide plate20laterally extending between the second source electrode52and the drain electrode56comprises a second semiconductor channel; bit lines78laterally extending along the first horizontal direction hd1and electrically connected to a respective column of the drain electrode56; first word lines (15or35) laterally extending along a second horizontal direction hd2and including a respective row of the first gate electrodes as material portions therein; second word lines (15or35) laterally extending along the second horizontal hd2and including a respective row of the second source electrodes as material portions therein; and a two-dimensional array of capacitor pairs, wherein each of the capacitor pairs comprises a first capacitor structure98comprising a first conductive node (such as a first capacitor plate92) that is electrically connected to (i.e., electrically shorted to) a respective one of the first source electrodes52and a second capacitor structure98comprising a second conductive node (such as another first capacitor plate92) that is electrically connected to a respective one of the second source electrodes52.

In one embodiment, the substrate8comprises a single crystalline silicon substrate; lower-level dielectric material layers (601,610,620) having formed therein lower-level metal interconnect structures (612,618,622,628) are located between the single crystalline silicon substrate and the semiconducting metal oxide plate20; and the semiconductor device comprises field effect transistors701including a respective portion of the single crystalline silicon substrate as a channel and electrically connected to at least one of the drain electrode56, the first gate electrode, and the second gate electrode.

In one embodiment, the field effect transistors701comprise: first word line drivers configured to apply a first gate voltage to a respective one of the first word lines (15or35) through a respective subset of the lower-level metal interconnect structures (612,618,622,628); second word line drivers configured to apply a second gate voltage to a respective one of the second word lines (15or35) through a respective subset of the lower-level metal interconnect structures (612,618,622,628); bit line drivers configured to apply a bit line bias voltage to a respective one of the bit lines78; and a sense amplifier circuit configured to detect electrical current that flows through the bit lines78during a read operation.

The various embodiments of the present disclosure uses thin film transistors as access transistors for a capacitor structure in a dynamic random access memory cell. Further, a pair of thin film transistors are merged such that a common portion of a semiconducting metal oxide plate20is used to provide electrical contact to a common drain node, which may comprise a drain electrode56contacting a center portion of the semiconducting metal oxide plate20. Further, use of field effect transistors701using portions of a single crystalline silicon layer as channel regions provides vertical stacking of a peripheral circuit, access transistors, and capacitor structures. Thus, a high density array of random access memory cells may be provided using the various embodiments of the present disclosure.