Processing device mounted in an image sensing apparatus having a memory storing information on possible configurations of a logic circuit

A detachable processing device that is mounted in an image sensing apparatus, integrated, and used by the device includes a logic circuit that can be changed to a plurality of configurations, which implement functions corresponding to a plurality of processes performed by the image sensing apparatus, a memory that stores possible configurations of the logic circuit, and a controller that controls the configuration of the logic circuit on the basis of the logical configurations stored in the memory.

FIELD OF THE INVENTION

The present invention relates to a detachable processing device which is mounted and used in an image sensing apparatus, and an image sensing apparatus.

BACKGROUND OF THE INVENTION

A conventional digital camera processes, within its main body, image information obtained from an image sensing element, converts the image information into image data, and saves the image data on a recording medium. As the recording medium, detachable recording media, such as a rewritable flash memory card are often used.

A conventional digital camera of this type executes an image process in only its main body, and a large part of the image process is defined by hardware in the main body. Even if the user is not satisfied with the image performance of the camera, the hardware cannot be exchanged.

To solve this problem, there is proposed a method of implementing some of the functions of the hardware configuration by software (computer program) and after the user purchases a camera, separately updating the program into the camera (see, e.g., Japanese Patent Application Laid-Open No. 2000-324430).

However, when a new hardware process or image processing method is developed and the camera cannot deal with it by only altering the program in the main body, the user has to buy a new camera.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above situation, and has as its object to easily improve the function of an image sensing apparatus without changing the image sensing apparatus itself.

According to the present invention, the foregoing object is attained by providing a processing device that is mounted in an image sensing apparatus, integrated, and used by the camera, comprising: a logic circuit that can be changed to a plurality of configurations which implement functions corresponding to a plurality of processes performed by the image sensing apparatus; a memory that stores configuration information indicative of possible configurations of the logic circuit; and a controller that controls the configuration of the logic circuit on the basis of the configuration information stored in the memory.

According to the present invention, the foregoing object is also attained by providing an image sensing apparatus comprising: a connection unit that can integrally mount the above-discussed processing device; and a display unit that displays that some of processes of the image sensing apparatus are executed by the processing device when the processing device is mounted.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described in detail in accordance with the accompanying drawings. However, the dimensions, shapes and relative positions of the constituent parts shown in the embodiment should be changed as convenient depending on various conditions and on the structure of the apparatus adapted to the invention, and the invention is not limited to the embodiment described herein.

FIG. 1is a block diagram showing the functional arrangement of a camera according to the embodiment of the present invention.FIG. 2is a perspective view showing the rear surface of the camera shown inFIG. 1. An outline of operation of each part of the camera according to the embodiment will be described.

In using the camera, a memory card111or a processor card121is inserted into a card slot202of a camera main body101, as shown inFIG. 2. The opening/closing state of a card slot cover204is detected by an open/close sensor203. The memory card111and the processor card121receive necessary power from the camera main body101.

An image is not recorded by only the camera main body101in the embodiment, but may be recorded by only the main body101.

<Camera Operation when Memory Card is Mounted>

An operation when the memory card111is mounted in the camera main body101will be explained.

When the user inserts the memory card111into the card slot202of the camera main body101, a connector109of the camera main body101and a connector112of the memory card111are connected.

The camera main body101is controlled by a CPU103; the CPU103performs control in accordance with an executable code written in advance in a non-volatile memory (FROM)102. In control, the CPU103uses a rewritable memory (DRAM)104as a work area. The user executes an image sensing operation with a keyboard (KEY)108. The open/close sensor203inFIG. 2is part of the circuit of the KEY108. The signal of the KEY108is read by the CPU103to perform a predetermined image sensing operation. The camera main body101comprises a liquid crystal display device (LCD)107as a user interface, and the display is controlled by the CPU103in an image sensing operation. The CPU103can determine the power supply state of the camera main body101as needed.

When the user designates the start of image sensing with the KEY108, the CPU103controls a CCD signal processing unit (DSP)105to expose an image sensing element (CCD)106. Image data obtained by image sensing is temporarily saved in a specific area of the DRAM104. This image data corresponds to the exposure amount of each pixel of the CCD106, and will be called RAW data.

The CPU103reads out RAW data stored in the DRAM104, sequentially converts them into a compression recording format, and transmits the compressed data to a controller (CTRL)113in the memory card111connected via the connector109. The CTRL113stores the compressed data in a non-volatile memory (FROM)114.

The above-described operation is executed by the camera main body101and the memory card111in correspondence with one image sensing operation.

When the user designates playback of image data with the KEY108, the CPU103controls the CTRL113in the memory card111, reads out compressed image data obtained by image sensing from the FROM114, and transfers the image data to the DRAM104while performing an expansion process corresponding to the compression. The CPU103then displays the expanded data in the DRAM104on the LCD107. The user can see the image data displayed on the LCD107.

<Camera Operation when Processor Card is Mounted>

An operation when the processor card121is inserted into the card slot202will be explained.

As shown inFIG. 2, in the embodiment, the processor card121is equal in thickness, width, and length to the memory card111, and can be inserted into the card slot202similarly to the memory card111. The user can discriminate the processor card121from the memory card111by their appearances because the upper surface of the processor card121has a wavy metal radiation plate.

The processor card121has a connector122which is identical in electrical characteristic and shape to the connector112. The processor card121includes a reconfigurable logic circuit (RECONF)123, a controller (CTRL)124for the RECONF123, non-volatile memories (FROMs)125and128, and rewritable memories (DRAMs)126and127.

The RECONF123can freely change the configuration of its logic circuit by the CTRL124.

Data necessary for determine the logical configuration of the RECONF123is saved in the FROM128, and if necessary, the CTRL124reads out the data from the FROM128to determine the logical configuration of the RECONF123. The data of the FROM128can also be externally rewritten via the connector122.

The operation of the processor card121will be described with reference to the flowchart ofFIG. 3.

The processor card121is inserted into the card slot202of the camera main body101, and the connector122is connected to the connector109(step S301). Power is supplied from the camera main body101and the processor card121is initialized.

Immediately after activation, the RECONF123in the processor card121is initialized into a configuration as shown inFIG. 4in step S302. In the embodiment, the configuration shown inFIG. 4will be called configuration1. A CPU401is a processor configured by the RECONF123, and is connected to the CTRL124and FROM128via a signal bus402which is simultaneously configured.

After the setting of the logical configuration, the CTRL124notifies the CPU401and CPU103of the end of setting of the logical configuration. At this time, the CPU401communicates with the CPU103to receive power data DPW suppliable from the camera main body101.

If the control processor CPU103of the camera main body101detects by the open/close sensor203serving as part of the KEY108that any device has been connected to the connector109, the CPU103transmits a model recognition code representing a camera model name to the connected device. In step S303, the processor card121determines whether the model recognition code has been received. If the processor card121corresponds to the model recognition code, the CPU401receives it and responds to it. The memory card111described above does not correspond to the model recognition code, and does not send back any response. By this response process, the CPU103can determine whether the connected device is the memory card111or the processor card121. At the same time, the CPU401can detect the model of the connected camera main body101. Even if no model recognition code can be received after the lapse of a predetermined time since the card is inserted, the CPU401determines that the connected camera is an old model which does not correspond to the model recognition code, and the flow advances to step S320.

In step S304, it is determined whether the power data DPW received in step S302is smaller than a predetermined value. If YES in step S304, the CPU401determines that the processes in steps S305to S311to be described later cannot be performed, and the flow advances to step S320for low-power operation.

If NO in step S304, the flow advances to step S305, and the CPU401communicates with the CPU103. If the user designates image sensing with the KEY108, the flow advances to step S306; if the user does not designate image sensing (in this case, playback is assumed to be designated), to step S330.

In step S306, the CPU401compares the model recognition code received in step S303and information written in advance in the FROM128to recognize an image sensing operation of the camera main body101. In the embodiment, the camera main body101performs exposure, the RAW data process, conversion into a recording format, and writing in the FROM, as described above. In correspondence with this flow, the CPU401reads out configuration data from the FROM128and sends it to the CTRL124. Then, the CTRL124changes the logical configuration of the RECONF123. The changed logical configuration is shown inFIG. 5(configuration2).

The configuration inFIG. 5is a logical configuration specialized in the RAW data process. This configuration can perform a process at a higher speed than the above-mentioned RAW data process which is executed within the camera main body101ofFIG. 1. In order to realize a high-speed process, the configuration corresponding to the DSP105inFIG. 1is multiplexed by changing the logical configuration of a signal processing unit DSP502having double the performance. A CPU501and a signal bus503, which correspond to communication with the DSP502, are logically configured. Similar to the CPU401, the CPU501performs control in accordance with an executable code written in advance in the FROM128. The CPU501performs necessary control for the DSP502. The DSP502can directly read out an executable code and data from the FROM128, as needed. Most part of the band of the signal bus503is used for a signal process by the DSP502.

After the setting of the logical configuration, the CTRL124notifies the CPU501and CPU103of the end of setting of the logical configuration.

The CPU103displays on the LCD107a message that the processor card121performs a RAW data process in step S307to be described later. From this display, the user can recognize that a higher-speed signal process of a higher speed than a process performed by only the camera main body101is performed by the processor card121. The user can also grasp the camera state and reflect it in an image sensing operation.

If the user designates the start of image sensing by operating the KEY108, the CPU103starts exposing the CCD106, similar to the operation when the memory card111is mounted. When the memory card111is mounted, the DSP105executes the RAW data signal process. In this case, however, the DSP105does not perform any process, and RAW data is sent to the processor card121via the signal connectors and then to the DSP502via the signal bus503. The DSP502executes the RAW data process (step S307), and saves RAW data in the DRAM127. The DRAM127has a higher speed and larger capacity than those of the DRAM104. At this time, part of the image process may be properly assisted by the CPU103and the DSP105in accordance with the performance.

After the end of the RAW data process, the DSP502notifies the CPU501, the CTRL124, and the CPU103of the end of the process.

In response to the end of the RAW data process, the CPU501reads out configuration data from the FROM128and sends it to the CTRL124. Then, the CTRL124changes the logical configuration of the RECONF123(step S308). The changed logical configuration is shown inFIG. 6(configuration3).

The configuration inFIG. 6is a logic circuit configuration specializing in the conversion of RAW data into a recording data format. In this configuration, a DSP602is an image processing circuit dedicated to conversion into the recording data format. The DSP602is connected to the DRAM126via a signal bus603and to the DRAM127via a signal bus604. A CPU601is a processor specializing in control of the DSP602, and is connected to the FROM128, the CTRL124, and the CPU103via a signal bus605. The CPU601performs control in accordance with an operation code written in advance in the FROM128. The CPU601and the DSP602are connected by a control bus606, and the CPU601controls the DSP602.

After the setting of the logical configuration, the CTRL124notifies the CPU601and the CPU103of the end of setting of the logical configuration.

The CPU103displays on the LCD107a message that the processor card121performs an image compression process in step S309to be described later. From this display, the user can recognize that a higher-speed signal process of a higher speed than a process performed by only the camera main body101is performed by the processor card121. The user can also grasp the camera state and reflect it in image sensing operation.

The DSP602reads out RAW data generated by the RAW data process in step S307from the DRAM127, sequentially performs a data compression process, and saves the compressed data in the DRAM126(step S309). The compression method is not particularly limited, and may be lossless compression or lossy compression. Part of the image process may be properly assisted by the CPU103in accordance with the performance.

After the end of the image compression process, the DSP602notifies the CPU601, the CTRL124, and the CPU103of the end of the process.

In response to the end of the image compression process, the CPU601reads out configuration data from the FROM128and sends it to the CTRL124. Then, the CTRL124changes the logical configuration of the RECONF123(step S310). The changed logical configuration is shown inFIG. 7(configuration4).

The configuration inFIG. 7is a logic circuit configuration specializing in writing of compressed image data in the FROM125. In this configuration, a DSP702is a processing circuit dedicated to writing compressed image data in the FROM125at a high speed. The DSP702is connected to the DRAM126via a signal bus704and to the FROM125via a signal bus703. A CPU701is a processor specializing in control of the DSP702, and is connected to the FROM128, the CTRL124, and the CPU103via a signal bus706. The CPU701performs control in accordance with an operation code written in advance in the FROM128. The CPU701and the DSP702are connected by a control bus705, and the CPU701controls the DSP702.

After the setting of the logical configuration, the CTRL124notifies the CPU701and the CPU103of the end of setting of the logical configuration.

The CPU103displays on the LCD107a message that the processor card121performs writing in the FROM in step S311to be described later. From this display, the user can recognize that a higher-speed signal process of a higher speed than a process performed by only the camera main body101is performed by the processor card121. The user can also grasp the camera state and reflect it in image sensing operation.

The DSP702reads out image data compressed in step S309, sequentially performs a write data process, and saves the compressed data in the FROM125(step S311). Part of the data process may be properly assisted by the CPU103in accordance with the performance.

After the end of the data write process, the DSP702notifies the CPU701, the CTRL124, and the CPU103of the end of the process.

The CPU103determines whether the user tries to continue the image sensing operation by using the KEY108. In step S312, the CPU701communicates with the CPU103. If image sensing is determined to end, the process ends; if image sensing is determined to continue, the process returns to step S306to repeat the above process.

If it is determined in step S303that no model recognition code can be received even upon the lapse of a predetermined time after the processor card121is inserted, or if it is determined in step S304that the received power data DPW is smaller than a predetermined value, the CPU401of configuration1shown inFIG. 4communicates with the CPU103of the camera main body101, and the camera main body101measures the read/write rate via the connector109in step S320. The measurement result is used in steps S322and S330to be described later.

In step S321, similar to step S305, the CPU401communicates with the CPU103and determines whether the user designates image sensing with the KEY108. If the user designates image sensing, the flow advances to step S322; if the user does not designate image sensing (in this case, playback is assumed to be designated), to step S330.

In step S322, the CPU401reads out configuration data from the FROM128and sends it to the CTRL124. Then, the CTRL124changes the logical configuration of the RECONF123. The changed logical configuration is shown inFIG. 8(configuration5). The logic circuit inFIG. 8is the same as the above-described logic circuit in the memory card111, and a CTRL801is an equivalent circuit to the CTRL113. The CTRL801is connected to the FROM125and saves image data in the FROM125(step S323).

The CTRL801is optimized for the read/write rate measured in step S320, and can write data at the maximum write rate of the FROM125. Operation by the logic circuit changed in step S322is the same as operation by the memory card111when viewed from the camera main body101.

In step S324, similar to step S312, the CPU801communicates with the CPU103, and determines whether to end image sensing. If image sensing is determined to end, the process ends; if image sensing is determined to continue, the process returns to step S323to repeat the above process.

If it is determined in step S305or S321that no image sensing is designated (in this case, playback is designated), the process advances to step S330to change the logical configuration into that of configuration5shown inFIG. 8, similar to step S321. Also at this time, the CTRL801is optimized for the read rate measured in step S320, and can read out data at the maximum read rate of the FROM125. Operation by the logic circuit changed in step S330is the same as operation by the memory card111when viewed from the camera main body101.

In step S331, the same operation as playback operation upon mounting the memory card111is performed.

The CPU103determines whether the user tries to continue playback operation by using the KEY108. In step S332, the CPU801communicates with the CPU103. If playback is determined to end, the process ends; if playback is determined to continue, the process returns to step S331to repeat the above process.

As has been described above, according to the embodiment, a general-purpose digital camera which is widely used at present can be easily used as a high-grade convertible model by only inserting into the digital camera a processor card which can execute a process of the digital camera at a higher speed.

CLAIM OF PRIORITY

This application claims priority from Japanese Patent Application No. 2004-194297 filed on Jun. 30, 2004, which is hereby incorporated by reference herein.