DISPLAY APPARATUS, DISPLAY PANEL AND METHOD OF PREPARING THE SAME

The present disclosure provides a display apparatus, a display panel and a method of preparing the same. A display panel includes: a base substrate; and a plurality of light-emitting units provided on the base substrate, where each of the light-emitting units includes a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode which are stacked, the first electrode is provided on a side of the second electrode facing away from the base substrate, and the plurality of light-emitting units share a common first electrode. The present disclosure can improve display resolution.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, and in particular to a display apparatus, a display panel and a method of preparing the same.

BACKGROUND

With the development of science and technology, display technology has attracted more and more attention. Conventional display apparatuses have low display resolution.

SUMMARY

An object of the present disclosure is to provide a display apparatus, a display panel and a method of preparing the same, which can improve display resolution.

According to an aspect of the present disclosure, there is provided a display panel including:a base substrate; anda plurality of light-emitting units provided on the base substrate, where each of the light-emitting units includes a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode which are stacked, the first electrode is provided on a side of the second electrode facing away from the base substrate, and the plurality of light-emitting units share a common first electrode.

Further, the display panel further includes:an isolation structure, at least part of the isolation structure being located between adjacent two of the light-emitting units, and a surface of the isolation structure facing away from the base substrate being further away than a surface of each light-emitting layer facing away from the base substrate in a thickness direction of the base substrate.

Further, the isolation structure is provided on the base substrate and includes a plurality of openings: the plurality of light-emitting units are provided one-to-one in the plurality of openings; and the first electrode is provided on a side of the isolation structure facing away from the base substrate.

Further, the first semiconductor layers of the plurality of light-emitting units are arranged in a same layer and are of a monolithic structure, and the first semiconductor layers are provided on the surface of the isolation structure facing away from the base substrate.

Further, a refractive index of the isolation structure is the same as that of the first semiconductor layers.

Further, a spacing area is between portions of adjacent two of the light-emitting units other than the first electrode, and a recess is formed in a portion of the first electrode corresponding to the spacing area; and the isolation structure is provided on a side of the first electrode facing away from the base substrate, and located in the recess.

Further, the isolation structure includes a retro-reflective material.

Further, the second electrode is bonded to the base substrate via a metal bonding layer.

Further, the display panel further includes:

a light extraction structure provided on a light-exiting side of the light-emitting layer.

Further, a surface of the first electrode facing away from the base substrate is a roughened surface that forms the light extraction structure: or

a surface of the first semiconductor layer facing away from the second semiconductor layer is a roughened surface that forms the light extraction structure.

Further, the display panel further includes:a light condenser unit provided on the first electrode in an area corresponding to the light-emitting layer.

Further, a surface of the light condenser unit facing away from the first electrode is a curved surface, and protrudes towards a direction away from the base substrate.

Further, the first semiconductor layers include a common film layer and a plurality of protrusions, where the plurality of protrusions are provided one-to-one on surfaces of the light-emitting layers of the plurality of light-emitting units facing away from the second semiconductor layer, and the common film layer is provided on a side of the plurality of protrusions facing away from the second semiconductor layer.

Further, a ratio of a thickness of each of the protrusions to a thickness of the common film layer is ¼ to ½.

Further, the display panel further includes:a metal grid provided on a side of the first electrode facing away from the base substrate and connected with the first electrode, where the metal grid includes a plurality of holes corresponding to the light-emitting units one-to-one, and an orthographic projection of each light-emitting layer onto the base substrate is located within an area of an orthographic projection of a respective hole of the metal grid onto the base substrate.

Further, the display panel includes a display area and a peripheral area surrounding the display area, the plurality of light-emitting units being located in the display area, and the display panel further includes:a connecting wire provided on the base substrate and located in the peripheral area, where the metal grid is electrically connected with the connecting wire.

Further, the base substrate is a silicon-based substrate.

According to an aspect of the present disclosure, there is provided a method of preparing a display panel, including:providing a base substrate; andforming a plurality of light-emitting units on the base substrate, where each of the light-emitting units includes a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode which are stacked, the first electrode is provided on a side of the second electrode facing away from the base substrate, and the plurality of light-emitting units share a common first electrode.

Further, the method further includes:forming an isolation structure, where at least part of the isolation structure is located between adjacent two of the light-emitting units, and a surface of the isolation structure facing away from the base substrate is further away than a surface of each light-emitting layer facing away from the base substrate in a thickness direction of the base substrate.

Further, the isolation structure is provided on the base substrate and includes a plurality of openings: the plurality of light-emitting units are provided one-to-one in the plurality of openings; and the first electrode is formed on a side of the isolation structure facing away from the base substrate.

Further, forming the plurality of light-emitting units on the base substrate includes:sequentially forming the first semiconductor layer, the light-emitting layer, and the second semiconductor layer on a support plate;forming a first etching trench and a plurality of first retention units arranged at intervals by a patterning process, where the first etching trench is disposed around the first retention units, and a distance between a bottom surface of the first etching trench and the support plate is less than or equal to a thickness of the first semiconductor layer;bonding the first retention units and the base substrate via a metal bonding layer that forms the second electrode, and removing the support plate; and forming the first electrode.

Further, the distance between the bottom surface of the first etching trench and the support plate is greater than zero and less than the thickness of the first semiconductor layer, the first semiconductor layers include a common film layer and a plurality of protrusions, where the plurality of protrusions are provided one-to-one on surfaces of the light-emitting layers of the plurality of light-emitting units facing away from the second semiconductor layer, and the common film layer is provided on a side of the plurality of protrusions facing away from the second semiconductor layer.

Further, forming the plurality of light-emitting units on the base substrate includes:sequentially forming the first semiconductor layer, the light-emitting layer, and the second semiconductor layer on a support plate;bonding the second semiconductor layer and the base substrate via a metal bonding layer that forms the second electrode;removing the support plate and forming a second etching trench and a plurality of second retention units arranged at intervals by a patterning process, where the second etching trench is disposed around the second retention units, and a bottom surface of the second etching trench is the base substrate; and forming the first electrode.

According to an aspect of the present disclosure, there is provided a display apparatus including the display panel.

With the display apparatus, the display panel and the method of preparing the same according to the present disclosure, a light-emitting unit includes a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode which are stacked, that is, the light-emitting unit is of a vertical structure, such that the number of light-emitting units on the base substrate can be increased, and in turn the display resolution of the display panel can be improved. Moreover, since a plurality of light-emitting units share a common first electrode, the preparation process can be simplified.

DESCRIPTION OF REFERENCE NUMERALS

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numerals in different drawings indicate the same or similar elements, unless otherwise indicated. Embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of the present disclosure as detailed in the appended claims.

Terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Unless otherwise defined, technical or scientific terms used in the present disclosure shall have their ordinary meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. Terms “first,” “second,” and the like as used in the specification and claims of the present disclosure do not imply any order, quantity, or importance, but are merely used to distinguish one component from another. Similarly, terms “a” or “an” and the like do not denote a limitation on quantity, but rather denote the presence of at least one. “A plurality of” or “several” means two or more. Unless otherwise indicated, terms “front,” “rear,” “lower,” and/or “upper” and the like are for the purpose of illustration only and are not limited to one position or spatial orientation. Terms “including” or “comprising” and the like are intended to mean that elements or items preceding “including” or “comprising” are intended to encompass elements or items listed after “including” or “comprising.” and equivalents thereof, and are not intended to exclude other elements or items. Terms “connected” or “coupled” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in the specification of the present disclosure and the appended claims, the singular forms of “a.” “an,” “the,” and “said” are intended to include plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term “and/or” as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items. Embodiments of the present disclosure provide a display panel. As shown inFIGS.7,13,15and16, the display panel may include a base substrate1and a plurality of light-emitting units2.

The plurality of light-emitting units2are provided on the base substrate1. Each of the light-emitting units2includes a first electrode201, a first semiconductor layer202, a light-emitting layer203, a second semiconductor layer204, and a second electrode205which are stacked. The first electrode201is located on a side of the second electrode205facing away from the base substrate1. The plurality of light-emitting units2share a common first electrode201.

With the display panel according to embodiments of the present disclosure, a light-emitting unit2includes a first electrode201, a first semiconductor layer202, a light-emitting layer203, a second semiconductor layer204, and a second electrode205which are stacked, that is, the light-emitting unit2is of a vertical structure. Compared to a light-emitting unit with a horizontal structure, the present disclosure can increase the number of light-emitting units2on the base substrate1, and in turn improve the display resolution of the display panel. Moreover, since a plurality of light-emitting units share a common first electrode201, the preparation process can be simplified.

Components of the display panel according to embodiments of the present disclosure will be described in detail below.

The base substrate1may be a glass substrate or, of course, a polyimide substrate. In other embodiments, the base substrate1may be a silicon-based substrate, which can improve the thermal conductivity and electrical conductivity of the base substrate1and facilitate the subsequent preparation of a plurality of film layers. Meanwhile, the silicon-based substrate has a low cost, which can also reduce the preparation cost. The base substrate1may be provided with a pixel driving circuit. The pixel driving circuit may include a driving transistor and a switching transistor connected to the driving transistor. The switching transistor may be a CMOS (Complementary Metal Oxide Semiconductor) transistor. The display panel may include a display area100and a peripheral area200surrounding the display area100(seeFIG.14). The pixel driving circuit as described above may be located in the display area100. Furthermore, the base substrate1is provided with a connection structure101on a surface thereof. The connection structure101is electrically connected to a source or drain of the driving transistor.

The light-emitting unit2may be located in the display area100(seeFIG.14). The light-emitting unit2may be a light-emitting diode, or the like. The light-emitting unit2includes a first electrode201, a first semiconductor layer202, a light-emitting layer203, a second semiconductor layer204, and a second electrode205which are stacked. The first electrode201is located on a side of the second electrode205facing away from the base substrate1. The second electrode205may be bonded to the base substrate1, such that the second electrode205is electrically connected to the connection structure101, and in turn electrically connected to the source or drain of the driving transistor. The second electrode205may be bonded to the base substrate1via a metal bonding layer. The first semiconductor layer202may have a different conductivity type than the second semiconductor layer204. For example, the first semiconductor layer202is an n-type semiconductor layer and the second semiconductor layer204is a p-type semiconductor layer. For another example, the first semiconductor layer202is a p-type semiconductor layer and the second semiconductor layer204is an n-type semiconductor layer. Both the first semiconductor layer202and the second semiconductor layer204may include GaN. The light-emitting layer203may be a quantum well layer. In an embodiment, the first electrode201is a cathode and the second electrode205is an anode. In another embodiment, the first electrode201is an anode and the second electrode205is a cathode.

As shown inFIG.7, second electrodes205of the plurality of light-emitting units2may be arranged at intervals. Second semiconductor layers204of the plurality of light-emitting units2may be arranged at intervals. Light-emitting layers203of the plurality of light-emitting units2may be arranged at intervals. First semiconductor layers202of the plurality of light-emitting units2may be arranged at intervals (seeFIG.13). However, the first semiconductor layers202of the plurality of light-emitting units2are arranged in the same layer and are of a monolithic structure (seeFIG.7), that is, the light-emitting layers203of the plurality of light-emitting units2are connected to a common first semiconductor layer202, which can improve the uniformity of electric current in the first semiconductor layers202of the plurality of light-emitting units2after power on, and in turn improve the light-emitting uniformity of the plurality of light-emitting units2. The plurality of light-emitting units2may share a common first electrode201, that is, the first electrodes201of the plurality of light-emitting units2are arranged in the same layer and are of a monolithic structure.

For example, in the case that the first semiconductor layers202of the plurality of light-emitting units2are arranged in the same layer and are of a monolithic structure, the first semiconductor layers202may include a common film layer2021and a plurality of protrusions2022, as shown inFIG.5. The plurality of protrusions2022are disposed one-to-one on surfaces of the light-emitting layers203facing away from the second semiconductor layers204. The common film layer2021is disposed on a side of the plurality of protrusions2022facing away from the second semiconductor layers204. A ratio of a thickness L2of the protrusion2022to a thickness L1of the common film layer2021may be ¼ to ½. An orthographic projection of any one of the light-emitting layer203, the second semiconductor layer204, and the second electrode205onto the base substrate1has the same shape as and completely overlaps with an orthographic projection of the protrusion2022onto the base substrate1. A shape of the orthographic projection of the light-emitting layer203onto the base substrate1may be a square, a rectangle, a circle, or the like. For example, in the case that the shape of the orthographic projection of the light-emitting layer203onto the base substrate1is a square, a side length of the square may be 5 μm, or the like.

As shown inFIG.7, the display panel according to the present disclosure may further include an isolation structure3. The isolation structure3and the light-emitting units2may be located on the same side of the base substrate1. At least part of the isolation structure3is located between adjacent two of the light-emitting units2. The isolation structure3may be disposed around each of the light-emitting units2so as to separate any two adjacent light-emitting units2from each other. In a thickness direction of the base substrate1, a surface of the isolation structure3facing away from the base substrate1is further away than a surface of each light-emitting layer203facing away from the base substrate1, that is to say, the surface of the isolation structure3facing away from the base substrate1is located on a side of the light-emitting layers203away from the base substrate1. In this way, light crosstalk between adjacent two of the light-emitting layers203can be reduced through the isolation structure3.

In an embodiment of the present disclosure, as shown inFIG.7, the isolation structure3may be disposed on the base substrate1and include a plurality of openings. The plurality of light-emitting units2are disposed one-to-one in the plurality of openings, and the first electrode201shared by the plurality of light-emitting units2may be disposed on a side of the isolation structure3facing away from the base substrate1. Further, in the case that the plurality of light-emitting units2share a common first semiconductor layer202for example, the first semiconductor layer202may also be disposed on the surface of the isolation structure3facing away from the base substrate1. The isolation structure3may be made of a transparent colloidal material. A refractive index of the isolation structure3may be different from that of the first semiconductor layer202. However, a refractive index of the isolation structure3may be the same as that of the first semiconductor layer202. In this way, light loss due to the difference in the refractive index between the isolation structure3and the first semiconductor layer202can be reduced. For example, in the case that the refractive index of the isolation structure3is the same as that of the first semiconductor layer202, the refractive index of the isolation structure3may be greater than or equal to 2. However, the isolation structure3may also include a retro-reflective material, that is, the isolation structure3is a retro-reflective structure to reflect light incident to the isolation structures3. The retro-reflective material included in the isolation structure3may have a reflectivity greater than 60%. The retro-reflective material may be an epoxy resin material, such as white glue.

In another embodiment of the present disclosure, as shown inFIGS.15and16, the first semiconductor layers202of the plurality of light-emitting units2may be arranged at intervals, the light-emitting layers203of the plurality of light-emitting units2may be arranged at intervals, the second semiconductor layers204of the plurality of light-emitting units2are arranged at intervals, and the second electrodes205of the plurality of light-emitting units2are arranged at intervals. That is, a spacing area is between portions of adjacent two of the light-emitting units2other than the first electrode201. The first electrode201may extend into the spacing area, such that a recess is formed in a portion of the first electrode201corresponding to the spacing area. The isolation structure3may be provided on a side of the first electrode201facing away from the base substrate1and located in the recess. The isolation structure3may include a retro-reflective material, such as white glue. That is to say, the isolation structure3is a retro-reflective structure to reflect light incident to the isolation structure3.

As shown inFIG.15, the display panel according to the embodiment of the present disclosure may further include a light extraction structure7. The light extraction structure7may be provided on a light-exiting side of the light-emitting layer203. A surface of the first electrode201facing away from the base substrate1may be a roughened surface6which may form the light extraction structure7. In this way, when light emitted from the light-emitting layer203arrives at the roughened surface6, total reflection of the light can be reduced, and the reduced light extraction efficiency caused by the total reflection of the light can be solved. An area of the surface of the first electrode201facing away from the base substrate1corresponding to the light-emitting layer203may have a roughened surface6, but is not limited thereto. An entire area of the surface of the first electrode201facing away from the base substrate1may have a roughened surface6. As shown inFIG.6andFIG.7, a surface of the first semiconductor layer202facing away from the second semiconductor layer204may also be a roughened surface6which forms a light extraction structure7. In this way, when light emitted from the light-emitting layer203arrives at the roughened surface6, total reflection of the light can be reduced, and the reduced light extraction efficiency caused by the total reflection of the light can be solved. An area of the surface of the first semiconductor layer202facing away from the second semiconductor layer204corresponding to the light-emitting layer203may have a roughened surface6, but is not limited thereto. An entire area of the surface of the first semiconductor layer202facing away from the second semiconductor layer204may have a roughened surface6.

As shown inFIG.16, the display panel according to the embodiment of the present disclosure may further include a light condenser unit10. The light condenser unit10may be provided on the first electrode201in an area corresponding to the light-emitting layer203, and the light condenser unit10is configured to condense light emitted from the light-emitting layer203. A surface of the light condenser unit10facing the first electrode201may be adhered to the first electrode201, a surface of the light condenser unit10facing away from the first electrode201is a curved surface, and the surface of the light condenser unit10facing away from the first electrode201protrudes towards a direction away from the base substrate1. A boundary of the surface of the light condenser unit10facing the first electrode201may be connected to a boundary of the surface of the light condenser unit10facing away from the first electrode201. A shape of an orthographic projection of the light condenser unit10onto the base substrate1may be a circle, a diameter of which may be 5 μm, or the like. For example, in the case that the shape of the orthographic projection of the light-emitting layer203onto the base substrate1is a square, the diameter of the circular orthographic projection of the light condenser unit10onto the base substrate1may be the same as the side length of the orthographic projection of the light-emitting layer203. The maximum thickness L3of the light condenser unit10in the thickness direction of the base substrate1is 2.5 μm, or the like.

As shown inFIG.7,FIG.13, andFIG.14, the display panel according to the embodiment of the present disclosure may further include a metal grid4. The metal grid4may be provided on a surface of the first electrode201facing away from the base substrate1, that is, the metal grid4is connected to the first electrode201. The metal grid4includes a plurality of holes corresponding to the plurality of light-emitting units2one-to-one. The orthographic projection of each light-emitting layer203onto the base substrate1is located within an area of an orthographic projection of a respective hole of the metal grid4onto the base substrate1, that is, orthographic projections of grid lines of the metal grid4onto the base substrate1are spaced apart from orthographic projections of the light-emitting layers203onto the base substrate1, such that not only a resistance of the first electrode201can be reduced and a voltage drop (IR drop) across the first electrode201can be reduced, but also the shading of light emitted from the light-emitting layer203by the metal grid4can be reduced due to the fact that an orthographic projection of the metal grid4onto the base substrate1is disposed around orthographic projections of the light-emitting layers203onto the base substrate1. The metal grid4has a relatively low resistivity. The display panel according to the embodiment of the present disclosure may further include a connecting wire8. The connecting wire8is provided on the base substrate1and may be located in the peripheral area200of the display panel. The connecting wire8may extend along the periphery of the display area100to surround the display area100, i.e., the connecting wire8is in the shape of a ring. The metal grid4may be electrically connected to the connecting wire8. For example, in the case that the first electrode201is a cathode, the connecting wire8may be a cathode ring.

The present disclosure further provides a method of preparing a display panel, which is used for preparing the display panel according to any one of the above embodiments. The method of preparing the display panel may include steps S100to S110.

At step S100, as shown inFIG.1, a base substrate1is provided.

At step S110, as shown inFIG.7andFIG.13, a plurality of light-emitting units2are formed on the base substrate1. Each of the light-emitting units2includes a first electrode201, a first semiconductor layer202, a light-emitting layer203, a second semiconductor layer204, and a second electrode205which are stacked, where the first electrode201is located on a side of the second electrode205facing away from the base substrate1, and the plurality of light-emitting units2share a common first electrode201.

The display panel prepared by the method of preparing the display panel according to the present disclosure is the same as the display panel according to the above embodiments, and thus has the same beneficial effects as the display panel according to the above embodiments, which will not be repeated herein.

In an embodiment of the present disclosure, the above step S110may include steps S1101A to S1104A.

At step S1101A, as shown inFIG.2, a first semiconductor layer202, a light-emitting layer203, and a second semiconductor layer204are sequentially formed on a support plate5.

According to the present disclosure, the first semiconductor layer202, the light-emitting layer203, and the second semiconductor layer204may be sequentially formed on the support plate5through an epitaxial growth process. The support plate5may be made of Si, but the present disclosure is not limited thereto.

At step S1102A, as shown inFIG.3, a first etching trench11and a plurality of first retention units12arranged at intervals are formed by a patterning process, the first etching trench11being disposed around the first retention units12.

The patterning process may be a photolithography process, or the like. A distance between a bottom surface of the first etching trench11and the support plate5may be equal to a thickness of the first semiconductor layer202. That is, the sum of a thickness of the light-emitting layer203and a thickness of the second semiconductor layer204is equal to a depth of the first etching trench11. However, the distance between the bottom surface of the first etching trench11and the support plate5may be greater than zero and less than the thickness of the first semiconductor layer202. That is, the light-emitting layer203formed in step S1101A is over-etched in the present disclosure, which can ensure that the light-emitting layer203is completely etched in a thickness direction of the support plate5, thereby simplifying the etching process. In other embodiments of the present disclosure, the bottom surface of the first etching trench11may be the support plate5. For example, in the case that the distance between the bottom surface of the first etching trench11and the support plate5is greater than zero and less than or equal to the thickness of the first semiconductor layer202, the plurality of first retention units12are arranged at intervals, and the first etching trench11is disposed around the first retention units12, that is, each of the first retention units12retains a portion of the second semiconductor layer204and a portion of the light-emitting layer203. The first semiconductor layers202may include a common film layer2021and a plurality of protrusions2022. The plurality of protrusions2022are disposed one-to-one on surfaces of the plurality of light-emitting layers203facing away from the second semiconductor layer204. The common film layer2021is disposed on a side of the plurality of protrusions2022facing away from the second semiconductor layer204. A ratio of a thickness L2of the protrusion2022to a thickness L1of the common film layer2021is ¼ to ½.

An orthographic projection of the first retention unit12onto the support plate5may be in the shape of a square, a rectangle, a circle, or the like. For example, in the case that an orthographic projection of the first retention unit12onto the support plate5is in the shape of a square, a side length of the square may be 5 μm, or the like. Further, the plurality of first retention units12arranged at intervals may be distributed in an array.

At step S1103A, as shown inFIG.4, the first retention unit12is bonded to the base substrate1via a metal bonding layer15, and the support plate5is removed. The metal bonding layer15forms the second electrode205.

For example, step S1103A may include forming a first bonding layer on surfaces of the first retention units12, forming a second bonding layer on the base substrate1, and bonding the first bonding layer and the second bonding layer to form the metal bonding layer15. The bonding process may adopt eutectic bonding or, of course, thermocompression bonding. In the eutectic bonding process, both the first bonding layer and the second bonding layer may be of a bimetallic layer structure, such as Cu/Sn or Au/In. In the thermocompression bonding process, both the first bonding layer and the second bonding layer may be of a monometallic layer structure, such as Au, Cu, or Al.

At step S1104A, as shown inFIG.7, the first electrode201is formed.

The first electrode201may be formed by evaporation.

In another embodiment of the present disclosure, step S110may include steps S1101B to S1104B.

At step S1101B, as shown inFIG.2, a first semiconductor layer202, a light-emitting layer203, and a second semiconductor layer204are sequentially formed on a support plate5.

According to the present disclosure, the first semiconductor layer202, the light-emitting layer203, and the second semiconductor layer204may be sequentially formed on the support plate5through an epitaxial growth process. The support plate5may be made of Si, but the present disclosure is not limited thereto. The first semiconductor layer202may have a different conductivity type than the second semiconductor layer204. For example, the first semiconductor layer202is an n-type semiconductor layer and the second semiconductor layer204is a p-type semiconductor layer. For another example, the first semiconductor layer202is a p-type semiconductor layer and the second semiconductor layer204is an n-type semiconductor layer. Both the first semiconductor layer202and the second semiconductor layer204may include GaN. The light-emitting layer203may be a quantum well layer.

At step S1102B, as shown inFIG.8, the second semiconductor layer204and the base substrate1are bonded via a metal bonding layer15, which forms the second electrode205.

For example, step S1102B may include forming a first bonding layer on a surface of the second semiconductor layer204, forming a second bonding layer on the base substrate1, and bonding the first bonding layer and the second bonding layer to form the metal bonding layer15. Both the first bonding layer and the second bonding layer may be of a bimetallic layer structure, such as Cu/Sn or Au/In. It should be noted that at step S1102B, the first bonding layer covers an entire surface area of the second semiconductor layer204, and the second bonding layer covers an entire surface area of the base substrate1, such that the bonding strength can be improved.

At step S1103B, as shown inFIG.9, the support plate5is removed, and a second etching trench13and a plurality of second retention units14arranged at intervals are formed by a patterning process. The second etching trench13is disposed around the second retention units14, and a bottom surface of the second etching trench13is the base substrate1.

For example, in the case that the support plate5is made of Si, the support plate5may be removed by an acidic etching solution such as HF (Hydrogen Fluoride) in the present disclosure. The patterning process may be a photolithography process or the like. The bottom surface of the second etching trench13may be the base substrate1. That is, the sum of a thickness of the first semiconductor layer202, a thickness of the light-emitting layer203, a thickness of the second semiconductor layer204, and a thickness of the metal bonding layer15is equal to a depth of the second etching trench13. The plurality of second retention units14are arranged at intervals, and the second etching trench13is disposed around the second retention units14. That is, each of the second retention units14retains a portion of the first semiconductor layer202, a portion of the second semiconductor layer204, a portion of the light-emitting layer203, and a portion of the second electrode205.

As shown inFIG.10, an orthographic projection of the second retention unit14onto the base substrate1may be in the shape of a square, a rectangle, a circle, or the like. For example, in the case that an orthographic projection of the second retention unit14onto the base substrate1is in the shape of a square, a side length of the square may be 5 μm, or the like. Further, the plurality of second retention units12arranged at intervals may be distributed in an array. After step S1103B, the present disclosure may further include step S1104B of forming the first electrode201as shown inFIG.13.

The method of preparing the display panel according to the present disclosure may further include forming the above-described isolation structure3. For example, in the case that the isolation structure3is disposed between the base substrate1and the first electrode201, as shown inFIG.6, the isolation structure3may be formed after the above step S1103A and before the above step S1104A. However, as shown inFIG.12, the isolation structure3may be formed after step S1103B and before step S1104B. As shown inFIG.15andFIG.16, in the case that the isolation structure3is disposed on the side of the first electrode201facing away from the base substrate1, for example, the isolation structure3may be formed after the formation of the first electrode201. It should be noted that inFIGS.15and16, an insulating layer9may be formed before the first electrode201is formed. The insulating layer9covers side surfaces of the first semiconductor layer202, the light-emitting layer203, the second semiconductor layer204, and the second electrode205, and is provided with a window exposing a top surface of the first semiconductor layer202. The first electrode201is in contact with the first semiconductor layer202through the window.

The method of preparing the display panel according to the present disclosure may further include forming the above-described light extraction structure7. For example, in the case that the first semiconductor layer202has the above-described roughened surface6, as shown inFIGS.5and11, the surface of the first semiconductor layer202may be roughened with an alkaline solution before the first electrode201is formed in the present disclosure, in order to form the roughened surface6. For example, in the case that the first electrode201has the above-described roughened surface6, as shown inFIG.15, the surface of the first electrode201may be patterned through a photolithography process after the first electrode201is formed in the present disclosure, in order to form the roughened surface6.

After forming the first electrode201, as shown inFIG.7andFIG.13, the method of preparing the display panel according to the present disclosure may further include forming the above-described metal grid4and connecting wire8.

After forming the first electrode201, as shown inFIG.16, the method of preparing the display panel according to the present disclosure may further include forming the above-described light condenser unit10. The light condenser unit10may be formed by dispensing adhesive.

Embodiments of the present disclosure further provide a display apparatus. The display apparatus may include the display panel according to any one of the above embodiments. Since the display panel in the display apparatus according to the embodiments of the present disclosure is the same as the display panel according to the above embodiments, it has the same beneficial effects as the display panel according to the above embodiments, which will not be repeated herein.

The foregoing are merely preferred embodiments of the present disclosure, and are not intended to limit the present disclosure in any form. Although the present disclosure has been disclosed as above in the preferred embodiments, they are not intended to limit the present disclosure. Any person of skill in the art, without departing from the scope of the technical solutions of the present disclosure, may make some changes or modifications into equivalent embodiments with equivalent changes by using the above disclosed technical contents. Any simple variations, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure, without deviating from the contents of the technical solutions of the present disclosure, still fall within the scope of the technical solutions of the present disclosure.