Frequency multiplier for a phase-locked loop

The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

TECHNICAL FIELD

This application relates generally to frequency multipliers, including frequency multipliers for phased-locked loops (PLLs).

BACKGROUND

A phase-locked loop (PLL) is used to establish and maintain a phase relationship between a generated output signal and an input reference signal. To provide such functionality, a PLL includes a variable frequency oscillator to generate the output signal and a phase detector to compare the phase of the output signal to the phase of the reference signal. Based on the comparison, the PLL adjusts the variable frequency oscillator to establish and maintain the phase relationship between the output signal and the reference signal. Once the phase relationship between the two signals becomes substantially constant in time (a result of which is that the input reference signal and the output signal frequencies are equal), the PLL is said to be “in lock.”

Often, rather than comparing the phase of the output signal directly to the phase of the reference signal, a frequency divider is used to first reduce the frequency of the output signal by a division factor to generate a comparison signal. The phase detector then compares the phase of the comparison signal to the phase of the reference signal and any adjustment needed to the variable frequency oscillator is made based on this comparison. The use of a frequency divider results in the frequency of the output signal being generated with a frequency that is multiple times greater than the frequency of the reference signal by an amount equal to the division factor.

A PLL has several figures of merit that are used to characterize its performance. Often, one of the more important PLL figures of merit is output phase noise. All ideal PLL generates an output signal with a single tone at a desired frequency. For such an ideal PLL, the spectrum of the output signal assumes the shape of an impulse. In practice, phase noise is seen in the spectrum of the output signal as random fluctuations or “skirting” around the impulse. For many applications, phase noise in the output signal can have a negative impact on performance.

In communication systems that use a PLL output signal to down-convert a signal, this phase noise can corrupt the resulting frequency translated signal. For example, in a received signal, a desired channel centered at a frequency ω0can be spaced very close to a strong undesired channel centered at a frequency ω0−ΔΩ. To down-convert the desired channel to baseband, the PLL can be configured to provide an output signal with a frequency equal to the center frequency ω0of the desired channel, and the two signals can be mixed.

In the ideal ease, the PLL output signal consists of a single tone, with no phase noise, at the frequency ω0, and only the desired channel is down-converted to baseband. In practice, the PLL output signal includes phase noise around the single tone at ω0. This phase noise further mixes with the received signal and, if the bandwidth of the phase noise is larger than the distance separating the two channels (i.e., larger than Δω), the strong undesired channel will be down-converted to baseband where it will interfere with the desired channel and reduce the sensitivity of the communication system.

One way in which the phase noise of a can be reduced is by increasing the frequency of the reference signal. A higher frequency reference signal allows for a smaller division factor to be used by the frequency divider, As described above, the division factor has the effect of multiplying the frequency of the reference signal to produce the output signal at a higher frequency. In the process, the phase noise of the reference signal is also multiplied. Thus, even though the reference signal is typically generated by a crystal oscillator with low phase noise, high-levels of noise multiplication due to a large division factor can still cause the reference signal phase noise to degrade the phase noise of the output signal.

Increasing the frequency of the reference signal allows for a decrease in the division factor and a corresponding decrease in phase noise from the reference signal in the output signal. At the same time, a higher frequency reference signal enables a higher loop bandwidth, which can reduce phase noise contributions from the variable frequency oscillator of the PLL in the output signal. A higher frequency reference signal can also provide for a lower quantization noise from the PLL divider (e.g., from a PLL divider implemented using a sigma-delta modulator).

To achieve a higher frequency reference signal, a crystal oscillator that produces a reference signal at a higher frequency can be used, but such a solution is typically costly. Another approach is to use a frequency doubler to increase the frequency of the reference signal by a factor of two. Conventional methods of doubling the frequency of the reference signal rely on duty-cycle correction circuits to first correct the duty-cycle of the reference signal provided by a crystal oscillator to be 50%. The duty-cycle of a signal is the percentage of a cycle of the signal in which the signal is “active” or high. The problem with duty-cycle correction circuits is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal. These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL.

In general, a crystal oscillator provides a reference signal at a stable frequency and with low levels of phase noise but often with a duty cycle that is not 50%. The duty-cycle correction circuits are used because, without a 50% duty-cycle reference signal, a frequency doubler will typically produce a frequency doubled version of the reference signal with a constant duty-cycle variation and period variation between adjacent cycles. As a result of these variations, edges (either rising or falling) of the frequency doubled reference signal that are used as reference points by a PLL phase detector to measure phase error in the PLL output signal will deviate from their ideal positions and cause a periodic inaccuracy in the measured phase error.

FIG. 1illustrates an example frequency doubler100that can be used to double the frequency of a reference signal. As shown inFIG. 1, frequency doubler100includes a delay element102and an exclusive-OR gate104. Delay element102is configured to delay a reference signal106with a stable frequency and low phase noise to produce a delayed reference signal108. Exclusive-OR gate104is then configured to exclusive-OR the reference signal106and the delayed reference signal108to produce a reference signal110with double the frequency of reference signal106.

A waveform diagram112is further provided inFIG. 1to illustrate the operation of frequency doubler100when reference signal106does not have a 50% duty-cycle (i.e., TH/TH+TL)≠0.5). As can be seen from waveform diagram112, when reference signal106does not have a 50% duty-cycle, frequency doubler100produces frequency doubled reference signal110with a constant duty-cycle variation and period variation between adjacent cycles. More specifically, between adjacent cycles1and2in frequency doubled reference signal110, there is an apparent duty-cycle variation and period variation. This same duty-cycle variation and period variation also occurs between all other subsequent adjacent cycles, including cycles3and4and cycles5and6shown in waveform diagram112.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be apparent to those skilled in the art that the disclosure, including structures, systems, and methods, may be practiced without these specific details. The description and representation herein are the common means used by those experienced or skilled in the art to most effectively convey the substance of their work to others skilled in the art. In other instances, well-known methods, procedures, components, and circuitry have not been described in detail to avoid unnecessarily obscuring aspects of the disclosure.

For purposes of this discussion, the term “module” shall be understood to include software, firmware, or hardware (such as one or more circuits, microchips, processors, and/or devices), or any combination thereof. In addition, it will be understood that each module can include one, or more than one, component within an actual device, and each component that forms a part of the described module can function either cooperatively or independently of any other component forming a part of the module. Conversely, multiple modules described herein can represent a single component within an actual device. Further, components within a module can be in a single device or distributed among multiple devices in a wired or wireless manner.

As discussed above, a conventional frequency doubler uses a duty-cycle correction circuit to correct the duty-cycle of a reference signal to be 50% before doubling the frequency of the reference signal. The duty-cycle correction circuit is used because, without a 50% duty-cycle reference signal, a frequency doubler will typically produce a frequency doubled version of the reference signal with a constant duty-cycle variation and period variation between adjacent cycles. As a result of these variations, edges (either rising or falling) of the frequency doubled reference signal that are used as reference points by a PLL phase detector to measure phase error in the PLL output signal will deviate from their ideal positions and cause a periodic inaccuracy in the measured phase error.

The problem with duty-cycle correction circuits used by conventional frequency doublers is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal. These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL.

Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL divider to compensate for the measured period error.

In one embodiment, the apparatus and method of the present disclosure use one or more counters to count the number of cycles of the output signal that occur during each cycle of two adjacent cycles of the frequency doubled reference signal or, alternatively, the number of cycles of the output signal that occur during each of the high and low portions of a cycle of the reference signal. One-half the difference between the count values is used as a measure of the period error between adjacent cycles of the frequency doubled reference signal.

In another embodiment, the apparatus and method of the present disclosure integrates a sequence of one-bit values (after they have been normalized as explained further below) that each indicate whether a cycle of the frequency doubled reference signal leads or lags a corresponding cycle of the output signal after the output signal has been reduced in frequency by the PLL frequency divider. The integrated value is used as a measure of the period error between adjacent cycles of the frequency doubled reference signal in terms of cycles of the output signal.

Before further describing these and other features of the present disclosure, an exemplary operating environment in which embodiments of the present disclosure can be implemented is provided in the following section.

2. Exemplary Operating Environment

FIG. 2illustrates an example PLL200in which embodiments of the present disclosure can be implemented. In general, PLL200is used to generate an output signal202having a desired output frequency from a reference signal204having a given reference frequency. PLL200includes a phase detector206, a loop filter208, a variable frequency oscillator210(e.g., a voltage controlled oscillator or a digitally controlled oscillator), and a fractional divider212.

In operation, fractional divider212generates a comparison signal214based on output signal202. Specifically, fractional divider212reduces the frequency of output signal202by a fractional division factor N.f, where N is the integer portion and f is the fractional portion of the fractional division factor N.f, to generate comparison signal214. This reduction in frequency allows output signal202to be generated at a desired frequency that is N.f times greater than the frequency of input signal204. The fractional division factor of fractional divider212can be adjusted to adjust the frequency of output signal202to a desired value.

Phase detector206generates a control signal218based on the difference in phase between reference signal204and comparison signal214. In a digital implementation, phase detector206can be a time-to-digital converter or a bang-bang phase detector, for example. For a bang-bang phase detector implementation, control signal218indicates whether comparison signal214is leading or lagging reference signal204, but generally does not include information as to the magnitude of the difference in phase between reference signal204and comparison signal214.

Loop filter208low-pass filters control signal218to produce a filtered control signal220. Filtered control signal220is then applied to variable frequency oscillator210to correct for any phase error between reference signal204and comparison signal214to either maintain PLL200in a locked state or to bring PLL200into a locked state.

One possible implementation of fractional divider212is shown inFIG. 2. In particular, fractional divider212is shown as being implemented by a multi-modulus divider (MMD)222and a modulator224. In operation, MMD222reduces the frequency of output signal202using two or more integer division factors to generate comparison signal214. MMD222is specifically controlled by the sum of the output of modulator224and an integer word230(that represents the integer portion N of the fractional division factor N.f) to alternately select the different integer division factors of MMD222in such a way that the frequency of output signal202is reduced on average by the fractional division factor N.f.

Modulator224can include at least one accumulator (not shown) for causing the integer division factors of MMD222to be alternately selected in this way. The accumulator can be clocked by comparison signal214and incremented by an amount determined by a fractional word226(that represents the fractional portion f of the fractional division factor N.f) with each pulse of comparison signal214. Assuming MMD222is implemented as a dual-modulus divider that reduces the frequency of output signal202by either the integer division factor N or N+1, when the accumulator overflows, modulator224can use the output or modulator224to adjust the integer division factor of MMD222to be set to N+1 for one cycle of comparison signal214and to the integer division factor N at all other times. One way in which modulator224can accomplish this functionality is by setting the output of modulator224equal to the carry out of its accumulator.

For example, if the fractional division factor N.f of fractional divider212is 5.2, modulator224can control MMD222to alternately switch between the integer division factors of five and six such that comparison signal214has an average frequency that is 5.2 times slower than the frequency of output signal202. Modulator224can specifically control MMD222using the output of modulator224to use the integer division factor five for four consecutive pulses of comparison signal214and then switch to the integer division factor six for the next pulse of comparison signal214. This integer division factor selection sequence (i.e., 5, 5, 5, 5, 6) can then be repeated thereafter. As can be verified, this integer division factor selection sequence will provide comparison signal214with an average frequency that is 5.2 times slower than the frequency of output signal202.

To control MMD222to alternately select between the integer division factors of five and six according to the integer division factor selection sequence noted above, fractional word226can be appropriately set. For example, assuming that the modulus of the accumulator a modulator224is equal to five, then fractional word226can be set equal to one to provide the desired control of MMD222. Setting the fractional word226equal to one means that, for each pulse of comparison signal214, the accumulator of modulator224increments by one and, for every five pulses of comparison signal214, the accumulator overflows. Thus, setting fractional word226to one causes MMD222to tae the integer division factor of five for four pulses of comparison signal214and then, when the accumulator of modulator224overflows on the fifth pulse of comparison214, switch to the integer division factor of six for the fifth pulse of comparison signal214as desired.

FIG. 3provides a signal waveform300that further illustrates the operation of MMD222and modulator224. Signal waveform300assumes, for illustration purposes, that the fractional division factor N.f of fractional divider212is equal to 5.2, that MMD222is a dual-modulus divider with two integer division factors of live and six, and that mode224includes as single accumulator with a modulus of five and receives as input a fractional word226with a value of one as described above.

As can be seen from signal waveform300, the use of integer division factors by the MMD222that are not exactly equal to the fractional division factor of 5.2 introduces phase noise into comparison signal214. The phase noise of comparison signal214increases during accumulation of fractional word226by the accumulator value of modulator224and then is reduced back down to zero (in at least this example) when the accumulator overflows. Because of the periodic nature and abrupt changes in the phase noise of the comparison signal214, spurs can be introduced into the frequency domain of output signal202depending on the bandwidth of loop filter208.

It should be noted that, in other implementations of fractional divider212, MMD222can include more than two division factors and modulator224each be implemented as a second-order or higher sigma-delta modulator instead of an accumulator. A second-order or higher sigma-delta modulator combined with an MMD that provides more than two integer division factors can be used to further randomize the integer division factor selection sequence in such a way that the spur causing noise is translated to a higher-frequency that is more easily filtered by loop filter208.

3. Frequency Multiplier for a PLL with

Referring now toFIG. 4A, a frequency synthesizer400is illustrated in accordance with embodiments of the present disclosure. Frequency synthesizer400includes a PLL with the same structure as PLL200described above in regard toFIG. 2as well as a frequency doubler402and a counter based period error detector404.

Frequency doubler402is configured to double the frequency of reference signal204to provide a frequency doubled reference signal406. Frequency doubled reference signal406allows for a decrease in the fractional division factor N.f of fractional divider212and a corresponding decrease in phase noise in output signal202from reference signal204. At the same time, frequency doubted reference signal406enables a higher loop bandwidth, which can further reduce phase noise in output signal202from variable frequency oscillator210.

Frequency doubler402doubles the frequency of reference signal204using a circuit, such as the circuit of frequency doubler100inFIG. 1. As discussed above, a conventional frequency doubler uses a duty-cycle correction circuit to correct the duty-cycle of a reference signal, such as reference signal204, to be 50% before doubling the frequency of the reference signal. The duty-cycle correction circuit is used because, without a 50% duty-cycle reference signal, a frequency doubler will typically produce a frequency doubled version of the reference signal with a constant duty-cycle variation and period variation between adjacent cycles. As a result of these variations, edges (either rising or falling) of the frequency doubled reference signal that are used as reference points by a PLL phase detector to measure phase error in the PLL output signal will deviate from their ideal positions and cause a periodic inaccuracy in the measured phase error.

The problem with duty-cycle correction circuits used by conventional frequency doublers is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal. These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL.

Rather than directly correct the duty-cycle of reference signal204, frequency synthesizer400uses counter based period error detector404to measure the period error between adjacent cycles of frequency doubled reference signal406in terms of cycles of output signal202and adjust the fractional division factor N.f of fractional divider212to compensate for the measured period error408.

A waveform diagram is shown to the bottom right of frequency synthesizer400inFIG. 4Athat illustrates a cycle of reference signal204and a corresponding pair of adjacent cycles of frequency doubled reference signal406. As can be seen from the waveform, the adjacent cycles of frequency doubled reference signal406have different periods (i.e., different time durations). Counter based period error detector404includes one or more counters that count the respective number of cycles of output signal202that occur during each of the adjacent cycles of frequency doubled reference signal406(with some quantization error). Because the adjacent cycles of frequency doubled reference signal406ideally should have the same period, half the difference between the two count values provides a measure of the period error of each adjacent cycle of the frequency doubled reference signal406. More specifically, the absolute value of half the difference between the two count values specifies how much the shorter of the two adjacent cycles should be increased by in duration and how much the longer of the two adjacent cycles should be decreased by in duration in order for the two adjacent cycles to have substantially equal periods.

To compensate for the difference in period between the two adjacent cycles, measured period error408(equal to the absolute value of half the difference between the two count values) can be used to adjust the division factor of fractional divider212. In particular, for the shorter of the two adjacent cycles, measured period error408can be subtracted from integer word230and, for the longer of the two adjacent cycles, measured period error408can be added to integer word230, where integer word230represents the integer portion N of the fractional division factor of fractional divider212, in order to add and subtract measured period error408in the manner above, counter based error detector404can ping-pong between providing measured period error408as a negative and positive value.

By changing the integer portion N of the fractional division factor N.f of fractional divider212in this way, the period of comparison signal214is effectively being changed or modulated to compensate for the period variation in frequency doubled reference signal406. As a result, the edges (either rising or falling) of frequency doubled reference signal406that are used as reference points by phase detector206to measure a difference in phase between comparison signal214and frequency doubled reference signal406, and that deviate from their ideal positions because of the period variation between adjacent cycles of the frequency doubled reference signal406, will not cause (or at least not to the same extent) a periodic inaccuracy in control signal218.

It should be noted that, prior to outputting measured period error408, measured period error408can be further gain adjusted by counter based period error detector404and/or filtered by counter based period error detector404based on previous values of measured period error408determined from earlier occurring pairs of adjacent cycles of frequency doubled reference signal406. For example, counter based period error detector404can low-pass filter measure period error408.

It should be further noted that counter based error detector404can alternatively determine the measured period error408based on reference signal204as opposed to frequency doubled reference signal406. More specifically, counter based period error detector404can use its one or more counters to count the respective number of cycles of output signal202that occur during each of the high and low portions of the cycle of reference signal204that corresponds to the two adjacent cycles of frequency doubled reference signal406. As shown in the waveform to the bottom right of frequency synthesizer400inFIG. 4A, the high and low portions of the cycle of reference signal204can respectively have the same duration as the corresponding two adjacent cycles of frequency doubled reference signal406. This alternative applies to other embodiments of counter based period error detector404shown in the figures discussed below, including counter based period detectors504and604, as well as bang bang based period error detector702shown inFIG. 7.

Finally, it should be noted that PLL structure200used in frequency synthesizer400is provided by way of example and not limitation. One of ordinary skill in the art will recognize the other PLL structures can be used with frequency doubler402and counter based period error detector404. For example, in the implementation of fractional divider212shown inFIG. 4A, the measured period error408is used as a frequency domain correction factor. In other implementations of fractional divider212, the measured period408can be used as a phase domain correction factor as will be appreciated by one of ordinary skill in the art. Such an implementation, is shown inFIG. 4B. In particular, frequency synthesizer450has a similar configuration as frequency synthesizer400inFIG. 4A, but with the general exception of a modified fractional divider452and an additional integrator454. Integrator454integrates the entire division factor N.f456and adds the integrated division factor, which is a phase domain value, to measured period error408. The resulting sum is then used as input to a sigma delta modulator458. The output of sigma delta modulator458is used by edge selector460to provide a pulse or cycle of comparison signal214with a desired phase value. In general, edge selector460can provide a pulse or cycle of comparison signal214with any one of a plurality of different phase values as determined by the output of sigma delta modulator458. It will be appreciated by one of ordinary skill in the art that the fractional dividers of the other frequency synthesizers described below can be similarly modified to operate in the phase domain.

Referring now toFIG. 5, another frequency synthesizer500is illustrated in accordance with embodiments of the present disclosure. Frequency synthesizer500has a similar structure as frequency synthesizer400inFIG. 4Abut includes a delay line502and a counter based period error detector504that has slightly modified functionality from counter based period error detector404.

Similar to how frequency synthesizer400inFIG. 4Auses counter based period error detector404, frequency synthesizer500uses counter based period error detector504to measure the period error between adjacent cycles of frequency doubled reference signal406and adjust the division factor of fractional divider212to compensate for the measured period error408. However, unlike counter based period error detector404, which measures the period error between adjacent cycles of frequency doubled reference signal406in terms of cycles of output signal202, counter based period error detector504is configured to measure the period error between adjacent cycles of frequency doubled reference signal in terms of a higher frequency clock signal than output signal202. Using a higher frequency clock can improve the accuracy of the period error measurement by reducing quantization noise.

In the embodiment ofFIG. 5, frequency synthesizer500is specifically configured to measure the period error between adjacent cycles of frequency doubled reference signal406using both rising and falling edges of output signal202, effectively doubling the frequency of output signal202.

Counter based period error detector504includes one or more counters that count the respective number of rising and falling edges of output signal202that occur during each of the adjacent cycles of frequency doubled reference signal406. Because the adjacent cycles of frequency doubled reference signal406ideally should have the same period, half the difference between the two count values provides a measure of the period error of each adjacent cycle in terms of half-cycles of output signal202. More specifically. the absolute value of half the difference between the two count values specifies much the shorter of the two adjacent cycles should be increased by in duration and how much the longer of the two adjacent cycles should be decreased by in duration in order for the two adjacent cycles to have substantially equal periods.

To compensate tor the difference in period between the two adjacent cycles, a coarse measured period error506equal to the integer part of the absolute value of the difference between the two count values divided by four and a fine measured period error508equal to the fractional part of the absolute value of the difference between the two count values divided by two are provided as output. In particular, coarse measured period error506can be used to adjust the division factor of fractional divider212. For the shorter of the two adjacent cycles, coarse measured period error506can be subtracted from integer word230and, for the longer of the two adjacent cycles, coarse measured period error506can be added to integer word230, where integer word230represents the integer portion N of the fractional division factor N.f of fractional divider212. In order to add and subtract coarse measured period error506in the manner above, counter based error detector504can ping-pong between providing coarse measured period error506as a negative and positive value.

Fine measured period error508can be used to adjust delay line502to delay the output of fractional divider212by an integer number of half-cycles of output signal202determined based on the value of fine measured period error508. Delay line502can be implemented, for example, as a flip-flop based delay line, with the flip-flops clocked by both the rising and falling edges of output signal202. It other embodiments, delay line502can be implemented using, in addition to or as an alternative to flip-flops, inverters and/or buffers. The inverters or buffers can be used to provide for a resolution finer than a half-cycle of output signal202.

Referring now toFIG. 6, another frequency synthesizer600is illustrated in accordance with embodiments of the present disclosure. Frequency synthesizer600has a similar structure as frequency synthesizer400inFIG. 4Abut includes a prescaler602, a counter based period error detector604that has slightly modified functionality from counter based period error detector404, and a delay line606.

Prescaler602is configured to pre-divide output signal202by an integer amount before output signal202is processed by fractional divider212. A prescaler, such as prescaler602, is typically used to extend the upper frequency range at which a PLL can produce an output signal. Prescaler602can pre-divide output signal202by a factor of two, four, or eight, for example.

Counter based period error detector604is configured to function in the same manner as counter based period error detector404described above inFIG. 4Abut output a measured period error in a slightly different format to account for the effects of prescaler602. In particular, counter based period error detector604is configured to output a coarse measured period error608to adjust the fractional division factor N.f of fractional divider212. Coarse measured period error608is the same as measured period error408but divided (or effectively divided) by the division factor used by prescaler602.

Any resulting remainder of the division can optionally be used as a fine measured period error610. Fine measured period error610can be used to adjust a delay line606to delay the output of fractional divider212by an integer number of cycles of output signal202determined based on the value of fine measured period error610to provide comparison signal214. Delay line606can be implemented, for example, as a flip-flop based delay line, with the flip-flops clocked by output signal202. In other embodiments, delay line606can be implemented using, in addition to or as an alternative to flip-flops, inverters and/or buffers that can provide for a finer resolution.

Counter based error detector604can ping-pong between providing coarse measured period error508as a negative and positive value in a similar manner that counter based error detector404inFIG. 4Aprovides measured period error408.

Referring now toFIG. 7, another frequency synthesizer700is illustrated in accordance with embodiments of the present disclosure. Frequency synthesizer700has a similar structure as frequency synthesizer400inFIG. 4Abut includes a bang bang based period error detector702as opposed to a counter based period error detector.

Bang bang based period error detector702is configured to measure the period error between adjacent cycles of frequency doubled reference signal406in terms of cycles of output signal202and adjust the division factor of fractional divider212to compensate for the measured period error704. Bang bang based period error detector702includes a bang bang phase detector (BBPD) that compares the phase of frequency doubled reference signal406to the phase of comparison signal214and provides an output (e.g., a one-bit output) that indicates whether a cycle of the frequency doubled reference signal leads or lags a corresponding cycle of comparison signal214in phase. Bang bang based period error detector702integrates the output of the BBPD and uses the integrated value as a measured period error704(i.e., a measure of the period error between adjacent cycles of frequency doubled reference signal406in terms of cycles of output signal202). The integration can also include other forms of filtering and gain adjustment.

Before integrating the output of the BBPD, the output can be effectively “normalized” based on whether the output of the BBPD was generated for the shorter or the longer of the two adjacent cycles of frequency doubled reference signal406. For example, and in one embodiment, the output of the BBPD can be multiplied by +1 if the output of the BBPD was generated for the shorter of the two adjacent cycles of frequency doubled reference signal406and multiplied by −1 if the output of the BBPD was generated for the longer of two adjacent cycles of frequency doubled reference signal406.

To compensate for the difference in period between the two adjacent cycles, measured period error704can be used in adjust the fractional division factor N.f of fractional divider212. In particular, for the shorter of the two adjacent cycles, measured period error704can be subtracted from integer word230and, for the longer of the two adjacent cycles, measured period error704can be added to integer word230, where integer word230represents the integer portion N of the fractional division factor of fractional divider212. In order to add and subtract measured period error704in the manner above, bang bang based error detector702can ping-pong between providing measured period error704as a negative and positive value.

It should be noted that, in a PLL implementation where PD206is implemented as a BBPD, bang bang based period error detector702can be implemented without its own BBPD and use the output of PD206instead as would be appreciated by one of ordinary skill in the art based on the teachings herein.

It should be noted that the frequency synthesizers illustrated inFIGS. 4-7and described above all use a frequency doubler to increase the frequency of the reference signal to a PLL. As will be appreciated by one of ordinary skill in the art based on the teachings herein, the embodiments of the apparatus and method of the present disclosure described above can be readily extended and used in frequency synthesizers that increase the frequency of the reference signal by more than a factor of two. In such instances, the counter based period error detector or bang bang based error detector can determine the relative period errors between adjacent cycles of the increased frequency reference signal and similarly adjust the division factor of the PLL divider to compensate for any variations.