Startup circuit and method

A startup circuit provides a single connection to a node of a reference or other circuit to be started. The startup circuit injects high current into devices to start a reference circuit. The startup circuit provides strong current invention during startup, and low power consumption during operation.

FIELD

The present invention relates generally to startup circuits and in particular the present invention relates to low power startup circuits.

BACKGROUND

Reference voltages are needed in equipment such as power supplies, current supplies, panel meters, calibration standards, data conversion systems, and the like. Bandgap reference circuits are typically chosen to produce reference voltages due to their ability to maintain stable output voltages that vary little with temperature and supply voltage.

A typical bandgap reference circuit10is shown inFIG. 1. Circuit10includes an amplifier11and a bandgap voltage generator12. The output of the bandgap reference circuit (at node Vbgr) stabilizes according to the following equation:

In equation (1), the first term on the right hand side has a negative temperature coefficient, while the second term on the right had side has a positive temperature coefficient. An almost zero temperature coefficient can be obtained by setting a proper ratio between the first and the second terms on the right had side of the equation.

An intrinsic problem with a bandgap reference circuit such as circuit10is that it has two stable states. A first stable state is the normal operational state, where Vbgr is equal to about 1.25 Volts (V). The second stable state is the zero-current state, where Vbgr is equal to 0 and Vbias is equal to 0.

To prevent the reference circuit10from staying in the zero-current state, a startup circuit, such as startup circuit23shown inFIG. 2, is normally added to the bandgap reference circuit. The startup circuit may include a resistor and several diode-connected n-channel metal oxide semiconductor field effect transistors (NMOSFETs). In circuit23, the voltage at terminal24is higher than Vt1+Vt2, where Vt1and Vt2are the threshold voltages of transistors18and19, respectively. This ensures that Vbias, Vbgr, and the voltage at node25will be pulled to at least Vt1+Vt2−Vt3, where Vt3is the threshold voltage of the transistors20,21, and22. Therefore, using the startup circuit23, the bandgap circuit will be powered up to the normal operational state.

The startup circuit23has two major drawbacks. First, if the power supply voltage Vcc is less than Vt1+Vt2, then Vbias, Vbgr, and the voltage at node25can only be pulled up to a level of Vcc−Vt3. For example, if Vcc=1.6 V, and Vt3=1.0 V, Vbias, Vbgr, and the node25voltage can be pulled to 0.6 V, which is not enough to turn on the NMOSFETs26,27,28, and29, and BJTs15and16provided the threshold voltages of those devices are larger than 0.6 V, since typical threshold voltages for such devices are approximately 0.7 V. Therefore, the bandgap reference circuit10will stay in the zero-current state. Second, the startup circuit23consumes power during the normal operation of the circuit10. This is unacceptable, especially if the circuit10is used for portable devices, which have stringent power consumption requirements of a few microwatts.

DETAILED DESCRIPTION

The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

An improved startup circuit300is shown inFIGS. 3 and 4.FIG. 3is a circuit diagram of a startup circuit300according to one embodiment of the present invention. Circuit300comprises two circuit branches310and320, each connected between a supply voltage302and ground. Branch310includes a PMOS transistor336, and NMOS transistors337and338, all source to drain connected in series between the supply voltage302and ground. Transistors336and338are each gate connected to an enable signal enb. Branch320includes four PMOS transistors331,332,333, and334, and two NMOS transistors339and335, all source to drain connected in series between the supply voltage and ground. The PMOS transistors331,332,333,334, and335are each gate connectable to a node (indicated inFIG. 3as Vbgr) of a circuit that is to be started using the circuit300. The gate of transistor337is connected to a node340between transistor334and transistor339, and the gate of transistor339is connected to a node342(also node Vbgr, see alsoFIG. 4) between transistor337and transistor338.

Circuit300is shown connected to a bandgap reference circuit400inFIG. 4. Node342/Vbgr of circuit300is connected to the node of the circuit to be started, in this embodiment node Vbgr of bandgap reference circuit400, to start node Vbgr. Circuit400is similar to circuit10ofFIG. 1in one embodiment. Two PMOS transistors440and441are connected to the enable signal enb in the circuit400.

Before the reference circuit400is started, the enable signal providing a potential to node enb and to transistors336and338of circuit300is at Vcc. With this voltage at node enb, transistors336,440, and441are off. NMOSFET338is on, pinning node Vbgr to ground. NMOSFETs335and339are off, and PMOSFETs331,332,333, and334are fully on. Node340is therefore pulled to Vcc. NMOSFET337is on, but no current flows into node Vbgr because PMOSFET336is off. BJT416is also off. This greatly reduces if not eliminates leakage current through branch310of the circuit300.

When the reference circuit400is enabled, node enb goes to ground. Initially, node Vbgr remains close to ground. PMOSFETs331,332,333,334,440, and441turn on, NMOSFET337is on, and NMOSFETs335and338are off. At the beginning of the cycle, PMOSFET336and NMOSFET337are fully on (their absolute gate to source voltages are approximately Vcc). Therefore at the beginning of the cycle, a large current injects into node Vbgr through FETs336and337. The ideal current value can be represented as:
μ*Cox*W/L*(|Vgs|−|Vt|)2/2
of PET336if it is weaker than FET337, or
μ*Cox*W/L*(|Vgs|−|Vt|)2/2
of FET337if it is weaker than PET336.

The current injection into node Vbgr after the circuit has been enabled at the time of approximately 300 nanoseconds is shown inFIG. 5. The current injection brings node Vbgr to a higher voltage. When the voltage at node Vbgr becomes greater than about 0.7 V at room temperature, BJT416turns on.

After the bandgap reference circuit stabilizes to the operational state, node Vbgr rises to approximately 1.25 V. At this potential, NMOSFETs335and339are on. PMOSFET331switches from fully on at the beginning of the startup sequence to weakly on (its absolute gate to source voltage equals Vcc−Vbgr). The drain to source voltage drop across the weakly on FET331causes the source voltage of FET332to drop below Vcc. The body effect, caused by the source voltage of FET332being lower than the Nwell voltage (Vcc) gives transistor332a higher threshold voltage Vt than transistor331. Therefore, PMOS332is on, but is on even more weakly than PMOS331, presuming they have the same size, because |Vgs−Vt| of PMOS332is smaller than PMOS331. Similar analysis applies to PMOSs333and334. The result is that the voltage at node340is pushed very close to ground. The node voltage at node340after the circuit has been enabled for approximately 300 ns is shown inFIG. 6. PMOS334and NMOS337are actually off at this time. The current consumption of the two branches310and320of the startup circuit300after startup is zero if leakage current is not taken into account. After startup, the voltage at node Vbgr can remain at any voltage between Vtn and Vcc (approximately 1.8 V) and not be disturbed by the startup circuit, where Vtn is the threshold voltage of devices335and339.

In another embodiment, two more startup circuits like startup circuit300are used to start up nodes425and Vbias of circuit400. Such circuits are connected similarly to the way circuit300is connected to node Vbgr of circuit400, and operate in the same fashion. Nodes425and Vbias in that embodiment each have their own startup circuit, with the respective nodes fed back in the same way as circuit300has node Vbgr fed back to it to start up node Vbgr. Each can use a separate startup circuit with its own enable signal, and feeds nodes back the same way node Vbgr is fed back to the circuit300. In this way, multiple nodes of a circuit can be started, with the same benefits of the startup circuit. Further, the nodes can be started in an order that is most logical for power consumption and the like for the circuit being started.

Other types of circuits for which the embodiments of the present invention are useful include by way of example but not by way of limitation, any circuit using a large amount of current injection which then shuts off itself after stabilization of the Vbgr node. The startup circuit embodiments of the present invention may be used with many different startup circuits, not just bandgap circuits, but anything that is to be started. Further, many low power analog circuits also need and use startup circuits. The embodiments of the present invention are also amenable to use with such analog circuits as well.

FIG. 7is a functional block diagram of a memory device700, such as a flash memory device, of one embodiment of the present invention, which is coupled to a processor710. The memory device700and the processor710may form part of an electronic system720. The memory device700has been simplified to focus on features of the memory that are helpful in understanding the present invention. The memory device includes an array of memory cells730. The memory array730is arranged in banks of rows and columns.

An address buffer circuit740is provided to latch address signals provided on address input connections A0-Ax742. Address signals are received and decoded by row decoder744and a column decoder746to access the memory array730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends upon the density and architecture of the memory array. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device reads data in the array730by sensing voltage or current changes in the memory array columns using sense/latch circuitry750. The sense/latch circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array. Data input and output buffer circuitry760is included for bi-directional data communication over a plurality of data (DQ) connections762with the processor710, and is connected to write circuitry755and read/latch circuitry750for performing read and write operations on the memory700.

Command control circuit770decodes signals provided on control connections772from the processor710. These signals are used to control the operations on the memory array730, including data read, data write, and erase operations. An analog voltage and current supply780is connected to control circuitry770, row decoder744, write circuitry755, and read/latch circuitry750. In a flash memory device, analog voltage and current supply780is important due to the high internal voltages necessary to operate a flash memory. The flash memory device has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

A startup circuit, such as startup circuit300, is shown inFIG. 7connected to control circuitry770, address circuitry740, and analog voltage and current supply780. The startup circuit300is used in various embodiments in a memory device and in a processing system including processor710, to startup various nodes of the circuitry within the memory device or the system. It should be understood that any circuit or node in such a memory device or processing system that needs to be started may be started with the embodiments of the present invention, and that while not all connections are shown, such connections and use of the startup circuit embodiments of the present invention are within its scope. It should also be understood that while a generic memory device is shown, the startup circuit embodiments of the present invention are amenable to use with multiple different types of memory devices, including but not limited to dynamic random access memory (DRAM), synchronous DRAM, flash memory, and the like.

The embodiments of the present invention offer good startup behavior to a reference circuit while keeping almost zero current consumption after startup. The concept is in part based on the MOSFET body effect, so it is reliable and easy to implement, and has a small size.

CONCLUSION

A startup circuit has been described that is able to inject high current into npn bipolar junction transistors, pnp BJTs, or the gates of MOSFET current sources in order to start a reference circuit with a Vcc of 1.4-2.2 V. The invention utilizes the body effect of MOSFETs to eliminate the leakage through the startup circuit after the bandgap circuit successfully starts, while still offering strong current injection during startup of the bandgap circuit.