Outphasing power amplifier signal splitter using next stage input impedance and multiple biasing

Embodiments relate to outphasing amplifiers and amplification. One example system includes a signal splitter configured to receive an input signal and output a plurality of signals, wherein the signal splitter shifts each of the plurality of signals by a distinct phase based at least in part on a power of the input signal; a plurality of power amplifiers (PAs), each configured to amplify a distinct signal of the plurality of signals to generate a distinct amplified signal; a plurality of input matching networks, each coupled to a distinct PA of the plurality of PAs and configured to transform an input impedance of the coupled PA to an outphasing load condition based on the distinct signal the coupled PA is configured to amplify; and a combiner configured to combine the plurality of distinct amplified signals to generate an amplified input signal.

FIELD

The present disclosure relates to outphasing power amplifiers with reduced power consumption and complexity, while achieving higher efficiency.

BACKGROUND

High peak-to-average ratio signals for high data-rate communication require power amplifiers to operate in a wide back-off mode, resulting in low average efficiency. Outphasing power amplifiers (PAs) use multiple amplifiers to provide output power in a linear and efficient way at the back-off condition when it is used with non-isolating power combiners.

One example of a non-isolating power combiner is the Chireix combiner.FIG. 1illustrates two variations of an outphasing power amplifier (PA) with a Chireix combiner and input phase modulator. At100is a Chireix combiner using two quarter wave length transmission lines (2-way) and shunt reactive elements. These shunt elements can be replaced by transmission lines of different lengths with similar functionality as shown in the Chireix combiner at110.

Another conventional example of an outphasing PA employs four power amplifiers with a 4-way power combiner that results in flatter efficiency over a wider back-off operation range. When these amplifiers are used in an outphasing mode with a combiner requires an input signal splitter or phase modulator such as those depicted in the Chireix combiners ofFIG. 1. These signal splitters have been conventionally implemented using digital signal processing (DSP), up-converting a baseband signal to out-phased RF signals.

DETAILED DESCRIPTION

Conventional outphasing amplifiers that use digital signal processing (DSP) for up-conversion of baseband signals to out-phased RF signals introduce complexity to outphasing power amplifier (PA) design and also restrict adoption of such outphasing amplifiers into existing systems as drop-in PAs. These conventional outphasing PAs cannot be easily replaced with pre-existing power amplifiers and require new transmitter system design to accommodate the outphasing PA. Additionally, the system complexity also increases as the number of power amplifiers used increases, for example, when employing N-way outphasing amplifiers.

Another issue with conventional outphasing PAs is that the efficiency of the non-isolating outphasing combiner versus power has the desirable flat response only for the high power region (from peak power to the designed back-off power level) and quickly drops in the low power region (and is even lower than conventional fixed-load power amplifiers), as shown inFIG. 2, illustrating the combiner efficiency against input signal amplitude for an ideal Chireix combiner.

Referring toFIG. 3, illustrated is a conventional outphasing PA with a 4-way output combiner and input signal splitter. The signal splitter inFIG. 3was implemented in a digital domain using IQ-modulators which up-convert baseband signals into RF signals with corresponding phases. The high complexity of digital control circuits was removed via the use of the analog signal splitter shown inFIG. 3. The output combiner was reused as a signal splitter with added nonlinear resistors for the phase splitting to achieve outphasing.

The output power combiner inFIG. 3presents varied loads to power amplifiers versus output power during outphasing operation. This combiner is used in a reverse way at the input. The input signals are split into different phases when the outputs of the splitter are loaded with varied loads. Nonlinear variable resistors (RNL) are introduced at the output of the splitter to produce signal splitting for power amplifiers. In this configuration, as illustrated inFIG. 4A, the nonlinear variable resistors were implemented using anti-parallel diodes and a resistor.FIG. 4Bshows the simulated nonlinear resistance variation for the outphasing PA ofFIG. 3.

At low power, the diodes are off and the resistance is constant, so in this power region the system ofFIG. 3behaves like conventional fixed-load power amplifiers. Thus, it addresses the issue of low efficiency at low power region. Conventionally, at low power, the phases were fixed and operated as normal power amplifiers using digital control at the cost of complexity. When the voltages across the diodes are above on-voltage (Von), they conduct currents (Id) resulting in nonlinear variable resistance and operate in an outphasing mode. However, one drawback to this method is that the diodes and the resistor consume power (Von×Id+IR2RP) when they are on. Thus, lower splitter gain and power inefficiency are expected. Another drawback is that these anti-parallel diodes add complexity in design by themselves. Additionally, the nonlinear resistance variation may not be suitable for 2-way outphasing power amplifiers, which have higher reactive load variation than 4-way implementations or require nonlinear complex impedance variation rather than resistive variation only. The unnecessary power consumption of the outphasing PA ofFIG. 3can lead to lower gain and low efficiency, with higher complexity and larger form factor than embodiments discussed herein.

Embodiments disclosed herein relate to outphasing power amplifiers with reduced complexity and power consumption, while providing higher efficiency. Systems, methods, and apparatuses discussed herein can include signal splitters that can replace complex digital signal splitters for 4-way outphasing amplifiers as well as 2-way. Embodiments discussed herein can also be used for complex Chireix-Doherty composite amplifier implementation with significantly reduced complexity. Conventionally, outphasing amplifiers have been less frequently chosen by power amplifier designers due to increased complexity compared to Doherty amplifiers. However, outphasing PAs and signal splitters discussed herein have reduced complexity and power consumption, and can be employed in a variety of applications for flatter and wider back-off efficiency, with higher average efficiency.

In contrast to conventional outphasing PAs, embodiments discussed herein do not require digital signal processing. Thus, pre-existing PAs can be replaced with amplifiers discussed herein as a drop-in PA, with less complexity and potentially smaller form factor, while maintaining at least the same performance. Additionally, signal splitter aspects discussed herein can simplify prior analog signal splitters, which have required nonlinear or active components with higher complexity such as in Chireix-Doherty composite amplifiers or the 4-way outphasing PA ofFIG. 3.

In aspects, input matching networks of power amplifiers can be configured to transform the input impedance variation of devices versus power to the necessary load variation of signal splitters for outphasing operation. Additionally, in various embodiments, multiple biasing can be selected by adjusting the gate bias voltage of at least some of the PAs employed in such embodiments. Outphasing amplifiers have conventionally had degraded efficiency at low power range. In aspects, to recover efficiency at the low power region, multiple gate biasing can be applied. As one example, a first PA can be biased at class-AB operation, while a second PA can be biased at class-C operation condition.

Referring toFIG. 5, illustrated is a block diagram of a system500that facilitates outphasing power amplification in accordance with various aspects discussed herein. System500can include a signal splitter510, a plurality of power amplifiers520i, a plurality of input matching networks530i, and a combiner540.

Signal splitter510can receive an input data signal (e.g., modulated input RF signal, etc.) and split that signal into a plurality of distinct data signals, each of which can be shifted by a distinct phase that can be based at least in part on the input data signal. Signal splitter510can output the plurality of different data signals along a plurality of distinct signal paths. Signal splitter510can shift the distinct data signals by different phases through any of a variety of means, such as via shunt reactive elements on distinct signal paths, different lengths of transmission lines on distinct signal paths, combinations thereof, etc.

Each of the plurality of power amplifiers520ican be along one of the plurality of distinct signal paths, and can receive and amplify one of the distinct data signals, outputting an amplified version of that distinct data signal. In various embodiments, different numbers of power amplifiers520ican be employed in system500, such as two power amplifiers, three, four, or substantially any number of power amplifiers. Each of the power amplifiers520ican be of any of a variety of device types (e.g., gallium nitride (GaN), laterally diffused metal oxide semiconductor (LDMOS), etc.), and the plurality of power amplifiers520ican each be of the same device type, or can be of two or more different device types. As discussed in greater detail below, the device type of each power amplifier520ican affect the input impedance of that power amplifier520i.

In various aspects, multiple gate biasing can be employed with the plurality of power amplifiers520i, which can provide improved efficiency at low power. In such aspects, at least one of the PAs520ican have a first gate bias, and at least one of the PAs520ican have a second distinct gate bias (in some aspects, further distinct gate biases can also be used). Thus, in some embodiments, when the power of the input data signal is below some threshold power (which can depend on the associated gate bias(es)), one or more (e.g., all but one, etc.) of the PAs520i(e.g., those with the second gate bias, etc.) can be deactivated or remain inactive. As one example, in a system with two PAs520i, a first PA5201can be biased as a class-AB PA, and a second PA5202can be biased as a class-C PA, such that below a certain threshold power of the input data signal, the second PA5202can deactivate or remain inactive. Thus, below the threshold power, outphasing operation need not be employed, and low power efficiency can be increased.

Each of the plurality of input matching networks530ican be on a distinct signal path and coupled to the distinct PA520iof the plurality of PAs520ion that signal path. Each input matching network530ican transform the input impedance of the coupled PA520ito an outphasing load condition based on the distinct data signal on that signal path (the distinct data signal the coupled PA520iamplifies).

Combiner540can receive the plurality of distinct amplified data signals that have been amplified by the plurality of PAs520i, and combine those distinct amplified data signals by shifting their phases to generate an amplified version of the input data signal. Combiner540can shift the phases of the distinct amplified data signals by different phases through any of a variety of means, such as via shunt reactive elements on distinct signal paths, different lengths of transmission lines on distinct signal paths, combinations thereof, etc. Additionally, combiner540and signal splitter510can employ similar or distinct techniques for shifting the phases of the distinct data signals and distinct amplified data signals, respectively.

As discussed above, each input matching network530itransforms impedances from the input impedance of the associated PA520ito the outphasing load conditions at the signal splitter510. If the input impedance of the associated PA520iis unknown, the input matching network530icannot be designed. That input impedance can be identified as follows. First, for each signal path, the impedance can be measured at the input of combiner when in the outphasing condition, wherein signals with distinct phases versus power level are applied to the combiner and combined into one output signals versus power. Second, the impedances determined at the inputs of combiner when in the outphasing condition can be applied to the respective outputs of the PAs520iin the outphasing condition, thus the input powers of the PAs520iis varied based on the impedance variation measured at the respective input of combiner when in the outphasing condition as a function of power. In various aspects, the PAs520ican be linear or nonlinear with a certain gain, therefore, the input powers can be adjusted accordingly to maintain the intended outphasing condition at the combiner540. Third, input impedance variation at the input of each PA520ican be measured as a function of power. From this input impedance variation, the associated input matching network530ican be designed.

Non-ideal devices such as gallium nitride (GaN), etc., or amplifiers have inherent input impedance variation versus power and loads. In various embodiments, this impedance variation can be exploited to achieve the load variation to the splitter to enable outphasing operation. This technique can also use the output combiner as an input signal splitter. However, aspects discussed herein can replace the anti-parallel diodes ofFIG. 3, using the inherent input impedance variation of devices with an input matching network configured to provide load variation for signal splitting. Therefore, the power consumption of the diodes in the system ofFIG. 3is eliminated. The impedance transformation of the input impedance variation to outphasing load condition at the splitter can be absorbed into the input matching networks of the power amplifiers, which are typically included in power amplifier designs. thus, the complexity of using anti-parallel diodes is removed and the signal splitter can be significantly simplified according to various aspects discussed herein. The input impedance variations of devices are a function of output power and load and are not necessarily resistive. Thus, with a proper impedance transformation, the load variation is not limited to resistive variation. Thus the techniques employed herein can be used for a wider range of applications, for example, 2-way and N-way (e.g., 4-way, etc.) outphasing power amplifiers which may require resistive as well as complex impedance variation.

Furthermore, the low efficiency at the low power region can be addressed using multiple biasing, as discussed herein. The gate biases of amplifiers can be different, and some or all of the devices can be turned on, depending on whether operating in low or high power modes. This technique need not be limited to GaN devices, and can employed in a range of devices where the input impedance variation of the device is sufficiently large.

Referring toFIG. 6, illustrated is a flow diagram of a method600that can facilitate amplification of an input data signal.

At602, optionally, one or more PAs of a plurality of PAs can be biased, and in various aspects, multiple distinct biases can be applied to different PAs of the plurality of PAs. For example, at least a first set of one or more PAs can be biased with a first bias (e.g., biased as a class-AB PA), at least a second set of one or more PAs can be biased with a second bias (e.g., biased as a class-C PA), etc.

At604, optionally, the input impedances of the plurality of PAs can be determined. This can involve the technique discussed above. Thus, for each PA, an associated input impedance at the combiner in connection with the outphasing load condition can be measured, the measured combiner input impedance can be applied to the output of the PA, and the input impedance of the PA based on the applied combiner input impedance can be measured.

At606, the input impedances of each PA of the plurality of PAs can be transformed to an outphasing load condition, such as via an input matching network such as input matching network530i.

At608, the input data signal can be split into a plurality of distinct data signals, by shifting each of the distinct data signals by a different phase, and providing each via a distinct signal path (e.g., a distinct output of a signal splitter such as signal splitter510, etc.). Splitting can be accomplished via shunt reactive elements, varying transmission line lengths, a combination thereof, etc.

At610, each of the distinct data signals can be amplified by an associated PA to generate an amplified version of the distinct data signal. If distinct biases were applied to different PAs at602, depending on the power of the input data signal, it may be low enough (e.g., below a threshold power, etc.) that only some of the plurality of PAs (e.g., those with the first bias) will amplify respective distinct data signals, while the others are deactivated or remain inactive.

At612, the amplified distinct data signals can be combined (e.g., via a combiner that phase shifts the amplified distinct data signals to combine them) to generate an amplified version of the input data signal. As with the splitting of the input data signal, the combining can be accomplished via shunt reactive elements, varying transmission line lengths, combinations thereof, etc.

Referring toFIG. 7, illustrated is a pair of conventional outphasing combiners, showing a Chireix combiner at700, and an alternative version employing transmission lines only at710. Chireix combiners have quarter wave length transformers with shunt reactive elements for proper backoff operation. As can be seen at710, the shunt elements of the Chireix combiner can be effectively represented by using different lengths of transmission lines.

Referring toFIG. 8A, illustrated are typical phases of two voltage signals applied to the combiner inputs versus input signal amplitude. With these signals,FIG. 8Billustrates the load variation seen at the input of the combiner which is typically presented to power amplifiers where the smith chart is normalized to 50 Ohm. The ideal efficiency of the combiners ofFIG. 7versus input amplitude is depicted inFIG. 2, discussed above. The efficiency is maintained at high level from the peak amplitude to the back-off second peak efficiency point and rapidly decreases as input amplitude decreases.

The combiners inFIG. 7can be configured as signal splitters, as discussed above. The combiner can be reversed, the output can be connected to signal sources, and the inputs can be connected to power amplifier inputs with proper load variation.FIG. 9illustrates two example outphasing signal splitters900and910according to various aspects discussed herein. The load variation applied to the output of signal splitters are the same as the load variation of combiners ofFIG. 8B. Note that the reactive elements connected at the V1and V2nodes in signal splitters can be switched between the two nodes different from the combiner as shown at900. The transmission line length differences are reversed as well in910. Otherwise, the shunt reactive elements and the transmission line lengths can be kept the same when the loads are complex conjugated for the same operation.

Referring toFIG. 10, shows split signal phases at the nodes V1and V2versus source signal amplitude with appropriate load variation at the output of signal splitter. In the example, shown in R0=70.7Ω, B=0.007 and X=1/B inFIG. 9at900and R0=82.6Ω, ΔI=31° inFIG. 9at910, with Rs=50Ω. These parameters can be selected in particular embodiments for a designed back-off operation of power amplifiers. ZL1and ZL2are varied-loads of Chireix combiner.

Although the specific examples considered inFIGS. 9 and 10have two PAs, techniques discussed herein need not be limited to two-way outphasing amplifiers. Four-way and N-way outphasing splitters can be employed in various embodiments. The required load variation for signal split in the conventional outphasing amplifier ofFIG. 3, however, was implemented using anti-parallel diodes with a parallel resistor, as shown inFIG. 4A. Those diodes and resistor consume power, resulting in lower gain and added complexity. In various embodiments disclosed herein, those diodes and the resistor can be removed by using input impedance variation of realistic devices (e.g., GaN devices, LDMOS devices, etc.).

Referring toFIG. 11, illustrated is a circuit diagram of an example power amplifier designed using a GaN device that can be loaded with the varied loads of a 2-way outphasing combiner. The loads ZL1and ZL2, which are variable loads, mimic the load variation presented to power amplifiers by outphasing combiners, as illustrated inFIG. 12at1200. The input impedance of the power amplifier is function of output power and loads as Zin=f(Pout, ZL(Pout)), where Zin, Poutand ZLare input impedance, output power and the load presented to the power amplifier, respectively. All these parameters depend on the design frequency (not explicitly shown here), and it is assumed that all the load variations and matching networks have been properly designed for the specific design frequency. Also note that the output matching of the power amplifier is properly phased in such a way that the output power is decreased when the load is increased. However, this load variation direction as a function of power also can be reversed in various embodiments.

FIG. 12illustrates the input impedance variation for the two different load variation cases (ZL1, ZL2) of1200at1210. These input impedance variations can be effectively transformed to the necessary impedance variation of the splitter by a proper impedance transformer as shown inFIG. 13, illustrating two different example embodiments of outphasing amplifiers according to various aspects discussed herein, with an example embodiment employing shunt elements at130, and an example transmission line only embodiment at1310. The input matching network (IMN) can be implemented in a variety of ways, for example, using lumped elements or transmission lines with single or multiple sections, etc.

As discussed above, in various aspects, multiple biasing can be employed. As discussed above in connection withFIG. 2, the efficiency of outphasing combiners quickly degrades in the low power operation range. The system ofFIG. 3attempted to address this via nonlinear impedance variation using the on and off conditions of diodes; however, this resulted in increased complexity and power consumption. In various embodiments, at least some PAs can have different biases from one another to address the low power efficiency issues. In one example with two PAs, one amplifier can be biased as a class-AB mode PA, while the other amplifier can be biased for class-C operation mode. With this varied bias in various embodiments, the gain of a particular power amplifier can be varied and can be compensated for by using various methods such as adjusting the signal split ratio, using different device sizing, etc.

Referring toFIG. 14, illustrated are graphs of the fundamental drain current with various gate biases (Vg2) at1400and the corresponding power added efficiency recovery of the outphasing operation in the low power range at1410. As can be seen in1400, the turn-on time of devices can be controlled via selection of the gate bias. Graph1410demonstrates the power added efficiency (PAE) recovery at the low power region in outphasing operation condition with varied bias. Any expected phase mismatch at high power region caused by this gate bias adjustment can be compensated for via tuning of the phase offset line of power amplifier output matching networks. Additionally, any gain mismatch at the high power region caused by gate bias adjustment can be compensated for via adjusting the signal split ratio, using different device sizing, etc.

Simulations were performed in connection with various example embodiments. An input signal splitter with input matching network was simulated for signal splitting and outphasing operation, using a nonlinear simulator as shown inFIG. 15.FIG. 15shows a transmission line implementation of a splitter (similar to that of1310), which is the reverse of the connected output power combiner. Note that the transmission line lengths are switched from the combiner when used as a splitter. The input impedance variation was transformed by the input matching network to provide load variation for signal splitting. Additionally, the two paths have separate gate biases for biasing (Vg1=−3.0V, Vg2=−3.8 V).

FIG. 16shows the simulated load variation at the input of the outphasing combiner, demonstrating the proper outphasing operation when compared to the theoretical load variation ofFIG. 8B. Note that when the class-C biased power amplifier is turned off at low power operation, the impedance seen from the class-C biased amplifier goes out of the smith chart as can be seen in curve ZL2of1600. The split phases at the output of the signal splitter are shown in1610versus input amplitude, showing out-phased signal splitting after the class-C bias amplifier is turned on.

Referring toFIG. 17, illustrated is a graph comparing simulated PAE between a conventional fixed-load power amplifier and an outphasing power amplifier according to various aspects disclosed herein. The outphasing amplifier clearly shows improved efficiency at back-off due to the intended outphasing operation with the signal splitter implemented with input matching network and multiple biasing. Although the example discussed in connection withFIGS. 15-17relates to a transmission-line only implementation, embodiments employing shunt elements perform similarly.