Semiconductor device including on-die resistor and method of calibrating on-die resistor

A semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2022-0129099, filed in the Korean Intellectual Property Office on Oct. 7, 2022, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

The present disclosure relates to a semiconductor device, and particularly, to a semiconductor device including an on-die resistor and a method of calibrating an on-die resistor.

An on-die resistor may mean a resistor that is integrated into a system on chip (SoC) for impedance matching in an output stage or input stage thereof. In general, a resistance value of the on-die resistor is changed depending on a process, a voltage, and a temperature. Accordingly, a resistance value of the on-die resistor needs to be adjusted through the calibration of the on-die resistor. The calibration of the on-die resistor that is integrated into the SoC has a limit in that the accuracy of calibration is not high because the calibration is performed through external calibration means.

SUMMARY

In an embodiment, a semiconductor device may include an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.

Furthermore, in an embodiment, a method of calibrating an on-die resistor of a semiconductor device is a method of calibrating an on-die resistor of a semiconductor device in which the on-die resistor and a calibration circuit configured to perform calibration on the on-die resistor are integrated in a single chip form. The method may include setting a calibration current within the calibration circuit, performing a first calibration process that sets a first input voltage that is applied to the on-die resistor by the calibration current, performing a second calibration process that sets a second input voltage that is applied to an external resistor having a target resistance value of the on-die resistor by the calibration current, and performing a third calibration process that compares the first input voltage with the second input voltage and stores a resistance value of the on-die resistor when the first input voltage is higher than the second input voltage.

DETAILED DESCRIPTION

In the following description of embodiments, it will be understood that the terms “first” and “second” are intended to identify elements, but not used to define a particular number or sequence of elements. In addition, when an element is referred to as being located “on,” “over,” “above,” “under,” or “beneath” another element, it is intended to mean relative positional relationship, but not used to limit certain cases for which the element directly contacts the other element, or at least one intervening element is present between the two elements. Accordingly, the terms such as “on,” “over,” “above,” “under,” “beneath,” “below,” and the like that are used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as being “connected” or “coupled” to another element, the element may be electrically or mechanically connected or coupled to the other element directly, or may be electrically or mechanically connected or coupled to the other element indirectly with one or more additional elements between the two elements. Moreover, when a parameter is referred to as being “predetermined,” it may be intended to mean that a value of the parameter is determined in advance of when the parameter is used in a process or an algorithm. The value of the parameter may be set when the process or the algorithm starts or may be set during a period in which the process or the algorithm is executed. A logic “high” level and a logic “low” level may be used to describe logic levels of electric signals. A signal having a logic “high” level may be distinguished from a signal having a logic “low” level. For example, when a signal having a first voltage corresponds to a signal having a logic “high” level, a signal having a second voltage may correspond to a signal having a logic “low” level. In an embodiment, the logic “high” level may be set as a voltage level which is higher than a voltage level of the logic “low” level. Meanwhile, logic levels of signals may be set to be different or opposite according to embodiment. For example, a certain signal having a logic “high” level in one embodiment may be set to have a logic “low” level in another embodiment.

Various embodiments of the present disclosure will be described hereinafter in detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

FIG.1is a block diagram illustrating a semiconductor device10according to an embodiment of the present disclosure. Referring toFIG.1, the semiconductor device10may include an on-die resistor circuit100, a calibration circuit200, a calibration control circuit300, a first pad410, and a second pad420. The semiconductor device10may be constituted within a single chip or may be constituted within a part of a single chip. That is, the on-die resistor circuit100, the calibration circuit200, and the calibration control circuit300may be integrated into a single die.

The on-die resistor circuit100may include an on-die resistor. In an example, the on-die resistor circuit100may be constructed by having a plurality of resistors that are disposed in an array format. In this case, a connection state of the plurality of resistors may be controlled by an e-fuse. That is, a resistance value of the on-die resistor may be determined based on a signal that is applied to the e-fuse. The on-die resistor circuit100may be configured to have a resistance value that varies based on a value of a resistance adjustment code CODE1that is transmitted by the calibration control circuit300. The resistance adjustment code CODE1may be constituted within a digital signal. The on-die resistor circuit100may include a digital-analog converter (DAC) configured to convert the resistance adjustment code CODE1into an analog signal. The on-die resistor circuit100may be connected to the calibration circuit200and the first pad410. For a calibration operation for the on-die resistor, an electrical connection between the on-die resistor circuit100and the first pad410may be temporarily blocked. To this end, the on-die resistor circuit100may include a switch to electrically connect with the first pad410or block against the first pad410. The switch within the on-die resistor circuit100may become on or off based on a switching control signal SW_A from the calibration control circuit300.

The calibration circuit200may perform a calibration operation on the on-die resistor of the on-die resistor circuit100. The calibration circuit200may include a current generating circuit210, a comparing circuit220, and a switch230. Although not illustrated in this drawing, the current generating circuit210may include a plurality of switches. The switch230and the plurality of switches within the current generating circuit210may become on or off based on the switching control signals SW_Bs from the calibration control circuit300.

The current generating circuit210may receive a current adjustment code CODE2from the calibration control circuit300. The current generating circuit210may provide a current that is increased in proportion to a value of the current adjustment code CODE2. The current generating circuit210may include a DAC configured to convert the current adjustment code CODE2into an analog signal. The current generating circuit210may generate a reference voltage VREF in order to set a calibration current to be used for the calibration of the on-die resistor of the on-die resistor circuit100. The reference voltage VREF that is generated by the current generating circuit210may be applied to the comparing circuit220. The current generating circuit210may supply a calibration current to the on-die resistor circuit100. Furthermore, the current generating circuit210may provide a calibration current to an external resistor, which is outside of the semiconductor device10, through the first pad410.

The comparing circuit220may be used for a calibration current setting operation in the current generating circuit210and a calibration operation for the on-die resistor of the on-die resistor circuit100. First, during the calibration current setting process in the current generating circuit210, the comparing circuit220may receive the reference voltage VREF from the current generating circuit210. In such a process, the switch230may maintain an open state. The comparing circuit220may receive a voltage that is applied to the first pad410, that is, a voltage that is applied to a node N1in the state in which the switch230has been closed. The comparing circuit220may generate an output signal OUT by comparing the reference voltage VREF with a voltage of the node N1. Next, during the calibration process for the on-die resistor, the comparing circuit220may receive a first input signal that is generated by a calibration current and the on-die resistor, instead of the reference voltage VREF. Furthermore, the comparing circuit220may receive a voltage of the node N1that is generated by a calibration current and an external resistor, as a second input signal. The comparing circuit220may generate the output signal OUT by comparing the magnitudes of the first input signal and the second input signal. The output signal OUT from the comparing circuit220may be transmitted to the calibration control circuit300and may also be transmitted to an external device, which is outside of the semiconductor device10, through the second pad420.

The switch230may maintain a closed state during a process in which the current generating circuit210sets a calibration current so that a voltage of the node N1may be applied to the comparing circuit220. When the calibration current is set in the current generating circuit210, the switch230may maintain an open state during a process in which the first input signal is transmitted to the comparing circuit220. The switch230may maintain a closed state during a process in which the second input signal is transmitted to the comparing circuit220.

The calibration control circuit300may generate the resistance adjustment code CODE1and the switching control signal SW_A capable of changing a resistance value of the on-die resistor of the on-die resistor circuit100and may transmit the resistance adjustment code CODE1and the switching control signal SW_A to the on-die resistor circuit100. The calibration control circuit300may generate the current adjustment code CODE2capable of changing a current value of the current generating circuit210of the calibration circuit200and may transmit the current adjustment code CODE2to the current generating circuit210. Furthermore, the calibration control circuit200may generate the switching control signals SW_Bs and may transmit the switching control signals SW_Bs to the calibration circuit200. The calibration control circuit300may change values of the resistance adjustment code CODE1and the current adjustment code CODE2based on the output signal OUT that is transmitted by the comparing circuit220of the calibration circuit200and may then output the resistance adjustment code CODE1and the current adjustment code CODE2.

The first pad410and the second pad420may be provided as electrical coupling means between the semiconductor device10and an external device. The first pad410may be connected to the on-die resistor circuit100and the calibration circuit200in common. The second pad420may be connected to an output stage of the comparing circuit220of the calibration circuit200. The first pad410may be electrically connected to or electrically blocked against the on-die resistor circuit100by the switch within the on-die resistor circuit100. Furthermore, the first pad410may be electrically connected to or electrically blocked against the calibration circuit200by the switch within the calibration circuit200.

FIG.2is a circuit diagram illustrating the on-die resistor circuit100and the calibration circuit200that are included in the semiconductor device10ofFIG.1. A first switching control signal SW1inFIG.2may mean the switching control signal SW_A inFIG.1. Second to sixth switching control signals SW2to SW6inFIG.2may mean the switching control signals SW_Bs inFIG.1. A third node N3inFIG.2may mean the node N1inFIG.1. Furthermore, a sixth switch560inFIG.2may mean the switch230inFIG.1.

Referring toFIG.2, the on-die resistor circuit100may include an on-die resistor ROD and a first switch510. The on-die resistor ROD that is presented inFIG.2may correspond to equivalent resistors of a plurality of resistors that is disposed in the on-die resistor circuit100in an array form.

The on-die resistor ROD of the on-die resistor circuit100may include a first terminal and a second terminal. The first terminal of the on-die resistor ROD may be connected to the calibration circuit200and the first pad410. Specifically, the first terminal of the on-die resistor ROD may be connected to the third node N3and the first pad410through the first switch510. A switching operation of the first switch510may be controlled by the first switching control signal SW1that is transmitted by the calibration control circuit (300inFIG.1). The first terminal of the on-die resistor ROD may be connected to a second node N2of the calibration circuit200through a second switch520within the calibration circuit200. A switching operation of the second switch520may be controlled by the second switching control signal SW2that is transmitted by the calibration control circuit (300inFIG.1). The second terminal of the on-die resistor ROD may be connected to a ground terminal. As described with reference toFIG.1, a resistance value of the on-die resistor ROD may be changed based on a value of the resistance adjustment code CODE1that is transmitted by the calibration control circuit300. The resistance adjustment code CODE1may be a plurality of bits, for example, an 8-bit binary stream. In this case, if a 1 least significant bit (LSB) is set to 0.5 ohm, the resistance adjustment code CODE1may change a resistance value of the on-die resistor ROD in a 0.5 ohm unit.

The current generating circuit210of the calibration circuit200may include a voltage division circuit211and a variable current source212. The voltage division circuit211may include a first resistor R1and a second resistor R2that are disposed between a supply voltage line and the ground terminal in series. A supply voltage VDD may be applied to the supply voltage line. A first node N1between the first resistor R1and the second resistor R2may be connected to a second node N2through a third switch530. A switching operation of the third switch530may be controlled by the third switching control signal SW3that is transmitted by the calibration control circuit (300inFIG.1). In an example, if the first resistor R1and the second resistor R2have the same resistance value, a voltage in the first node N1may become a half of the supply voltage VDD, that is, “VDD/2”.

The variable current source212of the current generating circuit210may provide a calibration current ICAL that is used in a calibration process for the on-die resistor ROD. A first terminal of the variable current source212may be connected to the supply voltage line. A second terminal of the variable current source212may be connected to the second node N2and the third node N3in parallel. Specifically, the second terminal of the variable current source212may be connected to the second node N2through a fourth switch540. Furthermore, the second terminal of the variable current source212may be connected to the third node N3through a fifth switch550. Switching operations of the fourth switch540and the fifth switch550may be controlled by the fourth switching control signal SW4and the fifth switching control signal SW5, respectively, that are transmitted by the calibration control circuit (300inFIG.1). As described with reference toFIG.1, the amount of current of the variable current source212may be changed based on a value of the current adjustment code CODE2that is transmitted by the calibration control circuit300.

The comparing circuit220of the calibration circuit200may include a comparator221including a first input terminal, a second input terminal, and an output terminal. Although not illustrated in this drawing, the comparator221may include bias terminals. The first input terminal and second input terminal of the comparator221may be a negative input terminal and a positive input terminal, respectively. The first input terminal of the comparator221may be connected to the second node N2. Accordingly, when the second switch520of the calibration circuit200is closed, the first input terminal of the comparator221may be connected to the first terminal of the on-die resistor ROD. Furthermore, when the third switch530of the calibration circuit200is closed, the first input terminal of the comparator221may be connected to the first node N1of the voltage division circuit211. Furthermore, when the fourth switch540of the calibration circuit200is closed, the first input terminal of the comparator221may be connected to the second terminal of the variable current source212. The second input terminal of the comparator221may be connected to the third node N3through the sixth switch560. The output terminal of the comparator221may be connected to the second pad420. Although not illustrated in this drawing, the output terminal of the comparator221may also be connected to the calibration control circuit (300inFIG.1). The comparator221may compare the magnitudes of the first input signal and the second input signal that are input to the first input terminal and the second input terminal, respectively, and may output a result of the comparison as the output signal OUT through the output terminal. In the following several examples, when the first input signal is greater than the second input signal, the comparator221may output the output signal OUT having a low level. In contrast, when the second input signal is greater than the first input signal, the comparator221may output the output signal OUT having a high level.

FIGS.3to5are circuit diagrams illustrated to describe a calibration current setting process of the calibration circuit200inFIG.2. First, referring toFIG.3, in order to set a calibration current of the variable current source212, the external resistor REXT may be connected to the first pad410. That is, an external resistor REXT may be disposed between the first pad410and the ground terminal, outside of the semiconductor device (10inFIG.1). The external resistor REXT may have a resistance value that is identical to a resistance value of the on-die resistor ROD, which will be set. In the state in which the external resistor REXT is connected between the first pad410and the ground terminal, the calibration control circuit (300inFIG.1) may provide the variable current source212with a first current adjustment code CODE21. Accordingly, the variable current source212may supply a current I1corresponding to the first current adjustment code CODE21.

The calibration control circuit (300inFIG.1) may transmit, to the on-die resistor circuit100, the first switching control signal SW1having a low level “L”. Furthermore, the calibration control circuit (300inFIG.1) may transmit, to the calibration circuit200, the third switching control signal SW3, the fifth switching control signal SW5, and the sixth switching control signal SW6having a high level “H”, and the second switching control signal SW2and the third switching control signal SW4having a low level “L”. The first switch510of the on-die resistor circuit100may be opened by such switching control signals. Furthermore, the third switch530, fifth switch550, and sixth switch560of the calibration circuit200may be closed, and the second switch520and the fourth switch540of the calibration circuit200may be opened. Accordingly, the current I1from the variable current source212of the calibration circuit200may flow into the external resistor REXT through the third node N3and the first pad410. A first node voltage VN1in the first node N1may be applied to the first input terminal of the comparator221of the calibration circuit200. Furthermore, a third node voltage VN31in the third node N3may be applied to the second input terminal of the comparator221of the calibration circuit200. The first node voltage VN1may be a reference voltage that is fixedly supplied by the voltage division circuit211. In contrast, the third node voltage VN31may be a voltage that is applied to both ends of the external resistor REXT by the current I1corresponding to the first current adjustment code CODE21. The comparator221may compare the voltage levels of the first node voltage VN1with the third node voltage VN31that are applied to the first input terminal and the second input terminal, respectively. When the third node voltage VN31is not higher than the first node voltage VN1, the comparator221may output the output signal OUT having a low level “L” through the output terminal. The output signal OUT having a low level “L” from the comparator221may be transmitted to the calibration control circuit (300inFIG.1).

Next, referring toFIG.4, the calibration control circuit (300inFIG.1) that has received the output signal OUT having a low level “L” from the comparator221may provide a second current adjustment code CODE22to the variable current source212. The second current adjustment code CODE22may have a greater value than the first current adjustment code (CODE21inFIG.3). The variable current source212may supply a current I2corresponding to the second current adjustment code CODE22. In the state in which the first to sixth switching control signals SW1to SW6maintain the same logic level, the first node voltage VN1and a third node voltage VN32may be applied to the first input terminal and second input terminal of the comparator221, respectively. The third node voltage VN32may be a voltage that is applied to both ends of the external resistor REXT by the current I2corresponding to the second current adjustment code CODE22. The comparator221may compare the voltage levels of the first node voltage VN1and the third node voltage VN32that are applied to the first input terminal and the second input terminal, respectively. When the third node voltage VN32is not higher than the first node voltage VN1, the comparator221may output the output signal OUT having a low level “L” through the output terminal. The output signal OUT having a low level “L” from the comparator221may be transmitted to the calibration control circuit (300inFIG.1).

The calibration current setting process that has been described with reference toFIGS.3and4may be repeated and performed until the logic level of the output signal OUT from the comparator221is changed from a low level “L” to a high level “H”. While the calibration current setting process is being performed, a value of the current adjustment code CODE2that is provided by the calibration control circuit (300inFIG.1) to the variable current source212of the current generating circuit210may be increased. Accordingly, the amount of current that is generated by the variable current source212may also be increased. In this example, a case in which the logic level of the output signal OUT of the comparator221is not changed when one of the first to seventh current adjustment codes is provided to the variable current source212of the current generating circuit210has been presupposed.

Next, referring toFIG.5, the calibration control circuit (300inFIG.1) that has received the output signal OUT having a low level “L” from the comparator221may provide the variable current source212with an eighth current adjustment code CODE28. The variable current source212may supply a current I8corresponding to the eighth current adjustment code CODE28. In the state in which the first to sixth switching control signals SW1to SW6maintain the same logic level, the first node voltage VN1and the third node voltage VN38may be applied to the first input terminal and second input terminal of the comparator221, respectively. The third node voltage VN38may be a voltage that is applied to both ends of the external resistor REXT by the current I8corresponding to the eighth current adjustment code CODE28. The comparator221may compare the voltage levels of the first node voltage VN1and the third node voltage VN38that are applied to the first input terminal and the second input terminal, respectively. When the third node voltage VN38is higher than the first node voltage VN1, the comparator221may output the output signal OUT having a high level “H” through the output terminal. The output signal OUT having a high level “H”, output from the comparator221, may be transmitted to the calibration control circuit (300inFIG.1).

As described with reference toFIG.3, the external resistor REXT that is connected to the third node N3through the first pad410, which is outside of the semiconductor device (10inFIG.1), may have a resistance value that is identical to a resistance value of the on-die resistor ROD, which will be calibrated. Accordingly, the third node voltage VN38(i.e., a voltage that is applied to both ends of the external resistor REXT by the current I8corresponding to the eighth current adjustment code CODE28) that is applied to the third node N3may have a voltage level that is close to the first node voltage VN1(i.e., the reference voltage) in the first node N1, which is set by the voltage division circuit211. A case in which the voltage level of a voltage that is applied to both ends of the external resistor REXT by the current I8is identical to the voltage level of a voltage that is applied to both ends of the on-die resistor ROD by the current I8may mean a case in which a resistance value of the on-die resistor ROD and a resistance value of the external resistor REXT are substantially the same.

Accordingly, the calibration control circuit (300inFIG.1) may set, as the calibration current ICAL, the current I8corresponding to the eighth current adjustment code CODE28that is provided by the variable current source212. The calibration control circuit (300inFIG.1) may perform such setting by storing the eighth current adjustment code CODE28.

FIGS.6to14are circuit diagrams illustrated to describe a calibration operation of the calibration circuit200inFIG.2. In the following examples, the state in which the current I8that is supplied from the variable current source212by the eighth current adjustment code CODE28has been set as the calibration current ICAL through the processes ofFIGS.3to5is presupposed. In this example, a calibration operation may include first to third calibration steps. The first to third calibration steps may be repeated and performed until a resistance value of the on-die resistor ROD reaches a desired resistance value or a target resistance value through the calibration process.

First, referring toFIG.6, the calibration control circuit (300inFIG.1) may perform a control operation for the 1stfirst calibration step during the calibration process. Specifically, the calibration control circuit300may block an electrical connection between the on-die resistor circuit100and the third node N3. To this end, the calibration control circuit300may open the first switch510by providing the on-die resistor circuit100with the first switching control signal SW1having a low level “L”. Furthermore, the calibration control circuit300may block an electrical connection between the voltage division circuit211of the current generating circuit210and the second node N2. To this end, the calibration control circuit300may open the third switch530by providing the calibration circuit200with the third switching control signal SW3having a low level “L”. The calibration control circuit300may maintain both the first switch510and the third switch530at an open state while the first to third calibration steps of the calibration process are being performed.

The calibration control circuit300may open the fifth switch550and the sixth switch560by providing the calibration circuit200with the fifth switching control signal SW5and the sixth switching control signal SW6having a low level “L”. Accordingly, an electrical connection between the variable current source212and the third node N3and an electrical connection between the second input terminal of the comparator221and the third node N3may be blocked. The calibration control circuit300may close the second switch520and the fourth switch540by providing the calibration circuit200with the second switching control signal SW2and the fourth switching control signal SW4having a high level “H”. Accordingly, the variable current source212and the on-die resistor ROD may be electrically connected to the second node N2.

The calibration control circuit300may provide the on-die resistor ROD with a first resistance adjustment code CODE11. Accordingly, the on-die resistor ROD may have a resistance value corresponding to a value of the first resistance adjustment code CODE11. The calibration control circuit300may provide the variable current source212with the eighth current adjustment code CODE28. Accordingly, the variable current source212may supply the calibration current ICAL. The calibration current ICAL that is supplied from the variable current source212may flow into the on-die resistor ROD of the on-die resistor circuit100through the second node N2. A second node voltage VN21in the second node N2of the calibration circuit200may have the same voltage level as a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL. Although not illustrated in this drawing, the second node voltage VN21may be stored by a first capacitor that is between the second node N2and the ground terminal.

Next, referring toFIG.7, the calibration control circuit (300inFIG.1) may perform a control operation for the 1stsecond calibration step during the calibration process. Specifically, the calibration control circuit300may open the second switch520and the fourth switch540by providing the calibration circuit200with the second switching control signal SW2and the fourth switching control signal SW4having a low level “L”. Accordingly, an electrical connection between the variable current source212and the on-die resistor ROD and the second node N2may be blocked. The calibration control circuit300may close the fifth switch550and the sixth switch560by providing the calibration circuit200with the fifth switching control signal SW5and the sixth switching control signal SW6having a high level “H”. Accordingly, the variable current source212and the comparator221may be electrically connected to the third node N3. The calibration current ICAL that is supplied from the variable current source212may flow into the external resistor REXT through the third node N3and the first pad410. That is, a third node voltage VN3in the third node N3may have the same voltage level as a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL. Although not illustrated in this drawing, the third node voltage VN3may be stored by a second capacitor between the third node N3and the ground terminal.

Next, referring toFIG.8, the calibration control circuit (300inFIG.1) may perform a control operation for the 1stthird calibration step during the calibration process. Specifically, the calibration control circuit300may open the fourth switch540and the fifth switch550by providing the calibration circuit200with the fourth switching control signal SW4and the fifth switching control signal SW5having a low level “L”. Accordingly, an electrical connection between the variable current source212and the second node N2and the third node N3may be blocked. The calibration control circuit300may close the second switch520and the sixth switch560by providing the calibration circuit200with the second switching control signal SW2and the sixth switching control signal SW6having a high level “H”. The second node voltage VN21(i.e., a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL) may be supplied to the first input terminal of the comparator221(i.e., the negative input terminal) as a first input signal. Furthermore, the third node voltage VN3(i.e., a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL) may be supplied to the second input terminal of the comparator221(i.e., the positive input terminal) as a second input signal. The comparator221may compare the first input signal and the second input signal. When the second node voltage VN21is not higher than the third node voltage VN3, the comparator221may output the output signal OUT having a high level “H” through the output terminal. The output signal OUT having a high level “H” from the comparator221may be transmitted to the calibration control circuit300. As the output signal OUT having a high level “H” is transmitted by the comparator221, the calibration control circuit300may perform the 2ndfirst to third calibration steps on the condition that the resistance value of the on-die resistor ROD has been increased.

Referring toFIG.9, the calibration control circuit (300inFIG.1) may perform a control operation for the 2ndfirst calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stfirst calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.6. The calibration control circuit300may provide the on-die resistor ROD with a second resistance adjustment code CODE12. Accordingly, the on-die resistor ROD may have a resistance value corresponding to a value of the second resistance adjustment code CODE12. That is, the on-die resistor ROD may have a resistance value that is higher than a resistance value that has been set in the 1stfirst to third calibration steps. The calibration control circuit300may provide the variable current source212with the eighth current adjustment code CODE28. Accordingly, the variable current source212may supply the calibration current ICAL. The calibration current ICAL that is supplied from the variable current source212may flow into the on-die resistor ROD of the on-die resistor circuit100through the second node N2. A second node voltage VN22in the second node N2of the calibration circuit200may have the same voltage level as a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL.

Referring toFIG.10, the calibration control circuit (300inFIG.1) may perform a control operation for the 2ndsecond calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stsecond calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.7. As in the 1stsecond calibration step, the third node voltage VN3in the third node N3may have the same voltage level as a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL.

Referring toFIG.11, the calibration control circuit (300inFIG.1) may perform a control operation for the 2ndthird calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stthird calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.8. Accordingly, the second node voltage VN22(i.e., a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL) may be supplied to the first input terminal of the comparator221(i.e., the negative input terminal) as the first input signal. Furthermore, the third node voltage VN3(i.e., a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL) may be supplied to the second input terminal of the comparator221(i.e., the positive input terminal) as the second input signal. When the second node voltage VN22is not higher than the third node voltage VN3, the comparator221may output the output signal OUT having a high level “H” through the output terminal. The output signal OUT having a high level “H” from the comparator221may be transmitted to the calibration control circuit300. As the output signal OUT having a high level “H” is transmitted by the comparator221, the calibration control circuit300may perform the 3rdfirst to third calibration steps on the condition that the resistance value of the on-die resistor ROD has been increased.

The calibration process of the first calibration step, the second calibration step, and the third calibration step being sequentially performed may be repeated and performed until the logic level of the output signal OUT that is output by the comparator221is changed from a high level “H” to a low level “L”. As described above, a value of the resistance adjustment code CODE1that is provided from the calibration control circuit (300inFIG.1) to the on-die resistor ROD of the on-die resistor circuit100may be increased whenever the calibration process is performed. Accordingly, a resistance value of the on-die resistor ROD may be increased in proportion to the increased value of the resistance adjustment code CODE1. Accordingly, if a voltage in the second node N2becomes higher than a voltage in the third node N3, the logic level of the output signal OUT that is output by the comparator221may be changed from a high level “H” to a low level “L”. In this example, a case in which the comparator221outputs the output signal OUT having a high level “H” when one of the first to seventh resistance adjustment codes is provided to the on-die resistor ROD of the on-die resistor circuit100and a case in which the comparator221outputs the output signal OUT having a low level “L” when the eighth resistance adjustment code is provided to the on-die resistor ROD of the on-die resistor circuit100may be presupposed.

Referring toFIG.12, the calibration control circuit (300inFIG.1) may perform a control operation for the 8thfirst calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stfirst calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.6. The calibration control circuit300may provide the on-die resistor ROD with an eighth resistance adjustment code CODE18. Accordingly, the on-die resistor ROD may have a resistance value corresponding to a value of the eighth resistance adjustment code CODE18. That is, the on-die resistor ROD may have a resistance value that is higher than the resistance values in previous 7thfirst to third calibration steps. The calibration control circuit300may provide the variable current source212with the eighth current adjustment code CODE28. Accordingly, the variable current source212may supply the calibration current ICAL. The calibration current ICAL that is supplied from the variable current source212may flow into the on-die resistor ROD of the on-die resistor circuit100through the second node N2. A second node voltage VN28in the second node N2of the calibration circuit200may have the same voltage level as a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL.

Referring toFIG.13, the calibration control circuit (300inFIG.1) may perform a control operation for the 8thsecond calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stsecond calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.7. As in the 1stsecond calibration step, the third node voltage VN3in the third node N3may have the same voltage level as a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL.

Referring toFIG.14, the calibration control circuit (300inFIG.1) may perform a control operation for the 8ththird calibration step during the calibration process. Specifically, the calibration control circuit300may transmit, to the on-die resistor circuit100and the calibration circuit200, the same switching control signals as those in the 1stthird calibration step. Accordingly, the states of the first to sixth switches510to560may be the same as those that have been described with reference toFIG.8. The second node voltage VN28(i.e., a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL) may be supplied to the first input terminal of the comparator221(i.e., the negative input terminal) as the first input signal. Furthermore, the third node voltage VN3(i.e., a voltage that is applied to both ends of the external resistor REXT by the calibration current ICAL) may be supplied to the second input terminal of the comparator221(i.e., the positive input terminal) as the second input signal. When the second node voltage VN28is higher than the third node voltage VN3, the comparator221may output the output signal OUT having a low level “L” through the output terminal. The output signal OUT having a low level “L” from the comparator221may be transmitted to the calibration control circuit300. As the output signal OUT having a low level “L” is transmitted by the comparator221, the calibration control circuit300may set a current resistance value of the on-die resistor ROD as a calibrated resistance value and may store the eighth resistance adjustment code CODE18that has been provided to the on-die resistor ROD.

FIG.15is a circuit diagram illustrated to describe a connection state of the on-die resistor circuit100and the calibration circuit200after the calibration of the on-die resistor is completed. Referring toFIG.15, when the calibration of a resistance value of the on-die resistor ROD is completed, the calibration control circuit (300inFIG.1) may block a connection between the calibration circuit200and the on-die resistor circuit100and a connection between the calibration circuit200and the first pad410. Furthermore, the calibration control circuit300may connect the on-die resistor ROD of the on-die resistor circuit100and the first pad410.

Specifically, the calibration control circuit300may open all of the second to sixth switches520to560by transmitting, to the calibration circuit200, the second to sixth switching control signals SW2to SW6having a low level “L”. Accordingly, an electrical connection between the calibration circuit200and the on-die resistor circuit100may be blocked. Furthermore, an electrical connection between the variable current source212of the calibration circuit200and the comparator221and the third node N3may be blocked. Accordingly, all the connection of the calibration circuit200with the first pad410may be blocked. Accordingly, the calibration circuit200may no longer consume power after the calibration of the on-die resistor ROD is completed. The calibration control circuit300may close the first switch510by transmitting, to the on-die resistor circuit100, the first switching control signal SW1having a high level “H”. Accordingly, the on-die resistor ROD of the on-die resistor circuit100and the first pad410may be electrically interconnected.

FIG.16is a block diagram illustrating the comparing circuit220that is included in the calibration circuit200inFIG.1. Referring toFIG.16, the comparing circuit220may include a data tracking and latch regeneration circuit222and an offset cancellation circuit223. The data tracking and latch regeneration circuit222may perform a data tracking operation that generates an output signal by amplifying a signal that is generated as a result of a comparison between the first input signal and the second input signal. Furthermore, the data tracking and latch regeneration circuit222may perform a latch regeneration operation that releases the output of a latch circuit after the output signal is generated and swings the output of a difference between voltages of the first input signal and the second input signal toward an opposite voltage rail. For the latch regeneration operation, the data tracking and latch regeneration circuit222may receive the reference voltage VREF. The offset cancellation circuit223may perform an operation that cancels an offset within the comparing circuit220. The operation that cancels an offset by the offset cancellation circuit223may be performed while the first calibration step and the second calibration step are being performed. Furthermore, the tracking operation and latch regeneration operation of the data tracking and latch regeneration circuit222may be performed from timing at which the third calibration step is performed. As described above, as the operation of cancelling an offset is performed before the data tracking and latch regeneration operation is performed, that is, while the first calibration step and the second calibration are being performed, a malfunction attributable to an offset within the comparing circuit220can be prevented.

FIG.17is a circuit diagram illustrated to describe an example of an external calibration process for the semiconductor device10according to an embodiment of the present disclosure. As illustrated inFIG.17, after the calibration of the on-die resistor ROD is completed, that is, after the calibration circuit (200inFIG.1) is electrically separated from the on-die resistor circuit100, calibration may be performed by using an external test apparatus. Specifically, one terminal of a test current source610may be connected to the first pad410. The other terminal of the test current source610may be connected to the supply voltage line. An external current IEXT that is supplied from the test current source610may flow into the on-die resistor ROD. Accordingly, a voltage in the first pad410may have the voltage level of a voltage that is applied to both ends of the on-die resistor ROD by the external current IEXT. A resistance value of the on-die resistor ROD may be calculated by measuring the voltage in the first pad410. When the calculated resistance value is different from a calibrated resistance value, the resistance value of the on-die resistor ROD may be changed by providing, from the calibration control circuit (300inFIG.1) to the on-die resistor ROD, the resistance adjustment code CODE1having a value that is different from a current value.

FIGS.18to21are circuit diagrams illustrated to describe another example of an external calibration process for the semiconductor device10according to an embodiment of the present disclosure. InFIGS.18and19, the same reference numerals as those inFIG.2denote the same elements, and a redundant description of the same elements is omitted. According to the present example, a temperature change in the on-die resistor ROD of the semiconductor device (10inFIG.1) may be measured in various conditions by using an external test apparatus. A resistance value of the on-die resistor ROD may be changed suitably for a use condition based on the results of the measurement.

First, referring toFIG.18, an external test circuit700may be connected through the first pad410of the semiconductor device10. The external test circuit700may include a contact resistor RCNT, an external resistor REXT, a trace resistor RTRA, and an external switch710. The contact resistor RCNT may be disposed between the first pad410and a first terminal of the external switch710. The external resistor REXT may be disposed between a second terminal of the external switch710and the ground terminal. The external resistor REXT may have the same resistance value as a calibrated resistance value of the on-die resistor ROD. The trace resistor RTRA may be disposed between a third terminal of the external switch710and the test apparatus720. A switching operation of the external switch710may be controlled by the test apparatus720. The external switch710may perform a switching operation that connects the first terminal and second terminal or connects the first terminal and the third terminal.

In the state in which the on-die resistor ROD has a calibrated resistance value as in the first calibration step that has been described with reference toFIG.6, the calibration control circuit (300inFIG.1) may supply the second node N2with the second node voltage VN2that is identical to a voltage that is applied to both ends of the on-die resistor ROD by the calibration current ICAL.

Referring toFIG.19, in the state in which the first terminal and second terminal of the external switch710have been connected, the calibration control circuit (300inFIG.1) may supply the third node N3with the third node voltage VN3having the same voltage level as that of a voltage that is applied to the contact resistor RCNT and the external resistor REXT by the calibration current ICAL, as in the second calibration step that has been described with reference toFIG.7.

Referring toFIG.20, the calibration control circuit (300inFIG.1) may input the second node voltage VN2and the third node voltage VN3to the first input terminal and second input terminal of the comparator221, respectively, as in the third calibration step that has been described with reference toFIG.8. The comparator221may compare the second node voltage VN2and the third node voltage VN3and may output the output signal OUT having a logic level according to a result of the comparison. The output signal OUT that is output by the comparator221may be transmitted to the test apparatus720through the second pad420. When the process that has been described with reference toFIGS.18to20is repeated while changing a resistance value of the on-die resistor ROD until the second node voltage VN2and the third node voltage VN3have close voltage levels, a resistance value of the on-die resistor ROD may become a value that is obtained by adding a resistance value of the contact resistor RCNT and a resistance value of the external resistor REXT.

Referring toFIG.21, after the resistance value of the on-die resistor ROD is calibrated as the value that has been obtained by adding the resistance value of the contact resistor RCNT and the resistance value of the external resistor REXT through the process that has been described with reference toFIGS.18to20, the first terminal and third terminal of the external switch710may be connected. The calibration control circuit (300inFIG.1) may block both the connection between the calibration circuit200and the on-die resistor circuit100and the connection between the calibration circuit200and the first pad410. Furthermore, the calibration control circuit (300inFIG.1) may connect the on-die resistor ROD and the first pad410by closing the first switch510. The test equipment720may measure a resistance value on a path along which the trace resistor RTRA, the contact resistor RCNT, and the on-die resistor ROD are connected in series. The measured resistance value may have a value that is obtained by adding all of the resistance value of the on-die resistor ROD, the resistance value of the contact resistor RCNT, and a resistance value of the trace resistor RTRA. The resistance value of the trace resistor RTRA may be a value that may be known through direct measurement. Accordingly, a resistance value that is obtained by subtracting the resistance value of the trace resistor RTRA from the measured resistance value may become a value that is obtained by adding the resistance value of the external resistor REXT and twice the resistance value of the contact resistor RCNT. A change in the resistance value of the on-die resistor ROD according to a temperature change or a change in a process condition can be checked by performing such measurement of resistance values under several conditions, for example, various temperature conditions or process conditions, and a subsequent and proper correction is made possible.

A limited number of possible embodiments for the present teachings have been presented above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions, and substitutions are possible. While this patent document contains many specifics, these should not be construed as limitations on the scope of the present teachings or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.