Circuit for controlling memory and associated method

A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal.

This application claims the benefit of Taiwan application Serial No. 107100498, filed Jan. 5, 2018, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a memory, and more particularly to a circuit for controlling a dynamic random access memory (DRAM) and an associated method.

Description of the Related Art

In a common dynamic random access memory (DRAM) system, a memory controller performs down-frequency when a high bandwidth is not required for a memory, so as to achieve the effectiveness of power saving. However, in the prior art, a DRAM can change the frequency only in a self-refresh mode. Thus, if a memory controller is to control a DRAM for up-frequency or down-frequency, an additional period (in a scale of ms) for entering/exiting the self-refresh mode needs to be sacrificed. If a memory demands a fast changes in the bandwidth, a memory controller then frequently controls the memory to enter/exit the self-refresh mode, causing long periods of time delay.

SUMMARY OF THE INVENTION

Therefore, it is a primary object of the present invention to provide a circuit for controlling a memory and an associated method capable of significantly reducing the number of times of entering a self-refresh mode for the memory, so as to solve issues of the prior art.

A circuit for controlling a memory is disclosed according to an embodiment of the present invention. The circuit includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency parameter generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal to adjust the frequency of the clock signal from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal, and controls the memory according to the clock signal.

A method for controlling a method is further disclosed according to another embodiment of the present invention. The method includes: generating at least one frequency control signal by a frequency parameter generator; increasing or decreasing the frequency of a clock signal by a multiple number of times according to the frequency control signal to adjust the frequency of the clock signal from an initial frequency to a target frequency; and controlling the memory according to the clock signal.

A circuit for controlling a memory is disclosed according to another embodiment of the present invention, wherein the memory is a dynamic random access memory (DRAM). The circuit includes a memory controller and an adjustment frequency determining circuit. The memory controller controls access of the memory. The adjustment frequency determining circuit automatically detects an access requirement of the memory to trigger the memory controller to control the memory to enter or exit a self-refresh mode.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a block diagram of a circuit100according to an embodiment of the present invention. As shown inFIG. 1, the circuit100includes a frequency parameter generator control circuit110, a frequency parameter generator120, a clock generator130, a memory controller140and a memory150. In this embodiment, the memory controller140is a dynamic random access memory (DRAM) controller, and the memory150is a DRAM.

In the operation of the circuit100, when the frequency of the memory150needs to be adjusted, the frequency parameter generator control circuit110first generates an initial frequency parameter START, a target frequency parameter END and a frequency adjustment speed parameter R to the frequency parameter generator120. The initial frequency parameter START represents an initial frequency of a clock signal CLK (or a current frequency of the clock signal CLK) generated by the clock generator130, the target frequency parameter END represents a target frequency of the clock signal CLK, and the frequency adjustment speed parameter R represents a speed for adjusting the clock signal CLK during frequency adjustment. The frequency parameter generator control circuit110uses an enable signal EN to enable the frequency parameter generator120. Further, the frequency parameter generator control circuit110generates a sampling interval parameter CNT to control the frequency parameter generator120to output, according to a sampling interval, a frequency control signal VSET for the clock generator130to accordingly adjust the frequency of the clock signal CLK.

For example, assuming that the frequency of the memory150needs to be decreased from 3200 MHz to 1600 MHz, the frequency parameter generator control circuit110first generates the initial frequency parameter START for representing 3200 MHz, the target frequency parameter END for representing 1600 MHz, and the frequency adjustment speed parameter R to the frequency parameter generator120. According to the same sampling interval parameter CNT, if the setting of the frequency adjustment speed parameter R is a slower frequency adjustment speed, after receiving the enable signal EN, the frequency parameter generator120can sequentially output the frequency control signals VSET representing 3100 MHz, 3000 MHz, 2900 MHz, . . . and 1600 MHz according to the sampling interval parameter CNT to control the clock generator130to slowly change the frequency of the clock signal CLK. If the setting of the frequency adjustment speed parameter R is a faster frequency adjustment speed, after receiving the enable signal EN, the frequency parameter generator120can directly output the frequency control signal VSET representing 1600 MHz to the clock generator130so as to quickly change the frequency of the clock signal CLK. In practice, the frequency adjustment speed parameter R may be set according to requirements and is not a constant value.

The memory controller140receives the clock signal CLK from the clock generator130, and uses the clock signal CLK to access the memory150.

In one embodiment of the present invention, the frequency adjustment speed parameter R generated by the frequency parameter generator control circuit110controls the speed at which the frequency of the clock CLK changes to be lower than an upper limit. Further, when the clock generator130adjusts the frequency of the clock signal CLK according to the frequency control signal VSET, the memory controller140is not required to control the memory150to first enter a self-refresh mode but can directly adjust the frequency of the clock signal CLK while the memory150remains in the normal operation mode. As such, the issue of the prior art, in which significant time delay is caused by frequently entering/exiting a self-refresh mode, is eliminated.

By having the frequency adjustment speed parameter R control the speed at which the frequency of the clock signal CLK changes to be lower than an upper limit, in addition to eliminating the foregoing issue of frequently entering/exiting a self-refresh mode, glitch caused by drastically increasing or decreasing the frequency at a fast speed in the prior art can also be avoid; moreover, slowing increasing or decreasing the frequency also alleviates the issue of electromagnetic interference (EMI).

Further, in one embodiment, the frequency parameter generator control circuit110can receive the clock signal CLK generated by the clock generator130or the frequency control signal VSET outputted by the frequency parameter generator120. If the frequency of the clock signal CLK received is equal to the target frequency or the frequency of the clock signal CLK corresponding to the frequency control signal VSET received is equal to the target frequency, the frequency parameter generator control circuit110ceases to generate the enable signal EN to turn off the frequency parameter generator120.

FIG. 2shows a block diagram of the frequency parameter generator120according to an embodiment of the present invention. As shown inFIG. 2, the frequency parameter generator120includes a subtractor210, a subtractor220, an adder270, a multiplier230, a delay circuit250and a sampling circuit280. In the operation of the frequency parameter generator120, the subtractor210first performs subtraction on the initial frequency parameter START and the target frequency parameter END to generate a difference signal. The subtractor220, the multiplier230and the delay circuit250form a loop. The subtractor220first performs subtraction on the difference signal and the output of the delay circuit250, multiplication is then performed on a difference of the difference signal and the output of the delay circuit250and the frequency adjustment speed parameter R to obtain an adjustment value, and subtraction is performed on the adjustment value having been delayed by the delay circuit250with the subsequent difference signal. Meanwhile, the adder270adds the adjustment value to the initial frequency parameter START to generate a frequency control signal to be sampled, and the sampling circuit280then samples the frequency control signal to be sampled according to the sampling interval parameter CNT to generate the frequency control signal VSET and transmits the same to the clock generator130.

It should be noted that, the circuit structure inFIG. 2is an illustrative example and is not to be construed as a limitation to the present invention. Given that the frequency parameter generator120can control the speed at which the frequency represented by the frequency control signal VSET is increased or decreased according to the frequency adjustment speed parameter R, any related design modifications are to be encompassed within the scope of the present invention.

FIG. 3shows a block diagram of the clock generator130according to an embodiment of the present invention. As shown inFIG. 3, the clock generator130includes a spread spectrum clock generating circuit310and a phase-locked loop (PLL)320. The spread spectrum clock generating circuit310receives the frequency control signal VSET and accordingly generates a spread spectrum clock signal SS_CLK. For example, the spread spectrum clock generating circuit310may change the frequency of a signal by a periodical modulation signal (e.g., a triangle-wave signal) to disperse the energy originally focused at a frequency to achieve the function of frequency modulation. The PLL320then generates the clock signal CLK according to the spread spectrum clock signal SS_CLK to the memory controller140.

FIG. 4shows a flowchart of a method for controlling the memory150according to an embodiment of the present invention. Referring to the disclosure of the embodiment inFIGS. 1 to 3, the process ofFIG. 4is as follows.

In step400, the process begins.

In step401, it is determined whether the clock generator130is in a stable state. More specifically, step401determines whether the output of the PLL320in the clock generator130is in a stable state, i.e., whether the clock generator130is capable of generating the clock signal CLK having a stable initial frequency to the memory controller140.

In step420, it is determined whether the frequency of the clock signal CLK needs to be changed. If so, the process enters step404; if not, the process returns to step401.

In step407, the clock generator130changes the frequency of the clock signal CLK according to the frequency control signal VSET. More specifically, the clock generator130gradually controls the clock signal CLK having the initial frequency to change to the clock signal CLK having the target frequency according to the frequency control signal VSET, wherein the target frequency is determined by the target frequency parameter END.

In step408, it is determined whether the clock signal CLK is switched to the target frequency parameter END. If so, the processor enters step410; if not, the process returns to step408. It should be noted that, step408may also be determined through the frequency control signal VSET.

In step410, it is determined whether the clock generator130is in a stable state. More specifically, step410determines whether the output of the PLL320in the clock generator130is in a stable state; that is, whether the clock generator130is capable of generating the clock signal CLK having the stable target frequency to the memory controller140.

In step412, the frequency parameter generator120is turned off. The frequency parameter generator control circuit110ceases to transmit the enable signal EN to turn of the frequency parameter generator120. It should be noted that, although the frequency parameter generator120is turned off, the clock generator130nonetheless continues to output the clock signal CLK according to the final adjustment result.

FIG. 5shows a block diagram of a circuit500according to an embodiment of the present invention. Compared to the circuit100inFIG. 1, the circuit500further includes an adjustment frequency determining circuit560, and thus the description below focuses on details of the adjustment frequency determining circuit560. In the operation of the circuit500, the adjustment frequency determining circuit560automatically detects an access requirement of a memory550so as to determine whether to perform frequency adjustment on the clock signal CLK. That is to say, the adjustment frequency determining circuit560performs step402inFIG. 4. More specifically, the adjustment frequency determining circuit560can generate a frequency adjustment signal VF according to whether a memory controller540receives an access request from at least one function block, or according to the bandwidth that the memory controller540currently needs to use, to perform frequency adjustment. Assuming that the memory controller540currently has not received any access request from any function block or the bandwidth needed to be used in the memory controller540is lower than a threshold, it means that the frequency can be decreased to perform a more power saving operation. At this point, the adjustment frequency determining circuit560transmits the adjustment signal VF to the frequency parameter generator control circuit510to control a frequency parameter generator520to generate the frequency control signal VSET to a clock generator530, so as to decrease the frequency of the clock signal CLK. Assuming that the memory controller540later receives an access request from a function block, or the bandwidth needed to be used in the memory controller540is higher than the threshold, the adjustment frequency determining circuit560transmits the frequency adjustment signal VF to the frequency parameter generator control circuit510to control the frequency parameter generator520to generate the frequency control signal VSET to the clock generator530, so as to increase the frequency of the clock signal CLK to the target frequency. Operation details for increasing or decreasing the frequency can be referred to the above description associated with steps404to412, and are omitted herein.

In the embodiment inFIG. 5, because the adjustment frequency determining circuit560is capable of automatically detecting related information of the memory550accessed by the memory controller540to determine whether to adjust the frequency, operations can be effectively performed while achieving the effectiveness of power saving. Further, by gradually increasing or decreasing the frequency through the frequency parameter generator control circuit510and the frequency parameter generator520, impulsive interference caused by drastically increasing or decreasing the frequency at a fast speed as in the prior art can be avoided, thus allowing the system to be more stable.

In one embodiment, the adjustment frequency determining circuit560may be provided in the memory controller540.FIG. 6shows a block diagram of the memory controller540according to an embodiment of the present invention. As shown inFIG. 6, the memory controller540includes the adjustment frequency determining circuit560, an arbitration circuit610, a bandwidth detecting circuit620and a processing circuit630. The arbitration circuit610receives access requests from multiple function blocks602,604and606, and determines processing sequences thereof. The bandwidth detecting circuit620is capable of real-time detecting the bandwidth in the arbitration circuit610(i.e., the amount of data flow of the arbitration circuit610, and the amount of data flow gets increases as the number of access requests received by the arbitration circuit610gets larger), and the adjustment frequency determining circuit560real-time generates the frequency adjustment signal VF according to a detection result of the bandwidth detecting circuit620. Further/Alternatively, the bandwidth detecting circuit620may determine whether the function blocks602,604and606transmit access requests to the arbitration circuit610. If no access request transmitted from any of the function blocks is detected, the frequency adjustment determining circuit560generates the frequency adjustment signal VF to decrease the frequency of the clock signal CLK; if an access request transmitted from any one of the function blocks is detected, the adjustment frequency determining circuit560generates the frequency adjustment signal VF to increase the frequency of the clock signal CLK.

FIG. 7shows a block diagram of a circuit700according to another embodiment of the present invention. The function of the circuit700is similar to that of the circuit500inFIG. 5, with one difference being that an adjustment frequency determining circuit760additionally controls, according to an access requirement of a memory750, an internal processing circuit of a memory controller740to enter/exit a self-refresh mode. The process of entering/exiting the self-refresh mode includes three phases, which are a down-frequency phase, an idle phase and an up-frequency phase. More specifically, assuming that the current memory controller740does not receive any access request from any function block or the bandwidth needed to be used in the memory controller740is lower than a threshold, the adjustment frequency determining circuit760transmits a control signal CMD to the memory controller740to cause the internal circuit of the memory controller740to enter the self-refresh mode. Next, the adjustment frequency determining circuit760transmits a frequency adjustment signal VF to a frequency parameter generator control circuit710to control a frequency parameter generator720to generate the frequency control signal VSET to a clock generator730, so as to gradually decrease the frequency of the clock signal CLK. Operation details for decreasing the frequency can be referred from the description on steps404to412above. The memory controller740later enters the idle phase. Next, when the current memory controller740receives an access request from a function block or the bandwidth needed to be used in the memory controller740is higher than the threshold, the adjustment frequency determining circuit760again transmits the frequency adjustment signal VF to the frequency parameter generator control circuit710to control the frequency parameter generator circuit720to generate the frequency control signal VSET to the clock generator730, so as to gradually increase the frequency of the clock signal CLK. The adjustment frequency determining circuit760later again transmits the control signal CMD to the memory controller740to cause the internal circuit of the memory controller740to exit the self-refresh mode.

In the embodiment inFIG. 7, because the adjustment frequency determining circuit760is capable of automatically detecting related information for accessing the memory750to determine whether to enter/exit the self-refresh mode and then again enter a down-frequency/up-frequency operation, operations can be more effectively performed while achieving the effectiveness of power saving (an optimal power saving effect can be achieved during the idle phase after entering the self-refresh mode). Further, since technical content of controlling the speed for up-frequency/down-frequency described in the foregoing embodiments are adopted, the issues of impulsive interference and EMI can be avoid at the same time.

In one embodiment, the adjustment frequency determining circuit760may be provided in the memory controller740.FIG. 8shows a block diagram of the memory controller740according to another embodiment of the present invention. The memory controller740shown inFIG. 8is similar to the memory controller540inFIG. 6, with one difference being that the adjustment frequency determining circuit760additionally generates the control signal CMD to a processing circuit830so as to control the memory controller740to enter/exit the self-refresh mode. A person skilled in the art could easily understand operation details of the memory controller740inFIG. 8on the basis of the description of the embodiments inFIG. 4toFIG. 7, and such repeated details are omitted herein.

FIG. 9shows a flowchart of a method for controlling the memory750according to an embodiment of the present invention. Referring to the disclosure of embodiments inFIGS. 7 and 8, the process ofFIG. 9includes following steps.

In step900, the memory controller740operates in a normal mode.

In step902, it is determine whether the memory controller740is in an idle state, e.g., the adjustment frequency determining circuit760determines whether the memory controller740has not received access requests from function blocks802,804and806for a period of time.

In step904, the adjustment frequency determining circuit760controls, by the control signal CMD, the memory controller740to enter a self-refresh mode.

In step906, the adjustment frequency determining circuit760transmits the frequency adjustment signal VF to the frequency parameter generator control circuit710to control the frequency parameter generator720to generate the frequency control signal VSET to the clock generator730, so as to decrease the frequency of the clock signal CLK. When the frequency of the clock signal CLK is low enough, the process enters step908.

In step908, the memory controller740enters the idle phase of the self-refresh mode.

In step910, while step904is performed, it is determined whether the memory controller740receives the access requests from the function blocks802,804and806. If so, the process enters step918; if not, the process continues to step904.

In step912, while steps906and908are performed, it is determined whether the memory controller740receives the access requests from the function blocks802,804and806. If so, the process enters step916; if not, the process returns to step908.

In step916, adjustment frequency determining circuit760transmits the frequency adjustment signal VF to the frequency parameter generator control circuit710to control the frequency parameter generator720to generate the frequency control signal VSET to the clock generator730, so as to increase the frequency of the clock signal CLK.

In step918, the adjustment frequency determining circuit760controls, by the control signal CMD, the memory controller740to exit the self-refresh mode.

In conclusion of the present invention, in the embodiments of the present invention, a frequency parameter generator is provided to gradually adjust the frequency at a slower speed, such that a memory controller is still able to perform the operation of up-frequency or down-frequency without entering a self-refresh mode. By providing an adjustment frequency determining circuit to dynamically detect an access requirement to further determine whether to enter or exit a self-refresh mode, operations can be more efficiently performed while achieving the effectiveness of power saving. Further, while entering or exiting a self-refresh mode, a slower speed is used to gradually adjust the frequency, thus further avoiding the issue of impulsive interference and EMI caused by drastically increasing or decreasing the frequency at once, allowing the system to be more stable.