METHOD FOR MANUFACTURING IMAGE PICKUP APPARATUS, AND IMAGE PICKUP APPARATUS

A method for manufacturing an image pickup apparatus in which a second semiconductor region of first conductive type which becomes a well contact region is disposed adjacent to a first semiconductor region via an element isolation region in a pixel which has a well contact region among a plurality of pixels. A first mask which has openings in a region which becomes a first semiconductor region, an element isolation region disposed between the region which becomes the first semiconductor region and a region which becomes a second semiconductor region, and a region which becomes the second semiconductor region is disposed, and the first semiconductor region is formed in the region which becomes the first semiconductor region by conducting ion implantation of second conductive type at an oblique angle to a normal line of a principal surface using the first mask.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing an image pickup apparatus, and to a method for manufacturing a semiconductor region for supplying a predetermined voltage to a well in which an amplifying transistor of a pixel is disposed.

2. Description of the Related Art

A configuration in which a semiconductor region connected to an electric conductor to which a predetermined voltage is supplied is disposed in a well in which a source region and a drain region of an amplifying transistor of each pixel are arranged has been proposed (hereafter, a “well contact region”).

Japanese Patent Laid-Open No. 2011-071347 discloses an image pickup apparatus in which floating diffusion (hereafter, “FD”) to which charge of a photoelectric conversion unit is transferred and a well contact region are disposed adjacent to each other. The well contact region is disposed in each of a plurality of pixels. The well contact region is of conductivity type opposite to those of the source region and the drain region of the transistor of the pixel. Therefore, the well contact region, and the source region and the drain region of the transistor of the pixel are manufactured in different processes.

Japanese Patent Laid-Open No. 2011-251800 discloses a method for forming a source region and a drain region of the transistor of a pixel by ion implantation using a gate electrode as a mask (hereafter, “self-alignment formation). Japanese Patent Laid-Open No. 2011-251800 discloses a method for forming a source region and a drain region by self-alignment formation by forming FD by ion implantation at an oblique angle to a normal line of a principal surface of a semiconductor substrate.

SUMMARY OF THE INVENTION

The present disclosure is a method for manufacturing an image pickup apparatus which includes a plurality of pixels, each of which has a photoelectric conversion unit, floating diffusion which holds charge generated in the photoelectric conversion unit, an amplifying transistor electrically connected to the floating diffusion, and a reset transistor which resets a potential of an input node of the amplifying transistor, wherein some of the plurality of pixels have a well contact region connected to a conductor which supplies a predetermined voltage to the well and others do not, each of the plurality of pixels has a first semiconductor region of a second conductive type which constitutes a source region of the reset transistor and the floating diffusion in the well of the first conductivity type, and an element isolation region is disposed on a principal surface of a semiconductor substrate, and a second semiconductor region of a first conductive type which becomes the well contact region is disposed at a position adjacent to the first semiconductor region via the element isolation region in a pixel which has the well contact region, the method including: a first process in which a first mask having openings in a region which becomes the first semiconductor region, the element isolation region disposed between a region which becomes the first semiconductor region and a region which becomes the second semiconductor region, and the region which becomes the second semiconductor region is disposed, and ion implantation of a second conductive type is conducted at an oblique angle to a normal line of the principal surface using the first mask to form the first semiconductor region in the region which becomes the first semiconductor region; and a second process in which a second mask which covers the region which becomes the first semiconductor region and has an opening in the region which becomes the second semiconductor region is disposed, and the second semiconductor region is formed in the region which becomes the second semiconductor region by conducting ion implantation of the first conductive type using the second mask.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, an image pickup apparatus according to embodiments of the present invention are described with reference to the drawings. In the drawings, the same elements having the same function are denoted by the same reference numerals and duplicate explanation is omitted.

First Embodiment

An image pickup apparatus10of the present embodiment is described with reference toFIGS. 1 to 5B.

FIG. 1is a block diagram of the image pickup apparatus10according to the present embodiment. The image pickup apparatus10includes a pixel unit100, a driving pulse generation unit109, a vertical scanning circuit113, a signal line115, a column circuit114, a horizontal scanning circuit111, and an output unit112.

The pixel unit100includes a plurality of pixels101that convert light into charge signals and output the converted charge signal. The plurality of pixels101are arranged in a matrix form.

The driving pulse generation unit109generates driving pulses. The vertical scanning circuit113receives the driving pulses from the driving pulse generation unit109and supplies control pulses to each pixel column. The control pulses supplied here are pTX that drives a transfer transistor, pRES that drives a reset transistor, and pSEL that drives a selection transistor which are described later. The column circuit114processes in parallel signals output from the pixel unit100. The column circuit114includes an amplifier unit, a noise reduction unit, and an AD conversion unit. The horizontal scanning circuit111outputs signals processed by the column circuit114to the output unit112for each column.

The driving pulse generation unit109, the vertical scanning circuit113, the column circuit114, the horizontal scanning circuit111, and the output unit112constitute a peripheral circuit arranged around the pixel unit100, and a region where these components are arranged is referred to as a peripheral circuit region. The AD conversion unit is included in the column circuit114here, but this configuration is not restrictive.

FIG. 2illustrates an exemplary equivalent circuit of a single pixel. In the present embodiment, signal charge is described as an electron and each transistor is described as an N-type transistor. Alternatively, a hole may be used as the signal charge and a P-type transistor may be used as the transistor of the pixel. In the present embodiment, a semiconductor region of a first conductive type is P-type, and a semiconductor region of a second conductive type is N-type.

An equivalent circuit is not limited to that described above, and a part of the configuration may be shared by a plurality of pixels. The same applies to the following embodiments.

The pixel101includes a photoelectric conversion unit102, a transfer transistor103, a reset transistor106, an amplifying transistor105, floating diffusion (hereafter, “FD”)104, and a selection transistor107.

The photoelectric conversion unit102produces a charge pair of a quantity according to incident light quantity by photoelectric conversion, and accumulates electrons. The photoelectric conversion unit102is formed, for example, by photodiode.

The transfer transistor103transmits electrons accumulated by the photoelectric conversion unit102to the FD104. The control pulse pTX is supplied to a gate of the transfer transistor103to switch between an ON state and an OFF state. The FD104holds electrons transmitted by the transfer transistor103.

The amplifying transistor105is connected to the FD104at a gate thereof, and outputs amplified signals based on the electrons transmitted to the FD104by the transfer transistor103. Specifically, the electrons transmitted to the FD104are converted into a voltage according to the quantity thereof, and charge signals according to the voltage are output to the signal line115via the amplifying transistor105.

The amplifying transistor105constitutes a source follower circuit together with an unillustrated current source. In this circuit, an input node of the amplifying transistor105includes the FD104, a source region of the reset transistor106, a gate of the amplifying transistor105, and an electric conductor which electrically connects these components.

The reset transistor106resets a potential of the input node of the amplifying transistor105. A potential of the photoelectric conversion unit102is reset when the ON state of the reset transistor106and the ON state of the transfer transistor103are superimposed. The control pulse pRES is supplied to the gate of the reset transistor106to switch between the ON state and the OFF state.

The selection transistor107makes signals of a plurality of pixels provided on a single signal line115output from each one pixel or each of a plurality of pixels at a time. The drain of the selection transistor107is connected to the source of the amplifying transistor105, and the source of the selection transistor107is connected to the signal line115.

Alternatively, the selection transistor107may be provided between the drain of the amplifying transistor105and a power supply line to which a power supply voltage is supplied. In any of these cases, the selection transistor107controls electrical connection of the amplifying transistor105and the signal line115. The control pulse pSEL is supplied to the gate of the selection transistor107to switch between the ON state and the OFF state of the selection transistor107.

Alternatively, instead of providing the selection transistor107, a selected state and a non-selected state may be switched by connecting the source of the amplifying transistor105to the signal line115and switching a potential of the drain of the amplifying transistor105or the gate of the amplifying transistor105.

An equivalent circuit is not limited to that described above, and a part of the configuration may be shared by a plurality of pixels. The present embodiment is applicable to both an image pickup apparatus of front-side irradiation type in which light enters from a front side, and an image pickup apparatus of back-side irradiation type in which light enters from a back side. The same applies to the following embodiments.

A plurality of pixels arranged in the pixel unit100of the image pickup apparatus10of the present embodiment are disposed in an unillustrated well of first conductivity type. Some pixels among a plurality of pixels are provided with a well contact region which provides a reference potential to the wells.

FIG. 3Aillustrates an element isolation region306and active regions201to203separated by the element isolation region306. The element isolation region306is disposed to separate the active region201from peripheral elements or peripheral active regions. The element isolation region306may be formed, for example, by an insulator isolation portion formed by a LOCOS process and an STI separation unit. The element isolation region306may be a high-concentration P-type semiconductor region. Hereinafter, description is made in which the insulator isolation portion formed by the LOCOS process is used as the element isolation region.

FIG. 3Billustrates a state where a gate electrode is disposed on each active region ofFIG. 3A. The reference numerals of the active regions (201to203) inFIG. 3Aare omitted inFIG. 3B. The photoelectric conversion unit102and the FD104are disposed in the active region201. Each of the source regions and the drain regions of the amplifying transistor105, the reset transistor106, and the selection transistor107are disposed in the active region202. The well contact region110is disposed in the active region203.

The active region201and the active region202are arranged in a first direction. The active region202is elongated in a second direction different from the first direction (typically, a direction which crosses perpendicularly the first direction) when seen in a plan view. The active region202and the active region203are arranged in the second direction.

FIG. 4is a schematic plan view of the pixel unit100in which a plurality of pixels101illustrated inFIG. 3Bare arranged. Four (2×2) pixels are illustrated inFIG. 4. No well contact region110is provided for the left two pixels whereas a well contact region110is provided for each of the right two pixels. In the configuration illustrated inFIG. 4, the well contact region110is provided every two pixels.

In the present embodiment, a mask having openings above the source region of the reset transistor106, the FD104, the element isolation region disposed between the source region of the reset transistor106and the well contact region110, the element isolation region disposed between the FD104and the well contact region110, and the well contact region110is used. As an example, description is made with reference to a mask which covers a region that becomes the photoelectric conversion unit102and has openings in other regions. Impurity ions implantation is conducted to the FD104of the active region201, and the source region and the drain region of each transistor of the active region202using the mask.

Although not illustrated, a plurality of pixels are arranged in a P-type well307inFIG. 5A. In the pixel101, the semiconductor regions which constitute the source region and the drain region of each transistor and the well contact region110are disposed in the well. A P-type semiconductor region305with high impurity concentration is disposed below the element isolation region306as a channel stop region. The P-type semiconductor region, constituted by P-type semiconductor regions314,315and318, is disposed in the well contact region110.

The P-type semiconductor region disposed in the well contact region110is connected to a contact plug322to which a predetermined voltage is supplied, and supplies a predetermined voltage to the well307. The voltage supplied to the well307is, for example, a ground voltage. A P-type semiconductor region316with impurity concentration lower than those of the P-type semiconductor regions314and315is disposed between the P-type semiconductor region305below the element isolation region306and the P-type semiconductor region315.

An N-type semiconductor region310b(“first semiconductor region”) is disposed in one of the regions adjacent to the well contact region110via the element isolation region306. The N-type semiconductor region310bconstitutes the source region of the reset transistor106and constitutes a part of the input node of the amplifying transistor105. An N-type semiconductor region310aand an N-type semiconductor region312constitute a drain region of the reset transistor106, and a gate electrode309constitutes the gate electrode of the reset transistor106.

An N-type semiconductor region310c(“first semiconductor region”) is disposed in the other of the regions adjacent to the well contact region110via the element isolation region306. The N-type semiconductor region310cconstitutes the FD104and constitutes a part of the input node of the amplifying transistor105. The FD104also constitutes a drain region of the transfer transistor103, and a gate electrode324constitutes the gate electrode of the transfer transistor103.

FIG. 5Billustrates a cross section of a pixel101where no well contact region110is disposed. The element isolation region306is disposed in the region corresponding to the region in which the well contact region110is disposed inFIG. 5A. Other configurations are the same as that ofFIG. 5A.

Next, a process of manufacturing the image pickup apparatus in the cross section ofFIGS. 5A and 5Bis described with reference toFIGS. 6A to 6C. The order of the process steps may be changed unless otherwise specified. Well-known manufacturing methods are applicable to the process steps which are not specified.

The left diagrams inFIGS. 6A to 6Cillustrate processes of manufacturing a region along line A-B ofFIG. 4, and the right diagrams ofFIGS. 6A to 6Cillustrate processes of manufacturing a region along line C-D ofFIG. 4.

InFIG. 6A, a silicon oxide film302, a polysilicon film303, and a silicon nitride film304are formed in this order on a semiconductor substrate299to form a laminated film including these three films, and then a part of the laminated film is patterned. The portion from which the laminated film is removed by the patterning becomes the element isolation region306later. The conductivity type of the semiconductor substrate299may be N-type or P-type. The semiconductor substrate299may be a substrate with an epitaxial layer formed on a surface thereof.

InFIG. 6B, ion implantation is conducted in parallel with the normal line of a principal surface of the semiconductor substrate299ofFIG. 6A. Specifically, using the laminated film as a mask, a P-type semiconductor region298is formed on the semiconductor substrate299by conducting P-type ion implantation at the opening formed by removing the laminated film (“intermediate B”). The P-type semiconductor region298becomes a part of the channel stop region later. The principal surface is a surface of the semiconductor substrate299on which the element isolation region is formed.

Next, inFIG. 6C, the element isolation region306is formed by the LOCOS process in which the semiconductor substrate300and the entire laminated film are heated (“intermediate C”). The region in which the element isolation region306is not formed becomes the active region.

Next, as illustrated inFIG. 7A, impurity implantation is conducted to the entire pixel unit100of the semiconductor substrate300to obtain the semiconductor substrate301in which the P-type well307is formed (“intermediate D”). The P-type well307may be formed only in the pixel unit100, or may be formed also in the peripheral circuit region disposed around the pixel unit100.

If the P-type well307is formed only in the pixel unit100, it is only necessary to conduct the ion implantation ofFIG. 7Ausing the mask with the peripheral circuit region being shielded. In this case, the P-type well different from the P-type well307is formed in the peripheral circuit region by conducting ion implantation using the mask with the pixel unit100being shielded before or after the impurity implantation process ofFIG. 7A. If the N-type well is needed in the peripheral circuit region, it is only necessary to conduct the N-type ion implantation at the peripheral circuit region to form the N-type well using a mask with the regions in which the pixel unit and the P-type well of the peripheral circuit region will be formed being shielded.

Next, as illustrated inFIG. 7B, an insulating film296is formed above the entire intermediate D. The insulating film296may be formed by various methods. The insulating film296may be desirably silicon oxide film or silicon nitride film, which can be formed by, for example, thermal oxidation and CVD. A polysilicon film297is formed on the insulating film296(“intermediate E”).

Next, as illustrated inFIG. 7C, the gate electrodes309and324and gate insulating films308and323are formed by removing a part of the region of the polysilicon film297of the intermediate E and the insulating film296by patterning. A part of the gate electrode324is not illustrated. The gate electrode309is disposed above a predetermined position of the active region and becomes the gate electrode of the reset transistor106, and the gate electrode324becomes the gate electrode of the transfer transistor103(“intermediate F”).

Next, as illustrated inFIG. 8A, ion implantation is conducted from an oblique angle to the normal line of the principal surface of the semiconductor substrate to the intermediate F using the gate electrodes309and324as the mask (“first process”). Specifically, rotational ion implantation is conducted at an angle inclined from20to 70 degrees to the normal line of the principal surface of the semiconductor substrate. The dosage at this time is 2.5×1012atoms/cm2≦D1≦2.5×1014atoms/cm2.

With this ion implantation, the N-type semiconductor regions310a,310b,310c, and310dare formed. The ion implantation is conducted in a state where the region which becomes the photoelectric conversion unit is shielded using a mask (“first mask”) formed by, for example, unillustrated photoresist.

The first mask may be disposed above the gate electrode324. The first mask has an opening in a region which becomes the well contact region110in the pixel which has the well contact region110. The first mask also has openings corresponding to the element isolation region306disposed between the region which becomes the FD104and the region which becomes the well contact region110, and the element isolation region306disposed between the region which becomes the source of the reset transistor106and the region which becomes the well contact region110. Also in a pixel which has no well contact region110, the first mask has an opening at the same position as the pixel having a well contact region110.

Therefore, a part of the region of the source region and the drain region of the reset transistor106and the FD104are formed by self-alignment formation. The N-type semiconductor region310aconstitutes a part of a low-concentration region of the drain region of the reset transistor106, and the N-type semiconductor region310bconstitutes the source region of the reset transistor106. The N-type semiconductor region310cis the low-concentration N-type semiconductor region which becomes the FD. The N-type semiconductor region310dis an N-type semiconductor region disposed in the region which becomes the well contact region110. A part or the entire N-type semiconductor region310dbecomes the P-type semiconductor region in the subsequent process.

Since the ion implantation conducted inFIG. 8Ais conducted as rotational ion implantation, a part of P-type impurity concentration in the P-type semiconductor region305disposed below the element isolation region306becomes low, and the P-type semiconductor region316is formed (“intermediate G”).

Next, as illustrated inFIG. 8B, the laminated film of the silicon nitride film295and the silicon oxide film294is formed above the entire principal surface in which a gate electrode of an intermediate G is formed. These films are formed by plasma CVD (“intermediate H”).

Next, as illustrated inFIG. 8C, side spacers293are formed on side surfaces of the gate electrode309and the gate electrode324by removing (i.e., etching) the laminated film of the silicon nitride film295and the silicon oxide film294of the intermediate H (“intermediate I”). A part of the side spacer293of the gate electrode324is not illustrated. The side spacers are formed also in other gate electrodes of transistors which are not illustrated.

Next, a mask292is formed as illustrated inFIG. 9A. The mask292shields N-type semiconductor regions310b,310cand310d, a region which becomes the well contact region110, the photoelectric conversion unit102, and the gate electrode324of the intermediate I.

The mask292has openings at portions corresponding to the source region and the drain region of other transistors (i.e., an amplifying transistor and a selection transistor) of the pixel.

Impurity implantation is conducted in parallel with the normal line of the principal surface of the semiconductor substrate using the mask292. The N-type semiconductor region312is formed by self-alignment with respect to the side spacer293(“intermediate J”). Therefore, the source region and the drain region of other transistors of the pixel are formed.

Next, as illustrated inFIG. 9B, a mask291which covers regions except for the region which becomes the well contact region110and has an opening corresponding only to the region which becomes the well contact region110is formed (“second mask”), and P-type ion implantation is conducted (“second process”). The second mask may have an opening above the element isolation region306.

The dosage may be determined under a condition with which the N-type semiconductor region310dbecomes the P-type semiconductor region and may be, for example, 4.0×1014atoms/cm2≦D24.016atoms/cm2. Therefore, a P-type semiconductor region (“second semiconductor region”) is formed in the region which becomes the well contact region110. The second semiconductor region is constituted by the P-type semiconductor region315disposed on the front surface side of the semiconductor substrate301, and the P-type semiconductor region314disposed at a deeper position of the semiconductor substrate than the P-type semiconductor region315.

The P-type semiconductor region315is formed by conducting P-type ion implantation in the region where the N-type semiconductor region310ddisposed in the process ofFIG. 8Aexists.

The P-type semiconductor region314is formed by conducting P-type impurity ion implantation in the P-type well307. Therefore, P-type impurity concentration in the P-type semiconductor region314is higher than in the P-type semiconductor region315.

N-type impurity ions are implanted in a part of the portion below the element isolation region306in the impurity implantation process ofFIG. 8Aand the P-type semiconductor region316with low impurity concentration is disposed. The P-type ion implantation of this process is conducted in the direction of the normal line to the principal surface of the semiconductor substrate301. Therefore, the P-type semiconductor region316with lower concentration than those of the P-type semiconductor regions305and315is disposed between the P-type semiconductor region315and the P-type semiconductor region305(“intermediate K”).

According to this configuration, an electric field at the end of the element isolation region306can be alleviated. With this configuration, generation of hot carrier amplification can be controlled and noise can be reduced.

In the process ofFIG. 9B, impurity implantation may be conducted in parallel with the normal line of the principal surface of the semiconductor substrate, or may be conducted from an oblique angle to the normal line. However, if the impurity implantation is conducted from an oblique angle to the normal line, the P-type semiconductor region316is not formed.

Next, as illustrated inFIG. 9C, an interlayer insulation film317is formed on the principal surface of the semiconductor substrate301of the intermediate K. The interlayer insulation film317may be formed using, for example, a silicon oxide film, BPSG, and NSG (“intermediate L”).

Next, as illustrated inFIG. 10A, a plurality of contact holes including a contact hole321corresponding to the well contact region110are formed in the interlayer insulation film317of the intermediate L. The plurality of contact holes are formed in the regions corresponding to the regions which become the gate electrode, the source region and the drain region of each transistor, the FD, and the well contact region110(“intermediate M”).

Next, as illustrated inFIG. 10B, a mask319which covers the contact holes except for the contact hole321is formed. Then P-type ion implantation is conducted using the contact hole321disposed in the region corresponding to the well contact region110as a mask.

Therefore, the P-type semiconductor region318is formed at a part of the P-type semiconductor region315. The P-type semiconductor region318may be formed also at a part of the P-type semiconductor region314. The well contact region110is constituted by the P-type semiconductor regions314,315, and318. Impurity concentration of the P-type semiconductor region318is higher than those of the P-type semiconductor regions314,315, and316(“intermediate L”).

Next, as illustrated inFIG. 10C, an electric conductor is embedded in each contact hole to form a contact plug322(“intermediate N”). The contact hole321disposed in the region corresponding to the well contact region110may be covered before this process. In that case, N-type ion implantation may be conducted using a mask with openings in the regions corresponding to the contact holes corresponding to the gate electrode, the source region, and the drain region of each transistor.

Then, after forming a required number of wiring layers by a well-known wiring process, a passivation film, a color filter, and a microlens are formed to complete an image pickup apparatus.

According to the manufacturing method described above, in a case where some of a plurality of pixels101have the well contact region110and others do not, variation in ion implantation when N-type ion implantation is conducted at an oblique angle to the normal line of the principal surface can be reduced. Therefore, variation in impurity concentration distribution of the semiconductor region which constitutes the input node of the amplifying transistor105can be reduced. Therefore, variation in capacitance of the input node of the amplifying transistor can be reduced.

Although the source region of the reset transistor106and the FD104are disposed in different active regions in the present embodiment, this configuration is not restrictive. The source region of the reset transistor106and the FD104may be disposed in the same active region, and may be constituted by the same semiconductor region (“first semiconductor region”).

In the present embodiment, the regions adjacent to the well contact region110via the element isolation region306are the FD104and the source region of the reset transistor106. However, this configuration is not restrictive: for example, the same effect can be provided if a semiconductor region including a switch that can switch capacitance of the input node is disposed in the region adjacent to the well contact region110via the element isolation region306.

Second Embodiment

The present embodiment differs from the first embodiment in the position at which the well contact region110is disposed in the pixel unit100.

The present embodiment differs from the first embodiment in that, as illustrated inFIG. 11, a distance between the well contact region110and the source region of the reset transistor106is shorter than a distance between the well contact region110and the FD104.

In the present embodiment, a process of forming the source region of the reset transistor106and the process of forming the FD104are conducted separately. When forming the source region of the reset transistor106, the region which becomes the well contact region110is not shielded. When forming the FD104, the region which becomes the well contact region110is shielded.

In a semiconductor region in which a distance to the well contact region110is shorter, variation in impurity concentration when the well contact region110is shielded with a mask is larger. Therefore, according to the present embodiment, variation in impurity concentration when forming the source region of the reset transistor106with shorter distance can be reduced.

A method for manufacturing the image pickup apparatus along lines A-B and C-D ofFIG. 11is described with reference toFIGS. 12A and 12B. Processes different from those of the first embodiment are described.

FIG. 12Aillustrates a subsequent state of the intermediate F ofFIG. 7Cof the first embodiment. The region in which the FD104is formed is covered with a mask290, and N-type impurity implantation is conducted in the regions which become the source region and the drain region of each transistor, whereby the N-type semiconductor regions310a,310b, and310dare formed (“intermediate P”). Ion implantation is conducted from an oblique angle to the normal line of the principal surface of the semiconductor substrate in the same manner as the process ofFIG. 8A.

Specifically, rotational ion implantation is conducted at an angle inclined from 20 to 70 degrees to the normal line of the principal surface. The dosage at this time is 2.5×1012atoms/cm2≦D1≦2.5×1014atoms/cm2

The ion implantation is conducted with the photoelectric conversion unit102, the gate of the transfer transistor103, and the FD104being covered using the mask290formed by, for example, photoresist.

The mask290has openings corresponding to a region which becomes the well contact region110, and a region which becomes the source region of the reset transistor106. Further, the mask290has an opening corresponding to the element isolation region306disposed between the region which becomes the well contact region110and a region which becomes the source region of the reset transistor106.

The source region of the reset transistor106can be formed in this process. An opening corresponding to the element isolation region306disposed between the region which becomes the FD104and the region which becomes the well contact region110may be formed.

Since the mask290used in this process is disposed to cover the region which becomes the FD104, N-type impurity implantation is not conducted in the region which becomes the FD104. Since the mask290is disposed not to cover the region which becomes the well contact region110, N-type ion implantation is conducted in the region which becomes the well contact region110.

Next, inFIG. 12B, the source region and the drain region of other transistors (i.e., an amplifying transistor and a selection transistor) of the pixel and the region which becomes the well contact region110are shielded to the intermediate P. Further, the source region of the reset transistor106is shielded. A mask289having openings in the element isolation region306disposed between the region which becomes the well contact region110and the FD104, and in the region which becomes FD104is formed. Then N-type impurity implantation is conducted using the mask289.

Then N-type impurity is implanted in the region in which FD104is formed and the N-type semiconductor region310cis formed (“intermediate Q”). Subsequent processes are the same as those of the first embodiment.

According to the present embodiment, ion implantation is conducted also in the region which becomes the well contact region110when forming a semiconductor region relatively closer to the well contact region110among the semiconductor regions which constitute the input node of the amplifying transistor.

The present embodiment is applicable also to a case where, as illustrated inFIG. 13, a distance between the FD104and the well contact region110is shorter than a distance between the source region of the reset transistor106and the well contact region110. In this case, in the process of forming the FD104, openings corresponding to the region which becomes the well contact region110and the region which becomes the FD104are formed in the mask. Further, an opening corresponding to the element isolation region306disposed between the region which becomes the well contact region110and the region which becomes the FD104is formed.

In the process of forming the source region of the reset transistor106, the region which becomes the well contact region110is shielded. Further, a mask289having openings in the element isolation region306disposed between the region which becomes the well contact region110and the region which becomes the source region of the reset transistor106, and in the region which becomes the source region of the reset transistor106is formed.

According also to the present embodiment, it is possible to reduce variation in impurity concentration in the semiconductor region which constitutes the input node of the amplifying transistor105between the pixel in which the well contact region110is disposed and the pixel in which no well contact region110is disposed. Therefore, it is possible to reduce variation in capacitance of the input node of the amplifying transistor.

This application claims the benefit of Japanese Patent Application No. 2015-006070, filed Jan. 15, 2015 which is hereby incorporated by reference herein in its entirety.