Battery protection circuit and battery device

Provided is a battery protection circuit and a battery device which may be manufactured at lower cost. Before all terminals of a battery protection circuit are each connected to batteries, even when a logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by P-wells due to a connection order in which the batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the P-wells. For this reason, a charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2008-046374 filed on Feb. 27, 2008, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a battery protection circuit for protecting a plurality of batteries connected in series, and to a battery device.

2. Description of the Related Art

Portable devices such as a laptop computer and a cellular phone, in some cases, include a battery device which includes a plurality of batteries connected in series and first and second battery protection circuits. The first battery protection circuit controls charge/discharge of the battery to protect the battery. Should the first battery protection circuit not operate when it is supposed to operate, in order to prevent the battery from igniting due to its overdischarge, the second battery protection circuit stops a function of the battery device. The second battery protection circuit performs the function of ultimately protecting the battery, and thus the battery device may not be used when the second battery protection circuit operates (for example, see JP 2000-295777 A).

More specifically, as illustrated inFIG. 4, a second battery protection circuit10monitors voltages of batteries BAT1to BAT4, and cuts off a fuse20provided in a charge/discharge path when at least any one of the voltages is equal to or more than a predetermined voltage. As a result, the charge/discharge path is interrupted, and the battery device is stopped.

Here, as illustrated inFIG. 4, the second battery protection circuit10includes a parasitic diode which is formed between a P-well12aconnected to an intermediate terminal VC2and an N-substrate. In addition, the second battery protection circuit10includes a parasitic bipolar transistor12in which a base is the N-substrate, an emitter is the P-well12a, and a collector is a P-well12b. Moreover, it is assumed that a positive electrode terminal of the battery BAT1at the uppermost stage is a power supply terminal VDD, a negative electrode terminal of the battery BAT4at the lowermost stage is a ground terminal VSS, and terminals of the batteries BAT2and BAT3are intermediate terminals VC1to VC3.

Then, for example, when only the intermediate terminal VC2and the ground terminal VSS are connected to the batteries, a forward current flows from the intermediate terminal VC2to the power supply terminal VDD via the parasitic bipolar diode, and the parasitic bipolar transistor12operates in response to the forward current (base current), whereby a logical circuit11malfunctions in some cases. Due to this malfunction, in some cases, the second battery protection circuit10outputs a signal for making the battery device unusable.

Accordingly, limitations should be placed on an order of connecting the respective terminals of the second battery protection circuit10to the respective batteries, whereby a manufacturing process for the battery device is complicated to reduce a yield, leading to an increase in manufacturing cost for the battery device.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above-mentioned problem, and therefore an object thereof is to provide a battery protection circuit and a battery device which may be manufactured at lower cost.

In order to solve the above-mentioned problem, the present invention provides a battery protection circuit for protecting a plurality of batteries connected in series, including: a power supply terminal to which a positive electrode terminal of the battery at an uppermost stage among the plurality of batteries is connected via a switch group; a ground terminal to which a negative electrode terminal of the battery at a lowermost stage among the plurality of batteries is connected via the switch group; an intermediate terminal to which a connection point between the adjacent batteries among the plurality of batteries is connected via the switch group; a plurality of monitoring circuits for monitoring voltages of the plurality of batteries; a logical circuit for operating so that a charge/discharge path of the plurality of batteries is interrupted when the voltages of the plurality of batteries are equal to or higher than a predetermined voltage; a first well which is provided at the intermediate terminal; a second well which is not provided at the intermediate terminal but provided in a vicinity of the first well; and a third well which is not provided at the intermediate terminal but provided in the vicinity of the first well so as to surround the first well.

Further, in order to solve the above-mentioned problem, the present invention provides a battery device including: a battery protection circuit for protecting a plurality of batteries connected in series, which includes: a power supply terminal to which a positive electrode terminal of the battery at an uppermost stage among the plurality of batteries is connected via a switch group; a ground terminal to which a negative electrode terminal of the battery at a lowermost stage among the plurality of batteries is connected via the switch group; and an intermediate terminal to which a connection point between the adjacent batteries among the plurality of batteries is connected, and further includes: a plurality of monitoring circuits for monitoring voltages of the plurality of batteries; a logical circuit for operating so that a charge/discharge path of the plurality of batteries is interrupted when voltages of the plurality of batteries are equal to or more than a predetermined voltage; a first well which is provided at the intermediate terminal; a second well which is not provided at the intermediate terminal but provided in a vicinity of the first well; and a third well which is not provided at the intermediate terminal but provided in the vicinity of the first well so as to surround the first well; the plurality of batteries; and the switch group.

According to the present invention, before all the respective terminals of the battery protection circuit are connected to the respective batteries, even when the logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by the first well and the second well due to a connection order in which the respective batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the first well and the third well. As a result, the charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order, whereby a manufacturing process of the battery device is simplified to increase a yield, and a manufacturing cost for the battery device is reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

First, a configuration of a battery protection circuit is described.FIG. 1is a diagram illustrating the battery protection circuit.FIG. 2is a layout diagram illustrating the battery protection circuit.

A battery device includes batteries BAT1to BAT4, switches SW1to SW5, a battery protection circuit30, and a fuse20. The battery protection circuit30includes a power supply terminal VDD, intermediate terminals VC1to VC3, a ground terminal VSS, and an output terminal VOUT. In addition, the battery protection circuit30includes a pull-down resistor34, comparator circuits36to39, reference voltage circuits36ato39a, and a logical circuit31. The logical circuit31includes a reset circuit31a. The comparator circuits and the reference voltage circuits function as a monitoring circuit.

The comparator circuit38includes a P-well32aand a P-well33b. The logical circuit31includes a P-well32b. The battery protection circuit30includes a parasitic diode which is formed between the P-well32aconnected to the intermediate terminal VC2and an N-substrate. In addition, the battery protection circuit30includes a parasitic bipolar transistor32in which a base is the N-substrate, an emitter is the P-well32a, and a collector is the P-well32b. Moreover, the battery protection circuit30includes a parasitic bipolar transistor33in which a base is the N-substrate, an emitter is the P-well32a, and a collector is the P-well33b.

The batteries BAT1to BAT4are connected in series in the stated order. A positive electrode terminal of the battery BAT1is connected to the power supply terminal VDD via the switch SW1. A positive electrode terminal of the battery BAT2is connected to the intermediate terminal VC1via the switch SW2. A positive electrode terminal of the battery BAT3is connected to the intermediate terminal VC2via the switch SW3. A positive electrode terminal of the battery BAT4is connected to the intermediate terminal VC3via the switch SW4. A negative electrode terminal of the battery BAT4is connected to the ground terminal VSS via the switch SW5. Moreover, the positive electrode terminal of the battery BAT1is connected to a charger (not shown) or a load (not shown) via the fuse20. The power supply terminal VDD, the intermediate terminal VC1, the intermediate terminal VC2, and the intermediate terminal VC3are connected to non-inverting input terminals of the comparator circuits36to39, respectively. Output terminals of the reference voltage circuits36ato39aare connected to inverting input terminals of the comparator circuits36to39, respectively. Output terminals of the comparator circuits36to39are each connected to input terminals of the logical circuit31. An output terminal of the logical circuit31is connected to the output terminal VOUT. The fuse20is provided between the output terminal VOUT and the positive electrode terminal of the battery BAT1.

In the parasitic bipolar transistor32, the base is connected to the power supply terminal VDD, the emitter is connected to the P-well32a, and the collector is connected to the P-well32b. In the parasitic bipolar transistor33, the base is connected to the power supply terminal VDD, the emitter is connected to the P-well32a, and the collector is connected to the P-well33b. The P-well32ais connected to the intermediate terminal VC2. One end of the pull-down resistor34is connected to the ground terminal VSS, and the other end thereof is connected to the P-well33band an input terminal of the reset circuit31a.

It should be noted that, between the power supply terminal VDD and the logical circuit31, there is provided a voltage regulator (not shown) for generating a constant voltage which is lower than a voltage of the power supply terminal VDD. In addition, between the comparator circuits36to39and the logical circuit31, there is provided a level shifter circuit (not shown) for shifting output voltages of the comparator circuits36to39to lower levels. Moreover, between the logical circuit31and the output terminal VOUT, there is provided another level shifter circuit (not shown) for shifting an output voltage of the logical circuit31to a higher level.

Here, the P-well32ais provided at the intermediate terminal VC2. The P-well32bis not provided at the intermediate terminal VC2but provided in the vicinity of the P-well32a. The P-well33bis not provided at the intermediate terminal VC2but provided in the vicinity of the P-well32aso as to surround the P-well32a.

The reset circuit31ais designed so that a voltage of the input terminal thereof becomes high when a voltage of the P-well33bis substantially equal to a voltage of the intermediate terminal VC2.

The reference voltage circuits36ato39agenerate reference voltages. Based on the reference voltages, the reference voltage circuit36aand the comparator circuit36, the reference voltage circuit37aand the comparator circuit37, the reference voltage circuit38aand the comparator circuit38, and the reference voltage circuit39aand the comparator circuit39monitor voltages of the batteries BAT1to BAT4, respectively. When the voltages of the batteries BAT1to BAT4are equal to or higher than the reference voltages, the logical circuit31operates so that a charge/discharge path of the batteries BAT1to BAT4is interrupted.

Power supply voltages of the comparator circuits36to39and the reference voltage circuits36ato39aare the voltage of the power supply terminal VDD. That is, the comparator circuits36to39and the reference voltage circuits36ato39aare located in a high-voltage region. The power supply voltage of the logical circuit31is a constant voltage which is lower than the voltage of the power supply terminal VDD, which is generated by the voltage regulator. In other words, the logical circuit31is located in a low-voltage region.

Further, the battery protection circuit30is formed on the N-substrate.

Next, a description is given of an operation of the battery protection circuit30in a case where the intermediate terminal VC2is connected before the power supply terminal VDD is connected, the battery protection circuit30is being connected to the batteries BAT1to BAT4, only the switch SW3and the switch SW5are turned on, the intermediate terminal VC2is connected to the positive electrode terminal of the battery BAT3, and the ground terminal VSS is connected to the negative electrode terminal of the battery BAT4.

The P-well32ahas the highest voltage in the battery protection circuit30, and thus the forward current flows from the intermediate terminal VC2to the power supply terminal VDD via the parasitic diode, and the parasitic bipolar transistor32operates in response to the forward current (base current). Accordingly, a current flows from the P-well32aserving as the emitter to the P-well32bserving as the collector, and the voltage of the P-well32bbecomes the voltage of the intermediate terminal VC2.

At this time, the parasitic bipolar transistor33operates in the similar manner as described above, and thus a current flows from the P-well32aserving as the emitter to the P-well33bserving as the collector, and a voltage of the P-well33balso becomes the voltage of the intermediate terminal VC2. As a result, a voltage of the input terminal of the reset circuit31abecomes high. Then, the reset circuit31aforcibly resets a given flip flop (not shown) or the like contained in the logical circuit31, whereby the logical circuit31is reset, and the logical circuit31does not output a signal for making the battery device unusable.

Here, the voltage of the intermediate terminal VC2becomes substantially equal to the voltage of the power supply terminal VDD by means of the parasitic bipolar transistors32and33. The voltage of the power supply terminal VDD is the power supply voltage of the logical circuit31and the reset circuit31a, and thus the voltage of the intermediate terminal VC2becomes the power supply voltage of the logical circuit31and the reset circuit31a. Therefore, when the voltage of the P-well33bbecomes substantially equal to the voltage of the intermediate terminal VC2, the logical circuit31and the reset circuit31arecognize that the voltage of the P-well33bbecomes high.

Next, a description is given of the operation of the battery protection circuit30in a case where the battery protection circuit30has been connected to the batteries BAT1to BAT4, the switches SW1to SW5are turned on, the ground terminal VDD is connected to the positive electrode terminal of the battery BAT1, the intermediate terminals VC1to VC3are connected to the positive electrode terminals of the batteries BAT2to BAT4, respectively, and the ground terminal VSS is connected to the negative electrode terminal of the battery BAT4.

The N-substrate has the highest voltage in the battery protection circuit30, and thus the forward current does not flow from the intermediate terminal VC2to the power supply terminal VDD via the parasitic diode, and the parasitic bipolar transistors32and33do not operate. Accordingly, the current is consumed less by that amount. Here, the pull-down resistor34pulls down the P-well33b, whereby the voltage of the P-well33bis determined around the ground voltage.

The batteries BAT1to BAT4are charged, and thus the voltages of the batteries BAT1to BAT4are increased. When the voltage of any one of the batteries BAT1to BAT4, for example, the voltage of the battery BAT3is equal to or higher than the reference voltage of the reference voltage circuit38a, an output voltage of the comparator circuit38becomes high. At this time, the battery BAT3is in an overcharged state. Delay processing or the like is performed on a high signal indicating the above by the logical circuit31, and the high signal is output from the output terminal VOUT as an overcharge detection signal.

During the delay processing performed by the logical circuit31, when the voltage of the battery BAT3is smaller than the reference voltage of the reference voltage circuit38a, the output voltage of the comparator circuit38becomes low. At this time, the battery BAT3is in a normal state. A low signal indicating the above is input to the input terminal of the reset circuit31aas an overcharge detection release signal.

As a result, before all the terminals of the battery protection circuit30are each connected to the batteries BAT1to BAT4, even when the logical circuit31malfunctions by the operation of the parasitic bipolar transistor32formed of the P-well32aand the P-well32bdue to a connection order in which the batteries BAT1to BAT4are connected, the logical circuit31is reset by the operation of the parasitic bipolar transistor33formed of the P-well32aand the P-well33b. For this reason, the charge/discharge path of the batteries BAT1to BAT4is not interrupted due to the connection order of the batteries BAT1to BAT4. Accordingly, limitations are not placed on the connection order, whereby a manufacturing process of the battery device is simplified and a yield is increased. Therefore, a manufacturing cost for the battery device is reduced.

The logical circuit31does not malfunction simply through the provision of the P-well33band the pull-down resistor34, and thus device isolation is not required so as to prevent the logical circuit31from malfunctioning by employing a complicated manufacturing process. Therefore, the complicated manufacturing process is not required, which reduces the manufacturing cost.

It should be noted thatFIG. 2illustrates only the parasitic diode and the parasitic bipolar transistor provided for the intermediate terminal VC2, but, in reality, there are also formed parasitic diodes (not shown) and parasitic bipolar transistors (not shown) provided for the intermediate terminal VC1and the intermediate terminal VC3. At this time, respective P-wells connected to the respective intermediate terminals may be surrounded by one P-well, or may be each surrounded by a different P-well.

The P-well32bis included in the logical circuit31, but may be included in the reference voltage circuit or the comparator circuit.

Four batteries are used inFIG. 2, but batteries of less than four or equal to or more than five may be used. At this time, in accordance with the number of the batteries, there are provided a switch, an intermediate terminal, and a P-well which surrounds a P-well connected to the intermediate terminal.

In a case where a circuit design is made so that the overcharge detection release signal is a high signal, a node of the overcharge detection release signal may be connected to the P-well33b. At this time, even when the overcharge detection release signal is output or even when the voltage of the P-well33bbecomes high, the logical circuit31does not output a signal for making the battery device unusable.

An output terminal of other component having a reset function may be connected to the P-well33bas well. At this time, even when the reset function of the other component works or even when the voltage of the P-well33bbecomes high, the logical circuit31does not output the signal for making the battery device unusable.

The battery protection circuit30is formed on the N-substrate, and the power supply terminal VDD, the intermediate terminals VC1to VC3, and the ground terminal VSS are connected to the batteries BAT1to BAT4in the stated order, respectively, whereby the logical circuit31does not output the signal for making the battery device unusable.

The battery protection circuit30is formed on a P-substrate, and the ground terminal VSS, the intermediate terminals VC3to VC1, and the power supply terminal VDD are connected to the batteries BAT4to BAT1in the stated order, respectively, whereby the logical circuit31does not output the signal for making the battery device unusable.

Second Embodiment

The battery protection circuit30is formed on the N-substrate inFIG. 2, but as illustrated inFIG. 3, a battery protection circuit40may be formed on a P-substrate. Then, the parasitic bipolar transistor is a PNP bipolar transistor inFIG. 2, but is an NPN bipolar transistor inFIG. 3. In addition, the fuse20is provided between the output terminal VOUT and the positive electrode terminal of the battery BAT1inFIG. 2, but is provided between the output terminal VOUT and the negative electrode terminal of the battery BAT4.

First, a configuration of the battery protection circuit is described.FIG. 3is a layout diagram illustrating the battery protection circuit.

A battery device includes batteries BAT1to BAT4, switches SW1to SW5, the battery protection circuit40, and the fuse20. The battery protection circuit40includes a power supply terminal VDD, intermediate terminals VC1to VC3, a ground terminal VSS, and an output terminal VOUT. In addition, the battery protection circuit40includes a pull-up resistor44, comparator circuits (not shown), reference voltage circuits (not shown), and a logical circuit41. The logical circuit41includes a reset circuit41a. The comparator circuits and the reference voltage circuits function as a monitoring circuit.

The comparator circuit includes an N-well42aand an N-well43b. The logical circuit41includes an N-well42b. The battery protection circuit40includes a parasitic diode which is formed between the N-well42aconnected to the intermediate terminal VC2and the P-substrate. In addition, the battery protection circuit40includes a parasitic bipolar transistor42in which a base is the P-substrate, an emitter is the N-well42a, and a collector is the N-well42b. Moreover, the battery protection circuit40includes a parasitic bipolar transistor43in which a base is the P-substrate, an emitter is the N-well42a, and a collector is the N-well43b.

Here, the N-well42ais provided at the intermediate terminal VC2. The N-well42bis not provided at the intermediate terminal VC2but provided in the vicinity of the N-well42a. The N-well43bis not provided at the intermediate terminal VC2but provided in the vicinity of the N-well42aso as to surround the N-well42a.

The reset circuit41ais designed so that a voltage of an input terminal of the reset circuit41abecomes low when a voltage of the N-well43bis substantially equal to a voltage of the intermediate terminal VC2.

Next, a description is given of an operation of the battery protection circuit40in a case where the intermediate terminal VC2is connected before the ground terminal VSS is connected, the battery protection circuit40is being connected to the batteries BAT1to BAT4, only the switch SW1and the switch SW3are turned on, the power supply terminal VDD is connected to a positive electrode terminal of the battery BAT1, and the intermediate terminal VC2is connected to a positive electrode terminal of the battery BAT3.

A voltage of the N-well42abecomes the voltage of the intermediate terminal VC2, and a voltage of the P-substrate becomes higher than a voltage of the N-well42a, whereby a forward current flows from the ground terminal VSS to the intermediate terminal VC2via the parasitic diode, and the parasitic bipolar transistor42operates in response to the forward current (base current). Accordingly, a current flows from the N-well42bserving as the collector to the N-well42aserving as the emitter, and a voltage of the N-well42bbecomes the voltage of the intermediate terminal VC2.

At this time, the parasitic bipolar transistor43also operates in the similar manner as described above, a current flows from the N-well43bserving as the collector to the N-well42aserving as the emitter, a voltage of the N-well43balso becomes the voltage of the intermediate terminal VC2, and the voltage of the input terminal of the reset circuit41abecomes low. As a result, the reset circuit41aforcibly resets a given flip flop (not shown) or the like contained in the logical circuit41. Accordingly, the logical circuit41is reset, and does not output a signal for making the battery device unusable.