Over-limit electrical condition protection circuits and methods

Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

TECHNICAL FIELD

Embodiments of the invention relate generally to integrated circuits, and more particularly, in one or more of the illustrated embodiments, to protection circuitry for over-limit electrical conditions that may damage the integrated circuits.

BACKGROUND OF THE INVENTION

Integrated circuits are connectable to “the outside world” through input nodes, output nodes, or input/output nodes such as bond pads, input pads, input/output pins, die terminals, die pads, or contact pads. Circuitry is often interposed between such nodes and active circuitry of the integrated circuit. The circuitry typically includes transistors which should be protected from over-limit electrical conditions. This may be especially true for circuits that include field-effect transistors (FETs), which are formed having a gate insulator. An uncontrolled over-limit electrical event may subject the gate insulator to a relatively high voltage that exceeds a breakdown voltage that causes permanent damage to the transistor.

An electrostatic discharge event during which the circuitry is subjected to an electrostatic discharge (ESD) is an example of an over-limit electrical condition that may cause damage to the circuitry of the integrated circuit unless adequately protected. Another example of an over-limit electrical condition for example, latch-up, may result from an “overdrive condition,” An overdrive condition exists when voltages or currents at an electrical node exceed specified levels, such as a manufacturer's specification of the “normal” operating parameters for the device. Overdrive conditions can be contrasted with what is typically referred to as a normal operating conditions, that is, conditions specified by a semiconductor device manufacturer to be within specified limits. Circuitry subjected to an overdrive condition may conduct current inadvertently and without control over the current path or the magnitude of current conducted. It is desirable, however, that circuitry is designed to withstand an occasional or even sustained overdrive condition without adverse consequences. Uncontrolled overdrive conditions, in contrast, may cause over-limit electrical conditions that may damage circuitry, and consequently, should be avoided.

Typically, an over-limit protection circuit is connected to a node, such as a bond pad, that may be subjected to an over-limit electrical condition in order to protect circuitry also coupled to the node. Typical over-limit electrical condition protection circuits include circuitry that provide a low-impedance conductive path from the node to a reference voltage, such as ground, to dissipate the over-limit electrical condition before operational circuitry also coupled to the node are damaged. For example, the over-limit protection circuit keeps the potential of the bond pad from exceeding a maximum value.

Many of the protection circuits include circuits that exhibit a “snap-back” characteristic. Generally, a snap-back characteristic provides a trigger condition which when exceeded, causes the circuit to enter a low-impedance state. The low-impedance state is maintained while the electrical condition on a node exceeds a hold condition. In designing an adequate protection circuit using a snapback circuit, the trigger condition for the snapback circuit must be appropriate for the electrical conditions the node will experience under normal operating conditions. For example, the trigger conditions should be sufficiently high to prevent the protection circuit from inadvertently triggering but low enough to trigger before operational circuitry coupled to the node are subjected to damaging over-limit electrical conditions. An example of a node that will be subjected to relatively high voltages during normal operation are high-voltage (HV) pads which are used to provide circuitry relatively high-voltages during normal operation. Over-limit protection circuitry for such pads should be designed to avoid triggering when the expected operating voltage is provided to the pad but nonetheless trigger at an over-limit electrical condition below that which will damage circuitry coupled to the pad.

Examples of conventional circuits having snapback characteristics include thyristors, such as silicon controlled rectifiers (SCRs), and overdriven metal-oxide-semiconductor (MOS) transistors, and diodes. Examples of conventional circuits having a set trigger condition, and typically a set hold condition as well, include diode-triggered SCRs (DTSCRs). Once set, however, adjusting (e.g. changing, altering, etc.) the trigger condition often requires redesign of the protection circuit. That is, the protection circuits are typically “hard-wired” and are not modified after the integrated circuit is fabricated. Moreover, trigger conditions for ESD protection and protection against latch-up conditions are often different, thus, having a protection circuit having a trigger condition set to protect against one condition may be a compromise for protecting against the other over-limit electrical conditions.

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of apparatuses and methods described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1illustrates a over-voltage protection circuit100according to an embodiment of the invention. The protection circuit100is coupled to a protected circuit, for example, protected circuit10, and protect the protected circuit10from being subjected to an over-voltage condition, which as previously discussed, may otherwise damage the circuitry of the protected circuit10. As illustrated inFIG. 1, the protected circuit10is coupled to pad20and a cathode node30. The cathode node30may be coupled to a reference voltage, for example, ground. An over-voltage signal may be inadvertently applied to the pad20, in response to which the protection circuit100is activated and provides a current path to the reference voltage. In the embodiment ofFIG. 1, the protection circuit100is coupled to the pad20and the cathode node30.

The protection circuit100includes a shunt circuit110and a trigger circuit140. The trigger circuit140is configured to trigger the shunt circuit110to provide a current path responsive to an over-voltage being applied to the pad20through which current resulting from the over-voltage may be shunted to protect the protected circuit10from being damaged. Additionally, the shunt circuit110is configured to hold a voltage across the protected circuit10to below a voltage the protected circuit10may be subjected before being damaged.

Protected circuits10may include one or more transistors. Examples of various protected circuits10are illustrated inFIGS. 2A-2D.FIG. 2Aillustrates a driver210having one or more transistors220(1)-220(n) that are used to provide an output signal OUT responsive to respective input signals Ng_1-Ng_n. The transistors220(1)-220(n) are illustrated in the embodiment ofFIG. 2Aas n-channel field effect transistors (nFETs).FIG. 2Billustrates a driver230having a one or more transistors240(1)-240(n) that are used to provide an output signal OUT responsive to respective input signals Pg_1-Pg_n. The transistors240(1)-240(n) are illustrated in the embodiment ofFIG. 2Bas p-channel field effect transistors (pFETs). The OUT signal may have a relatively high-voltage provided to the pad20.

FIG. 2Cillustrates a logic circuit250having a pull-up transistor254and a pull-down transistor258. An output signal OUT is provided by the logic circuit250responsive to input signal IN. In the embodiment ofFIG. 2C, the pull-up transistor254is illustrated as a pFET and the pull-down transistor258is illustrated as an nFET.FIG. 2Dillustrates a voltage detect circuit260having diode-coupled transistors270(1)-270(n) series coupled between the pad20and a gate of a detect transistor280. A detection output signal DETOUT based on a detection input signal DETIN may be provided by the detect circuit260responsive to a voltage applied to the pad20exceeding a voltage. The diode-coupled transistors270(1)-270(n) are illustrated in the embodiment ofFIG. 2Das diode-coupled nFETs, and the detect transistor280is illustrated as a nFET. Transistors of different types than those shown in the embodiments ofFIGS. 2A-2Dmay be used as well. The circuits ofFIGS. 2A-2Dhave been provided by way of example and the invention is not limited to the specific examples of protected circuits10described.

Returning toFIG. 1, the shunt circuit110includes at least a portion that is formed in a p-well in which at least a portion of the trigger circuit140is formed, which will be described in more detail below. Leakage currents from the trigger circuit140resulting from an over-voltage condition are used to enhance forward biasing of a diode junction of the shunt circuit110, and thus, trigger the shunt circuit110. The p-well is formed in a semiconductive material, such as a semiconductor substrate. As used herein, the term semiconductive material, includes a bulk semiconductive region, an epitaxial layer, a doped well region, and the like.

In some embodiments, the trigger circuit140may trigger the shunt circuit110at a plurality of different trigger conditions. A control circuit160may be coupled to the shunt circuit110and trigger circuit140and a reference voltage node (e.g., ground) to adjust the trigger conditions for the protection circuit100. The trigger conditions may be set responsive to the control signal CNTRL.

A shunt circuit110exhibiting a “snapback” current-voltage (I-V) characteristic may be used to provide the protection circuit100with the same characteristic. A protection circuit100having the snapback characteristic is triggered at a trigger condition to provide a current path to shunt over-voltage current. Once triggered, a voltage across the protection circuit100decreases to a hold condition having a voltage that is less than a voltage for the trigger condition. The lower voltage of the hold condition protects the protected circuit10from being damaged by an over-voltage that exceeds the maximum voltage capability of the protected circuit10.

FIG. 3illustrates snapback characteristics for two conditions of a CNTRL signal applied to the trigger circuit140ofFIG. 1. In particular, a first I-V curve310represents the response of the protection circuit100for a CNTRL signal having a first voltage and a second I-V curve320represents the response of the protection circuit100for a CNTRL signal having a second voltage. Each of the I-V curves exhibits a respective trigger condition, trig1and trig2, and a hold condition hold1and hold2. The trigger and hold conditions represent current-voltage conditions to trigger the snapback response of the protection circuit100and to maintain the snapback condition. Circuits having the general snapback response as illustrated inFIG. 3that may be used for the shunt circuit110of the protection circuit100are known by those ordinarily skilled in the art. Such shunt circuits110may be implemented using conventional snapback circuits or snapback circuits later developed.

The I-V curves ofFIG. 3may be used to illustrate an example relationship of the protection circuit100where the CNTRL signal is used to control the control circuit160to adjust added resistance through the control circuit160. The I-V curve associated with a CNTRL=V2exhibits a greater trigger condition (trig2) as well as a greater hold condition (hold2) relative to the I-V curve associated with a CNTRL=V1having trigger condition trig1and hold condition hold1. The increase in the trigger and hold conditions from trig1/hold1to trig2/hold2result from decreasing the added resistance through the control circuit160.

In some embodiments of the invention, the control circuit160is used during power-up of an integrated circuit in which the protection circuit is included. For example, when the integrated circuit having an embodiment of the invention is unpowered, the CNTRL signal controls the control circuit160to add a relative large resistance between the trigger circuit140and the reference voltage. As previously discussed, under this condition, the trigger voltage may be lowered for the protection circuit100. An advantage to a lowered trigger voltage is that it will provide greater over-voltage/over-current protection to the protected circuit10in the event a relatively high-voltage and/or current is applied to the pad20. That is, less voltage and/or current is necessary to trigger the protection circuit100to discharge the over-voltage/over-current. An example of an event that presents relatively high-voltage and/or current to a node is an ESD impulse.

Following power-up of the integrated circuit, the CNTRL signal is adjusted to control the control circuit160to reduce the additional resistance provided by the control circuit160. As previously described, the decrease in resistance between the trigger circuit140and the reference voltage results in an increase to the trigger condition and the hold condition of the protection circuit100. The increased hold condition increases latch-up immunity of the protection circuit100. In some embodiments, the CNTRL signal is adjusted to increase the hold condition to approximately two-three times the operating voltage of the integrated circuit. For example, where the operating voltage for an integrated circuit is 1.0 V, the control circuit160is adjusted to provide a hold condition approximately 2.0-3.0 V. As previously described, the CNTRL signal can be adjusted to modulate the performance characteristics of the protection circuit100to provide the desired hold condition. The increased hold condition may prevent the ESD devices from triggering based on acceptably normal power spikes that may occur during certain operation cycles. If the power spike has relatively high voltage and/or current levels that can induce damages to the integrated circuits, or if there is an ESD event, the control circuits may capture these changes, and switch mode to low trigger/hold voltage levels.

As described by the previous example, operating the protection circuit100through the use of the control circuit160in such a manner can provide both the relatively high voltage requirements to prevent latch-up and the relatively low trigger-current needed for ESD protection. In other embodiments, the control circuit160is not operated in a binary-type manner of providing either maximum added resistance or minimum resistance. The control circuit160may be additionally or alternatively adjusted continuously over the range of the available impedance using the CNTRL signal. In this manner, the added resistance, and consequently, the trigger condition for the protection circuit100, can be adjusted to a desired level within the available range of modulation provided by the control circuit160.

A shunt circuit400according to an embodiment of the invention is illustrated inFIG. 4. The shunt circuit400may be used as the shunt circuit110of the protection circuit100ofFIG. 1. The shunt circuit400is a thyristor, such as a silicon controlled rectifier (SCR). As known and as illustrated inFIG. 4, an SCR is formed by a combination of PNP-NPN bipolar junction transistors (BJTs)410,420. The resulting circuit may be represented as three diodes440,450, and460coupled between the pad20and cathode node30, as illustrated inFIG. 4. The diode460may be integrated with trigger circuit by being formed in a common well, as will be described in more detail below. An example conventional design includes formation of the PNP-BJTs and NPN-BJTs410,420in a p+-region formed in an n-well (i.e., a well region of n-type doping) and a n+-region in p-well (i.e., a well region of p-type doping). In embodiments of the invention utilizing the shunt circuit400as the shunt circuit110, a lateral NPN-BJT420may be formed in an p-well in which a portion of the trigger circuit is formed as well.

In operation, the shunt circuit400is triggered as the base-to-emitter diode of the lateral NPN-BJT420is forward biased. Using conventional designs, the forward bias for the base-to-emitter diode may be approximately 0.6 V at room temperature. The base-to-emitter diode may be forward biased as the voltage of the p-well in which the NPN-BJT420is formed increases as a result of current discharging through the inherent resistance of the p-well. Current may be provided when the voltage across the shunt circuit400causes a reverse-bias breakdown of the junction between the n-well in which the PNP-BJT410is formed and the p-well in which the NPN-BJT420is formed. The typical breakdown voltage for the nwell-pwell junction can be approximately 20 V. Current through the p-well may also be provided from circuits of the trigger circuit formed in the same p-well as the NPN-BJT420, as will be described in more detail below. That is, leakage currents from the trigger circuit resulting from an over-voltage condition may be used to forward bias the base-to-emitter diode of the NPN-BJT420of the shunt circuit400.

FIG. 5illustrates a protection circuit500according to an embodiment of the invention. The protection circuit500is coupled to a protected circuit50, which is shown in the embodiment ofFIG. 5as a high-voltage driver circuit that includes one or more transistors60(1)-60(n). The protected circuit50and the protection circuit500are coupled to a pad20and a cathode node30. The protection circuit500includes a shunt circuit510and a trigger circuit540.

In the embodiment ofFIG. 5, the trigger circuit540is provided by a driver circuit that matches the driver circuit of the protected circuit50. The trigger circuit540includes one or more transistors550(1)-550(n) coupled in series between the pad20and the cathode node30. Each of the transistors550(1)-550(n) correspond to a respective one of the one or more transistors60(1)-60(n) of the protected circuit50. Transistors550have gates coupled to a respective one of transistors60, except for the last transistor550(n). Transistors550and60(other than the last transistor550(n)) have gates coupled together and biased to minimize channel and gate-induced leakage currents. The gate of transistor550(n) and body regions of the transistors550(1)-550(n) are coupled to a control circuit560. The control circuit560is coupled to a reference voltage, for example, ground. The transistor550(n) remains in an “off” state due to the coupling of its gate to ground through the control circuit560. The shunt circuit510includes a SCR having an anode node512and first base node514coupled together, and a second base node516coupled to the body regions of the transistors550(1)-550(n).

The control circuit560is represented by an adjustable resistance in the embodiment ofFIG. 5. The control circuit560may be used to set different voltages at which the trigger circuit540triggers the shunt circuit510. The adjustable resistance of the control circuit560may be used to adjust resistance between the reference voltage and the body regions of the transistors550(1)-550(n) and base node516. Generally, a lower resistance added by the control circuit560results in a higher trigger voltage than for a higher control circuit resistance. Providing the control circuit560allows for base modulation of the SCR of the trigger circuit510, which can be used to adjust the trigger conditions of the protection circuit500.

Using a trigger circuit540that matches the circuitry of the protected circuit50provides a benefit that trigger circuit540will typically trigger the shunt circuit510earlier than when the protected circuit50begins to react to an over-voltage applied to the pad20, thereby preventing the protected circuit50from being damaged by the over-voltage. Trigger circuits matching the various protected circuits illustrated byFIGS. 2A-2Dmay be used in protection circuits coupled to a corresponding protected circuit. In other embodiments of the invention, however, the trigger circuit may not match the protected circuit.

In other embodiments of the ESD protection, trigger circuit540and protected circuit50may be fully or partially merged. A portion of all of the transistors60(1)-60(n) of the protected circuit50may replace the transistors550(1)-550(n) to trigger the shunt circuit510. When transistors60(1)-60(n) replace the original trigger transistors550(1)-550(n), the control circuit may still be used to control the p-well540.

Portions of the shunt circuit510and the trigger circuit540may be formed in the same p-well (e.g., an isolated p-well). For example, the diode460(not shown inFIG. 5) may be formed in the same p-well as the transistors of the trigger circuit540. The trigger circuit540may provide leakage currents under an over-voltage condition that are used to forward bias the diode460of the shunt circuit510.FIG. 6illustrates a cross-sectional drawing of the shunt circuit510and trigger circuit540according to an embodiment of the invention. The protected circuit50is also illustrated inFIG. 6.

A deep n-well610is formed in which p-well630and n-well608are formed. Portions of the shunt circuit510and the trigger circuit540are formed in the p-well630. The protected circuit50is formed in p-well640by n-regions52,54, and56, as well as, gates58and59formed over the p-well640. The n-region52is coupled to cathode node30and the n-region56is coupled to pad20.

The SCR of the shunt circuit510, which as previously discussed, includes back-to-back PNP-BJT and NPN-BJT (e.g., PNP-BJT410and NPN-BJT420ofFIG. 4). A PNP-BJT410is formed by p-region612, the n-well608, and p-well630. An NPN-BJT420is formed by n-well608, p-well630, and n-region632. An n-region614is used to couple the p-region612(i.e., anode of PNP-BJT650) to the n-base/n-collector of n-well608. An externally accessible pad, for example, pad20, is coupled to the p-region612. The n-region632may be used to couple with the cathode of the SCR of the shunt circuit510.

The trigger circuit540is formed by n-regions632,634636, formed in the p-well630, and gates650and652formed over the p-well. In particular, with reference toFIG. 5, the transistor550(1) is formed by n-regions634,636, and gate652, and the transistor550(n) is formed by n-regions632,634, and gate650. The n-region636also provides for coupling the trigger circuit540to the pad20. Body regions of the transistors550(1)-550(n) and the p-base of the NPN-BJT660are represented by p-well630. A p-region638provides an electrical connection to the p-base of the NPN-BJT660and the body of transistors550(1)-550(n) of p-well630. As known, a parasitic p-well resistance, represented inFIG. 6as Rpwell639is present between the p-base of the NPN-BJT420and the p-region638. The p-region638is coupled to a control circuit670(e.g., control circuit560) and to gate650of the transistor550(n), as shown inFIG. 5. The control circuit670is shown schematically inFIG. 6. Those ordinarily skilled in the art, however, have sufficient knowledge to form the control circuit670and to couple the control circuit670to p-well630and to gate650.

In operation, under normal operating conditions the trigger circuit540remains biased in an inactive state by the coupling the gate of transistor550(1) to the gate of transistor60(1), as well as coupling the gate of transistor550(n) to a reference voltage (e.g., ground). When an over-voltage condition occurs, for example, an ESD event which applies relatively high voltage to the pad20, a reverse-bias leakage conducts current from the n-region636(i.e., a drain of the trigger circuit540) to the p-well630, and from the p-well through the control circuit670to the reference voltage. Due to the Rpwell639and the resistance of the control circuit670, the voltage of the p-well630increases. The increase in voltage of the p-well in effect forward biases the emitter-base of the NPN-BJT420, which causes the SCR of the shunt circuit510to conduct from the pad20to the reference voltage. The additional current provides positive feedback to further forward bias the emitter-base. The voltage at the pad20is also controlled to a magnitude that is generally below the voltage at which the trigger circuit540triggered the SCR of the shunt circuit510. Thus, the protected circuit50is protected by maintaining the voltage below the trigger voltage and shunting resulting from an ESD event through the SCR of the shunt circuit510rather than through the protected circuit50.

The adjustable resistance of the control circuit670may be used to set different voltages at which the trigger circuit540triggers the shunt circuit510. A lower resistance provided by the control circuit670effectively results in a higher trigger voltage than for a higher control circuit resistance, or conversely, a higher resistance provided by the control circuit670effectively results in a lower trigger voltage for a lower control circuit resistance. That is, the p-well current required to forward bias the base-to-emitter of the NPN-BJT420is decreased with a higher resistance, thereby effectively decreasing the trigger voltage of the protection circuit500.

FIG. 7illustrates a control circuit700for a protection circuit according to some embodiments of the invention. As previously described, control circuits560and670may be used to set different voltages at which a trigger circuit triggers a shunt circuit. The control circuit700may be used for the control circuits560and670. The control circuit700includes a resistance710and a transistor720coupled in parallel to the resistance710. The transistor720is controlled by a control signal CNTRL. The resistance710is illustrated inFIG. 7as a resistor Rcontrol and the transistor720is illustrated as a nFET. In some embodiments of the invention, the resistance710and the transistor720may be implemented using other circuits.

In operation, the transistor720is used to adjust the overall resistance between a reference voltage to which a trigger circuit is coupled and a p-well region in which at least a portion of a shunt circuit and at least a portion of a trigger circuit are formed. The resistance between the p-well and the reference voltage may be adjusted based at least in part on the CNTRL signal. Generally, a lower resistance provided by the control circuit700effectively results in a higher trigger voltage than for a higher control circuit resistance. As a result, the resistance between the p-well and the reference voltage can be modulated to adjust the snapback performance characteristics of the protection circuit.

For example, in embodiments of the invention utilizing the protection circuit500(FIG. 5) and the control circuit700, the CNTRL signal can be used to in effect modulate trigger and hold conditions for the protection circuit500. Operation of the protection circuit and the control circuit700will be made with reference toFIG. 3.

Under a first condition with CNTRL=V1(e.g., V1<Vt of the transistor720) the transistor720behaves as an open circuit, thereby adding the Rcontrol resistance to the total resistance between the p-well and reference voltage of resistance710. As a result, the p-well current required to forward bias the base-to-emitter of the NPN-BJT420is decreased, thereby effectively decreasing the trigger voltage of the protection circuit500. In some embodiments, the resistance710is a relatively high resistance, for example, 50-100 kohms.

In contrast, under a second condition with CNTRL=V2(e.g., V2>Vt), the resistance of the control circuit700will be less than Rcontrol of the resistance710. With the lower resistance, the trigger voltage for the protection circuit500effectively increases. In a condition where the CNTRL signal is high enough to cause the transistor720to have a low resistance, for example, around 100 ohms, which results in essentially electrically shorting the p-well to ground, the protection circuit500will exhibit performance characteristics similar to having an un-modulated shunt circuit510.

FIG. 8illustrates a protection circuit800according to an embodiment of the invention. The protection circuit800includes similar components as the protection circuit500previously described with reference toFIG. 5. The same reference numbers used for the embodiment ofFIG. 5are used inFIG. 8where applicable. The protection circuit800further includes a diode820coupled between the cathode node30and the pad20in contrast to the protection circuit500. The cathode node30is illustrated inFIG. 8as being coupled to a reference voltage, for example, ground. The diode820may be a diode configured to provide ESD protection for ESD events that cause current to conduct from the cathode node30to the pad20. As a result, the protection circuit800provides current conduction during over-voltage conditions from the pad20to the cathode node30(i.e., current I1) as well as from the cathode node30to the pad20(i.e., current I2). With reference to the cross-sectional view ofFIG. 6, the diode820may be formed in n-well608by further forming a p-region in the n-well608to provide the anode of diode820. The p-region may be coupled to the cathode node30.

FIG. 9illustrates a protection circuit900according to an embodiment of the invention. The protection circuit900includes a first protection circuit910coupled to a pad20and a cathode node30, shown inFIG. 9as being coupled to a reference voltage node (e.g., ground). The protection circuit900further includes a second protection circuit920coupled to the pad20and a power supply node40which may be coupled to a power supply, for example, Vcc. Generally, the voltage coupled to the power supply node40is less than the voltage provided to the pad20. A protected circuit10is coupled to the pad20and the cathode node30. The first protection circuit910is configured to conduct current from the pad20to the cathode as well as conduct current from cathode node30to the pad20. The first protection circuit910may be implemented using the protection circuit800ofFIG. 8, which includes a diode configured to provide ESD protection for ESD events that cause current to conduct from the cathode node30to the pad20. The second protection circuit920is configured to conduct current from the pad20to the power supply node40. The second protection circuit920may be implemented using the protection circuit500ofFIG. 5. The protection circuit900may be used to provide ESD protection for both power and ground sides.

FIG. 10illustrates a portion of a memory1000according to an embodiment of the present invention. The memory1000includes an array1002of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other types of memory cells. The memory1000includes a command decoder1006that receives memory commands through a command bus1008and generates corresponding control signals within the memory1000to carry out various memory operations. Row and column address signals are applied to the memory1000through an address bus1020and provided to an address latch1010. The address latch then outputs a separate column address and a separate row address.

The row and column addresses are provided by the address latch1010to a row address decoder1022and a column address decoder1028, respectively. The column address decoder1028selects bit lines extending through the array1002corresponding to respective column addresses. The row address decoder1022is connected to word line driver1024that activates respective rows of memory cells in the array1002corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry1030to provide read data to a data output buffer1034via an input-output data bus1040. The output buffer1034may include output driver circuits (not shown) coupled to pad1020to be provided a relatively high voltage when providing output data. Write data are applied to the memory array1002through a data input buffer1044and the memory array read/write circuitry1030. The command decoder1006responds to memory commands applied to the command bus1008to perform various operations on the memory array1002. In particular, the command decoder1006is used to generate internal control signals to read data from and write data to the memory array1002.

Over-voltage/over-current protection circuit1050according to an embodiment of the present invention is coupled to the pad1020. The protection circuit1050protects circuits of the output buffer1034that are coupled to the pad1020(e.g., driver circuits) in the event a relatively high-voltage/high-current signal is applied to the pad1020. Additionally, as previously discussed, the protection circuit1050allows for modulating the trigger conditions and the hold conditions for the protection circuit. In some embodiments, the protection circuit may be used in power-up sequences for the memory1000, as previously discussed. That is, while no power is applied to the memory1000, the trigger conditions for the protection circuit1050is relatively low. In contrast, after power has been applied to the memory1000, the trigger conditions for the protection circuit1050is modulated to a higher trigger condition relative to when no power is applied.