Semiconductor device having a reduced surface doping in an edge termination area, and method for manufacturing thereof

A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

TECHNICAL FIELD

Embodiments described herein relate to semiconductor devices having a surface doping region with a reduced net doping concentration relative to a net doping concentration of an upper drift region of a drift region. Further embodiments pertain to methods for manufacturing semiconductor devices.

BACKGROUND

Semiconductor devices such as MOSFET using field electrodes for charge compensation have become very popular during the last decade as they offer a significant improvement of the area-specific resistance. The devices typically use a stripe design where the field electrodes and the mesa regions containing the gate electrodes are formed in the shape of long stripes which run parallel to each other.

More recent concepts employ a cell design having a hole-like deep trench, also referred to as spicular trench, containing the so-called field-plate in the centre of a given transistor cell. The deep trench containing the field-plate is surrounded by a separate gate trench. This cell design, also referred to as needle trench design due to the central deep field-plate shaped as oblong electrode, offers a larger cross-sectional area for the mesa region around the spicular trench than the stripe design. A larger cross-sectional area for the mesa is believed to further reduce the overall on-state resistance RONof the semiconductor device.

For illustrating purposes, reference is made toFIGS. 11A and 11Bwhich show schematics of unit cells of the stripe design inFIG. 11Aand of the needle trench design inFIG. 11B. Assume that the unit cell has dimensions defined by a in length and width direction. We further assume that the width of the trench is a−w with w being the width of the mesa region. A trench for the field plate in the stripe design assumes an area equal to a·(a−w). Different thereto, the spicular trench only assumes an area of (a−w)2which means that the area left for the mesa region is larger in the needle trench design than in the stripe design. A larger cross-sectional area of the mesa results in a lower on-state resistance RON.

As with semiconductor devices of the stripe design, semiconductor devices having transistor cells of the needle trench design include a so-called edge termination region which surrounds an active region of the semiconductor device. The active region of a semiconductor device includes the active transistor cells which carry the electric current through the semiconductor device and which can be controlled by applying a gate voltage. The edge termination region is provided to maintain and improve the blocking capabilities of the semiconductor device when operated in blocking mode or off-state.

A breakdown of the semiconductor device may particularly happen at the outer rim of the semiconductor substrate of the semiconductor device due to crystal defects and a locally increased electrical field. The edge termination region is provided to control the relief of the electric field so that the occurrence of high electric fields at the outer rim or other regions susceptible to electrical breakdown can be avoided.

In view of the above, there is need for further improvement.

SUMMARY

According to an embodiment, a semiconductor device includes a semiconductor substrate having a first side, a second side opposite to the first side, a lateral rim, an active area, an edge termination area arranged between the active area and the lateral rim of the semiconductor substrate, a drift region of a first conductivity type and a body region of a second conductivity type, wherein the drift region includes an upper drift region and a lower drift region. The active area includes at least portions of the body region and a plurality of spicular trenches each having a field electrode and extending from the first side through the body region and into the drift region. Each of the spicular trenches in the active area has a lower end which lower ends together define a lower end of the upper drift region extending towards the first side. The lower drift region extends from the lower end of the upper drift region towards the second side. The edge termination area includes a plurality of spicular termination trenches extending from the first side at least into the upper drift region. The drift region has a surface doping region arranged in the upper drift region in the edge termination area and extending to the first side, wherein the surface doping region is spaced apart from the lower end of the upper drift region and has a net doping concentration lower than a net doping concentration of the upper drift region.

According to an embodiment, a method for manufacturing a semiconductor device includes: providing a semiconductor base substrate; forming an epitaxial layer on the semiconductor base substrate, the epitaxial layer and the semiconductor base substrate forming together a semiconductor substrate; forming a drift region comprising a surface doping region of a first conductivity type and an upper drift region of the first conductivity type in the epitaxial layer, the surface doping region having a net doping concentration lower than a net doping concentration of the upper drift region; forming a body region of a second conductivity type in an active area; forming, in an active area, a plurality of spicular trenches extending from the first side through the body region and into the drift region; and forming, in an edge termination area, a plurality of termination trenches extending from the first side into the upper drift region.

Those skilled in the art will recognise additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

DETAILED DESCRIPTION

As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

In this specification, a second surface of a semiconductor substrate is considered to be formed by the lower or back-side surface while a first surface is considered to be formed by the upper, front or main surface of the semiconductor substrate. The terms “above” and “below” as used in this specification therefore describe a relative location of a structural feature to another structural feature with consideration of this orientation.

The terms “electrical connection” and “electrically connected” describe an ohmic connection between two elements.

The semiconductor device is at least a two-terminal device, an example is a diode. The semiconductor device can also be a three-terminal device such as a field-effect transistor (FET), insulated gate bipolar transistor (IGBT), junction field effect transistors (JFET), and thyristors to name few. The semiconductor device can also include more than three terminals.

Specific embodiments described herein pertain to, without being limited thereto, power semiconductor devices and particularly to devices which are controlled by a field-effect.

In the Figures, like reference signs designate corresponding parts.

A “plane projection” or a “plan view” intends to describe a virtual projection of structures, elements or regions on a reference plane for describing the arrangement of the structures, elements and regions relative to each other.

FIG. 1illustrates a plan view onto a semiconductor device according to an embodiment. The semiconductor device includes a semiconductor substrate100having an outer rim103, an active area104, and an edge termination area110arranged between the active area104and the outer rim103. The outer rim103defines the outer boundary of the semiconductor substrate100and limits the semiconductor substrate100by a circumferentially running vertical surface extending perpendicular to the main surfaces of the semiconductor substrate100.

The active area104may include a transistor array having a plurality of transistor cells107,108which can be arranged in a given pattern in the active area104. The active area104may include active transistor cells107, arranged in a central part of the active area104, and inactive transistor cells108arranged in a region surrounding the region of the active transistor cells107. The inactive transistor cells108may form a transition area106between an active cell area105defined by the active transistor cells107and the edge termination area110.

Each of the transistor cells107,108can include a spicular trench130which is described further below. Spicular trenches130can also be formed in the edge termination area110to improve the blocking capabilities of the semiconductor device. The edge termination area110can include a termination structure formed by spicular trenches and/or other structures such as doping regions which are provided to controllably relax the electrical field under blocking conditions.

With reference toFIGS. 2A and 2Bthe differences between a transistor cell of the stripe design and a transistor cell of the trench needle design is explained in more detail.FIG. 2Ashows a unit cell of the stripe design whileFIG. 2Billustrates a unit cell of the trench needle design.

The transistor cell ofFIG. 2Ais formed in a semiconductor substrate200having a first side201and the second side. The first side201defines the main side or surface of the semiconductor substrate200while the second side defines a side opposite to the first side201. The stripe design includes a long and deep field plate trench230which is formed to extend from the first side201of the semiconductor substrate into the semiconductor substrate100. The field plate trench230has a stripe shape when seen in plain projection onto the first side201of the semiconductor substrate200. Each field plate trench230includes a field electrode231which is indicated by phantom lines inFIG. 2A. The field electrode231has a plate-like shape parallel to the longitudinal extension of the field plate trench230. A thick field oxide232electrically insulates the field electrode231from the semiconductor substrate200. Next to and parallel with the field plate trench230is running a cell mesa region220extending up to the first side201of the semiconductor substrate200.

The design as shown inFIG. 2Acontinues in the direction indicated by arrow A and is mirrored at the planes A1and A2. The plane A1runs parallel to and along a centreline of the field plate trench230. The plane A2runs parallel to and along a centreline of a gate trench240formed in the cell mesa region220.

The gate trench240and the field plate trench230run parallel to each other. The stripe design thus includes stripe-shaped field plate trenches230with strip-shaped field electrodes, stripe-shaped cell mesa regions230arranged between and extending along adjacent field plate trenches230, and stripe-shaped gate trenches240formed in the cell mesa region220and running parallel to field plate trenches230.

In an embodiment, contact structures245may be provided. For example, the contact structures may be contact grooves extending over at least a part of the active area. The contact grooves may be formed, when seen in plan projection onto the first side201, over the full spicular trench area and overlapping some distance into the silicon around the spicular trench.

For example, contact grooves or contact trenches245are formed in the cell mesa region220between the gate trenches240and the field plate trenches230. The contact trenches245extend from the first side201through source regions251and into body regions252as shown inFIG. 2A. The contact trenches245are less deep than the gate trenches240which extend from the first side201through the source region251and the body region252and into the drift region253arranged below the body region252and between adjacent field plate trenches230.

As shown inFIG. 2A, the field plate trench230extends much deeper into the semiconductor substrate200than the gate trench240. Adjacent field plate trenches230thus define and border a cell mesa region220which includes at the first side201of the semiconductor substrate200the source region251, the body region252and a large part of the drift region253. The field electrodes231are typically electrically connected to the source regions251and are therefore at source potential. When the semiconductor device is operated in blocking mode, the field electrodes231being on source potential contribute to the depletion of the drift region253between adjacent field trenches230. This improves the blocking capabilities of the device and allows to provide the drift region with a higher doping concentration to reduce the on-state resistance RON.

FIG. 2Ashows furthermore a drain region257at the lower side ofFIG. 2Awhich extends to the second side of the semiconductor substrate200. An optional field stop region256can be formed between the drain region275and the drift region253.

Different to the stripe design illustrated inFIG. 2A, the trench needle design illustrated inFIG. 2Bincludes a deep trench having a cross-section, when seen in plan projection onto the semiconductor substrate, which has substantially the same width and length. The cross-section can be, for example, square-like, hexagonal, substantially circular, or octagonal. The deep trench includes a central long field electrode surrounded by a field oxide to insulate the field electrode from the surrounding semiconductor substrate. Due to the shape of the (deep) spicular trenches and the field electrode arranged therein being similar to a long needle extending from the first side into the semiconductor substrate, the design may also be referred to as needle trench design.

Instead of having a long stripe-shaped field plate trench, the needle trench design uses a plurality of spicular trenches which can be arranged in lines, when seen in plan projection onto the first side. A single long field trench is thus replaced by a plurality of spicular trenches. Since semiconductor material, i.e. mesa regions, remain between adjacent spicular trenches in long and with direction, both of which are parallel to the main surface of the semiconductor substrate, the total “mesa” area is larger in the needle trench design than in the stripe design leading to a reduction of the on-state resistance RON.

FIG. 2Billustrates a quadrant or quarter of a complete transistor cell according to an embodiment when seen in plan projection onto the first side101of the semiconductor substrate100. Similar toFIG. 2A, the semiconductor substrate100includes a first side101and a second side102arranged opposite the first side101.

According to an embodiment, the semiconductor substrate100can comprise any semiconductor material suitable for manufacturing semiconductor devices. An example for a suitable semiconductor material is silicon.

A spicular trench130vertically extends from the first side101through a source region151and a body region152deeply into the drift region153. The spicular trench130may stop short before an optional field stop region156formed between the drift region153and a drain region157. A lower end of the spicular trench130may also vertically be spaced from the field stop region156or may also partially extend into the field stop region156.

The spicular trench130includes a field electrode, which is referred to as needle electrode131and which is in the embodiment shown inFIG. 2Ba long and vertically extending conductive structure. The needle electrode131is electrically insulated from the surrounding semiconductor substrate100by a comparably thick field oxide132. The needle electrodes131are typically at source potential to improve depletion of the upper or main part of the drift region153. Again, this allows raising the doping concentration of the drift region153which is beneficial for the on-state resistance RON.

The source region151, the drift region153, the optional field stop region156, and the drain region157are of a first conductivity type which is typically n-type. Different thereto, the body region252is of a second conductivity type which is typically p-type. The semiconductor devices as described herein are, however, not limited thereto, and the first conductivity type can also be p-type while the second conductivity type can be n-type.

When the drain region157is of the first conductivity type, the semiconductor device is a MOSFET having a compensation structure formed by the spicular trenches. When the “drain” region is of the second conductivity type, the semiconductor device is an IGBT. In this case, the region157is referred to as emitter region.

According to an embodiment, the source region151and the drain region157are highly n-doped regions while the drift region153is a weakly n-doped region. The field stop region156has a doping concentration between the doping concentration of the drift region153and the doping concentration of the drain region157. The dashed lines inFIG. 2Billustrate the increasing doping concentration in the field stop region156from the drift region153to the drain region157.

Different to the stripe design, the cell mesa region120of a field trench transistor completely surrounds the spicular trench130when seen in plan projection onto the first side101. A full transistor cell is obtained when the illustration inFIG. 2Bis rotated around a vertical axis A3in steps of 90° asFIG. 2Billustrates only a quadrant or quarter.

A contact structure145may be provided as described above, for example as a contact groove or a contact trench without being limited thereto.

The trench needle design thus allows to enlarge the cross-sectional area, when seen in plan projection onto the first side101, of the cell mesa region120per unit cell. In addition to that, the length of the gate trench140in each of the unit cells can also be increased in comparison to the stripe design so that the effective length of the channel region can be increased.

When referring back toFIGS. 11A and 11B, the gate trench in the stripe design would run along the longitudinal extension of the cell mesa region, i.e. in the vertical direction ofFIG. 11A, and would therefore have a length a per unit cell. Different thereto, the gate trench surrounds the spicular trench130in the needle trench design, which is illustrated inFIG. 11Bin the left lower corner. Depending on the specific location of the gate trench in the cell mesa region, the gate trench can have a length of up to 2·a. Therefore, the channel length per unit cell area can be much larger in the needle trench design relative to the stripe design. This further reduces the on-state resistance RON.

FIG. 3illustrates a vertical cross-section through a portion of the semiconductor device according to an embodiment. The vertical cross-section shown inFIG. 3contains portion of the active cell area105, of the transition area106and of the edge termination area110. As illustrated inFIG. 3, spicular trenches130can be formed in any of the active cell area105, the transition area106, and the edge termination area110. For example, the spicular trenches130can be formed at a given pattern throughout the semiconductor substrate100. Typically, the spicular trenches130are arranged with the same pattern in the active cell area105, the transition area106and the edge termination area110. It would, however, also be possible to arrange the spicular trenches130with different patterns in, for example, the active area104and the edge termination area110.

As further shown inFIG. 3, each of the spicular trenches130includes a needle-shaped field electrode131, referred to as needle electrode, which is electrically insulated from the surrounding semiconductor substrate100by a thick field oxide132. The spicular trenches130extent from the first side101deeply into the semiconductor substrate100without reaching the drain region157formed at the second side102of the semiconductor substrate100. As described further above, the drain region is a highly-doped region which is illustrated here by “n+”. The drift region153is a weakly n-doped region which is illustrated here by “n−”. The doping concentration of the drift region153is typically defined by the background doping of the semiconductor substrate100which can either be a bulk semiconductor substrate100formed by cutting off a slice from an ingot, or an epitaxial layer formed on a base semiconductor substrate100. Typically, the semiconductor substrate100includes an epitaxial layer as this would allow to tailor the doping concentration of the epitaxial layer during growth. The base semiconductor substrate100can later form the drain region157, or can be removed.

An active transistor cell107additionally includes a body region152which forms a first pn-junction with the drift region153. The source region151is formed at the first side101of the semiconductor substrate100and forms a second pn-junction with the body region152. The first pn-junction between the body region152and the drift region153is the main pn-junction while the second pn-junction between the body region152and the source region151is typically short-circuited by a body contact. The source region151is a highly n-doped region indicated inFIG. 3by “n+”. The body region152is a p-doped region as indicated inFIG. 3by “p”.

As shown inFIG. 3, the spicular trenches130extend much deeper into the semiconductor substrate100than the body region152. Therefore, the cell mesa region120between adjacent spicular trenches130is a narrow region which can be easily depleted by supplying a source potential to the needle electrodes131.

The spicular trenches130in the active area104have a lower end pointing to the second side102of the semiconductor substrate100. The lower end of the spicular trenches130define a level within the semiconductor substrate100which is substantially parallel to the first side101and the second side102. The drift region153can be considered to include an upper drift region153aand a lower drift region153b. The upper drift region153aextends from the level defined by the lower ends of the trenches130in the active area104toward the first side101. The lower drift region153bextends from the level defined by the lower ends of the spicular trenches130in the active area104toward the second side102. The upper drift region153amay also referred to as cell mesa region120when arranged between adjacent spicular trenches130.

According to an embodiment, the upper drift region153aand the lower drift region153bmay have the same doping concentration. According to an embodiment, the upper drift region153aand the lower drift region153bmay have different doping concentrations.

A gate trench140is arranged in the cell mesa region120formed by the upper drift region153abetween adjacent spicular trenches130. The gate trench140extends from the first side101through the source region151and the body region152into the drift region153. As seen in the cross-sectional view ofFIG. 3, the spicular trenches130are much deeper than the respective gate trenches140, which merely extend slightly deeper into the semiconductor substrate100than a lower end of the body region152. The lower end of the gate trenches140are therefore slightly below the first pn-junction between the drift region153and the body region152. The gate trench140may form, when seen in plan projection onto the first side101, a net or a grid of crossing gate trenches. When seen in a vertical cross-sectional view as inFIG. 3, the gate trenches140may appear to be separated although they are connected with each other at gate crossing regions.

Each gate trench140includes a gate electrode141which is electrically insulated from the surrounding semiconductor substrate100by a gate dielectric142. The gate dielectric142is typically much thinner than the field oxide131of the spicular trench130, because the gate dielectric142needs to tolerate only moderate voltages such as 5 V to 15 V. Different thereto, the field oxide131needs to withstand much higher voltages, such as 50 V to 250 V or above, particularly in the region at the bottom of the spicular trenches130.

The needle electrodes132, the source regions151and the body regions152are electrically connected to a source metallization which is schematically shown inFIG. 3as being connected with a terminal L1. Thus, the same voltage, or electrical potential, is applied to the source regions151, the body regions152and the needle electrodes132. The gate electrodes141are electrically connected to a gate terminal G.

FIG. 3illustrates that only the field electrodes131in the active area104are electrically connected to the source metallization. The field electrodes131in the edge termination area110are illustrated as electrically disconnected from the source metallization. Each of the field electrodes131in the edge termination area110can be, for example, electrically connected to a floating p-region formed in the edge termination area110at the first side101of the semiconductor substrate100. Another option is to electrically connect the field electrodes131in the edge termination area110to the source metallization so that all field electrodes131in the active area104and in the edge termination area110are at source potential. It would also be possible to electrically connect only a portion of the field electrodes131in the edge termination area110with a source metallization while other field electrodes131in the edge termination area110are electrically insulated from the source metallization.

FIG. 3also illustrates a structural difference between an active transistor cells and an inactive transistor cell. An active transistor cell is capable of forming and controlling a conductive channel region extending from the source region151through the body region152to the drift region153along the gate dielectric142of the gate trenches140. The conductive channel region is formed under the influence of the electrical field generated by applying a gate voltage above a given threshold to the gate electrodes141. The dotted vertical line in the body regions152next to the gate trenches140illustrates the conductive channel region.

If any of source region151, body region or gate electrode141is missing, the transistor cell is not capable of providing a controllable conductive channel region between the source region151and the drain region157through the body region152.

Therefore, an inactive transistor cell may have substantially the same structure as an active transistor cell but does not include, for example, a source region or a gate electrode. In addition to that, an active transistor cell which otherwise includes all required structural elements such as source region, body region, drift region and gate electrode can be rendered inactive or inoperable when either the source region or the gate electrode is electrically disconnected from the source metallization and the gate terminal, respectively.

The transition region106shown inFIG. 3may include inactive transistor cells108which do not include a source region and the gate electrode. The inactive transistor cells108do not contribute to the current through the semiconductor device. The main function of the inactive transistor cells108is to maintain a desired distribution of the electrical field within the semiconductor substrate100when the device is operated in blocking mode and to provide an “electrical transition” between the active area104and the edge termination area110.

According to an embodiment, a surface doping region155is formed in the edge termination area110at the first side101of the semiconductor substrate100. The surface doping region155is a weakly n-doped region having a lower doping concentration than the upper drift region153aof the drift region153. The upper drift region153aof the drift region153may have the background doping of the semiconductor substrate100. The surface doping region155having a lower doping concentration than the upper drift region153aof the drift region153can be described as a shallow doping region which is only formed close to the first side101of the semiconductor substrate100.

According to an embodiment, the surface doping region155can vertically extend less deep than the body regions152. According to a further embodiment, the surface doping region155can vertically extend deeper than the body regions152.

In view thereof, a semiconductor device includes a semiconductor substrate100having a first side101, a second side102opposite to the first side101, and a lateral rim103. A drift region153of a first conductivity type is formed in the semiconductor substrate100. The drift region153includes a surface doping region155with a net doping concentration lower than a net doping concentration of an upper drift region153aof the drift region153. An active area104includes a body region152of a second conductivity type and a plurality of spicular trenches130extending from the first side101through the body region152and into the drift region153. An edge termination area110is arranged between the active area104and the lateral rim103of the semiconductor substrate100and includes a plurality of termination trenches130extending from the first side101into the upper drift region153a. The body region152may extend deeper into the semiconductor substrate100than the surface doping region155of the drift region153. Alternatively, the surface doping region155may extend deeper into the semiconductor substrate100than the body region152.

A surface doping region155extending less deep than the body region152may be more effective since the weakness of the edge termination comes partly from the high electric field at the p-body junction end.

According to an embodiment, the surface doping region155is formed only in the edge termination area110and not in the active area104. This avoids that the reduced net doping concentration of the surface doping region155influences the characteristics of the transistor cells formed in the active area104.

According to an embodiment, the plurality of termination trenches comprises a plurality of spicular trenches130in the edge termination area110extending from the first side101into the upper drift region153aof the drift region153.

According to an embodiment, the net doping concentration, or average net doping concentration, of the surface doping region155is lower than 80% of the net doping concentration, or average net doping concentration, of the upper drift region153ain the cell mesa regions of the active area104, particularly lower than 50% such as lower than 20%. According to an exemplary embodiment, the net doping concentration of the upper drift region153ais at least 1·1016/cm3, particularly at least 1.5·1016/cm3, and more particularly at least 2·1016/cm3. Different thereto, the net doping concentration of the surface doping region155can be equal to or lower than 1·1016/cm3, according to an embodiment. In further embodiments, the net doping concentration of the surface doping region155is equal to or lower than 8·1015/cm3, particularly equal to or lower than 6·1015/cm3, and more particularly equal to or lower than 3·1015/cm3.

The weakly doped surface doping region155laterally relaxes the distribution of the electrical field in the edge termination area110and thus contributes to the blocking capabilities of the electronic device in the edge termination area110.

The effect of the weakly doped surface doping region155is described with reference toFIGS. 4A, 4B, 5A, and 5B. All of these Figures illustrate an edge termination area110of a semiconductor device of a needle trench design having a plurality of spicular trenches arranged in the edge termination area110. The rightmost spicular trench in the Figures represents the most outer active transistor cell. The lateral rim103of the semiconductor substrate100would be on the left side of the respective Figure.

For a semiconductor device having a stable and reliable breakdown characteristics the location of the avalanche generation during breakdown should be within the active area104of the semiconductor substrate100at the lower end of the spicular trenches130, i.e. at the trench bottom. The active area104is typically larger and therefore more stable and robust than the edge termination area110which includes the outer rim103. It is therefore desirable that an avalanche breakdown occurs in a region of the semiconductor device which can tolerate a breakdown. Such a robust region is, for example, at the lower end of the spicular trenches130. This region is also capable of tolerating repetitive avalanche breakdowns which may occur during operation of the semiconductor device. Many power semiconductor devices need to tolerate such avalanche breakdowns which can frequently occur during operation.

Due to further optimization of the semiconductor devices towards lower on-state resistance RONthe net doping concentration of the drift region153of modern devices is increased. Simulations revealed that the breakdown location in case of a higher doping concentration of the drift region153may move to the end of the last spicular trench in the edge termination area as shown inFIG. 4A.FIG. 4Aillustrates the distribution of the electrical field strength under blocking conditions, i.e. when no conductive channel is formed and a high voltage difference appears between source region and drain region. The large voltage drop between source region and drain region must be accommodated by the drift region. The electrical field strength occurring in the drift region can be large.

The simulation of the distribution of the electrical field strength inFIG. 4Ashows that high field strength appears along the last spicular trench which is the leftmost spicular trench inFIGS. 4A and 4B.FIG. 4Billustrates the distribution of the electrostatic potential under blocking condition. The distribution of the electrostatic potential inFIG. 4Bindicates that the potential changes vary rapidly at the outer region of the last spicular trench, resulting in high electric field strength. To improve the blocking capability of the edge termination area, it is desired to relax the electrostatic potential distribution at the end of the termination structure.

According to an embodiment, when providing the drift region153with a shallow weakly doped surface doping region155, the distribution of the electrostatic potential can be laterally spread and strong electrical fields prevented at the outer spicular trench in the edge termination area110.

According to an embodiment, the net doping concentration of the surface doping region155, as of other doping regions, may vary to a given degree. However, the average net doping concentration of the surface doping region155is lower than the average net doping concentration of the upper drift region153a.

For example, the drift region153, when formed by epitaxial deposition, can be provided with a graded surface doping region155towards the first side101by reducing the net doping concentration during epitaxial growth. When referring to the net doping concentration, the absolute value of the difference between the n-doping concentration and p-doping concentration is meant as the net doping concentration basically defines the conductivity type and conductivity of the respective doping region.

The surface doping region155having a reduced net doping concentration is typically formed only at the first side101and does not extend deep into the semiconductor substrate100. According to an embodiment, an nn-junction or interface between the upper drift region153aand the surface doping region155is vertically above the first pn-junction between the body region152and the drift region153. The upper drift region153aof the drift region153therefore vertically extends above the first pn-junction, so that the first pn-junction can be described to be formed between the upper drift region153aand the body region153.

The surface doping region155may be less deep than the body region152. The reduction of the net doping concentration therefore does not appear in the cell mesa region120between the spicular trenches130in the active area104. The reduction of the surface doping in the drift region153thus does not affect the doping relations within the upper drift region153a, or the cell mesa regions120, in the active area104.

According to a practical embodiment, the surface doping region155of the drift region153extends, from the first side101, to a depth of equal to or less than 1 μm, for example less than 500 nm. The body regions152may extend to a different depth into the semiconductor substrate100, for example, may extend deeper than the surface doping region.

According to an embodiment, the surface doping region155is formed by implanting counter dopants into the upper drift region153a. The drift region153may be formed by epitaxial deposition to form the upper drift region153awith a substantially homogeneous doping concentration. In a later process, counter dopants may be implanted globally, or in selected areas using an implantation mask, to reduce the net-doping concentration at the first side101and to form the surface doping region155having a lower net-doping concentration than the upper drift region153a.

Both the upper drift region153aand the surface doping region155may be of the first conductivity type and have the same doping concentration of dopants of the first conductivity type. The surface doping region155may have also dopants of the second conductivity type which effectively reduces the net doping concentration of the surface doping region155. Since the doping concentration of the dopants of the first conductivity type is higher than the doping concentration of the dopants of the second conductivity type in the surface doping region155, the “net” conductivity type of the surface doping region155remains of the first conductivity type.

According to an embodiment, the upper drift region153ain the cell mesa regions120of the active area104does not contain a counter doping while the surface doping region155formed in the edge termination area110includes a counter doping to reduce the net doping concentration relative to the net doping concentration of the upper drift region153ain the cell mesa regions120of the active area104.

For evaluating the effect of the surface doping region155, reference is made toFIGS. 5A and 5B.FIG. 5Billustrates the distribution of the electrostatic potential of a semiconductor device having a surface doping region155with a reduced net doping concentration relative to the net doping concentration of the upper drift region153aof the drift region153. As shown inFIG. 5B, the electrostatic potential is significantly spread toward the outer rim (left side ofFIG. 5B) which means that the electric field close to the outer spicular trench, i.e. the leftmost spicular trench, is reduced. This is confirmed byFIG. 5Awhich shows the location of avalanche generation, which may be expressed by the impact ionisation in cm−3·s−1. The risk for an avalanche breakdown is significantly reduced in the region of the last spicular trench and maybe even lower than close to the active area104which begins at the rightmost spicular trench inFIG. 5B.

FIG. 6illustrates the results of a further simulation to evaluate the influence on the net-doping concentration of the upper drift region153a. The net-doping concentration is referred to as Nepi inFIG. 6. Curve301represents the dependency of the breakdown voltage BV in the active area104from the net doping concentration. Curve302represents the dependency of BV in the edge termination area110when no surface doping region is formed. Curve303represents the dependency of BV in the edge termination area110when a surface doping region is formed.FIG. 6reveals that the breakdown voltage BV remains substantially high in the active area104even at a high doping concentration of the upper drift region153a. Different thereto, an increase of the doping concentration at the first side101, i.e. when no surface doping region with reduced net-doping concentration is formed, leads to a significant reduction of the breakdown voltage in the edge termination area110. This is illustrated by curve302. When reducing the doping concentration at the first side101by providing a surface doping region of reduced doping concentration, the drop of BV can be significantly reduced as illustrated by curve303.

FIG. 7illustrates the edge termination area110according to an embodiment. The edge termination area110includes a plurality of spicular trenches130each having a needle electrode131electrically insulated from the semiconductor substrate100by a comparably thick field oxide132. The field oxide132can be a thermally grown silicon oxide. Further options include a layer stack of several insulating layers such as nitride layers and oxide layers. According to an embodiment, the field electrode trenches130in the edge termination area110have the same structure as the field electrode trenches130in the active area104. All field electrode trenches130including the field oxide132and the needle electrodes131are commonly formed.

FIG. 7illustrates a small portion of the active area104in the left part of the Figure. The leftmost spicular trench130, which is a spicular trench130formed in the active area104, is shown to be completely surrounded by a gate trench140. For sake of simplicity, a contact trench is not illustrated inFIG. 7. The body region152is illustrated inFIG. 7to extend only within the active area104. Body and source regions are not formed in the edge termination area110. However, a body region152can also be at least partially formed in the edge termination area110between selected spicular trenches130.

FIG. 7further illustrates the drift region153which includes an upper drift region153aand a surface doping region155which is formed at the first side101of the semiconductor substrate100. The surface doping region155laterally completely extend from the outer end of the active area104to the lateral rim103of the semiconductor substrate100. According to an embodiment, the surface doping region155is only formed in an outer part of the edge termination area110extending to the lateral rim103while the upper drift region153ais formed to extend to the first side101in an inner part of the edge termination area110next to the active area104.

In addition to improving the avalanche breakdown robustness of the edge termination area, the surface doping region155with reduced net doping concentration also helps to reduce the electric field at the lateral end of the body region, where the electric field can also be critical.

A further improvement for the electrical field relaxation in the edge termination area110is to place a so-called source runner and/or a so-called gate runner above the critical region at the end of the edge termination area. Each of these runners are at comparably low voltage or at 0 V during blocking mode. These electrical structures push the electrical field lines further away from the most outer trench leading to a further reduction of the electrical field strength. Embodiments with gate runners and source runners are illustrated inFIGS. 8A and 8B.

FIG. 8Aillustrates a vertical cross-section through the semiconductor substrate100showing a plurality of spicular trenches130each having a needle electrode131and a field oxide132. The needle electrode133is electrically connected to a source contact line195by respective needle contact133.

FIG. 8Billustrates a plan view onto the first side101of the semiconductor substrate100. A large source metallization195is formed in the active area104and basically completely covers the active area104when seen in plan projection onto the first side101. For illustration purposes only, the source metallization195is partially removed to show the spicular trenches130and the gate electrodes141in the active area104. The source contact lines196laterally extend from the source metallization195to provide an ohmic connection for all, or selected, needle electrodes in the edge termination area110.

Along an outer region of the semiconductor substrate100between the most outer spicular trenches130and the lateral rim103, a gate runner190is formed. Gate contact lines191, which may also be referred to as gate fingers, laterally extend from the gate runner190to be in ohmic connection with the gate electrodes141at gate contacts192.

The gate runner190, the gate contact lines191, the source metallization195, and the source contact lines196are all structures formed in the same level above the first side101of the semiconductor substrate100. Typically, these structures are formed by structuring a metal layer which is deposited onto an insulation layer. The insulation layer is then arranged between the first side101of the semiconductor substrate100and the source metallization195, the source contact lines196, the gate runner190, and the gate contact lines191. The needle contacts133, best shown inFIG. 8A, and the gate contacts192vertically extend through the insulation layer.

The gate runner190, being at a comparably low electrostatic potential in blocking mode, further supports the lateral spreading of the electrical field which further improves the breakdown characteristics of the semiconductor device. AlthoughFIG. 8Billustrates only a gate runner190along the edge termination are110, other embodiments may include a gate runner and a source runner, or only a source runner. Since a source runner is also at low electrostatic potential in breakdown mode, providing a source runner in the edge termination area110is also beneficial.

According to an embodiment, the gate runner and/or the source runner are provided to at least partially cover a region between the most outer trench and the lateral rim103.

FIGS. 9A and 9Bgive some examples for suitable patterns to arrange the spicular trenches130and for the cross-sectional shape of the transistor cells when seen in plan projection onto the first side101.FIG. 9Billustrates in the lower portion an example for a spicular trench having a square like cross-sectional area. The upper portion ofFIG. 9Billustrates a spicular trench having a hexagonal cross-sectional area. When using spicular trenches having a hexagonal cross-sectional area, a staggered pattern, e.g. a non-orthogonal regular pattern, of the transistor cells can be formed as illustrated inFIG. 9A. Different thereto, when using spicular trenches having a square like cross-sectional area, the transistor cells can be arranged on a regular pattern as illustrated inFIG. 9C. An arrangement in a regular pattern, i.e. in columns and stripes, is also possible with spicular trenches having a hexagonal cross-sectional area while spicular trenches with a square-like cross-sectional shape can also be arranged in a staggered pattern.

Depending on the actual design of the spicular trenches, when seen in plan projection onto the first side101, the gate trenches140, or gate electrodes141, may form gate crossings143having a different layout.FIG. 9Aillustrates a hexagonal shape of the spicular trenches. The region, were to crossing gate trenches140meet, is a gate crossing143. In the embodiment ofFIG. 9A, the respective gate crossing143is between three adjacent spicular trenches and has a triangular shape. InFIG. 9Chaving a square-like cross-sectional shape of the spicular trenches, the respective gate crossing143is between four adjacent spicular trenches and has a square-like shape.

With reference toFIG. 10, a method for manufacturing a semiconductor device according to an embodiment is explained. The method may include providing a semiconductor base substrate and forming an epitaxial layer on the semiconductor base substrate, wherein the epitaxial layer and the semiconductor base substrate form together a semiconductor substrate. A drift region153is formed comprising a surface doping region155of a first conductivity type and an upper drift region153aof the first conductivity type in the epitaxial layer. The surface doping region155has a net doping concentration lower than a net doping concentration of the upper drift region153a. A body region152of a second conductivity type may be formed in an active area104. Furthermore, a plurality of spicular trenches130extending from the first side101through the body region152and into the drift region153are formed in the active area104. A plurality of termination trenches130extending from the first side101into the upper drift region153aare formed in the edge termination area110.

According to an embodiment, the body region152is formed to extend deeper into the semiconductor substrate100than the surface doping region155. According to an alternative embodiment, the surface doping region155is formed to extend deeper into the semiconductor substrate100than the body region152.

The semiconductor base substrate can be a bulk material obtained by cutting a slice from an ingot. The epitaxial layer may later include all doping regions such as the drain region151, the body region152, the drift region153, the field stop region156and the drain region157. The semiconductor base substrate can be finally removed or used as drain region157.

The doping concentration of the upper rift region153aand of the surface doping region155of the drift region153can be adjusted during epitaxial growth. Alternatively, the drift region153is formed with a homogeneous doping concentration and the surface doping region153is subsequently formed by a counter implantation.

The net doping concentration of the upper drift region153acan be at least 1·1015/cm3, typically at least 1·1016/cm3according to some embodiments.

According to an embodiment, the surface doping region155is formed such to have a net doping concentration of 80% or less than the net doping concentration of the upper drift region153in the cell mesa region120of the active area104.

The net doping concentration of the surface doping region155can be equal to or lower than 1·1016/cm3, typically equal to or lower than 8·1015/cm3, particularly equal to or lower than 6·1015/cm3, for example depending on the net doping concentration of the upper drift region as already exemplarily explained above.

According to an embodiment, source regions151of the first conductivity type are formed in the active area104.

According to an embodiment, gate trenches140are formed in the active area104adjacent to respective spicular trenches130, wherein the gate trenches140extend from the first side101through the body region152. Each of the gate trenches140has a gate electrode141electrically insulated from the adjacent body region152, wherein the spicular trenches130extends deeper into the semiconductor substrate100than the gate trenches140.

According to an embodiment, the drift region may be formed by supplying a doping gas during formation of the epitaxial layer, and reducing the supply of the doping gas to form the surface doping region155when the epitaxial layer has reached a predetermined thickness. The grading of the doping concentration can thus be provided during epitaxial growth. This is a cost-efficient approach for reducing the doping concentration at the first side101of the semiconductor substrate100to form the surface doping region.

According to a further embodiment, the drift region is formed by supplying a doping gas during formation of the epitaxial layer, and stopping the supply of the doping gas to form the surface doping region155when the epitaxial layer has reached a predetermined thickness. The upper region of the epitaxial layer is thus initially undoped. Due to thermal processes, dopants diffuse from lower parts of the epitaxial layer to the upper region arranged at the first side101. The resulting doping profile, in vertical direction, shows a reduction towards the first side101.

According to a further embodiment, the drift region is formed by supplying a doping gas during formation of the epitaxial layer at a substantially constant supply rate, and after forming the epitaxial layer, by implanting counter dopants into the epitaxial layer to reduce the net doping concentration at a surface of the epitaxial layer to form the surface doping region155. This approach allows the local formation of the surface doping region without affecting other regions. Furthermore, using of counter dopants provides a better control of the doping concentration to better tailor the net-doping concentration in the surface doping region155.

For implanting counter dopants, the active area104may be covered with a mask to avoid that the counter dopants are implanted into the active area104. The mask thus leaves only the edge termination area110, or only an outer part of the edge termination area110uncovered.

According to an embodiment, a mask may be formed on the surface of the epitaxial layer to cover the active area and to expose the edge termination area. The mask is used as implantation mask during implantation to avoid that the counter dopants are implanted into the active area.