SiP substrate

Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.

FIELD OF THE INVENTION

This invention relates, in one embodiment, to a system in package (SiP) substrate. The package includes an interconnect substrate disposed between a conductive trace frame and an integrated circuit. The interconnect substrate permits the integrated circuit to make electrical contacts with the fine pitch spacing found in the substrate.

BACKGROUND OF THE INVENTION

Current design trends in the computer industry include increased miniaturization of computer components and, as a result, more efficient utilization of circuit board “real estate.” One approach to efficiently utilizing space includes the use of system-in-a-package (SiP) substrates, wherein a plurality of integrated circuits are encased within a single package. With the proper configuration, this can reduce the footprint of the package. See U.S. Pat. No. 7,061,077 to Joshi (Substrate Based Unmolded Package Including Lead Frame Structure and Semiconductor Die) and U.S. Pat. No. 7,309,913 to Shim et al. (Stacked Semiconductor Packages).

When a package contains a large number of devices, the device must connect to a large number of leads. The pitch spacing between the leads must be relatively small. Unfortunately, the space limitations imposed by such fine pitch spacing are problematic. Traditional lead frames must be relatively rigid structures in order to maintain their required self-supporting characteristics. If the pitch spacing between the leads of a lead frame is reduced to fit more leads within a given area, the leads necessarily become smaller and their rigidity is unacceptably reduced. Traditional lead frames have proven incapable of providing a large number of fine pitched leads. An alternative solution is desired.

Therefore, a system for producing a package of systems is desired that allows fine pitch leads to be used.

SUMMARY OF THE INVENTION

The invention relates generally to a package and more particularly to a system of devices within a single package. The package includes a interconnect substrate with a plurality of conductive interconnects. The interconnects are configured to permit electrical connections to be made between connectors with relatively fine pitch spacing to connectors with relatively large pitch spacing.

The die is bonded electrically with a composite material in such a manner that the intricate pattern requirement of the integrated circuit wirebonding corresponds to traced connections rerouted within the bulk of the composite material toward the underside of the die. These rerouted trace pads of the composite material are bonded directly to the arrayed pads at a first side of the premolded leadframe substrate.

Corresponding reference characters indicate corresponding parts throughout the several views. The examples set out herein illustrate several embodiments of the invention but should not be construed as limiting the scope of the invention in any manner.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring toFIG. 1A, package100includes conductive traces102aand102b, integrated circuit104, active or passives devices103and105, interconnect substrate106, and molding compound108.FIG. 1Bis a cut-out perspective view of package100ofFIG. 1A. Interconnect substrate106has electrical interconnects107which are embedded in the interconnect substrate and extend from the upper contacts to the lower contacts. The contacts on the upper surface of the interconnect substrate are electrically connected to device104. The contacts on the lower surface of the interconnect substrate are electrically connected to traces,102aand102b. Interconnect substrate106may be a small batch of BT (Bismaleimide Triazine) or FR4 (flame retardant 4) laminate/flex or equivalent composite material. The electrical interconnects107are rerouted to fully utilize the space underneath the interconnect substrate106. Molding compound108preferably includes a silica or inorganic-filled mold compound. Such a molding compound helps to reduce moisture absorption compared to an organic laminate.

FIG. 1Cshows an expanded view of the interconnect substrate106. The contacts on the upper surface of substrate106have a fine pitch spacing110. The contacts on the lower surface of substrate106have a larger pitch spacing112. Substrate106allows fine pitch110to be expanded to larger pitch spacing112. The process for forming package100with interconnect substrate106is outlined inFIG. 2AtoFIG. 5B. The process begins withFIG. 2A.

FIG. 2Ashows pre-molded conductive trace frame200that includes a plurality of conductive traces such as trace102a. As show inFIG. 2B, the frame200is partially encased in molding compound202such that at least the upper surface of the frame200remains exposed. In some embodiments, the lower surface of frame200remains exposed. In other embodiments, only a surface of the frame200is exposed on the lateral edges of the package.

FIG. 3Ashows substrate106being attached to conductive trace frame200. As show inFIG. 3A, the lower surface of substrate106has a plurality of lower contacts300. These lower contacts300are spaced to mate with corresponding trace contacts302on the top surface of the conductive trace frame200. The lower contacts may be arranged into a regular pattern. For example, inFIG. 3A, the lower contacts are in a grid formation. Other suitable patterns would be apparent to one skilled in the art after benefiting from reading this specification.FIG. 3Bshows substrate106after it has been mounted to frame200. Upper contacts308are visible inFIG. 3B.

Upper contacts308are arranged in a ring about central region306, which serves as the mounting region for integrated circuit104(seeFIG. 1A). As discussed elsewhere in this specification, the fine spacing between the contacts on the upper surface is smaller than the spacing between the contacts on the lower surface of substrate106. In assembly304depicted inFIG. 3B, such increased spacing is accommodated by having at least one of the lower contacts dispersed under the central region306on the lower surface, whereas the central region306is devoid of corresponding upper contacts on the upper surface.

FIG. 4AandFIG. 4Bshow a top and bottom perspective view, respectively, of assembly304.FIG. 4Bshows the bottom surface of conductive frame200(seeFIG. 2A) and depicts the exposed, bottom trace contacts400.

FIG. 5Ais a perspective view of assembly304after integrated circuit104has been wirebonded to the upper contacts such that electrical connections have been formed to the contacts on the upper surface of substrate106. A plurality of other active and/or passive devices500have also been mounted to the frame200. There is no limit on the number or types of devices. Such devices may include, but are not limited to, logic integrated circuits, DRAMS, SRAMS, programmable logic devices, flash memories, power devices such as diodes, MOSFETS, IGBTs, thyristors, capacitors, inductors and resistors. InFIG. 5A, the integrated circuit104is mounted in the corner of the package. The leads extend out of all four sides (500,502,504and506) of device104but, due to the space-saving configuration of interconnect substrate106and frame200, the leads are routed to two adjacent sides (508and510). InFIG. 5A, such a configuration is obtained by running some of the leads under a portion of integrated circuit104(see the leads inFIG. 3A). This mounting configuration is substantially more compact than prior art mounting techniques and permits a higher density of devices to be mounted within a small package.

In contrast,FIG. 5Billustrates a more conventional approach. InFIG. 5B, the device512is connected to the external environment by leads516. Other devices514are also present. Since the leads516extend in all four directions from device512, a significant amount of surface area is lost to such leads and the resulting package cannot support as many devices. Nevertheless, the configuration ofFIG. 5Bis deemed within the scope of the claims and is one embodiment of the invention.

FIG. 5Cshows the package100after the entire assembly ofFIG. 5Ahas been encased in molding compound108. Electrical contacts to frame200are available on the bottom and lateral surfaces of package100.

In one embodiment, shown inFIG. 6A, the trace contacts on the bottom surface of package100remain exposed to the environment. In another embodiment, shown inFIG. 6Bas package600, a ball grid array (BGA)602is disposed on the bottom surface to facilitate the formation of electrical connections to the package100. The ball grid array is comprised of a multiplicity of conductive balls604.

FIG. 6Cis a side view of another embodiment of the invention. In the embodiment ofFIG. 6C, folded clips606aand606bare folded about device608aand608brespectively. Clips606aand606bare electrically conductive and are disposed about the devices such that an electrical connection is made between the upper surface of the devices and the conductive traces, such as trace607. In some embodiments, such as that shown inFIG. 6C, the upper surface of the clips606aand606bare enclosed within the molding compound108. In other embodiments, such as that shown inFIG. 6D, the upper surface of the clips610aand610bare exposed to the environment outside molding compound108. Such an embodiment is useful for efficiently dissipating heat away from the device. An example of such an embodiment is shown inFIG. 6E. In particular devices608a,608bcould be power MOSFETS. Each is flip chip mounted so the drain faces up while the source and gate contacts are ball attached to the contacts within the interconnect substrate. Clips606aand606bare electronically and mechanically attached to the drains of the MOSFET. The clips have depending arms618that terminate in ball or flat contact connections to the trace.

FIG. 6Eis a side view of one device ofFIG. 6D. In the example shown inFIG. 6E, the device is a MOSFET with a gate612(connected to conductive trace612a), a source614(connected to conductive traces614a) and a drain616. The drain616is connected to conductive traces616athrough folded clip610a.

FIG. 7Ais a close-up view of the device104ofFIG. 6A. Electrical connections between the device104and the upper contacts308are made with wires702. Such wires may be connected by conventional wirebonding techniques. Interconnects107are clearly shown within substrate106. Each interconnect forms an electrical connection between upper contact308and lower contact300. This permits the pitch spacing of the lower contacts300to be larger than the pitch spacing of the upper contacts308(seeFIG. 1Cand the associated discussion). Device104is attached to substrate106with insulating adhesive700.

FIG. 7Bis a perspective view of substrate106and trace200showing electrical interconnect107connecting upper contact308to lower contact300. Lower contact300is disposed directly above trace contact302on trace200. For clarity of illustration, a single pair of contacts is shown, although it is clear that multiple contacts are commonly present. Electrical interconnect107moves along both vertical direction704aand704band along horizontal direction706aand706b. In the embodiment depicted, there are two horizontal sections706aand706bwhich allow the upper contact308to be non-aligned with respect to lower contact300. These two sections706aand706bare orientated at relatively sharp angles to one another. InFIG. 7B, the angle is approximately ninety degrees. In another embodiment, a single horizontal section, rather than two horizontal sections, is used to allow the upper and lower contacts308and300to be non-aligned.

While the invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof to adapt to particular situations without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.