Logarithmic function generating system

A logarithmic function generating system which generates an output signal bearing a logarithmic functional relation to the input signal. The time constant RC of a resistance-capacitance circuit is increased for every unit time elapsed in proportion to the unit time to produce a broken line approximating the logarithmic function. With its simple circuit construction employing no elements whose characteristics vary with ambient temperature changes or which tend to involve variations in characteristics among the elements of the same type, the system is capable of generating the desired logarithmic function output with a high degree of accuracy.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a logarithmic function generating system 
wherein the time constant of a time constant circuit is increased 
successively and a logarithmic function with a time as a variable is 
generated by approximating it with a broken line. 
2. Description of the Prior Art 
The logarithmic function generators heretofore known in the art include for 
example analog type logarithmic function generators wherein the fact that 
the voltage-current characteristic of diodes is a logarithmic 
characteristic is utilized to generate an output voltage bearing a 
logarithmic relation to the input voltage and digital type logarithmic 
function generators wherein a logarithmic function is generated in an 
approximate manner in accordance with series expansion formulas of the 
logarithmic function. In the case of the former analog type generators, 
due to nonuniformity in the characteristics of diodes of the same type, it 
has been difficult to obtain logarithmic function generators having the 
uniform characteristics. There has been another disadvantage that the 
characteristics of diodes are liable to change with temperature changes 
and hence the resulting logarithmic function voltage is unstable. 
In the case of the digital type generators, it has been necessary to use a 
complicated computing circuit for realizing the required series expansion 
formulas. There has been another disadvantage that the circuit 
construction tends to become extremely large and complicated in order to 
ensure a high degree of accuracy. 
SUMMARY OF THE INVENTION 
It is an object of this invention to provide a logarithmic function 
generating system which employs no such elements whose characteristics 
vary considerably with changes in the ambient temperature or such elements 
which tend to involve variations in the characteristics among the elements 
of the same type, but is capable of generating highly accurate logarithmic 
function voltages with a simple circuit construction. 
In accomplishing the above and other equally desirable objects, the 
logarithmic function generating system provided in accordance with this 
invention is designed so that clock signals having a predetermined 
frequency are counted to change a time constant in accordance with a 
setting signal which is changed gradually each time a predetermined unit 
time expires, and a capacitor voltage is developed with a charging slope 
gradually varying with changes in the time constant, whereby the capacitor 
voltage gives a broken line approximation to a logarithmic function with a 
time as a variable. 
The system of this invention has among its great advantages the fact that 
it is capable of generating a logarithmic function voltage with a high 
degree of accuracy using a very simple circuit construction which is 
realized through the combination of the digital operation of a time 
constant setting circuit and the analog operation of a time constant 
circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
The present invention will now be described in greater detail with 
reference to the illustrated embodiment. 
The basic principles of the system of this invention will be described 
first with reference to the characteristic diagrams of FIGS. 1 and 2. With 
the logarithmic function V = k.log t (where V and t are variables and k is 
a constant) shown in FIG. 1, dV/dt = k . (1/t). Consequently, where the 
variable t changes by a fixed value t.sub.o as t.sub.0, 2t.sub.0, 
3t.sub.0, . . . , nt.sub.0 (n is an integer), the slope of the tangent to 
the curve at each of the corresponding points A.sub.1, A.sub.2, A.sub.3, . 
. . , A.sub.n is given as follows. Namely, assuming that M.sub.1 
represents the slope of the tangent at the point A.sub.1, then the slopes 
of the tangents at the points A.sub.1, A.sub.2, A.sub.3, . . . , A.sub.n 
are given as M.sub.1, M.sub.1 /2, M.sub.1 /3, . . . , M.sub.1 /n which 
are inversely proportional to the variable t. 
If these tangents are connected to one another, the resulting broken line 
approximates the logarithmic function V = k . log t. In this case, it is 
evident that the smaller the value of the fixed value t.sub.0 is, the 
greater the accuracy of approximation of a logarithmic function with a 
broken line becomes. 
These tangents will now be examined in greater detail. With the logarithmic 
function V = k.log t, if the variable t is replaced with a time and the 
variable V is replaced with a voltage as shown in FIG. 2, where the value 
of the fixed value t.sub.0 is sufficiently small, each of the tangents may 
be approximated by the charging curve of a resistance-capacitance circuit 
obeying an equation V = E.[1-exp (-(1/RC). t)]. In this equation, E is a 
constant voltage, R is the resistance value of a resistor and C is the 
capacitance value of a capacitor. The reason for this is that the slope of 
the tangent of the resistor-capacitor charging curve given by the above 
equation is given as dV/dt = E.exp (- t/RC)/RC, so that if RC &gt;&gt;t, then 
the slope of the tangent may be approximated as dV/dt = E.(1/RC). This 
equation is of the same form as the tangent slope equation dV/dt = k.(1/t) 
for the logarithmic function V = k.log t. Consequently, to fit the 
charging curve to each of the tangents of the logarithmic function V = 
k.log t which are shown by the dotted lines in FIG. 1, it is necessary 
that the time constant .tau. in the equation V = E[1-exp (-(1/RC).t)] is 
increased successively as RC, 2RC, 3RC, . . . , nRC as the time t in the 
equation V = k.log t is increased as t.sub.0, 2t.sub.0, 3t.sub.0, . . . , 
nt.sub.0 by a unit time t.sub.0, thereby producing a curve that 
approximates the broken line approximation to the logarithmic function V = 
k.log t. 
Referring now to FIG. 3 showing a wiring diagram for an embodiment of the 
system of this invention, numeral 1 designates a time constant setting 
circuit for generating a setting signal corresponding to the number of 
input pulse signals, 2 a resistance-capacitance time constant circuit 
(hereinafter simply referred to as an RC charging circuit) whose time 
constant varies in accordance with the output setting signal of the time 
constant setting circuit 1. The detailed constructions of these circuits 
are as follows. The time constant setting circuit 1 comprises a binary 
counter 11 (such as the Motorola MC 14040), inverters 12a, 12b, 12c and 
12d respectively connected to the first-position to fourth-position 
outputs Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 of the binary counter 11, a 
NAND gate 13 for receiving as its inputs the third-position output Q.sub.3 
and fifth-position output Q.sub.5 of the binary counter 11, an inverter 14 
for inverting the output of the NAND gate 13, a D-type flip-flop 15 for 
delaying the output of the NAND gate 13 and applying it to a reset 
terminal R of the binary counter 11 and an inverter 16 connected to a 
clock input terminal CL of the binary counter 11. The RC charging circuit 
2 comprises series-connected resistors 21a and 21b of a resistance value 
R, resistor 21c of a resistance value 2R, resistor 21d of a resistance 
value 4R and resistor 21e of a resistance value 8R, analog switches 22a, 
22b, 22c and 22d (such as the RCA CD4016) respectively connected to the 
ends of the resistors 21b, 21c, 21d and 21e and disposed to receive as 
their control inputs the outputs of the inverters 12a to 12d, 
respectively, a capacitor 23 having a capacitance value C and connected to 
the end of the resistor 21e and an analog switch 24 connected in parallel 
with the capacitor 23 and disposed to receive as its control input the 
fifth-position output Q.sub.5 of the binary counter 11. Numerals 6, 7 and 
8 designate terminals for respectively receiving a preset voltage V.sub.i, 
constant voltage V.sub.c and clock signals of a predetermined frequency. 
In this embodiment, as shown in FIG. 3, there are further provided a 
comparator 3, an R-S flip-flop 4 and an AND gate 5 so that a pulse signal 
of a time width bearing a logarithmic relation to the preset voltage 
V.sub.i applied to the terminal 6 is generated. 
With the construction described above, the operation of this embodiment 
will now be described with reference to FIG. 4. When the reset signal 
shown in (d) of FIG. 4 is applied to the reset terminal R of the binary 
counter 11, the binary counter 11 is reset so that all of the outputs 
Q.sub.1 to Q.sub.5 go to a low level (hereinafter simply designated by a 
logical symbol "O") and all of the outputs of the inverters 12a to 12d go 
to a high level (hereinafter simply designated by a logical symbol "1"). 
On the other hand, when a "1" control input is applied to the control 
input terminal c of each of the analog switches 22a through 22d, 
conduction occurs between its input terminal i and output terminal o, 
whereas when a "0" control input is applied to the control input terminal 
c the conduction between the input and output terminals i and o is 
terminated. Thus, when the binary counter 11 is reset, the analog switches 
22a to 22d are all turned on and only the analog switch 24 is turned off. 
In this condition, the resistance value between the terminal 7 and a point 
X in FIG. 3 is R and the potential at the point X rises according to a 
function V = VC.(1-exp(-t/RC)) as shown in (e) of FIG. 4. Assuming that 
the clock signals having a predetermined frequency and applied to the 
binary counter 11 has a period t.sub.0 as shown in (a) of FIG. 4, at the 
expiration of the unit time t.sub.0 after the application of the reset 
signal, the count of the binary counter 11 is advanced by "1" so that the 
first-position output Q.sub.1 goes to "1" and the other outputs Q.sub.2 to 
Q.sub.5 go to "0". Consequently, the analog switch 22a is turned off, 
while the analog switches 22b to 22d remain on and the analog switch 24 
also remains off, causing the resistance value between the terminal 7 and 
the point X to become 2R. Thus, the potential at the point X starts rising 
with a time constant 2RC as shown in (e) of FIG. 4 after the expiration of 
the time t.sub.0. Thereafter, each time the unit time t.sub.0 expires, the 
time constant of the RC charging circuit 2 is increased in proportion to 
the time expired, thus increasing the time constant from RC to 2RC, 3RC, . 
. . , 16RC. Thus, as shown in (e) of FIG. 4, the voltage waveform 
generated at the point X consists of 16 interconnected charging curves 
with different time constants and it is evident that as previously noted 
this voltage waveform approximately realizes the broken line approximation 
to the logarithmic function which is shown by the dotted lines in FIG. 1. 
Then, at the expiration of 16 t.sub.0 times after the application of the 
reset signal, all of the outputs Q.sub.1 through Q.sub.4 of the binary 
counter 11 go to "0" and the fifth-position output Q.sub.5 shown in (c) of 
FIG. 4 goes to "1". Consequently, the analog switches 22a to 22d and 24 
are all turned on and the charge stored in the capacitor 23 is discharged 
decreasing the potential at the point X instantaneously to 0 volt as shown 
in (e) of FIG. 4. Thereafter, when 4 clock signals are applied further to 
the binary counter 11, the third-position output Q.sub.3 of the binary 
counter 11 which is shown in (b) of FIG. 4, goes to "1" and the output of 
the NAND gate 13 goes to "0". The output of the NAND gate 13 is inverted 
by the inverter 14, delayed by one clock period or unit time t.sub.0 and 
then applied to the reset terminal R of the binary counter 11. When this 
occurs, the binary counter 11 is reset clearing all of its outputs Q.sub.1 
to Q.sub.5 to "0" and restoring the initial conditions and the RC charing 
circuit 2 starts again its charging action with the time constants RC, 
2RC, 3RC, . . . . In this embodiment, the inverter 16 is connected to the 
clock input terminal CL of the binary counter 11 to adjust the phase 
relationships between the binary counter 11 and the D-type flip-flop 15 
since the binary counter 11 counts the applied clock signals at their 
falling edges and the D-type flip-flop 15 changes its state in response to 
the rising edges of the clock signals. 
The point X is also connected to the noninverting input of the comparator 3 
which compares the voltage at the point X with the preset voltage V.sub.i 
which is applied to its inverting input. Since the output of the 
comparator 3 is connected to a reset terminal R of the R-S flip-flop 4 and 
the output of the inverter 14 is connected to the set input terminal of 
the R-S flip-flop 4, when the count value of the binary counter 11 reaches 
20 so that the third-position output Q.sub.3 and the fifth-position output 
Q.sub.5 go to "1", the output of the inverter 14 goes to "1" and the R-S 
flip-flop 4 is set causing its Q output to go to "1" as shown in (f) of 
FIG. 4. Then, when the voltage at the point X rises and becomes higher 
than the preset voltage V.sub.i applied to the inverting input of the 
comparator 3, the output of the comparator 3 goes from "0" to "1". As a 
result, the R-S flip-flop 4 is reset and its Q output goes to "0" 
producing the pulse width shown in (f) of FIG. 4. The Q output of the R-S 
flip-flop 4 and the output of the inverter 14 are applied to the AND gate 
5 so that the time width t.sub.0 of the set pulse is substracted from the 
pulse width shown in (f) of FIG. 4 and the pulse of the pulse width 
t.sub.Q shown in (g) of FIG. 4 is generated at the output of the AND gate 
5. In this case, it is evident that a relation approximating to the 
equation V.sub.i = k.log t.sub.Q (where k is a constant) holds between the 
time width t.sub.Q and the preset voltage V.sub.i. The R-S flip-flop 4 
serves to prevent the occurrence of a chattering phenomenon to the output 
of the comparator 3 due to the effect of the accuracy of detection or the 
response characteristics of the comparator 3. In other words, once a "1" 
has been applied to the reset input R of the R-S flip-flop 4 changing its 
Q output to "0", the Q output remains in the same state until a "1" is 
applied to the set input S and in this way any chattering produced in the 
output of the comparator 3 is cancelled. 
In the above-described embodiment, while the charging time constant for 
each interval is increased in proportion to the t, due to the fact that 
the voltage rise V.sub.n-1 up to the end of the preceding interval is 
added as an initial charge, a potential V.sub.n at the point X for the 
n-th interval is given by the following equation: 
EQU V.sub.n = (V.sub.c - V.sub.n-1).[1-exp(-t/nRC)]+V.sub.n-1 
Modifying the above equation yields: 
EQU dV.sub.n /dt = (V.sub.c -V.sub.n-1).exp(-t/nRC)/nRC 
thus, the slope of the tangent is no longer inversely proportional to the 
time and slopes gradually deviate from the broken line shown by the dotted 
lines in FIG. 1. However, it has been found that if the frequency of clock 
signals and the constant voltage V.sub.c are respectively selected 4096 Hz 
and 6 V, with a specified time constant, the resulting approximation 
errors with respect to the computed values would be less than .+-.3% under 
a range 200 (.mu.sec) &lt; t.sub.Q &lt;3.5 (m sec), making it possible to 
produce with a sufficiently high degree of accuracy a logarithmic function 
voltage with a time as a variable and put it to practical use. Further, if 
the clock signal frequency is increased, the desired approximation 
accuracy may be obtained even if the predetermined time constant is 
decreased, while the similar approximation accuracy may be obtained by 
setting the frequency and the time constant conversely. Still further, it 
is possible to correct the previously mentioned deviations with the lapse 
of time so as to ensure the desired approximation accuracy over a wide 
range of intervals. 
In the system of this invention, those elements which involve the problem 
of nonuniformity of characteristics or the problem of temperature 
characteristics are only the resistors 21a through 21e and the capacitor 
23 constituting the RC charging circuit 2. However, the ordinary resistors 
such as metal film resistors which are stable and highly accurate with a 
variation of about .+-.1% and a temperature coefficient of .+-. 50 
ppm/.degree. C. are available. Also, the ordinary type capacitors, such 
as, ceramic capacitors and polyester film capacitors whose temperature 
coefficients are almost zero are available. Furthermore, nonuniformity in 
the capacitance of capacitors of the same type is included in the constant 
k of the logarithmic function V = k.log t and is easily adjustable. Thus, 
it is possible to provide a stable and highly accurate logarithmic 
function generating system in which the variations in the characteristics 
of the elements are reduced or the effects of the temperature 
characteristics are reduced. 
Further, while the analog switches 22a through 22d are controlled to change 
the time constant of the RC charging circuit 2, this control may be 
accomplished with only the binary counter 11 and the inverters 12a through 
12d simplifying the circuitry considerably. Still further, since a pulse 
of the time width t.sub.Q can be easily generated, it is possible to 
easily obtain the number of clock pulses proportional to the output pulse 
width t.sub.Q through such an operation by which the number of clock 
signals applied during the time width t.sub.Q is counted and thus the 
system of this invention may be made to serve such functions as served by 
analog-to-digital converters. 
Further, while, in the above-described embodiment the desired logarithmic 
function voltage is approximated with 16 RC charging curves having 
different time constants, by increasing the number of bit positions in the 
binary counter 11 and adding as many analog switches and resistors as 
desired to the analog switches 22a and 22d and the resistors 21a to 21e, 
it is possible to approximate with increased accuracy the desired 
logarithmic function voltage with a broken line including a greater number 
of segments. 
Still further, by grounding the point X, inserting the analog switch 24 
between the constant voltage input terminal 7 and the resistor 21a and 
connecting the juncture of the analog switch 24 and the resistor 21a to 
the ground through the capacitor 23, the potential at the juncture of the 
analog switch 24, the resistor 21a and the capacitor 23 may be obtained as 
a voltage which decreases logarithmically as a variable of a time or an 
approximating curve V = -k.log t (k is a constant). 
Still further, while the RC charging circuit 2 is designed to change its 
time constant by varying the resistance value, it is possible to arrange 
so that a plurality of capacitors are similarly controlled by means of 
analog switches to vary the total capacitance and thereby to change the 
time constant. 
Still further, by arranging in such a manner that each of n independent 
resistors or capacitors is separately connected to n analog switches and 
each of the analog switches is controlled by a counter with a divider, the 
time constant for each interval may be determined by means of the single 
resistor or capacitor and therefore it is possible to generate with 
greater accuracy the desired logarithmic function voltage with a time as a 
variable by strictly adjusting the resistance values or capacitance 
values. Further, the resistance-capacitance (R-C) time constant circuit 
may be replaced by a resistance-inductance (R-L) time constant circuit as 
well without departing from the scope of this invention.