Band selected clock data recovery circuit and associated method

A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock data recovery (CDR) circuit, and more particularly, to a band selected CDR circuit and an associated method.

2. Description of the Prior Art

In a conventional thin film transistor (TFT) liquid crystal display (LCD) system, the ground noise from high voltage (e.g. 12 Volts) will induce jitter in a CDR circuit which causes poor performance. Furthermore, for a wide band application (160 MHz-1.8 GHz), components installed in the CDR circuit such as a voltage-controlled oscillator (VCO) are required to respond to different frequency bands in order to obtain a better performance. Otherwise, the clock signal generated by the VCO might introduce more jitter.

SUMMARY OF THE INVENTION

One of the objectives of the present invention is therefore to provide a band selected CDR circuit to solve the problems of the related art.

According to an embodiment of the present invention, a clock data recovery (CDR) circuit is disclosed, the CDR circuit comprising: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

According to an embodiment of the present invention, a clock data recovery (CDR) method for a CDR circuit is disclosed, the method comprising: generating a digital signal according to a reference voltage and a control voltage; utilizing a low dropout regulator (LDO) to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; generating a control voltage according to at least a part of the digital signal; and

utilizing a voltage-controlled oscillator (VCO) to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

DETAILED DESCRIPTION

FIG. 1is a diagram illustrating a clock data recovery (CDR) circuit10according to an embodiment of the present invention. As shown inFIG. 1, the CDR circuit10comprises typical components including a pre-amplifier1′, a differential-to-single (D2S) circuit2′, a bang bang phase detector (BBPD)3′, a phase frequency detector (PFD)4′, a multiplexer (MUX)5′, a lock detector6′, and a frequency divider7′, and further comprises a band select circuit101, a low dropout regulator (LDO)102, a voltage-controlled oscillator (VCO)103, a charge pump104, and a low pass filter105. The present invention applies a band select technique on the LDO102, the VCO103and the charge pump104(those components to the right of the dotted line). A detailed description of the above-mentioned typical components (those components to the left of the dotted line) is omitted here for brevity. The band select circuit101is arranged to generate a band select digital signal BS by comparing a control voltage VCTRL and a reference voltage VREF. Please note that, in this embodiment, the band select digital signal BS comprises three digital bits; in other words, the band select digital signal BS can be written as BS[2:0]. This is only for illustrative purposes and not a limitation of the present invention. In other embodiments, the band select digital signal BS can comprise more or less than three bits based on a designer's consideration.

The LDO102is arranged to regulate a ground voltage VSS by using a regulating ground voltage VSSVCO generated by the VCO103in order to prevent a ground noise from a high voltage influencing other circuits of the integrated circuit (IC) where the CDR circuit10is installed. The LDO circuit102is further arranged to receive at least a part of the band select digital signal BS, e.g. two bits of the band select digital signal BS (i.e. BS [2:1]), to thereby adjust the operating band of the LDO102by changing the bias current therein.

The VCO103is arranged to generate a clock signal CLK according to the control voltage VCTRL, wherein after the ground voltage being regulated by the LDO, the jitter which usually accompanies the clock signal CLK generated by the VCO103can be reduced. The VCO103is further arranged to receive the band select digital signal BS to adjust the operating band of the LDO102by changing the bias current. The architecture of the LDO102and the VCO103will be discussed in the following paragraphs.

The charge pump104is arranged to generate the control voltage VCTRL by transmitting a current Icpto the LPF105, wherein the current Icpis adjusted by at least a part of the band select digital signal BS, e.g. two bits of the band select digital signal BS (i.e. BS [2:1]). Table 1 shows the current Icpcorresponding to the two bits of the band select digital signal BS. It should be noted that the variation of the current Icpcorresponding to the band select digital signal BS is only for illustrative purposes, and not a limitation of the present invention.

As shown inFIG. 1, the LPF105comprises a resistor R1, and capacitors C1and C2, wherein a terminal of the resistor R1is coupled to a node N1, the other terminal of the resistor R1is coupled to a terminal of the capacitor C1, the other terminal of the capacitor C1is coupled to a supply voltage VDD, a terminal of the capacitor C2is also coupled to the node N1, and the other terminal of the capacitor C2is coupled to the supply voltage VDD. It should be noted that the architecture of the LPF105in this embodiment is only for illustrative purposes, and not a limitation of the present invention. Those skilled in the art should readily understand other implementations of the LPF105.

Considering a clock signal generated by a conventional CDR circuit (without the band select circuit101), assume that the conventional CDR circuit is operating in a high operating band. When the frequency of the clock signal is low, the strong (due to the high operating band) current Icpgenerated by the charge pump104causes a huge variation in the control voltage VCTRL which results in a huge variation in the frequency of the clock signal. Assuming that the conventional CDR circuit is operating in a low operating band, when the frequency of the clock signal is high, the weak (due to the low operating band) current Icpgenerated by the charge pump104means the control voltage VCTRL can only vary within a small range which results in poor spreading spectrum ability. With the band select circuit101proposed by the present invention which dynamically adjusts the current Icp, the bias current of the VCO103, and the bias current of the LDO102in response to the different frequency bands, the abovementioned problem can be effectively solved. More specifically, the LDO102and the VCO103can operate in a low operating band by reducing the bias current in response to a low frequency band, and operate in a high operating band by increasing the bias current in response to a high frequency band. The detailed operation will be described in the following paragraphs.

It should be noted that the architecture of the band select circuit101is not a limitation of the present invention. As long as the band select circuit101can generate the band select digital signal BS to adjust the operating band of the LDO102and the VCO103in response to the frequency of the control voltage VCTRL, all architectures fall within the scope of the present invention. For example, the band select circuit101can be implemented by comparators and logic gates.

FIG. 2is a diagram illustrating the LDO102of the CDR circuit10according to an embodiment of the present invention. The LDO102comprises a bias control circuit201, an amplifier202, a transistor T1, resistors R2and R3, wherein the bias control circuit201is arranged to receive at least a part of the band select digital signal BS, e.g. two bits of the band select digital signal BS (i.e. BS[2:1]), to control a bias current Ibiaspassing through the amplifier202. Please note that, in this embodiment, the transistor T1is implemented by an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS); however, this is only for illustrative purposes, and not a limitation of the present invention. Table 2 shows the bias current Ibiascorresponding to the two bits of the band select digital signal BS (i.e. BS[2:1]).

The amplifier202is arranged to generate an output voltage Voutto a gate terminal of the transistor T1according to a feedback voltage Vfeedand the reference voltage VREF. As shown inFIG. 2, a source terminal of the transistor T1is coupled to the ground voltage VSS while the regulating ground voltage VSSVCO is received at a drain terminal of the transistor T1, and a terminal of the resistor R2is coupled to the drain terminal of the transistor T1, the other terminal of the resistor R2connected to a terminal of the resistor R3is connected to a node Nfeed, and the other terminal of the resistor R3is coupled to the supply voltage VDD. The feedback voltage Vfeedreceived by the amplifier202is generated at the node Nfeed. By adjusting the bias current Ibiaswith the band select digital signal BS, the operating band of the LDO102can be adjusted to respond to different frequency bands of the CDR circuit100.

FIG. 3is a diagram illustrating the VCO103of the CDR circuit10according to an embodiment of the present invention. The VCO103comprises a current generating circuit301and a control circuit302, wherein the current generating circuit301comprises a transistor T2, and the control circuit302comprises a plurality of transistors CT0-CT9. The transistor T2of the current generating circuit301generates a reference current Irefat a drain terminal of the transistor T2by receiving the control voltage VCTRL with a gate terminal of the transistor T2. The plurality of transistors CT0-CT9of the control circuit302operates as current mirrors by receiving the reference current Ireffrom the transistor T2. The operation of a current mirror should be well known to those skilled in the art; the detailed description is therefore omitted here. It should be noted that the gate terminals of the transistors CT0-CT7are coupled to corresponding switches SW0-SW7which are controlled by the band select digital signal BS. More specifically, the band select digital signal BS is first converted into a thermal code which comprises 8 bits (band0-band7) as shown in Table 3, wherein each bit of the thermal code is arranged to control the switches SW0-SW7corresponding to the transistors CT0-CT7shown inFIG. 3.

The VCO103further comprises a plurality of inverters inv1-inv6driven by a bias current Idrivecomposed of the current generated from the transistors CT0-CT7. The more switches turned on by the thermal code, the stronger the bias current Idrive. By adjusting the bias current Idrivewith the band select digital signal BS, the operating band of the VCO103can be adjusted correspondingly to respond to different frequency bands of the CDR circuit100. In addition, by adjusting the current ICPwith the band select digital signal BS, the control voltage VCTRL received by the transistor T2is correspondingly adjusted, causing an adjustment in the reference current IREF. In other words, the adjustment of the current ICPwith the band select digital signal BS can also adjust the operating band of the VCO103.

FIG. 4is a diagram illustrating the operating band of the VCO103corresponding to the control voltage VCTRL and the band select digital signal BS according to an embodiment of the present invention. As shown inFIG. 4, when the control voltage VCTRL changes from 0.3 Volt to 1 Volt, the operating band of the VCO103varies within a small range. When the band select digital signal BS changes, the operating band of the VCO103varies within a big range. In this embodiment, the control voltage VCTRL varies from 0.3 Volt to 1 Volt and the operating band of the VCO103varies from 160 MHz to 1.8 GHz. This is only for illustrative purposes, however, and not a limitation of the present invention.

It should be noted that the number of the inverters for generating the clock signal CLK and the number of the transistor for generating the bias current Idrivedetailed in the specification are only for illustrative purposes, and are not a limitation of the present invention. For example, the VCO103can receive only a part of the band select digital signal BS, e.g. two bits of the band select digital signal BS (BS[2:1]). In this case, only 4 transistors are needed to generate the bias current Idrive. These alternative designs also fall within the scope of the present invention.

Briefly summarized, the present invention proposes a CDR circuit with a band select circuit which can prevent jitter from the clock signal. More specifically, with the band select circuit101, the LDO102and the VCO103can operate in a low operating band in response to a low frequency band and can operate in a high operating band in response to a high frequency band. In this way, the jitter caused by a huge variation in the clock signal frequency can be reduced.