Resistor structures of integrated circuit devices including stacked transistors and methods of forming the same

Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

FIELD

The present disclosure generally relates to the field of electronics and, more particularly, to integrated circuit devices including stacked transistors.

BACKGROUND

Integrated circuit devices may include resistors having various resistance values for different purposes. For example, a DC bias circuit may include a resistor having a high resistance value (e.g., about 10 kiloohms), and a feedback path for reducing an IR drop or a load may include a resistor having a low resistance value (e.g., about 100 ohms or lower). Integrated circuit devices including stacked transistors, such as a complementary field effect transistor (CFET) stack, were introduced to reduce the area of integrated circuit devices, thereby increasing the integration density. Accordingly, resistor structures that can be formed by manufacturing processes compatible with manufacturing processes of stacked transistors and can have various resistance values may be desirable.

SUMMARY

According to some embodiments of the present invention, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts. In some embodiments, an integrated circuit device may include the resistor structure and a stacked transistor structure. The stacked transistor structure may include an upper transistor comprising an upper source/drain region and a lower transistor that may be between the substrate and the upper transistor and may include a lower source/drain region. The the upper semiconductor layer and the upper source/drain region may include the same material and may have an equal thickness in the vertical direction, and the lower semiconductor layer and the lower source/drain region may include the same material and may have an equal thickness in the vertical direction.

According to some embodiments of the present invention, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, and a lower semiconductor layer that may be between the substrate and the upper semiconductor layer. At least two of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may be configured to function as respective resistors that are connected in parallel.

According to some embodiments of the present invention, methods of forming an integrated circuit device may include forming a resistor structure. Forming the resistor structure may include forming a lower thin semiconductor layer and an upper thin semiconductor layer on a substrate. The lower thin semiconductor layer may be spaced apart from the substrate in a vertical direction and may be between the substrate and the upper thin semiconductor layer. Forming the resistor structure may also include forming a lower semiconductor layer by performing a first epitaxial growth process using the lower thin semiconductor layer as a first seed layer, forming an upper semiconductor layer by performing a second epitaxial growth process using the upper thin semiconductor layer as a second seed layer, and forming first and second resistor contacts that may be spaced apart from each other in a horizontal direction and may contact at least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate.

DETAILED DESCRIPTION

Resistor structures and methods of forming the same pursuant to embodiments of the present invention can simplify manufacturing processes of an integrated circuit device that includes both resistor structures and stacked transistors, as common manufacturing processes can be used to form elements of the resistor structures and stacked transistors.

Processes of forming stacked transistors may form multiple semiconductor elements (e.g., a first upper semiconductor layer26U_1, a first lower semiconductor layer26L_1and a first portion12_1of a substrate10inFIG.5), each of which can be used as a resistor, and may also form conductive contacts (e.g., a first resistor contact32_1and a second resistor contact32_2inFIG.5) that are electrically connected to at least one of those three semiconductor elements and thus can be used as resistor contacts. Accordingly, a resistor structure according to some embodiments of the present invention may be formed by processes of forming stacked transistors without additional processes.

According to some embodiments of the present invention, resistor elements may be formed to have different resistance values by adjusting, for example, a material and/or an impurity concentration, and resistor structures having various resistance values may be formed by electrically connecting different sets of those resistor elements.

According to some embodiments of the present invention, a resistor structure may include multiple resistor elements that are electrically connected in parallel and have different respective resistance values, and thus it may be easier to reduce a deviation of a resistance value of the resistor structure from a pre-determined resistance value.

As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Further, as used herein, “formed concurrently” refers to being formed by the same fabrication process(es), at approximately (but not necessarily exactly) the same time.

FIGS.1to3are schematic illustrations of various first resistor structures RS1. Referring toFIG.1, a first resistor structure RS1_1may include a first resistor element R1, a second resistor element R2and a third resistor element R3that are all electrically connected to a first resistor contact RC1and a second resistor contact RC2. The first, second and third resistor elements R1, R2, and R3may be electrically connected to each other in parallel.

For example, the first, second and third resistor elements R1, R2, and R3may be an upper semiconductor layer (e.g., a first upper semiconductor layer26U_1inFIG.5), a lower semiconductor layer (e.g., a first lower semiconductor layer26L_1inFIG.5) and a portion of a substrate (e.g., a first portion12_1of a substrate10inFIG.5), respectively.

Referring toFIG.2, the first and second resistor contacts RC1and RC2of each of the first resistor structures RS1_2, RS1_3and RS1_4may be electrically connected to two of the first, second and third resistor elements R1, R2, and R3, and may be electrically isolated from the remaining one of the first, second and third resistor elements R1, R2, and R3.

Referring toFIG.3, the first and second resistor contacts RC1and RC2of each of the first resistor structures RS1_5, RS1_6and RS1_7may be electrically connected to one of the first, second and third resistor elements R1, R2, and R3and may be electrically isolated from the remaining two of the first, second and third resistor elements R1, R2, and R3. The first resistor structures RS1illustrated inFIGS.1to3may have various resistance values, as different sets of the first, second and third resistor elements R1, R2, and R3are electrically connected to each other.

FIG.4is a plan view of an integrated circuit device according to some embodiments of the present invention.FIGS.5and6are side views of the integrated circuit device from viewpoints V and W inFIG.4, respectively, according to some embodiments of the present invention. Specifically,FIG.5shows an example configuration of elements of the first resistor structure RS1_1inFIG.1.FIGS.7and8are cross-sectional views of the integrated circuit device taken along the line A-A′ and the line B-B′ inFIG.4, respectively, according to some embodiments of the present invention. For simplicity of illustration,FIG.4does not show some elements (e.g., conductive wires36and an interlayer insulating layer42) inFIGS.5-8.

Referring toFIGS.4through8, the integrated circuit device may include a stacked transistor structure ST on a substrate10and a first resistor structure RS1. The substrate10may include a first surface S1and a second surface S2. The first surface S1and the second surface S2may be opposite and parallel to each other. The first surface S1may be a front side of the substrate10, and the second surface S2may be a backside of the substrate10.

FIG.4illustrates that the stacked transistor structure ST is spaced apart from the first resistor structure RS1in a first direction D1, but the present invention is not limited thereto. In some embodiments, the stacked transistor structure ST may be spaced apart from the first resistor structure RS1in any direction. The first direction D1may be parallel to the first surface S1and the second surface S2of the substrate10and may be a first horizontal direction.

The first resistor structure RS1may include a first upper semiconductor layer26U_1and a second upper semiconductor layer26U_2that may be spaced apart from the first upper semiconductor layer26U_1in a second direction D2. The second direction D2may be parallel to the first surface S1and the second surface S2of the substrate10and may be a second horizontal direction. The second direction D2may be different from the first direction D1, and in some embodiments, the second direction D2may be perpendicular to the first direction D1. The first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2may have a first conductivity type (e.g., an N-type conductivity or a P-type conductivity).

Each of the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2may have a first thickness T1in a third direction D3. The third direction D3may be perpendicular to the first and second directions D1and D2and may be a vertical direction.

A first upper thin semiconductor layer22U_1may be provided between the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2and may contact both the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2. In some embodiments, the first upper thin semiconductor layer22U_1may contact side surfaces of the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2as illustrated inFIG.8. The first upper thin semiconductor layer22U_1may have a conductivity type that is different from the conductivity type of the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2. In some embodiments, the first upper thin semiconductor layer22U_1may include a material different from the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2. For example, the first upper thin semiconductor layer22U_1may include a silicon layer, and each of the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2may include a silicon germanium layer.

The first upper thin semiconductor layer22U_1may have a third thickness T3in the third direction D3, and the third thickness T3may be thinner than the first thickness T1. For example, the third thickness T3may be in a range of from 1 nm to 100 nm, and the first thickness T1may be at least 1.5 times the third thickness T3.

The first resistor structure RS1may also include a first lower semiconductor layer26L_1and a second lower semiconductor layer26L_2that may be spaced apart from the first lower semiconductor layer26L_1in the second direction D2. A first lower thin semiconductor layer22L_1may be provided between the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2and may contact both the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2. In some embodiments, the first lower thin semiconductor layer22L_1may contact side surfaces of the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2as illustrated inFIG.8.

The first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2may have a second conductivity type that is different from the first conductivity type. The first lower thin semiconductor layer22L_1may have a conductivity type that is different from the conductivity type of the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2. In some embodiments, the first lower thin semiconductor layer22L_1may include a material different from the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2. For example, the first lower thin semiconductor layer22L_1may include a silicon layer, and each of the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2may include a silicon germanium layer.

Each of the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2may have a second thickness T2in the third direction D3. The first lower thin semiconductor layer22L_1may have a fourth thickness T4in the third direction D3, and the fourth thickness T4may be thinner than the second thickness T2. For example, the fourth thickness T4may be in a range of, for example, from 1 nm to 100 nm, and the second thickness T2may be at least 1.5 times the fourth thickness T4.

Further, the first resistor structure RS1may include a first portion12_1of the substrate10. The first portion12_1of the substrate10may include impurities (e.g., boron, aluminum, gallium, indium, phosphorus or arsenic) and may have the first conductivity type or the second conductivity type. The first portion12_1of the substrate10may have an impurity concentration in a range of from 1011cm−3to 1015cm−3(e.g., from 1012cm−3to 1014cm−3).

The first resistor structure RS1may additionally include a first contact32_1(also referred to as a first resistor contact) and a second contact32_2(also referred to as a second resistor contact). The first contact32_1and the second contact32_2may be spaced apart from each other in the first direction D1. Each of the first contact32_1and the second contact32_2may contact the first upper semiconductor layer26U_1, the first lower semiconductor layer26L_1and the first portion12_1of the substrate10, and thus the first upper semiconductor layer26U_1, the first lower semiconductor layer26L_1and the first portion12_1of the substrate10may be electrically connected in parallel.

AlthoughFIG.4illustrates that the first contact32_1and the second contact32_2respectively contact opposing ends of the first upper semiconductor layer26U_1and the first lower semiconductor layer26L_1, the present invention is not limited thereto. In some embodiments, at least one of the first contact32_1and the second contact32_2may contact a side surface of the the first upper semiconductor layer26U_1, which extends in the first direction D1, or a side surface of the first lower semiconductor layer26L_1, which extends in the first direction D1.

In some embodiments, a first metal layer24_1may be provided between the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2and between the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2. The first metal layer24_1may be spaced apart from the first lower semiconductor layer26L_1, the second lower semiconductor layer26L_2, the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2in the second direction D2as illustrated inFIGS.4and8. A portion of the first lower thin semiconductor layer22L_1and a portion of the first upper thin semiconductor layer22U_1may be in the first metal layer24_1as illustrated inFIGS.4,7and8.

Still referring toFIGS.4through8, the stacked transistor structure ST may include a third lower semiconductor layer26L_3and a fourth lower semiconductor layer26L_4that may be spaced apart from the third lower semiconductor layer26L_3in the second direction D2. A second lower thin semiconductor layer22L_2may be provided between the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4and may contact both the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4. In some embodiments, the second lower thin semiconductor layer22L_2may contact side surfaces of the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4. The third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4may have the second conductivity type. The second lower thin semiconductor layer22L_2may be a lower active layer of a lower transistor, and the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4may be lower source/drain regions of the lower transistor.

Each of the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4may have the second thickness T2in the third direction D3. The second lower thin semiconductor layer22L_2may have the fourth thickness T4in the third direction D3.

The stacked transistor structure ST may also include a third upper semiconductor layer26U_3and a fourth upper semiconductor layer26U_4that may be spaced apart from the third upper semiconductor layer26U_3in the second direction D2. A second upper thin semiconductor layer22U_2may be provided between the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4and may contact both the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4. In some embodiments, the second upper thin semiconductor layer22U_2may contact side surfaces of the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4. The third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4may have the first conductivity type. The second upper thin semiconductor layer22U_2may be an upper active layer of an upper transistor, and the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4may be upper source/drain regions of the upper transistor.

Each of the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4may have the first thickness T1in the third direction D3. The second upper thin semiconductor layer22U_2may have the third thickness T3in the third direction D3.

In some embodiments, a lower surface of the first upper semiconductor layer26U_1and a lower surface of the third upper semiconductor layer26U_3may be coplanar with each other, and a lower surface of the first lower semiconductor layer26L_1and a lower surface of the third lower semiconductor layer26L_3may be coplanar with each other as illustrated inFIG.5. As used herein, “a lower surface of an element A” (or similar language) means a surface of the element A facing the substrate10.

The stacked transistor structure ST may further include a fifth contact32_5, a sixth contact32_6, a seventh contact32_7, an eighth contact32_8and a second metal layer24_2. The fifth contact32_5may contact the third lower semiconductor layer26L_3and the third upper semiconductor layer26U_3, and the sixth contact32_6may contact the second metal layer24_2. The seventh contact32_7and the eight contact32_8may contact the fourth lower semiconductor layer26L_4and the fourth upper semiconductor layer26U_4, respectively. In some embodiments, the first, second, fifth, seventh and eight contacts32_1,32_2,32_5,32_7and32_8may have upper surfaces coplanar with each other and may be at an equal height from the first surface S1of the substrate10.

The second metal layer24_2may be provided between the third lower semiconductor layer26L_3and the fourth lower semiconductor layer26L_4and between the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4. The second metal layer24_2may be spaced apart from the third lower semiconductor layer26L_3, the fourth lower semiconductor layer26L_4, the third upper semiconductor layer26U_3and the fourth upper semiconductor layer26U_4in the second direction D2as illustrated inFIG.4. A portion of the second lower thin semiconductor layer22L_2and a portion of the second upper thin semiconductor layer22U_2may be in the second metal layer24_2as illustrated inFIG.7. The second metal layer24_2may be a layer of a gate electrode. Although not shown, an insulating layer (i.e., a gate insulating layer) may be provided between the portion of the second lower thin semiconductor layer22L_2and the second metal layer24_2and between the portion of the second upper thin semiconductor layer22U_2and the second metal layer24_2.

In some embodiments, a first upper surface US1of the first upper thin semiconductor layer22U_1may be coplanar with a second upper surface US2of the second upper thin semiconductor layer22U_2as illustrated inFIG.7, and the first upper thin semiconductor layer22U_1and the second upper thin semiconductor layer22U_2may have an equal thickness in the third direction D3. In some embodiments, a third upper surface US3of the first lower thin semiconductor layer22L_1may be coplanar with a fourth upper surface US4of the second lower thin semiconductor layer22L_2as illustrated inFIG.7, and the first lower thin semiconductor layer22L_1and the second lower thin semiconductor layer22L_2may have an equal thickness in the third direction D3.

InFIG.7, the first upper semiconductor layer26U_1, the first lower semiconductor layer26L_1, the third upper semiconductor layer26U_3, the third lower semiconductor layer26L_3are represented by dotted boxes to show spatial relationships of those elements with other elements. In some embodiments, each of the first upper semiconductor layer26U_1, the first lower semiconductor layer26L_1, the third upper semiconductor layer26U_3, and the third lower semiconductor layer26L_3may overlap the entirety of a corresponding thin semiconductor layer in the second direction D2as illustrated inFIG.7. For example, the first upper semiconductor layer26U_1may overlap the entirety of the first upper thin semiconductor layer22U_1. As used herein, “an element A overlapping an element B in a direction X” (or similar language) means that there is at least one line that extends in the direction X and intersects both the elements A and B.

Although each of the first metal layer24_1and the second metal layer24_2is illustrated as a single layer, the present invention is not limited thereto. In some embodiments, each of the first metal layer24_1and the second metal layer24_2may include multiple conductive layers. For example, the first and second metal layers24_1and24_2may include a semiconductor layer (e.g., a poly silicon layer), a work function layer (e.g., TiC layer, TiAl layer, TiAlC layer or TiN layer) and/or a metal layer (e.g., a tungsten layer, an aluminum layer or a copper layer).

Further, in some embodiments, a lower portion of each of the first metal layer24_1and the second metal layer24_2may include material(s) different from an upper portion of each of the first metal layer24_1and the second metal layer24_2. Further, in some embodiments, an isolation layer may be provided between the lower portion and the upper portion of each of the first metal layer24_1and the second metal layer24_2, and the lower portion may be electrically isolated from the upper portion.

The integrated circuit device may further include first to third and fifth to eighth conductive vias34_1,34_2,34_3,34_5,34_6,34_7and34_8that may contact the first contact32_1, the second contact32_2, the first metal layer24_1, the fifth contact32_5, the second metal layer24_2, the seventh contact32_7, and the eighth contact32_8, respectively. The conductive vias34_1,34_2,34_3,34_5,34_6,34_7and34_8may be electrically connected to conductive wires36, respectively. In some embodiments, the conductive vias34_1,34_2,34_3,34_5,34_6,34_7and34_8may contact the conductive wires36, respectively, as illustrated inFIGS.5and6.

An interlayer insulating layer40may be provided on the substrate10. Although the interlayer insulating layer40is illustrated as a single layer, the interlayer insulating layer40may include multiple layers stacked on the substrate10. The first resistor structure RS1and the stacked transistor structure ST may be provided in the interlayer insulating layer40. The interlayer insulating layer40may include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and/or low-k material). The low k material may include, for example, fluorine-doped silicon dioxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymeric dielectric, or spin-on silicon based polymeric dielectric.

The substrate10may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP. In some embodiments, the substrate10may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate.

Each of the first lower thin semiconductor layer22L_1, the first upper thin semiconductor layer22U_1, the second lower thin semiconductor layer22L_2and the second upper thin semiconductor layer22U_2may include multiple thin semiconductor layers stacked in the third direction D3. For example, the first upper thin semiconductor layer22U_1may include two thin semiconductor layers as illustrated inFIGS.7and8but the present invention is not limited thereto. Each of the stacked thin semiconductor layers may be, for example, a nanosheet. The nanosheet may include semiconductor material(s) (e.g., silicon, germanium, silicon-germanium, and/or III-V semiconductor compound). For example, each of nanosheets may have a thickness in a range of, for example, from 1 nm to 100 nm in the third direction D3.

Each of the first to fourth lower semiconductor layers26L_1,26L_2,26L_3and26L_4and the first to fourth upper semiconductor layers26U_1,26U_2,26U_3and26U_4may include semiconductor material(s) (e.g., silicon, germanium, silicon-germanium) and may also include impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic). In some embodiments, the first lower semiconductor layer26L_1and the first upper semiconductor layer26U_1may be a silicon layer (e.g., an amorphous silicon layer).

The first contact32_1, the second contact32_2, the fifth contact32_5, the sixth contact32_6, the seventh contact32_7, the eighth contact32_8, the first to third and fifth to eighth conductive vias34_1,34_2,34_3,34_5,34_6,34_7and34_8, and the conductive wires36may include a metal layer (e.g., a ruthenium layer, a molybdenum layer, a copper layer, a cobalt layer, an aluminum layer and/or a tungsten layer) and/or a metal nitride layer (e.g., a titanium nitride layer and/or a tantalum nitride layer).

FIGS.9through12are side views of the integrated circuit device from the viewpoint V inFIG.4according to some embodiments of the present invention.FIG.9shows an example configuration of elements of the first resistor structure RS1_2inFIG.2according to some embodiments of the present invention. Referring toFIG.9, the first and second contacts32_1and32_2may be spaced apart from the substrate10in the third direction D3, and thus the first portion12_1of the substrate10may be electrically isolated from the first and second contacts32_1and32_2.

FIG.10shows an example configuration of elements of the first resistor structure RS1_5inFIG.3according to some embodiments of the present invention. Referring toFIG.10, lower surfaces of the first and second contacts32_1and32_2may be above an upper surface of the first lower semiconductor layer26L_1such that the first lower semiconductor layer26L_1may be electrically isolated from the first and second contacts32_1and32_2.

Each ofFIGS.11and12shows an example configuration of elements of the first resistor structure RS1_3inFIG.2according to some embodiments of the present invention. In some embodiments, the lower semiconductor layer26L_1may be formed to have a width in the first direction D1narrower than a width of the upper semiconductor layer26U_1in the first direction D1, and opposing sides, in the first direction D1, of the lower semiconductor layer26L_1may be spaced apart from the first and second contacts32_1and32_2as illustrated inFIG.11. Accordingly, the lower semiconductor layer26L_1may be electrically isolated from the first and second contacts32_1and32_2. In some embodiments, one of the opposing sides, in the first direction D1, of the lower semiconductor layer26L_1may contact the first contact32_1or the second contact32_2.

Referring toFIG.12, in some embodiments, the lower semiconductor layer26L_1may have a width in the first direction D1equal to a width of the upper semiconductor layer26U_1in the first direction D1, and each of the first and second contacts32_1and32_2may have a lower portion having a narrower width in the first direction D1compared to a width of its upper portion. Opposing sides, in the first direction D1, of the lower semiconductor layer26L_1may be spaced apart from the first and second contacts32_1and32_2as illustrated inFIG.12and may be electrically isolated from the first and second contact32_1and32_2. In some embodiments, only one of the first and second contacts32_1and32_2may have the narrower lower portion, and the lower semiconductor layer26L_1may contact the first contact32_1or the second contact32_2. In some embodiments, the upper semiconductor layer26U_1may not be used as a resistor element, as in the first resistor structure RS1_4inFIG.2, and at least one of the first and second contacts32_1and32_2may have an upper portion having a narrow width in the first direction D1compared to a width of its lower portion such that the upper semiconductor layer26U_1is spaced apart from the at least one of the first and second contacts32_1and32_2.

FIG.13is a plan view of a resistor structure according to some embodiments of the present invention. The resistor structure may include two resistor structures (i.e., a first resistor structure RS1and a second resistor structure RS2) that may be connected in series and may share a common resistor contact (e.g., a second contact32_2). Each of the first and second resistor structures RS1and RS2may have any configuration and structure described with reference toFIGS.1to12. For example, the first resistor structure RS1may be the first resistor structure RS1_7inFIG.3, and the second resistor structure RS2may be the first resistor structure RS1_2inFIG.2.

FIG.14is a schematic illustration of a resistor structure inFIG.13, andFIG.15is a side view of the resistor structure from a viewpoint V inFIG.13when each of the first and second resistor structures RS1and RS2has a configuration and structure of the first resistor structure RS1_1inFIG.1according to some embodiments of the present invention. The second resistor structure RS2may also include a first resistor element R1′ (e.g., a fifth upper semiconductor layer26U_5inFIG.15), a second resistor element R2′ (e.g., a fifth lower semiconductor layer26L_5inFIG.15) and a third resistor element R3′ (e.g., a second portion12_2of the substrate10inFIG.15), which are connected in parallel, as illustrated inFIG.14. The second resistor structure RS2may have any configuration and structure described with reference toFIGS.1to12.

In some embodiments, a resistor element (e.g., the first resistor element R1) of the first resistor structure RS1and a resistor element (e.g., the first resistor element R1′) of the second resistor structure RS2may be electrically connected in series through the second contact32_2.

Referring toFIGS.13to15, the second resistor structure RS2may include a fifth upper semiconductor layer26U_5, a sixth upper semiconductor layer26U_6, a fifth lower semiconductor layer26L_5, a sixth lower semiconductor layer26L_6, which may include a material and/or may have a shape and spatial relationship with other elements the same as or similar to the first upper semiconductor layer26U_1, the second upper semiconductor layer26U_2, the first lower semiconductor layer26L_1, the second lower semiconductor layer26L_2, respectively. The fifth upper semiconductor layer26U_5and the sixth upper semiconductor layer26U_6may have the first conductivity type, and the fifth lower semiconductor layer26L_5and the sixth lower semiconductor layer26L_6may have the second conductivity type.

The second resistor structure RS2may also include a second portion12_2of the substrate10. The second portion12_2of the substrate10may include impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic) and may have the first conductivity type or the second conductivity type. The second portion12_2of the substrate10may have an impurity concentration in a range of from 1011cm−3to 1015cm−3(e.g., from 1012cm−3to 1014cm−3).

A third upper thin semiconductor layer22U_3may be provided between the fifth upper semiconductor layer26U_5and the sixth upper semiconductor layer26U_6and may contact both the fifth upper semiconductor layer26U_5and the sixth upper semiconductor layer26U_6. A third lower thin semiconductor layer22L_3may be provided between the fifth lower semiconductor layer26L_5and the sixth lower semiconductor layer26L_6and may contact both the fifth lower semiconductor layer26L_5and the sixth lower semiconductor layer26L_6. The third upper thin semiconductor layer22U_3and the third lower thin semiconductor layer22L_3may include a material and/or may have a shape and spatial relationship with other elements the same as or similar to the first upper thin semiconductor layer22U_1and the first lower thin semiconductor layer22L_1, respectively.

The second resistor structure RS2may also include a ninth contact32_9(also referred to as a third resistor contact). In some embodiments, the ninth contact32_9may contact the fifth upper semiconductor layer26U_5, the fifth lower semiconductor layer26L_5, and the second portion12_2of the substrate10as illustrated inFIG.15. Additionally, the second resistor structure RS2may include a third metal layer24_3, conductive vias34_9and34_10, and conductive wires36as illustrated inFIGS.13and15.

FIG.16is a plan view of an integrated circuit device according to some embodiments of the present invention, andFIGS.17to19are cross-sectional views of the integrated circuit device taken along the line D-D′ inFIG.16according to some embodiments of the present invention. The integrated circuit devices illustrated inFIGS.16-19are the same as or similar to the integrated circuit devices illustrated inFIGS.4-8with primary differences being that a first contact32_1and a second contact32_2′ of a third resistor structure RS3are on opposing sides of the first metal layer24_1, respectively, and the first upper thin semiconductor layer22U_1′ and the first lower thin semiconductor layer22L_1′ of the third resistor structure RS3include impurities for electrical connection between the first contact32_1and the second contact32_2′ through the first upper thin semiconductor layer22U_1′ and the first lower thin semiconductor layer22L_1′.

The third resistor structure RS3may also include three resistor elements, a first resistor element R1, a second resistor element R2, and a third resistor element R3, which can be connected in various ways as illustrated inFIGS.1and3. The first resistor element R1of the third resistor structure RS3may include a first upper semiconductor layer26U_1, a second upper semiconductor layer26U_2and a first upper thin semiconductor layer22U_1′ that contacts the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2. The first upper thin semiconductor layer22U_1′ may include impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic) to have the same conductivity type as the first upper semiconductor layer26U_1and the second upper semiconductor layer26U_2.

The second resistor element R2of the third resistor structure RS3may include a first lower semiconductor layer26L_1, a second lower semiconductor layer26L_2and a first lower thin semiconductor layer22L_1′ that contacts the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2. The first lower thin semiconductor layer22L_1′ may include impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic) to have the same conductivity type as the first lower semiconductor layer26L_1and the second lower semiconductor layer26L_2.

For example, each of the first upper thin semiconductor layer22U_1′ and the first lower thin semiconductor layer22L_1′ may be a silicon layer or a silicon germanium layer and may have an impurity concentration in a range of from 1015cm−3to 1020cm−3(e.g., about from 1016cm−3to 1019cm−3or about from 1017cm−3to 1018cm−3).

The third resistor element R3of the third resistor structure RS3may include a third portion12_3of the substrate10. The third portion12_3of the substrate10may include impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic) and may have the first conductivity type or the second conductivity type. The third portion12_3of the substrate10may have an impurity concentration in a range of from 1011cm−3to 1015cm−3(e.g., from 1012cm−3to 1014cm−3).

The first, second and third resistor elements R1, R2and R3of the third resistor structure RS3may be connected to the first contact32_1and the second contact32_2′ in various ways as illustrated inFIGS.1and3to make the third resistor structure RS3have a pre-determined resistance value.

As examples,FIGS.17to19show cross-sectional views of the third resistor structures RS3that have electrical connections the same as the first resistor structures RS1_1inFIG.1, RS1_2inFIG.2and RS1_5inFIG.3, respectively.

In some embodiments, the first, second and third resistor elements R1, R2and R3of the third resistor structure RS3all may contact the first contact32_1and the second contact32_2′ and may be electrically connected in parallel as illustrated inFIG.17. In some embodiments, only two resistor elements (e.g., the first and second resistor elements R1, R2, the first and third resistor elements R1, R3or the second and third resistor elements R2, R3) among the three resistor elements R1, R2and R3may contact the first contact32_1and the second contact32_2′ and may be electrically connected in parallel. For example, the first and second resistor elements R1, R2may contact the first contact32_1and the second contact32_2′, and the third resistor element R3may not contact the first contact32_1and the second contact32_2′ as illustrated inFIG.18. In some embodiments, only single resistor element (e.g., the first resistor element R1, the second resistor element R2, or the third resistor element R3) among the three resistor elements R1, R2and R3may contact and may be electrically connected to the first contact32_1and the second contact32_2′. For example, the first resistor element R1may contact the first contact32_1and the second contact32_2′, and the second and third resistor elements R2, R3may not contact the first contact32_1and the second contact32_2′ as illustrated inFIG.19.

FIG.20is a flow chart of methods of forming an integrated circuit device according to some embodiments of the present invention.FIGS.21-23are cross-sectional views taken along the line B-B′ and the line C-C′ inFIG.4illustrating methods of forming an integrated circuit device according to some embodiments of the present invention.

Referring toFIGS.20and21, the methods may include forming a doped portion (e.g., the first portion12_1of the substrate10inFIG.5) in a substrate10(Block1000) by adding impurities (e.g., boron, aluminum, gallium, indium, phosphorus, and/or arsenic) to the substrate10. For example, an ion implantation process and/or a diffusion process may be used to form the doped portion. The methods may also include forming a lower thin semiconductor layer22L_1(also referred to as a first lower thin semiconductor layer) and a lower active layer22L_2(also referred to as a second lower thin semiconductor layer) on the substrate10(Block1100).

In some embodiments, each of the lower thin semiconductor layer22L_1and the lower active layer22L_2may include multiple layers (e.g., two layers as illustrated inFIG.21) stacked in the third direction D3. In some embodiments, one of the lower thin semiconductor layers22L_1and one of the lower active layers22L_2may be formed concurrently at the same height from the first surface S1of the substrate10as illustrated inFIG.21. For example, preliminary lower semiconductor layers may be formed on the substrate10and then the preliminary lower semiconductor layers may be patterned, thereby forming the lower thin semiconductor layers22L_1and the lower active layers22L_2. One of the lower thin semiconductor layers22L_1and one of the lower active layers22L_2, which have lower surfaces coplanar with each other, may be respective portions of a single preliminary lower semiconductor layer. First interlayer insulating layers42_1may be formed to be stacked alternately with the lower thin semiconductor layers22L_1and the lower active layers22L_2and may expose opposing side surfaces of the lower thin semiconductor layers22L_1and the lower active layers22L_2.

An upper thin semiconductor layer22U_1(also referred to as a first upper thin semiconductor layer) and an upper active layer22U_2(also referred to as a second upper thin semiconductor layer) may be formed on the lower thin semiconductor layer22L_1and the lower active layer22L_2, respectively (Block1200). In some embodiments, each of the upper thin semiconductor layer22U_1and the upper active layer22U_2may include multiple layers (e.g., two layers as illustrated inFIG.21) stacked in the third direction D3. In some embodiments, one of the upper thin semiconductor layers22U_1and one of the upper active layers22U_2may be formed concurrently at the same height from the first surface S1of the substrate10as illustrated inFIG.21. For example, preliminary upper semiconductor layers may be formed on the substrate10and then the preliminary upper semiconductor layers may be patterned, thereby forming the upper thin semiconductor layers22U_1and the upper active layers22U_2. One of the upper thin semiconductor layers22U_1and one of the upper active layers22U_2, which have lower surfaces coplanar with each other, may be respective portions of a single preliminary upper semiconductor layer. Second interlayer insulating layer42_2may be formed to be stacked alternately with the upper thin semiconductor layer22U_1and the upper active layer22U_2and may expose opposing side surfaces of the upper thin semiconductor layer22U_1and the upper active layer22U_2.

Referring toFIGS.18and22, lower semiconductor layers26L_1and26L_2(also referred to as first and second lower semiconductor layers) and lower source/drain regions26L_3and26L_4(also referred to as third and fourth lower semiconductor layers) may be formed (Block1300). In some embodiments, the first and second lower semiconductor layers26L_1and26L_2may be formed by an epitaxial growth process using the lower thin semiconductor layer22L_1as a seed layer, and the lower source/drain regions26L_3and26L_4may be formed by an epitaxial growth process using the lower active layer22L_2as a seed layer. In some embodiments, the first and second lower semiconductor layers26L_1and26L_2and the lower source/drain regions26L_3and26L_4may be formed by a single epitaxial growth process (e.g., a first epitaxial growth process).

Opposing side surfaces of the lower thin semiconductor layer22L_1may contact the first and second lower semiconductor layers26L_1and26L_2, respectively, and opposing side surfaces of the lower active layer22L_2may contact the lower source/drain regions26L_3and26L_4, respectively, as illustrated inFIG.22.

AlthoughFIG.22illustrates that the first and second lower semiconductor layers26L_1and26L_2and the lower source/drain regions26L_3and26L_4are formed after the upper thin semiconductor layers22U_1and the upper active layers22U_2are formed, in some embodiments, the lower source/drain regions26L_3and26L_4may be formed before the upper thin semiconductor layers22U_1and the upper active layers22U_2are formed.

Referring toFIGS.18and23, upper semiconductor layers26U_1and26U_2(also referred to as first and second upper semiconductor layers) and upper source/drain regions26U_3and26U_4(also referred to as third and fourth upper semiconductor layers) may be formed (Block1400). In some embodiments, the upper semiconductor layers26U_1and26U_2may be formed by an epitaxial growth process using the upper thin semiconductor layer22U_1as a seed layer, and the upper source/drain regions26U_3and26U_4may be formed by an epitaxial growth process using the upper active layer22U_2as a seed layer. In some embodiments, the upper semiconductor layers26U_1and26U_2and the upper source/drain regions26U_3and26U_4may be formed by a single epitaxial growth process (e.g., a second epitaxial growth process).

Referring toFIGS.4to6,16and18, the methods may include forming resistor contacts (e.g., the first and second contact32_1and32_2) and source/drain contacts (e.g., fifth, seventh and eight contacts32_5,32_7and32_8) (Block1500) and forming a first metal layer24_1and a second metal layer24_2(Block1600). In some embodiments, portions of the first and second interlayer insulating layers42_1and42_2may be replaced with the first metal layer24_1and the second metal layer24_2. In some embodiments, the resistor contacts and the source/drain contacts may be formed concurrently. For example, the resistor contacts and the source/drain contacts may include the same metal layer formed by the same deposition process. In some embodiments, the resistor contacts and the source/drain contacts may have upper surfaces coplanar with each other.

In some embodiments, the first metal layer24_1and the second metal layer24_2may be formed concurrently. For example, first metal layer24_1and the second metal layer24_2may include the same metal layer formed by the same deposition process.

It should also be noted that in some alternate implementations, the functions/acts noted in flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present inventive concepts.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the scope of the present invention. Accordingly, the present invention should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing, unless the context clearly indicates otherwise.