Sampling circuits

A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a sampling circuit, and more particularly to a sampling circuit with offset cancellation and low-frequency noise cancellation.

2. Description of the Related Art

Generally, a sampling circuit with an operational amplifier (opamp) has a problem of opamp offset. In order to eliminate opamp offset in a sampling circuit, the operational amplifier is generally placed in a unit-gain feedback loop. However, the unit-gain feedback loop restricts the input common mode voltage and the output common mode voltage of the operational amplifier to be equal, which limits the type of operational amplifiers used in the sampling circuit. Moreover, because the gain of the sampling circuit is limited to be “1”, the gain cannot be adjusted according to system requirements.

Thus, it is desired to provide a sampling circuit with an operational amplifier, which has opamp offset cancellation functionality and adjustable gain and can operate under different input and output common mode voltages.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a sampling circuit operating in a sampling phase and a holding phase comprises an amplifier, a first switch, a first capacitor, a second capacitor, and a voltage source. The amplifier has a first input terminal and an output terminal for outputting an output signal. The first switch has a first terminal receiving an input signal and a second terminal coupled to a first node and turned on during the sampling phase. The first capacitor is coupled between the first node and the first input terminal and samples an input signal during the sampling phase. The second capacitor is coupled to the first input terminal. The second capacitor samples a reference signal during the sampling phase and receives charges from the first capacitor during the holding phase. The voltage source is coupled between the first input terminal and the output terminal. The voltage source shifts the output signal by a predetermined level during the sampling phase to eliminate difference between an input common mode voltage and an output common mode voltage of the amplifier.

Another exemplary embodiment of sampling circuit operating in a first phase and a second phase following the first phase comprises an amplifier, a first capacitor, a second capacitor, and a voltage source. The amplifier has a first input terminal and an output terminal for outputting an output signal. The first capacitor is coupled to the first input terminal and receives an input signal during the first phase and the second phase. The second capacitor is coupled to the first input terminal. The second capacitor samples a reference signal during the first phase and receives charges from the first capacitor during the second phase. The voltage source is coupled between the first input terminal and the output terminal. The voltage source shifts the output signal by a predetermined level during the first phase to eliminate difference between an input common mode voltage and an output common mode voltage of the amplifier.

DETAILED DESCRIPTION OF THE INVENTION

Sampling circuits are provided. In an exemplary embodiment shown inFIG. 1a, a sampling circuit operates in a sampling phase and a hold phase and may act as a sample-and-hold circuit. Referring toFIG. 1a, the sampling circuit comprises an amplifier10, a sampling capacitor Cs10, a feedback capacitor Cf10, switches11-14, and a voltage source15. The amplifier10comprises a positive input terminal (+) coupled to a voltage source providing a voltage level equal to an input common mode voltage Vcmi of the amplifier10, a negative input terminal (−), and an output terminal (OUT). The switch11has a first terminal receiving an input signal Vin and a second terminal coupled to a node N0. The sampling capacitor Cs10is coupled between the node N10and the negative input terminal (−) of the amplifier10. The switch12has a first terminal receiving a reference signal Vref and a second terminal coupled to a node N11. The feedback capacitor Cf10is coupled between the negative input terminal1(−) of the amplifier10and the node N11. The switch13has a first terminal coupled to the node N10and a second terminal receiving a voltage level arranged to be equal to an output common mode voltage Vcmo of the amplifier10. The switch14has a first terminal coupled to the node N11and a second terminal coupled to the output terminal (OUT) of the amplifier10. The ON/OFF states of the switches11and12are determined according to a clock signal Ps corresponding to the sampling phase, while the ON/OFF states of the switches13and14are determined according to a clock signal Ph corresponding to the hold phase, as shown inFIG. 2.

Referring toFIG. 1a, the voltage source15provides a voltage level substantially equal to the voltage difference between the input common mode voltage Vcmi and the output common mode voltage Vcmo of the amplifier10. In one embodiment, the voltage source15can be implemented by a level shifter. This level shifter comprises switches150-153and a capacitor C15, as shown inFIG. 1b. The switch150has a first terminal coupled to the negative input terminal (−) of the amplifier10and a second terminal coupled to a node N12. The switch151has a first terminal coupled to the output terminal (OUT) of the amplifier10and a second terminal coupled to a node N13. The switch152is coupled between a voltage source providing a voltage level substantially equal to the input common mode voltage Vcmi and the node N12. The switch153is coupled between a voltage source providing a voltage level substantially equal to the output common mode voltage Vcmo and the node N13. The capacitor C15is coupled between the nodes N12and N13. The ON/OFF states of the switches150and151are determined according to the clock signal Ps, while the ON/OFF states of the switches152and153are determined according to the clock signal Ph. Referring toFIG. 2, when the clock signal Ph is asserted and the clock signal Ps is de-asserted (that is, during the holding phase), the switches152and153respectively couple the voltage sources to the terminals of the capacitor C15, the switches150and151decouple the capacitor C15from the amplifier10, and thereby the voltage drop of the capacitor C15is the voltage difference between the input common mode voltage Vcmi and the output common mode voltage Vcmo of the amplifier10. In some embodiments, if the input common mode voltage and output common mode voltage of the amplifier10are equal, the voltage drop of the capacitor C15is substantially equal to zero.

Referring toFIGS. 1band2, during a following sampling phase, the clock signal Ph is de-asserted and the clock signal Ps is asserted to control the switch11to transmit the input signal Vin to the sampling capacitor Cs10, control the switch12to transmit the reference signal Vref to the feedback capacitor Cf10, and control the switches150and151to couple the capacitor C15to the amplifier10. The sampling capacitor Cs10samples the input signal Vin, and the feedback capacitor Cf10samples the reference signal Vref. Since the difference between the input common mode voltage Vcmi and output common mode voltage Vcmo of the amplifier10has been stored into the capacitor C15during the previous holding phase, the level of the output signal Vout is first shifted by the voltage difference during this sampling phase.

During a following holding phase, the clock signal Ps is de-asserted and the clock signal Ph is asserted again. Since the output common mode voltage Vcmo is provided to the node N10through the switch13, the charges of the sampling capacitor Cs10is pushed to the feedback capacitor Cf10, and the charges of the feedback capacitor Cf10is also pushed to the output terminal (OUT) of the amplifier10, so that a gain substantially equal to Cf10/Cs10is obtained at the output signal Vout.

According to the above operations, by providing a voltage level substantially equal to (Vcmi-Vcmo) between the input terminal (−) and the output terminal OUT of the amplifier10during the sampling phase, the amplifier10is not necessarily placed in a unit-gain feedback loop to sample the offset of the amplifier10. Thus, the capacitance of the sampling capacitor Cs10and the capacitance of the feedback capacitor Cf10are not required to be equal, which results in an adjustable gain coefficient, and the amplifier10can be implemented by an amplifier with different or equal input and output common mode voltages, such as a telescopic amplifier with low power consumption and less noise.

Moreover, since one plate of the sampling capacitor Cs10and one plate of the feedback capacitor Cf10are coupled to the negative input terminal (−) of the amplifier10, the offset of the amplifier10and low-frequency noise can be cancelled during the holding phase.

FIG. 3ashows another exemplary embodiment of a sampling circuit. Referring toFIG. 3a, a sampling circuit alternately operates in a data phase and a reset phase and comprises an amplifier30, a sampling capacitor Cs30, a feedback capacitor Cf30, switches31-32, and a voltage source33. The amplifier30comprises a positive input terminal (+) receiving a voltage level substantially equal to the input common mode voltage Vcmi of the amplifier30, a negative input terminal (−), and an output terminal (OUT). The sampling capacitor Cs30has one plate receiving the input signal Vin and the other plate coupled to the negative input terminal (−) of the amplifier30. The switch31has a first terminal receiving a reference signal Vref and a second terminal coupled to a node N30. The feedback capacitor Cf30is coupled between the negative input terminal I (−) of the amplifier30and the node N30. The switch32has a first terminal coupled to the node N30and a second terminal coupled to the output terminal (OUT) of the amplifier30. The ON/OFF states of the switch31is determined according to a clock signal Ps corresponding to the reset phase, while the ON/OFF states of the switch32is determined according to a clock signal Ph corresponding to the data phase, as shown inFIG. 4.

Referring toFIG. 3a, the voltage source33provides a voltage level substantially equal to the difference between the input common mode voltage Vcmi and an output common mode voltage Vcmo of the amplifier30. In one embodiment, the voltage source33can be implemented by a level shifter. This level shifter comprises switches330-333and a capacitor C33, as shown inFIG. 3b. The switch330has a first terminal coupled to the negative input terminal (−) of the amplifier30and a second terminal coupled to a node N31. The switch331has a first terminal coupled to the output terminal (OUT) of the amplifier10and a second terminal coupled to a node N32. The switch332is coupled between a voltage source providing a voltage level substantially equal to the input common mode voltage Vcmi and the node N31. The switch333is coupled between a voltage source providing a voltage level substantially equal to the output common mode voltage Vcmo and the node N32. The capacitor C33is coupled between the nodes N31and N32. The ON/OFF states of the switches330and331are determined according to the clock signal Ps, while the ON/OFF states of the switches332and333are determined according to the clock signal Ph. When the clock signal Ph is asserted and the clock signal Ps is de-asserted (that is, during the data phase), the voltage drop of the capacitor Cf33is the difference between the input common mode voltage Vcmi and the output common mode voltage Vcmo of the amplifier10. In some embodiments, if the input common mode voltage and output common mode voltage of the amplifier10are equal, the voltage difference stored in the capacitor Cf33is substantially equal to zero.

In one embodiment, the sampling circuit is utilized as a correlated double sampling circuit for pixel sampling, and the input signal Vin is a charge-coupled device (CCD) signal provided from an image sensor, such as a digital camera or a scanner. As shown inFIG. 4, a CCD signal is a stream of pixels from a charge-coupled device, and each pixel comprises a reset level Lreset and a data level Ldata. A CCD signal may introduce an error which exists from one pixel to another due to different reset level Lreset of the pixels (the error is referred to as reset error). Thus, to remove the reset error, the reset level Lreset and the data level Ldata of each pixel need to be sampled to obtain the difference between the reset level Lreset and the data level Ldata.

Referring toFIGS. 3band4, during a following reset phase, the clock signal Ps is asserted and the clock signal Ph is de-asserted. The reference signal is therefore inputted to the feedback capacitor Cf30, and a voltage level equal to (Vcmi-Vcmo) is provided between the negative input terminal (−) and the output to shift the output signal Vout by the voltage difference. The sampling capacitor Cs30samples the reset level of the input signal Vin, and the feedback capacitor Cf30samples the reference signal Vref.

During a following data phase, the clock signal Ps is de-asserted to control the switches31,330, and331to decouple the reference signal Vref from the node N30and decouple the capacitor Cf33from the nodes N31and N32, and the clock signal Ph is asserted to control the switches32,332, and333to couple the node N30to the output terminal OUT of the amplifier and couple the capacitor Cf33to the voltage sources. The voltage applied to the sampling capacitor Cs30is changed by (Lreset-Ldata). The feedback capacitor Cf30receives the charges from the sampling capacitor Cs30and then pushes the charges to the output terminal (OUT). Thus, the voltage level of the output signal Vout is changed according to the difference (Lreset-Ldata).

According to the foregoing description of the structure and operation of inventive embodiments, the sampling circuit acts as a correlated double sampling circuit for a CCD signal. The amplifier30of the correlated double sampling circuit is not necessarily placed in a unit-gain feedback to sample the offset of the amplifier30. The input common mode voltage and output common mode voltage of the amplifier30are not required to be equal, and the amplifier30can be implemented by an amplifier with different or equal input and output common mode voltages, such as a telescopic amplifier with low power consumption and less noise.

Moreover, since one plate of the sampling capacitor Cs30and one plate of the feedback capacitor Cf30are coupled to the negative input terminal (−) of the amplifier30, the offset of the amplifier30and the low-frequency noise can be cancelled during the holding phase.

In the embodiment, the capacitance of the sampling capacitor Cs30can be equal to or different from the capacitance of the feedback capacitor Cf30, therefore the gain of the sampling circuit can be adjusted according to system requirements.

For illustrative clarity, the sampling circuits ofFIG. 1a,FIG. 1b,FIG. 3a, andFIG. 3bare shown as single-ended structures. However, as a person with ordinary skill in the art would readily appreciate, the above-mentioned sampling circuits can be implemented with differential structures as well. Further descriptions of the differential structures are omitted here for the sake of brevity. These modifications still fall within the scope of the present invention.