Semiconductor package including stacked semiconductor chips

A semiconductor package may include: a first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; and first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction, wherein each of the other first semiconductor chips, except at least the uppermost first semiconductor chip from among the plurality of first semiconductor chips includes: an active surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to an other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad, and disposed at an edge of the active surface, which is close to one side surface in the second direction, wherein the plurality of first semiconductor chips are stacked with an offset toward one side in a third direction crossing the first and second directions, the one side being away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pads and the first redistribution pads, wherein the first vertical interconnectors electrically coupled to the first semiconductor chips have one ends connected to the first one-side chip pads and the first redistribution pads, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0110687 filed on Sep. 6, 2019, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

The present disclosure generally relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked therein.

2. Related Art

Electronic products are required to process a larger amount of data while having a smaller volume. Thus, it is necessary to increase the degree of integration of a semiconductor device used in such electronic products.

However, due to the limitations of the semiconductor integration technology, required functions cannot be satisfied by only a single semiconductor chip. Thus, a semiconductor package having a plurality of semiconductor chips embedded therein is fabricated.

Although a semiconductor package includes a plurality of semiconductor chips, the semiconductor package is required to have a designated size or a size smaller than the designated size, according to the requirements of an application in which the semiconductor package is to be mounted.

SUMMARY

In an embodiment, a semiconductor package may include: a first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; and first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction, wherein each of the other first semiconductor chips, except at least the uppermost first semiconductor chip from among the plurality of first semiconductor chips includes: an active surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to an other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad, and disposed at an edge of the active surface, which is close to one side surface in the second direction, wherein the plurality of first semiconductor chips are stacked with an offset toward one side in a third direction crossing the first and second directions, the one side being away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pads and the first redistribution pads, wherein the first vertical interconnectors electrically coupled to the first semiconductor chips have one ends connected to the first one-side chip pads and the first redistribution pads, respectively.

In an embodiment, a semiconductor package may include: a first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction; a second chip stack disposed on the first chip stack, and including a plurality of second semiconductor chips stacked in the vertical direction, the second semiconductor chips including other second semiconductor chips and an uppermost second semiconductor chip; and second vertical interconnectors electrically coupled to the plurality of second semiconductor chips, respectively, and extended in the vertical direction. Each of the first semiconductor chips may include: an active surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; an first other-side chip pad disposed at an edge of the active surface, which is close to the other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad and disposed at an edge of the active surface, which is close to one side surface between the two side surfaces in the second direction. The plurality of first semiconductor chips may be stacked with an offset toward one side in a third direction crossing the first and second directions, the one side being spaced away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pad and the first redistribution pad. Each of the first vertical interconnectors may have one end connected to the first one-side chip pad and the first redistribution pad. The other second semiconductor chips except at least the uppermost second semiconductor chip among the plurality of second semiconductor chips may be disposed in the same state as the state in which the first semiconductor chips are but rotated by 180 degrees about one axis parallel to the vertical direction, and each include a second one-side chip pad, a second other-side chip pad and a second redistribution pad which are located at the opposite positions of the positions of the first one-side chip pad, the first other-side chip pad and the first redistribution pad. The plurality of second semiconductor chips may be stacked with an offset in the opposite direction of the offset stacking direction of the plurality of first semiconductor chips, in order to expose the second one-side chip pads and the second redistribution pads of the other second semiconductor chips. Each of the second vertical interconnectors electrically coupled to the other second semiconductor chips may have one end connected to the second one-side chip pad and the second redistribution pad.

In an embodiment, a method of fabricating a semiconductor package may include: forming a first chip stack on a carrier substrate, the first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; and forming first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction. Each of the other first semiconductor chips except at least the uppermost first semiconductor chip from among the plurality of first semiconductor chips may include: an active surface defined by two side surfaces thereof in a first direction and two side surfaces thereof in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to the other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad, and disposed at an edge of the active surface, which is close to one side surface between the two side surfaces in the second direction. The forming of the first chip stack may include stacking the first semiconductor chips with an offset toward one side in a third direction crossing the first and second directions, the one side being spaced away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pad and the first redistribution pad.

In an embodiment, a method of fabricating a semiconductor package may include: forming a first chip stack on a carrier substrate, the first chip stack including a plurality of first semiconductor chips stacked in a vertical direction; forming a second chip stack on the first chip stack, the second chip stack including a plurality of second semiconductor chips stacked in the vertical direction, the second semiconductor chips including other second semiconductor chips and an uppermost second semiconductor chip; and forming first vertical interconnectors electrically coupled to the plurality of first semiconductor chips, respectively, and extended in the vertical direction and second vertical interconnectors electrically coupled to the plurality of second semiconductor chips, respectively, and extended in the vertical direction. Each of the first semiconductor chips may include: an active surface defined by two side surfaces thereof in a first direction and two side surfaces thereof in a second direction crossing the first direction; a first one-side chip pad disposed at an edge of the active surface, which is close to one side surface in the first direction; a first other-side chip pad disposed at an edge of the active surface, which is close to the other side surface in the first direction; and a first redistribution pad electrically coupled to the first other-side chip pad and disposed at an edge of the active surface, which is close to one side surface between the two side surfaces in the second direction. The other second semiconductor chips except at least the uppermost second semiconductor chip among the plurality of second semiconductor chips may be disposed in the same state as the state in which the first semiconductor chips are but rotated by 180 degrees about one axis parallel to the vertical direction, and each include a second one-side chip pad, a second other-side chip pad and a second redistribution pad which are located at the opposite positions of the positions of the first one-side chip pad, the first other-side chip pad and the first redistribution pad. The forming of the first chip stack may include stacking the first semiconductor chips with an offset toward one side in a third direction crossing the first and second directions, the one side being spaced away from the one side surface in the first direction and the one side surface in the second direction, in order to expose the first one-side chip pad and the first redistribution pad. The forming of the second chip stack may include stacking the second semiconductor chips with an offset in the opposite direction of the offset-stacking direction of the plurality of second semiconductor chips, in order to expose the second one-side chip pads and the second redistribution pads of the other second semiconductor chips.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below with reference to the accompanying drawings.

Various embodiments are directed to a semiconductor package which has a small thickness and can satisfy high-performance and high-capacity requirements through a method for stacking a plurality of semiconductor chips each having chip pads disposed at both edges thereof.

Before a semiconductor package and a method for fabricating the same in accordance with an embodiment are described, a semiconductor chip included in the semiconductor package in accordance with a present embodiment will be described with reference toFIGS. 1A and 1B.

FIG. 1Ais a plan view illustrating an active surface of a semiconductor chip in accordance with an embodiment, andFIG. 1Bis a cross-sectional view taken along a line A1-A1′ ofFIG. 1A.

Referring toFIGS. 1A and 1B, the semiconductor chip100in accordance with an embodiment may include an active surface101having chip pads110disposed thereon, an inactive surface102located on the opposite side of the active surface101, and side surfaces103,104,105, and106connecting the active surface101and the inactive surface102.

Since the semiconductor chip100has a rectangular plan shape or a similar shape thereto, the semiconductor chip100may include the four side surfaces103to106. Among the side surfaces103to106, the side surfaces103and105facing each other in a first direction parallel to the active surface101and/or the inactive surface102of the semiconductor chip100will be referred to as a first side surface103and a third side surface105, and the side surfaces104and106facing each other in a second direction which crosses the first direction while being parallel to the active surface101and/or the inactive surface102of the semiconductor chip100will be referred to as a second side surface104and a fourth side surface106. In an embodiment, the first and third side surfaces103and105may have a smaller length than the second and fourth side surfaces104and106. However, the present embodiments are not limited thereto, and the lengths of the side surfaces may be set to various values.

The chip pads110may be disposed at both edge areas of the active surface101in the first direction, i.e. the edge area adjacent to the first side surface103and the edge area adjacent to the third side surface105. That is, the chip pads110may be disposed in an edge-pad type. Among the chip pads110, the chip pads110disposed at the edge area close to the first side surface103will be referred to as one-side chip pads110A, and the chip pads110disposed at the edge area close to the third side surface105will be referred to as other-side chip pads110B. In an embodiment, the one-side chip pads110A may be arranged in a line along the second direction, and the other-side chip pads110B may also be arranged in a line along the second direction. However, the present embodiments are not limited thereto, and the one-side chip pads110A and/or the other-side chip pads110B may be arranged in various manners at both edge areas in the first direction. In an embodiment, the number of the one-side chip pads110A may be larger than the number of the other-side chip pads110B. However, the present embodiments are not limited thereto, and the number of the one-side chip pads110A and the number of the other-side chip pads110B may be set to various values. In an embodiment, the chip pads110may have a rectangular plan shape. However, the present embodiments are not limited thereto, and the plan shape of the chip pads110may be modified in various manners.

When such semiconductor chips100are stacked in a vertical direction, it is difficult to expose the one-side chip pads110A and the other-side chip pads110B at the same time, even though the semiconductor chips100are stacked through any methods. This will be described below. In order to solve such a problem, the semiconductor chip100may further include a chip redistribution layer120formed on the active surface101.

The chip redistribution layer120may include redistribution dielectric layers121and125and a redistribution conductive layer123.

For example, the redistribution conductive layer123may include redistribution pads123A and redistribution lines123B which are located on a plane illustrated inFIG. 1A. The redistribution pads123A may be disposed at an edge area close to the fourth side surface106between both edge areas in the second direction, and the redistribution lines123B may be extended from the redistribution pads123A to the other-side chip pads110B. In an embodiment, the redistribution pads123A may be arranged in a line along the first direction while the number of the redistribution pads123A is set to the same value as the number of the other-side chip pads110B such that the redistribution pads123A one-to-one correspond to the other-side chip pads110B. However, the present embodiments are not limited thereto, but the number and arrangement of the redistribution pads123A may be modified in various manners. In an embodiment, the redistribution pads123A may be disposed at the edge area close to the fourth side surface106. However, the present embodiments are not limited thereto, but the redistribution pads123A may be disposed at the edge area close to the second side surface104. The edge area where the redistribution pads123A are disposed, between both edge areas in the second direction, may be decided according to an offset stacking direction of the semiconductor chip100which will be described below. In an embodiment, the redistribution pads123A may be electrically coupled to the other-side chip pads110B. However, the present embodiments are not limited thereto, but the redistribution pads123A may be electrically coupled to the one-side chip pads110A. The chip pads to which the redistribution pads123A are connected, between the one-side chip pads110A and the other-side chip pads110B, may be decided according to the offset stacking direction of the semiconductor chip100which will be described below. When the redistribution pads123A are electrically coupled to the other-side chip pads110B, the redistribution pads123A may be disposed relatively close to the third side surface105in the first direction as illustrated inFIG. 1A, which makes it possible to shorten connection paths to the other-side chip pads110B. On the other hand, when the redistribution pads123A are connected to the one-side chip pads110A, the redistribution pads123A may be disposed relatively close to the first side surface103in the first direction in the opposite way of the illustrated structure. When the redistribution pads123A are connected to the other-side chip pads110B fewer than the one-side chip pads110A, a routing path through the chip redistribution layer120and a package redistribution layer600(seeFIG. 7) to be described below can be relatively simplified. In an embodiment, the redistribution pads123A may have the same or similar rectangular plan shape as or to the chip pads110. For convenience of description, the redistribution pads123A are represented by thicker solid lines than the chip pads110. However, the present embodiments are not limited thereto, and the plan shape of the redistribution pads123A may be modified in various manners. The redistribution lines123B may be formed not to cross each other. For this structure, the redistribution pads123A and the other-side chip pads110B may be respectively connected to each other in ascending order of distance therebetween.

Referring to the cross-section illustrated inFIG. 1B, the redistribution conductive layer123may be covered by the redistribution dielectric layers121and125, except portions exposed through openings of the redistribution dielectric layers121and125, and thus electrically isolated from other components. The first redistribution dielectric layer121covering the active surface101of the semiconductor chip100may have openings that expose the chip pads110. The redistribution lines123B may fill the openings of the first redistribution dielectric layer121to be electrically coupled to the chip pads110, and extended over the first redistribution dielectric layer121. The redistribution line123B may be extended in a line shape with a small width, and have an end with a relatively large width. The second redistribution dielectric layer125may have an opening to expose the ends of the redistribution lines123B, while covering the redistribution lines123B and the first redistribution dielectric layer121. Portions of the ends of the redistribution lines123B, exposed through the openings formed in the second redistribution dielectric layer125, may constitute the redistribution pads123A.

The semiconductor chip100in accordance with an embodiment may include a mobile dynamic random access memory (DRAM). However, the present embodiments are not limited thereto, but the semiconductor chip100may include a nonvolatile memory such as a flash memory, a phase change RAM (PRAM) or a magneto-resistive RAM (MRAM) or a volatile memory such as a DRAM or a static RAM (SRAM).

The above-described plurality of semiconductor chips100may be stacked in a vertical direction to form a semiconductor package. This structure will be described with reference toFIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6 and 7.

FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6 and 7are diagrams for describing a semiconductor package and a method for fabricating the same in accordance with an embodiment. For example,FIGS. 2A, 3A, 4A, and 5Aare plan views when the semiconductor package is seen in the direction of the active surface.FIGS. 2B, 3B, 4B, and 5Bare cross-sectional views corresponding toFIGS. 2A, 3A, 4A, and 5A, respectively. In particular,FIGS. 2B, 3B, 4B, and 5Bare cross-sectional views taken along lines A2-A2′ ofFIGS. 2A, 3A, 4A, and 5A, respectively.FIGS. 6 and 7are cross-sectional views for describing subsequent processes of a process which is described with reference toFIGS. 5A and 5B. The descriptions of substantially the same components as those described with reference toFIGS. 1A and 1Bwill be omitted herein.

First, the fabrication method will be described.

Referring toFIGS. 2A and 2B, a carrier substrate200may be provided. The carrier substrate200may be a glass carrier substrate, a silicon carrier substrate, a ceramic carrier substrate or the like. Alternatively, the carrier substrate200may be a wafer, and a plurality of packages may be simultaneously formed on the carrier substrate200.

Then, a first chip stack300may be formed on a first surface201of the carrier substrate200. The first chip stack300may include a plurality of first semiconductor chips300-1to300-4stacked in a direction perpendicular to the first surface201of the carrier substrate200. In an embodiment, the first chip stack300may include four first semiconductor chips300-1to300-4. However, the present embodiments are not limited thereto, but the number of semiconductor chips included in the first chip stack300may be set to various values such as, but not limited to, 2 and 8. For convenience of description, the four first semiconductor chips are sequentially represented by reference numerals300-1to300-4in ascending order of distance from the carrier substrate200.

Each of the first semiconductor chips300-1to300-4may have substantially the same structure as the semiconductor chip100described with reference toFIGS. 1A and 1B. Thus, each of the first semiconductor chips300-1to300-4may include chip pads310, an active surface301on which a redistribution conductive layer323including redistribution pads323A and redistribution lines323B is disposed, an inactive surface302positioned in the opposite side of the active surface301, and first to fourth side surfaces303,304,305, and306connecting the active surface301and the inactive surface302. For reference,FIG. 2Bis a cross-sectional view taken along the line A2-A2′ ofFIG. 2A, and the chip pads310might not be seen on this cross-sectional view. For convenience of description, illustration of the redistribution lines323B and the redistribution dielectric layer is omitted from the cross-sectional view ofFIG. 2B. However, each of the first semiconductor chips300-1to300-4may include the same redistribution layer as the chip redistribution layer120described with reference to the cross-sectional view ofFIG. 1B. The first semiconductor chips300-1to300-4may be the same memory chips, for example, mobile DRAM chips.

The plurality of first semiconductor chips300-1to300-4may be stacked on the carrier substrate200in such a manner that the inactive surface302faces the carrier substrate200and the active surface301is located on the opposite side of the inactive surface302. That is, the plurality of first semiconductor chips300-1to300-4may be stacked in a face-up manner. The inactive surface302of each of the first semiconductor chips300-1to300-4may have an adhesive layer330formed thereon. Through the adhesive layer330, each of the first semiconductor chips300-1to300-4may be attached to the first semiconductor chip located immediately thereunder or the first surface201of the carrier substrate200. The adhesive layer330may include a dielectric adhesive material such as a die attach film (DAF).

The plurality of first semiconductor chips300-1to300-4may be stacked in such a manner that the one-side chip pads310A and the redistribution pads323A of each of the first semiconductor chips300-1to300-4are all exposed. For example, any one of the first semiconductor chips300-1to300-4may be stacked with a constant offset from another first semiconductor chip, which is adjacent in the stacking direction, in a predetermined direction parallel to the first surface201of the carrier substrate200. The predetermined direction may indicate a direction away from a first side surface303close to the one-side chip pads310A and a fourth side surface306close to the redistribution pads323A, among third directions crossing the first and second directions. The predetermined direction will be hereafter referred to as a first offset direction. Hereafter, the offset between the first semiconductor chips300-1to300-4adjacent to each other will be referred to as a first offset D1. The first offset D1may be constant or not, but needs to have a value capable of exposing at least the one-side chip pads310A and the redistribution pads323A. The cross-sectional view ofFIG. 2B, taken in the third direction, illustrates the first chip stack300having a stair shape as a whole.

As the first semiconductor chips are offset-stacked, the one-side chip pads310A and the redistribution pads323A of the lowermost first semiconductor chip300-1might not be covered by the other first semiconductor chips300-2to300-4, but exposed to the outside.

Similarly, the one-side chip pads310A and the redistribution pads323A of the first semiconductor chip300-2located at the second place from the bottom might not be covered by the first semiconductor chips300-3and300-4located over the first semiconductor chip300-2, but exposed to the outside, and the one-side chip pads310A and the redistribution pads323A of the first semiconductor chip300-3located at the third place from the bottom might not be covered by the first semiconductor chip300-4located on the first semiconductor chip300-3but exposed to the outside. Since the uppermost first semiconductor chip300-4is located at the uppermost part of the first chip stack300, the uppermost first semiconductor chip300-4may be always exposed regardless of the stack structure, if the semiconductor package includes only the first chip stack300. In this case, the redistribution pads323A and the redistribution lines323B of the uppermost first semiconductor chip300-4may be omitted. As will be described below, however, when another semiconductor chip, for example, a second semiconductor chip400-1ofFIGS. 3A and 3Bis located on the first semiconductor chip300-4, the first semiconductor chip300-4may include the redistribution pads323A and the redistribution lines323B like the other first semiconductor chips300-1to300-3.

Then, referring toFIGS. 3A, 3B, 4A, and 4B, a second chip stack400may be formed on the first chip stack300. For reference,FIGS. 3A and 3Billustrate only the second semiconductor chip400-1located at the lowermost part among second semiconductor chips400-1to400-4included in the second chip stack400, for description.FIGS. 4A and 4Billustrate the entire second chip stack400.

The second chip stack400may include the plurality of second semiconductor chips400-1to400-4stacked in the vertical direction. The number of the second semiconductor chips400-1to400-4included in the second chip stack400may be set to four which is equal to the number of the first semiconductor chips300-1to300-4included in the first chip stack300. However, the present embodiments are not limited thereto, but the number of the semiconductor chips included in the second chip stack400may be set to various values such as, but not limited to, 2 and 8. The number of the semiconductor chips included in the second chip stack400may be different from the number of the semiconductor chips included in the first chip stack300. For convenience of description, the four second semiconductor chips are sequentially represented by reference numerals400-1to400-4in ascending order of distance from the carrier substrate200.

Each of the second semiconductor chips400-1to400-4may have substantially the same structure as the semiconductor chip100ofFIGS. 1A and 1Band/or each of the first semiconductor chips300-1to300-4. Thus, each of the second semiconductor chips400-1to400-4may include chip pads410, an active surface401on which a redistribution conductive layer423including redistribution pads423A and redistribution lines423B is disposed, an inactive surface402located on the opposite side of the active surface401, and first to fourth side surfaces403to406connecting the active surface401and the inactive surface402.

However, each of the second semiconductor chips400-1to400-4may be stacked in the same state as the state in which the semiconductor chip100is rotated by 180 degrees about one axis in a direction parallel to the side surfaces103to106of the semiconductor chip100, i.e. a direction passing through the active surface101and the inactive surface102. Therefore, the first to fourth side surfaces403to406of each of the second semiconductor chips400-1to400-4may be located at the opposite positions of the positions of the first to fourth side surfaces303to306of each of the first semiconductor chips300-1to300-4, respectively. That is, under the supposition that the first to fourth side surfaces303to306of each of the first semiconductor chips300-1to300-4are located on the top, right, bottom and left sides on a plane, respectively, the first to fourth side surfaces403to406of each of the second semiconductor chips400-1to400-4may be located on the bottom, left, top and right sides on the plane, respectively. Furthermore, the chip pads410and the redistribution conductive layers423of the second semiconductor chips400-1to400-4may also be located at the opposite positions of the positions of the chip pads310and the redistribution conductive layers323of the first semiconductor chips300-1to300-4. That is, under the supposition that the one-side chip pads310A and the other-side chip pads310B of the first semiconductor chips300-1to300-4are located at the top and bottom edge areas on the plane and the redistribution pads323A are located close to the bottom side at the left edge area on the plane, the one-side chip pads410A and the other-side chip pads410B of the second semiconductor chips400-1to400-4may be located at the bottom and top edge areas on the plane, and the redistribution pads423A may be located close to the top side at the right edge area on the plane.

For reference,FIGS. 3B and 4Bare cross-sectional views taken along the line A2-A2′ likeFIG. 2B. Unlike the first semiconductor chips300-1to300-4, the one-side chip pads410A of the second semiconductor chips400-1to400-4may be seen on the cross-sectional views, and the other-side chip pads410B and the redistribution pads423A might not be seen on the cross-sectional views. For convenience of description, illustration of the redistribution lines423B and the redistribution dielectric layer is omitted from the cross-sectional views ofFIGS. 3B and 4B. However, each of the second semiconductor chips400-1to400-4may include the same redistribution layer as the chip redistribution layer120described with reference to the cross-sectional view ofFIG. 1B.

The second semiconductor chips400-1to400-4may be the same memory chips, for example, mobile DRAM chips. The second semiconductor chips400-1to400-4may be the same memory chips as the first semiconductor chips300-1to300-4.

The plurality of second semiconductor chips400-1to400-4may be stacked on the first chip stack300in such a manner that the inactive surface402faces the carrier substrate200and the active surface401is located on the opposite side of the inactive surface402. That is, the plurality of second semiconductor chips400-1to400-4may be stacked in a face-up manner. The inactive surface402of each of the second semiconductor chips400-1to400-4may have an adhesive layer430formed thereon. Through the adhesive layer430, each of the second semiconductor chips400-1to400-4may be attached to the second semiconductor chip located immediately thereunder or the active surface301of the uppermost first semiconductor chip300-4of the first chip stack300. The adhesive layer430may include a dielectric adhesive material such as a DAF.

The plurality of second semiconductor chips400-1to400-4may be stacked in such a manner that the one-side chip pads410A and the redistribution pads423A of each of the second semiconductor chips400-1to400-4are all exposed. For example, any one of the second semiconductor chips400-1to400-4may be stacked with a constant offset from another second semiconductor chip, which is adjacent in the stacking direction, in a predetermined direction parallel to the first surface201of the carrier substrate200. The predetermined direction may indicate a direction away from the first side surface403close to the one-side chip pads410A and the fourth side surface406close to the redistribution pads423A, among the third directions crossing the first and second directions. The predetermined direction will be hereafter referred to as a second offset direction. Since the one-side chip pads410A and the redistribution pads423A of the second semiconductor chips400-1to400-4are located on the opposite side of the one-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4, respectively, the second offset direction may face the opposite direction of the first offset direction. For example, when the first offset direction faces between the right and bottom sides, the second offset direction may face between the top and left sides while being parallel to the first offset direction. Hereafter, the offset between the second semiconductor chips400-1to400-4adjacent to each other will be referred to as a second offset D2. The second offset D2may be constant or not, but needs to have a value capable of exposing at least the one-side chip pads410A and the redistribution pads423A. In an embodiment, the second offset D2may be equal to the first offset D1. In other embodiments, however, the second offset D2may be different from the first offset D1.FIG. 4B, which is a cross-sectional view taken in the third direction, shows the second chip stack400having a stair shape facing the opposite direction of the first chip stack300.

As the second semiconductor chips are offset-stacked, the one-side chip pads410A and the redistribution pads423A of the lowermost second semiconductor chip400-1might not be covered by the other second semiconductor chips400-2to400-4, but exposed to the outside. Similarly, the one-side chip pads410A and the redistribution pads423A of the second semiconductor chip400-2located at the second place from the bottom might not be covered by the second semiconductor chips400-3and400-4located on the second semiconductor chip400-2, but exposed to the outside, and the one-side chip pads410A and the redistribution pads423A of the second semiconductor chip400-3located at the third place from the bottom might not be covered by the second semiconductor chip400-4located on the second semiconductor chip400-3, but exposed to the outside. Since the uppermost second semiconductor chip400-4is located at the uppermost part of the second chip stack400, the redistribution layer including the redistribution pads423A and the redistribution lines423B may be omitted from the uppermost second semiconductor chip400-4as illustrated inFIG. 4A, when the semiconductor package includes only the first and second chip stacks300and400and no other electronic elements are disposed on the second chip stack400. However, when an electronic element (not illustrated) such as another semiconductor chip is disposed on the second chip stack400, the uppermost second semiconductor chip400-4may include the redistribution pads423A and the redistribution lines423B like the other second semiconductor chips400-1to400-3.

One-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4may be exposed. That is, one-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4may not covered by the second chip stack400. This is in order to form vertical interconnectors on the one-side chip pads310A and the redistribution pads323A to be extended in the vertical direction, as will be described below. Meanwhile, since the offset stacking direction of the second chip stack400is opposite to the offset stacking direction of the first chip stack300, the second chip stack400is likely to cover at least some of the one-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4. In some embodiments, in order to prevent such a risk, a distance D3between the lowermost second semiconductor chip400-1of the second chip stack400and the uppermost first semiconductor chip300-4of the first chip stack300in the third direction may be increased as much as possible. Furthermore, the second offset D2may be reduced as much as possible. In other embodiments, in order to prevent such a risk, a distance D3between the lowermost second semiconductor chip400-1of the second chip stack400and the uppermost first semiconductor chip300-4of the first chip stack300in the third direction may be increased to allow the vertical interconnectors on the one-side chip pads310A and the redistribution pads323A to be extended in the vertical direction. Furthermore, in these other embodiments, the second offset D2may be reduced to allow the vertical interconnectors on the one-side chip pads310A and the redistribution pads323A to be extended in the vertical direction.

However, when the distance D3is excessively increased, the second chip stack400might not be reliably supported by the first chip stack300, but tilted to one side. In order to prevent such a tilt, the distance D3may be properly adjusted, or a support structure (not illustrated) having substantially the same thickness as the first chip stack300may be formed under the second chip stack400.

In this way, the first and second chip stacks300and400may be formed in an arrow shape facing the first offset direction over the carrier substrate200. In this state, the one-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4of the first chip stack300may be all exposed, and the one-side chip pads410A and the redistribution pads423A of the second semiconductor chips400-1to400-3of the second chip stack400except the uppermost second semiconductor chip400-4may be all exposed. Since the entire active surface401of the uppermost second semiconductor chip400-4is exposed, all of the chip pads410may be exposed.

Referring toFIGS. 5A and 5B, first vertical interconnectors340may be formed on the one-side chip pads310A and the redistribution pads323A of the first semiconductor chips300-1to300-4and extended in the vertical direction while connected to the one-side chip pads310A and the redistribution pads323A, respectively. Second vertical interconnectors440may be formed on the one-side chip pads410A and the redistribution pads423A of the second semiconductor chips400-1to400-3and the chip pads410of the uppermost second semiconductor chip400-4of the second chip stack400, and extended in the vertical direction while connected to the one-side chip pads410A, the redistribution pads423A and the chip pads410, respectively.

The first and second vertical interconnectors340and440may be bonding wires, for example. When the first and second vertical interconnectors340and440are bonding wires, a process of forming the first and second vertical interconnectors340and440will be briefly described as follows. For example, the process of forming the first vertical interconnectors340connected to the one-side chip pads310A will be described. First, one end of a wire may be bonded to the one-side chip pad310A by a wire bonding machine (not illustrated). The wire may include metals, such as gold, silver, copper and platinum, or alloys thereof, which can be welded to the one-side chip pad310A by ultrasonic energy and/or heat. Then, the other end of the wire may be pulled in the vertical direction away from the carrier substrate200, for example, from bottom to top by the wire bonding machine. Subsequently, when the other end of the wire is extended to a desired position, the other end of the wire may be cut. In this way, the first vertical interconnector340may be formed, which has a first end (for example, a lower end) bonded to the one-side chip pad310A and a second end (for example, an upper end) located at a predetermined distance from the first surface201of the carrier substrate200. The predetermined distance may have a larger value than a distance from the first surface201of the carrier substrate200to the top surface of the second chip stack400. That is, a distance from the bottom surface of the first chip stack300to the second ends of the first and second vertical interconnectors340and440is larger than a distance from the bottom surface of the first chip stack300to the top surface of the second chip stack400.

The second vertical interconnector440connected to each of the chip pads410of the second semiconductor chip400-4located at the uppermost part of the second chip stack400may be another type of interconnector instead of a bonding wire. For example, the second vertical interconnector440connected to each of the chip pads410of the second semiconductor chip400-4may be various types of bumps such as a stud bump and a pillar bump. The bump may include metals such as copper, silver, tin and lead.

Referring toFIG. 6, a molding layer500may be formed on the carrier substrate200on which the first and second chip stacks300and400and the first and second vertical interconnectors340and440are formed.

The molding layer500may be formed through a molding process of filling an empty space of a molding die (not illustrated) with a molding material and then curing the molding material. The molding material may include thermosetting resin, for example, epoxy mold compound (EMC).

The molding layer500may be formed to expose the other ends of the first and second vertical interconnectors340and440, for example, the upper ends, while covering the first and second chip stacks300and400and the first and second vertical interconnectors340and440. For this structure, after the molding layer500is formed to such a thickness that covers the first and second chip stacks300and400and the first and second vertical interconnectors340and440, a grinding process may be performed on the molding layer500. The grinding process may include a mechanical or chemical polishing process. Alternatively, by adjusting the shapes of the first and second vertical interconnectors340and440and/or the shape of the molding die without the grinding process, the other ends of the first and second vertical interconnectors340and440may be exposed.

Thus, the molding layer500may have a first surface501formed at substantially the same level as the other ends of the first and second vertical interconnectors340and440, and the other ends of the first and second vertical interconnectors340and440may be exposed through the first surface501.

Referring toFIG. 7, a package redistribution layer600may be formed on the first surface501of the molding layer500. In order to distinguish from the redistribution layers120,323and423formed in the above-described semiconductor chips, the redistribution layer formed on the first surface501of the molding layer500is referred to as the package redistribution layer600.

The formation process of the package redistribution layer600will be described as follows. First, a first redistribution dielectric layer610may be formed on the first surface501of the molding layer500. The first redistribution dielectric layer610may be patterned to have openings that expose the other ends of the first and second vertical interconnectors340and440, respectively. Then, a redistribution conductive layer620may be formed on the first redistribution dielectric layer610. The redistribution conductive layer620may fill the openings of the first redistribution dielectric layer610to be electrically coupled to the other ends of the first and second vertical interconnectors340and440, and patterned in various shapes. The redistribution conductive layer620connected to the first vertical interconnectors340will be referred to as a first redistribution conductive layer620A, and the redistribution conductive layer620connected to the second vertical interconnectors440will be referred to as a second redistribution conductive layer620B. Then, a second redistribution dielectric layer630may be formed on the first redistribution dielectric layer610and the redistribution conductive layer620. The second redistribution dielectric layer630may be patterned to have openings that expose portions of the redistribution conductive layer620.

Subsequently, external connection terminals700may be formed on the package redistribution layer600to be electrically coupled to the redistribution conductive layer620through the openings of the second redistribution dielectric layer630. In an embodiment, solder balls may be used as the external connection terminals700. However, the present embodiments are not limited thereto, but various types of electrical connectors may be used as the external connection terminals700. The external connection terminals700may include a first external connection terminal700A connected to the first redistribution conductive layer620A and a second external connection terminal700B connected to the second redistribution conductive layer620B.

Then, the carrier substrate200may be removed. The carrier substrate200may be removed at any time after the molding layer500is formed.

Through the above-described process, the semiconductor package illustrated inFIG. 7may be fabricated.

Referring back toFIG. 5AwithFIG. 7, the semiconductor package in accordance with an embodiment may include the first chip stack300, the first vertical interconnectors340, the second chip stack400and the second vertical interconnectors440. The first chip stack300may include the plurality of first semiconductor chips300-1to300-4stacked in the vertical direction, and the first vertical interconnectors340may be electrically coupled to the plurality of first semiconductor chips300-1to300-4, respectively, and extended in the vertical direction. The second chip stack400may be disposed on the first chip stack300and include the plurality of second semiconductor chips400-1to400-4stacked in the vertical direction, and the second vertical interconnectors440may be electrically coupled to the plurality of second semiconductor chips400-1to400-4, respectively, and extended in the vertical direction.

Each of the first semiconductor chips300-1to300-4may include the active surface301, one-side first chip pads310A, other-side first chip pads310B, and first redistribution pads323A. The active surface301may be defined by both side surfaces in the first direction and both side surfaces in the second direction. The one-side first chip pads310A may be disposed at an edge of the active surface301, which is close to one side surface in the first direction, and the other-side first chip pads310B may be disposed at an edge of the active surface301, which is close to the other side surface in the first direction. The first redistribution pads323A may be electrically coupled to the other-side first chip pads310B and disposed at an edge of the active surface301, which is close to one side surface between both side surfaces in the second direction.

The plurality of first semiconductor chips300-1to300-4may be offset-stacked in the third direction crossing the first and second directions, such that the one-side first chip pads310A and the first redistribution pads323A are exposed. For example, the plurality of first semiconductor chips300-1to300-4may be stacked with an offset in a direction away from the one side surface in the first direction and the one side surface in the second direction.

The first vertical interconnectors340may have one ends connected to the exposed one-side first chip pad310A and the exposed first redistribution pad323A.

Each of the second semiconductor chips400-1to400-4may be stacked in the same state as the state in which any one of the first semiconductor chips300-1to300-4is rotated by 180 degrees about one axis parallel to the vertical direction. Thus, the second semiconductor chip may include one-side second chip pads410A, other-side second chip pads410B and second redistribution pads423A, which are located at the opposite positions of the positions of the one-side first chip pads310A, the other-side first chip pads310B and the first redistribution pads323A. However, since the uppermost second semiconductor chip400-4does not need the second redistribution pads423A, the second redistribution pads423A may be omitted from the uppermost second semiconductor chip400-4.

The plurality of second semiconductor chips400-1to400-4may be offset-stacked in the third direction such that the one-side second chip pads410A and the second redistribution pads423A are exposed. For example, the plurality of second semiconductor chips400-1to400-4may be offset-stacked in the opposite direction of the offset stacking direction of the first semiconductor chips300-1to300-4.

The second vertical interconnector440may have one end connected to the one-side second chip pad410A and the second redistribution pad423A. However, when the second redistribution pads423A are omitted from the uppermost second semiconductor chip400-4, the second vertical interconnector440connected to the uppermost second semiconductor chip400-4may have one end connected to the one-side second chip pad410A and the other-side second chip pad410B.

The semiconductor package in accordance with an embodiment may further include the molding layer500covering the first and second chip stacks300and400and the package redistribution layer600and the external connection terminals700which are formed on the first surface501of the molding layer500. Since the package redistribution layer600can be formed in the area defined by the molding layer500, the semiconductor package in accordance with an embodiment may be a fan-out semiconductor package.

The first chip stack300may be recognized as one semiconductor chip while connected to an external component through the first vertical interconnector340, the first redistribution conductive layer620A and the first external connection terminal700A, which are connected thereto. The second chip stack400may be recognized as another semiconductor chip different from the first chip stack300, while connected to an external component through the second vertical interconnector440, the second redistribution conductive layer620B and the second external connection terminal700B, which are connected thereto. That is, the electrical path through the first chip stack300, the first vertical interconnector340, the first redistribution conductive layer620A and the first external connection terminal700A may be electrically isolated from and recognized as a separate path from the electrical path through the second chip stack400, the second vertical interconnector440, the second redistribution conductive layer620B and the second external connection terminal700B.

Since the components of the semiconductor package have been already described while the fabrication method is described, the detailed descriptions thereof are omitted herein.

The semiconductor package and the method for fabricating the same, which have been described so far, may acquire the following effects.

First, the semiconductor package including the plurality of stacked semiconductor chips can be formed to satisfy high-performance/high-capacity requirements. Furthermore, the fan-out semiconductor package using the redistribution layer instead of the existing substrate can be formed through the vertical wires, which makes it possible to implement the semiconductor package with a small thickness.

Furthermore, the semiconductor package and the fabrication method can solve a problem in which it is difficult to stack semiconductor chips while exposing all chip pads disposed at both edges thereof, when the semiconductor chips include the chip pads disposed at both edges thereof. For example, the redistribution layer may be added to the semiconductor chips, and the plurality of semiconductor chips may be offset-stacked in a diagonal direction, in order to solve the problem. In particular, the redistribution layer connected only to the chip pads disposed at one edge of the semiconductor chip between both edges thereof may be formed, which makes it possible to reduce the process cost or to lower the difficulty level of the process, due to the formation of the redistribution layer.

In an embodiment, the case in which the semiconductor package includes two chip stacks stacked in the vertical direction, i.e. the first and second chip stacks300and400has been described. However, the semiconductor package may include only any one of the first and second chip stacks300and400, and one or more chip stacks may be further disposed on the second chip stack400.

When the semiconductor package includes only one chip stack, the redistribution layer of the uppermost semiconductor chip may be omitted. Thus, the vertical interconnectors connected to the uppermost semiconductor chip may be connected to the one-side chip pads and the other-side chip pads, respectively. Furthermore, the vertical interconnectors connected to the uppermost semiconductor chip may be conductive bumps, and the vertical interconnectors connected to the other semiconductor chips may be bonding wires.

When the semiconductor package includes three or more chip stacks, structures similar to the first and second chip stacks300and400may be repeatedly stacked over the first and second chip stacks300and400. Among the semiconductor chip stacks, only the redistribution layer of the uppermost semiconductor chip of the uppermost chip stack may be omitted, and the other semiconductor chips may include the redistribution layer. Three or more chip stacks may be stacked while the offset directions thereof are alternately changed to expose all of the one-side chip pads and the redistribution pads of the semiconductor chips except the uppermost semiconductor chip.

Since the case in which the semiconductor package includes only one chip stack or three or more chip stacks can be easily derived from the descriptions of the above-described embodiments, the detailed descriptions thereof are omitted herein.

In accordance with the present embodiments, it is possible to provide a semiconductor package which has a small thickness and can satisfy high-performance and high-capacity requirements through the method for stacking a plurality of semiconductor chips each having chip pads disposed at both edges thereof.

FIG. 8shows a block diagram illustrating an electronic system including a memory card7800employing at least one of the semiconductor packages according to the embodiments. The memory card7800includes a memory7810, such as a nonvolatile memory device, and a memory controller7820. The memory7810and the memory controller7820may store data or read out the stored data. At least one of the memory7810and the memory controller7820may include at least one of the semiconductor packages according to described embodiments.

The memory7810may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG. 9shows a block diagram illustrating an electronic system8710including at least one of the semiconductor packages according to described embodiments. The electronic system8710may include a controller8711, an input/output device8712, and a memory8713. The controller8711, the input/output device8712, and the memory8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711or the memory8713may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen and so forth. The memory8713is a device for storing data. The memory8713may store data and/or commands to be executed by the controller8711, and the like.

The memory8713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. For example, a flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system8710represents equipment capable of performing wireless communication, the electronic system8710may be used in a communication system using a technique of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband Internet).

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims.