CIRCUIT AND METHOD FOR OPERATING AN ANALOG-TO-DIGITAL CONVERTER IN MULTIPLE MODES USING RING OSCILLATORS

A device may include one or more ring oscillators and circuitry. The one or more ring oscillators may include a plurality of rings. The circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. The circuitry may be configured to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals to one or more digital signals.

FIELD OF THE DISCLOSURE

This disclosure generally relates to systems and methods for analog-to-digital conversion, and more particularly to operating an analog-to-digital converter (ADC) in multiple modes using ring oscillators.

BACKGROUND

In a ring oscillator-based ADC (e.g., voltage-controlled ring oscillator (VCRO)-based ADC), the phase noise of the VCRO may be a major contributor to the noise floor of the ADC (e.g., the amount of noise generated by the ADC). Moreover, the power consumption of an ADC may not scale with bandwidths, thereby causing the chip power consumption to be relatively high even in the lowest bandwidth.

The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below.

DETAILED DESCRIPTION

Various embodiments disclosed herein are related to a device including one or more ring oscillators and circuitry. In some embodiments, a ring oscillator is a device or circuitry whose output oscillates between two voltage levels using a plurality of buffers, delay stages, inverters (e.g., NOT gates), or amplifiers connected in a ring according to some embodiments. For example, a ring oscillator may include an odd number of NOT gates or inverters connected in a ring. In some embodiments, a ring oscillator may include (1) an odd number of NOT gates or inverters and (2) one or more other non-inverting buffers/delay stages/amplifiers. In some embodiments, a ring oscillator may include one or more rings or a plurality of rings in each of which a plurality of buffers, delay stages, inverters, or amplifiers are connected. The circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. Coupled rings refers to a plurality of rings (in a ring oscillator) coupled to one another such that at least one buffer, delay stage, inverter or amplifier of one ring is coupled to at least one buffer, delay stage, inverter or amplifier of another ring, according to some embodiments. The circuitry may be configured to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals to one or more digital signals.

In some embodiments, the circuitry may be configured to receive a selection of a sampling frequency. The circuitry may be configured to convert the plurality of signals to the one or more digital signals at least based on the sampling frequency.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include a multi-ring oscillator having N rings that are coupled to each other. In configuring the one or more ring oscillators, the circuitry may be configured to configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include N ring oscillators, each having a different number of coupled rings to each other. In configuring the one or more ring oscillators, the circuitry may be configured to select a ring oscillator having L coupled rings, from among the N ring oscillators, as the configured one or more ring oscillators.

In some embodiments, the circuitry may include a plurality of circuits respectively configured to perform a plurality of modes of analog digital converter (ADC) operations. Modes of ADC operations refer to different configurations of a plurality of components of an ADC (e.g., ring oscillator, sampling circuitry, phase decoder, differentiator, decimator, or other components), or other configuration that may produce different power consumption characteristics of the ADC (e.g., power consumption with respect to bandwidths, dynamic ranges, phase noise, quantization noise, etc.). The circuitry may be configured to select one or more circuits from among the plurality of circuits. The circuitry may be configured to cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals.

Various embodiments disclosed herein are related to an analog digital converter including an input to receive an analog signal, one or more ring oscillators, and circuitry. In some embodiments, the one or more ring oscillators may include a plurality of rings. The one or more ring oscillators may be configurable to operate at least based on a programmable number of coupled rings of the plurality of rings. The circuitry may be coupled to the one or more ring oscillators. The circuitry may be programmable to receive a selection of a number of coupled rings and a number of phases. The circuitry may be programmable to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be programmable to cause the configured one or more ring oscillators to receive the analog signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be programmable to convert the plurality of signals to one or more digital signals.

In some embodiments, the circuitry may be configured to receive a selection of a sampling frequency. The circuitry may be configured to convert the plurality of signals to the one or more digital signals at least based on the sampling frequency.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include a multi-ring oscillator having N rings that are coupled to each other. In configuring the one or more ring oscillators, the circuitry may be configured to configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include N ring oscillators, each having a different number of coupled rings to each other. In configuring the one or more ring oscillators, the circuitry may be configured to select a ring oscillator having L coupled rings, from among the N ring oscillators, as the configured one or more ring oscillators.

In some embodiments, the circuitry may include a plurality of circuits respectively configured to perform a plurality of modes of analog digital converter operations. The circuitry may be configured to select one or more circuits from among the plurality of circuits. The circuitry may be configured to cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals.

Various embodiments disclosed herein are related to a device including one or more ring oscillators and circuitry. In some embodiments, the one or more ring oscillators may be configured to receive an input signal and output a plurality of signals. The circuitry may be configured to convert the plurality of signals from the one or more ring oscillators to one or more digital signals. The one or more ring oscillators may include a multi-ring oscillator having first-to-Nthrings, each ring comprising first-to-Mthdifferential amplifiers. N and M may be integers greater than 1. A multi-ring oscillator refers to a ring oscillator including a plurality of rings in each of which a plurality of buffers, delay stages, inverters, or amplifiers are connected, according to some embodiments. The term “differential amplifier” means an amplifier, a buffer, delay stage, or other electronic device that has at least two inputs and amplifies or outputs a difference between two inputs, according to some embodiments. In some embodiments, a differential amplifier may include at least one output (e.g., two outputs). Each differential amplifier may have a first input and a first output that have a first polarity, and a second input and a second output that have a second polarity. The first to Nthrings may be cyclically coupled such that the second output of the Mthdifferential amplifier of the Nthring is coupled to the first output of the first differential amplifier of the first ring. Cyclically coupled rings refer to a plurality of rings that are connected to one another such that buffers, delay stages, inverters or amplifiers of respective ones of the plurality of rings are coupled in a cycle, a ring, or a chain, according to some embodiments.

In some embodiments, the first to Nthrings may be cyclically coupled such that the second input of the Mthdifferential amplifier of the Nthring is coupled to the second output of the Mthdifferential amplifier of the first ring.

In some embodiments, in each ring, the first output and the second output of the ithdifferential amplifier may be coupled to the first input and the second input of the (i+1)thdifferential amplifier, respectively, where i is an integer that is greater than or equal to 1 and less than M. The first output and the second output of the Mthdifferential amplifier may be coupled to the second input and the first input of the first differential amplifier, respectively.

In some embodiments, the first outputs of the ithdifferential amplifiers of the N rings may be coupled to each other, where i is an integer that is greater than or equal to 1 and less than or equal to M. The second outputs of the ithdifferential amplifiers of the N rings may be coupled to each other.

In some embodiments, the circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. The circuitry may be configured to configure the multi-ring oscillator to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured multi-ring oscillator to output the plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals from the configured multi-ring oscillator to one or more digital signals. The circuitry may be configured to receive a selection of a sampling frequency, and convert the plurality of signals from the configured multi-ring oscillator to the one or more digital signals at least based on the sampling frequency. The number of coupled rings may be an integer L that is less than or equal to N. In configuring the one or more ring oscillators, the circuitry may be configured to configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators.

In some embodiments, the circuitry may include a plurality of circuits respectively configured to perform a plurality of modes of analog digital converter operations. The circuitry may be configured to select one or more circuits from among the plurality of circuits, and cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals.

Various embodiments disclosed herein are related to a method. The method includes receiving, by circuitry, a selection of a number of coupled rings and a number of phases. The method may include configuring, by the circuitry, one or more ring oscillators to operate at least based on the number of coupled rings. The one or more ring oscillators may include a plurality of rings. The method may include causing, by the circuitry, the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The method may include converting, by the circuitry, the plurality of signals to one or more digital signals.

In some embodiments, the circuitry may receive a selection of a sampling frequency. The circuitry may convert the plurality of signals to the one or more digital signals at least based on the sampling frequency.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include a multi-ring oscillator having N rings that are coupled to each other. In configuring the one or more ring oscillators, the circuitry may configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may be N ring oscillators, each having a different number of coupled rings to each other. In configuring the one or more ring oscillators, the circuitry may select a ring oscillator having L coupled rings, from among the N ring oscillators, as the configured one or more ring oscillators.

In some embodiments, the circuitry may include a plurality of circuits respectively configured to perform a plurality of modes of analog digital converter operations. The circuitry may select one or more circuits from among the plurality of circuits. The circuitry may cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals.

In one aspect, in a ring oscillator-based ADC (e.g., VCRO-based ADC), the phase noise of the VCRO may be a major contributor to the noise floor of the ADC (e.g., the amount of noise generated by the ADC). For example, in wireless local area network (WLAN) radio receivers, it would be beneficial for an ADC to maintain the same or similar dynamic range over across different ranges of baseband bandwidth. Therefore, there is a need to reduce the phase noise of the VCRO in VCRO-based ADCs used in WLAN receivers.

To solve this problem, according to certain aspects, embodiments in the present disclosure relate to techniques for configuring a ring oscillator (e.g., VCRO) including a plurality of rings to improve/reduce phase noises and/or quantization noises of the VCRO. In some embodiments, the plurality of rings may be coupled to one another to improve/reduce phase noises and/or quantization noises of the VCRO. In some embodiments, the plurality of rings (e.g., L number of rings) may cyclically coupled in a VCRO (e.g., L-ring coupled VCRO), providing (1) approximately 10×log 10 (L) dB improvement in phase noise compared to a VCRO including a single ring (e.g., single-ring VCRO), and/or (2) improvement in the quantization noise of an ADC compared to an ADC using a single-ring VCRO. An L-ring coupled oscillator refers to a ring oscillator (e.g., VCRO) including L number of rings that are cyclically coupled together or to one another.

In some embodiments, an L-ring coupled oscillator may include a first ring, a second ring, . . . , a Lthring, in each of which M number of delay stages (e.g., amplifier, buffer, inverter, etc.) are coupled/connected in ring. In some embodiments, each delay stage may include a differential amplifier that has at least two inputs and amplifies or outputs a difference between two inputs. In some embodiments, a differential amplifier may include at least one output (e.g., two outputs). In some embodiments, in each ring, outputs of a one delay stage may be coupled to inputs of a next delay stage next to or adjacent to the one delay stage, and outputs of an Mthdelay stage may be coupled to inputs of a first delay stage. For example, in each ring, an output phase of a non-inverting output of the first delay stage may be coupled to an output phase of a non-inverting input of the second delay stage, and so on. In each ring, an output phase of an inverting output of the first delay stage may be coupled to an output phase of an inverting input of the second delay stage, and so on. An output phase of an inverting output of the Mthdelay stage may be coupled to an output phase of a non-inverting input of the first delay stage, and an output phase of a non-inverting output of the Mthdelay stage may be coupled to an output phase of an inverting input of the first delay stage.

In some embodiments, L number of rings may be cyclically coupled such that output phases of the Lthring may be coupled to output phases of the first ring. For example, an output phase of an inverting output of the Mthdelay stage in the Lthring may be coupled to an output phase of a non-inverting output of the first delay stage in the first ring. The output phase of the non-inverting output of the first delay stage in the first ring may be coupled to an output phase of the non-inverting output of the first delay stage in the second ring, and so on. The output phase of the non-inverting output of the first delay stage in the Lthring may be coupled to an output phase of the non-inverting output of the second delay stage in the first ring. Similarly, for inverting outputs, an output phase of an inverting output of the first delay stage in the first ring may be coupled to an output phase of an inverting output of the first delay stage in the second ring, and so on. An output phase of an inverting output of the first delay stage in the Lthring may be coupled to an output phase of an inverting output of the second delay stage in the first ring. An output phase of an inverting output of the (M−1)thdelay stage in the Lthring may be coupled to an output phase of an inverting output of the Mthdelay stage in the first ring.

Coupling L number of rings (in a ring oscillator) in this manner can reduce the phase noise of the ring oscillator (e.g., VCRO) by approximately 10*log 10 (L) dB compared to a single-ring VCRO. Moreover, the multi-ring coupled VCRO according to some embodiments can improve the quantization noise (in a VCRO-based ADC) compared to an ADC including a single-ring VCRO.

In another aspect, it would be beneficial if the power consumption of an ADC can scale with bandwidths because it can keep the chip power consumption low in the lowest bandwidth. For example, in WLAN receivers with different process sizes, it would be beneficial for an ADC, which may use a successive approximation register (SAR) architecture, to consume power proportional to bandwidths, while maintaining the same or similar dynamic range across all baseband bandwidth ranges. Conventional VCRO-based ADCs may either support only one bandwidth or support multiple bandwidths with the same power consumption. In the latter cases, the same or fixed power consumption may be dictated by the highest bandwidths supported, which makes the ADC power consumption inefficient in the lowest bandwidths supported. Therefore, there is a need to scale the power consumption of an ADC with bandwidths, for example, when using VCRO-based ADCs in WLAN receivers.

To solve this problem, according to certain aspects, embodiments in the present disclosure relate to techniques for providing a multi-mode ADC including a ring oscillator (e.g., VCRO). A multi-mode or multiple modes of ADC operations refer to different configurations of a plurality of components of an ADC (e.g., ring oscillator, sampling circuitry, phase decoder, differentiator, decimator, or other components), or other configuration that may produce different power consumption characteristics of the ADC (e.g., power consumption with respect to bandwidths, dynamic ranges, phase noise, quantization noise, etc.), according to some embodiments. In some embodiments, the multi-mode ADC including a ring oscillator can scale the power consumption of the ADC depending on bandwidth requirements and/or dynamic range requirements.

In some embodiments, a multi-mode ADC may include a ring oscillator (e.g., VCRO), sampling circuitry, conversion circuitry, and/or control circuitry. The ring oscillator may receive an analog signal (e.g., input voltage for the VCRO) as ADC input and output phase data including a plurality of phase outputs. The sampling circuitry may receive the plurality of phase outputs and output sampled phase data including a plurality of sampled phase outputs. The conversion circuitry may receive the sampled phase data, convert the sampled phase data to one or more digital signals, and output the one or more digital signals as ADC output. The control circuitry may receive control inputs and configure/operate components of the ADC (e.g., ring oscillator, sampling circuitry, conversion circuitry) via one or more control signals according to the received control inputs. In some embodiments, input configuration of the multi-mode ADC may be single-ended. In some embodiments, input configuration of the multi-mode ADC may be pseudo differential.

In some embodiments, the ring oscillator may include a plurality of rings (e.g., N number of rings) and may be implemented as a single ring oscillator instance (e.g., a single VCRO) with a programmable/adjustable number of coupled rings. For example, in response to receiving a control signal indicating L number of coupled rings, the ring oscillator may dynamically configure/adjust L number of rings to be cyclically coupled among the N number of rings.

In some embodiments, the ring oscillator may implemented as separate ring oscillator instances (e.g., N number of VCROs) each with a different number of coupled rings. For example, the ring oscillator may include N ring oscillators which include a single-ring oscillator, a dual-ring coupled oscillator, a 3-ring coupled oscillator, . . . , a N-ring coupled oscillator. In response to receiving a control signal indicating L number of coupled rings, the ring oscillator may select the L-ring coupled oscillator among the N ring oscillators. The implementation of single ring oscillator instance can compromise performance for area saving, while the implementation of separate ring oscillator instances can sacrifice some extra area for better performance.

In some embodiments, the multi-mode ADC (or the control circuitry thereof) may receive, as control inputs, a number of coupled rings in the ring oscillator (L), a number of phase outputs from the ring oscillator (Nϕ), and an ADC sampling frequency (fs) to scale the power consumption of the ADC for different bandwidth requirements and/or dynamic range requirements. In some embodiments, each of the number of coupled rings (L), the number of phase outputs (Nϕ), and the sampling frequency (fs) may be programmable or selectable such that the values L, Nϕ, and/or fscan be dynamically changed by external control inputs or user selection. In response to receiving/selecting the values L, Nϕ, and/or fs, the multi-mode ADC may be configured to use L number of coupled rings, Nϕnumber of phase output from the ring oscillator, and/or the sampling frequency (fs) to scale the power consumption of the ADC to meet the bandwidth requirements and/or dynamic range requirements. In this manner, the multi-mode ADC (which may be used in a radio receiver) can efficiently consume the power with a limited power budget.

In some embodiments, the control circuitry may configure the ring oscillator to operate using L number of coupled rings via a control signal. In some embodiments, the control circuitry may configure, via a control signal, the ring oscillator to output Nϕnumber of phase outputs. In some embodiments, the control circuitry may generate a clock signal according to the sampling frequency (fs) and provide the clock signal to the sampling circuitry and the conversion circuitry so that the sampling circuitry and the conversion circuitry operate according to the sampling frequency (fs). In some embodiments, the sampling frequency is the number of samples per time unit, such as per second, taken from a signal, such as the number of discrete time signals (e.g., values of signals at discrete points in time) per time unit, taken from a continuous time signal (e.g., analog signal).

In some embodiments, the sampling circuitry may include a counter configured to output K number of bits, and a plurality of sampling D flip-flops (DFFs). In response to receiving a first phase output (among the Nϕnumber of phase outputs) from the ring oscillator, the counter may be configured to count a number of cycles in the first phase output (e.g., sine wave signal or square wave signal) and output the number of cycles in K bit as a rate of the original phase data (before sampling). In response to receiving the Nϕnumber of phase outputs from the ring oscillator, the plurality of sampling DFFs may be configured to sample phase outputs according to the sampling frequency (fs) and output sampled phase data. In response to receiving the rate of the original phase data and sampled phase outputs (from the sampling DFFs), the conversion circuitry may be configured to convert the sampled phase data to one or more digital signals, and output the one or more digital signals as ADC output. In this manner, the multi-mode ADC can improve/reduce phase noises and/or quantization noises of the ADC according to a programmable/selectable number of coupled rings. The multi-mode ADC can also scale the power consumption of the ADC across all baseband bandwidth (frequency) ranges to meet the bandwidth requirements and/or dynamic range requirements.

In some embodiments, the conversion circuitry may include a plurality of mode circuits and selection circuitry configured to select one or more mode circuits of the plurality of mode circuits. In some embodiments, each of the plurality of mode circuits may include a phase decoder, one or more differentiators, and/or a decimator. The phase decoder (ϕ-decoder) may be configured to map/decode/convert the sampled phases to quantized phases (e.g., as 1-bit stream). The differentiators may be configured to calculate the difference between the current sample and the previous sample, e.g., s [n]−s [n−1]. The decimator may be configured to down-sample the sampled phase data based on a rate of the original phase data (which is output from the sampling circuitry). In some embodiments, each of the plurality of mode circuits may have different configurations/arrangements of the phase decoder, one or more differentiators, and/or a decimator.

The selection circuitry may include a plurality of AND gates each receiving a clock signal and an internal mode selection signal from the control circuitry. In some embodiments, the control circuitry may receive, as a control input, one or more external mode selection signals and control the selection circuitry to select one or more mode circuits of the plurality of mode circuits via one or more internal mode selection signals according to the one or more external mode selection signals. In response to receiving the one or more internal mode selection signals, the selection circuitry may enable corresponding AND gates via the one or more internal mode selection signals such that the selected mode circuits can operate. In response to receiving a rate of the original phase data and sampled phase data from the sampling circuitry, the selected mode circuits may be configured to operate at least one of a phase decoder, one or more differentiators, and/or a decimator thereof to convert the sampled phase data to one or more digital signals, and output the one or more digital signals as ADC output. In some embodiments, the phase decoder, differentiators, and decimator can be separately implemented for different modes which can save power in low bandwidth/dynamic range modes at the cost of some extra area. Alternatively, the conversion circuitry may include a single logic block that can be configured for different modes, which would save area at the cost of some extra power especially in low bandwidth/dynamic range modes.

Embodiments in the present disclosure have at least the following advantages and benefits. First, embodiments in the present disclosure can provide useful techniques for a multi-mode ADC to scale its power consumption across all baseband bandwidth ranges while maintaining the same or similar dynamic range across all baseband bandwidth ranges. In some embodiments, the multi-mode ADC including a plurality of rings may receive, as control inputs, a number of coupled rings in the ring oscillator (L), a number of phase outputs from the ring oscillator (Nϕ), and an ADC sampling frequency (fs) to scale the power consumption of the ADC for different bandwidth requirements and/or dynamic range requirements. In response to receiving/selecting the values L, Nϕ, and/or fs, the multi-mode ADC may be configured to use L number of coupled rings, Nϕnumber of phase output from the ring oscillator, and/or the sampling frequency (fs) to scale the power consumption of the ADC to meet the bandwidth requirements and/or dynamic range requirements. In this manner, the multi-mode ADC (which may be used in a radio receiver) can efficiently consume the power with a limited power budget.

Second, embodiments in the present disclosure can provide useful techniques for configuring a ring oscillator (e.g., VCRO) including a plurality of rings to improve/reduce phase noises and/or quantization noises of the VCRO. In some embodiments, the plurality of rings may be coupled to one another to improve/reduce phase noises and/or quantization noises of the VCRO. In some embodiments, the plurality of rings (e.g., L number of rings) may cyclically coupled in a VCRO (e.g., L-ring coupled VCRO), providing (1) approximately 10×log 10 (L) dB improvement in phase noise compared to a VCRO including a single ring (e.g., single-ring VCRO), and/or (2) improvement in the quantization noise of an ADC compared to an ADC using a single-ring VCRO.

Third, embodiments in the present disclosure can provide useful techniques for operating an ADC in multiple modes of operations which correspond to different configurations of a plurality of components of the ADC (e.g., ring oscillator, sampling circuitry, phase decoder, differentiator, decimator, or other components), or other configuration that may produce different power consumption characteristics of the ADC (e.g., power consumption with respect to bandwidths, dynamic ranges, phase noise, quantization noise, etc.). In some embodiments, a multi-mode ADC may receive, as a control input, one or more external mode selection signals and select one or more mode circuits of the plurality of mode circuits via one or more internal mode selection signals according to the one or more external mode selection signals. In this manner, the multi-mode ADC can be selectably operated in one or more desirable configurations.

FIG.1is a schematic block diagram of a device100(e.g., multi-mode ADC) for operating an analog-to-digital converter (ADC) in multiple modes, in accordance with an embodiment. Referring toFIG.1, a multi-mode ADC100may include a ring oscillator120(e.g., VCRO), sampling circuitry140, conversion circuitry160, and/or control circuitry150. The ring oscillator120may receive an analog signal (e.g., input voltage for the VCRO) as ADC input101and output phase data121including a plurality of phase outputs. The sampling circuitry140may receive the plurality of phase outputs and output sampled phase data142including a plurality of sampled phase outputs. The conversion circuitry160may receive the sampled phase data142, convert the sampled phase data to one or more digital signals, and output the one or more digital signals as ADC output105. The control circuitry150may receive control inputs103and configure/operate components of the ADC (e.g., ring oscillator120, sampling circuitry140, conversion circuitry160) via one or more control signals (e.g., control signals151,152,153) according to the received control inputs103. In some embodiments, input configuration of the multi-mode ADC may be single-ended. In some embodiments, input configuration of the multi-mode ADC may be pseudo differential.

FIG.2AtoFIG.2Care schematic block diagrams of a ring oscillator200, in accordance with an embodiment. The ring oscillator200(e.g., VCRO) may include a plurality of rings (e.g., first ring, second ring, . . . , Lthring) to improve/reduce phase noises and/or quantization noises of the VCRO. In some embodiments, the plurality of rings (e.g., L number of rings) may cyclically coupled in a VCRO (e.g., L-ring coupled VCRO), providing (1) approximately 10×log 10 (L) dB improvement in phase noise compared to a VCRO including a single ring (e.g., single-ring VCRO), and/or (2) improvement in the quantization noise of an ADC compared to an ADC using a single-ring VCRO. As noted above, an L-ring coupled oscillator refers to a ring oscillator (e.g., VCRO) including L number of rings that are cyclically coupled together or to one another.

Referring toFIG.2A, an L-ring coupled oscillator may include a first ring, a second ring, . . . , a Lthring, in each of which M number of delay stages (e.g., amplifier, buffer, inverter, etc.) are coupled/connected in ring. In some embodiments, each delay stage may include a differential amplifier that has at least two inputs and amplifies or outputs a difference between two inputs. In some embodiments, a differential amplifier may include at least one output (e.g., two outputs). For example, in the first ring, an ith(differential) amplifier200-1-imay have a first (non-inverting) input201-1-i, a second (inverting) input202-1-i, a first (non-inverting) output203-1-i, and a second (inverting) output204-1-i. Similarly, in the Lthring ring, an ith(differential) amplifier200-L-i may have a first (non-inverting) input201-L-i, a second (inverting) input202-L-i, a first (non-inverting) output203-L-i, and a second (inverting) output204-L-i.

Referring toFIG.2B, in each ring, outputs of a one delay stage may be coupled to inputs of a next delay stage next to or adjacent to the one delay stage, and outputs of an Mthdelay stage may be coupled to inputs of a first delay stage. For example, in the first ring, an output phase ϕ<0, 0> of a non-inverting output of the first delay stage200-1-1may be coupled to an output phase of a non-inverting input of the second delay stage200-1-2, and so on. In the first ring, an output phase ϕ<0, M> of an inverting output of the first delay stage200-1-1may be coupled to an output phase of an inverting input of the second delay stage200-1-2, and so on. An output phase ϕ<0, 2M−1> of an inverting output of the Mthdelay stage may be coupled to an output phase of a non-inverting input of the first delay stage200-1-1, and an output phase ϕ<0, M−1> of a non-inverting output of the Mthdelay stage may be coupled to an output phase of an inverting input of the first delay stage200-1-1.

Referring toFIG.2BandFIG.2C, L number of rings may be cyclically coupled such that output phases of the Lthring may be coupled to output phases of the first ring. For example, an output phase211of an inverting output of the Mthdelay stage in the Lthring (200-L-M) may be coupled to an output phase212of a non-inverting output of the first delay stage in the first ring (200-1-1). The output phase212of the non-inverting output of the first delay stage in the first ring (200-1-1) may be coupled to an output phase ϕ<1, 0> of a non-inverting output of the first delay stage in the second ring (200-2-1), and so on. The output phase213of the non-inverting output of the first delay stage in the Lthring (200-L-1) may be coupled to an output phase214of the non-inverting output of the second delay stage in the first ring (200-1-2). Similarly, for inverting outputs, an output phase ϕ<0, M> of an inverting output of the first delay stage in the first ring (200-1-1) may be coupled to an output phase ϕ<1, M> of an inverting output of the first delay stage in the second ring (200-2-1), and so on. An output phase ϕ<L−1, M> of an inverting output of the first delay stage in the Lthring (200-L-1) may be coupled to an output phase ϕ<0, M+1> of an inverting output of the second delay stage in the first ring (200-1-2). An output phase231of an inverting output of the (M−1)thdelay stage in the Lthring (200-L-(M−1)) may be coupled to an output phase of an inverting output232of the Mthdelay stage in the first ring (200-1-M).

Referring toFIG.2AtoFIG.2C, a multi-ring oscillator (e.g., ring oscillator200) having first-to-Lthrings, each ring comprising first-to-Mthdifferential amplifiers (e.g., differential amplifiers200-1-1,200-1-2, . . . ,200-1-M in the first ring. each of L and M may be an integer greater than 1. Each differential amplifier (e.g., ithamplifier200-1-i) may have a first input201-1-iand a first output203-1-ithat have a first polarity (e.g., non-inverting input/output), and a second input202-1-iand a second output204-1-ithat have a second polarity (e.g., inverting input/output). The first to Lthrings may be cyclically coupled such that the second output211of the Mthdifferential amplifier of the Lthring (200-L-M) is coupled to the first output212of the first differential amplifier of the first ring (200-1-1). In some embodiments, the first to Lthrings may be cyclically coupled such that the second input231of the Mthdifferential amplifier of the Lthring (200-L-M) is coupled to the second output232of the Mthdifferential amplifier of the first ring (200-1-M).

In some embodiments, in each ring, the first output and the second output of the ithdifferential amplifier (e.g.,200-1-i) may be coupled to the first input and the second input of the (i+1)thdifferential amplifier (e.g.,200-1-(i+1)), respectively, where i is an integer that is greater than or equal to 1 and less than M. The first output (e.g., ϕ<0, M−1>) and the second output (e.g., ϕ<0, 2M−1>) of the Mthdifferential amplifier (e.g.,200-1-M) may be coupled to the second input and the first input of the first differential amplifier (e.g.,200-1-1), respectively. In some embodiments, the first outputs of the ithdifferential amplifiers of the L rings (e.g., first outputs of the amplifiers200-1-i,200-2-i, . . . ,200-L-i) may be coupled to each other, where i is an integer that is greater than or equal to 1 and less than or equal to M. The second outputs of the ithdifferential amplifiers of the N rings (e.g., second outputs of the amplifiers200-1-i,200-2-i, . . . ,200-L-i) may be coupled to each other.

In some embodiments, a ring oscillator may include a plurality of rings (e.g., N number of rings) and may be implemented as a single ring oscillator instance (e.g., a single VCRO) with a programmable/adjustable number of coupled rings. For example, in response to receiving a control signal indicating L number of coupled rings, the ring oscillator may dynamically configure/adjust L number of rings to be cyclically coupled (in a manner shown inFIG.2AtoFIG.2C) among the N number of rings.

In some embodiments, the ring oscillator may be implemented as separate ring oscillator instances (e.g., N number of VCROs) each with a different number of coupled rings.FIG.3is a schematic block diagram of one or more ring oscillators, in accordance with an embodiment. For example, the ring oscillator300may include N ring oscillators which include a single-ring oscillator300-1, a dual-ring coupled oscillator300-2, a 3-ring coupled oscillator, . . . , a N-ring coupled oscillator300-N. In response to receiving a control signal indicating L number of coupled rings, the ring oscillator300may select the L-ring coupled oscillator300-L among the N ring oscillators. The implementation of single ring oscillator instance (as shown inFIG.2AtoFIG.2B) can compromise performance for area saving, while the implementation of separate ring oscillator instances (as shown inFIG.3) can sacrifice some extra area for better performance.

FIG.4is a schematic block diagram of a device400(e.g., multi-mode ADC) for operating an ADC in multiple modes using one or more ring oscillators420, in accordance with an embodiment. Referring toFIG.4, the multi-mode ADC400may include a ring oscillator420(e.g., VCRO), sampling circuitry440, conversion circuitry460, and/or control circuitry450. In some embodiments, the control circuitry450may receive, as control inputs, a number of coupled rings in the ring oscillator (L)402, a number of phase outputs from the ring oscillator (Nϕ)403, and an ADC sampling frequency (fs)404to scale the power consumption of the ADC for different bandwidth requirements and/or dynamic range requirements.

In some embodiments, the ring oscillator420may include N number of rings and may be configure/adjust one or more rings, among the N number of rings, to be cyclically coupled (in a manner shown inFIG.2AtoFIG.2C). In some embodiments, the ring oscillator420may N ring oscillators which include a single-ring oscillator, a dual-ring coupled oscillator, a 3-ring coupled oscillator, . . . , a N-ring coupled oscillator (as shown inFIG.3), and may select one of the N ring oscillators. In response to receiving the number of coupled rings L and the number of phase outputs Nϕ, the multi-mode ADC400(or the control circuitry450thereof) may configure/control, via a control signal451, the ring oscillator420to use L number of coupled rings to output Nϕnumber of phase outputs421(ϕ<Nϕ−1:0>). The ring oscillator420may receive an input voltage Vin401and output phase outputs421to the sampling circuitry440. In some embodiments, each of the Nϕnumber of phase outputs421may be obtained/generated/outputted from an output of a differential amplifier of the L number of coupled rings.

In some embodiments, the control circuitry450may generate a clock signal452according to the sampling frequency (fs)404and provide the clock signal452to the sampling circuitry440(e.g., sampling D flip-flops (DFFs)422) and the conversion circuitry460so that the sampling circuitry440and the conversion circuitry460operate according to the sampling frequency (fs).

In some embodiments, the sampling circuitry440may receive the Nϕnumber of phase outputs421(e.g., ϕ<Nϕ−1:0>) and output Nϕnumber of sampled phase outputs447. In some embodiments, the sampling circuitry440may include a counter441configured to output K number of bits443(e.g., c<K−1:0>), and a plurality of sampling DFFs442. In response to receiving a first phase output443(e.g., ϕ<0>) (among the Nϕnumber of phase outputs421) from the ring oscillator420, the counter441may be configured to count a number of cycles in the first phase output (e.g., sine wave signal or square wave signal) and output the number of cycles in K number of bit (e.g., c<K−1:0>) as a rate of the original phase data444(before sampling). In response to receiving the Nϕnumber of phase outputs445(e.g., ϕ<Nϕ−1:0>) from the ring oscillator420, the plurality of sampling DFFs442may be configured to sample phase outputs according to the sampling frequency (fs)404and output Nϕnumber of sampled phase data447.

In response to receiving the rate of the original phase data446and sampled phase outputs447, the conversion circuitry460may be configured to convert the sampled phase data447to one or more digital signals and output the one or more digital signals as ADC output405. In this manner, the multi-mode ADC400can improve/reduce phase noises and/or quantization noises of the ADC according to a programmable/selectable number of coupled rings. The multi-mode ADC400can also scale the power consumption of the ADC across all baseband bandwidth (frequency) ranges to meet the bandwidth requirements and/or dynamic range requirements.

In some embodiments, circuitry (e.g., the control circuitry450) may be configured to receive a selection of a number of coupled rings (e.g., number of coupled rings L) and a number of phases (e.g., number of output phases Nϕ). A phase refers to a quantity (e.g., a fraction of the full cycle or an angle in radian) representing a position of a point or signal in time on a cycle of a waveform (e.g., sine waveform, square waveform). The number of output phases Nϕrefers to the number of output signals from a ring oscillator that have different phases from each other. The circuitry (e.g., the control circuitry450) may be configured to configure the multi-ring oscillator420including N number of rings to operate at least based on the number of coupled rings L. The circuitry (e.g., the control circuitry450) may be configured to cause the configured multi-ring oscillator420to output the plurality of signals421(e.g., ϕ<Nϕ−1:0>) having respective phases corresponding to the number of phases No. The circuitry (e.g., the sampling circuitry440, the conversion circuitry460) may be configured to convert the plurality of signals421(e.g., ϕ<Nϕ−1:0>) from the configured multi-ring oscillator420to one or more digital signals (e.g., ADC output405). The circuitry (e.g., the control circuitry450, the sampling circuitry440, the conversion circuitry460) may be configured to receive a selection of a sampling frequency (fs), and convert the plurality of signals421(e.g., ϕ<Nϕ−1:0>) from the configured multi-ring oscillator420to the one or more digital signals at least based on the sampling frequency (fs). The number of coupled rings may be an integer L that is less than or equal to N. In configuring the one or more ring oscillators (e.g., the multi-ring oscillator420), the circuitry may be configured to configure the multi-ring oscillator420to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators.

FIG.5is a diagram500showing noise power (in y-axis) over different frequencies (in x-axis) when using a device (e.g., multi-mode ADC400) for operating an ADC in multiple modes, in accordance with an embodiment.FIG.5shows that as the programmable/selectable number coupled rings L increases (e.g., from a L1-ring VCRO (L=L1) to a L2-ring VCRO (L=L2>L1)), the phase noises and/or quantization noises of the multi-mode ADC400may decrease (see lines511,512).FIG.5also shows that the noise power of the ADC scales for different configurations depending on different bandwidth requirements and/or dynamic range requirements. For example, each of the lines521,522,523,524linearly increases across all bandwidth ranges, while different combinations of programmable/selectable values Nϕand fsin the lines521,522,523,524meet different bandwidth requirements and/or dynamic range requirements. Although not shown inFIG.5, it could be understood that the power consumption of the ADC is proportional to the number of rings, number of phases, and the sampling frequency.

FIG.6is a schematic block diagram of a device600(e.g., multi-mode ADC) for operating an ADC in multiple modes using one or more ring oscillators620, in accordance with an embodiment. Referring toFIG.6, the multi-mode ADC600may include a ring oscillator620(e.g., VCRO), sampling circuitry640, conversion circuitry660, and/or control circuitry650. In some embodiments, the control circuitry650may receive, as control inputs, a number of coupled rings in the ring oscillator (L)602, a number of phase outputs from the ring oscillator (Nϕ)603, and an ADC sampling frequency (fs)604to scale the power consumption of the ADC for different bandwidth requirements and/or dynamic range requirements. The control circuitry650may receive, as control inputs, one or more external mode selection signals605which may indicate selection of one or more mode circuits among a plurality of mode circuits (e.g., P number of mode circuits including a mode-1 circuit670-1, . . . , a mode-P circuit670-P). In some embodiments, the one or more external mode selection signals605may include a plurality of signals corresponding to P number of mode circuits, each signal indicating whether the corresponding mode circuit is selected (e.g., signal indicating value “1”) or not selected (e.g., signal indicating value “0”).

In some embodiments, the ring oscillator620may have a configuration similar to that of the ring oscillator420. In response to receiving the number of coupled rings L and the number of phase outputs Nϕ, the control circuitry650may configure/control, via a control signal651, the ring oscillator620to use L number of coupled rings to output Nϕnumber of phase outputs621. The ring oscillator620may receive an input voltage Vin601and output the Nϕnumber of phase outputs621(e.g., ϕ<Nϕ−1:0>) to the sampling circuitry640. In some embodiments, the control circuitry650may generate a clock signal652according to the sampling frequency (fs)604and provide the clock signal652to the sampling circuitry640and the conversion circuitry660so that the sampling circuitry640and the conversion circuitry660operate according to the sampling frequency (fs). The sampling circuitry640may be configured to sample phase outputs according to the sampling frequency (fs)604and output Nϕnumber of sampled phase data642(e.g., sampled ϕ<Nϕ−1:0>) and the rate of the original phase data641.

In some embodiments, the conversion circuitry660may include a plurality of mode circuits (e.g., P number of mode circuits including a mode-1 circuit670-1, . . . , a mode-P circuit670-P) and selection circuitry680configured to select one or more mode circuits of the plurality of mode circuits. In some embodiments, each of the plurality of mode circuits may include a phase decoder (e.g., phase decoder671-1, . . . ,671-P), one or more differentiators (e.g., differentiator672-1, . . . ,672-P), and/or a decimator (e.g., decimator673-1, . . . ,673-P). The phase decoder (e.g., ϕ-decoder for ithsampled phase ϕ<i−1>) may be configured to map/decode/convert the respective sampled phase (e.g., ithsampled phase ϕ<i−1>) to quantized phases (e.g., as 1-bit stream). The differentiators may be configured to calculate the difference between the current sample and the previous sample, e.g., s[n]−s[n−1]. The decimator may be configured to down-sample the sampled phase data based on the rate of the original phase data641which is output from the sampling circuitry640. In some embodiments, each of the plurality of mode circuits670-1, . . . ,670-P may have different configurations/arrangements of the phase decoder, one or more differentiators, and/or a decimator.

In some embodiments, the control circuitry650may generate one or more internal mode selection signals653according to the one or more external mode selection signals605and provide the one or more internal mode selection signals653to the conversion circuitry660. In some embodiments, the internal mode selection signals653may be the same as the external mode selection signals605, e.g., each of the internal mode selection signals653indicating whether the corresponding mode circuit is selected (e.g., signal indicating value “1”) or not selected (e.g., signal indicating value “0”). The selection circuitry680may include a plurality of AND gates661-1, . . . ,661-P, each receiving the clock signal652and an internal mode selection signal653(corresponding to the respective mode circuit) from the control circuitry650. For example, in response to receiving the clock signal652and an internal mode selection signal653corresponding to the mode-1 circuit and indicating selection of the mode-1 circuit (e.g., indicating value of “1”), the AND gate661-1may be configured to activate/enable the mode-1 circuit670-1such that the selected mode circuit can operate.

In response to receiving the rate of the original phase data641and sampled phase data642from the sampling circuitry640, the selected mode circuits may be configured to operate at least one of a phase decoder (e.g., phase decoder671-1, . . . ,671-P), one or more differentiators (e.g., differentiator672-1, . . . ,672-P), and/or a decimator (e.g., decimator673-1, . . . ,673-P) thereof to convert the sampled phase data642to one or more digital signals, and output the one or more digital signals as ADC output607. In some embodiments, as shown inFIG.6, the phase decoder, differentiators, and decimator can be separately implemented for different modes which can save power in low bandwidth/dynamic range modes at the cost of some extra area. Alternatively, the conversion circuitry may include a single logic block (not shown) that can be configured for different modes, which would save area at the cost of some extra power especially in low bandwidth/dynamic range modes.

In some embodiments, an analog digital converter (e.g., multi-mode ADC600) may include an input (e.g., ADC input601) to receive an analog signal (e.g., Vin), one or more ring oscillators (e.g., ring oscillator620), and circuitry (e.g., control circuitry650, sampling circuitry640, conversion circuitry660). In some embodiments, the one or more ring oscillators may include a plurality of rings (e.g., rings shown inFIG.2AtoFIG.2C, rings shown inFIG.3). The one or more ring oscillators may be configurable to operate at least based on a programmable number of coupled rings of the plurality of rings (e.g., L number of coupled rings602). The circuitry may be coupled to the one or more ring oscillators. The circuitry may be programmable to receive a selection of a number of coupled rings (e.g., L number of coupled rings602) and a number of phases (e.g., Nϕnumber of phases (or phase outputs)603). The circuitry may be programmable to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be programmable to cause the configured one or more ring oscillators to receive the analog signal (e.g., Vin) and output a plurality of signals (e.g., Nϕnumber of sampled phase data642) having respective phases corresponding to the number of phases. The circuitry may be programmable to convert the plurality of signals to one or more digital signals (e.g., ADC output607).

In some embodiments, the circuitry (e.g., control circuitry650) may be configured to receive a selection of a sampling frequency (e.g., sampling frequency fs604). The circuitry (e.g., sampling circuitry640, conversion circuitry660) may be configured to convert the plurality of signals (e.g., Nϕnumber of sampled phase data642) to the one or more digital signals (e.g., ADC_out607) at least based on the sampling frequency. For example, the control circuitry650may generate a clock signal652according to the sampling frequency (fs)604and provide the clock signal652to the sampling circuitry640and the conversion circuitry660so that the sampling circuitry640and the conversion circuitry660operate according to the sampling frequency (fs).

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include a multi-ring oscillator having N rings that are coupled to each other (e.g., coupled in a manner shown inFIG.2AtoFIG.2C). In configuring the one or more ring oscillators, the circuitry may be configured to configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators. For example, in response to receiving from the control circuitry650, the control signal651corresponding to L number of coupled rings, the ring oscillator620including N coupled rings may be configured to recouple the N rings such that only L rings out of N rings are cyclically coupled as shown inFIG.2AtoFIG.2C.

In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include N ring oscillators, each having a different number of coupled rings to each other (e.g., N ring oscillators shown inFIG.3). In configuring the one or more ring oscillators, the circuitry may be configured to select a ring oscillator having L coupled rings, from among the N ring oscillators, as the configured one or more ring oscillators. For example, in response to receiving from the control circuitry650, the control signal651corresponding to L number of coupled rings, the ring oscillator620including N ring oscillators (e.g.,300-1,300-2, . . . ,300-N inFIG.3) may be configured to select the L coupled ring oscillator (e.g.,300-L) out of the N ring oscillators.

In some embodiments, the circuitry (e.g., conversion circuitry660) may include a plurality of circuits (e.g., mode-1 circuit670-1, . . . , mode-P circuit670-P) respectively configured to perform a plurality of modes (e.g., mode-1, . . . , mode-P) of analog digital converter operations. The circuitry may be configured to select one or more circuits from among the plurality of circuits. The circuitry may be configured to cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals. For example, n response to receiving the rate of the original phase data641and sampled phase data642from the sampling circuitry640, the selected mode circuits may be configured to operate at least one of a phase decoder (e.g., phase decoder671-1, . . . ,671-P), one or more differentiators (e.g., differentiator672-1, . . . ,672-P), and/or a decimator (e.g., decimator673-1, . . . ,673-P) thereof to convert the sampled phase data642to one or more digital signals, and output the one or more digital signals as ADC output607.

FIG.7is a flow diagram showing a process700for operating an ADC in multiple modes using one or more ring oscillators, in accordance with an embodiment. In some embodiments, the process700is performed by a device, circuitry, or an ADC (e.g., device100,400,600). In other embodiments, the process700is performed by other entities. In some embodiments, the process700includes more, fewer, or different steps than shown inFIG.7.

At step702, the device (e.g., multi-mode ADC600) may receive a selection of a number of coupled rings (e.g., L number of coupled rings602) and a number of phases (e.g., Nϕnumber of phases (or phase outputs)603).

At step704, the device may configure one or more ring oscillators (e.g., ring oscillator620) to operate at least based on the number of coupled rings (e.g., L number of coupled rings602). The one or more ring oscillators may include a plurality of rings (e.g., N number of rings). In some embodiments, the number of coupled rings may be an integer L that is less than or equal to an integer N. The one or more ring oscillators may include a multi-ring oscillator having N rings that are coupled to each other (e.g., N rings may be cyclically coupled in a manner shown inFIG.2AtoFIG.2C). In configuring the one or more ring oscillators, the circuitry may configure the multi-ring oscillator to operate with L coupled rings out of the N coupled rings, as the configured one or more ring oscillators. In some embodiments, the one or more ring oscillators may be N ring oscillators, each having a different number of coupled rings to each other. For example, in response to receiving from the control circuitry650, the control signal651corresponding to L number of coupled rings, the ring oscillator620including N coupled rings may be configured to recouple the N rings such that only L rings out of N rings are cyclically coupled as shown inFIG.2AtoFIG.2C.

In some embodiments, in configuring the one or more ring oscillators, the circuitry may select a ring oscillator having L coupled rings, from among the N ring oscillators, as the configured one or more ring oscillators. For example, in response to receiving from the control circuitry650, the control signal651corresponding to L number of coupled rings, the ring oscillator620including N ring oscillators (e.g.,300-1,300-2, . . . ,300-N inFIG.3) may be configured to select the L coupled ring oscillator (e.g.,300-L) out of the N ring oscillators.

At step706, the device may cause the configured one or more ring oscillators to receive an input signal (e.g., Vinas ADC input601), and output a plurality of signals (e.g., Nϕnumber of phase outputs621) having respective phases corresponding to the number of phases (e.g., ϕ<Nϕ−1:0>). In some embodiments, the input signal may be an analog voltage signal, an analog current signal, radio waves, sound waves, or any signal or physical quantity that continuously and infinitely varies in accordance with some time-varying parameter. In some embodiments, the output signals from the ring oscillators may be a plurality of signals that have periodic waveforms (e.g., sine waveform, square waveform).

At step708, the device may convert the plurality of signals (e.g., Nϕnumber of phase outputs621, or Nϕnumber of sampled phase data642) to one or more digital signals (e.g., ADC_out607). In some embodiments, the one or more digital signals may include digital voltage signals, digital current signals, or any signals that represent a sequence of discrete values. In some embodiments, the circuitry may receive a selection of a sampling frequency (e.g. sampling frequency fs604). The circuitry (e.g., sampling circuitry640, conversion circuitry660) may convert the plurality of signals (e.g., Nϕnumber of sampled phase data642) to the one or more digital signals (e.g., ADC_out607) at least based on the sampling frequency. For example, the control circuitry650may generate a clock signal652according to the sampling frequency (fs)604and provide the clock signal652to the sampling circuitry640and the conversion circuitry660so that the sampling circuitry640and the conversion circuitry660operate according to the sampling frequency (fs).

In some embodiments, the circuitry (e.g., conversion circuitry660) may include a plurality of circuits (e.g., mode-1 circuit670-1, . . . , mode-P circuit670-P) respectively configured to perform a plurality of modes (e.g., mode-1, . . . , mode-P) of analog digital converter operations. The circuitry may select one or more circuits from among the plurality of circuits. The circuitry may cause the selected one or more circuits to convert the plurality of signals to the one or more digital signals. For example, n response to receiving the rate of the original phase data641and sampled phase data642from the sampling circuitry640, the selected mode circuits may be configured to operate at least one of a phase decoder (e.g., phase decoder671-1, . . . ,671-P), one or more differentiators (e.g., differentiator672-1, . . . ,672-P), and/or a decimator (e.g., decimator673-1, . . . ,673-P) thereof to convert the sampled phase data642to one or more digital signals, and output the one or more digital signals as ADC output607.

The term “coupled” and variations thereof includes the joining of two members directly or indirectly to one another. The term “electrically coupled” and variations thereof includes the joining of two members directly or indirectly to one another through conductive materials (e.g., metal or copper traces). Such joining may be stationary (e.g., permanent or fixed) or moveable (e.g., removable or releasable). Such joining may be achieved with the two members coupled directly with or to each other, with the two members coupled with each other using a separate intervening member and any additional intermediate members coupled with one another, or with the two members coupled with each other using an intervening member that is integrally formed as a single unitary body with one of the two members. If “coupled” or variations thereof are modified by an additional term (e.g., directly coupled), the generic definition of “coupled” provided above is modified by the plain language meaning of the additional term (e.g., “directly coupled” means the joining of two members without any separate intervening member), resulting in a narrower definition than the generic definition of “coupled” provided above. Such coupling may be mechanical, electrical, or fluidic.

It should be noted that certain passages of this disclosure can reference terms such as “first” and “second” in connection with subsets of transmit spatial streams, sounding frames, response, and devices, for purposes of identifying or differentiating one from another or from others. These terms are not intended to merely relate entities (e.g., a first device and a second device) temporally or according to a sequence, although in some cases, these entities can include such a relationship. Nor do these terms limit the number of possible entities that can operate within a system or environment. It should be understood that the systems described above can provide multiple ones of any or each of those components and these components can be provided on either a standalone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above can be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture, e.g., a floppy disk, a hard disk, a CD-ROM, a flash memory card, a PROM, a RAM, a ROM, or a magnetic tape. The programs can be implemented in any programming language, such as LISP, PERL, C, C++, C#, or in any byte code language such as JAVA. The software programs or executable instructions can be stored on or in one or more articles of manufacture as object code. In some embodiments, the ADC is employed as an integrated circuit in a transmitter for wireless communication. The ADC is provided on an integrated circuit that includes the calibration engine. The ADC and calibration engine are provided in a single chip or multichip integrated package in some embodiments.

While the foregoing written description of the methods and systems enables one of ordinary skill to make and use embodiments thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The present methods and systems should therefore not be limited by the above-described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the disclosure.