Adhesive wafer bonding with controlled thickness variation

A method and structure for forming an array of micro devices is disclosed. An array of micro devices is formed over an array of stabilization posts included in a stabilization layer. The stabilization layer is bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface of the carrier substrate.

BACKGROUND

The present invention relates to micro devices. More particularly embodiments of the present invention relate to the stabilization of micro devices on a carrier substrate.

2. Background Information

Commercial manufacturing and packaging of micro devices often becomes more challenging as the scale of the micro devices decreases. Some examples of micro devices include radio frequency (RF) microelectromechanical systems (MEMS) microswitches, light-emitting diode (LED) display systems, and MEMS or quartz-based oscillators.

During fabrication of active devices, it is common to include bonding together two wafers or substrates. For example, a growth substrate may be bonded with a carrier substrate to position the device structure on a different wafer or substrate in order to perform processing operations on an alternate side of the micro device structure. The growth substrate may also be bonded with a carrier substrate because the carrier substrate is better suited to continue on in the fabrication process.

To bond one substrate/wafer to another, an adhesive bonding material may be applied as an adhesive layer between the two substrates. A wafer bonding fixture may be used to facilitate the process. The wafer bonding fixture may assist on exerting a controlled amount of pressure on the two wafers to encourage a close and uniform bonding of the two wafers. In some instances, the wafers to be bonded have alignment marks to promote a uniform bonding distance between the two wafers. In addition, the wafer bonding fixture may include fixture spacers positioned around the circumference of the two wafers in order to determine a thickness of the adhesive bonding material, and consequently, the spacing between the two wafers.

SUMMARY OF THE INVENTION

A structure and method of forming an array of micro devices which are poised for pick up are disclosed. In an embodiment, a structure include a stabilization layer including an array of stabilization posts. In an embodiment, the stabilization layer is formed of a thermoset material such as epoxy or benzocyclobutene (BCB) which is associated with 10% or less volume shrinkage during curing. An array of micro devices are formed over the array of stabilization posts. The structure includes a carrier substrate that includes raised spacers extending from a spacer-side surface of the carrier substrate. The raised spacers extend into the stabilization layer to meet a subset of the stabilization posts in the array of stabilization posts. In an embodiment the array of stabilization posts are separated by a pitch of 1 μm to 100 μm, or more specifically 1 μm to 10 μm. The array of micro devices may be micro LED devices, and may be designed to emit a specific wavelength such as a red, green, or blue light. In an embodiment, each micro LED device includes a device layer formed of a p-doped semiconductor layer, one or more quantum well layers over the p-doped semiconductor layer, and an n-doped semiconductor layer. For example, where the micro LED device is designed to emit a green or blue light, the p-doped layer may comprise GaN and the n-doped layer may also comprise GaN.

In one embodiment, a device layer is patterned to form an array of micro device mesa structures over a handle substrate. A patterned sacrificial layer including an array of openings is then formed over the array of micro device mesa structures. A stabilization layer can then be formed over the patterned sacrificial layer and within the array of openings. The stabilization layer is bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface. An adhesion promoter layer may be formed between the carrier substrate and the stabilization layer to increase adhesion.

In one embodiment, a patterned sacrificial layer including an array of openings is formed over a device layer. A stabilization layer is then formed over the patterned sacrificial layer and within the array of openings. The stabilization layer may be bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface. After bonding the stabilization layer to the spacer side of the carrier substrate, the device layer may be patterned to form the array of micro devices.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention describe a method and structure for stabilizing an array of micro devices such as micro light emitting diode (LED) devices and micro chips on a carrier substrate having raised spacers so that they are poised for pick up and transfer to a receiving substrate. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. While embodiments of some of the present invention are described with specific regard to micro LED devices comprising p-n diodes, it is to be appreciated that embodiments of the invention are not so limited and that certain embodiments may also be applicable to other micro semiconductor devices which are designed in such a way so as to perform a predetermined electronic function (e.g. diode, transistor, integrated circuit) or photonic function (LED, laser). Other embodiments of the present invention are described with specific regard to micro devices including circuitry. For example, the micro devices may be based on silicon or SOI wafers for logic or memory applications, or based on GaAs wafers for RF communications applications.

The terms “micro” device, “micro” LED device, or “micro” chip as used herein may refer to the descriptive size of certain devices, devices, or structures in accordance with embodiments of the invention. As used herein the term “micro device” specifically includes “micro LED device” and “micro chip”. As used herein, the terms “micro” devices or structures may refer to the scale of 1 to 100 μm. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller “micro” device or structure size scales. In an embodiment, a single micro device in an array of micro devices, and a single electrostatic transfer head in an array of electrostatic transfer heads both have a maximum dimension, for example length or width, of 1 to 100 μm. In an embodiment, the top contact surface of each micro device or electrostatic transfer head has a maximum dimension of 1 to 100 μm, or more specifically 3 to 20 μm. In an embodiment, a pitch of an array of micro devices, and a corresponding array of electrostatic transfer heads is (1 to 100 μm) by (1 to 100 μm), for example a 20 μm by 20 μm pitch or 5 μm by 5 μm pitch.

In the following embodiments, the mass transfer of an array of pre-fabricated micro devices with an array of transfer heads is described. For example, the pre-fabricated micro devices may have a specific functionality such as, but not limited to, an LED for light-emission, silicon IC for logic and memory, and gallium arsenide (GaAs) circuits for radio frequency (RF) communications. In some embodiments, arrays of micro LED devices which are poised for pick up are described as having a 20 μm by 20 μm pitch, or 5 μm by 5 μm pitch. At these densities, a 6 inch substrate, for example, can accommodate approximately 165 million micro LED devices with a 10 μm by 10 μm pitch, or approximately 660 million micro LED devices with a 5 μm by 5 μm pitch. A transfer tool including an array of transfer heads matching an integer multiple of the pitch of the corresponding array of micro LED devices can be used to pick up and transfer the array of micro LED devices to a receiving substrate. In this manner, it is possible to integrate and assemble micro LED devices into heterogeneously integrated systems, including substrates of any size ranging from micro displays to large area displays, and at high transfer rates. For example, a 1 cm by 1 cm array of micro device transfer heads can pick up and transfer more than 100,000 micro devices, with larger arrays of micro device transfer heads being capable of transferring more micro devices.

In one aspect, embodiments of the invention describe a structure for stabilizing an array of micro devices such as micro light emitting diode (LED) devices on a carrier substrate having raised spacers so that they are poised for pick up and transfer to a receiving substrate. In an embodiment, an array of micro devices are held in place on an array of stabilization posts on a carrier substrate having raised spacers. In an embodiment, the stabilization posts are formed of an adhesive bonding material. In this manner, the array of stabilization posts may retain the array of micro devices in place on a carrier substrate while also providing a structure from which the array of micro devices are readily picked up. In an embodiment, the adhesive bonding material includes a thermoset material such as, but not limited to, benzocyclobutene (BCB) or epoxy. In an embodiment, the thermoset material may be associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing. In this manner low volume shrinkage during curing of the adhesive bonding material may not cause delamination between the array of stabilization posts and the array of micro devices, and may allow for uniform adhesion between the array stabilization posts and the array of micro devices supported by the array of stabilization posts.

In one aspect of embodiments of the invention, a carrier substrate includes raised spacers to increase the planarity of the micro devices that are poised for pick up. It has been observed that the thickness of an adhesive bond layer between two wafers bonded using a conventional adhesive bonding fixture can be non-uniform across the area between the two bonded wafers, despite the use of alignment marks when aligning the two wafers, starting with substantially flat wafers and the use of fixture spacers between the two wafers around the circumference of the wafers. In one scenario, it was observed that when bonding an unpatterned GaN device layer ofFIG. 1Adescribed below to a silicon carrier substrate with an BCB adhesive bonding layer of approximately 2 μm thickness, the thickness of the final cured adhesive bonding layer was measured as being in the range between 1.5-9 μm across the carrier substrate. It is believed that the resultant non-uniformity in thickness of the adhesive bonding material (referred to as a stabilization layer in this disclosure below) may be attributed to factors such as particulate contamination, wafer bowing, and local stresses within the wafers. For example, wafer bowing of a sapphire growth substrate supporting an epitaxially grown GaN device layer may be from 50-100 μm in some instances. While the thickness of the GaN device layer remained constant across the substrate, the thickness variation profile of the BCB adhesive bonding material was found to be translated to the GaN device layer surface profiles. Since the micro devices that are formed from the device layer and the transfer heads that transfer the micro devices in accordance with embodiments of the invention may be of the “micro” scale, increasing the planarity of the micro devices with respect to each other and with respect to their carrier substrate may increase the yield of successful transfers of the micro devices from their carrier substrate to a target substrate. During an adhesive bonding operation of the stabilization layer and the carrier substrate, the raised spacers included in the carrier substrate can extend through the stabilization layer to a more solid structure (e.g. an oxide sacrificial layer) which results in a more uniform thickness of the stabilization layer. With the raised spacers causing a more uniform thickness in the stabilization layer, the micro devices also have a more planar relationship to each other as they more closely conform to the carrier substrate rather than following a curvature of a bowed handle substrate. As a result, the micro devices have an improved planar positioning across the carrier substrate and the height variation of the top surfaces of the micro devices is reduced, promoting a more consistent pick-up location of the micro devices for successful transfer by the electrostatic transfer heads. Furthermore, the raised spacers can be sized to control the thickness of the stabilization layer to be close to a desired dimension.

In one aspect of embodiments of the invention, the array of micro devices are formed in a one-sided process sequence in which a device layer is etched to form an array of micro device mesa structures prior to applying a stabilization layer (the stabilization layer having the adhesive bonding material that forms the stabilization posts). In one aspect of embodiments of the invention, the array of micro devices are formed in a two-sided process in which a device layer is patterned into micro devices after bonding to a stabilization layer that form the stabilization posts. Suitability of a one-sided process or two-sided process may depend upon the system requirement, and materials being used. For example, where the micro devices are micro LED devices, the devices layers may be formed from different materials selected for different emission spectra. By way of example, a blue-emitting or green-emitting micro LED device may be formed of a GaN (5.18 Å lattice constant) based material grown on a sapphire substrate (4.76 Å lattice constant), resulting in a lattice mismatch of approximately 0.42 Å. By way of comparison, a red-emitting micro LED device may be formed of a GaP (5.45 Å lattice constant) based material grown on a GaAs substrate (5.65 Å lattice constant), resulting in a lattice mismatch of approximately 0.2 Å. An increased amount of lattice mismatch between a device layer grown on a growth substrate may result in a greater amount of stress in the device layer. In the above exemplary growth systems, a blue-emitting or green-emitting device layer may have a greater amount of intrinsic stress than a red-emitting device layer.

It has been observed that when fabricating devices at the “micro” scale, stress in a device layer may cause the device layer to shift laterally upon removal of a growth substrate that the device layer is grown upon. This stress may potentially cause misalignment between the array of micro devices that are formed over an array of stabilization posts. In accordance with embodiments of the invention, and in particular when lattice mismatch between the device layer and growth substrate is greater than approximately 0.2 Å, a one-sided process sequence is performed in order to reduce the amount of shifting between the micro devices and stabilization posts by forming micro device mesa structures on stabilization posts prior to removing the growth substrate. However, when the lattice mismatch is less than or equal to 0.2 Å, stress in the device layer may be low enough that it is not an overriding concern and a two-sided process may be more efficient for fabricating the micro devices. As will become more apparent in the following description, the two-sided process allows for accurate alignment of the stabilization posts and bottom contacts of the micro devices.

Without being limited to a particular theory, embodiments of the invention utilize transfer heads and head arrays which operate in accordance with principles of electrostatic grippers, using the attraction of opposite charges to pick up micro devices. In accordance with embodiments of the present invention, a pull-in voltage is applied to a transfer head in order to generate a grip pressure on a micro device and pick up the micro device. In accordance with embodiments of the invention, the minimum amount pick up pressure required to pick up a micro device from a stabilization post can be determined by the adhesion strength between the adhesive bonding material from which the stabilization posts are formed and the micro device (or any intermediate layer), as well as the contact area between the top surface of the stabilization post and the micro device. For example, adhesion strength which must be overcome to pick up a micro device is related to the minimum pick up pressure generated by a transfer head as provided in equation (1):
P1A1=P2A2(1)

where P1is the minimum grip pressure required to be generated by a transfer head, A1is the contact area between a transfer head contact surface and micro device contact surface, A2is the contact area on a top surface of a stabilization post, and P2is the adhesion strength on the top surface of a stabilization post. In an embodiment, a grip pressure of greater than 1 atmosphere is generated by a transfer head. For example, each transfer head may generate a grip pressure of 2 atmospheres or greater, or even 20 atmospheres or greater without shorting due to dielectric breakdown of the transfer heads. Due to the smaller area, a higher pressure is realized at the top surface of the corresponding stabilization post than the grip pressure generate by a transfer head. In an embodiment, a bonding layer is placed between each micro device and stabilization post in order to aid in bonding each micro device to a receiving substrate. A variety of different bonding layers with different melting temperatures are compatible with embodiments of the invention. For example, heat may or may not be applied to the transfer head assembly, carrier substrate, and/or receiving substrate during the pick up, transfer, and bonding operations. In some embodiments, the bonding layer may be a comparatively higher melting temperature material such as gold. In some embodiments the bonding layer is a comparatively lower melting temperature material such as indium. In some embodiments, the transfer head assembly may be maintained at an elevated temperature during the pick up and transfer operations in order to assist bonding to the receiving substrate without thermal cycling of the transfer head assembly. In one embodiment, the bonding layer is gold, and the bonding layer is not liquefied during the pick up or transfer operations. In one embodiment the bonding layer is indium, and the bonding layer is liquefied during the pick up and transfer operations. In such an embodiment, the bonding layer may be partially picked up and transferred to the receiving substrate.

In another embodiment, the bonding layer is formed of a material characterized by a low tensile strength. For example, indium is characterized by a tensile strength of approximately 4 MPa which can be less than or near the adhesion strength between a gold/BCB bonding interface of 10 MPa or less, and which is significantly lower than an exemplary 30 MPa adhesion strength between a gold/BCB bonding interface (determined with stud pull test) when treated with adhesion promoter AP3000, an organosilane compound in 1-methoxy-2-propoanol available from The Dow Chemical Company. In an embodiment, the bonding layer is cleaved during the pick up operation due to the lower tensile strength, and a phase change is not created during the pick up operation. Though, a phase change may still be created in the portion of the bonding layer which is picked up with the micro device during placement of the micro device onto a receiving substrate to aid in bonding of the micro device to the receiving substrate.

In another aspect, embodiments of the invention describe a manner of forming an array of micro devices which are poised for pick up in which conductive contact layers can be formed on top and bottom surfaces of the micro devices, and annealed to provide ohmic contacts. Where a conductive contact is formed on a top surface of a micro device, the stabilization layer is formed of a material which is capable of withstanding the associated deposition and annealing temperatures. For example, a conductive contact may require annealing at temperatures between 200° C. to 350° C. to form an ohmic contact with the micro device. In this manner, embodiments of the invention may be utilized to form arrays of micro LED devices based upon a variety of different semiconductor compositions for emitting various different visible wavelengths. For example, micro LED growth substrates including active devices layers formed of different materials for emitting different wavelengths (e.g. red, green, and blue wavelengths) can all be processed within the general sequence of operations of the embodiments.

In the following description exemplary processing sequences are described for using a carrier substrate with raised spacers to fabricate an array of micro devices on an array of stabilization posts. Specifically, exemplary processing sequences are described for fabricating an array of micro LED devices and an array of micro chips on an array of stabilization posts. Where possible, similar features are illustrated with similar annotations in the figures and following description.

FIG. 1Ais an example cross-sectional side view illustration of a bulk LED substrate100in accordance with an embodiment of the invention. In the illustrated embodiment, bulk LED substrate100includes a growth substrate102, an epitaxial growth layer103, and a device layer105. In an embodiment, growth substrate102is sapphire and may be approximately 500 μm thick. Using a sapphire growth substrate may correspond with manufacturing blue emitting LED devices (e.g. 450-495 nm wavelength) or green emitting LED devices (e.g. 495-570 nm wavelength). It is to be appreciated, that while the specific embodiments illustrated and described in the following description may be directed to formation of green or blue emitting LED devices, the following sequences and descriptions are also applicable to the formation of LED devices that emit wavelengths other than blue and green. Epitaxial growth layer103may be grown on growth substrate102using known epitaxial growth techniques. Epitaxial growth layer103may be grown on growth substrate102at a relatively high temperature to facilitate gliding out dislocations in the layer. In an embodiment, epitaxial growth layer103is a gallium nitride (GaN) based material.

Device layer105may be formed on epitaxial growth layer103, as shown inFIG. 1A. In an embodiment the growth substrate102is approximately 200 μm thick. The epitaxial growth layer103may be any suitable thickness such as between 300 Å-5 μm. In the illustrated embodiment, device layer105includes layers for forming LED devices. InFIG. 1A, a zoomed-in view of an example device layer105illustrates one or more quantum well layers110between doped semiconductor layer108(e.g. n-doped) and doped semiconductor layer112(e.g. p-doped), although the doping of layers108and112may be reversed. In an embodiment, doped semiconductor layer108is formed of GaN and is approximately 0.1 μm to 3 μm thick. The one or more quantum well layers110may have a thickness of approximately 0.5 μm. In an embodiment, doped semiconductor layer112is formed of GaN, and is approximately 0.1 μm to 2 μm thick.

FIG. 1Bis a cross-sectional side view illustration of a device wafer180including circuitry in accordance with an embodiment of the invention. In accordance with embodiments of the invention, the device wafer180may be formed of a variety of materials depending upon the desired function. For example, in an embodiment, the device wafer180is a silicon wafer, or silicon-on-insulator (SOI) wafer for logic or memory. In an embodiment, the device wafer180is a gallium arsenide (GaAs) wafer for radio frequency (RF) communications. These are merely examples, and embodiments of the invention envision are not limited to silicon or GaAs wafers, nor are embodiments limited to logic, memory, or RF communications.

In an embodiment, the device wafer180includes an active device layer185, optional buried oxide layer184, and base substrate182. In the interest of clarity, the following description is made with regard to an SOI device wafer180, including an active device layer185, buried oxide layer184, and base silicon substrate182, though other types of devices wafers may be used, including bulk semiconductor wafers. In an embodiment, the active device layer185may include working circuitry to control one or more LED devices. In some embodiments, back-end processing may be performed within the active device layer185. Accordingly, in an embodiment, the active device layer185includes an active silicon layer187including devices such as transistors, metal build-up layers188including interconnects189, bonding pads190, and passivation192.

In the interest of clarity, the portion of the disclosure associated withFIGS. 2A-11Cis made with regard to the bulk LED substrate ofFIG. 1A. However, it is appreciated that the process sequences in the following description may be used to fabricate other micro devices. For example, micro chips may be similarly manufactured by substituting bulk LED substrate100with device wafer180and using the same or similar processes as described with reference to bulk LED substrate100. Accordingly, in the following description, both the growth substrate102and base substrate182can alternatively be referred to more generically as a “handle” substrate so as to not preclude the processing sequence on a growth substrate102from being applied to the processing sequence on a base substrate182.

FIG. 2Ais a cross-sectional side view illustration of a patterned conductive contact layer on bulk LED substrate100in accordance with an embodiment of the invention. A conductive contact layer may be formed over device layer105using a suitable technique such as sputtering or electron beam physical deposition followed by etching or liftoff to form the array of conductive contacts120. In an embodiment, the array of conductive contacts120have a thickness of approximately 0.1 μm-2 μm, and may include a plurality of different layers. For example, a conductive contact120may include an electrode layer121for ohmic contact, a mirror layer122, an adhesion/barrier layer123, a diffusion barrier layer124, and a bonding layer125. In an embodiment, electrode layer121may make ohmic contact to a p-doped semiconductor layer112, and may be formed of a high work-function metal such as nickel. In an embodiment, a minor layer122such as silver is formed over the electrode layer121to reflect the transmission of the visible wavelength. In an embodiment, titanium is used as an adhesion/barrier layer123, and platinum is used as a diffusion barrier124to bonding layer125. Bonding layer125may be formed of a variety of materials which can be chosen for bonding to the receiving substrate and/or to achieve the requisite tensile strength or adhesion or surface tension with the stabilization posts (yet to be formed). Following the formation of layers121-125, the substrate stack can be annealed to form an ohmic contact. For example, a p-side ohmic contact may be formed by annealing the substrate stack at 510° C. for 10 minutes.

In an embodiment, bonding layer125is formed of a conductive material (both pure metals and alloys) which can diffuse with a metal forming a contact pad on a receiving substrate (e.g. gold, indium, or tin contact pad) and has a liquidus temperature above 200° C. such as tin (231.9° C.) or bismuth (271.4° C.), or a liquidus temperature above 300° C. such as gold (1064° C.) or silver (962° C.). In some embodiments, bonding layer125such as gold may be selected for its poor adhesion with the adhesive bonding material used to form the stabilization posts. For example, noble metals such as gold are known to achieve poor adhesion with BCB. In this manner, sufficient adhesion is created to maintain the array of micro LED devices on the stabilization posts during processing and handling, as well as to maintain adjacent micro LED devices in place when another micro LED device is being picked up, yet also not create too much adhesion so that pick up can be achieved with an applied pick up pressure on the transfer head of 20 atmospheres or less, or more particularly 5-10 atmospheres.

In the embodiment illustrated inFIG. 2A, where bonding layer125has a liquidus temperature above the annealing temperature for forming the p-side ohmic contact, the anneal (e.g. 510° C. for 10 minutes) can be performed after the formation of the patterned conductive contact layer120, including bonding layer125. Where bonding layer125has a liquidus temperature below the annealing temperature for forming the p-side ohmic contact, the bonding layer125may be formed after annealing.

FIG. 2Bis a cross-sectional side view illustration of a patterned conductive contact layer on a bulk LED substrate100in accordance with an embodiment of the invention. The embodiment illustrated inFIG. 2Bmay be particularly useful where bonding layer125is formed of a material with a liquidus temperature below the annealing temperature of the p-side ohmic contact, though the embodiment illustrated inFIG. 2Bis not limited to such and may be used where the bonding layer125is formed of a material with a liquidus temperature above the annealing temperature of the p-side ohmic contact. In such embodiments, electrode layer121and minor layer122may be formed similarly as described with regard toFIG. 2A. Likewise, adhesion/barrier layer123and diffusion barrier124may be formed similarly as described with regard toFIG. 2Awith one difference being that the layers123and124may optionally wrap around the sidewalls of the layers121and122. Following the formation of layers121-124, the substrate stack can be annealed to form an ohmic contact. For example, a p-side ohmic contact may be formed by annealing the substrate stack at 510° C. for 10 minutes. After annealing layers121-124to form the p-side ohmic contact, the bonding layer125may be formed. In an embodiment, the bonding layer125has a smaller width than for layers121-124.

In an embodiment, bonding layer125has a liquidus temperature or melting temperature of approximately 350° C. or lower, or more specifically of approximately 200° C. or lower. At such temperatures the bonding layer may undergo a phase change without substantially affecting the other components of the micro LED device. In an embodiment, the resultant bonding layer may be electrically conductive. In accordance with some embodiments, the bonding layer125may be a solder material, such as an indium, bismuth, or tin based solder, including pure metals and metal alloys. In a particular embodiment, the bonding layer125is indium.

FIG. 3is a cross-sectional side view illustration of device layer105patterned to form an array of micro device mesa structures127over a handle substrate that includes growth substrate102and epitaxial growth layer103in accordance with an embodiment of the invention. Etching of layers108,110, and112of device layer105may be accomplished using suitable etch chemistries for the particular materials. For example, n-doped semiconductor layer108, quantum well layer(s)110, and p-doped layer112may be dry etched in one operation with a BCl3and Cl2chemistry. AsFIG. 3illustrates, device layer105may not be etched completely through which leaves unremoved portions129of device layer105that connect the micro device mesa structures127. In one example, the etching of device layer105is stopped in n-doped semiconductor layer108(which may be n-doped GaN). A height of the micro device mesa structures127(not including the thickness of the unremoved portions129may correspond substantially to the height of the laterally separate micro devices to be formed. In accordance with embodiments of the invention, the device layer105may alternatively be completely etched through. For example, where the bulk LED substrate100is replaced with a device wafer180in the processing sequence, etching may stop on the buried oxide layer184.

FIG. 4is a cross-sectional side view illustration of an adhesion promoter layer144and a sacrificial layer135including an array of openings133formed over the array of micro device mesa structures127in accordance with an embodiment of the invention. In an embodiment, sacrificial layer135is between approximately 0.5 and 2 microns thick. In an embodiment, sacrificial layer135is formed of an oxide (e.g. SiO2) or nitride (e.g. SiNx), though other materials may be used which can be selectively removed with respect to the other layers. In an embodiment, sacrificial layer135is deposited by sputtering, low temperature plasma enhanced chemical vapor deposition (PECVD), or electron beam evaporation to create a low quality layer, which may be more easily removed than a higher quality layer deposited by other methods such as atomic layer deposition (ALD) or high temperature PECVD.

Still referring toFIG. 4, after the formation of sacrificial layer135, an adhesion promoter layer144may optionally be formed in order to increase adhesion of the stabilization layer145(not yet formed) to the sacrificial layer135. A thickness of 100-300 angstroms may be sufficient to increase adhesion.

Specific metals that have good adhesion to both the sacrificial layer135and a BCB stabilization layer (not yet formed) include, but are not limited to, titanium and chromium. For example, sputtered or evaporated titanium or chromium can achieve an adhesion strength (stud pull) of greater than 40 MPa with BCB.

After forming sacrificial layer135, the sacrificial layer135is patterned to form an array of openings133over the array of conductive contacts120. If adhesion promoter layer144is present, it can also be patterned to form the array of openings133, exposing the array of conductive contacts120as illustrated inFIG. 4. In an example embodiment, a fluorinated chemistry (e.g. HF vapor, or CF4or SF6plasma) is used to etch the SiO2or SiNxsacrificial layer135.FIG. 4illustrates an optional adhesion promoter layer144being patterned with the sacrificial layer135to form openings. In other embodiments an adhesion promoter layer144may optionally be formed after patterning sacrificial layer135to form openings133. In such embodiments, the adhesion promoter layer may be formed within the openings133and on conductive contacts120. This may have the effect of increasing the pull force required to subsequently separate conductive contacts120and stabilization layer145(yet to be formed). In one embodiment, the structure including patterned sacrificial layer135is treated with an adhesion promoter such as AP3000, available from The Dow Chemical Company, in the case of a BCB stabilization layer145in order to condition the underlying structure. AP3000, for example, can be spin coated onto the underlying structure, and soft baked (e.g. 100° C.) or spun dry to remove the solvents prior to applying the stabilization layer145over the patterned sacrificial layer.

As will become more apparent in the following description the height, and length and width of the openings133in the sacrificial layer135correspond to the height, and length and width (area) of the stabilization posts to be formed, and resultantly the adhesion strength that must be overcome to pick up the array of micro devices (e.g. micro LED devices) poised for pick up on the array of stabilization posts. In an embodiment, openings133are formed using lithographic techniques and have a length and width of approximately 1 μm by 1 μm, though the openings may be larger or smaller so long as the openings have a width (or area) that is less than the width (or area) of the conductive contacts120and/or micro LED devices. Furthermore, the height, length and width of the openings131between the sacrificial layer135formed along sidewalls between the micro device mesa structures127will correspond to the height, length and width of the stabilization cavity sidewalls to be formed. Accordingly, increasing the thickness of the sacrificial layer135and the space separating adjacent micro device mesa structures127will have the effect of decreasing the size of the stabilization cavity sidewalls.

FIG. 5is a cross-sectional side view illustration of a stabilization layer145formed over adhesion promoter layer144and sacrificial layer135and within an array of openings133included in sacrificial layer135in accordance with an embodiment of the invention. Stabilization layer145may be formed of an adhesive bonding material. The adhesive bonding material may be a thermosetting material such as benzocyclobutene (BCB) or epoxy. In an embodiment, the thermosetting material may be associated with 10% or less volume shrinkage during curing, or more particularly about 6% or less volume shrinkage during curing so as to not delaminate from the conductive contacts120on the micro device mesa structures127.

In an embodiment, stabilization layer145is spin coated or spray coated over the patterned sacrificial layer135, though other application techniques may be used. For spin coating, the structure may be spun at 5,000 RPM to form the stabilization layer145at a thickness of 2 μm±0.5 μm. Following application of the stabilization layer145, the structure may be pre-baked at between 120 and 200° C. for 10-30 minutes to remove solvents, resulting in a b-staged layer. In an embodiment, the stabilization layer145is thicker than the height of openings131(when present) between micro device mesa structures127. In this manner, the thickness of the stabilization layer filling openings133will become stabilization posts152, the thickness of the stabilization layer filling openings131will become stabilization cavity sidewalls147, and the remainder of the thickness of the stabilization layer145over the filled openings131,133can function to adhesively bond the bulk LED substrate100to a carrier substrate.

FIG. 6is a cross-sectional side view illustration of bringing together (bonding) a carrier substrate160having raised spacers163and micro device mesa structures127formed on a handle substrate in accordance with an embodiment of the invention. Carrier substrate160has a back side164opposite a spacer side165. Spacer side165includes raised spacers163extending away from a spacer-side surface167of carrier substrate160. In one embodiment, raised spacers163are made from the same material (e.g. silicon) as the carrier substrate160. Raised spacers163may be formed using a subtractive process that etches or mills away part of carrier substrate160to make raised spacers163. Raised spacers163could also be of a different material than carrier substrate160and added to carrier substrate160in an additive process. In one example, oxide is added to carrier substrate160to form raised spacers163on carrier substrate160.

FIGS. 7A and 7Billustrate example placements of raised spacers163on example carrier substrates160in accordance with embodiments of the invention.FIGS. 7A and 7Bshow a top view looking down on spacer side165of carrier substrates160. Carrier substrate160may be approximately six inches in diameter and be made of silicon.FIG. 7Ashows raised spacers163arranged in a pattern following concentric circles.FIG. 7Bshows raised spacers163arranged in a rectangular grid pattern. In one embodiment, the height of raised spacers163is 80-90% of a thickness of a stabilization layer145. It is thought that raised spacers163that are taller than stabilization layer163can cause air gaps to form between stabilization layer145and carrier substrate160, yet raised spacers163that are too short may make it difficult to force excess stabilization layer145away. Of course other configurations than those illustrated can be implemented. Additionally, although raised spacers163are illustrated as circular, raised spacers163may also have a rectangular shape, when viewed from a view point that looks down on spacer side165, such as inFIGS. 7A and 7B.

Referring back toFIG. 6, carrier substrate160is bonded to the micro device mesa structures127via the adhesion properties of stabilization layer145. In one embodiment, 1,100 kg of force is applied for between two and three hours to bond carrier substrate160to the micro device mesa structures. Bonding may take place at approximately 200° C. In order to increase adhesion with the stabilization layer145, an adhesion promoter layer162can be applied to the carrier substrate160prior to bonding the bulk LED substrate100to the carrier substrate160similarly as described above with regard to adhesion promoter layer144. Likewise, in addition to, or in alternative to adhesion promoter layer162, an adhesion promoter such as AP3000 may be applied to the surface of the carrier substrate160or adhesion promoter layer162. Alternatively, stabilization layer145can be formed on carrier substrate160prior to bonding the carrier substrate160to the handle substrate. For example, the structure including the patterned sacrificial layer135and micro device mesa structures127can be embossed into an a-staged or b-staged stabilization layer145formed on the carrier substrate160.

Depending upon the particular material of stabilization layer145, stabilization layer145may be thermally cured, or cured with application of UV energy. In an embodiment, stabilization layer145is a-staged or b-staged prior to bonding the carrier substrate to the handle substrate, and is cured at a temperature or temperature profile ranging between 150° C. and 300° C. Where stabilization layer145is formed of BCB, curing temperatures should not exceed approximately 350° C., which represents the temperature at which BCB begins to degrade. In accordance with embodiments including a bonding layer125material characterized by a liquidus temperature (e.g. gold, silver, bismuth) greater than 250° C., full-curing of a BCB stabilization layer145can be achieved in approximately 1 hour or less at a curing temperature between 250° C. and 300° C. Other bonding layer125materials such as Sn (231.9° C.) may require between 10-100 hours to fully cure at temperatures between 200° C. and the 231.9° C. liquidus temperature. In accordance with embodiments including a bonding layer125material characterized by a liquidus temperature below 200° C. (e.g. indium), a BCB stabilization layer145may only be partially cured (e.g. 70% or greater). In such an embodiment the BCB stabilization layer145may be cured at a temperature between 150° C. and the liquidus temperature of the bonding layer (e.g. 156.7° C. for indium) for approximately 100 hours to achieve at least a 70% cure.

Achieving a 100% full cure of the stabilization layer is not required in accordance with embodiments of the invention. More specifically, the stabilization layer145may be cured to a sufficient curing percentage (e.g. 70% or greater for BCB) at which point the stabilization layer145will no longer reflow. Moreover, it has been observed that such partially cured (e.g. 70% or greater) BCB stabilization layer145may possess sufficient adhesion strengths with the carrier substrate160and patterned sacrificial layer135(or any intermediate layer(s)).

FIG. 8is a cross-sectional side view illustration of carrier substrate160bonded to the micro device mesa structures127formed over the handle substrate in accordance with an embodiment of the invention. InFIG. 8, raised spacer163of carrier substrate160has been brought to rest upon sacrificial layer135. In other words, raised spacers163extend into stabilization layer145, meeting at least a subset of stabilization posts152in the structure illustrated inFIG. 8. In the illustrated embodiment, adhesion promoter layer144and162may be disposed between sacrificial layer135and carrier substrate160, but in other embodiments, raised spacer163of carrier substrate160may contact sacrificial layer135.

Since during bonding raised spacer163extends through stabilization layer145to the more solid sacrificial layer135, the planar alignment of micro devices128and uniformity in thickness of the stabilization layer145across the carrier substrate160may improve. The improvement may manifest in comparison to having micro devices128and associated structure “float” atop stabilization layer145without any solid underpinning to carrier substrate160. Since the micro devices and the transfer heads that transfer the micro devices may be of on the μm scale, increasing the planarity of the micro devices with respect to each other and with respect to their carrier substrate160may increase the yield of successful transfers of the micro devices from their carrier substrate to a target substrate. Due to the improved planar positioning of the micro devices, the pick-up location of the micro devices becomes better defined for successful transfer by the electrostatic transfer heads.

FIG. 8also shows that growth substrate102has been removed. When growth substrate102is sapphire, laser lift off (LLO) may be used to remove the sapphire. Removal may be accomplished by other techniques such as grinding and etching, depending upon the material selection of the growth substrate102.

FIG. 9is a cross-sectional side view illustration of the removal of an epitaxial growth layer103and a portion of device layer105in accordance with an embodiment of the invention. The removal of epitaxial growth layer103and a portion of device layer105may be accomplished using one or more of Chemical-Mechanical-Polishing (CMP), dry polishing, or dry etch.FIG. 9illustrates that that unremoved portions129of device layer105that connected the micro device mesa structures127(FIG. 7) are removed inFIG. 9, which leaves laterally separated micro devices128. In an embodiment, removing unremoved portions129of device layer105includes thinning the array of micro device mesa structures127so that an exposed top surface109of each of the laterally separate micro devices128are below an exposed top surface139of patterned sacrificial layer135.

In embodiments where the bulk LED substrate100includes epitaxial growth layer103, a portion of the doped semiconductor layer108adjacent the epitaxial growth layer may also function as a “buffer”. For example, epitaxial growth layer103may or may not be doped, while semiconductor layer108is n-doped. It may be preferred to remove the epitaxial growth layer103using any suitable technique such as wet or dry etching, or CMP, followed by a timed etch of the remainder of the doped semiconductor layer108resulting in the structure illustrated inFIG. 9. In this manner, the thickness of the laterally separate micro devices128is largely determined by the etching operation illustrated inFIG. 3for the formation of the micro device mesa structures127, combined with the timed etch or etch stop detection of the etching operation illustrated inFIG. 9.

InFIG. 9, raised spacer163is shown “covering” an area that is two micro devices128wide. However, in one embodiment, raised spacer163covers an area that is five micro devices128wide, resulting in a total coverage of approximately 25 micro devices128. In one embodiment raised spacers163are circular having a diameter of 60-100 μm. The raised spacers are interspersed on the carrier substrate to cover only a small percentage (e.g. <5%) of the micro devices.

FIGS. 10A-10Bare cross-sectional side view illustrations of patterned conductive contacts175formed over the array of laterally separated micro device128in accordance with an embodiment of the invention.FIGS. 10A and 10Bare substantially similar, with a difference being the arrangement of layers within conductive contacts120.FIG. 10Acorresponds with the conductive contacts120illustrated inFIG. 2AwhileFIG. 10Bcorresponds with the conductive contacts120illustrated inFIG. 2B.

To form conductive contacts175, a conductive contact layer is formed over micro devices128and sacrificial layer135. The conductive contact layer may be formed of a variety of conductive materials including metals, conductive oxides, and conductive polymers. In an embodiment, conductive contacts are formed of a metal or metal alloy. In an embodiment, the conductive contact layer is formed using a suitable technique such as sputtering or electron beam physical deposition. For example, the conductive contact layer may include BeAu metal alloy, or a metal stack of Au/GeAuNi/Au layers. The conductive contact layer can also be a combination of one or more metal layers and a conductive oxide. In an embodiment, after forming the conductive contact layer, the substrate stack is annealed to generate an ohmic contact between the conductive contact layer and the device layer of micro devices128. Where the stabilization layer is formed of BCB, the annealing temperature may be below approximately 350° C., at which point BCB degrades. In an embodiment, annealing is performed between 200° C. and 350° C., or more particularly at approximately 320° C. for approximately 10 minutes. After the conductive contact layer is deposited, it can be patterned and etched to form conductive contacts175, which may be n-metal conductive contacts.

The resultant structures illustrated inFIGS. 10A and 10Bare robust enough for handling and cleaning operations to prepare the substrate structure for subsequent sacrificial layer removal and electrostatic pick up. In an exemplary embodiment where the array of micro devices have a pitch of 5 microns, each micro device may have a minimum width (e.g. along the top surface109) of 4.5 μm, and a separation between adjacent micro devices of 0.5 μm. It is to be appreciated that a pitch of 5 microns is exemplary, and that embodiments of the invention encompass any pitch of 1 to 100 μm as well as larger, and possibly smaller pitches.

FIGS. 10A and 10Billustrate a structure having a stabilization layer145that includes an array of stabilization cavities and an array of stabilization posts152. Each stabilization cavity in the array includes sidewalls147(which may be coated with adhesion promoter layer144) of stabilization layer145that surround stabilization posts152. InFIGS. 10A and 10B, the bottom surface107(having dimension D1) of each micro device128is wider that the corresponding stabilization post152that is directly under the micro device128. InFIGS. 10A and 10B, sacrificial layer135spans along side surfaces106of micro devices128. In the illustrated embodiments, stabilization posts152extend through a thickness of sacrificial layer135and the stabilization cavity sidewalls147of the stabilization layer145are taller than the stabilization posts152. However, in some embodiments, stabilization posts152are taller than the stabilization cavity sidewalls147.

FIG. 11Ais a cross-sectional side view illustration of an array of micro devices128formed on array of stabilization posts152after removal of sacrificial layer135in accordance with an embodiment of the invention. In the embodiments illustrated, sacrificial layer135is removed resulting in an open space177between each micro device128and stabilization layer145. As illustrated, open space177includes the open space below each micro device128and stabilization layer145as well as the open space between each micro device128and stabilization cavity sidewalls147of stabilization layer145. A suitable etching chemistry such as HF vapor, CF4, or SF6plasma may be used to etch the SiO2or SiNxof sacrificial layer135. In an embodiment where raised spacers163are formed of an oxide material, the raised spacers163may be removed along with sacrificial layer135if the etching chemistry for both sacrificial layer135and raised spacers163(formed of oxide) are similar.

After sacrificial layer135is removed, the array of micro devices128on the array of stabilization posts152are supported only by the array of stabilization posts152. At this point, the array of micro devices128are poised for pick up transferring to a target or receiving substrate. After sacrificial layer135is removed leaving only stabilization posts152to support micro devices128, it is possible that a micro device128may shift off of its corresponding stabilization post152. However, in the illustrated embodiment, the stabilization cavity sidewalls147may be advantageously positioned to contain the shifted micro device128within the stabilization cavity. Therefore, even when a micro device128loses adherence to a stabilization post152, it may still be poised for pick up because it is still positioned within an acceptable tolerance (defined by the stabilization cavity) to be transferred to a receiving substrate.

To further illustrate,FIGS. 11B-11Care schematic top view illustrations of example stabilization post152locations relative to a group of micro devices128in accordance with an embodiment of the invention. The cross-sectional side view ofFIG. 11Ais illustrated along line A-A inFIGS. 11B and 11C.FIG. 11Bshows an embodiment where stabilization posts152are centered in the x-y directions relative to a top view illustration of micro devices128.FIG. 11Balso shows how stabilization cavity sidewalls147can function to contain micro devices128, if a micro device128loses adhesion to a stabilization post152.FIG. 11Cis substantially similar toFIG. 11Bexcept that stabilization posts153have replaced stabilization posts152. Stabilization posts153differ from stabilization posts152in that they are not centered in the x-y direction relative to a top view illustration of the micro devices128. Of course, positions of stabilization posts other than the illustrated positions of stabilization posts152and153are possible. In an embodiment, during the pick up operation described below the off-centered stabilization posts153may provide for the creation of a moment when the array of transfer heads contact the array of micro devices in which the micro devices tilt slightly as a result of the applied downward pressure from the array of transfer heads. This slight tilting may aid in overcoming the adhesion strength between the stabilization posts153and the array of micro devices128. Furthermore, such assistance in overcoming the adhesion strength may potentially allow for picking up the array of micro devices with a lower grip pressure. Consequently, this may allow for operation of the array of transfer heads at a lower voltage, and impose less stringent dielectric strength requirements in the dielectric layer covering each transfer head required to achieve the electrostatic grip pressure.

FIGS. 1A-11Chave described a “one-sided process” for the production of micro devices, such as blue-emitting and green-emitting micro LEDs. The device layer used to fabricate blue-emitting and green-emitting LEDs may be under a higher amount of stress than other device layers grown on growth substrates with less lattice mismatch. The one-sided process may reduce shifting between the micro devices128and the stabilization posts152when removing the growth substrate102since the patterning of micro device mesa structures127relieves stress within the device layer105prior to removing the growth substrate102, which may produce high quality micro devices that are also positioned within an acceptable tolerance. In accordance with embodiments of the invention a “two-sided” process may be used to form micro devices, such as red-emitting micro LEDs when intrinsic stress within a device layer is not an overriding factor.FIGS. 12-21illustrate one example of a two-sided process suitable for fabricating red-emitting micro LEDs and LEDs of other color emissions as well.

FIG. 12is a cross-sectional side view illustration of a bulk LED substrate400in accordance with an embodiment of the invention. In the illustrated embodiment, bulk LED substrate400includes a substrate402and a device layer405. In an embodiment, substrate402is gallium arsenide (GaAs) and may be approximately 200-700 μm thick. Device layer405may be formed on substrate402, as shown inFIG. 12. In the illustrated embodiment, device layer405includes layers for forming LED devices. InFIG. 12, a zoomed-in view of an example device layer405illustrates one or more quantum well layers110between doped semiconductor layer108(e.g. n-doped) and doped semiconductor layer112(e.g. p-doped), although the doping of layers108and112may be reversed. It is appreciated that the two-sided process described in association withFIGS. 12-21may be used to fabricate other micro devices. For example, micro chips may be similarly manufactured by substituting device layer405with the active device layer185illustrated inFIG. 1B.

FIG. 13is a cross-sectional side view illustration of a patterned conductive contact layer on bulk LED substrate400in accordance with an embodiment of the invention. A conductive contact layer may be formed over device layer405using a suitable technique such as sputtering or electron beam physical deposition followed by etching or liftoff to form the array of conductive contacts420. Conductive contacts may be formed and have the same properties as described in the different embodiments described in association withFIGS. 2A and 2B.

FIG. 14is a cross-sectional side view illustration of an adhesion promoter layer444and a sacrificial layer435including an array of openings433formed over an array of conductive contacts420in accordance with an embodiment of the invention. In an embodiment, sacrificial layer435is between approximately 0.5 and 2 microns thick. In an embodiment, sacrificial layer435is formed of an oxide (e.g. SiO2) or nitride (e.g. SiNx), though other materials may be used which can be selectively removed with respect to the other layers. In an embodiment, sacrificial layer435is deposited by sputtering, low temperature PECVD, or electron beam evaporation to create a low quality layer, which may be more easily removed than a higher quality layer deposited by other methods such as ALD or high temperature PECVD.

Still referring toFIG. 14, after the formation of sacrificial layer435, an adhesion promoter layer444may optionally be formed in order to increase adhesion of the stabilization layer445(not yet formed) to the sacrificial layer435. A thickness of 100-300 angstroms may be sufficient to increase adhesion.

After forming sacrificial layer435, the sacrificial layer435is patterned to form an array of openings433over the array of conductive contacts420. If adhesion layer444is present, it can also be patterned to form the array of openings433, exposing the array of conductive contacts420as illustrated inFIG. 14. In an example embodiment, a fluorinated chemistry (e.g. HF vapor, or CF4or SF6plasma) is used to etch the SiO2or SiNxsacrificial layer435.FIG. 14illustrates an optional adhesion promoter layer444being patterned with the sacrificial layer435to form openings433. In other embodiments an adhesion promoter layer444may optionally be formed after patterning sacrificial layer435to form openings433. In such embodiments, the adhesion promoter layer may be formed within the openings433and on conductive contacts420. This may have the effect of increasing the pull force required to subsequently separate conductive contacts420and stabilization layer445(yet to be formed). In one embodiment, the structure including patterned sacrificial layer135is treated with an adhesion promoter such as AP3000, available from The Dow Chemical Company, in the case of a BCB stabilization layer445in order to condition the underlying structure. AP3000, for example, can be spin coated onto the underlying structure, and soft baked (e.g. 100° C.) or spun dry to remove the solvents prior to applying the stabilization layer445over the patterned sacrificial layer.

The height, and length and width of the openings433in the sacrificial layer435correspond to the height, and length and width (area) of the stabilization posts452to be formed, and resultantly the adhesion strength that must be overcome to pick up the array of micro devices (e.g. micro LED devices) poised for pick up on the array of stabilization posts. In an embodiment, openings433are formed using lithographic techniques and have a length and width of approximately 1 μm by 1 μm, though the openings may be larger or smaller so long as the openings have a width (or area) that is less than the width (or area) of the conductive contacts420and/or micro LED devices.

FIG. 15is a cross-sectional side view illustration of a stabilization layer445formed over adhesion promoter layer444and sacrificial layer435and within an array of openings433included in sacrificial layer435in accordance with an embodiment of the invention. Stabilization layer445may be formed of an adhesive bonding material. The adhesive bonding material may be a thermosetting material such as benzocyclobutene (BCB) or epoxy.

In an embodiment, stabilization layer445is spin coated or spray coated over the patterned sacrificial layer435, though other application techniques may be used. Following application of the stabilization layer445, the structure may be pre-baked to remove solvents, resulting in a b-staged layer. The thickness of the stabilization layer445filling openings433will become stabilization posts452and the remainder of the thickness of the stabilization layer445can function to adhesively bond the bulk LED substrate400to carrier substrate460, shown inFIG. 16.

In one aspect, the “two-sided process” described with regard toFIGS. 12-21allows for accurate alignment of the stabilization posts452and conductive contacts420. This may be attributed to the sacrificial layer435being planar during patterning to form openings433, which allows for accurate and uniform photoresist development. Accordingly, alignment error can be reduced using the “two-sided process” where shifting of the device layer405after removal of the growth substrate402is not an overriding factor.

FIG. 16is a cross-sectional side view illustration of bringing together carrier substrate460having raised spacers463and stabilization layer445formed over a micro device layer405in accordance with an embodiment of the invention. Carrier substrate460has a back side464opposite a spacer side465. Spacer side465includes raised spacers463extending away from a spacer-side surface467of carrier substrate460. In one embodiment, raised spacers463are made from the same material (e.g. silicon) as the carrier substrate460. Raised spacers463may be formed using a subtractive process that etches or mills away part of carrier substrate460to make raised spacers463. Raised spacers463could also be of a different material than carrier substrate460and added to carrier substrate460in an additive process. In one example, oxide is added to carrier substrate460to form raised spacers463on carrier substrate460. Carrier substrate460may have the same or similar placements of raised spacers463as described in reference to carrier substrate160and raised spacers163, shown inFIGS. 7A and 7B.

Still referring toFIG. 16, carrier substrate460is bonded to the underlying structure (which includes bulk LED substrate400, conduction contacts420and sacrificial layer435) via the adhesion properties of stabilization layer445. In order to increase adhesion with the stabilization layer445, an adhesion promoter layer462can be applied to the carrier substrate460prior to bonding the bulk LED substrate400to the carrier substrate460similarly as described above with regard to adhesion promoter layer144. Depending upon the particular material of stabilization layer445, stabilization layer445may be thermally cured, or cured with application of UV energy, as described in connection with stabilization layer145.

FIG. 17is a cross-sectional side view illustration of carrier substrate460having raised spacers463bonded to a stabilization layer445formed over micro device layer405in accordance with an embodiment of the invention. InFIG. 17, raised spacer463of carrier substrate460has been brought to rest upon sacrificial layer435. In other words, raised spacers463extend into stabilization layer445, meeting at least a subset of stabilization posts452in the structure illustrated inFIG. 17. In the illustrated embodiment, adhesion promoter layer444and462may be disposed between sacrificial layer435and carrier substrate460, but in other embodiments, raised spacer463of carrier substrate460may contact sacrificial layer435. Since during bonding raised spacer463extends through stabilization layer445to the more solid sacrificial layer, the planar alignment of device layer405and uniformity in thickness of the stabilization layer445across carrier substrate460may improve. And as a consequence, the micro devices (to be formed) will also enjoy the improved planarity, which has potential advantages that are similar to those described above in the description ofFIG. 8.

FIG. 18is a cross-sectional side view illustration of the removal of substrate402in accordance with an embodiment of the invention. When substrate402is GaAs, wet etch chemistry may be used to remove substrate402. In one embodiment, a NH4OH and H2O2chemistry is used to wet etch a substrate402that is of GaAs. Removal may be accomplished by other techniques such as grinding or CMP, depending upon the material selection of substrate402.

FIG. 19is a cross-sectional side view illustration of device layer405patterned to form an array of micro devices428over an array of stabilization posts452in accordance with an embodiment of the invention. Etching of layers108,110, and112of device layer405may be accomplished using suitable etch chemistries for the particular materials. For example, n-doped semiconductor layer108, quantum well layer(s)110, and p-doped layer112may be dry etched in one operation with a BCl3and Cl2chemistry. After the appropriate layers of device layer405are etched, an array of micro devices428remains. InFIG. 19, raised spacer463is shown “covering” an area that is two micro devices428wide. However, in one embodiment, raised spacer463covers an area that is five micro devices428wide, resulting in a total coverage of approximately 25 micro devices428. In one embodiment raised spacers463are circular, having a diameter of 60-100 μm.

FIG. 20is a cross-sectional side view illustrations of patterned conductive contacts475formed over the array of micro devices428in accordance with an embodiment of the invention. Conductive contacts475may be formed by electron beam physical deposition or by another suitable method. Conductive contact475may be formed of a variety of conductive materials including metals, conductive oxides, and conductive polymers. In an embodiment, conductive contacts475are formed of a metal or metal alloy. Conductive contacts475may include conductive contact layers that include BeAu metal alloy, or a metal stack of Au/GeAuNi/Au layers. The conductive contact layer can also be a combination of one or more metal layers and a conductive oxide. In an embodiment, conductive contacts475are n-metal conductive contacts.

The resultant structures illustrated inFIG. 20is robust enough for handling and cleaning operations to prepare the substrate structure for subsequent sacrificial layer removal and electrostatic pick up. In an exemplary embodiment where the array of micro devices428have a pitch of 5 microns, each micro device428may have a minimum width of 4.5 μm, and a separation between adjacent micro devices of 0.5 μm. It is to be appreciated that a pitch of 5 microns is exemplary, and that embodiments of the invention encompass any pitch of 1 to 100 μm as well as larger, and possibly smaller pitches. Also inFIG. 20, a bottom surface of each micro device428is wider that the corresponding stabilization post452that is directly under the micro device428. In the illustrated embodiments, stabilization posts452extend into a thickness of sacrificial layer435.

FIG. 21is a cross-sectional side view illustration of the array of micro devices428formed on an array of stabilization posts452after removal of a sacrificial layer435in accordance with an embodiment of the invention. To remove sacrificial layer435, a suitable etching chemistry such as HF vapor, CF4, or SF6plasma may be used to etch if sacrificial layer435includes SiO2or SiNx, for example. In an embodiment where raised spacers463are formed of an oxide material, the raised spacers463may be removed along with sacrificial layer435if the etching chemistry for both sacrificial layer435and raised spacers463(formed of oxide) are similar. After sacrificial layer435is removed, the array of micro devices428remain on the array of stabilization posts452and are supported only by the array of stabilization posts152. At this point, the array of micro devices428are poised for pick up transferring to a target or receiving substrate.

FIGS. 22A-22Eare cross-sectional side view illustrations of an array of electrostatic transfer heads204transferring micro devices128from a carrier substrate160to a receiving substrate300in accordance with an embodiment of the invention. Although the transfer process illustrated inFIGS. 22A-22Eis shown using the structure ofFIG. 11A, the transfer process could also be performed using the structure fromFIG. 21.

FIG. 22Ais a cross-sectional side view illustration of an array of micro device transfer heads204supported by substrate200and positioned over an array of micro devices128stabilized on stabilization posts152of stabilization layer145on carrier substrate160. The array of micro devices128are then contacted with the array of transfer heads204as illustrated inFIG. 22B. As illustrated, the pitch of the array of transfer heads204is an integer multiple of the pitch of the array of micro devices128. A voltage is applied to the array of transfer heads204. The voltage may be applied from the working circuitry within a transfer head assembly206in electrical connection with the array of transfer heads through vias207. The array of micro devices128is then picked up with the array of transfer heads204as illustrated inFIG. 22C. The array of micro devices128is then placed in contact with contact pads302(e.g. gold, indium, or tin) on a receiving substrate300, as illustrated inFIG. 22D. The array of micro devices128is then released onto contact pads302on receiving substrate300as illustrated inFIG. 22E. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or ICs, or a substrate with metal redistribution lines.

In accordance with embodiments of the invention, heat may be applied to the carrier substrate, transfer head assembly, or receiving substrate during the pickup, transfer, and bonding operations. For example, heat can be applied through the transfer head assembly during the pick up and transfer operations, in which the heat may or may not liquefy the micro device bonding layers125. The transfer head assembly may additionally apply heat during the bonding operation on the receiving substrate that may or may not liquefy one of the bonding layers on the micro device or receiving substrate to cause diffusion between the bonding layers.

The operation of applying the voltage to create a grip pressure on the array of micro devices can be performed in various orders. For example, the voltage can be applied prior to contacting the array of micro devices with the array of transfer heads, while contacting the micro devices with the array of transfer heads, or after contacting the micro devices with the array of transfer heads. The voltage may also be applied prior to, while, or after applying heat to the bonding layers.

Where the transfer heads204include bipolar electrodes, an alternating voltage may be applied across a the pair of electrodes in each transfer head204so that at a particular point in time when a negative voltage is applied to one electrode, a positive voltage is applied to the other electrode in the pair, and vice versa to create the pickup pressure. Releasing the array of micro devices from the transfer heads204may be accomplished with a varied of methods including turning off the voltage sources, lower the voltage across the pair of silicon electrodes, changing a waveform of the AC voltage, and grounding the voltage sources.

Furthermore, the method of pickup up and transferring the array of micro devices from a carrier substrate to a receiving substrate described with regard toFIGS. 22A-22Eis applicable in contexts where the micro devices are micro LEDs or other examples of micro devices described herein.

In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for stabilizing an array of micro devices on a carrier substrate, and for transferring the array of micro devices. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.