Audibly announcing apparatus

A timer-announcer system stores instructions for generating various types of time information, e.g., sharp time (announced at a pre-set time); and updated real time (announcing the present time upon demand by a key actuation). The sounds may be simultaneously required, in which case logic circuits assign relative priorities for delivery of the instructions to the sound synthesizer.

BACKGROUND OF THE INVENTION 
This invention relates to a method of preventing overlap delivery of a 
plurality of audible indications of information in an audible announcing 
output apparatus. 
In the case of visual indications of information, it need not take a great 
deal of time to complete the visual delivery of information. Nevertheless, 
audible indications of information require necessarily a substantial 
amount of time as compared with the visual indications. Accordingly, when 
different kinds of information are to be indicated at a time, many 
problems will occur mainly with audible indications. If different kinds of 
information, like news and weather forecasts, are audibly announced at the 
same time, one would not be able to hear both of those announcements. For 
instance, if only first information is allowed to be announced, then it is 
impossible for the operator to know information other than the first 
information. 
These problems are most severe with talking clocks and the like which deal 
with time information. There are great possibilities that a certain kind 
of information may overlap with another kind of information, when 
considering (1) announcement of updated or real time, (2) announcement of 
alarm information, and (3) announcement of each sharp time, that is, time 
information which is audibly recited each specific time period within the 
hour, for example, each 59 minutes, 48 second time period. 
Overlap occurs between (1) and (2); alarm time is reached in the middle of 
announcement of real time or real time is recalled in the middle of 
announcement of alarm information. 
Overlap occurs between (2) and (3): the clock shows sharp time to be 
audibly announced during the course of announcement of alarm information. 
Instead, alarm time is reached during announcement of sharp time. 
And overlap occurs between (1) and (3): sharp time arrives during the 
course of announcement of updated or real time and the operator recalls 
updated or real time during the course of announcement of sharp time. 
The same is true of the relationship among (1), (2) and (3). 
OBJECTS AND SUMMARY OF THE INVENTION 
Accordingly, it is a general object of the present invention to provide an 
audibly announcing apparatus which overcomes the above discussed problems 
and thus avoids overlap and simultaneous delivery of audible indications 
of information by allowing information with the first priority to be 
delivered when two or more items of information are to be delivered. 
Briefly, according to the present invention an audibly announcing apparatus 
providing audible indications of a plurality of items of information under 
control of instructions including means for determining whether said 
instructions are overlapped with each other and means for determining the 
order of priority of said instructions.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT 
Specific embodiments of the present invention will now be discussed in 
detail in terms of a talking timepiece. The following summarizes the 
concept of the present invention when applied to a talking timepiece. 
In order to prevent overlap between (1) announcement of updated or real 
time and (2) announcement of alarm information, there is provided a switch 
means for instructing the timepiece to announce updated time in the form 
of an audible sound or voice but serving as a halt switch for 
discontinuing announcement alarm information during the course of sharp 
time. Also when alarm time is reached during the course of real time 
announcement, announcement of real time comes to a halt and the alarm 
information is given priority as the most significant information upon 
actuation of the switch means. 
With respect to overlap between (2) announcement of alarm information and 
(3) information of each sharp time, it should be understood that each 
sharp time is announced between 59 min 48 sec and 00 min 0.3 sec and alarm 
information can be preset in units up to minutes. Announcement of the 
alarm information starts at each 00 seconds and continues within a limited 
length of time (say, 48 seconds). Therefore, overlap extends between only 
0.3 seconds and the present invention avoids such overlap by delaying 0.3 
seconds the time when alarm information is announced. The fact that 
alarmed time is delayed from its accurate one by 0.3 seconds is no 
significant importance for practical use and sharp time is very accurately 
announced without any delay or error. 
Overlap between (1) announcement of real time and (3) that of each sharp 
time is overcome in the manner by which announcement of real time is 
interrupted and announcement of each sharp time is allowed, when each 
sharp time is reached in the middle of announcement of real time, and 
announcement of real or updated time is inhibited with that of each sharp 
time having priority, when in the middle of announcement of each sharp 
time. 
It is also evident from the foregoing that any overlap is offset among (1) 
announcement of current time, (2) announcement of alarm time and (3) 
announcement of each sharp time. 
Current or updated time of day is announced in the form of an audible 
message "it is .sub.---- hours .sub.---- minutes.". Alarm time is 
announced in the form of "peep peep peep peep peep it is now .sub.---- 
hours .sub.---- minutes" three times and at each 00 seconds with an 
appropriate interval of time. Each sharp time is audibly indicated in the 
form of "peep peep it is .sub.---- o'clock, peep peep peep." 
Referring now to FIG. 1, there is illustrated a talking timepiece 
constructed in accordance with one preferred form of the present 
invention, which includes an instruction memory (program memory) set up 
with a conventional read only memory, an address register RAR, an address 
decoder RDC, an instruction selection gate circuit RUG, and an instruction 
decoder IM which develops a string of micro instructions 1 - n in 
response to the contents fetched from the program memory RU via the 
selection gate circuit RUG. A memory unit RM of a random access memory 
temporarily stores respective data to be audibly announced and has as its 
peripheral circuit elements an address counter AC, an address decoder AD, 
an input output control circuit MS, an adder FA which increments the 
address counter AC, and a reset circuit ACR which places the counter AC 
into the reset state. An accumulator ACC has its accessories an input gate 
GA, an output buffer OB with its input gate GO, and a decision circuit JRE 
which decides whether the data transferred into the accumulator ACC are a 
transfer end code EC described later. 
A clock generator CG is coupled to a divider DV which in turn generates 
standard signals for timekeeping purposes. A timekeeping counter CO 
includes a seconds section S, a minutes section M and a hours section H. A 
register AR stores alarm time which can be preset upon actuation of an 
alarm time set key ASK via a time setting circuit AS. 
A decision circuit JS decides if the contents of the seconds section S are 
zero and another decision circuit JA decides if the contents of the 
timekeeping counter CO are in agreement with the respective minutes and 
hours sections M and H of the alarm time register AR. A decision circuit 
JJ, on the other hand, decides if the time comes when announcement of each 
sharp time is due to start (59 minutes 48 seconds) while monitoring the 
counts of the seconds and minutes sections S and M. A time recall key TK 
serves as a halt key for discontinuing announcement of alarm time in the 
middle of the announcement of alarm time as set forth previously. 
Counters C.sub.1 and C.sub.2 count the time of announcement of alarm 
information (the former counts the time of continued announcements and the 
latter counts the time of intermittent or spaced announcements). The both 
have their circuits CR.sub.1 and CR.sub.2 and decision circuits JC.sub.1 
and JC.sub.2 as to whether the time exceeds three. 
FJ, FA.sub.1, FA.sub.2 and FT are conditional flip flops which provide 
various controls. Decision circuits JF.sub.1, JF.sub.2, JF.sub.3 and 
JF.sub.4 sense those flip flops in the set state. 
The illustrated timepiece further includes a sound output control circuit 
or a voice synthesizer VCC which can be realized by use of large scale 
integrated circuit technology, a loud speaker SP and an output buffer OB 
through which outputs are supplied to the loud speaker for the delivery of 
audible indications of a variety of time information. Details of the voice 
synthesizer VCC are depicted in a block diagram of FIG. 2. 
A memory unit VR of a well known read only memory is adapted to store sound 
quantizing data and has an address counter VAC and an address decoder VAD. 
When no sound is required to announce, a reset circuit CLA clears the 
address counter VAC not to specify any address of the memory unit VR. An 
adder FA increments the address specified by the address counter VAC by 
one and executes operation of VAC+1.fwdarw.VAC automatically at a given 
sampling frequency once an initial address for any specific sound region P 
has been set up for the delivery of sounds or audible messages. This leads 
to sequential readout of the quantizing date from that region. 
A code converter CC receives sound region specifying signals S.sub.1 from 
the output buffer OB and converts them into codes suitable for loading the 
initial address for the specific sound region P into the address counter 
VAC. An END code detector JE senses an END code inserted at the final step 
of the respective regions P and renders the reset circuit CLA operative to 
reset the address counter VAC. This output of the detector is applied as a 
signal S.sub.2 to the instruction selection gate RUG for establishment of 
the next initial address. 
As is well known in the art, the voice synthesizer VCC also comprises a 
digital to analog converter DAC, a low pass filter LPF, a speaker driver 
DD and the above mentioned loud speaker SP. 
Operation of the above described arrangement will be more clearly 
understood by reference to a flow chart of FIG. 3. 
The step n.sub.1 senses the flip flop FJ in the set state using the 
decision circuit JF.sub.1, the step n.sub.10 senses the flip flop FA.sub.2 
in the set state through the decision circuit JF.sub.3 and the step 
n.sub.29 senses the flip flop FT in the set state through the decision 
circuit JF.sub.4. The flip flop FJ is set when the seconds and minutes 
sections S and M of the timekeeping counter CO show 59 minutes and 48 
seconds as viewed by the decision circuit JJ, thus initiating announcement 
of each sharp time. 
The flip flop FA.sub.2 is set when the contents of the timekeeping counter 
CO agree with the contents of the hours and minutes sections H and M of 
the alarm time register AR as sensed by the decision circuit JA. In other 
words, with the flip flop FA.sub.2 in the set state, announcement of alarm 
time starts. When the flip flop FA.sub.1 is in the reset state as 
discussed hereinbelow and the time recall key TK is actuated, the flip 
flop FT triggers announcement of real or updated time. By a sequence of 
the steps n.sub.1 .fwdarw.n.sub.10 .fwdarw.n.sub.29, priority is 
determined in the order of announcement of sharp time, announcement of 
alarm time and announcement of updated time. 
ANNOUNCEMENT OF SHARP TIME 
If the step n.sub.1 detects the flip flop FJ in the set state, then the 
step n.sub.2 becomes operative to transfer a string JI of word data into 
the memory unit RM. The transferring of the word data JI is viewed in FIG. 
4(a) wherein the respective word data are sent sequentially into the 
memory unit RM in order to deliver the above mentioned message "peep peep, 
it is .sub.---- o'clock, peep peep peep peep." This mode of operation 
will now be discussed in further detail. 
During the first step m.sub.0 the micro instruction 7 is developed to 
reset the address counter AC with the help of the reset circuit ACR. This 
specifies the initial address of the word data to be loaded into the 
memory unit RM. The respective data words WD such as "peep", etc. are 
transferred as depicted in a flow chart of FIG. 5(a) and the numerical 
data N in the hours section H as in FIG. 5(b). For the linguistic data WD, 
the micro instruction 8 is developed at the step P.sub.1 to unload the 
linguistic data WD from the program memory RU into the accumulator ACC via 
the input gate GA. The step P.sub.2 follows wherein the micro instruction 
9 is developed to transfer them into the memory unit RM via the input 
output control circuit MS. The micro instruction 10 developed during the 
step P.sub.3 operates the adder FA to increment the address counter AC by 
one for next succeeding transmission of data. With respect to the 
numerical data N, the micro instruction 11 during the step P.sub.1 
sends the contents of the hours section H (plus one through an appropriate 
circuit although not shown, in the case of announcement of sharp time) to 
the accumulator ACC. Through the steps P.sub.2 and P.sub.3 as discussed 
previously the numerical data N are loaded into the memory unit RM and the 
address counter AC is incremented by one. After those linguistic data WD 
and numerical data N have been sequentially transferred into the memory 
unit RM, the transmission end code EC goes to the memory unit RM during 
the step m.sub.10 as depicted in FIG. 5(a). 
Upon the completion of transmission of the word data string JI, the micro 
instruction 7 is developed during the step n.sub.3 to reset again the 
address counter AC which is now ready for next readout operation. The step 
n.sub.4 decides if the signal S.sub.2 is derived from the voice 
synthesizer VCC and in other words whether the decision circuit JE senses 
the END code from the respective sound regions P within the voice 
synthesizer VCC. In the presence of the signal S.sub.2 (indicative of the 
sensed end code) the step n.sub.5 becomes operable to develop the micro 
instruction 12 and fetch the word data from the memory unit RM into the 
accumulator ACC. The step n.sub.6 decides if the word data transferred 
into the accumulator ACC are indicative of the end code EC. If not, the 
step n.sub.7 is executed to develop the micro instruction 6 and supply 
the word data to the output buffer OB via the input gate GO. 
Within the voice synthesizer VCC (see FIG. 2), a specific sound region P is 
designated in response to the transferred word data, the region storing 
its corresponding quantizing data which in turn are sequentially fetched 
for the delivery of an audible message. The step n.sub.3 is to specify the 
next readout address of the memory unit RM generating the micro 
instruction 10 and incrementing the address counter AC by one, followed 
by the step n.sub.4 which is set aside until the data relating one word 
are actually announced in the form of a synthesized voice. The step 
n.sub.5 is reached once the one word-related data have completely been 
announced. Those steps n.sub.4 through n.sub.8 are repeated until the 
transmission end code EC appears during the step n.sub.6. The step n.sub.9 
follows wherein the micro instruction 4 is useful in resetting the flip 
flop FJ and recovering the step n.sub.1, after the transmission end code 
EC is sensed. 
ANNOUNCEMENT OF ALARM INFORMATION 
Alarm information is announced if the flip flop FA.sub.2 in the set state 
is sensed by the step n.sub.10. However, in the case where both alarm time 
and sharp time are to be announced at the same time, the step n.sub.10 is 
not reached until sharp time has been completely announced with the flip 
flop FJ in the set state. As previously set forth, the step n.sub.10 is 
executed with a time lag of 0.3 seconds which is negligible from a 
practical point of view. On the other hand, with no overlap between alarm 
time and sharp time, the step n.sub.10 is executed at once after the set 
state of the flip flop FA.sub.2 has been detected. 
The step n.sub.11 makes the decision circuit JJ operative to decide if the 
count of the seconds section S of the timekeeping counter CO shows zero. 
Immediately after equality between alarm time and sharp time is detected, 
it shows zero and makes the step n.sub.12 operative to develop the micro 
instruction 15 and set the flip flop FA.sub.1. As is clear from FIG. 1, 
the setting of the flip flop FA.sub.1 makes it possible to reset the flip 
flop FA.sub.2 upon actuation of the time recall key TK and thus interrupt 
announcement of alarm information in progress. 
The step n.sub.14 transfers the word data string AL into the memory unit RM 
as viewed from FIG. 4(b). In order to deliver the message "peep peep peep 
peep, it is now .sub.---- hours .sub.---- minutes", the associated word 
data are fetched in sequence from the memory unit RM. The same procedure 
described above with respect to announcement of sharp time is applicable 
to this situation. The steps n.sub.15 through n.sub.21 are carried out in 
a similar manner so that the respective word data are sequentially 
supplied to the voice synthesizer VCC. The step n.sub.17 which makes 
decision as to the signal S.sub.2 is preceded by the step n.sub.16 which 
senses the flip flop FA.sub.2 in the set state while the signal S.sub.2 
appears through repetition of the steps n.sub.16 -n.sub.21. Accordingly, 
if the time recall key TK is actuated in the middle of announcement, then 
the flip flop FA.sub.2 is reset to return the step n.sub.1 and halt 
announcement of alarm time. The step n.sub.22 is interposed between the 
steps n.sub.16 and n.sub.1, which develops the micro instruction 3 and 
resets the flip flop FA.sub.1. 
After the step n.sub.19 senses the development of the transmission end code 
EC, the step n.sub.23 is carried out to develop the micro instruction 1 
and increment the counter C.sub.1. By the action of the decision circuit 
JC.sub.1, the step n.sub.24 decides if the count of the counter C.sub.1 is 
three. If not, the step n.sub.16 is returned to repeat the delivery of 
sounds. It goes without saying that the step n.sub.16 senses the flip flop 
FA.sub.2 in the set state during the delivery of audible sounds. If 
continued announcement of the same message are delivered three times 
without halt, then the procedure advances from n.sub.24 toward n.sub.25, 
developing the micro instruction 3 and placing the flip flop FA.sub.1 
into the reset state. The three continued announcements extend within 48 
seconds. 
With the flip flop FA.sub.1 in the reset state, the step n.sub.26 becomes 
effective to develop the micro instruction 13 and increment the counter 
C.sub.2. The step n.sub.27 monitors the contents of the counter C.sub.2 
using the decision circuit JC.sub.2, followed by the step n.sub.1 when 
they are not three. Since the flip flop FJ is normally in the reset state, 
the procedure proceeds with the step n.sub.10 which decides if the second 
section S assumes zero. If not, the steps n.sub.1 .fwdarw.n.sub.10 
.fwdarw.n.sub.11 .fwdarw.n.sub.29 .fwdarw.n.sub.1 are repeated until the 
seconds section S assumes zero. If the seconds section S shows zero, then 
the step n.sub.12 is effected for transmission and readout of the word 
data string AL. It is appreciated that the contents of the minutes section 
M in the word data string AL are one more than the previous one upon the 
passage of time. 
If sharp time is reached until the seconds section S assumes zero, then the 
step n.sub.1 senses the flip flop FT in the set state. Thereafter, the 
steps n.sub.2 and so forth are effected for announcement of sharp time. 
During the progress of announcement of sharp time a sequence of the steps 
n.sub.1 .fwdarw.n.sub.10 .fwdarw.n.sub.11 are not carried out so that 
announcement of alarm time begins with a time delay of 0.3 seconds from 
each 00 seconds. Even if the time recall key TK is actuated during 
announcement of alarm time, the flip flop FA.sub.2 is not reset because 
the flip flop FA.sub.1 has already been reset during the step n.sub.24. 
But upon actuation of the key TK the flip flop FT is placed into the set 
state which is confirmed by the step n.sub.29 relying upon the decision 
circuit JF.sub.4. This decision initiates announcement of real or updated 
time as will be discussed in detail below. 
After the message is repeated three times at an appropriate interval 
without actuation of the key TK, the step n.sub.27 decides that the 
contents of the counter C.sub.2 are three and renders the step n.sub.28 
operative to develop the micro instruction 14 and reset the flip flop 
FA.sub.2. The step n.sub.1 is returned, thus completing normal 
announcement of alarm information. 
ANNOUNCEMENT OF UPDATED TIME 
Upon actuation of the time recall key TK the flip flop FT is set and 
confirmed by the step n.sub.29 which in turn operates the step n.sub.30 
for loading the word data string T into the memory unit RM. The string T 
is transferred as shown in FIG. 4(c) to announce updated time in the form 
of a message "it is .sub.---- o'clock." Details of such transmission are 
substantially similar to that for other types of time information as 
discussed in greater detail. The step n.sub.31 is executed to develop 7 
and zero the address counter AC for the next succeeding readout operation. 
The step n.sub.34 is preceded by the step n.sub.32 which senses the flip 
flop in the set state and the step n.sub.33 which senses the flip flop 
FA.sub.2 in the set state. These two steps are repeated until the 
development of the signal S.sub.2. Repeated execution of the steps 
n.sub.32 -n.sub.38 fetches sequentially to respective ones of the word 
data string T and supplies them to the voice synthesizer VCC as set forth 
above. 
If sharp time comes during the course of announcement, the flip flop FJ is 
set and confirmed by the step n.sub.32. The result is that the step 
n.sub.1 is returned via the step n.sub.39 to initiate announcement of 
sharp time through execution of the steps n.sub.2 and so forth. When alarm 
time is reached, the step n.sub.33 senses the flip flop FA.sub.2 in the 
set state and the step n.sub.40 decides if the contents of the seconds 
section S assume zero. The procedure advances in the order of n.sub.39, 
n.sub.1 and n.sub.10. Announcement of alarm time begins by the step 
n.sub.11 and following steps. The step n.sub.39 develops the micro 
instruction 5 and resets the flip flop FT, while the step n.sub.36 
terminates announcement of updated time inclusive under the situation 
where the transmission end code EC is sensed by the step n.sub.36. 
It is noted earlier that the flip flop FT may be set upon actuation of the 
time recall key TK during the course of announcement of alarm time. In 
this case the step n.sub.29 senses the flip flop FT in the set state, 
making the step n.sub.30 and following steps operative. The step n.sub.33 
senses the flip flop FA.sub.2 in the reset state during the progress of 
announcement of alarm time. Since the contents of the seconds section S 
are not zero under the circumstance, the step n.sub.40 renders the step 
n.sub.34 operative. This enables updated time to be read out during the 
course of announcement of alarm time. Provided that the seconds section S 
assumes zero during announcement of updated time, the step n.sub.39 is 
executed to interrupt announcement of updated time to re-start 
announcement of alarm information. 
FIG. 6 shows another preferred form of the present invention, wherein T 
indicates announcement of any desired time such as announcement of current 
time and JI.sub.1 and JI.sub.2 indicate announcement of each sharp time. 
In other words, there are two different kinds of announcement of sharp 
time and for example JI.sub.1 takes the form of "please attention, it is 
now .sub.---- o'clock, peep peep peep" and the latter in the form of "it 
is .sub.---- hours .sub.---- minutes." 
Announcement of each sharp time JI.sub.1 normally begins with each 59 
minutes 51 seconds t.sub.1 and ends with 00 seconds t.sub.2. In the case 
where announcement T of any specific time ends before 59 minutes 51 
seconds t.sub.1 as depicted in FIG. 6(1) or announcement T starts after 00 
minutes 00 seconds t.sub.2 as depicted in FIG. 6(6), there is no problem 
with overlapping announcements. However, in the case where announcement T 
of any specific time extends between 59 minutes 51 seconds t.sub.1 and 00 
minutes 00 seconds, t.sub.2 as depicted in FIG. 6(2), announcement T 
continues without executing announcement JI.sub.1 and instead the 
different type of announcement JI.sub.2 starts at 00 minutes 00 seconds 
t.sub.2. When announcement T of any specific time continues between 59 
minutes 51 seconds t.sub.1 and 00 minutes 00 seconds t.sub.2, as shown in 
FIG. 6(3), neither JI.sub.1 nor JI.sub.2 does commence. In addition, when 
an instruction is given for announcement of any specific time on the way 
of announcement of sharp time JI.sub.1, announcement of sharp time 
JI.sub.1 is interrupted and new announcement T is allowed to start. Under 
the condition of FIG. 6(4) where announcement T ends before 00 minutes 00 
seconds t.sub.2, the different type of sharp time JI.sub.2 is allowed to 
continue. Announcement T continues after passing 00 minutes 00 seconds as 
depicted in FIG. 6(5) without releasing the different type of announcement 
JI.sub.2. 
In this manner, announcement T of any specific time is given priority and 
either of the different announcements JI.sub.1 and JI.sub.2 is selected 
according to the time when priority information is announced. 
The specific examples as herein shown and described are for illustrative 
purposes. Various changes will no doubt occur to those skilled in the art 
and will be understood as forming a part of the present invention insofar 
as they fall within the spirit and scope of the appended claims.