Memory block select circuitry including voltage bootstrapping control

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

BACKGROUND

Memory devices are widely used in computers, cellular phones, and many other electronic items. A conventional memory device, such as a flash memory device, has many memory cells to store information. During a memory operation, different voltages are used. Such voltages can have a relatively high voltage value during some memory operations of the memory device. As described in more detail below, such a high voltage value may cause stress and increase power consumption in some conventional memory devices.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of an apparatus in the form of a memory device100, according to some embodiments described herein. Memory device100can include a memory array (or multiple memory arrays)101containing memory cells102arranged in blocks (blocks of memory cells), such as blocks190and191. In the physical structure of memory device100, memory cells102can be arranged vertically (e.g., stacked over each other in a 3D arrangement) over a substrate (e.g., a semiconductor substrate) of memory device100. Alternatively, memory cells102can be arranged horizontally (e.g., in a planar or 2D arrangement) over a substrate of memory device100.FIG. 1shows memory device100having two blocks190and191as an example. Memory device100can have more than two blocks (e.g., hundreds or thousands of blocks).

As shown inFIG. 1, memory device100can include access lines (conductive lines that can include word lines)150and data lines (conductive lines that can include bit lines)170. Access lines150can carry signals (e.g., word line signals) WL0through WLm. Data lines170can carry signals (e.g., data signals) BL0through BLn. Memory device100can use access lines150to selectively access memory cells102of blocks190and191, and data lines170to selectively exchange information (e.g., data) with memory cells102of blocks190and191.

Memory device100can include an address register107to receive address information (e.g., address signals) ADDR on lines (e.g., address lines)103. Memory device100can include row access circuitry108and column access circuitry109that can decode address information from address register107. Based on decoded address information, memory device100can determine which memory cells102of which of blocks190and191are to be accessed during a memory operation.

Row access circuitry108can include driver circuits (e.g., word line drivers)140and driver select circuits145. Examples of driver circuits140and driver select circuits145are described in more detail with reference toFIG. 2throughFIG. 8. During memory operations of memory device100inFIG. 1, driver circuits140can operate (e.g., operate as switches) to form (or not to form) conductive paths (e.g., current paths) between respective access lines150and nodes (or lines) that provide voltages to access lines150. Driver select circuits145can operate to selectively activate (and deactivate) driver circuits140depending on which of the blocks (e.g., block190or191) of memory device100is selected to be accessed during a particular memory operation of memory device100.

Memory device100can perform a read operation to read (e.g., sense) information (e.g., previously stored information) from memory cells102of blocks190and191, or a write (e.g., programming) operation to store (e.g., program) information in memory cells102of blocks190and191. Memory device100can use data lines170associated with signals BL0through BLn to provide information to be stored in memory cells102or obtain information read (e.g., sensed) from memory cells102. Memory device100can also perform an erase operation to erase (e.g., clear) information from some or all of memory cells102of blocks190and191.

Memory device100can include a control unit118that can be configured to control memory operations of memory device100based on control signals on lines104. Examples of the control signals on lines104include one or more clock signals and other signals (e.g., a chip enable signal CE#, a write enable signal WE#) to indicate which operation (e.g., read, write, or erase operation) memory device100is to perform.

Memory device100can include sense and buffer circuitry120, which can include components such as sense amplifiers and page buffer circuits (e.g., data latches). Sense and buffer circuitry120can respond to signals BL_SEL0through BL_SELn from column access circuitry109. Sense and buffer circuitry120can be configured to determine (e.g., by sensing) the value of information read from memory cells102(e.g., during a read operation) of blocks190and191and provide the value of the information to lines (e.g., global data lines)175. Sense and buffer circuitry120can also be configured to use signals on lines175to determine the value of information to be stored (e.g., programmed) in memory cells102of blocks190and191(e.g., during a write operation) based on the values (e.g., voltage values) of signals on lines175(e.g., during a write operation).

Memory device100can include input/output (I/O) circuitry117to exchange information between memory cells102of blocks190and191and lines (e.g., I/O lines)105. Signals DQ0through DQN on lines105can represent information read from or to be stored in memory cells102of blocks190and191. Lines105can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside. Other devices external to memory device100(e.g., a memory controller or a processor) can communicate with memory device100through lines103,104, and105. For example, a controller (e.g., a memory controller or a processor) can send commands (e.g., read, write, and erase commands) to memory device100to cause memory device100to perform memory operations described herein with respect toFIG. 1throughFIG. 8.

Memory device100can receive voltages (e.g., supply voltages) Vcc and Vss. Voltage Vcc can have a positive value (e.g., Vcc>0V). Voltage Vss can operate at a ground potential (e.g., Vss=0V). Voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery, or alternatively from alternating current to direct current (AC-DC) converter circuitry.

Memory device100can include a voltage generator177to generate different voltages (not labeled inFIG. 1) and provide the generated voltages at outputs178. The voltages at outputs178can be used during different memory operations of memory device100. Voltage generator177can include circuit components (e.g., charge pumps) to generate voltages that can have different values, and such values can be greater than (or less than) the value of voltage Vcc. The voltages at outputs178can be similar to (or identical to) the voltages described below with reference toFIG. 2throughFIG. 8.

InFIG. 1, each of memory cells102can be programmed to store information representing a value of at most one bit (e.g., a single bit), or a value of multiple bits such as two, three, four, or another number of bits. For example, each of memory cells102can be programmed to store information representing a binary value “0” or “1” of a single bit. A cell capable of storing a single bit is sometimes called a single-level cell (or “SLC”). In another example, each of memory cells102can be programmed to store information representing a value for multiple bits, such as one of four possible values “00”, “01”, “10”, and “11” of two bits, one of eight possible values “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “11” of three bits, or one of other values of another number of multiple bits. A cell that has the ability to store multiple bits is sometimes called a multi-level cell (or multi-state cell). In some contexts in the industry, the term multi-level cell (or MLC) is used to refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), the term triple-level cell (TLC) is used to refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and the term quad-level cell (QLC) is used to refer to a cell that can store four bits of data per cell (e.g., one of sixteenth programmed states). For purposes of the present description, unless expressly indicated otherwise, the term multi-level cell (or MLC) will be used in the broader context to refer to a memory cell that can store two or more bits of data per cell. Thus, the term multi-level cell is generic to both triple level cells, quad level cells, and future memory cell configurations capable of storing more than four bits of data per cell.

Memory device100can include a non-volatile memory device, and memory cells102can include non-volatile memory cells, such that memory cells102can retain information stored thereon when power (e.g., voltage Vcc, Vss, or both) is disconnected from memory device100. For example, memory device100can be a flash memory device, such as a NAND flash (e.g., 3-dimensional (3-D) NAND) or a NOR flash memory device, or another kind of memory device, such as, by way of example but not limitation, a variable resistance memory device (e.g., a phase change memory device (of various configurations), a resistive Random Access Memory (RAM) device, or a magnetoresistive random-access memory (MRAM) device. For purposes of the present description, the device will be described in the context of a NAND flash memory device.

One of ordinary skill in the art may recognize that memory device100may include other components, several of which are not shown inFIG. 1so as not to obscure the example embodiments described herein. At least a portion of memory device100can include structures and perform operations similar to or identical to the structures and operations of any of the memory devices described below with reference toFIG. 2throughFIG. 8.

FIG. 2shows a schematic diagram of a portion of a memory device200including blocks (blocks of memory cells)290and291, driver circuits2400and2401, and driver select circuits2450and2451, according to some embodiments described herein. Memory device200can correspond to memory device100ofFIG. 1, such that blocks290and291can correspond to blocks190and191, respectively, ofFIG. 1, driver circuits2400and2401can correspond to driver circuits140ofFIG. 1, and driver select circuits2450and2451can correspond to driver select circuits145ofFIG. 1.

As shown inFIG. 2, blocks290and291can have similar elements. Thus, for simplicity, similar elements between blocks290and291are given the same labels (e.g., same reference numbers). The following description focuses on the description of block290. The elements of block291can have a similar description (which is not described in detail below for simplicity).

Block290can include memory cells210,211,212, and213, select transistors (e.g., source select transistors)261, and select transistors (e.g., drain select transistors)264. Memory cells210,211,212, and213can be arranged in respective memory cell strings, such as memory cell strings230,231, and232in the depicted example shown inFIG. 2. Memory device200can include a line299that can carry a signal SRC (e.g., source line signal). Line299can be structured as a conductive region (e.g., a conductive line) that can form part of a source (e.g., a source line) shared by blocks290and291of memory device200.

As shown inFIG. 2, memory device200can include data lines (e.g., bit lines)270,271, and272that can carry signals (e.g., data signals) BL0, BL1, and BL2, respectively. Data lines270,271, and272can correspond to some of data lines170ofFIG. 1. Each of memory cell strings230,231, and232of block290can be coupled to one of data lines270,271, and272through one of select transistors264. Each of memory cell strings230,231, and232of block290can also be coupled to line299through one of select transistors261. For example, memory cell string230of block290can be coupled to data line270through select transistor264(directly over memory cell string230) and to line299through select transistor261(directly under memory cell string230). In another example, memory cell string231of block290can be coupled to data line271through select transistor264(directly over memory cell string231) and to line299through select transistor261(directly under memory cell string231).

FIG. 2shows an example of three memory cell strings230,231, and232, and four memory cells210,211,212, and213in each memory cell string of block290(and block291). However, the number of memory cell strings and the number of memory cells in each memory cell string of block290can vary.

As shown inFIG. 2, memory device200can include sense and buffer circuitry220coupled to data lines270,271, and272. Sense and buffer circuitry220of memory device200can operate (e.g., during a read operation) to sense information read from memory cells210,211,212, and213of a block (e.g., block290or291) being accessed (e.g., a selected block). Sense and buffer circuitry220can also operate (e.g., during a write operation) to provide information to be stored in memory cells210,211,212, and213of a block (e.g., block290or291) being accessed (e.g., a selected block).

Memory device200can include a group of conductive lines (e.g., local access lines, such as, for example local word lines)2500,2510,2520, and2530in block290. Some memory cells (e.g., memory cells in the same row) of different memory cell strings of the same block can be coupled to and controlled by (e.g., can share) the same conductive line of that block. For example, memory cells213of block290can be coupled to and controlled by (e.g., can share) the same conductive line (e.g.,2530). In another example, memory cells212of block290can be coupled to and controlled by (e.g., can share) the same conductive line (e.g.,2520).

Each of conductive lines2500,2510,2520, and2530can be structured as a single conductive line (e.g., a single conductive region) that can be formed from conductive material (e.g., conductively doped polysilicon). During a memory operation of memory device200, conductive lines2500,2510,2520, and2530can receive respective signals WL00, WL10, WL20, and WL30to access memory cells210,211,212, and213of selected memory cell strings.

Select transistors (e.g., drain select transistors)264of block290can be coupled to select line (e.g., drain select line)2840. Select transistors264of block290can be controlled (e.g., turned on or turned off) by the same signal, such as signal SGD0(e.g., drain select gate signal) on select line2840.

Select transistors (e.g., source select transistors)261of block290can be coupled to a select line (e.g., source select line)2800. Select transistors261of block290can be controlled (e.g., turned on or turned off) by the same signal, such as signal SGS0(e.g., source select gate signal) applied to select line2800.

As mentioned above, block291includes elements similar to those of block290. For example, block291can include memory cell strings230,231, and232, and a group of conductive lines (e.g., local access lines or local word lines)2501,2511,2521, and2531that can receive respective signals WL01, WL11, WL21, and WL31to access memory cells210,211,212, and213of selected memory cell strings in block291. In another example, block291can include select transistors261, select line (e.g., source select line)2801and corresponding signal SGS1(e.g., source select gate signal), and select line (e.g., drain select line)2841and corresponding signal SGD1(drain select gate signal).

During a memory operation (e.g., a read or write operation) select transistors264of block290can be turned on (e.g., by activating signal SGD0) to couple (e.g., electrically couple) memory cell strings230,231, and232of block290to data lines270,271, and272, respectively. When select transistors264of block290are turned on during a particular memory operation, select transistors264of block291can be turned off (e.g., by deactivating signal SGD1) to decouple (e.g., electrically decouple) memory cell strings230,231, and232of block291from data lines270,271, and272, respectively. This allows memory cell strings230,231, and232of either block290or block291(e.g., one block at a time) to be electrically coupled to data lines270,271, and272during a particular memory operation of memory device200.

During a memory operation, such as a read or write operation, select transistors261of block290can be turned on (e.g., by activating signal SGS0) to couple (e.g., electrically couple) memory cell strings230,231, and232of block290to line299. When select transistors261of block290are turned on during a particular memory operation, select transistors (e.g., source select transistors)261of block291can be turned off (e.g., by deactivating signal SGS1) to decouple (e.g., electrically decouple) memory cell strings230,231, and232of block291from line299.

Each of blocks290and291can have a unique block address (block-level address) within memory device200. During a memory operation (e.g., read, write, or erase operation), only one of blocks290and291can be selected based on the block address. Memory device200can use an address register (which can be similar to address register107inFIG. 1) and row access circuitry (which can be similar to row access circuitry108inFIG. 1) to determine which block (e.g., either block290or291) of memory device200is selected to be accessed during a particular memory operation. The block address of the selected block during a particular memory operation can be provided to memory device200through lines (e.g., address lines) such as lines103ofFIG. 1. Memory device200can activate (e.g., turn on) the driver circuit (e.g., driver circuit2400) associated with the selected block (e.g., block290) to access the memory cells (e.g., selected memory cells) of the selected block. Memory device200can deactivate (e.g., turn off) the driver circuit (e.g., driver circuit2401) associated with the unselected (e.g., deselected) block (e.g., block291).

As shown inFIG. 2, driver circuit2400can include a group of transistors (e.g., high-voltage string driver transistor) T0. Transistors T0can share a transistor gate240T0(e.g., a common transistor gate240T0, which is a transistor control gate shared by transistors T0). Thus, transistors T0can be controlled (e.g., concurrently turned on or concurrently turned off) using the signal (e.g., voltage) on the same transistor gate240T0.

Driver circuit2401can include a group of transistors (e.g., high-voltage string driver transistor) T1. Transistors T1can share a transistor gate240T1(e.g., a common transistor gate240T1, which is a transistor control gate shared by transistors T1and different from transistor gate240T0). Thus, transistors T1can be controlled (e.g., turned on at the same time or turned off at the same time) using the signal (e.g., voltage) on the same transistor gate240T1.

Memory device200can include conductive lines (e.g., global access lines, such as, for example global word lines)250′,251′,252′,253′, and254′ through254i′, each of which can be provided with (e.g., can carry) a voltage (e.g., a voltage signal, which is different from a data signal). As an example, conductive lines250′,251′,252′, and253′ can be provided with voltages (e.g., voltage signals) V0, V1, V2, and V3, respectively. Each of conductive lines250′.251′,252′,253′, and254′ through254i′ can be structured with (e.g., formed from) a conductive material (e.g., conductively doped polysilicon, metal, or other conductive materials).

For simplicity,FIG. 2omits connections (e.g., conductive connections) between conductive lines254′ through254i′ and some elements of blocks290and291. Such connections include connections between conductive lines254′ through254i′ and select lines2800and2840(of block290), select lines2801and2841(of block291), and line (e.g., source line)299.

Driver circuit2400can use transistors T0to provide (e.g., to pass) voltages from conductive lines250′,251′,252′,253′, and254′ through254i′ to respective elements of block290. For example, driver circuit2400can use four of transistors T0to provide voltages V0, V1, V2, and V3from four corresponding conductive lines250′,251′,252′, and253′ to four conductive lines2500,2510,2520, and2530, respectively.

Driver circuit2401can use transistors T1to provide (e.g., to pass) voltages from conductive lines250′,251′,252′,253′, and254′ through254i′ to respective elements of block291. For example, driver circuit2401can use four of transistors T1to provide voltages V0, V1, V2, and V3from four corresponding conductive lines250′,251′,252′, and253′ to four conductive lines2501,2511,2521, and2531, respectively, of block291.

As shown inFIG. 2, transistor gates240T0and240T1are separate from each other. Thus, driver circuits2400and2401can separately use respective transistor gates240T0and240T1(e.g., separately activate respective signals BLKHVsel0and BLKHVsel1) to control (e.g., turn on or turn off) transistors T0and T1. Driver circuits2400and2401can be activated one at a time during a particular memory operation of memory device200.

For example, during a memory operation of memory device200, if block290is selected to be accessed (e.g., to operate on memory cells210,211,212, and213of block290) and block291is not selected (unselected) to be accessed, then signal BLKHVsel0can be activated by driver select circuit2450while signal BLKHVsel1is not activated (e.g., deactivated) by driver select circuit2451. In this example, transistors T0can be turned on (while transistors T1are turned off) to establish circuit paths (e.g., current paths) between conductive lines2500,2510,2520, and2530of memory cell block290(e.g., the selected block) and conductive lines250′,251′,252′, and253′ (e.g., through turned-on transistors T0), respectively. This allows voltages V0, V1, V2, and V3from respective conductive lines250′,251′,252′, and253′ to be applied to (e.g., to be passed to) respective conductive lines2500,2510,2520, and2530of block290through turned-on transistors T0. In this example, memory device200may establish no circuit paths (e.g., establish no current paths) between conductive lines2501,2511,2521, and2531of memory cell block291(e.g., the unselected block) and respective conductive lines250′,251′,252′, and253′ (because transistors T1are turned off). Thus, in this example, voltages V0, V1, V2, and V3from respective conductive lines250′,251′,252′, and253′ are not applied to (e.g., are not passed to) conductive lines2501,2511,2521, and2531of block291because transistors T1are turned off.

In another example, during a memory operation of memory device200, if block291(instead of block290as described in the above example) is selected to be accessed (e.g., to operate on memory cells210,211,212, and213of block291) and block290is not selected to be accessed, then signal BLKHVsel1can be activated by driver select circuit2451while signal BLKHVsel0is not activated (e.g., deactivated) by driver select circuit2450. In this example, transistors T1can be turned on while transistors T0are turned off. This allows voltages V0, V1, V2, and V3from respective conductive lines250′,251′,252′, and253′ to be applied to (e.g., to be passed to) respective conductive lines2501,2511,2521, and2531of block291through turned-on transistors T1. In this example, voltages V0, V1, V2, and V3from respective conductive lines250′,251′,252′, and253′ are not applied to (e.g., are not passed to) conductive lines2500,2510,2520, and2530because transistors T0are turned off.

Each of driver select circuits2450and2451can include elements (e.g., transistors and capacitors) similar to (or identical to) the elements of driver select circuits described in more detail with reference toFIG. 3throughFIG. 8. Improvements and benefits of memory device200over some conventional memory devices are also discussed below with reference toFIG. 3throughFIG. 8.

FIG. 3shows a schematic diagram of driver select circuit2450of memory device200ofFIG. 2, according to some embodiments described herein. For simplicity, only driver select circuit2450of memory device200ofFIG. 2is described in detail with respect toFIG. 3. Driver select circuit2451of memory device200ofFIG. 2includes elements and operations similar to the elements and operations of driver select circuit2450shown inFIG. 3. Thus, detailed description of driver select circuit2451ofFIG. 2is omitted from the description herein.

As shown inFIG. 3, driver select circuit2450can include transistors301,302,303,304, and305, and a capacitor C. Each of transistors301,303,304, and305can include an n-channel metal-oxide-semiconductor (NMOS) transistor. Transistor302can include a p-channel metal-oxide-semiconductor (PMOS) transistor. Transistor301can include a depletion-mode NMOS transistor, such that transistor301can have a negative threshold voltage Vt (Vt<0). Transistor303can include a depletion-mode NMOS transistor, such that transistor303can have a negative threshold voltage Vt (Vt<0). Alternatively, transistor303can include an enhancement mode NMOS transistor.

As shown inFIG. 3, driver select circuit2450can include nodes (e.g., power supply nodes)310,311,313, and316to receive voltages (e.g., voltage signals) Vcc, VPGMSW, VBSTRAP, and VCLAMP, respectively, and nodes (e.g., enable signal nodes)315and317to receive signals (e.g., enable signals) EN and EN*, respectively. Signals EN and EN* can be complementary signals (e.g., signal EN* is an inverted version of signal EN). Driver select circuit2450can also include a node (e.g., high-voltage node)340to provide voltage BLKHVsel0. Node340can be coupled (electrically coupled) to transistor gate240T0of transistors T0(FIG. 2). Thus, node340of driver select circuit2450and transistor gate240T0can be the same node (e.g., can be coupled to the same conductive region (e.g., conductive path)).

In operation, if block290(FIG. 2) is selected to store information in at least one of memory cells210,211,212, and213of block290, then signals EN and EN* can be provided with voltages (e.g., EN=Vcc, and EN*=0V) to turn on transistors305and302, respectively. Transistors301and302can operate to cause the value of voltage BLKHVsel′0at node312to be based on (e.g., to increase up to) the value of voltage VPGMSWat node311. Transistor304can include a gate coupled to node340, a terminal (e.g., a non-gate terminal (e.g., a drain)) coupled to node313, and a terminal (e.g., a non-gate terminal (e.g., a source)) coupled to node314. Transistor304can operate to pass voltage VBSTRAPto one conductive plate (e.g., the conductive plate coupled to node314) of capacitor C. Capacitor C can operate as bootstrap capacitor. Capacitor C and transistor304can operate to cause (to increase (e.g., to bootstrap)) the value of voltage BLKHVsel0at node340to be greater than the value of voltage BLKHVsel′0at node312. Voltage VCLAMPcan have a value less than the value of voltage VPGMSWby one threshold voltage value of transistor303. This may allow transistor303to form a conductive path from node312to node340and also to prevent the voltage (e.g., BLKHVsel0of at least 29V) at node340from drifting back to the voltage (e.g., BLKHVsel′0=26V) at node312.

During a write operation of memory device200, a relatively high value of voltage BLKHVsel0at node340allows transistors T0(FIG. 2) to properly pass a voltage (e.g., a programming voltage) from a conductive line (e.g., a selected global word line) among conductive lines (e.g., global word lines)250′,251′,252′, and253′ to a respective conductive line (e.g., a selected local word line) among conductive lines (e.g., local word lines)2500,2510,2520, and2530. This allows information to be properly stored in a memory cell (or memory cells) of block290.

FIG. 4is a timing diagram for some of the signals of memory device200ofFIG. 2and some of the voltages shown inFIG. 3during an example write operation of memory device200, according to some embodiments described herein. In the write operation associated withFIG. 4, it is assumed that block290(FIG. 2) is selected to store information (e.g., block291is not selected to store information). In the write operation associated withFIG. 4, it is also assumed that at least one of memory cells212(e.g., one memory cell212or multiple memory cells212) associated with conductive line2520(e.g., local word line) ofFIG. 2is selected to be accessed (e.g., selected to store information). Thus, in this example, conductive line2520(FIG. 2) can be called a selected conductive line (e.g., selected local word line). InFIG. 4, signal WL20is labeled “selected” to indicate that signal WL20is associated with selected conductive line2520(e.g., selected local word line).

In the example write operation ofFIG. 4, other memory cells210,211, and213(FIG. 2) associated with conductive lines2500,2510, and2530, respectively, are unselected (e.g., not selected) memory cells (e.g., memory cells that are not selected to store information). Thus, in this example, conductive lines2500,2510, and2530(FIG. 2) can be called unselected conductive lines (e.g., unselected local word lines). InFIG. 4, signals WL00, WL10, and WL30are labeled “unselected” to indicate that signals WL00, WL10, and WL30are associated with unselected conductive lines2500,2510, and2530, respectively.

In the description herein, the values (e.g., voltage values) of voltages being described (and shown in the drawings) are example values. However, actual values used in reality can be different from the values shown inFIG. 4.

InFIG. 4, times t0, t1, t2, and t3indicate different times during the example write operation. Information can be stored (e.g., programmed) in a selected memory cell (or memory cells) between times t2and t3.

As shown inFIG. 4, voltages V0, V1, V2, and V3associated with conductive lines250′,251′,252′, and253′ (FIG. 2) can be provided with different values depending on which of conductive lines250′,251′,252′, and253′ is a selected conductive line (e.g., selected global word line). A selected conductive line (e.g., selected global word line) among conductive lines250′,251′,252′, and253′ is the conductive line associated with (e.g., coupled to) a selected conductive line (e.g., selected local word line) among conductive lines2500,2510,2520, and2530through one of transistors T0(FIG. 2). Thus, in the example write operation ofFIG. 4, conductive line252′ (FIG. 2) is a selected conductive line (e.g., selected global word line). InFIG. 4, voltage V2is labeled “selected” to indicate that voltage V2is associated with selected conductive line252′ (e.g., selected global word line). Other conductive lines250′,251′, and253′ in the example write operation ofFIG. 4can be called unselected conductive lines (e.g., unelected global word lines). InFIG. 4, voltages V0, V1, and V3are labeled “unselected” to indicate that voltages V0, V1, and V3are associated with unselected conductive lines250′,251′, and253′ (e.g., unselected global word lines).

As shown inFIG. 4, voltage V2(e.g., associated with a selected global word line) can be provided with a programming voltage VPRGM(e.g., VPRGM=26V). Each of voltages V0, V1, and V3(e.g., associated with unselected global word lines) can be provided with a voltage VPASS(e.g., VPASS=10V). Thus, during a write operation of memory device200, one of conductive lines250′,251′,252′, and253′ can be provided with a voltage (e.g., V2=VPRGM=26V) that has a highest value (e.g., 26V) among values of voltages (e.g., voltages V0=V1=V3=10V and V2=26V) received at respective conductive lines250′,251′,252′, and253′.

Voltage VPGMSWcan be based on programming voltage VPRGM(e.g., VPGMSW=VPRGM). For example, VPGMSW=26V, which can be the same as the value of voltage V2(and the same as the value of programming voltage VPRGM=26V). Thus, during a write operation of memory device200, the value of voltage VPGMSWcan be no greater than (at most equal to) a highest value (e.g., the value of voltage V2) among values of the voltages (e.g., voltages V0=V1=V3=10V and V2=26V) received at respective conductive lines250′,251′,252′, and253′.

FIG. 4also shows labels VPGMSW=VPRGM, VPGMSW<VPRGM, and VPGMSW>VPRGMto indicate that the value of voltage VPGMSWcan alternatively be less than or greater than the value of programming voltage VPRGM.

Signals EN and EN* can be provided with 0V and the value of voltage Vcc, respectively, as shown inFIG. 4.

The value of voltage BLKHVsel′0is based on (e.g., follows) the value of voltage VPGMSW. As shown inFIG. 4, the value of voltage BLKHVsel′0can go up to the value of voltage VPGMSW(e.g., goes from 0V to 23V).

Voltage VCLAMPcan be provided with a value that is less than the value of voltage VPGMSW. For example, voltage VCLAMPcan be provided with a value such that VCLAMP=VPGMSW+Vt (where Vt is the threshold voltage of transistor303(FIG. 3)). As an example, if VPGMSW=26V and Vt=−3V, then VCLAMP=26V+Vt=26V−3V=23V (as shown inFIG. 4).

Voltage VBSTRAPcan be provided with a value less than the value of voltage VCLAMPand greater than the value of voltage Vcc. For example, the value of voltage VBSTRAPcan be 10V if the value of voltage Vcc is between 1V and 2V and the value of voltage VCLAMP=23V.

Voltages provided to signals WL00, WL10, WL20, and WL30can be based on voltages V0, V1, V2, and V3, respectively. For example, the value of a voltage on signal WL20can be up to the value of programming voltage VPRGM. As an example, the value of a voltage on signal WL20can go up to VPRGM=V2=26V.

The value of a voltage on each of signals WL00, WL10, and WL30can be based on the value of voltage VPASS. As an example, the value of a voltage on each of signals WL00, WL10, and WL30can go up to VPASS=10V.

In the example write operation ofFIG. 4, block291is not selected to store information. Thus, driver circuit2401(FIG. 2) can be deactivated (e.g., by turning off transistors T1) by providing a turned-off value (e.g., 0V) to voltage BLKHVsel1between times t0and t3(as shown inFIG. 4).

Voltage BLKHVsel0can depend on the values of voltage VPGMSW, voltage VCLAMP, threshold voltage Vt of transistor303, and the capacitance (e.g., coupling capacitance) at node340. Voltage BLKHVsel0can have a value greater than the value of voltage VPGMSW, such that BLKHVsel0can be at least (equal to or greater than) the sum of VPGMSW+Vx, where Vx is at least the absolute value of the threshold voltage Vt of transistor303. For example, if the value of voltage VPGMSWis 26V, and the value of threshold voltage Vt of transistor303is negative 3V (−3V), then the value of voltage BLKHVsel0can be 29V (26V+3V=29V) or greater than 29V.

As shown inFIG. 4, as voltage VBSTSAPramps up (e.g., between times t2and t3), voltage BLKHVsel0also ramps up through coupling. The amount of coupling can be dependent on the coupling ratio between capacitor C (FIG. 3) and the capacitance associated with transistors T0. The amount of coupling at node340can be proportional to the size (e.g., the capacitance) of capacitor C. Thus, the larger the size of capacitor C, the higher the amount of coupling at node340. As an example, if the capacitance of capacitor C and the capacitance associated with transistors T0are equal, then the coupling ratio can be approximately 50%. Thus, if capacitor C is formed from transistors and N=T (where N is the number of transistors that form capacitor C, and T is the number of transistors T0), then approximately 50% of voltage VBSTRAPat node313will contribute to (e.g., show up in) the value of voltage BLKHVsel0at node340. For example, if voltage VBSTRAP=10V, then 5V (50% of 10V) of voltage BLKHVsel0is from voltage VBSTRAP. In this example, if VPGMSW=26V, then BLKHVsel′0=26V, and BLKHVsel0can be increased from 26V (the value of voltage BLKHVsel′0) to 31V (26V+5V). Thus, inFIG. 4, the value of voltage BLKHVsel0can be 31V between times t2and t3.

Using driver select circuit2450ofFIG. 2andFIG. 3and the voltages shown inFIG. 4allows memory device200(FIG. 2) to have improvements and benefits over some conventional memory devices. Some such improvements and benefits are discussed below.

For example, some conventional memory devices may use a control voltage (e.g., a voltage similar to VPGMSW) and programming voltage (e.g., a voltage similar to V2=VPGMSW) during storing (programming) information in a memory cell. Such a control voltage in the conventional memory devices normally has a value (e.g., 29V) that is at least one threshold voltage (e.g., one Vt of transistors similar to transistors T0) greater than the value (e.g., 26V) of the programming voltage (e.g., the voltage applied to a selected word line associated with the memory cell being programmed). In such conventional memory devices, generating such a control voltage is unavoidably inefficient due to factors that may include junction loading each block in the memory device, and routing loading. Further, memory cell programming normally benefits from a relatively high programming voltage. However, in some conventional memory devices, providing such a high programming voltage can be challenging due to constraints such as poor charge pump efficiency, and to breakdown of components (e.g., complementary-metal-oxide semiconductor (CMOS) circuitries) needed to generate such a programming voltage.

In memory device200, the value of voltage VPGMSWat node311may be kept relatively low (e.g., 26V) in comparison to the value (e.g., 29V) of a similar voltage used in conventional memory devices. Although the value of voltage VPGMSWis kept relatively low, the value of voltage BLKHVsel0applied to transistor gate240T0can still be high enough (e.g., 29V or greater than 29V) to maintain proper operation of storing information in a memory cell in memory device200. For example, the value of voltage VPGMSWcan be selected to be relatively low, such as less than (or equal to) the value of programming voltage VPRGM. Although the value of voltage VPGMSWcan be selected to be less than or equal to the value of programming voltage VPRGM, the value of voltage VPGMSWcan also be selected to be greater than the value of programming voltage VPRGM. For example, VPGMSW=VPRGM+Vz, where Vz can be less than, equal to, or greater than the value of the threshold voltage of transistors T0.

The relatively low value of voltage VPGMSW(e.g., VPGMSW<BLKHVsel0) may improve efficiency in generating voltage VPGMSWin comparison to generation of a similar voltage in some conventional memory devices. Further, the relatively low value of voltage VPGMSWcan reduce stress associated with generation of voltage VPGMSW(e.g., reduce stress associated with a charge pump and signal path to node311) in comparison with generation of a similar voltage in some conventional memory devices. Moreover, in comparison with some conventional memory devices, power consumption (e.g., supply current Icc consumption) of memory device200may also be relatively low due to a relatively low value of voltage VPGMSW. Additionally, since the value of voltage BLKHVsel0can be relatively high (e.g., greater than 29V) in comparison with some conventional memory devices, the value of a voltage (e.g., V2=VPRGM) used to program a memory cell in memory device200can be greater than the value of a conventional programming voltage (thereby improving programming operation of memory device200) without exceeding current breakdown limits associated with programming voltage VPRGM.

FIG. 5shows a schematic diagram of driver select circuit5450that can be a variation of driver select circuit2450ofFIG. 3, according to some embodiments described herein. Driver select circuit5450can be used for each of driver select circuit2450and2451of memory device200ofFIG. 2. Thus, each of driver select circuit2450and2451of memory device200ofFIG. 2can include either elements (e.g., circuit elements) of driver select circuit2450ofFIG. 3(as described above) or elements (e.g., circuit elements) of driver select circuit5450ofFIG. 5.

As shown inFIG. 5, driver select circuit5450can include elements similar to or identical to the elements of driver select circuit2450ofFIG. 3. Thus, for simplicity, similar or identical elements are given the same labels and their descriptions are not repeated. Differences between driver select circuit2450(FIG. 3) and driver select circuit5450(FIG. 5) include the omission of transistor304, capacitor C, node313(that receives voltage VBSTRAP), and node314.

As described above with reference toFIG. 3andFIG. 4, transistor304and capacitor C can operate to cause (e.g., to increase) the value of voltage BLKHVsel0at node340(FIG. 3) to be greater than the value of voltage BLKHVsel′0at node312. The increased voltage (e.g., voltage BLKHVsel0), as described above, allows proper operation of storing information in a memory cell (or memory cells) of block290.

InFIG. 5, driver select circuit5450does not include transistor304and capacitor C. However, like driver select circuit2450ofFIG. 3, driver select circuit5450ofFIG. 5can also operate to cause (to increase (e.g., to bootstrap)) the value of voltage BLKHVsel0at node340to be greater than the value of voltage BLKHVsel′0at node312. The voltage increasing (e.g., bootstrapping) function in driver select circuit5450can be performed by a “built-in” coupling capacitor structure that is present in transistors T0(FIG. 2). For example, during a write operation of storing information in block290(FIG. 2), the coupling capacitor structure between transistor gate240T0(which is electrically coupled to node340) and the body of transistors T0can cause (increase (e.g., bootstrap)) the value of voltage BLKHVsel0at node340inFIG. 5to be at a value that is greater than the value of voltage BLKHVsel′0at node312(FIG. 5).

FIG. 6is a timing diagram for some of the signals of memory device200ofFIG. 2and some of the voltages shown inFIG. 5during an example write operation of memory device200if driver select circuit5450ofFIG. 5is used as driver select circuit2450ofFIG. 2, according to some embodiments described herein. The timing diagram ofFIG. 6is similar to the timing diagram ofFIG. 4. Thus, for simplicity, similar or identical elements (e.g., signals and voltages) inFIG. 4andFIG. 6are given the same labels and their descriptions are not repeated.

Differences betweenFIG. 4andFIG. 6include the timing (e.g., time intervals) at which voltages V0, V1, V2, and V3from corresponding conductive lines250′,251′,252′, and253′ are applied to (e.g., passed to) respective conductive lines2500,2510,2520, and2530. For example, as shown inFIG. 6, the value of voltage BLKHVsel0increases from 26V at time t2(which is the same as the value of voltage BLKHVsel′0=26V at time t2) to a value greater than 26V (e.g., 31V or greater) after time t2(e.g., between times t2and t3). The value (e.g., 31V or greater) and timing of voltage BLKHVsel0ofFIG. 6can be similar to the value and timing, respectively, of voltage BLKHVsel0ofFIG. 4. However, unlikeFIG. 4, the values of voltages V0, V1, V2, and V3inFIG. 6can be maintained at 0V between times t0and t2and may not be allowed to increase until time t2. For example, as shown inFIG. 6, voltage V2(e.g., associated with a selected global word line) starts to increase from 0V at time t2to 26V after time t2, and voltages V0, V1, and V3(e.g., associated with unselected global word lines) start to increase from 0V at time t2to 10V after time t2.

Thus, as shown inFIG. 6, voltages V0, V1, V2, and V3can be provided to conductive lines250′,251′,252′, and253′ after the value of voltage BLKHVsel0reaches (e.g., at time t2) the value of voltage BLKHVsel′0. In comparison, voltages V0, V1, V2, and V3inFIG. 4can be provided to conductive lines250′,251′,252′, and253′ before the value of voltage BLKHVsel0reaches (e.g., at time t2) the value of voltage BLKHVsel′0.

Thus, as shown inFIG. 6, the application (e.g., passing) of voltages V0, V1, V2, and V3from corresponding conductive lines250′,251′,252′, and253′ to respective conductive lines2500,2510,2520, and2530can be delayed until after the value of voltage BLKHVsel0reaches the value of voltage BLKHVsel′0at time t2. As shown inFIG. 6, the value of voltage BLKHVsel′0can be at its highest value (e.g., 26V, which can also be the highest value of voltage VPGMSWat time t2). Delaying the application (e.g., the passing) of voltages V0, V1, V2, and V3from corresponding conductive lines250′,251′,252′, and253′ to respective conductive lines2500,2510,2520, and2530as described here allows proper operation of the driver circuit (e.g., driver circuit2400inFIG. 2) associated with a selected block during a write operation of memory device200. In comparison with some conventional memory devices, driver select circuit5450allows memory device200to have improvements and benefits similar to those of driver select circuit2450described above with reference toFIG. 3andFIG. 4.

FIG. 7shows a structure of a portion of memory device700including a structure of capacitor C of driver select circuit7450, according to some embodiments described herein. Memory device700can include elements similar to (or identical to) the elements of memory device200. For example, driver circuit2400and driver select circuit7450can include elements similar to (or identical to) the elements of driver circuit2400and driver select circuit2450, respectively, ofFIG. 2. For simplicity, similar or identical elements between memory devices200and700are given the same labels (e.g., same reference numbers). Also for simplicity and to not obscure the embodiments described herein, some of the elements of memory device700are schematically (instead of structurally) shown inFIG. 7. Such elements (shown schematically inFIG. 7) include driver circuit2400, and part of driver select circuit7450including transistor304, node313(that receive voltage VBSTRAP), node314, and node340. InFIG. 7, node340is labeled twice for easy of following the connection of node340with other circuit elements of memory device700.

FIG. 7shows a side view (in the x-z directions) of a structure of a portion of block290of memory device700. As shown inFIG. 7, memory device700can include a substrate790, which can be a semiconductor substrate. For example, substrate790can include an n-type or p-type semiconductor material (e.g., an n-type or p-type silicon substrate).

Memory device700includes different levels (e.g., tiers)709through714with respect to a z-direction, which extends in a direction of the thickness of substrate790.FIG. 7also shows an x-direction, which is perpendicular to the z-direction. Levels709through714are internal physical levels (e.g., physical tiers arranged vertically in the z-direction) of memory device700.

Memory device700can include a group of semiconductor structures through7840located in respective levels709through714. Semiconductor structures779through7840can be electrically separate layers of semiconductor materials. Semiconductor structures779through7840can include conductively doped polysilicon (e.g., polysilicon doped with impurities (e.g., n-type or different types of impurities)) or other conductively doped semiconductor materials. Thus, each of semiconductor structures779through7840can include n-type (or p-type) polysilicon. Memory device700can also include dielectric materials (e.g., silicon dioxide) interleaved with (e.g., located in the spaces between the layers of) semiconductor structures779through7840. Such dielectric materials are not shown inFIG. 7for simplicity. Each of semiconductor structures779through7840can form portions of respective conductive lines (e.g., local access lines or local word lines)2500,2510,2520, and2530in block290.

Memory device700can include a group of semiconductor structures779′ through784′0located in respective levels709through714. Semiconductor structures779′ through784′0can be electrically separate layers of semiconductor materials. Semiconductor structures779′ through784′0are electrically separated from (e.g., electrically uncoupled to) semiconductor structures779through784′0by a gap795. Thus, gap795can be a location between semiconductor structures779′ through784′0and semiconductor structures779through784′0. Gap795can be located at the edge of block290. Gap795can be filled with dielectric material (e.g., silicon dioxide, not shown). Semiconductor structures779through7840and semiconductor structures779′ through784′0can be formed (e.g., deposited) from the same materials (e.g., the same semiconductor materials) and the same process steps (e.g., formed at the same time). Gap795can be formed by removing (e.g., by cutting) a portion (e.g., portion at gap795) of the materials that form semiconductor structures779through7840and779′ through784′0. Semiconductor structures779′ through784′0may be an excess portion (e.g., an unused portion) of the materials that form conductive lines2500,2510,2520, and2530. Thus, semiconductor structures779′ through784′0are not part of conductive lines2500,2510,2520, and2530of block290. As described below, semiconductor structures779′ through784′0can be used to form parts (e.g., conductive plates) of capacitor C (or a multiple of capacitor C) of driver select circuit7450of memory device700.

As shown inFIG. 7, memory cells210,211,212, and213of memory cell string230of block290can be located in levels710,711,712, and713, respectively (e.g., arranged vertically in the z-direction with respect to substrate790). Memory cells210,211,212, and213can be structured as floating gate memory cells, charge trap memory cells, or other types of non-volatile memory cells.

For simplicity, only two data lines270and271of memory device700are shown inFIG. 7. Data lines270and271can include conductive materials that are formed over semiconductor structures779through7840(e.g., formed above level714of memory device700). Each of data lines270and271can have a length extending in the y-direction that is perpendicular to the x-direction and z-direction.

Line (e.g., source)299of memory device700can include a conductive material and have a length extending in the x-direction. Source299can be formed under semiconductor structures779through7840(e.g., formed below level709of memory device700).FIG. 7shows an example where source299can be formed over a portion of substrate790(e.g., by depositing a conductive material over substrate790). Alternatively, source299can be formed in or formed on a portion of substrate790(e.g., by doping a portion of substrate790).

Driver circuit2400of memory device700can be located in (e.g., formed in or formed on) substrate790and below the level709. Thus, driver circuit2400can be formed under semiconductor structures779through7840(e.g., formed under the memory cell strings of memory device700). For simplicity, connections between driver circuit2400and other components (e.g., conductive lines2500,2510,2520, and2530) are not shown inFIG. 7. Substrate790can include other circuitry (not shown inFIG. 7) of memory device700such as decoders, and sense and buffer circuitry.

As shown inFIG. 7, memory device700can include pillars (e.g., vertical columns of materials)730and731. Each of pillars730and731can have a length extending through semiconductor structures779through7840in the z-direction. During processes of forming memory device700, semiconductor structures779through7840can be formed (e.g., deposited one after another in the z-direction over substrate790). Then, holes can be formed (e.g., vertically formed in the z-direction) through semiconductor structures779through7840. After the holes are formed, pillars730and731can be formed (e.g., vertically formed in the z-direction) in the holes. As shown inFIG. 7, pillars730and731can contact (e.g., can be electrically coupled to) source299.

Pillar730can include a conductive material contacting data line270and source299. Pillar730can form part of a body of memory cell string230, and bodies of two respectively select transistors261and264(e.g., source select transistor and drain select transistors, respectively) coupled to memory cell string230. During a memory operation of memory device700, pillar730can form a current path (e.g., a conductive channel) between data line270and source299(through respective bodies of select transistors261and264and memory cell string230).

Similarly, pillar731can include a conductive material contacting data line271and source299. Pillar731can form part of a body of memory cell string231, and bodies of two respectively select transistors261and264(e.g., source select transistor and drain select transistors, respectively) coupled to memory cell string231. During a memory operation of memory device700, pillar731can form a current path (e.g., a conductive channel) between data line271and source299(through respective bodies of select transistors261and264and memory cell string231).

As shown inFIG. 7, conductive lines2500,2510,2520, and2530(associated with signals WL00, WL10, WL20, and WL30) and respective memory cells210,211,212, and213can be located in levels710,711,712, and713, respectively, along a portion (e.g., the segment extending from level710to level713) of each of pillars730and731.

Select line (e.g., drain select line)2840can be formed over conductive lines2500,2510,2520, and2530. Select line2840can be formed from a portion of semiconductor structure7840. As shown inFIG. 7, select line2840and associated select transistors264can be located along a portion (e.g., the segment at level714) of each of pillars730and731.

Select line (e.g., source select line)2800can be formed under conductive lines2500,2510,2520, and2530. Select line2800can be formed from a portion of semiconductor structure779. As shown inFIG. 7, select line2800and associated select transistors261can be located along a portion (e.g., the segment at level709) of each of pillars730and731.

As mentioned above, semiconductor structures779′ through784′0can be used to form parts (e.g., conductive plates) of capacitor C (or a multiple of capacitor C) of driver select circuit7450of memory device700. Capacitor C can correspond to capacitor C of driver select circuit2450ofFIG. 3. As shown inFIG. 7, capacitor C can include conductive plates760and761that can be formed from two of semiconductor structures779′ through784′0. For example, conductive plates760and761can be formed from semiconductor structures782′ and783′, respectively. The dielectric of capacitor C can be the dielectric material (not labeled) between semiconductor structures782′ and783′.FIG. 7shows an example where each of capacitor plates760and761includes (e.g., can be formed from) a single (e.g., only one) semiconductor structure among semiconductor structures779′ through784′0. Alternatively, each of capacitor plates760and761can include (e.g., can be formed from) multiple semiconductor structures among semiconductor structures779′ through784′0. For example, capacitor plate760can include (e.g., can be formed from) two or three of semiconductor structures779′,781′, and783′ (e.g., odd layers of semiconductor structures779′ through784′0) and capacitor plate761can include (e.g., can be formed from) two or three of semiconductor structures780′,782′, and784′ (e.g., even layers of semiconductor structures779′ through784′0). In this example, semiconductor structures781′ and783′ (or779′,781′, and783′) can be electrically coupled (e.g., shorted) to each other to form capacitor plate760, and semiconductor structures780′ and782′ (or780′,782′, and784′) can be electrically coupled (e.g., shorted) to each other to form capacitor plate761.

As shown inFIG. 7, conductive plates760and761of capacitor C can be coupled (e.g., electrically coupled) to other components of driver select circuit7450through conductive paths760′ and761′, respectively. For example, conductive paths760′ and761′ can be coupled to nodes340and314, respectively. Each of conductive paths760′ and761′ can include a combination of different portions that can include vertical and horizontal conductive segments (not labeled) as shown inFIG. 7. A horizontal conductive segment can have length extending in the x-direction (e.g., parallel to substrate790). A vertical conductive segment can have length extending in the z-direction (e.g., perpendicular to substrate790). As shown inFIG. 7, each of conductive paths760′ and761′ can include a portion (e.g., a vertical conductive segment) going through a location where gap795is located. The vertical and horizontal conductive segments of each of conductive paths760′ and761′ can be formed from conductive material (e.g., conductively doped polysilicon, metal, or other conductive materials).

FIG. 7shows memory device700including one capacitor C as an example. However, memory device700can include a multiple of capacitor C, each with a similar structure, that can be formed from semiconductor structures779′ through784′0and the dielectric materials between semiconductor structures779′ through784′0. In comparison with some conventional memory devices, memory device700can have improvements and benefits similar to those of memory device200described above with reference toFIG. 2throughFIG. 4.

FIG. 8shows a structure of a portion of a memory device800including a structure of a driver circuit8400and a capacitor C of driver select circuit8450, according to some embodiments described herein. Memory device800can include elements similar to (or identical to) the elements of memory device200. For example, driver circuit8400and driver select circuit8450can include elements similar to (or identical to) the elements of driver circuit2400and driver select circuit2450, respectively, ofFIG. 2. For simplicity, similar or identical elements between memory devices200and800are given the same labels (e.g., same reference numbers). Also for simplicity and to not obscure the embodiments described herein, some of the elements of memory device800are schematically (instead of structurally) shown inFIG. 8. Such elements (shown schematically inFIG. 8) part of driver select circuit8450including transistor304, node313(that receive voltage VBSTRAP), node314, and node340. InFIG. 8, node340is labeled twice for easy of following the connection of node340with other circuit elements of memory device800.

FIG. 8shows a side view (in the x-z directions) of a structure of a portion of memory device800including a side view of a portion of block290. Part of the structure of memory device800is similar to (or identical to) part of the structure of memory device700. Thus, for simplicity, similar or identical elements between memory devices700and800are given the same labels (e.g., same reference numbers) and their descriptions are not repeated.

As shown inFIG. 8, memory device800can include conductive segments820z,821z,822z, and823z(e.g., vertical segments extending in the z-direction) contacting respective conductive lines (e.g., local word lines)2500,2510,2520, and2530, and conductive contacts820c,821c,822c, and823ccoupled to respective transistors T0of driver circuit8400. As shown inFIG. 8and described below, transistors T0of part of driver circuit8400can be formed vertically with respect to substrate790. Thus, driver circuit8400can be called a vertical string driver circuit (e.g., to access memory cell strings (e.g.,230and231inFIG. 8)) of block290.

Memory device800can include a group of conductive structures (e.g., electrically separated layers of conductive materials)851through856and a group of conductive structures (e.g., electrically separated layers of conductive materials)851′ through856′ located in (e.g., stacked vertically over) corresponding levels815through820of memory device800. Levels815through820are above levels709through714with respect to substrate790. Conductive structures851′ through856′ are electrically separated from (e.g., electrically uncoupled to) conductive structures851through856by a gap895. Thus, gap895can be a location between conductive structures851′ through856′ and conductive structures851through856. Gap895can be filled with a dielectric material (e.g., silicon dioxide, not shown). Conductive structures851through856can be part of driver circuit84000f memory device800. Conductive structures851′ through856′ can be used to form parts (e.g., conductive plates) of capacitor C (or a multiple of capacitor C) of driver select circuit8450of memory device800.

Conductive structures851through856and851′ through856′ can include conductively doped polysilicon (e.g., n-type or p-type polysilicon), metals, or other conductive materials. Memory device800can include dielectric materials (e.g., not labeled), interleaved with (e.g., located in the spaces between) conductive structures851through856. Memory device800can also include dielectric materials (e.g., not labeled), interleaved with (e.g., located in the spaces between) conductive structures851′ through856′. Examples of such dielectric materials (interleaved with conductive structures851through856and851′ through856′) include silicon dioxide.

Conductive structures851through856and851′ through856′ can be formed (e.g., deposited) from the same materials (e.g., semiconductor materials (e.g., polysilicon)) and the same process steps (e.g., formed at the same time). Gap895can be formed by removing (e.g., by cutting) a portion (e.g., portion at gap895) of the materials that form conductive structures851through856and851′ through856′.

As shown inFIG. 8, memory device800can include pillars840p,841p,842p, and843pcoupled to conductive lines2500,2510,2520, and2530, respectively, through respective conductive contacts820c,821c,822c, and823cand respective conductive segments820z,821z,822z, and823z. Each of pillars840p,841p,842p, and843pcan have length extending in the z-direction (e.g., extending vertically with respect to substrate790) through conductive structures851through856and through the dielectric materials (e.g., silicon dioxide) that are interleaved with conductive structures851through856. Pillars840p,841p,842p, and843pcan be part of (e.g., transistor bodies of) respective transistors T0(transistors T0are also schematically shown inFIG. 2). Part of conductive structures851through856can be used as control gates (e.g., transistor gates) to control transistors T0(e.g., to concurrently turn on transistors T0or to concurrently turn off transistors T0). For simplicity, only four transistors T0of driver select circuit8450are shown inFIG. 8. Other transistors T0of driver select circuit8450(e.g., transistors T0that are coupled to select lines2800and2840) are not shown inFIG. 8.

Memory device800can include connections (e.g., conductive connections that can include conductive segments851zthrough856z,851xthrough856x, and856u) to form conductive paths between respective conductive structures851through856and driver select circuit8450. For example, memory device800can include a conductive connection that can include conductive segments856z(e.g., a vertical segment in the z-direction),856x(e.g., a horizontal segment in the x-direction), and856u(e.g., a vertical segment in the z-direction) and conductive contact856ccoupled between conductive structure856and driver select circuit8450. Horizontal conductive segments851xthrough855x(and vertical conductive segments similar to conductive segment856u) coupled to respective conductive segments851zthrough855zare hidden from the view ofFIG. 8.

As mentioned above, conductive structures851′ through856′ can be used to form parts of capacitor C (or a multiple of capacitor C) of driver select circuit8450. Capacitor C can correspond to capacitor C of driver select circuit2450ofFIG. 3. As shown inFIG. 8, capacitor C can include conductive plates860and861that can be formed from two of conductive structures851′ through856′. For example, conductive plates860and861can be formed from conductive structures851′ and852′, respectively. The dielectric of capacitor C can be the dielectric material (not labeled) between conductive structures851′ and852′.FIG. 8shows an example where each of capacitor plates860and861includes (e.g., can be formed from) a single (e.g., only one) conductive structure among conductive structures851′ through856′. Alternatively, each of capacitor plates860and861can include (e.g., can be formed from) multiple conductive structures among conductive structures851′ through856′. For example, capacitor plate860can include (e.g., can be formed from) two or three of conductive structures851′,853′, and855′ (e.g., odd layers of conductive structures851′ through856′) and capacitor plate861can include (e.g., can be formed from) two or three of conductive structures852′,854′, and856′ (e.g., even layers of conductive structures851′ through856′). In this example, conductive structures851′ and853′ (or851′,853′, and855′) can be electrically coupled (e.g., shorted) to each other to form capacitor plate860, and conductive structures852′ and854′ (or852′,854′, and856′) can be electrically coupled (e.g., shorted) to each other to form capacitor plate861.

As shown inFIG. 8, conductive plates860and861of capacitor C can be coupled (e.g., electrically coupled) to other components of driver select circuit8450through conductive paths860′ and861′, respectively. For example, conductive paths860′ and861′ can be coupled to nodes340and314, respectively. Each of conductive paths860′ and861′ can include a combination of different portions that can include vertical and horizontal conductive segments (not labeled) as shown inFIG. 8. A horizontal conductive segment can have length extending in the x-direction (e.g., parallel to substrate790). A vertical conductive segment can have length extending in the z-direction (e.g., perpendicular to substrate790). As shown inFIG. 8, each of conductive paths860′ and861′ can include a portion (e.g., a vertical conductive segment) going through a location where gap895is located. The vertical and horizontal conductive segments of each of conductive paths860′ and861′ can be formed from conductive material (e.g., conductively doped polysilicon, metal, or other conductive materials).

FIG. 8shows memory device800including one capacitor C as an example. However, memory device800can include a multiple of capacitor C, each with a similar structure, that can be formed from conductive structures851′ through856′ (and the dielectric materials between conductive structures851′ through856′). In comparison with some conventional memory devices, memory device800can have improvements and benefits similar to those of memory device200described above with reference toFIG. 2throughFIG. 4

The illustrations of apparatuses (e.g., memory devices100,200,700, and800) and methods (e.g., operating methods associated with memory devices100,200,700, and800) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device (e.g., any of memory devices100,200,700, and800) or a system (e.g., a computer, a cellular phone, or other electronic systems) that includes a device such as any of memory devices100,200,700, and800.

Any of the components described above with reference toFIG. 1throughFIG. 8can be implemented in a number of ways, including simulation via software. Thus, apparatuses (e.g., memory devices100,200,700, and800or part of each of these memory devices, including a control unit in these memory devices, such as control unit118(FIG. 1)) described above may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single- and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired and/or as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

Memory devices100,200,700, and800may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference toFIG. 1throughFIG. 8include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate. Other embodiments including additional apparatuses and methods are described.

In the detailed description and the claims, a list of items joined by the term “one of” can mean only one of the listed items. For example, if items A and B are listed, then the phrase “one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase “one of A, B, and C” means A only, B only, or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

In the detailed description and the claims, a list of items joined by the term “at least one of” can mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only, B only, or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B, and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A. B. and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.