Digital-to-analog converter having enhanced current steering and associated method

A digital-to-analog converter includes a plurality of current cells, at least one cell in one embodiment including a pair of bipolar current switching transistors connected to a current source and a current summing bus in a current steering configuration so that one transistor is off while the other transistor is on. A temperature compensated control circuit is included for controlling the difference in base-emitter voltages of the bipolar current switching transistors based upon a temperature dependent bias voltage to compensate for a thermal voltage of the bipolar transistors. The temperature compensated control circuit preferably comprises a proportional to absolute temperature (PTAT) current source, and a steering pair of transistors connected to the PTAT current source and the pair of bipolar current switching transistors. The PTAT current source and steering transistors effectively bias the current switching transistors to account for the thermal voltage of the bipolar transistors. Method aspects of the invention are also disclosed.

FIELD OF THE INVENTION 
The present application relates to the field of electronic circuits, and 
more particularly, to a digital-to-analog converter (DAC) and method for 
operating the DAC. 
BACKGROUND OF THE INVENTION 
Digital-to-analog converters are widely used for converting digital signals 
to corresponding analog signals for many electronic circuits. For example, 
a high resolution, high speed digital-to-analog converter (DAC) may find 
applications in cellular base stations, wireless communications, direct 
digital frequency synthesis, signal reconstruction, test equipment, high 
resolution imaging systems and arbitrary waveform generators, for example. 
An integrated circuit DAC is described, for example, in U.S. Pat. No. 
3,961,326 to Craven entitled "Solid State Digital to Analog Converter". 
The DAC includes binarily scaled constant current sources with associated 
switch cells employing bipolar transistors to direct the bit currents 
either to a current summing bus or to ground. Each of the switch cells 
includes a first differential transistor pair driving a second 
differential pair of current switching transistors. 
Unfortunately when a DAC switches from one code to the next there typically 
exists some asymmetry in the speed that the bit switch turns on and turns 
off. This results in the output of the DAC going in the wrong direction 
for a short time until all of the switches have fully switched. The 
resulting error or glitch in the output is code dependent and thus 
produces harmonic distortion or other nonharmonic spurs in the output 
spectrum. Glitch is often tested at the major carry of the DAC and there 
will be a spike in the output as the DAC switches. Glitch is typically 
considered as the net area under that spike. 
There have been attempts to further reduce glitch in a DAC and thereby 
reduce harmonic distortion and other spurs in the output spectrum. For 
example, a DAC for video applications is disclosed in an article entitled 
"A Low Glitch 10-bit 75-MHz CMOS Video D/A Converter" by Wu et al. in the 
IEEE Journal of Solid-State Circuits, Vol. 30, No. 1, January 1995. The 
DAC includes a segmented antisymmetric switching sequence and an 
asymmetrical switching buffer. The DAC includes a large number of 
non-weighted current sources for the seven most significant bits, and 
weighted current sources for the three least significant bits. The current 
sources may be nonuniform for various reasons, such as layout mismatch, 
thermal distribution, and process deviation. A segmented antisymmetric 
switching sequence is disclosed to suppress the superposition of graded 
error, symmetrical error, and especially random error. The current cell 
includes a cascode current source and an asymmetrical switching buffer. 
The asymmetrical switch control avoids simultaneously turning off the 
differential switching transistors completely, but allow simultaneous 
turn-on for a short period of time. The current cell is disclosed as 
producing a glitch error of less than about 3.9 pVs. 
Another DAC is disclosed in an article by Bastiaansen et al. entitled "A 
10-b 40-MHz 0.8-um CMOS Current-Output D/A Converter" in IEEE Journal of 
Solid-State Circuits, Vol. 26, No. 7, July 1991. The DAC is based on 
current division and current switching. Monotonicity of the converter 
requires that the integral nonlinearity (INL) be less than .+-.0.5 LSB. 
Unfortunately, this places high demands on upon the matching of the 
current sources. Ten binary-weighted currents have to be generated. These 
currents are generated by a combination of 1024 equally sized MOS current 
sources. To reduce the influence of the output capacitance of the current 
sources, cascode stages are added. The ten binary-weighted currents are 
switched to either the output rail or the dump rail by two way current 
switches. The current switches are connected to the outputs of level-shift 
stages, which, in turn, are controlled by the digital input data stored in 
a data register. 
An article entitled "A 16-b D/A Converter with Increased Spurious Free 
Dynamic Range" by Mercer in the IEEE Journal of Solid-State Circuits, Vol. 
29, No. 10, October 1994, pp. 1180-1185 discloses another DAC. The article 
identifies the two broad categories of errors or distortion in 
digital-to-analog conversion. Segmentation of the bits and laser trimming 
of thin film resistors are often used to minimize static errors. Dynamic 
or AC errors include nonlinear settling, ringing, nonsymmetric slew, and 
glitch. Thermometer decoding of the most significant bits along with 
high-speed process technologies are often employed to minimize the dynamic 
errors. Segmentation of the four most significant bits into 15 currents of 
equal sized is disclosed. An R/2R ladder is used with the 12 current 
sources for the least significant bits. Laser trimmable thin-film 
resistors are used in the DAC current sources to allow trimming to reduce 
linearity errors. 
Unfortunately, despite continued improvements in DAC accuracy and operating 
speed, errors may still significantly effect linearity of the DAC. For 
example, non-linearities may arise from insufficient current steering 
between the current switching transistors particularly over a relatively 
wide operating temperature. In other words, particularly for bipolar 
current switching transistors, the current through the off transistor may 
be relatively high at higher temperatures thereby reducing linearity. 
SUMMARY OF THE INVENTION 
In view of the foregoing background, it is therefore an object of the 
present invention to provide a digital-to-analog converter and related 
method for having high accuracy and linearity over a relatively wide 
operating temperature. 
These and other objects, advantages and features of the present invention 
are provided by a digital-to-analog converter comprising a plurality of 
current cells, at least one cell including a pair of bipolar current 
switching transistors connected to a current source and a current summing 
bus in a current steering configuration so that one transistor is off 
while the other transistor is on, and temperature compensated control 
means for controlling a difference in base emitter voltages of the bipolar 
current switching transistors based upon a temperature dependent bias 
voltage to compensate for a thermal voltage of the bipolar transistors. 
The temperature compensated control means preferably comprises a 
proportional to absolute temperature (PTAT) current source, and a pair of 
steering transistors and associated bias resistors connected to the PTAT 
current source and the pair of bipolar current switching transistors. The 
PTAT current source and steering transistors effectively bias the current 
switching transistors to account for the thermal voltage of the bipolar 
transistors so that a predetermined high degree of current steering can be 
achieved over a relatively wide temperature range and while using a 
relatively low differential control voltage dependent on the temperature. 
A buffer stage may be connected between the pair of steering transistors 
and the pair of current switching transistors. For example, the buffer 
stage may be provided by a pair of buffer transistors and associated 
constant current sources connected thereto. 
The plurality of current cells of the DAC may be arranged in a split 
architecture with a first group of current cells for a first number of 
least significant bits and second group of current for a second number of 
most significant bits. Accordingly, each of the current cells for the 
second group of current cells may comprise the current source, the pair of 
bipolar current switching transistors, and the temperature compensated 
control means as described above. The DAC may also include a resistor 
network connected between the first group of LSB current cells and the 
current summing bus. 
The DAC may also include a master register receiving the digital inputs, a 
data buffer and level shifter connected to the master register, and a 
slave register connected to the data buffer and level shifter. The digital 
input means preferably further comprises a decoder connected between the 
data buffer and level shifter and slave register for the second group of 
current cells for the most significant bits. 
The concepts of the present invention may be adapted to a current cell 
including other than bipolar current switching transistors. For example, 
the current cell may include temperature compensated control means for 
controlling the difference in transistor control voltages of the current 
switching transistors based upon a temperature dependent bias voltage to 
compensate for the thermally dependent voltage of the transistors. 
A method aspect of the present invention is for steering current in a 
current cell comprising a pair of current switching transistors connected 
together in a current steering configuration so that one transistor is off 
while the other transistor is on, and with the pair of current switching 
transistors having a proportion of current steering based upon a 
difference in transistor control voltage and also based upon a thermally 
dependent voltage. The method preferably comprises the steps of: supplying 
a current to the pair of current switching transistors for steering; and 
controlling the difference in transistor control voltages of the current 
switching transistors based upon a temperature dependent bias voltage to 
compensate for the thermally dependent voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The present invention will now be described more fully hereinafter with 
reference to the accompanying drawings, in which preferred embodiments of 
the invention are shown. This invention may, however, be embodied in many 
different forms and should not be construed as limited to the embodiments 
set forth herein. Rather, these embodiments are provided so that this 
disclosure will be thorough and complete, and will fully convey the scope 
of the invention to those skilled in the art. Like numbers refer to like 
elements throughout. 
Referring to FIG. 1, the integrated circuit digital-to-analog converter 
(DAC) 20 in accordance with the invention is first described. The 
illustrated DAC 20 includes a substrate 21 and a plurality of circuit 
portions for converting a 12-bit digital input to an analog output signal 
as described in greater detail below. 
More particularly, the DAC 20 includes a 12-bit master register 24 for 
receiving the digital input signals wherein the least significant bit 
(LSB) is D0 and the most significant bit (MSB) is D11. The 12-bit master 
register feeds a data buffer/level shifter 25 as would be readily 
understood by those skilled in the art. The first eight bits from the data 
buffer/level shifter 25 are connected to the illustrated slave register 
27. The upper four bits pass through a 4-bit decoder 28 and provide 
fifteen outputs to the input of the slave register 27 in the illustrated 
embodiment. A clock input signal drives the 12-bit master register 24 and 
drives the slave register 27 via the illustrated inverter 30. A plurality 
of other terminals are provided including AV.sub.EE, AGND, DV.sub.EE, DGND 
and V.sub.CC as illustrated on the lower left hand portion of the 
schematic diagram of FIG. 1 as would be readily understood by those 
skilled in the art. 
The illustrated DAC 20 includes a split architecture wherein the eight LSBs 
are directed to a first block of current cells 31 which, in turn, are 
connected to the illustrated R/2R resistor ladder 32. The four MSBs are 
directed to the illustrated block of fifteen switched current cells with a 
temperature bias 33. In slightly different terms, the architecture employs 
a split R/2R ladder 32 and segmented switching current cell arrangement to 
reduce glitch. Bits DO (least significant bit) through D7 may directly 
drive the typical R/2R network 32 to create the binary weighted current 
sources. Bits D8 through D11 pass through a so-called thermometer decoder 
28 that converts the incoming data into fifteen individual segmented 
current source enables as would be readily understood by those skilled in 
the art. This split architecture of the DAC 20 also helps to reduce 
glitch, thus resulting in a more constant glitch characteristic across the 
entire output transfer function. 
Those of skill in the art will readily appreciate the operation of the 
illustrated overdriveable voltage reference 35, reference cell 36, 
amplifier 37, and 25 ohm resistor 38. These circuit portions provide the 
illustrated reference output REF OUT, reference set R.sub.SET, control 
output CTRL OUT, and control input CTRL IN. The reference cell 36 is 
connected in a feedback configuration using amplifier 37 to establish the 
precision reference for the switched current cells 31 and 33. 
Turning now additional to the schematic circuit diagram of FIG. 2 a 
switched current cell 40 in accordance with the present invention is 
further described. As will be readily appreciated by those skilled in the 
art, the current cell 40 is preferably used for at least the block of four 
MSBs 33, and more preferably for the block of LSBs 31 as well. 
The illustrated current cell 40 includes a pair of differentially connected 
bipolar current switching transistors Q1, Q2 having their emitters 
connected to the illustrated precision current source 42 for generating 
the current I1. As would be readily understood by those skilled in the 
art, the transistors Q1, Q2 are connected in a current steering 
configuration wherein the transistors are alternately conducting dependent 
upon the difference in the base-emitter voltages. The two transistors Q1, 
Q2 may be considered to be oppositely symmetrical wherein when one 
transistor is on, the other is off, and wherein each has the same low and 
high values as disclosed in U.S. Pat. No. 3,961,326 to Craven, the entire 
disclosure of which is incorporated herein by reference in its entirety. 
As would be readily understood by those skilled in the art, for the case of 
bipolar transistors and wherein transistor Q1 is off and transistor Q2 is 
conducting, the ratio of current steering or IC1/IC2 is given by: 
EQU I.sub.C1 /I.sub.C2 .congruent.e.DELTA.V.sub.BE /V.sub.T 
where .DELTA.V.sub.BE is the difference in the base-emitter voltages of the 
two transistors Q1, Q2, and V.sub.T is the thermal voltage of the 
transistors. The thermal voltage V.sub.T =kT/q where k is Boltzman's 
constant, T is the absolute temperature, and q is the electronic charge as 
would be readily appreciated by those skilled in the art. 
To provide substantially complete current steering, IC1/IC2 is preferably 
less than or equal to about 6 parts per million (ppm), for example. 
Letting the current ratio be equal to 6 ppm in the above equation, the 
ratio of .DELTA.V.sub.BE /V.sub.T is equal to 12. TABLE 1 below summarizes 
the desired .DELTA.V.sub.BE for the given operating temperatures and 
corresponding thermal voltages V.sub.T. 
TABLE 1 
______________________________________ 
TEMP (.degree.C.) 
V.sub.T (mv) 
.DELTA.V.sub.BE (mv) 
______________________________________ 
125 33 400 
25 25 300 
-40 20 240 
______________________________________ 
Most conventional current switches are designed so that at 25.degree. C., 
300 mv is used to switch the bipolar transistors Q1, Q2, Unfortunately, at 
the higher operating temperature of 125.degree. C., the 300 mv signal is 
insufficient to provide the relatively low 6 ppm error in the current 
steering ratio. Accordingly, a conventional current switching cell will 
have increased error at the higher temperature based upon the thermal 
voltage of the bipolar transistors. 
The present invention compensates for the thermal voltage V.sub.T by 
providing a bias to the base-emitter voltages of the current switching 
bipolar transistors Q1, Q2 based upon temperature. In particular, the bias 
is provided via the pair of illustrated differential steering transistors 
Q3, Q4, resistors R1, R2, and the proportional to absolute temperature 
(PTAT) current source 45 for providing a current I2 proportional to the 
absolute temperature. Accordingly, as the temperature increases, the 
difference in the base-emitter voltages is increased, and vice-versa. 
In other words, at 125.degree. C., for example, the PTAT bias scheme will 
provide a .DELTA.V.sub.BE of 400 mv, and will provide the lower 
corresponding voltages at the lower temperatures as in TABLE 1 so that the 
relatively low error based upon the current steering ratio is maintained 
over the entire desired temperature range. 
A second embodiment of the switched current cell 50 is understood with 
reference to FIG. 3. This embodiment is similar to that described above 
with reference to FIG. 2; however, in the embodiment of FIG. 3 a pair of 
transistors Q5, Q6 are connected in an emitter-follower configuration to 
serve as buffers between the pair of steering transistors Q3, Q4 and the 
pair of current switching transistors Q1, Q2 as would be readily 
appreciated by those skilled in the art. The current cell 50 also includes 
the illustrated additional bias resistor R3 connected between the two 
biasing resistors R1, R2 and ground GND. In addition, each of the buffer 
transistors Q5, Q6 is connected in series with a respective constant 
current source 51, 52 to provide the constant currents I3, I4. The choice 
on whether to use the illustrated buffer transistors Q5, Q6 may depend, at 
least in part, on the desired settling time of the DAC. The PTAT 
compensation circuit of this embodiment also provides an additional 
benefit in that the collector-emitter voltage of the current switching 
transistors Q1, Q2 is maintained at a higher level at higher temperatures 
than would otherwise be provided if I2 were constant, for example. 
Operation of the second embodiment of the current cell 50 is similar to 
that of the first embodiment and needs no further description herein. 
The PTAT current source 45 may be provided by any number of well-known 
circuits as would be readily understood by those skilled in the art. FIG. 
4 illustrates a PTAT current source 45 which may be used in the current 
cells in accordance with the present invention. The illustrated PTAT 
current source 45 is based upon the PTAT source disclosed in "Design of 
Analog Integrated Circuits" by Gray et al., pp. 282-283, published by John 
Wiley & Sons (1984). 
In particular, the collector currents I.sub.C9 and I.sub.C10 may be 
constrained to be equal by the current source formed by transistors Q7, 
Q8. Transistor Q11 provides a current mirror to generate the PTAT current 
output I2 (FIGS. 2 and 3) as would be readily understood by those skilled 
in the art. In addition, the bias resistors R1-R3 are desirably made from 
the same material as R4 so that any temperature coefficient effects of the 
resistors are substantially cancelled out as would also be readily 
understood by those skilled in the art. 
A method aspect of the present invention is for steering current in a 
current cell 40, 50 comprising a pair of current switching transistors Q1, 
Q2 connected together in a current steering configuration so that one 
transistor is off while the other transistor is on, and with the pair of 
current switching transistors having a proportion of current steering 
based upon a difference in transistor control voltage and also based upon 
a thermally dependent voltage. The method preferably comprises the steps 
of: supplying a current to the pair of current switching transistors Q1, 
Q2 for steering; and controlling the difference in transistor control 
voltages of the current switching transistors based upon a temperature 
dependent bias voltage to compensate for the thermally dependent voltage. 
The difference in control voltages may be provided using a pair of 
steering transistors Q3, Q4 and associated bias resistors R1, R2 supplied 
current from a PTAT current source 45 as described above. 
Those of skill in the art will readily appreciate that the DAC embodiments 
of the present invention may find uses in many applications including 
cellular base stations, wireless communications, direct digital frequency 
synthesis, signal reconstruction, test equipment, high resolution imaging 
systems and arbitrary waveform generators, for example. Those of skill in 
the art will also recognize that a current cell 40, 50 as described herein 
can be readily implemented using PNP bipolar transistors, for example, 
rather than the illustrated NPN transistors. The switching current cells 
may also be used in electronic circuits other than the illustrated DAC. 
Moreover, the concept of a temperature responsive bias to correct for the 
temperature dependence of current switching transistors may also be 
applied to metal oxide semiconductor (MOS) transistors, although the 
temperature relationship is somewhat more complicated than for the bipolar 
transistors as would be readily understood by those skilled in the art. 
Bipolar transistors may also offer an advantage for certain current 
steering applications because of the relatively large transconductance of 
bipolar transistors as compared, for example, with similar MOS devices. 
Many modifications and other embodiments of the invention will come to the 
mind of one skilled in the art having the benefit of the teachings 
presented in the foregoing descriptions and the associated drawings. 
Therefore, it is to be understood that the invention is not to be limited 
to the specific embodiments disclosed, and that modifications and 
embodiments are intended to be included within the scope of the appended 
claims.