Display device

A display device includes a substrate including a pixel area and a transmission area, and a pixel circuit disposed in the pixel area. The pixel circuit includes a first thin-film transistor included in a first multi-layer film, and a second thin-film transistor included in a second multi-layer film on the first multi-layer film. The first thin-film transistor and the second thin-film transistor are electrically connected to each other. The display device also includes a display element disposed on the second multi-layer film and including a pixel electrode electrically connected to the second thin-film transistor via a contact hole defined in the second multi-layer film, an opposite electrode facing the pixel electrode, and an intermediate layer between the pixel electrode and the opposite electrode.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and benefits of Korean Patent Application No. 10-2019-0135587 under 35 U.S.C. § 119, filed in the Korean Intellectual Property Office on Oct. 29, 2019, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

One or more embodiments relate to a transparent display device, the device performance of which may be maintained and simultaneously high transmittance of which may be achieved.

2. Description of the Related Art

The use of display devices has become diverse in a variety of fields. Since the thicknesses and weights of the display devices have decreased, the range of the usage thereof has widened.

For example, these display devices may be used in various ways, such as a display of a small product such as a mobile phone, a display of a large product such as a television (TV), a head up display (HUD) of a vehicle, or an electronic device for artificial intelligence (AI). Transparent display devices having a light-transmitting property may be desirable according to the application.

However, in conventional display devices, there have been hurdles in their development such that it is difficult to increase transmittance of a display device since an area needs be secured for a light-emitting device, and that in order to increase the transmittance, the performance of the light-emitting device may be degraded.

Therefore, it is desired that the performance of a display device may be maintained while transmittance of the display device increases.

SUMMARY

According to embodiments, a display device may include a substrate including a pixel area and a transmission area, and a pixel circuit disposed in the pixel area and including a first thin-film transistor included in a first multi-layer film, and a second thin-film transistor included in a second multi-layer film on the first multi-layer film. The first thin-film transistor and the second thin-film transistor may be electrically connected to each other. The display device may include a display element disposed on the second multi-layer film and including a pixel electrode electrically connected to the second thin-film transistor via a contact hole defined in the second multi-layer film, an opposite electrode facing the pixel electrode, and an intermediate layer between the pixel electrode and the opposite electrode.

The first multi-layer film and the second multi-layer film may extend into the transmission area, the first multi-layer film may include a first transmission opening in the transmission area, and the second multi-layer film may include a second transmission opening in the transmission area.

The display device may further include a light-transmitting filling layer disposed in the first transmission opening and the second transmission opening.

The first thin-film transistor may include a first semiconductor layer, a first gate electrode that overlaps the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer. The first multi-layer film may further include an insulating layer disposed on the first conductive layer to cover the first conductive layer.

The first thin-film transistor and the second thin-film transistor may be electrically connected to each other via a contact hole defined in the insulating layer.

The pixel circuit may further include a storage capacitor including an upper electrode and a lower electrode that overlap each other, and the lower electrode and the first gate electrode may include a same material.

The upper electrode may be between the first gate electrode and the first conductive layer.

The lower electrode may overlap the first semiconductor layer.

The second thin-film transistor may include a second semiconductor layer disposed on the first conductive layer, a second gate electrode that overlaps the second semiconductor layer, and a second conductive layer electrically connected to the second semiconductor layer.

The first semiconductor layer may include polycrystalline silicon, and the second semiconductor layer may include an oxide semiconductor material.

The first gate electrode and the second gate electrode may include a same material.

At least part of the first conductive layer and at least part of the second conductive layer may overlap each other.

The first conductive layer and the second conductive layer may include the same material.

The pixel circuit may further include a scan line that extends in a first direction, and the scan line and the first gate electrode may include a same material.

The pixel circuit may further include a data line that extends in a second direction crossing the first direction, and the data line and the first conductive layer may include a same material.

The first thin-film transistor may include a driving thin-film transistor.

The second thin-film transistor may include an emission control thin-film transistor.

The first multi-layer film may further include a third thin-film transistor, and the third thin-film transistor may include at least one of a switching thin-film transistor, a compensation thin-film transistor, and an operation control thin-film transistor.

The second multi-layer film may further include a fourth thin-film transistor, and the fourth thin-film transistor may include an initialization thin-film transistor.

The first multi-layer film may include a scan line and an emission control line that extend in the first direction, and the second multi-layer film may include a previous scan line and an initialization voltage line that extend in the first direction, and the scan line, the emission control line, and the previous line, and the initialization voltage line may bypass the transmission area.

According to other embodiments, a display device may include a substrate including a pixel area including a pixel circuit and a display element electrically connected to the pixel circuit, and a transmission area, a first active pattern disposed in the pixel area, a first gate pattern disposed on the first active pattern, a first conductive pattern disposed on the first gate pattern, a second active pattern disposed on the first conductive pattern, a second gate pattern disposed on the second active pattern, a second conductive pattern disposed on the second gate pattern, and a pixel electrode disposed on the second conductive pattern. The pixel circuit may include a first thin-film transistor including a first semiconductor layer and a second thin-film transistor including a second semiconductor layer, the first semiconductor layer may be a part of the first active pattern, and the second semiconductor layer may be a part of the second active pattern.

The first active pattern and the second active pattern may be electrically connected to each other via a bridge pattern between the first active pattern and the second active pattern.

The first active pattern and the second active pattern may be electrically connected to each other via a contact hole defined in an insulating layer between the first active pattern and the second active pattern.

The first active pattern may include polycrystalline silicon, and the second active pattern may include an oxide semiconductor material.

The pixel circuit may include a storage capacitor including a lower electrode and an upper electrode, the first gate pattern may be used as the lower electrode, and at least part of a third conductive pattern between the first gate pattern and the first conductive pattern may be used as the upper electrode.

The pixel circuit may further include a scan line and a first emission control line that are disposed on the same layer as the first gate pattern and extend in a first direction, and a previous scan line and a second emission control line that are disposed on the same layer as the second gate pattern and extend in the first direction.

The first gate pattern and the second gate pattern may include a same material.

The first conductive pattern and the second conductive pattern may include a same material.

Other aspects, features, and advantages of certain embodiments of the disclosure than the above-described aspects, features, and advantages will be apparent from a detailed description, the claims, and the drawings for implementing the following invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Hereinafter, embodiments of the disclosure will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and a redundant description therewith may be omitted.

It will be further understood that terms such as “comprise”, “comprising”, “has”, “have”, “having”, “include”, and “including” as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

It will be understood that when a layer, region, or component is referred to as being “formed on” or the like with respect to another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. For example, intervening layers, regions, or components may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, since sizes and thicknesses of components in the drawings may be arbitrarily illustrated for convenience of explanation, embodiments are not limited thereto.

“A and/or B” represents A, B, or A and B. “At least one of A and B” represents A, B, or A and B.

It will be understood that when a layer, region, or component is referred to as being “connected to” or the like with respect to another layer, region, or component, it may be directly or indirectly connected to the other layer, region, or component. For example, intervening layers, regions, or components may be present.

The x-axis, the y-axis and the z-axis may not be limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that may not be perpendicular to one another.

The term “overlap” may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

Hereinafter, an organic light-emitting display device will be described as an example of a display device1according to an embodiment. However, the display device according to the disclosure is not limited thereto. In another embodiment, the display device1according to the disclosure may be a display device, such as an inorganic light-emitting display device or an inorganic electroluminescence (EL) display device, or a quantum dot light-emitting display device. For example, an emission layer of a display element in the display device1may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

FIGS.1A and1Bare perspective views schematically illustrating display devices1and1′ according to embodiments.

Referring toFIG.1A, the display device1may include a display area DA, in which an image may be realized, and a non-display area NDA that may be a peripheral area in which no image may be realized. Pixels may be disposed in the display area DA and may provide an image to the outside due to light emitted from the pixels. The non-display area NDA may be outside the display area DA and may surround the display area DA.

The display area DA may include a pixel area PA and a transmission area TA. Pixel areas PAs and transmission areas TAs in combinations may be in the display area DA. The pixel area PA may be an area in which pixels may be disposed and may be an area in which emission may be substantially performed. Although not shown, the pixels in the pixel area PA may be of a variety of types, such as stripe types, pentile types, and mosaic types.

The transmission area TA may be an area in which no pixels may be disposed and may be an area through which light passing a substrate100may be transmitted. An organic layer and/or an inorganic layer may be located in the transmission area TA. In another embodiment, the substrate100may be located in the transmission area TA, and all layers on the substrate100may be removed. In another embodiment, the substrate100may be located in the transmission area TA, and only an inorganic layer, such as a buffer layer, may be located on the substrate100.

InFIG.1A, transmission areas TAs may be disposed throughout the entire display area DA. A transmission area TA may be an area through which light may be transmitted, as described above. As the transmission area TA and the pixel area PA may be repeatedly disposed in the display area DA, an image may be displayed to a user via the display area DA of the display device1, and simultaneously, the display area DA may be recognized as being approximately transparent. The display device1may be implemented in such a way that the entire surface of the display area DA may be like a transparent display.

In an alternative embodiment, as shown inFIG.1B, in the display device1′, a display area DA may include a first display area DA1and a second display area DA2, and transmission areas TAs may be only in the second display area DA2.

In an embodiment, the second display area DA2may be an area in which a component, such as a sensor using infrared rays, visible rays, or sound, may be located below the second display area DA2. For example, the transmission area TA may be an area through which light or/and sound that may be output from the component to the outside or proceeds toward the component from the outside may be transmitted. In case that light (e.g., infrared rays) transmits through the second display area DA2, light transmittance may be about 10% or more, more particularly, about 20% or more, about 25% or more, about 50% or more, about 85% or more, or about 90% or more.

The number of pixels disposed in the second display area DA2per unit area may be less than the number of pixels disposed in the display area DA.

InFIG.1B, the second display area DA2may be at a side (e.g., at an upper side) of the display area DA having a rectangular shape. However, embodiments are not limited thereto. In an embodiment, the second display area DA2may be within the display area DA and may have a circular or polygonal shape. The position of the second display area DA2and the number of second display areas DA2may be variously changed.

Also, the shape of the display area DA shown inFIGS.1A and1Bmay not be limited to the rectangular shape and may be a circular shape, an oval shape, or a polygonal shape, such as a triangular or pentagonal shape or the like. In case that the shape of the display area DA may be a circular shape, the substrate100may have an approximately circular shape according to the shape of the display area DA.

Hereinafter, an organic light-emitting display device will be described as an example of the display device1according to an embodiment. However, the display device according to the disclosure is not limited thereto. In another embodiment, the display device1according to the disclosure may be a display device, such as an inorganic light-emitting display device or an inorganic EL display device, or a quantum dot light-emitting display device. For example, an emission layer of a display element in the display device1may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

FIG.2is a plan view schematically illustrating a display device according to an embodiment.

Referring toFIG.2, a variety of components that may constitute the display device1may be located on the substrate100. The substrate100may include a glass material, a metal material, a plastic material, or a combination thereof. In case that the substrate100includes a plastic material, the substrate100may include a polymer resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate cellulose acetate propionate, or a combination thereof, for example. The substrate100including a plastic material may be flexible, rollable, or bendable.

The substrate100may include a display area DA and a non-display area NDA that surrounds the display area DA. The display area DA may be an area in which an image may be displayed on the whole. The display area DA may include a pixel area PA, in which pixels P may be disposed, and a transmission area TA, in which no pixels P may be disposed and which may have a light-transmitting property.

Pixels P may be disposed in the pixel area PA of the display area DA. Each of the pixels P may include a display element, such as an organic light-emitting diode OLED. Each of the pixels P may emit red, green, blue, or white light, for example, from the organic light-emitting diode OLED. Hereinafter, the pixels P in the specification may be (sub-)pixels that emit light having red, green, blue, and white colors, as described above.

The display area DA may be covered by an encapsulation member300and protected from external air or moisture. The encapsulation member300may be an encapsulation substrate including a glass material and may have a thin-film encapsulation layer including at least one organic layer and at least one inorganic layer that may be alternately stacked. Although not shown, in case that the encapsulation member300may be an encapsulation substrate, a sealing material for bonding the substrate100to the encapsulation member300may be deposited in the non-display area NDA.

The pixels P may be electrically connected to external circuits in the non-display area NDA. A first scan driving circuit150, a second scan driving circuit152, a first power supply line160, a second power supply line170, a pad part180, and a data driving circuit190may be disposed in the non-display area NDA.

The first scan driving circuit150may provide a scan signal to each pixel P through a scan line SL. The first scan driving circuit150may provide an emission control signal to each pixel through an emission control line EL. The second scan driving circuit152may be located in parallel to the first scan driving circuit150with the display area DA therebetween. Some of the pixels P disposed in the display area DA may be electrically connected to the first scan driving circuit150, and the remaining pixels P may be electrically connected to the second scan driving circuit152. In another embodiment, the second scan driving circuit152may be omitted.

The first power supply line160may include a first sub-line162and a second sub-line163, which extend in parallel to each other in an x-direction with the display area DA therebetween. The second power supply line170having a loop shape with an open side may surround the display area DA partially.

The pad part180may be located at an edge of the substrate100. The pad part180may not be covered by an insulating layer but may be exposed and thus may be electrically connected to a printed circuit board PCB. A pad part PCB-P of the printed circuit board PCB may be electrically connected to the pad part180of the display device1. The printed circuit board PCB may provide signals or power of a controller (not shown) to the display device1.

Control signals generated in the controller may be respectively transmitted to the first and second scan driving circuits150and152through the printed circuit board PCB. The controller may provide a first power supply voltage ELVDD and a second power supply voltage ELVSS (seeFIG.3) respectively to the first and second power supply lines160and170through first and second connection lines161and171. The first power supply voltage ELVDD may be provided to each of the pixels P via a driving voltage line PL electrically connected to the first power supply line160, and the second power supply voltage ELVSS may be provided to an opposite electrode of each pixel P electrically connected to the second power supply line170.

The data driving circuit190may be electrically connected to the data line DL. A data signal of the data driving circuit190may be provided to each pixel P via a connection line181electrically connected to the pad part180and a data line DL electrically connected to the connection line181.FIG.1Billustrates that the data driving circuit190may be located at the printed circuit board PCB. In another embodiment, the data driving circuit190may be located on the substrate100. For example, the data driving circuit190may be located between the pad part180and the first power supply line160.

FIG.3is a circuit diagram schematically illustrating a pixel of a display panel according to an embodiment.

Referring toFIG.3, each of the pixels P may include a pixel circuit PC and an organic light-emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include thin-film transistors and a storage capacitor. The thin-film transistors and the storage capacitor may be electrically connected to signal lines SL, SL-1, EL1, EL2, and DL, an initialization voltage line VL, and the driving voltage line PL.

FIG.3illustrates that each pixel P may be electrically connected to the signal lines SL, SL-1, EL1, EL2, and DL, the initialization voltage line VL, and the driving voltage line PL. However, embodiments are not limited thereto. In another embodiment, at least one of the signal lines SL, SL-1, EL1, EL2, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared among neighboring pixels.

The thin-film transistors may include a driving thin-film transistor (TFT) T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

The signal lines may include a scan line SL that may deliver a scan signal Sn, a previous scan line SL-1that may deliver a previous scan signal Sn-1to the first initialization TFT T4and the second initialization TFT T7, a first emission control line EL1and a second emission control line EL2that may deliver an emission control signal En to the operation control TFT T5and the emission control TFT T6, and the data line DL that crosses the scan line SL and may deliver a data signal Dm. The driving voltage line PL may deliver a driving voltage such as the first power supply voltage ELVDD to the driving TFT T1, and the initialization voltage line VL may deliver an initialization voltage Vint to the driving TFT T1and a pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode G1of the driving TFT T1may be electrically connected to a first storage capacitive plate Cst1of a storage capacitor Cst, and a driving source electrode S1of the driving TFT T1may be electrically connected to the driving voltage line PL thereunder via the operation control TFT T5, and a driving drain electrode D1of the driving TFT T1may be electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6. The driving TFT T1may provide a data signal Dm according to a switching operation of the switching TFT T2and may supply a driving current IOLEDto the organic light-emitting diode OLED.

A switching gate electrode G2of the switching TFT T2may be electrically connected to the scan line SL, and a switching source electrode S2of the switching TFT T2may be electrically connected to the data line DL, and a switching drain electrode D2of the switching TFT T2may be electrically connected to the driving source electrode S1of the driving TFT T1and to the driving voltage line PL thereunder via the operation control TFT T5. The switching TFT T2may be turned on according to the scan signal Sn delivered via the scan line SL and may perform a switching operation of delivering a data signal Dm transmitted to the data line DL to the driving source electrode S1of the driving TFT T1.

A compensation gate electrode G3of the compensation TFT T3may be electrically connected to the scan line SL, a compensation source electrode S3of the compensation TFT T3may be electrically connected to the driving drain electrode D1of the driving TFT T1and to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6, and a compensation drain electrode D3of the compensation TFT T3may be electrically connected to the first storage capacitive plate Cst1of the storage capacitor Cst, a first initialization drain electrode D4of the first initialization TFT T4, and the driving gate electrode G1of the driving TFT T1. The compensation TFT T3may be turned on according to the scan signal Sn provided via the scan line SL and may electrically connect the driving gate electrode G1to the driving drain electrode D1of the driving TFT T1, thereby diode-connecting the driving TFT T1.

A first initialization gate electrode G4of the first initialization TFT T4may be electrically connected to the previous scan line SL-1, and a first initialization source electrode S4of the first initialization TFT T4may be electrically connected to a second initialization drain electrode D7of the second initialization TFT T7and the initialization voltage line VL, and the first initialization drain electrode D4of the first initialization TFT T4may be electrically connected to the first storage capacitive plate Cst1of the storage capacitor Cst, the compensation drain electrode D3of the compensation TFT T3, and the driving gate electrode G1of the driving TFT T1. The first initialization TFT T4may be turned on according to the previous scan signal Sn-1delivered via the previous scan line SL-1and may perform an initialization operation of delivering the initialization voltage Vint to the driving gate electrode G1of the driving TFT T1and initializing a voltage of the driving gate electrode G1of the driving TFT T1.

An operation control gate electrode G5of the operation control TFT T5may be electrically connected to the first emission control line EL1, and an operation control source electrode S5of the operation control TFT T5may be electrically connected to the driving voltage line PL thereunder, and an operation control drain electrode D5of the operation control TFT T5may be electrically connected to the driving source electrode S1of the driving TFT T1and the switching drain electrode D2of the switching TFT T2.

An emission control gate electrode G6of the emission control TFT T6may be electrically connected to the second emission control line EL2, and an emission control source electrode S6of the emission control TFT T6may be electrically connected to the driving drain electrode D1of the driving TFT T1and the compensation source electrode S3of the compensation TFT T3, and an emission control drain electrode D6of the emission control TFT T6may be electrically connected to the second initialization source electrode S7of the second initialization TFT T7and the pixel electrode of the organic light-emitting diode OLED.

The operation control TFT T5and the emission control TFT T6may be simultaneously turned on according to the emission control signal En delivered via the second emission control line EL2, and thus, the driving voltage such as the first power supply voltage ELVDD may be delivered to the organic light-emitting diode OLED and the driving current IOLEDmay flow through the organic light-emitting diode OLED.

A second initialization gate electrode G7of the second initialization TFT T7may be electrically connected to the previous scan line SL-1, a second initialization source electrode S7of the second initialization TFT T7may be electrically connected to the emission control drain electrode D6of the emission control TFT T6and the pixel electrode of the organic light-emitting diode OLED, and a second initialization drain electrode D7of the second initialization TFT T7may be electrically connected to the first initialization source electrode S4of the first initialization TFT T4and the initialization voltage line VL. The second initialization TFT T7may be turned on according to the previous scan signal Sn-1provided via the previous scan line SL-1and may initialize the pixel electrode of the organic light-emitting diode OLED.

FIG.3illustrates that the initialization TFT T4and the second initialization TFT T7may be electrically connected to the previous scan line SL-1. However, embodiments are not limited thereto. In another embodiment, the initialization TFT T4may be electrically connected to the previous scan line SL-1and driven according to the previous scan signal Sn-1, and the second initialization TFT T7may be electrically connected to an additional signal line (for example, a subsequent scan line) and driven according to a signal delivered to the signal line.

A second storage capacitive plate Cst2of the storage capacitor Cst may be electrically connected to the driving voltage line PL, and an opposite electrode of the organic light-emitting diode OLED may be electrically connected to a common voltage such as the second power supply voltage ELVSS. Thus, the organic light-emitting diode OLED may receive the driving current IOLEDfrom the driving TFT T1to emit light, thereby displaying an image.

FIG.3illustrates that the compensation TFT T3and the initialization TFT T4may have a dual gate electrode. However, the compensation TFT T3and the initialization TFT T4may have one gate electrode.

FIG.4is a plan view schematically illustrating part of a display device according to an embodiment.

Referring toFIG.4, the pixel area PA and the transmission area TA may be adjacent to each other. Organic light-emitting diodes OLEDs may be disposed in the pixel area PA. In other words, the pixel area PA may include pixel circuit areas PCAs, and each of the organic light-emitting diodes OLED may correspond to each of the pixel circuit areas PCAs. The pixel circuit (see PC ofFIG.3) including TFTs and the storage capacitor may be located in the pixel circuit areas PCAs, and the pixel circuit PC may be electrically connected to the organic light-emitting diodes OLEDs and thus may drive the pixel (see P ofFIG.3).

FIG.4illustrates that the organic light-emitting diodes OLEDs may be located approximately in the center of the pixel circuit areas PCAs. However, embodiments are not limited thereto. In another embodiment, there may be various modifications in which the organic light-emitting diodes OLEDs may be disposed on a side of the pixel circuit areas PCAs or overall in the pixel circuit areas PCAs.

The transmission area TA that may be an area through which external light may be transmitted, may be an area in which no pixel circuit PC and no organic light-emitting diode OLED may be located. No pixel circuit PC means that conductive layers of the pixel circuit PC may not be located in the transmission area TA. In an embodiment, lines that extend in a first direction (x-direction) and/or a second direction (y-direction) may bypass the transmission area TA.

The pixel area PA and the transmission area TA may be in combination. The area of the transmission area TA on a plane may be greater than the area of the pixel area PA. In an embodiment, the transmission area TA may be about 50% or more of the display area DA. Alternatively, the transmission area TA may be about 75% or more of the display area DA. According to an embodiment, a display device in which the transmission area TA may be increased to achieve high transmittance, may be implemented.

FIGS.5A through5Dare cross-sectional views schematically illustrating portions of display devices according to embodiments.FIGS.5A and5Bmay correspond to a cross-section taken along line A-A′ ofFIG.1A or1B.

Referring toFIG.5A, a first multi-layer film ML1on the substrate100and a second multi-layer film ML2on the first multi-layer film ML1may be provided in the pixel area PA. A pixel-defining layer PDL and an organic light-emitting diode OLED may be located on the second multi-layer film ML2.

The first multi-layer film ML1and the second multi-layer film ML2may have a structure in which insulating layers and conductive layers may be alternately stacked. The pixel circuit PC may be implemented through the insulating layers that may be between patterned conductive layers to insulate them.

A first thin-film transistor TFT1may be included in the first multi-layer film ML1, and a second thin-film transistor TFT2may be included in the second multi-layer film ML2. “A thin-film transistor included in a multi-layer film” may mean that part of multiple conductive layers included in the multi-layer film constitute a semiconductor layer, a gate electrode, and a source/drain electrode of the thin-film transistor.

As shown inFIG.5A, at least one first thin-film transistor TFT1may be provided in the first multi-layer film ML1. Also, at least one second thin-film transistor TFT2may be provided in the second multi-layer film ML2.

The pixel circuit PC according to an embodiment includes thin-film transistors. In case that the pixel circuit PC includes seven thin-film transistors and a storage capacitor, as shown inFIG.3, a certain area may be required so that seven thin-film transistors may be disposed on the substrate100. In particular, in a transparent display device according to an embodiment, the ratio of the transmission area TA may be increased as the area of the pixel circuit PC may be gradually reduced. Thus, a display device having high transmittance may be implemented.

Thus, in a display device according to an embodiment, thin-film transistors may be disposed in multiple levels (e.g., duplex) so that the area of a pixel circuit including the same number of thin-film transistors may be relatively reduced on the plane. Thus, the same performance of the pixel circuit may be maintained and simultaneously, the area of the pixel circuit PC of each pixel P may be reduced so that a display device having high transmittance may be implemented.

The first multi-layer film ML1and the second multi-layer film ML2may extend to the transmission area TA. Referring toFIG.5A, no thin-film transistors may be located on the portion of the first multi-layer film ML1and the portion of the second multi-layer film ML2that extend to the transmission area TA. Although not shown, the first multi-layer film ML1and the second multi-layer film ML2in the transmission area TA may include only insulating layers of an inorganic layer and/or an organic layer excluding the conductive layers.

In an embodiment, the pixel-defining layer PDL may have a third transmission opening OP3that corresponds to the transmission area TA. For example, part of the pixel-defining layer PDL that corresponds to the transmission area TA may be removed.

In another embodiment, an opposite electrode230may have a fourth transmission opening OP4that corresponds to the transmission area TA, as shown inFIG.5B. For example, part of the opposite electrode230that corresponds to the transmission area TA may be removed. In particular, the opposite electrode230may be formed of metal and thus the transmittance thereof may be considerably lower than the insulating layers. Thus, in order to improve transmittance per unit area of the transmission area TA, part of the opposite electrode230that corresponds to the transmission area TA may be removed.

In another embodiment shown inFIG.5C, the first multi-layer film ML1and the second multi-layer film ML2that extend into the transmission area TA may have a first transmission opening OP1and a second transmission opening OP2, each corresponding to the transmission area TA. In this way, layers in the transmission area TA may be removed so that transmittance per unit area of the transmission area TA may be improved.

FIG.5Cillustrates that a top surface of the substrate100may be exposed to the outside through the first transmission opening OP1. However, in some embodiments, a buffer layer may remain on the substrate100corresponding to the transmission area TA.

A light-transmitting filling layer400may be disposed or filled in the first transmission opening OP1and the second transmission opening OP2, as shown inFIG.5D. The light-transmitting filling layer400may include silicon oxynitride (SiON) having an excellent light-transmitting property, for example. A top surface of the light-transmitting filling layer400may be located on a virtual surface between a top surface of the substrate100and a top surface of the pixel-defining layer PDL.

Hereinafter, a detailed structure of the pixel shown inFIG.3will be described with reference toFIGS.6through17.

FIG.6is a plan view schematically illustrating part of the thin-film transistors included in the pixel circuit ofFIG.3and the position of a storage capacitor.FIGS.7through10are plan views schematically illustrating the layers ofFIG.6.

FIG.11is a plan view schematically illustrating a remaining part of the thin-film transistors included in the pixel circuit ofFIG.3and the position of a pixel electrode.FIGS.12through15are plan views schematically illustrating the layers ofFIG.11.

FIGS.16and17are cross-sectional views schematically illustrating part of a pixel stack structure according to an embodiment.

FIG.6corresponds to the first multi-layer film ML1, andFIGS.12through14correspond to the second multi-layer film ML2. That is, structures fromFIGS.12through14may be sequentially stacked on the structure ofFIG.6, and a pixel electrode210may be located on the structure ofFIG.14, as shown inFIG.15.

In an embodiment, the first multi-layer film ML1ofFIG.6may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, and an operation control TFT T5. The second multi-layer film ML2shown inFIGS.12through14may include a first initialization TFT T4, an emission control TFT T6, and a second initialization TFT T7. The thin-film transistors on the first multi-layer film ML1and the thin-film transistors on the second multi-layer film ML2may be electrically connected to one another, and a circuit as schematically shown inFIG.3may be constituted.

Each ofFIGS.7through10illustrates the arrangement of lines, electrodes, and semiconductor layers on a same layer. Each ofFIGS.12through15illustrates the arrangement of lines, electrodes, and semiconductor layers on a same layer. The layer corresponding toFIGS.7through10may be different from the layer corresponding toFIGS.12through15.

An insulating layer may be between the layers shown inFIGS.7through10andFIGS.12through15. For example, a buffer layer111may be between the substrate100and the layer ofFIG.7. A first gate insulating layer (see112ofFIG.16) may be between the layer ofFIG.7and the layer ofFIG.8. A first interlayer insulating layer (see113ofFIG.16) may be between the layer ofFIG.8and the layer ofFIG.9. A second interlayer insulating layer (see114ofFIG.16) may be between the layer ofFIG.9and the layer ofFIG.10.

An insulating layer (see115ofFIG.16) may be between the layer ofFIG.10and the layer ofFIG.12. For example, the second multi-layer film ML2may be located on the insulating layer115. In this way, the first multi-layer film ML1according to an embodiment may include the layers shown inFIGS.7through10, the insulating layers, that is, the first gate insulating layer112, the first interlayer insulating layer113, and the second interlayer insulating layer114therebetween and the insulating layer115.

Also, a layer shown inFIG.12may be located on the first multi-layer film ML1. The layer shown inFIG.12may be on (e.g., directly on) the insulating layer115. A second gate insulating layer (see121ofFIG.16) may be between the layer ofFIG.12and a layer ofFIG.13, and a third interlayer insulating layer (see122ofFIG.16) may be between the layer ofFIG.13and a layer ofFIG.14, and a planarization insulating layer (see123ofFIG.16) may be between the layer ofFIG.14and a layer ofFIG.15. In this way, the second multi-layer film ML2according to an embodiment may include the layers ofFIGS.12through14, the insulating layers, that is, the second gate insulating layer121and the third interlayer insulating layer122therebetween and the insulating layer115.

The layers shown inFIGS.7through10andFIGS.12through15may be electrically connected to one another via contact holes defined in at least part of the above-described insulating layers.

Referring toFIGS.6and11, the pixel P may include the scan line SL, the previous scan line SL-1, the first emission control line EL1, the second emission control line EL2, and the initialization voltage line VL, which respectively may apply the scan signal Sn, the previous scan signal Sn-1, the emission control signal En, and the initialization voltage Vint and may extend in a first direction (x-direction). The pixel P may include the data line DL and the driving voltage line PL, which may extend in a second direction (y-direction) to cross the scan line SL-1, the first emission control line EL1, the second emission control line EL2, and the initialization voltage line VL and respectively apply a data signal Dm and the driving voltage such as the first power supply voltage ELVDD. The pixel P includes the thin-film transistors T1through T7, the storage capacitor Cst, and the organic light-emitting diode OLED electrically connected thereto. Hereinafter, for convenience of explanation, description will be provided according to a stack order.

Referring toFIGS.6through10andFIGS.16and17, the driving TFT T1, the switching TFT T2, the compensation TFT T3, and the operation control TFT T5may be disposed along a first active pattern ACT1shown inFIG.7. The first active pattern ACT1may be located on the substrate100, as shown inFIG.16, and the buffer layer111including an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), may be between the first active pattern ACT1and the substrate100.

Partial regions of the first active pattern ACT1may correspond to semiconductor layers of the driving TFT T1, the switching TFT T2, the compensation TFT T3and the operation control TFT T5, respectively. In other words, the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensation TFT T3, and the operation control TFT T5may be electrically connected to one another and may be bent in various shapes.

The first active pattern ACT1may be formed of polycrystalline silicon. Alternatively, the first active pattern ACT1may include amorphous silicon or an oxide semiconductor layer, such as a G-I-Z-O layer [(In2O3)a(Ga2O3)b(ZnO)c layer](where a, b, and c may be real numbers satisfying the condition of a≥0, b≥0, and c>0). Hereinafter, in an embodiment, the case where the first active pattern ACT1may be formed of polycrystalline silicon will be described.

Hereinafter, each of the first active pattern ACT1and a second active pattern ACT2ofFIGS.7and12may include a channel area and source and drain areas in both sides of the channel area. The source area and the drain area may be understood as a source electrode and a drain electrode of the thin-film transistor. Hereinafter, for convenience, the source area and the drain area may be referred to as the source electrode and the drain electrode, respectively.

The driving TFT T1may include a driving gate electrode G1that overlaps a driving channel area and a driving source electrode S1and a driving drain electrode D1at both sides of the driving channel area. The driving channel area that overlaps the driving gate electrode G1may have a bent shape, like the letter “S” or an omega shape and thus may constitute a large channel length within a narrow space. In case that the length of the driving channel area may be large, a driving range of a gate voltage may be widened so that a gray scale of light emitted from the organic light-emitting diode OLED may be more precisely controlled and display quality may be improved.

The switching TFT T2may include a switching gate electrode G2that overlaps a switching channel area and a switching source electrode S2and a switching drain electrode D2at both sides of the switching channel area. The switching drain electrode D2may be electrically connected to the driving source electrode S1.

The compensation TFT T3that may be a dual TFT may include compensation gate electrodes G3that overlap two compensation channel areas and a compensation source electrode S3and a compensation drain electrode D3, which may be located at both sides of the two compensation channel areas. The compensation TFT T3may be electrically connected to the driving gate electrode G1of the driving TFT T1via a node connection line NL that will be described later.

The operation control TFT T5may include an operation control gate electrode G5that overlaps an operation control channel area and an operation control source electrode S5and an operation control drain electrode D5, which may be located at both sides of the operation control channel area. The operation control drain electrode D5may be electrically connected to the driving source electrode S1.

The thin-film transistors described above may be electrically connected to the signal lines SL, EL1, and DL, the initialization voltage line VL, and the driving voltage line PL.

The first gate insulating layer112may be located on the first active pattern ACT1described above, and the scan line SL, the first emission control line EL1, and the driving gate electrode G1may be located on the first gate insulating layer112, as shown inFIG.8. The first gate insulating layer112may include an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a combination thereof. The scan line SL, the first emission control line EL1, and the driving gate electrode G1may include metal, such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and an alloy thereof.

The scan line SL may extend in the x-direction. Certain areas of the scan line SL may correspond to the switching and compensation gate electrodes G2and G3. For example, areas of the scan line SL that overlap the channel areas of the switching and compensation TFTs T2and T3may be switching and compensation gate electrodes G2and G3, respectively.

The first emission control line EL1extends in the x-direction. Certain areas of the first emission control line EL1may correspond to the operation control gate electrode G5. For example, an area of the first emission control line EL1that overlaps the channel areas of the operation control driving TFT T5may be the operation control gate electrode G5.

The driving gate electrode G1that may be a floating electrode may be electrically connected to the compensation TFT T3via a node connection line (see NL ofFIG.10).

An electrode voltage line HL may be located on the scan line SL, the first emission control line EL1, and the driving gate electrode G1described above, with the first interlayer insulating layer113including an inorganic material and being therebetween, as shown inFIG.9.

The electrode voltage line HL may extend in the x-direction to cross the data line DL and the driving voltage line PL, as shown inFIG.9. Part of the electrode voltage line HL may cover at least part of the driving gate electrode G1and may constitute the storage capacitor Cst together with the driving gate electrode G1. In an embodiment, the driving gate electrode G1may be the first storage capacitive plate Cst1(i.e., a lower electrode) of the storage capacitor Cst, and part of the electrode voltage line HL may be the second storage capacitive plate Cst2(i.e., an upper electrode) of the storage capacitor Cst. In other words, the electrode voltage line HL and the second storage capacitive plate Cst2may be integrally provided.

The electrode voltage line HL and the second storage capacitive plate Cst2may be electrically connected to the driving voltage line PL. In this regard,FIG.6illustrates that the electrode voltage line HL may be electrically connected to the driving voltage line PL on the electrode voltage line HL via a second contact hole (see CH2ofFIG.10). The electrode voltage line HL and the driving voltage line PL may have a same voltage level (a constant voltage, for example, +5 V). The electrode voltage line HL may be understood as a type of transverse driving voltage line.

Because the driving voltage line PL extends in the y-direction, and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x-direction crossing the y-direction, the driving voltage lines PL and the electrode voltage lines HL in the display area DA may constitute a mesh structure.

First conductive layers, such as the data line DL, the driving voltage line PL, a bridge connection line BL, and the node connection line NL may be located on the second storage capacitive plate Cst2and the electrode voltage line HL with the second interlayer insulating layer114including an inorganic material, therebetween, as shown inFIG.10. The data line DL, the driving voltage line PL, the bridge connection line BL, and the node connection line NL may include Al, Cu, Ti, or a combination thereof, for example. The data line DL, the driving voltage line PL, the bridge connection line BL, and the node connection line NL may have a multi-layer or single layer structure. In an embodiment, the driving voltage line PL and the data line DL may have a multi-layer structure of Ti/Al/Ti.

The data line DL may extend in the y-direction and may be electrically connected to the switching source electrode S2of the switching TFT T2via a first contact hole CH1. Part of the data line DL may be understood as a switching source electrode (i.e., an electrode layer).

The driving voltage line PL may extend in the y-direction and may be electrically connected to the electrode voltage line HL via a second contact hole CH2. Also, the driving voltage line PL may be electrically connected to the operation control TFT T5via a third contact hole CH3. The driving voltage line PL may be electrically connected to the operation control drain electrode D5via the third contact hole CH3.

An end of the bridge connection line BL may be electrically connected to the first active pattern ACT1via a fourth contact hole CH4, and another end of the bridge connection line BL may be electrically connected to the second active pattern ACT2via a seventh contact hole CH7that will be described later. For example, the first active pattern ACT1and the second active pattern ACT2in different layers may be electrically connected to each other via the bridge connection line BL. For example, an end of the bridge connection line BL may be electrically connected to the compensation drain electrode D3, and another end of the bridge connection line BL may be electrically connected to the first initialization drain electrode D4.

An end of the node connection line NL may be electrically connected to the compensation drain electrode D3via a fifth contact hole CH5, and another end of the node connection line NL may be electrically connected to the driving gate electrode G1via a sixth contact hole CH6.

The insulating layer115may be located on the data line DL, the driving voltage line PL, the bridge connection line BL, and the node connection line NL. The insulating layer115may include an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a combination thereof, and/or an organic insulating material, such as acryl, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), or a combination thereof.

The layers shown inFIG.11may be located on the insulating layer115.FIG.11illustrates that the second multi-layer film ML2including the layers ofFIGS.12through14and the pixel electrode shown inFIG.15may be sequentially stacked.

Referring toFIGS.11through17together, the first initialization TFT T4, the emission control TFT T6, and the second initialization TFT T7may be located along the second active pattern ACT2shown inFIG.12. The second active pattern ACT2may be located on the insulating layer115, i.e., the first multi-layer film ML1, as shown inFIG.16.

Partial areas of the second active pattern ACT2correspond to the semiconductor layers of the first initialization TFT T4, the emission control TFT T6, and the second initialization TFT T7, respectively. In other words, the semiconductor layers of the first initialization TFT T4, the emission control TFT T6, and the second initialization TFT T7may be connected to one another and may be bent in various shapes.

As described above, the first active pattern ACT1and the second active pattern ACT2may be electrically connected to each other via the bridge connection line BL.

The second active pattern ACT2may be formed of polycrystalline silicon. Alternatively, the second active pattern ACT2may include amorphous silicon or an oxide semiconductor layer, such as a G-I-Z-O layer [(In2O3)a(Ga2O3)b(ZnO)c layer](where a, b, and c may be real numbers satisfying the condition of a≥0, b≥0, and c>0).

The first initialization TFT T4that may be a dual TFT may include the first initialization gate electrode G4that overlaps two first initialization channel areas and a first initialization source electrode S4and a first initialization drain electrode D4, which may be located at both sides of the two first initialization channel areas.

The emission control TFT T6may include an emission control gate electrode G6that overlaps an emission control channel area and an emission control source electrode S6and an emission control drain electrode D6, which may be located at both sides of the emission control channel area. The emission control source electrode S6may be electrically connected to the driving drain electrode D1.

The second initialization TFT T7may include a second initialization gate electrode G7that overlaps a second initialization channel area and a second initialization source electrode S7and a second initialization drain electrode D7, which may be located at both sides of the second initialization channel area.

In an embodiment, the second active pattern ACT2may be electrically connected to the first active pattern ACT1located under the second active pattern ACT2. In an embodiment, the second active pattern ACT2may be in contact with an end of the bridge connection line BL located under the second active pattern ACT2via the seventh contact hole CH7, and the other end of the bridge connection line BL may be in contact with the first active pattern ACT1located under the second active pattern ACT2via the fourth contact hole CH4. Also, the second active pattern ACT2may be in contact with the first active pattern ACT1located under the second active pattern ACT2via an eighth contact hole CH8. For example, the emission control source electrode S6and the compensation source electrode S3may be electrically connected to each other via the eighth contact hole CH8.

The thin-film transistors described above may be electrically connected to the signal lines SL-1and EL2and the initialization voltage line VL.

The second gate insulating layer121may be located on the second active pattern ACT2described above, and the previous scan line SL-1and the second emission control line EL2may be located on the second gate insulating layer121, as shown inFIG.13. The second gate insulating layer121may include an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a combination thereof. The previous scan line SL-1and the second emission control line EL2may include metal, such as Mo, Al, Cu, Ti, and an alloy thereof.

The previous scan line SL-1and the second emission control line EL2may include metal, such as Mo, Al, Cu, Ti, and an alloy thereof. In an embodiment, the previous scan line SL-1, the second emission control line EL2, the scan line SL, the first emission control line EL1, and the driving gate electrode G1may include the same materials. Materials of the scan line SL, the first emission control line EL1, and the driving gate electrode G1may be described above.

The previous scan line SL-1may extend in the x-direction, and partial areas of the previous scan line SL-1may correspond to the first and second initialization gate electrodes G4and G7. For example, areas of the previous scan line SL-1that overlap the channel areas of the first and second initialization driving TFTs T4and T7may be the first and second initialization gate electrodes G4and G7, respectively.

The second emission control line EL2may extend in the x-direction. Certain areas of the second emission control line EL2may correspond to the emission control gate electrode G6. For example, an area of the second emission control line EL2that overlaps the channel areas of the emission control driving TFT T6may be the emission control gate electrode G6.

The second conductive layers, i.e., the initialization voltage line VL and the contact metal CM may be located on the previous scan line SL-1and the second emission control line EL2described above, with the third interlayer insulating layer122between the second conductive layers, the third interlayer insulating layer122including an inorganic material, as shown inFIG.14.

The initialization voltage line VL extends in the x-direction. The initialization voltage line VL may be electrically connected to the first and second initialization TFTs T4and T7via a ninth contact hole CH9. In an embodiment, the initialization voltage line VL may be electrically connected to the first initialization source electrode S4and the second initialization drain electrode D7via the ninth contact hole CH9.

As shown inFIG.16, the contact metal CM may connect the emission control TFT T6to the pixel electrode210. The contact metal CM may include metal, such as Mo, Al, Cu, Ti, and an alloy thereof. In an embodiment, the contact metal CM may have a triple layer of Ti/Al/Ti. In an embodiment, the contact metal CM, the data line DL, the driving voltage line PL, the bridge connection line BL, and the node connection line NL may include a same material. The data line DL, the driving voltage line PL, the bridge connection line BL, and the node connection line NL may be shown inFIG.10.

The planarization insulating layer123may be located on the initialization voltage line VL and the contact metal CM, and the pixel electrode210may be located on the planarization insulating layer123. The pixel electrode210may be electrically connected to the contact metal CM thereunder via a contact hole CNT formed in the planarization insulating layer123and thus may be electrically connected to the pixel circuit PC.

Referring toFIGS.15through17, the pixel electrode210may be located on the planarization insulating layer123. The pixel electrode210may be electrically connected to the emission control drain electrode D6of the emission control TFT T6via the contact metal CM.

A pixel-defining layer130for exposing the pixel electrode210may be located on the pixel electrode210. The pixel-defining layer130may include one or more organic insulating materials of polyimide, polyamide, acryl resin, BCB, and phenol resin. The pixel-defining layer130covers ends of the pixel electrode210and has an opening for exposing at least part of a top surface of the pixel-defining layer130. An emission area of the pixel P may be defined by the opening of the pixel-defining layer130.

An intermediate layer220may be disposed on the pixel electrode210exposed through the opening of the pixel-defining layer130. The intermediate layer220may include a polymer or small molecular weight organic material that emits light with a certain color. The intermediate layer220may include an emission layer EML. The intermediate layer220shown inFIGS.16and17may refer to an emission layer.

Although not shown, in an embodiment, the intermediate layer220may include a first functional layer under the emission layer and/or a second functional layer on the emission layer.

The first functional layer may have a single layer or multi-layer structure. For example, in case that the first functional layer includes a polymer material, the first functional layer that may be a hole transport layer (HTL) having a single layer structure may include poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). In case that the first functional layer includes a small molecular weight material, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL).

The second functional layer may not necessarily be provided. For example, in case that the first functional layer and the emission layer include a polymer material, the second functional layer may be provided so that the characteristics of an organic light-emitting diode OLED are excellent. The second functional layer may have a single layer or multi-layer structure. The second functional layer may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The opposite electrode230may face the pixel electrode210with the intermediate layer220therebetween. The opposite electrode230may include a conductive material having a small work function. For example, the opposite electrode230may include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposite electrode230may further include a layer such as ITO, IZO, ZnO, In2O3, or a combination thereof, on the (semi-)transparent layer including the materials described above.

FIG.16illustrates a driving semiconductor layer A1of the driving TFT T1and a compensation semiconductor layer A3of the compensation TFT T3that may correspond to part of the first active pattern ACT1ofFIG.7and an emission control semiconductor layer A6of the emission control TFT T6that may correspond to part of the second active pattern ACT2ofFIG.12.

Referring toFIGS.16and17, the pixel circuit PC according to an embodiment may include the first multi-layer film ML1and the second multi-layer film ML2on the substrate100, and each of the first multi-layer film ML1and the second multi-layer film ML2may include thin-film transistors. Thus, the thin-film transistors included in the first multi-layer film ML1and the thin-film transistors included in the second multi-layer film ML2may have a structure in which they may be vertically stacked.

For example, as shown inFIGS.16and17, the driving TFT T1and the compensation TFT T3on a lower layer may be provided in case that the first initialization TFT T4and the emission control TFT T6on an upper layer may be vertically stacked.

The thin-film transistors according to an embodiment ultimately have a structure of the pixel circuit PC shown inFIG.3. Thus, compared to the case where the structure of the same pixel circuit PC may be located on the same plane, as the thin-film transistors of an embodiment may be vertically stacked, the area of the pixel circuit PC per one pixel P may be reduced. In case that the pixel circuit PC according to an embodiment may be applied to a transparent display device, the area of the pixel circuit PC may be reduced so that the area of the transmission area TA may be relatively increased. In another embodiment, a display having high resolution may be implemented through the pixel circuit PC according to an embodiment.

Until now, display devices have been described. However, embodiments are not limited thereto. For example, a method of manufacturing the display device as described above may also belong to the scope of the disclosure.

In an embodiment of the disclosure described above, a display device, the device performance of which may be maintained and simultaneously high transmittance of which may be achieved, may be implemented. Of course, the scope of the disclosure is not limited by these effects.