Systems and methods for resistance compensation in a temperature measurement circuit

Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals are then used to calculate a temperature of the transistor.

BACKGROUND OF THE INVENTION

The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor.

Temperature measurement using a transistor as a sensor is a common application in the semiconductor area. Such a temperature measurement is done by applying two different currents to the transistor each resulting in a respective base-emitter voltage. The difference between the two different base-emitter voltages is proportional to the absolute temperature of transistor144. The following equation defines the relationship between the difference between base-emitter voltage measurements and absolute temperature:
ΔVbe=Vbe2−Vbe1=n*kT/q*1n(I2/I1).
The ‘n’ term is known as the non-ideality factor or emission coefficient is assumed to be a constant (n=1.008) for diodes and transistors.

An example of such a temperature measurement circuit100is shown inFIG. 1a.Turning toFIG. 1a,temperature measurement circuit100includes a transistor120that is used as a temperature sensor. The collector and the base of transistor120are electrically coupled to a variable current source110. Further, the base of transistor120is electrically coupled to one input of an analog to digital converter130, and the emitter of transistor120is electrically coupled to another input of analog to digital converter130. Analog to digital converter130is operable to receive the voltages at the base and emitter of transistor120, and to provide a ΔVbeoutput135representing the difference between two different base to emitter voltages. ΔVbeoutput135is provided to a temperature calculation circuit140that provides an uncorrected temperature output145.

In some cases, an input filter134including a series resistor131, a series resistor132, a and a capacitor133is used. Input filter134is operable to filter noise from the voltages received from the base and emitter of transistor120. While input filter134operates to increase the accuracy ΔVbeoutput135and thereby increase the accuracy of uncorrected temperature145, the series resistance introduced by input filter134results in an error in uncorrected temperature145. In particular, the resistance introduced by series resistor131and series resistor132(and in some cases non-idealities of transistor120) causes a voltage drop that is a function of the magnitude of an applied current. This voltage drop is described by the following equation:
ΔVbe=Vbe2−Vbe1=(Ie2−Ie1)*Rs+n*kT/q*ln(Ic2/Ic1).
Ie1is the current passing through the emitter upon application of a first current, and Ic1is the current passing through the collector upon application of the same current. Ie2and Ic2are similarly emitter and collector currents corresponding to the application of a second current. Rsis the series resistance. The voltage drop described by the aforementioned equation will create a temperature measurement error if not taken into account by the circuit.

To correct for the aforementioned temperature error, some circuits have included a backend offset circuit designed to add or subtract a calculated constant from uncorrected temperature145and thereby achieve a corrected temperature.FIG. 1bshows an example of one such temperature calculation circuit101. As shown, temperature calculation circuit101is substantially similar to temperature calculation circuit100, except for the addition of a temperature offset adder circuit150. Temperature offset adder circuit150receives uncorrected temperature145and a programmed temperature offset input147. The two inputs are added together to create a corrected temperature output155. While such an offset approach can effectively correct calculation errors at a given point on an operational curve, the inaccuracy of the calculated temperature still exists as operation moves farther from the aforementioned offset corrected point on the operational curve.

Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for temperature measurement.

BRIEF SUMMARY OF THE INVENTION

The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor.

Various systems and methods for temperature measurement are described herein. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals may then be used to calculate a temperature of the transistor. In some cases of the aforementioned embodiments, the transistor is a diode connected bipolar transistor, and the sequence of output signals are base-emitter voltages of the diode connected bipolar transistor. In such cases, the bipolar transistor may be either an NPN device or a PNP device.

Other embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a transistor, a variable current source and an analog to digital converter. The variable current source is electrically coupled to the transistor. It should be noted that as used herein, the phrase “electrically coupled” implies either direct or indirect coupling. Direct coupling would be accomplished by, for example, a wire extending directly between two coupled devices. Indirect coupling may be accomplished by, for example, coupling via other components such as, for example, capacitors, resistors, transistors, or the like. The variable current source is operable to provide at least a first current, a second current, a third current and a fourth current. The first current produces a first base-emitter voltage on the transistor, the second current produces a second base-emitter voltage on the transistor, the third current produces a third base-emitter voltage on the transistor, and the fourth current produces a fourth base-emitter voltage on the transistor. The analog to digital converter is operable sample and integrate the first base-emitter voltage while applying a first gain, wherein the analog to digital converter is operable sample and integrate the second base-emitter voltage while applying a second gain, wherein the analog to digital converter is operable sample and integrate the third base-emitter voltage while applying a third gain, wherein the analog to digital converter is operable sample and integrate the fourth base-emitter voltage while applying a fourth gain, and wherein the analog to digital converter is operable to provide an integrated output combining the first base-emitter voltage, the second base emitter voltage, the third base emitter voltage and the fourth base emitter voltage.

In some embodiments of the aforementioned embodiments of the present invention, a magnitude of the first current, a magnitude of the second current, a magnitude of the third current, a magnitude of the fourth current, a sign and magnitude of the first gain, a sign an magnitude of the second gain, a sign and magnitude of the third gain, and a sign and magnitude of the fourth gain are selected such that a resistance error is eliminated from the integrated output. In various instances of the aforementioned embodiments, the analog to digital converter includes a differential operational amplifier, a differential comparator, and a result counter. The base of the transistor is electrically coupled to a first input of the differential operational amplifier via a first input circuit and to a second input of the differential operational amplifier via a second input circuit. Further, the emitter of the transistor is electrically coupled to the first input of the differential operational amplifier via a third input circuit and to the second input of the differential operational amplifier via a fourth input circuit. In such cases, the first input circuit and the third input circuit share a first gain circuit, and the first gain circuit includes a first selectable capacitance and a second selectable capacitance. The second input circuit and the fourth input circuit share a second gain circuit, and the second gain circuit includes a third selectable capacitance and a fourth selectable capacitance. Configuring the analog to digital converter to select the first gain and configuring includes selecting the first selectable capacitance of the first gain circuit and selecting the third selectable capacitance of the second gain circuit. Configuring the analog to digital converter to select the second gain includes selecting the second selectable capacitance of the first gain circuit and selecting the fourth selectable capacitance of the second gain circuit.

Yet other embodiments of the present invention provide methods for resistance compensated temperature measurement. Such methods include providing a diode connected transistor and applying a first current, a second current, a third current and a fourth current to the diode connected transistor. In response to each of the aforementioned excitation currents, a corresponding base-emitter voltage is exhibited on the diode connected transistor. The four corresponding base-emitter voltages are combined such that a resistance error is eliminated.

This summary provides only a general outline of some embodiments according to the present invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is related to temperature measurement, and more particularly to temperature measurements using a transistor or diode as a sensor.

Various embodiments of the present invention provide temperature measurement methods and systems. In some cases, such temperature measurement systems and methods provide for series resistance compensation through use of four base-emitter voltages and corresponding gain factors. Using such approaches provides an efficient approach to compensating for series resistance that in many cases does not require additional circuitry when compared with a standard two base-emitter voltage measurement approach. Further, using such an approach may utilize only a multiplication and subtraction function to yield a resistance corrected delta base-emitter output value that corresponds to circuit temperature.

Turning toFIG. 2, a temperature measurement system200in accordance with one or more embodiments of the present invention is shown. Temperature measurement system200includes a static n-factor value210, a temperature calculation circuit295, and a first order integrating analog to digital converter205. In addition, temperature measurement system200includes a transistor270that is diode connected and used as a temperature sensor. It should be noted that while the figure shows an NPN transistor, that other circuits in accordance with one or more embodiments of the present invention may utilize a PNP transistor.

The collector and the base of transistor270are electrically coupled to a variable current source260. Further, the base and emitter of transistor270are electrically coupled to analog to digital converter205via an input filter264. Input filter264includes a series resistor261, a series resistor262and a capacitor263. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of input filters that may be used to couple transistor270to analog to digital converter205. In particular, the base of transistor270is electrically coupled to an input of analog to digital converter205via a switch235(i.e., a positive input243of an operational amplifier240via switch235and an input circuit299) and to another input of analog to digital converter205via a switch236(i.e., a negative input242of operational amplifier240via switch236and an input circuit298). The emitter of transistor270is electrically coupled to one input of analog to digital converter205via a switch237(i.e., positive input243of operational amplifier240via switch237and input circuit299) and to the other input of analog to digital converter205via a switch238(i.e., negative input242of operational amplifier240via switch238and input circuit298). It should be noted that while the disclosed embodiments are described as canceling out resistance added in an input filter, that other sources of resistance in the circuit are also canceled out in the same process. Such other sources of resistance may include, but are not limited to, bus resistance, pin resistance, resistances due to transistor non-idealities, and the like.

Analog to digital converter205includes a loadable counter271that is synchronized to a sample clock292; a result counter260that is also synchronized to sample clock292; operational amplifier240; a comparator250; a number of switches that are also synchronized to sample clock292; a number of sample and feedback capacitors; a voltage reference249and an inverted version of the aforementioned voltage reference248; and a result register280. It should be noted that the inverted version of the voltage reference may be generated in any number of ways including, but limited to, applying a negative reference voltage, using a positive reference voltage and a defined sampling sequence, or the like. In particular, the inverted version of voltage reference248is electrically coupled to negative input242of operational amplifier240via a switch225and a sample capacitor229, and to positive input243of operational amplifier240via a switch226and a sample capacitor221. Voltage reference249is electrically coupled to negative input242of operational amplifier240via a switch227and sample capacitor229, and to positive input243of operational amplifier240via a switch228and sample capacitor221.

Input circuit299includes a sample capacitor231and a sample capacitor232. Sample capacitor231is selectively coupled via a switch251. Input circuit299is electrically coupled to positive input243of operational amplifier240. Input circuit298includes a sample capacitor234and a sample capacitor235. Sample capacitor235is selectively coupled via a switch252. Input circuit298is electrically coupled to negative input242of operational amplifier240. A switch244aelectrically couples a negative output of operational amplifier240to positive input243, and a switch245aand a feedback capacitor246aelectrically couple the negative output of operational amplifier240to positive input243. A switch244belectrically couples a positive output of operational amplifier240to negative input243, and a switch245band a feedback capacitor246belectrically couple the positive output of operational amplifier240to negative input242.

The gain of operational amplifier250is proportional to the ratio of the input capacitance to the feedback capacitance. Thus, where switch251of input circuit299and switch252of input circuit298are open, one gain (i.e., G1) is exhibited by operational amplifier240. Where switch251of input circuit299and switch252of input circuit298are closed, another gain (i.e., G2) is exhibited by operational amplifier240. Thus analog to digital converter205may be operated with two distinct gains depending upon the position of switch251and switch252. In one embodiment of the present invention, capacitors221,229,231,232,234and235are all the same size.

The differential output of operational amplifier240is also electrically coupled to the differential input of comparator250. The output of comparator250is provided to result counter260, and as a feedback to control switches225,226,227,228. Result counter260counts up synchronously each time the output of comparator250is a logic ‘1’ (i.e., each time the positive output of operational output is greater than the negative output). The number of samples that are counted is equivalent to the value loaded from static n-factor value210. Each time a sample is completed, loadable counter271is decremented. Once the output value of loadable counter271is a logic ‘0’, the output value of result counter260is stored to result register280and result counter260is reset. The output (i.e., Delta Vbe265) of result register280is provided to a temperature calculation circuit295. The value of Delta Vbe265represents the difference between four or more different base-emitter voltages of transistor270compensated for series resistance (e.g., resistor261and resistor262). The number of samples taken before a result is produced corresponds to static n-factor value210. In some embodiments of the present invention, static n-factor value210is replaced with a programmable register. In such cases, the n-factor value is programmable (i.e., the number of samples taken before producing a result is programmable in such a way that it effectively results in use of a different n-factor value).

In operation, variable current source260is set to apply four different currents to transistor270. Further, switches235,236,237,238,251and252are configured to apply a different gain when each of the four currents are applied to transistor270. Upon application of each of the currents, the base-emitter voltage (Vbe) of transistor270is detected. In one particular embodiment of the present invention, a first current (I1) is applied with a negative first gain (−G1). Subsequently, a second current (I2) is applied with a positive second gain (G2). Subsequently, a third current (I3) is applied with a negative second gain (−G2). Finally, a fourth (I4) is applied with a positive first gain (G1). To apply I1with a gain −G1, variable current source260provides I1to transistor270, switch236and switch237are closed, switches244are closed, switch235and switch238are open, switches245are open, and switch251and switch252are open. To apply I2with a gain G2, variable current source260provides I2to transistor270, switch236and switch237are opened, switches244are closed, switch235and switch238are closed, switches245are open, and switch251and switch252are closed. To apply I3with a gain −G2, variable current source260provides I3to transistor270, switch236and switch237are closed, switches244are closed, switch235and switch238are open, switches245are open, and switch251and switch252are closed. To apply I4with a gain G1, variable current source260provides I4to transistor270, switch236and switch237are opened, switches244are closed, switch235and switch238are closed, switches245are open, and switch251and switch252are open.

Application of the aforementioned currents results in a corresponding charge being deposited on sample capacitors232and234where a gain of G1is selected, or a corresponding charge on sample capacitors231,232,233and234where a gain G2is selected. After the aforementioned sample phase is completed, the sampled charge is transferred to feedback capacitors246during an integration phase. Transferring the charge to feedback capacitors246involves opening switches244and closing switches245, and reversing particular ones of the input switches. In particular, where the charge corresponding to the aforementioned I1at a gain of −G1was previously sampled and is to be transferred to feedback capacitors246, switch236and switch237are opened, switches244are opened, switch235and switch238are closed, switches245are closed, and switch251and switch252are open. Where the charge corresponding to the aforementioned I2at a gain of G2was previously sampled and is to be transferred to feedback capacitors246, switch236and switch237are closed, switches244are opened, switch235and switch238are opened, switches245are closed, and switch251and switch252are closed. Where the charge corresponding to the aforementioned I3at a gain of −G2was previously sampled and is to be transferred to feedback capacitors246, switch236and switch237are opened, switches244are opened, switch235and switch238are closed, switches245are closed, and switch251and switch252are closed. Where the charge corresponding to the aforementioned I4at a gain of G1was previously sampled and is to be transferred to feedback capacitors246, switch236and switch237are closed, switches244are opened, switch235and switch238are opened, switches245are closed, and switch251and switch252are opened. The aforementioned sample phase and integration phase may be accomplished on succeeding edges (using both positive and negative edges) of a clock, on succeeding negative edges of the clock, or on succeeding positive edges of the clock.

Transferring the charge from sample capacitors231,232,233and244to feedback capacitors246results in an output from operational amplifier240at the input of comparator250. The output of operational amplifier240is processed by comparator250to produce either a logic ‘1’ or a logic ‘0’ depending upon the positive output of operational amplifier240relative to the negative output of operational amplifier240. Where the result is a logic ‘0’, result counter260is not incremented. In the next pass, the voltage at the base of transistor270is again sampled and integrated for the four currents and gains, and the same comparison process is repeated.

Alternatively, on any pass where the result of the comparison is a logic ‘1’, result counter260is incremented. Further, where the result is a logic ‘1’, the negative version of the voltage reference248is sampled along with the voltage at the base of transistor270on the next pass. This is done by closing switch227, switch226and switches244. This causes charge to build up on reference sample capacitor221and sample capacitor229representing the negative reference voltage, and charge to build up on the selected set of sample capacitors231,232,234representing the voltage at the base of transistor270. The charge from the aforementioned sample capacitors is then transferred to feedback capacitors during an integration phase where switch225and switch227are closed. By continually re-sampling the voltage at the base of transistor270and sampling the negative voltage reference any time a logic ‘1’ is noted, the following residue will remain for a counter value of X and a number of iterations N:
Residue=NVin−XVref,
where Vinis the difference between two or more base-emitter voltages. The digital value representing the voltage at the base of transistor270is that maintained on result counter260at the end of the process. The process is continued for the number of samples loaded into loadable counter271(i.e., static n-factor value210or another programmed value). An increase in the number of samples reduces the residue and increases the resolution of Delta Vbe265.

It should be noted that analog to digital converter205may be implemented as another type of analog to digital converter capable of sampling base-emitter voltages derived from application of four or more currents and exhibiting two or more gains. Based on the disclosure provided herein, one of ordinary skill in the art will recognize other types of analog to digital converters that may be used in relation to various embodiments of the present invention.

Further, it should be noted that in some embodiments of the present invention some form of processing circuit may be implemented between transistor270and analog to digital converter205. In such cases circuit operation is substantially as described above with the exception that transistor is electrically coupled to analog to digital converter205via the processing circuit and filter264. In any event, transistor270is electrically coupled to analog to digital converter205. In particular instances, the processing circuit performs the delta-Vbe computation and analog to digital converter205converts the output of the intervening processing circuit.

Turning toFIG. 3, a timing diagram300depicts performance of series resistance compensation using temperature measurement system200in accordance with one or more embodiments of the present invention. As shown, during an operational period310, temperature measurement system200is initialized during an initialization period320. After initialization, a number of samples360are taken during a sampling period340. Each sample may include excitation of the sampled transistor using four or more excitation currents (I1, I2, I3, I4) with at least four different gains (G1, −G1, G2, −G2). In one particular embodiment of the present invention, I1is one hundred microamperes, I2is fifty microamperes, I3is five microamperes, I4is ten microamperes, G1is a unity gain, and G2is a gain of two. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other currents and gains that may be used in accordance with one or more embodiments of the present invention to provide resistance and/or transistor non-ideality compensation.

As shown, during each sampling period represented by samples361and362, transistor270is excited using four excitation currents and four different gains: (1) I1and −G1, (2) I2and G2, (3) I3and −G2, and (4) I4and G1. As shown, this process of sampling and integrating base-emitter voltages corresponding to the aforementioned currents at the particular gains is completed a number of times, n, until the desired resolution of Delta Vbe265is achieved. At the end of sampling period340(e.g., once the output of loadable counter271is zero), the output of the analog to digital converter (e.g., Delta Vbe265) represents a delta Vbecreated using four excitation currents and corresponding gains. In this case, Delta Vbe265is represented by the following equation:
DeltaVbe=G2*(Vbe2−Vbe3)−G1*(Vbe4−Vbe1)
In the preceding equation, Vbe1is the base-emitter voltage on transistor270upon application of I1. Similarly, Vbe2is the base-emitter voltage on transistor270upon application of I2, Vbe3is the base-emitter voltage on transistor270upon application of I3, and Vbe4is the base-emitter voltage on transistor270upon application of I4. By incorporating four currents at different gains into the generation of Delta Vbe265errors due to series resistance and/or transistor non-idealities are reduced or eliminated.

In particular, to compensate for errors introduced by series resistance, two independent ΔVbevalues may be generated and used. Where the two independent ΔVbevalues are created with the correct magnitude and gain, a simple subtraction between the ΔVbevalues cancels out any effect of the series resistance. The following equations represent the method:
G2*ΔVbe2-3=G2*(Vbe2−Vbe3)=G2*[(Ie2−Ie3)*RS+n*kT/q*ln(Ic2/Ic3)]; and
G1*ΔVbe4-1=G1*(Vbe4−Vbe1)=G1*[(Ie4−Ie1)*Rs+n*kT/q*ln(Ic4/Ic1)].
In the preceding equations, Vbe1is the base-emitter voltage on transistor270upon application of I1. Similarly, Vbe2is the base-emitter voltage on transistor270upon application of I2, Vbe3is the base-emitter voltage on transistor270upon application of I3, and Vbe4is the base-emitter voltage on transistor270upon application of I4. Again, the ‘n’ term is known as the non-ideality factor or emission coefficient is assumed to be a constant (n=1.008) for diodes and transistors. Ie1is the current passing through the emitter upon application of a first current, and Ic1is the current passing through the collector upon application of the same current. Ie2, Ic2, Ie3, Ic3, Ie4, Ic4, are similarly emitter and collector currents corresponding to the application of the respective second excitation current, third excitation current, and fourth excitation current. Rsis the series resistance.

Each of the preceding equations includes an error component that is a function of the series resistance Rs. In particular, the error component of G2*ΔVbe2-3is G2*(Ie2−Ie3)*Rs, and the error component of G1*ΔVbe4-1is G1*(Ie4−Ie1)*Rs. Where the gains (G1and G2) and the currents (I1, I2, I3, I4) are appropriately selected, subtraction of G1*ΔVbe4-1from G2*ΔVbe2-3causes the error components to drop out and leaves a differential base-emitter voltage value that is proportional to the absolute temperature of transistor270. The following equation represents Delta Vbe265and is equivalent to subtracting G1*ΔVbe4-1from G2*ΔVbe2-3:
DeltaVbe=G2*[(Ie2−Ie3)*Rs+n*kT/q*ln(Ic2/Ic3)]−G1*[(Ie4−Ie1)*Rs+n*kT/q*ln(Ic4/Ic1)].
As an example, where Ic2=10*Ic3, Ic4=2*Ic2, Ic1=2*Ic3, Ie2=10*Ie3, Ie4=2Ie2, Ie1=2*Ie3, and G2=2*G1, then the following Delta Vbe265equation reduces to:
DeltaVbe=2*G1*[(10*Ie3−Ie3)*Rs+n*kT/q*ln(10)]−G1*[(20*Ie3−2Ie3)*Rs+n*kT/q*ln(10)];
thus,
DeltaVbe=G1*[n*kT/q*ln(10)].
As can be seen from the preceding equations, Delta Vbe265does not include an error component due to the series resistance. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of ratios between the aforementioned currents and gains that can be used to eliminate the error component from Delta Vbe265in accordance with one or more embodiments of the present invention. Further, based on the disclosure provided herein, one of ordinary skill in the art will recognize a number of excitation currents and gains that may be used in relation to one or more embodiments of the present invention to perform serial resistance compensation.

FIG. 4is a flow diagram400showing a method in accordance with various embodiments of the present invention for performing series resistance compensation in a temperature measurement scenario. Following flow diagram400, a sample count is initialized (block405), and a result count is initialized (block410). In some embodiments of the present invention this initialization may include loading a predetermined number of samples to be taken into a loadable down counter, and resetting a result counter to zero. A gain of −G1and an excitation current I1is selected (block415), and a temperature measurement circuit is excited using the aforementioned parameters (block420). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block425).

Next, a gain of G2and an excitation current I2is selected (block430), and the temperature measurement circuit is excited using the aforementioned parameters (block435). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block440). Subsequently, a gain of −G2and an excitation current I3is selected (block445), and the temperature measurement circuit is excited using the aforementioned parameters (block450). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block455). Then, a gain of G1and an excitation current I4is selected (block460), and the temperature measurement circuit is excited using the aforementioned parameters (block465). The temperature measurement circuit then samples and integrates the base-emitter voltage corresponding to the aforementioned excitation parameters (block470).

Once the preceding four sample and integration phases have been performed (block415to block470), a comparison of the output of the integrator is performed (block475). Where the result of the comparison is positive (block475), the result count is incremented (block480). It is next determined if the predetermined number of samples has been taken (block485). Where all of the samples have not yet been taken (block485), the processes of block415through block480are repeated. Alternatively, where the predetermined number of samples has been taken (block485), the result is provided to a temperature calculation circuit (block495). The provided result represents a Delta Vbeincorporating series resistance compensation in accordance with various embodiments of the present invention.

In conclusion, the present invention provides novel systems, devices, methods for data temperature measurement. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, other embodiments of the present invention, Delta Vbe265may be generated over two operational periods310. In the first operational period310, a gain of G1is selected and transistor270is repeatedly excited at a fourth current followed by a first current. This process is repeated for an appropriate number of samples to generate the aforementioned G1*ΔVbe4-1. During the second operational period310, a gain of G2is selected and transistor270is repeatedly excited at a second current followed by a third current. This process is again repeated for an appropriate number of samples to generate the aforementioned G2*ΔVbe2-3. In a post process, G1*ΔVbe4-1may be subtracted from G2*ΔVbe2-3to yield Delta Vbe265. As another example, the processes and systems are shown using a bipolar transistor, but other embodiments of the present invention may use other types of transistors or junction devices. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.