Vertical semiconductor device and method of fabricating the same

A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2019-0068800, filed on Jun. 11, 2019, in the Korean Intellectual Property Office, and entitled: “Vertical Semiconductor Device and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

Example embodiments relate to a vertical semiconductor device and a method of fabricating the same, and more particularly, to a vertical semiconductor device having excellent electrical characteristics and high reliability and a method of fabricating the same.

2. Description of the Related Art

In a vertical semiconductor device formed on an n-well, an erase operation of a memory cell may be performed by using a gate induced drain leakage (GIDL) method using a GIDL phenomenon. In this case, there is still room for improvement in the dispersion control of the electrical characteristics of devices.

SUMMARY

According to an aspect of embodiments, there is provided a vertical semiconductor layer including a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

According to another aspect of embodiments, there is provided a vertical semiconductor layer including a common source semiconductor layer on an n-well of a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, the channel pattern including a channel pattern extension portion protruding toward the support layer in a lateral direction of the support layer, and a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern.

According to another aspect of embodiments, there is provided a vertical semiconductor layer, including a common source semiconductor layer on an n-well of a substrate having a p-conductivity type, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, the channel pattern extending through a channel hole, and the support layer being in direct contact with a lowermost gate of the gates in the channel hole, and an information storage layer extending between the gates and the channel pattern, wherein a sidewall of the support layer facing the channel hole is offset relative to sidewalls of the gates facing the channel hole, and wherein the information storage layer extends horizontally toward the support layer along a lower surface of the lowermost gate of the gates and then extends in the first direction along the sidewall of the support layer.

According to another aspect of embodiments, there is provided a method of fabricating a vertical semiconductor device, the method including forming a lower sacrificial layer pattern on an n-well of a substrate having a p-conductivity type, forming a support layer on the lower sacrificial layer pattern, alternately stacking a sacrificial layer and an insulating layer on the support layer, forming a channel hole penetrating the sacrificial layer, the insulating layer, the support layer, and a lower sacrificial layer, partially removing an exposed sidewall of the support layer in the channel hole, forming an information storage material layer and a channel pattern in the channel hole, replacing the lower sacrificial layer with a common source semiconductor layer, and replacing the sacrificial layer with gates.

DETAILED DESCRIPTION

FIG. 1is an equivalent circuit diagram of a memory cell array MCA of a semiconductor device. In particular,FIG. 1illustrates an equivalent circuit diagram of a vertical NAND (VNAND) flash memory device having a vertical channel structure according to embodiments.

Referring toFIG. 1, the memory cell array MCA may include a plurality of memory cell strings MS including a plurality of memory cells MC1, MC2, . . . , MCn−1, MCn arranged in a vertical direction (z-direction inFIG. 1) on a substrate. Each of the plurality of memory cell strings MS may include the plurality of memory cells MC1, MC2, . . . , MCn−1, MCn connected in series, a string selection transistor SST, a ground selection transistor GST, and a gate induced drain leakage (GIDL) transistor GDT. The plurality of memory cells MC1, MC2, . . . , MCn−1, MCn may store data, and a plurality of word lines WL1, WL2, . . . , WLn−MCn−1, and MCn may be respectively connected to the memory cells MC1, MC2, . . . , MCn−1, MCn to control the memory cells MC1, MC2, . . . , MCn−1, MCn.

A gate terminal of the ground selection transistor GST may be connected to the ground selection line GSL, and a source terminal of the ground selection transistor GST may be connected to a source terminal of the GIDL transistor GDT, and a source terminal of the GIDL transistor GDT may be connected to the common source line CSL. A gate terminal of the string selection transistor SST may be connected to the string selection line SSL, and a source terminal of the string selection transistor SST may be connected to a drain terminal of the memory cell MCn, and a drain terminal of the string selection transistor SST may be connected to a plurality of bit lines BL1, BL2, . . . , BLm: BL. AlthoughFIG. 1illustrates an example that each memory cell string MS includes one ground selection transistor GST, one string selection transistor SST, and one GIDL transistor GDT, two or more ground selection transistors GST, two or more string selection transistors SST, and/or two or more GIDL transistors GDT may be included in each memory cell string MS.

When a signal is applied to the gate terminal of the string selection transistor SST through the string selection line SSL, a signal applied through the plurality of bit lines BL may be provided to the plurality of memory cells MC1, MC2, . . . , MCn−1, MCn and thus a data write operation may be performed. When a signal is applied to the gate terminal of the ground selection transistor GST through the ground selection line GSL, an erase operation of the plurality of memory cells MC1, MC2, . . . , MCn−1, MCn may be performed.

According to embodiments, a common source semiconductor layer110(seeFIG. 2) having an n-type conductivity type may be provided between the ground selection line GSL and the common source line CSL, and thus, an erase operation of the memory cell array MCA may be performed by using a GIDL method. For example, an erase voltage Ver may be applied to the common source line CSL and a reference voltage Vref may be applied to a GIDL erase line GEL connected to a gate of the GIDL transistor GDT. At this time, due to a potential difference between the erase voltage Ver and the reference voltage Vref, a high electric field may be generated in the common source semiconductor layer110adjacent to the GIDL erase line GEL and may generate electrons and holes in the common source semiconductor layer110. Holes generated in the common source semiconductor layer110may be injected into the memory cell string MS such that the erase operation of the plurality of memory cells MC1, MC2, . . . , MCn−1, MCn may be performed.

The semiconductor device of the related art uses an erase method using a substrate body and performs an erase operation of a plurality of memory cells by directly injecting holes from a substrate into a memory cell string electrically connected to the substrate. However, it has been necessary to form a lower substructure by a complicated process in order to provide an injection path of the holes from the substrate to the memory cell string. However, the semiconductor device according to embodiments may implement an erase operation by using the GIDL method through a simplified structure.

FIG. 2is a lateral cross-sectional view showing a semiconductor device100according to embodiments.

Referring toFIG. 2, a substrate101may include an upper surface101M extending in a first horizontal direction (x-direction) and a second horizontal direction (y-direction). The substrate101may include a semiconductor material, e.g., a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include monocrystalline silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium. The substrate101may be provided as a bulk wafer or an epitaxial layer. In another embodiment, the substrate101may include a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate.

The substrate101may have a first conductivity type, and a well of a second conductivity type opposite to the first conductive type may be formed in the substrate101. In some embodiments, the substrate101may have a p-conductivity type, and an n-well101nof an n-conductivity type may be provided in the substrate101. For example, the substrate101may be of a p-conductivity type, and the n-well101nof an n-conductivity type extending from the upper surface101M of the substrate101to a predetermined depth may be provided in the substrate101.

The common source semiconductor layer110may be provided on the substrate101. The common source semiconductor layer110may include a conductive layer, e.g., a semiconductor layer doped with impurities. In some embodiments, the common source semiconductor layer110may include a polysilicon layer doped with impurities. The common source semiconductor layer110may be separated by an isolation region180and may be configured to contact a common source line103nprovided below, e.g., adjacent, the isolation region180.

In some embodiments, a protection layer161and a support insulating layer162may be provided on the common source semiconductor layer110. For example, as illustrated inFIG. 2, the protection layer161may be formed between the support insulating layer162and the common source semiconductor layer110, e.g., to completely separate the support insulating layer162and the common source semiconductor layer110.

The support insulating layer162may isolate a support layer120(to be described later) from the common source semiconductor layer110when the support layer120is electrically conductive. The support insulating layer162may include, e.g., silicon oxide. In some embodiments, the support insulating layer162may include at least one of a high density plasma (HDP) oxide layer, Tetra Ethyl Ortho Silicate (TEOS), Plasma Enhanced-TEOS (PE-TEOS), O3-TEOS, Undoped Silicate Glass (USG), Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boro Phospho Silicate Glass (BPSG), Fluoride Silicate Glass (FSG), Spin On Glass (SOG), and Tonen SilaZene (TOSZ).

The protection layer161may protect the support insulating layer162from being removed when an information storage layer140(to be described later) is partially removed. The protection layer161may include, e.g., polysilicon. In some embodiments, the protection layer161may include, e.g., polysilicon doped with carbon.

The support layer120may be provided on the protection layer161, e.g., the support insulating layer162may be formed between the support layer120and the protection layer161. For example, the support layer120may include polysilicon doped or not doped with impurities. The support layer120may include, e.g., a support connection structure120cbetween the common source semiconductor layers110.

A plurality of gate electrodes130may be stacked on the support layer120. For example, as illustrated inFIG. 2, the plurality of gate electrodes130may include a gate electrode130GD of the GIDL erase line GEL (seeFIG. 1), a gate electrode130G of the ground selection line GSL (seeFIG. 1), gate electrodes130W1, . . . ,130Wn of the memory cell word lines WL1, . . . , WLn, and a gate electrode130sof the string selection line SSL (seeFIG. 1) may be sequentially provided on the support layer120and may be separated from each other by an interlayer insulating layer160. That is, as illustrated inFIG. 2, the plurality of gate electrodes130and a plurality of interlayer insulating layers160may be arranged alternately on the support layer120. An upper interlayer insulating layer165may be formed on an uppermost one of the gate electrodes130, e.g., on the gate electrode130sof the string selection line SSL.

Each of the gate electrodes130, i.e., each of the gate electrode130GD of the GIDL erase line, the gate electrode130G of the ground selection line GSL, the gate electrodes130W1, . . . ,130Wn of the memory cell word lines WL1, . . . , WLn, and the gate electrode130sof the string selection line SSL may include metal, e.g., tungsten (W). Each of the gate electrodes130may further include a diffusion barrier, and may include, e.g., any one of tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN).

A channel hole150H (FIG. 3) may be provided to pass through the upper interlayer insulating layer165, the gate electrodes130, the interlayer insulating layers160, the support layer120, the support insulating layer162, the protection layer161, and the common source semiconductor layer110on the substrate101. In the channel hole150H, the information storage layer140, a channel pattern150, and a buried insulating layer175may be provided.

As shown inFIGS. 3 and 4, the information storage layer140may have a structure including a tunneling dielectric layer142, a charge storage layer144, and a blocking dielectric layer146sequentially formed in the stated order from a channel pattern150toward a sidewall of the channel hole150H. e.g., the tunneling dielectric layer142may be between the charge storage layer144and the channel pattern150. Relative thicknesses of the tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146forming the information storage layer140are not limited to those illustrated inFIGS. 3 and 4, and may be variously modified.

The tunneling dielectric layer142may tunnel charges from the channel pattern150to the charge storage layer144. The tunneling dielectric layer142may include, e.g., silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and the like.

The charge storage layer144is a region that may store electrons that passed through the tunneling dielectric layer142from the channel pattern150and may include a charge trap layer. The charge storage layer144may include, e.g., quantum dots or nanocrystals. Here, the quantum dots or the nanocrystals may be composed of fine particles of a conductor, e.g., a metal or a semiconductor. The charge storage layer144may include, e.g., silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities.

The blocking dielectric layer146may include, e.g., silicon oxide, silicon nitride, or a high permittivity high-k metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include, e.g., hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. Here, the high permittivity metal oxide may refer to a metal oxide having a dielectric constant greater than that of silicon oxide.

The channel pattern150may include a semiconductor material, e.g., polysilicon or single crystal silicon. The semiconductor material may be doped with p-conductivity or n-conductivity impurity ions. The buried insulating layer175may be provided in the channel pattern150. In some embodiments, the buried insulating layer175may have a general cylindrical pillar structure. For example, as illustrated inFIG. 2, the buried insulating layer175may be formed in a center of each of the channel holes150H, and the channel pattern150may be formed along entire sidewalls of the buried insulating layer175, e.g., the channel pattern150may be between the sidewall of the buried insulating layer175and a sidewall of the channel hole150H. In some embodiments, when the channel pattern150is formed in a pillar shape, the buried insulating layer175may be omitted.

As illustrated inFIG. 3, a residue information storage layer140resmay be provided adjacent to a lower portion of the channel pattern150. The residue information storage layer140resmay have substantially the same structure as the information storage layer140, and may be positioned between a bottom of the channel pattern150and the n-well101nof the substrate101.

The isolation region180may be formed between adjacent memory cell strings using different gate electrodes130. The isolation regions180may extend in a second direction (y-direction), may be spaced apart in a first direction (x-direction), and may separate the gate electrodes130from each other in the first direction (x-direction). A common source line103nmay be disposed below the isolation region180.

The isolation region180may include a conductive layer182, a barrier layer186, and an insulating spacer184. The conductive layer182may include a metal, e.g., tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), etc. The barrier layer186may include, e.g., TiN. The insulating spacer184may include any insulating material e.g., silicon oxide, silicon nitride, or silicon oxynitride.

For example, as illustrated inFIG. 2, the conductive layer182, the barrier layer186, and the insulating spacer184may have a structure extending above the gate electrode130sof the string selection transistors SST (seeFIG. 1). In another example, the isolation region180may have a structure in which the conductive layer182has a small thickness adjacent to the common source line103nnot to extend higher than the lowermost interlayer insulating layer160, and the buried insulating layer is disposed on an upper portion of the conductive layer182. When the isolation region180has such a structure, the insulating spacer184may be omitted. In yet another example, the isolation region180may have a structure in which the insulating spacers184are formed only to a sidewall of the gate electrode130G of the ground selection transistor GST (seeFIG. 1) such that the conductive layer182is formed at a predetermined height between the insulating spacers184, and the buried insulating layer is disposed on the upper portion of the conductive layer182.

Bit lines193(BL1, BL2, . . . , BLm inFIG. 1) may be connected to drain sides of the string selection transistors SST (seeFIG. 1) of the string selection line SSL. For example, the bit lines193may extend in the first direction (x-direction) and may be formed in line shapes spaced from each other in the second direction (y-direction). The bit line193may be electrically connected to the drains of the string selection transistors SST (seeFIG. 1) of the string selection line SSL through a contact plug195formed on the channel pattern150.

FIG. 3is a partially enlarged view showing in detail region III ofFIG. 2according to an embodiment.

Referring toFIG. 3, the channel pattern150may include a channel pattern extension portion150p. The channel pattern extension portion150pmay be formed integrally with a portion of the channel pattern150extending in a vertical direction (z-direction). For example, as illustrated inFIGS. 2-3, the channel pattern150may include a vertical portion150v, e.g., having a linear film shape, that extends along the z-direction and is conformal on the outer sidewall of the buried insulating layer175, and the channel pattern extension portion150pmay extend laterally away from the vertical portion150vof the channel pattern150along the x-direction, e.g., the channel pattern extension portion150pand the vertical portion150vmay be integral with each other to define a single and seamless structure.

The vertical portion150vof the channel pattern150may have a thickness T2, e.g., as measured from the buried insulating layer175to the information storage layer140along the x-direction, in the portion extending in the vertical direction (z-direction). In addition, the channel pattern extension portion150pmay have a thickness T1in the vertical direction (z-direction), e.g., as measured from a top surface of the common source semiconductor layer110along the z-direction. The thickness T1may be greater than the thickness T2. In some embodiments, the thickness T1may be at least twice the thickness T2. In some embodiments, the thickness T1may have a value from about 2 times the thickness T2(2*T2) to about 100 times the thickness T2(100*T2), e.g., from about (2*T2) to about (80*T2), from about (2.2*T2) to about (70*T2), and from about (2.5*T2) to about (50*T2).

The support layer120may have a side wall120W which is retreated, e.g., offset, by a length L1relative to a side wall of the channel hole150H, e.g., a distance between a sidewall of the channel hole150H to the lateral side wall120W of the support layer120along the x-direction may be defined as the length L1. As the side wall of the channel hole150H and a lateral sidewall of the gate electrode130contact each other, the side wall120W of the support layer120that faces the channel hole150H may be retreated, e.g., offset, by the length L1relative to the side wall of the gate electrode130, e.g., the gate electrode130may extend toward the channel hole150H to overhang the support layer120along the x-direction by the length L1. As a result, the information storage layer140may be conformal along lateral sidewalls of the gate electrode130and of the support layer120, i.e., to extend along sidewalls of the interlayer insulating layer160and the gate electrode130in a vertical direction (z-direction) and extend along a lower surface of the gate electrode130GD of the GIDL erase line in a horizontal direction (x-direction, y-direction, and/or a combination thereof) toward the support layer120. Also, the information storage layer140may extend in the vertical direction (z-direction) along the sidewall of the support layer120. For example, the information storage layer140may extend to at least a lower end of the support layer120. For example, the information storage layer140may extend to the lower end of the support layer120and then extend along an upper surface of the support insulating layer162in the horizontal direction (x-direction, y-direction, and/or a combination thereof).

The tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146constituting the information storage layer140may extend horizontally by a predetermined length along the upper surface of the support insulating layer162and then terminate. At this time, positions of terminated ends of the tunneling dielectric layer142and the blocking dielectric layer146may be different from each other in a direction in which the information storage layer140extends, e.g., the charge storage layer144may extend beyond the tunneling dielectric layer142and the blocking dielectric layer146along the x-direction.

The channel pattern150may extend at least partially to a level lower than the upper surface101M of the substrate101, e.g., relative to a bottom of the substrate101. The residue information storage layer140resmay be provided below the lowermost end of the channel pattern150. The residue information storage layer140resmay have substantially the same structure as the information storage layer140. That is, the residue information storage layer140resmay include a residual tunneling dielectric layer142b, a residual charge storage layer144b, and a residual blocking dielectric layer146b, and compositions thereof may be substantially the same as those of the tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146, respectively.

The common source semiconductor layer110may extend horizontally along the upper surface101M of the substrate101, e.g., along the x-direction, and contact the channel pattern150. In some embodiments, a portion of the common source semiconductor layer110may extend, e.g., continuously, in the vertical direction (z-direction) and also contact the lower surface of the channel pattern extension portion150p. The common source semiconductor layer110may also extend in the horizontal direction (x-direction, y-direction, and/or a combination thereof) while contacting the lower surface of the channel pattern extension portion150pand may contact an end portion of the information storage layer140. For example, as illustrated inFIG. 3, a portion of the common source semiconductor layer110may extend, e.g., continuously, in the vertical direction (z-direction) along the channel pattern150and bend around edges of the protection layer161and the support insulating layer162(below the channel pattern extension portion150p) toward edges of the information storage layer140.

The common source semiconductor layer110may be disposed generally below the channel pattern extension portion150pin the vertical direction (z-direction). For example, a level of the uppermost end of the common source semiconductor layer110may be equal to or lower than a level of the lower surface of the channel pattern extension portion150pin the vertical direction (z-direction).

As shown inFIG. 3, because the uppermost end of the common source semiconductor layer110is defined by the channel pattern extension portion150p, a constant distance between the gate electrode130GD of the GIDL erase line and the uppermost end of the common source semiconductor layer110, i.e., distance T3which is a sum of the thickness T1and a thickness of the information storage layer140, may be secured. That is, even though the exact position of the end portion of the information storage layer140on the channel pattern extension portion150palong the horizontal direction may vary, the end portion of the information storage layer140is still on, e.g., directly on, the lower surface of the channel pattern extension portion150p, thereby providing constant distance T3between the gate electrode130GD and the common source semiconductor layer110.

In other words, a position of an end portion of the information storage layer140may be somewhat different for each individual semiconductor device due to various parameters in a fabrication process. If a distance between the gate electrode130GD of the GIDL erase line and the common source semiconductor layer110were to be determined according to the position of the end portion of the information storage layer140, there could be a performance deviation between individual semiconductor devices, e.g., as the position of an end portion of the information storage layer140may slightly vary among the individual semiconductor devices. In contrast, in the semiconductor device according to embodiments, as illustrated inFIG. 3, because the end portion of the information storage layer140is positioned at an arbitrary point in the horizontal direction (x-direction, y-direction, and/or a combination thereof) along the lower surface of the channel pattern extension portion150p, even though the position of the end portion of the information storage layer140is somewhat different for each individual semiconductor device, the distance T3between the gate electrode130GD of the GIDL erase line and the common source semiconductor layer110may remain constant. Thus, the performance deviation between individual semiconductor devices may be greatly reduced.

In addition, because an overlapping area between the channel pattern150and the gate electrode130GD of the GIDL erase line increases (i.e., the entire side surface and a part of the lower surface of the gate electrode130GD), an erase operation using a GIDL method may be more easily performed.

Further, a thickness of the channel pattern extension portion150pmay be sufficiently great, and thus, a concentration of impurities (for example, phosphorus (P)) due to diffusion may be sufficiently secured.

FIG. 4is a partially enlarged view showing in detail a region III ofFIG. 2in the semiconductor device100according to another embodiment. The embodiment shown inFIG. 4is the same as the embodiment shown inFIG. 3, except that the information storage layer140further includes a vertical extension portion extending in a vertical direction (z-direction) from a lower portion of the channel pattern extension portion150p. Therefore, the following description focuses on this difference.

Referring toFIG. 4, in some embodiments, an end portion of the information storage layer140may have a level between a lower surface of the protection layer161and an upper surface of the support insulating layer162. That is, as illustrated inFIG. 4, the end portion of the information storage layer140may bend to extend along and overlap at least a terminal edge of the support insulating layer162among the protection layer161and the support insulating layer162. A level of the uppermost end of the common source semiconductor layer110may be defined by the end portion of the information storage layer140. A distance between the gate electrode130GD of the GIDL erase line GEL and the common source semiconductor layer110may be determined as T3aaccording to a position of the end portion of the information storage layer140.

In the embodiments ofFIG. 4, the common source semiconductor layer110may be in direct contact with the end portion of the information storage layer140. In the embodiment ofFIG. 3, the common source semiconductor layer110may be in direct contact with the lower surface of the channel pattern extension portion150pand the end portion of the information storage layer140.

FIG. 5is a lateral cross-sectional view showing a semiconductor device100A according to other embodiments. The semiconductor device100A according to embodiment shown inFIG. 5has a major difference in a structure of a lower end portion of the channel pattern150as compared with the semiconductor device100shown inFIG. 2. Therefore, the following description will focus on this difference.

Referring toFIG. 5, the substrate101may include polycrystalline silicon doped with p-conductivity and may include the n-well101nof an n-conductivity type having a predetermined depth in the upper surface101M of the substrate101. A lower end of the channel pattern150may extend to a level lower than the upper surface101M of the substrate101. The lower end of the channel pattern150may include a lower extension portion150pnextending by a predetermined distance in a lateral direction (x-direction, y-direction, and/or a combination thereof) at the level lower than the upper surface101M of the substrate101. In some embodiments, a sidewall of the lower extension portion150pnmay be substantially aligned with a sidewall of the channel pattern extension portion150p.

A residue information storage layer240resmay be provided on the sidewall and a lower surface of the lower extension portion150pn. In addition, the residue information storage layer240resmay partially extend onto an upper surface of the lower extension portion150pn. The residue information storage layer240resmay have substantially the same configuration as the information storage layer140, which will be described in more detail later. A sidewall of the residue information storage layer240resmay be substantially aligned with a sidewall of the information storage layer140.

FIG. 6is a partially enlarged view showing in detail a region VI of the semiconductor device100A ofFIG. 5according to an embodiment. The semiconductor device100A according to an embodiment shown inFIG. 6has a major difference in a structure of a lower end portion of the channel pattern150as compared with the semiconductor device100shown inFIG. 3. Therefore, the following description will focus on this difference.

Referring toFIG. 6, a dimension in which the lower extension portion150pnprotrudes in a horizontal direction (x-direction, y-direction, and/or a combination thereof) may be substantially the same as a dimension in which the channel pattern extension portion150pprotrudes in the horizontal direction. As a result, a sidewall of the lower extension portion150pnmay be substantially aligned with a sidewall of the channel pattern extension portion150p, e.g., extension portions150pand150pnmay vertically overlap each other.

The residue information storage layer240resmay include a residual tunneling dielectric layer142c, a residual charge storage layer144c, and a residual blocking dielectric layer146c, and compositions thereof may be substantially the same as those of the tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146, respectively. In some embodiments, a sidewall of the information storage layer140(i.e. a sidewall of the support layer120) on the sidewall of the channel pattern extension portion150pmay be substantially aligned with a sidewall of the residue information storage layer240res.

The residual tunneling dielectric layer142cand the residual charge storage layer144cmay conformally extend along a lower surface and a side surface of the lower extension portion150pn. In addition, the residual tunneling dielectric layer142cand the residual charge storage layer144cmay extend by a predetermined length along an upper surface of the lower extension portion150pn. The residual blocking dielectric layer146cmay conformally extend along a lower surface and a side surface of the lower extension portion150pn. The residual blocking dielectric layer146cmay not extend onto the upper surface of the lower extension portion150pn.

In some embodiments, a thickness T4of the lower extension portion150pnin a vertical direction (z-direction) may be greater than or equal to the thickness T1of the channel pattern extension portion150pin the vertical direction (z-direction). When the thickness T4is greater than the thickness T1, the buried insulating layer175may partially extend into the lower extension portion150pnunlike inFIG. 6.

In the case where a polycrystalline silicon substrate (i.e., polysilicon) is used as the substrate101, when the support layer120is partially removed to retreat, e.g., offset, the sidewall of the support layer120, because the substrate101is partially removed similarly to the support layer120, a space is formed in which the lower extension portion150pnis to be formed. Also, in a subsequent process, the residue information storage layer240resand the lower extension portion150pnmay fill the space.

FIGS. 7A to 7Iare lateral cross-sectional views of stages in a method of fabricating the semiconductor device100, according to an embodiment.

Referring toFIG. 7A, a protection insulating layer103is formed on the substrate101on which the n-well101nis formed, and a lower sacrificial layer pattern110sis formed on the protection insulating layer103. The lower sacrificial layer pattern110smay be formed by, e.g., performing a photolithography process after forming a lower sacrificial material layer. The lower sacrificial layer pattern110smay include, e.g., silicon nitride. The protection insulating layer103may include any material having etch selectivity with respect to the lower sacrificial layer pattern110sand may include, e.g., silicon oxide.

After forming the lower sacrificial layer pattern110s, the protection layer161and the support insulating layer162are sequentially and conformally formed on the upper surface and the side surface of the lower sacrificial layer pattern110sand the protection insulating layer103, which is partially exposed. The protection layer161may include, e.g., polysilicon. In some embodiments, the protection layer161may include polysilicon doped with carbon. The support insulating layer162may include silicon oxide, which has been described in detail with reference toFIG. 2and thus a detailed description thereof is omitted. The protection layer161and the support insulating layer162may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), but are not limited thereto.

Referring toFIG. 7B, a support layer material layer120A may be formed on the support insulating layer162and an insulating layer160amay be formed thereon. The support layer material layer120A may include doped or undoped polysilicon, and the insulating layer160amay include any insulating layer, e.g., silicon nitride, silicon oxide, or silicon oxynitride. The insulating layer160amay be formed by forming an insulating material layer on the polysilicon and then performing chemical mechanical polishing (CMP) so that the upper surface of the support layer material layer120A is exposed.

Referring toFIG. 7C, sacrificial layers130hand the interlayer insulating layers160may be alternately stacked on the support layer material layer120A and the insulating layer160a. According to some embodiments, the interlayer insulating layers160and the sacrificial layers130hmay include different materials. According to some embodiments, the interlayer insulating layers160and the sacrificial layers130hmay include materials having high etch selectivity with respect to each other. For example, when the sacrificial layers130hinclude silicon oxide, the interlayer insulating layers160may include silicon nitride. As another example, when the sacrificial layers130hinclude silicon nitride, the interlayer insulating layers160may include silicon oxide. As another example, when the sacrificial layers130hinclude undoped polysilicon, the interlayer insulating layers160may include silicon nitride or silicon oxide. The sacrificial layers130hand the interlayer insulating layers160may be formed by CVD, PVD, or ALD.

FIG. 8is a partially enlarged view showing in detail a region B ofFIG. 7D.

Referring toFIGS. 7D and 8, the channel hole150H that sequentially passes through the sacrificial layers130hand the interlayer insulating layers160, the support layer material layer120A, the support insulating layer162, the protection layer161, the lower sacrificial layer pattern110s, and the protection insulating layer103may be formed. The channel hole150H may be formed by anisotropic etching.

Subsequently, a support layer recess120R may be formed by partially removing the support layer120and retreating, e.g., offsetting, the sidewall of the support layer120. The sidewall of the support layer120may be retreated, e.g., positioned farther, from the sidewall of the channel hole150H thereabove. The sidewall of the support layer120may be further retreated, e.g., offset, from a sidewall of the sacrificial layer130hpositioned directly on the support layer120, e.g., a portion of the support layer120may be removed to have the sacrificial layer130hdirectly on the support layer120overhang the support layer120.

Partial removal of the support layer120may be performed, e.g., by selective isotropic etching of the support layer120including polysilicon. According to a selection of an etchant, polysilicon and single crystal silicon may be different in terms of an etch selectivity. At this time, when the substrate101is single crystal silicon, it is possible to selectively remove the support layer120without substantially removing the single crystal silicon.

FIG. 9is a partially enlarged view showing in detail the region B ofFIG. 7E.

Referring toFIGS. 7E and 9, an information storage material layer140mmay be substantially conformally formed on an exposed inner surface of the channel hole150H. In detail, a blocking dielectric material layer146m, a charge storage material layer144m, and a tunneling dielectric material layer142mmay be formed conformally from the side wall of the channel hole150H, and may be formed by using e.g., ALD. The blocking dielectric material layer146m, the charge storage material layer144m, and the tunneling dielectric material layer142mmay respectively include substantially the same material as the blocking dielectric layer146, the charge storage layer144, and the tunneling dielectric layer142, and thus detailed descriptions thereof will be omitted.

The channel pattern150may then be formed on the inner surface of the tunneling dielectric material layer142m. The channel pattern150may be formed by, e.g., CVD or ALD. The channel pattern150may be formed to fill the inside of the support layer recess120R, thereby forming the channel pattern extension portion150p. In an implementation, the channel pattern150may completely fill the inside of the support layer recess120R. In some embodiments, the channel pattern150may be formed to have a greater thickness to completely fill the inside of the support layer recess120R and then be anisotropically etched to a desired thickness.

Then, an inner space of the channel pattern150may be filled by the buried insulating layer175. A formation of the buried insulating layer175may be performed by e.g., CVD or ALD.

FIG. 10is a partially enlarged view showing in detail the region B ofFIG. 7F.

Referring toFIGS. 7F and 10, a mask pattern may be formed on the upper interlayer insulating layer165, and a word line cut opening180H may be formed using the mask pattern as an etching mask. An upper surface of the lower sacrificial layer pattern110smay be exposed at a bottom portion of the word line cut opening180H. In some embodiments, an upper surface of the substrate101may be exposed at the bottom portion of the word line cut opening180H.

Thereafter, a spacer185may be formed to cover an upper surface of the upper interlayer insulating layer165and a sidewall of the word line cut opening180H. In exemplary embodiments, the spacer185may be selected to have a high etch selectivity with respect to the lower sacrificial layer pattern110s. For example, the spacer185may be silicon oxide, silicon oxynitride, or the like.

Subsequently, the lower sacrificial layer pattern110smay be removed by selective etching. In some embodiments, the lower sacrificial layer pattern110smay be removed by wet or dry isotropic etching. The protection insulating layer103may prevent the substrate101from being damaged when the lower sacrificial layer pattern110sis selectively removed. By removing the lower sacrificial layer pattern110s, the side surface of the information storage material layer140mhaving the same level as the lower sacrificial layer pattern110smay be exposed.

FIGS. 11 to 13are lateral cross-sectional views showing stages in a method of removing an exposed part of the information storage material layer140mwhich may correspond to the region B ofFIG. 7G.

Referring toFIG. 11, an exposed part of the blocking dielectric material layer146m(FIG. 10) may be removed by isotropic etching. The blocking dielectric layer146and the residual blocking dielectric layer146bmay be formed by partially removing the blocking dielectric material layer146m. In this case, when the support insulating layer162has an etching characteristic similar to that of the blocking dielectric material layer146m, the support insulating layer162may be partially removed together with the blocking dielectric material layer146m, e.g., to form the opening through the blocking dielectric material layer146madjacent the support insulating layer162and the residual blocking dielectric layer146b. In addition, when the protection insulating layer103has an etching characteristic similar to that of the blocking dielectric material layer146m, the protection insulating layer103may be removed together with the blocking dielectric material layer146m.

Referring toFIG. 12, an exposed part of the charge storage material layer144m(FIG. 10) may be removed by isotropic etching. The charge storage layer144and the residual charge storage layer144bmay be formed by partially removing the charge storage material layer144m, e.g., to form the opening through the charge storage material layer144madjacent the support insulating layer162and the residual blocking dielectric layer146b.

Referring toFIG. 13, an exposed part of the tunneling dielectric material layer142m(FIG. 10) may be removed by isotropic etching. The tunneling dielectric layer142and the residual tunneling dielectric layer142bmay be formed by partially removing the tunneling dielectric material layer142m.

An end portion of the tunneling dielectric layer142and an end portion of the blocking dielectric layer146are not necessarily aligned with each other. In some embodiments, the end portion of the tunneling dielectric layer142may protrude toward the channel pattern150in a horizontal direction compared to the end portion of the blocking dielectric layer146.

By summarizingFIGS. 11 to 13, the information storage layer140may be formed by removing a first portion140m1that is the exposed part of the information storage material layer140mand a second portion140m2adjacent to the first portion140m1. Also, by removing the first portion140m1and the second portion140m2, the residue information storage layer140resmay be formed adjacent to a lower end of the channel pattern150.

InFIG. 13, end portions of the tunneling dielectric layer142, the charge storage layer144, the blocking dielectric layer146, and the support insulating layer162are formed in curved surfaces, but embodiments are not limited thereto. InFIG. 13, end portions of the tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146are disposed on a lower surface of the channel pattern extension portion150p, but embodiments are not limited thereto. In some embodiments, the end portions of the tunneling dielectric layer142, the charge storage layer144, and the blocking dielectric layer146may be disposed on a side surface of the protection layer161.

FIG. 14is a partially enlarged view showing in detail the region B ofFIG. 7G.

Referring toFIGS. 7G and 14, a common source semiconductor material layer110mmay be provided to bury a part where the lower sacrificial layer pattern110sis removed and a part where the information storage material layer140mis removed. The common source semiconductor material layer110mmay be formed by diffusing and depositing a reactant to the part where the lower sacrificial layer pattern110sis removed and the part where the information storage material layer140mis removed through the word line cut opening180H.

The common source semiconductor material layer110mmay be deposited on a surface of an exposed sidewall (i.e., the spacer185) of the word line cut opening180H and on the upper interlayer insulating layer165. The common source semiconductor material layer110mmay be formed by, e.g., CVD, ALD, or the like. The common source semiconductor material layer110mmay be a polysilicon layer doped with impurities.

Referring toFIG. 7H, an upper surface of the substrate101may be exposed by removing the common source semiconductor material layer110mdeposited on the exposed sidewall of the word line cut opening180H and the upper interlayer insulating layer165. Thereafter, the common source line103nmay be formed by removing the spacer185and injecting impurities at a relatively high concentration from the upper surface of the substrate101to a predetermined depth.

Referring toFIG. 7I, the sacrificial layers130hmay be replaced with the gate electrode130. The sacrificial layers130hmay be selectively removed because the sacrificial layers130hhave etch selectivity with respect to the interlayer insulating layer160and the upper interlayer insulating layer165. Thereafter, the gate electrode130may be formed by forming a conductive material constituting the gate electrode130by, e.g., CVD or ALD, at a position where the sacrificial layers130hare removed.

Referring back toFIG. 2, the isolation region180including the conductive layer182, the barrier layer186, and the insulating spacer184may be formed in the word line cut opening180H. Specifically, the insulating spacer184may be formed in the word line cut opening180H, and then the barrier layer186and the conductive layer182may be formed. The conductive layer182, the barrier layer186, and the insulating spacer184may be formed by using, e.g., CVD, ALD, or the like, and specific materials thereof are described above, and thus detailed descriptions thereof will be omitted.

Subsequently, the conductive capping layer177, which is electrically conductive, may be formed by partially removing upper ends of the information storage layer140, the channel pattern150, and the buried insulating layer175. Thereafter, the upper interlayer insulating layer192may be formed and the contact plug195passing through the upper interlayer insulating layer192and extending in a vertical direction (z-direction) may be formed and then a bit line193which is electrically conductive and connected to the contact plug195may be formed. The contact plug195and the bit line193may include at least one of a metal (e.g., tungsten, titanium, tantalum, copper or aluminum), and a conductive metal nitride (e.g., TiN or TaN).

FIGS. 15A to 15Fare lateral cross-sectional views showing stages in a method of fabricating the semiconductor device100A, according to another embodiment.FIG. 16is a partially enlarged view showing in detail the region B ofFIG. 15A. Operations corresponding toFIGS. 7A to 7Care common, and thus redundant descriptions are omitted.

Referring toFIGS. 15A and 16, the channel hole150H that sequentially passes through the sacrificial layers130hand the interlayer insulating layers160, the support layer material layer120A, the support insulating layer162, the protection layer161, the lower sacrificial layer pattern110s, and the protection insulating layer103may be formed. The channel hole150H may be formed by anisotropic etching.

Subsequently, the support layer120and the support layer recess120R may be formed by partially removing the support layer material layer120A to retreat, e.g., position farther away, the sidewall of the support layer material layer120A. The sidewall of the support layer120may be retreated, e.g., offset, from the sidewall of the channel hole150H thereabove. The sidewall of the support layer120may be further retreated, e.g., offset, from a sidewall of the sacrificial layer130hpositioned directly on the support layer120.

In addition, the substrate101may be a polycrystalline silicon substrate. In this case, when the sidewall of the support layer material layer120A is retreated, e.g., offset, the substrate101may be also partially removed to form the lower recess122R. In some embodiments, a distance at which the support layer recess120R is recessed in the horizontal direction and a distance at which the lower recess122R is recessed in the horizontal direction may be substantially the same.

FIG. 17is a partially enlarged view illustrating in detail the region B ofFIG. 15B.

Referring toFIGS. 15B and 17, the information storage material layer140mmay be substantially conformally formed on an exposed inner surface of the channel hole150H. Specifically, a blocking dielectric material layer146m, a charge storage material layer144m, and a tunneling dielectric material layer142mmay be formed sequentially and conformally from the side wall of the channel hole150H, and may be formed by using, e.g., ALD.

Also, the channel pattern150and the buried insulating layer175may be formed on an inner surface of the tunneling dielectric material layer142m. The channel pattern150may be formed to bury the support layer recess120R such that the channel pattern extension portion150pmay be formed. In addition, the channel pattern150may be formed to bury the lower recess122R such that the lower extension portion150pnmay be formed.

The information storage material layer140m, the channel pattern150, and the buried insulating layer175are described in detail with reference toFIG. 9. Thus, additional descriptions thereof will be omitted.

FIG. 18is a partially enlarged view showing in detail the region B ofFIG. 15C.

Referring toFIGS. 15C and 18, a mask pattern may be formed on the upper interlayer insulating layer165, the word line cut opening180H may be formed using the mask pattern as an etching mask, the spacer185may be formed, and then the lower sacrificial layer pattern110smay be removed by selective etching.

FIGS. 19 to 21are lateral cross-sectional views showing a method of removing an exposed part of the information storage material layer140mwhich may correspond to the region B ofFIG. 15D.

Referring toFIG. 19, an exposed part of the blocking dielectric material layer146mmay be removed by isotropic etching. The blocking dielectric layer146and a residual blocking dielectric layer146cmay be formed by partially removing the blocking dielectric material layer146m. In this case, when the support insulating layer162has an etching characteristic similar to that of the blocking dielectric material layer146m, the support insulating layer162may be partially removed together with the blocking dielectric material layer146m.

In addition, when the protection insulating layer103has an etching characteristic similar to that of the blocking dielectric material layer146m, the protection insulating layer103may be removed together with the blocking dielectric material layer146m. In addition, when the protection insulating layer103is removed, the blocking dielectric material layer146mcovering an upper surface of the lower extension portion150pnmay be entirely exposed by isotropic etching. In this case, most of a horizontal extension part of the blocking dielectric material layer146mextending in a horizontal direction (x-direction, y-direction, or a combination thereof) along the upper surface of the lower extension portion150pnmay be removed.

Referring toFIG. 20, an exposed part of the charge storage material layer144mmay be removed by isotropic etching. The charge storage layer144and the residual charge storage layer144cmay be formed by partially removing the charge storage material layer144m.

Referring toFIG. 21, an exposed part of the tunneling dielectric material layer142mmay be removed by isotropic etching. The tunneling dielectric layer142and the residual tunneling dielectric layer142cmay be formed by partially removing the tunneling dielectric material layer142m.

FIG. 22is a partially enlarged view showing in detail the region B ofFIG. 15D.

Referring toFIGS. 15D and 22, a common source semiconductor material layer110mmay be provided to bury a part where the lower sacrificial layer pattern10sis removed and a part where the information storage material layer140mis removed. The common source semiconductor material layer110mmay be deposited on a surface of an exposed sidewall (i.e., the spacer185) of the word line cut opening180H and on the upper interlayer insulating layer165.

Referring toFIG. 15E, an upper surface of the substrate101may be exposed by removing the common source semiconductor material layer110mdeposited on the exposed sidewall of the word line cut opening180H and the upper interlayer insulating layer165. Thereafter, the common source line103nmay be formed by removing the spacer185and injecting impurities at a relatively high concentration from the upper surface of the substrate101to a predetermined depth.

Referring toFIG. 15F, the sacrificial layers130hmay be replaced with the gate electrode130. The sacrificial layers130hmay be selectively removed because the sacrificial layers130hhave etch selectivity with respect to the interlayer insulating layer160and the upper interlayer insulating layer165. Thereafter, the gate electrode130may be formed by forming a conductive material constituting the gate electrode130by e.g., CVD or ALD, at a position where the sacrificial layers130hare removed.

Referring toFIG. 5, the isolation region180including the conductive layer182, the barrier layer186, and the insulating spacer184may be formed in the word line cut opening180H. Specifically, the insulating spacer184may be formed in the word line cut opening180H and then the barrier layer186and the conductive layer182may be formed. The conductive layer182, the barrier layer186, and the insulating spacer184may be formed by, e.g., CVD, ALD, or the like, and specific materials thereof are described above, and thus detailed descriptions thereof will be omitted.

Subsequently, the conductive capping layer177may be formed by partially removing upper ends of the information storage layer140, the channel pattern150, and the buried insulating layer175. Thereafter, the upper interlayer insulating layer192, the contact plug195, and the bit line193are formed, which are the same as described with reference toFIG. 2, and thus detailed descriptions thereof will be omitted.

FIG. 23is a cross-sectional view illustrating a semiconductor device100B according to embodiments. InFIG. 23, the same reference numerals as inFIGS. 1 to 22denote the same components.

Referring toFIG. 23, a peripheral circuit region PERI may be formed at a lower vertical level than the memory cell region MCR. A lower substrate310may be disposed at a lower vertical level than the substrate101, and an upper level of the lower substrate310may be lower than an upper level of the substrate101. An active region may be defined in the lower substrate310by a device isolation layer322, and a plurality of driving transistors330T may be formed on the active region. The plurality of driving transistors330T may include a driving circuit gate structure332and an impurity region312disposed in a part of the lower substrate310on both sides of the driving circuit gate structure332.

A plurality of wiring layers342, a plurality of contact plugs346, and a lower interlayer insulating layer350may be disposed on the lower substrate310. The plurality of contact plugs346may connect between the plurality of wiring layers342or between the plurality of wiring layers342and the driving transistors330T. In addition, the lower interlayer insulating layer350may cover the plurality of wiring layers342and the plurality of contact plugs246.

Because the substrate101needs to be formed on the lower interlayer insulating layer350, the substrate101may include polysilicon instead of single crystal silicon. As described above with reference toFIGS. 15A and 16, when the substrate101is polysilicon, the lower recess122R may be formed together when the support layer recess120R is formed. As a result, the lower extension portion150pnmay be formed at a lower end of the channel pattern150.

According to embodiments, a vertical semiconductor device having excellent electrical characteristics and high reliability, as well as a method of manufacturing thereof, is provided. That is, a vertical semiconductor device having excellent electrical characteristics, e.g., a GIDL erase, and high reliability may be fabricated relatively easily.

In other words, according to embodiments, after formation of a channel hole, a support layer recess is formed by enlarging a sidewall of a support layer, and a space is filled with ONO and a channel pattern. When ONO isotropic etching is performed to form an ONO butting contact, an ONO end part is limited at a lower portion of the channel pattern extension portion. As a result, a distance between a gate of a GIDL transistor and a common source semiconductor layer may be maintained constant, and a region in which the gate of the GIDL transistor and the channel pattern overlap increases. The channel pattern extension portion also facilitates diffusion control, thereby improving GIDL efficiency and reducing leakage of a ground selection transistor.