Method for cleaning metal gate surface

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.

In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease.

Accordingly, an improved method for fabricating a semiconductor device including a metal gate is desired.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In addition, although the present disclosure provides examples may be used in a “gate last” metal gate process, one skilled in the art may recognize applicability of the present invention to other processes of fabricating the gate structure, and/or use of other materials in the gate structure.

FIG. 1is a flowchart illustrating a method100for fabricating an integrated circuit (IC) structure according to some embodiments of the present disclosure. It should be understood that additional processes may be provided before, during, and after the method100ofFIG. 1, and that some other processes may be briefly described herein.FIGS. 2-12are cross-sectional views of an IC structure200at various stages of fabrication using the method100ofFIG. 1according to some embodiments of the present disclosure. It should be noted that the IC structure200may be formed as part of a semiconductor device and may be fabricated with a CMOS process flow.

Referring toFIGS. 1 and 2, the method100begins with step102by providing the IC structure200. As shown inFIG. 2, the IC structure200includes a substrate202, a first dielectric layer204disposed on the substrate202, an etch stop layer (ESL)214formed on the first dielectric layer204, and a second dielectric layer216formed on the ESL214. As shown inFIG. 2, a metal gate (MG)206including sidewall spacers208may be formed in the first dielectric layer204. The first dielectric layer204may also include a conductive feature210and a barrier layer212formed to wrap around the conductive feature210.

In some embodiments, the substrate202may be a silicon wafer. The substrate202may also include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. In some alternative embodiments, the substrate202includes a semiconductor on insulator (SOI). In some embodiments, a dielectric layer may be formed over the substrate202. In some embodiments, the dielectric layer may include silicon oxide. In some embodiments, the dielectric layer may additionally or alternatively include silicon nitride, silicon oxynitride, or other suitable dielectric material.

The substrate202may also include various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, light doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED). The substrate202may further include other functional features such as a resistor or a capacitor formed in and on the substrate. In some embodiments, the substrate202may further include lateral isolation features provided to separate various devices formed in the substrate202. The isolation features may include shallow trench isolation (STI) features to define and electrically isolate the functional features. In some examples, the isolation regions may include silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof. The isolation regions may be formed by any suitable process. The various IC structures200may further include other features, such as silicide disposed on S/D and gate stacks overlying channels.

Referring toFIG. 2, the first dielectric layer204may be an interlayer dielectric (ILD) layer. In some embodiments, the first dielectric layer204may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating material. In some embodiments, the first dielectric layer204may include a single layer or multiple layers. In some embodiments, the first dielectric layer204may be formed using a suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin-on technique.

Still referring toFIG. 2, the MG206may include aluminum (Al), tungsten (W), copper (Cu), or other suitable metal material. In some examples, the MG206may be formed using a gate last process (also referred to as a replacement poly gate process (RPG)). In the gate last process, a dummy dielectric and dummy poly gate structure may be initially formed and may be followed by a normal CMOS process flow until deposition of the ILD204. The dummy dielectric and dummy poly gate structure may then be removed using a suitable etching process and replaced with a high-k gate dielectric/metal gate structure. In some embodiments, the high-k gate dielectric/metal gate structure may include an interface layer, a gate dielectric layer, a work function layer, and the MG206. The MG206may be deposited by CVD, physical vapor deposition (PVD), electrochemical plating (ECP), or other suitable process. Excess metal may then be removed by a chemical mechanical polishing (CMP) process to produce a planar surface of the dielectric layer204, the MG206, and/or the conductive feature210. In some alternative examples, the metal gate (MG) layer206may be formed using any suitable process.

The sidewall spacers208may be formed on the sidewalls of the MG206. The spacers208may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), a low-k dielectric material, combinations thereof, and/or other suitable material. The spacers208may have a multiple layer structure, for example, including one or more liner layers. The liner layer may include a dielectric material such as silicon oxide, silicon nitride, and/or other suitable materials. The spacers208may be formed by methods including deposition of suitable dielectric material and anisotropically etching the material to form the spacer208profile.

Still referring toFIG. 2, the conductive feature210may include a metal contact, a metal via, or a metal line. In some embodiments as shown inFIG. 2, the conductive feature210may be further surrounded by a barrier layer212to prevent diffusion and/or provide material adhesion. In some examples, the conductive feature210may include aluminum (Al), copper (Cu) or tungsten (W). The barrier layer206may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN) or tantalum silicon nitride (TaSiN). The barrier layer212may include metal that is electrically conductive but does not permit inter-diffusion and reactions between the second dielectric layer204and the conductive feature210. The barrier layer212may include refractory metals and their nitrides. In various examples, the barrier layer212includes TiN, TaN, Co, WN, TiSiN, TaSiN, or combinations thereof. The conductive feature210and the barrier layer212may be formed by a procedure including lithography, etching and deposition. For example, the conductive feature210and the barrier layer212may be deposited by PVD, CVD, metal-organic chemical vapor deposition (MOCVD), and ALD, or other suitable technique. In some alternative embodiments, the conductive feature210includes an electrode of a capacitor, a resistor or a portion of a resistor. In some examples, the conductive feature210includes a silicide feature disposed on respective source, drain or gate electrode. The silicide feature may be formed by a self-aligned silicide (salicide) technique. A CMP process may be used to form a coplanar surface of the dielectric layer204and the conductive feature210. In some embodiments, a cap layer may be formed on the conductive feature210.

As shown inFIG. 2, the ESL214is formed on the first dielectric layer204. In some embodiments, the ESL214includes a dielectric material chosen to have etching selectivity for proper etch process at subsequent processes to form contact trenches. In some embodiments, the ESL214may include silicon nitride (Si3N4), silicon oxynitride, titanium nitride, and/or other suitable materials. In some embodiments, the ESL214may be deposited using any suitable technique, such as CVD, physical vapor deposition (PVD), ALD, or an epitaxial growing process. In some embodiments, the thickness of the ESL214is in a range from about 10 Å to about 300 Å.

After forming the ESL214, the second dielectric layer216is formed on the ESL214. The materials included in the second dielectric layer216may be substantially similar to the materials included in the first dielectric layer204. The formation of the second dielectric layer216may be substantially similar to the first dielectric layer204.

Referring toFIGS. 1 and 3, method100proceeds to step104by etching the second dielectric layer216and the ESL214to form a trench218. In some embodiments, the trench218may be formed by a lithography process and an etching process including one or more etching steps. The lithography process is used to pattern the second dielectric layer216. In some examples, the etching process includes a first etch step to remove the second dielectric layer216in the contact regions using a dry etch process with a fluorine-containing etchant, such as difluoromethane (CH2F2) plasma. The first etch step may stop at the ESL214. Then a second etch step is used to selectively remove the ESL214in the contact regions using a wet etch with a suitable etchant without etching the MG206and the conductive feature210in the first dielectric layer204as shown inFIG. 3.

As shown inFIG. 3, after etching to form the trench218at step104, a top surface219of the MG206is exposed by the opening of the trench218. As shown inFIG. 4, the metal materials on the top surface219may be oxidized to form a first oxide layer220during the etching process and/or during the transfer process before the IC structure200is transferred into a metal contact deposition tool. In some embodiments, the thickness of the first oxide layer220is in a range from about 40 Å to about 90 Å. In some examples, the MG206includes Al, and the first oxide layer220includes Al2O3. The formed Al2O3between the MG206and the later deposited metal contact may increase the contact resistance thus reduce the performance and reliability of the IC structure200. Therefore, it is necessary to remove the first oxide layer220before the IC structure200is transferred into the metal contact deposition tool.

Referring toFIGS. 1 and 5, method100proceeds to step106by removing the first oxide layer220formed on the top surface of the MG206. In some examples, the first oxide layer220may be removed using an argon (Ar) sputter bombardment. However, this method may result in a chopping profile of the trench218, where the width W1of the upper portion of the trench218is over widened. The over widening of the trench218may cause lateral electrical leak if the later deposited metal contact is under polished. In addition, in the region with high pattern density, the over widening of the trench218may result in different thickness between the ILD and the isolation regions. In some alternative examples, the first oxide layer220may be removed using a wet etching process including using dilute hydrofluoric (HF) acid. However, due to the low selectivity of the HF between Al and Al2O3, the MG206, and even the functional metal beneath the MG gate206may be damaged during the wet etching process.

Still referring toFIG. 5at step106, the first oxide layer220may be removed by a wet etching process using an acid solution222with high selectivity between the metal in the MG206(e.g., Al) and the first oxide layer220(e.g., Al2O3) to etch the first oxide layer. In some embodiments, the acid solution222includes a phosphoric acid (H3PO4) solution due to the high selectivity between Al and Al2O3. In some embodiments, the Al2O3may be removed by the H3PO4solution using a reaction as shown in equation 1:
Al2O3+2H2PO4−+2H+→2AlPO4+3H2O  (1)

In some embodiments, the H3PO4solution includes H3PO4dissolved in de-ionized water (DIW) with a concentration in a range from about 5% to about 25%. The temperature of the H3PO4solution may be no greater than 50° C. The time using the H3PO4solution to clean the surface of the MG206may be in a range from about 5 seconds to about 180 seconds. Because the H3PO4solution used to remove the oxide layer on the MG206has high selectivity between Al and Al2O3, the MG206may not be damaged and the chopping effect can be avoided during the surface clean process. After the removal of the first oxide layer220, the top surface of the219of the MG206can be exposed as shown inFIG. 5.

Referring toFIGS. 1 and 6, method100proceeds to step108by rinsing, drying and transferring the IC structure200to the metal gate deposition tool. After cleaning the IC structure with the H3PO4solution to remove the first oxide layer in step106, the IC structure200may be rinsed with DIW, and spin-dried before the subsequent processes. In some embodiments, the metal contact deposition tool includes a PVD tool including one or more deposition/sputtering chambers that are connected to each other. For example, the IC structure200may be transferred to a pre-sputter chamber that is connected to the metal contact deposition chamber. In some embodiments, during the transferring process of the IC structure200, the metal materials on the top surface219may be oxidized to form a second oxide layer224. The second oxide layer224may be a native oxide layer which is formed when the MG206is exposed to the air in the ambient condition. In some embodiments, the thickness of the second oxide layer224is in a range from about 10 Å to about 30 Å. In some examples, the MG206includes Al, and the second oxide layer224includes Al2O3.

Referring toFIGS. 1 and 6, method100proceeds to step109by baking the IC structure200under vacuum in the pre-sputter chamber at a temperature in a range from about 50° C. to about 500° C. to remove the moisture and any organic chemical residue on the IC structure200.

Referring toFIGS. 1 and 7, method100proceeds to step110by reducing the second oxide layer224(e.g., Al2O3layer) to a metal (e.g., Al) included in the MG206. In some embodiments, the second oxide layer224may be reduced using a reducing agent226, such as nitrogen/hydrogen (N2/H2) plasma, in the pre-sputter chamber of the metal contact deposition tool. The N2/H2plasma is used as a chemical reactive agent that is used to reduce the second oxide layer224in the IC structure200. The N2/H2plasma includes H2+, H+, H., N2+, N+, N., and the Al2O3may be reduced to Al by a reaction as shown in equation 2:
Al2O3+3N2/H2(H2+,H+,H.,N2+,N+,N.)→2Al+3H2O  (2)

In some embodiments during reduction of the second oxide layer224, the flow rate of the N2is in a range from about 1000 sccm to about 4000 sccm. The flow rate of the H2is in a range from about 100 sccm to about 500 sccm. The pressure of the chamber for reducing the second oxide layer may be controlled to be in a range from about 10 mTorr to about 3000 mTorr. The plasma power is in a range from about 100 W to about 2000 W. During the reducing process using the N2/H2plasma, a bias power in a range from about 5 W to about 1500 W is applied to the substrate of the IC structure200, so that the charged molecules and ions in the N2/H2plasma can be introduced to the substrate to react with the second oxide layer (e.g., Al2O3layer) of the IC structure200as shown in equation 2. In some embodiments, the surface reduction process using the N2/H2plasma treatment may be conducted at a temperature in a range from about 50° C. to about 500° C. The treatment time may be in a range from about 10 seconds to about 240 seconds.

At step110, the N2/H2plasma can effectively reduce the Al2O3layer on the surface of the MG206to Al without damaging the MG206. The chopping effect can be minimized so that the process window of the IC structure can be improved. In some embodiments, when the dielectric layer216includes an organic material, the N2/H2plasma treatment may also expand the upper portion of the trench218, so that the width W1of the upper portion of the trench218may become slightly greater after reducing the second oxide layer224using the N2/H2plasma. The expansion effect of the trench218at step110can be tuned by adjusting the condition of the N2/H2plasma treatment.

Referring toFIGS. 1 and 8, method100proceeds to an optional step112by performing an Ar sputtering process in a sputtering chamber of the metal contact deposition tool. The sputtering chamber may be connected to the pre-sputter chamber and the metal contact deposition chamber, so that the IC structure200can be transferred among the chambers of the metal contact deposition tool without being exposed to the ambient environment. In some embodiments, the Ar sputtering process may be performed in the pre-sputter chamber. In order to provide a better gap filling in the following processes, the width W1of the upper portion of the trench218may be expanded to a width W2, where W2is greater than W1. In some embodiments, the width W2is in a range from about 5% to about 20% greater than the width W1. In some embodiments, the sputtering process includes using an Ar ion bombardment. For example, a bias power in a range from about 50 W to about 1000 W is applied to the substrate of the IC structure200, so that the charged ions and molecules in the Ar plasma can bombard the walls of the trench218to expand the trench218as shown inFIG. 8. In some embodiments, the Ar flow rate is in a range from about 5 sccm to about 100 sccm. The pressure of the sputter chamber may be in a range from about 0.01 mTorr to about 100 mTorr. The plasma power is in a range from about 50 W to about 1000 W. The Ar sputtering process may be performed in a temperature range from about room temperature (RT) to about 200° C.

Referring toFIGS. 1 and 9, method100proceeds to step114by forming a barrier layer230conformed to the bottom and the walls of the trench218. In some embodiments, the barrier layer230includes a metal and is electrically conductive but does not permit inter-diffusion and reactions between the dielectric layer216and the metal contact to be filled in the trench218. The barrier layer230may include refractory metals and their nitrides. In various examples, the barrier layer230includes TiN, TaN, Co, WN, TiSiN, TaSiN, or combinations thereof. In some embodiments, the barrier layer230may include multiple films. For example, Ti and TiN films may be used as the barrier layer230. In some embodiments, the barrier layer230may be deposited by PVD, CVD, metal-organic chemical vapor deposition (MOCVD), ALD, sputtering, or other suitable technique. The barrier layer230may be deposited in the metal contact deposition chamber of the metal contact deposition tool.

Referring toFIGS. 1 and 10, method100proceeds to step116by depositing a metal layer232on the barrier layer230to fill the trench218ofFIG. 9. In some embodiments, the metal layer232may include copper (Cu), aluminum (Al), tungsten (W) or other suitable conductive material. In some embodiments, the metal layer232may also include Cu or Cu alloy, such as copper magnesium (CuMn), copper aluminum (CuAl) or copper silicon (CuSi). In some embodiments, the metal layer232may be deposited by PVD. In some examples, the metal layer232may include Cu, and the Cu layer may be formed by depositing a Cu seed layer using PVD, and then forming a bulk Cu layer by plating. The metal layer232is deposited in the metal contact deposition chamber of the metal contact deposition tool. During the metal contact deposition, a carrier gas (e.g., Ar gas) may be used to bombard a metal target to form a metal vapor. The metal vapor can then be deposited to form the metal layer232on the IC structure. In some embodiments, the metal layer232may include a metal contact, a metal via, or a metal line.

Referring toFIGS. 1 and 11, method100proceeds to step118by performing a chemical mechanical polishing (CMP) process to remove excessive metal layer232to form a metal contact234in the trench218. A substantially coplanar top surface of the metal contact234and the dielectric layer216is formed. The CMP process is performed in a CMP tool. The CMP process may include polishing, cleaning, and drying processes. After the CMP process, the IC structure200may be transferred out of the CMP tool for subsequent processes.

It is to be understood that the IC structure200may include a plurality of dielectric layers and conductive features (e.g., metal lines, metal plugs, and MG) integrated to form an interconnect structure configured to couple the various p-type and n-type doped regions and the other functional features (such as gate electrodes), resulting a functional integrated circuit. In some embodiments, the interconnect structure includes a multi-layer interconnect (MLI) structure and an inter-level dielectric (ILD) integrated with the MLI structure, providing an electrical routing to couple various devices in the substrate202to the input/output power and signals. In some embodiments, the interconnect structure includes various metal lines, contacts and via features (or via plugs). The metal lines provide horizontal electrical routing. The contacts provide vertical connection between the substrate202and metal lines while via features provide vertical connection between metal lines in different metal layers.

Although Al metal gate is used an example for the discussion in the present invention, it is to be understood that the present disclosure can be implemented in an IC structure including a MG with any other kind of suitable metal materials having a corresponding oxide layer formed on the surface of the MG. The acid solution222used at step106and/or the reducing agent226used at step110may be chosen to effectively remove the corresponding oxide layer without damaging the MG or affecting the pattern profile.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4solution.

In some embodiments, the MG includes aluminum (Al), and the first oxide layer includes aluminum oxide (Al2O3). The thickness of the first oxide layer is in a range from about 40 Å to about 90 Å. The H3PO4solution includes H3PO4dissolved in de-ionized water with a concentration in a range from about 5% to about 25%. The Al2O3is removed by the H3PO4solution using a reaction: Al2O3+2H2PO4−+2H+→2AlPO4+3H2O.

In some embodiments, the method further includes transferring the IC structure to a deposition tool. The surface of the MG is oxidized to form a second oxide layer during the transfer. The method also includes baking the IC structure under vacuum at a temperature in a range from about 50° C. to about 500° C.; and reducing the second oxide layer to a metal included in the MG using a reducing agent. In some embodiments, the MG includes aluminum (Al), and the first oxide layer and the second oxide layer include Al2O3. In some embodiments, the thickness of the second oxide layer is in a range from about 10 Å to about 30 Å. In some embodiments, the method further includes performing an Ar sputtering process to expand an upper portion of the trench.

In some embodiments, reducing the second oxide layer includes using a nitrogen/hydrogen (N2/H2) plasma. The Al2O3is reduced to Al by a reaction Al2O3+3N2/H2→2Al+3H2O. In some embodiments, a flow rate of the H2is in a range from about 100 sccm to about 500 sccm, and a flow rate of the N2is in a range from about 1000 sccm to about 4000 sccm. In some embodiments, the reducing the second oxide layer is conducted in a pressure range from about 10 mTorr to about 3000 mTorr. In some embodiments, the reducing the second oxide layer includes using a power of the N2/H2plasma in a range from about 100 W to about 2000 W.

In some embodiments, the method further includes forming a barrier layer conformed to a bottom and walls of the trench; depositing a metal layer on the barrier layer to fill the trench; and performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench. The contact metal and the dielectric layer are coplanar after the CMP process.

The present disclosure also provides a method for forming an integrated circuit (IC) structure. The method comprises providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method also includes etching the ESL and the dielectric layer to form a trench to expose a surface of the MG; cleaning the surface of the MG using a H3PO4solution; cleaning the surface of the MG using a nitrogen/hydrogen (N2/H2) plasma; forming a barrier layer conformed to a bottom and walls of the trench; depositing a metal layer on the barrier layer to fill the trench; and performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench. The contact metal and the dielectric layer re coplanar after the CMP process.

In some embodiments, after cleaning the surface of the MG using the N2/H2plasma, the method further comprises performing an Ar sputtering process to expand an upper portion of the trench. In some embodiments, after cleaning the surface of the MG using a H3PO4solution, the method further comprises rinsing the IC structure using de-ionized water; and spin drying the IC structure.

The present disclosure also discloses a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method also includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method also includes removing the first oxide layer using a H3PO4solution; transferring the IC structure to a deposition tool. The surface of the MG is oxidized to form a second oxide layer during the transfer. The method further includes baking the IC structure in the deposition tool at a temperature in a range from about 50° C. to about 500° C.; reducing the second oxide layer to a metal included in the MG using a nitrogen/hydrogen (N2/H2) plasma in the deposition tool; performing an Ar sputtering process to expand an upper portion of the trench in the deposition tool; forming a barrier layer conformed to a bottom and walls of the trench in the deposition tool; depositing a metal layer on the barrier layer to fill the trench in the deposition tool; and performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench. The contact metal and the dielectric layer are coplanar after the CMP process. In some embodiments, the MG includes aluminum (Al), and the first oxide layer and the second oxide layer include Al2O3.