Semiconductor device having improved backing conductive layers

In a semiconductor device including at least two parallel conductive layers electrically isolated from each other and at least two parallel backing conductive layers opposing the two parallel conductive layers and electrically connected thereto via contact holes, a thickness of an insulating layer beneath one of the backing conductive layers is different from a thickness of an insulating layer beneath other adjacent backing conductive layers.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a semiconductor device having a plurality 
of parallel conductive layers, such as word lines, and a plurality of 
backing conductive layers for substantially reducing the resistance of the 
conductive layers. 
2. Description of the Related Art 
In a prior art semiconductor device such as a prior art semiconductor 
memory device, where a plurality of parallel conductive layers, such as 
word lines, are provided, as the integration has advanced so that the 
conductive layers are fine structured, the resistance of the conductive 
layers becomes large. In order to reduce the resistance of the conductive 
layers, backing conductive layers are provided in parallel with the 
conductive layers, and are electrically connected to the conductive layers 
via contact holes at an insulating layer therebetween. 
In the above-mentioned prior art semiconductor device, however, since the 
backing conductive layers are wider at the contact holes, it is impossible 
to reduce the pitch of the backing conductive layers, and as a result, it 
is impossible to reduce the pitch of the conductive layers. This will be 
explained later in detail. 
SUMMARY OF THE INVENTION 
It is, therefore, an object of the present invention to provide a 
highly-integrated semiconductor device where the pitch of parallel 
conductive layers parallelly connected to backing conductive layers is 
reduced. 
According to the present invention, in a semiconductor device including at 
least two parallel conductive layers electrically isolated from each other 
and at least two parallel backing conductive layers opposing the two 
parallel conductive layers and electrically connected thereto via contact 
holes, a thickness of an insulating layer beneath one of the backing 
conductive layers is different from a thickness of an insulating layer 
beneath other adjacent backing conductive layers. Since the height of the 
first backing conductive layer is different from that of the second 
backing conductive layer, it is possible to reduce the pitch of the 
backing conductive layers, and accordingly, it is possible to reduce the 
pitch of the conductive layers.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Before the description of the preferred embodiment, a prior art 
semiconductor device will be explained with reference to FIGS. 1 and 2. 
In FIG. 1 which illustrates a prior art semiconductor device and in FIG. 2 
which is a cross-sectional view taken along the line A--A of FIG. 1, 
conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4 which, in this 
case, serve as word lines, are formed on an insulating layer and a 
semiconductor substrate (not shown). The conductive layers WL.sub.1, 
WL.sub.2, WL.sub.3 and WL.sub.4 are made of polycrystalline silicon, for 
example. Formed on the conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and 
WL.sub.4 is an insulating layer 1 made of silicon oxide, for example. 
Then, contact holes C.sub.1, C.sub.2, C.sub.3 and C.sub.4 are formed in 
the insulating layer 1. Also, backing conductive layers BC.sub.1, 
BC.sub.2, BC.sub.3 and BC.sub.4 made of aluminium, for example, are formed 
on the insulating layers 1, and the backing conductive layers BC.sub.1, 
BC.sub.2, BC.sub.3 and BC.sub.4 are electrically connected to the 
conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4, respectively, 
via the contact holes C.sub.1, C.sub.2, C.sub. 3 and C.sub.4. Further, 
formed on the backing conductive layers BC.sub.1, BC.sub.2, BC.sub.3 and 
BC.sub.4 is a cap layer 2 made of silicon oxide. 
Thus, the backing conductive layers BC.sub.1, BC.sub.2, BC.sub.3 and 
BC.sub.4 are provided in parallel with the conductive layers WL.sub.1, 
WL.sub.2, WL.sub.3 and WL.sub.4, respectively, and the backing conductive 
layers BC.sub.1, BC.sub.2, BC.sub.3 and BC.sub.4 are electrically 
connected to the conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and 
WL.sub.4 via the contact holes C.sub.1, C.sub.2, C.sub.3 and C.sub.4 which 
are provided at regular intervals. Therefore, the resistance of the 
conductive layers is substantially reduced. 
In the semiconductor device of FIGS. 1 and 2, however, since the spacing 
and width of the backing conductive layers BC.sub.1, BC.sub.2, BC.sub.3 
and BC.sub.4 are both larger than those of the conductive layers WL.sub.1, 
WL.sub.2, WL.sub.3 and WL.sub.4, the spacing and width of the conductive 
layers WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4 are determined by those 
of the backing conductive layers BC.sub.1, BC.sub.2, BC.sub.3 and 
BC.sub.4. That is, the pitch of the conductive layers WL.sub.1, WL.sub.2, 
WL.sub.3 and WL.sub.4 is determined by 
EQU (W.sub.1 +W.sub.2)/2+d 
where W.sub.1 is a minimum width of the backing conductive layers BC.sub.1, 
BC.sub.2, BC.sub.3 and BC.sub.4 ; 
W.sub.2 is a width of the backing conductive layers BC.sub.1, BC.sub.2, 
BC.sub.3 and BC.sub.4 at the contact holes C.sub.1, C.sub.2, C.sub.3 and 
C.sub.4 ; and 
d is a minimum spacing between the backing conductive layers BC.sub.1, 
BC.sub.2, BC.sub.3 and BC.sub.4 . Particularly, the width W.sub.1 of the 
backing conductive layer BC.sub.1, BC.sub.2, BC.sub.3 and BC.sub.4 at the 
contact holes C.sub.1, C.sub.2, C.sub.3 and C.sub.4 are very large. 
Therefore, it is impossible to reduce the pitch of the conductive layers 
WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4. 
In FIG. 3, which illustrates an embodiment of the present invention and in 
FIGS. 4 and 5 which are cross-sectional views taken along the line B--B 
and the line C--C, respectively, of FIG. 3, an insulating layer 1' made of 
silicon oxide, for example, is added to the elements of FIGS. 1 and 2. 
That is, the backing conductive layers BC.sub.1 and BC.sub.3 are formed on 
the insulating layer 1, as shown in FIG. 4 while the backing conductive 
layers BC.sub.2 and BC.sub.4 are formed on the insulating layer 1' as 
shown in FIG. 5. Thus, backing conductive layers BC.sub.1 and BC.sub.3 are 
separated from conductive layers WL.sub.1 and WL.sub.3 by a portion of 
insulating layer 1 having a height h.sub.1, as shown in FIG. 4, and 
backing conductive layers BC.sub.2 and BC.sub.4 are separated from 
conductive layers WL.sub.2 and WL.sub.4 by a portion of insulating layers 
1 and 1' having a height h.sub.2, as shown in FIG. 5. As illustrated in 
FIGS. 4 and 5, height h.sub.1 is less than height h.sub.2. 
Since the height of one of the backing conductive layers, such as BC.sub.1, 
is different from that of its adjacent conductive layer, such as BC.sub.2, 
even if the spacing d therebetween is 0, a short-circuit may not be 
generated. That is, the spacing and width of the backing conductive layers 
BC.sub.1, BC.sub.2, BC.sub.3 and BC.sub.4 never affect those of the 
conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4. Therefore, 
the pitch of the conductive layers WL.sub.1, WL.sub.2, WL.sub.3 and 
WL.sub.4 can be determined by the spacing and width thereof, per se, 
without consideration of the spacing and width of the backing conductive 
layers BC.sub.1, BC.sub.2, BC.sub.3 and BC.sub.4. 
A semiconductor device according to the invention may comprise a number of 
conductive layers and a number of backing conductive layers according to 
the following formula: 
(1) 2N (N-1, 2, . . .) conductive layers; 
(2) N parallel first backing conductive layers, each opposing a 2i (i=1, 2, 
. . . , N/2)-th conductive layer and being electrically connected to the 
2i-th conductive layer through contact holes; and 
(3) N parallel second backing conductive layers, each opposing a (2i-1) 
(i=1, 2, . . . , N/2)-th conductive layer and being electrically connected 
to the (2i-1)-th conductive layer through contact holes. 
In the above-described embodiment, although the two distinct insulating 
layers 1 and 1' are provided, it is possible to provide only one 
insulating layer and perform an etching operation thereupon so as to 
create two portions having different thicknesses. 
As explained hereinbefore, according to the present invention, since the 
pitch of parallel conductive layers connected to backing conductive layers 
is determined without consideration of the pitch of the backing conductive 
layers, a semiconductor device including such parallel conductive layers 
can be highly integrated.