Data driven information processor

A data driven information processor includes an operation processor unit for prestoring a data flow program and carrying out processing, and a storage microprocessor unit having a plurality of data memories including external data memories for inputting/outputting data to and from the operation processor unit. In the storage microprocessor unit, a plurality of data memories are accessed, in parallel, based on the content of an applied data packet for a single access time. The result of each access is operated in accordance with the content of the data packet. Finally, the subsequent program is read from a data flow program prestored in the storage microprocessor unit so that access to the plurality of data memories and processing of a result of the access continue in the storage microprocessor unit. Thus, in the information processor, parallel access to a plurality of data memories can be achieved by program control independent of program control by the operation processor unit.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a data driven information processor, and 
more particularly, to a data driven information processor having a data 
driven type information processing unit and a memory to be accessed upon 
execution of information processing by the processing unit, and capable of 
improving efficiency of access to the memory. 
2. Description of the Background Art 
A data driven information processor is one type of non-von-Neumann computer 
having no concept of sequential execution of instructions by a program 
counter. Such a data driven information processor employs architecture 
based on parallel processing of instructions. In the data driven 
information processor, an execution of an instruction is enabled upon a 
collection of data to be operated, and a plurality of instructions are 
simultaneously driven by data, so that programs are executed in parallel 
in accordance with a natural flow of the data. As a result, time required 
for operation will be drastically reduced compared to the case of 
von-Neumann computers. In order to further improve a processing speed of 
the data driven information processor, the speeding up of access to a 
memory (hereinafter referred to as a data memory) for storing data to be 
referred to or updated upon execution of processing is desired. 
FIG. 13 is a diagram showing the connection of a conventional data driven 
processor and an external data memory, and FIG. 14 is a diagram showing 
connection of a plurality of conventional data driven processors and 
external data memories. 
FIG. 15 is a diagram showing a structure of a memory interface for a 
conventional data driven processor. 
In conventional data driven processors, a multi-processor system consisting 
of a plurality of processors and a plurality of memory interfaces is 
proposed in an article entitled "An Evaluation of Parallel-Processing in 
the Dynamic Data Driven Processor", pp. 9-18 issued on Nov. 12, 1991 in 
the Micro Computer Architecture Symposium sponsored by Information 
Processing Society of Japan. 
In the conventional processor proposed therein, although a data memory 
(hereinafter referred to as an internal data memory) incorporated into the 
processor or a data memory (hereinafter referred to as an external data 
memory) located external to the processor is connected to a single memory 
interface, data cannot be read/written from and to both memories 
simultaneously. In other words, since the conventional data driven 
processor allows an access to only one data memory for one memory 
interface, only one data can be accessed for a single access time (see 
FIG. 13). Accordingly, a double access time is required to access data in 
both internal and external data memories, so that the speeding up of 
processing has been prevented. 
In addition, in the conventional data driven processor, although an 
addresses of a data memory is modified by address modification, addresses 
in a plurality of different data memories cannot be modified using this 
address modification. Therefore, in order to access first and second data 
memories, first and second memory interfaces for respectively accessing to 
the first and the second memories are required as shown in FIG. 14, 
thereby causing an increase in cost and preventing a reduction in device 
size. 
Furthermore, in the conventional data driven information processor, an 
internal data memory and a cache memory are not provided separately, and 
therefore, there has been no facility which accesses data in each of the 
internal data memory and the cache memory simultaneously. 
In addition, the conventional data driven processor is not provided with a 
function to store a program in a memory interface, and therefore, a data 
memory cannot be accessed without processing by a host processor (see FIG. 
15). Accordingly, frequent accesses to the data memory cause an increase 
in load on the host processor, so that speeding up of the whole processing 
has been prevented. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a data driven 
information processor having a plurality of a data memories, which is 
capable of increasing processing speed, including access to each data 
memory. 
In order to achieve this object, the data driven information processor in 
accordance with the present invention includes a processing unit for 
receiving an applied data packet, processing the content of the received 
data packet, and outputting a data packet which stores a result of the 
processing and subsequent program data of a first prestored data flow 
program; and a memory control unit having a plurality of data memories for 
storing data to be referred to or updated upon execution of processing in 
the information processor for inputting/outputting data to and from the 
processing unit. 
The memory control unit further includes an input unit for receiving, 
processing and outputting an applied data packet; an access unit for 
receiving a data packet output from the input unit, accessing at least one 
of the plurality of data memories in parallel based on the content of the 
received data packet, and outputting the received data packet which stores 
a result of the access upon each access to each data memory; an operation 
unit for receiving a data packet output from the access unit, operating 
the result of the access in the received data packet in accordance with 
the content of the received data packet, storing a result of the operation 
in the received data packet, and outputting the received data packet; and 
a program storage unit for receiving a data packet output from the 
operation unit and outputting a data packet which stores both a result of 
the operation in the received data packet and subsequent program data in a 
second prestored data flow program. 
According to the above described data driven information processor, since a 
plurality of data memories can be accessed in parallel by the access unit 
of the memory control unit in a single access time, improvement in a speed 
of the entire processing, including access to each data memory, of the 
information processor can be achieved. The memory control unit stores the 
second data flow program in the program storage unit, so that program 
control for access to a data memory can be achieved independently of 
control of the processing unit. Thus, the load on the processing unit is 
reduced, resulting in a higher processing speed of the processing unit. 
Since the input unit in the memory control unit of the above described data 
driven information processor includes an address operation unit for 
calculating an address for parallel access by the access unit based on the 
content of a data packet and on address modification data, address 
modification for a plurality of data memories can be carried out. 
If the plurality of data memories include an external data memory and one 
or more internal data memories, each having a different access speed, 
parallel access to the external and the internal data memories as well as 
parallel access to a plurality of internal data memories each having a 
different access speed can be performed. 
The foregoing and other objects, features, aspects and advantages of the 
present invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
An embodiment of the present invention will now be described in conjunction 
with the accompanying drawings. 
In the following description, a data cache indicates a memory with smaller 
capacity than internal and external data memories, which can be accessed 
at a higher speed than those memories. Further, an internal data memory 
indicates a memory with smaller capacity than an external data memory, 
which can be accessed at a higher speed than the external data memory. 
FIG. 1 schematically shows a structure of a data driven information 
processor in accordance with an embodiment of the present invention. 
FIGS. 2A and 2B show a format of an I/O packet of the data driven 
information processor of FIG. 1. 
Data to be processed in the data driven information processor of FIG. 1 has 
a data packet structure shown in FIGS. 2A and 2B. A packet for access to a 
video memory, which will be described later, is formed of two words each 
having 36 bits as shown in FIGS. 2A and 2B, and a packet other than that 
packet is formed of two words each having 32 bits without a generation 
offset OFF in FIGS. 2A and 2B. A data packet stores instruction 
information 100, destination information 101, generation information 102 
and an operand 103. 
Instruction information 100 includes an operation code OPC, and destination 
information 101 includes a node number ND# and a processor number PE#. 
Generation information 102 is information allotted when the packet stores 
time series data for video signal processing or the like. Generation 
information 102 is allotted to a data packet in accordance with the 
input-time order to the information processor. Generation information 102 
is used as an address for access to a video memory as will be described 
below, and includes a 3-bit field address fd, an 11-bit line address in 
and a 10-bit pixel address px. Operand 103 includes operand data DATA 
which is processed with operation code OPC. 
The data driven information processor of FIG. 1 includes a storage 
microprocessor unit 1, an I/O control unit 2 having input ports IA and IB 
and output ports OA and OB for controlling input/output of a data packet 
to and from the processor, and an operation processor unit 3, and 
externally connects with external data memories 4A and 4B. 
I/O control unit 2 receives a data packet externally, and outputs the data 
packet to storage microprocessor unit 1 or operation processor unit 3. 
Storage microprocessor unit 1 performs reading/writing from and to each 
type of data memory and operation processing accompanying the 
reading/writing, and is able to access an internal data memory and an 
external data memory (4A, 4B) which will be described below. Operation 
processor unit 3 is similar to that in the conventional data driven 
processor. 
A data packet input through I/O control unit 2 to the information processor 
is processed in accordance with a data flow program stored in each of 
storage microprocessor unit 1 and operation processor unit 3. In this 
case, the data packet may be output from storage microprocessor unit 1 to 
operation processor unit 3, or may be output from operation processor unit 
3 to storage microprocessor unit 1, depending on the processing of the 
program. The data packet which has been processed within the information 
processor is output to the outside of the information processor from I/O 
control unit 2. 
FIG. 3 shows a structure of storage microprocessor unit 1 of FIG. 1. 
Storage microprocessor unit 1 of FIG. 3 includes an input processing unit 
10 for processing and outputting a data packet received from I/O control 
unit 2 or operation processor unit 3; an internal memory control unit 14 
for controlling access to internal data memories 18A and 18B as well as 
data caches 19A and 19B; an external memory control unit 15 for 
controlling access to external data memories 4A and 4B; an operation 
processing unit 16; and a program storage unit 17 for prestoring a data 
flow program mainly for access to a data memory and processing of the 
access result. 
Input processing unit 10 includes an address modifier constant unit 11, an 
address modifier operation unit 12 and a branch unit 13. An external data 
memory, an internal data memory and a data cache are prepared to make one 
set as shown in the figure, since memories in each set are accessed 
(interleaved) alternately on a one-by-one basis so as to achieve 
high-speed access to a memory. 
Address modifier constant unit 11 includes a memory (not shown) for 
prestoring at least one constant value for address modification. Upon 
receiving a data packet, constant unit 11 reads a constant value from the 
memory based on the content of the received data packet to store the 
constant value in the received data packet as a generation offset OFF, and 
outputs the packet. 
Based on an operation code OPC of the data packet, address modifier 
operation unit 12 calculates an address for accessing each memory from a 
constant value of generation offset OFF and an address value (generation 
information 102) in the data packet applied from constant unit 11; stores 
the address resulting from the calculation in the data packet as 
generation information 102; and outputs the data packet to branch unit 13. 
Based on instruction information 100 of the data packet, branch unit 13 
outputs the data packet to internal memory control unit 14 if it 
determines that an address to be accessed is an address of an internal 
memory (memories 18A and 18B or data caches 19A and 19B), outputs the data 
packet to external memory control unit 15 if it determines that an address 
to be accessed is an address of external data memories 4A and 4B, and 
outputs the data packet in parallel to internal memory control unit 14 and 
external memory control unit 15 if it determines that an address to be 
accessed is both an address of internal memories (memories 18A and 18B, or 
data caches 19A and 19B) and an address of external data memories 4A and 
4B. 
Then, the data packet which stores, as an operand 103, the result of access 
to a corresponding data memory through each control unit is output to 
operation processing unit 16. Operation processing unit 16 operates 
corresponding operand 103 based on an operation code OPC of the data 
packet, stores the data of the result of the operation in the data packet 
as operand 103 and outputs the packet to program storage unit 17. 
Operation processing unit 16 only performs an operation of data obtained 
by access to a memory, and an operation other than that is carried out in 
operation processor unit 3. 
Program storage unit 17 reads the subsequent program data from the 
prestored data flow program in accordance with the content of the data 
packet received from operation processing unit 16, and stores the program 
data in the data packet. Then, program storage unit 17 outputs the data 
packet to address modifier constant unit 11 if destination information 101 
in the received data packet indicates the inside of storage microprocessor 
unit 1, and outputs the data packet to operation processor unit 3 external 
to storage microprocessor unit 1 if destination information 101 in the 
received data packet indicates operation processor unit 3. If destination 
information 101 indicates the outside of the data driven information 
processor, the received data packet is output to the outside of the 
information processor through I/O control unit 2. 
FIG. 4 shows a structure of I/O control unit 2 of FIG. 1. In the figure, 
I/O control unit 2 includes router units 20 and 26 for controlling a path 
of a data packet, junction units 21 and 23, an input processing unit 22, a 
branch unit 25 and an output processing unit 24. 
Router unit 20 receives a data packet applied from the outside of the 
information processor through an input port IA or IB and identifies 
destination information 101 thereof so as to output the data packet to 
router unit 26 if the destination information 101 indicates the outside of 
the information processor, and to output the data packet to junction unit 
21 if the destination information 101 indicates the inside of the 
information processor. Junction unit 23 sequentially receives data packets 
applied from storage microprocessor unit 1 and operation processor unit 3 
and outputs a data packet to output processing unit 24. 
Output processing unit 24 converts a data packet received from junction 
unit 23 from a data packet having a data format of the inside of the 
information processor into a data packet having a data format of the 
outside of the information processor to output the resultant data packet 
to branch unit 25. If destination information 101 of the data packet 
received from output processing unit 24 indicates the outside of the 
information processor, branch unit 25 outputs the received data packet to 
router unit 26, and if the destination information 101 indicates the 
inside of the information processor, branch unit 25 outputs the received 
data packet to junction unit 21. 
Router unit 26 outputs the data packet received from router unit 20 or 
branch unit 25 to the outside of the information processor through either 
output port OA or OB, based on destination information 101 of the received 
data packet. Junction unit 21 sequentially receives data packets applied 
from branch unit 25 and router unit 20 to output a data packet to input 
processing unit 22. Input processing unit 22 converts the data packet 
received from junction unit 21 from a packet having a data format of the 
outside of the information processor into a data packet having a data 
format of the inside of the information processor, and outputs the 
resultant data packet either storage microprocessor unit 1 or operation 
processor unit 3 based on destination information 101 of the packet. 
FIG. 5 shows a structure of operation processor unit 3 of FIG. 1. In the 
figure, operation processor unit 3 includes junction units 30 and 31, a 
paired data production/constant unit 32, an operation processing unit 33, 
a program storage unit 34 and a branch unit 34. Since the data processing 
in paired data production/constant unit 32, operation processing unit 33 
and program storage unit 34 is described in detail in the above mentioned 
article "An Evaluation of Parallel-Processing in the Dynamic Data Driven 
Processor", a description of which will be given briefly herein. 
Junction unit 30 sequentially receives data packets applied from I/O 
control unit 2 and branch unit 33 and outputs a data packet to junction 
unit 31. Junction unit 31 sequentially receives data packets applied from 
junction unit 30 and storage microprocessor unit 1 and outputs a data 
packet to paired data production/constant unit 32. 
Paired data production/constant unit 32 sequentially receives data packets 
applied from junction unit 31, and produces a pair of operand data DATA 
which can be operated, or produces, if constant data corresponding to the 
received data packet is prestored in the constant unit, a pair of operant 
data DATA of the received data packet and the constant data. The data pair 
produced is stored in the received data packet as operand data DATA, and 
the data packet is output to operation processing unit 33. 
Operation processing unit 33 receives the data packet output from paired 
data production/constant unit 32, processes a data pair in the received 
packet in accordance with instruction information 100 in the received 
packet, and outputs the data packet which stores data of the result as 
operand data DATA to program storage unit 34. 
Program storage unit 34 prestores a data flow program. When program storage 
unit 34 receives the data packet applied from operation processing unit 
33, it reads the subsequent program data from the program based on a node 
number ND# and generation information 102 of the received data packet, 
stores the program data in the received packet, and outputs the packet to 
branch unit 35. 
When branch unit 35 receives the data packet applied from program storage 
unit 34, it outputs the data packet to either junction unit 30, storage 
microprocessor unit 1 or I/O control unit 2 based on destination 
information 101 thereof. 
Storage microprocessor unit 1 has program storage unit 17 as shown in FIG. 
3, so that control of a program for access to a data memory in the 
information processor can be performed independently of control of a 
program stored in program storage unit 34 of operation processor unit 3. 
Accordingly, since operation processing by the operation processor unit 3 
and access to a data memory by the microprocessor unit 1 can be carried 
out in parallel, load on the operation processor unit 3 is reduced and 
processing speed in the information processor is improved compared to a 
conventional example. 
Storage microprocessor unit 1 includes input processing unit 10, internal 
memory control unit 14 and external memory control unit 15, so that 
parallel access to data memories 18A and 18B, data caches 19A and 19B and 
external data memories 4A and 4B can be performed for a single access 
time. This access to a memory will now be described in detail using, as an 
example, image data processing which particularly requires high speed 
processing and handles a large amount of data, assuming that internal and 
external data memories are video memories. 
FIG. 6 is a diagram showing a structure of image data in accordance with an 
embodiment of the present invention. As shown in the figure, image data 
consists of a plurality of frames (fields), each frame is constituted by a 
plurality of picture element data arranged two-dimentionally (in pixel and 
line directions), and each picture element data in image data is 
identified (addressed) uniquely on a data memory by an address (field, 
pixel direction, line direction). 
Characteristic processing of image data processing includes filtering 
processing. In the filtering processing, a comparison between data 
adjacent to each other in the pixel direction, a comparison between data 
adjacent to each other in the line direction, and the comparison between 
fields adjacent to each other are carried out for picture element data. In 
this case, information on picture element data in the pixel direction of 
image data is stored in data caches 19A and 19B, information on picture 
element data in the line direction of image data is stored in internal 
data memories 18A and 18B, and information on a field of image data is 
stored in external data memories 4A and 4B. It is herein noted that a 
pixel address px is used to identify picture element data in the pixel 
direction of a data memory, a line address ln is used to identify picture 
element data in the line direction on a data memory, and a field address 
fd is used to identify picture element data by field. Access to a memory 
in accordance with the present embodiment will now be described with 
reference to FIGS. 7 to 12. 
It is noted that a constant value (16 bits) of FIGS. 7 to 12 is applied as 
a generation offset OFF to address modifier operation unit 12 by address 
modifier constant unit 11 of FIG. 3. Operation of calculating an address 
to be accessed from an address (24 bits) upon execution indicated by 
generation information 102 and from a constant value (16 bits), storing 
the calculated address in a data packet as generation information 102 and 
outputting the data packet is carried out by address modifier operation 
unit 12. 
FIGS. 7A and 7B are diagrams illustrating access to an internal data memory 
and an external data memory in accordance with an embodiment of the 
present invention. 
FIG. 7A shows an example of access to internal data memory 18A or 18B. An 
IVM (Internal Video Memory) instruction is set in an operation code OPC 
for carrying out this access. The whole area of internal data memory 18A 
or 18B can be accessed in accordance with the IVM instruction. 
In addition, FIG. 7A shows an example of access to external data memory 4A 
or 4B. An EVM (External Video Memory) instruction is set in an operation 
code OPC for carrying out this access. The whole area of external data 
memory 4A or 4B can be accessed in accordance with the EVM instruction. 
Although the same address for access is used in both the IVM instruction 
and the EVM instruction, the internal data memory and the external data 
memory are provided separately as shown in FIG. 3, so that access thereto 
is carried out separately. 
FIG. 7B shows a relationship between an address and an address modification 
value (hereinafter referred to simply as a constant value) of address 
modifier constant unit 11. An address upon execution is indicated by a 
field address fd, a line address in and a pixel address px in a data 
memory. Picture element data in the data memory can be accessed by 
generation information 102. 
An address (fd, ln, px) upon execution is converted into an address of 
internal data memory 18A or 18B and external data memory 4A or 4B in 
address modifier operation unit 12, using a constant value (a field offset 
value .DELTA.fd, a line offset value .DELTA.ln, a pixel offset value 
.DELTA.px) applied by address modifier constant unit 11 of FIG. 3 as an 
offset value. Then, each data memory is accessed through internal memory 
control unit 14 or external memory control unit 15 based on the address 
(fd+.DELTA.fd, ln+.DELTA.ln, px+.DELTA.px) obtained by conversion. 
FIG. 8 is a diagram illustrating simultaneous access to an internal data 
memory and an external data memory in accordance with an embodiment of the 
present invention. A CPX (ALU for Complex operation) instruction is set in 
an operation code OPC for carrying out this access. Since only a pixel 
offset value .DELTA.px of the constant value is valid in the CPX 
instruction, data cache 19A or 19B is accessed. 
FIGS. 9A and 9B are diagrams illustrating access to addresses of the same 
line of an internal data memory and a data cache in accordance with an 
embodiment of the present invention. An MDC/CL (Multiple access with Data 
Cache in Common Line) instruction is set in an operation code OPC for 
carrying out this access. Since a pixel offset value .DELTA.DmPx of an 
internal data memory and a pixel offset value .DELTA.DcPx of a data cache 
are included in a constant value in the MDC/CM instruction, separate pixel 
addresses px for internal data memory 18A or 18B and data cache 19A or 19B 
are accessed. In this case, an offset value .DELTA.ln for a line address 
ln is not included in the constant value. 
FIGS. 10A and 10B are diagrams illustrating access to addresses of the same 
pixel of an internal data memory and a data cache in accordance with an 
embodiment of the present invention. An MDC/CP (Multiple access with a 
Data Cache in Common Pixel) instruction is set in an operation code OPC 
for carrying out this access. Since only an offset value .DELTA.DmLx for a 
line address ln of internal data memory 18A or 18B is included in a 
constant value in the MDC/CP instruction, a line address ln of internal 
data memory 18A or 18B is accessed. In this case, a pixel offset value 
.DELTA.Px for a pixel address px is common to internal data memory 18A or 
18B and data cache 19A or 19B. 
FIGS. 11A and 11B are diagrams illustrating access to addresses of the same 
line of an external data memory and an internal data memory in accordance 
with an embodiment of the present invention. 
An MVM/CL (Multiple access with Video Memory in Common Line) instruction is 
set in an operation code OPC for carrying out this access. Since offset 
values .DELTA.DmPx and .DELTA.VmPx for pixel addresses of internal data 
memory 18A or 18B and external data memory 4A or 4B are included in a 
constant value in the MVM/CL instruction, separate pixel addresses px of 
internal data memory 18A or 18B and external data memory 4A or 4B are 
accessed. In this case, an offset value .DELTA.ln for a line address ln is 
common to internal data memory 18A or 18B and external data memory 4A or 
4B. 
FIGS. 12A and 12B are diagrams illustrating access to address the same 
pixel of an external data memory and an internal data memory in accordance 
with an embodiment of the present invention. An MVM/CP (Multiple access 
with Video Memory in Common Pixel) instruction is set in an operation code 
OPC for carrying out this access. Since offset values .DELTA.Dmln and 
.DELTA.Vmln for line addresses in of internal data memory 18A or 18B and 
external data memory 4A or 4B are included in a constant value in the 
MVM/CP instruction, separate line addresses of internal data memory 18A or 
18B and external data memory 4A or 4B are accessed. In this case, an 
offset value .DELTA.px for a pixel address px is common to internal data 
memory 18A or 18B and external data memory 4A or 4B. 
Since a unique program is stored in each of storage microprocessor unit 1 
and operation processor unit 3 as shown in FIGS. 1, 3 and 5, parallel 
access to memories shown in FIGS. 7 to 12 can be carried out without 
processing of a program by operation processor unit 3 of a host processor. 
In addition, a plurality of memory interfaces have been provided 
conventionally for access to a plurality of data memories, while parallel 
access to a plurality of different data memories can be carried out for a 
single access time by storage microprocessor unit 1 which is a single 
memory interface. 
Furthermore, as shown in FIGS. 9 and 10, parallel access to internal data 
memory 18A or 18B and internal data cache 19A or 19B can be carried out 
for a single access time. 
In addition, a plurality of different address modification facilities can 
be provided by address modifier constant unit 11 and address modifier 
operation unit 12, so that parallel access to different addresses of a 
plurality of data memories can be carried out for a single access time. 
Although the present invention has been described and illustrated in 
detail, it is clearly understood that the same is by way of illustration 
and example only and is not to be taken by way of limitation, the spirit 
and scope of the present invention being limited only by the terms of the 
appended claims.