Systems and methods for implementing a synchronous FIFO with registered outputs

Example systems and related methods may relate to a synchronous first-in-first-out (FIFO) data buffer. The synchronous FIFO data buffer may include a counter. The counter may (i) receive a plurality of signals and (ii) output a count of total entries in the FIFO. The FIFO may further include a status generator that may (i) receive the plurality of signals and the count of total entries, and (ii) outputs a status signal. The FIFO may further include a selection generator that may (i) receive the count of total entries, the write signal, and the read signal, and (ii) output a data enable signal and a multiplexor selection signal. The FIFO may further include a scalable N×M flip-flop memory structure. N may be a number of entries in the memory structure and M may be a number of bits using flip-flops.

BACKGROUND

Printing devices have become more complex in design and implementation. In most cases, print jobs are handled using a data buffer. For example, a printing device may receive multiple print jobs and use a data buffer to transfer printing information between multiple modules within the printing device to complete the print jobs. There are multiple types of data buffers, such as first-in, first-out (FIFO) data buffers. Using data buffers, printing systems may be able to determine an efficient order to complete the print jobs.

However, existing data buffers might not provide registered outputs, which may result in reduced power efficiency when different modules of a printing system are attempting to communicate with one another. Thus, a need exists for an efficient system and method of storing data that is scalable and provides registered outputs for use by modules in printing systems.

SUMMARY

In a first aspect, a synchronous FIFO data buffer is provided. The data buffer may include a counter. The counter may receive a plurality of signals, including a system clock signal, a reset signal, a write signal, and read signal. The counter may output a count of total entries in the FIFO. The data buffer may also include a status generator. The status generator may receive the plurality of signals and the count of total entries. The status generator may output a status signal. The data buffer may further include a selection generator. The selection generator may receive the count of total entries, the write signal, and the read signal. The selection generator may output a data enable signal and a multiplexor selection signal. The data buffer may further include a scalable N×M flip-flop memory structure. N may relate to a number of entries in the memory structure, and M may relate to a number of bits using flip-flops. Each entry of the N entries in the memory structure may include an M bit wide multiplexor. The multiplexor may receive the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the memory structure. The multiplexor may output the new write data. Each entry may also include a flip-flop bank. The flip-flop bank may receive the new write data, the data enable signal, and the system clock signal. The flip-flop bank may output a data output comprising information stored in the flip-flop bank.

In a second aspect, a method for implementing a synchronous FIFO data buffer is provided. The method may involve receiving, via a counter, a plurality of signals comprising a system clock signal, a reset signal, a write signal, and a read signal. The method may further involve transmitting, via the counter, a count of total entries in the FIFO. The method may further involve receiving, via a status generator, the plurality of signals and the count of total entries. The method further involves transmitting, via the status generator, a status signal. The method may further involve receiving, via a selection generator, the count of total entries from the counter, the write signal, and the read signal. The method may further involve transmitting, via the selection generator, a data enable signal and a multiplexor selection signal. The method may further involve receiving, via an M bit wide multiplexor within one entry of a scalable N×M flip-flop memory structure, the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the scalable N×M flip-flop memory structure. N may be a number of entries in the scalable N×M flip-flop memory structure, and M may be a number of bits using flip-flops. The method may further involve transmitting, via the M bit wide multiplexor, write data. The method may further involve receiving, via a flip-flop bank within one entry of the scalable N×M flip-flop memory structure, the write data, the data enable signal, and the system clock signal. The method may further involve transmitting, via the flip-flop bank, a data output comprising information stored in the flip-flop bank.

In a third aspect, a tangible, non-transitory computer-readable medium is provided. The tangible, non-transitory computer-readable medium includes program instructions encoded therein. The program instructions, when executed by one or more processors, cause a printing device to perform a method for implementing a synchronous FIFO data buffer. The method may involve receiving, via a counter, a plurality of signals comprising a system clock signal, a reset signal, a write signal, and a read signal. The method may further involve transmitting, via the counter, a count of total entries in the FIFO. The method may further involve receiving, via a status generator, the plurality of signals and the count of total entries. The method further involves transmitting, via the status generator, a status signal. The method may further involve receiving, via a selection generator, the count of total entries from the counter, the write signal, and the read signal. The method may further involve transmitting, via the selection generator, a data enable signal and a multiplexor selection signal. The method may further involve receiving, via an M bit wide multiplexor within one entry of a scalable N×M flip-flop memory structure, the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the scalable N×M flip-flop memory structure. N may be a number of entries in the scalable N×M flip-flop memory structure, and M may be a number of bits using flip-flops. The method may further involve transmitting, via the M bit wide multiplexor, write data. The method may further involve receiving, via a flip-flop bank within one entry of the scalable N×M flip-flop memory structure, the write data, the data enable signal, and the system clock signal. The method may further involve transmitting, via the flip-flop bank, a data output comprising information stored in the flip-flop bank.

DETAILED DESCRIPTION

Data buffers are typically regions of a physical memory storage. Many devices and systems may implement data buffers to temporarily store data while it is being moved from one place to another. One example of a data buffer may include a music playlist. In this example, a user may select multiple songs to be played. The songs may be put in a buffer, or “queue,” and played in the order the user selected the songs for playback. This is an example of a first-in, first-out (FIFO) data buffer.

Printing systems may use FIFO data buffers to handle print jobs submitted by users on a local area network (LAN). For instance, the printing system may receive print jobs faster than it is able to complete the print jobs. In this scenario, the printing system may (i) complete the first print job it receives, (ii) store the additional print jobs in a data buffer (e.g., a temporary place in memory), and after completing the first print job, (iii) retrieve a second print job from the data buffer, and (iv) complete the second print job.

In some circumstances, FIFO data buffers are implemented with an array of storage elements, write/read pointer logic, and a module to generate indications that the FIFO data buffer is full or empty. However, one problem these FIFO data buffers may encounter is that they are difficult to manufacture when a large number of multiplexors are needed when outputting data. Further, these FIFO data buffers might not allow for registered outputs. Thus, it may be beneficial, in some embodiments, to provide a FIFO data buffer that has flip-flop banks that has registered outputs, resulting in more reliable handling of print jobs.

II. System Examples

FIG. 1is a schematic block diagram illustrating a system100, according to an example embodiment. System100includes a computer110. System100may include a printing system, payment software system, or communication system, for example. Other types of computing systems exist and are contemplated.

Computer110may include a processor120and memory130. Computer110may include computing devices configured to receive and process a print job. Computer110may have a processor120and a memory130. For example, computer110may receive multiple requests to print documents and then send the instructions to print the document to a processor120. Processor120may print one of the documents and send the other document to memory130for temporary storage. After printing the document, processor120may retrieve the other document from memory130and then print the other document.

Processor120may be disposed within computer110and may be configured to execute program instructions to handle various tasks (e.g., receiving and processing print jobs). Processor120may include an application specific integrated circuit (“ASIC”), which may be used to transfer data between different modules with either different clock frequencies or between modules with the same clock frequency but with different input and output data rates. Processor120may be configured to retrieve and store the print job in memory130.

Memory130may be associated with an allocation of physical memory. Alternatively or additionally, memory130may be associated with a virtual and/or dynamic memory allocation. A portion of memory130may be configured to operate as FIFO data buffer (hereinafter “FIFO”)140. FIFO140may be a data structure in which the first and/or oldest entry is processed first, while the last and/or newest entry is processed last.

For example, in a printing system, FIFO140may be configured to have a maximum capacity of 10 print jobs. If a user submits six consecutive print jobs, FIFO140may store the first print job in a first entry, the second print job in a second entry, continuing until storing the sixth print job in a sixth entry. Processor120may retrieve the first print job from the first entry and send the first print job for printing. After the print job is completed, processor120may retrieve the second print job from the second entry and send the second print job for printing. This process may continue until all six print jobs are completed.

In another example, computer110may receive three print jobs. The print job may include a document or an image. Computer110may, via processor120, execute program instructions to process the first print job, and store the second and third print jobs in FIFO140of memory130. After processor120processes the first print job, it may retrieve the second print job from FIFO140of memory130. Processor120may then process the second print job. After processor120processes the second print job, processor120may then retrieve and process the third print job.

FIG. 2is a schematic block diagram illustrating an asynchronous FIFO data buffer, according to an example embodiment. System200may represent a communication protocol between two modules via an asynchronous FIFO data buffer. System200may be implemented in hardware or through an ASIC. System200may include FIFO202, module204, and module206.

FIFO202may include storage elements228. The number of storage elements228in FIFO202may be customizable depending on the needs of system200. FIFO202may include a write interface and a read interface. The write interface may be connected to module204, and the read interface may be connected to module206.

Module204may include a component that wants to write data to FIFO202. For example, module204may include processor120fromFIG. 1. Module204communicates to FIFO202's write interface via write data bus208, write signal210, full signal212, write reset signal214, and write clock signal216. Write data bus208may include the data module204wishes to store in FIFO202(e.g., a print job). Write signal210may include an indication that module204is currently writing the data stored in write data bus208into one of storage elements228. Full signal212may include an indication that FIFO202might not have any available storage elements228for which to write data. Write reset signal214may include an indication that module204wishes to initialize or re-initialize the write logic of FIFO202. Write clock signal216may include the clock signal from module204.

Module206may include a component is configured to read data from FIFO202. For example, module206may include processor120fromFIG. 1, or another hardware component configured to retrieve data from FIFO202. In some circumstances, module204and module206may be the same hardware component. Module206communicates to FIFO202's read interface via read data bus218, read signal220, empty signal222, read reset signal224, and read clock signal226. Read data bus218may include the data module206wishes to read and/or retrieve from FIFO202(e.g., a print job). Read signal220may include an indication that module206is currently reading the data stored in read data bus218from one of storage elements228. Empty signal222may include an indication that FIFO202might not have any data stored in storage elements228from which to read data. Read reset signal224may include an indication that module206wishes to initialize or re-initialize the read logic of FIFO202. Read clock signal226may include the clock signal from module206.

In operation, module204(e.g., processor120, other hardware, etc.) may receive a print job. Module204may divide the print job into multiple data segments for storage in FIFO202. Module204may check full signal212to determine whether FIFO202has sufficient memory to store the data segments. Once module204determines full signal212is deasserted, indicating FIFO202is not full, module204may assert write signal210and begin sending data segments via write data bus208. To accomplish this, module204may point write data bus208to the location of the data packets within FIFO202, then assert write signal210for the duration of one write clock signal216(e.g., from one rising edge of the clock signal to another rising edge of the clock signal). The real-time duration of one write clock signal216may depend on the processing capabilities of system200. Module204fills one of storage elements228during one write clock signal.

After module204has stored all of the data segments into FIFO204, module206may determine it wants to retrieve the data segments from FIFO202to print the information stored in the data segments. To retrieve the data segments from FIFO202, module206may check empty signal222to determine that FIFO202has data stored to retrieve (e.g., not empty). Once module206determines empty signal222is deasserted, indicating FIFO202is not empty, module206may assert read signal220and begin reading the data segments via read data bus218. To accomplish this, module206may point read data bus218to the location of the data segments within FIFO202and then assert read signal220for the duration of one read clock signal226. The real-time duration of one read clock signal226may depend on the processing capabilities of system200. The real-time duration of one write clock signal216and one read clock signal226may be different, which makes FIFO202an example of an asynchronous FIFO data buffer. After module206has read all of the data stored in FIFO202, FIFO202may assert empty signal222indicating FIFO202no longer has data stored in storage elements228.

FIG. 3is a schematic block diagram illustrating a synchronous FIFO data buffer300, according to an example embodiment. In a synchronous FIFO data buffer, all modules are controlled by the same clock signal.

Synchronous FIFO data buffer300may include storage elements302, write pointer module314, read pointer module316, and status generation module318.

Storage elements302may implemented in the form of static random access memory (“SRAM”) or an array of flip-flops. Typically, synchronous FIFO data buffers with a depth greater than 32 and a width greater than 256 may be implemented using SRAM. Similarly, synchronous FIFO data buffers with a smaller depth and/or width may be implemented with an array of flip-flops. Synchronous FIFO data buffer300inFIG. 3is implemented with an array of flip-flops. Storage elements302may include storage elements306,308,310, and312.

Write pointer module314may keep track of the location where the next data entry may reside in storage elements302. To accomplish this, write pointer module314asserts the appropriate write enable signal corresponding to one of storage elements306,308,310, and312. The write pointer is incremented following an assertion of the write signal upon the rising edge of the clock signal. For example, when synchronous FIFO data buffer300is empty, write pointer module314may assert the write enable signal that corresponds to storage element306, indicating the next write data should be stored in storage element306. On the next rising edge of the clock signal, the data in the write data bus is stored in storage element306. After the write data bus is stored in storage element306, write pointer module314may deassert the write enable signal corresponding to storage element306and assert the write enable signal corresponding to storage element308. The storage location of write pointer module314is tracked using a counter that has a value from 0 to N−1, with N being the number of storage elements in storage elements302. The counter may implemented as the write pointer or read pointer. The counter may rollover once the maximum count has been reached. For example, if the counter has two bits, the counter may increment by one from zero to three and then rollover back to zero. InFIG. 3, N is 4 because there are four storage elements (e.g., storage elements306,308,310, and312).

In operation, when data is to be stored in synchronous FIFO data buffer300, the write signal may be asserted by a module connected to synchronous FIFO data buffer300(not shown inFIG. 3). When the write enable signal is asserted for storage element306, the data contained in the write data bus may be stored in storage element306on the rising edge of the clock signal. After the data is stored in storage element306, the counter for write pointer module314may be incremented, the write enable signal corresponding to storage element may be deasserted, and the write enable signal for storage element308may be asserted. On the next rising edge of the clock, the data remaining in the write data bus may be stored in storage element308. This operation continues until either no more data remains in the write data bus or the synchronous FIFO data buffer300is full.

Read pointer module316may keep track of the location of the next storage element from which to read data. This may be accomplished by sending the read pointer to read data multiplexor304. The read pointer uses a similar pointer logic as implemented in write pointer module314, however the read and write pointer operate independent of one another. The read pointer is incremented following an assertion of the read signal upon the rising edge of the clock signal. Similar to the write pointer, the read pointer may rollover once the maximum count has been reached. For example, if the counter is initialized at 0 and two write actions are performed, data is stored in storage elements306and308and the counter value is 2. The write pointer may point to storage element310, but the read pointer may point to storage element306.

In operation, read data multiplexor304receives the read pointer value and outputs the data associated with the storage element the read pointer indicates as part of the read data bus. Once this read action is performed, the read pointer points to the next location of stored data to be output. These actions may continue until all data is read from synchronous FIFO data buffer300, resulting in synchronous FIFO data buffer300being empty.

Status generation module318may generate the synchronous FIFO data buffer300's full and empty signals, which may be based on whether there is data stored in storage elements302from which to read or write. This may be accomplished by comparing the read and write pointers. The read and write pointers may both include a rollover status bit (e.g., a binary toggle bit with a flagged and unflagged state). The roller over status bit may initialize as unflagged and become flagged when the read or write pointer reaches its maximum number and rolls back to zero, as described above.

Synchronous FIFO data buffer300may generate an empty signal when both the read and write pointers are the same and their respective rollover bits are in the same state (e.g., both flagged or unflagged). Synchronous FIFO data buffer300may generate a full signal when both the read and write pointers are the same but their respective rollover bits are in different states (e.g., one is flagged and the other is unflagged).

In some circumstances, using FIFOs with write and read pointer logic can be inefficient because the processor allocates processing power to keep track of the location of the write and read pointers. Further, the outputs of FIFOs that utilize write and read pointer logic may not be registered (e.g., originate from a data register), which may increase the instability of the FIFO because data is more likely to be overwritten or corrupted. To address this potential problem, in some embodiments, it may be beneficial to implement a scalable synchronous FIFO data buffer with fully registered outputs. This may include a FIFO data buffer that has a customizable depth and width and outputs (e.g., an N number of entries deep, and an M number of entries wide). A scalable synchronous FIFO data buffer may have registered outputs at each element of the FIFO, which may result in more efficient and stable data management.

FIG. 4is a schematic block diagram illustrating a scalable synchronous FIFO data buffer with registered outputs400, according to an example embodiment. Scalable synchronous FIFO data buffer400may include N×M memory structure401, counter420, status generator422, and selection generator424. Scalable synchronous FIFO data buffer400may receive a plurality of signals from other hardware modules that wish to use scalable synchronous FIFO data buffer400for temporary data storage. These signals may include, but are not limited to, (i) write data containing data to be stored, (ii) a reset signal, (iii) a write signal, (iv) a read signal, and (v) a system clock signal. The reset signal may either be in an asserted or deasserted state and may include a command to reset synchronous FIFO data buffer400by emptying all data currently stored. The write signal may either be in an asserted or deasserted state and may indicate data a request to write data in synchronous FIFO data buffer400. The read signal may either be in an asserted or deasserted state and may indicate a request to read data from synchronous FIFO data buffer400. The system clock signal is a signal that oscillates between a high and low state, coordinating the actions of synchronous FIFO data buffer400. Scalable synchronous FIFO data buffer400may be additionally or alternatively referred to as FIFO400throughout this description.

N×M memory structure401may include storage entries402,404, and406, which may include multiplexors408,410, and412, and flip-flop banks414,416, and418, respectively. N corresponds to the depth of the memory structure and M corresponds to the width of the memory structure. The depth and width of the memory structure can be customized during manufacturing of the hardware on which N×M memory structure401is located.

Storage entries402,404, and406represent storage elements within N×M memory structure401to which data can be stored. A hardware module may write and/or read data directly to the storage elements without the need of a write or read interface.

Multiplexors408,410, and412may be M bit wide multiplexors configured to (i) receive multiple inputs and a selection signal, and (ii) output data. Multiplexors408,410, and412can be set to have a width of 1 to M bits, where M is the width of scalable synchronous FIFO data buffer400.

Flip-flop banks414,416,418may be groups of connected flip-flops configured to store data. Each of flip-flop banks414,416, and418may store information as small as a single bit, up to the number of bits customized by the parameter M. For example, if the scalable synchronous FIFO data buffer400is initialized to be 50 entries deep and 8 bits wide, each flip-flop bank may store information from 1 to 8 bits.

Counter420is a module tasked with maintaining a count value relating to the number of storage entries that are occupied in N×M memory structure401. Counter420is comprised of a number of flip-flops that store the count value. The number of flip-flops used to store the count value may correspond to the ceiling of the following equation: log2N, where N is the number of entries that may be used in FIFO400for a particular set of data. For example, if the data requires four entries in FIFO400, the counter value may be stored in two flip-flops. In another example, if the data requires five entries in FIFO400, the counter value may be stored in three flip-flops. Counter420maintains the count value by incrementing the count value when new entries are added to FIFO400, and decrementing the count value when entries are read and removed from FIFO400. Counter420performs the incrementing and/or decrementing action on the residing edge of the clock connected to FIFO400. As discussed previously, all elements of FIFO400share the same clock signal since FIFO400is an example of a synchronous FIFO.

In operation, counter420begins its operation on the rising edge of the clock signal. If the reset signal is asserted, counter420may reset the count value to zero. If the read signal is asserted (e.g., data is being read from FIFO400on this clock cycle) and the write signal is deasserted (e.g., no data is being written to FIFO400on this clock cycle), counter420may decrement the count value by one. Further, if the write signal is asserted (e.g., data is being written to FIFO400) and the read signal is deasserted (e.g., data is not being read from FIFO400), counter420may increment the count value by one. Additionally, if both the read and write signals are asserted or deasserted (e.g., data is being written to and read from FIFO400, or data is not being read from or written to FIFO400), counter420might not change the count value.

Status generator422is tasked with generating the full and empty signals for FIFO400. The full signal is an indication that there are no more available storage entries in FIFO400in which to store data. The empty signal is an indication that none of the storage entries in FIFO400have data from which to read. Status generator422receives the count value from counter420, and the reset, write, and read signals from the component or hardware communicating with FIFO400. Status generator422, along with the other components of FIFO400, performs its operations on the rising edge of the clock signal.

Status generator422may deassert the full signal if the reset signal received by status generator422is asserted. Status generator422may assert the full signal if (i) the count value received from counter420is equal to one less than the number of storage entries in N×M memory structure401, (ii) the write signal is asserted, and (iii) the read signal is deasserted. Status generator422may deassert the full signal if (i) the full signal is already asserted, (ii) the read signal is asserted, and (iii) the write signal is deasserted. If the above conditions are not met, status generator422might not assert or deassert the full signal, leaving the full signal in the same state it was in before status generator422performed its operations.

Status generator422may assert the empty signal if the reset signal received by status generator422is asserted. Status generator422may also assert the empty signal if (i) the count value is equal to 1, (ii) the read signal is asserted, and (iii) the write signal is deasserted. Status generator422may deassert the empty signal if (i) the read signal is deasserted and (ii) the write signal is asserted. If the above conditions are not met, status generator422might not assert or deassert the empty signal, leaving the empty signal in the same state it was in before status generator422performed its operations. In operation, when FIFO400is initialized, status generator422may assert the empty signal because no data is stored in FIFO400.

In one example, FIFO400may have four storage entries, three of which are storing data. In this example, status generator422would not assert the full signal nor the empty signal. However, if status generator422receives an asserted write signal and deasserted read signal, status generator422may assert the full signal on the next rising edge of the clock signal because FIFO400would have all data stored in all available storage entries. If the next operation for FIFO400is to read data out of FIFO400, and the full signal is asserted, then status generator422may deassert the full signal on the next rising clock edge after the data is read from FIFO400.

Selection generator424may be tasked with generator a flip-flop enable and multiplexor selection signal for each storage entry in N×M memory structure401. The flip-flop data enable signal may include an indication to one of flip-flop banks414,416, and/or418to store data on the next rising clock edge. The multiplexor selection signal may include an indication to multiplexors408,410, and/or412to route the write data bus connected to the “1” input to the output.

In operation, selection generator424receives the counter value from counter420, and the write and read signals from the module or hardware component that is communication with FIFO400. Selection generator424may assert or deassert the multiplexor selection and data enable signals for each storage entry in N×M memory structure401according to the following behavior: for each of storage entries402,404, and406of N×M memory structure401, selection generator424may assert the multiplexor selection signal if the count value is equal to an index value of the storage entry in N×M memory structure401or if (i) the write signal is asserted, (ii) the read signal is asserted, and (iii) the count value is one greater than the index value of the storage entry in N×M memory structure401. Selection generator424may deassert the multiplexor selection signal if none of the above conditions are satisfied.

Selection generator424may assert or deassert the flip-flop data enable signal for each storage entry in N×M memory structure401according to the following behavior: for each of storages entries402,404, and406of N×M memory structure401, selection generator424may assert the data enable signal if (i) the count value is equal to the index value of the storage entry and (ii) the write signal is asserted. Selection generator424may also assert the data enable signal if the read signal is asserted. If none of the conditions above are met, selection generator424may deassert the data enable signal.

For example, storage entry406may have an index value of 0, storage entry404may have an index value of 1, and storage entry402may have an index value of 2. Selection generator424may first determine whether to assert or deassert the multiplexor signal for storage entry406. If the count value received from counter is 0, which matches the index value of 0 for storage entry406, selection generator424may assert the multiplexor selection signal for storage entry406. Additionally, if the write signal and read signal received by selection generator424are asserted and the count value is 1 (e.g., one greater than storage entry406's index value of 0), selection generator424may assert the multiplexor selection signal for storage entry406. However, if the above conditions are not satisfied, selection generator424may deassert the multiplexor selection signal. Selection generator424may assert the data enable signal for storage entry406if (i) the count value received from counter is 0, which matches the index value of 0 for storage entry406, and (ii) the write signal is asserted. If the count value does not match the index value, selection generator424may still assert the data enable signal if the read signal is asserted. However, if the above conditions for asserting the data enable are not met, selection generator424may deassert the data enable signal for storage entry406. This process may be repeated for storage entries404and402.

In one example embodiment, the processor may use FIFO400to temporarily store data. As previously discussed and shown inFIG. 4, FIFO400may have N×M memory structure401, counter420, status generator422, and selection generator424. When initialized, counter420may set the count value to zero, status generator422may assert the empty signal and deassert the full signal, and selection generator424may assert the multiplexor selection and data enable signals for storage entry406. Selection generator424may deassert the multiplexor selection and data enable signals for storage entries404and402.

FIFO400may then receive an asserted write signal from the processor, indicating it wishes to store data in FIFO400. Multiplexor412of storage entry406may (i) receive the data to be stored through the write data bus and the asserted multiplexor selection signal, and (ii) store the data into flip-flop bank418. Counter420may receive the asserted write signal and increment the count value from zero to one. Status generator422may receive the asserted write signal and may deassert the empty signal.

FIFO400may then receive an asserted read signal and deasserted write signal, indicating the data stored in storage entry406is now to be outputted and there is no new data to store. Counter420may receive the asserted read signal and decrement the count value from one to zero. Status generator422may receive the asserted read signal and may assert the empty signal because after the data is outputted, FIFO400might be empty. Selection generator424may receive the asserted read signal and assert both the multiplexor selection signal and data enable signal. Flip-flop bank418may output valid data to the Read Data signal if the status of FIFO400is not empty. The output from flip-flop bank418is a registered output.

III. Method Examples

FIG. 5illustrates a method, according to an example embodiment. The method includes blocks that may be carried out in an order other than that illustrated. Furthermore, various blocks may be added to or subtracted from the described methods within the intended scope of this disclosure. The methods may correspond to steps that may be carried out using some or all of the elements of system200, FIFO300, and/or FIFO400, as illustrated and described in reference toFIGS. 2-4.

FIG. 5is a flow diagram illustrating a method500, according to an example embodiment. Method500describes how a scalable synchronous FIFO data buffer operates. Block502may include receiving, via a counter, a plurality of signals comprising a system clock signal, a reset signal, a write signal, and a read signal.

Block504may include transmitting, via the counter, a count of total entries in the FIFO.

Block506may include receiving, via a status generator, the plurality of signals and the count of total entries.

Block508may include transmitting, via the status generator, a status signal.

Block510may include receiving, via a selection generator, the count of total entries from the counter, the write signal, and the read signal.

Block512may include transmitting, via the selection generator, a data enable signal and a multiplexor selection signal.

Block514may include receiving, via an M bit wide multiplexor within one entry of a scalable N×M flip-flop memory structure, the multiplexor selection signal, new write data to the FIFO, and a data output from a previous entry in the scalable N×M flip-flop memory structure. N may be a number of entries in the scalable N×M flip-flop memory structure. M may be a number of bits using flip-flops.

Block516may include transmitting, via the M bit wide multiplexor, write data.

Block518may include receiving, via a flip-flop bank within one entry of the scalable N×M flip-flop memory structure, the write data, the data enable signal, and the system clock signal.

Block520may include transmitting, via the flip-flop bank, a data output comprising information stored in the flip-flop bank.

In some embodiments, the previous entry in the scalable N×M flip-flop memory structure may be entry N−1.

In some embodiments, the counter may include a number of flip-flops equal to log2(N).

In some embodiments, the counter may operate on a rising edge of the system clock signal.

In some embodiments, the status signal may consist of either a full signal or an empty signal.

In some embodiments, the flip-flop bank of the scalable N×M flip-flop memory structure may store a number of bits in a range of 1 to M.

While various examples and embodiments have been disclosed, other examples and embodiments will be apparent to those skilled in the art. The various disclosed examples and embodiments are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.