Chopper-stabilized amplifier and method therefor

In one embodiment a chopper-stabilized amplifier may be formed to include a symmetrical passive RC notch filter having two cut-off frequencies. In an embodiment, the chopper stabilized amplifier may use only two clock signals to control the chopping operations.

BACKGROUND OF THE INVENTION

The present invention relates, in general, so electronics, and more particularly, to semiconductors, structures thereof, and methods of forming semiconductor devices.

Chopper stabilized amplifiers were previously used in various electronic applications. One example of a chopper stabilized amplifier was disclosed in U.S. Pat. No. 7,292,095. Some applications of chopper stabilized amplifiers used a four phase clock, that had four clock signals that were staggered in time. These prior chopper stabilized amplifiers often had excessive ripple or noise on the output and some had glitches on the output. For example, the operation resulting from the four phase clock system could result in a glitch in the output voltage for every transition of each phase of the four phase clock.

Accordingly, it may be desirable to form an integrated circuit chopper stabilized amplifier that reduces glitches and/or reduces ripple in the output. It may be desirable to have a chopper stabilized amplifier that has low noise, low-offset drift, good signal stability, or low current consumption.

For simplicity and clarity of the illustration(s), elements in the figures are not necessarily to scale, some of the elements may be exaggerated for illustrative purposes, and the same reference numbers in different figures denote the same elements, unless stated otherwise. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying element or current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control element or control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Additionally, one current carrying element my a carry current in one direction through a device, such as carry current entering the device, and a second current carrying element may carry current in an opposite direction through the device, such as carry current leaving the device. Although the devices are explained herein as certain N-channel or P-Channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. One of ordinary skill in the art understands that the conductivity type refers to the mechanism through which conduction occurs such as through conduction of holes or electrons, therefore, and that conductivity type does not refer to the doping concentration but the doping type, such as P-type or N-type. It will be appreciated by those skilled in the art that the words during, while, and when as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay(s), such as various propagation delays, between the reaction that is initiated by the initial action. Additionally, the term while means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. When used in reference to a state of a signal, the term “asserted” means an active state of the signal and the term “negated” means an inactive state of the signal. The actual voltage value or logic state (such as a “1” or a “0”) of the signal depends on whether positive or negative logic is used. Thus, asserted can be either a high voltage or a high logic or a low voltage or low logic depending on whether positive or negative logic is used and negated may be either a low voltage or low state or a high voltage or high logic depending on whether positive or negative logic is used. Herein, a positive logic convention is used, but those skilled in the art understand that a negative logic convention could also be used. The terms first, second, third and the like in the claims or/and in the Detailed Description of the Drawings, as used in a portion of a name of an element are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1schematically illustrates an example of an embodiment of a portion of a chopper-stabilized amplifier10that has reduced number of glitches and/or amplitude of glitches in the output signal. Amplifier10may include an input chopper circuitry or input, chopper circuit, or circuit15, a first operational transconductance amplifier or amplifier85, an output chopping circuitry or output chopper circuit or circuit25, a passive RC symmetrical notch filter or filter40, and a second operational transconductance amplifier or amplifier83. Amplifier10may also include operational transconductance amplifiers86and87. Amplifier10may include an inverting input conductor or inverting input or input11and a non-inverting input conductor or non-inverting input or input12by which amplifier10may receive an input signal Vin. Amplifier10may also include an output conductor or output terminal or output95. Amplifier10may be configured to form an output signal Vout on output95. First chopper circuit15may be configured to chop the input signal, Vin, and form a first chopped signal. Circuit15may also be configured to apply the first chopped signal, that is derived from the input signal Vin, to first operational transconductance amplifier85. An embodiment of circuit15may include outputs connected to respective input conductors or input terminals or inputs20and21of amplifier85. Amplifier85may also include output conductors or output terminals or outputs26and27. Output chopper circuit25may be coupled to receive the output signal from amplifier85. For example, circuit25may have inputs connected to outputs26and27to receive the output signal from amplifier85. Circuit25may be configured to chop the output signal from amplifier85and form a second chopped signal. Those skilled in the art will understand that chopper circuits15and25may assist in reducing offsets voltages in the output of amplifier85and to reduce common mode voltages in the output signal of amplifier85.

An embodiment of amplifier10may be configured to have at least two signal paths. A first signal path of amplifier10may include a three-stage high gain signal path through operational transconductance amplifiers85,83, and87, and a second signal path of amplifier10may include a two-stage wideband width signal path through operational transconductance amplifiers86and87.

Symmetrical notch filter40may include a first input35and a second input36that are configured to receive the second chopped signal from circuit25. An embodiment of amplifier10may include a compensation capacitor39connected between inputs35and36of filter40. Filter40may also include first and second output conductors or outputs80and81, respectively. Outputs80and81may be respectively connected to a non-inverting input and an inverting input of amplifier83.

An embodiment of circuit15may include switches16and18each having a first terminal connected to inverting input11, and switches19and17each having a first terminal connected to non-inverting input12. Switches16and19may also include a second terminal connected to input20of amplifier85, such as for example a non-inverting input, and switches18and17may include a second terminal connected to input21of amplifier85, such as for example an inverting input. Outputs26and27of amplifier85may be connected to inputs of output chopper circuit25. Circuit25may include chopper switches30and32each having a first terminal connected to output26, and chopper switches33and31each having a first, terminal connected to output27. Switches30and33may also include a second terminal connected to input35, and switches32and31may include a second terminal connected to input36. The output of circuit25is applied to differential inputs35and36of filter40. An embodiment may include that input36may be connected to one terminal of a compensation capacitor38, the other terminal of which may be connected to ground. Input35may be connected to one terminal of a compensation capacitor37, the other terminal of which may be connected to ground. A compensation capacitor92may have a first terminal connected to input35and the other terminal of capacitor92may be connected to output95. In one embodiment, capacitor37may have a value that may be substantially identical with the value of capacitor38.

In an embodiment, filter40may be configured to form a symmetrical capacitive load for the common-mode voltage provided between inputs35and36of filter40. An embodiment may include that the symmetrical capacitive load of filter40may be for the differential voltage at inputs35and36or alternately for both the differential and common mode voltages. In another embodiment, filter40together with capacitors37and38may be configured to form a symmetrical capacitive load for the common-mode voltage provided between inputs35and36. An embodiment may include that the symmetrical capacitive load for filter40and capacitors37and38may be for the differential voltage at inputs35and36or alternately for both the differential and common mode voltages. In another embodiment, filter40together with capacitors37,38, and39may be configured to form a symmetrical capacitive load for the common-mode voltage provided between inputs35and36. An embodiment may include that the symmetrical capacitive load for filter40and capacitors37,38, and39may be for the differential voltage at inputs35and36or alternately for both the differential and common mode voltages.

In an embodiment, filter40may be configured to be symmetrical including symmetrical to a virtual ground. For example, section57may be symmetrical around a virtual ground such that the two signal paths connected to input35and connected between input35and the virtual ground, and such that the two signal paths connected to input36are connected between input36and the virtual ground. In an embodiment, filter40may be symmetrical by being configured to receive a differential input signal from the two outputs of circuit25and configured to provide a differential output signal between outputs80and81.

In another embodiment, most of the compensation capacitors, except capacitor91, may be relocated from inputs35and36of filter40to outputs80-81. For example, compensation capacitor92may have the first terminal connected to output80and the other terminal may be connected to output95, compensation capacitor39may be connected between outputs80and81of filter40, compensation capacitor37may be connected between output80and a ground terminal, and compensation capacitor38may be connected between output81and the ground.

A balanced combination between the two described compensation capacitor networks may be formed within another embodiment, too, as a trade-off for certain electrical parameters such as: settling time, transient overshoot and undershoot, rise and tall time, unity gain bandwidth and phase margin.

FIG. 2illustrates in a general manner a block diagram embodiment of an example of a clock generation circuit and also includes a graph illustrating some signals that may be formed during the operation of the clock generator circuit. The clock generation circuit may include a main oscillator circuit or oscillator22and a clock circuit23. In one embodiment, amplifier10may be configured to use only a two phase clock. For example, a single two phase clock may be used for operating circuits15and25. An embodiment may include that no clock signal may be used for operating any of the elements of filter40. For example, oscillator22may be configured to form a master clock signal. Circuit23may be configured to receive the main clock signal and form the two phase clock signals C1and C2. A plot100illustrates the master clock signal from oscillator22that is used to form the synchronized two phase clock signals C1and C2. A plot98illustrates a first clock signal (C1) of the two phase clock signals and a plot99illustrates a second clock signal (C2) of the two phase clock signals. In one embodiment, the first and second clock signals (C1and C2) may be formed to have substantially the same frequency as each other and may be formed to be substantially opposite in phase. Signals C1and C2may have substantially fifty percent duty cycles in some embodiments. An embodiment may include that signals C1and C2have transitions substantially simultaneously. In other embodiments, signals C1and C2may not overlap but in other embodiments may have some overlap. Those skilled in the art will appreciate that in some embodiments there may be a short dead time between the asserted states of C1and C2to ensure that there is no overlap of the asserted states of the C1and C2signals. Those skilled in the art will appreciate that although the master clock signal is used to generate the C1and C2clock signals, the master clock signal is not used in operating amplifier10, nor is the switching frequency of amplifier10the same as the frequency of the master clock signal. The C1and C2clock signals may be referenced to or derived from the master clock signal from oscillator22formed with amplifier10on a common semiconductor substrate.

Signals C1and C2may be used to control the various chopping switches as shown inFIG. 1. C1may be configured to control switches16,17,30, and31, and C2may be configured to control switches18,19,32, and33.

Referring back toFIG. 1, filter40may be formed to include a frequency response that includes a plurality of notches or cutoff frequencies. In one embodiment, filter40may be configured to form the notches approximately at harmonics of the chopping frequency (fs) of circuits15and25, so that the notches may assist in suppressing the ripple voltages that can occur in a chopper-stabilized amplifier. The chopping frequency may be the frequency of either of clock signals C1or C2. The amplitude of the ripple voltage as it appears at the input of filter40, such as for example a triangle voltage waveform, may be related to the value of capacitor39and also to the chopping frequency fs. In an embodiment, filter40may be configured to include at least two-cutoff frequencies. An embodiment of filter40may be configured to filter not only the first harmonic or fundamental of the chopping frequency (fs) used to operate circuit25(or alternately the frequency fs used to operate circuits15and/or25), but also at least one other harmonic of the chopping frequency used to operate circuit25. In an embodiment, the other harmonic may be the third harmonic. An embodiment may include configuring filter40as a symmetrical passive RC notch filter. An embodiment may include configuring filter40with only passive components, such as for example with only resistors and capacitors. In an embodiment, filter40may be configured to operate without receiving a two phase clock signal. An embodiment of filter40may be configured to be devoid of clock signals used to operate any of the elements of filter40. In an embodiment, amplifier10may be configured to operate with only a single two phase clock, such as for example a single two phase clock that is derived from a master clock. An embodiment may include that the chopping frequency may be correlated with the cut-off frequencies of filter40by forming the clock generation circuit that includes oscillator22and circuit23to include a current-driven oscillator and a bias circuit that are formed to use the same type of resistor as the resistors in filter40. It has been found that filter40improves the stability of the output signal Vout formed on output95and reduces output glitches in the output signal Vout.

Filter40may also be configured to include multiple signal paths in an embodiment. An embodiment of filter40may be configured to include two sections, a first section57and a second section58. Additionally, first section57may be configured to include multiple signal paths in an embodiment. For example, each input35or36may be connected to a first signal path made with resistors and to a second signal path made with capacitors. In an embodiment, input35may be connected to one signal path that includes series connected resistors42and43, and to another signal path that includes series connected capacitors44and45. Both of these signal paths may be reconnected together an a node60. In an embodiment, node60may be configured as a first output or output of first section57. Similarly, input36may be connected to a first signal path that includes series connected resistors50and51, and to a second signal path that includes series connected capacitors52and53. Both of these signal paths may be reconnected together at a node61. In an embodiment, node61may be configured as a second output or output of first section57. Thus, section57of filter40may have two resistor signal paths and two capacitor signal paths coming from inputs35and36. Intermediate connections of the two resistor paths, such as for example at nodes46and47, may be connected to a capacitor48, while intermediate connections of the two capacitor paths, such as for example nodes54and55, may be connected to a resistor41. In an embodiment, the value of resistors41-43and50-51may be identical. Also, an embodiment may include that the value of capacitors44-45,48, and52-53may be identical. This may assist in providing good matching.

An embodiment of filter40may also include that second section58may also be configured to include multiple signal paths. An embodiment of second section58may be obtained by multiplying first section57, connecting it in series, and changing only the values of the resistors.

An embodiment of second section58may include two resistor signal paths and two capacitor signal paths connected to the two inputs of section58. In an embodiment, the two inputs of section58may be connected to respective outputs60and61of section57. In an embodiment, second section58may include a first signal path and a second signal path connected to a first input of section58, for example, such as to output60of first section57. The first signal path may include series connected resistors6and64and the second signal path may include series connected capacitors65and66. Both these signal paths may be reconnected together at output80. In an embodiment, output80may be configured as a first output of second section58. Also, an embodiment of the second input to section58may be connected both to a first signal path made with series connected resistors72and73, and to a second signal path made with series connected capacitors74and75. Both of these two signal paths from output61may be reconnected together at output81. In an embodiment, output81may be configured as a second output of second section58. The intermediate connections of the two resistors paths of section58, such as for example nodes67and68, may be connected to a capacitor69, while the intermediate connections of the capacitor paths, such as for example nodes77and78, may be connected to a resistor62.

The value of resistors62-64and72-73may be substantially equal. Also, the value of capacitors65-66,69, and74-75may be substantially equal, and in one embodiment may also be substantially equal to the value of capacitors44-45,48, and52-53.

Amplifier10may also include a feed-forward path that includes amplifier86and amplifier87. In some embodiments, amplifier87may be configured as an operation amplifier. Input12of amplifier10may be connected to an inverting input of amplifier86, and a non-inverting input of amplifier86may be connected to input11of amplifier10. An output90of amplifier86may be commonly connected to an inverting input of amplifier87, to an output of amplifier83, and to a first terminal of compensation capacitor91, the other terminal of which may be connected to output95. A non-inverting input of amplifier87may be connected to ground. An output of amplifier87may be connected to output95. The transconductance of amplifiers85and83are gm1 and gm2, respectively. The transconductance of amplifiers87and86are gm3 and gm4, respectively.

As expressed hereinbefore, an embodiment of filter40may be configured to have two cutoff frequencies. In an embodiment, the first cutoff frequency may be the chopping frequency used to operate circuit25(or alternately the frequency used to operate circuit15) and the second cutoff frequency may be a harmonic of the chopping frequency. In an embodiment, the second cutoff frequency may be the third harmonic of the chopping frequency. For example, an embodiment of filter40may be configured to filter not only the first harmonic of the chopping frequency used to operate circuit25(or alternately the frequency used to operate circuit15), such as for example the frequency of signals C1and C2, but also at least one other harmonic of the chopping frequency used to operate circuit25. Those skilled in the art will appreciate that the second cutoff frequency of filter40may be formed to be other harmonics other than the third harmonic. The second notch frequency may be other odd harmonics since the odd harmonics are believed to carry most of the energy, apart from the even harmonics. For example, the second notch frequency may be a fifth harmonic. However, in other embodiments, at least one of the cutoff frequencies may be an even harmonic. A formula for a cutoff frequency of filter40may be expressed as:
fcutoff=1/(2πRC).

In an embodiment, the values of the resistors and capacitors in first section57may be selected to form the first cutoff frequency, and the values of the resistors and capacitors of second section58of filter40may be chosen for form the second cutoff frequency.

One non-limiting example embodiment may include that the frequency of the C1and C2signals, thus the chopping frequency, may be approximately one hundred twenty five kilo-Hertz (125 kHz). Those skilled in the art will understand that the explanation of this example embodiment of a 125 kHz chopping frequency is explained as vehicle to explain certain aspects and advantages of amplifier10. However, the chopping frequency may have other values or be other frequencies in other embodiments. For example, higher frequencies may be easier to filer while lower frequencies may give certain improved performance. In some embodiments, the chopping frequency may be between approximately ten (10) kHz to approximately one (1) MHz in other embodiments. The actual value of the cutoff frequencies of filter40would change according to the frequency selected for the chopping frequency

For the example embodiment of the 125 kHz chopping frequency, the first cutoff frequency is approximately the 125 kHz or chopping frequency itself. In this embodiment, the value of all the capacitors within filter40may be chosen to be approximately five (5) picofarads. This value may be high enough to minimize the parasitic capacitance influence, but also small enough to be easily integrated as a portion of semiconductor device formed on a semiconductor substrate. The value of capacitor91may have a value of approximately five (5) picofarads, capacitor92may have a value of approximately six (6) picofarads, and capacitor39may have a value of approximately eighteen (18) picofarads. The value of capacitor92may be optimized versus91for symmetrical error in processing the high-amplitude sinusoidal signal. Capacitors38and37may each have a value of approximately eighteen (18) picofarads. Those skilled in the art will appreciate that the capacitor values may be different in other embodiments.

For this non-limiting example embodiment, values of resistors41-43,50, and51used in first section57were calculated to be approximately 254.65 kilo ohms each in order to form the first cutoff frequency at the chopping frequency fs of approximately 125 kHz. To form the second cutoff frequency or second notch at the third harmonic, the value of resistors62-6,72, and73was calculated to be approximately 84.88 kilo ohms. Once the values of the passive devices within filter40are calculated, a simulation or other means can be used to evaluate the magnitude versus frequency of the differential transfer function of filter40which may be expressed in one embodiment, in dB or decibels, as:
|H40|[dB]=20(log|(V80−V81))/(V35−V36)

where:|H40| is the magnitude of the differential transfer function of filter40,V35−V36is the differential input voltage to filter40between inputs35and36, andV80−V81is the differential output voltage of filter40between outputs80and81.

In one example embodiment, the obtained simulated cutoff frequencies may not be exactly the expected ones for the values used for the resistors and capacitors. For example in the above non-limiting example embodiment, the first cutoff frequency obtained from the simulation may be approximately 123.14 kHz and a higher 381.42 kHz for the second cutoff frequency. Thus, the real cutoff frequencies of the two series connected sections57and58of filter40may be both affected by an error of approximately −1.49% and approximately +1.71%, respectively. It is believed that these errors may be the result of mutual interaction.

In another non-limiting example embodiment, the value of resistors41-43,50, and51may be changed to a value of approximately 250.85 kilo ohms, while the value of resistors62-64,72, and73may be changed to approximately 86.33 kilo ohms. A simulation with these changed values illustrates an attenuation of the differential input signal.

FIG. 3is a graph having a plot93that illustrates in a general manner an example of the transfer function (H40) of filter40and the cutoff frequencies or notches formed by the changed values of the non-limiting example embodiment. The abscissa indicates frequency and the ordinate illustrates one non-limiting example of the value of the magnitude of the transfer function H40 in db. In an embodiment of filter40, the magnitude of the differential transfer function of filter40at low frequencies may be near to substantially 0 dB or 1, which means that a signal having such a frequency will pass substantially without any modification. For an embodiment of filter40, the magnitude of the differential transfer function of filter40at higher frequencies, such as in a non-limiting example embodiment at frequencies near to the chopping frequency and greater, may at first decrease and thereafter it may follow a specific symmetrical double notch shape. In a non-limiting example embodiment, filter40may provide an attenuation of approximately 59.2 db at frequencies close to substantially 125 kHz, while the attenuation near substantially 375 kHz may be approximately 61.5 dB. In an embodiment and considering a frequency domain around the chopping frequency, in referring to plot93, it can be shown that if the chopping frequency shifts, due to certain causes, a minimum attenuation of 40 dB can be obtained between 113.6 kHz and 140 kHz. Another attenuation, such as for example approximately 40 db, around the third harmonic of the chopping frequency, for example approximately 375 kHz, can be obtained for a frequency domain between 334.2 kHz and 412.9 kHz. Frequencies between the two cutoff frequencies, for example between approximately 1.25 kHz and 375 kHz, may be attenuated with more than approximately 31.4 db, and a minimum may result near approximately 215.18 kHz. An example of a fifth harmonic of the chopping frequency, such as for example approximately 625 kHz, may be attenuated with only 23.2 dB. But, since the ripple component at this harmonic is much smaller than those of the previous two odd harmonics, this means that the overall performance of the filter and the changed values is good.

In a non-limiting example embodiment of filter40, the magnitude of differential transfer function of filter40may increase at high frequencies to a value near to substantially 0 db or 1.

It is believed that filter40may be formed to provide around 60 dB (or 1,000:1) attenuation for both first and third harmonics of the chopping frequency. Filter40may also be formed to provide an acceptable level of performance if the chopping frequency is modified with ±10%. In an embodiment, the acceptable performance may be approximately 40 dB of attenuation. Those skilled in the art will appreciate that a certain tracking behavior may be formed within amplifier10. For example, oscillator22(FIG. 2) may include current generators or current sources that may be formed to include resistors formed from the same type of material or from the same type of structure used for forming the resistors of filter40. For example, the resistors of the oscillator22and the resistors of filter40may be formed from polysilicon resistors that have approximately the same resistivity or the same cross-sectional area. Consequently, if value of the resistors of oscillator22change (such as for example by temperature variation or by placement on the semiconductor wafer or by process parameter variations) the value of the filter40resistors may also change and provide a tracking between the cutoff frequencies and the frequency of clock signals C1and C2. Thus, in an embodiment, a certain tracking behavior may be built-in within amplifier10. In an embodiment, the chopping frequency and the cutoff frequencies of the symmetrical passive RC notch filter may be well correlated, as Monte-Carlo simulations have confirmed, and it is believed that, in an embodiment, the chopping frequency and the cutoff frequencies of the symmetrical passive RC notch filter may be well correlated.

Forming filter40with two cutoff frequencies or notches may introduce certain series resistances between outputs35and36of chopping circuit25and outputs80-81of filter40. However, the noise generated by these series resistances is divided, from the overall input-referred noise point of view, by the voltage gain of amplifier85which means that any noise degradation brought by filter40with two cutoff frequencies is quite low. In an embodiment, the value of the voltage gain of amplifier85may be between approximately 66 dB and approximately 74 dB in one non-limiting example embodiment, depending on conditions.

FIG. 4is a graph having a plot94that illustrates in a general manner an example of an embodiment of a non-limiting example embodiment of a signal received between inputs35-36of filter40. The abscissa indicates time and the ordinate indicates increasing value of the illustrated signals. A plot102illustrates in a general manner an example of a non-limiting example embodiment of output signal Vout. The abscissa indicates time and the ordinate indicates increasing value of the illustrated signal. Plot94illustrates that the input signal received by filter40may have high magnitude ripple noise. Plot102illustrates that output signal Vout on the output of amplifier10has minimized ripple noise. In one non-limiting example embodiment of amplifier10and filter40for non-limiting examples of signals illustrated by plots94and102, amplifier85may be configured to have an intrinsic ten milli-volt (10 mV) offset voltage, while the closed loop gain of the non-limiting example embodiment of amplifier10may be approximately ten (10). For the non-limiting example embodiment the ripple noise may have a peak-to-peak amplitude of approximately fourteen milli-volts (14 mV), it the output ripple noise shown in the example embodiment of plot102may have a peak-to-peak amplitude of approximately one hundred and forty (140) micro-volts. Ripple noise frequency may be the chopping frequency of approximately 125 kHz.

It is believed that filter40provides amplifier10with reduced ripple over prior art chopper-stabilized operational amplifiers such as for example over prior art chopper stabilized operational amplifiers that used more than two multi-phase clock signals for the amplifier, considering similar or different closed-loop and load conditions.

FIG. 5is a graph having a plot96that illustrates in a general manner glitches found at the output of a prior-art chopper-stabilized operational amplifier, and having a plot97that illustrates in a general manner an example of glitches at the output of a non-limiting example embodiment of amplifier10. The abscissa indicates time and the ordinate indicates increasing value of the illustrated signal. The output glitches of plots96-97may be 0.003 mV (or 3 micro-volts) peak-to-peak. In the non-limiting example embodiment, both operational amplifiers may be unity-gain configured while having a load of 100 kilo ohms in parallel with 100 picofarads.

For one non-limiting example embodiment of amplifier85, the offset voltage of amplifier85may give certain, even much reduced, 125 kHz ripple on Vout. In an embodiment, a similar offset voltage of amplifier86may provide on Vout a DC voltage error value equal with the offset voltage Vos of the operational amplifier itself, times the closed loop gain. A typical Vos value depends on both the gain of the cells and on the circuit and layout techniques used to implement them. It is believed that amplifier10could have a typical input offset voltage Vas of plus or minus one (±1) micro-volt, while the minimum/maximum Vas values could be within plus or minus five (±5) micro-volts, over the entire temperature and process drift ranges. These values can be favorable compared with prior-art amplifiers. For a non-limiting embodiment of amplifier10that uses a multi-phase clock that has only two clock phases, instead of the four phases for some prior-art amplifiers, amplifier10may form only half of the number of glitches in the output signal Vout.

In one non-limiting example embodiment, a closed loop gain of one (1) was considered, together with a load consisting of a ten (10) kilo ohms resistor connected in parallel with a one hundred (100) picofarads capacitor.FIG. 5illustrates that a non-limiting example embodiment of amplifier10has half the number of glitches of prior-art amplifiers. In one example embodiment, amplifier10may have, on its output voltage, a glitch at every four micro-seconds (4 μs), while the prior-art amplifier has one at every two micro-second (2 μs). This means that amplifier10may have a lower intrinsic noise and also a lower intrinsic current consumption, since fewer transitions will produce fewer glitches within the supply current. Considering such advantages, it is believed that amplifier10may be particularly advantages in micro-power integrated circuit applications and/or low noise applications.

FIG. 6illustrates in a general manner an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit110that is formed on a semiconductor die111. Filter40and/or amplifier10may be formed on die111. Die111may also include other circuits that are not shown inFIG. 6for simplicity of the drawing. Filter40and device or integrated circuit110may be formed on die111by semiconductor manufacturing techniques that are well known to those skilled in the art. In one non-limiting example embodiment of filter40and amplifier10formed on a semiconductor die, the example implementation of amplifier10occupied approximately 0.5 square-mm and the non-limiting example embodiment of filter40occupied approximately 0.07 square-mm.

From all the foregoing, one skilled in the art can determine that it is desirable to form a chopper-stabilized amplifier having reduced output ripple noise and a reduced offset voltage such as for example by using a novel filtering of the signal generated at the output of the chopper amplifier. An embodiment may include forming a passive symmetrical notch filter.

In one embodiment, multi-phase clock signals may be used that have only two substantially symmetrical clock signals. In an embodiment, no clock signals may be used within the filter section of the symmetrical notch filter. It is believed that the number of glitches within the output signal is reduced. An embodiment may include the use of a symmetrical passive PC (Resistor-Capacitor) notch filter with two-cutoff frequencies.

An embodiment of filter40is formed to be symmetrical. In one method of forming the symmetrical notch filter, may be conceptually thought of as a passive RC twin-T filter may be mirrored related to GND and merged at the identical series connected elements. Another symmetrical passive RC notch filter may be connected to the passive RC twin-T filter and in series therewith.

Those skilled in the art will appreciate that an embodiment of the symmetrical passive RC notch filter may include—a first path including a first resistor coupled between the first input terminal and a first conductor, a second resistor coupled between the first conductor and a second conductor, a third resistor coupled between the second conductor and a third conductor, and a fourth resistor coupled between the third conductor and the second output terminal.

An embodiment of filter may include a second path having a fifth resistor coupled between the second input terminal and a fourth conductor, a sixth resistor coupled between the fourth conductor and a fifth conductor, a seventh resistor coupled between the fifth conductor and a sixth conductor, and an eighth resistor coupled between the sixth conductor and the second output terminal.

In an embodiment, filter may include a third path having a first capacitor coupled between the second input terminal and a seventh conductor, a second capacitor coupled between the seventh conductor and the fifth conductor, a third capacitor coupled between the fifth conductor and an eighth conductor, and a fourth capacitor coupled between the eighth conductor and the second output terminal,

An embodiment of filter may include a fourth path having a fifth capacitor coupled between the first input terminal and a ninth conductor, a sixth capacitor coupled between the ninth conductor and the second conductor, a seventh capacitor coupled between the second conductor and a tenth conductor, and an eighth capacitor coupled between the tenth conductor and the first output terminal,

An embodiment of filter may also include at least one of a ninth resistor coupled between the seventh conductor and the ninth conductor, a tenth resistor coupled between the eighth conductor and the tenth conductor, a ninth capacitor coupled between the first conductor and the fourth conductor, and a tenth capacitor coupled between the third conductor and the sixth conductor.

Those skilled in the art will appreciate that an embodiment of a chopper-stabilized amplifier may comprise:

a first operational transconductance amplifier, such as for example amplifier85;

a first chopper circuit, such as for example circuit15, coupled to an input of the first operational transconductance amplifier for chopping an input signal and applying a chopped input signal to the input of the first operational transconductance amplifier;

a second chopper circuit, such as for example circuit25, coupled to an output of the first operational transconductance amplifier for chopping an output signal produced by the first operational transconductance amplifier; and

a symmetrical passive RC notch filter, such as for example filter40, with two cutoff frequencies having an input coupled to an output of the second chopper circuit to filter a chopped output signal produced by the second chopper circuit to notch filter ripple voltages received from the output of the second chopper circuit.

In an embodiment, the chopper-stabilized amplifier may also include that a chopper switching frequency may be correlated with at least a first cutoff frequency of the two cutoff frequencies of the symmetrical passive RC notch filter by using a current-driven oscillator and a bias circuit that both use a same type of resistor as the symmetrical passive RC notch filter itself.

An embodiment may include that the two cutoff frequencies of the symmetrical passive RC notch filter are correlated to approximately the chopping frequency and approximately a third harmonic of the chopping frequency.

Another embodiment may include that the two cutoff frequencies of the symmetrical passive RC notch filter may be correlated to approximately the chopping frequency and approximately a fifth harmonic of the chopping frequency.

An embodiment may include configuring the chopper-stabilized amplifier to use no more than two complementary clock signals, both having substantially fifty percent duty cycles and having substantially simultaneous and opposite transitions wherein the first and second chopper circuits are configured to operate with the two complementary clock signals.

In an embodiment, the symmetrical passive RC notch filter may include first and second inputs, wherein the symmetrical passive RC notch filter includes first and second outputs, and wherein the symmetrical passive RC notch filter may also include:

a first path including a first resistor, such as for example a resistor42, coupled between the first input, such as for example input35, and a first node, such as for example node46, and a second resistor, such as for example resistor43, coupled between the first node and a second node, such as for example node60;

a second path including a first capacitor, such as for example capacitor44, coupled between the first input and a third node, such as for example node54, and a second capacitor, such as for example capacitor45, coupled between the third node and the second node;

a third path including a third resistor, such as for example resistor50, coupled between the second input, such as for example input36, and a fourth node, such as for example node47, and a fourth resistor, such as for example resistor51, coupled between the fourth node and a fifth node, such as for example node61;

a fourth path including a third capacitor, such as for example capacitor52, coupled between the second input and a sixth node, such as for example node55, and a fourth capacitor, such as for example capacitor53, coupled between the sixth node and the fifth node;

a fifth resistor, such as for example resistor41, coupled between the third node and the sixth node and a fifth capacitor, such as for example capacitor48, coupled between the first node and the fourth node.

Another embodiment may also include, a fifth path including a sixth resistor, such as for example resistor63, coupled between the second node and a seventh node, such as for example node67, and a seventh resistor, such as for example resistor64, coupled between the seventh node and the first output, such as for example output80;

a sixth path including a sixth capacitor, such as for example capacitor65, coupled between the second node and an eighth node, such as for example node77, and a seventh capacitor, such as for example capacitor66, coupled between the eighth node and the first output;

a seventh, path including an eighth resistor, such as for example resistor72, coupled between the fifth node and a ninth node, such as for example node68, and a ninth resistor, such as for example resistor73, coupled between the ninth node and the second output, such as for example output81;

an eighth path including an eighth capacitor, such as for example capacitor74, coupled between the fifth node and a tenth node, such as for example node78, and a ninth capacitor, such as for example capacitor75, coupled between the tenth node, such as for example node78, and the second output; and

a tenth capacitor, such as for example capacitor69, coupled between the seventh node and the ninth node and a tenth resistor, such as for example resistor62, coupled between the eighth, node and the tenth node.

An embodiment may also include a clock generation circuit having a current driven oscillator and a bias circuit that both include resistors formed from a same type of semiconductor material.

Another embodiment may include a second operational transconductance amplifier, such as for example amplifier83, having an input coupled to an output of the symmetrical passive RC notch filter, a third operational transconductance amplifier, such as for example amplifier87, having an input coupled to an output of the second operational transconductance amplifier, and a fourth operational transconductance amplifier, such as for example amplifier86, having an input coupled to receive the input signal and an output coupled to the output of the second operational transconductance amplifier.

Another embodiment may also include a first compensation capacitor, such as for example capacitor92, coupled between a first input of the symmetrical passive RC notch filter and an output, such as for example output95, of the chopper stabilized amplifier;

a second compensation capacitor, such as for example capacitor91, coupled between the input and an output of the third operational transconductance amplifier, such as for example amplifier87; and

a third compensation capacitor, such as for example capacitor39, coupled between the first input, such as for example input35, and a second input, such as for example input36, of the symmetrical passive RC notch filter.

An embodiment may also include a forth compensation capacitor, such as for example one of capacitors37or38, coupled between a first input, such as for example one of inputs35or36, of the symmetrical passive AC notch filter and a ground node; and

a fifth compensation capacitor, such as for example the other one of capacitors37or38, coupled between a second input, such as for example the other one of inputs35or36, of the symmetrical passive RC notch filter and the ground node.

Another embodiment may also include a first compensation capacitor, such as for example capacitor92, coupled between a first output, such as for example output80, of the symmetrical passive RC notch filter and an output, such as for example output95, of the chopper-stabilized amplifier;

a second compensation capacitor, such as for example capacitor91, coupled between the output and an input of the third operational transconductance amplifier, such as for example amplifier87; and

a third compensation capacitor, such as for example capacitor39, coupled between outputs, such as for example outputs80and81, of the symmetrical passive RC notch filter.

An embodiment may also include, a forth compensation capacitor, such as for example one of capacitors37or38, coupled between a first output, such as for example one of outputs80or81, of the symmetrical passive RC notch filter and a ground node; and

a fifth compensation capacitor, such as for example the other one of capacitors37or38, coupled between a second output, such as for example the other one of outputs80or81, of the symmetrical passive RC notch filter and the ground node.

Those skilled in the art will, appreciate that a method of forming a chopper-stabilized amplifier may comprise:

configuring the chopper-stabilized amplifier, such as for example amplifier10, to chop a signal at a first frequency no produce a chopped signal; and

configuring a symmetrical passive RC notch filter, such as for example filter40, to have at least two cutoff frequencies including a first cutoff frequency and a second cutoff frequency wherein the first cutoff frequency is substantially near the first frequency and the second cutoff frequency is a harmonic of the first frequency.

An embodiment of the method may also include forming the second cutoff frequency to be a third harmonic of the first frequency.

Those skilled in the art will also appreciate that a method of forming a chopper-stabilized amplifier may comprise:

forming a symmetrical passive RC notch filter, such as for example filter40, to have two cutoff frequencies;

forming a first section, such as for example section57, of the symmetrical passive RC notch filter with a first plurality of signal paths including a first plurality of input signal paths, such as for example a plurality of payouts from input35, coupled to a first input, such as for example input35, of the first section and a second plurality of input signal paths, such as for example from input36, coupled to a second input, such as for example input36, of the first section;

configuring the first plurality of input signal paths to include a first plurality of resistors, such as for example resistors42and43, and a first plurality of capacitors, such as for example capacitors44and45; and

configuring the second plurality of input signal paths to include a second plurality of resistors, such as for example resistors50and51, and a second plurality of capacitors, such as for example resistors52and53.

An embodiment may include forming a second section, such as for example section58, of the symmetrical passive RC notch filter coupled to an output of the first section and forming the second section with a second plurality of signal paths including a third plurality of input signal paths coupled to a first output, such as for example output60, of the first section and a fourth plurality of input signal paths coupled to a second output, such as for example output61, of the first section.

Another embodiment may include configuring the third plurality of input signal paths to include a third plurality of resistors, such as for example resistors63and64, and a third plurality of capacitors, such as for example capacitor65and66; and

configuring the fourth plurality of input signal paths to include a fourth plurality of resistors, such as for example resistor72and73, and a fourth plurality of capacitors, such as for example capacitor74and75.

An embodiment may also include configuring the first plurality of resistors to include at least first and second series coupled resistors, such as for example resistors42and43, coupled between a first input, such as for example input35, of the symmetrical passive RC notch filter and a first output, such as for example output80, of the symmetrical passive RC notch filter; and

configuring the second plurality of resistors to include at least third and fourth series coupled resistors, such as for example resistors50and51, coupled between a second input, such as for example input36, of the symmetrical, passive RC notch filter and a second output, such as for example output81, of the symmetrical passive RC notch filter.

In another embodiment, the method may also include forming the symmetrical passive RC notch filter to be devoid of a clock signal used to operate elements of the symmetrical passive RC notch filter.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming a notch filter that has two cut-off frequencies. An embodiment includes forming amplifier10that includes filter40to operate with only two clock signals. In an embodiment, symmetrical passive notch filter is configured to include two cutoff frequencies. In an embodiment, a first cutoff frequency may be a chopper frequency and a second cutoff frequency may be a harmonic of the chopper frequency. The two cut-off frequencies may be correlated with the chopper frequency. An embodiment may include that the chopping frequency may be correlated with the cut-off frequencies by using a current-driven oscillator and a bias circuit that both use the same type of resistor as the resistors in the filter.

While the subject matter of the descriptions are described with specific preferred embodiments and example embodiments, the foregoing drawings and descriptions thereof depict only typical and examples of embodiments of the subject matter and are not therefore to be considered to be limiting of its scope, it is evident that many alternatives and variations will be apparent to those skilled in the art. Although compensation capacitors37-39and92are illustrated as connected to inputs35and36of filter40, these compensation capacitors may be connected to outputs80and81in other embodiments. In some embodiments, one or more of capacitors37-39or90may be omitted. Filter40may be used in other applications other than to filter the output of a chopper amplifier. For example, filter40may be used to filter signals received from portions of a switching voltage regulator.

As the claims hereinafter reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the hereinafter expressed claims are hereby expressly incorporated into this Description portion of the Application, with each claim standing on its own as a separate embodiment of an invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art.