Memory controller and method of operating the same

A memory controller configured to control a memory device may include: a metadata storage configured to store a plurality of metadata segments; a metadata updater configured to sequentially update the metadata segments; a backup data storage configured to store at least one original metadata segment (a metadata segment existing before being updated) among the metadata segments; a metadata backup circuit configured to store, before a selected metadata segment among the metadata segments is updated, an original metadata segment of the selected metadata segment in the backup data storage; and a metadata restorer configured to generate storage inhibit information indicating whether storing data in the memory device is inhibited based on a residual storage capacity of the memory device, and store, in the metadata storage, the original metadata segment stored in the backup data storage in response to the storage inhibit information while the metadata segments are updated.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims priority to and benefits of the Korean patent application number 10-2019-0110527, filed on Sep. 6, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Various embodiments of the disclosed technology generally relate to an electronic device including a memory controller and a method of operating the memory controller.

BACKGROUND

A storage device is a semiconductor device which stores data under control of a host device such as a computer or a smartphone. The storage device may include a memory device configured to store data, and a memory controller configured to control the memory device. Memory devices are generally classified into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device that can retain its data only when power is supplied thereto. Thus, such a volatile memory device loses its data in the absence of power. Examples of a volatile memory device include a static random access memory (SRAM), and a dynamic random access memory (DRAM).

A nonvolatile memory device is a memory device that can retain its data even in the absence of power. Examples of a nonvolatile memory device include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory.

SUMMARY

Various embodiments of the disclosed technology relate to a memory controller having improved metadata management performance, and a method of operating the memory controller.

In one aspect, a memory controller configured to control a memory device is provided to include: a metadata storage configured to store a first metadata segment and a second metadata segment; a metadata updater communicatively coupled to the metadata storage and configured to transmit an indication to update the first metadata segment and update the first metadata segment stored in the metadata storage to an updated first metadata segment; a metadata backup circuit configured to receive from the metadata updater the indication and control copying of the first metadata segment in response to the indication; a backup data storage communicatively coupled to the metadata backup circuit and configured to store the first metadata segment based on the indication; and a metadata restorer configured to generate storage inhibit information indicating that storing data in the memory device is inhibited, and replace the updated first metadata segment stored in the backup data storage with the first metadata segment in response to the storage inhibit information.

In another aspect, a method is provided for operating a memory controller including a metadata storage configured to store a first metadata segment and a second metadata segment, and a backup data storage configured to store backup data of at least one of the first metadata segment or the second metadata segment. The method includes: storing, in response to a selection of the first metadata segment as being updated, the first metadata segment in the backup data storage; updating the first metadata segment to an updated first metadata segment such that the metadata storage stores the updated first metadata segment instead of the first metadata segment; and replacing, in response to storage inhibit information indicating that storing data in the memory device is inhibited, the updated first metadata segment stored in the metadata storage with the first metadata segment.

In another aspect, a memory controller is provided to include: a metadata storage configured to store a plurality of metadata segments; and a metadata restorer configured to back up a selected target segment to be updated among the plurality of metadata segments before the target segment is updated to an updated target segment, and restore the selected target segment instead of the updated target segment in the metadata storage based on a residual storage capacity of the memory device.

DETAILED DESCRIPTION

Specific structural or functional descriptions in the embodiments of the disclosed technology introduced in this specification or application are only for description of the embodiments. The descriptions should not be construed as being limited to the embodiments described in the specification or application.

Various embodiments of the disclosed technology will now be described hereinafter with reference to the accompanying drawings.

FIG. 1is a block diagram illustrating an example of a storage device based on some implementations of the disclosed technology.

Referring toFIG. 1, the storage device50may include a memory device100and a memory controller200configured to control one or more operations of the memory device100.

The storage device50may be configured to store and retrieve data according to requests from a host300such as a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV, a tablet PC, or an in-vehicle infotainment system.

The storage device50may be implemented as any one of various kinds of storage devices depending on a host interface, which is a communication interface between the host300and the storage device50. For example, the storage device50may be configured of any one of various kinds of storage devices such as an SSD, MMC, eMMC, RS-MMC, or micro-MMC type multimedia card, an SD, mini-SD, micro-SD type secure digital card, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI-express (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

The storage device50may be manufactured in the form of any one of various package types. For instance, the storage device50may be manufactured in the form of any one of various package types such as a package on package (POP) type, a system in package (SIP) type, a system on chip (SOC) type, a multi-chip package (MCP) type, a chip on board (COB) type, a wafer-level fabricated package (WFP) type, or a wafer-level stack package (WSP) type.

The memory device100may provide a storage space where data to be processed and/or instructions to be executed are stored. The memory device100may include the logic needed to read from and write to the memory device100and be operated under control of the memory controller200. The memory device100may include a memory cell array including a plurality of memory cells which are configured to store data therein.

Each of the memory cells may be configured in various manners to store data. In some implementations, the memory cells can store a single bit or more bits of information. In some implementations, the memory cells may be implemented as a single level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of pages, and each page corresponds to a plurality of memory cells. In an embodiment, read and program (write) operations are performed on a page basis, and erase operations are performed on a block basis.

The memory controller200can access the memory device100based on request from the user/host by providing command/address signals to the memory controller200. In some implementations, the memory device100is configured to receive, from the memory controller200, a command and an address in which the command is performed or executed. The memory device100may access an area of the memory cell array that is selected by the received address. The memory device100which has accessed the selected area may perform an operation in the area identified by the address based on the received command requested by the user/host.

For example, the memory device100may perform a write (program) operation, a read operation, or an erase operation. During the program operation, data is written to the area (e.g., memory cell area) of the memory device100, which is identified by the address. During the read operation, data is read from the area of the memory device100, which is identified by the address. During the erase operation, data is erased from the area of the memory device100, which is identified by the address.

The memory controller200may control the overall operation of the storage device50.

When power is applied to the storage device50, the memory controller200may execute firmware (FW). The firmware FW may include a host interface layer (HIL) configured to receive a request input from the host300or output a response to the host300, a flash translation layer (FTL) configured to manage an operation between an interface of the host300and an interface of the memory device100, and a flash interface layer (FIL) configured to provide a command to the memory device100or receive a response from the memory device100. In an implementation, a flash translation layer (FTL) may be situated in the memory controller200to implement logical-to-physical mapping, garbage collection, wear leveling management, and bad block management. For example, the FTL may provide an interface between a host interface layer and a flash interface layer.

In an embodiment, the memory controller200may receive data and a logical address (LA) from the host300, and translate the LA into a physical address (PA) indicating where in the memory device100the memory cells to write data to or read from are. The logical address may be a logical block address (LBA). The physical address may be a physical block address (PBA).

The memory controller200may control the memory device100to perform a program operation, a read operation, or an erase operation based on a request provided from the host300. During the program operation, the memory controller200may provide a program command, a PBA, and data to the memory device100. During the read operation, the memory controller200may provide a read command and a PBA to the memory device100. During the erase operation, the memory controller200may provide an erase command and a PBA to the memory device100.

In an embodiment, the memory controller200may autonomously control the memory device100to perform a program operation, a read operation, or an erase operation regardless of a request from the host300. For example, the memory controller200may control the memory device100to perform a program operation, a read operation, or an erase operation which is used to perform background operations such as a wear leveling operation, a garbage collection operation, or a read reclaim operation. The term “garbage collection” as used herein may refer to a form of memory management, in which a garbage collector attempts to reclaim (garbage) memory that is occupied by objects that are no longer in use. The wear leveling indicates techniques for prolonging lifetime of erasable storage devices.

In an embodiment of the disclosed technology, the memory controller200may include a map data storage201, and a metadata storage202.

The map data storage201may store map data indicating a relationship between a logical address and a physical address. The map data storage201may be included in a nonvolatile memory device. For example, the map data storage201may be included in either a static random access memory (SRAM) or a dynamic random access memory (DRAM). Therefore, the memory controller200may store map data in the memory device100which is a nonvolatile memory device. When map data is updated, the memory controller200may perform a map update operation to store the updated map data in the memory device100.

When power is supplied to the storage device50, the memory controller200may read map data stored in the memory device100and store the read map data in the map data storage201. The memory controller200may perform, using the map data, operations requested by the host300.

In an embodiment, the memory controller200may load some of the map data from the memory device100to the map data storage201.

When the logical address received from the host is not included in the map data stored in the map data storage201, the memory controller200may load another map data from the memory device100to the map data storage201.

The memory controller200may update the map data and store the updated map data in the memory device100. The map data stored in the map data storage201may be updated based on a request from the host300or a background operation. For example, if the physical address corresponding to the logical address is changed through a background operation such as a garbage collection operation, a read reclaim operation, or a wear leveling operation, the memory controller200may store the updated map data in the memory device100. If an unmap request for releasing the relationship between the logical address and the physical address is input from the host300, the relationship between the logical address and the physical address may be released. When the relationship between the logical address and the physical address is released and the logical address does not have a corresponding physical address mapped, the memory controller200may assign a predetermined trim data as the physical address corresponding to the unmapped logical address. The memory controller200may control the memory device100to store the updated map data in the memory device100.

The metadata storage202may store metadata. The metadata may be used to retain or maintain the performance or capabilities of the storage device50. The metadata may be data related with the map data. The metadata may be changed as well as the map data is updated. For example, the metadata may include L1map data that indicates a position where in the memory device100map data is stored, or L0map data that indicates a position where in the memory device100the L1map data is stored. In an embodiment, the metadata may include at least one of i) valid page bit map data indicating whether data stored in pages included in a memory block included in the memory device100is valid, ii) valid page count data indicating the number of valid page included in the memory block included in the memory device, or iii) group block address data indicating physical addresses of memory blocks that form a super block.

In an embodiment, the metadata may include at least one of read count data which is information about the number of read requests transmitted to a memory block included in the memory device100, an erase count data which is information about the number of erase operations performed on the memory block, or hot/cold metadata indicating whether stored data is hot data or cold data.

The metadata may be stored in the memory device100. The memory controller200may update the metadata and store the updated metadata in the memory device100.

If power is applied to the storage device50, the memory controller200may load the metadata from the memory device100to the metadata storage202. The memory controller200may mange the performance or capabilities of the memory device100using the metadata.

Updating the map data may cause updating of the metadata. Thus, if the map data is updated, the metadata may be updated based on a relationship between a logical address and a physical address, the relationship being indicated by the updated map data. For example, when a physical address corresponding to a logical address is changed, at least one among valid page bit map data, valid page count data, group block address data, read count data, erase count data, or hot cold metadata, which can be included in the metadata, may be updated.

Alternatively, when the updated map data is stored in the memory device100, the L1map data or the L0map data may be updated depending on a position wherein in the memory device100the updated map data is stored.

In an embodiment, the metadata storage202may be included in a volatile memory device. For example, the metadata storage202may be storage space included in the volatile memory device. For example, the metadata storage202may be included in either a static random access memory (SRAM) or a dynamic random access memory (DRAM). Therefore, the memory controller200may store map data in the memory device100which is a nonvolatile memory device.

The host300may communicate with the storage device50using at least one of various communication methods such as universal serial bus (USB), serial AT attachment (SATA), serial attached SCSI (SAS), high speed interchip (HSIC), small computer system interface (SCSI), peripheral component interconnection (PCI), PCI express (PCIe), nonvolatile memory express (NVMe), universal flash storage (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM), and load reduced DIMM (LRDIMM) communication methods.

FIG. 2is a diagram illustrating an operation of updating map data and metadata.

Referring toFIG. 2, the memory controller200may update map data stored in the map data storage201. The memory controller200may store the updated map data in the memory device100. The memory controller200may update the metadata after the map data has been updated or the updated map data has been stored in the memory device.

The memory controller200may sequentially update a plurality of pieces of metadata. For example, first metadata, second metadata, and third metadata may be sequentially updated.

In an embodiment, metadata to be subsequently updated may be updated after preceding updated metadata has been stored in the memory device100. For example, the second metadata may be updated after the first metadata has been stored in the memory device100. The third metadata may be updated after the second metadata has been stored in the memory device100.

In an embodiment, the first metadata, the second metadata, and the third metadata may be updated based on the updated map data. The first metadata, the second metadata, and the third metadata each may be data which is changed depending on updating the map data. For example, the metadata may include at least one of i) L1map data indicating a position at which the map data is stored in the memory device100, ii) L0map data indicating a position at which the L1map data is stored in the memory device100, iii) valid page bit map data indicating whether data stored in pages included in a memory block included in the memory device100is valid, iv) valid page count data indicating the number of valid pages included in the memory block included in the memory device100, v) group block address data indicating physical addresses of memory blocks that form a super block, vi) read count data that is information about the number of read requests transmitted to the memory block included in the memory device100, vii) erase count data that is information about the number of erase operations performed on the memory block, or viii) hot/cold metadata indicating whether the stored data is hot data or cold data. In an embodiment, the first metadata, the second metadata, and the third metadata may be updated based on a position of an area in which the updated map data is stored in the memory device100. For example, the first metadata may be L1map data indicating a position at which the map data is stored in the memory device100. The second metadata may be L0map data indicating a position at which the L1map data is stored in the memory device100.

In an embodiment, the first metadata, the second metadata, and the third metadata may be different from one another.

FIG. 3is a diagram illustrating a case where only some of metadata is updated.

Referring toFIG. 3, after the first metadata and the second metadata are sequentially updated, storing data in the memory device100may be inhibited. The case where storing data in the memory device is inhibited may include the case where the capacity with which data can be stored in the memory device100is a reference value or less, the case where the memory controller200receives a storage inhibit signal from the memory device100, or the case where the memory controller200receives a storage inhibit command from the host.

In an embodiment, metadata to be subsequently updated may be updated after previously updated metadata has been stored in the memory device100. For example, the second metadata may be updated after the first metadata has been stored in the memory device100. The third metadata may be updated after the second metadata has been stored in the memory device100.

Therefore, when a storage operation is inhibited, at least one of the first metadata, the second metadata, and the third metadata may not be updated. For example, when a data storage inhibit event occurs after the updated first metadata and the updated second metadata have been stored in the memory device100, the third metadata cannot be stored in the memory device100even if the third metadata is updated. Hence, the memory controller200may not update the third metadata.

Because the third metadata is not updated, the updating operation may be suspended when the updated first metadata, the updated second metadata, and the third metadata have been stored in the metadata storage202. Since the memory controller200performs, using metadata stored in the metadata storage202, an operation corresponding to a request from the host or a background operation, the operation or the background operation may be abnormally performed if only some of metadata has been updated.

FIGS. 4A and 4Bare diagram showing two cases where metadata is stored in a metadata storage.

Referring toFIG. 4Awhere all metadata has been updated, updated first metadata, updated second metadata, and updated third metadata may be stored in the metadata storage202.

InFIG. 4B, the first metadata and the second metadata have been updated but the third metadata has not been updated. Thus, the updated first metadata, the updated second metadata, and the third metadata may be stored in the metadata storage202.

The updated first metadata and the updated second metadata may be related with updated map data. The third metadata may be related with original map data (previous map data existing before the update). Therefore, in the case where the memory controller200performs, using metadata stored in the metadata storage202, an operation corresponding to a request from the host or a background operation, the operation or the background operation may be abnormally performed.

FIG. 5is a block diagram for describing the memory controller200in accordance with an embodiment.

Referring toFIG. 5, the memory controller200may include a map data manager210, a metadata manager220, a map data storage201, a metadata storage202, and a backup data storage203.

The map data manager210may receive a request from the host300and transmit map data update information to the metadata manager220. The map data update information may be or include information indicating that map data stored in the map data storage201is updated, or information indicating that the updated map data is stored in the memory device100. The map data update information may include an updated relationship between a logical address and a physical address, and/or a position information at which the updated map data is stored in the memory device100.

The map data manager210may include a map updater211. The map updater211may update map data stored in the map data storage201, based on a request from the host300or a background operation. For example, if data stored in a first area indicated by a logical address is transferred to a second area through a background operation, the map updater211may update the map data so that the logical address corresponds to a physical address of the second area. Alternatively, if an unmap request for releasing the relationship between the logical address and the physical address is input or received from the host300, the relationship between the logical address and the physical address may be released.

The metadata manager220may include a metadata updater221and a metadata restorer222. The metadata manager220may receive map data update information from the map data manager210and manage the metadata.

In some implementations, the metadata updater221may update metadata stored in the metadata storage202based on the updated map data. The metadata updater221may control the memory device100to store the updated metadata in the memory device100. The metadata restorer222may back up metadata to be updated in the backup data storage203. For example, among first to third metadata stored in the metadata storage202, a first metadata is to be updated to an updated first metadata, the metadata restorer222may store the first metadata in the backup data storage203. The metadata restorer222may sense or detect an event in which an operation of storing data in the memory device100is inhibited, and restore the metadata backed up in the backup data storage203to the metadata storage202in the case of the event. For example, when the event that storing data in the memory device100is habited, the metadata restorer222controls the metadata storage202which already stores the updated first metadata instead of the first metadata to replace the updated first metadata with the first metadata that existed in the metadata storage202before the update of the first metadata.

The backup data storage203may be or include a memory which is used to store original metadata existing before being updated. The backup data storage203may be a storage space included in a nonvolatile memory device. For example, the backup data storage203may be included in either a static random access memory (SRAM) or a dynamic random access memory (DRAM).

Referring toFIG. 6, the first metadata, the second metadata, and the third metadata may be stored in the metadata storage202. The metadata updater221may receive map data update information from the map data manager210, and update the metadata stored in the metadata storage202based on the updated map data. For example, the metadata updater221may load metadata stored in the metadata storage202on a buffer (not illustrated) included in the metadata updater221, update the metadata based on the updated map data, and store the updated metadata in the metadata storage202. The metadata updater221may sequentially update metadata stored in the metadata storage202. For example, the metadata updater221may first update the first metadata among the first metadata, the second metadata, and the third metadata. The metadata updater221may transmit update start information to the metadata restorer222before the first metadata is updated. The update start information may include information indicating a position at which the first metadata is stored in the metadata storage202. The metadata updater221may store the updated first metadata in the memory device100.

The metadata restorer222may receive the update start information and back up the first metadata. For example, a metadata backup circuit223may back up the first metadata from the metadata storage202in the backup data storage203, based on the information indicating the position at which the first metadata is stored in the metadata storage202.

The metadata updater221may transmit update complete information to the metadata restorer222after the metadata has been updated. As the result of the completion of the update that is performed for the first metadata among first to third metadata, the metadata storage202stores an updated first metadata instead of the first metadata. The update complete information may include information indicating that updating the metadata has been completed. The update complete information may include information that the metadata has been stored in the memory device100.

The metadata restorer222may receive the update complete information and restore the metadata. For example, the metadata restorer224may sense an event in which storing data in the memory device100is inhibited, and generate storage inhibit information in response to the sensing of such event. The metadata restorer224may restore the metadata stored in the backup data storage203to the metadata storage202in response to the storage inhibit information. For example, the metadata restorer224may restore the first metadata stored in the backup data storage203to the metadata storage202in response to the storage inhibit information. As the result of the restoration, the metadata storage202stores the first metadata instead of the updated first metadata.

The storage inhibit information may include information indicating that the memory device is used only for read. The storage inhibit information may include information indicating that the storage capacity with which data is stored in the memory device100is a reference value or less, information indicating that the memory controller200has received the storage inhibit signal from the memory device100, or information indicating that the memory controller200has received a storage inhibit command from the host. In an embodiment, the metadata restorer224may generate storage inhibit information when the number of free blocks in the memory device100is a threshold number or less.

When the metadata restorer224senses the event in which the storing data in the memory device100is inhibited, the metadata restorer224may transmit storage inhibit information to the metadata updater221. The metadata updater221may receive storage inhibit information and suspend updating the metadata. For example, an operation of updating the second metadata and the third metadata that have not been updated yet but been stored in the metadata storage202may be suspended.

The metadata restorer224may generate update continue information based on a result of the sensing that indicates that storing data in the memory device100is not inhibited, and transmit the update continue information to the metadata updater221. The update continue information may include information indicating that the operation of updating metadata that has not yet been updated among the metadata stored in the metadata storage202needs to be continuously performed.

The metadata updater221may receive the update continue information, and update metadata that has not yet been updated among the metadata stored in the metadata storage202. For example, since the first metadata stored in the metadata storage202has been updated, the second metadata that has not been updated may be updated.

The metadata updater221may transmit update start information to the metadata restorer222before the second metadata is updated.

The metadata backup circuit223may back up the second metadata stored in the metadata storage202to the backup data storage203, in the same manner as that of the operation of backing up the first metadata.

The metadata updater221may transmit update complete information to the metadata restorer222after the second metadata has been updated. As the result of the completion of the update that is performed for the second metadata, the metadata storage202stores an updated second metadata instead of the second metadata.

The metadata restorer224that has received the update complete information may sense an event in which storing data in the memory device100is inhibited, and generate storage inhibit information in response to the sensing of such event. The metadata restorer224may restore the metadata stored in the backup data storage203to the metadata storage202in response to the storage inhibit information. For example, the metadata restorer224may restore the first metadata and the second metadata stored in the backup data storage203to the metadata storage202in response to the storage inhibit information. As the result of the restoration, the metadata storage202stores the second metadata instead of the updated second metadata.

Since the updated metadata stored in the metadata storage202is restored to the original metadata (the metadata exiting before being updated), an event in which only some of the metadata stored in the metadata storage202is updated can be prevented from occurring.

FIG. 7is a diagram for describing a process of restoring the first metadata.

Referring toFIG. 7, before the metadata is updated, the first metadata, the second metadata, and the third metadata may be stored in the metadata storage202, and no metadata may be stored in the backup data storage203. Although for the sake of explanation,FIG. 7shows only three metadata stored in the metadata storage202, the number of stored metadata can be changed.

The metadata backup circuit223may back up the first metadata stored in the metadata storage202to the backup data storage203in response to the update start information received form the metadata updater221. After the first metadata has been backed up, the metadata storage202stores the first metadata, the second metadata, and the third metadata, and the backup data storage stores the first metadata.

The metadata updater221may update the first metadata stored in the metadata storage202based on the updated map data. The metadata updater221may store the updated first metadata in the memory device100. After the first metadata has been updated, the metadata storage202stores the updated first metadata, the second metadata, and the third metadata, and the backup data storage203stores the first metadata.

After the update complete information has been received from the metadata updater221, the metadata restorer224may sense an event in which storing data in the memory device100is inhibited, and generate storage inhibit information in response to the sensing of the event.

For example, the metadata restorer224may sense an event in which the number of free blocks included in the memory device100is a threshold number or more, an event in which the memory controller200receives a storage inhibit signal from the memory device100, or an event in which the memory controller200receives a storage inhibit command from the host. The metadata restorer224may transmit the storage inhibit information to the metadata updater221.

In response to the storage inhibit information, the metadata restorer224may restore the updated first metadata stored in the metadata storage202to the first metadata using the first metadata backed up in the backup data storage203. After the first metadata has been restored, the metadata storage202stores the first metadata, the second metadata, and the third metadata, and the backup data storage203stores the first metadata.

By the restoration of the updated metadata to the original metadata that existed before the update, the problem in which only some of the metadata stored in the metadata storage202is updated while some other of the metadata stored in the metadata storage200is not updated can be solved. Thus, the memory controller200may normally perform an operation corresponding to a request from the host or a background operation.

FIG. 8is a diagram for describing a process of restoring the first metadata and the second metadata.

Referring toFIG. 8, the metadata updater22may update the first metadata and the second metadata. The process of updating the first metadata will be omitted because it has been described with reference toFIG. 7. Hereinafter, a process of updating the second metadata will be described.

The metadata restorer224that receives update complete information from the metadata updater221that has updated the first metadata may sense an event in which storing data in the memory device100is inhibited. The metadata restorer224may generate update continue information based on a result of the sensing. The update continue information may include information indicating that the operation of updating metadata that has not yet been updated among the metadata stored in the metadata storage202needs to be continuously performed. The update continue information may include information indicating that additional data can be stored in the memory device100. The metadata restorer224may transmit update continue information to the metadata updater221.

The metadata updater221may receive the update continue information, and update metadata that has not yet been updated among the metadata stored in the metadata storage202. For example, the second metadata that has not been updated among the metadata stored in the metadata storage202may be updated based on the updated map data. The metadata updater221may update the second metadata and transmit update complete information to the metadata restorer222. As the result of the completion of the update of the second metadata, the metadata updater221may store the updated second metadata in the memory device100. After the second metadata has been updated, the metadata storage202stores the updated first metadata, the updated second metadata, and the third metadata and the backup data storage203stores the first metadata and the second metadata.

In response to the update complete information received from the metadata updater221, the metadata restorer224may sense an event in which storing data in the memory device100is inhibited, and generate storage inhibit information depending on a result of the sensing.

For example, the metadata restorer224may sense an event in which the number of free blocks included in the memory device100is a threshold number or more, an event in which the memory controller200receives a storage inhibit signal from the memory device100, or an event in which the memory controller200receives a storage inhibit command from the host. The metadata restorer224may transmit the storage inhibit information to the metadata updater221.

In response to the storage inhibit information, the metadata restorer224may restore the updated first metadata and the updated second metadata stored in the metadata storage202to the first metadata and the second metadata, respectively, using the first metadata and the second metadata backed up in the backup data storage203. After the first metadata and the second metadata have been restored, the metadata storage202stores the first metadata, the second metadata, and the third metadata may be in a state of having been stored in, and the backup data storage203stores the first metadata and the second metadata.

Since the problem in which only some of the metadata stored in the metadata storage202is updated can be solved by the restoration, the memory controller200may normally perform an operation corresponding to a request from the host or a background operation.

FIG. 9is a flowchart illustrating an operation of updating, by the memory controller, selected metadata.

Referring toFIG. 9, at step S901, the memory controller may update map data. The memory controller200may update a relationship between a logical address and a physical address, the relationship being indicated by the map data, based on a request from the host or a background operation.

At step S903, the memory controller200may store, in the backup data storage203, original metadata of selected metadata among pieces of metadata. For example, the memory controller200may store, in the backup data storage203, the first metadata among the first metadata, the second metadata, and the third metadata that are stored in the metadata storage202.

At step S905, the memory controller200may update the selected metadata. The memory controller200may update the selected metadata based on the updated map data. For example, the memory controller200may update the first metadata based on the updated map data.

At step S907, the memory controller200may sense an event in which storing data in the memory device100is inhibited. For example, the memory controller200may sense an event in which the number of free blocks included in the memory device100is a threshold number or more, an event in which the memory controller200receives a storage inhibit signal from the memory device100, or an event in which the memory controller200receives a storage inhibit command from the host, and may generate storage inhibit information based on a result of the sensing.

At step S909, the memory controller200may store the original metadata (the metadata existing before being updated) stored in the backup data storage203in the metadata storage202. For example, in response to the storage inhibit information, the memory controller200may restore the updated first metadata stored in the metadata storage202to the first metadata using the first metadata backed up in the backup data storage203.

FIG. 10is a flowchart illustrating an operation of updating metadata by the memory controller200.

Referring toFIG. 10, at step S1001, the memory controller200may update map data stored in the map data storage. The memory controller200may store the updated map data in the memory device100.

The memory controller200may sequentially update Max pieces of metadata based on the updated map data, wherein Max is a natural number indicating a number of metadata to be updated. At step S1003, the memory controller200may set K to 1 (i.e., K=1) and first update the first metadata.

At step S1005, the memory controller200may back up the first metadata in the backup data storage203. The memory controller200may back up the original first metadata in the backup data storage203before updating the first metadata. The original first metadata corresponds to the first metadata before the update of the first metadata.

At step S1007, the memory controller200may update the first metadata based on the updated map data. In an embodiment, the memory controller200may update the first metadata based on a position of an area in which the updated map data is stored in the memory device100. The memory controller200may store the updated first metadata in the memory device100.

At step S1009, the memory controller200may sense an event in which storing data in the memory device100is inhibited. For example, the memory controller200may sense an event in which the number of free blocks included in the memory device100is a threshold number or more, an event in which the memory controller200receives a storage inhibit signal from the memory device100, or an event in which the memory controller200receives a storage inhibit command from the host, and may generate storage inhibit information or update continue information based on a result of the sensing.

For example, if an event in which the number of free blocks included in the memory device100is a threshold number or more, an event in which the memory controller200receives a storage inhibit signal from the memory device100, or an event in which the memory controller200receives a storage inhibit command from the host is sensed, storage inhibit information may be generated. The update continue information may include information indicating that the operation of updating metadata that has not yet been updated among the metadata stored in the metadata storage202is required to be continuously performed. The update continue information may include information indicating that additional data can be stored in the memory device100.

The memory controller200may perform step S1015in response to the storage inhibit information, and perform step S1011in response to the update continue information.

At step S1015, the memory controller200may restore the first metadata backed up in the backup data storage203to the metadata storage202. The memory controller200may restore the first metadata in response to the storage inhibit information, and suspend updating the second metadata and the third metadata that have not yet been updated among pieces of metadata stored in the metadata storage202. Thus, the metadata storage202stores the first metadata (instead of the updated first metadata), the second metadata and the third metadata.

At step S1011, the memory controller200may determine whether the updated metadata is last metadata to be updated. For example, the memory controller200may determine whether the currently updated metadata is a Max-th metadata. If the currently updated metadata is not the Max-th metadata, the memory controller200increases K by 1 at step S1013. Therefore, at step S1005, the second metadata that is metadata to be updated in a subsequent turn may be backed up to the backup data storage202

Steps S1005to S1009for the second metadata are the same as steps S1005and S1009for the first metadata; therefore repetitive explanation thereof will be omitted.

At step S1015for the second metadata, the memory controller200may restore the first and the second metadata backed up in the backup data storage203to the metadata storage, in response to the storage inhibit information. The memory controller200may restore the first metadata and the second metadata in response to the storage inhibit information, and suspend updating the third metadata that has not yet been updated among the pieces of metadata stored in the metadata storage202. Thus, the metadata storage202stores the first metadata (instead of the updated first metadata), the second metadata (instead of the updated second metadata), and the third metadata.

At step S1011for the second metadata, the memory controller200may determine whether the second metadata is last metadata to be updated. For example, the memory controller200may determine whether the second metadata is the Max-th metadata.

In the case where the second metadata is the Max-th metadata, the operation of updating the metadata may be terminated. In the case where the second metadata is not the Max-th metadata, the memory controller200may increase K by 1, at step S1013. At step S1005, the memory controller200may back up, in the backup data storage203, the third metadata that is metadata to be subsequently updated

Since the problem in which only some of the metadata stored in the metadata storage202is updated may be solved by the restoration, the memory controller200may normally perform an operation corresponding to a request from the host or a background operation.

FIG. 11is a diagram for describing the type of metadata.

Referring toFIG. 11, the metadata may include at least one among L1map data, L0map data, valid page bitmap data, valid page count data, group block address data, erase count data, read count data, or hot cold metadata. The metadata stored in the metadata storage202may be stored in the memory device100.

The L1map data may include information indicating a position at which the map data is stored in the memory device100. For example, in the case where the map data is dispersed and stored in the memory device100, the L1map data may include physical addresses of dispersed areas.

The L0map data may include information indicating a position at which the L1map data is stored in the memory device100. The L0map data may be generated based on the L1map data.

The valid page bit map data may indicate whether data stored in pages included in a memory block included in the memory device100is valid. For example, a page in which valid data is stored may be bit map data indicated as 1, and a page in which invalid data is stored may be bit map data indicated as 0.

The valid page count data may indicate the number of valid pages included in a memory block included in the memory device100. For example, the valid page count data may indicate the number of valid pages among pages corresponding to respective physical block addresses (PBAs).

Alternatively, the valid page count data may indicate the number of valid pages among pages corresponding to respective logical block addresses (LBAs). The valid page count data may be generated based on the valid page bit map data.

The group block address data may include information indicating physical addresses of memory blocks that form a super block. For example, the group block address may include information indicating respective physical addresses of memory blocks that are disposed in different planes included in the memory device100.

The erase count data may be information about the number of times erase operations have been performed in a memory block included in the memory device100. For instance, in the case where data stored in a victim block is erased by a garbage collection, an erase count of the victim block may be increased.

The read count data may be information about the number of times read requests have been transmitted to a memory block included in the memory device100. For example, in the case where a read operation is performed on the memory block in response to a request from the host or by a background operation, the read count may be increased. The read count data may be used for an operation such as a read reclaim operation which is performed based on a read count.

The hot/cold metadata may indicate whether stored data is hot data or cold data. For example, the hot/cold metadata may be managed by at least recently used (LRU) algorithm

FIG. 12is a diagram for describing the memory device100in accordance with an embodiment of the present disclosure.

Referring toFIG. 12, the memory device100may include a memory cell array1210, a peripheral circuit1220, and a control logic1230.

The memory cell array1210may include a plurality of memory blocks BLK1to BLKz. The plurality of memory blocks BLK1to BLKz are coupled to a row decoder1221through row lines RL. The plurality of memory blocks BLK1to BLKz may be coupled to a page buffer group1223through bit lines BL1to BLn. Each of the memory blocks BLK1to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as one page. Hence, each memory block may include a plurality of pages.

The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

Each of the memory cells included in the memory cell array1210may be formed of a single-level cell (SLC) capable of storing a single data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

The peripheral circuit1220may perform a program operation, a read operation, or an erase operation on a selected area of the memory cell array1210under control of the control logic1230. The peripheral circuit1220may drive the memory cell array1210. For example, the peripheral circuit1220may apply various operating voltages to the row lines RL and the bit lines BL1to BLn or discharge the applied voltages, under control of the control logic1230.

The peripheral circuit1220may include the row decoder1221, a voltage generator1222, the page buffer group1223, a column decoder1224, and an input/output circuit1225.

The row decoder1221is coupled to the memory cell array1210through the row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe select line.

The row decoder1221may operate under control of the control logic1230. The row decoder1221may receive a row address ADDR from the control logic1230.

The row decoder1221may decode the row address RADD. The row decoder1221may select at least one memory block of the memory blocks BLK1to BLKz in response to the decoded address. The row decoder1221may select at least one word line WL of the selected memory block in response to the decoded address so that voltages generated from the voltage generator1222are applied to the at least one word line WL.

For example, during a program operation, the row decoder1221may apply a program voltage to a selected word line and apply a program pass voltage having a level lower than that of the program voltage to unselected word lines. During a program verify operation, the row decoder1221may apply a verify voltage to a selected word line and apply a verify pass voltage higher than the verify voltage to unselected word lines. During a read operation, the row decoder1221may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.

In an embodiment, an erase operation of the memory device100may be performed on a memory block basis. During an erase operation, the row decoder1221may select one memory block in response to a decoded address. During the erase operation, the row decoder1221may apply a ground voltage to word lines coupled to the selected memory block.

The voltage generator1222may operate under control of the control logic1230. The voltage generator1222may generate a plurality of voltages using an external supply voltage supplied to the memory device100. For example, the voltage generator1222may generate various operating voltages Vop to be used for a program operation, a read operation, and an erase operation in response to an operating signal OPSIG. For example, the voltage generator1222may generate a program voltage, a verify voltage, a pass voltage, a read voltage, an erase voltage, and so forth under control of the control logic1230.

In an embodiment, the voltage generator1222may generate an internal supply voltage by regulating the external supply voltage. The internal supply voltage generated from the voltage generator1222may be used as an operating voltage of the memory device100.

In an embodiment, the voltage generator1222may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

For example, the voltage generator1222may include a plurality of pumping capacitors for receiving the internal supply voltage and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under control of the control logic1230.

The generated voltages may be supplied to the memory cell array1210by the row decoder1221.

The page buffer group1223may include first to n-th page buffers PB1to PBn. The first to n-th page buffers PB1to PBn are coupled to the memory cell array1210through the first to n-th bit lines BL1to BLn, respectively. The first to n-th page buffers PB1to PBn may operate under control of the control logic1230. For example, the first to n-th page buffers PB1to PBn may operate in response to page buffer control signals PBSIGNALS. For instance, the first to n-th page buffers PB1to PBn may temporarily store data received through the first to n-th bit lines BL1to BLn, or sense voltages or currents of the first to n-th bit lines BL1to BLn during a read operation or a verify operation.

For example, during a program operation, the first to n-th page buffers PB1to PBn may transmit data DATA received through the data input/output circuit1225to selected memory cells through the first to n-th bit lines BL1to BLn when a program pulse is applied to a selected word line.

The memory cells in the selected page are programmed based on the transmitted data DATA. A memory cell coupled to a bit line to which a program enable voltage (e.g. a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of a memory cell coupled to a bit line to which a program inhibit voltage (for example, a supply voltage) is applied may be retained. During a program verify operation, the first to n-th page buffers PB1to PBn may read page data from selected memory cells through the first to n-th bit lines BL1to BLn.

During a read operation, the first to n-th page buffers PB1to PBn may read data DATA from memory cells of a selected page through the first to n-th bit lines BL1to BLn, and output the read data DATA to the data input/output circuit1224under control of the column decoder1225.

During an erase operation, the first to n-th page buffers PB1to PBn may float the first to n-th bit lines BL1to BLn.

The column decoder1224may transmit data between the input/output circuit1225and the page buffer group1223in response to a column address CADD. For example, the column decoder1224may exchange data with the first to n-th page buffers PB1to PBn through data lines DL or exchange data with the input/output circuit1225through column lines CL.

The input/output circuit1225may transmit, to the control logic1230, a command CMD or an address ADDR received from the memory controller200described with reference toFIG. 1, or may exchange data DATA with the column decoder1224.

During a read operation or a verify operation, the sensing circuit1226may generate a reference current in response to an enable bit signal VRYBIT, and may compare a sensing voltage VPB received from the page buffer group1223with a reference voltage generated by the reference current and output a pass signal PASS or a fail signal FAIL.

The control logic130may output an operating signal OPSIG, a row address RADD, page buffer control signals PBSIGNALS, and an enable bit signal VRYBIT in response to a command CMD and an address ADD, and thus control the peripheral circuit1220. In addition, the control logic1230may determine whether a target memory cell has passed a verification during a verify operation in response to a pass signal PASS or a fail signal FAIL.

FIG. 13is a diagram for describing a memory block BLKi ofFIG. 12.

Referring toFIG. 13, in the memory block BLKi, a plurality of word lines arranged parallel to each other may be coupled between a first select line and a second select line. Here, the first select line may be a source select line SSL, and the second select line may be a drain select line DSL. In more detail, the memory block BLKi may include a plurality of strings ST coupled between the bit lines BL1to BLn and the source line SL. The bit lines BL1to BLn may be respectively coupled to the strings ST, and the source lines SL may be coupled in common to the strings ST. The strings ST may have the same configuration; therefore, the string ST that is coupled to the first bit line BL1will be described in detail by way of example.

The string ST may include a source select transistor SST, a plurality of memory cells MC1to MC16, and a drain select transistor DST which are coupled in series to each other between the source line SL and the first bit line BL1. At least one source select transistor SST and at least one drain select transistor DST may be included in each string ST, and a larger number of memory cells than the number of memory cells MC1to MC16shown in the drawing may be included in each string ST.

A source of the source select transistor SST may be coupled to the source line SL, and a drain of the drain select transistor DST may be coupled to the first bit line BL1. The memory cells MC1to MC16may be coupled in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in different strings ST may be coupled to the source select line SSL, gates of the drain select transistors DST may be coupled to the drain select line DSL, and gates of the memory cells MC1to MC16may be coupled to the plurality of word lines WL1to WL16. Among the memory cells included in different strings ST, a group of memory cells coupled to each word line may be referred to as a physical page PG. Therefore, the number of physical pages PG included in the memory block BLKi may correspond to the number of word lines WL1to WL16.

Each memory cell may store 1-bit data. This memory cell is typically called a single level cell (SLC). In this case, each physical page PG may store one logical page (LPG) of data. One logical page (LPG) of data may include data bits corresponding to the number of cells included in a single physical page PG. Furthermore, each memory cell may store two- or more-bit data. In this case, each physical page PG may store two or more LPGs of data.

FIG. 14is a block diagram illustrating a memory card system2000to which the storage device in accordance with an embodiment of the present disclosure is applied.

ReferringFIG. 14, the memory card system2000may include a memory controller2100, a memory device2200and a connector2300.

The memory controller2100is coupled to the memory device2200. The memory controller2100may access the memory device2200. For example, the memory controller2100may control a read operation, a write operation, an erase operation, and a background operation of the memory device2200. The memory controller2100may provide an interface between the memory device2200and the host. The memory controller2100may drive firmware for controlling the memory device2200. The memory controller2100may be embodied in the same manner as that of the memory controller200described with reference toFIG. 1.

In an embodiment, the memory controller2100may include components such as a random access memory (RAM), a processing unit, a host interface, and a memory interface, and an ECC circuit.

The memory controller2100may communicate with an external device through the connector2300. The memory controller2100may communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller2100may communicate with the external device through at least one of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memory express (NVMe) protocols. In an embodiment, the connector2300may be defined by at least one of the above-described various communication protocols.

In an embodiment, the memory controller2100and the memory device2200may be integrated into a single semiconductor device to form a memory card. For example, the memory controller2100and the memory device2200may be integrated into a single semiconductor device to form a memory card such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), a SD card (SD, miniSD, microSD, or SDHC), or a universal flash storage (UFS).

FIG. 15is a block diagram illustrating a solid state drive (SSD) system to which the storage device in accordance with an embodiment of the present disclosure is applied.

Referring toFIG. 15, the SSD system3000may include a host3100and an SSD3200. The SSD3200may exchange signals SIG with the host3100through a signal connector3001and may receive power PWR through a power connector3002. The SSD3200may include an SSD controller3210, a plurality of flash memories3221to322n, an auxiliary power supply3230, and a buffer memory3240.

In an embodiment, the SSD controller3210may perform the function of the memory controller200, described above with reference toFIG. 1.

The SSD controller3210may control the plurality of flash memories3221to322nin response to the signals SIG received from the host3100. In an embodiment, the signals SIG may be signals based on an interface between the host3100and the SSD3200. For example, the signals SIG may be signals defined by at least one of various interfaces such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA), small computer small interface (SCSI), enhanced small disk interface (ESDI), integrated drive electronics (IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memory express (NVMe) interfaces.

The auxiliary power supply3230may be coupled to the host3100through the power connector3002. The auxiliary power supply3230may be supplied with power PWR from the host3100, and may be charged by the power PWR. The auxiliary power supply3230may supply the power of the SSD3200when the supply of power from the host3100is not smoothly performed. In an embodiment, the auxiliary power supply3230may be positioned inside the SSD3200or positioned outside the SSD3200. For example, the auxiliary power supply3230may be disposed in a main board and may supply auxiliary power to the SSD3200.

The buffer memory3240functions as a buffer memory of the SSD3200. For example, the buffer memory3240may temporarily store data received from the host3100or data received from the plurality of flash memories3221to322nor may temporarily store metadata and map data of the flash memories3221to322n. The buffer memory3240may include volatile memories such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, and a GRAM or nonvolatile memories such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM.

FIG. 16is a block diagram illustrating a user system to which the storage device in accordance with an embodiment of the present disclosure is applied.

The application processor4100may run components included in the user system4000, an operating system (OS) or a user program. In an embodiment, the application processor4100may include controllers, interfaces, graphic engines, etc. for controlling the components included in the user system4000. The application processor4100may be provided as a system-on-chip (SoC).

The memory module4200may function as a main memory, a working memory, a buffer memory, or a cache memory of the user system4000. The memory module4200may include a volatile RAM such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDARM, an LPDDR2 SDRAM, and an LPDDR3 SDRAM, or a nonvolatile RAM such as a PRAM, a ReRAM, an MRAM, and an FRAM. In an embodiment, the application processor4100and the memory module4200may be packaged based on package-on-package (POP) and may then be provided as a single semiconductor package.

The network module4300may communicate with external devices. For example, the network module4300may support wireless communication, such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication. In an embodiment, the network module4300may be included in the application processor4100.

The storage module4400may store data therein. For example, the storage module4400may store data received from the application processor4100. Alternatively, the storage module4400may transmit the data stored in the storage module4400to the application processor4100. In an embodiment, the storage module4400may be implemented as a nonvolatile semiconductor memory device, such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the storage module4400may be provided as a removable storage medium (i.e., removable drive), such as a memory card or an external drive of the user system4000.

In an embodiment, the storage module4400may include a plurality of nonvolatile memory devices, and each of the plurality of nonvolatile memory devices may be operated in the same manner as that of the memory device100described above with reference toFIG. 1. The storage module4400may be operated in the same manner as that of the storage device50described above with reference toFIG. 1.

The user interface4500may include interfaces for inputting data or instructions to the application processor4100or outputting data to an external device. In an embodiment, the user interface4500may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and a piezoelectric device. The user interface4500may further include user output interfaces such as an a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

In a memory controller and a method of operating the memory controller in accordance with an embodiment, update version between metadata chunks may be managed by backing up and restoring metadata chunks.

In a memory controller and a method of operating the memory controller in accordance with an embodiment, even when an event in which storing data in the memory device100is inhibited occurs, an operation corresponding to a request from the host or a background operation may be normally performed by managing the update version between the metadata chunks.

A memory controller and a method of operating the memory controller in accordance with an embodiment of the present disclosure may provide improved metadata management performance.

Examples of embodiments have been disclosed herein, and features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments. Various changes may be made based on the present disclosure.