Biasing scheme for high voltage circuits using low voltage devices

Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

TECHNICAL FIELD

Embodiments described herein pertain to input/output circuitry in electronic items. Some embodiments relate to circuits operating at different voltages.

BACKGROUND

I/O circuits (e.g., I/O buffers) are included components (e.g., transceivers) of many electronic devices or systems, such as computers, tablets, cellular phones, and memory cards. Many conventional I/O circuits operate at a relatively high voltage using low voltage devices (e.g., transistors), for example a 3.3V IO using 1.8V devices. In such conventional I/O circuits, a reference voltage is often used in order to protect the low voltage devices from voltage stress that may cause lifetime degradation. Although the device reliability issues are addressed, such conventional I/O circuits may suffer from one or more other issues, as described in detail below.

DETAILED DESCRIPTION

FIG. 1shows an apparatus100including an integrated circuit (IC)101having buffers (e.g., output driver circuits)1100through110Mto provide information (e.g., in the form of signals) from a functional unit115to nodes120and121, according to some embodiments described herein. Apparatus100can include or be included in an electronic device or system, such as a computer (e.g., desktop, laptop, or notebook), a tablet, a cellular phone, a memory card (e.g., a Secure Digital (SD) memory card, a MultiMediaCard (MMC), a flash memory card, a Subscriber Identity Module (SIM) card, and other types of memory cards), or other electronic devices or systems. IC101can include a processor, a memory device, a system on chip (SoC), or other electronic devices or systems. IC101can include an IC die (e.g., an IC chip, such as a semiconductor chip).

Functional unit115of IC101can include components (e.g., circuits and logic) of a processor (e.g., to process information, such as data), a memory device (e.g., to store information), or both. Nodes120and121can include corresponding output nodes of buffer1100through110Mand can form part of input/output (I/O) connections (e.g., I/O pads) of IC101to allow buffers1100through110Mto provide information from IC101(e.g., information originated from functional unit115) to another device or system coupled to nodes120and121. Signals (e.g., output signals) DOUT0and DOUTMon corresponding nodes120and121can represent information (e.g., data) to be provided by IC101to another device (or system).FIG. 1shows IC101including two buffers1100through110Mand two associated nodes120and121, as an example. The number of buffers of IC101may vary.

InFIG. 1, the value of signals DOUT0can be based on the values of signals (e.g., input signals) IN_P0and IN_N0. The value of signal DOUTMcan be based on the values of signals (e.g., input signals) IN_PMand IN_NM. Signals IN_P0and IN_N0may be in-phase signals. Signals IN_PMand IN_NMmay be in-phase signals. Signals IN_P0, IN_N0, IN_P0, and IN_N0can carry information (e.g., data) processed by functional unit115or information stored in memory cells (not shown) of IC101.

For simplicity,FIG. 1shows details of only one of buffers1100through110M. Buffers1100through110Mmay include similar or identical circuit components. As shown inFIG. 1, buffers1100can include a pre-driver stage130that includes pre-drivers131and132, a bias stage140that includes bias voltage generators141and142, and an output stage150that includes transistors P1, P2, N1, and N2that can be coupled in series (e.g., arranged as a stack) between nodes190and193. Each of transistors P1and P2can include p-channel field effect transistors, such as a p-channel metal-oxide semiconductor (PMOS) transistor. Each of transistors N1and N2can include an n-channel field effect transistor, such as an n-channel metal-oxide semiconductor (NMOS) transistor.

Pre-driver stage130and bias stage140can operate to control the values of signals (e.g., input signals) In_p and In_n (at corresponding nodes181and184) and the values of voltages (e.g., bias voltages) VG_Pand VG_N(at corresponding nodes182and183) to control (e.g., turn on or off) transistors P1, P2, N1, and N2in order to switch the signal between different levels (e.g., voltage levels). For example, pre-driver stage130and bias stage140can turn on transistors P1, P2, and N2while they turn off transistor N1in order to switch signal DOUT0from a level corresponding to the value of voltage V0at node190to another level corresponding to the value of voltage a V3at node193. In another example, pre-driver stage130and bias stage140can turn on transistors N1, N2, and P2while they turn off transistor P1in order to switch signal DOUT0from the level corresponding to the value of voltage V3to the level corresponding to the value of voltage V0.

Voltage V0can have a value of zero volts (e.g., ground potential). Voltage V3can have a positive value. Voltage V0can include a supply voltage (e.g., rail supply voltage Vss) of IC101. Voltage V3can include another supply voltage (e.g., rail supply voltage VDD_IO). Since voltages V0and V3can include rail supply voltages of IC101, signal DOUTcan switch from rail to rail (e.g., can have a full swing). In some arrangements, voltage V3can have a value of approximately 3.3V. Thus, in some arrangements, signal DOUTcan switch between 0V and 3.3V.

Pre-driver131can receive a signal (e.g., input signal) IN_P and generate signal In_p based on signal IN_P. Signal In_p can switch (e.g., can have a signal swing) between levels (e.g., voltage levels) based on the values of voltages VG_Pand V3. The value of voltage VG_Pmay be greater than zero. Thus, signal In_p may not have a full swing (may not swing from zero to V3). In some arrangements, the value of voltage VG_Nmay be zero. For example, the value of voltage VG_Nmay be zero when the value of voltage V3is within the operating limit of transistors P1, P2, N1, and N2.

Pre-driver132can receive a signal (e.g., input signal) IN_N and generate signal In_n based on signal IN_N. Signal In_n can switch (e.g., can have a signal swing) between levels (e.g., voltage levels) based on the values of voltages V0and VG_N. The value of voltage VG_Nis greater than zero. Thus, signal In_n may not have a full swing (may not swing from zero to V3).

Bias voltage generator141can generate voltage VG_N. The value of voltage VG_Ncan be relatively constant at (e.g., remain at 1.8V) during the operation of buffer1100. Bias voltage generator141of buffer1100may be shared by the buffers (e.g., buffers1100through110M) of IC101. For example, node183in buffer1100may also be coupled to buffers110M, so that voltage VG_Nat node183may also be provided as a bias voltage to buffer110M.

Bias voltage generator142can generate voltage VG_P. The value of voltage VG_Pcan be based on a value of voltage VG_N. For example, the value of voltage VG_Pcan be the difference between the values of voltages V3and VG_N. The value of voltage VG_Pcan be relatively constant at (e.g., remain at VG_P=V3−VG_N) during the operation of buffer1100. Bias voltage generator142of buffer1100may be shared by the buffers (e.g., buffers1100through110M) of IC101. For example, node182in buffer1100may also be coupled to buffers110M, so that voltage VG_Pat node182may also be provided as a bias voltage to buffer110M.

Transistors P1, P2, N1, and N2can have an operating voltage tolerance less than the value of voltage V3. For example, each of transistors P1, P2, N1, and N2can be relatively low voltage device relative to voltage V3. For example, each of transistors P1, P2, N1, and N2may be a 1.8V transistor (1.8V device), such that the transistor may have an operating gate-to-drain voltage (VGD=1.8V) less than V3(e.g., 3.3V, an operating gate-to-source voltage (e.g., VGS=1.8V) less than V3), and an operating drain-to-source voltage (e.g., VDS=1.8V) less than voltage V3. Although transistors P1, P2, N1, and N2may be low voltage devices (e.g., 1.8V devices), the arrangement of transistors P1, P2, N1, and N2with pre-driver stage130and bias stage140as described above, may allow buffers1100through110Mto operate safely (e.g., operate in an electrical overstress safe condition) at a higher operating voltage (e.g., V3of 3.3V).

Each of buffers1100through110Mcan include a buffer described below with reference toFIG. 2throughFIG. 8.

FIG. 2shows a circuit diagram of a buffer210, according to some embodiments described herein. Buffer210can be used as each of buffers1100through110M(FIG. 1). Buffer210can include nodes (e.g., input nodes)201and202to receive signals (input signals) IN_P and IN_N, respectively, and a node (e.g., output node)220to provide a signal (e.g., output signal) DOUT. Signals IN_P, IN_N, and DOUTcan correspond to signals IN_P0, IN_N0, and DOUT0, respectively, of buffer1100(FIG. 1) or correspond to signals IN_PM, IN_NM, and DOUTM, respectively, of buffer110M(FIG. 1).

Buffer210can include a pre-driver stage230having pre-drivers231and232, a bias stage240having bias voltage generators241and242, and an output stage250having a pair of transistors P1and P2and a pair of transistors N1and N2. Transistors P1, P2, N1, and N2can correspond to transistors P1, P2, N1, and N2ofFIG. 1.

As shown inFIG. 2, transistor P1and P2can be coupled (e.g., coupled in series) between a node (e.g., supply node)293and node220. Transistor N1and N2can be coupled (e.g., coupled in series) between node220and node (e.g., supply node)290. Nodes290and293can receive voltage V0and V3, respectively. Voltage V0can have a value of zero volts (e.g., ground potential). Voltages V0and V3can include supply rail voltages of an IC (e.g., IC101) that includes buffer210. Signal DOUTat node220can switch (e.g., can have a signal swing) between levels (e.g., voltage levels) based on the values of voltages V0and V3. Since voltages V0and V3can include supply rail voltages, signal DOUTcan switch from rail to rail (e.g., can have a full swing).

Transistor P1includes a gate coupled to a node281to receive a signal (e.g., input signal) In_p. Transistor N1includes a gate coupled to a node284to receive a signal In_n. Transistor P2includes a gate coupled to a node282to receive a voltage (e.g., bias voltage) VG_P. Transistor N2includes a gate coupled to a node283to receive a voltage (e.g., bias voltage) VG_N.

Pre-driver231can include a transistor (e.g., p-channel transistor) P3and a transistor (e.g., n-channel transistor) N3coupled between node293(that receive voltage V3) and a node282(that receive a voltage VG_P). Transistors P3and N3can operate as an inverter that has an input coupled to node201to receive signal IN_P and an output coupled to node281to provide signal In_p. Signal In_p can be an inverted version of signal IN_P. As shown inFIG. 2, signal IN_P can switch (e.g., can have a signal swing) between levels (e.g., voltage levels) based on the values of voltages VG_Pand V3. Signal In_p can also switch (e.g., can have a signal swing) between levels based on the values of voltages VG_Pand V3.

Pre-driver232can include a transistor (e.g., p-channel transistor) P4and a transistor (e.g., n-channel transistor) N4coupled between node283(that receives voltage VG_N) and a node290(that receives voltage V0). Transistors P4and N4can operate as an inverter that has an input coupled to node202to receive signal IN_N and an output coupled to node284to provide signal In_n. Signal In_n can be an inverted version of signal IN_N. As shown inFIG. 2, signal IN_N can switch (e.g., can have a signal swing) between levels (e.g., voltage levels) based on the values of voltages V0and VG_N. Signal In_n can also switch (e.g., can have a signal swing) between levels based on the values of voltages V0and VG_N.

Bias voltage generator241can generate voltage VG_N. The value of voltage VG_Ncan be selected to be the maximum allowed gate-to-source voltage (e.g., VGSMAX) of transistor N2. Voltage VG_Ncan be generated from a supply voltage (e.g., different from voltage V3) of buffer210, such that value of voltage VG_Ncan include the value of the supply voltage (e.g., 1.8V) of buffer210. Alternatively, the value of voltage VG_Ncan be generated from a bandgap reference voltage. As shown inFIG. 2, the value of voltage VG_Nis greater than zero volts and can be relatively constant at (e.g., remain at 1.8V) during the operation of buffer210.

Bias voltage generator242can generate a voltage (e.g., bias voltage) VG_P. The value of voltage VG_Pis based on a value of voltage VG_N. The value of voltage VG_Pcan be based on the value of voltage VG_Nor both voltages V3and VG_N. For example, the value of voltage VG_Pcan be the difference between the values of voltages V3and VG_N(e.g., VG_P=V3−VG_N). As shown inFIG. 2, the value of voltage VG_Pmay be greater than zero volts and may be relatively constant at (e.g., remain at VG_P=V3−VG_N) during the operation of buffer210. In some arrangements, such as when value of voltage V3is within the operating limit of transistors P1, P2, N1, and N2, the value of voltage VG_Nmay be zero.

FIG. 3AandFIG. 3Bshow block diagrams of different bias voltage generators341A and341B to generate a voltage (e.g., bias voltage) VG_N(at node383aor383b), according to some embodiments described herein. Either bias voltage generator341A or341B can be used as bias voltage generator141(FIG. 1) or bias voltage generator241of buffer210(FIG. 2). Each of node383aand383bcan correspond to node183(coupled to the gate of transistor N2) ofFIG. 1or node283(coupled to the gate of transistor N2) ofFIG. 2.

As shown inFIG. 3A, bias voltage generator341A can include a supply voltage generator that provides a supply voltage (e.g., an IC chip supply voltage of 1.8V). As shown inFIG. 3B, bias voltage generator341B can include a bandgap reference based voltage generator, such that voltage VG_Ncan be generated based on a bandgap reference voltage that is generated by the bandgap reference based voltage generator. Thus, as shown inFIG. 3AandFIG. 3B, voltage VG_Ncan be generated based on a supply voltage or a bandgap reference voltage.

FIG. 4shows a block diagram of a bias voltage generator442to generate a voltage (e.g., bias voltage) VG_Pat a node482, according to some embodiments described herein. Bias voltage generator442can be used as bias voltage generator142(FIG. 1) or bias voltage generator242of buffer210(FIG. 2). Bias voltage generator442can generate voltage VG_Pbased on voltage V3(e.g., supply voltage VDD_IO) at node493(e.g., supply node) and voltage VG_Nat a node483. The value of voltage VG_Pcan be the difference between the values of voltages V3and VG_N(e.g., VG_P=V3−VG_N).

Node482can correspond to node182(coupled to the gate of transistor P2) ofFIG. 1or node282(coupled to the gate of transistor P2) ofFIG. 2. Node483(that receives voltage VG_NinFIG. 4) can correspond to node183(coupled to the gate of transistor N2) ofFIG. 1or node283(coupled to the gate of transistor N2) ofFIG. 2.

FIG. 5shows a circuit diagram of bias voltage generator542to generate a voltage (e.g., bias voltage) VG_Pat a node582(output of bias voltage generator542), according to some embodiments described herein. Bias voltage generator542can be used as a bias voltage generator of an I/O circuit (e.g., a buffer), such as bias voltage generator142of buffer1100ofFIG. 1or bias voltage generator242of buffer210ofFIG. 2.

As shown inFIG. 5, bias voltage generator542can include a node (e.g., supply node)593to receive a voltage V3and a node583to receive a voltage VG_N. Voltage V3can be a supply voltage (e.g., VDD_IO=3.3V) of a buffer of a device (or system) that includes bias voltage generator542. Voltage VG_Ncan be generated based on another supply voltage of the buffer of a device (or system) that includes bias voltage generator542. For example, voltage VG_Ncan be generated by bias voltage generator341A ofFIG. 3A. Alternatively, voltage VG_NinFIG. 5can be generated based on a bandgap reference voltage. For example, voltage VG_Ncan be generated by bias voltage generator341B ofFIG. 3B.

Voltage VG_NinFIG. 5can be the same as the voltage (bias voltage) provided (e.g., applied) to a gate of a transistor (e.g., transistor N2) of an output stage of the buffer that includes bias voltage generator542. Voltage VG_Pcan be another bias voltage provided (e.g., applied) to a gate of another transistor (e.g., transistor P2) of the buffer.

As shown inFIG. 5, bias voltage generator542can include circuit branches501and502. Circuit branch501can include a transistor P5(e.g., p-channel transistor) and a resistor R1coupled between nodes583and593, such that the value of current I is proportional to the difference between the values of voltage V3at node593and voltage VG_Nat node583. Circuit branch502can include transistors P6and P7(e.g., p-channel transistors) and a resistor R2coupled between node593and a node590. Node590can receive a voltage V0(e.g., ground potential, such as Vss). Circuit branches501and502can be arranged in a current mirror arrangement to mirror a current I from circuit branch501to circuit branch502.

Circuit branches501and502can include circuit portions511and512, respectively. Circuit portions511and512have matched circuit structure, such that the structure of circuit portion511matches (e.g., is the same as) the structure of circuit portion512. For example, transistors P5and P7can have the same transistor structure. Resistors R1and R2can have the same resistance value. Thus, in operation, the value of the voltage (e.g., voltage drop V3−VG_N) across circuit portion511(which is also a function of current I and the resistance of circuit portion511) can be the same as the value of the voltage (e.g., voltage drop VG_P−V0) across circuit portion512(which is a function of current I and a resistance of circuit portion512). Therefore, VG_P−V0=V3−VG_N. Since V0can be zero (e.g., ground potential), VG_P=V3−VG_N.

In sum, when bias voltage generator542ofFIG. 5is used in a buffer (e.g., one of buffers1100through110MofFIG. 1or buffer210ofFIG. 2), the value of a bias voltage (e.g., VG_P) provided to the gate of a transistor (e.g., P2inFIG. 1orFIG. 2) at an output stage of the buffer can be the difference between the value of a supply voltage (e.g., V3) at the output stage of the buffer and the value of another bias voltage (e.g., VG_N) provided to the gate of another transistor (e.g., N2inFIG. 1orFIG. 2) of the output stage of the buffer.

Generating voltage VG_Pbased on voltage VG_N, as described above with reference toFIG. 5, may allow bias voltage generator542to improve operations of an I/O circuit (e.g., each of buffers1100through110MofFIG. 1or buffer210ofFIG. 2) that includes bias voltage generator542, in comparison with some conventional I/O circuits. For example, some conventional I/O circuits that use conventional biasing techniques (e.g., resistive voltage division and constant voltage biasing techniques) may have one or more of the following issues: asymmetric transmitter rise and fall times due to unequal VGS(gate overdrive voltage) for PMOS and NMOS drivers, especially over variation in I/O supply voltage (e.g., variation in voltage similar to voltage V3inFIG. 5); use of large devices due to sub-optimal VGS, especially at the lower limit of supply voltage range; and low noise resilience in receivers due to high variation in switching thresholds of transistor (e.g., transistor in the output stage of the I/O circuit).

InFIG. 5, generating voltage VG_Pusing bias voltage generator542based on voltage VG_Nmay allow an I/O circuit (e.g., buffer210ofFIG. 2) that includes bias voltage generator542to reduce or eliminate one or more of the above issues that may occur in some conventional I/O circuits. Moreover, with the arrangement as shown inFIG. 5, the devices (e.g., transistors P5, P6, and P7) of bias voltage generator542may be protected (e.g., self-protected) against voltage stress potentially caused by voltage V3.

As mentioned above, bias voltage generator542can be used as a bias voltage generator of an I/O circuit, such as a buffer (e.g., buffer1100ofFIG. 1or buffer210ofFIG. 2). Bias voltage generator542, however, may also be used in other I/O circuits, such as receiver circuits and level shifter circuits, and other circuits that may use a bias voltage (e.g., voltage VG_P) control a gate of a transistor among transistors coupled (e.g., coupled in series) between nodes having different voltages (e.g., different supply voltages).

FIG. 6shows a bias voltage generator642that can be variation of bias voltage generator542ofFIG. 5, according to some embodiments described herein. Bias voltage generators542(FIG. 5) and642(FIG. 6) can include similar or identical elements, such as voltages V3and VG_Nand circuit portions511and512. For simplicity, the description of similar or identical elements between bias voltage generators542and642is not repeated in the description of bias voltage generator642. Bias voltage generator642can be used as a bias voltage generator of an I/O circuit (e.g., a buffer), such as bias voltage generator142of buffer1100ofFIG. 1or bias voltage generator242of buffer210ofFIG. 2.

As shown inFIG. 6, besides transistor P6and circuit portions511and512, bias voltage generator642can include additional elements such as transistor P8(e.g., p-channel transistor) and N5and N6(e.g., n-channel transistors), and capacitors C1and C2. Some of these additional elements (e.g., transistors N6and P8) can be included in a circuit branch603between nodes593and590. Bias voltage generator642can include an output at node682in circuit branch603.

The value of the voltage at node685can be the same as (e.g., substantially equal to) the value of the voltage (e.g., V3−VG_N) across circuit portion511. The value of voltage VG_Pat node682(output of bias voltage generator642) can be the same as (e.g., substantially equal to) the value of the voltage at node685. Since the value of the voltage at node685can be V3−VG_N(the difference between the values of voltages V3and VG_N), the value of voltage (VG_P) at node682can also be VG_P=V3−VG_N.

Although voltage VG_Pin bias voltage generators542(FIG. 2)642(FIG. 6) can have the same value (e.g., VG_P=V3−VG_N), the additional elements (e.g., transistors P8, N5, and N6, and capacitors C1and C2which can operate to stabilize the buffer) in bias voltage generator642may allow it to have a lower output impedance than that of bias voltage generator542. This may allow bias voltage generator642to be suitable for a buffer in which the output stage of such a buffer is arranged to have relatively lower impedance.

For example, node682can correspond to node282ofFIG. 2. Thus, when bias voltage generator642is used in buffer210, pre-driver231of buffer210may pump a relatively high amount of transient current into bias voltage generator642. Further, signal DOUTof buffer210may switch at a relatively high frequency (e.g., fast swings). This may cause a high amount of capacitive coupling through the gate-drain voltage of transistor P6when bias voltage generator642is used in buffer210. The additional elements (e.g., transistor P8, N5, and N6, and capacitors C1and C2, as shown inFIG. 6) in bias voltage generator642it may allow it to have a relatively lower output impedance (e.g., impendence at node682) that may improve the operation of bias voltage generator642and buffer210.

Bias voltage generator642may also be used in a buffer in which one of the bias voltages is generated based on a bandgap reference voltage. For example, if voltage VG_Nof buffer210ofFIG. 2is generated based on a bandgap reference voltage, using bias voltage generator642that has relatively lower output impedance that may improve the operation of bias voltage generator642and buffer210.

Generating voltage VG_Pbased on voltage VG_N, as described above with reference toFIG. 6, may allow bias voltage generator642to improve operations of an I/O circuit (e.g., each of buffers1100through110MofFIG. 1or buffer210ofFIG. 2) that includes bias voltage generator542in comparison with some conventional I/O circuits. For example, some conventional I/O circuits that use conventional biasing techniques (e.g., resistive voltage division and constant voltage biasing techniques) may have one or more of the following issues: high output impedance variation and variation in I/O supply voltage causing signal integrity and noise issues; unstable bias voltages due to high output impedance of the bias generators; and other issues mentioned above with reference to the description ofFIG. 5(e.g., asymmetric transmitter rise and fall times due to unequal VGSfor PMOS and NMOS drivers, especially over variation in I/O supply voltage; use of large devices due to sub-optimal VGS, especially at the lower limit of supply voltage range; and low noise resilience in receivers due to high variation in switching thresholds of transistor).

InFIG. 6, generating voltage VG_Pusing bias voltage generator642based on voltage VG_Nmay allow an I/O circuit (e.g., each of buffers1100through110MofFIG. 1or buffer210ofFIG. 2) that includes bias voltage generator642ofFIG. 6to reduce or eliminate one or more of the above issues that may occur in some conventional I/O circuits. Moreover, with the arrangement as shown inFIG. 6, the devices (e.g., transistors P5, P6, P7, P8, N5and N6) of bias voltage generator642may be protected (e.g., self-protected) against voltage stress potentially caused by voltage V3. Bias voltage generator642may also be relatively smaller than some conventional I/O circuits.

Further, in comparison with some conventional I/O circuits that use conventional biasing techniques (e.g., resistive voltage division technique), the I/O circuit that uses voltage VG_Pgenerated by bias voltage generator642based on voltage VG_Nmay have an approximately 15% improvement (e.g., benefit) in operating frequency of the I/O circuit and a significantly (e.g., approximately 70%) better current sinking and sourcing capability of the biasing circuit. Depending on the interface specification (e.g., specification based on conventional standards) that the buffer may be used, an appropriate trade-off point can be chosen such that these improvements can be used for better performance or die area or power consumption of the interface. The I/O circuit that includes bias voltage generator642ofFIG. 6may be relatively smaller than some conventional I/O circuits.

Moreover, generating voltage VG_Pusing bias voltage generator542(FIG. 5) or642(FIG. 6) based on voltage VG_N(e.g., VG_P=V3−VG_N), as described above with reference toFIG. 5andFIG. 6, may provide the maximum allowed and equal (e.g., symmetry bias) overdrive (VGS) to both PMOS and NMOS transistors (e.g., P2and N2inFIG. 1orFIG. 2) of the I/O circuit. The supply voltage (e.g., V3) of the I/O circuit may have an operating range (e.g., a specified range) such that the value of the supply voltage (e.g., V3) can have different values, depending on the interface specification (as mentioned above). Generating voltage VG_Pusing bias voltage generator542(FIG. 5) or642(FIG. 6) may also provide equal overdrive to the transistors (e.g., P2and N2inFIG. 1orFIG. 2) across variations (e.g., across different voltages values) in the supply voltage (e.g., V3) of the I/O circuit.

For example, inFIG. 1(orFIG. 2), if the value of voltage V3is 2.7V and the value of voltage VG_Nis 1.7V (e.g., the overdrive of transistor N2), then voltage VG_P=V3−VG_N=2.7−1.7=1.0V. Thus, the overdrive of transistor P2is 2.7V−1.0V=1.7V, which is equal to the overdrive of transistor N2in this example. In another example, inFIG. 1(orFIG. 2), if the value of voltage V3is 3.6V and the value of voltage VG_Nis 1.7V (e.g., the overdrive of transistor N2), then voltage VG_P=V3−VG_N=3.6−1.7=1.9V. Thus, the overdrive of transistor P2is 2.7V−1.9V=1.7V, which is also equal to the overdrive of transistor N2in this example. Thus, using bias voltage generator542(FIG. 5) or642(FIG. 6) to generate voltage VG_Pbased on voltage VG_Nand voltage V3, such that VG_P=V3−VG_N, may provide symmetrical overdrive to the transistors (e.g., P2and N2inFIG. 1orFIG. 2) of the buffer. This may allow the buffer to have improvements (e.g., benefits) over some conventional buffers, such as improvements discussed above.

As mentioned above, bias voltage generator642can be used as a bias voltage generator of an I/O circuit, such as a buffer (e.g., buffer1100ofFIG. 1or buffer210ofFIG. 2). Bias voltage generator642, however, may also be used in other I/O circuits, such as receiver circuits and level shifter circuits, and other circuits that may use a bias voltage (e.g., voltage VG_P) control a gate of a transistor among transistors coupled (e.g., coupled in series) between nodes having different voltages (e.g., different supply voltages).

FIG. 7shows an apparatus in the form of according to some embodiments described herein. System700can include or be included in a computer, a cellular phone, or other electronic systems. As shown inFIG. 7, system700can include a processor705, a memory device720, a memory controller730, a graphics controller740, an input and output (I/O) controller750, a display752, a keyboard754, a pointing device756, at least one antenna758, a connector715, and a bus760.

Each of processor705, memory device720, memory controller730, graphics controller740, and I/O controller750can include an IC such as IC101(FIG. 1).

In some arrangements, system700does not have to include a display. Thus, display752can be omitted from system700. In some arrangements, system700does not have to include any antenna. Thus, antenna758can be omitted from system700.

Processor705may include a general-purpose processor or an application specific integrated circuit (ASIC).

Memory device720may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination of these memory devices.FIG. 7shows an example where memory device720is a stand-alone memory device separated from processor705. In an alternative arrangement, memory device720and processor705can be located on the same die. In such an alternative arrangement, memory device720is an embedded memory in processor705, such as embedded DRAM (eDRAM), embedded SRAM (eSRAM), embedded flash memory, or another type of embedded memory.

Display752can include a liquid crystal display (LCD), a touchscreen (e.g., capacitive or resistive touchscreen), or another type of display. Pointing device756can include a mouse, a stylus, or another type of pointing device.

I/O controller750can include a communication module for wired or wireless communication (e.g., communication through one or more antenna758). Such wireless communication may include communication in accordance with WiFi communication technique, Long Term Evolution Advanced (LTE-A) communication technique, or other communication techniques.

I/O controller750can also include a module to allow system700to communicate with other devices or systems in accordance with to one or more of the following standards (e.g., I/O standards), including the Secure Digital standard (e.g., Secure Digital Input Output (SDIO) standard), the MultiMediaCard (MMC) standard, the Universal Serial Bus (USB) standard, and the Subscriber Identity Module (SIM) standard (e.g., universal SIM (USIM) standard).

Connector715can be arranged (e.g., can include terminals, such as pins) to allow system700to be coupled to an external device (or system). This may allow system700to communicate (e.g., exchange information) with such device (or system) through connector715. Connector715can be at least one of (e.g., one or more of) a SDIO connector, an MMC connector, USB connector, SIM (or USIM) connector, and other types of connectors.

I/O controller750can include a transceiver (Tx/Rx)770ahaving a receiver (Rx)772and a transmitter (Tx)774. Receiver772can operate to allow I/O controller750to receive information from another part of system700or from an external device (or system) coupled to connector715. Transmitter774can include buffers710to allow I/O controller750to transmit information from I/O controller750to another part of system700or to an external device (or system) coupled to connector715.

Each of the buffers710can include any of the buffers (e.g., buffers1100through110Mand buffer210) including bias voltage generators (e.g.,141,142,241,242,341A,341B,442,542, and642) described above with reference toFIG. 1throughFIG. 6. Thus, buffers710can be arranged to operate in ways similar to, or identical to, those of any of the buffers described above with reference toFIG. 2throughFIG. 6. InFIG. 7, for example, each of buffers710can include an output node (e.g.,120or121ofFIG. 1 or 220ofFIG. 2) arranged to couple to connector715to allow I/O controller750to communicate with an external device (or system) coupled to connector715.

As shown inFIG. 7, processor705, memory device720, memory controller730, and graphics controller740can include transceivers770b,770c,770d, and770e, respectively, to allow each of these components to transmit and receive information through their respective transceiver. At least one of transceivers770b,770c,770d, and770ecan be similar to or identical to transceiver770a. Thus, at least one of transceivers770b,770c,770d, and770ecan include one or more buffers that can be similar to or identical to buffers710. For example, at least one of transceivers770a,770b,770c,770d, and770ecan include at least one of buffers710having an output node (e.g.,120or121ofFIG. 1 or 220ofFIG. 2) that can be arranged to couple to connector715to allow at least one of processor705, memory device720, memory controller730, and graphics controller740to communicate with an external device (or system) coupled to connector715.

FIG. 7shows the components of system700arranged separately from each other as an example. For example, each of processor705, memory device720, memory controller730, graphics controller740, and I/O controller750can be located on a separate die (e.g., semiconductor die or an IC chip). In some arrangements, two or more components (e.g., processor705, memory device720, graphics controller740, and I/O controller750) of system700can be located on the same die (e.g., same IC chip) that forms a system-on-chip (SoC). In such arrangements, the output node of the buffer, such as one of buffers710, in at least one of processor705, memory device720, memory controller730, graphics controller740, and I/O controller750, can be part of an input/out (I/O) pad of the SoC.

FIG. 8is a flowchart showing a method800of operating a buffer, according to some embodiments described herein. The buffer used in method800can include any of the buffers (e.g., buffers1100through110MofFIG. 1, buffer210ofFIG. 2, and buffers included in at least one of transceivers770athrough770eofFIG. 7) described above with reference toFIG. 1throughFIG. 7.

As shown inFIG. 8, activity810of method800can include providing a bias voltage to a gate of a transistor among transistors of an output stage of a buffer. The transistor can be coupled between a supply voltage and ground. Activity820can include generating an additional bias voltage based on the supply voltage and the bias voltage generated in activity810. Activity830can include providing the additional bias voltage to a gate of another transistor among the transistors of the output stage of the buffer.

Method800can include fewer or more activities relative to activities810,820, and830shown inFIG. 8. For example, method800can include activities and operations of a buffer described above with reference toFIG. 1throughFIG. 7.

The illustrations of the apparatuses (e.g., apparatus100including IC101and system700) and methods (e.g., method800and operations of IC101, buffers1100through110M, buffer210, buffers710, and system700) described above are intended to provide a general understanding of the structure of different embodiments and are not intended to provide a complete description of all the elements and features of an apparatus that might make use of the structures described herein.

The apparatuses and methods described above can include or be included in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multilayer, multi-chip modules. Such apparatuses may further be included as sub-components within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, etc.), tablets (e.g., tablet computers), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

ADDITIONAL NOTES AND EXAMPLES

Example 1 includes subject matter (such as a device, circuit apparatus or electronic system apparatus, or machine) including a first node to receive a supply voltage, a second node to receive a first bias voltage provided to a gate of a first transistor of a plurality of transistors coupled in series, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes, wherein the first and second circuit branches are arranged to provide a second bias voltage to a gate of a second transistor of the plurality of transistors, such that a value of the second bias voltage is based on a value of the first bias voltage.

In Example 2, the subject matter of Example 1 may optionally include, wherein the value of the second bias voltage is based on a difference between a value of the supply voltage and the value of the first bias voltage.

In Example 3, the subject matter of Example 1 may optionally include, wherein the first circuit branch including a first circuit portion coupled between the first and second nodes, the second circuit branch including a second circuit portion coupled between the first and third nodes, and the first and second circuit portions have matched circuit structure.

In Example 4, the subject matter of Example 1 may optionally include a third circuit branch coupled between the first and third nodes and coupled to the first and second circuit branches, wherein third circuit branch includes a node to provide the second bias voltage.

In Example 5, the subject matter of Example 1 may optionally include, wherein the first transistor is included in a pair of transistors of the plurality of transistors, the pair of transistors is coupled between the third node and an output node of an input/output (I/O) circuit, the second transistor is included in an additional pair of transistors of the plurality of transistors, and the additional pair of transistors is coupled between the output node of the I/O circuit and the first node.

Example 6 includes subject matter (such as a device, circuit apparatus or electronic system apparatus, or machine) including a first node to receive a first voltage, a second node to receive a second voltage less than the first voltage, an output stage including transistors coupled between the first and second nodes, and a bias stage to provide a first bias voltage to a gate of a first transistor among the transistors and to provide a second bias voltage to a gate of a second transistor among the transistors, and a value of second bias voltage is based on a value of the first voltage and a value of the first bias voltage.

In Example 7, the subject matter of any one of Example 6 may optionally include, wherein the first voltage includes a first supply voltage, the second voltage includes ground potential, and the first bias voltage includes a second supply voltage of the apparatus.

In Example 8, the subject matter of any one of Example 6 may optionally include, wherein the first voltage includes a first supply voltage of the apparatus, the second voltage includes ground potential, and the first bias voltage is generated from a bandgap reference voltage.

In Example 9, the subject matter of Example 6 may optionally include a pre-driver to provide a signal to a gate of a third transistor among the transistors, wherein the pre-driver is arranged such that the signal provided to the gate of the third transistor has a signal swing between a level based on a value of the first voltage and a level based on the value of the second bias voltage.

In Example 10, the subject matter of Example 9 may optionally include an additional pre-driver to provide a signal to a gate of a fourth transistor among the transistors, wherein the additional pre-driver is arranged such that the signal provided to the gate of the fourth transistor has a signal swing between a level based on a value of the second voltage and a level based on the value of the first bias voltage.

In Example 11, the subject matter of Example 6 may optionally include an output node to provide an output signal based on a first input signal and a second input signal, wherein the transistors includes a pair of transistors coupled between the first node and the output node, the pair of transistors including the second transistor and a transistor having a gate to receive the first signal, and an additional pair of transistors coupled between the output node and the second node, the pair of transistors including the first transistor and a transistor having a gate to receive the second signal.

In Example 12, the subject matter of Example 11 may optionally include a third node to receive the first bias voltage, wherein the bias stage includes a bias voltage generator to generate the second bias voltage at an output of the bias voltage generator, the bias voltage generator including a first circuit branch having a first circuit portion coupled between the first and third nodes, and a second circuit branch having a second circuit portion coupled between the first and second nodes, and wherein the first and second circuit portions have matched circuit structure, and the value of the second bias voltage is a function of a current and a resistance across the second circuit portion.

In Example 13, the subject matter of Example 12 may optionally include, wherein the bias voltage generator further comprising a third circuit branch coupled between the first and second nodes and arranged with the first and second circuit branches such that the second bias voltage is provided at a node in the third circuit branch.

In Example 14, the subject matter of Example 13 may optionally include, wherein first additional transistors coupled between the first node and the output of the bias voltage generator, the first additional transistors arranged to operate as an inverter having an input to receive a first input signal and an output to provide the first signal based on the first input signal, and second additional transistors coupled between the second node and the gate of the first transistor of the output stage, the second additional transistors arranged to operate as an inverter having an input to receive a second input signal and an output to provide the second signal based on the second input signal.

In Example 15, the subject matter of Example 6 may optionally include, wherein the first node is arranged to receive the first voltage including a supply voltage having a range from approximately 2.7 volts to approximately 3.6 volts.

In Example 16, the subject matter of Example 15 may optionally include, wherein a third node to receive an additional supply voltage having a value of approximately 1.8 volts, wherein the first bias voltage has a value based on the value of the additional supply voltage.

Example 17 includes subject matter (such as a device, circuit apparatus or electronic system apparatus, or machine) including an integrated circuit including a first node to receive a supply voltage and a second node to receive ground potential, and a transmitter located in the integrated circuit, the transmitter including a buffer to transmit a signal, the buffer including an output stage including a first pair of transistors coupled between the first node and an output node, and a second pair of transistors coupled between the output node and the second node, and a bias stage to provide a first bias voltage to a gate of a transistor in the second pair of transistors and a second bias voltage to a gate of a transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is based on a value of the supply voltage and the value of the first bias voltage.

In Example 18, the subject matter of Example 17 may optionally include, wherein the value of the second bias voltage is based on a difference between the value of the supply voltage and the value of the first bias voltage.

In Example 19, the subject matter of Example 17 may optionally include, wherein the output node is arranged to couple to a connector, the connector including at least one of a Secure Digital Input Output (SDIO) connector, a MultiMediaCard (MMC) connector, a Universal Serial Bus (USB) connector, and a Subscriber Identity Module (SIM) connector.

In Example 20, the subject matter of Example 17 may optionally include at least one of a display coupled to the integrated circuit and an antenna coupled to the integrated circuit.

In Example 21, the subject matter of Example 17 may optionally include, wherein the apparatus comprises a system on a chip (SoC), and the output node is part of an input/output (I/O) pad of the SoC.

Example 22 includes subject matter including a method of operating a buffer, the method comprising providing a first bias voltage to a gate of a first transistor among transistors of an output stage of a buffer, the transistors coupled between a node having a supply voltage and ground, generating a second bias voltage based on the supply voltage and the first bias voltage, and providing the second bias voltage to a gate of a second transistor among the transistors.

In Example 23, the subject matter of Example 22 may optionally include providing the first bias voltage includes coupling the gate of the first transistor to an additional supply voltage, the additional supply voltage having a value greater than zero and less than a value of the supply voltage coupled to the transistors.

In Example 24, the subject matter of Example 22 may optionally include, wherein providing the first bias voltage includes coupling the gate of the first transistor to a bandgap reference based voltage generator.

In Example 25, the subject matter of Example 22 may optionally include, wherein generating the second bias voltage includes mirroring a current from a circuit portion of a first circuit branch of a bias voltage generator to a circuit portion of a second circuit branch of the bias voltage generator, the first circuit branch coupled between the node having the supply voltage and the gate of the first transistor, and the circuit portions of the first and second circuit branches having a matched circuit structure, and wherein the second bias voltage is based on a value of a voltage across the matched circuit structure.

The subject matter of Example 1 through Example 25 may be combined in any combination.

The above description and the drawings illustrate some embodiments to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.