Semiconductor memory device and manufacturing method of the semiconductor memory device

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2019-0138568, filed on Nov. 1, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor memory device and a manufacturing method of the semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a manufacturing method of the three-dimensional semiconductor memory device.

2. Related Art

A semiconductor memory device may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may include a plurality of memory cells and the peripheral circuit may be configured to perform various operations of the memory cells.

The plurality of memory cells may be arranged in three dimensions to form a three-dimensional semiconductor memory device. In the three-dimensional semiconductor memory device, gate electrodes of the memory cells may be coupled to a plurality of word lines stacked over a substrate. To improve integration density of the three-dimensional semiconductor memory device, the number of word lines stacked on top of each other may be increased. The more word lines are stacked on top of each other, the more complicated manufacturing processes of a semiconductor memory device may become.

SUMMARY

According to an embodiment, a semiconductor memory device may include a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

According to an embodiment, a method of manufacturing a semiconductor memory device may include forming a preliminary structure including a first semiconductor pattern and a second semiconductor pattern separated from each other by an insulating layer, forming a stack structure including interlayer insulating layers and sacrificial layers alternately stacked on each other over the preliminary structure, forming a channel hole and a first contact hole passing through the stack structure, forming a memory layer on a surface of each of the channel hole and the first contact hole, filling the channel hole with a channel structure, forming a first contact plug in the first contact hole, and replacing the sacrificial layers by conductive patterns. The channel hole may overlap the first semiconductor pattern and the first contact hole may overlap the second semiconductor pattern. The first contact plug may pass through the memory layer in the first contact hole and the second semiconductor pattern. The conductive patterns may surround the channel structure and the first contact plug with the memory layer interposed between each of the conductive patterns and each of the channel structure and the first contact plug.

DETAILED DESCRIPTION

The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Embodiments may be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein.

Various embodiments are directed to a semiconductor memory device capable of simplifying manufacturing processes of the semiconductor memory device and a manufacturing method of the semiconductor memory device.

FIG. 1is a schematic diagram illustrating a configuration of a semiconductor memory device according to an embodiment.

Referring toFIG. 1, the semiconductor memory device may include a peripheral circuit and a memory cell array disposed over a substrate201shown inFIG. 6which includes a first region A1and a second region A2. The first region A1may be defined as a region that overlaps gate stack structures GST forming the memory cell array. The second region A2may be defined as a region that does not overlap the gate stack structures GST.

Although not illustrated inFIG. 1, the peripheral circuit may include a row decoder, a page buffer, control logic, and the like. The row decoder, the page buffer, and the control logic may include transistors TR. A first group of transistors among the transistors TR included in the peripheral circuit may be disposed in the second region A2of the substrate. A second group of transistors among the transistors TR included in the peripheral circuit may be disposed in the first region A1of the substrate and may overlap the gate stack structures GST. A gate electrode213of each of the transistors TR may be disposed in an active region ACT defined in the substrate. Junctions JN shown inFIG. 6which serve as a source and a drain of each of the transistors TR may be formed in the active regions ACT in opposite sides of the gate electrode213.

The gate stack structures GST may be spaced apart from each other by a slit SI. Each of the gate stack structures GST may include a cell array region CAR and a stepped region STA. The stepped region STA may extend from the cell array region CAR. According to an embodiment, each of the gate stack structures GST may include two or more cell array regions CAR and the stepped structure STA disposed between adjacent cell array regions CAR. However, embodiments are not limited thereto. For example, the stepped structure STA of each of the gate stack structures GST may be disposed at an edge of the gate stack structure GST corresponding to the stepped structure STA.

The stepped structure STA may include a first contact region CA1and a second contact region CA2. The stepped structure of the gate stack structure GST may be coupled to gate contact plugs GCT shown inFIG. 2which are disposed in the first contact region CA1corresponding to the stepped structure. The stepped structure of the gate stack structure GST may be penetrated by first contact plugs PCT1shown inFIG. 2which are disposed in the second contact region CA2corresponding to the stepped structure.

The cell array region CAR may include a plurality of word lines WL shown inFIG. 5Aand select lines SSL and DSL shown inFIG. 5Awhich are coupled to memory strings. The memory strings may be coupled to bit lines BL disposed over the gate stack structures GST.

According to an embodiment, the transistors TR disposed in the second region A2may overlap a dummy stack structure disposed in the same level as the gate stack structures GST. According to an embodiment, a dummy stack structure may be omitted.

FIG. 2is a diagram illustrating the cell array region CAR and the stepped region STA of a semiconductor memory device according to an embodiment.

Referring toFIG. 2, the cell array region CAR of the gate stack structure GST may be penetrated by channel structures CH. The cell array region CAR of the gate stack structure GST may extend in a first direction D1and a second direction D2. The channel structures CH may extend in a third direction D3orthogonal to a plain extending in the first direction D1and the second direction D2. According to an embodiment, the first direction D1, the second direction D2, and the third direction D3may correspond to an x-axis, a y-axis, and a z-axis of a Cartesian coordinate system.

A sidewall of each of the channel structures CH may be surrounded by a memory layer81. The channel structures CH may be disposed in the gate stack structure GST corresponding to the channel structures. The channel structures CH may be arranged in zigzag. The array of the channel structures CH is not limited thereto. In an embodiment, the array of the channel structures CH may form a matrix structure. Each of the channel structures CH may have one of various cross-sectional shapes, including, but not limited to, a circle, an ellipse, a polygon, or a square.

The channel structures CH may be arranged in opposite sides of an upper slit USI that is formed in the gate stack structure GST. The upper slit USI and the slit SI may extend in the first direction D1and the third direction D3.

The stepped structure STA of the gate stack structure GST may include the first contact region CA1coupled to the gate contact plugs GCT and the second contact region CA2penetrated by the first contact plugs PCT1as described with reference toFIG. 1. The semiconductor memory device may further include supporting pillars SP passing through the stepped region STA of the gate stack structure GST.

Each of the gate contact plugs GCT, the supporting pillars SP, and the first contact plugs PCT1may have one of various cross-sectional shapes, including, but not limited to, an ellipse, a polygon, or a square. Arrangement of the gate contact plugs GCT, the supporting pillars SP, and the first contact plugs PCT1is not limited to the embodiment illustrated inFIG. 2but may be variously changed. In a plane extending in the first direction D1and the second direction D2, the area of each of the supporting pillars SP and the first contact plugs PCT1may be greater than the area of each of the channel structures CH.

The gate contact plugs GCT may overlap the stepped region STA and may extend in the third direction D3. A sidewall of each of the first contact plugs PCT1may be surrounded by a first insulating structure IS1. Each of the first contact plugs PCT1may be insulated from the gate stack structure GST by the first insulating structure IS1. A sidewall of each of the supporting pillars SP may be surrounded by a first dummy memory layer81d1. The first dummy memory layer81d1may include the same material as the memory layer81.

Referring toFIGS. 3A to 3C, the gate stack structure GST may include interlayer insulating layers41and63and conductive patterns CP1to CPn alternately stacked on each other, where n is a natural number. The conductive patterns CP1to CPn may be stacked to be spaced apart from each other in the third direction D3by the interlayer insulating layers41or63disposed therebetween. The conductive patterns CP1to CPn may include various conductive materials such as a doped semiconductor, a metal, and a conductive metal nitride. Each of the conductive patterns CP1to CPn may include a single conductive material or two or more conductive materials. The interlayer insulating layers41and63may include a silicon oxide layer.

Each of the channel structures CH passing through the gate stack structure GST may be spaced apart from the conductive patterns CP1to CPn by the memory layer81. Each of the supporting pillars SP passing through the gate stack structure GST may be spaced apart from the conductive patterns CP1to CPn by the first dummy memory layer81d1.

Each of the supporting pillars SP may include the same material as each of the channel structures CH. According to an embodiment, each of the channel structures CH and supporting pillars SP may include a channel layer83, a core insulating pattern85, and a capping pattern91. The channel layer83may be formed on the memory layer81or the first dummy memory layer81d1corresponding to the channel layer83and may include a semiconductor material. For example, the channel layer83may include silicon. The channel layer83of each of the channel structures CH may be used as a channel of a memory string. The core insulating pattern85and the capping pattern91may fill the central region of the channel layer83. The core insulating pattern85may include an oxide. The capping pattern91may be disposed on the core insulating pattern85and may have a sidewall surrounded by an upper end of the channel layer83. The capping pattern91may include a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. For example, the capping pattern91may include a doped silicon layer. According to an embodiment, the core insulating pattern85may be omitted and the channel layer83may fill the central region of the memory layer81or the first dummy memory layer81d1corresponding to the channel layer83.

One gate stack structure GST may be spaced apart from another gate stack structure GST adjacent thereto by the slit SI. A depth of the upper slit USI passing through an upper part of the gate stack structure GST may be smaller than a depth of the slit SI in the third direction D3. According to an embodiment, the upper slit USI may be deep enough to pass through at least the uppermost conductive pattern CPn among the conductive patterns CP1to CPn. However, embodiments are not limited thereto. For example, the upper slit USI may pass through one or more conductive patterns successively disposed under the nth conductive pattern CPn. A conductive pattern, for example, CPn, which is penetrated by the upper silt USI, may be separated into select lines. The conductive patterns which serve as the word lines WL shown inFIG. 5Amight not be penetrated by the upper slit USI.

The first contact plugs PCT1may pass through the stepped structure of the gate stack structure GST. The first insulating structure IS1surrounding each of the first contact plugs PCT1may include a second dummy memory layer81d2that includes the same material as the memory layer81. The first insulating structure IS1may further include an oxide layer95disposed between the second dummy memory layer81d2and the first contact plug PCT1corresponding to the second dummy memory layer81d2.

Each of the channel structures CH, the supporting pillars SP, and the first contact plugs PCT1may be formed in a hole passing through the gate stack structure GST. According to an embodiment, the hole may have a structure in which a lower hole and an upper hole are coupled together. The lower hole may be defined as a part passing through a first stack structure G1that forms a lower part of the gate stack structure GST and the upper hole may be defined as a part passing through a second stack structure G2that forms an upper part of the gate stack structure GST. The interlayer insulating layers41and63may be classified into first interlayer insulating layers41included in the first stack structure G1and second interlayer insulating layers63included in the second stack structure G2. The conductive patterns CP1to CPn may include conductive patterns of a first group (CP1to CPk) included in the first stack structure G1and conductive patterns of a second group (CPk+1 to CPn) included in the second stack structure G2, where k is a natural number less than n. The lower hole may be deep enough to pass through the first stack structure G1, and the upper hole may be deep enough to pass through the second stack structure G2. An etching process for forming each of the lower hole and the upper hole may be easier than an etching process for forming a hole having a depth to pass through both the first and second stack structures G1and G2. When the lower hole and the upper hole are separately formed as described above, an undercut region may be defined at a boundary between the lower hole and the upper hole. Embodiments are not limited to the structure in which the undercut region is defined at the boundary between the lower hole and the upper hole, and a sidewall of each of the channel structures CH, the supporting pillars SP, and the first contact plugs PCT1may be substantially flat.

The conductive patterns CP1to CPn of the gate stack structure GST may be coupled to the gate contact plugs GCT. The gate contact plugs GCT may be coupled to parts of the conductive patterns CP1to CPn forming the stepped structure, respectively, and may extend in the third direction D3.

A rise defined by the stepped structure may be covered by a gap-fill insulating structure. The gap-fill insulating structure may include a first gap-fill insulating layer50covering a rise defined by the first stack structure G1and a second gap-fill insulating layer68covering a rise defined by the second stack structure G2. The gap-fill insulating structure and the gate stack structure GST may be covered by an upper insulating layer99. The channel structures CH may extend to pass through the upper insulating layer99. Each of the supporting pillars SP, the gate contact plugs GCT, and the first contact plugs PCT1may pass through the upper insulating layer99, and the first and second gap-fill insulating layers50and68of the gap-fill insulating structure.

The gate stack structure GST may be disposed on semiconductor patterns20A and20B separated from each other by an insulating layer35. The semiconductor patterns20A and20B may include a first semiconductor pattern20A and second semiconductor patterns20B.

Each of the first and second semiconductor patterns20A and20B may include a first semiconductor layer21and a second semiconductor layer29. The second semiconductor layer29may be spaced apart from the first semiconductor layer21and may extend along the bottom surface of the gate stack structure GST. The first semiconductor pattern20A may include a channel coupling pattern121disposed between the first semiconductor layer21and the second semiconductor layer29corresponding to the first semiconductor pattern20A, and each of the second semiconductor patterns20B may include a sacrificial stack structure SA disposed between the first semiconductor layer21and the second semiconductor layer29. The sacrificial stack structure SA may include a first protective layer23, a sacrificial layer25, and a second protective layer27sequentially stacked over the first semiconductor layer21.

The first semiconductor layer21and the channel coupling pattern121may include an n-type or p-type impurity. According to an embodiment, the channel coupling pattern121and the first semiconductor layer21including an n-type impurity may be used for a gate induced drain leakage (GIDL) erase method that performs an erase operation by using a GIDL. According to an embodiment, the channel coupling pattern121and the first semiconductor layer21including a p-type impurity may be used for a well erase method that performs an erase operation by supplying a hole. The second semiconductor layer29may be an undoped semiconductor layer or a doped semiconductor layer including the same type of impurity as the first semiconductor layer21and the channel coupling pattern121. The sacrificial layer25may include a material having a different etch rate from the first protective layer23and the second protective layer27to selectively etch the sacrificial layer25. For example, the sacrificial layer25may include an undoped silicon layer. Each of the first protective layer23and the second protective layer27may include an oxide layer.

The first semiconductor pattern20A may extend to overlap the slit SI and the channel structures CH. The slit SI may pass through the second semiconductor layer29of the first semiconductor pattern20A. An oxide layer125may be formed between the slit SI and the first semiconductor pattern20A.

The first semiconductor pattern20A may extend to overlap the supporting pillars SP. The first semiconductor pattern20A may overlap a part of the stepped structure penetrated by the supporting pillars SP.

The channel structures CH and the supporting pillars SP may extend into the first semiconductor pattern20A. According to an embodiment, the channel structures CH and the supporting pillars SP may extend into the first semiconductor layer21of the first semiconductor pattern20A.

The memory layer81may be divided into a first memory pattern P1and a second memory pattern P2. The first memory pattern P1may be disposed between the channel structure CH corresponding to the first memory pattern P1and the first semiconductor layer21of the first semiconductor pattern20A, and the second memory pattern P2may be disposed between the channel structure CH corresponding to the second memory pattern P2and the gate stack structure GST.

The first dummy memory layer81d1may be divided into a first dummy pattern P1dand a second dummy pattern P2d. The first dummy pattern P1dmay be disposed between the supporting pillar SP corresponding to the first dummy pattern P1dand the first semiconductor layer21of the first semiconductor pattern20A, and the second dummy pattern P2dmay be disposed between the supporting pillar SP corresponding to the second dummy pattern P2dand the gate stack structure GST.

The first semiconductor layer21of the first semiconductor pattern20A may surround a lower part of each of the channel structures CH and a lower part of each of the supporting pillars SP. The second semiconductor layer29of the first semiconductor pattern20A may extend along the bottom surface of the gate stack structure GST to surround the channel structures CH and the supporting pillars SP. The channel coupling pattern121may extend between the first memory pattern P1and the second memory pattern P2to contact the channel structures CH. The channel coupling pattern121may extend between the first dummy pattern P1dand the second dummy pattern P2dto contact the supporting pillars SP.

The second semiconductor patterns20B may be penetrated by the first contact plugs PCT1. A width of each of the second semiconductor patterns20B may be greater than a width of the first contact plug PCT1. The first semiconductor layer21, the first protective layer23, the sacrificial layer25, the second protective layer27, and the second semiconductor layer29of each of the second semiconductor patterns20B may surround the first contact plug PCT1. Each of the first contact plugs PCT1may pass through the first insulating structure IS1and may extend farther than the first insulating structure IS1.

A first vertical doped semiconductor pattern31A may be formed on a sidewall of the first semiconductor pattern20A, and a second vertical doped semiconductor pattern31B may be formed on a sidewall of each of the second semiconductor patterns20B. The first vertical doped semiconductor pattern31A and the second vertical doped semiconductor pattern31B may include an n-type or p-type impurity. According to an embodiment, the first vertical doped semiconductor pattern31A and the second vertical doped semiconductor pattern31B may include the same type of impurity as the first semiconductor layer21.

The semiconductor patterns20A and20B may be disposed on a lower insulating layer10penetrated by lower contact plugs11A and11B. The lower contact plugs11A and11B may include a first lower contact plug11A coupled to the first semiconductor pattern20A and second lower contact plugs11B coupled to the first contact plugs PCT1, respectively.

The first semiconductor pattern20A and the first vertical doped semiconductor pattern31A may overlap the first lower contact plug11A, and each of the first contact plugs PCT1and each of the second semiconductor patterns20B may overlap the second lower contact plug11B. Each of the first contact plugs PCT1may pass through the second semiconductor pattern20B to contact the second lower contact plug11B.

FIG. 4is a cross-sectional diagram illustrating a part of a semiconductor memory device according to an embodiment. The part of the semiconductor memory device shown inFIG. 4may overlap the second region A2shown inFIG. 1.

Referring toFIG. 4, the lower insulating layer10and the insulating layer35described with reference toFIGS. 3A to 3Cmay extend to overlap the second region A2described with reference toFIG. 1.

The lower contact plugs passing through the lower insulating layer10may further include a third lower contact plug11C. The semiconductor patterns divided by the insulating layer35may further include a third semiconductor pattern20C.

The third semiconductor pattern20C may include the same material as the second semiconductor pattern20B shown inFIG. 3B. The third semiconductor pattern20C may include the first semiconductor layer21, the first protective layer23, the sacrificial layer25, the second protective layer27, and the second semiconductor layer29that are sequentially stacked on one another. The third semiconductor pattern20C may overlap the third lower contact plug11C. A third vertical doped semiconductor pattern31C may be formed on a sidewall of the third semiconductor pattern20C. The third vertical doped semiconductor pattern31C may include the same type of impurity as the first semiconductor layer21.

The third semiconductor pattern20C and the third vertical doped semiconductor pattern31C may be covered by a dummy stack structure DST. The dummy stack structure DST may include dummy interlayer insulating layers41dand63dand sacrificial layers43and61alternately stacked over the third semiconductor pattern20C and the third vertical doped semiconductor pattern31C. The dummy interlayer insulating layers41dand63dmay include the same material as the interlayer insulating layers41and63described with reference toFIGS. 3A to 3C, and the dummy interlayer insulating layers41dmay be disposed in the same level as the interlayer insulating layers41and the dummy interlayer insulating layers63dmay be disposed in the same level as the interlayer insulating layers63. The sacrificial layers43and61may be disposed in the same level as the conductive patterns CP1to CPn described with reference toFIGS. 3A to 3C, respectively. The sacrificial layers43and61may include material having a different etch rate from the dummy interlayer insulating layers41dand63dto selectively etch the sacrificial layers43and61. For example, each of the sacrificial layers43and61may include a nitride layer.

The dummy stack structure DST and the third semiconductor pattern20C may be penetrated by a second contact plug PCT2. The second contact plug PCT2may extend to contact the third lower contact plug11C.

A sidewall of the second contact plug PCT2may be surrounded by a second insulating structure IS2. The second insulating structure IS2may include the same material as the first insulating structure IS1described with reference toFIG. 3B. According to an embodiment, the second insulating structure IS2may include a third dummy memory layer81d3having the same material as the memory layer81shown inFIGS. 3A and 3B, and the oxide layer95disposed between the third dummy memory layer81d3and the second contact plug PCT2.

The second contact plug PCT2may be formed in a hole passing through the dummy stack structure DST. The hole may be formed by a forming process of a lower hole that passes through a lower stack structure40forming a lower part of the dummy stack structure DST, and by a forming process of an upper hole that passes through an upper stack structure60forming an upper part of the dummy stack structure DST. According to this embodiment, an undercut region may be defined at a boundary between the lower hole and the upper hole. Embodiments are not limited to the structure in which the undercut region is defined at the boundary between the lower hole and the upper hole, and a sidewall of the second contact plug PCT2may be substantially flat. Embodiments are not limited to a method of manufacturing the hole by the forming process of the lower hole and the forming process of the upper hole.

The upper insulating layer99described with reference toFIGS. 3A to 3Cmay extend to cover the dummy stack structure DST and may be penetrated by the second contact plug PCT2. A width of the third semiconductor pattern20C may be greater than a width of the second contact plug PCT2.

The first, second, and third lower contact plugs11A,11B, and11C and the first and second contact plugs PCT1and PCT2shown inFIGS. 3A to 3C and 4may include various conductive materials capable of transmitting an electrical signal.

FIG. 5Ais a diagram illustrating a memory string according to an embodiment, andFIG. 5Bis a diagram illustrating a memory layer according to an embodiment.

Referring toFIG. 5A, a memory string may be coupled to the plurality of word lines WL and the select lines SSL and DSL. The select lines SSL and DSL may include at least one source select line SSL and at least one drain select line DSL. The word lines WL may be disposed between the source select line SSL and the drain select line DSL. The source select line SSL may be coupled to a gate electrode of a source select transistor, the drain select line DSL may be coupled to a gate electrode of a drain select transistor, and the word lines WL may be coupled to gate electrodes of memory cells.

The conductive patterns CP1to CPn described with reference toFIGS. 3A to 3Cmay form the source select line SSL, the word lines WL, and the drain select line DSL. According to an embodiment, among the conductive patterns CP1to CPn, the first conductive pattern CP1adjacent to the first semiconductor pattern20A may serve as the source select line SSL and the nth conductive pattern CPn disposed farthest from the first semiconductor pattern20A may serve as the drain select line DSL. Conductive patterns between the source select line SSL and the drain select line DSL may serve as the word lines WL. According to an embodiment, one or more conductive patterns successively disposed over the first conductive pattern CP1may serve as another source select line, and one or more conductive patterns successively disposed under the nth conductive pattern CPn may serve as another drain select line.

According to the structure described above, a drain select transistor may be formed in an intersection of the drain select line DSL and the channel structure CH, a source select transistor may be formed in an intersection of the source select line SSL and the channel structure CH, and memory cells may be formed in intersections of the word lines WL and the channel structure CH. The memory cells may be coupled in series between the source select transistor and the drain select transistor by the channel layer83of the channel structure CH. The source select transistor may be coupled to the channel coupling pattern121of the first semiconductor pattern20A by the channel layer83. The capping pattern91of the channel structure CH may serve as a junction of the drain select transistor.

The memory layer81may extend between the channel structure CH and each of the first semiconductor layer21and the second semiconductor layer29of the first semiconductor pattern20A. Each of the first memory pattern P1and the second memory pattern P2of the memory layer81may include a tunnel insulating layer TI, a data storage layer DL, and a blocking insulating layer BI as shown inFIG. 5B.

FIG. 5Billustrates a cross section of the memory layer81surrounding the channel layer83.

Referring toFIG. 5B, the central region of the memory layer81may be filled with the channel layer83, the core insulating pattern85, and the capping pattern91shown inFIG. 5A. The tunnel insulating layer TI of the memory layer81may surround the channel layer83, the data storage layer DL of the memory layer81may surround the tunnel insulating layer TI, and the blocking insulating layer BI of the memory layer81may surround the data storage layer DL.

The data storage layer DL may include a material layer capable of storing data changed by using Fowler-Nordheim tunneling. The data storage layer DL may include various materials, for example, a charge trap layer. The charge trap layer may include a nitride layer. Embodiments are not limited thereto, and the data storage layer DL may include a phase-change material, nanodots, or the like. The blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunnel insulating layer TI may include a silicon oxide layer enabling charge tunneling.

Each of the first dummy memory layer81d1shown inFIG. 3A, the second dummy memory layer81d2shown inFIG. 3B, and the third dummy memory layer81d3shown inFIG. 4may include the same material layers as the tunnel insulating layer TI, the data storage layer DL, and the blocking insulating layer BI described above.

FIG. 6is a cross-sectional diagram illustrating a lower structure LS of a semiconductor memory device according to an embodiment.

Referring toFIG. 6, the lower structure LS may be disposed between the substrate201including the first region A1and the second region A2and the lower insulating layer10penetrated by the first, second, and third lower contact plugs11A,11B, and11C.

The lower structure LS may include the plurality of transistors TR, a discharge impurity region DCI, and interconnection structures221. The plurality of transistors TR may be formed over active regions. The active regions and the discharge impurity region DCI may be separated from each other by isolation layers203formed in the substrate201. The interconnection structures221may be connected to the transistors TR and the discharge impurity region DCI. The discharge impurity region DCI and the transistors TR may be covered by an insulating-layer stack structure220in which two or more insulating layers are stacked and the interconnection structures221may pass through the insulating-layer stack structure220.

The discharge impurity region DCI may be formed in the substrate201. The discharge impurity region DCI may be connected to the first lower contact plug11A via the interconnection structure221corresponding to the discharge impurity region DCI. The discharge impurity region DCI may be provided to discharge charges accumulated in the first semiconductor pattern20A.

Each of the transistors TR may include a gate insulating layer211, the gate electrode213, and the junctions JN. The gate insulating layer211and the gate electrode213of each of the transistors TR may be stacked over an active region. The junctions JN of the transistors TR may be formed by injecting an n-type or p-type impurity into active regions that protrude at opposite sides of the corresponding gate electrode213.

Each of the first contact plugs PCT1passing through the stepped region STA of the gate stack structure GST may be connected to the transistor TR via the second lower contact plug11B and the interconnection structure221.

A transistor disposed in the second region A2among the transistors TR may be connected to the second contact plug PCT2passing through the dummy stack structure DST via the interconnection structure221and the third lower contact plug11C corresponding to the transistor disposed in the second region A2.

FIG. 7is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

Referring toFIG. 7, a method of manufacturing a semiconductor memory device may include step ST1for forming a preliminary structure, step ST3for forming a stack structure, step ST5for forming a channel structure, a supporting pillar, and contact plugs, and step ST7for forming a channel coupling pattern.

A substrate including a lower structure and lower contact plugs may be formed before step ST1is performed. The lower structure may include the lower structure LS described with reference toFIG. 6, and the lower contact plugs may include the first, second, and third lower contact plugs11A,11B, and11C described with reference toFIGS. 3A to 3C, 4, and 6. The preliminary structure may be formed over the substrate including the lower structure and the lower contact plugs at step ST1.

At step ST3, the stack structure may be formed to have a stepped structure, and may be penetrated by a channel hole, a dummy hole, and contact holes. According to an embodiment, step ST3may include forming a first stepped structure which forms a lower part of the stack structure and forming a second stepped structure which forms an upper part of the stack structure. However, embodiments are not limited thereto. According to an embodiment, step ST3may include stacking a plurality of material layers as much as a height of a target stack structure and forming a stepped structure by etching the plurality of material layers.

Step ST5may include forming a memory layer on a sidewall of each of the channel hole, the dummy hole, and the contact holes, forming a channel structure and a supporting pillar in the channel hole and the dummy hole, respectively, and forming contact plugs in the contact holes. Accordingly, each of the channel structure, the supporting pillar, and the contact plugs may be surrounded by the memory layer.

Step ST7may include partially exposing the sidewall of the channel structure and forming a channel coupling pattern contacting the exposed sidewall of the channel structure.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment is described with reference toFIGS. 8A to 8C, 9A to 9J, 10A to 10K, 11A to 11C, 12A, 12B, 13, 14A, and 14B. The figures below are cross-sectional diagrams of structures according to manufacturing steps. The figures below are cross-sectional diagrams taken along line I-I′, line II-II′, and line III-III′ and corresponding to the second region A2. The figures below illustrate an embodiment regarding a method of manufacturing a semiconductor memory device including the structures shown inFIGS. 3A to 3C and 4.

Referring toFIG. 8A, lower contact plugs311A,311B, and311C passing through a lower insulating layer300may be formed over the substrate201including the lower structure LS shown inFIG. 6before step ST1is performed. The lower contact plugs311A,311B, and311C may include various conductive materials capable of transmitting an electrical signal.

The lower contact plugs311A,311B, and311C may include a first lower contact plug311A, a second lower contact plug311B, and a third lower contact plug311C. The first lower contact plug311A may be connected to the discharge impurity region DCI shown inFIG. 6. The second lower contact plug311B and the third lower contact plug311C may be connected to corresponding transistors, respectively, among the transistors TR of the peripheral circuit shown inFIG. 6.

Referring toFIG. 8B, step ST1may include forming a preliminary first semiconductor pattern320A1, a second semiconductor pattern320B, and a third semiconductor pattern320C separated from each other.

The preliminary first semiconductor pattern320A1may overlap the first lower contact plug311A, the second semiconductor pattern320B may overlap the second lower contact plug311B, and the third semiconductor pattern320C may overlap the third lower contact plug311C. An edge of the preliminary first semiconductor pattern320A1may overlap the first lower contact plug311A. A width of the second semiconductor pattern320B may be greater than a width of the second lower contact plug311B and the second semiconductor pattern320B may protrude toward opposite sides of the second lower contact plug311B. A width of the third semiconductor pattern320C may be greater than a width of the third lower contact plug311C and the third semiconductor pattern320C may protrude toward opposite sides of the third lower contact plug311C.

Forming the preliminary first semiconductor pattern320A1, the second semiconductor pattern320B, and the third semiconductor pattern320C may include sequentially stacking a first semiconductor layer321, a sacrificial stack structure305, and a second semiconductor layer329over the lower insulating layer300to cover the first, second, and third lower contact plugs311A,311B, and311C and etching the first semiconductor layer321, the sacrificial stack structure305, and the second semiconductor layer329.

The first semiconductor layer321may include an n-type or p-type impurity. The sacrificial stack structure305may include a first protective layer323, a sacrificial layer325, and a second protective layer327that sequentially stacked on each other. The sacrificial layer325may include a material having a different etch rate from the first protective layer323and the second protective layer327to selectively etch the sacrificial layer325, and the first protective layer323and the second protective layer327may include a material capable of protecting the first semiconductor layer321and the second semiconductor layer329when the sacrificial layer325is etched. For example, the sacrificial layer325may include an undoped silicon layer. Each of the first protective layer323and the second protective layer327may include an oxide layer. The second semiconductor layer329may include an undoped semiconductor layer or a doped semiconductor layer including an n-type or p-type impurity. At least one of the first protective layer323, the second protective layer327, and the second semiconductor layer329may be omitted.

Referring toFIG. 8C, step ST1may include forming a first vertical doped semiconductor pattern331A, a second vertical doped semiconductor pattern331B, and a third vertical doped semiconductor pattern331C on sidewalls of the preliminary first semiconductor pattern320A1, the second semiconductor pattern320B, and the third semiconductor pattern320C, respectively. The first, second, and third vertical doped semiconductor patterns331A,331B, and331C may include the same impurity as the first semiconductor layer321described with reference toFIG. 8B.

Step ST1may include filling spaces among the preliminary first semiconductor pattern320A1, the second and third semiconductor patterns320B and320C with an insulating layer335.

The preliminary structure including the preliminary first semiconductor pattern320A1and the second and third semiconductor patterns320B and320C that overlap the first, second, and third lower contact plugs311A,311B, and311C, respectively, and that are separated from each other by the insulating layer335may be formed by the processes described above with reference toFIGS. 8A to 8C.

Referring toFIG. 9A, step ST3may include forming a first stack structure340on the preliminary structure. The first stack structure340may include first interlayer insulating layers341and first sacrificial layers343alternately stacked on each other. The first interlayer insulating layers341may include a first material layer and the first sacrificial layers343may include a second material layer. The second material layer may include an insulating material having a different etch rate from the first material layer to selectively etch the second material layer. For example, the first material layer may include an oxide layer and the second material layer may include a nitride layer.

Referring toFIG. 9B, step ST3may include etching the first stack structure340to form a first stepped structure SW1.

Referring toFIG. 9C, step ST3may include forming a first gap-fill insulating layer350covering the first stepped structure SW1shown inFIG. 9B. A rise defined by the first stepped structure SW1may be covered by the first gap-fill insulating layer350.

Referring toFIG. 9D, step ST3may include forming lower holes351A to351D. The lower holes351A to351D may be simultaneously formed. The lower holes351A to351D may include a first lower hole351A, a second lower hole351B, a third lower hole351C, and a fourth lower hole351D.

The first lower hole351A may pass through the first stack structure340and may extend into the preliminary first semiconductor pattern320A1. The first lower hole351A may pass through the second semiconductor layer329, the second protective layer327, the sacrificial layer325, and the first protective layer323of the preliminary first semiconductor pattern320A1and may extend into the first semiconductor layer321.

The second lower hole351B may pass through the first gap-fill insulating layer350covering the first stepped structure SW1shown inFIG. 9Band the first stepped structure SW1under the first gap-fill insulating layer350or may pass through a part of the first stack structure340adjacent to the first stepped structure SW1. The second lower hole351B may pass through the second semiconductor layer329, the second protective layer327, the sacrificial layer325, and the first protective layer323of the preliminary first semiconductor pattern320A1and may extend into the first semiconductor layer321.

The third lower hole351C may pass through a part of the first stack structure340overlapping the second semiconductor pattern320B. The third lower hole351C may pass through a part of the first stepped structure SW1shown inFIG. 9Band the first gap-fill insulating layer350over the part of the first stepped structure SW1. The third lower hole351C may pass through the second semiconductor layer329, the second protective layer327, the sacrificial layer325, and the first protective layer323of the second semiconductor pattern320B and may extend into the first semiconductor layer321. A width of the third lower hole351C may be smaller than a width of the second semiconductor pattern320B.

The fourth lower hole351D may pass through a part of the first stack structure340overlapping the third semiconductor pattern320C. The fourth lower hole351D may pass through the second semiconductor layer329, the second protective layer327, the sacrificial layer325, and the first protective layer323of the third semiconductor pattern320C and may extend into the first semiconductor layer321. A width of the fourth lower hole351D may be smaller than a width of the third semiconductor pattern320C.

When an etching process for forming the first, second, third, and fourth lower holes351A,351B,351C, and351D is performed, each of the preliminary first semiconductor pattern320A1and the second and third semiconductor patterns320B and320C may serve as an etch stop layer.

Referring toFIG. 9E, step ST3may include filling the first, second, third, and fourth lower holes351A,351B,351C, and351D with vertical sacrificial layers353. The vertical sacrificial layers353may include a material having a different etch rate from the first material layer and the second material layer described above with reference toFIG. 9Ato selectively remove the vertical sacrificial layers353. According to an embodiment, the vertical sacrificial layers353may include metal such as tungsten.

Referring toFIG. 9F, step ST3may include forming a second stack structure360on the first stack structure340having the first stepped structure that is penetrated by the vertical sacrificial layers353and covered by the first gap-fill insulating layer350. The second stack structure360may include second sacrificial layers363and second interlayer insulating layers361alternately stacked on each other. The second interlayer insulating layers361may include the first material layer described with reference toFIG. 9Aand the second sacrificial layers363may include the second material layer described with reference toFIG. 9A.

Referring toFIG. 9G, step ST3may include etching the second stack structure360to form a second stepped structure SW2. A part of the second stack structure360which overlaps the first stepped structure SW1may be removed and the first stepped structure SW1might not overlap the second stack structure360having the second stepped structure SW2.

Referring toFIG. 9H, step ST3may include forming a second gap-fill insulating layer368covering the second stepped structure SW2shown inFIG. 9G. A rise defined by the second stepped structure SW2may be covered by the second gap-fill insulating layer368. Subsequently, a first mask layer371may be formed to cover the second gap-fill insulating layer368and the second stack structure360. The first mask layer371may include a nitride layer.

Referring toFIG. 9I, step ST3may include forming upper holes373A to373D. The upper holes373A to373D may be simultaneously formed. The upper holes373A to373D may include a first upper hole373A coupled to the first lower hole351A, a second upper hole373B coupled to the second lower hole351B, a third upper hole373C coupled to the third lower hole351C, and a fourth upper hole373D coupled to the fourth lower hole351D.

The first, second, third, and fourth upper holes373A,373B,373C, and373D may be formed by etching the first mask layer371, the second stack structure360, and the second gap-fill insulating layer368to expose the vertical sacrificial layers353. The first upper hole373A may pass through the second stack structure360. The second upper hole373B may pass through the second stepped structure SW2shown inFIG. 9Gor may pass through the second gap-fill insulating layer368overlapping the first stepped structure SW1shown inFIG. 9G. The third upper hole373C may pass through the second stepped structure of the second stack structure360that overlaps the third lower hole351C or may pass through the second gap-fill insulating layer368that overlaps the third lower hole351C. The fourth upper hole373D may pass through a part of the second stack structure360that overlaps the fourth lower hole351D.

Referring toFIG. 9J, step ST3may include removing the vertical sacrificial layers353shown inFIG. 9Ithrough the first, second, third, and fourth upper holes373A,373B,373C, and373D shown inFIG. 9I. Accordingly, a channel hole HA, a dummy hole HB, a first contact hole HC, and a second contact hole HD may be opened.

The channel hole HA may be defined by coupling the first lower hole351A to the first upper hole373A shown inFIG. 9Iand may expose the first semiconductor layer321of the preliminary first semiconductor pattern320A1. The dummy hole HB may be defined by coupling the second lower hole351B to the second upper hole373B shown inFIG. 9Iand may expose the first semiconductor layer321of the preliminary first semiconductor pattern320A1. The first contact hole HC may be defined by coupling the third lower hole351C to the third upper hole373C shown inFIG. 9Iand may expose the first semiconductor layer321of the second semiconductor pattern320B. The second contact hole HD may be defined by coupling the fourth lower hole351D to the fourth upper hole373D shown inFIG. 9Iand may expose the first semiconductor layer321of the third semiconductor pattern320C.

A stepped stack structure379having a stepped structure and penetrated by the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD may be formed by the processes described above with reference toFIGS. 9A to 9J. The channel hole HA, the dummy hole HB, the first and second contact holes HC and HD may be formed such that the channel hole HA and the dummy hole HB overlap the preliminary first semiconductor pattern320A1, the first contact hole HC overlaps the second semiconductor pattern320B, and the second contact hole HD overlaps the third semiconductor pattern320C.

Referring toFIG. 10A, step ST5may include forming a memory layer381on a surface of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, forming a channel layer383on the memory layer381, and filling the central region of the channel layer383with a core insulating layer385.

The memory layer381may be formed by sequentially stacking the blocking insulating layer BI, the data storage layer DL, and the tunnel insulating layer TI described with reference toFIG. 5B. The memory layer381may be simultaneously formed on the surfaces of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD.

According to an embodiment, the channel layer383may be conformally formed on the memory layer381and the core insulating layer385may be formed by filling the central region of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, which is not filled with the channel layer383, with a flowable material layer and then by hardening the flowable material layer. The flowable material layer may include polysilazane (PSZ).

Referring toFIG. 10B, step ST5may include removing an upper end of the core insulating layer385shown inFIG. 10Ato define a hollow portion HP in an upper end of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD. Accordingly, a core insulating pattern385P opening the upper end of the channel layer383may be defined.

Subsequently, step ST5may include forming a doped semiconductor layer391L to fill the hollow portion HP. The doped semiconductor layer391L may include at least one of an n-type impurity and a p-type impurity.

Referring toFIG. 10C, step ST5may include planarizing the doped semiconductor layer391L shown inFIG. 10Bto expose the first mask layer371. Accordingly, a capping pattern391surrounded by the upper end of the channel layer383may be formed.

A channel structure380A may be formed in the channel hole HA, a supporting pillar380B may be formed in the dummy hole HB, and a first dummy channel structure380C and a second dummy channel structure380D may be formed in the first contact hole HC and the second contact hole HD, respectively, by the processes described with reference toFIGS. 10A to 10C. According to an embodiment, each of the channel structure380A, the supporting pillar380B, the first and second dummy channel structures380C and380D may include the channel layer383, the core insulating pattern385P, and the capping pattern391.

Although not illustrated inFIG. 10C, according to an embodiment, the capping pattern391may be omitted and each of the channel structure380A, the supporting pillar380B, and the first and second dummy channel structures380C and380D may include the channel layer383filling the central region of the memory layer381.

Referring toFIG. 10D, step ST5may include forming a second mask layer393extending to cover the channel structure380A and the supporting pillar380B on the first mask layer371. The second mask layer393may be etched to expose the first dummy channel structure380C and the second dummy channel structure380D shown inFIG. 10C.

Subsequently, step ST5may include removing the capping pattern391shown inFIG. 10Cfrom each of the first contact hole HC and the second contact hole HD by an etching process using the second mask layer393as an etching barrier. Accordingly, the core insulating pattern385P may be exposed. When the capping pattern391is etched, the upper end of the channel layer383shown inFIG. 10Cmay be removed from the first contact hole HC and the second contact hole HD and a part of the channel layer383P may remain.

Referring toFIG. 10E, step ST5may include removing the core insulating pattern385P shown inFIG. 10Dfrom each of the first contact hole HC and the second contact hole HD by an etching process using the second mask layer393as an etching barrier.

Referring toFIG. 10F, step ST5may include removing the channel layer383P shown inFIG. 10Efrom each of the first contact hole HC and the second contact hole HD by an etching process using the second mask layer393as an etching barrier. Accordingly, the memory layer381formed along the surface of each of the first contact hole HC and the second contact hole HD may be exposed.

Referring toFIG. 10G, step ST5may include forming an oxide layer395on the memory layer381exposed on the surface of each of the first contact hole HC and the second contact hole HD. The oxide layer395may be formed to compensate for insulation characteristics of the memory layer381. According to an embodiment, forming the oxide layer395may be omitted.

Referring toFIG. 10H, step ST5may include forming a first contact hole extending portion EA coupled to the first contact hole HC and a second contact hole extending portion EB coupled to the second contact hole HD.

The first contact hole extending portion EA may pass through the memory layer381and the oxide layer395of the bottom surface of the first contact hole HC and pass through the first semiconductor layer321of the second semiconductor pattern320B to expose the second lower contact plug311B. The second contact hole extending portion EB may pass through the memory layer381and the oxide layer395of the bottom surface of the second contact hole HD and pass through the first semiconductor layer321of the third semiconductor pattern320C to expose the third lower contact plug311C. Hereinafter, a memory layer and an oxide layer remaining in each of the first and second contact holes HC and HD may be referred to as a dummy memory layer381P and an oxide layer pattern395P.

Referring toFIG. 10I, step ST5may include forming a first contact plug397A filling the first contact hole HC and the first contact hole extending portion EA and a second contact plug397B filling the second contact hole HD and the second contact hole extending portion EB.

The first contact plug397A and the second contact plug397B may include various conductive materials capable of transmitting an electrical signal. The first contact plug397A may contact the second lower contact plug311B and the second contact plug397B may contact the third lower contact plug311C. When the first contact plug397A and the second contact plug397B are formed, the second mask layer393shown inFIG. 10Hmay be removed.

Referring toFIG. 10J, after the first contact plug397A and the second contact plug397B are formed, the first mask layer371shown inFIG. 10Imay be removed.

Referring toFIG. 10K, a region from which the first mask layer is removed may be filled with a first upper insulating layer399. The first upper insulating layer399may surround upper ends of the channel structure380A, the supporting pillar380B, the first contact plug397A, and the second contact plug397B.

As described above with reference toFIGS. 10A to 10I, the dummy memory layer381P surrounding each of the first contact plug397A and the second contact plug397B may be formed by a process of forming the memory layer381that surrounds the channel structure380A. The dummy memory layer381P may serve as an insulating structure to insulate the first contact plug397A and the second contact plug397B.

Referring toFIG. 11A, forming an upper slit, forming an isolation insulting layer401filling the upper slit, and forming a second upper insulating layer411on the first upper insulating layer399may be performed before step ST7is performed. The second upper insulating layer411may extend to cover the channel structure380A, the supporting pillar380B, the first contact plug397A, and the second contact plug397B shown inFIG. 10K. The upper slit may correspond to the upper slit USI shown inFIGS. 2 and 3C.

Step ST7may include forming a slit413passing through the second upper insulating layer411, the first upper insulating layer399, and the stepped stack structure379. The slit413may extend into the preliminary first semiconductor pattern320A1. The slit413may pass through the second semiconductor layer329of the preliminary first semiconductor pattern320A1. The slit413may extend into the sacrificial layer325of the preliminary first semiconductor pattern320A1. The sacrificial layer325may be exposed through the bottom surface of the slit413.

Referring toFIG. 11B, step ST7may include removing the sacrificial layer325of the preliminary first semiconductor pattern320A1shown inFIG. 11Ato expose a memory layer through the slit413and dividing the memory layer into a first memory pattern381P1and a second memory pattern381P2by removing the exposed memory layer. When an etching process for removing the memory layer is performed, the first protective layer323and the second protective layer327of the preliminary first semiconductor pattern320A1shown inFIG. 11Amay be removed to expose the first semiconductor layer321and the second semiconductor layer329of the preliminary first semiconductor pattern320A1.

Hereinafter, a space disposed between the first semiconductor layer321and the second semiconductor layer329and extending between the first memory pattern381P1and the second memory pattern381P2may be defined as a horizontal space415. The horizontal space415may expose the channel layer383of the channel structure380A.

Referring toFIG. 11C, step ST7may include filling the horizontal space415shown inFIG. 11Bwith a channel coupling pattern421. The channel coupling pattern421may contact the first and second semiconductor layers321and329and the channel layer383. The channel coupling pattern421may include an n-type impurity or a p-type impurity.

The channel coupling pattern421may be formed by a selective growth method, for example, a Selective Epitaxial Growth (SEG) method using at least one of the first and second semiconductor layers321and329and the channel layer383as a seed layer. According to an embodiment, the channel coupling pattern421may be formed by a non-selective method such as a chemical vapor deposition (CVD) method.

A first semiconductor pattern320A2including the first semiconductor layer321, the second semiconductor layer329, and the channel coupling pattern421may be formed by the processes described above with reference toFIGS. 11A to 11C.

FIGS. 12A and 12Bare cross-sectional diagrams illustrating replacing the first sacrificial layers343described with reference toFIG. 9Aand the second sacrificial layers363described with reference toFIG. 9Fby conductive patterns.

Referring toFIG. 12A, an oxide layer425may be formed on a surface of the first semiconductor pattern320A2through the slit413. The oxide layer425may be formed by oxidizing a part of the first semiconductor pattern320A2.

Subsequently, first sacrificial layers and second sacrificial layers adjacent to the slit413may be selectively removed. Hereinafter, regions from which the first sacrificial layers and the second sacrificial layers are removed may be referred to as gate regions431. The gate regions431may be defined between the first and second interlayer insulating layers341and361.

Forming the conductive patterns433may include forming a barrier metal layer extending along surfaces of the gate regions431, forming a conductive layer thick enough to fill the gate regions431on the barrier metal layer, and etching the barrier metal layer and the conductive layer to be separated into the conductive patterns433. Accordingly, a gate stack structure430including the first and second interlayer insulating layers341and361and the conductive patterns433disposed between the first and second interlayer insulating layers341and361that neighbor each other may be formed.

FIG. 13is a cross-sectional diagram of an end of the first semiconductor pattern320A2formed by the processes described above with reference toFIGS. 11A to 11C, the stepped structure of the gate stack structure430formed by the processes described above with reference toFIGS. 12A and 12B, and the first and second sacrificial layers343and363remaining and forming a dummy stack structure440.

Referring toFIG. 13, the first vertical doped pattern331A may remain on a sidewall of the first semiconductor pattern320A2.

The gate stack structure430may surround the channel structure380A, the supporting pillar380B, and the first contact plug397A. The supporting pillar380B and the first contact plug397A may pass through the stepped structure of the gate stack structure430covered by the first gap-fill insulating layer350and the second gap-fill insulating layer368. The conductive patterns433of the gate stack structure430may surround the channel structure380A and parts of the conductive patterns433forming the stepped structure of the gate stack structure430may surround the supporting pillar380B and the first contact plug397A.

The channel coupling pattern421of the first semiconductor pattern320A2may not only extend between the first memory pattern381P1and the second memory pattern381P2but extend to contact the channel layer383of the supporting pillar380B. Accordingly, the memory layer surrounding the supporting pillar380B may be divided into a first dummy pattern381P1dand a second dummy pattern381P2d. The supporting pillar380B may be insulated from the conductive patterns433by the second dummy pattern381P2d.

The first contact plug397A may be insulated from the conductive patterns433by the dummy memory layer381P. Accordingly, according to an embodiment, operating characteristics of the semiconductor memory device may be secured even when a barrier structure for preventing formation of the conductive patterns433around the first contact plug397A is not separately formed. Therefore, the semiconductor memory device according to an embodiment may prevent processes from being difficult and defective due to a manufacturing process for forming a barrier structure.

When the gate stack structure430is formed, some of the first and second sacrificial layers343and363which are disposed in the second region A2spaced apart farther from the slit413shown inFIGS. 12A to 12Cthan the first region A1shown inFIG. 2might not be replaced by the conductive patterns433but may remain. The first and second sacrificial layers343and363remaining in the second region A2and the first and second interlayer insulating layers341and361may form the dummy stack structure440. The dummy stack structure440may overlap the third semiconductor pattern320C and may surround the second contact plug397B.

FIGS. 14A and 14Bare cross-sectional diagrams illustrating forming a bit-line contact plug451, a gate contact plug453, a first upper contact plug455, and a second upper contact plug457.

Referring toFIG. 14A, upper contact holes441,443,445, and447passing through at least one of the second upper insulating layer411, the first upper insulating layer399, the second gap-fill insulating layer368, and the first gap-fill insulating layer350may be formed. The supporting pillar380B may be covered by the second upper insulating layer411not to be externally exposed.

The upper contact holes441,443,445, and447may include a first upper contact hole441exposing the capping pattern391of the channel structure380A, a second upper contact hole443exposing corresponding one among the conductive patterns433, a third upper contact hole445exposing the first contact plug397A, and a fourth upper contact hole447exposing the second contact plug397B. The second upper contact hole443may overlap the stepped structure and may expose the conductive pattern433corresponding to the second upper contact hole443.

Referring toFIG. 14B, after each of the first, second, third, and fourth upper contact holes441,443,445, and447is filled with a conductive material, a surface of the conductive material may be planarized. Accordingly, the bit-line contact plug451, the gate contact plug453, the first upper contact plug455, and the second upper contact plug457may be formed.

The bit-line contact plug451may be coupled to the channel structure380A, the gate contact plug453may be coupled to the conductive pattern433corresponding to the gate contact plug453, the first upper contact plug455may be coupled to the first contact plug397A, and the second upper contact plug457may be coupled to the second contact plug397B.

Subsequently, processes, such as forming the bit line BL shown inFIG. 1, that are subsequent to the process of forming the bit-line contact plug451, the gate contact plug453, the first upper contact plug455, and the second upper contact plug457may be performed. The bit line BL may be coupled to the bit-line contact plug451.

FIG. 15is a block diagram illustrating a memory system1100according to an embodiment.

Referring toFIG. 15, the memory system1100may include a memory device1120and a memory controller1110.

The memory device1120may be a multi-chip package including a plurality of flash memory chips. The memory device1120may include a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a stepped structure, a contact plug passing through the stepped structure of the gate stack structure, and an insulating structure surrounding the contact plug.

The memory controller1110may be configured to control the memory device1120and may include Static Random Access Memory (SRAM)1111, a Central Processing Unit (CPU)1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111may serve as operational memory of the CPU1112, the CPU1112may perform general control operations for data exchange of the memory controller1110, and the host interface1113may include a data exchange protocol of a host accessing the memory system1100. In addition, the error correction block1114may detect and correct errors included in data read from the memory device1120, and the memory interface1115may perform interfacing with the memory device1120. In addition, the memory controller1110may further include Read Only Memory (ROM) for storing code data for interfacing with the host.

The memory system1100having the above-described configuration may be a Solid State Drive (SSD) or a memory card in which the memory device1120and the memory controller1110are combined. For example, when the memory system1100is an SSD, the memory controller1110may communicate with an external device (e.g., a host) through one of various interface protocols including, but not limited to, a Universal Serial Bus (USB), a MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), a Small Computer Small Interface (SCSI), an Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

FIG. 16is a block diagram illustrating a configuration of a computing system1200according to an embodiment.

Referring toFIG. 16, the computing system1200may include a CPU1220, Random Access Memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210that are electrically coupled to a system bus1260. In addition, when the computing system1200is a mobile device, a battery for supplying an operating voltage to the computing system1200may be further included, an application chipset, an image processor, mobile DRAM, and the like may be further included.

The memory system1210may include a memory device1212and a memory controller1211. The memory device1212may include a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a stepped structure, a contact plug passing through the stepped structure of the gate stack structure, and an insulating structure surrounding the contact plug.

According to the present disclosure, manufacturing processes may be simplified by forming a contact hole using a channel hole forming process.

According to the present disclosure, an insulating structure that is capable of insulating a contact plug disposed in a contact hole from a conductive pattern of a gate stack structure may be formed by a memory layer forming process, and thus manufacturing processes may be simplified.