Energy conversion device and method of forming the same

Various embodiments may provide a method of forming an energy conversion device. The method may include forming an electrolyte layer on the first surface of the semiconductor substrate. The method may also include forming a cavity on the second surface of the semiconductor substrate using a deep reactive ion etch. The method may further include enlarging said cavity by carrying out one or more wet etches so that the enlarged cavity is at least partially defined by a vertical arrangement comprising a first lateral cavity surface of the semiconductor substrate extending substantially along a first direction, and a second lateral cavity surface of the semiconductor substrate adjoining the first lateral cavity surface. The method may include forming a first electrode on a first surface of the electrolyte layer, and forming a second electrode on a second surface of the electrolyte layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority of Singapore application No. 10201504046S filed May 22, 2015, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

Various aspects of this disclosure relate to energy conversion devices and methods of forming the same.

BACKGROUND

Solid oxide fuel cells (SOFCs) are efficient energy conversion devices with flexible selection of hydrocarbon fuels. Currently, downscaling of electrolyte thickness to reduce ohmic resistance has been an effective way for further improving the performance of SOFCs at low operating temperatures below 500° C. For drastic reduction of electrolyte thickness to nanometer-scale, silicon-based microfabrication process using chemical etching has been successfully utilized for SOFCs.

Thin film electrolytes with nanoscale thicknesses of between 50 to 150 nm were fabricated previously by MEMS-based microfabrication processes with atomic layer deposition (ALD), sputtering, or pulsed laser deposition (PLD). Further, fuel cell performances from the yttria-stabilized zirconia (YSZ) electrolytes with superior power densities above 1000 mW/cm2at 500° C. were also reported.

Nevertheless, successful low-temperature SOFCs with a nanoscale thin electrolyte are currently only feasible in miniature scale due to severe residual stress on the membrane. A 50 nm thick, free-standing YSZ membrane is typically confined within only a few hundred micrometers in lateral dimensions, which limits the available electrochemically active area. Although superior power densities at reduced temperature have been reported elsewhere, the tininess of such SOFCs leads to insignificant power output of only at micro-watts scale, thereby limiting their applications as practical power sources.

It is virtually impractical to simply enlarge the size of such a thin membrane to increase surface area. Therefore, an effective method to scale up the nano thin film YSZ membrane SOFCs with robust mechanical strength of membranes is prerequisite for higher total power output.

To maximize electrochemically active area within a confined dimension, free-standing array μ-SOFCs has been fabricated. By creating free-standing corrugated YSZ electrolyte films from the pre-patterned silicon substrate, surface utilization was significantly increased by 30% to 64% on the silicon wafer. The array, which is 600 μm×600 μm, delivered a higher total power output of 3.1 mW at temperatures below 500° C. However, as individual cells featured free-standing and cup-shaped structure, there are many geometrical discontinuities, which may be mechanically weak points. The cells, which are arrayed on a square template, may undergo non-uniform membrane stress distribution. In particular, cells in the vicinity of each corner, where stress concentration experience is the highest, may be damaged, leading to membrane failures during fuel cell operation.

Kerman et al. (K. Kerman, T. Tallinen, S. Ramanathan and L. Mahadevan,Journal of Power Sources,2013, 222, 359-366) reported stress behavior around the boundaries of square thin film SOFCs by numerical simulation and confirmed that stress was highly concentrated at the corners of the square membrane.

Su et al. (P. C. Su and F. B. Prinz,Electrochemistry Communications,2012, 16, 77-79) presented electrolyte membrane array μ-SOFCs with silicon supporting layer to improve mechanical stability of the array membrane. Individual cells were supported by surrounding single crystal silicon and 6 mm by 6 mm square YSZ membrane electrolyte array was successfully demonstrated. Nevertheless, this structure has still stress concentration points at each corner of square templates.

SUMMARY

Various aspects of this disclosure provide a method of forming an energy conversion device. The method may include forming an electrolyte layer on the first surface of the semiconductor substrate. The method may also include forming a cavity on the second surface of the semiconductor substrate using a deep reactive ion etch. The method may further include enlarging said cavity by carrying out one or more wet etches so that the enlarged cavity is at least partially defined by a vertical arrangement comprising a first lateral cavity surface of the semiconductor substrate extending substantially along a first direction, and a second lateral cavity surface of the semiconductor substrate adjoining the first lateral cavity surface. The second lateral cavity may extend substantially along a second direction different from the first direction. The method may additionally include forming a first electrode on a first surface of the electrolyte layer. The method may also include forming a second electrode on a second surface of the electrolyte layer.

In various embodiments, an energy conversion device may be provided. The energy conversion device may include a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate may include an enlarged cavity on the second surface. The enlarged cavity may be at least partially defined by a vertical arrangement comprising a first lateral cavity surface extending substantially along a first direction, and a second lateral cavity surface adjoining the first lateral cavity surface. The second lateral cavity surface may extend substantially along a second direction different from the first direction. The energy conversion device may also include an electrolyte layer on the first surface of the semiconductor substrate. The energy conversion device may additionally include a first electrode on a first surface of the electrolyte layer. The energy conversion device may also include a second electrode on a second surface of the electrolyte layer.

DETAILED DESCRIPTION

In various embodiments, a method of forming an energy conversion device may be provided.FIG. 1is a diagram100illustrating a method of forming an energy conversion device may be provided according to various embodiments. The method may include, in102, forming an electrolyte layer on the first surface of the semiconductor substrate. The method may also include, in104, forming a cavity on the second surface of the semiconductor substrate using a deep reactive ion etch. The method may further include, in106, enlarging said cavity by carrying out one or more wet etches so that the enlarged cavity is at least partially defined by a vertical arrangement comprising a first lateral cavity surface of the semiconductor substrate extending substantially along a first direction, and a second lateral cavity surface of the semiconductor substrate adjoining the first lateral cavity surface. The second lateral cavity may extend substantially along a second direction different from the first direction. The method may additionally include, in108, forming a first electrode on a first surface of the electrolyte layer. The method may also include, in110, forming a second electrode on a second surface of the electrolyte layer.

In other words, the method may include using forming an electrolyte layer on the front of a semiconductor substrate and using deep reactive ion etching to etch the substrate from the back. The etched cavity may then be enlarged by using wet etching. Consequently, the enlarged cavity may be bound by two lateral surfaces which extend in different directions. Electrodes are then formed on both sides of the electrolyte layers.

Various embodiments may help to address or mitigate the problems as described herein. By using a combination of deep reactive ion etching and wet etching, a tapered structure is formed at the corners of the etched cavity, thus reducing the sharpness of the corners that induce stress concentration. Various embodiments may provide an energy conversion device with an electrolyte layer that may experience reduced stress during operation, leading to reduced failures during fuel cell.

In various embodiments, the energy conversion device may be a solid oxide fuel cell (SOFC) or a micro solid oxide fuel cell (μSOFC) or a solid oxide fuel cell (SOFC) array. In various embodiments, the electrolyte layer may also be referred to as a membrane or a membrane layer or a solid electrolyte layer or film.

In various embodiments, the semiconductor substrate may be a silicon substrate. In various other embodiments, the semiconductor substrate may be a germanium substrate or a gallium arsenide substrate. If a germanium substrate or a gallium arsenide substrate is used, etching parameters may need to be adjusted.

Deep reactive ion etching is a highly anisotropic etch process used to create deep penetration, steep-sided cavities and trenches in substrates, typically with high aspect ratios. The cavities and trenches formed may have nearly vertical side walls. In various embodiments, the angle between a side wall and the front surface of the substrate may be about 88° to about 92°.

Deep reactive ion etching may include a plasma etching and depositing a passivation layer. Deep reactive ion etching alternating between plasma etching and depositing a passivation layer. In other words, plasma etching may be carried out first to form an initial hole, followed by forming of a passivation layer on the base and side walls of the hole; followed by plasma etching which removes the passivation layer at the base and further increasing the depth of the hole, followed by alternate phases of passivation and plasma etching until a deep cavity is formed. The plasma used during plasma etching contains some ions, which attack the wafer from a nearly vertical direction. Sulfur hexafluoride (SF6) may be used for silicon. The passivation layer may be chemically inert. The passivation layer may be formed by a gas such as octafluorocyclobutane (C4F8).

In plasma etching, etch species are generated in a glow discharge. The etch species may be charged (ions) or neutral (atoms and radicals). Etching of the substrate may be done by physical means (e.g. ions under influence of an electric field may accelerate and impinge onto the substrate to cause physical removal of material) and chemical means (chemical reactions between the elements of the material etched and the reactive species generated by the plasma form volatile etch products which may then be removed).

Wet etching is a material removal process that may use liquid chemicals or etchants to remove materials from a substrate. The specific patterns may be defined by masks on the wafer. Materials that are not protected by the masks may be etched away by liquid chemicals. Wet etching may be carried out using aqueous alkaline solutions such as potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol water (EDP) or ammonium hydroxide (NH4OH).

In various embodiments, the second lateral cavity surface may extend at an angle selected from a range of about 3° to about 30°, e.g. about 3° to about 4° from the first surface and/or the second surface of the semiconductor substrate. In various embodiments, the second lateral cavity surface may extend at an angle that is less than about 30°. A smaller angle may lead to greater stability.

In various embodiments, the second lateral cavity surface may be a shoulder region extending substantially parallel to the first surface of the semiconductor substrate. The enlarged cavity may be further defined by a third lateral cavity surface adjoining the second lateral cavity surface so that the second lateral cavity surface is between the first lateral cavity surface and the third lateral cavity surface.

In various embodiments, the method may include forming a plurality of trenches on the first surface of the semiconductor substrate before forming the electrolyte layer.

In various embodiments, the method may further include forming a first dielectric layer on the first surface of the semiconductor substrate and a second dielectric layer on the second surface of the semiconductor substrate before forming the electrolyte layer. The method may also include removing a portion of the second dielectric layer so that a portion of the second surface of the semiconductor substrate is exposed for forming the cavity. The portion of the second dielectric layer may be removed using reactive ion etching. The first and second dielectric layers may be protective layers for protecting the substrate during deep reactive ion etching and/or wet etching. By removing a portion of the second dielectric layer to form an opening, the underlying portion of the semiconductor substrate may be subsequently etching while the first dielectric layer and the remaining portion of the second dielectric layers act as protective layers for the underlying portions of the semiconductor substrate.

In various embodiments, the one or more wet etches may include a first wet etch carried out at a first temperature and a second wet etch carried out at a second temperature lower than the first temperature.

In various embodiments, the one or more wet etches may be carried out until the electrolyte layer is exposed.

In various embodiments, the first lateral cavity surface may be substantially along the (111) plane of the semiconductor substrate.

In various embodiments, the first lateral cavity surface may form a rounded junction with the second lateral cavity surface.

In various embodiments, the enlarged cavity may be at least partially defined by the electrolyte layer and forms a circular interface with the electrolyte layer.

In various embodiments, an energy conversion device formed by a method as described herein may be provided.

Various embodiments may provide a new fabrication method for a solid oxide fuel cell (SOFC), or a fuel cell array or a large scale, silicon-based micro solid oxide fuel cell (μ-SOFC).

In various embodiments, an energy conversion device may be provided.FIG. 2is a schematic showing an energy conversion device200according to various embodiments. The energy conversion device200may include a semiconductor substrate202having a first surface202aand a second surface202bopposite the first surface202a. The semiconductor substrate may include an enlarged cavity204on the second surface202b. The enlarged cavity204may be at least partially defined by a vertical arrangement comprising a first lateral cavity surface204aextending substantially along a first direction, and a second lateral cavity surface204badjoining the first lateral cavity surface204a. The second lateral cavity surface204bmay extend substantially along a second direction different from the first direction. The energy conversion device200may also include an electrolyte layer206on the first surface202aof the semiconductor substrate202. The energy conversion device200may additionally include a first electrode208on a first surface206aof the electrolyte layer206. The energy conversion device may also include a second electrode210on a second surface206bof the electrolyte layer206.

In other words, the energy conversion device200may include an electrolyte layer206over a cavity204on a substrate202. The cavity204may be defined by a first lateral surface204aand a second lateral surface204b. Electrodes208,210are formed on both sides of the electrolyte layer206. The first lateral surface204aand a second lateral surface204bare adjacent to each other and form the side wall of the cavity204.

In various embodiments, the electrolyte layer206may be suspended over the enlarged cavity204. In various embodiments, the electrolyte layer206may be corrugated.

In various embodiments, a portion of the electrolyte layer206may be suspended over the enlarged cavity. In other words, the electrolyte layer206is on or over the substrate202but a portion of the electrolyte layer206may be adjacent or adjoining the enlarged cavity. The portion of the electrolyte layer206may be held over the enlarged cavity204only by the remaining portion(s) of electrolyte layer206.

In various embodiments, the enlarged cavity204may have a diameter nearly equal to the diameter of the substrate, which may be a wafer. In various embodiments, the portion of the electrolyte layer206suspended over the enlarged cavity204may have a diameter nearly equal to the diameter of the substrate. The substrate202may have a diameter of 2 inches (″), 3″, 4″, 6″, 8″, 12″, or 18″. For instance, the enlarged cavity204or the portion of the electrolyte layer206may be below about 2 μm to about 3 μm shorter than the diameter of the substrate202.

In various embodiments, the second electrode210may extend from on the second surface206bof the electrolyte layer206over the first lateral cavity surface204aand the second lateral cavity surface204bto on the second surface202bof the semiconductor substrate202.

In various embodiments, the electrolyte layer206may be solid state oxygen ion-conductors, such as yttria-stabilized zirconia (YSZ), or a proton conductor, such as yttrium-doped BaZrO3(BYZ).

In various embodiments, the enlarged cavity204may extend from the first surface202aof the substrate202to the second surface202bof the substrate202. In various other embodiments, the enlarged cavity204may not fully extend from the second surface202bto the first surface202a. In various embodiments, the device200may include a layer of semiconductor material under the electrolyte layer206.

In various embodiments, the enlarged cavity204may be defined by the first lateral cavity surface204a, the second lateral cavity surface204band a base surface. The base surface may be or may include the electrode210or a portion of the electrode210or/and may be or may include a portion of the electrolyte layer206(e.g. surface206bof the electrolyte layer206). The base surface may be substantially parallel to the surface202aand/or surface202bof the substrate202. The first lateral cavity surface204aand the second lateral cavity surface204bmay be at different angles to the base surface. The first lateral cavity surface204aand the second lateral cavity surface204bmay be lateral to the cavity204and/or the base surface. The first lateral cavity surface204aand the second lateral cavity surface204bmay lie along different crystal planes of the semiconductor substrate204.

In various embodiments, the second lateral cavity surface204bmay define a flat-top conical portion of the enlarged cavity204. The first lateral cavity surface204amay define a flat-top pyramidal portion of the enlarged cavity. The first lateral cavity surface204amay form a circular interface with the electrolyte layer206.

In various embodiments, the second lateral cavity surface204bmay be a shoulder region extending substantially parallel to the first surface202aof the semiconductor substrate202and/or the second surface202bof the semiconductor substrate202. The enlarged cavity204may be further defined by a third lateral cavity surface (not shown inFIG. 2) adjoining the second lateral cavity surface204bso that the second lateral cavity surface204bis between the first lateral cavity surface204aand the third lateral cavity surface. The vertical arrangement may include the first lateral cavity surface204a, the third lateral cavity surface, and the second lateral cavity surface204bbetween the first lateral cavity surface204aand the third lateral cavity surface. The third lateral cavity surface may be between the electrolyte layer206and the second lateral cavity surface204b. The third lateral cavity surface may define a flat-top conical portion of the enlarged cavity. The third lateral cavity surface may form a circular interface with the electrolyte layer206. The first lateral cavity surface204aand the second lateral cavity surface204b, and the third lateral surface may be lateral to the cavity204and/or the base surface. The first lateral cavity surface204a, the second lateral cavity surface204b, and the third lateral surface may lie along different crystal planes of the semiconductor substrate204. The first lateral cavity surface204aand the second lateral cavity surface204b(or the third lateral cavity surface) may form a vertical arrangement. One end of the first lateral surface204amay adjoin one end of the second lateral surface204b.

In various embodiments, the third lateral cavity surface may extend at an angle selected from a range of about 3° to about 30°, e.g. about 3° to about 4° from the first surface202aand/or the second surface202bof the semiconductor substrate202.

In various embodiments, the first electrode208and/or the second electrode may include a suitable electrically conductive and catalytically active material such as gold, silver, nickel, copper, platinum, palladium, ruthenium or the like.

Various embodiments may provide a fuel cell structure such as a SOFC or a fuel cell array, or a large scale, silicon-based micro solid oxide fuel cell (μ-SOFC).

The micro solid oxide fuel cell may include a large-scale array of circular YSZ electrolyte membrane with thickness of about 80 nm and diameter of about 50 μm. Array size may be scaled up to 4 mm and each electrolyte membrane may be supported by surrounding single crystalline silicon with the thickness of about 3 to about 5 μm. The corners may be reinforced with a tapered silicon support creating by combination of plasma and wet silicon etching to effectively avoid sharp corners inducing stress concentrations.

The different effects of using potassium hydroxide (KOH) etching with or without (deep reactive ion etch) DRIE trench (formed before using KOH etching) are shown inFIGS. 3A-3DandFIGS. 4A-4D.FIGS. 3A-3Dshow the effect of KOH etching on a structure without using DRIE whileFIGS. 4A-4Dshow the effect of KOH etching on a structure in which DRIE is carried out before KOH etching.

Experimental Data

FIG. 3Ais a schematic showing the planar bottom view of structure300with a substrate302covered by a dielectric layer312such as silicon nitride (Si3N4) before etching using potassium hydroxide (KOH) etching.FIG. 3Bis a schematic showing the side view of the structure300shown inFIG. 3A. The substrate302may have a plurality of trenches and may have an electrolyte layer306on the top surface.FIG. 3Cis a schematic showing the side view of the structure300after etching using potassium hydroxide (KOH) etching. The structure300has a cavity304.FIG. 3Dis an optical image300′ of the structure300.318corresponds to the boxed region shown inFIG. 3C.

FIG. 4Ais a schematic showing the planar bottom view of structure400with a substrate402covered by a dielectric layer412such as silicon nitride (Si3N4) before etching using potassium hydroxide (KOH) etching according to various embodiments. As shown inFIG. 4A, the substrate has a deep reactive ion etch (DRIE) cavity404not covered by the dielectric layer412.FIG. 4Bis a schematic showing the side view of the structure400shown inFIG. 4Aaccording to various embodiments. The substrate402may have a plurality of trenches and may have an electrolyte layer406the top surface.FIG. 4Cis a schematic showing the side view of the structure400after etching using potassium hydroxide (KOH) etching according to various embodiments. The cavity404has increased in size to form enlarged cavity404′.FIGS. 4A-Cshow a method of forming an energy conversion device according to various embodiments.FIG. 4Dis an optical image400′ of the structure400according to various embodiments.418corresponds to the boxed region shown inFIG. 4C.

As shown inFIG. 3C, anisotropic KOH etching without DRIE trench may induce over-etched corners due to the uneven etching rate according to silicon crystallinity. The over-etching may introduce a feeble anchor318at each corner which is highly vulnerable to mechanical and thermal impact. Furthermore, the center part of array306may still blocked by silicon residues and further etching to fully release the electrolyte membrane306from the substrate302may make the edge of silicon membrane306more unstable and subsequently induces membrane failure from the corners. On the other hand, introducing DRIE circular trench404inside the KOH etching window may generate a new plane after KOH etching process and may form a tapered edge reinforcement416. The surface created by DRIE trench may be orthogonal to silicon <100> orientation, and the etching rate at this surface may be faster than of <100> plane. The newly created structure on the corners of array may be a tapered and rounded silicon support416, which may reinforce the silicon supporting membrane406and with silicon residues underneath the array406was fully removed.

FIGS. 5A-Hillustrate a method of forming a micro solid oxide fuel cell (μSOFC)500according to various embodiments.FIG. 5Ais a schematic illustrating side view of a silicon wafer502being etched according to various embodiments.FIG. 5Bis an image showing the top view of a surface502aof wafer502according to various embodiments. A four-inch <100> double-side polished silicon wafer502with thickness of about 400 μm is utilized as a supporting substrate of the μ-SOFCs array500. Circular trenches520are generated on a top surface502aof the water502using photolithography and deep-reactive ion etching (DRIE). The diameter of the circular trenches520may be about 50 μm as shown inFIG. 5B, and the depth may be about 30 μm.

FIG. 5Cis a schematic illustrating side view of the wafer502with dielectric layers512,514being formed on the wafer502according to various embodiments. Low stress silicon nitride512,514, which are 200 nm in thickness, may be deposited by low pressure chemical vapor deposition (LPCVD) to form dielectric layer512on the bottom surface502band dielectric layer514on the top surface502a. The backside nitride layer512may be then patterned with square open windows and etched by reactive ion etching. Afterward, to generate a reinforced edge support, a DRIE trench504with a depth of 30 μm may be patterned inside the open window.

FIG. 5Dis a schematic illustrating side view of the wafer502with an electrolyte layer506being formed over the top surface502aof the silicon wafer502according to various embodiments. Thin film YSZ electrolyte with thickness of 80 nm may be deposited onto dielectric layer514by atomic layer deposition (ALD) with the condition similar to previously reported works (P. C. Su, C. C. Chao, J. H. Shim, R. Fasching and F. B. Prinz,Nano Lett,2008, 8, 2289-2292; P. C. Su and F. B. Prinz,Electrochemistry Communications,2012, 16, 77-79; P. C. Su and F. B. Prinz,Microelectronic Engineering,2011, 88, 2405-2407) to form electrolyte layer506on nitride layer512. The deposited YSZ thin film506may replicate or follow the surface contour of pre-patterned circular trenches520on the top side and may form a three-dimensional thin film.

FIG. 5Eis a schematic illustrating side view of the wafer502in which the cavity504is enlarged according to various embodiments. The silicon substrate502may be then etched by through-wafer etching in 30 weight percent (wt %) KOH solution at 85° C. (i.e. wet etching) to remove silicon until 20 μm of silicon remained, and an edge-reinforced silicon membrane516for supporting μ-SOFC array may be fabricated. An enlarged cavity504′ may be formed from the cavity504.FIG. 5Fis an image500bshowing circular arrayed cells520′ viewed from bottom after wet etching according to various embodiments.

FIG. 5Gis a schematic illustrating side view of the wafer502in which the dielectric layer514exposed by the enlarged cavity504′ is also etched according to various embodiments. The process as illustrated inFIGS. 5A, C, D, E and G may result in the electrolyte layer506being corrugated. The layer506may have an array506′ of cup-shaped folds520′.FIG. 5His an image500cshowing circular arrays506′ on 15 mm×15 mm silicon chips520according to various embodiments. The dielectric layer512may also be completely removed.

FIG. 5Iis a schematic illustrating side view of the wafer502with electrodes508,510formed according to various embodiments. Both cathode508and anode510of the μ-SOFCs array may be deposited by radio-frequency (RF) sputtering or direct current (DC) sputtering with a nanoporous platinum. It may also be envisioned that the top electrode508is the anode and the bottom electrode510is the cathode. The deposition may be done at a suitable pressure and power, e.g. 30 mTorr Ar pressure and 100 W RF power without a substrate heating. The thickness of platinum electrodes508,510in one embodiment may be about 100 nm, and after deposition of platinum electrodes508,510, each YSZ cell520′ may become an individual fuel cell, and all individual fuel cells520′ in the array506′ may be connected in parallel. The electrolyte layer506/array506′ may be supported by a silicon membrane502′, which is formed from the substrate502by the KOH etch. InFIGS. 5A-H, only three cells520′ have been drawn to illustrate the fabrication process. In the actual arrays fabricated, a total number of approximately 2,600 individual cells have been embedded in a single circular window506′ with a diameter of 4 mm. Circular arrays506′ formed on circular templates with various diameters are shown inFIG. 5G.

FIG. 5Ishows that the enlarged cavity504′ may be defined by a first lateral cavity surface504a, a second lateral cavity surface504b, a third lateral cavity surface504c, as well as a base surface including electrode layer510on electrolyte layer506as well as the silicon membrane502′. The first lateral cavity surface504amay adjoin surface502bof the substrate502, the second lateral cavity surface504bmay adjoin first lateral cavity surface504a, the third lateral cavity surface504cmay adjoin the second lateral cavity surface504b, and the base surface may adjoin the third lateral cavity surface504c. The first lateral cavity surface504a, the second lateral cavity surface504band the third lateral cavity surface504c, and the base surface may lie along different planes of the semiconductor substrate502. The first lateral cavity surface504a, the second lateral cavity surface504band the third lateral cavity surface504cmay be lateral to the cavity504and the base surface. The second lateral cavity surface504bmay be substantially parallel to surface502aand/or surface502bof substrate502. The second lateral cavity surface504bmay lie along the (100) plane of the semiconductor substrate502. The first lateral cavity surface504amay be substantially along the (111) plane of the semiconductor substrate502.

For fuel cell measurement, an μ-SOFCs array on circular template with a diameter of 3.6 mm has been prepared with a total of 2100 individual thin film μ-SOFCs connected in parallel. The array is characterized by potentiostat (Solartron 1470E, Solartron Analytical) at 350 and 400° C. to obtain current-voltage (I-V) behavior. Dry H2is been supplied at the flow rate of 5 sccm on anode side, and cathode side is opened to ambient air as the oxidant. To investigate thermal stability of a circular array structure, thermal cycling test is performed between 150° C. and 400° C. inside a custom-made furnace. Cooling and heating rates were set up as 10° C./min. To apply a harsher thermal condition on the membrane, heating and cooling rates were increased to both 25° C./min. The furnace is surrounded by a ceramic wall to maintain a stable convection from the outside. Field emission secondary electron microscope (FESEM, JEOL JSM-7600F) and an optical microscope are used for morphological and dimensional characterization of the cells.

The addition of DRIE circular trench generated a new etched profile around the membrane. Cross-section of silicon supporting structure with a FESEM image is illustrated inFIGS. 6A-C.

FIG. 6Ashows the schematic600aand image600bof a micro solid oxide fuel cell (μSOFC)600according to various embodiments.FIG. 6Amay result from the process illustrated inFIGS. 5A-I. The fuel cell600may correspond to fuel cell500shown in FIG. SI. The fuel cell600may include a silicon substrate602with lateral cavity side surfaces604a,604b,604cdefining enlarged cavity604. The fuel cell600may include a dielectric layer614on the silicon substrate602, and a corrugated electrolyte layer606with one portion suspended over enlarged cavity604aand another portion over the substrate602.

The silicon support for the array may consist of three different portions: A—(100) plane604bby anisotropic etching; B—tapered plane604cbetween (100) and (111) planes; and C—silicon membrane602′ for supporting 80 nm thick YSZ membrane array606′ to form array606′ of cells620′. In addition, the enlarged cavity604′ may be bound by (111) plane604a. The tapered plane604cmay have an angle of 4° to silicon (100) plane, and may be evolved from the boundary of DRIE trench formed. The tapered edges622may play a role in fortifying the silicon supporting membrane structure602′ as an anchor, which may reduce the chances of failure. The tapered edges622may be bound by surface604c. The process may result in an enlarged cavity604′ having a circular cross sectional plane parallel to surface of the substrate602. The process may also result in the portion of the membrane606being suspended over the enlarged cavity604′ be of circular shape. In other words, the enlarged cavity604′ may be at least partially defined by the electrolyte layer606and may form a circular interface with the electrolyte layer606. Compared to square μ-SOFC membranes (in which membranes are suspended over cavities with square cross-sectional areas along a plane parallel to the plane of the substrate), membranes suspended over circular shaped cavities may evenly distribute the stress on the membrane and may have significantly reduced chances of breaking.

FIG. 6Bshows an image600ctaken from the bottom showing planes604b,604cand array606′ of cells620′ according to various embodiments.FIG. 6Cis an image600dshowing the transition between (100) plane604cand the array606′ of cells620′ according to various embodiments.

The dimension of supporting structures622may be controlled by various parameters of KOH etching window and DRIE. The depth of DRIE trench is 30 μm in one experiment. From the images600b,600c, three-stage supports may clearly be observed and image600dshows the transition region between tapered plane604band array support plane606′. The entire array606′ may be sustained by stress-free single crystal silicon. The distance between centres of neighbouring individual cells in array606′ may be about 1 μm and above. Complex stress conditions observed in freestanding square thin films may be reduced. Various embodiments may provide better mechanical stability.

FIG. 7Ais a plot700aof voltage (V)/power density (mW/cm2) against current density (mA/cm2) of a circular micro solid oxide fuel cell (μSOFC) according to various embodiments. To verify the functional stability of array μ-SOFCs, long-term open circuit voltage (OCV) tests were carried out. Line702show the voltage measured as a function of current density at 350° C.; line704show the voltage measured as a function of current density at 400° C.; line706show the power density as a function of current density at 350° C.; and line708show the power density as a function of current density at 400° C.FIG. 7Bis a plot700bof open circuit voltage (V) against duration (hours or h) showing the open circuit voltage stability of the micro solid oxide fuel cell (μSOFC) according to various embodiments.

FIG. 7Bis a plot700bshowing the long-term OCV result measured over 30 h at 350° C. It is noteworthy fact that OCV has slightly increased to 1.1 V during initial 5 h and stabilized at 1.03 V without OCV degradation and failure. This result may indicate that the membrane array is a defect-free and gas-impermeable structure.

FIG. 7Cis an image700cshowing the cathode side of cell according to various embodiments after the open circuit voltage (OCV) test.FIG. 7Dis an image700dshowing the anode side of the cell according to various embodiments after the open circuit voltage (OCV) test. No visible failures and degradations of the membranes have been observed.

The polarization curves from the 3.6 mm μ-SOFC array measured at 350 and 400° C. are shown inFIG. 7A. High open circuit voltage (OCVs) of 1.1 V has been obtained and the peak power density is 36.2 mW/cm2at 400° C., which is lower than those previously reported. This may be due to the contamination issues during fabrication processes. However, the total power output from the 3.6 mm array was approximately 1.48 mW which is significantly greater than that delivered by the highest performance μ-SOFC reported to date (3.7 μW from a 43 μm×43 μm membrane with 1.3 W/cm2at 450° C., J. An, Y-B. Kim, J. Park, T. M. Gur and F. B. Prinz,Nano Letters,2013, 13, 4551-4555.).

The thermal stability of μ-SOFCs array may be verified by repeated thermal cycles. Total 7 thermal cycling tests were performed and the μ-SOFCs array is cooled down to 150° C. to avoid vapor condensation and heated up to 400° C. repetitively. From simple calculation with mechanical properties of YSZ electrolyte, a high thermal stress of 700 MPa is applied in the membrane during thermal cycling tests.

FIG. 8Ais a plot800aof open circuit voltage (volts or V)/temperature (° C.) against number of thermal cycles showing open circuit voltage changes of the device according to various embodiments with moderate thermal cycles (10° C./min) during thermal cycling tests. Line802indicates the thermal temperatures in which the membrane is subjected to, while line804indicates the open circuit voltage (OCV) measured.

FIG. 8Bis a plot800bof open circuit voltage (volts or V)/temperature (° C.) against number of thermal cycles showing open circuit voltage changes of the device according to various embodiments with steep thermal cycles (25° C./min) during thermal cycling tests. Line806indicates the thermal temperatures in which the membrane is subjected to, while line808indicates the open circuit voltage (OCV) measured.

However, reproducible OCV values have been obtained without any short circuit caused by damage of membranes as shown inFIG. 8A. Heating rate and cooling rate are both 10° C./min and isothermal periods of 5 min are imposed after heating or cooling to stabilize OCV. The OCV is found to oscillate between 0.95 V and 1.08 V, exactly following the thermal cycles, which indicates good OCV response according to temperature changes. To introduce harsher thermal conditions on the cell, heating and cooling rate are increased to 25° C./min and thermal cycles without an isothermal period are carried out consecutively. InFIG. 8B, OCV is found to follow the thermal cycles, with the OCV locally fluctuating during cooling. However, no visible membrane deformation and cell degradation have been observed in the μ-SOFCs array during the harsh thermal cycling, which indicate excellent thermo-mechanical integrity of the array architecture.

A scalable, thin-film, μ-SOFC array with the edge-reinforced structure is demonstrated by utilizing silicon-based micromachining techniques according to various embodiments. Circular array μ-SOFCs with edge-reinforced platforms are generated by combining a dry anisotropic etching with a wet anisotropic etching of (100) silicon and successfully fabricated and tested with various diameters (1 mm˜6 mm) to study functional and thermal stability With the presented design and fabrication method attaining good mechanical stability of nanothin film SOFCs, the μ-SOFC array is able to achieve high OCV of 1.1 V and to provide 1.38 mW of total power output at 400° C. with the array of 3.6 mm in lateral dimension.

Functional stability is verified with long-term OCV test and thermal cycling test with fast heating and cooling rates (25° C./min) are conducted to confirm the thermal stability. OCV at 350° C. is stably maintained with 1.04 V above 30 h without any membrane failures and no membrane failures from thermal impact due to severe temperature changes are observed. The reinforced silicon edge supports may be provide a better strength by a thicker supporting layer at the edge of the μ-SOFCs array and allow good scalability for higher power output. With the reinforced silicon support, a larger array size of beyond 6 mm may be expected. A higher total power output may be achieved at low temperature through further design and process optimization.

Micro solid oxide fuel cells (μ-SOFCs) using nanoscale thin-film electrolytes is an emerging area for low-temperature SOFCs operating at 300-500° C. A dense and gas-impermeable electrolyte with sub-micrometer-scale thickness has been demonstrated using thin-film deposition techniques, including atomic layer deposition (ALD), pulsed laser deposition (PLD), and sputtering. Such thin-film electrolytes are typically grown on silicon wafers or porous substrates, such as anodic aluminum oxide (AAO) as supporting substrates. However, as obtaining dense and gas-tight electrolytes with minimized nanoscale thickness is technically challenging, micro-machined silicon substrate remains to be more practical architecture for μ-SOFCs.

The fabrication of such free-standing electrolyte membranes has typically been done by through-wafer etching in potassium hydroxide (KOH) solution to release the membrane from the substrate.FIG. 9Ais a schematic showing a perspective view of wet etching on a structure900a.FIG. 9Bis a schematic showing the cross-sectional side view of the structure900ashown inFIG. 9Awith an electrolyte layer906a. A substrate902ais covered by dielectric layers912a,914a. A portion of the dielectric layer912ais then removed, exposing the underlying silicon. A wet etch using potassium hydroxide (KOH) solution is then carried out to etch away the underlying silicon, thereby forming a cavity904awith side walls along the (111) plane. An electrolyte layer906ais then formed on dielectric914a.

The resulting membrane geometry is either square or rectangular due to the crystallinity of the (100) silicon substrate. Such architecture for thin-film SOFCs has been a common platform in literature studying various materials operating at below 500° C. However, as the electrolyte is usually deposited at an elevated temperature (about 250-about 800° C., depending on the deposition method), a compressive residual stress within the membrane is often observed. For example, highly compressive residual stress of 1,100±150 MPa has been reported in a 300 nm-thick yttria-stabilized zirconia (YSZ) thin film deposited by PLD at 700° C., and severe membrane buckling has also been observed. For sputtered YSZ deposited at room temperature, the residual stress has been reported to vary from −1.4 GPa (compressive) to 100 MPa (tensile), depending on deposition parameters. Such high residual stress within the extremely thin electrolyte makes its mechanical stability very poor. Based on a Weibull analysis for brittle materials, the failure probability of a flat film increases exponentially with the geometric factor, L2h for a square membrane, where L and h represent the lateral length and thickness of the membrane, respectively. In this sense, it is virtually impossible to further expand the lateral dimensions of the membrane for higher total power output without causing membrane fracture. A typical lateral dimension for a 100 nm-thick, free-standing square membrane to be mechanically stable is limited to 100 μm or less.

Fracturing of a membrane occurs when the maximum principal stress at any point within the membrane exceeds the tensile strength of the material (the Rankine criterion). For a membrane with higher compressive stress than the critical buckling stress, buckling may occur to relieve the compressive stress, and as a result, the fracture of a membrane may be avoided. Unfortunately, for a square electrolyte membrane, although buckling may reduce the magnitude of the stress, the asymmetric buckling pattern may cause irregular membrane wrinkles, which induces high stress concentration points at the clamped edge. The buckling phenomena of square free-standing YSZ and yttria-doped barium zirconate (BYZ) electrolytes were both observed and reported in the literature. Kerman et al. (K. Kerman, T. Tallinen, S. Ramanathan and L. Mahadevan,Journal of Power Sources,2013, 222, 359-366.) has calculated the stress behavior of a square electrolyte membrane and concluded that the compressive stress within the membrane is indeed relaxed by buckling, but buckling-induced wrinkles, causing high stress concentration points at the clamped edges, also leads to membrane fracture.

A circular membrane may have both a more uniform stress distribution under a static loading, as well as a higher buckling resistance compared with a square membrane. Circular membranes have no geometrical discontinuities, such as sharp corners in square membranes, to introduce high stress points by the buckling and wrinkles. To date, only a few research groups have reported the fabrication of circular membrane electrolyte μ-SOFCs, but either the fabrication process is too complex, or the membrane stability is poor with inferior fuel cell performance, due to electronic or gas leakages.FIG. 9Cis a schematic showing a perspective view of dry reactive ion etching (DRIE) on a structure900b.FIG. 9Dis a schematic showing the cross-sectional side view of the structure900bshown inFIG. 9Cwith an electrolyte layer906bformed. A substrate902bmay be covered by dielectric layers912b,914b. A portion of the dielectric layer912bmay then be removed, exposing the underlying silicon. A wet etch using potassium hydroxide (KOH) solution may then be carried out to etch away the underlying silicon, thereby forming a cavity904bwith substantially vertical side walls. As seen fromFIG. 9C, the membrane over cavity904bmay be circular. An electrolyte layer906bmay then be formed on dielectric layer914b. A significant scaling up of a nano thin-film circular electrolyte membrane with good mechanical stability has not been reported previously.

A free-standing membrane on a silicon substrate may be fabricated by performing through-wafer etching with either wet chemicals to obtain a square membrane (FIGS. 9A, 9B) or dry deep reactive ion etching (DRIE) (FIGS. 9C, 9D) to obtain an arbitrary shape of interest. The latter requires sophisticated DRIE equipment with about 4 to about 5 h of etching time to process each wafer, and therefore is not practical for the batch production of thin-film SOFCs.

Various embodiments may provide a fabrication process of our new architecture for a circular membrane combined both anisotropic wet etching and DRIE.FIG. 9Eis a schematic showing a perspective view of dry reactive ion etching (DRIE), followed by wet etching on a structure900caccording to various embodiments.FIG. 9Fis a schematic showing the cross-sectional side view of the structure900cshown inFIG. 9Ewith a membrane906cformed according to various embodiments.

A substrate902cis covered by dielectric layers912c,914c. A portion of the dielectric layer912cis then removed, exposing the underlying silicon. A first DRIE short etching may be applied to predefine a circular shape, and the etching depth may be a few tens of microns out of the total 400 μm etching depth. A second KOH wet etching may then be applied to continue and complete the through-wafer etching and release the membrane914c. An electrolyte layer906cis then formed on the membrane914c. The shape of the resulting through-hole904ccreated by the combinatorial etching may be circular, with a thin tapered silicon ring at the edge of the membrane914c.

FIGS. 10A-Fillustrate a method of forming an energy conversion device1000according to various embodiments.FIG. 10Ais a schematic illustrating the cross-sectional side view of a semiconductor substrate1004deposited with dielectric layers1012,1014according to various embodiments. For instance, low-stress Si3N4with a thickness of about 200 nm may be deposited on both sides1002a,1002bof the 400 μm-thick <100> silicon wafer1004by low-pressure chemical vapor deposition (LPCVD) to form layer1012on the second surface1002b, and layer1014on the first surface1002a. Next, square windows may be lithographically patterned (on layer1012) to define a portion of the surface1002bfor KOH etching and a portion of the dielectric layer1012over the portion of the surface1002bmay be removed by reactive ion etching (RIE) with CF4and O2.

The window sizes (b) as indicated inFIG. 10Bmay vary from about 1 mm to about 4 mm.FIG. 10Bis a schematic illustrating forming a cavity1004using deep reactive ion etching (DRIE) according to various embodiments. The bottom side of a silicon substrate1004may be lithographically patterned for additional etching by deep reactive ion etching (DRIE) process (ICP-RIE, Surface Technology Systems). DRIE may be performed with coil power of 800 W for 10 s etching cycles by SF6and coil power of 800 W for 6 s passivation cycles by C4F8. The cavity1004formed may extend only partially through the substrate1002. The cavity1004may have an etching depth of 30 μm. The diameters of the etched cavity1004(i.e. (a)) may vary from about 0.5 mm to about 3 mm. The silicon etching using DRIE may effectively remove silicon, and may also predefine circles in advance. The circular shape may still be retained even after KOH etching to release a free-standing membrane due to etching rate differences according to silicon crystallinity.

FIG. 10Cis a schematic illustrating the enlargement of the cavity1004via wet etching to form enlarged cavity1004′ according to various embodiments. The wet etch may be carried outing using a chemical solution such as aqueous potassium hydroxide (KOH). The opened silicon windows may be chemically etched by 30 weight percent (wt %) KOH solution at about 80° C. The dielectric layer1014may act as an etch stop for wet etching. The combination of dry reactive ion etching with wet etching may result in the formation of enlarged cavity1004with tapered edges1022. The enlarged cavity1004′ may have a first face1004aextending in a first direction and a second face1004bextending in a second direction. In other words, the side wall of the enlarged cavity1004′ may not slope in the same angle with increasing depth. The portion of the side wall adjoining the surface1002a(i.e. portion of the side wall which is the exposed surface of the tapered edges1022) may make a smaller angle with a surface1002aof the substrate1002while the portion of the side wall further from the surface1002amay form a bigger angle with the surface1002aof the substrate1002. The dimension of the tapered edge support1022may be controllable according to KOH etching time (450 μm in width and 30 μm in thickness in this study). An angle between the first lateral cavity surface1004aand the second lateral cavity surface may be more than 90 degree but may be less than 180 degree.

FIG. 10Dis a schematic illustrating the forming of an electrolyte layer1006on the dielectric layer1014according to various embodiments. The wafer1002may be diced into 10 mm×10 mm silicon chips before forming of the electrolyte layer1006onto the dielectric layer1014. The electrolyte layer1006may be formed via pulsed laser deposition (PLD) or atomic laser deposition (ALD). The electrolyte layer1006may include YSZ or BYZ. The electrolyte layer maybe about 100 nm.

In this experiment, the electrolyte thin films are prepared by two deposition methods, ALD and PLD, for two different electrolyte materials, YSZ and BYZ, respectively, to obtain different residual stresses for the stability test of our cell structure. 100 nm-thick YSZ have been deposited by ALD at 250° C. of substrate temperatures. 100 nm-thick BYZ have also been deposited by PLD (Coherent 248 nm KrF excimer laser, 2.5 J/cm2, 3 Hz, 1 Pa O2) at a substrate temperature of 700° C.

FIG. 10Eis a schematic illustrating etching of a portion of the dielectric layer1014according to various embodiments. The etching of the dielectric layer1014under the electrolyte layer1006for releasing the electrolyte layer1006may be via reactive ion etching (RIE). The dielectric layer1012may also be etched away to expose surface1002bof the substrate1002. Free-standing circular membranes with tapered edge support1022may thus be formed.

FIG. 10Fis a schematic illustrating the forming of electrodes1008,1010according to various embodiments. The electrodes1008,1010may be formed on opposing surfaces of the electrolyte layer1006. The electrode1010may extend onto surfaces1004aand1004bof the enlarged cavity1004′. The electrode1010may further extend onto surface1002bof the substrate1002.

For instance, 100 nm-thick porous Pt may be deposited on the both sides of the structure by radio-frequency (RF) sputtering under 30 mTorr Ar pressure and 100 W RF power without substrate heating to form electrodes1008,1010.

In various embodiments, an energy conversion device1000may be formed. In various embodiments, free-standing circular thin film μ-SOFCs with diameters between 0.5 mm and 3 mm may be obtained. The enlarged cavity1004′ may be defined by lateral cavity surfaces1004a,1004bas well as base surface of electrode1010on electrolyte layer1006. The first lateral cavity surface1004amay adjoin the second lateral cavity surface1004b. The second lateral cavity surface1004bmay adjoin the base surface.

FIGS. 11A-Care schematics showing the progression of the cavity during wet etching to form the enlarged cavity according to various embodiments. Wet etching may be carried out using KOH.FIG. 11Ais a schematic showing a perspective view of a (100) silicon substrate1102with a cavity1104etched using deep reactive ion etching according to various embodiments. As shown inFIG. 11A, the cavity1104may be cylindrical with a circular cross-section, and may be only partially through the substrate1102. Dielectric layer1114such as Si3N4may be on a surface1102aof the substrate1102, while cavity1104may be formed on opposing surface1102bof the substrate1102.

FIG. 11Bis a schematic showing the perspective view of the silicon substrate1102shown inFIG. 11Aduring wet etching according to various embodiments. The cavity1104inFIG. 11Amay be enlarged to form cavity1104′ shown inFIG. 11B.FIG. 11Cis a schematic showing the perspective view of the silicon substrate1102shown inFIG. 11Bafter wet etching according to various embodiments. The cavity1104′ inFIG. 11Bmay be enlarged further to cavity1104″ shown inFIG. 11C. Tapered edge is labelled as1122. The second lateral cavity surface1104bmay be along the (111) plane, while the first lateral cavity surface1104amay be between the (100) and the (111) plane.

FIG. 11Dshows an image of the top view of cavity1104illustrated inFIG. 11Aaccording to various embodiments.FIG. 11Eis a magnified image of the cavity1104shown inFIG. 11Daccording to various embodiments.

FIG. 11Fis an image of the cavity1104′ illustrated inFIG. 11Baccording to various embodiments.FIG. 11Gis a magnified image of a portion1126shown inFIG. 11Faccording to various embodiments.

FIG. 11His an image of the cavity1104″ illustrated inFIG. 11Caccording to various embodiments.FIG. 11Iis a magnified image ofFIG. 11Haccording to various embodiments.

The additional anisotropic DRIE shown inFIG. 11Abefore the KOH etching predefined the circle on a silicon substrate1102. This circular trench1104with the etching depth of 30 μm may evolve to be the circular opening after KOH etching. As the KOH etching proceeds, the (100) planes exposed to KOH were etched at much higher rate and a tapered structure appears along the circular boundary. As the front (100) plane etched by DRIE reached the bottom of Si3N4etch stop layer1114, an annular-shaped and tapered edge support1122may be formed completely. The support1122may be evolved from the corner of the DRIE trench, and as it has a taper angle of about 3.4 degree to about 3.9 degree from the (100) plane. The support1122may be related to the (110) plane.

The principal stress distributions within the membrane are computed with a finite element method (FEM) simulation to confirm the stress distribution within the square and circular YSZ membranes. A commercial software package (COMSOL Inc.) is used to identify the highly stress-concentrated regions on the membranes under a clamped boundary condition. To simplify the modeling, the YSZ electrolyte may be modeled as a linear elastic and isotropic material. The three different membrane models shown inFIGS. 9A-Fare constructed to investigate the effect of membrane shape and tapered edge support on the mechanical stability, namely: (1) a 2 mm×2 mm square membrane clamped at the edge; (2) a circular membrane with a diameter of 2 mm clamped at the edge; and (3) a circular membrane with a diameter of 2 mm and a tapered edge support of 450 μm in width.

To simulate the fuel cell operating condition, 5 psi of static pressure difference on the bottom side and 400° C. of operating temperature are applied in the calculation. The material properties of YSZ and silicon substrates for the numerical simulation are obtained from the literature (V. T. Srikar, K. T. Turner, T. Y. Andrew Ie and S. M. Spearing,Journal of Power Sources,2004, 125, 62-69), which is incorporated herein for reference. Maximum principal stresses in the films are assessed with non-linear large-deflection theory because the deflections are expected to be non-trivial with respect to the membrane thickness. A compressive in-plane strain is applied to simulate the residual stress in the initial configuration as σ0(1−v)/E, where σ0, V, and E represent residual stress of a thin film, Poisson's ratio, and Young's modulus, respectively, and a compressive stress of 500 MPa was preloaded. In this calculation, the stress distribution without letting buckling occur is examined.

μ-SOFCs with circular electrolytes are prepared by depositing 100 nm-thick nanoporous Pt electrodes on both sides of the circular electrolyte. The μ-SOFC is clamped on a custom-built cell chamber placed inside a tube furnace for measurements. Pure dry hydrogen at a flow rate of 10 sccm is fed at the anode side while the cathode side is opened to ambient air for the oxygen source. A gold-coated titanium probe attached in a micro-manipulator is in contact with the cathode side for current collection, and the anode is electrically connected to the chamber via the Pt electrode. The test chips were heated at 5° C.·min−1to the desired operating temperature. A multichannel potentiostat (Solartron Analytical, 1260/1287) is used to obtain current-voltage (I-V) characteristics. The film thickness, morphologies, and membrane deflections are examined with a field emission secondary electron microscope (FESEM, Jeol JSM-7600F, operating voltage 15 kV) and an optical microscope (OM).

The OM images of the fabricated circular electrolyte membranes architecture are shown inFIGS. 12A-C.FIG. 12Ashow the image of 100 nm-thick free-standing electrolyte membranes with diameters from 500 μm to 3 mm according to various embodiments.1202adenotes a 500 μm diameter membrane;1202bdenotes a 600 μm diameter membrane;1202cdenotes a 2.6 mm diameter membrane;1202ddenotes a 2.8 mm diameter membrane;1202edenotes a 2.9 mm diameter membrane; and1202fdenotes a 3 mm diameter membrane. Circular membranes with diameters up to 6 mm is also fabricated, but the survival rate to date is fairly low, around only 15%, and thus the 3 mm diameter membrane, which had a more than 50% survival rate, is taken as the largest mechanically stable dimension with this architecture.

FIG. 12Bshow the image of membranes fabricated using different methods and of different shapes and materials according to various embodiments.1204ais a square-shaped atomic layer deposited—yttria-stabilized zirconia (ALD-YSZ) membrane,1204bis a circular-shaped pulsed laser deposition—yttrium-doped BaZrO3(PLD-BYZ) membrane, and1204cis a circular-shaped atomic layer deposited—yttria-stabilized zirconia (ALD-YSZ) membrane.

FIG. 12Cshows the cross-sectional schematic as well as optical images of different portions of a circular template with tapered edge support according to various embodiments.1206ais the schematic of the circular membrane;1206bis an image showing a side view of the tapered edge;1206cis a scanning electron microscope image of the membrane edge; and1206dis an image of the circular membrane viewed from the bottom. The locations of images1206band1206care indicated in1206a. Further, labels “A” and “B” denote the two stage supporting structures while “C” denotes the membrane.

As shown inFIG. 12B, buckling deformation, caused by compressive stress, has also been observed in the circular membranes for both ALD-YSZ and PLD-BYZ but is much less severe than with the square ALD-YSZ membrane. In terms of the buckling-induced wrinkles at the clamped edge(s), many wrinkles are present in the square membrane while no apparent wrinkle has been observed in the circular ones. From Kerman's calculation (K. Kerman, T. Tallinen, S. Ramanathan and L. Mahadevan,Journal of Power Sources,2013, 222, 359-366.), such buckling-induced wrinkles at the clamped edges may be stress concentration points where fracture of membranes usually occurs. Here, by changing the membrane from square to circular, the buckling-induced wrinkles may be minimized or reduced and the chances of membrane fracture may be expected to decrease significantly.

FIG. 12Cshows that the membrane-supporting structure has an additional tapered support (portion B) between the major support (portion A) and the free-standing nano-thin electrolyte membrane (portion C). The tapered edge support may be a thin and annular single crystal silicon with approximately 450 μm in width and 30 μm in height, where the exact dimensions may vary depending on process and design parameters.

The addition of this thin taper-shaped support may be the key to the success of scaling up the nano thin-film electrolyte because this thin support may serve as a stress absorber to effectively reduce the high stress at the clamped edge.

FIG. 13Ashows schematic of a cross-sectional side view of a clamped square membrane1300aas well as a planar image1302aof the principal stress distribution of a portion of the membrane. The clamped square membrane is a YSZ membrane with a lateral length of 2 mm.1304aindicates the portion of the membrane which stress distribution image1302apertains to.

Various embodiments provide the fabrication of a circular nano thin-film electrolyte for μ-SOFCs with successful enlargement in the lateral dimension from micrometer- to millimeter-scale. A simple two-step through wafer etching process may be provided, and the resulting cell architecture may feature a tapered edge support, which may act as an effective stress absorber at the clamped edge of the membrane. Principal stress analysis has been carried out using a finite element method (FEM) simulation to compare the mechanical stability of the square and circular membranes. The functionality and mechanical stability of the circular nano thin-film SOFCs have also been verified by OCV measurements and statistical results of membrane survival rates.

FIG. 13Bshows schematic of a cross-sectional side view of a clamped circular membrane1300bas well as a planar image1302bof the principal stress distribution of a portion of the membrane. The clamped circular membrane is a YSZ membrane with a diameter of 2 mm.1304bindicates the portion of the membrane which stress distribution image1302bpertains to.

FIG. 13Cshows schematic of a cross-sectional side view of a clamped circular membrane1300cas well as a planar image1302cof the principal stress distribution of a portion of the membrane according to various embodiments. The clamped circular membrane is a YSZ membrane with a diameter of 2 mm and tapered edge support of 450 μm.1304cindicates the portion of the membrane which stress distribution image1302cpertains to.

The thickness of the membranes as shown inFIGS. 13A-Cis 300 nm. The arrows point to the highest stress distribution of the membranes.

FIG. 13Dshows a planar image1300dof a clamped square membrane with width of 2.9 mm that is broken during fuel cell test.FIG. 13Eshows a planar image1300eof a clamped circular membrane with width of 2.8 mm that is broken during fuel cell test.FIG. 13Fshows a planar image1300fof a clamped circular membrane with tapered edged support and having width of 2.8 mm according to various embodiments. The clamped circular membrane inFIG. 13Fis also broken during fuel cell test. The arrows inFIGS. 13D-Fpoint to the approximate regions of initiating failures.

The stress distributions within the nano thin-film electrolyte have been calculated by finite element modeling (FEM) to evaluate the effectiveness of the tapered edge support in relieving stress in the membranes. The calculation results of principal stress distribution (FIGS. 13A-C) demonstrate a much more uniform stress distribution across the circular membrane with a tapered edge support (FIG. 13Cthan either the square membrane (FIG. 13A) or the circular membrane without a tapered edge support (FIG. 13B). The maximum principal stress is 1.4 GPa in a clamped square membrane, 1.2 GPa in a clamped circular membrane, and 0.8 GPa in a clamped circular membrane with a tapered edge support. Compared with the clamped square and circular membranes, the circular membrane with a support showed about 30 to about 40% reduction in the maximum principal stress. The maximum principal stress of the circular membrane, located at the clamped edge(s), may be reduced significantly by changing the membrane shape from square to circle, and may be reduced further by introducing the tapered edge support.

FIGS. 13D-Fshow the corresponding fractured thin-film μSOFCs with structures in FIGS. A-C respectively after fuel cell tests, which provide a good indication of where the fractures in the membrane initiated. For the square membrane (FIG. 13D) and the circular membrane without tapered support (FIG. 13E), the fracture is initiated at the clamped edge, where the stress is the highest, as confirmed by our simulation results. On the other hand, for the circular membrane with a tapered edge support (FIG. 13F), the fracture is initiated at the membrane center because the fragments of the fractured membrane are still clamped along the circular boundaries. This is also in agreement with the FEM calculation results that the highest stress is at the center of the membrane for the membrane with tapered support. This shows that the tapered edge support may effectively restrain the edge-fractures typically observed in square membranes and accordingly, mechanical stability may be improved during fuel cell operation.

The enhanced mechanical stability of the tapered edge-supported circular membranes may be further quantified with the membrane survival rate (percentage of membranes surviving after the fabrication process), as shown inFIG. 14.FIG. 14is a plot1400of membrane survival rate (percent or %) as a function of diameter or width (millimeter or mm) according to various embodiments.1402pertains to the square membranes while1404pertains to the circular membranes.

The survival rates for different membrane lateral dimensions between square and circular membranes have been compared by counting a total of 144 cells with 12 cells for each size. The survival rate decreases as the membrane size increases for both membranes. More importantly, the circular membranes showed higher survival rates than the square membranes over all membrane sizes. For YSZ membranes with 3 mm of lateral dimension, none of the square membranes survives, while 50% of the circular membranes remain intact. These results provide statistical evidence of the enhanced mechanical stability of the new cell architecture over the widely reported square structure.

The mechanical stability of the new cell architecture may be further explored by open circuit voltage (OCV) measurements.FIG. 15Ais a plot1500aof open circuit voltage (volts or V) as a function of time (hours) showing the variation of the open circuit voltages of atomic layer deposited—yttria-stabilized zirconia (ALD-YSZ) membrane and pulsed laser deposition—yttrium-doped BaZrO3(PLD-BYZ) membrane according to various embodiments over time.1502relates to ALD-YSZ membrane while1504relates to PLD-BYZ membrane. As shown inFIG. 15A, the OCVs for YSZ and BYZ fuel cells are able to achieve high values of 1.07 V and 1.12 V, which are close to the theoretical OCVs of 1.17 V at 400° C. with pure hydrogen (H2) fuel and air as the oxidant, and OCVs are stable for over 8 h, with less than 10 mV decay in both fuel cells. The high and stable OCVs over time provide direct evidence that the circular template developed according to various embodiments has better mechanical stability and functionality of μ-SOFCs using nanoscale thin-film electrolytes.

Fuel cell performance measurements with the 1.4 mm diameter circular μ-SOFC are conducted at 350° C., 400° C. and 450° C.FIG. 15Bis a plot1500bof voltage (volts or V)/power density (milliwatts/square centimetres or mW/cm2) as a function of current density (milliamperes/square centimetres or mA/cm2) showing the polarization curves of a platinum (Pt)/yttria-stabilized zirconia (YSZ)/platinum (Pt) micro-solid oxide fuel cell (μ-SOFC) according to various embodiments at various temperatures. Curve1506arepresents the OCV variation as a function of current density at 350° C.; curve1506brepresents the OCV variation as a function of current density at 400° C.; and curve1506crepresents the OCV variation as a function of current density at 450° C. Curve1508arepresents the power density variation as a function of current density at 350° C.; curve1508brepresents the power density variation as a function of current density at 400° C.; and curve1508crepresents the power density variation as a function of current density at 450° C. As shown inFIG. 15B, high open circuit voltage (OCVs) of 1.09 V and peak power density of 127 mW/cm2at 450° C. have obtained. The total power output from the circular μ-SOFC is about 1.95 mW, which may be the highest total power output at 450° C. for thin film μ-SOFCs featuring a free-standing flat membrane configuration reported to date to the best of our knowledge.

Various embodiments relate to circular nano thin-film μ-SOFCs with a tapered edge support as well as methods of forming the same to effectively enhance the mechanical stability of the fuel cell. The center-symmetric geometry of the circular thin-film may help to distribute the stress of the membrane uniformly in the radial and circumferential directions, and the tapered edge support may serve as a stress absorber and may significantly suppress the high magnitude of stress at the clamped edges. The addition of the tapered edge support created along the circular boundary may reduce by 30-40% of the maximum principal stress at the clamped edge of the membrane, and accordingly may reduce the risk of membrane fracture. The membrane survival rates may provide statistical evidence for enhanced mechanical stability of the membrane using the new fuel cell architecture, and subsequently may enable scale-up of μ-SOFC to millimeter size and significantly improve total power output. The stable OCVs over 8 h at 400° C. may also justify the better mechanical stability and functionality of circular thin film electrolytes to be dense and pinhole-free in this cell-supporting structure. Thus, the new cell architecture according to various embodiments may be a promising template for large-scale nano thin-film SOFCs to achieve higher total power output with mechanical and functional stability.

Various embodiments may provide a structure that defines an opening which is used to support a thin film membrane deposited over the opening.

The structure may include a thin edge support that extrudes from a mother supporting substrate which is a single crystalline silicon wafer.FIG. 16Ais a schematic showing a cross-sectional side view of a device1600according to various embodiments. The device1000may include a semiconductor substrate1602and a cavity1604extending through the substrate1602. The cavity1604may be formed by a combination of deep reactive ion etching and wet etching as described herein. The device1000may further include a membrane1606suspended over the cavity.

FIG. 16Bshows a membrane1606aaccording to various embodiments. The membrane1606amay be the membrane1606shown inFIG. 16A. The membrane1606amay include an electrolyte layer and electrodes on both sides of the electrolyte layer. There may be a dielectric layer1614between the membrane1606aand the substrate1602.FIG. 16Cis an optical image of the membrane1606aaccording to various embodiments.

FIG. 16Dshows a membrane1606baccording to various embodiments. The membrane1606bmay be the membrane1606shown inFIG. 16A. The membrane1606bmay be a membrane array. The membrane1606bmay include a plurality of cells. There may be a dielectric layer1614between the membrane1606band the substrate1602.FIG. 16Eis an optical image of the membrane1606baccording to various embodiments.

In various embodiments, the thin film membrane may include core fuel cell components including electrolyte and electrode layers, or may include a thin silicon layer with embedded array of electrolyte/electrode membranes. Various embodiments may be suitable for as energy conversion devices such as fuel cells utilizing solid state thin film electrolytes.

Various embodiments may provide a stress-free integrated two-stage support. Unlike existing technologies where such support is created by adding heterogeneous materials (such as nickel, poly-crystalline silicon, doped silicon, etc), the thin support according to various embodiments may be formed by directly etching the mother supporting substrate which is a single crystalline silicon wafer. Since single crystalline silicon have virtually no inherent residual stress, this may effectively avoid the additional unwanted stress from the foreign materials introduced to the thin film membrane. In other words, the tapered silicon support may be part of the silicon substrate, thus reducing stress as compared to methods which involves using a different material as a support, which may lead to residual stress. For instance, using a nickel grid anode grown by electroplating as a support may lead to residual stress.

The thin edge support may serve as a shock/stress absorber that may effectively accommodate environmental impacts and inherent residual stress from the thin film membrane. The shape of the support, the methodology to create such a support, and/or the critical dimensions may be important.

The two stage supporting substrate may be formed by a combination of through-wafer etching methods, namely wet KOH etching and deep reactive ionic etching (DRIE), which are both simple and cost effective with minimum requirements of process environment and processing apparatuses.

Various embodiments may be scalable with leeway for increasing lateral dimensions. With the addition of edge support, various embodiments may be applied in different configurations of fuel cells to reinforce the structural integrity as well as to scale up the cell dimension. Various embodiments may increase the lateral dimensions of a free-standing electrolyte membrane from hundreds of micrometer scale to millimetre scale. Various embodiments may successfully stabilize the corners of a silicon membrane that is usually thinner at the (100)/(111) corner and is subjected to fracture.

FIG. 17is a schematic illustrating a cross-sectional side view of a silicon substrate1702to show the etching dimensions for deep reactive ion etching according to various embodiments. The silicon substrate1702may be covered by low stress Si3N4dielectric layers1712,1714. The etched diameter (D) may be about 500 μm to about 3000 μm. An etched window size (W) of D+about 1000 μm may be made on dielectric layer1714. The edge depth may be about 30 μm.

FIG. 18A-Dillustrate forming an enlarged cavity on a substrate1802according to various embodiments.FIG. 18Ais a cross-sectional schematic showing a side view of a silicon substrate1802coated with a dielectric layer1814on a first surface1802aof the substrate1802and a dielectric layer1812on a second surface1802bof the substrate1802opposite the first surface1802aaccording to various embodiments. A portion of the dielectric layer1812may be removed by reactive ion etching (RIE) using CF4of about 30 standard cubic centimetres per minute (sccm), power of about 150 W, and at an etching rate of about 45 to about 50 nm/min to expose the underlying surface1802b.

FIG. 18Bis a cross-sectional schematic showing a side view of the silicon substrate1802subjected to deep reactive ion etching (DRIE) according to various embodiments. The parameters may be about 130 sccm SF6, about 100 sccm C4F8, about 800 W of radio frequency (RF) coil power, and an etching rate of about 3 to about 3.2 μm/min. The etching dimensions may be similar to that illustrated forFIG. 17. A cavity1804may be formed by DRIE.

FIG. 18Cis a cross-sectional schematic showing a side view of the silicon substrate1802subjected to a first wet etch according to various embodiments. The first wet etching may be used to enlarge the cavity1804to form cavity1804′. The first wet etch may be carried out using KOH and may be carried out until a layer of about 10 μm remains from the cavity1804′ to the top surface1802a.30% weight percent (wt %) of KOH may be used. The etching temperature may be about 90° C. and the etching rate may be about 2.0 to about 2.2 μm/min.

FIG. 18Dis a cross-sectional schematic showing a side view of the silicon substrate1802subjected to a second wet etch according to various embodiments. The second wet etching may be used to further enlarge the cavity1804′ to form enlarged cavity1804″. The second wet etch may be carried out using 30 wt % KOH. The etching temperature may be about 70° C. and the etching rate may be about 0.6 to about 0.8 μm/min. Various embodiments may include enlarging a cavity using two wet etches at different temperatures.