MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A method of forming a memory device including providing a base wafer including a semiconductor material layer, and forming first and second spacers in the semiconductor material layer. The first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The second spacers cross the first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. A plurality of semiconductor material strips are formed each between bottoms of the second spacers and the second surface of the semiconductor material layer and sandwiched between two neighboring first spacers. The method further includes performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority of Chinese Patent Application No. 202211557957.7, filed on Dec. 6, 2022, the content of which is incorporated herein by reference in its entirety.

FIELD OF THE TECHNOLOGY

This application relates to the field of memory devices and, more particularly, to a dynamic random-access memory device and manufacturing method thereof.

BACKGROUND OF THE DISCLOSURE

Memory devices, such as dynamic random-access memory (DRAM) devices, are widely used in smartphones, tablets, laptops, desktop computers, data servers, or other computational devices. New memory device structures have been developed to overcome the inherent scaling limitations and to improve the cost effectiveness of mass production. One of these structures is a memory device with a vertical-channel transistor structure. Such a memory device has the advantage of significantly reducing the chip area compared with a conventional memory device.

Wafer bonding is a technology widely used in the process of forming a memory device such as a vertical-channel memory device. In the wafer bonding process of a vertical-channel memory device, sources and drains are led out on a front surface and a bonding back surface of the device, respectively. For example, sources are led out using a metal layer and a single contact. The drains are led out using a backside process, and bit lines are formed at the backside to connect to the drains. Because of the wafer bonding process, photolithography alignment in a backside process is difficult. As the technology continuously develops, the critical size of the devices becomes smaller and smaller, and the size of the alignment window for the photolithography process also becomes smaller, making the alignment during photolithography even more difficult. As a result, the yield of the products is reduced. Further, the wafer bonding process and the strain of previous layers induce local distortion of the device pattern. For example, some drains that are supposed to be on a straight line can deviate from that line, and hence some of the drains become not aligned with the bit lines, causing broken circuit or increasing contact resistance. This could further reduce the yield of the products and induce resistance-capacitor (RC) delay, influencing the uniformity of performance of the device.

SUMMARY

In accordance with the disclosure, there is provided a method of forming a memory device including providing a base wafer that includes a semiconductor material layer, forming a plurality of first spacers in the semiconductor material layer, and forming a plurality of second spacers in the semiconductor material layer. The plurality of first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The plurality of second spacers cross the plurality of first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. A plurality of semiconductor material strips are formed each between bottoms of the second spacers and the second surface of the semiconductor material layer and sandwiched between two neighboring ones of the first spacers. The method further includes performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer.

Also in accordance with the disclosure, there is provided a memory device including a semiconductor material layer, a plurality of first spacers in the semiconductor material layer, a plurality of second spacers in the semiconductor material layer, and a plurality of silicide layers. The plurality of first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The plurality of second spacers cross the plurality of first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. The plurality of silicide layers extend from the second surface of the semiconductor material layer into the semiconductor material layer. Each of the plurality of silicide layers has a strip shape and is sandwiched between two neighboring ones of the plurality of spacers.

Also in accordance with the disclosure, there is provided a memory system including a memory device and a memory controller coupled to the memory device and configured to control operation of the memory device. The memory device includes a semiconductor material layer, a plurality of first spacers in the semiconductor material layer, a plurality of second spacers in the semiconductor material layer, and a plurality of silicide layers. The plurality of first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The plurality of second spacers cross the plurality of first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. The plurality of silicide layers extend from the second surface of the semiconductor material layer into the semiconductor material layer. Each of the plurality of silicide layers has a strip shape and is sandwiched between two neighboring ones of the plurality of spacers.

DESCRIPTION OF EMBODIMENTS

The following describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. The described embodiments are merely some but not all of the embodiments of the present disclosure. Other embodiments obtained by a person skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same or similar meanings as generally understood by one of ordinary skill in the art. As described herein, the terms used in the specification of the present disclosure are intended to describe example embodiments, instead of limiting the present disclosure.

As used herein, when a first component is referred to as “fixed to” a second component, it is intended that the first component can be directly attached to the second component or can be indirectly attached to the second component via another component. When a first component is referred to as “connecting” to a second component, it is intended that the first component can be directly connected to the second component or can be indirectly connected to the second component via a third component between them. The terms “vertical,” “horizontal,” “perpendicular,” “left,” “right,” and similar expressions used herein, are merely intended for purposes of description. The term “and/or” used herein includes any suitable combination of one or more related items listed.

In this disclosure, a value or a range of values can refer to a desired, target, or nominal value or range of values and can include slight variations. The term “about” or “approximately” associated with a value can allow a variation within, for example, 10% of the value, such as +2%, +5%, or +10% of the value, or another proper variation as appreciated by one of ordinary skill in the art. The term “about” or “approximately” associated with a state can allow a slight deviation from the state. For example, a first component being approximately perpendicular to a second component can indicate that the first component is either exactly perpendicular to the second component or slightly deviates from being perpendicular to the second component, and an angle between the first and second components can be within a range from, e.g., 80° to 100°, or another proper range as appreciated by one of ordinary skill in the art.

FIGS.1-10Cschematically show an example process of fabricating a memory device consistent with embodiments of the disclosure, which will be described in more detail below. The steps in the fabrication process are described below in a certain order. This, however, does not necessarily mean the steps must be performed in such an order. The order of certain steps can be different from that in the description below, and some steps can be performed simultaneously. Further, not all steps must be included in the fabrication process, and some steps can be omitted.

FIG.1is a cross-sectional view schematically showing a structure at a certain stage of the process of forming the memory device. As shown inFIG.1, a first substrate110is provided. A sacrificial layer120and a semiconductor material layer130are sequentially formed over the first substrate110. The wafer formed so far including the first substrate110, the sacrificial layer120, and the semiconductor material layer130is also referred to as a “base wafer.”

The first substrate110is also referred to as a “growth substrate” or a “sacrificial substrate,” and can be made of, e.g., an elemental semiconductor material such as silicon or germanium, a semiconductor alloy such as SiGe, a compound semiconductor material such as SiC, InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, or a composite material such as silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or a combination of any of the above materials.

In some embodiments, the sacrificial layer120can be made of an insulation material such as silicon oxide, silicon nitride, or silicon oxynitride. The semiconductor material layer130can be made of e.g., an elemental semiconductor material such as silicon or germanium, a semiconductor alloy such as SiGe, a compound semiconductor material such as SiC, InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, or a combination of any of the above materials.

FIGS.2A-2Cschematically show another stage in the fabrication process of the memory device.FIG.2Ais a top view,FIG.2Bis a cross-sectional view along A-A′ line inFIG.2A, andFIG.2Cis a cross-sectional view along B-B′ line inFIG.2A. As shown inFIGS.2A to2C, a plurality of first grooves210are formed in the semiconductor material layer130.

The plurality of first grooves210can be arranged in a row along a first direction. Each of the plurality of first grooves210can extend along a second direction, and the plurality of first grooves210can be parallel to each other.

An angle between the first direction and the second direction can be non-zero. In some embodiments, the angle between the first direction and the second direction can be approximately 90°, i.e., the first direction can be approximately perpendicular to the second direction. In the embodiments described below in connection withFIGS.2A-10C, the first direction and the second direction are approximately perpendicular to each other, with the first direction being denoted as an x-direction and the second direction being denoted as a y-direction, such as shown inFIG.2A. The first direction can be, e.g., a word line direction in the memory device and the second direction can be, e.g., a bit line direction in the memory device.

The plurality of first grooves210can penetrate through the semiconductor material layer130, and can expose portions of a top surface of the sacrificial layer120. That is, the plurality of first grooves210can extend from a top surface (first surface) of the semiconductor material layer130to a bottom surface (second surface) of the semiconductor material layer130. In some embodiments, the plurality of first grooves210can also extend further into the sacrificial layer120.

The plurality of first grooves210can be formed by photolithography and etching (wet etching or dry etching), and the etching process can include a selective etching process. For example, the etchant used to form the first grooves210can etch the semiconductor material layer130much faster than etching the sacrificial layer120, and hence the etching process can effectively “stop” at the sacrificial layer120.

FIGS.3A-3Cschematically show another stage in the fabrication process of the memory device.FIG.3Ais a top view,FIG.3Bis a cross-sectional view along A-A′ line inFIG.3A, andFIG.3Cis a cross-sectional view along B-B′ line inFIG.3A. As shown inFIGS.3A-3C, first spacers211are formed in the plurality of first grooves210. Thus, the first spacers211extend from the top surface of the semiconductor material layer130to the bottom surface of the semiconductor material layer130.

The first spacers211can be made of an insulation material such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. In some embodiments, the first spacers211can be formed by, e.g., depositing the material for the first spacers211(first spacer material) in the first grooves210to fill the first grooves210. The deposition process can include, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. In some other embodiments, the first spacers211can be formed by oxidizing the material, such as silicon, of the semiconductor material layer130to fill the first grooves210. The oxidization process can include, for example, a thermal oxidization process. In some embodiments, a first spacer material layer is formed to fill the plurality of first grooves210and also on a top surface of the semiconductor material layer130. Excessive first spacer material on the top surface of the semiconductor material layer130can be removed using a planarization process, such as etching and/or chemical-mechanical polishing (CMP), forming the first spacers211in the plurality of first grooves210. In some embodiments, the top surfaces of the first spacers211can be flush with the top surface of the semiconductor material layer130, as shown inFIGS.3B and3C. In some other embodiments, the top surfaces of the first spacers211do not flush with the top surface of the semiconductor material layer130and can be higher or lower than the top surface of semiconductor material layer130.

FIGS.4A-4Cschematically show another stage in the fabrication process of the memory device.FIG.4Ais a top view,FIG.4Bis a cross-sectional view along A-A′ line inFIG.4A, andFIG.4Cis a cross-sectional view along C-C′ line inFIG.4A. As shown inFIGS.4A-4C, a plurality of second grooves310are formed in the semiconductor material layer130and the first spacers211.

The plurality of second grooves310can be arranged in a row along the second direction. Each of the plurality of second grooves310can extend along the first direction, and the plurality of second grooves310can be parallel to each other. That is, as shown inFIG.4A, the plurality of second grooves310can cross the first spacers211(hence cross the first grooves210) and not parallel to the first spacers211(hence not parallel to the first grooves210).

In the embodiments described below in connection withFIGS.4A-10C, the first direction and the second direction are approximately perpendicular to each other, and the plurality of second grooves310are approximately perpendicular to the first spacers211, with the first direction being the x-direction and the second direction being the y-direction, such as shown inFIG.4A.

The plurality of second grooves310can penetrate only a portion of a thickness of the semiconductor material layer130and may not expose the top surface of the sacrificial layer120, as shown inFIG.4C. That is, each of the plurality of second grooves310can extend from the top surface of the semiconductor material layer130to a position inside the semiconductor material layer130and away from the bottom surface of the semiconductor material layer130.

The plurality of second grooves310can be formed by photolithography and etching (wet etching or dry etching). For example, the etchant used for forming the second grooves310can etch both the material for the semiconductor material layer130and the material for the first spacers211. The depth of the second grooves310(and hence the thickness of the remaining semiconductor material layer130and the thickness of the remaining first spacers211at the bottoms of the second grooves310) can be controlled by controlling the etching conditions, such as the duration of the etching process.

As shown inFIGS.4A-4C, at least a portion of the semiconductor material layer130is divided by the first grooves210(and hence the first spacers210) and the second grooves310into a plurality of pillars132, each of which will serve as an active area (AA) for a vertical-channel transistor of the memory device, and is also referred to as an “AA pillar” in this disclosure. In the example shown inFIGS.4A-4C, each of the AA pillars132has a rectangular shape. In some other embodiments, the AA pillars132can have a different shape, such as a square shape. The region of the semiconductor material layer130constituted by the active areas can also be referred to as an “active region,” i.e., the active region of the semiconductor material layer130can include a plurality of active areas (AA pillars132). As shown in, e.g.,FIG.4C, since the second grooves310do not penetrate all the way through the semiconductor material layer130, the remaining portions of the semiconductor material layer130at the bottom of the second grooves310form a plurality strips134parallel to each other in the first direction, and each extending in the second direction and connecting a corresponding column of AA pillars132at the bottoms of the AA pillars132. That is, in the first direction, each strip134is sandwiched between two neighboring first spacers211, while in a direction perpendicular to a surface (first surface or second surface) of the semiconductor material layer130, each strip134is between bottoms of the second grooves310and the bottom surface of the semiconductor material layer130. These strips134are also referred to as “semiconductor material strips” or “semiconductor material strips.”

FIGS.5A-5Cschematically show another stage in the fabrication process of the memory device.FIG.5Ais a top view,FIG.5Bis a cross-sectional view along A-A′ line inFIG.5A, andFIG.5Cis a cross-sectional view along C-C′ line inFIG.5A. As shown inFIG.5C, a gate dielectric layer230is formed at a sidewall of each of the plurality of second grooves310(part of which is also a sidewall of a corresponding AA pillar132). As shown in, e.g.,FIG.4A, the second grooves310not only cut into the semiconductor material layer130to form the AA pillars132, but also cut into the first spacers211, forming a plurality of first spacer pillars. A portion of a sidewall of each of the first spacer pillars is also exposed, and the gate dielectric layer230can also be formed on the exposed portion of the sidewall of a first spacer pillar. In some embodiments, the gate dielectric layers230can include a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. Further, the gate dielectric layers230can be formed by depositing the dielectric material on the sidewalls of the plurality of AA pillars132, or can be formed by, e.g., oxidizing portions of the sidewalls of the AA pillars132, e.g., via thermal oxidization. In some embodiments, the gate dielectric layers230can be a composite layer including two or more dielectric films made of same, similar, or different materials.

As shown inFIG.5C, a gate electrode layer240is formed on the gate dielectric layer230. The gate electrode layer240can be formed by deposited, e.g., by PVD, CVD, or ALD, onto the gate electrode layer240, and can be made of a conductive material, such as polysilicon or metal, where the metal can include, e.g., copper, aluminum, tungsten, or a combination thereof.

Further, a second spacer311is formed in each second groove310. Thus, each second spacer311extends from the top surface of the semiconductor material layer130to a position inside the semiconductor material layer130and away from the bottom surface of the semiconductor material layer130. That is, in the direction perpendicular to a surface (first surface or second surface) of the semiconductor material layer130, each semiconductor material strip134is between bottoms of the second spacers311and the bottom surface of the semiconductor material layer130. The gate dielectric layer230and the gate electrode layer240are embedded in the corresponding second spacer311.

The gate dielectric layers230and the gate electrode layer240are also illustratively shown inFIG.5Ausing dashed lines, while in reality they may not be seeable from the top view inFIG.5Abecause they are covered by the second spacers311.

The second spacers311can be made of an insulation material such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. Top surfaces of the second spacers311can be flush with the top surface of the semiconductor material layer130.

In some embodiments, formation of the second spacers311can include, e.g., depositing the material for the second spacers311(second spacer material) in the second grooves310to fill the second grooves310. The deposition process can include, for example, a PVD process, a CVD process, or an ALD process. In some other embodiments, the formation of the second spacers311can include oxidizing the material, such as silicon, of the semiconductor material layer130to fill the second grooves310. The oxidization process can include, for example, a thermal oxidization process. In some embodiments, a second spacer material layer is formed to fill the plurality of second grooves310and also on a top surface of the semiconductor material layer130. Excessive second spacer material on the top surface of the semiconductor material layer130can be removed using a planarization process, such as etching and/or CMP, forming the second spacers311in the plurality of second grooves310. In some embodiments, the top surfaces of the second spacers311can be flush with the top surface of the semiconductor material layer130, as shown inFIGS.5B and5C. In some other embodiments, the top surfaces of the second spacers311do not flush with the top surface of the semiconductor material layer130and can be higher or lower than the top surface of semiconductor material layer130.

An example process for forming the structure shown inFIGS.5A-5Cis as follows. First, a silicon oxide-silicon nitride-silicon oxide composite layer is deposited in each of the second grooves310. Then the silicon nitride layer is removed by selective etching using an etchant that can etch silicon nitride much faster than etching silicon oxide, forming void in each second groove310and exposing a portion of a sidewall of the corresponding AA pillar132. After that, the gate dielectric layer230and the gate electrode layer240are sequentially formed on the exposed portion of the sidewall of the AA pillar132. Finally, additional dielectric material, such as silicon oxide, is formed in the void to fill the space not occupied by the gate dielectric layer230and the gate electrode layer240. The filled-in additional dielectric material, together with the silicon oxide layers from the composite layer, can form the second spacer311.

The gate dielectric layer230and the gate electrode layer240together form a gate structure of a vertical-channel transistor in the memory device. In the example shown inFIG.5C, the gate structure is formed on one sidewall of the AA pillar132. In some other embodiments, the gate structure can be formed on more sidewalls of the AA pillar132, such as two opposite sidewalls in the second direction.

As described above, the first spacers211can be parallel to each other and arranged in a row along the first direction. The second spacers311can be parallel to each other and arranged in a row along the second direction. The first spacers211can intersect the second spacers311(i.e., not parallel to the second spacers311), and can together define the plurality of active areas (AA pillars132) in the semiconductor material layer130. The plurality of active areas (AA pillars132) can be arranged in an array expanding along the first direction and the second direction. That is, the plurality of active areas (AA pillars132) can be considered as including one or more columns of active areas (AA pillars132) arranged along the first direction and each extending in the second direction; or the plurality of active areas (AA pillars132) can be considered as including one or more rows of active areas arranged along the second direction and each extending in the first direction. One gate dielectric layer230and one corresponding gate electrode layer240can be located on a side wall of one corresponding active area (AA pillar132). The gate electrode layers240of each row of active areas (AA pillars132) can be connected, for example, via portions of the gate electrode layer formed on the sidewalls of the first spacer pillars as described above, to form a word line of the memory device.

FIGS.6A-6Cschematically show another stage in the fabrication process of the memory device.FIG.6Ais a top view,FIG.6Bis a cross-sectional view along A-A′ line inFIG.6A, andFIG.6Cis a cross-sectional view along C-C′ line inFIG.6A. As shown inFIGS.6B and6C, a first conductive structure251(AA pick up for the vertical-channel transistor) is formed on the top surface of each of the plurality of active areas (AA pillars132) of the semiconductor material layer130, and a second conductive structure252is formed on top surfaces of each column of first conductive structures251to electrically couple the first conductive structures251. Each first conductive structure251can have a pillar shape, and each second conductive structure252can have a strip shape.

In addition, as shown inFIG.6C, a plurality of third conductive structures253are also formed on the top surface of a region of the semiconductor material layer130outside the active region. Each of the third conductive structures253can have a pillar shape and be electrically coupled to a column of first conductive structures251via a corresponding second conductive structure252. The second conductive structures252are arranged along the first direction and each second conductive structure252extends along the second direction. The second conductive structures252can be approximately parallel to each other. Each of the plurality of active areas (AA pillars132) can be electrically coupled to a corresponding one of the first conductive structures251. One column of first conductive structures251corresponding to one column of active areas AA can be electrically coupled to a corresponding second conductive structure252. A first insulation layer260is formed on the top surface of the semiconductor material layer130. The first conductive structures251, the second conductive structures252, and the third conductive structures253can be embedded in the first insulation layer260.

The first conductive structures251and the second conductive structures252can be formed by various suitable methods. In some embodiments, the first insulation layer260(or a portion thereof) can be deposited over the semiconductor material layer130. After that, a plurality of holes for the first conductive structures251and the third conductive structures253can be formed in the first insulation layer260by photolithography and etching to expose at least portions of top surfaces of the plurality of active areas (AA pillars132), and then a plurality of trenches for the second conductive structures252can be formed in the first insulation layer260by photolithography and etching, where each trench can be aligned with a column of holes. Alternatively, the plurality of trenches for the second conductive structures252can be formed first and the plurality of holes for the first conductive structures251and the third conductive structures253can then be formed in the trench and into the first insulation layer260to expose portions of top surfaces of the plurality of active areas (AA pillars132). Once the holes and trenches are formed, a conductive material can be filled therein to form the first conductive structures251, the second conductive structures252together. In some other embodiments, the first conductive structures251and the third conductive structures253can be formed first by lithography/etching and filling corresponding conductive material and the second conductive structures252can be then formed by lithography/etching and filling corresponding conductive material; or the second conductive structures252can be formed first by lithography/etching and filling corresponding conductive material and the first conductive structures251and the third conductive structures253can then be formed by lithography/etching and filling corresponding conductive material.

In some embodiments, after the first conductive structures251, the second conductive structures252, and the third conductive structures253are formed, additional insulation material for the first insulation layer260can be deposited to bury the first conductive structures251, the second conductive structures252, and the third conductive structures253, such that the first conductive structures251, the second conductive structures252, and the third conductive structures253are embedded in the final first insulation layer260.

Each of the first conductive structures251, the second conductive structures252, and the third conductive structures253can be made of a conductive material, such as polysilicon or metal, and the metal can include copper, aluminum, tungsten, or a combination thereof. The conductive materials for the first conductive structures251, the second conductive structures252, and the third conductive structures253can be the same as or different from each other. For example, the first conductive structures251, the second conductive structures252, and the third conductive structures253can be made of tungsten.

The first insulation layer260can be made of a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials.

InFIG.6A, the first spacers211, the second spacers311, the AA pillars132, the first conductive structures251, the second conductive structures252, and the third conductive structures253are indicated using dashed lines for illustrative purposes, while in reality they may not be seeable from the top view inFIG.6A.

FIGS.7A-7Cschematically show another stage in the fabrication process of the memory device.FIG.7Ais a top view (note the viewing direction inFIG.7A, as well as that in subsequentFIGS.8A,9A, and10A) is opposite to that inFIGS.2A,3A,4A,5A, and6A),FIG.7Bis a cross-sectional view along A-A′ line inFIG.7A, andFIG.7Cis a cross-sectional view along C-C′ line inFIG.7A. InFIG.7A, the second spacers311are indicated using dashed lines for illustrative purposes, while in reality they may not be seeable from the top view inFIG.7A.

Consistent with the disclosure, after the first conductive structures251, the second conductive structures252, and the third conductive structures253are formed, the entire wafer (the wafer formed so far is also referred to as an “intermediate wafer”) is flipped and bonded to a second substrate410, also referred to as a “carrier substrate.” After the wafer is bonded to the second substrate410, the first insulation layer260is proximal to the second substrate410(as shown inFIGS.7B and7C), while the first substrate110is distal from the second substrate410. In some embodiments, a bonding interface can be formed between the first insulation layer260and the second substrate410.

The second substrate410can be made of, e.g., an elemental semiconductor material such as silicon or germanium, a semiconductor alloy such as SiGe, a compound semiconductor material such as SiC, InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, or a composite material such as silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or a combination of any of the above materials.

After the wafer is bonded to the second substrate410, the first substrate110and the sacrificial layer120are removed such that another surface (which would be a bottom surface inFIGS.2A-6C) of the semiconductor material layer130away from the first conductive structures251are exposed, as shown inFIGS.7A-7C. The first substrate110and the sacrificial layer120can be removed by, e.g., a CMP method and/or an etching method.

FIGS.8A-8Cschematically show a next stage in the fabrication process of the memory device.FIG.8Ais a top view,FIG.8Bis a cross-sectional view along A-A′ line inFIG.8A, andFIG.8Cis a cross-sectional view along C-C′ line inFIG.8A. Similar toFIG.7A, inFIG.8A, the second spacers311are indicated using dashed lines for illustrative purposes, while in reality they may not be seeable from the top view inFIG.8A.

As shown inFIGS.8A-8C, a mask layer260is formed over the semiconductor material layer130and the first spacers211, and is then patterned to open a window that exposes the active region, and hence exposes the semiconductor material strips134each connecting a corresponding column of AA pillars132. The mask layer260can include a photolithography resist layer or a hard mask layer made of, e.g., a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.

FIGS.9A-9Cschematically show a next stage in the fabrication process of the memory device.FIG.9Ais a top view,FIG.9Bis a cross-sectional view along A-A′ line inFIG.9A, andFIG.9Cis a cross-sectional view along C-C′ line inFIG.8A. Similar toFIGS.7A and8A, inFIG.9A, the second spacers311are indicated using dashed lines for illustrative purposes, while in reality they may not be seeable from the top view inFIG.9A.

As shown inFIGS.9A-9C, silicidation is conducted, which converts at least a portion of each semiconductor material strips134into a silicide layer261(also referred to as a “silicide strip”). The process described above and below with in connection withFIGS.8A-9Cfor silicidizing the semiconductor material strips134can be collectively referred to as a silicidation process.

The silicide layers261can be considered “embedded” in the semiconductor material layer130. In the example shown inFIGS.9A-9C, an upper portion of a semiconductor material strip134is converted into a corresponding silicide layer261, and the silicide layer261does not contact the second spacers311. In some other embodiments, the entire semiconductor material strip134can be silicidized (i.e., the semiconductor material strip134can be entirely silicidized) and the silicide layer261can contact the second spacers311. Consistent with the disclosure, the bottom surface of the silicide layer261can be higher than, flush with, or lower than the upper surfaces of the second spacers311(in the orientation shown inFIGS.9B and9C).

In some embodiments, silicidation can include depositing a layer of metal material, such as aluminum, cobalt, titanium, tungsten, tantalum, or molybdenum, onto the exposed semiconductor material strips134(i.e., in the window), followed by a heat treatment, to convert silicon in at least a portion of each semiconductor material strip134into silicide. The excess metal material can then be removed.

Since the silicide layers261are formed by at least partially silicidizing the semiconductor material strips134, which, by the nature of their formation, are each aligned with a column of AA pillars132, the silicide layers261are also each automatically aligned with a corresponding column of AA pillars132. That is, the silicide layers261are “self-aligned.” With this process, even distortion occurs during the fabrication process and some AA pillars132in one column do not form a straight line as designed, the corresponding semiconductor material strip134and hence the corresponding silicide layer261formed therefrom will exhibit similar distortion and still be aligned with the column of AA pillars132. Thus, good electrical connection among the column of AA pillars132can be maintained. As such, broken circuit and resistance increasing can be avoided or minimized.

FIGS.10A-10Cschematically show another stage in the fabrication process of the memory device.FIG.10Ais a top view,FIG.10Bis a cross-sectional view along A-A′ line inFIG.10A, andFIG.10Cis a cross-sectional view along C-C′ line inFIG.10A. InFIG.10A, the gate dielectric layer230, the gate electrode layers240, the first spacers211, the second spacers311are indicated using dashed lines for illustrative purposes, while in reality they may not be seeable from the top view inFIG.10A.

As shown inFIGS.10A-10C, a second insulation layer270, first lead-out structures271, second lead-out structures272, and third lead-out structures273are formed. These lead-out structures serve to electrically coupling embedded structures to other parts of the memory device.

The first lead-out structures271are formed at positions on the top surfaces of the silicide layers261corresponding to the plurality of AA pillars132. The first lead-out structures271can be, e.g., bit line pick-ups. The shape of a first lead-out structure271can be a strip shape, similar to that of a silicide layer261. Because a silicide layer261connects and electrically couples a column of AA pillars132, as long as the first lead-out structure271can contact the corresponding silicide layer261at a certain point, all the AA pillars132in the same column can be electrically coupled together and to the first lead-out structure271, even if some AA pillars are displaced to a large extent that projections thereof on a surface of the substrate do not overlap at all with a projection of the first lead-out structure271on the surface of the substrate. As shown inFIGS.10A-10C, similar to the silicide layers261, the plurality of first lead-out structures271are arranged along the first direction and are parallel to each other, and each extends along the second direction.

As shown inFIGS.10A-10C, the first lead-out structures271penetrate through the second insulation layer270to contact and electrically couple to the corresponding silicide layers261. The first lead-out structures271can be formed by various suitable methods. In some embodiments, a plurality of trenches for the first lead-out structures271can be formed in the second insulation layer270by photolithography and etching to expose at least portions of the silicide layers261, and then a conductive material can be filled therein to form the first lead-out structures271.

The second lead-out structures272penetrate through the second insulation layer270and the semiconductor material layer130, and are electrically coupled to corresponding third conductive structures253. Since the second lead-out structures272penetrate through the semiconductor material layer130, they are also referred to as “through silicon contacts (TSCs).”

The second lead-out structures272can be formed by various suitable methods. In some embodiments, a plurality of holes can be formed in the second insulation layer270and the semiconductor material layer130by photolithography and etching, to expose the third conductive structures253, then an insulation layer can be formed on a sidewall of each hole, followed by deposition of a conductive material into the holes to form the second lead-out structures272.

The third lead-out structures273penetrate through the second insulation layer270and a portion of the semiconductor material layer130, and are electrically coupled to corresponding gate electrode layers240. The third lead-out structures273can be, e.g., word line pick-ups. The third lead-out structures273are illustratively shown inFIG.10Cusing dashed lines, while in reality they may not be seeable from the cross-sectional view inFIG.10C. The third lead-out structures273can be formed using, e.g., a method similar to that for forming the second lead-out structures272, except that the holes for the third lead-out structures273do not need to penetrate through the entire semiconductor material layer130.

Each of the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273can be made of a conductive material, such as polysilicon or metal, and the metal can include copper, aluminum, tungsten, or a combination thereof. The conductive materials for the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273can be same or different. For example, the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273can be made of tungsten. In some embodiments, after the trenches for the first lead-out structures271and the holes for the second lead-out structures272and the third lead-out structures273can be formed, the conductive material can be deposited to form the first, second, and third lead-out structures271,272, and273at once, and planarization process can be performed to remove excessive conductive material on the second insulation layer270so that the first, second, and third lead-out structures271,272, and273are separated from each other.

Other processes for forming the final memory device, such as wiring and packaging, can be further performed, descriptions of which are omitted here.

The present disclosure also provides a memory device.FIG.10Ais a top view of a portion of a memory device1000consistent with the present disclosure.FIG.10Bis a cross-sectional view along A-A′ line inFIG.10A, andFIG.10Cis a cross-sectional view along C-C′ line inFIG.10A. As shown inFIGS.10A-10C, the memory device1000includes the second substrate410, the first insulation layer260, the first conductive structures251, the second conductive structures252, the semiconductor material layer130, the first spacers211, the second spacers311, the gate dielectric layers230, the gate electrode layers240, the silicide layers261, the second insulation layer270, the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273.

The second insulation layer260is located over the second substrate410, the semiconductor material layer130is located over the second insulation layer260, and the second insulation layer270is located over the semiconductor material layer130.

The first spacers211are buried in the semiconductor material layer130, and can be made of an insulation material such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. The second spacers311are also buried in the semiconductor material layer130, and can be made of an insulation material such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. The first spacers211and the second spacers311can be made of a same material or be made of different materials.

The first spacers211can be arranged in a row along the first direction (e.g., x-direction inFIG.10A). Each of the first spacers211can extend along the second direction (e.g., y-direction inFIG.10A), and the first spacers211can be parallel to each other.

The second spacers311can be arranged in a row along the second direction. Each of the second spacers311can extend along the first direction, and the second spacers311can be parallel to each other.

As shown inFIG.10A, the first spacers211intersect the second spacers311, and together define a plurality of areas in the semiconductor material layer130. That is, at least a portion of the semiconductor material layer130is divided by the first spacers211and the second spacers311into the plurality of AA pillars132, each of which serves as an active area (AA) for a vertical-channel transistor of the memory device1000. In the example shown inFIGS.10A-10C, each of the AA pillars132has a rectangular shape. In some other embodiments, the AA pillars132can have a different shape, such as a square shape. As described above, the region of the semiconductor material layer130constituted by the active areas can also be referred to as an “active region,” i.e., the active region of the semiconductor material layer130can include a plurality of active areas (AA pillars132).

Further, as shown in, e.g.,FIG.10C, since the top surface of the second spacer311is lower than the top surface of the semiconductor material layer130, a portion of the semiconductor material layer130on the second spacers311form the plurality semiconductor material strips134parallel to each other in the first direction, and each extending in the second direction and connecting a corresponding column of AA pillars132at the bottoms of the AA pillars132.

A gate dielectric layer230is located at a sidewall of each of the AA pillars132, and a gate electrode layer240is formed on the gate dielectric layer230. The gate dielectric layers230can include a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials. The gate electrode layer240can be made of a conductive material, such as polysilicon or metal, where the metal can include, e.g., copper, aluminum, tungsten, or a combination thereof. The gate dielectric layer230and the gate electrode layer240together form a gate structure of a vertical-channel transistor in the memory device1000. In the example shown inFIG.10C, the gate structure is located on one sidewall of the AA pillar132. In some other embodiments, the gate structure can be located on more sidewalls of the AA pillar132, such as two opposite sidewalls in the second direction.

The plurality of active areas (AA pillars132) can be arranged in an array expanding along the first direction and the second direction. That is, the plurality of active areas (AA pillars132) can be considered as including one or more columns of active areas (AA pillars132) arranged along the first direction and each extending in the second direction; or the plurality of active areas (AA pillars132) can be considered as including one or more rows of active areas arranged along the second direction and each extending in the first direction. One gate dielectric layer230and one corresponding gate electrode layer240can be located on a side wall of one corresponding active area (AA pillar132). The gate electrode layers240of each row of active areas (AA pillars132) can be connected, for example, via portions of the gate electrode layer formed on the sidewalls of the first spacer pillars as described above, to form a word line of the memory device1000.

A first conductive structure251(AA pick up for the vertical-channel transistor) is located on the bottom surface of each of the plurality of active areas (AA pillars132) of the semiconductor material layer130, and a second conductive structure252is formed at the bottom surfaces of each column of first conductive structures251to electrically couple the first conductive structures251. The third conductive structures253are also formed on the bottom surface of a region of the semiconductor material layer130outside the active region, and each of the third conductive structures253can be electrically coupled to a column of first conductive structures251via a corresponding second conductive structure252. The second conductive structures252are arranged along the first direction and each second conductive structure252extends along the second direction. The second conductive structures252can be approximately parallel to each other. Each of the plurality of active areas (AA pillars132) can be electrically coupled to a corresponding one of the first conductive structures251. One column of first conductive structures251corresponding to one column of active areas AA can be electrically coupled to a corresponding second conductive structure252. A first insulation layer260is formed on the top surface of the semiconductor material layer130. The first conductive structures251, the second conductive structures252, and the third conductive structures253can be embedded in the first insulation layer260.

The first insulation layer260can be made of a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, or can be a composite layer including two or more dielectric films made of same, similar, or different materials.

The second substrate410can be made of, e.g., an elemental semiconductor material such as silicon or germanium, a semiconductor alloy such as SiGe, a compound semiconductor material such as SiC, InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, or a composite material such as silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or a combination of any of the above materials.

The silicide layers261are embedded in the semiconductor material layer130. Each silicide layer261is located on a semiconductor material stripe134connecting a corresponding column of AA pillars132. The silicide layers261can be parallel to each other and arranged in a row along the first direction. As described above, each silicide layer261can be formed by silicide a portion of a corresponding semiconductor material stripe134. In some other embodiments, a semiconductor material stripe134can be completely silicided to form a silicide layer261, i.e., the silicide layer261can completely replace the semiconductor material stripe134in the final memory device1000, and be in contact with a corresponding column of second spacers311.

The first lead-out structures271, the second lead-out structures272, and the third lead-out structures273are buried at least partially in, e.g., the second insulation layer270. These lead-out structures serve to electrically coupling embedded structures to other parts of the memory device1000.

The first lead-out structures271are located at positions on the top surfaces of the silicide layers261corresponding to the plurality of AA pillars132. The first lead-out structures271can be, e.g., bit line pick-ups. The shape of a first lead-out structure271can be a strip shape, similar to that of a silicide layer261. Because a silicide layer261connects and electrically couples a column of AA pillars132, as long as the first lead-out structure271can contact the corresponding silicide layer261at a certain point, all the AA pillars132in the same column can be electrically coupled together and to the first lead-out structure271, even if some AA pillars are displaced to a large extent that projections thereof on a surface of the substrate do not overlap at all with a projection of the first lead-out structure271on the surface of the substrate. As shown inFIGS.10A-10C, similar to the silicide layers261, the plurality of first lead-out structures271are arranged along the first direction and are parallel to each other, and each extends along the second direction. The first lead-out structures271penetrate through the second insulation layer270to contact and electrically couple to the corresponding silicide layers261.

The second lead-out structures272penetrate through the second insulation layer270and the semiconductor material layer130, and are electrically coupled to corresponding third conductive structures253. Since the second lead-out structures272penetrate through the semiconductor material layer130, they are also referred to as “through silicon contacts (TSCs).” Each second lead-out structure272can be surrounded by an insulation layer and be electrically isolated from the semiconductor material layer130by the insulation layer.

The third lead-out structures273penetrate through the second insulation layer270and a portion of the semiconductor material layer130, and are electrically coupled to corresponding gate electrode layers240. The third lead-out structures273can be, e.g., word line pick-ups. The third lead-out structures273are illustratively shown inFIG.10Cusing dashed lines, while in reality they may not be seeable from the cross-sectional view inFIG.10C.

Each of the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273can be made of a conductive material, such as polysilicon or metal, and the metal can include copper, aluminum, tungsten, or a combination thereof. The conductive materials for the first lead-out structures271, the second lead-out structures272, and the third lead-out structures273can be same or different.

FIG.11is a block diagram of an example system1100having a memory device consistent with the disclosure. The system1100can be a mobile phone (e.g., a smartphone), a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having storage therein. As shown inFIG.11, the system1100includes a memory system1102having one or more memory devices1104and a memory controller1106. The system1100further includes a host1108. The host1108can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host1108can be configured to send or receive data to or from the one or more memory devices1104. Each of the one or more memory devices1104can include a memory device consistent with the disclosure, such as one of the example memory devices described above.

The memory controller1106is coupled to the one or more memory devices1104and the host1108, and is configured to control operation of the one or more memory devices1104, according to some implementations. The memory controller1106can also be integrated into the one or more memory devices1104. The memory controller1106can manage the data stored in the one or more memory devices1104and communicate with the host1108via an interface1110. In some embodiments, the memory controller1106is designed for operating in a low duty-cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) Flash drive, or another medium for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some other embodiments, the memory controller1106is designed for operating in a high duty-cycle environment, such as a solid-state drive (SSD) or an embedded multi-media-card (eMMC) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller1106can be configured to control operations of the one or more memory devices1104, such as read, erase, and program operations.

The memory controller1106and the one or more memory devices1104can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the memory system1102can be implemented and packaged into different types of end electronic products.FIGS.12and13are block diagrams of an example memory card1200and an example SSD1300, respectively, consistent with the disclosure. As shown inFIG.12, a single memory device1202and a memory controller804are integrated into the memory card1200. The memory device1202can include a memory device consistent with the disclosure, such as one of the above-described example memory devices. The memory card1200can include a PC card (personal computer memory card international association (PCMCIA)), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), a UFS, etc. As shown inFIG.12, the memory card1200further includes a memory card interface or interface connector1206configured to couple the memory card1200to a host (e.g., the host1108shown inFIG.11).

As shown inFIG.13, multiple memory devices1302and a memory controller1304are integrated into the SSD1300. Each of the memory devices1302can include a memory device consistent with the disclosure, such as one of the above-described example memory devices. As shown inFIG.13, the SSD1300further includes an SSD interface or interface connector1306configured to couple the SSD1300to a host (e.g., the host1108shown inFIG.11).

Although the principles and implementations of the present disclosure are described by using specific embodiments in the specification, the foregoing descriptions of the embodiments are only intended to help understand the idea of the present disclosure. A person of ordinary skill in the art can make modifications to the specific implementations and application range according to the idea of the present disclosure. For example, one or more components of the disclosed memory device can be omitted or one or more components not explicitly described above can be added to the memory device. Similarly, one or more steps in the fabrication process of the memory device can be omitted or one or more steps not explicitly described above can be included in the fabrication process. The content of the specification should not be construed as a limitation to the present disclosure.