THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

A three-dimensional semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes on the first substrate, a second dielectric layer on the stack structure, a cell contact plug that extends through the second dielectric layer and the contact region, a selection mold structure on the stack structure and the second dielectric layer, a third dielectric layer on the selection mold structure, and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact has a second width. The capping through contact has a first width. The second width is different from the first width.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2023-0035025 filed on Mar. 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relate to a three-dimensional semiconductor memory device, and more particularly, to a nonvolatile three-dimensional semiconductor memory device including a vertical channel structure, a method of fabricating the same, and an electronic system including a three-dimensional semiconductor memory device.

BACKGROUND

It may be desirable to have a semiconductor device that is capable of storing a large amount of data in an electronic system. A semiconductor device has been highly integrated to meet high performance and low manufacturing costs. Integration of typical two-dimensional or planar semiconductor devices may be determined by the area occupied by a unit memory cell, such that it is influenced by the level of technology for forming fine patterns. However, the expensive processing equipment used to increase pattern fineness may inhibit the integration of the two-dimensional or planar semiconductor devices.

SUMMARY

Some embodiments of the present disclosure provide a three-dimensional semiconductor memory device with increased reliability and improved electrical properties.

Some embodiments of the present disclosure provide an electronic system including the three-dimensional semiconductor memory device.

An object of the present disclosure is not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description.

According to some embodiments of the present disclosure, a three-dimensional semiconductor memory device may comprise: a first substrate that includes a cell array region and a contact region that extends from the cell array region; a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the first substrate; a second dielectric layer on the stack structure; a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure; a selection mold structure on the stack structure and the second dielectric layer; a third dielectric layer on the selection mold structure; and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact may have a second width in a direction that is parallel to a top surface of the first substrate. The capping through contact may have a first width in the direction that is parallel to a top surface of the first substrate. The second width may be different from the first width.

According to some embodiments of the present disclosure, a three-dimensional semiconductor memory device may comprise: a first substrate that includes a cell array region and a contact region that extends from the cell array region; a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the first substrate; a second dielectric layer on the stack structure; a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure; a selection mold structure on the stack structure and the second dielectric layer; a third dielectric layer on the selection mold structure; a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug; and a spacer dielectric layer between the selection mold structure and a sidewall of the capping through contact.

According to some embodiments of the present disclosure, an electronic system may comprise: a first substrate that includes a cell array region and a contact region that extends from the cell array region; a three-dimensional semiconductor memory device that includes a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, a dielectric layer on the cell array structure, and an input/output pad on the dielectric layer and connected to the peripheral circuit structure; and a controller connected to the three-dimensional semiconductor memory device through the input/output pad. The cell array structure may include: a second substrate on the peripheral circuit structure; a stack structure that includes interlayer dielectric layers and gate electrodes that are alternately stacked on the second substrate; a second dielectric layer on the stack structure; a cell contact plug that extends through the second dielectric layer and the contact region of the stack structure; a selection mold structure on the stack structure and the second dielectric layer; a third dielectric layer on the selection mold structure; and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact may have a second width in a direction that is parallel to a top surface of the first substrate. The capping through contact may have a first width in the direction that is parallel to the top surface of the first substrate. The second width may be greater than the first width.

DETAILED DESCRIPTION OF EMBODIMENTS

To clarify the present disclosure, parts that are not connected with the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. Further, since sizes and thicknesses of constituent members shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the illustrated sizes and thicknesses. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for better understanding and ease of description, thicknesses of some layers and areas are excessively displayed.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

In addition, unless explicitly described to the contrary, the word “comprises”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. As used herein, the phrase “at least one of A, B, and C” refers to a logical (A OR B OR C) using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B and at least one of C.” As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components and/or groups thereof. The term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, “an element A is at a same level as element B” refers to at least one surface of element A that is coplanar with at least one surface of element B. The term “connected” may be used herein to refer to a physical and/or electrical connection and may refer to a direct or indirect physical and/or electrical connection.

In conjunction with the accompanying drawings, the following will describe in detail a three-dimensional semiconductor memory device, a method of fabricating the same, and an electronic system including the same.

FIG.1illustrates a block diagram of an electronic system that includes a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIG.1, an electronic system1000according to some embodiments of the present disclosure may include a three-dimensional semiconductor memory device1100and a controller1200electrically connected to the three-dimensional semiconductor memory device1100. The electronic system1000may be a storage device that includes a single or a plurality of three-dimensional semiconductor memory devices1100or may be an electronic device that includes the storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical apparatus, or a communication apparatus, where each includes a single or a plurality of three-dimensional semiconductor memory devices1100.

The three-dimensional semiconductor memory device1100may be a nonvolatile memory device, such as a three-dimensional NAND Flash memory device, which will be discussed below. The three-dimensional semiconductor memory device1100may include a first region1100F and a second region1100S on the first region1100F. For example, the first region1100F may be on a side of the second region1100S. The first region1100F may be a peripheral circuit region that includes a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second region1100S may be a memory cell region that includes bit lines BL, a common source line CSL, word lines WL, first lines LL1and LL2, second lines UL1and UL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

On the second region1100S, each of the memory cell strings CSTR may include first transistors LT1and LT2adjacent to the common source line CSL, second transistors UT1and UT2adjacent to the bit line BL, and memory cell transistors MCT between the first transistors LT1and LT2and the second transistors UT1and UT2. The number of the first transistors LT1and LT2and of the second transistors UT1and UT2may vary in other embodiments and is not limited to the example described herein.

For example, the first transistors LT1and LT2may include a ground selection transistor, and the second transistors UT1and UT2may include a string selection transistor. The first lines LL1and LL2may be gate electrodes of the first transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT. The second lines UL1and UL2may be gate electrodes of the second transistors UT1and UT2, respectively.

For example, the first transistors LT1and LT2may include a first erase control transistor LT1and a ground selection transistor LT2that are connected in series. The second transistors UT1and UT2may include a string selection transistor UT1and a second erase control transistor UT2that are connected in series. One or both of the first and second erase control transistors LT1and UT2may be employed to perform an erase operation in which a gate induced drain leakage (GIDL) phenomenon is used to erase data stored in the memory cell transistors MCT.

The common source line CSL, the first lines LL1and LL2, the word lines WL, and the second lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection lines1115that extend from the first region1100F toward the second region1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection lines1125that extend from the first region1100F toward the second region1100S.

On the first region1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selection memory cell transistor among the plurality of memory cell transistors MCT. The logic circuit1130may control the decoder circuit1110and the page buffer1120. The three-dimensional semiconductor memory device1100may communicate with the controller1200through an input/output pad1101electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection line1135that extends from the first region1100F toward the second region1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. For example, the electronic system1000may include a plurality of three-dimensional semiconductor memory devices1100, and in this case, the controller1200may control the plurality of three-dimensional semiconductor memory devices1100.

The processor1210may control an overall operation of the electronic system1000that includes the controller1200. The processor1210may operate based on certain firmware, and may control the NAND controller1220to access the three-dimensional semiconductor memory device1100. The NAND controller1220may include a NAND interface1221that processes communication with the three-dimensional semiconductor memory device1100. The NAND interface1221may be used to transfer a control command that controls the three-dimensional semiconductor memory device1100, data to be written on the memory cell transistors MCT of the three-dimensional semiconductor memory device1100, and/or data to be read from the memory cell transistors MCT of the three-dimensional semiconductor memory device1100. The host interface1230may provide the electronic system1000with communication with an external host. When a control command is received through the host interface1230from an external host, the three-dimensional semiconductor memory device1100may be controlled by the processor1210in response to the control command.

FIG.2illustrates a simplified perspective view showing an electronic system that includes a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIG.2, an electronic system2000according to some embodiments of the present disclosure may include a main board2001, a controller2002mounted on the main board2001, at least one semiconductor package2003, and a dynamic random access memory (DRAM)2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002through wiring patterns2005provided in the main board2001.

The main board2001may include a connector2006including a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector2006are based on a communication interface between the electronic system2000and the external host. The electronic system2000may communicate with the external host through one or more interfaces, for example, universal serial bus (USB), peripheral component interconnect express (PIC-Express), serial advanced technology attachment (SATA), and M-PHY for universal flash storage (UFS). For example, the electronic system2000may operate with power that is supplied through the connector2006from the external host. The electronic system2000may further include a power management integrated circuit (PMIC) by which the power supplied from the external host is distributed to the controller2002and the semiconductor package2003.

The controller2002may write data to the semiconductor package2003, may read data from the semiconductor package2003, or may increase an operating speed of the electronic system2000.

The DRAM2004may be a buffer memory that reduces a difference in speed between the external host and the semiconductor package2003that serves as a data storage space. The DRAM2004included in the electronic system2000may operate as a cache memory, and may provide a space for temporary data storage in a control operation of the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the controller2002may include not only a NAND controller for controlling the semiconductor package2003, but also a DRAM controller for controlling the DRAM2004.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bthat are spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay include a plurality of semiconductor chips2200. Each of the first and second semiconductor package2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesion layers2300on bottom surfaces of the semiconductor chips2200, connection structures2400that electrically connect the semiconductor chips2200to the package substrate2100, and a molding layer2500on the package substrate2100and that covers the semiconductor chips2200and the connection structures2400.

The package substrate2100may be an integrated circuit board including package upper pads2130. Each of the semiconductor chips2200may include input/output pads2210. Each of the input/output pads2210may correspond to the input/output pad1101ofFIG.1. Each of the semiconductor chips2200may include gate stack structures3210and vertical channel structures3220. Each of the semiconductor chips2200may include a three-dimensional semiconductor memory device, which will be discussed below.

For example, the connection structures2400may be bonding wires that electrically connect the input/output pads2210to the package upper pads2130. On each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other in a wire bonding manner, and may be electrically connected to the package upper pads2130of the package substrate2100. In some embodiments, on each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other using through-silicon vias (TSVs) instead of the connection structures2400or the bonding wires.

For example, the controller2002and the semiconductor chips2200may be included in a single package. For example, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate other than the main board2001, and may be connected to each other through lines provided in the interposer substrate.

FIGS.3and4illustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.2, showing a semiconductor package that includes a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIGS.3and4, a semiconductor package2003may include a package substrate2100, a plurality of semiconductor chips on the package substrate2100, and a molding layer2500on and covering the package substrate2100and the plurality of semiconductor chips.

The package substrate2100may include a package substrate body2120, package upper pads2130on a top surface of the package substrate body2120, package lower pads2125exposed at a bottom surface of the package substrate body2120, and internal wiring lines2135in the package substrate body2120and that electrically connect the package upper pads2130to the package lower pads2125. The package upper pads2130may be electrically connected to a plurality of connection structures2400. The package lower pads2125may be connected through conductive connectors2800to the wiring patterns2005in the main board2001of the electronic system2000depicted inFIG.2.

Each of the semiconductor chips2200may include a semiconductor substrate3010, and may also include a first structure3100and a second structure3200that are sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral wiring lines3110. The second structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, vertical channel structures3220and separation structure3230that extend through the gate stack structure3210, bit lines3240electrically connected to the vertical channel structures3220, gate connection lines3235and conductive lines3250that are electrically connected to word lines (see WL ofFIG.1) of the gate stack structure3210.

Each of the semiconductor chips2200may include one or more through wiring lines3245that extend into the second structure3200and are electrically connected to the peripheral wiring lines3110of the first structure3100. The through wiring line3245may extend through the gate stack structure3210, and may further be arranged outside the gate stack structure3210. Each of the semiconductor chips2200may further include an input/output connection line3265that is electrically connected to the peripheral wiring lines3110of the first structure3100, and may also further include input/output pads2210electrically connected to the input/output connection line3265.

FIG.5illustrates a plan view showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.FIGS.6A and6Billustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.5, showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIGS.5,6A, and6B, a three-dimensional semiconductor memory device according to the present disclosure may include a first substrate10, a peripheral circuit structure PS on the first substrate10, and a cell array structure CS on the peripheral circuit structure PS. The first substrate10, the peripheral circuit structure PS, and the cell array structure CS may respectively correspond to the semiconductor substrate3010, the first structure3100on the semiconductor substrate3010, and the second structure3200on the first structure3100ofFIGS.3and4.

The first substrate10may include a cell array region CAR and a contact region CCR. The first substrate10may extend in a first direction D1directed from the cell array region CAR toward the contact region CCR and in a second direction D2that intersects the first direction D1. The first substrate10may have a top surface perpendicular to a third direction D3that intersects the first and second directions D1and D2. For example, the first, second, and third directions D1, D2, and D3may be orthogonal to each other.

When viewed in plan, the contact region CCR may extend in the first direction D1(or a direction opposite to the first direction D1) from the cell array region CAR. The cell array region CAR may be an area on which the vertical channel structure3220, the separation structures3230, and the bit lines3240are provided. The contact region CCR may be an area on which a stepwise structure including pads parts ELp are provided, which will be discussed below. Although not shown, the contact region CCR may extend in the second direction D2(or a direction opposite to the second direction D2) from the cell array region CAR.

The first substrate10may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The first substrate10may include a device isolation layer11that defines an active section of the first substrate10. The device isolation layer11may include, for example, silicon oxide.

The peripheral circuit structure PS may be provided on the first substrate10. The peripheral circuit structure PS may include peripheral circuit transistors PTR on the active section of the first substrate10, peripheral contact plugs31, peripheral circuit lines33electrically connected to the peripheral circuit transistors PTR through the peripheral contact plugs31, and a first dielectric layer30that surrounds the peripheral circuit transistors PTR, the peripheral contact plugs31, and the peripheral circuit lines33. The peripheral circuit structure PS may correspond to the first region1100F ofFIG.1, and the peripheral circuit lines33may correspond to the peripheral wiring lines3110ofFIGS.3and4.

A peripheral circuit may include the peripheral circuit transistors PTR, the peripheral contact plugs31, and the peripheral circuit lines33. For example, the peripheral circuit transistors PTR may correspond to the decoder circuit1110, the page buffer1120, and the logic circuit1130ofFIG.1. In more detail, each of the peripheral circuit transistors PTR may include a peripheral gate dielectric layer21, a peripheral gate electrode23, a peripheral capping pattern25, a peripheral gate spacer27, and peripheral source/drain sections29.

The peripheral gate dielectric layer21may be provided between the peripheral gate electrode23and the first substrate10. The peripheral capping pattern25may be provided on the peripheral gate electrode23. The peripheral gate spacer27may be on and/or cover a sidewall of the peripheral gate dielectric layer21, a sidewall of the peripheral gate electrode23, and a sidewall of the peripheral capping pattern25. The peripheral source/drain sections29may be provided in the first substrate10adjacent to opposite sides of the peripheral gate electrode23. The peripheral circuit lines33may be electrically connected to the peripheral circuit transistors PTR through the peripheral contact plugs31. Each of the peripheral circuit transistors PTR may be, for example, an NMOS transistor, a PMOS transistor, or a gate-all-around type transistor. For example, the peripheral contact plugs31may each have a width in the first direction D1or the second direction D2that increases as the distance between the peripheral contact plugs31and the first substrate10increases in the third direction D3. The peripheral contact plugs31and the peripheral circuit lines33may include a conductive material, such as metal.

The first dielectric layer30may be on the top surface of first substrate10. On the first substrate10, the first dielectric layer30may cover the peripheral circuit transistors PTR, the peripheral contact plugs31, and the peripheral circuit lines33. The first dielectric layer30may include a plurality of dielectric layers that constitute a multi-layered structure. For example, the first dielectric layer30may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials.

The first dielectric layer30may be provided thereon with the cell array structure CS that includes a second substrate100and a stack structure ST on the second substrate100. The second substrate100may extend in the first and second directions D1and D2. The second substrate100may not be provided on a partial area of the contact region CCR. The second substrate100may be a semiconductor substrate including a semiconductor material. The second substrate100may include, for example, at least one selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium-gallium-arsenic (InGaAs), aluminum-gallium-arsenic (AlGaAs), and a combination thereof.

The stack structure ST may be provided on the second substrate100. The stack structure ST may extend from the cell array region CAR toward the contact region CCR. The stack structure ST may correspond to the gate stack structures3210ofFIGS.3and4. The stack structure ST may be provided in plural, and the plurality of stack structures ST may be arranged along the second direction D2and spaced apart in the second direction D2from each other across a separation structure150, which will be discussed below. For convenience of description, the following explanation will focus on a single stack structure ST, but this explanation may also be applicable to other stack structures ST.

The stack structure ST may include first and second interlayer dielectric layers ILDa and ILDb and first and second gate electrodes ELa and ELb that are alternately stacked. The first and second gate electrodes ELa and ELb may correspond to the word lines WL, the first lines LL1and LL2, and the second lines UL1and UL2ofFIG.1.

The stack structure ST may include, for example, a first stack structure ST1on the second substrate100and a second stack structure ST2on the first stack structure ST1. The first stack structure ST1may include the first interlayer dielectric layers ILDa and the first gate electrodes ELa that are alternately stacked, and the second stack structure ST2may include the second interlayer dielectric layers ILDb and the second gate electrodes ELb that are alternately stacked. The first and second gate electrodes ELa and ELb may have substantially the same thickness in the third direction D3. In this description below, the term “thickness” may indicate a thickness in the third direction D3.

The first and second gate electrodes ELa and ELb may have their lengths in the first direction D1that decrease as the distance between the first and second gate electrodes Ela and ELb and the second substrate100increase in the third direction D3. For example, each of the first and second gate electrodes ELa and ELb may have a length in the first direction D1that is greater than a length in the first direction D1of an immediately overlying gate electrode. A lowermost one of the first gate electrodes ELa included in the first stack structure ST1may have a maximum length in the first direction D1, and an uppermost one of the second gate electrodes ELb included in the second stack structure ST2may have a minimum length in the first direction D1.

The first and second gate electrodes ELa and ELb may have their pad parts ELp on the contact region CCR. The pad parts ELp of the first and second gate electrodes ELa and ELb may be arranged at different horizontal and vertical positions. The pad parts ELp may constitute a stepwise structure along the first direction D1.

The stepwise structure may be arranged such that each of the first and second stack structures ST1and ST2may have a thickness that decreases as the distance between the first and second stack structures ST1and ST2and an outermost one of vertical channel structures VS increases, which will be discussed below. As such, the first and second gate electrodes ELa and ELb may have their sidewalls spaced apart from each other along the first direction D1at a regular interval when viewed in plan.

The first and second electrodes ELa and ELb may include, for example, at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and transition metals (e.g., titanium, tantalum, etc.). For example, the first and second gate electrodes ELa and ELb may include tungsten.

The first and second interlayer dielectric layers ILDa and ILDb may be provided between the first and second gate electrodes ELa and ELb, and may each have a sidewall aligned with that of an underlying one of the first and second gate electrodes ELa and ELb. For example, similar to the first and second gate electrodes ELa and ELb, the first and second interlayer dielectric layers ILDa and ILDb may have their lengths in the first direction D1that decrease as the distance between first and second interlayer dielectric layers ILDa and ILDb and the second substrate100increase in the third direction D3.

A lowermost one of the second interlayer dielectric layers ILDb may be in contact with an uppermost one of the first interlayer dielectric layers ILDa. For example, each of the first and second interlayer dielectric layers ILDa and ILDb may have a thickness less than that of each of the first and second gate electrodes ELa and ELb. For example, a lowermost one of the first interlayer dielectric layers ILDa may have a thickness less than that of each of other first and second interlayer dielectric layers ILDa and ILDb. For example, an uppermost one of the second interlayer dielectric layers ILDb may have a thickness greater than that of each of other first and second interlayer dielectric layers ILDa and ILDb.

Except the lowermost first interlayer dielectric layer ILDa and the uppermost second interlayer dielectric layer ILDb, other first and second interlayer dielectric layers ILDa and ILDb may have substantially the same thickness. This, however, is merely an example, and the first and second interlayer dielectric layers ILDa and ILDb may have other thicknesses that are based on properties of a semiconductor device.

The first and second interlayer dielectric layers ILDa and ILDb may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials. For example, the first and second interlayer dielectric layers ILDa and ILDb may include high-density plasma (HDP) oxide or tetraethylorthosilicate (TEOS).

A source structure SC may be provided between the lowermost first interlayer dielectric layer ILDa and the second substrate100on the cell array region CAR. The source structure SC may correspond to the common source line CSL ofFIG.1or the common source line3205ofFIGS.3and4. The source structure SC may include a first source conductive pattern SCP1and a second source conductive pattern SCP2that are sequentially stacked on the second substrate100. The second source conductive pattern SCP2may be provided between the first source conductive pattern SCP1and the lowermost first interlayer dielectric layer ILDa. The first source conductive pattern SCP1may have a thickness greater than that of the second source conductive pattern SCP2. The first and second source conductive patterns SCP1and SCP2may include a semiconductor material, such as silicon or a semiconductor material doped with impurities. When the first and second source conductive patterns SCP1and SCP2include an impurity-doped semiconductor material, the first source conductive pattern SCP1may have an impurity concentration greater than that of the second source conductive pattern SCP2.

The first source conductive pattern SCP1of the source structure SC may be provided only on the cell array region CAR, but not on the contact region CCR. The second source conductive pattern SCP2of the source structure SC may extend from the cell array region CAR to the contact region CCR. The second source conductive pattern SCP2on the contact region CCR may be referred to as a “second semiconductor layer123,” which will be discussed below.

A first mold structure MS1may be provided between the lowermost first interlayer dielectric layer ILDa and the second substrate100on the contact region CCR. The first mold structure MS1may include a first buffer dielectric layer111, a first semiconductor layer121, a second buffer dielectric layer113, and a second semiconductor layer123that are sequentially stacked on the second substrate100.

The first semiconductor layer121may be provided between the second substrate100and the second semiconductor layer123. The first buffer dielectric layer111may be provided between the second substrate100and the first semiconductor layer121, and the second buffer dielectric layer113may be provided between the first semiconductor layer121and the second semiconductor layer123. The first buffer dielectric layer111may have a bottom surface substantially coplanar with that of the first source conductive pattern SCP1. The second buffer dielectric layer113may have a top surface substantially coplanar with that of the first source conductive pattern SCP1.

The first and second buffer dielectric layers111and113may include, for example, silicon oxide. The first and second semiconductor layers121and123may include a semiconductor material, such as silicon.

On the cell array region CAR, a plurality of vertical channel structures VS may extend through the stack structure ST and the source structure SC. The vertical channel structures VS may extend through at least a portion of the second substrate100, and each of the vertical channel structures VS may have a bottom surface located at a lower level than that of a top surface of the second substrate100and that of a bottom surface of the source structure SC. Stated differently, a distance between the first substrate10and a bottom surface of each of the vertical channel structures VS is less than a distance between the first substrate10and a top surface of the second substrate100and a distance between the first substrate10and a bottom surface of the source structure SC. For example, the vertical channel structures VS may be in direct contact with the second substrate100.

When viewed in plan as shown inFIG.5, the vertical channel structures VS may be arranged in a zigzag fashion along the first direction D1or the second direction D2. The vertical channel structures VS may not be provided on the contact region CCR. The vertical channel structures VS may correspond to the vertical channel structures3220ofFIGS.2to4. The vertical channel structures VS may correspond to channels of the first transistors LT1and LT2depicted inFIG.1and channels of the memory cell transistors MCT depicted inFIG.1.

The vertical channel structures VS may be provided in vertical channel holes CH that extend through the stack structure ST. Each of the vertical channel holes CH may include a first vertical channel hole CH1that extends through the first stack structure ST1and a second vertical channel hole CH2that extends through the second stack structure ST2. The first and second vertical channel holes CH1and CH2of each of the vertical channel holes CH may be connected to each other in the third direction D3.

Each of the vertical channel structures VS may include a first part VSa and a second part VSa. The first part VSa may be provided in the first vertical channel hole CH1, and the second part VSb may be provided in the second vertical channel hole CH2. The second part VSb may be provided on and connected to the first part VSa.

The first part VSa and the second part VSb may each have a width in the first direction D1or the second direction D2that increases in the third direction D3. An uppermost portion of the first part VSa may have a width greater than that of a lowermost portion of the second part VSb. For example, each of the vertical channel structures VS may have a sidewall that has a step difference at a boundary between the first part VSa and the second part VSb. This, however, is merely an example, and the present disclosure is not limited thereto. For example, each of the vertical channel structures VS may have a sidewall that has three or more step differences at different levels or that is flat with no step difference.

Each of the vertical channel structures VS may include a data storage pattern DSP and a vertical semiconductor pattern VSP that are sequentially provided on an inner sidewall of the vertical channel holes CH, a buried dielectric pattern VI that fills an inner space surrounded by the vertical semiconductor pattern VSP, and a conductive pad PAD on the buried dielectric pattern VI. The conductive pad PAD may be provided in a space surrounded by the buried dielectric pattern VI and the data storage pattern DSP (or the vertical semiconductor pattern VSP). The vertical channel structures VS may each have a top surface that has, for example, a circular shape, an oval shape, or a bar shape. The data storage pattern DSP may be adjacent to the stack structure ST to cover sidewalls of the first and second interlayer dielectric layers ILDa and ILDb and sidewalls of the first and second gate electrodes ELa and ELb. The vertical semiconductor pattern VSP may conformally cover an inner sidewall of the data storage pattern DSP.

The vertical semiconductor pattern VSP may be provided between the data storage pattern DSP and the buried dielectric pattern VI. The vertical semiconductor pattern VSP may have a macaroni shape or a pipe shape whose bottom end is closed. The data storage pattern DSP may have a cylindrical shape whose bottom end is opened.

The vertical semiconductor pattern VSP may include, for example, an impurity-doped semiconductor material, an impurity-undoped intrinsic semiconductor material, or a polycrystalline semiconductor material. As discussed below with reference toFIG.7B, the vertical semiconductor pattern VSP may contact a portion of the source structure SC. The conductive pad PAD may include, for example, an impurity-doped semiconductor material or a conductive material.

On the contact region CCR, a plurality of dummy vertical channel structures DVS may extend through a second dielectric layer170, which will be discussed below, the stack structure ST, and the first mold structure MS1. For example, the dummy vertical channel structures DVS may extend through the pad parts ELp of the first and second gate electrodes ELa and ELb. The dummy vertical channel structures DVS may be provided around cell contact plugs CCP, which will be discussed below. The dummy vertical channel structures DVS may not be provided on the cell array region CAR. The dummy vertical channel structures DVS and the vertical channel structures VS may be formed simultaneously with each other and may have substantially the same structure. According to some embodiments, the dummy vertical channel structures DVS may not be provided or not be formed simultaneously with the vertical channel structures VS.

On the contact region CCR, a second dielectric layer170may be provided on and cover the stack structure ST and a portion of the first dielectric layer30. For example, the second dielectric layer170may cover the stepwise structure of the stack structure ST, and may be provided on the pad parts ELp of the first and second gate electrodes ELa and ELb. The second dielectric layer170may have a top surface that is substantially flat. The top surface of the second dielectric layer170may be substantially coplanar with an uppermost surface of the stack structure ST. For example, the top surface of the second dielectric layer170may be substantially coplanar with that of the uppermost second interlayer dielectric layer ILDb of the stack structure ST.

The second dielectric layer170may include a single or a plurality of stacked dielectric layers. The second dielectric layer170may include a dielectric material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials. The second dielectric layer170may include a dielectric material different from that of the first and second interlayer dielectric layers ILDa and ILDb of the stack structure ST. For example, when the first and second interlayer dielectric layers ILDa and ILDb of the stack structure ST include high-density plasma oxide, the second dielectric layer170may include tetraethylorthosilicate (TEOS).

A selection mold structure SSLM and a third dielectric layer260may be provided on the second dielectric layer170and the stack structure ST. The selection mold structure SSLM may include a first capping dielectric layer210, a second capping dielectric layer220, a third capping dielectric layer230, a selection semiconductor layer240, and a mold dielectric layer250that are sequentially stacked. The first capping dielectric layer210may be on and cover a top surface of the second dielectric layer170, the top surface of the uppermost second interlayer dielectric layer ILDb of the stack structure ST, and top surfaces of the vertical channel structures VS.

The first capping dielectric layer210, the second capping dielectric layer220, the third capping dielectric layer230, the mold dielectric layer250, and the third dielectric layer260may each include a single dielectric layer or a plurality of stacked dielectric layers. The first capping dielectric layer210, the second capping dielectric layer220, the third capping dielectric layer230, the mold dielectric layer250, and the third dielectric layer260may each include, for example, one or more of silicon oxide, silicon oxynitride, and low-k dielectric materials. The first capping dielectric layer210, the third capping dielectric layer230, the mold dielectric layer250, and the third dielectric layer260may each include, for example, a dielectric material substantially the same as that of the second dielectric layer170. The second capping dielectric layer220may include silicon nitride. The selection semiconductor layer240may include, for example, polycrystalline silicon.

When the stack structure ST is provided in plural, a separation structure150may be provided in a first trench TR1that runs in the first direction D1across between the plurality of stack structures ST. The first trench TR1may extend along the first direction D1from the cell array region CAR toward the contact region CCR of the first substrate10. The separation structure150may be spaced apart in the second direction D2from the vertical channel structures VS. For example, the separation structure150may have a top surface located at a higher level than that of the top surfaces of the vertical channel structures VS. Stated differently, a distance between the first substrate10(or the second substrate100) and a top surface of the separation structure150is greater than a distance between the first substrate10(or the second substrate) and top surfaces of the vertical channel structures VS. The top surface of the separation structure150may be coplanar with that of the first capping dielectric layer210. The separation structure150may have a bottom surface which is substantially coplanar with that of the second source conductive pattern SCP2and which is located at a higher level than that of the top surface of the second substrate100.

The separation structure150may be provided in plural, and the plurality of separation structures150may be spaced apart in the second direction D2from each other across the stack structure ST. The separation structure150may correspond to the separation structure3230ofFIGS.3and4.

A separation spacer130may be provided between the separation structure150and the stack structure ST and may surround the separation structure150. The separation spacer130may conformally cover the sidewalls of the first and second interlayer dielectric layers ILDa and ILDb and the sidewalls of the first and second gate electrodes ELa and ELb. The separation structure150and the separation spacer130may include, for example, silicon oxide.

Cell contact plugs CCP may be provided that extend through the second dielectric layer170and are connected to the first and second gate electrodes ELa and ELb. Each of the cell contact plugs CCP may extend through one of the first and second interlayer dielectric layers ILDa and ILDb to directly contact one of the pad parts ELp of the first and second gate electrodes ELa and ELb. The cell contact plugs CCP may correspond to the gate connection lines3235ofFIG.4.

Each of the cell contact plugs CCP may be spaced apart in a horizontal direction and electrically separated from the first and second gate electrodes ELa and ELb below the pad parts ELp across a first dielectric pattern IP1, which horizontal direction is one direction on a plane parallel to the first direction D1and the second direction D2. Each of the cell contact plugs CCP may be spaced apart in the horizontal direction and electrically separated from the second substrate100across a second dielectric pattern IP2. The first and second dielectric patterns IP1and IP2may include the same material as that of the first and second interlayer dielectric layers ILDa and ILDb of the stack structure ST. Each of the cell contact plugs CCP may have a bottom surface located at a lower level than that of a bottom surface of the second substrate100. Stated differently, a distance between the first substrate10and a bottom surface of the cell contact plugs CCP is less than a distance between the first substrate and a bottom surface of the second substrate100. A height in the third direction D3of each of the cell contact plugs CCP may be substantially the same as a height in the third direction D3of a peripheral contact plug TCP.

The peripheral contact plug TCP may extend through the second dielectric layer170and at least a portion of the first dielectric layer30to be electrically connected to the peripheral circuit transistor PTR of the peripheral circuit structure PS. In other embodiments, the peripheral contact plug TCP may be provided in plural. The peripheral contact plug TCP may be spaced apart in the first direction D1from the second substrate100, the source structure SC, and the stack structure ST. The peripheral contact plug TCP may correspond to the through wiring line3245ofFIGS.3and4.

The cell contact plug CCP and the peripheral contact plug TCP may include a conductive pattern including at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt and a barrier pattern including a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CON) layer, and a platinum nitride (PtN) layer.

For example, the cell contact plug CCP and the peripheral contact plug TCP may each have a width in the first direction D1or the second direction D2that increases in the third direction D3.

On the cell array region CAR, a plurality of upper vertical channel structures UVS may be provided that extend through the selection mold structure SSLM. When viewed in plan as shown inFIG.5, the upper vertical channel structures UVS may be arranged in a zigzag fashion along the first direction D1or the second direction D2. The upper vertical channel structure UVS may vertically overlap (e.g., in the third direction D3) with the vertical channel structure VS, and when viewed in plan, the upper vertical channel structure UVS and the vertical channel structure VS may be provided at substantially the same position and electrically connected to each other. The upper vertical channel structure UVS may have a top surface coplanar with that of the mold dielectric layer250. The upper vertical channel structures UVS may not be provided on the contact region CCR. The upper vertical channel structures UVS may correspond to the vertical channel structures3220ofFIGS.2to4. The upper vertical channel structures UVS may correspond to channels of the second transistors UT1and UT2depicted inFIG.1.

A separation dielectric pattern241may be provided to extend in the third direction D3through the selection semiconductor layer240and to extend in the first direction D1across the selection semiconductor layer240. The separation dielectric pattern241may extend along the first direction D1. The separation dielectric pattern241may have a top surface coplanar with that of the selection semiconductor layer240. The upper vertical channel structure UVS may not be provided on a portion where the separation dielectric pattern241is located. For example, the separation dielectric pattern241may be horizontally spaced apart from the upper vertical channel structure UVS.

Between two separation structures150that are spaced apart from each other in the second direction D2, the separation dielectric pattern241may separate a string selection line of a three-dimensional NAND Flash memory device.

A separation dummy pattern242may be provided in the selection semiconductor layer240. The separation dummy pattern242may include, for example, silicon oxide. A dummy through contact DTC may be disposed in and extend through the separation dummy pattern242. The separation dummy pattern242may be interposed between the selection semiconductor layer240and a sidewall part of the dummy through contact DTC. The separation dummy pattern242may have a top surface coplanar with that of the selection semiconductor layer240.

A capping through contact CTC may be provided to extend through the first capping dielectric layer210, the second capping dielectric layer220, and the third capping dielectric layer230. The capping through contact CTC may be electrically connected to the cell contact plug CCP or the peripheral contact plug TCP. The capping through contact CTC may be on and vertically overlap (e.g., in the third direction D3) with the cell contact plug CCP or the peripheral contact plug TCP.

Contact plugs CP may extend through the third dielectric layer260and the mold dielectric layer250. The contact plug CP may be electrically connected to the dummy through contact DTC. Each of the contact plugs CP may be on and vertically overlap (e.g., in the third direction D3) with the dummy through contact DTC.

Bit-line contact plugs BLCP may extend through the third dielectric layer260to be electrically connected to the upper vertical channel structures UVS. The bit-line contact plugs BLCP may include a metallic material, such as tungsten.

The third dielectric layer260may be provided thereon with bit lines BL connected to the bit-line contact plugs BLCP. The bit lines BL may correspond to the bit lines BL ofFIG.1and/or the bit lines3240ofFIGS.3and4.

The third dielectric layer260may be provided thereon with first conductive lines CL1and second conductive lines CL2that are connected to the contact plugs CP. The first conductive lines CL1may be electrically connected to the cell contact plugs CCP through corresponding contact plugs CP, corresponding dummy through contacts DTC, and corresponding capping through contacts CTC. The second conductive lines CL2may be electrically connected to the peripheral contact plugs TCP through corresponding contact plugs CP, corresponding dummy through contacts DTC, and corresponding capping through contacts CTC. The first and second conductive lines CL1and CL2may correspond to the conductive lines3250ofFIG.4.

A conductive material, such as metal, may be included in the bit-line contact plugs BLCP, the cell contact plugs CCP, the peripheral contact plug TCP, the capping through contact CTC, the dummy contact plugs DTC, the contact plugs CT, the bit lines BL, and the first and second conductive lines CL1and CL2. Although not shown, the third dielectric layer260may be provided thereon with additional wiring lines and additional vias that are electrically connected to the bit lines BL and the first and second conductive lines CL1and CL2.

FIG.7Aillustrates an enlarged view of section A depicted inFIG.6A, partially showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.FIG.7Billustrates an enlarged view of section B depicted inFIG.6A, partially showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIGS.6A,7A, and7B, the source structure SC is illustrated and includes the first and second source conductive patterns SCP1and SCP2, and one of the vertical channel structures VS is illustrated and includes the data storage pattern DSP, the vertical semiconductor pattern VSP, the buried dielectric pattern VI, and a lower data storage pattern DSPr. For convenience of description, the following explanation will focus on a single stack structure ST and a single vertical channel structure VS, but this explanation may also be applicable to other vertical channel structures VS that extend through other stack structures ST.

The data storage pattern DSP may include a blocking dielectric layer BLK, a charge storage layer CIL, and a tunneling dielectric layer TIL that are sequentially stacked. The blocking dielectric layer BLK may be adjacent to the stack structure ST or the source structure SC, and the tunneling dielectric layer TIL may be adjacent to the vertical semiconductor pattern VSP. The charge storage layer CIL may be interposed between the blocking dielectric layer BLK and the tunneling dielectric layer TIL. The blocking dielectric layer BLK may conformally cover an inner wall of the vertical channel hole CH.

The blocking dielectric layer BLK, the charge storage layer CIL, and the tunneling dielectric layer TIL may extend in the third direction D3between the vertical semiconductor pattern VSP and the first and second gate electrodes ELa and ELb and between the vertical semiconductor pattern VSP and the first and second interlayer dielectric layers ILDa and ILDb. The data storage pattern DSP may store and/or change data by using Fowler-Nordheim tunneling induced by a voltage difference between the vertical semiconductor pattern VSP and the first and second gate electrodes ELa and ELb. For example, the blocking dielectric layer BLK and the tunneling dielectric layer TIL may include silicon oxide, and the charge storage layer CIL may include silicon nitride or silicon oxynitride.

The first source conductive pattern SCP1of the source structure SC may be in contact with the vertical semiconductor pattern VSP, and the second source conductive pattern SCP2of the source structure SC may be spaced apart from the vertical semiconductor pattern VSP across the data storage pattern DSP. The first source conductive pattern SCP1may be spaced apart from the buried dielectric pattern VI across the vertical semiconductor pattern VSP.

For example, the first source conductive pattern SCP1may include protrusions SCP1btlocated at a level higher than that of a bottom surface SCP2bof the second source conductive pattern SCP2or lower than that of a bottom surface SCP1bof the first source conductive pattern SCP1. The protrusions SCP1btmay be located at a lower level than that of a top surface SCP2aof the second source conductive pattern SCP2. The protrusions SCP1btmay each have, for example, a curved shape at a surface in contact with the data storage pattern DSP or the lower data storage pattern DSPr.

FIGS.7C and7Dillustrate enlarged view of section C depicted inFIG.6B, partially showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIGS.6B, a spacer dielectric layer221may be provided between the selection mold structure SSLM and a sidewall part of the capping through contact CTC. For example, the spacer dielectric layer221may be interposed between the sidewall part of the capping through contact CTC and each of the first, second, and third capping dielectric layers210,220, and230. An upper portion of the spacer dielectric layer221may be in contact with a lower portion of the dummy through contact DTC, and a lower portion of the spacer dielectric layer221may be in contact with an upper portion of the cell contact plug CCP or an upper portion of the peripheral contact plug TCP. The spacer dielectric layer221may have a top surface coplanar with a bottom surface of the selection semiconductor layer240. The spacer dielectric layer221may include, for example, silicon oxide.

The capping through contact CTC may have a first width W1. The first width W1may indicate a width, which is measured at an arbitrary vertical level, in the first direction D1or the second direction D2of the capping through contact CTC. The dummy through contact DTC may have a second width W2. The second width W2may indicate a width, which is measured at an arbitrary vertical level, in the first direction D1or the second direction D2of the dummy through contact DTC. The contact plug CP may have a third width W3. The third width W3may indicate a width, which is measured at an arbitrary vertical level, in the first direction D1or the second direction D2of the contact plug CP. According to some embodiments, as shown inFIG.7C, the third width W3may be greater than the first width W1, and the second width W2may be greater than the third width W3. According to some embodiments, as shown inFIG.7D, the second width W2may be less than the first width W1, and the first width W1may be less than the third width W3. On an interface between the dummy through contact DTC and the capping through contact CTC, a lateral surface of the dummy through contact DTC may not be aligned with a lateral surface of the capping through contact CTC, and may be offset in the first direction D1or the second direction D2from the lateral surface of the capping through contact CTC. For example, on the interface between the dummy through contact DTC and the capping through contact CTC, a stepped structure may be formed at the lateral surfaces of the dummy through contact DTC and the capping through contact CTC. On an interface between the dummy through contact DTC and the contact plug CP, the lateral surface of the dummy through contact DTC may not be aligned with a lateral surface of the contact plug CP, and may be offset in the first direction D1or the second direction D2from the lateral surface of the contact plug CP. For example, on the interface between the dummy through contact DTC and the contact plug CP, a stepped structure may be formed at the lateral surfaces of the dummy through contact DTC and the contact plug CP.

FIGS.8to17illustrate cross-sectional views taken along line II-II′ ofFIG.5, showing a method of fabricating a three-dimensional semiconductor memory device according to some embodiments of the present disclosure. With reference toFIGS.5,6A,6B, and8to17, the following will describe in detail a method of fabricating a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.

Referring toFIGS.5and8, a first substrate10may be provided which includes a cell array region CAR and a connection region CCR. A device isolation layer11may be formed in the first substrate10, defining an active section. The device isolation layer11may be formed by forming a trench on an upper portion of the first substrate10and filling the trench with silicon oxide.

Peripheral circuit transistors PTR may be formed on the active section defined by the device isolation layer11. Peripheral contact plugs31and peripheral circuit lines33may be formed to be connected to peripheral source/drain sections29of the peripheral circuit transistors PTR. A first dielectric layer30may be formed to cover the peripheral circuit transistors PTR, the peripheral contact plugs31, and the peripheral circuit lines33.

A second substrate100may be formed on the first dielectric layer30. The second substrate100may extend from the cell array region CAR toward the contact region CCR.

A portion of the second substrate100may be removed from the contact region CCR. The partial removal of the second substrate100may include forming a mask pattern that covers the cell array region CAR and a portion of the contact region CCR, and then using the mask pattern to pattern the second substrate100. The partial removal of the second substrate100may include forming a space where a peripheral contact plug TCP will be provided as discussed below.

A first mold structure MS1may be formed on the second substrate100. The formation of the first mold structure MS1may include sequentially stacking a first buffer dielectric layer111, a first semiconductor layer121, a second buffer dielectric layer113, and a second semiconductor layer123on the second substrate100. The first and second buffer dielectric layers111and113may be formed of, for example, silicon oxide. The first and second semiconductor layers121and123may be formed of a semiconductor material, such as silicon.

A stack structure ST may be formed on the first mold structure MS1. The stack structure ST may be formed by alternately stacking interlayer dielectric layers ILDa and ILDb and gate electrodes ELa and ELb. For example, the formation of the stack structure ST may include alternately stacking first interlayer dielectric layers ILDa and first sacrificial layers, forming first vertical channel holes CH1that penetrate the first interlayer dielectric layers ILDa and the first sacrificial layers, forming first channel sacrificial patterns that correspondingly fill the first vertical channel holes CH1, alternately stacking second interlayer dielectric layers ILDb and second sacrificial layers on an uppermost one of the first interlayer dielectric layers ILDa, forming second vertical channel holes CH2that extend through the second interlayer dielectric layers ILDb and the second sacrificial layers and are connected to the first vertical channel holes CH1, and forming second channel sacrificial patterns that correspondingly fill the second vertical channel holes CH2and are connected to the first channel sacrificial patterns. The formation of the stack structure ST may further include removing the first and second sacrificial layers in a subsequent procedure, and allowing first and second gate electrodes ELa and ELb to fill spaces from which the first and second sacrificial layers are removed. The first vertical channel holes CH1may extend through the first mold structure MS1in addition to the first interlayer dielectric layers ILDa and the first sacrificial layers, and may further extend through at least a portion of the second substrate100.

The first and second sacrificial patterns may be removed. On the cell array region CAR, vertical channel structures VS may be formed in spaces (or vertical channel holes CH) where the first and second channel sacrificial patterns are removed.

The formation of each of the vertical channel structures VS may include forming a data storage pattern DSP that conformally covers an inner wall of the vertical channel hole CH, forming a vertical semiconductor pattern VSP that conformally covers a sidewall of the data storage pattern DSP, forming a buried dielectric pattern VI that fills at least a portion of a space surrounded by the vertical semiconductor pattern VSP, and forming a conductive pad PAD that fills a space surrounded by the vertical semiconductor pattern VSP and the buried dielectric pattern VI.

A first capping dielectric layer210may be formed to cover top surfaces of the vertical channel structures VS, a top surface of an uppermost one of the second interlayer dielectric layers ILDb, a top surface of a cell contact hole CCH, which will be discussed below, and a top surface of a peripheral contact hole TCH, which will be discussed below.

A first trench TR1may be formed to extend through the first capping dielectric layer210and the stack structure ST. The first trench TR1may further extend through at least a portion of the first mold structure MS1. The first trench TR1may have a bottom surface located at a lower level than that of a bottom surface of the stack structure ST (or a bottom surface of a lowermost one of the first interlayer dielectric layers ILDa) and that of a top surface of the first mold structure MS1. For example, the bottom surface of the first trench TR1may be lower than a top surface of the first semiconductor layer121and higher than a bottom surface of the first semiconductor layer121. The first trench TR1may expose sidewalls of the first and second interlayer dielectric layers ILDa and ILDb and sidewalls of the first and second sacrificial layers. The first trench TR1may extend from the cell array region CAR toward the contact region CCR.

A preliminary spacer may be formed to partially cover inner sidewall of the first trench TR1. The preliminary spacer may cover the sidewalls of the first and second sacrificial layers, the sidewalls of the first and second interlayer dielectric layers ILDa and ILDb, and a sidewall of the second semiconductor layer123. The preliminary spacer may include a material having an etch selectivity with respect to the first and second semiconductor layers121and123and the first and second buffer dielectric layers111and113. The preliminary spacer may include, for example, silicon nitride.

The first semiconductor layer121may be selectively removed and is exposed by the first trench TR1and the preliminary spacer. The selective removal of the first semiconductor layer121may be achieved by a wet etching process that uses an etching solution. The first semiconductor layer121may be selectively removed to expose the first and second buffer dielectric layers111and113.

The first and second buffer dielectric layers111and113may be selectively removed. The selective removal of the first and second buffer dielectric layers111and113may be achieved by a wet etching process that uses an etching solution. When the first and second buffer dielectric layers111and113are selectively removed, the data storage pattern DSP of each vertical channel structure VS may be partially removed. Therefore, the vertical semiconductor pattern VSP of each vertical channel structure VS may be partially exposed.

The first and second buffer dielectric layers111and113may be removed from the cell array region CAR, while leaving the first mold structure MS1on the contact region CCR or a portion of each of the first and second buffer dielectric layers111and113provided on the contact region CCR.

A first source conductive pattern SCP1may be formed to fill a space from which the first semiconductor layer121, the first and second buffer dielectric layers111and113, and a portion of the data storage pattern DSP of each vertical channel structure VS are removed. Although not shown, an air gap may be formed in the first source conductive pattern SCP1. The second semiconductor layer123on the cell array region CAR may be called a second source conductive pattern SCP2, and as a result, a source structure SC may be formed to include the first and second source conductive patterns SCP1and SCP2.

The preliminary spacer may be removed, and this may re-expose the sidewalls of the first and second interlayer dielectric layers ILDa and ILDb and the sidewalls of the first and second sacrificial layers. The first and second sacrificial layers exposed by the first trench TR1may be selectively removed. The selective removal of the first and second sacrificial layers may be achieved by a wet etching process that uses an etching solution. The first and second gate electrodes ELa and ELb may be formed to fill spaces from which the first and second sacrificial layers are removed. After the formation of the first and second gate electrodes ELa and ELb, a separation spacer130and a separation structure150may be formed to fill the first trench TR1. The separation structure150may have a top surface substantially coplanar with that of the first capping dielectric layer210. As such, the stack structure ST may be formed to include the first and second gate electrodes ELa and ELb and the first and second interlayer dielectric layers ILDa and ILDb.

A cell contact hole CCH and a peripheral contact hole TCH in which a cell contact plug CCP and a peripheral contact plug TCP are provided may be formed to extend through the stack structure ST and a second dielectric layer170. An etching process may be employed to form the cell contact hole CCH and the peripheral contact hole TCH. A blocking layer172may be conformally formed on inner sidewalls of the cell contact hole CCH and the peripheral contact hole TCH. The blocking layer172may include, for example, silicon nitride. A plug sacrificial layer171may be formed to fill unoccupied portions of the cell contact hole CCH and the peripheral contact hole TCH. The formation of the blocking layer172and the plug sacrificial layer171may include, for example, forming the blocking layer172that conformally cover an inner surface of each of the cell contact hole CCH and the peripheral contact hole TCH, forming the plug sacrificial layer171that fills an unoccupied portion of each of the cell contact hole CCH and the peripheral contact hole TCH, and planarizing the blocking layer172and the plug sacrificial layer171until a top surface of the second dielectric layer170is exposed. The planarization may be achieved by, for example, a chemical mechanical polishing (CMP) process or an etch-back process. The blocking layer172may include, for example, silicon nitride.

A second capping dielectric layer220and a third capping dielectric layer230may be formed on the first capping dielectric layer210.

Referring toFIG.9, a capping through hole CTCH may be formed to extend through the first capping dielectric layer210, the second capping dielectric layer220, and the third capping dielectric layer230. The capping through hole CTCH may be formed to vertically overlap (e.g., in a third direction D3) with the cell contact hole CCH and the peripheral contact hole TCH. The capping through hole CTCH may be formed by an etching process.

Referring toFIG.10, a spacer dielectric layer221may be formed to conformally cover an inner sidewall and a bottom surface of the capping through hole CTCH. The spacer dielectric layer221may extend onto a top surface of the third capping dielectric layer230. The spacer dielectric layer221may be formed by using a layer-formation technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), having superior step coverage properties. The spacer dielectric layer221may include, for example, silicon oxide.

As the spacer dielectric layer221is formed and before the formation of a cell contact plug CCP and a peripheral contact plug TCP, which will be discussed below, a portion of the second capping dielectric layer220may not be etched when removing the blocking layer172formed on the inner sidewalls of the cell contact hole CCH and the peripheral contact hole TCH. Accordingly, a three-dimensional semiconductor memory device according to the present disclosure may improve in reliability and electrical properties.

Referring toFIG.11, the spacer dielectric layer221may be partially removed by an etch-back process. Therefore, the plug sacrificial layer171in the cell contact hole CCH may be exposed at its top surface. The spacer dielectric layer221that covers an inner sidewall of the capping through hole CTCH may not be removed.

Referring toFIG.12, a selection semiconductor layer240may be formed on the third capping dielectric layer230, filling an unoccupied portion of the capping through hole CTCH. The selection semiconductor layer240may extend onto the top surface of the third capping dielectric layer230.

Referring toFIG.13, a separation dielectric pattern241may be formed to extend in a first direction D1across the selection semiconductor layer240. The separation dielectric pattern241may extend along the first direction D1. During an etching process by which the separation dielectric pattern241is formed, a separation dummy pattern242may be formed simultaneously. Referring together toFIGS.5and9, the separation dummy pattern242may be formed to have an annular shape in the selection semiconductor layer240and on the capping through hole CTCH. When viewed in plan, the separation dummy pattern242may surround a portion of the selection semiconductor layer240on the capping through hole CTCH. A dielectric material may fill an inside of each of the separation dielectric pattern241and the separation dummy pattern242. The dielectric material may be formed by using a layer-formation technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), having superior step coverage properties, and may be planarized until a top surface of the selection semiconductor layer240is exposed. The planarization may be achieved by, for example, a chemical mechanical polishing (CMP) process or an etch-back process. According to the present disclosure, the separation dummy pattern242may decrease in critical dimension (CD), and thus dishing and/or erosion may be prevented while the dielectric material is planarized. As such, the present disclosure may allow a three-dimensional semiconductor memory device to have improved reliability and electrical properties. The separation dielectric pattern241and the separation dummy pattern242may be filled with, for example, silicon oxide.

Referring toFIG.14, a mold dielectric layer250may be formed on the top surface of the selection semiconductor layer240. The first capping dielectric layer210, the second capping dielectric layer220, the third capping dielectric layer230, the selection semiconductor layer240, and the mold dielectric layer250may constitute a selection mold structure SSLM.

Referring toFIG.15, on the cell array region CAR, upper vertical channel structures UVS may be formed to penetrate the selection mold structure SSLM. The formation of the upper vertical channel structures UVS may be substantially the same as the formation of the vertical channel structures VS discussed above. A third dielectric layer260may be formed to cover the mold dielectric layer250and a top surface of the upper vertical channel structure UVS.

Referring toFIG.16, a contact plug hole CPH may be formed to extend through the mold dielectric layer250and the third dielectric layer260. The contact plug hole CPH may expose the top surface of the selection semiconductor layer240between the separation dummy patterns242. A bit-line contact hole BLCH may be formed to extend through the third dielectric layer260. The bit-line contact hole BLCH may expose a conductive pad of the upper vertical channel structure UVS.

Referring toFIG.17, a portion of the selection semiconductor layer240surrounded by the separation dummy pattern242, another portion of the selection semiconductor layer240that fills the capping through hole CTCH between the spacer dielectric layers221, the plug sacrificial layer171, and the blocking layer172may be selectively removed. The selective removal may be performed by a wet etching process that uses an etching solution. It may thus be possible to expose sidewalls of the separation dummy pattern242, the spacer dielectric layer221, the first and second interlayer dielectric layers ILDa and ILDb, the first and second gate electrodes ELa and ELb, and the first dielectric pattern IP1. The spacer dielectric layer221may prevent the second capping dielectric layer220from being partially etched in the etching process, and thus it may be possible to improve reliability and electrical properties of a three-dimensional semiconductor memory device according to the present disclosure.

Referring back toFIGS.5,6A, and6B, on the cell array region CAR, bit-line contact plugs BLCP may be formed to extend through the third dielectric layer260. On the contact region CCR, contact plugs CP may be formed to extend through the third dielectric layer260and the mold dielectric layer250. On the contact region CCR, a dummy through contact DTC may be formed between the separation dummy patterns242of the selection semiconductor layer240. On the contact region CCR, a capping through contact CTC may be formed to extend through the third capping dielectric layer230, the second capping dielectric layer220, and the first capping dielectric layer210. The capping through contact CTC may be formed between the spacer dielectric layers221. On the contact region CCR, a cell contact plug CCP may be formed to extend through the second dielectric layer170, the stack structure ST, the first mold structure MS1, the second substrate100, and at least a portion of the first dielectric layer30. On the contact region CCR, a peripheral contact plug TCP may be formed to extend through the second dielectric layer170and at least a portion of the first dielectric layer30. On the third dielectric layer260, bit lines BL may be formed to be connected to the bit-line contact plugs BLCP, first conductive lines CL1may be formed to be connected to the cell contact plugs CCP, and a second conductive line CL2may be formed to be connected to the peripheral contact plug TCP.

FIG.18illustrates a plan view showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure.FIGS.19A and19Billustrate cross-sectional views respectively taken along lines III-III′ and IV-IV′ ofFIG.18, showing a three-dimensional semiconductor memory device according to some embodiments of the present disclosure. For convenience of description, omission will be made to avoid a repetitive explanation of the same components discussed with reference toFIGS.5,6A, and6B, and a difference thereof will be described in detail.

Referring toFIGS.18,19A, and19B, a first substrate10may be provided thereon with a peripheral circuit structure PS including peripheral circuit transistors PTR, peripheral contact plugs31, peripheral circuit lines33electrically connected to the peripheral circuit transistors PTR through the peripheral contact plugs31, first bonding pads35electrically connected to the peripheral circuit lines33, and a first dielectric layer30that surrounds the peripheral circuit transistors PTR, the peripheral contact plugs31, the peripheral circuit lines33, and the first bonding pads35. The first dielectric layer30may not cover top surfaces of the first bonding pads35. The first dielectric layer30may have a top surface substantially coplanar with those of the first bonding pads35.

The peripheral circuit structure PS may be provided thereon with a cell array structure CS including a bonding structure BS, a stack structure ST, a selection mold structure SSLM, and a second substrate100. The second substrate100may be provided on the stack structure ST. The stack structure ST may be provided between the second substrate100and the peripheral circuit structure PS. The bonding structure BS may be provided between the peripheral circuit structure PS and the cell array structure CS.

The bonding structure BS may include second bonding pads45on the first dielectric layer30and contact the first bonding pads35of the peripheral circuit structure PS, connection contact plugs41, connection circuit lines43electrically connected to the second bonding pads45through the connection contact plugs41, and a fourth dielectric layer40that surrounds the second bonding pads45, the connection contact plugs41, and the connection circuit lines43. The fourth dielectric layer40may include a plurality of dielectric layers that constitute a multi-layered structure. The fourth dielectric layer40may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials. The connection contact plugs41may each have a width in a first direction D1or a second direction D2that decreases in a third direction D3(or decreases with increasing distance from the first substrate10). The connection contact plugs41and the connection circuit lines43may include a conductive material, such as metal.

The fourth dielectric layer40may not cover bottom surfaces of the second bonding pads45. The fourth dielectric layer40may have a bottom surface substantially coplanar with those of the second bonding pads45. The bottom surfaces of the second bonding pads45may be correspondingly in direct contact with the top surfaces of the first bonding pads35. The first and second bonding pads35and45may include metal, such as copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), or tin (Sn). For example, the first and second bonding pads35and45may include copper (Cu). The first bonding pad35and the second bonding pad45may constitute a single unitary body (i.e., a monolithic body) with no interface therebetween. Although the first and second bonding pads35and45are illustrated to have their sidewalls aligned with each other, the present disclosure are not limited thereto, and when viewed in plan, the first and second bonding pads35and45may have their sidewalls spaced apart from each other.

The fourth dielectric layer40may be provided in its upper portion with bit lines BL and first and second conductive lines CL1and CL2in contact with the connection contact plugs41. The fourth dielectric layer40may be provided thereon with a third dielectric layer260, a mold dielectric layer250, a selection semiconductor layer240, a third capping dielectric layer230, a second capping dielectric layer220, and a first capping dielectric layer210that are sequentially stacked, and a stack structure ST and a second dielectric layer170may be provided on the first capping dielectric layer210.

First gate electrodes ELa of a first stack structure ST1and second gate electrodes ELb of a second stack structure ST2may have their lengths in a first direction D1that increase with increasing distance from the first substrate10. When viewed in plan as shown inFIG.18, the first and second gate electrodes ELa and ELb may have their sidewalls that are spaced apart from each other at a regular interval along the first direction D1. A lowermost one of the second gate electrodes ELb included in the second stack structure ST2may have a minimum length in the first direction D1, and an uppermost one of the first gate electrodes ELa included in the first stack structure ST1may have a maximum length in the first direction D1. Likewise, the first and second gate electrode ELa and ELb, first and second interlayer dielectric layers ILDa and ILDb may have their lengths in the first direction D1that increase with increasing distance from the first substrate10.

Bit-line contact plugs BLCP, contact plugs CP, capping through contacts CTC, cell contact plugs CCP, a peripheral contact plug TCP, and vertical channel structures VS may each have a width in the first direction D1or the second direction D2that decreases in the third direction D3. A separation structure150may have a width in the second direction D2that decreases in the third direction D3.

The second dielectric layer170may be provided thereon with an input/output pad IOP electrically connected through the peripheral contact plug TCP to at least one of the peripheral circuit transistors PTR included in the peripheral circuit structure PS. The input/output pad IOP may correspond to the input/output pad1101ofFIG.1or one of the input/output pads2210ofFIGS.3and4.

As the cell array structure CS is bonded to the peripheral circuit structure PS, it may be possible to increase a cell capacity per unit area of a three-dimensional semiconductor memory device according to the present disclosure. In addition, as the peripheral circuit structure PS and the cell array structure CS are manufactured separately and then bonded to each other, damage to the peripheral transistors PTR may be prevented due to various heat treatment processes, and accordingly, it may be possible to improve the reliability and electrical properties of a three-dimensional semiconductor memory device according to the present disclosure.

According to the present disclosure, a three-dimensional semiconductor memory device may include a peripheral circuit structure, a stack structure, and a selection mold structure on the stack structure. As a separation dummy pattern is formed in the selection mold structure, it may be possible to prevent deterioration in step difference due to dishing and/or erosion in a subsequent planarization procedure or a chemical mechanical polishing (CMP) process. In addition, a spacer dielectric may be additionally provided between a capping through contact and the selection mold structure, and thus it may be possible to fabricate a three-dimensional semiconductor memory device whose reliability and electrical properties are improved in a subsequent process for forming a contact plug.

Although the present disclosure has been described in connection with some embodiments of the present disclosure illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and features of the present disclosure. The above disclosed embodiments should thus be considered illustrative and not restrictive.