Integrated circuit interconnect structure having metal oxide adhesive layer

Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods are disclosed herein. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.

TECHNICAL FIELD

This disclosure relates generally to the field of integrated circuits and semiconductor manufacturing, and more specifically, to an integrated circuit interconnect structure having a metal oxide-containing adhesive layer for improved bonding of a metal layer to a dielectric layer where the dielectric material is highly filled.

BACKGROUND

The smaller scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. The scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor IC chips. IC chips are used in a variety of devices including computers, mobile phones, and consumer electronics. A plurality of IC chips can typically be formed on a single silicon wafer, i.e. a silicon disk having a diameter of, for example, 300 millimeters (mm), which is then diced apart to create individual chips or dies. IC chips can include feature sizes on the nanometer scale and can comprise hundreds of millions of components.

As integrated circuit features are scaled down and density increases, reliability of integrated circuits may be affected by a number of stresses that increase as feature size drops and density increases. These stresses include electrical, thermal, environmental, and mechanical stresses. Materials may be modified to address these stresses. For example, dielectric materials with low co-efficient of thermal expansion (CTE) and low dielectric loss may improve IC performance and reliability. However, as materials are modified, material performance may be affected in other aspects, such as when modified to improve thermal or electrical properties while worsening mechanical properties. In particular, there is a need for fabricating structures with dielectric materials having good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability) while maintaining adequate adhesion to conductive material layers.

DETAILED DESCRIPTION

Described herein are integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related apparatuses and methods. More specifically, described herein are metal oxide adhesives for improved bonding between a metal and a dielectric material containing 60% or higher amounts of filler material. For example, in some embodiments, an integrated circuit interconnect structure may include a dielectric layer having 60% or more filler, a conductive layer, and a metal oxide adhesive layer between the dielectric and conductive layers. In some embodiments, the metal oxide adhesive layer may include one or more of aluminum oxide, chromium oxide, and nickel oxide.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. Common elements in different figures may be identified with a common label.

As integrated circuit features become smaller and thinner, component stresses that lead to circuit failure, such as delamination and electromigration, may occur more readily. Delamination is understood as the separation of layers. Electromigration is understood as the transport of material due to movement of ions in a conductor. Both delamination and electromigration are examples of phenomena that reduce semiconductor reliability, lead to interconnection failure, and become relatively more prominent as feature size decreases, particularly below 50 nanometers (nm), and as power density increases. Electromigration may occur through surface, interface, grain-boundary and lattice diffusion, with strongest contributions from interface and surface diffusion. Electromigration may result in the formation of hillocks or voids within the vias and interconnects, and eventually lead to its failure.

Various approaches have been implemented in order to reduce electromigration and other stress induced failures. Current technologies attempt to fix interconnect electromigration by adding or thickening barrier layers, by adding filler material to insulating layers, which also may reduce the CTE of the material, or by adding selective metal depositions such as electro-less copper. While adding fillers to dielectric material may reduce electromigration, adhesion between the dielectric layer and conductive layer also may be reduced and delamination may be more likely to occur. Methods for improved adhesion between a dielectric layer and a metal layer in a semiconductor device, as well as materials and devices, are provided.

Electronic connections between the electronic devices (e.g., transistors) in an integrated circuit (IC) chip are created using conductive material, typically, copper metal or alloys of copper metal. Devices in an IC chip may be placed side-by-side on the surface of the IC chip or may be stacked in a plurality of layers on the IC chip. Electrical interconnections between electronic devices on the IC chip are built using vias and trenches that are filled with conductive material. Layer(s) of insulating materials, frequently, dielectric materials with low co-efficient of thermal expansion (CTE), low dielectric loss (Df), and/or low dielectric constant (low-k), separate the various components and devices in the IC chip.

As is known in the art, the term “interconnect” (also sometimes referred to as a trench, a line, or a trace) is used to describe an electrically conductive line isolated by a layer typically comprising an interlayer low-k and/or low Df dielectric material that is provided within the plane of an IC chip. Such interconnects are typically stacked into several levels with a layer of dielectric in between the metal layers. As is also known in the art, the term “via” is used to describe an electrically conductive element that electrically interconnects two or more metal trenches of different levels. Vias are provided substantially perpendicularly to the plane of an IC chip. A via may interconnect two metal trenches in adjacent levels or two metal trenches in levels that are not adjacent to one another. As is known in the art, the terms lines, trenches, and vias are commonly associated with the features that are used to form metal interconnects. As used herein, the terms “line”, “interconnect”, and “trench” may be used interchangeably.

To form electrical interconnects, dielectric layers may be patterned to create one or more trench or via openings that may be filled with metal to form interconnects. In general, a feature used to form a metal interconnect is a depression having any shape formed in a substrate or layer deposited on the substrate. The feature is filled with conducting material. The trenches or vias may be created using conventional wet or dry etch semiconductor processing techniques. Dielectric materials may be used to isolate electrically metal interconnects from the surrounding components.

In various embodiments, the conductive interconnects described herein may be used to connect various components associated with an integrated circuit. Components include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an integrated circuit may include those that are mounted on an integrated circuit or those connected to an integrated circuit. The integrated circuit may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a computer.

Implementations of the interconnect structures disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate or core. In some embodiments, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. In some embodiments, the dielectric and conductive layers may be formed on a temporary carrier in a coreless process. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device or semiconductor subcomponent, such as a package substrate, may be built falls within the spirit and scope of the present disclosure.

The one or more dielectric layers may be formed on the substrate using dielectric materials known for their applicability in integrated circuit structures, such as low-k and/or low Df dielectric materials. The dielectric layer may be deposited by any suitable process, including, for example, chemical vapor deposition (CVD), film lamination, atomic layer deposition (ALD), or spin on process, among others. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass (OSG). Typically, low-k films have a dielectric constant smaller than that of SiO2, which has a dielectric constant of about 4.0. Low-k films having dielectric constants of about 2.7 to about 3 are typical in current semiconductor fabrication processes. Typically, low Df films have a Df value of less than 0.004. The dielectric layers may include pores or air gaps to further reduce their dielectric constant.

In some embodiments, dielectric materials may include epoxies, resins, and/or other fillers, such as silica treated with a silane coupling agent, which may be formulated to reduce the dielectric constant. As the filler material percentage increases, the mechanical adhesive properties of the dielectric material may be decreased. For example, in dielectric materials having resin and filler, among other materials, as amounts of filler material increase less resin material is exposed on the surface and lower surface adhesion occurs. Metal oxide layers placed between a dielectric material, silicon, and or other materials and the copper interconnect may promote adhesion of the copper to the other material(s). In some embodiments where dielectric materials having 60% or greater filler content, decreased adhesion to the metal layer may be improved by a metal oxide adhesive layer between the metal and dielectric layers.

Embodiments described herein provide metal oxide layers of materials that act as adhesion promoters between metal structures and dielectric materials containing a high percentage of fillers. More specifically, embodiments described herein provide metal oxide layers of materials that may act as adhesion promoters between electroless copper and dielectric materials containing a high percentage of silica filler. As used herein, dielectric materials containing a high percentage of filler are dielectric materials that are about 60% or more filler. Preferably, dielectric materials have between 65% to 75% filler. Without being limiting, it may be understood that the metal oxide adhesive may form bonds with the fillers (e.g., silica) in the dielectric material, and, also, may form bonds with the metal (e.g., electroless copper). As used herein, the terms “metal oxide adhesive” or “metal oxide adhesive layer” may be used interchangeably, and may refer to an adhesive that includes a metal oxide as well other materials and/or compounds or may refer to an adhesive that is purely a metal oxide material.

A conductive layer may be one or more layers. A multi-layered conductive layer may include a thicker metal layer deposited on a thinner seed layer of metal. For example, an electroless metal seed layer and an electrolytic metal layer deposited on top of the seed layer. The metal layers may be the same metal, such as copper, or may be different metals, such as copper and nickel. A standard electroless copper seed layer is typically about 1 micron (um) thick, and requires dielectric roughening for mechanical adhesion. Surface roughness provides a mechanical anchor for overlying photoresist and/or conductive layers, but, as such, has a high etch bias. A standard sputter seed layer may be thinner, but uses an adhesion layer, such as a titanium thin film, to maintain good adhesion. However, titanium is costly and difficult to remove, and titanium etching solutions are volatile and have a short bath-life. A metal oxide adhesion layer provides a cost-effective solution that provides good surface bonding to the dielectric layer and metal layer, and that is selectively and readily removed by etching.

FIG. 1illustrates a portion of an electrical interconnect structure having a metal oxide adhesive layer. As shown inFIG. 1, dielectric layer104is deposited on top and bottom sides of substrate102to form two separate structures. Adhesive layer106lines the bottom and sides of conductive vias108and pads112, and the bottom of conductive lines110. Adhesive layer106includes a metal oxide and provides adhesion or bonding between dielectric layer104and the conductive vias108, pads112, and lines110in this embodiment. Vias108are a depression in dielectric layer104that may be formed using any suitable process, including laser drilling. Lines110and pads112may be formed using any suitable process, including patterning with photoresist material and plating with conductive material. The photoresist may be removed and any exposed metal plating and underlying adhesive may be etched.

FIGS. 2-7are cross-sectional views of an example process in various stages of forming a package substrate having a metal oxide adhesive layer, in accordance with various embodiments.FIG. 2illustrates dielectric layer104deposited on substrate102to create assembly200.

Substrate102may be made of any suitable material, such as stainless steel, glass, silicon, fiber-glass reinforced epoxy, among others. Substrate102may be temporary and may include a release layer, or may be a core that is permanently with the substrate. For example, substrate102may be a copper clad laminate core where a dielectric layer is hard pressed on the copper and thermally cured.

Dielectric layer104may be formed using any suitable process, such as lamination or slit coating and curing, and with any suitable material, such as epoxy with filler or epoxy resin with filler. Preferably, dielectric material includes silica or glass filler treated with silane coupling agents. In some embodiments, dielectric layers are formed to a thickness that will completely cover a top surface of the one or more vias to account for uneven surfaces. In some embodiments, the thickness of dielectric layers may be minimized to reduce the etching time required to expose the one or more vias in a subsequent processing operation. In various embodiments, the dielectric layer may include various epoxies, resins, and filler material that includes glass or silica, among other fillers. In various embodiments, the dielectric material may be about 60% to 90% filler. Preferably, the dielectric material is about 65% to 75% filler. Preferably, the filler material comprises silica.

FIG. 3illustrates assembly300, which is assembly300after drilling via openings302in dielectric layer104. Via openings302may be created, for example, by laser drilling dielectric layer104, which may leave behind dielectric residue304. In some embodiments, via openings302may have substantially vertical sidewalls. In some embodiments, via openings302may have angled sidewalls to form conical-shaped vias.

FIG. 4illustrates assembly400, which is assembly300after cleaning away residue304in via openings302. Via openings may be cleaned402using any suitable process, for example, a wet desmear process.

FIG. 5illustrates assembly500, which is assembly400after depositing a metal oxide adhesive layer502on dielectric layer104and via openings302. Adhesive layer106includes a metal oxide, such as, for example, aluminum oxide, chromium oxide, and nickel oxide, or a combination of these materials, among others. The metal oxide may be any suitable material that provides reliable performance of the integrated circuit. The adhesive layer may have an average thickness of between 4 nm and 40 nm. Metal oxide adhesive layer may be deposited using any suitable process, including wet coating, dry sputtering, CVD, physical vapor deposition (PVD), and ALD. Preferably, the adhesive layer is deposited by a sol gel based metal oxide dip coating. Annealing, such as, thermal, UV, or laser, may be performed at a temperature of 200 degrees Celsius or less. Annealing removes solvents to form a more densely packed metal oxide layer.

FIG. 6illustrates assembly600, which is assembly500after a first conductive material layer602is deposited. Conductive material layer602may be any type of conductive metal, including copper, nickel, or silver, preferably, copper, and may be deposited using any suitable process, including lithography or electroless plating, preferably, electroless plating.

In general, an electrodeposition process comprises the deposition of a metal onto a substrate from an electrolytic solution that comprises ions of the metal to be deposited. A negative bias is placed on the substrate. The electrolyte solution can be referred to as a plating bath or an electroplating bath. The positive ions of the metal are attracted to the negatively biased substrate. The negatively biased substrate reduces the ions and the metal deposits onto the substrate.

FIG. 7illustrates assembly700, which is assembly600after patterning of photoresist layer, depositing conductive material, removing the photoresist, and etching the exposed first conductive material layer602and underlying adhesive layer. Adhesive layer106remains between dielectric layer104and conductive features108,110,112.

Conductive vias108, lines110, and pads112may be formed using any suitable method, including lithography and/or electroless plating, and may include one or more layers. Conductive vias108and lines110may be formed from any suitable conductive material, for example, copper, aluminum (Al), gold (Au), silver (Ag) and/or alloys thereof. In some embodiments of the invention, the metal used for interconnects is copper or an alloy of copper. Preferably, conductive interconnects are copper (Cu). The conductive (or metal) layer may have an average thickness of between 20 nm and 20 um, or may be of any suitable thickness.

For one embodiment, the patterning of photoresist layer may be implemented with lithographic patterning processes (e.g., exposed with a radiation source through a routing layer mask and developed with a developer) to pattern traces and pads. As illustrated, conductive material is deposited into openings formed by the patterned photoresist layer to form conductive traces110, and pads112. In some embodiments, conductive material is deposited using an elytic copper plating. In some embodiments, conductive lines, and pads may be formed with a copper electroplating process, sputtered copper, or the like. Conductive material may be deposited only on the portions of the exposed conductive layer. Conductive vias or pillars may be formed from copper and may act as vertical interconnects between adjacent conductive layers. In some embodiments, portions of exposed conductive layer and underlying adhesive layer may be recessed with a flash etching process, a wet etch or a dry etch process.

If conductive interconnects are formed using lithography, photoresist layers may be deposited using any suitable process, such as lamination, and may be positively or negatively charged to create crosslinked and non-crosslinked portions using ultraviolet for patterning conductive material layer. Non-crosslinked portions dissolve to form openings where conductive material may be deposited.

Additional dielectric layers, adhesive layers, and conductive material layers, including vias, may be added by repeating the process as described inFIGS. 2-7. In some embodiments, a dielectric layer is deposited on top of the conductive features, and the top surface of the conductive via is subsequently revealed by a mechanical, chemical, or plasma etchback.

FIG. 8is a process flow diagram of an example method of forming an integrated circuit substrate having a metal oxide adhesive layer, in accordance with various embodiments.

At802, a first dielectric layer may be formed on a substrate. At804, vias may be formed in the first dielectric layer. At806, residue in vias may be cleaned. At808, a metal oxide adhesive layer may be deposited on first dielectric layer and via surfaces. At810. a first conductive layer may be deposited on the metal oxide adhesive layer. At812, a first photoresist layer may be deposited and patterned to expose a portion of the first conductive layer, a conductive material may be deposited on the exposed portion of the first photo resist layer to form a patterned conductive layer, and the first photoresist layer may be removed. At814, portions of the exposed first conductive layer and underlying adhesive layer may be etched.

Additional dielectric layers, metal oxide adhesive layers, and conductive layers may be formed by repeating the process as described in802through814.

An example method of forming a package substrate according to an embodiment is to hard press dielectric on a copper foil coated pre-preg carrier, such as, copper clad laminate, and then cure the dielectric using dry heat. After curing the dielectric layer, laser drill the dielectric material to form vias and to expose the copper on the carrier. Use a wet desmear process to clean away any dielectric residue created by the laser drilling. After the wet desmear process, submerge the carrier with the laser cut dielectric in a sol gel based metal oxide dip coating and then dry using dry heat, ultraviolet light, or other suitable method to remove the solvent. After drying, plate the surface with electroless copper and continue with the semi-additive process (SAP), which is known in the art, to add a patterned conductive layer. Additional dielectric layers, metal oxide adhesive layers, and conductive layers may be added by depositing another dielectric layer on the conductive layer rather than on a substrate and repeating the process.

A die may be coupled to the package substrate via first level interconnects (FLI). The package substrate may be coupled to a circuit board via second level interconnects (SLI). The package substrate may include electrical pathways to route signals or power between the FLI and the SLI, as known in the art.

FIGS. 9A-Bare top views of a wafer900and dies902that may take the form of any of the embodiments of the IC structures100disclosed herein. The wafer900may be composed of semiconductor material and may include one or more dies902having IC elements formed on a surface of the wafer900. Each of the dies902may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer900may undergo a singulation process in which each of the dies902is separated from one another to provide discrete “chips” of the semiconductor product. The die902may include one or more transistors (e.g., some of the transistors1040ofFIG. 10, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. The die902may include one or more conductive pathways. In some embodiments, the wafer900or the die902may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die902. For example, a memory array formed by multiple memory devices may be formed on a same die902as a processing device (e.g., the processing device1202ofFIG. 12) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 10is a cross-sectional side view of an IC device1000that may be used with any of the embodiments of the IC structures disclosed herein. The IC device1000may be formed on a substrate1002(e.g., the wafer900ofFIG. 9A) and may be included in a die (e.g., the die902ofFIG. 9B). In some embodiments, the substrate1002may provide the IC substrate102. The substrate1002may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate1002may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the substrate1002may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate1002. Although a few examples of materials from which the substrate1002may be formed are described here, any material that may serve as a foundation for an IC device1000may be used. The substrate1002may be part of a singulated die (e.g., the dies902ofFIG. 9B) or a wafer (e.g., the wafer900ofFIG. 9A).

The IC device1000may include one or more device layers1004disposed on the substrate1002. The device layer1004may be included in the circuitry at the device side of the die of the IC structures disclosed herein. The device layer1004may include features of one or more transistors1040(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate1002. The device layer1004may include, for example, one or more source and/or drain (S/D) regions1020, a gate1022to control current flow in the transistors1040between the S/D regions1020, and one or more S/D contacts1024to route electrical signals to/from the S/D regions1020. The transistors1040may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1040are not limited to the type and configuration depicted inFIG. 10and may include a wide variety of other types and configurations such as, for example, planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wraparound or all-around gate transistors, such as nanoribbon and nanowire transistors.

The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type work-function metal or N-type work-function metal, depending on whether the transistor1040is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work-function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

The S/D regions1020may be formed within the substrate1002adjacent to the gate1022of each transistor1040. The S/D regions1020may be formed using either an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate1002to form the S/D regions1020. An annealing process that activates the dopants and causes them to diffuse farther into the substrate1002may follow the ion-implantation process. In the latter process, the substrate1002may first be etched to form recesses at the locations of the S/D regions1020. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1020. In some implementations, the S/D regions1020may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1020may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1020.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors1040of the device layer1004through one or more interconnect layers disposed on the device layer1004(illustrated inFIG. 10as interconnect layers1006-1010), which may be any of the embodiments of the IC structures disclosed herein. For example, electrically conductive features of the device layer1004(e.g., the gate1022and the S/D contacts1024) may be electrically coupled with the interconnect structures1028of the interconnect layers1006-1010. The one or more interconnect layers1006-1010may form an interlayer dielectric (ILD) stack1019of the IC device1000. The conductive pathways1012may extend to, and electrically couple to, one or more of the interconnect layers1006-1010. The conductive pathways may route signals to/from the devices in the device layer1004, or may route signals through the interconnect layers1006-1010to/from other devices (e.g., other electronic components in a stacked IC structure, or other components sharing a circuit board with the IC device1000).

The interconnect structures1028may be arranged within the interconnect layers1006-1010to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures1028depicted inFIG. 10). Although a particular number of interconnect layers1006-1010is depicted inFIG. 10, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1028may include trench structures1028a(sometimes referred to as “lines”) and/or via structures1028b(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench structures1028amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate1002upon which the device layer1004is formed. For example, the trench structures1028amay route electrical signals in a direction in and out of the page from the perspective ofFIG. 10. The via structures1028bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate1002upon which the device layer1004is formed. In some embodiments, the via structures1028bmay electrically couple trench structures1028aof different interconnect layers1006-1010together.

The interconnect layers1006-1010may include a dielectric material1026disposed between the interconnect structures1028, as shown inFIG. 10. In some embodiments, the dielectric material1026disposed between the interconnect structures1028in different ones of the interconnect layers1006-1010may have different compositions; in other embodiments, the composition of the dielectric material1026between different interconnect layers1006-1010may be the same.

A first interconnect layer1006(referred to as Metal1or “M1”) may be formed directly on the device layer1004. In some embodiments, the first interconnect layer1006may include trench structures1028aand/or via structures1028b, as shown. The trench structures1028aof the first interconnect layer1006may be coupled with contacts (e.g., the S/D contacts1024) of the device layer1004.

A second interconnect layer1008(referred to as Metal2or “M2”) may be formed directly on the first interconnect layer1006. In some embodiments, the second interconnect layer1008may include via structures1028bto couple the trench structures1028aof the second interconnect layer1008with the trench structures1028aof the first interconnect layer1006. Although the trench structures1028aand the via structures1028bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1008) for the sake of clarity, the trench structures1028aand the via structures1028bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer1010(referred to as Metal3or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1008according to similar techniques and configurations described in connection with the second interconnect layer1008or the first interconnect layer1006.

The IC device1000may include a solder resist material1034(e.g., polyimide or similar material) and one or more bond pads1036formed on the interconnect layers1006-1010. The bond pads1036may provide the contacts to couple to the FLI, for example. The bond pads1036may be electrically coupled with the interconnect structures1028and configured to route the electrical signals of the transistor(s)1040to other external devices. For example, solder bonds may be formed on the one or more bond pads1036to mechanically and/or electrically couple a chip including the IC device1000with another component (e.g., a circuit board). The IC device1000may have other alternative configurations to route the electrical signals from the interconnect layers1006-1010than depicted in other embodiments. For example, the bond pads1036may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 11is a cross-sectional side view of an IC device assembly1100that may include any of the embodiments of the IC structures disclosed herein. The IC device assembly1100includes a number of components disposed on a circuit board1102(which may be, e.g., a motherboard). The IC device assembly1100includes components disposed on a first face1140of the circuit board1102and an opposing second face1142of the circuit board1102; generally, components may be disposed on one or both faces1140and1142.

The IC device assembly1100illustrated inFIG. 11includes a package-on-interposer structure1136coupled to the first face1140of the circuit board1102by coupling components1116. The coupling components1116may electrically and mechanically couple the package-on-interposer structure1136to the circuit board1102, and may include solder balls (as shown inFIG. 11), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1136may include an electronics package1120coupled to an interposer1104by coupling components1118. The coupling components1118may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1116. Although a single electronics package1120is shown inFIG. 11, multiple electronics packages may be coupled to the interposer1104; indeed, additional interposers may be coupled to the interposer1104. The interposer1104may provide an intervening substrate used to bridge the circuit board1102and the electronics package1120. The electronics package1120may be or include, for example, a die (the die902ofFIG. 9B), an IC device (e.g., the IC device1000ofFIG. 10), or any other suitable component. Generally, the interposer1104may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1104may couple the electronics package1120(e.g., a die) to a ball grid array (BGA) of the coupling components1116for coupling to the circuit board1102. In the embodiment illustrated inFIG. 11, the electronics package1120and the circuit board1102are attached to opposing sides of the interposer1104; in other embodiments, the electronics package1120and the circuit board1102may be attached to a same side of the interposer1104. In some embodiments, three or more components may be interconnected by way of the interposer1104. In some embodiments, the electronics package1120may include an IC structure disclosed herein. An additional electronic component may be disposed on the electronics package1120to form a stacked IC structure.

The IC device assembly1100may include an electronics package1124coupled to the first face1140of the circuit board1102by coupling components1122. The coupling components1122may take the form of any of the embodiments discussed above with reference to the coupling components1116, and the electronics package1124may take the form of any of the embodiments discussed above with reference to the electronics package1120. In some embodiments, the electronics package1124may include any IC structure disclosed herein. An additional electronic component may be disposed on the electronics package1124to form a stacked IC structure.

The IC device assembly1100illustrated inFIG. 11includes a package-on-package structure1134coupled to the second face1142of the circuit board1102by coupling components1128. The package-on-package structure1134may include an electronics package1126and an electronics package1132coupled together by coupling components1130such that the electronics package1126is disposed between the circuit board1102and the electronics package1132. The package-on-package structure1134may take the form of an IC structure disclosed herein. The coupling components1128and1130may take the form of any of the embodiments of the coupling components1116discussed above, and the electronics packages1126and1132may take the form of any of the embodiments of the electronics package1120discussed above.

FIG. 12is a block diagram of an example computing device1200that may include one or more of any of the embodiments of the IC structures disclosed herein. A number of components are illustrated inFIG. 12as included in the computing device1200, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device1200may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device1200may not include one or more of the components illustrated inFIG. 12, but the computing device1200may include interface circuitry for coupling to the one or more components. For example, the computing device1200may not include a display device1206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1206may be coupled. In another set of examples, the computing device1200may not include an audio input device1224or an audio output device1208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1224or audio output device1208may be coupled.

In some embodiments, the communication chip1212may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip1212may include multiple communication chips. For instance, a first communication chip1212may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip1212may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip1212may be dedicated to wireless communications, and a second communication chip1212may be dedicated to wired communications.

The computing device1200may include battery/power circuitry1214. The battery/power circuitry1214may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device1200to an energy source separate from the computing device1200(e.g., AC line power).

The computing device1200may include a display device1206(or corresponding interface circuitry, as discussed above). The display device1206may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device1200may include an audio output device1208(or corresponding interface circuitry, as discussed above). The audio output device1208may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device1200may include an audio input device1224(or corresponding interface circuitry, as discussed above). The audio input device1224may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device1200may include a global positioning system (GPS) device1218(or corresponding interface circuitry, as discussed above). The GPS device1218may be in communication with a satellite-based system and may receive a location of the computing device1200, as known in the art.

The computing device1200may include an other output device1210(or corresponding interface circuitry, as discussed above). Examples of the other output device1210may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device1200may include an other input device1220(or corresponding interface circuitry, as discussed above). Examples of the other input device1220may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

Some Examples in accordance with various embodiments of the present disclosure are now described.

Example 1 is an integrated circuit interconnect structure including: a dielectric layer, wherein the dielectric layer comprises 60% or more filler; a conductive layer; and a metal oxide adhesive layer, wherein the metal oxide adhesive layer is between the dielectric layer and the conductive layer.

Example 2 may include the subject matter of Example 1, and may further specify that the metal oxide adhesive layer comprises one or more of aluminum oxide, chromium oxide, and nickel oxide.

Example 3 may include the subject matter of any of Examples 1-2, and may further specify that a thickness of the metal oxide adhesive layer is between 4 nanometers and 40 nanometers.

Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the dielectric layer material comprises between 65% and 75% filler.

Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the dielectric layer filler material comprises silica.

Example 6 may include the subject matter of Example 5, and may further specify that the silica filler material comprises silica treated with a silane coupling agent.

Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the dielectric layer comprises one or more of epoxy and resin.

Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the conductive layer comprises one or more layers, and wherein one of the one or more layers is an electroless copper seed layer.

Example 9 may include the subject matter of any of Examples 1-8, and may further include a via, wherein the metal oxide adhesive layer is formed within the via.

Example 10 is a method of manufacturing an integrated circuit interconnect structure, including: forming a first dielectric layer on a substrate; forming a via in the first dielectric layer; cleaning via formation residue from the via; depositing a first metal oxide adhesive layer on the first dielectric layer including the via; depositing a first conductive layer on the metal oxide adhesive layer; patterning and depositing a second conductive layer on the first conductive layer; and etching the exposed first conductive layer and the underlying first metal oxide adhesive layer.

Example 11 may include the subject matter of Example 10, and may further specify that the substrate is a copper clad laminate.

Example 12 may include the subject matter of any of Examples 10-11, and may further specify that the via is formed by laser drilling.

Example 13 may include the subject matter of any of Examples 10-12, and may further specify that the metal oxide adhesive layer is deposited by sol gel based metal oxide dip coating.

Example 14 may include the subject matter of Example 13, and may further specify that depositing the metal oxide adhesive layer further comprises annealing at a temperature at or below 200 degrees Celsius.

Example 15 may include the subject matter of any of Examples 10-14, and may further specify that the metal oxide adhesive layer comprises one or more of aluminum oxide, chromium oxide, and nickel oxide.

Example 16 may include the subject matter of any of Examples 10-15, and may further specify that the first conductive layer comprises copper deposited by electroless plating.

Example 17 may include the subject matter of any of Examples 10-16, and may further specify that the via formation residue is cleaned by a wet desmear process.

Example 18 may include the subject matter of any of Examples 10-17, and may further specify that the first conductive layer and the underlying first metal oxide adhesive layer are etched by a chemical etch.

Example 19 may include the subject matter of Example 10, and may further include: forming a second dielectric layer on the first dielectric layer and the second conductive layer; forming a via in the second dielectric layer; cleaning via formation residue from the via; depositing a second metal oxide adhesive layer on the second dielectric layer including the via; depositing a third conductive layer on the metal oxide adhesive layer; patterning and depositing a fourth conductive layer on the third conductive layer; and etching the exposed third conductive layer and the underlying second metal oxide adhesive layer.

Example 20 is an integrated circuit package including: a die; first level interconnects; second level interconnects; and a package substrate including: a dielectric layer, wherein the dielectric layer comprises 60% or more filler; a conductive layer; and a metal oxide adhesive layer, wherein the metal oxide adhesive layer is between the dielectric layer and the conductive layer.

Example 21 may include the subject matter of Example 20, and may further specify that the metal oxide adhesive layer comprises one or more of aluminum oxide, chromium oxide, and nickel oxide.

Example 22 may include the subject matter of any of Examples 20-21, and may further specify that a thickness of the metal oxide adhesive layer is between 4 nanometers and 40 nanometers.

Example 23 may include the subject matter of any of Examples 20-22, and may further specify that the dielectric layer material comprises between 65% and 75% filler.

Example 24 may include the subject matter of any of Examples 20-23, and may further specify that the dielectric layer filler material comprises silica.

Example 25 may include the subject matter of Example 24, and may further specify that the silica filler material comprises silica treated with a silane coupling agent.

Example 26 may include the subject matter of any of Examples 20-25, and may further specify that the conductive layer comprises one or more layers, and wherein one of the one or more layers is an electroless copper seed layer.

Example 27 is a computing device, including: a circuit board; and an IC package coupled to the circuit board, wherein the IC package includes: a die; first level interconnects; second level interconnects; and a package substrate including: a dielectric layer, wherein the dielectric layer comprises 60% or more filler; a conductive layer; and a metal oxide adhesive layer, wherein the metal oxide adhesive layer is between the dielectric layer and the conductive layer.

Example 28 may include the subject matter of Example 27, and may further specify that the metal oxide adhesive layer comprises one or more of aluminum oxide, chromium oxide, and nickel oxide.

Example 29 may include the subject matter of any of Examples 27-28, and may further specify that a thickness of the metal oxide adhesive layer is between 4 nanometers and 40 nanometers.

Example 30 may include the subject matter of any of Examples 27-29, and may further specify that the dielectric layer material comprises between 65% and 75% filler.

Example 31 may include the subject matter of any of Examples 27-30, and may further specify that the dielectric layer filler material comprises silica.

Example 32 may include the subject matter of Example 31, and may further specify that the silica filler material comprises silica treated with a silane coupling agent.

Example 33 may include the subject matter of any of Examples 27-32, and may further specify that the conductive layer comprises one or more layers, and wherein one of the one or more layers is an electroless copper seed layer.