Image drawing apparatus

In an image drawing apparatus for conducting a data transfer at a bit unit for image data stored in a memory device, a region storing part stores a region where at least one attribute value concerning a pixel is not constant in the image data, an attribute value storing value stores each attribute value of pixels in the region, a constant value storing part stores a constant value as the attribute value, an inside region determining part determines whether or not a coordinate being transferred is within the region, and a selection signal generating part selects one of the attribute value storing part as a selected storing part and the constant value storing part based on a determination result obtained by the inside region determining part, and generating a selection signal indicating the selected storing part, wherein a predetermined process for source image data is conducted by obtaining the attribute value from the selected storing part.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority of Japanese Patent Application No. 2004-321008 filed on Nov. 4, 2004, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to image drawing apparatuses for conducting a data transfer by a bit unit with respect to image data being stored in an arbitrary rectangle region in a memory device, and more particularly to an image drawing apparatus that can transfer an image including both a portion where a transmission coefficient is constant and a portion where the transmission coefficient is not constant by one data transfer.

2. Description of the Related Art

Japanese Laid-open Patent Applications No. 7-74927 and No. 9-212410 disclose image drawing apparatuses in that when a data transfer function (hereinafter, called a BITBLT transfer) by a bit unit is conducted with respect to image data stored in an arbitrary block region (or rectangle region) of a memory device, transmission coefficient data (or pixel value) are set in a register when the transmission coefficient data (pixel value) are constant, the transmission coefficient data are read out, and then a transmission drawing process is conducted based on the transmission coefficient data.

Japanese Laid-open Application No. 2003-157433 discloses an image drawing apparatus in that all transmission coefficient data (all pixel values) for the image data are stored in the memory device when the transmission coefficient data (pixel value) are different for each pixel, and the transmission coefficient data are read out for each pixel.

Alternatively, when the transmission coefficient data (pixel value) are given as a function between pixels, a value (memory reference value) stored in the memory device or a value given by a function in a register is read out.

In the above-described conventional image drawing apparatuses, only one of the above three functions is available for a single BITBLT transfer. Accordingly, in a case of a typical icon image as shown inFIG. 1A, even if the transmission coefficient is constant on a periphery of an arrow image, it is required to store transmission coefficients for all pixels in the memory device, and read out a respective transmission coefficient for each pixel. In this case, a larger amount of area blocks of the memory device is unnecessarily used.

On the other hand, as shown inFIG. 1B, it is considered that the icon image is divided into portions where the transmission coefficient is constant and a portion where the transmission coefficient is not constant. In this case, it is required to divide into five rectangle regions and conduct the BITBLT transfer five times. Accordingly, a data amount to transfer becomes larger.

That is, when the BITBLT transfer is conducted with respect to an image including both a portion where the transmission coefficient is constant and a portion where the transmission coefficient is not constant in the image, it is required to store the transmission coefficients for all pixels in the memory device or to divide the rectangle area of the image into a plurality of rectangle regions and conduct the BITBLT transfer for each divided rectangle regions. Accordingly, a larger area used to store the transmission coefficients in the memory device is needed and a larger amount of data to is transferred. In addition, a plurality of the BITBLT transfers makes it complicated.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide an image drawing apparatus in which the above-mentioned problems are eliminated.

A more specific object of the present invention is to provide an image drawing apparatus that can transfer an image including both a portion where a transmission coefficient is constant and a portion where the transmission coefficient is not constant by using one data transfer.

The above objects of the present invention are achieved by an image drawing apparatus for conducting a data transfer at a bit unit for image data stored in a memory device, including: a region storing part storing a region where at least one attribute value concerning a pixel is not constant in the image data; an attribute value storing part storing each attribute value of pixels in the region; a constant value storing part storing a constant value as the attribute value; an inside region determining part determining whether or not a coordinate being transferred is within the region; and a selection signal generating part selecting one of the attribute value storing part as a selected storing part and the constant value storing part based on a determination result obtained by the inside region determining part, and generating a selection signal indicating the selected storing part, wherein a predetermined process for source image data is conducted by obtaining the attribute value from the selected storing part.

According to the above invention, it is possible to conduct a data transfer (BITBLT transfer) for the image data including a portion where the transmission coefficient as the attribute value is constant and a portion where the transmission coefficient as the attribute value is not constant during a single process of the data transfer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A mechanism for conducting a BITBLT transfer (Bit Block Transfer) at higher speed with respect to an image created by a bitmap will be described.

FIG. 2is a diagram explaining for a method for executing the BITBLT transfer in an image drawing apparatus according to an embodiment of the present invention. InFIG. 2, an image7showing a right pointing arrow used as an icon is illustrated, but the present invention is not limited to the image7showing the right pointing arrow. The image7is created by using the bitmap.

In the image7shown inFIG. 2, an inner rectangle7bincluding a inner portion where a transmission coefficient is not constant is a rectangle a coordinate of which upper left corner is (XMIN, YMAX) and a coordinate of which lower right corner is (XMAX, YMIN). For example, these two coordinates are set in predetermined registers, respectively, by a host such as software or a like positioned at an upper device.

By using a circuit configuration for determining whether or not coordinates of source image data is located within an inner region8bbeing an inner region of the inner rectangle7bthat is defined by these two coordinates (XMIN, YMAX) and (XMAX, YMIN), when it is determined that the coordinates of the source image data are located within an outer region8abeing a region between an outer rectangle7aand the inner rectangle7bin that the region shows that the transmission coefficient is constant, the BITBLT transfer is conducted with respect to the source image data at a predetermined transfer coefficient. On the other hand, when it is determined that the coordinates of the source image data are located within the inner region8b,the BITBLT transfer is conducted with respect to the image data in accordance with the transmission coefficient.

Since the BITBLT transfer is conducted for two regions only: the outer region8awhere the transmission coefficient is constant and the inner region8bwhere the transmission coefficient is not constant, it is possible to simplify the BITBLT transfer and to improve a speed of the BITBLT transfer to be higher.

A basic circuit configuration for realizing the method for conducting the BITBLT transfer described above with reference toFIG. 2will be described as a first circuit configuration with reference toFIG. 3.FIG. 3is a block diagram showing the first circuit configuration according to the embodiment of the present invention.

InFIG. 3, an image drawing apparatus100is an apparatus controlled by a CPU (Central Processing Unit) and includes an image drawing function using the bitmap, and includes a host10, an XMAX storage register11a,an XMIN storage register11b, a YMAX storage register21a, a YMIN storage register21b, an X coordinate comparator15, a Y coordinate comparator25, an AND circuit27, a selection signal generating unit30, a transmission coefficient data reading unit41a, a source image data reading unit41b, a destination image data reading unit41c, a transmission coefficient data address generating unit42a, a source image data address generating unit42b, a destination image data address generating unit42c, a transmission coefficient data buffer43a, a source image data buffer43b, a destination image data buffer43c, a memory device (main memory)50, a constant register51, a function operating unit52, selectors55a,55b, and55c, and a transmission drawing processing control unit60.

The host10is the upper device such as software (for example, an operating system) for controlling the entire image drawing apparatus100.

The XMAX storage register11ais a register for storing a value of the XMAX of the X coordinate concerning two coordinates described inFIG. 2in that the two coordinates are set by the host10. The XMIN storage register11bis a register for storing a value of the XMIN of the X coordinate concerning two coordinates described inFIG. 2in that the two coordinates are set by the host10. The YMAX storage register21ais a register for storing a value of the YMAX of the Y coordinate concerning two coordinates described inFIG. 2in that the two coordinates are set by the host10. The YMIN storage register21bis a register for storing a value of the YMIN of the Y coordinate concerning two coordinates described inFIG. 2in that the two coordinates are set by the host10.

The X coordinate comparator15is a comparator for comparing the X coordinate in the image7with XMIN and XMAX. When XMIN<X<XMAX, it is determined as “true”. On the other hand, when X≦XMIN or XMAX≦X, it is determined as “false”. The Y coordinate comparator25is a comparator for comparing the Y coordinate in the image7with YMIN and YMAX. When YMIN<Y<YMAX, it is determined as “true”. On the other hand, when Y≦YMIN or YMAX≦Y, it is determined as “false”.

The AND circuit27conducts a logic operation AND for a comparison result of the X coordinate comparator15and a comparison result of the Y coordinate comparator25, and sends out a value showing whether or not a coordinate in the image7is within the outer region8aor the inner region8b, to the selection signal generating unit30. For example, a value showing “0” (zero) is sent out to the selection signal generating unit30when the coordinate is within the outer region8a, and a value showing “1” is sent out to the selection signal generating unit30when the coordinate is within the outer region8b.

The selection signal generating unit30determines a means to obtain the transmission coefficient and generates a selection signal. The selection signal generating unit30includes a selection register31for storing data showing the means to obtain the transmission coefficient, which is informed from the host10to select. As the means to obtain the transmission coefficient, any one of the memory device50, the constant register51, and the function operating unit52is selected. When the coordinate of source image data is within the outer region8aor the inner region8b, a respective means is selected to read out the transmission coefficient. The selection signal generated by the selection signal generating unit30is a signal specifying the means to obtain the transmission coefficient corresponding to the outer region8aor the inner region8b. The selection signal is sent to the transmission coefficient data address generating unit42a, the source image data address generating unit42b, the destination image data address generating unit42c, and the selectors55a,55b, and55c.

The transmission coefficient data reading unit41asends out a signal showing a transmission coefficient data read request to the transmission coefficient data address generating unit42aand the transmission coefficient data buffer43a, and stores the transmission coefficient data obtained from one of the memory device50, the constant register51, and the function operating unit52, to the transmission coefficient data buffer43a.

In response to the signal showing the transmission coefficient data read request from the transmission coefficient data reading unit41a, when the selection signal received from the selection signal generating unit30indicates the memory device50, that is, when an arbitrary block region (or rectangle region) of the memory device50is indicated as the transmission coefficient data, the transmission coefficient data address generating unit42areads location information showing a starting point of the block region and information showing a width in a longitudinal direction and a length in a lateral direction. The transmission coefficient data address generating unit42acalculates an address of the transmission coefficient data corresponding to the block region, and sends out an address signal showing a read address with respect to the memory device50. In response to the address signal, the transmission coefficient data stored at the read address are read out from the memory device50, and are stored into the transmission coefficient data buffer43a.

The source image data reading unit41bscans the image7being rectangular while sequentially changing the X coordinate and the Y coordinate to transfer, and sends a signal showing the X coordinate and the Y coordinate being transferred to the X coordinate comparator15and the Y coordinate comparator25. Simultaneously, the source image data reading unit41bsends out a signal showing a source image data read request to the source image data address generating unit42band the destination image data buffer43b. Then the source image data reading unit41bstores the source image data obtained from one of the memory device50, the constant register51, and the function operating unit52to the source image data buffer43b.

In response to the signal showing the source image data read request from the source image data reading unit41b, when the selection signal received from the selection signal generating unit30indicates the memory device50, that is, when an arbitrary block region of the memory device50indicates the source image data, the source image data address generating unit42breceives location information showing a starting point of the block region and information showing a width in a longitudinal direction and a length in a lateral direction. The source image data address generating unit42bcalculates an address of the source image data corresponding to the block region, and sends out an address signal showing a read address with respect to the memory device50. In response to the address signal, the source image data stored at the read address are read out from the memory device50, and are stored into the source image data buffer43b.

The destination image data reading unit41csends out a signal showing a source image data read request to the destination image data address generating unit42cand the destination image data buffer43b, and stores the source image data obtained from one of the memory device50, the constant register51, and the function operating unit52to the destination image data buffer43c.

In response to the signal showing the destination image data read request from the destination image data reading unit41c, when the selection signal received from the selection signal generating unit30indicates the memory device50, that is, when an arbitrary block region of the memory device50is indicated as the destination image data, the destination image data address generating unit42creceives location information showing a starting point of the block region and information showing a width in a longitudinal direction and a length in a lateral direction. The destination image data address generating unit42ccalculates an address of the source image data corresponding to the block region, and sends out an address signal showing a read address with respect to the memory device50. In response to the address signal, the destination image data stored at the read address are read out from the memory device50, and are stored into the destination image data buffer43c.

The memory device50is a main memory. In a case in that an arbitrary block region of the memory device50is indicated as the transmission coefficient data, a transmission coefficient corresponding to each pixel of the image7is stored into the block region. Moreover, in a case in that an arbitrary block region of the memory device50is indicated as the source image data, each pixel value of the image7is stored as the source image data in the block region. Furthermore, in a case in that an arbitrary block region of the memory device50is indicated as the destination image data, each pixel value of the image7being a destination image is stored as the destination image data. In the embodiment, each pixel value is referred from the memory device50.

In the constant register51, a value for the outer region8ahaving a constant transmission coefficient is set as a constant value.

The function operating unit52is an operating unit that calculates the transmission coefficient at the coordinate being transferred by using a function. For example, the function operating unit52is used to create a gradation.

When the memory device50is indicated by the selection signal received from the selection signal generating unit30, the selector55asends the transmission coefficient data received from the memory device50to the transmission coefficient data buffer43a. Similarly, when the selection signal indicates the constant register51, the selector55asends a constant value received from the constant register51to the transmission coefficient data buffer43a. Moreover, when the selection signal indicates the function operating unit52, the selector55asends a value received from the function operating unit52to the transmission coefficient data buffer43a. Similarly, the selector55bsends data from the means indicated by the selection signal to obtain the transmission coefficient to the source image data buffer43b. Moreover, the selector55csends data from the means indicated by the selection signal to obtain the transmission coefficient to the destination image data buffer43c.

The transmission drawing processing control unit60nearly simultaneously receives the transmission coefficient data, the source image data, and the destination image data from the transmission coefficient data buffer43a, the source image data buffer43b, and the destination image data buffer43c, respectively. The transmission drawing processing control unit60executes transmission drawing process by using the transmission coefficient data, and generates image data as an execution result. The image data generated as the execution result are stored in a predetermined storage area (for example, memory device50).

As described above, in the image drawing apparatus100according to the present invention, with respect to the image7including the inner region8bwhere the transmission coefficient is not constant, the inner region8bis determined. Therefore, a single BITBLT transfer can transfer the entire image7. In addition, it is possible to reduce a used area in the memory device50and a transmission amount.

As described above, in the embodiment, the outer region8aand the inner region8bare defined based on a determination whether or not the transmission coefficient in the image7is constant. However, a region where only the transmission coefficient is not constant, a region where only the pixel value is not constant, and a region where the transmission coefficient or the pixel value is not constant may be set based on a determination conducted by the host10. In each case, it is possible to realize the BITBLT transfer at higher speed by applying the first circuit configuration. Similarly, in the following other circuit configuration, which will be described, the BITBLT transfer can be realized at higher speed.

Next, a case of neglecting a range of the X coordinate informed from the host10will be described with reference toFIG. 4.FIG. 4is a block diagram showing a second circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 4, elements that are the same as the ones inFIG. 3are indicated by the same reference numerals and the explanation thereof will be omitted. The image drawing apparatus100shown inFIG. 4includes an X range neglection setting unit71a, and an OR circuit26ain addition to the first circuit configuration shown inFIG. 3.

The X range neglection setting unit71ais a register used to store a value informed from the host10. The host10sets the value so that the X coordinate being transferred always becomes within a range (that is, XMAX>X>XMIN), regardless of the comparison result of the X coordinate comparator15. For example, the host10sets a value “1” into the X range neglection setting unit71a, so that the X coordinate being transferred always becomes within the range, regardless of the comparison result of the X coordinate comparator15. On the other hand, the host10sets a value “0” (zero) into the X range neglection setting unit71a, when the comparison result showing whether or not the X coordinate being transferred is available.

The OR circuit26ais provided between the X coordinate comparator15and the AND circuit27. The OR circuit26aconducts a logical addition with respect to the comparison result output from the X coordinate comparator15and a value input from the X range neglection setting unit71a. Then, the OR circuit26asends a logic operation result to the AND circuit27.

The AND circuit27conducts a logical product with respect to a value input from the OR circuit26aand the comparison result of the Y coordinate comparator25. The AND circuit27outputs a value showing whether or not the coordinate in the image7is within the outer region8aor the inner region8bto the selection signal generating unit30. For example, a value “0” (zero) is output from the AND circuit27when the Y coordinate is within the outer region8a, and a value “1” is output from the AND circuit27when the Y coordinate is within the inner region8b.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

Next, a case of neglecting a range of the Y coordinate informed from the host10will be described with reference toFIG. 5.FIG. 5is a block diagram showing a third circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 5, elements that are the same as the ones inFIG. 3are indicated by the same reference numerals and the explanation thereof will be omitted. The image drawing apparatus100shown inFIG. 5includes a Y range neglection setting unit72b, and an OR circuit26bin addition to the first circuit configuration shown inFIG. 3.

The Y range neglection setting unit72bis a register used to store a value informed from the host10. The host10sets the value so that the Y coordinate being transferred always becomes within a range (that is, YMAX>Y>YMIN), regardless of the comparison result of the Y coordinate comparator25. For example, the host10sets a value “1” into the Y range neglection setting unit72b, so that the Y coordinate being transferred always becomes within the range, regardless of the comparison result of the Y coordinate comparator25. On the other hand, the host10sets a value “0” (zero) into the Y range neglection setting unit72b, when the comparison result showing whether or not the Y coordinate being transferred is available.

The OR circuit26bis provided between the Y coordinate comparator25and the AND circuit27. The OR circuit26bconducts a logical addition with respect to the comparison result output from the Y coordinate comparator25and a value input from the Y range neglection setting unit72b. Then, the OR circuit26bsends a logic operation result to the AND circuit27.

The AND circuit27conducts the logical product with respect to a value input from the OR circuit26band the comparison result of the X coordinate comparator15. The AND circuit27outputs a value showing whether or not the coordinate in the image7is within the outer region8aor the inner region8bto the selection signal generating unit30. For example, a value “0” (zero) is output from the AND circuit27when the X coordinate is within the outer region8a, and a value “1” is output from the AND circuit27when the X coordinate is within the inner region8b.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

Next, a case of inversing the transmission coefficient of the outer region8aand the transmission coefficient of the inner region8bwill be described with reference toFIG. 6.FIG. 6is a block diagram showing a fourth circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 6, elements that are the same as the ones inFIG. 3are indicated by the same reference numerals and the explanation thereof will be omitted. The image drawing apparatus100shown inFIG. 6includes an inside-outside inversion switching unit73, and an EXOR circuit28in addition to the first circuit configuration shown inFIG. 3.

The inside-outside inversion switching unit73is a register used to store a value informed from the host10. The host10sets the value so that the X coordinate and the Y coordinate in the outer region8aand being transferred are inverted to be within the inner region8bor so that the X coordinate and the Y coordinate in the inner region8band being transferred are inverted to be within the outer region8a. For example, the host10sets a value “1”, so that the above-described inversion is conducted. On the other hand, the host10sets a value “0” (zero), so that the above-described inversion is not conducted.

The EXOR circuit28is provided between the AND circuit27and the selection signal generating unit30. The EXOR circuit28operates an exclusive OR with respect to a value output from the AND circuit27and a value input from the inside-outside inversion switching unit73. Then, the EXOR circuit28sends a logic operation result to the selection signal generating unit30.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

In the fourth circuit configuration, when the X coordinate and the Y coordinate being transferred are within respective ranges, a constant transmission coefficient for the outer region8ais applied. On the other hand, when either one of the X coordinate and the Y coordinate being transferred are out of the respective range, a transmission coefficient, which is not constant is applied.

Next, a case in that both the X coordinate and the Y coordinate being transferred are out of the respective ranges will be described with reference toFIG. 7.FIG. 7is a block diagram showing a fifth circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 7, elements that are the same as the ones inFIG. 3are indicated by the same reference numerals and the explanation thereof will be omitted. The image drawing apparatus100shown inFIG. 7includes an outside range setting unit74a, an inverter circuit29a, and an AND circuit29bin addition to the first circuit configuration shown inFIG. 3.

The outside range setting unit74ais a register used to store a value informed from the host10. The host10sets the value so that the X coordinate and the Y coordinate being transferred are always out of the respective ranges, regardless of the comparison result of the X coordinate comparator15and the comparison result of the Y coordinate comparator25. For example, the host10sets a value “1”, so that both the X coordinate and the Y coordinate being transferred always become out of the respective ranges. On the other hand, the host10sets a value “0” (zero), so that the comparison result of the X coordinate comparator15and the comparison result of the Y coordinate comparator25become available.

The inverter circuit29ais provided between the outside range setting unit74aand the AND circuit29b. The inverter circuit29ainverts a value input from the outside range setting unit74aand outputs the value to the AND circuit29b. For example, when the host10sets a value “1”, a value “0” (zero) is output to the AND circuit29b. On the other hand, the host10sets a value “0” (zero) a value “1” is output to the AND circuit29b.

The AND circuit29bis provided between the AND circuit27and the selection signal generating unit30. The AND circuit29bconducts a logical addition with respect to a value input from the AND circuit27and a value input from the outside range setting unit74a. Then, the AND circuit29bsends a logic operation result to the selection signal generating unit30.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

In the fifth circuit configuration, even if the X coordinate and the Y coordinate being transferred are within the respective ranges, the constant transmission coefficient for the outer region8ais applied.

Next, a case in that both the X coordinate and the Y coordinate being transferred are within the range informed from the host10will be described with reference toFIG. 8.FIG. 8is a block diagram showing a sixth circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 8, elements that are the same as the ones inFIG. 3are indicated by the same reference numerals and the explanation thereof will be omitted. The image drawing apparatus100shown inFIG. 8includes an inside range setting unit74b, and an AND circuit29cin addition to the first circuit configuration shown inFIG. 3.

The inside range setting unit74bis a register used to store a value informed from the host10. The host10sets the value so that the X coordinate and the Y coordinate being transferred are always within the respective ranges, regardless of the comparison result of the X coordinate comparator15and the comparison result of the Y coordinate comparator25. For example, the host10sets a value “1”, so that both the X coordinate and the Y coordinate being transferred always become within the respective ranges. On the other hand, the host10sets a value “0” (zero), so that the comparison result of the X coordinate comparator15and the comparison result of the Y coordinate comparator25become available.

The AND circuit29cis provided between the AND circuit27and the selection signal generating unit30. The AND circuit29cconducts a logical addition with respect to a value input from the AND circuit27and a value input from the inside range setting unit74b. Then, the AND circuit29csends a logic operation result to the selection signal generating unit30.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

In the sixth circuit configuration, even if the X coordinate and the Y coordinate being transferred are out of the respective ranges, the transmission coefficient for the inner region8b, which is not constant, is applied.

Next, a process conducted in the selection signal generating unit30will be described with reference toFIG. 9AandFIG. 9B.FIG. 9AandFIG. 9Bare diagrams for explaining the process conducted in the selection signal generating unit according to the embodiment of the present invention. InFIG. 9AandFIG. 9B, the selection signal generating unit30stores a four bit value informed from the host10into the selection register31. The selection signal generating unit30determines a value as a reference in response to an input signal showing “inside” (inner region8b) or “outside” (outer region8a) and sends an output signal as the selection signal.

For example, the input signal shows a value “1” to indicate “inside” and a value “0” to indicate “outside”.

For example, the output signal indicates the means to obtain data by using two bits. A value “00” is indicated to refer a value stored in the memory device50(memory reference value), a value “01” is indicated to refer a value stored in the constant register51(register value) , and a value “10” is indicated to refer a value stored in the function operating unit52(function value).

The four bit value is set by the host10indicates a value to refer as follows:

A four bit value “0000” indicates to use the memory reference value when the input signal indicates “inside”, and to use the memory reference value when the input signal indicates “outside”.

A four bit value “0001” indicates to use the memory reference value when the input signal indicates “inside”, and to use the register value when the input signal indicates “outside”.

A four bit value “0010” indicates to use the memory reference value when the input signal indicates “inside”, and to use the function value when the input signal indicates “outside”.

A four bit value “0011” indicates to use the register value when the input signal indicates “inside” (that is, the coordinate being transferred is in the inner region8b), and to use the memory reference value when the input signal indicates “outside” (that is, the coordinate being transferred is in the outer region8a).

A four bit value “0100” indicates to use the register value when the input signal indicates “inside”, and to use the register value when the input signal indicates “outside”.

A four bit value “0101” indicates to use the register value when the input signal indicates “inside”, and to use the function value when the input signal indicates “outside”.

A four bit value “0110” indicates to use the function value when the input signal indicates “inside”, and to use the memory reference value when the input signal indicates “outside”.

A four bit value “0111” indicates to use the function value when the input signal indicates “inside”, and to use the register value when the input signal indicates “outside”.

A four bit value “1000” indicates to use the function value when the input signal indicates “inside”, and to use the function value when the input signal indicates “outside”.

A case in that the four bit value “0001” is set into the selection register31by the host10will be described with reference toFIG. 9A. InFIG. 9A, the selection signal generating unit30outputs the output signal (out_signal) showing the two bit value “00” (memory reference value) when the input signal (in_signal) shows “1” (inside). On the other hand, the selection signal generating unit30outputs the output signal (out_signal) showing the two bit value “01” when the input signal (in_signal) shows “0” (zero) (outside).

Next, another case in that the four bit value “0110” is set into the selection register31by the host10will be described with reference toFIG. 9B. InFIG. 9B, the selection signal generating unit30outputs the output signal (out_signal) showing the two bit value “10” (function value) when the input signal (in_signal) shows the value “1” (inside). On the other hand, the selection signal generating unit30outputs the output signal (out_signal) showing the two bit value “00” (memory reference value) when the input signal (in_signal) shows the value “0” (zero) (outside).

Similar processes as described above are conducted for other four bit values, respectively.

Next, a circuit configuration including the first circuit configuration through the sixth circuit configuration will be described with reference toFIG. 10.FIG. 10is a block diagram showing a seventh circuit configuration of the image drawing apparatus according to the embodiment of the present invention. InFIG. 10, elements that are the same as the ones shown inFIG. 3throughFIG. 8are indicated by the same reference numerals and the explanation thereof will be omitted.

InFIG. 10, the OR circuit26ainputs signals output from the X coordinate comparator15and the X range neglection setting unit71a, and outputs the logic operation result obtained from the logical addition, to the AND circuit27. The OR circuit26binputs signals output from the Y coordinate comparator25and the Y range neglection setting unit72b, and outputs the logic operation result obtained from the logical product, to the AND circuit27.

The AND circuit27inputs signals output from the OR circuit26aand the OR circuit26b, and outputs the logic operation result obtained from the logical product, to the EXOR circuit28.

The EXOR circuit28inputs signals output from the AND circuit27and the inside-outside inversion switching unit73, and outputs the logic operation result from operating the exclusive OR, to the AND circuit29b.

The inverter circuit29ainputs a signal output from the outside range setting unit74a, inverts the signal, and outputs the signal being inverted to the AND circuit29b. The AND circuit29binputs signals output from the EXOR circuit28and the inverter circuit29a, and outputs a signal showing the logic operation result to the OR circuit29c.

The OR circuit29cinputs signals from the AND circuit29band the inside range setting unit74b, and outputs a signal showing “inside” or “outside” as the logic operation results obtained from the logical addition, to the selection signal generating unit30.

Other processes after that are conducted similarly as described above with reference toFIG. 3, and the explanation thereof will be omitted.

By configuring logic circuits as described above, functions realized by the first circuit configuration through the sixth circuit configuration can be realized in the single image drawing apparatus100.

As described above, the host10sets the coordinate (XMIN, XMAX) of the upper left corner of the inner rectangle7band the coordinate (XMAX, YMIN) of the lower right corner of the outer rectangle7ain order to compare with the coordinate being transferred. Alternatively, as shown inFIG. 11, the host10may set a lateral width Wx and a longitudinal width Wy showing a difference between the outer rectangle7aand the inner rectangle7b.

FIG. 11is a diagram showing a method for setting the coordinates of the inner rectangle according to the embodiment of the present invention. In the outer rectangle7ainFIG. 11showing an outer rectangle having the transmission coefficient, which is not constant, the coordinate of the upper left corner is (X0, Y0), and the coordinate of the lower right corner is (X1, Y1) Circuits may be configured so that XMAX is obtained by subtracting the lateral width Wx from an abscissa X1(XMAX=X1−Wx), and XMIN is obtained by adding the lateral width Wx to an abscissa X0(XMIN=X0−Wx), and similarly, YMAX is obtained by subtracting the longitudinal width Wy from an ordinate Y0(YMAX=Y0−Wy), and YMIN is obtained by adding the longitudinal width Wy to an ordinate Y1(YMIN=Y1−Wy).

For example, the above-described operation can be realized by configuring circuits as shown inFIG. 12.FIG. 12is a diagram showing a circuit configuration for calculating the coordinates of the inner rectangle, according to the embodiment of the present invention.

InFIG. 12, an X1storage register131, a Wx storage register132, an X0storage register133, a subtracter134, and an adder135are additionally configured before the XMAX storage register11aand the XMIN storage register11bconcerning the X coordinate of the inner rectangle7b. An Y1storage register141, a Wy storage register142, an Y0storage register143, a subtracter144, and an adder145are additionally configured before the YMAX storage register21aand the YMIN storage register21bconcerning the Y coordinate of the inner rectangle7b.

The X1storage register131is a register used to store the abscissa X1, the Wx storage register132is a register used to store the lateral width Wx, and the X0storage register133is a register used to store the abscissa X0. The subtracter134receives a signal showing the abscissa X1from the X1storage register131and a signal showing the lateral width Wx from the Wx storage register132, and outputs a logical operation result obtained by subtracting the lateral width Wx from the abscissa X1, to the XMAX storage register11a. The adder135receives a signal showing the lateral width Wx from the Wx storage register132and a signal showing the abscissa X0from the X0storage register133, and outputs a logical operation result obtained by adding the abscissa X0to the lateral width Wx, to the XMIN storage register11b.

The Y1storage register141is a register used to store the ordinate Y1, the Wy storage register142is a register used to store the longitudinal width Wy, and the Y0storage register143is a register used to store the ordinate Y0. The subtracter144receives a signal showing the ordinate Y1from the Y1storage register141and a signal showing the longitudinal width Wy from the Wy storage register142, and outputs a logical operation result obtained by subtracting the longitudinal width Wy from the ordinate Y1, to the YMAX storage register21a. The adder145receives a signal showing the longitudinal width Wy from the Wy storage register142and a signal showing the ordinate Y0from the Y0storage register143, and outputs a logical operation result obtained by adding the ordinate Y0to the longitudinal width Wy, to the YMIN storage register21b.

When the lateral width Wx is the same as the longitudinal width Wy, either one of the Wx storage register132and the Wy storage register142may be omitted and one of the Wx storage register132and the Wy storage register142may be shared with the lateral width Wx and the longitudinal width Wy.

As described above, according to the present invention, since the inner region8bof the inner rectangle7bis simply indicted, that is, one setting is required to set a range for the bit block to transfer, the image7created by using the bitmap can be transferred with one BITBLT transfer. Accordingly, it is possible to realize the BITBLT transfer at higher speed.

As described above, the outer region8aand the inner region8bare defined by determining whether or not the transmission coefficient is constant in the image7. Alternatively, the host10may determine and set at least one of a region where only the transmission coefficient is not constant, a region where only the pixel value is not constant, a region where the transmission coefficient or the pixel value is not constant, and a like. In each case, it is possible to realize the BITBLT transfer at higher speed by applying one of the first circuit configuration through the seventh circuit configuration. The pixel value may be a binary or a multiple-value for a color display using the YUV color space, the RGB color space, the YMCK color space, or a like.

In an image drawing apparatus displaying a digital color screen, at least one region in the image7is determined based on an attribute (the transmission coefficient and/or the pixel value) necessary to depict colors.

Moreover, the first circuit configuration is considered as the basic circuit configuration, and any functions additionally configured in the second circuit configuration through the sixth circuit configuration can be combined to form another circuit configuration.

For example, the present invention can be applied to a car navigation system, a mobile phone, a pachinko machine, or a like that displays a predetermined image for a menu screen or a like.

According to the present invention, in a case of the BITBLT transfer for an image including a portion where the transmission coefficient is constant and a portion where the transmission coefficient is not constant, it is possible to selectively switch to one of the memory device50, the constant register51, and the function operating unit52to obtain the transmission coefficient (or the pixel value) during the BITBLT transfer. Therefore, it is possible to reduce a memory amount and a data transfer amount for the BITBLT transfer.