A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor devices, and more particularly to silicon-controlled rectifiers, for example those used to protect against electrostatic discharge in high-voltage applications.

BACKGROUND OF THE INVENTION

Electrostatic discharge (ESD) protection for high-voltage integrated circuits is challenging due to the requirement of high holding voltage to minimize the risk of ESD latchup. Silicon controlled rectifiers (SCR's) are attractive devices for ESD protection applications, for example because of their inherent bipolar conductivity modulation mechanism which can provide a deep snapback characteristic with a relatively small holding voltage, in the range of 1.0 to 2.0 V. This characteristic can reduce power dissipation in the SCR during an ESD event and result in a device which can be more robust when exposed to ESD than other devices such as diodes and grounded-gate NMOS (GGNMOS) devices.

A conventional twin-well SCR which can be used in low voltage ESD applications is depicted as a circuit schematic atFIG. 1, and as a cross section of one possible physical layout of theFIG. 1circuit atFIG. 2. A top view of theFIG. 2structure is depicted inFIG. 3.

FIG. 1depicts a PNP parasitic bipolar junction transistor (BJT)10, an NPN parasitic BJT12, a first resistor R_pwell14, and a second resistor R_nExt16. The PNP device includes an emitter18, a base20, and a collector22, and the NPN device has an emitter24, a base26, and a collector28. The devices are electrically coupled with an anode30, which can be coupled to a bond pad, and a cathode32. The cross section ofFIG. 2depicts a cross section of one possible physical layout of theFIG. 1circuit.FIG. 2depicts anode30, cathode32, PNP emitter18, base20, and collector22, NPN emitter24, base26, and collector28. The PNP base20is provided by an N extension33, which also provides R_nExt resistor16. The NPN base26is provided by a P-well34, which also provides R_pwell resistor14. These structures can be formed within an N-type epitaxial layer35, which in turn can be formed over a P-type silicon semiconductor substrate assembly36.FIG. 2further depicts isolation regions38-46, which can be shallow trench isolation (STI) or LOCOS field isolation.

A blocking junction48of the N-Extension33and the P-Well34controls the SCR triggering. The doping of the N-Extension33and the P-Well34is designed to form a blocking junction48which yields a trigger voltage as high as 45 V for high-voltage ESD protection. Avalanche breakdown of this blocking junction48injects carriers into the N-Extension33and P-Well34, thereby biasing the NPN12and PNP10transistors ON. Electrons added from the NPN emitter24and holes from the PNP emitter18reinforce the avalanche breakdown, creating a positive feedback. Once the gain of the system exceeds unity, the SCR will enter its ON state and the anode to cathode potential will drop to the holding voltage (VH).

TheFIG. 2structure can be implemented in theFIG. 3top view of theFIG. 2structure, demonstrating the use of strip technology. The topology depicted consists of a strip18of p-type dopant material which provides the P+ diffusion region for the emitter of the PNP device10, and a strip24of n-type dopant material which provides the N+ diffusion region for the emitter of NPN device12. The strips are uniformly doped with the appropriate dopant materials to the dopant concentrations sufficient for operation of the device.FIG. 2further depicts a distance D1which is the width of the PNP emitter18and NPN emitter24, D2which is the distance between the PNP emitter18and the NPN collector28and also the distance between the NPN emitter24and the PNP collector22, D3which is the width of the PNP collector22and also the width of the NPN collector28, D4which is the distance from the edge of the PNP collector22and the edge of the P Well34and also the distance from the edge of the NPN collector28and the edge of the N Extension33, D5which is the distance from the edge of the PNP emitter18and the blocking junction48, and D6which is the distance from the edge of the NPN emitter and the blocking junction48. In addition to the features depicted inFIGS. 2 and 3, various other conventional features will be formed over and on the structures depicted in a completed semiconductor device.

When using SCR's for ESD protection of high-voltage integrated circuits, however, the small holding voltage VHbecomes problematic, particularly for the case of a supply clamp connected between two supply rails with a voltage difference of more than 30 or 40 V. This is because the SCR is susceptible of being latched up unless the SCR's holding voltage is larger than the supply voltage difference. Specifically, in high voltage applications subsequent to an ESD event, an inability to shut off the latchup state can occur.

Various SCR structures aimed at increasing the holding voltage have been reported. For example, the article “High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps” (Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, and Peter Hopper, IEEE Transactions on Device and Materials Reliability, vol. 4, pp. 273-280, June 2004) proposes a low-voltage trigger SCR (LVTSCR) with a high holding voltage based on reducing the parasitic BJT emitter area. However, the increase of the holding voltage was not sufficiently large for high-voltage IC ESD applications. Also, the article “ESD protection for high-voltage CMOS technologies” (Olivier Quittard, Zeljko Mrcarica, Fabrice Blanc, Guido Notermans, Theo Smedes, and Hans van Zwol, in Proc. EOS/ESD Symposium, pp. 77-86, 2006) proposes a structure which can be used to realize a high voltage supply clamp design by stacking several MOS transistors. However, this structure uses a large silicon area.

A device which provides an SCR for high voltage applications and which has a high holding voltage VHwould be desirable.

SUMMARY OF THE EMBODIMENTS

In accordance with various embodiments of the invention, a semiconductor device comprises a PNP bipolar transistor comprising an emitter formed in a PNP emitter area. The PNP emitter area comprises at least two separate segments having a p-type conductivity and at least two separate segments having an n-type conductivity. A width of each of the at least two separate segments in the PNP emitter area having the p-type conductivity is about equal to a width of each of the at least two separate segments in the PNP emitter area having the n-type conductivity.

This embodiment of the device further comprises an NPN bipolar transistor comprising an emitter formed in an NPN emitter area. The NPN emitter area comprises at least two separate segments having an n-type conductivity and at least two separate segments having a p-type conductivity, wherein a width of each of the at least two separate segments in the NPN emitter area having the n-type conductivity is about equal to a width of each of the at least two separate segments in the NPN emitter area having the p-type conductivity.

In another embodiment of the invention, a semiconductor device comprises a PNP bipolar transistor comprising an emitter and a collector, wherein the PNP bipolar transistor collector has only an n-type conductivity. The device further comprises an NPN bipolar transistor comprising an emitter and a collector, wherein the NPN bipolar transistor collector has only a p-type conductivity. One of the PNP bipolar transistor emitter and the NPN bipolar transistor emitter has only one of the n-type conductivity and the p-type conductivity, and the other of the PNP bipolar transistor emitter and the NPN bipolar transistor emitter has both an n-type conductivity and a p-type conductivity.

Another embodiment, a method for forming a semiconductor device, comprises forming a PNP bipolar transistor and an NPN bipolar transistor. Formation of the PNP bipolar transistor and the NPN bipolar transistor comprises masking a PNP emitter area and an NPN emitter area with a first mask having openings therein, implanting n-type dopants through the openings in the first mask into both the PNP emitter area and the NPN emitter area to form at least two separate n-type segments in the PNP emitter area and at least two separate n-type segments in the PNP emitter area, and masking the PNP emitter area and the NPN emitter area with a second mask having openings therein. P-type dopants are implanted through the openings in the second mask into both the PNP emitter area and the NPN emitter area to form at least two separate p-type segments in the PNP emitter area and at least two separate p-type segments in the NPN emitter area. A width of the p-type segments in the PNP emitter area, a width of the p-type segments in the NPN emitter area, a width of the n-type segments in the PNP emitter area, and a width of the n-type segments in the NPN emitter area are all about the same width.

It should be noted that some details of the FIGS. have been simplified and are drawn to facilitate understanding of the inventive embodiments rather than to maintain strict structural accuracy, detail, and scale.

DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present teachings comprise a silicon controlled rectifier which has a high holding voltage (VH), and thus lends itself for use in applications where the supply voltage is high. In these applications, conventional SCR's are susceptible to latchup, for example because it is difficult to provide a device wherein VHis higher than the supply voltage.

FIG. 4depicts a top view of an embodiment of the invention. This embodiment comprises the use of “segmented topology” in which PNP emitter strip18and NPN emitter strip24ofFIG. 3are replaced with the segments ofFIG. 4. With the segmented topology of this embodiment, the PNP emitter area47and the NPN emitter area49each comprise alternating P-type regions and N-type regions. In the present disclosure, the segmented regions47and49are referred to as “emitter areas” because it is believed that only the portions of the regions implanted with the appropriate dopant (i.e., p-type for the PNP device and n-type for the NPN device) function as a portion of the emitter, while the regions having the opposite conductivity remain inactive during device operation. In theFIG. 4embodiment, doped regions50form P-type regions of the PNP emitter, and regions52form N-type regions of the PNP emitter. Further, regions54form P-type regions of the NPN emitter, and regions56form of N-type regions of the NPN emitter.

The emitter injection efficiency factor can be expressed as:

where NBis the base doping concentration, NEis the emitter doping concentration, DEand DBare the minority carrier diffusion coefficients in emitter and base regions, respectfully, xBis the width of the neutral base region, and xEis the width of the neutral emitter region. Based on this equation and without being limited by theory, the emitter injection efficiency can be decreased by: increasing the base length; decreasing the emitter length; increasing the base doping concentration; decreasing the emitter doping concentration; or reducing the area of the emitter Changing a portion of each emitter to the opposite conductivity type, in effect, decreases the emitter areas such that the emitter injection efficiencies of these two regions are reduced. This results in an increase in the holding voltage VH. In principle, SCR VHcan be increased by decreasing the emitter injection efficiency of the bipolar transistors imbedded in the SCR.

Additionally, as depicted inFIG. 4, PNP emitter regions which are adjacent to NPN emitter regions at a perpendicular direction across isolation region42have opposite conductivity types. In the vertical direction, each separate segment of the emitter column is equal in width to the other separate segments in the column. (As used herein, two “separate” segments refers to two segments having a first type conductivity with another segment having a different dopant conductivity interposed between the two separate segments.) Further, each emitter segment is immediately adjacent to another emitter segment, with no undoped portion existing between adjacent segments.

InFIG. 4, the segmented emitter topology depicted comprises a replacement of 50% of the P+ diffusion regions for the emitter of PNP device with N+ diffusion regions. Similarly, 50% of the N+ diffusion regions for the emitter of the NPN device have been replaced with P+ diffusion regions. As a result, this exemplary embodiment comprises a “segment ratio” of 1:1/1:1. The emitter on the anode side has 1 original P+ region for every 1 N+ replacement, and the emitter on the cathode side has 1 original N+ region for every 1 P+ replacement. That is, the length of each original dopant segment is the same length as each replaced dopant segment (i.e. 50% of the conventional strip emitter diffusion for each of the PNP and NPN devices remains and 50% has been replaced with a diffusion material of the opposite conductivity type) and the emitter replacements are the same on both the anode side and the cathode side.

FIG. 5is a graph comparing transmission line pulse (TLP) current-voltage (I-V) curves of a conventional device according to the technology ofFIG. 3and a SCR device which incorporates the embodiment ofFIG. 4. The conventional and inventive devices which are measured to provide the plot information for the graph ofFIG. 3each comprise an emitter having a width (vertical direction inFIGS. 3 and 4) of 186 micrometers (μm) and a length (horizontal direction inFIGS. 3 and 4) of 33 μm. The conventional device has the emitter strips ofFIG. 3, while the inventive device has the segmented emitter topology ofFIG. 4(1:1/1:1 segmented topology). For the inventive device, each individual doped emitter region52,54has a width of 186 μm and a length of 33 μm.

As reflected in theFIG. 5graph, while the holding voltage60of the conventional device having strip topology is about 4 V, the holding voltage62of the exemplary inventive device having the segmented topology of the present teachings is greater than about 35 V, for example about 40 V. In addition, by measuring the leakage current, it can be determined that while the failure current (i.e. breakdown current, “It2”) of the conventional device is greater than 10 A, the failure current of the device of the present embodiment is greater than about 7.5 A, for example about 8.0 A, as shown at64, despite the measured VHincrease. This is in contrast to conventional devices having an actual decrease in the size of the emitter areas, which can result in a decrease in the failure current It2and can heat to unacceptable temperatures during operation.

Further, as reflected inFIG. 6, the segmented SCR device possesses a slightly higher trigger voltage and current (about 52.0 V at 0.05 A) compared to the conventional device having strip topology (about 46.0 V at 0.02 A).

While the previous embodiment comprises a device having and anode/cathode segment ratio of 1:1/1:1, devices having other anode/cathode segment ratios are also contemplated.FIG. 7depicts a device having a segment ratio of 3:1/3:1 (the length of the original segment is three times longer than each replaced segment). Said another way, 75% of the conventional strip emitter diffusion for each of the PNP and NPN devices remains and 25% has been replaced with a diffusion material of the opposite conductivity type, to result in a segment ratio of 3:1/3:1. In the segmented topology ofFIG. 7, the segmented PNP emitter area47comprises segments70doped to a P-type conductivity which are three times the length of each segment72doped to an N-type conductivity. The segmented NPN emitter area49comprises segments74doped to an N-type conductivity which are three times the length of each segment76doped to a P-type conductivity.

FIG. 8depicts TLP results for SCR devices having five different segment ratios. It is demonstrated that the holding voltage increases quickly when the segment ratio is decreased from 3:1/3:1 (FIG. 4) to 1:1/1:1 (FIG. 7). However, increasing the segment ratio further does not appear to increase the holding voltage, and can also decrease It2. Without being limited to theory, it is believed that for such a small segment ratio (less than 1:1/1:1), the effective emitter area becomes excessively undersized and results in saturation of injection efficiency and current crowding near the emitter regions. The former results in an unchanged holding voltage, while the latter gives rise to a decrease in It2.

Changing the dimensions of D5(the distance from the edge of the PNP emitter18and the breakdown junction48) and D6(the distance from the edge of the NPN emitter24and the breakdown junction48) can also alter the ESD performance.FIG. 9shows the TLP results of the 1:1/1:1 segment ratio SCR ofFIG. 4having four different D5and D6dimensions (with D5and D6being equal). When D5and D6is changed from 2 μm to 8 μm, the holding voltage is increased from 10 V to 45 V. Another advantage of increasing D5and D6is that the failure current It2increases by about 31 mA/μm. D5and D6represent the base layer thicknesses of the PNP device and the NPN device respectively. While not intending to be bound by any particular theory, it is believed that the increased holding voltage results from a decrease in the current gain of the BJT devices when D5and D6are increased, and that the increased It2results from the increased area of the SCR.

The devices depicted inFIGS. 4 and 7, for purposes of the present disclosure, can be referred to as having symmetrical emitter segmentations. The size of the original emitter segment on the anode side is the same as the original emitter segment on the cathode side, and the replaced emitter segment on the anode side is the same as the replaced emitter segment on the cathode side. In other words, in an anode/cathode segment ratio of A:B/X:Y, A=X and B=Y (the anode segment ratio being A:B and the cathode segment ratio being X:Y).FIG. 10depicts partial reproductions ofFIG. 4(10A) andFIG. 7(10B). For every doped PNP emitter segment, there is an analogous, similarly-sized but oppositely-doped NPN emitter segment located perpendicular across the breakdown junction. The horizontal arrows indicate that for every segment in PNP emitter area47, there is a similar, oppositely-doped NPN emitter segment in NPN emitter area49at a direction perpendicular to the breakdown junction48. Each analogous segment has a similar length (vertical direction) and width (horizontal direction), but opposite doping types.

FIG. 11depicts three different asymmetrical emitter segmentation designs. With each design, the PNP collector, PNP emitter, and NPN collector are all doped uniformly to a single dopant concentration. The NPN emitter, however, comprises a segmented topology comprising both n-type regions and p-type regions.

The structure ofFIG. 11Acomprises a segment ratio of 1:0/1:2, or more simply 0/1:2. There are no anode emitter replacement segments (i.e. the anode emitter is entirely doped to a p-type conductivity and has only a p-type conductivity), and there is one original cathode emitter segment (N+) for every two replacement cathode emitter segments (P+). In other words, each P+ cathode emitter replacement segment is twice as long as the original cathode emitter segment.

The structure ofFIG. 11Bcomprises a segment ratio of 0/1:1, as there are no anode emitter replacement segments and there is one original cathode emitter segment (N+) for each replacement cathode emitter segment (P+).

The structure ofFIG. 11Ccomprises a segment ratio of 0/2:1, as there are no anode emitter replacement segments and there are two original cathode emitter segments (N+) for each replacement cathode emitter segment (P+).

The structure ofFIG. 12also depicts three different asymmetrical emitter segmentation designs. With each of these designs, the PNP collector, the NPN emitter, and the NPN collector are all uniformly doped to a single dopant concentration. The PNP emitter, however, comprises a segmented topology comprising both n-type regions and p-type regions.

The structure ofFIG. 12Acomprises a segment ratio of 1:2/1:0, or more simply 1:2/0. There is one original anode emitter segment (P+) for every two replacement anode emitter segments (N+), and there are no cathode emitter replacement segments.

Similarly, it follows that the structure ofFIG. 12Bcomprises a segment ratio of 1:1/0, and the structure ofFIG. 12Ccomprises a segment ratio of 2:1/0.

FIG. 13is a graph depicting the electrical characteristics for three exemplary asymmetrical segment topology designs in which the cathode emitter is segmented into ratios of 0/1:3, 0/2:3, and 0/1:2.FIG. 14is a graph depicting the electrical characteristics for three exemplary asymmetrical segment topology designs in which the anode emitter is segmented into ratios of 1:3/0, 2:3/0, and 1:2/0. Results indicate that asymmetrical segmentation in the NPN emitter significantly alters the holding voltage VH. However, asymmetrical segmentation of the PNP emitter has little effect on the holding voltage. Asymmetrically segmenting the cathode emitter in an SCR can increase VHfrom about 10 V to about 36 V. In addition to the change in VH, the failure current It2is also altered by the topology segmentation on the cathode side. For example, It2decreases as the segmented ratio is increased from 0/1:2 to 0/1:1 to 0/2:1. The trade-off between holding voltage VHand failure current It2can be considered when using the proposed devices for high-voltage ESD applications.

To manufacture the exemplary devices, a photoresist mask used to form each of the PNP emitter area47and the NPN emitter area49can be altered such that no additional masking steps are required. For example, separate N+ segments of both the PNP emitter and the NPN emitter can be implanted during a single N+ doping step by simultaneously exposing portions of the PNP emitter and the NPN emitter through openings in a first mask during N+ dopant implantation. Similarly, P+ regions of both the PNP emitter and the NPN emitter can be implanted during a single P+ doping step by simultaneously exposing portions of the PNP emitter and the NPN emitter through openings in a second mask during P+ implantation. Typical N+ doping concentrations in both the PNP and NPN emitters can be about 9×1019atoms/cm3, and typical P+ doping concentrations in both PNP and NPN emitters can be about 6×1019atoms/cm3.

Various embodiments of the SCR as presently described have been designed based on the concept that the holding voltage VHcan be increased with reduced emitter injection efficiency in the SCR. Both symmetrically and asymmetrically segmented emitter topology have been disclosed to achieve this objective. In various embodiments, an asymmetrical design having dual doped regions (e.g. both n-type and p-type regions) on the cathode (NPN) emitter can be more effective than a design having dual doped regions on the anode (PNP) emitter. As described above, various inventive SCR embodiments can possess a holding voltage larger than 40 V and failure current It2higher than 31 mA/μm, thus realizing a high holding voltage SCR adaptable for use as a supply clamping device for high-voltage ESD applications. This can be accomplished without additional masking steps in a device having a relatively small area while minimizing damage from ESD stress. Inventive embodiments can be suitable for use with CMOS and BiCMOS processing, for example in twin-well processes.

Further, even though the effective area of the emitters is reduced to increase VH, the actual area is not reduced. As a result, problems found with a reduction in the actual emitter area, such as increased temperature a resulting decrease in current handling capability of the SCR, are avoided.

Use of various embodiments of the invention in liquid crystal display (LCD) driver circuits, telecommunication circuits, power switches, and automotive circuits is contemplated. Further, devices having a symmetrical segment ratio of one of 0/2:1, 0/1:1, 0/2:3, 0/1:2, 0/1:3, 2:1/0, 1:1/0, 2:3/0, 1:2/0, and 1:3/0, or having a segment ratio in the range from 3:1/3:1 to 1:3/1:3 inclusive, are contemplated.