Pixel unit, array substrate, and display device, and fabrication methods thereof

Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor, including a drain electrode; a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2017/081874, filed Apr. 25, 2017, which claims the priority of Chinese Patent Application No. 201610323593.4, filed on May 16, 2016, the entire contents of which are incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to the field of display technology and, more particularly, relates to a pixel unit, an array substrate, and a display device, and their fabrication methods.

BACKGROUND

In a conventional array substrate for display devices, a pixel electrode is often electrically connected to a drain electrode of a transistor through a via-hole in a planarization layer. This, however, may include a small contact area, and thus a high contact resistance, between the bottom conductive layer and the drain electrode. Consequently, an effective current produced by the transistor is small, and a power consumed by the entire display device is large.

The disclosed pixel unit, array substrate, and display device, and their fabrication methods are directed to solve one or more problems set forth above and other problems.

BRIEF SUMMARY OF THE DISCLOSURE

In accordance with some embodiments of the present disclosure, a pixel unit, an array substrate, and a display device, and their fabrication methods are provided.

One aspect of present disclosure provides a pixel unit, including: a transistor, including a drain electrode; a pixel electrode, including a first bottom conductive layer in contact with a surface of the drain electrode and a metal layer; and a planarization layer, formed on the transistor and the first bottom conductive layer. The metal layer is electrically connected to the first bottom conductive layer through a via-hole in the planarization layer.

In some embodiments, the first bottom conductive layer covers an entire surface of the drain electrode.

In some embodiments, the first bottom conductive layer further covers one or more sidewalls of the drain electrode.

In some embodiments, the pixel unit further includes a second bottom conductive layer formed on a source electrode of the transistor. The second bottom conductive layer covers an entire surface and one or more sidewalls of the source electrode.

In some embodiments, the second bottom conductive layer further covers data lines connected with the source electrode.

In some embodiments, the pixel unit further includes a third bottom conductive layer formed to cover a gate line connected with the gate electrode of the transistor.

In some embodiments, the metal layer is metallic silver layer.

In some embodiments, the pixel electrode further includes a top conductive layer formed on the metal layer. The top conductive layer covers the metal layer.

Another aspect of the present disclosure provides an array substrate, including: a base substrate; and at least one disclosed pixel unit on the base substrate.

Another aspect of the present disclosure provides a display device including a disclosed array substrate.

Another aspect of the present disclosure provides a method for fabricating a pixel unit, including: forming a transistor including a drain electrode; forming a first bottom conductive layer in contact with a surface of the drain electrode to cover the drain electrode; forming a planarization layer on the transistor and the first bottom conductive layer; forming a via-hole in the planarization layer to expose the first bottom conductive layer; and forming a metal layer on the planarization layer and electrically connected with the first bottom conductive layer through the via-hole.

In some embodiments, the first bottom conductive layer is formed to cover an entire surface and one or more sidewalls of the drain electrode.

In some embodiments, forming the first bottom conductive layer includes: forming a conductive film on the transistor; and patterning the conductive film to form the first bottom conductive layer on the drain electrode.

In some embodiments, the method further includes forming a second bottom conductive layer on a source electrode of the transistor to cover the source electrode.

In some embodiments, the second bottom conductive layer is formed simultaneously with the first bottom conductive layer during a one-stage patterning process.

In some embodiments, the second bottom conductive layer is formed to cover an entire top surface and all sidewalls of the source electrode.

In some embodiments, the second bottom conductive layer is formed to further cover a data line connected with the source electrode.

In some embodiments, the method further includes forming a third bottom conductive layer on a gate line connected with the gate electrode of the transistor to cover the gate line.

In some embodiments, the third bottom conductive layer is formed simultaneously with the first bottom conductive layer during the patterning process.

In some embodiments, the method further includes forming a top conductive layer on the metal layer to cover the metal layer.

DETAILED DESCRIPTION

Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings in order to fully understand and being able to implementing the present disclosure and to realizing the technical effect. It should be understood that the following description has been made only by way of example, but not to limit the present disclosure.

Various embodiments of the present disclosure and various features in the embodiments that are not conflicted with each other can be combined and rearranged in various ways. Without departing from the spirit and scope of the present disclosure, modifications, equivalents, or improvements to the present disclosure are understandable to those skilled in the art and are intended to be encompassed within the scope of the present disclosure.

Various embodiments, the present disclosure provides a pixel unit, a fabrication method thereof, a related array substrate, and a related display device. For example, array substrates may be used in display devices, such as active matrix liquid crystal display devices, and active matrix organic light-emitting display devices for driving the display screens to display images.

As illustrated inFIG. 1, an array substrate includes a base substrate1, and multiple pixel units provided on the base substrate1. Each pixel unit includes a transistor2, a pixel electrode3, and a planarization layer4located between the transistor2and the pixel electrode3. The planarization layer4has a via-hole. The pixel electrode3generally includes three layers stacked in an order of: a bottom, conductive layer31, a metal layer32, and a top conductive layer33. The bottom conductive layer31is electrically connected to the drain electrode21of the transistor2through the via-hole.

However, since the bottom conductive layer31and the drain electrode21are electrically connected through only one via-hole, the contact area between the bottom conductive layer31and the drain electrode21is normally small, resulting in a high contact resistance between the pixel electrode3and the drain electrode21. Therefore, an effective current produced by the transistor2is small, and a power consumed by the entire display device is large.

FIG. 2illustrates a schematic cross sectional structural view of an exemplary pixel unit in accordance with some embodiments of the present disclosure.

As illustrated, the pixel unit can include a transistor2, a pixel electrode3, a planarization layer4, and a pixel definition layer5.

The transistor2can include a drain electrode21, an active layer22, a gate insulating layer23, a gate electrode24, an interlayer insulating layer25, and a source electrode26.

The pixel electrode3can include a first bottom conductive layer311, a metal layer32, and a top conductive layer33.

The first bottom conductive layer311can be formed on the drain electrode21of the transistor2. The first bottom conductive layer311can entirely cover the drain electrode21.

The planarization layer4can be formed on the transistor2and the first bottom conductive layer311. A via-hole can be formed in the planarization layer4.

The metal layer32and the top conductive layer33can be successively formed on the planarization layer4. The metal layer32can be electrically connected to the first bottom conductive layer311through the via-hole.

The gate insulating layer23can be formed on the active layer22.

The gate electrode24can be formed on the gate insulating layer23.

The interlayer insulating layer25, or an interlayer dielectric layer, can be formed on the gate electrode24. The interlayer insulating layer25can have two via-holes. The two via-holes also pass through the gate insulating layer23. The active layer22under the gate insulating layer23can be exposed through the two via-holes.

The source electrode26and the drain electrode21can be respectively formed on the interlayer insulating layer25. The source electrode26can be electrically connected to the active layer22through one of two via-holes in the interlayer insulating layer25. The drain electrode21can be electrically connected to the active layer22through the other of the two via-holes in the insulating layer25.

In some embodiments, the pixel electrode3can include three layers: the first bottom conductive layer311, the metal layer32, and the top conductive layer33covering the metal layer32. In some other embodiments, depending on product designing and functional requirements, the pixel electrode3can only include two layers: the first bottom conductive layer311and the metal layer32.

It should be noted that, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased.

Further, since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in a fabricating process of the disclosed pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before forming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Referring toFIG. 3, a schematic cross sectional structural view of another exemplary pixel unit is shown in accordance with some other embodiments of the present disclosure.

As illustrated, the first bottom conductive layer311can cover the entire top surface and all sidewalls of the drain electrode21. It should be noted that,FIG. 3is a cross sectional structural view of the pixel unit, thus, only the top surface and two sidewalls of the drain electrode21are shown, while other sidewalls of the drain electrode21are not shown inFIG. 3.

In some embodiments, a material of the first bottom conductive layer311can be a transparent conductive material, such as Indium Tin Oxide (ITO).

In the conventional pixel units, the metal layer32is normally a metal silver layer. The drain electrode21of the transistor2contains metal aluminum. The planarization layer4is formed on the drain electrode21, but does not cover all sidewalls of the drain electrode21. Therefore, the sidewalls of the drain electrode21not covered by the planarization layer4are exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the sidewalls of the drain electrode21can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the drain electrode21in the same time, thereby resulting in a defect of the transistor2.

In the disclosed pixel unit, the first bottom conductive layer311can be formed to cover an entire top surface and all sidewalls of the drain electrode21. As such, not only the contact area between the first bottom conductive layer311and the drain electrode21can be increased, the electrochemical reaction between the metal aluminum of the drain electrode21and the metal silver of the metal layer32can be prevented. Therefore, the quality of the transistor2and the pixel electrode3can be ensured.

Referring toFIG. 4, a schematic cross sectional structural view of another exemplary pixel unit is shown in accordance with some other embodiments of the present disclosure.

As illustrated, a second conductive layer312can be formed between the source electrode26of the transistor2and the planarization layer4. The second conductive layer312can cover the source electrode26of the transistor2.

Specifically, the second bottom conductive layer312can cover the entire top surface and all sidewalls of the source electrode26. It should be noted that,FIG. 4is a cross sectional structural view of the pixel unit, thus, only the top surface and two sidewalls of the source electrode26are shown, while other sidewalls of the source electrode26are not shown.

In some embodiments, a material of the second bottom conductive layer312can be a transparent conductive material, such as Indium Tin Oxide (ITO).

In the conventional pixel units, a material of the source electrode26contains metal aluminum, which is the same material contained in the drain electrode21. The planarization layer4is formed on the source electrode26, but does not cover all sidewalls of the source electrode26. Therefore, the sidewalls of the source electrode26not covered by the planarization layer4are exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the sidewalls of the source electrode26can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the source electrode26in the same time, thereby resulting in a defect of the transistor2.

In the disclosed pixel unit, when forming the first bottom conductive layer311, a second bottom conductive layer312can also be formed simultaneously between the source electrode26and the planarization layer4. The second bottom conductive layer312can be formed to cover an entire top surface and all sidewalls of the source electrode26. As such, not only the contact area between the second bottom conductive layer312and the source electrode26can be increased, the electrochemical reaction between the metal aluminum of the source electrode26and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

In some embodiments, the second bottom conductive layer312can further cover a data line connected with the source electrode26of the transistor2.

In the conventional fabricating process for forming pixel units, the source electrode26of the transistor2and the data line connected with the source electrode26can be formed simultaneously by using a patterning process. A material of the data line contains metal aluminum, which is the same material contained in the source electrode26. However, the planarization layer4does not cover the data line. Therefore, the data line is exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the data line can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the data line in the same time, thereby resulting in a defect of the transistor2.

In the disclosed pixel unit, the second bottom conductive layer312can be formed to cover an entire top surface and all sidewalls of the source electrode26, as well as the data line connected with the source electrode26. As such, the electrochemical reaction between the metal aluminum of the data line and the metal silver of the metal layer32can be prevented. Therefore, the quality of the transistor2and the pixel electrode3can be ensured.

In some embodiments, the first bottom conductive layer311and the second bottom conductive layer312can be simultaneously formed by using a one-stage patterning process. Further, a mask for forming the source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode can be used in such one-stage patterning process.

Often, the source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode can be formed through a one-stage patterning process using a single mask. In the disclosed pixel unit, the first bottom conductive layer311covers the drain electrode21, and the second bottom conductive layer312covers the source electrode26and the data line connected to the source electrode. Thus, after coating a conductive layer on the source electrode26and the drain electrode21of the transistor2, as well as an the data line connected with the source electrode, by using the same single mask for patterning the he source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode, same patterns of the source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode can be formed.

In the same time, the line width of the patterns can be controlled by adjusting the exposure process. As such, the first bottom conductive layer311can cover not only the entire top surface of the drain electrode21, but also all sidewalls of the drain electrode21. Similarly, the second bottom conductive layer312can cover not only the entire top surface of the source electrode26, but also all sidewalls of the source electrode26, and the data line connected to the source26as well.

Accordingly, by repeatedly using the same single mask for patterning the source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode, the cost of mask can be reduced.

In some other embodiments, the first bottom conductive layer311and the second bottom conductive layer312can be formed by using two patterning processes, which may be selected in accordance with the actual situation.

In some embodiments, a third bottom conductive layer (not shown in the figures) can be formed on a gate line connected with the gate electrode24of the transistor2. The third bottom conductive layer can cover the gate line connected with the gate electrode24of the transistor2. A material of the third bottom conductive layer can be a transparent conductive material, such as Indium Tin Oxide (ITO).

In the conventional fabricating process for forming pixel units, the gate electrode24of the transistor2and the gate line connected with the gate electrode24can be formed simultaneously by using a patterning process. A material of the gate line contains metal aluminum, which is the same material contained in the gate electrode24. However, the planarization layer4does not cover the gate line. Therefore, the gate line is exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the gate line can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the gate line in the same time, thereby resulting in a defect of the transistor2.

In the disclosed pixel unit, the third bottom conductive layer can be formed to cover the gate line connected with the gate electrode24. As such, the electrochemical reaction between the metal aluminum of the gate line and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

In some embodiments, the first bottom conductive layer311, the second bottom conductive layer312, and the third bottom conductive layer can be simultaneously formed by using a one-stage patterning process. In some other embodiments, the first bottom conductive layer311, the second bottom conductive layer312, and the third bottom conductive layer can be formed by using different patterning processes, which may be selected in accordance with the actual situation.

It should be noted that, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased. Since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in a fabricating process of the disclosed pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before forming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Further, the disclosed pixel unit can include a first bottom conductive layer311, a second bottom conductive layer312and a third bottom conductive layer. The first bottom layer311can cover the entire top surface and all sidewalls of the drain electrode21. The second bottom layer312can cover the entire top surface and all sidewalls of the source electrode26, as well as a data line connected with the sauce electrode. The third bottom conductive layer can cover a gate line connected with the gate electrode. As such, the electrochemical reaction between the metal aluminum of the drain electrode21, source electrode26, data line, gate electrode24, as well as gate line, and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

Another aspect of the present disclosure provides an array substrate. The array substrate can include base substrate1, and at least one pixel unit on the base substrate1. The pixel unit can be any one of the disclosed pixel unit discussed above in connection withFIGS. 2-4.

In each pixel unit of the disclosed array substrate, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased. Since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in a fabricating process of the disclosed array substrate, for each pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before forming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Further, each pixel unit of the disclosed array substrate can include a first bottom conductive layer311, a second bottom conductive layer312and a third bottom conductive layer. The first bottom layer311can cover the entire top surface and all sidewalls of the drain electrode21. The second bottom layer312can cover the entire top surface and all sidewalls of the source electrode26, as well as a data line connected with the sauce electrode. The third bottom conductive layer can cover a gate line connected with the gate electrode. As such, the electrochemical reaction between the metal aluminum of the drain electrode21, source electrode26, data line, gate electrode24, as well as gate line, and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

Another aspect of the present disclosure provides a display device. The display device can be an active matrix liquid crystal display device, or an active matrix organic light emitting display device. The display device can include the disclosed array substrate described above.

Specifically, the display device can be a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, a navigator, or any other product or component having a display function.

When the display device is an active matrix organic light emitting display device, as shown inFIG. 4, a pixel definition layer5can be formed on the pixel electrode3of each pixel unit. And a light emitting layer can be formed on the pixel definition layer5. As such, the display device is able to display an image.

In each pixel unit of the disclosed display device, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased. Since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in a fabricating process of the disclosed display device, for each pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before forming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Further, each pixel unit of the disclosed display device can include a first bottom conductive layer311, a second bottom conductive layer312and a third bottom conductive layer. The first bottom layer311can cover the entire top surface and all sidewalls of the drain electrode21. The second bottom layer312can cover the entire top surface and all sidewalls of the source electrode26, as well as a data line connected with the sauce electrode. The third bottom conductive layer can cover a gate line connected with the gate electrode. As such, the electrochemical reaction between the metal aluminum of the drain electrode21, source electrode26, data line, gate electrode24, as well as gate line, and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

Referring toFIG. 5, a flow chart of an exemplary process for fabricating a pixel unit is shown in accordance with some embodiments of the present disclosure.

As illustrated, the process for fabricating a pixel unit can include the following steps.

At step101, a transistor2can be formed on a base substrate1.

As shown inFIG. 2, forming the transistor2can include: forming an active layer22on the base substrate1; forming a gate insulating layer23on the active layer22; forming a gate electrode24on the gate insulating layer23; forming an interlayer insulating layer25on the gate electrode24; forming two via-holes in the interlayer insulating layer25, where the two via-holes also pass through the gate insulating layer23, and the active layer22under the gate insulating layer23can be exposed through the two via-holes; and forming a source electrode26and a drain electrode21on the interlayer insulating layer25, where the source electrode26can be electrically connected to the active layer22through one of two via-holes in the interlayer insulating layer25, and the drain electrode21can be electrically connected to the active layer22through the other of the two via-holes in the insulating layer25.

At step102, a first bottom conductive layer311can be formed on the drain electrode21of the transistor2. The first bottom conductive layer311can entirely cover the drain electrode21.

As shown inFIG. 2, the first bottom conductive layer311can be formed by a one-stage patterning process. Specifically, a conductive film can be formed on the transistor2, and a photoresist film can be coated on the conductive film. The conductive film coated by the photoresist film can be exposed, developed and etched to remove the excess conductive film. The remaining photoresist film can be peeled off. As such, the first bottom conductive layer311can be formed on the drain electrode21of the transistor2to cover the drain electrode21.

At step103, a planarization layer4can be formed on the transistor2and the first bottom conductive layer311. A via-hole can be formed in the planarization layer4.

Specifically, a one-stage patterning process can be used to form the planarization layer4and the via-hole on the transistor2and the first bottom conductive layer311.

At step104, a metal layer32and a top conductive layer33can be successively formed on the planarization layer4. The metal layer32can be electrically connected to the first bottom conductive layer311through the via-hole.

Specifically, a one-stage patterning process can be used to simultaneously form the metal layer32and the top conductive layer33.

In some embodiments, the pixel electrode3can include three layers: the first bottom conductive layer311, the metal layer32, and the top conductive layer33covering the metal layer32. In some other embodiments, depending on product designing and functional requirements, the pixel electrode3can only include two layers: the first bottom conductive layer311and the metal layer32. When the pixel electrode3includes two layers, the step104can be: forming a metal layer32on the planarization layer4. The metal layer32can be electrically connected to the first bottom conductive layer311through the via-hole.

It should be noted that, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased.

Further, since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in the disclosed process for fabricating the pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before forming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Further, as illustrated inFIG. 3, the first bottom conductive layer311formed at step102can cover the entire top surface and all sidewalls of the drain electrode21. And a material of the first bottom conductive layer311can be a transparent conductive material, such as Indium Tin Oxide (ITO).

In the conventional pixel units, the metal layer32is normally a metal silver layer. The drain electrode21of the transistor2contains metal aluminum. The planarization layer4is formed on the drain electrode21, but does not cover all sidewalls of the drain electrode21. Therefore, the sidewalls of the drain electrode21not covered by the planarization layer4are exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the sidewalls of the drain electrode21can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the drain electrode21in the same time, thereby resulting in a defect of the transistor2.

In the disclosed fabricating process, the first bottom conductive layer311can be formed to cover an entire top surface and all sidewalls of the drain electrode21. As such, not only the contact area between the first bottom conductive layer311and the drain electrode21can be increased, the electrochemical reaction between the metal aluminum of the drain electrode21and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

Referring toFIG. 6, a flow chart of another exemplary process for fabricating a pixel unit is shown in accordance with some other embodiments of the present disclosure. As illustrated, step102inFIG. 5can further include the following sub-steps.

At sub-step1021, a conductive film can be formed on the transistor2. Specifically, the conductive film can be deposited in the transistor2by using any suitable deposition technique.

At sub-step1022, by using a one-stage patterning process on the conductive film, the first bottom conductive layer can be formed on the drain electrode21of the transistor2.

Referring toFIG. 7, a flow chart of another exemplary process for fabricating a pixel unit is shown in accordance with some other embodiments of the present disclosure.

As illustrated, the sub-step1022inFIG. 6can further include forming a second conductive layer312between the source electrode26of the transistor2and the planarization layer4. The second conductive layer312and the first conductive layer311can be formed by a one-stage patterning process. The second conductive layer312can cover the source electrode26of the transistor2. A material of the second bottom conductive layer312can be a transparent conductive material, such as Indium Tin Oxide (ITO).

Specifically, a conductive film can be formed on the transistor2, and a photoresist film can be coated on the conductive film. The conductive film coated by the photoresist film can be exposed, developed and etched to remove the excess conductive film. The remaining photoresist film can be peeled off. As such, the first bottom conductive layer311and the second bottom conductive layer311can be formed. The first bottom conductive layer311can cover the entire top surface and all sidewalls of the drain electrode21. The second bottom conductive layer312can cover the entire top surface and all sidewalls of the source electrode26.

In some other embodiments, the first bottom conductive layer311and the second bottom conductive layer312can be formed by musing two patterning processes, which may be selected in accordance with the actual situation.

In the conventional pixel units, a material of the source electrode26contains metal aluminum, which is the same material contained in the drain electrode21. The planarization layer4is formed on the source electrode26, but does not cover all sidewalls of the source electrode26. Therefore, the sidewalls of the source electrode26not covered by the planarization layer4are exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the sidewalls of the source electrode26can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the source electrode26in the same time, thereby resulting in a defect of the transistor2.

In the disclosed fabricating process, the second bottom conductive layer312can be formed to cover the entire top surface and all sidewalls of the source electrode26. As such, not only the contact area between the second bottom conductive layer312and the source electrode26can be increased, the electrochemical reaction between the metal aluminum of the source electrode26and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

In some embodiments, the second bottom conductive layer312can be formed to cover a data line connected with the source electrode26of the transistor2.

Specifically, a conductive film can be formed on the source electrode26, the drain electrode21, and the data line connected with the source electrode26. Then, a mask for forming the source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode can be used again in a one-stage patterning process to form the first bottom conductive layer311and the second bottom conductive layer311simultaneously. In the same time, the line width of the patterns can be controlled by adjusting the exposure process. As such, the first bottom conductive layer311can cover not only the entire top surface of the drain electrode21, but also all sidewalls of the drain electrode21. Similarly, the second bottom conductive layer312can cover not only the entire top surface of the source electrode26, but also all sidewalls of the source electrode26, and the data line connected to the source26as well.

In the conventional fabricating process for forming pixel units, the source electrode26of the transistor2and the data line connected with the source electrode26can be formed simultaneously by using a patterning process. A material of the data line contains metal aluminum, which is the same material contained in the source electrode26. However, the planarization layer4does not cover the data line. Therefore, the data line is exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the data line can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the data line in the same time, thereby resulting in a defect of the transistor2.

In the disclosed pixel unit, the second bottom conductive layer312can be formed to cover an entire top surface and all sidewalls of the source electrode26, as well as the data line connected with the source electrode26. As such, the electrochemical reaction between the metal aluminum of the data line and the metal silver of the metal layer32can be prevented. Therefore, the quality of the transistor2and the pixel electrode3can be ensured. Further, by repeatedly using the same single mask for patterning the he source electrode26and the drain electrode21of the transistor2, as well as the data line connected with the source electrode, the cost of mask can be reduced.

Referring toFIG. 8, a flow chart of another exemplary process for fabricating a pixel unit is shown in accordance with some other embodiments of the present disclosure. As illustrated, the step1022inFIG. 6can further include: forming a third bottom conductive layer (not shown in the figures). In some embodiments, the first bottom conductive layer311, the second bottom conductive layer312, and the third bottom conductive layer can be simultaneously formed by using a one-stage patterning process. The third bottom conductive layer can cover the gate line connected with the gate electrode24of the transistor2. A material of the third bottom conductive layer can be a transparent conductive material, such as Indium Tin Oxide (ITO).

Specifically, a conductive film can be formed on the transistor2, and a photoresist film can be coated on the conductive film. The conductive film coated by the photoresist film can be exposed, developed and etched to remove the excess conductive film. The remaining photoresist film can be peeled off. As such, the first bottom conductive layer311, the second bottom conductive layer311, and the third bottom conductive layer can be formed. In some other embodiments, the first bottom conductive layer311, the second bottom conductive layer312, and the third bottom conductive layer can be formed by using different patterning processes, which may be selected in accordance with the actual situation.

In the conventional fabricating process for forming pixel units, the gate electrode24of the transistor2and the gate line connected with the gate electrode24can be formed simultaneously by using a patterning process. A material of the gate line contains metal aluminum, which is the same material contained in the gate electrode24. However, the planarization layer4does not cover the gate line. Therefore, the gate line is exposed to the outside. During the patterning process to etch the metal layer32, the exposed metal aluminum of the gate line can react with the metal silver of the metal layer32due to the etching liquid. Therefore, the metal layer32can lost certain amount of metal silver, which may cause a defect of the pixel electrode3, and may cause a defect of the gate line in the same time, thereby resulting in a defect of the transistor2.

In the disclosed fabricating process, the third bottom conductive layer can be formed to cover the gate line connected with the gate electrode24. As such, the electrochemical reaction between the metal aluminum of the gate line and the metal silver of the metal layer32can be prevented. Therefore, the qualities of the transistor2and the pixel electrode3can be ensured.

It should be noted that, the contact area of the first bottom conductive layer311and the drain electrode21can be increased by covering the first bottom conductive layer311of the pixel electrode3on the drain electrode21. As such, the contact resistance can be reduced, the effective current can be enlarged, and the display device power consumption can be decreased. Since the contact area between the first bottom conductive layer311and the drain electrode21is increased, an adhesion force between the first bottom conductive layer311and the drain electrode21can be enhanced. Therefore, the first bottom conductive layer311can be prevented being dropping off from the drain electrode21due to a too small contact area.

In addition, in a fabricating process of the disclosed pixel unit, the first bottom conductive layer311of the pixel electrode3can be formed before farming the planarization layer4. And the metal layer32and the top conductive layer33of the pixel electrode3can be obtained by a one-stage patterning process on the planarization layer4. Comparing to the conventional fabricating process where the first bottom conductive layer311, the metal layer32and the top conductive layer33of the pixel electrode3are obtained by a one-stage patterning process after forming the planarization layer4, the disclosed fabricating process can reduce the number of layers to be etched on the planarization layer4. Therefore, during the etching process, the dimensions of the metal layer32and the top conductive layer33and the etching rate can be more desirably controlled.

Further, the disclosed pixel unit can include a first bottom conductive layer311, a second bottom conductive layer312and a third bottom conductive layer. The first bottom layer311can cover the entire top surface and all sidewalls of the drain electrode21. The second bottom layer312can cover the entire top surface and all sidewalls of the source electrode26, as well as a data line connected with the sauce electrode. The third bottom conductive layer can cover a gate line connected with the gate electrode. As such, the electrochemical reaction between the metal aluminum of the drain electrode21, source electrode26, data line, gate electrode24, as well as gate line, and the metal silver of the metal layer32can be prevented. Therefore, the quality of the transistor2and the pixel electrode3can be ensured.

It should be noted that, the above steps of the flow diagrams ofFIGS. 5-8can be executed or performed in any order or sequence not limited to the order and sequence shown and described in the present drawings. Also, some of the above steps of the flow diagrams ofFIGS. 5-8can be executed or per substantially simultaneously where appropriate or in parallel to reduce latency and processing times. Furthermore, it should be noted thatFIGS. 5-8are provided as an example only. At least some of the steps shown in the figures may be performed in a different order than represented, performed concurrently, or altogether omitted.

The provision of the examples described herein (as well as clauses phrased as “such as,” “e.g.,” “including,” and the like) should not be interpreted as limiting the claimed subject matter to the specific examples; rather, the examples are intended to illustrate only some of many possible aspects.

Accordingly, a pixel unit, an array substrate, and a display device, and their fabrication methods are provided.

Although the present disclosure has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of embodiment of the present disclosure can be made without departing from the spirit and scope of the present disclosure, which is only limited by the claims which follow. Features of the disclosed embodiments can be combined and rearranged in various ways. Without departing from the spirit and scope of the present disclosure, modifications, equivalents, or improvements to the present disclosure are understandable to those skilled in the art and are intended to be encompassed within the scope of the present disclosure.