Quasi-vertical structure for high voltage MOS device

A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Application Ser. No. 61/156,279 filed on Feb. 27, 2009, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments described herein relate generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to a MOS structure for high voltage operations.

BACKGROUND

Many metal—oxide—semiconductor field-effect transistors (MOSFET) designed for high voltage applications (with high breakdown voltage) have a vertical structure. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the n-epitaxial layer (“n-epi layer”) in the case of NMOS, while the current rating is a function of the channel width (i.e. the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the “silicon estate.” With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the n-epi layer thickness) is proportional to the breakdown voltage. Vertical MOSFETs are usually designed for switching applications. In general, NMOS is used instead of PMOS for many applications due to better performance given the same dimensions (because of higher mobility of electrons than holes).

In a conventional vertical NMOS, an n+ sinker is generally used for a vertical drain current collection.FIG. 1illustrates a cross-section of a conventional vertical NMOS with a p-substrate. The vertical NMOS has a p-substrate102, an n+ buried layer (NBL)104and an n-sinker108for a vertical drain current collection, an n-epi layer106, p-bodies110, source n+ regions112and p+ regions114both connected to the source contact116, a gate118, and a drain contact120. The n-sinker108requires a large lateral space122for isolation between the source116and the drain120. However, the required space122for the isolation will increase the device area and lead to an increased RDSon (drain to source resistance in on-state). In addition, the profile of the n-sinker108is hard to control because of different thermal budget. The n-sinker108is used as a vertical connection between NBL104and drain contact120. Since a high-energy implant step has its limitation in the implant depth, a larger thermal driver-in is required to push implant atoms deeper. In this kind of thermal, the n-sinker108receives a large thermal budget (temperature×hours) and results in an isotropic diffusion. Thus, the profile of n-sinker108becomes broader and deeper, which leads to a connection of NBL104with n-sinker108having an unwanted device area. Further, a multi-implant step is required for a deep n-sinker108. Therefore, the body of the n-sinker108will become broader than expectation and the body of n-sinker108occupies an extra device area.

FIG. 2illustrates a cross-section of another conventional vertical NMOS with a silicon-on-insulator (SOI) wafer. The NMOS has a p-substrate102, a buried oxide (BOX) layer202, n+ regions204connected to a drain contact120, an n-epi layer106, p-wells210, source n+ regions112and p+ regions114both connected to the source contact116, a gate118, and isolation oxide layers206and208. The oxide layers206and208provide pn-junction isolation and a higher break down voltage. The BOX layer202is also required for high voltage operation. Still, this structure requires a large lateral space122for isolation between the source116and the drain120.

Accordingly, new methods and structures to reduce the required device area and to have a high breakdown voltage for high-side operations are needed.

SUMMARY

Embodiments herein describe a metal-oxide-semiconductor (MOS) device structure for high breakdown voltage (BV) and low turn-on resistance RDSon in high voltage applications. Two general purposes are realized; one is to reduce device area and the other is to establish a high-side capable device. To reduce device area, drain current flows in a vertical direction and is collected by an n+ Buried Layer (NBL). A deep electrode (e.g. metal or polysilicon) surrounded by an insulator is connected to NBL for the drain current pickup. As a high dielectric strength insulator (e.g. oxide) is chosen, a smaller lateral space between source and drain can be achieved. The formation of the deep electrode, the insulator, and NBL, allows for a reduced device area and high-side operation.

In accordance with one embodiment, a semiconductor device includes a substrate, a buried n+ layer disposed in the substrate, an n-epi layer disposed over the buried n+ layer, p-well disposed in the n-epi layer, a source n+ region disposed in the p-well and connected to a source contact on one side, a first insulation layer disposed on top of the p-well and the n-epi layer, a gate disposed on top of the first insulation layer, and a metal electrode extending from the buried n+ layer to a drain contact, where the electrode is insulated from the n-epi layer and the p-well using a second insulation layer. The portion of the buried n+ layer contacting the metal electrode can be further n+ doped. The portion of the p-well adjacent to the source n+ region can be further p+ doped and connected to the source contact. The first insulation layer can be a high-voltage oxide layer. The second insulation layer can have a circular shape surrounding the metal electrode. The second insulation layer can be a dielectric layer, e.g. oxide. In another embodiment, a polysilicon electrode is used instead of the metal electrode.

In accordance with another embodiment, a method of fabricating a semiconductor device includes providing a semiconductor substrate, implanting a buried n+ layer on the substrate, forming an n-epi layer over the buried n+ layer, implanting a p-well in the n-epi layer, depositing a first insulation layer on top of the n-epi layer and the p-well where the first insulation layer covers only a specified area for a gate, forming the gate on top of the first insulation layer, implanting a source n+ region in the p-well, etching a trench in the n-epi layer and/or the p-well to expose the buried n+ layer and provide space for a drain electrode and an oxide insulation layer, depositing oxide in the trench, performing oxide Chemical-Mechanical Polishing (CMP), etching oxide in the trench to form a hole that extends to the buried n+ layer, implanting further an n+ region in the buried n+ layer exposed by the hole, and forming a drain electrode in the hole. The first insulation layer can be a high voltage oxide (HVOX) layer. The gate can be formed by performing polysilicon deposition and etching. In one embodiment, the drain electrode can be metal and formed by depositing and etching metal in the hole. In another embodiment, the drain electrode can be polysilicon and formed by depositing and etching polysilicon in the hole. The method can include implanting a p+ region adjoining the source n+ region in the p-well and providing a source contact connected to both the p+ region and the source n+ region.

Features of the disclosed embodiments include high operating voltage (e.g. in one embodiment, more than 700V was achieved), reduction of device area because of dielectric isolation (e.g. oxide), and a more robust breakdown voltage because of a stronger dielectric insulation (e.g. oxide) compared to silicon.

DETAILED DESCRIPTION

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the disclosed embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed are merely illustrative of specific ways to make and use the semiconductor device, and do not limit the scope of the device.

A metal-oxide-semiconductor (MOS) device structure for high breakdown voltage (BV) and low turn-on resistance RDSon in high voltage operations is provided. An embodiment of the structure and a method to fabricate the structure is provided, and the variations of the structure and method are also discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG. 3illustrates a cross-section of an example embodiment of a vertical NMOS device, and includes a deep electrode for vertical drain current collection. The vertical NMOS has a P-substrate102, an n+ buried layer (NBL)104, an n-epi layer106, p-wells210, source n+ regions112and p+ regions114both connected to the source contact116, a gate118, and a drain contact120. Also, there are deep electrodes302connected to the drain contact120for a vertical drain current collection, n+ regions306under the deep electrodes302to reduce contact resistance, and insulation layers304surrounding the deep electrodes302. The electrodes302can be implemented using metal or polysilicon, for example. The insulation layers304surrounding electrodes302can be dielectric material, e.g. oxide, and can be in a circular shape. The structure, including electrodes302and NBL104to collect vertical drain current, enable high-side operations.

In one embodiment, metal electrodes302and oxide insulation layer304enable high voltage operations of more than 700V. Also, because of a stronger oxide dielectric insulation layer304compared to silicon, a more robust breakdown voltage is possible. Further, the device area can be reduced because of the effective insulation using the insulation layer304surrounding electrodes302, because the lateral space122needed for isolation between the source116and the drain120reduced.

FIG. 4illustrates an example potential (voltage) distribution for the structure shown inFIG. 3, wherein electrodes302are metal and insulation layers304are oxide inFIG. 4. InFIG. 4, the p-substrate102, the source contact116, the gate118, and the p-wells210show relative low voltage close to the surface (top or bottom), about less than 100V. The potential (voltage) increases as the location in the cross section diagram moves close to the electrodes302, NBL104, and the drain contact120, to over 700V. The oxide insulation layer304, n-epi layer106, and p-substrate102show gradual variation of potential from less than 100V to over 700V, showing that the structure can sustain a high-side operation over 700V.

FIG. 5illustrates a flow diagram showing an exemplary process to fabricate one embodiment of the NMOS device. At step502, a semiconductor substrate (i.e. p-substrate102) is provided for fabrication of the MOS device. At step504, a buried n+ layer is implanted on the substrate to form the NBL104. At step506, an n-epi layer106is formed over the buried n+ layer104. At step508, a p-well210is implanted in the n-epi layer106. At step510, a first insulation layer308is deposited on top of the n-epi layer106and the p-well210, where the first insulation layer308covers only a specified area for a gate118. The first insulation layer308can be a high voltage oxide layer in one embodiment. At step512, the gate118is formed on top of the first insulation layer308. The gate308can be formed by performing polysilicon deposition and etching, for example. At step514, a source n+ region112is implanted in the p-well210. In one embodiment, a p+ region adjoining the source n+ region can be implanted to be connected to the source contact116together. At step516, a trench is etched in the n-epi layer106and/or the p-well210to expose the buried n+ layer104and provide space for the drain electrode302and an oxide insulation layer304that surrounds the electrode302. At step518, oxide is deposited in the trench to form an insulation layer304. At step520, oxide Chemical-Mechanical Polishing (CMP) is performed. In another embodiment, it is possible to use “etch-back method” instead of CMP, especially for breakdown voltages smaller than 500V. At step522, oxide in the trench is etched to form a hole that extends to the buried n+ layer to provide space for the electrode302. At step524, an n+ region306can be further implanted in the buried n+ layer exposed by the hole to improve the contact resistance of the electrode302to the buried n+ layer104. At step526, a drain electrode302is formed in the hole. The drain electrode302is one of metal and polysilicon, and it can be formed by depositing and etching metal or polysilicon.

FIG. 6illustrates example geometry of the structure shown inFIG. 3.FIG. 6shows a symmetric lateral length L1of the insulation layer304around the electrode302, the lateral length L2of the electrode302, and the height H1of the insulation layer304. The aspect ratio is the height (i.e. H1) over the lateral length (i.e. L1or L2). In this example, for a value of L1=24 um, the aspect ratio is 2.08-3.33 for a value of H1=50 um˜80 um. For the value of L2, 3 um-10 um is given in this example with an aspect ratio of 10˜20. The aspect ratio can depend upon the etching capability in the process, e.g. the depth and precision that a deep trench can be etched for a small area.

Features of the disclosed embodiments include high operating voltage (e.g. in one embodiment, more than 700V was achieved), reduction of device area because of dielectric isolation (e.g. oxide), and a more robust breakdown voltage because of a stronger dielectric insulation (e.g. oxide) compared to silicon.