Damascene oxygen barrier and hydrogen barrier for ferroelectric random-access memory

Disclosed herein is an apparatus that includes a ferroelectric capacitor disposed on a damascene barrier film, and fabrication methods thereof. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with the oxygen barrier being in contact with a bottom surface of the ferroelectric capacitor. Other embodiments are also disclosed herein.

TECHNICAL FIELD

Embodiments described herein relate to semiconductor devices, and more particularly to the fabrication of ferroelectric random-access memory devices.

BACKGROUND

Ferroelectric random-access memories (FRAM) typically include a grid or an array of storage elements or cells, each including at least one ferroelectric capacitor and one or more associated transistors to select the cell and control reading or writing thereto. When an external electric field is applied across a ferroelectric material of a ferroelectric capacitor in the cell, dipoles in the material align with the field direction. After the electric field is removed, the dipoles retain their polarization state. Data is stored in the cells as one of two possible electric polarizations in each data storage cell. For example, in a one transistor-one capacitor (1T1C) cell, a “1” may be encoded using a negative remnant polarization, and a “0” may be encoded using a positive remnant polarization.

The ferroelectric capacitor (“ferrocapacitor”) in an FRAM cell typically includes a ferroelectric material, such as lead zirconate titanate (PZT) between an upper electrode and a lower electrode. The transistors in the cells are typically metal-oxide-semiconductor (MOS) transistors fabricated using a standard or baseline complementary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting, and dielectric materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure that the resultant MOS transistors function properly. Materials and processes typically used to fabricate the ferroelectric capacitor differ significantly from those of the baseline CMOS process flow, and can detrimentally impact the MOS transistors.

Moreover, stringent design rules may be utilized when fabricating interconnect layers to interface the ferroelectric components with CMOS layers, as the potential for defects and errors in the manufacturing process (e.g., misalignments, incomplete etching steps, etc.) increases with the number of subsequent processing steps.

DETAILED DESCRIPTION

Non-volatile memory cells including CMOS transistors and embedded ferroelectric capacitors formed according to methods of the present disclosure include damascene hydrogen and oxygen barrier films (or damascene barrier films) into the devices during fabrication reduce defects introduced by misalignment of metal contacts as well as reduce vertical dimensions of the ferroelectric capacitors.

In one embodiment, an apparatus includes a damascene barrier film having a first upper surface and a first lower surface. The damascene barrier film includes a hydrogen barrier region and a first oxygen barrier region. A ferrocapacitor, having a top surface, a bottom surface, and at least one sidewall, is disposed on the first upper surface of the damascene barrier film such that the lower surface of the ferrocapacitor is in contact with the first oxygen barrier region. A hydrogen barrier film is disposed along the at least one sidewall of the ferrocapacitor and at least a first portion of the upper surface of the ferrocapacitor. In some embodiments, the lower surface of the ferrocapacitor is in further contact with the hydrogen barrier region. In other embodiments, the lower surface of the ferrocapacitor fully contacts the first oxygen barrier region without contacting the hydrogen barrier region.

In another embodiment, a method includes forming a damascene barrier film disposed above a gate level layer, the damascene barrier film including a hydrogen barrier region and a first oxygen barrier region. The method further includes forming a ferrocapacitor on the damascene barrier film such that a lower surface of the ferrocapacitor contacts the first oxygen barrier region.

Embodiments of an FRAM cell including a damascene barrier film are described herein with reference to figures. Specifically, the damascene barrier film may be disposed below one or more ferrocapacitors within a dielectric layer. By incorporating an oxygen barrier region within the damascene barrier film, an individual oxygen barrier layer may be eliminated during the deposition of a ferrocapacitor stack when forming the ferrocapacitor. Moreover, pre-forming the oxygen barrier layer in this way allows for a decrease in height of the ferrocapacitor. This in turn reduces a total etch time when forming the ferrocapacitor, thus reducing the amount of etching experienced by the topmost layer of the ferrocapacitor while also eliminating defects that may arise due to incomplete etching (e.g., such as conductive oxygen barrier residues that can potentially create electrical shorting). Moreover, the damascene barrier film may also serve to eliminate defects that arise from misaligned metal contacts, by providing a large area interconnect region between metal contacts from different layers. It is noted that particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and apparatuses.

As used herein, the term “damascene barrier film” refers to a barrier film formed using a damascene process, resulting in a barrier film having a first barrier material that fills gaps or trenches previously formed in a second barrier material.

An embodiment of an apparatus including FRAM cells having a damascene barrier film, and a method of fabricating and integrating such ferroelectric capacitors into a standard or baseline CMOS process flow will now be described in detail with reference toFIG. 1andFIGS. 2A-2K.FIG. 1is a flow diagram illustrating a method for fabricating FRAM cells according to one embodiment of the present invention.FIGS. 2A-2Killustrate cross sectional views of portions of an FRAM cell during the fabrication thereof according to one embodiment of the present invention.

Referring toFIG. 1andFIGS. 2A-2C, the process begins at block102in which openings228aand228bare formed in an inter-metal dielectric or first dielectric layer204after formation of an underlying gate level layer206on a surface208of a substrate202. Additional openings may also be formed. As illustrated inFIG. 2Aprior to forming the openings228aand228b, the gate level includes gate stacks of one or more metal-oxide-semiconductor (MOS) transistors210,212,214separated by, or located above, one or more isolation structures216. The first dielectric layer204overlays the MOS transistors210,212,214. In addition to a source and a drain, diffusion regions220can also include a channel region. Generally, the substrate202and, hence, diffusion regions220, may be composed of any material suitable for semiconductor device fabrication. In one embodiment, the substrate202is a bulk substrate composed of a single crystal of a material which may include one or more of, but is not limited to, silicon, germanium, silicon-germanium, or an III-V compound semiconductor material. In another embodiment, the substrate202includes a bulk layer with a top epitaxial layer. In another embodiment, a bulk layer is composed of a single crystal of a material which may include one or more of, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material, or quartz, while a top epitaxial layer is composed of a single crystal layer which may include one or more of, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. The top epitaxial layer may be composed of a single crystal layer which may include one or more of, but is not limited to, silicon (i.e., to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, silicon-germanium, or an III-V compound semiconductor material. An insulator layer may be composed of a material which may include one or more of, but is not limited to, silicon dioxide, silicon nitride, or silicon oxy-nitride. A lower portion of the bulk layer may be composed of a single crystal which may include one or more of, but is not limited to, silicon, germanium, silicon-germanium, an III-V compound semiconductor material, or quartz. Alternatively, the substrate202, bulk layer, top epitaxial layer and the insulator material may be composed of other materials.

The substrate202and, hence, the channel region, may include dopant impurity atoms. In one embodiment, the channel region is doped P-type silicon and, and in another embodiment, the channel region is doped N-type silicon. Source and drain diffusion regions220in the substrate202have opposite conductivity to the channel region. For example, in one embodiment, the substrate202and, hence, the channel region, is composed of boron-doped single-crystal silicon having a boron concentration in the range of 1×1015atoms/cm3to 1×1019atoms/cm3. Source and drain diffusion regions220may be composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5×1016atoms/cm3to 5×1019atoms/cm3. Generally, source and drain diffusion regions220have a depth in the substrate202in the range of 80 nanometers to 200 nanometers. In accordance with an alternative embodiment of the present disclosure, source and drain diffusion regions220are P-type doped regions while the substrate202and channel region is an N-type doped region.

The MOS transistor214may include a gate oxide222formed on the surface208of the substrate202, a gate layer224formed on the gate oxide222, and one or more sidewall spacers226isolating the gate layer224from the first dielectric layer204. Additionally, it is to be understood by those skilled in the art that the gate layer224is generally electrically coupled to an overlying local interconnect, which is described in more detail below.

The first dielectric layer204can include a single layer of dielectric material or multiple layers of dielectric material. For example, in one embodiment the first dielectric layer204includes a lower or bottom first dielectric layer204a, which may include phosphosilicate glass (PSG) formed or deposited by a chemical vapor deposition (CVD) process, such as plasma or low pressure or atmospheric CVD. The first dielectric layer204may also include an upper or top first dielectric layer204b, which may include a silicon oxide deposited by low pressure CVD (LPCVD) using tetraethyl-orthosilicate (TEOS) based process gas or precursors. Alternatively, other deposition chemistries may be used.

Referring back toFIG. 1and toFIG. 2B, the openings228aand228bmay be formed by performing a contact etch to etch the first dielectric layer204and expose the underlying diffusion regions220. The contact etch can be accomplished using standard photolithographic techniques and any suitable wet or dry etching chemistry for etching a silicon oxide and/or PSG. Suitable contact etch chemistries can include, for example, wet etching using hydrofluoric acid (HF), or gas phase etching (GPE) using a reactive ion etch (RIE) process gas. Alternatively, other contact etch chemistries may be used.

Referring back toFIG. 1and toFIG. 2C, the openings228aand228bformed in the first dielectric layer204are filled with a metal (typically a refractory metal) to form lower metal contacts230aand230b. The term “refractory metal” refers to a metal of elements of the groups4,5and6of the periodic table, including titanium (Ti), tantalum (Ta), tungsten (W), and nitrides or alloys thereof, which are resistant to high temperatures. The metal can be deposited, for example, by physical vapor deposition (PVD), such as sputtering or evaporation, or by CVD and electroless plating. After metal deposition, the lower metal contacts230aand230band the upper surface218of the first dielectric layer204are planarized, for example, using a chemical mechanical polishing (CMP) process, resulting in planarized surfaces231aand231bof the lower metal contacts230aand230b, respectively, and a planarized upper surface218of the first dielectric layer204.

Referring toFIG. 1andFIG. 2D, at block104, one, two, or more layers of a hydrogen (H2) barrier film232is deposited onto the upper surface218and the surfaces231aand231bof the lower metal contacts230aand230b, respectively. The hydrogen barrier film232can include a single material layer, or multiple material layers, and can have an overall thickness ranging from, for example, 50 nanometers to 200 nanometers. In one embodiment, the hydrogen barrier film232may include one or more layers of aluminum oxide (Al2O3), which may be deposited by ALD or PVD. In one embodiment, the hydrogen barrier film232may include one or more layers of silicon nitride (SiN), which may be deposited by CVD or ALD. Alternatively, other techniques may be used to deposit the one or more layers of the hydrogen barrier film232.

Referring toFIG. 1andFIG. 2E, trenches234aand234bare etched through the hydrogen barrier film232, revealing planarized surfaces231aand231bof the lower metal contacts230aand230b, respectively. In one embodiment, the trenches234aand234bare etched using standard photolithographic and contact etching techniques (e.g., using an inverse mask), followed by treatment with an etch chemistry composed of carbon-monoxide (CO), argon (Ar), octafluorocyclobutane (C4F8) or Freon® 318, and, optionally, nitrogen (N2). In some embodiments, other etch chemistries may be used.

Referring toFIG. 1andFIG. 2F, at block106, one or more layers of an oxygen barrier film are deposited, filling the trenches234aand234bof the hydrogen barrier film232. In one embodiment, the oxygen barrier film can include one or more a layers of titanium aluminum nitride (TiAlN) and/or one or more layers of a different material. The oxygen barrier film may be deposited or formed using any suitable deposition method, such as CVD, atomic layer deposition (ALD), or PVD. After the oxygen barrier film has been deposited, the oxygen barrier film is planarized using, for example, a CMP process. The planarization may be performed until the oxygen barrier film disposed above the hydrogen barrier film232is removed, leaving behind oxygen barrier regions236aand236bwithin the trenches234aand234b, respectively. In one embodiment, the planarization may be performed until at least an upper portion of the hydrogen barrier film232is removed. The result of the planarization may be referred to as a damascene barrier film237, which includes oxygen barrier regions236aand236band a hydrogen barrier region defined by a remaining portion of the hydrogen barrier film232, which collectively define an upper surface237aand a lower surface237bof the damascene barrier film237. In one embodiment, the oxygen barrier regions236aand236beach have widths270aand270b, respectively, ranging from 0.1 to 1 micrometer. In one embodiment, the oxygen barrier regions236aand236bmay be sized to match respective widths of the top portions of the lower metal contacts230aand230b. In another embodiment, the oxygen barrier regions236aand236bmay be sized to be wider than the top portions of the lower metal contacts230aand230b. In one embodiment, a thickness of the damascene barrier film237is at least partially controlled by the planarization process.

Referring toFIG. 1andFIG. 2G, at block108, layers of a ferro stack, from which one or more ferroelectric capacitors will be formed, are deposited or formed over the planarized damascene barrier film237. Generally, the ferro stack layers include a layer of a ferroelectric material, such as a lead zirconate titanate (PZT) ferroelectric layer240, between a top electrode242and bottom electrode238in electrical contact with or electrically coupled to one of the underlying lower metal contacts230aand230bvia the oxygen barrier regions236aand236b, respectively. In some embodiments, the oxygen barrier regions236aand236bmay be sized such that each is substantially the same width as the other. In other embodiments, the oxygen barrier regions236aand236bmay be sized such that the oxygen barrier region236ais wider than the oxygen barrier region236b. In one embodiment, the top electrode242is a multi-layer top electrode including, for example, a lower layer242aof iridium oxide (IrO2) in contact with the PZT ferroelectric layer240and an upper layer242bof iridium (Ir) overlying the lower layer242aof the top electrode242. The PZT ferroelectric layer240is deposited on the bottom electrode238to a thickness ranging from, for example, 0.04 micrometers to 0.30 micrometers using MOCVD, ALD, or PVD. A hard mask244may be formed over the ferro stack layers. The hard mask244can include, for example, a layer of titanium aluminum nitride (TiAlN) having a thickness ranging from 0.1 micrometers to 0.4 micrometers, and can be deposited or formed using PVD. In certain embodiments, the hard mask244can include multiple layers and the material of the hard mask may be selected to form a conductive hydrogen (H2) barrier. Alternatively, other materials and methods may be used to fabricate the ferro stack layers.

Referring toFIG. 1andFIG. 2H, at block110, the ferro stack layers may be patterned by first patterning the hard mask244and then using standard etching technologies, such as standard metal etch chemistries, to define a ferrocapacitor246. The ferrocapacitor246includes a bottom electrode238(which is electrically coupled to the lower metal contact230a), a PZT ferroelectric layer240, a top electrode242, and a hard mask244, each of which correspond to their counterpart ferro stack layers described with respect toFIG. 2G. A top surface247of the ferrocapacitor246corresponds to an upper surface of the hard mask244, and a bottom surface249of the ferrocapacitor246contacts the upper surface237aof the damascene barrier film237such that the bottom surface249contacts the oxygen barrier region236a, as illustrated inFIG. 2H. In such embodiments, when the oxygen barrier region236ais narrower than the ferrocapacitor246(e.g., such that the bottom surface249of the ferrocapacitor246contacts the oxygen barrier region236aand the hydrogen barrier film232), this allows for design rules that may impose a minimum spatial separation between oxygen barrier regions236a,236bto be relaxed, thus allowing for a greater density of ferrocapacitors per FRAM cell. In other embodiments, the oxygen barrier region236ais sized to be wider than the ferrocapacitor246such that the bottom surface249of the ferrocapacitor246fully contacts the oxygen barrier region236awithout contacting the hydrogen barrier film232, or such that the bottom surface249of the ferrocapacitor246at least partially contacts the oxygen barrier region236aand the hydrogen barrier film232(e.g., if the ferrocapacitor246is misaligned with respect to the oxygen barrier region236a). In other embodiments, the oxygen barrier region236ais the same width as the bottom surface249of the ferrocapacitor246.

The ferrocapacitor246also includes one or more sidewalls248that run from the top surface247to the bottom surface249. In one embodiment, the one or more sidewalls248are slanted with respect to the upper surface237aof the damascene barrier film237. In one embodiment, the ferrocapacitor246may be a round structure (e.g., a cylinder, a tapered cylinder, etc.) in which the sidewall248defines a circumference of the ferrocapacitor246. In one embodiment, the ferrocapacitor246may be multi-walled of various shape (e.g., a cube, a trapezoid, an elongated cube, an elongated trapezoid, etc.) having multiple sidewalls240athat define a perimeter. Alternatively, the ferrocapacitor246may have different shapes. It is noted that the ferrocapacitor246is illustrative, and that any suitable number of ferrocapacitors may be fabricated in accordance with the present embodiments. Moreover, each may be fabricated to have any suitable dimensions and/or shapes. In one embodiment, a height275of the ferrocapacitor246(e.g., as measured from the upper surface237aof the damascene barrier film237to the top surface247of the ferrocapacitor246) ranges from 0.2 micrometers to 0.5 micrometers.

Referring toFIG. 1andFIG. 2I, at block112, one, two, or more layers of a hydrogen (H2) barrier film250are deposited, the hydrogen barrier film250having an outer surface251aand an inner surface251b, such that the inner surface251bof the hydrogen barrier film250contacts the top surface247and one or more sidewalls248of the ferrocapacitor246and the upper surface237aof the damascene barrier film237, encapsulating the ferrocapacitor between the hydrogen barrier film250and the damascene barrier film237. Encapsulating the ferrocapacitor246in this way can prevent degradation that can occur when hydrogen is introduced during subsequent processing. The hydrogen barrier film250can include a single material layer, or multiple material layers, and can have an overall thickness280ranging from, for example, 10 nanometers to 130 nanometers. In one embodiment, the hydrogen barrier film250can include a lower or first hydrogen encapsulation layer250aof aluminum oxide (Al2O3) having a thickness ranging from, for example, 5 nanometers to 30 nanometers, and may be deposited by ALD or PVD, and an upper or second hydrogen encapsulation layer250bof silicon nitride (SiN) having a thickness ranging from, for example, 5 nanometers to 100 nanometers, and may be deposited by CVD or ALD. Alternatively, other techniques may be used to deposit the hydrogen barrier film250.

After deposing the hydrogen barrier film250, a second dielectric layer, referred to as an inter-level dielectric (ILD) layer252, is deposited or formed over the hydrogen barrier film250. The ILD layer252can include one or more layers of an undoped oxide, such as silicon-dioxide (SiO2), a nitride, such as silicon nitride (SixNy), a silicon-oxynitride (SixOyNz) or, as with the first dielectric layer204described above, an oxide, such as phosphosilicate glass (PSG). In one embodiment, the ILD layer252may include a lower layer252a, which may be deposited by, for example, LPCVD using TEOS. Once the lower layer252ais formed, an upper surface of the lower layer252amay be planarized using, for example, a CMP process, resulting in a thickness of the lower layer252athat ranges from 0.5 micrometers to 0.9 micrometers. In one embodiment, the ILD layer252may include an upper layer252b, which may be deposited onto the lower layer252aby, for example, LPCVD using TEOS. A thickness of the upper layer252bmay range from 0.1 micrometers to 0.4 micrometers.

Referring toFIG. 1andFIG. 2J, at block114, openings for upper metal contacts254aand254bare etched through the ILD layer252and hydrogen barrier film250using standard photolithographic and contact etching techniques. For example, for an SiO2ILD layer, a suitable contact etching technique can include forming a patterned photoresist layer on the upper surface of the ILD layer and etching the ILD layer with an etch chemistry comprising carbon-monoxide (CO), argon (Ar), octafluorocyclobutane (C4F8) or Freon® 318, and, optionally, nitrogen (N2). The opening for the upper metal contact254areveals the hard mask244and allow for electrical coupling of the top electrode242of the ferrocapacitor246to upper metal contact254a. The opening for the upper metal contact254bpasses through the hydrogen barrier film250to reveal the second oxygen barrier region236bof the damascene barrier film237. The second oxygen barrier region236bprovides protection against oxygen diffusion during processing steps, and also serves as a “landing pad” for the upper metal contact254to provide electrical coupling to the lower metal contact202bshould the metal contacts be misaligned resulting from a manufacturing defect.

As with the lower metal contacts230aand230bdescribed above, the upper metal contacts254aand254bmay be formed in the ILD layer252by filling the openings with a refractory metal, such as titanium (Ti), tantalum (Ta), tungsten (W), and nitrides or alloys thereof, by physical vapor deposition, such as sputtering, evaporation, or CVD. After forming the upper metal contacts254aand254b, upper surfaces of the upper metal contacts254aand254bmay be planarized using, for example, a CMP process.

The upper metal contacts254aand254belectrically couple any additional upper layers added downstream in the processing (e.g., by performing subsequent processing steps) and the gate level layer206below. The upper metal contact254adirectly contacts the hard mask244of the ferrocapacitor246. The upper metal contact254bconnects directly to the lower metal contact230bof the gate level layer206via the oxygen barrier region236bof the damascene barrier film237. The upper metal contacts254aand254bmay be wider at their upper portions than at their lower portions, which may be an artifact of the ILD etching process. Widths275aand275bof the upper portions of the upper metal contacts254aand254b, respectively, are defined by a lithographic process used to etch the openings in the ILD layer252. The widths275aand275bmay each range from 65 nanometers to 200 nanometers.

Referring toFIG. 1andFIG. 2K, at block116, additional processing steps may be performed. For example, metal contacts256a,256b,256c,256d, and258may be formed to provide additional connectivity within the FRAM cell.

FIG. 3illustrates a local interconnect layer formed according to one embodiment of the present invention. The structure depicted inFIG. 3may have been fabricated in a similar fashion as that ofFIG. 2, except that additional oxygen barrier regions360aand360bhave been included in order to define local interconnects. For example, blocks104and106may be modified to further allow for etching of additional trenches for which oxygen barrier regions360aand360bmay be deposited. Accordingly,FIG. 3depicts a structure having a ferrocapacitor346with a hydrogen barrier film350disposed thereon. A damascene barrier film337includes oxygen barrier regions336aand336b, as well as the oxygen barrier regions360aand360bthat define the local interconnects. Each of these components may be the same or similar to their identically named counterparts described with respect toFIGS. 1 and 2. It is noted that the inclusion of local interconnects, as defined by the oxygen barrier regions336aand336b, is compatible with all of the embodiments described herein.

FIG. 4illustrates a multi-layered damascene barrier film formed according to one embodiment of the present invention. The structure depicted inFIG. 4may have been fabricated in a similar fashion as that ofFIGS. 2 and 3, except that a damascene barrier film437includes a multi-layered hydrogen barrier film having a lower hydrogen barrier layer437aand an upper hydrogen barrier layer437b. Accordingly,FIG. 4depicts a structure having a ferrocapacitor446with a hydrogen barrier film450disposed thereon. The damascene barrier film437includes the lower hydrogen barrier layer437a, the upper hydrogen barrier layer437b, oxygen barrier regions436aand436b, and oxygen barrier regions460aand460bthat define local interconnects. Each of these components may be the same or similar to their identically named counterparts described with respect toFIGS. 1-3. It is noted that the inclusion of one, two, or more hydrogen barrier layers within a hydrogen barrier film is compatible with all of the embodiments described herein.

FIG. 5illustrates a damascene barrier film formed within an oxide film according to one embodiment of the present invention. The structure depicted inFIG. 5may have been fabricated in a similar fashion as that ofFIGS. 2-4, except that an upper oxide layer504bhas been modified to serve as a damascene barrier film. For example, blocks102and106may be modified to further allow for etching of trenches within the upper oxide layer504bin which oxygen barrier regions360aand360bmay be deposited, with blocks104being omitted to eliminate the hydrogen barrier film. Accordingly,FIG. 5depicts a structure having a ferrocapacitor546with a hydrogen barrier film550disposed thereon. The upper oxide layer504bis disposed on a lower oxide layer504a, with the upper oxide layer504bdefining a damascene barrier film that includes oxygen barrier regions536aand536b, and oxygen barrier regions560aand560bthat define local interconnects. Each of these components may be the same or similar to their identically named counterparts described with respect toFIGS. 1 and 2. In one embodiment, the lower metal contacts are formed prior to depositing the upper oxide layer504b. In one embodiment, the upper oxide layer504bis composed of a material that is suitable for serving as a hydrogen barrier (e.g., silicon nitride).

FIGS. 6A and 6Billustrate a processing defect formed in an FRAM cell. As shown inFIG. 6A, lower metal contacts602aand602bare formed through a lower604aand upper604boxide layer. In some scenarios, planarization may result in depressed surfaces603aand603bof the lower metal contacts602aand602b, respectively. The depressed surfaces603aand603bmay result in downstream defects in the FRAM cell if a damascene barrier film is not included. As shown inFIG. 6B, a ferrocapacitor646includes five layers: an oxygen barrier636, a bottom electrode638, a ferroelectric layer640, a top electrode642, and a hard mask644. The depressed surface603aintroduces a defect that propagates through each of the layers of the ferrocapacitor646, resulting in a deformed ferrocapacitor646that may demonstrate diminished and/or unpredictable performance during operation of the FRAM cell.

FIGS. 6C and 6Dillustrate prevention of a processing defect in an FRAM cell formed according to one embodiment of the present invention. As shown inFIG. 6A, lower metal contacts652aand652bare formed through a lower654aand upper654boxide layer. By including a damascene barrier film defined by, for example, a hydrogen barrier film (or portion)660and oxygen barrier regions662aand662b, defects resulting from planarization of the lower metal contacts652aand652bcan be mitigated.

Thus, embodiments of FRAM cells that include damascene barrier films have been presented herein. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

The terms “above,” “under,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer deposited or disposed above or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming the initial disk is a starting substrate and the subsequent processing deposits, modifies and removes films from the substrate without consideration of the absolute orientation of the substrate. Thus, a film that is deposited on both sides of a substrate is “over” both sides of the substrate.

In the foregoing description, numerous specific details are set forth, such as specific materials, dimensions, processes parameters, etc., to provide a thorough understanding of the present invention. In some instances, well-known semiconductor design and fabrication techniques have not been described in particular detail to avoid unnecessarily obscuring the present invention. Reference throughout this specification to “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

The present invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader scope of the embodiments of the invention as set for in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.