Execution circuitry for floating-point power operation

Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating-point power instruction to evaluate the power function xy as 2y logx. In some embodiments, base-2 logarithm circuitry is configured to evaluate a base-2 logarithm for a first input (e.g., log2 x) by determining coefficients for a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, multiplication circuitry multiplies the base-2 logarithm result by a second input to generate a multiplication result. In some embodiments, base-2 power function circuitry is configured to evaluate a base-2 power function for the multiplication result. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, relative to traditional techniques.

BACKGROUND

Technical Field

This disclosure relates generally to computer processors and more particularly to floating-point circuitry.

Description of the Related Art

Complex functions are often executed in computer processors for various applications such as numeric computations, graphics processing, machine learning algorithms, display processing, etc. Generally speaking, computer processors perform many common operations such as multiplication and addition using dedicated circuitry. However, certain more complex operations (such as the power function xy, exponent function, and logarithm function for example) are typically implemented using software libraries with multiple instructions. It may be challenging to implement such operations in hardware with acceptable circuit area and desired accuracy.

DETAILED DESCRIPTION

Common compute functions such as multiplication and addition typically utilize dedicated circuitry to generate floating-point results. For more complex functions such as the power function, however, traditional techniques utilize software libraries, e.g., due to accuracy and area constraints. Speaking generally, disclosed dedicated power function circuitry may substantially increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy for a range of input values, relative to traditional techniques.

In some embodiments, execution circuitry is configured to execute a single floating-point power instruction to evaluate the power function, xy=2y log2x. Executing a single instruction for the power function may have various performance benefits relative to executing multiple instructions of a software library. Further, disclosed circuitry may implement various techniques to maintain an accuracy target.

For example, in some embodiments, execution hardware approximates the power function in three steps, including performing a base-2 logarithm approximation for the first input (e.g., log2x), multiplying the base-2 logarithm approximation result by the second input (e.g., y×log2x), and performing a base-2 power function approximation based on the multiplication result (e.g., 2y log2x).

In some embodiments, discussed in detail below, as part of the base-2 logarithm approximation, execution circuitry determines coefficients for a polynomial function and evaluates the polynomial function using the determined coefficients and the x input to generate a result. This operation may use head-tail arithmetic to improve accuracy relative to using the initial input format (e.g., a 32-bit floating-point format) without the circuit area associated with operations in a higher-precision format (e.g., associated with multiplications in a 64-bit floating-point format). Generally, using head-tail arithmetic may reduce rounding errors, assisting in the tradeoff between accuracy and area considerations mentioned above. Further, the base-2 logarithm circuitry may be configured using overlapping intervals when determining coefficients (e.g., using a lookup table), which may reduce error (which typically may be greatest near the edges of a given interval).

Multiplication circuitry may also perform the multiplication operation using head-tail arithmetic. In some embodiments, discussed in detail below, execution circuitry generates a power function result by approximating a base-2 power function based on the multiplication result (and the base-2 power function may also use polynomial approximation).

Note that dedicated power function circuitry, in addition to the performance benefits listed above, may advantageously provide intermediate results utilized by other functions (e.g., a base-2 logarithm result or base-2 power result used as an activation function for a machine learning application) with little to no increases in circuit area. This may reduce power consumption and improve performance for those functions as well.

Example Execution Circuitry

FIG.1is a block diagram illustrating example execution circuitry, according to some embodiments. In the illustrated embodiment, execution circuitry100includes base-2 logarithm circuitry110, multiplication circuitry120, and base-2 power function circuitry130.

In some embodiments, execution circuitry100evaluates a floating-point power function by generating an approximation of a base-2 logarithm for a first input, multiplying the result of the base-2 logarithm approximation by a second input, and generating an approximation of a base-2 power function for a multiplication result.

In the illustrated embodiment, base-2 logarithm circuitry110is configured to evaluate a base-2 logarithm based on an input operand x, e.g., log2x. In some embodiments, base-2 logarithm circuitry110may perform various operations, as discussed in detail below with respect toFIGS.4and5, including the following: argument shift, floating-point conversion, polynomial approximation, head-tail arithmetic addition, etc.

In some embodiments, base-2 logarithm circuitry evaluates the base-2 logarithm of the input operand x by determining coefficients for a polynomial function, based on the input operand x, and evaluating the polynomial function to determine a base-2 logarithm result based on the determined coefficients and the input operand x. In some embodiments, discussed in detail below with respect toFIG.3, the base-2 logarithm result evaluated by base-2 logarithm circuitry may include a head component and a tail component for head-tail arithmetic.

In some embodiments, head-tail arithmetic is used to generate a greater precision result such that rounding error does not become unacceptable in a later stage (e.g., in the multiplication operation performed by multiplication circuitry120). As understood by those of skill in the art, head-tail arithmetic represents a higher precision number using two components of lower precision and operates on the two components individually. This approach may advantageously maintain precision without the need to increase the width of certain circuit elements (e.g., multiplier, adder, etc.), which might more substantially impact area considerations, power consumption, etc. Note that in some embodiments, head-tail operations may utilize more than two portions of a given operand, e.g., with a middle portion for three total portions, four total portions, etc., with similar separate operations and subsequent conversion to a more traditional format.

In some embodiments, input operand x is provided in a first floating-point format to base-2 logarithm circuitry110. As one example, input operand x may be represented using the IEEE standard single precision floating-point format, which represents a floating-point number using 32 bits. In some embodiments, the head and tail components use less than or equal to the number of bits of the input operand x.

In the illustrated embodiment, multiplication circuitry120is configured to perform a multiplication operation between the base-2 logarithm result generated by base-2 logarithm circuitry110and input operand y, to generate a multiplication result y×log2x. In some embodiments, discussed in detail below with respect toFIG.3, the multiplication operation may be a head-tail operation and the multiplication result may include a multiplication head result and a multiplication tail result.

In the illustrated embodiment, base-2 power function circuitry130is configured to evaluate two to the power of a representation of the multiplication result to generate a result of the floating-point instruction in the first floating-point format. The representation of the multiplication result may be the output of converting a head-tail multiplication result to a non-head-tail format, for example. In these embodiments, base-2 power function circuitry130is not configured to perform head-tail arithmetic.

Example Pipeline

FIG.2is a block diagram illustrating an example pipeline, according to some embodiments. In the illustrated embodiment, the example pipeline illustrates multiple elements including fetch stage210, decode stage220, dispatch stage230, and execution circuitry100. While the illustrated stages are included for purposes of illustration, a given pipeline may include various other stages or may omit illustrated stages, in other embodiments. Further, one or more illustrated elements may themselves be pipelined (e.g., execution circuitry100may include multiple stages).

The concept of a processor “pipeline” is well understood, and refers to the concept of splitting the “work” a processor performs on instructions into multiple stages. In some embodiments, instruction decode, dispatch, execution (i.e., performance), and retirement may be examples of different pipeline stages. Many different pipeline architectures are possible with varying orderings of elements/portions. Various pipeline stages perform such steps on an instruction during one or more processor clock cycles, then pass the instruction or operations associated with the instruction on to other stages for further processing.

Fetch stage circuitry210, in some embodiments, is configured to fetch instructions for execution, including instructions that specify to evaluate a floating-point power function. In some embodiments, a floating-point power instruction may be a single instruction-set-architecture (ISA) instruction. In some embodiments, a floating-point power instruction may be a single micro-operation supported by the processor. In other embodiments, a single floating-point power instruction may be implemented using multiple micro-operations. Note that in other embodiments, multiple instructions (e.g., two or three) may be used to implement the floating-point power operation. Generally, however, the ability to perform the power operation with dedicated hardware support and a limited number of instructions may improve throughput of power operations, with the single-instruction implementation providing the most throughput.

In some embodiments, disclosed techniques may allow fetch stage circuitry210to fetch a floating-point power instruction every cycle, which may substantially increase throughput relative to software-based techniques.

Decode stage circuitry220, in the illustrated embodiment, is configured to decode the fetched instruction from stage210. In some embodiments, decode220prepares the fetched instruction for further processing such as by inspecting opcodes of the fetch instruction and determining locations of source and destination operands, for example.

Dispatch stage circuitry230, in some embodiments, is configured to dispatch operations to reservation stations (not shown) within various execution units of pipeline circuitry, according to some embodiments.

In the illustrated embodiment, execution circuitry100is configured to evaluate a floating-point power function. In some embodiments, this includes evaluating a base-2 logarithm, performing a multiplication operation, and evaluating a base-2 power function, as discussed in detail below with respect toFIG.3. Note that execution circuitry100may also include various other units, e.g., an integer unit, a load/store unit, etc. Various units of execution circuitry100may be pipelined.

Detailed Execution Circuitry

FIG.3is a block diagram illustrating detailed example execution circuitry, according to some embodiments. In the illustrated embodiment, execution circuitry100includes base-2 logarithm circuitry110, base-2 power function circuitry130, exception control circuitry310, and various other circuit elements (e.g., a multiplier320, multiplexors330,340,350, and360, etc.).

In the illustrated embodiment, execution circuitry100is configured to execute a single floating-point power instruction to generate a power function result. In some embodiments, execution circuitry100receives input operand x, input operand y, and a function input. In some embodiments, input operands x and y are provided in a first floating-point format (e.g., N-bit floating-point format).

In some embodiments, the function input is based on the type of instruction being executed and specifies whether an intermediary result is to be provided, e.g., using results evaluated by base-2 logarithm circuitry110or base-2 power function circuitry130. Thus, portions the disclosed hardware configured to execute the power function instruction may also be advantageously used to execute other types of instructions, e.g., by selecting intermediate results.

In the illustrated embodiment, base-2 logarithm circuitry110evaluates the base-2 logarithm for input operand x. In some embodiments, this includes determining coefficients for a polynomial function based on input operand x and evaluating the polynomial function to determine an approximation of a base-2 logarithm result in a second floating-point format (e.g., head-tail format with an N-bit or less head component and N-bit or less tail component). In some embodiments, determining the base-2 logarithm result includes evaluating the polynomial function based on the determined coefficients and input operand x.

In the illustrated embodiment, the base-2 logarithm result includes head and tail components log 2a_head and log 2a_tail that are inputs to the illustrated multiplier circuit320to be multiplied by input operand y.

In the illustrated embodiment, multiplier circuit320(which may correspond to multiplication circuitry120ofFIG.1) performs a head-tail multiplication operation based on operands log 2a_head, log 2a_tail, and y, to generate a multiplication result that includes a multiplication head result and a multiplication tail result.

In the illustrated embodiment, the multiplication head result and multiplication tail result are inputs to two separate multiplexor circuits330and340that propagate the multiplication head and multiplication tail results to base-2 power function circuitry130for the power function. For a base-2 power instruction (indicated by the function input EXP2), however, the input operand y and value zero are propagated to base-2 power function circuitry130instead.

In some embodiments, prior to propagating the specified values to base-2 power function circuitry130, conversion circuitry (not shown) may convert the multiplication head result and multiplication tail result to the floating-point format of the input operands to generate a converted multiplication result.

In the illustrated embodiment, base-2 power function circuitry130is configured to evaluate two to the power of a representation of the multiplication result to generate a result in the first floating point format. The representation of the multiplication result may be the multiplication result itself or the converted multiplication result (e.g., converted from head-tail to a traditional format), for example.

In some embodiments, the result generated by base-2 power function circuitry130is propagated through a multiplexor circuit350for the power instruction. For a base-2 logarithm instruction (indicated by the function input FLOG2), however, the head result generated by base-2 logarithm circuitry110(e.g., log 2a_head) is propagated instead.

In the illustrated embodiment, exception control circuitry310is configured to generate exceptions in certain situations based on the provided input operands x and y, and the function input, according to some embodiments. In some embodiments, exception control circuitry310is configured to ensure input operand x (e.g., the base) and input operand y (e.g., the exponent) do not fall within a set of constraints, which may be programmable. In some embodiments, the constraints may include but are not limited to the following types of numbers: ±zero, ±∞, ±QNaN (quiet not a number), ±SNaN (signaling not a number), ±sub-normal numbers, negative normal numbers, etc.

In some embodiments, in response to detecting that input operand x or input operand y fall within the constraints listed above, exception control circuitry310may provide a 0 value of the is_valid signal and a value associated with the exception to multiplexor circuit360. In some embodiments, the 0 value of the is_valid signal selects the exception value to be the output result of the multiplexor circuit360. In some embodiments, based on the function specified and the input operands, the output result may be an SNaN value or some other appropriate value.

FIG.4is a block diagram illustrating example base-2 logarithm circuitry, according to some embodiments. In the illustrated embodiment, base-2 logarithm circuitry110includes argument shift circuitry410, polynomial approximation circuitry420, floating-point conversion circuitry430, and head-tail addition circuitry440.

In the illustrated embodiment, argument shift circuitry410is configured to extract mantissa and exponent values from a floating-point input. In some embodiments, argument shift circuitry410receives, as input, input operand x and performs one or more operations to output two values: the mantissa of x and the exponent of x.

In some embodiments, argument shift circuitry410computes the mantissa of x by performing a bit-mask AND operation and a bit-mask OR operation. In some embodiments, argument shift circuitry410generates the mantissa of x in a floating-point format equivalent to 1.mantissa. In the illustrated embodiment, the mantissa of x propagates to polynomial approximation circuitry420. In some embodiments, the exponent of x is generated by performing a right-shift operation by a number of bits equal to the size of the mantissa of x (e.g., 23 bits for the IEEE standard single precision floating-point format).

In some embodiments, disclosed circuitry may be configured to provide results for input values within a certain range. In some embodiments, for values greater than the range, the mantissa of x is folded into a smaller range, which may reduce or avoid floating-point cancellation error at a later stage in the pipeline (e.g., in the multiplication step). As one non-limiting example, the mantissa of x may be folded into the smaller range of [0.75, 1.5) which may reduce or avoid floating-point cancellation error at a later stage in the pipeline (e.g., in the multiplication step).

In the illustrated embodiment, polynomial approximation circuitry420is configured to generate an approximation of the base-2 logarithm based on the mantissa and generate head and tail results lgx_head and lgx_tail. A detailed example of circuitry420is discussed in detail below with reference toFIG.5.

In the illustrated embodiment, adder circuitry subtracts a bias value from the exponent of x, the result of which propagates to floating-point conversion circuitry430.

In the illustrated embodiment, floating-point conversion circuitry430is configured to convert the exponent of x minus the bias from twos component representation to a single-precision floating-point representation (the unbiased exponent inFIG.4).

In the illustrated embodiment, head-tail addition circuitry440is configured to perform a head-tail addition operation between the unbiased exponent and the head (e.g., lgx_head) and tail (lgx_tail) outputs generated by polynomial approximation circuitry420. In some embodiments, the head-tail addition includes to perform separate 32-bit floating-point addition operations to generate the head (log 2a_head) and tail (log 2a_tail) results.

Example Polynomial Approximation Circuitry

FIG.5is a block diagram illustrating detailed polynomial approximation circuitry, according to some embodiments. In the illustrated embodiment, polynomial approximation circuitry420includes polynomial coefficient table510and fused Multiply/Add circuitry520A-520C.

In the illustrated embodiment, polynomial approximation circuitry420is configured to perform the base-2 logarithm polynomial approximation discussed with reference toFIG.4above.

In the illustrated embodiment, polynomial approximation circuitry420receives, as input, the mantissa of x and generates a third order polynomial approximation based on the mantissa of x and coefficients stored in polynomial coefficient table510. In some embodiments, the polynomial approximation is a piecewise polynomial approximation that includes multiple sets of coefficients (e.g., C0-C3 in this example) corresponding to different ranges of input values. In some embodiments, polynomial approximation circuitry420implements the polynomial approximation equation, ((xmantissa×C0+C1)×xmantissa+C2)×mantissa+C3. In the illustrated example, coefficient C0 represents the highest degree coefficient for the third order polynomial approximation, while coefficient C3 represents the lowest degree (e.g., constant) coefficient for the third order polynomial approximation.

In the illustrated embodiment, polynomial coefficient table510is configured to store coefficients for the polynomial approximation. Table510may store different sets of inputs for different ranges of input x mantissa values. In the illustrated embodiment, some of the determined coefficients include head and tail components (e.g., C2_Head, C2_Tail, etc.) and some of the determined coefficients do not use a head-tail representation (e.g., C0, C1, etc.). This approach may satisfy an accuracy target without using head-tail representations for some values (which may reduce area and power consumption).

In some embodiments, the coefficients stored in table510are generated using overlapping intervals. For example, the coefficients for a given entry in table510may correspond to a curve fitting over a greater range of input values than a range of input values corresponding to the entry. As one hypothetical example and for purposes of explanation, a given entry of table510may store (and return) coefficients for a mantissa of x in the range of input values [0.80, 0.90), but the corresponding coefficients for the given entry may correspond to a curve fitting operation over the greater range [0.78, 0.92).

In some embodiments, generating coefficients in table510using overlapping intervals maintains monotonicity of the base-2 logarithm approximation. This may also advantageously reduce error (which typically may be greatest near the edges of a given interval).

In the illustrated embodiment, fused Multiply/Add circuitry520A-520C is configured to perform cascaded fused multiply-add operations between the determined coefficients and the mantissa of x to implement the polynomial. In other embodiments, fused multiply-add operations may use a variation of the mantissa of x to implement the polynomial. For example, conversion circuitry (not shown) may convert the mantissa of x to a different format before fused Multiply/Add circuitry520A-520C performs cascaded fused multiply-add operations. In some embodiments, fused Multiply/Add circuitry520A-520C perform fixed-point fused multiply/add operations.

In some embodiments, fused multiply/add circuit520A performs a multiplication operation between the mantissa of x and the coefficient C0, followed by addition of the coefficient C1, to generate the expression (xmantissa×C0+C1) represented by the intermediary result z1.

In some embodiments, fused multiply/add circuit520B performs a multiplication between the intermediary result z1 and the mantissa of x, followed by a head-tail addition operation using coefficients C2_Head and C2_Tail, to generate intermediary results z2_head and z2_tail. In some embodiments, intermediary result z2_head represents the expression (xmantissa×C0+C1)×xmantissa+C2_head, while z2_tail represents (xmantissa×C0+C1)×xmantissa+C2_tail.

In some embodiments, fused multiply/add circuit520C performs separate head-tail multiplication operations between the intermediary results z2_head and z2_tail, and the mantissa of x, followed by a head-tail addition operation using coefficients C3_Head and C3_Tail, to generate log 2a_head and log 2a_tail results. In some embodiments, log 2a_head and log 2a_tail represent the head and tail components of the base-2 logarithm polynomial approximation, respectively.

Example Method

FIG.6is a flow diagram illustrating an example method, according to some embodiments. The method shown inFIG.6may be used in conjunction with any of the computer circuitry, systems, devices, elements, or components disclosed herein, among others. In various embodiments, some of the method elements shown may be performed concurrently, in a different order than shown, or may be omitted. Additional method elements may also be performed as desired.

At610, in the illustrated embodiment, a computing device (e.g., execution circuitry100) executes a single power instruction that operates on first and second floating-point inputs in a first floating-point format to generate a result that evaluates a power function, 2(second input*log2(first input)).

In some embodiments, the first floating-point format is an N-bit floating-point format. As one example, the first floating-point format may be the IEEE standard single precision floating-point format, which represents a floating-point number using 32 bits

At620, in the illustrated embodiment, the computing device (e.g., base-2 logarithm circuitry110) determines coefficients for a polynomial function based on the first input.

In some embodiments, the polynomial function is a third order polynomial. In some embodiments, to determine the coefficients for the polynomial function includes to access a polynomial coefficient table based on the first input.

In some embodiments, a given entry of the polynomial coefficient table includes multiple coefficients for the third order polynomial corresponding to a range of input values.

In some embodiments, the polynomial coefficient table is generated using overlapping intervals such that coefficients for a given entry in the polynomial coefficient table correspond to curve fitting over a greater range of input values than a range of input values corresponding to the entry.

At630, in the illustrated embodiment, the computing device (e.g., base-2 logarithm circuitry110) evaluates the polynomial function to determine a first result in a second floating-point format, based on the determined coefficients and the first input.

In some embodiments, the second floating-point format includes a head component and a tail component (e.g., head-tail format). In some embodiments, this includes an N-bit or less head component and N-bit or less tail component. In some embodiments, the head-tail format is used to generate a greater precision result such that rounding error does not become unacceptable in a later stage (e.g., in the multiplication operation at640). A head-tail format represents a higher precision number using two components of lower precision and operates on the two components individually.

In some embodiments, one or more of the determined coefficients include head and tail components and one or more of the determined coefficients use a non-head-tail representation.

In some embodiments, the first result includes a first head result and a first tail result.

At640, in the illustrated embodiment, the computing device (e.g., multiplication circuitry120) multiplies the first result by the second floating-point input to generate a multiplication result.

In some embodiments, the multiplication is a head-tail operation and the multiplication result includes a second head result (e.g., multiplication head result) and a second tail result (e.g., multiplication tail result).

At650, in the illustrated embodiment, the computing device (e.g., base-2 power function circuitry130) evaluates two the power of a representation of the multiplication result to generate a result of the single floating-point power function in the first floating-point format.

In some embodiments, to evaluate two to the power of a representation of the multiplication result, the computing device (e.g., base-2 power function circuitry130) determines coefficients for a third order polynomial function based on the multiplication result and evaluates the third order polynomial function to determine two to the power of a representation of the multiplication result in the first floating-point format.

In some embodiments, the computing device converts the second head result and the second tail result to the first floating-point format to generate converted multiplication result. In some embodiments, the computing device (e.g., base-2 power function circuitry130) evaluates two the power of the converted multiplication result.

In some embodiments, the first head result, first tail result, second head result, and second tail result are each represented using N bits or less. In some embodiments, the computing device (e.g., execution circuitry100) further executes a base-2 logarithm instruction and evaluates the base-2 logarithm of an input to generate a result of the base-2 logarithm instruction. In some embodiments, the computing device includes multiplexor circuitry that selects the result of the base-2 logarithm instruction.

In some embodiments, the computing device (e.g., execution circuitry100) further executes a base-2 power function instruction and evaluates the base-2 power function of an input to generate a result of the base-2 power function instruction. In some embodiments, the computing device (e.g., execution circuitry100) includes multiplexor circuitry that selects the result of the base-2 power function instruction.

Example Device

Referring now toFIG.7, a block diagram illustrating an example embodiment of a device700is shown. In some embodiments, elements of device700may be included within a system on a chip. In some embodiments, device700may be included in a mobile device, which may be battery-powered. Therefore, power consumption by device700may be an important design consideration. In the illustrated embodiment, device700includes fabric710, compute complex720input/output (I/O) bridge750, cache/memory controller745, graphics unit775, and display unit765. In some embodiments, device700may include other components (not shown) in addition to or in place of the illustrated components, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

Fabric710may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of device700. In some embodiments, portions of fabric710may be configured to implement various different communication protocols. In other embodiments, fabric710may implement a single communication protocol and elements coupled to fabric710may convert from the single communication protocol to other communication protocols internally.

In the illustrated embodiment, compute complex720includes bus interface unit (BIU)725, cache730, and cores735and740. In various embodiments, compute complex720may include various numbers of processors, processor cores and caches. For example, compute complex720may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache730is a set associative L2 cache. In some embodiments, cores735and740may include internal instruction and data caches. In some embodiments, a coherency unit (not shown) in fabric710, cache730, or elsewhere in device700may be configured to maintain coherency between various caches of device700. BIU725may be configured to manage communication between compute complex720and other elements of device700. Processor cores such as cores735and740may be configured to execute instructions of a particular instruction set architecture (ISA) which may include operating system instructions and user application instructions.

Cache/memory controller745may be configured to manage transfer of data between fabric710and one or more caches and memories. For example, cache/memory controller745may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller745may be directly coupled to a memory. In some embodiments, cache/memory controller745may include one or more internal caches.

As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, inFIG.7, graphics unit775may be described as “coupled to” a memory through fabric710and cache/memory controller745. In contrast, in the illustrated embodiment ofFIG.7, graphics unit775is “directly coupled” to fabric710because there are no intervening elements.

Graphics unit775may include one or more processors, e.g., one or more graphics processing units (GPU's). Graphics unit775may receive graphics-oriented instructions, such as OPENGL®, Metal, or DIRECT3D® instructions, for example. Graphics unit775may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit775may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display, which may be included in the device or may be a separate device. Graphics unit775may include transform, lighting, triangle, and rendering engines in one or more graphics processing pipelines. Graphics unit775may output pixel information for display images. Graphics unit775, in various embodiments, may include programmable shader circuitry which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and compute tasks (which may or may not be graphics-related).

Display unit765may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit765may be configured as a display pipeline in some embodiments. Additionally, display unit765may be configured to blend multiple frames to produce an output frame. Further, display unit765may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).

I/O bridge750may include various elements configured to implement: universal serial bus (USB) communications, security, audio, and low-power always-on functionality, for example. I/O bridge750may also include interfaces such as pulse-width modulation (PWM), general-purpose input/output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C), for example. Various types of peripherals and devices may be coupled to device700via I/O bridge750.

In some embodiments, device700includes network interface circuitry (not explicitly shown), which may be connected to fabric710or I/O bridge750. The network interface circuitry may be configured to communicate via various networks, which may be wired, wireless, or both. For example, the network interface circuitry may be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi), or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks that use one or more radio access technologies. In some embodiments, the network interface circuitry is configured to communicate using device-to-device communications (e.g., Bluetooth or WiFi Direct), etc. In various embodiments, the network interface circuitry may provide device700with connectivity to various types of other devices and networks.

Various elements ofFIG.7may utilize disclosed techniques. For example, execution circuitry100may be included in compute complex720or graphics unit775. Disclosed techniques may advantageously increase performance and reduce power consumption of floating-point power function operations with reasonable area and accuracy, in various embodiments.

Example Applications

Turning now toFIG.8, various types of systems that may include any of the circuits, devices, or system discussed above. System or device800, which may incorporate or otherwise utilize one or more of the techniques described herein, may be utilized in a wide range of areas. For example, system or device800may be utilized as part of the hardware of systems such as a desktop computer810, laptop computer820, tablet computer830, cellular or mobile phone840, or television850(or set-top box coupled to a television).

Similarly, disclosed elements may be utilized in a wearable device860, such as a smartwatch or a health-monitoring device. Smartwatches, in many embodiments, may implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device may also be designed solely to perform health-monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communication to an emergency medical service, etc. Other types of devices are also contemplated, including devices worn on the neck, devices implantable in the human body, glasses or a helmet designed to provide computer-generated reality experiences such as those based on augmented and/or virtual reality, etc.

System or device800may also be used in various other contexts. For example, system or device800may be utilized in the context of a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service870. Still further, system or device800may be implemented in a wide range of specialized everyday devices, including devices880commonly found in the home such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Elements may also be implemented in various modes of transportation. For example, system or device800could be employed in the control systems, guidance systems, entertainment systems, etc. of various types of vehicles890.

The applications illustrated inFIG.8are merely exemplary and are not intended to limit the potential future applications of disclosed systems or devices. Other example applications include, without limitation: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

Example Computer-Readable Medium

The present disclosure has described various example circuits in detail above. It is intended that the present disclosure cover not only embodiments that include such circuitry, but also a computer-readable storage medium that includes design information that specifies such circuitry. Accordingly, the present disclosure is intended to support claims that cover not only an apparatus that includes the disclosed circuitry, but also a storage medium that specifies the circuitry in a format that is recognized by a fabrication system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuitry. Claims to such a storage medium are intended to cover, for example, an entity that produces a circuit design, but does not itself fabricate the design.

FIG.9is a block diagram illustrating an example non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. In the illustrated embodiment semiconductor fabrication system920is configured to process the design information915stored on non-transitory computer-readable medium910and fabricate integrated circuit930based on the design information915.

Design information915may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information915may be usable by semiconductor fabrication system920to fabricate at least a portion of integrated circuit930. The format of design information915may be recognized by at least one semiconductor fabrication system920. In some embodiments, design information915may also include one or more cell libraries which specify the synthesis, layout, or both of integrated circuit930. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies cell library elements and their connectivity. Design information915, taken alone, may or may not include sufficient information for fabrication of a corresponding integrated circuit. For example, design information915may specify the circuit elements to be fabricated but not their physical layout. In this case, design information915may need to be combined with layout information to actually fabricate the specified circuitry.

Integrated circuit930may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information915may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (GDSII), or any other suitable format.

In various embodiments, integrated circuit930is configured to operate according to a circuit design specified by design information915, which may include performing any of the functionality described herein. For example, integrated circuit930may include any of various elements shown inFIGS.1-5and7. Further, integrated circuit930may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits.

In some cases, various units/circuits/components may be described herein as performing a set of tasks or operations. It is understood that those entities are “configured to” perform those tasks/operations, even if not specifically noted.