HYBRID BONDING A DIE TO A SUBSTRATE WITH VIAS CONNECTING METAL PADS ON BOTH SIDES OF THE DIE

Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular hybrid bonding of a die within a package.

BACKGROUND

Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for reducing package component size and increasing package reliability.

DETAILED DESCRIPTION

Embodiments of the present disclosure may generally relate to systems, apparatus, techniques, and/or processes directed to facilitate the creation of complex packages by using hybrid bonding techniques to bond a die to a substrate. In embodiments, these same techniques may be used to bond a die to a die. In embodiments, a die may be a chiplet. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both.

In embodiments, the die may be hybrid bonded as part of an Omnidirectional Interconnect™ (ODI) or as part of another device component where the die serves as a bridge or a component in a bridge between one or more dies, between one or more interposers, or between a combination thereof. In embodiments, the die to be hybrid bonded may include a conductive metal via that extends from a first side of the die to a second side of the die opposite the first side. A metal pad may be coupled with the conductive metal via, and the metal pad may be used to hybrid bond the die to another metal pad on a substrate

As requirements for interconnect bandwidth increase, package form factor reduction and layer count reduction are becoming increasingly important. Legacy implementations for bonding a die to a substrate may include creating a cavity within a substrate, and then attaching the die to the bottom of the cavity using a die attach film (DAF). Other legacy implementations may use a die that has solder bump connections on one surface of the die that solders to solder bumps on the substrate, where solder reflow physically and electrically couples the die to the substrate. Each of these legacy techniques may increase the number of layers and/or form factor sizes in comparison to embodiments described herein.

With embodiments described herein, there may be no DAF removal process, and furthermore the overall package may not need to be exposed to any chemistry during processing which may create quality issues. In addition, because hybrid bonding is used, there are no void concerns within small pitch regions between metal pads on the die and on the substrate. As a result, the die in the substrate will have a stronger bond, and be less sensitive to subsequent reflow processes because no intermetallic compounds (IMC) has been formed during the hybrid bonding process.

Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.

FIGS.1A-1Billustrate various legacy implementations for bonding a die to a substrate.FIG.1Ashows a legacy implementation of a cross section side view100a1and a top-down view100a2of a package that includes a substrate102, with multiple layers102a,102b,102c,102d. A cavity104extends from the top of the substrate102to the bottom layer102d, specifically extending to a metal106. In implementations, the metal106may be a non-metal feature which may be referred to as a cavity interface material.

A die110may be placed within the cavity104, on top of the metal106using a DAF108. In implementations, the DAF108may be thermoplastic or thermosetting organic resin that may be incorporated with a conductive filler, and dried into sheets/film of thickness ranging anywhere between 10-40 μm. Examples of polymer resins that may be used in the DAF108include epoxies, maleimides, bismaleimides, acrylates, silicone, and/or cyanate esters.

The die110may include electrical contacts112on the top side of the die110that may electrically couple with other devices, such as other dies (not shown), subsequently in the legacy manufacturing process. In some implementations, there may be electrical contacts (not shown) near the bottom of the die110, above the metal106and above the DAF108. Note that in implementations, after the die110is bonded to the substrate102, the remaining cavity104may be filled with a mold, a polymer, or some other filling agent.

In implementations, the DAF108material may have a limitation of lower mechanical strength that may result in the loosening or detachment of the die110from the substrate102. In addition, if the DAF108has to be removed, a wet chemistry or a dry etch process is required in order to expose any backside copper pads (not shown) on the die110to enable vertical electrical connections through the backside of the substrate102.

FIG.1Bshows a legacy implementation of a cross section side view100biof a die120that includes a die body122, that may have electrically conductive vias124running from a first side of the die body122to a second side of the die body122opposite the first side. Note that electrically conductive vias124may be also referred to as through silicon vias (TSV). In implementations, top metal pads130may couple with some of the electrically conductive vias124at the first side of the die body122, and bottom metal pads126may couple with the electrically conductive vias124at the second side of the die body122. Note that the bottom metal pads126may include solder balls128in preparation for physical and/or electrical coupling with the substrate140.

Substrate140may include a substrate layer142, which in some implementations may be referred to as a carrier. Substrate140may include copper pillars144that are attached to the substrate layer142, as well as metal pads146also attached to the substrate layer142. In implementations, there may be a layer150, that may include routing features (not shown), above the substrate layer142. Note that the metal pads146may have solder balls148on top of them.

In legacy implementations, the die120may be connected with the substrate140by soldering the bottom metal pads126with the metal pads146of the substrate140. This may be accomplished by coupling the solder balls128with solder balls148and then applying a reflow process. This may be referred to as a “solder to solder” joining of the die120to the substrate140.

These legacy implementations have drawbacks. First, when a smaller pitch and bump size is applied, there may be at most a full layer of intermetallic compound (IMC)149formed at the solder interface. Diagram100b2shows a cross-section image of a solder joint formed by solder148on metal pad146coming into contact with solder128on bottom metal pad126. As a result of the reflow process, an excess amount of IMC149is formed, which poses significant reliability challenges for the operation of the resulting device. In addition, because of the smaller pitch used for the bottom metal pads126and metal pads146, it is far easier to create encapsulation voids during the encapsulation process, resulting in a weaker bond. In addition, the reflow process will exert additional thermal history to the package, which may further compromise the structural integrity of the package.

FIG.2illustrates a cross section side view and a top-down view of a die to be hybrid bonded to a substrate, in accordance with various embodiments. Diagram200ais a cross section side view of a die220and a substrate240. The die220may include a die body222that may have electrically conductive vias224running from a first side of the die body222to a second side of the die body222opposite the first side. In implementations, top metal pads230couple with some of the electrically conductive vias224at the first side of the die body222. Bottom metal pads226may couple with the electrically conductive vias224at the second side of the die body222. In embodiments, a dielectric227may be on the bottom side of the die body222, and surround bottom metal pads226. In embodiments, the dielectric227may be a Polyimide, or some other dielectric material that may be used during hybrid bonding. Diagram200cshows a top-down view of die220.

Substrate240may include a substrate layer242. In some embodiments, substrate layer242may be a silicon layer. In some embodiments, substrate layer242may be a carrier that may be made out of a glass or some other material, that may be eventually removed during processing. Substrate240may include copper pillars244that are attached to the substrate layer242, as well as metal pads246also attached to the substrate layer242. In embodiments, a dielectric247may be on the substrate layer242, and surround the metal pads246. In embodiments, the dielectric247may be a Polyimide that may be used during hybrid bonding.

Diagram200bis a cross section side view of the result of die220being hybrid bonded to substrate240. The bottom metal pads226and the metal pads246, which may include copper, have been fused. In addition, the dielectric227and the dielectric247, which may include a Polyimide, have also been fused. Note that in embodiments, the entire surface area of the die220that includes the dielectric227and the bottom metal pads226have been directly physically coupled with the substrate240. In embodiments, the metal pads246of the substrate240may be coupled with metallic routings (not shown) elsewhere on the substrate240. In embodiments, the vias224that connect with the top metal pads230may provide electrical connection from the substrate240through the die220. Note that in embodiments, in this configuration, the die220may serve as a bridge die that may be used to bridge other devices attached to a top of the die220.

FIG.3illustrates an image of a cross section side view of cured Polyimide layer bonding between two substrates. Layers320may represent the bottom portion of the die220ofFIG.2, and layers340may represent a portion of the substrate240to which the die220is to be attached. Silicon layer322, which may be similar to a portion of the die body222, is above a Polyimide layer327, which may be similar to dielectric layer227. Directly below Polyimide layer327is another Polyimide layer347, which may be similar to dielectric layer247, and on top of silicon layer342which may be similar to a portion of substrate layer242. As shown, the two Polyimide layers327,347have cured and then bonded, with no void in the interface329between them.

FIGS.4A-4Fillustrate stages in a manufacturing process for hybrid bonding a die onto a substrate, in accordance with various embodiments. In embodiments, the die may be a chip.FIG.4Ashows a cross section side view of a stage in the manufacturing process where a die420and a substrate440, which may be similar to die220and substrate240ofFIG.2, are provided. The die420may include a die body422that may have electrically conductive vias424running from a first side of the die body422to a second side of the die body422opposite the first side. In implementations, top metal pads430may couple with some of the electrically conductive vias424at the first side of the die body422, and bottom metal pads426may couple with the electrically conductive vias424at the second side of the die body422opposite the first side. In embodiments, a dielectric427may be on the bottom side of the die body422, and surround bottom metal pads426. In embodiments, the dielectric427may be a Polyimide, or some other dielectric material that may be used during hybrid bonding. In embodiments, electronic circuitry or other electronic components (not shown) may be within the die body422, and may be electrically coupled with the vias424within the die420.

Substrate440may include a substrate layer442, which in some embodiments may be referred to as a carrier. Substrate440may include copper pillars444that are attached to the substrate layer442, as well as metal pads446that are also attached to the substrate layer442. In embodiments, a dielectric447may be on the substrate layer442, and surround the metal pads446. In embodiments, the substrate layer442may be a glass layer that serves as a carrier, which may later be removed. In embodiments, the dielectric447may be a Polyimide that may be used during hybrid bonding in the subsequent manufacturing process stage.

FIG.4Bshows a cross section side view of a stage in the manufacturing process where the die420and the substrate440fromFIG.4Aare hybrid bonded to each other. As a result of hybrid bonding, the bottom metal pads426of the die are bonded with the metal pads446of the substrate, and the dielectric427of the die420is bonded with the dielectric447of the substrate440.

The hybrid bonding process may be a part of a thermal compression bonding (TCB) process that may involve a series of stages. For example, a first stage of the hybrid bonding process may involve bringing the dielectric427of the die420into physical contact with the dielectric447of the substrate440, where the bottom metal pads426and metal pads446are aligned with each other. This may be done at a lower temperature, for example at an ambient room temperature. A second stage of the hybrid bonding process may involve applying heat so that the bottom metal pads426and the metal pads446are brought into physical contact with each other. A third stage of a hybrid bonding process may involve applying further heat to compress the bottom metal pads426and the metal pads446, creating a bonding between them, as well as a bonding between the dielectric427and the dielectric447. The result is device470.

FIG.4Cshows a cross section side view of a stage in the manufacturing process where the device470is encapsulated with a mold460. In embodiments, the mold460may be applied using compression molding techniques, or other molding application techniques. In embodiments, the mold460may include any molding compound that may provide good encapsulation performance and good mechanical reliability.

FIG.4Dshows a cross section side view of a stage in the manufacturing process where a grinding or polishing process is applied to planarize and to remove a portion462of the mold460. As a result, tops of copper pillars444, as well as tops of top metal pads430will be exposed.

FIG.4Eshows a cross section side view of a stage in the manufacturing process where dies470,472are coupled with the top metal pads430and the copper pillars444. In this embodiment, metal pads446may be electrically coupled with the dies470,472through the bottom metal pads426and the conductive vias424. It should be noted that two dies470,472are shown here, however in other embodiments a single die or any number of multiple dies may be electrically coupled with the pillars444or the top metal pads430. An encapsulation material474, which may also serve as an underfill material, may be placed around or at least partially around the dies470,472.

FIG.4Fshows a cross section side view of a stage in the manufacturing process where the substrate layer442ofFIG.4Eis a glass carrier that has been debonded476. In subsequent manufacturing stages, the device ofFIG.4Fmay be attached to another substrate.

FIGS.5A-5Killustrate stages in a manufacturing process for creating a die for hybrid bonding to a substrate, in accordance with various embodiments. The manufacturing stages shown below with respect toFIGS.5A-5Kmay be used to produce a die that may be similar to die220ofFIG.2or die420ofFIG.4A.

FIG.5Ashows a cross section side view of a stage in the manufacturing process where a glass carrier542may be provided. In embodiments, the glass carrier542may be a panel made of glass to serve as a temporary support that will later be removed. In embodiments, a laser release layer578may be physically coupled with a side of the glass carrier542. In embodiments, a wafer521or a portion of a wafer may be provided, that includes a die body522, and a plurality of top metal pads530, which may be similar to the top metal pads230ofFIG.2. Note that subsequent stages in the manufacturing process will flip orientation of the wafer521so that the top metal pads530will be at the top.

In embodiments, conductive vias524may be created that electrically couple with at least some of the top metal pads530. In embodiments, the conductive vias524may be formed by first drilling out a via, and filling the drilled via with a conductive metal, such as copper. Note that the wafer521may include multiple die structures that are similar to die220ofFIG.2, which will be diced later. The top metal pads530may be surrounded by a dielectric material580.

FIG.5Bshows a cross section side view of a stage in the manufacturing process where the wafer521is bonded with the laser release layer578on top of the glass carrier542to form a structure582.

FIG.5Cshows a cross section side view of a stage in the manufacturing process where a portion584of the die body522is ground to expose the conductive vias524.

FIG.5Dshows a cross section side view of a stage in the manufacturing process where the bottom metal pads526, which may be similar to the bottom metal pads226ofFIG.2, are placed proximate to the conductive vias524. In embodiments, the bottom metal pads526may be formed as a patterned copper bump.

FIG.5Eshows a cross section side view of a stage in the manufacturing process where a dielectric527is placed above and around the bottom metal pads526. In embodiments, the dielectric527may be similar to dielectric227ofFIG.2, and may include a Polyimide or other dielectric that may be used for subsequent hybrid bonding processes.

FIG.5Fshows a cross section side view of a stage in the manufacturing process where a portion527aof the dielectric527is ground or polished, for example by a chemical mechanical planarization (CMP) process, to a level of the bottom metal pads526. The remaining dielectric527bsurrounds the bottom metal pads526. The result of this stage is structure586.

FIG.5Gshows a cross section side view of a stage in the manufacturing process where the structure586ofFIG.5Fis flipped, and the bottom metal pads526that are coupled with the electrically conductive vias524, and the dielectric527bare physically coupled with a lamination layer590on top of a dicing tape588. In embodiments, lamination layer590may be an adhesive layer on top of dicing tape588.

FIG.5Hshows a cross section side view of a stage in the manufacturing process where the glass carrier542and the laser release layer578are removed, leaving dielectric material580that surrounds the top metal pads530.

FIG.5Ishows a cross section side view of a stage in the manufacturing process where the dielectric material580is removed. In embodiments, a wet etch process or a dry etch process may be used to remove the dielectric material580.

FIG.5Jshows a cross section side view of a stage in the manufacturing process where a cut592may be made through the die body522, through the dielectric layer527b, through the lamination layer590, and into the dicing tape588. This stage may be referred to as a singulation process.

FIG.5Kshows a cross section side view of the stage in the manufacturing process where a singulated die520is shown after the dicing tape588and the laminate590have been removed. In embodiments, the singulated die520may be referred to as a chiplet, and may be similar to die220ofFIG.2.

FIG.6illustrates an example of a process for hybrid bonding a die to a substrate, in accordance with various embodiments. Process600may be performed by one or more elements, techniques, or systems that may be described herein, and in particular with respect toFIGS.1-5J.

At block602, the process may include providing a die that has a first side and a second side opposite the first side, wherein the first side includes one or more metal pads, and wherein the first side includes a dielectric layer surrounding the one or more metal pads. The die, the metal pads, and the dielectric layer may be similar to die220, bottom metal pads226and dielectric layer227ofFIG.2, die420, bottom metal pads426and dielectric layer427ofFIG.4A, or die520, bottom metal pads526, and dielectric layer527bofFIGS.5J-5K.

At block604, the process may further include providing a substrate that includes one or more metal pads on a side of the substrate, wherein the side of the substrate includes a dielectric layer surrounding the one or more metal pads. In embodiments, the substrate, metal pads, and dielectric layer surrounding the metal pads may be similar to substrate240, metal pads246, and dielectric layer247ofFIG.2, or substrate440, metal pads446, and dielectric layer447ofFIG.4A.

At block606, the process may further include hybrid bonding the first side of the die with the side of the substrate. In embodiments, the hybrid bonding process may be similar to the process shown with respect to diagram200bofFIG.2, or structure470ofFIG.4B.

FIGS.7A-7Bschematically illustrate a top view of an example die in wafer form and in singulated form, and a cross section side view of a package assembly, in accordance with various embodiments.FIG.7Aschematically illustrates a top view of an example die702in a wafer form701and in a singulated form700, in accordance with some embodiments. In some embodiments, die702may be one of a plurality of dies, e.g., dies702,702a,702b, of a wafer703comprising semiconductor material, e.g., silicon or other suitable material. The plurality of dies, e.g., dies702,702a,702b, may be formed on a surface of wafer703. Each of the dies702,702a,702b, may be a repeating unit of a semiconductor product that includes devices as described herein. For example, die702may include circuitry having elements such as capacitors and/or inductors704(e.g., fin structures, nanowires, and the like) that provide a channel pathway for mobile charge carriers in transistor devices. Although one or more capacitors and/or inductors704are depicted in rows that traverse a substantial portion of die702, it is to be understood that one or more capacitors and/or inductors704may be configured in any of a wide variety of other suitable arrangements on die702in other embodiments.

After a fabrication process of the device embodied in the dies is complete, wafer703may undergo a singulation process in which each of dies, e.g., die702, is separated from one another to provide discrete “chips” of the semiconductor product. Wafer703may be any of a variety of sizes. In some embodiments, wafer703has a diameter ranging from about 25.4 mm to about 450 mm. Wafer703may include other sizes and/or other shapes in other embodiments. According to various embodiments, the one or more capacitors and/or inductors704may be disposed on a semiconductor substrate in wafer form701or singulated form700. One or more capacitors and/or inductors704described herein may be incorporated in die702for logic, memory, or combinations thereof. In some embodiments, one or more capacitors and/or inductors704may be part of a system-on-chip (SoC) assembly.

FIG.7Bschematically illustrates a cross-section side view of an integrated circuit (IC) assembly750, in accordance with some embodiments. In some embodiments, IC assembly750may include one or more dies, e.g., die702, electrically or physically coupled with a package substrate721. Die702may include one or more capacitors and/or inductors704as described herein. In some embodiments, package substrate721may be electrically coupled with a circuit board722as is well known to a person of ordinary skill in the art. Die702may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like. In some embodiments, die702may be, include, or be a part of a processor, memory, SoC or ASIC in some embodiments.

Die702can be attached to package substrate721according to a wide variety of suitable configurations including, for example, being directly coupled with package substrate721in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side S1of die702including circuitry is attached to a surface of package substrate721using hybrid bonding structures as described herein that may also electrically couple die702with package substrate721. Active side S1of die702may include multi-threshold voltage transistor devices as described herein. An inactive side S2of die702may be disposed opposite to active side S1.

In some embodiments, package substrate721is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. Package substrate721may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

Package substrate721may include electrical routing features configured to route electrical signals to or from die702. The electrical routing features may include pads or traces (not shown) disposed on one or more surfaces of package substrate721and/or internal routing features (not shown) such as trenches, vias, or other interconnect structures to route electrical signals through package substrate721. In some embodiments, package substrate721may include electrical routing features such as pads (not shown) configured to receive the respective die-level interconnect structures706of die702.

Circuit board722may be a printed circuit board (PCB) comprising an electrically insulative material such as an epoxy laminate. Circuit board722may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR-4), FR-1, cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures such as traces, trenches, vias may be formed through the electrically insulating layers to route the electrical signals of die702through circuit board722. Circuit board722may comprise other suitable materials in other embodiments. In some embodiments, circuit board722is a motherboard as is well known to a person of ordinary skill in the art.

Package-level interconnects such as, for example, solder balls712may be coupled to one or more pads710on package substrate721and/or on circuit board722to form corresponding solder joints that are configured to further route the electrical signals between package substrate721and circuit board722. Pads710may comprise any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple package substrate721with circuit board722may be used in other embodiments.

IC assembly750may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package configurations including system-in-package (SiP), and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between die702and other components of IC assembly750may be used in some embodiments.

A person of ordinary skill in the art should recognize that any known semiconductor device fabricated using any known semiconductor process that may benefit from the principles described herein.

FIG.8is a schematic of a computer system800, in accordance with an embodiment of the present invention. The computer system800(also referred to as the electronic system800) as depicted can embody hybrid bonding a die to a substrate with vias connecting metal pads on both sides of the die, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. The computer system800may be a mobile device such as a netbook computer. The computer system800may be a mobile device such as a wireless smart phone. The computer system800may be a desktop computer. The computer system800may be a hand-held reader. The computer system800may be a server system. The computer system800may be a supercomputer or high-performance computing system.

In an embodiment, the electronic system800is a computer system that includes a system bus820to electrically couple the various components of the electronic system800. The system bus820is a single bus or any combination of busses according to various embodiments. The electronic system800includes a voltage source830that provides power to the integrated circuit810. In some embodiments, the voltage source830supplies current to the integrated circuit810through the system bus820.

The integrated circuit810is electrically coupled to the system bus820and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit810includes a processor812that can be of any type. As used herein, the processor812may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor812includes, or is coupled with, hybrid bonding a die to a substrate with vias connecting metal pads on both sides of the die, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit810are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit814for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit810includes on-die memory816such as static random-access memory (SRAM). In an embodiment, the integrated circuit810includes embedded on-die memory816such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the integrated circuit810is complemented with a subsequent integrated circuit811. Useful embodiments include a dual processor813and a dual communications circuit815and dual on-die memory817such as SRAM. In an embodiment, the dual integrated circuit810includes embedded on-die memory817such as eDRAM.

In an embodiment, the electronic system800also includes an external memory840that in turn may include one or more memory elements suitable to the particular application, such as a main memory842in the form of RAM, one or more hard drives844, and/or one or more drives that handle removable media846, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory840may also be embedded memory848such as the first die in a die stack, according to an embodiment.

In an embodiment, the electronic system800also includes a display device850, an audio output860. In an embodiment, the electronic system800includes an input device such as a controller870that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system800. In an embodiment, an input device870is a camera. In an embodiment, an input device870is a digital sound recorder. In an embodiment, an input device870is a camera and a digital sound recorder.

As shown herein, the integrated circuit810can be implemented in a number of different embodiments, including a package substrate having hybrid bonding a die to a substrate with vias connecting metal pads on both sides of the die, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having hybrid bonding a die to a substrate with vias connecting metal pads on both sides of the die, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having hybrid bonding a die to a substrate with vias connecting metal pads on both sides of the die embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line ofFIG.8. Passive devices may also be included, as is also depicted inFIG.8.

Examples

Example 1 is an electronic device comprising: a substrate; a metal pad on a side of the substrate; a dielectric material on the side of the substrate, the dielectric material surrounding the metal pad; a die having a first side and a second side opposite the first side, the first side of the die includes a metal pad and a dielectric material surrounding the metal pad; and wherein the first side of the die is hybrid bonded to the side of the substrate, wherein the metal pad on the side of the substrate is directly bonded to the metal pad of the first side of the die, and wherein the dielectric material on the side of the substrate is directly bonded to the dielectric material on the first side of the die.

Example 2 includes the electronic device of example 1, or of any other example or embodiment herein, wherein the dielectric material includes Polyimide.

Example 3 includes electronic device of example 1, or of any other example or embodiment herein, wherein the metal pad on the side of the substrate is an active metal pad.

Example 4 includes electronic device of example 1, or of any other example or embodiment herein, wherein the metal pad on the first side of the die is electrically coupled with a via that extends from the first side of the die to the second side of the die.

Example 5 includes electronic device of example 4, or of any other example or embodiment herein, wherein the via extends from the metal pad on the first side of the die to a metal pad on the second side of the die.

Example 6 includes electronic device of example 4, or of any other example or embodiment herein, wherein the die includes electronic circuitry, and wherein the via is electrically coupled with the electronic circuitry.

Example 7 includes electronic device of example 1, or of any other example or embodiment herein, wherein the metal pad on the side of the substrate is a plurality of metal pads, and wherein the metal pad on the first side of the die is a plurality of metal pads.

Example 8 includes electronic device of example 7, or of any other example or embodiment herein, where at least some of the plurality of metal pads on the side of the substrate are active metal pads.

Example 9 includes electronic device of example 1, or of any other example or embodiment herein, wherein the first side of the die is hybrid bonded at a bottom of a cavity within the substrate.

Example 10 includes electronic device of example 1, or of any other example or embodiment herein, wherein the die is a bridge die.

Example 11 includes electronic device of example 1, or of any other example or embodiment herein, wherein the die is a first die; and further comprising a second die, wherein the second die is directly coupled with the second side of the first die.

Example 12 includes electronic device of example 1, or of any other example or embodiment herein, wherein the device is a portion of an omnidirectional interconnect (ODI).

Example 13 is a die comprising: a first side and a second side opposite the first side; one or more metal pads on the first side; a dielectric material on the first side surrounding the one or more metal pads; and one or more vias extending from the first side to the second side, the one or more vias directly electrically coupled, respectively, from one of the one or more metal pads on the first side to one of one or more metal pads on the second side.

Example 14 includes the die of example 13, or of any other example or embodiment herein, further comprising a dielectric layer on the first side, the dielectric layer surrounding the one or more metal pads.

Example 15 includes the die of example 14, or of any other example or embodiment herein, wherein the dielectric layer includes Polyimide.

Example 16 includes the die of example 13, or of any other example or embodiment herein, wherein the die includes electrical circuitry, and wherein at least one of the one or more vias electrically couple with the electrical circuitry.

Example 17 is a method comprising: providing a die that has a first side and a second side opposite the first side, wherein the first side includes one or more metal pads, and wherein the first side includes a dielectric layer surrounding the one or more metal pads; providing a substrate that includes one or more metal pads on a side of the substrate, wherein the side of the substrate includes a dielectric layer surrounding the one or more metal pads; and hybrid bonding the first side of the die with the side of the substrate.

Example 18 may include the method of example 17, or of any other example or embodiment herein, wherein hybrid bonding the first side of the die with the side of the substrate further includes: placing the first side of the die on the side of the substrate, wherein at least a subset of the one or more metal pads of the first side of the die are in direct physical contact with at least a subset of the one or more metal pads on the side of the substrate, and wherein the dielectric layer on the first side of the die is in direct physical contact with the dielectric layer on the side of the substrate; and applying heat to the die and the substrate.

Example 19 includes the method of example 17, or of any other example or embodiment herein, wherein providing a die further includes: providing a die that includes one or more vias that directly electrically couple, respectively, with at least one of the one or more metal pads on the first side, wherein each of the one or more vias electrically couple with a metal pad at the second side of the die.

Example 20 includes the method of example 17, or of any other example or embodiment herein, wherein the metal pads include copper.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.

These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.