Fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, has been introduced to replace a planar transistor. Although existing semiconductor devices and methods of fabricating semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, to introduce three dimensional nanostructure to a gate channel raises challenges in a semiconductor device process development. It is desired to have improvements in this area.

DETAILED DESCRIPTION

The present disclosure is directed to, but not otherwise limited to a metal-oxide-semiconductor field-effect transistor (MOSFET), for example a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present invention. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

FIG. 1Ais a top view of a design layout100of the FinFET device constructed according to some embodiments of the present disclosure. As shown inFIG. 1A, the design layout100includes a PMOS region102and an NMOS region104. The PMOS region102is formed in an n-well region, and the NMOS region104is formed in a p-well region. The PMOS region102may be configured on a first active region106, and the NMOS region104may be configured on a second active region108. As shown inFIG. 1A, the first active region106may include one or more active fin lines, e.g., fin lines106-1,106-2, and106-3. Similarly, the second active region108may also include one or more active fin lines, e.g., fin lines108-1,108-2, and108-3. The one or more fin lines are configured to extend along a first direction192.

Referring toFIG. 1A, one or more gates110-115are configured to extend along a second direction194and formed on the first active region106and the second active region108. The one or more gates110-115may be configured to be parallel to each other. The second direction194may be substantially perpendicular to the first direction192. In some embodiments, the one or more gates may be configured with the active regions to form one or more corresponding pull-up (PU) device, pull-down (PD) devices, and pass-gate (PG) devices in a cell. As shown inFIG. 1A, the doped regions, e.g., sources and drains, of each gate may be electrically and physically connected to the doped regions of the adjacent gate. For example, the sources of the gate111may be electrically and physically connected to the sources of the gate112by sharing a common source region defined in the active regions and positioned between the gate111and the gate112.

Still referring toFIG. 1A, various contacts120-127may be formed on the doped regions for electrically connecting the doped regions. For example, a contact120may be used to electrically connecting the doped drain region of the gate110to the doped drain region of the gate111in the first active region106. A contact121may be used to electrically connecting the doped drain region of the gate110to the doped drain region of the gate111in the second active region108. A contact123may be used to electrically connecting the doped drain region of the gate112to the doped drain region of the gate113in the first active region106. A contact124may be used to electrically connecting the doped drain region of the gate112to the doped drain region of the gate113in the second active region106. A contact126may be used to electrically connecting the doped drain region of the gate114to the doped drain region of the gate115in the first active region104. A contact127may be used to electrically connecting the doped drain region of the gate114to the doped drain region of the gate115in the second active region106.

One or more long contacts may be configured to extend along the second direction194and to extend over the first active region106and the second active region108. The long contacts have a first dimension extending along the first direction192and a second dimension extending along the second direction194, and the first dimension is substantially shorter than the second dimension. The one or more long contacts may be used to electrically connect the doped regions of two adjacent gates on both the first active region106and the second active region108. For example, a long contact122may be used to electrically connect doped source regions of the gate111and the gate112extending over the first active region106and the second active region108. A long contact125may be used to electrically connect doped source regions of the gate113and the gate114extending over the first active region106and the second active region108.

One or more gate contacts128-130may also be formed on the corresponding gates for routing the gates to the metal routing lines (not shown) correspondingly. The metal routing lines may be formed in one or more metal layers (not shown) on the gates.

Still referring toFIG. 1A, the design layout100may include more than one circuit, e.g., a first circuit131and a second circuit132. In some embodiments, an isolation feature, such as a dummy gate113may be formed between the first circuit131and the second circuit132.

FIG. 1Bis a cross sectional view of the FinFET device200along the line A-A inFIG. 1Aaccording to some embodiments of the present disclosure. As shown inFIG. 1B, the FinFET device200includes a substrate202. The substrate202may include bulk silicon (Si). Alternatively, an elementary semiconductor, such as silicon (Si) or germanium (Ge) in a crystalline structure, may also be included in the substrate202. The substrate202may also include a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), or combinations thereof. Possible substrate202may also include a semiconductor-on-insulator substrate, such as Si-on-insulator (SOI), SiGe-on-insulator (SGOI), Ge-on-insulator (GOI) substrates. For example, the SOI substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

Referring toFIG. 1B, various doped regions204may also be included in the substrate202depending on design requirements. The doped regions may be doped with p-type dopants, such as boron (B) or boron fluoride (BF3). The doped regions may also be doped with n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may also be doped with combinations of p-type and n-type dopants. The doped regions may be formed directly on the substrate202, in a p-well structure, in a n-well structure, in a dual-well structure, or using a raised structure.

Still referring toFIG. 1B, the FinFET device200may include one or more isolation regions206. The one or more isolation regions206are formed over the substrate202to isolate active regions. For example, each isolation region206separates the adjacent doped regions204in the substrate202from each other. The one or more isolation regions206may be formed using traditional isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the one or more active fins lines. In some examples, the isolation regions206may include silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof. The isolation regions206may be formed by any suitable process. In some examples, the formation of an STI includes a photolithography process, etching a trench in the substrate202(for example, by using a dry etching and/or wet etching), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials to form the isolation regions206. The filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. A chemical mechanical polishing (CMP) process may then be performed to remove excessive dielectric materials and planarize the top surface of the isolation regions206.

Referring toFIG. 1B, one or more gates110-115may be formed on the first active region106, the second active region108, and the doped regions204. The one or more gates110-115may include functional gates and/or dummy polygates. For example, gate113may be a dummy polygate configured to isolate the circuit131and the circuit132. The dummy polygate113may include polysilicon. Gates110-112, and114-115may be functional gates. The one or more gates110-115may be formed by a procedure including depositing, lithography patterning, and/or etching processes. The deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable methods, and/or combinations thereof.

Still referring toFIG. 1B, sidewall spacers216may be formed along each of the gates110-115. The sidewall spacers216may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The sidewall spacers216may also include multiple layers. Typical formation methods for the sidewall spacers216include depositing a dielectric material over each of the gates110-115. The dielectric material may be then anisotropically etched back. The etching back process may include a multiple-step etching to gain etch selectivity, flexibility and desired over-etch control. In some examples, one or more material layers (not shown), e.g., an interfacial layer, may also be formed between the gate and the corresponding sidewall spacers. The one or more material layers may include an interfacial layer and/or a high-k dielectric layer.

Still referring toFIG. 1B, one or more source/drain features208may be formed on the substrate202. In some embodiments, the formation processes of the one or more source/drain features208may include recessing to form source/drain trenches, and depositing to form the one or more source/drain features208in the source/drain trenches. In some examples, the one or more source/drain features208may be formed by epitaxially growing a semiconductor material layer in the source/drain recessing trenches. The one or more source/drain features208may be in-situ doped during the epitaxial process. For example, the epitaxially grown SiGe source/drain features may be doped with boron; and the epitaxially grown Si epitaxial source/drain features may be doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, an implantation process (i.e., a junction implant process) may be performed to dope the source/drain features. One or more annealing processes may be performed to activate source/drain epitaxial feature. The annealing processes may comprise rapid thermal annealing (RTA) and/or laser annealing processes. In some embodiments, a source/drain feature is a source region, and the other source/drain feature is a drain region. The adjacent source/drain features208are separated by a gate, such as a corresponding gate of the gates110-115as shown inFIGS. 1A-1B. As shown inFIG. 1B, one or more contacts120-126are formed on the one or more source/drain features208.

For further clarification,FIG. 1Cshows an enlarged top view of the highlighted structure300of the FinFET device inFIGS. 1A-1Baccording to some embodiments of the present disclosure. As shown inFIG. 1C, a gate dummy polygate113is formed on the active fin line106-3.FIG. 1Dis a cross sectional view of the structure300along the line A-A inFIG. 1Caccording to some embodiments of the present disclosure.FIG. 1Eis a cross sectional view of the structure300along the line B-B inFIG. 1Caccording to some embodiments of the present disclosure.

According to some embodiments of the present disclosure, an interlayer dielectric (ILD) layer218may be formed on the source/drain features208as shown inFIGS. 2A-2C. The ILD layer218may include silicon oxide, silicon oxynitride, or other suitable dielectric materials. The ILD layer218may include a single layer or multiple layers. The ILD layer218may be formed by a suitable technique, such as CVD, ALD, and spin-on dielectric, such as spin-on glass (SOG). After forming the ILD layer218, a chemical mechanical polishing (CMP) process may be performed to remove excessive ILD layer218and planarized the top surface of the ILD layer218.

Referring toFIGS. 3A-3D, a dummy polygate113for isolating the first circuit131and the second circuit132is removed to form a trench220. The dummy polygate113may be removed using any appropriate lithography and etching processes. The etching processes may include selective wet etch or selective dry etch, such that the dummy polygate113has an adequate etch selectivity with respect to the doped region204. After removing the dummy polygate113, one or more active fin lines in the first active region106and the second active region108are revealed. In some embodiments, the lithography process may include forming a photoresist layer (resist), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. As shown inFIG. 3A, the masking element may be used to expose a region302including the dummy polygate113by any appropriate dry etching and/or wet etching method.

Referring toFIGS. 4A-4D, the ILD layer218may be used as mask elements to further recess the trench220within the region302to form a trench222. In some embodiments, the remained spacer sidewalls216may also be used as mask elements to recess the trench220. This may be regarded as a self-aligned etching process. In some embodiments, the trench formed using the self-aligned process is a V-shaped trench222as shown inFIG. 4C. A portion of the active fin line106-3exposed in the trench220is removed as shown inFIGS. 4A-4B. As shown inFIG. 4C, a depth (d1) between a top surface of the source/drain features208and a bottom of the recessed V-shaped trench222may be in a range from about 50 nm to about 200 nm. In the present embodiment, a mask element with an exposed area substantially larger than the area of the dummy polygate may be used to etch the substrate to form the trench. For example, the area of the exposed region302ofFIGS. 1A, 3A, and/or4A is substantially greater than the area of the dummy polygate113and/or the trench220. This may provide a lithography friendly process.

Referring toFIGS. 5A-5D, one or more material layers224may be deposited in the trench222to form an isolation gate224. The isolation gate224may include a V-shaped bottom conformed to the V-shaped trench222as shown inFIGS. 5B and 5D. As shown inFIG. 5B, a depth (d2) between a top surface of the source/drain features208and a bottom of the isolation gate224may be in a range from about 50 nm to about 200 nm. In some embodiments as shown inFIGS. 5B and 5D, the one or more material layers deposited in the trench222may include a dielectric layer212and a material layer224. In some embodiments, the dielectric layer212may include an interfacial layer (IL) and/or a high-k (HK) dielectric layer formed in the trench222and conformed to the surfaces of the trench222. The IL layer may be deposited by any appropriate method, such as ALD, CVD, and/or PVD. The IL layer may include silicon oxide (SiO2), or silicon oxynitride (SiON). The HK dielectric layer may be deposited over the IL layer by any suitable techniques, such as ALD, CVD, metal-organic CVD, PVD, or a combination thereof. The HK dielectric layer may include one or more material selected from the group consisting of HfO2, Ta2O5, and Al2O3, and/or other suitable materials.

Still referring toFIGS. 5A-5E, the material layer224may include one or more metal gate (MG) layers, such as work function metal layer, low resistance metal layer, liner layer, wetting layer, and/or adhesion layer. In some embodiments, the work function metal layer may include one or more materials selected from the group consisting of Tin, TaN, TiAl, TaAl, Ti-included materials, Ta-included materials, Al-included materials, W-included materials, TiSi, NiSi, and PtSi. In some embodiments, the low resistance metal layer may include one or more materials selected from the group consisting of poly Si with silicide, Al-included materials, Cu-included materials, W-included materials, Ti-included materials, Ta-included materials, TiN, TaN, TiW, and TiAl. The MG layer may be formed by ALD, PVD, CVD, or other suitable process. A CMP process may be performed to remove excessive MG layer and provide a substantially planar top surface for the ILD layer218and the material layer224. The device work function determined by the work function metal layer may be in a range from about 4 eV to about 5 eV. The dielectric layer212is formed to provide sufficient insulating property to the material layer224filled in the trench222. After forming the dielectric layer212and the material layer224in the trench222, the circuit131and the circuit132may be sufficiently electrically isolated from each other.

In some embodiments, the materials, formation, and layout of the dielectric layer212and/or the material layer224may also be designed such that, a controlled bias voltage may be applied to the isolation gate224for effective isolation between the circuit131and the circuit132.

In some embodiments, the trench222may also be filled by a dielectric layer. The dielectric layer may be formed using similar method(s) and/or similar material(s) as those for the dielectric layer212as discussed previously. For example, the dielectric layer may include one or more materials selected from the group consisting of LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), HfO2, BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, and silicon oxynitride (SiON). The dielectric layer used to fill the trench222may include any suitable materials, such as silicon oxide, silicon nitride, silicon carbide, and/or silicon oxynitride. In some examples, the dielectric layer may be deposited to fully fill the trench222to provide sufficient electrical isolation property. In some embodiments when the isolation gate224includes a dielectric material filled in the trench222, the dielectric material used to fill in the trench222is different from the materials used to form the sidewall spacers216formed along the isolation gate224. In some examples, the dielectric layer may partially fill the trench222. For example a lower portion of the trench222may be filled by the dielectric layer, and an upper portion of the trench222may be filled by the dielectric layer212and the material layer224. The dielectric layer filled in the lower portion of the trench222may have similar function(s) as that of the isolation region (STI) to separate the circuit131and the circuit132. The dielectric layer may be formed by ALD, PVD, CVD, or other suitable process.

Referring toFIG. 5A, after forming the isolation gate224, the FinFET device200includes an isolation gate224configured to separate the circuit131and the circuit132. The gates110,111,112,114, and115are functional gates including functional metal gates. In some embodiments, the functional gates may include materials different from the materials in the isolate gate. As shown inFIGS. 5B and 5D, a height (h1) of the isolation gate224is substantially greater than a height (h2) of each of the sidewall spacers216formed along the isolation gate224. The height (h1) of the isolation gate224is also substantially greater than the height (hf) of the functional gates. In addition, the isolation gate224extends into the doped regions204and has a bottom lower than that of the functional gates110,111,112,14, and115. The material of the isolation gate224can be same material as functional gates, or have different material. Example materials include a purely dielectric material such as SiO2, SiON, Si3N4, high-K dielectric, or a combination thereof in the isolation gate224. In this example, the process flow will be:1. isolation gate poly removing and trench etch,2. dielectric deposition (re-fill the isolation gate), and3. functional gate formation (which may further include removing the poly gate, high-K gate dielectric, work-function metal, and the low resistance metal formation.)

FIG. 6Ais a top view of a design layout400of the FinFET device constructed according to some embodiments of the present disclosure.FIG. 6Bis a cross sectional view of the FinFET device650along the line A-A inFIG. 6Aaccording to some embodiments of the present disclosure. In some embodiments, the one or more gates located at the edges of the active fin lines, e.g., gate110and/or gate115ofFIG. 1A, may also be removed and the corresponding one or more trenches may be formed using the ILD layer and/or spacer sidewalls on the sides of the gates as mask elements. Dielectric materials, or dielectric materials and metal materials may be used to fill the one or more trenches to form the isolation gates, such as gate226and/or gate228located at the edge of the active fin lines. The formation processes and/or materials of the isolation gates226and/or228may be substantially similar to the formation processes and/or materials of the isolation gate224as discussed previously. As shown inFIG. 6A, the formation process of the isolation gate226at the edge of the active fin lines may include using a mask having an area of the exposed region304substantially greater than the area of the gate110. Similarly, the formation process of the isolation gate228at the edge of the active fin lines may also include using a mask having an area of the exposed region306substantially greater than the area of the gate115.

Referring toFIGS. 6A-6B, the FinFET device650includes an isolation gate224configured to separate the circuit131and the circuit132, and isolation gates226and228configured to be at the edges of the active fin lines. The gates111,112, and114are functional gates including functional metal gates. In some embodiments as shown inFIG. 6B, a height (h1) of the isolation gate224is substantially greater than a height (h2) of each of the sidewall spacers216formed along the isolation gate224. The sidewall spacers216and the isolation gates226and228located at the edges of the active fin lines may have asymmetric structures as shown inFIG. 6B. For example, sidewall spacer216aformed on outside of the isolation gate226or228, and an outside portion of the isolation gate226or228may have a height (h3), sidewall spacer216bformed on inside of the isolation gate226or228, and an inside portion of the isolation gate226or228may have a height (h4), and the height h3is substantially greater than the height h4. In addition, the isolation gate226or228may have a bottom lower than the bottom of the functional gates111,114, and higher than the bottom of the isolation gate224.

FIG. 7is a flow chart of an example method500for fabricating the FinFET device according to various aspects of the present disclosure. Method500includes a process502for providing a MOSFET device precursor, a process504for depositing an ILD layer over the source/drain features, a process506for removing the dummy polygate between the adjacent circuits to form a trench, a process508for recessing the trench using the ILD layer as mask elements, and a process510for depositing one or more material layers to form an isolation gate. It should be understood that additional processes may be provided before, during, and after the method500ofFIG. 7, and that some other processes may be briefly described herein.

At process502, the MOSFET device precursor, e.g., the FinFET device precursor200is provided. In some embodiments, the MOSFET device precursor includes a substrate, and one or more fins formed in a first active region and a second active region over the substrate. The one or more fins may be separated by one or more isolation regions. One or more gates may be formed over the one or more fins and extending over the first active region and the second active region. The one or more gates may be formed to extend along a direction that is substantially perpendicular to a direction along which the one or more fins may be formed to extend. Source/drain features may be formed in source/drain regions of the MOSFET device precursor.

At process504, an ILD layer is deposited over the surfaces of each of the fins. The ILD layer may include silicon oxide, silicon oxynitride, or other suitable dielectric materials. The ILD layer may include a single layer or multiple layers. The ILD layer may be formed by a suitable technique, such as CVD, ALD, and spin-on dielectric, such as SOG. A CMP process may be performed to provide a planar top surface of the ILD layer.

At process506, a dummy polygate may be removed to form a trench disposed between two adjacent circuits. The dummy polygate may be removed using any appropriate lithography and etching processes. The etching processes may include selective wet etch or selective dry etch. After removing the dummy polygate, one or more active fin lines in the active regions are revealed. In some embodiments, the lithography process may include forming a photoresist layer (resist), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. As shown inFIG. 3A, a masking element may be used to expose a region302including the dummy polygate113by any appropriate dry etching and/or wet etching method. The mask element may have an area substantially greater than the area of the dummy polygate.

At process508, the trench may be further recessed using the ILD layer as etching mask elements. The remained spacer sidewalls may also be used as mask elements to recess the trench. For example as shown inFIGS. 4A-4B, a portion of the active fin line106-3exposed in the trench220is removed. In the present embodiment, the mask element with an exposed area substantially greater than the area of the dummy polygate may be used to etch the substrate to form the trench.

At process510, one or more material layers may be deposited in the recessed trench to form an isolation gate between the two adjacent circuits. In some embodiments, the isolation gate may include a multiple layered structure of IL/HK/MG. In some embodiments, the isolation gate may include a dielectric material fully filled in the recessed trench. In some embodiments, the isolation gate may include a dielectric material filling a lower portion of the recessed trench, and an IL/HK/MG structure filling an upper portion of the recessed trench. The isolation gate may be formed to electrically isolate the two adjacent circuits. The one or more material layers may be formed using ALD, PVD, CVD, or other suitable process.

It is understood, however, that the present disclosure should not be limited to a particular type of device, except as specifically claimed. For example, the present disclosure is also applicable to other MOSFET device. It is also understood that additional steps can be provided before, during, and after the method, and some of the steps described can be replaced or eliminated for other embodiments of the method.

The present embodiments describe structures and methods for forming MOSFET devices using a self-aligned etching process to form an isolation gate for sufficient electrical isolation between adjacent transistors. The mechanisms involve using the remained ILD layer and the spacer sidewalls as etching mask elements to form a trench in the MOSFET device. One or more materials layers may then be deposited to fill the trench to provide sufficient electrical isolation between adjacent circuits. The mechanisms provide a lithography friendly patterning process with improved overlay control without using advanced lithography tools. Thus, no extra cost or area penalty is needed in the present embodiments. The mechanisms may also provide a fully balance source/drain epitaxial growth environment, which may improve device stability, chip speed, cell matching performance, and reduce standby specification. The various embodiments of the present disclosure may achieve an improved uniformity control on source/drain regions, and a fully uniform fin-end allocation for both reliability and process margin improvement.

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

The present disclosure provides a fin-like field-effect transistor (FinFET) device comprising a substrate including a first active region and a second active region spaced apart from each other in a first direction; a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction; one or more gates configured to extend over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and at least one functional gate; sidewall spacers formed on sides of the one or more gates; source/drain features formed on sides of the sidewall spacers; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the one or more gates. A first height of the first isolation gate is substantially greater than a second height of sidewall spacers formed on sides of the first isolation gate.

The present disclosure provides a method of forming a semiconductor device comprises providing a device precursor including a substrate including a first active region and a second active region spaced apart from each other in a first direction; a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction; and one or more gates including a polygate configured to extend over the first active region and the second active region, each of the one or more gates extending along the first direction. The polygate is configured to separate a first circuit and a second circuit. The method further comprises depositing an interlayer dielectric (ILD) layer over the substrate; removing the polygate to form a trench; recessing the trench to the substrate using the ILD layer as etching mask elements; and depositing one or more material layers in the recessed trench to form an isolation gate between the first circuit and the second circuit.

The present disclosure provides a method of forming a semiconductor device comprising forming a first group of fins in an n-well region and a second group of fins in a p-well region on a substrate; forming one or more isolation features to separate adjacent fins of the first group of fins and the second group of fins; forming one or more gates including a polygate on the first group of fins and the second group of fins, the polygate configured to separate a first circuit and a second circuit; forming sidewall spacers along the polygate; forming source/drain features on the substrate and on two sides of the polygate; depositing an interlayer dielectric (ILD) layer on the source/drain features; removing the polygate to form a trench between the first circuit and the second circuit; recessing the trench using the ILD layer as etching mask elements to a depth lower than bottoms of the source/drain features to form a V-shaped trench; and depositing one or more material layers in the V-shaped trench to form an isolation gate between the first circuit and the second circuit.

In some embodiments, the recessing the trench further comprises: using the ILD layers and the sidewall spacers along the polygate as etching mask elements.

In some embodiments, the depositing the one or more material layers includes depositing interfacial layer (IL)/high-k (HK) dielectric layer/metal gate (MG) in the V-shaped trench.

In some embodiments, the depositing the one or more material layers includes depositing a dielectric layer in the V-shaped trench.