Isolation connections for high-voltage power stage

Embodiments of a power stage for a direct current (DC)-DC converter and a DC-DC converter are disclosed. In an embodiment, a power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input DC voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage, and a low-side segment connected between the output signal of the power stage and ground. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection.

BACKGROUND

A power stage can be used, for example, in a direct current (DC)-DC converter, to convert a DC power source from one voltage level to another. A high-voltage (e.g., 5 volt (V) to 36 V) power stage may be formed by a stack of lower-voltage-rated (e.g., 2.5 V or 20V) switch devices alternately enabling switch segments between either the input supply or ground and the output. Each of the stacked switch devices may have a voltage rating that is lower than the voltage rating of the power stage. However, significant substrate injection can occur during switch deadtime, which is the interval during which no switch path is turned on. Therefore, there is a need for a power stage formed by stacked switch devices in which isolation connections of switch devices are appropriately biased to reduce or minimize effects of substrate injection, while preserving circuit operating efficiency and avoiding overvoltage stresses on the stacked switch devices.

SUMMARY

Embodiments of a power stage for a DC-DC converter and a DC-DC converter are disclosed. In an embodiment, a power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input DC voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage, and a low-side segment connected between the output signal of the power stage and ground. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection. Other embodiments are also described.

In an embodiment, one of the stacked transistors has an isolation terminal that is connected to the input DC voltage.

In an embodiment, one of the stacked transistors has an isolation terminal that is connected to a boot voltage, which is connected to an output signal of the power stage via a capacitor.

In an embodiment, one of the stacked transistors has an isolation terminal that is connected to a Schottky diode or a Zener diode.

In an embodiment, one of the stacked transistors has an isolation terminal that is connected to ground.

In an embodiment, the stacked transistors include field effect transistors (FETs).

In an embodiment, the FETs include a first FET having a drain terminal that is connected to the input DC voltage and a second FET having a drain terminal that is connected to a source terminal of the first FET.

In an embodiment, the first FET has an isolation terminal that is connected to the input DC voltage.

In an embodiment, the first FET has an isolation terminal that is connected to a source terminal of a third FET.

In an embodiment, the second FET has an isolation terminal that is connected to a boot voltage, which is connected to an output signal of the power stage via a capacitor.

In an embodiment, the FETs further include a first FET having a drain terminal that is connected to the output signal of the power stage and a second FET having a drain terminal that is connected to a source terminal of the first FET and a source terminal that is connected to ground.

In an embodiment, the first FET has an isolation terminal that is connected to a Schottky diode or a Zener diode.

In an embodiment, the second FET has an isolation terminal that is connected to ground or a positive fixed voltage.

In an embodiment, a high-voltage (HV) power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input direct current (DC) voltage is received, a high-side segment connected between the input DC voltage and an output signal of the HV power stage, and a low-side segment connected between the output signal of the HV power stage and ground. Each of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection.

In an embodiment, the stacked transistors of the high-side segment include a first LV N-channel FET having a drain terminal that is connected to the input DC voltage and a second LV N-channel FET having a drain terminal that is connected to a source terminal of the first LV N-channel FET. The stacked transistors of the low-side segment include a third LV N-channel FET having a drain terminal that is connected to a source terminal of the second LV N-channel FET and a fourth LV N-channel FET having a drain terminal that is connected to a source terminal of the third LV N-channel FET and a source terminal that is connected to ground.

In an embodiment, the first LV N-channel FET has an isolation terminal that is connected to the input DC voltage.

In an embodiment, the second LV N-channel FET has an isolation terminal that is connected to a boot voltage, which is connected to an output signal of the HV power stage via a capacitor.

In an embodiment, the third LV N-channel FET has an isolation terminal that is connected to a Schottky diode or a Zener diode.

In an embodiment, the fourth LV N-channel FET has an isolation terminal that is connected to ground.

In an embodiment, a DC-DC converter includes a power stage including an input terminal from which input power of the DC-DC converter with an input direct current (DC) voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage and a low-side segment connected between the output signal of the power stage and ground, and an inductor-capacitor (LC) network connected to the power stage. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection. The power stage and the LC network are configured to convert the input power with the input DC voltage into an output signal with an output DC voltage.

DETAILED DESCRIPTION

FIG.1is a schematic block diagram of a DC-DC converter100in accordance with an embodiment of the invention. The DC-DC converter converts input power with an input DC voltage, Vin, which is received from an input electrical terminal or node102into an output signal with a desired output DC voltage, Vout, which is output from an output electrical terminal or node104. The DC-DC converter can be used in various applications, such as automotive applications, communications applications, industrial applications, medical applications, computer applications, and/or consumer or appliance applications. In the embodiment depicted inFIG.1, the DC-DC converter includes a control circuit106, a power stage108, and an inductor-capacitor (LC) network110. In some embodiments, the DC-DC converter is included in a computing device, such as a smartphone, a tablet computer, a laptop, etc. In some embodiments, the DC-DC converter is implemented in a substrate, such as a semiconductor wafer. In an embodiment, the DC-DC converter is constructed as a stand-alone semiconductor IC chip. In some embodiments, the DC-DC converter is a Buck DC-DC converter in which the input voltage, VIN, is higher than the output voltage, VOUT. Although the DC-DC converter is shown inFIG.1as including certain circuit elements, in other embodiments, the DC-DC converter may include one or more additional circuit elements. For example, although the DC-DC converter is shown inFIG.1as an inductive DC-DC converter and including the LC network110, in other embodiments, the DC-DC converter is a switched capacitor DC-DC converter and does not include the LC network110.

In the embodiment depicted inFIG.1, the control circuit106is configured to control the operation of the power stage108. The control circuit may include a transconductance amplifier, a comparator, and/or a multiplexer.

In the embodiment depicted inFIG.1, the power stage108is connected to the input electrical terminal102that is configured to receive the input DC signal with the input voltage, VIN, to the ground, and to the LC network110. In some embodiments, the power stage108and the LC network110are configured to convert the input DC signal with the input voltage, VIN, into the output DC signal with the output voltage, VOUT, using stacked semiconductor devices (e.g., stacked transistors, such as, field effect transistors (FETs)) that may be connected in series) in at least one switch segment. In some embodiments, the power stage108is constructed as a semiconductor IC chip. For example, the power stage108is constructed as a first semiconductor IC chip, while the control circuit106and/or the LC network110is constructed as a second semiconductor IC chip. In some embodiments, the control circuit106, the power stage108, and the LC network110are constructed in the substrate of the same semiconductor IC chip. In the embodiment depicted inFIG.1, the output signal, LX, of the power stage108is input into the LC network110. The power stage108can be used in an inductive DC-DC converter or a switched capacitor DC-DC converter.

In the embodiment depicted inFIG.1, the LC network110is connected to the output electrical terminal104from which the output DC signal with the output voltage, VOUT, is output. The LC network110includes an inductor112and a capacitor114. Although the LC network110is shown in FIG.1as including certain circuit elements, in other embodiments, the LC network110may be implemented differently from the embodiment depicted inFIG.1.

FIG.2depicts a power stage208, which is an embodiment of the power stage108depicted inFIG.1. In the embodiment depicted inFIG.2, the power stage208is a high-voltage (HV) power stage that includes four lower-voltage rated FETs222,224,226,228that are in a high-side (HS) segment220-1connected between the input DC voltage, VIN, and the output signal, LX, of the power stage208or a low-side (LS) segment220-2connected between the output signal, LX, of the power stage208and ground. Although the power stage208is shown inFIG.2as including four FETs, in other embodiments, the power stage208includes more than four FETs or fewer than four FETs. In addition, although each of the high-side (HS) and the low-side (LS) segments of the power stage208is shown inFIG.2as including two FETs, in other embodiments, one of the high-side (HS) segment220-1and the low-side (LS) segment220-2of the power stage208includes two or more FETs. For example, the high-side (HS) segment220-1of the power stage208includes two stacked FETs, while the low-side (LS) segment220-2of the power stage208includes only one FET. In another example, the low-side (LS) segment220-2of the power stage208includes two stacked FETs, while the high-side (HS) segment220-1of the power stage208includes only one FET. The power stage208can be used in high-voltage (HV) applications in which the FET drain-source voltage, VDS, capability is much higher than the FET gate-source voltage, VGScapability. In some embodiments, the input voltage, VIN, is at 36V, and each of the FETs222,224,226,228has a voltage rating (VDS,MAX) of 20V or 24V. In the embodiment depicted inFIG.2, in addition to gate (G), source (S), and drain (D) terminals, each of the FETs222,224,226,228has an isolation (Iso) connection or terminal (I) to isolate the respective FET from other device(s) constructed in the same substrate and to collect currents generated from drain-substrate PN junction forward bias. Each of the FETs222,224,226,228also has a limitation on the maximum voltage allowed between its isolation and body or bulk terminals. In the embodiment depicted inFIG.2, the Iso terminals of the FETs222,224,226,228are connected to voltages that reduce or minimize effects of substrate injection, while preserving circuit operating efficiency and avoiding overvoltage stresses on the FETs222,224,226,228. The power stage208depicted inFIG.2is one possible embodiment of the power stage108depicted inFIG.1. However, the power stage108depicted inFIG.1is not limited to the embodiment shown inFIG.2.

In the embodiment depicted inFIG.2, the high-side (HS) segment220-1includes stacked FETs222,224connected between the input DC voltage, VIN, and the output signal, LX, of the power stage208. The individual maximum voltage rating of the FETs222,224does not meet the maximum voltage rating required for the high-side (HS) segment220-1(approximately VIN). The low-side (LS) segment220-2includes stacked FETs226,228connected between the output signal, LX, of the power stage208and ground. The individual maximum voltage rating of the FETs226,228does not meet the maximum voltage rating required for the low-side (LS) segment220-2(approximately VIN).

In the embodiment depicted inFIG.2, the FET222is an N-channel or N-type high-side (HS) FET that has a drain terminal (D) connected to the input DC signal with the input voltage, VIN, a source terminal (S) connected to a drain terminal (D) of the FET224, and a body or bulk terminal (B) connected to the source terminal (S) of the FET222. In the embodiment depicted inFIG.2, the FET222has an isolation terminal (I) that is connected to the input DC signal with the input voltage, VIN. A parasitic NPN transistor232with a parasitic resistor R1is formed between the body or bulk terminal (B), the drain terminal (D), and the isolation terminal (I) of the FET222. A parasitic PNP transistor236is formed between the body or bulk terminal (B) and the isolation terminal (I) of the FET222. A parasitic NPN transistor238is formed between the source terminal (S) of the FET222and the parasitic NPN transistor232. A parasitic diode234is formed between the substrate and the isolation terminal (I) of the FET222of the power stage208. The voltage at the isolation terminal (I) of the FET222may be between 18V and 36V. By biasing the isolation terminal (I) of the FET222, the parasitic NPN transistors232,238and the parasitic PNP transistor236can be prevented from being turned on to minimize the power dissipation, to avoid performance degradation from substrate injection, and to avoid excessive voltage between the isolation terminal (I) and the source terminal (S) and the body or bulk terminal (B) of the FET222.

In the embodiment depicted inFIG.2, the FET224is an N-channel or N-type high-side (HS) FET that has a drain terminal (D) connected to the source terminal (S) of the FET222, a source terminal (S) connected to a drain terminal (D) of the FET226, and a body or bulk terminal (B) connected to the source terminal (S) of the FET224. In the embodiment depicted inFIG.2, the FET224has an isolation terminal (I) that is connected to a boot voltage, VBOOT. A parasitic NPN transistor242with a parasitic resistor R2is formed between the body or bulk terminal (B), the drain terminal (D), and the isolation terminal (I) of the FET224. A parasitic PNP transistor246is formed between the body or bulk terminal (B) and the isolation terminal (I) of the FET224. A parasitic NPN transistor248is formed between the source terminal (S) of the FET224and the parasitic NPN transistor242. A parasitic diode244is formed between the substrate and the isolation terminal (I) of the FET224of the power stage208. The boot voltage, VBOOT, may be connected to the output signal, LX, of the power stage208via a capacitor240. In some embodiments, with a load current, during a deadtime of the FET224, the bulk-drain junction within the FET224is forward biased, and the boot voltage, VBOOT, stored on the capacitor240is discharged. The voltage at the isolation terminal (I) of the FET224may swing between 5V and 41V in each switch cycle. By biasing the isolation terminal (I) of the FET224, the parasitic NPN transistors242,248and the parasitic PNP transistor246can be controlled (e.g., prevented from being turned on) to minimize the power dissipation, to avoid performance degradation from substrate injection, and to avoid excessive voltage between the isolation terminal (I) and the source terminal (S) and the body or bulk terminal (B) of the FET224.

In the embodiment depicted inFIG.2, the FET226is an N-channel or N-type low-side (LS) FET that has a drain terminal (D) connected to the source terminal (S) of the FET224, a source terminal (S) connected to a drain terminal (D) of the FET228, and a body terminal (B) connected to the source terminal (S) of the FET226. In the embodiment depicted inFIG.2, the FET226has an isolation terminal (I) that is connected to a diode250, which may be a Schottky diode or a Zener diode. A parasitic NPN transistor252with a parasitic resistor R3is formed between the body or bulk terminal (B), the drain terminal (D), and the isolation terminal (I) of the FET226. A parasitic PNP transistor256is formed between the body or bulk terminal (B) and the isolation terminal (I) of the FET226. A parasitic NPN transistor258is formed between the source terminal (S) of the FET226and the parasitic NPN transistor252. A parasitic diode254is formed between the substrate and the isolation terminal (I) of the FET226of the power stage208. In the embodiment depicted inFIG.2, the Schottky or Zener diode250is connected to the source terminal (S) of the FET226, for example, to pull up the isolation terminal (I) of the FET226and to bypass the base and the emitter of the parasitic PNP transistor256, thus preventing the parasitic PNP transistor256from turning on. In some embodiments, the anode of the Schottky or Zener diode250is connected to a fixed voltage, for example, 5 volts (V). In some embodiments, the isolation terminal (I) of the FET226is connected to a fixed voltage that is greater than input DC voltage, Vin, to collect current injected by the FET228. By biasing the isolation terminal (I) of the FET226, the parasitic NPN transistors252,258and the parasitic PNP transistor256can be prevented from failing to be turned on to minimize the power dissipation, to avoid performance degradation from substrate injection, and to avoid excessive voltage between the isolation terminal (I) and the source terminal (S) and the body or bulk terminal (B) of the FET226.

In the embodiment depicted inFIG.2, the FET228is an N-channel or N-type low-side (LS) FET that has a drain terminal (D) connected to the source terminal (S) of the FET226, a source terminal (S) connected to a fixed voltage, for example, the ground (zero volt), and a body or bulk terminal (B) connected to the source terminal (S) of the FET228. In the embodiment depicted inFIG.2, the FET228has an isolation terminal (I) that is connected to the ground (zero volts). A parasitic NPN transistor262with a parasitic resistor R4is formed between the body or bulk terminal (B), the drain terminal (D), and the isolation terminal (I) of the FET228. A parasitic PNP transistor266is formed between the body or bulk terminal (B) and the isolation terminal (I) of the FET228. A parasitic NPN transistor268is formed between the source terminal (S) of the FET228and the parasitic NPN transistor262. A parasitic diode264is formed between the substrate and the isolation terminal (I) of the FET228of the power stage208. When the isolation terminal (I) of the FET228is connected to the ground, injected current is efficiently collected only to a certain level, and, at injection levels higher than that level, injected carriers may propagate to adjacent regions. In some embodiments, the isolation terminal (I) of the FET228is connected to a fixed positive voltage, which can have better collection but worse power dissipation. By biasing the isolation terminal (I) of the FET228, the parasitic NPN transistor268and the parasitic PNP transistor266can be prevented from failing to be turned on to minimize the power dissipation, to avoid performance degradation from substrate injection, and to avoid excessive voltage between the isolation terminal (I) and the source terminal (S) and the body or bulk terminal (B) of the FET228.

In the power stage208depicted inFIG.2, the connection or the voltage bias of the isolation terminals (I) of the FETs222,224,226,228may be independent from each other. For example, the isolation terminal (I) of the FET222is connected to the input DC signal with the input voltage, VIN, as depicted inFIG.2, while the connection or the voltage bias of the isolation terminals (I) of the FETs224,226,228are different from the connection or the voltage bias as depicted inFIG.2. In another example, the isolation terminal (I) of the FET224is connected to the boot voltage, VBOOT, as depicted inFIG.2, while the connection or the voltage bias of the isolation terminals (I) of the FETs222,226,228are different from the connection or the voltage bias as depicted inFIG.2. In another example, the isolation terminal (I) of the FET226is connected to the Schottky or Zener diode250as depicted inFIG.2, while the connection or the voltage bias of the isolation terminals (I) of the FETs222,224,228are different from the connection or the voltage bias as depicted inFIG.2. In another example, the isolation terminal (I) of the FET228is connected to ground as depicted inFIG.2, while the connection or the voltage bias of the isolation terminals (I) of the FETs222,224,226are different from the connection or the voltage bias as depicted inFIG.2. In some embodiments, the isolation terminals (I) of the HS FETs222,224are connected as depicted inFIG.2, while the isolation terminals (I) of the LS FETs226,228are connected differently from the manner as depicted inFIG.2. In some embodiments, the isolation terminals (I) of the LS FETs226,228are connected as depicted inFIG.2, while the isolation terminals (I) of the HS FETs222,224are connected differently from the manner as depicted inFIG.2. In some embodiments, the power stage208only includes one LS FET, and the isolation terminals (I) of the HS FETs222,224are connected as depicted inFIG.2. In some embodiments, the power stage208only includes one HS FET, and the isolation terminals (I) of the LS FETs226,228are connected as depicted inFIG.2.

In the embodiment depicted inFIG.2, gate terminals (G) of the FETs222,224,226,228may be connected to different voltages and are driven by different signals (e.g., pulse-width modulation (PWM) signals).

FIG.3depicts a cross section of a FET300, which is an embodiment of the FETs222,224,226,228of the power stage208depicted inFIG.2. The FET300depicted inFIG.3is one possible embodiment of the FETs222,224,226,228of the power stage208depicted inFIG.2. However, the FETs222,224,226,228of the power stage208depicted inFIG.2are not limited to the embodiment shown inFIG.3. In the embodiment depicted inFIG.3, the FET300is formed on a P+ substrate layer302and includes a first epitaxially grown P-type region labeled “Pepi-1,” an n-buried layer (NBL)304, a second epitaxially grown P-type region labeled “Pepi-2,” a P− region306, N-well regions308,310, p-type doped bulk region312, a high voltage n-type well (HVNW) region314, N+ regions316,318,320, a P+ region322, shallow trench isolation (STI) regions324,326,328, and a gate region330. In the embodiment depicted inFIG.3, the N+ region316connects to an isolation terminal of the FET300, the P+ region322forms a body terminal of the FET300, the N+ region318forms a source terminal of the FET300, and the N+ region320forms a drain terminal of the FET300. A “main” metal-oxide-semiconductor field-effect transistor (MOSFET) M1operates within the FET300. An NPN transistor is between the drain terminal (as an emitter), the bulk terminal (or a base) and the Isolation terminal (as a collector). Parasitic diodes D1, D2and a parasitic resistor R1exist in the FET300between various regions. When the drain-bulk junction is forward biased (e.g., in an LS FET (e.g., the FET228depicted inFIG.2), the bulk region is connected to GND, the drain can be at, for example, about −0.7V when this condition occurs), current flows from the drain region to the bulk region, but also (through NPN action), current is collected at the isolation terminal. In some embodiments, the intent of the isolation connection for the FET300is to connect this isolation terminal to GND such that the VCE (the voltage measured between the collector and emitter) of the parasitic NPN (Q1) is low and power dissipation is low. If there is a risk that the parasitic NBL resistance is too high (thus forward biasing a second parasitic NPN Q2), this isolation connection can instead be connected to a convenient higher voltage (e.g., higher than 0V (GND)). Although the FET300is shown inFIG.3as including certain circuit elements, in other embodiments, the FET may include one or more additional circuit elements.