Semiconductor device and method for manufacturing the same

A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-086341, filed Mar. 24, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

2. Description of the Related Art

In recent years, NAND type flash memories have been commonly used as electrically erasable nonvolatile semiconductor storage devices. The NAND type flash memory includes a large number of NAND cell units. Each NAND cell unit is configured so that a plurality of memory cells connected together in series are provided between select transistors. A control gate line (word line) is connected to each memory cell. A select gate line is connected to each select transistor.

In the NAND type flash memory, each of the select gate lines is wider than each of the control gate lines. That is, the control gate lines are arranged at the same pitch, and the select gate lines are arranged at a pitch different from that of the control gate lines. Thus, the select gate lines disturb the periodicity of the line arrangement. As a result, a decrease in the size of the semiconductor device affects the resolution or margin in a lithography step. This makes it difficult to accurately form the patterns of select gate lines and control gate lines.

Jpn. Pat. Appln. KOKAI Publication No. 2003-51557 discloses a structure in which two select gate lines having the same line width as that of control gate lines are provided in place of one select gate line with a large line width. This structure enables the select gate lines to be arranged at the same pitch as that of the control gate lines.

However, in this proposal, the two select gate lines are connected together using only a conductive portion that contacts the top surfaces of both select gate lines. That is, the two select gate lines are separated from each other. Accordingly, in the areas of the two select gate lines other than those in which the connecting conductive portion is formed, separate control signals propagate through the two select gate lines. Thus, disadvantageously, operational timings for the two select transistors corresponding to the two select gate lines may deviate from each other. This may prevent high-speed operations.

Thus, problems with the conventional art are that it is difficult to accurately form patterns and that the operational timings for the two select transistors may deviate from each other to prevent appropriate desired operations.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to a first aspect of the present invention includes a memory cell gate structure having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on the first gate electrode, and a second gate electrode formed on the second gate insulating film; a select gate structure having a third gate insulating film formed on the semiconductor substrate and a third gate electrode formed on the third gate insulating film and including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion; a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion of the select gate structure; and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion of the select gate structure.

A method for manufacturing a semiconductor device according to a second aspect of the present invention includes forming a memory cell gate structure, a first dummy gate structure, and a second dummy gate structure each having a first gate insulating film formed on a semiconductor substrate, a first gate electrode film formed on the first gate insulating film, a second gate insulating film formed on the first gate electrode film, and a second gate electrode film formed on the second gate insulating film; forming a first impurity diffusion layer and a second impurity diffusion layer, the first impurity diffusion layer being formed in a surface area of the semiconductor substrate and being located at a portion which corresponds to an area between the memory cell gate structure and the first dummy gate structure, the second impurity diffusion layer being formed in a surface area of the semiconductor substrate and being located at a portion which corresponds to an area between the first dummy gate structure and the second dummy gate structure; removing at least the second gate electrode films and second gate insulating films of the first and second dummy gate structures to form a hole; and forming a conductive film in the hole to form a select gate structure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is an equivalent circuit diagram showing the basic configuration of a semiconductor device (NAND type flash memory) according to a first embodiment of the present invention.FIG. 2is a plan view schematically showing the configuration of the NAND type flash memory according to the present embodiment (however, bit lines are not shown).

As shown inFIGS. 1 and 2, each NAND cell unit is configured so that memory cells M1to M8connected together in series are provided between select transistors S1and S2. The memory cells M1to M8and the select transistors S1and S2are formed in an element region. Adjacent element regions are separated from each other by an isolation region (isolation insulating film). Select gate lines SG1and SG2are connected to the select transistors S1and S2, respectively. Control gate lines (word lines) CG1to CG8are connected to the memory cells M1to M8, respectively. Bit lines BL1and BL2are each connected to each select transistor S1via a bit line contact BC. A source line (not shown) is connected to select transistors S2.

As described later, the select transistors S1and S2are each formed substantially of two MIS transistors having a common gate electrode. Therefore, each of the select transistors S1and S2functions as one select transistor. Thus, on the drawings, these two MIS transistors are drawn as one select transistor. Further, each NAND cell unit is shown containing eight memory cells, but the number of memory cells is not limited to eight.

FIGS. 6 to 8are sectional views schematically showing the configuration of the NAND flash memory according to the present embodiment.FIGS. 6,7, and8correspond to a cross section taken along line A-A inFIG. 2(along a bit line direction), a cross section taken along line B-B inFIG. 2(along a word line direction), and a cross section taken along line C-C inFIG. 2(along the word line direction).

A plurality of memory cell gate structure101are formed in association with the plurality of memory cells M1to M8, shown inFIG. 2. A select gate structure103is formed in association with each of the select transistors S1and S2. As shown inFIGS. 7 and 8, a silicon substrate (semiconductor substrate)11has an element region11aseparated by isolation trenches. A memory cell gate structure101and a select gate structure103are formed on the element region11a. The isolation trenches are filled with an isolation insulating film17.

As shown inFIGS. 6 and 7, each memory cell gate structure101is formed of a tunnel insulating film (first gate insulating film)12aformed on the silicon substrate11, a floating gate electrode (first gate electrode)13aformed on the tunnel insulating film12a, an inter-electrode insulating film (second gate insulating film)14aformed on the floating gate electrode13a, and a control gate electrode (second gate electrode)15aformed on the inter-electrode insulating film14a. Further, a stopper film16for CMP (Chemical Mechanical Polishing) is formed on the control gate electrode15a.

As shown inFIGS. 6 and 8, the select gate structure103is formed of a gate insulating film (third gate insulating film)12bformed on the silicon substrate11and a gate electrode (third gate electrode)18formed on the gate insulating film12b. In the present embodiment, the gate insulating film12bof the select gate structure103is formed during the same step as that in which the tunnel insulating film12aof the memory cell gate structure101is formed. The gate insulating film12band the tunnel insulating film12ause the same film thickness and the same material. Further, in the present embodiment, the gate electrode18of the select gate structure103is formed of a lower conductive film13band an upper conductive film25. The lower conductive film13bis formed during the same step as that in which the floating gate electrode13aof the memory cell gate structure101is formed. The lower conductive film13bis also formed of the same material as that of the floating gate electrode13a. The upper conductive film25is formed after the formation of the memory cell gate structure101.

In a direction parallel to a main surface of the silicon substrate11, the gate electrode18is composed of a first electrode portion P1, a second electrode portion P2, and a third electrode portion P3between the first electrode portion P1and the second electrode portion P2. The gate insulating film12bis formed between the electrode portion P1and the silicon substrate11and between the electrode portion P2and the silicon substrate11. However, instead of the gate insulating film12b, an insulating film (insulating portion22cdescribed later) different from the gate insulating film12bis formed between the electrode portion P3and the silicon substrate11.

An insulating portion22ais formed in an area between the adjacent memory cell structures101. An insulating portion (first insulating portion)22bis formed in an area between the memory cell gate structure101and the electrode portion P1of the select gate structure103. A top surface of the insulating portion22bhas the same height as that of a top surface of the gate electrode18. The insulating portion22c(second insulating portion) is formed in an area between the electrode portion P1and electrode portion P2of the select gate structure103and is located under the electrode portion P3. A top surface of the insulating portion22cis lower than the top surfaces of the insulating portions22aand22b. In the present embodiment, the insulating portions22a,22b, and22care formed of an interlayer insulating film22.

The electrode portions P1and P2and the memory gate structure101have an equal width (in the bit line direction). Further, the insulating portions22a,22b, and22chave an equal width (in the bit line direction). That is, the spacing between the adjacent memory cell gate structures101, the spacing between the memory cell gate structure101and the electrode portion P1, and the spacing between the electrode portions P1and P2are equal. Accordingly, the memory cell gate structures101and the electrode portions P1and P2are arranged at the same pitch.

An impurity diffusion layer21afor source and drain is formed in a surface area of the silicon substrate11under the insulating portion22a. In other words, the impurity diffusion layer21ais formed in a surface area of the silicon substrate11which area corresponds to the area between the adjacent memory cell gate structures101. Further, an impurity diffusion layer21bfor source and drain (first impurity diffusion layer) is formed in a surface area of the silicon substrate11under the insulating portion22b. In other words, the impurity diffusion layer21bis formed in a surface area of the silicon substrate11which area corresponds to the area between the memory cell gate structure101and the electrode portion P1. Furthermore, an impurity diffusion layer21cfor source and drain (second impurity diffusion layer) is formed in a surface area of the silicon substrate11under the insulating portion22c. In other words, the impurity diffusion layer21cis formed in a surface area of the silicon substrate11which area corresponds to the area between the electrode portions P1and P2.

When an on voltage is applied to the gate electrode18of the select gate structure103, a channel is induced in an area located under the electrode portion P1. A channel is also induced in an area located under the electrode portion P2. These channels are coupled together via the impurity diffusion layer21c. Thus, the application of the on voltage to the gate electrode18turns on the entire select transistor S1(or entire select transistor S2) having the select gate structure103. That is, the select transistor S1(or select transistor S2) is formed substantially of two MIS transistors but share the gate electrode18. Consequently, the select transistor S1or S2functions as one select transistor.

With reference toFIGS. 3 to 6, description will be given below of a method for manufacturing the NAND type flash memory according to the present embodiment.FIGS. 3 to 6correspond to a cross section taken along line A-A inFIG. 2(cross section taken in the bit line direction).

First, as shown inFIG. 3, a silicon oxide film of thickness 10 nm is formed by a thermal oxidation method on the surface of the p-type silicon substrate (semiconductor substrate)11as the tunnel insulating film (first gate insulating film)12. Subsequently, a phosphorous-doped polycrystal silicon film of thickness 40 nm is deposited by an LPCVD (Low Pressure Chemical Vapor Deposition) method on the tunnel insulating film12as the floating gate electrode film (first gate electrode film)13. Then, the floating gate electrode film13, the tunnel insulating film12, and the silicon substrate11are sequentially etched using a mask pattern (not shown) extended in the bit line direction as a mask. A plurality of element regions and a plurality of isolation trenches are thus formed. Moreover, the isolation trenches are filled with an isolation insulating film (isolation insulating film17, shown inFIGS. 7 and 8) to form isolation regions.

Then, an ONO film of a silicon oxide film/silicon nitride film/silicon oxide film structure is formed by the LPCVD method as the inter-electrode insulating film (second gate insulating film)14. Subsequently, a phosphorous-doped polycrystal silicon film of thickness 200 nm is deposited by the LPCVD method on the inter-electrode insulating film14as the control gate electrode film (second gate electrode film)15. Moreover, a silicon nitride film is formed by the LPCVD method as a stopper film16for CMP.

Then, the stopper film16, the control gate electrode film15, the inter-electrode insulating film14, the floating gate electrode film13, and the tunnel insulating film12are sequentially etched by an RIE (Reactive Ion Etching) method using a resist pattern (not shown) extended in the word line direction as a mask. This forms a plurality of memory cell gate structures101each formed of the tunnel insulating film12a, the floating gate electrode film13a, the inter-electrode insulating film14a, and the control gate electrode film15a. At the same time, dummy gate structures102aand102bare formed which are each formed of the tunnel insulating film12b, the floating gate electrode film13b, the inter-electrode insulating film14b, and the control gate electrode film15b.

The mask resist pattern is formed so that the memory cell gate structure101and the dummy gate structures102aand102bhave an equal width in the bit line direction. The mask resist pattern is formed so that the spacing between the adjacent memory cell gate structures101, the spacing between the memory cell gate structure101and the dummy gate structure102a, and the spacing between the dummy gate structures102aand102bare equal. As a result, the memory cell gate structures101and the dummy gate structures102aand102bare formed at the same pitch. This makes it possible to prevent a reduced resolution or margin in a lithography step executed in the formation of a resist pattern. It is thus possible to accurately form memory gate structures101and dummy gate structures102aand102b.

Then, as shown inFIG. 4, impurity diffusion layers21a,21b, and21cfor source and drain are formed using an ion implantation method. The impurity diffusion layer21ais formed in the surface area of the silicon substrate11between the adjacent memory cell gate structures101. The impurity diffusion layer21bis formed in the surface area of the silicon substrate11between the memory cell gate structure101and the dummy gate structure102a. The impurity diffusion layer21cis formed in the surface area of the silicon substrate11between the dummy gate structures102aand102b.

Then, an inter-layer insulating film22is formed by the LPCVD method all over the surface of the resulting structure. Subsequently, the inter-layer insulating film22is polished by the CMP method using the stopper film16as a CMP stopper. The inter-layer insulating film22is thus flattened. As a result, the area between the adjacent memory cell gate structures101is filled with the insulating portion22a. The area between the memory cell gate structure101and the dummy gate structure102ais filled with the insulating portion22b. The area between the dummy gate structures102aand102bis filled with the insulating portion22c.

Then, as shown inFIG. 5, the resist pattern23is used as a mask to etch, by the RIE method, the stopper film16, control gate electrode film15, and inter-electrode insulating film14formed in the area corresponding to the dummy gate structures102aand102b. At the same time, the insulating portion22cis also etched to have its height reduced. The floating gate electrode film13and the tunnel insulating film12are not etched but left as they are. Holes (or trenches)24are thus formed.

Then, as shown inFIG. 6, the resist pattern23is removed and then a phosphorous-doped polycrystal silicon film is deposited as a conductive film25by the LPCVD method all over the surface of the resulting structure. Subsequently, the CMP method is used to polish and flatten the conductive film25. This results in a structure in which the holes24are filled with the conductive film25. This forms gate electrodes18each composed of the floating gate electrode film13band conductive film25to obtain select gate structures103.

As described above, according to the present embodiment, after the memory cell gate structures101and the dummy gate structures102aand102bhave been formed, the electrode portions P1and P2are formed in the area corresponding to the dummy gate structures102aand102b. Further, the electrode portion P3is formed between the electrode portions P1and P2. Since the memory cell gate structures101and the dummy gate structures102aand102bare formed at the same pitch, it is possible to prevent a reduced resolution or margin in the lithography step. In the select gate structure103, the presence of the electrode portion P3between the electrode portions P1and P2makes the select gate structure103wider than the memory cell gate structure101. Therefore, the present embodiment makes it possible to form a select gate structure103wider than the memory cell gate structure101, while avoiding a decrease in resolution or margin in the lithography step.

Further, in the present embodiment, the electrode portions P1, P2, and P3are integrated together to form the gate electrode18of the select gate structure103. This enables a control signal to be simultaneously supplied to the electrode portions P1and P2. It is thus possible to prevent operational timings for an MIS transistor corresponding to the electrode portion P1from deviating from those for an MIS transistor corresponding to the electrode portion P2. As a result, appropriate desired operations are ensured.

Therefore, the present embodiment provides a NAND type flash memory which exhibits an excellent pattern accuracy and which can perform appropriate desired operations.

Further, in the present embodiment, the gate insulating film12bof the select gate structure103is formed of the same material as that of the tunnel insulating film12aof the memory cell gate structure101and during the same step in which the tunnel insulating film12ais formed. This eliminates the need for the formation of a new gate insulating film for the select gate structure103. It is thus possible to simplify the manufacturing process.

FIGS. 9 and 10are sectional views schematically showing a method for manufacturing a semiconductor device (NAND type flash memory) according to a second embodiment of the present invention. An equivalent circuit diagram and plan view for the second embodiment are similar toFIGS. 1 and 2, shown in the first embodiment. Further, the basic configuration and manufacturing method according to the second embodiment are similar to those according to the first embodiment. The description of the matters described in the first embodiment is thus omitted.

First, such a structure as shown inFIG. 4is formed by executing steps similar to those described in the first embodiment.

Then, as shown inFIG. 9, the resist pattern23is used as a mask to etch, by the RIE method, the stopper film16, control gate electrode film15, inter-electrode insulating film14, floating gate electrode film13, and tunnel insulating film12formed in the area corresponding to the dummy gate structures102aand102b(seeFIG. 4). At this time, the entire insulating portion22c(seeFIG. 4) is etched. As a result, holes (or trenches)24are formed to expose the surface of the silicon substrate11.

Then, as shown inFIG. 10, the resist pattern23is removed. A gate insulating film (third gate insulating film)31is newly formed on the exposed surface of the silicon substrate11. The gate insulating film31may be formed by the thermal oxidation method or deposition method. Subsequently, a phosphorous-doped polycrystal silicon film is deposited by the LPCVD method all over the surface of the resulting structure as the conductive film25. Moreover, the CMP method is used to polish and flatten the conductive film25. This results in a structure in which the holes24are filled with the conductive film25. As a result, gate electrodes18each composed of the conductive film25are formed on the gate insulating film31to obtain select gate structures103. The gate insulating film31is formed on the exposed surface of the silicon substrate11and thus also interposed between the electrode portion P3of the select gate structure103and the impurity diffusion layer21c.

As described above, according to the present embodiment, the memory cell gate structures101and the select gate structures103are formed using a technique basically similar to that according to the first embodiment. The present embodiment can thus exert effects similar to those of the first embodiment. In the present embodiment, the new gate insulating film31is formed after the holes24have been formed to expose the surface of the silicon substrate11. Thus, the gate insulating film31of the select gate structure103may be made different from the tunnel insulating film12aof the memory cell gate structure101in at least one of the film thickness and the material. Therefore, it is possible to optimize each of the gate insulating film31of the select gate structure103and the tunnel insulating film12aof the memory cell gate structure101. A semiconductor device can thus be provided which has excellent characteristics and a high reliability.

FIGS. 11 and 13are sectional views schematically showing a method for manufacturing a semiconductor device (NAND type flash memory) according to a third embodiment of the present invention. An equivalent circuit diagram and plan view for the third embodiment are similar toFIGS. 1 and 2, shown in the first embodiment. Further, the basic configuration and manufacturing method according to the third embodiment are similar to those according to the first embodiment. The description of the matters described in the first embodiment is thus omitted.

First, such a structure as shown inFIG. 3is formed by executing steps similar to those described in the first embodiment.

Then, as shown inFIG. 11, impurity diffusion layers21a,21b, and21cfor source and drain are formed using an ion implantation method as in the case of the first embodiment. Subsequently, side wall insulating films41are formed by the LPCVD method in order to form side wall films for LDD on gate electrodes of MIS transistors in a control circuit (peripheral circuit; not shown). The side wall insulating films41are then etched back. Since a reduction in the size of a semiconductor device reduce the spacing between memory cells, the area between the adjacent memory cell gate structures101is completely filled with the side wall insulating film41(insulating portion41a). Similarly, the area between the memory cell gate structure101and the dummy gate structure102ais completely filled with the side wall insulating film41(insulating portion41b). The area between the dummy gate structures102aand102bis completely filled with the side wall insulating film41(insulating portion41c). However, a wide void42is not completely filled with the side wall insulating film41; the void42is formed in the area between NAND cell units arranged adjacent to each other in the bit line direction (area in which a bit line contact is formed).

Then, as shown inFIG. 12, an inter-layer insulating film43is formed by the LPCVD method all over the surface of the resulting structure. Subsequently, the CMP method is used to polish and flatten the inter-layer insulating film43, by using a stopper film16as a CMP stopper. As a result, the void42is filled with the inter-layer insulating film43.

Then, as in the case of the first embodiment, the resist pattern23is used as a mask to etch, by the RIE method, the stopper film16, control gate electrode film15, and inter-electrode insulating film14formed in the area corresponding to the dummy gate structures102aand102b. At the same time, the insulating portion41cis also etched to have its height reduced. The floating gate electrode film13and the tunnel insulating film12are not etched but left as they are. Holes (or trenches)24are thus formed.

Then, as shown inFIG. 13, the resist pattern23is removed and then the holes24are filled with the conductive film25as in the case of the first embodiment. This forms gate electrodes18each composed of the floating gate electrode film13band conductive film25to obtain select gate structures103.

In this manner, according to the present embodiment, the memory cell gate structures101and the select gate structures103are formed using a technique similar to that according to the first embodiment. Therefore, the present embodiment can exert effects similar to those of the first embodiment.

In the present embodiment, when the holes24are formed in the step shown inFIG. 12, the tunnel insulating film12band the floating gate electrode film13bare left as they are as in the case of the first embodiment. However, the tunnel insulating film12band the floating gate electrode film13bmay be removed as in the case of the first embodiment. In this case, after the holes24have been formed, it is possible to apply a method and structure similar to those according to the second embodiment.