METHOD FOR FORMING PHOTOELECTRIC CONVERSION REGION OF IMAGE SENSING DEVICE

A method for forming a photoelectric conversion region of an image sensing device includes determining a thickness of a substrate and a capacitance of a photoelectric conversion region of an image sensing pixel corresponding to a desired performance of the image sensing pixel, determining a size of a desired photoelectric conversion region for the image sensing pixel based on the determined thickness of the substrate and the determined capacitance of the photoelectric conversion region, determining a first ion implantation energy suitable for implanting impurities into a predetermined depth in the substrate, determining a thickness of a mask pattern corresponding to the first ion implantation energy, and determining at least one second ion implantation energy suitable for implanting the impurities into the substrate for forming a plurality of sub-photoelectric conversion regions at different depths that collectively form the desired photoelectric conversion region.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims the priority and benefits of Korean patent application No. 10-2022-0087288, filed on Jul. 15, 2022, which is incorporated by reference in its entirety as part of the disclosure of this patent document.

TECHNICAL FIELD

The technology and implementations disclosed in this patent document generally relate to an image sensing device.

BACKGROUND

An image sensor is used in electronic devices to convert optical images into electrical signals. With the recent development of automotive, medical, computer and communication industries, the demand for highly integrated, higher-performance image sensors has been rapidly increasing in various electronic devices such as digital cameras, camcorders, personal communication systems (PCSs), video game consoles, surveillance cameras, medical micro-cameras, robots, etc.

The image sensing device may be roughly divided into CCD (Charge Coupled Device) image sensing devices and CMOS (Complementary Metal Oxide Semiconductor) image sensing devices. The CCD image sensing devices offer a better image quality, but they tend to consume more power and are larger as compared to the CMOS image sensing devices. The CMOS image sensing devices are smaller in size and consume less power than the CCD image sensing devices. Furthermore, CMOS sensors are fabricated using the CMOS fabrication technology, and thus photosensitive elements and other signal processing circuitry can be integrated into a single chip, enabling the production of miniaturized image sensing devices at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications including mobile devices.

SUMMARY

Various embodiments of the disclosed technology relate to a method for uniformly maintaining a critical dimension (CD) of a photoelectric conversion region while deeply forming the photoelectric conversion region.

In some embodiments of the disclosed technology, a method for forming a photoelectric conversion region of an image sensing device may include determining a thickness of a substrate and a capacitance of a photoelectric conversion region of an image sensing pixel corresponding to a desired performance of the image sensing pixel, determining a size of a desired photoelectric conversion region for the image sensing pixel based on the determined thickness of the substrate and the determined capacitance of the photoelectric conversion region, determining a first ion implantation energy suitable for implanting impurities into a predetermined depth in the substrate, determining a thickness of a mask pattern corresponding to the first ion implantation energy, and determining at least one second ion implantation energy suitable for implanting the impurities into the substrate for forming a plurality of sub-photoelectric conversion regions at different depths that collectively form the desired photoelectric conversion region.

In some embodiments of the disclosed technology, a method for forming a photoelectric conversion region of an image sensing device may include forming a first mask pattern defining a photoelectric conversion region over a first surface of a substrate, implanting impurities from the first surface of the substrate into a first region in the substrate using the first mask pattern as an implantation mask, forming a second mask pattern defining the photoelectric conversion region over a second surface opposite to the first surface of the substrate, and implanting impurities from the second surface of the substrate into a second region in the substrate using the second mask pattern as an implantation mask. Each of the first mask pattern and the second mask pattern may be formed to have a minimum thickness that prevents the corresponding impurities from penetrating a material layer of the first mask pattern and a material layer of the second mask pattern when the impurities are implanted into the substrate at a first ion implantation energy using the first mask pattern and the second mask pattern as implantation mask, respectively.

In some embodiments of the disclosed technology, a method for forming a photoelectric conversion region of an image sensing device may include calculating a thickness of a substrate and a capacitance of a photoelectric conversion region, each of which corresponds to a predetermined pixel performance, calculating a size of the photoelectric conversion region based on the calculated substrate thickness and the calculated capacitance of the photoelectric conversion region, calculating a first ion implantation energy required to implant impurities into a center portion of the photoelectric conversion region, calculating a thickness of a mask pattern corresponding to the first ion implantation energy, and dividing the photoelectric conversion region into a plurality of sub-photoelectric conversion regions, and calculating a second ion implantation energy required to implant the impurities into each sub-photoelectric conversion region.

In some embodiments of the disclosed technology, a method for forming a photoelectric conversion region of an image sensing device may include forming a first mask pattern defining a photoelectric conversion region over a first surface of a substrate, implanting impurities into a first region of the substrate through the first mask pattern, forming a second mask pattern defining the photoelectric conversion region over a second surface opposite the first surface in the substrate, and implanting impurities into a second region of the substrate through the second mask pattern. Each of the first mask pattern and the second mask pattern may be formed to have a minimum thickness that prevents the corresponding impurities from penetrating a material layer of the first mask pattern and a material layer of the second mask pattern when the impurities are implanted into a substrate with the first ion implantation energy using the mask pattern.

It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the disclosure as claimed.

DETAILED DESCRIPTION

This patent document provides implementations and examples of an image sensing device that may be used to substantially address one or more technical or engineering issues and mitigate limitations or disadvantages encountered in some other image sensing devices. Some implementations of the disclosed technology suggest examples of a method for uniformly maintaining a critical dimension (CD) of a photoelectric conversion region while deeply forming the photoelectric conversion region. The disclosed technology provides various implementations of a method for forming a photoelectric conversion region of the image sensing device which can minimize a thickness of a substrate and can improve dark characteristics of pixels by making a critical dimension (CD) of the photoelectric conversion region uniform.

Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts. In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

Hereafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents and/or alternatives of the embodiments. The embodiments of the disclosed technology may provide a variety of effects capable of being directly or indirectly recognized through the disclosed technology.

FIG.1is a block diagram illustrating an image sensing device based on some implementations of the disclosed technology.

Referring toFIG.1, the image sensing device may include a pixel array100, a row driver200, a correlated double sampler (CDS)300, an analog-digital converter (ADC)400, an output buffer500, a column driver600, and a timing controller700. The components of the image sensing device illustrated inFIG.1are discussed by way of example only, and this patent document encompasses numerous other changes, substitutions, variations, alterations, and modifications.

The pixel array100may include a plurality of unit pixels (PXs) arranged in rows and columns. The plurality of unit pixels (PXs) may convert incident light into an electrical signal (e.g., a pixel signal) corresponding to the incident light by performing photoelectric conversion of the incident light, and may thus output the electrical signal. Each unit pixel (PX) may include a photoelectric conversion region that generates photocharges through photoelectric conversion of the incident light. The photoelectric conversion region of each unit pixel (PX) may be formed to have the same critical dimension (CD) as a whole in a vertical direction. At this time, the critical dimension (CD) of the photoelectric conversion region may refer to a size (e.g., a length in a row direction and a length in a column direction) when viewed in a horizontal plane.

The pixel array100may receive driving signals (for example, a row selection signal, a reset signal, a transmission (or transfer) signal, etc.) from the row driver200. Upon receiving the driving signal, the unit pixels (PXs) may be activated to perform the operations corresponding to the row selection signal, the reset signal, and the transfer signal.

The row driver200may activate the pixel array100to perform certain operations on the unit pixels in the corresponding row based on control signals provided by controller circuitry such as the timing controller700. In some implementations, the row driver200may select one or more pixel groups arranged in one or more rows of the pixel array100. The row driver200may generate a row selection signal to select one or more rows from among the plurality of rows. The row driver200may sequentially enable the reset signal and the transfer signal for the unit pixels arranged in the selected row. The pixel signals generated by the unit pixels arranged in the selected row may be output to the correlated double sampler (CDS)300.

The correlated double sampler (CDS)300may remove undesired offset values of the unit pixels using correlated double sampling. In one example, the correlated double sampler (CDS)300may remove the undesired offset values of the unit pixels by comparing output voltages of pixel signals (of the unit pixels) obtained before and after photocharges generated by incident light are accumulated in the sensing node (i.e., a floating diffusion (FD) node). As a result, the CDS300may obtain a pixel signal generated only by the incident light without causing noise. In some implementations, upon receiving a clock signal from the timing controller700, the CDS300may sequentially sample and hold voltage levels of the reference signal and the pixel signal, which are provided to each of a plurality of column lines from the pixel array100. That is, the CDS300may sample and hold the voltage levels of the reference signal and the pixel signal which correspond to each of the columns of the pixel array100. In some implementations, the CDS300may transfer the reference signal and the pixel signal of each of the columns as a correlate double sampling (CDS) signal to the ADC400based on control signals from the timing controller700.

The ADC400is used to convert analog CDS signals received from the CDS300into digital signals. In some implementations, the ADC400may be implemented as a ramp-compare type ADC. The analog-to-digital converter (ADC)400may compare a ramp signal received from the timing controller700with the CDS signal received from the CDS300, and may thus output a comparison signal indicating the result of comparison between the ramp signal and the CDS signal. The analog-to-digital converter (ADC)400may count a level transition time of the comparison signal in response to the ramp signal received from the timing generator700, and may output a count value indicating the counted level transition time to the output buffer500.

The output buffer500may temporarily store column-based image data provided from the ADC400based on control signals of the timing controller700. The image data received from the ADC400may be temporarily stored in the output buffer500based on control signals of the timing controller700. The output buffer500may provide an interface to compensate for data rate differences or transmission rate differences between the image sensing device and other devices.

The column driver600may select a column of the output buffer500upon receiving a control signal from the timing controller700, and sequentially output the image data, which are temporarily stored in the selected column of the output buffer500. In some implementations, upon receiving an address signal from the timing controller700, the column driver600may generate a column selection signal based on the address signal, may select a column of the output buffer500using the column selection signal, and may control the image data received from the selected column of the output buffer500to be output as an output signal.

The timing controller700may generate signals for controlling operations of the row driver200, the ADC400, the output buffer500and the column driver600. The timing controller700may provide the row driver200, the column driver600, the ADC400, and the output buffer500with a clock signal required for the operations of the respective components of the image sensing device, a control signal for timing control, and address signals for selecting a row or column. In some implementations, the timing controller700may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, a communication interface circuit and others.

The image sensing device may include a three-dimensional (3D) stack structure in which a first semiconductor layer in which the pixel array100is formed and a second semiconductor layer in which the CDS300, the ADC400, the output butter500, the column driver600, and the timing controller700are formed are stacked. Alternatively, the row driver200, the CDS300, the ADC400, the output buffer500, the column driver600, and the timing controller700may be disposed outside the pixel array100within the same semiconductor layer as that of the pixel array100.

FIG.2is a cross-sectional view illustrating an example of the pixel array taken along the line A-A′ shown inFIG.1based on some implementations of the disclosed technology.

Referring toFIG.2, the pixel array100of the image sensing device may include a substrate layer110, a buffer layer120, a grid structure130, a color filter layer140, and a lens layer150.

The substrate layer110may include a substrate112, a device isolation structure114, and a photoelectric conversion region116.

The substrate112may include a semiconductor substrate having a first surface and a second surface opposite to the first surface. The first surface of the substrate112may be a light reception surface upon which light is incident, and may be formed to have the buffer layer120, the grid structure130, the color filter layer140, and the lens layer150. The second surface of the substrate112may be formed to have pixel transistors that can be used to generate digital data corresponding to photocharges generated by the photoelectric conversion region116. The semiconductor substrate112may include a silicon bulk wafer or an epitaxial wafer. In some implementations, the epitaxial wafer may include a crystalline material layer (e.g., a silicon epitaxial layer) that is formed by an epitaxial growth process on a bulk substrate. In other implementations, the semiconductor substrate112may be formed using a variety of wafers different from the bulk wafer or the epitaxial wafer, such as a polished wafer, an annealed wafer, a silicon-on-insulator (SOI) wafer, and others.

The substrate112may include P-type impurities, and photoelectric conversion regions116corresponding to each unit pixel (PX) may be formed in the substrate112. The photoelectric conversion regions116may generate photocharges by converting light incident upon the first surface of the substrate112into electrical signals (photoelectric conversion). The photoelectric conversion regions116may be electrically and/or optically isolated by the device isolation structure114, thereby forming unit pixels PXs. Each of the photoelectric conversion regions116may include an organic or inorganic photodiode. A P-type impurity region may be formed between the device isolation structure114and the photoelectric conversion regions116.

The photoelectric conversion region116may include a plurality of sub-photoelectric conversion regions116_1to116_5located at different depths to be vertically stacked in the substrate112. As illustrated in the example inFIG.2, the sub-photoelectric conversion regions116_1to116_5may be formed to have the same critical dimension (CD) when viewed in a plan view. For example, the sub-photoelectric conversion regions116_1to116_5may be formed to have the same width in the row and column directions. In addition, the sub-photoelectric conversion regions116_1to116_5may be stacked on top of one another and may be successively arranged in a vertical direction substantially perpendicular to the substrate layer110to form one photoelectric conversion region116. In some implementations, the sub-photoelectric conversion regions116_1to116_5may be stacked such that the central axes thereof can vertically overlap each other. For example, the photoelectric conversion region116may be formed to extend in a vertical direction with a uniform CD.

AlthoughFIG.2illustrates five sub-photoelectric conversion regions116_1to116_5successively connected to form one photoelectric conversion region116by way of example, it should be noted that the number of sub-photoelectric conversion regions may vary. In addition, althoughFIG.2shows the sub-photoelectric conversion regions116_1to116_5as having the same height, the heights of the sub-photoelectric conversion regions116_1to116_5may be different in certain implementations.

In some implementations, the photoelectric conversion region116may have an overall uniform CD as will be discussed below.

The sub-photoelectric conversion regions116_1to116_5may be formed in the semiconductor substrate112through an ion implantation process. For example, when the semiconductor substrate142is based on the P-type epitaxial wafer, N-type impurities may be implanted into the sub-photoelectric conversion regions116_1to116_5.

The device isolation structure114may be disposed between adjacent photoelectric conversion regions116to electrically isolate the photoelectric conversion regions116from each other. The device isolation structure114may include an insulation material that is buried in a trench. For example, the device isolation structure114may include a deep trench isolation (DTI) structure. Alternatively, the device isolation structure114may include high-density insulation impurities that are implanted into the semiconductor substrate112.

The buffer layer120may be used as a planarization layer to remove surface topologies on the second surface of the substrate112. In addition, the buffer layer120may operate as an anti-reflection layer to allow incident light received through the lens layer150and the color filters140to pass through the photoelectric conversion region116. The buffer layer120may include a multilayer structure formed by stacking different material layers having different refractive indices. For example, the buffer layer120may include a multilayer structure formed by stacking at least one nitride film122and at least one oxide film124.

The nitride film122may include a silicon nitride film (SixNy, where x and y are natural numbers) or a silicon oxide nitride film (SixOyNz, where x, y, and z are natural numbers). The oxide film124may include a monolayer structure formed of any one of an Undoped Silicate Glass (USG) film and an Ultra-Low Temperature Oxide (ULTO) film, or may include a multilayer structure formed by stacking the USG film and the ULTO film. The oxide film124may include the same material as the capping layer136of the grid structure143, and the oxide film124and the capping layer136may be simultaneously formed through the same deposition process.

In addition, a fixed charge layer (not shown) may be formed below the nitride film122to prevent hole (electron hole) accumulation from occurring in the substrate112. The fixed charge layer may include a metal oxide material such as aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), and others.

Each grid structure130may be disposed between the adjacent color filters140, and may prevent optical crosstalk from occurring between the color filters140. The grid structure130may include a metal layer132, an air layer134, and a capping layer136. The capping layer136may be a material film formed at an outermost part of the grid structure130, and may cover the air layer134. The capping layer136may be formed to extend to a lower portion of the color filter layer140. In this case, the capping layer formed below the color filter layer140may be used as the oxide film124of the buffer layer120.

The color filter layer140may include color filters that are located on the buffer layer120. In some implementations, each unit pixel (PX) includes a color filter formed on the buffer layer120. The color filters may be located in a region defined by the grid structure130. The color filter layer140may include a plurality of red color filters (Rs), a plurality of green color filters (Gs), and a plurality of blue color filters (Bs). Each red color filter (R) may transmit only red light and absorb other colors. Each green color filter (G) may transmit only green light and absorb other colors. Each blue color filter (B) may transmit only blue light and absorb other colors.

The lens layer150may be disposed over the color filter layer140. The lens layer150may direct (or guide) incident light to the photoelectric conversion region116of each unit pixel (PX). The lens layer150may converge the incident light and transmit the converged light to the color filter layer140. The lens layer150may include an over-coating layer, a microlens layer, and an anti-reflection layer. The over-coating layer may be disposed below the microlens layer to prevent irregular or diffused reflection of incident light that would have caused flare and to surface topologies of the color filters. The microlens layer may be disposed over the over-coating layer, and may be formed in a hemispherical shape to converge incident light. The anti-reflection layer may be disposed over the microlens layer, and may prevent incident light from being reflected by the microlens layer while protecting the microlens layer.

FIG.3is a flowchart illustrating a method for calculating information required to form the photoelectric conversion region in the cross-sectional structure ofFIG.2based on some implementations of the disclosed technology.

Referring toFIG.3, a design system (not shown) may design components of pixels that can meet the requirements for pixel performance of an image sensor to be manufactured (S310).

For example, the design system may calculate, for example, a substrate thickness, a full well capacity (FWC) and a formation position of a photoelectric conversion region, a transfer capacity of the transfer transistor, which are required to manufacture the image sensor having a desired performance. In this case, the substrate thickness may refer to the thickness of a substrate in which the photoelectric conversion region is to be formed. Pixel performance required for the image sensor may be preset and configured in the design system by a system designer.

The design system may calculate the size (e.g., a critical dimension (CD) and a height) of a photoelectric conversion region to be formed, a maximum ion implantation energy, and a thickness of a mask pattern corresponding to the maximum ion implantation energy, based on the capacity of the photoelectric conversion region and the substrate thickness which have been determined/calculated at S310(S320).

For example, in order for the photoelectric conversion region to have an overall uniform CD in a vertical direction and to have the capacity determined/calculated at S310, the design system may calculate the CD of the photoelectric conversion region to be formed, and the position and height of the photoelectric conversion region to be formed. In this case, the CD of the photoelectric conversion region may include a width in the row direction and a width in the column direction when viewed in a plan view.

In addition, the design system may calculate the maximum energy (maximum ion implantation energy) for implanting impurities into the photoelectric conversion region and the thickness of the mask pattern corresponding to the maximum ion implantation energy, based on the substrate thickness and the formation position and height of the photoelectric conversion region. For example, the design system may calculate a maximum value (i.e., the maximum ion implantation energy) of the ion implantation energy required when the impurities are implanted at a position in the substrate corresponding to ½ of the substrate thickness determined at S310.

When the maximum ion implantation energy is determined, the design system may calculate the thickness (i.e., a minimum thickness) of the mask pattern to prevent the impurities from penetrating a material layer of the mask pattern even if the impurities are implanted with the maximum ion implantation energy.

For example, when a photoresist pattern is used as a mask pattern for impurity implantation, some impurities may be introduced into the substrate after passing through the photoresist layer during the impurity implantation process. As such, the impurities introduced into the substrate after passing through the photoresist layer are mainly concentrated near the surface of the substrate, and such impurities may affect the operation characteristics of the pixel. For example, the impurities introduced onto the surface of the substrate after passing through the photoresist layer may degrade the dark characteristics of the pixel. Therefore, during the impurity implantation process, the photoelectric conversion region is formed by implanting the corresponding impurities into the substrate only through the open region of the photoresist pattern without penetrating the photoresist layer.

In order to prevent impurities from penetrating the photoresist layer, the ion implantation energy is set low or the thickness of the photoresist pattern is increased to a sufficiently large thickness so that the penetration through the photoresist layer by the implanted impurities is minimized below a desired level or substantially eliminated. However, it is difficult to form the photoelectric conversion region deep in the substrate by using such a low ion implantation energy. In addition, when the thickness of the photoresist pattern is increased, it is difficult to pattern the photoresist layer in a desired shape or pattern and accurately control the CD of the photoelectric conversion region, causing deviation between pixels.

In some embodiments of the disclosed technology, in order to form a thin photoresist pattern and form the photoelectric conversion region having a uniform CD at a deep depth in the substrate, the maximum ion implantation energy may be determined based on the position or depth in the substrate corresponding to ½ of the substrate thickness, and the thickness of the photoresist pattern corresponding to the maximum ion implantation energy may be determined.

In addition, the design system may divide the photoelectric conversion region into a plurality of sub-regions (e.g., a plurality of sub-photoelectric conversion regions), and may calculate the ion implantation energy for each sub-photoelectric conversion region (S330).

Impurity implantation with the same ion implantation energy over the entire photoelectric conversion region may render the CD of the photoelectric conversion region non-uniform, and thus the design system based on the disclosed technology uses different levels of implanting energy for forming different adjacent sub regions at different depths from the substrate surface so that those different adjacent sub regions at different depths collectively form the desired contiguous photoelectric conversion region. Therefore, instead of designing the photomask and the implanting energy for implanting impurities to form the desired final the photoelectric conversion region in a substrate in one single implantation process at the same implantation energy level, the disclosed technology divides the desired photoelectric conversion region into a plurality of different and adjacent sub-photoelectric conversion regions at different depths from the substrate surface in the vertical direction perpendicular to the substrate and forming those sub-photoelectric conversion regions at different depths using different implanting steps at different implanting energy levels by using a thinner mask pattern that the mask matter needed for the one single implantation process. This multi-step implanting process involves determination of different desired ion implantation energy levels for the different sub-photoelectric conversion regions at different depths. For example, the design system may divide the photoelectric conversion region into an upper region and a lower region based on a specific position or depth in the substrate corresponding to ½ of the substrate thickness, and may divide each of the upper region and the lower region into at least one sub-photoelectric conversion region. The implanting process can be performed in different processes at different energy levels less than the maximum energy level and can further reduce the implantation energy and the thickness of the mask pattern by performing the implanting of impurities from two opposite surfaces of the substrate. In some implementations, the ion implantation energy for each sub-photoelectric conversion region and the height of each sub-photoelectric conversion region may have specific values such that the sub-photoelectric conversion regions have the same CD value.

As shown inFIG.2by way of example, the photoelectric conversion region116is divided into five sub-photoelectric conversion regions116_1to116_5, and, in some implementations, the sub-photoelectric conversion regions116_1to116_5may have the same height.

FIGS.4to7are cross-sectional views illustrating example method for forming the photoelectric conversion region using information determined by the method ofFIG.3based on some implementations of the disclosed technology. In this example,FIGS.4and5show implanting via the first top surface of the substrate112for forming sub-photoelectric conversion regions closer to the first top surface andFIGS.6and7show implanting via the second bottom surface of the substrate112for forming sub-photoelectric conversion regions closer to the second bottom surface.

Referring toFIG.4, a mask pattern182for defining a specific region (hereinafter referred to as a predetermined photoelectric conversion region)116′ that will be formed as a photoelectric conversion region in a subsequent fabrication process may be formed over the first surface of the substrate112having a thickness calculated at S310. In some implementations, the size (i.e., the row-directional width and the column-directional width) of the open region of the mask pattern182may be set to the CD of the photoelectric conversion region determined at S320inFIG.3.

The substrate112may include a bulk silicon wafer including P-type impurities, or an epitaxial wafer. The substrate112may include a first surface and a second surface opposite the first surface. The mask pattern182may include a photoresist pattern. As an example, the thickness of the photoresist pattern182may be equal to the thickness of the mask pattern determined at S320inFIG.3. That is, the photoresist pattern182may be formed to have a thickness such that impurities are not introduced into the substrate112through the photoresist layer of the photoresist pattern182even when the impurities are implanted with the maximum ion implantation energy determined at S320inFIG.3.

The predetermined photoelectric conversion region116′ may include an upper region (116′_UP) located close to the first surface of the substrate112and a lower region (116′_DN) located close to the second surface of the substrate112with respect to the center line (or half-substrate depth) in the substrate184corresponding to ½ of the substrate thickness.

Referring toFIG.5, N-type impurities are implanted through the first (top) surface of the substrate112, so that the sub-photoelectric conversion regions116_1and116_2may be sequentially formed in the upper region (116′_UP) of the predetermined photoelectric conversion region116′. For example, the first sub-photoelectric conversion region116_1close to the center line184may be formed first in the upper region (116′_UP) of the photoelectric conversion region116′. Subsequently, a second sub-photoelectric conversion region116_2immediately above and in contact with the first sub-photoelectric conversion region116_1may be formed next by using the same mask pattern182. Since the second sub-photoelectric conversion region116_2is immediately above the first sub-photoelectric conversion region116_1and thus is closer to the first (top) surface of the substrate112than the first sub-photoelectric conversion region116_1, the additional implanting of N-type impurities into the upper region (116′_UP) for forming the shallower second sub-photoelectric conversion region116_2can be achieved by using an implantation energy level smaller than the implantation energy level that is used to form the first sub-photoelectric conversion region116_1. The second sub-photoelectric conversion region116_2may have the same CD as the first sub-photoelectric conversion region116_1.

Therefore, the energy for implanting impurities into the first sub-photoelectric conversion region116_1may be equal to or smaller than the maximum ion implantation energy. Therefore, when impurities (N-type impurities) are implanted into the first sub-photoelectric conversion region116_1, few or no impurities can penetrate the material layer of the mask pattern182, and thus few or no impurities are present around the first surface of the substrate112. Further, since the second sub-photoelectric conversion region116_2is located closer to the first surface of the substrate112than the first sub-photoelectric conversion region116_1, impurities may be implanted for forming the second sub-photoelectric conversion region116_2with an ion implanting energy level smaller than the energy that is used to implant impurities into the first sub-photoelectric conversion region116_1. Therefore, even when impurities are implanted into the second sub-photoelectric conversion region116_2, the impurities targeted at the second sub-photoelectric conversion region116_2generally are not sufficiently energic to penetrate the material layer of the mask pattern182.

Referring toFIG.6, after finishing formation of the first sub-photoelectric conversion region116_1and second sub-photoelectric conversion region116_2in the upper region (116′_UP) by using the mask pattern182, the mask pattern182formed over the first surface of the substrate112may be removed, and a mask pattern186defining a photoelectric conversion region116′ may be formed over a second surface of the substrate112for forming sub-photoelectric conversion regions by impurity implanting from the second (bottom) surface of the substrate112.

Similarly to the formation of the first sub-photoelectric conversion region116_1and second sub-photoelectric conversion region116_2in the upper region (116′_UP), the size (e.g., width in the row direction and the width in the column direction) of the open region of the mask pattern186may be the CD of the photoelectric conversion region determined at S320inFIG.3. The mask pattern186may include a photoresist pattern, and the thickness of the photoresist pattern186may be a thickness of the mask pattern determined at S320ofFIG.3. For example, the mask pattern186may be formed to have the same thickness as the mask pattern182.

Referring toFIG.7, N-type impurities are implanted through the second (bottom) surface of the substrate112so that the sub-photoelectric conversion regions116_3to116_5are sequentially formed in the lower region116′_DN of the photoelectric conversion region116′ to jointly form the photoelectric conversion region116with the first sub-photoelectric conversion region116_1and second sub-photoelectric conversion region116_2in the upper region (116′_UP). For example, the third sub-photoelectric conversion region116_3close to the center line184may be formed first in the lower region116′_DN of the photoelectric conversion region116′. Subsequently, a fourth sub-photoelectric conversion region116_4connected to the third sub-photoelectric conversion region116_3may be formed by using the same mask pattern186and additionally implanting N-type impurities into the lower region116′_DN with energy smaller than the energy that is used to form the third sub-photoelectric conversion region116_3. Thereafter, a fifth sub-photoelectric conversion region116_5connected to the fourth sub-photoelectric conversion region116_4may be formed by using the same mask pattern186, and additionally implanting N-type impurities into the lower region116′_DN with energy smaller than the energy that is used to form the fourth sub-photoelectric conversion region116_4. Since the first to fifth sub-photoelectric conversion regions116_1to116_5have the same CD, the photoelectric conversion region116formed by stacking the first to fifth sub-photoelectric conversion regions116_1to116_5may have an overall uniform CD.

In this case, the energy for implanting impurities into the third sub-photoelectric conversion region116_3may be equal to or smaller than the maximum ion implantation energy. Therefore, when impurities are implanted into the third sub-photoelectric conversion region116_3, few or no impurities can penetrate the material layer of the mask pattern186, and thus be few or no impurities are present around the second surface of the substrate112. Further, since the fourth and fifth sub-photoelectric conversion regions116_4and116_5are located closer to the second surface of the substrate112than the third sub-photoelectric conversion region116_3, impurities may be implanted with energy smaller than the energy that is used to implant impurities into the third sub-photoelectric conversion region116_3. Therefore, even when impurities are implanted into the fourth and fifth sub-photoelectric conversion regions116_4and116_5, the impurities do not penetrate the material layer of the mask pattern186.

As is apparent from the above description, in forming a photoelectric conversion region of the image sensing device, the disclosed technology can be implemented in some embodiments to minimize a thickness of a substrate and the uniform critical dimension (CD) of the photoelectric conversion region can reduce or minimize dark current in pixels.

Some embodiments of the disclosed technology may provide a variety of effects capable of being directly or indirectly recognized through the above-mentioned patent document.

Although a number of illustrative embodiments have been described, it should be understood that various modifications or enhancements of the disclosed embodiments and other embodiments can be devised based on what is described and/or illustrated in this patent document.