FUSI gated device formation

Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.

BACKGROUND

Many modern-day electronic devices contain metal-oxide-semiconductor field-effect transistors (MOSFETs). A MOSFET has a gate structure arranged over a substrate between a source region and a drain region. A voltage applied to a gate electrode of the gate structure determines the conductivity of the MOSFET. Gate structures with a fully silicided (FUSI) gate electrode are a promising candidate for next generation MOSFET devices due to advantages with scaling high κ MOSFET devices.

DETAILED DESCRIPTION

A typical metal-oxide-semiconductor field-effect transistor (MOSFET) includes a gate structure over a well region within a substrate. Source and drain regions are located in the substrate on opposing sides of a channel region underlying the gate structure. The gate structure comprises a gate electrode disposed over a gate dielectric layer. Applying a voltage from the gate electrode to the source and drain regions varies a resistance of the MOSET. Increasing the voltage increases the concentration of charge carriers (e.g., electrons) in the channel region, thereby reducing resistance between the source and drain regions.

Over the last two decades, MOFSET transistors have typically used gate structures comprising polysilicon. In recent years, high κ metal gate (HKMG) transistors have begun to see widespread use due to their ability to further enable scaling and improve performance of a MOSFET device. However, it is challenging to embed low voltage and high voltage devices together using HKMG replacement gate processes. One alternative to HKMG is to use fully silicided (FUSI) gates. During fabrication of a MOSFET having a FUSI gate, a polysilicon layer is formed over the gate dielectric layer, and a metal layer is formed over the polysilicon layer. An annealing process is performed to convert the polysilicon layer and metal layer into a fully silicided (FUSI) gate electrode of the gate structure. Subsequently, the source and drain regions are formed on opposing sides of the gate structure. Conductive contacts are disposed over the FUSI gate electrode, and the source and drain regions. Overlying metal wires are subsequently formed within an inter-level-dielectric (ILD) layer over the conductive contacts.

Ideally, a relatively thin layer of polysilicon is used during FUSI processes. This is because a thick polysilicon layer will lead to processing issues during the annealing process. For example, if the polysilicon layer is too thick (e.g. greater than approximately 600 Angstroms), and not uniform in thickness, then the annealing process will not be able to convert the entire polysilicon layer into the FUSI gate electrode, leaving portions (e.g. within a center region of the FUSI gate electrode) of the FUSI gate electrode as polysilicon and degrading performance of the MOSFET device. However, it has been appreciated that after forming a thin polysilicon layer over the gate dielectric layer there will be grain boundaries that result in hump defects having an elevated height. The hump defects cause non-uniformities in height of the polysilicon layer over an array of MOSFET devices on the substrate, which will also lead to processing issues during the annealing process.

The present disclosure, in some embodiments, relates to a method of forming a MOSFET device that includes forming a gate structure comprising a first dielectric layer (e.g. the first dielectric layer comprising a high κ dielectric) over the gate dielectric layer, forming a metal layer over the first dielectric layer (e.g. the metal layer comprising TiN), and forming a polysilicon layer over the metal layer. The polysilicon layer forms on the metal layer uniformly and defect free, hereby removing any potential hump defect issues. Source and drain regions are formed on opposing sides of the gate structure. A second dielectric layer is formed over the gate structure and the source and drain regions. A planarization and etch process are performed to expose an upper surface of the polysilicon layer. A conductive layer is formed over the upper surface of the polysilicon layer and an annealing process is performed to convert the polysilicon layer and conductive layer into a FUSI layer. Formation of the polysilicon layer on the metal layer allows the polysilicon layer to be thin (e.g. having a thickness of approximately less than 300 Angstroms) and substantially uniform in thickness, ensuring the annealing process silicides an entire thickness of the polysilicon layer directly below the conductive layer.

Referring toFIG. 1, a cross-sectional view of an integrated circuit (IC)100in accordance with some embodiments is provided.

The IC100includes a substrate101with a first MOSFET device122and a second MOSFET device124disposed over and within the substrate101. An etch stop layer110is disposed over the substrate101and around sidewalls of the first and second MOSFET devices122,124. A first inter-level dielectric (ILD) layer128is disposed over the first and second MOSFET devices122,124and the etch stop layer110.

The first and second MOSFET devices122,124respectively comprise a gate structure121. The gate structure121includes a gate dielectric layer112, a first dielectric layer114, a metal layer116, and a fully silicided (FUSI) layer118. The gate dielectric layer112is in direct contact with the substrate101. The first dielectric layer114overlies the gate dielectric layer112. The metal layer116overlies the first dielectric layer114. The FUSI layer118overlies the metal layer116. In some embodiments, the FUSI layer118is relatively thin and uniform in thickness, for example, a thickness at each point between a top surface of the FUSI layer118and a respective bottom surface of the FUSI layer118varies within a range of approximately −15 Angstroms to +15 Angstroms. In some embodiments, the FUSI layer118is formed to a thickness within a range of approximately 150 Angstroms to approximately 300 Angstroms. In other embodiments, the FUSI layer118is formed to a thickness within a range of approximately 225 Angstroms to approximately 300 Angstroms. In some embodiments, the FUSI layer118is entirely silicided so that no unsilicided polysilicon material exists between the top and bottom surfaces of the FUSI layer118. In some embodiments, the metal layer116comprises titanium nitride (TiN). A sidewall spacer120surrounds sidewalls of respective individual layers in the gate structure121. First conductive contacts126respectively overlie the FUSI layer118of the first and second MOSFET devices122,124.

A first source/drain region102and a second source/drain region104are disposed on opposing sides of the gate structure121of the first MOSTEFT device122. A third source/drain region106and a fourth source/drain region108are disposed on opposing sides of the gate structure121of the second MOSFET device124. The first, second, third, and fourth source/drain regions102,104,106,108are disposed within the substrate101. The first and second source/drain regions102,104have a first doping type. The third and fourth source/drain regions106,108have a second doping type. In some embodiments, the first and second doping types are the same. In yet another embodiment, the first doping type is P+-type and the second doping type is N+-type, or vice versa.

In some embodiments, the first and second MOSFET devices122,124may comprise high voltage devices. High voltage technology has been widely used in power management, regulator, battery protector, DC motor, automotive relative, panel display driver (STN, TFT, OLED, etc), color display driver, power supply relative, Telecom, and the like. In some embodiments, the disclosed MOFSET devices may comprise symmetrical and asymmetrical laterally diffused MOSFET (LDMOS), double-diffused MOSFET (DMOS) devices, or the like. The thin and uniform FUSI layer118overlying the metal layer116ensures low voltage and high voltage devices can be embedded together.

Having the FUSI layer118overlie the metal layer116allows the FUSI layer118to have a relatively thin and uniform thickness (e.g. a thickness less than or equal to approximately 300 Angstroms or within a range of approximately 150 Angstroms to 300 Angstroms). This relatively thin and uniform thickness ensures an entire thickness of the FUSI layer118is completely silicided and mitigates processing issues related to the thickness of the FUSI layer118. Having the metal layer116ensures that MOSFET devices of opposite doping types can be embedded on the same platform with minimal defects (e.g. preventing hump defects) within the FUSI layer118(e.g. specifically in high voltage applications, with a voltage in a range of approximately 6 V to 32 V).

FIG. 2illustrates a cross-sectional view of some additional embodiments of an IC200.

The IC200includes a substrate101with a first MOSFET device122disposed over and within the substrate101. The substrate101may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P doped silicon, or N doped silicon. A second dielectric layer212overlies the first MOSFET device122. A first ILD layer128is disposed over the second dielectric layer212.

The first MOSFET device122comprises a gate structure121. The gate structure121includes a gate dielectric layer112, a first dielectric layer114, a metal layer116and a fully silicided (FUSI) layer118. The gate dielectric layer112is in direct contact with the substrate101. In some embodiments, the gate dielectric layer112may, for example, be or comprise an oxide (e.g. silicon oxide, silicon oxy-nitride, or the like), a high κ dielectric (e.g. hafnium oxide, zirconium silicate, or the like), or any combination of the foregoing formed to a thickness of approximately 208 Angstroms or within a range of approximately 50 Angstroms to approximately 250 Angstroms. The first dielectric layer114overlies the gate dielectric layer112. In some embodiments, the first dielectric layer114may, for example, be or comprise a high κ dielectric, hafnium oxide (HfO2), zirconium oxide (ZrO2), or any combination of the foregoing formed to a thickness of approximately 10 Angstroms, 20 Angstroms, or within a range of approximately 5 Angstroms to approximately 25 Angstroms. As used herein, a high κ dielectric may be, for example, a dielectric with a dielectric constant κ greater than about 3.9, 10, or 20. The metal layer116overlies the first dielectric layer114. In some embodiments, the metal layer116may, for example, be or comprise titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or any combination of the foregoing formed to a thickness of approximately 10 Angstroms, 30 Angstroms, or within a range of approximately 5 Angstroms to approximately 40 Angstroms. The FUSI layer118overlies the metal layer116. In some embodiments, the FUSI layer118may, for example, be or comprise nickel silicide, cobalt silicide, titanium silicide, copper silicide, or the like formed to a thickness of approximately 150 Angstroms, 169 Angstroms, 200 Angstroms, 250 Angstroms, or within a range of approximately 125 Angstroms to approximately 325 Angstroms.

The gate structure121is defined within a center region214a. In some embodiments, the center region214ais centered at a midpoint of the gate structure121(e.g., a midpoint of the FUSI layer118). A first outer region214band a second outer region214care defined on opposite sides of the center region214a. The FUSI layer118is defined within the center region214a. An entire thickness of the FUSI layer118is silicided, so that no unsilicided polysilicon material exists between a top and bottom surface of the FUSI layer118. The first and second outer regions214b,214crespectively comprise a polysilicon layer204overlying the metal layer116. In some embodiments, the polysilicon layer204may, for example, be or comprise polysilicon formed to a thickness of approximately 150 Angstroms, 300 Angstroms, or within a range of approximately 125 Angstroms to approximately 500 Angstroms. In some embodiments, a bottom layer of the polysilicon layer204is aligned with a bottom layer of the FUSI layer118and a thickness of the polysilicon layer204is greater than a thickness of the FUSI layer118. In some embodiments, the thickness of the polysilicon layer204is approximately 10 percent, 25 percent, 50 percent or 75 percent thicker than the thickness of the FUSI layer118. In some embodiments, a portion of the polysilicon layer204is partially or fully silicided with a conductive material from the FUSI layer118.

A masking layer210overlies the polysilicon layer204. In some embodiments (not shown), the masking layer210may extend from directly over the polysilicon layer204to directly over the FUSI layer118. In some such embodiments, the FUSI layer118may have angled outer sides (i.e. defining an angled interface between the FUSI layer118and the polysilicon layer204) that cause a width of the FUSI layer118to increase as a distance from the substrate101increases. In some embodiments, the masking layer210may, for example, be or comprise silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), or any combination of the foregoing formed to a thickness of approximately 150 Angstroms, 250 Angstroms, or within a range of approximately 100 Angstroms to approximately 350 Angstroms. The second dielectric layer212overlies the masking layer210.

The first and second outer regions214b,214crespectively comprise a first contact region209aand a second contact region209b. The first and second contact regions209a,209brespectively comprise a third dielectric layer206surrounded by a U-shaped etch stop layer208. In some embodiments, the center region214aand the gate structure121are defined between inner sidewalls of the first and second contact regions209a,209b. A first source/drain region102and a second source/drain region104are respectively disposed within the substrate101directly below the first and second contact regions209a,209b. A first silicide region102aand a second silicide region104aare respectively disposed above the first and second source/drain regions102,104. In some embodiments, the first and second source/drain regions102,104have a first doping type opposite the doping type of the substrate101. An isolation structure202extends into an upper or top surface of the substrate101to provide electrical isolation between the MOSFET device122and neighboring devices. The isolation structure202includes a pair of isolation segments respectively on opposite sides of the MOSFET device122. In some embodiments, the isolation structure202comprises a dielectric material, and/or is a shallow trench isolation (STI) structure, a deep trench isolation structure (DTI), or some other suitable isolation structure.

Referring toFIG. 3, a cross-sectional view of some embodiments of an IC300comprising a first MOSFET device122and a second MOSFET device124.

The IC300includes a substrate101with first and second MOSFET devices122,124disposed over and within the substrate101. In some embodiments, the substrate101is doped with an N dopant or with a P dopant. A first well region304and a second well region308respectively overlie a first deep well region302and second deep well region306within the substrate101. First source/drain extension regions303are disposed along an inner sidewall of the first and second source/drain regions102,104respectively. The first source/drain extension regions303comprise the same dopant as the first and second source/drain regions102,104at a lower concentration. Second source/drain extension regions305are disposed along an inner sidewall of the third and fourth source/drain regions106,108respectively. The second source/drain extension regions305comprise the same dopant as the third and fourth source/drain regions106,108at a lower concentration.

In some embodiments, the first and second source/drain regions102,104respectively comprise a first dopant type (e.g., P-type or N-type). The first well region304and first deep well region302respectively comprise a second dopant. The first dopant is opposite the second dopant. In some embodiments, the third and fourth source/drain regions106,108respectively comprise a third dopant. The second well region308and second deep well region306respectively comprise a fourth dopant. The third dopant is opposite the fourth dopant. In some embodiments, the first and third dopants are the same or opposite, or the first and fourth dopants are the same or opposite. Thus, in some embodiments, the first MOSFET device122is N-type and the second MOSFET device124is P-type, or vice versa. In some embodiments, the first and second MOSFET devices122,124are both either N-type or P-type.

The first and second MOSFET devices122,124respectively comprise a gate structure121. The gate structure121comprises a gate dielectric layer112, a first dielectric layer114, a metal layer116, a FUSI layer118, and a second sidewall spacer310. The gate dielectric layer112is in direct contact with the substrate101. The first dielectric layer114is disposed over the gate dielectric layer112. The metal layer116is disposed over the first dielectric layer114. The FUSI layer118is disposed over the metal layer116. The second sidewall spacer310comprises two segments disposed over the metal layer116on opposite sides of the FUSI layer118. The two segments of the second sidewall spacer310sandwich the FUSI layer118. In some embodiments, the second sidewall spacer310may, for example, be or comprise SiN, SiC, SiO), or any combination of the foregoing. A first ILD layer128is disposed over the first and second MOSFET devices122,124and the substrate101.

First conductive contacts126respectively overlie the FUSI layer118and the source/drain regions (first, second, third, and fourth source/drain regions102,104,106, and108) of the first and second MOSFET devices122,124. The first conductive contacts126may, for example, be or comprise tungsten (W), copper (Cu), aluminum (Al), a combination of the aforementioned, or the like. First conductive wires314respectively overlie the first conductive contacts126and are disposed within a second ILD layer312. The first conductive wires314may, for example, be or comprise Cu, Al, a combination of the aforementioned, or the like. Second conductive vias318respectively overlie the first conductive wires314and are disposed within a third ILD layer316. The second conductive vias318may, for example, be or comprise Cu, Al, a combination of the aforementioned, or the like. Second conductive wires322respectively overlie the second conductive vias318and are disposed within a fourth ILD layer320. The second conductive wires322may, for example, be or comprise Cu, Al, a combination of the aforementioned, or the like.

Referring toFIG. 4, a cross-sectional view of some embodiments of an IC400comprising a first MOSFET device122and a second MOSFET device124. The first and second MOSFET devices122and124are each as the MOSFET device122ofFIG. 2is illustrated and described, whereby the first and second MOSFET devices122,124each comprises a FUSI layer118and a metal layer116. Additionally, the first and second MOSFET devices122,124respectively comprise a first and second well regions304,308as described inFIG. 3. In some embodiments, the first and second MOSFET devices122,124respectively comprise deep well regions disposed beneath the first and second well regions304,308. In some embodiments, the first MOSFET device122is N-type and the second MOSFET device124is P-type, or vice versa. In some embodiments, the first and second MOSFET devices122,124are both either N-type or P-type.

FIGS. 5, 6, 7A, 8-16illustrate cross-sectional views500,600,700a,800-1600of some embodiments of a method of forming an IC including a MOSFET device with a FUSI layer and metal layer according to the present disclosure. Although the cross-sectional views500,600,700a,800-1600shown inFIGS. 5, 6, 7A, 8-16are described with reference to a method, it will be appreciated that the structures shown inFIGS. 5, 6, 7A, 8-16are not limited to the method but rather may stand alone separate of the method. AlthoughFIGS. 5, 6, 7A, 8-16are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As shown in cross-sectional view500ofFIG. 5, an isolation structure202is formed, extending into an upper or top surface of a substrate101to provide electrical isolation between a MOSFET device and neighboring devices. The substrate101may, for example, be a bulk monocrystalline silicon substrate, some other suitable bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate. The isolation structure202includes a pair of isolation segments. In some embodiments, the isolation structure202comprises a dielectric material, and/or is a shallow trench isolation (STI) structure, a deep trench isolation structure (DTI), or some other suitable isolation structure. In some embodiments, the forming of the isolation structure202comprises patterning the substrate101to form a trench and filling the trench with a dielectric material. In some embodiments, a well region is formed within the substrate101between the pair of isolation segments of the isolation structure202. In some embodiments, a deep well region is formed beneath the well region.

As shown in cross-sectional view600ofFIG. 6, a gate dielectric layer112is formed over the substrate101. A first dielectric layer114is formed over the gate dielectric layer112. A metal layer116is formed over the first dielectric layer114. The gate dielectric layer112, first dielectric layer114, and metal layer116may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process(es), or any combination of the foregoing.

As shown in cross-sectional view700aofFIG. 7A, a polysilicon layer204is formed over the metal layer116. A masking layer210is formed over the polysilicon layer204. The masking layer210comprises a set of two sidewalls defining a first opening702and a second opening704. The first and second openings702,704expose an upper surface of the polysilicon layer204. The polysilicon layer204, and masking layer210may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process(es), or any combination of the foregoing.

In some embodiments, the metal layer116may, for example, be or comprise titanium nitride (TiN). The polysilicon layer204forms in a uniform thickness over the metal layer116mitigating defects within the polysilicon layer204(e.g., hump defects). In some embodiments, this process ensures a plurality of MOSFET devices respectively have a substantially uniform height.

FIG. 7Billustrates a top-view of some additional embodiments of an IC700b.

The IC700bcomprises a top-view of a silicon wafer706along a horizontal line (between A and A′ ofFIG. 7A) of cross-sectional view700aofFIG. 7A. The horizontal line (between A and A′ ofFIG. 7A) is aligned with an upper surface of the polysilicon layer204. A plurality of hump defects204aare distributed across the silicon wafer706. The plurality of hump defects204aare raised above the upper surface of the polysilicon layer204. The difference in height between the plurality of hump defects204aand the upper surface of the polysilicon layer204is due to processing errors (e.g. grain boundaries) with forming the polysilicon layer204over the gate dielectric layer (112ofFIG. 7A) resulting in the plurality of hump defects204a. In some embodiments, the plurality of hump defects204acomprise 10 or less hump defects across the silicon wafer706, in comparison an embodiment without the metal layer (116ofFIG. 7A) comprises 1000 or more hump defects across the silicon wafer706. In some embodiments, there are no hump defects and the plurality of hump defects204aare not present, resulting in the polysilicon layer204comprising a substantially level and uniform upper surface. In some embodiments, the polysilicon layer204is aligned with a horizontal line. Thus, the presence of the metal layer (116ofFIG. 7A) overcomes processing errors with the polysilicon layer204and results in a uniform and hump defect free upper surface across the silicon wafer706.

As shown in cross-sectional view800ofFIG. 8, a patterning process is performed to remove a portion of the gate dielectric layer112, first dielectric layer114, metal layer116, and polysilicon layer204, directly below the first and second openings (702,704ofFIG. 7A). The patterning process respectively define a first hole802and a second hole804. In some embodiments, the patterning process may be performed by exposing layers underlying the first and second openings (702,704ofFIG. 7A) to an etchant806. The patterning process may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process(es).

A first source/drain region102and a second source/drain region104are formed within the substrate101directly below the first and second holes802,804. A first silicide region102aand a second silicide region104aare formed within the substrate101directly below the first and second holes802,804. The first and second source/drain regions102,104may, for example, be formed by ion implantation and/or some other suitable doping process(es) in which dopants are implanted into the substrate101.

As shown in cross-sectional view900ofFIG. 9, an etch stop layer208is formed over the masking layer210and lines an inner surface of the first and second holes802,804. The etch stop layer208has a U-shape within the first and second holes802,804.

As shown in cross-sectional view1000ofFIG. 10, a third dielectric layer206is formed over the etch stop layer208. The third dielectric layer206completely fills the first and second holes,802and804. A planarization process is performed (resulting structure is illustrated inFIG. 11) along a horizontal line1002. The planarization process removes a portion of the masking layer210, etch stop layer208, and third dielectric layer206. The planarization may, for example, be performed by a chemical mechanical planarization (CMP) process and/or some other suitable planarization process(es).

As shown in cross-sectional view1100ofFIG. 11, a second masking layer1102is formed over the masking layer210, etch stop layer208, and the third dielectric layer206. The second masking layer1102comprises sidewalls that define a third opening1104directly above the polysilicon layer204.

As shown in cross-sectional view1200ofFIG. 12, a patterning process is performed to remove a portion of the masking layer210and the polysilicon layer204defining a third hole1204. In some embodiments, the patterning process removes approximately 5 Angstroms to approximately 150 Angstroms of the polysilicon layer204, resulting in a center portion of the polysilicon layer204that is less thick than outer portions of the polysilicon layer204. In some embodiments, the patterning process may be performed by exposing the polysilicon layer204below the third opening (1104ofFIG. 11) to an etchant1202. The patterning process may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process(es).

As shown in cross-sectional view1300ofFIG. 13, a conductive layer1304is formed over the polysilicon layer204directly below the third hole1204. In some embodiments, the conductive layer1304is formed over the center portion of the polysilicon layer204and is laterally set back from outermost sidewalls of the polysilicon layer204by non-zero spaces. In some embodiments, the conductive layer1304may, for example, be or comprise nickel, platinum, palladium, cobalt, titanium, nickel silicide (NiSi), cobalt silicide (CoSi), titanium silicide (TiSi), copper silicide (CuSi), or the like formed to a thickness of approximately 25 Angstroms, 50 Angstroms, 75 Angstroms, or within a range of approximately 5 Angstroms to approximately 150 Angstroms.

An annealing process1306is performed to convert the center portion of the polysilicon layer204and the conductive layer1304into a FUSI layer (118ofFIG. 14). The annealing process1306converts an entire thickness of the center portion of the polysilicon layer204into the FUSI layer (118ofFIG. 14). The FUSI layer (118ofFIG. 14) may, for example, be or comprise a silicide of NiSi, CoSi, TiSi, CuSi, or the like formed to a thickness of approximately 169 Angstroms, 150 Angstroms, 300 Angstroms, or within a range of approximately 125 Angstroms to approximately 325 Angstroms. In some embodiments, a portion of the polysilicon layer outside of the center portion (e.g. portions of the polysilicon layer204outside of outer sidewalls of the FUSI layer118ofFIG. 14) is partially and/or fully silicided.

As shown in cross-sectional view1400ofFIG. 14, the second masking layer (1102ofFIG. 13) is removed by an etching process (not shown). In some embodiments, the etching process may use a dry etchant. In other embodiments, the etching process may use a wet etchant (e.g., acetone, NMP (1-methyl-2-pyrrolidon), or the like). A second dielectric layer212is formed over the FUSI layer118and the masking layer210.

As shown in cross-sectional view1500ofFIG. 15, a first ILD layer128is formed over the second dielectric layer212. First conductive contacts126are respectively formed over the first source/drain region102, second source/drain region104, and the FUSI layer118.

As shown in cross-sectional view1600ofFIG. 16, an interconnect structure1602is formed over the structure ofFIG. 15. The interconnect structure1602comprises ILD layers1604,1606, a plurality of wires1622, a plurality of vias1620, and a plurality of contact pads1624. The ILD layers1604,1606may, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing. The plurality of wires1622, plurality of vias1620, and plurality of contact pads1624may, for example, be respectively formed by: patterning the ILD layers1604,1606to form via, wire, or contact pad openings with a pattern of the vias1620, wires1622, or contact pads1624; depositing a conductive layer filling the via, wire, contact pad openings and covering the ILD layers1604,1606; and performing a planarization into the conductive layer until the ILD layer1604or1606is reached. The patterning may, for example, be performed by a photolithography/etching process and/or some other suitable patterning process(es). The depositing may, for example, be performed by CVD, PVD, electroless plating, electroplating, some other suitable deposition process(es), or any combination of the foregoing. The planarization may, for example, be performed by a CMP and/or some other suitable planarization process(es). The plurality of wires1622, plurality of vias1620, and plurality of contact pads1624may, for example, respectively be or comprises Al, Cu, or the like. For ease of illustration, only some of the plurality of wires1622, plurality of vias1620, and plurality of contact pads1624are labeled.

FIG. 17illustrates a method1700of forming a memory device in accordance with some embodiments. Although the method1700is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At1702, a first dielectric layer is formed over a substrate, a second dielectric layer is formed over the first dielectric layer, and a metal layer is formed over the second dielectric layer.FIG. 6illustrates a cross-sectional view600corresponding to some embodiments of act1702.

At1704, a polysilicon layer is formed over the metal layer and a first masking layer is formed over the polysilicon layer, the first masking layer defines openings.FIG. 7Aillustrates a cross-sectional view700acorresponding to some embodiments of act1704.

At1706, a portion of the polysilicon layer, metal layer, second dielectric layer, and first dielectric layer are removed directly below the openings exposing an upper surface of the substrate.FIG. 8illustrates a cross-sectional view800corresponding to some embodiments of act1706.

At1708, a first and second source/drain region are formed within the substrate.FIG. 8illustrates a cross-sectional view800corresponding to some embodiments of act1708.

At1710, an etch stop layer is formed over the first masking layer and the substrate.FIG. 9illustrates a cross-sectional view900corresponding to some embodiments of act1710.

At1712, a third dielectric layer is formed over the etch stop layer, filling the openings.FIG. 10illustrates a cross-sectional view1000corresponding to some embodiments of act1712.

At1714, a planarization process is performed to remove a portion of the first masking layer, third dielectric layer, and the etch stop layer.FIG. 10illustrates a cross-sectional view1000corresponding to some embodiments of act1714.

At1716, a second masking layer is formed over the first masking layer, covering the openings.FIG. 11illustrates a cross-sectional view1100corresponding to some embodiments of act1716.

At1718, a portion of the first masking layer and the polysilicon layer are removed.FIG. 12illustrates a cross-sectional view1200corresponding to some embodiments of act1718.

At1720, a conductive layer is formed over the polysilicon layer.FIG. 13illustrates a cross-sectional view1300corresponding to some embodiments of act1720.

At1722, the conductive layer and a center region of the polysilicon layer are converted into a FUSI layer.FIG. 13illustrates a cross-sectional view1300corresponding to some embodiments of act1722.

At1724, an ILD layer is formed over the FUSI layer and first masking layer.FIG. 15illustrates a cross-sectional view1500corresponding to some embodiments of act1724.

Accordingly, in some embodiments, the present application relates to a MOSFET device that comprises a gate structure with a thin FUSI layer formed directly above a metal layer.

In some embodiments, the present application provides a method for forming a fully silicided (FUSI) gated device including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer; forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, wherein the gate structure is formed before the first source and drain regions; performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer, wherein the first source and drain regions are formed before the first removal process; forming a conductive layer directly contacting the upper surface of the polysilicon layer after the first removal process; and converting the conductive layer and polysilicon layer into a FUSI layer.

In some embodiments, the present application provides a method for forming a fully silicided (FUSI) gated structure including: forming a masking layer over a gate structure comprising a polysilicon layer, wherein the masking layer comprises two sets of sidewalls respectively defining openings; selectively etching the polysilicon layer according to the masking layer to remove a portion of the gate structure directly below the openings; forming a first source/drain region and a second source/drain region within a substrate below the openings;

forming a first dielectric layer over the masking layer, wherein the first dielectric layer fills the openings; performing a planarization process to remove a portion of the masking layer and the first dielectric layer; performing a first etch to selectively remove parts of the masking layer and the polysilicon layer according to a second masking layer over the first masking layer and covering the openings; forming a conductive layer over the polysilicon layer; and performing an annealing process to convert the conductive layer and polysilicon layer into a silicide layer.

In some embodiments, the present application provides a fully silicided (FUSI) gated device including: a well region disposed within a substrate; a first dielectric layer in contact with the substrate; a high κ dielectric layer overlying the first dielectric layer; a metal layer overlying the high κ dielectric layer; a FUSI layer overlying the metal layer; and a polysilicon layer arranged along opposing sides of the FUSI layer, wherein a bottom surface of the polysilicon layer is aligned with a bottom surface of the FUSI layer, wherein the polysilicon layer has a greater thickness than the FUSI layer.