Anti-fuse circuit and semiconductor device having the same

A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0017091 filed on Feb. 20, 2012, the entire contents of which are incorporated herein by reference in their entirety.

BACKGROUND

Example embodiments relate to an anti-fuse circuit and a semiconductor device having the same.

A fuse or anti-fuse may be used for a semiconductor device, particularly, a semiconductor memory device. The fuse may be turned off when conditions are satisfied, while the anti-fuse may be turned on when desired conditions are satisfied. The fuse or anti-fuse may be used to select an operation mode of the semiconductor device, or enable a redundancy array when a defective cell is included in a memory cell array.

An anti-fuse circuit may break down a gate oxide layer of an anti-fuse cell transistor included in the anti-fuse circuit and sense a state of a broken anti-fuse. However, even if the gate oxide layer of the anti-fuse cell transistor is broken down, there may be cases where it is difficult or impossible to sense a state of the anti-fuse according to a breakdown state.

Accordingly, an anti-fuse circuit including not only a normal cell array having normal cell transistors but also a vote cell array having the same configuration as the normal cell array, has conventionally been used. As a result, an area occupied by the conventional anti-fuse circuit within a chip is increased.

SUMMARY

Some example embodiments provide an anti-fuse circuit capable of easily sensing an anti-fusing state.

Other embodiments provide a semiconductor memory device including the anti-fuse circuit.

Other embodiments provide a semiconductor device including the anti-fuse circuit.

The anti-fuse circuit includes an anti-fuse cell driving circuit and an anti-fuse cell array.

The anti-fuse cell driving circuit generates a normal cell driving voltage and a vote cell driving voltage. The anti-fuse cell array includes a plurality of anti-fuse cells, and each of the anti-fuse cells includes a normal cell transistor and a vote cell transistor connected in parallel to each other. The normal cell driving voltage applies to the normal cell transistor, and the vote cell driving voltage applies to the vote cell transistor. The normal cell transistor stores data in response to the normal cell driving voltage having the first voltage level and the vote cell driving voltage having the second voltage level. When the normal cell transistor has defect data, the vote cell transistor stores data in response to the vote cell driving voltage having the first voltage level.

In accordance with another example embodiment, an anti-fuse cell includes a first MOS transistor, a second MOS transistor, and a third MOS transistor.

The first MOS transistor has a control terminal to which a first cell driving voltage is applied, a first terminal, and a second terminal electrically connected to a first node. The first MOS transistor is configured to store data in response to the first cell driving voltage. The second MOS transistor has a control terminal to which a second cell driving voltage is applied, a first terminal, and a second terminal electrically connected to the first node. The second MOS transistor is configured to store data in response to the second cell driving voltage. The third MOS transistor has a control terminal to which a driving signal is applied, a first terminal connected to the first node, and a second terminal connected to a bit line in response to the driving signal. The third MOS transistor forms a current path between the first node and the bit line.

The first MOS transistor may be a normal cell transistor, and the second MOS transistor may be a vote cell transistor.

When an anti-fusing operation is performed on the normal cell transistor, the first cell driving voltage applied to the control terminal of the first MOS transistor may have a first voltage level, the second cell driving voltage applied to the control terminal of the second MOS transistor may have a second voltage level lower than the first voltage level, and a voltage having a third voltage level lower than the second voltage level may be applied to the bit line.

When an anti-fusing operation is performed on the vote cell transistor, the control terminal of the first MOS transistor may be floated, the second cell driving voltage applied to the control terminal of the second MOS transistor may have the first voltage level, and a voltage having the third voltage level lower than the second voltage level may be applied to the bit line.

In accordance with another example embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a redundant column decoder.

The memory cell array includes a normal memory cell array including a plurality of normal memory cells connected to word lines and column selection lines, and a redundant memory cell array including a plurality of spare memory cells connected to redundant word lines and redundant column selection lines. The column decoder decodes column address signals, generates column selection signals, and transmits the column selection signals to the column selection lines. When a defect occurs in at least one of normal memory cells connected to the column selection lines, the redundant column decoder decodes the column address signals, generates redundant column selection signals, and transmits the redundant column selection signals to the redundant column selection lines. The redundant column decoder includes an anti-fuse cell driving circuit and a anti-fuse cell. The anti-fuse cell driving circuit generates a normal cell driving voltage and a vote cell driving voltage. The anti-fuse cell includes a normal cell transistor and a vote cell transistor connected in parallel to each other, and performs a fuse operation in response to the normal cell driving voltage and the vote cell driving voltage.

In accordance with another example embodiment, a memory system includes a memory controller and a semiconductor memory device.

The memory controller generates an address signal and a command signal. The semiconductor memory device stores received data or outputs stored data in response to the address signal and the command signal. The semiconductor memory device includes an anti-fuse cell driving circuit and a anti-fuse cell. The anti-fuse cell driving circuit generates a normal cell driving voltage and a vote cell driving voltage. The anti-fuse cell includes a normal cell transistor and a vote cell transistor connected in parallel to each other, and performs a fuse operation in response to the normal cell driving voltage and the vote cell driving voltage.

In accordance with another example embodiment, a semiconductor device includes an anti-fuse circuit and an internal circuit.

The anti-fuse circuit includes an anti-fuse cell driving circuit and a anti-fuse cell. The anti-fuse cell driving circuit generates a normal cell driving voltage and a vote cell driving voltage. The unit anti-fuse cell includes a normal cell transistor and a vote cell transistor connected in parallel to each other, and performs a fuse operation in response to the normal cell driving voltage and the vote cell driving voltage.

In accordance with another example embodiment, a memory device includes an anti-fuse cell array including a plurality of anti-fuse cells, each anti-fuse cell including a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first and second cell transistors are configured to store data. The second cell transistor is configured to store data when the first cell transistor has defect data.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. It is important to understand that the present disclosure may be embodied in many alternate forms and should not be construed as limited to the example embodiments set forth herein. Accordingly, while the disclosure can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit the disclosure to the particular forms disclosed. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description.

It will be understood that, although the terms first, second, A, B, etc. may be used herein in reference to elements of the invention, such elements should not be construed as limited by these terms unless indicated otherwise. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the present disclosure. Herein, the term “and/or” includes any and all combinations of one or more referents.

Unless expressly defined in a specific order herein, respective steps described in the present disclosure may be performed otherwise. That is, the respective steps may be performed in a specified order, substantially at the same time, or in reverse order.

FIG. 1is a circuit diagram of an anti-fuse cell array100according to example embodiments.FIG. 1illustrates an example of an anti-fuse cell array100used for a semiconductor memory device.

Referring toFIG. 1, the anti-fuse cell array100may include unit anti-fuse cells110,115,120,125,130, and135configured to perform fuse operations in response to a first normal cell driving voltage NWP0, a first vote cell driving voltage VWP0, and a first word line driving signal NWL0, and unit anti-fuse cells140,145,150,155,160, and165configured to perform fuse operations in response to a second normal cell driving voltage NWP1, a second vote cell driving voltage VWP1, and a second word line driving signal NWL1. Each of the first and second normal cell driving voltages NWP0and NWP1, the first and second vote cell driving voltages VWP0and VWP1, and the first and second word line driving signals NWL0and NWL1may be generated in response to address signals. Each of the unit anti-fuse cells may include a normal cell transistor and a vote cell transistor connected in parallel to each other, and an output terminal of each of the unit anti-fuse cells may be electrically connected to the corresponding one of bit lines BL0, BL1, BL2, BL3, BL4, and BL5. Each of the bit lines BL0, BL1, BL2, BL3, BL4, and BL5may be selected in response to address signals.

AlthoughFIG. 1illustrates the anti-fuse cell array100including anti-fuse cells arranged in two rows, the anti-fuse cell array100may include anti-fuse cells arranged in an arbitrary number of rows.

FIG. 2is a circuit diagram of an example of a configuration of a unit anti-fuse cell110constituting the anti-fuse cell array ofFIG. 1according to example embodiments.

Referring toFIG. 2, the unit anti-fuse cell110may include a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3.

The first NMOS transistor MN1may have a control terminal to which the normal cell driving voltage NWP0is applied, a floated first output terminal, and a second output terminal electrically connected to a first node N1, and a gate insulating layer may be broken down in response to the normal cell driving voltage NWP0. The second NMOS transistor MN2may have a control terminal to which the vote cell driving voltage VWP0is applied, a floated first output terminal, and a second output terminal electrically connected to the first node N1, and a gate insulating layer may be broken down in response to the vote cell driving voltage VWP0. The third NMOS transistor MN3may have a control terminal to which a driving signal is applied, a first output terminal connected to the first node N1, and a second output terminal connected to the bit line BL0. A current path may be formed between the first node N1and the bit line BL0in response to the first word line driving signal NWL0.

InFIG. 2, the first NMOS transistor MN1may be a normal cell transistor, and the second NMOS transistor MN2may be a vote cell transistor.

FIG. 3is a circuit diagram of an operation of the unit anti-fuse cell ofFIG. 2when a gate oxide layer of a normal cell is broken down according to certain example embodiments.

Referring toFIG. 3, when an anti-fusing operation performs on a normal cell transistor, the normal cell driving voltage NWP0applied to the control terminal of the first NMOS transistor MN1may have a first voltage level, and the vote cell driving voltage VWP0applied to the control terminal of the second NMOS transistor MN2may have a second voltage level lower than the first voltage level. Also, a voltage having a third voltage level lower than the second voltage level may be applied to the bit line BL0.

In an example ofFIG. 3, a voltage of about 6.5V or 2Vcc (herein after, Vcc is a power supply voltage or a cell array voltage) may be applied to the control terminal of the first NMOS transistor MN1, a voltage of about 3V or Vcc may be applied to the control terminal of the second NMOS transistor MN2and the control terminal of the third NMOS transistor MN3, and a voltage of about 0V may be applied to the bit line BL0. Under these conditions, a gate oxide layer of the first NMOS transistor MN1may be broken down or ruptured, and a current path IPATH1leading from the control terminal of the first NMOS transistor MN1(i.e., a gate of the first NMOS transistor MN1) through the third NMOS transistor MN3to the bit line BL0may be formed. In one embodiment, a sensing circuit (not shown) may sense the current to output a logic low level or a logic high level depending on an amount of the current. For example, the sensing circuit may generate a logic high level when the current is higher than a certain value, and may generate a logic low level when the current is lower than the certain value. If the first NMOS transistor MN1has a defect data after performing the anti-fusing operation on the first NMOS transistor MN1, the sensing circuit may sense a low current. Accordingly, the first NMOS transistor MN1should not be used as an anti-fuse cell.

FIG. 4is a circuit diagram of an operation of the unit anti-fuse cell ofFIG. 2when a gate oxide layer of a vote cell is broken down according to certain example embodiments.

Referring toFIG. 4, when an anti-fusing operation performs on the vote cell transistor, the control terminal of the first NMOS transistor MN1may be floated, the vote cell driving voltage VWP0applied to the control terminal of the second NMOS transistor MN2may have the first voltage level, and a voltage having a third voltage level lower than the second voltage level may be applied to the bit line BL0. The anti-fusing operation on the second NMOS transistor MN2may be performed if the first NMOS transistor MN1has a defect data after performing the anti-fusing operation on the first NMOS transistor MN1.

In an example ofFIG. 4, the control terminal of the first NMOS transistor MN1may be floated, a voltage, for example, of about 6.5V or 2Vcc may be applied to the control terminal of the second NMOS transistor MN2, a voltage of about 3V or Vcc may be applied to the control terminal of the third NMOS transistor MN3, and a voltage of about 0V may be applied to the bit line BL0. Under these conditions, a gate oxide layer of the second NMOS transistor MN2may be broken down or ruptured, a current path IPATH2leading from the control terminal of the second NMOS transistor MN2(i.e., a gate of the second NMOS transistor MN2) through the third NMOS transistor MN3to the bit line BL0may be formed.

The unit anti-fuse cell110shown inFIG. 2may include an anti-fuse cell driving circuit configured to generate a normal cell driving voltage and a vote cell driving voltage, and a normal cell transistor and a vote cell transistor connected in parallel to each other. The unit anti-fuse cell110shown inFIG. 2may perform a fuse operation in response to the normal cell driving voltage and the vote cell driving voltage. Accordingly, an anti-fuse circuit including unit anti-fuse cells110may easily sense an anti-fusing state using a simple circuit configuration.

FIG. 5is a circuit diagram of another example of a configuration of the unit anti-fuse cell110constituting the anti-fuse cell array ofFIG. 1according to example embodiments.

Referring toFIG. 5, a unit anti-fuse cell110amay include a first NMOS transistor MN1, second NMOS transistors MN2a, MN2b, and MN2c, and a third NMOS transistor MN3.

The first NMOS transistor MN1may have a control terminal to which a normal cell driving voltage NWP0is applied, a floated first output terminal, and a second output terminal electrically connected to a first node N1, and a gate insulating layer may be broken down in response to a normal cell driving voltage NWP0. Each of the second NMOS transistors MN2a, MN2b, and MN2cmay have a control terminal to which vote cell driving voltages VWP0, VWP1, and VWP2is applied, respectively, a floated first output terminal, and a second output terminal electrically connected to a first node N1, and a gate insulating layer may be broken down in response to the vote cell driving voltages VWP0VWP1, and VWP2. For example, if each of the first NMOS transistor MN1and the second NMOS transistor MN2ahas a defect data after performing a respective anti-fusing operation, an anti-fusing operation may be performed on the second NMOS transistor MN2b. Furthermore, if each of the first NMOS transistor MN1and the second NMOS transistors MN2aand MN2bhas a defect data after performing a respective anti-fusing operation, an anti-fusing operation may be performed on the second NMOS transistor MN2c. The third NMOS transistor MN3may have a control terminal to which a driving signal is applied, a first output terminal connected to the first node N1, and a second output terminal connected to a bit line BL0. A current path maybe formed between the first node N1and the bit line BL0.

InFIG. 5, the first NMOS transistor MN1may be a normal cell transistor, and each of the second NMOS transistors MN2a, MN2b, and MN2cmay be a vote cell transistor. Since the unit anti-fuse cell110aofFIG. 5includes a plurality of vote cell transistors, a number of vote cell transistors to be fused may be controlled.

FIG. 6is a block diagram of an example of an anti-fuse circuit200including an anti-fuse cell array according to example embodiments.

The anti-fuse cell driving circuit210may generate normal cell driving voltages NWP0and NWP1and vote cell driving voltages VWP0and VWP1. The bit line cell array220may include a plurality of unit anti-fuse cells, and each of the unit anti-fuse cells may include a normal cell transistor and a vote cell transistor connected in parallel to each other, and perform an anti-fusing operation in response to the normal cell driving voltages NWP0and NWP1and the vote cell driving voltages VWP0and VWP1.

The anti-fuse cell driving circuit210may generate the normal cell driving voltages NWP0and NWP1and the vote cell driving voltages VWP0and VWP1based on one or more addresses and a control signal CON (e.g., test mode register set (TMRS) signal). The normal cell driving voltage NWP0and the vote cell driving voltage VWP0may be generated based on the same address, and the normal cell driving voltage NWP1and the vote cell driving voltage VWP1may be generated based on a same address. In one embodiment, the anti-fuse cell driving circuit210may generate the first and second word line driving signals NWL0and NWL1, and may select bit lines BL0through BL5based on address signals.

When an output current of the anti-fuse circuit200is not sufficiently large for a sensing operation after an anti-fusing operation is performed on the normal cell transistor, the anti-fuse circuit200shown inFIG. 6may perform an anti-fusing operation on the vote cell transistor.

FIG. 7is a block diagram of an example of a semiconductor memory device1000including an anti-fuse circuit according to example embodiments.

Referring toFIG. 7, the semiconductor memory device1000may include a memory cell array1100, a row address buffer1200, a column address buffer1250, a row decoder1350, a redundant row decoder1300, a column decoder1500, a redundant column decoder1550, a column selection circuit1400, and a redundant column selection circuit1450. Also, the semiconductor memory device1000may include a control circuit1600configured to generate control signals CON1, CON2, and CON3in response to command signals, such as a clock signal CLK, a clock enable signal CKE, a chip selection signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB, and control blocks constituting the semiconductor memory device1000.

The memory cell array1100may include a normal memory cell array1110including a plurality of normal memory cells connected to word lines and column selection lines, and a redundant memory cell array1120including a plurality of redundant memory cells connected to redundant word lines and redundant column selection lines. When at least one of the plurality of normal memory cells defects, the defect cell may be replaced with at least one of the plurality of redundant memory cells. The row address buffer1200may buffer address signals A0, A1, . . . , and Ap and generate row address signals RA0, RA1, . . . , and RAp. The column address buffer1250may buffer address signals A0, A1, . . . , and Ap and generate column address signals CA0, CA1, . . . , and CAq. In one embodiment, the address signals of the row address buffer1200may be different from the address signals of the column address buffer1250(for example, different address signals may be received from separate lines).

The row decoder1350may decode the row address signals RA0, RA1, . . . , and RAp, generate word line driving signals WL0, . . . , and WLn, and transmit the word line driving signals WL0, . . . , and WLn to the word lines. When defects occur in at least one of the word lines, the redundant row decoder1300may decode row address signals RA0, RA1, . . . , and RAp, generate redundant word line driving signals SWL0, . . . , and SWLm, and transmit the word line driving signals SWL0, . . . , and SWLm to the redundant word lines.

The column decoder1500may decode the column address signals CA0, CA1, . . . , and CAq, generate column selection signals CSL0, . . . , and CSLi, and transmit the column selection signals CSL0, . . . , and CSLi to the column selection lines. When defects occur in at least one of the column selection lines, the redundant column decoder1550may decode column address signals CA0, CA1, . . . , and CAq, generate redundant column selection signals SCSL0, . . . , and SCSLj and transmit the redundant column selection signals SCSL0, . . . , and SCSLj to the redundant column selection lines.

The column selection circuit1400may amplify column selection signals CSL0, . . . , and CSLi and control the input/output of data to/from the normal memory cell array1110. The redundant column selection circuit1450may amplify redundant column selection signals SCSL0, . . . , and SCSLj and control the input/output of data to/from the redundant memory cell array1120.

The redundant row decoder1300and/or redundant column decoder1550constituting the semiconductor memory device1000shown inFIG. 7may include an anti-fuse circuit according to example embodiments of the present disclosure. Each of unit anti-fuse cells of the anti-fuse circuit included in the redundant row decoder1300and/or the redundant column decoder1550of the semiconductor memory device1000may include a normal cell transistor and a vote cell transistor connected in parallel to each other. When an output current of the anti-fuse circuit is not sufficiently large for a sensing operation after performing the anti-fusing operation on the normal cell transistor, an anti-fusing operation may be performed on the vote cell transistor. Accordingly, the unit anti-fuse cells of the anti-fuse circuit included in the redundant row decoder1300and/or the redundant column decoder1550of the semiconductor memory device1000may easily sense an anti-fusing state using a simple circuit configuration.

Accordingly, when a defective cell is included in the normal memory cell array1110, the semiconductor memory device1000may safely replace the defective cell with a redundant memory cell.

AlthoughFIG. 7illustrates the semiconductor memory device1000including both the redundant row decoder1300and the redundant column decoder1550, the semiconductor memory device may include any one of the redundant row decoder1300and the redundant column decoder1550.

FIG. 8is a plan view of a semiconductor module2000in which a semiconductor memory device including an anti-fuse circuit according to example embodiments is mounted.

Referring toFIG. 8, the semiconductor module2000according to example embodiments may include a module substrate2010, a plurality of semiconductor memory devices2020, and a control chip package2030. Input/output (I/O) terminals2040may be formed in the module substrate2010. One or more of the semiconductor memory devices2020may include the anti-fuse circuit according to the foregoing example embodiments.

The semiconductor memory devices2020and the control chip package2030may be mounted on the module substrate2010. The semiconductor memory devices2020and the control chip package2030may be electrically connected to the I/O terminals2040in series or parallel.

The semiconductor module2000may not include the control chip package2030in some applications. Each of the semiconductor memory devices2020may include a volatile memory chip, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory chip, such as a flash memory, a phase-change memory, a magnetic RAM (MRAM), or a resistive RAM (RRAM), or a combination thereof, stacked chips may be used as well.

FIG. 9is a simplified perspective view of a stack semiconductor device2500including a semiconductor memory device having an anti-fuse circuit according to example embodiments.

Referring toFIG. 9, the stack semiconductor device2500may include an interface2510and memory chips2520,2530,2540, and2550electrically connected by through substrate vias, such as through-silicon vias (TSVs)2560. AlthoughFIG. 9illustrates the TSVs2560disposed in two rows, the stack semiconductor device2500may include an arbitrary number of TSVs.

Each of the memory chips2520,2530,2540, and2550included in the stack semiconductor device2500may include the anti-fuse circuit according to the foregoing example embodiments. The interface chip2510may serve as an interface between the memory chips2520,2530,2540, and2550and an external apparatus.

FIG. 10is a block diagram of an example of a memory system2600including an anti-fuse circuit according to example embodiments.

Referring toFIG. 10, the memory system2600may include a memory controller2610and a semiconductor memory device2620.

The memory controller2610may generate an address signal ADD and a command CMD, and transmit the address signal ADD and the command CMD to the semiconductor memory device2620through buses. Data DQ may be transmitted from the memory controller2610to the semiconductor memory device2620through the buses, or transmitted from the semiconductor memory device2620to the memory controller2610through the buses.

The semiconductor memory device2620may include an anti-fuse circuit, which may include an anti-fuse cell driving circuit and unit anti-fuse cells. The anti-fuse cell driving circuit may generate a normal cell driving voltage and a vote cell driving voltage. Each of the unit anti-fuse cells may include a normal cell transistor and a vote cell transistor connected in parallel to each other, and perform a fusing operation in response to the normal cell driving voltage and the vote cell driving voltage. Accordingly, the unit anti-fuse cells of the anti-fuse circuit included in the semiconductor memory device2620may easily sense an anti-fuse state using a simple circuit configuration.

FIG. 11is a block diagram of an example of a semiconductor device2700including an anti-fuse circuit according to example embodiments.

Referring toFIG. 11, the semiconductor device2700may include an anti-fuse circuit and an internal circuit2720.

The anti-fuse circuit2710may include an anti-fuse cell driving circuit and unit anti-fuse cells. The anti-fuse cell driving circuit may generate a normal cell driving voltage and a vote cell driving voltage. Each of the unit anti-fuse cells may include a normal cell transistor and a vote cell transistor connected in parallel to each other, and perform a fusing operation in response to the normal cell driving voltage and the vote cell driving voltage. Accordingly, the unit anti-fuse cells of the anti-fuse circuit2710may easily sense an anti-fusing state using a simple circuit configuration.

The anti-fuse circuit may perform an anti-fusing operation and generate an anti-fuse output voltage FOUT. The internal circuit2720may perform a specific operation in response to the anti-fuse output voltage FOUT. The specific operation may include selecting an operation mode of the semiconductor device2700, or enabling a redundancy array when a defective cell is included in a memory cell array.

FIG. 12is a block diagram of an example of an electronic system3000including a semiconductor memory device having an anti-fuse circuit according to example embodiments.

Referring toFIG. 12, the electronic system3000according to example embodiments may include a controller3010, an I/O device3020, a memory device3030, an interface3040, and a bus3050.

The bus3050may provide a path through which data may be transmitted among the controller3010, the I/O device3020, the memory device3030, and the interface3040.

The controller3010may include at least one of at least one microprocessor (MP), at least one digital signal processor (DSP), at least one microcontroller (MC), and logic devices capable of similar functions thereto. The I/O device3020may include at least one of a keypad, a keyboard, and a display device. The memory device3030may serve to store data and/or commands executed by the controller3010.

The memory device3030may include a volatile memory chip, such as a DRAM or an SRAM, a non-volatile memory chip, such as a flash memory, a phase-change memory, an MRAM), or an RRAM, or a combination thereof. The memory device3030may be a semiconductor memory device including the anti-fuse circuit according to the embodiments described herein.

The interface3040may serve to transmit/receive data to/from a communication network. The interface3040may include an antenna or a wired/wireless transceiver and transmit/receive data by wire or wirelessly. Also, the interface3040may include an optical fiber and transmit/receive data through the optical fiber. An application chipset, a camera image processor (CIP), and an I/O device may be further provided in the electronic system3000.

The electronic system3000may be embodied by a mobile system, a personal computer (PC), an industrial computer, or a logic system with various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer (PC), a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music system, and a data transmission/receiving system.

When the electronic system3000is an apparatus capable of wireless communication, the electronic system3000may be used for a communication system, such as a code division multiple access (CDMA), a global system for mobile communication (GSM), a North American digital cellular (NADC), an enhanced-time division multiple access (E-TDMA), a wideband code division multiple access (WCDMA), or CDMA2000.

The present disclosure may be applied to a semiconductor device, particularly, a semiconductor memory device and a memory module and memory system including the same.

An anti-fuse circuit according to example embodiments of the present disclosure may include an anti-fuse cell driving circuit configured to generate a normal cell driving voltage and a vote cell driving voltage, and a plurality of unit anti-fuse cells. Each of the unit anti-fuse cells can include a normal cell transistor and a vote cell transistor connected in parallel to each other, and perform a fuse operation in response to the normal cell driving voltage and the vote cell driving voltage. Accordingly, the anti-fuse circuit including the unit anti-fuse cells can easily sense an anti-fusing state, for example, a unit anti-fuse cell having a broken gate oxide layer, using a simple circuit configuration. As a result, a semiconductor device including the anti-fuse circuit according to the example embodiments may occupy a small area within a semiconductor chip and consume little power.