Data input circuit and memory device including the same

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2020-0032629, filed on Mar. 17, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Embodiments of the present disclosure relate to a memory device, and more particularly, to a memory device that receives test data through a test data input pad.

2. Description of the Related Art

With the rapid development of semiconductor memory technology, a high level of integration and performance is demanded in packaging semiconductor memory devices. To meet this demand, researchers and the industry are developing diverse technologies related to a three-dimensional structure in which a plurality of semiconductor memory chips are vertically stacked, rather than a two-dimensional structure in which semiconductor memory chips are planarly disposed on a printed circuit board (PCB) using wires or bumps.

Also, as the operation speeds of semiconductor memory devices increase, a semiconductor memory system of a System-In-Package (SIP) form in which a memory controller, such as a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU), and a semiconductor memory device are integrated into one package is widely used. Because the pads of a semiconductor memory device of the stacked structure or the SIP structure are not exposed to the outside of the semiconductor memory device, it is difficult to perform a direct test by using a pin of test equipment.

Therefore, a semiconductor memory device may be provided with an additional pad for testing. Inevitably, the number of test pads of an integrated and miniaturized semiconductor memory device may be limited, resulting in a need to develop a technology capable of testing a semiconductor memory device with a limited number of test pads.

SUMMARY

Some embodiments of the present teachings are directed to a data input circuit capable of setting and copying input data in diverse patterns, and a memory device including the data input circuit.

In accordance with an embodiment of the present disclosure, a memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

In accordance with another embodiment of the present disclosure, a memory device includes at least one test data input pad. The memory device also includes a test control circuit suitable for generating a first control signal and a plurality of second control signals based on test mode information in response to a test enable signal which is activated during a test operation. The memory device further includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting set data or test data received through the at least one test data input pad to the corresponding channels in response to the first control signal and the plurality of second control signals, respectively.

In accordance with yet another embodiment of the present disclosure, a memory device includes a base die and a plurality of core dies stacked over the base die. The base die includes at least one test data input pad. The base die also includes a plurality of data input circuits suitable for copying test data received through the at least one test data input pad and suitable for transmitting the copied test data to the core dies during a test operation. The base die further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the core dies during the test operation.

DETAILED DESCRIPTION

Embodiments of the present teachings will be described below in detail with reference to the accompanying drawings. The present teachings may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be enabling to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present teachings.

FIG.1is a plan view illustrating a memory system100in accordance with an embodiment of the present disclosure.

Referring toFIG.1, the memory system100may have a System-In-Package (SIP) structure. The memory system100may include a controller110and a plurality of memory devices120,121,122,123,124, and125.

The controller110may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), an Application Processor (AP), a memory controller chip, and the like. Diverse types of processing units may be included in the controller110in the form of a System-On-Chip (SDC). In other words, the controller110may represent one chip in which diverse systems are integrated.

Each of the memory devices120to125may include a plurality of integrated circuit chips. The integrated circuit chips may be stacked on one another and electrically connected using through silicon vias (TSVs). In other words, the memory devices120to125may be formed of high bandwidth memory (HBM) in which a bandwidth is increased by increasing the number of input/output units.

However, the present teachings are not limited thereto, and the memory devices120to125are not only volatile memory devices using memory such as Dynamic Random Access Memory (DRAM), but also non-volatile memory devices, such as a flash memory device, a Phase Change Random Access Memory device (PCRAM), and a Resistive Random Access Memory device (ReRAM), a ferroelectric memory device (FeRAM), a Magnetic Random Access Memory device (MRAM), a Spin Transfer Torque Random Access Memory device (STTRAM), or the like. Alternatively, the memory devices120to125may be formed as a combination of two or more of the volatile memory devices and the non-volatile memory devices.

The controller110and the memory devices120to125may be stacked over an interposer. The controller110and the memory devices120to125may communicate with each other through a signal path formed in the interposer. For communication with the controller110, the memory devices120to125may include PHY interfaces PHY0, PHY1, PHY2, PHY3, PHY4, and PHY5that are coupled to the interposer through micro bumps. However, it may be difficult to test the memory devices120to125through the PHY interfaces PHY0to PHY5because the physical size of the micro bumps is very small and the number of the micro bumps is more than approximately 1000.

Therefore, the memory devices120to125may include a Direct Access (DA) interfaces DA0, DA1, DA2, DA3, DA4, and DA5for directly accessing and testing the memory devices120to125, respectively, from the outside of the memory devices120to125. The DA interfaces DA0to DA5may be interfaced through the direct access pads having a relatively larger physical size and less in number than micro bumps and may be used for testing.

FIG.2is a cross-sectional view illustrating the memory system100shown inFIG.1.

FIG.2shows a structure in which the controller110and the first memory device120among the memory devices120to125are stacked. Although not illustrated inFIG.2, the second to sixth memory devices121to125may also have a stacked structure which is similar to that of the first memory device120.

The memory system100may further include a package substrate210and an interposer220which is stacked over the package substrate210. The interposer220may be stacked over the package substrate210or coupled to the package substrate210through electrical connection means, such as a bump ball, a ball grid array, and the like. The controller110and the first memory device120may also be stacked over the interposer220and electrically connected to the interposer220through a micro bump.

The first memory device120may include a plurality of integrated circuit chips230and240that are stacked on one another. The integrated circuit chips230and240may be electrically connected to each other through micro bumps and through silicon vias (TSVs) formed vertically penetrating the inside of the integrated circuits230and240to transmit and receive signals.

The integrated circuit chips230and240may include a base die230and a number of core dies240. The core dies240may be provided with data storage space, such as a memory cell array for storing data and a memory register. On the other hand, circuits for transmitting signals between the core dies240and the controller110may be disposed in the base die230.

As described above, the first memory device120may communicate with the controller110through the PHY interface250coupled to the micro bumps. Also, the first memory device120may be directly accessed and tested from the outside of the first memory device120through the DA interface260formed of direct access pads. The direct access pads may be provided in a relatively larger size and be smaller in number than the micro bumps.

FIG.3is a block diagram illustrating a memory device300shown inFIG.1.

FIG.3shows a base die of the memory device300, and it shows a portion related to a DA interface and a PHY interface. The memory device300may include a plurality of data input pads310to317, at least one test data input pad320, and a plurality of data input circuits330to337. The data input pads310to317may include a micro bump pad as the PHY interface. In a normal operation, data PHY_DQ<0:31> may be inputted from a host through the data input pads310to317.

The at least one test data input pad320may include a direct access pad as a DA interface. During a test operation, test data DA_DQ<0:3> may be inputted from the outside of the memory device300through the at least one test data input pad320.

The data input circuits330to337may correspond to a plurality of channels CH0to CH7, respectively. In a normal operation, the data input circuits330to337may transmit the data PHY_DQ<0:31> received by the data input pads310to317to the corresponding channels, respectively.

Meanwhile, during a test operation, the data input circuits330to337may transmit the test data DA_DQ<0:3> received by the at least one test data input pad320to the corresponding channels in response to a test enable signal EN. When the test enable signal EN is activated during the test operation, the data input circuits330to337may transmit the test data DA_DQ<0:3> received by the at least one test data input pad320to the channels CH0to CH7instead of the data PHY_DQ<0:31> received by the data input pads310to317.

As described above, the at least one test data input pad320may be relatively large in size and small in number compared to the data input pads310to317. Accordingly, during the test operation, the data input circuits330to337may copy the test data DA_DQ<0:3> received through the at least one test data input pad320and transmit the same data to the channels CH0to CH7.

In the test operation, the memory device300may transfer the test data DA_DQ<0:3> to core dies through the channels CH0to CH7. Data transferred to the core dies may be stored in memory cells included in the core dies. Herein, the memory device300may perform an error correction code (ECC) operation to detect and correct errors occurring in the data stored in the memory cells.

For example, the memory device300may generate parity data by performing an ECC encoding operation on the test data DA_DQ<0:3>, and store a codeword formed of the test data DA_DQ<0:3> and the parity data in memory cells. The memory device300may perform an ECC decoding operation on the data that are read from the memory cells and detect and correct errors occurring in the data stored in the memory cells based on the parity data.

During the test operation, an ECC operation of the memory device300may also be tested. The memory device300may check whether the ECC operation is normally performed or not based on the logic level of the parity data generated through the ECC operation. However, when data of the same pattern is used by copying the test data DA_DQ<0:3>, the parity data may also be generated in a uniform pattern. Therefore, it may be difficult to accurately test the ECC operation of the memory device300.

FIG.4is a block diagram illustrating a memory device400in accordance with an embodiment of the present disclosure.

FIG.4shows a base die of the memory device400, andFIG.4shows a portion related to the DA interface and the PHY interface. The memory device400may include a test control circuit410, a plurality of data input pads420to427, at least one test data input pad430, and a plurality of data input circuits440to447.

The data input pads420to427may include a micro bump pad as a PHY interface. In a normal operation, data PHY_DQ<0:31> may be inputted from a host through the data input pads420to427.

The at least one test data input pad430may include a direct access pad as a DA interface. During a test operation, test data DA_DQ<0:3> may be inputted from the outside of the memory device400through the at least one test data input pad430,

The data input circuits440to447may correspond to channels CH0to CH7, respectively. In a normal operation, the data input circuits440to447may transmit the data PHY_DQ<0:31> received by the data input pads420to427to the corresponding channels, respectively.

In a test operation, the test control circuit410may generate a first control signalENand a plurality of second control signals TM<0:7> based on test mode information TM in response to a test enable signal EN. Herein, the test enable signal EN may represent a signal that is activated during a test operation. The test mode information TM may be stored as a predetermined value in a mode register set, or the like, or the test mode information TM may be generated by combining addresses inputted from the outside of the memory device400during a test operation.

To be specific, the test control circuit410may generate the first control signalENby inverting the test enable signal EN. When the test enable signal EN is activated, the test control circuit410may select at least one signal among the second control signals TM<0:7> according to the code value of the test mode information TM and generate the first control signalENto have a different logic level from the logic levels of the other signals. For example, the test control circuit410may activate the other signals while deactivating the at least one selected signal among the second control signals TM<0:7>. As the at least one selected signal among the second control signals TM<0:7> is activated, the other signals may be deactivated, which may be realized differently according to an embodiment of the present teachings.

During a test operation, the data input circuits440to447may transmit set data or the test data DA_DQ<0:3> received through the at least one test data input pad430to the corresponding channels, respectively, in response to the first control signalENand the second control signals TM<0:7>. In other words, the data input circuit corresponding to the signal selected from the second control signals TM<0:7> among the data input circuits440to447may transmit the set data to the corresponding channel. On the other hand, the data input circuits corresponding to the other signals of the second control signals TM<0:7> among the data input circuits440to447may transmit the test data DA_DQ<0:3> to the corresponding channels.

Accordingly, during a test operation, the test control circuit410may select at least one data input circuit among the data input circuits440to447and control the selected data input circuit to transmit the set data to the corresponding channel by using the first control signalENand the second control signals TM<0:7>. The test control circuit410may control the other data input circuits among the data input circuits440to447except the selected data input circuit to transmit the test data DA_DQ<0:3> to the corresponding channels.

FIG.5is a block diagram illustrating the data input circuit440shown inFIG.4.

The data input circuit440may include a first transmitter510, a second transmitter520, a first driver530, a second driver540, and a signal combining unit550. AlthoughFIG.5illustrates one among the data input circuits440to447shown inFIG.4, all of the data input circuits440to447ofFIG.4may have similar structures with only a difference in their input and output signals.

The first transmitter510may transmit the data PHY_DQ<0:3> received by the corresponding data input pad420among the data input pads420to427in response to the first control signalENto a first node ND1. The first transmitter510may include a first inverter IV1and a first transfer gate TG1. The first inverter IV1may invert and output the first control signalEN, and the first transfer gate TG1may output the data PHY_DQ<0:3> to the first node ND1in response to the first control signalENand the output signal of the first inverter IV1.

The second transmitter520may transmit the test data DA_DQ<0:3> received through the at least one test data input pad430to the second node ND2in response to the corresponding second control signal TM<0> among the second control signals TM<0:7>. The second transmitter520may include a second inverter IV2and a second transfer gate TG2. The second inverter IV2may invert and output the corresponding second control signal TM<0>, and the second transfer gate TG2may output the test data DA_DQ<0:3> to the second node ND2in response to the corresponding second control signal TM<0> and the output signal of the second inverter IV2.

The first driver530may drive the first node ND1with a power supply voltage VDD level in response to the first control signalEN. The first driver530may include a first PMOS transistor PM1which is coupled between a power supply voltage VDD terminal and the first node ND1to receive the first control signalENthrough a gate.

The second driver540may drive the second node ND2with the power supply voltage VDD level in response to the corresponding second control signal TM<0> among the second control signals TM<0:7>. The second driver540may include a second PMOS transistor PM2that is coupled between the power supply voltage VDD terminal and the second node ND2to receive the corresponding second control signal TM<0> through a gate.

The signal combining unit550may combine the signals of the first node ND1and the second node ND2so as to produce a combined signal and output the combined signal to the corresponding channel CH0. The signal combining unit550may include a NAND gate that receives the signals from the first node ND1and the second node ND2and performs a logical operation.

When the test enable signal EN is deactivated during a normal operation, the test control circuit410may deactivate all of the second control signals TM<0:7> while generating the first control signalENat a logic high level. In response to the first control signalENof the logic high level, the first transmitter510may transmit the data PHY_DQ<0:3> to the first node ND1and the first driver530may be turned off. On the other hand, the second control signals TM<0:7> may be disabled, and the second transmitter520may block the transfer of the test data DA_DQ<0:3>, and the second driver540may drive the second node ND2with the power supply voltage VDD level. Therefore, the signal of the second node ND2may have a logic high level, and the signal combining unit550may transfer the data PHY_DQ<0:3> of the first node ND1to the corresponding channel CH0.

During a test operation, when the test enable signalENis activated, the test control circuit410may generate the first control signalENat a logic low level. In response to the first control signalENof the logic low level, the first transmitter510may block the transfer of the data PHY_DQ<0:3>, and the first driver530may drive the first node ND1with the power supply voltage VDD level.

Herein, when the test control circuit410selects and deactivates the corresponding second control signal TM<0> among the second control signals TM<0:7>, the second transmitter520may block the transfer of the test data DA_DQ<0:3>, and the second driver540may drive the second node ND2with the power supply voltage VDD level. Accordingly, the signals of the first node ND1and the second node ND2may all have a logic high level, and the signal combining unit550may transfer the data that are set to a logic low level to the corresponding channel CH0.

Meanwhile, when the test control circuit410selects another second control signal among the second control signals TM<0:7> and activates the corresponding second control signal TM<0>, the second transmitter520may transmit the test data DA_DQ<0:3> to the second node ND2, and the second driver540may be turned off. Therefore, the signal of the first node ND1may have a logic high level, and the signal combining unit550may transfer the test data DA_DQ<0:3> of the second node ND2to the corresponding channel CH0.

FIG.6is a signal waveform diagram illustrating an operation of the memory device400in accordance with the embodiment of the present disclosure.

When the memory device400enters a test mode, the test enable signal EN may be activated. Subsequently, after a write latency WL according to a write command WR directing a write operation, the memory device400may be synchronized with a data strobe signal WDQS to receive the test data DA_DQ<0:3> through the test data input pad430.

The test control circuit410may deactivate the first control signalENby inverting the activated test enable signal EN. Accordingly, the first transmitter of each of the data input circuits440to447may block the transfer of the data PHY_DQ<0:31>, and the first driver of each of the data input circuits440to447may drive the first node with the power supply voltage VDD level.

Herein, as illustrated as an example inFIG.6, the test control circuit410may select and deactivate a second signal among the second control signals TM<0:7> according to the test mode information TM. Accordingly, among the data input circuits440to447, the second transmitter of the second data input circuit may block the transfer of the test data A, B, C, and D, and the second driver of the second data input circuit may drive the second node with the power supply voltage VDD level. As a result, the second data input circuit of the data input circuits440to447may transmit data that are set to a logic low level 0 to the corresponding channel CH1.

Meanwhile, the test control circuit410may activate the other second control signals except the selected second control signal among the second control signals TM<0:7>. Therefore, in the other data input circuits except the second data input circuit among the data input circuits440to447, the second transmitter may transmit the test data A, B, C, and D to the second node, and the second driver may be turned off. As a result, the other data input circuits except the second data input circuit among the data input circuits440to447may transmit the test data A, B, C, and D to the corresponding channels CH0and CH2to CH7.

The memory device400in accordance with the embodiment of the present disclosure may be able to mask some data based on the test mode information TM and transfer set data by copying data received by the test input pad430and transferring the copied data to the channels CH0to CH7. The memory device400may be able to transfer data of a pattern that is set according to a test operation to the channels CH0to CH7. Accordingly, result data according to various operations of the memory device400may be predicted, and the coverage of an operation that may be tested may be increased.

According to the embodiment of the present disclosure, a memory device may be tested by copying data received through a limited number of test input pads, thereby minimizing the number of the test input pads and increasing the efficiency of a test operation. Also, when the received data are copied, the copied data may be set in diverse patterns to test diverse operations of the memory device.

For example, a plurality of data input circuits that receive and copy data may be selectively disabled according to test mode information. In other words, it is possible to selectively mask some data that are copied by the data input circuits. Accordingly, the pattern of data generated by various operations of the memory device, such as an Error Correction Code (ECC) operation, etc., may also be predicted by using data of a desired pattern, thereby increasing the coverage of the test operation.

While the present teachings have been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the following claims.