Vertical 3D single word line gain cell with shared read/write bit line

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

BACKGROUND

Memory devices are widely used in computers and many other electronic items to store information. Memory devices are generally categorized into two types: volatile memory device and non-volatile memory device. An example of a volatile memory device includes a dynamic random-access memory (DRAM) device. An example of a non-volatile memory device includes a flash memory device (e.g., a flash memory stick). A memory device usually has numerous memory cells to store information. In a volatile memory device, information stored in the memory cells are lost if supply power is disconnected from the memory device. In a non-volatile memory device, information stored in the memory cells are retained even if supply power is disconnected from the memory device.

The description herein involves volatile memory devices. Most conventional volatile memory devices store information in the form of charge in a capacitor structure included in the memory cell. As demand for device storage density increases, many conventional techniques provide ways to shrink the size of the memory cell in order to increase device storage density for a given device area. However, physical limitations and fabrication constraints may pose a challenge to such conventional techniques if the memory cell size is to be shrunk to a certain dimension. Unlike some conventional memory devices, the memory devices described herein include features that can overcome challenges faced by conventional techniques.

DETAILED DESCRIPTION

The memory device described herein includes volatile memory cells having a charge storage node (e.g., structure) that can be a floating gate structure). Each of the described memory cells can include two transistors (2T memory cell). One of the two transistors is a charge storage transistor having the charge storage structure of the memory cell (such as, for example, a floating gate of a floating gate memory cell, or a charge trap structure of a charge trap memory cell). The memory device described herein can have structure that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices, such that Information can be stored in a storage node of the memory cell. Different variations of the described memory device are discussed in detail below with reference toFIG. 1throughFIG. 12.

FIG. 1shows a block diagram of an apparatus in the form of a memory device100including volatile memory cells, according to some embodiments described herein. Memory device100includes a memory array101, which can contain memory cells102. Memory device100is volatile memory device (e.g., a DRAM device), such that memory cells102are volatile memory cells. Thus, information stored in memory cells102may be lost (e.g., invalid) if supply, power (e.g., supply voltage Vcc) is disconnected from memory device100. Hereinafter, Vcc is referred to represent some voltage levels, however, they are not limited to a supply voltage (e.g., Vcc) of the memory device (e.g., memory device100). For example, if the memory device (e.g., memory device100) has an internal voltage generator (not shown inFIG. 1) that generates an internal voltage based on Vcc, such an internal voltage may be used instead of Vcc.

In a physical structure of memory device100, memory cells102can be formed vertically (e.g., stacked over each other in different layers) in different levels over a substrate (e.g., semiconductor substrate) of memory device100. The structure of memory array101including memory cells102can include the structure of memory arrays and memory cells described below with reference toFIG. 2throughFIG. 6.

As shown inFIG. 1, memory device100can include access lines104(or “word lines”) and data lines (or “bit lines”)105. Memory device100can use signals word line signals) on access lines104to access memory cells102and data lines105to provide information (e.g., data) to be stored in (e.g., written) or sensed (e.g., read) from memory cells102.

Memory device100can include an address register106to receive address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines)107. Memory device100can include row access circuitry (e.g., X-decoder)108and column access circuitry Y-decoder)109that can operate to decode address information ADDR from address register106. Based on decoded address information, memory device100can determine which memory cells102are to be accessed during a memory operation. Memory device100can perform a write operation to store information in memory cells102, and a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells102. Memory device100can also perform an operation (e.g., a refresh operation) to refresh (e.g., to keep valid) the value of information stored in memory cells102. Each of memory cells102can be configured to store information that can represent at most one bit (e.g., a single hit having a binary 0 (“0”) or a binary 1 (“1”), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

Memory device100can receive a supply voltage, including supply voltages Vcc and Vss, on lines130and132, respectively. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuitry.

As shown inFIG. 1, memory device100can include a memory control unit118to control memory operations (e.g., read and write operations) of memory device100based on control signals on lines (e.g., control lines)120. Examples of signals on lines120include a row access strobe signal RAS*, a column access strobe signal CAS*, a write-enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock-enable signal CKE. These signals can be part of signals provided to a DRAM device.

As shown inFIG. 1, memory device100can include lines (e.g., global data lines)112that can carry signals DQ0through DQN. In a read operation, the value (e.g., logic 0 and logic 1) of information (read from memory cells102) provided to lines112(in the form signals DQ0through DQN) can be based on the values of signals DL0and DL0* through DLNand DLN* on data lines105. In a write operation, the value (e.g., “0” (binary 0) or “1” (binary 1)) of the information provided to data lines105(to be stored in memory cells102) can be based on the values of signals DQ0through DQN on lines112.

Memory device100can include sensing circuitry103, select circuitry115, and input/output (I/O) circuitry116. Column access circuitry109can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuitry115can respond to the signals on lines114to select signals on data lines105. The signals on data lines105can represent the values of information to be stored in memory cells102(e.g., during a write operation) or the values of information read (e.g., sensed) from memory cells102(e.g., during a read operation).

I/O circuitry116can operate to provide information read from memory cells102to lines112(e.g., during a read operation) and to provide information from lines112(e.g., provided by an external device) to data lines105to be stored in memory cells102(e.g., during a write operation). Lines112can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside. Other devices external to memory device100(e.g., a memory controller or a processor) can communicate with memory device100through lines107,112, and120.

Memory device100may include other components, which are not shown to help focus on the embodiments described herein. Memory device100can be configured to include at least a portion of the memory device with associated structures and operations described below with reference toFIG. 2throughFIG. 6.

One of ordinary skill in the art may recognize, upon reading this description, that memory device100may include other components, several of which are not shown inFIG. 1so as not to obscure the example embodiments described herein. At least a portion of memory device100(e.g., a portion of memory array101) can include structures similar to or identical to any of the memory devices described below with reference toFIGS. 2-6.

FIG. 2shows a schematic diagram of a portion of a memory device200including a memory array201, according to some embodiments described herein. Memory device200can correspond to memory device100ofFIG. 1. For example, memory array201can form part of memory array101ofFIG. 1. As shown inFIG. 2, memory device200can include memory cells210through215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements among memory cells210through215are given the same labels.

Each of memory cells210through215can include two transistors T1and T2. Thus, each of memory cells210through215can be called a 2T (two-transistor) memory cell. Each of transistors T1and T2can include a field-effect transistor (FET). Transistor T1can include a floating-gate based transistor. Each of memory cells210through215can include a charge storage node202, which can include the floating gate (e.g., floating gate202) of transistor T1. Charge storage node202can store charge. Charge storage node202is the memory element of a respective memory cell among memory cells210through215. The value (e.g., “0” or “1”) of information stored in a particular memory cell among memory cells210through215can be based on the amount of charge in charge storage node202of that particular memory cell. As shown inFIG. 2, a non-gate terminal (e.g., source or drain) of transistor T2of a particular memory cell among memory cells210through215can be directly coupled to (e.g., electrically in contact with) charge storage node202of that particular memory cell.

Memory cells210through215can be arranged in memory cell groups2010and2011.FIG. 2shows two memory cell groups (e.g.,2010and2011) as an example. However, memory device200can include more than two memory cell groups. Memory, cell groups2010and2011can include the same number of memory cells. For example, memory cell group2010can include memory cells210,212, and214, and memory cell group2011can include memory cells221,213, and215.FIG. 2shows three memory cells in each of memory cell groups2010and2011as an example. The number of memory cells in memory cell groups2010and2011can be different from three.

Memory device200can perform a write operation to store information in memory cells210through215, and a read operation to read (e.g., sense) information from memory cells210through215. Memory cells210through215can be randomly selected during a read or write operation. Thus, memory device200can be called a dynamic random-access memory device (DRAM) device. Unlike some conventional DRAM devices that store information in a structure such as a capacitor, memory device200can store information in the form of charge in charge storage node202. As mentioned above, charge storage node202can be the floating gate (e.g., floating gate202) of transistor T1. Thus, memory device200can also be called a floating-gate based DRAM device.

Memory device200can include access lines (e.g., word lines)241,242, and243that can carry respective signals (e.g., word line signals) WL1, WL2, and WL3. Access lines241,242, and243can be shared between memory cell groups2010and2011. Access lines241,242, and243can be selectively activated (e.g., activated one at a time) during an operation read or write operation) of memory device200to access a selected memory cell (or selected memory cells) among memory cells210through215. A selected cell can be referred to as a target cell. In a read operation, information can be read from a selected memory cell (or selected memory cells). In a write operation, information can be stored information in a selected memory cell (or selected memory cells).

In memory device200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or turn off) transistors T1and T2of a respective memory cell during either a read or write operation of memory device200. Some conventional memory devices may use multiple (e.g., two separate) access lines to control access to a respective memory cell during read and write operations. In comparison with such conventional memory devices (that use multiple access lines for the same memory cell), using a single access line in memory device200to control access to a respective memory cell (e.g., to control both transistors T1and T2) can save space and simplify operation of memory device200.

In memory device200, the gate of each of transistors T1and T2can be part of a respective access line (e.g., a respective word line). For example, the gate of each of transistors T1and T2of memory cells210and221can be part of access line241. The gate of each of transistors T1and T2of memory cells212and213can be part of access line242. The gate of each of transistors T1and T2of memory cells214and215can be part of access line243.

As shown inFIG. 2, memory device200can include data lines (e.g., bit lines)221,221′,222, and222′ that can carry respective signals (e.g., bit line signals) BL1, BL1*, BL2, and BL2*. During a read operation, memory device200can use data lines221and221′ to read information from a selected memory cell of memory cell group2010, and data lines222and222′ to read information from a selected memory cell of memory cell group2011. During a write operation, memory device200can use data line221to store information in a selected memory cell of memory cell group2010, and data line222to store information in a selected memory cell of memory cell group2011.

Transistor T1includes a channel portion between the source and drain (e.g., non-gate terminals) of transistor T1. Transistor T2includes a channel portion between the source and drain (e.g., non-gate terminals) of transistor T2. The two channel portions of respective transistors T1and T2can be controlled by the same access line (e.g., by a single word line), such as one of access lines241,242, and243. The channel portion of transistor T2can be formed from a material or a combination of materials a high band-gap material) that can provide a relatively low leakage between charge storage node202of a respective memory cell and data line221or222. Such a low leakage can improve accuracy of information read from a selected memory cell and can improve the retention of information stored in the selected memory cell.

Memory device200can include read paths (e.g., circuit paths). Information read from a selected memory cell during a read operation can be obtained through a read path coupled to the selected memory cell. In memory cell group2010, a read path of a particular memory cell (e.g.,210,212, or214) can include transistor T1(e.g., can include a read current path through the source, drain, and channel portion of transistor T1) of that particular memory cell and data lines221and221′. In memory cell group2011, a read path of a particular memory cell (e.g.,221,213, or215) can include transistor T1(e.g., can include a read current path through the source, drain, and channel portion of transistor T1) of that particular memory cell and data lines222and222′. Since transistor T1can be used in a read path to read information from the respective memory cell during a read operation, transistor T1can be called a read transistor.

Memory device200can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell through a write path coupled to the selected memory cell. In memory cell group2010, a write path of a particular memory cell can include transistor T2(e.g., can include a write current path through the source, drain, and channel portion of transistor T2) of that particular memory cell and data line221. In memory cell group2011, a write path of a particular memory cell (e.g.,221,213, or215) can include transistor T2(e.g., can include a write current path through the source, drain, and channel portion of transistor T2) of that particular memory cell and data line222. Since transistor T2can be used in a write path to store information in a respective memory cell during a write operation, transistor T2can be called a write transistor.

Each of transistors T1and T2can have a threshold voltage (Vt). Transistor T1has a threshold voltage Vt1. Transistor T2has a threshold voltage Vt2. The value of threshold voltage Vt2can be greater than the value of threshold voltage Vt1. The difference in values of threshold voltages Vt1and Vt2allows reading (e.g., sensing) of information stored in charge storage node202in transistor T1on the read path without affecting (e.g., without turning on) transistor T2on the write path (e.g., path through transistor T2). This can prevent leaking of charge from charge storage node202to the write path.

In a structure of memory device200, transistor T1can be formed (e.g., engineered) such that threshold voltage Vt1of transistor T1can be less than zero volts (e.g., Vt1<0V) regardless of the value information stored charge storage node202of transistor T1(e.g., regardless of the state (e.g., “0” or “1”) of charge storage node202). Thus, in this structure, the relationship between the values of threshold voltages Vt1and Vt2can be express as follows, Vt1for state “0”<Vt1for state “1”<0V and Vt2=0V (or alternatively Vt2>0V).

In an alternative structure of memory device200, transistor T1can be formed (e.g., engineered) such that threshold voltage Vt1of transistor T1can be less than zero volts if information stored in memory cell210through215has one value corresponding to a particular state (e.g., Vt1<0V (or alternatively Vt1=0V) for state “0”), and such that threshold voltage Vt1of transistor T1can be greater than zero volts if information stored in memory cell210through215has another value corresponding to another particular state (e.g., Vt1>0V for state “1”, and Vt2>Vt1). Thus, in the alternative structure, the relationship between the values of threshold voltages Vt1and Vt2can be express as follows, Vt1for state “0”<Vt1for state “1”<Vt2, where Vt1for state “0”<0V (or alternatively Vt1for state “0”=0V) and Vt1for state “1”>0V.

In another alternative structure, transistor T1can be formed (e.g., engineered) such that threshold voltage Vt1of transistor T1can be at least zero volts (e.g., Vt1=0 or Vt1>0V) regardless of the information stored in charge storage node202of transistor T1(e.g., regardless of the state (e.g., “0” or “1”) of charge storage node202). Thus, in this alternative structure, the relationship between the values of threshold voltages Vt1and Vt2can be express as follows, Vt1(for state “0”)<Vt1(for state “1”)<Vt2, where Vt1for state “0”=0V (or alternatively Vt1for state “0”>0V.

During read operation of memory device200, only one memory cell of the same memory cell group can be selected one at a time to read information from the selected memory cell. For example, only memory cell210,212, or214of memory cell groups2010can be selected at a time during a read operation to read information from the selected memory cell (e.g., memory cell210,212, or214in this example). In another example, only memory cell221,213, or215of memory cell groups2011can be selected one at a time during a read operation to read information from the selected memory cell (e.g., memory cell221,213, or215in this example).

During read operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2011) that share the same access line (e.g., word line241,242, or243) can be concurrently selected (or alternatively can be sequentially selected). For example, memory cells210and221can be concurrently selected during a read operation to read concurrently read) information from memory cells210and221. Memory cells212and213can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells212and213. Memory cells214and215can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells214and215.

The value of information read from the selected memory cell of memory cell group2010during a read operation can be determined based on the value of a current detected (e.g. sensed) from a read path (described above) that includes transistor T1of the selected memory cell (e.g., memory cell210,212, or214) and data lines221and221′. The value of information read from the selected memory cell of memory cell group2011during a read operation can be determined based on the value of a current detected (e.g. sensed) from a read path that includes transistor T1of the selected memory cell (e.g., memory cell221,213, or215) and data lines222and222′.

Memory device200can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., I1, not shown) on a read path that includes data lines221and221′ and a current (e.g., I2, not shown) on a read path that includes data lines222and222′. The value of the detected current can be based on the value of information stored in the selected memory cell. For example, depending on the value of information stored in the selected memory cell of memory cell group2010, the value of the detected current (e.g., the value of I1) between data lines221and221′ can be zero or greater than zero. Similarly, depending on the value of information stored in the selected memory cell of memory cell group2011, the value of the detected current (e.g., the value of I2) between data lines222and222′ can be zero or greater than zero. Memory device200can include circuitry (not shown) to translate the value of detected current into the value (e.g., “0”, or a combination of multi-bit values) of information stored in the selected memory cell.

During write operation of memory device200, only one memory cell of the same memory cell group can be selected one at a time to store information in the selected memory cell. For example, only memory cell210,212, or214of memory cell groups2010can be selected one at a time during a write operation to store information in the selected memory cell (e.g., memory cell210,212, or214in this example). In another example, only memory cell221,213, or215of memory cell groups2011can be selected one at a time during a write operation to store information in the selected memory cell (e.g., memory cell221,213, or215in this example).

During write operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2010that share the same access line (e.g., word line241,242, or243) can be concurrently selected. For example, memory cells210and221can be concurrently selected during a write operation, operation to store (e.g., concurrently store) information in memory cells210and221. Memory cells212and213can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells212and213. Memory cells214and215can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells214and215.

Information to be stored in a selected memory cell of memory cell group2010during a write operation can be provided through a write path (describe above) that includes data line221and transistor T2of the selected memory cell (e.g., memory cell210,212, or214). Information to be stored in a selected memory cell of memory cell group2011during a write operation can be provided through a write path (described above) that includes data line222and transistor T2of the selected memory cell (e.g., memory cell221,213, or215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells210through215can be based on the amount of charge in charge storage node202of that particular memory cell.

In a write operation, the amount of charge in charge storage node202of a selected memory cell can be changed (to reflect the value of information stored in the selected memory cell) by applying a voltage on a write path that includes transistor T2of that particular memory cell and the data line (e.g., data line221or222) coupled to that particular memory cell. For example, a voltage having one value (e.g., 0V) can be applied on data line221(e.g., provide 0V to signal BL1) if information to be stored in a selected memory cell among memory cells210,212, and214has one value (e.g., “0”). In another example, a voltage having another value (e.g., a positive voltage) can be applied on data line221(e.g., provide a positive voltage to signal BL1) if information to be stored in a selected memory cell among memory cells210,212, and214has another value (e.g., “1”). Thus, information can be stored (e.g., directly stored) in charge storage node202of a particular memory cell by providing the information (to be stored) through a write path that includes transistor T2of that particular memory cell and the data line (e.g., data line221or222) coupled to that particular memory cell.

FIG. 3shows memory device200ofFIG. 2including example voltages V0, V1, V2, and V3used during a read operation of memory device200, according to some embodiments described herein. The example ofFIG. 3assumes that memory cell210is a selected memory cell (e.g., target memory cell) during a read operation to read (e.g., to sense) information stored (e.g., previously stored) in memory cell210. Memory cells211through215are assumed to be unselected memory cells. This means that memory cells211through215are not accessed and information stored in memory cells211through215are not read while information is read from memory cell210in the example ofFIG. 3.

InFIG. 3, voltages V0, V1, V2, and V3can represent different voltages applied to respective access lines214,242, and243, and data lines221,221*,222, and222* during a read operation of memory device200. As an example, voltages V0, V1, V2, and V3can have values of 0V ground), −0.3V, −0.75V, and 0.5V, respectively. Different values may be used.

In the read operation shown inFIG. 3, voltage V1can have a value (a first read voltage value) to turn on read transistor T1of memory cell210(a selected memory cell in this example) and turn off (or keep off) write transistor T2of memory cell210. This allows in information to be read from memory cell210. Voltage V0and V2and can have values, such that transistors T1and T2of each of memory cells211through215(unselected memory cells in this example) are turned off (e.g., kept off). Voltage V3can have a second read voltage value, such that a current (e.g., read current) may be formed on a read path that include data lines221and221* and transistor T1of memory cell210. This allows a detection of current on the read path coupled to memory cell210. A detection circuitry (not shown) of memory device200can operate to translate the value of detected current (during reading of information from a selected memory cell) into the value (e.g., “0”, “1”, or a combination of multi-bit values) of information read from the selected memory cell. In the example ofFIG. 3, the value of detected current on data lines221and221* can be translated into the value of information read from memory cell210.

In the read operation shown inFIG. 3, the voltages applied to respective access lines241,242, and243can cause transistors T1and T2of each of memory cells211through215, except transistor T1of memory cell210, to turn off (or to remain turned off). Transistor T1of memory cell210may or may not turn on, depending on the value of the threshold voltage Vt1of transistor T1of memory cell210. For example, if transistor T1of each of memory cells (e.g.,210through215) of memory device200is formed such that Vt1<0V regardless of the value (e.g., the state) of information stored in a respective memory cell210, then transistor T1of memory cell210in this example can turn on and conduct a current between data lines221and221* (through transistor T1of memory cell210). Memory device200can determine the value of information stored in memory cell210based on the value of the current (e.g., measured by detection circuitry) between read data lines221and221*.

FIG. 4shows memory device200ofFIG. 2including example voltages V0, V4, V5, V6, and V7used during a write operation of memory device200, according to some embodiments described herein. The example ofFIG. 4assumes that memory cells210and211are selected memory cell (e.g., target memory cells) during a write operation to store information in memory cells210and211. Memory cells212through215are assumed to be unselected memory cells. This means that memory cells212through215are not accessed and information stored is not to be stored in memory cells212through215while information is stored in memory cells210and211in the example ofFIG. 4.

InFIG. 4, voltages V0, V4, V5, V6, and V7can represent different voltages applied to respective access lines214,242, and243, and data lines221,221′,222, and222′ during a write operation of memory device200. As an example, voltages V0, V4, and V5can have values of 0V, 3.3V, and −0.75V. These values are example values. Different values may be used. The values of voltages V6and V7can be the same or different depending the value (e.g., “0” or “1”) of information to be stored in memory cells210and211. For example, the values of voltages V6and V7can be the same if the memory cells210and211are to store information having the same value (e.g., V6=V7=0V if information to be stored in each memory cell210and211is “0”, and V6=V7=1V to 3V if information to be stored in each memory cell210and211is “1”). In another example, the values of voltages V6and V7can be different (e.g., V6≠V7) if the memory cells210and211are to store information having different values. For example, V6=0V and V7=1V to 3V if “0” to be stored in memory cell210and “1” is to be store in memory cell211). Different values may be used, or V6=1V to 3V and V7=0V if “1” to be stored in memory cell210and “0” is to be store in memory cell211). The range of voltage of 1V to 3V used in the examples here can be other positive values different from the range of 1V to 3V.

In a write operation of memory device200, voltage V5can have a value, such that transistors T1and T2of each of memory cells212through215(unselected memory cells in this example) are turned off (e.g., kept off). Voltages V4can have a value to turn on transistor T2of each of memory cells210and211(selected memory cells in this example) and form a write path between charge storage node202of memory cell210and data line221and a write path between charge storage node202of memory cell211and data line222. A current (e.g., write current) may be formed between charge storage node202of memory cell210and data line221. This current can change the amount of charge on charge storage node202of memory device210to reflect the value of information to be stored in memory cell210. Another current (e.g., another write current) may be formed between charge storage node202of memory cell211and data line222. This current can change the amount of charge on charge storage node202of memory, device211to reflect the value of information to be stored in memory cell211.

In the example write operation ofFIG. 4, the value of voltage V6may cause charge storage node202of memory cell210to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage node202of memory cell210can reflect the value of information stored in memory cell210. Similarly, the value of voltage V7in this example may cause charge storage node202of memory cell211to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage node202of memory cell211can reflect the value of information stored in memory cell211.

FIG. 5Ais an illustration of the structure of a memory cell, according to some embodiments described herein. The memory cell510can be any of the memory cells shown inFIG. 2, such as memory cell210for example. The memory cell includes a charge storage transistor T1and a write transistor T2. In the depicted example, the charge storage transistor T1includes a floating gate (FG) structure502as the charge storage structure of the memory cell510. The charge storage transistor T1also includes a control gate. Write transistor T2includes a gate region, a source region and a drain region. The source or drain region of the write transistor T2is directly coupled to the charge storage structure (FG) of the charge storage transistor T1. When the gate of the write transistor is activated it creates a write channel region. Because the source or drain of the write transistor contacts the floating gate of the charge storage transistor, the write channel of T2directly contacts the floating gate of T1.

FIG. 5Ashows a read channel portion551and a separate write channel portion553. The read channel portion is coupled between bit lines of a bit line pair (e.g., BL1and BL1*). The read channel portion551is a two-sided read channel with one side on each side of the floating gate structure502. The read channel portion551is separated from the floating gate structure502by an insulating material552(e.g., silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), etc.). A first channel portion is arranged adjacent to a first surface of the floating gate structure502, and a second channel portion is arranged adjacent to a second surface of the floating gate structure502. The two channel portions are arranged on opposite surfaces of the floating gate structure502. The read channel portion551is contacted by bit line pair521,521* or BL1, BL1*. The bit lines BL1, BL1* extend orthogonal to the plane of the page ofFIG. 5A. Write bit line521is shown contacting the write channel portion553.

FIG. 5Aalso shows access line541, which may be WU inFIG. 2. The access line541is shown overlapping parts of the floating gate structure502, the read channel portion551, and the write channel portion553. The read channel portion551and the access line541are separated from each other by an insulating material. The floating gate502and the access line are separated from each other by an insulating material. The insulating material may be the same or different from the insulating material separating the read channel portion551and the access line541. In some embodiments, the access line541does not overlap the floating gate structure502. The access line541and the floating gate502may include the same material or different materials.

Because the access line overlaps both the write channels and the read channels, the one access line541can be used to activate both the write channel and the read channel of a memory cell. The threshold voltage (Vt) of the write channel portion can be greater than a threshold voltage of the read channel portion. This prevents a read operation using the access line from affecting the charge on the charge storage structure. The difference in Vt can be implemented by including semiconductor material in the write channel portion having a greater bandgap than material included in the read channel portion.

In certain embodiments, the read channel portion includes polysilicon (or poly). The write channel can include material with a higher bandgap than polysilicon. In certain embodiments, the write channel can include gallium phosphide (GaP). In certain embodiments, the write channel can include an oxide semiconductor material, such as one or more of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxlnyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

InFIG. 5A, the bit lines BL1and BL* extend in a direction orthogonal to the page showing the Figure. Thus inFIG. 2, the memory cells210,212, and214of the first column would extend into the page ofFIG. 5A.FIG. 5Bis a cross section view looking toward the access line541. The view shows two memory cells510,512for simplicity. The memory cells may be memory cells210and212inFIG. 2. The dashed area560shows the direction that memory cells of the 3D memory array would be traversed along the same bit line pair (e.g., BL1and BL1*). Additional rows in the same plane as memory cells510and512can be formed to the left and right of the memory cell510inFIG. 5A.

The view inFIG. 5Bshows the read channel551, the write channel553, and an access line. As shown inFIG. 5B, the access line can be a two-sided access line that includes a first access line portion541A arranged adjacent to a first side (e.g., a back side) of the write channel portion553, and a second access line541B portion arranged adjacent to a second side a front side) of the write channel portion553. A shown inFIG. 5B, the second side of the access line can be opposite the first side with the write channel portion553and the floating gate structure between the two portions. The front and back portions of the two-sided access line provide improved control of the charge storage transistor. The front and back portions of the two-sided access line are electrically connected together so that one electrical signal drives both access line portions.

WhileFIGS. 5A and 5Bare used to describe one row of a two-dimensional array of memory cells arranged horizontally, additional memory cells can be formed in the vertical direction to form a three-dimensional (3D) memory array. Multiple decks or levels of cells can be formed in a stack to form the 3D memory array.

FIG. 6Ais an illustration of four 2T memory cells arranged in multiple levels. As in the example ofFIG. 5A, memory cells connected to the same bit line pair (e.g., BL1, BL1*) extend orthogonally in one level in the direction in and out of the page ofFIG. 6A. Therefore, the memory cells inFIG. 6Arepresent a three dimensional memory array.

FIG. 6Bis the view along A-A′ inFIG. 6Alooking toward the access line641. Dashed area660shows the direction that memory cells of the 3D memory array would be traversed along the same bit line pair (e.g., BL1and BL1*). Dashed area662shows the direction that memory cells of the 3D memory array would be traversed along the same access line (e.g., WL1). The example ofFIGS. 6A and 6Bshows two rows and two columns of memory cells for simplicity, but an implementation would include many memory cells in each of the three dimensions.

Each of the 2T memory cells inFIG. 6Aincludes two transistors T1and T2. Memory cells arranged in vertical column of memory cells can be connected to one access line (e.g., access line641or WL1) extending vertically in the 3D memory array. The vertically extending access line is coupled to gates of both the charge storage transistor T1and the write transistor T2of a 2T memory cell in each of multiple respective levels of the column of memory cells. In some embodiments, the charge storage transistor is a floating gate transistor and the access line is coupled to control gates of the floating gate transistors and the write transistors of the 2T memory cells in the multiple respective levels of the multiple vertically arranged levels. The access line is shown overlapping the floating gates. In some embodiments, the access line does not overlap the floating gate. For example, the bottom edge of the access line641can be higher than the top edge of floating gates FG1and FG2.

The vertically extending access line is operable for performing both write operations and read operations of each of the 2T memory cells to which it is coupled. A single bit line pair (e.g., bit line pair BL1, BL1*) is coupled to multiple 2T memory cells in a respective level memory cells. The bit line pair is operable for performing both write operations and read operations of each of the 2T memory cells to which it is coupled.

FIG. 7throughFIG. 12show processes of forming a memory device, according to some embodiments described herein. The memory device includes multiple levels of 2T memory cells. The multiple levels are arranged vertically. As shown inFIG. 7, multiple levels of a sacrificial material774alternated with multiple levels of a dielectric material772are formed vertically on a substrate770. The levels may be layers fabricated by a material deposition process. The dielectric material may include, for example, SiO2. In other examples, multilayer dielectrics may be utilized. The sacrificial material may include, for example, silicon nitride (Si3N4).

InFIG. 8, openings776(e.g., holes) are formed in the multiple levels. The openings can be formed by drilling or etching. The openings expose sides of the levels with the sacrificial material. InFIG. 9, recesses are formed in the multiple levels of sacrificial material774. The recesses can be formed using an isotropic etch process that essentially removes only the sacrificial material and selective to the dielectric material752. As shown inFIG. 9, the resulting structure includes openings in the multiple levels of dielectric material752and multiple levels of recesses in the levels of sacrificial material774.

FIG. 10is an illustration of a portion ofFIG. 9showing opening756and multiple levels of recesses778. Multiple layer or films can be deposited in the recesses to form multiple levels of read channel regions, write channel regions, and charge storage structures for multiple levels of write transistors and charge storage transistors of the multiple levels of the 2T memory cells.

InFIG. 11, a layer or film of polysilicon is formed in the recesses to form a read channel portion751for the charge storage transistors. As shown in the embodiment ofFIG. 11, polysilicon film is disposed on two sides of a recess to form a two-sided channel region of a charge storage transistor. A layer or film of dielectric material772is formed over the polysilicon of the read channel portions. The dielectric material may be the same as the dielectric material of the multiple dielectric levels (e.g., SiO2) or may be a different dielectric material. A gate oxide is disposed in the recesses to form a charge storage structure702of the charge storage transistors. The dielectric material772isolates the charge storage structure702from the read channel portion751. In certain embodiments, the charge storage structure702is a floating gate structure of a floating gate transistor. In the embodiment ofFIG. 11, the gate oxide is disposed between sides of the two-sided read channel portion751of the charge storage transistor. The dielectric material772isolates the floating gate structure from other conductive elements of the floating gate transistor.

A semiconductor material is formed in the recesses to form a write channel portion753for the write transistors of the 2T memory cells. The semiconductor material has a higher bandgap than the polysilicon of the read channel portion751. In certain embodiments, the semiconductor material of the write channel portion753includes n-type GaP. In certain embodiments, the write channel portion751includes an oxide semiconductor material. The write channel region of the write transistors is formed to contact the charge storage structure702.

Vertical openings are again formed in the multiple levels. The vertical openings are formed in the multiple levels of the dielectric material and the multiple levels of the channel regions. The layers or films of the read channel portions and the write channel portions may be etched back to prepare space for the bit lines formed later. The openings and etched areas are filled with sacrificial material774. The sacrificial material may be the same or different from the sacrificial material of the multiple levels of sacrificial material.

When the read and write channels are formed, processing continues in a different direction than the one shown inFIG. 11to form the gates of the write transistors and the control gates of the charge storage transistors. The multiple levels of channel regions are chopped drilled or etched) to isolate the individual read channel portions and write channel portions of the multiple levels. Gate oxide is deposited to form the gate regions of the write transistors and charge storage transistors. Openings (e.g., holes) are formed (e.g., by etching) for the access lines to contact the gate regions. The openings may be filled with conductive material (e.g., metal) to form the access lines. The access lines extend vertically in the multiple levels. A single access line (e.g., WL1inFIG. 2) is formed to contact multiple memory cells in a column of memory cells. The same single access line contacts the gate region of a write transistor and the control gate region of a charge storage transistor of a 2T memory cell of a first level of the memory cells, and contacts the gate region of a write transistor and the control gate region of a charge storage transistor of a 2T memory cell of a second level of the memory cells. The access lines may be two-sided access lines, with gate regions for the write transistors and control gate regions for the charge storage transistors on two sides of a 2T memory cell.

A shown inFIG. 12, the sacrificial material774orFIG. 11is removed. The vertical opening is filled with conductive material to form one of the bit lines of the bit line pairs. At this point the bit lines may be shorted together by the conductive material. The formed bit lines are separated (e.g., by etching the conductive material), and the separation or opening is filled with a dielectric, such as an insulating oxide (e.g., SiO2) to electrically isolate the formed bit lines.FIG. 12shows formed bit lines BL1, BL2, BL3, and BL4. The bit lines extend in a direction orthogonal to the page showingFIG. 12, and contact one end of the read channel portion751of the memory cells.

The multiple levels of channel regions are again chopped (e.g., drilled or etched) to expose the opposite ends of the read channel portions751. Conductive material is disposed in the opening to contact the opposite ends of the read channel portions. The conductive material may again be separated and the separation or opening filled with the insulating oxide to form the second bit line of the bit line pairs (e.g., bit lines BL1*, BL2*, BL3*, and BL4*).

The illustrations of apparatuses (e.g., memory devices100and200) and methods (e.g., operations of memory devices100and200) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device or a system that can include memory devices100and200.

Any of the components described above with reference toFIG. 1throughFIG. 4can be implemented in a number of ways, including simulation via software. Thus, apparatuses, e.g., memory devices100and200, or part of each of these memory devices described above, may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single- and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired and/or as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

Memory devices100and200may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference toFIG. 1throughFIG. 12include apparatuses and methods of forming the apparatuses. One of the apparatuses includes memory device200. Other embodiments including additional apparatuses and methods are described.

Additional Description and Examples

Example 1 is an apparatus comprising: multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate, wherein each 2T memory cell includes: a charge storage transistor and a write transistor, wherein a source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor; a vertically extending access line disposed to gate both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels, wherein the vertically extending access line is operable for performing both write operations and read operations of each of the 2T memory cells to which it is coupled; and a single bit line pair coupled to multiple 2T memory cells in a respective level, and operable for performing both write operations and read operations of each of the 2T memory cells to which it is coupled.

In Example 2, the subject matter of Example 1, wherein the write transistor includes a write channel portion and the charge storage transistor includes a read channel portion separate from the write channel portion, the read channel portion coupled between bit lines of the single bit line pair; and wherein a threshold voltage of the write channel portion is greater than a threshold voltage of the read channel portion.

In Example 3, the subject matter of Example 2 optionally includes a vertically extending access line that overlaps both the write channel portion and the separate read channel portion of each of the 2T memory cells to which it is coupled.

In Example 4, the subject matter of any of Examples 2-3, wherein a bandgap of semiconductor material included in the write channel portion is greater than a bandgap of semiconductor material included in the read channel portion.

In Example 5, the subject matter of any of Examples 2-4, wherein the read channel portion comprises two channel sides including a first channel portion arranged adjacent to a first surface of the charge storage structure and a second channel portion arranged adjacent to a second surface of the charge storage structure, and wherein the second surface is on an opposite side of the charge storage structure from the first surface.

In Example 6, the subject matter of any of Examples 1-5T memory cell is a floating gate transistor and the charge storage structure is a floating gate structure of the floating gate transistor.

In Example 7, the subject matter of Example 6T memory cells in multiple respective levels of the multiple vertically arranged levels.

Example 8 is a method of forming multiple levels of two-transistor (2T) memory cells, the method comprising: forming, vertically on a substrate, multiple levels of a sacrificial material alternated with multiple levels of a dielectric material; forming first openings in the multiple levels of the dielectric material and forming multiple levels of recesses in the multiple levels of the sacrificial material; forming multiple levels of channel regions for write transistors and charge storage transistors of the 2T memory cells, wherein a channel region of a write transistor contacts a charge storage structure of a charge storage transistor in each 2T memory cell; forming second vertical openings in the multiple levels of the dielectric material and the multiple levels of the channel regions, and filling the second vertical openings with the sacrificial material; forming gate regions of the write transistors and the charge storage transistors of the 2T memory cells; forming multiple vertically extending access lines, each access line to control gate regions of both a charge storage transistor and a write transistor of a 2T memory cell in multiple respective levels of the 2T memory cells; and removing the sacrificial material and forming bit line pairs for the 2T memory cells using the second vertical openings, wherein only one bit line pair contacts one 2T memory cell.

In Example 9, the subject matter of Example 8, wherein the forming multiple levels of channel regions includes disposing a polysilicon film on two sides of a recess to form a two-sided read channel region of a charge storage transistor.

In Example 10, the subject matter of Example 9T memory cells includes disposing gate oxide between sides of the two-sided read channel region of the charge storage transistor.

In Example 11, the subject matter of Example 10, wherein the forming multiple levels of channel regions includes disposing gallium phosphide between the sides of the two-sided channel region of the charge storage transistor and in contact with the charge storage structure to form a write channel region of a write transistor.

In Example 12, the subject matter of any of Examples 9-11T memory cells includes: removing the sacrificial material from a second vertical opening to expose a first end of the two-sided channel region; disposing a conductive material in the second vertical opening to form a first bit line of a bit line pair of a 2T memory cell, wherein the first bit line contacts the first end of the two-sided channel region; forming an opening to expose a second end of the two-sided channel region; and disposing the conductive material to form the second bit line of the bit line pair of the 2T memory cell, wherein the second bit line contacts the second end of the two-sided channel region.

In Example 13, the subject matter of any of Examples 8-12T memory cells includes: filling the second vertical openings with a conductive material to form first bit lines of the bit line pairs; etching the conductive material to separate the formed first bit lines; and filling the opening with an insulating oxide to electrically isolate the formed first bit lines.

In Example 14, the subject matter of any of Examples 8-13, including forming multiple levels of floating gate structures for the charge storage transistors, and wherein the forming gate regions of the charge storage transistors includes disposing gate oxide to form control gate regions of the charge storage transistors.

In Example 15, the subject matter of Example 14 includes forming, for a same single access line, contacts to a gate region of a write transistor and a control gate region of a charge storage transistor of a 2T memory cell.

In Example 16, the subject matter of any of Examples 8-15 includes forming contacts for a single vertically extending access line to gate regions of a write transistor and a gate region of a charge storage transistor of a 2T memory cell of a first level of the 2T memory cells, and to gate regions of a write transistor and a charge storage transistor of a 2T memory cell of a second level of the 2T memory cells.

Example 17 is a method of operating a memory array having multiple levels of two-transistor (2T) memory cells vertically arranged, the method comprising: applying, during a write operation, a first write voltage to a target 2T memory cell of a first level of the memory array using a single vertically extending access line; and applying, during a read operation, a first read voltage to the target 2T memory cell using the same single vertically extending access line used in the write operation; wherein the same single vertically extending access line contacts the target 2T memory cell and contacts a first non-target 2T memory cell of a second level of the memory array.

In Example 18, the subject matter of Example 17, including: applying, during the write operation, a second write voltage to both bit lines of a single bit line pair of the target 2T memory cell, wherein the first write voltage and the second write voltage are greater than zero volts; and applying zero volts to both bit lines of a single bit line pair of the non-target 2T memory cell.

In Example 19, the subject matter of Example 18, including: applying, during the read operation, a second read voltage to a single bit line of the single bit line pair of the target 2T memory cell, wherein the second read voltage is greater than zero volts; and applying zero volts to the other bit line of the single bit line pair of the target 2T memory cell and both bit lines of the single bit line pair of the non-target 2T memory cell during the read operation.

In Example 20, the subject matter of any of Examples 18-19, including applying, during the write operation and the read operation, an isolation voltage to unselected access lines of the memory array, wherein the isolation voltage is less than zero volts.

In Example 21, the methods of any one or any combination of Examples 8-15 may be performed to form a structure in accordance with one or any combination of Examples 1-7.

In Example 22, the method of operating a memory array of one or any combination of Examples 17-20 may be performed using the apparatus of one or any combination of Examples 1-7.

In Example 23, the subject matter of one or any combination of Examples 1-15 optionally includes a charge storage transistor that includes a charge trap storage structure.

In Example 24, the multiple levels of two-transistor (2T) memory cells of one or any combination of Examples 1-22 optionally includes multiple vertically arranged tiers of memory devices.

These non-limiting Examples can be combined in any permutation or combination.

In the detailed description and the claims, a list of items joined by the term “at least one of” means any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only; B only; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

In the detailed description and the claims, a list of items joined by the term “one of” means only one of the list items. For example, if items A and B are listed, then the phrase “one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase “one of A, B and C” means A only; B only; or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements. The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.