Semiconductor device

According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-061083, filed on Mar. 22, 2013; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A through via (through silicon via, TSV) is introduced as a technology whereby a plurality of semiconductor chips can be mounded at high density. In the case where the semiconductor is silicon (Si), the through via is a conductive layer penetrating from the back surface to the front surface of the silicon substrate, for example. Each of a plurality of semiconductor chips is electrically connected via the through via to mount the plurality of semiconductor chips at high density; thereby, high-speed data transfer is enabled.

The TSV technology is expected to be applied to a semiconductor device such as a NAND flash memory. In such a semiconductor device, a relatively high power supply potential is used in the write and erase operations. Therefore, if the TSV technology is applied to the semiconductor device, a high power supply is supplied also to the through via as a matter of course, and it is feared that a potential difference with an element will occur to cause a yield reduction due to the unstable operation and operational dysfunction of the element. Furthermore, it has been necessary to set a sufficient distance between the through via and the element in order to prevent a yield reduction due to the unstable operation and operational dysfunction of the element, and this has been leading to an increase in the area of the semiconductor chip. For such a semiconductor device, a structure is desired that avoids a yield reduction due to the unstable operation and operational dysfunction of the element caused when a high power supply is supplied also to the through via, and prevents an increase in the chip area of the semiconductor device electrically connected by the through via.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first surface and a second surface on an opposite side to the first surface; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

Hereinbelow, embodiments are described with reference to the drawings. In the following description, identical components are marked with the same reference numerals, and a description of components once described is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross-sectional view showing a semiconductor device according to a first embodiment.

FIG. 2is a schematic plan view showing the semiconductor device according to the first embodiment.

FIG. 1shows a cross section in the position along line A-A′ ofFIG. 2.FIG. 2shows a cross section in the position along line B-B′ ofFIG. 1.

A semiconductor device1according to the first embodiment is part of a NAND flash memory device, as an example. The semiconductor device1includes a semiconductor layer10, a conductive layer20(a first conductive layer), a semiconductor region30(a first semiconductor region), and an insulating film40(a first insulating film).

The semiconductor layer10is a p-type semiconductor layer. The semiconductor layer10has a back surface10rs(a first surface) and a front surface10ss(a second surface) on the opposite side to the back surface10rs. The semiconductor layer10is a semiconductor layer formed by processing and thinning a semiconductor substrate such as a semiconductor wafer, for example. The thickness in the Z direction of the semiconductor layer10is 20 μm to 50 μm, for example.

The conductive layer20penetrates from the back surface10rsside to the front surface10ssside of the semiconductor layer10. That is, the conductive layer20is a through via (TSV). In the semiconductor device1, at least one conductive layer20is provided. Thus, the number of conductive layers20is not limited to the number illustrated. The number of conductive layers20may be one or plural. That is, another conductive layer20penetrating from the back surface10rsside to the front surface10ssside of the semiconductor layer10may be provided. In the first embodiment, a region where at least one conductive layer20is provided is referred to as a first region1a.

The conductive layer20has a conductive region20aand a conductive region20b. The conductive region20ais the main body of the conductive layer20. The conductive region20bis a barrier layer that suppresses the diffusion of components of the conductive region20ato the semiconductor layer10and the semiconductor region30. Alternatively, the conductive region20bfunctions as an adhesion layer that increases the adhesion between the conductive region20aand the insulating film40provided on the outside of the conductive region20a. The planar shape of the conductive layer20is not limited to a circle but may be a rectangle or a polygon. The conductive layer20is connected to an electrode pad21.

The semiconductor region30is a p-type semiconductor region. The conductivity type of the semiconductor layer10and the conductivity type of the semiconductor region30are the same. The semiconductor region30surrounds part (for example, an upper portion) of the conductive layer20on the front surface10ssside of the semiconductor layer10. In the semiconductor region30, portions other than the front surface of the semiconductor region30(for example, a lower portion and a side portion of the semiconductor region30) are surrounded by the semiconductor layer10. In the first embodiment, a region where the semiconductor region30is provided is referred to as a second region1b. The planar shape of the semiconductor region30is not limited to a quadrangle but may be a rectangle or a polygon. The semiconductor region30may be referred to as a well region.

The concentration of the p-type impurity element contained in the semiconductor region30is higher than the concentration of the p-type impurity element contained in the semiconductor layer10. In the case where the semiconductor device1is part of a NAND flash memory device, the impurity concentration of the semiconductor layer10is set lower than the impurity concentration of a semiconductor substrate forming an ordinary CMOS or the like.

As the background of this, since a relatively high potential (approximately 25 (V)) is used for the write and erase operations of memory cells, a boost circuit is needed that produces a relatively high potential required for the write and erase operations, and a transistor with a very small back bias effect is needed as an element forming the boost circuit. It is common knowledge that in order to reduce the back bias effect of a transistor, the semiconductor substrate needs to have a very low impurity concentration; and the impurity concentration of the semiconductor layer10is 1×1014(atoms/cm3), for example. The impurity concentration of the semiconductor region30is 2×1017(atoms/cm3), for example.

Here, the “impurity concentration” refers to the effective concentration of the impurity element contributing to the electrical conductivity of the semiconductor material. For example, in the case where an impurity element serving as a donor and an impurity element serving as an acceptor are contained in the semiconductor material, the concentration of the activated impurity element excluding the amount of offset between donors and acceptors is taken as the impurity concentration.

The insulating film40is provided between the conductive layer20and the semiconductor layer10and between the conductive layer20and the semiconductor region30. The insulating film40is further provided under the back surface10rsof the semiconductor layer10.

The semiconductor device1further includes an element50provided on the semiconductor layer10and an electrode60provided on the front surface10ssof the semiconductor layer10. An insulating film51(a second insulating film) is provided on the semiconductor layer10and on the semiconductor region30.

The element50is provided on the outside of the second region1bwhere the semiconductor region30is disposed. The element50is a MOSFET. The element50uses the semiconductor layer10as a base region, and includes an n+-type (second conductivity type) source region50s, an n+-type drain region50dapart from the source region50s, and a gate electrode50g. The insulating film51provided between the semiconductor layer10and the gate electrode50gis a gate insulating film. In the case where the semiconductor device1is part of a NAND flash memory device, the element50corresponds to a transistor that transfers an electric potential to the word line of a memory cell, for example.

In the semiconductor device1, in addition to the element50, for example, an active element such as a diode, a passive element such as a resistance and a capacitor, or a memory element, an interconnection, etc. are provided on the front surface10ssside of the semiconductor layer10(not shown).

The electrode60is connected to the conductive layer20. The electrode60is connected to an electrode61via a contact70. The electrode61is connected to an electrode62avia a contact71. The electrode62ais connected to an electrode63via a contact72. The electrode63is connected to an electrode pad66via a contact73. The electrode63is connected to an electrode62bvia a contact74. The electrodes60to63and the contacts70to74are provided in an interlayer insulating film80. The electrode pad66is exposed from the interlayer insulating film80.

Although not illustrated, in addition to these, multiple interconnections are provided in a lower portion of the interlayer insulating film80. A contact electrode is connected to each of the source region50s, the drain region50d, and the gate electrode50gof the element50.

In the semiconductor device1, an insulating layer90is provided between part (for example, an upper portion) of the conductive layer20and the semiconductor region30. When the semiconductor device1is viewed from the Z direction, the insulating layer90surrounds part of the conductive layer20. An insulating layer91is provided between the semiconductor region30and the semiconductor layer10. When the semiconductor device1is viewed from the Z direction, the insulating layer91surrounds the semiconductor region30. The element50is partitioned from a region other than the element50by the insulating layer91.

The semiconductor layer10and the semiconductor region30contain a silicon crystal doped with an impurity element such as boron (B), for example. The source region50sand the drain region50dcontain a silicon crystal doped with an impurity element such as phosphorus (P) and arsenic (As), for example. The gate electrode50gcontains polysilicon doped with an impurity element, tungsten, or the like.

The conductive region20acontains at least one of copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), tin (Sn), polysilicon, and the like, for example. The conductive region20amay be a stacked body in which at least one of copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), tin (Sn), polysilicon, and the like is stacked, for example. The conductive region20bcontains at least one of titanium (Ti), titanium nitride (TiN), and the like. The conductive region20bmay be a stacked body in which at least one of titanium (Ti), titanium nitride (TiN), and the like is stacked.

The electrode pad21contains at least one of copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), tin (Sn), polysilicon, and the like, for example. The electrode pad21may be a stacked body in which at least one of copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), tin (Sn), polysilicon, and the like is stacked, for example.

The electrodes60to63, the electrode pad66, and the contacts70to74contain at least one of aluminum (Al), copper (Cu), tungsten (W), and polysilicon. The electrodes60to63, the electrode pad66, and the contacts70to74may be a stacked body in which at least one of aluminum (Al), copper (Cu), tungsten (W), polysilicon, and the like is stacked.

The insulating films40and51, the insulating layers90and91, and the interlayer insulating film80contain at least one of silicon oxide (SiO2), silicon nitride (Si3N4), and the like, for example.

Before the operation of the semiconductor device1is described, a semiconductor device according to a reference example is described.

FIG. 3is a schematic cross-sectional view showing a semiconductor device according to a reference example.

The basic structure of a semiconductor device100according to the reference example is the same as the basic structure of the semiconductor device1. However, in the semiconductor device100, the semiconductor region30described above is not provided.

In the case where the semiconductor device100is a NAND flash memory device, a high voltage of approximately 25 V, for example, is needed in the cell write and erase operations, and there is a case where a voltage of several tens of volts (e.g. approximately 30 V) is applied to the conductive layer20as a matter of course. In this case, a depletion layer is formed in a large area on the semiconductor layer10side so as to surround the conductive layer20. The way in which the depletion layer extends is shown by arrow10dp.

The depletion layer generally tends to extend longer as the impurity concentration becomes lower. In the embodiment, the extension of the depletion layer is schematically expressed by (10dp).

As described above, in regard to the semiconductor layer10, since a transistor with a very small back bias effect is needed as an element formed on the same substrate, a semiconductor substrate with a very low impurity concentration is required in order to make the back bias effect of the transistor small.

Therefore, when a voltage of several tens of volts (e.g. approximately 30 V) is applied, a depletion layer10dpis formed in a large area on the semiconductor layer10side so as to surround the conductive layer20, and in the worst case may reach the element50adjacent to the conductive layer20.

In such a state, the operation of the element50becomes unstable, or rather the element50becomes inoperative and does not normally function as a NAND flash memory device.

As a method for avoiding such a phenomenon, there is a method that makes the distance between the conductive layer20and the element50longer. However, if this method is employed, an increase in the size of the semiconductor device is caused. In addition, from the necessity of making the distance between the conductive layer20and the element50a prescribed length or more, the flexibility of arrangement of the conductive layer20, the element50, and other portions is reduced.

FIG. 4is a schematic cross-sectional view showing the operation of the semiconductor device according to the first embodiment.

As compared to the reference example, the semiconductor device1includes the semiconductor region30. The impurity concentration of the semiconductor region30is higher than the impurity concentration of the semiconductor layer10. Therefore, the extension of the depletion layer10dpin the semiconductor layer10is suppressed by the semiconductor region30. Consequently, the extension of the depletion layer10dpin the semiconductor layer10in the semiconductor device1is suppressed as compared to the reference example. For example,FIG. 4shows a state where the formation of the depletion layer10dpin the semiconductor layer10is sufficiently suppressed in the semiconductor region30, and the depletion layer10dpexists only in a position sufficiently distant from the element50adjacent to the conductive layer20.

Therefore, when a voltage of several tens of volts (e.g. approximately 30 V) is applied to the conductive layer20, the depletion layer extending to the semiconductor layer10side is formed in a limited space. Thereby, the depletion layer10dpdoes not extend to such a level as to affect the element50adjacent to the conductive layer20, and the operation of the element50is stabilized and the element50does not become inoperative. Consequently, a yield reduction due to the unstable operation and operational dysfunction of the element can be prevented. Furthermore, in the semiconductor device1, it is not necessary to make the distance between the conductive layer20and the element50long. Thereby, the size of the semiconductor device1is not increased. Furthermore, in the semiconductor device1, the flexibility of arrangement of the conductive layer20, the element50, and other portions is increased.

Thus, the increase in the chip area of the semiconductor device electrically connected by the through via is minimized, and thereby a semiconductor device that is inexpensive due to high yield and the reduction in the semiconductor chip area can be manufactured.

Second Embodiment

FIG. 5is a schematic cross-sectional view showing a semiconductor device according to a second embodiment.

FIG. 6is a schematic plan view showing the semiconductor device according to the second embodiment.

FIG. 5shows a cross section in the position along line A-A′ ofFIG. 6.FIG. 6shows a cross section in the position along line B-B′ ofFIG. 5.

The basic structure of a semiconductor device2according to the second embodiment is the same as the basic structure of the semiconductor device1. The semiconductor device2further includes a conductive layer55(a second conductive layer). The conductive layer55is provided on the semiconductor region30via the insulating film51. As viewed from the Z direction, the conductive layer55surrounds the first region is where at least one conductive layer20is provided. The conductive layer55contains polysilicon doped with an impurity element, tungsten, or the like.

In the semiconductor device2, the conductive layer55may be grounded, or a prescribed potential may be applied to the conductive layer55. Alternatively, the electric potential of the conductive layer55may be set to a floating potential. In the semiconductor device2, by the conductive layer20being surrounded by the conductive layer55, the electric potential of the conductive layer20is shielded by the conductive layer55. Therefore, the depletion layer10dpformed on the element50side due to the electric potential of the conductive layer20is suppressed to a more limited one.

Thereby, in the semiconductor device2, the depletion layer extending to the semiconductor layer10side is formed in a more limited space than in the semiconductor device1, and this leads to stable operation of the semiconductor device. Furthermore, in the semiconductor device2, the distance between the conductive layer20and the element50can be set still shorter, and therefore the device size is further reduced. Furthermore, in the semiconductor device2, the flexibility of arrangement of the conductive layer20, the element50, and other portions is further increased. Thereby, the chip area of the semiconductor device electrically connected by the through via can be made still smaller, and a semiconductor device that is inexpensive due to high yield and the reduction in the semiconductor chip area can be manufactured.

The conductive layer55is located at the same height as the memory cell transistor. Hence, the conductive layer55can be formed along with the memory cell transistor in the process of forming the memory cell transistor. Therefore, even when the conductive layer55is provided, a cost increase of the manufacturing process does not occur.

Third Embodiment

FIG. 7is a schematic cross-sectional view showing a semiconductor device according to a third embodiment.

FIG. 8is a schematic plan view showing the semiconductor device according to the third embodiment.

FIG. 7shows a cross section in the position along line A-A′ ofFIG. 8.FIG. 8shows a cross section in the position along line B-B′ ofFIG. 7.

The basic structure of a semiconductor device3according to the third embodiment is the same as the basic structure of the semiconductor device1. The semiconductor device3further includes a p+-type semiconductor region56(a second semiconductor region). The semiconductor region56contains a silicon crystal doped with an impurity element such as boron (B), for example.

The semiconductor region56is provided on the semiconductor region10. The impurity concentration of the semiconductor region56is higher than the impurity concentration of the semiconductor region30. The semiconductor region56is a conductive region.

The semiconductor region56surrounds the first region1aand the second region1bwhere the semiconductor region30is provided. In the semiconductor device3, the element50provided on the semiconductor layer10is provided on the outside of the semiconductor region56surrounding the first region1aand the second region1b.

In the semiconductor device3, the semiconductor region56may be grounded, or a prescribed potential may be applied to the semiconductor region56. In the semiconductor device3, by the conductive layer20being surrounded by the conductive layer55and the semiconductor region56, the electric potential of the conductive layer20is shielded by the conductive layer55and the semiconductor region56. Therefore, the depletion layer10dpformed on the element50side due to the electric potential of the conductive layer20is suppressed to a more limited one.

Thereby, in the semiconductor device3, when a voltage of several tens of volts (e.g. approximately 30 V) is applied to the conductive layer20, the depletion layer extending to the semiconductor layer10side is formed in a limited space. Thereby, the depletion layer10dpdoes not extend to such a level as to affect the element50adjacent to the conductive layer20, and the operation of the element50is stabilized and the element50does not become inoperative. Furthermore, in the semiconductor device3, the distance between the conductive layer20and the element50can be set still shorter, and therefore the device size is further reduced. Furthermore, in the semiconductor device3, the flexibility of arrangement of the conductive layer20, the element50, and other portions is further increased. Thereby, the chip area of the semiconductor device electrically connected by the through via can be made still smaller, and a semiconductor device that is inexpensive due to high yield and the reduction in the semiconductor chip area can be manufactured.

Fourth Embodiment

FIG. 9is a schematic cross-sectional view showing a semiconductor device according to a fourth embodiment.

In a semiconductor device4, the semiconductor region is provided between the conductive layer20and the semiconductor layer10. In the case where the semiconductor region30is disposed so as to surround the entire conductive layer20like the semiconductor device4, the depletion layer extending from the conductive layer20is kept in a more limited region. Therefore, the depletion layer10dpformed on the element50side due to the electric potential of the conductive layer20is suppressed to a more limited one.

In the embodiment, the p type is taken as the first conductivity type and the n type is taken as the second conductivity type. Also structures in which the p type and the n type are exchanged to take the n type as the first conductivity type and the p type as the second conductivity type are included in the embodiment.

The term “on” in “a portion A is provided on a portion B” refers to the case where the portion A is provided on the portion B such that the portion A is in contact with the portion B and the case where the portion A is provided above the portion B such that the portion A is not in contact with the portion B.

The embodiments have been described above with reference to examples. However, the embodiments are not limited to these examples. More specifically, these examples can be appropriately modified in design by those skilled in the art. Such modifications are also encompassed within the scope of the embodiments as long as they include the features of the embodiments. The components included in the above examples and the layout, material, condition, shape, size and the like thereof are not limited to those illustrated, but can be appropriately modified.

Furthermore, the components included in the above embodiments can be combined as long as technically feasible. Such combinations are also encompassed within the scope of the embodiments as long as they include the features of the embodiments. In addition, those skilled in the art could conceive various modifications and variations within the spirit of the embodiments. It is understood that such modifications and variations are also encompassed within the scope of the embodiments.