Structure and method for back end of the line integration

An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.

BACKGROUND

The invention relates generally to a semiconductor structure and a method of fabrication thereof, and more particularly to integrating an interconnect in an upper interconnect level with an interconnect in a lower interconnect level to provide good electrical and mechanical contact between the upper and lower level interconnects.

Good electrical and mechanical contact between the upper and lower level interconnects is required to insure overall interconnect reliability. With each generation, more devices and circuits are squeezed onto a semiconductor chip. Consequently, the lines and vias formed in the semiconductor chips have become ever thinner. A major problem with the thinning metal lines and vias resides in the integration of thin vias in an upper interconnect level with lines in a lower interconnect level. More specifically, as the vias become thinner, the mechanical integrity of those vias worsens particularly for deep submicron vias embedded in low-k dielectric materials at the contact area with underlying interconnects. Porous low-k dielectric material only exasperates the problem because a bigger thermal coefficient mismatch between the lower-k dielectrics and metal interconnect is expected than with higher-k dielectrics.

U.S. Patent Publication No. 2007/0205482 depicts a prior art structure for integrating interconnects in an upper interconnect level with interconnects in a lower interconnect level in which a “via punch through,” also known as a “via gouging” process is used to create a via with improved mechanical and electrical integrity. The via has an anchoring area, also known as a gouged via feature, that achieves reasonable contact resistance as well as increases the mechanical strength of the via. The improved contact resistance and mechanical strength improves integration of the interconnect with interconnects in a lower interconnect level. The reason for the improved integration is that the gouged via increases the contact area of the interconnect with the interconnect in the lower interconnect level.

BRIEF SUMMARY

A first embodiment of the invention is directed a method of fabricating a semiconductor structure. The method includes the step of providing an interconnect structure that includes a lower interconnect level comprising a first dielectric layer having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric having at least one via opening that exposes a portion of the at least one conductive feature located atop the lower interconnect level, the lower and upper interconnect levels are partially separated by a dielectric capping layer, and a patterned hard mask on a surface of the upper interconnect level. The method includes the step of forming a first barrier layer on all exposed surfaces of the via opening. The method includes the step of removing the first barrier layer at a bottom of the via opening and on the patterned hard mask while maintaining the first barrier layer on remaining sidewall surfaces of the via opening. The method includes the step of forming a conductive protrusion in the at least one conductive feature, the conductive protrusion located at a bottom of the via opening and extends upward from bottom of the via opening and into the at least one via opening. The method includes the step of forming a seed layer within the at least one via opening. The method includes the step of filling the at least one via opening with a conductive material.

A second embodiment of the invention is directed to a semiconductor structure. The structure includes a lower interconnect level comprising a first dielectric layer having at least one conductive feature embedded therein. The structure includes a dielectric capping layer located on the first dielectric layer and at least a portion of the conductive feature. The structure includes an upper interconnect level comprising a second dielectric having at least one conductively filled via wherein the conductively filled via is in contact with an exposed portion of the at least one conductive feature of the first interconnect level by a conductive protrusion located at a bottom of the via that extends upward from bottom of the via and into the via. The conductively filled via is separated from the second dielectric in the upper interconnect level by a first barrier layer.

DETAILED DESCRIPTION

The invention will now be described with reference to the accompanying figures. In the figures, various aspects of the structures have been depicted and schematically represented in a simplified manner to more clearly describe and illustrate the invention.

By way of overview and introduction, the embodiments of the invention are directed to a semiconductor integration structure and method. More specifically, a conductive feature in a lower interconnect level is connected to a conductive feature in an upper interconnect level by a conductive protrusion that extends from the bottom of a via opening and up into the via opening in an upper interconnect level. The conductive protrusion increases the mechanical strength of the via, and thereby ensures a reliable electrical contact. The conductive protrusion has increased contact area with the underlying interconnect, and therefore the mechanical strength of the via is improved.

The invention will be described with reference toFIG. 1, which depicts an embodiment of the invention andFIGS. 2a-2g, which depict the formation of the embodiment inFIG. 1.

With reference toFIG. 1, there is shown an embodiment of the invention. As depicted, the lower interconnect level includes at least one conductive feature106embedded in dielectric layer102. The conductive feature includes a conductive protrusion114that integrates conductive feature106in the lower interconnect level with the via in the upper interconnect level. Dielectric capping layer108separates the lower and upper interconnect levels. The via depicted inFIG. 1has two barrier layers112,116, however as described herein the second barrier layer116is an optional layer in an embodiment of the invention. Finally, the via depicted inFIG. 1includes a seed layer118and conductive material fill120.

FIG. 2adepicts the first step of the method of an embodiment of the invention. More specifically,FIG. 2adepicts a lower interconnect level124separated from an upper interconnect level126by a dielectric capping layer108. The dielectric capping layer108is preferably made of Si3N4, SiC, Si4NH3, SiO2, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H), or multilayers formed by any combination of these materials. The purpose of the dielectric capping layer108is to act as an etching stop layer for the next level build.

The lower interconnect level124ofFIG. 2aincludes as least one conductive feature106embedded in a dielectric layer102. The conductive feature106comprises Cu, Al, Al(Cu), W or alloys of these materials. The dielectric layer102is preferably made of any of the following materials SiO2, Si3N4, SiCOH, SiLK®, dense dielectric material with a dielectric constant of about 2.5 or more, or porous ultra low-k dielectric material with a dielectric constant of 2.5 or less.

The upper interconnect level126ofFIG. 2aincludes a via opening122formed in dielectric layer104that exposes a portion of a conductive feature106in the lower interconnect level124. The dielectric layer104is made of any of the following materials SiO2, Si3N4, SiCOH, SiLK®, dense dielectric material with a dielectric constant of about 2.5 or more, or porous ultra low-k dielectric material with a dielectric constant of 2.5 or less. Note that while a single damascene structure, e.g. single via opening122, is depicted inFIG. 2a, one skilled in the art would appreciate that the invention is not limited to a single damascene structure but includes dual damascene structures, e.g. a line and via opening, as well. The via opening122is formed through the use of a hard mask110that has via patterns and transferring those via patterns to dielectric material104below the hard mask110. The hard mask110consists of the following types of materials SiO2, Si3N4, SiC, SiC(N), Ta(N), Ti(N), or W(N).

FIG. 2bdepicts forming a barrier layer112on the exposed portions of the via opening122inFIG. 2a. The barrier layer112is conformally deposited on all exposed surfaces of the via opening122. The barrier layer112prevents diffusion of conductive material into the surrounding dielectric104. The barrier layer112consists of depositing one of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or Co and has a thickness in the range of 10 A to 200 A.

FIG. 2cdepicts removal of the deposited barrier layer112inFIG. 2b. The barrier layer112is removed by a directional gaseous sputtering. Any of the following materials could be used for the gaseous sputtering Ar, He, Ne, Xe, N2, H2, NH3, N2H2or mixtures of any of these materials. As shown inFIG. 2c, the directional gaseous sputtering only removes the barrier layer112on the bottom of the via opening122and on the field area while maintaining the barrier layer112on the sides of the via opening122. The gaseous sputtering further does not remove a significant amount of the conductive fill in the underlying conductive feature106. That is, a gouged feature is not formed in the underlying interconnect from this sputtering process.

FIG. 2ddepicts the formation of a conductive protrusion114in the conductive feature106. The conductive protrusion114is placed at the bottom of the via opening122and extends upward from the bottom of the via opening122and into the via opening122. The conductive protrusion114has a pyramid shape with a height between 5 A and 500 A. The conductive protrusion114is formed by PVD, CVD, ALD, electro plating, electroless plating, or combinations of any of these techniques. The conductive protrusion114is preferably made of Cu, Ru Ir, Co, Rh, Ta, W, Ti, Pt or alloys made of any of these materials. Either a directional PVD deposition or selective deposition from CVD, ALD, electro plating, electroless plating can create the conductive protrusion114at bottom of the via as shown inFIG. 2d. For selective deposition from CVD, ALD, electro plating and electroless plating methods, the conductive protrusion material initially nucleates at the via bottom and on the underlying interconnect surface, and then grows/extends upward.

FIG. 2edepicts an optional additional step in the formation of an embodiment of the invention. More specifically,FIG. 2edepicts forming a second barrier layer116over the first barrier layer112that exists on the sides of the via opening122, and over the conductive protrusion114formed inFIG. 2d. The second barrier layer116has a thickness in the range of between 20 A and 200 A. Similar to the first barrier layer112, the second barrier layer116consists of depositing one of the following materials Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or Co on top of the first barrier layer112that exists on the sides of the via opening122and the conductive protrusion114. While the second barrier layer116could be formed over the sides of the via opening122and conductive protrusion114, the second barrier layer116is not a required element of the invention. The purpose of the second barrier layer116is to behave as a diffusion barrier or an adhesion layer.

FIG. 2fdepicts the forming an adhesion/plating seed layer118either over a second barrier layer116, if the optional second barrier layer116ofFIG. 2eis formed, or over the first barrier layer112that exists on the sides of the via opening122and the conductive protrusion114, if the optional second barrier layer116ofFIG. 2eis not formed. The adhesion/plating seed layer118is formed by depositing one or combination of Ru, TaRu, Ir, Rh, Pt, Pd, Cu, Co or alloys of any of these materials. The adhesion/plating seed layer118has a thickness in a range of 20 A to 800 A.

FIG. 2gdepicts filling the via opening122with a conductive material120after formation of the adhesion/plating seed layer inFIG. 2f. The via opening122is filled by depositing Cu, Al, W or alloys of any of these materials.

As mentioned above,FIG. 1depicts an embodiment of the invention. Once the via opening122has been filled with conductive material120as depicted inFIG. 2g, the semiconductor structure is planarized. As shown inFIG. 1, after planarization, the conductive filled via has an upper surface coplanar with the upper surface of the second dielectric material104.FIG. 1depicts the embodiment of the invention that includes the second barrier layer116. As discussed herein, the second barrier layer is an optional layer in an embodiment of the invention.