Semiconductor device with a protection diode

According to one embodiment, a semiconductor device includes a semiconductor substrate, a semiconductor region, a first and second electrodes. The semiconductor region is provided on the semiconductor substrate via an insulating film. The semiconductor region includes a protection diode. An overvoltage causes breakdown of the protection diode. A PN junction of the protection diode is exposed at an end face of the semiconductor region. A first and second electrodes are provided distally to the exposed end face of the PN junction. The first and second electrodes are connected to the semiconductor region to provide a current to the protection diode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-1495.56, filed on Jun. 24, 2009; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

Trends in recent years of higher speeds and greater information volumes have led to increasingly higher technical requirements for electronic devices such as downscaling and increasing frequencies. As a result, requirements to increase the electrostatic discharge (ESD) immunity of electronic devices have abruptly increased as well. Also, in small high-speed switching devices used in portable devices, etc., and MOS transistors widely used in voltage converter circuits, etc., downscaling the device or reducing the gate oxide film thickness causes concern about reduced ESD immunity.

In such devices, ESD protection diodes are often formed simultaneously on the silicon substrate. In particular, protection elements using polycrystalline silicon have high degrees of freedom during the device manufacturing processes and are widely used.

Because conventional ESD protection diodes are provided in a ring-like closed annular structure, the surface area of the central portion is an ineffective surface area. Therefore, in the case where the junction surface area of a protection diode is increased to obtain a high ESD immunity, the ineffective surface area increases and the surface area of the entire device increases.

Therefore, there have been proposals to provide a high breakdown-voltage protection diode by connecting a ring-like protection diode formed in a chip peripheral portion and the like to a ring-like protection diode formed in a peripheral portion of an electrode pad.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a semiconductor region, a first and second electrodes. The semiconductor region is provided on the semiconductor substrate via an insulating film. The semiconductor region includes a protection diode. An overvoltage causes breakdown of the protection diode. A PN junction of the protection diode is exposed at an end face of the semiconductor region. A first and second electrodes are provided distally to the exposed end face of the PN junction. The first and second electrodes are connected to the semiconductor region to provide a current to the protection diode.

Exemplary embodiments of the invention will now be described in detail with reference to the drawings.

The drawings are schematic or conceptual; and the relationships among the configurations and the lengthwise and crosswise dimensions of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among the drawings, even for identical portions.

In the specification and the drawings of the application, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

FIG. 1is a schematic plan view illustrating the configuration of a semiconductor device according to an embodiment.

FIG. 2is a cross-sectional view along line A-A of the semiconductor device illustrated inFIG. 1.

As illustrated inFIGS. 1 to 2, a semiconductor device60of this example includes a semiconductor substrate5, an insulating film17, a semiconductor region50, and first and second electrodes20and21.

The semiconductor region50is provided on the semiconductor substrate5via the insulating film17. The case is illustrated in this example where the semiconductor region50has a band configuration. N-type semiconductor regions18a,18b, and18care formed alternately with P-type semiconductor regions19aand19bin the semiconductor region50in striped configurations to an end face Q (a side wall). In other words, PN junctions among the N-type semiconductor regions18a,18b, and18cand the P-type semiconductor regions19aand19bare exposed at the end face Q (the side wall) of the semiconductor region50. The electrodes20and21are provided distally to the end face Q.

The P-type semiconductor region19aand the N-type semiconductor region18aform a protection diode28a. Similarly, the P-type semiconductor region19band the N-type semiconductor region18bform a protection diode28b. The P-type semiconductor region19aand the N-type semiconductor region18bform a protection diode29a. The P-type semiconductor region19band the N-type semiconductor region18cform a protection diode29b.

The multiple protection diodes28a,29a,28b, and29bare formed in the semiconductor region50and connected in series in an NPNPN structure.

The first electrode20and the second electrode21are connected to the N-type semiconductor regions18aand18cof the semiconductor region50, respectively. An overvoltage applied to the first electrode20and the second electrode21causes breakdown to occur in the protection diodes28a,29a,28b, and29bhaving the NPNPN structure; and a current flows.

As described below with reference toFIG. 6, such a semiconductor region50may be integrated with other elements such as transistors. In such a case, the configuration of the semiconductor region50is not limited to the straight-line band configuration illustrated inFIG. 1. The configuration of the semiconductor region50also may be a band configuration bent in various configurations such as an L-shape, a crank-like configuration, etc. The planar configuration of the protection diode also may have a band configuration bent in various configurations corresponding to the configuration of the semiconductor region50.

Herein, as illustrated inFIG. 1, a major surface of the semiconductor region50is taken as an XY plane. A first direction perpendicular to the XY plane is taken as a Z axis. The direction of the current flowing between the first and second electrodes20and21is taken as a Y axis. An X axis is taken to be perpendicular to the Y axis and the Z axis.

The first and second electrodes20and21have a spacing Ld therebetween in the Y axis direction.

In such a case, the end face Q (the side wall) of the semiconductor region50where the PN junctions of the protection diodes28a,29a,28b, and29bare exposed is formed a distance of at least the spacing Ld outside of an end portion P of the first and second electrodes20and21in the X axis direction. In other words, the semiconductor region50is formed such that Ws≧Ld is satisfied, where Ws is the distance between the end face Q and the end portion P.

Although the end face Q and the end portion P are illustrated inFIG. 1only for the right side of the electrodes20and21and the semiconductor region50, the left side is similar.

The semiconductor device60of this example can be manufactured by, for example, the following manufacturing processes.

First, an oxide film (the insulating film)17is formed with, for example, a film thickness of 0.5 μm on an N-type silicon substrate5. Thereupon, a polycrystalline silicon region (the semiconductor region)50is formed with, for example, a film thickness of 0.6 μm. Further, the oxide film (the insulating film)17is formed with, for example, a film thickness of 0.1 μm.

Then, boron (B) ion implantation is performed into the polycrystalline silicon region (the semiconductor region)50with, for example, an acceleration voltage of 40 keV and a dose of 5×1013cm−2. The polycrystalline silicon region (the semiconductor region)50is a P-type semiconductor region.

Using photolithography and, for example, RIE (Reactive Ion Etching), unnecessary regions of the polycrystalline silicon region (the semiconductor region)50are removed.

The oxide film (the insulating film)17is formed on the entire surface.

Subsequently, arsenic (As) ion implantation is performed in selective regions of the polycrystalline silicon region (the semiconductor region)50using photolithography. The ion implantation is performed with, for example, an acceleration voltage of 70 keV and a dose of 5×1014cm−2to form the N-type semiconductor regions18a,18b, and18c. The regions of the polycrystalline silicon region (the semiconductor region)50where the arsenic (As) ion implantation is not performed form the P-type semiconductor regions19aand19b.

Heat treatment is performed, for example, in a nitrogen gas (N2) atmosphere at a temperature of 900° C. for 20 minutes to activate each of the regions.

The first and second electrodes20and21are formed on the N-type semiconductor regions18aand18c.

Electrode interconnection metal to other electrodes and electrode pads is formed as necessary.

The semiconductor device60of this example illustrated inFIG. 1andFIG. 2can be manufactured by the manufacturing processes recited above.

The diffusion of the impurities of the ion implantation and the heat treatment recited above is about 1 to 2 μm. Therefore, the minimum length of the N-type semiconductor regions18a,18b, and18cand the P-type semiconductor regions19aand19bis about 2 μm. Accordingly, the minimum length of an NPN or PNP structure having three P-type or N-type semiconductor regions is 6 μm.

In the semiconductor device60of this example, each of the N-type semiconductor regions18a,18b, and18cand the P-type semiconductor regions19aand19bis formed with a length of, for example, 4 μm. The distance from the first electrode20to the most proximal P-type semiconductor region19ais, for example, 4 μm. The distance from the second electrode21to the most proximal P-type semiconductor region19balso is, for example, 4 μm.

In such a case, the spacing Ld between the first and second electrodes20and21in the Y axis direction is 20 μm. In this example, the distance Ws from the end portion P of the first and second electrodes20and21to the end face Q (the side wall) of the semiconductor region50where the PN junctions of the protection diodes28a,29a,28b, and29bare exposed is, for example, 20 μm.

The case is illustrated in this example where the N-type semiconductor regions18a,18b, and18cand the P-type semiconductor regions19aand19bform the protection diodes28a,29a,28b, and29bhaving an NPNPN structure. However, the invention is not limited thereto. Any number of N-type semiconductor regions and P-type semiconductor regions may be formed alternately to form any number of protection diodes. Moreover, protection diodes having a PNPNP structure also may be formed.

When an overvoltage is applied to the first electrode20and the second electrode21of such a semiconductor device60, breakdown occurs in the protection diodes28a,29a,28b, and29bformed in the semiconductor region50; and a current flows.

In the case where a high voltage is applied to the first electrode20and a low voltage is applied to the second electrode21, an overvoltage causes breakdown to occur in the protection diodes28aand28b; and a current flows from the first electrode20toward the second electrode21. Conversely, in the case where a low voltage is applied to the first electrode20and a high voltage is applied to the second electrode21, an overvoltage causes breakdown to occur in the protection diodes29aand29b; and a current flows from the second electrode21toward the first electrode20.

FIG. 3is a graph of calculated values of a current density of the semiconductor device illustrated inFIG. 1.

The direction of the X axis inFIG. 3corresponds to the direction of the X axis illustrated inFIG. 1. The positions of the X axis inFIG. 3are taken to be the positions passing through the center of the N-type semiconductor region18bin the vertical direction inFIG. 1. The Y axis is set as illustrated inFIG. 1with an origin O of the centers of the first and second electrodes20and21in the X axis direction. A current density J is taken as the current density in the Y direction along the X axis in the case where a current 2×I flows between the first and second electrodes20and21.

InFIG. 3, a position X along the X axis in such a case is plotted on the horizontal axis; and the calculated value of the current density J in the Y axis direction is plotted on the vertical axis.

For the calculation of the current density J, the thickness of the semiconductor region50is taken to be 1 μm; and the Y axis direction length of each of the first and second electrodes20and21is taken to be 6 μm. An X axis direction width Wd of each of the first and second electrodes20and21is taken to be 50 μm; and the current 2×1 is 2 A.

In other words, the end portion P of the first and second electrodes20and21has a position of X=±Wd/2=±25 μm. InFIG. 1, the semiconductor device60is symmetric to the left and right. Therefore, inFIG. 3, the current density J in the Y axis direction along the X axis is calculated for the case where a current I of 1 A flows in the portion of 0≦X≦25 μm.

From symmetry, the current I flows parallel to the Y axis at X=0. Also, the current I flows parallel to the Y axis at Y=0, that is, along the X axis.

For ESD assuming an Human Body Model (HBM), a current of 1 A corresponds to 1500 V when converted to the voltage of the HBM. For the entire semiconductor device60, a current of 2 A flows and corresponds to 3000 V.

As illustrated inFIG. 3, the current density3at a position about 10 μm from the end portion P of the first and second electrodes20and21is substantially zero. Also at the end face Q (the side wall) of the semiconductor region50where the PN junctions of the protection diodes28a,29a,28b, and29bare exposed, there is no large concentration of recombination current.

Accordingly, according to the semiconductor device60of this example as described below, a protection diode structure can be obtained having a high ESD immunity and a low ineffective surface area.

A semiconductor device of a comparative example will now be described.

FIG. 4is a schematic plan view of the semiconductor device of the comparative example.

As illustrated inFIG. 4, a semiconductor device160of the comparative example includes the semiconductor substrate5, the insulating film17, a polycrystalline silicon region150, and first and second electrodes120and121.

The cross-sectional view along line A-A of the semiconductor device160of the comparative example is similar to the cross-sectional view along line A-A of the semiconductor device60of this example illustrated inFIG. 2.

However, in the semiconductor device160of the comparative example, an N-type semiconductor region118cis formed in a rectangular configuration inside the second electrode121as well. The planar configuration of the polycrystalline silicon region150also is a rectangular configuration. The planar configurations of N-type semiconductor regions118a,118b, and118cand P-type semiconductor regions119aand119bare concentric rectangular configurations formed alternately; and the PN junctions have closed annular structures. Therefore, in the semiconductor device160of the comparative example, the polycrystalline silicon region150does not have an end face (side wall) where the PN junctions are exposed. Otherwise, the semiconductor device160is similar to the semiconductor device60of this example illustrated inFIG. 1toFIG. 2.

In other words, the P-type semiconductor region119aand the N-type semiconductor region118aform a protection diode128a. Similarly, the P-type semiconductor region119band the N-type semiconductor region118bform a protection diode128b. The P-type semiconductor region119aand the N-type semiconductor region118bform a protection diode129a. The P-type semiconductor region119band the N-type semiconductor region118cform a protection diode129b.

The multiple protection diodes128a,129a,128b, and129bare formed in the polycrystalline silicon region150and connected in series in an NPNPN structure.

The N-type semiconductor region118aof the outermost portion of the polycrystalline silicon region150and the N-type semiconductor region118cof the innermost portion of the polycrystalline silicon region150are connected to the first electrode120and the second electrode121, respectively. By applying an overvoltage to the first electrode120and the second electrode121, breakdown occurs in the protection diodes128a,129a,128b, and129bhaving the NPNPN structure; and a current flows. Because the current flows between the first electrode120and the second electrode121, the portion of the N-type semiconductor region118cinside the second electrode121is an ineffective surface area as described below.

The semiconductor device160of the comparative example forms, for example, an ESD protection diode of a MOS transistor formed on the same semiconductor substrate5by electrically connecting the first electrode120and the second electrode121to the source and gate of the MOS transistor, respectively.

In the case where an ESD voltage is applied between the gate and source of the MOS transistor, breakdown occurs in the protection diodes128a,129a,128b, and129bof the semiconductor device160; and a current flows. In other words, the ESD voltage is discharged between the gate and source via the diode structure; and the MOS transistor is protected.

However, the planar configuration of the diode structure has a rectangular configuration in which the PN junctions are formed in closed annular structures. The reason behind such a structure is to not expose the PN junctions at the end face of the polycrystalline silicon region150because, in the case where the PN junctions are exposed at the end face of the polycrystalline silicon region150, the crystalline structure at the end face is disturbed or the end face is a fragmentation region occurring due to the manufacturing process; and therefore, there is a risk of a rapid recombination rate at the end face.

A rapid recombination rate easily causes the undesirable deterioration of the diode characteristics because, in such a region, an amount of energy corresponding to the band gap emitted during the recombination destructs the crystal lattice and further increases the regions having rapid recombination rates. Therefore, an annular structure is employed as a contrivance to avoid the PN junctions from being exposed at the end face of the polycrystalline silicon region150.

Of course, the protection diode itself must have a high ESD immunity to protect a MOS transistor and the like. It is necessary, to begin with, that the ESD protection diode has a structure that does not easily deteriorate.

However, in the case where the annular structure is used to avoid deterioration of such a protection diode, the surface area efficiency of the protection diode portion undesirably decreases.

In other words, generally, a greater diode junction surface area provides a better ESD protection function and ensures a greater ESD immunity. Accordingly, it is necessary to make the diode junction surface area as large as possible to obtain a high ESD immunity. However, to increase the diode junction surface area, it is necessary to increase the circumferential length of the rectangles having the annular structures as illustrated inFIG. 4. In such a case, the surface area of the central portion, i.e., the portion of the N-type semiconductor region118cinside the second electrode121illustrated inFIG. 4, is an ineffective surface area. Moreover, this leads to a surface area increase of the entire device and increased manufacturing costs and is industrially unfavorable.

Although it is effective to increase the film thickness of the polycrystalline silicon region150, in such a case, it is known that problems occur due to cracks and the like due to stress differences among the polycrystalline silicon, the oxide films, and the substrate silicon; and the limit is about 1 μm. Thus, attempts to obtain a protection diode having a good ESD protection function have undesirably caused an increase of the ineffective surface area and an increase of the surface area of the entire device.

Although the case is described in the semiconductor device160of the comparative example where the planar configuration of the protection diode is a concentric rectangular configuration, the case is similar for a ring-like configuration.

Conversely, in the semiconductor device60of this example, the protection diodes28a,29a,28b, and29bare formed in band configurations in the semiconductor region50; and there is little ineffective surface area.

In other words, as illustrated inFIG. 3, it is conceivable that a current path may be formed between the first and second electrodes20and21in the case where the ESD voltage is applied. In such a case, although the current path spreads outward, the degree of the spread is about the inter-electrode distance Ld or less. Accordingly, even when the ESD voltage is applied, the current does not reach the PN junction exposed portion of the end face Q (the side wall) of the semiconductor region50; and diode structure does not deteriorate radically.

Thus, according to the semiconductor device60of this example, a protection diode structure can be obtained in which a large recombination current does not concentrate at the PN junction exposed portion of the end face Q (the side wall) of the semiconductor region50; the ESD immunity is high; and the ineffective surface area is low.

FIG. 5is a schematic plan view illustrating another configuration of the semiconductor device according to an embodiment.

As illustrated inFIG. 5, a semiconductor device60aof this example includes the semiconductor substrate5, the insulating film17, the semiconductor region50, and first and second electrodes20aand21a.

In the semiconductor device60a, both end portions25in the X axis direction of the first and second electrodes20aand21aare formed in semicylindrical configurations. In other words, as illustrated inFIG. 5, the planar configurations of the first and second electrodes20aand21adiffer from those of the semiconductor device60in that both end portions25in the X axis direction are formed in arc-like configurations having radii of, for example, 3 μm. Otherwise, the semiconductor device60ais similar to the semiconductor device60.

Although a configuration is illustrated in this example in which both end portions25are formed in arc-like configurations, the configuration is not limited to an arc-like configuration. It is sufficient for the configuration to have a curvature relaxation portion. In other words, it is sufficient for the planar configurations of both end portions25such as those illustrated inFIG. 5to be non-polygonal and to be formed of a curve.

In the case where the end portion configurations of the first and second electrodes20and21are nearly perpendicular, current concentration occurs due to electric field concentration; abnormal heating occurs at such portions; and as a result, it is conceivable that diode deterioration also may occur. Therefore, by providing a curvature relaxation portion in the end portions25, such abnormal current concentration is avoided; and the deterioration of the diode structure can be suppressed.

Accordingly, in the semiconductor device60a, a large recombination current does not concentrate at the PN junction exposed portion of the end face Q (the side wall) of the semiconductor region50. A protection diode structure can be obtained in which current does not concentrate in the end portions25of the first and second electrodes20aand21a; the ESD immunity is high; and the ineffective surface area is low.

FIG. 6is a schematic plan view illustrating another configuration of the semiconductor device according to an embodiment.

As illustrated inFIG. 6, a semiconductor device61of this example includes the semiconductor substrate5, the insulating film17, semiconductor regions50ato50e, the first and second electrodes20aand21a, a MOS transistor region40, and an electrode pad45.

In the semiconductor device61of this example, the semiconductor regions50ato50dare provided in a peripheral portion of the semiconductor substrate5. The semiconductor region50eis provided in a periphery of the electrode pad45.

Only the first and second electrodes20aand21aconnected to the semiconductor region50aare illustrated. The first and second electrodes connected to the other semiconductor regions50bto50eare omitted.

Here, the semiconductor substrate5, the insulating film17, the semiconductor region50a, and the first and second electrodes20aand21aare similar to those of the semiconductor device60a. The planar configurations of the semiconductor regions50band50care similar to the planar configuration of the semiconductor region50aexcept for having U-shaped and L-shaped planar configurations, respectively. The semiconductor region50dis similar to the semiconductor region50aexcept for being provided inside the semiconductor region50ain the peripheral portion of the semiconductor substrate5. Although not illustrated, the planar configurations of the protection diodes of the semiconductor regions50band50c, which have the U-shaped and L-shaped planar configurations, may be U-shaped and L-shaped, respectively.

A distance Wp between the semiconductor regions50aand50bis not particularly limited and may be zero. However, even in the case where the distance Wp is zero and one end of the semiconductor region50ais connected to one end of the semiconductor region50b, the PN junctions are exposed at the end faces of at least the other ends of the semiconductor regions50aand50b.

FIG. 7is a cross-sectional view along line A-A of the semiconductor device illustrated inFIG. 6.

As illustrated inFIG. 7, a bottom face drain electrode4is provided on the lower side of the semiconductor substrate5in the MOS transistor region40of the semiconductor device61. P-type base regions6a,6b, and6care formed on the top face of the N-type semiconductor substrate5. N-type source regions7aand7bare formed on the top face of the P-type base region6a. N-type source regions7cand7dare formed on the top face of the P-type base region6b. N-type source regions7eand7fare formed on the top face of the P-type base region6c.

The MOS transistor region40is a region where a MOS transistor element is formed simultaneously with the semiconductor regions50ato50e; and the MOS transistor element is protected from ESD by the protection diodes formed in the semiconductor regions50ato50e.

The electrode pad45is electrically connected (not illustrated) to a gate8of the MOS transistor region40. Although the case is illustrated in this example where one electrode pad45is used, any number may be used.

A polycrystalline silicon gate electrode8ais formed on a region from the N-type source region7bto the N-type source region7cvia the oxide film17. Similarly, a polycrystalline silicon gate electrode8bis formed on a region from the N-type source region7dto the N-type source region7evia the oxide film17.

A source electrode10is formed to connect to the N-type source regions7ato7e.

The second electrodes21aof the semiconductor regions50ato50ewhich function as ESD protection diodes are electrically connected (not illustrated) to the polycrystalline silicon gate electrodes8aand8b. The first electrodes20aare electrically connected (not illustrated) to the source electrode10. Thereby, the MOS transistor region40is protected from the ESD voltage applied between the gate and source.

The case is illustrated in this example where the semiconductor substrate5is the N-type and the MOS transistor region40has an N-channel vertical MOS transistor structure. However, the invention is not limited thereto. A P-type semiconductor substrate may be used. Further, a P-channel MOS transistor region may be included; and a bipolar transistor region may be included.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the invention is not limited to these specific examples. For example, one skilled in the art may appropriately select specific configurations of components of semiconductor devices from known art and similarly practice the invention. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all semiconductor devices practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices described above as exemplary embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.

Furthermore, various modifications and alterations within the spirit of the invention will be readily apparent to those skilled in the art. All such modifications and alterations should therefore be seen as within the scope of the invention.