Electronic system

An electronic system is provided. The electronic system includes a platform controller and a plurality of peripheral devices. The platform controller has a first bus. The plurality of peripheral devices are respectively connected to the platform controller through the first bus. The plurality of peripheral devices include a master peripheral device and a slave peripheral device. The master peripheral device is connected to the slave peripheral device through a communication signal line. The master peripheral device communicates with the platform controller through the first bus. When the master peripheral device receives a communication request from the slave peripheral device through the communication signal line, the master peripheral device provides a communication signal corresponding to the communication request to the first bus, so the slave peripheral device communicates with the platform controller through the first bus.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 109122530, filed on Jul. 3, 2020. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a system, and particularly relates to an electronic system.

Description of Related Art

In an electronic system of the related art, a platform controller may only be connected to a single peripheral device through a single enhanced serial peripheral interface (eSPI) bus, so that when a plurality of peripheral devices are to be controlled or read, a plurality of buses must be used to connect the peripheral devices in order to implement control or reading operations of the peripheral devices. Therefore, in a conventional electronic system, communication and connection between the platform controller and the peripheral devices may not only increase the manufacturing cost of the electronic system, but the number of the peripheral devices connected to the electronic system is also limited by the number of physical buses, resulting in poor compatibility of the electronic system.

SUMMARY

The invention is directed to an electronic system, in which a platform controller is capable of simultaneously connecting a plurality of peripheral devices through a single bus.

The invention provides an electronic system including a platform controller and a plurality of peripheral devices. The platform controller has a first bus. The peripheral devices are respectively connected to the platform controller through the first bus. The peripheral devices include a master peripheral device and a slave peripheral device. The master peripheral device and the slave peripheral device are connected to a communication signal line. The master peripheral device communicates with the platform controller through the first bus. When the master peripheral device receives a communication request from the slave peripheral device through the communication signal line, the master peripheral device provides a communication signal corresponding to the communication request to the first bus, so that the slave peripheral device communicates with the platform controller through the first bus.

The invention provides an electronic system including a platform controller and a plurality of peripheral devices. The platform controller has a first bus. The peripheral devices are respectively connected to the platform controller through the first bus. The peripheral devices include a master peripheral device and a slave peripheral device. The master peripheral device and the slave peripheral device are connected to an interrupt signal line. The master peripheral device communicates with the platform controller through the first bus. When the master peripheral device receives an interrupt request provided by the slave peripheral device from the interrupt signal line, the master peripheral device provides an interrupt signal to the platform controller through the first bus, and the platform controller communicates with the slave peripheral device through the first bus according to the interrupt signal.

Based on the above description, the platform controller of the electronic system may be simultaneously connected to a plurality of peripheral devices through a single bus, and the peripheral devices do not cause signal conflicts on the bus.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1Ais a schematic diagram of an electronic system1according to an embodiment of the invention. The electronic system1includes a platform controller10, and a plurality of peripheral devices11-14. The platform controller10is connected to the peripheral devices11-14through a bus CS, and the platform controller10may communicate with the peripheral device11-14through the single bus CS. In an embodiment, the platform controller10is, for example, a platform controller hub (PCH), and the bus CS may be a bus compatible with an enhanced serial peripheral interface (eSPI), to connect the platform controller10and the peripheral devices11-14. Although the exemplary embodiment shown inFIG. 1is taken as an example for description, i.e., the connection relationship that the platform controller10in the electronic system1is connected to the four peripheral devices11-14, those of ordinary skills in the art may surely adjust the number of the peripheral devices connected to the platform controller10in the electronic system1, so that the electronic system1may adaptively meet different design requirements and usage concepts.

Since the peripheral devices11-14communicate with the platform controller10only through the single bus CS, in order to avoid signal conflicts caused by multiple peripheral devices11-14communicating on the bus CS at the same time, one of the peripheral devices11-14(the peripheral device11) may be preset as a master peripheral device, and the other peripheral devices12-14may be set as slave peripheral devices. In this way, the master peripheral device of the peripheral devices11-14may be responsible for most of the communications on the bus CS, and the other slave peripheral devices may monitor the communication content on the bus, and when communications of the slave peripheral devices are required, the slave peripheral devices may notify the master peripheral device, and the master peripheral device communicates with the platform controller10.

In an embodiment, the peripheral devices11-14may respectively have setting pins, respectively, and the peripheral devices11-14may be set as the master peripheral device or the slave peripheral devices according to voltages received by the setting pins. For example, as shown inFIG. 1, the peripheral device11is set as the master peripheral device as the setting pin receives an operating voltage VCC, and the other peripheral devices12-14are set as the slave peripheral devices12-14as the setting pins receive a ground voltage GND.

Further, the peripheral devices11-14have an interconnected communication signal line L1to communicate with each other, and when one or more of the slave peripheral devices12-14want to communicate, the slave peripheral devices12-14may provide communication requests to the communication signal line L1. When the master peripheral device11receives the communication requests through the communication signal line L1, it learns that one or more of the slave peripheral devices12-14want to communicate with the platform controller10, and the master peripheral device11may provide a communication signal to the platform controller10through the bus CS, and the platform controller10may communicate with one or more of the slave peripheral devices12-14according to the communication signal.

Referring toFIG. 1AandFIG. 2,FIG. 2is a signal waveform diagram of the electronic system1according to an embodiment of the invention. The platform controller10and the peripheral devices11-14may communicate through the bus CS according to a clock signal S_CK to generate a bus signal S_CS. More precisely, the clock signal S_CK is a signal for the platform controller10to communicate with the peripheral devices11-14when the platform controller10wants to communicate with one of the slave peripheral devices12-14. Therefore, the clock signal S_CK may be, for example, an input/output read command signal or a memory read command signal, which instructs to communicate with one of the slave peripheral devices12-14.

The bus signal S_CS includes a command time interval CMD, a time interval D1, a cyclic redundancy check interval CRC1, time intervals D2and D3, a state interval STS, and a cyclic redundancy check interval CRC2. Further, in the command time interval CMD, the time interval D1, and the cyclic redundancy check interval CRC1, the signal of the bus signal S_CS may be provided to the bus CS by the platform controller10for the peripheral devices11-14to read. Then, after turn around (TAR), in the time intervals D2and D3, the state interval STS and the cyclic redundancy check interval CRC2, in response to a command signal of the platform controller10, the signal of the bus signal S_CS may be provided to the bus CS from one of the master periphery device11and the slave peripheral devices12-14to provide data to be read by the platform controller10. Therefore, the platform controller10may provide a read command signal according to the bus signal S_CS and instruct the peripheral devices11-14to provide the data to be read.

In the command time interval CMD, the platform controller10may provide a command code to the bus CS, and the peripheral devices11-14may determine operation content to be performed by the platform controller10according to the command code. The command code provided by the platform controller10may be, for example, a command code of an input/output read command (for example, PUT_IORD_SHORT) or a memory read command (for example, PUT_MEMRD32_SHORT), so that the peripheral devices11-14may learn the operation content to be performed by the platform controller10according to the command code received in the command time interval CMD.

In the time interval D1, the platform controller10may provide address information to the bus CS. The peripheral devices11-14may read the address information and determine a reading target of the platform controller10. Further, the address information stores physical address information (for example, 32-byte physical address information) to be read by the platform controller10, and each of the peripheral devices11-14may respectively determine whether it is the reading object of the platform controller10after reading the address information, and when the peripheral devices11-14determine to correspond to the reading object of the platform controller10according to the address information, the corresponding peripheral devices11-14respond to the read command or the memory read command of the platform controller10through the bus CS in a subsequent time interval.

In the cyclic redundancy check interval CRC1, the platform controller10may provide a corresponding verification code to the bus CS according to data content transmitted in the command time interval CMD and the time interval D1, and the peripheral devices11-14determine whether the data received in the command time interval CMD and the time interval D1is correct according to the verification code.

In the time interval D2, the master peripheral device11may detect the communication signal line L1to determine whether the slave peripheral devices12-14need to transmit data. When the master peripheral device11receives a communication request from the communication signal line L1, the master peripheral device11may provide a communication signal to the platform controller10through the bus CS, and one or more of the slave peripheral devices12-14may communicate with the platform controller10through the bus CS.

When the address information provided by the platform controller10in the time interval D1corresponds to the slave peripheral device12, it represents that the platform controller10intends to perform a read operation on the slave peripheral device12. The master peripheral device11may detect a voltage level of the communication signal line L1to determine whether the communication request is received. For example, the communication signal line L1may be driven by a driving circuit (not shown inFIG. 1A) in the electronic system1to set the voltage level of the communication signal line L1to a first voltage level (for example, a high voltage level). When the slave peripheral device12changes the voltage level of the communication signal line L1from the first voltage level (for example, the high voltage level) to a second voltage level (for example, a low voltage level), the master peripheral device11detects the above voltage level change of the communication signal line L1, and determines that the communication request provided by one of the slave peripheral device12-14is received. Therefore, the master peripheral device11may provide a wait signal (for example, WAIT_STATE) of the communication signal to the bus CS. Then, when the slave peripheral device12reads or obtains the data content to be read by the platform controller10, the slave peripheral device12may change the voltage level of the communication signal line L1from the second voltage level (for example, the low voltage level) to the first voltage level (for example, the high voltage level). In this way, the master peripheral device11may provide an accept signal (for example, ACCEPT) of the communication signal to the bus CS. Therefore, the platform controller10may receive the communication signal including the wait signal and the accept signal in the time interval D2to better determine whether the read command is correctly transmitted to the peripheral devices11-14and whether the peripheral devices11-14are in a ready state for reading.

In the time interval D3, the master peripheral device11does not provide a signal to the bus CS, but the slave peripheral device12that provides the communication request provides data to the bus CS to avoid data conflicts on the bus CS. The platform controller10may obtain the data to be read according to the data in the time interval D3.

In the state interval STS, the master peripheral device11and the platform controller10may provide a state of data transmission through the bus CS, for example, information about whether the peripheral devices11-14still have data to be transmitted, or whether the data to be transmitted is ready for transmission, etc.

In the cyclic redundancy check interval CRC2, the master peripheral device11may provide the corresponding verification codes to the bus CS according to the data content transmitted in the time intervals D2, D3and the state interval STS, so that the platform controller10may determine whether the data received in the time intervals D2, D3and the state interval STS is correct according to the verification codes.

Therefore, the platform controller10in the electronic system1may be connected to a plurality of the peripheral devices11-14through the single bus CS. By configuring the master peripheral device and the slave peripheral devices of the peripheral devices11-14, the master peripheral device11may effectively integrate and manage communications of the peripheral devices11-14with the platform controller10on the bus CS through the communication signal line L1, so that the electronic system1may be simultaneously connected to a plurality of the peripheral devices11-14without signal conflicts on the bus CS, thereby reducing the manufacturing cost of the electronic system1and improving the scalability of the electronic system1at the same time.

Then, referring toFIG. 1B,FIG. 1Bis a schematic diagram of an electronic system2according to an embodiment of the invention. The electronic system2shown inFIG. 1Bis similar to the electronic system1shown inFIG. 1A, so the same components are marked with the same symbols. Differences betweenFIG. 1AandFIG. 1Bare that the peripheral devices11-14inFIG. 1Aare respectively replaced by peripheral devices21-24inFIG. 1B, and the communication signal line L1inFIG. 1Ais replaced by an interrupt signal line L2inFIG. 1B. In the electronic system2, the peripheral device21is set as the master peripheral device21and the peripheral devices22-24are set as the slave peripheral devices22-24. The peripheral devices21-24are connected to each other through the interrupt signal line L2.

In the electronic system2, in order to avoid signal conflicts, the master peripheral device21may be responsible for most of the communications on the bus CS to communicate with the platform controller10. When one of the slave peripheral devices22-24needs to send an interrupt request and needs to communicate with the platform controller10, the slave peripheral devices22-24may provide an interrupt request through the interrupt signal line L2to notify the master peripheral device21, and the master peripheral device21sends an interrupt request (IRQ) to the platform controller10.

Then, referring toFIG. 1B,FIG. 3AandFIG. 3B,FIG. 3AandFIG. 3Bare signal waveform diagrams of the interrupt signal line L2according to an embodiment of the invention. In detail, when one or more of the slave peripheral devices22-24send the interrupt request to the master peripheral device21through the interrupt signal line L2, the master peripheral device21may determine whether to send the interrupt request (IRQ) to the platform controller10by monitoring the signal on the interrupt signal line L2.

An interrupt request signal S_IRQ1shown inFIG. 3Ais a signal waveform diagram on the interrupt signal line L2. The signal waveform diagram of the interrupt request signal S_IRQ1has thin lines, thick lines, and dotted lines. The thin lines represent that the interrupt signal line L2is driven by a driving circuit (not shown inFIG. 1B) in the electronic system2to set the voltage level of the interrupt signal line L2to the first voltage level (for example, the high voltage level)). The thick lines represent that the interrupt request signal S_IRQ1on the interrupt signal line L2is driven by the master peripheral device21to change the voltage level. The dotted lines represent that the interrupt request signal S_IRQ1on the interrupt signal line L2is driven by one or more of the slave peripheral devices22-24to change the voltage level.

As shown inFIG. 3A, in the interrupt request signal S_IRQ1, the interrupt request signal S_IRQ1has a reset time interval T0and a plurality of sub-time intervals T1˜T15. The sub-time intervals T1-T15may commonly constitute an interrupt request time interval in the interrupt request signal S_IRQ1, and the reset time interval T0may be ahead of the interrupt request time interval. Although a number of the sub-time intervals shown inFIG. 3Ais 15, the number of the sub-time intervals may be adjusted according to different design requirements, and is not limited by the invention.

In the reset time interval T0, the master peripheral device21may change the voltage level of the interrupt signal line L2from the first voltage level (for example, the high voltage level) to the second voltage level (for example, the low voltage level) to provide a reset signal to the interrupt signal line L2, such that the slave peripheral devices22-24may perform reset operations according to the reset signal. For example, the reset signal may be a second voltage level signal (for example, the low voltage level) that lasts for 16 time periods.

In the sub-time intervals T1-T15after the reset time interval T0, the sub-time intervals T1-T15may respectively have a synchronization time interval and a signal determination time interval. The master peripheral device21may provide a synchronization signal during the synchronization time interval to synchronize the operations of each of the slave peripheral devices22-24, and let each of the slave peripheral devices22-24to distinguish each of the sub-time intervals. Then, in the signal determination time interval after the synchronization time interval, one or more of the slave peripheral devices22-24may provide an interrupt request to the interrupt signal line L2, and the master peripheral device21may detect the interrupt signal line L2to determine whether the interrupt request is received.

Taking the sub-time interval T1as an example, in a synchronization time interval T11, the master peripheral device21may provide a synchronization signal to the interrupt signal line L2to synchronize the operations of the slave peripheral devices22-24, and the slave peripheral devices22-24may identify the sub-time interval T1according to the synchronization signal. For example, the synchronization signal may be the second voltage level signal (for example, the low voltage level) that lasts for 2 time periods.

In a signal determination time interval T12after the synchronization time interval T11, one or more of the slave peripheral devices22-24may provide an interrupt request to the interrupt signal line L2. In detail, the sub-time intervals T1-T15may correspond to different interrupt request types, and the master peripheral device21may determine the interrupt request type to be provided by the slave peripheral devices22-24according to the sub-time interval when the interrupt request is received. For example, one or more of the slave peripheral devices22-24may change the voltage level on the interrupt signal line L2from the first voltage level (for example, the high voltage level) to the second voltage level (for example, the low voltage level), and last for 2 time periods to provide the interrupt request to the interrupt signal line L2. The voltage level on the interrupt signal line L2may be changed back to the first voltage level (for example, the high voltage level) by the driving circuit (not shown inFIG. 1B) in the electronic system2after one or more of the slave peripheral devices22-24provide the interrupt request.

In the embodiment, the master peripheral device21proceeds with the reset time interval T0and the sub-time intervals T1-T15to determine whether to send an interrupt request to the platform controller10according to the interrupt request sent by the slave peripheral devices22-24. After the reset time interval T0and the sub-time intervals T1-T15are ended, the master peripheral device21periodically repeats the reset time interval T0and the sub-time intervals T1-T15to continuously detect whether the slave peripheral devices22-24intend to send the interrupt request.

As shown inFIG. 3B, in the interrupt request signal S_IRQ2, the interrupt request signal S_IRQ2has an enable time interval T00, the reset time interval T0, and a plurality of sub-time intervals T1-T15. Operation details of the reset time interval T0and the sub-time intervals T1-T15may refer to the related content ofFIG. 3Adescribed above, which are not repeated. A difference between the interrupt request signal S_IRQ1and the interrupt request signal S_IRQ2is that the interrupt request signal S_IRQ1is a periodic signal, while the interrupt request signal S_IRQ2is a one-time signal generated by one of the slave peripheral devices22-24after being triggered, and the voltage level on the interrupt signal line L2may be driven by the driving circuit (not shown inFIG. 1B) in the electronic system2, so that the voltage level on the interrupt signal line L2may be set to the first voltage level (for example, the high voltage level).

In the enable time interval T00of the interrupt request signal S_IRQ2, one of the slave peripheral devices22-24may provide an enable signal to the interrupt signal line L2, so as to change the voltage level on the interrupt signal line L2from the first voltage level (for example, the high voltage level) to the second voltage level (for example, the low voltage level). For example, the enable signal may be the second voltage level signal (for example, the low voltage level) that lasts for 3 time periods. After receiving the enable signal, the master peripheral device21may learn that one of the slave peripheral devices22-24needs to send an interrupt request, so that the master peripheral element21may proceed with the one-time reset time interval T0and the sub-time intervals T1-T15after the enable time interval T00to determine the type of interrupt request to be provided. After the reset time interval T0and the interrupt request time interval (the sub-time intervals T1-T15) are ended, the voltage level on the interrupt signal line L2may be driven to the first voltage level (for example, the high voltage level) by the driving circuit of the electronic system2. The master peripheral device21may wait for trigger of the next enable signal before the master peripheral device21repeats the reset time interval T0and the interrupt request time interval (the sub-time intervals T1-T15).

Therefore, in the electronic system2, the platform controller10may be connected to a plurality of the peripheral devices21-24through the single bus CS. The peripheral devices21-24may effectively integrate whether the peripheral devices21-24need to send an interrupt request through the interrupt signal line L2, so that the electronic system2may be simultaneously connected to a plurality of the peripheral devices21-24without signal conflicts on the bus CS, thereby further reducing the manufacturing cost of the electronic system2and improving the scalability of the electronic system2at the same time.

Referring toFIG. 1C,FIG. 1Cis a schematic diagram of an electronic system3according to an embodiment of the invention. The electronic system3shown inFIG. 1Cis similar to the electronic system1shown inFIG. 1Aand the electronic system2shown inFIG. 1B, so that the same components are marked with the same symbols. A difference betweenFIG. 1A,FIG. 1BandFIG. 1Cis that peripheral devices31-34inFIG. 1Chave both of the communication signal line L1and the interrupt signal line L2. Therefore, in the electronic system3, the peripheral devices31-34may communicate with each other through the communication signal line L1and the interrupt signal line L2at the same time. The slave peripheral devices32-34may notify the master peripheral device31to communicate with the platform controller10on the bus CS, and the master peripheral device31determines whether the slave peripheral devices32-34need to send an interrupt request.

In summary, the platform controller in the electronic system may be simultaneously connected to a plurality of the peripheral devices through the single bus. By setting one of the peripheral devices as the master peripheral device and setting the other peripheral devices as the slave peripheral devices, the master peripheral device may integrate communications between the slave peripheral devices and the platform controller through the communication signal line and/or the interrupt signal line interconnected to the peripheral devices, or determine whether the slave peripheral devices need to send the interrupt request. In this way, in case that the platform controller in the electronic system is simultaneously connected to a plurality of the peripheral devices through the single bus, signal conflicts may also be effectively avoided, thereby reducing the manufacturing cost of the electronic system and improving the scalability of the electronic system at the same time.