Nanowire memory

Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0053397, filed Jun. 6, 2009, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a nanowire memory, and more particularly, to a nanowire memory having a nanowire as a channel and using nanodots adsorbed on the nanowire.

2. Discussion of Related Art

A non-volatile memory including nanodots operates as a memory by applying a negative or positive voltage to a gate electrode to inject or discharge charges into or from the nanodot, and changing a threshold voltage on a source and a drain. Since this memory goes through many complicated processes generally used as semiconductor fabrication processes, which causes high fabrication costs. In addition, a conventional memory has two states, i.e., “1” or “0,” so that multi-level data cannot be stored.

SUMMARY OF THE INVENTION

The present invention is directed to a memory device capable of storing multi-level data through a memory including nanodots having a simple structure.

One aspect of the present invention provides a nanowire memory including: a source and a drain corresponding to the source; and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges.

The nanowire may be formed of a doped semiconductor.

The nanodot may be formed of a doped semiconductor or a silicide formed by intermixing a semiconductor material with a metal.

The nanowire memory may include at least one nanodot.

The source and the drain may be formed of a silicide including a metal.

The nanowire memory may further include a gate disposed adjacent to the nanodot and configured to adjust a level of potential energy of the nanodot.

The nanowire memory may include the same number of gates as the nanodots.

The nanowire memory may sequentially or non-sequentially adjust the potential energy of the nanodot through the plurality of gates.

The nanowire memory may have a hybrid structure of non-volatile and volatile memories by adjusting respective charge concentrations of the plurality of nanodots.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, the present invention will be described with reference to the accompanying drawings in detail. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout the specification.

Throughout the specification, one part “comprises” a component, which, not illustrated otherwise, does not mean another component is omitted, but another component may be further included.

A nanowire memory according to the present invention will be described with reference toFIGS. 1 to 5below.

FIG. 1is a plan view of a nanowire memory according to an exemplary embodiment of the present invention, andFIG. 2is an enlarged cross-sectional view of a nanowire channel ofFIG. 1.

Referring toFIG. 1, the nanowire memory according to the exemplary embodiment of the present invention includes a source210, a drain220and a nano channel230which are disposed on a substrate200.

That is, the source210and the drain220are spaced apart from each other on the substrate200, and the nano channel230is formed to connect the source210to the drain220.

As shown inFIG. 2, the nano channel230is formed of a nanowire233on the substrate200which is exposed between the source210and the drain220, and a plurality of nanodots235are adsorbed on the nano channel230formed of the nanowire233.

The substrate200is formed of silicon, glass or other insulating material, the source210and the drain220may be formed of metal silicide, doped silicon or a doped semiconductor, the nanowire233forming the nano channel230may be formed of a doped semiconductor, and the nanodots235may be formed by directly adsorbing a doped semiconductor or a metal on the nanowire233.

The nanowire memory according to the exemplary embodiment of the present invention does not include separate gate and gate insulating layers, so that its fabrication process can be simplified.

Hereinafter, an operation principle of the nanowire memory ofFIG. 1will be explained.

FIG. 3is a diagram illustrating states of the nanowire memory according to voltages,FIG. 4is a diagram illustrating an operation principle of the nanowire memory ofFIG. 1, andFIG. 5is a current-voltage curve according to a first exemplary embodiment of the present invention.

FIG. 3illustrates an example according to the exemplary embodiment of the present invention, which is a nanowire memory formed by adsorbing a Pb nanodot235on a V2O5nanowire233, i.e., a nano channel.

An early state in which the Pd nanodot235is adsorbed on the V2O5nanowire233is referred to as state A.

That is, as the nanodot235is adsorbed on the nanowire233, a nano Schottky barrier is formed between the nanowire233and the nanodot235. A portion shown as a dotted line is a depletion region510of the nanowire.

As shown inFIG. 3, charges are distributed in a circle in the nanodot235. This state expands in area as in state B when water520is adsorbed on the nanodot235and the nanowire233. That is, the depletion region510of the nanowire233and an electron-distribution region of the nanodot235expand, respectively.

Due to the increase of the depletion region510and formation of defect potential having positive charges in the depletion region510, the amount of current flowing is changed according to the voltage.

Referring toFIGS. 4 and 5, a nano-Schottky barrier is formed around the nanodot235due to the depletion region510and induces a very small electron flow530at a low source-drain voltage (V=V1), thereby having a low amount of current as in state I.

However, as the voltage is increased, potential becomes higher than a barrier due to depletion, so that the electron flow530becomes larger and thus the current value is drastically increased as in state II. When the voltage is gradually increased, state II develops into state III. Here, a potential has a higher energy than the nano-schottky barrier. Thus, the electrons between the source and the drain flow into the nanodot235so as to be captured therein.

In state III, when the voltage is decreased, the capture of the electrons continues, and thus the captured electrons are emitted from the nanodot235, resulting in separation from the electron flow530.

However, in state IV, an amount of the electrons emitted from the nanodot235is smaller than that of the captured electrons due to attraction of the electrons to the positive charges present in the depletion region510. Thus, the current value in state IV is also lower than that in state III.

However, as the voltage is gradually decreased, the separation of the electrons captured in the nanodot due to the attraction to the positive charges is accelerated, resulting in states V and VI. Here, in state VI, a larger amount of current than that in state I flows at the same voltage.

That is, when the electrons flowing into the nanodot235are emitted during distribution of the positive charges in the depletion region510, hysteresis in which the current generated when the electrons flows outward due to the attraction caused by the positive charges in the depletion region510has a different value from that generated when the electrons flow inward is shown.

Likewise, the nanowire memory device according to the exemplary embodiment of the present invention can operate by capturing charges in a nanodot by adjusting a drain voltage instead of the current flow caused by a separate gate insulating layer and gate electrode. In other words, the nanodot is biased only by voltages of the drain and the source.

Another exemplary embodiment of the present invention will be described with reference toFIGS. 6 to 9below.

FIG. 6is a plan view of a nanowire memory according to a second exemplary embodiment, andFIGS. 7 to 9are graphs illustrating an operation principle of the nanowire memory ofFIG. 6.

Referring toFIG. 6, the nanowire memory has a similar structure to that ofFIG. 1. That is, a source630and a corresponding drain620are formed on a substrate610, and a nano channel690is formed between the source630and the drain620.

The nanowire memory according to another exemplary embodiment further includes the same number of gates640and650as that of the nanodots660and680on the nano channel690.

That is, as shown inFIG. 6, two gates640and650correspond to two nanodots660and680, respectively.

These gates640and650control potential energies of the corresponding nanodots660and680, respectively, and the detailed operations thereof are shown inFIGS. 7 to 9.

Referring toFIG. 7, defect potential generated when a positive voltage is applied to the drain as shown in the above-mentioned exemplary embodiment is lower than a fermi level of the source, and thus the defect potential is filled with charges.

These charges filling the defect potential flow to the drain in the state shown inFIG. 7to which a gate voltage is not applied.

Here, inFIGS. 8 and 9, the gate voltage applied to the defect potentials is adjusted. As shown inFIG. 8, when the gate voltage is increased, the defect potential becomes deeper, and thus tunneling of the charges staying in the defect potential to the drain is difficult, resulting in being operated as a non-volatile memory. As shown inFIG. 9, when the gate voltage applied to each defect potential is decreased, the depth of the defect potential is decreased, and the charges are not captured. Thus, the charges are transferred from the source to the drain.

Multi-level signals may be stored by adjusting the amount of the charges in each nanodot using the above-described method. That is, the multi-level signals may be controlled by adjusting several stable current values obtained by adjusting several nanodots and gate voltages.

Thus, unlike the first exemplary embodiment of the present invention relating to the non-volatile nanowire memory, the nanowire memory according to the second exemplary embodiment may adjust volatility using gates.

Further, a hybrid structure of non-volatile and volatile memories may be embodied by adjusting the depth of the defect potential.

That is, the depth of the defect potential is changed by adjusting the size of the nanodot and the concentration of charges. The hybrid structure of the non-volatile and volatile memories may be embodied using the changing depth of the potential.

For example, as shown inFIG. 7, in the nanowire memory adjusting energy using two gates640and650, when both nanodots have different charge concentrations from each other, the nanodot having a lower charge concentration is applicable as a volatile memory, and the nanodot having a higher charge concentration is applicable as a non-volatile memory.

As the charge concentration is increased, a deeper potential well may be formed and the depletion region may have more positive charges. Thus, the nanowire memory may be used as a non-volatile memory. In addition, the nanodot having a lower concentration can be applied as a volatile memory by adjusting the potential depth using the gate electrode.

A non-volatile nanowire memory according to the present invention has a simple structure, thereby simplifying a process, and generates multi-level current level by adjusting several energy states using gates. Further, the non-volatile nanowire memory can be operated as a volatile memory or a non-volatile memory by adjusting the gates and energy level, and a hybrid structure of the volatile memory and the non-volatile memory can be formed by having additional gates configured to adjust the energy level.