ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY PANEL

Provided is a array substrate, a manufacturing method thereof, and a display panel. The array substrate comprises a laminated substrate, a first insulating layer, a second insulating layer, and a third insulating layer, wherein a horizontal etching rate of the second insulating layer is less than that of the first insulating layer and the third insulating layer. The array substrate comprises a first region provided with a first type of via holes and a second region provided with a second type of via holes, the first type of via holes penetrates through the first, second and third insulating layers, and the second type of via holes penetrates through the third insulating layer. In the present disclosure, undercut structures formed in the first type of via holes can be eliminated through two etching processes, thus avoiding over-etching of the second type of via holes.

CROSS-REFERENCE TO RELATED APPLICATION

The present disclosure claims priority to and the benefit of Chinese Patent Application No. 202211256574.6, filed on Oct. 14, 2022, the entire content of which is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a technical field of display, and in particular, to an array substrate, a method for manufacturing an array substrate and a display panel.

BACKGROUND

In the structure of an existing thin film transistor, a plurality of layers of insulating materials are usually provided to insulate metal materials of different layers. Due to the existence of line-changing between different metal layers, it is necessary to etch the plurality of layers of insulating materials to form line-changing holes. Since there are deep line-changing holes and shallow line-changing holes in different regions, and in order to reduce the etching process, the deep line-changing holes and shallow line-changing holes are usually etched simultaneously. However, different etching rates of the different insulating materials result in technical problems such as undercut structures or over-etching of the line-changing holes or electrically connected via holes occur.

SUMMARY

The present disclosure provides an array substrate, a method for manufacturing an array substrate and a display panel to solve the technical problems that undercut structures or over-etching of the line-changing holes or electrically connected via holes occur in a current array substrate.

To solve the above problems, technical solutions provided in the present disclosure are as follows:

The present disclosure provides an array substrate, which comprises:a substrate;a first insulating layer disposed on the substrate;a second insulating layer disposed on the first insulating layer, a horizontal etching rate of the first insulating layer being greater than a horizontal etching rate of the second insulating layer; anda third insulating layer disposed on the second insulating layer, a horizontal etching rate of the third insulating layer being greater than a horizontal etching rate of the second insulating layer;wherein the array substrate is provided with a first region and a second region, and the array substrate comprises a first type of via holes and a second type of via holes, wherein the first type of via holes are disposed in the first region, the second type of via holes are disposed in the second region, the first type of via holes penetrate through the first insulating layer, the second insulating layer, and the third insulating layer, the second type of via holes penetrate through the third insulating layer, a hole depth of the first type of via holes is greater than that of the second type of via holes, and a pore diameter of the first type of via holes is greater than that of the second type of via holes.

In the array substrate of the present disclosure, the first type of via holes comprise a first via hole penetrating through the first insulating layer, the second insulating layer, and a third insulating layer; andthe second type of via holes comprise a second via hole and a third via hole, wherein the third via hole penetrates through the third insulating layer, and the second via hole penetrates through the second insulating layer and the third insulating layer;wherein a hole depth of the first via hole is greater than that of the second via hole, a hole depth of the second via hole is greater than that of the third via hole, a pore diameter of the first via hole is greater than that of the third via hole, and a pore diameter of the third via hole is greater than that of the second via hole.

In the array substrate of the present disclosure, the second via hole comprises a first via hole wall disposed on the third insulating layer and a second via hole wall disposed on the second insulating layer, and the first via hole wall and the second via hole wall are continuously disposed; orthe first via hole wall and the second via hole are discontinuously disposed, and a pore diameter of the second via hole on the third insulating layer is larger than that of the second via hole on the second insulating layer.

In the array substrate of the present disclosure, via hole walls of the first via hole on the third insulating layer, the second insulating layer, and the first insulating layer are continuously disposed;wherein an inclination angle of the via hole walls in the first via hole is smaller than that of the via hole walls in the second via hole.

In the array substrate of the present disclosure, the via hole wall of the first via hole on the second insulating layer and the via hole wall on the first insulating layer are continuously disposed, and the via hole wall of the first via hole on the third insulating layer and the via hole wall on the second insulating layer are discontinuously disposed;wherein a pore diameter of the first via hole on the third insulating layer is greater than pore diameters of the first via hole on the second insulating layer and the first insulating layer.

In the array substrate of the present disclosure, the array substrate comprises a gate layer disposed on the substrate, a gate insulating layer disposed on the gate layer, a source-drain layer disposed on the gate insulating layer, a first passivation layer disposed on the source-drain layer, a common electrode layer disposed on the first passivation layer, a second passivation layer disposed on the common electrode layer, and a pixel electrode layer disposed on the second passivation layer; andwherein the first via hole penetrates through the second passivation layer, the first passivation layer and the gate insulating layer for electrically connecting the common electrode layer and the gate layer, the second via hole penetrates through the second passivation layer and the first passivation layer for electrically connecting the source-drain layer and the pixel electrode layer, and the third via hole penetrates through the second passivation layer for electrically connecting the common electrode layer and a portion of the pixel electrode layer.

The present disclosure further provides a method for manufacturing an array substrate, comprising steps of:sequentially forming a first insulating layer, a second insulating layer, a third insulating layer, and a photoresist layer on a substrate, wherein a horizontal etching rate of the first insulating layer is greater than a horizontal etching rate of the second insulating layer, and a horizontal etching rate of the third insulating layer is greater than a horizontal etching rate of the second insulating layer;performing a first patterning process on the photoresist layer to form a first photoresist pattern, and performing a first etching process on the first insulating layer, the second insulating layer, and the third insulating layer in a first region of the array substrate through the first photoresist pattern;performing a second patterning process on the first photoresist pattern to form a second photoresist pattern, and performing a second etching process on the first insulating layer, the second insulating layer and the third insulating layer in the first region of the array substrate through the second photoresist pattern to form a first type of via holes, and performing a first etching process on the third insulating layer and/or the second insulating layer in a second region of the array substrate to form a second type of via holes;wherein a hole depth of the first type of via holes is greater than that of the second type of via holes, and a pore diameter of the first type of via holes is greater than that of the second type of via holes.

In the method for manufacturing an array substrate of the present disclosure, the step of performing a first patterning process on the photoresist layer to form a first photoresist pattern, and performing a first etching process on the first insulating layer, the second insulating layer, and the third insulating layer in a first region of the array substrate through the first photoresist pattern comprises:performing a first patterning process on the photoresist layer to form a first photoresist pattern, the first photoresist pattern comprises a first photoresist portion, a second photoresist portion, a third photoresist portion, and a fourth photoresist portion, thicknesses of the first photoresist portion, the second photoresist portion, and the third photoresist portion being the same, the thicknesses of the first photoresist portion, the second photoresist portion, and the third photoresist portion being less than a thickness of the fourth photoresist portion, and the first photoresist portion comprising a first through hole located in the first region; andperforming a first etching process on the first insulating layer, the second insulating layer, and the third insulating layer exposed through the first via hole.

In the method for manufacturing an array substrate of the present disclosure, the step of performing a second patterning process on the first photoresist pattern to form a second photoresist pattern, and performing a second etching process on the first insulating layer, the second insulating layer and the third insulating layer in the first region of the array substrate through the second photoresist pattern, and performing a first etching process on the third insulating layer in a second region of the array substrate comprises:processing the first photoresist pattern by an ashing process to remove the first photoresist portion, the second photoresist portion, and the third photoresist portion; andperforming a second etching process on the first insulating layer, the second insulating layer and the third insulating layer corresponding to the first photoresist to form a first via hole, performing a first etching process on the second insulating layer and the third insulating layer corresponding to the second photoresist portion to form a second via hole, and performing a first etching process on the third insulating layer corresponding to the third photoresist portion to form a third via hole;wherein a hole depth of the first via hole is greater than that of the second via hole, a hole depth of the second via hole is greater than that of the third via hole, a pore diameter of the first via hole is greater than that of the third via hole, and a pore diameter of the third via hole is greater than that of the second via hole.

The present disclosure further provides a display panel comprising the above mentioned array substrate.

Beneficial effects: according to the present disclosure, in the first etching process, initially etching is performed on the first type of via holes, and in the second etching process, etching is performed simultaneously on the first type of via holes and the second type of via holes, so that undercut structures formed in the first type of via holes caused by the second insulating layer with a low etching rate are eliminated, meanwhile the second type of via holes are subjected to etching for only one time, thus avoiding the technical problem of over-etching of the second type of via holes.

DETAILED DESCRIPTION

Hereinafter, technical solutions in embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings in embodiments of the present disclosure. Apparently, the described embodiments are part of, but not all of, the embodiments of the present disclosure. All other embodiments, obtained by a person with ordinary skill in the art on the basis of the embodiments in the present disclosure without expenditure of creative labor, belong to the protection scope of the present disclosure.

Referring toFIGS.1to6, the present disclosure provides an array substrate10, which comprises a substrate100, a first insulating layer200disposed on the substrate100, a second insulating layer300disposed on the first insulating layer200, and a third insulating layer400disposed on the second insulating layer300.

In this embodiment, a horizontal etching rate of the first insulating layer200is greater than a horizontal etching rate of the second insulating layer300, and a horizontal etching rate of the third insulating layer400is greater than a horizontal etching rate of the second insulating layer300.

In this embodiment, the array substrate10is provided with a first region180and a second region190. The array substrate10comprises a first type of via holes500and a second type of via holes600, wherein the first type of via holes500are disposed in the first region180, the second type of via holes600are disposed in the second region190, the first type of via holes500penetrate through the first insulating layer200, the second insulating layer300, and the third insulating layer400, the second type of via holes600penetrate through the third insulating layer400, a hole depth of the first type of via holes500is greater than that of the second type of via holes600, and a pore diameter of the first type of via holes500is greater than that of the second type of via holes600.

According to the present disclosure, in the first etching process, initially etching is performed on the first type of via holes500, and in the second etching process, etching is performed simultaneously on the first type of via holes500and the second type of via holes600, so that undercut structures formed in the first type of via holes500caused by the second insulating layer300with a low etching rate are eliminated, meanwhile the second type of via holes600are subjected to etching for only one time, thus avoiding the technical problem of over-etching of the second type of via holes600. Meanwhile, since the first type of via holes500penetrate through three insulating layers, when depths of the via holes electrically connected to each other are large, if pore diameters of an opening is small, contact impedance between an upper layer metal and the first metal layer120may be increased, and a technical problem of poor contact may occur. In the present disclosure, pore diameters of the first type of via holes500are increased, so that contact areas between the upper layer metal and the first metal layer120can be increased, and contact impedance between an upper layer metal and the first metal layer120can be reduced, thus improving the technical problem of poor contact between the upper layer metal and the first metal layer120.

Technical solutions of the present disclosure will now be described with reference to specific embodiments.

Referring toFIGS.1-2, the array substrate10may comprise a substrate100and a thin film transistor layer disposed on the substrate100, and the thin film transistor layer may comprise a plurality of metal layers and a plurality of insulating layers.

In this embodiment, material of the substrate100may be a material such as glass, quartz, or polyimide, or a flexible material such as polyimide, or a laminated film layer of a flexible material and an inorganic material.

In this embodiment, referring toFIG.2, the thin film transistor layer may comprise a plurality of thin film transistors, which may be of an etch-blocking type, a back-channel etching type, or a structure that is divided into a bottom-gate thin film transistor, a top-gate thin film transistor, etc. according to positions of the gate and the active layer103, but there is no specific limitation. For example, the thin film transistor shown inFIG.2is a bottom-gate type thin film transistor, which may comprise a gate layer101disposed on the substrate100, a gate insulating layer102disposed on the gate layer101, an active layer103disposed on the gate insulating layer102, an interlayer insulating layer104disposed on the active layer103, a source-drain layer105disposed on the interlayer insulating layer104, a first passivation layer106disposed on the source-drain layer105, and a common electrode layer107disposed on the first passivation layer106, a second passivation layer108disposed on the common electrode layer107, and a pixel electrode layer109disposed on the second passivation layer108, wherein the common electrode layer107layer is connected with a constant voltage source, the pixel electrode layer109is electrically connected with the source-drain, and an electric field generated by the common electrode layer107and the pixel electrode layer109drives a liquid crystal to deflect.

In this embodiment, the gate layer101may be the first metal layer120of the array substrate10of the present disclosure, and the source-drain layer105may be the second metal layer130of the array substrate10of the present disclosure. The bottom-gate type thin film transistor in this embodiment comprises the interlayer insulating layer104. In other embodiments, the interlayer insulating layer104may not be provided, but the source-drain layer105and the active layer103are directly connected in contact.

In this embodiment, the first insulating layer200may comprise the gate insulating layer102, the second insulating layer300may comprise the first passivation layer106, and the third insulating layer400may comprise the second passivation layer108.

In this embodiment, due to the existence of line-changing between different metal layers or electrical connection between different metal layers in the existing array substrate10, it is necessary to etch an intermediate insulating layer to electrically connect the different metal layers.

In the array substrate10of the present disclosure, referring toFIG.1, the first type of via holes500may comprise a first via hole510penetrating through the first insulating layer200, the second insulating layer300, and the third insulating layer400. The second type of via holes600comprise a second via hole610and a third via hole620, wherein the third via hole620penetrates through the third insulating layer400, and the second via hole610penetrates through the second insulating layer300and the third insulating layer400.

In this embodiment, a hole depth of the first via hole510is greater than that of the second via hole610, a hole depth of the second via hole610is greater than that of the third via hole620, a pore diameter L1of the first via hole510is greater than a pore diameter L3of the third via hole620, and a pore diameter L3of the third via hole620is greater than a pore diameter L2of the second via hole610.

In this embodiment, the first metal layer120may be in contact with the first insulating layer200, the first via hole510may correspond to the first metal layer120, and the first via hole510exposes a portion of the first metal layer120, so that an upper metal layer can be electrically connected with the first metal layer120through the first via hole510. The second metal layer130may be in contact with the second insulating layer300, the second via hole610corresponds to the second metal layer130, and the second via hole610exposes a portion of the second metal layer130, so that the upper metal layer can be electrically connected with the second metal layer130through the second via hole610. The common electrode layer107may be in contact with the third insulating layer400, the third via hole620corresponds to the common electrode layer107, and the third via hole620exposes a portion of the common electrode layer107, so that an upper metal layer can be electrically connected with the common electrode layer107through the third via hole620.

In this embodiment, referring toFIG.3, which is a schematic structural diagram of a display panel900according to the present disclosure. The display panel900comprises a display area910within which the first area180may be located and a non-display area920within which the second area190may be located. Alternatively, the first area180and the second area190may be simultaneously located within the display area910or the non-display area920. In the following embodiments of the present disclosure, it is illustrated by taking the first area180in the non-display area920, and the second area190in the display area910as an example.

Referring toFIG.3, the first via hole510may be disposed in the non-display area920, and the second via hole610and the third via hole620may be disposed in the display area910. For example, the first via hole510may be a peripheral line-changing hole in the array substrate10of the display panel900, so that a metal line provided in the same layer as the gate layer101is changed to the second passivation layer108. Since the first via hole510is located in the non-display area920, and the interlayer insulating layer104may be formed into a film only in the display area910, there are only three insulating film layers between the peripheral gate layer101and the common electrode layer107. The second via hole610may be a connection hole in the display area910, for example, the source-drain is electrically connected with the upper pixel electrode layer109through the second via hole610.

In this embodiment, the third via hole620may be a connection hole in the display area910, and the common electrode layer107is connected with a constant voltage source, and a signal line of the constant voltage source is generally provided in the same layer as the gate layer101or the source-drain layer105. Therefore, if it is necessary to introduce a signal of the constant voltage source to the common electrode layer107, a mask process needs to be added to form a via hole on the first passivation layer106, so that the source-drain layer105and the common electrode layer107are electrically connected. Referring toFIG.2, in the present disclosure, a first transfer pad640may be formed on a second passivation layer108, the first transfer pad640and the pixel electrode layer109may be formed in one mask process, the common electrode layer107is electrically connected with the first transfer pad640through a third via hole620, and the first transfer pad640is electrically connected with the second transfer pad650through a transfer hole630, and the second transfer pad650and the source-drain may be formed in one mask process. Since both the transfer hole630and the second via hole610penetrate through the first passivation layer106and the second passivation layer108, the transfer hole630and the second via hole610may be formed in the same etching process, without adding an additional mask process, that is, a constant voltage source can be transmitted to the common electrode layer through the second transfer pad650, the transfer hole630, the first transfer pad640and the third via hole620.

In this embodiment, referring toFIG.1, since the first via hole510needs to be initially etched before the second via hole610and the third via hole620are etched, then the first via hole510is subjected to a second etching process together with the second via hole610and the third via hole620, therefore, the first via hole510is subjected to two etching processes, such that the pore diameter L1of the first via hole510is greater than the pore diameters of the second via hole610and the third via hole620. In addition, the second via hole610and the third via hole620need to be subjected to only one etching process, further, since two layers of insulating layer are etched when the second via hole610is subjected to the etching process, and one layer of insulating layer is etched when the third via hole620is subjected to the etching process, therefore, the pore diameter L3of the third via hole620is greater than the pore diameter L2of the second via hole610under the same etching time.

In this embodiment, since the first via hole510penetrates through three insulating layers, when depth of the electrically connected via hole is large, if pore diameter of the opening is small, the contact impedance of an upper layer metal and the first metal layer120may be increased, and a technical problem of poor contact may occur. In the present disclosure, the pore diameter L1of the first via hole510is increased, which increases contact area between the upper layer metal and the first metal layer120, and reduces contact impedance therebetween, meanwhile, the technical problem of poor contact between the upper layer metal and the first metal layer120can be improved.

In the array substrate10of the present disclosure, referring toFIG.1, the second via hole610comprises a first via hole wall611disposed on the third insulating layer400and a second via hole wall612disposed on the second insulating layer300, and the first via hole wall611and the second via hole wall612are continuously disposed.

In this embodiment, since the second via hole610penetrates through the third insulating layer400and the second insulating layer300, and a horizontal etching rate of the second insulating layer300is less than a horizontal etching rate of the third insulating layer400, a step will appear between the third insulating layer400and the second insulating layer300when the second via hole610is etched, which will cause reduction of an exposed area of the second metal layer130corresponding to the second via hole610, so as to reduce contact area between an upper layer metal and the second metal layer130and increase contact impedance between the upper layer metal and the second metal layer130. Therefore, in the present disclosure, excessive material of the second insulating layer300in the second via hole610can be removed by increasing etching time, so that via hole wall of the second via hole610on the third insulating layer400and via hole wall on the second insulating layer300are discontinuously disposed.

In the array substrate10of the present disclosure, referring toFIG.1, via hole walls of the first via hole510on the third insulating layer400, the second insulating layer300, and the first insulating layer200are continuously disposed, and an inclination angle of the via hole walls in the first via hole510is smaller than that of the via hole walls in the second via hole610.

In this embodiment, the via hole walls of the first via hole510and the second via hole610are continuously disposed. However, since depth of the first via hole510is greater than that of the second via hole610, the via hole with a larger depth has a larger contact impedance, and a problem of line breakage is prone to occur on the via hole walls. In the present disclosure, by increasing the inclination angle of the first via hole510, slope of the via hole wall of the first via hole510is slower, which increases deposition area of the upper metal layer on the via hole wall of the first via hole510, and reduces risk of line breakage of the upper metal layer on the via hole wall of the first via hole510, and meanwhile reduces the contact impedance of the upper metal layer and the first metal layer120.

In the array substrate10of the present disclosure, referring toFIG.4, the via hole wall of the second via hole620on the third insulating layer400and the via hole wall on the second insulating layer300are discontinuously disposed, and a pore diameter of the second via hole610on the third insulating layer400is greater than that of the second via hole610on the second insulating layer300.

In this embodiment, since the horizontal etching rate of the third insulating layer400is greater than the horizontal etching rate of the second insulating layer300, a step will appear between the third insulating layer400and the second insulating layer300when the second via hole610is etched. If the step needs to be removed, a longer etching time will be required, and may lead to over-etching of the third via hole620. Therefore, etching of the second via hole610can be stopped according to whether there is an undercut structure in the first via hole510. In addition, in the second via hole610, via hole walls may have a large inclination angle, and occurrence of the step structure in the second via hole610may reduce risk of line breakage of the upper layer metal in the second via hole610.

In the array substrate10of the present disclosure, referring toFIG.6, the via hole wall of the first via hole510on the second insulating layer300and the via hole wall on the first insulating layer200are continuously disposed, and the via hole wall of the first via hole on the third insulating layer400and the via hole wall on the second insulating layer300are discontinuously disposed.

In this embodiment, a pore diameter of the first via hole510on the third insulating layer400is greater than pore diameters of the first via hole510on the second insulating layer300and the first insulating layer200.

In this embodiment, since the first via hole510penetrates through the third insulating layer400, the second insulating layer300, and the first insulating layer200, and the horizontal etching rate of the second insulating layer300is less than the horizontal etching rate of the third insulating layer400and the first insulating layer200, a step will appear between the third insulating layer400and the second insulating layer300when the first via hole510is etched. Specifically, referring to the structure inFIG.5, an undercut structure is formed between the first insulating layer200and the second insulating layer300. Further, because the etching rate in the vertical direction of dry etching is greater than that in the horizontal direction, etching time of the first via hole510can be increased, that is, the undercut structure inFIG.5can be eliminated when the first via hole510is subjected to the second etching, so that structure of the first via hole510forms the structure as shown inFIG.6.

In this embodiment, due to greater depth of the first via hole510, risk of line breakage is easy to occur when the upper layer metal is deposited in the first via hole510. However, in the present disclosure, a step structure is formed in the first via hole510, which increases deposition area of the upper metal on the via hole wall of the first via hole510, and reduces the risk of line breakage of the upper metal in the first via hole510.

In the array substrate10of the present disclosure, materials of the first insulating layer200and the third insulating layer400are the same, and the materials of the first insulating layer200and the third insulating layer400may comprise silicon oxide and materials of the second insulating layer300may comprise silicon nitride.

In this embodiment, materials of the common electrode layer107and the pixel electrode layer109may comprise a transparent conductive material such as indium tin oxide.

Referring toFIG.7, the present disclosure provides a method for manufacturing the array substrate10, comprising steps of:

S10, sequentially forming the first insulating layer200, the second insulating layer300, the third insulating layer400, and a photoresist layer700on the substrate100, wherein a horizontal etching rate of the first insulating layer200is greater than a horizontal etching rate of the second insulating layer300, and a horizontal etching rate of the third insulating layer400is greater than a horizontal etching rate of the second insulating layer300.

In this step, material of the substrate100may be a material such as glass, quartz, or polyimide, or a flexible material such as polyimide, or a laminated film layer of a flexible material and an inorganic material.

Referring toFIG.8a, materials of the first insulating layer200and the third insulating layer400are the same, and the materials of the first insulating layer200and the third insulating layer400may comprise silicon oxide and materials of the second insulating layer300may comprise silicon nitride.

S20, performing a first patterning process on the photoresist layer700to form a first photoresist pattern, and performing a first etching process on the first insulating layer200, the second insulating layer300, and the third insulating layer400in a first region180of the array substrate10through the first photoresist pattern.

In this embodiment, step S20may comprise:

S201, performing a first patterning process on the photoresist layer700to form a first photoresist pattern, the first photoresist pattern comprises a first photoresist portion710, a second photoresist portion720, a third photoresist portion730, and a fourth photoresist portion740, thicknesses of the first photoresist portion710, the second photoresist portion720, and the third photoresist portion730are the same, thicknesses of the first photoresist portion710, the second photoresist portion720, and the third photoresist portion730are less than a thickness of the fourth photoresist portion740, and the first photoresist portion710comprises a first through hole711located in the first region180.

S202, performing a first etching process on the first insulating layer200, the second insulating layer300, and the third insulating layer400exposed through the first through hole711.

In this embodiment, referring toFIG.8b, the first photoresist710is located in the first region180of the array substrate10, which may be a peripheral line-changing region of the array substrate10, corresponding to a non-display area920of the display panel900. The second photoresist portion720and the third photoresist portion730may be located in the second region190of the array substrate10, the second region190is an in-plane region of the array substrate10, and the second region190corresponds to the display area910of the display panel900.

In the step S201, referring toFIG.8b, a multi-stage mask plate800is used to pattern the photoresist layer700to form the first photoresist portion710, the second photoresist portion720, the third photoresist portion730, and the fourth photoresist portion740with different thicknesses. The multi-stage mask plate800may comprise a first light-transmitting region810, a second light-transmitting region820, and a third light-transmitting region830, the first light-transmitting region810corresponds to the fourth photoresist portion740, the third light-transmitting region830corresponds to the first through hole711, and the second light-transmitting region820corresponds to the remaining regions.

In this embodiment, a positive photoresist is taken as an example of the material of the photoresist layer700. The first light-transmitting region810may have a light transmittance of 0%, the second light-transmitting region820may have a light transmittance of 50%, and the third light-transmitting region830may have a light transmittance of 100%.

In the step S202, referring toFIG.8c, in the present disclosure, a dry etching process can be used to perform a first etching process on three insulating layers, since the horizontal etching rate of the second insulating layer300is less than the horizontal etching rate of the third insulating layer400and the first insulating layer200, a step may appear between the third insulating layer400and the second insulating layer300during the first etching process, and an undercut structure is formed between the first insulating layer200and the second insulating layer300.

S30, performing a second patterning process on the photoresist layer700to form a second photoresist pattern, and performing a second etching process on the first insulating layer200, the second insulating layer300and the third insulating layer400in the first region180of the array substrate10through the second photoresist pattern to form a first type of via holes500, and performing a first etching process on the third insulating layer400and/or the second insulating layer300in the second region190of the array substrate10to form a second type of via holes600. The first type of via holes500have a hole depth greater than that of the second type of via holes600, and the first type of via holes500have a pore diameter greater than that of the second type of via holes600.

In this embodiment, the step S30may comprise:

S301, processing the first photoresist pattern710, the second photoresist portion720, and the fourth photoresist portion740by an ashing process to remove the first photoresist portion710, the second photoresist portion720, and the third photoresist portion730.

In the step S301, referring toFIG.8d, in the present disclosure, the first photoresist portion710, the second photoresist portion720, and the fourth photoresist portion740may be processed by using plasma, so as to remove the first photoresist portion710, the second photoresist portion720, and the third photoresist portion730, and to reduce thickness of the fourth photoresist portion740.

In this embodiment, plasma in the ashing process may be at least one of nitrogen tetrafluoride, sulfur hexafluoride, oxygen, etc.

After the ashing process is performed on the photoresist, continuing to perform Step S302: performing a second etching process on the first insulating layer200, the second insulating layer300and the third insulating layer400corresponding to the first photoresist portion710to form a first via hole510, performing a first etching process on the second insulating layer300and the third insulating layer400corresponding to the second photoresist portion720to form a second via hole610, and performing a first etching process on the third insulating layer400corresponding to the third photoresist portion730to form a third via hole620.

Specifically, in the step S302, referring toFIG.8e, in the first region180, the plasma contacts the third insulating layer400, the second insulating layer300, and the first insulating layer200exposed by the first photoresist portion710. Since the plasma has a vertical etching rate greater than a horizontal etching rate to the insulating layers, at this time, the first insulating layer200and the third insulating layer400are in contact with the plasma only in the horizontal direction, and the second insulating layer300is in contact with the plasma in both the horizontal direction and the vertical direction, so the plasma has a horizontal etching rate to the second insulating layer300greater than that to the first insulating layer200and the third insulating layer400, and the second insulating layer300has a back-off rate greater than that of the first insulating layer200and the third insulating layer400, thereby forming the first via hole510inFIG.8e.

In the step S302, referring toFIG.8e, in the second region190, the plasma also contacts the third insulating layer400and the second insulating layer300exposed by the second photoresist portion720at the same time. Since the etching rate of the second insulating layer300in the horizontal direction is less than that of the third insulating layer400in the horizontal direction, the third insulating layer400and the second insulating layer300exposed by the second photoresist720form a step at the beginning of etching stage. As the etching time increases, the plasma has a vertical etching rate greater than a horizontal etching rate to the insulating layers, at this time, the third insulating layer400is in contact with the plasma only in the horizontal direction, and the second insulating layer300is in contact with the plasma in both the horizontal direction and the vertical direction, so the plasma has a horizontal etching rate to the second insulating layer300greater than that to the third insulating layer400, and the second insulating layer300has a back-off rate greater than that of the third insulating layer400, thereby forming the second via hole610inFIG.8e.

In the step S302, referring toFIG.8e, in the second region190, the plasma also contacts the third insulating layer400exposed by the third photoresist portion730, thereby forming the third via hole620inFIG.8e.

In this embodiment, the array substrate10may comprise the first metal layer120, the second metal layer130, and the common electrode layer107disposed on the substrate100. The first metal layer120may be in contact with the first insulating layer200, the first via hole510may correspond to the first metal layer120, the first via hole510exposes a portion of the first metal layer120so that upper metal layers can be electrically connected with the first metal layer120through the first via hole510. The second metal layer130may be in contact with the second insulating layer300, the second via hole610corresponds to the second metal layer130, and the second via hole610exposes a portion of the second metal layer130so that the upper metal layers can be electrically connected with the second metal layer130through the second via hole610. The common electrode layer107may be in contact with the third insulating layer400, the third via hole620corresponds to the common electrode layer107, and the third via hole620exposes a portion of the common electrode layer107so that the upper metal layers can be electrically connected with the common electrode layer107through the third via hole620.

In this embodiment, structures shown inFIGS.4and6may also be obtained by the manufacturing method of the present disclosure.

Finally, peeling off the photoresist materials on the third insulating layer400, and performing subsequent film layer processes.

The present disclosure further provides a display panel900comprising the array substrate10. When the display panel900is a liquid crystal display panel, the display panel900further comprises a counter substrate disposed opposite to the array substrate10, and a liquid crystal layer disposed between the array substrate10and the counter substrate. When the display panel900is an organic light-emitting display panel, the display panel900further comprises an organic light-emitting functional layer disposed on the array substrate, and a thin film encapsulation layer disposed on the organic light-emitting functional layer. In addition, the array substrate10may also serve as a driving layer in a backlight module.

The present disclosure further provides a mobile terminal comprising a terminal main body and the above display panel, wherein the terminal main body and the display panel are integrated. The terminal body may be a circuit board and other devices bound to the display panel, a cover plate covering the display panel. The mobile terminal may comprise an electronic device such as a mobile phone, a television, or a laptop.

The present disclosure discloses an array substrate, a method of manufacturing an array substrate, and a display panel. The array substrate comprises a laminated substrate, a first insulating layer, a second insulating layer, and a third insulating layer, wherein a horizontal etching rate of the second insulating layer is less than a horizontal etching rate of the first insulating layer and the third insulating layer. The array substrate comprises a first region provided with a first type of via holes and a second region provided with a second type of via holes, the first type of via hole penetrates through the first insulating layer, the second insulating layer, and the third insulating layer, and the second type of via hole penetrates through the third insulating layer. According to the present disclosure, in the first etching process, initially etching is performed on the first type of via holes, and in the second etching process, etching is performed simultaneously on the first type of via holes and the second type of via holes, so that undercut structures formed in the first type of via holes caused by the second insulating layer with a low etching rate are eliminated, meanwhile the second type of via holes are subjected to etching for only one time, thus avoiding the technical problem of over-etching of the second type of via holes.

In the above-mentioned embodiments, descriptions of each embodiment have its own emphasis. For parts that are not detailed in one embodiment, please refer to the related descriptions of other embodiments.

An array substrate, a method for manufacturing an array substrate, and a display panel provided in embodiments of the present disclosure are described in detail above. The principles and embodiments of the present disclosure are described by using specific examples herein. Descriptions of the above embodiments are merely intended to help understand the technical solutions and core ideas of the present disclosure. A person skilled in the art shall understand that it is still possible to modify the technical solutions described in the above embodiments, or equivalently substitute some of the technical features thereof. However, these modifications or substitutions do not make the essence of the corresponding technical solutions depart from scopes of the technical solutions of each embodiment of the present disclosure.