Emission control line driver and organic light emitting display using the same

An emission control line driver is capable of securing the stability of an output and of freely controlling the width of emission control signals. The emission control line driver includes a plurality of stages respectively coupled to emission control lines. Each of the stages includes a plurality of transistors that are configured to output the emission control signal. The width of the emission control signal may be controlled to correspond to the width of a start signal. Furthermore, a circuit structure of the stages is simplified.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0001419, filed on Jan. 6, 2011, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

BACKGROUND

Aspects of embodiments according to the present invention relate to an emission control line driver and an organic light emitting display using the same.

2. Description of the Related Art

Recently, various flat panel displays (FPDs) with reduced weight and volume as compared to cathode ray tube (CRT) displays have been developed. The FPDs include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display.

Among the FPDs, the organic light emitting display displays an image using organic light emitting diodes (OLEDs) that generate light by re-combination of electrons and holes. The organic light emitting display has a fast response speed and is driven with low power consumption. A typical organic light emitting display supplies current corresponding to data signals to the OLEDs by using transistors formed in pixels so that light is emitted by the OLEDs.

The typical organic light emitting display includes a data driver for supplying the data signals to data lines, a scan driver for sequentially supplying scan signals to scan lines, an emission control line driver for supplying emission control signals to emission control lines, and a display unit including a plurality of pixels coupled to the data lines, the scan lines, and the emission control lines.

The pixels included in the display unit are selected, when the scan signals are supplied to the scan lines, to receive the data signals from the data lines. The pixels that receive the data signals generate light with brightness (e.g., predetermined brightness) corresponding to the data signals and display a predetermined image. Here, the emission times of the pixels are controlled by the emission control signals that are supplied from the emission control lines. In general, the emission control signals are supplied to overlap the scan signals that are supplied to one scan line or two scan lines to set the pixels, to which the data signals are supplied, in a non-emission state.

Therefore, the emission control line driver includes stages coupled to the emission control lines. The stages receive at least four clock signals and output high or low voltages to output lines.

However, since the stages included in the typical emission control line driver are driven by at least four clock signals, a large number of transistors are included. Therefore, manufacturing cost increases and it is difficult to secure the reliability of driving. In addition, when the emission control line driver is formed of a PMOS transistor, a low level output is unstable.

To be specific, when a low signal is supplied to an emission control line, the gate electrode of the transistor that outputs the low signal is maintained at a lower voltage than the low signal. However, the voltage of the gate electrode of the transistor increases due to leakage current and the output of the low signal is unstable.

SUMMARY

Accordingly, embodiments of the present invention are directed toward an emission control line driver capable of securing the stability of an output and of freely controlling the width of emission control signals, and an organic light emitting display using the same.

According to an embodiment of the present invention, there is provided an emission control line driver including a plurality of stages. Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a third input terminal to control the voltage of the second node, and a first capacitor coupled between the second input terminal and the second node.

The emission control line driver may further include a second capacitor coupled between the first node and the first power source. The first input terminal may be configured to receive a first clock signal. The second input terminal may be configured to receive a second clock signal. The third input terminal may be configured to receive a third clock signal. The fourth input terminal may be configured to receive a start signal or a sampling signal of a previous stage. The first clock signal, the second clock signal, and the third clock signal may not overlap each other. Each of the first clock signal and the second clock signal may be set in a period of i (i is a natural number) horizontal periods. The third clock signal may be set in a period of i/2 horizontal periods. The third clock signal may be supplied in a horizontal period after the first clock signal or the second clock signal is supplied in the horizontal period.

The first controller may include a fifth transistor coupled between the fourth input terminal and a third node, and having a gate electrode coupled to the first input terminal, a sixth transistor coupled between a sixth node and the second input terminal, and having a gate electrode coupled to the third node, a seventh transistor coupled between the sixth node and the first power source, and having a gate electrode coupled to the first output terminal, a third capacitor coupled between the third node and the sixth node, and a fourth capacitor coupled between the first output terminal and the first power source. The second output terminal may be electrically coupled to the sixth node.

The second controller may include an eighth transistor coupled between the first input terminal and a fourth node, and having a gate electrode coupled to the first node, a ninth transistor coupled between the fourth node and the second power source, and having a gate electrode coupled to the first input terminal, a tenth transistor coupled between the second node and a fifth node, and having a gate electrode coupled to the third input terminal, an eleventh transistor coupled between the fifth node and the third input terminal, and having a gate electrode coupled to the fourth node, and a fifth capacitor coupled between the fourth node and the fifth node.

The emission control line driver may further include a twelfth transistor coupled between the fourth input terminal and the third transistor, the twelfth transistor being configured to be turned on when a first control signal is supplied to a gate electrode of the twelfth transistor, and a thirteenth transistor coupled between a fifth input terminal and the first controller, the thirteenth transistor being configured to be turned on when a second control signal is supplied to a gate electrode of the thirteenth transistor. The first control signal and the second control signal may not overlap each other. The emission control line driver may further include a fourteenth transistor coupled between the first node and the second power source, the fourteenth transistor being configured to be turned on when a reset signal is supplied to a gate electrode of the fourteenth transistor. The reset signal may be commonly supplied to all of the stages.

According to an embodiment, an organic light emitting display includes a scan driver for sequentially supplying scan signals to scan lines, a data driver for supplying data signals to data lines, an emission control line driver for supplying emission control signals to emission control lines, and pixels positioned at crossing regions of the scan lines, the data lines, and the emission control lines. The emission control line driver includes stages respectively coupled to the emission control lines. Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a third input terminal to control the voltage of the second node, and a first capacitor coupled between the second input terminal and the second node.

According to the emission control line driver illustrated in the embodiments of the present invention and the organic light emitting display using the same, the voltage of the gate electrode of the transistor that outputs the low signal is periodically reduced using the clock signal so that the stability of an output may be secured. In addition, according to the embodiments of the present invention, the width of the emission control signal may be controlled to correspond to the width of the start signal. Furthermore, according to the embodiments of the present invention, since the stages receive three clock signals, a circuit structure may be simplified.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present invention, by which those skilled in the art may perform the present invention, will be described in detail with reference toFIGS. 1 to 6.

FIG. 1is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.

Referring toFIG. 1, the organic light emitting display according to an embodiment of the present invention includes a display unit40that includes pixels50positioned at the crossing regions of scan lines S1to Sn, data lines D1to Dm, and emission control lines E1to En, a scan driver10for driving the scan lines S1to Sn, a data driver20for driving the data lines D1to Dm, an emission control line driver30for driving the emission control lines E1to En, and a timing controller60for controlling the drivers10,20, and30.

The scan driver10sequentially supplies scan signals to the scan lines S1to Sn. When the scan signals are supplied to the scan lines S1to Sn, the pixels50are selected in units of horizontal lines (e.g., line-by-line).

The data driver20supplies data signals to the data lines D1to Dm in synchronization with the scan signals. The data signals supplied to the data lines D1to Dm are supplied to the pixels50that are selected by the scan signals.

The emission control line driver30sequentially supplies emission control signals to the emission control lines E1to En. Here, the emission control line driver30supplies the emission control signals so that the pixels50are set in a non-emission state during a period when the voltages corresponding to the data signals are charged. Therefore, the emission control signal supplied to the ith(i is a natural number) emission control line Eioverlaps the scan signal supplied to the ithscan line Si. On the other hand, the width of the emission control signal may be suitably set to correspond to the structure of the pixel50and the brightness to be realized.

FIG. 2is a block diagram schematically illustrating stages of the emission control line driver ofFIG. 1.

Referring toFIG. 2, the emission control line driver30according to an embodiment of the present invention includes n stages321to32nin order to supply emission control signals to the n emission control lines E1to En. The stages321to32nare coupled to the emission control lines E1to En, respectively, and are driven by three clock signals CLK1, CLK2, and CLK3.

Each of the stages321to32nincludes a first input terminal33, a second input terminal34, a third input terminal35, and a fourth input terminal36.

The first input terminal33of a kth(k is an odd or even number) stage32kreceives the first clock signal CLK1and the second input terminal34receives the second clock signal CLK2. The first input terminal33of a (k+1)thstage32k+1 receives the second clock signal CLK2, and the second input terminal34receives the first clock signal CLK1. The third clock signal CLK3is supplied to the third input terminal35of each of the stages321to32n, and a start signal FLM or a sampling signal of a previous stage is supplied to the fourth input terminal36.

The stages321to32nmay be formed of the same circuit and generate the emission control signals having width that is changed to correspond to the start signal FLM.

FIG. 3is a circuit diagram illustrating a first embodiment of one of the stages ofFIG. 2. InFIG. 3, for convenience sake, the first stage321will be illustrated.

Referring toFIG. 3, the stage321, according to the first embodiment of the present invention, includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, a first controller100, and a second controller102.

The first transistor M1is coupled between a first output terminal37and a first power source VDD. The gate electrode of the first transistor M1is coupled to a first node N1. The first transistor M1controls the voltage of the first output terminal37to correspond to the voltage applied to the first node N1. Here, when the first transistor M1is turned on, the first power source VDD (e.g., a high voltage) is supplied to the first output terminal37. Since the first output terminal37is coupled to the emission control line E1, the high voltage supplied to the first output terminal37is used as an emission control signal.

The second transistor M2is coupled between the first output terminal37and a second power source VSS. The gate electrode of the second transistor M2is coupled to a second node N2. The second transistor M2controls the voltage of the first output terminal37to correspond to the voltage applied to the second node N2. Here, when the second transistor M2is turned on, the second power source VSS (e.g., a low voltage) is supplied to the first output terminal37.

The third transistor M3is coupled between the fourth input terminal36and the first node N1. The gate electrode of the third transistor M3is coupled to the first input terminal33. The third transistor M3is turned on or off to correspond to the first clock signal CLK1supplied to the first input terminal33. When the third transistor M3is turned on, the fourth input terminal36and the first node N1are electrically coupled to each other. When the start signal FLM (or a previous stage sampling signal) is supplied to the fourth input terminal36, the first transistor M1is turned on.

The fourth transistor M4is coupled between the first power source VDD and the second node N2. The gate electrode of the fourth transistor M4is coupled to the first node N1. The fourth transistor M4is turned on or off to correspond to the voltage that is applied to the first node N1in order to control the voltage of the second node N2. That is, the fourth transistor M4is turned on when a low voltage is applied to the first node N1in order to supply the voltage of the first power source VDD to the second node N2. When the low voltage is supplied to the first node N1, the high voltage of the first power source VDD is supplied to the second node N2so that the first transistor M1and the second transistor M2are turned on or off at different times.

The first capacitor C1is coupled between the second input terminal34and the second node N2. The first capacitor C1controls the voltage of the second node N2to correspond to the second clock signal CLK2supplied to the second input terminal34. The operation processes of the first capacitor C1will be described later in more detail.

The second capacitor C2is coupled between the first node N1and the first power source VDD. The second capacitor C2is charged with the voltage corresponding to the turning on or off of the first transistor M1.

A first controller100supplies a sampling signal to a second output terminal38to correspond to the first clock signal CLK1and the second clock signal CLK2. Therefore, the first controller100includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a third capacitor C3, and a fourth capacitor C4.

The fifth transistor M5is coupled between the fourth input terminal36and a third node N3. The gate electrode of the fifth transistor M5is coupled to the first input terminal33. The fifth transistor M5is turned on or off to correspond to the first clock signal CLK1supplied to the first input terminal33in order to control the voltage of the third node N3.

The sixth transistor M6is coupled between a sixth node N6and the second input terminal34. The gate electrode of the sixth transistor M6is coupled to the third node N3. The sixth transistor M6controls the voltage of the sixth node N6to correspond to the voltage applied to the third node N3.

The seventh transistor M7is coupled between the first power source VDD and the sixth node N6. The gate electrode of the seventh transistor M7is coupled to the first output terminal37. The seventh transistor M7is turned on or off to correspond to the voltage applied to the first output terminal37in order to control the voltage of the sixth node N6.

The third capacitor C3is coupled between the third node N3and the sixth node N6. The third capacitor C3is charged with the voltage corresponding to the turning on or turning off of the sixth transistor M6.

The fourth capacitor C4is coupled between the first power source VDD and the first output terminal37. The fourth capacitor C4is charged with the voltage corresponding to the turning on or off of the seventh transistor M7.

InFIG. 3, the second output terminal38is coupled to the sixth node N6. The second output terminal38supplies the voltage applied to the sixth node N6as a sampling signal to a next stage322.

The second controller102controls the voltage of the second node N2to correspond to the first clock signal CLK1and the third clock signal CLK3. Here, in a period when the emission control signal is not supplied to the first output terminal37, the second controller102maintains the voltage of the second node N2as a low voltage. InFIG. 3, the second controller102includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a fifth capacitor C5.

The eighth transistor M8is coupled between the first input terminal33and a fourth node N4. The gate electrode of the eighth transistor M8is coupled to the first node N1. The eighth transistor M8is turned on or off to correspond to the voltage applied to the first node N1in order to control the voltage of the fourth node N4.

The ninth transistor M9is coupled between the fourth node N4and the second power source VSS. The gate electrode of the ninth transistor M9is coupled to the first input terminal33. The ninth transistor M9is turned on or off to correspond to the first clock signal CLK1supplied to the first input terminal33in order to control the voltage of the fourth node N4.

The tenth transistor M10is coupled between the second node N2and a fifth node N5. The gate electrode of the tenth transistor M10is coupled to a third input terminal35. The tenth transistor M10is turned on or off to correspond to the third clock signal CLK3supplied to the third input terminal35in order to control the voltage of the second node N2.

The eleventh transistor M11is coupled between the fifth node N5and the third input terminal35. The gate electrode of the eleventh transistor M11is coupled to the fourth node N4. The eleventh transistor M11is turned on or off to correspond to the voltage applied to the fourth node N4in order to control the voltage of the fifth node N5.

The fifth capacitor C5is coupled between the fourth node N4and the fifth node N5. The fifth capacitor C5is charged with the voltage corresponding to the turning on or off of the eleventh transistor M11.

FIG. 4is a waveform chart illustrating the operation processes of the stage ofFIG. 3.

Referring toFIG. 4, the first clock signal CLK1and the second clock signal CLK2are supplied in the period of iH (i is a natural number, e.g., a horizontal period), and the third clock signal CLK3is supplied in the period of i/2H. InFIG. 4, for convenience sake, the first clock signal CLK1and the second clock signal CLK2are set in the period of 2H and the third clock signal CLK3is set in the period of 1H.

InFIG. 4, the first clock signal CLK1and the second clock signal CLK2are supplied in different horizontal periods H, and the third clock signal CLK3is supplied every horizontal period H so that the first clock signal CLK1does not overlap the third clock signal CLK3. Then, in the horizontal period H, after the first clock signal CLK1or the second clock signal CLK2is supplied, the third clock signal CLK3is supplied. That is, in an exemplary horizontal period, the third clock signal CLK3is supplied after the first clock signal CLK1is supplied. In the next horizontal period, the third clock signal CLK3is supplied after the second clock signal CLK2is supplied.

Operation processes will be described in more detail as follows. First, the start signal FLM (e.g., the low signal) is supplied to the fourth input terminal36. After the start signal FLM is supplied to the fourth input terminal36, the first clock signal CLK1is supplied to the first input terminal33. When the first clock signal CLK1is supplied, the third transistor M3, the fifth transistor M5, and the ninth transistor M9are turned on.

When the third transistor M3is turned on, the start signal FLM is supplied to the first node N1. When the start signal FLM is supplied to the first node N1, the first transistor M1, the fourth transistor M4, and the eighth transistor M8are turned on.

When the first transistor M1is turned on, the voltage corresponding to the turning on of the first transistor M1is charged at the second capacitor C2. When the first transistor M1is turned on, the voltage of the first power source VDD is supplied to the first output terminal37. In this case, the emission control signal is supplied to the emission control line E1.

When the fourth transistor M4is turned on, the first power source VDD is supplied to the second node N2. When the first power source VDD is supplied to the second node N2, the second transistor M2is turned off. When the second transistor M2is turned off, the first power source VDD may be stably supplied to the first output terminal37.

When the eighth transistor M8is turned on, the fourth node N4and the first input terminal33are electrically coupled to each other. Here, since the first clock signal CLK1is supplied to the first input terminal33, the fourth node N4receives a low voltage.

When the fifth transistor M5is turned on, the start signal is supplied to the third node N3. When the start signal is supplied to the third node N3, the sixth transistor M6is turned on. When the sixth transistor M6is turned on, the sixth node N6and the second input terminal34are electrically coupled to each other. Here, since the second clock signal CLK2is not supplied to the second input terminal34, the sixth node N6maintains a high voltage so that a sampling signal is not supplied to the second output terminal38. On the other hand, since the sixth transistor M6is turned on, the voltage corresponding to the turning on of the sixth transistor M6is charged at the third capacitor C3.

When the ninth transistor M9is turned on, the voltage of the second power source VSS is supplied to the fourth node N4. When the second power source VSS is supplied to the fourth node N4, the eleventh transistor M11is turned on. When the eleventh transistor M11is turned on, the fifth node N5and the third input terminal35are electrically coupled to each other. Here, since the third clock signal CLK3is not supplied to the third input terminal35, the fifth node N5maintains a high voltage. On the other hand, since the eleventh transistor M11is turned on, the voltage corresponding to the turning on of the eleventh transistor is charged at the fifth capacitor C5.

Then, the supply of the first clock signal CLK1to the first input terminal33is stopped. When the supply of the first clock signal CLK1is stopped, the third transistor M3, the fifth transistor M5, and the ninth transistor M9are turned off.

When the third transistor M3is turned off, the fourth input terminal36and the first node N1are electrically isolated from each other. Here, the first node N1maintains a low voltage by the second capacitor C2. Therefore, the first transistor M1maintains a turn on state so that the voltage of the first power source VDD is output to the first output terminal37. Since the fourth transistor M4maintains a turn on state by the voltage of the second capacitor C2, the second transistor M2stably maintains a turn off state.

When the fifth transistor M5is turned off, the fourth input terminal36and the third node N3are electrically isolated from each other. Here, the sixth transistor M6maintains a turn on state to correspond to the voltage charged at the third capacitor C3so that the second output terminal38maintains a previous voltage.

When the ninth transistor M9is turned off, the fourth node N4and the second power source VSS are electrically isolated from each other. Here, since the eighth transistor M8maintains a turned on state to correspond to the voltage applied to the first node N1, the fourth node N4and the first input terminal33are electrically coupled to each other. Therefore, the voltage of the fourth node N4increases to the voltage supplied to the first input terminal33(e.g., the voltage of a high signal). When the fourth node N4receives the voltage of the high signal, the eleventh transistor M11is turned off. Here, the fifth capacitor C5is charged with the voltage corresponding to the turning off of the eleventh transistor M11.

Then, the third clock signal CLK3is supplied to the third input terminal35. When the third clock signal CLK3is supplied, the tenth transistor M10is turned on. When the tenth transistor M10is turned on, the second node N2and the fifth node N5are electrically coupled to each other. At this time, since the fourth transistor M4maintains a turned on state and the eleventh transistor M11maintains a turned off state, the second node N2maintains the voltage of the first power source VDD.

After the third clock signal CLK3is supplied, the second clock signal CLK2is supplied to the second input terminal34in the next horizontal period. Here, since the sixth transistor M6is set in a turn on state, the second clock signal CLK2is supplied to the sixth node N6. The second clock signal CLK2supplied to the sixth node N6as a sampling signal is supplied to the next stage via the second output terminal38. On the other hand, when the second clock signal CLK2is supplied to the sixth node N6, the voltage of the third node N3is reduced by the coupling of the third capacitor C3. Therefore, the sixth transistor M6stably maintains a turned on state.

Additionally, the second clock signal CLK2supplied to the second input terminal34is transmitted to the second node N2by the coupling of the first capacitor C1. Here, since the second node N2receives the first power source VDD, the voltage of the first power source VDD is maintained without a change in a voltage.

Then, the third clock signal CLK3is supplied to the third input terminal35. When the third clock signal CLK3is supplied, the tenth transistor M10is turned on. When the tenth transistor M10is turned on, the second node N2and the fifth node N5are electrically coupled to each other. Here, since the fourth transistor M4maintains a turned on state and the eleventh transistor M11maintains a turned off state, the second node N2maintains the voltage of the first power source VDD.

After the third clock signal CLK3is supplied, the supply of the start signal FLM is stopped (e.g., a high voltage) in the next horizontal period, and the first clock signal CLK1is supplied to the first input terminal33.

When the first clock signal CLK1is supplied, the third transistor M3, the fifth transistor M5, and the ninth transistor M9are turned on.

When the third transistor M3is turned on, the first node N1and the fourth input terminal36are electrically coupled to each other. Here, since a high voltage is supplied to the first node N1, the first transistor M1, the fourth transistor M4, and the eighth transistor M8are turned off. When the first transistor M1is turned off, the first output terminal37is set in a floating state. In this case, the first output terminal37maintains the high voltage that is an output signal of a previous period.

Since the emission control signal supplied to the emission control line E1is supplied to the pixels50, charging is performed by the capacitors of the pixels. Therefore, although the first output terminal37is set in a floating state, the output voltage of a previous period is maintained by the parasitic capacitors of the pixels50and the emission control line.

When the fifth transistor M5is turned on, a high voltage is supplied to the third node N3so that the sixth transistor M6is turned off. When the sixth transistor M6is turned off, the sixth node N6and the second input terminal34are electrically isolated from each other. Here, the third capacitor C3is charged with the voltage corresponding to the turning off of the sixth transistor M6.

When the ninth transistor M9is turned on, the fourth node N4and the second power source VSS are electrically coupled to each other. Here, the fourth node N4receives the voltage of the second power source VSS so that the eleventh transistor M11is turned on. When the eleventh transistor M1is turned on, the fifth node N5and the third input terminal35are electrically coupled to each other. On the other hand, the voltage corresponding to the turning on of the eleventh transistor M11is stored at the fifth capacitor C5.

Then, the third clock signal CLK3is supplied to the third input terminal35. When the third clock signal CLK3is supplied, the tenth transistor M10is turned on. When the tenth transistor M10is turned on, the second node N2and the third input terminal35are electrically coupled to each other via the fifth node N5. Here, the third clock signal CLK3(e.g., a low voltage) is supplied to the second node N2. When the low voltage is supplied to the second node N2, the second transistor M2is turned on so that the voltage of the second power source VSS is output to the first output terminal37. In this case, the supply of the emission control signal to the emission control line E1is stopped. When the second power source VSS is supplied to the first output terminal37, the seventh transistor M7is turned on. When the seventh transistor M7is turned on, the voltage of the first power source VDD is supplied to the sixth node N6.

According to an embodiment of the present invention, the third clock signal CLK3may be set as a voltage lower than the second power source VSS so that the second transistor M2may be stably turned on. Then, the stage321outputs the voltage of the first power source VDD to the first output terminal37until the next start signal FLM is supplied.

Additionally, according to embodiments of the present invention, whenever the second clock signal CLK2is supplied, the voltage of the second node N2is reduced by the coupling of the first capacitor C1. Therefore, the voltage of the second node N2stably maintains a low voltage so that the voltage of the second power source VSS may be stably output to the first output terminal37.

On the other hand, a sampling signal is supplied to the next stage in synchronization with the second clock signal CLK2(In the next stage, the second clock signal CLK2is supplied to the first input terminal). In this case, the next stage stably outputs the emission control signal using the sampling signal.

Additionally, inFIG. 4, it is illustrated that one sampling signal is generated to correspond to the start signal FLM. However, the present invention is not limited to the above. For example, when the start signal FLM overlaps two first clock signals CLK1, two sampling signals are supplied to the next stage. Therefore, according to embodiments of the present invention, the width of the start signal FLM is controlled so that the width of the emission control signal may be freely controlled.

FIG. 5is a circuit diagram illustrating a second embodiment of the stage ofFIG. 2. InFIG. 5, the same elements as those ofFIG. 3are denoted by the same reference numerals and detailed description thereof will be omitted.

Referring toFIG. 5, the stage321, according to the second embodiment of the present invention, further includes a twelfth transistor M12and a thirteenth transistor M13for bidirectional driving.

The twelfth transistor M12is coupled between the fourth input terminal36and the third transistor M3. The gate electrode of the twelfth transistor M12receives a first control signal CS1. The twelfth transistor M12is turned on when the first control signal CS1is supplied.

The thirteenth transistor M13is coupled between a fifth input terminal39and the fifth transistor M5(or a first controller100). Then, the gate electrode of the thirteenth transistor M13receives a second control signal CS2. The thirteenth transistor M13is turned on when the second control signal CS2is supplied. The fifth input terminal39receives the start signal or the sampling signal of the next stage.

Here, the first control signal CS1and the second control signal CS2are supplied at different times (e.g., not overlapped with each other). For example, when the emission control signals are supplied in a first direction (from top to bottom of a panel), the first control signal CS1is supplied so that the twelfth transistor M12is turned on and so that the thirteenth transistor M13maintains a turned off state. When the emission control signals are supplied in a second direction (from bottom to top of the panel), the second control signal CS2is supplied so that the thirteenth transistor M13is turned on and so that the twelfth transistor M12maintains a turned off state.

The stage321, according to the second embodiment of the present invention, further includes the twelfth transistor M12and the thirteenth transistor M13for bidirectional driving, and the operation processes are substantially the same as the first embodiment illustrated inFIG. 3.

FIG. 6is a circuit diagram illustrating a third embodiment of the stage ofFIG. 2. InFIG. 6, the same elements as those ofFIG. 3are denoted by the same reference numerals, and detailed description thereof will be omitted.

Referring toFIG. 6, the stage321, according to the third embodiment of the present invention, further includes a fourteenth transistor M14coupled between the first node N1and the second power source VSS. The fourteenth transistor M14is turned on to supply the voltage of the second power source VSS to the first node N1when a reset signal (Reset) is supplied to the gate of the fourteenth transistor M14. When the second power source VSS is supplied to the first node N1, the first transistor M1is turned on so that the voltage of the first power source VDD is supplied to the first output terminal37.

Here, the reset signal (Reset) is commonly supplied to all of the stages321to32nwhen a power source is turned on and/or off. As described above, when the reset signal (Reset) is supplied and the power source is turned on and/or off, the emission control signals are supplied to the emission control lines E1to En so that the pixels50are set in a non-emission state. That is, according to the third embodiment of the present invention, it is possible to prevent over-current from flowing or unnecessary light from being generated when the power source is turned on and/or off using the reset signal.

Additionally, inFIG. 2, the third clock signal CLK3is supplied to all of the stages321to32n. However, the present invention is not limited to the above. For example, the third clock signal CLK3may be supplied to even and odd stages via different lines. Then, the load of the third clock signal CLK3is minimized or reduced so that the stability of driving the stages may be improved.