Phase locked loop circuit and a method in the phase locked loop circuit

A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.

CLAIM OF PRIORITY

This application claims priority to Chinese Application No. 201310170137.7 entitled “A PHASE LOCKED LOOP CIRCUIT AND A METHOD IN THE PHASE LOCKED LOOP CIRCUIT”, filed on May 8, 2013 by Beken Corporation, which is incorporated herein by reference.

TECHNICAL FIELD

The present application relates to electrostatic circuits, and more particularly but not exclusive to a phase locked loop circuit and a method in the phase locked loop circuit.

BACKGROUND

A phase locked loop or phase-locked loop (PLL) is a control system that generates an output signal, also called a F_N clock, whose phase is related to the phase of an input “reference” signal, also called a F_ref clock.

After a PLL is powered on, the F_ref clock has initial phase error with the F_N clock, which ranges from 0 to 2π. The PLL can only start a locking operation after the phase error has been cancelled.

SUMMARY OF THE INVENTION

In an embodiment, there is provided a phase locked loop (PLL) circuit, A PLL circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a voltage controlled oscillator (VCO), a frequency divider (FD) and a reset module. The PFD receives a first and a second input signals, and outputs a first and a second adjustment parameters according to phase and frequency difference between the first and the second input signal. The CP is coupled to the PFD, generates a current according to the first and the second adjustment parameters. The LPF is coupled to the CP, and generates a voltage according to the current. The VCO is coupled to the LPF, and generates an oscillation frequency according to the voltage. The FD receives and divides the oscillation frequency, and generates the second input signal. The reset module generates a reset signal to feed to the FD, wherein the reset module receives the first signal.

In another embodiment, there is provided a method in a phase locked loop (PLL) circuit, comprising: receiving, by a phase frequency detector, a first input signal and a second input signal, and to output a first adjustment parameter and a second adjustment parameter according to phase and frequency difference between the first input signal and the second input signal; generating, by a charge pump, a current according to the first adjustment parameter and the second adjustment parameters; generating, by a low pass filter, a voltage according to the current; generating, by a voltage controlled oscillator (VCO), an oscillation frequency according to the voltage; receiving the oscillation frequency, dividing the oscillation frequency, generating the second input signal using the divided oscillation frequency, by a frequency divider; and generating, by a reset module, a reset signal to feed to the frequency divider.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

FIG. 1shows a schematic diagram of a phase locked loop according to an embodiment of the invention.

As shown inFIG. 1, the phase locked loop (PLL) circuit10comprises a reset module (100), a phase frequency detector (PFD)105, a charge pump (CP)110, a low pass filter (LPF)115, a voltage controlled oscillator (VCO)120, and a frequency divider (FD)125.

The phase frequency detector105is configured to receive a first input signal F_ref and a second input signal F_N, and to output a first adjustment parameter, as marked as UP (up) inFIG. 1, and a second adjustment parameter, as marked as DN (down) inFIG. 1, according to a phase and frequency difference between the first input signal F_ref and the second input signal F_N. The first input signal comprises the F_ref clock signal (marked as F_ref inFIG. 1), and the second input signal comprises the F_N clock signal (marked as F_N inFIG. 1). The difference between the first adjustment parameter UP and the second adjustment parameter DN is proportional to the phase and frequency difference between the first input signal F_ref and the second input signal F_N.

The charge pump110is coupled to the phase frequency detector105, and is configured to generate a current according to the first adjustment parameter UP and the second adjustment parameter DN.

The low pass filter115is coupled to the charge pump110. The low pass filter115is configured to generate a voltage according to the current.

The voltage controlled oscillator120is coupled to the low pass filter115. The voltage controlled oscillator120is configured to generate an oscillation frequency according to the voltage. The voltage controlled oscillator120may comprise a LC oscillator.

The frequency divider125is configured to receive the oscillation frequency, to divide the oscillation frequency by N, and to generate the second input signal F_N using the divided oscillation frequency, therefore the second input signal F_N equals the output frequency of the voltage controlled oscillator120divided by N.

The PLL circuit10uses a negative feedback loop. Assume that initially the second input signal F_N is at nearly the same frequency as the first input signal F_ref. Further assume that the output frequency of voltage controlled oscillator120is inversely proportional to the voltage inputted into the voltage controlled oscillator120, as illustrated inFIG. 2. If the phase of second input signal F_N falls behind that of the first input signal F_ref, as illustrated inFIG. 3A, the phase frequency detector105changes the control voltage of the voltage controlled oscillator120, for example outputs the first adjustment parameter UP with a pulse bandwidth smaller than the second adjustment parameter DN, so that the voltage controlled oscillator120speeds up and the second input signal F_N speeds up accordingly, and the second input signal F_N approaches the first input signal F_ref. Likewise, if the phase of the second input signal F_N creeps ahead of that of the first input signal F_ref, as illustrated inFIG. 3B, the phase detector105changes the control voltage to the voltage controlled oscillator120, for example outputs the first adjustment parameter UP with a pulse bandwidth larger than the second adjustment parameter DN, so that the second input signal F_N slows down accordingly, and the second input signal F_N approaches the first input signal F_ref:

The reset module100is configured to generate a reset signal to feed to the frequency divider125, wherein the reset module100is configured to receive the first signal F_ref.

More detailed discussion of the reset module100will be given below with reference toFIGS. 4,4A and4B.

FIG. 4shows a circuit diagram of the reset module according to an embodiment of the invention.

InFIG. 4, the reset module40comprises a first inverter400, a first D-type flip flop405, a second D-type flip flop410, a third D-type flip flop415, and an Exclusive-OR(XOR) gate420. The first inverter400receives a third signal PLLpwd (PLL power down). A D port of the first D-type flip flop405is connected to an output port of the first inverter400, and a Q port of the first D-type flip flop405is connected to a D port of the second D-type flip flop410. A Q port of the second D-type flip flop410is connected to both a first input port of the XOR gate420and a D port of the third D-type flip flop415. A Q port of the third D-type flip flop415is connected to a second input port of the XOR gate420. Clock ports of the first, second and third D-type flip flops405,410and415all receive the first input signal F_ref, such that the XOR gate420outputs a reset pulse.

Those skilled in the art can appreciate that the two input ports of XOR gate420respectively receive the output from the second D-type flip flop410and the third D-type flip flop415. The XOR gate420outputs “1” when the output of the second D-type flip flop410is “1” and the output of the third D-type flip flop415is “0”, or when the output of the second D-type flip flop410is “0” and the output of the third D-type flip flop415is “1”. The XOR gate420outputs “0” when the output of the second D-type flip flop410and the output of the third D-type flip flop415are the same. Since the output of the third D-type flip flop415is a delayed version of the second D-type flip flop410, that is to say, a pulse is generated during the time when the first D-type flip flop410is “1” and the output of the second D-type flip flop415is “0”. Therefore, the duration of the pulse generated by the XOR gate420is the same as delay time for a D-type flip flop. Here, “0” represents logic low voltage, for example, ground, and “1” represents high voltage, for example Vcc.

FIG. 4Ashows another embodiment of the reset module40A. InFIG. 4A, same reference numbers refer to the same circuit elements as inFIG. 4. InFIG. 4A, the reset module40A further comprises an AND gate425. A first input port of the AND gate425is connected to both the Q port of the second D-type flip flop410and the first input port of the XOR gate420, a second input port of the AND gate425is connected to the output port of the XOR gate420, and the AND gate425outputs the reset signal.

FIG. 4Bshows another embodiment of the reset module40B. InFIG. 4B, same reference numbers refer to the same circuit elements as inFIG. 4. InFIG. 4B, the reset module40B further comprises at least one fourth D-type flip flop430serially connected between the Q port of the first D-type flip flop405and the D port of the second D-type flip flop410.FIG. 4Bshows one fourth D-type flip flop430between the first D-type flip flop405and the second D-type flip flop410. Those skilled in the art can appreciate that a plurality of additional D-type flip flops can be arranged serially between the first D-type flip flop405and the second D-type flip flop410.

FIG. 5shows a block diagram of part of the phase locked loop50, showing the connection relationship among the frequency divider, the reset signal and the voltage control oscillator.

As shown inFIG. 5, the frequency divider125further comprises a 2-module prescaler500and a counter module505. The counter module505further comprises a counter A505A and a counter B505B. The phase locked loop circuit50further comprises a fifth D-type flip flop510, a sixth D-type flip flop515, a second inverter520and a third inverter525.

The 2-module prescaler500is connected to a first input port of the counter module505. The 2-module prescaler500is configured to divide the frequency of an input signal in the frequency division ratio of 1/K or 1/(K+1) according to the contents of a control signal supplied to the control terminal of the 2-module prescaler500. In other words, the frequency Fvco of a signal delivered from the voltage controlled oscillator120is divided by the prescaler505in the ratio corresponding to the contents of a control signal. Where, in this case, the control terminal of the prescaler500is supplied with a high level signal, then the prescaler divides the frequency of an input signal in the ratio of 1/(K+1), for example 1/9. Where the control terminal of the presccaler500receives a low level signal, then the prescaler500divides the frequency of an input signal in the ratio of 1/K, for example, ⅛. Alternatively, the 2-module prescaler comprises a ⅘ divider, or the 2-module prescaler comprises a ⅔ divider.

The counter505is used to control the prescaler500. The counter505comprises a counter A505A and a counter B505B. Counter A is able to divide input frequency by a predetermined number A, and counter B is able to divide input frequency by a predetermined number B. The output frequency of the signal of the frequency divider125equals

F=FvcoAK+B.
For example, the input Fvco equals 2.4 GHz, the prescaler has a K which equals 8. A equals 300, and B equals 0. Therefore the output frequency equals 1 MHz.

A clock port of a fifth D-type flip flop510receives the reset signal (rst). A D port of the fifth D-type flip flop510is configured to receive a negative supply voltage (Vss). A Q port of the fifth D-type flip flop510is connected to a negative set port (SN) of a sixth D-type flip flop515. A Q port of the sixth D-type flip flop515is connected to an input port of the second inverter520. An output port of the second inverter520is connected to both the third inverter525and a negative set port (SN) of the fifth D-type flip flop510. The third inverter525is connected to a second input port of the counter module505. A first output port of the counter module505is connected to a D port of the sixth D-type flip flop515. A second output port of the counter module505is fed back to the 2-module prescaler500. The 2-module prescaler500is further connected to a clock port of the sixth D-type flip flop515.

When the negative set port (SN) of the fifth D-type flip flop510is set to “0”, it means that whatever the value of D port of the fifth D-type flip flop510is, Q port of the fifth D-type flip flop510always outputs “1”. When negative set port (SN) of the fifth D-type flip flop510is set to “1”, then the fifth D-type flip flop510captures the value of the D port of the fifth D-type flip flop510at a definite portion of the clock cycle (such as the rising edge of the clock), and the captured value becomes the Q output of the fifth D-type flip flop510.

FIG. 6shows a sketch illustrating order of the reset signal and the second input signal F_N according to an embodiment of the present invention.

Note that since the reset signal is generated from the first input signal F_ref, the high voltage of the reset signal always align with the first input signal F_ref. If the reset signal is generated at the time when the second input signal F_N is at high “1”, as shown inFIG. 6, then the negative set port (SN) of fifth D-type flip flop510is “0”, which means the reset signal does not work, and the circuit will not be reset. The duty cycle of the signal F_N is small. The width of high level voltage of F_N is 8/Fvco, for example. If Fvco equals 2400 MHz, then the width of high level voltage of F_N is 3.33 ns. F_ref=1M. Therefore, the maximum phase error between the first input signal F_N and the second input signal F_ref is

If the initial frequency of VCO is Fvco+ΔF, or Fvco-ΔF, wherein Fvco represents the locked frequency, and Fvco=N×Fref, then the frequency of F_N is

When the initial frequency of VCO equals Fvco+ΔF, in order to compensate a 2π phase duration, there are k F_N periods and k−1 F_ref periods, that is

k=N×Fref+Δ⁢⁢FΔ⁢⁢F.
In order to compensate a 2π phase error, the following time is needed:

When the initial frequency of VCO is Fvco-ΔF, in order to compensate a 2π phase duration, there are k−1 F_N period and k F_ref period, that is

k=N×FrefΔ⁢⁢F.
In order to compensate a 2π phase error, the following time is needed:

k×1Fref=NΔ⁢⁢F
Therefore, the time needed for compensating a 2π phase error equals

In order to cancel the maximum phase error,

3.331000×2⁢⁢π,
between the first input signal F_N and the second input signal F_ref, a time of

FIG. 7shows a sketch illustrating order of the reset signal, second input signal F_N and Q output of the fifth D-type flip flop510Q1, according to another embodiment of the present invention.

If the reset signal is generated when the second input signal F_N is at low “0”, as shown inFIG. 7, then the negative set port (SN) of fifth D-type flip flop510is “1”, which means the reset signal works. The Q port (Q1) of the fifth D-type flip flop510outputs a low voltage, which will set the second input signal F_N to a high voltage, and the high voltage of F_N will set the SN of the fifth D-type flip flop, that is the high voltage of F_N feed a “0” to the SN of the fifth D-type flip flop, so that the SN of the fifth D-type flip flop is set to “0”. When the SN of the fifth D-type flip flop is set to “0”, the Q port (Q1) of the fifth D-type flip flop510is set to “1”. Therefore, a narrow low voltage pulse occurs in the signal output by the Q port (Q1) of the fifth D-type flip flop. The second input signal F_N will reset the counter505, and trigger the counter505to restart countering, therefore the frequency divider505resume the denominator of AK+B. In this situation, the phase difference between the first input signal F_ref and the second input signal F_N equals the delay of gate, which can be neglected.

FIG. 8shows a method in a phase locked loop (PLL) circuit according to an embodiment of the present invention. The method80comprises receiving (800), by a phase frequency detector, a first input signal and a second input signal. The method80further comprises outputting (805) a first adjustment parameter and a second adjustment parameter according to phase and frequency difference between the first input signal and the second input signal. The method80then generates (810), by a charge pump, a current according to the first adjustment parameter and the second adjustment parameters. The method80then generates (815), by a low pass filter, a voltage according to the current. The method then generates (820), by a voltage controlled oscillator (VCO), an oscillation frequency according to the voltage. The method80then receives (825) the oscillation frequency and divides the oscillation frequency. The method80then generates (830), by a frequency divider, the second input signal using the divided oscillation frequency. The method80then generates (835), by a reset module, a reset signal to feed to the frequency divider.

Alternatively, the first signal comprises a reference signal.

Alternatively, the third signal comprises a phase locked loop power down signal.

It should be appreciated by those skilled in the art that components from different embodiments may be combined to yield another technical solution. This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.