Storage system and storage control apparatus

A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

TECHNICAL FIELD

The present invention relates to technology for computing a redundancy code stored in a storage device.

BACKGROUND ART

There is known a storage system that has a plurality of disk devices and a storage controller for controlling these disk devices, wherein each of the disk devices functions to create a parity (Patent Literature 1, for example). In this storage system, the storage controller transmits updated data (new data) to a disk device storing data before update (old data). From the old data and the new data, the disk device creates an intermediate value (intermediate parity) used for creating a new parity, writes the new data into the disk thereof, and empties the storage region in which the old data was stored, to have a blank region. The disk device transmits this intermediate parity to the storage controller. The storage controller stores the intermediate parity in a cache memory and nonvolatile memory of the storage controller. The storage controller then reads the intermediate parity from the cache memory and transmits the intermediate parity to a disk device storing an old parity. This disk device creates a new parity from the received intermediate parity and the old parity, writes the new parity into the disk thereof, and empties the storage region in which the old parity was stored, to have a blank region.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

In Patent Literature 1, the process for storing the intermediate parity in both the cache memory and the nonvolatile memory increases the load imposed on the storage controller. This makes the performance of the storage controller a bottleneck, deteriorating the performance of the storage controller. However, storing the intermediate parity in either the cache memory or the nonvolatile memory can cause data loss in case of a system fault.

Solution to Problem

A storage system as one aspect of the present invention has: a plurality of storage devices, each of which has a plurality of storage media and a device controller for controlling the plurality of storage media and has a RAID group configured by the plurality of storage media; and a system controller that has a processor, a buffer memory coupled to the plurality of storage devices and the processor by a predetermined communication network, and a cache memory coupled to the processor and the buffer memory by the predetermined communication network.

The processor stores first data, which is related to a write request from a host computer, in the cache memory, specifies from the plurality of storage devices a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller of the first storage device transmits the first data and second data based on the data before update, from the first storage device to the system controller.

The processor stores the second data in the buffer memory, specifies a second storage device from the plurality of storage devices, and transfers the stored second data to the specified second storage device. The processor also manages a process stage information item indicating a stage of a process performed on the write request.

DESCRIPTION OF EMBODIMENTS

Several embodiments of the present invention are now described hereinafter.

In the following description, various types of information are expressed by “*** table,” but the various types of information may be expressed by data structures other than tables. In order to describe that the various types of information are independent of the data structures, “*** table” can be referred to as “*** information.”

Furthermore, in the following description, each process is described using “program” as the subject of the sentence; however, the subject of the sentence describing each process may be “processor”, because a program is executed by a processor (e.g., a CPU (Central Processing Unit)), to perform a certain process by appropriately using a storage resource (e.g., memory) and/or a communication interface device (e.g., a communication port). The process that is described using “program” as the subject may be performed by a storage system, a controller contained in the storage system, an MPPK contained in the controller, which is described hereinafter, or an MP (Microprocessor) inside the MPPK. The processor may include a hardware circuit that performs part of or the entire process performed by the processor. The computer program may be installed from a program source into each computer. The program source may be, for example, a program distribution server or a storage medium.

Configuration of Storage System

A configuration of a storage system is described hereinafter as an example of the application of the present invention.

FIG. 1shows a configuration of a storage system. The storage system10has a controller100, and a storage unit200coupled to the controller100. In the diagram, the controller100and the storage unit200are coupled to each other by a BE-I/F (Back End Inter/Face)141.

The storage unit200has a plurality of (or one) FMPKs (Flash Memory PacKage)144. A physical storage medium adopted in the storage unit200is a memory drive (e.g., an SSD (Solid State Drive)) that has a nonvolatile semiconductor memory (e.g., a flash memory). One or a plurality of RAID (Redundant Arrays of Inexpensive (or Independent) Disks) groups145are configured by the plurality of FMPKs144. In the present embodiment, a RAID group of RAID level 5 is formed by the controller100using the plurality of FMPKs144. Furthermore, in the present embodiment, the FMPKs included in a single RAID group are coupled to different buses. In the case where the RAID group is configured from the plurality of FMPKs coupled to a single bus, if a fault occurs in the bus, none of the FMPKs becomes accessible; therefore, the data cannot be recovered. However, the RAID group may be configured by the plurality of FMPKs coupled to the same bus.

One or a plurality of host computers30and a management computer20are coupled to the controller100. The controller100and the host computer30are coupled to each other by a predetermined communication network1(e.g., a SAN (Storage Area Network)). The controller100and the management computer20are coupled to each other by a predetermined communication network150(including e.g., a switch or a LAN (Local Area Network)).

The controller100is composed of various packages (PK) such as an FEPK (Front End Package)110, an MPPK (Microprocessor Package)120, a CMPK (Cache Memory Package)130, and a BEPK (Back End Package)140. In the example shown inFIG. 1, a plurality of the various packages (PK) are multiplexed, but at least one type of PK of the plurality of types of PKs may exist in the singular. The FEPK110, the MPPK120, the CMPK (Cache Memory Package)130, and the BEPK140are coupled to one another by the predetermined communication network (including e.g., a switch)150.

The FEPK110has one or more FE-IFs (Front End Inter/Faces)111, a transfer circuit112, and a buffer113. The FE-I/F111is an interface device communicating with a communication device that exists at a front end of the host computer30or the like. For example, the FE-I/F111receives an I/O request (a write request or a read request) from the host computer30, temporarily stores the received I/O request in the buffer113, and transfers the I/O request to the MPPK120via the transfer circuit112. The FEPK110may have a control device such as a CPU. The buffer113is, for example, a volatile semiconductor memory. The buffer113may also be a nonvolatile semiconductor memory.

The BEPK140has one or more BE-I/Fs141, a transfer circuit142, and a buffer143. The BE-I/F141is an interface device communicating with the FMPKs144. For example, the BE-I/F141reads data from the FMPKs144and temporarily stores the data in the buffer143. The transfer circuit142sends to the CMPK130the data written from the FMPKs144to the buffer143. The transfer circuit142also writes the data read from the CMPK130, into the buffer143. The BE-I/F141sends the data written to the buffer143to the FMPKs144. The BEPK140may have a control device such as a CPU. The BEPK140may also be an interface such as a disk adapter between a control device and a storage device. The buffer143is, for example, a volatile semiconductor memory. The buffer143may also be a nonvolatile semiconductor memory.

The MPPK120has a plurality of (or one) microprocessors (“MP,” hereinafter)121, and one or a plurality of LMs (Local Memories)122coupled to the MPs121by an internal path123. The MPs120process the I/O request sent from the FE-I/F111. Each LM122stores a necessary portion of management information stored in an SM (Shared Memory)132or stores a computer program executed by the MPs121. In the system configuration according to the present embodiment, the MPPK120is coupled to the FEPK110, the CMPK130, and the BEPK140by internal networks thereof. Therefore, the MPPK120can control transfer of data with the PKs (the MPPK120, FEPK110, CMPK130, and BEPK140), and storage/deletion of data transmitted to the buffer113of the FEPK110, the CM (Cache Memory)131and SM132of the CMPK130, and the buffer143of the BEPK140.

The CMPK130has a CM131and the SM132. The CM131and the SM132are, for example, volatile semiconductor memories. At least either the CM131or the SM132may be a nonvolatile memory.

The CM131has a storage region for temporarily storing I/O target data for the storage medium. The SM132has a storage region in which are stored various pieces of management information (various pieces of information used in operations performed by the storage system) and computer programs.

The buffer143of the BEPK140stores data read from the CM131and transmitted to the FMPK144. Generally, a buffer has a smaller capacity than a CM. The buffer keeps data related to one certain process (e.g., an I/O process) until the completion of the process. In other words, the data stored in the buffer is deleted once a series of processes are completed. On the other hand, data stored in the CM basically is not deleted even after the completion of a certain I/O process and remains on the CM as long as the CM has enough capacity. Furthermore, the data is reused in another I/O process. Data related to an I/O process is stored in the CM; however, the data is deleted asynchronously with the I/O process. When deleting the data stored in the CM, for example, the data may be deleted starting with the chronologically oldest data that has been stored for the longest period of time, or with the data having the oldest last access time. Regions in the CM and the data stored in the CM are used by the MPPK, FEPK and BEPK; therefore a great amount of load is imposed on the CM.

At least one type of an FC (Fibre Channel), a SAS (Serial Attached SCSI) or a SATA (Serial ATA) may be the interfaces of these components.

The management computer20is, for example, a computer with a display device and an input device. For instance, the management computer20transmits a command for establishing various settings on the storage system, in response to an operation of an SVP (Service Processor) by an administrator. The SVP updates the management information stored in the SM132and sets information in the SM132, in response to a command from the administrator. The management information includes region information indicating a region within the CM131for storing data, and process stage information indicating one of a plurality of states of the system during a write process.

FIG. 2shows a configuration example of one of the FMPKs144. The FMPK144has communication interface devices, storage devices, and a control device coupled to the communication interface devices and the storage devices. The communication interface devices are, for example, a port1441coupled to the communication network, and a disk I/F1446coupled to FMs1443. An FM controller1447includes the port1441, a logical operation circuit1442, a CPU1444, a memory1445, and the disk I/F1446.

The storage devices are, for example, the memory1445and the FMs (Flash Memories)1443. The control device is, for example, the CPU1444. In addition to such a processor as the CPU1444, the control device may include a dedicated hardware circuit that performs a predetermined process (e.g., compression, expansion, encryption, or decryption). The dedicated hardware circuit is, for example, the logical operation (e.g., XOR (exclusive or) operation) circuit1442that computes a parity or a halfway parity. The logical operation circuit1442is referred to as “XOR circuit1442” in the following description.

The FM1443is a nonvolatile semiconductor memory (typically a NAND-type FM chip) into/from which data is written/read in units of pages or in which data is erased in units of blocks. The FM includes a plurality of blocks, each of which includes a plurality of pages. When rewriting data stored in the FM1443, data cannot be overwritten on a physical region (a physical page) in which the former data is stored. Therefore, when the FM controller1447receives data to be updated to data stored in a certain physical page, the received data is written to another physical page. In so doing, mappings of a logical page address and physical page address are updated. Then, the FM controller1447disables data before update, to obtain disabled data, and manages the updated data as enabled data. A physical page in which the disabled data is stored is erased. A physical page in which the enabled data is stored is associated with a logical page, but the physical page in which the disabled data is stored is not associated with the logical page. In the FM1443, in order to rewrite the data stored in a certain physical region, an erasing process (“block erasing,” hereinafter) needs to be executed on the data in the physical region, in units of blocks. The block subjected to the erasing process can be emptied so that data can be rewritten thereto. The FM1443may not only be a flash memory but also be a WORM memory (e.g., a phase-change memory). The FM controller1447carries out a reclamation process. In the reclamation process, the FM controller1447copies the enabled data stored in a certain block (data associated with the logical page) to another block, disables the enabled data of the copy-source block, and erases this block. The FM controller1447then erases the data in units of blocks.

A pointer table that associates a logical page accessed from the controller100with a physical page inside the FM1443is stored in the memory1445of the FMPK144. The memory1445may temporarily have stored therein data obtained from the controller100. The memory1445is, for example, a volatile semiconductor memory. The memory1445may also be a nonvolatile semiconductor memory.

The RAID group that uses the plurality of FMPKs144is described next.

The controller100creates a RAID group of RAID level 5 from the plurality of FMPKs144(seeFIG. 1). The controller100allocates consecutive regions from address spaces of the created RAID group to a plurality of logical volumes (LU: Logical Units).

The controller100allocates stripe lines extending across the address spaces on the plurality of FMPKs144. The address spaces on the plurality of FMPKs144that configure the stripe lines include an address space having user data stored therein and one address space having parity data stored therein. For example, the controller100allocates an FMPK number to each of the plurality of FMPKs144, and shifts the FMPK numbers allocated to the user data and the parity data, for each stripe line. The controller100writes information related to each RAID group and the LUs into the LMs122.

Hereinafter, of the plurality of FMPKs144allocated to the RAID group, the FMPK144that stores the user data indicated by a write command is referred to as “data FMPK144A”, and the FMPK144that stores the parity data based on the user data is referred to as “parity FMPK144P.”

The storage system10is capable of performing a read-modify-write process in accordance with a write request from the host computer30. The read-modify-write process is a write process for updating only the user data stored in a logical region (block or page) of a single FMPK144in a certain stripe line.

In the following description, user data before update in the logical region designated by the write request is referred to as “old user data,” user data after update in the logical page as “new data,” parity data before update based on the old user data as “old parity,” and parity data after update based on the new user data as “new parity.” In the following description and drawings, the old user data is referred to as “oD,” the new user data as “nD,” the old parity as “oP,” and the new parity as “nP.” In addition, an XOR operator is marked with “+.”

In the read-modify-write process, for example, an intermediate parity is generated by the XOR operation performed on the old data and the new data, and the new parity is generated by the XOR operation performed on the intermediate parity and the old parity. In the following description and drawings, the intermediate parity is referred to as “mP.” In other words, the mP is computed from (oD+nD), and the nP is computed from (oP+mP).

Setting of parity calculation functions of the FMPK144is described next.

In the following embodiments, the FMPK144having the logical operation circuit1442performs parity calculation for generating intermediate parities and parities in accordance with instructions from the controller100. The controller100(any one or more of the MPPK120, the BEPK140, the FEPK110, and the CMPK130) may have a logical operation function. In the case where both the FMPK144and the controller100have logical operation functions, which one of the logical operation functions should be used to calculate the intermediate parities and/or parities may be determined based on a user operation.

In this case, the management computer20may display a menu screen for setting the parity calculation functions of the FMPK144.FIG. 3shows the menu screen. This menu screen G100has an FMPK setting field G101, a logical volume setting field G104, a save button B10, and a cancel button B11.

The FMPK setting field G101is an entry field for setting the availability of an XOR function of the FMPK144. The FMPK setting field G101has a GUI, such as a radio button G102, for inputting an enable state or a disable state of the XOR function of the FMPK144.

The logical volume setting field G104becomes enabled when the XOR function of the FMPK144is set as enable through the FMPK setting field G101. The logical volume setting field G104has a logical volume number display field G105and an XOR function setting field G106. The logical volume number display field G105displays a logical volume number created by the FMPK144. The XOR function setting field G106is an entry field for setting the availability of the XOR function of the FMPK144with respect to the logical volume displayed on the logical volume number display field G105. The XOR function setting field G106is a GUI, such as a radio button, for inputting an enable state or a disable state of the XOR function of the logical volume.

The save button B10is a button for saving the settings input to the menu screen G100and then closing the menu screen G100. The cancel button B10is a button for discarding the settings input to the menu screen G100and then closing the menu screen G100.

In the case where the XOR function of the FMPK144is set as enable for a certain logical volume, the XOR circuit1442of the FMPK144generates the intermediate parity or the new parity during the write process for the logical volume. When the XOR function of the FMPK144is set as disable for a certain logical volume, the controller100generates the intermediate parity or the new parity during the write process for the logical volume.

In this manner, a user can set the availability of the XOR function of the FMPK144and the availability of the XOR function of the FMPK144for each logical volume. According to the above description, the storage regions based on the RAID group are allocated beforehand to all of the regions of the logical volume. However, a logical volume according to thin provisioning (virtual volume) may be applied to the logical volume. Storage regions for storing data are not allocated beforehand to the virtual volume; however, the storage regions are allocated to the virtual volume in terms of a predetermined unit, in response to a write request with respect to the virtual volume. In the case where the write request is targeted to the regions of the virtual volume to which the storage regions are allocated, the storage regions are not necessarily allocated. The MPPK120of the controller100allocates the storage regions and manages the allocated or unallocated regions.

Write Process According to Embodiment 1

A normal write process is now described hereinafter.

Here is described a case where the storage system10performs the read-modify-write process based on a write command from the host computer30. The read-modify-write process updates data stored at least in a single page within the RAID group created by the FMPKs144.

In this embodiment, in addition to a normal write command and a normal read command, a new data transmission command, an intermediate parity reception command, an intermediate parity transmission command, and a new data commit command are defined as I/O commands sent from the controller100to the FMPK144.

FIG. 4shows a write process according to Embodiment 1. This diagram and the subsequent sequence diagrams show operations by the host computer30, the controller100, the data FMPK144A, and the parity FMPK144P. The operation targets in the upper sequence (operations prior to S2350) in this sequence diagram are the SM132, the MP121, the CM131, the buffer113of the FEPK110, the I/F111of the FEPK110, and the host computer30. The operation targets in the lower sequence (operations after S2350) in the sequence diagram are the SM132, the MP121, the CM131, the buffer143of the BEPK140, the I/F141of the BEPK140, the port1441of the data FMPK144A, the XOR circuit1442of the data FMPK144A, storage media DFa and DFb of the data FMPK144A, the port1441of the parity FMPK144P, the XOR circuit1442of the parity FMPK144P, and storage media PFa and PFb of the parity FMPK144P.

Here, the storage medium DFa of the data FMPK144A represents the memory1445of the FM1443. The storage medium DFb represents a physical page of the FM1443. Furthermore, the storage medium DFa of the data FMPK144A represents the memory1445of the FM1443. The storage medium DFb represents a physical page of the FM1443. The storage medium PFa of the parity FMPK144P represents the memory1445of the parity FM1443. The storage medium PFb represents a physical page inside the parity FM1443.

In this sequence diagram, the number of accesses to each of the operation targets in the write process is shown below an operation (lifeline) of each operation target.

In the data FMPK144A, the DFb is a physical page that stores the old user data before the write process, and DFa is a physical page, different from the DFb, which stores the new user data after the write process. In the parity FMPK144P, the PFb is a physical page, different from the PFa, which stores an old parity before the write process, and the PFa is a physical page that stores the new parity after the write process.

For the purpose of illustration, hereinafter a state of the storage system10in the write process is referred to as a “system state.” Some system states of the storage system10are defined hereinafter. As will be described later, data loss upon the occurrence of a fault can be avoided by changing the process performed upon the occurrence of a fault, in accordance with the system state.

First, the host computer30sends a write command for updating the old user data to the new user data to the controller100of the storage system10.

FIG. 5shows an operation performed by the MP121upon reception of the write command, according to Embodiment 1. The MP121receives the write command from the host computer30(S2110). The MP121then secures a region in the buffer113of the FEPK110to write the new user data thereto (S2120). The MP121then transmits a write preparation completion to the host computer30(S2130).

In the controller100shown inFIGS. 1 and 4, the I/F111of the FEPK110writes the new data obtained from the host computer into a region in the buffer113, secured in S2120.

FIG. 6shows an operation performed by the MP121after the execution of writing into the buffer113of the FEPK110, according to Embodiment 1. Subsequently, the MP121is notified by the host computer30of the completion of writing into the buffer113(S2210). The MP121then secures regions in the CMs131of two CMPKs130to write the new user data thereto (S2220). The MP121then transmits to the FEPK110a write instruction for writing the new user data into the secured regions of the two CMs131(S2230).

In the controller100shown inFIGS. 1 and 4, the transfer circuit112of the FEPK110duplicates the new user data stored in the buffer113and writes the resultant data into the regions of the two CMs131, secured in S2230.

FIG. 7shows an operation performed by the MP121after the execution of writing new user data into the CMs131, according to Embodiment 1. Subsequently, the MP121is notified by the FEPK110of the completion of writing into the two CMs131(S2310). The MP121then writes values (addresses on CM) indicating the regions of the two CMs131, in which the new user data are stored, into region information items stored in two SMs132corresponding to the two CMs131(S2320). The MP121then writes values indicating a pre-parity generation stage into process stage information items stored in the two SM132corresponding to the regions of the two CMs131(S2330). The MP121then registers this pre-parity generation stage in a pre-parity generation queue in the SM132(S2340). Subsequently, the MP121instructs the FEPK110to release the buffer113in which the new user data is stored (S2345). The MP121then notifies the host computer30of a normal end of the write command (S2350). MP121stores the region information items and process step information items on the SM for each write process performed on the new user data. When a fault occurs in an MP, other MPs are enabled to take over a write process by referring to process step information items.

The system state at this moment is called “state 1.”

FIG. 8shows an operation performed by the MP121after a write command response is obtained, according to Embodiment 1. Subsequently, once the MP121detects that there is a registration in the pre-parity generation queue (S2410), the MP121secures a region in the buffer143of the BEPK140to write the new user data thereto (S2420). The MP121then transmits to the BEPK140an instruction for reading the new user data from one of the CMs131(S2430).

In the controller100shown inFIG. 4, the transfer circuit142of the BEPK140reads the new user data from the CM131and writes the new user data into the buffer143.

FIG. 9shows an operation performed by the MP121after the execution of writing into the buffer143of the BEPK140, according to Embodiment 1. Subsequently, once the MP121is notified by the BEPK140of the completion of the reading (S2510), it transmits to the data FMPK144A a new data transmission command for writing the new user data (S2530). This new data transmission command designates a logical page that stores a logical page of the old user data, and accompanies the new user data.

At this moment, the I/F141of the BEPK140reads the new user data from the buffer143and sends the new user data to the data FMPK144A.

Next, in the data FMPK144A shown inFIG. 4, the CPU1444receives the new data transmission command and the new user data via the port1441, writes the new user data into the DFa of the FM1443, and notifies the controller100of a normal end of the new data transmission command. Here, in the FM1443, the new user data and the old user data are stored and kept in a physical page associated with a certain logical page address. The stored new user data and old user data are kept in the physical page, at least until a new parity is generated based on the stored new user data and old data and then written to the physical page.

The system state at this moment is called “state 2.”

FIG. 10shows an operation performed by the MP121after the normal end of the new data transmission command, according to Embodiment 1. Subsequently, once the MP121is notified by the data FMPK144A of the normal end of the new data transmission command (S2610), the MP121secures the storage region of the buffer143of the BEPK140(S2620), and transmits to the data FMPK144A an intermediate parity reception command for causing the data FMPK144A to generate an intermediate parity and acquiring the intermediate parity (S2630). This intermediate parity reception command designates the logical page that stores the logical page of the old user data.

In the data FMPK144A shown inFIG. 4, the CPU1444receives the intermediate parity reception command via the port1441, reads the old user data from the DFb, reads the new user data from the DFa, and sends the old user data and the new user data to the XOR circuit1442. The XOR circuit1442calculates an intermediate parity from the old user data and the new user data. The CPU1444notifies the BEPK140of a normal end of the intermediate parity reception command, through the port1441, and sends the intermediate parity to the controller100.

Next, in the controller100shown inFIG. 4, the I/F141of the BEPK140writes the intermediate parity received from the data FMPK144A, into the storage region of the buffer143, secured in S2620.

FIG. 11shows an operation performed by the MP121after the normal end of the intermediate parity reception command, according to Embodiment 1. Once the MP121is notified by the data FMPK144A of the normal end of the intermediate parity reception command (S3110), the MP121sends to the parity FMPK144P an intermediate parity transmission command for generating and writing a new parity from the intermediate parity (S3120). This intermediate parity transmission command designates the logical page that stores the logical page of the old parity, and accompanies the intermediate parity.

At this moment, the I/F141of the BEPK140reads the intermediate parity from the buffer143and sends the intermediate parity to the parity FMPK144P. Here, the MP121stores the intermediate parity, which is read from the data FMPK144A, into the buffer143of the BEPK140, and then transfers the intermediate parity to the parity FMPK without storing the intermediate parity in the CM131. Because the CM131is not used when transferring the intermediate parity, the load imposed on the CM131can be reduced, improving the performance of the storage system. Moreover, because each FMPK144is coupled to a position in the vicinity of the buffer143, the intermediate parity can be transferred efficiently.

Next, in the parity FMPK144P shown inFIG. 4, the CPU1444receives the intermediate parity transmission command and the intermediate parity via the port1441, reads the old parity from the PFb, and sends the old parity and the intermediate parity to the XOR circuit1442. The XOR circuit1442calculates a new parity from the old parity and the new parity. The CPU1444writes the new parity into the PFa and notifies the controller100of a normal end of the intermediate parity transmission command.

The system state at this moment is called “state 3.”

FIG. 12shows an operation performed by the MP121after the normal end of the intermediate parity transmission command, according to Embodiment 1. Subsequently, once the MP121is notified by the parity FMPK144P of the normal end of the intermediate parity transmission command (S3210), the MP121writes values indicating a post-parity generation stage into the process stage information items stored in the abovementioned two SMs132(S3220). The system state at this moment is called “state 4.” Next, the MP121instructs the BEPK140to release the buffer area in which the intermediate parity is stored (S3225). The MP121then sends a new data commit command to the data FMPK144A (S3230). The new data commit command designates the logical page that stores the logical page of the old user data.

Next, in the data FMPK144A shown inFIG. 4, the CPU1444receives the new data commit command via the port1441, determines the new user data as the user data after update, and notifies the controller100of a normal end of the new data commit command. As a result, the new user data can be accessed based on the normal write command and the normal read command sent from the controller100.

The system state at this moment is called “state 5.”

FIG. 13shows an operation performed by the MP121after the normal end of the new data commit command transmitted to the data FMPK144A, according to Embodiment 1. Once the MP121is notified by the data FMPK144A of the normal end of the new data commit command (S3310), the MP121sends a new data determination to the parity FMPK144P (S3320). This new data commit command designates the logical page that stores the old parity. As a result, the new user data can be accessed based on the normal write command and the normal read command sent from the controller100. The transmission of the new data commit command to the data FMPK144A and the transmission of the new data commit command to the parity FMPK144P may occur in reverse order.

Next, in the parity FMPK144P shown inFIG. 4, the CPU1444receives the new data commit command via the port1441, determines the new parity as a parity after update, and notifies the controller100of a normal end of the new data commit command.

The system state at this moment is called “state 6.”

FIG. 14shows an operation performed by the MP121after the normal end of the new data commit command transmitted to the parity FMPK144P, according to Embodiment 1. Once the MP121is notified by the parity FMPK144P of the normal end of the new data commit command (S3410), the MP121clears the regions of the two SMs132in which the process stage information items are stored (S3420), and ends the write process.

The system state at this moment is called “state 7.”

The above is the write process. The number of accesses to CM is indicated in parentheses below.

In this write process, the new user data from the host computer30is duplicated and written (twice) into the CM131of the CMPK130and is read from the other CM131and then sent from the CM131to the buffer143of the BEPK140. The new user data from the CM131is written to the buffer143and sent from the buffer143to the data FMPK144A. The intermediate parity from the data FMPK144A is written to the buffer143and sent from the buffer143to the parity FMPK144P. Because of this, the number of accesses to the CM131become three times in a single write process, hence the number of accesses to the CM131can be reduced.

As described above, the FMPK144executes the parity calculation and the controller100sends the intermediate parity from the buffer143to the parity FMPK144P without writing the intermediate parity received from the data FMPK144A into the CM131. As a result, the load imposed on the MP and the CM in the storage controller can be reduced, improving the write process performance of the storage system.

For a comparison purpose, now is described a case where the controller100performs the parity calculation on the RAID 5 using the CM131in a conventional write process. In this case, the controller100duplicates the new user data obtained from the host computer, writes the resultant data into the CM (twice), acquires the old user data from the data FMPK144A, writes the old user data into the CM131(once), acquires the old parity from the parity FMPK144P, and writes the old parity into the CM131(once). Furthermore, the controller100reads the old user data, the new user data, and the old parity stored in the CM131(three times) to calculate a new parity, duplicates the new parity and writes the resultant parities into two CMs131(twice), reads the new user data stored in the CM131(once), writes the new user data into the data FMPK144A, reads the new parities stored in the CMs131(once), and writes the new parities into the parity FMPK144P. In this case, the number of accesses to the CM131in a single write process is eleven.

In this embodiment, the intermediate parity can be transferred efficiently by using the buffer143of the BEPK140located in the vicinity of the FMPK144.

Furthermore, the RAID 5 is configured by the plurality of FMPKs144coupled to the different buses, in order to maintain a redundant configuration upon system fault. Allowing the plurality of FMPKs144to share the buffer of the BEPK140can maintain the redundant configuration and transfer the intermediate parity using the buffer. According to this embodiment, the reliability of the storage system10can be improved by storing the new user data in two CMPKs130and storing the process stage information items corresponding to the new user data into the SMs132.

The CM131having the new user data stored therein and the SM132having the process stage information corresponding to the new user data stored therein may be provided in the packages different from each other. Furthermore, the pointer table of the FMPK144is stored in the memory1445but may be stored in the FM1443.

Transition Write Process according to Embodiment 1

A transition write process that is performed upon an occurrence of an MP fault is described hereinafter.

The takeover write process is a process that occurs when a fault occurs in the MP121during the write process. In this case, the other MPs121free of faults perform the transition write process that takes over the write process. During the write process, the MPs121free of faults can recognize the process stage information items, since the process stage information items are stored in the two SMs132, and perform an appropriate transition write process in accordance with the process stage information items. If the process stage information items are lost, data loss occurs. Data loss is a situation where write data of the host computer are lost and therefore cannot be recovered. Data loss is not a favorable condition for the storage system. Therefore, the process stage information items are duplicated and stored. Moreover, a transition write process described hereinafter is executed in order to avoid data loss caused upon the occurrence of an MP fault.

The transition write process is now described.FIG. 15shows an operation performed by the MP121upon the occurrence of the MP fault, according to Embodiment 1. First, the MP121of the MPPK120free of faults detects the occurrence of a fault in the other MPPK120(S3610). The MP121then selects one of the SMs132that is not searched from among a plurality of SMs132(S3620), searches this SM132, and determines whether or not the pre-parity generation stage of the process stage information items is detected from the searched SM132(S3630).

When the pre-parity generation stage is detected (S3630, YES), the MP121registers the pre-parity generation stage in the pre-parity generation queue of the SM132on the basis of the region information stored in the SM132(S3640), and advances the process to S3670.

On the other hand, when the pre-parity generation stage is not detected (SS3630, NO), the MP121determines whether or not a post-parity generation stage of the process stage information item is detected from the searched SM132(S3650).

When the post-parity generation stage is detected (S3650, YES), the MP121registers this post-parity generation stage in the post-parity generation queue stored in the SM132based on the region information stored in the SM132(S3660), and advances the process to S3670.

When the post-parity generation stage is not detected (S3650, NO), the MP121ends this process flow.

Subsequent to S3640and S3660, the MP121determines whether searching for all SMs132is completed or not (S3670). When searching for all SMs132is not completed (S3670, NO), the MP121returns the process to S3620. When searching for all SMs132is completed (S3670, YES), the MP121ends this process flow.

The operations that are performed by the MP121when there is a registration in the pre-parity generation queue are the same as S2410to S2430described above. In other words, the MP121takes over the process at the stage where the new user data stored in the CM131is transferred to the BEPK140.

FIG. 16shows an operation performed by the MP121in the case where there is a registration in the post-parity generation queue, according to Embodiment 1. Once the MP121detects that there is a registration in the post-parity generation queue (S3710), the MP121sends the new data commit command to the data FMPK144A (S3720). Specifically, when there is a registration in the post-parity generation queue of any of the SMs132, the MP121takes over the write process, from the point where the new data commit command is transmitted to the data FMPK144A, as with the case of the normal write process.

In this manner, the MP121free of faults can take over the write process from the MP121having a fault, depending on the type of the process stage information item stored in the SM132.

Specific Examples of Transition Write Process According to Embodiment 1

Several specific examples of the transition write process performed upon the occurrence of the MP fault are now described.

First Specific Example of Transition Write Process According to Embodiment 1

Here is described the transition write process that is performed upon the occurrence of the MP fault in the pre-parity generation stage.

FIG. 17shows a transition write process performed upon the occurrence of the MP fault in the pre-parity generation stage, according to Embodiment 1. The key components of the operations shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults acknowledges that the process stage information items indicate the pre-parity generation stage, the MP121free of faults send the new data transmission command to the data FMPK144A, as in the normal write process described above (S2530). Consequently, the data FMPK144A writes the new user data into the DFa (memory1445).

Next, in the controller100, the MP121sends the intermediate parity reception command to the data FMPK144A, as in the normal write process (S2630). Accordingly, the data FMPK144A calculates the intermediate parity and sends the intermediate parity to the controller100. Consequently, the BEPK140writes the intermediate parity into the buffer143.

In the controller100, the MP121then sends the intermediate parity transmission command to the parity FMPK144P, as in the normal write process (S3120). Consequently, the parity FMPK144P calculates the new parity and writes the new parity into the PFa (memory1445).

Subsequently, in the controller100, the MP121sends the new data commit command to the data FMPK144A, as in the normal write process (S3230). Consequently, the data FMPK144A determines the new user data as the user data after update.

In the controller100, the MP121then sends the new data commit command to the parity FMPK144P, as in the normal write process (S3320). Consequently, the parity FMPK144P determines the new parity as the parity after update.

The above is the transition write process.

Because the process stages are recorded in the SMs132, another MP121free of faults can take over the write process even upon the occurrence of a fault in a certain MP121. When the process stage information items indicate the pre-parity generation stage at the time of the occurrence of the MP fault, the other MP121free of faults takes over the write process at the stage where the new user data is transferred from the CM131to the BEPK140.

Second Specific Example of Transition Write Process According to Embodiment 1

Here is described the transition write process that is performed upon the occurrence of the MP fault in the post-parity generation stage.

FIG. 18shows a transition write process performed upon the occurrence of the MP fault in the post-parity generation stage, according to Embodiment 1. The operation targets of the operations shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process. Once the MP121free of faults acknowledges that the process stage information items indicate the post-parity generation stage, the MP121free of faults sends the new data commit command to the data FMPK144A, as in the normal write process (S3230). Consequently, the data FMPK144A determines the new user data as the user data after update.

In the controller100, the MP121then sends the new data commit command also to the parity FMPK144P, as in the normal write process (S3320). Consequently, the parity FMPK144P determines the new parity as the parity after update.

The above is the transition write process.

As described above, recording the process stage information items in the SMs132can allow the other MP to take over the write process even upon the occurrence of a fault in a certain MP. When the process stage information items indicate the post-parity generation stage at the time of the occurrence of the MP fault, the other MP121free of faults takes over the write process at the stage where the new user data stored in the data FMPK144A is determined. When the process stage information items indicate the post-parity generation stage, it is not necessary to re-transfer the user data from the CM131, because the new user data exists in the FMPK144A. In other words, this transition write process does not cause additional access to the CM131.

FMPK State in Write Process According to Embodiment 1

Hereinafter, the state of the parity FMPK144P during the write process is referred to as “FMPK state,” and “FMPK state 1” and “FMPK state 2” are described hereinbelow.FIG. 19shows the FMPK state 1, according to Embodiment 1.FIG. 20shows the FMPK state 2, according to Embodiment 1.

In the following description of the operations by the FMPK144, the old user data stored in the data FMPK144A and the old parity stored in the parity FMPK144P are referred to as “old data.” The new user data stored in the data FMPK144A and the new parity stored in the parity FMPK144P are referred to as “new data.” In other words, the operations by the FMPK144described hereinafter can be applied to the operations by the data FMPK144A and the operations by the parity FMPK144P. Furthermore, “additional data” indicates the new user data that is re-transmitted from the controller100to the FMPK144by the transition write process. The operations performed mainly by the CPU1444of the FMPK144are described using the FMPK144.

A pointer table1448that associates a logical page accessed from the controller100with some physical pages inside the FM1443is stored in the memory1445of each FMPK144. The pointer table1448includes correspondence relationships of the physical pages to all logical pages within the FMPK144. In the following description, of the logical pages within each FMPK144, the logical page designated by a command sent from the controller100to the FMPK144is referred to as “target logical page.” Of the entries in the pointer table1448shown in the memory1445, the entry for the target logical page is referred to as “target entry1449.”

The target entry1449has a field for a logical page address, which is a logical address (e.g., LBA: Logical Block Address) designating the target logical page, a field for an old physical page address, which is a physical address designating an old physical page, and a field for a new physical page address, which is a physical page different from the abovementioned physical page and designating a new physical page as a candidate for an old physical page. In the diagram and the following description, in the target entry1449, the logical page address is called “LA,” the old physical page address is called “oPA,” and the new physical page address is called “nPA.” In the diagram and the following description, the value of the logical page address is described as “LBA xxxx,” and the values of the old physical page address and the new physical page address are described as “p0,” “p1,” “p2,” etc.

In the diagrams, an arrow directed from the physical page address stored in the target entry1449to the inside of the FM1443represents a pointer, indicating that this physical page address indicates the physical page pointed by the arrow. When the arrow is in the form of a dashed line, it means that the pointer of the arrow is deleted.

In the case where the FMPK144receives from the controller100a normal write command and a normal read command for the target physical page, the FMPK144associates the target logical page with the old physical page based on the target entry1449of the pointer table, to access the old physical page. In other words, the normal access from the controller100is performed only on the old physical page.

The target entry1449may have stored therein a logical page number indicating the logical page, in place of the logical page address. The target entry1449may have stored therein a physical page number indicating the old physical page, in place of the physical page address. The target entry1449may have stored therein a physical page number indicating the new physical page, in place of the new physical page address. The pointer table is managed and updated by the CPU1444.

In the following description, when the FMPK144registers the value of a physical address for storing data, into the old physical page address or the new physical page address of the target entry1449, this operation is called “pointer connection” for the data. In addition, when the FMPK144changes the value registered in the old physical page address or the new physical page address of the target entry1449to the value of a physical address of a physical page having other data, this operation is called “pointer replacement” for the data. When the FMPK144deletes the value registered in the old physical page address or the new physical page address of the target entry1449, this operation is called “pointer deletion” for the data. These operations mean that the CPU1444updates the target entry1449of the pointer table.

In “FMPK state 1,” the old data is stored in the old physical page. The logical page address and the old physical page address are stored in the target entry1449. In the “FMPK state 2,” the old data is stored in the old physical page, and the new data is stored in the new physical page. The logical page address, the old physical page address, and the new physical page address are stored in the target entry1449. In “FMPK state 1,” the old data is the enabled data. In “FMPK state 2,” the new data and the old data are the enabled data. In the case where the reclamation process is executed in “FMPK state 2,” since the new data and the old data are the enabled data, the new data and the old data are copied from the blocks that respectively store the new data and the old data, to other empty blocks. The FM controller1447may perform control in a manner that the blocks that include the new data and/or the old data obtained during the parity calculation are not reclaimed. Either way, the FM controller1447does not erase the old data until receiving the new data commit command. In this manner, the intermediate parity can be generated in a process performed upon the occurrence of a fault, the process being described hereinafter. Next is described the target entry of the pointer table. The FM controller1447can execute the parity calculation process and the read/write process in parallel on a plurality of entries (logical pages).

Operations by FMPK144Based on Command

An operation by the FMPK144based on each command is described hereinafter.

FIG. 21shows an operation performed based on the new data transmission command under the FMPK state 1, according to Embodiment 1. This operation corresponds to S2530described above. In the FMPK144, the old data is stored in the old physical page. In the target entry1449, the old physical page address indicates the old physical page. First, the BEPK140sends the new data transmission command designating the target logical page and accompanying new data to the FMPK144(S5110). The FMPK144stores the new data temporarily in the memory1445and afterward writes the new data into the new physical page of the FM1443(S5120). The FMPK144then performs the pointer connection on the new data by designating the new physical page for the new physical page address of the target entry1449(S5130). Subsequently, the FMPK144sends a normal end response to the controller100(S5140). This operation allows the system state to transit from the state 1 to the state 2. With this new data transmission command, the correspondence relationship between the logical page address and the old physical page address can be maintained even after writing the new data, without having the old data disabled. When the FM controller1447described hereinafter receives the new data commit command, the correspondence relationship between the logical page address and the old physical page address is canceled. Moreover, with the new data transmission command, the new data can be written to the physical page of the physical page of the FM prior to the generation of the intermediate parity. The old user data is kept in the parity FMPK144P until the new parity is written to the physical storage region. Accordingly, even upon the occurrence of a fault, the intermediate parity can be generated using the old user data. The normal write process, on the other hand, is described with reference toFIG. 31.

FIG. 22shows an operation performed based on the new data transmission command under the FMPK state 2, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page and the new data is stored in the new physical page. In the target entry1449, the old physical page address indicates the old physical page, and the new physical page address indicates the new physical page. First, the controller100sends the new data transmission command designating the target logical page and accompanying additional data to the FMPK144(S5210). The FMPK144stores the additional data temporarily in the memory1445and afterward writes the additional data into an additional physical page, which is a physical page different from the old physical page and the new physical page of the FM1443(S5220). The FMPK144then performs the pointer replacement for replacing the new data with the additional data, by designating the additional physical page for the new physical page address of the target entry1449(S5230). Subsequently, the FMPK144sends a normal end response to the controller100(S5240). In this process, the new data stored in the FM is not taken as the old data. Since the stage occurs prior to the generation of the new parity, the old data obtained when the old parity was generated is maintained as the old data. When processing the new data transmission command, the FMPK state does not transit from the FMPK state 2. In other words, when processing the new data transmission command in the FMPK state 1, the FMPK state transits to the FMPK state 2. When processing the new data transmission command in the FMPK state 2, the FMPK state remains as the FMPK state 2. This means that the transition of the state of the FMPK occurs due to the new data transmission command, regardless of the state of the FMPK. The normal write process, on the other hand, is described with reference toFIG. 32.

FIG. 23shows an operation performed based on the intermediate parity reception command under the FMPK state 1, according to Embodiment 1. First, the controller100sends the intermediate parity reception command to the FMPK144(S5310). This intermediate parity reception command designates the target logical page. Subsequently, the FMPK144sends an abnormal end response to the controller100(S5320).

FIG. 24shows an operation performed based on the intermediate parity reception command under the FMPK state 2, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page, and the new data in the new physical page. In the target entry1449, the old physical page address indicates the old physical page, and the new physical page address indicates the new physical page. In other words, the old physical page and the new physical page are mapped to the logical page address. First, the controller100sends the intermediate parity reception command to the FMPK144(S5410). This intermediate parity reception command designates the target logical page. The FMPK144then reads the old data and the new data indicated respectively by the old physical page address and the new physical page address stored in the target entry1449, and generates an intermediate parity using the XOR circuit1442(S5420). In the FMPK144, mapping to the old data is maintained based on the new data transmission command from the controller100. Accordingly, the FM controller can specify the new user data and the old user data for a certain logical page address. Subsequently, the FMPK144sends a response regarding the intermediate parity to the controller100(S5430). In addition, as shown inFIG. 22, the same process is carried out even when the additional data is stored in the FM. In other words, the FM controller generates the intermediate parity from the additional user data and the old user data. In the FMPK144, the intermediate parity generation process is executed a number of times on the other user data, in parallel with the normal read/write process, and the memory1445is used in these processes as well. Therefore, maintaining the written new user data in the memory1445and writing the intermediate parity to the FM after the generation thereof increases the period of time in which the new user data is stored in the memory. This can deteriorate the performance of the read/write process. In the present embodiment, the FM controller reads the new user data and the old user data to generate the intermediate parity after writing the new data into the FM and upon reception of the intermediate parity reception command. Thus, the period of time in which the new user data and the old user data are stored in the memory1445of the FMPK144can be shortened when the intermediate parity is generated. As a result, the region in the memory that can be used in the read/write process can be increased, improving the process performance of the FMPK144.

FIG. 25shows an operation performed based on the intermediate parity transmission command under the FMPK state 1, according to Embodiment 1. In the FMPK144, the old parity is stored in the old physical page. In the target entry1449, the old physical page address indicates the old physical page. First, the BEPK140sends to the FMPK144the intermediate parity transmission command designating the target logical page and related to the intermediate parity (S5510). Then, the FMPK144temporarily stores the intermediate parity in the memory1445, reads the old parity from the old physical page indicated by the old physical page address of the target entry1449, temporarily stores the old parity in the memory1445, generates a new parity from the intermediate parity and the old parity by using the XOR circuit1442, and writes the new parity to the new physical page (S5520). The FMPK144then performs the pointer connection on the new parity by designating the new physical page for the new physical page address of the target entry1449(S5530). Subsequently, the FMPK144sends a normal end response to the controller100(S5540).

FIG. 26shows an operation performed based on the intermediate parity transmission command under the FMPK state 2, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page and the new data is stored in the new physical page. In the target entry1449, the old physical page address indicates the old physical page, and the new physical page address indicates the new physical page. First, the controller100sends the intermediate parity transmission command designating the target logical page and accompanying the intermediate parity to the FMPK144(S5610). The FMPK144then reads the old data from the old physical page indicated by the old physical page address stored in the target entry1449, generates additional data from the intermediate parity and the old data using the XOR circuit1442, and writes the additional data into the additional physical page different from the old physical page and the new physical page (S5620). The FMPK144then performs the pointer replacement for replacing the new data with the additional data, by designating the additional physical page for the new physical page address of the target entry1449(S5630). Subsequently, the FMPK144sends a normal end response to the controller100(S5640). In this manner, even in the FMPK state 1 or the FMPK state 2, the additional parity (same as the new parity) can be generated from the old parity and the intermediate parity when the FM controller receives the intermediate parity transmission command.

FIG. 27shows an operation performed based on the new data commit command under the FMPK state 1, according to Embodiment 1. When this process is performed by the data FMPK144A, the new data is determined. When the process is performed by the parity FMPK144P, the new parity is determined. In the FMPK144, the old data is stored in the old physical page. In the target entry1449, the old physical page address indicates the old physical page. First, the controller100sends the new data commit command to the FMPK144(S5710). This new data commit command designates the target logical page. Subsequently, the FMPK144sends a normal end response to the controller100(S5720). In other words, because the new data is already determined, the FMPK state 1 is recognized as a normal state. This process is executed in order to confirm the FMPK state, when a system fault occurs after the new data and the new parity are determined and before the process stage information items in the SMs132are cleared.

FIG. 28shows an operation performed based on the new data commit command under the FMPK state 2, according to Embodiment 1. When this process is performed by the data FMPK144A, the new data is determined. When the process is performed by the parity FMPK144P, the new parity is determined. As a result of this process, the state of the FMPK144transits from the FMPK state 2 to the FMPK state 1. In the FMPK144, the old data is stored in the old physical page and the new data is stored in the new physical page. In the target entry1449, the old physical page address indicates the old physical page, and the new physical page address indicates the new physical page. First, the controller100sends the new data commit command to the FMPK144(S5810). This new data commit command designates the target logical page. The FMPK144then performs the pointer replacement for replacing the old data with the new data, by designating the new physical page for the old physical page address of the target entry1449, and performs the pointer deletion on the new data by deleting the new physical page from the new physical page address of the target entry1449(S5820). Subsequently, the FMPK144sends a normal end response to the controller100(S5830). After these steps, the FM controller responds with new data when receiving a read request. In this way, in both FMPK state 1 and FMPK state 2, the establishment of the FMPK state 1 is ensured when the new data commit command is received

FIG. 29shows an operation performed based on the normal read command under the FMPK state 1, according to Embodiment 1. First, the controller100sends the normal read command to the FMPK144(S4310). This normal read command designates the target logical page. The FMPK144then reads the old data indicated by the old physical page address of the target entry1449, and sends a response regarding the old data to the controller100(S4320).

FIG. 30shows an operation performed based on the normal read command under the FMPK state 2, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page, and the new data in the new physical page. In the state 2, both the old physical page and the new physical page are mapped to a certain LBA. In other words, for the storage system, this state is where writing of the new data is not completed. First, the controller100sends the normal read command to the FMPK144(S4410). This normal read command designates the target logical page. The FMPK144then reads the old data indicated by the old physical page address of the target entry1449, and sends a response regarding the old data to the controller100(S4420).

FIG. 31shows an operation performed based on the normal write command under the FMPK state 1, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page. In the target entry1449, the old physical page address indicates the old physical page. First, the controller100sends the normal write command designating the target logical page and accompanying new data to the FMPK144(S4110). The FMPK144then writes the new data into the new physical page stored in the FM1443(S4120). The FMPK144then performs the pointer replacement for replacing the old data with the new data, by designating the new physical page for the old physical page address of the target entry1449(S4130). Subsequently, the FMPK144sends a normal end response to the controller100(S4140). This operation does not allow the FMPK state to transit from the FMPK state 1.

FIG. 32shows an operation performed based on the normal write command under the FMPK state 2, according to Embodiment 1. In the FMPK144, the old data is stored in the old physical page and the new data is stored in the new physical page. In the target entry1449, the old physical page address indicates the old physical page, and the new physical page address indicates the new physical page. First, the controller100sends the normal write command designating the target logical page and accompanying additional data to the FMPK144(S4210). The FMPK144then writes the additional data into the additional physical page, which is a physical page different from the old physical page and the new physical page stored in the FM1443(S4220). The FMPK144then performs the pointer replacement on the old data by designating the additional physical page for the old physical page address of the target entry1449(S4230). Subsequently, the FMPK144performs the pointer deletion on the new data by deleting the new physical page from the new physical page address of the target entry1449(S4240). The FMPK144then sends a normal end response to the controller100(S4250). This operation allows the system state to transit from the FMPK state 2 to the FMPK state 1.

Transitions of System State

FIG. 33shows the each process according to Embodiment 1 and transitions of the state of the system caused due to the occurrence of a system fault. The states of the system adopted in this embodiment are, in addition to the system states 1 to 7 described above, a system state a, system state b, system state c, system state e, system state f, system state A, system state B, system state C, system state D, system state E, system state F, system state G, and system state I, each of which indicates a state of the system upon the occurrence of a fault. The numbers of the drawings describing the corresponding processes by the FMPK are shown in parentheses. In the drawing, the terms “pre-parity generation stage” and “post-parity generation stage” indicate the contents of the process stage information items stored in the SM132. The term “clear SM” means that the new data and the new parity are determined and that the process stage information items related to the FMPK are deleted from the SM132. In the system states 1 to 3, the correspondence relationship between the logical page and the physical page in which the old user data is stored is kept in the data FMPK144A. In the system states 1 to 3, the correspondence relationship between the logical page and the physical page in which the old parity is stored is kept in the parity FMPK144P. Therefore, when faults occur in the system states 1 to 3, the intermediate parity can be generated by allowing the controller100to transmit the new user data to the data FMPK144A, and the new parity can be generated from the intermediate parity and the old parity. In the system states 4 to 6, the correspondence relationship between the logical page and the physical page in which the new user data is stored is kept in the data FMPK144A. In the system states 4 to 6, the correspondence relationship between the logical page and the physical page in which the new parity is stored is kept in the parity FMPK144P. Therefore, when faults occur in the system states 4 to 6, the new user data and the new parity can be determined by allowing the controller100to transmit the new data commit command to the data FMPK144A and the parity FMPK144P. As described above, the process stage information item stored in the SM132has two stages: “pre-parity generation stage” and “post-parity generation stage.” For this reason, data loss that is caused upon the occurrence of a fault can be avoided, and the load imposed to manage the process stage information item can be reduced. Managing the process stage information item in detail increases the number of accesses to the SMs132for recording the process stage information item therein and increases the load caused as a result of the accesses made to the SMs132.

First, a Normal Transition of the System State is Described.

FIG. 34shows an arrangement of data in the system state 1, according to Embodiment 1. In the following description, two of the FEPKs110of the controller100are referred to as “FEPK110A” and “FEPK110B,” respectively. Two of the MPPKs120of the controller100are referred to as “MPPK120A” and “MPPK120B,” respectively. Two of the CMPKs130of the controller100are referred to as “CMPK130A” and “CMPK130B,” respectively. Two of the BEPKs140of the controller100are referred to as “BEPK140A” and “BEPK140B,” respectively. Of the plurality of FMPKs144configuring the RAID groups, the FMPKs144other than the data FMPK144A and the parity FMPK144P are referred to as “other data FMPKs144E.” In addition, in the diagram and the following description, the old user data, which is the user data obtained before the update by the write process, is referred to as “oDi,” the new user data, which is the user data after the update, is referred to as “nDi,” other user data, which is the user data stored in the other data FMPKs144E within the same stripe as the oDi, is referred to as “oDx.” Furthermore, the intermediate parity is referred to as “mP,” the old parity as “oP,” and the new parity as “nP.” In the drawings and the following description, the MP121of the MPPK120A in the write process is referred to as “MP in process.”

The system state 1 occurs before the controller100transmits the new data transmission command. The CM131of the CMPK130A and the CM131of the CMPK130B have the new user data stored therein. The SM132of the CMPK130A and the SM132of the CMPK130B show the pre-parity generation stages. The data FMPK144A has the old user data stored therein. The parity FMPK144P has the old parity stored therein. The other FMPKs144E have other user data stored therein. The old physical page address of the target entry1449of the data FMPK144A indicates the old user data. The old physical page address of the target entry1449of the parity FMPK144P indicates the old parity.

In the state 1, the controller100sends the new data transmission command to the data FMPK144A. As a result, the system state transits to the state 2.

FIG. 35shows an arrangement of data in the system state 2, according to Embodiment 1. This state occurs after the completion of the new data transmission command by the controller100. The new data transmission command sends the new user data stored in the CM131of the CMPK130A, to the FMPK144A via the BEPK140A. As a result, the BEPK140A stores the new user data. Also, the data FMPK144A stores the old user data and the new user data. Both the new physical page address and the old physical page address are associated with the target logical page address in the data FMPK144A. The new physical page address indicates the physical page in which the new user data is stored, and the old physical page address indicates the physical page in which the old user data is stored.

In the system state 2, the controller100sends the intermediate parity reception command to the data FMPK144A and the intermediate parity transmission command to the parity FMPK144P. As a result, the system state transits to the state 3.

FIG. 36shows an arrangement of data in the system state 3, according to Embodiment 1. This state occurs after the completion of the intermediate parity reception command and the intermediate parity transmission command by the controller100. The intermediate parity reception command sends the intermediate parity generated by the data FMPK144A, to the buffer143of the BEPK140A. The intermediate parity transmission command sends the intermediate parity of the buffer143of the BEPK140A to the parity FMPK144P without being stored in the CM, and writes the new parity generated by the parity FMPK144P into the parity FMPK144P. Accordingly, the buffer143of the BEPK140A stores the new user data and the intermediate parity. Both the new physical page address and the old physical page address are associated with the target logical page address in the parity FMPK144P. The new physical page address indicates the physical page in which the new parity is stored, and the old physical page address indicates the physical page in which the old parity is stored. At least up to this stage, the correspondence relationship between the target logical page address and the old physical page in which the old user data is stored is kept in the data FMPK144A. Therefore, when faults occur in the states 1 to 3, as will be described hereinafter, transmitting the new data to the data FMPK144A can generate the intermediate parity.

In the system state 3, the controller100changes the process stage information of the SMs132to the post-parity update stage, whereby the system state transits to the state 4.

FIG. 37shows an arrangement of data in the system state 4, according to Embodiment 1. This state occurs after the transmission of the intermediate parity transmission command by the controller100, after completion of the writing of the new parity in the parity FMPK, and after the MP updates the process stage information item stored in the SM132to the post-parity generation stage. The process stage information item is stored in both the SM132of the CMPK130A and the SM132of the CMPK130B to obtain a redundant process stage information.

In the system state 4, the controller100sends the new data commit command to the data FMPK144A. As a result, the system state transits to the state 5.

FIG. 38shows an arrangement of data in the system state 5, according to Embodiment 1. This state occurs after the completion of the new data commit command on the new user data by the controller100. Accordingly, the old physical page address of the target entry1449in the data FMPK144A indicates the new user data, and the new physical page address is cleared. After the new parity is written to the physical page of the FM in the parity FMPK144P, the old data stored in the data FMPK144A becomes no longer necessary. Mapping of the logical page and the old physical page in which the old data is stored is canceled by the new data commit command, and thus the old physical page is erased. The storage device having the FMs needs empty regions in order for the reclamation process, a wear leveling process and the like to be performed. In the present embodiment, therefore, the old data can be erased by not mapping the old data, as soon as the old data becomes unnecessary, so that empty blocks (free spaces) can be ensured in the FMs by executing appropriate processes.

In the system state 5, the controller100sends the new data commit command to the parity FMPK144P. As a result, the system state transits to the state 6.

FIG. 39shows an arrangement of data in the system state 6, according to Embodiment 1. This state occurs after the completion of the new data commit command on the parity FMPK144P by the controller100. Therefore, the old physical page address of the target entry1449in the parity FMPK144P indicates the new parity, and the new physical page address is cleared.

In the system state 6, the controller100clears the process stage information item stored in each SM132, whereby the system state transits to the system state 7.

FIG. 40shows an arrangement of data in the system state 7, according to Embodiment 1. This system state 7 occurs after the process stage information item stored in each SM132is cleared by the controller100. As a result, both the SM132of the CMPK130A and the SM132of the CMPK130B are cleared.

Next is described a restoration process that is executed when a system fault occurs in each of the states 1 to 7.

The system fault here means a simultaneous point of fault occurring in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs140, and the plurality of FMPKs144. Upon the occurrence of this system fault, the number of faulty packages of one type is equal to or less than one. In addition, the occurrence of this system fault includes a simultaneous occurrence of faults in a plurality of types of pages. As will be described hereinafter, even upon a simultaneous occurrence of faults in a plurality of types of packages, the data thereof can be restored without being lost.

In the state 1, the occurrence of the system fault causes the system state to transit to the state a.

FIG. 41shows an arrangement of data in the system state a, according to Embodiment 1. This system state a means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. The sections where the faults occur are shown by “X” in this diagram. In the diagram and the following description, the MP121of the MPPK120B that takes over the process by the MPPK120A in which a fault has occurred is referred to as “transition MP.” The transition MP detects that the process stage information stored in the SM132of the CMPK130B indicates the pre-parity generation stage. In response to this detection, the transition MP transmits the new data transmission command.

In the system state a, the controller100sends the new data transmission command to the data FMPK144A. As a result, the system state transits to the system state A.

FIG. 42shows an arrangement of data in the system state A, according to Embodiment 1. This system state A occurs after the completion of the new data transmission command by the controller100. The new data transmission command sends the new user data stored in the CM131of the CMPK130B free of faults to the data FMPK144A via the BEPK140B free of faults. Accordingly, the BEPK140B has the new user data stored therein. The data FMPK144A has the old user data and the new user data stored therein. The new physical page address stored in the target entry1449of the data FMPK144A indicates the new user data.

In the system state A, the controller100sends the intermediate parity reception command to the data FMPK144A and the intermediate parity transmission command to the parity FMPK144P. As a result, the system state transits to the state B.

FIG. 43shows an arrangement of data in the system state B, according to Embodiment 1. This state occurs after the completion of the intermediate parity reception command and the intermediate parity transmission command by the BEPK140. The intermediate parity reception command sends the intermediate parity, which is generated by the data FMPK144A, to the BEPK140B. The intermediate parity transmission command sends the intermediate parity stored in the buffer of the BEPK140B to the parity FMPK144P without being stored in the CM131, and writes the new parity generated by the parity FMPK144P into the parity FMPK144P. Accordingly, the BEPK140B has the new user data and the intermediate parity stored therein. The parity FMPK144P has the old parity and the new parity stored therein.

In the system state B, the controller100changes the process stage information of each SM132, whereby the system state transits to the system state C.

FIG. 44shows an arrangement of data in a system state C, according to Embodiment 1. This state occurs after the controller100completes the parity transmission command and updates the process stage information stored in each SM132. Thus, the SM132of the CMPK130B indicates the post-parity generation stage.

In the system state C, the controller100sends the new data commit command to the data FMPK144A. As a result, the system state transits to the system state D.

FIG. 45shows an arrangement of data in a system state D, according to Embodiment 1. This system state D occurs after the completion of the new data commit command on the new user data by the controller100. Thus, the old physical page address stored in the target entry1449of the data FMPK144A indicates the new user data, and the new physical page address is cleared.

In the system state D, the controller100sends the new data commit command to the parity FMPK144P, whereby the system state transits to the system state E.

FIG. 46shows an arrangement of data in the system state E, according to Embodiment 1. This system state occurs after the completion of the new data commit command on the new parity by the controller100. Thus, the old physical page address stored in the target entry1449of the parity FMPK144P indicates the new parity, and the new physical page address is cleared.

In the system state E, the controller100clears the process stage information of the SM132, whereby the system state transits to the system state F.

FIG. 47shows an arrangement of data in the system state F, according to Embodiment 1. In this system state F, the process stage information item stored in the SM132of the CMPK130B is cleared. This system state F occurs after the completion of the write process related to parity generation. When the system state transits to the system state F, it is determined that the write process is completed without causing data loss.

As a result of the occurrence of a system fault in the system state 2, the system state transits to the system state b.

FIG. 48shows an arrangement of data in the system state b, according to Embodiment 1. As with the system state a, this system state b means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. The transition MP detects that the process stage information item stored in the SM132of the CMPK130B indicates the pre-parity generation stage. In response to this detection, the transition MP transmits the new data transmission command. In this system state b, because the old user data is associated with the logical page to which the new user data is to be written, transmission of the new user data can generate the intermediate parity.

In the system state b, the controller100sends the new data transmission command to the data FMPK144A, whereby the system state transits to the state A. Thereafter, the system state can transit in order of the system state B, the system state C, the system state D, the system state E, and the system state F.

As a result of the occurrence of the system fault in the system state 3, the system state transits to the system state c.

FIG. 49shows an arrangement of data in the system state c, according to Embodiment 1. As with the state a, this state means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. The transition MP detects that the process stage information stored in the SM132of the CMPK130B indicates the pre-parity generation stage. In response to this detection, the transition MP transmits the new data transmission command. The data FMPK144A has the old user data and the new user data stored therein. In the target entry1449of the data FMPK144A, the old physical page address indicates the old user data, and the new physical page address indicates the new user data. The parity FMPK144P has the old parity and the new parity stored therein. In the target entry1449of the parity FMPK144P, the old physical page address indicates the old parity, and the new physical page address indicates the new parity. The data FMPK in the system state c maintains the correspondence relationship between the old user data and the logical page to which the new user data is to be written. Therefore, the intermediate parity can be generated by transmitting the new data.

In the system state c, the controller100sends the new data transmission command to the data FMPK144A, whereby the system state transits to the state G.

FIG. 50shows an arrangement of data in the system state G, according to Embodiment 1. This system state G occurs after the completion of the new data transmission command by the controller100. As in the system state A, the new data transmission command sends the new user data stored in the CM131of the CMPK130B free of faults to the data FMPK144A via the BEPK140B free of faults. Accordingly, the BEPK140B stores the new user data. The data FMPK144A in the system state G maintains the correspondence relationship between the old user data and the logical page to which the new user data is to be written. Therefore, the intermediate parity can be generated by transmitting the new data. Moreover, the parity FMPK144P in the state G maintains the correspondence relationship between the old parity and the target logical page. Thus, the new parity can be generated by transmitting the intermediate parity.

In the system state G, the controller100sends the intermediate parity reception command to the data FMPK144A and the intermediate parity transmission command to the parity FMPK144P. As a result, the system state transits to the system state B. Subsequently, the system state can transit in order of the system state C, the system state D, the system state E, and the system state F.

As a result of the occurrence of the system fault in the state 4, the system state transits to the state C. Subsequently, the system state can transit in order of the system state D, the system state E, and the system state F.

As a result of the occurrence of the system fault in the system state 5, the system state transits to the system state e.

FIG. 51shows an arrangement of data in the system state e, according to Embodiment 1. As with the system state a, this system state e means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. The transition MP detects that the process stage information stored in the SM132of the CMPK130B indicates the post-parity generation stage. In other words, this state occurs after the completion of the parity transmission command by the controller100and after the process stage information stored in the SM132is updated. In response to the detection, the transition MP transmits the new data commit command to the data FMPK144A. The data FMPK144A has the new user data stored therein. In the target entry1449of the data FMPK144A, the old physical page address indicates the new user data. The parity FMPK144P has the old parity and the new parity stored therein. In the target entry1449of the parity FMPK144P, the old physical page address indicates the old parity, and the new physical page address indicates the new parity.

In the system state e, the controller100sends the new data commit command to the data FMPK144A, whereby the system state transits to the state D. Subsequently, the system state can transit from the system state E to the system state F.

As a result of the occurrence of the system fault in the system state 6, the system state transits to the system state f.

FIG. 52shows an arrangement of data in the system state f, according to Embodiment 1. As with the system state a, this state means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. The transition MP detects that the process stage information item stored in the SM132of the CMPK130B indicates the post-parity generation stage. In other words, this state occurs after the completion of the parity transmission command by the controller100and after the process stage information item stored in the SM132is updated. Accordingly, the transition MP transmits the new data commit command to the data FMPK144A. The data FMPK144A stores the new user data. In the target entry1449of the data FMPK144A, the old physical page address indicates the new user data. The parity FMPK144P stores the new parity. In the target entry1449of the parity FMPK144P, the old physical page address indicates the new parity.

In the system state f, the controller100sends the new data commit command to the data FMPK144A, whereby the system state transits to the state I.

FIG. 53shows an arrangement of data in the system state I, according to Embodiment 1. As with the system state a, this system state I means a situation where faults occur in the MPPK120A in the write process, the CMPK130A, the BEPK140A having the new user data stored therein, and the FMPK144E having the other user data stored therein. This state occurs after the completion of the new data commit command on the new user data by the controller100. In response to the detection, the transition MP transmits the new data commit command to the parity FMPK144P. The data FMPK144A has the new user data stored therein. In the target entry1449of the data FMPK144A, the old physical page address indicates the new user data. The parity FMPK144P has the new parity stored therein. In the target entry1449of the parity FMPK144P, the old physical page address indicates the new parity.

In the system state I, the controller100sends the new data commit command to the parity FMPK144P, whereby the system state transits to the state E. Subsequently, the system state can transit to the system state F.

As a result of the occurrence of a system fault in the system state 7, the system state transits to the system state F. In the system state 7 the data stored in the FMPKs144are determined and the process stage information items are cleared. Therefore, no additional processes are required even when the system fault occurs and the system state consequently transits to the state F. Therefore, even upon the occurrence of a system fault, the host computer30can read oDi and oD1 to oDy free of faults that are shown in the stripes of the RAID, as long as the system state can transit to the system state 7 or the state F. Therefore, data loss does not occur because the host computer30can also read oDx in which a fault occurs, by XORing the oD1 . . . nDi . . . oDy, nP within the stripes.

In this embodiment, the number of the MPPKs120, the CMPKs130, and the BEPKs140are each two but may be three or more. Even when the number of the MPPKs120, the CMPKs130, or the BEPKs140is one, the same operations can be carried out as long as no faults occur in a section thereof.

According to the state transitions described above, data loss does not occur, even when the system fault occurs in any of the system states 1 to 7. In other words, data loss does not occur even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs140and the plurality of FMPKs144. Thus, the reliability of the storage system10can be improved. Note that the present embodiment can couple the other storage systems having the XOR function in place of the FMPKs144and cause the other storage devices to implement the intermediate parity and/or parity calculation process.

Furthermore, because overwriting of data cannot be performed in a normal flash memory, the new physical page is allocated to the logical page in a normal write process.

The present embodiment uses the data that are stored in the old physical page which is disabled as a result of the allocation of the new physical page. Therefore, the present embodiment does not increase the number of times the write process is performed and the number of times the data is erased. In other words, in the present embodiment, the operating life of the flash memory is not shortened.

This embodiment illustrates a situation where the FMPK144supports the XOR function based on a request regarding a SCSI command. Examples of the SCSI command include XDWRITE, XDREAD, and XPWRITE. The rest of the configurations of the storage system10are the same as those described in Embodiment 1. In the present embodiment, the storage media are not limited to the flash memory devices as long as these SCSI commands are supported.

Write Process According to Embodiment 2

A normal write process is now described.

FIG. 54shows a write process according to Embodiment 2. In this sequence diagram as well, the DFa and the DFb of the data FMPK144A represent the memory1445and the FM1443(physical page) of the data FMPK144A. Furthermore, the DFa and the DFb of the parity FMPK144P represent the memory1445and the FM1443(physical page) of the parity FMPK144P. The other key components of the operations in the sequence diagram are the same as those shown in the sequence diagram illustrating the write process according to Embodiment 1.

In the present embodiment, the process stage information items stored in the SMs132indicate “pre-parity generation stage,” “stage in process of data media update,” “stage in process of parity media update,” and “post-parity generation stage.” Compared to Embodiment 1, the present embodiment has more of the process stage information items stored in the SMs132. First, the MP121performs the processes S2110to S2350, as in the write process of Embodiment 1. The MP121accordingly changes the values of the process stage information items stored in the two SMs132corresponding to the regions of the two CMs131having the new user data stored therein, to values corresponding to the stage in process of data media update.

Next, the MP121sends an XDWRITE command to the data FMPK144A (S6210). This XDWRITE command designates the logical page in which the old user data is stored, and accompanies the new user data. At this moment, in response to an instruction from the MP121, the BEPK140secures the buffer143, reads the new user data from the CM131, and writes the new user data into the secured buffer143. The MP121then reads the new user data from the buffer143and sends the new user data to the data FMPK144A.

The data FMPK144A then receives the XDWRITE command and the new user data from the controller100. The data FMPK144A accordingly writes the new user data into the FM1443. Subsequently, the data FMPK144A reads the old user data and the new user data stored in the FM1443, generates the intermediate parity using the XOR circuit1442, and writes the intermediate parity into the memory1445. The data FMPK144A then sends a normal end of the XDWRITE command the controller100.

Thereafter, the MP121receives the normal end of the XDWRITE command from the data FMPK144A. The MP121accordingly sends an XDREAD command to the data FMPK144A (S6220). This XDREAD command designates the address of the memory1445having the intermediate parity stored therein. Note that the address of the memory1445having the intermediate parity stored therein is stored in the memory1445.

The data FMPK144A then receives the XDREAD command from the controller100. The data FMPK144A accordingly reads the intermediate parity stored in the memory1445on the basis of information in the memory1445, sends the intermediate parity to the controller100, and sends a normal end of the XDREAD command to the controller100.

At this moment, the BEPK140receives the intermediate parity from the data FMPK144A and writes the intermediate parity into the buffer143. Next, the MP121receives the normal end of the XDREAD command from the data FMPK144A. The MP121accordingly changes the values of the process stage information items to a mid-stage of parity media update.

The MP121then sends an XPWRITE command to the parity FMPK144P (S6410). This XPWRITE command designates the logical page having the old parity stored therein, and accompanies the intermediate parity. At this moment, in response to an instruction from the MP121, the BEPK140reads the intermediate parity from the buffer143and sends the intermediate parity to the parity FMPK144P.

Next, the parity FMPK144P receives the XPWRITE command and the intermediate parity from the controller100. The parity FMPK144P accordingly receives the intermediate parity and writes the intermediate parity into the memory1445. As a result of the XOR operation on the old parity stored in the PFb and the intermediate parity stored in the memory1445, the parity FMPK144P generates the new parity and writes the same into the FM1443. Subsequently, the parity FMPK144P sends a normal end of the XPWRITE command to the controller100.

Thereafter, the MP121clears the process stage information items stored in the SM132.

The Above is the Write Process.

As described above, the controller100sends the intermediate parity from the buffer143to the parity FMPK144P without writing the intermediate parity received from the data FMPK144A into the CM131. Accordingly, the number of accesses to the CM131during the write process becomes three, thereby the number of accesses to the CM131can be reduced (see paragraph [0208]).

According to this embodiment, the reliability of the storage system10can be improved by storing the new user data and each process stage information in two CMPKs130.

In addition, this embodiment can increase the speed of the storage system10because the new data commit commands (in S3230and S3320) are not required.

According to this embodiment, the storage medium employed for the storage system10may be a magnetic storage medium, an optical storage medium, or other nonvolatile storage medium.

Specific Examples of Transition Write Process According to Embodiment 2

Several specific examples of the transition write process performed upon the occurrence of the MP fault are now described.

First Specific Example of Transition Write Process According to Embodiment 2

Here is described the transition write process that is performed upon the occurrence of the MP fault in the pre-parity generation stage.

FIG. 55shows a transition write process performed upon the occurrence of an MP fault in the pre-parity generation, according to Embodiment 2. The operation targets of the operations shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes that a fault has occurred in another MP121, the MP121acknowledges that each process stage information indicates the pre-parity generation. The MP121accordingly changes the values of the process stage information items stored in the two SMs132corresponding to the regions of the two CMs131having the new user data stored therein, to the data media update.

Next, the MP121performs the processes S6210to S6410, as in the normal write process. In other words, the MP121free of faults takes over the write process, from the point where the XDWRITE command is sent to the data FMPK144A (S6210). Because the new user data is stored in the CM131, the BEPK140reads the new user data from the CM131, writes the new user data into the buffer143, reads the new user data from the buffer143, and sends the new user data to the data FMPK144A, in response to the instruction from the MP121. In this manner, the MP121free of faults can take over the write process to perform the write process successfully.

Subsequently, the MP121clears the process stage information items stored in the SMs132.

The above is the transition write process.

As described above, even when the MP fault occurs in the pre-parity generation stage, another MP121free of faults can take over the write process to perform the write process successfully based on the process stage information items stored in the SMs132. When the process stage information item obtained upon the occurrence of the MP fault indicates the pre-parity generation stage, the MP121takes over the write process, from the point where the XDWRITE command is sent to the data FMPK144A (S6210).

Second Specific Example of Transition Write Process According to Embodiment 2

Here is described the transition write process that is performed upon the occurrence of the MP fault in the mid-stage of data media update.

FIG. 56shows a transition write process performed upon the occurrence of the MP fault in the mid-stage of data media update, according to Embodiment 2. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process. In the diagram and the following description, the user data other than the old user data stored in the RAID groups configured by the plurality of FMPKs144are referred to as “other user data.” The FMPK144having the other user data stored therein is referred to as “other data FMPK144E.” In the diagram and the following description, the other user data are referred to as “oD1, . . . , oDn.”

Once the MP121free of faults recognizes a fault occurring in another MP121, the MP121acknowledges that each process stage information item indicates the state in process of data media update. The MP121accordingly sends the normal read (READ) command to the other data FMPK144E (S6510). In other words, the MP121free of faults takes over the write process, from the point where the new parity is generated. This normal read command designates the logical page having the other user data stored therein. The other data FMPK144E accordingly reads the other user data and sends the other user data to the controller100. Consequently, the BEPK140writes the other user data into the buffer143and further writes the other user data into the CM131.

Next, the MP121performs the XOR operation on the new user data and the other user data stored in the CM131, generates the new parity, and writes the new parity into the two CMs131(S6520). The MP121then writes a value indicating the post-parity generation into the process stage information items stored in the two SMs132corresponding to the two CMs131.

Subsequently, the MP121sends the normal write (WRITE) command to the data FMPK144A (S6530). This normal write command accompanies the new user data. Consequently, the BEPK140writes the new user data stored in the CM131into the buffer143, and sends the new user data to the data FMPK144A. The data FMPK144A accordingly writes the new user data into the FM1443.

Subsequently, the MP121sends the normal write command to the parity FMPK144P (S6540). This normal write command accompanies the new parity. Consequently, the BEPK140writes the new parity stored in the CM131into the buffer143, and sends the new parity to the parity FMPK144P. The parity FMPK144P accordingly writes the new parity into the FM1443.

The MP121then clears the process stage information items stored in the SM132.

The above is the transition write process.

As described above, even when the MP fault occurs in the mid-stage of data media update, the other MPs121can take over the write process to perform the transition write process. When the process stage information items during the occurrence of MP fault are being data-media updated, the MP121free from a fault takes over a write process from a stage in which other data are transferred from the FMPK to the CM131.

Third Specific Example of Transition Write Process According to Embodiment 2

Here is described a transition write process performed upon the occurrence of the MP fault in the mid-stage of parity media update.

FIG. 57shows a transition write process performed upon the occurrence of the MP fault in the mid-stage of parity media update, according to Embodiment 2. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes that a fault has occurred in another MP121, the MP121acknowledges that each process stage information indicates the mid-stage of parity media update. The MP121accordingly performs S6510, S6520and S6540described above (seeFIG. 56). Consequently, the new parity stored in the CM131is written to the parity FMPK144P.

Subsequently, the MP121clears the process stage information items stored in the SM132.

The above is the transition write process.

As described above, even when the MP fault occurs in the mid-stage of parity media update, the other MPs121can take over the write process to perform the transition write process. When the process stage information items during the occurrence of MP fault are being parity-media updated, a write process is taken over from a stage in which other data are transferred from the FMPK144E to the CM131.

Fourth Specific Example of Transition Write Process According to Embodiment 2

Here is described a transition write process performed upon the occurrence of an MP fault in the post-parity generation stage.

FIG. 58shows a transition write process performed upon the occurrence of the MP fault in the post-parity generation stage, according to Embodiment 2. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes an MP121in which a fault has occurred, the MP121acknowledges that each process stage information indicates the post-parity generation. The MP121accordingly performs S6530and S6540described above. Consequently, the new user data stored in the CM131is written to the data FMPK144A. Furthermore, the new parity stored in the CM131is written to the parity FMPK144P.

Subsequently, the MP121clears the process stage information items stored in the SM132.

The above is the transition write process.

As described above, even when the MP fault occurs in the post-parity generation stage, the other MPs121free from faults can take over the write process to perform the transition write process. Similarly, data loss does not occur even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, and the plurality of BEPKs140. Thus, the reliability of the storage system10can be improved. In the case where the process stage information obtained upon the occurrence of the MP fault indicates the post-parity generation stage, the MP121free of faults takes over the write process, from the point where the new user data is written to the data FMPK144A and the new parity is written to the parity FMPK144P.

Operations by FMPK144Based on Command, According to Embodiment 2

An operation by the FMPK144based on each command is described hereinafter.

FIG. 59shows an operation performed based on the normal read command, according to Embodiment 2. In the following description, the logical page that is designated by a command sent from the controller100to the FMPK144is referred to as “target logical page.” Of the entries of the pointer table shown in the memory1445of the FMPK144, the entry corresponding to the target logical page is referred to as “target entry1449.” The target entry1449has a field for a logical page address, which is a logical address designating the target logical page, and a field for a physical page address, which is a physical address designating a physical page corresponding to the target logical page. In the diagram and the following description, in the target entry1449, the logical page address is called “LA,” and the old physical page address is called “PA.” In addition, the value of the logical page address is described as “LBA xxxx,” and the values of the physical page address are described as “p0” and “p1.”

In Embodiment 2, the FMPK144receiving the normal read command is the same as the other data FMPK144E. First, the other data FMPK144E receives the normal read command from the BEPK140of the controller100(S7110). This normal read command designates the target logical page having the old data stored therein. The other data FMPK144E then reads the old data from the old physical page designated by the physical page address of the target entry1449(S7120). The other data FMPK144E then sends a data response including the old data to the controller100(S7130).

FIG. 60shows an operation performed based on the normal write command, according to Embodiment 2. In Embodiment 2, the FMPK144receiving the normal write command is the same as the data FMPK144A or the parity FMPK144P. First, the FMPK144A or144P receives the normal write command from the BEPK140of the controller100(S7210). This normal write command designates the target logical page having the old data stored therein, and accompanies the new data. The FMPK144A or144P then writes the new data into a new physical page different from the old physical page (S7220). The FMPK144A or144P then performs the pointer connection on the new data by designating the new physical page for the physical page address of the target entry1449(S7230). Subsequently, the FMPK144A or144P sends a normal end response to the controller100(S7240).

FIG. 61shows an operation performed based on the XDWRITE command, according to Embodiment 2. In Embodiment 2, the FMPK144receiving the XDWRITE command is the same as the data FMPK144A. First, the data FMPK144A receives the XDWRITE command from the BEPK140of the controller100(S7310). This XDWRITE command designates the target logical page having the old data stored therein, and accompanies the new data. The data FMPK144A then writes the new data into the new physical page different from the old physical page (S7320). Next, the data FMPK144A reads the old data stored in the old physical page and the new data stored in the new physical page, generates the intermediate parity using the XOR circuit1442, and writes the intermediate parity into the memory1445(S7330). The data FMPK144A then performs the pointer connection on the new data by designating the new physical page for the physical page address of the target entry1449(S7340). Subsequently, the FMPK144sends a normal end response to the controller100(S7350). With this XDWRITE command, the intermediate parity can be written into the memory1445and the new data can be determined, while reducing the load imposed on the CM131and the number of accesses to the data FMPK144A. In the present embodiment, the new data commit command (S3230and S3320) described in Embodiment 1 is not required for determining the data stored in the FMPK144.

FIG. 62shows an operation performed based on the XDREAD command, according to Embodiment 2. In Embodiment 2, the FMPK144receiving the XDREAD command is the same as the data FMPK144A in which the intermediate parity is written for the memory1445. First, the data FMPK144A receives the XDREAD command from the BEPK140of the controller100(S7410). This XDREAD command designates the address having the intermediate parity therein. The data FMPK144A then reads the intermediate parity stored in the memory1445(S7420). The data FMPK144A then sends a data response including the intermediate parity to the controller100(S7430).

FIG. 63shows an operation performed based on the XPWRITE command, according to Embodiment 2. In Embodiment 2, the FMPK144receiving the XPWRITE command is the same as the parity FMPK144P. First, the parity FMPK144P receives the XPWRITE command from the BEPK140of the controller100(S7510). This XPWRITE command designates the target logical page having the old parity stored therein, and accompanies the intermediate parity. The parity FMPK144P then writes the intermediate parity into the memory1445(S7520). Next, the parity FMPK144reads the old parity from the old physical page indicated by the physical page address of the target entry1449, reads the intermediate parity from the memory1445, generates the new parity using the XOR circuit1442, and writes the new parity into the new physical page different from the old physical page (S7530). The parity FMPK144P then performs the pointer connection on the new parity by designating the new physical page for the physical page address of the target entry1449(S7540). Subsequently, the parity FMPK144P sends an end response to the controller100(S7550). This XPWRITE process can generate and determine the new parity, while reducing the load imposed on the CM131and the number of accesses made to the data FMPK144A. In the present embodiment, the new data commit command (S3230and S3320) described in Embodiment 1 is not required for determining the data.

As with Embodiment 2, this embodiment illustrates a situation where the FMPK144supports the XOR function of the standard SCSI command. The rest of the configurations of the storage system10are the same as those described in Embodiment 1.

As with Embodiment 2, in the present embodiment the process information item stored in the SM132indicates “pre-parity generation stage,” “stage in process of data media update,” “stage in process of parity media update,” and “post-parity generation stage.”

Write Process According to Embodiment 3

A normal write process is now described.

FIG. 64shows a write process according to Embodiment 3. In this sequence diagram as well, the DFa and the DFb of the data FMPK144A represent the memory1445and the FM1443(physical page) of the data FMPK144A. Furthermore, the DFa and the DFb of the parity FMPK144P represent the memory1445and the FM1443(physical page) of the parity FMPK144P. The key components of the operations in this sequence diagram are the same as those shown in the sequence diagram illustrating the write process according to Embodiment 2.

First, the MP121performs the processes S2110to S2350, as in the write processes according to Embodiments 1 and 2. As in the write process according to Embodiment 2, the MP121accordingly changes the values of the process stage information items stored in the two SMs132corresponding to the regions of the two CMs131having the new user data stored therein, from the value corresponding to the pre-parity generation stage to the value corresponding to the stage in process of data media update. The present embodiment can cope with a simultaneous point of fault in the MP121or the CM131.

The MP121then sends the normal read command to the data FMPK144A (S6110). This normal read command designates the logical page having the old user data stored therein. The data FMPK144A accordingly reads the old user data and sends the old user data to the controller100. Consequently, the BEPK140writes the old user data into the buffer143and further writes the old user data into the two CMs131. Next, the MP121writes the value indicating the mid-stage of data media update into the process stage information items stored in the two SMs132corresponding to the two CMs131.

Subsequently, as in the write process according to Embodiment 2, the MP121sends the XDWRITE command to the data FMPK144A (S6210). This XPWRITE command designates the logical page having the old user data stored therein, and accompanies the new user data. Accordingly, in the data FMPK144A, the new user data is stored and the intermediate parity is stored in the memory1445.

Subsequently, as in the write process according to Embodiment 2, the MP121sends the XDREAD command to the data FMPK144A (S6220). This XDREAD command designates the logical page having the intermediate parity stored therein. Consequently, the intermediate parity is stored in the buffer143of the BEPK140.

The MP121then sends the normal read command to the parity FMPK144P (S6310). This normal read command designates the logical page having the old parity stored therein. The parity FMPK144P accordingly reads the old parity and sends the old parity to the controller100. Consequently, the BEPK140writes the old parity into the buffer143and further writes the old parity into the two CMs131. The MP121then changes the values of the process stage information items to the mid-stage of parity media update.

Subsequently, as in the write process according to Embodiment 2, the MP121sends the XPWRITE command to the parity FMPK144P (S6410). This XPWRITE command designates the logical page having the old parity stored therein, and accompanies the intermediate parity. Accordingly, the new parity is stored in the parity FMPK144P.

The MP121then clears the process stage information items stored in the SM132.

The Above is the Write Process.

As described above, the controller100writes the old user data received from the data FMPK144A and the old parity received from the parity FMPK144P into the CM131, but sends the intermediate parity from the buffer143to the parity FMPK144P without writing the intermediate parity received from the data FMPK144A into the CM131. Therefore, the number of accesses to the CM131during the write process becomes seven, thereby the number of accesses to the CM131can be reduced. Accordingly, the number of accesses to the CM131in the write process can be reduced, lowering the number of accesses to the CM131and improving the write process performance of the storage system.

In addition, according to the present embodiment, the new user data, the old user data, the old parity, and each of the process stage information items are stored in the two CMPKs130. Therefore, even when one of the data items is lost, the other data can be used, improving the reliability of the storage system10.

Transition Write Process According to Embodiment 3

Several specific examples of the transition write process are now described.

First Specific Example of Transition Write Process According to Embodiment 3

Here is described the transition write process that is performed upon the occurrence of the MP fault in the pre-parity generation stage.

FIG. 65shows a transition write process performed upon the occurrence of an MP fault in the pre-parity generation stage, according to Embodiment 3. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes the MP121having a fault, the MP121acknowledges that each process stage information item indicates the pre-parity generation stage. The MP121accordingly performs the processes S6110to S6410, as in the normal write process. In other words, the MP121free of faults takes over the write process, from the point where the XDWRITE command is sent to the data FMPK144A (S6210). Because the new user data is stored in the CM131, the BEPK140, in response to the instruction from the MP121, reads the new user data from the CM131, writes the new user data into the buffer143, reads the new user data from the buffer143, and sends the new user data to the data FMPK144A. As a result, the MP121free of faults can take over the write process and perform the write process successfully.

The MP121then clears the process stage information items stored in the SM132.

The Above has Described the Transition Write Process.

As described above, even when the MP fault occurs in the pre-parity generation stage, the other MPs121free from faults can take over the write process to perform the transition write process on the basis of the process stage information.

Second Specific Example of Transition Write Process According to Embodiment 3

Here is described the transition write process that is performed upon the occurrence of the MP fault in the mid-stage of data media update.

FIG. 66shows a transition write process performed upon the occurrence of the MP fault in the mid-stage of data media update, according to Embodiment 3. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes an MP fault, the MP121acknowledges that each process stage information indicates the data media update. The MP121accordingly sends the normal write command to the data FMPK144A (S6010). This normal write command accompanies the old user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the old user data from the CM131, writes the old user data into the buffer143, reads the old user data from the buffer143, and sends the old user data to the data FMPK144A.

The MP121then performs the processes S6110to S6410, as in the normal wrote process. In other words, when the process stage information item indicates the stage in process of data media update, the MP121free of faults takes over the write process, from the stage where the normal read command is sent to the data FMPK144A (S6110).

Subsequently, the MP121clears the process stage information items stored in the SM132.

The above is the transition write process.

As described above, even when the MP fault occurs in the mid-stage of data media update, the other MPs121free from faults can take over the write process to perform the transition write process on the basis of the process stage information.

Third Specific Example of Transition Write Process According to Embodiment 3

Here is described a transition write process performed upon the occurrence of the MP fault in the mid-stage of parity media update.

FIG. 67shows a transition write process performed upon the occurrence of the MP fault in the mid-stage of parity media update, according to Embodiment 3. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes an MP having a fault, the MP121acknowledges that each process stage information item indicates the stage in process of parity media update. The MP121accordingly reads the old user data, the old parity, and the new user data stored in the CM131, generates the new parity by means of the XOR operation, and writes the new parity into the two CMs131(S6020). In other words, when each process stage information item indicates the stage in process of parity media update, the MP121free of faults takes over the write process, from the point where the new parity is generated from the old user data, the old parity, and the new user data that are stored in the CM131.

The MP121then performs the process S6410, as in the normal write process.

Subsequently, the MP121clears the process stage information items stored in the SM132.

The above is the transition write process.

As described above, even when the MP fault occurs in the mid-stage of parity media update, the other MPs121free from faults can take over the write process to perform the transition write process on the basis of the process stage information.

In this embodiment, the storage device of the storage unit200is not limited to the FM1443.

According to this embodiment, the simultaneous point of fault occurring in the MPPKs120and the FMPKs144configuring the RAID groups in process of destaging can be tolerated, preventing the occurrence of data loss. Destaging here means writing the data stored in the CM131into the FM1443of the FMPK144. Similarly, even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs140, and the plurality of FMPKs144, data loss does not occur. Therefore, the reliability of the storage system10can be improved. Therefore, the reliability of the storage system10can be improved.

The rest of the configurations of the storage system10are the same as those described in Embodiment 1.

Write Process According to Embodiment 4

A normal write process is now described.

FIG. 68shows a write process according to Embodiment 4. The operation targets in this sequence diagram are the same as those shown in the sequence diagram illustrating the write process according to Embodiment 1.

In the present embodiment, an old data transmission command, new data transmission command, and new data commit command are defined as the I/O commands sent from the controller100to the FMPKs144. Moreover, in the present embodiment, the process stage information items stored in the SMs132indicate the pre-parity generation and post-parity generation stages.

For the purpose of illustration, the state of the parity FMPK144P in the write process is referred to as “FMPK state.” Several states of the FMPK144are defined hereinafter.

First, the MP121performs the processes S2110to S2350, as in the write process according to Embodiment 1. The MP121accordingly registers the values of the process stage information items stored in the two SMs132, as the pre-parity generation stage, as in the write process according to Embodiment 1.

The MP121then sends the normal read command to the data FMPK144A (S8110). This normal read command designates the logical page having the old user data stored therein. Accordingly, the data FMPK144A reads the old user data from the FM1443, sends the old user data to the controller100, and notifies the controller100of a normal end of the normal read command.

At this moment, the BEPK140receives the old user data from the data FMPK144A, and writes the old user data into the buffer143.

Subsequently, the MP121is notified by the data FMPK144A of the normal end of the normal read command.

The state of the parity FMPK144P obtained at this moment is referred to as “FMPK state 1a.”FIG. 71shows the FMPK state of the parity FMPK144P.

The MP121then sends the old data transmission command to the parity FMPK144P (S8120). This old data transmission command designates the logical page having the old parity stored therein, and accompanies the old user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the old user data from the buffer143, and sends the old user data to the parity FMPK144P. Because the MPPK120is coupled to the CMPK130and the BEPK140by the internal networks, the MPPK120can control storage of data in the CMPK130and the BEPK140. Therefore, after being read from the data FMPK144and stored in the buffer of the BEPK140, the old user data can be transferred to the parity FMPK144P without being stored in the CM131, reducing the access load imposed on the CM131.

Subsequently, the parity FMPK144P receives the old data transmission command and the old user data from the controller100. The parity FMPK144P accordingly writes the old user data into the FM1443, and notifies the controller100of a normal end of the old data transmission command.

Thereafter, the MP121is notified by the parity FMPK144P of the normal end of the old data transmission command.

The state of the parity FMPK144P obtained at this moment is referred to as “FMPK state 2a.”FIG. 72shows the FMPK state of the parity FMPK144P.

Accordingly, the MP121sends the new data transmission command to the parity FMPK144P (S8130). This new data transmission command designates the logical page having the old user data and the old parity stored therein, and accompanies the new user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the new user data from the CM131, writes the new user data into the buffer143, reads the new user data from the buffer143, and sends the new user data to the parity FMPK144P.

Next, the parity FMPK144P receives the new data transmission command and the new user data from the controller100. The operations performed by the FMPK144P based on the new data transmission command in this embodiment are different from those described in Embodiment 1. Consequently, the parity FMPK144P writes the new user data into the memory1445, reads the old user data and the old parity from the FM1443, generates the new parity by means of the XOR circuit1442, and writes the new parity into the FM1443. The parity FMPK144P then notifies the controller100of a normal end of the new data transmission command.

The MP121is then notified by the parity FMPK144P of the normal end of the new data transmission command. Accordingly, the MP121changes the value of each process stage information item to the post-parity generation stage.

The state of the parity FMPK144P obtained at this moment is referred to as “FMPK state 3a.”FIG. 73shows the FMPK state of the parity FMPK144P.

Subsequently, the MP121sends the normal write command to the data FMPK144A (S8140). This normal write command accompanies the new user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the new user data from the buffer143, and sends the new user data to the data FMPK144A. At this moment, the BEPK140transmits the new user data, which is stored in the buffer in S8130, to the data FMPK144A. Since the MPPK120can control the CMPK130and the BEPK140, it is not necessary to read the new user data from the CMPK130again. Therefore, the access load imposed on the CMPK130can be reduced.

Next, the data FMPK144A receives the normal write command and the new user data from the controller100. The data FMPK144A accordingly writes the new user data into the FM1443, and notifies the controller100of a normal end of the normal write command. The normal write command is processed in the same manner as shown inFIG. 31.

Subsequently, the MP121is notified by the data FMPK144A of the normal end of the normal write command. Accordingly, the MP121sends the new data commit command to the parity FMPK144P (S8150). This new data commit command designates the logical page having the new parity stored therein.

Next, the parity FMPK144P receives the new data commit command from the controller100. Accordingly, the parity FMPK144P determines the new parity as the parity after update, and notifies the controller100of a normal end of the new data commit command.

Then, the MP121is notified by the parity FMPK144P of the normal end of the new data commit command. Accordingly, the MP121clears the value of each process stage information item.

The Above is the Write Process.

In this manner, the controller100sends the old user data from the buffer143to the parity FMPK144P without writing the old user data received from the data FMPK144A into the CM131. As a result, the number of accesses to the CM131during the write process becomes three, thereby the number of accesses to the CM131can be reduced.

According to this embodiment, the reliability of the storage system10can be improved by storing the new user data and each process stage information item in the two CMPKs130.

Specific Examples of Transition Write Process According to Embodiment 4

Several specific examples of the transition write process performed upon the occurrence of an MP fault are now described hereinafter. By storing the process stage information item in the SM132at an appropriate stage, another MP121free of faults can take over the write process when a fault occurs in a certain MP121, without causing data loss.

First Specific Example of Transition Write Process According to Embodiment 4

Here is described a transition write process that is performed upon the occurrence of the MP fault in the pre-parity generation stage.

FIG. 69shows the transition write process performed upon the occurrence of the MP fault in the pre-parity generation stage, according to Embodiment 4. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes the MP121fault, the MP121acknowledges that each process stage information item of the SM132indicates the pre-parity generation stage. Accordingly, the MP121performs the processes S8110to S8150, as in the normal write process.

The MP121then clears the process stage information items stored in the SM132.

The above is the first specific example of the transition write process. In the present embodiment, it is guaranteed that the old user data existing in the data FMPK144A can be read as long as the process stage information item indicates the pre-parity generation stage. Therefore, the MP121that carries out the transition process can take over the write process, from the point where the old user data is read (S8110), and complete the write process.

Second Specific Example of Transition Write Process According to Embodiment 4

FIG. 70shows a transition write process performed upon the occurrence of the MP fault in the post-parity generation stage, according to Embodiment 4. The operation targets shown in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes a fault in another MP121, the MP121acknowledges that each process stage information item of the SM132indicates the post-parity generation stage. Accordingly, the MP121transfers the new user data from the CM131to the BEPK140and performs the processes S8140and S8150, as in the normal write process.

The MP121then clears the process stage information items.

The above is the second specific example of the transition write process. In the present embodiment, it is guaranteed that the new parity is written into the physical page of the parity FMPK144P as long as the process stage information item indicates the post-parity generation stage. Therefore, the MP121that carries out the transition process can take over the write process, from the point where the new user data is written (S8140), and complete the write process.

According to this embodiment, the other MPs121can take over the write process to perform the transition write process, even when the MP fault occurs in the pre-parity generation stage or the post-parity generation stage. Similarly, data loss does not occur even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs140and the plurality of FMPKs144.

Write Process to FMPK144According to Embodiment 4

The FMPK states in the aforementioned write process are now described hereinafter.

The FMPK144here is the same as the parity FMPK144P.

FIG. 71shows a state of the parity FMPK144P in the FMPK state 1a according to Embodiment 4. In the following description, the logical page that is designated by a command sent from the controller100to the parity FMPK144P is referred to as “target logical page.” Of the entries of the pointer table shown in the memory1445of the FMPK144, the entry corresponding to the target logical page is referred to as “target entry1449.” The target entry1449has a field for a logical page address, which is a logical address designating the target logical page, a field for an old physical page address, which is a physical address designating an old physical page, a field for a new physical page address, which is a physical address designating a new physical page, and a field for a temporary physical page address, which is a physical address designating a temporary physical page. In the diagram and the following description, in the target entry1449, the logical page address is called “LA,” the old physical page address “oPA,” the new physical page address “nPA,” and the temporary physical page address “tPA.” In addition, the value of the logical page address is described as “LBA xxxx,” and the values of the old physical page address, the new physical page address, and the temporary physical page address are described as “p0,” “p1,” “p2,” “p3,” and “p4.”

In the parity FMPK144P under the FMPK state 1a, the old parity is stored in the old physical page. Furthermore, the logical page address and the old physical page address are associated with each other and stored in the target entry1449.

FIG. 72shows an FMPK state 2a according to Embodiment 4. In the parity FMPK144P under the FMPK state 2a, the old parity is stored in the old physical page, and the old user data is stored in the temporary physical page. The correspondence relationship among the logical page address, the old physical page address, and the temporary physical page address is stored in the target entry1449.

FIG. 73shows an FMPK state 3a according to Embodiment 4. In the parity FMPK144P under the FMPK state 3a, the old data is stored in the old physical page, the old user data is stored in the temporary physical page, and the new parity in the new physical page. The correspondence relationship among the logical page address, the old physical page address, the temporary physical page address, and the new physical page address is stored in the target entry1449.

Operations by FMPK144Based on Commands, According to Embodiment 4

Next are described operations that are performed in Embodiment 4 by the FMPK144under the FMPK states and based on commands upon the occurrence of system faults under the FMPK states.

FIG. 74shows an operation performed based on the old data transmission command under the FMPK state 1a, according to Embodiment 4. First, the parity FMPK144P receives the old data transmission command from the BEPK140of the controller100(S9110). This old data transmission command accompanies the old user data. The parity FMPK144P then writes the old user data into the temporary physical page different from the old physical page (S9120). Next, the parity FMPK144P performs the pointer connection on the old user data by designating the temporary physical page for the temporary physical page address of the target entry1449(S9130). The parity FMPK144P then sends a normal end response to the controller100(S9140). With the old data transmission command, the parity FMPK144P can write the received data into the physical page different from the old parity, without overwriting the data into the old parity. As a result of transmitting the old data transmission command to the parity FMPK in the FMPK state 1a, the FMPK state transits to the FMPK state 2a.

FIG. 75shows an operation performed by the parity FMPK144P under the FMPK state 2a based on the old data transmission command, according to Embodiment 4. First, the parity FMPK144P receives the old data transmission command from the BEPK140of the controller100(S9210). This old data transmission command accompanies the old user data. The parity FMPK144P then secures an additional temporary physical page, which is a physical page different from the temporary physical page, and writes the old user data into the additional temporary physical page (S9220). Subsequently, the parity FMPK144P performs the pointer replacement for replacing the first temporary data of the temporary physical page with the first temporary data of the additional temporary physical page, by designating the additional temporary physical page for the temporary physical page address of the target entry1449(S9230). The parity FMPK144P then sends a normal end response to the controller100(S9240). This process is carried out during the transition write process when a fault occurs after the transmission of the old data (S8120) in the pre-parity generation stage. In other words, even when the old data transmission command is transmitted to the parity FMPK in the FMPK state 2a, the state same as the FMPK state 2a can be obtained.

FIG. 76shows an operation performed based on the old data transmission command in the parity FMPK144P under the state 3a, according to Embodiment 4. First, the FMPK144receives the old data transmission command from the BEPK140of the controller100(S9310). This old data transmission command accompanies the first temporary data. The parity FMPK144P then writes the first temporary data into the additional temporary physical page (S9320). Subsequently, the parity FMPK144P performs the pointer replacement for replacing the first temporary data of the temporary physical page with the first temporary data of the additional temporary physical page, by designating the additional temporary physical page for the temporary physical page address of the target entry1449(S9330). Then, the parity FMPK144P sends a normal end response to the controller100(S9340). This process is carried out during the transition write process when a fault occurs after the transmission of the new data (S8130) in the pre-parity generation stage. In other words, even when the old data transmission command is transmitted to the parity FMPK in the FMPK state 3a, the state same as the FMPK state 3a can be obtained.

FIG. 77shows an operation performed based on the new data transmission command under the FMPK state 1a, according to Embodiment 4. First, the parity FMPK144P receives the new data transmission command from the BEPK140of the controller100(S9410). This new data transmission command accompanies second temporary data. The second temporary data is the same as the new user data obtained in the aforementioned write process. The FMPK144then sends an abnormal end response to the controller100(S9420).

FIG. 78shows an operation performed based on the new data transmission command under the FMPK state 2a, according to Embodiment 4. First, the parity FMPK144P receives the new data transmission command from the BEPK140of the controller100(S9510). This new data transmission command accompanies the new user data. The FMPK144then writes the new user data into the memory1445(S9520). Next, the FMPK144reads the old parity in the old physical page and old user data in the temporary physical page, and the new user data stored in the memory1445, generates the new parity by means of the XOR circuit1442, and writes the new data into the new physical page (S9530). Subsequently, the FMPK144performs the pointer connection on the new parity by designating the new physical page for the new physical page address of the target entry1449(S9540). The FMPK144then sends a normal end response to the controller100(S9550). As a result of transmitting the new data transmission command to the parity FMPK in the FMPK state 2a, the FMPK state transits to the FMPK state 3a.

FIG. 79shows an operation performed based on the new data transmission command under the FMPK state 3a, according to Embodiment 4. First, the parity FMPK144P receives the new data transmission command from the BEPK140of the controller100(S9610). This new data transmission command accompanies the new user data. The FMPK144then writes the new user data into the memory1445(S9620). The parity FMPK144P then reads the old data stored in the old physical page, the old user data stored in the temporary physical page, and the new user data stored in the memory1445, generates the new data by means of the XOR circuit1442, secures an additional physical page, which is a physical page different from the new physical page, and writes the new data into the additional physical page (S9630). Subsequently, the parity FMPK144P performs the pointer replacement for replacing the new data stored in the new physical page with the new data stored in the additional physical page, by designating the additional physical page for the new physical page address of the target entry1449(S9640). Subsequently, the parity FMPK144P sends a normal end response to the controller100(S9650). This process is carried out during the transition write process, subsequent to the one shown inFIG. 76, when a fault occurs after the transmission of the new data (S8130) in the pre-parity generation stage. In other words, even when the old data transmission command is transmitted to the parity FMPK in the FMPK state 3a, the same FMPK state 3a can be obtained.

In this manner, regardless of the presence/absence of a system fault, the MP121can change the FMPK state to the FMPK state 3a by issuing the command from the old data reading process, as long as the process stage information item indicates the pre-parity generation stage.

FIG. 80shows an operation performed based on the new data commit command under the state 1a, according to Embodiment 4. First, the parity FMPK144P receives the new data commit command from the BEPK140of the controller100(S9710). The new data commit command designates the logical page in which the new data is stored. The parity FMPK144P then sends a normal end response to the controller100(S9720). This process is carried out during the transition write process when a fault occurs after the transmission of the new data commit command (S8150) in the post-parity generation stage.

FIG. 81shows an operation performed based on the new data commit command under the state 2a, according to Embodiment 4. First, the parity FMPK144P receives the new data commit command from the BEPK140of the controller100(S9810). This new data commit command designates the logical page having the new data stored therein. The parity FMPK144P then sends an abnormal end response to the controller100(S9820).

FIG. 82shows an operation performed based on the new data commit command under the state 3a, according to Embodiment 4. First, the parity FMPK144P receives the new data commit command from the BEPK140of the controller100(S9910). This new data commit command designates the logical page in which the new data is stored. The parity FMPK144P then performs the pointer replacement for replacing the old data stored in the old physical page with the new data stored in the new physical page, by designating the new physical page for the old physical page address of the target entry1449, and performs the pointer deletion on the first temporary data stored in the temporary physical page, by clearing the temporary physical page address (S9920). Next, the parity FMPK144P sends a normal end response to the controller100(S9930). As a result of this process, the state can transit to a state in which the new parity is determined in the parity FMPK144P, even upon the occurrence of a fault prior to the transmission of the new data commit command in the post-parity generation stage. In this manner, defining each of the commands can allow the process to be taken over even upon the occurrence of a system fault and prevent the occurrence of data loss. In addition, in the present embodiment, when the process stage information item indicates the two stages, “pre-parity generation stage” and “post-parity generation stage,” the process is taken over upon the occurrence of a fault, whereby the number of accesses to the SM132for recording the process stage information item therein and the access load can be reduced.

This embodiment has the same functions as those described in Embodiment 2 but illustrates a situation where the XOR circuit1442of the FMPK144supports only an XPWRITE function of the SCSI command. Furthermore, in the present embodiment, the process stage information item stored in the SM132indicates the pre-parity generation stage, the stage in process of parity media update, and the post-parity generation stage.

Write Process According to Embodiment 5

A normal write process is now described hereinafter.

FIG. 83shows a write process according to Embodiment 5. In this sequence diagram, the DFa and DFb of the data FMPK144A represent the memory1445and the FM1443(physical page) of the data FMPK144A. Also, the DFa and the DFb of the parity FMPK144P represent the memory1445and the FM1443(physical page) of the parity FMPK144P. The key components of the operations shown in this sequence diagram are the same as those shown in the sequence diagrams related to the write process according to Embodiment 2.

First, the MP121performs the processes S2110to S2350, as in the write process according to Embodiment 1. The MP121accordingly changes the values of the process stage information items of the two SMs132corresponding to the regions of the two CMs131having the new user data stored therein, to the pre-parity generation, as in the write process according to Embodiment 1.

The MP121then performs the process S8110, as in the write process according to Embodiment 4. Consequently, the BEPK140receives the old user data from the data FMPK144A and writes the old user data into the buffer143. The MP121accordingly changes the value of each process stage information to the parity media update.

Subsequently, the MP121sends the XPWRITE command to the parity FMPK144P (S8320). This XPWRITE command designates the logical page having the old parity stored therein, and accompanies the old user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the old user data from the buffer143, and sends the old user data to the parity FMPK144P.

Subsequently, the parity FMPK144P receives the XPWRITE command and the old user data from the controller100. The parity FMPK144P accordingly writes the old user data into the memory1445, reads the old parity from the FM1443, reads the old user data from the memory1445, generates the intermediate parity using the XOR circuit1442, and writes the intermediate parity into the memory1445of the FM1443. The parity FMPK144P then notifies the controller100of a normal end of the XPWRITE command.

Subsequently, the MP121is notified by the parity FMPK144P of the normal end of the XPWRITE command.

Accordingly, the MP121sends the XPWRITE command to the parity FMPK144P (S8330). This XPWRITE command designates the physical address of the memory1445having the intermediate parity stored therein, and accompanies the new user data. At this moment, in response to an instruction from the MP121, the BEPK140reads the new user data from the CM131, writes the new user data into the buffer143, reads the new user data from the buffer143, and sends the new user data to the parity FMPK144P.

Next, the parity FMPK144P receives the XPWRITE command and the new user data from the controller100. The parity FMPK144P accordingly writes the new user data into the memory1445, reads the intermediate parity from the memory1445, reads the new user data from the memory1445, generates the new parity from the intermediate parity and the new user data by means of the XOR circuit1442, and writes the new parity into the FM1443. The parity FMPK144P then notifies the controller100of a normal end of the XPWRITE command.

Subsequently, the MP121is notified by the parity FMPK144P of the normal end of the XPWRITE command. The MP121accordingly changes the value of each process stage information item to the post-parity generation stage.

The MP121then sends the normal write command to the data FMPK144A (S8340). This normal write command accompanies the new user data.

The data FMPK144A then receives the normal write command and the new user data from the controller100. The data FMPK144A accordingly writes the new user data into the FM1443and notifies the controller100of a normal end of the normal write command.

Subsequently, the MP121is notified by the data FMPK144A of the normal end of the normal write command. The MP121accordingly clears the value of each process stage information item.

The Above is the Write Process.

In this manner, the controller100sends the old user data from the buffer143to the parity FMPK144P without writing the old user data received from the data FMPK144A into the CM131. As a result, the number of accesses to the CM131during the write process is reduced, thereby the number of accesses to the CM131can be reduced.

Moreover, according to this embodiment, the reliability of the storage system10can be improved by storing the new user data and each process stage information item into the two CMPKs130.

Specific Examples of Transition Write Process According to Embodiment 5

Several specific examples of a transition write process performed upon the occurrence of an MP fault are described hereinafter.

First Specific Example of Transition Write Process According to Embodiment 5

Here is described a transition write process that is performed upon the occurrence of an MP fault in the pre-parity generation stage.

FIG. 84shows the transition write process performed upon the occurrence of the MP fault in the pre-parity generation stage, according to Embodiment 5. The operation targets shown in this sequence diagram are the same as those illustrated in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes a fault in another MP121, the MP121acknowledges that the process stage information item indicates the pre-parity generation stage. Accordingly, the MP121performs the processes S8110to S8340, as in the normal write process. In other words, when the process stage information item indicates the pre-parity generation stage, the MP121takes over the write process, from the point where the old user data is transmitted from the data FMPK144A to the buffer143of the BEPK140.

Subsequently, the MP121clears the process stage information item stored in the SM132.

The above is the transition write process.

Second Specific Example of Transition Write Process According to Embodiment 5

Here is described a transition write process that is performed upon the occurrence of the MP fault in the mid-stage of parity media update.

FIG. 85shows the transition write process performed upon the occurrence of the MP fault in the mid-stage of parity media update, according to Embodiment 5. The key operation targets illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes the fault occurring in another MP, the MP121acknowledges that the process stage information items indicate the mid-stage of parity media update. Accordingly, the MP121performs the processes S6510and S6520, as in the transition write process that is performed upon the occurrence of the MP fault in the mid-stage of parity media update according to Embodiment 2 (seeFIG. 56). In other words, the MP121free from faults takes over a write process from a process of generating a new parity.

The MP121then sends the normal write command to the parity FMPK144P (S8360). This normal write command accompanies the new parity. Consequently, the BEPK140writes the new parity stored in the CM131into the buffer143, and sends the new parity to the parity FMPK144P. The parity FMPK144P accordingly writes the new parity into the FM1443.

Subsequently, the MP121is notified by the parity FMPK144P of a normal end of the normal write command. The MP121accordingly changes the value of each process stage information item to the post-parity generation.

The MP121then sends the normal write command to the data FMPK144A (S8370). The normal write command accompanies the new user data. Consequently, the BEPK140writes the new user data stored in the CM131into the buffer143, and sends the new user data to the data FMPK144A. The data FMPK144A accordingly writes the new user data into the FM1443.

Subsequently, the MP121clears each process stage information item stored in the SM132.

The above is the transition write process.

Third Specific Example of Transition Write Process According to Embodiment 5

Here is described a transition write process that is performed upon the occurrence of the MP fault in the post-parity generation stage.

FIG. 86shows a transition write process performed upon the occurrence of the MP fault in the post-parity generation, according to Embodiment 5. The key components of the operations illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes the MP fault, the MP121acknowledges that the process stage information items indicate the post-parity generation. Accordingly, the MP121performs the process S8370, as in the aforementioned transition write process that is performed upon the occurrence of the MP fault in the parity media update. In other words, the MP121free of faults takes over the write process, from the point where the normal write command is sent to the data FMPK144A (S8370).

Subsequently, the MP121clears the process stage information item stored in the SM132.

The above is the transition write process.

According to these transition write processes (the first specific example to the third specific example), even when the MP fault occurs in the pre-parity generation stage, the stage in process of parity media update, or the post-parity generation stage, which are indicated by the process stage information item, in the present embodiment another MP121free of faults can take over the write process to perform the transition write process. Similarly, data loss does not occur in the present embodiment even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, and the plurality of BEPKs140. Therefore, the reliability of the storage system10can be improved.

In addition, this embodiment can realize the same functions as those described in Embodiment 2, by using the XPWRITE function of the FMPK144.

This embodiment has the same configurations as those described in Embodiment 5, and illustrates a situation where the reliability of the storage system10is improved more than by Embodiment 5. In this embodiment, the process stage information item stored in the SM132indicates the pre-parity generation stage, the stage in process of parity media update, and the post-parity generation stage.

Write Process According to Embodiment 6

A normal write process is described hereinafter.

FIG. 87shows a write process according to Embodiment 6. The operation targets illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the write process according to Embodiment 2.

First, the MP121performs the processes S2110to S2350, as in the write process according to Embodiment 1. The MP121accordingly changes the values of the process stage information items of the two SMs132corresponding to the two CMs131having the new user data stored therein, to the pre-parity generation.

The MP121then performs the process S6310, as in the write process according to Embodiment 3. Accordingly, the old parity stored in the parity FMPK144P is written to the buffer143.

Subsequently, the MP121performs the process S8110, as in the write processes according to Embodiment 4 and Embodiment 5. Accordingly, the old user data stored in the data FMPK144A is written to the buffer143. The MP121accordingly changes the value of each process stage information item to the of parity media update.

The MP121then performs the processes S8320to S8340, as in the write process according to Embodiment 5. Accordingly, the intermediate parity is generated in the parity FMPK144P and written to the memory1445. Additionally, the new user data stored in the CM131is written into the buffer143. The new parity is generated in the parity FMPK144P and written into the FM1443.

Accordingly, the MP121clears each process stage information item stored in the SM132.

The Above is the Write Process.

In this manner, the controller100sends the old user data from the buffer143to the parity FMPK144P without writing the old user data received from the data FMPK144A into the CM131. As a result, the number of accesses to the CM131during the write process is reduced.

Furthermore, according to this embodiment, the reliability of the storage system10can be improved by storing the new user data, each process stage information, and the old parity in the two CMPKs130.

Specific Examples of Transition Write Process According to Embodiment 6

Several specific examples of a transition write process performed upon the occurrence of an MP fault are now described hereinafter.

First Specific Example of Transition Write Process According to Embodiment 6

Here is described a transition write process that is performed upon the occurrence of an MP fault in the pre-parity generation stage.

FIG. 88shows a transition write process performed upon the occurrence of the MP fault in the pre-parity generation stage, according to Embodiment 6. The operation targets illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes a fault occurring in another MP121, the MP121acknowledges that the process stage information item indicates the pre-parity generation stage. Accordingly, the MP121performs the processes S6310to S8340, as in the normal write process. In other words, the MP121free of faults takes over the write process, from the point where the old parity stored in the parity FMPK144P is written to the buffer143.

The MP121accordingly clears the process stage information item stored in the SM132.

The above is the transition write process.

Second Specific Example of Transition Write Process According to Embodiment 6

Here is described a transition write process that is performed upon the occurrence of the MP fault in the mid-stage of parity media update.

FIG. 89shows a transition write process performed upon the occurrence of the MP fault in the mid-stage in process of parity media update, according to Embodiment 6. The key components of the operations illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes a fault occurring in another MP121, the MP121acknowledges that the process stage information item indicates the stage in process of parity media update. Accordingly, the MP121sends the normal write command to the parity FMPK144P (S8210). In other words, the MP121free of faults takes over the write process, from the point where the normal write command is sent to the parity FMPK144P. This normal write command accompanies the old parity. Consequently, the BEPK140writes the old parity stored in the CM131into the buffer143, and sends the old parity to the parity FMPK144P. Accordingly, the parity FMPK144P writes the old parity into the FM1443.

The MP121is then notified by the parity FMPK144P of a normal end of the normal write command. Accordingly, the MP121sends the XPWRITE command to the parity FMPK144P (S8220). This normal write command accompanies the old user data. Accordingly, the BEPK140writes the old user data stored in the CM131into the buffer143, and sends the old user data to the data FMPK144A. The parity FMPK144P accordingly writes the old user data into the memory1445, generates the intermediate parity from the old parity stored in the FM1443and the old user data stored in the memory1445, and writes the intermediate parity into the FM1443.

Subsequently, the MP121is notified by the parity FMPK144P of a normal end of the XPWRITE command. The MP121accordingly performs the S8330and S8340, as in the normal write process.

Accordingly, the MP121clears each process stage information item stored in the SM132.

The above is the transition write process.

Third Specific Example of Transition Write Process According to Embodiment 6

Here is described a transition write process that is performed upon the occurrence of an MP fault in the post-parity generation stage.

FIG. 90shows a transition write process performed upon the occurrence of the MP fault in the post-parity generation stage, according to Embodiment 6. The operation targets illustrated in this sequence diagram are the same as those shown in the sequence diagrams related to the normal write process.

Once the MP121free of faults recognizes a fault has occurred in the MP121, the MP121acknowledges that the process stage information items indicate the post-parity generation stage. Accordingly, the MP121then sends the normal write command to the data FMPK144A (S8230). The MP121free of faults takes over the write process, from the point where the normal write command is sent to the data FMPK144A. This normal write command accompanies the new user data.

Subsequently, the data FMPK144A receives the normal write command and the new user data from the controller100. The data FMPK144A accordingly writes the new user data stored in the CM131into the FM1443, and notifies the controller100of a normal end of the normal write command.

Subsequently, the MP121is notified by the data FMPK144A of the normal end of the normal write command. The MP121accordingly clears the value of each process stage information item stored in the SM132.

The above is the transition write process.

According to these transition write processes (first to third specific examples), even when the MP fault occurs in the pre-parity generation stage, the mid-stage of the parity media update, or the post-parity generation stage, the other MPs121free from faults can take over the write process to perform the transition write process. Similarly, data loss does not occur even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs1440, and the plurality of FMPKs144. Therefore, the reliability of the storage system10can be improved.

This embodiment can realize the same functions as those described in Embodiment 2, by using the XPWRITE function of the FMPK144. Moreover, this embodiment can improve the reliability of the storage system10better than by Embodiment 5, by writing the old parity into the two CMs131.

This embodiment illustrates a situation where Embodiment 1 is applied to RAID level 6.

The controller100uses the plurality of FMPKs144to construct a RAID group of RAID level 6. This RAID group uses a Reed-Solomon method. A P parity and Q parity are obtained by the following formulae by using the user data D[0], D[1], . . . , D[n−1], and Q parity generation coefficients A[0], A[1], A[n−1]:
P=D[0]+D[1]+ . . . +D[n−1]  (Ep)
Q=A[0]*D[0]+A[1]*D[1]+ . . . +A[n−1]*D[n−1]  (Eq)

The memory1445of the FMPK144has A[i] stored therein, where i is a data row number within the stripe (i=0, 1, . . . , n−1). A[i] may be stored in the XOR circuit1442.

Write Process According to Embodiment 7

A normal write process is now described hereinafter.

In the diagrams, the write process according to Embodiment 7 is divided into a first process and a second process.FIG. 91shows the first process of the write process according to Embodiment 7.FIG. 92shows the second process of the write process according to Embodiment 7.

In the following description, the P parity generated from the old user data is referred to as “old parity,” the Q parity generated from the old user data as “old Q parity,” the P parity generated from the new user data as “new parity,” and the Q parity generated from the new user data as “new Q parity.”

In the following description, of the plurality of FMPKs144configuring the RAID group, the FMPK144having the old party stored therein is referred to as “parity FMPK144P,” and the FMPK144having the old Q parity stored therein is referred to as “parity FMPK144Q.” The configurations other than that of the parity FMPK144Q in the storage system10are the same as those described in Embodiment 1. The controller100sends information indicating the data row number to the parity FMPK144Q so that the parity FMPK144Q specifies the A[i].

In this embodiment, a Q parity intermediate parity transmission command is newly defined as the I/O command sent from the controller100to the FMPK144.

Each of the operation targets illustrated in the sequence diagram of the first process are the same as each of the operation targets illustrated in the sequence diagram related to the write process according to Embodiment 1. The operation targets illustrated in the sequence diagram of the second process are, in addition to the operation targets illustrated in the sequence diagram of the first process, the port1441within the parity FMPK144Q, the XOR circuit1442within the parity FMPK144Q, and storage media QFa and QFb within the parity FMPK144Q. The storage media QFa and QFb of the parity FMPK144Q respectively represent two physical pages stored in the FM1443.

The first process of the write process is described hereinafter.

First, MP121performs the processes S2110to S3120, as in the write process according to Embodiment 1. Accordingly, the buffer143of the BEPK140has the intermediate parity stored therein. Furthermore, the FM1443of the parity FMPK144P has the old parity and the new parity stored therein.

The second process of the write process is described hereinafter.

Subsequently, the MP121sends the Q parity intermediate parity transmission command to the parity FMPK144Q (S9110). This Q parity intermediate parity transmission command designates the logical page having the old Q parity stored therein, and accompanies the intermediate parity and the data row number. At this moment, in response to an instruction from the MP121, the BEPK140reads the intermediate parity from the buffer143, and sends the intermediate parity to the parity FMPK144Q.

The parity FMPK144Q then receives the Q parity intermediate parity transmission command, the intermediate parity, and the data row number from the controller100. The parity FMPK144Q accordingly writes the intermediate parity into the memory1445, reads the old Q parity stored in the FM1443, reads the intermediate parity stored in the memory1445, reads the Q parity generation coefficient stored in the memory1445on the basis of the data row number, generates the new Q parity by means of the XOR circuit1442, and writes the new parity Q into the FM1443. The parity FMPK144Q then notifies the controller100of a normal end of the Q parity intermediate parity transmission command.

Subsequently, the MP121is notified by the parity FMPK144Q of the normal end. The MP121accordingly changes the value of each process stage information item to the post-parity generation stage.

The MP121then sends the new data commit command to the parity FMPK144P (S9120). This new data commit command designates the logical page having the new user data stored therein.

Then, the data FMPK144A receives the new data commit command from the controller100. Accordingly, the data FMPK144A determines the new user data as the user data after update, and notifies the controller100of a normal end of the new data commit command.

Subsequently, the MP121is notified by the data FMPK144A of the normal end of the new data commit command. Accordingly, the MP121sends the new data commit command to the parity FMPK144P (S9230). This new data commit command designates the logical page having the new parity stored therein.

The parity FMPK144P then receives the new data commit command from the controller100. Accordingly, the parity FMPK144P determines the new parity as the P parity after update, and notifies the controller100of a normal end of the new data commit command.

Subsequently, the MP121is notified by the parity FMPK144P of the normal end of the new data commit command. The MP121accordingly sends the new data commit command to the parity FMPK144Q (S9240). This new data commit command designates the logical page having the new Q parity stored therein.

The parity FMPK144Q then receives the new data commit command from the controller100. Accordingly, the parity FMPK144Q determines the new Q parity as the Q parity after update, and notifies the controller100of a normal end of the new data commit command.

Subsequently, the MP121is notified by the parity FMPK144Q of the normal end of the new data commit command. Accordingly, the MP121clears the value of each process stage information item stored in the SM132.

The above is the write process.

In this manner, the controller100sends the intermediate parity from the buffer143to the parity FMPK144P and the parity FMPK144Q without writing the intermediate parity received from the data FMPK144A into the CM131. As a result, the number of accesses to the CM131during the write process is reduced.

In addition, as with Embodiment 1, data loss does not occur even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, the plurality of BEPKs140, and the plurality of FMPKs144. Therefore, the reliability of the storage system10can be improved.

According to each of the embodiments described above, reducing the number of accesses to the CM131can reduce the communication overhead of the communication with the CMPK130and the load on the CM131, improving the throughput of the storage system10.

According to each of the embodiments described above, the reliability of the storage system10can be improved by storing the new user data and each process stage information item in the two CMPKs130.

Furthermore, according to each of the embodiments described above, the occurrence of data loss can be prevented even when the simultaneous point of fault occurs in the plurality of MPPKs120, the plurality of CMPKs130, and the plurality of BEPKs140during the write processes.

In each of the embodiments described above, hamming codes, redundancy codes and the like may be used in place of the parities.

Moreover, the order of the steps of the operations performed by the controller100is often changed. For instance, S3230and S3320can be switched over. Additionally, S8120and S8310can be switched over as well.

Each logical region group may be in the form of a stripe based on the RAID group. Each logical region may be an element configuring the stripe, or may be provided one-on-one to a nonvolatile memory. Each logical region group may be a component of a logical unit provided to a transmission-source device to which a write request is transmitted (e.g., the host computer or another storage system), or may be a region group (a region group that is allocated to a write-destination virtual segment, when writing occurs on the virtual segment) that is dynamically allocated to any of a plurality of virtual segments (virtual storage regions), which configure a virtual logical unit (e.g., a logical unit according to thin provisioning) provided to the transmission-source device. In the latter case, a storage region pool may be configured by the plurality of logical segments. Each logical segment may be configured by one or more logical region groups and allocated to a virtual segment in units of the logical segments. The storage region pool may be configured by a plurality of logical units, in which case each of the logical units may be configured by two or more logical segments.

The present specification has described, for example, the following storage systems according to (Description 1) to (Description 4).

A storage system, comprising:a plurality of storage devices, each of which has a plurality of storage media and a device controller for controlling the plurality of storage media and has a RAID group configured by the plurality of storage media; anda system controller that has a processor, a buffer memory coupled to the plurality of storage devices and the processor by a predetermined communication network, and a cache memory coupled to the processor and the buffer memory by the predetermined communication network,wherein the processor stores first data, which is related to a write request from a host computer, in the cache memory, specifies from the plurality of storage devices a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device,a first device controller of the first storage device transmits the first data and second data based on the data before update, from the first storage device to the system controller, andthe processor stores the second data in the buffer memory, specifies a second storage device from the plurality of storage devices, transfers the stored second data to the specified second storage device, and manages a process stage information item indicating a stage of a process performed on the write request.

The storage system according to Description 1,wherein the second data is an intermediate parity and the second storage device is a storage device in which parity data before update is stored,the first device controller calculates the intermediate parity based on the first data and the data before update that are stored in the first storage device, and transmits the calculated intermediate parity to the system controller,the processor stores the intermediate parity in the buffer memory and transfers the stored intermediate parity to the second storage device, anda second device controller of the second storage device calculates an updated parity based on the transferred intermediate parity and a parity before update, and writes the calculated updated parity into the second storage device.

The storage system according to Description 2,wherein each of the storage media is a flash memory,the data before update is stored in a first physical region of the flash memory, andthe first device controller stores the first data in a second physical region different from the first physical region of the flash memory, and keeps a correspondence relationship between the data before update and the first physical region and a correspondence relationship between the first data and the second physical region until the updated parity is stored in a flash memory of the second storage device.

The storage control apparatus according to Description 4,wherein the first device controller allocates the first physical region storing the data before update to a first logical region designated by a write request, and writes first data obtained from the second memory into the second physical region, which is a physical region different from the first physical region in the first storage device, andafter the updated parity is written to the second storage device, the first device controller allocates the second physical region to the first logical region.

In these descriptions, the system controller and additional system controller correspond to, for example, the MPs121. Each device controller corresponds to, for example, the CPU1444of the FMPK144. Each storage device corresponds to, for example, the FM1443of the FMPK144. The first memory corresponds to, for example, the SM132. The first data corresponds to, for example, the new user data. The second data corresponds to, for example, the intermediate parity or the old user data.

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