System and method for avoiding offset in and reducing the footprint of a non-volatile memory

A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit under 35 USC 119 of Italian Application no. MI2004A 001927, filed on Oct. 12, 2004.

FIELD OF THE INVENTION

The present invention relates to non-volatile memory, and more particularly to avoiding offset in and reducing the footprint of a non-volatile memory.

BACKGROUND OF THE INVENTION

Non-volatile memory is a type of memory that preserves data with or without power applied to the memory. Most computer and electronic systems use a binary number system with bits. Two distinctly different current levels that flow through the memory under the correct conditions represent each bit, a one or a zero.

Some memory is single-level, where one bit of information is stored in each memory cell. In order to determine the value of the memory cell, current through the memory cell is compared to a reference memory cell. A current through the memory cell that is lower than that through the reference cell represents one bit value, while a current through the memory cell that is higher than that through the reference cell represents the other bit value.

In advanced memory devices, it is desirable to simultaneously perform multiple operations on memory, for example read while writing, or read while erasing. In order to achieve this, a memory device is organized into smaller blocks of memory called ‘banks.’ One operation may be performed on one bank while another operation is performed on another bank.

In one memory architecture, a set of sense amplifiers handles ‘read’ operations for the banks of memory and another set of sense amplifiers handles ‘verify’ operations for the banks. The offset between the two sets of amplifiers reduces current within the memory device and causes associated performance problems.

FIG. 1is a schematic diagram illustrating one solution to this problem with conventional system90. System90is a non-volatile memory with memory banks100connected to Y-decoder and sense amplifier circuit102, and to X-decoder circuit104. Rather than having only two sets of amplifiers, as in previously described memory architecture, each memory bank100has amplifier circuit102.

In order to read a memory cell (seeFIG. 2) from memory bank100, bias circuit103activates a reference cell current from reference matrix101. The reference cell current is mirrored from reference matrix101through bias circuit103to amplifier circuit102. Amplifier circuit102compares the reference cell current to a memory cell current through memory bank100in order to determine the value in a memory cell.

FIG. 2is a schematic diagram illustrating components of conventional system90fromFIG. 1. Bias circuit103includes transistor110, which, during a memory read, for example, activates reference matrix101. Reference matrix101includes transistors112and114. Transistor114is also activated during a memory read, which causes a reference cell current to flow through reference cell118. Cell116is used during verify operations. Current through reference cell118flows through transistor120and is mirrored by transistor122, and caused to flow through transistor124.

In Y-decoder and amplifier circuit102, transistor126mirrors reference cell current and causes it to flow through transistor128. As part of the memory read operation, memory block100with memory cell130is biased by transistor132, causing current to flow, with a voltage drop across transistors132and memory cell130, and other associated components that are not illustrated for simplicity. Sense amplifier134compares the current through (or voltage across) memory cell130with the current through reference cell118. The bit value stored in memory cell130is related to the current through memory cell130relative to current through reference cell118.

One problem with conventional system90is that it takes a large amount of space to implement (it has a large “footprint”). Another problem is that it takes a significant amount of time to test conventional system90.

Accordingly, what is needed is a system and method for avoiding offset, reducing the footprint and decreasing test time in a non-volatile memory. The present invention addresses such a need.

SUMMARY OF THE INVENTION

The present invention provides a system and method for avoiding offset, reducing test time and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.

According to the method and system disclosed herein, the present invention reduces the footprint necessary by connecting a single reference cell matrix to multiple memory banks, rather than having a single reference cell for each memory bank. Offset has not been affected over conventional system90because there are still sets of sense amplifiers for each memory bank, and testing time is improved over a conventional system.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to non-volatile memory, and more particularly to avoiding offset in and reducing the footprint of a non-volatile memory.

FIG. 3is a schematic diagram illustrating one embodiment of the invention in a non-volatile memory300. A non-volatile memory300has, for example, memory banks302connected to X-decoders304and sense amplifiers306. Biasing circuits308connect to sense amplifiers306. Both the biasing circuits308and the sense amplifiers306are local to memory banks302, in other words a given biasing circuit and a given sense amplifier serve a particular memory bank. Typically the sense amplifiers306include Y-decoders, while the X-decoder304is also local to a particular memory bank. Keeping sense amplifiers306local avoids the problem of offset arising in some conventional systems.

A reference cell matrix310attaches to each of the biasing circuits308and is global, i.e. it provides reference cell current to multiple biasing circuits308. InFIG. 3, six memory banks are illustrated, though less or more may be implemented in system300. All six memory banks are connected to a global reference cell310. In another embodiment, the reference cell matrix310may be connected to less or more memory banks302, and need not be connected to every memory bank302in system300. Lines312may be connected to ground in order to shield reference current from interference and noise.

During a memory read operation, for example, one of the biasing circuits308biases the reference cell matrix310in order that the reference cell matrix310may provide reference cell current to one of the sense amplifiers306. Then the sense amplifier306that receives the reference cell current compares the reference cell current to current in a memory cell (seeFIG. 4) of memory banks302in order that the value of data held in the memory cell may be determined. The system300provides a global reference cell matrix310for multiple memory blocks302, as opposed to conventional systems, which utilizes a local reference matrix for each memory block.

FIG. 4is a schematic diagram illustrating more detail from system300fromFIG. 3. The memory bank302includes, among other circuits, a memory cell400. In sense amplifiers306, a transistor402connects to the memory cell400and other circuits (not shown). Transistors404and406connect to provide a point of contact for an amplifier408, which compares current through the memory cell400with a reference cell current during memory read operations, for example. Although only a single memory cell400and a single amplifier306are illustrated inFIG. 4, a typical non-volatile memory has more than one of each of these. For example, one of the memory banks302typically has more than one memory cell400, while one of the sense amplifiers306typically has more than one amplifier408.

Transistors410and412comprise a current mirror to reflect current through the biasing circuit308to the sense amplifiers306. Multiple sense amplifiers306are typically connected to each biasing circuit308. Transistors414and416comprise a current mirror to reflect reference cell current passing through the reference cell matrix310to the biasing circuit308.

A bias transistor418biases both of the transistors420and422, which in one embodiment are verify and read transistors. The verify transistor420may be biased for a memory verify operation, while the read transistor422may be biased for a memory read operation. One of the memory banks302may be conducting a memory verify operation with the transistors418and420biased (respective to the relevant memory bank302), while another memory bank is conducting a memory read operation with the transistors418and422biased (respective to the relevant memory bank302).

During a memory read operation, for example, the read transistor422biases the read cell424through the read cell line426. During a memory verify operation, for example, the verify transistor420biases the verify cell428through the verify cell line430. The verify cell428and the read cell424are part of the global reference cell matrix310, serving multiple memory banks302. The lines312may be grounded and function to shield the verify cell line430and the read cell line426from interference and noise that could decrease error margin.

The advantages of the invention include minimizing test time, reducing circuit footprint by keeping local the circuitry that biases the reference cells. The number of reference cells are reduced and placed in a global location and offset is avoided by using local sense amplifiers.

The present invention has been described in accordance with the embodiments shown, and one of ordinary skill in the art will readily recognize that there could be variations to the embodiments, and any variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.