Circuit fabrication method which optimizes source/drain contact resistance

A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

FIELD OF THE INVENTION
 The present invention is related to integrated circuit (IC) devices and
 processes of making IC devices. More particularly, the present invention
 relates to an IC which is optimized for small size and low source/drain
 contact resistance.
 BACKGROUND OF THE INVENTION
 Integrated circuits (ICs) include a multitude of transistors formed on a
 semiconductor substrate. Transistors, such as, metal oxide semiconductor
 field effect transistors (MOSFETs), are generally built on the top surface
 of a bulk substrate. The substrate is doped to form impurity diffusing
 layers (i.e. source and drain regions). Between the source and drain
 regions is a conductive layer which operates as a gate for the transistor.
 The gate controls current in a channel between the source and the drain
 regions.
 To reduce series resistance associated with the source and drain regions,
 manufacturers use a process known as "silicidation." Typically,
 silicidation is accomplished by depositing a refractory metal (e.g. Co,
 Ti, Ni) onto an exposed surface of source and drain regions in a
 semiconductor substrate. The atoms of silicon (Si) in the source and drain
 regions react with the atoms of the refractory metal, forming a silicide
 layer. The layer of silicide reduces the contact resistance at the
 silicide source/drain junction by helping break through the residual
 surface oxide so that good electrical contact can be made.
 As MOSFETs are made smaller and smaller, however, the source and drain
 regions become more shallow and contact resistance associated with the
 source and drain regions increases. The source/drain contact resistance
 (i.e. silicide junction resistance) is very critical to transistor
 performance. High contact resistance degrades the transistor drive current
 and, thus, also degrades transistor speed and performance.
 U.S. Pat. No. 5,258,637, issued Nov. 2, 1993, and U.S. Pat. No. 5,108,954,
 issued Apr. 28, 1992, both to Sandhu and Anjum, disclose a method of
 reducing contact resistance at silicide/active area interfaces. Sanhu and
 Anjum explain that during the elevated temperature anneal to form the
 silicide, the conductivity enhancing impurity (or dopant) tends to diffuse
 toward the silicide region. The void of dopants near the silicide
 increases the contact resistance between the silicide and active areas.
 In the process disclosed by Sandhu and Anjum, germanium is implanted
 through the contact opening and into the active area of the wafer. As
 such, the germanium restricts diffusion of the conductivity enhancing
 impurity therethrough during the silicide anneal. While the germanium
 implant may reduce the contact resistance caused by a void of dopants near
 the silicide, the Sanhu and Anjum process does not optimize the contact
 resistance by maximizing the level of dopants proximate to the silicide.
 The conventional method of silicidation makes it very difficult to locate
 the bottom of the silicide layer in the region of peak dopant
 concentration during transistor fabrication. The least contact resistance
 would be achieved by locating the bottom of the silicide layer in the peak
 dopant concentration. Physically, though, conventional methods cannot do
 this. The manufacturing process can be varied by random process variation,
 making precise placement of the silicide layer difficult. Further, the
 peak is usually located close to the surface of the silicon semiconductor
 layer. When silicidation occurs, the silicon is consumed, locating the
 bottom of the silicide layer deeper than the peak. As the amount of
 contact resistance resulting from fabrication depends on how close the
 bottom of the silicide formation is to the peak dopant concentration, the
 conventional fabrication process results in excessive contact resistance.
 Thus, there is a need for a method to optimize MOSFET source/drain contact
 resistance in the fabrication process. Further, there is a need to reduce
 the contact resistance without implanting germanium at a precise location
 in the source/drain regions. Even further, there is a need for fabricating
 a transistor such that the bottom of the silicide always intersects with a
 high density of dopant.
 SUMMARY OF THE INVENTION
 One embodiment of the invention relates to a method of manufacturing an
 integrated circuit. The method includes implanting a first material in a
 layer of semiconductor, the first material creating a buried amorphous
 layer; implanting a second material in the layer of semiconductor and
 layer of amorphous semiconductor, the second material forming a profile
 region with a curved shape; depositing a layer of metal on the layer of
 semiconductor; exposing laser energy to the integrated circuit such that
 the amorphous semiconductor layer is melted and the profile region has a
 box-like shape; and forming a semiconductor/metal layer with the layer of
 semiconductor and the layer of metal, whereby the bottom of the
 semiconductor/metal layer is located in the profile region.
 Another embodiment of the invention relates to a method of manufacturing an
 integrated circuit including amorphosizing a silicon structure, creating a
 buried amorphous silicon structure; implanting an ion in the silicon
 structure and amorphous silicon structure; depositing a layer of metal on
 the silicon structure; exposing laser energy to the integrated circuit
 such that the amorphous silicon structure is melted; and forming silicide
 with the silicon structure and layer of metal, the bottom of the silicide
 located in the amorphous silicon structure.
 Another embodiment of the invention relates to a method of manufacturing an
 ultra-large scale integrated circuit including a plurality of transistors,
 each transistor having a layer of silicon with impurity diffusing layers
 and a layer of silicide adjacent each impurity diffusing layer, the
 contact resistance between the impurity diffusing layers and the
 corresponding layer of silicide being optimized. The method includes
 amorphosizing the layer of silicon, creating a buried amorphous silicon
 layer; implanting a dopant in the layer of silicon and amorphous silicon
 layer; depositing a layer of metal on the insulator structure; exposing
 laser energy to the integrated circuit such that the amorphous silicon
 layer is melted; and forming silicide with the insulator structure and
 layer of metal, the bottom of the silicide located in the amorphous
 silicon layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 Referring to FIG. 1, a cross-sectional view of a portion 8 of an integrated
 circuit is illustrated in accordance with an exemplary embodiment of the
 present invention. Portion 8 includes a silicide layer 10 and a substrate
 or silicon layer 12. Silicide layer 10 is a metal/semiconductor layer
 disposed over silicon layer 12 (shown in FIG. 1 with dashed lines).
 Silicon layer 12 includes a profile region 14 indicating relative
 concentration of impurities in silicon layer 12. Silicon layer 12 may, in
 other embodiments, be a layer of some other kind of semiconductor type of
 material. Layer 10 can be provided over, in contact with or integral a
 source or drain such as a drain region 11.
 With reference to FIGS. 2-5, the fabrication of portion 8 is described
 below. In FIG. 2, a cross-sectional view of portion 8 illustrates an
 implantation step to create a buried amorphous silicon region 16 in
 silicon layer 12. In the implantation step, an implantation species 18 is
 implanted in silicon layer 12 to create buried amorphous region 16.
 Implantation species 18 can be Si.sup.+ or Ge.sup.+. Implantation species
 18 is implanted such that buried amorphous region 16 lacks a distinct
 crystalline structure. Silicon layer 12, in contrast, has a distinct
 crystalline structure. Silicon layer 12 and buried amorphous region 16 are
 also of a thickness which, when silicidation occurs in FIG. 5, allows the
 bottom of silicide layer 10 to be located in buried amorphous region 16.
 In FIG. 3, a cross-sectional view of portion 8 illustrates an implantation
 step and a resulting curved profile region 20 in silicon layer 12. In the
 implantation step, an implantation species 22 is implanted in the silicon
 layer 12 and buried amorphous region 16. Implantation species 22 in one
 particular embodiment is a dopant, such as phosphorous, boron, boron
 difluoide (BF.sub.2), arsenic, indium or other material. Implantation
 species 22 adds impurity to silicon layer 12 and buried amorphous region
 16, as represented by curved dopant profile region 20. Curved dopant
 profile region 20 represents the relative concentration of impurities in
 silicon layer 12 and buried amorphous region 16.
 In FIG. 4, a cross-sectional view of portion 8 illustrates a metal
 deposition step on silicon layer 12. In the metal deposition step, a metal
 24 is disposed over silicon layer 12. Metal 24 can be a refractory metal.
 Material 24 can be Co, Ti, Ni, W or any other metal appropriate for the
 silicidation process.
 In FIG. 5, a cross-sectional view of portion 8 illustrates a laser exposure
 step and a resulting box-like dopant profile region 26. In the laser
 exposure step, laser pulse 28 emits from, for example, an excimer laser
 and is directed to metal 24, silicon layer 12, and buried amorphous region
 16. During the laser exposure step, laser pulse 28 creates a temperature
 high enough to melt buried amorphous region 16, but not high enough to
 melt silicon layer 12 or metal 24. In one particular embodiment, the
 temperature range which melts buried amorphous region 16 is
 900-1000.degree. C. Melting of buried amorphous region 16 also impurities
 present in buried amorphous region 16, as represented by curved profile
 region 20 in FIG. 4. The redistribution of impurities results in box-like
 profile region 26 as shown in FIG. 5. Silicon layer 12 intermediate metal
 24 and buried amorphous region 16 prevents atoms from metal 24 from
 diffusing into buried amorphous region 16.
 In FIG. 6, a cross-sectional view of portion 8 illustrates a recrystalizing
 step and a resulting crystalized layer 12. In the recrystalizing step,
 laser pulse 28 is removed and buried amorphous region 16 recrystalizes.
 After recrystalization of buried amorphous region 16, silicide formation is
 performed to create silicide layer 10, shown in FIG. 1. Silicide layer 10
 is formed by depositing a refractory metal (e.g., Co, Ti, Ni) onto an
 exposed surface of impurity diffused layers in a semiconductor substrate.
 During silicidation, atoms of silicon from silicon layer 12 and the
 recrystalized silicon layer of former buried amorphous region 16 (FIG. 6)
 react with atoms of the refractory metal from metal 24 to form silicide
 layer 10. Silicide layer 10 is located over silicon layer 12 such that the
 bottom of silicide layer 10 is located in a flat portion of box-like
 dopant profile region 26, representing relative concentration of
 impurities (e.g. dopants, ions) in silicon layer 12. Such location, by
 proper design, completely consumes silicon layer 12 intermediate metal 24
 and former buried amorphous region 16 into silicide layer 10. Location of
 silicide layer 10 depends on the thickness of silicon layer 12 and former
 buried amorphous region 16. The thickness of silicon layer 12 and former
 buried amorphous region 16 provides a location for silicide layer 10
 adjacent a high concentration of impurities after the silicidation
 process. FIG. 1 shows where drain and source regions could be located in
 silicon layer 12. Such placement optimizes (i.e., minimizes) contact
 resistance at the junction of silicide layer 10 and silicon layer 12. If
 there is a reasonably large thickness of the buried amorphous region 16,
 the process window for the manufacturing is large.
 It is understood that while the detailed drawings, specific examples, and
 particular values given provide a preferred exemplary embodiment of the
 present invention, it is for the purpose of illustration only. The method
 and apparatus of the invention is not limited to the precise details and
 conditions disclosed. For example, although particular drain and source
 structures are described, other types of active regions can utilize the
 principles of the present invention. Various changes may be made to the
 details disclosed without departing from the spirit of the invention which
 is defined by the following claims.