Technologies for demoting cache lines to shared cache

Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

BACKGROUND

Modern computing devices have become ubiquitous tools for personal, business, and social uses. As such, many modern computing devices are capable of connecting to various data networks, including the Internet, to transmit and receive data communications over the various data networks at varying rates of speed. To facilitate communications between computing devices, the data networks typically include one or more network computing devices (e.g., compute servers, storage servers, etc.) to route communications (e.g., via switches, routers, etc.) that enter/exit a network (e.g., north-south network traffic) and between network computing devices in the network (e.g., east-west network traffic). In present packet-switched network architectures, data is transmitted in the form of network packets between networked computing devices. At a high level, data is packetized into a network packet at one computing device and the resulting packet transmitted, via a transmission device (e.g., a network interface controller (NIC) of the computing device), to another computing device over a network.

Upon receipt of a network packet, the computing device typically performs one or more processing operations (e.g., security, network address translation (NAT), load-balancing, deep packet inspection (DPI), transmission control protocol (TCP) optimization, caching, Internet Protocol (IP) management, etc.) to determine what the computing device is to do with the network packet (e.g., drop the network packet, process/store at least a portion of the network packet, forward the network packet, etc.). To do so, such packet processing is often performed in a packet processing pipeline (e.g., a service function chain) where at least a portion of the data of the network packet is passed from one processor core to another as it is processed. However, during such packet processing, stalls can occur due to cross-core snoops and cache pollution with stale data can be a problem.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring now toFIG. 1, in an illustrative embodiment, a system100for demoting cache lines to shared cache includes a source compute device102communicatively coupled to a network compute device106via a network104. While illustratively shown as having a single source compute device102and a single network compute device106, the system100may include multiple source compute devices102and multiple network compute devices106, in other embodiments. It should be appreciated that the source compute device102and network compute device106have been illustratively designated herein as being one of a “source” and a “destination” for the purposes of providing clarity to the description and that the source compute device102and/or the network compute device106may be capable of performing any of the functions described herein. It should be further appreciated that the source compute device102and the network compute device106may reside in the same data center or high-performance computing (HPC) environment. In other words, the source compute device102and network compute device106may reside in the same network104connected via one or more interconnects.

In use, the source compute device102and the network compute device106transmit and receive network traffic (e.g., network packets, frames, etc.) to/from each other. For example, the network compute device106may receive a network packet from the source compute device102. Upon receipt of a network packet, the network compute device106, or more particularly a host fabric interface (HFI)126of the network compute device106, identifies one or more processing operations to be performed on at least a portion of the network packet and performs some level of processing thereon. To do so, a processor core112requests access to data which may have been previously stored or moved into shared cache memory, typically on-processor or near-processor cache. The network compute device106is configured to move the requested data to a core-local cache (e.g., the core-local cache114) for quicker access to the requested data by the requesting processor core112.

Oftentimes, more than one processing operation (e.g., security, network address translation (NAT), load-balancing, deep packet inspection (DPI), transmission control protocol (TCP) optimization, caching, Internet Protocol (IP) management, etc.) is performed by the network compute device, with each operation typically performed by a different processor core in a packet processing pipeline, such as a service function chain. Accordingly, the data accessed by one processor core needs to be released (e.g., demoted to the shared cache116) upon processing completion in order for the next processor core to perform its designated processing operation.

To do so, as will be described in further detail below, the network compute device106is configured to either transmit instructions to a cache manager to demote cache line(s) from the core-local cache114to the shared cache116or transmit a command to an offload device (see, e.g., the cache line offload device130) to trigger a cache line demotion operation to be performed by the offload device to demote cache line(s) from the core-local cache114to the shared cache116, based on a size of the network packet. In other words, each processor core demotes the applicable packet cache lines to the shared cache116once processing has been completed, which allows better cache reuse on a first processing core and saves cross-core snoops on a second processing core in the packet processing pipeline (e.g., modifying data) or input/output (I/O) pipeline. Accordingly, unlike present technologies, stalls due to cross-core snoops and cache pollution can be effectively avoided. Additionally, also unlike present technologies, the cost attributable to an ownership request when the requested data is not in the shared cache or otherwise inaccessible by the requesting processor core can be avoided.

The network compute device106may be embodied as any type of computation or computer device capable of performing the functions described herein, including, without limitation, a computer, a server (e.g., stand-alone, rack-mounted, blade, etc.), a sled (e.g., a compute sled, an accelerator sled, a storage sled, a memory sled, etc.), an enhanced or smart network interface controller (NIC)/HFI, a network appliance (e.g., physical or virtual), a router, switch (e.g., a disaggregated switch, a rack-mounted switch, a standalone switch, a fully managed switch, a partially managed switch, a full-duplex switch, and/or a half-duplex communication mode enabled switch), a web appliance, a distributed computing system, a processor-based system, and/or a multiprocessor system.

As shown inFIG. 1, the illustrative network compute device106includes one or more processors108, memory118, an I/O subsystem120, one or more data storage devices122, communication circuitry124, a demote device130, and, in some embodiments, one or more peripheral devices128. It should be appreciated that the network compute device106may include other or additional components, such as those commonly found in a typical computing device (e.g., various input/output devices and/or other components), in other embodiments. Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.

The processor(s)108may be embodied as any type of device or collection of devices capable of performing the various compute functions as described herein. In some embodiments, the processor(s)108may be embodied as one or more multi-core processors, digital signal processors (DSPs), microcontrollers, or other processor(s) or processing/controlling circuit(s). In some embodiments, the processor(s)108may be embodied as, include, or otherwise be coupled to an integrated circuit, an embedded system, a field-programmable-array (FPGA) (e.g., reconfigurable circuitry), a system-on-a-chip (SOC), an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein.

The illustrative processor(s)108includes multiple processor cores110(e.g., two processor cores, four processor cores, eight processor cores, sixteen processor cores, etc.) and a cache memory112. Each of processor cores110may be embodied as an independent logical execution unit capable of executing programmed instructions. It should be appreciated that, in some embodiments, the network compute device106(e.g., in supercomputer embodiments) may include thousands of processor cores. Each of the processor(s)108may be connected to a physical connector, or socket, on a motherboard (not shown) of the network compute device106that is configured to accept a single physical processor package (i.e., a multi-core physical integrated circuit). Further, each of the processor cores110is communicatively coupled to at least a portion of the cache memory112and functional units usable to independently execute programs, operations, threads, etc. It should be appreciated that the processor(s)108as described herein are not limited to being on the same die, or socket.

The cache memory112, which may be embodied as any type of cache that the processor104can access more quickly than the memory118(i.e., main memory), such as an on-die cache, or on-processor cache. In other embodiments, the cache memory108may be an off-die cache, but reside on the same system-on-a-chip (SoC) as the processor104. The illustrative cache memory112includes a multi-level cache architecture embodied as a core-local cache114and a shared cache116. The core-local cache114may be embodied as a cache memory dedicated to a particular one of the processor cores110. Accordingly, while illustratively shown as a single core-local cache114, it should be appreciated that there may be at least one core-local cache114for each processor core110, in some embodiments.

The shared cache116may be embodied as a cache memory, typically larger than the core-local cache114and shared by all of the processor cores110of a processor108. For example, in an illustrative embodiment, the core-local cache114may be embodied as a level 1 (L1) cache and a level 2 (L2) cache, while the shared cache116may be embodied as a layer3(L3) cache. In such embodiments, it should be appreciated that the L1 cache may be embodied as any memory type local to a processor core110, commonly referred to as a “primary cache” that is the fastest memory closest to the processor108. It should be further appreciated that, in such embodiments, the L2 cache may be embodied as any type of memory local to a processor core110, commonly referred to as a “mid-level cache” that is capable of feeding the L1 cache, having larger, slower memory than the L1 cache, but typically smaller, faster memory than the L3/shared cache116(i.e., last-level cache (LLC)). In other embodiments, the multi-level cache architecture may include additional and/or alternative levels of cache memory. While not illustratively shown inFIG. 1, it should be further appreciated that the cache memory112includes a memory controller (see, e.g., the cache manager214ofFIG. 2), which may be embodied as a controller circuit or other logic that serves as an interface between the processor108and the memory118.

The memory118may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. In operation, the memory118may store various data and software used during operation of the network compute device106, such as operating systems, applications, programs, libraries, and drivers. It should be appreciated that the memory118may be referred to as main memory (i.e., a primary memory). Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM).

Each of the processor(s)108and the memory118are communicatively coupled to other components of the network compute device106via the I/O subsystem114, which may be embodied as circuitry and/or components to facilitate input/output operations with the processor(s)108, the memory118, and other components of the network compute device106. For example, the I/O subsystem114may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem114may form a portion of a SoC and be incorporated, along with one or more of the processors108, the memory118, and other components of the network compute device106, on a single integrated circuit chip.

The one or more data storage devices122may be embodied as any type of storage device(s) configured for short-term or long-term storage of data, such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device122may include a system partition that stores data and firmware code for the data storage device122. Each data storage device122may also include an operating system partition that stores data files and executables for an operating system.

The communication circuitry124may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications between the network compute device106and other computing devices, such as the source compute device102, as well as any network communication enabling devices, such as an access point, switch, router, etc., to allow communication over the network104. Accordingly, the communication circuitry124may be configured to use any one or more communication technologies (e.g., wireless or wired communication technologies) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, LTE, 5G, etc.) to effect such communication.

It should be appreciated that, in some embodiments, the communication circuitry124may include specialized circuitry, hardware, or combination thereof to perform pipeline logic (e.g., hardware algorithms) for performing the functions described herein, including processing network packets (e.g., parse received network packets, determine destination computing devices for each received network packets, forward the network packets to a particular buffer queue of a respective host buffer of the network compute device106, etc.), performing computational functions, etc.

In some embodiments, performance of one or more of the functions of communication circuitry124as described herein may be performed by specialized circuitry, hardware, or combination thereof of the communication circuitry124, which may be embodied as a SoC or otherwise form a portion of a SoC of the network compute device106(e.g., incorporated on a single integrated circuit chip along with a processor108, the memory118, and/or other components of the network compute device106). Alternatively, in some embodiments, the specialized circuitry, hardware, or combination thereof may be embodied as one or more discrete processing units of the network compute device106, each of which may be capable of performing one or more of the functions described herein.

The illustrative communication circuitry124includes the HFI126, which may be embodied as one or more add-in-boards, daughtercards, network interface cards, controller chips, chipsets, or other devices that may be used by the network compute device106to connect with another compute device (e.g., the source compute device102). In some embodiments, the HFI126may be embodied as part of a SoC that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the HFI126may include a local processor (not shown) and/or a local memory (not shown) that are both local to the HFI126. In such embodiments, the local processor of the HFI126may be capable of performing one or more of the functions of a processor108described herein. Additionally or alternatively, in such embodiments, the local memory of the HFI126may be integrated into one or more components of the network compute device106at the board level, socket level, chip level, and/or other levels.

The one or more peripheral devices128may include any type of device that is usable to input information into the network compute device106and/or receive information from the network compute device106. The peripheral devices128may be embodied as any auxiliary device usable to input information into the network compute device106, such as a keyboard, a mouse, a microphone, a barcode reader, an image scanner, etc., or output information from the network compute device106, such as a display, a speaker, graphics circuitry, a printer, a projector, etc. It should be appreciated that, in some embodiments, one or more of the peripheral devices128may function as both an input device and an output device (e.g., a touchscreen display, a digitizer on top of a display screen, etc.). It should be further appreciated that the types of peripheral devices128connected to the network compute device106may depend on, for example, the type and/or intended use of the network compute device106. Additionally or alternatively, in some embodiments, the peripheral devices128may include one or more ports, such as a USB port, for example, for connecting external peripheral devices to the network compute device106.

The cache line demote device130may be embodied as any type of firmware, software, and/or hardware device that is usable to initiate a cache line demotion from core-local cache114to shared cache116. In some embodiments, the cache line demote device130may be embodied as, but is not limited to a copy engine, a direct memory access (DMA) device usable to copy data, an offload read-capable device, etc. It should be appreciated that the cache line demote device130may be any type of device that is capable of reading or pretending to read data, so long as when the device interacts with the data or otherwise requests access to the data, the cache lines associated with that data will get demoted to shared cache116as a side effect.

The source compute device102may be embodied as any type of computation or computer device capable of performing the functions described herein, including, without limitation, a smartphone, a mobile computing device, a tablet computer, a laptop computer, a notebook computer, a computer, a server (e.g., stand-alone, rack-mounted, blade, etc.), a sled (e.g., a compute sled, an accelerator sled, a storage sled, a memory sled, etc.), a network appliance (e.g., physical or virtual), a web appliance, a distributed computing system, a processor-based system, and/or a multiprocessor system. While not illustratively shown, it should be appreciated that source compute device102includes similar and/or like components to those of the illustrative network compute device106. As such, figures and descriptions of the like components are not repeated herein for clarity of the description with the understanding that the description of the corresponding components provided above in regard to the network compute device106applies equally to the corresponding components of the source compute device102. Of course, it should be appreciated that the computing devices may include additional and/or alternative components, depending on the embodiment.

The network104may be embodied as any type of wired or wireless communication network, including but not limited to a wireless local area network (WLAN), a wireless personal area network (WPAN), an edge network (e.g., a multi-access edge computing (MEC) network), a fog network, a cellular network (e.g., Global System for Mobile Communications (GSM), Long-Term Evolution (LTE), 5G, etc.), a telephony network, a digital subscriber line (DSL) network, a cable network, a local area network (LAN), a wide area network (WAN), a global network (e.g., the Internet), or any combination thereof. It should be appreciated that, in such embodiments, the network104may serve as a centralized network and, in some embodiments, may be communicatively coupled to another network (e.g., the Internet). Accordingly, the network104may include a variety of other virtual and/or physical network computing devices (e.g., routers, switches, network hubs, servers, storage devices, compute devices, etc.), as needed to facilitate communication between the network compute device106and the source compute device102, which are not shown to preserve clarity of the description.

Referring now toFIG. 2, in use, the network compute device106establishes an environment200during operation. The illustrative environment200includes the processor(s)108, the HFI126, and the cache line demote device130ofFIG. 1, as well as a cache manager214and a demotion manager220. The illustrative HFI126includes a network traffic ingress/egress manager208, the illustrative cache line demote device130includes an interface manager210, and the illustrative processor(s)108include a packet process operation manager212. The various components of the environment200may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment200may be embodied as circuitry or collection of electrical devices (e.g., network traffic ingress/egress management circuitry208, demote device interface management circuitry210, packet process operation management circuitry212, cache management circuitry214, demotion management circuitry220, etc.).

As illustratively shown, the network traffic ingress/egress management circuitry208, the demote device interface management circuitry210, the packet process operation management circuitry212, the cache management circuitry214, and the demotion management circuitry220form a portion of a particular component of the network compute device106. However, while illustratively shown as being performed by a particular component of the network compute device106, it should be appreciated that, in other embodiments, one or more functions described herein as being performed by the network traffic ingress/egress management circuitry208, the demote device interface management circuitry210, the packet process operation management circuitry212, the cache management circuitry214, and/or the demotion management circuitry220may be performed, at least in part, by one or more other components of the network compute device106.

Additionally, in some embodiments, one or more of the illustrative components may form a portion of another component and/or one or more of the illustrative components may be independent of one another. Further, in some embodiments, one or more of the components of the environment200may be embodied as virtualized hardware components or emulated architecture, which may be established and maintained by the HFI126, the processor(s)108, or other components of the network compute device106. It should be appreciated that the network compute device106may include other components, sub-components, modules, sub-modules, logic, sub-logic, and/or devices commonly found in a computing device, which are not illustrated inFIG. 2for clarity of the description.

In the illustrative environment200, the network compute device106additionally includes cache line address data202, demotion data204, and network packet data206, each of which may be accessed by the various components and/or sub-components of the network compute device106. Further, each of the cache line address data202, the demotion data204, and the network packet data206may be accessed by the various components of the network compute device106. Additionally, it should be appreciated that in some embodiments the data stored in, or otherwise represented by, each of the cache line address data202, the demotion data204, and the network packet data206may not be mutually exclusive relative to each other. For example, in some implementations, data stored in the cache line address data202may also be stored as a portion of one or more of the demotion data204and/or the network packet data206, or in another alternative arrangement. As such, although the various data utilized by the network compute device106is described herein as particular discrete data, such data may be combined, aggregated, and/or otherwise form portions of a single or multiple data sets, including duplicative copies, in other embodiments.

The network traffic ingress/egress manager208, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to receive inbound and route/transmit outbound network traffic. To do so, the illustrative network traffic ingress/egress manager208is configured to facilitate inbound network communications (e.g., network traffic, network packets, network flows, etc.) to the network compute device106(e.g., from the source computing device102). Accordingly, the network traffic ingress/egress manager208is configured to manage (e.g., create, modify, delete, etc.) connections to physical and virtual network ports (i.e., virtual network interfaces) of the network compute device106(e.g., via the communication circuitry124), as well as the ingress buffers/queues associated therewith.

Additionally, the network traffic ingress/egress manager208is configured to facilitate outbound network communications (e.g., network traffic, network packet streams, network flows, etc.) from the network compute device106. To do so, the network traffic ingress/egress manager208is configured to manage (e.g., create, modify, delete, etc.) connections to physical and virtual network ports/interfaces of the network compute device106(e.g., via the communication circuitry124), as well as the egress buffers/queues associated therewith. In some embodiments, at least a portion of the network packet (e.g., at least a portion of a header of the network packet, at least a portion of a payload of the network packet, a checksum, etc.) may be stored in the network packet data206.

The demote device interface manager210, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the interface of the cache line demote device130. For example, the demote device interface manager210is configured to receive cache line demote commands from the processor(s)108that are usable to identify which cache line(s) are to be demoted from core-local cache114to shared cache116. Additionally, the demote device interface manager210is configured to perform some operation (e.g., a read request) in response to having received a cache line demote command to demote one or more cache lines from core-local cache114to shared cache116. It should be appreciated that the cache line demote command includes an identifier of each cache line that is to be demoted from core-local cache114to shared cache116and each identifier is usable by the cache line demote device130to demote (e.g., copy, evict, etc.) the applicable cache line(s).

The packet process operation manager212, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to identify which packet processing operations are to be performed on at least a portion of the data of a received network packet (e.g., a header field of the network packet, a portion of the payload of the network packet, etc.) and the associated processor core110that each packet processing operation is to be performed thereby. Additionally, in some embodiments, the packet process operation manager212may be configured to identify when each packet processing operation has completed and provide an indication of completion (e.g., to the demotion manager220). It should be appreciated that, while described herein as being performed by an associated processor core110, one or more of the packet processing operations may be performed by any type of compute device/logic (e.g., an accelerator device/logic) that may need to access the cache memory112.

The cache manager214, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the cache memory112(e.g., the core-local cache114and the shared cache116). To do so, the cache manager214is configured to manage the addition and eviction of entries into and out of the cache memory112. Accordingly the cache manager214, which may be embodied as or otherwise include a memory management unit is further configured to record results of virtual address to physical address translations. In such embodiments, the translations may be stored in the cache line address data202. The cache manager214is additionally configured to facilitate the fetching of data from main memory and the storage of cached data to main memory, as well as the demotion of data from the applicable core-local cache114to the shared cache116and the promotion of data from the shared cache116to the applicable core-local cache114.

The demotion manager220, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to manage the demotion of data from the core-local cache114to the shared cache116. To do so, the demotion manager220is configured to either transmit instructions to a cache memory manger (e.g., the cache manager214) to demote (e.g., copy, evict, etc.) the processed data from the core-local cache114to the shared cache116, or transmit a command to the cache line demote device130to demote the processed data the core-local cache114to the shared cache116. To determine whether to send the cache line demotion instruction to the cache manager214or the cache line demotion command to the cache line demote device130, the demotion manager220is further configured to compare a size of a network packet to a predetermined packet size threshold.

If the demotion manager220determines the network packet size is greater than the packet size threshold, the demotion manager220is configured to transmit the cache line demotion instruction to the cache manager214. Otherwise, if the demotion manager220determines the network packet size is less than or equal to the packet size threshold, the demotion manager220is configured to transmit the cache line demotion command to the cache line demote device130. Additionally, the demotion manager220is configured to include an identifier of each cache line, or a range of cache lines, to be demoted from the core-local cache114to the shared cache116in the cache line demotion instructions/commands. As illustratively shown, the demotion manager220may be configured as an offload device; however, in some embodiments, the functions as described herein may be performed by or the demotion manager220may otherwise form a portion of the processor108, or the processor cores110. It should be appreciated that under such conditions in which the next cache location is known ahead of time, the demotion manager220may be configured to move the data to known core-local cache entries of the core-local cache associated with the next processor core in the packet processing pipeline.

Referring now toFIG. 3, a method300for demoting cache lines to shared cache is shown which may be executed by a compute device (e.g., the network compute device106ofFIGS. 1 and 2). The method300begins with block302, in which the network compute device106determines whether to process a network packet (e.g., a processor108has polled the HFI126for the next packet to process). If so, the method300advances to block304, in which the network compute device106identifies one or more packet processing operations to be performed on at least a portion of a network packet by a processor core110. In block306, the network compute device106, or more particularly the requesting processor core110, performs the identified packet processing operation(s) on the applicable portion of the network packet to be processed. It should be appreciated that, while described herein as being performed by a requesting processor core110, one or more of the packet processing operations may be performed by any type of compute device/logic (e.g., an accelerator device/logic) that may need to access the cache memory112.

In block308, the network compute device106determines whether the requesting processor core110, or applicable compute device/logic, has completed the identified packet processing operation(s), such as may be indicated by the requesting processor core110. If so, the method300advances to block310, in which the network compute device106determines which one or more cache lines in core-local cache114are associated with the processed network packet. Additionally, in block312, the network compute device106identifies a size of the network packet. In block314, the network compute device106compares the identified network packet size to a packet size threshold. In block316, the network compute device106determines whether the identified network packet size is greater than the packet size threshold.

If the network compute device106determines that the identified network packet size is less than or equal to the packet size threshold the method300branches to block318, in which the network compute device106is configured to transmit a cache line demotion instruction to the cache manager214to demote the one or more cache lines associated with the processed network packet from the core-local cache114to the shared cache116. Additionally, in block320, the network compute device includes a cache line identifier of each determined cache line in the core-local cache114in the cache line demotion instruction. Referring back to block316, if the demotion manager220determines that the network packet size is greater than the packet size threshold, the method300branches to block322, in which the network compute device106transmits a cache line demotion command to the cache line demote device130to trigger a cache line demotion operation to demote one or more cache lines associated with the processed network packet from the core-local cache114to the shared cache116. Additionally, in block324, the network compute device106includes one or more cache line identifiers corresponding to the one or more cache lines to be demoted in the cache line demotion command.

Referring now toFIGS. 4 and 5, in use, the network compute device106establishes an illustrative environment400for demoting cache lines to shared cache116via cache line demote instructions and an illustrative environment500for demoting cache lines to shared cache116via cache line demote commands to a cache line demote device130. Referring now toFIG. 4, the illustrative environment400includes the HFI126, a processor core110, the core-local cache114, the shared cache116, and the demote device130ofFIG. 1, as well as the cache manager214ofFIG. 2. Each of the illustrative core-local cache114and the shared cache116include multiple cache entries.

As illustratively shown, the core-local cache114includes multiple core-local cache entries404. The illustrative core-local cache entries404include a first core-local cache entry designated as core-local cache entry (1)404a, a second core-local cache entry designated as core-local cache entry (2)404b, a third core-local cache entry designated as core-local cache entry (3)404c, a fourth core-local cache entry designated as core-local cache entry (4)404d, and a fifth core-local cache entry designated as core-local cache entry (N)404e(i.e., the “Nth” core-local cache entry404, wherein “N” is a positive integer and designates one or more additional core-local cache entries404). Similarly, the illustrative shared cache116includes multiple shared cache entries406. The illustrative shared cache entries406include a first shared cache entry designated as shared cache entry (1)406a, a second shared cache entry designated as shared cache entry (2)406b, a third shared cache entry designated as shared cache entry (3)406c, a fourth shared cache entry designated as shared cache entry (4)406d, and a fifth shared cache entry designated as shared cache entry (N)406e(i.e., the “Nth” shared cache entry406, wherein “N” is a positive integer and designates one or more additional shared cache entries406).

Referring now toFIG. 5, similar to the illustrative environment ofFIG. 4, the illustrative environment500includes the HFI126, the processor core110, the core-local cache114, the shared cache116, and the demote device130ofFIG. 1, as well as the cache manager214ofFIG. 2. As described previously, the processor core110is configured to poll an available network packet form processing from the HFI126(e.g., via an HFI/host interface (not shown)) and perform some level of processing operation on at least a portion of the data of the network packet. As also described previously, upon completion of the processing operation, the processor core110is further configured to provide some indication that one or more cache lines are to be demoted from the core-local cache114to the shared cache116.

Referring back toFIG. 4, as illustratively shown, the indication provided by the processor core110is in the form of one or more cache line demote instructions. It should be appreciated that each cache line demote instruction is usable to identify a cache line from the core-local cache114and demote the data to the shared cache116. As such, it should be appreciated that such instructions may not be as efficient for larger packets. Accordingly, the processor110may be configured to, for larger blocks of data, utilize the cache line demote device to offload the demote operation. To do so, referring again toFIG. 5, the processor110may be configured to transmit a cache line demotion command502to the cache line demote device130to trigger a cache line demotion operation to be performed by the cache line demote device130, such as may be performed via a data read request, a DMA request, etc., or any other type of request that will result in the data being demoted to shared cache116as a side effect without wasting processor core cycles.

As illustratively shown in bothFIGS. 4 and 5, the data in core-local cache line (1)404a, core-local cache line (2)404b, and core-local cache line (3)404cis associated with the processed network packet, as indicated by the highlighted outline surrounding each of those core-local cache lines404. As also illustratively shown, the cache line demotion operation results in that data being demoted such that the data in core-local cache line (1)404ais demoted to shared cache line (1)406a, the data in core-local cache line (2)404bis demoted to shared cache line (2)406b, and the data in core-local cache line (3)404cis demoted to shared cache line (3)406c; however, it should be appreciated that, as a result of the cache line demotion operation, the demoted cache lines may be moved to any available shared cache lines406.

Examples

Example 1 includes a compute device for demoting cache lines to a shared cache, the compute device comprising one or more processors, wherein each of the one or more processors includes a plurality of processor cores; a cache memory, wherein the cache memory includes a core-local cache and a shared cache, wherein the core-local cache includes a plurality of core-local cache lines, and wherein the shared cache includes a plurality of shared cache lines; a cache line demote device; and a host fabric interface (HFI) to receive a network packet, wherein a processor core of a processor of the one or more processors is to retrieve at least a portion of data of the received network packet, wherein to retrieve the data comprises to move the data into one or more core-local cache lines of the plurality of core-local cache lines; perform one or more processing operations on the data; and transmit, subsequent to having completed the one or more processing operations on the data, a cache line demotion command to the cache line demote device, and wherein the cache line demote device is to perform, in response to having received the cache line demotion command, a cache line demotion operation to demote the data from the one or more core-local cache lines to one or more shared cache lines of the shared cache.

Example 2 includes the subject matter of Example 1, and wherein the processor core is further to determine, subsequent to having completed the one or more processing operations on the data, whether a size of the received network packet is greater than a packet size threshold, wherein to transmit the cache line demotion command to the cache line demote device comprises to transmit the cache line demotion command subsequent to a determination that the size of the received network packet is greater than the packet size threshold.

Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the processor core is further to transmit, subsequent to having determined that the size of the received network packet is less than or equal to the packet size threshold, a cache line demote instruction to a cache manager of the cache memory, and wherein the cache manager is to demote the data from the one or more core-local cache lines to the one or more shared cache lines of the shared cache based on the cache line demote instruction, wherein the cache line demote instruction bypasses the cache line demote device.

Example 4 includes the subject matter of any of Examples 1-3, and wherein to transmit the cache line demotion instruction includes to transmit one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 5 includes the subject matter of any of Examples 1-4, and wherein to perform the cache line demotion operation comprises to perform a read request or a direct memory access.

Example 6 includes the subject matter of any of Examples 1-5, and wherein the cache line demotion command includes an indication of the core-local cache lines associated with the received network packet that are to be demoted to the shared cache.

Example 7 includes the subject matter of any of Examples 1-6, and wherein the cache line demote device comprises one of a copy engine, a direct memory access (DMA) device usable to copy data, or an offload device usable to perform a read operation.

Example 8 includes the subject matter of any of Examples 1-7, and wherein to transmit the cache line demotion command includes to transmit one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 9 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute device to retrieve, by a processor of the compute device, at least a portion of data of a network packet received by a host fabric interface (HFI) of the compute device, wherein to retrieve the data comprises to move the data into one or more core-local cache lines of a plurality of core-local cache lines of a core-local cache of the compute device, and wherein the processor includes a plurality of processor cores; perform, by a processor core of the plurality of processor cores, one or more processing operations on the data; transmit, by the processor and subsequent to having completed the one or more processing operations on the data, a cache line demotion command to a cache line demote device of the compute device; and perform, by the cache line demote device and in response to having received the cache line demotion command, a cache line demotion operation to demote the data from the one or more core-local cache lines to one or more shared cache lines of a shared cache of the compute device.

Example 10 includes the subject matter of Example 9, and wherein the processor core is further to determine, subsequent to having completed the one or more processing operations on the data, whether a size of the received network packet is greater than a packet size threshold, wherein to transmit the cache line demotion command to the cache line demote device comprises to transmit the cache line demotion command subsequent to a determination that the size of the received network packet is greater than the packet size threshold.

Example 11 includes the subject matter of any of Examples 9 and 10, and wherein the processor core is further to transmit, subsequent to having determined that the size of the received network packet is less than or equal to the packet size threshold, a cache line demote instruction to a cache manager of a cache memory that includes the core-local cache and the shared cache, and wherein the cache manager is to demote the data from the one or more core-local cache lines to the one or more shared cache lines of the shared cache based on the cache line demote instruction.

Example 12 includes the subject matter of any of Examples 9-11, and wherein to transmit the cache line demotion instruction includes to transmit one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 13 includes the subject matter of any of Examples 9-12, and wherein to perform the cache line demotion operation comprises to perform a read request or a direct memory access.

Example 14 includes the subject matter of any of Examples 9-13, and wherein to transmit the cache line demotion command includes to transmit one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 15 includes a method for demoting cache lines to a shared cache, the method comprising retrieving, by a processor of the compute device, at least a portion of data of a network packet received by a host fabric interface (HFI) of the compute device, wherein to retrieve the data comprises to move the data into one or more core-local cache lines of a plurality of core-local cache lines of a core-local cache of the compute device, and wherein the processor includes a plurality of processor cores; performing, by a processor core of the plurality of processor cores, one or more processing operations on the data; transmitting, by the processor core and subsequent to having completed the one or more processing operations on the data, a cache line demotion command to a cache line demote device of the compute device; and performing, by the cache line demote device and in response to having received the cache line demotion command, a cache line demotion operation to demote the data from the one or more core-local cache lines to one or more shared cache lines of a shared cache of the compute device.

Example 16 includes the subject matter of Example 15, and further including determining, subsequent to having completed the one or more processing operations on the data, whether a size of the received network packet is greater than a packet size threshold, wherein transmitting the cache line demotion command to the cache line demote device comprises to transmitting the cache line demotion command subsequent to a determination that the size of the received network packet is greater than the packet size threshold.

Example 17 includes the subject matter of any of Examples 15 and 16, and further including transmitting, by the processor core and subsequent to having determined that the size of the received network packet is less than or equal to the packet size threshold, a cache line demote instruction to a cache manager of a cache memory that includes the core-local cache and the shared cache; and demoting, by the cache manager, the data from the one or more core-local cache lines to the one or more shared cache lines of the shared cache based on the cache line demote instruction.

Example 18 includes the subject matter of any of Examples 15-17, and wherein transmitting the cache line demotion instruction includes transmitting one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 19 includes the subject matter of any of Examples 15-18, and wherein performing the cache line demotion operation comprises performing one of a read request or a direct memory access.

Example 20 includes the subject matter of any of Examples 15-19, and wherein transmitting the cache line demotion command includes transmitting one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 21 includes a compute device for demoting cache lines to a shared cache, the compute device comprising circuitry for retrieving, by a processor of the compute device, at least a portion of data of a network packet received by a host fabric interface (HFI) of the compute device, wherein to retrieve the data comprises to move the data into one or more core-local cache lines of a plurality of core-local cache lines of a core-local cache of the compute device, and wherein the processor includes a plurality of processor cores; circuitry for performing, by a processor core of the plurality of processor cores, one or more processing operations on the data; circuitry for transmitting, by the processor core and subsequent to having completed the one or more processing operations on the data, a cache line demotion command to a cache line demote device of the compute device; and means for performing, by the cache line demote device and in response to having received the cache line demotion command, a cache line demotion operation to demote the data from the one or more core-local cache lines to one or more shared cache lines of a shared cache of the compute device.

Example 22 includes the subject matter of Example 21, and further including circuitry for determining, subsequent to having completed the one or more processing operations on the data, whether a size of the received network packet is greater than a packet size threshold, wherein transmitting the cache line demotion command to the cache line demote device comprises to transmitting the cache line demotion command subsequent to a determination that the size of the received network packet is greater than the packet size threshold.

Example 23 includes the subject matter of any of Examples 21 and 22, and further including circuitry for transmitting, by the processor core and subsequent to having determined that the size of the received network packet is less than or equal to the packet size threshold, a cache line demote instruction to a cache manager of a cache memory that includes the core-local cache and the shared cache; and circuitry for demoting, by the cache manager, the data from the one or more core-local cache lines to the one or more shared cache lines of the shared cache based on the cache line demote instruction.

Example 24 includes the subject matter of any of Examples 21-23, and wherein transmitting the cache line demotion instruction includes transmitting one or more cache line identifiers corresponding to the one or more shared cache lines.

Example 25 includes the subject matter of any of Examples 21-24, and wherein the means for performing the cache line demotion operation comprises means for performing one of a read request or a direct memory access.