Semiconductor device

A semiconductor device includes a first base material having a first surface; a second base material having a coefficient of linear expansion different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface; and a first interconnect formed over the first and second surfaces to straddle a borderline between the first and second base materials. The cross-sectional area of the first interconnect along the borderline is greater than the cross-sectional area of at least part of a portion of the first interconnect on the first surface along a width of the first interconnect, or the cross-sectional area of at least part of a portion of the first interconnect on the second surface along the width of the first interconnect.

BACKGROUND

The present disclosure relates to interconnects on substrates and semiconductor packages, and more particularly relates to a semiconductor device including an interconnect extending over different base materials.

In the fields of semiconductor packages, with increasing miniaturization of transistors each formed on a semiconductor chip, the area of the semiconductor chip continues decreasing. Furthermore, with downsizing of devices including a semiconductor package, such as mobile phones, there has been an increasing demand to further downsize semiconductor packages.

To address this demand, wafer level packages (WLPs) or wafer level chip size packages (WL-CSPs) that can be each placed on a printed circuit board with the size of the semiconductor package kept small have been developed. A so-called redistribution layer is formed on each of semiconductor chips at the wafer level, and a solder ball is placed on an electrode connected to the redistribution layer. In this state, the wafer is singulated into semiconductor packages. Such semiconductor packages are referred to as WLPs. The WLPs allow the size of each of the semiconductor packages to be substantially equal to that of each of the semiconductor chips.

However, with increasing functionality required of semiconductor chips, the number of input/output terminals of a semiconductor package increases, and a WLP having a small area cannot include all terminals.

To address this problem, fan out WLPs have been proposed. The fan out WLPs are semiconductor packages that each include an extension surrounding a semiconductor chip and made of a material such as an epoxy resin, a redistribution interconnect extending from immediately above an electrode on the semiconductor chip to immediately above the extension, and solder balls on the semiconductor chip surface including the extension surface. Such semiconductor packages ensure the required number of terminals.

The fan out WLP includes an interconnect straddling the borderline between the principal surface of the semiconductor chip and the principal surface of an epoxy resin body. In addition to the fan out WLP, a semiconductor package that includes a semiconductor chip embedded in a recess formed in a glass epoxy resin substrate also includes an interconnect straddling the borderline between the principal surface of the semiconductor chip and the principal surface of a printed circuit board.

Japanese Unexamined Patent Publication No. 2000-183231 describes a package including an interconnect provided over two different base materials.

FIG. 10is a perspective view illustrating the configuration of a conventional semiconductor device described in Japanese Unexamined Patent Publication No. 2000-183231. As illustrated inFIG. 10, the conventional semiconductor device includes a semiconductor chip106that is flip-chip bonded onto a circuit board101.

A surface of the circuit board101includes circuit sections103, and a surface of the semiconductor chip106includes chip junction portions107. Interconnects102and104aand junction interconnect portions104are formed on the surface of the circuit board101so as to be each electrically connected to a corresponding one of the circuit sections103. The junction interconnect portions104are each provided on a corresponding one of low dielectric constant materials105.

The semiconductor chip106is bonded onto the circuit board101such that the surface of the circuit board101including the circuit sections103faces the surface of the semiconductor chip106including circuits. In this case, the semiconductor chip106is placed on the circuit board101such that the chip junction portions107each overlap a corresponding one of the junction interconnect portions104.

SUMMARY

When a semiconductor package or a substrate including an interconnect is practically used as a product, the semiconductor package or the substrate is heated and cooled to repeatedly undergo changes in temperature. Materials forming a semiconductor device have a coefficient of linear expansion (CLE) specific to heat. Here, the coefficient of linear expansion denotes the amount of expansion of a material along the length thereof per unit temperature.

When the temperature of a semiconductor device has changed, the amounts of expansion or contraction of materials having different CLEs (for example, the circuit board101and the low dielectric constant material105illustrated inFIG. 10) are different from each other. This difference induces a strain at the interface at which the materials having different CLEs are in contact with each other. Thus, when an interconnect is provided over base materials having different CLEs to straddle the borderline therebetween, a change in temperature of the semiconductor device produces a stress on the interconnect due to the strain at the interface. When the semiconductor device repeatedly undergoes changes in temperature, strain is accumulated in the interconnect, and the interconnect may be finally broken.

When an interconnect is formed over different base materials to straddle the borderline therebetween, a semiconductor device of the present disclosure can reduce the possibility that the interconnect may be broken.

In order to solve the problem, in the semiconductor device of the present disclosure, an interconnect is formed over base materials having different CLEs, and the cross-sectional area of a portion of the interconnect on a boundary region of the base materials is increased to improve the strength of the interconnect against strains induced on the boundary region of the base materials.

Specifically, an example semiconductor device according to the present disclosure includes: a first base material having a first surface on which a circuit is formed; a second base material having a CLE different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface and facing in a direction identical with a direction in which the first surface faces; and a first interconnect formed over the first and second surfaces to straddle a first borderline between the first and second base materials when viewed in plan, and connected to the circuit formed on the first surface. Furthermore, a cross-sectional area of the first interconnect along the first borderline is greater than a cross-sectional area of at least part of a portion of the first interconnect on the first surface along a width of the first interconnect, or a cross-sectional area of at least part of a portion of the first interconnect on the second surface along the width of the first interconnect.

Here, the situation where “the first and second surfaces face in an identical direction” includes errors arising from thermal expansion of the base materials and variations among fabricated base materials. The first and second surfaces may be adjacent to each other while having different heights without interfering with the formation of the interconnect.

The configuration above increases the cross-sectional area of a portion of the first interconnect on the boundary region to improve the strength of the interconnect. Thus, even when changes in temperature cause misalignment between the first and second base materials or a strain at the interface between the first and second base materials, the possibility that the interconnect may be broken can be reduced. This further improves the reliability of the semiconductor device.

Such a configuration of the interconnect can be used also in a so-called fan out WLP and a semiconductor package including the fan out WLP, and significantly contributes to improvement in reliability of such semiconductor devices. When such a configuration is used in a fan out WLP, the first base material is a semiconductor chip, the second base material is an extension member, and the first interconnect is a so-called redistribution interconnect.

As described above, the example semiconductor device according to the present disclosure can reduce the possibility that an interconnect formed over different base materials to straddle the borderline between the different base materials may be, for example, broken.

DETAILED DESCRIPTION

Embodiment

An embodiment of the present disclosure will be described hereinafter with reference to the drawings.FIG. 1is a plan view illustrating a semiconductor device according to the embodiment of the present disclosure.FIG. 2Ais a cross-sectional view of the semiconductor device of this embodiment taken along the line IIa-IIa illustrated inFIG. 1, andFIG. 2Bis a cross-sectional view of the semiconductor device taken along the line IIb-IIb illustrated inFIG. 1.

As illustrated inFIG. 1, the semiconductor device of this embodiment includes a base material1, a base material2, and interconnects31,32, and33. The base material2is in contact with the base material1, and has a principal surface20being adjacent to a principal surface19of the base material1and facing in a direction identical with the direction in which the principal surface19faces. The interconnects31,32, and33are each provided over the principal surface19of the base material1and the principal surface20of the base material2to straddle a borderline28between the base materials1and2when viewed in plan. The borderline28here is the borderline between the principal surfaces19and20.

The base materials1and2are materials having different coefficients of linear expansion (CLEs). The base materials1and2may be each a semiconductor chip made of, e.g., silicon (Si), or an epoxy resin substrate made of, e.g., an FR4 resin, an FR5 resin, or a bismaleimide triazine (BT) resin. The base materials1and2may be, for example, an epoxy encapsulating resin, ceramic, glass, a metal such as copper or gold, a solid material obtained by plating the epoxy encapsulating resin, ceramic, glass, or the metal, or an alloy, and are not limited as long as they are solid objects having different CLEs. Note that the base materials1and2may be plate-like in shape. The principal surfaces19and20may be flush with each other. Alternatively, the heights of the principal surfaces19and20may be different from each other as long as the interconnects can be formed directly on the principal surfaces or on the principal surfaces with an insulating protective film interposed between the interconnects and the principal surfaces.

At least one of the base materials1and2may include circuits (not shown) electrically connected to the interconnects31,32, and33. The circuits may be formed on the principal surface19or20.

The interconnects31,32, and33are metal interconnects made of, e.g., copper or aluminum. When the base materials1and2are made of an insulating material, the interconnects31,32, and33may be provided directly on the base materials1and2. However, when the base materials1and2are made of at least a conductive material or a semiconductor, the interconnects31,32, and33are provided on the base materials1and2with an insulating protective film4interposed between the interconnects31,32, and33and the base materials1and2as illustrated inFIGS. 2A and 2B. To clearly show the borderline between the base materials1and2, the insulating protective film4is not shown inFIG. 1.

As illustrated inFIGS. 1,2A, and2B, in the semiconductor device of this embodiment, the cross-sectional area of the interconnect31along the borderline28is greater than the cross-sectional area of at least part of a portion of the interconnect31on the principal surface19along the interconnect width, and/or the cross-sectional area of at least part of a portion of the interconnect31on the principal surface20along the interconnect width.

The cross-sectional area of the interconnect32along the borderline28is also greater than the cross-sectional area of at least part of a portion of the interconnect32on the principal surface19along the interconnect width, and/or the cross-sectional area of at least part of a portion of the interconnect32on the principal surface20along the interconnect width, and the cross-sectional area of the interconnect33along the borderline28is also greater than the cross-sectional area of at least part of a portion of the interconnect33on the principal surface19along the interconnect width, and/or the cross-sectional area of at least part of a portion of the interconnect33on the principal surface20along the interconnect width.

Specifically, the width of a portion of the interconnect31on a boundary region8including the borderline28(i.e., an interconnect widening portion31a) is greater than that of a portion of the interconnect31on each of non-boundary regions9and10. Here, the boundary region8denotes a region of a group of the principal surfaces19and20near the borderline28, and the non-boundary regions9and10denote regions of the principal surfaces19and20, respectively, except the boundary region8. The non-boundary regions9and10are away from the borderline28. The boundaries of the boundary region8are optionally determined by the design of the semiconductor device.

The direction of extension of a portion32aof the interconnect32on the boundary region8including the borderline28is not orthogonal to the borderline28. In the example illustrated inFIG. 1, the portion32aextends obliquely relative to the direction of extension of portions of the interconnect32on the non-boundary regions9and10.

The interconnect33branches into a plurality of interconnects (inFIG. 1, two interconnects) on the boundary region8including the borderline28. Thus, the sum of the cross-sectional area of a branch portion33aof the interconnect33along the borderline28and the cross-sectional area of a branch portion33bof the interconnect33along the borderline28is greater than the cross-sectional area of a portion of the interconnect33on each of the non-boundary regions9and10along the interconnect width.

To fabricate the semiconductor device of this embodiment, base materials1and2are first bonded together. In this case, when one of the base materials is made of a resin material such as an epoxy resin, curing of the resin allows both the base materials to be bonded together. When the base materials are made of silicon, ceramic, or a metal such as copper, the base materials may be bonded together using an adhesive, or a recess may be formed in one of the base materials, and the other base material may be embedded in the recess. Alternatively, while the back surfaces of both the base materials are fixed with a tape, a principal surface19of the base material1and a principal surface20of the base material2may be coated with a protective film made of polyimide to bond both the base materials together.

Next, if necessary, electrodes are formed on the principal surfaces19and20. Subsequently, an insulating protective film4is formed on the principal surfaces19and20of the base materials1and2by, for example, spin coating. The thickness of the insulating protective film4is not specifically limited. However, the thickness of the insulating protective film4here is, for example, about 5 μm. Subsequently, portions of the insulating protective film4are etched away to form openings on the electrodes (not shown) provided on the principal surfaces19and20of the base materials1and2. Next, interconnects31,32, and33shaped as described above are formed by, for example, a subtractive process or an additive process. In the foregoing manner, the semiconductor device of this embodiment can be fabricated.

This method merely requires changing the shapes of, e.g., masks for use in the formation of interconnects, and enables the fabrication of the semiconductor device of this embodiment without causing the number of process steps to be greater than that for a conventional semiconductor device.

As described above, in the semiconductor device of this embodiment, the cross-sectional areas of the interconnects31,32, and33along the borderline28are respectively greater than the cross-sectional areas of portions of the interconnects31,32, and33on each of the non-boundary regions9and10along the interconnect widths. Thus, even when the semiconductor device undergoes changes in temperature, and the changes in temperature induce misalignment between the base materials1and2or a strain at the interface therebetween, the interconnects are less likely to be broken.

In contrast to this, in the conventional semiconductor device illustrated inFIG. 10, the cross-sectional area of the joint between each of the interconnects104aand a corresponding one of the junction interconnect portions104along the borderline between the top surface of the circuit board101and the top surface of a corresponding one of the low dielectric constant materials105is less than the cross-sectional area of the corresponding one of the junction interconnect portions104. The width of the interconnect104aon the circuit board101is less than that of the junction interconnect portion104on the low dielectric constant material105. Thus, in the conventional semiconductor device, the interconnects104atend to be subject to stress, such as strains arising from changes in temperature, on the borderlines between the top surface of the circuit board101and the top surfaces of the low dielectric constant materials105.

As such, in the semiconductor device of this embodiment, the cross-sectional area of a portion of an interconnect on the boundary region is greater than that of the conventional semiconductor device, and the interconnect strength, therefore, increases. Thus, even when the semiconductor device repeatedly undergoes changes in temperature, the interconnect is less likely to be broken, and the reliability of the semiconductor device is further improved.

Since, in particular, the interconnect31has the interconnect widening portion31aon the boundary region8, the strength of a portion of the interconnect31on the boundary region8significantly increases.

While the strength of a portion of the interconnect32on the boundary region8of the principal surfaces19and20increases, the width of the interconnect32does not vary across the entire interconnect32. This can prevent a reduction in interconnect density.

Since the interconnect33branches into the plurality of branch portions33aand33bon the boundary region8, this increases the cross-sectional area of the interconnect33along the borderline28, thereby improving the interconnect strength. Furthermore, even when any one of the branch portions33aand33bis broken, the other one thereof is electrically continuous. Thus, the interconnect33is less likely to be defective.

The shape of a portion of an interconnect on the boundary region8when viewed in plan is not limited to the shape of a portion of each of the interconnects31,32, and33thereon when viewed in plan. For example, corners of the interconnect widening portion31amay be rounded when viewed in plan, or the width of the obliquely extending portion32aof the interconnect32may be greater than that of each of the other portions thereof. Alternatively, the branch portions33aand33bof the interconnect33may each have an obliquely extending portion.

Furthermore, all of one or more interconnects31, one or more interconnects32, and one or more interconnects33may be provided on the base materials1and2, or one or two of the interconnects31,32, and33may be provided thereon.

FIG. 3is a plan view illustrating another example semiconductor device according to the embodiment of the present disclosure.

Similarly to an interconnect44illustrated inFIG. 3, an interconnect provided over base materials1and2may have a portion located on a borderline28between the base materials1and2and having a width that increases only in one of directions along the interconnect width. Furthermore, similarly to an interconnect46, the cross-sectional area of an interconnect along the borderline28may be greater than the cross-sectional area of at least part of a portion of the interconnect on at least one of the base materials1and2along the interconnect width. In other words, the cross-sectional area of the interconnect along the borderline28merely needs to be greater than the cross-sectional area of at least part of a portion of the interconnect located on one of the base materials along the interconnect width. In this case, similarly to an interconnect48, with increasing distance from the borderline28, the width of a portion of an interconnect on the other one of the base materials1and2may increase such that the portion of the interconnect thereon extends radially outward.

FIG. 4is a cross-sectional view illustrating a variation of the semiconductor device according to the embodiment of the present disclosure.FIG. 4illustrates a cross section passing through an interconnect34and taken along a direction parallel to the direction of extension of the interconnect34.

Also in the semiconductor device of this variation, the cross-sectional area of the interconnect34along the borderline between principal surfaces19and20is greater than the cross-sectional area of a portion of the interconnect34on at least part of each of non-boundary regions9and10along the interconnect width similarly to the semiconductor device illustrated inFIG. 1.

However, unlike the interconnects31,32, and33illustrated inFIG. 1, the interconnect34illustrated inFIG. 4has a thick interconnect portion34athat is located on a boundary region8of the principal surfaces19and20and is thicker than the other portions of the interconnect34. The configuration of the semiconductor device according to this variation is similar to that of the semiconductor device illustrated inFIG. 1except for the interconnect shape.

To fabricate the semiconductor device of this variation, base materials1and2are bonded together, and then an insulating protective film4is formed on a principal surface19of the base material1and a principal surface20of the base material2by, for example, spin coating. Next, an interconnect34made of a metal is formed on the insulating protective film4by a known process. To form a thick interconnect portion34aof the interconnect34, a thick interconnect, for example, is formed, a portion of the thick interconnect that will be the thick interconnect portion34ais then masked by a process, such as silk screen printing, or with, for example, a photo resist, and portions of the thick interconnect except the portion thereof that will be the thick interconnect portion34aare etched. Alternatively, a plating resist may be formed on each of portions of an interconnect except a portion thereof that will be the thick interconnect portion34a, and in this situation, a plating may be grown on the interconnect to form the thick interconnect portion34a. In the foregoing manner, the semiconductor device of this variation can be fabricated.

When the thickness of a portion of the interconnect34on the borderline between the principal surface19of the base material1and the principal surface20of the base material2is greater than that of a portion of the interconnect34on each of the non-boundary regions9and10similarly to the semiconductor device of this variation, this can also increase the cross-sectional area of the interconnect34along the borderline. This increase in cross-sectional area can improve the strength of the interconnect34, and reduce the possibility that the interconnect34may be broken. When the width of the thick interconnect portion34aon the boundary region8is equal to that of a portion of the interconnect34on each of the non-boundary regions9and10, this can prevent a reduction in interconnect density.

When the thickness of each of the interconnect widening portion31aof the interconnect31illustrated inFIG. 1, the obliquely extending portion32aof the interconnect32illustrated therein, the branch portions33aand33bof the interconnect33illustrated therein is greater than that of a portion of a corresponding one of the interconnects on at least part of each of the non-boundary regions9and10, this can further increase the cross-sectional area of the interconnect along the borderline28. This configuration can further improve the strength of the interconnect. In particular, when the coefficient of linear expansion of the base material1is significantly different from that of the base material2, such an interconnect configuration is useful.

When the thickness of a portion of each of the interconnects44,46, and48, which are illustrated inFIG. 3, on the borderline28is greater than that of a portion of a corresponding one of the interconnects on each of the non-boundary regions9and10, this can reduce the possibility that the interconnects may be broken.

—Explanation of Semiconductor Device According to First Example of Application—

A first example of application in which the configuration described with reference toFIGS. 1,2A, and2B is used in a semiconductor device corresponding to a fan out WLP will be described hereinafter.

FIG. 5is a plan view illustrating a semiconductor device according to the first example of application of the embodiment of the present disclosure. For ease of understanding, an insulating protective film is not shown inFIG. 5.

As illustrated inFIG. 5, the semiconductor device of this example of application includes an extension member21, a semiconductor chip11, a first insulating protective film, chip electrodes51,52, and53, redistribution interconnects35,36, and37, a second insulating protective film, electrodes (not shown), and electrodes61,62, and63. The extension member21has a principal surface49including a recess40. The semiconductor chip11is placed in the recess40, and has a principal surface50that is adjacent to the principal surface49and faces substantially in a direction identical with the direction in which the principal surface49faces. The first insulating protective film is provided over the principal surfaces49and50. The chip electrodes51,52, and53are provided on the principal surface50to pass through the first insulating protective film. The redistribution interconnects35,36, and37each straddle the borderline between the principal surfaces49and50to extend from above the principal surface50to above the principal surface49. The second insulating protective film is provided over the first insulating protective film and the redistribution interconnects35,36, and37. The unshown electrodes pass through the second insulating protective film. The electrodes61,62, and63are respectively connected through the unshown electrodes to the redistribution interconnects35,36, and37.

The redistribution interconnects35,36, and37are electrically connected through the chip electrodes51,52, and53, respectively, to circuits (not shown) provided on the principal surface50of the semiconductor chip11.

Comparison between the semiconductor device of this example of application and the semiconductor device illustrated inFIG. 1shows that the semiconductor chip11corresponds to one of the base materials1and2, the extension member21corresponds to the other one of the base materials1and2, and the redistribution interconnects35,36, and37correspond to the interconnects31,32, and33, respectively.

Specifically, the redistribution interconnect35has a wider interconnect widening portion35aon a boundary region of the principal surface50of the semiconductor chip11and the principal surface49of the extension member21similarly to the interconnect31. The redistribution interconnect36has an obliquely extending portion36aon the boundary region of the principal surface50of the semiconductor chip11and the principal surface49of the extension member21similarly to the interconnect32. The redistribution interconnect37has branch portions37aand37bon the boundary region of the principal surface50of the semiconductor chip11and the principal surface49of the extension member21similarly to the interconnect33.

In the semiconductor device of this example of application, the principal surface49of the extension member21surrounds the principal surface50of the semiconductor chip11when viewed in plan.

For example, an encapsulating resin such as an epoxy resin is used as a material of the extension member21. However, the material is not limited to the epoxy resin, and may be, for example, ceramic or glass. Alternatively, the extension member21may be an organic substrate.

To fabricate the semiconductor device of this example of application, an extension member21is first formed outward from the side surfaces of a semiconductor chip11(outward of the semiconductor chip11) with a principal surface50of the semiconductor chip11exposed. In this case, the semiconductor chip11is entirely enclosed in a die with the principal surface50facing downward, and an encapsulating resin is injected into an internal space of the die to form the extension member21. This results in the semiconductor chip11placed in a recess40of the extension member21.

Next, chip electrodes51,52, and53are formed on the semiconductor chip11. Thereafter, a first insulating protective film is formed over the principal surface50of the semiconductor chip11and the principal surface49of the extension member21by, for example, spin coating.

Next, portions of the first insulating protective film covering the chip electrodes51,52, and53are removed by etching to expose the chip electrodes51,52, and53. Next, redistribution interconnects35,36, and37made of a metal are formed on an upper surface of the first insulating protective film by a subtractive process or an additive process to each form an optional shape. Then, electrodes61,62, and63are respectively formed on portions of the redistribution interconnects35,36, and37on the principal surface49of the extension member21. Next, a second insulating protective film is formed over the electrodes61,62, and63and the first insulating protective film, and then portions of the second insulating protective film covering the electrodes61,62, and63are removed to expose the electrodes61,62, and63. Subsequently, bumps (not shown) are appropriately formed on the electrodes61,62, and63.

In the semiconductor device of this example of application, similarly to the semiconductor device illustrated inFIG. 1, the cross-sectional area of each of the redistribution interconnects35,36, and37along the borderline between the principal surfaces49and50is greater than the cross-sectional area of a portion of a corresponding one of the interconnects35,36, and37away from the borderline along the interconnect width. This can improve the strengths of the interconnects against strains and misalignment caused by changes in temperature due to the difference in CLE between the semiconductor chip11and the extension member21. This improvement allows the reliability of the semiconductor device corresponding to a fan out WLP according to this example of application to be much higher than that of the conventional semiconductor device.

The redistribution interconnect37having the branch portions37aand37bcan improve its strength against strains, and even when any one of the branch portions37aand37bis broken, the redistribution interconnect37does not become defective as long as the other one of the branch portions37aand37bis electrically continuous.

In the semiconductor device illustrated inFIG. 5according to the first example of application, the shapes of the redistribution interconnects35,36, and37may be similar to those of the interconnects44,46, and48, respectively, illustrated inFIG. 3.

FIG. 6is a cross-sectional view illustrating a variation of the semiconductor device illustrated inFIG. 5according to the first example of application. InFIG. 6, the same characters as those inFIG. 5are used to designate equivalent elements.

In the semiconductor device of this variation, redistribution interconnects38provide connection between chip electrodes54provided on a semiconductor chip11and electrodes64for connection with an external member. The electrodes64each pass through a second insulating protective film42provided on a first insulating protective film41. Bumps71that are, for example, solder balls are each provided on a corresponding one of the electrode64.

As illustrated inFIG. 6, unlike the semiconductor device illustrated inFIG. 5, in the semiconductor device of this variation, the redistribution interconnects38each have a thick interconnect portion38aon a boundary region including the borderline between the principal surfaces49and50. The thick interconnect portion38ais thicker than the other portions of the redistribution interconnect38.

To fabricate the semiconductor device of this variation, similarly to the fabrication method for the semiconductor device illustrated inFIG. 5, a first insulating protective film41is first formed over a principal surface50of a semiconductor chip11and a principal surface49of an extension member21, and then chip electrodes54are formed on the principal surface50. The chip electrodes54may be formed, for example, on an outer region of the semiconductor chip11.

Next, redistribution interconnects38each having a thick interconnect portion38aare formed on the first insulating protective film41. To form the thick interconnect portion38a, for example, a uniformly thick redistribution interconnect may be formed, a portion of the thick redistribution interconnect that will be the thick interconnect portion38amay be then masked by a process, such as silk screen printing, or with, for example, a photo resist, and the thickness of each of portions of the thick redistribution interconnect except the portion of the thick redistribution interconnect that will be the thick interconnect portion38amay be reduced by etching. Alternatively, after a redistribution interconnect has been formed, a plating resist may be formed on each of portions of the redistribution interconnect except a portion thereof that will be the thick interconnect portion38a, and in this situation, a plating may be grown on the redistribution interconnect to form the thick interconnect portion38a.

Thereafter, an electrode64is formed on a portion of each of the redistribution interconnects38on the principal surface49of the extension member21. The electrode64is an electrode for electrical continuity with an external member. Next, a second insulating protective film42is formed over the electrode64and the first insulating protective film41. Subsequently, portions of the second insulating protective film42covering the electrodes64are removed by etching to expose the electrodes64. Next, a metal layer, such as an under barrier metal (UBM) layer, is formed on each of the exposed electrodes64, and a bump71that is, for example, a solder ball is formed on the metal layer, thereby forming a semiconductor device corresponding to a fan out WLP according to this variation.

When the thickness of a portion of each of the redistribution interconnects38on the borderline between the principal surfaces49and50is increased similarly to the semiconductor device of this variation, this also allows the cross-sectional area of the redistribution interconnect38(the thick interconnect portion38a) along the borderline to be greater than the cross-sectional area of a portion of the redistribution interconnect38away from the borderline along the interconnect width. This can improve the strength of the redistribution interconnect38, and thus, reduce the possibility that the redistribution interconnect38may be broken.

When, similarly to the redistribution interconnects38, the thickness of each of the interconnect widening portion35aof the redistribution interconnect35illustrated inFIG. 5, the obliquely extending portion36aof the redistribution interconnect36illustrated therein, the branch portions37aand37bof the redistribution interconnect37illustrated therein is greater than that of each of the other portions of a corresponding one of the redistribution interconnects, this can further improve the strengths of the redistribution interconnects35,36, and37. Thus, even when the coefficient of linear expansion of the semiconductor chip11is significantly different from that of the extension member21, breaks in the redistribution interconnects can be efficiently reduced.

WhileFIG. 6illustrates an example in which the principal surface49of the extension member21is flush with the principal surface50of the semiconductor chip11, the configurations of the principal surfaces49and50are not limited to this example. As long as the difference in height between the principal surfaces49and50is less than or equal to the thickness of the first insulating protective film41(10 μm or less), the redistribution interconnects38can be formed. In this case, even with a difference in height between the principal surfaces49and50, the formation of a thicker first insulating protective film41allows an upper surface of the first insulating protective film41to be flat enough to form the redistribution interconnects38. When the height of the principal surface49is different from that of the principal surface50, the phrase “the borderline between the principal surfaces49and50” in the above description denotes “the borderline between the principal surfaces49and50when viewed in plan.”

—Explanation of Semiconductor Device According to Second Example of Application—

FIG. 7is a cross-sectional view illustrating a semiconductor device according to a second example of application of the embodiment of the present disclosure. The semiconductor device of this example of application is a system-in-package (SiP) including the fan out WLP illustrated inFIG. 5or6. At least one of redistribution interconnects39illustrated inFIG. 7may have a thick interconnect portion39a, or may have an interconnect widening portion, an obliquely extending portion, or branch portions similarly to any one of the redistribution interconnects35,36, and37illustrated inFIG. 5. Chip electrodes each configured to electrically connect circuits on a semiconductor chip11to the redistribution interconnects39are not shown.

As illustrated inFIG. 7, the semiconductor device of this example of application includes the fan out WLP illustrated inFIG. 5or6, a semiconductor chip12flip-chip bonded onto a principal surface (circuit formation surface) of the semiconductor chip11in the fan out WLP with a circuit formation surface of the semiconductor chip12facing toward the semiconductor chip11, a substrate81having an upper surface on which the fan out WLP is placed with an adhesive83interposed between the substrate81and the fan out WLP, wires (connection members)91through each of which an electrode65of the fan out WLP and a land82provided on the substrate81are connected together, and an encapsulating resin22.

In the fan out WLP illustrated inFIG. 7, no bump is formed on the electrode65provided on each of the redistribution interconnects39. Electrodes55are formed on the circuit formation surface of the semiconductor chip11, and bumps71athat are, for example, solder balls provide electrical connection between circuits on the semiconductor chip11and circuits on the semiconductor chip12.

The encapsulating resin22is provided on the upper surface of the substrate81to cover the side surfaces of the extension member21, the principal surface thereof including the redistribution interconnects39, a surface of the semiconductor chip12opposite to the circuit formation surface of the semiconductor chip12, and the wires91. An underfill material86is provided between the second insulating protective film42and the semiconductor chip12.

To fabricate the semiconductor device of this example of application, a fan out WLP is first formed similarly to the fabrication method for the semiconductor device illustrated inFIG. 6. Here, portions of first and second insulating protective films41and42are previously removed by, for example, etching to expose electrodes55formed on a semiconductor chip11.

Next, the fan out WLP (the semiconductor chip11) and the semiconductor chip12are flip-chip bonded together such that their circuit formation surfaces face each other. Bumps71aare previously formed on the semiconductor chip12. Thus, the electrodes55on the semiconductor chip11are aligned with the bumps71a, and the electrodes55and the bumps71aare pressed against each other while being heated, thereby electrically bonding the semiconductor chip11to the semiconductor chip12. The bumps71amay be made of, for example, gold instead of solder, or may be, for example, metal posts.

Next, the fan out WLP flip-chip bonded to the semiconductor chip12is adhered onto a substrate81with an adhesive83. Next, lands82provided on an upper surface of the substrate81are connected through wires91to electrodes65provided on a surface of the fan out WLP so as to be electrically connected to a circuit on the semiconductor chip11.

Next, the fan out WLP, the semiconductor chip12, and the wires91are encapsulated in a die with an encapsulating resin22. Subsequently, solder balls or electrodes are placed on the back surface of the substrate81, and consequently the semiconductor device of this example of application serves as a ball grid array (BGA) semiconductor package or a land grid array (LGA) semiconductor package.

As such, using the highly reliable fan out WLP illustrated inFIG. 5or6enables the fabrication of a similarly highly reliable semiconductor package.

When the cross-sectional area of an interconnect along the borderline between different base materials is greater than that of a portion of the interconnect on each of non-boundary regions, this allows not only the semiconductor package described above but also various semiconductor devices each including a fan out WLP to have high reliability.

—Explanation of Semiconductor Device According to Third Example of Application—

FIG. 8Ais a cross-sectional view illustrating a semiconductor device according to a third example of application of the embodiment of the present disclosure.FIG. 8Bis an enlarged cross-sectional view illustrating a portion A of the semiconductor device according to this example of application, andFIG. 8Cis an enlarged plan view of the portion A. What is illustrated in each ofFIGS. 8A and 8Bbetween a second insulating protective film42and a semiconductor chip12is an underfill material86. InFIG. 8C, a portion of each of redistribution interconnects39under the semiconductor chip12is illustrated by the broken line.

As illustrated inFIGS. 8A-8C, in the semiconductor device of the third example of application, the area of the semiconductor chip11when viewed in plan is greater than that of the semiconductor chip12when viewed in plan, unlike the semiconductor device illustrated inFIG. 7according to the second example of application.

When the coefficient of linear expansion of the semiconductor chip11is significantly different from that of an extension member21, stress is most likely concentrated on a portion of each of the redistribution interconnects39of the semiconductor device of this example of application immediately above the interface between the semiconductor chip11and the extension member21as described above. Furthermore, stress tends to be concentrated also on a portion of the redistribution interconnect39immediately below an end surface of the upper semiconductor chip12due to the difference in coefficient of linear expansion between the semiconductor chip12and an encapsulating resin22.

Thus, in the semiconductor device of this example of application, the cross-sectional area of a portion of each of the redistribution interconnects39immediately above at least the interface between the semiconductor chip11and the extension member21is greater than that of another portion thereof along the interconnect width. This efficiently reduces breaks in the interconnect.

Furthermore, as illustrated inFIG. 8C, a portion of one of the redistribution interconnects39extending from a region thereof immediately above the borderline between the semiconductor chip11and the extension member21to a region thereof immediately below the end surface of the semiconductor chip12may have a greater cross-sectional area along the interconnect width than another portion thereof. To increase the cross-sectional area of the portion of the redistribution interconnect39, the above-described thick interconnect portion39amay be formed, or the width of the redistribution interconnect39may be increased. Alternatively, a predetermined portion of the redistribution interconnect39including a portion thereof immediately above the interface between the semiconductor chip11and the extension member21, and a predetermined portion thereof including a portion thereof immediately below the end surface of the semiconductor chip12may each have a greater cross-sectional area along the interconnect width than another portion thereof on which stress is not concentrated.

As such, when the width or thickness of each of the portions thereof on which stress is concentrated is greater than that of another portion thereof in a situation where stress is concentrated on a plurality of portions of each of the redistribution interconnects39, this can more efficiently reduce ruptures or breaks in the redistribution interconnect at low cost without increasing the number of fabrication process steps.

—Explanation of Semiconductor Device According to Fourth Example of Application—

FIG. 9Ais a cross-sectional view illustrating a semiconductor device according to a fourth example of application of the embodiment of the present disclosure.FIG. 9Bis an enlarged cross-sectional view illustrating a portion A of the semiconductor device according to this example of application, andFIG. 9Cis an enlarged plan view of the portion A.

As illustrated inFIGS. 9A-9C, in the semiconductor device of the fourth example of application, the area of a semiconductor chip11when viewed in plan is less than that of a semiconductor chip12when viewed in plan, unlike the semiconductor device illustrated inFIG. 7according to the second example of application. InFIG. 9C, a portion of each of redistribution interconnects39under the semiconductor chip12is illustrated by the broken line.

When the coefficient of linear expansion of the semiconductor chip11is significantly different from that of an extension member21, stress is most likely concentrated on a portion of each of the redistribution interconnects39of the semiconductor device of this example of application immediately above the interface between the semiconductor chip11and the extension member21as described above. Furthermore, stress tends to be concentrated also on a portion of the redistribution interconnect39immediately below an end surface of the upper semiconductor chip12due to the difference in coefficient of linear expansion between the semiconductor chip12and an encapsulating resin22.

Thus, in the semiconductor device of this example of application, the cross-sectional area of a portion of each of the redistribution interconnects39immediately above at least the interface between the semiconductor chip11and the extension member21is greater than that of another portion thereof along the interconnect width. This efficiently reduces breaks in the interconnect.

Furthermore, as illustrated inFIG. 9C, a portion of one of the redistribution interconnects39extending from a region thereof immediately above the interface between the semiconductor chip11and the extension member21to a region thereof immediately below the end surface of the semiconductor chip12may have a greater cross-sectional area along the interconnect width than another portion thereof. To increase the cross-sectional area of the portion of the redistribution interconnect39, the above-described thick interconnect portion39amay be formed, or the width of the redistribution interconnect39may be increased. Alternatively, a predetermined portion of the redistribution interconnect39including a portion thereof immediately above the interface between the semiconductor chip11and the extension member21, and a predetermined portion thereof including a portion thereof immediately below the end surface of the semiconductor chip12may each have a greater cross-sectional area along the interconnect width than another portion thereof on which stress is not concentrated.

As such, when the width or thickness of each of the portions thereof on which stress is concentrated is greater than that of another portion thereof in a situation where stress is concentrated on a plurality of portions of each of the redistribution interconnects39, such as a situation where the size of the semiconductor chip11when viewed in plan is different from that of the semiconductor chip12when viewed in plan, this can more efficiently reduce ruptures or breaks in the redistribution interconnect at low cost without increasing the number of fabrication process steps.

The present disclosure is not limited to the embodiment described above, its variations, and the examples of application, and various changes and modifications can be made to the configurations of semiconductor devices according to the embodiment, the variations, and the examples of application without departing from the scope and spirit of the present disclosure.

An example semiconductor device according to the present disclosure can be used as a device having an interconnect formed over base materials with different coefficients of linear expansion to straddle the borderline between the base materials. The example semiconductor device according to the present disclosure is useful for, for example, SiPs each including a fan out WLP, and various electronic devices each including a SiP.