Heterostructure power transistor with AlSiN passivation layer

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

TECHNICAL FIELD

The present invention relates generally to high-voltage field effect transistors (FETs); more specifically, to high-electron-mobility transistors (HEMTs) and heterostructure field-effect transistors (HFETs), and to methods of fabricating such power transistor devices.

BACKGROUND

One type of high-voltage FET is a heterostructure FET (HFET), also referred to as a heterojunction or high-electron mobility transistor (HEMT). HFETs based on gallium nitride (GaN) and other wide bandgap direct transitional semiconductor materials, such as silicon carbide (SIC), are advantageously utilized in certain electronic devices due to their superior physical properties over silicon-based devices. For example, GaN and AlGaN/GaN transistors are commonly used in high-speed switching and high-power applications (e.g., power switches and power converters) due to the high electron mobility, high breakdown voltage, and high saturation electron velocity characteristics offered by GaN-based materials and device structures. Due to the HFETs physical properties, HFETs may change states substantially faster than other semiconductor switches that conduct the same currents at the same voltages and the wide bandgap may improve performance of the HFET at elevated temperatures.

GaN-based HFETs devices are typically fabricated by epitaxial growth on substrate semiconductor materials such as silicon, sapphire and silicon carbide formed into a thin disk or wafer. The fabrication steps for forming electronic devices (e.g., transistors) directly in the semiconductor material are frequently referred to as front-end-of-line (FEOL) processing. During FEOL processing of an HFET, the wafer may be moved from various machines to build the various material layers of the device structure. But because GaN is a piezoelectric material, GaN-based HFET devices are susceptible to charge build-up (positive or negative) during FEOL processing. For example, charge build-up may result from the passivation process which involves deposition or growth of dielectric layers on the surface of a semiconductor. Passivation may be utilized to provide electrical stability by isolating the surface of the wafer from electrical and chemical conditions in the environment. For instance, exposure to air during fabrication of the HFET can cause surface reactions such as oxidation to occur which may impact the overall performance of the HFET device.

DETAILED DESCRIPTION

In the descriptions below, an example HFET is used for the purpose of explanation. However, it should be appreciated that embodiments of the present invention may be utilized with other types of FETs, such as a metal oxide semiconductor FET (MOSFET) or metal insulator semiconductor FET (MISFET) devices.

As mentioned above, sheet charge may accumulate on the wafer of HFET devices during fabrication processing. To combat the effects of accumulated surface charge and to protect the HFET devices from other environmental conditions, one or more layers of dielectric material may be used as a passivation layer that protects the surface of the HFET.

In accordance with embodiments of the present invention, a GaN-based HFET device structure and method of fabricating the same is disclosed which utilizes a new material combination based on aluminum silicon nitride (AlSiN) to passivate a GaN surface of a HFET device. In one embodiment, the AlSiN layer functions both as a passivation layer and a gate dielectric in the HFET device. Compared with traditional passivation materials, the wider bandgap of AlSiN when used in the HFET structure described herein may minimize current collapse during switching, reduce gate leakage, and provide enhanced gate reliability and stability.

In one embodiment, the HFET device has first and second active layers with a two-dimensional electron gas layer forming therebetween. A passivation layer of AlSiN (e.g., AiSi3N4) is disposed on the second active layer. The AlSiN passivation layer may also serve as a first gate dielectric layer. (In the present disclosure, this dual function layer is also referred to as a passivation/first gate dielectric layer.) In a further embodiment, a second gate dielectric layer is disposed on the first gate dielectric layer. In one example, aluminum oxide (Al2O3) is utilized for the second gate dielectric layer. In other embodiments, one or more additional layers are formed over the second gate dielectric layer. A gate member is disposed above the AlSiN passivation layer. Ohmic contacts (source and drain) of the device extend down to the second active layer.

FIG. 1illustrates a cross-sectional side view of an example semiconductor device100, i.e., a HFET device, which includes a first active layer102, also referred to as a channel layer, a second active layer106, also called a barrier or donor layer, a passivation layer108, a gate112, and respective source and drain ohmic contacts114and116. Respective source and drain ohmic contacts114and116are shown extending vertically down through passivation layer108to electrically connect to second active layer106. As shown, source and drain ohmic contacts114&116are laterally spaced-apart, with gate114being disposed between source and drain ohmic contacts116&118.

Further shown inFIG. 1is an electrical charge layer104which is formed between the first active layer102and the second active layer106. The electrical charge layer104is sometimes referred to as a two-dimensional electron gas (2DEG) layer104. The 2DEG layer104defines a lateral conductive channel for the HFET device. The 2DEG layer104forms due to the bandgap difference between the two active layers. In particular, the 2DEG layer104forms due to the change in spontaneous and piezoelectric polarizations between the two active layers. Electrons trapped in a quantum well that results from the bandgap difference between the respective first and second active layer102and106are thus free to move laterally in two (horizontal) dimensions but are tightly confined in the third (vertical) dimension.

In the context of the present disclosure, the term “in-situ” refers to a process that is carried out within a single tool or reaction chamber without exposing the wafer to the environment outside the tool or chamber. Further, the term “ex-situ” may refer to a process that is not carried out in a single tool. In another embodiment, formation of passivation layer108may be carried out using metal-organic chemical vapor decomposition (MOCVD) after formation of the first and second active layers102and106, respectively. In other words, the passivation layer108may be deposited in-situ with the first and second active layers102and106, respectively.

It is appreciated that first active layer102is typically disposed over a substrate (not shown) formed of any one of a number of different materials, such as sapphire (Al2O3), silicon (Si), GaN, or silicon carbide (SiC). In one embodiment, first active layer102comprises an epitaxial GaN layer. To avoid possible problems with lattice mismatch and/or differences in thermal coefficients of expansion, one or more additional layers may be disposed between first active layer102and the underlying substrate. For example, an optional thin nucleation layer may be formed between the substrate and first active layer102. In other examples, first active layer102may comprise different semiconductor materials containing various nitride compounds of other Group III elements. In addition, a thin (˜1 nm) layer of AlN may be formed on top of first active layer102prior to formation of second active layer106. First active layer102may be grown or deposited on the substrate.

The second active layer106is disposed on the first active layer102. In the example ofFIG. 1; second active layer106comprises aluminum gallium nitride (AlGaN). In other examples, different Group III nitride semiconductor materials such as aluminum indium nitride (AlInN) and aluminum indium gallium nitride (AlInGaN) may be used for second active layer106. In other embodiments, the material of second active layer106may be a non-stoichiometric compound. In such materials, the ratios of the elements are not easily represented by ordinary whole numbers, For example, the second active layer106may be a non-stoichiometric compound of a Group III nitride semiconductor material such as AlXGa1-XN, where 0<X<1. In one implementation, second active layer106comprises AlGaN (Al 25%) having a thickness of about 20 nanometers (nm) thick. A thin (˜1 nm) termination layer of GaN may be optionally formed on top of second active layer106prior to formation of passivation layer108. The second active layer106may be grown or deposited on the first active layer102.

As shown inFIG. 1, passivation layer108is disposed on second active layer106. As discussed above, in one embodiment, passivation layer108comprises aluminum silicon nitride (AlSiN). In one example, the thickness of passivation108may be in an approximate range of 1-10 nanometers (nm) thick. Further, in one implementation passivation layer108is substantially 5-10% of aluminum (Al) to silicon nitride (SiN) and formed between 1-10 nm thick. As previously discussed, passivation layer108may be deposited in-situ with the first and second active layers102and106, respectively, and utilized to passivate the GaN-based active layers. In one example, passivation layer108has purity, density, and strength characteristics similar to a layer grown in-situ using MOCVD. For example, a layer grown in-situ generally has greater purity, higher strength, and higher density as compared to a layer grown ex-situ. Further, passivation layer108may also be utilized as a gate dielectric layer.

Passivation layer108separates gate112from second active layer106. As shown, gate112is disposed atop passivation layer108. In one embodiment, gate112comprises a gold nickel (NiAu) alloy. In another embodiment, gate112comprises a titanium gold (TiAu) alloy or molybdenum gold MoAu alloy. In other examples, gate112may comprise a gate electrode and gate field plate. In operation, gate112controls the forward conduction path between respective source and drain ohmic contacts114&116. In the example ofFIG. 1, the portion of gate112which is above passivation layer108and extends laterally towards ohmic drain contact116serves as a gate field plate, which functions to alleviate the electric field intensity at an edge (closest to ohmic drain contact116).

Ohmic contacts114and116are disposed through passivation dielectric layer108to contact second active layer106. Ohmic contact114is one example of a source contact, while ohmic contact116is one example of a drain contact. In one embodiment, ohmic contacts114and116may be formed by etching openings in passivation layer108, followed by a metal deposition and annealing steps.

As shown,FIG. 1illustrates the device structure at a point in the fabrication process just after formation of gate112and ohmic metal contacts114and116, which respectively comprise source and drain electrodes of Gail HFET device100.FIG. 1shows ohmic metal contacts114and116formed directly on passivation layer108. In other embodiments, ohmic metal contacts114and116may be formed in recesses which extend vertically downward into the second active layer106. In still other embodiments, ohmic metal contacts114and116may be formed in recesses that extend vertically downward through second active layer106to contact the first active layer102.

When semiconductor device100is configured for use as a power switch, gate112and ohmic contacts114and116are typically coupled through terminals to form electrical connections to external circuits. In operation, electric charge in 2DEG layer104flows laterally between ohmic contacts114and116to become a current in an external circuit. The electric charge flow, and hence the current, may be controlled by a voltage from an external circuit that is electrically connected between the gate112and ohmic contact114.

As used in this disclosure, an electrical connection is an ohmic connection. An ohmic connection is one in which the relationship between the voltage and the current is substantially linear and symmetric for both directions of the current. For example, two metal patterns that contact each through only metal are electrically connected. In contrast, ohmic contacts114and116are not electrically connected to each other in semiconductor device100because any connection between these two contacts is through a channel in the semiconductor material, which conduction path is controlled by gate112. Similarly, gate112is not electrically connected to second active layer106since passivation layer108insulates gate112from the underlying active layers.

As discussed above, utilizing AlSiN as passivation layer108helps to alleviate the adverse effects of accumulated surface charge during the fabrication and/or handling of the device100. In addition, utilizing AlSiN as passivation layer108in the HFET structure described herein may minimize current collapse during switching, reduce gate leakage, and provide enhanced gate reliability and stability. Further, passivation layer108may also be utilized as a gate dielectric layer.

FIG. 2illustrates a cross-sectional side view of an example semiconductor device (HFET device)200which includes a first active layer202, a second active layer206, and a 2DEG layer204formed there between. Also shown are a passivation/first gate dielectric layer208, a second gate dielectric210, a gate212, and respective source and drain ohmic contacts214and216. Semiconductor device200shown inFIG. 2is the similar to semiconductor device100ofFIG. 1, except that HFET device200includes a second gate dielectric layer210atop passivation layer218. Second gate dielectric layer210is disposed on passivation/first gate dielectric layer208and laterally surround respective source and drain ohmic contacts114and116, as well as gate112. Further, passivation/first gate dielectric layer208is similar to passivation layer108, however is referred to as “passivation/first gate dielectric layer” to emphasize that the passivation layer208may also be utilized as one layer of multiple gate dielectric layers.

As shown, second gate dielectric layer210is disposed on passivation/first gate dielectric layer208. In one example, second gate dielectric layer210comprises aluminum oxide (Al2O3). In still further examples, other oxide materials, such as ZrO, HfO, SiO2and GdO, may be utilized for the second gate dielectric layer210. In one embodiment, second gate dielectric layer210has a thickness in the range of approximately 10-20 nm thick. In one embodiment, second gate dielectric layer210is thicker than passivation/first gate dielectric layer208. For example, the thickness of passivation/first gate dielectric layer208may be in a range of approximately 1-10 nm. In one example fabrication process, second gate dielectric layer210may be deposited ex-situ from respective first and second active layers202&206utilizing atomic layer deposition (ALD).

As shown, passivation/first gate dielectric layer208and second gate dielectric layer210vertically separate gate212from second active layer206. In certain embodiments, gate212may comprise a gate electrode and a gate field plate member. In the example ofFIG. 2, the portion of gate212which is above the second passivation layer218and extends laterally towards drain ohmic contact216serves as a gate field plate member, which functions to alleviate the electric field intensity at an edge (closest to drain ohmic contact216).

As shown, source and drain ohmic contacts214and216are respectively disposed on opposite lateral sides of gate212. Ohmic contacts214and216extend vertically the second gate dielectric layer210and passivation/first gate dielectric layer208to contact second active layer206. In one embodiment, ohmic contacts214and216may be formed by etching openings in the second gate dielectric layer210and passivation/first gate dielectric layer208, followed by a metal deposition and annealing steps. In another example fabrication process, ohmic contacts214and216may be formed before the deposition of second gate dielectric layer210.

Further, passivation/first gate dielectric layer208may be utilized as one gate dielectric layer along with second gate dielectric layer210. Practitioners in the art will appreciate that utilizing multiple gate dielectric layers in the manner described herein may advantageously produce higher critical voltage operation of the resulting HFET device. The critical voltage, VCRIT, is defined as the gate-to-source voltage. VGS, at which there is a relatively sharp rise in the gate leakage current. In addition, the use of multiple gate dielectric layers may improve the thermal stability of semiconductor device200as compared to a device utilizing only a single gate dielectric layer. Thermal stability relates to how much the gate leakage current of the device increases with temperature.

FIG. 3illustrates a cross-sectional side view of an example semiconductor device (HFET device)300which includes a first active layer302, a second active layer306; and a 2DEG layer304formed therebetween. Also shown are a passivation/first gate dielectric layer308, a second gate dielectric310, an upper passivation layer318, a gate312, and respective source and drain ohmic contacts314and316. Semiconductor device300shown inFIG. 3is similar to the semiconductor device100ofFIGS. 1 and 200ofFIG. 2, except that HFET device300includes upper passivation layer318. Upper passivation layer318is disposed on second gate dielectric310and laterally surround respective source and drain ohmic contacts314and316, as well as gate312. Further, passivation/first gate dielectric layer308is similar to passivation layer108, however is referred to as “passivation first gate dielectric layer” to emphasize that the passivation layer1first gate dielectric layer308may also be utilized as one layer of multiple gate dielectric layers.

In one embodiment, upper passivation layer318may comprise a dielectric material such as silicon nitride (SiN). In other embodiments, upper passivation layer318may comprise multiple layers of material. It is appreciated that upper passivation layer318provides stability of the electrical characteristics of HFET device300by isolating the surface of the device from electrical and chemical contaminants in the surrounding environment. Upper passivation layer218may be deposited through chemical vapor deposition such as low pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

As shown, upper passivation layer318, passivation/first gate dielectric layer308and second gate dielectric layer310vertically separate gate312from second active layer306. In certain embodiments, gate312may comprise a gate electrode and a gate field plate member. As shown, gate312extends vertically through an opening formed in upper passivation layer318to contact second gate dielectric layer210. In an example fabrication process, gate312may be formed by etching an opening in upper passivation layer318, followed by a gate metal deposition. In the example ofFIG. 3, the portion of gate312which is above the upper passivation layer318and extends laterally towards drain ohmic contact316serves as a gate field plate member, which functions to alleviate the electric field intensity at an edge (closest to drain ohmic contact316).

As shown, source and drain ohmic contacts314and316are respectively disposed on opposite lateral sides of gate312. Ohmic contacts314and316extend vertically through upper passivation layer318, second gate dielectric layer310, and passivation first gate dielectric layer308to contact second active layer306. In one embodiment ohmic contacts314and316may be formed by etching openings in upper passivation layer318, second gate dielectric layer310, and passivation/first gate dielectric layer308, followed by a metal deposition and annealing steps. In another example fabrication process, ohmic contacts314and316may be formed before the deposition of second gate dielectric layer310and the upper passivation layer318.

FIG. 4illustrates an example process flow400for constructing a semiconductor device such as HFET devices100,200, or300respectively shown inFIGS. 1,2, and3. In the example shown, the process starts after the completion of the epitaxial growth or deposition of the first and second active layers on the substrate. Formation of the passivation layer (also referred to as the passivation/first gate dielectric layer above) comprising AlSiN is carried out in-situ after growth of the GaN/AlGaN active layers (block402). In one embodiment, the passivation layer is deposited using a MOCVD technique carried out at a temperature range between 800-900° C. with a reactor pressure of about100Torrs. In one embodiment a passivation layer comprising AlSiN is grown with a MOCVD technique using silane (SiH4), ammonia (NH3) and trimethylaluminum (TMAl) as precursors for the AlSiN. Hydrogen (H2) and nitrogen (N2) may be used as carrier gases A total flow of about 50 l/min. with NH3flow in a range of about 1-10 l/min., SiH4of about 1 l/min., and TMAl flow in a range of about 5-20 sccm. The NH3flow is maintained so that the integrated N composition is maintained at stoichiometry between Si3N4and AlN as monitored by the overall refractive index and the density of the AlSiN film.

The passivation layer is formed to a thickness in a range of approximately 1-10 nm, and is continuous over the surface of the wafer, In one embodiment, the thickness of the passivation layer is about 5 nm. In still another embodiment, the passivation layer is formed in-situ with the first and second active layers. For example, the same MOCVD machine that is used to form the first and second active layers may also be used to form the passivation/first gate dielectric layer. In one example, the passivation layer/first gate dielectric layer has purity, density, and strength characteristic to a layer grown in-situ using MOCVD. For example, a layer grown in-situ generally has greater purity, higher strength, and higher density to a layer grown ex-situ.

After growth of the passivation layer, the surface of the passivation layer undergoes mesa isolation etching to define the active region of the ohmic contacts (block404). The mesa isolation may be performed utilizing a reactive-ion etching (RIE) system. In other fabrication methods, the mesa isolation may be performed using inductively coupled plasma (ICP) RIE, At this point in the process flow, ohmic via openings may optionally be formed through the passivation layer, followed by ohmic metallization and annealing (block406). An example ohmic contact metal is TiAlMoAu. The metal ohmic contacts may be annealed utilizing a RTA tool at a temperature range of approximately 600-900 ° C. for about one minute.

Next, the second gate dielectric layer which may be comprised of Al2O3may be optionally deposited on the passivation layer (block408). The second gate dielectric layer may also be deposited over the source and drain ohmic contacts. In one embodiment, the second gate dielectric layer is deposited on the wafer surface using ALD at 300° C. The second gate dielectric layer may be grown to a thickness in a range of approximately 10-20 nm.

In one embodiment, the deposition of the second gate dielectric layer may be performed ex-situ from the first and second active layers and the passivation / first gate dielectric layer. For example, both the passivation/first and second gate dielectric layers may be deposited on the wafer surface using the same ALD chamber or other machine or system.

A high temperature anneal may be performed after the second gate dielectric layer has been deposited (block410) to improve the film and interface quality of the second gate dielectric layer. By way of example, the annealing step may be performed in a furnace at temperature range of 450-750° C. for approximately 5-10 minutes. Annealing may also be performed using a number of different tools, such as a rapid temperature annealing (RTA) tool. It should be appreciated that block408and block410are considered optional, as the blocks apply to the HFET devices shown inFIGS. 2 and 3, which illustrate a second gate dielectric layer.

After annealing, an upper passivation layer may be optionally deposited over the second gate dielectric layer (block412). In one embodiment, the upper passivation layer may be deposited using PECVD. The upper passivation layer may also be deposited using LPCVD. The upper passivation layer is typically formed to a thickness in a range of approximately 100-150 nm. As discussed above, the upper passivation layer may comprise silicon nitride (SiN) or other materials having similar properties.

Gate via formation is shown in block314. This step is optionally performed when an upper passivation layer has been formed over the stack of multiple gate dielectric layers. Gate via formation comprises masking and etching the upper passivation layer such that an opening is formed through the upper passivation layer, thereby exposing the underlying second gate dielectric layer. In one embodiment, dry etching may be utilized with a gas such as CF4or SF6to etch through the upper passivation layer. After the etching process exposes the second gate dielectric layer, a gate metal or metal alloy deposition (block316) is performed to fill the etched opening. In one example, NiAu is used as the gate metal. As shown inFIGS. 1,2, and3, a field plate portion of the gate may be formed by masking or etching the gate metal such that a top portion laterally extends over the upper passivation layer towards the farthest (drain) ohmic contact. It should be appreciated that blocks412and414are considered optional, as the blacks apply to the HFET device300shown inFIG. 3, which illustrates an upper passivation layer.

Persons of ordinary skill in the semiconductor arts will understand that other standard post-fabrication or back-end processing steps may be performed, including forming metal (e.g., patterned lines or traces) on the surface of the wafer, wafer backgrinding (also called backlapping or wafer thinning), die separation, and packaging.

FIG. 5is a diagram illustrating another example process flow400for constructing a HFET device such as semiconductor device200or300shown inFIGS. 2 and 3. The process shown inFIG. 5is the same as that discussed in connection withFIG. 4, with like numbered steps being the same as described above, except that process flow500includes additional block503interposed between block502and block504. After the in-situ grown of the AlSiN passivation/first gate dielectric layer, aluminum nitride (AlN) is grown on top of the AlSiN layer (block503). In one embodiment, the AlN layer is grown in-situ with the AlSiN passivation/first gate dielectric layer and first and second active layers. The thickness of the AlN layer may be about 1 nm thick. After mesa isolation etching and ohmic metallization and annealing in blocks504and506, the AlN layer is effectively utilized as a seed layer to form the Al2O3second gate dielectric layer (block508).

The above description of illustrated example embodiments, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments and examples of the subject matter described herein are for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example thicknesses, material types, temperatures, voltages, times, etc., are provided far explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.