Node controller for a data storage system

A node controller for a data storage system having at least one node provides access to a data storage facility. The node controller is distinct from a computer-memory complex of the node. The node controller provides overall control for transferring data through the node.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to the field of data storage and, more particularly, to a node controller for a data storage system.

BACKGROUND OF THE INVENTION

In the context of computer systems, enterprise storage architectures provide mass electronic storage of large amounts of data and information. Many enterprise architectures incorporate disk storage systems to provide relatively inexpensive, non-volatile storage. Disk storage systems, however, may suffer from numerous problems. These problems include the following. Disk systems are prone to failure due to their mechanical nature and the inherent wear-and-tear associated with operation. Accesses (i.e., reads and writes) into disk systems are relatively slow, again due to their mechanical nature. Furthermore, disk storage systems have relatively low bandwidth for data transfer because the effective bandwidth is limited by “platter speed” (i.e., the rate at which data bits move under a disk head).

Various techniques have previously been developed to reduce the problems associated with disk storage systems. One such technique, referred to as “RAID” (Redundant Array of Inexpensive Disks), employs multiple disk drives. With RAID, one or more of the disk drives can store redundant data (e.g., parity information or a duplicate copy of the data itself) so that if another disk drive fails, the redundant data can be used to reconstruct the data.

The RAID technique, however, taxes the resources of a data storage system and the computer system for controlling the same. For example, RAID requires high-speed data cache, high bandwidth communication between data cache and other elements for the replication of data, mirroring of data for protected write caching, and high system bandwidth to host devices and disk drives.

Furthermore, with previously developed storage systems in general, a redundant pair of buses is used to connect all of the individual functional units, such as, host interfaces, disk interfaces, data cache, and communication channels. This approach not only limits the scalability of the systems, but also causes the shared interconnect to become a bottleneck to performance.

SUMMARY OF THE INVENTION

The disadvantages and problems associated with previously developed storage systems and techniques have been substantially reduced or eliminated using the present invention.

According to an embodiment of the present invention, a node controller for a data storage system having at least one node provides access to a data storage facility. The node controller is distinct from a computer-memory complex of the node. The node controller provides overall control for transferring data through the node.

According to another embodiment of the present invention, a node controller provides overall control for transferring data through a node of a data storage system. The node controller is distinct from a computer-memory complex of the node. The node controller includes a logic engine operable to perform a logic operation on data from at least one data source in the data storage system. A command queue is coupled to the logic engine. The command queue is operable to store a logic control block which can be processed by the logic engine.

A technical advantage of the present invention includes providing a node controller which can be integrated at a node of a data storage system and architecture. The node controller is separate from the computer-memory complex. The node controller, using cluster memory at the node, controls or coordinates transfers of data through the node. Accordingly, the computer-memory complex at the node is not burdened with such task. Thus, by reducing the workload and responsibilities of the computer-memory complex, the node controller facilitates and optimizes the overall operation of the data storage system and architecture.

The node controller can be implemented as an application specific integrated circuit (ASIC) on a system board for the node. The node controller may support a number of interconnect links that are connected via a backplane connector to other system boards. The node controller may control accesses (i.e., reads or writes) into one or more banks of cluster memory located at the node.

Other aspects and advantages of the present invention will become apparent from the following descriptions and accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments for the present invention and their advantages are best understood by referring toFIGS. 1-7the drawings. Like numerals are used for like and corresponding parts of the various drawings.

Environment for a Node Controller

FIG. 1is a block diagram of a node10within which a node controller12, according to an embodiment of the present invention, may operate. Node10generally functions as a point of interface/access between one or more host devices and storage devices. These host devices can include various processing devices, such as, for example, a server cluster, a personal computer, a mainframe, and a server tower. Host devices may also include various peripheral devices, such as, for example, a printer, a modem, and a router. Storage devices can be implemented with any suitable mass storage resource, such as tape or disk storage. A data storage system within which node10can be incorporated is described in U.S. patent application Ser. No. 09/633,088 filed Aug. 4, 2000, entitled “Data Storage System,” which is assigned to the present Assignee and incorporated by reference herein.

For interface/access, node10may include one or more peripheral component interconnect (PCI) slots, each of which supports one or more respective connections14. As used herein, the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements; such connection or coupling can be physical or logical. For clarity, only one connection14is labeled inFIG. 1. Each connection14can connect a host device or a storage device. Connections14can be small computer system interface (SCSI), fibre channel (FC), fibre channel arbitrated loop (FCAL), Ethernet, Infiniband, or any other suitable connection.

Node10may also interact with other nodes to implement a scalable architecture particularly well suited for communication-intensive, highly available data storage, processing, or routing. Such a data storage system is described in detail in U.S. application Ser. No. 09/633,088, which is incorporated by reference herein in its entirety. Node10supports a number of communication paths16, which enable communication with other nodes. A separate communication path16may be provided for each node with which node10communicates. Each communication path16may be implemented as a high-speed, bi-directional link having high bandwidth to provide rapid transfer of data and information between node10and another node. In one embodiment, the links can be two-bytes wide and operate at 266 MHz in each direction, for a total bandwidth of 1,064 MB/s per link. Communication paths16provide a low latency communication channel between nodes without the protocol overhead of transmission control protocol/internet protocol (TCP/IP) or Fibre Channel protocol. Control of data/information transfers over communication paths16is shared among the nodes. In one embodiment, transfers of data/information over communication paths16are covered by an error-correcting code (ECC) that can cover a single bit error in any 64-bit word and can detect any line error on the communication paths16.

As depicted, node10may include a computer-memory complex18. Computer-memory complex18can be a computer system which includes one or more central processing units (CPUs) and associated memory, each CPU-memory combination running an independent copy of an operating system. Computer-memory complex18functions to support, control, or otherwise manage one or more suitable buses through which data and information can be transferred via connections14. In one embodiment, each such bus can be a peripheral component interconnect (PCI) bus. Computer-memory complex18may also support other functions, such as, for example, a hypertext transport protocol (HTTP) service, a network file system (NFS) service, and a common Internet file system (CIFS) service.

In one embodiment, node10can be implemented as a system board on which are provided suitable central processing unit (CPU) devices, memory devices, and application specific integrated circuit (ASIC) devices for providing the functionality described herein. This system board can be connected on a backplane connector which supports communication paths16. Such an embodiment is shown and described below with reference toFIG. 2.

Node controller12resides on node10along with a cluster memory20. Node controller12and cluster memory20are distinct and separate from computer-memory complex18. In one embodiment, node controller12can be implemented as an application specific integrated circuit (ASIC) device. Node controller12may cooperate with computer-memory complex18but, to some degree, operates independently of the same. That is, computer-memory complex18may program node controller12. Node controller12, as programmed, can then operate independently on data, thereby providing overall control for the transfer of data through node10. Accordingly, computer-memory complex18is not burdened with the task of performing actual operations on the data. Cluster memory20is coupled to node controller12and, as described herein, generally functions to cache data and information being transferred through node10. Cluster memory20can be implemented as any suitable cache memory, for example, synchronous dynamic random access memory (SDRAM).

With node controller12(cooperating with cluster memory20), data/information being transferred through node10(including bulk transfers) does not have to be temporarily stored in computer-memory complex18. This ability to let bulk data transfer bypass the general purpose computer-memory complex18is advantageous. It enables the transfer of data/information at tremendous bandwidth. Furthermore, because the computer-memory complex18complex is less loaded, it is more available to provide or support other functions, such as, for example, a HTTP service, a NFS service, and a CIFS service. Thus, by reducing the workload and responsibilities of computer-memory complex18, node controller12facilitates and optimizes the transfer of data and information through node10.

Exemplifying Implementation for a Node

FIG. 2illustrates an exemplifying implementation for a node10, according to an embodiment of the present invention. Within this implementation, computer-memory complex18and node controller12may be implemented with one or more integrated circuit (IC) devices mounted on a suitable system board connected to other nodes via a backplane connector.

In general, computer-memory complex18can be implemented using a multi-processor capable chipset. As shown, the chipset can include a main controller24, an input/output (I/O) bridge26, and a PCI/Legacy bridge28. In one embodiment, main controller24, I/O bridge26, and PCI/Legacy bridge28can be implemented with a “Champ North Bridge,” a “Champion Input/Output (I/O) Bridge (CIOB),” and a “South Bridge,” respectively, all commercially available from ServerWorks. Other chipsets can also be used.

One or more central processing units (CPUs)30, which are separately labeled30aand30b, generally provide processing capability for the control of data transfers through node10. Each CPU30can be implemented with any suitable processing device, such as, for example, a PENTIUM III by Intel Corporation.

One or more slots32connect main controller24to system memory. For clarity, only one slot32is labeled. Each slot32may hold a suitable memory device for implementing system memory. System memory can be implemented, for example, with synchronous dynamic random access memory (SDRAM). System memory generally functions to store data and information used in controlling transfers for node10. System memory is not required to cache data for bulk transfers through node10as this function can be performed by cluster memory at the node.

A local drive34is connected to PCI/Legacy bridge28. Drive34can be used to boot the local operating system for computer-memory complex18and to back up local data from system memory in the event of a power failure.

Two peripheral component interconnect (PCI) buses36are supported by computer-memory complex18. These PCI buses, which are separately labeled36aand36b, can each be a 66 MHz, 64-bit bus. A number of PCI bridges38are provided for each bus. As depicted, PCI bridges38aand38bare provided for PCI bus36a, and PCI bridges38cand38dare provided for PCI bus36b. PCI buses36and the respective PCI bridges38support one or more PCI slots to which a host device or a storage device can be connected. In this embodiment, each PCI bus36supports one 66 MHz, 64-bit PCI slot40(separately labeled40aand40b) and two 66 MHz, 64-bit PCI slots42(separately labeled42a,42b,42c, and42d). Collectively, PCI buses36, PCI bridges38, and PCI slots40and42support or provide an implementation for connections14described with reference toFIG. 1.

Node controller12resides on both PCI buses36, and thus may transfer data/information to and from host devices and storage devices directly (i.e., without routing through computer-memory complex18). Node controller12can be implemented as an application specific integrated circuit (ASIC). One or more slots44connect node controller12to cluster memory. Although eight slots44are shown, for clarity only two of these slots44are labeled inFIG. 2. Each slot44can hold a suitable memory device for implementing cluster memory.

Cluster memory may be implemented in banks which, as depicted, are separately labeled “Cluster Memory Bank 1” and “Cluster Memory Bank 0.” In one embodiment, each bank may comprise a number of dual in-line memory modules (DIMMs), each DIMM being held in a separate slot44. Each DIMM can be a synchronous dynamic random access memory (SDRAM) of up to 1 GByte capacity. Thus, the total capacity for both banks of cluster memory in node10can be eight GBytes.

The memory banks can be accessed with long bursts so that the sustainable bandwidth is close to the peak bandwidth. In one embodiment, each bank of cluster memory is eight bytes wide and operates at 133 MHz, thus resulting in a peak bandwidth of 1064 MBytes/s. The aggregate bandwidth of the two banks is approximately two GBytes/s.

Unlike the system memory in a general-purpose computer-memory complex, cluster memory is not bottlenecked by the limitations or constraints of a system bus (e.g., PENTIUM bus). Rather, because data is carried in and out of cluster memory by two PCI buses, transfer bandwidth can be approximately the full aggregate bandwidth of these two PCI buses. Since each 66 MHz, 64-bit PCI bus is capable of transferring 500 Mbytes/s, the two PCI buses alone can contribute about 1 GByte/s of cluster memory bandwidth, which exceeds the achievable bandwidth on a system bus.

Node Controller

FIG. 3illustrates an exemplifying implementation for a node controller12, according to an embodiment of the present invention. In this implementation, node controller12includes one or more PCI control interfaces50, which are separately labeled50aand50b. Each PCI control interface50provides an interface with a respective PCI bus (“PCI 0” or “PCI 1”). Each such bus can be a 64-bit, 66 MHz bus. PCI control interfaces50allow node controller12to appear as a PCI device on each bus. Configuration software in the respective computer-memory complex18may view node controller12as separate and independent devices on the two PCI buses.

Control and status registers (CSRs)52are connected to each PCI control interface50. Control and status registers52generally function to maintain or keep track of various information used in node controller12, or control information to be sent over communication paths16to another node10. Thus, for example, control and status registers52may maintain the current values for flags or other control signals used in node controller12. These may include interrupt, mask, and command signals. Also, control and status registers52may maintain base addresses for data. Other parts of node controller12, as well as external PCI devices, may read or write into control and status registers52.

Node controller12may act as a slave device (target), thus allowing other devices on each PCI bus (e.g., host devices or the CPUs of computer-memory complex18) to read from or write to cluster memory20. PCI devices may also read or write into the control and status registers52.

A memory controller54generally functions to provide or support an interface for the cluster memory20of respective node10and/or a remote node. In one embodiment, a separate memory controller54is provided to support each of two 72-bit, 133 MHz SDRAM channels (0 and 1) for the local cluster memory20and communication paths16extending out to the cluster memories of other nodes.

As depicted, each communication path16may comprise two separate interconnect links. For each such pair of links, one link carries data/information out of node controller12to the respective node10, and the other link carries data/information from the same node10into node controller12(particularly, memory controller54). In one embodiment, the links are eighteen bits wide and run nominally at 133 MHz. If data is sampled on both edges of a clock, the data rate is 532 MB/s for each link.

Cluster memory20may be programmed or divided into multiple regions. Each region may be, for example, a line of sixty-four bytes, and can be associated with a remote node10. Node controller12may be configured so that the writing of data into a particular region of cluster memory20causes the same data to be sent to the associated remote node via the respective interconnect link. Accordingly, the data is “mirrored” at the cluster memory of the remote node. Node controller12may also be configured so that the writing of data to other regions causes the same data to be “broadcast”—i.e., the data is sent over every outgoing interconnect link to the respective remote nodes.

One or more logic engines56are coupled to PCI control interfaces50, memory controller54, and the outgoing interconnect links of communication paths16. In one embodiment, logic engines56comprise “exclusive OR” (XOR) engines. Logic engines56may also include error-correcting code (ECC) scrub, Direct Memory Access (DMA) engines, Bzero engines, and/or parity engines. Logic engines56in node controller12can operate (e.g., perform an XOR operation) on data from up to thirteen sources (in local cluster memory20or PCI buses36) and write the result into a destination (in either local cluster memory20, one of the two PCI buses36, or one of communication paths16). The sources, destination, length, and operation type and flags are programmed in one or more logic control blocks (LCBs) stored in respective command queues58. In one embodiment, each logic control block can be an XOR control block (XCB). Each logic control block can specify or relate to one or more commands for actions to be taken at or by node controller12. Logic engines56take “jobs” off the head or consumer end of the queues (as described below). In one embodiment, there are multiple logic engines56in node controller12. While one logic engine56is operating on a logic control block from a queue, the other logic engines56will only operate on logic control blocks from other queues. Thus, only one logic control block from any given queue may be active at a time.

Logic engines56provide or support a number of different functions in node controller12. For example, logic engines56may support a redundant array of inexpensive disks (RAID) configuration. Specifically, logic engines56may compute RAID parity when initializing a RAID volume or writing a full RAID strip, reconstruct data when one disk in a RAID group is bad, and compute new RAID parity from old parity read from disk and partial parity received over the interconnect link from another node. Logic engines56may perform other types of operations, such as, for example, checksums. Checksums are codes that can be used to ensure that data is valid.

In one embodiment, logic engines56can read multiple regions of local cluster memory20, perform a particular logic operation (e.g., an “exclusive OR” operation) on all of the regions, and write the result back to another region of local cluster memory20. This is used to accelerate the writing of a full RAID strip and to speed up reconstruction of data after disk failure in a RAID group. A separate logic engine56may provided for each interconnect link. Each such logic engine56can perform a logic operation on multiple regions of local cluster memory20and place the result into the cluster memory at a remote node. This is used in writing of a RAID partial strip to compute the new parity. Each link logic engine56can also be used to copy a region of local cluster memory20into a remote node's cluster memory.

Command queues58are connected to logic engines56. Queues58store the logic control blocks which can be processed by logic engines56. Each logic control block may specify a number of sources upon which a logic operation can be performed, and the result sent to a particular destination. Each source can be a region of cluster memory20or one of PCI buses36. The destination can be one of the outgoing interconnect links (e.g., communication paths16), a PCI bus36, or a region of cluster memory20. A separate command queue58may be provided for each destination.

With the functionality described herein, node controller12accelerates the storage of data/information and communication through node10, thereby enhancing performance and availability. Furthermore, because memory control, links, PCI control, and logic engines may be integrated on a single integrated circuit device (e.g., application specific integrated circuit (ASIC)) in at least one embodiment, such implementation for node controller12substantially reduces or eliminates the need to transfer data between components over system resources, thereby consuming less system resources and greatly enhancing performance.

For example, in an embodiment in which node controller12is implemented as part of a system board for a node10, the node controller may communicate and cooperate with node controllers on other system boards to transfer data/information therebetween, for example, in bulk transfers. These node controllers12can interact to perform peer-to-peer transfers-i.e., transfers between two PCI devices other than the main computer system comprising CPUs and system memory (i.e., computer-memory complex18in each node12). This is advantageous for a number of reasons. Because the node controllers12primarily handle the peer-to-peer transfers, the main computer systems in each system board are made more available for other functions. At the same time, “normal” PCI bus transfers to the main computer systems can be used for control information without requiring separate buses. Furthermore, bulk transfers of data avoid the limitations of a typical main computer system, such as, for example, relatively narrow bandwidth on system buses and limited capacity system memory. Because bulk data transfers are carried out using the large capacity, relatively wide cluster memory and over high-speed links, transfers between nodes can be very fast. Since cluster memory20is separately provided for each node controller10, no additional transfer is required to transport data to another node controller at a different node. These optimize the efficiency and performance of a data storage system incorporating such node controllers12.

Node Controller Address Space

FIG. 4illustrates an exemplifying address space60for node controller12, according to an embodiment of the present invention. In general, within node10, node controller12appears as a PCI device on each of two PCI buses36a,36b(seeFIG. 2), which may be referred to as “PCI 0” and “PCI 1.” PCI device configuration software treats node controller12as a separate and independent device on each bus36(each with its own PCI configuration header) and allocates space for node controller12on both buses. Since the addresses on the two PCI buses36a,36bare different, address space60provides separate PCI base address registers in control and status registers (CSRs)52and cluster memory20for each bus. Nevertheless, the two PCI buses36a,36bmay physically share many of the other PCI configuration header registers.

Referring toFIG. 4, regions in both control and status registers52and cluster memory20can be mapped on PCI for node controller12. As shown, control and status registers52provide a 1 KB region which may be mapped as non-prefetchable memory. Cluster memory20provides 0.5 GB region which may be mapped as prefetchable memory. In one embodiment, the base address register of cluster memory20specifies sufficient space for all of the local cluster memory, which could be more than 4 GB. Since this requires 64-bit PCI addressing, the base address register can be a 64-bit base address register. However, because there may be system hardware and software restrictions that limit the available address space, address space60provides two cluster memory base address registers: a small cluster memory base address register and a large cluster memory base address register. The small cluster memory base address register may map only the top 0.5 GB of cluster memory20, whereas the large cluster memory base address register may map all of cluster memory20(up to 8 GB). As shown, the same cluster memory20is mapped to both PCI buses. An exemplifying configuration for the node controller address space is outlined below in Tables 1-4.

TABLE 2CSR Base Address RegisterResetFieldBitsModeStateDescriptionBase31:10RW0Base address [31:10] programmable toAddressset base address of node controllerCSRs.Base9:4R0Hardwired to 0, indicates that 1 KB ofAddressspace is required for node controllerCSRs.Prefetch-3R0Indicates that CSRs are notableprefetchable.Type2:1R00Indicates that the CSR Base AddressRegister is a 32-bit register and can bemapped anywhere in the 32-bit memoryspace.Space0R0Indicates that this is a memory space.

TABLE 3Small Cluster Memory Base Address RegisterResetFieldBitsModeStateDescriptionBase31:29RW0Base address [31:29] programmable toAddressset base address of Small ClusterMemory SpaceBase28:4R0Hardwired to 0, indicates that 512 MBAddressof space is required for the SmallCluster Memory Space.Prefetch-3R1Indicates that Cluster Memory space isableprefetchable.Type2:1R00Indicates that the Small Cluster MemoryBase Address Register is a 32-bitregister and can be mapped anywhere inthe 32-bit memory space.Space0R0Indicates that this is a memory space.

TABLE 4Large Cluster Memory Base Address RegisterResetFieldBitsModeStateDescriptionBase63:33RW0Base address [63:33] programmable toAddressset base address of Large ClusterMemory SpaceBase32:4R0Hardwired to 0, indicates that 8 GB ofAddressspace is required for the Small ClusterMemory Space.Prefetch-3R1Indicates that Cluster Memory space isableprefetchable.Type2:1R10Indicates that the Large Cluster MemoryBase Address Register is a 64-bitregister and can be mapped anywhere inthe 64-bit address space.Space0R0Indicates that this is a memory space.
Command Queues

FIG. 5illustrates exemplifying command queues58, according to an embodiment of the present invention. Command queues58store a number of command or logic control blocks (LCBs) which can be processed by logic engines56. As such, command queues58can also be referred to as LCB queues. Each logic control block may specify a number of sources upon which a logic operation can be performed, and the result sent to a particular destination. Each source can be a region of cluster memory20or one of PCI buses36. The destination can be one of the outgoing interconnect links (e.g., communication paths16), a PCI bus, or a region of cluster memory20.

A separate command queue58may be provided for each destination. As shown, these queues58include command queues58aand58bfor first and second PCI buses (PCI 0, PCI 1); command queues58c,58d,58e,58f,58g,58h, and58ifor a number of communication path node links (Node Link 0, Node Link 1, Node Link 2, Node Link 3, Node Link 4, Node Link 5, and Node Link 6); and command queue58jfor a cluster memory connection.

In one embodiment, as shown inFIG. 6, each command or LCB queue58may be implemented as a separate buffer61. Each buffer61may operate as a circular queue that wraps around from the end to the beginning of the buffer61. A plurality of logic control blocks (LCBS) may be stored into each buffer61.

Furthermore, as depicted inFIG. 6, an LCB producer register62and an LCB consumer register64may be associated with each command queue58. The LCB producer register62and the LCB consumer register64can be control and status registers52(FIG. 3). The LCB producer register62specifies a particular address of the command queue58into which the next logic control block should be written. The LCB consumer register64specifies a particular address of the command queue58from which the next or current logic control block should be read in order to operate on the same. In one embodiment, software at node controller12writes to the producer end of the command queue (indicated by the LCB producer register62). Hardware at node controller12takes logic control blocks off the consumer end of the queue (indicated by the LCB consumer register64) so that they may be operated on by logic engines56.

If the addresses specified by LCB consumer register64and LCB producer register62are the same, the command queue58is empty and the logic engines56skip that queue. When software increments the LCB producer register62for a queue58, the next logic engine56that services such queue58reads the next logic control block and starts executing its task. In one embodiment, software may only write to the LCB producer registers62; the LCB consumer registers64cannot be directly written to by software since hardware writes to them as tasks are completed.

An exemplifying configuration or arrangement for an logic control block is outlined below in Table 5.

With respect to the configuration given in Table 5, the destination address (DEST_ADDR) can be in local cluster memory20, on one of the two PCI buses36a,36b, or on one of the links (e.g., communication paths16). The source addresses (SRCO_ADDR through SRCD-ADDR) can be in local cluster memory20or one of the two PCI buses36a,36b. Preferably, the destination address is implicit in the queue, but each source address must specify whether it is in local cluster memory20or the PCI buses36.

The cluster memory20of a particular node10can be written to by the logic engines56of a remote node. Link memory protection is used to limit the local memory locations that can be written via a link by the logic engines of the remote node. That is, each link is provided with a specific range of local cluster memory20which it can access. To accomplish this, for each link, node controller12may comprise a base and bounds register pair which specifies the memory range. The base and bounds register pair comprises a link protection base register and a link protection bounds register, which can be control and status registers52(FIG. 3). The link protection base register holds or contains information for a base address in local cluster memory20. The link protection bounds register holds or contains information for a bounds address in local cluster memory20. The respective link is allowed to write to any address starting from and including the base address up to (but not including) the bounds address.

In one embodiment, when a logic engine56encounters an error while operating on particular logic control block of a command queue58, that queue58is suspended and a corresponding bit for the specific error is set in a control and status register52for logic engine56. The errors encountered may include, for example, programming errors for a specific destination (e.g., links, PCI buses, or cluster memory). The command queue58can be restarted by clearing the bit; the logic control block associated with that the error, however, is not restarted.

Memory Banks

FIG. 7illustrates a number of memory banks under the control of a node controller12, according to an embodiment of the present invention. These memory banks can be contained in a number of Dual In-line Memory Modules (DIMMs)70, which are separately labeled DIMM0, DIMM1, DIMM2, DIMM3, DIMM4, DIMM5,  DIMM6, and DIMM7. As depicted, DIMM0contains bank0and bank2, DIMM1contains bank1and bank3, DIMM2contains bank4and bank6, DIMM3contains bank5and bank7, DIMM4contains bank8and bank10, DIMM5contains bank9and bank11, DIMM6contains bank12and bank14, and DIMM7contains bank13and bank14. Each DIMM70in general can have one or two physical banks. In one embodiment, each DIMM70may include a number of Synchronous DRAMs (SDRAMs). The number and width of the DRAMs may determine the physical memory banks.

Node controller12may have two memory controllers54(seeFIG. 3), each of which may support a separate data path (cntr10 and cntr11) to DIMMS70. In one embodiment, each memory controller54may support a 72-bit wide (64-bit data and 8-bit ECC) data path to four 72-bit DIMMs70. All memory operations may performed in units of 64-byte lines. An entire line of memory may be accessed in a single burst of length 8-cycles from a single memory bank on one DIMM70. DIMMs70may be installed as pairs of identical DIMMs, one for each controller54. The memory can be interleaved two-ways on 64-byte line boundaries across the memory controllers54. One memory controller54may control even-numbered memory banks on even-numbered DIMMs70, and the other memory controller54may control odd-numbered memory banks on odd-numbered DIMMs70. Each memory bank can be selected by the associated memory controller54with a respective chip select line CS[15:0], where CS[x] is associated with memory bank x.

Memory decoding registers may be provided for maintaining data regarding the chip select lines. One address bit can be used to select between the even-numbered memory banks and the odd-numbered memory banks. Each pair of identical memory banks may be referred to as a segment. The memory decoding registers determine the range of addresses that activate a given segment of memory. In one embodiment, the top of each segment is specified by a respective 32-bit memory decoding register that specifies the first address of the next segment, or equivalently, the cumulative total memory (in units of 128 MB) in the memory bank plus all the lower numbered segments. An exemplifying address block for memory segments is illustrated in Table 6 below.

In one embodiment, a memory control register is provided for each per pair of identical DIMMs70. The memory control register can be a control and status register52(seeFIG. 3). Each memory control register controls the row address strobe (RAS), column address strobe (CAS), and bank address generation, and memory timing. An exemplifying illustration for memory control register is provided in Table 7 below.

A single memory mode register may be provided for both memory controllers54. The memory mode register, which may be a control and status register52(FIG. 3), can be used to accelerate programming of the SDRAMS. The SDRAMs are programmed one physical memory bank at a time with the address used to select the bank. An exemplifying illustration for memory mode register is provided in Table 8 below.

TABLE 8Memory Mode RegisterResetFieldBitsModeStateDescriptionResvd31:4R0ReservedPGMODE3RW0Page mode access for all banks.0 => Always close the banksafter each access.1 => Keep banks open if possibleto take advantage of sequentialaccesses to the same page.MCTLMODE2:0RW0x0Selects the mode for the DRAMoperation.0 => Normal DRAM operation1 => NOP Commands are issuedinstead of the normal DRAMaccess.2 => All banks prechargecommands are issued instead of thenormal DRAM access.3 => CBR (auto refresh) com-mands are issued instead of thenormal DRAM access.4 => Mode Register Set commandis issued instead of the normalDRAM access.5-7 => Reserved (treated asnormal DRAM operation).

Accordingly, an embodiment of the present invention provides a node controller which can be integrated at a node of a data storage system and architecture. The node controller is separate from any computer-memory complex at the node. The node controller, using cluster memory at the node, controls or coordinates transfers of data through the node. Accordingly, the computer-memory complex at the node is not burdened with such task. Thus, by reducing the workload and responsibilities of computer-memory complex, the node controller facilitates and optimizes the overall operation of the data storage system and architecture.

Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes or modifications may be made without departing from the present invention in its broader aspects, and therefore, the appended claims are to encompass within their scope all such changes and modifications that fall within the true scope of the present invention.