Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses

Two-wire bus system comprises a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses. A communication bus system has a single clock wire and a single data wire. Each wire has wired logic that upon presentation of any prevalence logic signal value imparts to that wire the prevalence logic value regardless of any non-prevalence value second presented thereto. The system has clock synchronization by a master station of any information transmission. The system arbitrates among coexistent prospective masters to select a single actual master. The protocol has a start condition by presenting said first value to the data wire with the clock line at the second value, and generates any subsequent data wire transition exclusively under existence of the prevalence value on the clock wire. The subsequent stop condition is represented by a transition to the second value on the data wire with the clock wire at the second value. The message format has an initial byte accommodating either a short slave address, or alternatively both a control signal indicating a long-format slave address inclusive of a high significance address part, to be followed in the next byte by a low significance part of the address. For enhancing the bit rate, the system has a switched pull up device, whereas furthermore each station has a slope controlled output stage.

FIELD OF THE INVENTION 
The invention relates to a two-wire bus communication system that allows 
for an extremely straightforward protocol between stations which stations 
are usually respective integrated circuits, and suitable in particular for 
use within a consumer electronics device such as for audio-video 
entertainment and personal communication, although such proposed use 
should not be construed as an express limitation. Present-day electronics 
has realized various bus protocols and environments for application in 
numerous commercial fields. 
BACKGROUND TO THE INVENTION 
Principal state of the art is the so-called I.sup.2 C bus that has been 
patented in U.S. Pat. No. 4,689,740 assigned to the present assignee. With 
a seven bit address space the reference allows to explicitly address some 
one hundred-odd stations, without requiring that the addressing master 
have any knowledge about the physical position of the addressee. Due to 
the various different types of stations, with respect to their internal 
functionality, and also due to the various different manufacturers that 
have entered this fast-growing market, the present inventor has 
experienced a growing dearth of available addresses to such an extent that 
necessity repeatedly has caused assigning of a particular address to 
various types of stations. 
SUMMARY OF THE INVENTION 
Accordingly, amongst other things it is an object of the present invention 
to greatly increase the number of available addresses, while keeping 
inside the already specified I.sup.2 C protocol already specified, and 
also while keeping the necessary message length quite restricted. As a 
related object to the above, which effectively boils down to expanding a 
spatial parameter such as the address space to a greater value, it was 
felt necessary to enhance the attainable bit rate or in other words a 
temporal parameter. Now, according to one of the aspects of the invention, 
the object is realized in part by a communication bus system, comprising a 
plurality of stations interconnected by a single clock wire and a single 
dam wire. Each wire being provided with wired logic functionality means 
for upon presentation thereto of at least one prevalence logic signal 
value, from any station imparting to the wire in question the prevalence 
first logic value regardless of any non-prevalence second value presented 
thereto, the system being arranged for under clock synchronization by a 
master station transmitting information from a source station to a 
destination station. The system having arbitration means for upon 
coexistent manifestation of more than one prospective master station 
through bitwise arbitration selecting an actual master station 
thereamongst, the system in a master station having protocol means for 
generating a start condition by presenting said first value to the data 
wire with the clock wire at the second value, for generating any 
subsequent data wire transition exclusively under existence of said first 
value on said clock line, and for generating a subsequent stop condition 
by a transition to said second value on said data wire line with said 
clock wire at said second value, and in such master station having message 
formatting means for producing a bytewise acknowledgeable message 
constitution, an initial byte accommodating a short slave address, 
characterized in that such formatting means are arranged for in said 
initial byte signalling both a forthcoming long-format slave address 
inclusive of a high significance address part thereof, and in a 
next-following byte a low significance address part thereof. This means 
that the address length of the newly added space is greater than one byte, 
in particular 10 bits, which appears sufficient for a long time to come: 
the number of allowable addresses has been enhanced by a factor of about 
ten. The addition of only the addresses that would fit in a single byte 
(256 addresses) was expected to produce the same problems encountered at 
present again within short time. On the other hand the message length is 
only increased by a single byte. If only the extra byte itself were used, 
256 addresses could have been added; if then the added address space 
should have been greater, a further byte would have to be added. 
Advantageously, the system has switched pull up means for under control of 
an incipient upgoing signal edge on any said wire transiently lowering a 
pull up resistance value of said pull up resistance means with respect to 
an otherwise steady state pull up resistance value. In particular, this 
device would be needed only once for each wire in a system for so 
providing a kind of feed-forward to increase the pulling up speed of the 
associated wire. 
The invention also relates to a master station and to a slave station for 
use with such communication bus system and having the extended 
addressability feature. Advantageously, such station would comprise a 
slope-controlled output stage connected to one of said wires, said stage 
having pull down switch means drivable by a stage input signal for then 
downpulling a stage output and having low-pass filtering means for during 
said downpulling partially attenuating a control signal to said pull down 
switch means, whereby an output slope of said stage is expanded. In 
particular, this would at such increased bit rate provide EMC (Electro 
Magnetic Compatibility) adherence. 
Further advantageous aspects are recited in dependent claims. 
In consequence, a "ten-bit addressing" feature can be added to an I.sup.2 C 
bus system, without conflicting with the original; bus protocol and 
without conflicting with the normal operation of existing seven-bit 
address devices in the same system. Further, seven-bit addressing and 
ten-bit addressing can be used simultaneously in a single system, while 
maintaining existing principles for arbitrating and synchronizing between 
respective prospective master stations. Effectively, a seven-bit address 
gets preference over a ten-bit address. A ten-bit addressing format for a 
"data transmit" operation needs one extra byte over a seven-bit addressing 
"data transmit" format. A ten-bit addressing format for a "data receive" 
operation needs one extra byte over a seven-bit addressing "data receive" 
format, because after a repeated start condition only the most significant 
address part is required. A ten-bit addressing format for a combined "data 
transmit" and "data receive" operation needs one extra byte over a 
combined seven-bit addressing "data transmit" and "data receive" format, 
because after a repeated start condition only the most significant address 
part is required. Finally, slave addresses 11111XX remain reserved for 
future extensions. 
STATEMENT OF ADDITIONAL PUBLICATION 
The present invention has to an appreciable part been published in the 
document "The I.sup.2 C bus and how to use it" (including specifications) 
by Philips Semiconductors, Eindhoven, The Netherlands, of January, 1992, 
No. 939839340011, which has been received at the premises of assignee on 
Jan. 27, 1992, and in consequence, has not been distributed to the Public 
before Jan. 31, 1992, which is less than one year before the filing date 
of the present application for patent. This document added various aspects 
to the earlier existing I.sup.2 C system, while stating explicitly that 
Neither the 100 kbits/s nor the 100 kbits/s devices have been changed. 
This means that all aspects of the earlier bus protocol remain in force. 
Notably, 7-bit and 10-bit addresses may be used on a single system. The 
only limitation is that slow (100 kbits/sec) stations may not be used in a 
fast (400 kbits/sec) system.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
Herein various embodiments according to the invention are described. FIG. 1 
is an elementary block diagram of an I.sup.2 C system with serial data 
wire SDA, serial clock wire SCL, and three stations 20, 22, 24. Generally, 
with respect to the bus interface each station is executed as a single 
integrated circuit, but this is not an express restriction. For brevity, 
the wired logic functionality and the register structure of the stations 
is not discussed extensively, as these have been already described long 
ago in the first reference. 
FIGS. 2A and 2B show a complete data transfer. The start condition S or 
repeated start condition Sr implies a change of the data wire to the 
prevalence logic condition (from high to low) while the clock wire is 
still at the non-prevalence condition (=high). Any prospective master 
station can do this so long as the bus has not been assigned to another 
master. At the end, the stop condition P is anti-symmetric with the start 
condition. At all other times, the dam may only change when the clock is 
at the prevalence value (=low). The first transfer has seven address bits, 
next a read/write (R/W) control bit, and space for an acknowledge bit from 
another station having recognized its slave address. Subsequently, a 
series of 8-bit data bytes is transmitted, each with its own space for an 
acknowledge bit. In case of a long-format 10-bit address, the first data 
byte is replaced by the second byte of the slave address. If two or more 
prospective masters start transmitting simultaneously, the arbitrage is 
effected bit by bit on the basis of the slave address. If more than one 
prospective master addresses the same slave, the arbitrage may thus 
proceed on the basis of the subsequent data. 
FIG. 3 is a diagram of a data transfer with 7-bits address; hatching means 
transfer direction from master to slave; the non-hatched remainder goes 
the opposite way. Here, the transfer direction of successive bytes is not 
changed. The transmission sequence is start condition S, seven bit slave 
address SLA, read/write control bit R/W' indicating a write (0), address 
acknowledge A, sequence of one or more data bytes each accompanied by its 
own acknowledge A, and stop condition P. The final acknowledge may have 
logic value `false`. 
FIG. 4 is a diagram of a data-transmit to a slave station with a 10-bit 
address. The difference with the preceding Figure is that the first slave 
address byte SLA1 starts with a control code 11110, which indicates a 
forthcoming long-format slave address. This code as well as 11111 are 
forbidden for the short format seven-bit slave address. This means that in 
principle, 120 different addresses were available. In practice, a few of 
these have been reserved, such as for "address all slaves". Now, any such 
address has at least one zero in the four leading bit positions. The 
arbitrage grants a "zero" bit prevalence to a "one" bit, which means that 
any seven-bit address always "wins" against a ten-bit address. Next, the 
sixth and seventh bits are the high-significance bits of the long-format 
slave address. Slave stations having a short-format address are precluded 
from being addressed through the control code 11110, while being 
completely normally addressable through their respective original address 
codes. Slave stations having the long-format address and the correct high 
significance address part SLA1 now give a positive acknowledge A1, even if 
their low-significance address part would not match. After the second 
slave address byte SLA2 only the slave station with the total correct 
slave address will give a positive acknowledge A2. Next, a sequence of 
data bytes is transmitted just as in the earlier case. 
FIG. 5 is a diagram of a data-receive from a slave station with a 10-bit 
address. The transmission of the long-format slave address is identical to 
that of the preceding Figure, up to acknowledge A2. Subsequently, a 
repeated start condition Sr is given to signal to the actually locked-in 
slave station that a control change will be undertaken. This is effected 
by producing a repeated start condition, having the same shape as the 
original start condition, and repeating the first address byte, again 
SLA1, but with inverting the read/write control bit. Subsequently, the 
one- or multi-byte data transfer is undertaken as before, be it that the 
data transfer direction is now towards the master. The clock 
synchronization is always effected by the master station, regardless of 
the direction of the data transfer. During arbitrage between a plurality 
of prospective master stations, they all generate clock pulses that merge 
through the wired logic functionality jsut as in the case of the various 
address bits generated by those prospective master stations on the data 
wire. 
FIG. 6 is a diagram of a combined data transmit and receive format with a 
10-bits address. The format largely conforms to that of FIG. 5, be it that 
the repeated start condition and associated first slave address byte SLA1 
are only given after one or more data bytes had been transmitted from the 
master towards the slave station. 
FIG. 7 shows a data transmit with two 10-bits addresses. This largely 
corresponds to the setup of FIG. 4, be it that now data is transmitted 
first to one slave, next to another slave, each with a repective ten-bit 
adrress, without releasing the bus. 
FIG. 8 shows a data transmit with mixed addresses. First, the set-up with a 
seven bit address is shown, followed by addressing of a slave station that 
has the long-format address, again without releasing the bus. The 
alternative sequence, starting with a ten-bit slave address is feasible 
just as well. In similar fashion, an established master may go on 
addressing successive slave stations with arbitrary seven-bit and ten-bit 
addresses, and either for a data-transmit or for a data receive operation. 
The bus is only released with the stop condition P. Thereafter, any 
propsective master, whether earlier rejected during the arbitrage, or 
newly emerged, may start a fresh arbitraging operation. 
FIG. 9 shows a slope controlled output stage in C-MOS; this circuit is 
added at the interface between the respective station and either the clock 
wire SCL or the data wire SDA; the circuit is thus generally provided 
twice for each applicable station. Now, the wire in question has a pull-up 
resistance R.sub.p to V.sub.DD and a load Capacitance C.sub.b to V.sub.SS. 
As shown, the wire itself is bidirectional: I/O. The signal input of the 
station in question has been labeled IN, the signal output has been 
labeled OUT. The latter goes to a CMOS inverter P1/N1, whose output 
controls line drive transistor N2. Steering the latter to conductivity can 
bring the wire voltage to V.sub.SS within a very short time of a few 
nanoseconds only. This circuit has been intended for allowing a higher 
bit-rate of some 400 kbits/second. Now, the circuit shown would at such 
increased bit rate provide better EMC (ElectroMagnetic Compatibility) 
adherence. The effect is realized through provision of resistor R1 and 
capacitor C1, which together provide a time constant of 100 nanoseconds. 
In fact, if the line voltage changes too fast towards V.sub.SS, capacitor 
C1 operates as a Miller capacitor for coupling the instantaneous wire 
voltage to the control electrode of transistor N2 for so slowing down the 
transient signal edge. A particular advantage of the circuit is that no 
current source is necessary during standby operation, when the station in 
question is non-transmitting. In the other direction, when transistor N2 
is steered to a blocking condition, the pull-up resistor R.sub.p is rather 
too high for allowing a sufficiently fast edge, as will be discussed with 
respect to FIG. 11. For brevity, the attachment of connections IN and OUT, 
respectively, to the inner functionality of the station in question has 
not been shown. 
FIG. 10 shows a slope controlled output stage using bipolar transistors. 
The circuit to a great extent corresponds to that of FIG. 9, and largely 
has the same advantages. The line drive transistor T2 is controlled by the 
output signal of transistor T1. Because of the necessity of providing the 
base current of transistor T2, resistor R1 now has a lower value. Through 
increasing the value of capacitor C1, the RC time constant value is kept 
the same. Variations on the theme shown would likewise flatten the edge 
within the context of the present invention. 
FIG. 11 shows a switched pull-up circuit. In principle, this needs to be 
provided only once for each wire SDA or SCL. Specifically shown are two 
stations DEV1, DEV2, together with their optional serial input resistance 
R.sub.s, and line drive transistors N (N2 in FIG. 9). The maximum load 
capacitance C.sub.b is 400 pF. For small systems, wherein this capacitance 
is lower than 200 pF, the circuit of FIG. 11 may even be omitted. During 
the rising/falling edges on the bus wire, the bilateral switch cum 
inverter in HCT4066 switches pull up resistor R.sub.p 2 on and off between 
levels of 0.8 and 2.0 Volts, respectively. Combined resistors R.sub.p 1 
and R.sub.p 2 can pull up the bus wire within the maximum specified rise 
time of 300 nanoseconds.