Semiconductor MEMS structure and manufacturing method thereof

The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a plurality of conductive pads over the first substrate; forming a film on a first subset of the plurality of conductive pads, thereby leaving a second subset of the plurality of conductive pads exposed from the film; forming a self-assembled monolayer (SAM) over the film; and forming a cavity by the first substrate and a second substrate through bonding a portion of the second substrate to the second subset of the plurality of conductive pads that are exposed from the film.

BACKGROUND

Electronic equipment involving semiconductive devices are essential for many modern applications. Technological advances in materials and design have produced generations of semiconductive devices where each generation has smaller and more complex circuits than the previous generation. In the course of advancement and innovation, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such advances have increased the complexity of processing and manufacturing semiconductive devices.

Micro-electro mechanical system (MEMS) devices have been recently developed and are also commonly involved in electronic equipment. The MEMS device is a micro-sized device, usually in a range from less than 1 micron to several millimeters in size. The MEMS device includes fabrication using semiconductive materials to form mechanical and electrical features. The MEMS device may include a number of elements (e.g., stationary or movable elements) for achieving electro-mechanical functionality. MEMS devices are widely used in various applications. MEMS applications include motion sensors, pressure sensors, printer nozzles, or the like. Other MEMS applications include inertial sensors, such as accelerometers for measuring linear acceleration and gyroscopes for measuring angular velocity. Moreover, MEMS applications are extended to optical applications, such as movable mirrors, and radio frequency (RF) applications, such as RF switches or the like.

DETAILED DESCRIPTION

As MEMS devices are widely adopted in various applications, it is usually required that the structure of one MEMS device may accommodate more than one type of MEMS function. For example, a single MEMS framework may include an accelerometer and a gyroscope. For such MEMS devices, the final product is fabricated as a composite chip and performs multiple functions with a reduced die size.

In some cases, the merge of different types of MEMS elements into one die may confront incompatible design criterions. For example, the accelerometer is manufactured to form a cavity where a moderate amount of gas is permitted. However, a gyroscope is required to be fabricated under a near vacuum environment for achieving a designated sensing accuracy. Unfortunately, existing semiconductor methods cannot provide an efficient solution to make a cost-effective composite MEMS die.

Taking a combo chip as an example, the combo chip may be fabricated to combine an accelerometer and a gyroscope in a single MEMS structure with different manufacturing criteria. In addition, an anti-stiction layer is usually deposited on sensing electrodes of the MEMS structure for mitigating the stiction problem of a movable membrane when the movable membrane hits the sensing electrodes. An anti-stiction layer is usually deposited non-selectively and may be on each surface and sidewall of the MEMS structure. However, the anti-stiction layer may hinder the adhesion performance when a bonding operation is performed to bond different components at the bonding pads thereof. In order to maintain the performance of eutectic bonding, various methods are used for removing undesired anti-stiction materials at the bonding interface of the bonding pads before the MEMS device is sealed. Although those methods, such as a thermal treatment, may be effective in cleaning the anti-stiction materials off of the bonding interface, the integrity of the anti-stiction layer on the sensing electrodes would also be adversely affected.

The present disclosure presents a new architecture and method for mitigating the problems discussed above. A seed layer is patterned over the sensing electrodes before the anti-stiction layer is formed. Then the anti-stiction layer is deposited on the seed layer. The seed layer can effectively increase the bonding performance between the anti-stiction layer and the sensing electrodes. In addition, the seed layer is patterned to cover the sensing electrodes only. When a thermal removal process is performed to remove undesired portions of the anti-stiction layer on the surface on the bonding pads, the anti-stiction layer can still be safely bonded to the sensing electrodes through the seed layer.

FIG. 1Ais a schematic perspective view of a semiconductor structure100in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor structure100comprises an MEMS device. The MEMS device100includes a first structure110having a substrate112and an interconnect structure114. The MEMS device100also includes a second substrate160opposite to the first structure110. The semiconductor structure100further includes several first pads152and several second pads154, and a sensing element157in the cavity140.

The first semiconductor structure110is configured to perform specific functions and communicate with neighboring components. In some embodiments, the first structure110may include a logic circuit. In some embodiments, the first structure110may further include memory cells or other electrical components. In some embodiments, the substrate112may include a myriad of passive or active components (not shown) disposed on a surface facing the interconnect structure114. In some embodiments, the first structure110is referred to as a first substrate110.

The substrate112includes a semiconductor material such as silicon. In some embodiments, the substrate112may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In some embodiments, the substrate112is a p-type semiconductive substrate (acceptor type) or n-type semiconductive substrate (donor type). Alternatively, the substrate112includes another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the substrate112is a semiconductor-on-insulator (SOI). In other alternatives, the substrate112may include a doped epitaxial layer, a gradient semiconductor layer, and/or a semiconductor layer overlaying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer.

The interconnect114is disposed over the substrate112. In some embodiments, the interconnect114is disposed between the second structure160and the substrate112. The interconnect114is configured to electrically couple electrical components within the substrate112. In some embodiments, the interconnect114is configured to electrically couple the substrate112with a device or component external to the first substrate110. The interconnect114may include multiple metal layers. Each of the metal layers may include conductive wires or lines and is electrically coupled to an adjacent overlaying or underlying metal layer through at least one metal via. In the present embodiment, metal layers131,133,135and137are disposed in a layered structure and are interconnected through corresponding metal vias132,134and136. The numbers and patterns of the metal layers and vias of the interconnect114are provided for illustration. Other numbers of metal layers, metal vias, or conductive wires and alternative wiring patterns are also within the contemplated scope of the present disclosure.

Moreover, the aforesaid metal layers and metal vias are electrically insulated from other components. The insulation may be achieved by insulating materials. In some embodiments, the remaining portion of the interconnect114may be filled with an inter-metal dielectric (IMD)123. The dielectric material of the IMD123may be formed of oxides, such as un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values lower than 3.8, although the dielectric materials of the IMD123may also be close to 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5.

In some embodiments, the first substrate110may be a sensing device configured to captured physical data. Typical sensing devices include an accelerometer, gyroscope, inertial measurement unit (IMU), acoustic sensor, temperature sensor, etc.

In some embodiments, the cavity140is formed between the first substrate110and the second substrate160. In still other embodiments, the cavity140comprises a side on the first substrate110or the second substrate160. The cavity140is formed to accommodate the sensing element157and the first pads152. The first pads152may be disposed on one side of the cavity and extruding from a surface114A of first substrate110. In some embodiments, the first substrate110or the second substrate160comprises a recessed portion, and the cavity140may be formed by bonding the first substrate110with the second substrate160whereby the recessed portion is transformed into the cavity140. In some embodiments, the cavity140may be filled with a gas or liquid for facilitating data sensing. In some embodiments, an inlet via is configured to introduce gas into the cavity140. In some embodiments, the cavity140is kept at a vacuum or near-vacuum environment.

In some embodiments, the first pads152are configured as sensing electrodes. For example, the first pads152are configured to induce a variable capacitance or resistance in response to changes of data that is being measured. In some embodiments, the first pads (e.g., sensing electrodes)152are configured to perform data sensing in conjunction with the sensing element157. In some embodiments, the sensed electrical properties, such as current or voltage, are transmitted to a data collection unit or signal processing unit in the first substrate110through the interconnect114. For example, one first pad152is configured to provide the sensing data to the substrate112via the metal layers131,133,135and137and metal vias132,134and136.

The first pads152are disposed in the cavity140. In some embodiments, the first pads152are disposed on one side of the cavity140. In some embodiments, the first pads152may be disposed over the first substrate110. In some embodiments, the first pads152are proximal to the sensing element157. The first pads152and the sensing element157may be arranged closely but yet separate from each other.

The first pads152may be formed of conductors. Alternatively, the first pads152may be formed with conductive or semiconductive materials. In some embodiments, the first pads152may include metal such as gold, silver, aluminum, titanium, copper, tungsten, nickel, titanium, chromium, and an alloy, oxide or nitride thereof.

The second pads154are disposed on the cavity140. In some embodiments, the second pads154are disposed on the top surface114A of the first substrate110. In some embodiments, the second pads154are disposed on a top surface of the interconnect114and leveled with the first pads152. The second pads154are configured to provide bonds between the first substrate110and the second substrate160.

In some embodiments, the second pads154are configured as bonding pads. For example, the second pads154are configured to form a eutectic bonding with the second substrate160. In some embodiments, the second pads154may be formed with conductive materials. In some embodiments, the second pads154may include metal such as gold, silver, aluminum, titanium, copper, tungsten, nickel, titanium, chromium, and an alloy, oxide or nitride thereof.

The second substrate160is configured to form the cavity140in conjunction with the first substrate110. In some embodiments, the second structure160is configured to serve as a capping substrate over the first substrate110.

The second substrate160includes a semiconductor material such as silicon. In some embodiments, the second substrate160may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In some embodiments, the second substrate160is a p-type semiconductive substrate (acceptor type) or n-type semiconductive substrate (donor type). Alternatively, the second substrate160includes another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In yet another alternative, the second substrate160is a semiconductor-on-insulator (SOI). In some embodiments, the material of the second substrate160is the same as that of the substrate112.

The second substrate160comprises several protrusions extended toward the first substrate110. Also, the second substrate160comprises a bonding portion162at one end for each of the protrusions. The bonding portions162are configured to bond with the second pads154. In some embodiments, the bonding portions162perform eutectic bonding with the second pads154. In some embodiments, the bonding portions162comprise a suitable metal for composing eutectic alloys, such as In, Sn, Si and Ge. In some embodiments, the materials of the second pads154and the bonding portions162can be exchanged such that both the second pads154and the bonding portions162still constitute all elements for the same eutectic alloys.

The sensing element157is disposed opposite to the first substrate110. In some embodiments, the sensing element157is disposed away from the first pads152at a distance of about 0.5 μm to about 5 μm, or about 0.3 μm to about 5 μm. In some embodiments, the sensing element157is a movable membrane. In some embodiments, the sensing element157is in circular, rectangular, quadrilateral, triangular, hexagonal, or any other suitable shapes. In some embodiments, the sensing element157includes polysilicon. In some embodiments, the sensing element157is conductive and capacitive. In some embodiments, the sensing element157is supplied with a predetermined charge prior to performing data sensing.

In some embodiments, the sensing element157is a movable or oscillatable element. For example, the sensing element157is displaceable relative to the first substrate110and the first pads152. In some embodiments, the sensing element157is a movable membrane or diaphragm. In some embodiments, the displacement of the sensing element157relative to the first pads152would cause a capacitance change between the sensing element157and the first pads152. In some embodiments, the sensing element157is configured to capture a resistance change resulting from movement of the gas in the cavity140. The change of capacitance or resistance would then be translated into an electrical signal by a circuitry connected with the sensing element157or the first pads152. In some embodiments, the electrical signal generated would be transmitted to another device, another substrate or another circuitry for further processing.

In some embodiments, the movable membrane157may be displaced to contact the first pads152in response to an external stimulus, and restored to its original straight configuration. In some embodiments, the movable membrane157may be attached to the first pads152after hitting the first pads152, and is not capable of moving for a certain period. The issue of membrane stiction may cause the semiconductor device100to provide sensing results with reduced accuracy and reliability. In order to alleviate the stiction problem of the movable membrane157, in some embodiments, an anti-stiction layer158is proposed.

The anti-stiction layer158is disposed between the sensing element157and the first pads152. In some embodiments, the anti-stiction layer158is attached on a surface of the sensing element157, or a top surface and sidewalls of the first pads152at the contacting portions. For example, the sensing element157oscillates and contacts a top surface of the first pad152. The anti-stiction layer158covers the top surface of the first pad152. In some embodiments, the sensing element157oscillates and contacts a sidewall of the first pad152. In that case, the anti-stiction layer158covers the sidewall of the first pad152.

In some embodiments, the anti-stiction layer is a self-assembled monolayer (SAM) coating. In some embodiments, the SAM coating158has a thickness from about 5 Å to about 30 Å. In some embodiments, the SAM coating158has a thickness from about 15 Å to about 30 Å. In some embodiments, the SAM coating158has a thickness from about 5 Å to about 15 Å.

In some embodiments, the anti-stiction layer158comprises a hydrophobic surface which is helpful in counteracting the stiction strength of the sensing element157. In some embodiments, the presence of the anti-stiction layer158may be measured by the hydrophobic characteristic thereof. For example, the anti-stiction layer158may be measured with a water contact angle (WCA) metric. In some embodiments, the anti-stiction layer158comprises a WCA greater than about 90 degrees. In some embodiments, the anti-stiction layer158comprises a WCA from about 90 degrees to about 150 degrees. In some embodiments, the anti-stiction layer158comprises a WCA from about 100 degrees to about 120 degrees.

As discussed previously, when the anti-stiction material, such as the SAM coating158, is coated upon surfaces and sidewalls of the semiconductor structure100, portions of the SAM coating158may cover top surfaces of the second pads154. When the first substrate110is bonded with the bonding portions162of the second substrate160, the interposed anti-stiction material may hinder the bonding performance. A conventional method, such as a thermal treatment, may be effective in cleaning the anti-stiction material off of the bonding interface. However, the removal of the anti-stiction layer is not selective to different underlying materials. As a result, the anti-stiction layer on the sensing pads would also be partially or completely removed. The anti-stiction property of the sensing pads is deteriorated accordingly.

In the present disclosure, a film156is patterned and disposed on the first pads152. The film156may serve as a seed layer for the anti-stiction layer158. In some embodiments, the film156layer is disposed between the first pads152and the anti-stiction layer158. In some embodiments, the film156layer is sandwiched between the first pads152and the anti-stiction layer158. The film156couples the first pads152with the anti-stiction layer158. Therefore, the film156is arranged to enhance the inter-layer bondability between the anti-stiction layer158and the first pads152. In addition, the film156comprises a predetermined pattern to cover the first pads152only. In other words, the film156is configured to expose the second pads154in order to help bonding between the second pads154and the bonding portions162. However, a portion of the anti-stiction layer158on the first pads152are preserved by the film156. As a result, when an annealing process is performed to remove other portions of the anti-stiction layer158on the surface of the second pads154, the anti-stiction layer158can still be securely bonded to the first pads152through the film156.

In some embodiments, the film156contains silicon, or an oxide thereof. Alternatively, the film156contains a silicon nitride. In some embodiments, the film156comprises dielectric materials and may, for example, be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO2), a nitrogen-bearing oxide (e.g., nitrogen-bearing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), silicon oxynitride (SixOyNz), and the like. The film156and the anti-stiction layer158may be referred to as a silicon-containing layer156/158.

FIG. 1Bis a partially enlarged schematic view of the semiconductor device100inFIG. 1A, in accordance with some embodiments of the present disclosure. Specifically, several mesas including the first pads152are formed and protrude from the top surface114A of the first substrate110.

The film156exposes at least a portion of the top surface114A of the first substrate110. For example, a portion of the top surface114A of the interconnect114that is away from the mesas152is exposed from the film156. In some embodiments, the film156covers a top surface152A and a sidewall152B of the mesa152. In some embodiments, the anti-stiction layer158covers a top surface156A and a sidewall156B of the film156. In some cases the sensing element157oscillates in a lateral direction substantially parallel to the top surface114A and would otherwise contact the sidewall152B of the mesa152if the anti-stiction layer156is absent. As a result, a lateral stiction phenomenon may otherwise occur. In the present disclosure, the composite layer of anti-stiction layer158and the seed layer156covers the sidewall152B. The composite layer156/158is configured to expose the second pads154. Therefore, the bonding performance of the second pads154would not be adversely affected.

In some embodiments, the composite layer156/158comprises a top surface158A having a higher WCA than the top surface114A and any surface of the second pads154. In some embodiments, the composite layer156/158comprises a top surface having a WCA greater than 90 degrees. In some embodiments, the composite layer156/158comprises a top surface having a WCA between 90 degrees and 150 degrees. In some embodiments, the composite layer156/158comprises a top surface having a WCA between 100 degrees and 120 degrees.

In some embodiments, the composite layer156/158comprises a sidewall158B having a higher WCA than the top surface114A and any surface of the second pads154. In some embodiments, the composite layer156/158comprises a sidewall having a WCA greater than 90 degrees. In some embodiments, the composite layer156/158comprises a sidewall having a WCA between 90 degrees and 150 degrees. In some embodiments, the composite layer156/158comprises a sidewall having a WCA between 100 degrees and 120 degrees.

In some embodiments, the seed layer156may be differentiated from the anti-stiction layer158in terms of thickness. In some embodiments, the seed layer156has a larger thickness than the anti-stiction layer158. For example, the seed layer156comprises a thickness from about 80 Å to about 300 Å. In other embodiments, the seed layer156comprises a thickness from about 100 Å to about 200 Å. In some embodiments, a ratio of thickness between the seed layer156and the anti-stiction layer158is greater than about 10. In some embodiments, a ratio of thickness between the seed layer156and the anti-stiction layer158is from about 10 to about 50. In some embodiments, a ratio of thickness between the seed layer156and the anti-stiction layer158is from about 50 to about 100.

FIGS. 2A through 2Gare cross-sectional views of intermediate structures for a method of manufacturing a semiconductor structure inFIG. 1A, in accordance with some embodiments. InFIG. 2A, the substrate112is provided. In some embodiments, at least one active or passive element (not shown) may be formed in the substrate112. The substrate112has a first dopant type, such as a P-type.

Referring toFIG. 2B, the interconnect114is formed over the substrate112. The interconnect114may be formed of stacked metal layers from a bottom layer to a top layer. For example, the metal layer137is formed by depositing a mask layer (not separately shown) on the substrate112. The mask layer is patterned through an etching operation to form desired patterns. Then, conductive materials are filled in the etched patterns. The mask layer is stripped off by a removing operation after the pattern is filled with conductive materials. The IMD material123may be filled among the conductive materials of the metal layer137. Similarly, the conductive via layer136is formed over the metal layer137in order to generate a conductive connection between the metal layer137and the overlaying metal layer135. The metal layers135,133and131are formed in sequence along with the intervening conductive via layers134and132. A portion of the metal layer131is exposed from the interconnect114.

Referring toFIG. 2C, several first pads152and second pads154are formed at a topmost level of the first interconnect structure114. The first pads152are configured as sensing electrodes or metallic bumps on bump stop structures while the second pads154are used for bonding with overlaying structures.

InFIG. 2D, a patterned film156is deposited on the first pads152. The patterned film156may be formed by providing a mask layer with a predetermined pattern over the interconnect114, followed with an operation of vapor deposition or spin coating. “Vapor deposition” refers to processes of depositing materials on a substrate though the vapor phase. Vapor deposition processes include any process such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Examples of vapor deposition methods include hot filament CVD, radio-frequency CVD (rf-CVD), laser CVD (LCVD), conformal diamond coating processes, metal-organic CVD (MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), low-pressure CVD (LPCVD) and the like. In some embodiments, the film156includes silicon oxide or silicon nitride. A precursor for the deposition process may include silane. The mask layer is stripped off after the deposition operation is completed. The patterned film156covers the top surface152A and sidewalls152B of the first pads152.

Referring toFIG. 2E, an anti-stiction material158is blanket deposited over the top surface114A of the interconnect114. In addition, the anti-stiction material158covers the top surface156A and sidewalls156B of the film156. In some embodiments, the anti-stiction material158may cover the top surface or sidewalls of the second pads154. The anti-stiction layer158may be formed by vapor deposition. Examples of vapor deposition methods include molecular vapor deposition (MVD), hot filament CVD, radio-frequency CVD (rf-CVD), laser CVD (LCVD), conformal diamond coating processes, metal-organic CVD (MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), low-pressure CVD (LPCVD) and the like.

In an operation with reference toFIG. 2F, a thermal treatment or annealing process is applied to the first substrate110. The control parameters for the thermal treatment include a process temperature and a process period. In some embodiments, the process temperature may be controlled at about 400 degrees Celsius, and the process period may be control as about 120 minutes. After the thermal treatment, only the portions of the anti-stiction layer158bonded with the seed layer156are kept intact. In other words, the remaining seed layer156covers the top surface156A and sidewalls156B of the seed layer156. The other portions of the anti-stiction material158, such as those disposed on the second pads154, are removed due to the annealing operation.

Referring toFIG. 2G, the second substrate160including the sensing element157is provided and bonded with the interconnect114of the first substrate110. The cavity140is formed accordingly. The bonding process may comprise suitable operations, such as compressive bonding, thermal diffusion bonding, and eutectic bonding. In some embodiments, the bonding portions162are configured to form eutectic bonds with the interconnect114. The bonding interface between the bonding portions162and the interconnect114is free of the anti-stiction material158. As a result, the bonds along with the securely deposited anti-stiction layer over the first pads152can help provide reliable MEMS products with a wafer level package process.

The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a plurality of conductive pads over the first substrate; forming a film on a first subset of the plurality of conductive pads thereby leaving a second subset of the plurality of conductive pads exposed from the film; forming a self-assembled monolayer (SAM) over the film; and forming a cavity by the first substrate and a second substrate through bonding a portion of the second substrate to the second subset of the plurality of conductive pads that are exposed from the film.

The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a conductive mesa over the first substrate; forming a silicon containing layer over the mesa; and forming a cavity comprising a movable member proximal to the first substrate.

The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. The structure also includes a movable membrane in the cavity. Further, the structure includes a mesa in the cavity and the mesa is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the mesa, wherein the dielectric layer includes a first surface in contact with the mesa and a second surface opposite to the first surface is positioned toward the cavity.