Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

BACKGROUND

The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to fabricating a nanosheet transistor with a stacked air gap between stacked sheets and a side subway air gap along an edge.

As semiconductor microchips and integrated circuits become smaller, vertically stacked semiconductor nanosheets are increasingly being used. Nanosheets are two-dimensional nanostructures in which the vertical thickness is substantially less than the width. Semiconductor nanosheets are seen as a feasible option for reducing the size of semiconductor devices. Vertically stacked semiconductor nanosheets provide area efficiency and can provide increased drive current within a given layout.

The general process flow for semiconductor nanosheet formation involves the formation of a material stack that contains sacrificial layers of silicon germanium between silicon nanosheets. After removing the sacrificial layers, vertically stacked and suspended silicon nanosheets are provided. A functional gate structure can be formed above and below each silicon nanosheet.

SUMMARY

Aspects of an embodiment of the present invention include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

Aspects of an embodiment of the present invention include methods of fabricating a nanosheet transistor. The methods may include forming a nanosheet stack comprising sacrificial inner spacers and nanosheets, forming an epitaxial layer adjacent to the nanosheet stack, indenting the epitaxial layer to expose the sacrificial inner spacer at a corner etch, and removing the sacrificial inner spacer to form an air gap around the nanosheets.

Aspects of an embodiment of the present invention include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack comprising a first nanosheet and a second nanosheet and an inner spacer region between the first nanosheet and the second nanosheet. The inner spacer region may include an air gap over a width of the first nanosheet and the second nanosheet.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which show specific examples of embodiments of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the described embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the included embodiments are defined by the appended claims.

With regard to the fabrication of transistors and integrated circuits, major surface refers to that surface of the semiconductor layer in and about which a plurality of transistors are fabricated, e.g., in a planar process. As used herein, the term “vertical” means substantially orthogonal with respect to the major surface. Typically, the major surface is along a plane of a monocrystalline silicon layer on which transistor devices are fabricated.

Improvements in the design of transistor devices have enabled feature sizes to enter into deep submicron and nanometer regime. These smaller feature sizes, however, can cause otherwise minor issues to have more detrimental effect on the operation of the transistor device. For example, parasitic capacitance, especially a fringing parasitic capacitance between a gate and a source/drain, may account for a higher proportion of the total capacitance in smaller transistor devices. A high proportion of parasitic capacitance can result in a severe influence on the transient response of the device.

To reduce parasitic capacitance, transistor devices can include spacers made of materials with low dielectric constants in designated areas. In certain embodiments, the spacers may be formed using air gaps, since air has a very low dielectric constant. If the air gaps are not formed properly, however, then any benefit the air provides may be unrealized. For example, if epitaxially grown source/drain regions grow into the air gap region, then the transistor device will suffer decreased performance. The embodiments described below, therefore, include a spacer region that has an air gap formed after the epitaxial regions are grown.

FIG.1depicts a nanosheet transistor100at a fabrication stage of the processing method, in accordance with one embodiment of the present invention. The nanosheet transistor100includes nanosheets102and sacrificial semiconductor layers104that are formed in an alternating series as a vertical layer stack105on a substrate106. The substrate106includes a shallow trench isolation108, which may be the buried oxide (BOX) layer of a semiconductor-on-insulator (SOI) substrate or dielectric isolation in a bulk substrate. The nanosheets102(i.e., nanosheets or nanowires) may be composed of a semiconductor material, such as silicon (Si). The sacrificial semiconductor layers104may be composed of a semiconductor material, such as silicon germanium (SiGe). The nanosheets102and the sacrificial semiconductor layers104may be formed by an epitaxial growth process, and at least the sacrificial semiconductor layers104may be undoped. The semiconductor material of the sacrificial semiconductor layers104is selected to be removed cleanly from the semiconductor material of the nanosheets102. As used herein, the term “cleanly” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. The sacrificial semiconductor layers104may include a bottom sacrificial semiconductor layer104athat has a different silicon germanium ratio that enables a fabrication operator to cleanly remove the bottom sacrificial layer104awithout removing the other sacrificial semiconductor layers104or the nanosheets102. The number of nanosheets102and sacrificial semiconductor layers104may differ (more layers or fewer layers) from the number depicted in the representative embodiment.

A hardmask110is formed on the top surface of the layer stack105that includes the nanosheets102and the sacrificial semiconductor layers104. The hardmask110may be composed of a hardmask material, such as silicon nitride, that is deposited (e.g., by chemical vapor deposition (CVD)) and patterned using a litho patterning process. The patterning enables the nanosheet transistor100to be formed as a fin112, where the nanosheets102and the sacrificial semiconductor layers104are a trimmed layer stack105with alternating sections of the nanosheets102and sacrificial semiconductor layers104. The fin112projects in a vertical direction relative to a major surface114of the shallow trench isolation108. The hardmask110furnishes as an etch mask during the etching process forming the fin112.

FIG.2depicts a cross-sectional side view of the nanosheet transistor100ofFIG.1, with like reference numerals referring to like features and at a subsequent fabrication stage of the processing method. InFIG.2, the nanosheet transistor100has side sacrificials116formed on either side of the fin112. The side sacrificials116may be formed using atomic layer deposition (ALD) and anisotropic etch. Additionally or alternatively, the side sacrificials116may be formed epitaxially. The side sacrificials116may be formed using the same material as the sacrificial semiconductor layers104. For example, the side sacrificials116and the sacrificial semiconductor layers104may be formed with silicon germanium having the same percentage of germanium (e.g., 25 percent, 30 percent, 35 percent, 40 percent, or 45 percent). The bottom sacrificial semiconductor layer104amay also include silicon germanium, but may include a different percentage (e.g., 50 percent, 55 percent, 60 percent, 65 percent, or 70 percent). The side sacrificials116may also be formed using different material from the sacrificial semiconductor layer104.

FIG.3depicts a cross-sectional side view of the nanosheet transistor100ofFIG.1, with like reference numerals of previous figures referring to like features and at a subsequent fabrication stage of the processing method. InFIG.3, the nanosheet transistor100has a blocking mask118that protects one side sacrificial116per fin112while the other side sacrificial116is etched. Etching one side sacrificial116exposes the nanosheets102and the sacrificial semiconductor layers104on a first edge120a. The material of118could be conventional organic thin films used in lithography process, such as OPL.

FIG.4depicts a schematic top view of the nanosheet transistor100at the fabrication stage ofFIG.7, with like reference numerals of previous figures referring to like features.FIG.4also illustrates cross-sectional lines, namely X, X′, Y, and Y′, that indicate the cross-sectional views for subsequent figures described in this application. The X and X′ lines indicate cross-sectional views along the x-axis, while the Y and Y′ lines indicate cross-sectional views along the y-axis. The X cross-sectional view is lengthwise along the stack105of nanosheets102and sacrificial layers104. The X′ cross-section view is lengthwise along the side sacrificial116that will eventually become a side subway region. The Y cross-sectional view is widthwise across the stack105of nanosheets102and sacrificial layers104under the gate spacer region (and is the cross-sectional view ofFIGS.1-3). The Y′ cross-sectional view is also widthwise, but at a location that will eventually be source/drain regions of the devices as shown in detail below.

FIG.5depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.3.FIG.5also includes cross-sectional lines in the X′ figure indicating the location for the Y and Y′ cross-sections, and cross-sectional lines in the Y figure indicating the location for the X and X′ cross-sections. InFIG.5, the blocking mask118and the nanosheet hardmask110have been removed. The nanosheet transistor100now includes a dummy gate structure122having a top hard mask122aand a bottom dummy gate structure122b(i.e., only shown in the X and X′ subfigures). The dummy gate structure122may be formed from hard mask materials of any variety, since the dummy gate structure122is removed before fabrication of the nanosheet transistor100is completed. The bottom dummy gate structure122bmay include a thin silicon oxide layer followed by amorphous silicon that is patterned by conventional litho and etch process.

FIG.6depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.5.FIG.6also includes a gap124where the bottom sacrificial semiconductor layer104ahas been etched cleanly from the substrate106, the side sacrificial116, and the remaining sacrificial semiconductor layers104. The nanosheets102and sacrificial semiconductor layers104are held in place at a second edge120bby the side sacrificial116, which is attached to the shallow trench isolation108.

FIG.7depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.6.FIG.7also includes a spacer dielectric126(e.g., silicon oxide, silicon nitride) formed around the dummy gate structure122and around the stacks105of nanosheets102and sacrificial semiconductor layers104. The spacer dielectric126forms under the sacrificial semiconductor layer104as well, in the location where the bottom sacrificial layer104ahad been before being removed. As shown in subfigure Y′, the spacer dielectric126does not fill all of an interlayer dielectric area128between the first stacks105-1and the second stacks105-2. In the regions directly around the dummy gate structure122, however, the space between the stacks105is filled with spacer dielectric126.

FIG.8depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.7.FIG.8illustrates segmentation of the fin112, and the indentation of the sacrificial semiconductor layers104. The fin112is segmented when the entire stack105(nanosheets102, sacrificial semiconductor layers104, and side sacrificials116) is etched down to the major surface114of the substrate106and the shallow trench isolation108in the areas between the dummy gate structures122, as shown in subfigure Y′. This segmentation creates a separation130between a first stack105aand a second stack105b(see subfigure X). The nanosheets102under the spacer dielectric126between the stacks105a/105bare not etched, but the sacrificial semiconductor layers104are indented an indentation distance132that corresponds to the thickness of the spacer dielectric126covering the dummy side structure122. The side sacrificial116under the dummy gate structure122is etched the indentation distance132, but is not etched completely, as shown in subfigure X′.

FIG.9depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.8.FIG.9shows the formation of a sacrificial inner spacer134, and the growth of the epitaxial layer136. The sacrificial inner spacer134may include titanium oxide, titanium nitride, or other materials and are formed around where the sacrificial semiconductor layers104were indented. After the sacrificial inner spacer134is formed, then the epitaxial layer136is formed between stack105aand stack105b.

FIG.10depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.9.FIG.10shows the deposition of an interlayer dielectric (ILD)138(e.g., silicon oxide, other dielectric materials). The ILD138is deposited between the dummy gate structures122in some areas over the epitaxial layer136(see subfigures X and X′) and in some areas over the major surface114(see subfigure Y′). The nanosheet transistor100is then planarized to a poly surface140. The poly surface140is located at a level so that the bottom dummy gate structure122bis exposed.

FIG.11depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.10.FIG.11shows a stage in which the dummy gate structure122(i.e., the bottom dummy gate structure122b) has been removed completely; the sacrificial semiconductor layer104, the side sacrificials116have been released; and a high-k metal gate (HKMG) stack142has replaced the sacrificial semiconductor layer104, the side sacrificials116, and a portion of the bottom dummy gate structure122b. After replacement of the HKMG stack142, the top portion of the HKMG stack142, including the spacer dielectric126are recessed, and re-filled with dielectric capping material144(i.e., a self-aligned contact cap or sacrificial cap).

FIG.12depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.11.FIG.12shows a contact cut148that defines regions where there are no S/D contacts in the ILD138over the epitaxial layer136. The contact cut148may be completed using reactive-ion etching (RIE). The contact cut148etches the ILD138without etching the spacer dielectric126or the epitaxial layer136.FIG.12purposefully shows that placement of the contact cut148can be not ideal (i.e., where some misalignment can happen during lithography process), such that the left edge of the contact cut lands over the epitaxial layer136, while the right edge of the contact cut lands over the epi spacer dielectric126. The embodiments disclosed herein enable air gaps to be formed under ideal contact cuts or misaligned cuts.

FIG.13depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.12.FIG.13shows a spacer pulldown region150, in which the spacer dielectric126is etched within the contact cut148. The spacer pulldown region150exposes the epitaxial layer136in both the left and right edge of the contact cut regions.

FIG.14depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.13.FIG.14shows a corner etch152on the epitaxial layer136. The corner etch152is located in the area that was exposed by the contact cut148and the spacer pulldown region150. The corner etch152exposes the sacrificial inner spacer134, as shown in subfigure X′, and the spacer dielectric126is above a top nanosheet102aas shown in subfigure Y.

FIG.15depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.14.FIG.15shows an air gap154in a spacer region156between the HKMG stack142and the epitaxial layer136. The air gap154is formed when the sacrificial inner spacer134is cleanly etched from the nanosheet transistor100. The sacrificial inner spacer134is made of a material that may be etched with minimal effect on the remainder of the nanosheet transistor100. As mentioned with regard toFIG.14, the etching of the sacrificial inner spacer134is enabled and completed through the corner etch152in the epitaxial layer136. For example, a chemical etch that is reactive with the sacrificial inner spacer134contacts the sacrificial inner spacer134through the corner etch152and is allowed to continue etching until the entirety of the sacrificial inner spacer134is removed. The air gap154thus includes an inner spacer region158between the nanosheets102, the inner spacer region158may include the entire width of the nanosheets102from the first edge120ato the second edge120b, such that the inner spacer region consists of only the air gap154. The air gap154may also include a side subway region160along the second edge120bof the nanosheets102and the inner spacer region158.

FIG.16depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.15.FIG.16shows a non-formal dielectric deposition162, such as silicon nitride fill that closes off the corner etch152and the spacer pulldown region150so that the air gap154is no longer exposed. As illustrated, the non-formal dielectric deposition162does not flow into the air gap154, but merely fills in the corner etch152and the spacer pulldown region150. The air gap154realizes completion, therefore, after the growth of the epitaxial layer136, which reduces the likelihood that any epitaxial growth will negatively contribute to parasitic capacitance in the nanosheet transistor100. One example of formation of the non-formal dielectric deposition162may be using a high-density plasma (HDP) deposition.

FIG.17depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.16.FIG.17shows a dielectric deposition overfill164that has filled the contact cut148up to the SAC cap surface140. The nanosheet transistor100may than be planarized back to the SAC cap surface140. The contact cut148may be filled, for example, using a chemical vapor deposition technique.

FIG.18depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.17.FIG.18shows an etch back of the ILD138from a trench area166. The ILD138is cleanly etched back without etching the spacer dielectric126, the sacrificial cap144, the epitaxial layer136, or the dielectric deposition overfill164.

FIG.19depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.18.FIG.19shows a metal liner deposition168for silicide formation. One example of metal liner could be titanium deposited by radio frequency physical vapor deposition (RFPVD).

FIG.20depicts four cross-sectional side views of the nanosheet transistor100at the locations indicated inFIG.4, with like reference numerals of previous figures referring to like features, and at a fabrication stage of the processing method that is subsequent toFIG.19.FIG.20shows the trench area166filled in with a trench contact170around the dielectric deposition overfill164, so that the nanosheet transistor100is ready for operation. In operation, the nanosheet transistor100will have less parasitic capacitance due to the spacer region156that is between the HKMG stack142and the epitaxial layer136. The spacer region156includes nanosheet stacks105made of nanosheets102. Between the nanosheets102, the stacks105include the inner spacer regions158and the side subway region160. The side subway region160is located along the second edge120bof the nanosheets102and the inner spacer region158.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.