Timing insulation circuitry for partial reconfiguration of programmable integrated circuits

A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.

TECHNICAL FIELD

This disclosure relates to integrated circuits (ICs) and, more particularly, to partial reconfiguration for a programmable IC.

BACKGROUND

A programmable integrated circuit (IC) refers to a type of device that includes programmable circuitry. An example of a programmable IC is a field programmable gate array (FPGA). An FPGA is characterized by the inclusion of programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), digital signal processing blocks (DSPs), processors, clock managers, and delay lock loops (DLLs).

Typically, each programmable circuit block includes programmable interconnects and programmable logic (referred to collectively as “programmable circuitry”). Programmable interconnects typically include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). Programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.

Some programmable ICs may be partially reconfigured. Partial reconfiguration refers to a capability in which a region of programmable circuitry of the device is reconfigured by loading different configuration data therein to implement different circuitry in the region than was previously implemented. The region is a portion of the available programmable circuitry on the device. Other portions of programmable circuitry of the device not included in the region may implement circuit design(s) that continue to operate uninterrupted by reconfiguration of the region. Partial reconfiguration allows the programmable IC to implement different circuit designs in a designated region over time while other neighboring and/or surrounding programmable circuitry of the device continues to operate without interruption.

SUMMARY

In one aspect, a device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device also includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.

In another aspect, a method includes providing a platform implemented in programmable circuitry of a device, wherein the platform is configured to communicate with a host data processing system, and providing a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The method also includes providing timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region and implementing a modified version of the platform in the device while keeping the timing insulation circuitry unchanged.

DETAILED DESCRIPTION

This disclosure relates to integrated circuits (ICs) and, more particularly, to partial reconfiguration for a programmable IC. In accordance with the inventive arrangements described herein, a programmable IC is used to provide a platform for implementing user-specified circuitry. The platform implemented in the programmable IC provides a circuit architecture that is capable of communicating with a host data processing system. The user-specified circuitry, or “kernels,” are hardware accelerated applications or circuit designs implemented in programmable circuitry of the programmable IC. Kernels may be implemented in the programmable IC under control of the host data processing system and, for example, a user-specified application executing in the host data processing system that requests implementation of different kernels in the programmable IC over time. The kernels are designed to couple to, or integrate with, the platform.

The platform allows the programmable IC to maintain connectivity, e.g., a communication link, with the host data processing system while different kernels are dynamically inserted, removed, and/or modified within the programmable IC over time. In addition to allowing the programmable IC to remain in communication with the host data processing system, the platform also allows kernel developers to focus their efforts on the particular operations to be performed by the kernels and not on the underlying infrastructure needed to move data into the kernel, out of the kernel, and/or exchange data between the programmable IC and the host data processing system.

In some data center environments, the platform implemented in the programmable IC is created and/or provided by the data center vendor. The kernels may be custom user-specified circuitry or pre-designed circuits selected by the user (e.g., where the user in this example is the data center customer) by way of the user-specified application executing in the host data processing system. This type of arrangement may be used with Field Programmable Gate Array (FGPA)-as-a-Service or “FaaS.”

It is not uncommon for platform providers to modify a platform over time. For example, a data center vendor may release an updated version of a platform to fix a bug, provide an incremental improvement to the platform, and/or provide a new feature in the platform. Since kernels are implemented against the platform available at the time (e.g., a particular platform), changes to the platform may render prior implemented kernels incompatible with the updated version of the platform. This means that each user may need to re-implement their kernels for use with the updated version of the platform. Re-implementation typically entails performing one or more stages of a design flow (e.g., synthesis, placement, and routing) anew. This is often a time consuming endeavor. Appreciably, in a data center environment, updating a platform may render many kernels across many different customers incompatible.

The inventive arrangements described within this disclosure address the incompatibility of implemented kernels with modified and/or updated platforms. Timing insulation circuitry is incorporated into the programmable IC to isolate timing of the user kernels from that of the platform. The timing insulation circuitry is implemented at or about the boundary between the platform and the partially reconfigurable (PR) region, or regions, used to implement kernels. For purposes of discussion, a PR region used to implement a user kernel (e.g., a user circuit design) is referred to herein as a “user PR region.” The timing insulation circuitry may be used to convey signals exchanged between the platform and the user PR region(s). By incorporating the timing insulation circuitry, the platform may be modified without affecting compatibility of the kernels. In short, kernels that were implemented and compatible with the platform will also be compatible with the updated version of the platform.

FIG. 1illustrates an example computing environment100for use with the inventive arrangements described within this disclosure. The computing environment includes a host data processing system (host system)102coupled to a hardware acceleration card (card)104. The components of host system102may include, but are not limited to, one or more processors106(e.g., central processing units), a memory108, and a bus110that couples various system components including memory108to processor(s)106. Processor(s)106may include any of a variety of processors that are capable of executing program code. Example processor types include, but are not limited to, processors having an x86 type of architecture (IA-32, IA-64, etc.), Power Architecture, ARM processors, and the like.

Bus110represents one or more of any of several types of communication bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of available bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, Peripheral Component Interconnect (PCI) bus, and PCI Express (PCIe) bus.

Host system102typically includes a variety of computer readable media. Such media may be any available media that is accessible by host system102and may include any combination of volatile media, non-volatile media, removable media, and/or non-removable media.

Memory108may include computer readable media in the form of volatile memory, such as random-access memory (RAM)112and/or cache memory114. Host system102may also include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example, storage system116may be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each may be connected to bus110by one or more data media interfaces. As will be further depicted and described below, memory108may include at least one computer program product having a set (e.g., at least one) of program modules (e.g., program code) that are configured to carry out the functions and/or operations described within this disclosure.

For example, program/utility118, having a set (at least one) of program modules120which may include, but are not limited to, an operating system, one or more application programs (e.g., user applications), other program modules, and/or program data, is stored in memory108. Program modules120generally carry out the functions and/or methodologies as described herein at least with respect to operations performed by host system102. For example, program modules120may implement a software stack. The software stack may implement a runtime environment capable of performing the host system102operations described herein. In one aspect, program modules120includes a driver or daemon capable of communicating with programmable IC132.

Program/utility118is executable by processor(s)106. Program/utility118and any data items used, generated, and/or operated upon by processor(s)106are functional data structures that impart functionality when employed by processor(s)106. As defined within this disclosure, a “data structure” is a physical implementation of a data model's organization of data within a physical memory. As such, a data structure is formed of specific electrical or magnetic structural elements in a memory. A data structure imposes physical organization on the data stored in the memory as used by an application program executed using a processor.

Host system102may include one or more Input/Output (I/O) interfaces128communicatively linked to bus110. I/O interface(s)128allow host system102to communicate with external devices, couple to external devices that allow user(s) to interact with host system102, couple to external devices that allow host system102to communicate with other computing devices, and the like. For example, host system102may be communicatively linked to a display130and to hardware acceleration card104through I/O interface(s)128. Host system102may be coupled to other external devices such as a keyboard (not shown) via I/O interface(s)128. Examples of I/O interfaces128may include, but are not limited to, network cards, modems, network adapters, hardware controllers, etc.

In an example implementation, the I/O interface128through which host system102communicates with hardware acceleration card104is a PCIe adapter. Hardware acceleration card104may be implemented as a circuit board that couples to host system102. Hardware acceleration card104may, for example, be inserted into a card slot, e.g., an available bus and/or PCIe slot, of host system102.

Hardware acceleration card104includes a programmable IC132. Hardware acceleration card104also includes volatile memory134coupled to programmable IC132and a non-volatile memory136also coupled to programmable IC132. Volatile memory134may be implemented as a RAM that is external to programmable IC132, but is still considered a “local memory” of programmable IC132, whereas memory108, being within host system102, is not considered local to programmable IC132. In some implementations, volatile memory134may include multiple gigabytes of RAM, e.g., 64 GB of RAM. Non-volatile memory136may be implemented as flash memory. Non-volatile memory136is also external to programmable IC132and may be considered local to programmable IC132.

FIG. 1is not intended to suggest any limitation as to the scope of use or functionality of the examples described herein. Host system102is an example of computer hardware (e.g., a system) that is capable of performing the various operations described within this disclosure relating to hardware acceleration card104and/or programmable IC132.

Host system102is only one example implementation of a computer that may be used with a hardware acceleration card. Host system102is shown in the form of a computing device, e.g., a computer or server. Host system102can be practiced as a standalone device, as a bare metal server, in a cluster, or in a distributed cloud computing environment. In a distributed cloud computing environment, tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

As used herein, the term “cloud computing” refers to a computing model that facilitates convenient, on-demand network access to a shared pool of configurable computing resources such as networks, servers, storage, applications, ICs (e.g., programmable ICs) and/or services. These computing resources may be rapidly provisioned and released with minimal management effort or service provider interaction. Cloud computing promotes availability and may be characterized by on-demand self-service, broad network access, resource pooling, rapid elasticity, and measured service.

Some computing environments, e.g., cloud computing environments and/or edge computing environments using host system102or other suitable data processing system, generally support the FPGA-as-a-Service (FaaS) model. In the FaaS model, user functions are hardware accelerated as circuit designs implemented within programmable ICs operating under control of the (host) data processing systems. Other examples of cloud computing models are described in the National Institute of Standards and Technology (NIST) and, more particularly, the Information Technology Laboratory of NIST.

Host system102is also an example implementation of an Electronic Design Automation (EDA) system. Program modules120, for example, may include software that is capable of performing a design flow (e.g., synthesis, placement, routing, and/or bitstream generation) on a circuit design. In this regard, host system102serves as an example of an EDA system that is capable of processing circuit designs and/or generating configuration bitstreams as described herein.

FIG. 2illustrates an example layout for a platform and a user PR region of a programmable IC. In the example ofFIG. 2, programmable IC132includes a platform202. Platform202is circuitry implemented in programmable circuitry of programmable IC132. Platform202facilitates communication between host system102and programmable IC132including any kernels implemented therein. The kernels are implemented in a user PR region208, which is connected to platform202.

Platform202is specified by a circuit design that is loaded into programmable IC132. Once implemented in programmable IC132, platform202provides host system interfaces and optionally memory interfaces for the duration of operation. Platform202may be implemented in programmable IC132by loading one or more configuration bitstreams therein.

In the example ofFIG. 2, platform202includes static platform circuitry210implemented in static region204and dynamic platform circuitry212implemented in platform PR region206. In one aspect, platform202is implemented by loading a first configuration bitstream to implement static platform circuitry210in static region204and a second configuration bitstream to implement dynamic platform circuitry212in platform PR region206. In some cases, as described herein, static platform circuitry210may include additional programmable circuitry located external to static region204and/or external to platform PR region206.

Static region204represents a region of programmable circuitry of programmable IC132that, once configured with a circuit design, implements components of platform202that do not change over time. Platform202may be provided by the manufacturer or provider of programmable IC132. In one aspect, static platform circuitry210is capable of establishing a communication link between programmable IC132and host system102. While static region204may be reconfigured (e.g., since the entirety of programmable IC132may be initialized and restarted), such an operation would take programmable IC132offline from host system102(e.g., disconnect the communication link established between programmable IC132and host system102).

Platform PR region206represents a region of programmable circuitry of programmable IC132. Platform PR region206implements other components of platform202that provide an interface between static region204, user PR region208, and optionally other resources such as off-chip memory (e.g., volatile memory134and/or non-volatile memory136) and/or other hardwired circuit blocks that may be included in programmable IC132. Dynamic platform circuitry212may be provided by the data center vendor. Platform PR region206may be reconfigured by loading a different configuration bitstream in programmable IC132without affecting or disrupting operation of static platform circuitry210in static region204. As such, aspects of platform202may be updated over time dynamically without disconnecting the communication link between programmable IC132and host system102.

User PR region208represents a region of programmable circuitry of programmable IC132. User PR region208connects to platform PR region206. User PR region208is used to implement one or more kernels specified by users (e.g., the end user). The kernels may have connections among themselves and/or to platform202via platform PR region206. User PR region208may be dynamically reconfigured over time to implement different kernels therein. The kernels implemented in user PR region208are designed to connect to circuit block(s) of dynamic platform circuitry212implemented platform PR region206.

In general, PR regions represent physical areas of programmable circuitry on programmable IC132that may be reconfigured. Each PR region may correspond to a reconfigurable module of a circuit design implemented in programmable IC132(e.g., in reference to the entire circuit structure implemented across programmable IC132). In one aspect, each PR region must not intersect with any other PR region. During partial reconfiguration of a specific reconfigurable module, only the PR region corresponding to that particular reconfigurable module is reprogrammed.

While platform202and user PR region208are described as being implemented using programmable circuitry, it should be appreciated that platform202and/or user PR region208may include one or more hardwired circuit blocks. Further, while a single user PR region is illustrated inFIG. 2, programmable IC132may include a plurality of user PR regions each connected to platform202.

FIG. 3illustrates an example implementation of platform202ofFIG. 2.FIG. 3illustrates a more detailed example of static platform circuitry210and dynamic platform circuitry212. In the example ofFIG. 3, static platform circuitry210may include Peripheral Component Interconnect Express (PCIe) interface302. Dynamic platform circuitry212may include a direct memory access (DMA) engine304and interconnect306. DMA engine304is connected to PCIe interface302and to interconnect306. Interconnect306may include a plurality of communication interfaces that may connect to timing insulation circuitry308, which in turn connects to kernels implemented in user PR region208. Dynamic platform circuitry212optionally includes one or more memory controllers310that are capable of connecting to volatile memory134(e.g., DDR memory) and/or non-volatile memory136.

In an example implementation, interconnect306is implemented as an on-chip interconnect. An example of an on-chip interconnect is an Advanced Microcontroller Bus Architecture (AMBA) eXtensible Interface (AXI) bus. An AMBA AXI bus is an embedded microcontroller bus interface for use in establishing on-chip connections between circuit blocks and/or systems. AXI is provided as an illustrative example of a communication interface and is not intended as a limitation of the examples implementations described within this disclosure. Other examples of communication interfaces include, but are not limited to, other types of buses, a network-on-chip (NoC), a cross-bar, or other type of switch. Interconnect306may provide streaming interfaces, memory mapped interfaces, or a combination thereof.

In the example ofFIG. 3, PCIe interface302is implemented in static region204. The other circuit blocks (e.g., interconnect306, DMA engine304, and optional memory controller(s)310) are implemented in platform PR region206. Timing insulation circuitry308may be implemented outside of platform PR region206as part of static platform circuitry210or within platform PR region206as part of dynamic platform circuitry212. As discussed, because platform202includes components such as PCIe interface302, DMA engine304, interconnect306, and/or memory controller(s)310, programmable IC132is capable of maintaining a communication link (e.g., a PCIe link) with host system102while user PR region208is dynamically reconfigured to insert, remove, and/or modify kernels implemented therein. Platform202may operate uninterrupted while user PR region208is dynamically reconfigured.

Further, platform PR region206may be dynamically reconfigured while static region204continues to operate uninterrupted. As such, platform202may be updated or modified while also maintaining the communication link with host system102. With the inclusion of timing insulation circuitry308as described herein, platform202may be updated while any kernels implemented for use with a particular platform implementation maintain compatibility with an updated (e.g., modified) version of the platform.

It should be appreciated that the particular interface used to communicate with host system102implemented within static region204may be one other than PCIe, e.g., an endpoint configured to operate with any of the example bus architectures described herein in connection with host system102.

FIGS. 4 and 5, taken collectively, illustrate an example modification to platform202without use of timing insulation circuitry. More particularly,FIGS. 4 and 5illustrate a modification to the dynamic platform circuitry within platform PR region206of platform202.

In the example ofFIG. 4, a signal path passing from the dynamic platform circuitry of platform PR region206to a kernel (e.g., one or more kernels or user circuitry) implemented in user PR region208is shown. The signal path traverses between platform PR region206and user PR region208with flip-flops (FFs)402and414as clocked endpoints. For purposes of illustration, the segment of the signal path shown starts at FF402, continues to lookup table (LUT)404, to port406, traverses from platform PR region206to user PR region208entering port408, continues to LUT410, to LUT412, and to FF414. The signal path from FF402to FF414is also a timing path in that the endpoints (e.g., FF402and FF414) are clocked circuit elements. The intervening circuit elements (e.g., LUT404, LUT410, and LUT412) are not clocked (e.g., are combinatorial logic).

In the example ofFIG. 5, platform202has been modified. The modification to platform202shown inFIG. 5may be implemented by the platform provider for any of a variety of reasons. These reasons may include, but are not limited to, implementing a bug fix, providing an incremental enhancement to the platform, or adding a new feature to the platform. The modification to platform202may be implemented after a number of users (e.g., FaaS users) have built kernels for implementation in user PR region208. Since these kernels are configured to connect to the prior version of platform202as shown inFIG. 4, the kernels are compatible with the version of platform202illustrated inFIG. 4.

FIG. 5illustrates how a change to platform202and, in particular, to the dynamic platform circuitry in platform PR region206, can change the timing of signals that pass between platform PR region206and user PR region208. Within platform PR region206, the number of logic levels has changed in the timing path from FF402to FF414, which crosses PR region boundaries. LUT502has been inserted into the dynamic platform circuitry in the signal path passing between FF402of platform PR region206and FF414of user PR region208. It should be appreciated that more than one LUT or other circuit component (e.g., combinatorial circuit element or unclocked circuit element) may be incorporated in the dynamic platform circuitry in platform PR region206between FF402and port406. Further, additional modifications may be introduced into the dynamic platform circuitry that are not illustrated inFIG. 5.

The modification to platform202shown inFIG. 5may render prior kernels implemented in user PR region208inoperable (e.g., function incorrectly) or incompatible (e.g., fail to meet timing) with the modified version of the platform shown inFIG. 5. For example, whereas a kernel may function correctly and meet timing when connected to the platform ofFIG. 4, the kernel may not function correctly or may not meet timing when connected to the platform ofFIG. 5. The modification to platform PR region206may negatively impact operability of the kernel and/or timing of signals that cross between platform PR region206and user PR region208. In such cases, the users have no choice other than to re-implement all kernel designs to close timing. As the number of user designs (e.g., kernels) grows over time, the maintenance required for these designs can become unwieldy and pose a limitation on how scalable platform202is.

FIGS. 6 and 7, taken collectively, illustrate an example modification to platform202with timing insulation circuitry. More particularly,FIGS. 6 and 7illustrate how the use of timing insulation circuitry addresses the operability and/or timing issues that may arise with modification of platform202.

In the example ofFIG. 6, timing insulation circuitry602is inserted into a region of programmable circuitry between platform PR region206and user PR region208. More particularly, timing insulation circuitry602is located between a boundary of the user PR region208and a boundary of the platform PR region206. In one aspect, the region of programmable circuitry in which timing insulation circuitry602is inserted is static circuitry. For example, the timing insulation circuitry is part of the static platform circuitry implemented in static region204of platform202. Timing insulation circuitry602may include a FF placed on each signal passing between ports of user PR region208and ports of platform PR region206. As shown, timing insulation circuitry602includes FFs604,606,608,610, and612. It should be appreciated that fewer or more FFs than shown may be included in timing insulation circuitry602depending on the number of signals that pass between user PR region208and platform PR region206. The inventive arrangements are not intended to be limited by the particular number of FFs shown.

In the example ofFIG. 7, platform202is modified. The dynamic platform circuitry of platform PR region206is modified to include additional logic levels between FF402and the port of platform PR region206. For example, multiplexers702and706, LUT704, and carry chain logic708are added. Timing insulation circuitry602insulates the timing of signal paths that pass between user PR region208and platform PR region206. Modifications to platform202can be made transparently without any impact on timing for existing implementations of user designs. Use of timing insulation circuitry602allows platform202to scale as needed through continued modifications to platform PR region206without causing operability and/or timing issues to arise with user designs implemented in user PR region208.

FIG. 7illustrates that increased delays associated with the modifications introduced in the dynamic platform circuitry are completely insulated and contained within platform PR region206. The timing of the signal path at the boundary between platform PR region206and user PR region208, which is now FF608to FF414in user PR region208, remains unchanged. Timing insulation circuitry602, in this example, shields changes in platform PR region206from user PR region206and guarantees that the previous kernel (e.g., user design) implementations compatible with the platform ofFIG. 6will be compatible with the updated platform ofFIG. 7.

In addition, the use of timing insulation circuitry602to separate two PR regions means that different combinations of user designs for user PR region208and designs for platform PR region206are compatible at the partial configuration bitstream level. Both timing and bitstream compatibility are achieved. Timing can be closed independently for a kernel (or kernels as the case may be) to be implemented in user PR region208and for the dynamic platform circuitry of platform202.

FIG. 8illustrates another example implementation of timing insulation circuitry602. In the example ofFIG. 8, timing insulation circuitry602is implemented within platform PR region206. Timing insulation circuitry602is implemented as part of the dynamic platform circuitry within platform PR region206. Any modifications introduced into platform PR region206may be implemented in the signal paths to the right of FFs604-612. This ensures that timing of the dynamic platform circuitry of platform PR region206is isolated from the timing of kernel(s) implemented in user PR region208. Timing of signal paths from any of FFs604-612into user PR region208remain unchanged.

In the example ofFIG. 8, timing insulation circuitry602is implemented within platform PR region206at a boundary of the user PR region208and the platform PR region206. More particularly, timing insulation circuitry602is located within platform PR region206at a boundary of platform PR region206adjacent to a boundary of user PR region208.

In the examples ofFIGS. 7 and 8, the EDA system used to implement the platform is capable of adding timing insulation circuitry602into either the static region or the platform PR region. In either case, the EDA system is capable of marking the timing insulation circuitry602. Once marked, the EDA system does not change the placement or routing of timing insulation circuitry for subsequent modifications to the platform. For example, the circuit design for the platform PR region is modified. When re-implemented, the EDA system does so without any change to the timing insulation circuitry. Prior placement and routing for the timing insulation circuitry in the prior version of the platform may be preserved and used in the modified version of the platform.

FIG. 9illustrates an example method900of implementing a platform for a programmable IC. An EDA system as described in connection withFIG. 1may perform the operations described in connection withFIG. 9.

In block902, a platform is provided. The platform is implemented in programmable circuitry of a device (e.g., a programmable IC). The platform is configured to communicate with a host system.

In block904, a first (e.g., user) PR region is provided. The first PR region is implemented in the programmable circuitry of the device. The first PR region is coupled to the platform. The first PR region is reserved for implementing user circuitry (e.g., kernels).

In block906, timing insulation circuitry is provided. The timing insulation circuitry is implemented in the programmable circuitry of the device. The timing insulation circuitry is capable of isolating timing of signals passing between the platform (e.g., the platform PR region) and the first PR region.

In block908, the EDA system is capable of implementing a modified version of the platform in the device. The modified version of the platform is implemented in the device while keeping the timing insulation circuitry unchanged. For example, updated or modified dynamic platform circuitry may be implemented in the platform PR region. This may be performed while the static platform circuitry continues to operate uninterrupted. Further, the user circuitry need not be reimplemented. In some cases, the user circuitry may continue to operate uninterrupted.

FIG. 10illustrates another example method1000of implementing a platform for a programmable IC. Method1000may be performed by host system102as described herein in connection withFIG. 1.

In block1002, the host system is capable of initiating the loading of a partial configuration bitstream into the programmable IC. The partial configuration bitstream loaded in block1002specifies the static platform circuitry of the platform implemented in the static region of the platform. In block1004, the host system is capable of initiating the loading of another partial configuration bitstream into the programmable IC. The partial configuration bitstream loaded in block1004specifies the dynamic platform circuitry of the platform. The dynamic platform circuitry is the portion implemented in the platform PR region of the platform.

In block1006, the timing insulation circuitry is implemented in the programmable circuitry of the programmable IC as part of the static region or the platform PR region. For example, when implemented as part of the static region, the timing insulation circuitry may be specified by the partial configuration bitstream of block1002. When implemented as part of the platform PR region, the timing insulation circuitry may be specified by the partial configuration bitstream of block1004.

In block1008, the host system is capable of initiating the loading of a partial configuration bitstream implementing one or more kernels within the user PR region. The partial configuration bitstream loaded in block1008specifies user circuitry that connects to the timing insulation circuitry of the platform. As discussed, whether implemented as part of the dynamic platform circuitry within the platform PR region or as part of the static platform circuitry between the platform PR region and the user PR region, the timing insulation circuitry exists at the boundary between the platform PR region and the user PR region.

In block1010, the host system is capable of initiating the loading of a different partial configuration bitstream that implements modified dynamic platform circuitry in the platform PR region of the programmable IC. The modified dynamic platform circuitry of the platform may include one or more modified signal paths that have endpoints corresponding to FFs of the timing insulation circuitry. As such, changes in the timing of these signal paths are isolated to within the platform PR region and do not extend into the user PR region.

FIG. 11illustrates another example method1100of implementing a platform for a programmable IC. Method1100may be performed by an EDA system as described herein in connection withFIG. 1.

In block1102, the EDA system is capable of including timing insulation circuitry in a circuit design for the platform. In block1104, the EDA system is capable of processing the static platform circuitry in the dynamic platform circuitry of the circuit design for the platform through a design flow. For example, the EDA system is capable of synthesizing, placing, and routing the circuit design.

In block1106, the EDA system is capable of marking the placement and routing information for the timing insulation circuitry. It should be appreciated that the EDA system is also capable of storing or preserving the placement and routing information for the timing insulation circuitry thereby allowing such information to be reused or preserved for subsequent modifications to the platform.

In block1108, the EDA system is capable of generating configuration bitstreams for the platform. For example, the EDA system may generate a first partial configuration bitstream specifying a placed and routed version of the static platform circuitry of the platform. The EDA system may also generate a second partial configuration bitstream specifying a placed and routed version of the dynamic platform circuitry of the platform.

In block1110, the EDA system is capable of processing modified version of the dynamic platform circuitry of the platform through the design flow. The EDA system processes the modified dynamic platform circuitry of the platform through the design flow while preserving the placement and routing information for the timing insulation circuitry.

In one aspect, where the timing insulation circuitry is included in the static platform circuitry, the modified dynamic platform circuitry of the platform is placed and routed to connect to the timing insulation circuitry (e.g., as in the example ofFIG. 7). In another aspect, where the timing insulation circuitry is included in the dynamic platform circuitry of the platform, the placement and routing information for the timing insulation circuitry may be re-used within the design flow of block1110.

In block1112, the EDA system is capable of generating a configuration bitstream specifying a placed and routed version of the modified dynamic platform circuitry of the platform for implementation in the platform PR region of the programmable IC.

FIG. 12illustrates an example architecture1200for an IC. In one aspect, architecture1200may be implemented within a programmable IC. For example, architecture1200may be used to implement a field programmable gate array (FPGA). Architecture1200may also be representative of a System-on-Chip (SoC) type of IC. An SoC is an IC that includes a processor that executes program code and one or more other circuits. The other circuits may be implemented as hardwired circuitry, programmable circuitry, and/or a combination thereof. The circuits may operate cooperatively with one another and/or with the processor.

As shown, architecture1200includes several different types of programmable circuit, e.g., logic, blocks. For example, architecture1200may include a large number of different programmable tiles including multi-gigabit transceivers (MGTs)1201, configurable logic blocks (CLBs)1202, random access memory blocks (BRAMs)1203, input/output blocks (IOBs)1204, configuration and clocking logic (CONFIG/CLOCKS)1205, digital signal processing blocks (DSPs)1206, specialized I/O blocks1207(e.g., configuration ports and clock ports), and other programmable logic1208such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth.

In some ICs, each programmable tile includes a programmable interconnect element (INT)1211having standardized connections to and from a corresponding INT1211in each adjacent tile. Therefore, INTs1211, taken together, implement the programmable interconnect structure for the illustrated IC. Each INT1211also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top ofFIG. 12.

For example, a CLB1202may include a configurable logic element (CLE)1212that may be programmed to implement user logic plus a single INT1211. A BRAM1203may include a BRAM logic element (BRL)1213in addition to one or more INTs1211. Typically, the number of INTs1211included in a tile depends on the height of the tile. As pictured, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) also may be used. A DSP tile1206may include a DSP logic element (DSPL)1214in addition to an appropriate number of INTs1211. An10B1204may include, for example, two instances of an I/O logic element (IOL)1215in addition to one instance of an INT1211. The actual I/O pads connected to IOL1215may not be confined to the area of IOL1215.

In the example pictured inFIG. 12, a horizontal area near the center of the die, e.g., formed of regions1205,1207, and1208, may be used for configuration, clock, and other control logic. Vertical areas1209extending from this horizontal area may be used to distribute the clocks and configuration signals across the breadth of the programmable IC.

Some ICs utilizing the architecture illustrated inFIG. 12include additional logic blocks that disrupt the regular columnar structure making up a large part of the IC. The additional logic blocks may be programmable blocks and/or dedicated circuitry. For example, a processor block depicted as PROC1210spans several columns of CLBs and BRAMs.

In one aspect, PROC1210may be implemented as dedicated circuitry, e.g., as a hardwired processor, that is fabricated as part of the die that implements the programmable circuitry of the IC. PROC1210may represent any of a variety of different processor types and/or systems ranging in complexity from an individual processor, e.g., a single core capable of executing program code, to an entire processor system having one or more cores, modules, co-processors, interfaces, or the like.

In another aspect, PROC1210may be omitted from architecture1200and replaced with one or more of the other varieties of the programmable blocks described. Further, such blocks may be utilized to form a “soft processor” in that the various blocks of programmable circuitry may be used to form a processor that can execute program code as is the case with PROC1210.

The phrase “programmable circuitry” refers to programmable circuit elements within an IC, e.g., the various programmable or configurable circuit blocks or tiles described herein, as well as the interconnect circuitry that selectively couples the various circuit blocks, tiles, and/or elements according to configuration data that is loaded into the IC. For example, circuit blocks shown inFIG. 12that are external to PROC1210such as CLBs1202and BRAMs1203are considered programmable circuitry of the IC.

In general, the functionality of programmable circuitry is not established until configuration data is loaded into the IC. A set of configuration bits may be used to program programmable circuitry of an IC such as an FPGA. The configuration bit(s) typically are referred to as a “configuration bitstream.” In general, programmable circuitry is not operational or functional without first loading a configuration bitstream into the IC. The configuration bitstream effectively implements a particular circuit design within the programmable circuitry. The circuit design specifies, for example, functional aspects of the programmable circuit blocks and physical connectivity among the various programmable circuit blocks.

Circuitry that is “hardwired” or “hardened,” i.e., not programmable, is manufactured as part of the IC. Unlike programmable circuitry, hardwired circuitry or circuit blocks are not implemented after the manufacture of the IC through the loading of a configuration bitstream. Hardwired circuitry is generally considered to have dedicated circuit blocks and interconnects, for example, that are functional without first loading a configuration bitstream into the IC, e.g., PROC1210.

In some instances, hardwired circuitry may have one or more operational modes that can be set or selected according to register settings or values stored in one or more memory elements within the IC. The operational modes may be set, for example, through the loading of a configuration bitstream into the IC. Despite this ability, hardwired circuitry is not considered programmable circuitry as the hardwired circuitry is operable and has a particular function when manufactured as part of the IC.

In the case of an SoC, the configuration bitstream may specify the circuitry that is to be implemented within the programmable circuitry and the program code that is to be executed by PROC1210or a soft processor. In some cases, architecture1200includes a dedicated configuration processor that loads the configuration bitstream to the appropriate configuration memory and/or processor memory. The dedicated configuration processor does not execute user-specified program code. In other cases, architecture1200may utilize PROC1210to receive the configuration bitstream, load the configuration bitstream into appropriate configuration memory, and/or extract program code for execution.

FIG. 12is intended to illustrate an example architecture that may be used to implement an IC that includes programmable circuitry, e.g., a programmable fabric. For example, the number of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top ofFIG. 12are purely illustrative. In an actual IC, for example, more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of a user circuit design. The number of adjacent CLB columns, however, may vary with the overall size of the IC. Further, the size and/or positioning of blocks such as PROC1210within the IC are for purposes of illustration only and are not intended as limitations.

For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the various inventive concepts disclosed herein. The terminology used herein, however, is for the purpose of describing particular aspects of the inventive arrangements only and is not intended to be limiting.

As defined herein, the term “approximately” means nearly correct or exact, close in value or amount but not precise. For example, the term “approximately” may mean that the recited characteristic, parameter, or value is within a predetermined amount of the exact characteristic, parameter, or value.

As defined herein, the term “automatically” means without human intervention.

As defined herein, the term “computer readable storage medium” means a storage medium that contains or stores program code for use by or in connection with an instruction execution system, apparatus, or device. As defined herein, a “computer readable storage medium” is not a transitory, propagating signal per se. A computer readable storage medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. The various forms of memory, as described herein, are examples of computer readable storage media. A non-exhaustive list of more specific examples of a computer readable storage medium may include: a portable computer diskette, a hard disk, a RAM, a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an electronically erasable programmable read-only memory (EEPROM), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, or the like.

As defined herein, the term “responsive to” and similar language as described above, e.g., “if,” “when,” or “upon,” means responding or reacting readily to an action or event. The response or reaction is performed automatically. Thus, if a second action is performed “responsive to” a first action, there is a causal relationship between an occurrence of the first action and an occurrence of the second action. The term “responsive to” indicates the causal relationship.

As defined herein, the term “processor” means at least one hardware circuit. The hardware circuit may be configured to carry out instructions contained in program code. The hardware circuit may be an integrated circuit. Examples of a processor include, but are not limited to, a central processing unit (CPU), an array processor, a vector processor, a digital signal processor (DSP), an FPGA, a programmable logic array (PLA), an ASIC, programmable logic circuitry, and a controller.

Computer readable program instructions for carrying out operations for the inventive arrangements described herein may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language and/or procedural programming languages. Computer readable program instructions may include state-setting data. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a LAN or a WAN, or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some cases, electronic circuitry including, for example, programmable logic circuitry, an FPGA, or a PLA may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the inventive arrangements described herein.

In some alternative implementations, the operations noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In other examples, blocks may be performed generally in increasing numeric order while in still other examples, one or more blocks may be performed in varying order with the results being stored and utilized in subsequent or other blocks that do not immediately follow. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, may be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements that may be found in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

A device may include a platform implemented in programmable circuitry of the device. The platform may be configured to communicate with a host data processing system. The device may include a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region may be reserved for implementing user-specified circuitry. The device may include timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.

In one aspect, the timing insulation circuitry may include a flip-flop on each signal passing between the platform and the first partial reconfiguration region.

In another aspect, the platform may include static platform circuitry. The timing insulation circuitry may be part of the static platform circuitry.

In another aspect, the platform may include a second partial reconfiguration region coupled to the first partial reconfiguration region. The timing insulation circuitry may be implemented between a boundary of the first partial reconfiguration region and a boundary of the second partial reconfiguration region.

In another aspect, the static platform circuitry of the platform may remain unchanged while the second partial reconfiguration region is reconfigured.

In another aspect, the static platform circuitry may remain unchanged while the first partial reconfiguration region is reconfigured.

In another aspect, the platform may include a second partial reconfiguration region coupled to the first partial reconfiguration region. The timing insulation circuitry may be implemented within the second partial reconfiguration region at a boundary of the second partial reconfiguration region adjacent to a boundary of the first partial reconfiguration region and the second partial reconfiguration region.

In another aspect, the timing insulation circuitry may remain unchanged while the second partial reconfiguration region is reconfigured.

In another aspect, the placement and routing of the timing insulation circuitry may remain when circuitry of the platform is modified.

In another aspect, the timing insulation circuitry may remain unchanged while a modified version of the platform is implemented in the device, wherein the modified version of the platform includes a modification of one or more of the signals that pass between the platform and the first partial reconfiguration region.

A method may include providing a platform implemented in programmable circuitry of a device. The platform may be configured to communicate with a host data processing system. The method may include providing a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The method may include providing timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region. The method may also include implementing a modified version of the platform in the device while keeping the timing insulation circuitry unchanged.

In one aspect, the timing insulation circuitry may include a flip-flop on each signal passing between the platform and the first partial reconfiguration region.

In another aspect, the modified version of the platform may include a modification of one or more of the signals that pass between the platform and the first partial reconfiguration region.

In another aspect, the platform may include static platform circuitry. The timing insulation circuitry may be part of the static platform circuitry.

In another aspect, the platform may include a second partial reconfiguration region coupled to the first partial reconfiguration region. The timing insulation circuitry may be implemented between a boundary of the first partial reconfiguration region and a boundary of the second partial reconfiguration region.

In another aspect, the static platform circuitry of the platform may remain unchanged while the second partial reconfiguration region is reconfigured.

In another aspect, the static platform circuitry may remain unchanged while the first partial reconfiguration region is reconfigured.

In another aspect, the platform may include a second partial reconfiguration region coupled to the first partial reconfiguration region. The timing insulation circuitry may be implemented within the second partial reconfiguration region at a boundary of the second partial reconfiguration region adjacent to a boundary of the first partial reconfiguration region and the second partial reconfiguration region.

In another aspect, the timing insulation circuitry may remain unchanged while the second partial reconfiguration region is reconfigured.

In another aspect, the placement and routing of the timing insulation circuitry may remain unchanged when circuitry of the platform is modified.

The description of the inventive arrangements provided herein is for purposes of illustration and is not intended to be exhaustive or limited to the form and examples disclosed. The terminology used herein was chosen to explain the principles of the inventive arrangements, the practical application or technical improvement over technologies found in the marketplace, and/or to enable others of ordinary skill in the art to understand the inventive arrangements disclosed herein. Modifications and variations may be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described inventive arrangements. Accordingly, reference should be made to the following claims, rather than to the foregoing disclosure, as indicating the scope of such features and implementations.