SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

A method for forming a semiconductor device structure is described. In some embodiments, the method includes forming a gate electrode, forming a mask structure over the gate electrode, patterning the mask structure to form an opening, and performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme. The first bias power has a first frequency to control etching along a lateral direction. The method further includes performing a second etch process on the mask structure exposed within the opening by applying a second source power and a second bias power with a second pulsing scheme, and the second bias power has a second frequency to control etching along a vertical direction. The first and second frequencies are substantially different.

BACKGROUND

Therefore, there is a need to improve processing and manufacturing ICs.

DETAILED DESCRIPTION

The present disclosure is generally related to semiconductor devices and fabrication methods, and more particularly to fabricating semiconductor devices using a cut metal gate (CMG) process. A CMG process refers to a fabrication process where after a gate electrode (e.g., a metal gate) replaces a dummy gate structure (e.g., a polysilicon gate), the gate electrode is cut (e.g., by an etching process) to separate the gate electrode into two or more portions. Each portion functions as a gate electrode for an individual transistor. An isolation material is subsequently filled into openings between adjacent portions of the gate electrode. In order to minimize a void formed in the isolation material, a main etch step and a final breakthrough etch step are performed to form the openings.

In some instances, in the described embodiments, various losses, e.g., in height, to the illustrated structures may occur during processing. These losses may not be expressly shown in the figures or described herein, but a person having ordinary skill in the art will readily understand how such losses may occur. Such losses may occur as a result of a planarization process such as a chemical mechanical polish (CMP), an etch process when, for example, the structure realizing the loss is not the primary target of the etching, and other processes.

FIGS.1,2,3A-B,4A-D, and5A-C through8A-C are various views of respective intermediate structures during intermediate stages in an example process of forming a semiconductor device structure including one or more FinFETs, in accordance with some embodiments.FIG.1illustrates, in a cross-sectional view, a semiconductor substrate20with a stressed semiconductor layer22formed thereover. The semiconductor substrate20may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include an elemental semiconductor such as silicon (Si) and germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof.

The stressed semiconductor layer22can have a compressive stress or a tensile stress. In some examples, the stressed semiconductor layer22is stressed as a result of heteroepitaxial growth on the semiconductor substrate20. For example, heteroepitaxial growth generally includes epitaxially growing a grown material having a natural lattice constant that is different from the lattice constant of the substrate material at the surface on which the grown material is epitaxially grown. Pseudomorphically growing the grown material on the substrate material can result in the grown material having a stress. If the natural lattice constant of the grown material is greater than the lattice constant of the substrate material, the stress in the grown material can be compressive, and if the natural lattice constant of the grown material is less than the lattice constant of the substrate material, the stress in the grown material can be tensile. For example, pseudomorphically growing SiGe on relaxed silicon can result in the SiGe having a compressive stress, and pseudomorphically growing SiC on relaxed silicon can result in the SiC having a tensile stress.

The stressed semiconductor layer22can be or include silicon, silicon germanium (Si1-xGex, where x can be between approximately 0 and 100), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Further, the stressed semiconductor layer22can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof on the semiconductor substrate20. A thickness of the stressed semiconductor layer22can be in a range from about 30 nm to about 50 nm.

FIG.2illustrates, in a cross-sectional view, the formation of fins24in the stressed semiconductor layer22and/or semiconductor substrate20. In some examples, a mask (e.g., a hard mask) is used in forming the fins24. For example, one or more mask layers are deposited over the stressed semiconductor layer22, and the one or more mask layers are then patterned into the mask. In some examples, the one or more mask layers may include or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another deposition technique. The one or more mask layers may be patterned using photolithography. For example, a photo resist can be formed on the one or more mask layers, such as by using spin-on coating, and patterned by exposing the photo resist to light using an appropriate photomask. Exposed or unexposed portions of the photo resist may then be removed depending on whether a positive or negative resist is used. The pattern of the photo resist may then be transferred to the one or more mask layers, such as by using a suitable etch process, which forms the mask. The etch process may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, the like, or a combination thereof. The etch process may be anisotropic. Subsequently, the photo resist is removed in an ashing or wet strip processes, for example.

Using the mask, the stressed semiconductor layer22and/or semiconductor substrate20may be etched such that trenches are formed between neighboring pairs of fins24and such that the fins24protrude from the semiconductor substrate20. In some embodiments, each fin24has a height ranging from about 115 nm to about 120 nm. The etch process may include a RIE, NBE, ICP etch, the like, or a combination thereof. The etch process may be anisotropic. The trenches may be formed to a depth in a range from about 80 nm to about 150 nm from the top surface of the stressed semiconductor layer22. In some embodiments, the trench between a pair of fins24may be substantially shallower than the trench between neighboring pairs of fins24due to the loading effect, as shown inFIG.2. In some embodiments where the trenches have different depths, the different depths may not be explicitly illustrated.

Although examples described herein are in the context of stress engineering for the fins24(e.g., the fins24include respective portions of the stressed semiconductor layer22), other examples may not implement such stress engineering. For example, the fins24may be formed from a bulk semiconductor substrate (e.g., semiconductor substrate20) without a stressed semiconductor layer. Also, the stressed semiconductor layer22may be omitted from subsequent figures; this is for clarity of the figures. In some embodiments where such a stress semiconductor layer is implemented for stress engineering, the stressed semiconductor layer22may be present as part of the fins24even if not explicitly illustrated; and in some embodiments where such a stress semiconductor layer is not implemented for stress engineering, the fins24may be formed from the semiconductor substrate20.

FIGS.3A and3Billustrate, in a cross-sectional view and top view, respectively, the formation of isolation regions26, each in a corresponding trench. The isolation regions26may include or be an insulating material, such as an oxide (such as silicon oxide), a nitride, the like, or a combination thereof, and the insulating material may be formed by a high density plasma CVD (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the isolation regions26include silicon oxide that is formed by a FCVD process. A planarization process, such as a CMP, may remove any excess insulating material and any remaining mask (e.g., used to form the trenches and the fins24) to form coplanar top surfaces of the insulating material and the fins24. The insulating material may then be recessed to form the isolation regions26. The insulating material is recessed such that the fins24protrude from between neighboring isolation regions26, which may, at least in part, thereby delineate the fins24as active areas on the semiconductor substrate20. The insulating material may be recessed using an acceptable dry or wet etch process, such as one that is selective to the material of the insulating material. Further, top surfaces of the isolation regions26may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof, which may result from an etch process. As illustrated in the top view ofFIG.3B, the fins24extend longitudinally across the semiconductor substrate20. The fins24may have a height in a range from about 30 nm to about 50 nm from top surfaces of respective neighboring isolation regions26. For example, the interface between the stressed semiconductor layer22and the semiconductor substrate20corresponding to each fin24can be below top surfaces of the isolation regions26.

A person having ordinary skill in the art will readily understand that the processes described with respect toFIGS.1through3A-B are just examples of how fins24may be formed. In other embodiments, a dielectric layer can be formed over a top surface of the semiconductor substrate20; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches (e.g., without stress engineering); and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still other embodiments, heteroepitaxial structures can be used for the fins. For example, the fins24can be recessed (e.g., after planarizing the insulating material of the isolation regions26and before recessing the insulating material), and a material different from the fins may be epitaxially grown in their place. In an even further embodiment, a dielectric layer can be formed over a top surface of the semiconductor substrate20; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the semiconductor substrate20(e.g., with stress engineering); and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in situ doped during growth, which may obviate prior implanting of the fins although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material for an n-type device different from the material in for a p-type device.

FIGS.4A,4B,4C and4Dillustrate the formation of dummy gate stacks on the fins24.FIGS.4A and4Billustrate cross-sectional views;FIG.4Cillustrates a top view; andFIG.4Dillustrates a perspective view.FIG.4Dillustrates cross-sections A-A and B-B.FIGS.1,2,3A,4A, and the following figures (up toFIGS.8A-C) ending with an “A” designation illustrate cross-sectional views at various instances of processing corresponding to cross-section A-A, andFIG.4Band the following figures (up toFIGS.8A-C) ending with a “B” designation illustrate cross-sectional views at various instances of processing corresponding to cross-section B-B. In some figures, some reference numbers of components or features illustrated therein may be omitted to avoid obscuring other components or features; this is for case of depicting the figures.

The dummy gate stacks are over and extend laterally perpendicularly to the fins24. Each dummy gate stack, or more generally, gate structure, includes one or more interfacial dielectrics28, a dummy gate30, and a mask32. The one or more interfacial dielectrics28, dummy gates30, and mask32for the dummy gate stacks may be formed by sequentially forming respective layers, and then patterning those layers into the dummy gate stacks. For example, a layer for the one or more interfacial dielectrics28may include or be silicon oxide, silicon nitride, the like, or multilayers thereof, and may be thermally and/or chemically grown on the fins24, as illustrated, or conformally deposited, such as by plasma-enhanced CVD (PECVD), ALD, or another deposition technique. A layer for the dummy gates30may include or be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique. A layer for the mask32may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique. The layers for the mask32, dummy gates30, and one or more interfacial dielectrics28may then be patterned, for example, using photolithography and one or more etch processes, like described above, to form the mask32, dummy gate30, and one or more interfacial dielectrics28for each dummy gate stack.

In some embodiments, after forming the dummy gate stacks, lightly doped drain (LDD) regions (not specifically illustrated) may be formed in the fins24. For example, dopants may be implanted into the fins24using the dummy gate stacks as masks. Example dopants for the LDD regions can include or be, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. The LDD regions may have a dopant concentration in a range from about 1015cm−3to about 1017cm−3.

The cross-section A-A is along a gate stack through which a cut will be made in subsequent figures and description. The cross-section B-B is along a fin24(e.g., along a channel direction in the fin24) through which a cut will be made in subsequent figures and description. Cross-sections A-A and B-B are perpendicular to each other.

FIGS.5A,5B, and5Cillustrate the formation of gate spacers34. Gate spacers34are formed along sidewalls of the dummy gate stacks (e.g., sidewalls of the one or more interfacial dielectrics28, dummy gates30, and masks32) and over the fins24. Additionally, residual gate spacers34may be formed along exposed sidewalls of the fins24, as illustrated in the figures. The gate spacers34may be formed by conformally depositing one or more layers for the gate spacers34and anisotropically etching the one or more layers, for example. The one or more layers for the gate spacers34may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbide, the like, multi-layers thereof, or a combination thereof, and the etch process can include a RIE, NBE, or another etch process.

Epitaxy source/drain regions36are then formed in the fins24. Recesses for epitaxy source/drain regions36are formed in the fins24on opposing sides of the dummy gate stacks. The recessing can be by an etch process. The etch process can be isotropic or anisotropic, or further, may be selective with respect to one or more crystalline planes of the stressed semiconductor layer22and/or semiconductor substrate20. Hence, the recesses can have various cross-sectional profiles based on the etch process implemented. The etch process may be a dry etch process, such as a RIE, NBE, or the like, or a wet etch process, such as using tetramethyalammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or another etchant. The recesses may extend to a depth in a range from about 0 nm to about 80 nm from respective top surfaces of the fins24into the fins24. For example, the recesses may, in some instances, not extend below a level of top surfaces of neighboring isolation regions26and/or below the interface between the stressed semiconductor layer22and the semiconductor substrate20; although in other instances, the recesses may extend below a level of top surfaces of neighboring isolation regions26and/or the interface.

Epitaxy source/drain regions36are formed in the recesses in the fins24. The epitaxy source/drain regions36may include or be silicon germanium (Si1-xGex, where x can be between approximately 0 and 100), silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. The epitaxy source/drain regions36may be formed in the recesses by epitaxially growing a material in the recesses, such as by MOCVD, MBE, LPE, VPE, SEG, the like, or a combination thereof. Due to blocking by the isolation regions26and/or residual gate spacers34depending on the depth of the recess in which the epitaxy source/drain region36is formed, epitaxy source/drain regions36may be first grown vertically in recesses, during which time the epitaxy source/drain regions36do not grow horizontally. After the recesses within the isolation regions26and/or residual gate spacers34are fully filled, the epitaxy source/drain regions36may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the semiconductor substrate20. Epitaxy source/drain regions36may be raised in relation to the fin24, as illustrated by dashed lines inFIG.5B. In some examples, different materials are used for epitaxy source/drain regions for p-type devices and n-type devices. Appropriate masking during the recessing or epitaxial growth may permit different materials to be used in different devices. In this disclosure, a source region and a drain region are interchangeably used, and the structures thereof are substantially the same. Furthermore, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

The CESL38and ILD40are formed with top surfaces coplanar with top surfaces of the dummy gates30. A planarization process, such as a CMP, may be performed to level the top surfaces of the ILD40and CESL38with the top surfaces of the dummy gates30. The CMP may also remove the mask32(and, in some instances, upper portions of the gate spacers34) on the dummy gates30. Accordingly, top surfaces of the dummy gates30are exposed through the ILD40and CESL38.

FIGS.7A,7B, and7Cillustrate the removal of the dummy gate stacks. The dummy gates30and one or more interfacial dielectrics28are removed, such as by one or more etch processes. The dummy gates30may be removed by an etch process selective to the dummy gates30, wherein the one or more interfacial dielectrics28act as ESLs, and subsequently, the one or more interfacial dielectrics28can be removed by a different etch process selective to the one or more interfacial dielectrics28. The etch processes can be, for example, a RIE, NBE, a wet etch process, or another etch process. Recesses42are formed between gate spacers34where the dummy gate stacks are removed, and channel regions of the fins24are exposed through the recesses42. In some embodiments, the interfacial dielectrics28are not removed.

FIGS.8A,8B, and8Cillustrate the formation of replacement gate structures in the recesses42. The replacement gate structures each include a gate dielectric layer44, one or more optional conformal layers46, and a gate electrode48.

The gate dielectric layer44is conformally deposited in the recesses42(e.g., on top surfaces of the isolation regions26, sidewalls and top surfaces of the fins24(or the interfacial dielectrics28if not removed) along the channel regions, and sidewalls of the gate spacers34) and on the top surfaces of the gate spacers34, the CESL38, and ILD40. The gate dielectric layer44can be or include silicon oxide, silicon nitride, a high-k dielectric material, multilayers thereof, or other dielectric material. A high-k dielectric material may have a k value greater than about 7.0, and may include a metal oxide of or a metal silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), multilayers thereof, or a combination thereof. The gate dielectric layer44can be deposited by ALD, PECVD, MBD, or another deposition technique.

Then, the one or more optional conformal layers46can be conformally (and sequentially, if more than one) deposited on the gate dielectric layer44. The one or more optional conformal layers46can include one or more work-function tuning layers. The one or more work-function tuning layer may include or be a nitride, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide, and/or aluminum carbide of titanium and/or tantalum; a carbide of tungsten; cobalt; platinum; the like; or a combination thereof; and may be deposited by ALD, PECVD, MBD, or another deposition technique.

A layer for the gate electrodes48is formed over the gate dielectric layer44and, if implemented, the one or more optional conformal layers46. The layer for the gate electrodes48can fill remaining recesses42where the dummy gate stacks were removed. The layer for the gate electrodes48may be or include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multi-layers thereof, a combination thereof, or the like. The layer for the gate electrodes48can be deposited by ALD, PECVD, MBD, PVD, or another deposition technique.

Portions of the layer for the gate electrodes48, one or more optional conformal layers46, and gate dielectric layer44above the top surfaces of the ILD40, CESL38, and gate spacers34are removed. For example, a planarization process, like a CMP, may remove the portions of the layer for the gate electrodes48, one or more optional conformal layers46, and gate dielectric layer44above the top surfaces of the ILD40, CESL38, and gate spacers34. Each replacement gate structure including the gate electrode48, one or more optional conformal layers46, and gate dielectric layer44may therefore be formed as illustrated inFIG.8A-C.

FIG.9shows a pulsing scheme for the process of etching the gate electrode48, andFIGS.10-13are cross-sectional views at various instances of processing corresponding to cross-section A-A inFIG.4D, in accordance with some embodiments. InFIG.10, a mask structure52is formed on the gate electrodes48. The mask structure52may also be formed on the ILD40. The mask structure52includes one or more layers54,56,58. In some embodiments, the layer54includes SiN, the layer56includes amorphous silicon, and the layer58includes SiN. The mask structure52may include more or less layers. The mask structure52is patterned with one or more openings60to expose portions of the gate electrodes48. In some embodiments, as shown inFIG.10, a hard mask layer59, for example, a SiN layer, is conformally formed on the exposed surface of the gate electrode48and the sidewall of the mask structure52exposed within the opening60.

An etching process is performed to remove the gate electrode48within the opening60. The hard mask layer59and a portion of the mask structure52may also be removed by the etching process. As shown inFIG.11, the etching process extends the opening60to or slightly below the bottom of the remaining gate electrode48. The profile of the extended portion60mof the opening60may affect the subsequent processes. For example, if the extended portion60mhas a bowling profile, a large void may exist in a refill material formed subsequently in the opening60. The existence of the large void within the refill material may cause some portions of the refill material as thin as weak points. The weak points not only result in a poor isolation between metal gates, but may also be punched through to cause missing metal gate in the continuous cut-metal on oxide definition edge (CMODE) process performed subsequently. The poor isolation and the missing metal gate may degrade the device performance and result in low yield.

According to some embodiments, a combination of a main etch step and a breakthrough (BT) etch step are provided to etch the gate electrode with a desired profile that minimizes the size of a void, if any, within the dielectric layer that refills the opening. The main etch step may be performed using a mixture of etching gases, including SiCl4, BCl3, N2. Cl2, and He with a processing pressure of about 20 mTorr. The processing pressure may be adjusted by a value ranging from about −20 mTorr to about 20 mTorr. A plasma source, for example, a transformer coupled plasma (TCP), may be used to generate ions from the gas mixture. The TCP power may be controlled within a range from about 1500 W to about 2500 W. In some embodiments, the TCP power may be controlled at about 2000 W. A bias power is also applied to pull the ions towards the gate electrodes48. It has been observed that the etching angle with respect to a vertical line is dependent on the frequency of the bias power. That is, by selecting an appropriate frequency, the ratio of the lateral etching to the vertical etching may be controlled, such that a predetermined profile of the opening60mextending through the gate electrode48may be obtained. According to some embodiments, the bias power with a frequency of about 1 MHz is applied to control lateral etch on the gate electrode48as shown by the horizontal arrows inFIG.11.

FIG.9shows a pulsing scheme of the TCP power and the bias power of the main etch step for etching the gate electrode48according to some embodiments. The TCP power has an 80% duty cycle (DC) at a power level of about 2000 W. That is, the TCP power is controlled at a power level of about 2000 W for 80% of the time in each period and switched off (0 W) for the remaining time, that is, 20% of the time, in each period. The power level may be adjusted by a value ranging from +500 W to about −500 W according to some embodiments. The bias power also has an 80% duty cycle. That is, the bias power is switched on for 80% of the time in each period and switched off for 20% of the time in each period. However, the voltage level of the bias power for the first 30% is controlled at about 200 V, while the voltage level drops to about 50 V for the following 50% in each period. Each voltage level may be adjusted with a voltage value ranging from about +50 V to about −50V. In some embodiments, the voltage for the following 50% in each period ranges from about 5 V to about 100V. The 30% duty cycle may be adjusted with a percentage ranging from about +30% to about −30%, while the 50% duty cycle may be adjusted with a percentage ranging from about +40% to about −40%. The off cycle may also be adjusted with a percentage ranging from about +20% to about −20%. The parameters of the plasma etching process for etching the gate electrode48are listed in Table I presented below.

The main etch step with the pulsing scheme as shown inFIG.9and the etching conditions as shown in Table I provide a control of substantially lateral etch as indicated by the horizontal arrows as shown inFIG.11. The gate electrode48is etched with a tapered profile that has a gradually decreasing cross section from a top to a bottom.

InFIG.12, the opening60is further extended by etching through the isolation region26and a top portion of the substrate20. The bottom portion60bextending through the isolation region26and the top portion of the substrate20may be formed by an etching process using a gas mixture of C4F6, O2, and N2under a pressure of about 20 mTorr±20 mTorr. The source power may be controlled with a power level of about 100 W, and a 1000 V bias power with a frequency of about 13.5 MHz may also be applied.

InFIG.12, the sidewall61of the mask structure52exposed to the top portion60tof the opening60may have a substantially straight portion61aand a slant portion61b. In some embodiments, an angle A is formed between a side surface of the layer54exposed to the top portion60tof the opening60and a bottom surface of the layer54disposed on the gate electrode48, and the angle A ranges from about 80 degrees to about 90 degrees. In some embodiments, an angle B is formed between a side surface of the layer58exposed to the top portion60tof the opening60and a top surface of the layer58, and the angle B ranges from about 100 degrees to about 120 degrees. A sharp corner may be formed at where the substantially straight portion61aand the slant portion61bmeet. The sharp corner may hinder the flow of material to refill the opening60subsequently. In addition, the sharp corner may cause the refill material to merge at the top portion60tbefore the middle portion60mand the bottom portion60bare filled completely. Similar to the bowling profile of the middle portion60m, the sharp corner may cause the formation or further enlarge a large void within the refill material. Therefore, according to some embodiments, an additional etch step is performed after the opening60has extended into the substrate20. The additional etch step may be referred to as a final breakthrough (BT) etch step for fine tuning the profile of the opening60.

FIG.13shows a pulsing scheme used for performing the final BT etch step, andFIGS.14-17are cross-sectional views at various instances of processing corresponding to cross-section A-A inFIG.4D, in accordance with some embodiments. The final BT step may be a plasma etching process with an always-on source power at a power level of about 100 W. That is, the source power has a 100% duty cycle at a lower level of about 100 W. The power level may be adjusted by a value ranging from about +100 W to about −100 W. In some embodiments, the power level ranges from about 10 W to about 200 W. According to some embodiments, the bias power has a frequency of about 13.5 MHz and a 50% duty cycle at a power level of about 500 V. That is, the bias power is switched on to a voltage level of about 500 V for 50% of the time in each period and switched off for 50% of the time in each period. The power level may be adjusted with a value ranging from about +300 V to about −300V. In some embodiments, the power level ranges from about 200 V to about 800 V. The etching gas may include a mixture of C4F6, O2, and Ar. A pressure of about 20 mTorr±20 mTorr may be applied. The etching parameters may be controlled according to Table II presented below.

As listed in Table II, the TCP power is controlled at a power level around 100 W, and the frequency of the bias power is around 13.5 MHZ. It can be expected that the ions may stay at the top portion60tof the opening60to etch the sidewall of the mask structure52along a substantially vertical direction as shown by the arrows as shown inFIG.14. The parameters illustrated in Table II allow ions created by the TCP power to locate at the top portion60tto widen and smooth the sidewall of mask structure52within the top portion60tof the opening60without further laterally etching the gate electrode48and the isolation regions26. As a result, the sharp corner in the sidewall61may be removed, and a substantially linear slant sidewall61of the mask structure52exposed to the top portion60tis formed. The substantially linear sidewall61provides an overall funnel profile of the opening60. In some embodiments, the angle A is substantially decreased by the final BT etch step, and the angle B is substantially enlarged by the final BT etch step. In some embodiments, the angle A after the final BT etch step ranges from about 30 degrees to about 60 degrees, and the angle B after the final B ranges from about 140 degrees to about 170 degrees. The final BT etch step modifies the profile of the mask structure52without substantially affect the gate electrode48. The final BT etch step is performed after the formation of the bottom portion60bof the opening60in order to protect the gate electrode48. If the final BT etch step is performed before the etch process to form the bottom portion60bof the opening60, the etch process to form the bottom portion60bof the opening60may remove portions of the mask structure52, which are thinner as a result of the final BT etch step, and damage the gate electrode48and/or unnecessarily enlarge the critical dimension of the opening60in the gate electrode48.

As shown inFIG.15, the combination of the main etching step for removing the gate electrode48and the final BT etching step result in a funnel profile of the opening60. The top critical dimension (TCD) “a” at the top of the metal gate, that is, the patterned gate electrode48, is larger than the middle critical dimension (MCD) “b” at the top level of the fins24. In some embodiments, the difference between TCD and MCD, that is, “a-b” may be improved from the range of −4 nm to −1 nm to range of −1 nm to 1 nm with the main etching process using the pulsing scheme as shown inFIG.9and the etching condition listed in Table I. In combination with the final BT etch step, the difference may be further improved to the range of 1 nm to 4 nm.

As shown inFIG.16, a dielectric material64is formed in the opening60. The dielectric material64may be any suitable dielectric material, such as SiN. The gapfill capability of the dielectric material64is poor in the high aspect ratio opening60, and a void66may be formed in the dielectric material64. In some embodiments, the void66has a dimension greater than about 1 nm. As discussed above, the funnel profile of the opening60resulted from the main etching step of the gate electrode48and the final BT etch step improves refill of the dielectric material64and thus minimizes the size of the void66. For example, the width of void66may be reduced to less than 1 nm according to some embodiments.

FIG.17shows the device after performing the CMODE process. As the size of the void66has been minimized, the dielectric layer64has a sufficient thickness to provide a good isolation between metal gates. There is no weak point to be punched by CMODE process. Therefore, the missing metal gate is prevented. A higher yield and improved device performance can thus be expected.

Embodiments of the present disclosure provide a method to form an opening60in a mask structure52and a gate electrode48. In some embodiments, the method includes a main etch step and a final BT step. Some embodiments may achieve advantages. For example, the process conditions of the main etch step prevents bowling of the opening60in the gate electrode48, while the final BT step enlarges the portion of the opening60in the mask structure52. As a result, the dielectric layer64formed in the opening60includes a void66with reduced size.

An embodiment is a method. The method includes forming a gate electrode, forming a mask structure over the gate electrode, patterning the mask structure to form an opening, and performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme. The first bias power has a first frequency to control etching along a lateral direction. The method further includes performing a second etch process on the mask structure exposed within the opening by applying a second source power and a second bias power with a second pulsing scheme, and the second bias power has a second frequency to control etching along a vertical direction. The first and second frequencies are substantially different.

Another embodiment is a method. The method includes a first etch process performed on a gate electrode. The first etch process includes a plasma etch process with a first source power with an 80% duty cycle at a power level ranging from about 1500 W to about 2500 W, and a first bias power with a 30% duty cycle at a voltage level ranging from about 150 V to about 250 V and 50% duty cycle at a voltage level ranging from about 5 V to about 100 V immediately following the 30% duty cycle. The method further includes a second etch process performed on a mask structure disposed on the gate electrode. The second etch process includes a plasma etch process with a second source power with a 100% duty cycle at a power level ranging from about 10 W to about 200 W, and a second bias power with a 50% duty cycle at a voltage level ranging from about 200 V to about 800 V.

A further embodiment is a method. The method includes forming a plurality of fins from a semiconductor substrate, forming isolation regions around each fin of the plurality of fins, depositing a gate electrode over the plurality of fins, forming a mask structure over the gate electrode, forming an opening in the mask structure, extending the opening through the gate electrode by a first plasma etch process with a first bias power having a frequency to control a lateral etch of the gate electrode, extending the opening through the isolation region, etching a sidewall of the mask structure within the opening by a second plasma etch process with a second bias power having a frequency to control a vertical etch of the mask structure and to remove a sharp corner in the sidewall of the mask structure exposed to the opening, and filling the opening with a dielectric layer.