Content addressable memories with wireline compensation

What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of the group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2 . . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated.

FIELD OF THE INVENTION

The present invention generally relates to design of memory arrays and, more specifically, to wireline routing from cells of the memory array to peripheral circuitry.

BACKGROUND OF THE INVENTION

Memory arrays include content addressable memory (CAM) used for high performance data search in computers. Most CAM devices utilize static random access memory (SRAM) as data storage devices (utilizing transistors to store information), and additional transistors and complementary transistors for search operations. Often in these CAM devices, search-line access elements and word-line access elements are necessary to operate and program individual memory cells in the memory arrays. These search-line access elements and word-line access elements are often comprised of power intensive, large drive field effect transistors (FET's).

Phase change material can also be utilized to store information for CAM devices. Information is stored in materials that can be manipulated into different phases. Each of these phases exhibits different electrical properties that can be used for storing information.

Chalcogenides are a group of materials commonly utilized as phase change material. They typically contain a chalcogen (Periodic Table Group 16/VIA) and a more electropositive element. Selenium (Se) and tellurium (Te) are the two most common semiconductors in the group used to produce a chalcogenide when creating a phase change memory cell. An example of this is Ge2Sb22Te5(GST), SbTe, and In2Se3. However, some phase change materials do not utilize chalcogen, such as GeSb. Thus, a variety of materials can be used in a phase change memory cell.

Phase change memory (PCM) technology has lead to increased density enhancements in TCAM/CAM. In search operation, reference match line (ML) timing using resistive-capacitive (RC) sensing schemes is employed to differentiate the search results of “matching”, “non-matching”, and “don't care”. However, RC based sensing schemes are very sensitive to non-idealities, including resistance variability and capacitance mismatch across the match lines.

SUMMARY OF THE INVENTION

One aspect of the invention is a novel method for reducing wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. In one example, the routing design of the memory includes a total area constraint (A) of additional routing lines available. Each memory cell in the array includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). The group of wires is divided into at least one subgroup (N). Next, a capacitance (C1, C2. . . CN) of each wire in the subgroup (N) is calculated. Continuing further, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated. This add-on capacitance is calculated to minimize a difference between the maximum capacitance (CMAX) and a compensated wire capacitance defined as the add-on capacitance plus the capacitance of each wire (C1, C2. . . CN)) to maximize NA, with NA≦N. In an example, where the total area constraint (A) of the additional routing lines available is considered, calculating the area of the add-on capacitance to be added is not greater than the total area constraint (≦A).

Another aspect of the invention is a novel memory array. The memory array includes a plurality of memory cells, with each memory cell including one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). Selected from the group of wires is at least one subgroup (N) of wires. A group of compensation wires is added to the subgroup of wires (N), and electrically connected between one or more of the memory cells and the peripheral circuitry (PC). The group of compensation wires includes an add-on capacitance added to a number (NA) of the wires in the subgroup (N) in order to minimize a difference between the maximum capacitance (CMAX) and a compensated wire capacitance defined as the add-on capacitance plus a capacitance of each wire (C1, C2. . . CN)) in the subgroup (N) of wires to maximize NA, with NA≦N.

DETAILED DESCRIPTION

The terms “a” or “an”, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms “including” and “having” as used herein, are defined as comprising (i.e. open language). The term “coupled” as used herein, is defined as “connected” although not necessarily directly, and not necessarily mechanically. The terms bitline (BL) and matchline (ML) are used interchangeably herein. The term BL is typically used with general memory and ML used with CAM. Wireline is used to refer to physical electrical connections to the storage elements used with CAMs such as bitlines (BL) and matchlines (ML).

The present invention provides efficient wireline compensation techniques that reduce timing uncertainties. This improved wireline compensation works well with higher density TCAM/CAM that use resistive-capacitive (RC) sensing schemes. Specifically, the present invention improves the sensing margin in RC-based sensing schemes whether due to phase change memory (PCM) variability, such as variability in resistance (R), and/or matchline (ML) variability, in which capacitance (C) variability is often the dominating factor. The present invention reduces the resistance-capacitance (RC) variability of matchlines (ML). Although examples are directed to CAMS and TCAMS including phase change memory (PCM) TCAM/CAMS, other examples include applying the methods and layouts to other types of memory cells, as well. Further, the wireline compensation method in these examples can be applied to any system with a large number of peripheral driver circuitry and small area of array size. The spacing between metal lines can be adjusted to trade off between coupling and number of matchlines/bitlines to be compensated.

Higher density TCAM/CAM that use resistive-capacitive RC sensing schemes do not share sense amplifier across cells and this leads to wiring challenges and ML capacitance mismatch. ML capacitance mismatch results in timing uncertainty which degrades the sensing accuracy. The present invention mitigates these problems through an efficient wireline compensation technique.

As described in detail below, one example of the current invention is a ternary content addressable memory device for searching ternary data words. Each data bit in a data word is settable to one of three values of a first binary value (i.e., a “0” or low value), a second binary value (i.e., a “1” or high value), and a don't care value (i.e., a “X” value). The ternary content addressable memory device is comprised of a pair of two memory cells. Each individual memory cell includes a memory element and an access device electrically coupled in series with the memory element. Additionally, each memory cell is electrically coupled to a respective word line (WL) and a common match line (ML). In a particular configuration of the invention, the memory elements are phase change elements comprised of a phase change material, such as Germanium-Antimony-Tellurium (GST) and electrical contact electrode. In one particular embodiment of the invention, the memory elements may be programmed to one of two states: a low resistance state and a high resistance state. The combination of data stored in the pair of two memory cells in each TCAM cell represents one of the three data bit values. For example, high resistance state in both memory cells in each TCAM cell represent the don't care value, the high resistance state in one cell while the low resistance state in the other cell represents the first (high) binary value, and reversely, the low resistance state in one cell while the high resistance state in the other cell represents the second (low) binary value.

SRAM Binary CAM

FIG. 1shows a two elements of a typical SRAM based ternary CAM cell110. The term CAM cell is used to mean two elements of the ternary CAM cell. The identical description with reference to “Element1” is applicable to “Element2”, as well. “Element1” and “Element2” together form, with the appropriate access circuitry, a ternary CAM cell. The ternary CAM cell stores one of three binary values for CAM operations, logical “0”, logical “1”, or “X” for “don't care”. Returning to “Element1”, two inverters INV1and INV2form a latch that stores the true and complementary data on nodes N1and N2. In the write mode, data is written into CAM cells through complementary writebitlines WBL1,WBL1through N-type metal oxide semiconductor (NMOS) transistor T1and T2. In the precharge phase of the search mode, matchline (ML) is precharged to high. In the evaluation phase of the search mode, input data presented to the CAM are delivered to the CAM cells through selectline1(SL1) and selectline2(SL2).

When there is a match, the two gates in the path of T3and T4will have different polarity, so that one of the transistors in each path will be off. Thus, there is no current flowing between the match-line and ground line also know as a sink-line through a matched CAM cell.

On the other hand, when there is a mismatch, one of the two paths will have both transistors turned on and allow current flowing between the match-line (ML) and sink-line (not shown). Sink-line (not shown) is normally connected to ground and thus will discharge the match-line when a mismatch occurs. In an example of a 16 bit wide CAM, each match-line is connected to all sixteen CAM cells110. When any of the CAM cells shows a mismatch, the match-line will be discharged quickly. If all cells match, the match-line will stay at high level and a match is found.

A CAM with SRAM as described above is now expanded to include a phase-change memory based ternary content addressable memory (PCM-TCAM), an array of PCM-TCAM cells, and peripheral circuits for the content addressable memory (CAM) operation, and for the random access memory (RAM) operation.

PCM Binary CAM

FIG. 2shows a typical implementation of a phase change memory (PCM) cell200. The PCM cell includes selectline1/writewordline (SSL1/WWL)240, selectline2/writewordline (SSL2/WWL)242, and matchline/writebitline (ML/WBL)210,212. Each PCM cell includes: (1) a phase change memory element220,222, represented by a circle, with one end connected to matchline/writebitline (ML/WBL)210; (2) a n-type field effect transistor (nFET)230,232that has its gate connected to the selectline/writewordlines (SSL1/WWL, SSL2/WWL)240,242and its source and drain connected to GND210and the phase change material220,222, respectively. The ternary CAM cell stores one of three binary values for CAM operations, logical “0”, logical “1”, or “X” for “don't care”.

The PCM TCAM cell200stores a ternary data value as one of three states. For example, high resistance state in both memory cells in each PCM-CAM cell200represent the don't care value, the high resistance state in one cell while the low resistance state in the other cell represents the first (high) binary value, and reversely, the low resistance state in one cell while the high resistance state in the other cell represents the second (low) binary value. During programming operations, voltage pulses are applied to the matchline/writebitline (ML\WBL)210,212and selectline/writewordlines (SSL1/WWL, SSL2/WWL)240,242based on a target programming value. In one embodiment of the invention, the voltage pulse applied to matchline/writebitline (ML\WBL)210,212is high enough to change the phase change elements to an amorphous state (high resistance). One of the wordlines (SL1/WWL, SL2/WWL)240,242is biased to turn on one of the access devices230,232. A suitable current or voltage pulse is then applied to the matchline/writebitline (ML\WBL)210,212to program one of the memory elements220,222to the desired resistance state.

CAM Sensing Circuit

FIG. 3is a block diagram of sensing circuitry coupled to a TCAM array with a plurality of TCAM cells. During search operations, a search bit is compared with the stored data bit. The search data is applied to the selectlines (SSL1, SSL2)312. The matchline330senses the collective effective resistance (Element1, Element2) of a plurality of memory cells such as PCM cell200ofFIG. 2or cell110ofFIG. 1. In one embodiment of the invention, the matchline330, senses the voltage decay454of the matchlines introduced by discharge current passing through the memory cell (Element1, Element2) and access device, such as230,232ofFIG. 2. A group of latches340stores the value of the match lines in accordance with the timing pulse CLK (S/A Timing Signal)352,424. Latches are triggered by reference CLK to differentiate match/no-match time delay. The final latch value forms the search output360.

FIG. 4is a waveform of a sensing circuitry ofFIG. 3. The clock452is shown as wave form402. The voltage of matchline (ML)454is shown. Notice the two slopes412(no match case) and414(match case) show different voltage discharge rate due to different RC constant of matchline. The Vtrip418illustrates the trigger voltage of SA's. The wave form420of search output (SAout)460also illustrates two slopes422(no match case) and424(match case) illustrating the small sense margin in time-based TCAM sensing schemes due to resistance and capacitance mismatch largely because of variabilities in the matchlines. TCAM have small sense margins because of parallel wiring paths and poor array efficiency. This wireline mismatch is due to different metal lengths and manufacturing variability.

FIG. 5illustrates match line capacitance mismatching. Shown is a block diagram of matchline (ML) capacitance coupling502. Diagrammatically, this is shown as MLN−1, MLN, MLN+1to represent the wires electrically coupled to each other. The wireline or ML wiring has two major components as shown in the wire routing510, the wiring as part of the array506and the wiring as part of the periphery508that contributes to a large overall capacitance difference. Even assuming approximately equal capacitance for each ML in the array506there is ML-ML coupling. In this example, the wire routing is divided into subgroups of N wires. Other subgroups of any other number of wires are possible in other examples. Notice in this group the various lengths of wires in periphery508in the wire routing. For example, the longest matchline (ML) in a subgroup N may have a capacitance that is more than twice that of the shortest matchline (ML) in the subgroup N. Each square inFIG. 5-7indicates a separate SA circuit attached to each ML.

Wireline Compensation

FIG. 6illustrates a model600of the matchline wireline compensation. In this, model600wireline compensation is achieved by making the capacitance loading identical for each by adding wire to it. Stated differently, a small or short ML capacitance (CML) would have a longer add-on capacitance, whereas a longer CMLhas a short add-on capacitance. A subgroup of wires N is shown in this model600. The lower portion of each wire in the subgroup denoted602illustrate wirelines with different capacitances (before compensation) with a maximum capacitance CMAX610. Continuing with this model600, add-on capacitance to be added is denoted604. In this model600, the add-on capacitance604to be added to a number (NA) of the wires in the subgroup (N) is calculated in order to minimize a difference between the maximum capacitance (CMAX) and a compensated wire capacitance to maximize the number of wires added NA, with NA≦N. The compensated wire capacitance is the add-on capacitance plus the capacitance of each wire (C1, C2. . . CN). Notice in this example there is no wire added to wire N−1 denoted640. This is because wire N−1 already has a capacitance close to CMAXand the number of additional routing lines in most memory array architectures is limited.

FIG. 7illustrates match line wireline compensation with a ground wire using the compensation model600ofFIG. 6. The ground wire electrically isolates the neighboring compensated wirelines to ensure no additional coupling capacitance introduced to each matchline while doing compensation.

Again, the wireline or ML wiring has two major components, denoted as CMLrepresenting the capacitance of the matchline and CPCrepresenting the capacitance of the peripheral circuitry. Wireline compensation is achieved by making the capacitance loading identical for each by adding wire to it. Stated differently, a small or short ML capacitance (CML) would have a longer addi-oncapacitance, whereas a longer CMLhas a short add-on capacitance. The original ML wire and compensating wire are shown schematically702and704. The ML capacitance (CML)702is compensated by adding lump capacitance through a different manufacturing layer(s)704. The compensating capacitance704is designed in order to effectively minimize ML capacitance mismatch and to minimize additional coupling. In this example, the compensating wires comprise a GND shield line added between each ML as shown schematically in704.

In examples with ground shield wires being added as part of the compensation in order to reduce coupling, the ground shield wires may have different pitches. ML spacing (XS) or width of each matchline is shown. The area of each matchline is used to calculate a capacitance (C1, C2. . . Cn) of each wire in the subgroup. A total area of each wire in the subgroup (A1+A2. . . An) is calculated to estimate the total area constraint for compensating wires in a subgroup known from the routing design.

The coupling capacitance is a function of wire space in each subgroup.
Max(CTOTAL)=Max(CML+CPC)≦CMAX

where

CML is first part of matchline capacitance in memory array;

CPC is second part of matchline capacitance in peripheral circuit;

CMAX is target maximum capacitance of a wire in the subgroup (N) after compensation.

FIG. 8illustrates match line wireline compensation without a ground wire using the compensation model600ofFIG. 6. In one embodiment, wireline compensation is achieved by making the capacitance loading identical for each by adding wire to it. Stated differently, a small or short ML capacitance (CML) would have a longer compensating capacitance, whereas a longer CMLhas a short compensating capacitance.

Compensation Process Flow

FIGS. 9-10is a flow diagram of the wireline compensation method using the compensation model600ofFIG. 6. The flow minimizing timing uncertainty in memory arrays by compensating for wireline variations and by minimizing capacitance mismatch. The process flow900begins at step902and immediately proceeds to step904in which a routing design of a memory array with a plurality of memory cells is accessed. Each memory cell includes one or more access devices, and a group of wires electrically connected between one or more of the memory cells and peripheral circuitry (PC). Next in step906, the group of metallic wires is divided into at least one subgroup (N). For each wire in the subgroup a capacitance (C1, C2. . . CN) is calculated in step908. In step912, a maximum capacitance (CMAX) of wires in the subgroup (N) is determined. An add-on capacitance to be added to a number (NA) of the wires in the subgroup (N) is calculated. More specifically, the add-on capacitance is calculated in order to minimize a difference between the maximum capacitance (CMAX) and a compensated wire capacitance defined as the add-on capacitance plus the capacitance of each wire (C1, C2. . . CN) to maximize the number (NA) of wires in the subgroup. The number of wires (NA) is less than or equal to a number of wires in the subgroup (≦N). A routing design in step914is updated to include the additional wires connected between one or more of the memory cells and the periphery circuit (PC). A test is made in step916, if all subgroups (N) are complete. In this case, no other subgroups need to be compensated and the process returns to step910. Otherwise, the process terminates in step918.

Example Design Process

The embodiments of the present invention described above are meant to be illustrative of the principles of the present invention. These device fabrication processes are compatible with conventional semiconductor fabrication methodology, and thus various modifications and adaptations can be made by one of ordinary skill in the art. All such modifications still fall within the scope of the present invention. For example, the various layer thicknesses, material types, deposition techniques, and the like discussed above are not meant to be limiting.

Furthermore, some of the features of the examples of the present invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples and exemplary embodiments of the present invention, and not in limitation thereof.

FIG. 11shows a block diagram of an exemplary design flow1100used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow1100includes processes and mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown inFIGS. 1-1. The design structures processed and/or generated by design flow1100may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Design flow1100may vary depending on the type of representation being designed. For example, a design flow1100for building an application specific IC (ASIC) may differ from a design flow1100for designing a standard component or from a design flow1100for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

FIG. 11illustrates multiple such design structures including an input design structure1120that is preferably processed by a design process1110. Design structure1120may be a logical simulation design structure generated and processed by design process1110to produce a logically equivalent functional representation of a hardware device. Design structure1120may also or alternatively comprise data and/or program instructions that when processed by design process1110, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure1120may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure1120may be accessed and processed by one or more hardware and/or software modules within design process1110to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those described in the figures above. As such, design structure1120may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL), design entities, or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process1110may include hardware and software modules for processing a variety of input data structure types including netlist1180. Such data structure types may reside, for example, within library elements1130and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications1140, characterization data1150, verification data1160, design rules1170, and test data files1185which may include input test patterns, output test results, and other testing information. Design process1110may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process1110without deviating from the scope and spirit of the invention. Design process1110may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

Design structure1190may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g., information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure1190may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown inFIGS. 6-11. Design structure1190may then proceed to a stage1195where, for example, design structure1190: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.