Fast transient load response device for switched-mode power supply

This specification discloses methods and systems for reducing negative undershoot during transient load response for a PWM (Pulse Width Modulation) boost power converter. In some embodiments, reduction of negative undershoot during transient load response is achieved by overriding the PWM duty cycle to a maximum duty cycle when VDDBOOST drops during load step. This maximum duty cycle (“max”) mode is triggered when VDDBOOST is within a hysteresis window. Setpoint for maximum duty cycle is versus DCDC converter output and input voltage. In some embodiments, a lookup table is implemented for determining the setpoint for maximum duty cycle.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to European Patent Application No. 18305587.0, filed on May 14, 2018, the contents of which are incorporated by reference herein.

FIELD

The described embodiments relate generally to methods and systems for operating a switched-mode power supply (SMPS), and more particularly to methods and systems for operating a fast transient load response device for a switched-mode power supply (SMPS).

BACKGROUND

A NFC (Near Field Communication) device is an example of a communications device that communicates via inductive coupling. NFC is a short-range wireless technology that allows communication between NFC enabled objects over a distance of less than 10 cm. NFC is based on Radio Frequency Identification (RFID) standards. It is a technology that is designed to make an easier and more convenient world for us, enhancing the way we make transactions, exchange content and connect devices.

For mobile applications, a NFC device can include a NFC transmitter. The NFC transmitter can be supplied by a DCDC (or DC-to-DC) converter. For example, a DCDC converter is needed for boosting the battery voltage for higher communication distance.

Because an “NFC Device” is very useful, there are strong motivations for enhancing the performance of a DCDC converter.

SUMMARY

The present specification discloses methods and systems for reducing negative undershoot during transient load response for a PWM (Pulse Width Modulation) boost power converter. In some embodiments, reduction of negative undershoot during transient load response is achieved by overriding the PWM duty cycle to a maximum duty cycle when VDDBOOST drops during load step. This maximum duty cycle (“max”) mode is triggered when VDDBOOST is within a hysteresis window. Setpoint for maximum duty cycle is versus DCDC converter output and input voltage. In some embodiments, a lookup table is implemented for determining the setpoint for maximum duty cycle.

This disclosure is novel in providing an integrated solution for DCDC converter fast transient load response. In some embodiments, this disclosure provides for a VBATPWR-VDDBOOST lookup table. The lookup table allows for keeping DCDC stability over VBAT (battery voltage) range in case of configurable DCDC output voltage. Additionally, this disclosure also provides the following advantages: (a) no need for higher BOM (bill of materials) and PCB (printed circuit board) footprint, (b) no impact on power dissipation, and (c) no need for extra external components.

The present invention provides for a method for reducing negative undershoot during transient load response that is associated with a PWM (Pulse Width Modulation) boost power converter, the method comprising: (a) switching on a NFC (Near Field Communication) field from an off state, wherein a PWM duty cycle of the PWM boost power converter is set to a steady state value, wherein the switching on of the NFC field creates a negative undershoot during transient load response; (b) detecting when a boost voltage of the PWM boost power converter drops below a first threshold value; (c) setting the PWM duty cycle to a maximum value in response to detecting the boost voltage drop below the first threshold value, wherein the maximum value is higher than the steady state value, wherein setting the PWM duty cycle to the maximum value causes the boost voltage to rise; (d) detecting when the boost voltage rises above a second threshold value, wherein the second threshold value is higher than the first threshold value; (e) setting the PWM duty cycle back to the steady state value in response to detecting the boost voltage rise above the second threshold value, wherein setting the PWM duty cycle to the steady state value causes the boost voltage to drop; (f) continuing the above steps of changing the PWM duty cycle between the maximum value and the steady state value until the boost voltage no longer drops below the first threshold value while the PWM duty cycle is set to the steady state value.

In some embodiments, the maximum value is based on an input voltage to the PWM boost power converter and an output voltage from the PWM boost power converter.

In some embodiments, the maximum value is further based on a power efficiency associated with the PWM boost power converter.

In some embodiments, the maximum value is stored in a lookup table.

In some embodiments, the maximum value is determined by a microcontroller.

In some embodiments, the NFC field is generated by a NFC transmitter, wherein the NFC transmitter is supplied by an output from a LDO (Low-Dropout Regulator) voltage regulator, wherein the LDO voltage regulator is supplied by an output from the PWM boost power converter.

In some embodiments, the transient load response occurs during an initial NFC field on event and/or peer to peer communications.

In some embodiments, the transient load response occurs when a time period between current NFC field on event and last NFC field on event is long.

The present invention also provides for a system comprising: (a) a PWM (Pulse Width Modulation) boost power stage, the PWM boost power stage configured to provide for PWM boost power conversion, wherein the PWM boost power stage provides power for generating a NFC (Near Field Communication) field, wherein the PWM boost power stage inputs an input voltage and outputs a boost voltage; (b) a boost clock scheme, the boost clock scheme configured to provide PWM clock signal to the PWM boost power stage; (c) a voltage monitor, the voltage monitor configured to sense the boost voltage from the PWM boost power stage; (d) a microcontroller, the microcontroller configured to provide a clock reference signal to the boost clock scheme and a setpoint for the boost voltage, (e) wherein the boost clock scheme sets a PWM duty cycle of the PWM boost power stage to a steady state value, wherein switching the NFC field from an “off” state to an “on” state creates a negative undershoot associated with a transient load response, (f) wherein the voltage monitor detects when the boost voltage drops below a first threshold value, (g) wherein the boost clock scheme sets the PWM duty cycle to a maximum value in response to the voltage monitor detecting the boost voltage drop below the first threshold value, wherein the maximum value is higher than the steady state value, wherein setting the PWM duty cycle to the maximum value causes the boost voltage to rise, (h) wherein the voltage monitor detects when the boost voltage rises above a second threshold value, wherein the second threshold value is higher than the first threshold value, (i) wherein the boost clock scheme sets the PWM duty cycle back to the steady state value in response to the voltage monitor detecting the boost voltage rise above the second threshold value, wherein setting the PWM duty cycle to the steady state value causes the boost voltage to drop, (j) wherein the boost clock scheme continues the above steps of changing the PWM duty cycle between the maximum value and the steady state value until the boost voltage no longer drops below the first threshold value while the PWM duty cycle is set to the steady state value.

In some embodiments for a system, the maximum value is based on the input voltage and the boost voltage, wherein the ADC provides the input voltage and the voltage monitor provides the boost voltage.

In some embodiments for a system, the maximum value is further based on a power efficiency associated with the PWM boost power stage.

In some embodiments for a system, the system further comprising: (a) an ADC (analog-to-digital converter), the ADC configured to convert the input voltage from an analog voltage level to a digital voltage level; (b) a lookup table configured to determine the maximum value.

In some embodiments for a system, the maximum value is determined by the microcontroller.

In some embodiments for a system, the NFC field is generated by a NFC transmitter, wherein the NFC transmitter is supplied by an output from a LDO (Low-Dropout Regulator) voltage regulator, wherein the LDO voltage regulator is supplied by an output from the PWM boost power stage.

The present invention provides for a computer program product comprising executable instructions encoded in a non-transitory computer readable medium which, when executed by a system, carry out or control the following method for reducing negative undershoot during transient load response that is associated with a PWM (Pulse Width Modulation) boost power converter, the method comprising: (a) switching on a NFC (Near Field Communication) field from an off state, wherein a PWM duty cycle of the PWM boost power converter is set to a steady state value, wherein the switching on of the NFC field creates a negative undershoot during transient load response; (b) detecting when a boost voltage of the PWM boost power converter drops below a first threshold value; (c) setting the PWM duty cycle to a maximum value in response to detecting the boost voltage drop below the first threshold value, wherein the maximum value is higher than the steady state value, wherein setting the PWM duty cycle to the maximum value causes the boost voltage to rise; (d) detecting when the boost voltage rises above a second threshold value, wherein the second threshold value is higher than the first threshold value; (e) setting the PWM duty cycle back to the steady state value in response to detecting the boost voltage rise above the second threshold value, wherein setting the PWM duty cycle to the steady state value causes the boost voltage to drop; (f) continuing the above steps of changing the PWM duty cycle between the maximum value and the steady state value until the boost voltage no longer drops below the first threshold value while the PWM duty cycle is set to the steady state value.

The above summary is not intended to represent every example embodiment within the scope of the current or future Claim sets. Additional example embodiments are discussed within the Figures and Detailed Description below. Other aspects and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

As an example, to be integrated within a mobile application, a NFC (Near Field Communication) transmitter is supplied by a DCDC (or DC-to-DC) converter, and then a linear voltage regulator. A DCDC converter is needed for boosting the battery voltage for higher communication distance. A DCDC output voltage ripple is filtered with a LDO (low-dropout) voltage regulator for avoiding interference on communication.

In some embodiments, the trend for secure mobile transaction is to use an inductive DCDC converter with Pulse Width Modulation (PWM). The reason for using an inductive converter is to target for good power efficiency and low output voltage ripple. Using PWM leads to a fixed switching frequency so that there are no spurious noises within the NFC communication bandwidth.

FIG. 1shows the transmitter path of a NFC (Near Field Communication) system100that utilizes a DC-to-DC boost converter110and an LDO (low-dropout) voltage regulator120in accordance with some embodiments of the invention. In some embodiments, a part of the NFC system100can be implemented as an IC (integrated circuit) targeting the mobile market. The IC can integrate a DCDC boost converter (BOOST110), a LDO voltage regulator (VDDPA LDO120), and a NFC transmitter130. An EMC (Electromagnetic Compatibility) filter and matching filter (140) can be placed between the IC and a NFC antenna150. The NFC transmitter130can be used to generate NFC field160emanating from NFC antenna150.

InFIG. 1, NFC system100includes a DCDC boost converter110. The DCDC boost converter110can be a DC-to-DC power converter that steps up voltage (while stepping down current) from its input (supply) to its output (load). InFIG. 1, the input (supply) is VBATPWR105(e.g., battery power voltage supply). The output (load) is a stepped-up voltage VDDBOOST115(e.g., VDD (drain supply) boost voltage).

InFIG. 1, NFC system100also includes a LDO voltage regulator (VDDPA LDO120). The LDO voltage regulator (VDDPA LDO120) is a DC linear voltage regulator that can regulate the output voltage even when the supply voltage is very close to the output voltage. InFIG. 1, the supply voltage is VDDBOOST115. The output voltage is VDDPA125(e.g., VDD (drain supply) voltage for power amplifier, which is the NFC transmitter130). The advantages of a LDO (low-dropout) voltage regulator over other DC to DC regulators can include the absence of switching noise (as no switching takes place), smaller device size (as neither large inductors nor transformers are needed), and greater design simplicity (usually consists of a reference, an amplifier, and a pass element). The disadvantage is that, unlike switching regulators, linear DC regulators must dissipate power, and thus heat, across the regulation device in order to regulate the output voltage. However, here the DCDC output voltage ripple from boost converter110is filtered with a LDO (low-dropout) voltage regulator120for avoiding interference on communication.

InFIG. 1, NFC system100further includes a NFC transmitter130. The NFC transmitter130can be a power amplifier, which is an electronic device that can increase the power of a signal (a time-varying voltage or current). InFIG. 1, LDO voltage regulator120provides the supply voltage (i.e., VDDPA125, which is VDD (drain supply) voltage for power amplifier) for NFC transmitter130, which is a power amplifier. NFC transmitter130, in turn, provides the outputs TX1132and TX2134to generate the NFC field160emanating from NFC antenna150.

FIG. 2shows the boost transient response during NFC data exchange of a NFC system (such as NFC system100) that does not utilize a “max” (duty cycle) mode (which results in a negative undershoot of VDDBOOST (“averaged” value), VDDPA, and the NFC field) in accordance with some embodiments of the invention. (Note:FIG. 2actually shows an “averaged” VDDBOOST, where the ripples due to a 3.87 MHz switching frequency have been averaged out. On the other hand,FIG. 8shows an “actual” VDDBOOST together with the ripples due to a 3.87 MHz switching frequency.)FIG. 2is showing a potential problem (of a negative undershoot) that can arise during the use of the NFC system100. For example, this problem (of a negative undershoot) can occur during the transient load response of the supply chain from ASK (Amplitude-shift keying) modulation of the NFC field. When sending data, the NFC transmitter stops the field. This leads to a 100% load variation on DCDC converter (BOOST110). Drops on VDDBOOST115should be filtered by the VDDPA LDO120, because otherwise this can lead to non-compliancy regarding normalizations on secure data exchange.FIG. 2shows that switching on a NFC field260from an off state can result in a negative undershoot of VDDBOOST215and VDDPA225. This occurs while the DCDC load current is also being switched on from an off state, so the DCDC load current increases from 0 mA to nominal current (INOM) within a short time interval. The net result is a huge initial negative undershoot of the NFC field260, which is undesirable. Of course, after some time, the system returns to a steady state condition, where VDDBOOST215, VDDPA225, and NFC field260all return to a stable steady state value. But the initial transient behavior of a huge negative undershoot for VDDBOOST, VDDPA, and the NFC field is clearly undesirable, so that the huge negative undershoot needs to be reduced.

InFIG. 2, for some embodiments, if the time interval between when the NFC field is switched off and when the NFC field is switched back on again is short enough, it is possible that the negative undershoots of VDDBOOST, VDDPA, and the NFC field will be reduced. For some embodiments, if the time interval is very short, it is possible that the negative undershoots of VDDBOOST, VDDPA, and the NFC field will be substantially eliminated.

InFIG. 2, for some embodiments, in fact during ASK (Amplitude-shift keying) the time the NFC field is turned off is very short and the boost will not see it due to its low bandwidth. In some embodiments, the system is really used at the first NFC field on event, because boost is in overshoot protection or pulse skipping with very low duty cycle. In this case, duty cycle is low and the time needed for the loop to respond is too slow. In some embodiments, this system is also used for peer to peer communications, because there is a long time between two NFC field on events.

FIG. 3shows the transient load response during NFC data exchange of a NFC system that utilizes a “max” (duty cycle) mode (which reduces or eliminates the negative undershoot of VDDBOOST (“averaged” value), VDDPA, and the NFC field) in accordance with some embodiments of the invention. (Note:FIG. 3actually shows an “averaged” VDDBOOST, where the ripples due to a 3.87 MHz switching frequency have been averaged out. On the other hand,FIG. 8shows an “actual” VDDBOOST together with the ripples due to a 3.87 MHz switching frequency.)FIG. 3is showing a solution to the problem (of a negative undershoot) that can arise during the use of the NFC system100. The solution consists of forcing the BOOST PWM clock to be in maximum duty cycle when VDDBOOST drops below a threshold. The setpoint for the maximum duty cycle can be given by a lookup table, or it can be determined by a microcontroller. A NFC system can sense the DCDC input supply voltage (i.e., VBATPWR), and then configured a clamp (e.g., maximum duty cycle) for duty cycle vs. VDDBOOST target.

In particular,FIG. 3shows that by forcing the BOOST PWM clock to be in maximum duty cycle (which is shown as a “max mode”) when VDDBOOST315drops below a threshold, the negative undershoot of VDDBOOST is reduced, while the negative undershoots of VDDPA340and the NFC field360are substantially eliminated. This occurs while the DCDC load current340is also being switched on from an off state, so the DCDC load current increases from 0 mA to nominal current (INOM) within a short time interval.

FIG. 3also shows two VDDBOOST thresholds associated with the “max mode”: VTH_LH312and VTH_HL314. VTH_HL314(i.e., high to low voltage threshold) is a first VDDBOOST threshold, while VTH_LH312(i.e., low to high voltage threshold) is a second VDDBOOST threshold. Initially, when VDDBOOST drops below the first threshold VTH_HL314, the NFC system will force the BOOST PWM clock to be in maximum duty cycle (i.e., in “max mode”). As the BOOST PWM clock is forced to be in maximum duty cycle (i.e., in “max mode”), VDDBOOST will start to increase. Then, when VDDBOOST rises above the second threshold VTH_LH312, the NFC system will reset the BOOST PWM clock back to the steady state value for duty cycle (i.e., exit from “max mode”). As the BOOST PWM clock is reset to the steady state value for duty cycle, VDDBOOST will start to decrease. Then, if VDDBOOST again drops below the first threshold VTH_HL314, the above step of changing the PWM duty cycle to a maximum value (and later resetting the PWM duty cycle back to a steady state value) will be repeated. If, however, the VDDBOOST does not again drop below the first threshold VTH_HL314while the PWM duty cycle is set to the steady state value, then the NFC system has stabilized to the steady state condition, and there is no longer any need for the NFC system to enter the “max mode”. InFIG. 3, the NFC system is seen to go through the above steps of changing the PWM duty cycle between the maximum value and the steady state value a few times before it stabilizes to the steady state condition.

FIG. 4shows a functional block diagram of a NFC system400that can utilize a “max” (duty cycle) mode (which reduces or eliminates the negative undershoot of VDDBOOST, VDDPA, and the NFC field) in accordance with some embodiments of the invention.FIG. 4shows that such a NFC system400can be comprised of: (a) a BOOST power stage410with an external coil417and a decoupling external capacitor419, (b) a BOOST clock scheme420providing PWM clock422to BOOST power stage410, (c) a voltage monitor430that is configured to monitor DCDC output voltage (by sensing voltage on VDDBOOST), (d) a microcontroller440, (e) an ADC450on VBATPWR, and (f) a lookup table460for configuring setpoint for maximum duty cycle from VBATPWR and VDDBOOST levels.

The BOOST power stage410can be a PWM (Pulse Width Modulation) boost power stage configured to provide for PWM boost power conversion. The PWM boost power stage can provide power for generating a NFC (Near Field Communication) field. The PWM boost power stage inputs an input voltage and outputs a boost voltage. InFIG. 4, the input voltage is supplied by VBATPWR405(e.g., battery power voltage supply). The output boost voltage is a stepped-up voltage VDDBOOST415(e.g., VDD (drain supply) boost voltage). Additionally,FIG. 4also shows a current level BOOSTLX407, which is positioned between the external coil417and the BOOST power stage410.

The BOOST clock scheme420is configured to provide PWM clock signal422to the PWM BOOST power stage410. The PWM clock signal422output is based on inputs from the BOOST power stage410(i.e., VDDBOOST sense412and coil current sense414), the voltage monitor430(i.e., a “max mode” signal432to trigger a maximum duty cycle when VDDBOOST drops below a threshold), the microcontroller440(i.e., a clock reference signal442and a setpoint444for the boost voltage), and the lookup table460(i.e., a setpoint462for maximum duty cycle).

The voltage monitor430is configured to sense the boost voltage output (i.e., VDDBOOST) from the PWM boost power stage410. The voltage monitor430is further configured to provide a “max mode” signal432to the BOOST clock scheme420in order to trigger a maximum duty cycle when VDDBOOST drops below a threshold.

The microcontroller440is configured to provide a clock reference signal442and a setpoint444for the boost voltage to the boost clock scheme420. The setpoint444for the boost voltage is also provided to the lookup table460for determining the maximum duty cycle for a given VBATPWR level and a given VDDBOOST setpoint. In some embodiments, the lookup table460determines the maximum duty cycle for a pre-determined VBATPWR level and a pre-determined VDDBOOST setpoint. In some embodiments, a power efficiency associated with the PWM boost power converter is also used for determining the maximum duty cycle.

The ADC (analog-to-digital converter)450is configured to convert an input voltage from an analog voltage level (i.e., VBATPWR405) to a digital voltage level (i.e., VBATPWR level452). InFIG. 4, the input voltage is supplied by VBATPWR405(e.g., battery power voltage supply).

The lookup table460is configured for determining setpoint for maximum duty cycle from VBATPWR and VDDBOOST levels. In other words, the lookup table460determines the setpoint462for maximum duty cycle based on a given input voltage (i.e., VBATPWR level452) and a given output voltage (i.e., VDDBOOST setpoint444). In some embodiments, the lookup table460also uses a power efficiency associated with the PWM boost power converter to determine the maximum duty cycle.

It is not shown inFIG. 4, but in some embodiments, the system can operate without a lookup table460. In those embodiment, the microcontroller440can be configured for determining setpoint for maximum duty cycle from VBATPWR and VDDBOOST levels. In other words, the microcontroller440determines the setpoint462for maximum duty cycle based on a given input voltage (i.e., VBATPWR level452) and a given output voltage (i.e., VDDBOOST setpoint444). In some embodiments, the microcontroller440can also use a power efficiency associated with the PWM boost power converter to determine the maximum duty cycle.

It is also not shown inFIG. 4, but in some embodiments, an analog device or a combination of an analog device and a digital device (instead of a lookup table or a microcontroller) can be configured for determining setpoint for maximum duty cycle from VBATPWR and VDDBOOST levels. In other words, an analog device or a combination of an analog device and a digital device determines the setpoint462for maximum duty cycle based on a given input voltage (i.e., VBATPWR level452) and a given output voltage (i.e., VDDBOOST setpoint444). In some embodiments, an analog device or a combination of an analog device and a digital device can also use a power efficiency associated with the PWM boost power converter to determine the maximum duty cycle.

FIG. 5shows a chronogram of the various signals during load response of a NFC system that is utilizing a “max” (duty cycle) mode to reduce or eliminate the negative undershoot of VDDBOOST (“averaged” value), VDDPA, and the NFC field in accordance with some embodiments of the invention. (Note:FIG. 5actually shows an “averaged” VDDBOOST, where the ripples due to a 3.87 MHz switching frequency have been averaged out. On the other hand,FIG. 8shows an “actual” VDDBOOST together with the ripples due to a 3.87 MHz switching frequency.)FIG. 5is very similar to previously describedFIG. 3, butFIG. 5provides more details for helping to understand the disclosed invention. In particular,FIG. 5shows the following signals in the time period after the NFC field560has been switched on from an off state: NFC field560, DCDC load current540, VDDBOOST515, “max mode” signal560, and PWM duty cycle570.

At the initial state (i.e., before time=t0), there is no NFC field, so there is no DCDC load current. The BOOST is in pulse skipping, with no PWM clock.

At time=t0, the NFC field is switched ON. The DCDC load current increases, so VDDBOOST drops.

At time=t1, high to low threshold (VTH_HL514) is triggered from the VDDBOOST fall. The “max mode” internal signal560goes to a high level. PWM clock is override at maximum duty cycle. Setpoint for maximum duty cycle can be given from a VDDBOOST/VBATPWR lookup table.

Between time t1and t2, VDDBOOST rises due to maximum duty cycle. At time=t2, VDDBOOST reaches low to high threshold (VTH_LH512) for “max mode”. “Max mode” signal set to low level, BOOST is back to regulation.

Between time t2and t3, BOOST loop not yet locked, so PWM duty cycle is still too low. VDDBOOST falls, until again triggering VTH_HL of “max mode”.

Between time t3and t4, BOOST goes alternatively from “max mode” to closed loop. VDDBOOST is kept within the hysteresis window (550) of “max mode”.

At time=t5, BOOST escapes from the “max mode” zone when PWM duty cycle of regulation loop reaches steady state.

FIG. 6shows the following signals: NFC field660, VDDBOOST615(“averaged” value), and VDDPA625. (Note:FIG. 6actually shows an “averaged” VDDBOOST, where the ripples due to a 3.87 MHz switching frequency have been averaged out. On the other hand,FIG. 8shows an “actual” VDDBOOST together with the ripples due to a 3.87 MHz switching frequency.)FIG. 6also shows the low to high threshold (VTH_LH312) and the high to low threshold (VTH_HL314) for “max mode”. Additionally,FIG. 6also shows the low to high threshold (VTH_LH316) and the high to low threshold (VTH_HL318) for overshoot protection (OVS prot).

FIG. 6shows why a maximum duty cycle that is too high can result in VDDBOOST instability. In particular,FIG. 6shows that if maximum duty cycle is too high vs VBATPWR/VDDBOOST headroom, then BOOST goes into relaxation. VDDBOOST is unstable going from the “max mode” threshold to the “OVS prot” (overshoot protection) threshold. In such a scenario, there is no possible escape from the loop going between the “max mode” threshold and the “OVS prot” (overshoot protection) threshold. In some embodiments, this scenario can be avoided by using a “maximum duty cycle” from a lookup table, which can tailor the “maximum duty cycle” to a lower value.

FIG. 7shows the formulas for the theoretical duty cycle in PWM (Pulse Width Modulation) regulation and the maximum duty cycle in PWM regulation with power loss.

For PWM BOOST converter, the duty cycle is fixed by the ratio between VBATPWR and VDDBOOST. Therefore, as shown inFIG. 7, the formula for the theoretical duty cycle in PWM (Pulse Width Modulation) regulation is given as:

Therefore, as an example, if VBATPWR=3V and VDDBOOST=5V, then Duty cycle=0.4.

Assuming power losses, maximum value for PWM duty cycle can be corrected for power losses using the parameter “Power Efficiency”. As shown inFIG. 7, the formula for the maximum duty cycle in PWM regulation with power loss is given as:

Therefore, as an example, if VBATPWR=3V and VDDBOOST=5V, and Power Efficiency=80%, then Duty cycle=0.48.

In some embodiments, the above formulas can be used to calculate setpoint for “Max Mode” duty cycle. In some embodiments, a microcontroller can use the above formulas to determine the maximum value for “Max Mode” duty cycle. In some embodiments, a microcontroller can use some other formulas or functions to determine the maximum value for “Max Mode” duty cycle. In some embodiments, a lookup table can be implemented versus VDDBOOST and VBATPWR level. In some embodiments, a microcontroller and a lookup table can be used in combination to determine the maximum value for “Max Mode” duty cycle.

FIG. 8shows that the negative undershoot of VDDBOOST (“actual” value) is reduced if the “max” (duty cycle) mode is enabled for a NFC system in accordance with some embodiments of the invention. (Note:FIG. 8shows an “actual” VDDBOOST together with the ripples due to a 3.87 MHz switching frequency.) In particular,FIG. 8shows that a huge negative undershoot of VDDBOOST815can result from switching on a NFC field from an off state. The switching on of the NFC field corresponds to the rise in the DCDC load current840, and, as can be seen inFIG. 8, this results in a huge 3-unit negative undershoot of VDDBOOST when “max mode” is disabled (see865). However, if “max mode” is enabled (see860), the negative undershoot of VDDBOOST is reduced to 2-unit. Therefore, the negative undershoot of VDDBOOST can be reduced by enabling the “max” (duty cycle) mode for a NFC system.

FIG. 9shows a method for reducing negative undershoot during transient load response that is associated with a PWM (Pulse Width Modulation) boost power converter in accordance with some embodiments of the invention. As shown inFIG. 9, the method900begins at step910, where the method switching on a NFC (Near Field Communication) field from an off state, wherein a PWM duty cycle of the PWM boost power converter is set to a steady state value, wherein the switching on of the NFC field creates a negative undershoot during transient load response. Then, the method proceeds to step920. In step920, the method detects when a boost voltage of the PWM boost power converter drops below a first threshold value. Next, at step930, the method sets the PWM duty cycle to a maximum value in response to detecting the boost voltage drop below the first threshold value, wherein the maximum value is higher than the steady state value, wherein setting the PWM duty cycle to the maximum value causes the boost voltage to rise. Then, the method proceeds to step940. In step940, the method detects when the boost voltage rises above a second threshold value, wherein the second threshold value is higher than the first threshold value. Next, at step950, the method sets the PWM duty cycle back to the steady state value in response to detecting the boost voltage rise above the second threshold value, wherein setting the PWM duty cycle to the steady state value causes the boost voltage to drop. Finally, at step960, the method continues the above steps of changing the PWM duty cycle between the maximum value and the steady state value until the boost voltage no longer drops below the first threshold value while the PWM duty cycle is set to the steady state value.

The various aspects, embodiments, implementations or features of the described embodiments can be used separately or in any combination. Various aspects of the described embodiments can be implemented by software, hardware or a combination of hardware and software.