Coherent interconnect power reduction using hardware controlled split snoop directories

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

BACKGROUND

Snoop directories help to increase the performance of coherent multi central processor unit (CPU) cluster systems. Snoop directories can increase snoop miss bandwidth independent of available CPU snoop bandwidth or frequency, reduce performance degradation on a snooped CPU, reduce structural latency to memory, and reduce power consumption for snoop misses. However, to achieve the foregoing benefits, existing snoop directory architectures must compromise among the competing drawbacks of using large amounts of memory, having high dynamic energy consumption, and/or having poor power scalability. These drawbacks, in part, are a result of tags that populate the snoop directory and indicate CPU use of memory location. These tags require high-speed static random access memory (SRAM) macros that consume significant power, especially in lower technology nodes.

SUMMARY

Various disclosed aspects may include apparatuses and methods for implementing multiple split snoop directories on a computing device. Various embodiments may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, in which the first power domain may include a plurality of processor caches and the second power domain may include at least one processor cache. Some embodiments may further include determining whether all of the plurality of processor caches are in a low power state and disabling the first split snoop directory in response to determining that all of the plurality of processor caches are in a low power state.

Some embodiments may further include detecting a condition for changing at least one processor cache of the plurality of processor caches to a low power state and sending a request to change the first split snoop directory to a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

Some embodiments may further include receiving the request to change the first split snoop directory to a low power state, in which determining whether all of the plurality of processor caches are in a low power state may include determining whether all of the plurality of processor caches are in a low power state in response to receiving the request to change the first split snoop directory to a low power state.

Some embodiments may further include receiving a condition for changing at least one processor cache of the plurality of processor caches to a low power state, in which determining whether all of the plurality of processor caches are in a low power state may include determining whether all of the plurality of processor caches are in a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

In some embodiments, receiving a condition for changing at least one processor cache of the plurality of processor caches to a low power state may include receiving a signal indicating a power state of the at least one processor cache of the plurality of processor caches from the first power domain.

Some embodiments may further include leaving the first split snoop directory enabled in response to determining that at least one processor cache of the plurality of processor caches is in a high power state.

Some embodiments may further include detecting a condition for changing at least one processor cache of the plurality of processor caches to a high power state, and enabling the first split snoop directory in response to detecting the condition for changing the at least one processor cache to a high power state and determining that the plurality of processor caches are in a low power state.

In some embodiments, a low power state may include one of an “OFF” state and a “RET” (retention) state, and a high power state may include an “ON” state.

Some embodiments may further include enabling N split snoop directories for N power domains and M split snoop directories for M power domains, in which N and M may be integers greater than 1, the N power domains may include N pluralities of processor caches and the M power domain may include at least one processor cache. Some embodiments may further include determining whether any of the N plurality of processor caches are all in a low power state and disabling any of the N split snoop directories for which all of the plurality of processor caches are in a low power state.

Various embodiments may include a computing device configured to implement multiple split snoop directories. The computing device may include a first power domain including a plurality of processor caches, a second power domain including at least one processor cache, a coherent interconnect having a first split snoop directory for the first power domain and a second split snoop directory for the second power domain, and a first processing device communicatively connected to the first power domain and communicatively connected to the coherent interconnect. The first processing device may be configured to perform operations of the embodiment methods summarized above.

Various embodiments may include a computing device configured to implement multiple split snoop directories, the computing device having means for performing functions of the embodiment methods summarized above.

Various embodiments may include a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of the embodiment methods summarized above.

DETAILED DESCRIPTION

Various aspects may include methods, and systems and devices implementing such methods for implementing power control of snoop directories using split snoop directory architectures for power domains having multiple processors, such as a central processing units (CPU). The multiple processors may be multicore processors. The apparatus and methods of the various aspects may include split snoop directory power control hardware for monitoring power domain power states and controlling split snoop directory power states for various snoop directories having split snoop directory architectures.

The terms “computing device” and “mobile computing device” are used interchangeably herein to refer to any one or all of cellular telephones, smartphones, personal or mobile multi-media players, personal data assistants (PDA's), laptop computers, tablet computers, convertible laptops/tablets (2-in-1 computers), smartbooks, ultrabooks, netbooks, palm-top computers, wireless electronic mail receivers, multimedia Internet enabled cellular telephones, mobile gaming consoles, wireless gaming controllers, and similar personal electronic devices that include a memory, and a programmable processor. The term “computing device” may further refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, super computers, mainframe computers, embedded computers, servers, home theater computers, and game consoles.

Realistic mobile device/smartphone use cases show that high performance multicore CPUs may be active less than 10% of the time in a typical day. High performance multicore CPUs also may have the biggest caches, which makes some of the most popular snoop directory architectures, such as a common tag or a statistical tag approach, very power inefficient in real use cases. These snoop directory architectures may service multiple multicore processors, including combinations of multicore processors of varying performance level. At any time, one or more of the multicore processors serviced by a snoop directory may be inactive while at least one the multicore processors serviced by the same snoop directory may be active. While any of the multicore processors serviced are active, the servicing snoop directory may not be powered down to conserve energy for a powered down multicore processor because the snoop directory may not be able to service the active multicore processor. Therefore, snoop directory architectures that service multiple multicore processors may be difficult to power scale. Snoop directory architectures that service individual multicore processors, such as a duplicate tag approach, may be more easily power scalable, because each snoop director may be powered down with the serviced multicore processor. However, one-to-one relationships between multicore processors and snoop directories may be very memory and power intensive.

A split snoop directory architecture may combine multiple snoop directories, referred to herein as split snoop directories. Each split snoop directory may be allocated for servicing one or more—but less than all—of the multicore processors. The multicore processors may be divided into power domains based on common characteristics of power consumption, including common levels and time of power consumption. In an example, a high performance multicore CPU, which is more often powered down than a standard multicore CPU, may be serviced by a first split snoop directory allocated only to the high performance multicore CPU or to multiple high performance multicore CPUs. In the same example, multiple standard multicore CPUs may be serviced by a second split snoop directory. The split snoop directories servicing a first power domain with multiple multicore processors, may use the common tag or the statistical tag approaches, while split snoop directories servicing a second power domain having only one multicore processor may use the duplicate tag, the common tag, or the statistical tag approaches. In an example, each multicore processor or group of multicore processors of a computing device may be its own power domain serviced by its own allocated split snoop directory using the common tag approach.

Split snoop directories may enable the ability to scale power based on multicore processor power states. In some aspects, one split snoop directory may be used for a power efficient power domain having one or more power efficient multicore processors, like standard performance multicore CPUs, and one split snoop directory may be used for the performance power domain having one or more performance multicore processors, like high performance multicore CPUs. For inclusive L2 cache, a single split snoop directory may be used. For exclusive L2 cache both duplicate tag and common tag options may be available. In some aspects, the common tag approach may be used for the split snoop directories to provide straight forward sizing of the split snoop directories, especially for inclusive L2 caches of the multicore processors; and to provide a reduced number of SRAM macros compared to the duplicate tag approach.

A split snoop directory power state may be tied to a power domain power state by hardware, making the power domain power state transparent to software. The power domain power state may include the power state of all of the multicore processors of the power domain. When a power domain is in a low power state, all of the multicore processors of the power domain also may be in a low power state.

Various multicore processors architectures manage power states differently. For example, a first multicore processor architecture may not provide any external indication of its power state and a second multicore processor architecture may provide a signal indicating its power state. For a first multicore processor architecture, a hardware implemented power domain low power monitor may be configured for different types of the first multicore processor architecture to detect whether a designated first multicore processor of a type of first multicore processor architecture may be in a low power state. The power domain low power monitor may monitor a power draw, a temperature, a multicore processor power control unit when the multicore processor is not indicating its power state, and/or input/output activity of the designated first multicore processor to determine the power state of the first multicore processor. In response to determining that the power domain is in a low power state, the power domain low power monitor may signal a split snoop directory power controller to power down the allocated split snoop directory of the power domain. Similarly, the power domain low power monitor may detect when the first multicore processor transitions to an active state (i.e., there is a change in the power domain), and signal the split snoop directory power controller to activate the allocated split snoop directory of the power domain in response.

As another example, in a second multicore processor architecture, the split snoop directory power controller may be configured for different types of the second multicore processor architecture to receive signals from a designated second multicore processor indicating whether the second multicore processor is in a low power state. Based on signals from the second multicore processor indicating whether it is in a low power state, a split snoop directory power controller may determine whether the power domain is in a low power state, and power down the allocated split snoop directory of the second multicore processor in response to determining the power domain is in the low power state. Similarly, the split snoop directory power controller may receive signals from a designated second multicore processor, and from those signals determine whether it is in an active state and activate the allocated split snoop directory of the power domain in response.

FIG. 1illustrates a system including a computing device10suitable for use with the various aspects. The computing device10may include a system-on-chip (SoC)12with a processor14, a memory16, a communication interface18, and a storage memory interface20. The computing device10may further include a communication component22such as a wired or wireless modem, a storage memory24, and an antenna26for establishing a wireless communication link. The processor14may include any of a variety of processing devices, for example a number of processor cores.

The term “system-on-chip” (SoC) is used herein to refer to a set of interconnected electronic circuits typically, but not exclusively, including a processing device, a memory, and a communication interface. A processing device may include a variety of different types of processors14and processor cores, such as a general purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), an auxiliary processor, a single-core processor, and a multicore processor. A processing device may further embody other hardware and hardware combinations, such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic device, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time references. Integrated circuits may be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

An SoC12may include one or more processors14. The computing device10may include more than one SoC12, thereby increasing the number of processors14and processor cores. The computing device10may also include processors14that are not associated with an SoC12. Individual processors14may be multicore processors as described below with reference toFIG. 2. The processors14may each be configured for specific purposes that may be the same as or different from other processors14of the computing device10. One or more of the processors14and processor cores of the same or different configurations may be grouped together. A group of processors14or processor cores may be referred to as a multi-processor cluster.

The memory16of the SoC12may be a volatile or non-volatile memory configured for storing data and processor-executable code for access by the processor14. The computing device10and/or SoC12may include one or more memories16configured for various purposes. One or more memories16may include volatile memories such as random access memory (RAM) or main memory, or cache memory. These memories16may be configured to temporarily hold a limited amount of data received from a data sensor or subsystem, data and/or processor-executable code instructions that are requested from non-volatile memory, loaded to the memories16from non-volatile memory in anticipation of future access based on a variety of factors, and/or intermediary processing data and/or processor-executable code instructions produced by the processor14and temporarily stored for future quick access without being stored in non-volatile memory.

The memory16may be configured to store data and processor-executable code, at least temporarily, that is loaded to the memory16from another memory device, such as another memory16or storage memory24, for access by one or more of the processors14. The data or processor-executable code loaded to the memory16may be loaded in response to execution of a function by the processor14. Loading the data or processor-executable code to the memory16in response to execution of a function may result from a memory access request to the memory16that is unsuccessful, or a miss, because the requested data or processor-executable code is not located in the memory16. In response to a miss, a memory access request to another memory16or storage memory24may be made to load the requested data or processor-executable code from the other memory16or storage memory24to the memory device16. Loading the data or processor-executable code to the memory16in response to execution of a function may result from a memory access request to another memory16or storage memory24, and the data or processor-executable code may be loaded to the memory16for later access.

The storage memory interface20and the storage memory24may work in unison to allow the computing device10to store data and processor-executable code on a non-volatile storage medium. The storage memory24may be configured much like an aspect of the memory16in which the storage memory24may store the data or processor-executable code for access by one or more of the processors14. The storage memory24, being non-volatile, may retain the information after the power of the computing device10has been shut off. When the power is turned back on and the computing device10reboots, the information stored on the storage memory24may be available to the computing device10. The storage memory interface20may control access to the storage memory24and allow the processor14to read data from and write data to the storage memory24.

Some or all of the components of the computing device10may be arranged differently and/or combined while still serving the necessary functions. Moreover, the computing device10may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of the computing device10.

FIG. 2illustrates a multicore processor suitable for implementing an aspect. The multicore processor14may include multiple processor types, including, for example, a central processing unit, a graphics processing unit, and/or a digital processing unit. The multicore processor14may also include a custom hardware accelerator which may include custom processing hardware and/or general purpose hardware configured to implement a specialized set of functions.

The multicore processor may have a plurality of homogeneous or heterogeneous processor cores200,201,202,203. A homogeneous multicore processor may include a plurality of homogeneous processor cores. The processor cores200,201,202,203may be homogeneous in that, the processor cores200,201,202,203of the multicore processor14may be configured for the same purpose and have the same or similar performance characteristics. For example, the multicore processor14may be a general purpose processor, and the processor cores200,201,202,203may be homogeneous general purpose processor cores. The multicore processor14may be a graphics processing unit or a digital signal processor, and the processor cores200,201,202,203may be homogeneous graphics processor cores or digital signal processor cores, respectively. The multicore processor14may be a custom hardware accelerator with homogeneous or heterogeneous processor cores200,201,202,203. For ease of reference, the terms “hardware accelerator,” “custom hardware accelerator,” “multicore processor,” “processor,” and “processor core” may be used interchangeably herein.

A heterogeneous multicore processor may include a plurality of heterogeneous processor cores. The processor cores200,201,202,203may be heterogeneous in that the processor cores200,201,202,203of the multicore processor14may be configured for different purposes and/or have different performance characteristics. The heterogeneity of such heterogeneous processor cores may include different instruction set architecture, pipelines, operating frequencies, etc. An example of such heterogeneous processor cores may include what are known as “big.LITTLE” architectures in which slower, low-power processor cores may be coupled with more powerful and power-hungry processor cores. In similar aspects, an SoC (for example, SoC12ofFIG. 1) may include any number of homogeneous or heterogeneous multicore processors14. In various aspects, not all off the processor cores200,201,202,203need to be heterogeneous processor cores, as a heterogeneous multicore processor may include any combination of processor cores200,201,202,203including at least one heterogeneous processor core.

Each of the processor cores200,201,202,203of a multicore processor14may be designated a private cache210,212,214,216that may be dedicated for read and/or write access by a designated processor core200,201,202,203. The private cache210,212,214,216may store data and/or instructions, and make the stored data and/or instructions available to the processor cores200,201,202,203, to which the private cache210,212,214,216is dedicated, for use in execution by the processor cores200,201,202,203. The private cache210,212,214,216may include volatile memory as described herein with reference to memory16ofFIG. 1.

The multicore processor14may further include a shared cache230that may be configured for read and/or write access by the processor cores200,201,202,203. The private cache210,212,214,216may store data and/or instructions, and make the stored data and/or instructions available to the processor cores200,201,202,203, for use in execution by the processor cores200,201,202,203. The shared cache230may also function as a buffer for data and/or instructions input to and/or output from the multicore processor14. The shared cache230may include volatile memory as described herein with reference to memory16ofFIG. 1.

In the example illustrated inFIG. 2, the multicore processor14includes four processor cores200,201,202,203(i.e., processor core0, processor core1, processor core2, and processor core3). In the example, each processor core200,201,202,203is designated a respective private cache210,212,214,216(i.e., processor core0and private cache0, processor core1and private cache1, processor core2and private cache2, and processor core3and private cache3). For ease of explanation, the examples herein may refer to the four processor cores200,201,202,203and the four private caches210,212,214,216illustrated inFIG. 2. However, the four processor cores200,201,202,203and the four private caches210,212,214,216illustrated inFIG. 2and described herein are merely provided as an example and in no way are meant to limit the various aspects to a four-core processor system with four designated private caches. The computing device10, the SoC12, or the multicore processor14may individually or in combination include fewer or more than the four processor cores200,201,202,203and private caches210,212,214,216illustrated and described herein.

FIGS. 3-5illustrate non-limiting examples of split snoop directory systems for multiple power domains with and without multicore processor state signaling. The examples illustrated and described herein, particularly with reference to those of and relating toFIGS. 3-5, are non-limiting. The split snoop directory systems may include any number of processors, processor cores, private caches, shared caches, power domains, split snoop directories, processor cache power controllers, and split snoop directory power controllers. Thus, the number of processors, processor cores, caches, power domains, split snoop directories, shared cache controllers, and split snoop directory power controllers illustrated in theFIGS. 3-5are merely for illustration. For ease of reference and clarity, the term multicore processor is used herein to refer to multicore processors, single core processors, and/or processor cores. Further, references to one or two power domains, split snoop directories, shared cashes, etc. in the descriptions of the various aspect methods are for illustration purposes only, as such methods may be extended to any number N of power domains, split snoop directories, shared cashes, etc.

FIG. 3illustrates an example aspect of a split snoop directory system for multiple power domains. A computing device (e.g., the computing device10inFIG. 1) configured to implement a split snoop directory system may include at least two, but up to any integer number “N” multicore processors, for example, processor114aand processor N14b. Each multicore processor14a,14bmay include any number of processor cores (e.g., processor cores200,201,202,203inFIG. 2), for example, multicore processor14amay include up to any integer number “M” processor cores, including processor core1300aand processor core M300b. Similarly, multicore processor14bmay include up to any integer number “P” processor cores, including processor core1300cand processor core P300d. As discussed herein, each of the multicore processors14a,14bmay be homogenous and/or heterogeneous with respect to each other and/or among their respective processor cores300a,300b,300c,300d.

Each processor core300a,300b,300c,300dmay be associated with a private cache (e.g., the private cache210,212,214,216inFIG. 2) designated for use by the associated processor core300a,300b,300c,300d. For example, a private cache302amay be associated with and designated for use by the processor core300a. Similarly, a private cache302bmay be associated with and designated to the processor core300b, a private cache302cmay be associated with and designated to the processor core300c, and a private cache302dmay be associated with and designated to the processor core300d.

Each multicore processor14a,14bmay also include a shared cache (e.g., shared cache230inFIG. 2) configured for read and/or write access by the multicore processor14a,14b, including the processor cores300a,300b,300c,300d. In the example illustrated inFIG. 3, the multicore processor14amay include a shared cache304a, and the multicore processor14bmay include a shared cache304b. In various aspects, the shared cache304a,304bmay be writable only within its respective multicore processor14a,14b. In various aspects, the shared cache304a,304bmay be readable by another multicore processor14a,14busing snooping.

A coherent interconnect308may be communicatively connected to the multicore processors14a,14b, any number of input/output (I/O) agents306a,306b, and any number of main memory or random access memory components312(e.g., memory16inFIG. 1). The coherent interconnect308may be configured to enable and control transmission of data between the various connected components. The I/O agents306a,306bmay communicate input data to the coherent interconnect308with the multicore processors14a,14band/or the random access memory components312as a destination for the data. The I/O agents306a,306bmay also receive data from the multicore processors14a,14band/or the random access memory components312through the coherent interconnect308. The random access memory components312may be configured to store and/or provide data and/or instructions for the multicore processors14a,14band/or the I/O agents306a,306b. The random access memory components312may be configured as a buffer for the data and/or instructions between the multicore processors14a,14b, the I/O agents306a,306b, and/or a storage device (e.g., storage memory24inFIG. 1).

The coherent interconnect308may also include random access memory components (e.g., memory16inFIG. 1, and static random access memory (SRAM)) configured to store and make available data representing the split snoop directories310a,310b. As described further herein, the split snoop directories310a,310bmay be correlated with a particular power domain. Each split snoop directory310a,310bmay include a number of tags corresponding with memory locations of the private caches302a,302b,302c,302dand/or the shared caches304a,304bof the respective multicore processors14a,14bof associated power domain. Each tag may be associated with information identifying whether certain data is located at a corresponding memory location of the private caches302a,302b,302c,302dand/or the shared caches304a,304b. The private caches302a,302b,302c,302dand/or the shared caches304a,304bmay be referred to herein as a processor cache(s) for ease of reference and clarity of explanation. Use of the term processor cache(s) does not limit the aspects described herein to necessarily include all of the private caches302a,302b,302c,302dand/or the shared caches304a,304b.

The split snoop directory310a,310bmay be queried by the multicore processors14a,14band/or the I/O agents306a,306bto determine whether data sought for execution of a process is stored locally for a multicore processor14a,14bon its processor cache302a,302b,302c,302d,304a,304b, without having to query the processor cache302a,302b,302c,302d,304a,304bdirectly. When the data is not stored on the processor cache302a,302b,302c,302d,304a,304b, the query to either the split snoop directory310a,310bor the processor caches302a,302b,302c,302d,304a,304bis known as a “miss.” Without implementation of the split snoop directory310a,310b, a snoop transaction by an issuing multicore processor14a,14bto each of the other multicore processors14a,14bis required to retrieve the data of the query. In response to a “miss” occurring, an external transaction to the random access memory components312is required to retrieve the data of the query. With implementation of the split snoop directory310a,310b, a snoop transaction to each of the other multicore processors14a,14bmay not be required. Rather a snoop transaction may be directed to the split snoop directories310a,310b. In response to a “miss” occurring in the split snoop directories310a,310b, the external transaction to the random access memory components312may be implemented to retrieve the data of the query. In response to finding a tag in the split snoop directory310a,310bfor a location in a processor cache302a,302b,302c,302d,304a,304bassociated with the data for the query, also known as a “hit”, a snoop transaction to all multicore processors14a,14bassociated with the split snoop directory310a,310bthat “hit” may be implemented. An external transaction to the random access memory components312might be implemented too (depending on access type, and snooped processor cache behavior).

Therefore, architectures that lack split snoop directories310a,310bmay require extra transactions between the multicore processors14a,14b, the I/O agents306a,306b, the coherent interconnect308, and the random access memory components312to retrieve the data of the query. Implementation of the split snoop directory310a,310bmay allow a query directed to a split snoop directory310a,310bto be redirected to the random access memory components312for a “miss.” This may obviate extra transactions between the coherent interconnect308and the multicore processors14a,14botherwise needed to check for the data in the processor cache302a,302b,302c,302d,304a,304b. The query may be used to check whether a tag of the split snoop directory310a,310bindicates that the queried data is or is not stored locally to the multicore processor14a,14bon the processor cache302a,302b,302c,302d,304a,304bwithout implementing transactions between the coherent interconnect308and the multicore processors14a,14b. Upon indication of a “miss,” the data may be retrieved from the random access memory components312.

FIG. 4illustrates an example aspect of a split snoop directory system for multiple power domains. The example illustrated inFIG. 4incorporates many aspects of the example illustrated inFIG. 3, including the multicore processors14a,14b, the processor cores300a,300b,300c,300d, the private caches302a,302b,302c,302d, the shared caches304a,304b, the coherent interconnect308, and the split snoop directories310a,310b. The example illustrated inFIG. 4further includes components similar to those described above, including the multicore processor14c, the processor cores300e,300f, the private caches302e,302f, and the shared cache304c. The multicore processor14cmay include up to any integer number “R” processor cores, including processor core1300eand processor core R300f. For clarity, the I/O agents306a,306b, and the random access memory components312are omitted from the example illustrated inFIG. 4. Also, the term processor cache(s) may include the additional private caches302e,302f, and the shared cache304cof the example inFIG. 4.

The example illustrated inFIG. 4also includes two power domains400a,400b, three processor cache power controllers402a,402b,402c, and two split snoop directory power controllers404a,404b. The power domains400a,400bmay be groups of at least one multicore processor14a,14b,14c, and may include any number N of power domains. Each power domain400a,400bmay include multiple processor cores300a,300b,300c,300d,300e,300f, and at least one shared cache304a,304b,304c. The power domains400a,400bmay also include any number of private caches302a,302b,302c,302d,302e,302f. Each of the power domains400a,400bmay be associated with one of the split snoop directory310a,310b. In the example illustrated inFIG. 4, the power domain400amay be associated with the split snoop directory310a, and the power domain400bmay be associated with the split snoop directory310b. In other words, the split snoop directory310amay store tags corresponding to memory locations in the processor caches302a,302b,302e,302f,304a,304c, the split snoop directory310bmay store tags corresponding to memory locations in the processor cache302c,302d,304b.

The processor cache power controllers402a,402b,402cmay be configured to detect conditions of the components of the power domains400a,400bin order to determine whether the components of the power domains are in or are transitioning between a low power state and a standard state. The processor cache power controllers402a,402b,402cmay monitor a power draw, a temperature, a multicore processor power control unit when the multicore processor is not indicating its power state, an interrupt, and/or input/output activity of a designated multicore processor14a,14b,14c. The processor cache power controllers402a,402b,402cmay be configured to signal to an associated split snoop directory power controllers404a,404b, associated with the same the split snoop directory310a,310band the power domain400a,400b. The processor cache power controllers402a,402b,402cand the split snoop directory power controllers404a,404bmay be associated in one-to-one relationships or many processor cache power controllers402a,402b,402cto one split snoop directory power controller404a,404b. In various aspects, the number of processor cache power controllers402a,402b,402cmay be the same as the number of private caches302a,302b,302c,302d,302e,302for shared caches304a,304b,304cof the associated power domain400a,400b.

The split snoop directory power controllers404a,404bmay be configured to track the power state of the components of the power domain400a,400bto which the split snoop directory power controller404a,404bis associated. The split snoop directory power controllers404a,404bmay update the power state of the components of the power domain400a,400bbased on the signals received from the processor cache power controllers402a,402b,402c. As described further herein, the split snoop directory power controllers404a,404bmay control a power state of the associated split snoop directory310a,310bbased on the power state of the components of the power domain400a,400b. The split snoop directory power controllers404a,404bmay power up and enable, power down and disable, or put in retention the associated split snoop directory310a,310b. In various aspects, each split snoop directory power controller404a,404bmay be associated with one split snoop directory310a,310b.

FIG. 5illustrates an example aspect of a split snoop directory system for multiple power domains. The example illustrated inFIG. 5incorporates many aspects of the example illustrated inFIGS. 3 and 4, including the multicore processors14a,14b,14c, the processor cores300a,300b,300c,300d,300e,300f, the processor caches including the private caches302a,302b,302c,302d,302e,302f, and the shared caches304a,304b,304c, the coherent interconnect308, the split snoop directories310a,310b, the power domains400a,400b, the processor cache power controllers402a,402b,402c, and the split snoop directory power controllers404a,404b. For clarity, the I/O agents306a,306band the random access memory components312are omitted from the example illustrated inFIG. 5.

In the example illustrated inFIG. 5the multicore processors14a,14b,14c, the processor cache power controllers402a,402b,402c, and the split snoop directory power controllers404a,404bmay be configured in a manner that differs from the example illustrated inFIG. 4. In various aspects, each multicore processors14a,14b,14cmay be configured to signal the processor's power state and the power state of the processor's components to the coherent interconnect308and to the split snoop directory power controllers404a,404b. The split snoop directory power controllers404a,404bmay use the power state signals received from the multicore processors14a,14b,14cto track the power states of the components of the power domains400a,400b. Therefore, the processor cache power controllers402a,402b,402cmay not need to be configured to detect conditions of the components of the power domains400a,400bin order to determine whether the components of the power domains are in or are transitioning between a low power state and a standard state.

In various aspects, the split snoop directory power controllers404a,404bmay be configured as described with reference toFIG. 4, except instead of using the signals from the processor cache power controllers402a,402b,402c, the split snoop directory power controllers404a,404bmay track the power state of the components of the power domains400a,400band control the power states of the split snoop directories310a,310bbased on signals received from the multicore processors14a,14b,14c.

FIG. 6illustrates an example power state table600for a power domain (e.g., power domain400a,400binFIGS. 4 and 5). A power state table600may include various rules for the split snoop directory power controllers (e.g., split snoop directory power controllers404a,404binFIGS. 4 and 5) for controlling the power state of an associated split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) according to the power states of the components of the power domain. The example illustrated inFIG. 6includes two columns for the power states of the processor caches (e.g., private caches302a,302b,302c,302d,302e,302fand shared cache304a,304b,304cinFIGS. 3-5) of two multicore processors (e.g., multicore processors14a,14b,14cinFIGS. 3-5). For clarity and simplicity, the example illustrated inFIG. 6shows two columns for the power states of two processor caches (e.g., the shared caches) of two multicore processors of a single power domain. However, this example is non-limiting, and a power state table for use with various aspects may include any number of columns used to track any number of processor caches, multicore processors, or power domains.

In various aspects, as long as at least one processor cache is in a high power state, such as an “ON” power state, the corresponding split snoop directory associated with the power domain having the “ON” processor cache may also be set to an “ON” power state. In various aspects, for a split snoop directory to be set to a low power state, such as an “OFF” power state, all of the processor caches of the associated power domain may be in an “OFF” power state. Because the split snoop directory is shared by multiple processor caches of a power domain, the split snoop directory may be powered to be able to service any portion of the power domain. Therefore, to be able to power off the split snoop directory, all of the processor caches of the power domain may need to be powered off so that there is no need for the split snoop directory to service any portion of the power domain.

In various aspects, in any combination of processor caches of a power domain being in various combinations of low power states including an “OFF” state and at least one of the processor caches being in a “RET” (retention) state, the split snoop directory for the power domain may be set to a “RET” state. Because retention of data requires power (albeit lower power than an “ON” state), the split snoop directory may be placed in a “RET” state to correspond with the at least one processor cache in the “RET” state while other processor caches of the power domain are powered off. Similar to the combination of “ON” state and “OFF” state processor caches, for any combination of at least one processor cache being in an “ON” state and any other processor caches being in “RET” and/or “OFF” states, the split snoop directory may be set to an “ON” state. In each of these combinations of power states, the higher power state of at least one processor cache of a power domain may dictate the power state of the split snoop directory; “ON” being the highest power state, then “RET”, and “OFF” being the lowest power state. The split snoop directory power controllers may be configured to track the power states of the components of the power domains with which they are associated, and apply rules, such as the rules in the example illustrated inFIG. 6, to control the power states of the split snoop directories.

Various aspects include methods700,800,900,1000,1100,1200,1300,1400,1500that may be implemented by one or more processors for multiple power domains and multiple split snoop directories as illustrated inFIGS. 7-15and described below. The methods700,800,900,1000,1100,1200,1300,1400,1500may be implemented individually and/or in parallel for multiple power domains (e.g., power domain400a,400binFIGS. 4 and 5) and their corresponding split snoop directories (e.g., split snoop directory310a,310binFIGS. 4 and 5). The multiple power domains may each include any combination of components, including a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and at least one processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) and/or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). For example, a first power domain may include multiple processor caches and a second power domain may include at least one processor cache. As described herein, each power domain may be associated with a corresponding split snoop directory. For example, the first power domain may be associated with a first split snoop directory and the second power domain may be associated with a second split snoop directory. For clarity and ease of reference, the methods700,800,900,1000,1100,1200,1300,1400,1500are described herein with reference to the first power domain and the first split snoop directory. However, the methods700,800,900,1000,1100,1200,1300,1400,1500may be similarly implemented for the second power domain and the second split snoop directory and/or any number N power domains and N split snoop directories, in which N is an integer greater than 1. Further, the aspect methods700,800,900,1000,1100,1200,1300,1400,1500may be implemented for N power domains and N split snoop directories individually or in parallel.

FIG. 7illustrates a method700for implementing split snoop directories for multiple power domains according to an aspect. The method700may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a software-configured processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method700is referred to herein as a “processing device.”

In block702, the processing device may monitor for and detect a power state change in a first power domain (e.g., power domain400a,400binFIGS. 4 and 5). In various aspects, monitoring for and detecting a power state change in a first power domain may include directly monitoring for and detecting a power state change, or monitoring for and detecting a condition for changing a power state. In various aspects, the power state change or condition for changing a power state may be detected for any of the components of the first power domain, including a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and a processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). The power state change detected may include a change from any of the high power state, such as the “ON” state, and the lower power states, such as the “OFF” or “RET” states, to another power state of the same set of power states. In some aspects, the processing device may monitor a power state of N power domains. For ease of reference, the method700is described with respect to the processor monitoring and detecting a power state of one (“first”) power domain. However, the reference to the first power domain is arbitrary and non-limiting because similar operations may be performed for any number N of power domains.

In block704, the processing device may determine a power state of the first power domain. The power state of the first power domain may be linked to the power state of any combination of the components of the first power domain. For example, the power state of the first power domain may be linked to the power state of the processor caches of the first power domain. As discussed herein, the power state for the first power domain may be the highest power state of any one of the components to which the power state of the first power domain is linked. In some aspects, the processing device may determine a power state of N power domains.

In determination block706, the processing device may determine whether the power state change is a power up state change for the first power domain. A power up state change may include a change from a low power state, including an “OFF” or “RET’ power state, to a high power state, including an “ON” power state. The processing device may compare the state of the first power domain and the power state change in the first power domain to determine whether there is a state change for the first power domain and what the state change is. For example, a power state change in the first power domain to a higher power state than the first power domain may result in a state change for the first power domain to the higher power state. In another example, a power state change in the first power domain to a lower power state than the first power domain may result in a state change for the first power domain to the lower power state, as long as no other component of the first power domain is in a higher power state than the power state of the power state change. In another example, a power state change in the first power domain to a power state that is the same as the power state for the first power domain may result in no power state change for the first power domain. In some aspects, the processing device may perform the operations in determination block706for N power domains.

In response to determining that the power state change is a power up state change for the first power domain (i.e., determination block706=“Yes”), the processing device may enable the first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) corresponding to the first power domain in block710. In some aspects, the processing device may perform the operations in block710for N power domains.

In response to determining that the power state change is not a power up state change for the first power domain (i.e., determination block706=“No”), the processing device may determine whether the power state change is a power down or retention state change for the first power domain in determination block708. The “OFF” and “RET’ power states may be referred to as low power states, and a power state change including a power down or retention state change may be a change to a low power state. In some aspects, the processing device may perform the operations in block708for N power domains.

In response to determining that the power state change is a power down or retention state change for the first power domain (i.e., determination block708=“Yes”), the processing device may disable the first split snoop directory corresponding to the first power domain in block712. In some aspects, the processing device may perform the operations in block712for N power domains.

In block714, the processing device may put the first split snoop directory into a retention state or power down the first split snoop directory depending on whether the power state change is a power down or retention state change for the first power domain in determination block708. In some aspects, the processing device may perform the operations in block714for N power domains.

In response to determining that the power state change is not a power down or retention state change for the first power domain (i.e., determination block708=“No”), the processing device may continue to monitor for and detect a further power state change in the first power domain (or N power domains) in block702.

FIG. 8illustrates a method800for implementing split snoop directory power up and enablement for multiple power domains according to an aspect. The method800may be implemented for any number N power domains in which N is an integer greater than 1. The method800may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method800is referred to herein as a “processing device.” In various aspects, the method800may be implemented as part of, in extension of, in conjunction with, or separate from the method700described with reference toFIG. 7.

In block802the processing device may detect a wake up condition in a first power domain (e.g., power domain400a,400binFIGS. 4 and 5). A wake up condition may be a condition for changing the first power domain to a high power (i.e., “ON”) state. Detecting a wake up condition may be based on monitoring a power draw, a temperature, a multicore processor power control unit activity and/or state when the multicore processor is not indicating its power state, an interrupt, and/or input/output activity of a component of the first power domain, including any of a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and a processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). An increase in a monitored level of power draw, temperature, and/or input/output activity, detecting the multicore processor power control unit's activity and/or state, and/or detecting an interrupt may indicate to the processing device that a wake up event has occurred in the first power domain. In some aspects, the processing device may perform the operations in block802for N power domains.

In block804, the processing device may send a power up request for the first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) for the first power domain. The power up request for the first split snoop directory for the first power domain may be sent after a determination of a power up state change for the first power domain, such as in determination block706of the method700, or irrespective of such a determination. In some aspects, the processing device may perform the operations in block804for N power domains.

In block806, the processing device may power up a multicore processor cache in response to detecting the wake up condition. In some aspects, the processing device may perform the operations in block806for N power domains.

In block808, the processing device may determine whether the first split snoop directory associated with the first power domain is enabled. In some aspects, the processing device may perform the operations in block808for N power domains and N split snoop directories.

In determination block810, the processing device may trigger tag initialization for the first split snoop directory associated with the first power domain, and trigger enabling the first split snoop directory. In some aspects, the processing device may perform the operations in block810for N power domains and N split snoop directories.

In response to determining that the first split snoop director associated with the first power domain is not enabled (i.e., determination block810=“No”), the processing device may send an enable request for the first split snoop directory in block812. In some aspects, the processing device may perform the operations in block812for N power domains and N split snoop directories.

In block814, the processing device may receive an acknowledgment of enablement of the first split snoop directory. In some aspects, the processor may receive acknowledgement of enablement in block810for N split snoop directories.

In block816, the processing device may enable snooping of the first split snoop directory. In some aspects, the processing device may perform the operations in block816for N power domains and N split snoop directories.

In block818, the processing device may enable the multicore processor cache.

In response to determining that the first split snoop director associated with the first power domain is enabled (i.e., determination block810=“Yes”), the processing device may enable snooping of the first split snoop directory in block816. In some aspects, the processing device may perform the operations in block810for N power domains and N split snoop directories.

FIG. 9illustrates a method900for implementing split snoop directory power up for multiple power domains according to an aspect. The method900may be implemented for any number N power domains in which N is an integer greater than 1. The method900may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method900is referred to herein as a “processing device.” In various aspects, the method900may be implemented as part of, in extension of, in conjunction with, or separate from the method700inFIG. 7and/or the method800described with reference toFIG. 8.

In block902, the processing device may receive a power up request for a first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) associated with a first power domain (e.g., power domain400a,400binFIGS. 4 and 5). The power up request may be the power up request sent in block804of the method800. In some aspects, the processor may perform the operations in block902for N power domains and N split snoop directories.

In determination block904, the processing device may determine whether the first split snoop directory associated with the first power domain is already powered up. In some aspects, the processing device may perform the operations in block904for N power domains and N split snoop directories.

In response to determining that the first split snoop directory is not already powered up (i.e., determination block904=“No”), the processing device may power up the first split snoop directory in block906. In some aspects, the processing device may perform the operations in block906for N power domains and N split snoop directories.

In response to determining that the first split snoop directory is already powered up (i.e., determination block904=“Yes”), the processing device may receive a power up request for a second split snoop directory associated with a second power domain in block902.

FIG. 10illustrates a method1000for enabling the split snoop directory for multiple power domains according to an aspect. The method1000may be implemented for any number N power domains in which N is an integer greater than 1. The method1000may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1000is referred to herein as a “processing device.” In various aspects, the method1000may be implemented as part of, in extension of, in conjunction with, or separate from the method700described with reference toFIG. 7and/or the method800described with reference toFIG. 8.

In block1002, the processing device may receive an enable request for a first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) associated with a first power domain (e.g., power domain400a,400binFIGS. 4 and 5). The enable request may be the enable request sent in block812of the method800. In some aspects, the processing device may perform the operations in block1002for N power domains and N split snoop directories.

In block1004, the processing device may enable the first split snoop directory. In block1006, the processing device may send an acknowledgement of the enablement of the power domain split snoop directory. The acknowledgement may be the acknowledgement received in block814of the method800.

FIG. 11illustrates a method1100for implementing split snoop directory disabling for multiple power domains according to an aspect. The method1100may be implemented for any number N power domains in which N is an integer greater than 1. The method1100may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1100is referred to herein as a “processing device.” In various aspects, the method1100may be implemented as part of, in extension of, in conjunction with, or separate from the method700inFIG. 7.

In block1102, the processing device may detect a condition for change in a first power domain (e.g., power domain400a,400binFIGS. 4 and 5) to a low power state including, power down and retention (i.e., RET) states. Detecting a power down (i.e., “OFF”) or retention (i.e., “RET”) condition may be based on monitoring a power draw, a temperature, a multicore processor power control unit activity and/or state when the multicore processor is not indicating its power state, and/or input/output activity of a component of the first power domain, including any of a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). A decrease or cessation in a monitored level of power draw, temperature, a multicore processor power control unit's activity and/or state, and/or input/output activity may indicate to the processing device that a power down or retention event has occurred in the first power domain. In some aspects, the processing device may perform the operations in block1102for N power domains.

In optional block1104, for a power down event, the processing device may flush the processor caches of the first power domain affected by the power down event. The processor cache flush may transmit the data stored in the processor cache at the time of the power down event to another memory (e.g., memory16and storage device24inFIG. 1and random access memory components312inFIG. 3). In some aspects, the processing device may perform the operations in block1104for N power domains and N split snoop directories.

In block1106, the processing device may disable snooping of a first split snoop directory associated with the first power domain for the processor caches associated with the change to a low power state. In some aspects, the processing device may perform the operations in block1106for N power domains and N split snoop directories.

In block1108, the processing device may change the processor caches of the first power domain, associated with the change to a low power state, to the low power state. In various embodiments, changing a processor cache to a low power state may include changing the processor cache to a powered down (i.e., “OFF”) state or to a retention (i.e., “RET”) state.

In block1110, the processing device may send a disable notification for the first split snoop directory associated with the first power domain. The disable notification may be a request to change the first split snoop directory to a low power state, such as the “OFF” or the “RET” state, in response to detecting the condition for changing a first power domain to a low power state in block1102. In some aspects, the processing device may perform the operations in block1108for N power domains and N split snoop directories.

FIG. 12illustrates a method1200for implementing split snoop directory disabling for multiple power domains according to an aspect. The method1200may be implemented for any number N power domains in which N is an integer greater than 1. The method1200may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1200is referred to herein as a “processing device.” In various aspects, the method1200may be implemented as part of, in extension of, in conjunction with, or separate from the method700described with reference toFIG. 7and/or the method1100described with reference toFIG. 11.

In block1202, the processing device may receive a disable notification for a first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) associated with a first power domain (e.g., power domain400a,400binFIGS. 4 and 5). The disable notification may be the disable notification sent in block1110of the method1100. The disable notification may be a request to change the first split snoop directory to a low power state, such as the “OFF” or the “RET” state, in response to detecting the condition for changing a first power domain to a low power state in block1102. In some aspects, the processing device may perform the operations in block1202for N power domains and N split snoop directories.

In block determination block1204, the processing device may determine whether the disable notification is triggered by changing a last powered processor cache (e.g., private cache302a,302b,302c,302d,302e,302for shared cache304a,304b,304cinFIGS. 4 and 5) of the first power domain to a low power state, either by powering down the last powered processor cache into retention or putting the last powered processor cache into retention. In other words, the processor may determine whether changing the processor cache to a low power state in block1108of the method1100results in all of the processor caches of the first power domain in an “OFF” or “RET” power state and none in an “ON” power state. In some aspects, the processing device may perform the operations in determination block1204for N power domains.

In response to determining that the disable notification is triggered by changing the last powered processor cache to a low power state (i.e., determination block1204=“Yes”), the processing device may disable the first split snoop directory associated with the first power domain in block1206. In some aspects, the processing device may perform the operations in block1206for N power domains and N split snoop directories.

In block1208, the processing device may power down or put into retention the first split snoop directory associated with the first power domain. In some aspects, the processing device may perform the operations in block1208for N power domains and N split snoop directories.

In response to determining that the disable notification is triggered by changing the not last powered processor cache to a low power state (i.e., determination block1204=“No”), the processing device may leave the first split snoop directory enabled in block1210. In some aspects, the processing device may perform the operations in block1210for N power domains and N split snoop directories.

In the methods700,800,900,1000,1100,1200described herein, the transmission (i.e., sending and receiving) of signals, requests, and acknowledgements may occur between the split snoop directory power controllers (e.g., the split snoop directory power controllers404a,404binFIGS. 4 and 5) and the processor cache power controllers (e.g., the processor cache power controllers402a,402b,402cinFIGS. 4 and 5) associated with a power domain (e.g., the power domain400a,400binFIGS. 4 and 5).

FIG. 13illustrates a method1300for implementing split snoop directory power up and enablement for multiple power domains with multicore processor state signaling according to an aspect. The method1300may be implemented for any number N power domains in which N is an integer greater than 1. The method1300may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1300is referred to herein as a “processing device.” In various aspects, the method1300may be implemented as part of, in extension of, in conjunction with, or separate from the method700described with reference toFIG. 7.

In block1302, the processing device may receive a wake up condition in the first power domain (e.g., power domain400a,400binFIGS. 4 and 5). A wake up condition may be a condition for changing the first power domain to a high power, “ON”, state. Receiving a wake up condition may be based on monitoring a power draw, a temperature, an interrupt, and/or input/output activity of a component of the first power domain, including any of a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and a processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). An increase in a monitored level of power draw, temperature, and/or input/output activity, may indicate to the processing device that a wake up event has occurred in the first power domain. In some aspects, the processing device may perform the operations in block1302for N power domains.

In determination block1304, the processing device may determine whether a first split snoop directory (e.g., split snoop directory310a,310binFIGS. 3-5) for the first power domain is already powered up. In some aspects, the processing device may perform the operations in determination block1304for N power domains and N split snoop directories.

In response to determining that the first split snoop directory associated with the first power domain is not already powered up (i.e., determination block1304=“No”), the processing device may power up the first split snoop directory in block1314. In some aspects, the processing device may perform the operations in block1314for N power domains and N split snoop directories.

In response to determining that the first split snoop directory associated with the first power domain is already powered up (i.e., determination block1304=“Yes”), the processing device may determine whether the first split snoop directory is enabled in determination block1306. In some aspects, the processing device may perform the operations in determination block1306for N power domains and N split snoop directories.

In response to determining that the first split snoop directory is not enabled (i.e., determination block1306=“No”) or after powering up the first split snoop directory in block1314, the processing device may trigger tag initialization for the first split snoop directory associated with the first power domain, and trigger enabling the first split snoop directory associated with the first power domain in block1308. In some aspects, the processing device may perform the operations in block1308for N power domains and N split snoop directories.

In block1310, the processing device may enable the first split snoop directory associated with the first power domain. In some aspects, the processing device may perform the operations in block1310for N power domains and N split snoop directories.

In response to determining that the first split snoop directory associated with the first power domain is enabled (i.e., determination block1306=“Yes”) or after enabling the first split snoop directory in block1310, the processing device may send an acknowledgment of enablement of the first split snoop directory in block1312. In some aspects, the processing device may perform the operations in block1312for N power domains and N split snoop directories.

FIG. 14illustrates a method1400for implementing split snoop directory disabling for multiple power domains with multicore processor state signaling according to an aspect. The method1400may be implemented for any number N power domains in which N is an integer greater than 1. The method1400may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1400is referred to herein as a “processing device.” In various aspects, the method1400may be implemented as part of, in extension of, in conjunction with, or separate from the method700described with reference toFIG. 7.

In block1402, the processing device may receive a condition for changing a first power domain (e.g., power domain400a,400binFIGS. 4 and 5) to a low power state, including power down and retention states. Receiving a power down, “OFF”, or retention (i.e., “RET”) condition may be based on monitoring or receiving a signal of a power state, a power draw, a temperature, and/or input/output activity of a component of the first power domain, including any of a multicore processor (e.g., multicore processor14a,14b,14cinFIGS. 4 and 5), a processor core (e.g., processor core300a,300b,300c,300d,300e,300finFIGS. 4 and 5), and a processor cache including a private cache (e.g., private cache302a,302b,302c,302d,302e,302finFIGS. 4 and 5) or a shared cache (e.g., shared cache304a,304b,304cinFIGS. 4 and 5). A decrease or cessation in a monitored level of power draw, temperature, and/or input/output activity, may indicate to the processing device that a power down or retention event has occurred in the first power domain. In some aspects, the processing device may perform the operations in block1402for N power domains.

In determination block1404, the processing device may determine whether the condition for changing to a low power state is for a last powered processor cache of the first power domain. In other words, the processor may determine whether changing to a low power state, either by powering down or putting into retention the processor cache, would result in all of the processor caches of the first power domain in an “OFF” or “RET” power state and none in an “ON” power state. In some aspects, the processing device may perform the operations in block1404for N power domains.

In response to determining that the condition for changing to a low power state is not for a last powered processor cache (i.e., determination block1404=“No”), the processing device may leave the first split snoop directory enabled in block1410. In some aspects, the processing device may perform the operations in block1410for N power domains and N split snoop directories.

In response to determining that the condition for changing to a low power state is for a last powered processor cache (i.e., determination block1404=“Yes”), the processing device may disable the first split snoop directory associated with the first power domain in block1406. In some aspects, the processing device may perform the operations in block1406for N power domains and N split snoop directories.

In block1408, the processing device may power down or put into retention the first split snoop directory associated with the first power domain. In some aspects, the processing device may perform the operations in block1408for N power domains and N split snoop directories.

In the methods700,1300,1400described herein, the transmission (i.e., sending and receiving) of signals, requests, and acknowledgements may occur between the split snoop directory power controllers (e.g., the split snoop directory power controllers404a,404binFIGS. 4 and 5) and the power domain (e.g., the power domain400a,400binFIGS. 4 and 5).

FIG. 15illustrates a method1500for implementing split snoop directories for multiple power domains according to an aspect. The method1500may be implemented for any number N power domains in which N is an integer greater than 1. The method1500may be implemented in a computing device in software executing in a processor (e.g., the processor14inFIGS. 1 and 2), in general purpose hardware, in dedicated hardware (e.g., split snoop directory power controllers404a,404band/or processor cache power controllers402a,402b,402cinFIGS. 4 and 5), or in a combination of a processor and dedicated hardware, such as a processor executing software within a split snoop directory system that includes other individual components. In order to encompass the alternative configurations enabled in the various aspects, the hardware implementing the method1500is referred to herein as a “processing device.”

In block1502, the processing device may initialize multiple split snoop directories (e.g., split snoop directory310a,310binFIGS. 3-5) each corresponding to one power domain (e.g., power domain400a,400binFIGS. 4 and 5). In various aspects, the processing device may initialize the first split snoop directory for the first power domain and the second split snoop directory for the second power domain. The first power domain may include a first plurality of processor caches (e.g., private cache302a,302b,302c,302d,302e,302fand/or shared cache304a,304b,304cinFIGS. 4 and 5) and the second power domain include at least one processor cache. In some aspects, the processing device may perform the operations in block1502for N (i.e., first, second, third, fourth, etc.) power domains and N (i.e., first, second, third, fourth, etc.) split snoop directories.

In block1504, the processing device may implement one or more of the methods700,800,900,1000,1100,1200,1300,1400described with reference toFIGS. 7-14, individually and/or in parallel for each power domain and corresponding split snoop directory. This may include the first power domain and corresponding first split snoop directory and the second power domain and corresponding second split snoop directory. In some aspects, the processing device may perform the operations in block1504for N power domains and N split snoop directories.

The various aspects (including, but not limited to, aspects described above with reference toFIGS. 1-15) may be implemented in a wide variety of computing systems including mobile computing devices, an example of which suitable for use with the various aspects is illustrated inFIG. 16. The mobile computing device1600may include a processor1602coupled to a touchscreen controller1604and an internal memory1606. The processor1602may be one or more multicore integrated circuits designated for general or specific processing tasks. The internal memory1606may be volatile or non-volatile memory, and may also be secure and/or encrypted memory, or unsecure and/or unencrypted memory, or any combination thereof. Examples of memory types that can be leveraged include but are not limited to DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller1604and the processor1602may also be coupled to a touchscreen panel1612, such as a resistive-sensing touchscreen, capacitive-sensing touchscreen, infrared sensing touchscreen, etc. Additionally, the display of the computing device1600need not have touch screen capability.

The mobile computing device1600may have one or more radio signal transceivers1608(e.g., Peanut, Bluetooth, Zigbee, Wi-Fi, RF radio) and antennae1610, for sending and receiving communications, coupled to each other and/or to the processor1602. The transceivers1608and antennae1610may be used with the above-mentioned circuitry to implement the various wireless transmission protocol stacks and interfaces. The mobile computing device1600may include a cellular network wireless modem chip1616that enables communication via a cellular network and is coupled to the processor.

The mobile computing device1600may include a peripheral device connection interface1618coupled to the processor1602. The peripheral device connection interface1618may be singularly configured to accept one type of connection, or may be configured to accept various types of physical and communication connections, common or proprietary, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface1618may also be coupled to a similarly configured peripheral device connection port (not shown).

The mobile computing device1600may also include speakers1614for providing audio outputs. The mobile computing device1600may also include a housing1620, constructed of a plastic, metal, or a combination of materials, for containing all or some of the components described herein. The mobile computing device1600may include a power source1622coupled to the processor1602, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to the peripheral device connection port to receive a charging current from a source external to the mobile computing device1600. The mobile computing device1600may also include a physical button1624for receiving user inputs. The mobile computing device1600may also include a power button1626for turning the mobile computing device1600on and off.

The various aspects (including, but not limited to, aspects described above with reference toFIGS. 1-15) may be implemented in a wide variety of computing systems include a laptop computer1700an example of which is illustrated inFIG. 17. Many laptop computers include a touchpad touch surface1717that serves as the computer's pointing device, and thus may receive drag, scroll, and flick gestures similar to those implemented on computing devices equipped with a touch screen display and described above. A laptop computer1700will typically include a processor1711coupled to volatile memory1712and a large capacity nonvolatile memory, such as a disk drive1713of Flash memory. Additionally, the computer1700may have one or more antenna1708for sending and receiving electromagnetic radiation that may be connected to a wireless data link and/or cellular telephone transceiver1716coupled to the processor1711. The computer1700may also include a floppy disc drive1714and a compact disc (CD) drive1715coupled to the processor1711. In a notebook configuration, the computer housing includes the touchpad1717, the keyboard1718, and the display1719all coupled to the processor1711. Other configurations of the computing device may include a computer mouse or trackball coupled to the processor (e.g., via a USB input) as are well known, which may also be used in conjunction with the various aspects.

The various aspects (including, but not limited to, aspects described above with reference toFIGS. 1-15) may also be implemented in fixed computing systems, such as any of a variety of commercially available servers. An example server1800is illustrated inFIG. 18. Such a server1800typically includes one or more multicore processor assemblies1801coupled to volatile memory1802and a large capacity nonvolatile memory, such as a disk drive1804. As illustrated inFIG. 18, multicore processor assemblies1801may be added to the server1800by inserting them into the racks of the assembly. The server1800may also include a floppy disc drive, compact disc (CD) or digital versatile disc (DVD) disc drive1806coupled to the processor1801. The server1800may also include network access ports1803coupled to the multicore processor assemblies1801for establishing network interface connections with a network1805, such as a local area network coupled to other broadcast system computers and servers, the Internet, the public switched telephone network, and/or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network).

Computer program code or “program code” for execution on a programmable processor for carrying out operations of the various aspects may be written in a high level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, a Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or programs stored on a computer readable storage medium as used in this application may refer to machine language code (such as object code) whose format is understandable by a processor.

The preceding description of the disclosed aspects is provided to enable any person skilled in the art to make or use the claims. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the aspects and implementations described herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.