High-speed transmission system, signal redriver, and control method of signal redriver

The high-speed transmission system includes a transmitting device, a receiving device, and the signal redriver. The signal redriver includes a terminal resistor. A high-speed receiving end and a high-speed transmitting end of the signal redriver are respectively coupled to a high-speed transmitting end of the transmitting device and a high-speed receiving end of the receiving device. The signal redriver is coupled to a control signal transceiving end of the transmitting device and a control signal transceiving end of the receiving device. The signal redriver monitors a control signal transmitted between the transmitting device and the receiving device and determines whether to enter a SLEEP mode based on the control signal. The terminal resistor of the signal redriver in the SLEEP mode is continuously coupled to the high-speed receiving end of the signal redriver.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan patent application serial no. 110124074, filed on Jun. 30, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to a transmission system, and particularly relates to a high-speed transmission system, a signal redriver, and a control method of the signal redriver.

Description of Related Art

A signal redriver (which is also referred to as a repeater) may improve transmission quality of signals transmitted between a transmitting device and a receiving device. For instance, the signal redriver may be applied in a peripheral component interconnect express (PCIe) bus. However, the signal redriver currently applied in the PCIe bus does not have a SLEEP mode with extremely low power consumption. In order to save power, the entire signal redriver may be turned off according to the related art. If the signal redriver is turned off directly, a terminal resistor of the signal redriver may not comply with a PCIe specification. Besides, after the entire signal redriver is turned off, a start-up time required for turning on the signal redriver may be overly long. The overly long start-up time may lead to connection failure of a PCIe device or PCIe disconnection.

The information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the related art that is already known to a person of ordinary skill in the art. Further, the information disclosed in the Background section does not mean that one or more problems to be resolved by one or more embodiments of the disclosure was acknowledged by a person of ordinary skill in the art.

SUMMARY

The disclosure is directed to a high-speed transmission system, a signal redriver, and a control method of the signal redriver, where the signal redriver may enter a SLEEP mode to reduce power consumption.

In an embodiment of the disclosure, the high-speed transmission system includes a transmitting device, a receiving device, and a signal redriver. The transmitting device has a first high-speed transmitting end and a first control signal transceiving end. The receiving device has a first high-speed receiving end and a second control signal transceiving end. The second control signal transceiving end is coupled to the first control signal transceiving end. The signal redriver includes a terminal resistor. The signal redriver is coupled between the transmitting device and the receiving device. The signal redriver has a second high-speed receiving end coupled to the first high-speed transmitting end of the transmitting device, and a second high-speed transmitting end coupled to the first high-speed receiving end of the receiving device. The signal redriver is coupled to the first control signal transceiving end and the second control signal transceiving end. The signal redriver monitors a control signal transmitted between the first control signal transceiving end of the transmitting device and the second control signal transceiving end of the receiving device. The signal redriver determines whether to enter a SLEEP mode based on the control signal. The terminal resistor of the signal redriver is continuously coupled to the second high-speed receiving end of the signal redriver in the SLEEP mode.

In an embodiment of the disclosure, the signal redriver includes a redriver circuit, a terminal resistor, a switch and a monitoring circuit. The redriver circuit has an input end coupled to a high-speed receiving end of the signal redriver. An output end of the redriver circuit is coupled to a high-speed transmitting end of the signal redriver. The terminal resistor and the switch are connected in series between the high-speed receiving end of the signal redriver and a reference voltage. The monitoring circuit is coupled to a first control signal transceiving end of a transmitting device and a second control signal transceiving end of a receiving device. The monitoring circuit is configured to monitor a control signal transmitted between the first control signal transceiving end of the transmitting device and the second control signal transceiving end of the receiving device to determine whether to enter a SLEEP mode. The monitoring circuit in the SLEEP mode continuously turns on the switch, and the monitoring circuit in a DISCONNECT mode turns off the switch.

In an embodiment of the disclosure, the control method of the signal redriver includes: providing the signal redriver between a transmitting device and a receiving device, wherein a first high-speed transmitting end of the transmitting device and a first high-speed receiving end of the receiving device are respectively coupled to a second high-speed receiving end and a second high-speed transmitting end of the signal redriver; monitoring a control signal transmitted between a first control signal transceiving end of the transmitting device and a second control signal transceiving end of the receiving device by the signal redriver; determining whether the signal redriver enters a SLEEP mode based on the control signal; and making a terminal resistor of the signal redriver to be continuously coupled to the second high-speed receiving end of the signal redriver in the SLEEP mode.

Based on the above description, in the high-speed transmission system, the signal redriver, and the control method of the signal redriver provided in one or more of the embodiments of the disclosure, it is possible to determine whether the signal redriver enters the SLEEP mode by monitoring the control signal transmitted between the transmitting device and the receiving device, and in the SLEEP mode, the terminal resistor of the signal redriver is continuously coupled to the high-speed receiving end of the signal redriver, so as to be coupled to the high-speed transmitting end of the transmitting device. As such, the power consumption of the signal redriver is reduced while a terminal impedance of the transmitting device is maintained.

DESCRIPTION OF THE EMBODIMENTS

A term “couple” used in the full text of the disclosure (including the claims) refers to any direct and indirect connections. For example, if a first device is described to be coupled to a second device, it is interpreted as that the first device is directly coupled to the second device, or the first device is indirectly coupled to the second device through other devices or connection means. “first”, “second”, etc. mentioned in the specification and the claims are merely used to name discrete components and should not be regarded as limiting the upper or lower bound of the number of the components, nor is it used to define a manufacturing order or setting order of the components. Moreover, wherever possible, components/members/steps using the same referential numbers in the drawings and description refer to the same or like parts. Components/members/steps using the same referential numbers or using the same terms in different embodiments may cross-refer related descriptions.

FIG.1is a schematic diagram of a high-speed transmission system100according to an embodiment of the disclosure. According to an actual design, the high-speed transmission system100may be a peripheral component interconnect express (PCIe) system or other transmission systems. In the embodiment shown inFIG.1, the high-speed transmission system100includes a transmitting device110, a receiving device120, and a signal redriver130. The transmitting device110has a high-speed transmitting end S1and a control signal transceiving end t1. The receiving device120has a high-speed receiving end R2and a control signal transceiving end t2. The signal redriver130is coupled between the transmitting device110and the receiving device120. For example, a high-speed receiving end R1of the signal redriver130is coupled to the high-speed transmitting end S1of the transmitting device110, and a high-speed transmitting end S2of the signal redriver130is coupled to the high-speed receiving end R2of the receiving device120. According to a design requirement, the signal redriver130may be provided in the form of a circuit board or a cable, which is not limited in the embodiment. For example, in some embodiments, the high-speed receiving end R2of the receiving device120may be coupled to the high-speed transmitting end S1of the transmitting device110through a cable, and the signal redriver130may be configured in this cable. In some other embodiments, the transmitting device110, the receiving device120and the signal redriver130may be three integrated circuits. In still other embodiments, the transmitting device110and the signal redriver130may be integrated into one integrated circuit, and the receiving device120may be another integrated circuit. In other embodiments, the transmitting device110may be an integrated circuit, and the receiving device120and the signal redriver130may be integrated into another integrated circuit.

A control signal CS is transmitted between the control signal transceiving end t1of the transmitting device110and the control signal transceiving end t2of the receiving device120. According to an actual design, in some embodiments, the transmitting device110may transmit the control signal CS to the control signal transceiving end t2of the receiving device120through the control signal transceiving end t1. In other embodiments, the receiving device120may transmit the control signal CS to the control signal transceiving end t1of the transmitting device110through the control signal transceiving end t2. In still some embodiments, other circuits that are not shown inFIG.1may transmit the control signal CS to the control signal transceiving end t1of the transmitting device110and the control signal transceiving end t2of the receiving device120. Based on the control signal CS, the transmitting device110and/or the receiving device120may decide whether to enter a power saving mode.

The signal redriver130may monitor the control signal CS transmitted between the control signal transceiving end t1of the transmitting device110and the control signal transceiving end t2of the receiving device120. This embodiment does not limit the meaning of “monitor”. The meaning of the word “monitor” in this embodiment includes but is not limited to “snoop”, “listen” or “capture”. Based on the control signal CS, the signal redriver130may decide whether to enter a SLEEP mode. When the signal redriver130enters the SLEEP mode from a STANDBY mode (a normal operating state), a terminal resistor inside the signal redriver130will be continuously coupled to the high-speed receiving end R1of the signal redriver130, and most of the circuits inside the signal redriver130are turned off to reduce the power consumption of the signal redriver130. Since the terminal resistor of the signal redriver130is continuously coupled to the high-speed receiving end R1of the signal redriver130in the SLEEP mode, the signal redriver130in the SLEEP mode still complies with terminal specifications of the high-speed transmission system100. After the signal redriver130returns to the STANDBY mode (the normal operating state) from the SLEEP mode, a response time of re-activating the signal redriver130may meet a time specification of the high-speed transmission system100.

For example,FIG.2is a schematic diagram of a high-speed transmission system200according to another embodiment of the disclosure. In the embodiment shown inFIG.2, the high-speed transmission system200includes a PCIe root complex device210, a PCIe endpoint device220, and a signal redriver230. According to an actual design, in some embodiments, the PCIe root complex device210shown inFIG.2may be an implementation example of the transmitting device110shown inFIG.1, or the PCIe root complex device210shown inFIG.2may be an internal component of the transmitting device110shown inFIG.1. The PCIe endpoint device220shown inFIG.2may be an implementation example of the receiving device120shown inFIG.1, or the PCIe endpoint device220shown inFIG.2may be an internal component of the receiving device120shown inFIG.1. According to the actual design, the signal redriver230shown inFIG.2may be deduced by analogy with reference to the related description of the signal redriver130shown inFIG.1, and (or) the signal redriver130shown inFIG.1may be deduced by analogy with reference to the related description of the signal redriver230shown inFIG.2.

In the embodiment shown inFIG.2, the high-speed transmitting end S1of the PCIe root complex device210may be coupled to the high-speed receiving end R2of the PCIe endpoint device220through a PCIe bus and the signal redriver230. In the embodiment shown inFIG.2, the high-speed transmission system200further includes a clock source240. Clock ends of the PCIe root complex device210and the PCIe endpoint device220are commonly coupled to an output end of the clock source240to receive a reference clock signal CLK_REF. According to an actual design, a clock request signal CLKREQ #shown inFIG.2may be an implementation example of the control signal CS shown inFIG.1, or the clock request signal CLKREQ #shown inFIG.2may be one of a plurality of components of the control signal CS shown inFIG.1. The PCIe root complex device210and/or the PCIe endpoint device220may send the clock request signal CLKREQ #that complies with the PCIe specification to the clock source240through the control signal transceiving ends. According to the clock request signal CLKREQ #, the clock source240may determine whether to generate the reference clock signal CLK_REF to the PCIe root complex device210and the PCIe endpoint device220. For example, when the clock request signal CLKREQ #is at a first logic level (for example, a high logic level), the reference clock signal CLK_REF is cancelled, i.e., the PCIe root complex device210and/or the PCIe endpoint device220enter the power saving mode (for example, an L1.2 low power consumption link state under the PCIe specification). When the clock request signal CLKREQ #is at a second logic level (for example, a low logic level), the reference clock signal CLK_REF is provided to the PCIe root complex device210and the PCIe endpoint device220, i.e., both of the PCIe root complex device210and the PCIe endpoint device220operate in a normal mode. The clock request signal CLKREQ #is a signal that complies with the PCIe specification, so that the details of the clock request signal CLKREQ #are not repeated here.

In the embodiment, the signal redriver230may monitor the clock request signal CLKREQ #(the control signal CS) transmitted between the PCIe root complex device210, the PCIe endpoint device220, and the clock source240. In this way, the signal redriver230may switch a working mode according to the clock request signal CLKREQ #. For example, in the embodiment, when the clock request signal CLKREQ #is at the first logic level (such as the high logic level), the signal redriver230may enter the SLEEP mode (in the SLEEP mode, the terminal resistor of the signal redriver230is continuously coupled to the high-speed receiving end R1of the signal redriver230). When the clock request signal CLKREQ #is at the second logic level (for example, the low logic level), the signal redriver230may end the SLEEP mode.

FIG.3is a schematic circuit block diagram of a high-speed transmission system300according to still another embodiment of the disclosure. The high-speed transmission system300shown inFIG.3includes a transmitting device310, a receiving device320, and a signal redriver330. According to an actual design, in some embodiments, the PCIe root complex device210shown inFIG.2may be an implementation example of the transmitting device310shown inFIG.3, or the PCIe root complex device210shown inFIG.2may be an internal component of the transmitting device310shown inFIG.3. The PCIe endpoint device220shown inFIG.2may be an implementation example of the receiving device320shown inFIG.3, or the PCIe endpoint device220shown inFIG.2may be an internal component of the receiving device320shown inFIG.3. In some other embodiments, the transmitting device310and the receiving device320shown inFIG.3may be deduced by analogy with reference to the related descriptions of the transmitting device110and the receiving device120shown inFIG.1, or the transmitting device110and the receiving device120shown inFIG.1may be deduced by analogy with reference to the related descriptions of the transmitting device310and the receiving device320shown inFIG.3, so that details thereof are not repeated.

According to an actual design, in some embodiments, the signal redriver230shown inFIG.2may be deduced by analogy with reference to the related description of the signal redriver330shown inFIG.3, and/or the signal redriver330shown inFIG.3may be deduced by analogy with reference to the related description of the signal redriver230shown inFIG.2. In some other embodiments, the signal redriver330shown inFIG.3may be deduced by analogy with reference to the related description of the signal redriver130shown inFIG.1, or the signal redriver130shown inFIG.1may be deduced by analogy with reference to the related description of the signal redriver330shown inFIG.3. In the embodiment shown inFIG.3, the signal redriver330includes a redriver circuit331, a monitoring circuit332, a terminal resistor RT, and a switch SW. The monitoring circuit332may include a microcontroller or other control/processing circuits.

The terminal resistor RT and the switch SW may be connected in series between the high-speed receiving end R1of the signal redriver330and a reference voltage VR. For example, a first end of the terminal resistor RT is coupled to the reference voltage VR, a first end of the switch SW is coupled to a second end of the terminal resistor RT, and a second end of the switch SW is coupled to the high-speed receiving end R1of the signal redriver330. It should be noted that the connection manner of the terminal resistor RT and the switch SW shown inFIG.3is just an example. In other embodiments, positions of the terminal resistor RT and the switch SW may be exchanged or the terminal resistor RT and the switch SW may be coupled to the high-speed receiving end R1in other forms, which is not limited by the disclosure. The reference voltage VR may be, for example, a ground voltage or other fixed voltages, which is not limited in the embodiment.

An input end of the redriver circuit331is coupled to the high-speed receiving end R1of the signal redriver330. An output end of the redriver circuit331is coupled to the high-speed transmitting end S2of the signal redriver330. The redriver circuit331may increase quality of signals on a high-speed transmission channel between the transmitting device310and the receiving device320.

The monitoring circuit332may monitor the control signal CS transmitted between the control signal transceiving end of the transmitting device310and the control signal transceiving end of the receiving device320to determine whether the signal redriver330enters the SLEEP mode. In an application situation where the transmitting device310and the receiving device320are PCIe devices, the control signal CS may include the clock request signal CLKREQ #that complies with the PCIe specification and/or other PCIe signals. The monitoring circuit332may control the switch SW according to the control signal CS. When the control signal CS (for example, the clock request signal CLKREQ #) is at the first logic level, the signal redriver330may enter the SLEEP mode; and when the control signal CS (for example, the clock request signal CLKREQ #) is at the second logic level, the signal driver330may end the SLEEP mode. When the signal redriver330is in the SLEEP mode, the monitoring circuit332may continuously turn on the switch SW, i.e., the terminal resistor RT may be continuously coupled to the high-speed receiving end R1of the signal redriver330. When the signal redriver330ends the SLEEP mode and returns to the STANDBY mode (the normal operating state), the monitoring circuit332continuously turns on the switch SW. When the signal redriver330is operated in either the STANDBY mode or an ACTIVE mode, the monitoring circuit332continuously turns on the switch SW. When the transmitting device310and (or) the receiving device320are (is) disconnected from the signal redriver330, the signal redriver330may enter a DISCONNECT mode. According to an actual design, in some embodiments, the monitoring circuit332in the DISCONNECT mode may turn off the switch SW.

In the embodiment shown inFIG.3, according to the design requirement, the signal redriver330may further include a receiver detector333. The receiver detector333is coupled to the high-speed transmitting end S2of the signal redriver330. The receiver detector333may detect whether the high-speed transmitting end S2of the signal redriver330is coupled to the high-speed receiving end R2of the receiving device320, and output a detection signal RD.

In the embodiment, the redriver circuit331may include an equalizer circuit311and a driver circuit312. An input end of the equalizer circuit311may be coupled to the high-speed receiving end R1of the signal redriver330. The equalizer circuit311may be used to optimize a transmission signal received by the signal redriver330. An input end of the driver circuit312may be coupled to an output end of the equalizer circuit311. An output end of the driver circuit312may be coupled to the high-speed transmitting end S2of the signal redriver330. In the embodiment shown inFIG.3, according to a design requirement, the redriver circuit331may further include a signal detector313. The signal detector313is coupled to the output end of the equalizer circuit311. The signal detector313may detect whether there is a valid signal at the output end of the equalizer circuit311and output a valid detection signal SD.

According to different design requirements, blocks of the aforementioned monitoring circuit332, the receiver detector333, and/or the signal detector313may be implemented in the form of hardware, firmware, and software (i.e., programs) or a combination thereof.

In terms of hardware, the aforementioned monitoring circuit332, the receiver detector333and/or the signal detector313may be implemented by logic circuits on an integrated circuit. The related functions of the aforementioned monitoring circuit332, the receiver detector333and/or the signal detector313may be implemented as hardware by using hardware description languages (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the aforementioned monitoring circuit332, the receiver detector333and/or the signal detector313may be implemented by one or a plurality of controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processors (DSP), field programmable gate arrays (FPGA), and/or various logic blocks, modules and circuits in other processing units.

In terms of software and/or firmware, relevant functions of the monitoring circuit332, the receiver detector333, and/or the signal detector313may be implemented as programming codes. For example, the monitoring circuit332, the receiver detector333, and/or the signal detector313may be implemented as general programming languages (such as C, C++, or assembly languages) or other suitable programming languages. The programming codes may be recorded/stored in a “non-transitory computer readable medium”. In some embodiments, the non-transitory computer readable medium includes, for example, a read-only memory (ROM), a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, and/or a storage device. The storage device includes a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. A central processing unit (CPU), a controller, a microcontroller, or a microprocessor may read and execute the programming code from the non-transitory computer readable medium, thereby realizing the relevant functions of the monitoring circuit332, the receiver detector333, and/or the signal detector313.

FIG.4is a schematic diagram of a finite-state machine of the signal redriver330shown inFIG.3according to an embodiment of the disclosure. In the embodiments shown inFIG.3andFIG.4, the signal redriver330may have a plurality of working modes, and may switch enabling states of internal circuit elements in different working mode states. For example, in the embodiment shown inFIG.4, the working mode of the signal redriver330may include an OFF mode410, a DISCONNECT mode420, a STANDBY mode430, an ACTIVE mode440and a SLEEP mode450. It should be noted that the working modes described in the embodiment are only an example. In other embodiments, the signal redriver330may also include other working modes or have fewer working modes.

In the embodiment, the signal redriver330may switch the working mode to the OFF mode410or the DISCONNECT mode420according to an enabling signal EN input from external. For example, when the signal redriver330receives the enabling signal EN to be disabled, the signal redriver330may enter the OFF mode410from any mode. In the OFF mode410, when the signal redriver330receives the enabling signal EN to be enabled, the OFF mode410may be ended to enter the DISCONNECT mode420.

In the DISCONNECT mode420, the signal redriver330may determine whether to switch the working mode of the signal redriver330from the DISCONNECT mode420to the STANDBY mode430or from the STANDBY mode430to the DISCONNECT mode420according to the detection signal RD output by the receiver detector333. For example, when the detection signal RD output by the receiver detector333indicates that the high-speed transmitting end S2of the signal redriver330is coupled to the high-speed receiving end of the receiving device320and the signal redriver330is in the DISCONNECT mode420, the working mode of the signal redriver330may be switched from the DISCONNECT mode420to the STANDBY mode430. When the detection signal RD output by the receiver detector333indicates that the high-speed transmitting end S2of the signal redriver330is not coupled to any receiving device and the signal redriver330is in the STANDBY mode430(or the SLEEP mode450), the working mode of the signal redriver330may be switched from the STANDBY mode430(or the SLEEP mode450) to the DISCONNECT mode420.

In the STANDBY mode, the signal redriver330may determine whether to switch the working mode of the signal redriver330from the STANDBY mode430to the ACTIVE mode440according to the valid detection signal SD output by the signal detector313. For example, when the valid detection signal SD output by the signal detector313indicates that the output of the equalizer circuit311is a valid signal (i.e., the high-speed receiving end R1of the signal redriver330receives a valid signal from the transmitting device310) and the signal redriver330is in the STANDBY mode430, the working mode of the signal redriver330may be switched from the STANDBY mode430to the ACTIVE mode440(a normal working mode). When the valid detection signal SD output by the signal detector313indicates that the equalizer circuit311does not output a valid signal (i.e., the high-speed receiving end R1of the signal redriver330does not receive a valid signal from the transmitting device310) and the signal redriver330is in the ACTIVE mode440, the working mode of the signal redriver330may be switched from the ACTIVE mode440back to the STANDBY mode430.

In the STANDBY mode430, the signal redriver330may determine whether to switch the working mode of the signal redriver330from the STANDBY mode430to the SLEEP mode450according to the control signal CS transmitted between the transmitting device310and the receiving device320. For example, when the control signal CS transmitted between the transmitting device310and the receiving device320is a preset first logic level and the signal redriver330is in the STANDBY mode430, the working mode of the signal redriver330may be switched from STANDBY mode430to the SLEEP mode450. When the control signal CS transmitted between the transmitting device310and the receiving device320is a preset second logic level and the signal redriver330is in the SLEEP mode450, the working mode of the signal redriver330is switched back from the SLEEP mode450to the STANDBY mode430. In addition, in the SLEEP mode450, when the detection signal RD output by the receiver detector333indicates that the receiving device320originally coupled to the high-speed transmitting end S2of the signal redriver330has been disconnected, the working mode of the signal redriver330may be switched from the SLEEP mode450back to the DISCONNECT mode420. In some embodiments, the power consumption of the signal redriver330in the SLEEP mode450may be less than the power consumption in the STANDBY mode430.

In another example, Table 1 below is a table illustrating enabling states of the internal circuit components of the signal redriver330shown inFIG.3according to an embodiment of the disclosure. A vertical axis shown in Table 1 represents the internal circuit components of the signal redriver330shown inFIG.3, including the terminal resistor RT, the equalizer circuit311, the driver circuit312, the signal detector313, and the receiver detector333. A horizontal axis shown in Table 1 represents the working modes of the signal redriver330, including the DISCONNECT mode420, the ACTIVE mode440, the STANDBY mode430, and the SLEEP mode450shown inFIG.4. “X” shown in Table 1 represents “disable”, “turn off” or “disconnect”. “O” shown in Table 1 represents “enable”, “turn on” or “connect”. The enabling states of the circuit components shown in Table 1 are only an example, and the embodiment is not limited thereto.

TABLE 1working modes and enabling relationship of theinternal components of the signal redriver 330DISCONNECTACTIVESTANDBYSLEEPTerminal resistorX◯◯◯Equalizer circuitX◯◯XDriver circuitX◯XXSignal detectorX◯◯XReceiver detector◯X◯◯

Referring toFIG.3,FIG.4, and Table 1, in the embodiment, when the signal redriver330is in the DISCONNECT mode420, for example, only the receiver detector333is enabled to detect a coupling state of the high-speed transmitting end S2of the signal redriver330. In the DISCONNECT mode420, the switch SW is turned off (i.e., the terminal resistor RT is disconnected from the high-speed receiving end R1of the signal redriver330), and the equalizer circuit311, the driver circuit312, the signal detector313and the receiver detector333are disabled or turned off. When the signal redriver330is in the ACTIVE mode440, the receiver detector333may be disabled to reduce the power consumption of the signal redriver330in the ACTIVE mode440. In the ACTIVE mode440, the switch SW is turned on (i.e., the terminal resistor RT is connected to the high-speed receiving end R1of the signal redriver330), and the equalizer circuit311, the driver circuit312, and the signal detector313are enabled or turned on.

When the signal redriver330is in the STANDBY mode430, for example, only the driver circuit312is disabled. In the STANDBY mode430, the switch SW is turned on (i.e., the terminal resistor RT is connected to the high-speed receiving end R1of the signal redriver330), and the equalizer circuit311, the signal detector313, and the receiver detector333are enabled or turned on. When the signal redriver330is in the SLEEP mode450, the receiver detector333is enabled and the terminal resistor RT is connected to the high-speed receiving terminal R1of the signal redriver330(i.e., the switch SW is turned on). In the SLEEP mode450, the equalizer circuit311, the driver circuit312, and the signal detector313are disabled or turned off.

In other words, the equalizer circuit311in the signal redriver330is enabled in the ACTIVE mode440and the STANDBY mode430, and disabled in the DISCONNECT mode420and the SLEEP mode450. The driver circuit312is enabled in the ACTIVE mode440, and disabled in the DISCONNECT mode420, the STANDBY mode430, and the SLEEP mode450. The signal detector313is enabled in the ACTIVE mode440and the STANDBY mode430, and disabled in the DISCONNECT mode420and the SLEEP mode450. The receiver detector333is enabled in the DISCONNECT mode420, the STANDBY mode430, and the SLEEP mode450, and may be disabled in the ACTIVE mode440. In the embodiment, the monitoring circuit332may control the switch SW to continuously turn on the switch SW when the signal redriver330is in the SLEEP mode450, the STANDBY mode430, and the ACTIVE mode440, and turn off the switch SW when the signal redriver330is in the DISCONNECT mode420. In this way, when the signal redriver330is in the SLEEP mode450, the redriver circuit331may be disabled to reduce the power consumption of the signal redriver330under the premise of maintaining the terminal resistor RT to be enabled.

FIG.5is a schematic flowchart illustrating a control method of a signal redriver according to an embodiment of the disclosure. According to an actual design, related description of the control method shown inFIG.5may be adapted to the signal redriver130shown inFIG.1, the signal redriver230shown inFIG.2, and/or the signal redriver330shown inFIG.3. Here, the circuit block diagram shown inFIG.1is used to assist explaining the control method shown inFIG.5.

With reference toFIG.1andFIG.5, in step S510, the signal redriver130is provided between the transmitting device110and the receiving device120, where the high-speed transmitting end S1of the transmitting device110is coupled to the high-speed receiving end R1of the signal redriver130, and the first high-speed receiving end R2of the receiving device120is coupled to the high-speed transmitting end S2of the signal redriver130. In step S520, the signal redriver130monitors the control signal CS transmitted between the control signal transceiving end t1of the transmitting device110and the control signal transceiving end t2of the receiving device120. In step S530, the signal redriver130determines whether to enter the SLEEP mode450based on the control signal CS. In step S540, the signal redriver130makes the terminal resistor (for example, the terminal resistor RT shown inFIG.3) of the signal redriver130in the SLEEP mode450to be continuously coupled to the high-speed receiving end R1of the signal redriver130.

In summary, in the high-speed transmission system and the signal redriver provided in one or more of the embodiments of the disclosure, it is possible to determine whether the signal redriver enters the SLEEP mode by monitoring the control signal CS (e.g., the clock request signal CLKREQ #) transmitted between the transmitting device and the receiving device, and in the SLEEP mode450, the terminal resistor RT of the signal redriver may be continuously coupled to the high-speed receiving end R1of the signal redriver. The power consumption of the signal redriver may be reduced as much as possible on the premise of maintaining a terminal impedance of the high-speed receiving end R1.