Method of making thermally enhanced substrate-base package

An array-type package encasing one or more semiconductor devices. The package includes a dielectric substrate having opposing first and second sides with a plurality of electrically conductive vias and a centrally disposed aperture extending from the first side to the second side. A heat slug has a mid portion extending through the aperture, a first portion adjacent the first side of the substrate with a cross sectional area larger than the cross sectional area of the aperture and an opposing second portion adjacent the second side of the substrate. One or more semiconductor devices are bonded to the first portion of the heat slug and electrically interconnected to the electrically conductive vias. A heat spreader having a first side and an opposing second side is spaced from the semiconductor devices and generally parallel with the heat slug, whereby the semiconductor devices are disposed between the heat spreader and the heat slug. A molding resin encapsulates the semiconductor devices and at least the first side of the substrate, the first portion of the heat slug and the first side of the heat spreader.

U.S. GOVERNMENT RIGHTS

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to packages to encase one or more semiconductor devices, and more particularly to a molded plastic ball grid array package have a substrate base and a heat slug.

2. Description of the Related Art

Enhancing the thermal performance of substrate-based packages for encasing semiconductor devices remains a challenge. Typical substrate-based packages such as land grid array and ball grid array packages typically extract heat through metallic vias. However, the small surface area of the vias limits the amount of heat that is dissipated. It is known to enhance the thermal dissipation of a surface mount package by brazing a heat sink to an aperture extending through the package base as disclosed in U.S. Pat. No. 5,111,277 to Medeiros et al. A package substrate including heat sink is also disclosed in U.S. Pat. No. 5,629,835 to Mahulikar et al. Both U.S. Pat. No. 5,111,277 and U.S. Pat. No. 5,629,835 are incorporated by reference in their entireties herein.

A method for enhancing the electrical properties of a molded plastic package by reducing self and mutual inductance is disclosed in U.S. Pat. No. 5,559,306 to Mahulikar. Parallel metallic plates are disposed within the package body with a semiconductor device disposed therebetween. U.S. Pat. No. 5,559,306 is incorporated by reference in its entirety herein.

There remains, however, a need for a substrate-based package with improved thermal dissipation that may be manufactured in large quantities at low cost.

BRIEF SUMMARY OF THE INVENTION

In accordance with a first embodiment of the invention, there is provided an array-type package to encase one or more semiconductor devices. The package includes a dielectric substrate having opposing first and second sides with a plurality of electrically conductive vias and a centrally disposed aperture extending from the first side to the second side. A heat slug has a mid-portion extending through the aperture, a first portion adjacent the first side of the substrate with a cross sectional area larger than the cross sectional area of the aperture and an opposing second portion adjacent the second side of the substrate. One or more semiconductor devices are bonded to the first portion of the heat slug and electrically interconnected to the electrically conductive vias. A heat spreader having a first side and an opposing second side is spaced from the semiconductor devices and generally parallel with the heat slug, whereby the semiconductor devices are disposed between the heat spreader and the heat slug. A molding resin encapsulates the semiconductor devices and at least the first side of the substrate, the first portion of the heat slug and the first side of the heat spreader.

In accordance with a second embodiment of the invention, there is provided a heat slug array that includes a dielectric substrate having opposing first and second sides and a plurality of apertures arranged in an array and a plurality of interconnected heat slugs. Each heat slug has a first portion and a second portion separated by a mid-portion wherein the mid-portion extends through one of the apertures and the first portion has a perimeter larger than the perimeter of the apertures.

In accordance with a third embodiment of the invention, there is provided a method for the manufacture of an array-type package for encasing one or more semiconductor devices. The method includes the steps of: (a). providing a heat slug array containing a dielectric substrate with a plurality of apertures and a plurality of interconnected heat slugs having opposing first and second portions separated by a mid-portion that extends through one of the apertures wherein the first portion has a perimeter larger than the perimeter of the apertures and multiple tie bars project from the perimeter of the first portion and where a tie bar from one heat slug intersects at least one other tie bar from an adjacent heat slug at an interconnection point; (b). bonding the semiconductor devices to the first portion and electrically interconnecting the semiconductor devices to electrically conductive vias on a first side of the dielectric substrate, the electrically conductive vias extending through the dielectric substrate to an opposing second side thereof; (c). providing an array of heat spreaders having multiple tie bars extending from a perimeter thereof wherein a tie bar from one heat spreader intersects at least one other tie bar from an adjacent heat spreader at an interconnection point; (d). bonding tie bars of the heat slugs to tie bars of the heat spreader such that the semiconductor devices are disposed between one of the heat slugs and one of the heat spreaders; and (e). encapsulating the semiconductor devices and at least a portion of the heat spreaders and heat slugs in a molding resin.

Like reference numbers and designations in the various drawings indicated like elements.

DETAILED DESCRIPTION

For this patent application, a “heat slug” or a “heat sink” is defined as a metallic component having a thermal conductivity greater than the thermal conductivity of a polymer molding resin and a maximum thickness greater than the thickness of a semiconductor device encapsulated in the molding resin. A “heat spreader” is defined as a metallic component having a thermal conductivity greater than the thermal conductivity of a polymer molding resin and a maximum thickness equivalent to or less than the thickness of a semiconductor device encapsulated in the molding resin.

FIG. 1shows in top planar view an array type package10in accordance with the invention. The package is partially broken away to illustrate the components of the package.FIG. 2illustrates the array type package in cross-sectional representation. All array type packages disclosed herein may encapsulate one or more integrated circuit devices, such as silicon base integrated circuit devices, as well as one or more passive devices such as resistors, inductors and capacitors. Multiple devices may be in adjacent or stacked relationship.

Referring toFIGS. 1 and 2, a dielectric substrate12has opposing first14and second16sides. A plurality of electrically conductive vias18extend through the dielectric substrate12. A centrally disposed aperture20also extends through the dielectric substrate12. The aperture may be any shape, such as square, rectangular or circular and has a first perimeter.

A heat slug22is supported by the first side14of dielectric substrate12. The heat slug22has a first portion24and opposing second portion26separated by mid-portion28. The mid-portion28is sized to fit through the centrally disposed aperture20, preferably with limited clearance. The first portion24has a perimeter larger than the perimeter of the centrally disposed aperture20forming a flange overlying the first surface14.

One or more semiconductor devices30or a combination of semiconductor devices and passive devices, such as in a hybrid circuit, are bonded to the first portion24using a suitable die attach bonding material such as a lead- or gold-base solder or metal filled epoxy. The one of more semiconductor devices30are electrically interconnected to electrically conductive vias18through small diameter bond wires32or thin metallic foil strips as used in tape automated bonding.

A heat spreader34having first36and second38opposing sides is spaced apart from the one or more semiconductor devices30with the first side36being generally parallel with the first side24of heat slug22. As illustrated inFIG. 2, first side36and first side24form adjacent sides of two parallel electrically conductive plates with the one or more semiconductor devices30disposed between the parallel plates.

A molding resin40encapsulates the one or more semiconductor devices30, the first portion24of the heat slug22and the first side36of the heat spreader34. The electrically conductive vias18adjacent to the second side16of the dielectric substrate12are electrically interconnected to circuit traces formed on external circuitry, such as a printed circuit board. Electrical interconnection may be by any suitable means including the use of solder balls42. The solder balls are all substantially the same diameter such that a point opposite the second side16of each solder ball is generally coplanar with all the other points opposite the second side16. The solder balls are typically formed from a low melting temperature lead-base solder such as, by weight, 63% tin/37% lead. Preferably, the second portion26of the heat slug22is also coplanar with the opposite points of the solder balls. The second portion may then be soldered to a heat sink or ground external to the package10.

FIGS. 3-6illustrate components useful for the manufacture of the array type package.FIG. 3shows in top planar view andFIG. 4in cross-sectional view a heat slug array44. The heat slug array44includes a plurality of heat slugs22each having a first portion24and second portion26separated by a mid-portion28. The heat slug array44also includes dielectric substrate12having opposing first14and second16sides and centrally disposed apertures20extending therethrough. A mid-portion26of a heat slug22extends through each aperture20. The first portion16has a perimeter larger than the perimeter of the apertures20. Heat slug tie bars46project from the perimeters of the first portions24and tie bars from one heat slug intersect with at least one tie bar from an adjacent heat slug at an intersection point48. As best seen inFIG. 8, the thickness of the tie bars46may be reduced at intersection points48to facilitate singulation.

With reference back toFIG. 4, the heat slugs22are typically bonded to dielectric substrate12by an epoxy or an adhesive tape. The heat slugs are preferably formed from a thermally conductive metal such as a copper alloy and may be pre-plated with a wire bondable material such as a layer of gold or palladium over nickel. Referring toFIGS. 5 and 6, a heat spreader array50has multiple heat spreader tie bars52extending from the perimeter thereof. Tie bars from adjacent heat spreaders are joined together at tie bar intersection points54that may have a reduced thickness to facilitate singulation.

The tie bars generally include an upset portion56so that the second side38is raised a sufficient amount to be exposed following encapsulation with a molding resin and to provide standoff clearance for the wires used in wire bonding. The exposed second side38may be any shape including circular or square. The heat spreader is formed from any metal having high thermal conductivity such as copper, aluminum and their alloys. The metal may be coated with another material to enhance marking contrast. Most preferred is black anodization for an aluminum alloy heat spreader. Peripheral portions58of the heat spreader34may be partially etched to form a step-like configuration to improve mechanical locking into the molding resin.

FIG. 7illustrates in cross-sectional representation an array60of array type packages in accordance with the invention. Heat spreader array50is bonded to heat slug array44such as by an adhesive bond62bonding heat spreader tie bars52to heat slug tie bars46. The array may then be singulated either before or after encapsulation with a molding resin.

Referring toFIGS. 9-11, heat spreader tie bars190may have bumps192to enhance standoff clearance from the wires used for wire bonding. The bumps192are also useful to align and lock the heat spreader in position on heat slug tie bars194. Apertures196may be formed in the heat slug tie bars194to further enhance alignment and lock-in. These bumps are typically formed during the chemical etching process or by coining/punching during the upset process. While the assembly process describes the array of heat slugs and the array of heat spreaders being molded together and subsequently singulated, it is within the scope of the invention for the heat spreaders and the heat slugs to be singulated prior to encapsulation with the molten resin and a pick and place process used to place individual heat slugs and individual heat spreaders in individual mold cavities for wire bonding and encapsulation.

FIG. 12illustrates in cross-sectional representation an alternative embodiment of the invention in which the package200includes a heat slug202that functions as a lead frame. The lead frame202is illustrated in top perspective view inFIG. 13and bottom perspective view inFIG. 14. The lead frame includes a surface-ward projecting portion204and a chip-ward projecting portion206. In addition, the lead frame includes a plurality of tie bars208that typically project outwardly and then downwardly from corners of the lead frame. Referring back toFIG. 12, the lead frame202includes a reduced thickness portion210circumscribing at least a portion of the surface-ward projecting portion204. Surface-ward projecting portion204forms a portion of a top surface212of the package200to facilitate the dissipation of heat. Because the lead frame202is formed from an electrically conductive material, the exposed surface-ward projecting portion204may also be used to conduct electrical signals to and from one or more integrated circuit devices214that are mounted on a central portion of dielectric substrate218. A molding resin216encapsulates the one or more integrated circuit devices214and extends over the reduced thickness portion210effectively locking the lead frame202in place.

The requirements for lead frame202are similar to those for the heat spreader described herein above. The lead frame202is formed from an electrically conductive metal such as copper, a copper alloy, aluminum, an aluminum alloy or an iron/nickel base alloy as sometimes used in lead frames, for example alloy 42 (42% nickel-balance iron) or Kovar (an iron-nickel-cobalt alloy). Since the surface-ward projecting portion204is exposed to the environment, at least the exposed portion of the surface-ward projecting portion is coated with a corrosion resistant material. Preferably, the lead frame202is formed from a copper base alloy and the exposed portion of the surface-ward projecting portion204is coated with black oxide.

Other features of the lead frame202in common with the heat spreader described herein above are that the lead frame may be provided in a web-like form for array requirements. The surface-ward projecting portion204may be rounded or square, or any other desired shape depending on the need. Features may be etched into the lead frame and tie bars to enhance mold locking and alignment of the tie bars. The tie bars are preferably upset to elevate the surface-ward projecting portion and to avoid contacting the wires of a wire bonded package. Portions of the tie bars may be thinned for singulation ease and may have bumps to provide standup clearance from the wire bonds.

The lead frame may be formed from a copper alloy, aluminum alloy or other metal with high thermal conductivity. When formed from an aluminum-base alloy, it may be black anodized or have another coating to improve marking contrast. The lead frames may be provided in a matrix form or singulated for use in a pick and place process. Molding may be as individual packages or as a strip form.

The package200substrate218is formed from a dielectric material and may include a downwardly projecting heat slug as described above. A number of electrically conductive vias220extend through a peripheral portion of the substrate interconnecting wire or tab bonds222to solder balls224. As illustrated, some of the electrically conductive vias provide a path for electrical communication with input/output (I/O) pads formed around the periphery226of the IC device214. Others of the electrically conductive vias220′ form an electrical path between solders balls and the tie bars208. Chip-ward projecting portion206may make electrical contact with a central portion228of the IC device214. In this way, the lead frame202provides at least one, and alternatively both, of a path for thermal conduction and a path for electrical conduction. A thermally conductive grease or other thermal/electrical enhancing material may be disposed between the chip-ward projecting portion206and the central portion228.

WhileFIG. 12illustrates a wire bonded integrated circuit device214, the electrically active face of the integrated circuit device214may be downwardly facing and electrically connected to the substrate218by flip chip bonding methods.

An alternative package230combining a lead frame202with a substrate218effective for use in ball grid array packages and land grid array packages is illustrated in cross-sectional representation inFIG. 15a. The lead frame202extends through centrally disposed aperture232in the substrate. Lead frame202is held in place by a conductive or non-conductive adhesive material between leadframe202and substrate218. One or more integrated circuit devices214are mounted on a surface234of an upwardly projecting portion235of the lead frame202. The integrated circuit device214is electrically interconnected to electrically conductive vias220by wire or tab bonds222. The integrated circuit device is then encapsulated in molding resin216.

Certain of the electrically conductive vias220″ electrically interconnect input/output pads on the electrically active face of integrated circuit device214to external portions236or tie bars of the lead frame202. A modified leadframe202′ for an alternative embodiment230′ of this package is illustrated inFIG. 15b.

Yet another alternative package240is illustrated in cross-sectional representation inFIG. 16. Lead frame202has a downwardly projecting portion241extending through centrally disposed aperture232. One or more integrated circuit devices214, optionally in combination with passive devices242, are mounted on a centrally disposed portion244of the lead frame202to reduce the overall height of the package240. Wire or tab bonds222electrically interconnect I/O pads on integrated circuit device214or passive device242to external circuitry such as on a printed circuit board. Selected ones220′″ of the electrically conductive vias electrically interconnect external portions236of the lead frame202to external circuitry. As with previous embodiments, integrated circuit device214and optional passive devices242are then encapsulated with molding resin216.

Surface246of the downwardly projecting portion241of the lead frame202provides a large surface area for the dissipation of heat. While all the packages disclosed herein have improved thermal dissipation characteristics as compared to conventional BGA and LGA packages, as illustrated by the Examples below, the package240ofFIG. 16very greatly enhances thermal dissipation. For even better thermal properties, the surface246may be thermally coupled to an external heat sink or heat spreader or exposed to a cooling fluid. Surface246may also function as a stop to control the dimensions of solder balls bonded to electrically conductive vias220′″ following melting for attachment to external circuitry.

The advantages of the invention will become more apparent from the examples that follow.

EXAMPLES

The package ofFIG. 12was modeled for thermal performance by computer simulation of a 169 ball 8×8 BGA (FBGA) package having the dimensions and specifications of Table 1. ΘJAis the thermal resistance from the operation portion of a semiconductor device to a still air environment surrounding the device. As shown in Table 2, the simulated ΘJAimproved by about 2° C./W. This improvement means a 7.9% improvement in power dissipation.

The packages ofFIGS. 15 and 16were modeled for thermal performance by computer simulation FBGA packages having the dimensions and specifications of Table 3. The calculated thermal performance of these simulated packages is reported in Table 4.

Table 4 illustrates the package ofFIG. 15has a ΘJAimprovement of about 2.4° C./W while the package ofFIG. 16has a ΘJAimprovement of almost 3° C./W. Because of the smaller centrally disposed aperture, as compared to the package ofFIG. 15, this package can maintain more signal I/Os. Referring back toFIG. 2, the mid-portion28can be made smaller and the centrally disposed aperture is smaller so that the package can maintain more signal I/Os on substrate12. In addition, the lead frame can be used as the ground plane as well as thermal paths.

One or more embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention.