Non-volatile memory cell

A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectric layer, and two doped regions in the substrate beside the gate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor structure and a method of fabricating the same. More particularly, this invention relates to a structure of a non-volatile memory cell and a method of fabricating the same.

2. Description of Related Art

A non-volatile memory provides the property of multiple entries, retrievals and erasures of data, and is able to retain the stored information even when the electrical power is off. As a result, non-volatile memory is widely used in personal computers and consumer electronic products.

The family of non-volatile memory includes the substrate/oxide/nitride/oxide/silicon (SONOS) memory. The silicon nitride layer in the oxide-nitride-oxide (ONO) composite layer serves as a charge trapping layer.

In the programming of a SONOS memory cell, hot electrons injected into the charge trapping layer are not evenly distributed in the entire charge trapping layer but localized in a certain region of the charge trapping layer. In the erasing of the SONOS memory cell, hot holes are injected into the charge trapping layer locally to eliminate the stored electrons. However, since the injection region of the hot holes is smaller than that of the hot electrons, the SONOS memory cell cannot be completely erased. Therefore, after multiple programming-erasing cycles, the performance of the memory cell is reduced and even errors may occur during the operation of the memory cell.

SUMMARY OF THE INVENTION

Accordingly, this invention provides a method of fabricating a non-volatile memory cell that can prevent the memory cell from being erased incompletely.

This invention also provides a non-volatile memory cell with higher performance that can be fabricated with the above method of this invention.

The method of fabricating a non-volatile memory cell of this invention is described as follows. Two separate charge trapping structures are formed on a semiconductor substrate. First spacers are formed on the sidewalls of the two charge trapping structures. A gate dielectric layer is formed on the substrate. A gate is formed on the two charge trapping structures and the gate dielectric layer therebetween. Two doped regions are formed in the substrate beside the gate.

In an embodiment of the above method, the step of forming the gate includes forming over the substrate a conductive layer covering the charge trapping structures and the gate dielectric layer, and successively patterning the conductive layer and the charge trapping structures to form the gate. In another embodiment, the conductive layer is patterned without patterning the two charge trapping structures.

The non-volatile memory cell of this invention includes a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the charge trapping structures, a gate on the charge trapping structures and the gate dielectric layer, and two doped regions in the substrate beside the gate.

In this invention, the non-volatile memory cell with two separate charge trapping structures not only can prevent the memory cell from being erased incompletely but also can improve the operation performance of the memory cell.

In order to make the above and other objects, features and advantages of this invention more comprehensible, several embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A-1Dschematically illustrate, in a cross-sectional view, the common part of two process flows of fabricating a non-volatile memory cell respectively according to the first and second embodiments of this invention.

Referring toFIG. 1A, a blanket charge trapping structure107is formed on a semiconductor substrate100, such as a silicon substrate. The blanket charge trapping structure107may include a bottom oxide layer102, a nitride layer104and a top oxide layer106. For example, the bottom oxide layer102may be formed through thermal oxidation or chemical vapor deposition (CVD). The nitride layer104, which is to be defined into a charge trapping layer, may be formed through LPCVD or PECVD. The top oxide layer106may be formed through surface oxidation of the nitride layer104or through CVD. Thereafter, a patterned mask layer108, such as a patterned photoresist layer, is formed on the blanket charge trapping structure107.

Referring toFIG. 1B, an etching process is performed using the patterned mask layer108as a mask to the blanket charge trapping structure107to pattern the blanket charge trapping structure107into two separate charge trapping structures107a. Each charge trapping structure107amay include a bottom oxide layer102aon the substrate100, a nitride trapping layer104aon the bottom oxide layer102aand a top oxide layer106aon the nitride layer104a. The patterned mask layer108is then removed.

Referring toFIG. 1C, first spacers110are formed on the sidewalls of the two charge trapping structures107a. The method of forming the first spacers110is, for example, depositing a spacer material layer over the substrate100and then removing a portion thereof by anisotropic etching. The spacer material layer may include silicon nitride (SiN), silicon oxide (SiO) or silicon oxyniride (SiON), for example. It is noted that the first spacers on the opposite sidewalls of the two charge trapping structures107aare labeled with “110a” and those on the other sidewalls labeled with “110b”.

Referring toFIG. 1D, a gate dielectric layer112is formed on the substrate100, possibly being a silicon oxide layer formed through thermal oxidation. A conductive layer114is then formed over the substrate covering the two charge trapping structures107aand the gate dielectric layer112. The conductive layer114may be a doped polysilicon layer formed with CVD, for example. Then, a patterned mask layer116, such as a patterned photoresist layer, is formed on the conductive layer114covering a portion of the two charge trapping structures107a. According to this invention, the gate dielectric layer112and the conductive layer114formed in the memory cell region as shown inFIG. 1Dcan be the same layers for forming the gate dielectric layers and the gates of the devices in the peripheral logic device region. Herein, it is for sure that the blanket charge trapping structure in the peripheral logic device region is removed in the aforementioned step of patterning the blanket charge trapping structure107. Similarly, the following fabricating steps of the memory cells can be integrated with the corresponding fabricating steps of the peripheral logic devices.

Afterwards, an etching process is performed using the patterned mask layer116as a mask to the conductive layer114. The etching process can be performed in two different ways as respectively described in the following two embodiments.

First Embodiment

FIGS. 1E-1Fschematically illustrate, in the cross-sectional view, the remaining part of the process flow of fabricating a non-volatile memory cell according to the first embodiment of this invention.

Referring toFIG. 1E, in this embodiment, the etching process using the patterned mask layer116(FIG. 1D) as a mask is performed to the conductive layer114and to the charge trapping structures107asuccessively, so that a gate114ais formed as well as a portion of the charge trapping structures107aand the first spacers110bare removed. The gate114acovers the remaining charge trapping structures107band the gate dielectric layer112between the same. Then, the patterned mask layer116is removed.

Referring toFIG. 1F, a second spacer118is formed beside the gate114aand two charging trapping structures107bon the substrate100. The method of forming the second spacer118is, for example, depositing a spacer material layer over the substrate100and then removing a portion thereof through anisotropic etching. The spacer material layer may include SiN, SiO or SiON, for example. Thereafter, two doped regions120aand120bas source/drain regions are formed in the substrate100beside the gate114a. The two doped regions120aand120bare formed, for example, with an ion implantation process that implants an N-type or P-type dopant in the substrate100.

According to the first embodiment of this invention, the memory cell includes a semiconductor substrate100, two charge trapping structures107b, first spacers110a, a gate dielectric layer112, a gate114a, a second spacer118and two doped regions120aand120b. The two charge trapping structures107bare separated from each other on the substrate100. The first spacers110aare disposed on the opposite sidewalls of the two charge trapping structures107b. The gate dielectric layer112is disposed on the substrate100between the two charge trapping structures107b. The gate114ais disposed on the two charge trapping structures107band the gate dielectric layer112, wherein the sidewalls of the gate114aare aligned with corresponding sidewalls of the two charge trapping structures107b. The second spacer118is disposed on the substrate100beside the gate114aand two charging trapping structures107b. The two doped regions120aand120bare disposed in the substrate100beside the gate104a.

Second Embodiment

FIGS.1E′-1F′ schematically illustrate, in the cross-sectional view, the remaining part of the process flow of fabricating a non-volatile memory cell according to the second embodiment of this invention.

Referring to FIG.1E′, in this embodiment, the etching process using the patterned mask layer116(FIG. 1D) as a mask is performed to the conductive layer114to form a gate114a, without substantially patterning the two charge trapping structures107a. As a result, the gate114acovers a portion of the two charge trapping structures107aand the gate dielectric layer112between the same. Thereafter, the patterned mask layer116is removed.

Referring to FIG.1F′, a second spacer119is formed on the substrate100beside the gate114aand the first spacers110bof the two charging trapping structures107a. The material of the second spacer119is SiN, SiO or SiON, for example. The method of forming the second spacer119may be the same as that of forming the second spacer118in the first embodiment. Then, two doped regions120aand120bas source/drain regions are formed in the substrate100beside the gate114a. The method of forming the doped regions120a/bmay be the same as that provided in the first embodiment.

According to the second embodiment of this invention, the memory cell includes a semiconductor substrate100, two charge trapping structures107a, first spacers110aand110b, a gate dielectric layer112, a gate114a, a second spacer119and two doped regions120aand120b. The two charge trapping structures107aare separated from each other on the substrate100. The first spacers110aare disposed on the opposite sidewalls of the two charge trapping structures107a, and the spacers110bon the other sidewalls of the same. The gate dielectric layer112is disposed on the substrate100between the two charge trapping structures107a. The gate114ais disposed on the two charge trapping structures107aand the gate dielectric layer112. The second spacer119is disposed on the substrate100beside the gate114aand the first spacers110bof the two charging trapping structures107a. The two doped regions120aand120bare disposed in the substrate100beside the gate114a.

Moreover, exemplary operation of the non-volatile memory cell of this invention is introduced, with the non-volatile memory cell depicted inFIG. 1Fas an example. Referring toFIG. 1F, the doped regions120aand120brespectively serve as a source region and a drain region here. The voltages applied to the gate114a, the source region120a, the drain region120band the substrate100are designated as Vg, Vs, Vd and Vb, respectively. When the programming is performed with CHEI (channel hot electron injection), for example, Vg is 6V, Vd is 4V, and Vs and Vb both are at the ground level. When the erasing is performed with BTBTHH (band-to-band tunneling hot holes) injection, for example, Vg is −3V, Vd is 6V, and Vs and Vb both are at the ground level. The erasing may alternatively be done by FN hole tunneling, wherein Vg is −6V, Vb is 6V, and Vs and Vd both are at the ground level, for example.

Accordingly, this invention divides the charge trapping layer of the non-volatile memory cell into two separate pieces, so that the injection region of hot electrons and that of hot holes both are confined in the pieces to prevent incomplete erasing. As a result, the performance of the memory cell is not lowered after repeated operations.

Moreover, the first spacers110aon the opposite sidewalls of the two charge trapping structures can prevent current leakage between the nitride trapping layer104aand the gate114a.

Furthermore, the fabricating process of the non-volatile memory cell of this invention is compatible with a logic device process. That is, this invention can be integrated with a logic device process without an extra step or mask.

This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.