Sensing amplifier circuit for data readout from a semiconductor memory device

In a semiconductor memory device, two sense amplifiers are provided on one output signal line for reading data stored in a memory cell. The sense amplifiers are connected in parallel to each other. A control signal generation circuit generates a control signal so that one of the sense amplifiers which has a greater drive capability is activated during a predetermined time period after an address from which data are to be read out is changed, and that the sense amplifier having a smaller drive capability is activated during a time period other than the predetermined time period.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to a semiconductor memory device such as a mask ROM 
(Read Only Memory), an EPROM (Erasable Programmable ROM) or an SRAM 
(Static Random Access Memory), and more particularly relates to a 
semiconductor memory device having an improved data read circuit. 
2. Description of the Prior Art 
In a semiconductor memory device, since data read out from a memory cell is 
a weak signal, the signal is amplified on an output signal line by a sense 
amplifier and then output. If the sense amplifier is always in an active 
state, the power consumption of the semiconductor memory device becomes 
too large. Therefore, in a conventional mask ROM or the like, after data 
read out from a memory cell is amplified by a sense amplifier and the 
read-out data becomes valid internally, the valid data is latched in a 
latch circuit. Thereafter, the sense amplifier is in an inactive state 
until the next read, whereby the power consumption is reduced. 
A data read circuit in a mask ROM of the above-mentioned configuration is 
shown in FIG. 7. A memory cell 1 is arranged at each crossing of a number 
of word lines 2 and bit lines 3. Data stored in the memory cell 1 is input 
into a sense amplifier 6 through a bit line 3 via an FET 5 which is 
controlled by a column selection line 4. The data S.sub.OUT amplified by 
the sense amplifier 6 is latched in a latch circuit 7 and output via an 
output circuit 8 as output data D.sub.OUT of the ROM. 
In this case, the sense amplifier 6 and the latch circuit 7 receive a sense 
signal .PHI..sub.SA and a latch signal .PHI..sub.LT from a timing 
generator (TG) circuit 9, respectively. As shown in FIG. 8, when the TG 
circuit 9 detects the change of an address signal A, the sense signal 
.PHI..sub.SA becomes High to activate the sense amplifier 6. The latch 
signal .PHI..sub.LT is at a High level during a short time period after 
the read-out data becomes valid internally, so as to allow the latch 
circuit 7 to latch the data S.sub.OUT output from the sense amplifier 6. 
When the data S.sub.OUT is latched at the rise of the latch signal 
.PHI..sub.LT, the sense signal .PHI..sub.SA returns to Low so that the 
sense amplifier 6 is inactivated, whereby the power consumption of the 
sense amplifier 6 is suppressed until the next read. The read-out data 
latched in the latch circuit 7 can be output from the output circuit 8 as 
the output data D.sub.OUT for a predetermined period. 
However, in the above configuration, in the case where the address signal A 
does not change at the first access after the power source V.sub.cc is 
turned on as shown in FIG. 9, the TG circuit 9 can not output the sense 
signal .PHI..sub.SA and the successive latch signal .PHI..sub.LT, so that 
the output data D.sub.OUT continues invalid. In this case, the operation 
must be performed in such a complicated manner that a dummy cycle is 
carried out in order to change the address signal A after power is turned 
on, and then the regular address signal is output as shown in FIG. 10. 
In the above-mentioned configuration in which the data read from the memory 
cell 1 is latched in the latch circuit 7 once and then output, when 
erroneous data is latched by a noise on a power supply line etc., the 
erroneous data is output as the output data D.sub.OUT, without conversion. 
As described above, a conventional semiconductor memory device has problems 
in that it requires a dummy cycle when the system is powered on, in order 
to suppress the power consumption of the sense amplifier 6, and that the 
probability of a data read error is prone to increase. 
SUMMARY OF THE INVENTION 
The semiconductor memory device of this invention, which overcomes the 
above-discussed and numerous other disadvantages and deficiencies of the 
prior art, comprises: a plurality of sense amplifiers provided on one 
output signal line for reading data stored in a memory cell, said sense 
amplifiers being connected in parallel to each other; and a control signal 
generation circuit for generating a control signal by which said sense 
amplifiers are selectively activated. 
In a preferred embedment, the drive capability of at least one of said 
sense amplifiers is greater than that of at least other one of said sense 
amplifiers. 
In the above configuration, said control signal generation circuit may 
generate said control signal so that said at least one sense amplifier 
having a greater drive capability is activated during a predetermined time 
period after an address from which data is to be read out is changed, and 
that said at least other one sense amplifier is activated during a time 
period other than said predetermined time period. 
In a preferred embodiment, said sense amplifiers are differential type 
sense amplifiers. 
In the above-mentioned configuration, the control signal generation circuit 
can activate one or more appropriate sense amplifiers when data is read 
out from a memory cell. For example, a sense amplifier with a 
high-amplification is selected and activated or a plurality of sense 
amplifiers are activated, so that the data can surely be output at a high 
speed, as in the prior art. After the read-out data becomes valid, the 
control signal is switched and a sense amplifier which has the same 
amplification but operates at a low speed with a low current consumption 
is selected and activated, whereby the power consumption can be suppressed 
as in the prior art. Alternatively, the number of sense amplifiers to be 
activated may be reduced. 
Even after the read-out data becomes valid, it is unnecessary to latch the 
data in a latch circuit because at least one sense amplifier is activated. 
Therefore, the probability of latching erroneous data by a noise on a 
power supply line etc. is greatly reduced, and the increase in the 
probability of data read error can be prevented. Moreover, since any one 
of the sense amplifiers is activated when power is turned on, the 
disadvantage that a dummy cycle must be carried out is eliminated. 
Thus, the invention described herein makes possible the objectives of: 
(1) providing a semiconductor memory device which needs no latch circuit; 
(2) providing a semiconductor memory device in which it is unnecessary to 
perform a dummy cycle when powered on; and 
(3) providing a semiconductor memory device in which the increase in the 
probability of data read error can be suppressed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIGS. 1 to 4 show one embodiment of the invention. This embodiment is a 
ROM, and like reference numerals represent like components having the same 
functions as those of the prior art shown in FIG. 7. 
In the ROM of FIG. 1, a memory cell 1 is arranged at each crossing of a 
plurality of word lines 2 and bit lines 3. Each of the bit lines 3 is 
connected to sense amplifiers 6a and 6b via an FET 5 which is controlled 
by a column selection line 4. The sense amplifiers 6a and 6b are connected 
in parallel, and the outputs thereof are coupled to an output circuit 8. 
The output circuit 8 outputs output data D.sub.OUT as readout data of the 
ROM. The control output of a TG circuit 9 is connected to the sense 
amplifiers 6a and 6b which receive respectively a first sense signal 
SA.sub.1 (Low: active) and a second sense signal SA.sub.2 (Low: active). 
The sense amplifiers 6a and 6b have MOSFETs which are arranged in a similar 
manner as shown in FIG. 2. When, in the sense amplifier 6a, the drive 
capability of p-MOS transistors Q.sub.1 and Q.sub.2 is indicated by 
.beta..sub.p and the drive capability of n-MOS transistors Q.sub.3 and 
Q.sub.4 by .beta..sub.n, the drive capability of p-MOS transistors Q.sub.5 
and Q.sub.6, and the drive capability of n-MOS transistors Q.sub.7 and 
Q.sub.8 are set to be .beta..sub.p /2 and .beta..sub.n /2, respectively, 
in the sense amplifier 6b. Accordingly, the sense amplifiers 6a and 6b 
have the same input-output voltage characteristics Vin-Vout, as shown in 
FIG. 3 In the vicinity of the logic threshold voltage, the current I.sub.2 
flowing through the sense amplifier 6b is half the current I.sub.1 flowing 
through the sense amplifier 6a. amplifier 6b is half that of the sense 
amplifier 6a. 
The operation of the data read circuit having the above-mentioned 
configuration will be described. When an address signal A is input into 
the ROM, a row of the memory cells 1 is first selected by one of the word 
lines 2. Then, one of the bit lines 3 is selected by a corresponding one 
of the column selection lines 4 so that the data stored in the selected 
memory cell 1 is sent to the respective sense amplifiers 6a and 6b from 
the bit line 3 via the FET 5. The TG circuit 9 detects the change of the 
address signal A so as to make the first sense signal SA.sub.1 Low and the 
second sense signal SA.sub.2 High. Thus, the sense amplifier 6a having a 
high drive capability is activated to amplify the read-out data and send 
it to the output circuit 8 as data S.sub.OUT. In this way, the weak signal 
of the data stored in the memory cell 1 can surely be read out at a high 
speed by the sense amplifier 6a. 
After the data S.sub.OUT thus read out becomes valid, the TG circuit 9 
switches the levels of the first sense signal SA.sub.1 to High and the 
second sense signal SA.sub.2 to Low. That is, the sense amplifier 6a which 
has the high drive capability is inactivated and the other sense amplifier 
6b is activated. Thereafter, the sense amplifier 6b outputs the data 
S.sub.OUT which is sent to the output circuit 8, whereby the power 
consumption of the ROM can be suppressed. The output circuit 8 outputs the 
output data D.sub.OUT as the read-out data of the ROM. 
As a result, according to the embodiment, the sense amplifier 6b is in the 
active state after the read-out data becomes valid, and therefore it is 
not necessary to latch the data in a latch circuit as in the prior art, so 
that there is no probability of latching erroneous data by a noise on a 
power supply line etc. Moreover, since at least the sense amplifier 6b is 
activated when the system is powered on, data can surely be read out even 
if there is no change of the address signal A. 
Alternatively, the sense amplifiers 6a and 6b may have the configuration 
shown in FIG. 5, so as to reduce the number of elements. In this case, the 
sense amplifier 6bwhose power consumption is low is always in the active 
state, and the activation of the sense amplifier 6a with a higher drive 
capability is controlled by the first sense signal SA.sub.1 and the 
inverse signal thereof. The sense amplifiers 6a and 6b can be constructed 
in the form of differential amplifiers as shown in FIG. 6. In this case, 
it is required to provide a dummy cell 11 having the same characteristics 
as those of the memory cell 1 at each dummy bit line 13, in order to 
generate a reference voltage. 
As apparent from the above description, according to the semiconductor 
memory device of the invention, the power consumption can be suppressed 
without using a latch circuit, and hence there is no probability of 
latching erroneous data by a noise on a power supply line etc. and the 
increase in the probability of data read error can be prevented. Moreover, 
since any one of the sense amplifiers is activated when the power is 
turned on, a disadvantage that data can not be read unless a dummy cycle 
is carried out can be eliminated. 
It is understood that various other modifications will be apparent to and 
can be readily made by those skilled in the art without departing from the 
scope and spirit of this invention. Accordingly, it is not intended that 
the scope of the claims appended hereto be limited to the description as 
set forth herein, but rather that the claims be construed as encompassing 
all the features of patentable novelty that reside in the present 
invention, including all features that would be treated as equivalents 
thereof by those skilled in the art to which this invention pertains.