JFET devices with PIN gate stacks

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

BACKGROUND

1. Field of the Invention

Embodiments of the present invention relate generally to the field of semiconductor devices. More particularly, embodiments of the present invention relate to improved semiconductor devices and techniques for fabricating improved semiconductor devices.

2. Description of the Related Art

Currently, the most commonly used transistor for implementing logic devices in integrated circuits is the metal-oxide semiconductor field effect transistor (MOSFET). In particular, the combination of complementary n-type and p-type MOSFETs, a technology known as “CMOS,” allows for the creation of low power logic devices. Because n-MOS and p-MOS devices are connected in series, no drain current flows—except for a small charging current during the switching process between two different states. Furthermore, improved fabrication techniques have, over the years, led to the reduction of MOSFET sizes through a technique known as “scaling,” which has led to smaller, more densely packed, and faster chips.

More recently, however, the speed benefits typically associated with scaling have diminished due to fundamental physical constraints inherent in MOSFETs. For example, in order to switch the voltage state of a MOSFET, the MOSFETs gate terminal must be sufficiently charged. The amount of charge that will switch the MOSFET on is proportional to the capacitance of the MOSFET's gate terminal. One consequence of scaling is that the thickness of the gate insulator must be reduced to maintain acceptably small short-channel effects. Furthermore, to counteract the increased leakage current that may result from the reduced dielectric thickness and thereby keep the gate leakage current below acceptable levels, the gate insulator may be made of a dielectric with a dielectric constant, “k,” higher than that of silicon dioxide, whose k equals 3.9. Both the reduced thickness and the higher dielectric constant result in higher capacitance. Therefore, although the maximum drain current may increase for the scaled CMOS device, this benefit is largely limited by the increased capacitance. The result is that although the density of CMOS devices continues to increase, the speed performance of such devices has not increased substantially over the generations.

Junction field effect transistors (JFETs), on the other hand, do not utilize an insulated gate. Rather, in a typical JFET, the gate is a p-doped or n-doped semiconductor material and the gate directly contacts the semiconductor body, forming a p-n junction between the gate and the transistor's conductive channel. Because JFETs do not utilize an insulated gate, the total gate capacitance in a JFET may be greatly reduced, which may result in a higher transistor switching speed compared to existing CMOS technology.

However, typical JFETs have limited applicability due to the low forward-bias turn-on voltage, i.e. the diode turn-on voltage, of the p-n junction between the gate and the channel of the JFET. In a typical JFET, the depletion region at the gate-channel interface prevents conduction when the gate potential is sufficiently low. To turn on the JFET, the gate potential is raised, which narrows the depletion region, allowing current to flow between the source and the drain. When the gate potential is raised above the forward bias potential of the p-n junction between the gate and the channel (typically 0.6 to 0.7 volts), current then starts to flow from the gate to the drain. This greatly increases the power consumption of the device. There is a limit, therefore, to the voltage that may be applied to a JFET. As a result, typical prior art JFETs may not be suitable in systems or devices which utilize a high voltage relative to the diode turn-on voltage of the JFET.

Therefore, it may be advantageous to provide an improved low-power semiconductor device with reduced gate capacitance and faster switching speed compared to existing CMOS technology. Specifically, it may be advantageous to provide a JFET with improved electrical characteristics that address the limitations discussed above.

DETAILED DESCRIPTION

Embodiments of the present invention relate to JFETs with improved electrical characteristics that address the limitations discussed above, making them more suitable for use in a wide range of semiconductor devices, such as logic devices and memory access devices. Specifically, several embodiments relate to methods and devices for raising the voltage level that may be applied to the gate of a JFET without exceeding the diode turn-on voltage of the p-n junction between the gate and the channel. Several embodiments also relate to systems and devices that include JFETs with improved electrical characteristics.

For the sake of clarity, it is noted that in discussing the relationship between deposited materials, the terms “over,” or “above” are used to describe materials that are connected but that may, or may not, be in direct contact. By contrast, the term “directly on” is used to indicate direct contact between the materials described.

Turning now to the drawings, and referring initially toFIG. 1, a block diagram depicting a processor-based system, generally designated by reference numeral10, is illustrated. The system10may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, etc. In a typical processor-based device, one or more processors12, such as a microprocessor, control the processing of system functions and requests in the system10. As will be appreciated, the processor12may include an embedded North or South bridge (not shown), for coupling each of the aforementioned components thereto. Alternatively, the bridges may include separate bridges coupled between the processor12and the various components of the system10.

The system10typically includes a power supply14. For instance, if the system10is a portable system, the power supply14may advantageously include permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supply14may also include an AC adapter, so the system10may be plugged into a wall outlet, for instance. The power supply14may also include a DC adapter such that the system10may be plugged into a vehicle cigarette lighter, for instance. Various other devices may be coupled to the processor12depending on the functions that the system10performs. For instance, a user interface16may be coupled to the processor12. The user interface16may include buttons, switches, a keyboard, a light pen, a mouse, and/or a voice recognition system, for instance. A display18may also be coupled to the processor12. The display18may include an LCD display, a CRT, LEDs, and/or an audio display, for example. Furthermore, an RF sub-system/baseband processor20may also be coupled to the processor12. The RF sub-system/baseband processor20may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). One or more communication ports22may also be coupled to the processor12. The communication port22may be adapted to be coupled to one or more peripheral devices24such as a modem, a printer, a computer, or to a network, such as a local area network, remote area network, intranet, or the Internet, for instance.

Because the processor12generally controls the functioning of the system10by implementing software programs, memory is operably coupled to the processor12to store and facilitate execution of various programs. For instance, the processor12may be coupled to the volatile memory26which may include Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM). The volatile memory26may include a number of memory modules, such as single inline memory modules (SIMMs) or dual inline memory modules (DIMMs). As can be appreciated, the volatile memory26may simply be referred to as the “system memory.” The volatile memory26is typically quite large so that it can store dynamically loaded applications and data.

The processor12may also be coupled to non-volatile memory28. The non-volatile memory28may include a read-only memory (ROM), such as an EPROM, and/or flash memory to be used in conjunction with the volatile memory. The size of the ROM is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory28may include a high capacity memory such as a tape or disk drive memory.

One or more components of the system10may include improved JFETs (depicted herein with reference numeral “32” for n-type and “52” for p-type) fabricated in accordance with embodiments described herein. Some examples of devices in which improved JFETs may be beneficial are illustrated inFIGS. 2-5. Specifically,FIG. 2illustrates a memory device with improved JFETs, andFIGS. 3-5illustrate integrated circuit logic devices with improved JFETs.FIGS. 6-9describe the improved JFETs and methods of fabrication.

Referring now toFIG. 2, a partial schematic illustration of an integrated circuit, such as a memory device29, which may be implemented in the volatile memory26, is illustrated. The memory device29includes an array of memory cells having transistors which may be fabricated in accordance with the techniques described herein. In one or more embodiments, the memory device29may comprise a dynamic random access memory (DRAM) device. The memory device29includes a number of memory cells30arranged in a grid pattern and comprising a number of rows and columns. The number of memory cells30(and corresponding rows and columns) may vary depending on system requirements and fabrication technology. Each memory cell30includes an access device comprising a JFET32and a storage device comprising a capacitor34. The access device is implemented to provide controlled access to the storage device. The JFET32includes a drain terminal36, a source terminal38, and a gate40. The capacitor34is coupled to the source terminal38. The terminal of the capacitor34that is not coupled to the JFET32may be coupled to a ground plane. As described further below, the drain36is coupled to a bit line (BL) and the gate40is coupled to a word line (WL).

It should be noted that although the above description depicts the terminal of the access device coupled to the capacitor34as the “source”38and the other non-gate terminal of the access device as the “drain”36, during read and write operations, the JFET32may be operated such that each of the terminals36and38operates at one time or another as a source or a drain. Accordingly, for purposes of further discussion it should be recognized that whenever a terminal is identified as a “source” or a “drain,” it is only for convenience and that in fact during operation of the JFET32either terminal could be a source or a drain depending on the manner in which the JFET32is being controlled by the voltages applied to the terminals36,38and40. In addition, it will be appreciated that embodiments of a memory device29may include p-type JFETs, n-type JFETS or a combination of both.

As previously described, the memory array is arranged in a series of rows and columns. To implement the data storage capabilities of a memory cell30, an electrical charge is placed on the drain36of the JFET32via a bit line (BL). By controlling the voltage at the gate40via the word line (WL), the depletion region between the gate40and the channel may be narrowed such that the electrical charge at the drain36can flow to the capacitor34. By storing electrical charge in the capacitor34, the charge may be interpreted as a binary data value in the memory cell30. For instance, for a single-bit storage device, a positive charge above a known threshold voltage stored in the capacitor34may be interpreted as binary “1.” If the charge in the capacitor34is below the threshold value, a binary value of “0” is said to be stored in the memory cell30. For reasons discussed above, it will be appreciated that the voltage at the gate40may be limited to a voltage sufficiently below the diode turn-on voltage of the JFET's gate-channel junction.

The bit lines BL are used to read and write data to and from the memory cells30. The word lines WL are used to activate the JFET32to access a particular row of a memory cell30. Accordingly, the memory device29also includes a periphery portion which may include an address buffer42, row decoder44and column decoder46. The row decoder44and column decoder46selectively access the memory cells30in response to address signals that are provided on the address bus48during read, write and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or another type of memory controller. The column decoder46may also include sense amplifiers and input/output circuitry to further facilitate the transmission of data to and from the memory cell30via the bit lines BL.

In one mode of operation, the memory device29receives the address of a particular memory cell30at the address buffer42. The address buffer42identifies one of the word lines WL of the particular memory cell30corresponding to the requested address and passes the address to the row decoder44. The row decoder44selectively activates the particular word line WL to activate the JFET's32of each memory cell30that is connected to the selected word line WL. The column decoder46selects the bit line (or bit lines) BL of the memory cell30corresponding to the requested address. For a write operation, data received by the input/output circuitry is coupled to the selected bit line (or bit lines) BL and provides for the charge or discharge of the capacitor34of the selected memory cell30through the JFET32. The charge corresponds to binary data, as previously described. For a read operation, data stored in the selected memory cell30, represented by the charge stored in the capacitor34, is coupled to the select bit line (or bit lines) BL, amplified by the sense amplifier and a corresponding voltage level is provided to the input/output circuitry in the column decoder46.

As described below, a memory device29that uses improved JFETs in accordance with certain disclosed embodiments may exhibit superior performance compared to prior art memory devices. For example, memory device29may exhibit increased performance due to the increased switching speed of the improved JFETs32. Furthermore, because the JFET32may be activated by a lower gate voltage compared to typical MOSFET based memory devices, the charge stored on capacitor34may also be reduced, which may reduce leakage current of the capacitor34.

In addition to the memory device29, improved JFETs may also be used in other parts of the system10. For example, JFETs fabricated in accordance with the techniques described herein may be used in the processor(s)12, or any other component of the system10that uses integrated circuit logic devices. Referring toFIGS. 3-5, various embodiments of integrated circuit logic devices that include improved JFETs are depicted. Turning first toFIG. 3, an embodiment of a JFET inverter50is shown. The JFET inverter50includes a p-type JFET52and an n-type JFET32coupled in series between a high voltage terminal54and a low voltage terminal56. It will be appreciated by a person of ordinary skill in the art that the output terminal58will be electrically coupled to the high voltage terminal54when the input terminal60is low and will be electrically coupled to the low voltage terminal56when the input terminal60is high.

FIG. 4depicts an embodiment of a JFET NAND gate64. The JFET NAND gate64includes two p-type JFETs52and two n-type JFETs32coupled between a high voltage terminal54and a low voltage terminal56as shown. It will be appreciated by a person of ordinary skill in the art that the output terminal66will be electrically coupled to the high voltage terminal54when either of input terminal68or70is low and will be electrically coupled to the low voltage terminal56when both input terminals68and70are high.

FIG. 5depicts an embodiment of a JFET NOR gate72. The JFET NOR gate72includes two p-type JFETs52and two n-type JFETs32coupled between a high voltage terminal54and a low voltage terminal56as shown. It will be appreciated by a person of ordinary skill in the art that the output terminal74will be electrically coupled to the high voltage terminal54when both input terminals76and78are low and will be electrically coupled to the low voltage terminal56when either of input terminals76or78is high.

With regard to the logic devices50,64, and72discussed above, the voltage level applied to the gates40and62of the JFETs32and52may be kept below the diode turn-on voltage of the gate-channel junction to avoid excessive gate-to-drain current and the resulting power dissipation. To increase the voltage that may be applied to the JFET gates40and62without causing gate-to-drain current, the JFETs32and52may be fabricated in accordance with one or more embodiments that will be discussed below. It will be appreciated that the integrated circuit logic devices depicted inFIGS. 3-5are examples only and many other JFET logic devices are possible, utilizing improved JFETs in accordance with disclosed embodiments.

Turning now toFIGS. 6-8, embodiments of improved JFETs are depicted. Generally,FIGS. 6 and 7depict JFETs with improved gate structures that allow the JFETs to be coupled to a higher gate voltage without exceeding the diode turn-on voltage of the gate-channel junction. In this way, the improved JFET will be less susceptible to the excessive power loss associated with exceeding the diode turn-on voltage of the gate-channel junction. By improving the performance of the JFET in this way, the improved JFETs may be used in a greater variety of semiconductor devices, as discussed above.

Accordingly,FIGS. 6-8depict an n-type, i.e. n-channel, JFET32with a gate structure having doped and undoped portions in accordance with one or more embodiments of the present invention. For example, as described further below, the gate structure may include an intrinsic material sandwiched between a p-type and an n-type material to provide a p-i-n (PIN) gate. It will be appreciated that an n-type JFET32is described for convenience only, and that embodiments of the present invention also include p-type, i.e. p-channel, JFETs. Therefore, it will be understood that the term “PIN” is not intended to refer to a particular ordering of the p-type and n-type materials. Furthermore, the JFET32depicted inFIGS. 6-8may be fabricated in any semiconductor material, such as the silicon substrate79, or, alternatively, a silicon-on-insulator (SOI) substrate (not shown).

As shown inFIGS. 6-8, the JFET32may be fabricated on top of a p-type material80. Accordingly, the silicon substrate79may be a p-type substrate, or, alternatively, a p-type material80may be formed by creating a p-type well in the substrate79. The p-type material80may also be electrically coupled to the gate terminal40via a terminal (not shown) that is directly coupled to the p-type material80. In alternative embodiments, the JFET32may not include the underlying p-type material80.

Above the p-type material80, the n-type JFET32depicted inFIGS. 6-8may also include a semiconductor material82, which is n-doped and forms a channel region between the source terminal36and the drain terminal38. In addition, the JFET32may include an n-type source region84and an n-type drain region86, which may optionally be heavily doped in order to provide a low resistance between the source and drain electrodes88and90and the channel region. In some embodiments, the JFET32may also include lightly doped drain (LDD) regions. Spacer oxides92may also be included to separate the source and drain electrodes88and90from the gate structure. Also included in the JFET32is a gate contact100, which may be formed of any suitable metal or polysilicon conductor and facilitates the electrical connection between the top material98of the gate and the gate terminal40.

Turning specifically toFIG. 6, a JFET32with a three-layer PIN gate in accordance with embodiments of the present invention is depicted. As shown inFIG. 6, the PIN gate may be a stack of three semiconductor materials, which may include any semiconductor material, such as silicon, silicon carbide, germanium, carbon-implanted silicon, silicon-germanium heterostructures or a combination thereof. The bottom material94of the PIN gate is n-doped and located directly on the semiconductor substrate79over the channel region formed in the semiconductor material82. Above the bottom material94is an intrinsic material96. Above the intrinsic material96is a p-doped top material98. Thus, the gate structure essentially forms a PIN diode disposed directly on the channel region.

In certain embodiments, both the bottom material94and the top material98may be approximately 500 to 700 angstroms thick and doped at a level of approximately 1e17 to 1e20 atoms per cubic centimeter. In the embodiment shown inFIG. 6, the bottom material94is n-doped and the top material98is p-doped, however, in embodiments in which the channel is p-doped, the bottom material94is also p-doped and the top material98is n-doped. The intrinsic material96may be approximately 50 to 200 angstroms thick and may be undoped or lightly doped. It will be understood by a person of ordinary skill in the art that the term “intrinsic” may be used to describe a semiconductor that is undoped or lightly doped. Furthermore, in some embodiments, the intrinsic material96may be silicon implanted with carbon. Implanting the silicon with carbon increases the bandgap of the intrinsic material96, and may therefore increase the diode turn-on voltage of the JFET32.

The advantage of forming a PIN gate as described above is that the diode turn-on voltage of the JFET32may be increased. In some embodiments, the diode turn-on voltage may be increased up to approximately 0.5 to 2.0 volts higher than JFETs that use conventional gate structures. This may allow for the use of n-JFETs and p-JFETs in logic devices and/or memory devices, such as those described in relation toFIGS. 1-5, with the advantage of significantly reduced gate capacitance.

Furthermore, the diode turn-on voltage of the JFET32may be manipulated by controlling the thicknesses and doping levels of the three PIN gate materials94,96and98. For example, the diode turn-on voltage may be increased by increasing the thickness of the intrinsic material96. Other characteristics of the JFET may also be manipulated. For example, the doping level of the bottom material94may be controlled so that the depletion layer may extend completely through the conductive channel in the semiconductor material82when the JFET32is switched off. For another example, the top material98may be heavily doped to provide good contact characteristics with the gate contact100and to increase the depth of penetration of the depletion region into the channel.

In some embodiments, the doping levels of the bottom material94and top material98may be kept low to avoid excessive diffusion of the dopants into the intrinsic material96. In addition to keeping the dopant levels low, diffusion of dopants into the intrinsic material96may also be avoided by including thin insulators between the materials, as shown inFIG. 7.

Turning toFIG. 7, a JFET32with a three-layer PIN gate in accordance with another embodiment of the present invention is depicted. As shown inFIG. 7, one or more embodiments may also include a first protective material102, located between the bottom material94and the intrinsic material96, and a second protective material104, located between the intrinsic material96and the top material98. The protective materials102and104may include a native oxide or may include other dielectric materials such as hafnium oxide, aluminum oxide, zirconium oxide and titanium dioxide. The thickness of the protective materials102and104may be in the range of approximately five to twenty angstroms. Although the protective materials102and104are made of electrically insulative material, the protective materials102and104are thin enough that the PIN gate materials94,96, and98are strongly coupled electrostatically. Therefore, the protective materials102and104may not significantly decrease the conductivity of the PIN gate structure. However, the protective materials102and104may prevent the passage of n-type and p-type dopants present in the bottom material94and the top material98. In this way, the dopants may be prevented from diffusing into the intrinsic material96during certain high-temperature processes typically used in semiconductor device fabrication. In alternative embodiments, the gate structure of the JFET32may include either the first protective material102or the second protective material104, but not both.

Turning toFIG. 7A, another embodiment of a PIN gate in accordance with embodiments of the present invention is depicted. As shown inFIG. 7A, the diode turn-on voltage of the JFET32may be further increased by forming the intrinsic material96with a silicon-germanium heterostructure. The silicon-germanium heterostructure may be formed from alternating formations of intrinsic germanium106,110and intrinsic silicon108,112. Although four formations are depicted, embodiments may include any number of formations and may include a number of silicon formations unequal to the number of germanium formations. Each formation106,108,110,112may be a monolayer approximately 10 angstroms thick.

Because the germanium and silicon exhibit different bandgaps, a barrier height will exist at the boundary between the silicon formations108,112and the germanium formations106,110. One of ordinary skill in the art will appreciate that the “barrier height” represents an amount of energy that a charge carrier must obtain to move from one material to another. The increased barrier height may, therefore, increase the diode turn-on voltage of the gate-channel junction.

Turning toFIG. 8, a JFET32with a two-layer PIN gate in accordance with another embodiment of the present invention is depicted. As shown inFIG. 8, the intrinsic material96may be located directly on the channel region and may be approximately 50 to 200 angstroms thick. As before, the top material98is p-doped and located over the intrinsic material96, however, unlike the previously described embodiments the bottom material94is eliminated. Nevertheless, the gate structure still resembles a PIN diode, with the n-type channel essentially taking the place of the n-type bottom material94. In some embodiments, a protective material may also be included between the top material98and the intrinsic material96, as described above in relation toFIG. 7.

Turning now toFIG. 9, a process for fabricating an improved JFET32in accordance with embodiments of the present invention is shown. The process114may be used to fabricate individual JFETs, JFET arrays, or complementary JFET devices such as those described in relation toFIGS. 2-5.

The process114starts with bulk semiconductor substrate79or silicon-on-insulator (SOI) substrate, which is processed at step116to form an active area and isolation regions using conventional lithography, oxidation and dopant implantation processes. At step116, p-doped and/or n-doped wells may be formed for the creation of n-type and/or p-type JFETs, respectively. In addition, a triple well may optionally be formed to provide increased isolation for the JFET device.

Next at step118, the threshold voltage of the device is adjusted by doping the active region of the JFET in accordance with techniques known to those of ordinary skill in the art. After adjusting the threshold voltage at step118, the process114may advance to step120.

At step120, the bottom material94of the PIN gate stack is formed directly on the substrate79over the channel region. The bottom material94may be formed of any suitable semiconductor material, such as silicon. The bottom material94may be deposited by chemical vapor deposition (CVD) or grown epitaxially via atomic layer deposition (ALD) to a thickness of approximately 500 to 700 angstroms. After depositing the bottom material94, the bottom material94is doped to a level of approximately 1e17 to 1e20 atoms per cubic centimeter. For an n-type JFET, the bottom material94is doped n-type, and for a p-type JFET, the bottom material94is doped p-type. Alternatively, the bottom material may be omitted or may be a part of the substrate79, as described and illustrated with reference toFIG. 8.

At step122, the first protective material102may be formed over the bottom material94. The first protective material102may be formed by growing a native oxide, or depositing a high dielectric constant dielectric material such as hafnium oxide, aluminum oxide, zirconium oxide and titanium dioxide through one or more ALD cycles. The first protective material102may be formed to a thickness in the range of approximately five to twenty angstroms. As described above, the formation of the first protective material102may be omitted in certain embodiments.

Next, at step124, the intrinsic material96may be formed over the first protective material102or the underlying bottom material94to a thickness of approximately 50 to 200 angstroms. The instrinsic material96may be deposited by chemical vapor deposition (CVD) or grown epitaxially. As described above in relation toFIG. 6, the intrinsic material96may be formed of silicon and may also be implanted with carbon. Therefore, after depositing the intrinsic material96, carbon may be implanted at a dose of 1.0e16 atoms per cubic centimeter with an implant energy of approximately 1 to 5 keV.

Furthermore, as described above in relation toFIG. 7A, the intrinsic material96may also be a heterostructure. Therefore, the intrinsic material96may be formed by depositing alternating monolayers of germanium and silicon. The process may begin by depositing either germanium or silicon over the first protective material102or, if the first protective material102is omitted, the underlying bottom material94. Each material may be formed to a thickness of approximately ten angstroms and may be formed by chemical vapor deposition (CVD) or grown epitaxially.

Next, at step126, the second protective material104may be formed over the intrinsic material96. As with the first protective material102, the second protective material104may be formed to a thickness of approximately ten angstroms by growing a native oxide, or depositing a high dielectric constant dielectric material via ALD or may be omitted.

Next, at step128, the top material98of the PIN gate stack may be formed over the second protective material104or the underlying intrinsic material96. As with the bottom material94, the top material98may be formed of any suitable semiconductor material, such as silicon and deposited by chemical vapor deposition (CVD) or grown epitaxially via atomic layer deposition (ALD) to a thickness of approximately 500 to 700 angstroms. After depositing the top material98, the top material98may be doped to a level of approximately 1e17 to 1e20 atoms per cubic centimeter. For an n-type JFET, the top material98will be doped p-type, and for a p-type JFET, the top material98will be doped n-type.

Next, at step130the PIN gate dopants are activated by annealing at a temperature in the range of 1000 degrees Celsius for a time period of approximately 5 seconds.

After finishing the steps described above, the gate structure will be substantially complete. The process114will then advance to step132, in which a gate contact material is formed over the top material98of the PIN gate stack with a thickness of approximately 200 to 1000 angstroms to form the gate contact100. The gate contact material may include any suitable metal, such as tungsten, nickel, titanium, tantalum, or cobalt, and may be formed by any method known in the art for depositing metal on semiconductor, such as CVD, physical vapor deposition (PVD), or sputtering for example. In one or more embodiments, the gate contact material may include a metal silicide, such as tungsten silicide, nickel silicide, titanium silicide, tantalum silicide, or cobalt silicide, and may be formed by growing or depositing polysilicon by CVD or low pressure CVD and doping the polysilicon through a process such as diffusion doping or ion implantation. After depositing the gate contact material, the gate contact100may be patterned using known photolithography techniques and formed using known etching techniques. In some embodiments, such as when the gate itself is metal, the step of forming a gate contact100over the gate may be eliminated.

Next, at step134, the source and drain regions are formed using a technique such as gate-self-aligned implantation to create source and drain extension regions known as lightly-doped-drain (LDD) regions. The source and drain regions may be doped with any suitable dopants, such as boron, BF2, or indium for p-type doping, or arsenic, phosphorous, or antimony for n-type doping. Dopants may be implanted with a dose in the range of 1e13 to 1e15 atoms per cubic centimeter and an implant energy in the range of 5 to 30 keV. In some embodiments, the implantation may optionally be accomplished through plasma assisted doping (PLAD).

Next, at step136, the spacers92may be formed. To form the spacers92an oxide, nitride or other dielectric material or combination of materials may be formed over the top and sides of the gate stack. After depositing the spacer material, the spacers92are formed on the sides of the gate to a thickness of approximately 100 to 500 angstroms using photolithography and etching techniques known in the art.

Next, at step138the source and drain regions84and86may be implanted to form heavily doped n+ or p+ source and drain regions. The source and drain regions may be doped with any suitable dopants, such as boron, BF2, or decaborane for p-type doping, or arsenic or phosphorous for n-type doping. Dopants may be implanted with a dose in the range of 1e15 to 1e16 atoms per cubic centimeter and an implant energy in the range of 0.5 to 10 keV.

Next, at step140the dopants implanted in previous steps are activated. First, a dielectric material, such as an oxide, nitride or combination is deposited to cap the active area. Then, the dopants are activated by an rapid thermal anneal or laser anneal. For example, the anneal may occur at 1000 to 1100 degrees Celsius and last for 2 to 10 seconds.

Finally, at step142, all of the remaining contacts and interconnects may be formed in accordance with processes that are well known in the art. Those of ordinary skill in the art will recognize process variations that may be implemented while still remaining within the scope of the present invention.

Those of ordinary skill in the art will recognize the advantages of forming a JFET in accordance with the process described above. Specifically, by forming a gate that includes a PIN gate stack, the diode turn-on voltage of the JFET may be increased. Therefore, unlike prior art, the presently described embodiments may operate under a larger operating voltage compared to conventional JFETs while still maintaining a low gate current. Consequently, this may allow the use of JFETs in a wider range of electronic devices, such as the logic devices and memory storage devices described above.