Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2016-0150808 filed on Nov. 14, 2016 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in their entirety are herein incorporated by reference.

BACKGROUND

1. Technical Field

Example embodiments relate to a semiconductor device and/or a method for fabricating the same.

2. Description of the Related Art

One of the scaling technologies to increase the density of semiconductor devices includes a multi-gate transistor in which silicon bodies in a fin or nano wire shape are formed on a substrate, with gates subsequently being formed on surfaces of the silicon bodies.

Such multi-gate transistor allows easier scaling, as the transistor includes a three-dimensional channel. Further, current control capability can be enhanced without requiring an increased gate length of the multi-gate transistor. Furthermore, it is possible to effectively reduce or suppress short channel effect (SCE), which is when the electric potential of a channel region is influenced by a drain voltage.

According to an example embodiment, a semiconductor device includes a substrate having first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed apart from each other on the fin in the third region, wherein the first and second spacers are sloped in a direction away from each other, and each or at least one of the angles between the first and second spacers and an upper surface of the fin is an acute angle, a recess is formed between the first and second spacers, wherein sidewalls of the recess are the fin, and the first and second spacers and a device isolating film substantially fill the recess.

According to another example embodiment, a semiconductor device includes a fin protruding on a substrate and extending in a first direction, first and second gate structures formed on the fin with spacings therebetween, first and second spacers formed on the fin and between the first and second gate structures, the first and second spacers being formed with spacings therebetween, a recess formed between the first and second spacers, wherein sidewalls of the recess are the fin, and the first and second spacers, a device isolating film filling the recess, an interlayer insulating film overlying the device isolating film, and the first and second gate structures and a contact penetrating the interlayer insulating film and formed respectively on side surfaces of the first and second spacers, wherein the first and second spacers are sloped in a direction of the contact, but are not in contact with the contact.

SUMMARY

Example embodiments relate to a semiconductor device with improved operating characteristics.

Example embodiments also relate to a method for fabricating a semiconductor device with improved operating characteristics.

The example embodiments are not limited to those set forth above, and embodiments other than those set forth above will be dearly understood to a person skilled in the art from the following description

In some example embodiments, a semiconductor device includes a fin protruding on a substrate, a sloped recess within the fin, first and second gate structures on the fin at opposite sides of the sloped recess, first and second spacers at opposite sides of the sloped recess between the first and second gate structures, and a device isolating film filling the recess.

DETAILED DESCRIPTION

These and other features and advantages are described in, or are apparent from, the following detailed description of various example embodiments.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a tolerance of ±10% around the stated numerical value. Moreover, when reference is made to percentages in this specification, it is intended that those percentages are based on weight, i.e., weight percentages. The expression “up to” includes amounts of zero to the expressed upper limit and all values therebetween. When ranges are specified, the range includes all values therebetween such as increments of 0.1%. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Although the tubular elements of the embodiments may be cylindrical, other tubular cross-sectional forms are contemplated, such as square, rectangular, oval, triangular and others.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 1 to 3.

FIG. 1is a perspective view of a semiconductor device according to some example embodiments, andFIG. 2is a cross sectional view taken on line A-A ofFIG. 1.FIG. 3is an enlarged cross sectional view of the encircled section B ofFIG. 2.FIG. 1skips illustration of a first interlayer insulating film131, a second interlayer insulating film132, and a capping film133for convenience of explanation.

Referring toFIGS. 1 to 3, the semiconductor device according to some example embodiments may include a substrate101, a first fin F1, a field insulating film110, a recess141b,a device isolating film173, first and second gate structures151a,151b,a first gate spacer115, a second gate spacer116, a first source/drain125a,a second source/drain125b,a third source/drain123, a fourth source/drain124, first and second interlayer insulating films131,132, a capping film133, a silicide film161, first and second contacts165, a third contact163, a fourth contact164, and so on.

Specifically, the substrate101may he formed of or include one or more semiconductor materials selected from Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. Further, a silicon on insulator (SOI) substrate may be used.

The first fin F1may be formed to protrude from the substrate101in a third direction Z1. The first fin F1may each extend longitudinally along a length direction, i.e., in a first direction X1. The first fin F1may have a long side and a short side. AlthoughFIG. 1illustrates that the long side is directed to the first direction X1and the short side is directed to second direction Y1, the example embodiments are not limited hereto. For example, the first fin F1may have the long side in the second direction Y1and the short side in the first direction X1.

The first fin F1may be a part of the substrate101, and may include an epitaxial layer grown from the substrate101. For example, the first fin F1may include Si or SiGe. The field insulating film110may be formed on the substrate100, and may partially overlie a sidewall of the first fin F1while exposing an upper surface of the first fin F1. For example, the field insulating film110may be an oxide film.

The first and second gate structures151a,151bmay be disposed at a distance from each other. Each, or at least one, of the first and second gate structures151a,151bmay intersect the first fin F1. AlthoughFIG. 1illustrates that the first and second gate structures151a,151bextend in the second direction Y1, example embodiments may not be limited hereto. Accordingly, the first and second gate structures151a,151bmay intersect the first fin F1by forming an acute angle or an obtuse angle with the first fin F1on a plane view.

The first and second gate structures151a,151bmay each include first and second gate insulating s153a,153band first and second gate electrodes155a,155b.

Each, or at least one, of the first and second gate insulating films153a,153bmay be formed between the first fin F1and the first and second gate electrodes155a,155b.Each, or at least one, of the first and second gate insulating films153a,153bmay be formed on an upper surface of the first fin F1and an upper surface of a side surface (long side). Further, each, or at least one, of the first and second gate insulating films153a,153bmay be disposed between the first and second gate electrodes155a,155band the field insulating film110. Such first and second gate insulating films153a,153bmay include a high-k dielectric material having a higher dielectric constant than a silicon oxide film. For example, the first and second gate insulating films153a,153bmay include HfO2, ZrO2, LaO, Al2O3or Ta2O5.

The first and second gate electrodes155a,155bmay each include first and second metal layers MG1, MG2. As illustrated, each, or at least one, of the first and second gate electrodes155a,155bmay be stacked with two or more of the first and second metal layers MG1, MG2. The first metal layer MG1may contribute to adjusting a work function, and the second metal layer MG2may contribute to filling a space defined by the first metal layer MG1. The first metal layer MG1may be formed conformally along an upper surface of the field insulating film110, and upper portion of an upper surface and a sidewall of the first fin F1. For example, the first metal layer MG1may include at least one of TiN, TaN, TiC, TiAlC and TaC. Further, the second metal layer MG2may include W or Al. Alternatively, the first and second gate electrodes155a,155bmay be respectively formed of or include non-metal elements such as Si or SiGe. For example, the first and second gate structures151a,151bdescribed above may be formed by a replacement process, but not limited hereto.

The first gate spacer115and the second gate spacer116may be respectively formed on sidewalls of the first and second gate strictures151a,151b.The first gate spacer115and the second gate spacer116may be disposed on the first fin F1. The first gate spacer115and the second gate spacer116may include, for example, at least one of an oxide film, a nitride film, and an oxynitride film, and differently from the illustration of drawings, a plurality of layers may be stacked and formed instead of a single layer.

A first spacer117aand a second spacer117bmay be formed between the first gate structure151aand the second gate structure151b.The first spacer117aand the second spacer117bmay be spaced apart from each other in the second direction Y1. That is, the first spacer117amay be positioned between the first gate structure151aand the second spacer117b,and the second spacer117bmay be positioned between the second gate stricture151band the first spacer117a.

The first spacer117aand the second spacer117bmay be simultaneously or contemporaneously formed with the first gate spacer115and the second gate spacer116. That is, a material of the first spacer117aand the second spacer117bmay be same as a material of the first gate spacer115and the second gate spacer116.

The first spacer117aand the second spacer117bmay be sloped in a direction of an increasing distance away from each other. This may be attributable to the tensile stress of a material in the first spacer117aand the second spacer117b.Accordingly, a first angle θ1between an outer side surface of the first spacer117a(in a direction of the first gate structure151a) and an upper surface of the first fin F1, may be an acute angle. Specifically, the first angle θ1may be greater than about 85 degrees and less than about 90 degrees. Likewise, an angle between an outer side surface of the second spacer117b(direction of the second gate structure151b) and an upper surface of the first fin F1may be an acute angle equal to or greater than about 85 degrees and less than about 90 degrees.

In some example embodiments, a height D2of the first spacer117aand the second spacer117bmay be less than the first gate spacer115and the second gate spacer116. That is, the first spacer117aand the second spacer117bmay be formed at a height which is less than, by a first distance D1, a height of the first gate spacer115and the second gate spacer116. This may be attributable to the upper portion of the first spacer117aand the second spacer117bbeing at least partially removed with an etch process, and being sloped thereafter. In an example, a height D2of the first spacer117aand the second spacer117bmay be about 20 to 26 nm. However, example embodiments are not limited to the example given above.

In some example embodiments, the recess141bmay be formed within the first fin F1in the first direction X1. The recess141bmay be formed between the first gate structure151aand the second gate structure151b.Specifically,the recess141bmay be formed between the first spacer117aand the second spacer117b.

A lower surface of the recess141bmay be lower than or level with lower surfaces of the first to fourth source/drains125a,125b,123,124. The lower surface of the recess141bmay be even lower on the first fin F1than on the field insulating film110, but not limited hereto.

The recess141bmay have a jaw on the upper surface of the first fin F1. That is, there may be an exposed portion of the upper surface of the first fin F1which is not covered by the first spacer117aand the second spacer117b.

AlthoughFIG. 2illustrates that the recess141bhas a trench shape of which a width becomes narrower as in a downward direction from an upper portion to a lower portion, the example embodiments may not be limited hereto. Accordingly, the recess141bmay have, for example, U-shape, V-shape, rectangular-shape, trapezoid-shape, and so on.

The device isolating film175may fill the recess141b.Accordingly, the device isolating film175may extend in the second direction Y1. The device isolating film175may be formed on the field insulating film110, and formed within the first fin F1. Because the device isolating film175fills the recess141b,the lower surface of the device isolating film175may be lower than lower surfaces of the first to fourth source/drains125a,125b,123,124. The device isolating film175may isolate the first and second source drains125a,125bformed on both sides of the device isolating film175, to block a short and hinder or prevent the currents from flowing. The device isolating film175may be, for example, an oxide film, a nitride film, an oxynitride film, and so on. The device isolating film175may be spaced apart from the first to fourth source/drains125a,125b,123,124.

A liner173may be disposed between the recess141band the device isolating film175. The liner173may be formed substantially conformally along the sidewalls of the first and second spacers117, an upper surface of the first fin F1, and an inner surface of the recess141b.The liner173may be disposed on the first fin F1and the field insulating film110.

The first spacer117aand the second spacer117bmay have a sloped upper surface. The upper surface of the first spacer117amay be highest in a direction of the first gate structure151aand may decrease in a direction of the second gate structure151b.On the other hand, the upper surface of the second spacer117bmay be highest in a direction of the second gate structure151band become lower in a direction of the first gate structure151a.

The upper surface of the liner173may be also highest at a portion in contact with the first and second spacers117and become lower as distance increases. A portion of the upper surface of the liner173, which is in contact with the device isolating film175, may have the same height as the height of the upper surface of the device isolating film175.

The first to fourth source/drains125a,125b,123,124may be disposed on both sides of the first and second gate structures151a,151band both sides of the device isolating film175. In other words, the first source/drain125amay be disposed between ate structure151aand the first spacer117a,and the second source/drain125bmay be disposed between the second gate structure151band the second spacer117b.Further, the third source/drain123may be disposed on a side surface opposite the device isolating film175with reference to the first gate structure151a,and the fourth source/drain124may be disposed on a side surface opposite the device isolating film175with reference to the second gate structure151b.

The first to fourth source/drains125a,125b,123,124may be disposed within the first fin F1. Accordingly, each of the first to fourth source/drains125a,125b,123,124may be respectively formed on the etched portion formed by etching a portion of the first fin F1.

The first to fourth source/drains125a,125b,123,124may be elevated source/drains. Accordingly, the upper surfaces of the first to fourth source/drains125a,125b,123,124may be higher than the upper surface of the first fin F1.

When the semiconductor device according to e example embodiments is a PMOS transistor, the first to fourth source/drains125a,125b,123,124may include a compressive stress material. For example, the compressive stress material may be a material such as SiGe, which has a greater lattice constant than Si. The compressive stress material may exert a compressive stress on the first fin F1of the lower portion of the first and second gate structures151a,152b,i.e., on the channel region, and thus enhance mobility of carriers in the channel region.

When the semiconductor device according to some example embodiments is an NMOS transistor, the first to fourth source/drains125a,125b,123,124may include the same material as the substrate101or a tensile stress material. For example, when the substrate101is Si, the first to third source/drains121,123,125may be Si, or other material (e.g., SiC, SiP) that has a lower lattice constant than Si.

The first to fourth source/drains125a,125b,123,124may be formed with the epitaxial growth.

The first to fourth source/drains125a,125b,123,124may have the silicide film161disposed thereon. The silicide film161may be formed along the upper surfaces of the first to fourth source/drains125a,125b,123,124. The silicide film161may play a role of reducing sheet resistance, contact resistance, and so on, when the first to fourth source/drains125b,123,124are respectively in contact with first and second contacts165, a third contact163, and a fourth contact164, and may include a conductive material, e.g., Pt, Ni, Co, and so on.

On the silicide film161, the first and second contacts165, the third contact163, and the fourth contact164may be formed respectively. Specifically, the first contact165aand the third contact163may be formed on both sides of the first gate structure151a.The first contact165amay be formed between the first gate structure151aand the device isolating film175. The second contact165band the fourth contact164may be formed on both sides of the second gate structure151b.The second contact165bmay be formed between the second gate structure151band the device isolating film175.

The contact163may be formed of or include a conductive material, and may include, for example, W, Al Cu, and so on, but not limited hereto.

The first interlayer insulating film131and the second interlayer insulating film132may be formed, for example sequentially formed, on the field insulating film110. The first interlayer insulating film131may overlay sidewalls of the silicide film161and the first spacer115, and partially overlay a sidewall of the contact163. The second interlayer insulating film131may overlay the other remaining sidewall of the contact163.

The capping film133may be positioned between the first interlayer insulating film131and the second interlayer insulating film132. Specifically, the capping film133may be formed on the device isolating film175, the liner173, the first and second spacers117, and the first interlayer insulating film131. The capping film133may include at least one of silicon oxide and silicon nitride.

As illustrated inFIG. 2, an upper surface of the first interlayer insulating film131and an upper surface of the capping film133may be positioned on a same plane as upper surfaces of the first and second gate structures151a,151b.Through the planarization process (e.g., CMP process), an upper surface of the first interlayer insulating film131and upper surfaces of the first and second gate electrodes151a,151band the capping film133may be coplanar. The second interlayer insulating film132may be formed to overlay the first and second gate structures151a,151band the capping film133. The first interlayer insulating film131and the second interlayer insulating film132may include at least one of an oxide film, a nitride film, and an oxynitride.

Although the capping film133is illustrated as a separate constituent element in the drawings, the second interlayer insulating film132and the first interlayer insulating film131may fill the area instead of the capping film133. Alternatively,the device isolating film175may fill the area instead of the capping film133. However, example embodiments are not limited to the example given above.

In the semiconductor device according to some example embodiments, the first spacer117aand the second spacer117bmay have a proper height range. That is, heights of the first spacer117aand the second spacer117bmay be greater than an upper surface of the first fin F1, and less than the first gate structure151aand the second gate structure151b.

When heights of the first spacer117aand the second spacer117bare too low, stress characteristic of a material of the device isolating film175may influence the first source/drain125a,the second source/drain125b,and a channel region adjacent to the first and second source/drains151a,151b(i.e., the first fin F1region under the first gate structure151aand the second gate structure151b). Accordingly, characteristic of the transistor may be modified in a way that is not intended.

On the other hand, when heights of the first spacer117aand the second spacer117bare too high, the first spacer117aand the second spacer117bare sloped, and accordingly, the first contact165aand the second contact165bmay not be properly formed in the subsequent process, as these overlap with vertical positions of the first spacer117aand the second spacer117b.That is, the first source/drain125aand the first contact165amay not be connected due to the first spacer117a,and the second source/drain125band the second contact165bmay not be connected due to the second spacer117b.

Accordingly, some example embodiments can encourage the first contact165aand the second contact165bto be formed into a complete shape while keeping the first spacer117aand the second spacer117at proper heights, and minimize stress caused by the device isolating film175on the channel region, thereby considerably enhancing performance of the semiconductor device.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 4 and 5. In the following description, description overlapped with the example embodiments already provided above will not be described or described as brief as possible for the sake of brevity.

FIG. 4is a cross sectional view of a semiconductor device according to some example embodiments, andFIG. 5is an enlarged cross sectional view of the encircled section B ofFIG. 4.

Referring toFIGS. 4 and 5, the semiconductor device according to some example embodiments may additionally include an inner spacer170.

The inner spacer170may be disposed between the device isolating film175and the first spacer117aand the second spacer117b.Specifically, the inner spacer170may be formed on sidewalls of the first spacer117aand the second spacer117b.A profile of the inner spacer170may be connected with a profile of the recess141b.The liner173may be conformally formed along inner surfaces of the inner spacer170and the recess141b,and the device isolating film175may be formed on the liner173.

With the inner spacer170, the recess141bmay include a smooth sidewall without a presence of jaw structure. An upper surface of the inner spacer170may be sloped. The inner spacer170may be highest at a portion thereof in contact with the first and second spacers117, and may have an upper surface that gradually decreases as distance from the first and second spacers117increases.

The capping film133may be formed on the first interlayer insulating film131, the inner spacer170, the liner173, and the device isolating film175.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 6 and 7. In the following description, any description that overlaps the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIG. 6is a cross sectional view of a semiconductor device according to some example embodiments, andFIG. 7is an enlarged cross sectional view of the encircled section B ofFIG. 6.

Referring toFIGS. 6 and 7, the semiconductor device according to some example embodiments may additionally include a second liner174.

The second liner174may be formed between the liner173and the device isolating film175, and the second liner174may be formed conformally along inner surfaces of the inner spacer170and the recess141b.

For example, the second liner174may include at least one of silicon oxide, silicon nitride, silicon oxynitride, Hf oxide, La oxide, polysilicon, Ge, Ge oxide, Ti oxide, and W oxide.

In the semiconductor device according to some example embodiments, multi-films of the liner173and the second liner174may hinder or prevent formation of an air gap with the restoration of the damaged surface portion of the recess141band gap filling capacity.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 8 and 9. In the following description, description overlapped with the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIG. 8is a cross sectional view of a semiconductor device according to some example embodiments, andFIG. 9is an enlarged cross sectional view of the encircled section B ofFIG. 8.

Referring toFIGS. 8 and 9, the device isolating175of the semiconductor device according to some example embodiments may substantially fill the recess141bwithout the liner. That is, the device isolating film175may be directly in contact with a sidewall of the recess141b.

However, the side surface of the upper portion of the device isolating film175may not be in contact with the first spacer117aand the second spacer117b,and may be in contact with the inner spacer170.

Accordingly, the capping film133may overlay the upper surfaces of the first interlayer insulating film131, the first spacer117a,the second spacer117b,the inner spacer170and the device isolating film175.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 10 and 11. In the following description, description overlapped with the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIG. 10is a cross sectional view of a semiconductor device according to some example embodiments, andFIG. 11is an enlarged cross sectional view of the encircled section B ofFIG. 10.

Referring toFIGS. 10 and 11, the first spacer117aand the second spacer117bof the semiconductor device according to some example embodiments may have a L-shape.

Specifically, a width of the lower portion of the first spacer117aand the second spacer117bmay become greater than a width of the upper portion of the first spacer117aand the second spacer117b,upon removal of the inner side surface of the upper portion of the first spacer117aand the second spacer117b.

Accordingly, the first spacer117aand the second spacer117bmay have a L-shape that have a protruding portion in a direction of the first spacer117aand the second spacer117bfacing each other. This may be attributable to the removal of the portion of the first and second spacers117with the chamfering process of forming the inner spacer170. Accordingly, the liner173may be formed conformally along the inner side surface of the L-shaped first and second spacers117.

With the chamfered shape, a width of the upper portion of the device isolating film175may be formed to be broader than a width of the lower portion. In an example embodiment, the device isolating film175may have an discontinuous side surface profile. That is, a stepped portion may be formed on the portion in which a width becomes broader, such that the upper portion and the lower portion having different widths may be clearly distinguished.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIG. 12. In the following description, description overlapped with the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIG. 12is a cross sectional view of a semiconductor device according to some example embodiments.

Referring toFIG. 12, the upper surface of the device isolating film175may have a downward convex shape according to some example embodiments. That is, the upper surface of the device isolating film175may have a downward convex profile, and the lower surface of the capping film133may correspondingly include a convex portion.

The upper surface of the device isolating film175may decrease as the distance increases from the first and second spacers117. This may be attributable to the fact that etch selectivities of the liner173and the device isolating film175are different from each other. That is, because an etch selectivity of the device isolating film175is greater than the etch selectivity of the liner173, the device isolating film175may be further etched than the liner173, and may have a downward convex shape.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIG. 13. In the following description, description overlapped with the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIG. 13is a cross sectional view of a semiconductor device according to some example embodiments.

Referring toFIG. 13, the recess141bof the semiconductor device according to some example embodiments may have V-shape in which a lower portion is pointed.

When the recess141bhas V-shape as illustrated in the drawing, a distance between the first source/drain125aand the second source/drain125band the device isolating film175within the recess141bmay become relatively longer.

Accordingly, stress characteristic of the device isolating film175may minimize influence on the first source/drain125aand the second source/drain125b.Further, likewise, influence of stress of the device isolating film175affecting the channel region of the lower portion of the first gate structure151aand the second gate structure151b,may be minimized.

Hereinbelow, a semiconductor device according to some example embodiments will be described with reference toFIGS. 1 to 3 and 14 to 31. In the following description, description overlapped with the example embodiments already provided above will not be described, or described briefly, for the sake of brevity.

FIGS. 14 to 31are views illustrating intermediate stages of fabrication in a method for fabricating a semiconductor device, according to some example embodiments. Specifically,FIG. 17is a cross sectional view taken on line A-A ofFIG. 16, andFIG. 18is a cross sectional view taken on line B-B ofFIG. 16.FIG. 21is a cross sectional view taken on line A-A ofFIG. 20, andFIG. 23is a cross sectional view taken on line A-A ofFIG. 22.FIGS. 23 to 31are cross sectional views describing a following process with respect to the cross sectional view ofFIG. 23.

Referring first toFIG. 14, the first fin F1may be formed on the substrate101. The first fin F1may be formed on the substrate101and protrude in the third direction Z1. The first fin F1may extend longitudinally along the first direction X1which is a length direction, and may have a long side in the first direction X1and a short side in the second direction Y1. However, the example embodiments are not limited hereto. For example, the long side direction may be the second direction Y1, and the short side direction may be the first direction X1.

The first fin F1may be a part of the substrate101, and may include an epitaxial layer grown from the substrate101. For example, Si or SiGe may be included.

Next, referring toFIG. 15, the insulating film110amay be formed so as to overlay a sidewall of the first fin F1.

The insulating film110amay be formed of or include a material including at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

Next, referring toFIGS. 16 to 18, an upper portion of the insulating film110amay be recessed, forming the field insulating film110and exposing an upper portion of the first fin F1.

The recess process may include a selective etch process.

Meanwhile, a part of the first fin F1protruding upward from the field insulating film110may be formed with the epitaxial process. For example, after formation of the insulating film110a,instead of proceeding a recess process, a part of the first fin F1may be formed with the epitaxial process that uses an upper portion of the first fin F1exposed by the insulating film110aas a seed.

Further, a threshold voltage adjusting doping may be performed on the exposed first fin F1. For example, when the NMOS transistor is formed, the impurity may be boron (B). When the PMOS transistor is formed, the impurity may be phosphorous (P) and arsenic (As).

Next, first to third sacrificial gate structures111a,111b,111cintersecting the first fin F1may be formed on the first fin F1. The first to third sacrificial gate structures111a,111b,111cmay be spaced apart from each other. AlthoughFIG. 16illustrates that the first to third sacrificial gate structures111a,111b,111cintersect the first fin F1in a vertical direction, i.e., in the first direction X1, the example embodiments may not be limited hereto. The first to third sacrificial gate structures111a,111b,111cmay intersect the first fin F1by forming an acute and/or obtuse angle with the first direction X1.

The first to third sacrificial gate structures111a,111b,111cmay be formed on an upper surface of the first fin F1and an upper portion of the sidewall. Further, the first to third sacrificial gate structures111a,111b,111cmay be disposed on the field insulating film110. The first to third sacrificial gate structures111a,111b,111cmay be a silicon oxide film, for example.

First to third hard mask films113a,113b,113cmay be respectively formed on the first to third sacrificial gate structures111a,111b,111c.The first to third hard mask films113a,113b,113cmay be formed of or include a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Next, the first gate spacer115, the second spacer116, and the first and second spacers117may be formed on both sidewalls of the first to third sacrificial gate structures111a,111b,111c.

Specifically, the first gate spacer115may be formed on a side surface of the first sacrificial gate structure111a,the first and second spacers117may be formed on a side surface of the second sacrificial gate structure111b,and the second gate spacer116may be formed on the side surface of the third sacrificial gate structure111c.

The first gate spacer115, the second gate spacer116, and the first and second spacers117may expose upper surfaces of the first to third hard mask films113a,113b,113c.The first gate spacer115, the second gate spacer116, and the first and second spacers117may include a silicon nitride film or a silicon oxynitride film.

A remaining portion of the first fin F1other than a portion overlain by the first to third sacrificial gate structures11a,111b,111cmay be etched. Accordingly, the first fin F1exposed between the first to third sacrificial gate structures111a,111b,111cmay be etched. The first fin F1-F3may be etched by using the first gate spacer115, the second gate spacer116, the first and second spacers117, and the first to third hard mask films113a,113b,113cas an etch mask.

Next, referring toFIGS. 20 and 21, the first to fourth source/drains125a,125b,123,124may be formed on the etched portion of the first fin F1.

In the first fin F1, the first source/drain125aand the third source/drain123may be respectively formed on both sides of the first sacrificial gate structure111a,the first source/drain125aand the second source/drain125bmay be respectively formed on both sides of the second sacrificial gate structure111b,and the second source/drain125band the fourth source/drain124may be respectively formed on both sides of the third sacrificial gate structure111c.That is, the first source/drain125amay be formed between the first sacrificial gate structure111aand the second sacrificial gate structure111b,and the second source/drain125bmay be formed between the second sacrificial gate structure111band the third sacrificial gate structure111c.

The first to fourth source/drains125a,125b,123,124may be elevated source/drains. Accordingly, the upper surfaces of the first to fourth source/drains125a,125b,123,124may be higher than the upper surface of the first fin F1.

When the semiconductor device according to some example embodiments is a PMOS transistor, the first to fourth source/drains125a,125b,123,124may include a compressive stress material. For example, the compressive stress material may be a material such as SiGe, which has a greater lattice constant than Si. The compressive stress material may later exert a compressive stress on the first fin F1(i.e., channel region) under the first and second gate structures151a,152b,thereby enhancing mobility of carriers in the channel region.

When the semiconductor device according to an example embodiment is the NMOS transistor, the first to fourth source/drains125a,125b,123,124may include a tensile stress material. The first to fourth source/drains125a,125b,123,124may be the same material as the substrate101, or a tensile stress material. For example, when the substrate101is Si, the first to fourth source/drains125a,125b,123,124may be Si, or a material (e.g., SiC, SiP) that has a lower lattice constant than Si.

The first to fourth source/drains125a,125b,123,124may be formed via, for example, epitaxial growth.

Next, referring toFIGS. 22 and 23, the first interlayer insulating film131overlying the first to fourth source/drains125a,125b,123,124may be formed.

The first interlayer insulating film131may overlay sidewalls of the first gate spacer115, the second gate spacer116, and the first and second spacers117, and expose upper surfaces of the first to third hard mask films113a,113b,113c.For example, the first interlayer insulating film131may include an oxide film.

Next, referring toFIG. 24, a first etch mask film137exposing the second sacrificial gate structure111bmay be formed on the first to third sacrificial gate structures111a,111b,111c.

A plurality of etch mask films may be formed for more precise and correct performance of the etch process.

In order to form the first etch mask film137, the process may include forming the first etch mask film137, forming a photo resist pattern on the first etch mask film137, and patterning the first etch mask film137by using the photo resist pattern.

The first etch mask film137may expose the second sacrificial gate structure111b.

Next, referring toFIG. 25, after the first etch mask film137is formed, a first mask spacer1137may be formed on a sidewall of the first etch mask film137.

When the first mask spacer1137is formed, the exposed portion of the first interlayer insulating film131may be hindered or prevented from being etched.FIGS. 24 and 25illustrate that the adjacent first interlayer insulating film131is exposed as well as the second sacrificial gate structure111b,although example embodiments are not limited hereto. In the semiconductor device according to some example embodiments, the first etch mask film137may expose only the second sacrificial gate structure111b.In the above case, the first mask spacer1137may not be necessarily formed.

Next, referring toFIG. 26, the second sacrificial gate structure111bmay be removed by using the first etch mask film137.

Simultaneously or contemporaneously with, or sequentially to, the removal of the second sacrificial gate structure111b,the first mask spacer1137may be removed. The upper surface of the first fin F1may be exposed by removing the second sacrificial gate structure111b.

Next, referring toFIG. 27, the inner spacer170amay be formed within the first recess141.

As illustrated inFIG. 27, the inner spacer170amay be formed along an upper surface and a sidewall of the first etch mask film137, an upper surface and a sidewall of the first and second spacers117, and the upper surface of the first fin F1.

Next, referring toFIG. 28, the spacer170may be left only on the sidewall of the first etch mask film137and the sidewall of the first and second spacers117, while the other portions may be removed by using an etch-back process, and so on. Accordingly, the upper surface of the first fin F1may also be exposed.

Next, a second mask spacer1138may be formed.

The second mask spacer1138may play a role in blocking the exposed portion of the first interlayer insulating film131from etching, for example subsequent etching. According to some example embodiments, the first etch mask film137may be formed to overlie the entire first interlayer insulating film131.

Next, referring toFIG. 29, the second recess141bmay be formed by etching the exposed upper surface of the first fin F1.

The second recess141bmay be formed by using the first etch mask film137and the inner spacer170as the etch mask. A width of the second recess141bmay be adjusted by adjusting a width of the inner spacer170. A lower surface of the second recess141bmay be lower than a lower surface of the first to fourth source/drains125a,125b,123,124.

Next, referring toFIG. 30, the second mask spacer1138and the inner spacer170may be removed.

Next, the liner173amay be formed. The liner173amay be formed along the upper surface and the sidewall of the first etch mask film137, the upper surface and the sidewall of the first and second spacers117, and an inner surface of the second recess141b.

For example, the liner173amay include at least one of an oxide film, a nitride film, and an oxynitride film.

Next, referring toFIG. 31, the device isolating film175may be filled in the second recess141b.The filled device isolating film175may have tensile stress characteristic, and accordingly, the first and second spacers117may be sloped outwardly.

Next, the first and second spacers117, the first interlayer insulating film131, and the device isolating film175may be etched by using the first etch mask film137as a mask. The above may be referred to as the ‘chamfering process’.

Accordingly, a portion of the upper surface of the first interlayer insulating film131, the upper surface of the first and second spacers117, and the upper surface of the liner173may all be formed at slope. That is, an angle between an outer side surface of the first and second spacers117and the upper surface of the first fin F1may be equal to or greater than about 85 degrees and less than about 90 degrees. However, example embodiments are not limited to the example given above.

Further, a height D2of the first and second spacers117may be less than the height of the first gate structure151aand the second gate structure151b.Specifically, a height D2of the first and second spacers117may be less than, by the first distance D1, the height of the first gate structure1510and of the second gate structure151b.

Next, referring toFIGS. 1 to 3, the process of forming the capping film133on the device isolating film175, performing the planarization process, forming the second interlayer insulating film, and forming the silicide film161and the first to fourth contacts165,163,164may be performed.

In an example, as a height of the first and second spacers117becomes lower, the first and second contacts165can be substantially completely formed. Further, as the first and second spacers117may remain rather than being completely removed, the influence of stress on a device of a periphery of the device isolating film175can be minimized.