Analog-to-digital converter and wireless communication device

According to one embodiment, an analog-to-digital converter includes a first digital-to-analog converter, a comparator configured to digitally output based on a first clock signal, a clock generator configured to generate the first clock signal from an input clock signal, and a controller configured to control the first digital-to-analog converter. The clock generator sets a cycle of the first clock signal to a first cycle if the input clock signal is at a first logic level, and sets the cycle of the first clock signal to a second cycle shorter than the first cycle if the input clock signal is at a second logic level.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-170255, filed Sep. 5, 2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to analog-to-digital converters and wireless communication devices.

BACKGROUND

As a type of analog-to-digital converter (hereinafter, also called “AD converter”), successive-approximation type AD converters are known. Analog-to-digital (AD) conversion operations by successive-approximation type AD converters involve a period for sampling input analog signals and a period for converting the sampled input analog signals (successive approximation period). Reducing the period for converting is an important factor in improving the processing speed of the AD converters.

DETAILED DESCRIPTION

In general, according to one embodiment, an analog-to-digital converter includes: a first digital-to-analog converter which is configured to generate a first analog voltage based on a sampled first analog signal and a digital code; a comparator to which the first analog voltage is input and which is configured to digitally output based on a first clock signal; a clock generator which is configured to generate the first clock signal from an input clock signal; and a controller which is configured to generate the digital code based on the digital output of the comparator and to control the first digital-to-analog converter. The clock generator sets a cycle of the first clock signal to a first cycle if the input clock signal is at a first logic level, and sets the cycle of the first clock signal to a second cycle shorter than the first cycle if the input clock signal is at a second logic level.

1. First Embodiment

An analog-to-digital converter (hereinafter, also called “AD converter”) and a wireless communication device according to the first embodiment will be described. The following descriptions will assume that this AD converter is a successive-approximation type AD converter.

1.1. General Configuration of Wireless Communication Device

First, an entire configuration of the wireless communication device will be described. A wireless communication device1includes a digital signal processor10, a receiver11, a transmitter12, an input/output circuit13, and an antenna14.

The receiver11converts radio-frequency signals (hereinafter, also called “analog signals”) from an external device into digital signals, and transmits the digital signals to the digital signal processor10. The receiver11includes a low noise amplifier (LNA)20, a low pass filter (LPF)21, an amplifier (AMP)22, and an AD converter23.

The low noise amplifier20amplifies weak analog signals received via the antenna14and the input/output circuit13, with relatively low noise.

The low pass filter21attenuates the analog signals amplified by the low noise amplifier20for frequency components lower than the cut-off frequency.

The amplifier22amplifies the analog signals filtered by the low pass filter21to an amplitude (voltage) required for the processing in the AD converter23.

The AD converter23converts the input analog signals into digital signals and transmits the digital signals to the digital signal processor10.

The digital signal processor10performs various processing based on the digital signals received from the receiver11. The digital signal processor10also transmits digital signals to the transmitter12based on the results of various types of processing.

The transmitter12includes a digital-to-analog converter (not shown) to convert the digital signals received from the digital signal processor10into analog signals, and transmits the analog signals to the input/output circuit13.

The input/output circuit13transmits signals received via the antenna14to the receiver11. The input/output circuit13also transmits signals received from the transmitter12to an external device via the antenna14.

1.2 Configuration of AD Converter

Next, the configuration of the AD converter23will be described with reference toFIG. 2. Example ofFIG. 2shows differential signal input successive-approximation type AD converter23which generates 8-bit digital signals. The bit number of the digital signals generated by the AD converter23may be discretionarily set. The AD converter23may also be a successive-approximation type AD converter adapted for the input of single-phase signals.

The AD converter23performs successive approximation of analog signal voltages Va to a voltage based on a reference voltage Vref, sequentially from the most significant bit (MSB) to the least significant bit (LSB), and generates a digital signal. The reference voltage Vref is a voltage that constitutes a criterion for assessing the analog signal voltages Va. For example, in the assessment for the MSB, if a voltage Va is equal to or higher than (½)Vref ((Va−(½)Vref)≥0), the MSB is determined to be at a “High” (“H”) level (data “1”). If the voltage Va is lower than (½)Vref ((Va−(½)Vref)<0), the MSB is determined to be at a “Low” (“L”) level (data “0”). In the assessment for the next significant bit, if data “1” has been determined, a voltage Va is compared to a ((½)+(¼))Vref, and if data “0” has been determined, the voltage Va is compared to a ((½)−(¼))Vref. Similar assessment continues until the least significant bit (LSB). As such, as the digital conversion proceeds from the MSB toward the LSB, the degree of variations in the comparative voltages based on the reference voltage Vref becomes smaller as (½)Vref, (½2)Vref, . . . , and (½n)Vref (n being a bit number).

The AD converter23includes a digital-to-analog converter (hereinafter, “DAC”)30a, a DAC30b, a comparator31, a successive-approximation register32, a DAC controller33, and a CLK generator34. The DACs30aand30bcorrespond to respective analog voltages Va+ and Va− of a differential input signal, and have similar configurations.

The DAC30aincludes three input terminals coupled to respective input terminals of the AD converter23, namely, an input terminal for the analog voltage Va+(or may be called “analog signal input terminal”), an input terminal for a reference voltage VrefH, and an input terminal for a reference voltage VrefL. The reference voltage VrefH is a high-side reference voltage, and the reference voltage VrefL is a low-side reference voltage. The difference in potential between the reference voltages VrefH and VrefL corresponds to the voltage Vref. An output terminal of the DAC30ais coupled to a non-inverting input terminal (+ terminal) of the comparator31. The DAC30asamples the analog voltages Va+ of analog signals and temporarily holds (stores) them. During the successive approximation, the DAC30agenerates analog voltages that differ for respective bits for comparison, based on 8-bit digital signals S_dac received from the DAC controller33. The DAC30acombines the generated analog voltage and the sampled voltage Va+, and outputs this composite voltage to the comparator31. The DAC30aincludes multiple samplers40and a switching element44. The number of the samplers40may be determined based on the number of bits subjected to the AD conversion by the AD converter23. For 8-bit AD conversion, eight samplers40are provided, for example.

Each sampler40includes a capacitive element41and switching elements42and43. The capacitive elements41included in the multiple samplers40are different in capacitance value each other. For example, for the 8-bit AD converter23, the capacitance values of the capacitive elements41are set so that voltages (½1)Vref, (½2)Vref, . . . , and (½8)Vref can be generated based on the digital signals S_dac. The capacitive element41includes a first electrode coupled to an output terminal of the switching element42, and a second electrode coupled to the output terminal of the DAC30a.

The switching element42includes a first input terminal to which the voltage VrefH is applied, and a second input terminal to which the voltage VrefL is applied. The switching element42selects the first input terminal or the second input terminal according to the signal S_dac when the switching element43is in an OFF state.

The switching element43includes an input terminal coupled to the input terminal for the analog voltage Va+, and an output terminal coupled to the first electrode of the capacitive element41. The switching element43connects the input terminal for the analog voltage Va+ to the corresponding sampler40according to a sampling clock signal CLK_S received from the CLK generator34.

The switching element44applies a voltage Vcom (e.g., ground voltage VSS) according to a clock signal (not shown) received from the CLK generator34.

When, for example, the DAC30asamples an analog signal, the switching element43in each sampler40is set to an ON state, and the switching element42is set to a state where neither the first nor the second input terminal is selected. The switching element44is then set to an ON state. This causes the capacitive element41in each sampler40to be charged by the analog voltage Va+.

When the DAC30agenerates an analog voltage according to the digital signal S_dac, the switching element43in each sampler40is set to an OFF state. The switching element42then selects the first or the second input terminal according to the digital signal S_dac.

The DAC30bis of a similar configuration to the DAC30a, so its descriptions will be omitted. The differences are that an input terminal of the DAC30bis coupled to an input terminal of the AD converter23for the analog voltage Va−, and that an output terminal of the DAC30bis coupled to an inverting input terminal (− terminal) of the comparator31.

The comparator31is a differential output type comparator, and outputs positive-side digital signals (voltage Vop) and negative-side digital signals (voltage Von). Output terminals of the comparator31are coupled to the successive-approximation register32and a CLK_C generator35, respectively. The comparator31compares the output voltage of the DAC30ato the output voltage of the DAC30bfor each bit, and sends the comparison result to the successive-approximation register32and the CLK_C generator35. The comparator31performs comparison if a comparator clock signal CLK_C received from the CLK_C generator35is at, for example, the “H” level.

The successive-approximation register32temporarily holds an 8-bit digital signal received from the comparator31. The 8-bit digital signal held in the successive-approximation register32is transmitted to the DAC controller33and the output terminal of the AD converter23.

The DAC controller33transmits the 8-bit digital signal S_dac to the DACs30aand30bto control the DACs30aand30b. More specifically, the DAC controller33generates the digital signal S_dac based on the digital signal of each bit (result of the successive approximation) received from the successive-approximation register32, and transmits the digital signal S_dac to the DACs30aand30b.

The CLK generator34generates the sampling clock signal CLK_S and the comparator clock signal CLK_C based on, for example, a master clock signal MCLK (i.e., input clock signal). The master clock signal MCLK is an input clock signal received by the AD converter23from external devices (including other circuits in the wireless communication device1). The CLK generator34includes the CLK_C generator35.

The CLK_C generator35generates the comparator clock signal CLK_C based on the master clock signal MCLK. More specifically, the CLK_C generator35generates, for example, eight “H” (high)-level pulses in dealing with 8-bit AD conversion. In this instance, the CLK_C generator35varies inter-pulse periods (hereinafter, “settling periods”), that is, an amount of delay up to generation of the next pulse, at the timing of the fall of the master clock signal MCLK, for example. The CLK_C generator35keeps a constant length for “H”-level pulses, irrespective of the amount of delay. Assuming that one cycle of the comparator clock signal CLK_C is defined by the time points to output “H”-level pulses by the comparator clock signal CLK_C (period between the rise to the “H” level and the next rise to the “H” level), the CLK_C generator35varies the cycle of the comparator clock signal CLK_C based on the master clock signal MCLK.

During the settling period, the DACs30aand30bundergo charge and discharge of the capacitive elements41for the AD conversion of the next bit. Accordingly, the output voltages of the DACs30aand30beach saturate during the settling period.

1.3 Overall Flow of AD Conversion Operations

Next, the overall flow of the AD conversion operations will be described with reference toFIG. 3.FIG. 3shows an example of the AD conversion operations for one cycle.

As shown inFIG. 3, the AD converter23first samples analog signals (step S1). More specifically, in the sampling period, the CLK generator34sets the sampling clock signal CLK_S to the “H” level. The DACs30aand30btake in the respective analog input signals (analog voltages Va+ and Va−) based on the “H”-level sampling clock signal CLK_S.

After the sampling, the CLK_C generator35generates a pulse signal of the comparator clock signal CLK_C (step S2). More specifically, the CLK generator34sets the sampling clock signal CLK_S to the “L” level, in response to, for example, the timing of the rise of the master clock signal MCLK. Then, after the sampling clock signal CLK_S has been set to the “L” level, the CLK_C generator35generates a pulse of the comparator clock signal CLK_C and transmits it to the comparator31. Upon receipt of the “H”-level comparator clock signal CLK_C, the comparator31compares the analog voltages received from the DACs30aand30b, and sends the comparison result to the successive-approximation register32and the CLK_C generator35.

If the pulse number of the comparator clock signals CLK_C is not yet reach a prescribed number (for example, eight for the case of 8-bit conversion) (step S3_No), the CLK_C generator35sets the settling period.

More specifically, if the master clock signal MCLK is at the “H” level (step S4_Yes), the CLK_C generator35sets the settling period after the pulse generation to a first settling period ST1(step S5). On the other hand, if the master clock signal MCLK is at the “L” level (step S4No), the CLK_C generator35sets the settling period after the pulse generation to a second settling period ST2(step S6). The relationship between the first settling period ST1and the second settling period ST2is given as ST1>ST2. That is, the second settling period ST2provides an amount of delay before generation of the next pulse, which is smaller than that of the first settling period ST1. As such, upon the master clock signal MCLK becoming the “L” level, the CLK_C generator35reduces the pulse cycle of the comparator clock signal CLK_C. Assuming that the cycle of the comparator clock signal CLK_C with the “H”-level master clock signal MCLK is a first cycle, and that the cycle of the comparator clock signal CLK_C with the “L”-level master clock signal MCLK is a second cycle, the relationship, first cycle >second cycle, is given.

After the passage of the set settling period, the AD converter23returns to the operation in step S2, where a pulse of the comparator clock signal CLK_C is generated.

Upon the pulse number of the comparator clock signal CLK_C reaching the prescribed number (step S3_Yes), the AD converter23terminates the AD conversion operations for one cycle.

1.4 Each Signal in AD Conversion Operations

Next, each signal in the AD conversion operations will be described with reference toFIG. 4.FIG. 4is an example showing in particular the AD converter operation period (hereinafter, “ADC operation period”) for one cycle of the AD conversion. Also,FIG. 4illustrates one example of the potential difference (symbol “Comp_IN”) between the comparator's non-inverting input terminal and inverting input terminal, that is, the potential difference between the output voltages of the DACs30aand30b. However, different waveforms may occur depending on analog signals and the results of comparison between respective bits.

As shown inFIG. 4, the AD converter23starts the sampling operation at time t0. More specifically, the CLK generator34terminates the oscillation (pulse generation) for the comparator clock signal CLK_C in the CLK_C generator35, and sets the sampling clock signal CLK_S to the “H” level. The DACs30aand30bstart sampling analog signals based on the sampling clock signal CLK_S. In the following descriptions, the period from time t0through time t1will be called “sampling period”.

At time t1, the AD converter23terminates the sampling. More specifically, upon the master clock signal MCLK having risen to the “H” level, or upon a clock signal CLKB having fallen, the CLK generator34sets the sampling clock signal CLK_S to the “L” level. The DACs30aand30bterminate sampling the analog signals based on the sampling clock signal CLK_S.

For the period from time t1through time t2, the DAC30agenerates an analog voltage that is a composite voltage of the sampled voltage Va+ and the voltage (½)Vref generated based on the digital signal S_dac corresponding to the MSB. The DAC30blikewise generates an analog voltage that is a composite voltage of the sampled voltage Va− and the voltage (½)Vref generated based on the digital signal S_dac. Then, the output voltages of the DACs30aand30beach saturate during the period from time t1through time t2. For example, in the example shown inFIG. 4, the potential difference Comp_IN between the output voltages of the DACs30aand30bsaturates on the positive voltage side.

At time t2, the AD converter23starts successive approximation. For the period from time t2through time t4, the AD converter23performs, for example, 8-bit successive approximation. In the following descriptions, the period from time t2to time t4will be called “conversion period (successive-approximation period)”.

More specifically, for the period from time t2through time t3, the CLK_C generator35sets the first settling period ST1based on the “H”-level master clock signal MCLK (“L”-level clock signal CLKB). In the example shown inFIG. 4, the CLK_C generator35generates four pulses with the first settling period ST1intervening therebetween. Also, for the period from time t3through time t4, the CLK_C generator35sets the second settling period ST2based on the “L”-level master clock signal MCLK (“H”-level clock signal CLKB). The CLK_C generator35then generates, for example, four pulses with the second settling period ST2intervening therebetween. That is, the first settling period ST1as a relatively longer settling period is set for the conversion of higher 4 bits including the MSB, and the second settling period ST2as a relatively shorter settling period is set for the conversion of lower 4 bits including the LSB. The bit numbers corresponding to the first settling period and the second settling period may each be discretionarily set.

In the conversion for each bit, the output voltages of the DACs30aand30b, that is, the potential difference Comp_IN, saturates before passage of the first settling period ST1or the second settling period ST2. At this time, as the AD conversion proceeds from the MSB to LSB, the changes in the output voltages of the DACs30aand30bbecome smaller or, in other words, the degree of variations in the potential difference Comp_IN becomes smaller. As such, the period required for the potential difference Comp_IN to saturate (stabilizing period) is made shorter.

At time t4, the AD converter23terminates the AD conversion operations for the first cycle, and starts the second AD conversion operations as in the time t0. The period from time t0through time t4corresponds to the ADC operation period for one cycle.

At time t5, the AD converter23terminates the sampling as in time t1. The period from time t1through time t5indicates one cycle of the master clock signal MCLK.

1.5 Effect of Present Embodiment

With the configurations according to this embodiment, the processing speed of a wireless communication device installed with an AD converter in the receiver can be improved. This effect will be explained.

In a successive-approximation type AD converter, when an MSB to an LSB are sequentially subjected to successive approximation, the degree of variations in the DAC's output voltages becomes smaller as the AD conversion proceeds from the MSB to the LSB. Accordingly, as the AD conversion proceeds from the MSB to the LSB, the stabilizing period required for the saturation of the DAC's output voltages becomes shorter. On the other hand, successive-approximation type AD converters generally perform successive approximation in constant cycles, irrespective of the bits for AD conversion. This case represents a setting state where the settling periods, i.e., the cycles of comparator clock signals, are excessively long for the conversion of lower bits which involve a relatively short stabilizing period for the DAC's output voltages. In the AD conversion operations for one cycle, the sampling period decreases by as much as the extended cycles of comparator clock signals, i.e., the prolonged conversion period (successive-approximation period). Thus, this would hamper the improvement of the processing speed of AD converters.

In contrast, in the configurations according to the present embodiment, the AD converter23includes the CLK_C generator35. The CLK_C generator35is capable of changing the length of the settling periods for the comparator clock signals CLK_C, that is, the amount of delay up to generation of the next pulse, based on the master clock signal MCLK. Thereby, the cycles of the comparator clock signals CLK_C can be changed. More specifically, the settling periods can be set shorter in response to, for example, the timing of the fall of the master clock signal MCLK. Accordingly, by reducing the settling periods, i.e., the cycles of the comparator clock signals CLK_C, for the AD conversion of lower bits which involve a relatively short stabilizing period for DAC's output voltages, the conversion period can be made shorter. Therefore, the AD conversion operations for one cycle can be shortened, and the processing capacity can be improved.

2. Second Embodiment

Next, an AD converter and a wireless communication device according to the second embodiment will be described. For the second embodiment, a concrete example of the CLK_C generator35from the first embodiment will be set forth. The following descriptions will concentrate on the differences from the first embodiment.

2.1 Configuration of CLK_C Generator

The CLK_C generator35will be described with reference toFIG. 5.

As shown inFIG. 5, the CLK_C generator35includes a comparison detector50, a CLK_C delay circuit51, a CLK_C output circuit52, and a counter53.

The comparison detector50includes two input terminals to which voltages Vop and Von are applied. A detection signal S_dt is output from an output terminal of the comparison detector50. For example, the comparison detector50monitors the voltages Vop and Von, sets the detection signal S_dt to the “H” level for the period during which the comparison operation is performed by the comparator31(when there is a difference between the voltages Vop and Von), and sets the detection signal S_dt to the “L” level for the period during which the comparison operation is not performed (when there is no difference between the voltages Vop and Von).

The CLK_C delay circuit51includes three input terminals to which the detection signal S_dt, the master clock signal MCLK, and the comparator clock signal CLK_C are input, respectively. A delay signal S_dly is output from an output terminal of the CLK_C delay circuit51. The CLK_C delay circuit51outputs the delay signal S_dly by delaying the detection signal S_dt based on the master clock signal MCLK and the comparator clock signal CLK_C. More specifically, the CLK_C delay circuit51, for example, takes in the master clock signal MCLK at the timing that the comparator clock signal CLK_C rises to the “H” level. Then, if the master clock signal MCLK is at the “H” level, the CLK_C delay circuit51outputs the “L”-level delay signal S_dly that is the “L”-level detection signal S_dt delayed by a first delay period (first settling period ST1). If the master clock signal MCLK is at the “L” level, the CLK_C delay circuit51outputs the “L”-level delay signal S_dly that is the “L”-level detection signal S_dt delayed by a second delay period (second settling period ST2). Also, the CLK_C delay circuit51outputs the “H”-level delay signal S_dly by delaying the “H”-level detection signal S_dt by a constant delay amount, irrespective of the master clock signal MCLK. The amount of delay in this instance corresponds to the “H”-level period (pulse length) of the comparator clock signal CLK_C.

The CLK_C output circuit52includes three input terminals to which the delay signal S_dly, a conversion start signal S_st from the CLK generator34, and an output signal S_ct from the counter53are input. The comparator clock signal CLK_C is output from an output terminal of the CLK_C output circuit52. The CLK_C output circuit52starts generating the first pulse of the comparator clock signal CLK_C upon the conversion start signal S_st having set to, for example, the “H” level. Thereafter, the CLK_C output circuit52repeats the pulse generation based on the delay signals S_dly. Also, the CLK_C output circuit52terminates the pulse generation upon, for example, receipt of a “H”-level output signal S_ct from the counter53.

The counter53counts the pulse number of the comparator clock signals CLK_C output from the CLK_C output circuit52. More specifically, upon receipt of the conversion start signal S_st, the counter53sets the output signal S_ct to the “L” level, resets the count number, and starts counting. The counter53then sets the output signal S_ct to the “H” level when the pulse count number has reached a prescribed value (for example, eight for the case of 8-bit conversion).

2.2 Operations of CLK_C Generator

Next, the operation of the CLK_C generator35will be described with reference toFIG. 6.

As shown inFIG. 6, the CLK_C output circuit52first receives the “H”-level conversion start signal S_st (step S11), and outputs the “H”-level comparator clock signal CLK_C (step S12). The CLK_C delay circuit51takes in the master clock signal MCLK at the timing that the comparator clock signal CLK_C rises to the “H” level.

The comparator31, upon receipt of the “H”-level comparator clock signal CLK_C, starts the comparison operation (step S13).

In response to the start of the comparison operation by the comparator31, the comparison detector50outputs the “H”-level detection signal S_dt based on the voltages Vop and Von (step S14).

The CLK_C delay circuit51outputs the “H”-level delay signal S_dly by delaying the “H”-level detection signal S_dt by a constant delay period (step S15).

The CLK_C output circuit52, upon receipt of the “H”-level delay signal S_dly, outputs the “L”-level comparator clock signal CLK_C (step S16).

The comparator31, upon receipt of the “L”-level comparator clock signal CLK_C, terminates the comparison operation (step S17).

In response to the termination of the comparison operation by the comparator31, the comparison detector50outputs the “L”-level detection signal S_dt based on the voltages Vop and Von (step S18).

If the master clock signal MCLK is at the “H” level (step S19_Yes), the CLK_C delay circuit51outputs the “L”-level delay signal S_dly upon passage of the first settling period ST1since the receipt of the “L”-level detection signal S_dt (step S20). On the other hand, if the master clock signal MCLK is at the “L” level (step S19_No), the CLK_C delay circuit51outputs the “L”-level delay signal S_dly upon passage of the second settling period ST2since the receipt of the “L”-level detection signal S_dt (step S21).

If the pulse number of the comparator clock signal CLK_C is not reached yet a prescribed number (step S22_No), the operation returns to step S12, where the CLK_C output circuit52outputs the “H”-level comparator clock signal CLK_C. On the other hand, if the pulse number of the comparator clock signal CLK_C has reached the prescribed number (step S22_Yes), the counter53sets the signal S_ct to the “H” level. The CLK_C output circuit52terminates the pulse generation upon receipt of the “H”-level signal S_ct.

2.3 Effect of Present Embodiment

The configurations according to this embodiment may be applied to the first embodiment. The same effect as in the first embodiment can thereby be attained.

Next, an AD converter and a wireless communication device according to the third embodiment will be described. For the third embodiment, explanations of the CLK_C delay circuit51from the second embodiment will be set forth. The following descriptions will concentrate on the differences from the first and second embodiments.

3.1 Configuration of CLK_C Delay Circuit

The CLK_C delay circuit51will be described with reference toFIG. 7.

As shown inFIG. 7, the CLK_C delay circuit51includes an inverter61, a flip-flop circuit62, and first to fourth variable delay inversion circuits63through66. The number of the variable delay inversion circuits may be discretionarily set as long as it is an even number, so that the delay signals S_dly will not be inverted.

The inverter61includes an input terminal to which the master clock signal MCLK is input. An output terminal of the inverter61is coupled to a data input terminal D of the flip-flop circuit62.

The flip-flop circuit62includes a clock signal input terminal to which the comparator clock signal CLK_C is input. The flip-flop circuit62includes a data output terminal Q to output a signal CDSB, and an inversion data output terminal to output a signal CDS. The flip-flop circuit62takes in the inverted signal of the master clock signal MCLK (clock signal CLKB) at the timing that the comparator clock signal CLK_C rises from the “L” level to the “H” level. More specifically, if the master clock signal MCLK is at the “H” level (the clock signal CLKB is at the “L” level), the signal CDSB is set to the “L” level and the signal CDS is set to the “H” level at the timing that the comparator clock signal CLK_C rises to the “H” level. If the master clock signal MCLK is at the “L” level (the clock signal CLKB is at the “H” level), the signal CDSB is set to the “H” level and the signal CDS is set to the “L” level. Note that the master clock signal MCLK and the signal CLK_C are asynchronous.

The first variable delay inversion circuit63is capable of varying the speed of the “L” to “H” level inversion when inverting input signals and outputting them. The first variable delay inversion circuit63includes an inverter63aand a variable resistor (or variable resistive element)63b.

The inverter63aincludes an input terminal to which the detection signal S_dt is input, and an output terminal coupled to an input terminal of an inverter64aof the second variable delay inversion circuit64. The inverter63aincludes a supply voltage terminal coupled to a supply voltage line via the variable resistor63b, and a ground voltage terminal which is grounded.

The resistance value of the variable resistor63bchanges based on the signal CDS. For example, the variable resistor63bis rendered in a high resistance state if the signal CDS is at the “H” level, and rendered in a low resistance state if the signal CDS is at the “L” level.

Using the change in the resistance value of the variable resistor63b, the inverter63acan adjust the amount of current flowing into the supply voltage terminal. Accordingly, the inverter63acan adjust the speed of the output signals inverting from the “L” level to the “H” level. More specifically, the amount of current flowing into the supply voltage terminal when the variable resistor63bis in the high resistance state is smaller than that when the variable resistor63bis in the low resistance state. As such, the speed of the “L” to “H” level inversion of the output signals of the inverter63ais higher with the variable resistor63bin the low resistance state (the signal CDS at the “L” level) than with the variable resistor63bin the high resistance state (the signal CDS at the “H” level).

The second variable delay inversion circuit64is capable of varying the speed of the “H” to “L” level inversion when inverting input signals and outputting them. The second variable delay inversion circuit64includes the inverter64aand a variable resistor (or variable resistive element)64b.

The inverter64aincludes an output terminal coupled to an input terminal of an inverter65aof the third variable delay inversion circuit65. The inverter64aincludes a supply voltage terminal coupled to the supply voltage line, and a ground voltage terminal grounded via the variable resistor64b.

The resistance value of the variable resistor64bchanges based on the signal CDSB. For example, the variable resistor64bis in a low resistance state if the signal CDSB is at the “H” level, and in a high resistance state if the signal CDSB is at the “L” level.

Using the change in the resistance value of the variable resistor64b, the inverter64acan adjust the amount of current flowing into the ground voltage terminal. Accordingly, the inverter64acan adjust the speed of the output signals inverting from the “H” level to the “L” level. More specifically, the amount of current flowing into the ground voltage terminal when the variable resistor64bis in the high resistance state is smaller than that when the variable resistor64bis in the low resistance state. As such, the speed of the “H” to “L” level inversion of the output signals of the inverter64ais higher with the variable resistor64bin the low resistance state (the signal CDSB at the “H” level) than with the variable resistor64bin the high resistance state (the signal CDSB at the “L” level).

The third variable delay inversion circuit65has the same circuit configuration as the first variable delay inversion circuit63. The third variable delay inversion circuit65is capable of varying the speed of the “L” to “H” level inversion when inverting input signals and outputting them. The third variable delay inversion circuit65includes the inverter65aand a variable resistor (or variable resistive element)65b. The inverter65aincludes an output terminal coupled to an input terminal of an inverter66aof the fourth variable delay inversion circuit66.

The fourth variable delay inversion circuit66has the same circuit configuration as the second variable delay inversion circuit64. The fourth variable delay inversion circuit66is capable of varying the speed of the “H” to “L” level inversion when inverting input signals and outputting them. The fourth variable delay inversion circuit66includes the inverter66aand a variable resistor (or variable resistive element)66b. The inverter66aincludes an output terminal to output the delay signal S_dly.

With the foregoing configurations, therefore, when the master clock signal MCLK is at the “H” level, the signal CDS is set to the “H” level and the signal CDSB is set to the “L” level. Then, the first to fourth variable resistors63bthrough66bare rendered in the high resistance state. This will increase the amount of delay in response to the detection signal S_dt being at the “L” level, and the “L”-level delay signal S_dly will be output upon passage of the first settling period ST1. Also, when the master clock signal MCLK is at the “L” level, the signal CDS is set to the “L” level and the signal CDSB is set to the “H” level. Then, the first to fourth variable resistors63bthrough66bare rendered in the low resistance state. This will decrease the amount of delay in response to the detection signal S_dt being at the “L” level, and the “L”-level delay signal S_dly will be output upon passage of the second settling period ST2. If the detection signal S_dt is at the “H” level, the detection signal S_dt is delayed by a constant delay period for outputting the delay signal S_dly, irrespective of the master clock signal MCLK, or the state of the signals CDS and CDSB.

3.2 Effect of Present Embodiment

The configurations according to this embodiment may be applied to the first and the second embodiments. The same effect as in the first and the second embodiments can thereby be attained.

Next, an AD converter and a wireless communication device according to the fourth embodiment will be described. For the fourth embodiment, explanations of the first to fourth variable delay inversion circuits63through66from the third embodiment will be set forth. The following descriptions will concentrate on the differences from the first through third embodiments.

4.1 Configuration of First Variable Delay Inversion Circuit

The first variable delay inversion circuit63will be described with reference toFIG. 8. Note that the third variable delay inversion circuit65is of the same configuration.

The PMOS transistor71includes a source coupled to the supply voltage line via the variable resistor63b, and a drain coupled to a drain of the NMOS transistor72and the output terminal of the inverter63a. A gate of the PMOS transistor71and a gate of the NMOS transistor72are coupled to the input terminal of the inverter63a. A source of the NMOS transistor72is grounded (coupled to the ground voltage line).

The variable resistor63bincludes a PMOS transistor73and resistive elements74and75.

The PMOS transistor73includes a source coupled to one end of the resistive element75and the supply voltage line, and a drain coupled to the other end of the resistive element75and one end of the resistive element74. The signal CDS is input to a gate of the PMOS transistor73. The other end of the resistive element74is coupled to the source of the PMOS transistor71.

For example, when the signal CDS is at the “H” level, the PMOS transistor73is in an OFF state. In this instance, a current flows into the inverter63afrom the supply voltage line via the resistive elements75and74. Assuming that the resistance value of the resistive element74is R1and the resistance value of the resistive element75is R2, the combined resistance in the variable resistor63bis then R1+R2, rendering the variable resistor63bin the high resistance state. As such, the amount of current flowing into the supply voltage terminal of the inverter63abecomes relatively small.

When the signal CDS is at the “L” level, the PMOS transistor73is in an ON state. In this instance, a current flows into the inverter63afrom the supply voltage line via the PMOS transistor73and the resistive element74. Assuming that the ON resistance of the PMOS transistor73is Ron_p1, the combined resistance in the variable resistor63bis R1+Ron_p1. The resistance values R2and Ron_p1are in the relationship R2>Ron_p1, and therefore, the variable resistor63bis in the low resistance state. As such, the amount of current flowing into the supply voltage terminal of the inverter63ais larger than that with the “H”-level signal CDS, providing a faster “L” to “H” level inversion of the output signals.

The master clock signal MCLK and the comparator clock signal CLK_C are asynchronous, and thus, the output signals of the flip-flop circuit62can be brought into a meta-stable state. That is, when the signal CDS is intermediate between the “L” level and the “H” level, the PMOS transistor73enters into a weak ON state. Assuming that the ON resistance of the PMOS transistor73in the weak ON state is Ron_p2, the relationship between the ON resistances Ron_p1and Ron_p2is Ron_p1<Ron_p2. The combined resistance in the variable resistor63bat this time is R1+(R2+Ron_p2)/(R2·Ron_p2). Accordingly, the amount of current flowing into the supply voltage terminal of the inverter63ais larger than that with the “H”-level signal CDS and smaller than that with the “L”-level signal CDS. As such, the “L” to “H” level inversion of the output signals of the inverter63ais faster than that with the “H”-level signal CDS and slower than that with the “L”-level signal CDS.

4.2 Configuration of Second Variable Delay Inversion Circuit

The second variable delay inversion circuit64will be described with reference toFIG. 9. The fourth variable delay inversion circuit66is of the same configuration.

As shown inFIG. 9, the inverter64aincludes a PMOS transistor76and an NMOS transistor77, as in the case of the inverter63a.

The PMOS transistor76includes a source coupled to the supply voltage line, and a drain coupled to a drain of the NMOS transistor77and the output terminal of the inverter64a. A gate of the PMOS transistor76and a gate of the NMOS transistor77are coupled to the input terminal of the inverter64a. A source of the NMOS transistor77is grounded via the variable resistor64b.

The variable resistor64bincludes an NMOS transistor78and resistive elements79and80.

One end of the resistive element79is coupled to the source of the NMOS transistor77. The other end of the resistive element79is coupled to a drain of the NMOS transistor78and one end of the resistive element80. A source of the NMOS transistor78and the other end of the resistive element80are grounded. The signal CDSB is input to a gate of the NMOS transistor78.

For example, when the signal CDSB is at the “L” level, the NMOS transistor78is in an OFF state. In this instance, a current flows into the ground voltage line from the inverter64avia the resistive elements79and80. The variable resistor64bis accordingly in the high resistance state. As such, the amount of current flowing into the ground voltage terminal of the inverter64abecomes relatively small.

When the signal CDSB is at the “H” level, the NMOS transistor78is in an ON state. In this instance, a current flows into the ground voltage line from the inverter64avia the resistive element79and the NMOS transistor78. Accordingly, the variable resistor64bis in the low resistance state. As such, the amount of current flowing into the ground voltage terminal of the inverter64ais larger than that with the “L”-level signal CDSB, providing a faster “H” to “L” level inversion of the output signals.

Also, when the signal CDSB is intermediate between the “L” level and the “H” level, the NMOS transistor78enters into a weak ON state. Accordingly, the amount of current flowing into the ground voltage terminal of the inverter64ais larger than that with the “L”-level signal CDSB and smaller than that with the “H”-level signal CDSB. As such, the “H” to “L” level inversion of the output signals of the inverter64ais faster than that with the “L”-level signal CDSB and slower than that with the “H”-level signal CDSB.

4.3 Each Signal in AD Conversion Operations

Next, each signal in the AD conversion operations will be described with reference toFIG. 10.FIG. 10is an example that shows in particular the ADC operation period for one cycle of the AD conversion, as inFIG. 4in the first embodiment. In this example ofFIG. 10, the signal CDSB is added. The following descriptions will concentrate on the differences fromFIG. 4in the first embodiment.

As shown inFIG. 10, the AD converter23starts the sampling operation at time t0. More specifically, the CLK generator34sets the sampling clock signal CLK_S to the “H” level. Also, the CLK_C output circuit52in the CLK_C generator35terminates the oscillation for the comparator clock signal CLK_C based on the output signal S_ct of the counter53. The output signal CDSB of the flip-flop circuit62in the CLK_C delay circuit51is set to the “L” level.

For the period from time t2through time t3, the CLK_C generator35sets the first settling period ST1after the first through third pulse generations of the comparator clock signal CLK_C.

At time t3, the master clock signal MCLK transitions from the “H” level to the “L” level. For example, the CLK_C output circuit52outputs the fourth pulse of the comparator clock signal CLK_C during the transition period of the master clock signal MCLK. The flip-flop circuit62then takes in the transitioning master clock signal MCLK, and is brought into the meta-stable state, accordingly. This results in the output signal CDSB being unstable. In this case, the CLK_C delay circuit51sets the settling period after the fourth pulse of the comparator clock signal CLK_C (hereinafter, “third settling period ST3”) to be longer than the second settling period ST2and shorter than the first settling period ST1. The first through third settling periods ST1through ST3are in the relationship ST2<ST3<ST1.

For the period from time t3through time t4, the CLK_C generator35, in response to the “L”-level master clock signal MCLK, sets the second settling period ST2after the fifth through seventh pulses of the comparator clock signal CLK_C.

4.4 Effect of Present Embodiment

The configurations according to this embodiment may be applied to the first to third embodiments. The same effect as in the first to third embodiments can thereby be attained.

Moreover, with the configurations according to this embodiment, it is possible to suppress the pulse cycles of the comparator clock signals CLK_C from becoming unstable when the CLK_C generator35is controlling the comparator clock signals CLK_C based on the master clock signal MCLK. More specifically, even when the output of the flip-flop circuit62in the CLK_C delay circuit51is in the meta-stable state, the settling periods of the comparator clock signals CLK_C can be controlled. Therefore, the reliability of the AD conversion operations by the AD converter can be improved.

The analog-to-digital converter according to the foregoing embodiments includes: a first digital-to-analog converter (30a) which is configured to generate a first analog voltage based on a sampled first analog signal (Va) and a digital code (S_dac); a comparator (31) to which the first analog voltage is input and which is configured to provide a digital output based on a first clock signal (CLK_C); a clock generator (35) which is configured to generate the first clock signal from an input clock signal (MCLK); and a controller (33) which is configured to generate the digital code based on the digital output (Vop, Von) of the comparator and to control the first digital-to-analog converter. The clock generator sets a cycle of the first clock signal to a first cycle if the input clock signal is at a first logic level (“H”), and sets the cycle of the first clock signal to a second cycle shorter than the first cycle if the input clock signal is at a second logic level (“L”).

By adopting the foregoing embodiments, AD converters with an improved processing capability can be provided.

The embodiments are not limited to the foregoing descriptions but may be applied various modifications.

For example, the DACs in the embodiments are not limited to the configurations shown inFIG. 2. Other configurations using capacitive elements, or configurations using, for example, resistive elements instead of the capacitive elements, may be employed.

Furthermore, the successive-approximation type AD converters in the embodiments are not limited to the configurations shown inFIG. 2. The AD converters are not limited to successive-approximation type AD converters, either.

In the context of the foregoing embodiments, the state intended by the expression “couple” or “connect” includes indirect connections interposing other elements, such as transistors and resistors, between the coupled elements.