ONE-TIME PROGRAMMABLE MEMORY CELL

A one-time programmable memory cell includes a transistor coupled to a capacitor. The transistor includes at least one first conductive gate element arranged in at least one first trench formed in a semiconductor substrate, and at least one first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.

PRIORITY CLAIM

This application claims the priority benefit of French Application for Patent No. 2107602, filed on Jul. 13, 2021, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure generally concerns electronic devices and, more particularly, one-time programmable memories.

BACKGROUND

Certain types of memory devices and particularly one-time programmable memory devices (OTP), operate by associating a transistor with a capacitive element. The memory cell (an oxide forming the dielectric of the capacitive element) has a native state (after manufacturing) with a given resistance which is relatively high defining a first state (arbitrarily 0). During a step of cell programming to a second state (arbitrarily 1), the transistor sends a signal which enables the break down of the oxide, which makes it conductive with a given resistance which is relatively low.

Current OTP memories occupy a surface area of several hundreds of square micrometers on the substrates of electronic chips.

Further, the resistance of the oxide of “broken down” OTP memory cells is difficult to control. This generates a dispersion of resistance values between the different memories of a same batch, which is not satisfactory.

There is a need for an OTP memory enabling to at least partially overcome one or a plurality of disadvantages of existing devices, such as the size of OTP memories and/or the resistance dispersion of the oxide when the latter has broken down.

SUMMARY

An embodiment enables to at last partially decrease the size of OTP memories while using a buried gate transistor. OTP memory cells of small size, for example, having a size smaller than 30 μm2, are thus obtained.

An embodiment enables to at least partially improve the resistance dispersions of the oxide once broken down by focusing the charges originating from the transistor during programming of the second state towards a specific location of the oxide of the capacitive element.

An embodiment provides a one-time programmable memory cell comprising: a transistor comprising: at least a first conductive gate element arranged in at least a first trench formed in a semiconductor substrate; at least a first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the first conductive gate element; and a capacitive element forming a memory element; said first channel portion being coupled to an electrode of the capacitive element.

In an embodiment, the first channel portion is formed according to a first doping type.

In an embodiment, the first channel portion is separated from the first conductive gate element by a first insulator layer.

In an embodiment, the capacitive element comprises: a second insulator layer arranged on a first surface of the substrate; at least one second conductive element formed on the second insulator layer; and an electrode, formed according to the first doping type, in the substrate and in front of at least a portion of the second conductive element, the second insulator layer being at least partly arranged between the electrode and the second conductive element.

In an embodiment, the capacitive element comprises a second portion formed in the substrate, in contact with the second insulator, and arranged between the electrode of the capacitive element and the first channel portion of the transistor, the second portion being formed according to a second doping type with a dopant concentration greater than a dopant concentration of the substrate.

In an embodiment, the transistor comprises at least one channel biasing portion arranged in contact with the first channel portion, the channel biasing portion being formed according to the first doping type with a dopant concentration greater than a dopant concentration of the first channel portion and separated from the first conductive gate element by the first insulator layer.

In an embodiment, the transistor comprises at least one source formed in the substrate and arranged in contact with the first channel portion, the source being formed according to the second doping type and separated from the first conductive gate element by the first insulator layer.

In an embodiment, the memory cell further comprises a third conductive element, electrically insulated from the first conductive gate element and the substrate, and at least partly arranged in said at least one first trench.

In an embodiment, the third conductive element is further arranged in the substrate and surrounds at least an assembly formed by the transistor and the capacitive element.

In an embodiment, the third conductive element is coupled to an electric ground.

In an embodiment, the first conductive gate element is further arranged in at least a second trench formed in the substrate, the first channel portion extending at least between the first trench and the second trench.

In an embodiment, the first channel portion further extends at the level of at least one second lateral surface of the first conductive gate element.

An additional embodiment provides an electronic device comprising: at least such a memory cell; and a control circuit configured to apply a first voltage in the range from 5 to 15 Volts between the first conductive gate element and the source, and to apply a second voltage in the range from 5 to 15 Volts between the first conductive gate element and the channel biasing portion.

In an embodiment, the control circuit is configured to apply a voltage greater than 5 Volts between the second conductive element and the electrode of the capacitive element.

DETAILED DESCRIPTION

For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

FIG.1schematically shows an OTP memory cell.

The OTP memory cell comprises a transistor10and a capacitive element30(forming a memory element) coupled in series between power supply voltage rails. Transistor10is, for example, a MOS transistor comprising a source, a drain, a gate, and a substrate contact. The source of transistor10is, for example, coupled to a first voltage rail, which is, for example, at a reference potential VS, such as the ground. The substrate contact is, for example, also coupled to the source. A substrate potential VBis thus, for example, equal to the ground potential. The transistor drain is, for example, coupled to an intermediate node20between transistor10and capacitive element30, for example delivering an output voltage VOTP_OUTof the OTP. Capacitive element30, for example, comprises a first electrode coupled to intermediate node20and a second electrode coupled to a second voltage rail, which is, for example, at a power supply potential VCAPAof the OTP memory cell.

Before the step of breaking down of the oxide of the capacitive element, the gate, the source, and the channel biasing region of transistor10are, for example, all at the same potential, for example, at 0 Volts, i.e. at ground. In other words, voltages VG, VS, and VBare, for example, equal to 0 Volts with respect to ground. The voltage applied across the capacitive element, that is, between VCAPAand intermediate node20, is, for example, also kept equal to zero.

In an example, to enable to break down the oxide of capacitive element30, voltage VCAPAis taken to a programming value, which is, for example, equal to or greater than 5 Volts, voltage VGis taken to an activation value of transistor10, which is, for example, greater than 5 Volts, and in the range from 5 Volts to 15 Volts, and voltages VSand VBremain, for example, at 0 Volts.

The readout phase, for example, comprises measuring the resistance between terminals VCAPAand VOTP_OUT. If the breakdown step has not occurred, the resistance is higher. If the breakdown step has occurred, the resistance is lower. For example, voltage VCAPAis taken to a readout value, which is for example equal to 2 Volts, and by activating transistor10, the level of voltage VOTP_OUTdepends on the resistance between terminals VCAPAand VOTP_OUT, and thus on the programming state of the OTP cell.

FIG.2is a top view of an embodiment of an OTP memory cell, for example integrating the circuit ofFIG.1.

Transistor10comprises at least one first conductive gate element101. In other words, the first conductive gate element101forms the gate of transistor10. In the example ofFIG.2, the first conductive gate element101is formed in a first trench102and in a second trench107, themselves formed in a semiconductor substrate25. Although first conductive gate element101is formed in the two trenches, in other embodiments, first conductive gate element101is formed in a single trench, such as first trench102or second trench107. The fact of having first conductive gate element101formed in a first trench102and in a second trench107enables to increase the surface area of the channel of transistor10.

In an example, first conductive gate element101has a widthwise dimension, that is, a width taken approximately parallel to a first surface of substrate25, which is smaller than the dimension extending depthwise in the trench. This enables to limit the size of the OTP memory cell and also enables to ease the breakdown of the oxide of capacitive element30by increasing the generated current. The electric contacting on first conductive gate element101occurs at the level of contacts101darranged above the first surface of substrate25through a passivation oxide present at the surface of substrate25. First conductive gate element101is surrounded, in the first and/or in the second trench102,107, by a first insulating layer104to electrically insulate it from the substrate and/or from other conductors. In an example, first insulator layer104has a thickness in the range from 35 to 45 nanometers.

In the present description, the first surface of substrate25similarly designates an external surface of the substrate or the surface of the passivation oxide that may be present at the surface of the substrate, and which is oriented towards substrate25.

In an example, first insulator layer104is formed with a silicon oxide or a silicon nitride.

In an example, first conductive gate element101is formed with polysilicon.

In an example, the length Lg of first conductive gate element101is in the range from 3 to 4 micrometers, this length extending parallel to the first surface of substrate25.

In an example, the width Lrg of first conductive gate element101is in the range from 0.4 to 0.8 micrometers.

In the example ofFIG.2, transistor10further comprises a first channel portion103. In other words, the channel of transistor10is formed by first channel portion103. First channel portion103is buried in substrate25and, for example, extends at the level of at least a first lateral surface101aof first conductive gate element101. Lateral surface101ais, for example, approximately oriented so that a normal to lateral surface101ais parallel to the first surface of substrate25. The term “buried” means that first channel portion103extends depthwise in the substrate. In other words, first channel portion103forms a three-dimensional structure having the approximate shape of a rectangle or of a square having two surfaces parallel to the first surface of the substrate and to a length of first conductive gate element101. The height of this rectangle shape is, for example, equal to a height of first conductive gate element101. In an example, the general shape of first channel portion103is similar to that of first conductive gate element101.

In an example, first channel portion103has a first P doping type with a dopant concentration in the range from 7×1019to 2×1020. cm−3. However, those skilled in the art may modify, based on their knowledge, the different doping types, for example selected according to the doping type of substrate25. Dopants such as aluminum, boron, gallium, or also indium may for example be used as P dopants for a silicon substrate.

In the example ofFIG.2of a structure having two trenches102,107and where first conductive gate element101is arranged in the first and the second trench107, first channel portion103, for example, extends at least between first trench102and second trench107. First channel portion103may further extend, for example, similarly with respect to first surface101a, at the level of at least one second lateral surface101bof the first conductive gate element101. This enables to further increase the channel conduction to ease the step of breakdown of the oxide of capacitive element30.

In an example, substrate25is doped according to a first P doping type. In another example, substrate25is doped according to a second N doping type. In the rest of the description, the case of an N-type substrate is taken as an example. However, those skilled in the art may modify, based on their knowledge, the different doping types according to the selected doping type of substrate25. Substrate25may be formed with silicon, germanium, a carbide such as SiC, a nitride such as GaN, or another semiconductor known by those skilled in the art. Dopants such as phosphorus or antimony may be used for the N doping for silicon.

In the example ofFIG.2, transistor10comprises at least one channel biasing portion106, corresponding to the substrate contact and arranged to be in contact with first channel portion103. One or a plurality of contacts106a arranged at the surface of substrate25enable to bias channel biasing portion106with potential VS/VB(the two contacts being shorted).

A plurality of channel biasing portions106may be formed if the first channel portion103is arranged in a plurality of locations as illustrated in the example ofFIG.2.

In an example, channel biasing portion106is formed according to the first P doping type with a dopant concentration which is, for example, greater than a dopant concentration of first channel portion103.

In an example, channel biasing portion106has a dopant concentration in the range from 1×1017to 5×1017at. cm−3.

In an example, channel biasing portion106is separated from first conductive gate element101by first insulator layer104.

In the example ofFIG.2, transistor10comprises a source108formed in substrate25and arranged in contact with first channel portion103. A plurality of sources108may be formed if first channel portion103is arranged in a plurality of locations as in the example ofFIG.2.

In an example, source108is formed according to the second N doping type. The dopant concentration of the source is, in an example, greater than that of substrate25.

In the example ofFIG.2, source108is separated from first conductive gate element101by first insulator layer104.

In an example, one or a plurality of contacts108a, arranged at the surface of substrate25, enable to apply potential Vs to source108.

In the example ofFIG.2, the different channel biasing portions106of a same transistor10may be connected to one another by a conductive track106c.

In the example ofFIG.2, the different sources108of a same transistor10may be connected together by a conductive track108c.

In the example ofFIG.2, the different first conductive gate elements101of a same transistor10may be connected by a conductive track101c.

In the example ofFIG.2, the OTP memory cell further optionally comprises a third conductive element400. Third conductive element400is electrically insulated from first conductive gate element101and from substrate25. Third conductive element400is, for example, at least partly arranged in first trench102, and in second trench107if the latter is present.

Third conductive element400is, for example, a field plate. It is, for example, made of polysilicon.

In the example ofFIG.2, third conductive element400is arranged at least under first conductive gate element101, that is, at the bottom of trench102,107. In other words, first conductive gate element101is arranged between third conductive element400and the first surface of substrate25. This enables to limit the influence of the high voltages developed by gates101on the rest of substrate25.

In an example, third conductive element400is coupled to an electric ground. This enables to improve the insulation of the OTP memory cell from electric disturbances and/or to insulate the rest of substrate25from the high voltages developed by the components of the OTP memory cell.

In the example ofFIG.2, third conductive element400is further arranged in substrate25to surround at least one assembly formed by the transistor10and the capacitive element30of the OTP memory cell. In an example, in the portion where third conductive element400is not formed in trenches102,107, third conductive element400, for example, extends from the first surface of substrate25down to a depth equivalent to the trench depth.

Contacts400a may be formed on the first surface of substrate25to be able to bias third conductive element400, for example, to ground.

The use of this third conductive element400further enables to limit the size of the OTP memory cells on substrate25. Indeed, the use of insulation trenches coupled to insulation well connections, taking more space, is then avoided.

In the example ofFIG.2, the OTP memory cell further comprises capacitive element30which is used to form the memory element.

First channel portion103is coupled to an electrode of capacitive element30located, for example, in substrate25. In other words, the drain of transistor10is formed by a portion of substrate25located between first channel portion103and the electrode of capacitive element30formed in substrate25. This enables to direct the charges originating from first channel portion103to the oxide of capacitive element30. The term “coupled” here means that first channel portion103can transfer charges and/or an electric potential to the electrode of the capacitive element directly or indirectly via a second optional portion304.

In the example ofFIG.2, capacitive element30comprises a second insulator layer301arranged on the first surface of substrate25. The term “insulating layer” is the synonym of the term oxide. In other words, second insulator layer301is broken down after the programming. The term “on” here means that second insulator layer301, in other words the oxide, may be formed above and in contact with the first surface of substrate25or at the same level as the first surface of substrate25or, for example, under the first surface of the substrate but in contact with the first surface. Second insulator layer301may be formed, in an example, by silicon dioxide. In an example, the thickness of second insulator layer301is in the range from 5 to 10 nanometers, and is for example approximately 6 or 7 nanometers.

Capacitive element30further comprises a second conductive element302formed on second insulator layer301. Second conductive element302forms one of the two electrodes of capacitive element30. Second conductive element302is for example formed with polysilicon. In an example, second conductive element302is formed in relief with respect to substrate25. Contacts302amay be formed to apply to second conductive element302potential VCAPA.

Capacitive element30also comprises an electrode303. This electrode is formed, in an example, according to the first P doping type, in substrate25. In an example, the dopant concentration of this electrode303is greater than the dopant concentration of channel103. For example, the dopant concentration of this electrode303is in the range from 1×1019to 7×1019at. cm−3. In an example, electrode303is formed in front of at least a portion of second conductive element302.

In an example, second insulator layer301, for example, the oxide layer, is at least partly arranged between electrode303and second conductive element302. In the example ofFIG.2, second insulator layer301extends, along the first surface of substrate25in top view, beyond second conductive element302by a distance E in the range from 0.4 to 1 micrometer, and beyond electrode303towards transistor10. This enables to duplicate the contacts used for the reading from the memory cell. In another example, second insulator layer301is limited to the physical extension of second conductive element302along the first surface of substrate25.

Contacts303amay be formed through substrate25and second insulator layer301to detect, on second conductive element303, potential VOTP-OUT.

In the example ofFIG.2, capacitive element30optionally comprises a second portion304formed in substrate25. In an example, second portion304is in contact with second insulator301and also, for example, with electrode303. In an example, second portion304is arranged between the electrode303of capacitive element30and the first channel portion103of transistor10. In the example ofFIG.2, the extension of second portion304is limited, along the first surface of substrate25, to a width Le smaller than the width Lec of second conductive element302. This is advantageous to concentrate the charges originating from first channel portion103and thus enable to accurately and reproducibly obtain the resistance of second insulator layer301after breakdown, at the level of second portion304and/or of the interface between second portion304and conductive element302. Second portion304and conductive element302can thus be seen as one and the same electrode.

To improve the charge concentration at the level of second portion304, the latter is, for example, formed according to the second N doping type with a dopant concentration greater than a dopant concentration of substrate25. In an example, the dopant concentration of second portion304is in the range from 1×1019to 7×1019at. cm−3. Those skilled in the art may modify the doping type or the concentration according to the substrate doping for example or according to the doping of electrode303or to the doping of first channel portion103.

In the example ofFIG.2, second portion304is separated, in substrate25, by a distance S of approximately 0.5 micrometers from first channel portion103. In this example, second portion304may be arranged in front and/or at a similar depth with respect to at least a portion of first channel portion103. This enables to further improve the charge concentration towards second portion304at the time of breaking down oxide301. It is thus possible to accurately control which portion of the oxide has broken down.

FIG.3is a simplified perspective view of an embodiment of an OTP memory cell at the level of area A ofFIG.2, where the substrate is made transparent for a better understanding.

FIG.3enables, among others, to also view the arrangement between gate101and this conductive element400at the level of trenches102.

First conductive gate element101is arranged in an upper portion of first trench102. The edges of first trench102are covered with first insulator layer104. First insulator layer104is also arranged in an upper portion of the trench located to the right of gate101inFIG.3. This enables to insulate gate101particularly from channel biasing portion106and/or from source108.

InFIG.3, it is visible that first channel portion103is arranged along approximately the same depth as first conductive gate element101.

In an example, first channel portion103extends in depth Dc with respect to the first surface of the substrate from 0.5 to 1.5 micrometers.

InFIG.3, it is visible that third conductive element400is arranged in a lower portion, that is, deeper, of first trench102. The depth Dpf of third conductive element400is, for example, in the range from 1.5 to 2.5 micrometers. Third conductive element400is electrically insulated from first conductive gate element101by first insulator layer104which stretches approximately parallel to the first surface of substrate25between first conductive gate element101and third conductive element400. This conductive element400is also insulated from substrate25by first insulator layer104.

In an example, the height, in other words the depth Dg relative to the first surface of substrate25, of first conductive gate element101, is in the range from 0.5 to 1.5 micrometers.

FIG.4is a simplified cross-section view of an embodiment of an OTP memory cell at the level of area B ofFIG.2and seen from the right-hand side in the orientation ofFIG.2.

FIG.4enables to have an example of the arrangement of second insulator layer301with respect to the first surface of substrate25.

First conductive gate element101and third conductive element400are illustrated in dotted lines since they are set back. Second portion304is partly arranged vertically in line with second conductive element302. Second insulator layer301extends beyond second portion304and second conductive element302. In the example ofFIG.4, second portion304is thinner than electrode303and is in contact with second insulator layer301. A thickness ECof second portion304is, for example, in the range from 100 to 500 nanometers.

In the example ofFIG.4, a portion of second insulator layer301, located at the far right in the drawing, may, for example, be thicker and deeper in substrate25with respect to its thickness at the level of second portion304. This enables to electrically insulate the memory cell.

In the example ofFIG.4, first channel portion103is separated from second portion304by a portion of substrate25.

When the voltage VGapplied to gate101is for example greater than 5 Volts and voltages VSand VBare, for example, kept equal to zero and the voltage VCAPAof external electrode302is for example greater than 5 Volts, a significant number of electric charges is generated in first channel portion103all along the height of first channel portion103which extends in front of first conductive gate element101. These charges are then concentrated, as shown by the arrows inFIG.4, on second portion304, which has decreased dimensions with respect to second insulating layer301and with respect to second conductive element302which forms the external electrode of capacitive element30. These decreased dimensions and/or the higher dopant concentration at the level of second portion304, with respect to the dopant concentration of substrate25, enable to accurately locate the charges and control the area where oxide301will break down. The resulting resistance dispersion is thus limited.

The number of charges is proportional to the surface developed by all the vertical surfaces of first channel portion103which are in front of first conductive gate element101. This charge generation surface being vertical, conversely to a transistor where the channel is only formed at the surface, this enables to significantly decrease the bulk of the OTP memory cell.

In the example ofFIG.4, the capacitive element further comprises a portion303bdoped according to the first P doping type, arranged in contact with electrode303and formed in substrate25under electrode303. This portion303benables to electrically insulate the cell due to a well and to read the state of each of the memory cells.

FIG.5illustrates, in top view, an electronic device500comprising four OTP memory cells such as described in the previous examples. Other examples of electronic devices500, not illustrated, may comprise from one to several hundreds of OTP memory cells such as described in the previous examples.

In the example ofFIG.5, the OTP memory cells are each surrounded with third conductive element400. This enables to insulate the OTP memory cells from one another and from possible external disturbances. Between two adjacent memory cells, a single third conductive element400is present. In other words, a single third conductive element400is common for two adjacent OTP memory cells. This enables to limit the size of OTP memory cells on substrate25. Such electronic devices500have a small size and controlled oxide resistances.

Electronic device500, for example, further comprises a control circuit CTRL configured to apply, during an operation of programming of one or a plurality of OTP memory cells, corresponding gate voltages, according to the value of the data bit to be stored in each cell. In the example ofFIG.5, four gate voltages VG1, VG2, VG3and VG4are generated by circuit CTRL to respectively control the four OTP cells. In certain cases, circuit CTRL is also configured to generate voltage VCAPA, which is for example a voltage common to all cells, and/or to receive the output voltages VOTP_OUT1, VOTP_OUT2, VOTP_OUT3, and VOTP_OUT4of one or a plurality of the OTP memory cells during a readout phase.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art.

Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove. In particular, the indicated doping types may be interchanged and adapted by those skilled in the art.