CCIe receiver logic register write only with receiver clock

Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.

FIELD

The present disclosure pertains to enabling efficient operations over a shared bus and, more particularly, simplifying transmission and/or reception over the shared bus by embedding a clock within transcoded transmissions.

BACKGROUND

I2C (also referred to as I2C) is a multi-master serial single-ended bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic devices. The I2C bus includes a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for devices: master and slave. A master device is a node that generates the clock and initiates communication with slave devices. A slave device is a node that receives the clock and responds when addressed by the master device. The I2C bus is a multi-master bus which means any number of master devices can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). I2C defines basic types of messages, each of which begins with a START and ends with a STOP.

In this context of a camera implementation, unidirectional transmissions may be used to capture an image from a sensor and transmit such image data to memory in a baseband processor, while control data may be exchanged between the baseband processor and the sensor as well as other peripheral devices. In one example, a Camera Control Interface (CCI) protocol may be used for such control data between the baseband processor and the image sensor (and/or one or more slave devices). In one example, the CCI protocol may be implemented over an I2C serial bus between the image sensor and the baseband processor.

An extension to CCI called CCIe (Camera Control Interface extended) has been developed that encodes information for transmission over the shared bus. CCIe does not implement a separate clock line on the shared bus. Instead, it embeds a clock within the transmitted transcoded information. However, such embedded clock may serve for reception of data and/or synchronization purposes, it may be insufficient to permit saving such data into registers.

Additionally, a mechanism is needed to allow slave devices to go into a power saving or sleep mode but also allow a master device to write data to the slave device. This may be done by having the master device track slave devices that are in sleep mode, but such mechanism adds unwanted overhead.

Therefore, a solution is needed that efficiently uses a recovered clock embedded within a transmission to allow writing data into registers of a slave device without a free-running clock while facilitating an efficient sleep and wakeup mechanism for slave devices.

SUMMARY

In an aspect of the disclosure, a method, a computer program product, and an apparatus are provided that provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices.

In certain aspects, a method performed by a receiver device includes receiving a plurality of symbols over a shared bus, extracting a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, converting the plurality of symbols into a transition number, converting the transition number into data bits, and storing at least a portion of the data bits into one or more registers using only the clock signal.

In one aspect, the symbols transition every clock cycle such that no two sequential symbols have the same value.

In one aspect, the receiver device independently enters a sleep mode without notifying any other devices coupled to the shared bus.

In one aspect, the receiver device receives and writes at least a portion of the data bits to the one or more registers without use of a local free-running clock. The receiver device may receive and write at least a portion of the data bits to the one or more registers while the receiver is in a sleep mode.

In one aspect, the transition number may be expressed as a ternary number. In one example, the transition number may be a twelve digit ternary number.

In one aspect, the shared bus is a camera control interface extended (CCIe) bus.

In one aspect, at least a portion of the data bits is written into the one or more registers by starting a down counter upon detection of a first cycle of the clock signal, triggering a marker when the down counter reaches a pre-defined value, and using the marker to store at least a portion of the data bits into registers. The pre-defined value may occur when a final clock cycle of the clock signal is reached.

In one aspect, the transition number is converted into the data bits between a penultimate clock cycle and a last clock cycle of the clock signal, and at least a portion of the data bits is stored into registers at a last clock cycle of the clock signal.

In certain aspects, a receiver device includes a bus interface adapted to couple the receiver device to a shared bus to receive a plurality of symbols, one or more registers, and a receiver circuit coupled to the bus interface. The receiver circuit may be configured to extract a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into a data bits, and store at least a portion of the data bits into the one or more registers using only the clock signal.

In certain aspects, a receiver device includes means for receiving a plurality of symbols over a shared bus, means for extracting a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, means for converting the plurality of symbols into a transition number, means for converting the transition number into a data bits, and means for storing at least a portion of the data bits into registers using only the clock signal.

In certain aspects, a machine-readable storage medium has instructions stored thereon. The storage medium may include a transitory and/or a non-transitory storage medium. The instructions may be executed by at least one processor, and the instructions may cause the at least one processor to receive a plurality of symbols over a shared bus, extract a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into a data bits, and store at least a portion of the data bits into registers using only the clock signal.

DETAILED DESCRIPTION

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific detail. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the embodiments.

Overview

A first feature provides a way of converting data bits into a ternary number. The ternary number is then converted into a plurality of symbols by sending a most significant digit of the ternary number to a transcoder first. The plurality of symbols is then transmitted over a bus. For example, the plurality of symbols may be transmitted over a camera control interface extended (CCIe) bus.

A second feature provides for a receiver device that is configured to extract the embedded clock from a received transmission and store data therein into registers solely using the embedded clock (without a free running clock or using padded filler transmissions to generate an extra clock cycle). Therefore, the receiver device can receive and store information even when the receiver device is in a sleep mode (when no free-running clock is available).

Exemplary Method for Simplifying Symbol Coding and Transmission Over CCIe Bus

FIG. 1is a block diagram illustrating a device102having a baseband processor104and an image sensor106and implementing an image data bus116and a multi-mode control data bus108. WhileFIG. 1illustrates the multi-mode control data bus108within a camera device, it should be clear that this control data bus108may be implemented in various different devices and/or systems. Image data may be sent from the image sensor106to the baseband processor104over an image data bus116(e.g., a high speed differential DPHY link). In one example, the control data bus108may be an I2C bus comprising two wires, a clock line (SCL) and a serial data line (SDA). The clock line SCL may be used to synchronize all data transfers over the I2C bus (control data bus108). The data line SDA and clock line SCL are coupled to all devices112,114, and118on the I2C bus (control data bus108). In this example, control data may be exchanged between the baseband processor104and the image sensor106as well as other peripheral devices118via the control data bus108. The standard clock (SCL) speed for I2C is up to 100 KHz. The standard clock SCL speed in I2C fast mode is up to 400 KHz, and in I2C fast mode plus (Fm+) it is up to 1 MHz. These operating modes over an I2C bus may be referred to as a camera control interface (CCI) mode when used for camera applications.

According to one aspect, an improved mode of operation (i.e., greater than 1 MHz) may be implemented over the multi-mode control data bus108to support camera operation. This improved mode of operation over an I2C bus may be referred to as a camera control interface extension (CCIe) mode when used for camera applications. In this example, the baseband processor104includes a master device/node112and the image sensor106includes a slave device/node114, both the master device/node112and slave device/node114may operate according to the camera control interface extension (CCIe) mode over the control data bus108without affecting the proper operation of other legacy I2C devices coupled to the control data bus108. According to one aspect, this improved mode over the control data bus108may be implemented without any bridge device between CCIe devices and legacy I2C slaves devices.

FIG. 2illustrates how a clock may be embedded within data symbols, thereby allowing the use of both I2C wires (i.e., SDA line and SCL line) for data transmissions. In one example, the clock may be embedded through the use of transition clock transcoding. Transition clock transcoding may involve transcoding original data into symbol data such that there is a transition in the signaling state of a communication link between consecutive symbols (i.e. the symbol value transitions at every symbol cycle). That is to say, the data204to be transmitted over the physical link (wires) may be transcoded such that signaling state of the physical link changes at every symbol cycle of the transmitted symbols206. Consequently, the original clock202is embedded in the change of symbol states at every symbol cycle.

A receiver recovers clock information208from the state transition at each symbol (in the transmitted symbols206) and then reverses the transcoding of the transmitted symbols206to obtain the original data210. This allows both wires of the I2C bus (control data bus108inFIG. 1, SDA line and SCL line) to be used to send data information. Additionally, the symbol rate can be doubled since it is no longer necessary to have a setup and hold time between clock and data signals.

FIG. 3is a block diagram illustrating one example of a method for transcoding of data bits into transcoded symbols at a transmitter to embed a clock signal within the transcoded symbols. At the transmitter300, input data bits304are converted into a multi-digit ternary (base 3) number, where each digit may be referred to as a “transition number.” The ternary number is then converted into a set of (sequential) symbols which are transmitted over the clock line SCL312and the data line SDA314of a physical link302. In one example, an original 20-bits of binary data is input to a bit-to-transition number converter block308to be converted to a 12-digits ternary number. Each digit of a 12-digits ternary number represents a “transition number.” Two consecutive transition numbers may have the same value. Each transition number is converted into a sequential symbol at a transition-to-symbol block310such that no two consecutive sequential symbols have the same value. Because a transition in symbol value (and signaling state of the wires312,314) is guaranteed between the symbols in every pair of sequential symbols, the sequential symbol transition may serve to embed a clock signal. Each sequential symbol316is then sent over a two wire physical link302which may include an I2C bus having a SCL line312and a SDA line314.

FIG. 4illustrates an example of the conversion from bits to transition numbers at a transmitter400, and then from transition numbers to bits at a receiver420. This example illustrates the transmission for a 2-wire system using 12 transition symbols. The transmitter400feeds binary information, Bits, into a “Bits to 12×T” converter406to generate 12 symbol transition numbers, T11to T0. The receiver420receives 12 symbols transition numbers, T11to T0, which are fed into a “12×T to Bits” converter408to retrieve the binary information (Bits). When there are r possible symbol transition states for each transition (T0-T11), 12 transitions can send r12different states. For a 2-wire bus, r=22−1. Consequently, transitions T0. . . T11contain data that can have (22−1)12different states. Consequently, r=4−1=3 and the number of states=(4−1)^12=531441.

In this manner, 12 transitions numbers may be converted into a number. Note that the ternary number 2100_1101_01213may be used as the transition number, for example, inFIG. 3, so that each integer may be mapped to a sequential symbol and vice versa. When sending 2100_1101_01213in inverse order, the transition numbers are sent in decreasing order of power, i.e., T11is the digit to be multiplied by 311so it is of the eleventh power and so forth.

The example illustrated inFIG. 4for a 2-wire system and 12 symbol transition numbers may be generalized to an n-wire system and m symbol transition numbers. If there are r possible symbol transition states per one T, T0to Tm-1, m transitions can send rmdifferent states, i.e., r=2n−1. Consequently, transitions T0. . . Tm-1contain data that can have (2n−1)mdifferent states.

FIG. 5is a diagram500illustrating one example of a scheme for converting between ternary numbers (transition number)502and (sequential) symbols504. A ternary number, base-3 number, also referred to as a transition number, can have one of the 3 possible digits or states, 0, 1, or 2. While the same value may appear in two consecutive ternary numbers, no two consecutive symbols have the same value.

The conversion function is set forth illustratively inFIG. 6. On the transmission side (TX: T to S) the logic is Ttmp=T=0 ? 3: T and Cs=Ps+Ttmp. In other words, the transition number T is compared to zero and when T=zero, Ttmp(T temporary) becomes equal to 3, else (when T not equal zero) Ttmpbecomes equal to T. And the current symbol (Cs) becomes the previous symbol (Ps) value plus Ttmp. For example, in a first cycle506, the T is 2, so Ttmpis also 2, and with Psbeing 1, the new Csis now 3.

In a second cycle508, the transition number 1 is input in the next cycle, and the transition number is not 3, so T's value of 1 is added to the previous symbol's value of 3. Since the result of the addition, 4, is larger than 3, the rolled over number 0 becomes the current symbol.

In a third cycle510, the same transition number 1 is input. Because T is 1 Ttmpis also 1. The conversion logic adds 1 to the previous symbol 0 to generate current symbol 1.

In a fourth cycle512, the transition number 0 is input. The conversion logic makes Ttmpequal to 3, when T is zero. So 3 is added to the previous symbol 1 to generate current symbol 0 (since the result of the addition, 4, is larger than 3, the rolled over number 0 becomes the current symbol).

Consequently, even if two consecutive ternary digits502have the same numbers, this conversion guarantees that two consecutive symbol numbers have different state values. Because of this, the guaranteed symbol transition in the sequence of symbols504may serve to embed a clock signal, thereby freeing the clock line SCL in an I2C bus for data transmissions. On the receiver side (RX: S to T) the logic is reversed: Ttmp=Cs+4−Psand T=Ttmp=3 ? 0: Ttmp.

Referring again toFIG. 3, at the receiver320the process is reversed to convert the transcoded symbols back to bits and, in the process, a clock signal is extracted from the symbol transition. The receiver320receives a sequence of sequential symbols322over the two wire physical link302, which may be an I2C bus connected to an SCL line input324and a SDA line input326. The received sequential symbols322are input into a clock-data recovery (CDR) block328to recover a clock timing and sample the transcoded symbols (S). The CDR328may recover a clock signal336from the symbol-to-symbol transitions in the received symbols. This recovered clock signal336may serve to enable the operation of receiver components and writing of extracted bits without the need for a separate clock. A symbol-to-transition number converter block330then converts each symbol to a transition number that may be expressed as a single digit ternary number representative of the difference between a current symbol and immediately preceding symbol. Then, a transition number-to-bits converter332converts 12 transition numbers to restore 20 bits304′ of original data from the 12 digit ternary number.

This technique illustrated herein may be used to increase the link rate of a control bus108(FIG. 1) beyond what the I2C standard bus provides and is referred hereto as CCIe mode. In one example, a master node and/or a slave node coupled to the control data bus108may implement transmitters and/or receivers that embed a clock signal within symbol transmissions (as illustrated inFIGS. 2 and 3) in order to achieve higher bit rates over the same control data bus than is possible using a standard I2C bus. Note that, in other implementations, a different number of data bits may be encoded into the ternary number (base-3 number system) or a number having a different numerical base.

FIG. 6is a diagram that illustrates the conversion between sequential symbols and transition numbers. This conversion maps each transition from a previous sequential symbol number (Ps) to a current sequential symbol (Cs) to a transition number (T). At the transmitter device, the transition numbers are being converted to sequential symbols. Because of the relative conversion scheme being used, the transition numbers guarantee that no two consecutive sequential symbols604will be the same.

In one example for a 2-wire system, there are 4 raw symbols assigned to 4 sequential symbols S0, S1, S2, and S3. For the 4 sequential symbols, Table602illustrates how a current sequential symbol (Cs) may be assigned based on a previous sequential symbol (Ps) and a temporary transition number Ttmpbased upon the current transition number (T).

In this example, the transition number Csmay be assigned according to:
Cs=Ps+Ttmp

Alternatively stated, if T is equal to zero, Ttmpbecomes 3, else Ttmpbecomes equal to T. And once Ttmpis calculated, Cs is set to Ps plus Ttmp. Moreover, on the receiver end, the logic is reversed to recover T,
Ttmp=Cs+4−PsandT=Ttmp−3?0:Ttmp.

FIG. 16includes an equation1600that illustrates a general example of converting a ternary number (base-3 number) to a binary number, where each T in {T11, T10, . . . T2, T1, T0} is a symbol transition number.

FIG. 17includes an equation1700that illustrates an exemplary method for converting a binary number (bits) to a 12 digit ternary number (base-3 number). Each digit can be calculated by dividing the remainder (result of a modulo operation) from a higher digit calculation with 3 to the power of the digit number, discarding decimal points numbers.

FIG. 18is a mathematical representation1800that illustrates an example of one possible implementation of the division and the module operations of theFIG. 17, which may be synthesizable by any commercial synthesis tools.

Extracting Data Using an Embedded Receive Clock

FIG. 7is a block schematic diagram that illustrates an example of a receiver700, which may be comparable to the receiver320ofFIG. 3. The receiver700may be configured to extract data724from a sequence of symbols702received from a shared bus that includes signal wires704,706, which may correspond to lines324and326inFIG. 3. A CDR circuit708may provide sampled symbols720and a receive clock716derived from timing information provided in a multi-bit signal718representative of the sequence of symbols702. The receive clock716may also be used provide timing information to decoding logic710,712that extracts data from the sequence of symbols702.

In some instances, a problem may exist when the receive clock716is used to write the extracted data724into the registers714using only the clock cycles derived from the transitions between symbols in the sequence of symbols702. The receive clock716extracted from symbol-to-symbol transitions within the received transmission702may not provide enough clock cycles to decode the data724and store the data724in the registers714. An extra clock cycle may be needed after the final symbol-to-symbol transition to write the extracted bits into the registers714for storage. In some instances, a free-running clock may be used to provide sufficient clock cycles. The use of a free-running clock may be undesirable because the presence of such free-running clock may require that the master device needs to ensure that the slave device is awake prior to transmission. Under certain conditions, including the conditions discussed in relation toFIG. 8, the extracted clock may be insufficient to extract data from the sequence of symbols702and write the data to the registers714.

FIG. 8is a timing diagram800illustrating the timing of associated with extracting data encoded within symbols, and the recovery of a clock from the symbol transitions. Preceded by a start indicator (S)802, a sequence of symbols702is transmitted through a two-line bus704and706. The relationship between the SI signal718, which may be representative of a sequence of symbols702and corresponding transitions722between symbols is illustrated in the diagram800. A receiver clock (RXCLK)716is extracted from the symbol-to-symbol transitions722. An initial clock pulse806corresponds to the start indicator (S)802, which may also be referred to as a “Start Condition.” A plurality of pulses C1, C2, . . . , C12 on the RXCLK716may be extracted from the transitions (T11, T10, T9. . . T0)722between consecutive symbols S11, S10, S9, . . . , S0718, since no two same sequential symbols repeat. The plurality of pulses may be considered to commence with a first pulse (C1)808that corresponds to the first transition between encoded symbols.

After a penultimate clock cycle (C11)810, and before the last clock cycle (C12)812corresponding to a transition between encoded symbols, a final or last symbol (S0)804is received and combined with the remaining symbols S11. . . S1such that 20 raw data bits816may be produced after the last clock cycle (C12)812occurs. Note that, it is only after reception of the last symbol (e.g., twelfth symbol S0) that the original bits can be decoded to obtain the raw data bits816. A last clock cycle814is to store the raw data bits816, or a portion thereof, into the registers714.

In one example, the number of symbols received is twelve. The twelve symbols may encode twenty bits of information (e.g., including sixteen (16) data bits and four (4) control bits). In other examples, different number of symbols may be used to encode different number of bits.

FIG. 9is a drawing900that illustrates different recovered clock conditions that correspond to differing signaling states of the two lines704and706of the serial bus. Four different cases912,914,916,918are presented. In each of the four cases912,914,916,918, a final symbol (S0) is received on the last clock (twelfth) clock pulse902. The four cases912,914,916,918cover the four possible values of the final symbol. In the fourth case918, the signaling state of the two lines704and706corresponding to the final symbol is identical to the signaling state of the two lines704and706during a terminating setup condition. Accordingly, not transition is observed on the signaling state of the two lines704and706after the symbol period during which the final symbol is transmitted. A thirteenth clock pulse904is generated in first three cases912,914,916and may be used to write received data into registers. A thirteenth clock pulse is absent in the fourth case918, and the receiver may be prevented from reliably writing the received data into the registers if the receiver relied on the availability of the thirteenth clock pulse904.

Generating a Guaranteed Register Write Signal

According to certain aspects disclosed herein, and as illustrated byFIGS. 10-12, a word marker may be generated to enable data decoded from a sequence of symbols to be reliably written to registers in a CCIe receiver.FIG. 10is a block schematic diagram that illustrates an example of a receiver1000, which may be adapted using circuits1100,1110, and/or1130ofFIG. 11to decode data from the SI signal1020. A timing diagram1200provided inFIG. 12illustrates the operation of the receiver1000and circuits1100,1110,1130. The SI signal1020may be processed by a combination of the S-to-T decoder1010, the T-to-Bits decoder1012and, in some instances, a register data decoder1114before the sampling edge of the RXCLK1016occurs. Accordingly, an addressed register1113performs the sampling related to the signals received from the serial bus, and the sampling is performed on decoded data.

The receiver1000may be configured to extract data from a sequence of symbols1002received from a shared bus that includes signal wires1004,1006, which may correspond to lines324and326inFIG. 3. The data may be written to registers1014using a receive clock1016recovered from the received data by a CDR circuit1008. A free-running clock is not required. The receive clock (RXCLK)1016may also be used provide timing information to decoding logic1010,1012that extracts data from the sequence of symbols1002. In this circuit, the symbols-to-transition number convertor1010receives and processes the SI signal1020.

The receiver1000may employ one or more counters to maintain an index to transition number position (DNCNT)1123and to produce a word marker that consistently permits writing received data1024to the registers1014, including in the fourth case918illustrated inFIG. 9. A register write operation may be performed on the last recovered clock RXCLK1016cycle without the need for a free-running clock or other additional clock on a slave device, and without the need to insert unused/padding bits solely for the purpose of making an extra clock cycle available

With continued reference toFIG. 10, certain circuits1100,1110,1130illustrated inFIG. 11may be adapted or configured to convert a twelve digit ternary number into bits, and to perform a register write operation of extracted bits using only a clock1016recovered from the transmission corresponding to the ternary number. Referring back toFIG. 3, original data of twenty bits (i.e., data bits304) is converted into a ternary transition number, then this transition number is converted (i.e., transcoded) to twelve sequential symbols316. The transcoded symbols316are transmitted on the bus302. A receiving device320(e.g., a slave device) receives the transcoded symbols316and performs clock recovery and symbol sampling to convert the transcoded symbols316back to a ternary number which is then supplied to one or more circuits such as the converter circuit332, which converts the ternary number back to the original twenty bit binary data.

A first circuit1100may be adapted to extract twenty (20) raw bits1108from twelve (12) transition numbers. Ternary weights1102are selected using DNCNT1123, to control the multiplexer1104, where DNCNT1123represents transition number position. The twelve transition numbers may be processed in an order determined based on their corresponding position in a sequence of transition numbers (e.g. in a sequence related to time of arrival), which may be indicated by the value of DNCNT1123, which may be provided by a counter, register, or other index circuitry. The ternary weights1102are provided as inputs to a single output multiplexer1104that is used to serialize the ternary weights1102such that the twenty raw bits1108can be extracted. The twenty raw bits1108may include sixteen (16) data bits and four (4) control bits. A second multiplexer1106functions as a multiplier for a Ti×3ioperation and is triggered and/or controlled by a signal1022representative of the 2-bit output from the symbol-to-ternary block1010ofFIG. 10. A first flip-flop1125, triggered by RXCLK1016, is used to accumulate the transitory bits as the ternary number is decoded or converted from the ternary weights1102to the raw bits1108. Note that the occurrence of the last symbol (S0)1221(seeFIG. 12), which is received after the penultimate clock pulse (C11)1217, triggers the first flip flop1125to output the collected transitory bits to be added to the bits from the last ternary weight1103output by a second multiplexer1106. Consequently, the raw bits1108(e.g., data1024inFIG. 10) hold valid value and are available after the last symbol S01221is input after the penultimate clock cycle (C11)1217but before the last clock cycle (C12)1219.

A second circuit1110may serve to obtain a word marker1122when all symbols are received. Upon detecting a start indicator1118of the receiver clock1120, the value (DNCNT)1123of a down counter decreases with each pulse on the RXCLK1016from 0xB hex to zero (0x0 hex) at the penultimate clock (C11)1217, and then to 0xF hex at the last clock (C12)1219. A pulse1215on the word marker1122is triggered when the down counter reaches 0x0 hex. The word marker1122serves as input to a third circuit1130to enable writing data bits into registers. Note that DNCNT1123also serves to select an input signal from the multiplexer1104, starting with input “B” (first ternary weight1105) and counting down to input “0” (last ternary weight1103).

The third circuit1130illustrates an example of a circuit configured to write the decoded bits into a second flip-flop or registers1113. An address decoder1112receives seventeen (17) bits of address information and decodes it. Similarly, a data decoder1114receives the twenty (20) raw bits1108and decodes them to obtain, for example, sixteen (16) data bits after four control bits have been removed. When the pulse1215of the word marker1122is triggered and the address is decoded, the decoded data provided by the data decoder1114may be stored in the flip-flops or register1113. This third circuit1130effectively uses the word marker1122to trigger a write to the second flip-flop or registers1113on the last clock cycle (C12)1219.

On the penultimate clock cycle (C11)1217, DNCNT1123has been decremented from 0xB hex to 0x0 hex, and the word marker1122transitions from logic low to logic high (i.e., the start of the pulse1215). At the last clock cycle (C12)1219, the second flip flop or register1113is enabled and stores the 16-bit bus now carrying the decoded data bits.

This approach permits storing the received data bits into flip-flops or registers1113without a running clock on the slave device. Consequently, the slave device can go into a sleep mode without notifying the master device. That is, no separate mechanism is needed for a master device to be informed when a slave device goes into a sleep mode (e.g., no “slave sleep request” is necessary from a slave device). Because the embedded clock allows the slave device to receive the transmitted bits and the third circuit1130generates an additional clock without the need for the slave device to be awake, a master device can write data to a slave device register even when the slave device is asleep or in a sleep mode (e.g., without the need for a free-running clock). In some implementations, the slave device may use the written register data to conditionally wake up part or all its functionality. Therefore, the master device does not have to know whether the slave device is awake or sleeping before sending or writing data to the slave device. Additionally, the slave device may independently enter into a sleep mode without notifying the master device.

The timing diagram1200ofFIG. 12illustrates the reception of data encoded within symbols, the recovery of a clock from the symbol transitions, as well as a timing of generated signals used to complete a write operation of the received data to registers using only the recovered clock. Preceded by a start indicator (S)1206, a sequence of symbols in the SI signal1020is transmitted through a two-line bus1004,1006. The sequence of symbols1020and corresponding transitions between symbols is illustrated. A receiver clock1016is extracted from the symbol-to-symbol transitions in the signal1022representative of the 2-bit output from the symbol-to-ternary block1010ofFIG. 10. An initial clock pulse1211corresponds to the start indicator or start condition, such as the start condition described in the I2C Specification. A plurality of clock pulses C1, C2, . . . , C12 may be extracted from the transitions (T11, T10, T9. . . T0) between consecutive symbols S11, S10, S9, . . . , S0since no two same sequential symbols repeat.

In this example, DNCNT1123is used for counting down twelve (12) cycles, each corresponding to a cycle from a low-to-high transition to a low-to-high transition of the receiver clock RXCLK1016. DNCNT1123is decremented after the first clock cycle1213is detected, and until a last cycle1219is detected. When the DNCNT1123reaches 0x0 hex, a pulse1215is triggered on the word marker1122.

After a penultimate clock cycle (C11)1217and before the last clock cycle (C12)1219, a final or last symbol (S0)1221is received and combined with the remaining symbols S11. . . S1so that the raw data bits1108are available when the last clock cycle C121219occurs. Note that, it is after reception of the last symbol (e.g., twelfth symbol S0) that the original bits can be decoded to obtain the raw data bits1108. A last clock cycle1219is then used to store the raw data bits1108, or a portion thereof, into the registers1113. This allows receiving, decoding, and storing the data1222solely using the embedded clock (e.g., clock recovered from symbol-to-symbol transitions) and without use of an external or free-running clock at the receiver (slave) device. Note that this is achieved without the need to pad or insert extra symbols or bits. In one example, the number of symbols received is twelve. The twelve symbols may encode twenty bits of information (e.g., including sixteen (16) data bits and four (4) control bits). In other examples, different number of symbols may be used to encode different number of bits.

FIG. 13is a block diagram1300that illustrates an example of a CCIe slave device1302that may be configured to receive a transmission from a shared bus by using a clock extracted from the received transmission and writing data from the transmission without the need for the slave device to be awake. The slave device1302includes a receiver circuit1308and a transmitter circuit1310coupled to a shared bus1304and1306. A control logic1314may serve to selectively activate/deactivate the receiver circuit1308and/or transmitter circuit1310so that the slave device receives or transmits over the shared bus1304and1306. The slave device1302may also include a sensor device that captures or collects information for transmission from the slave device.

The receiver circuit1308may include a clock data recovery circuit1312may extract a receiver clock (RXCLK) from symbol-to-symbol transitions according to certain aspects disclosed herein. The receiver circuit1308may also include one or more of the first circuit1100, second circuit1110, and/or third circuit1130(FIG. 11) to decode and extract data received over the shared bus and store such data in registers1318using only the extracted clock from the received data transmission and without introducing delays of the extracted clock. Note that the first circuit1100, second circuit1110, and/or third circuit1130(FIG. 11) may be integrated into one circuit or distributed among different modules or sub-systems.

A clock generator1320may be present within the slave device1302, but it is used only for transmission of data from the slave device and/or other slave device operation, e.g. motion detection or temperature measurement by sensor devices.

FIG. 14illustrates an example of a CDR circuit1400according to one or more aspects disclosed herein andFIG. 15shows an example of timing of certain signals generated by the CDR circuit1400. The CDR circuit1400may be used in a CCIe transmission scheme where clock information is embedded in transmitted sequences of symbols. The CDR circuit1400may be used as the CDR328(FIG. 3) or CDR1312(FIG. 13). The CDR circuit1400includes analog delay elements1408a,1412and1426, which are configured to maximize set up time for symbols1510,1512received from a CCIe two-line bus324&326. The CDR circuit1400includes a comparator1404, a set-reset latch1406, a one-shot element1408including first delay element1408a, a second analog delay element1412, a third analog delay element1426and a level latch1410. The comparator1404may compare an input signal (SI)1420that includes a stream of symbols1510and1512with a signal (S)1422that is a level-latched instance of the SI signal1420. The comparator outputs a comparison signal (NE)1414. The set-reset latch1406receives the NE comparison signal1414from the comparator1404and outputs a filtered version of the comparison signal (NEFLT)1416. The first analog delay device1408amay receive the filtered version of the NEFLT signal1416and outputs a signal (NEDEL signal)1428that is a delayed instance of the NEFLT signal1416. In operation, the one-shot logic1408receives the NEFLT signal1416and the delayed NEDEL signal1428and outputs a signal (NE1SHOT)1424that includes a pulse1506that is triggered by the NEFLT signal1416.

The second analog delay device1412receives the NE1SHOT signal1424and outputs the IRXCLK signal1418, where the IRXCLK signal1418may be used to generate an output clock signal1430using the third analog delay element1426. The output clock signal1430may be used for decoding the latched symbols in the S signal1422. The set-reset latch1406may be reset based on the state of the IRXCLK signal1418. The level latch1410receives the SI signal1420and outputs the level-latched S signal1422, where the level latch1410is enabled by the IRXCLK signal1418.

When a first symbol value S11510is being received, it causes the SI signal1420to commence changing its state. The state of the SI signal1420may be different from the state associated with the S1symbol1510due to the possibility that intermediate or indeterminate states may occur at the signal transition from the previous symbol S01502to the first symbol S11510due to inter-wire skew, signal overshoot, signal undershoot, crosstalk, and so on. The NE signal1414transitions high when the comparator1404detects different value between the SI signal1420and the S signal1422, causing the set-reset latch1406to be asynchronously set. Accordingly, the NEFLT signal1416transitions high, and this high state is maintained until the set-reset latch1406is reset when IRXCLK1418becomes high. The IRXCLK1418transitions to a high state in delayed response to the rising of the NEFLT signal1416, where the delay is attributable in part to the analog delay element1412.

The intermediate states on the SI signal1420may be regarded as invalid data and may include a short period of symbol value of the symbol S01502, and these intermediate states may cause spikes or transitions1538in the NE signal1414as the output of the comparator1404returns towards a low state for short periods of time. The spikes1538do not affect NEFLT signal1416output by the set-reset latch1406, because the set-reset latch1406effectively blocks and/or filters out the spikes1538on the NE signal1414before outputting the NEFLT signal1416.

The one-shot circuit1408outputs a high state in the NE1SHOT signal1424after the rising edge of the NEFLT signal1416. The one-shot circuit1408maintains the NE1SHOT signal1424at a high state for the delay P period1516before the NE1SHOT signal1424returns to the low state. The resultant pulse1506on the NE1SHOT signal1424propagates to the IRXCLK signal1418after the delay S period1518caused by the analog delay S element1412. The high state of the IRXCLK signal1418resets the set-reset latch1406, and the NEFLT signal1416transitions low. The high state of IRXCLK signal1418also enables the level latch1410and the value of the SI signal1420is output as the S signal1422.

The comparator1404detects when the S signal1422corresponding to the S1symbol1510matches the symbol S1symbol1510of the SI signal1420, and the output of the comparator1404drives the NE signal1414low. The trailing edge of the pulse1540on the NE1SHOT signal1424propagates to the IRXCLK signal1418after the delay S period1518caused by the analog delay S element1412. When a new symbol S21512is being received, the SI signal1420begins its transition to the value corresponding to the symbol S21512after the trailing edge of the IRXCLK signal1418.

In one example, the output clock signal RXCLK1430is delayed by a Delay R period1520by the third analog delay element1426. The output clock signal1430and the S signal1422(data) may be provided to the decoding circuits1100,1110, and/or1130(FIG. 11). The decoding circuits1100,1110, and/or1130(FIG. 11) may sample the symbols on the S signal1422using the output clock signal1430or a derivative signal thereof.

In the example depicted, various delays1522a-1522dmay be attributable to switching times of various circuits and/or rise times attributable to connectors. In order to provide adequate setup times for symbol capture by a decoding circuit, the timing constraint for the symbol cycle period tSYMmay be defined as follows:
tdNE+tdNEFLT+td1S+DelayS+DelayP+max(tHD,tREC−tdNE)<tSYM
and the timing constraint for the setup time tsumay be as follows:
Max skew spec+tSU<tdNE+td1S+DelayS

where:tsym: one symbol cycle period,tSU: setup time of SI1420for the level latches1410referenced to the rising (leading) edge of IRXCLK1418,tHD: hold time of SI1420for the level latches1410referenced to the falling (trailing) edge of IRXCLK1418,tdNE: propagation delay of the comparator1404,tdRST: reset time of the set-reset latch1406from the rising (leading) edge of IRXCLK1418.

The CDR circuit1400employs analog delay circuits1408a,1412and1426to ensure that a receiver device (e.g., slave device1302) may decode CCIe encoded symbols and store the resulting bits into registers without using a free-running system clock. Accordingly, a CCIe slave device1302(seeFIG. 13) may be adapted to use a transmit clock1320as a system clock when responding to a CCIe READ command, and the CDR generated clock1430may be used when receiving data or when the slave device is asleep.

FIG. 19is a conceptual diagram1900illustrating a simplified example of a hardware implementation for an apparatus employing a processing circuit1902that may be configured to perform one or more functions disclosed herein. In accordance with various aspects of the disclosure, an element, or any portion of an element, or any combination of elements as disclosed herein may be implemented using the processing circuit1902. The processing circuit1902may include one or more processors1904that are controlled by some combination of hardware and software modules. Examples of processors1904include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. The one or more processors1904may include specialized processors that perform specific functions, and that may be configured, augmented or controlled by one of the software modules1916. The one or more processors1904may be configured through a combination of software modules1916loaded during initialization, and further configured by loading or unloading one or more software modules1916during operation.

In the illustrated example, the processing circuit1902may be implemented with a bus architecture, represented generally by the bus1910. The bus1910may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit1902and the overall design constraints. The bus1910links together various circuits including the one or more processors1904, and storage1906. Storage1906may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and/or processor-readable media. The bus1910may also link various other circuits such as timing sources, timers, peripherals, voltage regulators, and power management circuits. A bus interface1908may provide an interface between the bus1910and one or more transceivers1912. A transceiver1912may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in a transceiver1912. Each transceiver1912provides a means for communicating with various other apparatus over a transmission medium. Depending upon the nature of the apparatus, a user interface1918(e.g., keypad, display, speaker, microphone, joystick) may also be provided, and may be communicatively coupled to the bus1910directly or through the bus interface1908.

A processor1904may be responsible for managing the bus1910and for general processing that may include the execution of software stored in a computer-readable medium that may include the storage1906. In this respect, the processing circuit1902, including the processor1904, may be used to implement any of the methods, functions and techniques disclosed herein. The storage1906may be used for storing data that is manipulated by the processor1904when executing software, and the software may be configured to implement any one of the methods disclosed herein.

One or more processors1904in the processing circuit1902may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage1906or in an external computer readable medium. The external computer-readable medium and/or storage1906may include a non-transitory computer-readable medium. A non-transitory computer-readable medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a “flash drive,” a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable medium and/or storage1906may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. Computer-readable medium and/or the storage1906may reside in the processing circuit1902, in the processor1904, external to the processing circuit1902, or be distributed across multiple entities including the processing circuit1902. The computer-readable medium and/or storage1906may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

The storage1906may maintain software maintained and/or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules1916. Each of the software modules1916may include instructions and data that, when installed or loaded on the processing circuit1902and executed by the one or more processors1904, contribute to a run-time image1914that controls the operation of the one or more processors1904. When executed, certain instructions may cause the processing circuit1902to perform functions in accordance with certain methods, algorithms and processes described herein.

Some of the software modules1916may be loaded during initialization of the processing circuit1902, and these software modules1916may configure the processing circuit1902to enable performance of the various functions disclosed herein. For example, some software modules1916may configure internal devices and/or logic circuits1922of the processor1904, and may manage access to external devices such as the transceiver1912, the bus interface1908, the user interface1918, timers, mathematical coprocessors, and so on. The software modules1916may include a control program and/or an operating system that interacts with interrupt handlers and device drivers, and that controls access to various resources provided by the processing circuit1902. The resources may include memory, processing time, access to the transceiver1912, the user interface1918, and so on.

One or more processors1904of the processing circuit1902may be multifunctional, whereby some of the software modules1916are loaded and configured to perform different functions or different instances of the same function. The one or more processors1904may additionally be adapted to manage background tasks initiated in response to inputs from the user interface1918, the transceiver1912, and device drivers, for example. To support the performance of multiple functions, the one or more processors1904may be configured to provide a multitasking environment, whereby each of a plurality of functions is implemented as a set of tasks serviced by the one or more processors1904as needed or desired. In one example, the multitasking environment may be implemented using a timesharing program1920that passes control of a processor1904between different tasks, whereby each task returns control of the one or more processors1904to the timesharing program1920upon completion of any outstanding operations and/or in response to an input such as an interrupt. When a task has control of the one or more processors1904, the processing circuit is effectively specialized for the purposes addressed by the function associated with the controlling task. The timesharing program1920may include an operating system, a main loop that transfers control on a round-robin basis, a function that allocates control of the one or more processors1904in accordance with a prioritization of the functions, and/or an interrupt driven main loop that responds to external events by providing control of the one or more processors1904to a handling function.

FIG. 20is a flow chart2000of a method operational on a slave device to receive a transmission over a shared bus and store such data within such transmission into registers using only a clock recovered from the transmission. For instance, the method may be implemented by the receiver device inFIG. 13.

At block2002, a plurality of symbols may be received over a shared bus. The shared bus may be a CCIe bus. The symbols may transition every clock cycle such that no two sequential symbols have the same value.

At block2004, a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols is extracted.

At block2006, the plurality of symbols may be converted into a transition number. The transition number may be a twelve digit ternary number.

At block2008, the transition number may be converted into data bits. The transition number may be converted into the data bits between a penultimate clock cycle and a last clock cycle of the clock signal.

At block2010, at least a portion of the data bits may be stored into one or more registers using only the clock signal. The receiver device may receive and write at least a portion of the data bits to the one or more registers without use of a local free-running clock. The receiver device receives and writes at least a portion of the data bits to the one or more registers while the receiver is in a sleep mode. At least a portion of the data bits is written into the one or more registers by starting a down counter upon detection of a first cycle of the clock signal, triggering a marker when the down counter reaches a pre-defined value, and using the marker to store at least a portion of the data bits into registers. The pre-defined value may occur when a final clock cycle of the clock signal is reached. At least a portion of the data bits may be stored into registers at a last clock cycle of the clock signal.

In one example, the receiver device may independently enter a sleep mode without notifying any other devices coupled to the shared bus.

FIG. 21is a diagram illustrating a simplified example of a hardware implementation for an apparatus2100employing a processing circuit2102. The processing circuit typically has a processor2116that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine. The processing circuit2102may be implemented with a bus architecture, represented generally by the bus2120. The bus2120may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit2102and the overall design constraints. The bus2120links together various circuits including one or more processors and/or hardware modules, represented by the processor2116, the modules or circuits2104,2106,2108and2110, line interface circuits2112configurable to communicate over connectors or wires of a serial bus2114, one or more registers2122that cooperate with symbol/ternary conversion circuitry, and the computer-readable storage medium2118. The bus2120may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processor2116is responsible for general processing, including the execution of software stored on the computer-readable storage medium2118. The software, when executed by the processor2116, causes the processing circuit2102to perform the various functions described supra for any particular apparatus. The computer-readable storage medium2118may also be used for storing data that is manipulated by the processor2116when executing software, including data decoded from symbols transmitted over the connectors2114, which may be configured as data lanes and clock lanes. The processing circuit2102further includes at least one of the modules2104,2106,2108and2110. The modules2104,2106,2108and2110may be software modules running in the processor2116, resident/stored in the computer-readable storage medium2118, one or more hardware modules coupled to the processor2116, or some combination thereof. The modules2104,2106,2108and/or2110may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

In one configuration, the apparatus2100for wireless communication includes a module and/or circuit2104that is configured to receive a plurality of symbols over the serial bus2114, a module and/or circuit2106that is configured to extract a clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, a module and/or circuit2108that is configured to convert the plurality of symbols into a transition number, a module and/or circuit2108that is configured to convert the transition number into data bits, and a module and/or circuit2122that is configured to store at least part of the data bits into registers using only the clock signal.

Moreover, a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, and/or other machine readable mediums for storing information. The term “machine readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing, or carrying instruction(s) and/or data.

The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted that the foregoing embodiments are merely examples and are not to be construed as limiting the invention. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.