Method and apparatus for changing operating conditions of nonvolatile memory

A nonvolatile memory array is associated with counting memory that stores data on a number of times a particular threshold state is reached in the associated nonvolatile memory. The aging physical characteristics of the nonvolatile memory can be compensated by adjusting the operating conditions of the nonvolatile memory. The operating conditions vary depending on the data stored in the counting memory.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to nonvolatile memory and integrated circuits including such memory, and more particularly to architectures for such devices supporting the storage of data on the use of the nonvolatile memory.

2. Description of Related Art

Electrically programmable and erasable nonvolatile memory technologies, such as flash memory and charge trapping memory, have many applications. Technologies based on floating gates, like EEPROM, and localized charge trapping structures like oxide-nitride-oxide memory cells known in various architectures as SONOS cells and NROM, are typically programmable and erasable many times.

The operating characteristics of nonvolatile memory cells change over the lifetime of the nonvolatile memory cells. As nonvolatile memory cells undergo an increasing number of program and erase cycles, the operational characteristics of the nonvolatile memory cells change. This aspect of nonvolatile memory technologies is problematic, because nonvolatile memory cells are expected to operate predictably over their expected lifetimes, regardless of the number of program and erase cycles any particular nonvolatile memory cell has experienced.

One approach to the varying behavior of nonvolatile memory cells due to an increasing number of program and erase cycles is rely exclusively on appropriate margins determined from the beginning, such that even if the operational characteristics of the nonvolatile memory cells change with an increasing number of program and erase cycles, the operating margins account for any expected varying behavior of the nonvolatile memory cells within the specified lifetime of the nonvolatile memory cells. However, exclusively relying on appropriately determined margins may subject nonvolatile memory cells to unnecessarily extreme operating conditions during part of their lifetimes. Such operating margins impliedly are more stringent than required during at least some portion of the lifetime of a nonvolatile memory cell. During this portion of the lifetime of some nonvolatile memory cells, the unnecessarily extreme operating conditions tend to shorten the lifetime of the nonvolatile memory cells.

Another approach to the varying behavior of nonvolatile memory cells due to an increasing number of program and erase cycles is rely exclusively on specifying a shorter lifetime for the nonvolatile memory cells. Although specifying a shorter lifetime is a simple solution, users of the nonvolatile memory cells must then more frequently replace the nonvolatile memory cells, as the increasing number of program and erase cycles undergone by the nonvolatile memory cells approaches the shorter lifetime. If replacing just the nonvolatile memory cells is impractical or not cost-effective, then the entire product which includes the nonvolatile memory cells is discarded or replaced.

Accordingly, it is desirable to provide apparatuses and methods for accounting for the operational characteristics of nonvolatile memory cells which vary with an increasing number of program and erase cycles over the lifetime of the nonvolatile memory cells.

SUMMARY OF THE INVENTION

One aspect is a method for adjusting operating conditions of nonvolatile memory on an integrated circuit. Data about a number of times an erased threshold state has been established in memory cells on the integrated circuit is maintained, for example in a counting memory associated with the memory cells. A bias procedure for the memory cells is determined based on the data, for example by consulting a look up table that indicates the proper bias procedure for a particular number of erase operations undergone by the memory cells. The bias procedure is then applied to the memory cells.

Other aspects are a nonvolatile memory apparatus and a manufacturing method with the counting memory.

In some embodiments, a memory is updated when the erased threshold state has been established in a group of memory cells for another predetermined number of times. For example, a first set of counting memory will be updated every time the erased threshold state has been established in the group of memory cells, and after the erased threshold state has been established another predetermined number of times, then the first set of counting memory is reset, and a second set of counting memory is updated to indicate that the erased threshold state has been established in the memory cells for another predetermined number of times. This second counting memory can be write-once memory so that a power outage or other error will not result in a large error in the counting memory.

In various embodiments, the bias procedure is programming procedure, an erase procedure, a programming procedure which includes verify, an erase procedure which includes verify.

Other examples of determining the bias procedures include adjusting a sequence of biasing arrangements applied in the bias procedure of the memory cells, adjusting a timing of biasing arrangements applied in the bias procedure of the memory cells, adjusting a duration of at least one biasing arrangement applied in the bias procedure of the memory cells, adjusting a waveform shape of at least one biasing arrangement applied in the bias procedure of the memory cells, adjusting a bias magnitude of at least one biasing arrangement applied in the bias procedure of the memory cells, adding at least one biasing arrangement applied in the bias procedure of the memory cells, and removing at least one biasing arrangement applied in the bias procedure of the memory cells.

DETAILED DESCRIPTION

FIG. 1shows an embodiment of a nonvolatile memory array100. The nonvolatile memory array100is divided in to a plurality of nonvolatile memory sectors, such as nonvolatile memory sector1101, nonvolatile memory sector N102, nonvolatile memory sector M103, and nonvolatile memory sector MN104. Each nonvolatile memory sector is associated with a counting memory. For example, nonvolatile memory sector1101is associated with counting memory1111, nonvolatile memory sector N102is associated with counting memory N112, nonvolatile memory sector M103is associated with counting memory M113, and nonvolatile memory sector MN104is associated with counting memory MN114. Each time a particular nonvolatile memory sector is erased, the counting memory associated with the nonvolatile memory sector is updated. This data stored in the counting memory is used to adjust the operating conditions of the nonvolatile memory.

InFIG. 2, an integrated circuit memory is provided with a flash array200. The array includes a plurality of sectors, sectors0–N as illustrated in the figure. The plurality of sectors is associated with a plurality of counting memories CM0–CMN as illustrated in the figure. Addresses are supplied on lines201to an address buffer and latch202. The address buffer and latch202supplies address signals on line203to an X decoder204which includes logical addressing, and to a Y decoder205. The Y decoder is coupled to pass gates206for the bit lines. Pass gates connect bit lines in the array200to sense amplifiers207, and to the program data high voltage circuits208. The program data high voltage circuits208are coupled to a program data latch209which is in turn connected to input/output I/O buffers210. Also the sense amplifiers207are coupled to the I/O buffers210. Input and output data are provided on line211. The I/O buffer210is also coupled to a command control block212which interprets commands received at the I/O buffer210. The command control block212is coupled to the write state machine213. The write state machine213in turn is coupled with control logic214which receives the output enable, chip enable and write enable signals on lines215,216and217respectively. Also the write state machine213controls the program and erase high voltage circuits218which are coupled to the array and to the word line drivers in the X decoder204.

FIG. 3is a simplified block diagram of an integrated circuit. The integrated circuit350includes a memory array300implemented using localized charge trapping memory cells, on a semiconductor substrate. The memory array300includes counting memory370. A row decoder301is coupled to a plurality of word lines302arranged along rows in the memory array300. A column decoder303is coupled to a plurality of bit lines304arranged along columns in the memory array300. Addresses are supplied on bus305to column decoder303and row decoder301. Sense amplifiers and data-in structures in block306are coupled to the column decoder303via data bus307. Data is supplied via the data-in line311from input/output ports on the integrated circuit350, or from other data sources internal or external to the integrated circuit350, to the data-in structures in block306. Data is supplied via the data-out line312from the sense amplifiers in block306to input/output ports on the integrated circuit350, or to other data destinations internal or external to the integrated circuit350. A bias arrangement state machine309controls the application of bias arrangement supply voltages308, such as for the program, erase, erase verify, and program verify voltages, and for the updating data in the counting memory370.

The write state machine213and the command control block212ofFIG. 2, and the bias arrangement state machine309ofFIG. 3determine the bias procedure or writing, reading, and/or erasing based on the number of times an erased threshold state has been established in a memory sector. The verify procedure is adjustable based on this number in some embodiments. Other adjustments are adjusting a sequence of biasing arrangements, a timing of biasing arrangements, a duration of at least one biasing arrangement, a waveform shape of at least one biasing arrangement, a bias magnitude of at least one biasing arrangement, adding a biasing arrangement applied during a biasing procedure, and/or removing a biasing arrangement applied during a biasing procedure. The write state machine213and the command control block212ofFIG. 2also update memory data on how many times a particular sector0–N of the array200has been erased. The bias arrangement state machine309ofFIG. 3updates memory data on how many times a particular sector0–N of the memory array300has been erased.

InFIG. 4, an erase procedure is initiated by an erase command (block400). Heuristically at this point, an index n is set to zero for use in the erase procedure. The erase command in some implementations corresponds with a “flash” sector erase operation typical for flash memory devices in the art. In response to the erase command, a biasing procedure is instituted. In one embodiment, the first operation in the biasing procedure is to apply a bias arrangement that induces hot hole injection in the sector of memory cells (block401). For example, word lines in the sector are biased with about −3 to −7 volts, bit lines coupled to the drains of the memory cells are biased with about +3 to +7 volts, and the source lines coupled to the sources of the memory cells in the sector are biased with ground, while the substrate region in which the memory cell channels are formed is grounded. This induces hot hole injection on the side of the charge trapping structure adjacent the drain terminal for the memory cells in the sector being erased. The specific bias procedure applied during the erase procedure is based on a look up table. The look up table is indexed by the number of erase operations undergone by the memory cells. This number is stored in memory associated with the memory cells, and is updated during the lifetime of the memory cells to reflect the increasing number of erase operations undergone by the memory cells.

After applying the hot hole injection bias arrangement, a state machine or other logic determines whether the erase operation has been successful for each cell in the sector by performing an erase verify operation. The specific voltages applied are based on a look up table indexed by the number of erase operations undergone by the memory cells. Thus, in the next step, the algorithm determines whether the memory cells passed the verify operation (block402). If the cell does not pass verify, then the index n is incremented (block403), and the algorithm determines whether the index has reached a pre-specified maximum number N of retries (block404). If the maximum number of retries has been executed without passing verify, then the procedure fails (block405). If the maximum number of retries has not been executed at block404, then the procedure returns to block402to retry the hot hole injection bias arrangement. If at block402, the memory cell passes verify, then the algorithm passes, and the counting memory is updated with the increased cycling number (block407), and erase procedure is finished (block408). The increased cycling number is accessed next time the sector erase operation is performed on the sector of memory cells. Each time the erase operation is performed, the data stored in the counting memory is used to adjust the erase bias conditions. This addresses the issue of a decrease in erasing speed as the number of times a sector of memory is used increases. Also, each time the verify operation is performed, the data stored in the counting memory is used to adjust the verify bias conditions. This addresses the issue of margin loss as the number of times a sector of memory is used increases.

A program procedure, or other procedure adapted to establish a programmed threshold state in the memory cell, as illustrated inFIG. 5. The procedure includes re-fill operations, in which the cell is first biased to induce a programmed threshold state, and then a charge balancing pulse is applied tending to lower the threshold by causing ejection of electrons from shallow traps in the charge trapping structure, and then the charge trapping structure is “re-filled” with negative charge by a second pulse to induce electron injection into the charge trapping structure. InFIG. 5, a program procedure is initiated by a program command (block500). Heuristically at this point, an index n is set to zero for use in the program retry procedure, and an index m is set to zero for use in counting the refill procedure. The program command in some implementations corresponds with a byte operation typical for flash memory devices in the art. In response to the program command, a biasing procedure is instituted. In one embodiment, the first operation in the biasing procedure is to apply a bias arrangement that induces electron injection memory cells subject of the program operation based on the erase count (block501). For example, channel initiated secondary electron injection is induced in a first bias arrangement. This induces electron injection on one side of the charge trapping structure in the cells being programmed. After applying the electron injection bias arrangement, a state machine or other logic determines whether the program operation has been successful for each cell using a program verify operation. Thus, in the next step, the algorithm determines whether the memory cells passed the verify operation based on the erase count (block502). If the cell does not pass verify, then the index n is incremented (block503), and the algorithm determines whether the index has reached a pre-specified maximum number N of retries (block504). If the maximum number of retries has been executed without passing verify, then the procedure fails (block505). If the maximum number of retries has not been executed at block504, then the procedure returns to block501to retry the electron injection bias arrangement. If at block502, the memory cell passes verify, then the algorithm passes as block509. Each time the program operation is performed, the data stored in the counting memory is used to adjust the program bias conditions. This addresses the issue of a decrease in programming speed as the number of times a sector of memory is used increases. Also, each time the verify operation is performed, the data stored in the counting memory is used to adjust the verify bias conditions. This addresses the issue of margin loss as the number of times a sector of memory is used increases.

Embodiments of the technology include a updating the erase count prior to, after, or during the actual erase procedure. Also, embodiments of the technology include updating the erase count with every erase operation, every other erase operation, or some other regular or irregular interval less frequent than every erase operation.

Another embodiment of counting memory shown inFIG. 6. InFIG. 6, the counting memory600includes a plurality of rewritable counting memories602, illustrated as reprogrammed counting memory0–N in the figure. The counting memory600also includes a plurality of one-time-program counting memory0–N604. The one-time-program counting memory takes into account the fact that the nonvolatile memory associated with the counting memory irreversibly changes behavior with increasing use. The data stored in the counting memory can be inadvertently erased or lost, for example due to a power loss. Particularly if this event occurs multiple times, then the data on the number of times a particular state has been established will no longer accurately reflect the actual number of times that particular state has been established. Such error can be addressed by the use of the one-time-program counting memory604. For example, after the data stored in the rewritable counting memories602is incremented to a particular value M, then the one-time-program counting memory604is incremented to record that the memory associated with the rewritable counting memories602has reached a particular state another M times, and the rewritable counting memories602reset.