DSL line tester

An analog front end system comprising a digital-to-analog converter, a line driver, a multiple-input device, and an analog-to-digital converter is presented. Furthermore, a method for DSL line testing comprising the steps of providing test stimuli to and receiving responses from a DSL line using an analog front end is presented. The presented system and method provides for the testing of a DSL line in an xDSL communications system deployment.

FIELD OF THE INVENTION

The present invention generally relates to digital subscriber line (DSL) communications. More specifically, the invention relates to DSL line testing.

BACKGROUND OF THE INVENTION

In recent years, telephone communication systems have expanded from traditional plain old telephone system (POTS) communications to include high-speed data communications as well. As is known, POTS communications include the transmission of voice information, control signals, public switched telephone network (PSTN) information, as well as, information from ancillary equipment in analog form (i.e., computer modems and facsimile machines) that is transmitted in the POTS bandwidth.

Prompted largely by the desire of large businesses to reliably transfer information over a broadband network, telecommunications service providers have implemented digital subscriber line (DSL) to provide a plethora of interactive multi-media digital signals over the same existing POTS twisted-pair lines. Since the introduction of DSL, several major types of DSL service have been developed and deployed. These major types include ISDN DSL (IDSL), Symmetric DSL (SDSL), Asymmetric DSL (ADSL), and High bit rate DSL (HDSL). With the advent of these major types, represented by the aforementioned acronyms, DSL is also referred to as xDSL.

In order to maintain the reliable operation of DSL communications service, the capability to test and evaluate the DSL line, i.e. the twisted-pair lines (which are typically composed of copper), is desired. In some xDSL deployments, a number of Incumbent Local Exchange Carriers (ILEC's) and Competitive Local Exchange Carriers (CLEC's) have been installing additional external devices known as metallic (e.g., copper) “cross-connects” in conjunction with other additional devices known as DSL Access Multiplexers (DSLAM's) to provide metallic access to the DSL line for testing purposes. Testing of the DSL lines for fault detection or evaluation of the bit-rate capacity of a particular loop can be accomplished using cross-connects and DSLAM's to by-pass the DSL line to an integrated test head. Also, functions for trouble-shooting and installation activities on a DSL line are obtained using cross-connects and DSLAM's. But, metallic cross-connects are external devices that are installed in addition to the required devices for normal operation of a communications system. DSLAM's are also additional devices that are typically integrated with the normal system devices, but may also be installed externally. Because of the additional devices and installation requirements, the use of cross-connects and DSLAM's for testing purposes is an undesirably expensive practice.

HDSL/T1 based communications systems are one popular example of the application of xDSL deployments. In HDSL deployments, such as HDSL/T1 based communications systems, current test systems only offer the capability for in-band (i.e. within the system unit) testing. HDSL/T1 based communications systems have evolved in popularity as a result of the development of the HDSL market as a replacement for conventional T1 systems, which consist of dedicated high-speed digital communications circuits. Specifically, HDSL plugs (where a plug contains some number of connection ports) are being integrated into existing T1 systems as an alternative to traditional T1 plugs. Advantages of this practice include the reduction of overhead equipment, such as repeaters (which amplify or regenerate signals to extend transmission distances), improved performance with respect to crosstalk (i.e. interference from adjacent lines), and higher quality bit-error performance. But, since current testing systems for HDSL/T1 based systems only offer in-band testing capability, the capability to test the physical DSL line using such test systems is lacking. Furthermore, this lack of capability to test the DSL line is a deficiency found in current test systems for other types of xDSL communications systems deployments as well, and costly work-arounds have been currently employed, as discussed above.

Expanding on HDSL/T1 based communications systems as an example of current testing practices in xDSL deployments,FIG. 1shows a simplified block diagram of a typical HDSL/T1 based communications system100and related typical testing components106,112, as is known in the prior art. In this regard, the communications system includes a central office (CO) line unit102and a remote unit104. The CO unit102and the remote unit104are networked to each other by one or more DSL lines110and to other communications systems (not shown) by T1 circuits116. The CO unit102includes, in addition to the testing components106,112, HDSL/T1 interface circuitry114and a T1 line interface unit (LIU)118. Although not shown, the remote unit104includes similar components to the CO unit102, such as interface circuitry114and T1 LIU118.

The testing components106,112, only offer the capability for in-band testing of the communications system100. Essentially, various loop-backs106(where a loop-back is a device that redirects a transmitted signal back to the transmitter for testing purposes), are employed within the communications system100for testing purposes, as shown in FIG.1. Testing is accomplished by detection of loop-back control signals transmitted in-band by a loop-back detector, such as the loop-back detector112. The loop-backs106and the loop-back detector112enable the locating of a problem in the system100at either the CO unit102or the remote unit104, but problems at the remote unit104can only be detected when the interfacing DSL line110is functioning properly (i.e., acceptable bit-rate capacity, no faults, etc.). Furthermore, the typical testing components106,112do not offer the capability to test the DSL line110for faults, proper performance, or other testing criteria.

Therefore, there is a need for a testing system and method capable of testing a DSL line in an xDSL communications system deployment. Furthermore, there is a need for a system and method capable of testing a DSL line in an xDSL deployment that does not require additional, external test-support devices and that is, therefore, cost-effective over the prior art.

SUMMARY OF THE INVENTION

Certain objects, advantages, and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve various objects and advantages, the present invention is directed to a novel system and method of a DSL line tester. Broadly, the present invention provides test stimuli to a DSL line using an analog front end (AFE).

In accordance with a preferred embodiment of the present invention, an AFE system is provided that includes a digital-to-analog converter (D/A) and an analog-to-digital converter (A/D), a line driver, and a multiple-input device. In accordance with another preferred embodiment of the present invention, a method for DSL line testing is provided that includes the steps of transmitting test stimuli to and receiving responses from a DSL line using an AFE.

One advantage of a preferred embodiment of the present invention is that it allows the testing of a DSL line, in an xDSL communications system deployment, for faults, proper performance, or other testing criteria. Another advantage of a preferred embodiment of the present invention is that it allows the testing of a DSL line, in an xDSL communications system deployment, without the requirement of additional, external test-support devices. Yet another advantage of a preferred embodiment of the present invention is that it allows the testing of a DSL line, in an xDSL communications system deployment, that is cost-effective over the prior art.

Other objects, features, and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features, and advantages be included herein within the scope of the present invention, as defined by the claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Having summarized the invention above, reference is now made in detail to the description of the invention as illustrated in the drawings. While the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents included within the spirit and scope of the invention as defined by the appended claims. Indeed, the present invention is believed to be applicable to a variety of systems, devices, and technologies.

Turning now to the drawings, wherein like referenced numerals designate corresponding parts throughout the drawings,FIG. 2shows a block diagram of a typical analog front end (AFE)202with related HDSL/T1 interface components114,118,214,216,218, as is known in the prior art. The following description of the present invention is made in the context of application to HDSL/T1 based communications systems in order to facilitate the description of the present invention, but it should be understood that the present invention can be applied to all communications systems in general that incorporate an xDSL interface and all such applications are included within the scope of the present invention. In this regard, the AFE202includes a digital-to-analog converter (D/A)204and an analog-to-digital converter (AID)206, as is known in the art. Further, as is known in the art, the AFE202includes a line drive208and a programmable gain amplifier (PGA)208. Also included in the AFE202is processing circuitry (not shown) that is responsive to AFE operation commands and is known in the art.

Any interface of an xDSL line to a line of a different communications system, for example T1, requires an AFE at the interface. For example, as shown inFIG. 2, the AFE202provides an interface between the DSL line110and the HDSL/T1 interface circuitry114. In one embodiment of the present invention, the AFE202is utilized to provide test stimuli for testing the DSL line110. Specifically, in a preferred embodiment of the present invention, the D/A204and the A/D206are utilized to generate and provide test stimuli for testing the DSL line110.

In another preferred embodiment of the present invention, testing information is carried on the in-band T1 signal, in a system such as that depicted inFIG. 2, to allow for capture and off-line processing of the testing information. Using the in-band T1 signal, testing samples from the D/A204and A/D206are transmitted over the T1 line116. The CO line unit102interprets the information being carried over the T1 line116as analog data in response to a specific in-band command. Furthermore, the capability to provide fault isolation to the DSL line110is incorporated within the signaling format. To further facilitate the description of the present invention,FIG. 3is presented which shows a diagrammatic representation of a T1 Extended SuperFrame (ESF) format300, as is known in the prior art. T1 ESF300is an enhanced T1 communications format. The format uses 24 frames grouped together as a T1 extended superframe (ESF)300, where each frame (e.g.,302,304,306) contains 24 8-bit channels (e.g.,308-311) that repeat at an 8 kHz frame-rate.

A block diagram representation of a testing system400, in accordance with an embodiment of the present invention, is shown in FIG.4. The testing system400implements an AFE202to interpret T1 test samples402as 8-bit D/A and A/D digitized values, using T1 ESF (e.g.,300ofFIG. 3) in an HDSL/T1 based system (e.g.,100of FIG.1), in response to test commands408that are received by the processing circuitry406. The processing circuitry406is responsive to test commands408, in addition to being responsive to common AFE commands (not depicted). In this embodiment, the test commands408, which may be sent to the AFE along with the test samples402over a T1 line116using a computer or other test input device (not shown), control the interpretation of the test samples402as 8-bit digitized values and the generation of test patterns404based on these digitized values. The digitized values interpreted from the test samples402by the AFE202in response to test commands408allow for the generation of test patterns404that have576samples which repeat for each T1 ESF300(FIG. 3) with a test frequency limited to 192 kHz. As shown inFIG. 4, the test samples402are carried on a T1 line116and the test patterns404are carried on a DSL line110.

A diagrammatic representation of a testing format, in accordance with a preferred embodiment of the present invention, is shown in FIG.5. The testing format comprises a test superframe500comprising 24 test frames (e.g.,502,504) per T1 ESF300(FIG.3). The entire test superframe500is formatted to comprise 384 12-bit samples, and the first 12-bit word after the test superframe marker522represents a test header506, which may be a test control header (during transmission from the test device to the AFE) or a test status header (during transmission from the AFE to the test device). The 12-bit sample format is an example of one format that provides high resolution to facilitate the testing of DSL line performance, but formats of other bit-lengths can be implemented and are included within the scope of the present invention.

A diagrammatic representation of a 12-bit test control header format600, in accordance with a preferred embodiment of the present invention, is shown in FIG.6. The 12-bit control header600is included in the T1 signal that is received by the AFE (e.g.,202ofFIG. 2) from a testing device (not shown) during testing and occupies the position of the test header506(FIG. 5) when the signal is transmitted. Thus, although the control header600is described as 12-bits in length for this particular application, it may be implemented in other bit-lengths and such implementations are included within the scope of the present invention. The information in the control header600provides at least the following capabilities: 1) generation of test patterns in excess of 384 samples; 2) generation of word sampling rates that support the analysis of subject test frequencies; 3) self-testing analysis of an AFE (e.g.,202of FIG.2); 4) providing of additional A/D test inputs for other testing functions; 5) disabling of a hybrid (e.g.,218ofFIG. 2) for various testing purposes.

The control header600is defined by several fields, as shown in FIG.6. The summation of the bit-lengths of these fields is equivalent to the bit-length of the control header600, which in the description for this particular application is 12-bits. Although specific bit-lengths are described for these fields, as follows, it is understood that these specific bit-lengths are only presented to facilitate the description of the present invention. Other bit-lengths can be implemented and such implementations are included within the scope of the present invention. The pattern length field604(a 4-bit field in this description) allows for the generation of up to 16 unique superframes comprised of 16 pattern fields and 384 unique patterns. To support the pattern length scheme, a buffer (not shown) of sufficient size to the store the D/A and A/D samples may be provided.

The sample rate field606(a 2-bit field in this description) allows the selection of one of four predefined sampling rates that the D/A and A/D (e.g.,204,206ofFIG. 2) operate at for the particular test pattern that is generated. The loop-back field610(a 1-bit field in this description) is used to loop-back the D/A204to the AID206for testing of the AFE202(e.g., FIG.2). The hybrid field612(a 1-bit field in this description) is used to enable or disable the internal hybrid216of the AFE202(e.g.,FIG. 2) to facilitate various fault isolation tests. The input select field614(a 2-bit field in this description) is used to select from a plurality of test inputs to the A/D. Between the sample rate field606and the loop-back field610, there is a spare field608(a 2-bit field in this description), as shown in FIG.6. This field may be used to increase the bit-length of another field, add additional functions to the control header600, or provide other fields for the control header600. Furthermore, the A/D mode control sub-header602, as shown inFIG. 6, comprises the fields which are used to control the setting modes of the AFE202(e.g.,FIG. 2) during testing. In this particular description, these fields are the spare field608, the loop-back field610, the hybrid field612, and the input select field614.

A diagrammatic representation of a 12-bit status header format700, in accordance with a preferred embodiment of the present invention, is shown in FIG.7. The status header700is supplied by the CO line unit (e.g.,102of FIG.1). The 12-bit status header700is included in the T1 signal that is transmitted from the AFE (e.g.,202ofFIG. 2) to a testing device (not shown) during testing and occupies the position of the test header506(FIG. 5) when the signal is transmitted. Thus, although the status header700is described as 12-bits in length for this particular application, it may be implemented in other bit-lengths and such implementations are included within the scope of the present invention. The information in the status header700provides at least the following capabilities: 1) identification of the A/D samples for each input test pattern; 2) providing of status in response to a specific control header.

The status header700is defined by several fields, as shown in FIG.7. These fields correspond to the fields of the test control header600(FIG.6). The summation of the bit-lengths of these fields is equivalent to the bit-length of the status header700, which in the description for this particular application is 12-bits. Although specific bit-lengths are described for these fields, as follows, it is understood that these specific bit-lengths are only presented to facilitate the description of the present invention. Other bit-lengths can be implemented and such implementations are included within the scope of the present invention. The pattern length field704(a 4-bit field in this description) allows for the identification of up to 16 unique superframes comprised of 16 pattern fields and 384 unique patterns. To support the pattern length scheme, a buffer (not shown) of sufficient size to the store the D/A and A/D samples may be provided. The sample rate field706(a 2-bit field in this description) provides the selection status of one of four predefined sampling rates that the D/A and A/D operate at for the particular test pattern that is generated. The loop-back field710(a 1-bit field in this description) is used to provide the status of the loop-back of the D/A204to the A/D206for testing of the AFE202(e.g., FIG.2). The hybrid field712(a 1-bit field in this description) is used to provide a status of the internal hybrid216(which is an interface component between the AFE202and the DSL line110) of the AFE202(e.g., FIG.2). The input select field714(a 2-bit field in this description) provides the status of the test input selection(s) to the A/D (e.g.,206of FIG.2). Between the sample rate field706and the loop-back field710, there is a spare field708(a 2-bit field in this description), as shown in FIG.7. This field can be used to provide status or pattern identification in correspondence to the use of the spare field608of the control header600(FIG.6). Furthermore, the AID mode status sub-header702, as shown inFIG. 7, comprises the fields which are used to provide the status of the setting modes of the AFE202(e.g.,FIG. 2) during testing. In this particular description, these fields are the spare field708, the loop-back field710, the hybrid field712, and the input select field714.

A block diagram of an analog front end (AFE) system802and related DSL line interface components800, in accordance with a preferred embodiment of the present invention, is shown in FIG.8. The AFE802comprises a D/A204, an AID206, and a line driver208, similar to the conventional AFE202(FIG.2), but the AFE802also comprises a multiple-input device810and processing circuitry406that is responsive to test commands (not depicted). The multiple-input device810may have two or more inputs and one or more outputs, for example four inputs and one output, as shown in FIG.8. The multiple-input device810multiplexes the inputs to the output(s), thus it may be implemented by, for example, a multiplexer. In this particular description, the multiple-input device810multiplexes a plurality of inputs (850-853) from the DSL line interface components800to the A/D206for testing purposes. As described above, the plurality of inputs are selectable using the input select field614of the control header600(FIG.6). The hybrid input850carries a signal from the hybrid218, which interfaces the D/A204and A/D206to the DSL line110and eliminates the transmit signal from the received signal in normal operation. The tip input851carries a signal from the tip conductor (“tip”)823of the DSL line110for various testing purposes, such as measuring the common-mode voltage with respect to a ground reference. The ring input852carries a signal from the ring conductor (“ring”)824of the DSL line110for various testing purposes, such as measuring the common-mode voltage with respect to a ground reference. Finally, the ground input853supplies a ground signal to the A/D for various testing purposes, such as providing a ground reference voltage for the common-mode voltage measurements of the tip823and ring824of the DSL line110.

Continuing with reference toFIG. 8, the signals carried by tip input851and ring input852pass through an isolation circuit804. The isolation circuit804allows monitoring or testing of the tip823and ring824of the DSL line110while maintaining DC isolation from the DSL line110. As shown inFIG. 8, the isolation circuit804may comprise, for example, a plurality of resistance and capacitance elements (830-835) such as but not limited to conventional electronics resistors and capacitors. These isolation resistance elements (830-833) may be sized to meet applicable regulatory requirements for DC isolation of testing or monitoring equipment from a communications system, which typically would require a very high resistance. Accordingly, the input impedance of the tip input851and ring input852may be made high enough to compensate for the size of the isolation resistance elements (830-833) to minimize signal losses. Other configurations and/or components, not shown, may be implemented to accomplish the function of the isolation circuit804within the scope of the present invention, for example an isolation transformer or a longitudinal sensing circuit using magnetic isolation instead of capacitive isolation.

Ground input853(FIG. 8) supplies a ground signal to the A/D from a ground circuit806. The ground circuit806provides a ground reference for monitoring and testing of the DSL line110for imbalances on the tip823or ring824with respect to ground, for example, a line-to-ground fault. As shown inFIG. 8, the ground circuit806may comprise a connection to a ground reference point841, such as the common ground of the AFE802, an earth ground point844, and a plurality of resistors (842,843). Although not shown, other configurations and/or components may be implemented to accomplish the function of the ground circuit806within the scope of the present invention, such as an isolation transformer.

The AFE802can interpret T1 test samples received via a T1 line116as digitized values and generate test patterns based on these digitized values in response to test commands (not depicted), such as those contained in the control header600, that are received by the processing circuitry406. This may involve the processing circuitry sending control signals to various elements of the AFE802such the D/A204, the A/D206, the line driver208, or the multiple input device810. The processing circuitry406is responsive to the test commands, in addition to being responsive to common AFE commands (also not depicted). Further, in response to the test commands received by the processing circuitry406, the AFE802can select from various test inputs (e.g.,850-853) that are connected to the multiple input device810. Other test functions may also be performed by the AFE802in response to test commands received by the processing circuitry406, for example, hybrid218balance, line driver208linearity, and AFE802dynamic range measurements.

FIG. 9shows a flowchart diagram of a method900for testing a DSL line that may be applied, for example, to the testing system ofFIG. 4to test a DSL line in accordance with one embodiment of the present invention. In this regard, the method900for testing a DSL line will be described in reference to its possible application to the testing system ofFIG. 4to facilitate the description of the present invention. It should be understood that the method900for testing a DSL line may be applied to other testing systems besides that ofFIG. 4, as will be apparent to one skilled in the art. It should be further understood that although the flowchart diagram ofFIG. 9presents the method900with steps in a specific order, one or more of these steps may be executed in a different order than that shown inFIG. 9, or described below, within the scope of the present invention, as will be apparent to one skilled in the art.

The method900for testing a DSL line begins with step902that is designated as “start”. From the start step902, the method900comprises step904in which T1 test samples402are transmitted to an AFE202via a communications line, such as T1 line116. The test samples402may be transmitted, for example, from a testing device such as a computer or other device capable of transmitting test samples402to the AFE202. Following step904, the method900comprises step906. In this step, the AFE202interprets the transmitted test samples402as multi-bit digitized values. The step906may be controlled, for example, by processing circuitry406that is responsive to internal settings or external test commands408received by the AFE202.

From step906, the method900comprises step908in which the AFE202generates test patterns404from the digitized values that are interpreted from the test samples402in step906. The step908may be controlled, for example, by processing circuitry406that is responsive to internal settings or external test commands408received by the APE202.

Following step908, the method900comprises step910in which the DSL line110that is interfaced to the T1 line116is tested using the test patterns404. Thus, in step910, the DSL line110is tested via the AFE202. The step910may be controlled, for example, by processing circuitry406that is responsive to internal settings or external test commands408received by the AFE202. After step910, the steps of the method900for testing a DSL line are complete and the method900proceeds to the final step912which is designated “stop”.

FIG. 10shows a flowchart diagram of a method1000for testing a DSL line that may be applied, for example, to the analog front end (AFE) system ofFIG. 8to test a DSL line in accordance with a preferred embodiment of the present invention. In this regard, the method1000for testing a DSL line will be described in reference to its possible application to the AFE system ofFIG. 8to facilitate the description of the present invention. It should be understood that the method1000for testing a DSL line may be applied to other systems besides that ofFIG. 8, as will be apparent to one skilled in the art. It should be further understood that although the flowchart diagram ofFIG. 10presents the method1000with steps in a specific order, one or more of these steps may be executed in a different order than that shown inFIG. 10, or described below, within the scope of the present invention, as will be apparent to one skilled in the art.

The method1000for testing a DSL line begins with step1002that is designated as “start”. From the start step1002, the method1000comprises step1004in which test commands and T1 test samples are transmitted to an AFE system802via a communications line, such as T1 line116. The test commands and test samples may be transmitted, for example, from a testing device such as a computer or other device capable of transmitting test commands and test samples to the AFE802. Following step1004, the method1000comprises step1006. In this step, the AFE802interprets the transmitted test samples as multi-bit digitized values in response to the transmitted test commands. The step1006may be controlled by processing circuitry406that is responsive to the test commands received by the AFE802.

From step1006, the method1000comprises step1008in which the AFE802generates test patterns, in response to the test commands transmitted to the AFE802in step1004, from the digitized values that are interpreted from the test samples in step1006. The step1008may be controlled by processing circuitry406that is responsive to the test commands received by the AFE802.

Following step1008, the method1000comprises step1010in which the AFE802selects from test inputs (e.g.,850-853) to the AFE802in response to the test commands transmitted to the AFE802. In this regard, the selection of one or more of the inputs to the AFE802, as was described in more detail above in reference toFIG. 8, facilitates various testing, such as verification of the AFE802, hybrid218balance, line driver208linearity, or other fault mechanisms that could be attributed to the testing circuit for the DSL line110. The step1008may be controlled by processing circuitry406that is responsive to the test commands received by the AFE802.

From step1010, the method1000comprises step1012in which the DSL line110that is interfaced to the T1 line116is tested, in response to the test commands, using the test patterns generated by the AFE802in step1008. Thus, in step1012, the DSL line110is tested via the AFE802. The step1012may be controlled by processing circuitry406that is responsive to the test commands received by the AFE802. After step1012, the steps of the method1000for testing a DSL line are complete and the method1000proceeds to the final step1014which is designated “stop”.

It is reiterated that the preceding description of the present invention is made in the context of application to HDSL/T1 based communications systems in order to facilitate the description of the present invention. Further, it should be understood that the present invention can be applied to all communications systems in general that incorporate an xDSL interface and all such applications are included within the scope of the present invention.

The flowchart diagrams of the method900,1000for testing a DSL line described above and shown inFIGS. 9 and 10of the present invention show the architecture, functionality, and operation of possible implementations of the present invention. In this regard, each block may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order shown.

It is emphasized that the above-described embodiments of the present invention, particularly any “preferred” embodiments, are merely possible examples of the implementations that are merely set forth for a clear understanding of the principles of the present invention. It will be apparent to those skilled in the art that many modifications and variations may be made to the above-disclosed embodiments of the present invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included within the scope of the disclosure and present invention and protected by the following claims.