Bonding structure and method of forming same

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

BACKGROUND

In wafer-to-wafer bonding technology, various methods have been developed to bond two package components (such as wafers) together. Some wafer bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In fusion bonding, an oxide surface of a wafer is bonded to an oxide surface or a silicon surface of another wafer. In eutectic bonding, two eutectic materials are placed together, and a high pressure and a high temperature are applied. The eutectic materials are hence melted. When the melted eutectic materials solidify, the wafers bond together. In direct metal-to-metal bonding, two metal pads are pressed against each other at an elevated temperature, and the inter-diffusion of the metal pads causes the bonding of the metal pads. In hybrid bonding, the metal pads of two wafers are bonded to each other through direct metal-to-metal bonding, and an oxide surface of one of the two wafers is bonded to an oxide surface or a silicon surface of the other wafer.

DETAILED DESCRIPTION

A bonding structure and method is provided, in accordance with some embodiments. A surface dielectric layer is formed over an interconnect structure, and bonding pads are formed in the surface dielectric layer. Through the use of a planarization stop layer, the thickness of the surface dielectric layer can be reduced. This can provide increased thermal conduction across the surface dielectric layer, which can allow for improved device performance at higher temperatures. Additionally, the overall size of the device may be reduced due to the thinner surface dielectric layer.

FIGS. 1-12illustrate cross-sectional views of intermediate stages in the formation of a device structure100, in accordance with some embodiments.FIG. 1illustrates a substrate102and features formed over the substrate102, in accordance with some embodiments. The substrate102may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, a SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

In some embodiments, the substrate102and features formed thereon are used to form a device die. In such embodiments, integrated circuit devices may be formed on the top surface of the substrate102. Exemplary integrated circuit devices may include complementary metal-oxide semiconductor (CMOS) transistors, fin field-effect transistors (FinFETs), resistors, capacitors, diodes, the like, or a combination thereof. The details of the integrated circuit devices are not illustrated herein. In some embodiments, the substrate102is used for forming an interposer structure. In such embodiments, no active devices such as transistors or diodes are formed on the substrate102. Passive devices such as capacitors, resistors, inductors, or the like may be formed in the substrate102. The substrate102may also be a dielectric substrate in some embodiments in which the substrate102is part of an interposer structure. In some embodiments, through vias (not shown) may be formed extending through the substrate102in order to interconnect components on the opposite sides of the substrate102.

InFIG. 1, a dielectric layer104is formed over the substrate102. The dielectric layer104may include one or more layers comprising one or more materials. In embodiments where integrated circuit devices are formed on the substrate102, the dielectric layer104may fill the spaces between the gate stacks of transistors (not shown) of the integrated circuit devices. In some embodiments, the dielectric layer104may be an inter-layer dielectric (ILD) layer. The dielectric layer104may be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), the like, or a combination thereof. In some embodiments, the dielectric layer104may include a layer formed from a low-k dielectric material having a k-value lower than about 3.0. In some embodiments, the dielectric layer104is formed using a spin-coating process or formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD), or the like.

Further inFIG. 1, contact plugs106are formed in the dielectric layer104. The contact plugs106are electrically connected to the integrated circuit devices of the substrate102. For example, the contact plugs106may be gate contact plugs that are connected to the gate electrodes of transistors (not shown) of the integrated circuit devices, and/or may be source/drain contact plugs that are electrically connected to the source/drain regions of the transistors. After forming the dielectric layer104, openings for the contact plugs106are formed through the dielectric layer104. The openings may be formed using acceptable photolithography and etching techniques. For example, a photoresist may be formed over the dielectric layer and patterned, and the openings in the dielectric layer104formed by etching the dielectric layer104using the patterened photoresist as an etching mask. The dielectric layer104may be etched using a suitable wet etching process, dry etching process, or a combination thereof. In some embodiments, a liner such as a diffusion barrier layer, an adhesion layer, or the like may be formed in the openings, and a conductive material may then be formed in the openings over the liner. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, the like, or a combination thereof. The conductive material may include cobalt, copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, the like, or a combination thereof. After forming the conductive material, a planarization process, such as a grinding process, a chemical-mechanical polish (CMP) process, or the like may be performed to remove excess material from a surface of dielectric layer104. The remaining liner and conductive material thus form the contact plugs106.

InFIG. 2, an interconnect structure108is formed over the contact plugs106and the dielectric layer104, in accordance with some embodiments. The interconnect structure108provides routing and electrical connections between devices formed in the substrate102, and may be a redistribution structure. The interconnect structure108may include a plurality of insulating layers110, which may be inter-metal dielectric (IMD) layers. Each of the insulating layers110includes one or more metal lines112and/or vias113formed therein. The metal lines112and vias113may be electrically connected to the active and/or passive devices of the substrate102by the contact plugs106. The metal lines112may be, for example, redistribution layers.

In some embodiments, the insulating layers110may be formed from a low-k dielectric material having a k-value lower than about 3.0. The insulating layers110may be formed from an extra-low-k (ELK) dielectric material having a k-value of less than 2.5. In some embodiments, the insulating layers110may be formed from an oxygen-containing and/or carbon containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), the like, or a combination thereof. In some embodiments, some or all of insulating layers110are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. In some embodiments, etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride, or the like, are formed between insulating layers110. In some embodiments, the IMD layers110are formed from a porous material such as SiOCN, SiCN, SiOC, SiOCH, or the like, and may be formed by spin-on coating or a deposition process such as plasma enhanced chemical vapor deposition (PECVD), CVD, PVD, or the like. In some embodiments, the interconnect structure108may include one or more other types of layers, such as diffusion barrier layers (not shown).

In some embodiments, the interconnect structure108may be formed using a single and/or a dual damascene process, a via-first process, or a metal-first process. In an embodiment, an insulating layer110is formed, and openings (not shown) are formed therein using acceptable photolithography and etching techniques. Diffusion barrier layers (not shown) may be formed in the openings and may include a material such as TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the openings by a deposition process such as CVD, ALD, or the like. A conductive material may be formed in the openings from copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like, and may be formed over the diffusion barrier layers in the openings by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. After formation of the conductive material, excess conductive material may be removed using, for example, a planarization process such as CMP, thereby leaving metal lines112in the openings of the bottommost IMD layer110. The process may then be repeated to form additional insulating layers110and metal lines112and vias113therein. In some embodiments, the topmost insulating layer110and the metal lines112formed therein may be formed having a thickness greater than a thickness of the other insulating layers110of the interconnect structure108. In some embodiments, one or more of the topmost metal lines112are dummy lines that are electrically isolated from the substrate102.

InFIG. 3, a passivation layer114is formed over the interconnect structure108, and one or more openings116are formed in the passivation layer114. The passivation layer114may comprise one or more layers of one or more materials. For example, the passivation layer114may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination. The passivation layer114may be formed by a suitable process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. The passivation layer114may be formed having a thickness greater than a thickness of the topmost insulating layer110.

The openings116in the passivation layer114may be formed using a suitable photolithographic and etching process. For example, a photoresist may be formed over the passivation layer114and patterned, and then the patterned photoresist may be used as an etching mask. The passivation layer114may be etched using a suitable wet etching process and/or dry etching process. The openings116are formed to expose portions of the metal layer112(e.g., the topmost metal line112of the interconnect structure108) for electrical connection.

InFIG. 4, conductive pads118are formed over the passivation layer114in accordance with some embodiments. One or more conductive pads118may be formed extending through the openings116and make electrical connection with one or more of the topmost metal lines112of the interconnect structure108. In some embodiments, the conductive pads118are formed by first forming a seed layer over the passivation layer114and the openings116. In some embodiments, the seed layer is a metal layer comprising one or more layers, which may be formed of different materials. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is formed and patterned on the seed layer and conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. In some embodiments, the conductive material may be formed by a plating process, such as using an electroplating or electroless plating process, or the like. The conductive material may include one or more materials such as copper, titanium, tungsten, gold, cobalt, aluminum, the like, or a combination thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, remaining exposed portions of the seed layer may be removed using an acceptable etching process, such as a wet etching process or a dry etching process. The remaining portions of the seed layer and conductive material form the conductive pads118.

In some embodiments, the conductive pads118may be formed by first depositing a blanket layer of a conductive material. For example, CVD, PVD, or the like may be used to deposit a layer of aluminum over the over the passivation layer114and the openings116, and over the metal line112. A photoresist layer (not separately illustrated) may then be formed over the aluminum layer and the aluminum layer may be etched to form the conductive pads118. The conductive pads118may be formed using other techniques in other embodiments, and all such techniques are considered within the scope of this disclosure.

In some embodiments, the conductive pads118that are electrically connected to the interconnect structure108may be used as test pads before additional processing steps are performed. For example, the conductive pads118may be probed as part of a wafer-acceptance-test, a circuit test, a Known Good Die (KGD) test, or the like. The probing may be performed to verify the functionality of the active or passive devices of the substrate102or the respective electrical connections within the substrate102or interconnect structure108(e.g., the metal lines112or the vias113). The probing may be performed by contacting a probe needle (not shown) to the conductive pads118. The probe needle may be a part of a probe card that includes multiple probe needles which, for example, may be connected to testing equipment.

In some embodiments, the conductive material of the conductive pads118may be different than the conductive material of the metal lines112. For example, the conductive pads118may be aluminum and the metal lines112may be copper, though other conductive materials may be used. In some embodiments, the conductive pads118may have a width W between about 2 μm and about 30 μm or a length (e.g., perpendicular to the width) between about 20 μm and about 100 μm. In some embodiments, the conductive pads118may have a thickness between about 500 nm and about 3000 nm. In some cases, a thicker conductive pad118may have less risk of becoming damaged when being probed. As such, the conductive pads118may have a greater thickness than the metal lines112. To reduce the chance of damage during probing, the conductive pads118may also be formed of a conductive material (e.g., aluminum) that is less soft than the conductive material (e.g., copper) of the metal lines112. The embodiments described in the present disclosure may allow for a greater thickness of conductive pads118to be used without increasing the overall thickness of the structure (e.g., device structure100).

Turning toFIG. 5, a first stop layer120is formed over the conductive pads118and the passivation layer114, in accordance with some embodiments. In some embodiments, the first stop layer120may be used as a stop layer for a subsequent CMP process (seeFIG. 7). The first stop layer120may comprise a dielectric material such as silicon carbide, silicon oxycarbide, silicon nitride, silicon oxide, the like, or a combination thereof. The first stop layer120may be formed using a process such as CVD, PVD, ALD, or the like. The first stop layer120is deposited over the top surfaces of the conductive pads118, and may be deposited conformally over the top surfaces of the passivation layer114and the conductive pads118and over the sidewalls of the conductive pads118. In some embodiments, the first stop layer120may be formed having a thickness T1that is between about 300 Å and about 1500 Å. The first stop layer120may be formed to a thickness suitable to stop or slow the planarization process described below inFIG. 7. In some cases, a thicker first stop layer120may be used to avoid exposing the conductive pads118during the planarization process described below. In some embodiments, the first stop layer120is also used as an etch stop (see e.g.,FIGS. 10 and 16), and the thickness of the first stop layer120may be chosen such that a sufficient thickness of the first stop layer120remains after planarization to act as an etch stop.

Turning toFIG. 6, a dielectric layer122is formed over the first stop layer120. The dielectric layer122may be formed from one or more layers of one or more dielectric materials, such as silicon oxide, silicon nitride, SiOCH, SiCH, the like, or a combination thereof. The dielectric layer122may be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the dielectric layer122and the first stop layer120are made of different dielectric materials. The dielectric layer122may be formed to have a thickness greater than a thickness of the conductive pads118so that the material of the dielectric layer122laterally surrounds the conductive pads118, and so that the dielectric layer122may be planarized (see below) without exposing the conductive pads118.

InFIG. 7, a planarization process is performed on the dielectric layer122. The planarization process may be, for example, a CMP process. The first stop layer120is used to stop or slow the planarization process near the top surfaces of the conductive pads118. As shown inFIG. 7, a portion of the first stop layer120may remain over the top surfaces of the conductive pads118after the planarization process has been performed. In some embodiments, the thickness T2of the first stop layer120that remains on the conductive pads118may be between about 100 Å and about 300 Å, such as about between about 50 Å and about 150 Å. In some embodiments, the ratio of T1to T2may be between about 3 to 1 and about 50 to 1. The thickness T2of the remaining first stop layer120may be thick enough to protect the conductive pads118. In some cases, a smaller thickness T2allows for a smaller overall distance between the conductive pads118and the top surface of the surface dielectric layer126(see e.g.,FIG. 17), which can improve thermal conductivity and reduce capacitance effects in the final device. In some embodiments a portion of the first stop layer120may be left remaining on the conductive pads118in order to be subsequently used as an etch stop (see e.g.,FIG. 10). In some embodiments, the planarization process may be controlled such that the thickness T2of the remaining first stop layer120may be sufficient to act as an etch stop.

Turning toFIG. 8, a second stop layer124is formed over the dielectric layer122and the first stop layer120. The second stop layer124may be subsequently used as an etch stop layer (seeFIG. 10). In some embodiments, the second stop layer124is the same material as the first stop layer120, but the first stop layer120and the second stop layer124may be different materials in other embodiments. The second stop layer124may comprise a material such as silicon carbide, silicon oxycarbide, silicon nitride, silicon oxide, the like, or a combination thereof. The second stop layer124may be formed using a process such as CVD, PVD, ALD, or the like. In some cases, the use of a second stop layer124may improve planarity of the surface of the second stop layer124and the planarity of surfaces during subsequent process steps. In some embodiments, the second stop layer124may be formed having a thickness that is between about 150 Å and about 1500 Å, such as about 300 Å. In some embodiments, the thickness of the second stop layer124may be sufficient to act as an etch stop (see e.g.,FIG. 10). In some cases, a thicker second stop layer124may improve planarity of the surface of the second stop layer124and of subsequently formed features.

Turning toFIG. 9, a surface dielectric layer126is formed over the second stop layer124. The surface dielectric layer126may be formed from one or more layers of one or more dielectric materials, and may comprise a silicon-containing material such as silicon oxide, silicon oxynitride, silicon nitride, or the like. In some embodiments, the surface dielectric layer126and the second stop layer124are made of different dielectric materials. The surface dielectric layer126may be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. In an embodiment, the surface dielectric layer126comprises silicon oxide, and may alternatively be referred to as a “bonding oxide.”

InFIG. 10, openings127are formed in the surface dielectric layer126, in accordance with some embodiments. The openings127may be formed using acceptable photolithography and etching techniques. For example, the photolithography process may include forming a photoresist (not shown) over the surface dielectric layer126, patterning the photoresist with openings corresponding to the openings127, extending the pad openings127through the photoresist and into the surface dielectric layer126, and then removing the photoresist. The photoresist may be a single-layer photoresist, a bi-layer photoresist, a tri-layer photoresist, or the like. The etching process is performed such that the etch stops on the second stop layer124. An additional etching process may be performed to extend the openings127through the second stop layer124. In some regions in which the second stop layer124is on the first stop layer120, the openings127may be extended through both the second stop layer124and the first stop layer120. For example, in regions over the conductive pads118, the openings127may extend through both the second stop layer124and the first stop layer120to expose top surfaces of the conductive pads118. Example openings that extend through both the second stop layer124and the first stop layer120are designated inFIG. 10as openings127A. In some embodiments, the openings127may have a width between about 1 μm and about 5 μm, although other widths are possible. In some embodiments, the openings127may have a tapered profile, such as having a bottom width between about 1 μm and about 2 μm and a top width between about 2 μm and about 5 μm. In some cases, the width of the openings127A may be between about 10% and about 100% of the width W of the conductive pad118. In this manner, the width of the openings127A may be such that multiple openings127A may be formed over a single conductive pad118.

Turning toFIG. 11, bonding pads128are formed in the openings127, in accordance with some embodiments. The bonding pads128may have similar dimensions as the openings127in which they are formed, and may have a similar shape (e.g., have a tapered profile). The bonding pads128may be formed of a conductive material including a metal or a metal alloy such as copper, silver, gold, tungsten, cobalt, aluminum, the like, or a combination thereof. In some embodiments, the bonding pads128and the conductive pads118may be different conductive materials. For example, the bonding pads128may be copper and the conductive pads118may be aluminum, though other materials are possible. In some embodiments, the formation of the bonding pads128includes depositing a seed layer (not shown) in the openings127, which may include copper, a copper alloy, titanium, or the like, and then filling the remainder of the openings127using, for example, a plating process, an electro-less plating process, or the like. Excess conductive material and the seed layer may be removed from the surface dielectric layer126using a planarization process such as a CMP process. The process shown inFIG. 11represents an example process that may be used for forming bonding pads128, and other processes or techniques may be used in other embodiments, such as a damascene process, a dual damascene process, or another process. The bonding pads128formed in the openings127A may make electrical connection to the conductive pads118, and multiple bonding pads128may make electrical connection to the same conductive pad118. In this manner, a device structure100may be formed, having bonding pads128that are electrically connected to devices in the substrate102.

Still referring toFIG. 11, in some embodiments, some bonding pads may be formed without having electrical connection to the conductive pads118. Bonding pads without electrical connection may be, for example, “dummy” bonding pads that may reduce uneven loading and improve surface planarity after the planarization step that removes excess conductive material. By improving surface planarity, a better bond between surfaces (seeFIG. 21) may be obtained. Example dummy bonding pads are designated as bonding pads128D inFIG. 11. Turning toFIG. 12, in some embodiments, dummy conductive pads118may be formed, examples of which are designated as dummy conductive pads118D. Forming dummy conductive pads118D may also reduce loading effects and further improve surface planarity. Dummy conductive pads118D may be used in any of the embodiments described herein, including those described below. The dummy conductive pads118D may or may not be electrically connected to any metal lines112. Dummy bonding pads128D may be formed in contact with dummy conductive pads118D, as shown inFIG. 12. In some embodiments, dummy bonding pads118D and/or dummy conductive pads128D are not formed.

Returning toFIG. 11, the use of a first stop layer120as a stop for the planarization process (seeFIG. 7) can allow for a thinner surface dielectric layer126. For example, the surface dielectric layer126may be formed having a thickness T3that is between about 0.5 μm and about 8 μm, such as about 1.5 μm or about 6 μm, though other thicknesses T3may be used. In some cases, the embodiment processes described herein can reduce the thickness of the surface dielectric layer126by as much as about 50%. By reducing the thickness of the surface dielectric layer126, the height of the bonding pads128may be reduced, which can reduce the resistance of the bonding pads128and improve electrical performance of the device. Additionally, by forming a thinner surface dielectric layer126as described herein, the combined thickness of all dielectric layers above the conductive pads118(e.g., the combined thickness of the surface dielectric layer126, the first stop layer120, and the second stop layer124) may be reduced. Reducing the combined thickness of the dielectric layers in this manner can reduce the barrier to thermal conduction (e.g., across the dielectric layers), and the thermal performance of the device may be improved. A thinner surface dielectric layer126can also reduce undesired capacitive effects. Having a thinner surface dielectric layer126can also reduce the overall thickness of the final device or package.

FIGS. 13-17illustrate intermediate stages in the formation of a device structure150, in accordance with some embodiments.FIGS. 13-17are cross-sectional views of a second embodiment in which the second stop layer124is omitted. By omitting the formation of the second stop layer124, the number of process steps may be reduced.

Turning toFIG. 13, a structure is shown that is similar toFIG. 6, in which a dielectric layer122has been formed over the first stop layer120. The first stop layer120may be similar to that described previously inFIG. 5, and in some embodiments may be formed having a thickness T4that is between about 500 Å and about 1500 Å, such as about 500 Å. The first stop layer120may be formed to a thickness suitable to stop or slow the planarization process described below inFIG. 14. The dielectric layer122may be a similar material as that described previously inFIG. 6, and may be formed in a similar manner.

InFIG. 14, a planarization process is performed on the dielectric layer122, using the first stop layer120. As shown inFIG. 14, portions of the first stop layer120remain on the conductive pads118. In some embodiments, the thickness T5of the first stop layer120remaining on the conductive pads118may be between about 100 Å and about 500 Å, such as about 300 Å. In the embodiment shown inFIG. 14, the thickness T5of the remaining first stop layer120may be greater than the thickness T2of the remaining first stop layer120shown inFIG. 7due to the fact that the first stop layer120shown inFIG. 14is used as both a planarization stop layer and as an etch stop layer, described below inFIG. 16.

Turning toFIG. 15, a surface dielectric layer126is formed over the first stop layer120, which may be similar to surface dielectric layer126described previously inFIG. 9. InFIG. 16, openings127are formed in the surface dielectric layer126. The openings127may be formed using acceptable photolithography and etching techniques as described previously. The openings127may be formed using the first stop layer120as an etch stop. The openings127then may be extended through the first stop layer120to expose the conductive pads118. In this manner, the first stop layer120is used both as a planarization stop layer and as an etch stop layer.

Turning toFIG. 17, bonding pads128are formed in the openings127to make electrical connection with the conductive pads118. The bonding pads128may be formed in a similar manner as described previously. In this manner, a device structure150may be formed using a single stop layer (the first stop layer120), and thus may be formed using fewer process steps. The device structure150also retains the benefit of the thinner surface dielectric layer126described above with respect toFIG. 11.

FIGS. 18-21illustrate intermediate stages in the formation of a device structure160, in accordance with some embodiments.FIGS. 18-21are cross-sectional views of a third embodiment in which bonding pad vias may be formed through the dielectric layer122and the passivation layer114to electrically connect some bonding pads133to the metal layer lines of the interconnect structure108. Besides providing additional electrical connection, the bonding pad vias can provide improved thermal conduction and thus improve the thermal performance of the device.

Turning toFIG. 18, a surface dielectric layer126is formed over the second stop layer124, which may be similar to surface dielectric layer126and second stop layer124described previously inFIG. 9. In some embodiments, portions of the dielectric layer122are enclosed by the first stop layer120and the second stop layer124, as shown inFIG. 18. InFIG. 19, first openings131A are formed in the surface dielectric layer126. The first openings131A may be formed using acceptable photolithography and etching techniques as described previously. The first openings131A may be formed using the second stop layer124and/or the first stop layer120as etch stops. The first openings131A then may be extended through the second stop layer124and/or the first stop layer120to expose the conductive pads118.

Turning toFIG. 20, via openings131B are formed extending through the dielectric layer122and the passivation layer114. The via openings131B are formed at the bottom of the openings131A that are not located over the conductive pads118. The via openings131B expose the metal layer112for electrical connection. The via openings131B may be formed using acceptable photolithography and etching techniques. The photolithography process may include forming a photoresist (not shown) over the surface dielectric layer126and in the first openings131A, patterning the photoresist with openings corresponding to the via openings131B, extending the via openings131B through the photoresist and through the passivation layer114, and then removing the photoresist. In some embodiments, the via openings131B may have a smaller width that is between about 1 μm and about 3 μm, or may have a width that is between about 50% and about 100% of the width of the first openings131A.

Turning toFIG. 21, bonding pads133A and via bonding pads133B are formed in the openings131A and131B to make electrical connection with the conductive pads118and the metal lines112. The bonding pads133A make electrical connection to the conductive pads118, and the via bonding pads133B make electrical connection to the metal lines112. The bonding pads133A and the via bonding pads133B may be formed in a similar manner as bonding pads128described previously. In this manner, additional electrical connections may be made from bonding pads to the interconnect structure108. In some embodiments, one or more of the via bonding pads133B may not be electrically connected, and may be “dummy” features used to reduce loading and improve planarity. In some embodiments, a dummy via bonding pad133B may be connected to metal layer lines112that are isolated from the interconnect structure108. As shown inFIG. 21, the conductive pads118are separated from the surface dielectric layer126by the first stop layer120and/or the second stop layer124.

Turning toFIG. 22, a device package1000is shown comprising two device structures bonded together, in accordance with some embodiments. The device package1000includes a first device structure100and a second device structure200, either or both of which may be similar to device structure100,150, or160described previously. The bonding pads128and surface dielectric layer126of the first device structure100are bonded to the bonding pads228and surface dielectric layer226of the second device structure200. In some embodiments, the bonding pads128of the first device structure100and the bonding pads228of the second device structure200are the same material. In some embodiments, the surface dielectric layer126of the first device structure100and the surface dielectric layer226of the second device structure200are the same material.

InFIG. 22, the second device structure200is bonded to the first device structure100using, e.g., direct bonding or hybrid bonding. Before performing the bonding, a surface treatment may be performed on the second device structure200or the first device structure100. In some embodiments, the surface treatment includes a plasma treatment. The plasma treatment may be performed in a vacuum environment (e.g., a vacuum chamber, not shown). The process gas used for generating the plasma may be a hydrogen-containing gas, which includes a first gas including hydrogen (H2) and argon (Ar), a second gas including H2and nitrogen (N2), or a third gas including H2and helium (He). The plasma treatment may also be performed using pure or substantially pure H2, Ar, or N2as the process gas, which treats the surfaces of the bonding pads128or228and the surface dielectric layers126or226. The second device structure200or the first device structure100may be treated with the same surface treatment process, or with different surface treatment processes. In some embodiments, the second device structure200or the first device structure100may be cleaned after the surface treatment. Cleaning may include performing a chemical cleaning and a de-ionized water cleaning/rinse.

Next, a pre-bonding process may be performed with the second device structure200and the first device structure100. The second device structure200and the first device structure100are aligned, with the bonding pads228of the second device structure200being aligned to the bonding pads128of the first device structure100. After the alignment, the second device structure200and the first device structure100are pressed against each other. The pressing force may be less than about 5 Newtons per die in some embodiments, although a greater or smaller force may also be used. The pre-bonding process may be performed at room temperature (e.g., at a temperature of from about 21° C. to about 25° C.), although higher temperatures may be used. The pre-bonding time may be shorter than about 1 minute, for example.

After the pre-bonding, the surface dielectric layer226of the second device structure200and surface dielectric layer126of the first device structure100are bonded to each other. The bonding interface is labeled inFIGS. 22 and 23as “B.” The second device structure200and the first device structure100in combination are referred to as device package1000hereinafter. The bond of the device package1000may be strengthened in a subsequent annealing step. The device package1000may be annealed at a temperature of from about 300° C. to about 400° C., for example. The annealing may be performed for a period of time between about 1 hour and about 2 hours, for example. During the annealing, metals in the bonding pads128and228may diffuse to each other so that metal-to-metal bonds are also formed. Hence, the resulting bonds of the second device structure200and the first device structure100may be hybrid bonds. In some embodiments, after the annealing, no material interface is present between the bonding pads118and their corresponding bonding pads128.

In some embodiments, a distance from the conductive pads118of the first device structure100and the conductive pads218of the second device structure200is between about 1 μm and about 16 μm, such as about 3 μm or about 12 μm. In some embodiments, the distance from the conductive pads118to the interface B is different than the distance from the conductive pads218to the interface B. In some embodiments, one or more bonding pads128may be offset along the interface B from their corresponding bonding pads228. In some embodiments, a bonding pad128and its corresponding bonding pad228may be electrically isolated from conductive pads118, conductive pads218, interconnect structure108, and/or interconnect structure208. Bonding pads128or bonding pads228that are completely isolated electrically may be considered “dummy” conductive features in some cases. In some embodiments, one or more of the bonding pads128may be electrically connected to the interconnect structure108(e.g., similar to via bonding pads133B shown inFIG. 21), and one or more of the bonding pads228may be electrically connected to the interconnect structure208. In some embodiments, a bonding pad128connected to a conductive pad118may be bonded to a bonding pad228that is not connected to a conductive pad218. In some embodiments, the bonding pads128or the bonding pads228may have a tapered profile, with the largest width near the interface B. In some embodiments, the bonding pads128may have a different width or profile than the bonding pads228.

Turning toFIG. 23, a device package1100is shown. The device package1100is similar to device package1000, except that a third device structure300is bonded to the first device structure100in addition to the second device structure200. The third device structure300and the first device structure100may be bonded in a similar manner as described forFIG. 22. All such variations of forming device packages are contemplated within the scope of this disclosure. In some embodiments, a singulation process may be performed on the device package1000or device package1100after bonding.

FIGS. 24 through 28illustrate intermediate steps in the formation of a package1300including a device package1200, in accordance with some embodiments.FIG. 24illustrates a fourth device structure400and a fifth device structure500that have been bonded into a device package1200. The fourth device structure400and the fifth device structure500may be similar to device structures100,150,160,200, or300described previously, and the device package1200may be similar to device packages1000or1100described previously.

FIG. 24also illustrates a carrier substrate721with an adhesive layer723and a polymer layer725over the adhesive layer723. In some embodiments, the carrier substrate721includes, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate721may be planar in order to accommodate an attachment of semiconductor devices such as the device package1200. The adhesive layer723is placed on the carrier substrate721in order to assist in the adherence of overlying structures (e.g., the polymer layer725). In some embodiments, the adhesive layer723may include a light to heat conversion (LTHC) material or an ultra-violet glue which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The adhesive layer723may be placed onto the carrier substrate721in a semi-liquid or gel form, which is readily deformable under pressure.

The polymer layer725is placed over the adhesive layer723and is utilized in order to provide protection to, e.g., the device package1200. In some embodiments, the polymer layer725may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may alternatively be utilized. The polymer layer725may be placed using, e.g., a spin-coating process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used. The device package1200is attached onto the polymer layer725. In some embodiments, the device package1200may be placed using, e.g. a pick-and-place process. However, any suitable method of placing the device package1200may be utilized.

In some embodiments, through-vias such as through-dielectric vias (TDVs)727are formed over the polymer layer725. In some embodiments, a seed layer (not shown) is first formed over the polymer layer725. The seed layer is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. In some embodiments, the seed layer may include a layer of titanium about 500 Å thick followed by a layer of copper about 3,000 Å thick. The seed layer may be created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials. Once the seed layer is formed, a photoresist (not shown) may be formed and patterned over the seed layer. The TDVs727are then formed within the patterned photoresist. In some embodiments, the TDVs727include one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In some embodiments, an electroplating process is used wherein the seed layer and the photoresist are submerged or immersed in an electroplating solution. Once the TDVs727have been formed using the photoresist and the seed layer, the photoresist may be removed using a suitable removal process. In some embodiments, a plasma ashing process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist may expose the underlying portions of the seed layer. Once the TDVs727have been formed, exposed portions of the seed layer are then removed, for example, using a wet or dry etching process. The TDVs727may be formed to a height of between about 180 μm and about 200 μm, with a critical dimension of about 190 μm and a pitch of about 300 μm.

FIG. 25illustrates an encapsulation of the device package1200and the TDVs727with an encapsulant729. The encapsulant729may be a molding compound such as a resin, polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like.FIG. 26illustrates a thinning of the encapsulant729in order to expose the TDVs727and the device package1200. The thinning may be performed, e.g., using a CMP process or another process.

FIG. 27illustrates a formation of a redistribution structure800with one or more layers over the encapsulant729. In some embodiments, the redistribution structure800may be formed by initially forming a first redistribution passivation layer801over the encapsulant729. In some embodiments, the first redistribution passivation layer801may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, such as a low temperature cured polyimide, may alternatively be utilized. The first redistribution passivation layer801may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 17 μm, such as about 7 μm, although any suitable method and thickness may alternatively be used.

Once the first redistribution passivation layer801has been formed, first redistribution vias803may be formed through the first redistribution passivation layer801in order to make electrical connections to the device package1200and the TDVs727. In some embodiments the first redistribution vias803may be formed by using a damascene process, a dual damascene process, or another process. After the first redistribution vias803have been formed, a first redistribution layer805is formed over and in electrical connection with the first redistribution vias803. In some embodiments the first redistribution layer805may be formed by initially forming a seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first redistribution layer805is desired to be located.

Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the seed layer through a deposition process such as plating. The conductive material may be formed to have a thickness of between about 1 μm and about 10 μm, such as about 4 μm. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the first redistribution layer805.

After the first redistribution layer805has been formed, a second redistribution passivation layer807may be formed and patterned to help isolate the first redistribution layer805. In some embodiments the second redistribution passivation layer807may be similar to the first redistribution passivation layer801, such as by being a positive tone PBO, or may be different from the first redistribution passivation layer801, such as by being a negative tone material such as a low-temperature cured polyimide. The second redistribution passivation layer807may be placed to a thickness of about 7 μm. Once in place, the second redistribution passivation layer807may be patterned to form openings using, e.g., a photolithographic masking and etching process or, if the material of the second redistribution passivation layer807is photosensitive, exposing and developing the material of the second redistribution passivation layer807. However, any suitable material and method of patterning maybe utilized.

After the second redistribution passivation layer807has been patterned, a second redistribution layer809may be formed to extend through the openings formed within the second redistribution passivation layer807and make electrical connection with the first redistribution layer805. In some embodiments the second redistribution layer809may be formed using materials and processes similar to the first redistribution layer805. For example, a seed layer may be applied and covered by a patterned photoresist, a conductive material such as copper may be applied onto the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In some embodiments the second redistribution layer809is formed to a thickness of about 4 μm. However, any suitable material or process of manufacture may be used.

After the second redistribution layer809has been formed, a third redistribution passivation layer811is applied over the second redistribution layer809in order to help isolate and protect the second redistribution layer809. In some embodiments the third redistribution passivation layer811may be formed of similar materials and in a similar fashion as the second redistribution passivation layer807to a thickness of about 7 μm. For example, the third redistribution passivation layer811may be formed of PBO or a low-temperature cured polyimide that has been applied and patterned as described above with respect to the second redistribution passivation layer807. However, any suitable material or process of manufacture may be utilized.

After the third redistribution passivation layer811has been patterned, a third redistribution layer813may be formed to extend through the openings formed within the third redistribution passivation layer811and make electrical connection with the second redistribution layer809. In some embodiments the third redistribution layer813may be formed using materials and processes similar to the first redistribution layer805. For example, a seed layer may be applied and covered by a patterned photoresist, a conductive material such as copper may be applied onto the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In some embodiments the third redistribution layer813is formed to a thickness of 5 μm. However, any suitable material or process of manufacture may be used.

After the third redistribution layer813has been formed, a fourth redistribution passivation layer815may be formed over the third redistribution layer813in order to help isolate and protect the third redistribution layer813. In some embodiments the fourth redistribution passivation layer815may be formed of similar materials and in a similar fashion as the second redistribution passivation layer807. For example, the fourth redistribution passivation layer815may be formed of PBO or a low-temperature cured polyimide that has been applied and patterned as described above with respect to the second redistribution passivation layer807. In some embodiments the fourth redistribution passivation layer815is formed to a thickness of about 8 μm. However, any suitable material or process of manufacture may be utilized.

In other embodiments, the redistribution vias and redistribution layers of the redistribution structure800may be formed using a damascene process, such as a dual-damascene process. For example, a first redistribution passivation layer may be formed over the encapsulant729. The first redistribution passivation layer is then patterned using one or more photolithographic steps to form both openings for vias and openings for conductive lines within the first redistribution passivation layer. A conductive material may be formed in the openings for vias and the openings for conductive lines to form the first redistribution vias and the first redistribution layer. Additional redistribution passivation layers may be formed over the first redistribution passivation layer, and additional sets of redistribution vias and conductive lines may be formed in the additional redistribution passivation layers as described for the first redistribution passivation layer, forming the redistribution structure800. This or other techniques may be used to form the redistribution structure800.

FIG. 27additionally illustrates a formation of underbump metallizations819and third external connectors817to make electrical contact with the third redistribution layer813. In some embodiments the underbump metallizations819may each comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the underbump metallizations819. Any suitable materials or layers of material that may be used for the underbump metallizations819are fully intended to be included within the scope of the embodiments.

In some embodiments, the underbump metallizations819are created by forming each layer over the third redistribution layer813and along the interior of the openings through the fourth redistribution passivation layer815. The forming of each layer may be performed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may be used depending upon the desired materials. The underbump metallizations819may be formed to have a thickness of between about 0.7 μm and about 10 μm, such as about 5 μm.

In some embodiments the third external connectors817may be placed on the underbump metallizations819and may be a ball grid array (BGA) which comprises a eutectic material such as solder, although any suitable materials may alternatively be used. In some embodiments in which the third external connectors817are solder balls, the third external connectors817may be formed using a ball drop method, such as a direct ball drop process. In another embodiment, the solder balls may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow in order to shape the material into the desired bump shape. Once the third external connectors817have been formed, a test may be performed to ensure that the structure is suitable for further processing.

FIG. 28illustrates a bonding of a package700to the TDVs727through the polymer layer725. Prior to bonding the package700, the carrier substrate721and the adhesive layer723are removed from the polymer layer725. The polymer layer725is also patterned to expose the TDVs727. In some embodiments, the polymer layer725may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated) is first deposited over the polymer layer725. Once protected, a laser is directed towards those portions of the polymer layer725which are desired to be removed in order to expose the underlying TDVs727. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ, and a drill angle of about 0 degree (perpendicular to the polymer layer725) to about 85 degrees to normal of the polymer layer725. In some embodiments the patterning may be formed to form openings over the TDVs727to have a width of between about 100 μm and about 300 μm, such as about 200 μm.

In another embodiment, the polymer layer725may be patterned by initially applying a photoresist (not individually illustrated) to the polymer layer725and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the polymer layer725are removed with, e.g., a dry etch process. However, any other suitable method for patterning the polymer layer725may be utilized.

In some embodiments, the package700includes a substrate702and one or more stacked dies710(710A and710B) coupled to the substrate702. Although one set of stacked dies710(710A and710B) is illustrated, in other embodiments, a plurality of stacked dies710(each having one or more stacked dies) may be disposed side-by-side and be coupled to a same surface of the substrate702. The substrate702may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate702may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate702is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate702.

The substrate702may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the package700. The devices may be formed using any suitable methods.

The substrate702may also include metallization layers or conductive vias (not shown). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate702is substantially free of active and passive devices.

The substrate702may have bond pads704on a first side of the substrate702to couple to the stacked dies710, and bond pads706on a second side of the substrate702, the second side being opposite the first side of the substrate702, to couple to the external connections901. In some embodiments, the bond pads704and706are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate702. The recesses may be formed to allow the bond pads704and706to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads704and706may be formed on the dielectric layer. In some embodiments, the bond pads704and706include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads704and706may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads704and706is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In an embodiment, the bond pads704and bond pads706are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the bond pads704and706. Any suitable materials or layers of material that may be used for the bond pads704and706are fully intended to be included within the scope of the current application. In some embodiments, the conductive vias extend through the substrate702and couple at least one of the bond pads704to at least one of the bond pads706.

In the illustrated embodiment, the stacked dies710are coupled to the substrate702by wire bonds712, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies710are stacked memory dies. For example, the stacked dies710may be memory dies such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.

The stacked dies710and the wire bonds712may be encapsulated by a molding material714. The molding material714may be molded on the stacked dies710and the wire bonds712, for example, using compression molding. In some embodiments, the molding material714is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing process may be performed to cure the molding material714. The curing process may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the stacked dies710and the wire bonds712are buried in the molding material714, and after the curing of the molding material714, a planarization step, such as a grinding, is performed to remove excess portions of the molding material714and provide a substantially planar surface for the package700.

In some embodiments, external connections901may be formed to provide an external connection between the package700and, e.g., the TDVs727. The external connections901may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In some embodiments in which the external connections901are tin solder bumps, the external connections901may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape.

Once the external connections901have been formed, the external connections901are aligned with and placed over the TDVs727, and a bonding is performed. For example, in some embodiments in which the external connections901are solder bumps, the bonding process may comprise a reflow process whereby the temperature of the external connections901is raised to a point where the external connections901will liquefy and flow, thereby bonding the package700to the TDVs727once the external connections901resolidify. An encapsulant903may be formed to encapsulate and protect the package700. The encapsulant903may extend between the polymer layer725and the package700and may be an underfill in some embodiments. In this manner, a package1300may be formed.

Embodiments may achieve advantages. By using a planarization stop layer over the conductive pads, the planarization process may be stopped near the top surface of the conductive pads. This can enable the formation of a thinner surface dielectric layer (e.g., “bonding oxide”). By reducing the thickness of the surface dielectric layer, the overall thickness of a package containing the device may be reduced. Additionally, the thinner surface dielectric layer provides improved thermal conduction and thus can improve the thermal performance of the device.

In an embodiment, a device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads. In an embodiment, the device includes an etch stop layer extending over the planarization stop layer, the surface dielectric layer on the etch stop layer. In an embodiment, the device includes a first dielectric layer between the planarization stop layer and the etch stop layer. In an embodiment, the multiple bonding pads extend through the planarization stop layer and the etch stop layer. In an embodiment, the planarization stop layer includes silicon carbide. In an embodiment, the surface dielectric layer has a thickness between 6 μm and 8 μm. In an embodiments, the device includes a second dielectric layer between the interconnect structure and the multiple first conductive pads, wherein the planarization stop layer extends over a top surface of the second dielectric layer. In an embodiment, the device includes multiple second conductive pads over the interconnect structure and includes multiple second bonding pads within the surface dielectric layer and connected to the multiple second conductive pads, wherein the second conductive pads are isolated from the interconnect structure. In an embodiment, the multiple first conductive pads include aluminum.

In an embodiment, a method includes forming a first metal line in an interconnect structure, forming an insulating layer over the interconnect structure, forming a conductive element over the insulating layer, the conductive element extending through the insulating layer to the first metal line, forming a first stop layer extending over the insulating layer and extending over sidewalls and a top surface of the conductive element, forming a second insulating layer over the first stop layer, performing a planarization process on the second insulating layer using the first stop layer as a planarization stop layer, forming a second stop layer over the first stop layer, wherein the second stop layer physically contacts a top surface of the second insulating layer and physically contacts a top surface of the first stop layer, forming a bonding oxide layer over the second stop layer, and forming a first bonding pad in the bonding oxide layer. In an embodiment, after performing the planarization process, a first thickness of the first stop layer over the insulating layer is greater than a second thickness of the first stop layer over the conductive element. In an embodiment, forming a bonding pad in the bonding oxide layer includes etching an opening in the bonding oxide layer using the second stop layer as an etch stop. And etching an opening in the first stop layer to expose the conductive element. In an embodiment, forming a bonding pad in the bonding oxide layer includes etching an opening in the bonding oxide layer to expose the second insulating layer, using the second stop layer as an etch stop. In an embodiment, the method includes extending the opening in the bonding oxide layer through the second insulating layer to expose a second metal line in the interconnect structure.

In an embodiment, a device includes an interconnect structure over a semiconductor substrate, multiple conductive pads over and connected to the interconnect structure, a first etch stop layer over the multiple conductive pads, a dielectric layer over the first etch stop layer and surrounding the conductive pads, a top surface of the dielectric layer coplanar with a top surface of the first etch stop layer, a bonding layer over the first etch stop layer and dielectric layer, and multiple bonding pads in the bonding layer, the multiple bonding pads connected to the multiple conductive pads. In an embodiment, the device includes a second etch stop layer over the first etch stop layer and the dielectric layer. In an embodiment, the material of the second etch stop layer is the same as the material of the first etch stop layer. In an embodiment, the device includes a top package bonded to the multiple bonding pads and to the bonding layer. In an embodiment, the first etch stop layer extends on sidewalls of the conductive pads of the multiple conductive pads. In an embodiment, at least one bonding pad extends from above the multiple conductive pads to below the multiple conductive pads.