Integrally-formed splitter for multiple-path power amplifiers and methods of manufacture thereof

Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. 119(b) to European patent application No. 20305826.8, filed on Jul. 17, 2020.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to splitters with multiple-path power amplifiers and methods of manufacture thereof that can be utilized with single or multi-stage amplifiers such as Doherty power amplifiers or other suitable amplifier architectures.

BACKGROUND

A typical Doherty power amplifier (PA) includes a signal splitter to receive and divide an input radio frequency (RF) signal, a main amplifier to amplify a first signal from the splitter, a peaking amplifier to amplify a second signal from the splitter, a signal combiner to combine the amplified signals from the main and peaking amplifiers, and various impedance transformation and phase delay elements to ensure that the amplified signals are combined in phase, and that desirable impedances are present at various points within the Doherty PA The signal splitter and signal combiner are commonly implemented on a printed circuit board (PCB) substrate, and the main and peaking amplifiers are implemented using one or more discretely-packaged devices that are physically coupled to the PCB substrate.

In modern wireless 4G and 5G communication systems, the design of RF power amplifiers becomes more complicated. Some of these systems require the PA to operate at very low power output back-off (e.g., 8 to 12 decibels (dB)) for good linearity, while limiting signal compression associated with high peak-to-average power ratio signals and achieving high power added efficiency. Doherty PA and inverted Doherty PA configurations remain popular in wireless base stations. However, high levels of integration are desired to meet the stringent requirements of modern wireless standards, including providing wide instantaneous bandwidths and high efficiency.

DETAILED DESCRIPTION

Embodiments of the inventive subject matter include a monolithic (i.e., integrally formed in and/or on a single semiconductor die) power splitter that can be electrically coupled to inputs of a multiple-path power amplifier (e.g., Doherty amplifier), each path of the multiple-path power amplifier including a single-stage or multi-stage amplifier. The power splitter can be on a distinct die or combined with the multi-path amplifier on the same die. The power splitter can include a plurality of power splitter branches, each branch configurable to couple to an amplification path of the multi-path amplifier. Each power splitter branch can include an amplifier and adjustment element. The adjustment element can comprise a transmission line, a lumped-element delay circuit, or other suitable delay circuit. The amplifiers used in the power splitter branches can have symmetric or asymmetric gain, and can be configured for a specific frequency band or a range of frequency bands. In order to increase electrical isolation between power splitter branches, each branch can be configured to have similar or substantially equal phase delays (e.g., 90 degrees per branch or other suitable delay). An isolation impedance can also be added between power splitter branches to further increase electrical isolation between such branches.

Although the subject disclosure emphasizes utilization of the power splitter with a Doherty power amplifier, it will be appreciated that the power splitter described below can also be utilized with other suitable single-path or multiple-path amplifiers on the same die or separate dies. Accordingly, it is contemplated that the power splitter descriptions that follow are non-limiting illustrations.

The below-described and illustrated embodiments of Doherty amplifier ICs correspond to two-way Doherty amplifiers that include a main amplifier and one peaking amplifier. Although not explicitly illustrated, other embodiments may include “N-way” Doherty power amplifiers, where N>2, in which the number of peaking amplifiers equals N−1.

FIG.1is a simplified schematic of an integrated Doherty power amplifier100, in accordance with an example embodiment. Doherty amplifier100includes an input node102, an output node192, a power splitter104(or splitter), a main amplification path120, a peaking amplification path111, and a combining node structure190. A load196may be coupled to the combining node structure190(e.g., through an impedance transformer, not shown) to receive an amplified RF signal from amplifier100.

Doherty power amplifier100is considered to be a “two-way” Doherty power amplifier, which includes one main amplifier120and one peaking amplifier140. The main amplifier120provides amplification along a first amplification path110, and the peaking amplifier140provides amplification along a second amplification path111. In the embodiment depicted inFIG.1, the peaking amplifier140is “divided”, in that the amplification performed by the peaking amplifier140actually is performed by two, substantially identical, peaking amplifier portions140′,140″ (collectively referred to as peaking amplifier140) along two parallel and substantially identical amplification paths111′,111″ (collectively referred to as amplification path111). As will be explained in more detail in conjunction withFIG.2, the peaking amplification paths111′,111″ are physically located on opposite sides of the main amplification path110, according to an embodiment. In other embodiments, the peaking amplifier140may not be “divided”, and instead a single amplification path may be used for the peaking amplification path.

Although the main and peaking amplifiers120,140may be of equal size (e.g., in a symmetric Doherty configuration with a 1:1 main-to-peaking size ratio), the main and peaking amplifiers120,140may have unequal sizes, as well (e.g., in various asymmetric Doherty configurations). In an asymmetric two-way Doherty amplifier configuration, the peaking power amplifier140typically is larger than the main power amplifier120by some multiplier. For example, the peaking power amplifier140may be twice the size of the main power amplifier120so that the peaking power amplifier140has twice the current carrying capability of the main power amplifier120. Asymmetric main-to-peaking amplifier size ratios other than a 1:2 ratio may be implemented, as well.

Power splitter104is configured to divide the power of an input RF signal received at input node102into main and peaking portions of the input signal. Because the peaking amplifier140is implemented using two peaking amplifier portions140′,140″, as explained above, the peaking portion of the input signal actually consists of two peaking input signals. Accordingly, power splitter104is configured to divide the power of the input RF signal received at input node102into one main portion of the input signal and two peaking portions of the input signal. The main input signal is provided to the main amplification path120at power splitter output106, and the peaking input signals are provided to the peaking amplification paths111′,111″ at power splitter outputs107and108. During operation in a full-power mode when both the main and peaking amplifiers120,140(including140′ and140″) are supplying current to the load196, the power splitter104divides the input signal power between the amplification paths110,111′,111″.

For example, the power splitter104may divide the power equally, such that roughly one third of the input signal power is provided to each path110,111′,111″. This may be the case, for example, when Doherty amplifier100has an asymmetric Doherty amplifier configuration in which the peaking amplifier140is approximately twice the size of the main amplifier120(i.e., the Doherty amplifier100has an asymmetric configuration with a 1:2 main-to-peaking size ratio). With a 1:2 main-to-peaking size ratio, the combined size of the peaking amplifier portions140′,140″ is about twice the size of the main amplifier120, which may be achieved when each of amplifiers120,140′,140″ is about equal in size. Alternatively, the power splitter104may divide the power unequally, particularly when the Doherty amplifier100has an asymmetric configuration other than a 1:2 main-to-peaking size ratio, or when the Doherty amplifier100has a symmetric configuration. In the case of a symmetric Doherty amplifier configuration, the size of the peaking amplifier140is about equal to the size of the main amplifier120(i.e., the Doherty amplifier100has a symmetric configuration with a 1:1 main-to-peaking size ratio). With a 1:1 main-to-peaking size ratio, the combined size of the peaking amplifier portions140′,140″ is about equal to the size of the main amplifier120, which may be achieved when each of amplifiers140′,140″ is about half the size of amplifier120. In that case, the power splitter104may divide the power so that about half of the input signal power is provided to the main amplification path120at power splitter output106, and about on quarter of the input signal power is provided to each of the peaking amplification paths111′,111″ at power splitter outputs107and108.

Power splitter104includes an input node102, three branches181,182′,182″, and three output nodes106-108. In other embodiments, the power splitter104may include two branches and two output nodes (e.g., in the embodiment illustrated inFIG.5B), or more than three branches and output nodes. Each splitter branch181,182′,182″ of the power splitter104includes a pre-driver amplifier and corresponding adjustment element, which will be described below inFIGS.5A-5I. The pre-driver amplifier and adjustment element of each splitter branch181,182′,182″ amplifies a divided input RF signal supplied at the input node102with equal phase across the splitter branches181,182′,182″, and the divided signals produced at output nodes106-108are separately further amplified along the main and peaking amplification paths110,111′,111″. The amplified signals generated by the main and peaking amplification paths110,111′,111″ are then combined in phase at the combining node structure190. It is important that phase coherency between the main and peaking amplification paths110,111′,111″ is maintained across a frequency band of interest to ensure that the amplified main and peaking signals arrive in phase at the combining node structure190, and thus to ensure proper Doherty amplifier operation. In the Doherty amplifier configuration depicted inFIG.1(i.e., a non-inverted Doherty configuration, as described below), input phase delay circuits109′,109″ are coupled between power splitter outputs107and108and peaking amplifier inputs141′,141″. According to an embodiment, each input phase delay circuit109′,109″ applies about 90 degrees of phase delay to the peaking input signals before they are provided to the peaking amplifier portions140′,140″. For example, each input phase delay circuit109′,109″ may include a quarter wave transmission line, a lumped-element delay circuit, or another suitable type of delay element with an electrical length of about 90 degrees.

The pre-driver amplifier in each splitter branch181,182′,182″ includes a single power transistor (e.g., composed of one or multiple transistor fingers). The main amplifier120and the peaking amplifier portions140′,140″ can be configured to include a single power transistor or multiple cascaded power transistors for amplifying an RF signal conducted through the amplifiers120,140′,140″. As used herein, the term “transistor” means a field effect transistor (FET) or another type of suitable transistor. For example, a “FET” may be a metal-oxide-semiconductor FET (MOSFET), a laterally-diffused MOSFET (LDMOS FET), an enhancement-mode or depletion-mode high electron mobility transistor (HEMT), or another type of FET. According to various embodiments, each of the power transistors in the main and peaking amplifier portions120,140′,140″ may be implemented, for example, using a silicon-based FET (e.g., an LDMOS FET), a silicon-germanium (SiGe) based FET, or a III-V FET (e.g., a HEMT), such as a gallium nitride (GaN) FET (or another type of III-V transistor, including a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET).

According to an embodiment of the Doherty amplifier100, the main amplifier120is a two-stage amplifier, which includes a relatively low-power driver amplifier126and a relatively high-power final-stage amplifier130connected in a cascade arrangement between main amplifier input121and main amplifier output134. In the main amplifier cascade arrangement, an output127of the driver amplifier126is electrically coupled to an input129of the final-stage amplifier130. Similarly, each of the peaking amplifier portions140′,140″ is a two-stage amplifier, which includes a relatively low-power driver amplifier146′,146″ and a relatively high-power final-stage amplifier150′,150″ connected in a cascade arrangement between a peaking amplifier input141′,141″ and a peaking amplifier output154′,154″. In each peaking amplifier cascade arrangement, an output147′,147″ of the driver amplifier146′,146″ is electrically coupled to an input149′,149″ of the final-stage amplifier150′,150″.

In other embodiments, the main amplifier120and the peaking amplifier portions140′,140″ may include a single-stage amplifier (e.g., driver amplifiers126,146′,146″ may be excluded). In yet other embodiments, the power splitter104can be coupled to a Doherty amplifier100in which the main and peaking amplifier paths each have more than the two, cascade-coupled amplification stages shown inFIG.1. Input and inter-stage impedance matching networks122,142′,142″,128,148′,148″ (IMN, ISMN) may be implemented, respectively, at the input125,145′,145″ of each driver amplifier126,146′,146″ and between each driver amplifier126,146′,146″ and each final-stage amplifier130,150′,150″. In each case, the matching networks122,142′,142″,128,148′,148″ may incrementally increase the circuit impedance toward the load impedance. In addition to providing signal amplification of an input signal at the input node102, each splitter branch181,182′,182″ of the power splitter104may also provide a 50 ohm (or other) input impedance suitable for the input node102and output impedance matching characteristics that may eliminate in whole or in part a need for matching networks IMN122,141′,141″ of the main amplifier120and the peaking amplifier portions140′,140″, respectively.

During operation of Doherty amplifier100, the main amplifier120is biased to operate in class AB mode, and the peaking amplifier140typically is biased to operate in class C mode. In some configurations, the peaking amplifier140may be biased to operate in class B or deep class B modes. In an embodiment, the amplifier of each splitter branch181,182′,182″ may also be biased to operate according to the same class mode or a suitable class mode of operation in conjunction with the class modes utilized by the main amplifier120and the peaking amplifier portions140′,140″, respectively. At low power levels, where the power of the input signal at node102is lower than the turn-on threshold level of peaking amplifier140, the amplifier100operates in a low-power (or back-off) mode in which the main amplifier120is the only amplifier supplying current to the load196. When the power of the input signal exceeds a threshold level of the peaking amplifier140, the amplifier100operates in a high-power mode in which the main amplifier120and the peaking amplifier140both supply current to the load196.

At this point, the peaking amplifier140provides active load modulation at combining node structure190, allowing the current of the main amplifier120to continue to increase linearly. As will be explained in more detail in conjunction withFIG.2, later, gate biasing of the main and peaking amplifiers120,140is performed using one or more resistor-divider gate bias circuits170,170′,170″ (e.g., resistor-divider gate bias circuits270,270′,270″,FIG.2), in an embodiment, where each resistor-divider gate bias circuit170,170′,170″ includes at least one resistor173,174,173′,173″,174′,174″ electrically coupled between a gate bias voltage input170,170′,170″ and an input125,129,145′,145″,149′,149″ (e.g., a gate terminal) of each amplifier126,130,146′,146″,150′,150″. Although not shown inFIG.1, the amplifier of each splitter branch181,182′,182″ may utilize the same resistor-divider gate bias circuits170,170′,170″ or other suitable resistor-divider circuits utilized by the main amplifier120and the peaking amplifier portions140′,140″, respectively.

Doherty amplifier100has a “non-inverted” load network configuration. In the non-inverted configuration, the input circuit is configured so that the input signals supplied to the peaking amplifier portions140′,140″ are delayed by 90 degrees with respect to the input signal supplied to the main amplifier120at the center frequency of operation, fo, of the amplifier100. To ensure that the main and peaking input RF signals arrive at the main and peaking amplifiers120,140,140″ with about 90 degrees of phase difference, as is fundamental to proper Doherty amplifier operation, input phase delay circuits109′,109″ each apply about 90 degrees of phase delay to the peaking input signals before they are provided to the peaking amplifier portions140′,140″, as described above.

To compensate for the resulting 90 degree phase delay difference between the main and peaking amplification paths110,111′,111″ at the inputs of amplifiers120,140′,140″ (i.e., to ensure that the amplified signals arrive in phase at the combining node structure190), an output phase delay circuit136is configured to apply about a 90 degree phase delay to the signal between the output of main amplifier120and the combining node structure190.

Alternate embodiments of Doherty amplifiers may have an “inverted” load network configuration. In such a configuration, the amplifier is configured so that an input signal supplied to the main amplifier120is delayed by about 90 degrees with respect to the input signals supplied to the peaking amplifier portions140′,140″ at the center frequency of operation, fo, of the amplifier100, and output phase delay circuits are configured to apply about a 90 degree phase delay to the signals between the outputs of the peaking amplifier portions140′,140″ and the combining node structure190.

Doherty amplifier100is “integrated,” as that term is used herein, because at least the main amplifier120(e.g., including the driver amplifier122and the final-stage amplifier130), the peaking amplifier140(including the driver amplifiers146′,146″ and the final-stage amplifiers150′,150″), and the combining node structure190are integrally- and monolithically-formed in one single IC die101(e.g., die201,FIG.2), which may be referred to herein as an “integrated Doherty amplifier die.” In an alternate embodiment, the combining node structure190may be implemented separately from the IC die that includes the main amplifier120and the peaking amplifier140. According to an embodiment, all or portions of the input and inter-stage impedance matching networks122,142′,142″,128,148′,148″ also may be integrally- and monolithically-formed in the same IC die (e.g., die201,FIG.2).

Alternatively, all or portion of the input impedance matching networks122,142′,142″ may be implemented in one or more components that are distinct from the IC die that includes the main and peaking amplifiers120,140. According to a further embodiment, the input node102, power splitter104, and output node192also are integrally- and monolithically-formed in the same IC die (e.g., die201,FIG.2) as the main and peaking amplifiers120,140. In an alternate embodiment, the input node102and power splitter104may be implemented in one or more components that are distinct from the IC die that includes the main and peaking amplifiers120,140. According to another further embodiment, the resistor-divider bias circuits170,170′,170″ also are integrally- and monolithically-formed in the same IC die (e.g., die201,FIG.2) as the main and peaking amplifiers120,140and the combining node structure190, although biasing may be performed by non-integrated circuits and structures in other embodiments.

FIG.2is a top view of a Doherty power amplifier IC200(or “Doherty IC”), in accordance with an example embodiment. For enhanced understanding,FIG.2should be viewed simultaneously withFIG.3, which is a side, cross-sectional view of the Doherty IC200ofFIG.2along line3-3. As used herein, the terms “integrated circuit die” and “IC die” mean a single, distinct semiconductor die (or semiconductor substrate) within which one or more circuit components (e.g., transistors, passive devices, and so on) are integrally-formed and/or directly physically connected to produce a monolithic structure.

Doherty IC200includes substantially an entire Doherty amplifier (e.g., Doherty amplifier100,FIG.1) integrally- and monolithically-formed in and on a single semiconductor die201, where the semiconductor die has a substantially rectangular periphery defined by opposed input and output sides210,211(e.g., bottom and top sides in the orientation ofFIG.2) and opposed left and right sides212,213that extend between the input and output sides. In the specific embodiment illustrated inFIG.2, Doherty amplifier IC200includes the following circuitry integrally- and monolithically-formed in and on semiconductor die201: an input terminal202(e.g., input node102,FIG.1), a power splitter204(e.g., power splitter104,FIG.1), input phase delay circuits209′,209″ (e.g., input phase delay circuits109′,109″,FIG.1), a two-stage main amplifier220(e.g., main amplifier120,FIG.1), a divided peaking amplifier consisting of first and second peaking amplifier portions240′,240″ (e.g., peaking amplifier portions140′,140″,FIG.1), an output phase delay circuit236(e.g., output phase delay circuit136,FIG.1), a combining node structure290(e.g., combining node structure190,FIG.1), and resistor-divider bias circuits270,270′,270″ (e.g., resistor-divider bias circuits170,170′,170″,FIG.1).

In various alternate embodiments, one or more of the input terminal202, power splitter204, input phase delay circuits209′,209″, and/or resistor-divider gate bias circuits270,270′,270″ may be implemented using circuitry and/or on substrates that are physically distinct from the semiconductor die201in and on which the remaining portions of the Doherty amplifier are formed. Although not shown inFIG.2, the power splitter204can share the same resistor-divider gate bias circuits270,270′,270″ or other suitable bias circuits utilized by the main amplifier220and the peaking amplifier portions240′,240″, respectively.

As seen most clearly inFIG.3, the semiconductor die201includes a base semiconductor substrate310and a plurality of build-up layers312over a top surface of the base semiconductor substrate310. In a particular example embodiment, the base semiconductor substrate310is a high-resistivity silicon substrate (e.g., a silicon substrate having bulk resistivity in a range of about 1000 ohm/centimeter (cm) to about 100,000 ohm/cm or greater). Alternatively, the base semiconductor substrate310may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a GaAs substrate having bulk resistivity up to 108ohm/cm), or another suitable high-resistivity substrate. In still other alternate embodiments, the base semiconductor substrate310may be any of multiple variants of a GaN substrate or other III-V semiconductor substrates.

The plurality of build-up layers312may include, for example, a plurality of interleaved dielectric layers, patterned conductive layers, and other conductive structures (e.g., conductive polysilicon structures). Portions of different patterned conductive layers and structures are electrically coupled with conductive vias (e.g., via332). Further, conductive through substrate vias (TSVs) (e.g., TSV348) may provide conductive paths between the top and bottom surfaces of the base semiconductor substrate310. The TSVs may or may not be lined with dielectric material to insulate the TSVs from the base semiconductor substrate310. According to an embodiment, a conductive layer328on the bottom surface of the base semiconductor substrate310functions as a ground node for the Doherty IC200. Although not shown inFIG.3, but as indicated inFIG.6, when the Doherty IC200ultimately is packaged, the conductive layer328may be physically and electrically coupled to a ground node of a package substrate (e.g., flange630,FIG.6).

In the below description of the Doherty IC200, reference will be made to various circuits that include capacitors, inductors, and/or resistors. The capacitors may be, for example, integrated metal-insulator-metal (MIM) capacitors formed within the build-up layers312, and/or small chip capacitors (discrete capacitors) coupled to the top surface of the die201, in various embodiments. The resistors may be, for example, integrated resistors (e.g., formed from polysilicon within the build-up layers312), or small discrete resistors coupled to the top surface of the die201. The inductors may be integrated spiral inductors (e.g., formed from patterned conductive layers and vias within the build-up layers312), or they may be discrete inductors or inductances formed from wirebonds or other inductive components.

In the embodiment ofFIGS.2and3, each of the main amplifier220and the peaking amplifier portions240′,240″ include a cascade arrangement of two power transistors, including a relatively low-power driver amplifier transistor226,246′,246″ (e.g., driver amplifiers126,146′,146″,FIG.1) and a relatively high-power final-stage amplifier transistor230,250′,250″ (e.g., final-stage amplifiers130,150′,150″,FIG.1). In other embodiments, the driver amplifier transistors226,246′,246″ may be excluded, and the main amplifier220and peaking amplifier portions240′,240″ may include just the high-power final-stage amplifier transistor230,250′,250″. The description herein refers to each transistor as including a control terminal and two current-conducting terminals. For example, using terminology associated with FETs, a “control terminal” refers to a gate terminal of a transistor, and first and second current-conducting terminals refer to drain and source terminals (or vice versa) of a transistor. Although the below description may use terminology commonly used in conjunction with FET devices, the various embodiments are not limited to implementations the utilize FET devices, and instead are meant to apply also to implementations that utilize bipolar junction transistors (BJT) devices or other suitable types of transistors.

Each transistor226,246′,246″,230,250′,250″ includes a gate terminal225,229,245′,245″,249′,249″ (or control terminal), a drain terminal227,231,247′,247″,251′,251″ (or first current-carrying terminal), and a source terminal (or second current-carrying terminal), not numbered. In a specific embodiment, each transistor226,246′,246″,230,250′,250″ is an LDMOS FET, which includes an active area disposed between gate and drain terminals. Each active area includes a plurality of elongated, parallel-aligned, and interdigitated drain regions and source regions, where each drain region and each source region is a doped semiconductor region formed in the base semiconductor substrate310. Due to their elongated shapes, each set of adjacent drain and source regions, along with an associated gate structure, may be referred to as a “transistor finger,” and each transistor226,246′,246″,230,250′,250″ includes a plurality of parallel transistor fingers within the active area of the transistor (indicated with vertical lines inFIG.2).

A variably-conductive channel (and, in some embodiments, a drain drift region) is present between adjacent source and drain regions. Conductive (e.g., polysilicon or metal) gate structures formed over the base semiconductor substrate310are coupled to and extend from each gate terminal225,229,245′,245″,249′,249″ over and along the channel regions. Similarly, additional conductive (e.g., polysilicon) drain structures formed over the base semiconductor substrate310are coupled to and extend from each drain terminal227,231,247′,247″,251′,251″ over and along the drain regions. The source regions are electrically coupled to conductive (e.g., polysilicon or metal) source contacts, which in turn are coupled to conductive TSVs (e.g., TSV348,FIG.3) that extend through the base semiconductor substrate310to connect with conductive layer328on the bottom surface of the base semiconductor substrate310. Voltages applied to the gate terminals225,229,245′,245″,249′,249″ during operation modulate the conductivity of the variably-conductive channels, thus enabling current flow between source and drain regions (or ultimately between conductive layer328and each drain terminal227,231,247′,247″,251′,251″).

The circuitry integrated within and coupled to Doherty IC200will now be described in more detail. Referring again toFIG.2, the input terminal202(e.g., input node102,FIG.1), which is configured to receive an input RF signal for amplification, is electrically connected to a splitter input205(e.g., input105,FIG.1) of power splitter204through a conductive path implemented in the build-up layers312of the Doherty IC200. Input terminal202may include, for example, a conductive bondpad, which is exposed at the top surface of the die201, and which is configured for attachment of one or more wirebonds (e.g., wirebond650,FIG.6). Alternatively, die201may be a flip-chip die or the input terminal may be exposed at the bottom surface of the die201, in which case the input terminal202may consist of a conductive land or other type of connection. These alternate configurations also may apply to the other terminals (e.g., terminals271,271′, and284) of the Doherty IC200.

The power splitter204(e.g., power splitter104,FIG.1) is configured to divide the power of an input RF signal received at input terminal205into main and peaking portions of the input signal and to pre-amplify the main and peaking portions of the input signal. As described in conjunction withFIG.1, because the peaking amplifier is implemented using two peaking amplifier portions240′,240″, power splitter204has three branches, and is configured to divide the power of the input RF signal received at input terminal202into one main portion of the input signal and two peaking portions of the input signal. The main portion of the input signal and the peaking portions of the input signal each are pre-amplified along the three power splitter branches. Essentially, the power splitter includes a same number of branches as amplification paths. Thus, in an alternate embodiment in which the peaking amplifier is implemented using only a single amplifier path, the power splitter may include only two branches (e.g., as in the embodiment ofFIG.5B).

In the illustrated embodiment, the main input signal is produced at power splitter output206(e.g., output106,FIG.1), and the peaking input signals are produced at power splitter outputs207and208(e.g., outputs107and108,FIG.1). As also discussed previously, the power splitter204may divide and pre-amplify the power equally or unequally, depending on the relative sizes of the main amplifier220and the peaking amplifier portions240′,240″. In the embodiment ofFIG.2, the sizes of the main amplifier220and the peaking amplifier portions240′,240″ are approximately equal (i.e., the three amplifiers220,240′,240″ have a 1:1:1 size relationship, and the Doherty amplifier is an asymmetric amplifier with a 1:2 main-to-peaking ratio), and thus the power splitter204divides the input RF signal so that roughly one third of the pre-amplified input signal power is produced at each power splitter output206-208. In other embodiments, the sizes of the main amplifier220and the peaking amplifier portions240′,240″ may be unequal, in which case the power splitter204may produce amplified RF signals with unequal power.

Input terminal205has a 50 ohm input impedance, in an embodiment, although the input impedance may be less or greater than 50 ohms, as well. According to an embodiment, the power splitter204has a Wilkinson-based design with active elements (e.g., power transistors), and the power splitter204essentially divides and pre-amplifies the power of the input signal received at input205into three pre-amplified signals with equal phase at outputs206-208.

According to an embodiment, power splitter204is formed from a combination of pre-amplifier transistors and delay elements coupled to passive components that are integrally-formed in and/or coupled to Doherty IC200. In a more specific embodiment, power splitter204is a three-branch splitter, where each splitter branch (e.g., branches401-403,501-503,FIGS.4,5A) has a pre-amplifier coupled to an adjustment element. The adjustment element can correspond to a transmission line having a suitable electrical length, a CLC (capacitor-inductor-capacitor) topology, or combination thereof, as will be described in more detail later. The components of the adjustment element can be configured to have an impedance and phase that optimizes gain, power added efficiency (PAE) and electrical isolation between splitter branches401-403,501-503,FIGS.4,5A. To increase electrical isolation between the splitter branches401-403,501-503, the power splitter404,504can be configured so that each branch has an equal delay in relation to another one of the other branches401-403,501-503. Put another way, electrical isolation between branches can be increased as a first combined phase delay of a first branch (e.g.,401,501) approaches a second combined phase delay of a second branch (e.g.,402,502). The first combined delay corresponds to a sum of a first phase delay of a first amplifier (e.g.,423,523) and a second phase delay of a first adjustment element (e.g.,412,512) of the first branch (e.g.,401,501). Similarly, the second combined phase delay corresponds to a sum of a third phase delay of a second amplifier (e.g.,439″,539″) and a fourth phase delay of a second adjustment element (e.g.,414″,514″) of the second branch (e.g.,402,502).

In an example embodiment, electrical isolation can be substantially achieved by configuring each splitter branch401-403,501-503to have a combined phase delay of approximately 90 degrees. Suppose, for example, the amplifier of each splitter branch401-403,501-503is of a same size having approximately a same phase delay of 55 degrees. In this illustration each splitter branch401-403,501-503can be configured to have the same phase by utilizing an adjustment element with a phase delay of 35 degrees (totaling 90 degrees of phase delay per splitter branch). Electrical isolation between splitter branches401-403,501-503can also be achieved by configuring pairs of splitter branches (e.g.,401&403;401&402;402&403) to have a total sum that is at or near 180 degrees so that each splitter branch is at least substantially out of phase with each other and thereby electrically isolated. Such summations are illustrated by path pairs408,408′ and408″ shown, respectively, inFIG.4. Power splitter204,404and504ofFIGS.2,4,5Amay provide an advantage over conventional power splitters with only passive components (e.g., inductors, capacitors and/or resistors), in that the multiple-section topology of power splitter204,404and504can provide pre-amplification for a single or multi-stage amplifier (e.g., Doherty amplifier) with a better broadband response than a conventional one-section power splitter.

FIGS.4and5A, illustrate simplified schematic diagrams of integrated signal splitters404,504(e.g., splitter104,204,FIGS.1,2) suitable for use in Doherty IC200, in accordance with an example embodiment. Splitter404,504includes a splitter input terminal405,505(e.g., input105,205,FIGS.1,2) configured to receive an input RF signal, and three splitter branches401-403,501-503coupled between the input terminal405,505and splitter output terminals406,506,407,507,408,508(e.g., outputs106-108,206-208,FIGS.1,2).

As can be seen inFIGS.4and5A, each branch401-403,501-503of splitter404,504may include a filter circuit (each including inductor520,530,540and a capacitor522,532,542, for example), a pre-amplifier423,439′,439″,523,539′,539″, and an adjustment element412,414′,414″,512,514′,514″. Isolation resistors452-453,552-553are coupled between the branches401-403,501-503. Each pre-amplifier523,539′,539″ shown inFIG.5Acan correspond to one or more transistor fingers (herein referred to as transistor fingers523,539′,539″). As will be described in more detail in conjunction with the description ofFIGS.5B-5E, each transistor finger may be configured as a FET with gate, drain, and source terminals. Within each branch501-503, the filter circuit519(including an inductor520,530,540and a capacitor522,532,542) is coupled between the splitter input terminal405,505and the gate terminal(s) of the transistor finger(s) corresponding to the pre-amplifiers523,539′,539″.

Each of the filter circuits provided by the inductors520,530,540and capacitors522,532,542can serve as a low-pass filter, bandpass filter or high pass filter and/or input impedance matching circuit for signals applied at splitter input terminal505. Although not shown, pre-driver amplifiers423,439′,439″ can utilize similar filter circuits as those illustrated inFIG.5A. The adjustment elements414′,412,414″,512,514′,514″ can be implemented with transmission lines having a suitable electrical length, and/or a lumped-element equivalent such as a capacitor-inductor-capacitor (CLC) topology (e.g., CLC525,524,526for branch501, CLC535,534,536for branch502, or CLC545,544,546for branch503). It will be appreciated that the inductors520,530,540values and capacitors522,532,542values of each of the filter circuits of filter519can differ among the filter circuits. In an embodiment, the capacitor522,532,542may be implemented solely according to an inherent capacitance of the gate terminal of pre-amplifier523,539′,539″. In another embodiment, the capacitor522,532,542may be implemented from a combination of the gate terminal capacitance and other capacitors (not shown inFIG.5A) coupled to the gate terminal of pre-amplifier523,539′,539″ to adjust the capacitance to desired values.

The adjustment elements412,414′,414″,512,514′,514″ are configured in view of a phase delay and output impedance of each pre-driver amplifier423,439′,439″,523,539′,539″ to achieve at least in part an impedance match with the outputs of each pre-driver amplifier423,439′,439″,523,539′,539″ and an equal (or substantially equal) phase at the outputs of the splitter branches401-403,501-503, in an embodiment. In particular, when all pre-driver amplifiers423,439′,439″,523,539′,539″ impart the same delay to signals amplified by the pre-amplifiers, the adjustment elements412,414′,414″,512,514′,514″ each also may impart equal delays to those signals (which may or may not be the same as the adjustment elements412,414′,414″,512,514′,514″) to ensure that the cumulative delays applied through each branch401-403,501-503are substantially equal. Conversely, when one or more of the pre-driver amplifiers423,439′,439″,523,539′,539″ imparts different delays from each other, then the adjustment elements412,414′,414″,512,514′,514″ may impart different delays to ensure that the cumulative delays applied through each branch401-403,501-503are substantially equal.

Each inductor (e.g., inductors520,524,530,534,540,544, shown inFIG.5A) may be implemented, for example, as an integrated spiral inductor formed from patterned conductive layers and vias within the build-up layers of the die201(e.g., build-up layers312,FIG.3). In alternate embodiments, some or all of the inductors520,524,530,534,540,544may be implemented as discrete inductors or wirebond arrays coupled to the top surface of the die201. Each of the inductors520,524,530,534,540,544may have an inductance value in a range of about 4 nanohenries (nH) to about 9 nH when a center frequency of operation, fo, of the Doherty IC200is about 2.0 gigahertz (GHz), although the center frequency of operation and/or the inductance values may be lower or higher, as well. Other inductive values and center frequency of operation, fo, are also contemplated by the subject disclosure.

Capacitors525,535,545represent the parasitic drain-source capacitance of pre-amplifier transistors523,539′,539″, and thus are not actual physical components. Conversely, each of capacitors522,526,532,536,542,546may be an integrated MIM capacitor formed within the build-up layers of the die201(e.g., build-up layers312,FIG.3), and/or small chip capacitors (discrete capacitors) coupled to the top surface of the die201, in various embodiments. According to an embodiment, each capacitor510,526,536,546is a shunt capacitor, with a bottom electrode coupled to a ground reference using through substrate vias (TSVs) that extend through the base semiconductor substrate (e.g., substrate310,FIG.3) to a conductive layer (e.g., layer328,FIG.3) on the bottom surface of the die300. Each of the capacitors510,522,526,532,536,542,546may have a capacitance value in a range of about 0.5 picofarads (pF) to about 1.5 pF when a center frequency of operation of the amplifier is about 2.0 GHz, although the center frequency of operation and/or the capacitance values may be lower or higher, as well. Other capacitance values and center frequency of operation, fo, are also contemplated by the subject disclosure.

Referring also toFIGS.4and5A, each power splitter404,504also includes a plurality of resistors (e.g., resistors452-453,552-553,FIGS.4,5A), in an embodiment, and as will be described in more detail below. The resistors452-453,552-553may be, for example, integrated resistors (e.g., formed from polysilicon within the build-up layers of die/substrates201,582,587,592,597,FIGS.3,5B-5E), or small discrete resistors coupled to the top surface of the die201or substrate582,587,592,597. Each of the resistors452-453,552-553may have a resistance value in a range of about 50 ohms to about 250 ohms, although the resistance values may be lower or higher, as well.

Beginning at the splitter input terminal405,505, a first shunt capacitor410,510is electrically coupled between the input terminal405,505and a dividing node409,509for the three branches401-403,501-503. Each splitter branch401-403,501-503can be a three-section branch having an input impedance matching and/or filter section.

Although not shown inFIG.4, the shunt capacitor410can be coupled to the input impedance matching and/or filter section in each of branches401-403, respectively. In an embodiment, the input impedance matching and/or filter section can be included in the pre-driver amplifiers423,439′,439″. The adjustment elements412,414′,414″ can be implemented with transmission lines having an electrical length that achieves a combined phase delay for each of the splitter branches401-403that satisfies impedance matching of the pre-driver amplifier outputs and the electrical isolation conditions between paths408,408′,408″ as discussed earlier. Alternatively, as illustrated inFIG.5A, the adjustment elements412,414′,414″ can be implemented with CLC circuits that provide a desired impedance match and delay to achieve gain, PAE, and the electrical isolation conditions between paths408,408′,408″. Each adjustment element412,414′,414″ has a first terminal coupled to a drain terminal of the pre-driver amplifier423,439′,439″, and a second terminal coupled to an output terminal406-408. To provide further isolation between the splitter branches401-403, resistors452-453can be coupled between output terminals406-408.

In the embodiment ofFIG.5A, filter519can be implemented as impedance matching networks (in a CLC or pi-type topology) that are coupled respectively to amplifiers523,539′,539″ that are in turn coupled to CLC circuits512,514′,514″ in series between the splitter input terminal505and a splitter output terminal506-508. A first section of each branch501-503includes a matching network that is defined by the first shunt capacitor510, a first inductor520,530,540, and a second shunt capacitor522,532,542(which may correspond solely to the inherent gate capacitance of amplifiers523,539′,539″ or a capacitance based on the gate capacitance combined with other capacitors not shown inFIG.5A). Each first inductor520,530,540has a first terminal coupled to the input terminal505(or to dividing node509), and a second terminal coupled to an inter-section node511,513,515. Each second shunt capacitor522,532,542is electrically coupled between the inter-section node511,513,515and the ground reference. A second section of each branch501-503includes the amplifier523,539′,539″, which includes a control (gate) terminal coupled to the inter-section node511,513,515, a drain terminal coupled to CLC circuits512,514′,514″, and a source terminal coupled to the ground reference.

As shown inFIG.5A, the CLC circuit section corresponding to adjustment elements512,514′,514″ is defined by the second shunt capacitor525,535,545coupled to a ground reference, a second inductor524,534,544, and a third shunt capacitor526,536,546coupled to the ground reference. The second shunt capacitor525,535,545which may correspond solely to the inherent drain capacitance of amplifiers523,539′,539″ or a capacitance based on the drain capacitance combined with other capacitors not shown inFIG.5A. Each second inductor524,534,544has a first terminal coupled to the drain terminal of the amplifier523,539′,539″, and a second terminal coupled to an output terminal506-508. Each third shunt capacitor526,536,546is electrically coupled between an output terminal506-508and the ground reference. According to an embodiment, each first inductor520,530,540is significantly larger (e.g., between about 10 percent and 100 percent larger) in inductance value than each second inductor524,534,544. In alternate embodiments, the first and second inductors may have substantially identical inductance values, or each second inductor524,534,544may be significantly larger in inductance value than each first inductor520,530,540.

AlthoughFIGS.4and5Adepict multiple-section splitters404,504that can include three splitter sections (CLC, amplifier, CLC) in each branch401-403,501-503, alternate embodiments may include more than three (e.g., four, or more) sections or less than three (e.g., two) sections in each branch501-503. In addition, other alternate embodiments that include a single peaking amplifier may include only two branches (e.g., one branch for the main amplifier and one branch for the single peaking amplifier), as discussed in conjunction withFIG.5B. Still other alternate embodiments that include more than two peaking amplifier portions (or more than one divided peaking amplifier) may include more than three branches (e.g., one branch for the main amplifier and one branch for each peaking amplifier or peaking amplifier portion). AlthoughFIGS.4and5Adepict a particular integrated signal splitter configuration, other types or configurations of signal splitters may be used, in other embodiments.

FIGS.5B,5C,5D and5Edepict embodiments of pre-driver amplifiers580,585,590,595(e.g., pre-driver amplifiers423,439′,439″,523,539′,539″ of the power splitter404,504ofFIGS.4and5A), that are implemented using various transistor finger configurations, in accordance with various example embodiments. To simplify the illustration of the various configurations for the pre-driver amplifiers ofFIGS.4and5A, implementations of the adjustment elements or input filter circuits shown inFIGS.4and5Aare not depicted inFIGS.5B-5E. The adjustment elements or input filter circuits can be readily included on the same die as the pre-driver amplifiers shown inFIGS.5B-5Eor separate dies interconnected with the pre-driver amplifiers ofFIGS.5B-5E. With this in mind, each of the pre-amplifiers580,585,590,595are integrally formed in a semiconductor substrate582,587,592,597, such as a silicon, GaN, or other suitable substrate. Pre-amplifiers580,585,590,595have a plurality of gate manifolds, each corresponding to one or a combination of the splitter inputs. Pre-amplifiers580,585,590,595also have a plurality of drain manifolds, each coupling to a corresponding adjustment element.

Pre-amplifier580has a drain manifold572, which corresponds to a first amplifier output (path501ofFIG.5A) that couples to an adjustment element512, which in turn is configurable for coupling to a main amplifier path (not shown inFIG.5B), and drain manifold573, which corresponds to a second amplifier output (path502or503ofFIG.5A) that couples to an adjustment element514′ or514″ (seeFIG.5A) configurable for coupling to a peaking amplifier path (not shown). Pre-amplifiers585,590,595have drain manifolds575,576,578,579,584,586, which can correspond to first and second amplifier outputs (paths502and503ofFIG.5A) that each couple to a corresponding adjustment element514″,514′ configurable for coupling to corresponding first and second peaking amplifier paths (not shown), and drain manifolds574,577,583, which can correspond to a third amplifier output that couples to an adjustment element512configurable for coupling to a main amplifier path (not shown).

In some embodiments, the pre-amplifiers582,587,592,597may be integrally formed in the same semiconductor substrate as the multi-path amplifier to which the splitter couples to (e.g., substrate201,FIG.2). In other embodiments, the pre-amplifiers580,585,590,595may be formed in a separate semiconductor substrate independent from the substrate of the multi-path amplifier, where the separate semiconductor substrate is directly coupled to the multi-path amplifier semiconductor substrate, or is packaged as a surface-mount device that is coupled to the multi-path amplifier semiconductor substrate. As noted above, the illustrations ofFIGS.5B-5Erepresent transistor fingers without showing the adjustment elements412,414′,414″,512,514′,514″ ofFIGS.4and5A. To achieve an equal phase between splitter branch401-403,501-503, adjustment elements412,414′,414″,512,514′,514″ can be configured with a proper phase delay and with impedance matching characteristics for coupling to an output (drain manifold) terminal of the transistor fingers ofFIGS.5B-5E.

Each transistor finger (555,556,556′,557,558,558′,560,561,561′,561″,562,563,563′,563″) ofFIGS.5B-5BEincludes a gate terminal511,513,515(or control terminal), a drain terminal572′,573′,573″,574′,575′,576′,577′,578′,578″,579′,583′,584′,584″,586′ (or first current-carrying terminal), and a source terminal (or second current-carrying terminal), not numbered and not shown. In a specific embodiment, each transistor finger555,556,556′,557,558,558′,560,561,561′,561″,562,563,563′,563″ is an LDMOS FET, which includes an active area disposed between gate and drain terminals. As described previously, each active area includes a plurality of elongated, parallel-aligned, and interdigitated drain regions and source regions, where each drain region and each source region is a doped semiconductor region formed in the base semiconductor substrate.

A variably-conductive channel (and, in some embodiments, a drain drift region) is present between adjacent source and drain regions. Conductive (e.g., polysilicon or metal) gate structures formed over the base semiconductor substrate are coupled to and extend from each gate terminal511,513,515over and along the channel regions. Similarly, additional conductive (e.g., polysilicon) drain structures formed over the base semiconductor substrate are coupled to and extend from each drain terminal572′,573′,573″,574′,575′,576′,577′,578′,578″,579′,583′,584′,584″,586′ over and along the drain regions. The source regions are electrically coupled to conductive (e.g., polysilicon or metal) source contacts, which in turn are coupled to conductive TSVs that extend through the base semiconductor substrate to connect with a conductive layer on the bottom surface of the base semiconductor substrate. Voltages applied to the gate terminals511,513,515during operation modulate the conductivity of the variably-conductive channels, thus enabling current flow between source and drain regions (or ultimately between the conductive layer on the bottom surface and each drain terminal572′,573′,573″,574′,575′,576′,577′,578′,578″,579′,583′,584′,584″,586′. In the embodiments ofFIGS.5B-5E, the gate terminals of transistor fingers556,556′,561,561′,563,563′ are electrically connected together, while the gate terminals of transistor fingers555,557,558,558′,560,561″,562,563″ are electrically isolated from each other and electrically isolated from transistor fingers556,556′,561,561′,563,563′.

InFIG.5B, the drain terminal572′ of finger555is connected to a first drain manifold572, and the drain terminals573′,573″ of fingers556and556′ are electrically connected together with a second drain manifold573that is electrically isolated from the first drain manifold572. In the embodiment ofFIG.5B, each of the transistor fingers555,556,556′ has a same size (or length, or periphery). Accordingly, each of the transistor fingers555,556,556′ provides the same level of signal amplification. Because the drain terminals573′,573″ of fingers556and556′ are electrically connected with drain manifold573, during operation, the signal power at drain manifold573(which is provided to the peaking amplifier path) is about twice the signal power at drain manifold572(which is provided to the main amplifier path).

InFIG.5C, the drain terminal574′ of finger557is connected to a first drain manifold574, and the drain terminals575′ and576″ of fingers558and558′ are electrically connected to second and third drain manifolds575and576that are electrically isolated from the first drain manifold574and each other. In the embodiment ofFIG.5C, each of the transistor fingers557,558,558′ has a same size (or length, or periphery). Accordingly, each of the transistor fingers557,558,558′ provides the same level of signal amplification. Because the drain terminals575′,576′ of fingers558and558′ are electrically connected respectively with drain manifolds575and576, during operation, the combined signal power at drain manifolds575and576(which is provided to corresponding peaking amplifier paths) is about twice the signal power at drain manifold574(which is provided to the main amplifier path).

InFIG.5D, the drain terminal577′ of finger560is connected to a first drain manifold577, and the drain terminals578′,578″ and579′ of fingers561,561′ and561″ are electrically connected, respectively, to second and third drain manifolds578and579that are electrically isolated from the first drain manifold577and each other. In the embodiment ofFIG.5D, each of the transistor fingers560,561,561′,561″ has a same size (or length, or periphery). Accordingly, each of the transistor fingers560,561,561′,561″ provides the same level of signal amplification. Because the drain terminals578′,578″,579′ of fingers561,561′,561″ are electrically connected, respectively, with drain manifolds578and579, during operation, the combined signal power at drain manifolds578and579(which is provided to corresponding peaking amplifier paths) is about three-times the signal power at drain manifold577(which is provided to the main amplifier path).

InFIG.5E, the drain terminal583′ of finger562is connected to a first drain manifold583, and the drain terminals584′,584″ and586′ of fingers563,563′ and563″ are electrically connected, respectively, to second and third drain manifolds584and586that are electrically isolated from the first drain manifold583and each other. In the embodiment ofFIG.5E, transistor finger562, transistor fingers563,563′ (of a same size or length, or periphery), and transistor finger563″ differ from each other in size and amplification. In an embodiment, the combination of transistor fingers563,563′ is three-times the size of transistor finger562and six-times the size of transistor finger563″, thereby providing a signal amplification ratio of 6:2:1.

In an asymmetric Doherty amplifier configuration as described earlier, the peaking amplification path may be larger in size (i.e., higher current carrying capability) than the main amplification path. For example, a Doherty amplifier with a 2:1 peaking-to-main power ratio has a peaking amplification path that is twice the size of the main amplification path. To achieve a 2:1 ratio in a Doherty amplifier having a single peaking path that is twice the size of a main amplification path, the power splitter404,504can be configured to use the 2:1 finger transistor ratio ofFIG.5B. In this configuration, a main splitter branch (e.g.,401-501) of the power splitter404,504can utilize one or more first transistor fingers (e.g., transistor finger555) to supply a first portion (e.g., one-third) of the input signal power to the main amplification path of the Doherty amplifier, while a peaking splitter branch (e.g.,402-502or403-503) of the power splitter404,504can utilize one or more second transistor fingers (e.g., transistor fingers556,556′) to supply a second portion (e.g., two-thirds) of the input signal power to the single peaking amplification path of the Doherty amplifier.

To achieve a 2:1 ratio in a Doherty amplifier having split peaking paths that together add up to twice the size of a main amplification path, the power splitter404,504can be configured to use the 1:1:1 finger transistor ratio ofFIG.5C. In this configuration, a main splitter branch (e.g.,401-501) of the power splitter404,504can utilize one or more first transistor fingers (e.g., transistor finger557) to supply a first portion (e.g., one-third) of the input signal power to the main amplification path of the Doherty amplifier. Additionally, a first peaking branch (e.g.,402-502) of the power splitter404,504can utilize one or more second transistor fingers (e.g., transistor finger558) to supply a second portion (e.g., one-third) of the input signal power to a first peaking amplification path of the Doherty amplifier, while a second peaking branch (e.g.,403-503) of the power splitter404,504can utilize the single transistor finger558′ to supply one-third of the input signal power to a second peaking amplification path of the Doherty amplifier.

The finger transistors ofFIGS.5D-5Ecan be used by the power splitter404,504to support other asymmetric Doherty amplifier configurations with power ratios such as 2:1:1 and 6:2:1, respectively. For example, an asymmetric Doherty amplifier can be configured with split peaking amplification paths in which one peaking amplification path is twice the size of the other peaking amplification path and twice the size of the main amplification path (hence, a 2:1:1 power ratio). To achieve a 2:1:1 asymmetric Doherty amplifier, the main splitter branch401,501of the power splitter404,504can be configured with the single transistor finger560ofFIG.5Dto supply one-quarter the input signal power to the main amplification path. Similarly, a first peaking splitter branch402,502can be configured to use the single transistor finger561″ to supply one-quarter the input signal power to the smaller peaking amplification path of the Doherty amplifier, while the other peaking splitter branch403,503can be configured to use dual transistor fingers561,561′ (with a shared output (drain) terminal) to supply half the input signal power to the larger peaking amplification path. Utilizing similar principles, the splitter branches401-501,402-502,403-503of the power splitter404,504can be configured to use the finger transistors562,563,563′,563″ to support an asymmetric Doherty configuration having a power ratio of 6:2:1.

FIGS.5G-5Hdepict alternative embodiments of the power splitters ofFIGS.4and5A, respectively, in accordance with example embodiments.FIG.5Gcombines a passive Wilkinson splitter460at the inputs of an active splitter470. In this configuration, the two resistors R1of the passive Wilkinson splitter460serve to provide isolation between the branches401-403of the passive Wilkinson splitter460. The passive Wilkinson splitter460can be configured so that path461has a total phase of 180 degrees (90 degrees for branch402plus 90 degrees for branch403) which results in branches402-403of the passive Wilkinson splitter460being out-of-phase and thereby electrically isolated. Similarly, the passive Wilkinson splitter460can be configured so that path461′ has a total phase of 180 degrees (90 degrees for branch402plus 90 degrees for branch401) which results in branches401and402of the passive Wilkinson splitter460being out-of-phase and thereby electrically isolated. Also, the passive Wilkinson splitter460can be configured so that path461″ has a total phase of 180 degrees (90 degrees for branch401plus 90 degrees for branch403) which results in branches401and403of the passive Wilkinson splitter460being out-of-phase and thereby electrically isolated. The passive Wilkinson splitter460can also be configured to match at least in part the impedance of the input terminal405. The capacitors shown in the passive Wilkinson splitter460can represent the gate capacitance of each of the amplifiers423,439′ and439″, respectively.

Turning to the active splitter470, the two resistors452-453provide isolation between the branches401-403of the active splitter470. Path408of the active splitter470has a total phase of 180 degrees (90 degrees for branch402plus 90 degrees for branch403) which results in branches402-403of the active splitter470being out-of-phase and thereby electrically isolated. Similarly, path408′ has a total phase of 180 degrees (90 degrees for branch402plus 90 degrees for branch401) which results in branches401and402of the active splitter470being out-of-phase and thereby electrically isolated. Also, path408″ has a total phase of 180 degrees (90 degrees for branch401plus 90 degrees for branch403) which results in branches401and403of the active splitter470being out-of-phase and thereby electrically isolated. The embodiment ofFIG.5Gdemonstrates alternative configurations of the embodiment ofFIG.4with passive and active configurations. The active splitter470also provides isolation between paths and an improved broadband frequency response. The adjustment elements412,414′,414″ of the active splitter are configurable to match at least in part the impedance of the outputs of the amplifiers423,439′,439″ and add a phase delay that achieves the 180 degree phase in paths408,408′,408″ to maintain isolation between batches401,402,403.

Turning toFIG.5H, in this embodiment, the gate terminals511,513and515of amplifiers523,539′, and539″ are electrically connected together. Capacitors522,532, and542can represent the gate capacitances of amplifiers523,539′, and539″, respectively. Inductor520can represent a wirebond to the shared gate terminal. The combination of capacitor510, inductor520, and parallel capacitors522,532,542can form a CLC filter519′ configurable to match the input impedance at input505. The remaining components shown inFIG.5Hoperate as described inFIG.5A.FIG.5Idepicts plots that compare a performance of the power splitter404,504ofFIGS.4and5Ato passive splitters, in accordance with an example embodiment.FIG.5I(1) illustrates that the power splitter404,504ofFIGS.4and5Acan be configured to have 20 dB more gain (e.g.,554) than a passive splitter at approximately −5 dB (e.g.,552).FIG.5I(2) further illustrates that the power splitter404,504can have an electrical isolation (e.g.,558) between output terminals of main and peaking amplification paths401-501,402-403,502-503that is similar to the electrical isolation (e.g.,556) of output terminals of main and peak paths of a passive splitter.FIG.5I(3) also illustrates that the input-to-output electrical isolation of the power splitter404,504shown at approximately −27 dB is an improvement of approximately 22 dB (e.g.,562) over the input-to-output electrical isolation of a passive splitter (e.g.,560) at approximately −5 dB.FIG.5I(4) further illustrates that the power splitter404,504has an electrical isolation (e.g.,566) between peaking amplification paths402-403,502-503that is similar to the electrical isolation (e.g.,564) between peaking amplification paths of a passive splitter.

Referring again toFIG.2, output206(e.g., output406,506,FIGS.4,5A) of power splitter204is electrically connected to the input221of the main amplifier220through a conductive path implemented in the build-up layers312of the Doherty IC200. According to an embodiment, outputs207,208(e.g., outputs407,507,408,508,FIGS.4,5A) of power splitter204are electrically connected to the inputs241′,241″ of the peaking amplifier portions240′,240″ through input phase delay circuits209′,209″ (e.g., input phase delay circuits109′,109″,FIG.1) and additional conductive paths implemented in the build-up layers312of the Doherty IC200. The input phase delay circuits209′,209″ are configured to ensure that the peaking input signals at the inputs241′,241″ to the peaking amplifier portions240′,240″ have about 90 degrees of phase difference from the main input signal at the input221to the main amplifier220.

Each of the main amplifier220and the peaking amplifier portions240′,240″ may have a substantially similar configuration, in an embodiment. According to an embodiment, each amplifier220,240′,240″ is a two-stage amplifier, which includes a relatively low-power driver amplifier226,246′,246″ (or driver amplifier FET) and a relatively high-power final-stage amplifier230,250′,250″ (or final-stage amplifier FET) connected in a cascade arrangement between an amplifier input221,241′,241″ and a combining node structure290.

In the main amplifier220, an input221of the amplifier220is coupled through an input impedance matching network222(e.g., IMN122,FIG.1) to an input terminal225(e.g., gate terminal) of driver amplifier FET226, an output227(e.g., drain terminal) of the driver amplifier FET226is electrically coupled through an inter-stage impedance matching network228(e.g., ISMN128,FIG.1) to an input terminal229(e.g., gate terminal) of final-stage amplifier FET230. Similarly, in each of the peaking amplifier portions240′,240″, an input241′,241″ of the amplifier240′,240″ is coupled through an input impedance matching network242′,242″ (e.g., IMNs142′,142″,FIG.1) to an input terminal245′,245″ (e.g., gate terminal) of driver amplifier FET246′,246″, an output247′,247″ (e.g., drain terminal) of the driver amplifier FET246′,246″ is electrically coupled through an inter-stage impedance matching network248′,248″ (e.g., ISMN148′,148″,FIG.1) to an input terminal249′,249″ (e.g., gate terminal) of final-stage amplifier FET250′,250″. The source terminals of each of FETs226,230,246′,246″,250′,250″ are electrically coupled to a ground reference (e.g., using TSVs through the base semiconductor substrate310to a bottom conductive layer328,FIG.3).

Each driver amplifier FET226,246′,246″ may be equal in size, in an embodiment, and may configured to apply a gain to a respective input RF signal in a range of about 15 decibels (dB) to about 25 dB when the Doherty IC200is operating in a high-power mode (e.g., close to compression), although only driver amplifier FET226provides gain to its input signal when the Doherty IC200is operating in a low-power mode. The final-stage amplifier FETs230,250′,250″ are significantly larger than the driver amplifier FETs226,246′,246″ (e.g., at least twice as large to apply at least twice the gain). Each final-stage amplifier FET230,250′,250″ also may be equal in size, in an embodiment, and may be configured to apply a gain to a respective input RF signal in a range of about 15 dB to about 25 dB when the Doherty IC200is operating in a high-power mode (e.g., close to compression), although only final-stage amplifier FET230provides gain to its input signal when the Doherty IC200is operating in a low-power mode.

According to an embodiment, gate bias voltages for each of the FETs226,230,246′,246″,250′,250″ are provided through resistor-divider gate bias circuits270,270′,270″ (e.g., resistor-divider gate bias circuits170,170′,170″,FIG.1). As indicated previously, for proper operation of Doherty amplifier IC200, the main amplifier220is biased to operate in class AB mode, and the peaking amplifier portions240′,240″ typically are biased to operate in class C mode. In some configurations, the peaking amplifier portions240′,240″ may be biased to operate in class B or deep class B modes. Because the main amplifier220is biased differently from the peaking amplifier portions240′,240″, the main amplifier resistor-divider gate bias circuit270is distinct from (and not electrically connected to) the peaking amplifier resistor-divider gate bias circuits270′,270″. However, since the peaking amplifier portions240′,240″ are biased the same as each other, the peaking amplifier resistor-divider gate bias circuits270′,270″ may be identical and electrically connected together, as is shown in the embodiment ofFIG.2.

In the illustrated embodiment, the main amplifier resistor-divider gate bias circuit270includes an input terminal271, resistors273,274, and RF isolation circuits275,276. Similarly, the peaking amplifier resistor-divider gate bias circuits270′,270″ each include an input terminal271′, resistors273′,273″,274′,274″ and RF isolation circuits275′,275″,276′,276″. In addition to the gate bias circuits270,270′,270″, Doherty amplifier IC200also may include one or more drain bias circuits282. According to an embodiment, a drain bias circuit282includes an input terminal284and RF isolation circuits286,286′,286″. The outputs (i.e., drain terminals231,251′,251″) of each of the final-stage amplifier FETs230,250′,250″ are electrically connected to combining node structure290(e.g., combining node structure190,FIG.1), which functions to combine the amplified RF signals produced by each of the final-stage amplifier FETs230,250′,250″ into a single amplified output RF signal.

Combining node structure290includes an elongated conductive bondpad that is exposed at the top surface of die201. According to an embodiment, the length of the combining node structure290extends from the outside end252′ of the drain terminal251′ of peaking amplifier final stage FET250′ to the outside end252″ of the drain terminal251″ of peaking amplifier final stage FET250″. As illustrated inFIG.2, combining node structure290has three sections, including a leftmost section that is electrically connected to the drain terminal251′ of peaking amplifier final-stage FET250′, a central section that is electrically connected (through wirebonds238) to the drain terminal231of main amplifier final-stage FET230, and a rightmost section that is electrically connected to the drain terminal251″ of peaking amplifier final-stage FET250″. According to an embodiment, the combining node structure290is a continuous conductive bondpad, although the combining node structure290could include discontinuous but electrically connected sections, as well.

Desirably, the drain terminals251′,251″ are connected to the combining node structure290with conductive paths having a negligible phase delay (i.e., as close to zero degrees of phase delay as possible, such as 10 degrees or less of phase delay), and in some embodiments, the drain terminals251′,251″ may be integrally formed portions of the combining node structure290. In other words, the drain terminal manifold of the peaking amplifier final-stage FETs250′,250″ may form portions of the combining node structure290, in some embodiments. As mentioned previously, base semiconductor substrate310is a high-resistivity substrate, and therefore potentially high losses that might otherwise occur with a relatively long transmission line (such as combining node structure290) on a relatively low-resistivity substrate are significantly reduced in Doherty amplifier IC200.

As mentioned previously, to compensate for the 90 degree phase delay difference between the main and peaking amplification paths at the inputs of amplifiers220,240′,240″ (i.e., to ensure that the amplified signals are combined in phase at the combining node structure290), an output phase delay circuit236(e.g., circuit136,FIG.1) is electrically coupled between the output (i.e., drain terminal231) of the main amplifier final-stage FET230and the outputs (i.e., drain terminals251′,251″) of the peaking amplifier final-stage FETs250′,250″. Specifically, the output phase delay circuit236is configured to result in a phase difference that is substantially equal to 90 degrees (i.e., 90 degrees+/−10 degrees) between an RF signal at the drain terminal231of the main amplifier final-stage FET230and RF signals at the drain terminals251′,251″ of the peaking amplifier final stage FETs250′,250″.

According to an embodiment, the output phase delay circuit236has a CLC (capacitance-inductance-capacitance) topology between drain terminal231and drain terminals251′,251″. The first (shunt) capacitance includes the drain-source capacitance, CdsM, of the main amplifier final-stage FET230. A plurality of wirebonds238are electrically connected between the drain terminal231of the main amplifier final-stage FET230and combining node structure290. More specifically, first ends of the wirebonds238are connected to the drain terminal231, and second ends of the wirebonds238are connected to the combining node structure290. The inductance in the CLC topology of the output phase delay circuit236is provided by the series combination of wirebonds238and portions of the combining node structure290that extend between the landing points of the wirebonds238on the structure290and the drain terminals251′,251″ of the peaking amplifier final-stage FETs250′,250″. According to an embodiment, the series combination of the wirebonds238and those portions of the combining node structure290have a combined inductance in a range of about 0.8 nH to about 1.2 nH at a center frequency of operation of about 2.0 GHz, although the center frequency and/or the combined inductance could be lower or higher, as well.

Finally, the second (shunt) capacitance in the CLC topology of the output phase delay circuit236approximately equals the combined drain-source capacitances, CdsP, of the peaking amplifier final-stage FETs250′,250″ minus a portion of CdsPthat is compensated for by a shunt inductance (e.g., shunt inductor750,FIG.7). To summarize, the 90 degree phase difference between drain terminal231and drain terminals251′,251″ is provided by an output phase delay circuit236with a CLC topology, where that topology includes a first shunt capacitance (provided by CdsM), a series inductance (provided by wirebonds238and portions of combining node structure290), and a second shunt capacitance (provided by A×CdsP, where A<1.0).

Doherty power amplifier IC200may be packaged and/or incorporated into a larger electrical system in a variety of ways. For example, Doherty IC200may be packaged within an overmolded or air-cavity power device package (e.g., package604,FIG.6). Alternatively, Doherty IC200may be packaged in a surface-mount type of package, such as a no-leads package (e.g., a dual-flat no leads (DFN) or quad-flat no leads (QFN) package). In still other embodiments, Doherty IC200may be mounted directly to a module or PCB substrate surface.

By way of example,FIG.6is a top view of a Doherty amplifier device600that includes a Doherty IC602(e.g., Doherty IC200,FIG.2) packaged in a high-power, discrete device package604, in accordance with an example embodiment. Package604includes a plurality of conductive input signal and bias leads610-616and at least one output lead620. The input signal and bias leads610-616are positioned at an input side of the package604, and the at least one output lead620is positioned at an output side of the package604. The input side (e.g., input side210,FIG.2) of the Doherty IC die602is proximate to and parallel with the input side of the device package604, in an embodiment.

In addition, package604includes a package substrate, such as a conductive flange630, to which Doherty IC602is physically and electrically connected (e.g., with conductive epoxy, solder, brazing, sintering, or other conductive connection methods). Finally, package604includes non-conductive structural features or materials, such as molding compound and/or other insulating materials, which hold the leads610-616,620and the flange630in fixed orientations with respect to each other.

Electrically conductive connections, such as conductive wirebonds650-656, electrically connect input signal and bias voltage bond pads (or terminals) on die602to conductive leads610-616on an input side of the device600. For example, one or more first wirebonds650may electrically connect an input RF signal lead610to a first bondpad corresponding to an input terminal (e.g., input terminal202,FIG.2), and the input RF signal lead610may be used to convey an input RF signal to the Doherty IC602.

According to an embodiment, the output of Doherty IC602(and more specifically the combining node structure290,FIG.2) is electrically connected to the output lead620through a plurality of wirebonds670. According to an embodiment, package604is designed so that die602, and more specifically the combining node structure of die602, may be positioned very close to output lead620when die602is coupled to package604. Accordingly, wirebonds670may be relatively short. In addition, the number of wirebonds670may be selected to be relatively large (e.g., 20-40 wirebonds, more or less), which renders wirebonds670a relatively low parasitic inductive element. According to an embodiment, wirebonds670have an inductance value in a range of about 20 pH to about 70 pH (e.g., about 60 pH) although the inductance value may be smaller or larger, as well. Desirably, wirebonds670are designed so that the inductance value of wirebonds670is as low as possible.

In some embodiments, leads610-616,620and flange630may form portions of a lead frame. To complete an overmolded package during device manufacturing, after attachment of die602and wirebonds650-656,670, the die602, the interior ends of leads610-616,620, wirebonds650-656,670, and the upper and side surfaces of flange630may be encapsulated with a non-conductive (e.g., plastic) molding compound640,642(only partially shown inFIG.6to avoid obscuring the interior components of device600). The molding compound640,642defines the perimeter of the device600from which leads610-616,620protrude, and also defines the top surface of the device600. The bottom surface of the device600is defined partially by the molding compound640, and partially by the bottom surface of flange630. Accordingly, when appropriately coupled to a system substrate (e.g., PCB710,FIG.7), flange630may function to convey a ground reference to the die602(e.g., through the bottom conductive layer328,FIG.3), and also may function as a heat sink for the device600.

In a similar but different embodiment, leads610-616,620with the configurations shown inFIG.6may be replaced with lands of a no-leads package. The flange630and lands again may form a lead frame to which the die602and wirebonds650-656,670are attached, and again the assembly may be encapsulated with a non-conductive molding compound to form a no-leads, surface mount device (e.g., a DFN or QFN device).

In other embodiments, package604may be an air-cavity package. In such an embodiment, flange630may have a larger perimeter, which is equal or approximately equal to the perimeter of the device600. A non-conductive insulator (e.g., ceramic, plastic, or another material) with a frame shape may be attached to the top surface of the flange, leads610-616,620may be placed over the non-conductive insulator, wirebonds650-656,670are attached, and a cap (not illustrated) is placed over the frame opening to encase the interior components of the device600in an air cavity.

Ultimately, Doherty amplifier device600is incorporated into a larger electrical system (e.g., a power transmitter lineup in a cellular base station). For example, as illustrated inFIG.7, a Doherty amplifier device720(e.g., device600,FIG.6) may be incorporated into amplifier system700.

Amplifier system700includes a single-layer or multi-layer PCB710, and a plurality of elements coupled to the PCB710, in an embodiment. For example, the amplifier system700may include a conductive coin715(or other feature) that is exposed at top and bottom surfaces of the PCB710, and a Doherty amplifier device720(e.g., device600,FIG.6) connected to the conductive coin715. More specifically, the bottom surface (e.g., the bottom of flange630,FIG.6) of the Doherty amplifier device720may be physically and electrically connected to the top surface of the conductive coin715. The conductive coin715, in turn, may be electrically connected to system ground, and a bottom surface of the coin715may be connected to a system heat sink. Accordingly, the conductive coin715may function as a ground reference and a heat sink for the amplifier system700.

In a typical configuration, the amplifier system700includes an input RF connector701and an output RF connector702, which are configured, respectively, to receive an input RF signal from an RF signal source, and to produce an amplified output RF signal for transmission (e.g., via a cellular antenna coupled to connector702). One or more bias voltage connectors703,704may be used to receive DC bias voltages from one or more voltage sources.

In addition, the amplifier system700includes a plurality of conductive paths and features730-736that are electrically coupled between the connectors701-703and the Doherty amplifier device720. The conductive paths and features730-736may be formed from patterned portions of a top conductive layer, a bottom conductive layer, and/or interior conductive layer(s) (if included) of the PCB710.

A first conductive path730electrically connects the input RF connector701to an input RF signal lead722(e.g., lead610,FIG.6) of the Doherty amplifier device720. An input RF signal received by input RF connector701is conveyed to the input RF signal lead722through the first conductive path730during operation of the system700. Similarly, a second conductive path731electrically connects the output RF connector702to an output RF signal lead728(e.g., lead620,FIG.6) of the Doherty amplifier device720. An amplified RF signal produced by the Doherty amplifier device720is conveyed to the output RF connector702through the second conductive path731during operation of the system700.

Additional conductive paths732,733,734electrically connect the bias voltage connector703to a plurality of bias voltage leads724(e.g., leads611,613,615,FIG.6) on a first side of the Doherty amplifier device720. A plurality of drain and gate DC bias voltages are conveyed to the bias voltage leads724through conductive paths732-734during operation of the system700. On the output side, a conductive path735electrically connects the bias voltage connector704to the output RF signal lead728(e.g., either directly or through path731, as shown inFIG.7). A drain DC bias voltage for the final-stage amplifiers is conveyed to the output RF signal lead728through bias voltage connector704, conductive path735, and output RF signal lead728during operation of the system700.

According to an embodiment, amplifier system700also includes a shunt inductor750, which is electrically coupled between the output RF signal lead728and an additional conductive feature736. The shunt inductor750may be a discrete inductor, for example, which has a first terminal coupled to the output RF signal lead728(e.g., either directly or through path731, as shown inFIG.7), and a second terminal coupled to the conductive feature736, which in turn is electrically coupled to system ground. The shunt inductor750is configured to at least partially absorb the drain source capacitance of the peaking amplifier final-stage transistor(s) (e.g., drain-source capacitances, CdsP, of the peaking amplifier final-stage FETs250′,250″,FIG.2), in an embodiment. In an alternate embodiment, all or a portion of the shunt inductance provided by shunt inductor750instead may be provided by designing an optimized conductive path735between the bias voltage connector704and the output RF signal lead728, in which case shunt inductor750may be omitted. Although conventional asymmetric Doherty amplifier systems may include a shunt inductance for this purpose, the shunt inductance typically needs to be implemented inside the amplifier package (e.g., inside device720). However, the relatively low inductance of the output wirebonds (e.g., wirebonds670,FIG.6) enables the shunt inductance to be moved outside of the amplifier package, in accordance with various embodiments. This may enable the amplifier package size to be decreased, while also facilitating easier tuning of the system700, since the shunt inductor750size can be modified without requiring a re-design of the Doherty amplifier device720.

FIG.8Ais a flowchart of a method of making a Doherty power amplifier IC (e.g., Doherty IC200,FIG.2), a packaged Doherty amplifier device (e.g., device600,FIG.6), and a Doherty amplifier system (e.g., system700,FIG.7), in accordance with an example embodiment. The method may begin, in block802, by forming an amplifier die (e.g., die201,FIG.2), which includes integrally-formed main amplifier transistors (e.g., FETs226,230,FIG.2), peaking amplifier transistors (e.g., FETs246′,246″,250′,250″,FIG.2), and a combining node structure (e.g., combining node structure290,FIG.2). In addition, forming the amplifier die may include integrally-forming a power splitter (e.g., splitter204,FIG.2) having pre-driver amplifier transistors (e.g., amplifiers423,439′,439″,523,539′,539″,FIGS.4,5A), matching networks (e.g., IMN222,242′,242″, ISMN228,248′,248″,FIG.2), bias circuits (e.g., bias circuits270,270′,270″,FIG.2), and/or other integrated components. In alternate embodiments, some of the circuits and components (e.g., the power splitter204) in the previous sentence may be implemented on substrates that are distinct from the amplifier die.

In block804, the Doherty amplifier IC (e.g., Doherty amplifier IC200,FIG.2) is completed by connecting the output terminal (e.g., drain terminal231,FIG.2) of the main amplifier final-stage transistor (e.g., FET230,FIG.2) to the combining node structure (e.g., combining node structure290,FIG.2). For example, the connection may be made with wirebonds (e.g., wirebonds238,FIG.2) that have a predetermined length, height, and number to create a desired phase delay (e.g., 90 degrees) between the main and peaking amplifier outputs.

The Doherty amplifier IC (e.g., Doherty IC200,FIG.2) may then be packaged in block806. As mentioned previously, the Doherty amplifier IC may be packaged in an overmolded or air-cavity power package. Alternatively, the Doherty amplifier IC may be attached as a bare die to a system substrate (e.g., a module or PCB substrate). When packaged in an overmolded package (e.g., package604,FIG.6), the Doherty amplifier IC may be connected to a conductive flange of a leadframe, wirebonds (e.g., wirebonds650-656,670,FIG.6) may be coupled between input, output, and bias leads of the leadframe and appropriate bond pads of the Doherty amplifier IC, and the flange, leads, and Doherty amplifier IC may be encapsulated in molding compound. When packaged in an air-cavity package, an insulator frame may be attached to the top surface of a conductive flange, the Doherty amplifier IC may be connected to the top surface of the flange in the frame opening, input, output, and bias leads may be connected to the top surface of the insulator frame, wirebonds (e.g., wirebonds650-656,670,FIG.6) may be coupled between the input, output, and bias leads and appropriate bond pads of the Doherty amplifier IC, and a cap may be applied over the flange, insulator frame, leads, wirebonds, and Doherty amplifier IC to encase the Doherty amplifier IC in an air cavity.

In block808, the amplifier system (e.g., system700,FIG.7) may be completed by attaching the Doherty amplifier device (e.g., device600,FIG.6) (or in some embodiments the bare die) to a system substrate, such as a PCB (e.g., PCB710,FIG.7). More specifically, the bottom surface of the Doherty amplifier device may be connected to a conductive coin (e.g., coin715,FIG.7) to provide a ground reference and heat sink to the device, and the device's input, output, and bias leads may be connected to corresponding conductive paths (e.g., paths730-734,FIG.7) of the system substrate.

According to an embodiment, additional components may be coupled to the system substrate (e.g., PCB710,FIG.7), in block810, to complete the amplifier system. For example, as described previously, a discrete inductor (e.g., inductor750,FIG.7) may be coupled between the Doherty amplifier device's output lead (e.g., output lead728,FIG.7) and a ground reference by coupling the inductor to conductive features (e.g., path731and feature736,FIG.7) of the system substrate. Additionally, a metallic cover or shield connected to a ground plane of the PCB can be used to cover in whole or in part the components of the PCB710to provide electrical isolation from other devices of other systems. The method may then end.

FIG.8Bis a flowchart of a method of making a power splitter IC (e.g., power splitter104,FIG.1,204,FIG.2,404,FIG.4,504,FIG.5A), a packaged power splitter device, and a power splitter system, in accordance with an example embodiment. The method may begin, in block822, by forming a power splitter die, which includes integrally-formed input matching networks (e.g.,519,FIG.5A, which can be optional), pre-driver amplifier transistors (e.g., FETs423,439′,439″,523,539′,539″,FIGS.4,5A), adjustment elements (e.g., transmission lines or CLCs412,414′,414″,512,514′,514″,FIGS.4,5A), and isolation resistors (e.g.,452-453,552-553,FIGS.4,5A). In addition, forming the power splitter die may include integrally-forming bias circuits coupled to the pre-driver amplifier transistors423,439′,439″,523,539′,539″. In alternate embodiments, some of the circuits and components (e.g., input matching networks) may be implemented on substrates that are distinct from the power splitter die.

In block824, the power splitter IC (e.g., power splitter IC404,504,FIGS.4,5A) is completed by connecting the output terminal of each adjustment element to wirebonds that have a predetermined length, height, and number to create a desired resulting branch phase (e.g., 90 degrees) that electrically isolates the splitter branches (e.g.,401-403,501-503,FIGS.4,5A). The power splitter IC may then be packaged in block826. Similar to the Doherty amplifier IC, the power splitter IC may be packaged in an overmolded or air-cavity power package. Alternatively, the power splitter IC may be attached as a bare die to a system substrate (e.g., a module or PCB substrate). When packaged in an overmolded package, the power splitter IC may be connected to a conductive flange of a leadframe, wirebonds may be coupled between input, output, and bias leads of the leadframe and appropriate bond pads of the power splitter IC, and the flange, leads, and power splitter IC may be encapsulated in molding compound. When packaged in an air-cavity package, an insulator frame may be attached to the top surface of a conductive flange, the power splitter IC may be connected to the top surface of the flange in the frame opening, input, output, and bias leads may be connected to the top surface of the insulator frame, wirebonds may be coupled between the input, output, and bias leads and appropriate bond pads of the power splitter IC, and a cap may be applied over the flange, insulator frame, leads, wirebonds, and power splitter IC to encase the power splitter IC in an air cavity.

In block828, the power splitter system may be completed by attaching the power splitter device (or in some embodiments the bare die) to a system substrate, such as a PCB. More specifically, the bottom surface of the power splitter device may be connected to a conductive coin to provide a ground reference and heat sink to the device, and the device's input, output, and bias leads may be connected to corresponding conductive paths of the system substrate.

According to an embodiment, additional components may be coupled to the power splitter system substrate, in block830. For example, outputs of the power splitter system substrate may be coupled to a single-stage or multi-stage amplifier such as a Doherty amplifier device that does not have an integrally formed power splitter. The method may then end.

An embodiment of a power splitter may include power amplifiers and corresponding adjustment elements. The power splitter can be a on a single die or combined with the multi-path amplifier (e.g., Doherty amplifier) on the same die. The power splitter can include a plurality of power splitter branches, each branch configurable to couple to an input terminal of a multi-path amplifier. Each power splitter branch includes a pre-driver amplifier and adjustment element. To achieve a desired phase delay and impedance matching characteristics for coupling to pre-driver amplifier outputs, the adjustment element can comprise a transmission line with a suitable electrical length, a lumped-element delay circuit, a combination of both, or other suitable delay circuit. Additionally, the adjustment elements can be configured to also provide impedance matching characteristics for coupling to input paths of a multi-path amplifier device. The pre-driver amplifier of each splitter branch can be a single-stage amplifier or multi-stage amplifier that is configurable to couple to a single-stage amplifier or multi-stage amplifier path of a multi-path amplifier device such as a Doherty amplifier device.

The pre-driver amplifier in each power splitter branch can have symmetric or asymmetric gain relative to the pre-driver amplifier of other splitter branches. Additionally, each pre-driver amplifier in each power splitter branch can be configured for a specific frequency band or a range of frequency bands may be the same or differ from the frequency band or a range of frequency bands of the pre-driver amplifier of other splitter branches. Further, each pre-driver amplifier can be configured with input filter circuits and/or matching network circuits for coupling to an RF input source. In order to increase electrical isolation between power splitter branches, each branch can be configured to have similar or substantially equal phase delay (e.g., 90 degrees or other suitable delay). An isolation impedance can also be added between power splitter branches to further increase electrical isolation between such branches.

An embodiment of a multiple-branch splitter can include a semiconductor die, a radio frequency (RF) signal input terminal, a first splitter branch, and a second splitter branch. An embodiment of the first splitter branch can include a first amplifier and a first adjustment element integrally formed with the semiconductor die. A first gate terminal of the first amplifier can be coupled to the RF signal input terminal, and a first drain terminal of the first amplifier can be coupled to a first input of the first adjustment element. The second splitter branch can include a second amplifier and a second adjustment element integrally formed with the semiconductor die. A second gate terminal of the second amplifier can be coupled to the RF signal input terminal, and a second drain terminal of the second amplifier can be coupled to a second input of the second adjustment element. The first splitter branch has a first combined phase delay based at least on a combination of a first phase delay of the first amplifier and a second phase delay of the first adjustment element. The second splitter branch has a second combined phase delay based at least on a combination of a third phase delay of the second amplifier and a fourth phase delay of the second adjustment element. The first splitter branch is substantially electrically isolated from the second splitter branch based on the first combined phase delay being substantially equal to the second combined phase delay. In an embodiment, the first combined phase delay can be substantially equal to the second combined phase delay when a phase offset between the first and second combined phase delays is +/−10% or lower. Other phase offset ranges that may be less than or more than +/−10% are contemplated by the subject disclosure. In an embodiment, the first splitter branch and the second splitter branch can be configured to split and amplify an input power level of an RF signal upon being applied at the RF signal input terminal according to an amplification ratio which may or may not be symmetric.

An embodiment of a multiple-path amplifier can include a semiconductor substrate, first and second splitter branches, and first and second amplification paths. The first splitter branch can include a first pre-driver amplifier integrally formed on the semiconductor substrate. A first gate terminal of the first pre-driver amplifier can be coupled to an RF signal input terminal. The second splitter branch can include a second pre-driver amplifier integrally formed on the semiconductor substrate. A second gate terminal of the second pre-driver amplifier can be coupled to the RF signal input terminal. The first amplification path can be integrally formed on the semiconductor substrate and can be further coupled to a first output of the first splitter branch. The second amplification path can be integrally formed on the semiconductor substrate and can coupled to a second output of the second splitter branch. In an embodiment, the first splitter branch can provide a first pre-amplification level of an RF signal upon being applied at the RF signal input terminal to generate a first amplified signal supplied to the first amplification path. The second splitter branch can provide a second pre-amplification level of the RF signal to generate a second amplified signal supplied to the second amplification path. Electrical coupling between the first splitter branch and the second splitter branch can be substantially reduced by configuring the first splitter branch and the second splitter branch to have approximating phase delays. In an embodiment, approximating phase delays can be achieved when a phase offset between the first and second splitter branches is +/−10% or lower. Other phase offset ranges that may be less than or more than +/−10% are contemplated by the subject disclosure.

In an embodiment, the power splitter can be manufactured according to a method. The method can include forming first and second splitter branches on a semiconductor substrate. The first splitter branch can include a first amplifier and a first adjustment element integrally formed with the semiconductor substrate. A first gate terminal of the first amplifier can be coupled to an RF signal input terminal, and a first drain terminal of the first amplifier can be coupled to a first input of the first adjustment element. The second splitter branch can include a second amplifier and a second adjustment element integrally formed with the semiconductor substrate. A second gate terminal of the second amplifier can be coupled to the RF signal input terminal, and a second drain terminal of the second amplifier can be coupled to a second input of the second adjustment element. The first splitter branch is substantially electrically isolated from the second splitter branch based on the first splitter branch and the second splitter branch having substantially similar phase delays. In an embodiment, substantially similar phase delays can be achieved when a phase offset between the first and second splitter branches is +/−10% or lower. Other phase offset ranges that may be less than or more than +/−10% are contemplated by the subject disclosure.

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.

As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.