Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same

A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

FIELD OF THE DISCLOSURE

The present disclosure relates to semiconductor devices, and more particularly to a semiconductor device comprising a metal gate electrode and a counter-doped channel and method for forming the same.

DESCRIPTION OF THE RELATED ART

State-of-the-art semiconductor devices currently include transistors having a gate dielectric layer formed from one or more high dielectric constant (“high-k”) materials. These materials typically have a dielectric constant higher than that of silicon dioxide, which is approximately 3.9. High-k dielectric materials, including HfO2, ZrO2, etc., are used as gate dielectric layers in transistors that have metal gate electrodes instead of polysilicon gate electrodes due to the potential problems with poly depletion in doped polysilicon gates. Exemplary materials for metal gate electrodes include TiN, TaC, TaSiN, and the like.

When a metal gate electrode is used, the portion of metal gate electrode closest to the gate dielectric layer establishes the work function for the gate electrode. Changing the work function metal gate electrode will also change the threshold voltage (VT). An NMOS (N-type metal-oxide semiconductor) transistor may have TaSiN as the portion of its metal-containing gate electrode closest to the high-k gate dielectric layer, and a PMOS (P-type metal-oxide semiconductor) transistor may have TiN as the portion of its metal-containing gate electrode closest to the high-k gate dielectric layer. The work function for TaSiN is about 4.3 eV, and the work function for TiN is about 4.6 eV. As a basis for comparison, the work function for N+silicon and the energy level for the conduction band (“Ec”) for silicon is 4.1 eV, and the work function for P+silicon and the energy level for the valence band (“Ev”) for silicon is 5.2 eV. Therefore, the difference between Ecand the work function for TaSiN is 0.2 eV, and the difference between Evand the work function for TiN is 0.6 eV. These differences can cause longer times to switch states (i.e., “on” and “off”) for the transistors, and therefore, result in a slower operating electronic device. Also, the work function for a metal gate electrode can be “pinned” towards mid-band, limiting the ability to change the VT.

Therefore, there is a need to be able to modulate the VTfor metal gate transistors.

DETAILED DESCRIPTION

One or more impurities may be incorporated within the channel region of a transistor having a metal-containing gate electrode to modify the threshold voltage of the transistor. In a particular embodiment, a boron-containing species is implanted into a channel region below the metal-containing gate electrode within a transistor.

In one embodiment, the boron-containing species includes B or BF2. In a particular embodiment, the first layer includes an elemental transition metal, a transition metal nitride, a transition metal silicon nitride, or any combination thereof.

Before addressing details of embodiments described below, some terms are defined or clarified. Group numbers corresponding to columns within the Periodic Table of the elements use the “New Notation” convention as seen in theCRC Handbook of Chemistry and Physics,81stEdition (2000).

The term “metal” or any of its variants is intended to refer to a material that includes an element that is within any of Groups 1 to 12, within Groups 13 to 16, an element that is along and below a diagonal line defined by atomic numbers 13 (Al), 32 (Ge), 51 (Sb), and 84 (Po), or any combination thereof. Metal does not include Si. The term “transition metal element” is intended to refer to an element that is within any of Groups 3 to 12.

The term “elemental transition metal” is intended to refer to a transition metal that is not part of a molecule that comprises at least two different elements. For example, Ti atoms that are not chemically bound to any other atoms are considered an elemental transition metal; however Ti atoms within TiN are not considered to be an elemental transition metal.

Additionally, for clarity purposes and to give a general sense of the scope of the embodiments described herein, the use of the “a” or “an” are employed to describe one or more articles to which “a” or “an” refers. Therefore, the description should be read to include one or at least one whenever “a” or “an” is used, and the singular also includes the plural unless it is clear that the contrary is meant otherwise.

To the extent not described herein, many details regarding specific materials, processing acts, and circuits are conventional and may be found in textbooks and other sources within the semiconductor and microelectronic arts.

FIG. 1includes an illustration of a cross-sectional view of a substrate10, which includes a PMOS portion11and an NMOS portion13. The substrate10can include a monocrystalline semiconductor material, a semiconductor-on-insulator substrate, or nearly any other substrate used in forming semiconductor devices. Within the PMOS portion11, the substrate10may include an n-type dopant, and within the NMOS portion13, the substrate10may include a p-type dopant. In another embodiment, the conductivity types for the dopants may be reversed or may be the same.

Layers are sequentially formed over the substrate10within the PMOS and NMOS portions11and13. The layers include a gate dielectric layer12, a first layer14, which will the part of the gate electrode within PMOS portion11, and a hard mask layer16. The gate dielectric layer12has a thickness in a range of approximately 1 to 5 nm, the first layer has a thickness in a range of approximately 5 to 20 nm, and the hard mask layer16has a thickness in a range of approximately 10 to 100 nm. Although not illustrated, an interfacial layer of approximately 1 nm may be formed between the substrate10and the gate dielectric layer12during or prior to the formation of the electronic device.

The gate dielectric layer12can include one or more high-k materials, such as HfO2. In another embodiment, the gate dielectric layer12can include HfOxNy, HfSixOy, HfSixOyNz, HfZrxOyNz, HfZrxSiyOzNq, HfZrO, ZrSixOy, ZrSixOyNz, ZrO2, other Hf-containing or Zr-containing dielectric material, or any combination thereof. The first layer14is compatible with the gate dielectric layer12(i.e., does not adversely interact with the gate dielectric layer12). In one embodiment, the first layer14includes a metallic element, such as a transition metal element. In a particular embodiment, the first layer14includes an elemental transition metal (e.g., substantially only atoms of the transition metal). In another embodiment, the first layer14may include a second element that, in one embodiment, is any element other than silicon. The first layer may include a third element. The third element may include silicon. Therefore, the first layer14can include only one element that is a metallic element, can include only two elements, wherein both of the elements are not silicon, or can include three or more elements, of which, one of the elements may be silicon. The first layer14can include TiN, MoxNy, TaC, MoSixNy, RuO2, IrO2, Ru, Ir, MoSiO, MoSiON, MoHfO, MoHfON, other transition metal containing material, or any combination thereof.

The hard mask layer16can include nearly any material that is relatively resistant to etching when portions of the first layer14are to be removed. Additionally, when the hard mask layer16is subsequently removed after patterning the first layer14, the hard mask layer16will be removed selectively to a remaining portion of the first layer14. The hard mask layer16can include SiO2, Si3N4, SiOxNy, or any combination thereof. In one embodiment, the hard mask layer16is formed by depositing an oxide layer using tetraethylorthosilicate (TEOS).

The gate dielectric layer12, first layer14, hard mask layer16, or any combination thereof can be formed by depositing an appropriate material using atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. In another embodiment, the gate dielectric layer12, first layer14, hard mask layer16, or any combination thereof can include one film or a plurality of films.

A resist layer is formed over the substrate10and is patterned to form a resist mask18, which overlies the hard mask layer16within the PMOS portion11. The resist mask18is not formed over the hard mask layer16within the NMOS portion13. In one embodiment, the resist mask18is formed by coating or otherwise depositing a photoresist material to form the resist layer, and using a lithographic process to pattern the resist layer to form the resist mask18. The resist layer may include a negative-acting or positive-acting photoresist material.

The exposed portion of the hard mask layer16is removed from the NMOS portion13, and the resist mask18is then subsequently removed, as illustrated inFIG. 2. The hard mask layer16may be removed by using a conventional etching process. The etching is performed such that the hard mask layer16is selectively removed as compared to the first layer14. In one embodiment, etching can be preformed as a wet etch using a dilute HF solution. In one embodiment, the dilute HF solution has at least 10 parts H2O for each part HF, and in a particular embodiment, the dilute HF solution has at least 100 parts H2O for each part HF. In another embodiment, etching can be performed as a dry etch. The resist mask18is removed using a conventional ashing technique.

At this point in the process, a remaining portion of the hard mask layer16lies within the PMOS portion11, and a portion of the first layer14is exposed within the NMOS portion13. The exposed portion of the first layer14is removed from the NMOS portion13. The hard mask layer16protects the portion of the first layer14within the PMOS portion11, such that it is not removed. The first layer14may be removed by using a conventional etching process. The etching is performed such that the first layer14is selectively removed as compared to the hard mask layer16. In one embodiment, etching can be performed as a wet etch using a diluted NH4OH solution. In one embodiment, the diluted NH4OH solution has at least 10 parts H2O and H2O2 for each part NH4OH, and in a particular embodiment, the diluted NH4OH solution has at least 100 parts H2O and H2O2 for each part NH4OH. In another embodiment, etching can be performed as a dry etch.

After the exposed portion of the first layer14is removed, the remaining portion of the hard mask layer16within the PMOS portion11is removed, as illustrated inFIG. 3. The hard mask layer16may be removed by using a conventional etching process. The etching is performed such that the hard mask layer16is selectively removed as compared to the first layer14and the gate dielectric layer12. In one embodiment, etching can be performed as a wet etch using a dilute HF solution. In one embodiment, the dilute HF solution has at least 10 parts H2O for each part HF, and in a particular embodiment, the dilute HF solution has at least 100 parts H2O for each part HF. In another embodiment, etching can be performed as a dry etch.

FIG. 4includes an illustration of cross-sectional views of the portions of the substrate inFIG. 3after adding a patterned mask layer over a portion of the substrate10in accordance with one embodiment. A dopant mask42is formed over the gate dielectric layer12within the NMOS portion13, as illustrated inFIG. 4. The dopant mask42can be formed using any one or more conventional techniques for forming a resist mask. In one embodiment, the process is substantially the same as described for the resist mask18. The thickness of the dopant mask42is sufficient to substantially prevent a significant amount of ions from reaching the channel region directly under the gate dielectric layer12within the NMOS portion13during a subsequent ion implantation44. In one embodiment, the dopant mask42includes a photoresist material and has a thickness in a range of approximately 100 to 1000 nm.

After the impurity has been introduced, the dopant mask42is removed. If the dopant mask includes a resist material, the dopant mask42can be removed using a conventional ashing technique. If the dopant mask42includes a hard mask layer, it will be removed selective to the gate dielectric layer12and the remaining portion of the first layer14within the PMOS portion11. If desired, an optional anneal may be performed to anneal damage caused by the ion implantation. Additionally, the anneal can be used to drive dopants from the metal gate and/or the high-K dielectric layer into the channel. The optional anneal can be performed using an inert gas (e.g., N2, a noble gas, or a combination thereof), at a temperature in a range of approximately 400 to 700° C. for a time in a range of approximately 0.5 to 2 minutes. In one embodiment, the concentration of the impurity within the first layer14can be less than 10 atomic %, and in a particular embodiment, less than 3 atomic %. After completing the steps illustrated inFIG. 4, processing continues withFIG. 7.

FIG. 5includes an illustration of cross-sectional views of portions of the substrate during ion implantation in accordance with another embodiment. InFIG. 5, a second metal layer52is formed over the substrate10. the second metal-containing gate layer52comprises at least one of TiN, TiAlN, TaAlN, TaN, TaSiN, TaSi, TaC, NiSi, WxNy, MoxNy, MoSixNy, RuO2, IrO2, MoSiO, MoSiON, MoHfO, MoHfO, MoHfON, and other transition metal containing materials. An amorphous silicon layer70is formed over the second metal layer52. Note that layer70may also comprise polysilicon or may also comprise a dielectric material. The thickness of amorphous silicon layer70is used to determine the depth of ion implantation before or after annealing into the channel region of both portions11and13of substrate10. The substrate10is then subjected to ion implantation44. In the embodiment ofFIG. 5, no masking layer is used and the ion implantation44is not selective to any particular portion.

FIG. 6includes an illustration of cross-sectional views of portions of the substrate during ion implantation in another alternate embodiment. InFIG. 6, a second metal layer52is formed over the substrate10and an amorphous silicon layer70is formed over the second metal layer52as disclosed above forFIG. 5. InFIG. 6, a masking layer72is formed over substrate10and patterned to mask portion13. The masking layer72can be a hard mask or photoresist. The substrate10is then subjected to ion implantation44which may then be annealed to drive the dopants into the channel region if required. The anneal may include furnace anneal, Rapid Thermal Anneal (RTA), laser anneal, or spike anneal. The masking layer72then prevents a significant amount of ions from reaching the layers below the masking layer72. The channel region below gate dielectric layer12in portion11is counter-doped by the ion implantation44to adjust the VT of the channel region. The VT can be adjusted up or down depending of the type of dopant used. The masking layer72is then removed. The dopants introduced prior to forming the masking layer72comprise at least one of boron, BF2, phosphorous, Aluminum, Gallium, Indium, Beryllium, Antimony, Calcium, and Arsenic.

FIG. 7includes an illustration of cross-sectional views of the portions of the substrate inFIG. 4after forming the remaining layers of the gate electrode stacks in accordance with an embodiment. InFIG. 7, a second layer52and a third layer54are then sequentially formed over the substrate10within the PMOS and NMOS portions11and13. The second layer52determines the work function for the gate electrode being formed within the NMOS portion13. For example, the second layer52can include TaC, TaSiN, TaN, TaSiC, HfC, NbC, TiC, NiSi, or any combination thereof. The third layer54includes one or more materials. In one embodiment, the third layer54includes heavily doped amorphous silicon or polycrystalline silicon, a metal silicide, or a combination thereof.

The layers14,52,70, and54will be subjected to a temperature of 300° C. or higher during subsequent processing acts in forming the electronic device. One such act may include a source/drain anneal that may be performed at a temperature in a  range of approximately 500-1100° C. In another embodiment, laser annealing may be performed at a temperature in a range of approximately 500 C to 1350° C. The actual materials selected for the layer14, the layer52, layer70, and the layer54can depend on potential interactions that are to be avoided between layers that contact or are adjacent to each other, particularly at elevated temperatures (i.e., significantly above room temperature). After reading this specification, skilled artisans will be able to select proper materials for the layers14,52,70, and54from a wide array of materials and still be able to avoid interactions that are undesired.

FIG. 8includes an illustration of cross-sectional views of the portions of the Substrate inFIG. 5after forming gate electrodes and source/drain regions for transistors in accordance with an embodiment. The layers within the gate stacks are patterned to form a gate electrode61within the PMOS portion11and a gate electrode63within the NMOS portion13, as illustrated inFIG. 8. The patterning is performed using a conventional technique. The gate electrode61includes portions of the layers14,52,70, and54. The gate electrode63includes portions of the layers52,70, and54. Ion implantation is performed to form P+ source/drain regions62within the PMOS portion11, and N+ source/drain regions64within the NMOS portion13. An anneal may be performed to activate the implanted dopants within the P+ and N+ source/drain regions62and64. Channel regions66and68lie within the substrate10between the P+ and N+ source/drain regions62and64. At this point in the process, a PMOS transistor and an NMOS transistor have been formed.

Although not illustrated, one or more insulating layers and one or more wiring layers are formed over the substrate10. A passivation layer and an optional alpha particle protection layer (e.g., polyimide) are deposited to form a substantially completed electronic device. Such layers and their processes for formation are conventional to skilled artisans.

Many modifications can be made to the embodiments described above. For example, the metal layer52may be formed and patterned before forming the layer14. In this embodiment, the hard mask layer16overlies the metal layer52and is used during the removal of the layer52from the PMOS portion11before the layer14is formed. In this embodiment, the layer14may be formed over the layer52before forming the layer54. In another embodiment, a lithographic sequence can be performed to remove the portion of the layer14from the NMOS portion13before the layer54is formed. Along similar lines and referring toFIG. 7, the portion of the layer52within the PMOS portion11can be removed before forming the layer54. Therefore, the layer14is not required within the NMOS portion13, and the layer52is not required within the PMOS portion11.

In still another embodiment, implantation can be performed through a sacrificial layer. For example, a sacrificial layer having a thickness of approximately 1 to 10 nm is deposited over the metal layer14within the PMOS portion11, as illustrated inFIG. 3. After forming the dopant mask42and performing the implantation, the sacrificial layer can be removed. In one embodiment the sacrificial layer includes SiO2, Si3N4, SiOxNy, or the like.

In yet another embodiment, the impurity may be incorporated using one or more dopant gases. Referring to, for example,FIG. 4, a gas including B2H6, PH3, POCl3, AsH3, or the like may be exposed to the portion of the first layer14within the PMOS portion11and the dopant mask42. If the gas exposure is performed at a temperature of approximately 50° C. or higher, the dopant mask may include an inorganic material, such as SiO2, Si3N4, SiOxNy, or the like. An optional anneal may be performed to drive the dopants from the gate electrodes and/or the gate dielectric into the channel. The dopant mask42is removed using a conventional technique. Other processing activities are performed substantially the same as previously described.

In a further embodiment, an impurity can be introduced into the second layer52within the NMOS portion13. Any one of the impurities and introduction methods as previously described with respect to the impurity for the first layer14may be used.

FIG. 9includes an illustration of cross-sectional views of the portions of the substrate10in a single-metal gate device after a masking layer is deposited and during ion implantation in accordance with an alternate embodiment. InFIG. 9, a single-metal gate electrode74is formed over the high-K gate dielectric12. The single-metal gate electrode74forms the gate electrode for both portions11and13. A masking layer76is formed over portion13. The masking layer76prevents a significant portion of the ions from the subsequent ion implantation step from reaching the channel regions of portion13. The portion11channel regions receive ions for adjusting the VTof the transistors formed in the portion11.

FIG. 10includes an illustration of cross-sectional views of the portions of the substrate ofFIG. 9after forming gate electrodes and source/drain regions for transistors in accordance with an alternate embodiment. The layers within the gate stacks are patterned to form a gate electrode80within the PMOS portion11and a gate electrode82within the NMOS portion13, as illustrated inFIG. 10. The patterning is performed using a conventional technique. The gate electrode80includes portions of the layers74and54. Likewise, the gate electrode82includes portions of the layers74and54. As described above forFIG. 8, ion implantation is performed to form P+source/drain regions62within the PMOS portion11, and N+source/drain regions64within the NMOS portion13. An anneal may be performed to activate the implanted dopants within the P+and N+source/drain regions62and64. The channel regions66and68lie within the substrate10between the P+and N+source/drain regions62and64. At this point in the process, a PMOS transistor and an NMOS transistor have been formed.

Although not illustrated, one or more insulating layers and one or more wiring layers are formed over the substrate10. A passivation layer and an optional alpha particle protection layer (e.g., polyimide) are deposited to form a substantially completed electronic device. Such layers and their processes for formation are conventional to skilled artisans. After processing of the electronic device is substantially completed, the concentration of the impurity that was introduced into the first layer14(inFIG. 4) is greater than the concentration of the same impurity within the channel region66.

Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. After reading this specification, skilled artisans will be capable of determining what activities can be used for their specific needs or desires.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that one or more modifications or one or more other changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense and any and all such modifications and other changes are intended to be included within the scope of invention.

Any one or more benefits, one or more other advantages, one or more solutions to one or more problems, or any combination thereof have been described above with regard to one or more specific embodiments. However, the benefit(s), advantage(s), solution(s) to problem(s), or any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced is not to be construed as a critical, required, or essential feature or element of any or all the claims.