A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.

BACKGROUND

Trench gate technology is commonly used for improved break down voltage characteristics in semiconductor devices, especially high voltage devices. In the trench gate technology, the gate is vertically buried in the source, typically separated by an isolation cover. Other advantages of the trench gate technology include reduced junction gate field effect transistor (JFET) effect that may be undesirable at least in some applications. However, the trench gate technology does offer some disadvantages when lower voltage configurations are desired due to a need to reduce the width of the embedded gate. Reduced Surface Field (RESURF) technology is one of the most widely-used methods for the design of lateral high-voltage, low on-resistance devices. The technique has allowed the integration of high voltage devices, ranging from 20 V to 1200 V, with bipolar and MOS transistors.

TrenchMOS (Metal Oxide Semiconductor with trench gate) semiconductor devices are commonly used for power applications. A TrenchMOS device typically includes a semiconductor substrate having a layer of epitaxially grown, doped silicon located thereon, in which is formed a trench containing a gate electrode and gate dielectric. A source region of the device is located adjacent an upper part of the trench. The device also includes a drain region, which is separated from the source region by a body region, through which the trench extends.

SUMMARY

In one embodiment process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.

In some embodiments, the process of manufacturing of the device further includes forming a layer of the first type oxide over the first vertical section, the first vertical trench and the second vertical section. The first type oxide is tetraethylorthosilicate (TEOS dielectric). The second type oxide is silicon dioxide. The first conductivity type is n-type. The second conductivity type is p-type.

In another embodiment, a device is disclosed. The device includes a substrate having an epitaxial layer of a first conductivity type. The device further includes two symmetrical and identical cells embodied in the epitaxial layer, wherein each of the two symmetrical cells including a deep trench, a Reduced Surface Field (RESURF) plate of a second conductivity type, a gate electrode embodied in the deep trench, a body region, a source region, and a drain region. The two symmetrical and identical cells are combined such that the combination shares the drain region and the RESURF plate.

In some embodiments, the deep trench is filled with an oxide and the body region is of the second conductivity type. The gate electrode in embodied in the deep trench and the gate electrode is filled with polysilicon and bound by a gate oxide. The source region is formed over the body region such that the source region fully covers the body region and each of the two symmetrical and identical cells includes a dielectric layer that substantially covers the gate electrode and the source region.

Note that figures are not drawn to scale. Intermediate steps between figure transitions have been omitted so as not to obfuscate the disclosure. Those intermediate steps are known to a person skilled in the art.

DETAILED DESCRIPTION

Many well-known fabrication steps, components, and connectors have been omitted or not described in details in the description so as not to obfuscate the present disclosure.

FIG. 1depicts a schematic of a cross sectional view of a device100fabricated using process described later in this document. The device100include a gate electrode112, a RESURF plate114, a source region102, a body region104, a gate dielectric106and a trench110that is filled with a dielectric108.

One method of fabricating such devices is to fabricate the gate electrode in a shallow trench and then create a RESURF plate by implanting p-type RESURF region at a high energy so that the RESURF plate goes deeper (to achieve high breakdown voltage (BVdss)). However, as the energy increases, the implanted species penetrates the implant mask that is put in place to protect areas other than the area through which the RESURF plate is being created. This penetration and lateral straggle of implants cause higher Rdsonthat is undesirable.

The device100may also fabricated using four terminal RESURF technology. However, the process is complex and requires special fab changes. Also, new optimization of device design may be required for different BVdssspecifications.

The fabrication of the device100according to embodiments described herein starts at a substrate200as shown inFIG. 2. Note that only a section of the substrate200is being shown. An expitaxial layer202is implanted on the top layer of the substrate200. The expitaxial layer202is n-type and may be formed using phosphorous. Other materials may be used to form this expitaxial layer202so long the material is capable of providing an n-type implant.

As depicted inFIG. 3, a photoresist layer204is formed on the surface of the expitaxial layer202. A part206of the photoresist layer206is etched using well known etching methods. The width of the part206is roughly equal to a desired width of the RESURF plate114. The REFURF plate114may be implanted or may also be formed using the process of ion deposition. It should be noted that the process described here is for the fabrication of a NMOS device. A person skilled in the art would realize that the process described herein may also be used for the fabrication of a PMOS device.

FIG. 4shows implantation of p-type epitaxial208through the part206. Boron or similar material may be used for such implantation. The photoresist layer204is then removed and as shown inFIG. 5, a second photoresist layer210is formed on the surface. The second photoresist layer210is etched in the middle. As shown inFIG. 6, the etching goes on to create a trench212. As shown inFIG. 7, the trench212is then filled with tetraethylorthosilicate (TEOS dielectric)214or a similar material. A part of the trench212is etched similar to the process shown inFIG. 6and gate oxide (e.g., silicon dioxide) is formed on the walls and bottom of the etched space. The etched space is then filled with n-type polysilicon to form the gate electrode218.

As shown inFIG. 8, a photoresist layer220is formed and a space222is etched away. Through the space222, first p-type body region104is implanted, preferably using Boron. On top of the p-type body region104, n-type source region102, using arsenic or similar material, is implanted.

As shown inFIG. 9, the photoresist layer220is removed and as shown inFIG. 10, a TEOS Dielectric layer224is deposited over the RESURF plate114, the gate electrode112and the source region102.

The process described above uses standard fabrication technologies without requiring any specialized process control or fab modifications. The process is also suitable for fabricating devices with various BVdsswithout any fabrication step changes. A higher BVdssmay be obtained compared to prior art fabrication technologies because in this process it is easier to control the size of the RESURF plate114and the size of the gate electrode112.

Above figures describes the fabrication of half cells.FIG. 11depicts a combination of such two half cells to make a transistor. The two half cells fabricated symmetrically side by side in mirrored fashion so that the two half cells share the RESURF plate114. The device can be distinguished from other devices manufactured using other techniques by the fact that there is only one channel per half cell. The region bounded by the deep trenches108is not contributing to Rdsonbut is biased at source to give a 0V RESURF shield.

Some or all of these embodiments may be combined, some may be omitted altogether, and additional process steps can be added while still achieving the products described herein. Thus, the subject matter described herein can be embodied in many different variations, and all such variations are contemplated to be within the scope of what is claimed.