METHOD FOR FORMING A SEMICONDUCTOR DEVICE

A method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductor manufacturing technology, and particularly relates to a method of manufacturing a semiconductor device.

2. Description of the Prior Art

It is known that Stress Memorization Technology (SMT) is usually performed after the source/drain (S/D) ion implantation step in the semiconductor process to induce stress on the channel area of a metal-oxide-semiconductor field effect transistor (MOSFET).

In the conventional SMT process, a stress layer and laser annealing are usually used to induce stress in the substrate, that is, the polysilicon gate under the stress layer is recrystallized by laser annealing to improve the electrical properties of the N-channel MOSFET (NMOSFET, hereinafter referred to as NMOS). The aforementioned stress layer is removed before the subsequent self-aligned silicidation process.

During the self-aligned metal silicide process, it is necessary to deposit a salicide block (SAB) layer, such as a silicon oxide layer and a silicon nitride layer. Exposure and development processes are performed to pattern the SAB layer to mask the area where the silicide layer is not needed (non-silicide region). However, the above-mentioned SMT process and self-aligned metal silicide process require multiple depositions and etchings, and the steps are relatively complicated.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved semiconductor manufacturing process that can simplify the process steps to solve the deficiencies and shortcomings of the prior art.

According to one aspect of the invention, a method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.

According to some embodiments, the SMT layer remained in the non-silicide region function acts as a salicide blocking (SAB) layer during the SAC process.

According to some embodiments, the SMT layer comprises a silicon oxide layer and a silicon nitride layer.

According to some embodiments, the stress comprises a tensile stress.

According to some embodiments, the stress is transferred by performing a laser spike anneal.

According to some embodiments, the method further comprises: performing a source/drain anneal to activate dopants in a source/drain region of the NMOS transistor and the PMOS transistor.

According to some embodiments, the source/drain anneal comprises a rapid thermal anneal (RTA).

According to some embodiments, before performing the SAC process, the method further comprises: shrinking spacers of the NMOS transistor and the PMOS transistor.

According to another aspect of the invention, a method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. The NMOS transistor comprises N-type source/drain doped regions in the semiconductor substrate, an N-channel between the N-type source/drain doped regions, an NMOS gate over the N-channel, and first spacers on sidewalls of the NMOS gate. The PMOS transistor comprises P-type source/drain doped regions in the semiconductor substrate, a P-channel between the P-type source/drain doped regions, a PMOS gate over the P-channel, and second spacers on sidewalls of the PMOS gate.

A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region, wherein the SMT layer comprises a silicon oxide layer and a silicon nitride layer is formed. The silicon nitride layer of the SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into the N-channel of the NMOS transistor. The silicon nitride layer of the SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. The silicon oxide layer is removed from the NMOS region and the PMOS region to expose the N-type source/drain doped regions and the P-type source/drain doped regions. A self-aligned silicidation (SAC) process is performed to form a salicide layer on the N-type source/drain doped regions and the P-type source/drain doped regions.

According to some embodiments, the SMT layer remained in the non-silicide region function acts as a salicide blocking (SAB) layer during the SAC process.

According to some embodiments, the stress comprises a tensile stress.

According to some embodiments, the stress is transferred by performing a laser spike anneal.

According to some embodiments, the method further comprising: performing a source/drain anneal to activate dopants in the N-type source/drain doped regions and the P-type source/drain doped regions.

According to some embodiments, the source/drain anneal comprises a rapid thermal anneal (RTA).

According to some embodiments, before performing the SAC process, the method further comprises: shrinking the first spacers of the NMOS transistor and the second spacers of the PMOS transistor.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIGS. 1 to 6, which are schematic cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown inFIG. 1, first, a semiconductor substrate10, such as a silicon substrate, is provided, but it is not limited thereto. According to an embodiment of the present invention, the semiconductor substrate10may include a fin structure, but is not limited thereto. The semiconductor substrate10comprises an NMOS region101, a PMOS region102, and a non-silicide region103. Next, an NMOS transistor20and a PMOS transistor30are formed in the NMOS region101and the PMOS region102, respectively. According to an embodiment of the present invention, the NMOS transistor20and the PMOS transistor30may be FinFETs, but are not limited thereto.

According to an embodiment of the present invention, the NMOS transistor20may include N-type source/drain doped regions202and203in the semiconductor substrate10, an N-channel205between the N-type source/drain doped regions202and203, an NMOS gate201on the N-channel205, and a first spacer206, such as a silicon nitride spacer, on the sidewall of the NMOS gate201. In addition, there may be a gate dielectric layer204between the NMOS gate201and the N-channel205, for example, a silicon dioxide layer.

According to an embodiment of the present invention, the N-type source/drain doped region202may include an N-type lightly doped drain (NLDD) region202a, and the N-type source/drain doped region203may include an N-type lightly doped drain (NLDD) region203a. The N-type channel205is located between the NLDD region202aand the NLDD region203a.

According to an embodiment of the present invention, the PMOS transistor30may include P-type source/drain doped regions302and303in the semiconductor substrate10, a P-channel305between the P-type source/drain doped regions302and303, a PMOS gate301on the P-channel305, and a second spacer306, for example, a silicon nitride spacer, on the sidewall of the PMOS gate301. In addition, there may be a gate dielectric layer304between the PMOS gate301and the P-channel305, for example, a silicon dioxide layer.

According to an embodiment of the present invention, the P-type source/drain doped region302may include a P-type lightly doped drain (PLDD) region302a, and the P-type source/drain doped region303may include a P-type lightly doped drain region303a. The P-channel305is located between the PLDD region302aand the PLDD region303a.

According to an embodiment of the present invention, at least one semiconductor structure40, such as a resistor, a capacitor, or a diode, can be formed in the non-silicide region103, but it is not limited thereto. According to an embodiment of the present invention, for example, the semiconductor structure40may include an electrode401and a third spacer406disposed on the sidewall of the electrode401.

Next, a stress memorization technique (SMT) layer50is formed to cover the NMOS region101, the PMOS region102and the non-silicide region103. According to an embodiment of the present invention, the SMT layer50conformally covers the NMOS transistor20, the PMOS transistor30and the semiconductor structure40. According to an embodiment of the present invention, the SMT layer50may include a silicon oxide layer52and a silicon nitride layer54. According to an embodiment of the present invention, the silicon oxide layer52may serve as a buffer layer, and the silicon nitride layer54may have a tensile stress.

As shown inFIG. 2, the SMT layer50is then removed from the PMOS region102. More specifically, the silicon nitride layer54of the SMT layer50is removed from the PMOS region102. For example, a photoresist pattern60is formed on the semiconductor substrate10using lithographic processes such as exposure and development. The photoresist pattern60covers the NMOS region101and the non-silicide region103to expose the PMOS region102. Next, an etching process62is performed to remove the exposed silicon nitride layer54of the SMT layer50from the PMOS region102. Subsequently, the remaining photoresist pattern60is removed. According to an embodiment of the present invention, a source/drain anneal process can then be performed to activate the dopants in the N-type source/drain doped regions202and203and the P-type source/drain doped region302and303. According to an embodiment of the present invention, the source/drain annealing process includes a rapid thermal anneal (RTA) process.

As shown inFIG. 3, a laser spike anneal process66is then performed to transfer a stress68from the SMT layer50to the N-channel205of the NMOS transistor20. According to an embodiment of the present invention, the stress68includes a tensile stress.

As shown inFIG. 4, the SMT layer50is then removed from the NMOS region101, but the SMT layer50in the non-silicide region102is left intact. For example, a photoresist pattern70is formed on the semiconductor substrate10through processes such as exposure and development. The photoresist pattern70covers the PMOS region102and the non-silicide region103to expose the NMOS region101. Then, an etching process72is performed to remove the exposed silicon nitride layer54of the SMT layer50from the NMOS region101. Subsequently, the remaining photoresist pattern70is removed.

As shown inFIG. 5, the silicon oxide layer52is then removed from the NMOS region101and the PMOS region102, revealing the N-type source/drain doped regions202,203and the P-type source/drain doped region302,303. According to an embodiment of the present invention, at this point, the non-silicide region103is still covered by the SMT layer50.

Next, a thickness reduction process may be performed on the first spacer206of the NMOS transistor20and the second spacer306of the PMOS transistor30by using, for example, dry etching or wet etching. At this point, since the non-silicide region103is still covered by the SMT layer50, the thickness of the third spacer406of the semiconductor structure40will not change. In other words, after the thickness reduction process described above, the thickness of the third spacer406of the semiconductor structure40may be greater than the thickness of the first spacer206and the second spacer306.

As shown inFIG. 6, a self-aligned silicidation (SAC) process is performed to form metal silicide layers700and800on the NMOS region101and the PMOS region102, including, metal silicide layers702and703respectively formed on the N-type source/drain doped regions202and203, metal silicide layers802and803respectively formed on the P-type source/drain doped regions302and303, and metal silicide layers701and801respectively formed on the NMOS gate201and the PMOS gate301. For example, a metal layer (not shown) is first blanket deposited. The metal layer is then subjected to heat treatment to react with the exposed silicon surface to form a silicide metal layer. Finally, the unreacted metal layer is removed.

According to an embodiment of the present invention, the metal silicide layers700and800may include nickel silicide (NiSi) or cobalt silicide (CoSi), but are not limited thereto. According to an embodiment of the present invention, during the SAC process, the SMT layer50left in the non-silicide region103is used as a salicide blocking (SAB) layer.

One advantage of the present invention is that the SMT layer50in the SMT process is also defined as the SAB layer located in the non-silicide region103, so that the non-silicide region103can be covered during the subsequent self-aligned silicidation process such that a metal silicide layer will not be formed in the non-silicide region103. Therefore, there is no need to deposit a salicide blocking layer, and the steps of etching, exposure, and development are also skipped, so that the process steps can be simplified.