Power semiconductor module

A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.

TECHNICAL FIELD

The present invention relates to a power semiconductor module including a semiconductor switching element and diode for electric power.

BACKGROUND ART

A power semiconductor module has a problem in suppressing a surge voltage that is generated when a semiconductor switching element is switched. Therefore, it is necessary to reduce the wiring inductance.

For example, Japanese Patent Laying-Open No. 2005-216876 (Patent Document 1) relates to a power semiconductor module configuring upper and lower arms of one phase by connecting in series two of a group of elements for one arm, each group formed of an IGBT (Insulated Gate Bipolar Transistor) chip and a diode chip connected antiparallel to the IGBT. The input/output terminal of the IGBT is connected to positive side DC power supply terminal, a negative side DC power supply terminal, and a load side output terminal via a copper foil pattern insulated from each other on an insulative substrate. The wire corresponding to the input/output current path of the upper arm side IGBT chip is arranged in proximity to the wire corresponding to the input/output current path of the lower arm side diode chip. Accordingly, the mutual inductance is increased, resulting in reduction in the wiring inductance.

According to Japanese Patent Laying-Open No. 2005-197433 (Patent Document 2), the positive side DC output conductor and the negative side DC output conductor are arranged at substantially the middle of the longer side direction on a rectangular insulation substrate. Further, a semiconductor element chip such as an IGBT and a diode chip are arranged at both sides so as to sandwich the conductors. Accordingly, the mutual inductance caused by the current flowing when the semiconductor element is switched is increased to reduce the total inductance value.

PRIOR ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

Problems To Be Solved By the Invention

Since the surge voltage at the time of switching becomes higher as the wiring inductance increases, a semiconductor element of high withstand voltage is required. The area of the semiconductor element is increased in proportion to the withstand voltage, leading to increase in the size and cost of the module. Moreover, EMI (Electromagnetic Magnetic Interference) will be generated externally if the surge voltage is high, which may cause erroneous operation of an external device.

Thus, reducing the wiring inductance is a critical issue. However, the effect of reducing the inductance is not sufficient by the approach disclosed in the aforementioned patent documents. The arrangement of each semiconductor element, wiring pattern, power supply terminal, and the like must be designed further carefully.

An object of the present invention is to provide a power semiconductor module that can reduce wiring inductance.

Means For Solving the Problems

The present invention is directed to a power semiconductor module, including a first insulation substrate, a conductor pattern formed on the first insulation substrate, and a plurality of first semiconductor elements and second semiconductor elements provided on the first insulation substrate. The plurality of first semiconductor elements are electrically connected parallel to each other between a positive side power supply and the conductor pattern. At least one of the plurality of first semiconductor elements is a switching element. The plurality of second semiconductor elements are electrically connected parallel to each other between a negative side power supply and the conductor pattern. At least one of the plurality of second semiconductor elements is a switching element. A plurality of first current paths between the positive side power supply and the conductor pattern running through the plurality of first semiconductor elements respectively, and a plurality of second current paths between the negative side power supply and the conductor pattern running through the plurality of second semiconductor elements respectively are aligned alternately along a periphery of the conductor pattern.

Effects of the Invention

According to the present invention, when the switching element included in the first semiconductor element is switched, a surge current flows through the second semiconductor elements located at both sides. In contrast, when the switching element included in the second semiconductor element is switched, a surge current flows through the first semiconductor elements located at both sides. Namely, a surge current flows clockwise and counterclockwise, i.e. in both directions, when viewed from the thickness direction of the substrate. Accordingly, the magnetic flux by the current will cancel each other to allow reduction in the wiring inductance.

MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail hereinafter with reference to the drawings. The same or corresponding elements have the same reference characters allotted, and description thereof will not be repeated.

First Embodiment

FIG. 1is a plan view showing a configuration of the main part of a power semiconductor module1according to a first embodiment of the present invention. InFIG. 1, the lateral direction, the vertical direction, and the direction perpendicular to the drawing sheet are taken as the X direction, the Y direction and the Z direction, respectively. The direction from the left side towards the right side in the drawing is the +X direction. The direction from the lower side towards the upper side in the drawing is the +Y direction. The direction from the back side to the top side of the drawing sheet is the +Z direction. An insulation substrate10shown inFIG. 1is arranged along the XY plane. The thickness direction of insulation substrate10corresponds to the Z direction.FIG. 1represents the state prior to coupling a P side power supply terminal26, an N side power supply terminal27, and a load side output terminal28to insulation substrate10. The arrangement of these terminals26-28will be described afterwards with reference toFIGS. 3-5.

FIG. 2is a circuit diagram corresponding to power semiconductor module1ofFIG. 1.FIG. 2also shows an example of a peripheral circuit connected to power semiconductor module1.

Referring toFIG. 2, power semiconductor module1is an inverter module of the so-called 2in1 structure. Power semiconductor module1includes a positive side (P side) power supply terminal26, a negative side (N side) power supply terminal27, a load side output terminal28, N channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors)16and18as switching elements, and diodes17and19. The MOSFET is also referred to as “MOS transistor” hereinafter.

MOS transistor16is connected between P side power supply terminal26and load side output terminal28. MOS transistor18is connected between load side output terminal28and N side power supply terminal27. In the first embodiment, MOS transistors16and18are formed using silicon carbide (SiC).

Diode17is connected parallel to MOS transistor16. Diode17has its cathode connected to P side power supply terminal26and its anode connected to load side output terminal28. In other words, diode17is connected in the reversed biased direction. Similarly, diode19is connected parallel to MOS transistor18. Diode19has its cathode connected to load side output terminal28, and its anode connected to N side power supply terminal27. In other words, diode19is connected in the reversed biased direction. Diodes17and19are free wheeling diodes allowing a current flow when MOS transistors16and18, respectively, are off In the first embodiment, Schottky barrier diodes are employed for diodes17and19.

In accordance with the above-described configuration, MOS transistor16and diode17connected to P side power supply terminal26constitute the upper arm. Semiconductor elements16and17of the upper arm are also referred to as P side semiconductor elements16and17hereinafter. Further, MOS transistor18and diode19connected to N side power supply terminal27constitute the lower arm. Semiconductor elements18and19of the lower arm are also referred to as N side semiconductor elements18and19hereinafter.

Power semiconductor module1ofFIG. 2is connected to a DC power supply41, a smoothing capacitor42, drive circuits44and45for gate driving, and an inductor43as an example of a load circuit. DC power supply41has a positive side power supply node41A connected to P side power supply terminal26, and a negative side power supply node41B connected to N side power supply terminal27. In addition, capacitor42is connected parallel to DC power supply41. Drive circuit44is connected to a gate terminal33A for MOS transistor16to control the voltage across gate terminal33A and source terminal34A. Similarly, drive circuit45is connected to a gate terminal31A for MOS transistor18to control the voltage across gate terminal31A and source terminal32A.

A specific configuration of power semiconductor module1will be described hereinafter with reference toFIG. 1. Power semiconductor module1ofFIG. 1includes a ceramic insulation substrate10such as of aluminium nitride (AlN), and conductor patterns11,12,13,14and15formed at the surface of insulation substrate10(hereinafter, also referred to as the front face), and isolated from each other. Conductor patterns11to15are formed using, for example, copper foil. Conductor patterns11and12have P side power supply terminal26solder-connected, whereas conductor patterns13and14have N side power supply terminal27solder-connected, as will be described afterwards with reference toFIGS. 3 and 4. Moreover, conductor pattern15has load side output terminal28solder-connected. The back side of the substrate (hereinafter, referred to as the rear face) has copper foil (not shown) entirely applied thereover.

As shown inFIG. 1, conductor pattern15takes a generally F-shape form, and includes convex pattern portions15A and15C protruding in the +Y direction and concave pattern portions15B and15D recessed in the −Y direction, all located alternately. Conductor patterns11to14are formed adjacent to pattern portions15A to15D, respectively, of conductor pattern15in the +Y direction, and aligned in the order of conductor patterns14,11,13and12from the −X direction towards the +X direction. In other words, conductor patterns14and13are formed adjacent to convex pattern portions15A and15C, respectively. Conductor patterns11and12are formed adjacent to concave pattern portions15B and15D, respectively.

MOS transistors16and18and diodes17and19formed as individual semiconductor chips are also mounted on the front face of insulation substrate10. MOS transistor16includes a source electrode16S and a gate electrode16G formed at the upper side of the drawing sheet (+Z direction), and a drain electrode formed at the back side of the drawing sheet (−Z direction). Similarly, MOS transistor18includes a source electrode18S and a gate electrode18G formed at the upper side of the drawing sheet (+Z direction), and a drain electrode formed at the back side of the drawing sheet (−Z direction). Diodes17and19each include an anode formed at the upper side of the drawing sheet (+Z direction), and a cathode formed at the back side of the drawing sheet (−Z direction).

The drain electrode of MOS transistor16is solder-connected on conductor pattern11. MOS transistor16is arranged in proximity to concave pattern portion15B of conductor pattern15. Concave pattern portion15B and source electrode16S of MOS transistor16are connected by a bonding wire21. Although only one bonding wire21is shown inFIG. 1to simplify the illustration, a plurality of bonding wires21to reduce the inductance are actually formed. The same applies to other bonding wires shown inFIG. 1.

The drain electrode of MOS transistor18is solder-connected to convex pattern portion15C of conductor pattern15, adjacent to conductor pattern13. MOS transistor18has a source electrode18S connected to conductor pattern13through bonding wire23.

The cathode of diode17is solder-connected on conductor pattern12. Diode17is disposed in proximity to concave pattern portion15D of conductor pattern15. Concave pattern portion15D and the anode of diode17are connected by a bonding wire22.

The cathode of diode19is solder-connected to convex pattern portion15A of conductor pattern15, adjacent to conductor pattern14. Diode19has its anode connected to conductor pattern14by bonding wire24.

In power semiconductor module1formed as set forth above, diode19, MOS transistor16, MOS transistor18, and diode17are sequentially arranged substantially linearly from the −X direction to the +X direction. In other words, semiconductor elements18and19of the N side and semiconductor elements16and17of the P side are arranged alternately, substantially linearly from the −X direction to the +X direction. In addition, P side conductor patterns11and12connected to P side power supply terminal26and N side conductor patterns13and14connected to N side power supply terminal27are arranged alternately in the order of NPNP along the periphery of conductor pattern15connected to load side output terminal28.

Focusing attention on the current path, the current path between the positive side power supply node (41A inFIG. 2) and conductor pattern15running through each of P side semiconductor elements16and17, and the current path between the negative side power supply node (41B inFIG. 2) and conductor pattern15running through each of N side semiconductor elements18and19are aligned alternately along the periphery of conductor pattern15. As a result, the inductance can be reduced, allowing suppression in the surge voltage that occurs at the time of switching of MOS transistors16and17. The reason will be described hereinafter.

Referring toFIG. 2, it is assumed that free-wheeling current46flows between inductor43identified as a load and diode17at the point of time immediately before N side MOS transistor18is turned on. At the moment MOS transistor18is turned on, the current path changes to a path flowing in sequence from DC power supply41, load inductor43, MOS transistor18, and DC power supply41. Since the voltage of the drain electrode of N side MOS transistor18suddenly changes from a high-voltage state to a low-voltage state, the voltage across P side MOS transistor16and diode17also changes suddenly. Accordingly, a displacement current47caused by the output capacitance of MOS transistor16and a displacement current48caused by the junction capacitance of diode17are generated. Displacement current47flows in the order of DC power supply41, P side MOS transistor16, N side MOS transistor18, and DC power supply41. Displacement current48flows in the order of DC power supply41, P side diode17, N side MOS transistor18, and DC power supply41. In the case where a PIN (Positive-Intrinsic-Negative) diode is employed for diode17, leakage current due to the hole accumulation effect (recovery current) will further flow to diode17. Almost no recovery current is generated in the case of the first embodiment employing a Schottky barrier diode17.

A value corresponding to multiplication of this current time change (di/dt) by the inductance will be observed as the surge voltage. The amount of current variation will become greater as the current value at the time of conduction of MOS transistor18becomes larger, and as the switching time of MOS transistor18becomes shorter. Therefore, since the amount of current variation will inevitably become larger in accordance with the higher performance of transistors, reducing the inductance becomes particularly significant in order to suppress the surge voltage.

It is to be noted that inductance includes self-inductance and mutual inductance. Self-inductance is ascribed mainly to the bonding wire. It is therefore important to shorten the length of the bonding wire to reduce the self-inductance. Mutual inductance depends greatly on the current path on the circuit pattern. The effective inductance can be reduced greatly by carefully designing the current path.

Specifically, in the case of power semiconductor module1of the first embodiment, the paths of displacement currents47and48are separated in two directions, as shown inFIG. 1. When viewed from the thickness direction of insulation substrate10(Z direction), the paths of displacement currents47and48run in opposite directions, i.e. clockwise and counterclockwise, so that the generated magnetic flux cancel each other. Moreover, the inner side area of the paths of displacement currents47and48is small since conductor patterns11to15are arranged on insulation substrate10in close proximity to each other. Therefore, the effective inductance is reduced.

The reason why clockwise current and counterclockwise current of opposite directions occur to cancel the magnetic flux is because the current path between P side conductor patterns11and12and load side conductor pattern15running through each of P side semiconductor elements16and17, and the current path between N side conductor patterns13and14and load side conductor pattern15running through each of N side semiconductor elements18and19are aligned alternately along the X direction (the direction along the periphery of conductor pattern15). In the case where P side MOS transistor16is switched, surge current flows in both directions, i.e. clockwise and counterclockwise, via N side semiconductor elements18and19located at respective sides. In contrast, when N side MOS transistor18is switched, surge current flows in both directions, i.e. clockwise and counterclockwise, via P type semiconductor elements16and17located at respective sides. It is to be noted that when the MOS transistor located at the ends in the arrangement direction of the semiconductor elements (X direction) is switched, a current will not flow in both directions, i.e. clockwise and counterclockwise. Therefore, it is desirable that diodes17and19are disposed at the ends in the arrangement direction of the semiconductor elements (X direction).

The computation result of the inductance at the current path ofFIG. 1actually using electromagnetic analysis software FAST-HENRY is 7 nH. The computation result of the inductance in the case where P side semiconductor elements16and17are located adjacent to each other and N side semiconductor elements18and19are located adjacent to each other, differing from the case shown inFIG. 1, is approximately 15 to 20 nH. Therefore, it is appreciated that power semiconductor module1of the first embodiment can have the inductance reduced approximately ½ as compared to a conventional element arrangement.

Although the above-described example is based on the case where MOS transistor18is turned on, a similar effect in reducing the inductance can be expected also in the case of turning off. However, it is to be noted that, when N side MOS transistor18is turned off, the voltage across MOS transistor18varies by the charging at the output capacitance of N side MOS transistor18and the junction capacitance of diode19. In the case of the SiC device employed in the first embodiment, charging is time-consuming since the capacitance component is great. Therefore, it is considered that the change in the voltage across MOS transistor18is so slow that a great surge current is not generated.

Power semiconductor module1of the first embodiment can also suppress outwardly generation of EMI. This is because the amount of leakage magnetic flux at a remote site becomes lower than that of a conventional case, as compared to the difference in the current path, since the flow by displacement currents47and48are clockwise and counterclockwise, i.e. in opposite directions.

In power semiconductor module1of the first embodiment, SiC is employed as the semiconductor material of MOS transistors16and18. A semiconductor of a wide bandgap typical of SiC can maintain the breakdown voltage even if the impurity concentration is increased to reduce the ON resistance. However, since increase of the impurity concentration will cause a greater output capacitance of the MOS transistor, the aforementioned displacement currents47and48generated at the time of switching will become greater. Therefore, in the case where a semiconductor of a wide bandgap is employed, a power semiconductor module1of the above-described configuration that can reduce the wiring inductance is particularly advantageous.

A specific configuration of P side power supply terminal26, N side power supply terminal27, and load side output terminal28will be described hereinafter.

FIGS. 3 and 4are diagrams to describe the arrangement of power supply terminals26and27in power semiconductor module1ofFIG. 1.FIG. 3represents the configuration of power supply terminals26and27in power semiconductor module1, initially at the time of fabrication.FIG. 4represents the configuration of power supply terminals26and27in power semiconductor module1, completed after fabrication.FIG. 4also shows the arrangement of load side output terminal28. InFIGS. 3 and 4, (A) and (B) are a plan view and a right side view, respectively.

Referring toFIGS. 3 and 4, each of P side power supply terminal26and N side power supply terminal27is formed of a metal plate having a thickness of 0.3 mm. P side power supply terminal26includes junction portions26D and26A coupled to conductor patterns11and12, respectively, bending portions26E and26B continuous to junction portions26D and26A, respectively, and a base portion26C connecting both bending portions26B and26E. Similarly, N side power supply terminal27includes junction portions27D and27A coupled to conductor patterns13and14, respectively, bending portions27E and27B continuous to junction portions27D and27A, respectively, and a base portion27C connecting both bending portions27B and27E.

The boundary between a bending portion and a junction portion and the boundary between a bending portion and the base portion are eventually bent substantially at right angles, as shown inFIG. 4. At the start of fabricating power semiconductor module1, the boundaries of bending portions26B,26E,27B and27E are hardly bent, as shown inFIG. 3. Power supply terminals26and27are attached to insulation substrate10in this state.

Specific steps in fabrication will be described hereinafter. Junction portion26A is solder-connected in proximity to the attachment site of diode17above conductor pattern12. Junction portion26D is solder-connected in proximity to the attachment site of MOS transistor16above conductor pattern11. Junction portion27A is solder-connected on conductor pattern14with just a gap required for wire bonding at the conductor pattern15side. Junction portion27D is solder-connected on conductor pattern13with just a gap required for wire bonding at the conductor pattern15side. Further, load side output terminal28is fixed by solder on insulation substrate10, partially overlapping conductor pattern15, at a site opposite to the attachment site of diode19in the Y direction.

Following the solder-connection of terminals26to28, a die-bonding step of fastening MOS transistors16and18and diodes17and19by soldering to corresponding conductor patterns is performed. Then, each electrode of MOS transistors16and18and diodes17and19is connected with a corresponding conductor pattern by a bonding wire.

Following wire bonding, bending portions26B,26E,27B and27E are bent in a direction coming closer to corresponding semiconductor elements16to19, respectively, from a distant direction, as shown inFIG. 4. In other words, each of power supply terminals26and27is bent substantially at right angles at the boundary between the bending portion and the junction portion. Furthermore, each of power supply terminals26and27is bent substantially at right angles at the boundary between the bending portion and the base portion such that base portions26C and27C are substantially parallel to insulation substrate10. Thus, power supply terminals26and27take the eventual shape. By employing the step set forth above, a wire bonding step in proximity to power supply terminals26and27, that was difficult through conventional steps, is allowed. In the wire bonding step, space corresponding to the header of the wire bonder is required at the neighborhood of the bonding site. In other words, clearance of at least 10 mm is required between power supply terminals26and27and the spot of wire bonding. Accordingly, the conventional arrangement of power supply terminal was restricted. In the first embodiment, bending portions26B,26E,27B and27E of power supply terminals26and27are located away from the spot where wire bonding is to be performed in the bonding process, and are allowed to have the bending angle modified so as to be in proximity to the spot where wire bonding is to be carried out, after the bonding process. Accordingly, a wire bonding step in proximity to power supply terminals26and27is allowed.

As a result, each of power supply terminals26and27can be arranged in close proximity to semiconductor elements16-19. Therefore, the inductance can be lowered, and the footprint of power semiconductor module1can be reduced. Moreover, conductor patterns11-15through which the main current flows can be formed short, allowing reduction in the electrostatic capacitance between conductor patterns11-15and the copper plate provided at the rear face of conductor patterns11-15for heat dispersion. By virtue of the reduction in the electrostatic capacitance, the current flowing from the main circuit to the aforementioned copper plate by electrostatic coupling can be reduced when a surge current flows at the time of switching. As a result, outwardly generation of EMI can be suppressed.

FIG. 5is a diagram to describe the arrangement of gate terminals in power semiconductor module1ofFIG. 1. Conventionally, a gate terminal is provided on the same insulation substrate where a semiconductor element is arranged. However, there is a problem that the power semiconductor module will become larger since the area of the insulation substrate is increased corresponding to the provision of a gate terminal on the insulation substrate.

Thus, power semiconductor module1of the first embodiment includes an insulation substrate30differing from insulation substrate10where semiconductor elements16-19are provided, as shown inFIG. 5. Power semiconductor module1includes insulation substrate30, conductor patterns31-34formed of copper foil on insulation substrate30, and metal gate terminals31A,33A and source terminals32A,34A, each connected by solder on conductor patterns31,33,32and34, respectively.

In order to reduce the area of installation, insulation substrate30is fixed at a position in proximity to MOS transistors16and18on insulation substrate10so as to cover a portion of conductor pattern15. Gate electrode18G of MOS transistor18and conductor pattern31are connected by a bonding wire35, whereas source electrode18S and conductor pattern32are connected by a bonding wire36. Gate electrode16G of MOS transistor16and conductor pattern33are connected by a bonding wire37, whereas source electrode16S and conductor pattern34are connected by a bonding wire38.

Since the area of insulation substrate10can be reduced by the configuration set forth above, the entire power semiconductor module1can be rendered compact. Further, since the length of the bonding wire from gate electrodes16G and18G is shortened, the wiring inductance of the gate wiring can be reduced. Since reduction in the inductance of the gate wiring leads to reduction in the overshooting voltage generated at the time of turning on MOS transistors16and18, the damage on the gate insulation film of MOS transistors16and18can be reduced.

In the actual fabrication step, insulation substrate30is attached above insulation substrate10, after conductor patterns31to34and terminals31A to34A are formed on insulation substrate30. Then, wire bonding is effected between conductor patterns31to34and MOS transistors16and18. Following wire bonding, sealing by an insulating material is performed.

According to power semiconductor module1of the first embodiment, a plurality of current paths between positive side power supply node41A and load side conductor pattern15running through P side semiconductor elements16and17respectively, and current paths between negative side power supply node41B and load side conductor pattern15running through N side semiconductor elements18and19respectively are aligned alternately along the periphery of conductor pattern15. Therefore, surge currents47and48generated when MOS transistors16and18are switched will flow clockwise and counterclockwise, differing from each other in direction, to cancel the magnetic flux, whereby the effective inductance can be reduced. Thus, the surge voltage generated when MOS transistors16and18are switched can be reduced. As a result, it is not necessary to set an excessive breakdown voltage for MOS transistors16and18in consideration of the surge voltage. A compact and economic power semiconductor module1can be provided. Furthermore, outwardly generation of EMI can be suppressed.

In the first embodiment, another semiconductor material such as Si (silicon) may be employed instead of SiC for the material of MOS transistors16and18. An advantage similar to that of SiC can be achieved even in this case.

Further, an IGBT (Insulated Gate Bipolar Transistor) may be employed instead of MOS transistors16and18as a switching element. An advantage similar to that of MOS transistors can be achieved even in this case.

Further, an advantage similar to that of the first embodiment described above can be achieved by using a PIN diode instead of the Schottky barrier diode constituting diodes17and19.

Moreover, a ribbon-type conductor may be employed instead of a bonding wire for the connection between semiconductor elements16to19and conductor patterns13to15. Alternatively, a plate-like electrode may be attached by soldering.

For the material of insulation substrate10, another ceramic material may be used instead of AlN.

Moreover, in the case where MOS transistors16and18take a vertical structure, a parasitic diode (body diode) that is inevitably formed at the MOS transistor may be employed instead of diodes17and19.

Second Embodiment

FIG. 6is a plan view showing a configuration of the main part of a power semiconductor module2according to a second embodiment of the present invention. InFIG. 6, the lateral direction, the vertical direction, and the direction perpendicular to the drawing sheet are taken as the X direction, the Y direction and the Z direction, respectively. The direction from the left side towards the right side in the drawing is the +X direction. The direction from the lower side towards the upper side in the drawing is the +Y direction. The direction from the back side to the top side of the drawing sheet is the +Z direction. An insulation substrate10shown inFIG. 6is arranged along the XY plane. The thickness direction of insulation substrate10corresponds to the Z direction.

FIG. 7is a circuit diagram corresponding to power semiconductor module2ofFIG. 6.

Referring toFIGS. 6 and 7, power semiconductor module2takes a configuration in which a plurality (three) of power semiconductor module1ofFIGS. 1 and 2are arranged in parallel. Each of upper and lower arms51to53inFIGS. 6 and 7correspond to power semiconductor module1ofFIGS. 1 and 2. Specifically, power semiconductor module2includes, as P side semiconductor elements, MOS transistors61A,61B and61C and free wheeling diodes62A,62B and62C, and as N side semiconductor elements, MOS transistors63A,63B, and63C, and free wheeling diodes64A,64B and64C. MOS transistor61A and diode62A are connected via a conductor pattern between P side power supply terminal65A and load side output terminal28. MOS transistor61B and diode62B are connected via a conductor pattern between P side power supply terminal65B and load side output terminal28. MOS transistor61C and diode62C are connected via a conductor pattern between P side power supply terminal65C and load side output terminal28. MOS transistor63A and diode64A are connected via a conductor pattern between N side power supply terminal66A and load side output terminal28. MOS transistor63B and diode64B are connected via a conductor pattern between N side power supply terminal66B and load side output terminal28. MOS transistor63C and diode64C are connected via a conductor pattern between N side power supply terminal66C and load side output terminal28. P side power supply terminals65A,65B and65C are connected to a positive side power supply node61A. N side power supply terminals66A,66B and66C are connected to a negative side power supply node41B. Load side output terminal28and a conductor pattern50connected to load side output terminal28are set in common between each of upper and lower arms51to53.FIG. 6shows conductor patterns31-34for gate terminals formed on insulation substrate10.

Likewise with the first embodiment, the above-described configuration includes the current paths between positive side power supply node41A and load side conductor pattern50running through P side semiconductor elements61A,61B,61C,62A,62B and62C respectively, and the current paths between negative side power supply node41B and load side conductor pattern50running through N side semiconductor elements63A,63B,63C,64A,64B and64C respectively, aligned alternately along the periphery of conductor pattern50. Therefore, the effective inductance can be reduced. As a result, the surge voltage generated at the time of switching MOS transistors61A,61B,61C,63A,63B and63C can be reduced. Further, diodes64A and62C are preferably arranged at the outermost side in the arrangement direction of the semiconductor elements, as shown inFIG. 6.

For the sake of simplification, each base portion of P side power supply terminals65A,65B and65C inFIG. 6may be formed integrally. Similarly, each base portion of N side power supply terminals66A,66B and66C may be formed integrally. Accordingly, only one site is required for the connection between positive side power supply node41A and the P side power supply terminal, and the connection between negative side power supply node41B and the N side power supply terminal.

Third Embodiment

FIG. 8is a plan view showing a configuration of the main part of a power semiconductor module3according to a third embodiment of the present invention. InFIG. 8, the lateral direction, the vertical direction, and the direction perpendicular to the drawing sheet are taken as the X direction, the Y direction and the Z direction, respectively. The direction from the left side towards the right side in the drawing is the +X direction. The direction from the lower side towards the upper side in the drawing is the +Y direction. The direction from the back side to the top side of the drawing sheet is the +Z direction. An insulation substrate10shown inFIG. 8is arranged along the XY plane. The thickness direction of insulation substrate10corresponds to the Z direction.

FIG. 9is a circuit diagram corresponding to power semiconductor module3ofFIG. 7.

Referring toFIGS. 8 and 9, power semiconductor module3is configured having two MOS transistors added parallel to MOS transistors16and18ofFIGS. 1 and 2, respectively. In other words, power semiconductor module3includes MOS transistors16A,16B and16C and free wheeling diode17as P side semiconductor elements, and MOS transistors18A,18B and18C and free wheeling diode19as N side semiconductor elements. MOS transistors16A,16B and16C and diode17are connected via a conductor pattern between P side power supply terminal54and load side output terminal28. Further, MOS transistors18A,18B and18C and diode19are connected via a conductor pattern between N side power supply terminal56and load side output terminal28. P side power supply terminal54is connected to positive side power supply node41A. N side power supply terminal56is connected to negative side power supply node41B. Further, a conductor pattern58connected to load side output terminal28is set in common.

Likewise with the first embodiment, the current paths between positive side power supply node41A and load side conductor pattern58running through P side semiconductor elements17,16A,16B and16C respectively, and the current paths between negative side power supply node41B and load side conductor pattern58running through N side semiconductor elements19,18A,18B and18C respectively are aligned alternately along the periphery of conductor pattern58. Therefore, the effective inductance can be reduced. As a result, the surge voltage generated at the time of switching MOS transistors16A,16B,16C,18A,18B and18C can be reduced. Further, diodes17and19are preferably arranged at the outermost side in the arrangement direction of the semiconductor elements, as shown inFIG. 8.

DESCRIPTION OF THE REFERENCE CHARACTERS