High voltage integrated circuit with high voltage junction termination region

An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n−-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2016-056061, filed on Mar. 18, 2016, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to a semiconductor device.

2. Description of the Related Art

For a high voltage integrated circuit (HVIC), an element separation scheme using a high voltage junction has been known traditionally in which a high potential side (a high side) region and a low potential side (a low side) region provided on a single semiconductor chip are electrically separated from each other by a high voltage junction termination region (HVJT) that is provided between the regions.

It is known that a high voltage n-channel metal oxide semiconductor field effect transistor (MOSFET) functioning as a level-raising circuit is arranged in the HVJT (see, for example, Japanese Laid-Open Patent Publication Nos. H9-283716 and 2005-123512). Signal transmission is executed between the high potential region and the low potential region through these level-shift circuits.

Configuration of traditional HVICs will be described.FIGS. 23, 24, 25, and 26are plan diagrams examples of a planar layout of essential portions of traditional semiconductor devices.FIGS. 23 and 24are respectively FIGS. 1 and 8 of Japanese Laid-Open Patent Publication No. H9-283716 andFIG. 26is FIG. 6 of Japanese Laid-Open Patent Publication No. 2005-123512. The traditional semiconductor device depicted inFIG. 23includes a high potential side region211and a low potential side region212on a single p−-type semiconductor substrate201, and is configured to electrically separate these regions from each other using an HVJT213. The high potential side region211is an n-type region202provided on the p−-type semiconductor substrate201. The low potential side region212is a portion of the p−-type semiconductor substrate201located farther outward (closer to the periphery of the chip) than an n−-type region203.

The HVJT213is the n−-type region203that surrounds the periphery of the n-type region202. A portion204of the p−-type semiconductor substrate201(hereinafter, referred to as “p−-type separation region”) is in between the n-type region202and the n−-type region203to have a substantially U-shaped planar layout starting from the low potential side region212and returning to the low potential side region212through the HVJT213and the high potential side region211. The p−-type separation region204electrically separates from other portions, portions202aand203aof a portion in which the n-type region202and the n−-type region203are continuous with each other. An n-channel MOSFET used as a level shifter214is arranged in the portions202aand203asurrounded by the p−-type separation region204. A reference numeral “217” denotes a parasitic diode in a region other than the level shifter214of the HVJT213(similarly inFIGS. 24 to 26).

In the traditional semiconductor device depicted inFIG. 24, a p−-type separation region205arranged in a substantially rectangular frame planar layout inside the n-type region202separates a portion202bon the outer side of the n-type region202(hereinafter, referred to as “peripheral edge portion”) and a portion on the inner side of the n-type region202(hereinafter, referred to as “central portion”) from each other. An n-channel MOSFET is arranged to be used as the level shifter214that uses a portion of the n−-type region203as a drift region. The arrangement of the high potential side region211, the low potential side region212, and the HVJT213of the traditional semiconductor device depicted inFIG. 24is same as that of the traditional semiconductor device depicted inFIG. 23(similarly inFIGS. 25 and 26).

In the traditional semiconductor device depicted inFIG. 25, a p-type separation region206arranged in a substantially C-shaped planar layout inside the n-type region202separates a portion202calong three sides of the peripheral edge portion of the n-type region202arranged in a rectangular planar layout and the central portion of the n-type region202from each other. An n-channel MOSFET is arranged to be used as the level shifter214that uses, as a drift region, a portion of the n−-type region203facing the high potential side region211sandwiching the n−-type separation region206therebetween.

A portion202dof the n-type region202along the other one side not separated by the p−-type separation region206has a potential that is fixed at the maximal potential of the high potential side region211. Resistance of a diffusion region is used as level-shift resistance, between the portion202dwhose potential is fixed at the maximal potential of the high potential side region211and the drain region not depicted of the re-channel MOSFET that constitutes the level shifter214. A reference numeral “208” denotes a p−-type region constituting a parasitic diode217.

In the traditional semiconductor device depicted inFIG. 26, a portion of the HVJT213is separated by trenches207(for example, at two points) and, in the regions each surrounded by the trench207, an n-channel MOSFET and a p-channel MOSFET are arranged that are used as the level shifters214(214aand214b). Reference numerals “215” and “216” each denote a wire.

With a configuration to use a portion of the HVJT213as the level shifter214as above, the p−-type separation regions204to206or the trenches207electrically separate the region having the inner circuits arranged therein of the high potential side region211and the level shifter214of the HVJT213from each other. High potential wiring that extends from the low potential side region212to the high potential side region211passing over the HVJT213is thereby unnecessary and the reliability is therefore high. Compared to a configuration to have the level shifter214arranged in a region other than the HVJT213, the chip size may be reduced (shrunk) by the footprint of the level shifter214.

To stably secure a high breakdown voltage, a high voltage diode, a high voltage MOSFET, and the like each often include a field plate (FP) arranged to extend on an interlayer insulating film as an edge termination structure. A resistive field plate (RFP) and the like that, inside the interlayer insulating film, includes a thin film resistive layer arranged in a spiral planar layout to surround the periphery of the high potential side region starting from the high potential side region reaching the low potential side region are known as field plates (see Japanese Laid-Open Patent Publication Nos. 2000-022175 and 2003-008009, International Patent Publication No. 2003-533886, and Japanese Patent Publication No. 5748353).

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a semiconductor device includes a first semiconductor region of a second conductivity type, selectively provided in a surface layer of a semiconductor substrate; a second semiconductor region of the second conductivity type and surrounding a periphery of the first semiconductor region; a third semiconductor region of a first conductivity type, provided to be in contact with the second semiconductor region and to surround and to be away from the first semiconductor region; a fourth semiconductor region of the second conductivity type, selectively provided in the third semiconductor region; a fifth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to face the fourth semiconductor region, the fifth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region; a gate electrode provided through a gate insulating film, on a surface of a portion of the third semiconductor region between the fourth semiconductor region and the second semiconductor region; a sixth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to be away from the fifth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region; a seventh semiconductor region of the first conductivity type, selectively provided in the first semiconductor region to be away from the fifth semiconductor region; an interlayer insulating film that covers the second semiconductor region; a first electrode electrically connected to the fifth semiconductor region, and extending on the interlayer insulating film; a second electrode electrically connected to the sixth semiconductor region or the seventh semiconductor region, and extending on the interlayer insulating film; and a third electrode electrically connected to the third semiconductor region and the fourth semiconductor region, and extending on the interlayer insulating film to face the first electrode and the second electrode. On the interlayer insulating film, an interval between the first electrode and a first portion of the third electrode, facing the fourth semiconductor region in a depth direction is larger than an interval between the second electrode and the third electrode.

In the semiconductor device, on the interlayer insulating film, the interval between the first portion and the first electrode is equal to or larger than an interval between the first electrode and a second portion other than the first portion of the third electrode.

In the semiconductor device, a third portion of the first electrode, facing the second portion of the third electrode overhangs more on the interlayer insulating film toward a side of the third electrode than a fourth portion of the first electrode, facing the first portion of the third electrode.

The semiconductor device includes a fourth electrode electrically connected to the seventh semiconductor region or the sixth semiconductor region, and extending on the interlayer insulating film, the fourth electrode being provided away from the second electrode. On the interlayer insulating film, the interval between the first portion of the third electrode and the first electrode is larger than an interval between the second portion of the third electrode and the fourth electrode.

According to another aspect of the invention, a semiconductor device includes a first semiconductor region of a second conductivity type, selectively provided in a surface layer of a semiconductor substrate; a second semiconductor region of the second conductivity type and surrounding a periphery of the first semiconductor region; a third semiconductor region of a first conductivity type, provided to be in contact with the second semiconductor region and to surround and to be away from the first semiconductor region; a fourth semiconductor region of the second conductivity type, selectively provided in the third semiconductor region; a fifth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to face the fourth semiconductor region, the fifth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region; a gate electrode provided through a gate insulating film, on a surface of a portion of the third semiconductor region between the fourth semiconductor region and the second semiconductor region; a sixth semiconductor region of the second conductivity type, selectively provided in the first semiconductor region or the second semiconductor region to be away from the fifth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the second semiconductor region; a seventh semiconductor region of the first conductivity type, selectively provided in the first semiconductor region to be away from the fifth semiconductor region; an interlayer insulating film that covers the second semiconductor region; a first electrode electrically connected to the fifth semiconductor region; a second electrode electrically connected to the sixth semiconductor region or the seventh semiconductor region; a third electrode electrically connected to the third semiconductor region and the fourth semiconductor region; and a fourth electrode provided in the interlayer insulating film between the second electrode and the third electrode. The fourth electrode has a width that is smaller at a first portion thereof that faces the fourth semiconductor region than at a second portion thereof.

In the semiconductor device, the fourth electrode connected to the second electrode and the third electrode and includes a resistive body arranged in a spiral layout so as to surround a periphery of the first semiconductor region and reach a side of the third semiconductor region from a side of the first semiconductor region.

In the semiconductor device, the fourth electrode includes a plurality of conductor layers arranged in an annular layout so as to surround a periphery of the first semiconductor region and to be away from each other.

In the semiconductor device, the fourth electrode includes polysilicon.

In the semiconductor device, the first electrode and the second electrode are arranged to be away from each other and in a layout so as to form a ring surrounding the periphery of the first semiconductor region.

In the semiconductor device, the third electrode is arranged to be away from the first electrode and the second electrode and to be positioned farther outward than the first electrode and the second electrode, the third electrode arranged in a layout so as to surround the periphery of the first semiconductor region.

DETAILED DESCRIPTION OF THE INVENTION

A configuration of a high voltage integrated circuit (HVIC) as a semiconductor device according to a first embodiment will be described.FIG. 1Ais a plan diagram of a planar layout of the semiconductor device according to the first embodiment. The planar layout refers to the planar shapes and the arrangement configuration of the components as viewed from a front surface side of a semiconductor substrate100.FIG. 1Adepicts a state of the semiconductor substrate (a semiconductor chip)100as viewed from the front surface side thereof (similarly inFIGS. 5 and 9). For example, description will be given taking an example of an HVIC that drives, of two insulated gate bipolar transistors (IGBTs) connected to each other in series and constituting a portion corresponding to one phase of an electric power converting bridge circuit, the IGBT on the high potential side (the high side) (hereinafter, referred to as “upper arm IGBT”).

The semiconductor device according to the first embodiment depicted inFIG. 1Ais an HVIC that includes a high potential side region101and a low potential side region102on the same semiconductor substrate100and that electrically separates these regions from each other using an HVJT103. The high potential side region101includes an n-type diffusion region (a first semiconductor region)1athat is arranged in a substantially rectangular planar layout. The n-type diffusion region1ais electrically connected to the maximal potential (a high-side power source potential) “H-VDD” of a high-side circuit portion not depicted. The n-type diffusion region1ahas a high-side circuit formation region1barranged therein. The high-side circuit formation region1bhas electrode pads of the high-side circuit portion arranged therein.

The high-side circuit formation region1bhas a high-side circuit portion, a configuration portion excluding an n-channel MOSFET (hereinafter, referred to as “nchMOSFET”)104of a level-raising circuit described later, and the like arranged therein. The high-side circuit portion is, for example, a complementary MOS (CMOS) circuit that operates using the high-side power source potential H-VDD as the power source potential and an emitter potential VS of the upper arm IGBT of the electric power converting bridge circuit as the reference potential (see reference numeral “146” ofFIG. 22). The configuration portion excluding the nchMOSFET104of the level-raising circuit is, for example, a level-shift resistor of the level-raising circuit.

The low potential side region102includes a portion (hereinafter, referred to as “p-type substrate region”)2of the n-type semiconductor substrate100present farther outward than the HVJT103. The p-type substrate region2has a potential that is fixed at, for example, the ground potential GND, which is the minimum potential of the HVIC. The p-type substrate region2has, for example, an n-type diffusion region not depicted to be a rear gate selectively provided, and the n-type diffusion region has the low-side circuit portion not depicted and the like arranged therein. The low-side circuit portion is a CMOS circuit that operates using a power source potential (a low side power source potential) VCC that is lower than a high-side power source potential H-VDD as the power source potential and the minimum potential of the HVIC as the reference potential.

An n−-type diffusion region (a second semiconductor region)3to be a breakdown voltage region is arranged between the n-type diffusion region1aand the p-type substrate region2. An n−-type diffusion region3is arranged in, for example, a substantially rectangular frame (ring) planar layout surrounding the periphery of the n-type diffusion region1a. The n−-type diffusion region3is electrically separated from a portion of the n-type diffusion region1aby a first p-type separation region4that is electrically connected to the ground potential GND.FIG. 1Adepicts the first p-type separation region4using a thick line (similarly inFIGS. 5, 9, 13, and 17 to 20). The n−-type diffusion region3is in contact with the n-type diffusion region1aat a portion (a second HVJT portion22described later) in which the first p-type separation region4is not present between the n−-type diffusion region3and the n-type diffusion region1a. The n−-type diffusion region3is electrically separated from the p-type diffusion region2by a second p-type separation region (a third semiconductor region)5that is electrically connected to the ground potential GND.

On the high potential side of the n−-type diffusion region3, an n+-type drain region (a fifth semiconductor region)6of the nchMOSFET104is arranged in a portion (a first HVJT portion21described later) in which the first p-type separation region4is present between the n−-type diffusion region3and the n-type diffusion region1a. When the first p-type separation region4is arranged inside the n-type diffusion region1a, the n+-type drain region6may be arranged in a portion of the n-type diffusion region1apresent farther outward than the first p-type separation region4.

On the high potential side of the n−-type diffusion region3, an n+-type pick-up region (a sixth semiconductor region)7at the high-side power source potential H-VDD is arranged in a portion (the second HVJT portion22described later) in which the first p-type separation region4is not present between the n−-type diffusion region3and the n-type diffusion region1a.FIG. 1Adepicts the border between the first and the second HVJT portions21and22using a dotted line (the same is applied toFIGS. 5 and 9). The n+-type pick-up region7may be arranged in the n-type diffusion region1a. The n+-type pick-up region7functions as a cathode contact region of a parasitic diode125of the HVJT103described later.

The first p-type separation region4is arranged in, for example, a substantially U-shaped or a substantially C-shaped planar layout that, for example, surrounds the periphery of the high-side circuit formation region1bbetween the n-type diffusion region1aand the n−-type diffusion region3. The first p-type separation region4only has to be arranged away from the second p-type separation region5, and may be arranged in the n-type diffusion region1aor may be arranged in the n−-type diffusion region3. When the first p-type separation region4is arranged in the n-type diffusion region1a, the high-side circuit formation region1bis arranged in the first p-type separation region4.

The second p-type separation region5, for example, is in contact with the n−-type diffusion region3and is arranged in a planar layout surrounding the periphery of the n−-type diffusion region3. The second p-type separation region5may be arranged inside the peripheral edge portion of the n−-type diffusion region3. The second p-type separation region5has an electrode pad at the ground potential (hereinafter, referred to as “GND pad”) arranged therein. The second p-type separation region5has a p+-type contact region8arranged therein in a substantially rectangular frame planar layout away from the n−-type diffusion region3and surrounding the periphery of the n−-type diffusion region3. The p+-type contact region8functions as an anode contact region of the parasitic diode125of the HVJT103described later.

The n−-type diffusion region3, the first and the second p-type separation regions4and5, and the p+-type contact region8are arranged in concentric circular (substantially rectangular frame) planar layouts surrounding the periphery of the high-side circuit formation region1b. The pn-junction between the second p-type separation region5and the n−-type diffusion region3forms the parasitic diode125(seeFIG. 3described later). This parasitic diode125constitutes the HVJT103. The high potential side region101and the low potential side region102may be electrically separated from each other with a high breakdown voltage by providing the HVJT103between the high potential side region101and the low potential side region102.

On the high potential side of the HVJT103, a first FP and a second FP (a first and a second electrodes)31and32are arranged away from each other. The first FP31is in contact with the n+-type drain region6of the nchMOSFET104. A contact (an electric contact portion)34between the first FP31and the n+-type drain region6is arranged in, for example, a substantially straight linear planar layout having a substantially same size (an area and a shape) as that of the n+-type drain region6. The second FP32is in contact with the n+-type pick-up region7. A contact35between the second FP32and the n+-type pick-up region7is arranged in, for example, a substantially straight linear planar layout having a substantially same size as that of the n+-type pick-up region7. The second FP32is connected to an electrode pad at the high-side power source potential (hereinafter, referred to as “H-VDD pad”). The first and the second FPs31and32each extends toward the low potential side on an interlayer insulating film not depicted, and each has a function of equalizing the surface potential distribution of the HVJT103.

On the low potential side of the HVJT103, a third FP (a third electrode)33is arranged away from the first and the second FPs31and32. The third FP33is in contact with the p+-type contact region8. A contact36between the third FP33and the p+-type contact region8is arranged in a substantially straight linear planar layout. The contact36may be arranged in plural between the third FP33and the p+-type contact region8. The third FP33is in contact with an n+-type source region (a fourth semiconductor region)9of the nchMOSFET104described later. A contact37between the third FP33and the n+-type source region9is arranged in, for example, a substantially straight linear planar layout having a substantially same size as that of the n+-type source region9. The third FP33is connected to the GND pad and has a potential that is fixed at the ground potential GND.

The third FP33extends toward the high potential side on the interlayer insulating film, and has a function of equalizing the surface potential distribution of the HVJT103. The second and the third FPs32and33respectively function as a cathode electrode and an anode electrode of the parasitic diode125of the HVJT103. InFIG. 1A, the first to the third FPs31to33are hatched portions each surrounded by a thick line frame (similarly inFIGS. 5 and 9).FIG. 1Adepicts a case where the contacts36of the third FP33are arranged at three points (in the vicinity of the n+-type source region9of the third FP33and a portion facing the n+-type pick-up region7of the second FP32sandwiching the n−-type diffusion region3therebetween) (similarlyFIGS. 5 and 9). The planar layouts of the first to the third FPs31to33will be described later in detail.

The first HVJT portion21is a portion that has the first p-type separation region4present between the n-type diffusion region1aand the n−-type diffusion region3, and that has the n-type diffusion region1aand the n−-type diffusion region3electrically separated from each other therein. The first HVJT portion21is a substantially U-shaped portion or a substantially C-shaped portion corresponding substantially to the three sides of the n−-type diffusion region3that has a substantially rectangular frame shape. The first HVJT portion21has the nchMOSFET104of the level-raising circuit arranged therein. AlthoughFIG. 1Adepicts a case where the one nchMOSFET104is arranged in the first HVJT portion21, when the nchMOSFET104is arranged in plural, preferably, the nchMOSFETs104are arranged at positions at which the distances from the second HVJT portion22are equal to each other.

The nchMOSFET104uses the n−-type diffusion region3, the second p-type separation region5, the p+-type contact region8, and the first and the third FPs31and33respectively as a drift region, a base region, a base contact region, a drain electrode, and a source electrode. The n+-type source region9of the nchMOSFET104is arranged in the second p-type separation region5to face the n+-type drain region6, and to be in contact with the p+-type contact region8. The n+-type source region9is in contact with the third FP33through the contact37as above. A gate electrode11of the nchMOSFET104is arranged in a portion between the n+-type source region9and the n−-type diffusion region3, of the second p-type separation region5.

The second HVJT portion22is a portion exclusive of the first HVJT portion21of the n−-type diffusion region3, and is a portion in which the n-type diffusion region1aand the n−-type diffusion region3are electrically connected to each other due to the absence of the first p-type separation region4between the n-type diffusion region1aand the n−-type diffusion region3. For example, the second HVJT portion22is a substantially straight linear portion corresponding to the remaining one side of the n−-type diffusion region3that has a substantially rectangular frame shape. The borders between the second HVJT portion22and the first HVJT portion21are each indicated by a vertical dashed line. In this manner, the HVJT103has the nchMOSFET104arranged therein that is integrated with the parasitic diode125.

The planar layouts of the first to the third FPs31to33will be described. The first FP31is arranged in the first HVJT portion21. The first FP31is arranged in a portion (hereinafter, referred to as “MOS region”)21aof the first HVJT portion21where at least the nchMOSFET104arranged therein. The first FP31may extend to a portion other than the MOS region21aof the first HVJT portion21(a portion not having the nchMOSFET104arrange therein) in a peripheral direction (the direction to surround the periphery of the high potential side region101) on the interlayer insulating film14. For example, the first FP31is arranged in a substantially straight linear planar layout along the one side of the n−-type diffusion region3to include the MOS region21aof the first HVJT portion21.

The second FP32is arranged in the second HVJT portion22. The second FP32may extend on the interlayer insulating film14from the second HVJT portion22to a portion other than the MOS region21aof the first HVJT portion21. For example, the second FP32is arranged in a substantially U-shaped planar layout or a substantially C-shaped planar layout along the other three sides of the n−-type diffusion region3. The first and the second FPs31and32are arranged away from each other and in one planar layout forming a substantially rectangular frame shape that surrounds the periphery of the high potential side region101, to be present farther outward than the first p-type diffusion region4. The third FP33is arranged in, for example, a substantially rectangular frame planar layout along the p+-type contact region8, at a position facing the p+-type contact region8in the depth direction, sandwiching the interlayer insulating film14therebetween.

On the interlayer insulating film14, an interval x1between a portion (hereinafter, referred to as “first portion”, a portion surrounded by a dashed-line rectangle)33aof the third FP33and facing the n+-type source region9in the depth direction, and a portion (hereinafter, referred to as “fourth portion”, a portion surrounded by a dashed-line rectangle)31aof the first FP31and facing the first portion, is larger than an interval x2between the second and the third FPs32and33(x1>x2). On the interlayer insulating film14, the interval x1between the fourth portion31aof the first FP31and the first portion33aof the third FP33is larger than an interval x3between a portion (hereinafter, referred to as “second portion”)33bof the third FP33exclusive of the first portion33aand a portion (hereinafter, referred to as “third portion”)31bof the first FP31exclusive of the fourth portion31a(x1>x3). Though not depicted, these intervals x1and x3may be equal to each other (x1=x3). The distance from the low potential side FP to the high potential side FP of the nchMOSFET104(the interval x1) is larger than the distance from the low potential side FP to the high potential side FP of the parasitic diode105of the region exclusive of the nchMOSFET104of the parasitic diode125of the HVJT103(the interval X2). The first portion33aof the third FP33is a portion of the MOS region21aof the first HVJT portion21, of the third FP33. The portion of the third FP33exclusive of the first portion33ais the portion of the third FP33exclusive of the MOS region21aof the first HVJT portion21.

To relatively increase the interval x1between the first portion33aof the third FP33and the fourth portion31aof the first FP31on the interlayer insulating film14, the interval x3between the second portion33bof the third FP33and the third portion31bof the first FP31only has to be reduced by, for example, configuring the planar shape of the third portion31bof the first FP31to be a planar shape that overhangs more toward the low potential side (periphery of the chip) than the fourth portion31adoes. A width w1bin a direction orthogonal to the longitudinal direction of the third portion31bof the first FP31(the direction parallel to the direction of the overhanging) is larger than a width w1ain the direction orthogonal to the circumferential direction of the fourth portion31aof the first FP31(w1a<w1b). The third portion31bof the first FP31may extend on the interlayer insulating film14, to have a substantially trapezoidal planar shape and a width w1cin the longitudinal direction, decreasing toward the low potential side. The interval x3between the third portion31bof the first FP31and the second portion33bof the third FP33may be reduced by causing the second portion33bof the third FP33to extend toward the high potential side. These intervals x1to x3are each set to have a dimension by which the resistance to breakdown of the nchMOSFET104may be secured to the extent that no breakdown occurs when avalanche current flows during the OFF time period.

The surface electric field of the drift region of the nchMOSFET104(the n−-type diffusion region3of the MOS region21aof the first HVJT portion21) may be alleviated by relatively increasing the interval x1between the FPs of the nchMOSFET104on the interlayer insulating film14as above. The applied voltage at which the nchMOSFET104succumbs to avalanche breakdown during the OFF time period (the OFF breakdown voltage) may thereby be configured to be relatively high. When a high voltage is applied to the H-VDD pad, the electric field concentrates at the relatively overhanging portions of the FPs (the third portion31bof the first FP31, the second FP32, and the second portion33bof the third FP33) of the parasitic diode105of the HVJT103. The parasitic diode105of the HVJT103succumbs to avalanche breakdown sooner than the nchMOSFET104does. The OFF breakdown voltage of the nchMOSFET104is therefore higher than the OFF breakdown voltage of the parasitic diode105of the HVJT103even when an interval (hereinafter, referred to as “high concentration region interval”) L1between the high concentration regions of the nchMOSFET104and an interval (hereinafter, referred to as “high concentration region interval”) L2between the high concentration regions of the parasitic diode105of the HVJT103are equal to each other.

The high concentration region interval L1of the nchMOSFET104is the interval (the width in the radial direction) between the n+-type source region9and the n+-type drain region6of the nchMOSFET104. The radial direction matches the direction in which the drift current flows (that is, the direction from the side of the high potential side region101to the side of the low potential side region102). The high concentration region interval L1of the nchMOSFET104is one factor that determines the drift length of the nchMOSFET104. The high concentration region interval L2of the parasitic diode105of the HVJT103is the interval between the cathode contact region (the n+-type pick-up region7) and the anode contact region (the p+-type contact region8) of the parasitic diode105of the HVJT103. The high concentration region interval L2of the parasitic diode105of the HVJT103is one factor that determines the drift length of the parasitic diode105of the HVJT103.

A width w2in a direction perpendicular to the longitudinal direction of the second FP32may be, for example, uniform for the overall periphery of the second FP32on the interlayer insulating film14. A width w3in a direction perpendicular to the circumferential direction of the third FP33may be, for example, uniform for the overall periphery of the third FP33on the interlayer insulating film14. The intervals each between the FPs on the interlayer insulating film14only have to satisfy “x1>x2” as above, and the distances each from the low potential side FP to the high potential side FP (the intervals x2and x3) on the interlayer insulating film14may be equal to each other in the longitudinal direction in the portion exclusive of the MOS region21aof the first HVJT portion21(x1>x2and x2=x3).

FIG. 1Bis a plan diagram of a planar layout of a semiconductor device according to a modification of the first embodiment.FIGS. 2B, 3B and 4Bare cross-sectional views corresponding toFIG. 1B. As shown inFIGS. 1B, 2B, 3B and 4B, the n+-type drain region6and the n+-type pick-up region7can be formed in the n-type diffusion region1a.

The cross-sectional structure of the HVJT103will be described.FIG. 2Ais a cross-sectional view taken along a cutting line A-A′ inFIG. 1A.FIG. 3Ais a cross-sectional view taken along a cutting line B-B′ inFIG. 1A.FIG. 4Ais a cross-sectional view taken along a cutting line C-C′ inFIG. 1A.FIG. 2Bis a cross-sectional view taken along a cutting line A-A′ inFIG. 1B.FIG. 3Bis a cross-sectional view taken along a cutting line B-B′ inFIG. 1B.FIG. 4Bis a cross-sectional view taken along a cutting line C-C′ inFIG. 1B.

For example,FIG. 2Adepicts a cross-sectional view of the MOS region21aof the first HVJT portion21.FIG. 3Adepicts a cross-sectional view of the portion other than the MOS region21aof the first HVJT portion21.FIG. 4Adepicts a cross-sectional view of the second HVJT portion22.FIG. 2Adepicts a cross-sectional view of the nchMOSFET104andFIGS. 3A and 4Aeach depict a cross-sectional view of the parasitic diode105of the HVJT103.

As depicted inFIGS. 2A to 4A, the n-type diffusion region1a, the p-type substrate region2(seeFIG. 1A), the n−-type diffusion region3, and the first and the second p-type separation regions4and5are each selectively provided in the surface layer of the front surface of the p-type semiconductor substrate100. Excluding the portions to be contacts34to37in contact with the first to the third FPs31to33, the front surface of the p-type semiconductor substrate100is covered with a local oxidation of silicon (LOCOS) film12and the interlayer insulating film14. The p-type substrate region2to be the low potential side region102is arranged farther outward than the n−-type diffusion region3. The depth of the p-type substrate region2is, for example, equal to or larger than the depth of the n−-type diffusion region3.

The n−-type diffusion region3is arranged farther outward than the n-type diffusion region1athat is the high potential side region101. The depth of the n−-type diffusion region3may be, for example, equal to the depth of the n-type diffusion region1a. The n−-type diffusion region3and the p-type region10on the rear surface side of the substrate constitute a single reduced surface field (RESURF) structure. The p-type region10on the rear surface side of the substrate is the portion that remains in a portion deeper than the n-type diffusion region1aand the n−-type diffusion region3from the front surface of the substrate, and that remains therein as a p-type region because these regions are not formed therein.

The n+-type drain region6(FIG. 2A) and the n+-type pick-up region7of the nchMOSFET104are each selectively provided away from each other on the high potential side in the surface layer on the substrate front side of the n−-type diffusion region3or the n-type diffusion region1a(FIG. 4A). The n+-type drain region6is provided in the MOS region21aof the first HVJT portion21, and the n+-type pick-up region7is provided in the second HVJT portion22. A p-type diffusion region not depicted and forming a double RESURF structure may be provided in the surface layer on the substrate front surface side of the n−-type diffusion region3. In this case, the n+-type drain region6and the n+-type pick-up region7are arranged away from the p-type diffusion region forming the double RESURF structure and are farther on the high potential side than the p-type diffusion region.

The first p-type separation region4is provided, for example, between the n-type diffusion region1aand the n−-type diffusion region3in the first HVJT portion21. The first p-type separation region4is provided at a depth reaching the p-type region10on the rear surface side of the substrate. The depth of the first p-type separation region4may be, for example, equal to the depth of the n−-type diffusion region3. The first p-type separation region4may be a portion of the p-type semiconductor substrate100remaining in a slit shape to be exposed at the front surface of the substrate from the p-type region10on the rear surface side of the substrate. To be exposed at the front surface of the substrate refers to being arranged to be in contact with the LOCOS film12.

The second p-type separation region5is arranged farther outward than the n−-type diffusion region3. The second p-type separation region5is provided at a depth reaching the p-type region10on the rear surface side of the substrate. The depth of the second p-type separation region5may be, for example, shallower than the depth of the n−-type diffusion region3. In the second p-type separation region5, the p+-type contact region8is selectively provided spanning from the first HVJT portion21to the second HVJT portion22(FIGS. 3 and 4). In the second p-type separation region5, the n+-type source region9is selectively provided of the nchMOSFET104in the MOS region21aof the first HVJT portion21(FIG. 2A).

As depicted inFIG. 2A, the planar gate horizontal nchMOSFET104is provided in the MOS region21aof the first HVJT portion21. In the MOS region21aof the first HVJT portion21, a parasitic npn-transistor106is produced that includes the n−-type diffusion region3, the second p-type separation region5, and the n+-type source region9. The n+-type source region9and the n+-type drain region6of the nchMOSFET104face each other sandwiching the n−-type diffusion region3therebetween. The gate electrode11of the nchMOSFET104is provided through a gate insulating film13on the surface of a portion of the second p-type separation region5sandwiched by the n−-type diffusion region3and the n+-type source region9. The gate electrode11may extend on the LOCOS film12that covers the n−-type diffusion region3between the gate electrode11and the n+-type drain region6.

The fourth portion31aof the first FP31is in contact with the n+-type drain region6through the contact34. The fourth portion31aof the first FP31extends toward the low potential side on the interlayer insulating film14. The first portion33aof the third FP33is in contact with the n+-type source region9through the contact37and is electrically insulated from the gate electrode11of the nchMOSFET104by the interlayer insulating film14. The first portion33aof the third FP33may be in contact with the p+-type contact region8in the MOS region21aof the first HVJT portion21. The first portion33aof the third FP33extends toward the high potential side on the interlayer insulating film14. The first portion33aof the third FP33may extend toward the high potential side more than the gate electrode11.

As depicted inFIG. 3A, in portions other than the MOS region21aof the first HVJT portion21, the n+-type source region9and the n+-type drain region6are not provided and the parasitic diode105is formed that uses the second p-type separation region5as an anode region and the n−-type diffusion region3as a cathode region. The first FP31extends on the interlayer insulating film14from the MOS region21ain the longitudinal direction (the depth direction from the page surface ofFIG. 3A). The portion of the first FP31extending from the MOS region21ais the third portion31bof the first FP31. The second portion33bof the third FP33extends from the MOS region21ain the longitudinal direction.

The third FP33is in contact only with the p+-type contact region8in the second portion33bexclusive of the MOS region21aof the first HVJT portion21, and is electrically connected to the second p-type separation region5through the p+-type contact region8. The interval x3between the first and the third FPs31and33in the portion exclusive of the MOS region21aof the first HVJT portion21is smaller than the interval x1between the first and the third FPs31and33in the MOS region21aof the first HVJT portion21. The third portion31bof the first FP31overhangs toward the low potential side, the second portion33bof the third FP33partially overhangs toward the high potential side, or these configurations may concurrently be established such that the interval x3between the first and the third FPs31and33in the portion exclusive of the MOS region21aof the first HVJT portion21becomes relatively small.

As depicted inFIG. 4A, the second HVJT portion22has the n+-type pick-up region7provided therein. The parasitic diode105is formed that uses the second p-type separation region5as an anode region and uses the n−-type diffusion region3as a cathode region. The second FP32is connected to the n+-type pick-up region7through the contact35. The second FP32extends toward the low potential side on the interlayer insulating film14. The third FP33extends from the first HVJT portion21, is in contact only with the p+-type contact region8, and is electrically connected to the second p-type separation region5through the p+-type contact region8.

On the interlayer insulating film14, the interval x2between the second and the third FPs32and33in the portion exclusive of the MOS region21aof the first HVJT portion21and the second HVJT portion22is smaller than the interval x1between the first and the third FPs31and33in the MOS region21aof the first HVJT portion21. For example, the second FP32overhangs toward the low potential side, the second portion33bof the third FP33partially overhangs toward the high potential side, or these configurations may concurrently be established such that the interval x2between the second and the third FPs32and33in the portion exclusive of the MOS region21aof the first HVJT portion21and the second HVJT portion22becomes relatively small on the interlayer insulating film14. The cross-sectional structure of the portion of the first HVJT portion21and having the second FP32extending therein is same as the cross-sectional structure formed by substituting the reference numeral “31b” ofFIG. 3Awith the reference numeral “32”.

As above, according to the first embodiment, the electric field applied to the drift region of the level shifter (for example, the nchMOSFET) may be alleviated and the OFF breakdown voltage of the level shifter may be increased to be higher than the OFF breakdown voltage of the parasitic diode of the region exclusive of the level shifter of the HVJT, by configuring the interval between the FPs of the level shifter to be larger than the interval between the FPs of the parasitic diode of the region exclusive of the level shifter of the HVJT. When a surge such as an ESD is input into the H-VDD pad during an OFF time period, the avalanche current passes mainly through the portions in which no operation of any parasitic npn-transistor is caused (the portion exclusive of the MOS region of the first HVJT portion and the second HVJT portion) to flow in the GND pad. Flow of the avalanche current in the level shifter resulting in the breakdown with the operation of the parasitic npn-transistor due to the avalanche current as the trigger thereof may be suppressed. Avalanche breakdown of the level shifter may thereby be suppressed and the surge capability of the overall semiconductor device may therefore be improved. This effect is useful especially for an HBM-model memory.

According to the first embodiment, adverse effects on electric properties such as the signal transmission are weak compared to a case where avalanche current is limited by setting the level-shift resistance to be high or the device size of the level shifter is increased, like a traditional structure. The chip area is not increased because the balance of the turn OFF capability (OFF breakdown voltage difference) between the parasitic diode of the region exclusive of the level shifter of the HVJT and the level shifter may be adjusted by adjusting the dimensions of the FPs (the overhang width). Increase of the chip area may therefore be suppressed to a maximal extent and the surge capability may be improved in an HVIC that includes an HVJT and a level shifter on a single semiconductor chip.

A configuration of a semiconductor device according to a second embodiment will be described.FIG. 5is a plan diagram of a planar layout of the semiconductor device according to the second embodiment.FIG. 6is a cross-sectional view taken along a cutting line D-D′ inFIG. 5.FIG. 7Ais a cross-sectional view taken along a cutting line E-E′ inFIG. 5.FIG. 7Bis a cross-sectional view taken along a cutting line F-F′ inFIG. 5.FIG. 8Ais a cross-sectional view taken along a cutting line O-O′ inFIG. 5.FIG. 8Bis a cross-sectional view taken along a cutting line P-P′ inFIG. 5.

The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a resistive field plate (a fourth electrode)40is included between the first and the second FPs31and32, and the third FP33.

For example, the resistive field plate40is provided in the interlayer insulating film14that covers the n−-type diffusion region3, and is electrically insulated from the first to the third FPs31to33and the gate electrode11of the nchMOSFET104by the interlayer insulating film14. The resistive field plate40is arranged, for example, more inwardly than the gate electrode11of the nchMOSFET104. The resistive field plate40is, for example, a thin film resistive layer that is arranged in a spiral planar layout surrounding the periphery of the high potential side region101to reach the side of the low potential side region102(the outer peripheral side) from the side of the high potential side region101(the inner peripheral side) and that includes a resistive material such as polysilicon (poly-Si).

As to the resistive field plate40, a high potential side end thereof is connected to the second FP32and a low potential side end thereof is connected to the third FP33at portions not depicted. A spiral wire on the innermost peripheral side of the resistive field plate40may be arranged to face the first and the second FPs31and32in the depth direction. The spiral wire on the outermost peripheral side of the resistive field plate40may be arranged to face the third FP33in the depth direction. Similar to the first to the third FPs31to33, the resistive field plate40has a function of equalizing the surface potential distribution of the HVJT103. The intervals between the first and the second FPs31and32, and the third FP33may be, for example, equal to each other in the longitudinal direction.

As to the resistive field plate40, a width w11of the spiral wire of a portion41thereof positioned in the MOS region21aof the first HVJT portion21is configured to be smaller than a width w12of the spiral wire in another portion42thereof (w11<w12). The surface electric field of an edge termination structure is thereby alleviated in the portion41positioned in the MOS region21aof the first HVJT portion21and the breakdown voltage thereof may be configured to be relatively higher than that of the HVJT103. The portion41positioned in the MOS region21aof the first HVJT portion21is the portion positioned between the n+-type drain region6and the n+-type source region9. The region whose width w11of the spiral wire is configured to be smaller than that of the other portion42(the range of the portion41positioned in the MOS region21aof the first HVJT portion21) is arranged to be positioned in a region to at least face the n+-type source region9in the direction for a drift current to flow therethrough.FIG. 5depicts the portion41of the resistive field plate40positioned in the MOS region21aof the first HVJT portion21using a line thinner than that for the other portion42. Similar to the first embodiment, the balance of the turn OFF capability between the parasitic diode105of the HVJT103and the level shifter may be adjusted by adjusting the widths w11and w12of the spiral wires of the resistive field plate40.

As above, according to the second embodiment, effects identical to those of the first embodiment may be achieved by using the resistive field plate.

A configuration of a semiconductor device according to a third embodiment will be described.FIG. 9is a plan diagram of a planar layout of the semiconductor device according to the third embodiment.FIG. 10is a cross-sectional view taken along a cutting line G-G′ inFIG. 9.FIG. 11is a cross-sectional view taken along a cutting line H-H′ inFIG. 9.FIG. 12is a cross-sectional view taken along a cutting line I-I′ inFIG. 9. The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that a capacitance coupled field plate (a fourth electrode)50is included between the first and the second FPs31and32, and the third FP33.

For example, the capacitance coupled field plate50is provided in the interlayer insulating film14that covers the n−-type diffusion region3, and is electrically insulated from the first to the third FPs31to33and the gate electrode11of the nchMOSFET104by the interlayer insulating film14. The capacitance coupled field plate50is arranged, for example, more inwardly than the gate electrode11of the nchMOSFET104. The capacitance coupled field plate50includes, for example, plural conductor layers that are arranged in concentric circular layouts surrounding the periphery of the high potential side region101and away from each other. The conductor layers are formed using a conductive material such as, for example, polysilicon and the adjacent conductor layers are capacitively coupled with each other sandwiching the interlayer insulating film14therebetween.

The conductor layer on the innermost peripheral side of the capacitance coupled field plate50is connected to the second FP32at a portion thereof not depicted, and the conductor layer on the outermost peripheral side thereof is connected to the third FP33in another portion thereof not depicted. The conductor layer on the innermost peripheral side of the capacitance coupled field plate50may be arranged to face the first and the second FPs31and32in the depth direction. The conductor layer on the outermost peripheral side of the capacitance coupled field plate50may be arranged to face the third FP33in the depth direction. Similar to the first to the third FPs31to33, the capacitance coupled field plate50has a function of equalizing the surface potential distribution of the HVJT103. The intervals between the first and the second FPs31and32, and the third FP33may be, for example, equal to each other in the longitudinal direction.

As to the capacitance coupled field plate50, a width w21of the conductor layer of a portion51thereof positioned in the MOS region21aof the first HVJT portion21is configured to be smaller than a width w22of the conductor layer in another portion52thereof (w21<w22). The surface electric field of an edge termination structure is thereby alleviated in the portion51positioned in the MOS region21aof the first HVJT portion21and the breakdown voltage thereof may be configured to be relatively higher than that of the HVJT103. The capacitance coupled field plate50has a capacitance at the portion51positioned in the MOS region21aof the first HVJT portion21that is relatively lower. The portion51positioned in the MOS region21aof the first HVJT portion21is the portion positioned between the n+-type drain region6and the n+-type source region9. The region whose width w21of the conductor layer is configured to be smaller than that of the other portion52(the range of the portion51positioned in the MOS region21aof the first HVJT portion21) is arranged to be positioned in a region to at least face the n+-type source region9in the direction for a drift current to flow therethrough.FIG. 9depicts the portion51of the capacitance coupled field plate50positioned in the MOS region21aof the first HVJT portion21using a line thinner than that for the other portion52. Similar to the first embodiment, the balance of the turn OFF capability between the parasitic diode105of the HVJT103and the level shifter may be adjusted by adjusting the widths w21and w22of the conductor layers of the capacitance coupled field plate50.

As above, according to the third embodiment, effects identical to those of the first and second embodiments may be achieved by using the capacitance coupled field plate50.

A configuration of a semiconductor device according to a fourth embodiment will be described.FIG. 13is a plan diagram of a planar layout of the semiconductor device according to the fourth embodiment.FIG. 14is a cross-sectional view taken along a cutting line J-J′ inFIG. 13.FIG. 15is a cross-sectional view taken along a cutting line K-K′ inFIG. 13.FIG. 16is a cross-sectional view taken along a cutting line M-M′ inFIG. 13. The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that the second FP32also acting as the cathode electrode of the parasitic diode125of the HVJT103is connected to the electrode pad at the emitter potential VS (hereinafter, referred to as “VS pad”) of the upper arm IGBT of the electric power converting bridge circuit.

As depicted inFIG. 13, the first to the third FPs31to33are arranged in the same planar layouts as those of the first embodiment. The second FP32connected to the VS pad and the n+-type pick-up region7connected to the H-VDD pad therefore face each other in the depth direction. In the fourth embodiment, a multilayer (in this case, two-layer) wiring electrode structure is therefore configured that is formed by arranging electrodes151to155in a lower layer of the first to the third FPs31to33through an interlayer insulating film to electrically connect the H-VDD pad and the n+-type pick-up region7to each other.FIG. 13does not depict the contact electrodes152to155and the interlayer insulating film. The configuration except for the electrode structure of the semiconductor device according to the fourth embodiment is same as that of the first embodiment (seeFIG. 1).

For example, the first FP31is electrically connected to the n+-type drain region6of the nchMOSFET104through the contact electrode of the lower layer not depicted. A contact161between the first FP31and the contact electrode is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the n+-type drain region6. The second FP32is connected to the VS pad. The second FP32is, for example, electrically connected to a p+-type region172through the contact electrode not depicted in a portion thereof that extends from the VS pad. The p+-type region172is, for example, the p+-type contact region of the nchMOSFET (see a reference numeral “134” ofFIG. 22) of the CMOS circuit constituting the high-side circuit portion that is arranged in the high-side circuit formation region1b.

A contact162between the second FP32and the contact electrode is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the p+-type region172. An electrode151connected to the H-VDD pad (hereinafter, referred to as “H-VDD electrode”) is arranged between the second FP32and the n+-type pick-up region7. The second FP32and the H-VDD electrode151are electrically insulated from each other by the interlayer insulating film. The H-VDD electrode151is in contact with the n+-type pick-up region7. A contact156between the H-VDD electrode151and the n+-type pick-up region7is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the n+-type pick-up region7.

The third FP33is electrically connected to the n+-type source region9of the nchMOSFET104through the contact electrode in the lower layer not depicted. A contact163between the third FP33and the contact electrode connected to the n+-type source region9is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the n+-type source region9. The third FP33is electrically connected to the p+-type contact region8through the contact electrode in the lower layer not depicted. A contact164between the third FP33and the contact electrode connected to the p+-type contact region8is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the p+-type contact region8.

The cross-sectional structure of the HVJT103will be described. As depicted inFIGS. 14 to 16, similarly to the first embodiment, the n-type diffusion region1a, the p-type substrate region2(seeFIG. 13), the n-type diffusion region3, the first and the second p-type separation regions4and5, the LOCOS film12, and the interlayer insulating film14are provided on the front surface side of the p-type semiconductor substrate100. The first to the third FPs31to33extend on the interlayer insulating film14similar to the first embodiment. The arrangement of the third and the fourth portions31band31aof the first FP31, the second FP32, and the first and the second portions33aand33bof the third FP33on the interlayer insulating film14is same as that of the first embodiment. The distances x1to x3from the low potential side FPs to the high potential side FPs on the interlayer insulating film14are configured for the same conditions as those of the first embodiment.

As depicted inFIG. 14, the fourth portion31aof the first FP31is in contact with the contact electrode154in the lower layer through the contact161. The contact electrode154is in contact with the n+-type drain region6of the nchMOSFET104through a contact159. The first portion33aof the third FP33is in contact with the contact electrode155in the lower layer through the contact163. The contact electrode155is in contact with the n+-type source region9of the nchMOSFET104through a contact160. The third FP33and the contact electrode155are electrically insulated from the gate electrode11of the nchMOSFET104by the interlayer insulating film14. The configuration of the nchMOSFET104is same as that of the first embodiment.

As depicted inFIGS. 15 and 16, the second portion33bof the third FP33is in contact with the contact electrode153in the lower layer through the contact164. The contact electrode153is in contact only with the p+-type contact region8through a contact158and is electrically connected to the second p-type separation region5through the p+-type contact region8. As depicted inFIG. 16, the second FP32is in contact with the contact electrode152in the lower layer through the contact162. The contact electrode152has a potential that is fixed at the source potential (that is, the potential of the VS pad) of the nchMOSFET (see the reference numeral “134” ofFIG. 22) of the CMOS circuit constituting the high-side circuit portion. The contact electrode152is in contact with the p+-type region172through the contact157.

The n+-type region172is selectively provided in the surface layer on the substrate front surface side of a p-type region171. The p-type region171is selectively provided in the surface layer on the substrate front surface side of the n-type diffusion region1ain the high-side circuit formation region1b. The p-type region171is, for example, a p-type base region of the nchMOSFET (see the reference numeral “134” ofFIG. 22) of the CMOS circuit constituting the high-side circuit portion. The configuration of the CMOS circuit constituting the high-side circuit portion exclusive of the p-type region171and the p+-type region172of the nchMOSFET is not depicted. The H-VDD electrode151is in contact with the n+-type pick-up region7through the contact156. The H-VDD electrode151faces the second FP32in the depth direction through the interlayer insulating film14.

The balance of the turn OFF capability between the parasitic diode105of the HVJT103and the level shifter may be adjusted using the width of the spiral wire of the resistive field plate or the width of the conductor layer of the capacitance coupled field plate, by applying the fourth embodiment to the second and the third embodiments. The configuration formed by applying the fourth embodiment to the second embodiment will be described as an example in the sixth embodiment described later.

As above, according to the fourth embodiment, effects identical to those of the first to the third embodiments may be achieved when the second FP also acting as the cathode electrode of the parasitic diode of the HVJT is connected to the VS pad.

A configuration of a semiconductor device according to a fifth embodiment will be described.FIG. 17is a plan diagram of a planar layout of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in that a portion (hereinafter, referred to as “second partial FP portion”)182of the second FP32also acting as the cathode electrode of the parasitic diode125of the HVJT103is separated to be connected to the VS pad. The configuration except for the connection destination of the second FP32of the semiconductor device according to the fifth embodiment is same as that of the first embodiment (seeFIG. 1).

For example, the second FP32is arranged in the same planar layout as that of the first embodiment. The second FP32is divided into two portions and includes a first partial FP portion181connected to the H-VDD pad and the second partial FP portion182connected to the VS pad. The first partial FP portion181is arranged at a position to face the n+-type pick-up region7in the depth direction sandwiching the interlayer insulating film not depicted therebetween and in, for example, a substantially straight linear planar layout along one side of the n−-type diffusion region3. The first partial FP portion181is in contact with the n+-type pick-up region7. A contact183between the first partial FP portion181and the n+-type pick-up region7is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the n+-type pick-up region7.

The second partial FP portion182is arranged in, for example, a substantial L-shape planar layout along the other two sides of the n−-type diffusion region3(the two sides other than the one side for which the first FP31is arranged and the one side for which the first partial FP portion181is arranged). The three FPs (the first FP31, and the first and the second partial FP portions181and182) are arranged away from each other on the high potential side of the HVJT103. The first FP31, and the first and the second partial FP portions181and182are arranged away from each other in a planar layout forming one substantially rectangular frame that surrounds the periphery of the high potential side region101to be farther outward than the first p-type separation region4. The second partial FP portion182is in contact with the p+-type region172in, for example, a portion thereof that extends from the VS pad.

The contact162between the second partial FP portion182and the p+-type region172is arranged in, for example, a substantially straight linear planar layout that has a substantially same size as that of the n+-type region172. The n+-type region172is, for example, the p+-type contact region of the nchMOSFET (see the reference numeral “134” ofFIG. 22) of the CMOS circuit that constitutes the high-side circuit portion arranged in the high-side circuit formation region1b. The intervals x2and x4respectively between the first and the second partial FP portions181and182, and the third FP33on the interlayer insulating film only have to be smaller than the distance (the interval x1) from the low potential side FP to the high potential side FP of the nchMOSFET104(x1>x2and x1>x4) and may be configured to have different dimensions. The widths w2and w4in the direction perpendicular to the longitudinal direction of the first and the second FP units181and182may be different from each other.

The balance of the turn OFF capability between the parasitic diode105of the HVJT103and the level shifter may be adjusted using the width of the spiral wire of the resistive field plate or the width of the conductor layer of the capacitance coupled field plate, by applying the fifth embodiment to the second and the third embodiments. The configuration formed by applying the fifth embodiment to the second embodiment will be described as an example in the sixth embodiment described later.

As above, according to the fifth embodiment, effects identical to those of the first to the fourth embodiments may also be achieved even when the second FP also acting as the cathode electrode of the parasitic diode of the HVJT is divided into two pieces to be separately connected to the H-VDD pad and the VS pad.

A configuration of a semiconductor device according to a sixth embodiment will be described.FIG. 18is a plan diagram of a planar layout of the semiconductor device according to the sixth embodiment. The semiconductor device according to the sixth embodiment is an HVIC formed by applying the fourth embodiment to the second embodiment. Similar to the second embodiment, the balance of the turn OFF capability is adjusted between the parasitic diode of the HVJT103and the level shifter, using the resistive field plate40arranged between the first and the second FPs31and32, and the third FP33. The high potential side end of the resistive field plate40may be connected to the second FP32to be configured to be at the emitter potential VS of the upper arm IGBT of the electric power converting bridge circuit, or may be connected to the H-VDD electrode151to be configured to be at the high-side power source potential H-VDD. Similar to the fourth embodiment, the multilayer (for example, two-layer) wiring electrode structure is configured that is formed by arranging electrodes in the lower layer of the first to the third FPs31to33through the interlayer insulating film to electrically connect the H-VDD pad and the n+-type pick-up region7to each other. The H-VDD electrode151is arranged in the lower layer of the second FP32.

As above, according to the sixth embodiment, effects identical to those of the fourth embodiment may be achieved using the resistive field plate.

A configuration of a semiconductor device according to a seventh embodiment will be described.FIGS. 19 and 20are plan diagrams each of a planar layout of the semiconductor device according to the seventh embodiment. The semiconductor device according to the seventh embodiment is an HVIC formed by applying the fifth embodiment to the second embodiment. Similar to the second embodiment, the balance of the turn OFF capability between the parasitic diode of the HVJT103and the level shifter is adjusted using the resistive field plate40arranged between the first FP31and the first and the second partial FP portions181and182(the second FP32), and the third FP33. The high potential side end of the resistive field plate40may be connected to the first partial FP portion181to be configured to be at the high-side power source potential H-VDD (FIG. 19) or may be connected to the second partial FP portion182to be configured to be at the emitter potential VS of the upper arm IGBT of the electric power converting bridge circuit (FIG. 20).

As above, according to the seventh embodiment, effects identical to those of the fifth embodiment may be achieved using the resistive field plate.

An example of circuit configuration of the semiconductor device according to the present invention will be described in an eighth embodiment.FIG. 21is a circuit diagram of an example of connection configuration of a general high voltage integrated circuit device.FIG. 21depicts an electric power converting device that includes a half-bridge circuit having two switching power devices (IGBTs114and115) connected to each other in series therein. The electric power converting device depicted inFIG. 21includes an HVIC120, low voltage power sources (a first and a second low voltage power sources)112and113, IGBTs114and115, free wheel diodes (FWDs)116and117, an L-load (an inductive load)118, and a capacitor119.

The electric power converting device depicted inFIG. 21alternately turns on the upper arm IGBT115and the lower arm IGBT114of the half-bridge circuit and thereby alternately outputs a high potential and a low potential from a VS terminal111that is an output terminal to supply AC power (to cause the AC power to flow) to the L-load118. The HVIC120is a driving element that complementarily turns on and off the IGBT115to be the upper arm and the IGBT114to be the lower arm of the half-bridge circuit. The HVIC120corresponds to the semiconductor device according to each of the first to the third embodiments.

When the high potential is output from the VS terminal111, the HVIC120operates the IGBTs114and115such that the upper arm IGBT115is turned on and the lower arm IGBT114is turned off. On the other hand, when the low potential is output from the VS terminal111, the HVIC120operates the IGBTs114and115such that the upper arm IGBT115is turned off and the lower arm IGBT114is turned on.

During the operation time period, the HVIC120outputs from “L-OUT” a gate signal that drives the lower arm IGBT114and that uses the ground potential as a reference. The HVIC120outputs from “H-OUT” another gate signal that drives the upper arm IGBT115and that uses the potential of the VS terminal111(the emitter potential VS of the upper arm IGBT115) as a reference. The HVIC120may have a level-shift function (the level shifter) to output the gate signal that drives the IGBT115.

The level-raising circuit produces the gate signal that drives the IGBT115, by raising the level of the input signal at the logic level input from H-IN. H-IN is connected to the gate of the CMOS circuit (the low-side circuit portion not depicted) that is a peripheral circuit on the low side (the pre-stage) of the level-raising circuit. H-IN is an input terminal that receives input of the input signal to be transmitted to the pre-stage low-side circuit portion of the level-raising circuit.

H-OUT is connected to an output terminal of the CMOS circuit (the high side portion not depicted) that is a peripheral circuit of the high side (the post-stage) of the level-raising circuit. H-OUT is connected to the gate of the upper arm IGBT115arranged in the post-stage of the HVIC120. H-OUT is an output terminal supplying the gate signal to the IGBT115. L-IN is an input terminal receiving input of an input signal to be transmitted to the CMOS circuit that supplies the gate signal to the IGBT114. The CMOS circuit supplying the gate signal to the IGBT114produces the gate signal that drives the IGBT114, based on the input signal at the logic level input from L-IN.

L-OUT is connected to the output terminal of the CMOS circuit that supplies the gate signal to the IGBT114. L-OUT is connected to the gate of the lower arm IGBT114arranged in the post-stage of the HVIC120. L-OUT is an output terminal that supplies the gate signal to the IGBT114.

H-VDD is a terminal connected to the high potential side of the low voltage power source113that uses the potential of VS as the reference thereof. L-VDD is a terminal connected to the high potential side of the low voltage power source112that uses the potential of GND as the reference thereof. VS is a terminal for an intermediate potential (a floating potential) that varies from the potential on the high potential side Vss of a high voltage power source (a main circuit power source) to the potential of GND, and is at a potential equal to that of the VS terminal111. GND is the GND terminal. The low voltage power source112is a low-side power source connected between L-VDD of the HVIC120and GND. The low voltage power source113is a high-side power source connected between H-VDD of the HVIC120and VS. In the case of a bootstrap circuit method, the low voltage power source113includes an external capacitor not depicted that is charged by an external bootstrap diode not depicted that is connected between L-VDD and H-VDD.

The emitter of the IGBT114is connected to GND that is the low potential side of the high voltage power source, and the collector thereof is connected to the emitter of the IGBT115. The collector of the IGBT115is connected to the high potential side Vss of the high voltage power source. The FWDs116and117are respectively connected in inverse-parallel to the IGBTs114and115. The connection point of the collector of the IGBT114and the emitter of the IGBT115(that is, the output terminal of the half-bridge circuit) is connected to the VS terminal111. The VS terminal111is connected to VS of the HVIC120and the L-load118. The L-load118is an AC resistor (reactance) such as, for example, a motor or lighting that operates using a bridge circuit configured by combining a half-bridge circuit (the IGBTs114and115). The capacitor119is connected between L-VDD and GND.

The circuit configuration of the level shifter will be described.FIG. 22is a circuit diagram of a configuration of the level-raising circuit.FIG. 22depicts a CMOS circuit that transmits an input signal to the level shifter and a CMOS circuit that transmits an output signal of the level shifter to the post-stage, as peripheral circuits of the level shifter. “H-IN”, “H-OUT”, “H-VDD”, “L-VDD”, “VS”, and “GND” depicted inFIG. 22correspond to H-IN, H-OUT, H-VDD, L-VDD, VS, and GND depicted inFIG. 21.

A level-raising circuit140depicted inFIG. 22includes the nchMOSFET104, a level-shift resistor142, and a diode143. The level-raising circuit140is necessary when the upper arm IGBT115of the half-bridge circuit is an n-channel IGBT. The configuration of the nchMOSFET104is same as those of the first to the third embodiments. The drain of the nchMOSFET104is connected to one end of the level-shift resistor142and the source thereof is connected to the ground. The nchMOSFET104incorporates therein a body diode141that is connected in inverse-parallel to the nchMOSFET104. The connection point of the nchMOSFET104and the level-shift resistor142is an output portion144of the level-raising circuit140.

The other end of the level-shift resistor142is connected to H-VDD. The diode143is connected in parallel to the level-shift resistor142. The diode143has a function of preventing the level-shift resistor142from generating heat and breaking down due to the heat generated when the potential of H-VDD (the high-side power source potential) becomes a potential that is significantly lower than the potential of GND (the ground potential). The diode143has a function of preventing excessive voltage from being applied to the gate of the CMOS circuit of the high-side circuit portion146described later when overvoltage is applied to H-VDD during the ON operation time period of the nchMOSFET104. A Zener diode is often used as the diode143.

A low-side circuit portion145is arranged in the pre-stage of the level-raising circuit140and a high-side circuit portion146is arranged in the post-stage thereof, as peripheral circuits of the level-raising circuit140. Both the low-side circuit portion145and the high-side circuit portion146each includes a CMOS circuit formed by complementarily connecting a pchMOSFET (a PMOS) and an nchMOSFET (an NMOS) to each other. The gate of the CMOS circuit of the low-side circuit portion145is connected to H-IN and receives input of an input signal transmitted from the HVIC120. The source of the pchMOSFET131of the CMOS circuit of the low-side circuit portion145is connected to L-VDD and the source of the nchMOSFET132thereof is connected to the ground. The low-side circuit portion145and the high-side circuit portion146may each include a transmission circuit other than the CMOS circuit.

The connection point (an output terminal) of the pchMOSFET131and the nchMOSFET132constituting the CMOS circuit of the low-side circuit portion145is connected to the gate of the nchMOSFET104and transmits the input signal to the level-raising circuit140. The gate of the CMOS circuit of the high-side circuit portion146is connected to the output portion144of the level-raising circuit140and receives input of the input signal transmitted from the level-raising circuit140. The source of the pchMOSFET133of the CMOS circuit of the high-side circuit portion146is connected to H-VDD and the source of the nchMOSFET134thereof is connected to VS. The connection point of the pchMOSFET133and the nchMOSFET134constituting the CMOS circuit of the high-side circuit portion146is connected to H-OUT and transmits the input signal to the HVIC.

In the level-raising circuit140, when the input signal from H-IN is input to the gate of the CMOS circuit of the low-side circuit portion145, the signal passes through the CMOS circuit of the low-side circuit portion145and is input to the gate of the nchMOSFET104of the level-raising circuit140. In response to the input of the input signal, the nchMOSFET104is turned on or off, and an output signal is output from the output portion144of the level-raising circuit140, and is input to the gate of the CMOS circuit of the high-side circuit portion146. In response to the input of this input signal, the CMOS circuit of the high-side circuit portion146is turned on or off, and an output signal of the CMOS circuit of the high-side circuit portion146(a signal whose level is raised by the level-raising circuit140) is output from H-OUT. This output signal is converted into a signal that uses the potential of the VS terminal111(seeFIG. 21) as the reference thereof, and the converted signal is input to the gate of the upper arm IGBT115. In response to the input of this input signal, the upper arm IGBT115of the half-bridge circuit is turned on or off.

As above, according to the eighth embodiment, the first to the seventh embodiments are applicable.

In the above, without limitation to the embodiments, the present invention may variously be modified within a scope not departing from the spirit of the invention. For example, the p-type separation region may electrically separate completely the high potential side region and the HVJT from each other (a configuration not having the second HVJT portion provided therein), or the p-type separation region may not be provided between the high potential side region and the HVJT (a configuration not having the first HVJT portion provided therein). Plural configuration portions each including the high potential side region, the low potential side region, and the HVJT may be arranged on the same semiconductor chip. The n+-type pick-up region also acting as the cathode contact region of the parasitic diode of the HVJT may be arranged in the first HVJT portion. The resistive field plate and the capacitance coupled field plate only have to be arranged in the HVJT and may be arranged in the interlayer insulating film that covers the first to the third FPs.

In the first to the third embodiments, the element separation scheme may be changed variously. For example, the high potential side region and the HVJT, and the HVJT and the low potential side region may each be electrically separated from each other by arranging a trench filled with an insulating layer instead of the p-type separation region. In the embodiments, the first conductivity type is set to be the p type and the second conductivity type is set to be the n type, however, the present invention is further implemented when the first conductivity type is set to be the n type and the second conductivity type is set to be the p type.

However, with the traditional semiconductor devices depicted inFIGS. 23 to 26, the length between predetermined regions, i.e., a factor determining the drift length, is equal for the parasitic diode217of the region exclusive of the level shifter214of the HVJT213and the level shifter214, and the OFF breakdown voltage is also equal therefor. In the parasitic diode217, the length between the predetermined regions, i.e., a factor determining the drift length, is the length (the width) in the direction in which drift current flows (the direction from the high potential side region211toward the low potential side region212) between a cathode contact region (an n+-type region at a high potential, not depicted) and an anode contact region (a p+-type region at a low potential, not depicted). In the level shifter214, the length is the length in the direction in which drift current flows between a drain region not depicted and a source region not depicted.

The following problem arises consequent to the OFF breakdown voltages of the parasitic diode217and the level shifter214being equal as above. When a surge such as electro-static discharge (ESD) is input during an OFF time period and the level shifter214and the parasitic diode217simultaneously breakdown, currents (hereinafter, referred to as “avalanche currents”) in the level shifter214and the parasitic diode217rapidly increase substantially evenly. Parasitic operation is induced (a parasitic npn-transistor is turned on) by the avalanche current in the level shifter214that includes the re-channel MOSFET and the like, and the level shifter214therefore tends to breakdown compared to the parasitic diode217.

Examples of a method for solving this problem include resolving the imbalance of the turn OFF capability between the parasitic diode217of the region exclusive of the level shifter214of the HVJT213and the level shifter214by limiting the avalanche current flowing through the level shifter214by increasing the level-shift resistance. For the level shifter214, to raise the level, a level-shift resistor is arranged therein between a drain not depicted of the level shifter214and a high-side power source (the power source to which the maximal potential of the high-side circuit portion is applied).

Examples of another method of improving the turn OFF capability of the level shifter214include improving the surge capability of the level shifter214alone by increasing the size of the level shifter214by increasing the gate width of the level shifter214or the like. In this case, however, the parasitic capacitance (output capacitance Coss) of the level shifter214is increased and the amount of variation of the potential in the level shifter214changes by dV/dt noise (variation of voltage per time applied between the source and the drain consequent to noise), and the dV/dt noise capability is thereby adversely influenced. Problems such as an increase of the chip footprint of the level shifter214and an increase of the amount of the self-heating, result from the increase of the device size of the level shifter214.

When an ESD surge is input from a high-side power source terminal of the HVJC between this terminal and the ground potential, in a human body model (HBM), a surge of about several thousand V is transitionally input. The level shifter is arranged between the high-side circuit portion and the low-side circuit portion, and operates using the high-side power source potential as the maximal potential and the ground potential as the minimum potential. The HVJC may breakdown at a level shifter portion whose resistance to breakdown is smaller than that of the HVJT when a surge exceeding the breakdown voltage of the HVIC is applied from the high-side power source of the HVIC between the power source and the ground potential.

According to the invention, the electric field applied to the drift region (a second semiconductor region) of the level shifter arranged in the HVJT (the pn-junction between the second and the third semiconductor regions) may be alleviated to a greater extent than that of the portion exclusive of the level shifter of the HVJT. The OFF breakdown voltage of the level shifter may therefore be configured to be higher than the OFF breakdown voltage of the parasitic diode in the portion other than the level shifter of the HVJT. The flow of the avalanche current in the level shifter resulting in the breakdown with the operation of the parasitic npn-transistor due to the avalanche current acting as the trigger thereof may be suppressed, and the surge current may be caused to dominantly flow in the region exclusive of the level shifter of the HVJT before the level shifter is subject to avalanche breakdown. According to the invention, the chip area is not increased because the balance of the resistance to breakdown during the OFF time period (the OFF breakdown voltage difference) of the parasitic diode of the region exclusive of the level shifter of the HVJT, and the level shifter may be adjusted by configuring the dimensions of the first to the third electrodes.

According to the semiconductor device of the present invention, in the HVIC including the HVJT and the level shifter on a single semiconductor chip, an effect is achieved in that increases of the chip area may be suppressed and the surge capability may be improved.

As described, the semiconductor device according to the present invention is useful for a high voltage integrated circuit device used in a power converting equipment, and a power supply devices such as in various industrial machines, and the like.