Method and apparatus for assembling multi-core dice using sockets with multiple sets of front side bus contacts

An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.

BACKGROUND

1. Field of the Invention

Embodiments of the invention relate to the field of semiconductor, and more specifically, to packaging.

2. Description of Related Art

Multi-core technology is a design technology in which a single physical processor contains the core logic of more than one processor. The multi-core design puts several processor cores and packages them as a single physical processor. The goal of this design is to enable a system to run more tasks simultaneously and thereby achieve greater overall system performance. Chipsets have been developed having multiple front side buses (FSBs) to provide interface to multi-core processors. Multiple-FSB chipsets provide further performance enhancement for multiprocessing systems that use multi-core processors.

The performance enhancement provided by multiple-FSB chipsets, however, is limited by the topology and design of the sockets that house the multi-core processors. Current socket design only supports a single FSB for multiprocessor systems using multi-core processors.

DESCRIPTION

An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.

One embodiment of the invention is a technique to enhance performance of multi-core processors or multiprocessor systems by using a socket with multiple sets of FSB contacts. With multiple sets of FSB contacts, the socket may house a package with more dice than prior art techniques. The number of sets of FSB contacts is compatible with the number of FSB signal groups on chipsets that are used to interface with the processors.

FIG. 1is a diagram illustrating a system100in which one embodiment of the invention can be practiced. The system100includes a processor assembly110, a graphics processor120, a memory130, an input/output controller (IOC)140, an interconnect150, an audio controller170, a mass storage interface180, and a basic input/output system (BIOS)190.

The processor assembly110is an assembly of one or more processors or processor units and one or more chipsets. It may represent a multi-core system, a multiprocessor system with a single chipset or a multiprocessor system with multiple chipsets. The processor unit or processors may be embodied in a die or dice. The die in the processor assembly110may represent a central processing unit of any type of architecture, such as processors using hyper threading, security, network, digital media technologies, single-core processors, multi-core processors, embedded processors, mobile processors, micro-controllers, digital signal processors, superscalar computers, vector processors, single instruction multiple data (SIMD) computers, complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. The chipset in the processor assembly110may be a memory controller (MC) or a chipset having multiple integrated functionalities. The chipset may provide control and configuration of memory and input/output devices such as the graphics processor120, the memory130, and the IOC140. The multiple functionalities in the chipset may include functionalities such as graphics, media, isolated execution mode, host-to-peripheral bus interface, memory control, power management, etc. The memory controller functionality in the chipset may be integrated in the processor or the die. In some embodiments, the memory controller, either internal or external to the processor, may work for all cores or processors in the processor unit. In other embodiments, it may include different portions that may work separately for different cores or processors in the processor unit.

The graphics processor120is any processor that provides graphics functionalities. The graphics processor120may also be integrated into the chipset in the processor assembly110to form a Graphics and Memory Controller (GMC). The graphics processor120may be a graphics card such as the Graphics Performance Accelerator (AGP) card, interfaced to the chipset via a graphics port such as the Accelerated Graphics Port (AGP) or a peripheral component interconnect (PCI) Express interconnect. The graphics processor120provides interface to a display monitor such as standard progressive scan monitor, television (TV)-out device, and Transition Minimized Differential Signaling (TMDS) controller. The display monitor may be any display device such as Cathode Ray Tube (CRT) monitor, TV set, Liquid Crystal Display (LCD), Flat Panel, and Digital CRT.

The memory130stores system code and data. The memory130is typically implemented with dynamic random access memory (DRAM), static random access memory (SRAM), or any other types of memories including those that do not need to be refreshed. The memory130may include multiple channels of memory devices such as DRAMs. The DRAMs may include Double Data Rate (DDR2) devices with a bandwidth of 8.5 Gigabyte per second (GB/s).

The IOC140has a number of functionalities that are designed to support I/O functions. The IOC140may also be integrated into a chipset together or separate from the chipset in the processor assembly110to perform I/O functions. The IOC140may include a number of interface and I/O functions such as peripheral component interconnect (PCI) bus interface, processor interface, interrupt controller, direct memory access (DMA) controller, power management logic, timer, system management bus (SMBus), universal serial bus (USB) interface, mass storage interface, low pin count (LPC) interface, wireless interconnect, direct media interface (DMI), etc.

The interconnect150provides interface to peripheral devices. The interconnect150may be point-to-point or connected to multiple devices. For clarity, not all interconnects are shown. It is contemplated that the interconnect150may include any interconnect or bus such as Peripheral Component Interconnect (PCI), PCI Express, Universal Serial Bus (USB), Small Computer System Interface (SCSI), serial SCSI, and Direct Media Interface (DMI), etc. The interconnect150provides interface to I/O devices1601to160K. The I/O devices1601to160Kmay include any I/O devices to perform I/O functions. Examples of I/O devices1601to160Kinclude controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphic), network card, and any other peripheral controllers.

The audio processor170may include any audio device such as microphone, speakers, amplifiers, digital-to-analog converters, analog-to-digital converter, audio codec. It may include high definition audio devices.

The mass storage interface180interfaces to mass storage devices to store archive information such as code, programs, files, data, and applications. The mass storage interface180may include SCSI, serial SCSI, Advanced Technology Attachment (ATA) (parallel and/or serial), Integrated Drive Electronics (IDE), enhanced IDE, ATA Packet Interface (ATAPI), etc. The mass storage device may include compact disk (CD) read-only memory (ROM)181, digital video/versatile disc (DVD)182, floppy drive183, hard drive184, tape drive185, and any other magnetic or optic storage devices. The mass storage device provides a mechanism to read machine-accessible media.

The BIOS190may include program or code for booting up the system. It may be implemented in non-volatile memory such as read only memory (ROM), programmable ROM, or flash memory. The BIOS190may include security features such as isolated execution mode, cryptographic operations. It may include functionalities such as initializing various components in the system (e.g., mass storage180, I/O devices1601to160K), testing memory devices, and loading the operating system (OS), etc.

FIG. 2is a diagram illustrating the processor assembly110shown inFIG. 1with a single chipset according to one embodiment of the invention. The processor assembly110includes a chipset210and two packages2201and2202.

The chipset210may be a memory controller or an integrated controller having multiple functionalities including a memory controller and a graphics processor. The chipset210interfaces to the graphics processor120, if needed, the memory130, and the IOC140shown inFIG. 1.

The chipset210has 2N front side bus (FSB) signal groups, where N is a positive integer. In the following, for illustrative purposes, N is equal to 2. The chipset210has 4 FSB signal groups2151,2152,2153, and2154. The 4 FSB signal groups may be divided into two groups. The first group includes the FSB signal groups2151and2152and the second group includes the FSB signal groups2153and2154. The FSB is the electrical interface between the chipset210and a processor in the packages2201and2202. It may be referred to as the processor bus or system bus. The FSB includes signals that carry memory, I/O transactions, and interrupt messages. In one embodiment, the FSB is implemented using Gunning Transceiver Logic (GTL), GTL Plus (GTLP or GTL+), or Assisted GTL (AGTL). The FSB may use a source synchronous transfer (SST) of address and data. The FSB may transfer data 4 times per bus clock and address 2 times per bus clock. The clock frequency of the FSB is related to the core frequency of the processors in the packages by a frequency ratio that may range from 1/15 to 1/25. For example, the bus clock frequency may range from 100 MHz to 133 MHz, and the core frequency may range from 2 GHz to 3.2 GHz. The signals on the FSB may include clock inputs, address, data, address strobes, data strobes, control, power and ground, test, etc. In one embodiment, the FSB supports 64-bit data bus.

Each of the packages2201and2202includes a number of processors or dice. In one embodiment, each of the packages2201and2202includes 2N dice. For illustrative purposes, each package is shown to have 4 dice2301to2304. For clarity, the same reference numerals2301to2304are used for the dice in both packages. Each die represents a processor. In one embodiment, each processor is a multi-core processor having M cores. For illustrative purposes, each die is shown to have two cores (M=2)2351and2352. For clarity, the same reference numerals2351and2352are used for all cores in the dice. Although it may be referred to as a dual-core die, it is understood that an M-core die may be employed, where M may be any positive integer. The 2N dice in each package are divided into two groups. The dice in each group may be joined inside the package using joined-at-bump technology. Each group is interfaced to a FSB signal group.

The packages2201and2202are installed or housed in sockets2401and2402, respectively. Each of the sockets2401and2402has N sets of contacts, or pin-outs that are matched to the FSB signal groups, referred to as N sets of FSB contacts. In one embodiment, N=2. Each group of dice in a package is connected to a FSB signal group on the chipset210via a set of FSB pint-outs on the corresponding socket. The socket2401has two sets of FSB contacts2451and2452. The socket2402has two sets of FSB contacts2453and2454.

The chipset210is interfaced to the package2201having 2N dice housed in the socket2301via the N sets of FSB contacts of the socket2301using the first N FSB signal groups of the 2N FSB signal groups. Similarly, the chipset210is interfaced to the package2202having 2N dice housed in the socket2302via the N sets of FSB contacts of the socket2302using the second N FSB signal groups of the 2N FSB signal groups. As illustrated inFIG. 2, the dice2301and2302of the package2201have their FSB signals connected to the FSB signal group2151on the chipset210via the FSB contact set2451. The dice2303and2304of the package2201have their FSB signals connected to the FSB signal group2152on the chipset210via the FSB contact set2452. The dice2301and2302of the package2202have their FSB signals connected to the FSB signal group2153on the chipset210via the FSB contact set2453. The dice2303and2304of the package2202have their FSB signals connected to the FSB signal group2154on the chipset210via the FSB contact set2454.

By having two sets of FSB contacts on each of the sockets2401and2402, the processor assembly110may support 8 dice/16 cores for the system100, for N=2. The performance gain may be doubled compared to systems using sockets that house only 2 dice and have one set of FSB contacts. Since the number of dice in each package is doubled, efficient thermal management on the sockets2401and2402may be employed. This may include having more efficient heat sinks or reducing processor clock frequency. Even if the processor frequency is reduced, the performance enhancement due to doubling the number of dice is significant. In addition, the packages2201and2202may be implemented without mix of silicon technology, resulting in low risk manufacturing.

FIG. 3is a diagram illustrating a processor assembly110with multiple chipsets according to one embodiment of the invention. The processor assembly110may include a number of circuit assemblies. For illustrative purposes, only two circuit assemblies3101and3102are shown. It is contemplated that more than two circuit assemblies may be employed.

Each of the circuit assemblies3101and3102is similar to the processor assembly110shown inFIG. 2. Therefore, many details are not repeated. The circuit assembly3101includes a chipset3201and two sockets2401and2402. The two sockets house the packages2201and2202, respectively. The chipset3201is similar to the chipset210shown inFIG. 2except that it includes a link bus interface3251. Similarly, the circuit assembly3102includes a chipset3202and two sockets2403and2404. The two sockets house the packages2203and2204, respectively. The chipset3202is similar to the chipset210shown inFIG. 2except that it includes a link bus interface3252. The chipsets3201and3202are essentially similar. Each of the link bus interfaces3251and3252provides interface to support communication between the two chipsets via a link bus330. Additional link bus interfaces may be included in each of the chipsets3201and3202if more than two circuit assemblies are used in the processor assembly110to support multiprocessor communication interface. The link bus330may be any multiprocessor or multi-core bus. Examples of the link bus330may be the Common System Interconnect (CSI) bus, Scalability Protocol (SP) bus, and Full Buffer Dual-In-Line Memory (DIMM) (FBD) bus.

FIG. 4is a diagram illustrating the socket240shown inFIGS. 2 and 3having multiple front side bus contacts according to one embodiment of the invention. The socket240includes a base410, a device seat420, a contact area430, a cover440, and a lever450.

The socket240may support dice packaged in one of a Land Grid Array (LGA) package, a Pin Grid Array (PGA) package, a micro PGA package, a Ball Grid Array (BGA) package, and a surface mount package.FIG. 4is merely for illustrative purposes. The exact design or configuration of the socket240depends on the applications, system considerations (e.g., thermal management, package size, package type).

The base410provides mechanical support for the housing that houses the package220(shown inFIG. 2). It has interface contact points at the bottom to face the interfacing component, such as a printed circuit board (PCB). The bottom contact points are soldered or attached to the PCB to interface to the FSB signal groups215of the chipset210as shown inFIG. 2.

The device seat420is a recessed area that provides a seat for the package220. The contact area430is within the device seat420and has a number of contacts or pin-outs. In particular, it includes a first FSB contact set2451and a second FSB contact set2452that are connected to two FSB signal groups2151and2152, or2153and2154. The first and second FSB signal groups may contain the FSB signals as discussed above.

The lever450has a vertical portion and a horizontal portion. It has closed and open positions. At the closed position, the vertical portion of lever450is pressed down horizontally, causing the cover440to stay flat on the device seat420and the contact area430and effectively covers the package installed in the device seat420. At the open position, the vertical portion of the lever450is moved up causing the cover440to rotate pivotably with respect to the horizontal part of the level440. Locking slots or guiding slots are available to secure or guide the lever450.

FIG. 5is a flowchart illustrating a process500to assemble a processor assembly with a single chipset according to one embodiment of the invention.

Upon START, the process500installs first package having first 2N dice in a first socket having first N sets of front side bus (FSB) contacts (Block510). Each of the first 2N dice has M cores. N and M are positive integers. In one embodiment, N=M=2. Next, the process500connects a first chipset having 2N FSB signal groups to the first socket to interface to the first package via the first N sets of FSB contacts using first N FSB signal group of the 2N FSB signal groups (Block520).

Then, the process500installs second package having second 2N dice in a second socket having second N sets of FSB contacts (Block530). Each of the second 2N dice has K cores where K is a positive integer. In one embodiment, K=2. Next, the process500connects the second socket to the first chipset to interface to second package via the second N sets of FSB contacts using second N FSB signal groups of the 2N FSB signal groups (Block540). The process500is then terminated.

FIG. 6is a flowchart illustrating a process600to assemble a processor assembly with multiple chipsets according to one embodiment of the invention.

Upon START, the process600forms a first circuit assembly having first and second sockets and a first chipset (Block610). This may be accomplished using a process similar to the process500shown inFIG. 5. Each of the first and second sockets has N sets of FSB contacts and 2N dice. The first chipset has a first link bus interface. Then, the process600forms a second circuit assembly having third and fourth sockets and a second chipset (Block620). This may be accomplished using a process similar to the process500shown inFIG. 5. Each of the third and fourth sockets has N sets of FSB contacts and 2N dice. The second chipset has a second link bus interface.

Next, the process600connects the first link interface to the second link interface via a link bus to provide communication interface between the first and second chipsets (Block630). The link bus may be any multiprocessor bus. The process600is then terminated.