Selectively grounding fill wires

The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

BACKGROUND

The present invention relates to the electrical, electronic, and computer arts, and more specifically, to semiconductor Electronic Design Automation (EDA) and the like. EDA involves the use of software tools for designing electronic systems such as integrated circuits (ICs) and printed circuit boards. Capacitive coupling between neighboring wires in advanced technology nodes results in timing/noise challenges. In some technology nodes, “fill wires” (i.e. wires not actually carrying a necessary signal) may be required due to lithography constraints. Current EDA techniques do not necessarily provide suitable techniques determining whether or not these fill wires should be floating or grounded. Fill removal has been practiced to assist timing in high metal layers.

SUMMARY

Principles of the invention provide techniques for selectively grounding fill wires. In one aspect, an exemplary method for increasing the accuracy of electronic design automation by determining whether individual ones of a plurality of fill wires in a putative integrated circuit design should be effectively grounded or floating includes, for each signal wire of a plurality of signal wires in the putative integrated circuit design adjacent to the plurality of fill wires, determining a signal sensitivity value which represents sensitivity of a given one of the plurality of signal wires to noise and timing; for each one of the plurality of fill wires in the putative integrated circuit design, determining a fill sensitivity value by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified; and selectively effectively grounding at least a portion of the fill wires based on the fill sensitivity value, to obtain a modified integrated circuit design.

In another aspect, an exemplary computer includes a memory; and at least one processor, coupled to the memory, and operative to increase the efficiency of electronic design automation by determining whether individual ones of a plurality of fill wires in a putative integrated circuit design should be effectively grounded or floating, by carrying out steps including for each signal wire of a plurality of signal wires in the putative integrated circuit design adjacent to the plurality of fill wires, determining a signal sensitivity value which represents sensitivity of a given one of the plurality of signal wires to noise and timing; for each one of the plurality of fill wires in the putative integrated circuit design, determining a fill sensitivity value by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified; and selectively effectively grounding at least a portion of the fill wires based on the fill sensitivity value, to obtain a modified integrated circuit design.

Techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of:

ability to design denser and more complicated circuits without overcompensating for negative coupling effects in timing and/or noise analyses; this may be especially beneficial in low metal layers of dense circuits where fill is required and noise issues could be large;

ability to provide noise reducing “shielding” where needed and float fill where timing is critical;

placing the fill in an optimal state can also reduce the pessimism in noise/timing simulations;

providing the designer an additional lever to fix noise and timing problems, which can lead to faster design closure.

DETAILED DESCRIPTION

One or more embodiments provide techniques for selectively grounding fill wires. As noted, capacitive coupling between neighboring wires in advanced technology nodes results in timing/noise challenges. In some technology nodes, “fill wires” (i.e. wires not actually carrying a necessary signal) may be required due to lithography constraints. Current EDA techniques do not necessarily provide suitable techniques for determining whether these fill wires should be floating or grounded nor how to ground them when needed; indeed, there are non-trivial issues in making such a determination. Grounded fill can help reduce noise effects due to capacitive coupling, but may slow a circuit's switching speed (also referred to as timing). In the prior art, grounded nets have been used as “shielding” to protect noise sensitive wires. Floating fill can cause increased coupling to aggressor signals (thus hurting noise) but may result in faster timing.

It should be noted that a fill shape can be effectively grounded by connecting it to either a ground net or a VDD (voltage supply) net. This will essentially fix its voltage to a steady value and thus cause it to appear “grounded” or unchanging by the neighboring wires. As used herein, “effectively grounding” means fixing a voltage to a steady value by connection to an actual ground (which could be a relative ground such as a chassis ground or an actual connection to the Earth) or connection to a fixed voltage such as a supply voltage terminal and an “effective ground” means anything that is fixed relative to “ground” or “at a fixed voltage relative to ground.”

One or more embodiments advantageously provide a solution that identifies the best “state” for a particular fill wire by balancing the noise and timing issues of the wires surrounding it. In one or more embodiments, this permits provision of noise reducing “shielding” where needed and float fill where timing is critical. In one or more instances, placing the fill in an optimal state can also reduce the pessimism in noise/timing simulations.

Referring now toFIG. 1, note the aggressor wire101, floating fill wire103, grounded fill wire105, and victim wire107. There is a parasitic capacitance C1between the aggressor wire and the floating fill wire; a parasitic capacitance C2between the victim wire and the floating fill wire; and a parasitic capacitance C3between the victim wire and the grounded fill wire. Noise from the aggressor wire undesirably couples into the victim wire. Floating fill increases the coupling between the victim and aggressor wires (as compared to grounded fill), thus increasing noise; however, it also decreases the total effective capacitance on the victim wire, resulting in faster timing transitions. Regarding grounded fill, grounded nets have been used as “shielding” to protect noise sensitive wires (thus decreasing noise); however, grounded fill wires increase the effective capacitance on the victim wire, resulting in slower timing transitions. It is worth noting that, technically, there is a small capacitance, not shown, between the aggressor and the victim even when a shield wire is present. However, it is much smaller than that without a shield wire, and thus is often treated as not being present.

One or more embodiments provide a methodology for calculating a “Sensitivity Value” indicating whether the collective neighboring wires are more sensitive to timing or noise and using this value to decide if the fill wire should be grounded or floating. Referring to the flow chart ofFIG. 2, which begins at201, one or more embodiments identify a noise/timing Signal Sensitivity Value (SSV) for all signal wires, as per step203. For exemplary details of step203, refer to the flow chart ofFIG. 3, which is carried out for each signal wire, until all the signal wires are complete, as per the decision block301. In step303, evaluate the projected noise status (proximity to pass vs fail). In step305, evaluate the projected timing status (proximity to pass vs fail). Optionally, divide the timing into Timing (the time it takes for a signal to traverse a circuit assuming non-switching neighbor wires) and Noise Impact On Timing (NIOT—the adjusted time it takes a signal to traverse a circuit when neighbor wires are allowed to switch and influence—i.e. add noise—to the signal). In step307, assign a sensitivity value to represent how sensitive the net is to timing versus noise. For example, a positive value indicates more noise sensitive; while a negative value indicates more timing sensitive. Optionally, weight the positive or negative value to account for the strength of coupling to fill or relative noise/timing sensitivity. In step309, save the Sensitivity Value. In one or more embodiments, noise and timing status evaluation indicates how sensitive the net is to failure due to noise and timing, respectively. The calculations can occur with varying accuracy at many points in the construction/synthesis flow. Various assumptions can be made about fill status during these calculations (e.g., ignore, assume floating, assume grounded, etc.). Optionally, timing status can be varied to account for timing with and without accounting for noise.

Consider several non-limiting exemplary SSV calculation detailed examples. In a first example, carry out the SSV calculation process early in the construction/synthesis flow. Ignore fill in the initial calculations. Use very simplistic timing/noise calculations (i.e. based on predictions of wire length, driver/sink abstracts, predicted congestion, and the like). An example sensitivity could be positive two for a long path through a congested area with poor noise tolerance gates, where the path is relatively timing insensitive. Another example sensitivity could be negative three for a short path on an extremely timing critical net in sparse area. This aspect enables prediction of fill state during initial wire synthesis and before detailed noise/timing calculations.

In a second example, carry out the SSV calculation process post construction/synthesis. Extract circuits assuming floating fill. Calculate detailed timing/noise results with extraction/timing windows and the like. In an example, the sensitivity could be plus four where a net fails, has very negative noise slack (noise slack is a metric comparing the observed noise against the maximum noise the circuit can tolerate before failure, with large negative values denoting bad failures), and very positive timing slack (timing slack is a metric comparing the observed switching time against the minimum/maximum switching time that the circuit can tolerate before failure, with large negative values denoting bad failures) because the net is failing noise and easily passing timing. Another example sensitivity could be neutral where the net easily passes noise and timing (0sensitivity because this net does not care). Still another example sensitivity could be negative one where a net has slightly positive timing slack and extremely positive noise slack, for a slightly timing sensitive case. After having assigned FSVs, selected fill wires can be retroactively grounded with more certainty about which ones to target.

Returning now toFIG. 2, in step205, identify noise/timing Fill Sensitivity Values (FSV) for all fill shapes; optionally, filter based on size and if the shapes can be grounded. For exemplary details of step205, refer to the flow chart ofFIG. 4, which is carried out for each fill wire, until all the fill wires are complete, as per the decision block401. In step403, identify coupling to neighboring signal wires. For example, identify all neighboring nets, optionally filtering neighbors based on coupling capacitance. In step405, determine a Fill Sensitivity Value (FSV) accounting for neighbor SSVs, optionally weight the FSV based on the total coupling of the Sum Sensitivity values for all neighboring nets. FSV will indicate recommended corrective action. The fill sensitivity value is recorded in step407. Regarding the corrective action, in one or more embodiments, if there is a positive value (noise sensitive), suggest grounding the fill; if there is a negative value (timing sensitive), suggest floating the fill.

In some cases, the FSV calculation can be a simple sum of neighboring SSVs. Optionally, the FSV can be a weighted sum of SSVs based on the total coupling between the fill and signal wires. Optionally, fill wires below a certain size can be ignored. Optionally, signal wires with minimal coupling to fill can be ignored. For example, in one embodiment, fill wires that contribute less than 1% of the total coupling capacitance on a victim wire may be ignored because they do not significantly impact the victim wire. Optionally, fill wires that have been identified as not amenable to grounding can be ignored. For example, fill wires so small that they cannot be connected to a metal contact from a different metal layer can be ignored because it is physically impossible or at least unfeasible to ground them. Optionally, neighboring fill wires can be included in the FSV calculation. Given the teachings herein, the skilled artisan will be able to employ a number of different strategies to identify what legal paths are available and acceptable; the examples herein are not intended to be limiting.

Returning again toFIG. 2, in step207, selectively ground fill shapes based on the FSV. For example, identify all legal floating fill ground paths. A legal floating fill ground path can be determined by starting at a segment of floating fill wire, and iteratively connecting to other fill wires (that can be connected within the design rules) until either contacting a segment of ground or VDD (supply voltage) OR exhausting all options of fill wire. For each path, use the FSVs of each segment to determine if the path should be grounded. The high-level flow chart ends at209. One or more embodiments carry out the steps iteratively until the optimal state is found. For exemplary details of step207, refer to the flow chart ofFIG. 5, which is carried out for each fill wire, until all the fill wires are complete, as per the decision block501. In step503, identify one or more valid coupling paths between the fill wire and ground and voltage supply (Vdd). In decision block507, determine whether the coupling path's cumulative FSV is positive (i.e., more noise sensitive). If NO, return to decision block501. If YES, as per step509, ground that path and return to decision block501.

There are a number of ways to identify valid coupling paths between fill and ground. For example, evaluate all fill shapes overlapping GND (ground)/Vdd (voltage supply) wires and trace all legal fill shape paths, and/or analyze only fill shapes with extremely positive FSVs (with thresholds to identify extremely positive FSVs identified through careful study of the various factors such as algorithm run time, total timing/noise benefit of changes, and the like, as will be appreciated by the skilled artisan given the teachings herein) and determine if there are legal paths to ground. Furthermore, there are many ways to determine if a particular coupling path should be effectively grounded. For example, if all fill wires on the path have positive FSVs (indicating noise sensitivity); if the sum of all FSVs is positive; and/or if the weighted sum (based on capacitance or wire length) of all FSVs is positive.

Aspects of the invention as described herein can be performed, for example, during routing, with initial estimates of noise/timing sensitivity. Refer to step911inFIG. 9, discussed elsewhere herein. In another approach, aspects of the invention as described herein can be performed, for example, after routing and full timing/noise analysis is complete; e.g., during step913inFIG. 9. Indeed, in one or more embodiments, timing/noise closure is implemented as an iterative process of carrying out detailed analysis, looking at what fails, identifying potential fixes, implementing the fixes, and reanalyzing the new circuit. It is during this iterative process that one or more embodiments disclosed herein can be applied to make things easier.

Depending on how extraction is performed, it is possible that there may only be coupling estimates assuming 1) effectively grounded fill or 2) floating fill. This will impact the noise/timing analysis and how decisions are weighted. For example, if all fill is treated as floating, then the noise analysis may be pessimistic because some of those fill wires may end up being effectively grounded in the final design. As a result, it may be appropriate to adjust how noise and timing performance are balanced when calculating an SSV.

Analysis could, for example, be provided to a designer who manually makes the final decision about fill state and implements the change (i.e. the designer sees values on the neighboring fill, letting the designer know he or she has the option of adjusting the state to change design performance). Analysis could also be performed by the system and a change could be automatically enforced.

In some cases, if NIOT data is available, then even some timing-critical nets may actually be noise sensitive. Thus, if this information is available, then the weighting and positive/negative determination may be adjusted.

Some embodiments limit which fill shapes are analyzed; for example, in some instances, the analysis can be rejected for very small shapes (i.e. shapes that contribute a very small percentage of the total capacitance as described earlier) or shapes not amenable to grounding. Given the teachings herein, the skilled artisan will appreciate which shapes are “very small” or not amendable to grounding, for purposes of this aspect.

Some embodiments limit which neighboring wires are considered for voting; for example, some embodiments reject neighboring wires based on a total coupling capacitance threshold.

Advantageously, one or more embodiments enable design of denser and more complicated circuits without overcompensating for negative coupling effects in the timing or noise analysis. This is believed to be particularly advantageous in low metal layers of dense circuits where fill is required and noise issues can be significant.

In one or more embodiments, calibration to implement an accurate voting system to come up with the best outcomes may be pertinent. Furthermore in this regard, one or more embodiments include a methodology that provides for a significant amount of customization in terms of how to assign SSVs, how to aggregate SSVs into FSVs, how to define paths to effective ground, and how to make a final decision regarding whether it is actually desirable to effectively ground a net. All of these decisions will typically impact the run time of the analysis and affect how much improvement the overall circuit achieves. Thus, it is appropriate, in one or more embodiments, to calibrate the system to ensure that, for example, ten hours of computational effort are not added in order to achieve only a few ps or mV of noise/timing performance.

One or more embodiments provide a system and/or method of identifying whether fill wires in a circuit should be floating or effectively grounded during wire synthesis/routing, based on the projected impact on one or more neighboring nets, wherein each neighboring net has been evaluated for noise and timing sensitivity, each neighboring net has been awarded a “Signal Sensitivity Value” classifying how strongly sensitive it is to either noise or timing, Signal Sensitivity Values from neighbors are aggregated to determine a “Fill Sensitivity Value” (indicating the optimal state for each piece of fill to minimize noise/timing failures), and viable paths to effective ground through floating fill are identified. In one or more embodiments, each path is evaluated to determine if any portion of the path should be effectively grounded based on the Fill Sensitivity Values along the path.

In some instances, computation is completed after the routing process is complete.

In some cases, limited extraction information is available regarding total coupling between fill shapes and neighbors.

In some embodiments, timing analysis is subcategorized into path based delay and noise based delay.

Some embodiments limit which fill shapes are analyzed.

Some instances, where a fill shape is large enough to be divided into smaller independent pieces, consider hypothetical smaller fill shapes that allow improved grounding solutions based on timing/noise tradeoff.

One or more embodiments provide a guided tradeoff between floating and effectively grounded fill explicitly as a technique for selectively improving timing or reducing coupling noise.

One or more embodiments add fill taking into account the capacitance between the fill and neighboring signal nets, and/or considering the timing and/or noise effects of the fill.

One or more embodiments improve prior art timing and metal-density-aware routing by using a tradeoff between floating fill and effectively grounded fill to help meet timing and noise-avoidance specifications.

As noted, in one or more embodiments, aspects of the invention as described herein can be performed, for example, during routing, with initial estimates of noise/timing sensitivity, or after routing and full timing/noise analysis is complete. One or more embodiments thus differ from prior art techniques where considerations to timing are made later in the design process through iterations with extraction and timing analysis. One or more embodiments are carried out without this type of prior art iteration, and/or take into account noise avoidance and/or signal delays on critical nets while the fill is being added.

Thus, it will be appreciated that one or more embodiments use fill to enhance the timing or noise response of a circuit. Indeed, one or more embodiments target specific critical nets to improve their timing and/or their noise susceptibility; and/or provide a guided tradeoff between floating and grounded fill explicitly as a means of selectively improving timing and/or reducing coupling noise.

Given the discussion thus far, it will be appreciated that in some embodiments, an exemplary method is provided for increasing the accuracy of electronic design automation by determining whether individual ones of a plurality of fill wires in a putative integrated circuit design should be effectively grounded or floating (e.g. by making a more informed design decision). Recall that, as indicated above, a fill shape can be effectively grounded by connecting it to either a ground net or a VDD net. This will essentially fix its voltage to a steady value and thus cause it to appear “grounded” or unchanging by the neighboring wires. According to an aspect of the invention, such an exemplary method includes, as per step203, for each signal wire of a plurality of signal wires in the putative integrated circuit design adjacent to the plurality of fill wires, determining a signal sensitivity value which represents sensitivity of a given one of the plurality of signal wires to noise and timing. The method further includes, as per step205, for each one of the plurality of fill wires in the putative integrated circuit design, determining a fill sensitivity value. In one or more embodiments, this is done by identifying coupling of each one of the fill wires to the adjacent signal wires, as per step403; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified, as per step405. The method still further includes, as per step207, selectively effectively grounding at least a portion of the fill wires based on the fill sensitivity value, to obtain a modified integrated circuit design.

In one or more embodiments, the determining of the signal sensitivity value includes, as per step303, for each signal wire in the putative integrated circuit design adjacent to the fill wires, evaluating a noise status including a proximity to failing a noise criterion; as per step305, for each signal wire in the putative integrated circuit design adjacent to the fill wires, evaluating a timing status including a proximity to failing a timing criterion; and, as per step307, assigning the signal sensitivity as a value with a first sign if the noise status dominates the timing status, and as a value with a second sign opposite the first sign if the timing status dominates the noise status.

In one or more embodiments, the first sign is positive and the second sign is negative. However, for the avoidance of doubt, in one or more embodiments, the selection of which sign is positive and which sign is negative is arbitrary and can be defined as desired.

One or more embodiments further include, as per step307, respectively weighting the value with the first sign or the value with the second sign based on a relative strength with which the noise status dominates the timing status or the timing status dominates the noise status.

In the determining of the fill sensitivity value, the combination aspect can include, for example, simple (i.e., unweighted) summing or weighted summing.

As noted elsewhere, in the determining of the fill sensitivity value, fill wires below a size threshold can be ignored, fill wires not amenable to effective grounding can be ignored, and/or signal wires below a coupling threshold can be ignored.

In one or more embodiments, the step of selectively effectively grounding at least the portion of the fill wires based on the fill sensitivity value, to obtain the modified integrated circuit design, includes: as at step503, for each of the fill wires, identifying at least one valid coupling path to ground or voltage supply; as per decision block507, for each of the fill wires, determining whether a cumulative fill sensitivity value of the at least one valid coupling path to ground or voltage supply indicates dominance by sensitivity to noise; and, responsive to the determining indicating the dominance by sensitivity to noise (YES branch of decision block507), effectively grounding the at least one valid coupling path as per step509. Furthermore in this regard, when seeking to effectively ground a fill shape, it may be necessary to connect to multiple pieces of metal in order to build a path all the way to a ground (or voltage supply) wire. Thus, the “coupling path” may include one or more fill shapes that need to be connected together. Accordingly, when the final decision is made regarding whether to ground a particular path, it is appropriate to consider the impact grounding will have on all of the shapes in that path. Thus, in one case, a shape that is actually timing sensitive may end up being effectively grounded, because effectively grounding the one timing-sensitive shape allows many other noise-sensitive shapes to be successfully effectively grounded.

One or more embodiments include fabricating a physical integrated circuit in accordance with the modified integrated circuit design. For example, referring toFIGS. 7-9discussed elsewhere herein, render the modified integrated circuit design in a design language; and prepare a layout based on the modified integrated circuit design rendered in the design language. Instantiate the layout as a design structure. The physical integrated circuit is then fabricated in accordance with the design structure.

Accordingly, in one or more embodiments, the layout is instantiated as a design structure. See discussion ofFIG. 7. A physical integrated circuit is then fabricated in accordance with the design structure. See again discussion ofFIG. 7. Refer also toFIG. 8. Once the physical design data is obtained, based, in part, on the analytical processes described herein, an integrated circuit designed in accordance therewith can be fabricated according to known processes that are generally described with reference toFIG. 8. Generally, a wafer with multiple copies of the final design is fabricated and cut (i.e., diced) such that each die is one copy of the integrated circuit. At block810, the processes include fabricating masks for lithography based on the finalized physical layout. At block820, fabricating the wafer includes using the masks to perform photolithography and etching. Once the wafer is diced, testing and sorting each die is performed at830to filter out any faulty die.

One or more embodiments include a computer including a memory28; and at least one processor16, coupled to the memory, and operative to carry out or otherwise facilitate any one, some, or all of the method steps described herein (as depicted inFIG. 6). In one or more embodiments, the performance (speed) of this computer is improved, for example, by the enhanced accuracy and/or reduced pessimism of the design process including techniques for determining whether to ground or float fill wires as disclosed herein. Accordingly, the amount of computer resources/CPU time needed during the design cycle, as well as the amount of human design engineer hours, can be reduced using aspects of the invention.

Furthermore, referring toFIG. 7, in one or more embodiments the at least one processor is operative to generate a design structure for the circuit design in accordance with the analysis, and in at least some embodiments, the at least one processor is further operative to control integrated circuit manufacturing equipment to fabricate a physical integrated circuit in accordance with the design structure. Thus, the layout can be instantiated as a design structure, and the design structure can be provided to fabrication equipment to facilitate fabrication of a physical integrated circuit in accordance with the design structure. The physical integrated circuit will be improved as compared to designs not using aspects of the invention for EDA. For example, the improvements can include any one, some, or all of: providing noise reducing “shielding” where needed and float fill where timing is critical; reducing the pessimism in noise/timing simulations (e.g., providing denser and more complicated circuits without overcompensating for negative coupling effects in the timing and/or noise analysis, which may be especially pertinent in low metal layers of dense circuits where fill is required and noise issues could be large); improved timing; reduced coupling noise.

FIG. 9depicts an example high-level Electronic Design Automation (EDA) tool flow, which is responsible for creating an optimized microprocessor (or other IC) design to be manufactured. A designer could start with a high-level logic description901of the circuit (e.g. VHDL or Verilog). The logic synthesis tool903compiles the logic, and optimizes it without any sense of its physical representation, and with estimated timing information. The placement tool905takes the logical description and places each component, looking to minimize congestion in each area of the design. The clock synthesis tool907optimizes the clock tree network by cloning/balancing/buffering the latches or registers. The timing closure step909performs a number of optimizations on the design, including buffering, wire tuning, and circuit repowering; its goal is to produce a design which is routable, without timing violations, and without excess power consumption. The routing stage911takes the placed/optimized design, and determines how to create wires to connect all of the components, without causing manufacturing violations. Post-route timing closure913performs another set of optimizations to resolve any violations that are remaining after the routing. Design finishing915then adds extra metal shapes to the netlist, to conform with manufacturing requirements. The checking steps917analyze whether the design is violating any requirements such as manufacturing, timing, power, electromigration (e.g., using techniques disclosed herein) or noise. When the design is clean, the final step919is to generate a layout for the design, representing all the shapes to be fabricated in the design to be fabricated921.

One or more embodiments of the invention, or elements thereof, can be implemented in the form of an apparatus including a memory and at least one processor that is coupled to the memory and operative to perform exemplary method steps.FIG. 6depicts a computer system that may be useful in implementing one or more aspects and/or elements of the invention; it is referred to herein as a cloud computing node but is also representative of a server, general purpose-computer, etc. which may be provided in a cloud or locally.

Thus, one or more embodiments can make use of software running on a general purpose computer or workstation. With reference toFIG. 6, such an implementation might employ, for example, a processor16, a memory28, and an input/output interface22to a display24and external device(s)14such as a keyboard, a pointing device, or the like. The term “processor” as used herein is intended to include any processing device, such as, for example, one that includes a CPU (central processing unit) and/or other forms of processing circuitry. Further, the term “processor” may refer to more than one individual processor. The term “memory” is intended to include memory associated with a processor or CPU, such as, for example, RAM (random access memory)30, ROM (read only memory), a fixed memory device (for example, hard drive34), a removable memory device (for example, diskette), a flash memory and the like. In addition, the phrase “input/output interface” as used herein, is intended to contemplate an interface to, for example, one or more mechanisms for inputting data to the processing unit (for example, mouse), and one or more mechanisms for providing results associated with the processing unit (for example, printer). The processor16, memory28, and input/output interface22can be interconnected, for example, via bus18as part of a data processing unit12. Suitable interconnections, for example via bus18, can also be provided to a network interface20, such as a network card, which can be provided to interface with a computer network, and to a media interface, such as a diskette or CD-ROM drive, which can be provided to interface with suitable media.

A data processing system suitable for storing and/or executing program code will include at least one processor16coupled directly or indirectly to memory elements28through a system bus18. The memory elements can include local memory employed during actual implementation of the program code, bulk storage, and cache memories32which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during implementation.

Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, and the like) can be coupled to the system either directly or through intervening I/O controllers.

It should be noted that any of the methods described herein can include an additional step of providing a system comprising distinct software modules embodied on a computer readable storage medium; the modules can include, for example, any or all of the appropriate elements depicted in the block diagrams and/or described herein; by way of example and not limitation, any one, some or all of the modules/blocks and or sub-modules/sub-blocks described. The method steps can then be carried out using the distinct software modules and/or sub-modules of the system, as described above, executing on one or more hardware processors such as16. Further, a computer program product can include a computer-readable storage medium with code adapted to be implemented to carry out one or more method steps described herein, including the provision of the system with the distinct software modules.

One example of user interface that could be employed in some cases is hypertext markup language (HTML) code served out by a server or the like, to a browser of a computing device of a user. The HTML is parsed by the browser on the user's computing device to create a graphical user interface (GUI).

Exemplary System and Article of Manufacture Details

Exemplary Design Process Used in Semiconductor Design, Manufacture, and/or Test

FIG. 7illustrates multiple such design structures including an input design structure720that is preferably processed by a design process710. Design structure720may be a logical simulation design structure generated and processed by design process710to produce a logically equivalent functional representation of a hardware device. Design structure720may also or alternatively comprise data and/or program instructions that when processed by design process710, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure720may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a gate array or storage medium or the like, design structure720may be accessed and processed by one or more hardware and/or software modules within design process710to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system. As such, design structure720may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

Design process710preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of components, circuits, devices, or logic structures to generate a Netlist780which may contain design structures such as design structure720. Netlist780may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist780may be synthesized using an iterative process in which netlist780is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist780may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a nonvolatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or other suitable memory.