Liquid crystal display panel and array substrate thereof

The present invention provides a liquid crystal display panel and array substrate thereof. The array substrate includes at least a plurality of first scan lines, second scan lines, data lines and a plurality of pixel units arranged in a matrix form; pixel electrodes of pixel unit being divided into at least first sub electrode, second sub electrode and third sub electrode, and controlling first sub electrode and second sub electrode to have a default voltage difference when displaying voltage signal of a same image in 3D display mode. As such, the present invention can reduce signal crosstalk problem in 3D display mode, improve color difference in large view angle condition and reduce color distortion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of liquid crystal displaying techniques, and in particular to a liquid crystal display panel and array substrate thereof.

2. The Related Arts

As the displaying technique continues to grow, the three dimensional (3D) displaying technique is also becoming more matured. A variety of 3D image equipments, such as, 3D TV, 3D projection, 3D camera, is becoming available in the market. Compared to a two dimensional (2D) displaying technique, the display of 3D displaying technique is more vivid and shows better visual effects. Three dimensional displaying is becoming a mainstream of the future display device.

Film-type patterned retarder (FPR) is one of the 3D liquid crystal imaging techniques. As shown inFIG. 1, FPR 3D display system includes a liquid crystal display panel11, patterned retarder thin film12and patterned retarder eyeglasses13. Liquid crystal display panel11includes pixel16forming left-eye signal, pixel17forming right-eye signal and black matrix (BM)18between pixel16and pixel17. FPR 3D display system mainly uses patterned retarder thin film12attached to liquid crystal panel11to separate 3D image into left-eye image14and right-eye image15. Then, through patterned retarder eyeglasses13, left-eye image14and right-eye image15are sent to left eye and right eye of the user respectively. The left eye and right eye of the user receive the two sets of images and the brain synthesizes the two image sets into a 3D image.

Because FPR 3D displaying technique does not require opening and closing of a lens, FPR 3D display system shows less flickering in the display and achieves better visual experience; especially, when working with vertical alignment (VA) display panel to view 3D images, the result is even better. This is because VA display panel, compared to known display panel, has high contrast and short response time, and can provide better display result. However, VA panel is deficient in screen uniformity so that color drift often occurs. When viewed in large view angle, the color cast is easily detectable. Also, FPR 3D displaying technique also suffers the problem of view angle restriction, i.e., the viewer has a narrower view angle. When the viewer is at the position of larger view angle, the two eyes may suffer signal crosstalk, for example, the signal that should be sent to right eye is seen by the left eye, shown as the dash-line inFIG. 1. This situation leads to serious image crosstalk and results in poor image clarity. Therefore, when realizing FPR 3D displaying technique on VA display panel, the large view angle problem is severe.

In known techniques, the solution to solve the above view angle restriction problem of FPR 3D displaying technique is usually to increase the width of BM18between pixel16forming left-eye signal and pixel17forming right-eye signal in order to reduce possible signal crosstalk between two eyes, as shown inFIG. 1. The computation shows that the width of BM18must increase to ⅓ width of the pixel to be effective in reducing crosstalk. However, this approach will result in opening ratio of the pixel greatly reduced, and the luminance of liquid crystal display panel will also be reduced. In particular, when in 2D display mode, there is no crosstalk problem between two eyes, and yet luminance is still reduced. On the other hand, when 2D display panel is transformed into a panel able to display 2D and 3D images, the transformation can be realized by manufacturing a BM mask. After increasing width of BM18, corresponding BM mask must also be modified and thus manufacture cost of liquid crystal display panel is increased.

Another approach is to use one gate line two data line (1G2D) pixel design. As shown inFIG. 2, a pixel structure using 1G2D pixel design includes a first data line21, a second data line22, a scan line23, a main pixel24and a sub pixel25. First data line21and second data line22supply signal to main pixel24and sub pixel25. Main pixel24and sub pixel25are driven by same scan line25. When liquid crystal display panel switches from 2D display mode to 3D display mode, black screen signal is inputted to main pixel24to display the color black to realize BM effect in main pixel area and to reduce signal crosstalk between two eyes. Main pixel24and sub pixel25of 1G2D pixel design have different liquid crystal rotation angles so that liquid crystal panel has good low color cast effect in 2D display mode. However, when switching to 3D display mode, because main pixel24is black, only liquid crystal rotation of sub pixel25is shown, and the low color cast effect is lost. In addition, VA display panel exists own color cast, the color anomaly observed by the viewer at position with large viewing angle is even more severe.

SUMMARY OF THE INVENTION

The technical issue to be addressed by the present invention is to provide a liquid crystal display panel and array substrate thereof, to allow liquid crystal display panel in 3D display mode to effectively improve color difference under large view angle, reduce color distortion and improve display result.

The present invention provides an array substrate for VA liquid crystal display panel, which comprises: at least a plurality of first scan lines, second scan lines, data lines and a plurality of pixel units arranged in a matrix form; each of the pixel units further comprising: switch element and pixel electrode, and each of the pixel units corresponding to at least a first scan line, a second scan line and a data line; pixel electrode at least comprising a first sub electrode, a second sub electrode and a third sub electrode; number of the switch element of each of pixel units being at least three, that is, a first switch element, a second switch element and a third switch element, respectively; output terminals of the first switch, the second switch and the third switch being electrically connected to the first sub electrode, the second sub electrode and the third sub electrode, respectively; input terminals of the first switch element and the second switch element being electrically connected to the data line or output end of the second switch element; control terminals of the first switch element and the second switch element being electrically connected to first scan line respectively, and control terminal of the third switch element being electrically connected to second scan line; wherein under condition of input terminal of the third switch element being electrically connected to data line, the second scan line inputting scan signal to control the third switch element to conduct when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode, and then stopping inputting scan signal to the second scan line; after stopping inputting scan signal to the second scan line, the first scan line inputting scan signal to control the first switch element and the second switch element to conduct, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode; when entering 2D display mode, the first scan line and the second scan line inputting scan signal respectively to control the first switch element, the second switch element and the third switch element to conduct, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element respectively to the first sub electrode, the second sub electrode and the third sub electrode, and controlling a default voltage difference existing between at least two sub electrodes of the first sub electrode, the second sub electrode and the third sub electrode.

According to a preferred embodiment of the present invention, the array substrate comprises at least a plurality of third scan lines, the data line comprises a first data line, each pixel unit corresponds to at least a third scan line and first data line; the switch elements of each pixel unit further comprise: a fourth switch element and a fifth switch element; the pixel unit further comprises a first coupling capacitor and a second coupling capacitor; output terminals of the fourth switch and the fifth switch are electrically connected to the first coupling capacitor and the second coupling capacitor, respectively; input terminals of the first switch element, the second switch element and the third switch element are electrically connected to the first data line, input terminals of the fourth switch element and the fifth switch element are electrically connected to the second sub electrode and the third sub electrode respectively, control terminals of the fourth switch element and the fifth switch element are electrically connected to the third scan line respectively; wherein a condition of when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode means that the first data line inputs a voltage signal corresponding to BM image through the third switch element to the third sub electrode; condition of the data line inputs voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode means that the first data line inputs voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and stops inputting scan signal to the first scan line; after stopping inputting scan signal to the first scan line, the third scan line inputs scan signal to control the fourth switch element to conduct, the voltage signal of the second sub electrode passes the fourth switch element and is coupled to the first coupling capacitor, capacitance of the first coupling capacitor is adjusted so that a default voltage difference exists between the first sub electrode and the second sub electrode.

The present invention provides an array substrate for liquid crystal display panel, which comprises: at least a plurality of first scan lines, second scan lines, data lines and a plurality of pixel units arranged in a matrix form; each of the pixel units further comprising: switch element and pixel electrode, and each of the pixel units corresponding to at least a first scan line, a second scan line and a data line; pixel electrode at least comprising a first sub electrode, a second sub electrode and a third sub electrode; number of the switch element of each of pixel units being at least three, that is, a first switch element, a second switch element and a third switch element, respectively; output terminals of the first switch, the second switch and the third switch being electrically connected to the first sub electrode, the second sub electrode and the third sub electrode, respectively; input terminals of the first switch element, the second switch element and the third switch element being electrically connected to the data line; control terminals of the first switch element and the second switch element being electrically connected to first scan line respectively, and control terminal of the third switch element being electrically connected to second scan line; wherein the second scan line inputting scan signal to control the third switch element to conduct when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode, and then stopping inputting scan signal to the second scan line; after stopping inputting scan signal to the second scan line, the first scan line inputting scan signal to control the first switch element and the second switch element to conduct, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode.

According to a preferred embodiment of the present invention, when entering 2D display mode, the first scan line and the second scan line input scan signal respectively to control the first switch element, the second switch element and the third switch element to conduct, the data line inputs voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element respectively to the first sub electrode, the second sub electrode and the third sub electrode, and controls a default voltage difference existing between at least two sub electrodes of the first sub electrode, the second sub electrode and the third sub electrode.

According to a preferred embodiment of the present invention, the array substrate comprises at least a plurality of third scan lines, the data line comprises a first data line, each pixel unit corresponds to at least a third scan line and first data line; the switch elements of each pixel unit further comprise: a fourth switch element and a fifth switch element; the pixel unit further comprises a first coupling capacitor and a second coupling capacitor; output terminals of the fourth switch and the fifth switch are electrically connected to the first coupling capacitor and the second coupling capacitor, respectively; input terminals of the first switch element, the second switch element and the third switch element are electrically connected to the first data line, input terminals of the fourth switch element and the fifth switch element are electrically connected to the second sub electrode and the third sub electrode respectively, control terminals of the fourth switch element and the fifth switch element are electrically connected to the third scan line respectively; wherein a condition of when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode means that the first data line inputs a voltage signal corresponding to BM image through the third switch element to the third sub electrode; condition of the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode means that the first data line inputs voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and stops inputting scan signal to the first scan line; after stopping inputting scan signal to the first scan line, the third scan line inputs scan signal to control the fourth switch element to conduct, the voltage signal of the second sub electrode passes the fourth switch element and is coupled to the first coupling capacitor, capacitance of the first coupling capacitor is adjusted so that a default voltage difference exists between the first sub electrode and the second sub electrode.

According to a preferred embodiment of the present invention, the first switch element, the second switch element, the third switch element, the fourth switch element and the fifth switch element are a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a fifth thin film transistor respectively; the first thin film transistor comprises a first gate terminal, a first source terminal and a first drain terminal, the first source terminal is electrically connected to the first data line, the first drain terminal is electrically connected to the first sub electrode, and the first gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the first thin film transistor; the second thin film transistor comprises a second gate terminal, a second source terminal and a second drain terminal, the second source terminal is electrically connected to the first data line, the second drain terminal is electrically connected to the second sub electrode, and the second gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the second thin film transistor; the third thin film transistor comprises a third gate terminal, a third source terminal and a third drain terminal, the third source terminal is electrically connected to the first data line or the second drain terminal of the second thin film transistor, the third drain terminal is electrically connected to the third sub electrode, and the third gate terminal is electrically connected to the second scan line to control the conduction and disconduction (i.e., on and off) of the third thin film transistor; the fourth thin film transistor comprises a fourth gate terminal, a fourth source terminal and a fourth drain terminal, the fourth source terminal is electrically connected to the second sub electrode, the fourth drain terminal is electrically connected to the first coupling capacitor, and the fourth gate terminal is electrically connected to the third scan line to control the conduction and disconduction (i.e., on and off) of the fourth thin film transistor; the fifth thin film transistor comprises a fifth gate terminal, a fifth source terminal and a fifth drain terminal, the fifth source terminal is electrically connected to the third sub electrode, the fifth drain terminal is electrically connected to the second coupling capacitor, and the fifth gate terminal is electrically connected to the third scan line to control the conduction and disconduction (i.e., on and off) of the fifth thin film transistor.

According to a preferred embodiment of the present invention, when entering 2D display mode, under condition of the third source terminal electrically connected to the first data line, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the first data line inputting voltage signal corresponding to a same image to be displayed through the first thin film transistor, the second thin film transistor and the third thin film transistor to the first sub electrode, the second sub electrode and the third sub electrode respectively, and then stopping inputting scan signal to the first scan line and the second scan line; after stopping inputting scan signal to the first scan line and the second scan line, the third scan line inputting scan signal to control the fourth thin film transistor and the fifth thin film transistor to conduct, voltage signal of the second sub electrode passing though the fourth thin film transistor and coupled to the first coupling capacitor, voltage signal of the third sub electrode passing though the fifth thin film transistor and coupled to the second coupling capacitor, adjusting the first coupling capacitor and the second coupling capacitor so that the first sub electrode having a default voltage difference with the second sub electrode and the third electrode respectively, or default voltage difference existing among the first sub electrode, the second sub electrode and the third sub electrode; under condition of the third source terminal and the second drain terminal of the second thin film transistor electrically connected, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the first data line inputting voltage signal corresponding to a same image to be displayed through the first thin film transistor and the second thin film transistor to the first sub electrode and the second sub electrode respectively, voltage signal passing through the second thin film transistor and the third thin film transistor to the third sub electrode, and then stopping inputting scan signal to the first scan line and the second scan line; after stopping inputting scan signal to the first scan line and the second scan line, the third scan line inputting scan signal to control the fourth thin film transistor and the fifth thin film transistor to conduct, voltage signal of the second sub electrode passing though the fourth thin film transistor and coupled to the first coupling capacitor, voltage signal of the third sub electrode passing though the fifth thin film transistor and coupled to the second coupling capacitor, adjusting the first coupling capacitor and the second coupling capacitor so that the first sub electrode having a default voltage difference with the second sub electrode and the third electrode respectively, or default voltage difference existing among the first sub electrode, the second sub electrode and the third sub electrode.

According to a preferred embodiment of the present invention, the array substrate comprises at least a plurality of third scan lines, the data line comprises a first data line, each pixel unit corresponds to at least a third scan line and first data line; the switch elements of each pixel unit further comprise: a fourth switch element; the pixel unit further comprises a first coupling capacitor; output terminal of the fourth switch element is electrically connected to the first coupling capacitor; input terminals of the first switch element, the second switch element and the third switch element are electrically connected to the first data line, input terminal of the fourth switch element is electrically connected to the second sub electrode, control terminal of the fourth switch element is electrically connected to the third scan line; wherein a condition of when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode means that the first data line inputs a voltage signal corresponding to BM image through the third switch element to the third sub electrode; condition of the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode means that the first data line inputs voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and stops inputting scan signal to the first scan line; after stopping inputting scan signal to the first scan line, the third scan line inputs scan signal to control the fourth switch element to conduct, the voltage signal of the second sub electrode passes the fourth switch element and is coupled to the first coupling capacitor, capacitance of the first coupling capacitor is adjusted so that a default voltage difference exists between the first sub electrode and the second sub electrode.

According to a preferred embodiment of the present invention, the first switch element, the second switch element, the third switch element and the fourth switch element are a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor respectively; the first thin film transistor comprises a first gate terminal, a first source terminal and a first drain terminal, the first source terminal is electrically connected to the first data line, the first drain terminal is electrically connected to the first sub electrode, and the first gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the first thin film transistor; the second thin film transistor comprises a second gate terminal, a second source terminal and a second drain terminal, the second source terminal is electrically connected to the first data line, the second drain terminal is electrically connected to the second sub electrode, and the second gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the second thin film transistor; the third thin film transistor comprises a third gate terminal, a third source terminal and a third drain terminal, the third source terminal is electrically connected to the first data line, the second drain terminal of the second thin film transistor or the first drain terminal of the first thin film transistor, the third drain terminal is electrically connected to the third sub electrode, and the third gate terminal is electrically connected to the second scan line to control the conduction and disconduction (i.e., on and off) of the third thin film transistor; the fourth thin film transistor comprises a fourth gate terminal, a fourth source terminal and a fourth drain terminal, the fourth source terminal is electrically connected to the second sub electrode, the fourth drain terminal is electrically connected to the first coupling capacitor, and the fourth gate terminal is electrically connected to the third scan line to control the conduction and disconduction (i.e., on and off) of the fourth thin film transistor.

According to a preferred embodiment of the present invention, when entering 2D display mode, under condition of the third source terminal electrically connected to the first data line, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the first data line inputting voltage signal corresponding to a same image to be displayed through the first thin film transistor, the second thin film transistor and the third thin film transistor to the first sub electrode, the second sub electrode and the third sub electrode respectively, and then stopping inputting scan signal to the first scan line and the second scan line; after stopping inputting scan signal to the first scan line and the second scan line, the third scan line inputting scan signal to control the fourth thin film transistor to conduct, voltage signal of the second sub electrode passing though the fourth thin film transistor and coupled to the first coupling capacitor, adjusting the first coupling capacitor so that the second sub electrode having a default voltage difference with the first sub electrode and the third electrode respectively; under condition of the third source terminal and the second drain terminal of the second thin film transistor electrically connected, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the first data line inputting voltage signal corresponding to a same image to be displayed through the first thin film transistor and the second thin film transistor to the first sub electrode and the second sub electrode respectively, voltage signal passing through the second thin film transistor and the third thin film transistor to the third sub electrode, and then stopping inputting scan signal to the first scan line and the second scan line; after stopping inputting scan signal to the first scan line and the second scan line, the third scan line inputting scan signal to control the fourth thin film transistor to conduct, voltage signal of the second sub electrode passing though the fourth thin film transistor and coupled to the first coupling capacitor, adjusting the first coupling capacitor so that the second sub electrode having a default voltage difference with the first sub electrode and the third electrode respectively; under condition of the third source terminal and the first drain terminal of the first thin film transistor electrically connected, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the first data line inputting voltage signal corresponding to a same image to be displayed through the first thin film transistor and the second thin film transistor to the first sub electrode and the second sub electrode respectively, voltage signal passing through the first thin film transistor and the third thin film transistor to the third sub electrode, and then stopping inputting scan signal to the first scan line and the second scan line; after stopping inputting scan signal to the first scan line and the second scan line, the third scan line inputting scan signal to control the fourth thin film transistor to conduct, voltage signal of the second sub electrode passing though the fourth thin film transistor and coupled to the first coupling capacitor, adjusting the first coupling capacitor so that the second sub electrode having a default voltage difference with the first sub electrode and the third electrode respectively.

According to a preferred embodiment of the present invention, the data lines further comprises second data line and third data line; each pixel unit corresponds to at least a second data line and third data line; input terminal of the first switch element is electrically connected to the second data line, input terminals of the second switch element and the third switch element are electrically connected to the third data line respectively; wherein a condition of when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode means that the third data line inputs a voltage signal corresponding to BM image through the third switch element to the third sub electrode; a condition of the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode means that the second data line and the third data line input voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode to make difference exist between inputted voltage signal from the second data line and the third data line so that a default voltage difference exists between the first sub electrode and the second sub electrode.

According to a preferred embodiment of the present invention, the first switch element, the second switch element and the third switch element are a first thin film transistor, a second thin film transistor and a third thin film transistor respectively; the first thin film transistor comprises a first gate terminal, a first source terminal and a first drain terminal, the first source terminal is electrically connected to the second data line, the first drain terminal is electrically connected to the first sub electrode, and the first gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the first thin film transistor; the second thin film transistor comprises a second gate terminal, a second source terminal and a second drain terminal, the second source terminal is electrically connected to the third data line, the second drain terminal is electrically connected to the second sub electrode, and the second gate terminal is electrically connected to the first scan line to control the conduction and disconduction (i.e., on and off) of the second thin film transistor; the third thin film transistor comprises a third gate terminal, a third source terminal and a third drain terminal, the third source terminal is electrically connected to the third data line, the second drain terminal of the second thin film transistor or the first drain terminal of the first thin film transistor, the third drain terminal is electrically connected to the third sub electrode; and the third gate terminal is electrically connected to the second scan line to control the conduction and disconduction (i.e., on and off) of the third thin film transistor.

According to a preferred embodiment of the present invention, when entering 2D display mode, under condition of the third source terminal electrically connected to the third data line, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the second data line inputting a first voltage signal corresponding to a same image to be displayed through the first thin film transistor to the first sub electrode, the third data line inputting a second voltage signal corresponding to a same image to be displayed through the second thin film transistor and the third thin film transistor to the second sub electrode and the third sub electrode respectively, so that a difference existing between the first voltage signal and the second voltage signal to make a default voltage difference existing between the first sub pixel and the second sub electrode and between the first sub electrode and the third electrode respectively; under condition of the third source terminal and the second drain terminal of the second thin film transistor electrically connected, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the second data line inputting a first voltage signal corresponding to a same image to be displayed through the first thin film transistor to the first sub electrode, the third data line inputting a second voltage signal corresponding to a same image to be displayed through the second thin film transistor to the second sub electrode, the second voltage signal passing through the second thin film transistor and the third thin film transistor to the third sub electrode, so that a difference existing between the first voltage signal and the second voltage signal to make a default voltage difference existing between the first sub pixel and the second sub electrode and between the first sub electrode and the third sub electrode respectively; under condition of the third source terminal and the first drain terminal of the first thin film transistor electrically connected, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element to the first sub electrode, the second sub electrode and the third sub electrode respectively, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode means that the second data line inputting a first voltage signal corresponding to a same image to be displayed through the first thin film transistor to the first sub electrode, the first voltage signal passing through the first thin film transistor and the third thin film transistor to the third sub electrode, the third data line inputting a second voltage signal corresponding to a same image to be displayed through the second thin film transistor to the second sub electrode, so that a difference existing between the first voltage signal and the second voltage signal to make a default voltage difference existing between the first sub pixel and the second sub electrode and between the first sub electrode and the third sub electrode respectively.

The present invention provides a liquid crystal display panel, which comprises: an array substrate, the array substrate further comprises: at least a plurality of first scan lines, second scan lines, data lines and a plurality of pixel units arranged in a matrix form; each of the pixel units further comprising: switch element and pixel electrode, and each of the pixel units corresponding to at least a first scan line, a second scan line and a data line; pixel electrode at least comprising a first sub electrode, a second sub electrode and a third sub electrode; number of the switch element of each of pixel units being at least three, that is, a first switch element, a second switch element and a third switch element, respectively; output terminals of the first switch, the second switch and the third switch being electrically connected to the first sub electrode, the second sub electrode and the third sub electrode, respectively; input terminals of the first switch element, the second switch element and the third switch element being electrically connected to the data line respectively; control terminals of the first switch element and the second switch element being electrically connected to first scan line respectively, and control terminal of the third switch element being electrically connected to second scan line; wherein the second scan line inputting scan signal to control the third switch element to conduct when entering 3D display mode, the data line inputting a voltage signal corresponding to BM image through the third switch element to the third sub electrode, and then stopping inputting scan signal to the second scan line; after stopping inputting scan signal to the second scan line, the first scan line inputting scan signal to control the first switch element and the second switch element to conduct, the data line inputting voltage signal corresponding to a same image to be displayed through the first switch element and the second switch element respectively to the first sub electrode and the second sub electrode, and controlling a default voltage difference existing between the first sub electrode and the second sub electrode.

According to a preferred embodiment of the present invention, the liquid crystal display panel is a VA liquid crystal display panel; when entering 2D display mode, the first scan line and the second scan line input scan signal respectively to control the first switch element, the second switch element and the third switch element to conduct, and the data line inputs a voltage signal corresponding to a same image to be displayed through the first switch element, the second switch element and the third switch element respectively to the first sub electrode, the second sub electrode and the third sub electrode, and controlling a default voltage difference to exist between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode.

The efficacy of the present invention is that to be distinguished from the state of the art. The present invention divides the pixel electrode of pixel unit into at least a first sub electrode, a second sub electrode and a third sub electrode, realizes the effect of a BM at the third sub electrode and make a default voltage difference existing between the first sub electrode and the second sub electrode when displaying voltage signal of a same image so as to solve the signal crosstalk problem in 3D display mode to achieve objectives of improving the color difference in large view angle situation, reducing color distortion and improving display result.

In addition, by supplying voltage signal of a same image to be displayed to the first sub electrode, the second sub electrode and the third sub electrode, and controlling a default voltage difference existing between at least two sub electrodes selected from the first sub electrode, the second sub electrode and the third sub electrode, the luminance of liquid crystal display panel in 2D display mode and opening ratio of the pixel are improved, the color difference in large view angle situation is improved, color distortion is reduced and display result is improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The structure of an array substrate of liquid crystal display panel of the present invention improves the color difference in large view angle situation in both 2D and 3D display modes, reduces color distortion and improves display result.

The following description refers to drawings and embodiments of the present invention.

Referring toFIG. 3andFIG. 4. An embodiment of array substrate10of liquid crystal display panel of the present invention comprises at least a plurality of first scan lines101, second scan line102, data lines103and a plurality of pixel units104arranged in a matrix form. In the instant embodiment, each of the pixel units104further comprises: switch element1041and pixel electrode1042, and each of the pixel units104corresponds to at least a first scan line101, a second scan line102and a data line103.

Pixel electrode1042at least comprises a first sub electrode10421, a second sub electrode10422and a third sub electrode10423. Number of switch element1041of each of pixel units104is at least three, that is, a first switch element10411, a second switch element10412and a third switch element10413, respectively.

Each of first switch element10411, second switch element10412and third switch element10413comprises an input terminal, and output terminal and a control terminal. Output terminals of first switch10411, second switch10412and third switch10413are electrically connected to first sub electrode10421, second sub electrode10422and third sub electrode10423, respectively. Input terminals of first switch10411, second switch10412and third switch10413are electrically connected to data line103. Control terminals of first switch10411and second switch10412are electrically connected to first scan line101respectively, and control terminal of third switch element10413is electrically connected to second scan line102.

First switch10411and second switch10412are to control display and disconduction of first sub electrode10421and second sub electrode10422, with control terminals connected to first scan line101. When a scan signal is inputted to first scan line101, first switch element10411and second10412are conductive simultaneously and data line103inputs voltage signal through first switch element10411and second switch element10412to first sub electrode10421and second sub electrode10422so that first sub electrode10421and second sub electrode10422simultaneously display. Third switch10413is to control display and disconduction of third sub electrode10423, with control terminals connected to second scan line102. When a scan signal is inputted to second scan line102, third switch element10413is conductive and data line103inputs voltage signal through third switch element10413to third sub electrode10423so that third sub electrode10423displays.

Array substrate10of the instant embodiment realizes the switching between 2D and 3D displays of the liquid crystal display panel.

When entering 3D display mode, a scan signal is inputted to second scan line102to control third switch element10413to conduct, data line103inputs a voltage signal corresponding to BM image through third switch element10413to third sub electrode10423, and then stops inputting scan signal to second scan line102. In this embodiment, the inputting of black image voltage signal to third sub electrode10423can perform “clearing screen” to third sub electrode10423so that third sub electrode10423displays a black image and then second scan line102is shut down, no longer supplies scan signal to third sub electrode10423to make third sub electrode10423maintain the black image, as shown inFIG. 5. After stopping inputting scan signal to second scan line102, first scan line101inputs scan signal to control first switch element10411and second switch element10412to conduct, data line103inputs a voltage signal corresponding to a same image to be displayed through first switch element10411and second switch element10412respectively to first sub electrode10421and second sub electrode10422, and controls a default voltage difference to exist between first sub electrode10421and second sub electrode10422.

When entering 3D display mode, the liquid crystal display panel can perform “clearing screen” on pixel units104. Specifically, input signals are inputted to first scan line101and second scan line102simultaneously to make first switch element10411, second switch element10412and third switch element10413conductive. Data line103inputs a voltage signal corresponding to BM image through first switch element10411, second switch element10412and third switch element10413to first sub electrode10421, second sub electrode10422and third sub electrode10423to perform “clearing screen” to the entire pixel unit104so that pixel unit104displays a black image. Then, second scan line102is shut down, no longer supplies scan signal to third sub electrode10423to make third sub electrode10423maintain the black image, while continuing to supply scan signal to first scan line101so that first scan line101can input scan signal to control first switch element10411and second switch element10412to conduct, data line103inputs a voltage signal corresponding to a same image to be displayed through first switch element10411and second switch element10412respectively to first sub electrode10421and second sub electrode10422, and controls a default voltage difference to exist between first sub electrode10421and second sub electrode10422. Specific value of the default voltage difference depends on requirements. The requirements are to guarantee display quality, improve the color difference in large view angle situation, reduce color distortion and improve display result. The present invention does not provide any limitation on the specific value.

As such, when liquid crystal display panel enters 3D display mode, third sub electrode10423maintains a black image, equivalent to BM, so as to reduce possibility of signal crosstalk between two eyes in 3D display mode. In addition, the controlling of default voltage difference to exist between first sub electrode10421and second sub electrode10422can further control polarization of liquid crystal molecules so as to improve the color difference in large view angle situation, reduce color distortion and improve 3D display result.

It should be noted that, referring toFIG. 6, the input terminal of third switch element20413can be electrically connected to the output terminal of second switch element20412. Data line203inputs voltage signal through second switch element20412to second sub electrode20422. The voltage signal passes through second switch element20412and third switch element20413to third sub electrode20423.

Besides the variation of electrically connecting the input terminal of third switch element20413to the output terminal of second switch element20412,FIG. 6is similar toFIG. 4in corresponding structure and elements, and the description will not be repeated here.

Refer toFIG. 4. When liquid crystal display panel enters 2D display mode, first scan line101and second scan line102input scan signal respectively to control first switch element10411, second switch element10412and third switch element10413to conduct, and data line103inputs a voltage signal corresponding to a same image to be displayed through first switch element10411, second switch element10412and third switch element10413respectively to first sub electrode10421, second sub electrode10422and third sub electrode20423, and controlling a default voltage difference to exist between at least two sub electrodes of t first sub electrode10421, second sub electrode10422and third sub electrode20423.

When liquid crystal display panel enters 2D display mode, first scan line101and second scan line102are both conductive, and all three sub electrodes10421,10422,10423input a voltage signal corresponding to a same image to be displayed. As such, pixel unit104can have a bigger opening ratio to increase luminance of liquid crystal display panel. In addition, the controlling of default voltage difference to exist between two sub electrodes of three sub electrodes10421,10422,10423can further control polarization of liquid crystal molecules so as to improve the color difference in large view angle situation, reduce color distortion.

The present invention further provides a plurality of pixel unit designs for controlling a default voltage difference to exist between at least two sub electrodes of three sub electrodes.

Refer toFIG. 7andFIG. 3. Array substrate10comprises at least a plurality of third scan lines305, and data line103comprises a first data line3031. Each pixel unit104corresponds to at least a third scan line305and first data line3031. Switch elements3041of each pixel unit104further comprise a fourth switch element30414and a fifth switch element30415. Pixel unit104further comprises a first coupling capacitor3043and a second coupling capacitor3044.

Output terminals of fourth switch30414and fifth switch30415are electrically connected to first coupling capacitor3043and second coupling capacitor3044, respectively. Input terminals of first switch element30411, second switch element30412and third switch element30413are electrically connected to first data line3031. Input terminals of fourth switch element30414and fifth switch element30415are electrically connected to second sub electrode30422and third sub electrode30423respectively. Control terminals of fourth switch element30414and fifth switch element30415are electrically connected to third scan line305respectively.

When the liquid crystal display panel enters 3D display mode, second scan line302inputs scan signal to make third switch element30413conductive, first data line3031inputs a voltage signal corresponding to BM image through third switch element30413to third sub electrode30423. Then, second scan line302stops inputting scan signal to keep third sub electrode30423to maintain black image. First scan line301inputs a control signal to make first switch element30411and second switch element30412conductive, first data line3031inputs voltage signal corresponding to a same image to be displayed through first switch element30411and second switch element30412respectively to first sub electrode30421and second sub electrode30422to make liquid crystal display panel display image. At this point, first sub electrode30421and second sub electrode30422have a same voltage. Then, first scan line301stop inputting scan signal. After stopping inputting scan signal to first scan line301, third scan line305inputs scan signal to make fourth switch element30414conductive. After fourth switch element30414becomes conductive, voltage signal on second sub electrode30422passes fourth switch element304141and is coupled to first coupling capacitor3043so that voltage on second sub electrode30422changes while voltage on first sub electrode30421does not change. Depending on actual requirement of color polarization of view angle, capacitance of first coupling capacitor3043is adjusted so that a default voltage difference exists between first sub electrode30421and second sub electrode30422.

In the present embodiment, switch element3041is a three-terminal control switch. As shown inFIG. 8, take thin film transistor as example. First switch element30411, second switch element30412, third switch element30413, fourth switch element30414and fifth switch element30415are first thin film transistor30411′, second thin film transistor30412′, third thin film transistor30413′, fourth thin film transistor30414′ and fifth thin film transistor30415′, respectively.

In the instant embodiment, first thin film transistor30411′ comprises a first gate terminal30411′3, a first source terminal30411′1and a first drain terminal30411′2. First gate terminal30411′3, first source terminal30411′1and first drain terminal30411′2are used as control terminal, input terminal and output terminal of first thin film transistor30411′ respectively. First source terminal30411′1is electrically connected to first data line3031. First drain terminal30411′2is electrically connected to first sub electrode30421. First gate terminal30411′3is electrically connected to first scan line301to control conduction and disconduction of first thin film transistor30411′.

Second thin film transistor30412′ comprises a second gate terminal30412′3, a second source terminal30412′1and a second drain terminal30412′2. Second gate terminal30412′3, second source terminal30412′1and second drain terminal30412′2are used as control terminal, input terminal and output terminal of second thin film transistor30412′ respectively. Second source terminal30412′1is electrically connected to first data line3031. Second drain terminal30412′2is electrically connected to second sub electrode30422. Second gate terminal30411′3is electrically connected to first scan line301to control conduction and disconduction of second thin film transistor30412′.

Third thin film transistor30413′ comprises a third gate terminal30413′3, a third source terminal30413′1and a third drain terminal30412′2. Third gate terminal30413′3, third source terminal30413′1and third drain terminal30413′2are used as control terminal, input terminal and output terminal of third thin film transistor30413′ respectively. Third source terminal30413′1is electrically connected to first data line3031. Third drain terminal30413′2is electrically connected to third sub electrode30423. Third gate terminal30413′3is electrically connected to second scan line302to control conduction and disconduction of third thin film30413′.

Fourth thin film transistor30414′ comprises a fourth gate terminal30414′3, a fourth source terminal30414′1and a fourth drain terminal30414′2. Fourth gate terminal30414′3, fourth source terminal30414′1and fourth drain terminal30414′2are used as control terminal, input terminal and output terminal of fourth thin film transistor30414′ respectively. Fourth source terminal30414′1is electrically connected to second sub electrode30422. Fourth drain terminal30414′2is electrically connected to first coupling capacitor3043. Fourth gate terminal30414′3is electrically connected to third scan line305to control conduction and disconduction of fourth thin film30414′.

Fifth thin film transistor30415′ comprises a fifth gate terminal30415′3, a fifth source terminal30415′1and a fifth drain terminal30415′2. Fifth gate terminal30415′3, fifth source terminal30415′1and fifth drain terminal30415′2are used as control terminal, input terminal and output terminal of fifth thin film transistor30415′ respectively. Fifth source terminal30415′1is electrically connected to third sub electrode30423. Fifth drain terminal30415′2is electrically connected to second coupling capacitor3044. Fifth gate terminal30415′3is electrically connected to third scan line305to control conduction and disconduction of fifth thin film30415′.

When the liquid crystal display panel enters 2D display mode, first scan line301and second scan line302respectively input scan signal to make first thin film transistor30411′, second thin film transistor30412′ and third thin film transistor30413′ conductive. First data line3031inputs a voltage signal required to display a same image through first thin film transistor30411′, second thin film transistor30412′ and third thin film transistor30413′ to first sub electrode30421, second sub electrode30422and third sub electrode30423to make the liquid crystal display panel to display the image. At this point, first sub electrode30421, second sub electrode30422and third sub electrode30423have a same voltage level. Then, first scan line301and second scan line302stop inputting scan signal. After first scan line301and second scan line302stop inputting scan signal, third scan line305inputs scan signal to make fourth thin film transistor30414′ and fifth thin film transistor30415′ conductive. Because of existence of first coupling capacitor3043and second coupling capacitor3044, after fourth thin film transistor30414′ and fifth thin film transistor30415′ become conductive, voltage signal on second sub electrode30422passes fourth thin film transistor30414′ to be coupled to first coupling capacitor3043, and voltage signal on third sub electrode30423passes fifth thin film transistor30415′ to be coupled to second coupling capacitor3044. As such, voltage levels on second sub electrode30422and third sub electrode30423are changed. Depending on actual requirement of color polarization of view angle, capacitances of first coupling capacitor3043and second coupling capacitor3044are adjusted so that voltage levels on second sub electrode30422and third sub electrode30423can change accordingly. In other words, capacitances of first coupling capacitor3043and second coupling capacitor3044are adjusted so that a default voltage difference exists between first sub electrode30411and second sub electrode30422, between first sub electrode30411and third sub electrode30423respectively; or, a default voltage difference exists between any two of first sub electrode30411, second sub electrode30422and third sub electrode30423respectively.

As such, through respective electrical connection of second sub electrode30422and third sub electrode30423to additional first coupling capacitor3043and second coupling capacitor3044, and changing capacitances of first coupling capacitor3043and second coupling capacitor3044, a default voltage difference exists between first sub electrode30411and second sub electrode30422, between first sub electrode30411and third sub electrode30423respectively; alternatively, a default voltage difference exists between any two of first sub electrode30421, second sub electrode30422and third sub electrode30423respectively so as to control polarization of liquid crystal molecules to improve the color difference in large view angle situation in 2D display mode, reduce color distortion and improve display result. Also, in 3D display mode, a default voltage difference exists between first sub electrode30421, second sub electrode30422, and third sub electrode30423is controlled by second scan line302alone to realize BM effect to solve the signal crosstalk problem to improve the color difference in large view angle situation and reduce color distortion.

Furthermore, refer toFIG. 9. Input terminal of third switch element40413can also be electrically connected to output terminal of second switch element40412. First data line4031inputs voltage signal through second switch element40412to second sub electrode40422. The voltage signal passes second switch element40412and then third switch element40413to third sub electrode40423.

Similarly, inFIG. 9, except the variation of connection of input terminal of third switch element40413to output terminal of second switch element40412, the remaining structure and elements are similar to those inFIG. 7, and the description will not be repeated here.

Referring toFIG. 10,FIG. 10shows an equivalent circuit diagram of switch element4041ofFIG. 9as a thin film transistor. Third source terminal40413′1of third thin film transistor4013′ is electrically connected to second drain terminal40412′2of second thin film transistor40412′. At this point, when the liquid crystal display panel enters 2D display mode, first data line4031inputs voltage signal required to display a same image through first thin film transistor40411′ and second thin film transistor40412′ to first sub electrode40421and second sub electrode40422respectively. The voltage signal passes second thin film transistor40412′ and third thin film transistor40413′ to third sub electrode40423. Then, first scan line401and second scan line402stop inputting scan signal. Third scan line405inputs scan signal to control fourth thin film transistor40414′ and fifth thin film transistor40415′ to conduct. The voltage signal of second sub electrode40422passes though fourth thin film transistor40414′ and is coupled to first coupling capacitor4043. The voltage signal of third sub electrode40423passes though fifth thin film transistor40415′ and is coupled to second coupling capacitor4044. As such, voltage levels on second sub electrode40422and third sub electrode40423are changed. Depending on actual requirements of color polarization of large view angle, capacitances of first coupling capacitor4043and second coupling capacitor4044are adjusted to change voltage levels of second sub electrode40422and third sub electrode40423so that a default voltage difference exists between first sub electrode40421and second sub electrode40422, between first sub electrode40421and third sub electrode40423respectively; or, a default voltage difference exists between any two of first sub electrode40421, second sub electrode40422and third sub electrode40423respectively.

Refer toFIG. 11andFIG. 3.FIG. 11is a schematic view showing the structure of yet another embodiment of a default voltage difference existing between at least two sub electrodes of the three sub electrodes of the pixel unit of the present invention. Array substrate10comprises at least a plurality of third scan lines705, and data line103further comprises a first data line7031. Each pixel unit104corresponds to at least a third scan line705and first data line7031. Switch elements7041of each pixel unit104further comprise: a fourth switch element70414. Pixel unit104further comprises a first coupling capacitor7043. The structure and the related connection of the pixel unit in this embodiment are similar to the embodiment ofFIG. 7, except the fifth switch element and the second coupling capacitor; thus, the descriptions of the embodiment ofFIG. 11and Figure are omitted here.FIG. 12is an equivalent circuit diagram of the switch element shown inFIG. 11being a thin film transistor.

When the liquid crystal display panel enters 3D display mode, the 3D display drive theory is similar to the previous embodiment, and thus will not be repeated here.

Refer toFIG. 12. When the liquid crystal display panel enters 2D display mode, under condition of third source terminal70413′1electrically connected to first data line7031, first data line7031inputs a voltage signal to first sub electrode70421, second sub electrode70422and third sub electrode70423so that three sub electrodes have the same voltage level. First scan line701and second scan line702are shut down, and third scan line705inputs scan signal to make fourth thin film transistor70414′ conductive. Because of first coupling capacitor7043, the voltage signal of second sub electrode70422passes though fourth thin film transistor70414′ and is coupled to first coupling capacitor7043. As such, voltage level on second sub electrode70422is changed. Depending on actual requirements of color polarization of large view angle, capacitances of first coupling capacitor7043is adjusted to change voltage level of second sub electrode70422so that a default voltage difference exists between second sub electrode70422and first sub electrode70421, between second sub electrode70422and third sub electrode70423respectively. First sub electrode70421and third sub electrode70423maintain the same voltage.

As such, through electrical connection of second sub electrode70422to additional first coupling capacitor7043, and changing capacitance of first coupling capacitor7043, a default voltage difference exists between second sub electrode70422and first sub electrode70421, between second sub electrode70422and third sub electrode70423respectively, so as to control polarization of liquid crystal molecules to improve the color difference in large view angle situation in 2D display mode, reduce color distortion and improve display result. Also, in 3D display mode, a default voltage difference exists between first sub electrode70421, second sub electrode70422, and third sub electrode70423is controlled by second scan line302alone to realize BM effect to solve the signal crosstalk problem to improve the color difference in large view angle situation and reduce color distortion.

Furthermore, refer toFIG. 13. Input terminal of third switch element80413can also be electrically connected to output terminal of second switch element80412. First data line8031inputs voltage signal through second switch element80412to second sub electrode80422. The voltage signal passes second switch element80412and then third switch element80413to third sub electrode80423.

InFIG. 13, except the variation of connection of input terminal of third switch element80413to output terminal of second switch element80412, the remaining structure and elements are similar to those inFIG. 11, and the description will not be repeated here.

Referring toFIG. 14,FIG. 14shows an equivalent circuit diagram of switch element ofFIG. 13as a thin film transistor. Third source terminal80413′1of third thin film transistor8013′ is electrically connected to second drain terminal80412′2of second thin film transistor80412′. At this point, when the liquid crystal display panel enters 2D display mode, first data line8031inputs voltage signal required to display a same image through first thin film transistor80411′ and second thin film transistor80412′ to first sub electrode80421and second sub electrode80422respectively. The voltage signal passes second thin film transistor80412′ and third thin film transistor80413′ to third sub electrode80423. Then, first scan line801and second scan line802stop inputting scan signal. Third scan line805inputs scan signal to control fourth thin film transistor80414′ to conduct. The voltage signal of second sub electrode80422passes though fourth thin film transistor80414′ and is coupled to first coupling capacitor8043. As such, voltage level on second sub electrode80422is changed. Depending on actual requirements of color polarization of large view angle, capacitance of first coupling capacitor4043is adjusted so that a default voltage difference exists between second sub electrode80422and first sub electrode80421, between second sub electrode80422and third sub electrode80423respectively.

It should be noted that third source terminal80413′1of third thin film transistor80413′ in the instant embodiment can also be electrically connected to first drain terminal80411′2of first thin film transistor80411′. At this point, when the liquid crystal display panel enters 2D display mode, a same voltage signal inputted to first sub electrode, second sub electrode and third sub electrode. The adjusted capacitance of first coupling capacitor8043make a default voltage difference exist between second sub electrode80422and first sub electrode80421, between second sub electrode80422and third sub electrode80423respectively. The remaining of the connection and drive theory are similar to the previous embodiment, and thus the descriptions are omitted here.

Refer toFIG. 15andFIG. 3.FIG. 15is a schematic view showing the structure of yet another embodiment of a default voltage difference existing between at least two sub electrodes of the three sub electrodes of the pixel unit of the present invention. Data line103of array substrate10further comprises a second data line5032and a third data line5033. Each pixel unit104corresponds to at least a second data line5032and a third data line5033.

In the instant embodiment, input terminal of first switch element50411is electrically connected to second data line5032. Input terminals of second switch element50412and third switch element50413are electrically connected to third data line5033. When the liquid crystal display panel enters 3D display mode, second scan line502inputs a scan signal to third switch element50413to make third switch element50413conductive. Third data line5033inputs a voltage signal corresponding to BM image through third switch element50413to third sub electrode50423to perform “clearing screen” on third sub electrode50423to make third sub electrode50423display a black image. Then, second scan line502stop inputting scan signal to keep third sub electrode50423to maintain black image. Then, first scan line501inputs scan signal to make first switch element50411and second switch element50412conductive. Second data line5032and third data line5033input voltage signal corresponding to a same image to be displayed through first switch element50411and second switch element50412respectively to first sub electrode50421and second sub electrode50422to make difference exist between inputted voltage signal from second data line5032and third data line5033so that a default voltage difference exists between first sub electrode50421and second sub electrode50422.

Refer ring toFIG. 16, switch element5042is three-terminal control switch. Take thin film transistor as example. First switch element50411, second switch element50412and third switch element50413are first thin film transistor50411′, second thin film transistor50412′ and third thin film transistor50413′, respectively.

In the instant embodiment, first thin film transistor50411′ comprises a first gate terminal50411′3, a first source terminal50411′1and a first drain terminal50411′2. First gate terminal50411′3, first source terminal50411′1and first drain terminal50411′2are used as control terminal, input terminal and output terminal of first thin film transistor50411′ respectively. First source terminal50411′1is electrically connected to second data line5032. First drain terminal50411′2is electrically connected to first sub electrode50421. First gate terminal50411′3is electrically connected to first scan line501to control conduction and disconduction of first thin film transistor50411′.

Second thin film transistor50412′ comprises a second gate terminal50412′3, a second source terminal50412′1and a second drain terminal50412′2. Second gate terminal50412′3, second source terminal50412′1and second drain terminal50412′2are used as control terminal, input terminal and output terminal of second thin film transistor50412′ respectively. Second source terminal50412′1is electrically connected to third data line5033. Second drain terminal50412′2is electrically connected to second sub electrode50422. Second gate terminal50411′3is electrically connected to first scan line501to control conduction and disconduction of second thin film transistor30412′.

Third thin film transistor50413′ comprises a third gate terminal50413′3, a third source terminal50413′1and a third drain terminal50412′2. Third gate terminal50413′3, third source terminal50413′1and third drain terminal50413′2are used as control terminal, input terminal and output terminal of third thin film transistor50413′ respectively. Third source terminal50413′1is electrically connected to third data line5033. Third drain terminal50413′2is electrically connected to third sub electrode50423. Third gate terminal50413′3is electrically connected to second scan line502to control conduction and disconduction of third thin film50413′.

When the liquid crystal display panel enters 2D display mode, first scan line501and second scan line502respectively input scan signal to make first thin film transistor50411′, second thin film transistor50412′ and third thin film transistor50413′ conductive. Second data line5032inputs a first voltage signal required to display a same image through first thin film transistor50411′, to first sub electrode50421. Third data line5033inputs a second voltage signal required to display the image through second thin film transistor50411′ and third thin film transistor50412′ respectively to second sub electrode50422and third sub electrode50423. Depending on actual requirement of color polarization of view angle, a default voltage difference exists between first sub electrode50411and second sub electrode50422, between first sub electrode50411and third sub electrode50423respectively, while second sub electrode50422and third sub electrode50423have same voltage level.

As such, through second data line5032inputting voltage signal to first sub electrode50421, third data line5033inputting voltage signal to second sub electrode50422and third sub electrode50423respectively, because a difference exists between the voltage signal inputted by second data line5032and the voltage signal inputted by third data line5033, a default voltage difference exists between first sub electrode50411and second sub electrode50422, between first sub electrode50411and third sub electrode50423respectively so as to control polarization of liquid crystal molecules to improve the color difference in large view angle situation in 2D and 3D display modes, reduce color distortion and improve display result. Also, third sub electrode50423is controlled by second scan line502alone to realize BM effect to solve the signal crosstalk problem. In 2D display mode, third sub electrode50423is opened normally so as to improve luminance of the liquid crystal display panel in 2D display mode and opening ratio of the pixel unit.

Furthermore, refer toFIG. 17. Input terminal of third switch element60413can also be electrically connected to output terminal of second switch element60412. Third data line6033inputs voltage signal through second switch element60412to second sub electrode60422. The voltage signal passes second switch element60412and then third switch element60413to third sub electrode60423.

Specifically,FIG. 18shows an equivalent circuit diagram of switch element6041ofFIG. 17as a thin film transistor. Third source terminal60413′1of third thin film transistor6013′ is electrically connected to second drain terminal60412′2of second thin film transistor60412′. At this point, when the liquid crystal display panel enters 2D display mode, first scan line601and second scan line602input scan signal respectively to make first thin film transistor60411′, second thin film transistor60412′ and third thin film transistor60413′. Second data line6032inputs a first voltage signal required to display a same image through first thin film transistor60411′ to first sub electrode60421. Third data line6033inputs a second voltage signal required to display a same image through second thin film transistor60412′ to second sub electrode60422. The second voltage signal passes second thin film transistor60412′ and then third thin film transistor60413′ to third sub electrode60423. Depending on actual requirements of color polarization of large view angle, a difference exists between the voltage signal inputted by second data line6032and the voltage signal inputted by third data line6033so that a default voltage difference exists between first sub electrode60421and second sub electrode60422, between first sub electrode60421and third sub electrode60423respectively.

It should be noted that third source terminal60413′1of third thin film transistor60413′ in the instant embodiment can also be electrically connected to first drain terminal60411′2of first thin film transistor60411′. At this point, when the liquid crystal display panel enters 2D display mode, second data line6032inputs a first voltage signal required to display a same image to first thin film transistor60411′. The first voltage signal passes first thin film transistor60411′ to third thin film transistor60413′ so that first sub electrode60421and third sub electrode60423have a same voltage level. Third data line6033inputs a second voltage signal required to display a same image to second thin film transistor60412′ a difference exists between the first voltage signal and the second voltage signal, so that a default voltage difference exists between second sub electrode60422and first sub electrode60421, between second sub electrode60422and third sub electrode60423respectively. The remaining of the connection and drive theory are similar to the previous embodiment, and thus the descriptions are omitted here.

The present invention further provides an embodiment of a liquid crystal display panel, comprising an array substrate described in any of aforementioned embodiments.