Semiconductor device using power gating

A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

BACKGROUND

The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device that uses power gating.

Due to the nanoscale nature of semiconductor processing, power consumption sharply increases due to leakage current. In order to reduce the leakage current, a technique referred to as power gating is used to cut off power supplied to a circuit block that is not currently used in a chip. However, the technique has drawbacks in that data stored in a flip-flop or in a memory is damaged due to the power being cut off. Also, inductive noise may occur in the chip since a current instantaneously rapidly flows when power is re-supplied to re-use the circuit block. The inductive noise is known as ground bounce noise which affects adjacent circuit blocks, and which may cause abnormal operation.

SUMMARY

The inventive concept provides a semiconductor device using power gating so that ground bounce noise can be minimized and a voltage can be stably applied to a circuit storing data in a data retention mode.

According to an aspect, there is provided a semiconductor device including a circuit unit and a current blocking unit. The circuit unit may be connected between a first voltage node and a virtual voltage node. The current blocking unit may be connected between the virtual voltage node and a second voltage node, and may block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit may control whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode.

The current blocking unit may include a plurality of transistors serially connected between the virtual voltage node and the second voltage node, each transistor having a gate to which a corresponding random signal from among the plurality of random signals is applied; and at least one capacitor having a first terminal connected to a node between the plurality of transistors which are serially connected and a second terminal to which a ground voltage is applied. In one embodiment, the transistors are NMOS transistors, a power voltage is applied to the first voltage node, and a ground voltage is applied to the second voltage node. In an alternative embodiment, the transistors are PMOS transistors, a ground voltage is applied to the first voltage node, and a power voltage is applied to the second voltage node.

The current blocking unit may include a plurality of transistors having first terminals connected to the virtual voltage node, having second terminals connected to the second voltage node, and having gates to which corresponding random signals from among the plurality of random signals are applied.

The semiconductor device may further include a random signal generating unit generating the plurality of random signals.

In one embodiment, the plurality of random signals comprise first through nthrandom signals (n is a natural number greater than 2), wherein a kthrandom signal (k is a natural number in a range of 2 through n) is a signal generated by shifting the first random signal during a k time period.

The semiconductor device may further include a current pass unit connecting the virtual voltage node and the second voltage node in a data retention mode; and a charge pump allowing a predetermined current to flow between the virtual voltage node and the second voltage node in the data retention mode, wherein the current pass unit is connected in parallel with the current blocking unit and the charge pump.

The current pass unit may be an NMOS transistor connected between the virtual voltage node and the second voltage node, and turned on in the data retention mode. The charge pump may comprise: a PMOS transistor turned on or turned off in the data retention mode; and a current source connected to the PMOS transistor.

The current pass unit may be a PMOS transistor connected between the virtual voltage node and the second voltage node, and turned on in the data retention mode. The charge pump may comprise: a NMOS transistor turned on or turned off in the data retention mode; and a current source connected to the NMOS transistor.

The current blocking unit may block connection between the virtual voltage node and the second voltage node in the data retention mode.

The current blocking unit may maintain connection between the virtual voltage node and the second voltage node when a voltage of the virtual voltage node equals a voltage of the second voltage node.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. Like reference numerals in the drawings denote like elements.

FIG. 1is a block diagram of a semiconductor device100according to an embodiment of the inventive concept.

Referring toFIG. 1, the semiconductor device100according to the present embodiment may include a circuit unit110, a current blocking unit120, and a random signal generating unit130. The circuit unit110is connected between a first voltage node N1and a virtual voltage node VN. In the current embodiment ofFIG. 1, it is assumed that a power voltage VDD is applied to the first voltage node N1. The circuit unit110may be a logic block that performs general circuit operations, or may be a storage block that stores data.

The current blocking unit120is connected between the virtual voltage node VN and a second voltage node N2. In the current embodiment ofFIG. 1, it is assumed that a ground voltage GND is applied to the second voltage node N2. The current blocking unit120may include first and second transistors TR1and TR2, and at least a capacitor C. In the current embodiment ofFIG. 1, the current blocking unit120includes the first and second transistors TR1and TR2, and the capacitor C. However, the inventive concept is not limited thereto, and even if the number of transistors and capacitors included in the current blocking unit120varies, an effect of the current embodiment of the inventive concept remains unchanged. The first transistor TR1may be an N-type metal-oxide-semiconductor (NMOS) transistor. A first terminal of the first transistor TR1is connected to the virtual voltage node VN, a second terminal thereof is connected to a first terminal of the second transistor TR2and a first terminal of the capacitor C, and a first random signal RS1is applied to a gate of the first transistor TR1. The second transistor TR2may be an NMOS transistor. The first terminal of the second transistor TR2is connected to the second terminal of the first transistor TR1and the first terminal of the capacitor C. A second terminal of the second transistor TR2is connected to the second voltage node N2, and a second random signal RS2is applied to a gate of the second transistor TR2. The first terminal of the capacitor C is connected to the second terminal of the first transistor TR1and the first terminal of the second transistor TR2, and the ground voltage GND is applied to a second terminal of the capacitor C.

The current blocking unit120blocks connection between the circuit unit110and the second voltage node N2in a standby mode, thereby blocking a leakage current that may be generated in the circuit unit110. That is, in the standby mode, the first and second transistors TR1and TR2are constantly maintained in a turn-off state. When the standby mode is shifted to an active mode, the current blocking unit120controls whether or not to connect the virtual voltage node VN and the second voltage node N2in response to the first and second random signals RS1and RS2.

In the standby mode, the virtual voltage node VN transits to a floating state, and thus, due to a leakage current, the virtual voltage node VN may have a voltage similar to the power voltage VDD, not the ground voltage GND. Thus, in the case where the first and second transistors TR1and TR2are turned on so as to shift the standby mode to the active mode, a large current flows in the first and second transistors TR1and TR2. In this manner, when the amount of a current is instantaneously sharply changed, ground bounce noise is generated. Ground bounce noise is noise occurring when a large current instantaneously flows to a parasitic inductance component in a bonding wire and a power distribution network. In the current embodiment illustrated inFIG. 1, the ground bounce noise may be minimized by randomly turning on or off the first and second transistors TR1and TR2. In the case where the first transistor TR1is in a turn-on state and the second transistor TR2is in a turn-off state, the capacitor C is charged. In the case where the first transistor TR1is in a turn-off state and the second transistor TR2is in a turn-on state, the electric charges stored in the capacitor C are discharged. In the case where both the first and second transistors TR1and TR2are in a turn-on state, a current flows from the virtual voltage node VN to the second voltage node N2. The aforementioned three cases randomly occur in the current blocking unit120so that the voltage of the virtual voltage node VN slowly transits to the ground voltage GND. That is, by slowly transiting the voltage of the virtual voltage node VN, the ground bounce noise may be minimized. When the voltage of the virtual voltage node VN transits to a voltage similar to the ground voltage GND of the second voltage node N2, the current blocking unit120continuously turns on the first and second transistors TR1and TR2so as to maintain connection between the virtual voltage node VN and the second voltage node N2, so that the semiconductor device100operates in the active mode.

The random signal generating unit130may generate the first and second random signals RS1and RS2whose logic states are randomly transited. That is, the first and second random signals RS1and RS2randomly transit to either a first logic state or a second logic state. Hereinafter, the first logic state is defined as a first logic high and the second logic state is defined as a second logic low. However, even though the first logic state can mean the second logic high and the second logic state means the first logic low, an effect of the current embodiment of the inventive concept remains unchanged. In the current embodiment ofFIG. 1, two random signals, that is, the first and second random signals RS1and RS2are generated. However, if required, the number of random signals to be possibly generated by the random signal generating unit130may vary. Also, the random signals may be completely random with respect to each other, or may have a predetermined rule among the random signals. For example, in the case where the random signal generating unit130generates first through nthrandom signals (n is a natural number greater than 2), a first random signal may be a signal whose logic state is randomly transited, and a second random signal may be a signal generated by shifting the first random signal during a first time period that is a predetermined time period. That is, a kthrandom signal (k is a natural number in a range of 2 through n) may be a signal generated by shifting the first random signal during a k time period that is a predetermined time period.

The semiconductor device100may further include a current pass unit140and a charge pump150so as to stably apply a voltage to the circuit unit110in a data retention mode. The data retention mode is a status in which power is not cut off and a clock signal is not applied. For example, in the data retention mode, when the current blocking unit120blocks connection between the virtual voltage node VN and the second voltage node N2, the virtual voltage node VN should have a predetermined voltage so as to retain data stored in the circuit unit110. Hereinafter, a minimum voltage, which should be applied to the circuit unit110so as to retain the data in the data retention mode, is referred to as a retention voltage.

The current pass unit140controls whether or not to connect the virtual voltage node VN and the second voltage node N2. That is, the current pass unit140may include a third transistor TR3having a first terminal connected to the virtual voltage node VN, and a second terminal connected to the second voltage node N2. A first control signal CON1is applied to the gate of the third transistor TR3. The current pass unit140may be a P-type metal-oxide-semiconductor (PMOS) transistor. In the data retention mode, the first control signal CON1transits to a second logic state, thereby turning on the third transistor TR3.

The charge pump150is connected between the virtual voltage node VN and the second voltage node N2, thereby allowing a predetermined current to flow between the virtual voltage node VN and the second voltage node N2in the data retention mode. The charge pump150may include a current source IS and a fourth transistor TR4. The current source IS is connected between the virtual voltage node VN and the fourth transistor TR4. The fourth transistor TR4may be an NMOS transistor having a first terminal connected to the current source IS, and a second terminal connected to the second voltage node N2. A second control signal CON2is applied to the gate of the fourth transistor TR4. Even if the position of the current source IS may be switched to the position of the fourth transistor TR4, an effect of the current embodiment of the inventive concept remains unchanged. That is, the first terminal of the fourth transistor TR4may be connected to the virtual voltage node VN, the second terminal of the fourth transistor TR4may be connected to a first terminal of the current source IS, and a second terminal of the current source IS may be connected to the second voltage node N2. The second control signal CON2is in a first logic state or in a second logic state in the data retention mode.

The voltage of the virtual voltage node VN varies according to the amount of process variation temperature (PVT) variation. Thus, when the voltage of the virtual voltage node VN increases, the second control signal CON2transits to the first logic state so as to allow a current to flow via the charge pump150. When the voltage of the virtual voltage node VN decreases, the second control signal CON2transits to the second logic state so as to allow the current not to flow via the charge pump150. In this manner, the voltage of the virtual voltage node VN is constantly maintained so that the retention voltage may be stably applied to the circuit unit110. In the data retention mode, the first and second transistors TR1and TR2of the current blocking unit120may be in a turn-off state.

FIG. 2is a block diagram of a semiconductor device200according to another embodiment of the inventive concept.

Referring toFIG. 2, the semiconductor device200according to the present embodiment may include a circuit unit210, a current blocking unit220, and a random signal generating unit230. The circuit unit210is connected between a first voltage node N1and a virtual voltage node VN. In the current embodiment ofFIG. 2, it is assumed that a ground voltage GND is applied to the first voltage node N1. The circuit unit210may operate similarly to the circuit unit110ofFIG. 1.

The current blocking unit220is connected between the virtual voltage node VN and a second voltage node N2. In the current embodiment ofFIG. 2, it is assumed that a power voltage VDD is applied to the second voltage node N2. The current blocking unit220may include first and second transistors TR1and TR2, and at least a capacitor C. Similar to the embodiment illustrated inFIG. 1, the number of transistors and capacitors included in the current blocking unit220may be varied without changing an effect of the current embodiment of the inventive concept. The first transistor TR1may be a PMOS transistor having a first terminal connected to the second voltage node N2, and a second terminal connected to a first terminal of the second transistor TR2and a first terminal of the capacitor C. A first random signal RS1is applied to a gate of the first transistor TR1. The second transistor TR2may be a PMOS transistor having a first terminal connected to the second terminal of the first transistor TR1and the first terminal of the capacitor C, and a second terminal connected to the virtual voltage node VN. A second random signal RS2is applied to a gate of the second transistor TR2. The first random signal RS1and the second random signal RS2are signals whose logic states are randomly transited. The first terminal of the capacitor C is connected to the second terminal of the first transistor TR1and the first terminal of the second transistor TR2, and a ground voltage GND is applied to a second terminal of the capacitor C.

The current blocking unit220operates similarly to the current blocking unit120ofFIG. 1. That is, the current blocking unit220blocks connection between the circuit unit210and the second voltage node N2in the standby mode, and when the standby mode is shifted to the active mode, the current blocking unit220controls whether or not to connect the virtual voltage node VN and the second voltage node N2in response to the first and second random signals RS1and RS2.

In the current embodiment ofFIG. 2, the virtual voltage node VN transits to a floating state in the standby mode, and thus, due to a leakage current, the virtual voltage node VN may have a voltage similar to the ground voltage GND, not the power voltage VDD. Thus, in the case where the first and second transistors TR1and TR2are turned on so as to shift the standby mode to the active mode, a large current flows in the first and second transistors TR1and TR2, thereby generating ground bounce noise. Similar to the embodiment illustrated inFIG. 1, the semiconductor device200ofFIG. 2controls the first and second transistors TR1and TR2to be randomly turned on or off in response to the first and second random signals RS1and RS2, thereby controlling a voltage of the virtual voltage node VN to slowly transit to the power voltage VDD. That is, by slowly transiting the voltage of the virtual voltage node VN, the ground bounce noise may be minimized. When the voltage of the virtual voltage node VN transits to a voltage similar to the power voltage VDD of the second voltage node N2, the current blocking unit220continuously turns on the first and second transistors TR1and TR2so as to maintain connection between the virtual voltage node VN and the second voltage node N2, so that the semiconductor device200operates in the active mode.

The random signal generating unit230operates similarly to the random signal generating unit130ofFIG. 1, and thus, a detailed description thereof will not be repeated here.

The semiconductor device200may further include a current pass unit240and a charge pump250so as to stably apply a voltage to the circuit unit210in the data retention mode.

The current pass unit240controls whether or not to connect the virtual voltage node VN and the second voltage node N2. That is, the current pass unit240may include a third transistor TR3having a first terminal connected to the second voltage node N2, and a second terminal connected to the virtual voltage node VN. A first control signal CON1is applied to a gate of the third transistor TR3. The current pass unit140may be a NMOS transistor. In the data retention mode, the first control signal CON1transits to a first logic state, thereby turning on the third transistor TR3.

The charge pump250is connected between the virtual voltage node VN and the second voltage node N2, thereby allowing a predetermined current to flow between the virtual voltage node VN and the second voltage node N2in the data retention mode. The charge pump250may include a current source IS and a fourth transistor TR4. The current source IS is connected between the second voltage node N2and the fourth transistor TR4. The fourth transistor TR4may be a PMOS transistor having a first terminal connected to the current source IS, and a second terminal connected to the virtual voltage node VN. A second control signal CON2is applied to a gate of the fourth transistor TR4. Similar to the embodiment illustrated inFIG. 1, the position of the current source IS may be switched to the position of the fourth transistor TR4without changing an effect of the current embodiment of the inventive concept.

The second control signal CON2is in a first logic state or at a second logic state in the data retention mode.

The voltage of the virtual voltage node VN varies according to the amount of the PVT variation, as described above. Thus, when the voltage of the virtual voltage node VN decreases, the second control signal CON2transits to the second logic state so as to allow a current to flow via the charge pump250. When the voltage of the virtual voltage node VN increases, the second control signal CON2transits to the first logic state so as to allow the current not to flow via the charge pump250. In this manner, the voltage of the virtual voltage node VN is constantly maintained in the data retention mode so that the retention voltage may be stably applied to the circuit unit210. In the data retention mode, the first and second transistors TR1and TR2of the current blocking unit220may be in a turn-off state.

FIG. 3is a block diagram of a semiconductor device300according to another embodiment of the inventive concept.

Referring toFIG. 3, the semiconductor device300according to the present embodiment may include a circuit unit310, a current blocking unit320, and a random signal generating unit330. The circuit unit310is similar to the circuit unit110ofFIG. 1, and thus, a detailed description thereof will not be repeated here.

The current blocking unit320is connected between a virtual voltage node VN and a second voltage node N2. In the current embodiment ofFIG. 3, it is assumed that a ground voltage GND is applied to the second voltage node N2. The current blocking unit320may include first through eighth transistors TR1through TR8connected in parallel with one another. However, the inventive concept is not limited thereto, and the number of transistors included in the current blocking unit320may vary without changing an effect of the current embodiment of the inventive concept. The first transistor TR1may be an NMOS transistor having a first terminal connected to the virtual voltage node VN, and a second terminal connected to the second voltage node N2. A first random signal RS1is applied to a gate of the first transistor TR1. Similarly, each of the second through eighth transistors TR2through TR8may be an NMOS transistor having a first terminal connected to the virtual voltage node VN, and a second terminal connected to the second voltage node N2. Second through eighth random signals RS2through RS8are applied to the gates of the second through eighth transistors TR2through TR8, respectively.

When the standby mode is shifted to the active mode, the current blocking unit320controls whether or not to connect the virtual voltage node VN and the second voltage node N2in response to the first through eighth random signals RS1through RS8. As described above, when the standby mode is shifted to the active mode, the amount of current variation instantaneously sharply increases, thereby generating ground bounce noise. In the current embodiment ofFIG. 3, the ground bounce noise may be minimized by randomly turning on or off the first through eighth transistors TR1through TR8. That is, since the first through eighth transistors TR1through TR8are randomly turned on or off, a large current does not instantaneously flow so that a voltage of the virtual voltage node VN may slowly transit to the ground voltage GND and the ground bounce noise may be minimized. When the voltage of the virtual voltage node VN transits to a voltage similar to the ground voltage GND of the second voltage node N2, the current blocking unit320continuously turns on the first through eighth transistors TR1through TR8so as to maintain connection between the virtual voltage node VN and the second voltage node N2, so that the semiconductor device300operates in the active mode.

Unlike in the embodiment illustrated inFIG. 1, the random signal generating unit330according to the present embodiment generates eight random signals, that is, the first through eighth random signals RS1through RS8. As described in relation to the embodiment illustrated inFIG. 1, if required, the number of random signals to be possibly generated by the random signal generating unit330may vary. Thus, a detailed description thereof will not be repeated here.

The semiconductor device300may further include a current pass unit340and a charge pump350so as to stably apply a voltage to the circuit unit310in the data retention mode. The current pass unit340and the charge pump350have similar structures and operate similarly to the current pass unit140and the charge pump150ofFIG. 1. Thus, detailed descriptions thereof will not be provided here.

FIG. 4is a block diagram of a semiconductor device400according to another embodiment of the inventive concept.

Referring toFIG. 4, the semiconductor device400according to the present embodiment may include a circuit unit410, a current blocking unit420, and a random signal generating unit430. The circuit unit410is similar to the circuit unit210ofFIG. 2, and thus, a detailed description thereof will not be repeated here.

The current blocking unit420is connected between a virtual voltage node VN and a second voltage node N2. In the current embodiment ofFIG. 4, it is assumed that a power voltage VDD is applied to the second voltage node N2. The current blocking unit420may include first through eighth transistors TR1through TR8which are connected in parallel with one another. Similar to the embodiment illustrated inFIG. 3, the current blocking unit420includes eight transistors, that is, the first through eighth transistors TR1through TR8. However, the inventive concept is not limited thereto, and the number of transistors included in the current blocking unit420may be varied without changing an effect of the current embodiment of the inventive concept. The first transistor TR1may be an NMOS transistor having a first terminal connected to the second voltage node N2, and a second terminal connected to the virtual voltage node VN. A first random signal RS1is applied to a gate of the first transistor TR1. Similarly, each of the second through eighth transistors TR2through TR8may be a PMOS transistor having a first terminal connected to the second voltage node N2, and a second terminal connected to the virtual voltage node VN. Second through eighth random signals RS2through RS8are applied to the gates of the second through eighth transistors TR2through TR8, respectively.

When the standby mode is shifted to the active mode, the current blocking unit420controls whether or not to connect the virtual voltage node VN and the second voltage node N2in response to the first through eighth random signals RS1through RS8. As described above, when the standby mode is shifted to the active mode, the amount of current variation instantaneously sharply increases, thereby generating ground bounce noise. In the current embodiment ofFIG. 4, the ground bounce noise may be minimized by randomly turning on or off the first through eighth transistors TR1through TR8. That is, since the first through eighth transistors TR1through TR8are randomly turned on or off, a large current does not instantaneously flow so that a voltage of the virtual voltage node VN may slowly transit to the power voltage VDD and the ground bounce noise may be minimized. When the voltage of the virtual voltage node VN transits to a voltage similar to the power voltage VDD of the second voltage node N2, the current blocking unit420continuously turns on the first through eighth transistors TR1through TR8so as to maintain connection between the virtual voltage node VN and the second voltage node N2, so that the semiconductor device400operates in the active mode.

The random signal generating unit430may operate similarly to the random signal generating unit330ofFIG. 3, and thus, a detailed description thereof will not be repeated here.

The semiconductor device400may further include a current pass unit440and a charge pump450so as to stably apply a voltage to the circuit unit410in the data retention mode. The current pass unit440and the charge pump450have similar structures and operate similarly to the current pass unit240and the charge pump250ofFIG. 2. Thus, detailed descriptions thereof will not be provided here.

FIG. 5illustrates waveforms of the first through eighth random signals RS1through RS8and voltage variations of the virtual voltage node VN according to the embodiment illustrated inFIG. 4.

Referring toFIGS. 4 and 5, when the first through eighth transistors TR1through TR8are randomly turned on or off by using the first through eighth random signals RS1through RS8as illustrated inFIG. 5, it is apparent that a voltage of the virtual voltage node VN slowly increases from a ground voltage GND to a voltage similar to a power voltage VDD. Thus, the semiconductor device400illustrated inFIG. 4may reduce the ground bounce noise. However, the first through eighth random signals RS1through RS8may be used in the embodiment ofFIG. 3, and two signals from among the first through eighth random signals RS1through RS8may be randomly selected to be used in the embodiment ofFIG. 1or in the embodiment ofFIG. 2. The waveforms of the first through eighth random signals RS1through RS8ofFIG. 5are an example and the inventive concept is not limited thereto.

The semiconductor device using the power gating according to the inventive concept can reduce current causing ground bounce noise, thereby minimizing the ground bounce noise. Also, in the data retention mode, the semiconductor device can stably apply a voltage to a circuit that stores data, so that the semiconductor device can retain the stored data at a low voltage.