Method for forming semiconductor structure having TiN layer

The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for forming a semiconductor structure, and more particularly, to a method for forming a semiconductor structure having a MOS with a TiN layer as the barrier layer.

2. Description of the Prior Art

In modern society, the micro-processor systems comprising integrated circuits (IC) are ubiquitous devices, which are utilized in diverse fields such as automatic control electronics, mobile communication devices and personal computers. With the development of technologies and the increasingly imaginative applications of the electrical products, the IC devices become smaller, more delicate and more diversified.

Metal-oxide-semiconductors (MOS) transistors are usually used in the integrated circuits. Conventionally, a poly-silicon layer is used as the gate material of the MOS. However, with a trend toward scaling down the size of semiconductor devices, conventional poly-silicon gates face problems such as inferior performances due to boron penetration and unavoidable depletion effect, which increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and worsens a driving force of the devices. Therefore, metals with a work function that are suitable for use as the high-k gate dielectric layer, are used to replace the conventional poly-silicon gates to serve as the control electrode.

However, some issues still need to be overcome in the current metal gate MOS fabrication method.

SUMMARY OF THE INVENTION

It is one objective of the present invention to form a semiconductor structure such as a metal gate MOS, wherein the elements in the metal gate MOS are free from whisker defects.

According to one embodiment of the present invention, the method for forming a semiconductor structure primarily comprises providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 to 0.8 angstrom/second. Lastly, a poly-silicon layer is formed directly on the TiN layer.

Since the TiN in the barrier layer is formed at a low rate to obtain a good quality, the problems, such as whisker defects in the TiN layer or the defects on the above layer, like a gate dummy layer or gate cap layer, can be avoided.

DETAILED DESCRIPTION

To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.

Please refer toFIG. 1toFIG. 8, which illustrate schematic diagrams of forming a semiconductor structure according to one embodiment of the present invention. As shown inFIG. 1, a substrate300is provided. The substrate300can be a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. A plurality of shallow trench isolations (STI)401is formed in the substrate300, thereby defining at least an active region402encompassed by the STI401. Then, an interface layer301and a dielectric layer303are sequentially formed on the substrate300through a deposition process, such as a chemical vapor deposition (CVD) or a physical vapor deposition (PVD). The interface layer301can increase the adhesive ability of the above dielectric layer303. Said interface layer301can be omitted in another embodiment, however. The material of the interface layer301may be silicon dioxide or nitridation silicon dioxide. In another embodiment, the interface layer301can be formed on the substrate300through an oxidation process. The dielectric layer303can be a single-layered or a multi-layered structure and the material thereof can be SiO2or a high-k dielectric material, such as a rare earth metal oxide for example. The high-k dielectric material has a dielectric constant substantially greater than 20. In one embodiment, the high-k dielectric material includes hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide, Ta2O3, zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) or barium strontium titanate (BaxSr1-xTiO3, BST), but is not limited thereto.

As shown inFIG. 2, a barrier layer305, such as a TiN layer, is formed on the dielectric layer303through a CVD process or a PVD process for example. In another embodiment, there can be other barrier layers containing TaN or other suitable materials formed between the barrier layer305and the dielectric layer303. In order to improve the quality of the TiN in the barrier layer305, the method for forming the barrier layer305in the present invention is to carry out the process at a relatively low rate. In one embodiment, the barrier layer305is formed at a rate between 0.3 and 0.8 angstrom/second, preferably between 0.4 and 0.6 angstrom/second. In comparison with conventional arts that forms TiN layers at a rate up to 1.5 angstrom/second, the present invention proposes a three times lower rate than that of the conventional arts, so as to obtain a more compact and smooth barrier layer305. In one embodiment, the lower forming rate is achieved by adjusting a DC/RF power. For example, when the barrier layer305of TiN is formed by a PVD process by supplying 0/60 sccm of Ar/N2gas, the PVD process is carried out with a DC/RF power of 500/600 W (compared to 2000/800 W in conventional arts). In another embodiment, when the barrier layer305is formed by a PVD process by supplying 20/40 sccm of Ar/N2gas, the PVD process is carried out with a DC/RF power of 500/600 W (compared to 1000/800 W in conventional arts). It is understood that the lower forming rate of TiN layer305is not limited to above-mentioned process but can be achieved by other means, such as performing the PVD layer at a lower temperature. The principle is that the barrier layer305of TiN should be formed at a rate between 0.3 to 0.8 angstrom/second.

As shown inFIG. 3, a dummy layer307, such as a poly-silicon layer, is formed directly on the barrier layer305. It is noted that in conventional arts, many defects, such as whisker defect or fallen-on particles, tend to occur on the dummy layer307that contains poly-silicon. A TiN layer formed by a PVD process may contain Ti-rich portions randomly distributed on the substrate if the deposition condition is not well-controlled. The poly-silicon grows quickly on the Ti-rich portions than the rest portions of the substrate, which results in whisker defects. The defects are mainly attributed to the roughness of the TiN layer and result from the poor interface between the TiN in the barrier layer305and the poly-silicon in the dummy layer307. Accordingly, since the TiN in the barrier layer305in the present invention is fabricated at a relatively lower rate, a smooth and compact surface can be successfully formed for the poly-silicon to be formed thereon and the whisker defects of the poly-silicon in the dummy layer307in conventional arts can be avoided. In practice, the amount of the defects decreases from 102,143/per wafer to 314/per wafer, providing strong evidence that the method provided in the present invention can improve the quality of the barrier layer305and thus avoid the defects. In one embodiment, the dummy layer307can be formed by a suitable deposition process such as a CVD process, but is not limited thereto. In another embodiment, the dummy layer307can be a multi-layered structure and include other suitable materials such as an amorphous silicon layer or a germanium layer. Preferably, the portion of the poly-silicon in the dummy layer307directly contacts the TiN in the barrier layer305. Then, a cap layer309such as a SiN layer is formed on the dummy layer307.

As shown inFIG. 4, the interface layer301, the dielectric layer303, the barrier layer305, the dummy layer307and the cap layer309are patterned through one or a plurality of photo-etching processes to form a gate stack structure404. The gate stack structure404has a gate interface layer302, a gate dielectric layer304, a gate barrier layer306, a gate dummy layer308and a gate cap layer310.

Subsequently, as shown inFIG. 5, a spacer312is formed on the sidewall of the gate stack structure404. The spacer312can be a mono-layered structure or a multi-layered structure including high temperature oxide (HTO), SiN, SiO or SiN formed from hexachlorodisilane (Si2Cl6) (HCD-SiN). The method for forming the sidewall312is well known in the art and is not described in detail. Then, an implant process is performed to form a source/drain314in the substrate300by using the spacer312and the gate stack structure404as a mask. Then, an annealing process is carried out to activate the source/drain314, thereby completing the transistor400. It is noted that the transistor400can further include other semiconductor structures which are not explicitly shown inFIG. 5, such as a light doped drain (LDD), a silicide layer, a source/drain having an hexagon (also called sigma Σ) or octagon shaped cross-section which is formed through selective epitaxial growth (SEG), or other protective films.

As shown inFIG. 6, after forming the transistor400, a contact etch stop layer (CESL)316and an inter-layer dielectric (ILD) layer318are formed on the substrate300to cover the transistor400. In one embodiment, the CESL316can generate a stress to form a selective strain scheme (SSS). Then, a planarization process, such as a chemical mechanical polish (CMP) process or an etching-back process is performed to remove a part of the ILD layer318, a part of the CESL316, a part of the spacer312, and completely remove the gate cap layer310, until the top surface of the gate dummy layer308is exposed.

As shown inFIG. 7, the gate dummy layer308is removed. The removing method includes a wet etching process, for example, by using a hydroxide solution. Since gate barrier layer306containing TiN has a good etching ratio with respect to the gate dummy layer308which is made of poly-silicon, the gate barrier layer306can act as a good etch stop layer. The etching process toward the gate dummy layer308is therefore stopped on the gate barrier layer306, thereby forming a trench320in the transistor400. In one embodiment, the gate barrier layer306can be further removed by a dry etching process for example.

As shown inFIG. 8, according to the conductive type of the transistor400, appropriate metal is filled into the trench320to form a gate metal326. The metal gate326includes a work function metal layer322and a metal layer324. If the transistor400is an N-type transistor, the work function metal layer322can be TiAl, ZrAl, WAl, TaAl or HfAl, but is not limited thereto. If the transistor400is a P type transistor, the work function metal layer322can be TiN or TiC, but is not limited thereto. The metal layer324can be Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN, but is not limited thereto.

It is one salient feature of the present invention that the gate barrier layer306is a thin layer in order not to greatly influence the work function tuning capability of the metal gate326. For example, the gate barrier layer306is between 10 and 30 angstroms, preferably 20 angstroms, which is relatively thin compared to other layers. Thus, the quality of the gate barrier layer306is important. The present invention therefore proposes forming the gate barrier layer306at a lower rate to generate a compact and smooth gate barrier layer306. It can not only avoid the formation of the defects of the gate dummy layer308and all the above layers, but also provide good conductivity for the metal gate326.

In summary, the present invention provides a method for forming a semiconductor structure having a TiN layer and a poly-silicon layer. The TiN in the barrier layer305is formed at a low rate so as to obtain a good quality. By doing this, the defects in the TiN layer or the defects on the above layer such as a gate dummy layer or a gate cap layer can be avoided. It is noted that the method of forming the semiconductor structure is not only applied to the above-mentioned embodiment that forms the transistor with a metal gate, but also can be applied to other semiconductor structures that have an interface between a TiN layer and a poly-silicon layer. By the method set forth in the present invention, the semiconductor structure can show good performances.