Asymmetric sensing amplifier, memory device and designing method

A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.

BACKGROUND

Processors and memories are various parts of computing systems and electronic devices. The performance of a memory impacts the overall performance of the system or electronic device. Various circuits are developed to improve one or more aspects of memory performance, such as capacity, access speed, power consumption, compact layout etc.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this description will be thorough and complete, and will fully convey the inventive concept to those of ordinary skill in the art. It will be apparent, however, that one or more embodiments may be practiced without these specific details.

In some embodiments, an asymmetric sensing amplifier has an output device coupled to a first bit line in a pair of bit lines. The pair of bit lines further includes a second bit line. The asymmetric sensing amplifier pulls the first bit line toward a predetermined voltage with a first current greater than a second current with which the asymmetric sensing amplifier pulls the second bit line toward the predetermined voltage. As a result, an effect associated with a parasitic capacitance of the output device coupled to the first bit line is compensated for by the greater first current. In one or more embodiments, a ratio of the first and second currents is matched with a ratio of total capacitance loadings of the corresponding first and second bit lines. As a result, logical “0” and logical “1” read speeds are balanced which, in turn, results in an improved overall read speed. Compared to other approaches where a dummy device and/or a dummy metal is coupled to the second bit line for symmetry, the asymmetric sensing amplifier in one or more embodiments does not include such dummy device and dummy metal, and therefore, is more compact in layout area and exhibits an improved read margin due to the reduced total capacitance loading.

FIG. 1is a schematic circuit diagram of a segment of a memory device101in accordance with some embodiments. The memory device101includes one or more memory cells (MC)102, one or more pairs of bit lines BLU/BLBU, BLL/BLBL, and one or more global bit lines GBL. One or more memory cells102are coupled to each pair of bit lines to form one or more memory blocks. Specifically, multiple memory cells102are coupled to the pair of bit lines BLU/BLBU to form an upper half120U of a memory block120, whereas multiple memory cells102are coupled to the pair of bit lines BLL/BLBL to form a lower half120L of the memory block120. One or more memory blocks is coupled to a global bit line. Specifically, the memory block120is coupled to the global bit line GBL. The memory device101further includes a plurality of word lines WL(0)-WL(2k−1) (where k is an integer) coupled to the memory cells102. The memory device101has a lower half130L and an upper half130U. In the lower half130L, the memory cells102are coupled to one half of the word lines, i.e., the word lines WL(0)-WL(k−1). In the upper half130U, the memory cells102are coupled to the other half of the word lines, i.e., the word lines WL(k)-WL(2k−1). InFIG. 1, WT and WC denote a pair of write data lines associated with each memory block120.

Each memory block120further includes bit line pre-charging circuits104U,104L, and input devices (or input stages)106U,106L, in the corresponding upper and lower halves130U,130L, of the memory device101. The memory block120further includes a write pass gate circuit108, an output device110, and a pull-down circuit112all of which are common for both the upper and lower halves130U,130L. The output device110and the input devices106U,106L, define a sensing amplifier which is connected to the bit lines BLU and BLL and configured to detect a state of the bit lines BLU and BLL in a single-ended sensing scheme (i.e., one bit line BLU, rather than both bit lines BLU/BLBU, is used for the sensing operation).

In this example, the output device110is implemented as a NAND gate, although other configurations are also within the scope of various embodiments. The bit line pre-charging circuits104U,104L are similarly configured. In one or more embodiments, each of the bit line pre-charging circuits104U,104L, includes two p-channel metal-oxide semiconductor (PMOS) transistors which are turned ON of OFF by a common pre-charging signal PREGU, PREGL. The input devices106U,106L are similarly configured. Each memory block120in particular and the memory device101in general have a symmetrical structure in some embodiments. In some embodiments, the memory device101does not have a symmetrical structure. For example, in some embodiments, the lower half of the memory device101, including the word lines WL(0)˜WL(k−1), the associated memory cells102, the bit line pre-charging circuit104L and the input device106L, is omitted. For simplicity, the following description is given for the upper half130U of the memory device101. In embodiments where the memory device101also includes the lower half130L, the following description similarly applies to the lower half130L.

For read and/or write operations, the bit line pre-charging circuit104U is configured to pre-charge the corresponding pair of bit lines BLU/BLBU, and the input device106U is configured to pull the pre-charged bit lines toward a predetermined voltage. The predetermined voltage is a ground voltage in a pull-down arrangement in which the bit lines are pulled down toward the ground voltage. In some embodiments, the predetermined voltage is a power supply voltage in a pull-up arrangement in which the bit lines are pulled up toward the power supply voltage. In some embodiments, the predetermined voltage is a voltage between the ground voltage and the power supply voltage, or another voltage level depending on applications and/or other considerations. The write pass gate circuit108is configured to enable or disable writing to the memory cells102in the memory block120.

In some embodiments, when a logical “0” is read from a memory cell102in the memory block120, the first bit line (e.g., BLU) in the corresponding pair of bit lines is pulled down toward the ground voltage, whereas the second bit line (e.g., BLBU) in the corresponding pair of bit lines is pulled up toward (or stays at) the power supply voltage. The pulled-down voltage on the first bit line BLU causes the output device110to output, at a node BLPD, a high voltage to the pull-down circuit112which, in turn, is turned ON to pull the global bit line GBL toward the ground voltage. When a logical “1” is read from a memory cell102in the memory block120, the second bit line BLBU is pulled down toward the ground voltage, whereas the first bit line BLU is pulled up toward (or stays at) the power supply voltage. The pulled-up voltage on the first bit line BLU causes the output device110to output, at the node BLPD, a low voltage to the pull-down circuit112which, in turn, is turned OFF and leaves the global bit line GBL at a global bit line pre-charge voltage. The voltage on the global bit line GBL indicates the datum read out from the memory cell102.

The overall memory read speed depends on several factors including, but not limited to, how fast the input device106U pulls the corresponding bit lines BLU, BLBU toward a predetermined voltage, e.g., the ground voltage or the power supply voltage. The overall memory read speed is also improved when logical “0” and logical “1” read speeds are balanced. In particular, the closer a pulling strength with which the input device106U pulls the first bit line BLU (when reading a logical “0”) is to a pulling strength with which the input device106U pulls the second bit line BLBU (when reading a logical “1”), the faster the overall memory read speed becomes. The coupling of the output device110to the first bit line BLU creates an asymmetry that affects, in some situations, the balancing of the pulling strengths of the input device106U on the first bit line BLU and on the second bit line BLBU.

FIG. 2is a schematic block diagram of an asymmetric sensing amplifier200for a memory device201in accordance with some embodiments. The memory device201comprises a first bit line BLU, a second bit line BLBU, and at least one memory cell MC coupled to the first bit line BLU and the second bit line BLBU. In some embodiments, the memory device201corresponds to the memory device101, the first and second bit lines BLU, BLBU, correspond to one pair of bit lines (e.g., BLU and BLBU), and the at least one memory cell MC corresponds to a memory cell102, as described with respect toFIG. 1.

The sensing amplifier200comprises a first node A configured to be coupled to the first bit line BLU via a first switch S1, and a second node B configured to be coupled to the second bit line BLBU via a second switch S2. The first switch S1and the second switch S2are configured to connect the corresponding first bit line BLU and second bit line BLBU to the sensing amplifier200when a memory cell MC connected to the first bit line BLU and the second bit line BLBU is accessed in a read operation. The first switch S1and the second switch S2are configured to disconnect the corresponding first bit line BLU and second bit line BLBU from the sensing amplifier200when no memory cell MC connected to the first bit line BLU and the second bit line BLBU is accessed in a read operation. In some embodiments, the switches S1and S2are transistors, such as PMOS transistors, although other switch configurations are within the scope of various embodiments. In some embodiments, the switches S1and S2are omitted.

The sensing amplifier200further comprises an input device206and an output device210. The input device206is coupled to the first node A and the second node B. The output device210is coupled to the first node A. The input device206is configured to detect a datum read out from the at least one memory cell MC of the memory device201, and the output device210is configured to output the datum read out from the memory cell MC. In some embodiments, the input device206corresponds to the input device106U or106L, the output device210corresponds to the output device110, and the sensing amplifier200corresponds to the sensing amplifier described with respect toFIG. 1.

The input device206includes a first circuit216and a second circuit226. Each of the first circuit216and the second circuit226is connected to both the first node A and the second node B. The first circuit216is configured to generate a first current I1pulling the first node A toward a predetermined voltage on a node227in response to a first datum read out from the memory cell MC. The second circuit226is configured to generate a second current I2pulling the second node B toward a predetermined voltage on a node228in response to a second datum read out from the memory cell MC. In some embodiments, the predetermined voltages on the nodes227and228are equal. In some embodiments, the predetermined voltages on the nodes227and228are different. In one or more embodiments, the predetermined voltage on the nodes227and228is the ground voltage. Other levels of the predetermined voltages at nodes227,228are within the scope of various embodiments.

More specifically, when the first datum, e.g., a logical “0,” is read out from the memory cell MC, the first bit line BLU is pulled down toward the ground voltage, whereas the second bit line BLBU is pulled up toward (or stays at) a power supply voltage. As a result, the first node A coupled to the first bit line BLU is pulled down toward the ground voltage and disables the second circuit226, whereas the second node B coupled to the second bit line BLBU is pulled up toward (or stays at) the power supply voltage and enables the first circuit216. The enabled first circuit216pulls the first node A towards the ground voltage with the first current I1. The output device210generates an output corresponding to a low voltage of the first node A, which is pulled down, indicating the logical “0” being read out. Similarly, when the second datum, e.g., a logical “1,” is read out from the memory cell MC, the second bit line BLBU is pulled down toward the ground voltage, whereas the first bit line BLU is pulled up toward (or stays at) the power supply voltage. As a result, the first node A coupled to the first bit line BLU is pulled up toward (or stays at) the power supply voltage and enables the second circuit226, whereas the second node B coupled to the second bit line BLBU is pulled down toward the ground voltage and disables the first circuit216. The enabled second circuit226pulls the second node B towards the ground voltage with the second current I2. The output device210generates an output corresponding to a high voltage of the first node A, which is pulled up or stays at the power supply voltage, indicating the logical “1” being read out.

As noted herein, the coupling of the output device210to the first bit line BLU via the first node A creates an asymmetry that affects, in some situations, the balancing of pulling strengths of the input device206on the first bit line BLU (via the first node A) and on the second bit line BLBU (via the second node B). Specifically, pulling strengths of the input device206on the first node A and on the second node B depend on corresponding total capacitance loadings of the first node A and the second node B. In some embodiments, the total capacitance loading of the first node A is a sum of parasitic capacitances of components coupled to the first node A. For example, the total capacitance loading of the first node A is a sum of a parasitic capacitance of the at least one memory cell MC, parasitic capacitances of elements of the first circuit216and second circuit226that are coupled to the first node A, and a parasitic capacitance of the output device210. Similarly, the total capacitance loading of the second node B, in some embodiments, is a sum of parasitic capacitances of components coupled to the second node B, e.g., the parasitic capacitance of the at least one memory cell MC, and parasitic capacitances of elements of the first circuit216and second circuit226that are coupled to the second node B. The output device210is not directly connected to the second node B and, therefore, the total capacitance loading of the second node B does not include the parasitic capacitance of the output device210. As a result, the total capacitance loading of the first node A, in one or more embodiments, is greater than the total capacitance loading of the second node B, which makes it harder for the input device206to pull the first node A than the second node B toward the ground voltage.

In some embodiments, to compensate for the greater total capacitance loading of the first node A compared to the total capacitance loading of the second node B, at least one of the first circuit216or the second circuit226is configured to have the first current I1greater than the second current I2. The input device206is configured to pull the first node A, which has a greater total capacitance loading, with a greater current. As a result, it is possible, in one or more embodiments, to cause the pulling strength with which the input device206pulls the first node A when reading a logical “0” to approach the pulling strength with which the input device206pulls the second node B when reading a logical “1”, thereby improving the overall memory read speed.

In some embodiments, a ratio I1/I2of the first current I1to the second current I2is matched with a ratio CBL,total/CBLB,totalof the total capacitance loading CBL,totalof the first node A to the total capacitance loading CBLB,totalof the second node B. In one or more embodiments, the input device206is designed to have I1/I2equal to CBL,total/CBLB,total. In one or more embodiments, due to one or more variations including, but not limited to, variations in manufacturing process, operation voltage and/or operation temperature (PVT variations), it is possible that the actual ratios I1/I2and CBL,total/CBLB,totalare close, but not necessarily equal to each other. In such situations, the ratio I1/I2is still considered matched with the ratio CBL,total/CBLB,total.

In some embodiments, the sensing amplifier200is free of a dummy output device and/or a dummy conductive pattern coupled to the second node B. Compared to other approaches where a dummy device and/or a dummy metal is coupled to the second bit line BLBU for balancing the total capacitance loading of the second storage node B with the total capacitance loading of the first node A, a layout area of the sensing amplifier200in one or more embodiments is more compact, because such dummy output device and/or dummy conductive pattern are not included. The absence of dummy output device and/or dummy conductive pattern further reduces the total capacitance loading of the second node B, resulting in a faster logical “1” read speed compared to the other approaches. In one or more embodiments, the sensing amplifier200has the first current I1greater than the second current I2to cause the logical “0” read speed to approach the logical “1” read speed, which results in a faster overall memory read speed and a better read margin compared to the other approaches.

FIG. 3is a schematic block diagram of an asymmetric sensing amplifier300for a memory device301in accordance with some embodiments. The memory device301comprises a first bit line BLU, a second bit line BLBU, and a plurality of memory cells MC coupled to the first bit line BLU and the second bit line BLBU. The memory cells MC define a memory array302. In some embodiments, the memory device301corresponds to the memory device101or201as described with respect toFIG. 1or2.

The sensing amplifier300comprises a first node A, a second node B, a power supply voltage node VDD and a reference or ground node VSS. In some embodiments, the first node A and the second node B are coupled to the corresponding first bit line BLU and second bit line BLBU via switches as described with respect toFIG. 2. The sensing amplifier300further comprises a first transistor N1, a second transistor N2, a third transistor P1, a fourth transistor P2, a fifth transistor M1, and an output device NAND1which is a NAND gate. In some embodiments, the first transistor N1, second transistor N2, third transistor P1, fourth transistor P2, and fifth transistor M1together define an input device corresponding to the input device106U,106L or206as described with respect toFIG. 1or2. In some embodiments, the output device NAND1corresponds to the output device110or210as described with respect toFIG. 1or2. The output device NAND1has a first input coupled to the first bit line BLU and the first node A. The output device NAND1has a second input coupled to another bit line BLL. The bit line BLL is at a lower half of the memory device301and corresponds to the first bit line BLU as described with respect toFIG. 1. The bit line BLL is coupled to another input device corresponding to the input device106L described with respect toFIG. 1. A sixth transistor M2is coupled between an output of the output device NAND1and a global bit line GBL. The sixth transistor M2corresponds to the pull-down circuit112described with respect toFIG. 1. In one or more embodiments, the first transistor N1, second transistor N2, fifth transistor M1and sixth transistor M2are n-channel metal-oxide semiconductor (NMOS) transistors, whereas the third transistor P1and fourth transistor P2are PMOS transistors. Other configurations are within the scope of various embodiments.

The first transistor N1and the third transistor P1are coupled in series between the power supply voltage node VDD and the reference node VSS. Specifically, a source of the first transistor N1is coupled to the reference node VSS via the fifth transistor M1, a drain of the first transistor N1is coupled to a drain of the third transistor P1at the first node A, and a source of the third transistor P1is coupled to the power supply voltage node VDD. The second transistor N2and the fourth transistor P2are coupled in series between the power supply voltage node VDD and the reference node VSS. Specifically, a source of the second transistor N2is coupled to the reference node VSS via the fifth transistor M1, a drain of the second transistor N2is coupled to a drain of the fourth transistor P2at the second node B, and a source of the fourth transistor P2is coupled to the power supply voltage node VDD. The first node A is coupled to gates of the second transistor N2and fourth transistor P2, and to the output device NAND1. The second node B is coupled to gates of the first transistor N1and third transistor P1. The fifth transistor M1has a drain coupled to the sources of the first transistor N1and second transistor N2, and a source coupled to the reference node VSS. The fifth transistor M1is controlled to turn ON or OFF by a sensing amplifier enabling signal SAE. The first transistor N1, second transistor N2, third transistor P1and fourth transistor P2define a cross-coupled latch having complementary logic states at the first node A and second node B. Other sensing amplifier configurations are within the scope of various embodiments.

In a read operation, the first bit line BLU and second bit line BLBU are pre-charged, and one memory cell MC in the memory array302is selected or accessed by a corresponding word line as described with respect toFIG. 1. Depending on the datum stored in the accessed memory cell MC, a voltage difference is developed across the first bit line BLU and second bit line BLBU. The voltage difference is applied to the first node A and the second node B, and causes the cross-coupled latch to reach one of two stable states when the sensing amplifier300is enabled by turning ON the fifth transistor M1with the enabling signal SAE.

Specifically, when reading a logical “0,” the voltage at the first node A is pulled down whereas the voltage at the second node B is pull up or stays at the power supply voltage, as described with respect toFIG. 2. As a result, the first transistor N1and fourth transistor P2are turned ON, and the second transistor N2and third transistor P1are turned OFF. A first current Id1flows from the first node A, via the turned ON first transistor N1and the turned ON fifth transistor M1to the reference node VSS. The first node A is pulled down toward the ground voltage by the first current Id1. The first current Id1is defined by a drain current of the first transistor N1and corresponds to the first current I1described with respect toFIG. 2. The stronger the first node A is pulled down by the first current Id1, the faster the cross-coupled latch reaches a first stable state with a logical “0” at the first node A and a logical “1” at the second node B.

When reading a logical “1,” the voltage at the first node A is pulled up or stays at the power supply voltage whereas the voltage at the second node B is pull down, as described with respect toFIG. 2. As a result, the first transistor N1and fourth transistor P2are turned OFF, and the second transistor N2and third transistor P1are turned ON. A second current Id2flows from the second node B, via the turned ON second transistor N2and the turned ON fifth transistor M1to the reference node VSS. The second node B is pulled down toward the ground voltage by the second current Id2. The second current Id2is defined by a drain current of the second transistor N2and corresponds to the second current I2described with respect toFIG. 2. The stronger the second node B is pulled down by the second current Id2, the faster the cross-coupled latch reaches a second stable state with a logical “1” at the first node A and a logical “0” at the second node B.

The speeds at which the cross-coupled latch reaches the first and second stable states are balanced by configuring at least one of the first transistor N1or second transistor N2to approach a ratio Id1/Id2to a ratio CBL,total/CBLB,totalof a total capacitance loading CBL,totalof the first node A to a total capacitance loading CBLB,totalof the second node B. The total capacitance loading CBL,totalof the first node A is a sum of parasitic capacitances of components coupled to the first node A. The total capacitance loading CBLB,totalof the second node B is a sum of parasitic capacitances of components coupled to the second node B. In some embodiments, the total capacitance loadings CBL,totaland CBLB,totalare determined as follows:
CBL,total=Carray,total+C(N1+P1),drain+C(N2+P2),gate+Cnand,gate(1)
CBLB,total=Carray,total+C(N2+P2),drain+C(N1+P1),gate(2)
where Carray,totalis a sum of parasitic capacitances of the memory cells MC in the memory array302, C(N1+P1), drainis a parasitic capacitance of the drains of the first transistor N1and third transistor P1, C(N2+P2),gateis a parasitic capacitance of the gates of the second transistor N2and fourth transistor P2, Cnand,gateis a parasitic capacitance of the output device NAND1, C(N2+P2),drainis a parasitic capacitance of the drains of the second transistor N2and fourth transistor P2, and C(N1+P1),gateis a parasitic capacitance of the gates of the first transistor N1and third transistor P1.

The drain current of the first transistor N1or second transistor N2is determined as follows:
Id=K′n/2*W/L*(VGS−VT)2*(1+λ*VDS)  (3)
where K′n=μnCox, Id is the drain current, μnis the mobility of a charge carrier in the transistor, Cox is the capacitance of a gate oxide of the transistor, W is a channel width of the transistor, L is a channel length of the transistor, VGSis a gate-source voltage of the transistor, VTis the threshold voltage of the transistor, VDSis a drain-source voltage, and λ is a channel-length modulation parameter. By modifying any one or more of the components in Equation (3), the drain current(s) of any one or both of the first transistor N1and second transistor N2is/are configured to approach the ratio Id1/Id2to the ratio CBL,total/CBLB,total.

CBL,totalis greater than CBLB,totalbecause Cnand,gateis included in CBL,totalbut not in CBLB,total. In other words, CBL,total/CBLB,totalis greater than 1. In some embodiments, the ratio Id1/Id2is approached to the ratio CBL,total/CBLB,totalby configuring at least one of the first transistor N1or second transistor N2to have Id1greater than Id2. In some embodiments, the relationship Id1greater than Id2is achieved by configuring the first transistor N1to be larger in size than the second transistor N2.

In some embodiments, by modifying any one or more of the components in Equation (3), the drain current(s) of any one or both of the first transistor N1and second transistor N2is/are configured to match the ratio Id1/Id2to the ratio CBL,total/CBLB,total, i.e., to achieve
Id1/Id2=CBL,total/CBLB,total(4)

In one or more embodiments, the first transistor N1and second transistor N2are configured similarly, except for the channel width to channel length ratio W/L. In such embodiments, the ratio Id1/Id2is matched to the ratio CBL,total/CBLB,totalas follows:
(W/L)N1/(W/L)N2=CBL,total/CBLB,total(5)
where (W/L)N1is the channel width to channel length ratio of the first transistor N1, and (W/L)N2is the channel width to channel length ratio of the second transistor N2. As discussed herein, although the sensing amplifier300in one or more embodiments is designed to achieve the relationship defined in Equation (4), due to one or more variations, such as PVT variations, it is possible that the actual ratios Id1/Id2and CBL,total/CBLB,totalare close, but not necessarily equal to each other. In such situations, the ratio Id1/Id2is still considered matched with the ratio CBL,total/CBLB,total.

One or more effects described with respect to the sensing amplifier200, such as compact layout area, improved read speed and read margin, is/are also obtainable in the sensing amplifier300in accordance with some embodiments. Further simulation results indicate that, with no dummy output device or dummy conductive pattern connected to the second node B, the sensing amplifier in accordance with some embodiments achieves equal or better mismatch and/or offset voltage performances compared to other approaches that connect a dummy output device and/or a dummy conductive pattern to the second node B for symmetry. The sensing amplifier in accordance with some embodiments achieves an overall read speed improvement of about 15% over the other approaches. The read time distribution of the sensing amplifier in accordance with some embodiments is also tighter than in the other approaches, achieving an improvement of about 60%. The sensing amplifier in accordance with some embodiments further achieves a low voltage performance at least equal to the other approaches, and is capable to operate at lower than 80% of nominal operational voltage (0.8*Vdd).

FIG. 4is a schematic block diagram of an asymmetric sensing amplifier400for a memory device401in accordance with some embodiments. The memory device401comprises a plurality of pairs of bit lines. Four pairs of bit lines BL[0]/BLB[0], BL[1]/BLB[1], BL[2]/BLB[2], and BL[3]/BLB[3] are shown inFIG. 4for illustrative purposes. Other numbers of bit lines are within the scope of various embodiments. Each pair of bit lines is coupled to multiple memory cells similarly to the first and second bit lines BLU/BLBU coupled to the memory array302. The sensing amplifier400is similar to the sensing amplifier300, except that the output device NAND1in the sensing amplifier300is replaced with an output device INV, which is an inverter. The sensing amplifier400is coupled to the pairs of bit lines BL[0]/BLB[0]˜BL[3]/BLB[3] via a column selector450, and a pair of data lines including a first data line DL and a second data line DLB. The first data line DL is coupled to the first node A, and the second data line DLB is coupled to the second node B.

The column selector450includes a plurality of pair of switches. Four pairs of switches S[0]/SB[0], S[1]/SB[1], S[2]/SB[2], and S[3]/SB[3] are shown inFIG. 4for illustrative purposes. Other numbers of switches are within the scope of various embodiments. Each pair of switches of the column selector450includes a first switch S[0]˜S[3] coupled between the first data line DL and the corresponding first bit line BL[0]˜BL[3], and a second switch SB[0]˜SB[3] coupled between the second data line DLB and the corresponding second bit line BLB[0]˜BLB[3]. The first and second switches in each pair of switches S[0]/SB[0]˜S[3]/SB[3] are configured to be turned ON or OFF by a common column select signal Ysel[0]˜Ysel[3]. When a memory cell of the memory device401is accessed in a read operation, the corresponding pair of bit lines BL[0]/BLB[0]˜BL[3]/BLB[3] is coupled to the pair of data lines DL/DLB by turning ON the corresponding pair of switches S[0]/SB[0]˜S[3]/SB[3]. In some embodiments, the switches S[0]/SB[0]˜S[3]/SB[3] are PMOS transistors. Other configurations for the column selector450are within the scope of various embodiments

Two PMOS transistors M3and M4are coupled to the corresponding first data line DL and second data line DLB. The PMOS transistors M3and M4define a pre-charging circuit corresponding to the pre-charging circuit104U or104L described with respect toFIG. 1. The PMOS transistors M3and M4are turned ON or OFF by a common pre-charging signal PREG corresponding to the pre-charging signal PREGU, PREGL described with respect toFIG. 1.

The operation of the sensing amplifier400is similar to the operation of the sensing amplifier300. Specifically, one pair of bit lines BL[0]/BLB[0]˜BL[3]/BLB[3] is selected by the column selector450to be coupled to the sensing amplifier400at a time. A memory cell in the memory array coupled to the selected pair of bit lines is accessed via the corresponding word line. The first node A and second node B are pulled up or down depending on the datum read out from the accessed memory cell.

The ratio Id1/Id2of the sensing amplifier400is configured to approach the ratio C(BL,total+DL,total)/C(BLB,total+DLB,total)of the total capacitance loading C(BL,total+DLB,total)of the first node A to the total capacitance loading C(BLB,total+DLB,total)of the second node B. The total capacitance loading C(BL,total+DLB,total)of the first node A is a sum of (a) parasitic capacitances of one or more memory cells coupled via one of the first bit lines BL[0]˜BL[3] and the column selector450to the first data line DL and (b) parasitic capacitances of components of the sensing amplifier400coupled to the first data line DL. The total capacitance loading C(BLB,total+DLB,total)of the second node B is a sum of (a) parasitic capacitances of one or more memory cells coupled via one of the second bit lines BLB[0]˜BLB[3] and the column selector450to the second data line DLB and (b) parasitic capacitances of components of the sensing amplifier400coupled to the second data line DLB. In some embodiments, the memory arrays coupled to the pairs of bit lines BL[0]/BLB[0]˜BL[3]/BLB [3] are identical, and C(BL,total+DL,total)and C(BLB,total+DLB,total)are determined by the Equations (1) and (2), where Carray,totalis a sum of the memory cells capacitance in one memory array coupled to one pair of bit lines BL[0]/BLB[0]˜BL[3]/BLB[3], and Cnand,gateis replaced with a gate capacitance of the output device INV. In some embodiments, the ratio Id1/Id2of the sensing amplifier400is matched to the ratio C(BL,total+DL,total)/C(BLB,total+DLB,total). One or more effects described with respect to the sensing amplifier300is/are obtainable in the sensing amplifier400in accordance with some embodiments.

FIG. 5is a flow chart of a method500of designing a memory device in accordance with some embodiments. In some embodiments, the memory device to be designed by the method500corresponds to the memory device101, memory device201, memory device301or memory device401described herein. An example of designing the memory device201by the method500in accordance with some embodiments will be described in the following description. The memory device101,301or401is designed in a similar manner by the method500in accordance with some embodiments.

At operation505, a total capacitance loading of a first node A of an asymmetric sensing amplifier200of the memory device201is determined. As described herein, in some embodiments, the total capacitance loading of the first node A is a sum of parasitic capacitances of components coupled to the first node A. In a specific example, the total capacitance loading of the first node A is determined by Equation (1).

At operation510, a total capacitance loading of a second node B of the asymmetric sensing amplifier200of the memory device201is determined. As described herein, in some embodiments, the total capacitance loading of the second node B is a sum of parasitic capacitances of components coupled to the second node B. In at least one specific example, the total capacitance loading of the second node B is determined by Equation (2).

At operation515, at least one of a first circuit216or a second circuit226of the asymmetric sensing amplifier200is configured, based on a ratio of the determined total capacitance loading of the first node A to the determined total capacitance loading of the second node B. In one or more embodiments, the first circuit216and/or the second circuit226is/are configured to have a first current I1with which the first circuit216pulls the first node A toward a predetermined voltage in response to a first datum (e.g., a logical “0”) read out from a memory cell greater than a second current I2with which the second circuit226pulls the second node B toward the predetermined voltage in response to a second datum (e.g., a logical “1”) read out from the memory cell. In one or more embodiments, the first current I1is defined by a drain current of a first transistor in the first circuit216, the second current I2is defined by a drain current of a second transistor in the second circuit226, and the first transistor is larger in size than the second transistor. In at least one embodiment, the first transistor has a greater channel width to channel length ratio than the second transistor. In some embodiments, the ratio I1/I2is matched with the ratio of the total capacitance loading of the first node A to the total capacitance loading of the second node B. In at least one specific example, the matching is achieved in accordance with Equation (4) and/or Equation (5).

FIG. 6is a block diagram of a computer system600in accordance with some embodiments. The method500described with respect toFIG. 5is realized in some embodiments by one or more computer systems600ofFIG. 6. The system600comprises at least one processor601, a memory602, a network interface (I/F)606, a storage610, an input/output (I/O) device608, and one or more hardware components618communicatively coupled via a bus604or other interconnection communication mechanism.

The memory602comprises, in some embodiments, a random access memory (RAM) and/or other dynamic storage device and/or read only memory (ROM) and/or other static storage device, coupled to the bus604for storing data and/or instructions to be executed by the processor601, e.g., kernel614, user space616, portions of the kernel and/or the user space, and components thereof. The memory602is also used, in some embodiments, for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor601.

In some embodiments, a storage device610, such as a magnetic disk or optical disk, is coupled to the bus604for storing data and/or instructions, e.g., kernel614, user space616, etc. The I/O device608comprises an input device, an output device and/or a combined input/output device for enabling user interaction with the system600. An input device comprises, for example, a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to the processor601. An output device comprises, for example, a display, a printer, a voice synthesizer, etc. for communicating information to a user.

In some embodiments, one or more operations and/or functionality described with respect toFIG. 5are realized by the processor601, which is programmed for performing such operations and/or functionality. One or more of the memory602, the I/F606, the storage610, the I/O device608, the hardware components618, and the bus604is/are operable to receive instructions, data and/or other parameters for processing by the processor601.

In some embodiments, one or more of the operations and/or functionality described with respect toFIG. 5is/are implemented by specifically configured hardware (e.g., by one or more application specific integrated circuits or ASIC(s)) which is included separate from or in lieu of the processor601. Some embodiments incorporate more than one of the described operations and/or functionality in a single ASIC.

The above method embodiment shows example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing various embodiments.

According to some embodiments, a sensing amplifier for a memory device comprises first and second nodes, an input device and an output device. The memory device comprises first and second bit lines, and at least one memory cell coupled to the first and second bit lines. The first node is configured to be coupled to the first bit line. The second node is configured to be coupled to the second bit line. The input device is coupled to the first and second nodes and configured to generate a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node, and configured to output the first or second datum read out from the memory cell. The first current is greater than the second current.

According to some embodiments, a memory device comprises at least one pair of bit lines including a first bit line and a second bit line, at least one memory cell coupled to the first and second bit lines, first through fourth transistors, and an output device. The first and third transistors are coupled in series between a power supply voltage node and a reference node. The second and fourth transistors are coupled in series between the power supply voltage node and the reference node. The first transistor is coupled to the third transistor at a first node. The first node is configured to be coupled to the first bit line. The first node is coupled to gates of the second and fourth transistors, and to the output device. The second transistor is coupled to the fourth transistor at a second node. The second node is configured to be coupled to the second bit line. The second node is coupled to gates of the first and third transistors. A ratio of a first drain current of the first transistor to a second drain current of the second transistor matches a ratio of a total capacitance loading of the first node to a total capacitance loading of the second node.

In some embodiments, a method of designing a memory device is performed by at least one processor. The method comprises determining a total capacitance loading of a first node and a total capacitance loading of a second node of an asymmetric sensing amplifier. The asymmetric sensing amplifier has complementary logic states at the first node and second node. The method further comprises configuring at least one of a first circuit or a second circuit of the asymmetric sensing amplifier based on a ratio of the determined total capacitance loading of the first node to the determined total capacitance loading of the second node. The first circuit is associated with the first node, and the second circuit is associated with the second node.