Method of boosting RON*COFF performance

An apparatus includes one or more field effect transistors configured as a switch. Each of the one or more field effect transistors comprises one or more source diffusions, one or more drain diffusions, and one or more gate fingers. Each of the one or more gate fingers is disposed between a source diffusion and a drain diffusion. A first electrical connection to the one or more source diffusions is made using one or more source electrodes that extend from a first end for a first length along a long axis of the source diffusions. A second electrical connection to the one or more drain diffusions is made using one or more drain electrodes that extend from a second end for a second length along a long axis of the drain diffusions. The first length of the one or more source electrodes and the second length of the one or more drain electrodes are generally selected to avoid juxtaposition of the one or more source electrodes and the one or more drain electrodes.

This application relates to U.S. Provisional Application No. 62/626,942, filed Feb. 6, 2018, which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to radio frequency (RF) switching generally and, more particularly, to a method and/or apparatus for boosting RON*COFF performance.

BACKGROUND

A key metric for radio frequency (RF) switching is RON*COFF performance. RON*COFF is a ratio of how much loss occurs when a radio signal passes through a switch in a conducting (ON) state (e.g., RON, or on-resistance) and how much the radio signal leaks through the switch in a non-conducting (OFF) state (e.g., COFF, or off-capacitance). Low RON*COFF is critical to ensure a switch with low insertion loss (low RON) as well as high isolation (low COFF).

It would be desirable to implement a method and/or apparatus for boosting RON*COFF performance.

SUMMARY

The invention concerns an apparatus comprising one or more field effect transistors configured as a switch. Each of the one or more field effect transistors comprises one or more source diffusions, one or more drain diffusions, and one or more gate fingers. Each of the one or more gate fingers is disposed between a source diffusion and a drain diffusion. A first electrical connection to the one or more source diffusions is made using one or more source electrodes that extend from a first end for a first length along a long axis of the source diffusions. A second electrical connection to the one or more drain diffusions is made using one or more drain electrodes that extend from a second end for a second length along a long axis of the drain diffusions. The first length of the one or more source electrodes and the second length of the one or more drain electrodes are generally selected to avoid juxtaposition of the one or more source electrodes and the one or more drain electrodes.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention include providing a method and/or apparatus for boosting RON*COFF performance that may (i) reduce an off-capacitance of a field effect transistor, (ii) pattern source and drain electrodes to avoid juxtaposition of the electrodes, (iii) provide improved isolation in a radio frequency (RF) switch, (iv) reduce radio signal leakage through an RF switch in a non-conducting (OFF) state, and/or (v) be implemented as one or more integrated circuits.

In wireless systems, a front-end module (FEM) provides an interface between an antenna and an RF transceiver. A FEM typically includes power amplifiers, switches, low-noise amplifiers, control circuitry, and passive elements. Wireless infrastructure, time division duplex (TDD) active antenna systems, and small cell base stations can involve switching high power levels (e.g., 35 dBm) at high frequencies (e.g., >2 GHz). The number of RF switch devices per phone has increased with the shift to 4G, or long-term evolution (LTE), and may be expected to grow with the introduction of 5G applications. A majority of the switches going into cellular (or smart) telephones are Silicon on Insulator (SOI). Although RF switches may utilize a variety of technologies, field effect transistor (FET) switches are typically used in cellular applications to lower power demand and extend battery life. In various embodiments, an RF switch is implemented utilizing a FET layout configured to reduce an off-capacitance of the FETs making up the RF switch, provide improved isolation, and reduce radio signal leakage through the RF switch in a non-conducting (OFF) state. In an example, source and drain electrodes of the FETs are patterned to avoid (or minimize) juxtaposition of the electrodes.

Referring toFIG. 1, a block diagram of a circuit80is shown illustrating an example application of a radio frequency (RF) switch in accordance with an embodiment of the invention. In an example embodiment, the circuit80may implement a transceiver. A transceiver is capable of both transmitting and receiving signals of a communication channel. In various embodiments, the circuit80may be capable of transmitting and receiving radio frequency (RF), microwave, and/or millimeter-wave signals. In various embodiments, the circuit80may be representative of transceiver circuits utilized in applications including, but not limited to cellular base stations (e.g., 2G, 3G, 4G, 5G, etc.), wireless communication systems, wireless local area networks (WLANs), wireless backhaul channels, broadband repeaters, community antenna television (CATV) networks, macro cells, micro cells, pico cells, femto cells, mobile devices (MDs), and portable handheld devices (UEs).

In an example, the circuit80may comprise a block (or circuit)82, a block (or circuit)84, and an antenna port86. In an example, the circuit82may be implemented as a stand alone transmitter circuit. In another example, the circuit82may be implemented as a transmit chain of a transceiver integrated circuit. In an example, the circuit84may be implemented as a stand alone receiver circuit. In another example, the circuit84may be implemented as a receive chain of the transceiver integrated circuit embodying the transmit chain82.

In an example, the transmitter or transmit chain82may comprise a first (input) amplifier90and a second (output) amplifier92. In an example, the amplifier90may be implemented as a variable gain amplifier (VGA) and the amplifier92may be implemented as a power amplifier (PA). The VGA amplifier90may be coupled, directly or indirectly through other components, to the power amplifier92. In various embodiments, the circuit82may further comprise one or more of additional components (e.g., RF amplifiers, IF amplifiers, RF mixers, digital step attenuators (DSAs), broadband modulators, wideband voltage variable attenuators, etc.), not shown.

In an example, the receive chain84may comprise a first (input) amplifier94and a second (output) amplifier96. In an example, the amplifier94may be implemented as a low noise amplifier (LNA) and the amplifier96may be implemented as a variable gain amplifier (VGA). The LNA94may be coupled, directly or indirectly through other components, to the VGA96. In various embodiments, the circuit84may further comprise one or more of additional components (e.g., filters, limiters, RF amplifiers, IF amplifiers, RF mixers, digital step attenuators (DSAs), broadband demodulators, wideband voltage variable attenuators, etc.), not shown.

In an example, the transmitter or transmit chain82, the receiver or receive chain84, and the antenna port86may be coupled together via a block (or circuit)100. The circuit100generally implements a transmit/receive (T/R) switch in accordance with an example embodiment of the present invention. In an example, the circuit100may be implemented as a stand alone integrated circuit. In another example, the circuit100may be integrated, along with the transmit chain82and the receive chain84, within a transceiver integrated circuit.

In an example, the circuit100may have a first (input) port102, a second (output) port104, a third (common) port106, and a control input108. The first port may be coupled to an output of the transmitter or transmit chain82. The second port104may be coupled to an input of the receiver or receive chain84. The common port106may be coupled to the antenna port86. The control input108may receive a signal (e.g., T/R). The signal T/R may implement a control signal for switching between a transmit mode where a signal is directed from the first (TX) port102to the common (TRX) port106and a receive mode where a signal is directed from the common (TRX) port106to the second (RX) port104. In an example, the signal T/R may be implemented as summarized in the following TABLE 1:

The signal T/R may be presented either directly to the input108or through a conditioning circuit (e.g., where a clean control signal cannot be guaranteed due to overshoot, undershoot, ringing, etc.).

Referring toFIG. 2, a diagram is shown illustrating an example implementation of the circuit100ofFIG. 1. In an example, the circuit100may implement a single-pole double throw (SPDT or SP2T) switch. However, other numbers of poles and/or throws may be implemented accordingly to meet design criteria of particular applications. In an example, the circuit100may be implemented as a high-power RF switch utilizing a silicon-on-insulator (SOI) process. However, in other examples, the circuit100may be implemented utilizing a CMOS fabrication process on bulk silicon or utilizing any other transistor technology in which terminals of the transistor are in juxtaposition generally.

In an example, the circuit100may comprise a series transmit switch110, a shunt transmit switch112, a series receive switch114, and a shunt receive switch116. In an example, each of the switches110,112,114, and116may be implemented by a large number (e.g., 24) of series connected stacked devices. However, other numbers (e.g., 2, 3, 4, 8, etc.) of stacked devices may be used to meet design criteria of a particular application. In various embodiments, each of the switches110,112,114, and116may be implemented having a similar number or a different number of stacked devices. In an example, the stack of 24 devices may handle up to a 44 dBm input power. The switch100generally occupies a large die area due to the high number of stacked devices. In addition to withstanding high input power in the OFF state, the stacked devices need to provide good isolation (low COFF). With a conventional layout technique, the high number of stacked devices making up the switches110,112,114, and116would have negative effects (e.g., through substrate loss and parasitic substrate capacitance due to the large device size and high stacking count). Instead of using the conventional technique, the devices making up the switches110,112,114, and116are generally configured (e.g., through source and drain electrode layout) to minimize parasitic source-drain capacitance (CSD) to minimize the amount of the input radio signal leaks through the switch in the non-conducting (OFF) state.

In various embodiments, the switches110,112,114, and116are used to route signals between an RF input port (e.g., TX), an RF output port (e.g., RX), and an RF common port (e.g., TRX). In an OFF state, the switch114needs to withstand the high input power levels (e.g., over 40 dBm) generally associated with transmitting wireless communications signals. In the OFF state, the relatively high input voltage is spread out among the individual devices in the stack of the switch114, reducing the voltage across each individual device, in order to prevent breakdown. Stacking the devices is important because the drain-to-source breakdown voltage (BVDS) and the drain-to-gate breakdown voltage (BVDG) of a single FET may be on the order of 2 to 4 volts (V) (3.5V typically) depending on the particular process technology.

In an example, an output of a transmit chain may be coupled to a first terminal of the series transmit switch110and a first terminal of the shunt transmit switch112. A second terminal of the series transmit switch110may be coupled to the RF common port (TRX) and a first terminal of the series receive switch114. In an example, the RF common port TRX may be connected to an antenna or a transmission line. A second terminal of the series receive switch114may be coupled to a first terminal of the shunt receive switch116and the RF output port RX. In an example, an input of a receive chain may be coupled to the RF output port RX. A second terminal of the shunt transmit switch112and a second terminal of the shunt receive switch116may be coupled to a circuit ground potential.

A high power RF switch generally utilizes a high number of stacked devices. Because of the high number of stacked devices, traditional high power SOI switches use a large die area. The traditionally configured high power switch generally has negative effects through substrate loss and parasitic substrate capacitance due to the large device size and high stacking. Due to large gate capacitance, fast switching time (e.g., <0.5 microsecond) is hard to implement with traditionally configured switches without degradation of insertion loss. Applications with traditionally configured switches may involve a trade-off between insertion loss and fast switching time through gate resistance. Obtaining a good return loss is also difficult due to large parasitic substrate capacitance.

In an example, the RF input port may be connected to an output end of a transceiver transmit chain and the RF output port RX may be connected to an input end of a transceiver receive chain. In a transmit mode, the series transmit switch110is in a conducting state (e.g., closed or ON), the shunt transmit switch112is in a non-conducting state (e.g., open or OFF), the series receive switch114is in a non-conducting state (e.g., open or OFF), and the shunt receive switch116is in a conducting state (e.g., closed or ON). In a receive mode, the series transmit switch110is in a non-conducting state (e.g., open or OFF), the shunt transmit switch112is in a conducting state (e.g., closed or ON), the series receive switch114is in a conducting state (e.g., closed or ON), and the shunt receive switch116is in a non-conducting state (e.g., open or OFF). Because of the magnitude of the transmit power, the series receive switch114generally needs to have a high breakdown rating to isolate the receive chain during the transmit mode. Because the series receive switch114is directly in the signal path of the receive chain, the series receive switch114directly contributes to insertion loss (IL) and noise figure (NF) ratings of the receiver input.

Referring toFIG. 3, a schematic diagram is shown illustrating an example of a stacked device implementation of the high power switch ofFIG. 1. In various embodiments, each of the switches110,112,114, and116may be implemented as a number of devices (e.g., transistors) stacked in series. In an example, the switch110may comprise a number of transistors M1a-M1n, the switch112may comprise a number of transistors M2a-M2n, the switch114may comprise a number of transistors M3a-M3n, and the switch116may comprise a number of transistors M4a-M4n. In an example, the switches110,112,114, and116may be implemented as stack-of-24 (So24) devices (e.g., n=24). In an example, the So24 devices may handle a maximum 44 dBm input power.

Field effect transistors (FETs) are typically used in cellular applications to meet low power demands of cellular applications. To handle the relatively high (e.g., tens of volts) RF voltages, the FETs making up the switches110,112,114, and116are typically stacked. The term stacked is used to describe a configuration where the drain of one transistor is the source of the next transistor.

In an example, the relatively high input voltage is spread out among the individual devices in the stack of the switches110,112,114, and116, reducing the voltage across each individual device, in order to prevent breakdown. Stacking the devices of the traditional configuration is important because the drain-to-source breakdown voltage (BVDS) and the drain-to-gate breakdown voltage (BVDG) of a single FET may be on the order of 2 to 4 volts (V) (3.5V typically) depending on the particular process technology, while the RF signals may be on the order of 20 or more volts. The individual transistors of each stack may also be configured to more evenly distribute the RF voltage. By stacking the devices, the relatively high voltage typically used in most RF front-end modules is dispersed over several (e.g., typically twelve or more), so that the voltage across any one device is relatively small, making breakdown unlikely. Ideally, each of the devices in the stack should have substantially the same drain-to-source voltage.

In an example, each of the switches110,112,114, and116receives a control signal (e.g., SR1, SH1, SR2, and SH2, respectively). When the respective control signal is held LOW, the corresponding switch is generally in a non-conducting state (e.g., open or OFF), blocking signals from passing through. When the respective control signal is held HIGH, the corresponding switch is generally in a conducting state (e.g., closed or ON), allowing the signals to pass through. In an example, when the control signals SR1 and SH2 are held HIGH and the control signals SR2 and SH1 are held LOW, the series transmit switch110allows signals to pass from the RF input port TX to the common RF port TRX and the shunt receive switch116directs signals to ground. When the control signals SR1 and SH2 are held LOW and the control signals SR2 and SH1 are held HIGH, the series receive switch114allows signals to pass from the RF common port TRX to the RF output port RX and the shunt transmit switch112directs signals to ground.

In some embodiments, the switches110and116may receive a first control signal and the switches112and114may receive a second control signal. In various embodiments, the signals SR1, SH1, SR2, SH2 may be derived from a single transmit/receive (T/R) control signal. In an example, a transmit mode may have the signal T/R held HIGH, resulting in the control signals SR1 and SH2 being held HIGH and the control signals SR2 and SH1 being held LOW. In another example, a receive mode may have the signal T/R held LOW, resulting in the control signals SR1 and SH2 being held HIGH and the control signals SR2 and SH1 being held LOW. However, other polarities may be implemented to meet design criteria of a particular implementation.

A typical antenna switch needs a high breakdown voltage (e.g., up to 30V swing) due to a combination of high power and mismatch at the antenna. To withstand such high voltages, multiple FETs are stacked to form a switch arm. For example, the switches110and112form a transmit arm of the switch100and the switches114and116form a receive arm of the switch100. Due to substrate loss, the capability of stacked FETs has diminishing marginal improvement as more and more FETs are stacked into a switch arm. Also, as more FETs are stacked, increasing parasitic capacitance actually degrades the overall switch performance.

Switches are designed in series-shunt configuration, where series arms provide a low resistance path for the RF signal between the ON ports, and shunt arms provide a low resistance path for the RF power that leaks to the OFF ports. For switches with a high throw count, large parasitic capacitance of OFF arms provides a leakage path for the RF signal, which translates into signal loss and/or insertion loss for the ON arm. This effect can impose a severe limitation on throw count for technologies with higher RON*COFF.

The switches114and116are generally implemented by large numbers of series connected stacked devices. In an example, each of the switches114and116may be implemented as a stack of 24 devices (e.g., transistors). In an example, the stack of 24 devices may handle a maximum 44 dBm input power. In an OFF state, the large number of stacked devices is needed to withstand the high input power (e.g., over 40 dBm) generally associated with transmitters. The relatively high input voltage is spread out among the individual devices in the stack, reducing the voltage across each individual device, preventing breakdown. Stacking the devices is important because the drain-to-source breakdown voltage (BVDS) and the drain-to-gate breakdown voltage (BVDG) of a single FET may be on the order of 2 to 4 volts depending on the particular process technology.

In addition to withstanding the high input power in the OFF state, the stacked devices need to provide good isolation and good frequency response/bandwidth (low COFF). High COFF degrades overall frequency response/bandwidth of a system. The stacked devices in accordance with embodiments of the invention are generally configured to minimize or avoid juxtaposition of the source and drain electrodes to minimize the parasitic capacitances of the OFF arms (off-capacitance or COFF). SOI technology involves placing an insulation layer beneath the field effect transistor (FET) channel. The insulation layer limits the space of the channel. The insulation layer also limits any current flow around the depletion region when the transistor is in the non-conducting (OFF) state. The insulator restricts the current to the space directly between the drain and source wells. The current restriction allows for an extremely high ROFF when compared to regular FET technology, and increases isolation as well.

The devices making up the switches114and116are generally configured to minimize parasitic source-drain capacitance (CSD) to minimize the amount of the input radio signal that leaks through the switch in the non-conducting (OFF) state. Part of the source-drain capacitance in the devices making up the switches114and116is contributed by capacitance between metal conductors forming the source and drain connections. In various embodiments, the source-drain capacitance between the metal source and drain conductors is adjusted by varying the configuration of the metal layer and via layer source/drain connections.

Referring toFIG. 4, a diagram of a transistor layout200is shown illustrating a source-drain configuration in accordance with an example embodiment of the invention. In an example, the transistor layout200comprises a source diffusion202, a drain diffusion204, and a gate disposed above a channel between the source and drain diffusions. A source conductor210is formed in a metal layer (e.g., M1) partially overlapping the source diffusion202. A drain conductor212is formed in the metal layer (e.g., M1) partially overlapping the drain diffusion204. An ohmic region214of the source diffusion202and an ohmic region216of the drain diffusion204are connected to the source conductor210and the drain conductor212, respectively, by a number of vias218. In contrast to convention field effect transistor layout, the source conductor210and the drain conductor212are configured to avoid any juxtaposition with one another. The configuration of the source conductor210and the drain conductor212maximizes the separation between the source conductor210and the drain conductor212(and the respective vias218), reducing the source-drain capacitance component attributable to the source and drain conductors.

Referring toFIG. 5, a diagram of a transistor layout300is shown illustrating another source-drain configuration in accordance with an example embodiment of the invention. In another example, the transistor layout300comprises a source diffusion302, a drain diffusion304, and a gate disposed above a channel between the source and drain diffusions. A source conductor310is formed in a metal layer (e.g., M1) partially overlapping the source diffusion302. A drain conductor312is formed in the metal layer (e.g., M1) partially overlapping the drain diffusion304. An ohmic region314of the source diffusion302and an ohmic region316of the drain diffusion304are connected to the source conductor310and the drain conductor312, respectively, by a number of vias318. The source conductor310and the drain conductor312may still be configured to avoid any juxtaposition with one another. However, instead of being of equivalent length, the source conductor310may have a first length and the drain conductor312may have a second length, different from the first length. In an example, instead of the source conductor310and the drain conductor312each covering 50% of the long axis of the source diffusion302and the drain diffusion304, respectively, some other ratio (e.g., 25%/75%, 33%/67%, 75%/25%, 67%/33%, etc.) may be implemented depending upon particular design criteria of the particular application. The configuration of the source conductor310and the drain conductor312generally maximizes the separation between the source conductor310and the drain conductor312(and the respective vias318), reducing the source-drain capacitance component attributable to the source and drain conductors.

Referring toFIG. 6, a diagram of a transistor layout400is shown illustrating yet another source-drain configuration in accordance with an example embodiment of the invention. In another example, the transistor layout400comprises a source diffusion402, a drain diffusion404, and a gate406disposed above a channel between the source diffusion402and the drain diffusion404. A source conductor410is formed in a metal layer (e.g., M1) partially overlapping the source diffusion402. A drain conductor412is formed in the metal layer (e.g., M1) partially overlapping the drain diffusion404. An ohmic region414of the source diffusion402and an ohmic region416of the drain diffusion404are connected to the source conductor410and the drain conductor412, respectively, by a number of vias418. The source conductor410and the drain conductor412may be further configured to avoid any juxtaposition with one another by a gap420between ends of the source conductor410and the drain conductor412. In various embodiments, the gap420may be implemented with the source conductor410and the drain conductor412having similar or different respective lengths. In an example, instead of the source conductor410and the drain conductor412may each cover the long axis of the source diffusion402and the drain diffusion404, respectively, by some ratio (e.g., 50%/50%, 25%/75%, 33%/67%, 75%/25%, 67%/33%, etc.), less the length of the gap420. The configuration of the source conductor410and the drain conductor412generally maximizes the separation between the source conductor410and the drain conductor412(and the respective vias418), reducing the source-drain capacitance component attributable to the source and drain conductors.

Referring toFIG. 7, a diagram of a transistor layout500is shown illustrating a multi-finger field effect transistor layout in accordance with an example embodiment of the invention. The transistors in RF switches are generally expected to sustain a significant amount of current. In an example, the transistors in the RF switch may be distributed over an area of a circuit wafer in a multi-finger layout. In an example, the transistor layout500comprises a multi-finger source conductor502formed in a metal layer (e.g., M1) partially overlapping source diffusions, a multi-finger drain conductor504formed in the metal layer (e.g., M1) partially overlapping drain diffusions, and a multi-finger gate506disposed above a channel between the source and drain diffusions. An ohmic region of the source diffusions and an ohmic region of the drain diffusions are connected to the fingers of the source conductor502and the fingers of the drain conductor504, respectively, by a number of vias (as illustrated inFIGS. 3-6). The fingers of the source conductor502and the drain conductor504are generally configured to avoid any juxtaposition with one another. The fingers of the source conductor502and the drain conductor504are laid out in an alternating basis. The multi-finger transistor generally operates like a set of many smaller transistors in parallel, providing an effective transistor width that is greater than the transistor length.

Although embodiments of the invention may have been described in the context of a 5G application, the present invention is not limited to 5G applications, but may also be applied in other high data rate wireless and wired communications applications where different rapid switching, multiple channel, and multiple user issues may exist. The present invention addresses concerns related to high speed wireless communications, mobile and stationary transceivers and point-to-point links. Future generations of wireless communications applications using radio frequency (RF), microwave, and millimeter-wave links can be expected to provide increasing speed, increasing flexibility, and increasing numbers of interconnections and layers. The present invention may also be applicable to wireless communications systems implemented in compliance with either existing (legacy, 2G, 3G, 4G, etc.) specifications or future specifications.