Resistive random access memory device and method for manufacturing the same

According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-178787, filed on Sep. 3, 2014; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a resistive random access memory device and a method for manufacturing the same.

BACKGROUND

Recently, the development of a two-terminal resistive random access memory device typified by a ReRAM (resistive random access memory) has been actively carried out. This resistive random access memory device enables low-voltage operation, high-speed switching, and miniaturization, and therefore is a potent candidate for a next-generation large-capacity memory device to replace a floating-gate type NAND flash memory. As a large-capacity memory device using this resistive random access memory device as a memory cell, a memory with a cross-point structure has been proposed.

In a memory with a cross-point structure, when an excessive current flows through a memory cell, the memory cell is destroyed, and therefore, it is preferred to suppress a current by a method in which a load resistance is connected in series to the memory cell, or the like.

A material of such a load resistance preferably has a higher resistivity than a material to be used for an interconnection or the like and has substantially linear current-voltage characteristics. For example, insulating materials such as silicon nitride (SiN), silicon oxide (SiO2), and aluminum nitride (AlN), each of which has insulating properties, have a high resistance, but do not have linear current-voltage characteristics, and therefore are not so suitable as a material of a load resistance.

DETAILED DESCRIPTION

According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode, having resistivity higher than resistivity of the first electrode and the second electrode, and including at least a first element and a second element. A concentration profile of the first element along a direction from the first electrode to the second electrode in the conductive layer repeating high and low concentrations.

According to one embodiment, a method for manufacturing a resistive random access memory device includes forming a resistance change layer on a first electrode and forming a second electrode on the resistance change layer. The method for manufacturing a resistive random access memory device also includes forming a conductive layer having resistivity higher than resistivity of the first electrode and the second electrode so as to be connected to the first electrode or the second electrode. The method for manufacturing a resistive random access memory device also includes the forming a conductive layer including forming a first material layer by depositing a first material and forming a second material layer including a second material which is different from the first material. The forming the first material layer and the forming the second material layer being repeated a plurality of times.

First, a first embodiment will be described.

FIG.1is a perspective view illustrating a resistive random access memory device according to the embodiment.

FIG.2is a cross-sectional view illustrating a portion shown inFIG.1.

FIG.3is a cross-sectional view illustrating a conductive layer of the resistive random access memory device according to the embodiment.

FIG.4Ais a graph illustrating a concentration profile of tantalum, silicon and nitrogen in the conductive layer of the resistive random access memory device according to the embodiment, wherein the abscissa represents a position in the vertical direction and the ordinate represents the concentration.

FIG.4Bis a graph illustrating a concentration profile of tantalum, silicon and nitrogen in the conductive layer of the resistive random access memory device according to the embodiment, wherein the abscissa represents a position in the vertical direction and the ordinate represents the concentration.

The resistive random access memory device according to the embodiment is a CBRAM (conduction-bridge RAM).

As shown inFIG.1, a resistive random access memory device1according to the embodiment is provided with a silicon substrate11, and a driving circuit (not shown) of the resistive random access memory device1is formed in an upper layer portion and on an upper surface of the silicon substrate11. On the silicon substrate11, an interlayer insulating film12composed of, for example, silicon oxide is provided so as to bury the driving circuit therein, and on the interlayer insulating film12, a memory cell section13is provided.

In the memory cell section13, a word line wiring layer14including a plurality of word lines WL extending in a direction parallel to the upper surface of the silicon substrate11(hereinafter referred to as “word line direction”) and a bit line wiring layer15including a plurality of bit lines BL extending in a direction which is parallel to the upper surface of the silicon substrate11and intersects, for example, is orthogonal to the word line direction (hereinafter referred to as “bit line direction”) are alternately stacked on each other. The adjacent word lines WL, the adjacent bit lines BL, and the adjacent word line WL and bit line BL are not in contact with each other. The word lines WL and the bit lines BL are formed from, for example, silicon (Si), tungsten (W), Carbon (C) and so on.

At a nearest neighbor point of each of the word lines WL and each of the bit lines BL, a pillar16extending in a direction perpendicular to the upper surface of the silicon substrate11(hereinafter referred to as “vertical direction”) is provided. The shape of the pillar16is, for example, a cylinder, a quadrangular prism, or a substantially quadrangular prism with rounded edges. The pillar16is formed between the word line WL and the bit line BL, and one memory cell MC is constituted by one pillar16. The resistive random access memory device1is a cross-point type device in which the pillar16is disposed at every nearest neighbor point of each of the word lines WL and each of the bit lines BL. Spaces among the word lines WL, the bit lines BL, and the pillars16are filled with an interlayer insulating film17(seeFIG.2).

As shown inFIG.2, in the pillar16of the resistive random access memory device according to the embodiment, a lower barrier metal layer21, a conductive layer22, an upper barrier metal layer23, a lower electrode24, a variable resistance layer25, a metal layer26, and an upper electrode27are stacked in this order from the word line WL side to the bit line BL side.

The variable resistance layer25and the metal layer26are collectively referred to as a resistance change layer31.

The lower barrier metal layer21is a layer which prevents a material of the word line WL from diffusing in the pillar16. The upper barrier metal layer23is a layer which prevents a material of the lower electrode24from diffusing in the conductive layer22. The lower barrier metal layer21and the upper barrier metal layer23are formed from, for example, tungsten nitride (WN) or tantalum nitride (TaN).

As shown inFIG.3, the conductive layer22is formed by alternately stacking a tantalum nitride layer28composed of tantalum nitride (TaN) and a silicon layer29composed of silicon (Si). Each tantalum nitride layer28and each silicon layer29have a thickness of, for example, about 1 nm (nanometer), and the thickness of the conductive layer22as a whole is, for example, 20 nm. The boundary surface between the tantalum nitride layer28and the silicon layer29is not always able to be clearly observed. When the concentration profile of tantalum, silicon and nitrogen along the vertical direction in the conductive layer22is measured, for example, a graph as shown inFIG.4Ais obtained. As shown inFIG.4A, the concentration profile of tantalum, silicon and nitrogen in the conductive layer22periodically fluctuates and repeats high and low concentrations. In other words, when focusing on one atom, a coarse part and a dense part are being repeated. InFIG.4A, a layer which has high concentrations of tantalum and silicon corresponds to a tantalum nitride layer28and a layer which has a high concentration of silicon corresponds to a silicon layer29. The thickness of the tantalum nitride layer28and the silicon layer29can be designed depending on a resistance value required for the conductive layer22. When a lower resistance value is required, the thickness of the tantalum nitride layer28is thickened and the thickness of the silicon layer29is thinned. The concentration profile is shown inFIG.4Bfor the case of the ratio (the thickness of the tantalum nitride layer28: the thickness of the silicon layer29) is equal to the ratio (3:2). The other way is that when a higher resistance value is required, the thickness of the tantalum nitride layer28is thinned and the thickness of the silicon layer29is thickened. For example, the ratio (the thickness of the tantalum nitride layer28: the thickness of the silicon layer29) range is favorable approximately to be from ratio (1:5) to ratio (5:1). Each of the thickness of the tantalum nitride layer28and the thickness of the silicon layer29is favorable, for example, approximately to be equal to or more than 0.2 nanometers and equal to or lower than 2.0 nanometers.

The concentration profiles of tantalum, silicon and nitrogen shown inFIG.4Ado not show the absolute concentration. The concentration profiles which are shown inFIG.4Ashow a high and a low concentration in the each element. For example, the concentrations of the tantalum and the nitrogen in the silicon layer29are lower than the concentration of those in the tantalum nitride layer28. The concentration of the silicon in the silicon layer29is higher than the concentration of that in the tantalum nitride layer28.

The resistivity of the conductive layer22as a whole is higher than the material to be used for the word line WL or the bit line BL, and the current-voltage characteristics are substantially linear.

The lower electrode24is formed from, for example, tungsten (W), and is connected to the upper barrier metal layer23and the variable resistance layer25.

The variable resistance layer25is connected to the lower electrode24and the metal layer26. For the variable resistance layer25, for example, one or more material selected from the group consisting of silicon, silicon oxide, silicon nitride, silicon oxynitride, and a metal oxide can be used. As the metal oxide, for example, one or more material selected from the group consisting of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, nickel oxide, tungsten oxide, and vanadium oxide can be used. Other than these, for the variable resistance layer25, an ion conductive material can be used. Examples of the ion conductive material include silver oxide (e.g. Ag2O), silver sulfide (e.g. Ag2S), silver selenide (e.g. Ag2Se), silver telluride (e.g. Ag2Te), silver iodide (e.g. AgI), copper iodide (e.g. CuI2), copper oxide (e.g. CuO), copper sulfide (e.g. CuS), copper selenide (e.g. CuSe), copper telluride (e.g. CuTe), and germanium oxide (e.g. GeO2). Further, the variable resistance layer25may have a structure in which a plurality of layers including any of these materials are stacked. These materials can be used without being limited to the specific compositional ratio described herein.

The metal layer26is connected to the variable resistance layer25and the upper electrode27. The material of the metal layer26may be, for example, one or more metal selected from the group consisting of silver (Ag), copper (Cu), zinc (Zn), gold (Au), titanium (Ti), nickel (Ni), cobalt (Co), tantalum (Ta), aluminum (Al), and bismuth (Bi), or an alloy, a nitride, or a silicide including one or more metal selected therefrom. As the alloy, for example, in the case of a copper alloy, examples thereof include CuTe and Cu-GST (Ge2Sb2Te5). Further, the metal layer26may have a structure in which a plurality of layers including these materials are stacked. These materials can be used without being limited to the specific compositional ratio described herein.

The upper electrode27is formed from, for example, tungsten (W), and is connected to the metal layer26and the bit line BL.

Next, a method of manufacturing a resistive random access memory device according to the embodiment will be described.

FIG.5is a view illustrating a method of manufacturing a resistive random access memory device according to the embodiment using a sputtering method.

First, as shown inFIG.1, an interlayer insulating film12is formed on a silicon substrate11.

Subsequently, word lines WL are formed by, for example, a damascene method.

Subsequently, on the word lines WL, a lower barrier metal layer21is formed.

Subsequently, on the lower barrier metal layer21, a conductive layer22is formed. The conductive layer22is formed by, for example, alternately depositing silicon (Si) and tantalum nitride (TaN) using a sputtering method.

Specifically, as shown inFIG.5, in a chamber40of a sputtering deposition apparatus, an intermediate structure41in which members up to the lower barrier metal layer21are formed on the silicon substrate11is placed, and at a position facing the intermediate structure41, a target51composed of tantalum nitride and a target42composed of silicon are placed. Then, the chamber is evacuated to vacuum. While disposing a shutter49at a position so as to cover the target42, for example, argon is introduced into the chamber and ionized. As a result, an argon ion47hits the target51, and a tantalum atom52and a nitrogen atom53sputtered from the target51are deposited on the intermediate structure41, whereby a tantalum nitride layer28is formed. Subsequently, the shutter49is transferred to a position so as to cover the target51. By doing this, an argon ion47hits the target42, and a silicon atom48sputtered from the target42is deposited on the intermediate structure41, whereby a silicon layer29is formed. Thereafter, by repeating the transfer of the shutter49, the tantalum nitride layer28and the silicon layer29are alternately formed.

Subsequently, an upper barrier metal layer23is formed on the conductive layer22. Then, on the upper barrier metal layer23, a lower electrode24is formed. Then, on the lower electrode24, a variable resistance layer25is formed. Then, on the variable resistance layer25, a metal layer26is formed. Then, on the metal layer26, an upper electrode27is formed.

Subsequently, on the upper electrode27, a mask (not shown) is formed and etching is performed, whereby a portion which is not covered with the mask is removed in the stacked body in which members from the lower barrier metal layer21to the upper electrode27are stacked, and thus, a pillar16is formed. Thereafter, spaces between the pillars16are filled with an interlayer insulating film17.

Subsequently, on the upper electrode27and the interlayer insulating film17, bit lines BL are formed in the same manner as in the case of forming the word lines WL.

Thereafter, the pillars16, the word lines WL, the pillars16, and the bit lines BL are formed repeatedly in the same manner as described above, whereby a resistive random access memory device1is manufactured.

Next, an operation of the resistive random access memory device according to the embodiment will be described.

FIGS.6A and6Bare cross-sectional views illustrating an operation of the resistive random access memory device according to the embodiment.FIG.6Ashows a case where the variable resistance layer25is in a high-resistance state andFIG.6Bshows a case where the variable resistance layer25is in a low-resistance state.

FIG.7is a graph illustrating the current-voltage characteristics of the resistive random access memory device according to the embodiment. The abscissa of the graph represents a voltage applied between the lower electrode24and the upper electrode27, and the ordinate represents the absolute value of a current flowing between the upper electrode27and the lower electrode24.

First, when a voltage (positive voltage) is applied to the pillar16in a state shown inFIG.6Asuch that the lower electrode24is used as a negative electrode and the upper electrode27is used as a positive electrode, as the portions iv and i shown inFIG.7, the current increases with an increase in the voltage. Then, when the voltage reaches a set voltage Vset, as the portion ii shown inFIG.7, the current rapidly increases.

This is because before applying the set voltage Vset, the variable resistance layer25is in a high-resistance state as shown inFIG.6A, however, by applying the set voltage Vset, the variable resistance layer25changes to a low-resistance state as shown inFIG.6B. That is, when applying the set voltage Vset, for example, a part of silver atoms (Ag) included in the metal layer26formed from silver (Ag) are ionized to be converted to silver ions (Ag+) and move toward the lower electrode24and permeate the variable resistance layer25. Then, these silver ions are coupled with electrons (e−) supplied from the lower electrode24, whereby silver atoms are deposited. As a result, a filament30composed mainly of silver is formed in the variable resistance layer25so that the variable resistance layer25changes from a high-resistance state to a low-resistance state, and thus, the current rapidly increases. This operation is called “SET”.

Thereafter, even if the maximum voltage Vmax is applied, the current is restrained by the conductive layer22, and an excessive current exceeding the maximum current Imax as the portion iii shown inFIG.7never flows. This is because by providing the conductive layer22, a sufficient resistance is interposed between the upper electrode27and the lower electrode24.

After the filament30is formed, the current begins to increase rapidly from the threshold voltage Vth which is lower than before forming the filament30, and the current changes along the portions iv-v-iii inFIG.7.

On the other hand, when a voltage (reverse voltage) is applied to the pillar16in a state shown inFIG.6Bsuch that the lower electrode24is used as a positive electrode and the upper electrode27is used as a negative electrode, and the absolute value thereof is made larger than the absolute value of a reset voltage Vreset, the variable resistance layer25changes from a low-resistance state to a high-resistance state.

This is because by applying the reverse voltage whose absolute value is larger than that of the reset voltage Vreset, the silver atoms forming the filament30are ionized again to be converted to silver ions and move toward the upper electrode27. Then, in the metal layer26, the silver ions are coupled with electrons supplied from the upper electrode27and return to silver atoms again, and therefore, at least a part of the filament30in the variable resistance layer25is lost. This operation is called “RESET”. When the variable resistance layer25is in a high-resistance state, the current changes along the portions iv-i-ii-iii inFIG.7.

When the variable resistance layer25is put into a high-resistance state once, the high-resistance state is maintained unless the voltage is made higher than the set voltage Vset. Further, when the variable resistance layer25is put into a low-resistance state once, the low-resistance state is maintained unless a reverse voltage whose absolute value is larger than that of the reset voltage Vreset is applied.

As shown inFIG.7A, when a current applying the positive voltage is higher than a current applying the negative voltage, a sneak current is favorably suppressed in a memory with a cross-point structure.

Next, an effect of the embodiment will be described.

In the embodiment, the conductive layer22is formed by alternately stacking the tantalum nitride layer28and the silicon layer29on each other.

By using silicon having high conductive properties and tantalum nitride having high insulating properties as the materials of the conductive layer22, the conductive layer22which has a favorable resistivity and also having substantially linear current-voltage characteristics can be realized. As a result, the voltage applied to the cell is distributed, and the breakdown of the resistive random access memory device due to an excessive current flowing through the resistance change layer31can be prevented.

In the embodiment, when the conductive layer22is formed, by performing sputtering alternately using the target42composed of silicon and the target51composed of tantalum nitride, the tantalum nitride layer28and the silicon layer29are alternately stacked on each other. Due to this, relatively soft targets can be used as the sputtering targets, and thus, little dust is generated accompanying sputtering.

On the other hand, it is also contemplated that as the conductive layer22, a single layer film composed of tantalum silicon nitride (TaSiN) is used. Also in this case, a conductive layer which has a high resistivity and also has favorable linear current-voltage characteristics can be obtained. However, in this case, when the conductive layer is formed by a sputtering method, a target composed of tantalum silicon nitride (TaSiN), which is a hard intermetallic compound, is used, and thus, a large amount of dust is generated accompanying sputtering.

Furthermore, according to the embodiment, by selecting the number of stacked layers of the tantalum nitride layer28and the silicon layer29, the resistance value of the conductive layer22can be set at will, and therefore, the degree of freedom of design of the device can be increased.

According to the embodiment, the conductive layer22is provided between the word line WL and the resistance change layer31, and therefore, impurities from the word line WL can be prevented from diffusing.

Next, a variation of the first embodiment will be described.

FIG.8is a cross-sectional view illustrating a resistive random access memory device according to the variation.

As shown inFIG.8, a lower barrier metal layer21, a conductive layer22and an upper barrier metal layer23are provided in this order on the whole upper surface of the word line WL and a lower electrode24, a variable resistance layer25, a metal layer26, and an upper electrode27are provided in this order on an intersection portion of the upper barrier metal layer23with the bit line BL.

The structure, manufacturing method and effect of the variation other than the above are the same as those of the first embodiment described above.

Next, a second embodiment will be described.

The resistive random access memory device according to the embodiment is a CBRAM (conduction-bridge RAM).

FIG.9is a cross-sectional view illustrating a conductive layer of the resistive random access memory device according to the embodiment.

As shown inFIG.9, a conductive layer34of the resistive random access memory device according to the embodiment is different from the conductive layer22(seeFIG.3) of the resistive random access memory device according to the first embodiment described above in that an aluminum layer32composed of aluminum (Al) and an aluminum nitride layer33composed of aluminum nitride (AlN) are alternately stacked on each other.

In the same manner as in the first embodiment, also the boundary surface between the aluminum layer32and the aluminum nitride layer33according to the embodiment is not always able to be clearly observed. The concentration profile of nitrogen (N) along the vertical direction in the conductive layer34periodically fluctuates in the same manner as in the first embodiment.

The configuration of the embodiment other than the above is the same as that of the first embodiment described above.

Next, a method of manufacturing a resistive random access memory device according to the embodiment will be described.

FIGS.10A to10Care cross-sectional views illustrating a method of manufacturing the conductive layer34according to the embodiment.

First, a method of forming members from an interlayer insulating film12to a lower barrier metal layer21on a silicon substrate11is the same as that of the first embodiment.

Subsequently, the conductive layer34is formed on the lower barrier metal layer21. A method of forming the conductive layer34will be described below.

First, as shown inFIG.10A, on the lower barrier metal layer21, an aluminum layer32is formed. Subsequently, as shown inFIG.10B, the surface of the aluminum layer32is nitridated. For example, an intermediate structure44in which members up to the aluminum layer32are formed on the silicon substrate11is heated in a nitrogen atmosphere to allow nitrogen to permeate the vicinity of the surface of the aluminum layer32, whereby the surface of the aluminum layer32is nitridated. As a result of the nitridation treatment, nitridation proceeds inward from the surface of the aluminum layer32, and then, as shown inFIG.10C, a portion of the aluminum layer32is nitridated, whereby an aluminum nitride layer33is formed. Thereafter, by alternately repeating the deposition of the aluminum layer32and the nitridation treatment, the conductive layer34is formed.

The manufacturing method, operation, and effect of the embodiment other than the above are the same as those of the first embodiment described above.

Next, a third embodiment will be described.

The resistive random access memory device according to the embodiment is a ReRAM.

FIG.11is a cross-sectional view illustrating a pillar of the resistive random access memory device according to the embodiment.

As shown inFIG.11, a pillar16of the resistive random access memory device according to the embodiment is different from the pillar16(seeFIG.2) of the resistive random access memory device according to the first embodiment described above in that a resistance change layer35is provided in place of the variable resistance layer25and the metal layer26. The resistance change layer35is formed from, for example, a metal oxide such as hafnium oxide, titanium oxide, or zinc oxide, or a carbon or chalcogenide material.

Next, a method of manufacturing a resistive random access memory device according to the embodiment will be described.

The method of manufacturing a resistive random access memory device according to the embodiment is different from the method of manufacturing a resistive random access memory device according to the first embodiment described above in that in place of forming the variable resistance layer25and the metal layer26, the resistance change layer35is formed on the lower electrode24.

Next, an operation of the resistive random access memory device according to the embodiment will be described.

When a set voltage Vset is applied to the pillar16of the resistive random access memory device shown inFIG.11, for example, oxygen vacancies are generated in the resistance change layer35formed from a metal oxide. Due to the generation of oxygen vacancies, a filament is formed and the resistance change layer35changes from a high-resistance state to a low-resistance state.

The configuration, manufacturing method, operation, and effect of the embodiment other than the above are the same as those of the first embodiment described above.

Next, a fourth embodiment will be described.

FIG.12is a cross-sectional view illustrating a pillar of the resistive random access memory device according to the embodiment.

In the resistive random access memory device according to the embodiment, a conductive layer composed of the stacked film (Al/AlN) described in the above second embodiment is provided for the ReRAM described in the above third embodiment.

More specifically, the overall structure of the resistive random access memory device according to the embodiment is a cross-point structure as shown inFIG.1, and the configuration of each pillar16is such that a resistance change layer35composed of a metal oxide, a conductive layer34, etc., are provided as shown inFIG.12. Further, as shown inFIG.9, the conductive layer34is formed by alternately stacking an aluminum layer32and an aluminum nitride layer33on each other.

The configuration, manufacturing method, operation, and effect of the embodiment other than the above are the same as those of the third embodiment described above.

In the above-described first embodiment, a case where as the materials to be alternately stacked on each other in the conductive layer22, tantalum nitride and silicon are used is shown, however, the materials are not limited thereto. In place of tantalum nitride, a material including either of a metal element and nitrogen may be used, or a material including both of a metal element and nitrogen may be used.

The formation may be performed by using, for example, a material including one or more metal selected from the group consisting of titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium in place of silicon, or the formation may be performed by using, for example, a material including a nitride or an oxide of one or more metal selected from the group consisting of silicon, titanium, tantalum, zirconium, aluminum, hafnium, molybdenum, tungsten, and vanadium in place of tantalum nitride.

In the above-described respective embodiments, a case where the concentration profile of tantalum along the vertical direction in the conductive layer22periodically fluctuates is shown, however, the concentration profile is not limited thereto, and a part of the concentration profile may periodically fluctuate, or the entire concentration profile may randomly fluctuate.

In the above-described respective embodiments, a case where the word line WL and the bit line BL are parallel to the silicon substrate11plane is described, however, the word line WL and the bit line BL are not limited thereto, and the word line WL and the bit line BL may be, for example, perpendicular to the silicon substrate11plane.

In the above-described respective embodiments, a CBRAM and a ReRAM are described by way of example, however, it is a matter of course that the device may be an element having an operating principle other than these, and the device may be, for example, a PCRAM (phase change memory), a molecular memory, or the like.

According to the embodiments described above, a resistive random access memory device provided with a conductive layer having a high resistivity and also having substantially linear current-voltage characteristics, and a method of manufacturing the same can be provided.