Array substrate and manufacturing method thereof, display panel

The present invention provides an array substrate and a display panel. The array substrate includes: an underlay; a source electrode and drain electrode disposed on underlay; a light shielding portion disposed on underlay; an active layer correspondingly disposed on the source electrode, the drain electrode, and the light shielding portion. The active layer includes a channel region, and the light shielding portion is disposed to correspond to the channel region. The present invention reduces processes and lowers cost by disposing the source electrode, the drain electrode, and the light shielding portion in a same layer such that the source electrode, the drain electrode, and the light shielding portion are simultaneously formed with a same material by a same process.

FIELD OF INVENTION

The present invention relates to a field of display technologies, especially to an array substrate and a manufacturing method thereof and a display panel.

BACKGROUND OF INVENTION

Mini/micro light emitting diode (LED) display technologies have entered an accelerated development stage in past two years and can be used in small and medium-sized display device applications. Compared to organic light emitting diode (OLED) screens, mini/micro LED displays can show better performance in terms of cost, contrast, high brightness and thin and light appearance. In the mini/micro LED display technologies, thin film transistor (TFT) backplate technologies are key technologies, but the technologies have complicated processes and high cost, which disadvantages mass production of mini/micro LED display panels.

With reference toFIG.1, a conventional array substrate usually disposes a light shielding portion1under an active layer2to shield external light emitted to the active layer2. The active layer2and a gate electrode3are separated by a gate electrode insulation layer4, and an interlayer dielectric layer5is usually deposited on the active layer2and the gate electrode3by a chemical vapor deposition (CVD) process. A source electrode/drain electrode6is manufactured on the interlayer dielectric layer5, and the source electrode/drain electrode6is electrically connected to the active layer2through a via hole in the interlayer dielectric layer5. Manufacturing processes of the conventional array substrate require multiple photomasks, for example, at least six photomask processes including a patterning process for the light shielding portion, a patterning process for the active layer, a patterning process for the gate electrode insulation layer, a patterning process for the gate electrode, a patterning process for the interlayer dielectric layer, and a patterning process for the source electrode/drain electrode, which makes the manufacturing processes of the array substrate complicated and have high costs.

SUMMARY OF INVENTION

Technical Issue

The present invention provides an array substrate and manufacturing method thereof, display panel that can solve a technical issue that a conventional TFT backplate manufacturing process is complicated and results in high costs.

Technical Solution

To solve the above issue, technical solutions provided by the present invention are as follows: The present invention embodiment provides an array substrate comprising:an underlay;a source electrode disposed on the underlay;a drain electrode disposed on the underlay;a light shielding portion disposed on the underlay; andan active layer disposed correspondingly on the source electrode, the drain electrode, and the light shielding portion, wherein the active layer comprises a channel region;wherein the light shielding portion corresponds to the channel region, the source electrode, the drain electrode, and the light shielding portion are disposed in a same layer, and a material of the source electrode and the drain electrode is same as a material of the light shielding portion.

Optionally, in some embodiments of the present invention, the active layer further comprises a non-channel region located on two sides of the channel region, and the source electrode and the drain electrode contact the non-channel region.

Optionally, in some embodiments of the present invention, the array substrate further comprises a top gate, the top gate is located on the active layer, and the top gate is disposed to correspond to the channel region of the active layer.

Optionally, in some embodiments of the present invention, the light shielding portion is disposed at an interval from the source electrode and is disposed at an interval from the drain electrode, and the light shielding portion is disposed opposite rightly to the top gate; or, the light shielding portion is connected to at least one of the source electrode and the drain electrode.

Optionally, in some embodiments of the present invention, the light shielding portion comprises a first portion connected to the source electrode and a second portion connected to the drain electrode, and the first portion and the second portion are spaced at an interval.

Optionally, in some embodiments of the present invention, an orthographic projection of the light shielding portion on the underlay covers an orthographic projection of a corresponding portion of the channel region of the active layer on the underlay.

Optionally, in some embodiments of the present invention, the top gate is electrically connected to the light shielding portion through a via hole.

Optionally, in some embodiments of the present invention, the array substrate further comprises:a buffer layer disposed between the light shielding portion and the active layer;a gate electrode insulation layer corresponding to the channel region and disposed between the active layer and the top gate; anda first passivation layer disposed on the top gate;wherein the top gate is electrically connected to the light shielding portion through a conductive layer disposed spaced at an interval from the active layer, the conductive layer comprises a first lead wire and a second lead wire; the first lead wire and the light shielding portion are disposed in a same layer and are electrically connected to each other; the second lead wire is located on the first passivation layer, an end of the second lead wire is electrically connected to the top gate through a first via hole extending through the first passivation layer, and another end of the second lead wire is electrically connected to the first lead wire through a second via hole extending through the first passivation layer and the buffer layer.

Optionally, in some embodiments of the present invention, the top gate and/or the light shielding portion, the source electrode, the drain electrode, and the active layer constitute a thin film transistor, the array substrate comprises a driver thin film transistor and a switch thin film transistor, wherein the driver thin film transistor and the switch thin film transistor are top gate structures; or, the driver thin film transistor and the switch thin film transistor are bottom gate structures; or, the driver thin film transistor and the switch thin film transistor are dual gate structures; or, the driver thin film transistor is a dual gate structure, and the switch thin film transistor is a top gate or a bottom gate structure.

The present invention embodiment also provides a display panel comprising an array substrate and a light emitting diode (LED), wherein the array substrate comprises:an underlay;a source electrode disposed on the underlay;a drain electrode disposed on the underlay;a light shielding portion disposed on the underlay; andan active layer disposed correspondingly on the source electrode, the drain electrode, and the light shielding portion, wherein the active layer comprises a channel region;wherein the light shielding portion corresponds to the channel region, the source electrode, the drain electrode, and the light shielding portion are disposed in a same layer, and a material of the source electrode and the drain electrode is same as a material of the light shielding portion.

Optionally, in some embodiments of the present invention, the active layer further comprises a non-channel region located on two sides of the channel region, and the source electrode and the drain electrode contact the non-channel region.

Optionally, in some embodiments of the present invention, the array substrate further comprises top gate, the top gate is located on the active layer, and the top gate is disposed to correspond to the channel region of the active layer.

Optionally, in some embodiments of the present invention, the light shielding portion is disposed at an interval from the source electrode and is disposed at an interval from the drain electrode, and the light shielding portion is disposed opposite rightly to the top gate; or, the light shielding portion is connected to at least one of the source electrode and the drain electrode.

Optionally, in some embodiments of the present invention, the light shielding portion comprises a first portion connected to the source electrode and a second portion connected to the drain electrode, and the first portion and the second portion are spaced at an interval.

Optionally, in some embodiments of the present invention, an orthographic projection of the light shielding portion on the underlay covers an orthographic projection of a corresponding portion of the channel region of the active layer on the underlay.

Optionally, in some embodiments of the present invention, the top gate is electrically connected to the light shielding portion through a via hole.

Optionally, in some embodiments of the present invention, the array substrate further comprises:a buffer layer disposed between the light shielding portion and the active layer;a gate electrode insulation layer corresponding to the channel region and disposed between the active layer and the top gate; anda first passivation layer disposed on the top gate;wherein the top gate is electrically connected to the light shielding portion through a conductive layer disposed at an interval from the active layer, the conductive layer comprises a first lead wire and a second lead wire; the first lead wire and the light shielding portion are disposed in a same layer and are electrically connected to each other; the second lead wire is located on the first passivation layer, an end of the second lead wire is electrically connected to the top gate through a first via hole extending through the first passivation layer, and another end of the second lead wire is electrically connected to the first lead wire through a second via hole extending through the first passivation layer and the buffer layer.

Optionally, in some embodiments of the present invention, the top gate and/or the light shielding portion, the source electrode, the drain electrode, and the active layer constitute a thin film transistor, the array substrate comprises a driver thin film transistor and a switch thin film transistor, wherein the driver thin film transistor and the switch thin film transistor are top gate structures; or, the driver thin film transistor and the switch thin film transistor are bottom gate structures; or, the driver thin film transistor and the switch thin film transistor are dual gate structures; or, the driver thin film transistor is a dual gate structure, and the switch thin film transistor is a top gate or a bottom gate structure.

The present invention embodiment also provides an array substrate manufacturing method, the manufacturing method comprises steps as follows:a step S11forming a first metal layer on an underlay, and patterning the first metal layer to form a light shielding portion, a source electrode, and a drain electrode;a step S12, forming a buffer layer on the first metal layer, and patterning the buffer layer to form source and drain electrode contact holes defined through the buffer layer and corresponding to the source electrode and the drain electrode; anda step S13forming an active layer on the buffer layer, and forming a channel region of the active layer and a non-channel region on two sides of the channel region;wherein the non-channel region of the active layer is connected to the source electrode and the drain electrode through the source and drain electrode contact holes, and the light shielding portion corresponds to the channel region.

Optionally, in some embodiments of the present invention, the manufacturing method further comprises a step as follow:a step S14forming a gate electrode insulation layer and a top gate laminated on the active layer, wherein the gate electrode insulation layer and the top gate corresponds to the channel region located in the active layer.

Advantages

Advantages of the present invention is as follows: The array substrate, the manufacturing method thereof, and the display panel provided by the present invention, dispose a source electrode, a drain electrode, and a light shielding portion in a same layer, and the source electrode and the drain electrode use the same material as that of the light shielding portion such that during manufacturing the array substrate, the source electrode, the drain electrode, and the light shielding portion can be simultaneously formed by the same process. Compared to the conventional structure employing two photomask processes for forming the light shielding portion and source and the drain electrode respectively, the present invention can reduce processes and lower costs.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The technical solution in the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are merely some embodiments of the present application instead of all embodiments. According to the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative effort shall fall within the protection scope of the present application. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the used orientation terminologies such as “upper” and “lower”, when are not specified to the contrary explanation, usually refer to the upper and lower states of the device in actual use or working conditions, specifically according to the direction of the figures in the drawings. Furthermore, “inner” and “outer” refer to the outline of the device.

To solve a technical issue that a conventional array substrate has complicated processes and high cost, the present invention embodiment provides an array substrate and a display panel. With reference toFIGS.2to17, the array substrate of the present invention comprises: an underlay101; a source electrode102disposed on the underlay101; a drain electrode103disposed on the underlay101; a light shielding portion104disposed on the underlay101; an active layer106disposed correspondingly on the source electrode102, the drain electrode103, and the light shielding portion104, wherein the active layer106comprises a channel region1061. The light shielding portion104is disposed to correspond to the channel region1061. The source electrode102, the drain electrode103, and the light shielding portion104are disposed in a same layer, and a material of the source electrode102and the drain electrode103is same as a material of the light shielding portion104.

It can be understood that, description “disposed in a same layer” here can be that the source electrode102, the drain electrode103, and the light shielding portion104are disposed at intervals in a same layer, and can be that the light shielding portion104is connected to one of the source electrode102and the drain electrode103and the three are disposed in a same layer.

The present invention simultaneously forms the source electrode102, the drain electrode103, and the light shielding portion104by using a same material and a same photomask process, and can omit one photomask process for individually manufacturing the source and the drain electrode compared to a conventional array substrate such that cost can be lowered and processes can be reduced.

Furthermore, the active layer106comprises a channel region1061and a non-channel region1062located on two sides of the channel region1061, and the source electrode102and the drain electrode103contact the non-channel region1062respectively. Because the source electrode102and the drain electrode103of the present invention are disposed in a same layer with the light shielding portion104, and a bottom portion of the active layer106contacts top portions of the source electrode102and the drain electrode103, a manufacturing process for an interlayer dielectric layer is omitted. InFIG.1, the interlayer dielectric layer5is usually manufactured by a chemical vapor deposition (CVD) process, and a process temperature would negatively affect the active layer2and the gate electrode3. Especially, when the active layer2is an oxide semiconductor material, a high temperature of the CVD process would affect crystallization capability of the oxide semiconductor. The present invention requires no interlayer dielectric layer, and therefore facilitates improvement of temperature stability of a device.

The array substrate of the present invention can be an array substrate with a bottom gate structure, can be an array substrate with a top gate structure, can also be an array substrate with a dual gate structure (i.e., a bottom gate and a top gate are included), or can also be a combination of any of the three structures.

With specific reference to an embodiment as follows, it should be explained that an order of descriptions in following embodiments is not to limit the preferred order of the embodiments.

First Embodiment

With reference toFIGS.2to4, the present embodiment takes an array substrate of a top gate structure as an example for explanation. The array substrate comprises: an underlay101, wherein the underlay101can be a glass underlay, or can also be a flexible underlay; a source electrode102, a drain electrode103, and a light shielding portion104disposed on the underlay101in a same layer; a buffer layer105disposed on the source electrode102, the drain electrode103, and the light shielding portion104; an active layer106disposed on the buffer layer105, wherein the active layer comprises a channel region1061and a non-channel region1062located on two sides of the channel region1061, and the source electrode102and the drain electrode103contact the non-channel region1062of the active layer106through via holes in the buffer layer105respectively; a gate electrode insulation layer107corresponding to the channel region1061and disposed on the active layer106; a top gate108corresponding to the channel region1061and disposed on the gate electrode insulation layer107; and a first passivation layer109disposed on the active layer106and the top gate108.

The light shielding portion104is located under the active layer106and is configured to shield external light emitted from the underlay101to the channel region1061of the active layer106. Furthermore, an orthographic projection of the light shielding portion104on the underlay101covers an orthographic projection of a corresponding portion of the channel region1061of the active layer106on the underlay101. With reference toFIG.2, the light shielding portion104is disposed at an interval from the source electrode102and is disposed at an interval from the drain electrode103. The light shielding portion104is located between the source electrode102and the drain electrode103, and the three are made of a same material. Therefore, the light shielding portion104, the source electrode102, and the drain electrode103cooperatively shield the external light emitted from the underlay101to the active layer106.

With reference toFIG.3, the light shielding portion104is connected to the source electrode102, namely, the light shielding portion104and the source electrode102commonly share a same film layer. In other words, a portion of the source electrode102can extend toward a side of the channel region1061as the light shielding portion104such that the source electrode102and the light shielding portion104can commonly share a same film layer. A size and a shape of the light shielding portion104can be set according to actual demands to shield the active layer106as much as possible.

Of course, in other embodiment, the light shielding portion104can be connected to the drain electrode103, and a connection way is similar to a connection way of the above light shielding portion104connected to the source electrode102and is not described repeatedly here.

With reference toFIG.4, the light shielding portion (1041,1042) comprises a first portion1041connected to the source electrode102, and comprises a second portion1042connected to the drain electrode103. The first portion1041and the second portion1042are spaced at an interval. In other words, a portion of the source electrode102extends toward the channel region1061as the first portion1041of the light shielding portion, a portion of the drain electrode103extends toward a side of the channel region1061as the second portion1042of the light shielding portion. In other words, the light shielding portion (1041,1042) can be shared with the source electrode102and the drain electrode103. At this time, the light shielding portion (1041,1042), the source electrode102, and the drain electrode103commonly shield the external light emitted from the underlay101to the active layer106.

The top gate108, the source electrode102, the drain electrode103, and the active layer106constitute a thin film transistor, the thin film transistor can be a driver thin film transistor or a switch thin film transistor. The array substrate of the present embodiment can comprise a driver thin film transistor and a switch thin film transistor. Both the driver thin film transistor and the switch thin film transistor are top gate structures.

Compared to the conventional array substrate, the present embodiment can omit a photomask process individually for manufacturing the source and drain electrode, and omit a process individually for manufacturing the interlayer dielectric layer such that processes can be reduced to lower cost.

Second Embodiment

With reference toFIG.5, the present embodiment takes an array substrate of a bottom gate structure as an example for explanation. The array substrate comprises: an underlay101; a source electrode102, a drain electrode103, and light shielding portion104disposed on the underlay101in a same layer, wherein the light shielding portion104is located between the source electrode102and the drain electrode103, a material of the light shielding portion104and the source electrode102is same as a material of the drain electrode103, and are all conductive and light shielding materials; a buffer layer105disposed on the source electrode102, the drain electrode103, and the light shielding portion104; an active layer106disposed on the buffer layer105, wherein the active layer comprises a channel region1061and a non-channel region1062located on two sides of the channel region1061, the source electrode102and the drain electrode103contact the non-channel region1062of the active layer106through via holes in the buffer layer105respectively, and the light shielding portion104right faces the channel region1061; and a first passivation layer109disposed on the active layer106.

The light shielding portion104is disposed at an interval from the source electrode102and is disposed at an interval from the drain electrode103. An orthographic projection of the light shielding portion104on the underlay101covers an orthographic projection of a corresponding portion of the channel region1061of the active layer106on the underlay101. The light shielding portion104can serve as a bottom gate of the thin film transistor, namely, the light shielding portion104can be shared with the bottom gate. Because the light shielding portion104, the source electrode102, and the drain electrode103have the same material, the light shielding portion (bottom gate)104, the source electrode102, and the drain electrode103can commonly shield external light emitted from the underlay101to the active layer106.

The light shielding portion (bottom gate)104, the source electrode102, the drain electrode103, and the active layer106constitute the thin film transistor, and the thin film transistor is a switch thin film transistor or a driver thin film transistor. The array substrate of the present embodiment can comprise the driver thin film transistor and the switch thin film transistor. Both the driver thin film transistor and the switch thin film transistor are bottom gate structures.

In the present embodiment, because the light shielding portion (bottom gate)104, the source electrode102, and the drain electrode103are simultaneously formed by the same material, processes can be simplified and cost can be lowered.

Third Embodiment

With reference toFIGS.6and7, the present embodiment takes an array substrate of a dual gate structure as an example for explanation. A difference of the present embodiment from the above second embodiment is as follows:

The array substrate of the present embodiment further comprises: a gate electrode insulation layer107corresponding to a channel region1061and disposed on an active layer106; and a top gate108corresponding to the channel region1061and disposed on the gate electrode insulation layer107. The first passivation layer109of the present embodiment is disposed on the active layer106and the top gate108. The top gate108is electrically connected to the light shielding portion104through a via hole. Specifically with reference toFIG.7, the top gate108is electrically connected to the light shielding portion104through a conductive layer, and the conductive layer comprises a first lead wire111and a second lead wire112. The first lead wire111and the light shielding portion104are disposed in a same layer and are electrically connected to each other. The second lead wire112is located above the first passivation layer109. An end of the second lead wire112is electrically connected to the top gate108through a first via hole extending through the first passivation layer109. Another end of the second lead wire112is electrically connected to the first lead wire111through a second via hole extending through the first passivation layer109and the buffer layer105.

Optionally, the first lead wire111can use a material the same as a material of the light shielding portion104, the source electrode102, and the drain electrode103, and can be simultaneously formed in a same process.

Optionally, the light shielding portion104and the first lead wire111can be formed integrally.

The light shielding portion104, the source electrode102, the drain electrode103, the active layer106, and the top gate108constitute a dual gate thin film transistor, and the dual gate thin film transistor is a switch thin film transistor or a driver thin film transistor. The array substrate of the present embodiment can comprise the driver thin film transistor and the switch thin film transistor. The driver thin film transistor and the switch thin film transistor are dual gate structures.

Other structures of the array substrate of the present embodiment are same as/similar to the structures of the array substrate of the above second embodiment, and will not be described repeatedly here.

In the present embodiment, because the thin film transistor is the dual gate structure, compared to the thin film transistors of a single gate structure of the first and second embodiments, current driving capability of the thin film transistor of the present embodiment is improved drastically. On one hand, it is because a width of an effective channel of the dual gate thin film transistor is greater. On another hand, because carriers in the dual gate thin film transistor suffer smaller interface scattering, mobility of the carriers is greater.

Fourth Embodiment

With reference toFIGS.2to6, the array substrate of the present embodiment comprises a driver thin film transistor and a switch thin film transistor, the driver thin film transistor is a dual gate structure and is configured to provide a greater driving current. The switch thin film transistor is a top gate or bottom gate structure. The thin film transistor of the dual gate structure can refer to the descriptions of the above third embodiment. The thin film transistor of the top gate structure can refer to the descriptions of the above first embodiment. The thin film transistor of the bottom gate structure can refer to the descriptions of the above second embodiment, and will not be described repeatedly here. Optionally, a material of the active layer106of the driver thin film transistor and/or a material of the active layer106of the switch thin film transistor is one of indium gallium zinc oxide, indium gallium zinc tin oxide, and indium gallium tin oxide.

Optionally, the driver thin film transistor is a metal oxide thin film transistor, the switch thin film transistor is a low-temperature polycrystalline silicon thin film transistor.

In the conventional mini/micro LED display technology, current required by an LED chip is higher, and total current of the display panel is generally3A to8A. Accordingly, voltage on the metal wires is also higher, which causes voltage power consumption of the metal wires of the display panel to increase. Also, to fulfill large current required by the LED chip in the conventional technology, VDD/VSS metal wire usually employs a design of dual layer metal wires. On one hand, the dual layer metal wires increase a number of photomasks for the array substrate, and on another hand, an increasing number of the metal wire layers raises a risk of a short circuit.

In the present embodiment, in one aspect, the active layer using the above metal oxide material can have a higher mobility to be able to lower the voltage power consumption of the metal wires. In another aspect, the driver thin film transistor employs a dual gate structure and can provide the LED chip with large current. Therefore, the VDD/VSS metal wires of the present embodiment can only adopt a design of single layer metal wires, which can further reduce the number of the photomasks to prevent the risk of the short circuit.

Fifth Embodiment

The present invention also provides a display panel, the display panel comprises the array substrate and the LED diode as above. The LED diode is a mini LED or a micro LED. Here, only the array substrate comprising the driver thin film transistor of the dual gate structure and the switch thin film transistor of the top gate structure is taken as an example for explanation.

With reference toFIG.8specifically, the display panel comprises: an underlay101; a source electrode102, a drain electrode103, and a light shielding portion104disposed on the underlay101in a same player, wherein the light shielding portion104is located between the source electrode102and the drain electrode103of a driver thin film transistor T1; a buffer layer105disposed on the source electrode102, drain electrode103, and light shielding portion104; an active layer106disposed on the buffer layer105at intervals, wherein the active layer106comprises a channel region1061and a non-channel region1062located on two sides of the channel region1061, the source electrode102and the drain electrode103contact the non-channel region1062of the active layer106through via holes of the buffer layer105respectively; a gate electrode insulation layer107corresponding to the channel region1061and disposed on the active layer106; a top gate108corresponding to the channel region1061and disposed on the gate electrode insulation layer107; and a first passivation layer109disposed on the active layer106and the top gate108.

The top gate108and the light shielding portion104of the driver thin film transistor T1are electrically connected to each other through a via hole. With specific reference toFIG.7, the top gate108and the light shielding portion104are electrically connected to each other through a conductive layer, and the conductive layer comprises a first lead wire111and a second lead wire112. The first lead wire111and the light shielding portion104are disposed in a same layer and are electrically connected to each other. The second lead wire112is located on the first passivation layer109, an end of the second lead wire112is electrically connected to the top gate108through a first via hole extending through the first passivation layer109, and another end of the second lead wire112is electrically connected to the first lead wire111through a second via hole extending through the first passivation layer109and the buffer layer105. The light shielding portion104of the driver thin film transistor T1can also serve as a bottom gate to control an electron channel in a lower surface of the active layer106. The top gate108controls an electron channel in an upper surface of the active layer106. The light shielding portion104and the top gate108are bridged to commonly control switching on and off of the driver thin film transistor T1.

The display panel further comprises: an electrode layer113corresponding to a pixel aperture region and disposed on the first passivation layer109, wherein the electrode layer113contacts the non-channel region1062of the active layer106of the driver thin film transistor T1through a third via hole extending through the first passivation layer109; a soldering pad114corresponding to the electrode layer113and disposed on the electrode layer113; a second passivation layer115disposed on the second lead wire112; a black matrix116disposed on the second passivation layer115, wherein the black matrix116and the second passivation layer115expose the soldering pad114and the electrode layer113in the pixel aperture region; an LED diode117is disposed in the pixel aperture region and is bonded to the electrode layer113through the soldering pad114.

The LED diode117comprises a red LED diode, a green LED diode, and a blue LED diode.

A design of the black matrix116can lower an influence of the thin film transistor to diffusion light of the LED.

In the present embodiment, the light shielding portion104, the source electrode102, and the drain electrode103has a same material that is conductive and light-shielding.

In the present embodiment, a design of the light shielding portion of the driver thin film transistor T1is same as or similar to a design of the light shielding portion in the above second embodiment. Namely, the light shielding portion104can be disposed at an interval from the source electrode102and at an interval from the drain electrode103. The light shielding portion104, source electrode102, and drain electrode103can commonly shield external light emitted from the underlay101to the active layer106. Alternatively, the light shielding portion104is connected to at least one of the source electrode102and the drain electrode103. At least one of the source electrode102and the drain electrode103serves as a light shielding portion. Please specifically refer to the above second embodiment andFIG.6, which will not be described repeated here.

In the present embodiment, a design of the light shielding portion104corresponding to a switch thin film transistor T2is same as or similar to a design of the light shielding portion104in the above first embodiment. Namely, the light shielding portion104is disposed at an interval from the source electrode102and at an interval from the drain electrode103, and the light shielding portion104, the source electrode102, and the drain electrode103commonly shield the external light emitted from the underlay101to the active layer106. Alternatively, the light shielding portion104is connected to at least one of the source electrode102and the drain electrode103. At least one of the source electrode102and the drain electrode103serves as a light shielding portion. Please specifically refer to the above first embodiment andFIGS.2to4, which will not be described repeated here.

In the present embodiment, because the source electrode102, the drain electrode103, and the light shielding portion104are in a same layer with a same material, and are formed by a same process, the present embodiment can omit two photomasks for individually manufacturing the source and drain electrode and the bottom gate compared to the conventional array substrate, and can further reduce processes and lower cost. In the meantime, the present embodiment requires no interlayer dielectric layer of a CVD process. Therefore, light irradiation of a device and stability of the temperature are improved drastically. Moreover, the driver thin film transistor of the present embodiment utilizes a dual gate structure, which can supply the LED diode with large current. Therefore, VDD/VSS metal wires of the display panel of the present embodiment only need to employ metal wires of a single layer, which can decrease a number of the photomasks to prevent a risk of a short circuit.

With reference toFIGS.9to17, the present invention also provides a display panel manufacturing method, the display panel manufacturing method comprises an array substrate manufacturing method, wherein the array substrate manufacturing method comprises steps as follows:

A step S11comprises forming a first metal layer on an underlay101, and patterning the first metal layer to form a light shielding portion104, a source electrode102, and a drain electrode103.

A material of the first metal layer is a light-shielding conductive material.

A step S12comprises forming on a buffer layer105on the first metal layer, and patterning the buffer layer105to form a source and drain electrode contact hole118extending through the buffer layer105and corresponding to the source electrode102and the drain electrode103.

A step S13comprises forming an active layer106on the buffer layer105, and forming a channel region1061of the active layer106and a non-channel region1062located on two sides of the channel region1061.

The non-channel region1062of the active layer106is connected to the source electrode102and the drain electrode103through the source and drain electrode contact hole118, and the light shielding portion104corresponds to the channel region1061.

In the present embodiment, the light shielding portion104can prevent external light from being emitted from a rear of the underlay101to the channel region1061of the active layer106, and the light shielding portion104can also serve as a bottom gate. Namely, the light shielding portion104, the source electrode102, the drain electrode103, and the active layer106form a thin film transistor of the bottom gate structure. The light shielding portion (bottom gate)104, the source electrode102, and drain electrode103are formed simultaneously to solve a technical issue that a conventional light shielding layer and a source and drain electrode are formed by different processes and result in complicated processes and high cost.

Of course, the light shielding portion104can only be used for light shielding. In an embodiment, the manufacturing method further comprises step as follows:

A step S14comprises forming a gate electrode insulation layer107and a top gate108laminated on the active layer106. The gate electrode insulation layer107and the top gate108are correspondingly located in the channel region1061of the active layer106.

In the present embodiment, the light shielding portion104can prevent external light from being emitted from the rear of the underlay101to the channel region1061of the active layer106. The source electrode102, the drain electrode103, the active layer106, and the top gate108form a thin film transistor of the top gate structure.

In an embodiment, the array substrate manufacturing method comprises steps as follows:

A step S1, as shown inFIG.9, comprises forming a first metal layer on an underlay101, and patterning the first metal layer to form a light shielding portion104, a source electrode102, a drain electrode103, and a first lead wire111.

The underlay101can be a glass substrate, but is not limited to be a glass substrate. The first metal layer can be Mo, a lamination layer of Mo/Cu, or a lamination layer of MoTi/Cu, and a thickness of the first metal layer is 5000 Å-8000 Å. A method for manufacturing the first metal layer can be a physical vapor deposition process, and can use H2O2series liquid medicine as an etchant to etch the first metal layer.

A step S2, as shown inFIG.10, comprises forming a buffer layer105on the first metal layer, and patterning the buffer layer105to form a source and drain electrode contact hole118extending through the buffer layer105.

A material of the buffer layer105can be SiOxor a lamination layer of SiNx/SiOx, and employs a chemical vapor deposition process, and is processed by a high temperature annealing process for 2-3 hours at a temperature of 300° C.-400° C., and then is patterned to form a source and drain electrode contact hole.

A step S3, as shown inFIG.11, comprises forming an active layer106on the buffer layer105.

A material of the active layer106is one of indium gallium zinc oxide, indium gallium zinc tin oxide, and indium gallium tin oxide.

A step S4, as shown inFIG.12, comprises forming a gate electrode insulation layer107and a top gate108laminated on the active layer106. The gate electrode insulation layer107and the top gate108are disposed to correspond to the channel region1061of the active layer106.

Specifically, a gate electrode insulation layer and a second metal layer are sequentially deposited on the active layer106, the second metal layer is patterned to formed a top gate108, and the gate electrode insulation layer107is patterned by a top gate self-alignment process, and then the active layer106is processed by plasma to form a channel region1061and a non-channel region1062of the thin film transistor. The non-channel region1062is electrically connected to the source electrode102and the drain electrode103through the source and drain electrode contact hole118.

A material of the gate electrode insulation layer107can be SiOx, a lamination layer of SiOxand SiNx, or a lamination layer of SiOx, SiNx, and Al2O3, and a thickness of the gate electrode insulation layer107is 2000 Å-5000 Å. A material of the top gate108can be Mo, a lamination layer of Mo/Cu, or a lamination layer of MoTi/Cu, and thickness of the top gate108is 5000 Å-8000 Å.

In the present embodiment, the light shielding portion104not only has a light shielding function, but also can serve as a bottom gate. The light shielding portion104, the source electrode102, the drain electrode103, the active layer106, and the top gate108form the thin film transistor of the dual gate structure.

Furthermore, the display panel manufacturing method further comprises steps as follows:

A step S5, as shown inFIG.13, comprises forming a first passivation layer109on the top gate108, and patterning the first passivation layer109to form a first via hole119corresponding to the top gate108, a second via hole120corresponding to the first lead wire111, and a third via hole121corresponding to the pixel aperture region.

A material of the first passivation layer109can be SiOxor a lamination layer of SiOx/SiNx.

A step S6, as shown inFIG.14, comprises forming an electrode layer113on the first passivation layer109. The electrode layer113corresponds to the pixel aperture region and contacts the non-channel region1062of the active layer106through the third via hole.

A step S7, as shown inFIG.15, comprises forming a soldering pad114on the electrode layer113, and simultaneously forming a second lead wire112on the first passivation layer109, wherein an end of the second lead wire112is electrically connected to the top gate108through the first via hole, and another end of the second lead wire112is electrically connected to the first lead wire111through the second via hole.

The soldering pad114and the second lead wire112employ a same material and are simultaneously formed in a same process, and the same material can be an electrode including Cu, or Cu/Mo.

A step S8, as shown inFIG.16, comprises forming a second passivation layer115and a black matrix116laminated on first passivation layer109, wherein the black matrix116and the second passivation layer115expose the soldering pad114and the electrode layer113in the pixel aperture region.

During patterning the second passivation layer115and the black matrix116, the patterned black matrix116serves as a photomask to complete patterning the second passivation layer115.

A step S9, as shown inFIG.17, comprises bonding the LED diode117to the soldering pad114.

In the present embodiment, because the source electrode102, the drain electrode103, a bottom gate110, and the light shielding portion104are in a same layer with a same material, and are formed by a same process, the present embodiment can omit two photomasks for individually manufacturing the source and drain electrode and the bottom gate compared to the conventional array substrate and can further reduce processes and lower cost. In the meantime, the present embodiment requires no interlayer dielectric layer of a CVD process. Therefore, light irradiation of a device and stability of the temperature are improved drastically. Moreover, the driver thin film transistor of the present embodiment utilizes a dual gate structure, which can supply the LED diode with large current. Therefore, VDD/VSS metal wires of the display panel of the present embodiment only need to employ metal wires of a single layer, which can decrease a number of the photomasks to prevent a risk of a short circuit.

The present invention has been described as above. In the specification, the specific examples are used to explain the principle and embodiment of the present application. The above description of the embodiments is only used to help understand the method of the present application and its spiritual idea. Meanwhile, for those skilled in the art, according to the present the idea of invention, changes will be made in specific embodiment and application. In summary, the contents of this specification should not be construed as limiting the present application.