Hinge design for enhanced optical performance for a micro-mirror device

An apparatus for use with a digital micro-mirror includes a hinge disposed outwardly from a substrate. The hinge is capable of at least partially supporting a micro-mirror disposed outwardly from the hinge. The micro-mirror is capable of being selectively transitioned between an on-state position and an off-state position. In one particular embodiment, the hinge comprises a substantially flat profile for at least a portion of the hinge disposed between a first hinge post of the hinge and a mid-point of the hinge. The apparatus also includes a plurality of process control voids formed within a conductive layer disposed inwardly from the hinge. In one particular embodiment, the substantially flat profile is at least partially created from the plurality of process control voids.

TECHNICAL FIELD OF THE INVENTION

This invention relates in general to optical processing devices and, in particular, to an apparatus having an improved hinge design and method of manufacturing the same.

BACKGROUND

Digital micro-mirror devices (DMD) are capable of being used in optical communication and/or projection display systems. DMDs involve an array of micro-mirrors that selectively communicate at least a portion of an optical signal or light beam. DMDs selectively communicate an optical signal or light beam by pivoting between active “on” and “off” states. To permit the micro-mirrors to pivot, each micro-mirror is attached to a hinge that is mounted on one or more support posts.

Conventional DMDs typically formed a sloped and/or sagged hinge profile in an attempt to minimize the effect of “popped” hinges that formed after final annealing of the DMD. Although the sloped and/or sagged profile attempted to minimize the effect of “popped” hinges, in some cases, the sloped and/or sagged profile is still susceptible to developing the “popped” hinges. In addition, the conventional hinges having the sloped and/or sagged profile typically exhibit poor dim line artifact.

SUMMARY

In one embodiment, an apparatus for use with a digital micro-mirror comprises a hinge disposed outwardly from a substrate. The hinge is capable of at least partially supporting a micro-mirror disposed outwardly from the hinge. The micro-mirror is capable of being selectively transitioned between an on-state position and an off-state position. In one particular embodiment, the hinge comprises a substantially flat profile for at least a portion of the hinge disposed between a first hinge post of the hinge and a mid-point of the hinge. The apparatus also comprises a plurality of process control voids formed within a conductive layer disposed inwardly from the hinge. In one particular embodiment, the substantially flat profile is at least partially created from the plurality of process control voids.

In a method embodiment, a method of forming an apparatus for use with a digital micro-mirror comprises forming a plurality of process control voids within a conductive layer disposed outwardly from a substrate. The plurality of process control voids define an intermediate profile of a hinge. The method also comprises forming a hinge layer disposed outwardly from the conductive layer. The hinge layer having the intermediate profile. In one particular embodiment, the intermediate profile comprises an approximately sinusoidal profile having a height of a mid-point that is substantially similar to a height of a first hinge post of the apparatus.

Depending on the specific features implemented, particular embodiments of the present invention may exhibit some, none, or all of the following technical advantages. Various embodiments may be capable of minimizing the likelihood of popped hinges after annealing the device. Some embodiments may be capable of providing an improved dim line performance.

Other technical advantages will be readily apparent to one skilled in the art from the following figures, description and claims. Moreover, while specific advantages have been enumerated, various embodiments may include all, some or none of the enumerated advantages.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1is a perspective view of one embodiment of a portion of a digital micro-mirror device (DMD)100. In this example, DMD100comprises a micro electro-mechanical switching (MEMS) device that includes an array of hundreds of thousands of tilting micro-mirrors104. In this example, each micro-mirror104is approximately 13.7 square microns in size and has an approximately one micron gap between adjacent micro-mirrors. In some examples, each micro-mirror can be less than thirteen square microns in size. In other examples, each micro-mirror can be approximately seventeen square microns in size. In addition, each micro-mirror104may tilt up to plus or minus ten degrees creating an active “on” state condition or an active “off” state condition. In other examples, each micro-mirror104may tilt plus or minus twelve degrees for the active “on” state or “off” state.

In this example, each micro-mirror104transitions between its active “on” and “off” states to selectively communicate at least a portion of an optical signal or light beam. To permit micro-mirrors104to tilt, each micro-mirror104is attached to one or more hinges116mounted on hinge posts108, and spaced by means of an air gap over a complementary metal-oxide semiconductor (CMOS) substrate102. In this example, micro-mirrors104tilt in the positive or negative direction until yoke106contacts conductive conduits110. Although this example includes yoke106, other examples may eliminate yoke106. In those examples, micro-mirrors104tilt in the positive or negative direction until micro-mirrors104contact a mirror stop (not explicitly shown).

In this particular example, electrodes112and conductive conduits110are formed within a conductive layer120disposed outwardly from an oxide layer103. Conductive layer120can comprise, for example, an aluminum alloy or other suitable conductive material. Oxide layer103operates to insolate CMOS substrate102from electrodes112and conductive conduits110.

Conductive layer120receives a bias voltage that at least partially contributes to the creation of the electrostatic forces developed between electrodes112, micro-mirrors104, and/or yoke106. In this particular example, the bias voltage comprises a steady-state voltage. That is, the bias voltage applied to conductive layer120remains substantially constant while DMD100is in operation. In this example, the bias voltage comprises approximately twenty-six volts. Although this example uses a bias voltage of twenty-six volts, other bias voltages may be used without departing from the scope of the present disclosure.

In this particular example, CMOS substrate102comprises the control circuitry associated with DMD100. The control circuitry can comprise any hardware, software, firmware, or combination thereof capable of at least partially contributing to the creation of the electrostatic forces between electrodes112, micro-mirrors104, and/or yoke106. The control circuitry associated with CMOS substrate102functions to selectively transition micro-mirrors104between “on” state and “off” state based at least in part on data received from a processor (not explicitly shown).

In this particular example, micro-mirror104ais positioned in the active “on” state condition, while micro-mirror104bis positioned in the active “off” state condition. The control circuitry transitions micro-mirrors104between “on” and “off” states by selectively applying a control voltage to at least one of the electrodes112associated with a particular micro-mirror104. For example, to transition micro-mirror104bto the active “on” state condition, the control circuitry removes the control voltage from electrode112band applies the control voltage to electrode112a.In this example, the control voltage comprises approximately three volts. Although this example uses a control voltage of approximately three volts, other control voltages may be used without departing from the scope of the present disclosure.

Conventional DMDs typically include a hinge that has a sloped profile between the hinge posts and a mid-point associated with the hinge. That is, at least a portion of the hinge disposed between the hinge post and the mid-point has a height that is substantially different than a height of the hinge post. In most cases, at least a portion of the hinge disposed between the hinge post and the mid-point has a height that is different than a height of the hinge post by at least six-hundred Angstroms.

In addition, conventional DMDs typically form a hinge by depositing a hinge material in a sagged profile between the hinge posts associated with the hinge. That is, a hinge profile that has a mid-point substantially below a plane defined by a height associated with each hinge post. The terms “above” and/or “below” refer to the proximity of a component in relation to another component of the DMD and are not intended to limit the orientation of the device and/or components. In most cases, the sagged profile associated with the hinge of the conventional device is greater than two-hundred fifty Angstroms.

Conventional DMDs typically formed the sloped and/or sagged profile in an attempt to minimize the effect of “popped” hinges that formed after final annealing of the DMD. A “popped” hinge refers to a hinge having at least a portion of a hinge profile that is disposed substantially above a plane defined by a height associated with each hinge post. Although the sloped and/or sagged profile attempted to minimize the effect of “popped” hinges, in some cases, the sloped and/or sagged profile is still susceptible to developing the “popped” hinges. In addition, the conventional hinges having the sloped and/or sagged profile typically exhibit poor dim line performance.

Unlike conventional DMDs, DMD100comprises a hinge116that has a substantially flat hinge profile between a hinge post108and a mid-point (not explicitly shown) of hinge116. That is, the portion of hinge116disposed between hinge post108and the mid-point has a height that is substantially similar to a height of hinge post108. In most cases, the portion of hinge116disposed between hinge post108and the mid-point has a height that is within two-hundred fifty Angstroms of a height of hinge post108. In other cases, the portion of hinge116disposed between hinge post108and the mid-point has a height that is within one-hundred fifty Angstroms of a height of hinge post108.

To obtain the substantially flat hinge profile, hinge116is manufactured by forming an approximately sinusoidal hinge profile between hinge posts108(as illustrated inFIGS. 3A-3D). The term “approximately sinusoidal profile” refers to a hinge profile that has a mid-point at approximately the same height as a plane defined by each hinge post and is not intended to limit the shape of the hinge profile to a sinusoid. In some cases, the mid-point can be within twenty Angstroms above or below the plane, and in other cases, the mid-point can be no more than thirty Angstroms below the plane; these are all instances of an approximately sinusoidal hinge. In particular embodiments, the approximately sinusoidal hinge profile comprises approximately two or more periods or repetitions in shape.

One aspect of this disclosure recognizes that by forming hinge116having a substantially flat hinge profile device manufactures can improve the yield by reducing the number of “popped” hinges. In addition, providing hinge116with a substantially flat hinge profile typically reduces the jitter and/or bouncing that occurs as a result of micro-mirrors104transitioning between “on” and “off” states. Reducing the jitter and/or bouncing tends to result in a reduced dim line artifact of DMD100.

FIG. 2is a cut-away view of a portion of a micro-mirror assembly150associated with a DMD. InFIG. 2, elements that are substantially similar in structure and function to elements inFIG. 1have the same reference numerals. In this example, assembly150includes hinge posts108, conductive conduits110, and electrodes112.

Micro-mirror assembly also includes a plurality of process control voids122formed within conductive layer120. As used in this document, the terms “patterned trench” and “process control voids” are used inter-changeably. Process control voids122operate to selectively displace a spacer layer material formed between hinge posts108. Selectively displacing the spacer layer material formed between hinge posts108can advantageously allow device manufacturers to control a profile and/or shape of a spacer layer during its formation. Controlling the profile and/or shape of the spacer layer allows a device manufacturer to control a shape and/or profile of a subsequently formed hinge associated with assembly150. In some cases, controlling the profile and/or shape of the spacer layer can allow a device manufacturer to form an approximately sinusoidal hinge profile. Forming the pattern of process control voids122may be effected through any of a variety of processes, such as, by removing a portion of conductive layer120.

FIGS. 3A through 3Eare cross sectional views illustrating one example of a method of forming a portion of a digital micro-mirror device (DMD)300. DMD300may be used as a basis for forming any of a variety of optical devices, such as a spatial light modulator, a gain equalizer, an optical filter, or combination of these or other optical devices. Particular examples and dimensions specified throughout this document are intended for example purposes only, and are not intended to limit the scope of the present disclosure. Moreover, the illustration inFIGS. 3A through 3Eare not intended to be to scale.

FIG. 3Ashows a cross sectional view of DMD300after formation of a inter-level oxide layer304disposed outwardly from a substrate302and after formation of a conductive layer306outwardly from inter-level oxide layer (ILO)304. Although substrate302and inter-level oxide layer304are shown as being formed without interstitial layers between them, such interstitial layers could alternatively be formed without departing from the scope of the present disclosure. Substrate302may comprise any suitable material used in semiconductor chip fabrication, such as silicon, poly-silicon, indium phosphide, germanium, or gallium arsenide. In various embodiments, substrate302can include complementary metal-oxide semiconductor (CMOS) circuitry capable of controlling DMD300after its formation.

Inter-level oxide layer304may comprise, for example, oxide, silicon dioxide, or oxi-nitride. Forming inter-level oxide layer304may be effected through any of a variety of processes. In one non-limiting example, inter-level oxide layer304can be formed by growing an oxide. Using a grown oxide as inter-level oxide layer304can advantageously provide a mechanism for removing surface irregularities in substrate302. For example, as oxide is grown on the surface of substrate302, a portion of substrate302is consumed, including at least some of the surface irregularities.

Conductive layer306may comprise, for example, an aluminum alloy or other conductive material. Where conductive layer306comprises an aluminum alloy, the aluminum alloy may comprise, for example, aluminum, silicon, polysilicon, tungsten, nitride, and/or a combination of these or other conductive materials. In this example, conductive layer306comprises silicon-based aluminum that has light absorbing and/or anti-reflective properties. In other embodiments, conductive layer306may include an anti-reflective material disposed outwardly from the silicon-based aluminum layer. Forming conductive layer306may be effected, for example, by depositing silicon-based aluminum. Although inter-level oxide layer304and conductive layer306are shown as being formed without interstitial layers between them, such interstitial layers could alternatively be formed without departing from the scope of the present disclosure.

At some point, the conductive conduits, electrodes, and process control voids (not explicitly shown) associated with DMD300are formed within conductive layer306. Forming the conductive conduits, electrodes, and process control voids may be effected through any of a variety of processes. For example, the conductive conduits, electrodes, and process control voids may be formed by removing a portion of conductive layer306. In other embodiments, the process control voids can be formed by removing a portion of inter-layer oxide layer304prior to the formation of conductive layer306. In this particular embodiment, the conductive conduits, electrodes, and process control voids are formed by patterning and etching conductive layer306using photo resist mask and etch techniques. In some cases, the conductive conduits, electrodes, and process control voids can be formed substantially simultaneously. In other embodiments, the conductive conduits, electrodes, and process control voids can be formed subsequent to one another. In various embodiments, the conductive conduits, electrodes, and process control voids formed in conductive layer306can be substantially similar in structure and function as conductive conduits110, electrodes112, and process control voids122ofFIGS. 1 and 2A.

Forming the process control voids in conductive layer306can allow a DMD device manufacturer to control the profile and/or shape of a spacer layer during its formation (to be formed later). Controlling the as formed shape of the spacer layer allows a device manufacturer to control as formed shape of a subsequently formed hinge associated with DMD300.

FIG. 3Bshows a cross sectional view of DMD300after formation of a spacer layer308outwardly from inter-level oxide layer304and after formation of hinge post cavities309aand309bwithin spacer layer308. Although spacer layer308and conductive layer306are shown as being formed without interstitial layers between them, such interstitial layers could alternatively be formed without departing from the scope of the present disclosure. Spacer layer308may comprise, for example, a photoresist material or other selectively etchable material. That is, spacer layer308can be removed using an etchant that does not significantly affect other materials.

Forming spacer layer308may be effected through any of a variety of processes. For example, spacer layer308can be formed by depositing or spinning-on a photo-resist material. In the illustrated embodiment, spacer layer308comprises a material that is selectively etchable from conductive layer306and/or inter-level oxide layer304. That is, each of spacer layer308and conductive layer306and/or inter-level oxide layer304can be removed using an etchant that does not significantly affect the other.

In this particular example, spacer layer308is formed after formation of the process control voids within conductive layer306. Forming the process control voids before forming spacer layer308allows device manufacturers to control a profile307of spacer layer308. Profile307depends at least in part on the location and pattern of the process control voids. Controlling profile307can advantageously allow DMD device manufacturers to form a desired hinge profile. In some cases, profile307can allow device manufacturers to form an approximately sinusoidal hinge profile.

Forming hinge post cavities309aand309bmay be effected through any of a variety of processes. For example, hinge post cavities309aand309bcan be formed by patterning and etching spacer layer308.

FIG. 3Cshows a cross sectional view of DMD300after formation of a hinge layer310outward from spacer layer308. Although spacer layer308and hinge layer310are shown as being formed without interstitial layers between them, such interstitial could alternatively be formed without departing from the scope of the present disclosure. Forming hinge layer310may be effected through any of a variety of processes. For example, hinge layer310can be formed by depositing an aluminum alloy. Hinge layer310may comprise, for example, aluminum, silicon, polysilicon, tungsten, nitride, and/or a combination of these or other materials. In this example, hinge layer310comprises an aluminum alloy that has reflective properties. In other examples, hinge layer310could comprise an aluminum compound that has light absorbing and/or anti-reflective properties. Forming hinge layer310may be effected, for example, by depositing an aluminum alloy.

In some cases, controlling the pattern associated with the process control voids, the deposition rate, and/or other process parameters can allow a DMD device manufacturer to control hinge profile311. In this example, the formation of hinge layer310results in at least a portion of hinge layer310having a hinge profile311. Although hinge profile311approximates a sinusoid in this example, any desired shape may be formed without departing from the scope of the present disclosure.

FIG. 3Dshows a cross sectional view of DMD300after removal of spacer layer308. Spacer layer308can be removed by any of a number of processes, such as, for example, by performing an isotropic plasma etch. Although this example illustrates the removal of spacer layer308after depositing hinge layer310without any additional process steps, such additional process steps could alternatively be performed without departing from the scope of the present disclosure.

In this particular embodiment, hinge profile311comprises an approximately sinusoidal hinge profile having approximately two periods or repetitions in shape. That is, hinge profile311has a mid-point height (XM) at approximately the same height as a hinge post height (XH) associated with hinge posts312. In some cases, the mid-point height (XM) can be within twenty Angstroms above or below the hinge post height (XH). In other cases, the mid-point height (XM) can be no more than thirty Angstroms below the hinge post height (XH).

FIG. 3Eshows a cross sectional view of DMD300after forming a substantially flat hinge314. Although this example illustrates forming substantially flat hinge314after removal of spacer layer308without any additional process steps, such additional process steps could alternatively be performed without departing from the scope of the present disclosure.

Substantially flat hinge314can be formed by any of a number of processes, such as, for example, by subjecting hinge layer310to an anneal process. In various embodiments, the anneal process can be performed at a specified temperature for a desired period. The anneal temperature being based at least in part on an anneal time necessary to activate the device. In various embodiments, the anneal process can comprise subjecting hinge layer310to a temperature of between one-hundred degrees Celsius and two-hundred degree Celsius for nine to fifteen hours.

One aspect of this disclosure recognizes that forming an approximately sinusoidal hinge profile311can allow DMD device manufacturers to form a hinge having a substantially flat profile. In this particular embodiment, hinge314comprises a substantially flat profile after the anneal process. That is, the portion of hinge314disposed between hinge post312and a mid-point314chas a height that is substantially similar to a height associated with hinge post312. In this particular embodiment, the portion of hinge314disposed between first end314aand mid-point314chas a height (Xc) that is within two-hundred fifty Angstroms of a height (Xa) associated first end314a.In some embodiments, the portion of hinge314disposed between second end314band mid-point314chas a height (Xc) that is within two-hundred fifty Angstroms of a height (Xc) associated with second end314b.In other embodiments, the portion of hinge314disposed between first end314aand mid-point314chas a height (Xc) that is within one-hundred fifty Angstroms of a height (Xa) associated first end314a.

One aspect of this disclosure recognizes that by forming hinge314having a substantially flat hinge profile device manufactures can improve the yield by reducing the number of “popped” micro-mirrors. In addition, providing hinge314with a substantially flat hinge profile typically reduces the jitter and/or bouncing that occurs as a result of the micro-mirrors transitioning between “on” and “off” states. Reducing the jitter and/or bouncing tends to result in an improved dim line performance of DMD300.

FIG. 4Ais a cross sectional view of a hinge profile452before subjecting a hinge to an anneal process. In this example, hinge profile452comprises an approximately sinusoidal hinge profile between hinge posts108ofFIG. 2. That is, hinge profile452has a mid-point height454at approximately the same height as a plane456defined by a height associated with each hinge post108. In this particular embodiment, mid-point height454is approximately two nanometers (e.g., twenty Angstroms) above plane456. In other cases, mid-point height454can be no more than three nanometers (e.g., thirty Angstroms) below plane456.

In this particular example, hinge profile452approximates a sinusoid having approximately two periods or repetitions in shape. Hinge profile452includes valleys458aand458bdefining a depth associated with hinge profile452. Valleys458can comprise, for example, a depth of no more than fourteen nanometers.

FIG. 4Bis a cross sectional view of a hinge profile462before subjecting a hinge to an anneal process. In this example, hinge profile462comprises an approximately sinusoidal hinge profile between hinge posts108ofFIG. 2. That is, hinge profile462has a mid-point height464at approximately the same height as a plane466defined by a height associated with each hinge post108. In this particular embodiment, mid-point height464is approximately one nanometer (e.g., ten Angstroms) above plane466. In other cases, mid-point height464can be no more than three nanometers (e.g., thirty Angstroms) below plane466.

In this particular example, hinge profile462comprises approximately two periods or repetitions in shape. Hinge profile462includes valleys468aand468bdefining a depth associated with hinge profile462. Valleys468can comprise, for example, a depth of no more than ten nanometers.

FIG. 4Cis a cross sectional view of a hinge profile472before subjecting a hinge to an anneal process. In this example, hinge profile472comprises an approximately sinusoidal hinge profile between hinge posts108ofFIG. 2. That is, hinge profile472has a mid-point height474at approximately the same height as a plane476defined by a height associated with each hinge post108. In this particular embodiment, mid-point height474is approximately 1.5 nanometers (e.g., fifteen Angstroms) above plane476. In other cases, mid-point height474can be no more than three nanometers (e.g., thirty Angstroms) below plane476.

In this particular example, hinge profile472comprises approximately two periods or repetitions in shape. Hinge profile472includes valleys478aand478bdefining a depth associated with hinge profile472. Valleys478can comprise, for example, a depth of no more than sixteen nanometers.

Although the present invention has been described in several embodiments, a myriad of changes, variations, alterations, transformations, and modifications may be suggested to one skilled in the art, and it is intended that the present invention encompass such changes, variations, alterations, transformations, and modifications as falling within the spirit and scope of the appended claims.