Fan-out wafer level package structure

A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

BACKGROUND

Generally, one of the driving factors in the design of modern electronics is the amount of computing power and storage that can be shoehorned into a given space. The well-known Moore's law states that the number of transistors on a given device will roughly double every eighteen months. In order to compress more processing power into ever smaller packages, transistor sizes have been reduced to the point where the ability to further shrink transistor sizes has been limited by the physical properties of the materials and processes. Designers have attempted to overcome the limits of transistor size by packaging ever larger subsystems into one chip (systems on chip), or by reducing the distance between chips, and subsequent interconnect distance.

One method used to reduce the distance between various chips forming a system is to stack chips, with electrical interconnects running vertically. This can involve multiple substrate layers, with chips on the upper and lower surfaces of a substrate. One method for applying chips to the upper and lower side of a substrate is called “flip-chip” packaging, where a substrate has conductive vias disposed through the substrate to provide an electrical connection between the upper and lower surfaces.

Additionally, a package-on-package structure may be mounted on another carrier, package, PCB, or the like, via a solder ball grid array (BGA), land grid array (LGA), or the like. In some instances, the separation of the individual interconnections in an array, or bond pitch, may not match the die within the package-on-page structure, or may require a different connection arrangement than within the package-on-package structure.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. For clarity non-essential reference numbers are left out of individual figures where possible.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Embodiments will be described with respect to a specific context, namely making and using fan-out structures useful in, for example, wafer level package assemblies. Other embodiments may also be applied, however, to other electrical components, including, but not limited to, mounting memory assemblies, displays, input assemblies, discrete components, power supplies or regulators or any other components.

FIG. 10is a flow diagram illustrating steps in an embodiment of a method1000for fabricating a fan-out wafer level package structure.FIG. 10is described in conjunction withFIGS. 1-7, which illustrate intermediate steps in the method1000for forming the fan-out wafer level packaging structure.

Initially referring toFIG. 10, a first step in an embodiment of a method1000for fabricating a fan-out wafer level package is shown in block1002. A carrier112and optionally, an adhesive layer110, may be provided as shown inFIG. 1. The carrier112may be configured to provide structural rigidity or a base for deposition of subsequent non-rigid layers. In one embodiment, the carrier112may be glass, but may alternatively be a wafer, semiconductor, metal, synthetic or other material having a suitable topography and structural rigidity.

The adhesive layer110may, in some embodiments, may be applied to the carrier112. In one embodiment, the adhesive layer110may be adhesive tape or die attachment film (DAF), or alternatively, may be a glue or epoxy applied to the carrier112via a spin-on process, or the like. In some embodiments, the adhesive layer110may be used to separate the carrier112from the fan-out assembly (SeeFIG. 8, element800) and associated devices or layers in subsequent steps.

A die102may be applied in block1004, and as shown inFIG. 1. The application of the die102is not limited to application of a single die102, as the presented disclosure may include more than one die102. In some embodiments, the die102may have one or more mounts114, which may for example, be contacts, pins, mounting pads, lands, or the like, for providing electrical connectivity to the circuit (not shown) within the die102. The die102may be attached or otherwise mounted to the carrier112by way of the adhesive layer110or another suitable attachment method. The die102may be attached to the carrier112at the top surface102aof the die102with the mounts114facing away from the carrier112.

One or more vias106may be attached or otherwise created in block1006, and as shown inFIG. 1. In one embodiment, the vias106may be formed within a via chip104which may be attached to the carrier112by way of the adhesive layer110, or another suitable attachment means. In one embodiment, the via chip104may be placed by a pick-and-place apparatus. The via chip104may be comprised of one or more dielectric layers108and one or more vias106comprised of a substantially conductive material. In some embodiments, the vias106may be copper, or in other embodiments, the vias106may be aluminum, gold, palladium, silver, alloys of the same, or another conductive material. Additionally, the dielectric layers may be formed of material different than the molded substrate202, and may separate the vias104from the molded substrate202.

The via chips104may be formed prior to placement on the carrier112, or vias106may be formed in situ on the carrier. Via chips104, for example, may be formed as part of a larger structure. For example, multiple vias106or multiple via chips104may be formed in a single structure and then cut to a desired or predetermined size. For example, a dielectric may be etched or otherwise have via openings formed therein, and then the vias106may be formed by a deposition or plating process. Alternatively, the vias106may be milled, molded, deposited or formed with a dielectric108or molding compound prior to placement on the carrier112.

Additionally, while the illustrated embodiment depicts a single die102with two via chips104, one on each side of the die102, the number and disposition of the via chips104and die102is not limited to the illustrated embodiment. For example, multiple dies102may be disposed on the carrier112, with one via chip104, or with more than two via chips104arranged around the dies102.

A molding compound202amay be applied in block1008, to form the molded substrate202, as shown inFIG. 2. The molding compound202amay be applied to the carrier112, and may fill the area around the die102and via chip104, and filling any gaps around the die102mounts114and vias106. In one embodiment, the molded substrate202may be formed from a nonconductive material, such as an epoxy, a resin, a moldable polymer, or the like. The molding compound202amay be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In another embodiment the molding compound202amay be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the die102and via chip104. In an embodiment employing a UV or thermally cured molding compound202a, the molded substrate202may be formed in place using a mold, for example, bordering the perimeter of the molded area, such as a wafer or package. Optionally, a release film may be applied prior to applying the molding compound202a, permitting parting of a mold from the molded substrate202, or from the carrier112. A release film may be advantageous where the molding compound202ais applied to the carrier112without an adhesive or other barrier between the molding compound202aand carrier112.

The molded substrate202may be reduced in block1010, and as shown inFIG. 3. The molded substrate202may undergo, in some embodiments, a grinding step to remove excess material from the die102mounts114and vias106. In such an embodiment, the molded substrate202may be subjected to a chemical-mechanical polish, a purely mechanical polish, chemical etching, or another suitable reduction process. The resulting reduced molded substrate202may, in some embodiments, have a top surface202bat or below the top surfaces of the vias106and the die102mounts114. In some embodiments, first ends of the vias106and the die102mounts114may be substantially planar with a first side202bof the molded substrate202. Thus, the first ends of the vias106and the die102mounts114may be exposed at the polished or first side202bof the reduced molded substrate202so that electrical contacts may be formed on the vias106and die102mounts114. In some embodiments, the grinding may also reduce the height of the vias106or die102mounts114.

A first redistribution layer402(RDL) may be formed in block1012, as shown inFIG. 4. The molded substrate202may have a RDL402disposed on one side202bof the planarized or reduced surface. The RDL402may, in some embodiments, have one or more conductive lines406disposed in an intermetal dielectric (IMD)408, and in electrical contact with RDL contact pads404. The RDL402conductive lines406may further be in contact with one or more of the die102mounts114or one or more vias106. The conductive lines406may fan out from one or more of the die102mounts114such that the RDL contact pads404may have a larger bond pitch than the die102mounts114, and which may be suitable for a ball grid array or other package mounting system. In one embodiment, the RDL402may have conductive lines406configured to fan out and provide an electrical connection between the die102mounts114and RDL contact pads404. In some embodiments, the RDL402may also have conductive lines406that connect one or more vias106to the RDL contact pads404. In some embodiment, the conductive lines406may electrically connect, for example, a via106to another via106, to a die102mount114, or to another die102or device.

Package mounts502may be applied in block1014and as shown inFIG. 5, and the die102or circuit may then be tested. In one embodiment, the package mounts502may be applied to the RDL contact pads404as, for example, solder balls comprising a ball grid array. In another embodiment, the package mounts may be a land grid array (LGA), a pin array, or another suitable package attachment system.

The carrier112may be debonded and the vias106exposed in block1016.FIG. 6illustrates a package with the carrier112debonded. The carrier112may be removed to expose the adhesive layer110where used, or to expose the vias and molded substrate. In one embodiment, the adhesive layer110may be softened or otherwise weakened through heat, ultraviolet light, or a solvent, and the carrier112separated from the molded substrate202. In other embodiments, the carrier112may be removed through a grinding or polishing process.

FIG. 7illustrates a package according to an embodiment of the presented disclosure with the vias106exposed at the second side202cof the molded substrate202. The adhesive layer110may be removed mechanically, such as by grinding, chemical mechanical polishing, heating, or the like, or by other means, such as a solvent. In some embodiments, the adhesive layer110may be removed in the process of reducing or planarizing the second end of the vias106and second side202cof the molded substrate202. The adhesive layer110may also be removed as part of the process of removing the carrier112. Thus, the second ends of the vias may be substantially planar with the second side202cof the molded substrate202. Additionally, the top surface102aof the die102may be exposed through the second side of the molded substrate202. The planarizing process applied to the second side202cof the molded substrate202may also be used to bring the molded substrate202to a desired or predetermined thickness. For example, in one embodiment, the molded substrate202may be reduced to expose the top surface102aof the die102, resulting in a molded substrate having the about the same thickness as the height of the die102, including the die102mounts114.

A second structure802may be mounted in block1018.FIG. 8illustrates one embodiment of a fan-out wafer level package structure800fabricated according to the presented disclosure, with a secondary structure802or die mounted over a single die102. In one embodiment, the second structure802may be mounted at a height where the bottom surface of the second structure802is separated from the top surface102aof the die102. In one embodiment, the second structure802may have a second substrate804and one or more structure connectors808may be applied to connect the second structure802to the vias106. In one embodiment, the structure connectors808may be solder balls applied to lands on the bottom of the second structure802. In another embodiment, the structure connectors808may be solder paste, a conductive adhesive, or the like.

FIG. 9illustrates another embodiment of a second fan-out wafer level package structure900fabricated according to the presented disclosure. A second structure902may, in one embodiment, be for example, a die with a pin array, such as in a wide I/O DRAM Chip. In such an embodiment, a single via chip104may be disposed in the molded substrate202, with two or more dies102disposed at the molded substrate202so that the via chip104is disposed between at least two dies102.

Thus, in view of the foregoing, a method for forming a fan-out wafer level package structure may comprise applying an active device or die102over a carrier112, the die102having a plurality of mounts114, providing one or more vias106on the carrier112and forming a molded substrate202over the carrier112and around the vias106. The molded substrate202may be reduced on a first side202bthat is opposite the carrier112to expose vias106. In some embodiments, mounts114on the die102may also be exposed through the first side202bof the molded substrate202. The ends of the vias106and the mounts114of the die102exposed through the first side202bof the molded substrate202may be substantially planar with the first side202bof the molded substrate202. An adhesive layer110may optionally be disposed on the carrier112, and the die and vias attached to the carrier112by way of the adhesive layer110. Additionally, the molded substrate202may be formed on the adhesive layer110.

Via chips104having vias106, and optionally, one or more dielectric layers108separating the vias106may be used to provide the vias106on the carrier112or adhesive layer110. The via chips104may be formed separate and away from the carrier112and adhesive layer110and prior to placement of the one or more via chips104on the adhesive layer110. The dielectric layer108of the via chips104may separate the vias106from the molded substrate202, the dielectric layer108comprising a material different from the molded substrate202. In one embodiment, the molded substrate202may have least two via chips104, with the die102disposed between the via chips104. In another embodiment, the molded substrate202may have at least two dies102on the adhesive layer110and a via chip104disposed between the two dies102.

An RDL402having a plurality of RDL contact pads404and conductive lines406may be formed on first side202bof the molded substrate202. The RDL contact pads404may have a bond pitch greater than a bond pitch of the mounts114of the die102, and package mounts502may be disposed on the RDL contact pads404.

The carrier112may be debonded and the adhesive layer110removed. One or more vias106may be exposed through the second side of the molded substrate202opposite the first side202b. A second structure802may be mounted at the second side of the molded substrate202, the second structure802having at least one die102disposed thereon and in electrical communication with at least one via106. In one embodiment, a die102on the second structure802in electrical communication with at least one RDL contact pad404by way of at least a via106.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. It will be readily understood by those skilled in the art that many of the features and functions discussed above can be implemented using a variety of materials and orders to the processing steps. For example, dies and vias may be attached to the carrier by any suitable means sufficient to retain the structure in place for application of the molding compound202a. As another example, it will be readily understood by those skilled in the art that many of the steps for creating a fan-out wafer level structure may be performed in any advantageous order while remaining within the scope of the present disclosure.