SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer and the encapsulation structure. The encapsulation structure includes a core substrate having a cavity formed therein, at least one semiconductor chip in the cavity such that a front surface on which chip pads are formed faces the lower redistribution wiring layer, and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0048667, filed on Apr. 13, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a fan out panel level package (FOPLP) and a method of manufacturing the same.

2. Description of the Related Art

In manufacturing a fan out panel level package (FOPLP), a semiconductor chip may be disposed in a core substrate, a sealing member covering the semiconductor chip may be formed on the core substrate, a front redistribution wiring layer may be formed on the core substrate and a lower surface of the semiconductor chip, and a backside redistribution wiring layer may be formed on the sealing member. Since the front redistribution wiring layer and the backside redistribution wiring layer are sequentially formed after the semiconductor chip is attached, there is a problem in that the semiconductor chip must be discarded when a defect occurs in forming the front redistribution wiring layer or the backside redistribution wiring layer. In addition, since all manufacturing processes must be performed sequentially, there is a problem in that lead time is long.

SUMMARY

Example embodiments provide a semiconductor package having a structure capable of improving process yield and shortening lead time.

Example embodiments provide a method of manufacturing the semiconductor package.

According to example embodiments, a semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure; and an adhesive layer attaching the lower redistribution wiring layer to the encapsulation structure, wherein the encapsulation structure includes a core substrate having a cavity formed therein; at least one semiconductor chip in the cavity such that a front surface of the at least one semiconductor chip on which chip pads are formed faces the lower redistribution wiring layer; and an upper redistribution wiring layer covering an upper surface of the core substrate and having upper redistribution wiring layers that are electrically connected to conductive structures of the core substrate.

According to example embodiments, a semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; a core substrate disposed on the lower redistribution wiring layer, the core substrate having a first surface and a second surface opposite to the first surface, the core substrate having a cavity formed therein; at least one semiconductor chip in the cavity of the core substrate on the lower redistribution wiring layer such that a front surface of the at least one semiconductor chip on which chip pads are formed faces the lower redistribution wiring layer; an upper redistribution wiring layer covering the first surface of the core substrate and having upper redistribution wirings that are electrically connected to conductive structures of the core substrate; a plurality of conductive bumps disposed between the core substrate and the lower redistribution wiring layer and between the at least one semiconductor chip and the lower redistribution wiring layer; and an adhesive layer disposed between the core substrate and the lower redistribution wiring layer and between the at least one semiconductor chip and the lower redistribution wiring layer, the adhesive layer covering side surfaces of the plurality of conductive bumps.

According to example embodiments, a semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings; an encapsulation structure on the lower redistribution wiring layer, the encapsulation structure including a core substrate, at least one semiconductor chip, and an upper redistribution wiring layer, wherein the core substrate has a first surface and a second surface opposite to the first surface and has a cavity formed therein, the at least one semiconductor chip is in the cavity and a front surface of the at least one semiconductor chip on which chip pads are formed is exposed from the second surface of the core substrate, and the upper redistribution wiring layer covers the first surface of the core substrate and a portion of the at least one semiconductor chip and has upper redistribution wirings that are electrically connected to conductive structures of the core substrate; a plurality of conductive bumps between the lower redistribution wiring layer and the encapsulation structure and electrically connecting the chip pads to the lower redistribution wirings and electrically connecting the conductive structures to the lower redistribution wirings; and an adhesive layer attaching the lower redistribution wiring layer to the encapsulation structure.

According to example embodiments, a method of manufacturing a semiconductor package includes providing an encapsulation structure including a first wiring and a sealing layer, wherein a semiconductor chip including a chip pad is in a cavity formed in the encapsulation structure and covered by the sealing layer; forming a first conductive bump on the first wiring and a second conductive bump on the chip pad of the semiconductor chip; providing a lower redistribution wiring layer including a first upper bonding pad and a second upper bonding pad exposed on an upper surface of the lower redistribution wiring layer; forming an adhesive layer on the upper surface of the lower redistribution wiring layer; bonding the encapsulation structure to the lower redistribution wiring layer.

According to example embodiments, in a method of manufacturing a semiconductor package, a lower redistribution wiring layer having lower redistribution wirings is formed. A core substrate having a first surface and a second surface opposite to the first surface and having a cavity formed therein is provided. At least one semiconductor chip is disposed in the cavity such that a front surface of the at least one semiconductor chip on which chip pads are formed is exposed from the second surface of the core substrate. A sealing layer covering the first surface of the core substrate and exposing the front surface of the at least one semiconductor chip is formed. An upper insulating layer provided on the encapsulation layer and having upper redistribution wires electrically connected to the conductive structures of the core substrate is formed. A plurality of bumps are formed on the conductive structures of the core substrate and on the chip pads of the at least one semiconductor chip. An adhesive layer is formed on the lower redistribution wiring layer. The core substrate and the at least one semiconductor chip are stacked on the lower redistribution wiring layer via the plurality of bumps.

According to example embodiments, a semiconductor package as a fan out wafer level package may include a lower redistribution wiring layer, an encapsulation structure stacked on the lower redistribution wiring layer via conductive bumps, and an adhesive layer interposed between the lower redistribution wiring layer and the encapsulation structure. After the encapsulation structure including a core substrate, a semiconductor chip and an upper redistribution wiring layer is formed and the lower redistribution wiring layer is formed by a different process, the encapsulation structure may be stacked on the lower redistribution wiring layer.

Thus, defects of the lower redistribution wiring layer may be inspected in advance and the encapsulation structure may be stacked only on the lower redistribution wiring layer of a good product to minimize die loss, thereby improving process yield and shortening lead time.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.1is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments.FIG.2is an enlarged cross-sectional view illustrating portion ‘A’ inFIG.1.

Referring toFIGS.1and2, a semiconductor package10may include a lower redistribution wiring layer400, an encapsulation structure ES disposed on the lower redistribution wiring layer400, a plurality of conductive bumps302disposed between the lower redistribution wiring layer400and the encapsulation structure ES, and an adhesive layer310attaching the lower redistribution wiring layer400to the encapsulation structure ES. The encapsulation structure ES may include a core substrate100, at least one semiconductor chip200disposed in the core substrate100, and an upper redistribution wiring layer130disposed on an upper surface of the core substrate100. In addition, the semiconductor package10may further include external connection members500disposed on an outer surface of the lower redistribution wiring layer400.

In example embodiments, the semiconductor package10may include a core substrate100that surrounds the semiconductor chip200and serves as a support member for supporting a redistribution wiring layer in a fan-out region. The core substrate100may serve as a frame surrounding the semiconductor chip200. The core substrate100may include core connection wirings120as conductive connectors serving as electrical connection paths from the semiconductor chip200in the fan-out region outside an area where the semiconductor chip200is disposed. Accordingly, the semiconductor package10can be provided as a fan-out package. Additionally, the semiconductor package10may be provided as a unit package on which a second package is stacked.

Additionally, the semiconductor package10may be provided as a System In Package (SIP). For example, one or more semiconductor chips may be disposed on the lower redistribution wiring layer400. The semiconductor chips may include a logic chip including a logic circuit and/or a memory chip. The logic chip may be a controller that controls memory chips. The memory chip includes various types of memory circuits, such as DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM.

In example embodiments, the lower redistribution wiring layer400may have first redistribution wirings402as lower redistribution wirings. A semiconductor chip200electrically connected to the first redistribution wiring layer402may be disposed on the lower redistribution wiring layer400. The lower redistribution wiring layer400may be provided on a front surface202of the semiconductor chip200to serve as a front redistribution wiring layer. Accordingly, the lower redistribution wiring layer400may be a front redistribution wiring layer (FRDL) of the fan-out package.

In particular, the lower redistribution wiring layer400may include a plurality of lower insulating layers including first, second and third lower insulating layers410,420and430and first redistribution wirings402provided in the first, second and third lower insulating layers410,420, and430. The first redistribution wirings402may include first and second lower redistribution wirings422and432.

The first, second and third lower insulating layers410,420, and430may be formed of or include a polymer or a dielectric layer. For example, the first, second and third lower insulating layers may include a photosensitive insulating layer such as PID (photo imagable dielectric), an insulating film such as ABF (Ajinomoto Build-up Film), etc. In this embodiment, the first lower insulating layer410may include the insulating film such as ABF (Ajinomoto Build-up Film), and the second and third lower insulating layers420and430may include photosensitive insulating films such as PID. The first, second and third lower insulating layers410,420, and430may be formed by a vapor deposition process, a spin coating process, etc. The first redistribution wirings402may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The first redistribution wirings402may be formed by a plating process, an electroless plating process, a vapor deposition process, etc.

Lower bonding pads412may be provided on the first lower insulating layer410. The lower bonding pad412may be a bump pad. The bump pad may include a solder pad or a pillar pad. For example, the lower bonding pad may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

The first lower redistribution wirings422may be formed on the first lower insulating layer410. The first lower redistribution wiring422may be electrically connected to the lower bonding pad412through a first opening formed in the first lower insulating layer410.

The second lower insulating layer420may be formed on the first lower insulating layer410and may cover the first lower redistribution wirings422. The second lower redistribution wirings432may be formed on the second lower insulating layer420. The second lower redistribution wiring432may be electrically connected to the first lower redistribution wiring422through a second opening formed in the second lower insulating layer420.

The third lower insulating layer430may be formed on the second lower insulating layer420and may cover the second lower redistribution wirings432. Upper bonding pads442may be provided on the third lower insulating layer430. The upper bonding pads442may be respectively provided on the second lower redistribution wirings432. Via holes may be formed in the third lower insulating layer430to expose portions of the second lower redistribution wirings432. The upper bonding pad442may be electrically connected to the second lower redistribution wiring432through the via holes in the third lower insulating layer430.

The number and arrangement of the lower insulating layers and the lower redistribution wirings of the lower redistribution wiring layer are provided as examples, and it will be understood that the present inventive concept is not limited thereto.

In example embodiments, when viewed from a plan view, the lower redistribution wiring layer400may include a first region that overlaps the semiconductor chip200mounted on an upper surface of the lower redistribution wiring layer400and a second region surrounding the first region. The second region may be a fan-out region outside the area where the semiconductor chip200is disposed.

The upper bonding pads442may be exposed from the upper surface of the lower redistribution wiring layer100, that is, the third lower insulating layer430. The upper bonding pads442may include chip connection bonding pads443that are formed on uppermost first redistribution wirings, that is, the second lower redistribution wirings432located in the first region and conductive structure connection bonding pads444that are formed on the uppermost first redistribution wirings, that is, the second lower redistribution wirings432in the second region.

In example embodiments, the encapsulation structure ES may include the core substrate100, the at least one semiconductor chip200disposed in the core substrate100and the upper redistribution wiring layer130disposed on an upper surface of the core substrate100.

In particular, the core substrate100may have a first surface (upper surface)102and a second surface (lower surface)104opposite to the first surface102. The core substrate100may have at least one cavity106(see, e.g.,FIG.3) in a central portion thereof. The cavity106may extend from the first surface102to the second surface104of the core substrate100.

The core substrate100may include a plurality of stacked insulating layers110and112and core connection wirings120in the insulating layers. The plurality of core connection wirings120may be provided in a fan-out region outside the area where the semiconductor chip (die) is disposed and may be used for electrical connection with the mounted semiconductor chip. The core connection wiring120may be a vertical connection structure penetrating the core substrate100from the first surface102to the second surface104of the core substrate100.

For example, the core substrate100may include a first insulating layer110and a second insulating layer112stacked on the first insulating layer110. The core connection wiring120may include a first wiring122, a first contact123, a second wiring124, a second contact125and a third wiring126. The first wiring122may be provided on the second surface104of the core substrate100, that is, a lower surface of the first insulating layer110, and at least a portion of the first wiring122may be exposed from the second surface104. The third wiring126may be provided on the first surface102of the core substrate100, that is, an upper surface of the second insulating layer112, and at least a portion of the third wiring126may be exposed from the first surface102. The numbers and arrangements of the insulating layers and the core connection wirings of the core substrate100are provided as examples, and it will be understood that the present inventive concept is not limited thereto.

In example embodiments, the at least one semiconductor chip200may be disposed in the cavity106of the core substrate100. Two semiconductor chips200may be disposed in one cavity106. A sidewall of the semiconductor chip200may be spaced apart from an inner wall of the cavity106. Accordingly, a gap may be formed between the sidewall of the semiconductor chip200and the inner wall of the cavity106. Alternatively, the core substrate100may include two cavities, and two semiconductor chips200may be disposed in the two cavities respectively.

The semiconductor chip200may include a substrate and chip pads210on a front surface202of the substrate, that is, an active surface. The front surface202of the semiconductor chip200on which the chip pads210are formed may face the lower redistribution wiring layer400. Accordingly, the chip pads210may be exposed from the second surface104of the core substrate100. The front surface202of the semiconductor chip200may be positioned on the same plane as the second surface104of the core substrate100. A backside surface204opposite to the front surface202of the semiconductor chip200may be positioned higher than the first surface102of the core substrate100, but the inventive concept is not limited thereto. A thickness of the semiconductor chip200may be greater than a thickness of the core substrate100, but the inventive concept is not limited thereto. The thickness of the semiconductor chip200may be within a range of 60 μm to 150 μm, and the thickness of the core substrate100may be within a range of 50 μm to 140 μm.

Although only a few chip pads are illustrated in the drawings, the structures and arrangements of the chip pads are provided as examples, and it will be understood that the present inventive concept is not limited thereto. Additionally, although only two semiconductor chips are illustrated, the inventive concept is not limited thereto, and one or three or more semiconductor chips may be disposed in the core substrate100.

In example embodiments, the upper redistribution wiring layer130may include a sealing layer140and at least one upper insulating layer150. The upper redistribution wiring layer130may include second redistribution wirings142as upper redistribution wirings. The second redistribution wirings142may be provided on the backside surface204of the semiconductor chip200and the first surface102of the core substrate100to serve as upper redistribution wirings. Accordingly, the upper redistribution wiring layer130may be a backside redistribution wiring layer (BRDL) of the fan-out package.

In particular, the sealing layer140may be provided on the first surface102of the core substrate100to fill the cavity106and to cover the backside surface204of the semiconductor chip200. The sealing layer140includes a first sealing portion that covers the first surface102of the core substrate100, a second molding portion that covers the backside surface204of the semiconductor chip200, and a third molding portion that fills the gap between the side surface of semiconductor chip200and the inner wall of the cavity106. The sealing layer140may have openings that expose the third wirings126of the core connection wiring120.

For example, the sealing layer140may be formed of or include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material such as inorganic fillers. In particular, the sealing layer may include an insulating film such as ABF (Ajinomoto Build-up Film), a composite material such as FR-4, and a resin such as BT (Bismaleimide Triazine). In addition, the sealing layer may include a molding material such as EMC (Epoxy Molding Compound), a photosensitive insulating material such as PIE (Photo Imagable Encapsulant), etc. When the sealing layer140includes an insulating film such as ABF, the sealing layer140may be formed by a lamination process.

The upper redistribution wirings142may be provided on the sealing layer140and may directly contact the third wirings126through the openings formed in the sealing layer140. Accordingly, the upper redistribution wirings142may be electrically connected to the core connection wirings120respectively. The upper insulating layer150may be provided on the sealing layer140and may cover the upper redistribution wirings142.

For example, the upper redistribution wirings142may be formed of or include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The upper insulating layer150may include an insulating film such as ABF, which is the same as the sealing layer140.

The upper insulating layer150may have openings151that expose at least portions of the upper redistribution wirings142. A bonding pad may be provided on a portion of the upper redistribution wiring142exposed by the opening151. A passivation layer may be provided on the upper insulating layer150and may expose a portion of the bonding pad.

The number, arrangement, etc. of the upper insulating layer150and the upper redistribution wirings142of the upper redistribution wiring layer130are provided as examples, and it will be understood that the present inventive concept is not limited thereto.

The upper redistribution wirings142are illustrated as including the first redistribution wirings formed in one layer on the sealing layer140, but may not be limited thereto. For example, the upper redistribution wirings142may include first upper redistribution wirings and second upper redistribution wirings stacked in at least two layers. In this case, the first upper redistribution wiring may correspond to the upper redistribution wiring142and the second upper redistribution wiring may correspond to an uppermost redistribution wiring. Bonding pads may be formed on the second upper redistribution wirings by a subsequent process.

In example embodiments, the encapsulation structure ES including the core substrate100, the at least one semiconductor chip200and the upper redistribution wiring layer130may be stacked on the lower redistribution wiring layer400via conductive bumps302.

The conductive bumps302may be interposed between the encapsulation structure ES and the lower redistribution wiring layer400. The conductive bumps302may be interposed between the core substrate100and the lower redistribution wiring layer400and between the semiconductor chip200and the lower redistribution wiring layer400. The conductive bumps302may electrically connect the conductive structure120of the core substrate100to the lower redistribution wirings402of the lower redistribution wiring layer400. The conductive bumps302may electrically connect the chip pads210of the semiconductor chip200to the lower redistribution wirings402of the lower redistribution wiring layer400.

The encapsulation structure ES may be stacked on the lower redistribution wiring layer400such that the front surface202of the semiconductor chip200and the second surface104of the core substrate100face the lower redistribution wiring layer400.

In example embodiments, the encapsulation structure ES may be attached to the lower redistribution wiring layer400using an adhesive layer310. The adhesive layer310serving as a gap fill material layer may be filled between the encapsulation structure ES and the lower redistribution wiring layer400. The adhesive layer310may cover side surfaces of the conductive bumps302.

For example, the adhesive layer310may be formed of or include a non-conductive film (NCF). Bumps on the chip pads210of the semiconductor chip200and the first wirings122of the conductive structure120may be reflowed by thermal compression of a bonding apparatus to form the conductive bumps302and the encapsulation structure ES may be attached on the lower redistribution wiring layer400by the adhesive layer310.

As illustrated inFIG.2, the conductive bumps302may include first conductive bumps303and second conductive bumps304. The first conductive bumps303are formed on the chip pads210of the semiconductor chip200, and the second conductive bumps304may be formed on the first wirings122of the conductive structure120of the core substrate100.

The first conductive bump303may be disposed between the chip connection bonding pad443among the upper bonding pads422and the chip pad210of the semiconductor chip200. Accordingly, the chip pads210of the semiconductor chip200may be electrically connected to the first redistribution wirings402of the lower redistribution wiring layer400by the first conductive bumps303.

The second conductive bump304may be disposed between the conductive structure connecting pad444among the upper bonding pads422and the conductive structure120of the core substrate100. Accordingly, the conductive structures120of the core substrate100may be electrically connected to the first redistribution wirings402of the lower redistribution wiring layer400by the second conductive bumps304.

For example, as shown, e.g., inFIG.2, the conductive bump302may have a diameter D1within a range of 5 μm to 60 μm. A diameter D2of the upper bonding pad442may be the same as a diameter D1of the conductive bump302. Alternatively, the diameter D2of the upper bonding pad442may be larger or smaller than the diameter D1of the conductive bump302.

The third lower insulating layer430may include via holes that expose portions of the second lower redistribution wirings432, and the upper bonding pads442may be provided in the via holes of the third lower insulating layer430. The upper bonding pad442may have a pillar shape corresponding to the via hole.

In example embodiments, the external connection members500may be disposed on lower bonding pads412on the outer surface of the lower redistribution wiring layer400. For example, the external connection member500may include a solder ball. The solder ball may have a diameter of 300 μm to 500 μm. The semiconductor package10may be mounted on a module substrate via the solder balls to form a memory module.

As mentioned above, the semiconductor package10as a fan-out wafer level package may include the lower redistribution wiring layer400, the encapsulation structure ES stacked on the lower redistribution wiring layer400via the conductive bumps302, and the adhesive layer310interposed between the lower redistribution wiring layer400and the encapsulation structure ES. The encapsulation structure ES may include the core substrate100, the at least one semiconductor chip200disposed in the core substrate100, and the upper redistribution wiring layer130disposed on the upper surface of the core substrate100. The conductive structures120of the core substrate100and the chip pads210of the semiconductor chip200may be electrically connected to the lower redistribution wirings402of the lower redistribution wiring layer400by the conductive bumps302. The upper redistribution wirings142of the upper redistribution wiring layer130may be electrically connected to the conductive structures120of the core substrate100.

After the encapsulation structure ES including the core substrate100, the semiconductor chip200and the upper redistribution wiring layer130is formed, and the lower redistribution wiring layer400is formed in a different process, the encapsulation structure ES may be stacked on the lower redistribution wiring layer400via the conductive bumps302as a medium.

Thus, defects of the lower redistribution wiring layer400may be inspected in advance and the encapsulation structure ES may be stacked only on the lower redistribution wiring layer of a good product to minimize die loss, thereby improving process yield and shortening lead time.

Hereinafter, a method of manufacturing the semiconductor package ofFIG.1will be described.

FIGS.3to15are views illustrating a method of manufacturing a semiconductor package in accordance with example embodiments.FIG.3is a plan view illustrating a panel in which a plurality of core substrates is formed.FIGS.4to15are cross-sectional views taken along line I-I′ inFIG.3.

Referring toFIGS.3to5, first, a panel P on which a plurality of core substrates100is formed may be prepared, at least one semiconductor chip200may be placed in a cavity106of the core substrate100, and a sealing layer140(see, e.g.,FIG.5) may be formed to cover the semiconductor chip200.

In example embodiments, the core substrate100may be used as a base substrate as a support member for electrical connection on which the semiconductor chip200is arranged to form a semiconductor package having a fan-out panel level package configuration.

As illustrated inFIG.3, the panel P may include a frame region FR for the core substrate100and a scribe lane region surrounding the frame region FR, that is, a cutting region CR. As will be described below, the panel P may be cut along the cutting region CR dividing the frame regions FR from each other to be divided into individual core substrates100.

As illustrated inFIG.4, the core substrate100may have a first surface102and a second surface104opposite to the first surface102. The core substrate100may have a cavity106in a central portion thereof. The cavity106may have a planar area for accommodating at least one semiconductor chip200. Alternatively, the core substrate100may have a plurality of cavities in the central portion, and one or more semiconductor chips may be disposed in each of the plurality of cavities.

The core substrate100may include a plurality of stacked insulating layers110and112and core connection wirings120as conductive connection structures provided in the insulating layers. The plurality of core connection wirings120may be provided to penetrate the core substrate100from the first surface102to the second surface104of the core substrate100to serve as electrical connection passages, respectively. That is, the core connection wirings120may be provided in a fan-out area outside an area where the semiconductor chip (die) is disposed and may be used for electrical connection. For example, the core connection wiring120may include a first wiring122, a first contact123, a second wiring124, a second contact125and a third wiring126. Alternatively, the core connection wiring may include a through via penetrating the core substrate.

Then, after the panel P may be disposed on a barrier tape20, at least one semiconductor chip200may be disposed in the cavity106.

The second surface104of the core substrate100may be attached on the barrier tape20. For example, dies (chips) may be disposed in hundreds to thousands of cavities106of the panel P, respectively. As will be described below, a singulation process may be performed to cut the panel P along the cutting region CR, to complete individual fan-out panel level packages.

In this embodiment, two semiconductor chips200may be disposed in one cavity106. The two semiconductor chips200may be spaced apart from each other along a first direction (X direction).

The semiconductor chip200may include a substrate and chip pads210provided on a front surface202of the substrate, that is, an active surface. The semiconductor chip200may be disposed such that the front surface of the semiconductor chip200on which the chip pads210are formed faces the barrier tape20. The front surface202of the semiconductor chip200may be positioned on the same plane as the second surface104of the core substrate100. The semiconductor chip200may be disposed in the cavity106of the core substrate100. A sidewall of the semiconductor chip200may be spaced apart from an inner wall of the cavity106. Thus, a gap may be formed between the sidewall of the semiconductor chip200and the inner wall of the cavity106.

A thickness of the semiconductor chip200may be smaller than a thickness of the core substrate100. Accordingly, a backside surface204of the semiconductor chip200may be positioned lower than the first surface102of the core substrate100. Alternatively, the thickness of the semiconductor chip200may be equal to or greater than the thickness of the core substrate100. In this case, the backside surface204of the semiconductor chip200may be positioned on the same plane as or higher than the first surface102of the core substrate100.

As illustrated inFIG.5, after the core substrate100and the barrier tape20are disposed on a first carrier substrate C1, a sealing layer140may be formed on the first surface102of the core substrate100to cover the semiconductor chip200.

The sealing layer140may be formed to fill a gap between the sidewall of the semiconductor chip200and the inner wall of the cavity106. Accordingly, the backside surface204of the semiconductor chip200, the first surface102of the core substrate100and the inner wall of the cavity106may be covered by the sealing layer140.

For example, the sealing layer140may be formed of or include an insulating film such as ABF (Ajinomoto Build-up Film), an insulating material (thermosetting dielectric material) such as epoxy resin, a photosensitive insulating material such as photo imagable dielectric (PID), etc. When the sealing layer140includes the insulating film such as ABF, the sealing layer140may be formed by a lamination process.

Referring toFIGS.6and7, at least one upper insulating layer150having upper redistribution wirings142may be formed on the sealing layer140on the first surface102of the core substrate100and the backside surface204of the semiconductor chip200. The upper redistribution wirings142may be electrically connected to the core connection wirings120.

As illustrated inFIG.6, the sealing layer140on the first surface102of the core substrate100may be partially removed to form openings that expose the third wirings126of the core connection wirings120, and the upper redistribution wirings142may be formed on the sealing layer140. The upper redistribution wirings142may be electrically connected to the core connection wirings120through the openings.

As illustrated inFIG.7, after the upper insulating layer150is formed on the sealing layer140, the upper insulating layer may be partially removed to form openings151that expose the upper redistribution wirings142. The upper insulating layer may include an insulating film such as ABF that is the same as the sealing layer140.

The upper redistribution wirings142are illustrated as including the first redistribution wirings formed in one layer on the sealing layer140, but may not be limited thereto. For example, the upper redistribution wirings142may include first upper redistribution wirings and second upper redistribution wirings stacked in at least two layers. In this case, the first upper redistribution wiring may correspond to the upper redistribution wiring142and the second upper redistribution wiring may correspond to an uppermost redistribution wiring. Bonding pads may be formed on the second upper redistribution wirings by a following process. For example, the first and second upper redistribution wirings may be formed of or include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

In one embodiment, second upper redistribution wirings may be formed on the upper insulating layer to be electrically connected to the first upper redistribution wirings142through openings151, and a second upper insulating layer may be formed on the upper insulating layer to cover the second upper redistribution wirings. Then, the second upper insulating layer may be partially removed to form openings that expose the second upper redistribution wirings. In this case, the upper redistribution wirings may include the first upper redistribution wirings142and the second upper redistribution wirings stacked in two layers, and the second upper redistribution wirings may correspond to the uppermost redistribution wirings among the upper redistribution wirings.

Then, bonding pads may be formed on the upper redistribution wirings142. For example, the bonding pad may be formed on the upper redistribution wiring142exposed by the opening151and a passivation layer may be formed on the upper insulating layer150to expose a portion of the bonding pad.

Accordingly, an encapsulation structure ES including the core substrate100in which the semiconductor chips200are accommodated, and an upper redistribution wiring layer130having the sealing layer140covering the first surface102of the core substrate100and the upper insulating layer150provided on the sealing layer140may be formed.

Referring toFIGS.8and9, conductive bumps300may be formed on the chip pads210of the semiconductor chips200and the first wirings122of the core connection wirings120of the encapsulation structure ES.

As illustrated inFIG.8, the first carrier substrate C1and the barrier tape20may be removed from the core substrate100and the sealing layer140. Thus, the second surface104of the core substrate100and the front surface202of the semiconductor chip200may be exposed.

As illustrated inFIG.9, the bumps300may be formed on the exposed second surface104of the core substrate100and the exposed front surface202of the semiconductor chip200. The bumps300may include micro bumps. For example, the bumps300may have a diameter D1within a range of 5 μm to 60 μm.

In particular, a seed layer may be formed on the second surface104of the core substrate100and the front surface202of the semiconductor chip200, and a photoresist pattern having openings that expose bump regions on the first wirings122and the chip pads210may be formed on the seed layer. Then, after filling the opening of the photoresist pattern with a conductive material, the photoresist pattern may be removed and a reflow process may be performed to form the bump300. For example, the conductive material may be formed on the seed layer by a plating process. Alternatively, the bumps may be formed by a screen printing process, a deposition process, etc.

Referring toFIGS.10to12, a lower redistribution wiring layer400having lower redistribution wirings402may be formed on a second carrier substrate C2.

In example embodiments, the second carrier substrate C2may be used as a base substrate for bonding the encapsulation structure on the lower redistribution wiring layer. The second carrier substrate C2may have a shape corresponding to the panel including the core substrate. For example, the second carrier substrate C2may include a silicon substrate, a glass substrate, a non-metal or metal plate, etc.

As illustrated inFIG.10, lower bonding pads412and first lower redistribution wirings422electrically connected to the lower bonding pads412may be formed on the second carrier substrate C2.

In particular, after forming a base insulating layer30on the second carrier substrate C2, the lower bonding pads412may be formed on the base insulating layer30. For example, the base insulating layer30and the first lower insulating layer410may be formed of or include a polymer or a dielectric layer. The base insulating layer30and the first lower insulating layer410may include an insulating film such as ABF. The lower bonding pad412may be a bump pad. The bump pad may include a solder pad or a pillar pad. For example, the lower bonding pad may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

Then, a first lower insulating layer410is formed on the base insulating layer30to cover the lower bonding pads412, and the first lower insulating layer410may be patterned to form first openings that expose regions of the lower bonding pad412. When the first lower insulating layer410includes the insulating film such as ABF, a laser processing process may be performed on the first lower insulating layer410to form the first openings that expose the lower bonding pad regions.

Then, first lower redistribution wirings422may be formed on the first lower insulating layer410to directly contact the lower bonding pads412through the first openings.

The first lower redistribution wiring may be formed by forming a seed layer on a portion of the first lower insulating layer410and in the first opening, patterning the seed layer, and performing an electroplating process. Accordingly, at least portions of the first lower redistribution wirings422may directly contact the lower bonding pads412through the first openings.

For example, the first lower redistribution wiring may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

Then, a second lower insulating layer420may be formed on the first lower insulating layer410to cover the first lower redistribution wirings422.

For example, the second lower insulating layer420may include a polymer or a dielectric layer. The second lower insulating layer420may include a photosensitive insulating material (PID) or an insulating film such as ABF. The second lower insulating layer may be formed by a spin coating process, a vapor deposition process, etc.

As illustrated inFIG.11, the second lower insulating layer420may be patterned to form second openings that expose the first lower redistribution wirings422. Then, second lower redistribution wirings432may be formed on the second lower insulating layer420to directly contact the first lower redistribution wirings422through the second openings. Accordingly, the lower redistribution wirings402including the first lower redistribution wirings422and the second lower redistribution wirings432may be formed. The first lower redistribution wiring422may correspond to a lowermost redistribution wiring among the lower redistribution wirings402, and the second lower redistribution wiring432may correspond to an uppermost redistribution wiring of the lower redistribution wirings402.

Then, a third lower insulating layer430may be formed on the second lower insulating layer420to cover the second lower redistribution wirings432.

For example, the third lower insulating layer430may be formed of or include a polymer or a dielectric layer. The third lower insulating layer430may include a photosensitive insulating material (PID) or an insulating film such as ABF. The third lower insulating layer may be formed by a spin coating process, a vapor deposition process, etc.

As illustrated inFIG.12, upper bonding pads442may be formed to be electrically connected to the second lower redistribution wirings432. The upper bonding pads442may be formed on the uppermost redistribution wirings432among the lower redistribution wirings402.

In example embodiments, when the third lower insulating layer430includes the photosensitive insulating material (PID), an exposure process and a developing process may be sequentially performed on the third lower insulating layer430to form via holes that expose portions of the second lower redistribution wirings432.

For example, a mask may be disposed on the third lower insulating layer430and light may be irradiated onto the mask. The mask may have an opening pattern corresponding to the bumps300on a lower surface of the encapsulation structure ES ofFIG.9.

Then, an electroplating process may be performed to fill the via holes of the third lower insulating layer430with a conductive material, to form the upper bonding pads442. An upper surface of the upper bonding pad442may be exposed by the third lower insulating layer430. A plating pattern for bonding with the bump300may be additionally provided on the upper surface of the upper bonding pad442. For example, the upper bonding pad442may have a diameter D2within a range of 5 μm to 60 μm. The diameter D2of the upper bonding pad442may be the same as the diameter D1of the bump300. The upper bonding pad442may have a pillar shape.

Accordingly, the lower redistribution wiring layer400having the first redistribution wirings402and the lower bonding pads412and the upper bonding pads442electrically connected to the first redistribution wirings402may be formed.

When viewed from a plan view, the lower redistribution wiring layer400may include a first region overlapping the semiconductor chip200mounted on the upper surface of the lower redistribution wiring layer400and a second region surrounding the first region. The second region may be a fan-out region outside the area where the semiconductor chip200is disposed.

The upper bonding pads442may be exposed from an upper surface of the lower redistribution wiring layer100, that is, the third lower insulating layer430. The upper bonding pads442may include chip connection bonding pads formed on the uppermost first redistribution wirings, that is, the second lower redistribution wirings432located in the first region, and conductive structure connection bonding pads formed on the uppermost first redistribution wirings, that is, the second lower redistributions432located in the second region.

Referring toFIGS.13and14, the encapsulation structure ES ofFIG.9may be stacked on the lower redistribution wiring layer400. The encapsulation structure ES may be attached to the lower redistribution wiring layer400using an adhesive layer310.

As illustrated inFIG.13, the adhesive layer310may be formed on the third lower insulating layer430of the lower redistribution wiring layer400. For example, the adhesive layer310may be formed of or include a non-conductive film (NCF). The adhesive layer310may have a thickness T within a range of 5 μm to 50 μm. The thickness T of the adhesive layer310may be determined in consideration of the diameter D1of the bump300. A ratio (T/D1) of the thickness T to the diameter D1may be within a range of 0.8 to 0.9. The micro bumps300may undesirably fail to connect to the lower redistribution wiring layer400if the adhesive layer310is too thick and the adhesive layer310may fail to provide adequate adhesion if its thickness is too small. As the number of the bumps increases, a pitch between the bumps decreases, and accordingly, the diameter of the bump may decrease. The adhesive layer310may be used to attach the encapsulation structure ES to the lower redistribution wiring layer400via the bumps300.

As illustrated inFIG.14, the lower redistribution wiring layer400may be held on a stage of a bonding apparatus, the encapsulation structure ES ofFIG.9may be adsorbed on a head of the bonding apparatus, and the encapsulation structure ES may be bonded on the lower redistribution wiring layer400by a thermal compression process.

The adhesive layer310may be heated and the bumps300may be reflowed to form conductive bumps302between the first wiring122of the core substrate100and the upper bonding pad442and between the chip pad210of the semiconductor chip200of the core substrate100and the upper bonding pads442.

The conductive bumps302may include first conductive bumps303and second conductive bumps304. The first conductive bumps303may be disposed between the chip connection bonding pad443among the upper bonding pads442and the chip pad210of the semiconductor chip200. The second conductive bump304may be disposed between the conductive structure connection bonding pad444among the upper bonding pads442and the conductive structure120of the core substrate100.

Additionally, the adhesive layer310may be formed to fill a gap between the conductive bumps302between the lower surface of the encapsulation structure ES and the lower redistribution wiring layer400. The adhesive layer310may cover side surfaces of the conductive bumps302.

Thus, the encapsulation structure ES may be stacked on the lower redistribution wiring layer400via the conductive bumps302.

In example embodiments, before stacking the encapsulation structure ES on the lower redistribution wiring layer, defects of the lower redistribution wiring layer may be inspected in advance. By stacking the encapsulation structure only on a good lower redistribution wiring layer, it may be possible to minimize die loss and improve process yield.

Further, the lead time may be shortened by simultaneously performing the process of forming the encapsulation structure ES and the process of forming the lower redistribution wiring layer400.

Referring toFIG.15, external connection members500electrically connected to the lower redistribution wiring layers402may be formed on an outer surface of the lower redistribution wiring layer400.

In example embodiments, after removing the second carrier substrate, solder balls as the external connection member may be formed on the lower bonding pads412. After removing the second carrier substrate C2, the base insulating layer30may be removed. Alternatively, after removing the second carrier substrate C2, the base insulating layer30may be partially removed to expose portions of the lower bonding pads412. In this case, the lower bonding pad412may serve as a landing pad, that is, a package pad.

Then, the core substrate100may be individualized by a sawing process to complete the fan out panel level package10ofFIG.1including the lower redistribution wiring layer400and the encapsulation structure ES stacked on the lower redistribution wiring layer140via the conductive bumps302.

FIG.16is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments. The semiconductor package may be substantially the same as the semiconductor package described with reference toFIG.1except for an additional second package. Thus, same reference numerals may be used to refer to the same or like elements and any further repetitive explanation concerning the above elements will be omitted.

Referring toFIG.16, a semiconductor package11may include a first package and a second package600stacked on the first package. The first package may include a lower redistribution wiring layer400, an encapsulation structure ES stacked on the lower redistribution wiring layer400via conductive bumps302and having a core substrate100, a semiconductor chip200and an upper redistribution wiring layer130, and an adhesive layer310interposed between the lower redistribution wiring layer400and the encapsulation structure ES. The first package may be substantially the same as or similar to the unit package described with reference toFIG.1.

In example embodiments, the second package600may include a second package substrate610, a plurality of second semiconductor chips620and630mounted on the second package substrate610, and a sealing member642covering the second semiconductor chips620and630on the package substrate610.

The second package600may be stacked on the first package via conductive connection members650. For example, the conductive connection members650may be formed of or include solder balls, conductive bumps, etc. The conductive connection member650may be disposed between a bonding pad on the upper redistribution wiring layer130of the upper redistribution wiring layer130and a second connection pad614of the second package substrate610. Accordingly, the first package and the second package600may be electrically connected to each other by the conductive connection members650.

The plurality of second semiconductor chips620and630may be sequentially stacked on the second package substrate610by adhesive members624and634. The bonding wirings640may connect the second chip pads622and632of the second semiconductor chips620and630, respectively, to the first connection pads612of the second package substrate610. The second semiconductor chips620and630may be electrically connected to the second package substrate610by bonding wirings640.

Although the second package600includes two semiconductor chips mounted by a wiring bonding method, it will be understood that the number of the semiconductor chips in the second package and a mounting method are not limited thereto.

In example embodiments, the semiconductor package11may further include a heat sink700stacked on the second package600. The heat sink700may be provided on the second package600to dissipate heat from the first and second packages to the outside. The heat sink700may be attached to the second package600by a thermal interface material (TIM)710.

FIG.17shows a method of manufacturing a semiconductor package according to example embodiments.

An encapsulation structure may be provided (S100) including a first wiring and a sealing layer, wherein a semiconductor chip including a chip pad is in a cavity formed in the encapsulation structure and covered by the sealing layer.

A first conductive bump and a second conductive bump may be formed on the first wiring and the chip pad, respectively (S200).

A lower redistribution wiring layer may be provided (S300) including a first upper bonding pad and a second upper bonding pad exposed on an upper surface of the lower redistribution wiring layer.

An adhesive layer may be formed on the upper surface of the lower redistribution wiring layer (S400).

The encapsulation structure may be bonded to the lower redistribution wiring layer (S500).

The semiconductor package may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), or the like, and volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like.