A Galois field multiply/multiply-add/multiply-accumulate system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficient for predicting the modulo remainder for a predetermined irreducible polynomial; and a Galois field adder circuit for adding the product of the multiplier circuit with a third polynomial with coefficients over a Galois field for performing the multiplication and add operations in a single cycle.

FIELD OF THE INVENTION

This invention relates to a Galois field multiply/multiply-add/multiply accumulate system which can perform a multiply/multiply-add/multiply accumulate operation in one cycle.

BACKGROUND OF THE INVENTION

Galois field Multiplication, Multiply-Add and Multiply-Accumulate operations are used in a number of applications. For example, in executing forwarded error control (FEC) coding schemes such as Reed-Solomon, sixteen syndromes must be calculated using polynomials over a Galois field. This is done recursively using Homer's rule. For example: 1+x+x2+x3+x4can also be written recursively as x(x(x(x+1)+1)+1)+1 which requires a series of multiply-add operations. Multiply-accumulate operations are required in advance encryption standards (AES) cipher function for the MixColumn transformation where a matrix is multiplied by a vector. In very long instruction word (VLIW) processors there are a number of compute units e.g., multiplier, adder and shifter. Thus at any time while one value is undergoing multiplication, the product of the previous multiplication can be undergoing an add operation. This simultaneous operation or pipelining enables a long string of n values to be completely processed in only n+1 cycles instead of 2n cycles. However in smaller processors where one compute unit must do all the function, each value requires two cycles to accomplish multiply and add operations, thus 2n cycles are required to process a set of n values.

BRIEF SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide an improved Galois field multiply/multiply-add/multiply-accumulate system.

It is a further object of this invention to provide such an improved Galois field multiply/multiply-add/multiply-accumulate system which can perform a multiply/multiply-add/multiply-accumulate operation in one cycle.

It is a further object of this invention to provide such an improved Galois field multiply/multiply-add/multiply-accumulate system which can achieve the increased performance without additional logic circuitry.

It is a further object of this invention to provide such an improved Galois field multiply/multiply-add/multiply-accumulate system which can perform either a multiply or multiply and add or multiply and accumulate operations in one cycle.

The invention results from the realization that an improved Galois field multiply/multiply-add/multiply-accumulate system which performs either multiply or multiply and add or multiply and accumulate operations in one cycle with little or no additional logic circuitry can be achieved using a Galois field adder circuit, polynomial multiplier circuit that multiplies binary polynomials in GF(2n), Galois field linear transformer circuit, and storage circuit, for adding the product of first and second polynomials from the multiplier with a third polynomial in a single cycle.

This invention features a Galois field multiply/multiply-add/multiply-accumulate system including a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product and a Galois field linear field transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial. A storage circuit supplies to the Galois field linear transformer circuit a set of coefficients for predicting the modulo remainder for a predetermined irreducible polynomial. A Galois field adder circuit adds the product of the multiplier circuit with a third polynomial with coefficients over a Galois field for performing the multiplication and add operations in a single cycle.

In the preferred embodiment, the third polynomial may be the additive identity polynomial and the add operation may be nulled. The multiplication product may be recursively fed back as the third polynomial and the adder circuit may perform a multiply-accumulate operation. The multiplication product may be delivered to a first output register and the multiply-add/multiply-accumulate result may be delivered to a second output register. The Galois field adder circuit may include a plurality of adder cells associated with the Galois field linear transformer circuit for combining the third polynomial with the product of the first and second in one cycle.

PREFERRED EMBODIMENT

Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings.

There is shown inFIG. 1a Galois field multiply/multiply-add/multiply-accumulate system10which can selectively multiply the values in registers14and16and provide their product to output register11or multiply the values in registers14and16and sum their product with the values in register15and provide that result to output register11.

Before explanation of an embodiment of the invention inFIG. 2et seq. a brief discussion of the properties and operations of Galois field multiplication and addition follows.

A Galois field GF(n) is a set of elements on which two binary operations can be performed. Addition and multiplication must satisfy the commutative, associative and distributive laws. A field with a finite number of elements is a finite field. An example of a binary field is the set {0,1} under modulo 2 addition and modulo 2 multiplication and is denoted GF(2). The modulo 2 addition and multiplication operations are defined by the tables shown in the following figure. The first row and the first column indicate the inputs to the Galois field adder and multiplier. For e.g. 1+1=0 and 1*1=1.

In general, if p is any prime number then it can be shown that GF(p) is a finite field with p elements and that GF(pm) is an extension field with pmelements. In addition, the various elements of the field can be generated as various powers of one field element, α, by raising it to different powers. For example GF(256) has 256 elements which can all be generated by raising the primitive element, α, to the 256 different powers.

In addition, polynomials whose coefficients are binary belong to GF(2). A polynomial over GF(2) of degree m is said to be irreducible if it is not divisible by any polynomial over GF(2) of degree less than m but greater than zero. The polynomial F(X)=X2+X+1 is an irreducible polynomial as it is not divisible by either X or X+1. An irreducible polynomial of degree m which divides X2m−1+1, is known as a primitive polynomial. For a given m, there may be more than one primitive polynomial. An example of a primitive polynomial for m=8, which is often used in most communication standards is F(X)=x8+x4+x3+x2+x+1.

Galois field addition is easy to implement in software, as it is the same as modulo addition. For example, if 29 and 16 are two elements in GF(28) then their addition is done simply as an XOR operation as follows: 29(11101)⊕16(10000)=13(01101).

Galois field multiplication on the other hand is a bit more complicated as shown by the following example, which computes all the elements of GF(24), by repeated multiplication of the primitive element α. To generate the field elements for GF(24) a primitive polynomial G(x) of degree m=4 is chosen as follows G(x)=X4+X+1. In order to make the multiplication be modulo so that the results of the multiplication are still elements of the field, any element that has the fifth bit set is brought into a 4-bit result using the following identity F(α)=α4+α+1=0. This identity is used repeatedly to form the different elements of the field, by setting α4=1+α. Thus the elements of the field can be enumerated as follows:

since α is the primitive element for GF(24) it can be set to 2 to generate the field elements of GF(24) as {0,1,2,4,8,3,6,12,11 . . . 9}.

It can be seen that Galois field polynomial multiplication can be implemented in two basic steps. The first is a calculation of the polynomial product c(x)=a(x)*b(x) which is algebraically expanded, and like powers are collected (addition corresponds to an XOR operation between the corresponding terms) to give c(x).For example c(x)=(a3x3+a2x2+a1x1+a0)*(b3x3+b2x3+b1x1+b0)
C(x)=c6x6+c5x5+c4x4+c3x3+c2x2+c1x1+c0
where:

The second is the calculation of d(x)=c(x) modulo p(x) where p(x) is an irreducible polynomial.

To illustrate, multiplications are performed with the multiplication of polynomials modulo an irreducible polynomial. For example: (if p(x)=x8+x4+x3+x+1)
{57}*{83}={c1} because,
Each of these {*} bytes is the concatenation of its individual bit values (0 or 1) in the order {b7, b6, b5, b4, b3, b2, b1, b0} and are interpreted as finite elements using polynomial representation:
b7x7+b6x6+b5x5+b4x4+b3x3+b2x2+b1x1+b0x0=Σb1x1

An improved Galois field multiplier system10,FIG. 2, according to this invention includes a binary polynomial multiplier circuit12for multiplying two binary polynomials in register14with the polynomials in register16to obtain their product is given by the sixteen-term polynomial c(x) defined as chart II. Multiplier circuit12actually includes a plurality of multiplier cells12a,12b,12c . . .12n.

Each term includes an AND function as represented by an * and each pair of terms are combined with a logical exclusive OR as indicated by a ⊕. This product is submitted to a Galois field linear transformer circuit18which may include a number of Galois field linear transformer units18a,18b,18c . . .18neach composed of 16×8 cells35, which respond to the product produced by the multiplier circuit12to predict in one cycle the modulo remainder of the polynomial product for a predetermined irreducible polynomial. The multiplication is performed in units18a,18b,18c . . .18n.The construction and operation of this Galois field linear transformer circuit and each of its transformer units and its multiplier function is explained more fully in U.S. Pat. No. 6,587,864 B1 entitled GALOIS FIELD LINEAR TRANSFORMER, to Stein et al. and GALOIS FIELD MULTIPLIER SYSTEM, Stein et al., Ser. No. 60/334,510, filed Nov. 30, 2001 (AD-240J) each of which is incorporated herein in its entirety by this reference. Each of the Galois field linear transformer units predicts in one cycle the modulo remainder by dividing the polynomial product by an irreducible polynomial. That irreducible polynomial may be, for example, any one of those shown in Chart III.

Chart III

The Galois field multiplier presented where GF(28) is capable of performing with all powers 28and under is shown in Chart III. For lower polynomials the coefficients at higher than the chosen power will be zeros, e.g., if GF(25) is implemented coefficents between GF(25) and GF(28) will be zero. Then the prediction won't be made above that level.

For this particular example, the irreducible or primitive polynomial 0x11D in group GF(28) has been chosen. A storage circuit20with storage cells26supplies to the Galois field linear transformer circuit a set of coefficients for predicting the modulo remainder for that particular primitive or irreducible polynomial. For a Galois field GF(28) with primitive polynomial 0x11D the storage circuit20produces the matrix setup values as shown inFIG. 3where each crossing of lines, e.g.,22represents a cell35of linear transformer units18a,18b, . . .18n.Each enlarged dot24indicates a cell which has been enabled by the presence of a 1 in the associated storage cell26in storage circuit20. The programming of the storage cells26of circuit20to provide the proper pattern of 1's to produce the prediction in one cycle of the modulo operation of the irreducible polynomial is shown in column28. The matrix shown inFIG. 3is an array of sixteen inputs and eight outputs.

An example of the GF multiplication according to this invention occurs as follows:

In accordance with this invention,FIG. 2, there is a third register15which includes a third polynomial with coefficients over a Galois field. Typically, each of the registers14,16, and15may include four byte sections of 8 bits each so that each register contains four bytes or 32 bits total. The output from register15is delivered to Galois field adder circuit19which in this embodiment includes bus17and number of exclusive OR gates19, one for each bit of bus17. The product obtained in Galois field linear transformer circuit18is delivered on bus21so that the simple product of the multiplication may be available in the Mpy register23in output register circuit11whereas the combination of the product on bus21and the third polynomial is combined in adder circuit19including exclusive OR circuit19′ to provide the multiply and add or multiply and accumulate result in Mpa register25of output register circuit11. For exampleFIG. 9, if the output of the Galois field multiplier system10is recursively feed back at input register circuit15while two new values are passed to input registers circuit14and16a Multiply and accumulate (MAC) is performed. On the other handFIG. 10, if the output of the Galois field multiplier system10is recursively feed back at input register circuit14while two new values are passed to input registers circuit15and16a Multiply and add (MPA) is performed. In this way the entire multiplication of the polynomials in registers14and16and their addition with the polynomial in register15is all accomplished in one cycle of operation.

Each cell29,FIG. 2, of the polynomial multiplier circuit12includes a number of AND gates30,FIG. 4, one for each term of the polynomial product and an exclusive OR gate32one for each pair of terms in the polynomial product. AND gate30executes the multiplication while exclusive OR gate32effects the summation. Each cell35,FIG. 2, in the Galois field linear transformer circuit18receives an input from the previous cell and provides an output to the next cell. The first cell input is grounded at31as shown inFIG. 3. Each cell,33,FIG. 5, of storage circuit20includes a flip-flop34having a data, D, input, a Wr, Clock, input, and a Q output, enable. Each cell35of the Galois field linear transformer circuit and each of the one or more units of the Galois field linear transformer circuit includes a cell35,FIG. 4, having an AND gate36,FIG. 6, and an exclusive OR gate38, as also explained in U.S. Pat. No. 6,587,864 entitled GALOIS FIELD LINEAR TRANSFORMER, to Stein et al., incorporated herein in its entirety. In each of the cells29,33, and35the specific implementations shown are not a limitation of the invention. For example the storage device33need not be implemented by a flip-flop, any other storage device could be used. InFIGS. 2 and 4cells29and35respectively need AND functions and exclusive OR functions, but these may be performed in a number of different ways not requiring a specific XOR gate or AND gate as long as these are logic circuits that function in a Boolean sense like an XOR gate and AND gate. For example, the AND function can be achieved without a specific AND gate using a 2:1 input multiplexor to perform the AND function.

Although inFIG. 2the embodiment shown uses adder circuit19, which includes an actual logic circuit, exclusive OR circuit19′, this is not a necessary limitation of the invention. The invention can be made even more simply as shown inFIG. 7where the polynomial value in register15is delivered directly on line17ato the first of cells35in Galois field linear transformer circuit18.

In this instance the grounded connections31,FIG. 3are removed and instead the connection is made at19awith the input on line17aso that the adder circuitry includes simply line17aand the connections19ato perform the multiply and add or multiply and accumulate all in one cycle. However, if straight multiplication without addition is desired, then input registers circuit15should hold the additive identity property for addition “0” and the add operation is nulled. In a slightly less simple implementation,FIG. 8, adder circuit19bincludes in addition to the input line17ba number of gate19′bwhich receive the inputs form line17band are in turn each one connected to a different input of the first cell35in Galois field linear transformer circuit18. The signal on line50conditions each gate to pass or not pass the value from the polynomial stored in register15. If straight multiplication without addition is desired then all of the gates19′bcan be disabled. With the gates enabled the polynomial in register15will be added to the product of the multiplication of the polynomials in registers14and16. This use of the first cells35in Galois field linear transformer circuit18is more fully shown and explained in the U.S. patent application entitled PROGRAMMABLE DATA ENCRYPTION ENGINE, by Stein et al., Ser. No. 10/170,267, filed Jun. 12, 2002, publication No. US 2003/0103626 A1, incorporated herein by this reference.