FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION

A hardware execution unit within a processor core executes a second instruction, which is part of a software thread, and which is executed out of order within the software thread. A sticky bit flip detection hardware device detects a change to a sticky bit in a floating-point status and control register (FPSCR) within the processor core. An instruction issue hardware unit identifies a first instruction that is in the software thread that is capable of reading or clearing the sticky bit. A flushing execution unit flushes all results of instructions from an instruction completion table (ICT) that include and are after the first instruction in the software thread. A hardware dispatch device dispatches all instructions that include and are after the first instruction in the software thread for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order.

BACKGROUND

The present disclosure relates to the field of processors, and more specifically to the field of processor cores. Still more specifically, the present disclosure relates to the use of status and control registers when executing instructions out of order within a processor core.

SUMMARY

In an embodiment of the present invention, a method and/or computer program product manages sticky bits within a floating-point status and control register (FPSCR) when instructions within a software thread are executed out of order within a processor core. A hardware execution unit within a processor core executes a second instruction, which is part of a software thread, and which is executed out of order within the software thread. A sticky bit flip detection hardware device detects a change to a sticky bit in a floating-point status and control register (FPSCR) within the processor core. A sticky bit is an exception bit that describes an exception that has occurred while executing an instruction within the processor core, and a sticky bit remains fixed until cleared by a move-to-FPSCR instruction, in which data is moved to the FPSCR, thus clearing the sticky bits. An instruction issue hardware unit identifies a first instruction that is in the software thread and that is capable of reading or clearing a sticky bit, where the first instruction is sequentially listed before any other instruction in the software thread that is capable of reading or clearing a sticky bit. In response to the instruction issue hardware unit identifying the first instruction, a flushing execution unit flushes all results of instructions from an instruction completion table (ICT) that include and are after the first instruction in the software thread. In response to the flushing execution unit flushing all results of instructions from the ICT that include and are after the first instruction in the software thread, dispatching, by a hardware dispatch device, all instructions that include and are after the first instruction in the software thread, and that are capable of reading or clearing a sticky bit, for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order.

In an embodiment of the present invention, a processor core includes: a hardware execution unit, where the hardware execution unit executes a second instruction, where the second instruction is part of a software thread, and where the second instruction is executed out of order within the software thread; a sticky bit flip detection hardware device that detects a change to a sticky bit in a floating-point status and control register (FPSCR) within the processor core, where the sticky bit is an exception bit that describes an exception that has occurred while executing an instruction within the processor core, and where the sticky bit remains fixed until cleared by a move-to-FPSCR instruction; an instruction issue hardware unit that identifies a first instruction in the software thread that is in an issue queue and that is capable of reading or clearing a sticky bit, where the first instruction is sequentially listed before any other instruction in the software thread that is capable of reading or clearing a sticky bit; a flushing execution unit that, in response to the first instruction being identified in the issue queue, flushes all results of instructions from an instruction completion table (ICT) that include and are after the first instruction in the software thread; and a hardware dispatch unit that, in response to the flushing execution unit flushing all results of instructions from the ICT that include and are after the first instruction in the software thread, dispatches all instructions including and after the first instruction in the software thread, that are capable of reading or clearing a sticky bit, for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order.

DETAILED DESCRIPTION

With reference now to the figures, and particularly toFIG. 1, there is depicted a block diagram of an exemplary computer101, within which the present invention may be utilized. Note that some or all of the exemplary architecture shown for computer101may be utilized by software deploying server149shown inFIG. 1.

Computer101includes a processor103, which may utilize one or more processors each having one or more processor cores105. Processor103is coupled to a system bus107. A video adapter109, which drives/supports a display111, is also coupled to system bus107. System bus107is coupled via a bus bridge113to an Input/Output (I/O) bus115. An I/O interface117is coupled to I/O bus115. I/O interface117affords communication with various I/O devices, including a keyboard119, a mouse121, a Flash Drive123, and an optical storage device125(e.g., a CD or DVD drive). The format of the ports connected to I/O interface117may be any known to those skilled in the art of computer architecture, including but not limited to Universal Serial Bus (USB) ports.

Computer101is able to communicate with a software deploying server149and other devices via network127using a network interface129, which is coupled to system bus107. Network127may be an external network such as the Internet, or an internal network such as an Ethernet or a Virtual Private Network (VPN). Network127may be a wired or wireless network, including but not limited to cellular networks, Wi-Fi networks, hardwired networks, etc.

A hard drive interface131is also coupled to system bus107. Hard drive interface131interfaces with a hard drive133. In a preferred embodiment, hard drive133populates a system memory135, which is also coupled to system bus107. System memory is defined as a lowest level of volatile memory in computer101. This volatile memory includes additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers. Data that populates system memory135includes computer101's operating system (OS)137and application programs143.

OS137includes a shell139, for providing transparent user access to resources such as application programs143. Generally, shell139is a program that provides an interpreter and an interface between the user and the operating system. More specifically, shell139executes commands that are entered into a command line user interface or from a file. Thus, shell139, also called a command processor, is generally the highest level of the operating system software hierarchy and serves as a command interpreter. The shell provides a system prompt, interprets commands entered by keyboard, mouse, or other user input media, and sends the interpreted command(s) to the appropriate lower levels of the operating system (e.g., a kernel141) for processing. Note that while shell139is a text-based, line-oriented user interface, the present invention will equally well support other user interface modes, such as graphical, voice, gestural, etc.

As depicted, OS137also includes kernel141, which includes lower levels of functionality for OS137, including providing essential services required by other parts of OS137and application programs143, including memory management, process and task management, disk management, and mouse and keyboard management.

Application programs143include a renderer, shown in exemplary manner as a browser145. Browser145includes program modules and instructions enabling a World Wide Web (WWW) client (i.e., computer101) to send and receive network messages to the Internet using HyperText Transfer Protocol (HTTP) messaging, thus enabling communication with software deploying server149and other described computer systems.

Application programs143in computer101's system memory (as well as software deploying server149's system memory) also include a Floating Point Status and Control Register Management Logic (FPSCRML)147. FPSCRML147includes code for implementing the processes described below inFIGS. 4-5. In one embodiment, computer101is able to download FPSCRML147from software deploying server149, including in an on-demand basis.

A Floating Point Status and Control Register (FPSCR) is a register within a processor core that contains exception bits indicative of exceptions that occur when certain instructions are executed within a processor core. For example, if an ADD operation performed by an execution unit (EU) within a processor core attempts to add two operands such that an overflow results (i.e., the sum is a value that is larger than a capacity of a target register in which the sum is to be stored), then a floating-point overflow exception bit (OX) is stored within the FPSCR. Subsequent operations/instructions within a software thread will need to know about and/or use this exception bit. When stored within the FPSCR, such exception bits are called “sticky bits” if they are non-transitory (i.e., they can only be cleared out of the FPSCR by a move-to-FPSCR instruction), such that the sticky bits are changed/flushed from the FPSCR.

Fast execution of reads (i.e., moving a sticky bit from the FPSCR) and clears (i.e., moving a sticky bit to the FPSCR) is highly important to a floating point code's performance. That is, when the FPSCR's sticky bit is updated by a floating point execution unit (e.g., a floating point add execution unit, a floating point load execution unit, etc.), all subsequent instructions that required the sticky bit must wait for the bit to be set before they can be executed. If the instructions are executed in order (i.e., in a serial next-to-complete (NTC) manner), then performance can suffer. That is, operations are slowed down since only one execution unit can be used at a time, and since no instruction can execute until the preceding instruction in the software thread executes, even if the subsequent instruction does not depend on the preceding instruction. However, if instructions are executed out of order (OOO), then problems may arise if an instruction reads the FPSCR looking for a sticky bit that should have been provided by a previous instruction, but which is not there since the OOO instruction was executed before that previous instruction (that generated and stored the sticky bit in the FPSCR) was executed.

FIG. 2illustrates a table200showing the impact on sticky bits within a floating-point status and control register (FPSCR) in a processor core when instructions within a software thread are executed in a next-to-complete (NTC) serial manner. Assume that instructions1-10identified in the “Instruction identifier” column are instructions in a software thread (i.e., a set of instructions designed to be executed as a set). Assume further inFIG. 2that instructions1-10are executed in an NTC in-order (serial) manner. That is, instruction2waits until instruction1finishes executing (i.e., being dispatched to a particular hardware execution unit in the processor core such as a floating point addition hardware execution unit, a floating point load/store hardware execution unit, etc.) before instruction2executes. Similarly, instruction3waits until instruction2finishes executing before instruction3starts executing, instruction4waits until instruction3finishes executing before instruction4starts executing, etc.

Assume now that instruction1is not able to set a sticky bit (as indicated by the “0” in the “Sticky bit set” column) for a particular exception condition (e.g., a data overflow). Thus, the content of the FPSCR for this exception/sticky bit is empty (as indicated by the “0” in the “FPSCR content” column) after instruction1executes (as indicated by the “1” in the “Completion flag” column). Note that since there is no earlier instruction in the software thread (instructions1-10), then there is no sticky bit in the FPSCR (for this exception) for instruction1to read (assuming that the FPSCR is flushed before a new software thread starts executing).

With reference now to instruction2, assume that instruction2is able to set the sticky bit (as indicated by the “1” in the “Sticky bit set” column), and does so (as indicated by the “1” in the FPSCR content column) after it finishes executing (as indicated by the “1” in the “completion flag” column). Note that instruction1did not set the sticky bit, and thus there is no sticky bit in the FPSCR for instruction2to read (as indicated by the “0” in the “Sticky bit read from FPSCR” column).

With reference now to instruction3, note that instruction3reads the sticky bit from the FPSCR (as indicated by the “1” in the “Sticky bit read from FPSCR” column) that was set by instruction2. Similarly, instructions4-10also read this same sticky bit that was set by instruction2, since the exception/sticky bit remains in the FPSCR (i.e., is “sticky”). Thus, each of instructions3-10read the correct sticky/set/exception bit.

With reference now toFIG. 3, a table301shows the same instructions1-10, but now they are able to execute out of order (OOO). For example, assume that instruction1has executed (as indicated by the “1” in the “Finish flag” column), and then instruction10executes out of order (as indicated by the “1” in the “Finish flag” column for instruction10but where there is a “0” in the “Finish flag” column for instructions2-9). When instruction10executes, there is no exception/sticky bit (for the exception described above) in the FPSCR, since instruction2has not executed yet. Thus, instruction10will erroneously assume that there is no exception/sticky bit in the FPSCR, and will not execute properly. Note that the term “Finish” indicates that the instruction has executed and written back results, which can happen out of order.

Thus, the present invention presents a new and novel mechanism to provide out-of-order execution of instructions that use the FPSCR's sticky bit to improve performance of the processor core. That is, the software thread (instructions1-10) could always execute serially (in a next-to-complete mode), but this is slow and inefficient. Therefore, out-of-order (OOO) instruction execution is faster if the sticky bits have been set at the right time. The present invention allows the processor core to routinely execute instructions in the software thread out-of-order, and to revert to the slower NTC serial mode only when there is an error in the FPSCR sticky bit (i.e., it has not been timely set).

With reference now toFIG. 4, illustrative components (i.e., not all of the components) within a processor core400that enable the management of sticky bits within an FPSCR when instructions within a software thread are executed out of order within the processor core is presented. That is, the present invention allows for speculative OOO instruction execution that assumes that sticky bits in the FPSCR are correct (i.e., they have been timely changed or else they do not change at all) while execution of instructions in a software thread are in flight (i.e., are in the process of executing within the processor core). However, if a sticky bit changes, then the thread is flushed as described below (i.e., beginning with the next instruction that is identified as being able to read or clear the sticky bit), and the process switches to a serial (NTC) execution order.

Note that the FPSCR428(e.g., an architected FPSCR) depicted inFIG. 4may be accessed by the mapper/register file406, the completion logic418, the FPSCR-sticky flip detection414, and other components of the processor core400shown inFIG. 4.

As shown within processor core400, a dispatch402is a hardware dispatching device that dispatches instructions to an instruction sequencing unit (ISU)432(i.e., elements below line404inFIG. 4). Dispatch402dispatches instructions (e.g., instructions1-10shown inFIG. 3) and identifies them according to whether or not they are able to set sticky bits (see the “Sticky bit set” columns inFIG. 3). That is, table301inFIG. 3is (or includes) an instruction completion table (ICT) that identifies which instructions are able to read (read a sticky bit from the FPSCR) or clear (move a zero to the FPSCR) sticky bits as “FPSCR-sticky instructions”. Table301also indicated a “FPSCR-sticky-pending” bit per thread to indicate that a sticky bit may change during the course of execution according to a particular instruction (e.g., instruction2inFIG. 3). This bit is active only when the ICT includes any FPSCR-sticky-instruction.

A Mapper/Register file406includes a hardware mapper that sources out the architected sticky bit to instructions that need to use it as a source, and also indicates to the Issue Queue408that the source (i.e., operand source such as a data cache in the processor core or result of an arithmetic instruction), is ready (i.e., has the requisite instruction code and operand data).

As described herein, the Mapper/Register file406generates a “sticky-change” bit per thread when an architected sticky-bit is modified (seeFIG. 3).

Issue queue408is a hardware storage device that stores an FPSCR-sticky source (i.e., the source data, or at least a tag indicating which instructions will produce the source data). The “valid” column in issue queue408indicates whether or not a particular instruction has an FPSCR-sticky source (i.e., needs to read the FPSCR).

If the instruction is using the FPSCR sticky bit as a source (when a speculative out-of-order execution is being performed), then the instruction is executed normally and out-of-order. Similarly, if the instruction is known to actually set or clear the sticky bit, then it is issued out normally, even if out-of-order.

Execution unit410represents one or more hardware execution units within the processor core. Examples of execution unit410include, but are not limited to, floating-point addition hardware units, floating-point load/store hardware units, etc., as well as sticky bit setters, sticky bit handlers, etc. As indicated by line412, some instructions cause execution unit410to directly (and always) set a sticky (exception) bit into the FPSCR, such as “Move To (MT) the FPSCR” instruction. Other instructions such as an “ADD” instruction may or may not set a sticky bit into the FPSCR, as also indicated by line412.

If the instruction using the FPSCR sticky bit is executing, then it executes and may write the sticky bit back as normal. Similarly, if the instruction setting the FPSCR sticky bit is executing, then it also executes and writes the sticky bit back as normal. If the sticky-bit changes, a FPSCR-sticky flip detection414(e.g., a hardware device that detects the change to the sticky bit) tells the Mapper/Register file406that a sticky bit is flipping. The Mapper/Register file406will then generate a “sticky change” bit and send it to the exception logic416as discussed below.

Completion logic418maintains an instruction completion table (ICT), which is a record of all instructions in flight, with an indicator for instructions that are able to set a sticky bit (as identified in the column labeled “FPSCR-sticky”). The “Valid” column indicates whether or not a particular instruction has completed (invalid) or is still in flight (valid—waiting to complete or else in the process of completing). When the FPSCR-sticky-bit instruction is at NTC (i.e., is the next to complete instruction, even though the software thread is executing in an out-of-order manner), then the processor core stops the completion logic418from completing instructions until the exception logic416is given the opportunity to examine the sticky-bit status.

With reference again to the exception logic416, a “FPSCR-change-seen” bit per thread as received from the Mapper/Register File406is maintained by 1) setting the “FPSCR-change-seen” bit when a “sticky-change” occurs (as detected by the FPSCR-sticky flip detection414), and 2) clearing the “FPSCR-change-seen” bit when “FPSCR-sticky-pending” is not active.

When an instruction completion table (ICT) (i.e., hardware that is in the ISU) is stopped for an FPSCR-sticky bit, the ICT examines the “FPSCR-change-seen” bit. If the “FPSCR-change-seen” bit is set, then a NTC FPSCR flush is performed, thus clearing the “FPSCR-change-seen” bit and setting a corresponding “FPSCR-flush” bit. For example, assume that instruction2inFIG. 3is the first instruction that is able to read or clear the sticky bit. As such, all instructions beginning with instruction2(include the NTC instruction2and subsequent instructions3-10) are flushed (including their sticky bits). These operations are performed by the FPSCR sticky change processing420, which identifies at least one of the instructions in the completion logic418is able to flip the sticky bit (according to OR logic422).

A Back-off Mechanism (i.e., logic above line404inFIG. 4) allows the processor core to switch from out-of-order (OOO) instruction execution to next-to-complete (NTC) instruction execution based on the change to the sticky bit. Thus, the “Back-off” mechanism includes a backoff counter424(that identifies how many FPSCR sticky-reading or -clearing instructions after the FPSCR flush instruction are to be executed when NTC) and a decoder426(that lets the dispatch402know if an instruction is an FPSCR-sticky bit reader or clearer and/or if the instructions should now be executed serially in a NTC manner) handles this by forcing any FPSCR sticky-reading or -clearing instructions to be marked as “NTC issue” during a window after an FPSCR flush.

The Decoder “Back-off” Behavior affects certain operations, such as those operations that can clear sticky FPSCR exceptions and those operations that read sticky FPSCR exceptions.

The backoff counter424sets a new counter to be implemented per thread. The backoff counter424is active when non-zero. The backoff counter424is set to a maximum value (e.g., 8 instructions after the identified sticky bit setting instruction) that are marked as “NTC Issue” when “FPSCR-flush” occurs. The backoff counter424is also set to the maximum value when the when counter is non-zero and “FPSCR-change-seen” occurs.

With reference now toFIG. 5, a high-level flow chart of exemplary steps taken by hardware devices to manage sticky bits within an FPSCR when instructions within a software thread are executed out of order within a processor core is presented.

After initiator block501, a hardware execution unit (e.g., execution unit410shown inFIG. 4) within a processor core (e.g., processor core400shown inFIG. 4) executes a second instruction, as described in block503. The second instruction (e.g., instruction10inFIG. 3) is part of a software thread, and is executed out of order within the software thread (e.g., before instruction2).

A sticky bit flip detection hardware device (e.g., FPSCR-sticky flip detection414shown inFIG. 4) detects a change to a sticky bit in a floating-point status and control register (e.g., FPSCR428shown inFIG. 4) within the processor core, as described in block505. The sticky bit is an exception bit that describes an exception that has occurred while executing an instruction within the processor core, and remains fixed until cleared by a Move-To FPSCR instruction.

As described in block507, an issue queue (e.g., issue queue408inFIG. 4) identifies a first instruction (e.g., instruction2inFIG. 3) in the software thread that is capable of setting the sticky bit. As described in the examples presented herein, the first instruction is sequentially listed before any other instruction in the software thread that is capable of setting the sticky bit. That is inFIG. 3, instruction1is not able to set the sticky bit; thus instruction2is the first instruction in the software thread that is capable of setting a sticky bit.

As described in block509, in response to examining that the next-to-complete instruction has been identified as an FPSCR-sticky bit reader or clearer, a flushing execution unit (e.g., FPSCR sticky change processing420and dispatch402shown inFIG. 4) flushes all results of instructions from an instruction completion table (ICT) that include and are after the next-to-complete instruction in the software thread.

As described in block511, in response to the flushing execution unit flushing all results of instructions from the ICT that include and are after the first instruction in the software thread, a hardware dispatch device (e.g., dispatch402inFIG. 4) dispatches all instructions beginning with the first instruction in the software thread for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order, for those instructions that can read or clear FPSCR sticky bits. Thus, instructions3-10inFIG. 3that can read or clear FPSCR sticky bits are now relegated to executing sequentially in a NTC manner.

The flow-chart ends at terminator block513.

In an embodiment of the present invention, an ICT stop bit setter (e.g., ICT stop bit setter430inFIG. 4) sets an ICT stop bit in the ICT (e.g., in the issue queue408) to identify all instructions that are capable of reading or clearing the sticky bit.

In an embodiment of the present invention, the hardware dispatch device (e.g., backoff counter424and dispatch402inFIG. 4) limits the instructions that can read or clear FPSCR sticky bits, beginning with the FSPCR-flushed instruction being executed in the NTC sequential order.

In an embodiment of the present invention, the first instruction is a move to instruction to write a sticky bit directly into the FPSCR.

In an embodiment of the present invention, the first instruction is a floating point instruction whose execution results in the sticky bit being set in the FPSCR.

In an embodiment of the present invention, a sticky bit flag hardware setter (e.g., part of mapper/register file406shown inFIG. 4) sets a flag with the ICT that identifies all instructions that are capable of reading or clearing a sticky bit from the FPSCR.

In an embodiment of the present invention, the first instruction and the second instruction are floating point instructions.