SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

The present disclosure relates to semiconductor packages. An example semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, and a second bonding pad disposed on a second surface of the second semiconductor chip facing the first surface. The second bonding pad is in contact with the first bonding pad, and includes a third surface in contact with the first bonding pad and a fourth surface opposite to the third surface. The second semiconductor chip includes a first wiring pad in contact with the fourth surface and a second wiring pad spaced apart from the first wiring pad and the second bonding pad. A thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority, under 35 U.S.C. 119, from Korean Patent Application No. 10-2023-0115145 filed on Aug. 31, 2023 in the Korean Intellectual Property Office, the entire contents of which are herein incorporated by reference.

BACKGROUND

With the development of the electronics industry, demands for higher functionality, higher speed, and smaller size of electronic components are increasing. In response to this trend, a method for stacking and mounting a plurality of semiconductor chips on a single package wiring structure, or stacking packages on top of each other may be used.

In recent years, an interconnected length between stacked chips is reduced, by using direct bonding to vertically stack a plurality of dies.

SUMMARY

The present disclosure relates to semiconductor packages and semiconductor package fabricating methods, including a semiconductor package having improved product reliability.

In general, according to some aspects, a semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad which is disposed on a first surface of the first semiconductor chip facing the second semiconductor chip and a second bonding pad which is disposed on a second surface of the second semiconductor chip facing the first surface, and is in contact with the first bonding pad, wherein the second bonding pad includes a third surface that is in contact with the first bonding pad, and a fourth surface opposite to the third surface, wherein the second semiconductor chip includes a first wiring pad that is in contact with the fourth surface of the second bonding pad, and a second wiring pad which is spaced apart from the first wiring pad and not in contact with the second bonding pad, wherein a thickness of the second wiring pad is smaller than a thickness of the first wiring pad.

In general, according to some aspects, a semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first bonding pad which is disposed on a first surface of the first semiconductor chip facing the second semiconductor chip and a second bonding pad which is disposed on a second surface of the second semiconductor chip facing the first surface, and is in contact with the first bonding pad, wherein the second semiconductor chip includes a first wiring pad which is in contact with the second bonding pad, and a second wiring pad which is spaced apart from the first wiring pad, and is not in contact with the second bonding pad, wherein the first wiring pad includes a third surface that is in contact with the second bonding pad, and a fourth surface opposite to the third surface, wherein the second wiring pad includes a fifth surface facing the first semiconductor chip, and a sixth surface opposite to the fifth surface, the fourth surface and the sixth surface are disposed on the same plane, and the third surface is located below the fifth surface on the basis of the first surface of the first semiconductor chip.

In general, according to some aspects, a semiconductor package comprises a package substrate, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bonding pad which is disposed on a first surface of the first semiconductor chip facing the second semiconductor chip, a second bonding pad which is disposed on a second surface of the second semiconductor chip facing the first surface, and is in contact with the first bonding pad and a molding film which is disposed on the package substrate, and covers the first semiconductor chip and the second semiconductor chip, wherein the second bonding pad includes a third surface that is in contact with the first bonding pad, and a fourth surface opposite to the third surface, the first semiconductor chip includes a first through electrode that is in contact with the first bonding pad, and a first wiring structure connected to the first through electrode, wherein the second semiconductor chip includes a first wiring pad that is in contact with the fourth surface of the second bonding pad, a second wiring structure including a second wiring pad that is spaced apart from the first wiring pad and not in contact with the second bonding pad, and a second through electrode connected to the second wiring structure, wherein the first bonding pad and the second bonding pad include copper, the first wiring pad and the second wiring pad include aluminum, and a thickness of the second wiring pad is 50% or less of a thickness of the first wiring pad.

In general, according to some aspects, a method for fabricating a semiconductor package comprises forming a first bonding pad on a first surface of a first semiconductor chip, forming a first wiring pad of a first thickness and a second wiring pad of a second thickness smaller than the first thickness, on a second surface of the second semiconductor chip, forming an insulating film which surrounds a side face of the first wiring pad and covers the second wiring pad, on the second surface of the second semiconductor chip, forming a second bonding pad on the first wiring pad and bonding the first bonding pad and the second bonding pad.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating an example of a semiconductor package.FIG.2is an example enlarged view of a portion P ofFIG.1.

Referring toFIGS.1and2, the semiconductor package includes first to fourth semiconductor chips100to400, a package substrate500, back bonding pads150,250,350, and450, front bonding pads160,260, and360, bonding insulation films610,620, and630, connection wiring pads142,242,342, and442, peripheral wiring pads144,244,344, and444, and a molding film700.

The explanation of the back bonding pads150,250,350, and450may be substantially the same as the explanation of the first back bonding pad150and the second back bonding pad250. Therefore, the following explanation will focus on the first back bonding pad150and the second back bonding pad250.

The explanation of the front bonding pads160,260, and360and the package bonding pad560may be substantially the same as the explanation of a first front bonding pad160. Therefore, the first front bonding pad160will be mainly described below.

The explanation of the connection wiring pads142,242,342, and442may be substantially the same as the explanation of a first connection wiring pad142and the second connection wiring pad242. Therefore, the following description will focus on the first connection wiring pad142and the second connection wiring pad242.

The explanation of the peripheral wiring pads144,244,344, and444may be substantially the same as the explanation of the first peripheral wiring pad144and the second peripheral wiring pad244. Therefore, the following explanation of will focus on the first peripheral wiring pad144and the second peripheral wiring pad244.

The first to fourth semiconductor chips100to400may be logic chips or memory chips. The first to fourth semiconductor chips100to400may all be memory chips of the same type. For example, the first to fourth semiconductor chips100to400may be volatile memory chips such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory). As another example, the first to fourth semiconductor chips100to400may be nonvolatile memory chips such as a PRAM (Phase-change RAM), a MRAM (Magnetoresistive RAM), a FeRAM (Ferroelectric RAM) or a RRAM (Resistive RAM). As still another example, the first to fourth semiconductor chips100to400may be a HBM (High Bandwidth Memory).

Furthermore, some of the first to fourth semiconductor chips100to400may be memory chips, and others thereof may be logic chips. For example, some of the first to fourth semiconductor chips100to400may be a microprocessor, an analog clement, a digital signal processor or an application processor.

The first to fourth semiconductor chips100to400may be stacked on the package substrate500in a vertical direction. The first to fourth semiconductor chips100to400may be electrically connected to each other through the back bonding pads150,250,350, and450and the front bonding pads160,260, and360, or may be electrically connected to the package substrate500.

The widths of the first to fourth semiconductor chips100to400may be equal to each other. The side faces of the first to fourth semiconductor chips100to400may be disposed on the same plane.

The first semiconductor chip100may include a first semiconductor substrate110, a first semiconductor element layer120, a first through electrode130, a first wiring structure140, a first connection wiring pad142, a first peripheral wiring pad144, a first back bonding pad150, and a first front bonding pad160.

The first semiconductor substrate110may be, for example, bulk silicon or silicon-on-insulator (SOI). As another example, the first semiconductor substrate110may be a silicon substrate. As still another example, the first semiconductor substrate110may include, but not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.

The first semiconductor substrate110may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. The first semiconductor substrate110may have various element isolation structures, such as a shallow trench isolation (STI) structure.

The first semiconductor element layer120may be disposed on the lower face of the first semiconductor substrate110. The first semiconductor element layer120may include a plurality of various types of individual devices and an interlayer insulating film. The individual devices may include various microelectronic devices, for example, a MOSFET (metal-oxide-semiconductor field effect transformer) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), a flash memory, a DRAM, a SRAM, an EEPROM, a PRAM, a MRAM, a RRAM, an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), an active device, a passive device, and the like.

The individual devices of the first semiconductor element layer120may be electrically connected to conductive regions formed inside the first semiconductor substrate110. The individual devices of the first semiconductor element layer120may be electrically separated from other adjacent individual devices by insulating films. The first semiconductor element layer120may include a first wiring structure140that electrically connects at least two of the plurality of individual devices or a plurality of individual devices and the conductive region of the first semiconductor substrate110.

The first semiconductor element layer120may include a first connection wiring pad142and a first peripheral wiring pad144. The first connection wiring pad142and the first peripheral wiring pad144may be disposed inside the first semiconductor element layer120.

The first connection wiring pad142and the first peripheral wiring pad144may be spaced apart from each other. For example, the first connection wiring pad142and the first peripheral wiring pad144may be horizontally spaced apart at the same level. For example, the first connection wiring pad142and the first peripheral wiring pad144may be spaced apart from each other in a first direction X.

The first connection wiring pad142may be connected to the first wiring structure140and the first back bonding pad150. The first connection wiring pad142may be in contact with the first wiring structure140and the first back bonding pad150. A lower face of the first connection wiring pad142may be in contact with an upper face of the first back bonding pad150. The first connection wiring pad142may electrically connect the first wiring structure140to the first back bonding pad150.

The first peripheral wiring pad144may be connected to the first wiring structure140. The first peripheral wiring pad144may be in contact with the first wiring structure140. The first peripheral wiring pad144may not be connected to the first back bonding pad150. The first peripheral wiring pad144may not be in contact with the first back bonding pad150. A lower face of the first peripheral wiring pad144may be spaced apart from an upper face of the first back bonding pad150. The lower face of the first peripheral wiring pad144may be covered with an insulating film inside the first semiconductor element layer120. The lower face of the first peripheral wiring pad144may be surrounded by an insulating film inside the first semiconductor clement layer120.

The first connection wiring pad142and the first peripheral wiring pad144may include at least one of aluminum (Al) and copper (Cu). For example, the first connection wiring pad142and the first peripheral wiring pad144may each include aluminum (Al).

Although a width of the first peripheral wiring pad144is shown as being smaller than a width of the first connection wiring pad142in the first direction X, the implementation is not limited thereto. For example, the width of the first peripheral wiring pad144may be larger than the width of the first connection wiring pad142.

A first passivation layer121for protecting structures different from the first wiring structure140, the first connection wiring pad142, and the first peripheral wiring pad144inside the first semiconductor element layer120from external impact and moisture may be formed on the first semiconductor element layer120. The first passivation layer121may expose a part of the lower face of the first connection wiring pad142.

The first through electrode130may penetrate the first semiconductor substrate110. The first through electrode130may extend from the upper face of the first semiconductor substrate110toward the lower face. The first through electrode130may be connected to the first wiring structure140provided in the first semiconductor element layer120.

The first through electrode130may include a barrier film formed on a columnar surface and a buried conductive layer for filling the inside of the barrier film. The barrier film may include, but not limited to, at least one of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include, but not limited to, at least one of Cu alloys such as Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, and CuW, W, W alloys, Ni, Ru, and Co.

In some implementations, the insulating film may be interposed between the first semiconductor substrate110and the first through electrode130. The insulating film may include, but not limited to, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

The first wiring structure140may include a metal wiring layer and a via plug. For example, the first wiring structure140may have a multilayer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

The first wiring structure140may be connected to a first connection wiring pad142and a first peripheral wiring pad144. The first wiring structure140may be in contact with the first connection wiring pad142and the first peripheral wiring pad144.

The first back bonding pad150may be disposed on the first semiconductor element layer120. The first back bonding pad150may be electrically connected to the first wiring structure140inside the first semiconductor element layer120. The first back bonding pad150may be electrically connected to the first through electrode130through the first wiring structure140.

The first back bonding pad150may be disposed on the first connection wiring pad142. The first back bonding pad150may be connected to the first connection wiring pad142. The first back bonding pad150may be in contact with the first connection wiring pad142. For example, an upper face of the first back bonding pad150may be in contact with a lower face of the first connection wiring pad142.

The first back bonding pad150may not be connected to the first peripheral wiring pad144. The first back bonding pad150may not be in contact with the first peripheral wiring pad144. The first back bonding pad150may be spaced apart from the first peripheral wiring pad144. An upper face of the first back bonding pad150may be spaced apart from a lower face of the first peripheral wiring pad144.

The first back bonding pad150may be electrically connected to the package bonding pad560. The first back bonding pad150may be in contact with the package bonding pad560. The first back bonding pad150may be bonded to the package bonding pad560. The first back bonding pad150and the package bonding pad560may be directly bonded. The first back bonding pad150and the package bonding pad560may be coupled through a high-temperature annealing process.

The first semiconductor chip100may be electrically connected to the package substrate500by bonding the first back bonding pad150and the package bonding pad560. For example, by coupling the first back bonding pad150and the package bonding pad560, the first connection wiring pad142and the first wiring structure140connected to the first back bonding pad150may be electrically connected to the back bonding pad560of the package substrate500.

The first back bonding pad150may be provided with at least one of a control signal, a power signal or a ground signal for operating the first to fourth semiconductor chips100to400from the outside. The first back bonding pad150may be provided with a data signal to be stored in the first to fourth semiconductor chips100to400from the outside. The first back bonding pad150may provide data stored in the first to fourth semiconductor chips100to400to the outside.

The first back bonding pad150may include at least one selected from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In some implementations, the first back bonding pad150may include copper (Cu).

The first front bonding pad160electrically connected to the first through electrode130may be formed on the upper face of the first semiconductor substrate110. The first front bonding pad160may be electrically connected to the first wiring structure140through the first through electrode130. The first front bonding pad160may be made of the same material as the first back bonding pad150. Although not shown, an upper passivation layer may be formed on the upper face of the first semiconductor substrate110to surround a part of the side face of the first through electrode130.

The first front bonding pad160may be connected to the second back bonding pad250. The first front bonding pad160may be in contact with the second back bonding pad250. For example, a second surface160S2of the first front bonding pad may be in contact with a first surface250S1of the second back bonding pad.

The first front bonding pad160may be bonded to the second back bonding pad250. The first front bonding pad160may be directly bonded to the second back bonding pad250. The first front bonding pad160and the second back bonding pad250may be coupled by a high-temperature annealing process.

The first front bonding pad160may be disposed on the second surface100S2of the first semiconductor chip. The second surface100S2of the first semiconductor chip may be opposite to the second semiconductor chip200. For example, the second surface100S2of the first semiconductor chip may face the first surface200S1of the second semiconductor chip. The first front bonding pad160may be disposed inside the first bonding insulation film610.

The second semiconductor chip200may be electrically connected to the first semiconductor chip100by bonding the first front bonding pad160and the second back bonding pad250. For example, the first through electrode130of the first semiconductor chip100and the second wiring structures240of the second semiconductor chip200may be electrically connected through the bonded first front bonding pad160and second back bonding pad250.

The first front bonding pad160and the second back bonding pad250may be surrounded by the first bonding insulation film610. A side face of the first front bonding pad160and a side face of the second back bonding pad250may be covered with the first bonding insulation film610.

The first front bonding pad160and the second back bonding pad250may be bonded with a bonding thickness THB. The bonding thickness THB may refer to a thickness between the first surface160S1of the first front bonding pad and the second surface250S2of the second back bonding pad. The first surface160S1of the first front bonding pad may be a face on which the first front bonding pad160is in contact with the second surface100S2of the first semiconductor chip. The second surface250S2of the second back bonding pad may be a face on which the second back bonding pad250is in contact with the first surface200S1of the second semiconductor chip.

The bonding thickness THB may be smaller than a thickness TH242of the second connection wiring pad. However, the implementations are not limited thereto. For example, the bonding thickness THB may be greater than a thickness TH242of the second connection wiring pad.

A width of the first front bonding pad160may be the same as a width of the second back bonding pad250. For example, a side face of the first front bonding pad160and a side face of the second back bonding pad250may be disposed on the same plane. The width of the first front bonding pad160may be greater than the width of the first through electrode130.

The thickness of the first front bonding pad160may be the same as the thickness of the second back bonding pad250. The thickness between the first surface160S1of the first front bonding pad and the second surface160S2of the first front bonding pad may be the same as the thickness between the first surface250S1of the second back bonding pad and the second surface250S2of the second back bonding pad.

The second semiconductor chip200may be disposed on the first semiconductor chip100. The second semiconductor chip200may be electrically connected to the first semiconductor chip100through the first front bonding pad160and the second back bonding pad250which are disposed between the first semiconductor chip100and the second semiconductor chip200.

The second semiconductor chip200may include a second semiconductor substrate210, a second semiconductor element layer220, a second through electrode230, a second wiring structure240, a second connection wiring pad242, a second peripheral wiring pad244, a second back bonding pad250, and a second front bonding pad260.

The second semiconductor element layer220may include a second connection wiring pad242and a second peripheral wiring pad244. The second connection wiring pad242and the second peripheral wiring pad244may be disposed inside the second semiconductor element layer220.

The second connection wiring pad242and the second peripheral wiring pad244may be spaced apart from each other. For example, the second connection wiring pad242and the second peripheral wiring pad244may be spaced apart from each other in a horizontal direction at the same level. For example, the second connection wiring pad242and the second peripheral wiring pad244may be spaced apart from each other in the first direction X.

The second connection wiring pad242and the second peripheral wiring pad244may have different thicknesses from each other. The thickness TH242of the second connection wiring pad may be greater than the thickness TH244of the second peripheral wiring pad. The thickness TH242of the second connection wiring pad may refer to a thickness between the first surface242S1and the second surface242S2of the second connection wiring pad. The thickness TH244of the second peripheral wiring pad may refer to a thickness between the first surface244S1and the second surface244S2of the second peripheral wiring pad.

The thickness TH244of the second peripheral wiring pad may be, for example, 50% or less of the thickness TH242of the second connection wiring pad. The thickness TH242of the second connection wiring pad may be greater than the bonding thickness THB at which the second back bonding pad250and the first front bonding pad160are bonded.

The second surface242S2of the second connection wiring pad and the second surface244S2of the second peripheral wiring pad may be disposed on the same plane.

The second surface242S2of the second connection wiring pad may be a face that is opposite to the first surface242S1of the second connection wiring pad. The first surface242S1of the second connection wiring pad may be a face that is in contact with the second back bonding pad250. The first surface242S1of the second connection wiring pad may face the first semiconductor chip100. The second wiring structure240may be in contact with the second surface242S2of the second connection wiring pad. The second wiring structure240may be connected to the second surface242S2of the second connection wiring pad.

The second surface244S2of the second peripheral wiring pad may be a face that is opposite to the first surface244S1of the second peripheral wiring pad. The first surface244S1of the second peripheral wiring pad may face the first semiconductor chip100. The first surface244S1of the second peripheral wiring pad may be covered with the second insulating film225inside the second semiconductor element layer220. The second wiring structure240may be in contact with the second surface244S2of the second peripheral wiring pad. The second wiring structure240may be connected to the second surface244S2of the second peripheral wiring pad.

The first surface242S1of the second connection wiring pad and the first surface244S1of the second peripheral wiring pad may not be disposed on the same plane. For example, on the basis of the second surface100S2of the first semiconductor chip, the first surface242S1of the second connection wiring pad may be disposed below the first surface244S1of the second peripheral wiring pad. The first surface242S1of the second connection wiring pad and the first surface244S1of the second peripheral wiring pad may have a level difference.

The first surface242S1of the second connection wiring pad may not be covered with the second insulating film225inside the second semiconductor element layer220. The first surface242S1of the second connection wiring pad may not overlap the second insulating film225inside the second semiconductor element layer220. For example, the second insulating film225may not be disposed between the second connection wiring pad242and the second back bonding pad250. The first surface242S1of the second connection wiring pad and the second surface250S2of the second back bonding pad may be in direct contact with each other. Only the side faces of the second connection wiring pad242may be surrounded by the second insulating film225inside the second semiconductor element layer220.

The first surface244S1of the second peripheral wiring pad may be covered with the second insulating film225inside the second semiconductor element layer220. The first surface244S1of the second peripheral wiring pad may overlap the second insulating film225inside the second semiconductor element layer220. The second insulating film225may be disposed between the second peripheral wiring pad244and the first bonding insulation film610. The second peripheral wiring pad244may be surrounded by the second insulating film225inside the second semiconductor element layer220not only on the side face but also on the first surface244S1.

The second back bonding pad250may be disposed on the second semiconductor element layer220. The second back bonding pad250may be electrically connected to the second wiring structure240inside the second semiconductor element layer220. The second back bonding pad250may be electrically connected to the second through electrode230through the second wiring structure240.

The second back bonding pad250may be disposed on the first surface200S1of the second semiconductor chip. For example, the first surface200S1of the second semiconductor chip may face the second surface100S2of the first semiconductor chip. The second back bonding pad250may be disposed inside the first bonding insulation film610.

The second back bonding pad250may be disposed on the second connection wiring pad242. The second back bonding pad250may be connected to the second connection wiring pad242. The second back bonding pad250may be in contact with the second connection wiring pad242. For example, the second surface250S2of the second back bonding pad may be in contact with the first surface242S1of the second connection wiring pad.

The second back bonding pad250may not be connected to the second peripheral wiring pad244. The second back bonding pad250may not be in contact with the second peripheral wiring pad244. The second back bonding pad250may be spaced apart from the second peripheral wiring pad244. The second surface250S2of the second back bonding pad may be spaced apart from the first surface244S1of the second peripheral wiring pad.

The second back bonding pad250may be electrically connected to the first front bonding pad160. The second back bonding pad250may be in contact with the first front bonding pad160. The second back bonding pad250may be bonded to the first front bonding pad160. The second back bonding pad250and the first front bonding pad160may be directly bonded. The second back bonding pad250and the first front bonding pad160may be coupled through a high-temperature annealing process.

The second back bonding pad250and the first front bonding pad160may be bonded to electrically connect the second semiconductor chip200to the first semiconductor chip100. For example, since the second back bonding pad250and the first front bonding pad160is in contact with each other, the second connection wiring pad242and the second wiring structure240connected to the second back bonding pad250may be electrically connected to the first through electrode130of the first semiconductor chip100.

A third semiconductor chip300may be disposed on the second semiconductor chip200. The third semiconductor chip300may include a third semiconductor substrate310, a third semiconductor clement layer320, a third through electrode330, a third wiring structure340, a third connection wiring pad342, a third peripheral wiring pad344, a third back bonding pad350, and a third front bonding pad360.

The fourth semiconductor chip400may be disposed on the third semiconductor chip300. The fourth semiconductor chip400may include a fourth semiconductor substrate410, a fourth semiconductor clement layer420, a fourth wiring structure440, a fourth connection wiring pad442, a fourth peripheral wiring pad444, and a fourth back bonding pad450. The fourth semiconductor chip400may not include a through electrode and a front bonding pad, unlike the first to third semiconductor chips100to300.

The second to fourth semiconductor chips200to400may be substantially the same as or similar to the first semiconductor chip100. Therefore, detailed explanation of the second to fourth semiconductor chips200to400will not be provided.

The package substrate500may be, for example, a printed circuit board (PCB), a ceramic substrate or an interposer. Alternatively, the package substrate500may be a semiconductor chip including a semiconductor element. The package substrate500may function as a support substrate for a semiconductor package. For example, the first to fourth semiconductor chips100to400described above may be stacked on the package substrate500.

The package substrate500may include a substrate body510, a lower pad520, and a package bonding pad560. The lower pad520may be disposed on a lower face of the substrate body510. The package bonding pad560may be disposed on an upper face of the substrate body510. The package bonding pad560may be disposed inside the upper passivation layer511. The upper passivation layer511may be disposed on the upper face of the substrate body510.

An external connecting terminal540may be disposed below the package substrate500. The external connecting terminal540may be disposed on the lower pad520. For example, the external connecting terminal540may be a solder ball or a bump.

The bonding insulation films610,620, and630may be disposed between the first to fourth semiconductor chips100to400. The bonding insulation films610,620, and630may include, for example, silicon oxide. The side faces of the bonding insulation films610,620, and630may be disposed on the same plane as the side faces of the first to fourth semiconductor chips100to400. That is, in the first direction X, the widths of the bonding insulation films610,620, and630may be equal to the widths of the first to fourth semiconductor chips100to400.

The first bonding insulation film610may fill the space between the first semiconductor chip100and the second semiconductor chip200. The first bonding insulation film610may surround the first front bonding pad160and the second back bonding pad250disposed between the first semiconductor chip100and the second semiconductor chip200.

The second bonding insulation film620may fill the space between the second semiconductor chip200and the third semiconductor chip300. The second bonding insulation film620may surround the second front bonding pad260and the third back bonding pad350, which are disposed between the second semiconductor chip200and the third semiconductor chip300.

The third bonding insulation film630may fill the space between the third semiconductor chip300and the fourth semiconductor chip400. The third bonding insulation film630may surround the third front bonding pad360and the fourth back bonding pad450, which are disposed between the third semiconductor chip300and the fourth semiconductor chip400.

The molding film700may be formed on the package substrate500. The molding film700may cover the first to fourth semiconductor chips100to400. The molding film700may include, for example, a polymer such as resin. For example, the molding film700may include, but not limited to, EMC (Epoxy Molding Compound).

FIGS.3to7are diagrams illustrating another example of a semiconductor package. For convenience of explanation, the explanation will focus on points that are different from those explained with reference toFIGS.1and2.

Referring toFIG.3, the bonding thickness THB and the thickness TH242of the second connection wiring pad may be the same. The thickness between the first surface160S1of the first front bonding pad and the second surface250S2of the second back bonding pad may be the same as the thickness TH242of the second connection wiring pad.

Referring toFIG.4, the width of the first front bonding pad160may not be constant. For example, the first front bonding pad160may have a reversed trapezoidal cross-section. The width of the first surface160S1of the first front bonding pad may be smaller than the width of the second surface160S2of the first front bonding pad. That is, the width of the first front bonding pad160may increase from the first semiconductor chip100toward the second semiconductor chip200.

The width of the second back bonding pad250may not be constant. For example, the second back bonding pad250may have a trapezoidal cross-section. The width of the first surface250S1of the second back bonding pad may be greater than the width of the second surface250S2of the second back bonding pad. That is, the width of the second back bonding pad250may decrease from the first semiconductor chip100toward the second semiconductor chip200.

The second surface160S2of the first front bonding pad and the first surface250S1of the second back bonding pad may have the same width. The first surface160S1of the first front bonding pad and the second surface250S2of the second back bonding pad may have the same width.

Referring toFIG.5, the second surface160S2of the first front bonding pad and the first surface250S1of the second back bonding pad may not have the same width. For example, the width of the second surface160S2of the first front bonding pad may be greater than the width of the first surface250S1of the second back bonding pad.

The first surface160S1of the first front bonding pad and the second surface250S2of the second back bonding pad may not have the same width. For example, the width of the first surface160S1of the first front bonding pad may be greater than the width of the second surface250S2of the second back bonding pad.

Referring toFIG.6, the first front bonding pads160and the second back bonding pads250may be alternately disposed. For example, the center of the first front bonding pad160and the center of the second back bonding pad250may not coincide with each other, but may be shifted from each other.

Referring toFIG.7, the thickness of the first front bonding pad160may not be equal to the thickness of the second back bonding pad250. The thickness of the first front bonding pad160may be smaller than the thickness of the second back bonding pad250. AlthoughFIG.7only shows that the thickness of the first front bonding pad160is smaller than the thickness of the second back bonding pad250, the implementations are not limited thereto. For example, the thickness of the first front bonding pad160may be greater than the thickness of the second back bonding pad250.

FIG.8is a diagram illustrating another example of a semiconductor package.FIG.9is an example enlarged view showing a portion Q ofFIG.8. For convenience of explanation, the explanation will focus on points that are different from those explained with reference toFIGS.1and2.

Referring toFIGS.8and9, a semiconductor package includes a first semiconductor chip100, a second semiconductor chip200, and a molding film700.

The second semiconductor chip200may be disposed on the first semiconductor chip100. The width of the second semiconductor chip200may be smaller than the width of the first semiconductor chip100. The side face of the second semiconductor chip200may not be disposed on the same plane as the side face of the first semiconductor chip100. The molding film700may cover the second semiconductor chip200. The molding film700may cover a side face of the second semiconductor chip200.

The first semiconductor element layer120may be disposed on the upper face of the first semiconductor substrate110. The first semiconductor clement layer120may include a fifth connection wiring pad182. The fifth connection wiring pad182may be disposed inside the first semiconductor element layer120.

The first front bonding pad160may be disposed on the first semiconductor element layer120. The first front bonding pad160may be electrically connected to the first wiring structure140.

The first front bonding pad160may be disposed on the fifth connection wiring pad182. The first front bonding pad160may be in contact with the fifth connection wiring pad182.

The fifth connection wiring pad182may be connected to the first wiring structure140and the first front bonding pad160. The fifth connection wiring pad182may be in contact with the first wiring structure140and the first front bonding pad160. The first surface182S1of the fifth connection wiring pad may be in contact with the first wiring structure140. The fifth connection wiring pad182may electrically connect the first wiring structure140to the first front bonding pad160. The second surface182S2of the fifth connection wiring pad may be in contact with the first surface160S1of the first front bonding pad.

The fifth connection wiring pad182may be surrounded by the first insulating film125inside the first semiconductor element layer120. The side face of the fifth connection wiring pad182may be surrounded by the first insulating film125inside the first semiconductor element layer120. The first surface182S1and the second surface182S2of the fifth connection wiring pad182may not be covered with the first insulating film125. The first surface182S1and the second surface182S2of the fifth connection wiring pad182may not overlap the first insulating film125. The fifth connection wiring pad182may include aluminum.

The first front bonding pad160may be disposed between the fifth connection wiring pad182and the first back bonding pad250. The first back bonding pad250may be disposed between the first front bonding pad160and the second connection wiring pad242.

FIG.10is a diagram illustrating another example of a semiconductor package. For convenience of explanation, points different from those described with reference toFIGS.8and9will be mainly explained.

Referring toFIG.10, the first semiconductor chip100may include a fifth peripheral wiring pad184. The fifth peripheral wiring pad184may be spaced apart from the fifth connection wiring pad182. For example, the fifth peripheral wiring pad184may be spaced apart from the fifth connection wiring pad182in the first direction X.

The fifth peripheral wiring pad184may not be in contact with the first front bonding pad160. The fifth peripheral wiring pad184may be spaced apart from the first front bonding pad160. The first front bonding pad160may not be disposed on the fifth peripheral wiring pad184.

The fifth connection wiring pad182and the fifth peripheral wiring pad184may have different thicknesses from each other. A thickness TH182of the fifth connection wiring pad may be greater than a thickness TH184of the fifth peripheral wiring pad. The thickness TH184of the fifth peripheral wiring pad may be, for example, 50% or less of the thickness TH182of the fifth connection wiring pad.

The first surface182S1of the fifth connection wiring pad and the first surface184S1of the fifth peripheral wiring pad may be disposed on the same plane.

The first surface182S1of the fifth connection wiring pad may be a face on which the first wiring structure140is in contact with the fifth connection wiring pad182. The first surface184S1of the fifth peripheral wiring pad may be a face on which the first wiring structure140is in contact with the fifth peripheral wiring pad184.

The second surface182S2of the fifth connection wiring pad and the second surface184S2of the fifth peripheral wiring pad may not be disposed on the same plane. For example, on the basis of the second surface100S2of the first semiconductor chip, the second surface182S2of the fifth connection wiring pad may be disposed above the second surface184S2of the fifth peripheral wiring pad. The second surface182S2of the fifth connection wiring pad and the second surface184S2of the fifth peripheral wiring pad may have a level difference.

The second surface182S2of the fifth connection wiring pad may be a face that is opposite to the first surface182S1of the fifth connection wiring pad. The second surface182S2of the fifth connection wiring pad may be a face that is in contact with the first front bonding pad160. The second surface182S2of the fifth connection wiring pad may face the second semiconductor chip200.

The second surface184S2of the fifth peripheral wiring pad may be a face that is opposite to the first surface184S1of the fifth peripheral wiring pad. The second surface184S2of the fifth peripheral wiring pad may face the second semiconductor chip200. The second surface184S2of the fifth peripheral wiring pad may be covered with the first insulating film125inside the first semiconductor element layer120.

InFIG.10, although the thickness TH182of the fifth connection wiring pad is shown as being equal to the thickness TH242of the second connection wiring pad, the implementation is not limited thereto. For example, the thickness TH182of the fifth connection wiring pad may be smaller than the thickness TH242of the second connection wiring pad. InFIG.10, although the thickness TH184of the fifth peripheral wiring pad is shown as being equal to the thickness TH244of the second peripheral wiring pad, the implementation is not limited thereto. For example, the thickness TH184of the fifth peripheral wiring pad may be smaller than the thickness TH244of the second peripheral wiring pad.

FIG.11is a diagram illustrating another example of a semiconductor package.FIG.12is an example enlarged view showing a portion R ofFIG.11. For convenience of explanation, the explanation will focus on points that are different from those explained with reference toFIGS.1and2.

Referring toFIGS.11and12, the semiconductor package includes a package substrate500, a first semiconductor chip100, a second semiconductor chip200, and an interposer800.

The package substrate500may be mounted on a motherboard of an electronic device or the like. For example, the package substrate500may be mounted on a motherboard or the like of an electronic device through the external connecting terminal540. The package substrate500may be, but not limited to, a ball grid array (BGA) substrate.

The external connecting terminal540may be, for example, but not limited to, a solder bump. The external connecting terminal540may have various shapes such as a land, a ball, a pin, and a pillar. Of course, the number, spacing, placement form, and the like of the external connecting terminals540are not limited to those shown in the drawings, and may vary depending on the design.

The interposer800may be disposed on the upper face of the package substrate500. The interposer800may be, but not limited to, a silicon interposer or an organic interposer. The interposer800may include a lower face and an upper face that are opposite to each other. The lower face of the interposer800may face an upper face of the package substrate500. The interposer800may be used to facilitate the connection between the package substrate500, the first semiconductor chip100, and the second semiconductor chip200, and alleviate warpage of the semiconductor package.

The interposer800may include an interposer substrate810, an interposer back bonding pad850, and an interposer front bonding pad860. The interposer back bonding pad850and the interposer front bonding pad860may each be used to electrically connect the interposer800to other constituent elements. For example, the interposer back bonding pad850may be exposed from the lower face of the interposer substrate810. The interposer front bonding pad860may be exposed from the upper face of the interposer substrate810. The interposer back bonding pad850and the interposer front bonding pad860may include, but not limited to, metallic materials such as copper (Cu) or aluminum (Al).

The interposer back bonding pad850may be in contact with the package the bonding pad560. The interposer back bonding pad850may be directly bonded to the package bonding pad560. The interposer back bonding pad850may be electrically connected to the package bonding pad560. The interposer back bonding pad850and the package bonding pad560may be bonded to electrically connect the interposer800and the package substrate500.

The interposer front bonding pad860may be in contact with the first back bonding pad150and the second back bonding pad250. The interposer front bonding pad860may be directly bonded to the first back bonding pad150and the second back bonding pad250. The interposer front bonding pad860may be electrically connected to the first back bonding pad150and the second back bonding pad250. The first semiconductor chip100and the interposer800may be electrically connected by bonding the interposer front bonding pad860and the first back bonding pad150. The second semiconductor chip200and the interposer800may be electrically connected by bonding the interposer front bonding pad860and the second back bonding pad250.

The first semiconductor chip100and the second semiconductor chip200may be mounted on the upper face of the interposer800. The first semiconductor chip100and the second semiconductor chip200may be spaced apart from each other, and disposed on the upper face of the interposer800. The first semiconductor chip100and the second semiconductor chip200may each be an integrated circuit (IC) in which hundreds to millions of or more semiconductor elements are integrated in a single chip.

In some implementations, first semiconductor chip100may be a logic semiconductor chip. For example, the first semiconductor chip100may be, but not limited to, an application processor (AP), such as a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), an FPGA (Field-Programmable Gate Array), a digital signal processor, an encryption processor, a micro processor, a micro controller, and an ASIC (Application-Specific IC).

In some implementations, the second semiconductor chip200may be a memory semiconductor chip. For example, the second semiconductor chip200may be a volatile memory such as a DRAM (dynamic random access memory) or a SRAM (static random access memory), or a non-volatile memory such as a flash memory, a PRAM (phase-change random access memory), a MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory) or a RRAM (Resistive Random Access Memory).

As an example, the first semiconductor chip100may be an ASIC such as a GPU, and the second semiconductor chip200may be a stack memory, such as a high bandwidth memory (HBM). Such a stack memory may have a form in which a plurality of integrated circuits are stacked. The stacked integrated circuits may be electrically connected to each other through a TSV (Through Silicon Via) or the like.

In some implementations, the second semiconductor chips200may be disposed in the larger numbers than the first semiconductor chips100. For example, a plurality of second semiconductor chips200may be disposed around the first semiconductor chip100. For example, two second semiconductor chips200may be disposed on each side of the first semiconductor chip100.

The first semiconductor chip100may include a first back bonding pad150. The first back bonding pad150may be used to electrically connect the first semiconductor chip100to other constituent elements. For example, the first back bonding pad150may be exposed from the lower face of the first semiconductor chip100.

The first back bonding pad150may be in contact with the interposer front bonding pad860. The first back bonding pad150may be disposed on the interposer front bonding pad860. The first back bonding pad150may be bonded to the interposer front bonding pad860. Accordingly, the first semiconductor chip100may be electrically connected to the interposer800.

The second semiconductor chip200may include a second back bonding pad250. The second back bonding pad250may be used to electrically connect the second semiconductor chip200to other constituent elements. For example, the second back bonding pad250may be exposed from the lower face of the second semiconductor chip200.

The second back bonding pad250may be in contact with the interposer front bonding pad860. The second back bonding pad250may be disposed on the interposer front bonding pad860. The second back bonding pad250may be bonded to the interposer front bonding pad860. The second semiconductor chip200may be electrically connected to the interposer800accordingly.

The first back bonding pad150and the second back bonding pad250may each include a metal material such as, but not limited to, copper (Cu) or aluminum (Al). In some implementations, the first back bonding pad150and the second back bonding pad250may each include copper (Cu).

The package substrate500may include a sixth connection wiring pad582and a sixth peripheral wiring pad584. The sixth connection wiring pad582and the sixth peripheral wiring pad584may be connected to the package substrate wiring530. The sixth connection wiring pad582and the sixth peripheral wiring pad584may be spaced apart from each other.

The sixth connection wiring pad582may be connected to the package bonding pad560. The sixth connection wiring pad582may be in contact with the package bonding pad560. The sixth connection wiring pad582may be disposed on the package bonding pad560. The upper face of the sixth connection wiring pad582may be in contact with the lower face of the package bonding pad560. The sixth connection wiring pad582may electrically connect the package substrate wiring530and the package bonding pad560.

The sixth peripheral wiring pad584may not be connected to the package bonding pad560. The sixth peripheral wiring pad584may not be in contact with the package bonding pad560. The upper face of the sixth peripheral wiring pad584may not be in contact with the lower face of the package bonding pad560. The sixth peripheral wiring pad584may be spaced apart from the package bonding pad560. An upper face of the sixth peripheral wiring pad584may be spaced apart from a lower face of the package bonding pad560.

A thickness of the sixth connection wiring pad582may be greater than a thickness of the sixth peripheral wiring pad584. The lower face of the sixth connection wiring pad582may be disposed on the same plane as the lower face of the sixth peripheral wiring pad584. The upper face of the sixth connection wiring pad582may be disposed above the upper face of the sixth peripheral wiring pad584on the basis of the lower face of the package substrate500. The upper face of the sixth connection wiring pad582and the upper face of the sixth peripheral wiring pad584may have a step difference.

FIG.13is a diagram illustrating another example of a semiconductor package. For convenience of explanation, the explanation will focus on points that are different from those explained with reference toFIGS.1and2.

Referring toFIG.13, the semiconductor package includes a fifth semiconductor chip20. The fifth semiconductor chip20may be spaced apart from the stacked first to fourth semiconductor chips100to400. The fifth semiconductor chip20may be disposed on the interposer800. The fifth semiconductor chip20may be spaced apart from the first to fourth semiconductor chips100to400stacked on the interposer800. The fifth semiconductor chip20may be covered with a molding film700. A side face of the fifth semiconductor chip20may be covered with the molding film700.

The fifth semiconductor chip20may include a fifth back bonding pad25, a seventh connection pad42, and a seventh peripheral wiring pad44.

The fifth back bonding pad25may be connected to the seventh connection wiring pad42. The fifth back bonding pad25may be in contact with the seventh connection wiring pad42. The fifth back bonding pad25may not be connected to the seventh peripheral wiring pad44. The fifth back bonding pad25may not be in contact with the seventh peripheral wiring pad44.

The fifth back bonding pad25may be in contact with the interposer front bonding pad860. The fifth back bonding pad25may be bonded to the interposer front bonding pad860. The fifth semiconductor chip50and the interposer800may be electrically connected by bonding the fifth back bonding pad25and the interposer front bonding pad860.

The interposer front bonding pad860may be connected to the interposer wiring840. The interposer front bonding pad860may be connected to the fifth back bonding pad25and the first back bonding pad150. The interposer front bonding pad860may be in contact with the fifth back bonding pad25and the first back bonding pad150.

A connecting bump870may be disposed between the interposer back bonding pad850and the package bonding pad560. However, the implementations are not limited thereto. For example, the interposer back bonding pad850and the package bonding pad560may be in direct contact with each other.

FIGS.14to27are diagrams illustrating intermediate steps of an example of a method for fabricating a semiconductor package.

Referring toFIG.14, the first semiconductor element layer120may be formed on the first semiconductor substrate110.

The first through electrode130may be formed inside the first semiconductor substrate110. The first wiring structure140connected to the first through electrode130may be formed inside the first semiconductor element layer120.

Referring toFIGS.15and16, a first portion142P1of the first connection wiring pad and the first peripheral wiring pad144may be formed.

The first portion142P1of the first connection wiring pad and the first peripheral wiring pad144may be formed inside the first portion125aof the first insulating film of the first semiconductor element layer120. The first portion125aof the first insulating film may be formed on the first wiring structure140. The first portion142P1of the first connection wiring pad and the first peripheral wiring pad144may be connected to the first wiring structure140.

The first portion142P1of the first connection wiring pad and the first peripheral wiring pad144may have the same thickness. The first surface142PS1of the first portion of the first connection wiring pad and the first surface144S1of the first peripheral wiring pad may be disposed on the same plane.

Referring toFIG.17, the first connection wiring pad142may be formed inside the first insulating film125.

Specifically, referring toFIG.18, a second portion125bof the first insulating film may be formed on the first portion142P1of the first connection wiring pad and the first peripheral wiring pad144. A first connection wiring pad recess142R which penetrates the second portion125bof the first insulating film and exposes the first portion142P1of the first connection wiring pad may be formed. The first surface142PS1of the first portion142P1of the first connection wiring pad may be exposed by the first connection wiring pad recess142R. The first surface144S1of the first peripheral wiring pad may be covered with the second portion125bof the first insulating film.

Next, referring toFIG.19, a second portion142P2of the first connection wiring pad may be formed inside the first connection wiring pad recess (142R ofFIG.18). The second portion142P2of the first connection wiring pad may fill the first connection wiring pad recess (142R ofFIG.18).

The second portion142P2of the first connection wiring pad may be formed on the first portion142P1of the first connection wiring pad. The second portion142P2of the first connection wiring pad may cover the first surface (142PS1ofFIG.18) of the first portion142P1of the first connection wiring pad.

Subsequently, referring toFIG.20, the second portion (142P2ofFIG.19) of the first connection wiring pad that covers the upper face of the second portion (125bofFIG.19) of the first insulating film is removed, and the first connection wiring pad142and the first peripheral wiring pad144may be formed.

The first surface142S1of the first connection wiring pad may be exposed from the first insulating film125. The first surface144S1of the first peripheral wiring pad may be covered with the first insulating film125. The first insulating film125may include a first portion (125aofFIG.19) and a second portion (125bofFIG.19).

Referring toFIGS.21and22, the first back bonding pad150may be formed.

The first back bonding pad150may be formed on the first connection wiring pad142. The first back bonding pad150may be in contact with the first connection wiring pad142.

The first passivation layer121may be formed on the first insulating film125. The first passivation layer121may cover the first insulating film125. The first back bonding pad150may be formed inside the first passivation layer121.

Referring toFIGS.23and24, the first semiconductor chip100may be bonded onto the package substrate500.

When the first semiconductor chip100is bonded onto the package substrate500, an annealing process may be performed. For example, when the first semiconductor chip100is bonded onto the package substrate500, heat may be applied. When annealed, the first back bonding pad150may expand. For example, the first surface150S1of the first back bonding pad may protrude beyond the first surface121S1of the first passivation layer.

The first back bonding pad150disposed on the first connection wiring pad142which is thicker than the first peripheral wiring pad144may protrude further than the first passivation layer121. For example, the first connection wiring pad142may also expand due to annealing. Therefore, the first back bonding pad150disposed on the first connection wiring pad142may expand relatively further than the first passivation layer121.

The first passivation layer121that covers the first peripheral wiring pad144, which is thinner than the first connection wiring pad142, may expand less than the first back bonding pad150. For example, the first peripheral wiring pad144may also expand due to annealing, but the first passivation layer121, which is not in direct contact with the first peripheral wiring pad144having a small thickness, may expand relatively less than the first back bonding pad150. Since the first insulating film125is disposed on the first peripheral wiring pad144, expansion of the first peripheral wiring pad144due to annealing may not affect the first passivation layer121.

Referring toFIG.25, the first back bonding pad150and the package bonding pad560may be bonded.

Since the first back bonding pad150expands relatively further than the first passivation layer121, the first back bonding pad150and the package bonding pad560may be stably bonded.

On the other hand, for example, referring toFIG.24, if the first surface144S1of the first peripheral wiring pad is disposed on the same plane as the first surface142S1of the first connection wiring pad, since the first peripheral wiring pad144expands due to annealing, the first passivation layer121may also expand. In such a case, since an extent to which the first surface150S1of the first back bonding pad protrudes beyond the first surface121S1of the first passivation layer decreases, the first back bonding pad150may not be stably bonded to the package bonding pad560.

Since the first surface144S1of the first peripheral wiring pad is disposed above the first surface142S1of the first connection wiring pad on the basis of the first surface121S1of the first passivation layer, even if the first peripheral wiring pad144expands due to the annealing, it is possible to reduce the extent to which the first passivation layer121expands due to the expansion of the first peripheral wiring pad144. Therefore, the first surface150S1of the first back bonding pad protrudes relatively further than the first surface121S1of the first passivation layer, and the first back bonding pad150may be stably bonded to the package bonding pad560.

Referring toFIG.26, the second semiconductor chip200may be bonded onto the first semiconductor chip100.

The first front bonding pad160may be formed inside the first portion610aof the first bonding insulation film disposed on the upper face of the first semiconductor chip100. The second back bonding pad250may be formed inside the second portion610bof the first bonding insulation film disposed on the lower face of the second semiconductor chip200.

The first front bonding pad160and the second back bonding pad250may be in direct contact with each other to bond the first semiconductor chip100and the second semiconductor chip200.

Similarly, the first semiconductor chip100and the second semiconductor chip200may be annealed when bonded. The second back bonding pad250disposed on the second connection wiring pad242, which is thicker than the second peripheral wiring pad244, may protrude relatively further than the second portion610bof the first bonding insulation film due to the annealing. Therefore, the second back bonding pad250may be stably bonded to the first front bonding pad160.

Referring toFIG.27, the third semiconductor chip300and the fourth semiconductor chip400may be bonded onto the second semiconductor chip200.

Next, referring toFIG.1, a molding film700that covers the first to fourth semiconductor chips100to400may be formed.

FIGS.28to33are diagrams illustrating intermediate steps of another example of a method for fabricating a semiconductor package. For convenience of explanation, the explanation will focus on the points that are different from those explained with reference toFIGS.14to27. For reference,FIG.28is a diagram showing steps afterFIG.14.

Referring toFIGS.14,28, and29, the first connection wiring pad142and a first pre-peripheral wiring pad144P may be formed.

The first connection wiring pad142and the first pre-peripheral wiring pad144P may be formed inside the first insulating film125of the first semiconductor element layer120. The first connection wiring pad142and the first pre-peripheral wiring pad144P may be connected to the first wiring structure140.

The first connection wiring pad142and the first pre-peripheral wiring pad144P may have the same thickness. The first surface142S1of the first connection wiring pad and the first surface144PS1of the first pre-peripheral wiring pad may be disposed on the same plane.

Referring toFIG.30, the first peripheral wiring pad144may be formed inside the first insulating film125.

Specifically, referring toFIG.31, a mask layer129may be formed on the first insulating film125. The mask layer129may cover the first connection wiring pad142.

A first peripheral wiring pad trench144T which penetrates the mask layer129and exposes the first pre-peripheral wiring pad144P may be formed. The first surface144PS1of the first pre-peripheral wiring pad may be exposed by the first peripheral wiring pad trench144T. The first surface142S1of the first connection wiring pad may be covered with the mask layer129.

Next, referring toFIG.32, the upper part of the first pre-peripheral wiring pad (144P ofFIG.31) may be removed inside the first peripheral wiring pad trench144T. For example, the upper part of the first pre-peripheral wiring pad (144P ofFIG.31) may be etched inside the first peripheral wiring pad trench144T.

The first peripheral wiring pad144may be formed while removing the upper part of the first pre-peripheral wiring pad (144P ofFIG.31). The first surface144S1of the first peripheral wiring pad may be located below the first surface142S1of the first connection wiring pad on the basis of the first semiconductor substrate110.

Next, referring toFIG.33, the first insulating film125may be formed inside the first peripheral wiring pad trench144T. The first insulating film125may fill the first peripheral wiring pad trench144T. The first insulating film125may cover the first surface144S1of the first peripheral wiring pad inside the first peripheral wiring pad trench144T.

The explanation of the steps afterFIG.33is the same as the explanation ofFIGS.21to27, and will therefore be omitted.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the described implementations without substantially departing from the principles of the present disclosure. Therefore, the disclosed implementations are used in a generic and descriptive sense only and not for purposes of limitation.