Memory device and method thereof

A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to electronic devices and more particularly to electronic devices having memories.

DESCRIPTION OF THE RELATED ART

Semiconductor memories can be categorized as volatile memories and non-volatile memories. A specific type of non-volatile memory is referred to as a “flash memory,” which can be erased on a given-area basis with a reduced writing time.FIG. 1illustrates a sense amplifier portion of a memory in accordance with the prior art that can be used to read a flash memory, such as a NAND flash memory.

During a pre-charge portion of a read access, the two switches illustrated inFIG. 1are closed to so that the bit line BL, which has a capacitance CL, is charged to a precharge voltage V_pc while the sense node SN is charged to VCC. During a discharge portion of the read access the switches are open and a fixed gate voltage Vg is applied to the gate of the transistor of the sense amplifier ofFIG. 1at the same time that the bit cell, which is represented by the current source having current IC, is selected. The voltage Vg is set equal to V_pc−V_delta−Vt, where V_pc is the pre-charge voltage, V_delta is a fixed voltage, and Vt is the threshold voltage of the transistor ofFIG. 1. The current ICrepresents the current that is passed through a selected memory cell when selected. Therefore, the current ICcan represent the current through a selected memory cell that is in either a conductive or non-conductive state. Note that the term “conductive state” is used with respect to a memory cell to indicate that the memory cell is configured to be in its more conductive state when selected, as opposed to the term “non-conductive state” which is used to indicate a memory cell is configured to be in its less conductive state when selected.

In order for the memory cell to be detected as being in its conductive state, it is necessary to remove sufficient charge from the bit line BL during a read operation to turn on the sense amplifier transistor, thereby allowing the sense node SN ofFIG. 1to discharge sufficiently to allow a low voltage to be detected by a sense device (not illustrated). Therefore, the necessary time for the sense amplifier transistor to be turned on is defined by T=CL*Vdelta*1/Ic. However, since the gate voltage Vg is a fixed voltage, changes in Vt of the transistor ofFIG. 2will result in the transistor turning on at a time that varies with temperature, which results in the node SN being discharged by a variable amount of time as well. As semiconductor devices are scaled to smaller geometries, it can become increasingly difficult to select an appropriate value of Vg that will work over a wide rage of temperature ranges.

DETAILED DESCRIPTION

In accordance with a specific embodiment of the present disclosure, a sense node of a sense amplifier and a bit line of a memory array are charged during a pre-charge portion of a first time period. A first gate signal, which is dependent upon temperature, is provided to the control gate of a sense transistor of the sense amplifier during a discharge portion of the first time period. For a given state of a memory cell being read, the sense node of the sense amplifier can discharge for a period of time that is based upon a voltage of the gate signal. For example, if a memory cell being read is in its conductive state, the sense transistor will turn on for a period of time during the read cycle that is sufficiently long to substantially discharge the sense node, whereby a low-voltage logic signal is generated at the sense node. Alternatively, if a bit cell being read is in its non-conductive state, the sense transistor will either not turn on at all during the discharge portion, or turn on for a period of time during the discharge portion that is not sufficiently long to substantially discharge the sense node, whereby a high-voltage logic signal is remains at the sense node. Specific embodiments of the present disclosure will be better understood with respect toFIGS. 2-10.

FIG. 2illustrates an electronic device100having a non-volatile memory at an integrated circuit portion105that includes a temperature dependent bias generator110, a sense amplifier121, a sense amplifier122, and a memory array130. The electronic device100can be data processor, such as a computer or integrated circuit that includes the integrated circuit portion105.

The sense amplifier121and the sense amplifier122are two of a plurality of sense amplifiers connected to the temperature dependent bias generator110via a node115. The plurality of sense amplifiers is connected to memory array130. For example, sense amplifier121is connected to the memory array130through a node referred to as a bit line, and labeled “BLO,” and sense amplifier122is connected to memory array130through a bit line labeled “BLn.” It will be appreciated that “n” represents an integer indicating the number of bit lines associated with the memory array130.

During operation, the temperature dependent bias generator110generates a voltage labeled “Vg_sa” that is provided to the sense amplifier121and to the sense amplifier122. The voltage Vg_sa is dependent upon the temperature at a location of the integrated circuit portion105where the temperature dependent bias generator110resides. Therefore, the value of Vg_sa will change as the temperature at this location changes. For example, a rise in temperature can result in Vg_sa having a lower voltage. By varying the voltage Vg_sa with temperature as the voltage threshold of transistors at the sense amplifiers121and122that control the discharge of their respective sense nodes also change with temperature, the amount of discharge variance at the sense nodes during a discharge cycle can be reduced. This reduction in discharge variance at a sense node, when compensated as described herein, is expected to be one-half the discharge variance over temperature when the voltage Vg_sa is not temperature compensated. This reduction in discharge variance allows a sense node of a sense amplifier to be discharged during a read access in a manner that is referred to herein as being substantially independent of temperature. This variance, being substantially independent of temperature, results in an amount of time from the start of a discharge portion of a read cycle until a time a transistor of the sense amplifier begins discharging the sense node that is referred to as being substantially the same for all operating temperatures, for a give logic state. Therefore, the duration of time during which a sense node is discharged for a given logic state is substantially the same for all operating temperatures. It will be appreciated that discharging a sense node by substantially the same amount facilitates accurate detection of logic levels at the sense nodes.

Each of the bit lines BL0-BLn of memory array130is connected to corresponding sense amplifiers121-122. For example, as illustrated inFIG. 2, bit line BL0connects sense amplifier121to portion131of memory array130that includes memory cells connected to the bit line BL0. A specific memory cell being read during a read cycle is represented as current source1311inFIG. 2and has a current IC. The current ICrepresents the current that is passed through a selected memory cell when selected. Therefore, the current ICcan represent the current through a selected memory cell that is either in a conductive or non-conductive state.

FIG. 3illustrates a combination block and circuit diagram of a portion of a sense amplifier. Sense amplifiers121-122ofFIG. 3can be implanted based on the sense amplifier ofFIG. 2. Specifically,FIG. 3illustrates a transistor221, a switch222, a switch223, and a latch224.

Transistor221includes a first current electrode connected to a sense node225, a second current electrode connected to a bit line labeled BLX, and a control electrode connected to receive the signal Vg_sa. The switch222has a first current electrode connected to a voltage reference node at a pre-charge voltage labeled “V_pc,” a second current electrode connected to the second current electrode of transistor221, and a control electrode connected to receive a control signal labeled “CTL_pc” that is capable of opening or closing switch222to selectively electrically connect the first current electrode to the second current electrode. Switch223includes a first current electrode connected to a voltage reference node at a voltage reference VCC, a second current electrode connected to the sense node225, and a control electrode connected to receive the control signal CTL_pc that is capable of opening or closing a switch223to selectively electrically connect the first current electrode to the second current electrode. A latch224has an input connected to the sense node225, and provides at its output, Dx, an inverted representation of a signal at its input in response to a signal labeled “RD” being asserted. The latch224can be an edge-triggered latch or a level-sensitive latch. For purposes of discussion herein, latch224is assumed to be a positive edge triggered latch. Operation of the device ofFIG. 2, and more particularly operation of the sense amplifier ofFIG. 3in response to receiving the temperature dependent signal Vg_sa during a read access will be better understood with reference toFIG. 4.

FIG. 4illustrates a timing diagram including waveforms311-317in accordance with a specific embodiment of the present disclosure. Waveform311represents signal CTL_pc, which represents the control signal received at the control electrodes of the switches222and223illustrated atFIG. 3. Waveform311is asserted to close switches222and223during a pre-charge portion of a period of time referred to as a read access cycle. Waveform312represents signal Vg_sa, which is received at the control gate of transistor221of each sense amplifier ofFIG. 3, and is asserted during a discharge portion of a read access period during which a memory cell is selected. Waveform313represents a signal SN0, which is the voltage at the sense node225of the sense amplifier121ofFIG. 2. Waveform314represents a signal SN1, which is the voltage at the sense node of a second sense amplifier (not illustrated) of device100ofFIG. 2. Waveform315represents a signal RD which controls when latch224of each sense amplifier latches data at its respective sense node. Waveform316represents a signal D0, which represents the logic output from the latch224associated with the sense amplifier121ofFIG. 2. Waveform317represents a signal Dn, which represents the logic output from a sense amplifier122.

The timing diagram ofFIG. 4includes two time periods: timing period320, and timing period330. These timing periods are also referred to as read access cycles during which first and second read accesses are preformed.

During a pre-charge portion321of time period320, the sense node and bit line associated with each sense amplifier are charged in response to the assertion of signal CTL_pc. As a result, during the pre-charge portion321of the first time period320, the voltage of the bit lines will be charged to the voltage V_pc, while the voltage at the sense nodes225will be charged to the voltage Vcc. For example, referring toFIGS. 2 and 3, it will be appreciated that the asserted signal CTL_pc during portion321causes the switches222and223to be closed. When closed the sense nodes225are connected to the voltage Vcc and the waveforms313and314representing the voltage SN0at sense node225of sense amplifier121and the waveform314, the voltage SN1at sense node225of an adjacent sense amplifier, respectively, are pre-charged to Vcc. Similarly, the bit lines of other sense amplifiers including sense amplifier122will be charged to V_pc during the precharge portion321. The read signal, RD, is negated during the pre-charge portion321of time period320. The output signals D0and D1maintain their previous state, which can be a logic level high (H) or a logic level low (L), during the pre-charge portion321of the first time period320.

A discharge portion322of time period320occurs following the pre-charge portion321. The discharge portion322can begin at or after completion of the pre-charge portion321. As specifically illustrated inFIG. 4, there can be a short period of time between completion of the pre-charge portion321and the beginning of the discharge portion at time322.

During the discharge portion322, a read voltage is applied to a memory cell of each bit line being read that results in the bit cell being in a conductive state, referred to as an “on state”, or a in a non-conductive state, referred to as an “off-state.” When a memory cell is in an on state, the current Icis greater than when the memory cell is in an off state, thereby discharging its respective bit line at a faster rate. The transistor121of a sense amplifier will remain off during discharge portion322until the voltage at the bit line is discharged to a voltage that is one Vt below the voltage Vg_sa. When this occurs, the transistor121turns on and begins to discharge the sense node225.

In operation, during discharge portion322, a temperature dependent gate signal Vg_sa is asserted to bias the transistor221of each sense amplifier, such as sense amplifiers121and122. The value of the voltage of signal Vg_sa is based upon a temperature at a location of the integrated circuit100where the temperature dependent bias generator100resides. In one embodiment, the signal Vg_sa is continuously updated based upon temperature, in other embodiments the value Vg_sa can be periodically updated based upon temperature and latched for use by the system. In one embodiment, a change in temperature that lowers the voltage threshold of a transistor, such as transistor221of a sense amplifier, will result in generating Vg_sa at a lower voltage to ensure transistor221turns on at substantially the same time relative the beginning of the discharge portion322over the change in temperatures. Therefore, if a temperature at the temperature dependent bias generator110were to increase, thereby causing a lowering of the voltage threshold of a transistor within the temperature dependent bias generator110, the signal Vg_sa would be lowered, as compared to the cooler temperature, to bias transistor221. It will be appreciated that if the signal Vg_sa where fixed, i.e., not temperature dependent, an increase in temperature that lowers the Vt of a transistor221would result in transistor221turning on at a later time as temperature increases.

During portion326of the discharge portion322, the signal SN0, which represents a voltage at the sense node225of sense amplifier121, discharges in response to transistor221being turned on. As previously discussed, transistor221is turned on when bit line BL0discharges to a voltage that is one Vt below Vg_sa. The discharge time326represents the time that transistor221is turned on during discharge portion326. Therefore, the discharge time326is long enough to allow sufficient current to flow from the sense node225to discharge sense node225to a voltage less than a voltage350to facilitate the latch224being able to detect a low logic level at its input.

During portion327of the discharge portion322, the signal SN1, which represents a voltage at the sense node of the sense amplifier122, discharges in response to its transistor221being turned on. As previously discussed, transistor221is turned on when bit line BLn discharges to a voltage that is one Vt below Vg_sa. The discharge time327represents the time that transistor221is turned on in response to a corresponding memory cell that is being read being in its non-conductive state. Therefore, the discharge time326, if any, is short enough to prevent the voltage at the sense node225from dropping below voltage350prior to the charge at the sense node being read. This allows the latch224of sense amplifier121to detect a high logic level at its input when the read signal RD is asserted.

The discharge time326represents a discharge time of a sense node through a corresponding transistor221connected to a bit line BL0that is being discharged to ground through a memory cell in its conductive state. Because Vg_sa is dependent upon temperature, the discharge time326is substantially independent of temperature. The discharge time327represents a discharge time of a sense node through a corresponding transistor222that is in turn connected to a bit line BLn being discharged to ground through a memory cell in its non-conductive state. Because Vg_sa is dependent upon temperature, the discharge time327is substantially independent of temperature. As used herein with respect to discharge time, the term “substantially independent of temperature” is intended to mean that the time that a sense node is discharged during a discharge cycle, for a give state, varies less over operating temperatures than the variance of the discharge time the same sense node over the same temperature if controlled by a fixed gate voltage. Therefore, by varying the voltage level of signals VG_sa0with temperature, the time when the sense node SN0begins discharging remains substantially the same, relative the beginning of time period320, for all temperatures. As a result, the sense node SN0will discharge by substantially the same amount, for a given logic state independent of temperature.

The read signal RD remains negated for at least an initial portion of the discharge portion322of time period320. Data out signals D0and D1are not affected during the discharge period320prior to assertion of the read signal RD. A read pulse329is generated at the read signal RD during the first time period320. In response to assertion of the read pulse329, a first logic state of the sense amplifier is determined based upon the charge at its sense node225. It will be appreciated that the charge at the sense node is based upon an amount of charge remaining at the sense node at the time of the pulse329is asserted. Therefore, the voltage of the sense node is based upon the amount of charge removed from the sense node during the discharge portion of the first time period that occurred prior to the read pulse329. As a result, the signal SN0, which is less than the reference voltage350at the time pulse329is asserted, is latched, resulting in the high-level logic signal (H) at output D0. Conversely, the signal SN1, which is greater than the reference voltage350at the time the pulse329is asserted, results in a logic level low being latched.

During the second timing period330, the ICportion105ofFIG. 2operates in a similar manner as during first timing period320. However, during the discharge portion322of timing period330the temperature dependent bias generator110generates the signal Vg_sa0based upon a different temperature than during time period320. Therefore, during the discharge portion322of the timing period330signal Vg_sa0has an asserted voltage value V2that is different than the voltage value V1of Vg_sa0that is asserted during the discharge portion322of the first timing portion320. This variation in the voltage value of Vg_sa0compensates for the variation in operation of the sense amplifiers due to a similar change in temperature. Therefore, assuming the data values being read from memory cells at the sense amplifiers do not change between the first timing period320and the second timing period330, the portion326of the second timing period330has a duration that is substantially the same as the portion326of the first timing period320at sense amplifier121, and the portion327of the second timing portion331has a duration that is substantially the same as the portion327of the first timing portion321, at the sense amplifier adjacent to sense amplifier121.

FIG. 5illustrates an electronic device1001having a non-volatile memory at an integrated circuit portion1051that is similar to the integrated circuit portion105ofFIG. 2. In particular, IC portion1051includes a temperature dependent bias generator110, a sense amplifier121, a sense amplifier122, and a memory array130similar to those previously described. In addition, IC portion1051ofFIG. 5includes a second temperature dependent bias generator1101that operates separate from, but in a similar manner as, temperature dependent bias generator110. Identically numbered elements inFIG. 5operate as previously discussed. The electronic device1001can be data processor, such as a computer or integrated circuit that includes the integrated circuit portion1051having the specifically illustrated devices.

The use of a plurality of temperatures bias generators as illustrated allows for the IC portion1051to compensate for temperature differences across a common integrated circuit substrate. Therefore, in the illustrated embodiment, sense amplifiers121-1211have their respective sense amplifier transistors biased by signal Vg_sa0, which is transmitted over node1151, and sense amplifiers1221-122have their respective sense amplifier transistors biased by signal Vg_sa1, which is transmitted over node1152. It will be appreciated that the closer a temperature bias generator is to a sense amplifier that it biases, the more likely the temperature bias generator and the sense amplifier being biased will be exposed to a similar temperature, thereby improving compensation. While two temperature bias generators110and1101are shown inFIG. 5, it will be appreciated that additional temperature bias generators can be implemented. For example, a separate temperature bias generator could be implemented for each sense amplifier.

The timing diagram ofFIG. 6is similar to the timing diagram ofFIG. 4, and applies to the device1001ofFIG. 5. Identically numbered elements inFIG. 6function as previously described.

In addition to the elements previously illustrated and described, the timing diagramFIG. 6includes waveform3122and waveform3141. Waveform312continues to represent signal Vg_sa0, which is received at the control gate of a respective transistor of each of the sense amplifiers121-1211, and is asserted during a discharge portion of a read access period. Waveform3122represents signal Vg_san, which is received at the control gate of a respective transistor of each of the sense amplifiers1221-122, and is asserted during a discharge portion of a read access period. Waveform3141represents a signal SNn, which is the voltage at the sense node of the sense amplifier122of device100ofFIG. 2in response to the signal Vg_san.

During the first time period320, signal Vg_sa0is the same as that previously described. However, signal Vg_sa1has a different voltage level, V3, than Vg_sa0due to its being located at a different physical location of IC portion1051having a different temperature. As a result, the portion3271of the first time period320is different than the portion327as discussed previously atFIG. 4. Since the sense amplifier122inFIG. 5is closer to the temperature dependent bias generator1102than sense amplifier122was to temperature dependent bias generator inFIG. 3, it is likely that portion3271represents a discharge time of the sense node that compensates sense amplifier122for temperature more accurately than temperature dependent bias generator110did as previously discussed with respect toFIG. 4.

During the second time period330ofFIG. 6, the voltage value of signal Vg_sa1has changed to V4. However, the portion3271remains substantially the same due to the temperature compensation provide by temperature dependent bias generator1101as previously discussed.

FIG. 7illustrates a specific implementation of a temperature dependent bias generator that can be implemented as a previously described temperature dependent bias generator. The temperature dependent bias generator ofFIG. 7includes a voltage offset generator413, a buffer414, a transistor411, a current reference412, and a select module416.

The voltage offset generator413has a positive terminal connected to a voltage reference node that is operable to provide voltage V_pc, and a negative terminal. Buffer414has an input connected to the negative terminal of the voltage offset generator413and an output. Buffer414can be specifically implemented using an operational amplifier having its output connected to its negative input. Transistor411includes a first current electrode, a second current electrode connected to the output of the buffer414, and a control electrode connected to the first current electrode. Current reference412includes a first terminal connected to a voltage reference node that is operable to provide a voltage such as Vcc, and a second terminal connected to the first current electrode of transistor411. Select module416includes a first input connected to the first current electrode of transistor411, a second input connected to the reference voltage (GND), a control input connected to receive a signal SEL to selectively electrically connect one of the first input or the second input to an output to provide signal Vg—sa.

During operation, the buffer414can operate as a unity gain buffer to provide a voltage, V_pc-Vdelta, at its output that matches the voltage at its input. The voltage Vdelta is a design parameter selected to control when a sense amplifier transistor, such as transistor211ofFIG. 2, turns on to discharge a corresponding sense node. Current reference412provides a bias current at transistor411to ensure the desired voltage Vgen can be maintained. Transistor411can be matched to transistor221of the sense amplifiers to ensure that a temperature that affects the sense amplifiers affects the temperature dependent bias generator in a similar manner. Unlike the prior art, which uses a fixed voltage to bias the sense amplifiers, a temperature change at transistor411will cause a change in the Vt of transistor411, which in turn will cause the value of Vgen to vary as previously discussed. The signal SEL is asserted at select module416to selectively electrically connect the temperature dependent signal Vgen to the output terminal of select module416.

FIG. 8illustrates another specific implementation of a temperature dependent bias generator that can be implemented as a previously described temperature dependent bias generator. The temperature dependent bias generator ofFIG. 8includes a voltage offset generator423, an amplifier424, a transistor421, and a current reference422, and a select module416.

The voltage offset generator423has a positive terminal connected to a voltage reference node that is operable to provide voltage V_pc, and a negative terminal. Amplifier424has a positive input connected to the negative terminal of the voltage offset generator424and an output. Transistor421includes a first current electrode connected to a voltage reference node that is operable to provide a voltage reference Vcc, a second current electrode connected to the negative input of amplifier buffer424, and a control electrode connected to the output of buffer424. Current reference422includes a first terminal connected to the second current electrode of transistor421, and a second terminal connected to a voltage reference node that is operable to provide a voltage reference, such as ground, during operation. Select module426includes a first input connected to the first current electrode of transistor421, a second input connected to the reference voltage (GND), a control input connected to receive a signal SEL to selectively electrically connect one of the first input or the second input to an output to provide signal Vg—sa.

During operation, transistor421is part of feed back path that includes amplifier424such that the signal Vg_sa varies as the gate to source voltage of transistor421varies. As previously discussed, the voltage Vdelta is a design parameter selected to define the voltage Vgen at the first current electrode of the transistor424. Current reference412provides a bias current to transistor421to ensure a desired voltage Vgen can be maintained during operation. Transistor421can be matched to transistor221of the sense amplifiers to ensure a temperature that affects the sense amplifier affects the temperature dependent bias generator in a similar manner. The signal SEL is asserted at select module426to selectively electrically connect the temperature dependent signal Vgen to the output terminal of select module426.

FIG. 9illustrates a block diagram of a system500that can be used to implement an integrated circuit containing the elements described with respect toFIGS. 2 and 5.

FIG. 9illustrates a control module512and a memory core520. Control module510includes a row decode module512connected to the set of row interconnects540, a column decode/sense amp module516connected to the set of column interconnects530, and a voltage control module514connected to the row decode module512and the column decode module/sense amp module516through interconnects511and512. One of the interconnects513can include an interconnect that provides a signal generated from a temperature dependent bias generated as described above.

Memory core520includes a plurality of bit lines that delineate columns of NAND strings within memory core520, including bit line230, bit line240, and bit line242. Each bit line of the plurality of bit lines has a plurality of NAND strings, for example, connected thereto. For example, NAND strings2300and2301are connected to bit line230, NAND strings2400and2401are connected to bit line240, and NAND strings2420and2421are connected to bit line242.

During operation, the row decode module512decodes OPERATION/CONTROL signals, and ADDRESS signals, to determine the output signals to be provided at row interconnects540for each NAND string of the memory core520. Similarly, the column decode module516decodes OPERATION/CONTROL signals, ADDRESS signals, and DATA signals, to determine the output signals to be provided at column interconnects530for each bit line of the memory core520. Based upon an operation being performed, the voltage control module514provides appropriate voltages, including Vg_sa as described above, to the row decode module512and to the column decode/sense amp module516. In accordance with a specific aspect of the present disclosure, memory control module510can perform read, write, and erase operations at NAND storage cells, which are also referred to as NAND storage gates, and at the select gates of memory core520.

FIG. 10illustrates a schematic representation of an embodiment of a memory block referred t as a NAND string. The NAND string ofFIG. 6includes transistors611,612, and621-624. Transistors621-624represent a string of NAND storage cells, also referred to as storage cells NAND[0. . . N], whereby NAND storage cells[0-N] form a string of NAND storage cells, while transistors611and612represent select gates. Storage cell NAND[0], i.e., transistor621, and storage cell NAND[N], i.e., transistor624, represent the two outer NAND storage cells of the string of NAND storage cells, while storage cells NAND[1. . . N−1] represent the interior storage cells of the string of NAND storage cells. The storage cell NAND[0] is the NAND storage cell of the sting of NAND storage cells most closely coupled to the local bit line interconnect LBLO[0]. During a read access, one of the storage cells611-623has its gate biased to a read voltage, RD, while the remaining storage cells have are turned on. The resulting current through the storage cell being read is modeled as a current source atFIG. 2.

In the foregoing specification, principles of the invention have been described above in connection with specific embodiments. However, one of ordinary skill in the art appreciates that one or more modifications or one or more other changes can be made to any one or more of the embodiments without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense and any and all such modifications and other changes are intended to be included within the scope of invention.

Any one or more benefits, one or more other advantages, one or more solutions to one or more problems, or any combination thereof have been described above with regard to one or more specific embodiments. However, the benefit(s), advantage(s), solution(s) to problem(s), or any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced is not to be construed as a critical, required, or essential feature or element of any or all the claims.

Other embodiments, uses, and advantages of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The specification and drawings should be considered exemplary only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof.