System and method for pattern correction in e-beam lithography

The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Photolithography systems are used to pattern a semiconductor wafer. When semiconductor technology continues progressing to circuit layouts having smaller feature sizes, a lithography system with higher resolution is need to image an IC pattern with smaller feature sizes. An electron-beam (e-beam) system is introduced for lithography patterning processes as the electron beam has wavelengths that can be tuned to very short, resulting in very high resolution.

To enhance the imaging effect when a design pattern is transferred to a wafer, an electron proximity correction (EPC) to minimize the proximity effect is indispensable. The design pattern is adjusted to generate an image on the wafer with improved resolution. However, along with the progress of the lithography patterning, some other imaging effects are unavoidable and those imaging factors may be pattern related. Those other imaging factors are not fully considered and not effectively corrected or efficiently corrected. Therefore, it is desirable to have a system and a method for improved e-beam lithography in IC fabrication to address the above issue.

DETAILED DESCRIPTION

FIG. 1illustrates a system100for performing pattern correction in e-beam lithography according to one or more embodiments of the present disclosure. The system100includes a design entity110that includes one or more computers and storage media for providing an integrated circuit (IC) layout design. The IC layout design may contain a plurality of semiconductor features. The IC layout design may be generated by a computer as a computer file, for example as a graphic database system (GDS) type file or as an open artwork system interchange standard (OASIS) type file. The GDS or OASIS files are database files used for data exchange of IC layout artwork. For example, these files may have binary file formats for representing planar geometric shapes, text labels, as well as other layout information of the IC layout. The GDS or OASIS files may each contain multiple layers. The GDS or OASIS files may be used to reconstruct the IC layout artwork, and as such can be transferred or shared between various fabrication tools.

The design entity110provides the IC layout design as a computer file to a pattern processing module120. In some embodiments, the pattern processing module120includes a computer for processing the design data. The computer includes a processor, memory, and input/output with which to perform the steps and operations discussed later in the present disclosure. The pattern processing module120can be distributed in various locations, and can physically be included in whole or in part with the design entity110or a different facility such as a fabrication facility130discussed below. The computer file including the IC layout design may be stored in a computer readable media on the one or more computers. Some common forms of computer readable media includes, for example, floppy disk, flexible disk, hard disk, magnetic tape, any other magnetic medium, CD-ROM, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, carrier wave, or any other medium from which a computer is adapted to read.

The pattern processing module120processes the design data of the IC layout design, and then provides the processing result of such operations to the fabrication facility130. In the present example, the fabrication facility130supports a lithography process to be performed in a semiconductor processing-related facility. The fabrication facility130can be a mask-making facility, an engineering facility, or part of a lithography system itself.

Still referring toFIG. 1, the pattern processing module120includes a pattern split process122, a model fitting process124, and a pattern correction process128. In some embodiments, the pattern processing module120includes an optical proximity correction (OPC) and/or an electron proximity correction (EPC). One or more processes of the pattern separation122, model fitting124, and pattern correction128may be performed by the processor, memory, and input/output of the computer, and the data files may be stored in the computer readable media.

The pattern split process122may include dividing the patterns in the IC layout design into different pattern types. In some embodiments, the patterns may be divided based on the polygon shape of the patterns.FIG. 2Aillustrates various exemplary polygon shapes of the patterns200according to some embodiments. For examples, a ratio between the length (l) and the width (w) of the square pattern202may be in a range from about 0.5:1 to about 1.5:1. A ratio between l and w of the trench pattern204may be greater than about 3:1. A ratio between l and w of the slot pattern206is in a range from about 2:1 to about 3:1. In some embodiments, the patterns may also be divided based on cell types. For example, one or more memory cell arrays may include repeating structures and may be presented periodically in the patterns, therefore the memory cell arrays with similar structures may be categorized as one pattern type. In some embodiments, the patterns may also be divided based on IP type and/or device type. For example, the patterns included in a static random-access memory (SRAM) may include a plurality of cells and the SRAM be categorized as one pattern type.

In some embodiments, the pattern split process122may be performed manually by engineers. For example, the pattern types may be predetermined and marked by different reference marks and/or different computer-aided design (CAD) layers.

In some embodiments, the pattern split process122may also be performed automatically by the computer based on the results of the model fitting124and/or pattern correction128of the IC layout design. For example, all the patterns in the IC layout design may be fitted using one or more models, and the patterns in the IC layout design can then be divided into different pattern types based on the error sensitivity of the fitting results.

After the patterns are split into a plurality of pattern types, a plurality of models126may be selected for the plurality of pattern types respectively. In some embodiments, the plurality of models126may be selected based on processing and/or manufacturing data from previous e-beam lithography and wafer manufacturing processes. The plurality of models126may be used to compensate for image errors, such as those that can arise from diffraction, interference, or other process effects to provide enhanced resolution and precision of the patterns.

Equation (1) illustrates the intensity distribution/Beam Blur (BS) of an electron beam incident on one point (x, y) of a wafer surface using Gaussian approximation:

BS=12⁢πσ2⁢ⅇ-(x2+y2)2⁢σ2(1)
where σ is a scattering coefficient.

Equation (2) is a Point Spread Function (PSF) illustrating the response of the incident electron beam on the surface of the wafer using double Gaussian approximation considering various scattering effects:

PSF=1π⁡(1+η)⁢(1α2⁢ⅇ-(x2+y2)α2+ηβ2⁢ⅇ-(x2+y2)β2)(2)
where α is a forward scattering coefficient, β is a backward scattering coefficient, and η is related to the ratio between a forwarding scattering component and a backward scattering component. In some embodiments, other factors may also be needed to compensate for the image errors of the incident electron beam on the wafer surface. Those factors may include, for example, acceleration voltage of the electron beam, resist material to be formed on the wafer, pattern types, wafer types, etc. Therefore the PSF may include other forms as expressed in equations (3)-(4) using triple Gaussian approximation or multiple Gaussian approximation, for example:

The beam intensity of the incident electron beam considering various scattering effects can be expressed as PSFeffin equation (5) as below:

The energy intensity distribution function I(xi,yi) of the incident electron beam when further considering the surrounding patterns M can be expressed in equation (6) as convolution of the beam blur BS, PSFifor each pattern type i decided by the pattern split process122, and pattern type M distributed near the incident electron beam:

The plurality of models126may take into account various factors, such as scattering effects as shown in equations (1)-(6). In some examples, the plurality of models126may further consider aerial image contrast, depth of focus (“DOF”), other suitable factors, or combinations thereof. The plurality of models126may also be based on actual processing parameters of the IC manufacturer. The processing parameters may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process.

The model fitting process124may include using the previous e-beam lithography and wafer manufacturing data and the IC design layout data from the design entity110to determine a plurality of selected models126for the plurality of pattern types respectively. The model fitting process124may be performed to the subset of patterns in each pattern type decided in the pattern split process122separately. When the errors of the fitting results are within a predetermined range, the selected models126may be accurate and can be used in the pattern correction process128. When the errors of the fitting results are beyond a predetermined range, the selected models126may be modified or adjusted in order to receive an improved fitting result. In some examples, when the errors of the fitting results are still beyond a predetermined range after some modification and/or adjustment to the models, the patterns may be re-split into a different group of pattern types, and the models may be re-selected for the model fitting process124.

After the model fitting process124, a plurality of models126including the coefficients may be determined for the plurality of pattern types respectively. In some examples, the plurality of models126may include similar equations used for the plurality of pattern types respectively in the model fitting process124, but the coefficients, such as α, β, η, for each pattern type may be determined to be different from one pattern type to another. In some examples, the plurality of models126may include different equations such as double Gaussian approximation, triple Gaussian approximation, or suitable multiple Gaussian approximation, used for different pattern types to achieve better fitting results.FIG. 2Billustrates an exemplary table250showing coefficients α, β, η are decided to be different for respective pattern types. For example, the coefficients αsq, βsq, ηsqfor square pattern202may be different from the coefficients αs1, βs1, ηs1for slot pattern206.

The pattern correction128includes shape correction and/or dose correction. The shape correction may include modifying IC pattern features and adding assist features based on refined models126or design rules such that, after a lithography process using the corrected IC design layout, a final pattern on a wafer is improved with enhanced resolution and precision. The shape correction may include e-beam proximity effects corrections, critical dimension (CD) modifications associated with loading effects related to pattern density, and/or geometry modifications. The dose correction may include adjusting the e-beam exposure dose based on refined models126such that, various patterns are able to be imaged on the resist layer with higher contrast or increased contrast. When all patterns are written with a same dose, some IC features, especially critical features, do not have enough contrast. The dose correction may be applied only to certain patterns or a subset of the patterns in the IC design layout for increased imaging contrast and imaging resolution. In a particular example, the exposure dose is changed by changing the pixel density of the IC features.

After the model fitting process124, in some embodiments at the pattern correction process128, the IC design layout may be first corrected using a rule based correction. The rule based correction may include adding features, such as scattering bars, serif, and/or hammerheads to the IC design layout according to optical models or rules such that, after a lithography process, a final pattern on a wafer is improved with enhanced resolution and precision. Then a simulation process at the pattern correction process128is performed to the correct IC layout.

In some embodiments at the pattern correction process128, the IC design layout may be first corrected using a model based correction, for example, using the determined plurality of models126from the model fitting process124. Then a simulation process at the pattern correction process128may be performed to the corrected IC design layout.

In some embodiments at the pattern correction process128, a simulation process may be first performed to the IC design layout, then the IC design layout is corrected using the plurality of models126to the corresponding pattern types.

The simulation process at the pattern correction process128may include creating a simulated manufactured device. The simulated manufactured device includes simulated contours of all or a portion of the IC design layout. When the simulated device is not satisfactory in pattern shape and/or dose, the patterns may be further corrected to reduce the errors. In some embodiments, when the simulated device based on the corrected patterns is not satisfactory even after pattern corrections, the plurality of models126used for model fitting process124may be adjusted, and the model fitting process124may be performed again until the simulated device based on the corrected patterns becomes satisfactory. In some embodiments, when the simulated device is not satisfactory even after pattern corrections and model adjustments, the pattern split process122may be adjusted to improve the fitting results.

It is to be understood that the pattern split process122, the model fitting process124, and the simulation process in pattern correction process128may be performed repeatedly in any suitable order to refine the plurality of models126until the fitting results are satisfactory. The refined plurality of models126may then be used for the pattern correction process128. After the simulation process, pattern correction128may make appropriate corrections to the IC design layout to compensate for the variations or errors associated with the e-beam lithography system (e.g., e-beam system300ofFIG. 3) to be used in forming the IC design layout on the wafer.

It should be understood that the above description of the pattern processing120has been simplified for the purposes of clarity, and the pattern processing120may include additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules, and a retarget process (RET) to modify the IC design layout to compensate for limitations in lithographic processes used by IC manufacturer. Additionally, the one or more processes applied to the IC design layout during the pattern processing120may be executed in a variety of different orders.

FIG. 3illustrates a schematic diagram of an electron beam lithography system300according to one or more embodiments of the present disclosure. The e-beam lithography system300may be included in the fabrication facility130of system100inFIG. 1. The electron beam lithography system300includes a source302, a condenser lens column304, a pattern generator (PG)306, an electric signal generator (ESG)308, a projection lens column312, a wafer stage314, and a wafer316disposed on the wafer stage314. It is understood that other configurations and inclusion or omission of various items in the system300may be possible. The system300is an example embodiment, and is not intended to limit the present invention beyond what is explicitly recited in the claims.

The source302may include an electron source to provide an electron beam. In some embodiments, the source302includes a cathode, an anode, and an aperture. The source302provides a plurality of electron beams emitted from a conducting material by heating the conducting material to a very high temperature, where the electrons have sufficient energy to overcome a work function barrier and escape from the conducting material (thermionic sources), or by applying an electric field (potential) sufficiently strong that the electrons tunnel through the work function barrier (field emission sources).

The condenser lens column304guides the radiation beams from the source302to the pattern generator306. In some embodiments, the radiation beams are parallel to each other after passing through the condenser lens column304. In some embodiments, the condenser lens column304may include a plurality of electromagnetic apertures, electrostatic lenses, and electromagnetic lenses.

The pattern generator306is coupled through fiber optics to an electric to optical signal converter that is coupled to the electric signal generator308and to the IC design entity110and the pattern processing module120. In some embodiments, the pattern generator306may include a mirror array plate, at least one electrode plate disposed over the mirror array plate, and at least one insulator sandwiched between the mirror array plate and the electrode plate or between the electrode plates. The mirror array plate includes a plurality of electric mirrors which are simply static metallic pads of the size between nanometers and micrometers. Each pad constitutes a pixel. The reflectivity of the mirrors is switched on and off by the electric signal from the electric signal generator308. The electrode plate may include a plurality of lenslets, and the insulator layer may include an insulator. The pattern generator306provides patterning radiation beams310according to a corrected IC design layout by reflecting or absorbing a radiation beam guided to each lenslet by the condenser lens column304. The electric signal generator308connects to mirrors embedded into the mirror array plate of the pattern generator306and to the IC design entity110and the pattern processing module120. The electric signal generator308turns mirrors on or off according to the corrected IC design layout by reflecting or absorbing a radiation beam.

The projection lens column312guides the patterning radiation beams310generated from the pattern generator36to the wafer316secured on the wafer stage314. In some embodiments, the projection lens column312includes a plurality of electromagnetic apertures, electrostatic lenses, electromagnetic lenses, and deflectors. The wafer stage314secures the wafer316by electrostatic force and provides accurate movement of the wafer316in X, Y and Z directions during focusing, leveling, and exposing the wafer316in the electron beam lithography system300. In some embodiments, the wafer stage314includes a plurality of motors, roller guides, and tables.

In some embodiments, a high electric potential is applied between the cathode and the anode at the source302, which accelerates the electrons towards and through the aperture. The value of the applied electric potential determines the energy level of the electron beams leaving the aperture. The energy of the electron beams reduces as the electron beams travel toward the pattern generator306. The pixels in the pattern generator306are programmed to be substantially zero or a few volts according to the signal from the optical fibers. Those pixels that are substantially zero in voltage receive the incoming electrons from the source302. The other pixels that carry a negative voltage of a few volts will repel the incoming electrons so that they travel through the optical column312towards the wafer316. The optical column312forms an image reduced in size and accelerates the electrons to a voltage that ranges from a few kilo volts to hundreds of kilo volts to reach the wafer316secured on the wafer stage314.

The electron beam lithography system300is operated under a high vacuum condition. Therefore, the electron beam lithography system300may include one or more vacuum pumps, such as a mechanical pump for a low vacuum and an ion pump for a high vacuum. In some embodiments, the electron beam lithography system300may also include a computer with a processor, a memory, and an I/O interface. The computer may be coupled to the source302, the PG306, the ESG308, the wafer stage114, the IC design entity110, and/or the pattern processing module120, for performing one or more of the operations described herein.

FIG. 4is a flowchart of a method400for performing pattern processing using system100according to some embodiments of the present disclosure. Method400starts from process401for splitting a plurality of patterns received from IC design layout into a plurality of pattern types. The plurality of patterns of the IC design layout may be received from the design entity110ofFIG. 1. The IC design layout is to be processed and used in patterning the one or more material layers on the wafer using the e-beam lithography system300ofFIG. 3. In various examples, the IC design layout may define STI features, gate electrodes, source/drain features, contact features, metal lines or via features, other suitable features, and combinations thereof. In some examples, the IC design layout may include pattern features with various polygon shapes as shown inFIG. 2A.

At process401, the plurality of patterns may be split by the pattern split process122of the pattern processing module120. In some embodiments, the plurality of patterns in the IC design layout may be predetermined into different types based on polygon shapes of the patterns as shown inFIG. 2A. The patterns may also be predetermined into different types based on cell type, IP type, and/or device type. The different types of IC patterns may be marked by different reference marks and/or different computer-aided design (CAD) layers prior to perform pattern fitting and correction processes. In some embodiments, the patterns may also be split based on the model fitting results and/or the pattern correction results. For example, when the errors of the model fitting process124and/or the simulation of the pattern correction128is out of an acceptable range, the patterns may be split based on the error sensitivity associated with model fitting process124and/or the simulation of the pattern correction process128. For example, a subset of pattern features with less fitting error from the pattern fitting may be assigned into a group, and a subset of pattern features with greater fitting error from the pattern fitting may be assigned into another group. The pattern splitting process at process401may be performed manually by engineers, or automatically by a computer with a processor.

Method400proceeds to process402by selecting a plurality of models126for the plurality of pattern types respectively. In some embodiments, the plurality of models126may be selected based on the e-beam lithography data and the wafer manufacturing data from previous processes. The plurality of models126may take into account various factors, such as scattering effects as shown in equations (1)-(6). In some examples, the plurality of models126may further consider aerial image contrast, depth of focus (“DOF”), other suitable factors, or combinations thereof. The plurality of models126may also be based on actual processing parameters of the IC manufacturer.

Method400proceeds to process404by performing model fitting process124using the plurality of models126selected at process402for the corresponding pattern types. The model fitting process404may be performed using real manufacturing data from previous e-beam lithography process and IC wafer manufacturing process, and the data from the IC design layout received from the design entity110. As shown inFIG. 4, processes404,406,407, and408may be included in the pattern correction process124.

Method400proceeds to process406by determining whether the error of the fitting result at process404is within a predetermined range. When the fitting error is not within the predetermined range, method400proceeds to process407by modifying the models. For example, the coefficients of the models for the corresponding pattern types may be adjusted, or models using different equations may be chosen for the corresponding pattern types to reduce the errors of the fitting results. Following process407, process404is performed again to model fittings using the modified models. In some examples, when the error of the fitting result is still out of the predetermined range even after model modifications, process406may proceed back to process401to re-split the patterns into different plurality of pattern types.

When the fitting error is within the predetermined range, method400proceeds to process408by determining whether all pattern types have been fitted. When not all pattern types have been fitted, method400proceeds back to process404to perform model fitting for a pattern type that has not been processed.

In some embodiments, the plurality of models126determined at process124for different pattern types may include similar equations with different coefficients such as coefficients α, β, η, etc. In some embodiments, the plurality of models126determined at process124for different pattern types may include different equations such as double Gaussian approximation, triple Gaussian approximation, or suitable multiple Gaussian approximation.

When all the pattern types have been fitted, method400proceeds to process410by performing a pattern correction to an IC layout. The pattern correction may be the pattern correction process128and may be based on the plurality of models determined at model fitting process124. The pattern correction process128may include a simulation process. The pattern correction process128may also include a shape and a dose correction. As shown inFIG. 4, processes410,412, and414may be included in the pattern correction process128.

Method400then proceeds to process412by performing a simulation process using the corrected IC layout at process410. The simulation process may be performed to the corrected patterns of the IC design layout to create a simulated manufactured device.

At process414, it is determined whether the error of the simulated device is within a predetermined range. When the error of the simulation result is beyond a predetermined range, process414proceeds to process410to further perform the pattern correction to reduce the simulation errors. In some examples, when the error of the simulation result is still out of the predetermined range even after pattern correction, process414may proceed back to process401to re-split the patterns into different plurality of pattern types. In some examples, when the error of the simulation result is out of the predetermined range, the plurality of models may also be modified, for example, the coefficients of the models may be modified, or the models may be modified to use a different equation, to reduce the simulation errors.

When the error of the simulation result is within the predetermined range, method400proceeds to process416by writing the wafer using the corrected patterns. The corrected patterns may be provided to the fabrication facility130(e.g., the e-beam lithography system300) for performing the e-beam exposure process. A typical lithography procedure may include coating, baking, exposure, post-exposure baking, developing and baking according to one embodiment. In some embodiments, a wafer is coated with an e-beam sensitive resist layer. The e-beam exposure process includes exposing the resist layer according to the corrected pattern at process128in a raster writing mode (raster mode) or a vector writing mode (vector mode). After the e-beam exposure process, the exposed wafer may then be developed using a developer chemical.

FIG. 5is a flowchart illustrating a method500of forming a pattern on a substrate using e-beam lithography system300according to some embodiments. It is understood that additional steps can be provided before, during, and after the method500, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method500.

Method500starts from process502by forming a resist film on a substrate. In some embodiments, the substrate may include elementary semiconductor, such as silicon, germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. The substrate may also include one or more semiconductor, conductive, and/or insulating features. In some embodiments, the resist layer may include e-beam sensitive resist layer. The resist layer may be a positive resist or a negative resist. The resist layer may include a single layer resist film or a multiple layer resist film. In some embodiments, the resist layer may be deposited on the substrate using a coating process, for example a spin-on process. After the resist layer is deposited, a soft baking (SB) process may be performed.

Method500proceeds to step504by performing an expose, e.g., e-beam exposure, to the resist layer using the corrected patterns obtained using method400of the present disclosure. The patterns may be split into a plurality of pattern types, and a plurality of models may be used to correct the plurality of pattern types respectively as discussed with regard to method400.

Method500proceeds to step506by developing the exposed resist layer on the substrate to form a resist pattern. In some embodiments, a developer includes a water based developer, such as tetramethylammonium hydroxide (TMAH), for a positive tone development (PTD). In some embodiments, a developer may include an organic solvent or a mixture of organic solvents, such as methyl a-amyl ketone (MAK) or a mixture involving the MAK, for a negative tome development (NTD). Developer may be applied onto the exposed resist film, for example using a spin-on process. The applied developer may also be performed with a post exposure bake (PEB), a post develop bake (PDB) process, or a combination thereof.

Method500proceeds to step508by transferring the resist pattern to the substrate. In some embodiments, transferring the resist pattern to the wafer includes performing an etching process to the substrate using the resist pattern as a mask. The etching process may include a dry (plasma) etching, a wet etching, and/or other etching methods.

The present embodiments describe systems and methods for performing pattern processing and correction in an e-beam lithography process. The mechanisms involve a pattern split process and a pattern fitting process performed to each pattern type so that different types of patterns in the IC design layout can be corrected using different models in the pattern correction process to reduce imaging errors. The mechanisms provide an improved pattern processing including pattern split, pattern fitting, and pattern correction to achieve enhanced pattern precisions and imaging resolutions in the IC design layout formed on the wafer using an e-beam lithography system.

The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.

The present disclosure provides a method for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes forming a resist layer on a substrate; splitting a plurality of patterns of an integrated circuit (IC) layout into a plurality of pattern types; correcting the IC layout using a plurality of models corresponding to the plurality of pattern types respectively to form a corrected IC layout; performing an e-beam exposure process to the resist layer according to the corrected IC layout; and developing the resist layer.

The present disclosure provides a system for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the system includes a design entity configured to provide an integrated circuit (IC) layout including a plurality of patterns; and a pattern processing module configured to split the plurality of patterns into a plurality of pattern types; and perform pattern corrections to the IC layout using a plurality of models corresponding to the plurality of pattern types respectively to form a corrected IC layout.