Current-mode line driver

Disclosed are various embodiments of a current-mode line driver that may facilitate transmitting signals to a load. The current-mode line driver may comprise a common-mode current sense element that provides a signal corresponding to the common-mode output current of the line driver. A transconductance element receives the signal from the common-mode current sense element and provides a compensating current that is based at least in part on the signal. The compensating current may reduce the common-mode output current of the line driver.

BACKGROUND

A communication device may communicate with one or more other devices through a conductive line. The communication device may employ a line driver in order to generate amplified signals that are able to travel across various distances and that overcome noise present in the conductive line.

DETAILED DESCRIPTION

The present disclosure is directed towards current-mode line drivers that may facilitate communication between communication devices. Reference is made toFIG. 1, which shows an example of a communication environment100according to various embodiments of the present disclosure. The communication environment100in the present example includes a transmitter device103in communication with a receiving device106via a conductive medium107. The conductive medium107may be, for example, one or more wires, cables, or any other type of medium that is capable of conducting electrical signals between the transmitter device103and the receiver device106.

The transmitter device103is a communication device that is capable of transmitting signals to another device via the conductive medium107, and the receiver device106is a communication device that is capable receiving signals from another device via the conductive medium107. For the purposes of simplicity, the transmitter device103and the receiver device106in the present example are in communication using a simplex communication configuration. However, it is understood that according to various embodiments, the transmitter device103and the receiver device106may communicate using half-duplex communication, full-duplex communication, or any other type of communication configuration. To this end, the transmitter device103in various embodiments may include circuitry (not shown) that facilitates receiving data via the conductive medium107, and the receiver device106in various embodiments may include circuitry (not shown) that facilitates transmitting data via the conductive medium107.

The transmitter device103includes a line driver109and other components that are not discussed in detail herein for the purposes of brevity. The line driver109may receive input data signals in the transmitter device103and amplify the signals for transmission to the receiver device106. By amplifying the signals being transmitted via the conductive medium107, it may be more likely that the data will reach the receiver device106and be of a quality that is usable by the receiver device106. According to various embodiments, the line driver109may be embodied in the form of a current-mode line driver109or a voltage-mode line driver109.

The receiver device106includes a load113and potentially other components that not discussed in detail herein for brevity. The load113represents circuitry that receives the signals transmitted via the conductive medium107.

Referring toFIG. 2A, shown is an example of a schematic representing an example of a differential-mode equivalent circuit for a current-mode line driver109, referred to herein as the current-mode line driver109a, that may be employed in the communication environment100(FIG. 1) according to various embodiments of the present disclosure. As shown, the schematic includes representations of the current-mode line driver109aand the load113. The current-mode line driver109ais represented by termination resistance R1that is across the outputs of the current-mode line driver109a. Additionally, a source current isis associated with the current-mode line driver109a. Associated with the load113is a differential-mode load impedance ZLdm. A differential output voltage v0is seen across the termination resistance R1and the differential-mode load impedance ZLdm.

Reference is now made toFIG. 2B, which shows a schematic diagram representing an example of a common-mode equivalent circuit for the current-mode line driver109aofFIG. 2Aaccording to various embodiments of the present disclosure. The common-mode equivalent circuit203includes a common-mode current icm, which represents the common-mode current component that may be associated with the current-mode line driver109a. The common-mode current icmmay be associated with noise, reflections, electromagnetic compatibility/electromagnetic interference (EMC/EMI) issues in the transmitter device103(FIG. 1), and/or other effects and may result in undesirable performance by the receiver device106(FIG. 1). Associated with the load113is a common-mode load impedance ZLcm. In the common mode equivalent circuit203shown inFIG. 2B, all of the undesirable common-mode current icmflows through the common-mode load impedance ZLcm.

Reference is now made toFIG. 3A, which shows a schematic diagram representing a differential-mode equivalent circuit for a voltage-mode line driver109, referred to herein as the voltage-mode line driver109b, that may be employed in the communication environment100(FIG. 1) according to various embodiments of the present disclosure. In the present example, the voltage-mode line driver109bis represented by a source voltage vsthat is in series with a pair of termination resistances R2-R3. The resistance value for each termination resistance R2-R3may be represented in relation to termination resistance R1ofFIG. 2Aby the following equations:

R2=R12⁢⁢and[Equation⁢⁢1]R3=R12,[Equation⁢⁢2]
where R1represents the value of the resistance for the termination resistance R1ofFIG. 2A, R2represents the value of the resistance for the termination resistance R2, and R3represents the value of the resistance for the termination resistance R3. As such, the value of the voltage source vsmay be determined using the following equation:
vs=2*v0,  [Equation 3]
where vsrepresents the value of the source voltage vsand v0represents the value of the differential output voltage v0. Because the value of the source voltage vsfor the voltage-mode line driver109bis twice the value of the differential output voltage v0of the current-mode line driver109a(FIG. 2A), the voltage-mode line driver109bmay be less efficient in terms of power consumption than the current-mode line driver109a.

Turning now toFIG. 3B, shown is a schematic diagram representing an example of a common-mode equivalent circuit for the voltage-mode line driver109bofFIG. 3Aaccording to various embodiments of the present disclosure. The common-mode equivalent circuit includes a common-mode current icmand a common-mode source resistance R4. The common-mode current icmrepresents the undesirable common-mode current component that may be associated with the voltage-mode line driver109b. Associated with the load113is a common-mode load impedance ZLcm. For cases in which the common-mode load impedance ZLcmis much greater than the common-mode source resistance R4, substantially all of the common-mode current icm, flows through the source resistance R4and avoids flowing through the common-mode load impedance ZLcm. As such, the voltage-mode line driver109bmay have better common-mode performance than the current-mode line driver109a(FIG. 2A).

Turning now toFIG. 4, shown is a schematic diagram representing an example of a current-mode line driver109athat may be employed in the communication environment100(FIG. 1) according to various embodiments of the present disclosure. The embodiment shown inFIG. 4includes the current-mode line driver109ain communication with the load113. Associated with the load113is a load impedance ZL. The current-mode line driver109aincludes a first differential input line400a, a second differential input line400b, a first source current i1, a second source current i2, a third source current i3, a transistor Q1, a transistor Q2, a termination resistance R1, and potentially other components.

The first differential input line400ais coupled to the gate of the transistor Q1, and the second differential input line400bis coupled to the gate of the transistor Q2. The output of the first current source i1is coupled to the drain of the transistor Q1and one of the lines of the termination resistance R1. Similarly, the output of the second current source i2is coupled to the drain of the transistor Q2and one of the lines of the termination resistance R1.

The sources of the first transistor Q1and the second transistor Q2are coupled to the third current source i3, as shown. The value of the current flowing through the third current source i3may be represented using the following equation:
i3=i1+i2,  [Equation 4]
where i1represents the value of the current through the first current source i1, i2represents the value of the current through the second current source i2, and i3represents the value of the current through the third current source i3.

As discussed above, a common-mode current icmmay be associated with the line driver109and may be experienced by the load113. In the present example, a first common-mode current component icm1and a second common-mode current component icm2may be received by the load impedance ZL. The values of the common-mode current components may be related using the following equation:
icm=icm1+icm2,  [Equation 5]
where icmrepresents the value of the common-mode current icmassociated with the current-mode line driver109a, and icm1and icm2represent the values of the first common-mode current component icm1and icm2the second common-mode current component icm2, respectively.

In order to reduce the amount of the first common-mode current component icm1and the second common-mode current component icm2, the line resistance R1may include a center-tap to which a relatively large capacitance may be coupled. For example, one line of a relatively large capacitor may be coupled to the center-tap of the termination resistance R1, and the other line of the capacitor may be coupled to ground. As an alternative, the input of a voltage buffer may be coupled to a reference common-mode voltage, and the output of the voltage buffer may be coupled to the center-tap of the termination resistance R1. As a result, the amount of the first common-mode current component icm1and the second common-mode current component icm2may be reduced.

With reference toFIG. 5, shown is a schematic diagram representing an example of another current-mode line driver109athat may be employed in the communication environment ofFIG. 1according to various embodiments of the present disclosure. Associated with the load113is a load impedance ZL. The current-mode line driver109ain the present example includes a first differential input line500a, a second differential input line500b, a first voltage buffer503a, a second voltage buffer503b, a first current mirror slave506a, a second current mirror slave506b, a termination resistance R1, a replica load resistance R5, a capacitance C1, and potentially other components that are not discussed in detail herein for brevity.

The first voltage buffer503aincludes a non-inverting input line509a, an inverting input line513a, a first buffer output line516a, an amplifier stage519a, and other components that are not discussed in detail herein for brevity. The non-inverting input line509aof the first voltage buffer503ais coupled to the first differential input line500aand is configured to receive a differential input signal. The inverting input line513aof the first voltage buffer503ais coupled to the first buffer output line516aof the first voltage buffer503a. Thus, the first voltage buffer503aoutputs on the first buffer output line516aa voltage signal that is substantially equal to the voltage for the differential input signal that may be applied to the first differential input line500a.

The amplifier stage519ais a portion of the first voltage buffer503athat may amplify signals in the first voltage buffer503a. To this end, the amplifier stage519amay be embodied in the form of a class AB amplifier stage or any other type of amplifier stage. In the present example, the amplifier stage519aincludes a transistor Q3, a transistor Q4, a first line529a, a second line533a, a third line536a, and potentially other components. The gate of the transistor Q3is coupled to the first line529aof the amplifier stage519a, and the gate of the transistor Q4is coupled to the third line536aof the amplifier stage519a. The drain of the transistor Q3is coupled to the drain of the transistor Q4. Furthermore, the drain of the transistor Q3and the drain of the transistor Q4are coupled to the second line533aof the amplifier stage519a. The second line533aof the amplifier stage519ais further coupled to the first buffer output line516aof the first voltage buffer503a.

The second voltage buffer503bincludes a non-inverting input line509b, an inverting input line513b, a second buffer output line516b, an amplifier stage519b, and other components that are not discussed in detail herein for brevity. The non-inverting input line509bis coupled to the second differential input line500band is configured to receive a differential input signal. The inverting input line513bof the second voltage buffer503bis coupled to the second buffer output line516b. Thus, the second voltage buffer503boutputs to the second buffer output line516ba voltage signal that is substantially the same voltage as the differential input signal that is applied to the second differential input line500b.

The amplifier stage519bis a portion of the second voltage buffer503bthat may amplify signals in the second voltage buffer503b. To this end, the amplifier stage519bmay be embodied in the form of a class AB amplifier stage or any other type of amplifier stage. In the present example, the amplifier stage519bincludes a transistor Q5, a transistor Q6, a first line529b, a second line533b, a third line536b, and potentially other components. The gate of the transistor Q5is coupled to the first line529bof the amplifier stage519b, and the gate of the transistor Q6is coupled to the third line536bof the amplifier stage519b. The drain of the transistor Q5is coupled to the drain of the transistor Q6. Furthermore, the drain of the transistor Q5and the drain of the transistor Q6are coupled to the second line533bof the amplifier stage519b. The second line533bof the amplifier stage519bis further coupled to the second buffer output line516b.

The first current mirror slave506amay generate a current islave1that is proportional to the current imaster1flowing from the second line533aof the amplifier stage519ain the first voltage buffer503a. As such, the amplifier stage519ain the first voltage buffer503amay be regarded as being a current mirror master for the first current mirror slave506a. Various embodiments of the first current mirror slave506amay employ a transistor Q7, a transistor Q8, and potentially other components. The gate of the transistor Q7in the first current mirror slave506ais coupled to the first line529aof the amplifier stage519ain the first voltage buffer503a. Additionally, the gate of the transistor Q8in the first current mirror slave506ais coupled to the third line536aof the amplifier stage519ain the first voltage buffer503a. Thus, the current islave1that is output from the first current mirror slave506amay be represented by the following equation:
islave1=m*imaster1,  [Equation 6]
where islave1is the value of the current islave1output from the first current mirror slave506a, imaster1is the value of the current imaster1output from the amplifier stage519a, and m is a scaling factor resulting from parameters set by the first current mirror slave506a.

The second current mirror slave506bmay generate a current islave2that is proportional to the current imaster2flowing from the second line533bof the amplifier stage519bin the second voltage buffer503b. As such, the amplifier stage519bin the second voltage buffer503bmay be considered a current mirror master for the second current mirror slave506b. Various embodiments of the second current mirror slave506bmay employ a transistor Q9, a transistor Q10, and potentially other components. The gate of the transistor Q9in the second current mirror slave506bis coupled to the first line529bof the amplifier stage519bin the second voltage buffer503b. Additionally, the gate of the transistor Q10in the second current mirror slave506bis coupled to the third line536bof the amplifier stage519ain the second voltage buffer503a. Thus, the current islave2output from the second current mirror slave506bmay be represented by the following equation:
islave2=m*imaster2,  [Equation 7]
where islave2is the value of the current islave2output from the second current mirror slave506b, imaster2is the value of the current imaster2output from the amplifier stage519bin the second voltage buffer503b, and m is a scaling factor resulting from parameters set by the second current mirror slave506b. It is noted that m in equation 7 may be the same value as m in equation 6.

The replica load resistance R5may facilitate replicating signals that are associated with the load impedance ZL. In various embodiments, the value of the replica load resistance R5may be given by the following equation:
R5=m*Rload,  [Equation 8]
where R5is the value of the replica load resistance R5, Rloadis the value of the real component of the load impedance ZL, and m is the scaling factor resulting from parameters set by the first current mirror slave506aand the second current mirror slave506b. As such, the differential output voltage v0across the load impedance ZLmay be related to the replica load voltage vrepby the following equation:
v0=vrep,  [Equation 9]
where v0is the value of the differential output voltage v0, and vrepis the value of the voltage vrepacross the replica load resistance R5. Thus, the replica load resistance may facilitate replicating signals that are associated with the load impedance ZL.

According to various embodiments, the replica load resistance R5may be embodied in the form of a tapped resistor, such as a center-tapped resistor. A relatively large capacitor C1may be coupled to the center-tap of the replica load resistance R5and to ground in order to provide an AC ground at the center-tap of the resistor. As an alternative, a voltage buffer may be coupled to the replica load resistance R5, such that the input of the voltage buffer is coupled to a reference common-mode voltage, and the output of the voltage buffer is coupled to the center-tap of the replica load resistance R5. As a result of these configurations, replica common-mode current components irep1and irep2flow into the replica load resistance R5, and a replica common-mode current irepflows from the center-tap of the replica load resistance R5to the ground. The replica common-mode current components irep1and irep2may be related to the replica common-mode current irepusing the following equation:

irep⁢⁢1=⁢irep⁢⁢2=⁢irep2,[Equation⁢⁢10]
where irep1and irep2represent the values of the replica common-mode current components irep1and irep2, and ireprepresents the value of the replica common-mode current irep. The replica common-mode current irepmay be related to the common-mode output currents icm1and icm2by the following equation:
icm1+icm2=m*irep,  [Equation 11]
where icm1represents the value of the common-mode output current icm1, icm2represents the value of the common-mode output current icm2, ireprepresents the value of the replica common-mode current irep, and m is the scaling factor resulting from the first current mirror slave506aand the second current mirror slave506b.

Next, a general description of an example of the operation of the current-mode line driver109ainFIG. 5is provided. In operation, a first differential input signal may be applied to the first differential input line500a, and a second differential input signal may be applied to the second differential input line500b. The first differential input signal is received by the first voltage buffer503a, which buffers the first differential input signal and outputs the corresponding voltage to the first buffer output line516a. Similarly, the second differential input signal is received by the second voltage buffer503b, which buffers the first differential input signal and outputs the corresponding voltage to the second buffer output line516b. These signals that are output from the first voltage buffer503aand the second voltage buffer503bare applied to the replica load resistance R5, thereby generating the replica load voltage vrep. Additionally, the replica common-mode current irepflows from the tap in the replica load resistance R5to ground through the capacitance C1.

The signal that is output from the first voltage buffer503aon the first buffer output line516ais mirrored to the output of the current-mode line driver109ausing the first current mirror slave506a. In this respect, the amplifier stage519ain the first voltage buffer503aacts as a current mirror master for the first current mirror slave506a. As a result, the current islave1may be mirrored to the output of the current-mode line driver109ain an amount that is proportional to the current imaster1, as expressed in equation 6 above.

Similarly, the signal that is output from the second voltage buffer503bon the second buffer output line516bmay be mirrored to the output of the current-mode line driver109ausing the second current mirror slave506b. In this respect, the amplifier stage519bin the second voltage buffer503bacts as a current mirror master for the second current mirror slave506b. As a result, the current islave2may be mirrored to the output of the current-mode line driver109ain an amount that is proportional to the current imaster2, as expressed in equation 7 above.

Because an undesirable common-mode signal may be present in the current imaster1and/or in the current imaster2, the first current mirror slave506aand the second current mirror slave506bmay multiply the undesirable current-mode signal when mirroring the currents imaster1and imaster2. Thus, the resulting common-mode output currents icm1and icm2may be provided to the load113. As previously discussed, the common-mode currents icm1and icm2may be provided to the output of the current-mode line driver109ain an amount that is proportional to the current irep, as expressed in equation 10 above. As a result, the quality of the signal received by the receiver device106(FIG. 2) may be degraded, EMI may occur, or the receiver device106may not function as desired.

Turning now toFIG. 6, shown is a schematic diagram representing another example of a current-mode line driver109athat may be employed in the communication environment ofFIG. 1according to various embodiments of the present disclosure. The current-mode line driver109ashown inFIG. 6is similar to the current-mode line driver109ashown inFIG. 5. However, in the embodiment shown inFIG. 6, the current-mode line driver109afurther includes a common-mode current sense element603, a transconductance element606, and potentially other components that are not discussed in detail herein for brevity.

The common-mode current sense element603may be a component configured to provide a signal609that corresponds to the value of the sum of the common-mode output currents icm1and icm2. For example, the common-mode current sense element603may provide a voltage that is proportional to the sum of the common-mode output currents icm1and icm2. To this end, the common-mode current sense element603may be embodied in the form of a first resistor and a second resistor that are connected in series with respect to each other such that the first resistor and the second resistor are coupled to the outputs of the current-mode line driver109a. The first resistor and the second resistor may have relatively large resistance values such that a relatively small current flows through the common-mode current sense element603. At the point where the first resistor and the second resistor are coupled to each other, a common-mode voltage signal609may be provided that is proportional to the total common-mode current that is experienced by the load113.

The input of the transconductance element606in the present example is coupled to the output of the common-mode current sense element603, and the output of the transconductance element606is coupled to the tap in the replica load resistance R5. The transconductance element606may be an element that is configured to receive the signal609and provide a compensating current icompbased at least in part on the signal609. For example, the compensating current icompmay be proportional to the voltage of the signal609. To this end, the transconductance element606according to various embodiments may be a transconductance amplifier. The output of the transconductance element606is coupled to the tap in the resistance R5. As such, the first buffer output line516aand the second buffer output line516bare in communication with the output of the transconductance element606.

It is noted that the value of the transconductance for the transconductance element606may be limited by the stability requirement that the gain-bandwidth product of the common-mode loop must be lower than the second pole that occurs at the center tap of the replica load resistance R5. Nonetheless, the magnitude of the compensating current icompmay be configured to be substantially the same as the magnitude of the replica common-mode current irep, with the polarity of the compensating current icompbeing opposite of the polarity of the replica common-mode current irep. This relation may be expressed as follows:
icomp=−irep,  [Equation 12]
where icomprepresents the value of the compensating current icomp, and ireprepresents the value of the replica common-mode current irep. As such, when the compensating current icompis provided to the center-tap in the replica load resistance R5, the compensating current icompmay substantially negate or eliminate the replica common-mode current irep.

Next, a general description of an example of the operation of the current-mode line driver109ainFIG. 6is provided. The operation of the current-mode line driver109ainFIG. 6is similar to the operation of the current-mode line driver109ainFIG. 5. However, in the current-mode line driver inFIG. 6, the common-mode current sense element603provides the signal609that corresponds to the value of the total common-mode current experienced by the load113. For example, if the common-mode current sense element603is embodied in the form of a first resistor in series with a second resistor and coupled across the output of the current-mode line driver109a, the point where the first resistor and the second resistor are coupled to each other may provide a common-mode voltage signal609that is proportional to the sum of the common-mode output currents icm1and icm2that is experienced by the load113.

The signal609is provided to the input of the transconductance element606, which provides the compensating current icompbased at least in part on the signal609. In turn, the compensating current icompis provided to the tap in the replica load resistance R5. Because the value of the compensating current icompmay be equal and opposite to the value of the replica common-mode current irep, the compensating current icmmay substantially negate or eliminate the replica common-mode current irep. As a result, the common-mode components in the current imaster1the current imaster2may be negated.

As represented in equations 6 and 7 above, the value of the current islave1may be proportional to the value of the current imaster1, and the value of the current islave2may be proportional to the value of the current imaster2. Thus, by the compensating current icompsubstantially negating the common-mode components in the current imaster1and the current imaster2, the common-mode components that may otherwise be present in the current imaster2and the current imaster2may be negated. Using equations 10 and 11 above, the value of the total common-mode current may be expressed using the following equation:
icm1+icm2=m*(irep+icomp)m*(irep−irep)=0.  [Equation 13]
Thus, the total common-mode current experienced by the load113may be substantially negated.

Turning now toFIG. 7, shown is a schematic diagram representing another example of a current-mode line driver109athat may be employed in the communication environment ofFIG. 1according to various embodiments of the present disclosure. The current-mode line driver109ashown inFIG. 7is similar to the current-mode line driver109ashown inFIG. 6. However, in the embodiment shown inFIG. 7, the capacitance C1shown inFIG. 6is not present. In addition, the current-mode line driver109aincludes the capacitances C2-C5. The capacitances C2-C5may utilize the Miller effect to compensate the common-mode loop for stability. As a result, the capacitances C2-C5may facilitate a wider bandwidth for the common-mode loop. To this end, the capacitances C2and C5may be embodied in the form of common-mode Miller compensation capacitors.

The capacitance C2is coupled to the output of the transconductance element606and to the third line536aof the amplifier stage519ain the first voltage buffer503a, and the capacitance C3is coupled to the output of the transconductance element606and to the first line529aof the amplifier stage519ain the first voltage buffer503a. Similarly, the capacitance C4is coupled to the output of the transconductance element606and to the first line529bof the amplifier stage519bof the second voltage buffer503b, and the capacitance C5is coupled to the output of the transconductance element606and to the third line536bof the amplifier stage519bin the second voltage buffer503b. The values of capacitances C2-C5may be relatively small as compared to the value of the capacitance C1(FIG. 6). Additionally, each capacitance C2-C5may be in series connection with a resistance (not shown) to facilitate Miller effects that may increase the bandwidth for the common-mode loop.

Referring next toFIG. 8, shown is a flowchart illustrating an example of functionality implemented by the current-mode line driver109aofFIGS. 6and/or7according to various embodiments of the present disclosure. It is understood that the flowchart ofFIG. 8provides merely an example of the many different types of functionality that may be implemented by the circuitry in the current-mode line driver109aas described herein. Additionally, the flowchart ofFIG. 8may be viewed as depicting an example of steps of a method implemented in the current-mode line driver109aaccording to one or more embodiments.

To begin, at reference number803, the current mode-line driver109areceives the differential-mode input signals. The differential-mode input signals may be voltage signals that are applied to the first differential input line500a(FIG. 5) and the second differential input line500b(FIG. 5). Next, as shown at reference number806, the line driver109aprovides the output current for that may be received by the load113(FIG. 1). The output current may be, for example, the current islave1(FIG. 5) and the current islave2(FIG. 5) and may have a common-mode component and a differential-mode component. At reference number809, the line driver109aprovides the signal609(FIG. 6) corresponding to the amount of the current-mode component of the output current. As discussed above, the signal609may be a voltage that corresponds to the amount of the common-mode component of the output current.

Moving to reference number813, the current-mode line drive109aprovides the compensating current icompto the tap in the resistance R5(FIG. 6). To this end, the transconductance element606may receive the signal609and generate the compensating current icompbased at least in part on the signal609. As a result of the compensating current icompbeing provided to the tap in the resistance R5, the common-mode output current for the current-mode line driver109amay be reduced, as shown at reference number816. Thereafter, the process ends.

Although the flowchart ofFIG. 8shows a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more blocks may be scrambled relative to the order shown. Also, two or more blocks shown in succession inFIG. 8may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the items shown inFIG. 8may be skipped or omitted. In addition, any number of elements might be added to the logical flow described herein, for purposes of enhanced utility, accounting, performance measurement, or providing troubleshooting aids, etc. It is understood that all such variations are within the scope of the present disclosure.

The components described herein may be implemented by circuitry. In this regard, such circuitry may be arranged to perform the various functionality described above by generating and/or responding to electrical or other types of signals. The circuitry may be general purpose hardware or hardware that is dedicated to performing particular functions. The circuitry may include, but is not limited to, discrete components, integrated circuits, or any combination of discrete components and integrated circuits. Such integrated circuits may include, but are not limited to, one or more microprocessors, system-on-chips, application specific integrated circuits, digital signal processors, microcomputers, central processing units, programmable logic devices, state machines, other types of devices, and/or any combination thereof. As used herein, the circuitry may also include interconnects, such as lines, wires, traces, metallization layers, or any other element through which components may be coupled. Additionally, the circuitry may be configured to execute software to implement the functionality described herein.