QFN package and manufacturing process thereof

The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a QFN package and manufacturing process thereof, and more particularly, to a QFN package with composite bumps.

2. Descriptions of the Related Art

Semiconductor packaging processes have been widely used to electrically connect a semiconductor chip to an external component with a better reliability and also to protect the semiconductor chip from damages caused by external conditions. However, packaging materials and the packaging processes used are not only associated with the manufacturing cost, but also have an influence on operational performance of the packaged chip. For this reason, the packaging structure and materials thereof selected for use become very important.

Among several package technologies, Quad Flat No-Leaded (QFN) semiconductor packages have achieved wide popularity in recent years because of their smaller package size. In a conventional QFN semiconductor package, a chip is electrically connected to a lead frame by wire, with each bond pad of the chip being electrically connected to a corresponding lead of the lead frame respectively. As to a flip chip QFN package10, a chip101is electrically connected to a lead frame103by bumps105as shown inFIG. 1AorFIG. 1C. The chip101is flipped and bonded on the lead frame103by solder joining of solder bump (FIG. 1A) or copper pillar with solder cap. Due to reflow for melting the solder bump or solder cap on copper pillar to solder join the bump105of chip101and lead of lead frame103, the lead width will be limited to enough space for avoid the melting solder over flow to the opposite side of lead during the reflow process (FIG. 1B). That melting solder107over flow on the opposite side of lead will induce assembly defect of further process, for example encapsulation, or SMT (Surface Mount Technology).

Unfortunately, sometimes limitation of chip size and package size, the lead width may not be designed with enough space to avoid the melting solder over flow. In view of this, it is highly desirable in the art to provide a solution that can improve the limitation of lead width and also provide a lower the manufacturing cost of a packaging structure.

SUMMARY OF THE INVENTION

The primary objective of the present invention is to provide a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. A semi-cured encapsulant is formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant, formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame, are provided.

To provide the aforesaid QFN package, the manufacturing process of the present invention comprises the following steps of: forming a plurality of lead frame module; forming a plurality of chip modules, each having a chip being connected with a plurality of composite bumps; bonding the lead frame modules to the chip modules by connecting the composite bumps to the leads respectively; and forming a plurality of QFN packages by encapsulating and singulating the chip modules and the lead frame modules.

When adapting thermo-ultrasonic bonding, the step of forming a plurality of lead frame modules comprises the following steps of: forming an upper unit by semi cured encapsulant onto a top carrier; forming a lower unit by disposing a matrix lead frame on a bottom carrier, wherein the matrix lead frame comprises a plurality of leads; bonding the upper unit and the lower unit by laminating the semi cured encapsulant with the matrix lead frame to have the leads be in contact with the top carrier; forming the plurality of lead frame modules by fully curing the encapsulant and removing the top carrier to make sure the top surface of lead is not lower than the encapsulant. It should be noted that the step of bonding the lead frame modules to the chip modules may be proceeded by one of thermo-ultrasonic bonding, reflowing and applying conductive paste.

As compared to the prior art, the present invention provides the following benefits: the QFN package and a manufacturing process thereof of the present invention replaces the conventional bumps with the composite bumps and a encapsulated matrix lead frame, so the pitch between and the height of the composite bumps of the QFN package could be controlled, and the short interconnection loop formed by the composite bumps could reduce the resistance and inductance and improve the performance of the whole QFN package.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following descriptions, this invention will be explained with reference to embodiments thereof, which relate to a QFN package and a manufacturing process thereof.

However, these embodiments are not intended to limit this invention to any specific environment, applications or particular implementations described in these embodiments. Therefore, descriptions of these embodiments are only for illustration purposes rather than limitation. It should be appreciated that in the following embodiments and the attached drawings, elements unrelated to this invention are omitted from depiction; and dimensional relationships among individual elements in the attached drawings are depicted in an exaggerative way for ease of understanding.

Referring toFIG. 2A, a preferred embodiment of a Quad Flat Non-leaded (QFN) package1in accordance with the present invention is shown therein. The QFN package1comprises a chip11, a lead frame13, a plurality of composite bumps15and an encapsulant17.

The chip11has an active surface113, a plurality of pads111and a passivation layer. The pads111are formed on the active surface113of the chip11. More specifically, the pads111are arranged at four sides of the active surface113, and the pads111may be only arranged at two parallel sides of the active surface113in other aspects. Each of the pads111is partially covered by the passivation layer115, and some portion of each of the pads111is exposed for electrical connection thereby. In the present invention, the chip11may be, for example, a display driver circuit IC, an image sensor IC, a memory IC, a logic IC, an analog IC, an ultra-high frequency (UHF) or a radio frequency (RF) IC, but it is not limited thereto.

The lead frame13has a plurality of leads131, which are arranged at four sides to form a square in this embodiment (not shown). Each lead131has an inner lead portion131aand an outer lead portion131b. Each of the inner lead portions131aand each of the outer lead portions131bhave a height difference that the inner lead portions131aare higher than the outer lead portions131bas shown inFIG. 2A.

The composite bumps15are electrically connected between the chip11and the lead frame13. Each composite bump15has a first conductive layer151and a second conductive layer153, and the second conductive layer153is softer than the first conductive layer151. The first conductive layer151is electrically connected between a corresponding pad111of the pads111of the chip11and the second conductive layer153. The second conductive layer153is electrically connected between the first conductive layer151and a corresponding inner lead portion131aof the inner lead portions131aof the leads131of the lead frame13. As a result, the composite bumps15electrically connect to the pads111of the chip11with the first conductive layers, and the composite bumps15electrically connect to the inner lead potions131aof the leads131of the lead frame13with the second conductive layers153. The first conductive layer151may be made of a material selected from a group consisting of copper, nickel, aluminum, zinc, and combinations thereof. The second conductive layer153may be made of a material selected from a group consisting of gold, copper, silver, tin, zinc, indium, and combinations thereof. The second conductive layer153made of gold forms a thickness which is at least less than a half of the total height of the composite bump15. The reduction of gold results in reducing the manufacture cost.

It shall be noted that, the composite bumps15disclosed above are only provided as an example, and as may be appreciated by those of ordinary skill in the art, the composite bumps15may also be “composite” bump structures formed by other existing bumps in combination (for example, the composite bumps are formed by two layers of stud bumps) to satisfy different demands for electrical connection between different kinds of flip chips and the substrate and to lower the manufacturing cost by reducing use of gold.

Each of the composite bumps15connects to the top surface of the corresponding inner lead portion131aof the lead131of the lead frame13by thermo-ultrasonic bonding, reflowing, or applying conductive paste therebetween. In this embodiment, the composite bumps15connect to the leads131by thermo-ultrasonic bonding. In another aspect of the present invention, the QFN package further comprises a plurality of plated structures, one of which is adhered between the second conductive layer and the lead for connecting each of the composite bumps to the corresponding inner lead portion of the lead of the lead frame by reflowing. The encapsulant of such modification would not have any encapsulation interface. The plated structure is solder or a copper pillar with a solder cap. Moreover, in a further aspect of the present invention, the QFN package further comprises a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads. The conductive paste may be silver paste or solder. Neither the encapsulant of such modification would have any encapsulation interface.

It should be noted that there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the inner lead portion131awould be bent, cracked or even fractured. Meanwhile, if a low melting temperature soft melt material is applied for solder (not shown) to join the bump15and inner lead portion131aof lead131of lead frame13, the soft melt material would overflow and induce some defects in further assembly process. To avoid such defects, the present invention further provides a QFN package which adopts specific manufacturing process and would be describe in detail later, further has an encapsulation interface19which is not higher than a top surface of the lead frame13as shown inFIG. 2B. In more detail, the encapsulant17is only formed around the chip and the composite bump, fully cured encapsulant17′ is formed around the leads131of the lead frames13under the encapsulant17, and the interface between the encapsulant17and the fully cured encapsulant17′ is the encapsulation interface

Hereinbelow, the manufacturing process for manufacturing the QFN packages of the abovementioned embodiment of the present invention will be detailed with reference to the above descriptions, the attached drawingsFIGS. 3A-3E,4A-4C,5A-5B. It shall be noted that, for simplicity of the description, the manufacturing process for manufacturing the QFN packages will be described with only one chip as a representative example in the following descriptions and the attached drawings, and the material or related description of the elements is the same as above-mentioned and is omitted.

Instead of providing a matrix lead frame in the well-known manufacturing process of QFN packages, a plurality of lead frame modules are provided by pre-molding in this specific manufacturing process. Referring toFIG. 3A, as shown therein, forming an upper unit3aby forming a semi cured encapsulant17″ onto a top carrier41is executed. A top carrier41could be metal, glass, organic film, or plastic, which could provide a flat surface and appropriate strength for the semi cured encapsulant17″. Then,FIG. 3Bshows that a lower unit3bis formed by disposing a matrix lead frame6(as shown inFIG. 6) on a bottom carrier31, which could be organic film, glass, plastic, or metal. As shown inFIG. 313andFIG. 6, the matrix lead frame6comprises a plurality of lead frames13, each of the lead frames13comprises a plurality leads131, and each lead131has an inner lead portion131aand an outer lead portion131b. Appropriate adhesion between the bottom carrier31and the lead frame13is necessary for further process. It should be noted that the executing priority of the processes illustrated inFIG. 3AandFIG. 3Bare not limited.

Then,FIG. 3Cfeatures that bonding the upper unit3aand the lower unit3bby laminating the semi cured encapsulant17″ with the matrix lead frame to have the leads131be in contact with the top carrier41. In more detail, the top carrier41contacts the top surface of the inner lead portions131aof the leads131. Since the semi cured encapsulant17″ is partially cured and is a semifluid substance, the leads131would be enclosed except for the top surface of the inner lead portions131aand the bottom surface of the outer lead portions131b.

Next, referring toFIG. 3D, as shown therein, forming a lead frame module3d(or3eshown inFIG. 3E) on each lead frame13of the matrix lead frame by fully cured the semi cured encapsulant17″ to fully cured encapsulant17′ and removing the top carrier41. After removing the top carrier41, the top surface of the fully cured encapsulant17′ may be as high as (or lower than shown inFIG. 3E) the top surface of the inner lead portions131aof the leads131. Thereby, the lead frame module3d(or3eshown inFIG. 3E) on the matrix lead frame is formed.

Referring toFIG. 4A, as shown therein, a wafer30is provided. The wafer30is formed with internal circuits, an active surface113, a plurality of pads111and a passivation layer115. The pads ill are disposed on the active surface113and are partially covered by the passivation layer115to provide exposed areas (or named “openings”). Signals would be transmitted from or to the internal circuits through the exposed areas of the pads111.

Referring toFIG. 4B, as shown therein, forming a composite bump15on each of the pads111is executed. Each of the composite bumps15comprises a first conductive layer151and a second conductive layer153, and the first conductive layer151is directly connected to and disposed between a corresponding pad111of the pads111and the second conductive layer153. Thereby, the internal circuits of the wafer30and the composite bumps15are electrically connected via the exposed areas of the pads111. Then, as shown inFIG. 4C, the wafer30is saw to provide a plurality of chips11, each of which is electrically connected with plural composite bumps15. As will be appreciated by those of ordinary skill in the art upon reviewing the above descriptions, other existing processes for composite bumps may also be applied in the present invention, and this will not be further described herein.

On the other hand, a plurality of lead frame module, which is disposed and formed on the matrix lead frame6on a bottom carrier31, is provided according to the stepsFIGS. 3A-3E. The matrix lead frame6(as shown inFIG. 6) comprises a plurality of lead frames13, and each of the lead frames13has a plurality of leads131as depicted above. And the leads131of the matrix lead frame13are enclosed with the fully cured encapsulant17′ except for the top surface of the inner lead portions131aand the bottom surface of the outer lead portions131b.FIG. 5Ashows the following step that bonding each of the chips11to a corresponding plurality of leads131of the lead frames13of lead frame module on the matrix lead frame with composite bumps15. Each of the chips11is electrically connected to a part of the leads131of the matrix lead frame by a plurality of composite bumps15. The second conductive layer153of each composite bump15is directly connected to the top surface of the inner lead portion131aof the corresponding lead131of the lead frame13by thermo-ultrasonic bonding, reflowing or applying conductive paste. It is known that there would be solder between the composite bumps15and the inner leads131a, and such solder is not shown inFIG. 5Aif reflow is applied.

Then, as shown inFIG. 5B, the chip11, the lead frames13on the matrix ad frame and the composite bumps15are encapsulated. The encapsulant17is formed around the chip11and the composite bumps15and covers almost the whole surface of the lead frame13except for the bottom surface of outer lead portion131bof lead131by transfer molding, screen printing, coating, or injection, etc. The encapsulation interface19would be formed in such case, no matter whether the encapsulant17is the same material as the fully cured encapsulant17′ or not. Finally, singulating the matrix lead frame and stripping off the bottom carrier31to the QFN packages1is executed as shown inFIG. 2. The QFN package1comprises one of the encapsulated chips11and a part of the encapsulated matrix lead frame.

When adapting thermo-ultrasonic bonding, there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the inner lead portion131awould be not bent, cracked or even fractured. And no more melting solder overflows in the present invention

In other aspect, the composite bump may further comprise at least an under bump metallization (UBM) layer, or a covering third conductive layer and a barrier layer. Referring toFIG. 7, as shown therein, the chip11is electrically connected to plural composite bumps through plural pads111. Each of the composite bumps2comprises an under bump metallization (UBM) layer21, a first conductive layer23, a second conductive layer25, a covering third conductive layer27and a barrier layer29. The UBM layer21is disposed between the first conductive layer23and the pad111of the chip11. The first conductive layer23is located on the UBM layer21, and the second conductive layer25is in turn located on the first conductive layer23. The covering third conductive layer27that covers the surface each of the composite bumps2, which includes the second conductive layer25, and the first conductive layer23. The barrier layer29located between the first conductive layer23and the second conductive layer25. The UBM layer21may be made of a material selected from titanium, tungsten, copper, gold, and alloys thereof. The covering third conductive layer27may be made of gold, but it is not limited thereto. The barrier layer29may be made of nickel, but it is not limited thereto.

Moreover, the step of forming the wafer30shown inFIG. 4Amay further comprises the following steps of forming a redistribution layer (RDL)51on each of the pads111of the chips11for electrical connection between the first conductive layer151of each of the composite bumps2; and forming the composite bump15by forming a first conductive layer151on each of the RIM layers51and forming a second conductive layer153on the first conductive layer151to re-layout the bump position as shown inFIG. 8.

With the composite bumps, the pitch between and the height of the composite bumps15of the QFN package1could be controlled, and the short interconnection loop formed by the composite bumps15could reduce the resistance and inductance and improve the performance of the whole QFN package. Moreover, pre-molding the lead frame could avoid the different leveling issue of inner lead portions and protect the lead surface.