A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate comprising a coupling part and a gate part is disposed over the control gate and located over a portion of the substrate with the gate oxide layer there-between. The source region adjoins with one side of the gate part, while the drain region adjoins with the other side of the gate part. The first dielectric layer is disposed on the floating gate. The second dielectric layer is disposed on the sidewalls of the floating gate. The erase gate is disposed over the coupling part of the floating gate and covers the first dielectric layer and the second dielectric layer.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a memory device. More particularly, the present invention relates to a non-volatile memory and a manufacturing method and an erasing method thereof.

2. Description of Related Art

Memory, just as its name implies, is a semiconductor device for storing information and data. Memory is required to perform more and more effectively as the functions of microprocessors become stronger and the programs and calculations of software become larger. Memory with mass storage and low cost must be manufactured to meet the requirements of this trend. Therefore, the process of manufacturing such memory devices continuously develops for the semiconductor technology with higher integration.

Among memories, non-volatile memory is capable of storing, reading, or erasing data repeatedly, and the stored data will not disappear after the power supply is disconnected. Because of these advantages, non-volatile memory has become a memory device widely employed in personal computers and electronic apparatuses.

FIG. 1is a schematic cross-sectional view of a conventional single poly non-volatile memory. The conventional single poly non-volatile memory consists of an N-type metal oxide semiconductor (NMOS) structure10and a P-type metal oxide semiconductor (PMOS) structure12, and a field oxide layer11between the NMOS structure10and the PMOS12structure. The NMOS structure10is formed on a P-type substrate14, and comprises a floating gate16, a gate oxide layer34, an N+source doped region18, and an N+drain doped region20. The PMOS structure12is formed on an N-type ion well region22, and comprises a floating gate24, a gate oxide layer36, a P+source doped region26, and a P+drain doped region28. Additionally, an N-type channel barrier region30is disposed below the floating gate24and adjoins to one side of the P+source doped region26. Furthermore, a floating gate wire32should be disposed between the floating gates16and24, in order to maintain the same potential for the floating gates16and24.

However, the conventional single poly non-volatile memory encounters a few problems. For example, the conventional single poly non-volatile memory including the NMOS structure10and the PMOS structure12occupies a much larger chip area, which results in a relatively high production cost. On the other hand, the conventional single poly non-volatile memory takes a longer time to erase data, resulting in low operating speed of the memory device. Moreover, for the erasing operation of the conventional single poly non-volatile memory, the electrons are drawn from the floating gate to the substrate through the gate oxide layer, and the gate oxide layer may be easily damaged, thus adversely affecting the cycling number and the reliability of the memory device.

FIG. 2is a schematic cross-sectional view of a split gate non-volatile memory. The conventional split gate non-volatile memory comprises a substrate40, a floating gate42, a control gate44, a source region46, and a drain region48. However, the memory device employing the conventional split gate non-volatile memory has a larger size, and electron can be trapped easily for the erasing operation, thus lowering endurance of the memory device.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to provide a non-volatile memory and a manufacturing method and an erasing method thereof, which are capable of reducing the erasing time, accelerating the operating speed of the device, and increasing the cycling numbers.

The invention provides a non-volatile memory, which comprises a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in the substrate, and the floating gate is disposed over the control gate and located on the substrate. The floating gate comprises a coupling part and a gate part. The gate oxide layer is disposed between the floating gate and the substrate. The source region is disposed in the substrate and adjoins with one side of the gate part of the floating gate. The drain region is disposed in the substrate and adjoins with the other side of the gate part of the floating gate. The first dielectric layer is disposed on the floating gate. The second dielectric layer is disposed on sidewalls of the floating gate. Additionally, the erase gate is disposed over the coupling part of the floating gate and covers the first dielectric layer and the second dielectric layer.

According to one embodiment of the invention, the top edge of the floating gate is sharp-angled.

According to the embodiment of the invention, the control gate is, for example, a heavily doped region.

According to the embodiment of the invention, the material of the erase gate is, for example, polysilicon or doped polysilicon.

According to the embodiment of the invention, the material of the floating gate is, for example, polysilicon or doped polysilicon.

According to the embodiment of the invention, the material of the gate oxide layer is, for example, silicon oxide.

The invention further provides an erasing method of a non-volatile memory, wherein the non-volatile memory comprises a control gate disposed in a substrate; a floating gate comprising a coupling part and a gate part disposed on the control gate and located on a portion of the substrate; a gate oxide layer disposed between the floating gate and the substrate; a source region disposed in the substrate and neighboring to one side of the gate part of the floating gate; a drain region disposed in the substrate and neighboring to the other side of the gate part of the floating gate; a first dielectric layer disposed on the floating gate; a second dielectric layer disposed on sidewalls of the floating gate; and an erase gate disposed over the coupling part of the floating gate and covering the second dielectric layer. The erasing method comprises applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased.

According to one embodiment of the invention, the first voltage, the second voltage, the third voltage, and the fifth voltage are zero volts, and the fourth voltage is 12 volts.

The invention further provides a manufacturing method of a non-volatile memory, which comprises first providing a substrate that has at least a device isolation structure for defining multiple pairs of active regions; forming a control gate in one of each pair of the active regions of the substrate; forming a gate oxide layer, a conductor layer, and a patterned mask layer on the substrate in sequence, wherein the patterned mask layer exposes a portion of the conductor layer; forming a first dielectric layer on the surface of the exposed portion of the conductor layer; removing the patterned mask layer; removing the conductor layer without covering the first dielectric layer, and using the remained conductor layer as the floating gate; forming a second dielectric layer on sidewalls of the floating gate; forming an erase gate above the floating gate and correspondingly above the control gate, wherein the erase gate covers the first dielectric layer and the second dielectric layer; and forming a source region and a drain region in the other one of each pair of the active regions of the substrate, and the source region and the drain region being respectively disposed at both sides of the floating gate.

According to one embodiment of the invention, the top edge of the floating gate is sharp-angled. The material of the floating gate is, for example, polysilicon or doped polysilicon, and the method for forming the same is, for example, chemical vapor deposition.

According to the embodiment of the invention, the control gate is, for example, a heavily doped region, and the method for forming the same is, for example, ion-implantation.

According to the embodiment of the invention, the material of the erase gate is, for example, polysilicon or doped polysilicon, and the method for forming the same is, for example, chemical vapor deposition.

According to the embodiment of the invention, the material of the gate oxide layer is, for example, silicon oxide, and the method for forming the same is, for example, thermal oxidation.

According to the embodiment of the invention, the device isolation structure is, for example, a field oxide layer and the method of forming the same is, for example, local oxidation of silicon.

In the non-volatile memory of the invention, since the heavily doped region formed in the substrate is used as the control gate, and an erase gate is formed above the floating gate, the chip size is not increased. Hence, the manufacturing cost will not be increased and the integration of the device will not be compromised. Additionally, in the erasing operation of the non-volatile memory of this invention, because a high voltage is applied on the erase gate for drawing the electrons to the erase gate to be erased, the non-volatile memory of this invention will not suffer the problem of damages in the gate oxide layer as the conventional single poly non-volatile memory, and the cycling number and the reliability of the memory device can be improved. Furthermore, the non-volatile memory of this invention affords shorter operating time for the erasing operation. In addition, because the top edge of the floating gate is sharp-angled, the erasing speed is further accelerated during the erasing operation.

DESCRIPTION OF EMBODIMENTS

FIGS. 3A-3Hare top views of the steps of the manufacturing method of the non-volatile memory according to one embodiment of the invention.

Firstly, with reference toFIG. 3A, a device isolation structure102is formed in a substrate100for defining a pair of active regions104aand104b. The device isolation structure102is, for example, a field oxide layer, and the method for forming the same is, for example, local oxidation of silicon (LOCOS).

Then, with reference toFIG. 3B, a control gate106is formed in one of the active regions104aand104bof the substrate100. In the embodiment, forming the control gate106in the active region104aof the substrate100is taken as an example. The control gate106is, for example, a heavily doped region formed in the substrate100, formed by ion-implantation.

Subsequently, with reference toFIG. 3C, a gate oxide layer108, a conductor layer110, and a patterned mask layer112are formed on the substrate100in sequence, and the patterned mask layer112exposes a portion of the conductor layer110. The material of the gate oxide layer108is, for example, silicon oxide, formed by thermal oxidation. The material of the conductor layer110is, for example, polysilicon or doped polysilicon, and the method for forming the same is, for example, chemical vapor deposition. Additionally, the material of the patterned mask layer112is, for example, silicon nitride or other suitable materials, and the method for forming the same is a chemical vapor deposition process.

Next, with reference toFIG. 3D, a dielectric layer114is formed on the surface of the exposed conductor layer110. The material of the dielectric layer114is, for example, silicon oxide formed by chemical vapor deposition. Alternatively, the dielectric layer114may be formed by thermal oxidation, and then the top edge of the conductor layer110is sharp-angled due to the high temperature of the thermal process.

Then, with reference toFIG. 3E, the patterned mask layer112is removed, and the conductor layer110not covered by the dielectric layer114is removed. Then, the remained conductor layer is used as a floating gate111. The method for removing the patterned mask layer112is, for example, an etching process. Additionally, the method for removing the conductor layer110is, for example, an etching process.

Then, with reference toFIG. 3F, a dielectric layer116is formed on the sidewalls of the floating gate111. The dielectric layer116is, for example, a nitrided oxide (NO) layer, and the method for forming the same is, for example, chemical vapor deposition.

Subsequently, with reference toFIG. 3G, an erase gate118is formed above the floating gate111and corresponding above the control gate106, wherein the erase gate118covers the dielectric layers114and116. The material of the erase gate118is, for example, polysilicon or doped polysilicon, and the method for the same is, for example, chemical vapor deposition.

Then, with reference toFIG. 3H, a source region120and a drain region122are formed in the active region104bof the substrate100, wherein the source region120and a drain region122are formed at both sides of the floating gate111respectively. The method for forming the source region120and the drain region122is, for example, ion-implantation.

Finally, after the manufacturing process of the non-volatile memory is completed, the subsequent inter layer dielectric (ILD), contact, conductor layer, and the like may be further fabricated. The process and related process parameters can be achieved by those skilled in the art and will not be described any more.

In view of the above, the manufacturing method of the non-volatile memory of the invention is compatible with the common semiconductor manufacturing process. That is, the manufacturing method of the non-volatile memory of the invention can be integrated in the common semiconductor manufacturing process without extra process steps. As such, the manufacturing costs and time are saved.

Next, the structure of the non-volatile memory according to this invention will be illustrated inFIG. 4.FIG. 4is a schematic cross-sectional view of the non-volatile memory taken along line I-I′ inFIG. 3H.

With reference toFIGS. 3H and 4, the non-volatile memory of the invention comprises the control gate106, the floating gate111, the gate oxide layer108, the source region120, the drain region122, the dielectric layer114, the dielectric layer116, and the erase gate118.

The control gate106is disposed in the substrate100, and the control gate106is, for example, a heavily doped region. Additionally, the floating gate111is disposed over the control gate106and located on a portion of the substrate110. The floating gate111comprises a coupling part and a gate part, wherein the coupling part of the floating gate111refers to the floating gate111located in the active region104a, the gate part of the floating gate111refers to the floating gate111located in the active region104b. The material of the floating gate111is, for example, polysilicon or doped polysilicon. In one embodiment, the top edge of the floating gate111is sharp-angled as shown by an arrow124inFIG. 4.

Additionally, the gate oxide layer108is disposed between the floating gate111and the substrate100, and the material is, for example, silicon oxide. The gate oxide layer108is used to isolate the floating gate111from the control gate106, as well as the floating gate111from the substrate100. The source region120is disposed in the substrate100and adjoins with one side of the gate part of the floating gate111. The drain region122is disposed in the substrate100and adjoins with the other side of the gate part of the floating gate111. The erase gate118is disposed over the coupling part of the floating gate111and covers the dielectric layers114and116, wherein the material of the erase gate118is, for example, polysilicon or doped polysilicon. The dielectric layer114is disposed on the floating gate111and the dielectric layer116is disposed on the sidewalls of the floating gate111, and the dielectric layers114and116are used to isolate the floating gate111from the erase gate118.

On the other hand, in the non-volatile memory of the invention, since a heavily doped region formed in the substrate is used as the control gate, and an erase gate is formed over the floating gate, the chip size is not increased, thereby not increasing the manufacturing cost.

Referring toFIG. 4for further understanding the erasing operation mode of the non-volatile memory of the embodiment of the invention.

When an erasing operation is performed for the non-volatile memory, a voltage V1is applied on the control gate106, a voltage V2is applied on the drain122, a voltage V3is applied on the source120, a voltage V4is applied on the erase gate118, and a voltage V5is applied on the substrate100. Thus, the electrons are drawn from the floating gate111to the erase gate118to be erased. The voltages V1, V2, V3, and V5are zero volts and the voltage V4is 12 volts. In other words, the erasing operation of the non-volatile memory of the invention is performed by applying a high voltage on the erase gate.

Furthermore, the operation for programming the non-volatile memory comprises, for example, applying a voltage V1on the control gate106, applying a voltage V2on the drain122, applying a voltage V3on the source120, applying a voltage V4on the erase gate118, and applying a voltage V5on the substrate100. Thus, the electrons bump and jump from the drain122to the floating gate111to be stored with the hot carrier, wherein the voltage V1is of 12 volts, the voltage V2is 8 volts, the voltages V3and V5are zero volts, and the voltage V4is floating.

Additionally, the method for reading the non-volatile memory comprises, for example, applying a voltage V1on the control106, applying a voltage V2on the drain122, applying a voltage V3on the source120, applying a voltage V4on the erase gate118, and applying a voltage V5on the substrate100. The voltage V1is of 2.5 volts, the voltage V2is of 2.5 volt, the voltages V3and V5are of zero volts, and the voltage V4is floating.

It should be noted that for the erasing operation of the non-volatile memory, the electrons are drawn to the erase gate to be erased without passing through the gate oxide layer. Therefore, the gate oxide layer of the non-volatile memory of this invention will not suffer damages as in the case of the conventional single poly non-volatile memory, thus the cycling number and the reliability of the memory device will not be influenced. Moreover, the operating time for the erasing operation of the non-volatile memory of this invention is shorter and has a more rapid operating speed.

In particular, the top edge of the floating gate of the non-volatile memory of the invention is sharp-angled. Therefore, when the erasing operation is performed, the electrons can be drawn to the erase gate through the top edge of the floating gate, and the erasing speed can be further accelerated.

In view of the above, the invention at least has the following advantages.

1. The erasing operation of the non-volatile memory of the invention affords a shorter operating time and has a more rapid operating speed.

2. The erasing operation of the non-volatile memory of the invention will not cause damage to the gate oxide layer, thereby increasing the cycling numbers and improving the reliability of the device.

3. The structure of the non-volatile memory of the invention increase the chip size, so that the manufacturing cost will not be increased and the integration of the device will not be influenced either.

4. The manufacturing method of the non-volatile memory of the invention can be integrated in the common semiconductor manufacturing process without any extra process step, thereby saving the manufacturing costs and time.