CIRCUIT CONVERSION METHOD, LATCH CIRCUIT, AND C-ELEMENT CIRCUIT

A circuit conversion method according to an embodiment of the present disclosure includes: setting a processing target path in an asynchronous logic circuit; first processing for determining whether or not a glitch occurs in each of a plurality of logic cells in the processing target path; second processing for performing conversion processing, the conversion processing being for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells, the one or more glitch suppression logic cells that are configured to suppress glitches, and perform same logical operation as the one or more logic cells; and, third processing for determining whether or not a glitch occurs in a subsequent-stage circuit in the processing target path after the second processing.

TECHNICAL FIELD

The present disclosure relates to a circuit conversion method to be performed on an asynchronous logic circuit, and a latch circuit and a C-element circuit that are used in such a circuit conversion method.

BACKGROUND ART

Logic circuits include a synchronous logic circuit and an asynchronous logic circuit. For example, PTL 1 discloses a circuit conversion method to be performed on an asynchronous logic circuit.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

In asynchronous logic circuits, it is desired to be able to suppress glitches, and it is expected to further suppress glitches.

It is desirable to provide a circuit conversion method, a latch circuit, and a C-element circuit that make it possible to suppress glitches.

A circuit conversion method according to an embodiment of the present disclosure includes: setting a processing target path in an asynchronous logic circuit; first processing for determining whether or not a glitch occurs in each of a plurality of logic cells in the processing target path; second processing for performing conversion processing, the conversion processing being for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells, the one or more glitch suppression logic cells that are configured to suppress glitches, and perform same logical operation as the one or more logic cells, and, third processing for determining whether or not a glitch occurs in a subsequent-stage circuit in the processing target path after the second processing.

A latch circuit according to an embodiment of the present disclosure includes a first inverter, first to eighth transistors, a NOR circuit, ninth to twelfth transistors, a second inverter, and a third inverter. The first inverter has an input terminal coupled to an input node, and an output terminal. The first transistor is a P-type transistor having a gate coupled to the output terminal of the first inverter, a source coupled to a power supply node, and a drain led to an first node. The second transistor is a P-type transistor having a gate to which a clock signal is to be inputted, a source coupled to the power supply node, and a drain led to the first node. The third transistor is an N-type transistor having a gate to which the clock signal is to be inputted, a drain led to the first node, and a source. The fourth transistor is an N-type transistor having a gate coupled to the output terminal of the first inverter, a drain coupled to the source of the third transistor, and a source coupled to a ground node. The fifth transistor is a P-type transistor having a gate coupled to the first node, a source coupled to the power supply node, and a drain led to a second node. The sixth transistor is an N-type transistor having a gate to which the clock signal is to be inputted, a drain led to the second node, and a source. The seventh transistor is an N-type transistor having a gate coupled to the input node, a drain coupled to the source of the sixth transistor, and a source. The eighth transistor is an N-type transistor having a gate coupled to the first node, a drain coupled to the source of the seventh transistor, and a source coupled to the ground node. The NOR circuit has a first input terminal to which a reset signal is to be inputted, a second input terminal coupled to the second node, and an output terminal coupled to a third node. The ninth transistor is a P-type transistor provided in a path coupling the power supply node and the second node, and having a gate coupled to the third node, a source, and a drain. The tenth transistor is a P-type transistor provided in a path coupling the power supply node and the second node, and having a gate to which the clock signal is to be inputted, a source, and a drain. The eleventh transistor is an N-type transistor provided in a path coupling the second node and the ground node, and having a gate coupled to the first node, a drain, and a source. The twelfth transistor is an N-type transistor provided in a path coupling the second node and the ground node, and having a gate coupled to the third node, a drain, and a source. The second inverter has an input terminal coupled to the third node, and an output terminal. The third inverter has an input terminal led to the output terminal of the second inverter, and an output terminal coupled to an output node.

A C-element circuit according to an embodiment of the present disclosure includes nineteenth to twenty-sixth transistors, a NOR circuit, a fourth inverter, a fifth inverter, and one or more transistors. The nineteenth transistor is a P-type transistor having a gate coupled to a first input node, a source coupled to a power supply node, and a drain. The twentieth transistor is a P-type transistor having a gate coupled to a second input node, a source coupled to the drain of the nineteenth transistor, and a drain led to a fourth node. The twenty-first transistor is an N-type transistor having a gate coupled to the second input node, a drain coupled to the fourth node, and a source. The twenty-second transistor is an N-type transistor having a gate coupled to the first input node, a drain coupled to the source of the twenty-first transistor, and a source coupled to a ground node. The twenty-third transistor is a P-type transistor having a gate coupled to the second input node, a source coupled to the power supply node, and a drain. The twenty-fourth transistor is a P-type transistor having a gate, a source coupled to the drain of the twenty-third transistor, a drain led to the fourth node. The twenty-fifth transistor is an N-type transistor having a gate, a drain led to the fourth node, and a source. The twenty-sixth transistor is an N-type transistor having a gate coupled to the second input node, a drain coupled to the source of the twenty-fifth transistor, and a source coupled to the ground node. The NOR circuit has a first input terminal to which a reset signal is to be inputted, a second input terminal coupled to the fourth node, and an output terminal coupled to a fifth node. The fourth inverter has an input terminal coupled to the fifth node, and an output terminal. The fifth inverter has an input terminal led to the output terminal of the fourth inverter, and an output terminal coupled to an output node. The one or more transistors is provided in one or more of a sixth path, a seventh path, an eighth path, a ninth path, and a tenth path. The sixth path couples the drain of the twentieth transistor and the fourth node. The seventh path couples the fourth node and the drain of the twenty-first transistor. The eighth path couples the drain of the twenty-fourth transistor and the fourth node. The ninth path couples the fourth node and the drain of the twenty-fifth transistor. The tenth path couples the output terminal of the fourth inverter and the input terminal of the fifth inverter.

In the circuit conversion method according to the embodiment of the present disclosure, the processing target path is set in the asynchronous logic circuit. The first processing is performed for determining whether or not a glitch occurs in each of the plurality of logic cells in the processing target path. The second processing for performing the conversion processing is performed. The conversion processing is for converting one or more logic cells in which a glitch is determined to occur in this first processing into one or more glitch suppression logic cells that are configured to suppress glitches and perform the same logical operation as the one or more logic cells. Thereafter, after this second processing, the third processing is performed for determining whether or not a glitch occurs in the subsequent-stage circuit in the processing target path.

MODES FOR CARRYING OUT THE INVENTION

Some embodiments of the present disclosure are described below in detail with reference to the drawings. It is to be noted that description is given in the following order.1. First Embodiment (An application example to a bundled-data logic circuit)2. Second Embodiment (An application example to a 2-wire SDI circuit)

1. First Embodiment

Configuration Example

FIG.1illustrates a configuration example of an asynchronous logic circuit1to which a circuit conversion method according to a first embodiment is applied. The asynchronous logic circuit1is what is called a bundled-data asynchronous logic circuit. The asynchronous logic circuit1illustrated inFIG.1is an example of a most basic configuration. In actuality, as described later, the asynchronous logic circuit1may be more complicated than this circuit configuration. The asynchronous logic circuit1includes a data-path circuit10and a handshake circuit20.

The data-path circuit10is configured to perform processing on a piece of data DT. The piece of data DT is supplied from the left to the right inFIG.1. The data-path circuit10includes a plurality of registers11and a plurality of combinational circuits12. In this example, the registers11and the combinational circuits12are alternately disposed. The register11includes, for example, a plurality of latch circuits, and is configured to latch the piece of data DT supplied from the combinational circuit12in a preceding stage, on the basis of a signal LCK that is a local clock. The combinational circuit12is configured to perform a logical operation on the piece of data DT supplied from the register11in a preceding stage and supply a thus-obtained piece of data DT to the register11in a subsequent stage.

The handshake circuit20is configured to generate a plurality of signals LCK on the basis of a signal REQ and a signal ACK and supply the plurality of signals LCK generated to the plurality of respective registers11in the data-path circuit10. The signal REQ is supplied from the left to the right inFIG.1. The handshake circuit20includes a plurality of control circuits21and a plurality of delay circuits22.

The control circuit21is configured to generate the signal LCK that is a local clock, and the signals REQ and ACK on the basis of the supplied signal REQ and the supplied signal ACK. Specifically, the control circuit21is supplied with the signal REQ from the control circuit21in a preceding stage through the delay circuit22, and is supplied with the signal ACK from the control circuit21in a subsequent stage, and generates the signals LCK, REQ, and ACK on the basis of these signals REQ and ACK. Thereafter, the control circuit21supplies the generated signal LCK to the register11, supplies the generated signal REQ to the control circuit21in the subsequent stage through the delay circuit22, and supplies the generated signal ACK to the control circuit21in the preceding stage. The signal REQ is supplied from the left to the right inFIG.1; therefore, the plurality of control circuits21issues the signal ACK in order from the control circuit21on the left.

FIG.2illustrates a configuration example of the control circuit21. InFIG.2, the signal REQ to be inputted to the control circuit21is represented by a signal REQ_IN, and the signal REQ to be outputted from the control circuit21is represented by a signal REQ_OUT. In addition, the signal ACK to be inputted to the control circuit21is represented by a signal ACK_IN, and the signal ACK to be outputted from the control circuit21is represented by a signal ACK_OUT.

The control circuit21includes a C-element29. The C-element29is what is called a waiting circuit, and has two input terminals, a reset terminal, and an output terminal. The signal REQ_IN and an inverted signal of the signal ACK_IN are inputted to the two input terminals. A reset signal RST is inputted to the reset terminal. The C-element29changes the signal LCK at the output terminal to a high level in a case where both the signal REQ_IN and the inverted signal of the signal ACK_IN are at the high level, changes the signal LCK at the output terminal to a low level in a case where both the signal REQ_IN and the inverted signal of the signal ACK_IN are at the low level, and maintains the signal LCK at the output terminal in other cases. In addition, the C-element29changes the signal LCK at the output terminal to the low level on the basis of the reset signal RST. It is to be noted that, the reset terminal is provided in this example, but the reset terminal may not be provided. In this case, signals having the same levels as each other are inputted to the two input terminals of the C-element29, thereby making it possible to determine the signal at the output terminal to the low level or the high level.

FIG.3illustrates an operation example of the control circuit21, where (A) indicates a waveform of the signal REQ_IN, (B) indicates a waveform of the signal ACK_IN, (C) indicates a waveform of the signal LCK, (D) indicates a waveform of the signal REQ_OUT, and (E) indicates a waveform of the signal ACK_OUT.

At a timing t1, the signal REQ_IN changes from the low level to the high level ((A) ofFIG.3). At this time, the signal ACK_IN is at the low level ((B) ofFIG.3); therefore, the inverted signal of the signal ACK_IN is at the high level. Accordingly, both the signal REQ_IN and the inverted signal of the signal ACK_IN are changed to the high level, which causes the C-element29to change the signal LCK from the low level to the high level ((C) ofFIG.3) and similarly change the signals REQ_OUT and ACK_OUT from the low level to the high level ((D) and (E) ofFIG.3).

Next, at a timing t2, the signal ACK_IN changes from the low level to the high level ((B) ofFIG.3). In other words, the inverted signal of the signal ACK_IN changes from the high level to the low level. At this time, the signal REQ_IN is at the high level ((A) ofFIG.3). Accordingly, the signals LCK, REQ_OUT, and ACK_OUT are unchanged and maintained at the high level ((C) to (E) ofFIG.3).

Next, at a timing t3, the signal REQ_IN changes from the high level to the low level ((A) ofFIG.3). At this time, the signal ACK_IN is at the high level ((B) ofFIG.3); therefore, the inverted signal of the signal ACK_IN is at the low level. Accordingly, both the signal REQ_IN and the inverted signal of the signal ACK_IN are changed to the low level, which causes the C-element29to change the signal LCK from the high level to the low level ((C) ofFIG.3) and similarly change the signals REQ_OUT and ACK_OUT from the high level to the low level ((D) and (E) ofFIG.3).

Next, at a timing t4, the signal ACK_IN changes from the high level to the low level ((B) ofFIG.3). In other words, the inverted signal of the signal ACK_IN changes from the low level to the high level. At this time, the signal REQ_IN is at the low level ((A) ofFIG.3). Accordingly, the signals LCK, REQ_OUT, and ACK_OUT are unchanged and maintained at the low level ((C) to (E) ofFIG.3).

As described above, the control circuit21performs an operation on the basis of the signals REQ_IN and ACK_IN that are four-phase signals to thereby generate the signals LCK, REQ_OUT, and ACK_OUT.

Next, a specific circuit example of the C-element29is described with reference to some examples.

FIG.4illustrates a configuration example of the C-element29. The C-element29includes two input terminals IN1and IN2, a reset terminal INR, an output terminal OUT, a logical AND (AND) circuit101, a logical OR (OR) circuit102, a negative AND (NAND) circuit103, and a latch circuit104. The AND circuit101is configured to find AND of a signal at the input terminal IN1and a signal at the input terminal IN2. The OR circuit102is configured to find OR of the signal at the input terminal IN1and the signal at the input terminal IN2. The NAND circuit103is configured to find NAND of an output signal of the OR circuit102and a signal at the reset terminal INR. The latch circuit104is a D-latch, and has a terminal D coupled to a power supply node of a power supply voltage VDD, a terminal G to be supplied with an output signal of the AND circuit101, and a terminal R to be supplied with an output signal of the NAND circuit103. The latch circuit104has a terminal Q coupled to the output terminal OUT.

FIG.5illustrates another configuration example of the C-element29. In this example, the C-element29is configured with use of what is called a majority gate. The C-element29includes two input terminals IN1and IN2, the reset terminal INR, the output terminal OUT, AND circuits111to113, a negative OR (NOR) circuit114, and an AND circuit115. The AND circuit111is configured to find AND of a signal at the input terminal IN1and an output signal of the AND circuit115. The AND circuit112is configured to find AND of the signal at the input terminal IN1and a signal at the input terminal IN2. The AND circuit113is configured to find AND of the signal at the input terminal IN2and the output signal of the AND circuit115. The NOR circuit114is configured to find NOR of output signals of the AND circuits111to113. The AND circuit115is configured to find AND of an inverted signal of an output signal of the NOR circuit114and a signal at the reset terminal NR. The AND circuit115has an output terminal coupled to the output terminal OUT.

As described above, it is possible to configure the C-element29with use of the latch circuit104, for example, as illustrated inFIG.4, or it is possible to configure the C-element29with use of the majority gate, for example, as illustrated inFIG.5.

The delay circuit22(FIG.1) is provided in a supply path of the signal REQ, and is configured to delay the signal REQ. A delay amount of the delay circuit22is set to a maximum value of a delay amount in a corresponding combinational circuit12.

With this configuration, in the asynchronous logic circuit1, the combinational circuit12supplies the piece of data DT to the register11. The delay circuit22delays the signal REQ, and supplies the delayed signal REQ to the control circuit21. This control circuit21generates the signal LCK on the basis of the delayed signal REQ, and the register11latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21supplies the signal ACK to the control circuit21in the preceding stage. In a case where the delay amount in the combinational circuit12is small, the delay amount in the delay circuit22is also set to a small value, and in a case where the delay amount in the combinational circuit12is large, the delay amount in the delay circuit22is set to a large value.

In the example inFIG.1, the control circuit21is coupled one-to-one to the control circuit21in the preceding stage through the delay circuit22, and is coupled one-to-one to the control circuit21in the subsequent stage through the delay circuit22. Likewise, the register11is coupled one-to-one to the register11in the preceding stage with the combinational circuit12interposed therebetween, and is coupled one-to-one to the register11in the subsequent stage with the combinational circuit12interposed therebetween. However, this is not limitative, and the control circuit21may be coupled to one-to-multiple to a plurality of control circuits21. In addition, the register11may be coupled to one-to-multiple to a plurality of registers11. Hereinafter, description is given of one-to-two coupling as an example.

FIG.6schematically illustrates an example of one-to-two coupling. A symbol FF indicates fork coupling in which a signal from one circuit is split into two, and a symbol JJ indicates join coupling in which two signals from two circuits are joined into one. In the fork coupling, the signal from one circuit is supplied to both of two circuits, and in the join coupling, both of two signals from two circuits are supplied to one circuit.

FIG.7schematically illustrates another example of one-to-two coupling. A symbol SS indicates split coupling in which a signal from one circuit is split into two, and a symbol MM indicates merge coupling in which two signals from two circuits are joined into one. In the split coupling, a signal from one circuit is supplied to one of two circuits, and in the merge coupling, one of two signals from two circuits is supplied to one circuit.

FIG.8schematically illustrates a specific example of the fork coupling and the join coupling illustrated inFIG.6. InFIG.8, a path of a piece of data DT is indicated by a thick line. A left half inFIG.8indicates the fork coupling, and a right half inFIG.8indicates the join coupling.

First, the fork coupling is described. In the fork coupling, the handshake circuit20includes a C-element23.

In the data-path circuit10, the register11(a register11A) supplies a piece of data DT to the combinational circuit12. The combinational circuit12performs a logical operation on the basis of this piece of data DT to thereby generate two pieces of data DT, and supplies these two pieces of data DT to respective two registers11(registers11B and11C).

In the handshake circuit20, the control circuit21(a control circuit21A) supplies the signal REQ to two control circuits (control circuits21B and21C) through respective two delay circuits22. The control circuit21B supplies the signal ACK to the C-element23, and the control circuit21C supplies the signal ACK to the C-element23. The C-element23generates the signal ACK on the basis of two signals ACK supplied from the control circuits21B and21C, and supplies the generated signal ACK to the control circuit21A.

With this configuration, the combinational circuit12performs a logical operation on the basis of the piece of data DT supplied from the register11A to thereby generate two pieces of data DT, and supplies these two pieces of data DT to respective two registers11B and11C. The control circuit21B generates the signal LCK on the basis of the signal REQ supplied from the control circuit21A through the delay circuit22, and supplies the generated signal LCK to the register11B. The register11B latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21B supplies the signal ACK to the C-element23. Likewise, the control circuit21C generates the signal LCK on the basis of the signal REQ supplied from the control circuit21A through the delay circuit22, and supplies the generated signal LCK to the register11C. The register11C latches the piece of data DT supplied from the combinational circuit12on the basis of the signal LCK. The control circuit21C supplies the signal ACK to the C-element23. When both of two signals ACK supplied from the control circuits21B and21C are changed to the high level, the C-element23changes the signal ACK to be supplied to the control circuit21A to the high level.

Next, the join coupling is described. In the join coupling, the handshake circuit20includes a C-element24.

In the data-path circuit10, the register11B supplies a piece of data DT to the combinational circuit12, and the register11C supplies a piece of data DT to the combinational circuit12. The combinational circuit12performs a logical operation on the basis of two pieces of data DT supplied from the registers11B and11C to thereby generate a piece of data DT, and supplies this piece of data DT to the register11(a register11D).

In the handshake circuit20, the control circuit21B supplies the signal REQ to the C-element24through the delay circuit22, and the control circuit21C supplies the signal REQ to the C-element24through the delay circuit22. The C-element24generates the signal REQ on the basis of two signals REQ supplied from the control circuits21B and21C, and supplies the generated signal REQ to the control circuit21D. The control circuit21D supplies the signal ACK to each of two control circuits21B and21C.

With this configuration, the combinational circuit12performs a logical operation on the basis of two pieces of data DT supplied from the registers11B and11C to thereby generate a piece of data DT, and supplies this piece of data DT to the register11D. When both of two signals REQ supplied from the control circuits21B and21C are changed to the high level, the C-element24changes the signal REQ to be supplied to the control circuit21D to the high level. The control circuit21D generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11D. The register11D latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21D supplies the signal ACK to the control circuits21B and21C.

FIG.9illustrates a specific example of the split coupling and the merge coupling illustrated inFIG.7. A left half inFIG.9illustrates the split coupling, and a right half inFIG.9illustrates the merge coupling.

First, the split coupling is described. In the split coupling, the data-path circuit10includes a demultiplexer (DMX)13, and the handshake circuit20includes a demultiplexer (DMX)31and an OR circuit32.

In the data-path circuit10, the register11(the register11A) supplies a piece of data DT to the combinational circuit12. The combinational circuit12performs a logical operation on the basis of this piece of data DT to thereby generate a piece of data DT and generate a selection signal SELL. The demultiplexer13supplies the piece of data supplied from the combinational circuit12to the resister11corresponding to the selection signal SEL1of two registers11(the registers11B and11C).

In the handshake circuit20, the control circuit21(the control circuit21A) supplies the signal REQ to the demultiplexer31. The demultiplexer31supplies the signal REQ supplied from the control circuit21A to the control circuit21corresponding to the selection signal SEL1of two control circuits21(the control circuits21B and21C). The control circuit21B supplies the signal ACK to the OR circuit32, and the control circuit21C supplies the signal ACK to the OR circuit32. The OR circuit32finds OR of two signals ACK supplied from the control circuits21B and21C to thereby generate the signal ACK, and supplies the generated signal ACK to the control circuit21A.

With this configuration, the combinational circuit12performs a logical operation to thereby generate the selection signal SEL1. For example, in a case where the selection signal SEL1is at the high level, the demultiplexer13supplies the piece of data DT supplied from the combinational circuit12to the register11B, and the demultiplexer31supplies the signal REQ supplied from the control circuit21A to the control circuit21B through the delay circuit22. The control circuit21B generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11B. Accordingly, the register11B latches the piece of data DT supplied from the demultiplexer13on the basis of the signal LCK supplied from the control circuit21B. Thereafter, the control circuit21B supplies the signal ACK to the control circuit21A through the OR circuit32.

For example, in a case where the selection signal SEL1is at the low level, the demultiplexer13supplies the piece of data DT supplied from the combinational circuit12to the register11C, and the demultiplexer31supplies the signal REQ supplied from the control circuit21A to the control circuit21C through the delay circuit22. The control circuit21C generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11C. Accordingly, the register11C latches the piece of data DT supplied from the demultiplexer13on the basis of the signal LCK supplied from the control circuit21C. Thereafter, the control circuit21C supplies the signal ACK to the control circuit21A through the OR circuit32.

Next, the merge coupling is described. In the merge coupling, the data-path circuit10includes a multiplexer (MUX)14, and the handshake circuit20includes an OR circuit33and C-elements34to36.

In the data-path circuit10, the register11B supplies the piece of data DT to the combinational circuit12(a combinational circuit12B) subsequent to the register11B, and the register11C supplies the piece of data DT to the combinational circuit12(a combinational circuit12C) subsequent to the register11C. The combinational circuit12B performs a logical operation on the basis of the piece of data DT supplied from the register11B to thereby generate a piece of data DT, and supplies this piece of data DT to the multiplexer14. The combinational circuit12C performs a logical operation on the basis of the piece of data DT supplied from the register11C to thereby generate a piece of data DT, and supplies this piece of data DT to the multiplexer14. The multiplexer14selects one of two pieces of data DT supplied from the combinational circuits12B and12C on the basis of a selection signal SEL2supplied from the handshake circuit20, and supplies the selected piece of data DT to the register11(a register11D).

In the handshake circuit20, the control circuit21B supplies the signal REQ to the OR circuit33through the delay circuit22, and the control circuit21C supplies the signal REQ to the OR circuit33through the delay circuit22. The OR circuit33finds OR of two signals REQ supplied from the control circuits21B and21C to thereby generate the signal REQ, and supplies the generated signal REQ to the control circuit21D. The C-element34generates the selection signal SEL2on the basis of the signal REQ supplied from the control circuit21B and an inverted signal of the signal REQ supplied from the control circuit21C. In a case where the signal REQ supplied from the control circuit21B is at the high level and the signal REQ supplied from the control circuit21C is at the low level, the C-element34changes the selection signal SEL2to the high level. In addition, in a case where the signal REQ supplied from the control circuit21B is at the low level and the signal REQ supplied from the control circuit21C is at the high level, the C-element34changes the selection signal SEL2to the low level. The control circuit21D supplies the signal ACK to two C-elements35and36. The C-element35generates the signal ACK on the basis of the signal REQ supplied from the control circuit21B and the signal ACK supplied from the control circuit21D. The C-element36generates the signal ACK on the basis of the signal REQ supplied from the control circuit21C and the signal ACK supplied from the control circuit21D.

With this configuration, the C-element34generates the selection signal SEL2on the basis of the signal REQ supplied from the control circuit21B and the inverted signal of the signal REQ supplied from the control circuit21C. For example, in a case where the signal REQ supplied from the control circuit21B is at the high level and the signal REQ supplied from the control circuit21C is at the low level, the C-element34changes the selection signal SEL2to the high level. In this case, the multiplexer14supplies the piece of data DT supplied from the combinational circuit12B to the register11D. The control circuit21D generates the signal LCK on the basis of the signal REQ supplied from the control circuit21B, and supplies the generated signal LCK to the register11D. Accordingly, the register11D latches the piece of data DT supplied from the multiplexer14on the basis of the signal LCK supplied from the control circuit21D. Thereafter, the control circuit21D supplies the signal ACK to the C-element35. The signal REQ supplied from the control circuit21B is at the high level; therefore, the C-element35supplies the signal ACK supplied from the control circuit21D to the control circuit21B.

For example, in a case where the signal REQ supplied from the control circuit21B is at the low level and the signal REQ supplied from the control circuit21C is at the high level, the C-element34changes the selection signal SEL2to the low level. In this case, the multiplexer14supplies the piece of data DT supplied from the combinational circuit12C to the register11D. The control circuit21D generates the signal LCK on the basis of the signal REQ supplied from the control circuit21C, and supplies the generated signal LCK to the register11D. Accordingly, the register11D latches the piece of the data DT supplied from the multiplexer14on the basis of the signal LCK supplied from the control circuit21D. Thereafter, the control circuit21D supplies the signal ACK to the C-element35. The signal REQ supplied from the control circuit21C is at the high level; therefore, the C-element35supplies the signal ACK supplied from the control circuit21D to the control circuit21C.

FIG.10illustrates an example of one-to-four split coupling. In this example, the handshake circuit20includes control circuits21E to21I, inverters37and38, AND circuits41to48, and an OR circuit39.

In the data-path circuit10, the register11(a register11E) supplies a piece of data DT to the combinational circuit12. The combinational circuit12performs a logical operation on the basis of this piece of data DT to thereby generate a piece of data DT, and supplies this piece of data DT to one of four registers11(registers11F to11I) in a subsequent stage. The combinational circuit12generates selection signals B1and B0. The combinational circuit12sets the selection signals B1and B0to “00” in a case of supplying the piece of data DT to the register11F, sets the selection signals B1and B0to “01” in a case of supplying the piece of data DT to the register11G, sets the selection signals B1and B0to “10” in a case of supplying the piece of data DT to the register11H, and sets the selection signals B1and B0to “11” in a case of supplying the piece of data DT to the register11I.

In the handshake circuit20, the inverter37inverts the selection signal B0, and the inverter38inverts the selection signal B1. The AND circuit41finds AND of an output signal of the inverter37and an output signal of the inverter38. The AND circuit42finds AND of the selection signal B0and the output signal of the inverter38. The AND circuit43finds AND of the output signal of the inverter37and the selection signal B1. The AND circuit44finds AND of the selection signal B0and the selection signal B1. The AND circuit45finds AND of an output signal of the AND circuit41and the signal REQ supplied from the control circuit21E through the delay circuit, and supplies a thus-obtained signal to the control circuit21F through the delay circuit. The AND circuit46finds AND of an output signal of the AND circuit42and the signal REQ supplied from the control circuit21E through the delay circuit, and supplies a thus-obtained signal to the control circuit21G through the delay circuit. The AND circuit47finds AND of an output signal of the AND circuit43and the signal REQ supplied from the control circuit21E through the delay circuit, and supplies a thus-obtained signal to the control circuit21H through the delay circuit. The AND circuit48finds AND of an output signal of the AND circuit44and the signal REQ supplied from the control circuit21E through the delay circuit, and supplies a thus-obtained signal to the control circuit21I through the delay circuit.

With this configuration, the combinational circuit12performs a logical operation to thereby generate the selection signals B1and B0. For example, in a case where the selection signals B1and B0are “00”, the combinational circuit12supplies the piece of data DT to the register11F. In a case where the selection signals B1and B0are “00” in such a manner, the output signal of the AND circuit41is changed to the high level, and the signal REQ generated by the control circuit21E is supplied to the control circuit21F through the AND circuit45. The control circuit21F generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11F. The register11F latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21F supplies the signal ACK to the control circuit21E through the OR circuit39.

Likewise, for example, in a case where the selection signals B1and B0are “01”, the combinational circuit12supplies the piece of data DT to the register11G. In a case where the selection signals B1and B0are “01” in such a manner, the output signal of the AND circuit42is changed to the high level, and the signal REQ generated by the control circuit21E is supplied to the control circuit21G through the AND circuit46. The control circuit21G generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11G. The register11G latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21G supplies the signal ACK to the control circuit21E through the OR circuit39.

Likewise, for example, in a case where selection signals B1and B0are “10”, the combinational circuit12supplies the piece of data DT to the register11H. In a case where selection signals B1and B0are “10” in such a manner, the output signal of the AND circuit43is changed to the high level, and the signal REQ generated by the control circuit21E is supplied to the control circuit21H through the AND circuit47. The control circuit21H generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11H. The register11H latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21H supplies the signal ACK to the control circuit21E through the OR circuit39.

Likewise, for example, in a case where selection signals B1and B0are “11”, the combinational circuit12supplies the piece of data DT to the register11I. In a case where selection signals B1and B0are “11” in such a manner, the output signal of the AND circuit44is changed to the high level, and the signal REQ generated by the control circuit21E is supplied to the control circuit21I through the AND circuit48. The control circuit21I generates the signal LCK on the basis of this signal REQ, and supplies the generated signal LCK to the register11I. The register11I latches the piece of data DT supplied from the combinational circuit12on the basis of this signal LCK. Thereafter, the control circuit21I supplies the signal ACK to the control circuit21E through the OR circuit39.

Incidentally, in recent years, a semiconductor process size has been further reduced, and a power supply voltage has been further lowered. In such a situation, glitches easily occur. In the asynchronous logic circuit1, using a four-phase signal as illustrated inFIG.3makes it possible to hinder glitches from occurring. However, when the semiconductor process size is further reduced and the power supply voltage is further lowered as described above, the variation tendency of a delay amount in a logic cell may become more complicated. For example, variations in delay amounts of a plurality of logic cells provided in one signal path in one semiconductor chip may vary differently from each other. Accordingly, even in a case where the four-phase signal as illustrated inFIG.3is used, glitches may occur.

FIG.11illustrates an example of occurrence of glitches. This example focuses on a path (a processing target path P) including the inverters37and38and the AND circuits43and47. For example, there is a possibility that a glitch occurs in a piece of data DT (a reference sign W1) generated by a circuit preceding to the register11E. This glitch may propagate to an output signal (a reference sign W2) of the register11E. In addition, there is a possibility that glitches occur in the selection signals B1and B0(a reference sign W3) generated by the combinational circuit12. This glitch may propagate to an output signal (a refence sign W4) of the AND circuit43. Thereafter, this glitch may further propagate to an output signal (a reference sign W5) of the AND circuit47. Thereafter, this glitch may further propagate to an output signal (a reference sign W6) of a C-element of the control circuit21H. In this case, glitches occur in the signals LCK, REQ, and ACK generated by this control circuit21, which causes a circuit malfunction.

In a case where the glitches occur as described above, a circuit malfunction easily occurs. In addition, in a case where glitches occur, power consumption is increased by switching. Accordingly, it is desirable to suppress glitches.

In the present technology, when the asynchronous logic circuit1is designed, a circuit is converted on the basis of design data of the asynchronous logic circuit1so as to hinder glitches from occurring. Specifically, in this circuit conversion method, for example, in a case where a predetermined condition is satisfied, a logic cell to which a plurality of signals are to be inputted in the processing target path P is converted into a glitch suppression cell that is configured to suppress glitches. The glitch suppression cell is a logic cell that hinders glitches from occurring or hinders glitches from propagating. Specifically, the glitch suppression cell is a logic cell in which a delay amount in this logic cell is larger than a time difference between transition timings of a plurality of signals to be inputted. In addition, in this circuit conversion method, in a case where the predetermined condition is satisfied, a logic cell in the processing target path P is converted into a QDI (Quasi-Delay Insensitive) logic cell. This QDI logic cell is a 2-wire logic cell, and is configured to hinder glitches from occurring. In the present technology, such a circuit conversion method makes it possible to impalement the asynchronous logic circuit1in which glitches are suppressed.

Next, description is given of an operation and workings of the asynchronous logic circuit1according to the present embodiment.

(Overview of Overall Operation)

First, description is given of an overview of an overall operation of the asynchronous logic circuit1with reference toFIG.1. The data-path circuit10performs processing on the piece of data DT. The register11includes, for example, a plurality of latch circuits, and latches the piece of data DT supplied from the combinational circuit12in a preceding stage on the basis of the signal LCK that is a local clock. The combinational circuit12performs a logical operation on the piece of data DT supplied from the register11in a preceding stage, and supplies the obtained piece of data DT to the register11in a subsequent stage. The handshake circuit20generates a plurality of signals LCK on the basis of the signal REQ and the signal ACK, and supplies the plurality of signals LCK generated to the plurality of respective registers11in the data-path circuit10.

A circuit conversion method that implements the asynchronous logic circuit1in which glitches are suppressed is described in detail below. In this circuit conversion method, a computer executes a program to thereby convert a circuit on the basis of the design data of the asynchronous logic circuit1so as to hinder glitches from occurring.

FIGS.12A to12Cillustrate an example of the circuit conversion method by the computer.

First, the computer identifies the processing target path P where circuit conversion is to be performed, and obtains the stage number M of logic cells in the processing target path P (step S101). In the design data of the asynchronous logic circuit1, the data-path circuit10and the handshake circuit20are defined as modules different from each other. The computer is able to identify a port of a signal to be inputted from the combinational circuit12of the data-path circuit10to the handshake circuit20, on the basis of such design data, and is able to identify a signal path from this port to the input terminal of the control circuit21in the handshake circuit20. The computer identifies such a signal path as the processing target path P. In the example inFIG.11, the computer identifies a path including the inverters37and38and the AND circuits43and47as the processing target path P. Thereafter, the computer obtains the stage number (the stage number M) of logic cells in this processing target path P.

Next, the computer sets a variable i to “1” (i=1) (step S102), and performs conversion processing A1(step S103). In this conversion processing A1, the computer sets all logic cells in i-th and subsequent stages in the processing target path P as processing targets. In this example, the variable i is set to “1” in step S102; therefore, the computer sets all logic cells in “1”st and subsequent stages in the processing target path P as processing targets of the conversion processing A1.

FIG.13illustrates an example of a subroutine of the conversion processing A1. In this conversion processing A1, the computer converts each of all logic cells in which a glitch possibly occurs out of all the logic cells in the i-th stage (the first stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells. This operation is described in detail below.

The computer confirms whether or not a plurality of signals is to be inputted to the logic cell in the i-th stage in the processing target path P (step S151). In a case where one signal is to be inputted to the logic cell in the i-th stage (“N” in step S151), the processing proceeds to step S156.

In step S151, in a case where a plurality of signals is to be inputted to the logic cell in the i-th stage (step S151), the computer confirms whether or not the logic cell in the i-th stage satisfies a glitch determination condition C (step S152). The glitch determination condition C is a condition for determining whether or not a glitch possibly occurs in the logic cell. Specifically, the glitch determination condition C is that a delay amount in the logic cell is less than or equal to a time difference between transition timings of the plurality of signals to be inputted. In a case where this logic cell does not satisfy the glitch determination condition C (“N” in step S153), the computer determines that no glitch occurs in this logic cell, and the processing proceeds to step S156.

In a case where this logic cell satisfies the glitch determination condition C in step S152(“Y” in step S153), the computer determines that a glitch possibly occurs in this logic cell, and converts this logic cell into one or a plurality of glitch suppression cells that performs the same operation (step S154). The glitch suppression cell is a logic cell that performs the same logical operation as the original logic cell, and has a delay amount larger than that of the original logic cell. For example, it is possible to prepare a circuit library, in which various glitch suppression cells are registered, in advance. In this case, the computer obtains a glitch suppression cell corresponding to an i-th logic cell from this circuit library, and converts the i-th logic cell into the obtained glitch suppression cell. Specifically, for example, in a case where the logic cell in the i-th stage is an AND circuit, the computer obtains a glitch suppression cell of an AND circuit having a delay amount larger than that of this AND circuit, and converts the logic cell (the AND circuit) in the i-th stage into this glitch suppression cell. For example, there is a possibility that an AND circuit to which two signals are to be inputted is prepared in the circuit library, but an AND circuit to which three signals are to be inputted is not prepared in the circuit library. In this case, in a case where the logic cell in the i-th stage is an AND circuit to which three signals are to be inputted, the computer first converts this AND circuit to which three signals are to be inputted into, for example, a logic circuit including two AND circuits to which two signals are to be inputted, and converts the two AND circuits into two glitch suppression cells.

Thereafter, the computer updates timing information in the design data (step S155). That is, the computer has converted the logic cell into one or a plurality of glitch suppression cells in step S154; therefore, the delay amount in this logic cell has been changed. Accordingly, the computer updates the timing information in the design data.

Next, the computer confirms whether or not the variable i is equal to the stage number M (i=M) (step S156). In a case where the variable i is smaller than the stage number M (“N” in step S156), the computer increments the variable i (step S157), and the processing returns to step S151. The computer repeats processing in steps S151to S157until the variable i becomes equal to the stage number M. Thus, out of all the logic cells in the first and subsequent stages in the processing target path P, each of all the logic cells in which a glitch possibly occurs is converted into one or a plurality of glitch suppression cells.

In a case where the variable i is equal to the stage number M in step S156(“Y” in step S156), the computer ends the subroutine of the conversion processing A1.

Next, the computer confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P (step S104). In the example inFIG.11, the computer confirms whether or not a glitch occurs in an output of a C-element in the control circuit21H in a subsequent stage in the processing target path P. In a case where no glitch occurs (“N” in step S105), this processing ends.

In a case where a glitch occurs in step S104(“Y” in step S105), the computer converts this C-element into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this C-element (step S106). In a case where no glitch occurs (“N” in step S107), this processing ends.

In a case where a glitch occurs in step S106(“Y” in step S107), the computer restores the C-element converted in step S106, and all logic cells converted in step S103in the processing target path P to an initial state (step S108).

Next, the computer sets a variable j to “1” (j=1) (step S109).

Next, the computer converts an input signal to the logic cell in a j-th stage in the processing target path P into a 2-wire signal, converts the logic cell in the j-th stage into a QDI logic cell, and converts an output signal of this QDI logic cell into a 1-wire signal (step S110). This causes the output signal of this QDI logic cell to be inputted to the logic cell in a stage subsequent to the QDI logic cell (in a j+1-th stage). It is to be noted that in a case where the logic cell in a stage (a j−1-th stage) preceding to the logic cell in the j-th stage is a QDI logic cell, a 2-wire signal outputted from the logic cell in the j−1-th stage is supplied as it is to the logic cell in the j-th stage. A method of converting a logic cell into a QDI logic cell is described in the following literature, for example. Kouki Uchida, “Studies on Testing QDI Asynchronous Circuits”, Master's Thesis, Nara Institute of Science and Technology, Nakashima Laboratory, 2012

Next, the computer confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P (step S111). In a case where no glitch occurs (“N” in step S112), this processing ends.

In a case where a glitch occurs in step S11(“Y” in step S112), the computer converts this C-element into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this C-element (step S113). In a case where no glitch occurs (“N” in step S114), this processing ends.

In a case where a glitch occurs in step S113(“Y” in step S114), the computer restores the C-element converted in step S113to the initial state (step S115).

Next, the computer sets the variable i to “j+1” (i=j+1) (step S116), and performs the conversion processing A1(step S117). In the conversion processing A1, as illustrated inFIG.13, the computer converts each of all logic cells in which a glitch possibly occurs out of all logic cells in the i-th stage (a j+1-th stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells.

Next, the computer confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P (step S118). In a case where no glitch occurs (“N” in step S119), this processing ends.

In a case where a glitch occurs in step S118(“Y” in step S119), the computer converts this C-element into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this C-element (step S120). In a case where no glitch occurs (“N” in step S121), this processing ends.

In a case where a glitch occurs in step S120(“Y” in step S121), the computer restores the C-element converted in step S120to the initial state, and restores all logic cells other than the QDI logic cell in the processing target path P to the initial state (step S122). Thus, all the logic cells converted in step S117in the processing target path P are restored to the initial state.

Next, the computer confirms whether or not the variable j is equal to the stage number M (j=M) (step S123). In a case where the variable j is smaller than the stage number M (“N” in step S123), the computer increments the variable j (step S124), and the processing returns to step S110. Thus, the computer converts the logic cell in the j+l-th stage into a QDI logic cell in step S110. By this operation, the computer converts logic cells into QDI logic cells in order from the logic cell in the first stage, and the number of QDI logic cells is increased by one. The computer repeats operations in steps S110to S124until no glitch occurs.

In a case where the variable j is equal to the stage number M in step S123(“Y” in step S123), the computer ends this processing.

Using this circuit conversion method makes it possible to suppress glitches in one or more of the AND circuit43(the reference sign W4), and the AND circuit47(the reference sign W5) in the processing target path P illustrated inFIG.11, for example, and the C-element (the reference sign W6) of the control circuit21H in the subsequent stage in the processing target path P. In addition, similar circuit conversion is performed also on the circuit preceding to the register11E, thereby making it possible to suppress glitches in the circuit preceding to the register11E (the reference sign W1). In this circuit conversion method, in the asynchronous logic circuit1, various processing target paths P are set, and processing is performed on each of these processing target paths P. As a result, in the asynchronous logic circuit1, it is possible to suppress glitches.

The glitch suppression cell is a logic cell that hinders glitches from occurring or hinders glitches from propagating. Specifically, the glitch suppression cell is a logic cell that performs the same logical operation as the original logic cell, and has a delay amount larger than that of the original logic cell. Glitch suppression cells of various logic cells are described below.

(Glitch Suppression Cell of Negative AND (NAND) Circuit)

FIG.14illustrates an example of a glitch suppression cell of a NAND circuit. This circuit includes transistors MP1to MP3and MN4to MN6. The transistors MP1to MP3are P-type MOS (Metal Oxide Semiconductor) transistors, and the transistors MN4to MN6are N-type MOS transistors.

The transistor MP1has agate coupled to an input terminal INA, a source coupled to the power supply node of the power supply voltage VDD, a drain coupled to a drain of the transistor MP2and a source of the transistor MP3. The transistor MP2has a gate coupled to an input terminal INB, a source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the drain of the transistor MP1and the source of the transistor MP3. The transistor MP3has a gate coupled to the ground node, the source coupled to the drains of the transistors MP1and MP2, and a drain coupled to the output terminal OUT. The transistor MN4has a gate coupled to the power supply node of the power supply voltage VDD, a drain coupled to the output terminal OUT, and a source coupled to a drain of the transistor MN5. The transistor MN5has agate coupled to the input terminal INB, a drain coupled to the source of the transistor MN4, and a source coupled to a drain of the transistor MN6. The transistor MN6has a gate coupled to the input terminal INA, the drain coupled to the source of the transistor MN5, and a source coupled to the ground node.

In the NAND circuit illustrated inFIG.14, the transistors MP3and MN4are provided. The transistors MP3and MN4function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this NAND circuit to suppress glitches, as compared with a case where the transistors MP3and MN4are not provided.

FIG.15illustrates another example of the glitch suppression cell of the NAND circuit. This circuit includes inverters IV11and IV12, transistors MP13, MP14, MN15, and MN16, and an inverter IV17. The transistors MP13and MP14are P-type MOS transistors, and the transistors MN15and MN16are N-type MOS transistors.

The inverter IV11has an input terminal coupled to the input terminal INA, and an output terminal led to gates of the transistors MP13and MN16. The inverter IV12has an input terminal coupled to the input terminal INB, and an output terminal led to gates of MP14and MN15. The transistor MP13has the gate led to the output terminal of the inverter IV11, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP14. The transistor MP14has the gate led to the output terminal of the inverter IV12, the source coupled to the drain of the transistor MP13, and a drain led to the node N1. The transistor MN15has the gate led to the output terminal of the inverter IV12, a drain led to the node N1, and a source coupled to the ground node. The transistor MN16has the gate led to the output terminal of the inverter IV11, a drain led to the node N1, and a source coupled to the ground node. The inverter IV17has an input terminal led to the node N1, and an output terminal coupled to the output terminal OUT.

In this NAND circuit, for example, it is possible to provide a transistor in one or more of a path (a path W11) coupling the output terminal of the inverter IV11and the gates of the transistors MP13and MN16, a path (a path W12) coupling the output terminal of the inverter IV12and the gates of the transistors MP14and MN15, a path (a path W13) coupling the drain of the transistor MP14and the node N1, a path (a path W14) coupling the node N1and the drains of the transistors MN15and MN16, and a path (a path W15) coupling the node N1and the input terminal of the inverter IV17.

FIG.16is an example in which transistors are provided in the paths W11and W12. An N-type MOS transistor and a P-type MOS transistor are provided in the path W11. The N-type MOS transistor has a gate coupled to the power supply node of the power supply voltage VDD, and the P-type MOS transistor has a gate coupled to the ground node. Likewise, an N-type MOS transistor and a P-type MOS transistor are provided in the path W12. The N-type MOS transistor has a gate coupled to the power supply node of the power supply voltage VDD, and the P-type MOS transistor has a gate coupled to the ground node.

FIG.17is an example in which transistors are provided in the paths W13and W14. A P-type MOS transistor is provided in the path W13. The P-type MOS transistor has a gate coupled to the ground node, a source coupled to the drain of the transistor MP14, and a drain coupled to the node N1. An N-type MOS transistor is provided in the path W14. The N-type MOS transistor has a gate coupled to the power supply node of the power supply voltage VDD, a drain coupled to the node N1, and a source coupled to the drains of the transistors MN15and MN16.

FIG.18is an example in which transistors are provided in the path W15. An N-type MOS transistor and a P-type MOS transistor are provided in the path W15. The N-type MOS transistor has a gate coupled to the power supply node of the power supply voltage VDD, and the P-type MOS transistor has a gate coupled to the ground node.

The transistors provided in the paths W11to W15function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this NAND circuit to suppress glitches, as compared with a case where the transistors are not provided in the paths W11to W15.

(Glitch Suppression Cell of Negative OR (NOR) Circuit)

FIG.19illustrates an example of a glitch suppression cell of an NOR circuit. This circuit includes transistors MP21to MP23and MN24to MN26. The transistors MP21to MP23are P-type MOS transistors, and the transistors MN24to MN26are N-type MOS transistors.

The transistor MP21has a gate coupled to the input terminal INA, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP22. The transistor MP22has a gate coupled to the input terminal INB, the source coupled to the drain of the transistor MP21, and a drain coupled to a source of the transistor MP23. The transistor MP23has a gate grounded, the source coupled to the drain of the transistor MP22, and a drain coupled to the output terminal OUT. The transistor MN24has a gate coupled to the power supply node of the power supply voltage VDD, a drain coupled to the output terminal OUT, and a source coupled to drains of the transistors MN25and MN26. The transistor MN25has a gate coupled to the input terminal INB, the drain coupled to the source of the transistor MN24and the drain of the transistor MN26, and a source coupled to the ground node. The transistor MN26has a gate coupled to the input terminal INA, the drain coupled to the source of the transistor MN24and the drain of the transistor MN25, and a source coupled to the ground node.

In the NOR circuit illustrated inFIG.19, the transistors MP23and MN24are provided. The transistors MP23and MN24function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this NOR circuit to suppress glitches, as compared with a case where the transistors MP23and MN24are not provided.

FIG.20illustrates another example of the glitch suppression cell of the NOR circuit. This circuit includes inverters IV31and IV32, transistors MP33, MP34, MN35, and MN36, and an inverter IV37. The transistors MP33and MP34are P-type MOS transistors, and the transistors MN35and MN36are N-type MOS transistors.

The inverter IV31has an input terminal coupled to the input terminal INA, and an output terminal led to gates of the transistors MP33and MN36. The inverter IV32has an input terminal coupled to the input terminal INB, and an output terminal led to gates of the transistors MP34and MN35. The transistor MP33has the gate led to the output terminal of the inverter IV31, a source coupled to the power supply node of the power supply voltage VDD, and a drain led to a node N3. The transistor MP34has the gate led to the output terminal of the inverter IV32, a source coupled to the power supply node of the power supply voltage VDD, and a drain led to the node N3. The transistor MN35has the gate led to the output terminal of the inverter IV32, a drain led to the node N3, and a source coupled to a drain of the transistor MN36. The transistor MN36has the gate led to the output terminal of the inverter IV31, the drain coupled to the source of the transistor MN35, and a source coupled to the ground node. The inverter IV37has an input terminal led to the node N3, and an output terminal coupled to the output terminal OUT.

In this NOR circuit, for example, it is possible to provide a transistor in one or more of a path (a path W31) coupling the output terminal of the inverter IV31and the gates of the transistors MP33and MN36, a path (a path W32) coupling the output terminal of the inverter IV32and the gates of the transistors MP34and MN35, a path (path W33) coupling the drains of the transistors MP33and MP34and the node N3, a path (a path W34) coupling the node N3and the drain of the transistor MN35, and a path (a path W35) coupling the node N3and the input terminal of the inverter IV37. An example in which transistors are provided in the paths W31and W32is similar to the example inFIG.16. An example in which transistors are provided in the paths W33and W34is similar to the example inFIG.17. An example in which transistors are provided in the path W35is similar to the example inFIG.18.

The transistors provided in the paths W31to W35function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this NOR circuit to suppress glitches, as compared with a case where the transistors are not provided in the paths W31to W35.

FIG.21illustrates an example of a glitch suppression cell of a latch circuit. This circuit includes an inverter IV41, transistors MN42and MP43, a NOR circuit NR44, transistors MP45, MP46, MN47, and MN48, an inverter IV49, transistors MN50and MP51, and an inverter IV52. The transistors MP43, MP45, MP46, and MP51are P-type MOS transistors, and the transistors MN42, MN47, MN48, and MN50are N-type MOS transistors.

The inverter IV41has an input terminal coupled to a terminal D, and an output terminal coupled to the transistors MN42and MP43. The transistor MN42is provided in a path coupling the output terminal of the inverter IV41and a node N4, and has a gate to be supplied with a clock signal CLKB. The transistor MP43is provided in the path coupling the output terminal of the inverter IV41and the node N4, and has a gate to be supplied with a clock signal CLK. The NOR circuit NR44has a first input terminal to be supplied with the reset signal RST, a second input terminal coupled to the node N4, and an output terminal coupled to a node N5. The transistor MP45has a gate coupled to the node N5, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP46. The transistor MP46has a gate to be supplied with the clock signal CLKB, the source coupled to the drain of the transistor MP45, and a drain coupled to the node N4. The transistor MN47has agate to be supplied with the clock signal CLK, a drain coupled to the node N4, and a source coupled to a drain of the transistor MN48. The transistor MN48has a gate coupled to the node N5, the drain coupled to the source of the transistor MN47, and a source coupled to the ground node. The inverter IV49has an input terminal coupled to the node N5, and an output terminal coupled to the transistors MN50and MP51. The transistor MN50is provided in a path coupling the output terminal of the inverter IV49and the input terminal of the inverter IV52, and has a gate coupled to the power supply node of the power supply voltage VDD. The transistor MP51is provided in the path coupling the output terminal of the inverter IV49and the input terminal of the inverter IV52, and has a gate coupled to the ground node. The inverter IV52has an input terminal coupled to the transistors MN50and MP51, and an output terminal coupled to a terminal Q. The clock signal CLKB is an inverted signal of the clock signal CLK.

FIG.22illustrates another example of the glitch suppression cell of the latch circuit. This circuit inFIG.22corresponds to the circuit inFIG.21in which coupling of the transistors MP45, MP46, MN47, and MN48is changed. The transistor MP46has the gate to be supplied with the clock signal CLKB, the source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the source of the transistor MP45. The transistor MP45has the gate coupled to the node N5, the source coupled to the drain of the transistor MP46, and the drain coupled to the node N4. The transistor MN48has the gate coupled to the node N5, the drain coupled to the node N4, and the source coupled to the drain of the transistor MN47. The transistor MN47has the gate to be supplied with the clock signal CLK, the drain coupled to the source of the transistor MN48, and the source coupled to the ground node.

In the latch circuit illustrated inFIGS.21and22, the transistors MN50and MP51are provided. The transistors MN50and MP51function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this latch circuit to suppress glitches, as compared with a case where the transistors MN50and MP51are not provided.

FIG.23illustrates another example of the glitch suppression cell of the latch circuit. This circuit inFIG.23corresponds to the circuit inFIG.21in which circuit portions of the inverter IV41and the transistors MN42and MP43are changed. This latch circuit includes transistors MP53, MP54, MN55, and MN56. The transistors MP53and MP54are P-type MOS transistors, and the transistors MN55and MN56are N-type MOS transistors.

The transistor MP53has a gate coupled to the terminal D, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP54. The transistor MP54has a gate to be supplied with the clock signal CLK, the source coupled to the drain of the transistor MP53, and a drain led to the node N4. The transistor MN55has a gate to be supplied with the clock signal CLKB, a drain led to the node N4, and a source coupled to a drain of the transistor MN56. The transistor MN56has a gate coupled to the terminal D, the drain coupled to the source of the transistor MN55, and a source coupled to the ground node.

FIG.24illustrates another example of the glitch suppression cell of the latch circuit. This circuit inFIG.24corresponds to the circuit inFIG.23in which coupling of the transistors MP45, MP46, MN47, and MN48is changed. The transistor MP46has the gate to be supplied with the clock signal CLKB, the source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the source of the transistor MP45. The transistor MP45has the gate coupled to the node N5, the source coupled to the drain of the transistor MP46, and the drain coupled to the node N4. The transistor MN48has the gate coupled to the node N5, the drain coupled to the node N4, and the source coupled to the drain of the transistor MN47. The transistor MN47has the gate to be supplied with the clock signal CLK, the drain coupled to the source of the transistor MN48, and the source coupled to the ground node.

In the latch circuit illustrated inFIGS.23and24, for example, it is possible to provide a transistor in one or more of a path (a path W41) coupling the drain of the transistor MP54and the node N4, a path (a path W42) coupling the node N4and the drain of the transistor MN55, and a path (a path W43) coupling the output terminal of the inverter IV49and the input terminal of the inverter IV52. An example in which transistors are provided in the paths W41and W42is similar to the example inFIG.17. An example in which transistors are provided in the path W43is similar to the example inFIG.18.

The transistors provided in the paths W41to W43function as resistor elements and also function as rectifier elements. This makes it possible to increase a delay amount and rectify a signal. As a result, it is possible for this latch circuit to suppress glitches, as compared with a case where the transistors are not provided in the path W41to W43.

FIG.25illustrates another example of the glitch suppression cell of the latch circuit. This circuit includes an inverter IV61, transistors MP62, MP63, MN64, MN65, MP66, and MN67to MN69, a NOR circuit NR70, transistors MP71, MP72, MN73, and MN74, and inverters IV75and IV76. The transistors MP62, MP63, MP66, MP71, and MP72are P-type MOS transistors, and the transistors MN64, MN65, MN67to MN69, MN73, and MN74are N-type MOS transistors. This latch circuit is configured to operate on the basis of the clock signal CLK without using the clock signal CLKB.

The inverter IV61has an input terminal coupled to the terminal D, and an output terminal coupled to gates of the transistors MP62and MN65. The transistor MP62has the gate coupled to the output terminal of the inverter IV61, a source coupled to the power supply node of the power supply voltage VDD, and a drain led to a node N6. The transistor MP63has a gate to be supplied with the clock signal CLK, a source coupled to the power supply node of the power supply voltage VDD, and a drain led to the node N6. The transistor MN64has a gate to be supplied with the clock signal CLK, a drain led to the node N6, and a source coupled to a drain of the transistor MN65. The transistor MN65has the gate coupled to the output terminal of the inverter IV61, the drain coupled to the source of the transistor MN64, and a source coupled to the ground node. The transistor MP66has a gate coupled to the node N6, a source coupled to the power supply node of the power supply voltage VDD, and a drain led to a node N7. The transistor MN67has a gate to be supplied with the clock signal CLK, a drain led to the node N7, and a source coupled to a drain of the transistor MN68. The transistor MN68has a gate coupled to the terminal D, the drain coupled to the source of the transistor MN67, and a source coupled to a drain of the transistor MN69. The transistor MN69has a gate coupled to the node N6, the drain coupled to the source of the transistor MN68, and a source coupled to the ground node. The NOR circuit NR70has a first input terminal to be supplied with the reset signal RST, a second input terminal coupled to the node N7, and an output terminal coupled to a node N8. The transistor MP71has a gate coupled to the node N8, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP72. The transistor MP72has a gate to be supplied with the clock signal CLK, the source coupled to the drain of the transistor MP71, and a drain coupled to the node N7. The transistor MN73has a gate coupled to the node N6, a drain coupled to the node N7, and a source coupled to a drain of the transistor MN74. The transistor MN74has a gate coupled to the node N8, the drain coupled to the source of the transistor MN73, and a source coupled to the ground node. The inverter IV75has an input terminal coupled to the node N8, and an output terminal led to an input terminal of the inverter IV76. The inverter IV76has the input terminal led to the output terminal of the inverter IV75, and an output terminal coupled to the terminal Q.

Here, the inverter IV61corresponds to a specific example of a “first inverter” in an embodiment of the present disclosure. The inverter IV75corresponds to a specific example of a “second inverter” in an embodiment of the present disclosure. The inverter IV76corresponds to a specific example of a “third inverter” in an embodiment of the present disclosure. The NOR circuit NR70corresponds to a specific example of a “NOR circuit” in an embodiment of the present disclosure. The transistor MP62corresponds to a specific example of a “first transistor” in an embodiment of the present disclosure. The transistor MP63corresponds to a specific example of a “second transistor” in an embodiment of the present disclosure. The transistor MN64corresponds to a specific example of a “third transistor” in an embodiment of the present disclosure. The transistor MN65corresponds to a specific example of a “fourth transistor” in an embodiment of the present disclosure. The transistor MP66corresponds to a specific example of a “fifth transistor” in an embodiment of the present disclosure. The transistor MN67corresponds to a specific example of a “sixth transistor” in an embodiment of the present disclosure. The transistor MN68corresponds to a specific example of a “seventh transistor” in an embodiment of the present disclosure. The transistor MN69corresponds to a specific example of an “eighth transistor” in an embodiment of the present disclosure. The transistor MP71corresponds to a specific example of a “ninth transistor” in an embodiment of the present disclosure. The transistor MP72corresponds to a specific example of a “tenth transistor” in an embodiment of the present disclosure. The transistor MN73corresponds to a specific example of an “eleventh transistor” in an embodiment of the present disclosure. The transistor MN74corresponds to a specific example of a “twelfth transistor” in an embodiment of the present disclosure.

FIG.26illustrates another example of the glitch suppression cell of the latch circuit. This circuit inFIG.26corresponds to the circuit inFIG.25in which coupling of the transistor MP71, MP72, MN73, and MN74is changed. The transistor MP72has the gate to be supplied with the clock signal CLK, the source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the source of the transistor MP71. The transistor MP71has the gate coupled to the node N8, the source coupled to the drain of the transistor MP72, and the drain coupled to the node N7. The transistor MN74has the gate coupled to the node N8, the drain coupled to the node N7, and the source coupled to the drain of the transistor MN73. The transistor MN73has the gate coupled to the node N6, the drain coupled to the source of the transistor MN74, and the source coupled to the ground node.

In the latch circuit illustrated inFIGS.25and26, the transistors MN67to MN69are provided. For example, in a case where the clock signal CLK is at the low level, the transistor MP63is turned on, which changes a voltage at the node N6to the high level and turns on the transistor MN69. This makes it possible to prevent the drain of the transistor MN69from being turned to a floating state. The transistor MN68is turned off in a case where a signal at the terminal D is at the low level. This makes it possible to reduce a possibility that a leakage current flows from the power supply node to the ground node through the transistors MP66and MN67to MN69upon transition of the clock signal. In addition, in this latch circuit, only the clock signal CLK is used, and the clock signal CLKB is not used; therefore, a glitch caused by a transition timing difference between the clock signal CLK and the clock signal CLKB does not occur. In addition, a signal is rectified in a MOS transistor to which the clock signal CLK is inputted. As a result, in this latch circuit, it is possible to hinder glitches from occurring.

In the latch circuit illustrated inFIGS.25and26, for example, it is possible to provide a transistor in one or more of a path (a path W61) coupling the drains of the transistors MP62and MP63and the node N6, a path (a path W62) coupling the node N6and the drain of the transistor MN64, a path (a path W63) coupling the drain of the transistor MP66and the node N7, a path (a path W64) coupling the node N7and the drain of the transistor MN67, and a path (a path W65) coupling the output terminal of the inverter IV75and the input terminal of the inverter IV76. An example in which transistors are provided in the paths W61and W62is similar to the example inFIG.17. An example in which transistors are provided in the paths W63and W64is similar to the example inFIG.17. An example in which transistors are provided in the path W65is similar to the example inFIG.18.

(Glitch Suppression Cell of C-Element)

It is possible to configure a C-element with use of, for example, the AND circuit101, the OR circuit102, the NAND circuit103, and the latch circuit104, as illustrated inFIG.4. It is possible to configure this AND circuit101with use of, for example, a NAND circuit and an inverter; therefore, it is possible to configure this NAND circuit with sue of the glitch suppression cell illustrated inFIGS.14to18. Likewise, it is possible to configure the OR circuit102with use of, for example, a NOR circuit and an inverter; therefore, it is possible to configure this NOR circuit with use of the glitch suppression cell illustrated inFIGS.19and20. In addition, it is possible to configure the NAND circuit103with use of the glitch suppression cell illustrated inFIGS.14to18. In addition, it is possible to configure the latch circuit104with use of the glitch suppression cell illustrated inFIGS.21to26.

In addition, it is possible to configure the C-element with use of, for example, the AND circuits111to113, the NOR circuit114, and the AND circuit115, as illustrated inFIG.5. Also in this case, it is possible to configure each logic cell included in the C-element with use of the glitch suppression cell illustrated inFIGS.14to26.

FIG.27illustrates another example of the glitch suppression cell of the C-element. This circuit includes transistors MP81, MP82, MN83, MN84, MP85to MP87, and MN88to MN90, a NOR circuit NR91, and inverters IV92and IV93. The transistors MP81, MP82, and MP85to MP87are P-type MOS transistors, and the transistor MN88to MN90are N-type MOS transistors.

The transistor MP81has agate to be supplied with a signal SA, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a source of the transistor MP82. The transistor MP82has a gate to be supplied with a signal SB, a source coupled to the drain of the transistor MP81, and a drain led to a node N9. The transistor MN83has a gate to be supplied with the signal SB, a drain led to the node N9, and a source coupled to a drain of the transistor MN84. The transistor MN84has a gate to be supplied with the signal SA, the drain coupled to the source of the transistor MN83, and a source coupled to the ground node. The transistor MP85has a gate to be supplied with the signal SA, a source coupled to the power supply node of the power supply voltage VDD, and a drain coupled to a drain of the transistor MP86and a source of the transistor MP87. The transistor MP87has agate coupled to anode N10, the source coupled to the drains of the transistors MP85and MP86, and a drain led to the node N9. The transistor MN88has a gate coupled to the node N10, a drain led to the node N9, and a source coupled to drains of the transistors MN89and MN90. The transistor MN89has a gate to be supplied with the signal SA, the drain coupled to the source of the transistor MN88and the drain of the transistor MN90, and a source coupled to the ground node. The transistor MN90has a gate to be supplied with the signal SB, the drain coupled to the source of the transistor MN88and the drain of the transistor MN89, and a source coupled to the ground node. The NOR circuit NR91has a first input terminal coupled to the node N9, a second input terminal to be supplied with the reset signal RST, and an output terminal coupled to the node N10. The inverter IV92has an input terminal coupled to the node N10, and an output terminal led to an input terminal of the inverter IV93. The inverter IV93has the input terminal led to the output terminal of the inverter IV92, and an output terminal coupled to an output terminal of the C-element.

Here, the transistor MP81corresponds to a specific example of a “nineteenth transistor” in an embodiment of the present disclosure. The transistor MP82corresponds to a specific example of a “twentieth transistor” in an embodiment of the present disclosure. The transistor MN83corresponds to a specific example of a “twenty-first transistor” in an embodiment of the present disclosure. The transistor MN84corresponds to a specific example of a “twenty-second transistor” in an embodiment of the present disclosure. The transistor MP86corresponds to a specific example of a “twenty-third transistor” in an embodiment of the present disclosure. The transistor MP87corresponds to a specific example of a “twenty-fourth transistor” in an embodiment of the present disclosure. The transistor MN88corresponds to a specific example of a “twenty-fifth transistor” in an embodiment of the present disclosure. The transistor MN90corresponds to a specific example of a “twenty-sixth transistor” in an embodiment of the present disclosure. The transistor MP85corresponds to a specific example of a “twenty-seventh transistor” in an embodiment of the present disclosure. The transistor MN89corresponds to a specific example of a “twenty-eighth transistor” in an embodiment of the present disclosure. The NOR circuit NR71corresponds to a specific example of a “NOR circuit” in an embodiment of the present disclosure. The inverter IV92corresponds to a specific example of a “fourth inverter” in an embodiment of the present disclosure. The inverter IV93corresponds to a specific example of a “fifth inverter” in an embodiment of the present disclosure.

FIG.28illustrates another example of the glitch suppression cell of the C-element. This circuit inFIG.28corresponds to the circuit inFIG.27in which coupling of the transistors MP85to MP87and MN88to MN90is changed. The transistor MP85is provided in a path coupling the drain of the transistor MP81and the source of the transistor MP82to the drain of the transistor MP86and the source of the transistor MP87, and has the gate to be supplied with the signal SA. The transistor MP86has the gate to be supplied with the signal SB, the source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the source of the transistor MP87and the transistor MP85. The transistor MP87has the gate coupled to the node N10, the source coupled to the drain of the transistor MP86and the transistor MP85, and the drain led to the node N9. The transistor MN88has the gate coupled to the node N10, the drain led to the node N9, and the source coupled to the drain of the transistor MN90and the transistor MN89. The transistor MN89is provided in a path coupling the source of the transistor MN83and the drain of the transistor MN84to the source of the transistor MN88and the drain of the transistor MN90, and has the gate to be supplied with the signal SA. The transistor MN90has the gate to be supplied with the signal SB, the drain coupled to the source of the transistor MN88and the transistor MN89, and the source coupled to the ground node. Here, the transistor MP85corresponds to a specific example of a “twenty-ninth transistor” in an embodiment of the present disclosure. The transistor MN89corresponds to a specific example of a “thirtieth transistor” in an embodiment of the present disclosure.

FIG.29illustrates another example of the glitch suppression cell of the C-element. This circuit inFIG.29corresponds to the circuit inFIGS.27and28in which coupling of the transistors MP85to MP87and MN88to MN90is changed. The transistor MP85is provided in a path coupling the drain of the transistor MP81and the source of the transistor MP82to the drain of the transistor MP86and the source of the transistor MP87, and has the gate coupled to the node N10. The transistor MP86has the gate to be supplied with the signal SB, the source coupled to the power supply node of the power supply voltage VDD, and the drain coupled to the source of the transistor MP87and the transistor MP85. The transistor MP87has the gate to be supplied with the signal SA, the source coupled to the drain of the transistor MP86and the transistor MP85, and the drain led to the node N9. The transistor MN88has the gate to be supplied with the signal SA, the drain led to the node N9, and the source coupled to the drain of the transistor MN90and the transistor MN89. The transistor MN89is provided in a path coupling the source of the transistor MN83and the drain of the transistor MN84to the source of the transistor MN88and the drain of the transistor MN90, and has the gate coupled to the node N10. The transistor MN90has the gate to be supplied with the signal SB, the drain coupled to the source of the transistor MN88and the transistor MN89, and the source coupled to the ground node. The transistor MP85corresponds to a specific example of a “twenty-ninth transistor” in an embodiment of the present disclosure. The transistor MN89corresponds to a specific example of a “thirtieth transistor” in an embodiment of the present disclosure.

In the C-element illustrated inFIGS.27to29, for example, it is possible to provide a transistor in one or more of a path (a path W81) coupling the drain of the transistor MP82and the node N9, a path (a path W82) coupling the node N9and the drain of the transistor MN83, a path (a path W83) coupling the drain of the transistor MP87and the node N9, a path (a path W84) coupling the node N9and the drain of the transistor MN88, and a path (a path W85) coupling the output terminal of the inverter IV92and the input terminal of the inverter IV93. An example in which transistors are provided in the paths W81and W82is similar to the example inFIG.17. An example in which transistors are provided in the paths W83and W84is similar to the example inFIG.17. An example in which transistors are provided in the path W85is similar to the example inFIG.18.

As described above, in the circuit conversion method, using such a glitch suppression cell makes it possible to suppress glitches.

As described above, in the circuit conversion method, for example, as illustrated in step S101, the computer sets the processing target path P in the asynchronous logic circuit1. Thereafter, for example, as illustrated in step S152of the conversion processing A1in step S103, the computer performs first processing for determining whether or not a glitch occurs in each of a plurality of logic cells in the processing target path P. Thereafter, for example, as illustrated in steps S153and S154of the conversion processing A1in step S103, the computer performs second processing including conversion processing for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells. The one or more glitch suppression logic cells are configured to suppress glitches, and perform the same logical operation as the one or more logic cells. Thereafter, as illustrated in steps S104to S107, after this second processing, the computer performs third processing for determining whether or not a glitch occurs in a C-element that is a subsequent-stage circuit in the processing target path P. Accordingly, in this circuit conversion method, it is possible to convert a logic cell in which a glitch is determined to occur into a glitch suppression logic cell, which makes it possible to suppress glitches.

Thereafter, in this circuit conversion method, for example, as illustrated in step S108, in a case where a glitch is determined as occurring in the third processing, the computer performs fourth processing for changing the plurality of logic cells in the processing target path P to the initial state. Thereafter, for example, as illustrated in step S110, after this fourth processing, the computer performs fifth processing for sequentially selecting one of the plurality of logic cells in the processing target path P and converting the selected logic cell into a QDI logic cell. Thereafter, for example, as illustrated in steps S111to S114, the computer performs sixth processing for determining whether or not a glitch occur in a C-element that is a subsequent-stage circuit every time one of the plurality of logic cells is selected in the fifth processing. Accordingly, in this circuit conversion method, it is possible to convert the logic cell into a QDI logic cell that makes it possible to suppress glitches. This makes it possible to suppress glitches. In addition, one of the plurality of logic cells is sequentially selected and the selected logic cell is converted into a QDI logic cell in such a manner. Accordingly, in this circuit conversion method, for example, the logic cells in the processing target path P are converted into QDI logic cells in order from the first stage. Thereafter, for example, in a case where a glitch is determined as not occurring in midstream, it is possible to end this processing. This makes it possible to suppress glitches while suppressing the number of QDI logic cells. The QDI logic cell is a 2-wire circuit, and includes various circuits for suppressing glitches; therefore, the QDI logic cell has a large circuit scale. Accordingly, reducing the number of QDI logic cells makes it possible to reduce a circuit area. As a result, in this circuit conversion method, it is possible to effectively suppress glitches while reducing the circuit area.

Effects

As described above, in the present embodiment, the computer sets the processing target path in the asynchronous logic circuit. Thereafter, the computer performs the first processing for determining whether or not a glitch occurs in each of the plurality of logic cells in the processing target path. Thereafter, the computer performs the second processing including the conversion processing for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells. The one or more glitch suppression logic cells are configured to suppress glitches, and perform the same logical operation as the one or more logic cells. Thereafter, after this second processing, the computer performs the third processing for determining whether or not a glitch occurs in a C-element that is a subsequent-stage circuit in the processing target path. Thus, it is possible to suppress glitches.

Modification Example 1-1

In the embodiment described above, as illustrated inFIGS.12A to12C, and13, in step S103, all logic cells satisfying the glitch determination condition C are converted into one or a plurality of glitch suppression cells, and thereafter, in steps S104and S106, it is confirmed whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. Likewise, in step S117, all logic cells satisfying the glitch determination condition C are converted into one or a plurality of glitch suppression cells, and thereafter, in steps S118and S120, it is confirmed whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. However, this is not limitative. Instead of this, all logic cells satisfying the glitch determination condition C may be selected one by one, and the selected one logic cell may be converted into one or a plurality of glitch suppression cells, and for every conversion, it may be confirmed whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. A circuit conversion method according to the present modification example is described in detail below.

FIGS.30A and30Billustrate an example of the circuit conversion method according to the present modification example.

First, the computer identifies the processing target path P where circuit conversion is to be performed, and obtains the stage number M of logic cells in the processing target path P (step S101).

Next, the computer sets the variable i to “1” (i=1) (step S102), and performs conversion processing A2(step S133). In this conversion processing A2, the computer sets all logic cells in i-th and subsequent stages in the processing target path P as processing targets. In this example, the variable i is set to “1” in step S102; therefore, the computer sets all logic cells in “1”st and subsequent stages in the processing target path P as processing targets of the conversion processing A2.

FIGS.31A and31Billustrate a subroutine of the conversion processing A2. In this conversion processing A2, the computer selects, one by one, all logic cells in which glitches possibly occurs out of all the logic cells in the i-th stage (the first stage in this example) and subsequent stages in the processing target path P, converts the selected one logic cell into one or a plurality of glitch suppression cells, and confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. This operation is described in detail below.

The computer confirms whether or not a plurality of signals is to be inputted to the logic cell in the i-th stage in the processing target path P (step S151). In a case where one signal is to be inputted to the logic cell in the i-th stage (“N” in step S151), the processing proceeds to step S156.

In step S151, in a case where a plurality of signals is to be inputted to the logic cell in the i-th stage (step S151), the computer confirms whether or not the logic cell in the i-th stage satisfies the glitch determination condition C (step S152). In a case where this logic cell does not satisfy the glitch determination condition C (“N” in step S153), the computer determines that no glitch occurs in this logic cell, and the processing proceeds to step S156.

In a case where this logic cell satisfies the glitch determination condition C in step S152(“Y” in step S153), the computer determines that a glitch possibly occurs in this logic cell, and converts this logic cell into one or a plurality of glitch suppression cells that performs the same operation (step S154). Thereafter, the computer updates the timing information in the design data (step S155).

Next, the computer confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P (step S171). In the example inFIG.11, the computer confirms whether or not a glitch occurs in an output of a C-element in the control circuit21H in a subsequent stage in the processing target path P. In a case where no glitch occurs (“N” in step S172), this processing ends.

In a case where a glitch occurs in step S171(“Y” in step S172), the computer converts this C-element into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this C-element (step S173). In a case where no glitch occurs (“N” in step S174), this processing ends.

In a case where a glitch occurs in step S173(“Y” in step S174), the computer restores the C-element converted in step S173, and all logic cells converted in step S154in the processing target path P to the initial state (step S175). Thus, all the logic cells in the processing target path P are restored to the initial state.

Next, the computer confirms whether or not the variable i is equal to the stage number M (i=M) (step S156). In a case where the variable i is smaller than the stage number M (“N” in step S156), the computer increments the variable i (step S157), and the processing returns to step S151. Thus, one logic cell out of all the logic cells satisfying the glitch determination condition C is converted into one or a plurality of glitch suppression cells, and it is confirmed whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. Thereafter, this operation is repeated until no glitch occurs.

In a case where the variable i is equal to the stage number M in step S156(“Y” in step S156), the computer ends the subroutine of the conversion processing A2.

In step S133, in a case where a glitch continuously occurs, the computer next sets the variable j to “1” (j=1) (step S109).

Next, the computer converts an input signal to the logic cell in the j-th stage in the processing target path P into a 2-wire signal, converts the logic cell in the j-th stage into a QDI logic cell, and converts an output signal of this QDI logic cell into a 1-wire signal (step S10).

Next, the computer confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P (step S111). In a case where no glitch occurs (“N” in step S112), this processing ends.

In a case where a glitch occurs in step S111(“Y” in step S112), the computer converts this C-element into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this C-element (step S113). In a case where no glitch occurs (“N” in step S114), this processing ends.

In a case where a glitch occurs in step S113(“Y” in step S114), the computer restores the C-element converted in step S113to the initial state (step S115).

Next, the computer sets the variable i to “j+1” (i=j+1) (step S116), and performs the conversion processing A2(step S137). In the conversion processing A2, as illustrated inFIGS.31A and31B, the computer converts one of all logic cells in which a glitch possibly occurs out of all logic cells in the i-th stage (the j+1-th stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells, and confirms whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. Thereafter, this operation is repeated until no glitch occurs.

In step S137, in a case where a glitch continuously occurs, the computer next restores the C-element converted in step S120to the initial state, and restores all logic cells other than the QDI logic cell in the processing target path P to the initial state (step S122).

Next, the computer confirms whether or not the variable j is equal to the stage number M (j=M) (step S123). In a case where the variable j is smaller than the stage number M (“N” in step S123), the computer increments the variable j (step S124), and the processing returns to step S110.

In a case where the variable j is equal to the stage number M in step S123(“Y” in step S123), the computer ends this processing.

Modification Example 1-2

In the embodiment described above, as illustrated inFIG.11, the port of the signal to be inputted from the combinational circuit12of the data-path circuit10to the handshake circuit20is identified, and a signal path from this port to the input terminal of the control circuit21in the handshake circuit20is identified as the processing target path P, but this is not limitative. Instead of this, for example, a longer signal path including this signal path may be identified as the processing target path P. Specifically, for example, inFIG.11, a port of a signal to be inputted from the register11E to the combinational circuit12is identified, and a signal path from this port to the input terminal of the control circuit21H through a part of the combinational circuit12, the inverters37and38, and the AND circuits43and47may be identified as the processing target path P.

Modification Example 1-3

In the embodiment described above, the circuit conversion method illustrated inFIGS.12A to12C and13is used, but the circuit conversion method is not limited thereto. For example, even in a case where it is not possible to completely suppress glitches, conversion processing may end without affecting the operation.

Modification Example 1-4

In the embodiment described above, the glitch suppression cells illustrated inFIGS.24to29are examples, and the glitch suppression cell is not limited thereto. It is possible to use various glitch suppression cells that are configured to suppress glitches.

Other Modification Examples

In addition, two or more of these modification examples may be combined.

2. Second Embodiment

Next, description is given of an asynchronous logic circuit2to which a circuit conversion method according to a second embodiment is applied. In the present embodiment, the circuit system itself of the asynchronous logic circuit is different from that of the asynchronous logic circuit according to the first embodiment. That is, in the first embodiment, the present technology is applied to what is called a bundled-data asynchronous logic circuit. Meanwhile, in the second embodiment, the present technology is applied to a 2-wire SDI (Scalable Delay Insensitive) circuit.

FIG.32illustrates a configuration example of the asynchronous logic circuit2to which the circuit conversion method according to the present embodiment is applied. The asynchronous logic circuit2is a 2-wire SDI circuit. The asynchronous logic circuit2illustrated inFIG.32is an example of a most basic configuration. In actuality, as described later, the asynchronous logic circuit2may be more complicated than this circuit configuration. The asynchronous logic circuit2includes a plurality of SDI combinational circuits51, a plurality of SDI registers60, and a plurality of completion detection circuits70. In this example, the SDI registers60, the SDI combinational circuit51, and the completion detection circuits70are alternately disposed.

The SDI combinational circuit51is a 2-wire combinational circuit using a 2-wire SDI logic cell. The SDI combinational circuit51is configured to perform a logical operation on a piece of 2-wire data DT supplied from the SDI register60in a preceding stage and supply the obtained piece of 2-wire data DT to the SDI register60in a subsequent stage. A 2-wire signal includes two signals (signals ST and SF). The signals ST and SF possibly takes “0, 0”, “1, 0”, “0, 1”, and “0, 0”. The phase “0, 0” is also referred to as an idle phase, and is disposed before and after “1, 0” or “0, 1”. A 2-wire SDI logic cell is described below with reference to some examples.

FIG.33illustrates a configuration example of an SDI logic cell of a logical AND (AND) circuit. This circuit includes a 1-wire AND circuit151and a 1-wire OR circuit152. Terminals A (terminals AT and AF) are supplied with a 2-wire signal, terminals B (terminals BT and BF) are supplied with a 2-wire signal, and terminals Z (ZT and ZF) outputs a 2-wire signal. The AND circuit151has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BT, and an output terminal coupled to the terminal ZT. The OR circuit152has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BF, and an output terminal coupled to the terminal ZF. For example, in a case where signals at the terminals AT and AF are “1, 0”, and signals at the terminals BT and BF are “1, 0”, signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.34illustrates a configuration example of an SDI logic cell of a negative AND (NAND) circuit. This circuit includes a 1-wire AND circuit153and a 1-wire OR circuit154. The AND circuit153has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BT, and an output terminal coupled to the terminal ZF. The OR circuit154has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BF, and an output terminal coupled to the terminal ZT. For example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.35illustrates a configuration example of an SDI logic cell of a logical OR (OR) circuit. This circuit includes a 1-wire OR circuit155and a 1-wire AND circuit156. The OR circuit155has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BT, and an output terminal coupled to the terminal ZT. The AND circuit156has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BF, and an output terminal coupled to the terminal ZF. For example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.36illustrates a configuration example of an SDI logic cell of a negative OR (NOR) circuit. This circuit includes a 1-wire OR circuit157and a 1-wire AND circuit158. The OR circuit157has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BT, and an output terminal coupled to the terminal ZF. The AND circuit158has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BF, and an output terminal coupled to the terminal ZT. For example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.37illustrates a configuration example of an SDI logic cell of a negative (NOT) circuit. In this circuit, the terminal AT is coupled to the terminal ZF, and the terminal AF is coupled to the terminal ZT. For example, in a case where the signals at the terminals AT and AF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.38illustrates a configuration example of an SDI logic cell of a buffer (BUFF) circuit. In this circuit, the terminal AT is coupled to the terminal ZT, and the terminal AF is coupled to the terminal ZF. For example, in a case where the signals at the terminals AT and AF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.39illustrates a configuration example of an SDI logic cell of an exclusive-OR (XOR) circuit. This circuit includes 1-wire AND circuits161,163, and166, and 1-wire OR circuits162,164, and165. The AND circuit161has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BT, and an output terminal coupled to the OR circuit165. The OR circuit162has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BF, and an output terminal coupled to the AND circuit166. The AND circuit163has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BF, and an output terminal coupled to the OR circuit165. The OR circuit164has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BT, and an output terminal coupled to the AND circuit166. The OR circuit165has a first input terminal coupled to the output terminal of the AND circuit161, a second input terminal coupled to the output terminal of the AND circuit163, and an output terminal coupled to the terminal ZT. The AND circuit166has a first input terminal coupled to the output terminal of the OR circuit162, a second input terminal coupled to the output terminal of the OR circuit164, and an output terminal coupled to the terminal ZF. For example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

FIG.40illustrates a configuration example of an exclusive-NOR (XNOR) circuit. This circuit include 1-wire AND circuits171,173, and17, and 1-wire OR circuits172,174, and175. The AND circuit171has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BT, and an output terminal coupled to the OR circuit175. The OR circuit172has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BF, and an output terminal coupled to the AND circuit176. The AND circuit173has a first input terminal coupled to the terminal AT, a second input terminal coupled to the terminal BF, and an output terminal coupled to the OR circuit175. The OR circuit174has a first input terminal coupled to the terminal AF, a second input terminal coupled to the terminal BT, and an output terminal coupled to the AND circuit176. The OR circuit175has a first input terminal coupled to the output terminal of the AND circuit171, a second input terminal coupled to the output terminal of the AND circuit173, and an output terminal coupled to the terminal ZF. The AND circuit176has a first input terminal coupled to the output terminal of the OR circuit172, a second input terminal coupled to the output terminal of the OR circuit174, and an output terminal coupled to the terminal ZT. For example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “1, 0”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “1, 0”, the signals at the terminals ZT and ZF become “0, 1”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 1”, and the signals at the terminals BT and BF are “0, 1”, the signals at the terminals ZT and ZF become “1, 0”. In addition, for example, in a case where the signals at the terminals AT and AF are “0, 0”, and the signals at the terminals BT and BF are “0, 0”, the signals at the terminals ZT and ZF become “0, 0”.

It is possible to convert, for example, a 1-wire logic circuit illustrated inFIG.41into, for example, a 2-wire logic circuit illustrated inFIG.42by using a 2-wire SDI circuit. The logic circuit illustrated inFIG.41includes an OR circuit and a NAND circuit. This OR circuit is converted into a 2-wire OR circuit illustrated inFIG.35, and the NAND circuit is converted into a 2-wire NAND circuit illustrated inFIG.34, thereby making it possible to obtain the 2-wire logic circuit illustrated inFIG.42.

The SDI register60includes, for example, a plurality of SDI latch circuits61(to be described later), and is configured to latch a piece of data DT supplied from the combinational circuit12in a preceding stage. In addition, the SDI register60also has a function of generating a plurality of flag signals F and supplying the plurality of flag signals F to the completion detection circuit70. The plurality of flag signals F each indicates whether or not a signal latched by each of the plurality of SDI latch circuits61is in the idle phase.

The completion detection circuit70is configured to generate a detection signal DET by detecting whether or not all signals latched by the plurality of SDI latch circuits61are in the idle phase, on the basis of the plurality of flag signals F supplied from the SDI register60.

FIG.43illustrates a configuration example of the SDI register60and the completion detection circuit70.

The SDI register60includes the plurality of SDI latch circuits61. Each of the plurality of SDI latch circuits61includes C-elements62and63and a NOR circuit64.

The C-element62has two input terminals, a reset terminal, and an output terminal. The signal ST of a 2-wire signal included in the piece of data DT supplied from the SDI combinational circuit in a preceding stage, and the detection signal DET supplied from the completion detection circuit70are inputted to the two input terminals. The reset signal RST is inputted to the reset terminal. The C-element62changes the signal ST at the output terminal to the high level in a case where both the signal ST and the detection signal DET are at the high level, changes the signal ST at the output terminal to the low level in a case where both the signal ST and the detection signal DET are at the low level, and maintains the signal ST at the output terminal in other cases. In addition, the C-element62changes the signal ST at the output terminal to the low level on the basis of the reset signal RST.

The C-element63has two input terminals, a reset terminal, and an output terminal. The signal SF of the 2-wire signal included in the piece of data DT supplied from the SDI combinational circuit in the preceding stage, and the detection signal DET supplied from the completion detection circuit70are inputted to the two input terminals. The reset signal RST is inputted to the reset terminal. The C-element63changes the signal SF at the output terminal to the high level in a case where both the signal SF and the detection signal DET are at the high level, changes the signal SF at the output terminal to the low level in a case where both the signal SF and the detection signal DET are at the low level, and maintains the signal SF at the output terminal in other cases. In addition, the C-element63changes the signal SF at the output terminal to the low level on the basis of the reset signal RST.

The NOR circuit64is configured to find NOR of the signal ST generated by the C-element62and the signal SF generated by the C-element63and output a thus-obtained result as the flag signal F. The NOR circuit64changes the flag signal F to the high level in a case where the signals ST and SF are “0, 0”.

The completion detection circuit70includes an AND circuit71, an OR circuit72, and a C-element73. The AND circuit71is configured to find AND of the plurality of flag signals F supplied from the plurality of SDI latch circuits61in the SDI register60. The OR circuit72is configured to find OR of the plurality of flag signals F supplied from the plurality of SDI latch circuits61in the SDI register60. The C-element73has two input terminals, a reset terminal, and an output terminal. An output signal of the AND circuit71and an output signal of the OR circuit72are inputted to the two input terminals. The reset signal RST is inputted to the reset terminal. The C-element73changes the detection signal DET at the output terminal to the high level in a case where both the output signal of the AND circuit71and the output signal of the OR circuit72are at the high level, changes the detection signal DET at the output terminal to the low level in a case where both the output signal of the AND circuit71and the output signal of the OR circuit72are at the low level, and maintains the detection signal DET at the output terminal in other cases. In addition, the C-element63changes the detection signal DET at the output terminal to the low level on the basis of the reset signal RST. With this configuration, the completion detection circuit70changes the detection signal DET to the high level in a case where all the plurality of flag signals F is changed to the high level, and changes the detection signal DET to the low level in a case where all the plurality of flag signals F is changed to the low level. In other words, the completion detection circuit70changes the detection signal DET to the high level in a case where all signals latched by the plurality of SDI latch circuits61are in the idle phase.

FIG.44illustrates a configuration example of the asynchronous logic circuit2. It is to be noted that this diagram illustrates each of the C-elements62and63using a circuit illustrated inFIG.4. In this example, the SDI register60(an SDI register60B) is provided in a stage subsequent to the SDI combinational circuit51, and another SDI register60(an SDI register60C) is provided in a stage subsequent to the SDI register60B. That is, in this example, the SDI combinational circuit51is not provided between the SDI register60B and the SDI register60C, and the SDI register60B and the SDI register60C are directly coupled to each other. In addition, the SDI register60C supplies a plurality of flag signals F to the completion detection circuit70(a completion detection circuit70C), and the completion detection circuit70C generates the detection signal DET on the basis of the plurality of flag signals F, and supplies the generated detection signal DET to the SDI register60B. That is, the completion detection circuit70C does not supply the detection signal DET to the SDI register60C, but supplies the detection signal DET to the SDI register60B. Likewise, the SDI register60B supplies a plurality of flag signals F to the completion detection circuit70(a completion detection circuit70B), and the completion detection circuit70B generates the detection signal DET on the basis of the plurality of flag signals F, and supplies the generated detection signal DET to the SDI register60(a SDI register60A) in a stage preceding to the SDI combinational circuit51. The SDI register60A supplies a plurality of flag signals F to the completion detection circuit70(a completion detection circuit70A), and the completion detection circuit70A generates the detection signal DET on the basis of the plurality of flag signals F.

Incidentally, in recent years, a semiconductor process size has been further reduced, and a power supply voltage has been further lowered. In such a situation, glitches easily occur. In the asynchronous logic circuit2, using a 2-wire SDI circuit as illustrated inFIGS.33to40makes it possible to hinder glitches from occurring. However, when the semiconductor process size is further reduced and the power supply voltage is further lowered as described above, the variation tendency of a delay amount in a logic cell may become more complicated. For example, variations in delay amounts of a plurality of logic cells provided in one signal path in one semiconductor chip may vary differently from each other. Accordingly, even in a case where the SDI circuit as illustrated inFIGS.33to40is used, glitches may occur.

FIG.45illustrates an example of occurrence of glitches. This example focuses on a path (the processing target path P) including the AND circuit101, the OR circuit102, and the NAND circuit103of one SDI latch circuit61in the SDI register60B. For example, in a case where, the delay amount of the SDI combinational circuit51is increased and the delay amounts of the SDI register60C and the completion detection circuit70C in a subsequent stage are decreased due to variations in delay amount, there is a possibility that glitches occur in an output signal (a reference sign W7) of the AND circuit101, an output signal (a reference sign W8) of the OR circuit102, and an output signal (a reference sign W9) of the NAND circuit103. In this case, there is a possibility that the latch circuit104malfunctions, and as a result, there is a possibility that the SDI latch circuit61in the SDI register60C that is a subsequent-stage circuit also malfunctions.

In a case where the glitches occur as described above, a circuit malfunction easily occurs. In addition, in a case where glitches occur, power consumption is increased by switching. Accordingly, it is desirable to suppress glitches.

A circuit conversion method that implements the asynchronous logic circuit2in which glitches are suppressed is described in detail below. In this circuit conversion method, a computer executes a program to thereby convert a circuit on the basis of design data of the asynchronous logic circuit2so as to hinder glitches from occurring.

FIGS.46A to46Cillustrate an example of the circuit conversion method by the computer.

First, the computer identifies the processing target path P where circuit conversion is to be performed, and obtains the stage number M of logic cells in the processing target path P (step S201). In the design data of the asynchronous logic circuit2, the SDI combinational circuit51, the SDI register60, and the completion detection circuit70are defined as modules different from each other. The computer is able to identify a port of a signal to be inputted from the completion detection circuit70to the SDI register60, on the basis of such design data, and is able to identify a signal path from this port to the input terminal of the latch circuit104in the SDI register60. The computer identifies such a signal path as the processing target path P. In the example inFIG.45, the computer identifies a path including the AND circuit101, the OR circuit102, and the NAND circuit103as the processing target path P. Thereafter, the computer obtains the stage number (stage number M) of logic cells in this processing target path P.

Next, the computer sets the variable i to “1” (i=1) (step S202), and performs conversion processing A3(step S203). In this conversion processing A3, the computer sets all logic cells in i-th and subsequent stages in the processing target path P as processing targets. In this example, the variable i is set to “1” in step S102; therefore, the computer sets all logic cells in “1”st and subsequent stages in the processing target path P as processing targets of the conversion processing A3.

FIG.47illustrate an example of a subroutine of the conversion processing A3. In this conversion processing A3, the computer converts each of all logic cells in which glitches possibly occurs out of all the logic cells in the i-th stage (the first stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells. This operation is described in detail below.

The computer confirms whether or not a plurality of signals is to be inputted to the logic cell in the i-th stage in the processing target path P (step S251). In a case where one signal is to be inputted to the logic cell in the i-th stage (“N” in step S251), the processing proceeds to step S256.

In step S251, in a case where a plurality of signals is inputted to the logic cell in the i-th stage (step S251), the computer confirms whether or not the logic cell in the i-th stage satisfies the glitch determination condition C (step S252). The glitch determination condition C is a condition for determining whether or not a glitch possibly occurs in the logic cell. Specifically, the glitch determination condition C is that a delay amount in the logic cell is less than or equal to a time difference between transition timings of the plurality of signals to be inputted. In a case where this logic cell does not satisfy the glitch determination condition C (“N” in step S253), the computer determines that no glitch occurs in this logic cell, and the processing proceeds to step S256.

In a case where this logic cell satisfies the glitch determination condition C in step S252(“Y” in step S253), the computer determines that a glitch possibly occurs in this logic cell, and converts this logic cell into one or a plurality of glitch suppression cells (step S254).

Thereafter, the computer updates timing information in the design data (step S255). That is, the computer has converted the logic cell into one or a plurality of glitch suppression cells in step S254; therefore, the delay amount in this logic cell has been changed. Accordingly, the computer updates the timing information in the design data.

Next, the computer confirms whether or not the variable i is equal to the stage number M (i=M) (step S256). In a case where the variable i is smaller than the stage number M (“N” in step S256), the computer increments the variable i (step S257), and the processing returns to step S251. The computer repeats processing in steps S251to S257until the variable i becomes equal to the stage number M. Thus, out of all logic cells in the first and subsequent stages in the processing target path P, each of all logic cells in which glitches possibly occurs is converted into one or a plurality of glitch suppression cells.

In a case where the variable i is equal to the stage number M in step S256(“Y” in step S256), the computer ends the subroutine of the conversion processing A3.

Next, the computer confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P (step S204). In the example inFIG.45, the computer confirms whether or not a glitch occurs in an output of the latch circuit104in a subsequent stage in the processing target path P. In a case where no glitch occurs (“N” in step S205), this processing ends.

In a case where a glitch occurs in step S204(“Y” in step S205), the computer converts this latch circuit into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this latch circuit (step S206). In a case where no glitch occurs (“N” in step S207), this processing ends.

In a case where a glitch occurs in step S206(“Y” in step S207), the computer restores the latch circuit converted in step S206, and all logic cells converted in step S203in the processing target path P to the initial state (step S208).

Next, the computer sets the variable j to “1” (j=1) (step S209).

Next, the computer converts an input signal to the logic cell in the j-th stage in the processing target path P into a 2-wire signal, converts the logic cell in the j-th stage into a QDI logic cell, and converts an output signal of this QDI logic cell into a 1-wire signal (step S210). This causes the output signal of this QDI logic cell to be inputted to the logic cell in a stage subsequent to the QDI logic cell (in the j+1-th stage). It is to be noted that in a case where the logic cell in a stage (the j−1-th stage) preceding to the logic cell in the j-th stage is a QDI logic cell, a 2-wire signal outputted from the logic cell in the j−1-th stage is supplied as it is to the logic cell in the j-th stage.

Next, the computer confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P (step S211). In a case where no glitch occurs (“N” in step S212), this processing ends.

In a case where a glitch occurs in step S211(“Y” in step S212), the computer converts this latch circuit into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this latch circuit (step S213). In a case where no glitch occurs (“N” in step S214), this processing ends.

In a case where a glitch occurs in step S213(“Y” in step S214), the computer restores the latch circuit converted in step S213to the initial state (step S215).

Next, the computer sets the variable i to “j+1” (i=j+1) (step S216), and performs the conversion processing A3(step S217). In the conversion processing A3, as illustrated inFIG.47, the computer converts each of all logic cells in which a glitch possibly occurs out of all logic cells in the i-th stage (the j+1-th stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells.

Next, the computer confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P (step S218). In a case where no glitch occurs (“N” in step S219), this processing ends.

In a case where a glitch occurs in step S218(“Y” in step S219), the computer converts this latch circuit into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this latch circuit (step S220). In a case where no glitch occurs (“N” in step S221), this processing ends.

In a case where a glitch occurs in step S220(“Y” in step S221), the computer restores the latch circuit converted in step S220to the initial state, and restores all logic cells other than the QDI logic cell in the processing target path P to the initial state (step S222). Thus, all the logic cells converted in step S217in the processing target path P are restored to the initial state.

Next, the computer confirms whether or not the variable j is equal to the stage number M (j=M) (step S223). In a case where the variable j is smaller than the stage number M (“N” in step S223), the computer increments the variable j (step S224), and the processing returns to step S110. Thus, the computer converts the logic cell in the j+1-th stage into a QDI logic cell in step S210. By this operation, the computer converts logic cells into QDI logic cells in order from the logic cell in the first stage, and the number of QDI logic cells is increased by one. The computer repeats operations in steps S210to S224until no glitch occurs.

In a case where the variable j is equal to the stage number M in step S223(“Y” in step S223), the computer ends this processing.

Using this circuit conversion method makes it possible to suppress glitches in one or more of the AND circuit101(the reference sign W7), the OR circuit102(the reference sign W8), the NAND circuit103in the processing target path P illustrated inFIG.45, for example, and the latch circuit in the subsequent stage in the processing target path P. In this circuit conversion method, in the asynchronous logic circuit2, various processing target paths P are set, and processing is performed on each of these processing target paths P. As a result, in the asynchronous logic circuit2, it is possible to suppress glitches.

As described above, in the circuit conversion method, for example, as illustrated in step S201, the computer sets the processing target path P in the asynchronous logic circuit2. Thereafter, as illustrated in step S252of the conversion processing A3in step S203, for example, the computer performs first processing for determining whether or not a glitch occurs in each of a plurality of logic cells in the processing target path P. Thereafter, for example, as illustrated in steps S253and S254of the conversion processing A3in step S203, the computer performs second processing including conversion processing for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells. The one or more glitch suppression logic cells are configured to suppress glitches, and performs the same logical operation as the one or more logic cells. Thereafter, as illustrated in steps S204to S207, after this second processing, the computer performs third processing for determining whether or not a glitch occurs in a latch circuit that is a subsequent-stage circuit in the processing target path P. Accordingly, in this circuit conversion method, it is possible to convert a logic cell in which a glitch is determined to occur into a glitch suppression logic cell, which makes it possible to suppress glitches.

Thereafter, in this circuit conversion method, for example, as illustrated in step S208, in a case where a glitch is determined as occurring in the third processing, the computer performs fourth processing for changing the plurality of logic cells in the processing target path P to the initial state. Thereafter, for example, as illustrated in step S210, after this fourth processing, the computer performs fifth processing for sequentially selecting one of the plurality of logic cells in the processing target path P and converting the selected logic cell into a QDI logic cell. Thereafter, for example, as illustrated in steps S211to S214, the computer performs sixth processing for determining whether or not a glitch occur in a latch circuit that is a subsequent-stage circuit every time one of the plurality of logic cells is selected in the fifth processing. Accordingly, in this circuit conversion method, it is possible to effectively suppress glitches while reducing a circuit area.

As described above, in the present embodiment, the computer sets the processing target path in the asynchronous logic circuit. Thereafter, the computer performs the first processing for determining whether or not a glitch occurs in each of the plurality of logic cells in the processing target path. Thereafter, the computer performs the second processing including the conversion processing for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells. The one or more glitch suppression logic cells are configured to suppress glitches, and perform the same logical operation as the one or more logic cells. Thereafter, after this second processing, the computer performs the third processing for determining whether or not a glitch occurs in a latch circuit that is a subsequent-stage circuit in the processing target path. Thus, it is possible to suppress glitches.

Modification Example 2-1

In the embodiment described above, as illustrated inFIGS.46A to46C and13, in step S103, all logic cells satisfying the glitch determination condition C are converted into one or a plurality of glitch suppression cells, and thereafter, in steps S204and S206, it is confirmed whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. Likewise, in step S117, all logic cells satisfying the glitch determination condition C are converted into one or a plurality of glitch suppression cells, and thereafter, in steps S218and S220, it is confirmed whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. However, this is not limitative. Instead of this, all logic cells satisfying the glitch determination condition C may be selected one by one, and the selected one logic cell may be converted into one or a plurality of glitch suppression cells, and for every conversion, it may be confirmed whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. A circuit conversion method according to the present modification example is described in detail below.

FIGS.48A and48Billustrate an example of the circuit conversion method according to the present modification example.

First, the computer identifies the processing target path P where circuit conversion is to be performed, and obtains the stage number M of logic cells in the processing target path P (step S201).

Next, the computer sets the variable i to “1” (i=1) (step S202), and performs conversion processing A4(step S233). In this conversion processing A4, the computer sets all logic cells in i-th and subsequent stages in the processing target path P as processing targets. In this example, the variable i is set to “1” in step S102; therefore, the computer sets all logic cells in “1”st and subsequent stages in the processing target path P as processing targets of the conversion processing A4.

FIGS.49A and49Billustrate a subroutine of the conversion processing A4. In this conversion processing A3, the computer selects, one by one, all logic cells in which glitches possibly occurs out of all the logic cells in the i-th stage (the first stage in this example) and subsequent stages in the processing target path P, converts the selected one logic cell into one or a plurality of glitch suppression cells, and confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. This operation is described in detail below.

The computer confirms whether or not a plurality of signals is to be inputted to the logic cell in the i-th stage in the processing target path P (step S251). In a case where one signal is to be inputted to the logic cell in the i-th stage (“N” in step S251), the processing proceeds to step S256.

In step S251, in a case where a plurality of signals is to be inputted to the logic cell in the i-th stage (step S251), the computer confirms whether or not the logic cell in the i-th stage satisfies the glitch determination condition C (step S252). In a case where this logic cell does not satisfy the glitch determination condition C (“N” in step S253), the computer determines that no glitch occurs in this logic cell, and the processing proceeds to step S256.

In a case where this logic cell satisfies the glitch determination condition C in step S252(“Y” in step S253), the computer determines that a glitch possibly occurs in this logic cell, and converts this logic cell into one or a plurality of glitch suppression cells that performs the same operation (step S254). Thereafter, the computer updates the timing information in the design data (step S255).

Next, the computer confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P (step S271). In the example inFIG.45, the computer confirms whether or not a glitch occurs in an output of the latch circuit104in a subsequent stage in the processing target path P. In a case where no glitch occurs (“N” in step S272), this processing ends.

In a case where a glitch occurs in step S271(“Y” in step S272), the computer convert this latch circuit into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this latch circuit (step S273). In a case where no glitch occurs (“N” in step S274), this processing ends.

In a case where a glitch occurs in step S273(“Y” in step S274), the computer restores the latch circuit converted in step S273, and all logic cells converted in step S254in the processing target path P to the initial state (step S275). Thus, all the logic cells in the processing target path P are restored to the initial state.

Next, the computer confirms whether or not the variable i is equal to the stage number M (i=M) (step S256). In a case where the variable i is smaller than the stage number M (“N” in step S256), the computer increments the variable i (step S257), and the processing returns to step S251. Thus, one logic cell of all the logic cells satisfying the glitch determination condition C is converted into one or a plurality of glitch suppression cells, and it is confirmed whether a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. Thereafter, this operation is repeated until no glitch occurs.

In a case where the variable i is equal to the stage number M in step S256(“Y” in step S256), the computer ends the subroutine of the conversion processing A4.

In step S233, in a case where glitches continuously occur, the computer next sets the variable j to “1” (j=1) (step S209).

Next, the computer converts an input signal to the logic cell in the j-th stage in the processing target path P into a 2-wire signal, converts the logic cell in the j-th stage into a QDI logic cell, and converts an output signal of this QDI logic cell into a 1-wire signal (step S210).

Next, the computer confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P (step S211). In a case where no glitch occurs (“N” in step S212), this processing ends.

In a case where a glitch occurs in step S211(“Y” in step S212), the computer converts this latch circuit into a glitch suppression cell, and confirms whether or not a glitch occurs in an output of this latch circuit (step S213). In a case where no glitch occurs (“N” in step S214), this processing ends.

In a case where a glitch occurs in step S213(“Y” in step S214), the computer restores the latch circuit converted in step S213to the initial state (step S215).

Next, the computer sets the variable i to “j+1” (i=j+1) (step S216), and performs the conversion processing A4(step S237). In the conversion processing A4, as illustrated inFIGS.49A and49B, the computer converts one of all logic cells in which a glitch possibly occurs out of all logic cells in the i-th stage (the j+1-th stage in this example) and subsequent stages in the processing target path P into one or a plurality of glitch suppression cells, and confirms whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P. Thereafter, this operation is repeated until no glitch occurs.

In step S237, in a case where a glitch continuously occurs, the computer next restores the latch circuit converted in step S273to the initial state, and restores all logic cells other than the QDI logic cell in the processing target path P to the initial state (step S222).

Next, the computer confirms whether or not the variable j is equal to the stage number M (j=M) (step S223). In a case where the variable j is smaller than the stage number M (“N” in step S223), the computer increments the variable j (step S224), and the processing returns to step S210.

In a case where the variable j is equal to the stage number M in step S223(“Y” in step S223), the computer ends this processing.

Modification Example 2-2

In the embodiment described above, as illustrated inFIG.45, the port of the signal to be inputted from the completion detection circuit70to the SDI register60is identified, and a signal path from this port to the input terminal of the latch circuit104in the SDI register60is identified as the processing target path P, but this is not limitative. Instead of this, for example, a longer signal path including this signal path may be identified as the processing target path P. Specifically, for example, inFIG.50, a port of a signal to be inputted from the C-elements62and63of the SDI register60C to the NOR circuit64is identified, and a signal path from this port to the input terminal of the latch circuit104through the NOR circuit64, the completion detection circuit70C, the AND circuit101, the OR circuit102, and the NAND circuit103may be identified as the processing target path P.

Modification Example 2-3

In the embodiment described above, the circuit conversion method illustrated inFIGS.46A to46C and47is used, but the circuit conversion method is not limited thereto. For example, even in a case where it is not possible to completely suppress glitches, conversion processing may end without affecting the operation.

Modification Example 2-4

In the embodiment described above, inFIGS.46A to46C, for example, as illustrated in steps S204, S206, S211, S213, S218, and S220, it is confirmed whether or not a glitch occurs in an output of a latch circuit in a subsequent stage in the processing target path P, but this is not limitative. Instead of this, for example, it may be confirmed whether or not a glitch occurs in an output of a C-element in a subsequent stage in the processing target path P. This C-element in the subsequent stage in the processing target path P may be, for example, the C-element62or63in the SDI latch circuit61.

Other Modification Examples

In addition, two or more of these modification examples may be combined.

The present technology has been described above with reference to some embodiments and the modification examples, but the present technology is not limited to the embodiments and the like, and may be modified in a variety of ways.

For example, in the embodiments described above, the present technology is applied to the bundled-data asynchronous logic circuit and the 2-wire SDI circuit, but the present technology is not limited thereto. The present technology may be applied to, for example, a 2-wire QDI circuit and an NCL (Null Convention Logic) circuit.

It is to be noted that the effects described herein are merely illustrative and non-limiting, and other effects may be provided.

It is to be noted that the present technology may have the following configurations. According to the present technology having the following configurations, it is possible to suppress glitches.

A circuit conversion method including:causing a computer to set a processing target path in an asynchronous logic circuit;causing the computer to perform first processing for determining whether or not a glitch occurs in each of a plurality of logic cells in the processing target path;causing the computer to perform second processing including conversion processing for converting one or more logic cells in which a glitch is determined to occur in the first processing into one or more glitch suppression logic cells, the one or more glitch suppression logic cells that are configured to suppress glitches, and perform same logical operation as the one or more logic cells; andcausing the computer to perform, after the second processing, third processing for determining whether or not a glitch occurs in a subsequent-stage circuit in the processing target path.
(2)

The circuit conversion method according to (1), in which the first processing including determining whether or not a glitch occurs in each of one or a plurality of logic cells to which a plurality of signals is to be inputted out of the plurality of logic cells by comparing a difference between transition timings of the plurality of signals to be inputted with a delay amount of a logic cell as a processing target.

The circuit conversion method according to (1) or (2), in which the second processing includes performing the conversion processing on all of the one or more logic cells in which a glitch is determined to occur in the first processing.

The circuit conversion method according to (1) or (2), in whichthe second processing includes sequentially selecting one of the one or more logic cells in which a glitch is determined to occur in the first processing, performing the conversion processing on the selected logic cell, and changing one or more logic cells other than the selected logic cell out of the one or more logic cells to an initial state, andthe third processing includes confirming whether or not a glitch occurs in the subsequent-stage circuit every time one of the one or more logic cells is selected in the second processing, and determining that a glitch occurs in a case where a glitch occurs in the subsequent-stage circuit whichever logic cell is selected from the one or more logic cells.
(5)

The circuit conversion method according to any one of (1) to (4), in whichthe third processing includesdetermining whether or not a glitch occurs in the subsequent-stage circuit,converting the subsequent-stage circuit into a glitch suppression circuit in a case where a glitch is determined occur in the subsequent-stage circuit, the glitch suppression circuit that is configured to suppress glitches, and performs same logical operation as the subsequent-stage circuit, anddetermining whether or not a glitch occurs in the subsequent-stage circuit converted into the glitch suppression circuit.
(6)

The circuit conversion method according to any one of (1) to (5), further including:causing the computer to perform fourth processing for changing the plurality of logic cells in the processing target path to an initial state in a case where a glitch is determined to occur in the third processing;causing the computer to perform fifth processing for sequentially selecting one of the plurality of logic cells and converting the selected logic cell into a QDI logic cell; andcausing the computer to perform sixth processing for determining whether or not a glitch occurs in the subsequent-stage circuit every time one of the plurality of logic cells is selected in the fifth processing.
(7)

The circuit conversion method according to (6), further including:causing the computer to perform seventh processing for converting one or more logic cells subsequent to one or a plurality of logic cells converted into the QDI logic cell in the fifth processing into one or more glitch suppression logic cells in a case where a glitch is determined to occur in the sixth processing, the one or more glitch suppression logic cells that are configured to suppress glitches; andcausing the computer to perform, after the seventh processing, eighth processing for determining whether or not a glitch occurs in the subsequent-stage circuit.
(8)

The circuit conversion method according to any one of (1) to (7), in whichthe asynchronous logic circuit includes a bundled-data logic circuit, andthe subsequent-stage circuit includes a C-element.
(9)

The circuit conversion method according to any one of (1) to (7), in whichthe asynchronous logic circuit includes a 2-wire SDI circuit, andthe subsequent-stage circuit includes a latch circuit or a C-element.
(10)

A latch circuit including:a first inverter having an input terminal coupled to an input node, and an output terminal;a first transistor of P-type having a gate coupled to the output terminal of the first inverter, a source coupled to a power supply node, and a drain led to an first node;a second transistor of P-type having a gate to which a clock signal is to be inputted, a source coupled to the power supply node, and a drain led to the first node;a third transistor of N-type having a gate to which the clock signal is to be inputted, a drain led to the first node, and a source;a fourth transistor of N-type having a gate coupled to the output terminal of the first inverter, a drain coupled to the source of the third transistor, and a source coupled to a ground node;a fifth transistor of P-type having a gate coupled to the first node, a source coupled to the power supply node, and a drain led to a second node;a sixth transistor of N-type having a gate to which the clock signal is to be inputted, a drain led to the second node, and a source;a seventh transistor of N-type having a gate coupled to the input node, a drain coupled to the source of the sixth transistor, and a source;an eighth transistor of N-type having a gate coupled to the first node, a drain coupled to the source of the seventh transistor, and a source coupled to the ground node;a NOR circuit having a first input terminal to which a reset signal is to be inputted, a second input terminal coupled to the second node, and an output terminal coupled to a third node;a ninth transistor of P-type provided in a path coupling the power supply node and the second node, and having a gate coupled to the third node, a source, and a drain;a tenth transistor of P-type provided in a path coupling the power supply node and the second node, and having a gate to which the clock signal is to be inputted, a source, and a drain;an eleventh transistor of N-type provided in a path coupling the second node and the ground node, and having a gate coupled to the first node, a drain, and a source;a twelfth transistor of N-type provided in a path coupling the second node and the ground node, and having a gate coupled to the third node, a drain, and a source;a second inverter having an input terminal coupled to the third node, and an output terminal; anda third inverter having an input terminal led to the output terminal of the second inverter, and an output terminal coupled to an output node.
(11)

The latch circuit according to (10), further including one or more transistors provided in one or more of a first path, a second path, a third path, a fourth path, and a fifth path, the first path coupling the drain of the first transistor and the drain of the second transistor to the first node, the second path coupling the first node and the drain of the third transistor, the third path coupling the drain of the fifth transistor and the second node, the fourth path coupling the second node and the drain of the sixth transistor, and the fifth path coupling the output terminal of the second inverter and the input terminal of the third inverter.

The latch circuit according to (11), in which the one or more transistors include a thirteenth transistor of P-type provided in the first path, and having a gate coupled to the ground node, a source coupled to the drain of the first transistor and the drain of the second transistor, and a drain coupled to the first node.

The latch circuit according to (11) or (12), in which the one or more transistors include a fourteenth transistor of N-type provided in the second path, and having a gate coupled to the power supply node, a drain coupled to the first node, and a source coupled to the drain of the third transistor.

The latch circuit according to any one of (11) to (13), in which the one or more transistors include a fifteenth transistor of P-type provided in the third path, and having a gate coupled to the ground node, a source coupled to the drain of the fifth transistor, and a drain coupled to the second node.

The latch circuit according to any one of (11) to (14), in which the one or more transistors include a sixteenth transistor of N-type provided in the fourth path, and having a gate coupled to the power supply node, a drain coupled to the second node, and a source coupled to the drain of the sixth transistor.

The latch circuit according to any one of (1) to (15), in whichthe one or more transistors includea seventeenth transistor of P-type provided in the fifth path, and having a gate coupled to the ground node, andan eighteenth transistor of N-type provided in the fifth path, and having a gate coupled to the power supply node.
(17)

A C-element circuit including:a nineteenth transistor of P-type having a gate coupled to a first input node, a source coupled to a power supply node, and a drain;a twentieth transistor of P-type having a gate coupled to a second input node, a source coupled to the drain of the nineteenth transistor, and a drain led to a fourth node;a twenty-first transistor of N-type having a gate coupled to the second input node, a drain coupled to the fourth node, and a source;a twenty-second transistor of N-type having a gate coupled to the first input node, a drain coupled to the source of the twenty-first transistor, and a source coupled to a ground node;a twenty-third transistor of P-type having a gate coupled to the second input node, a source coupled to the power supply node, and a drain;a twenty-fourth transistor of P-type having a gate, a source coupled to the drain of the twenty-third transistor, a drain led to the fourth node;a twenty-fifth transistor of N-type having a gate, a drain led to the fourth node, and a source;a twenty-sixth transistor of N-type having a gate coupled to the second input node, a drain coupled to the source of the twenty-fifth transistor, and a source coupled to the ground node;a NOR circuit having a first input terminal to which a reset signal is to be inputted, a second input terminal coupled to the fourth node, and an output terminal coupled to a fifth node;a fourth inverter having an input terminal coupled to the fifth node, and an output terminal;a fifth inverter having an input terminal led to the output terminal of the fourth inverter, and an output terminal coupled to an output node; andone or more transistors provided in one or more of a sixth path, a seventh path, an eighth path, a ninth path, and a tenth path, the sixth path coupling the drain of the twentieth transistor and the fourth node, the seventh path coupling the fourth node and the drain of the twenty-first transistor, the eighth path coupling the drain of the twenty-fourth transistor and the fourth node, the ninth path coupling the fourth node and the drain of the twenty-fifth transistor, and the tenth path coupling the output terminal of the fourth inverter and the input terminal of the fifth inverter.
(18)

The C-element circuit according to (17), further including:a twenty-seventh transistor of P-type having a gate coupled to the first input node, a source coupled to the power supply node, and a drain coupled to the drain of the twenty-third transistor and the source of the twenty-fourth transistor; anda twenty-eighth transistor of N-type having a gate coupled to the first input node, a drain coupled to the source of the twenty-fifth transistor and the drain of the twenty-sixth transistor, and a source coupled to the ground node, in whichthe gate of the twenty-fourth transistor is coupled to the fifth node, andthe gate of the twenty-fifth transistor is coupled to the fifth node.
(19)

The C-element circuit according to (17), further including:a twenty-ninth transistor of P-type provided in a path coupling the drain of the nineteenth transistor and the source of the twentieth transistor to the drain of the twenty-third transistor and the source of the twenty-fourth transistor, and having a gate coupled to the first input node; anda thirtieth transistor of N-type provided in a path coupling the source of the twenty-first transistor and the drain of the twenty-second transistor to the source of the twenty-fifth transistor and the drain of the twenty-sixth transistor, and having a gate coupled to the first input node, in whichthe gate of the twenty-fourth transistor is coupled to the fifth node, andthe gate of the twenty-fifth transistor is coupled to the fifth node.
(20)

The C-element circuit according to (17), further including:a thirty-first transistor of P-type provided in a path coupling the drain of the nineteenth transistor and the source of the twentieth transistor to the drain of the twenty-third transistor and the source of the twenty-fourth transistor, and having a gate coupled to the fifth node; anda thirty-second transistor of N-type provided in a path coupling the source of the twenty-first transistor and the drain of the twenty-second transistor to the source of the twenty-fifth transistor and the drain of the twenty-sixth transistor, and having a gate coupled to the fifth node, in whichthe gate of the twenty-fourth transistor is coupled to the first input node, andthe gate of the twenty-fifth transistor is coupled to the first input node.
(21)

The C-element circuit according to any one of (17) to (20), in which the one or more transistors include a thirty-third transistor of P-type provided in the sixth path, and having a gate coupled to the ground node, a source coupled to the drain of the twentieth transistor, and a drain coupled to the fourth node.

The C-element circuit according to any one of (17) to (21), in which the one or more transistors include a thirty-fourth transistor of N-type provided in the seventh path, and having a gate coupled to the power supply node, a drain coupled to the fourth node, and a source coupled to the drain of the twenty-first transistor.

The C-element circuit according to any one of (17) to (22), in which the one or more transistors include a thirty-fifth transistor of P-type provided in the eighth path, and having a gate coupled to the ground node, a source coupled to the drain of the twenty-fourth transistor, and a drain coupled to the fourth node.

The C-element circuit according to any one of (17) to (23), in which the one or more transistors include a thirty-sixth transistor of N-type provided in the ninth path, and having a gate coupled to the power supply node, a drain coupled to the fourth node, and a source coupled to the drain of the twenty-fifth transistor.

The C-element circuit according to any one of (17) to (24), in whichthe one or more transistors includea thirty-seventh transistor of P-type provided in the tenth path, and having a gate coupled to the ground node, anda thirty-eighth transistor of N-type provided in the tenth path, and having a gate coupled to the power supply node.

This application claims the priority on the basis of Japanese Patent Application No. 2022-023217 filed on Feb. 17, 2022 with Japan Patent Office, the entire contents of which are incorporated in this application by reference.