Method to fabricate an intrinsic polycrystalline silicon film

A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer; converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.5 microns in size; patterning an oxide layer into a transistor gate oxide, thus leaving uncovered sections of said grained silicon on opposing sides of said transistor gate oxide; conductively doping said uncovered sections of said grained silicon; forming a patterned metal gate on said transistor gate oxide.

FIELD OF THE INVENTION
 This invention relates to semiconductor fabrication processing and more
 particularly to a method for forming large grain polysilicon films for
 semiconductor structures, such as thin film transistors used in random
 access memories.
 BACKGROUND OF THE INVENTION
 In current technology to fabricate thin film field effect transistors, an
 intrinsic silicon film, ideally having high charge carrier mobility, is
 needed for the transistor channel. The conventional approach to obtain
 such a film is to anneal an amorphous silicon film either by rapid thermal
 annealing step or by low temperature furnace annealing, which requires
 considerable processing time. The resultant film has a large grain size
 and therefore the acceptable carrier mobility needed for the device.
 However, this approach requires a high temperature process in the case of
 rapid thermal anneal or long processing time in the case of furnace
 anneal. The high temperature should be avoided in most thin film
 transistor fabrication because of the extensive use of metal electrodes.
 The long processing time is not desired due to the slow through put
 required for each wafer to be processed.
 A major problem that must be overcome is that the thin film transistor is
 formed after the metal lines of the memory device have been fabricated.
 Once metal lines are formed, the subsequent fabrication steps that follow
 must stay below the re-flow temperature, or melting point, of the metal
 used. The present invention discloses a method to form very-large grain
 silicon as a way to increase charge carrier mobility of a thin film
 transistor pullup device, while avoiding high temperatures and long
 annealing times.
 SUMMARY OF THE INVENTION
 Exemplary implementations of the present invention comprise processes for
 forming a large grain silicon film for use in a semiconductor assembly.
 The process first forms hemispherical grain (HSG) silicon over a
 semiconductor assembly substrate by deposition of HSG silicon directly, or
 by converting an amorphous silicon layer seeded with silicon nucleation
 sites into HSG silicon by annealing. Next, an amorphous silicon layer is
 formed directly on the hemispherical silicon grain surface. Next, an
 anneal step is performed to cause the amorphous silicon layer to convert
 into large silicon grains that use the hemispherical grain silicon as a
 base.

DETAILED DESCRIPTION OF THE INVENTION
 Exemplary implementations of the present invention directed to processes
 for forming a large grain silicon film, which may be used to develop a
 thin film transistor in a semiconductor device, are depicted in FIGS. 1-3.
 A first exemplary implementation of the present invention is depicted in
 FIGS. 1A-1D. Referring to FIG. 1A, substrate 10 comprising a
 semiconductive material, such as a silicon wafer, is prepared for the
 processing steps of the present invention. During preparation, an
 insulation layer 11, overlying substrate 10 is formed to isolate a
 subsequently formed thin film transistor (TFT) from substrate 10. Next, an
 amorphous silicon layer 12 is formed over the top of insulation layer 11.
 Amorphous silicon layer 12 is formed with conventional fabrication
 techniques using deposition temperatures ranging from 500.degree. C. to
 550.degree. C. For example, an amorphous silicon layer having a thickness
 of approximately 300 angstroms can be deposited by presenting a
 silicon-based gas and nitrogen to the semiconductor assembly for time of
 30 minutes at the temperature range above. At 500.degree. C. to
 550.degree. C. and with a silicon to nitrogen ratio of 10:1 or 20:1,
 amorphous silicon is deposited at a rate of 10 angtroms/minute. After
 amorphous silicon layer 12 is formed, silicon nucleation sites 13 are
 formed on top of amorphous silicon layer 12.
 Silicon nucleation sites 13 can also be formed by conventional fabrication
 techniques. For example, one method is to deposit silicon at a temperature
 of 550.degree. C. to 650.degree. C., using a silicon-based gas (such as
 SiH.sub.4, SiH.sub.6, etc.) in combination with an inert gas (such as
 N.sub.2, He.sub.2, etc.), which results in the formation of silicon
 nucleation sites 13. Though silicon nucleation sites 13 appear uniform in
 size and in distribution, (in the cross-section of FIG. 1A) the
 representation of the silicon nucleation sites in FIG. 1A is not intended
 to indicate that the resulting silicon nucleation will necessarily result
 in such a pattern or size. The actual silicon nucleation sites 13 may vary
 in size and be distributed in a more random fashion than as depicted.
 However, to gain the desired large grain silicon of the present invention,
 it is desired that silicon nucleation sites 13 be approximately 200
 angstroms or less in size and separated from one another by approximately
 0.1 micron to 0.5 microns. The development of silicon nucleation sites 13
 and the spaces between them are controlled by the length of time the
 silicon-based gas is allowed to develop the silicon to nucleate. To gain
 the desired spacing, the silicon-based gas is presented to the
 semiconductor assembly for approximately 10 minutes and at the temperature
 range of 550.degree. C. to 650.degree. C. The reason for these desired
 dimension requirements will become apparent as the method of the present
 invention is fully developed.
 Referring to FIG. 1B, silicon nucleation sites 13 and amorphous silicon
 layer 12 are subjected to an annealing step at a temperature of
 550.degree. C. to 650.degree. C. to convert the amorphous silicon film
 into HSG silicon layer 14 by using silicon nucleation sites 13 as seeding
 for grain formation. The annealing step is performed for a period of time
 that is sufficient to convert the entire amorphous silicon to HSG. For
 example, to convert a 300 angstroms amorphous silicon layer to HSG at a
 temperature range of 550.degree. C. to 650.degree. C., the annealing step
 will need to be conducted for a period of 10 minutes to 20 minutes. The
 largest grain size that can be obtained by conventional method used to
 form HSG silicon is 500 angstroms to 1000 angstroms, which is less than 2
 to 5 times the desired grain size of the present invention. In order to
 create the very-large grain size of the present invention all processing
 steps are employed.
 Referring to FIG. 1C, a second amorphous silicon layer 15 is deposited
 directly on HSG silicon 14. The desired thickness of amorphous silicon
 layer 15 is 500 angstroms to 1000 angstroms. To obtain the desired
 thickness of layer 15 a silicon-based gas and nitrogen having a ration of
 silicon to nitrogen of 20:1, is presented to the semiconductor assembly at
 a temperature of 500.degree. C. to 550.degree. C. for a time period of 10
 minutes to 20 minutes. Amorphous silicon layer 15 will provide the
 catalyst to form the very-large grain silicon of the present invention.
 Next, amorphous silicon layer is subjected to an annealing step at a
 temperature from 550.degree. C. to 580.degree. C. to convert silicon layer
 15 into very-large grain silicon layer 16, as shown in FIG. 1D. The
 annealing step is performed for a period of time that is sufficient to
 convert the entire amorphous silicon to large grain silicon. For example,
 to convert a 500 angstroms amorphous silicon layer into large grain
 silicon at a temperature range of 550.degree. C. to 580.degree. C., the
 annealing step will need to be conducted for a period of 10 minutes to 20
 minutes. It is preferred that this annealing step be performed insitu
 after the deposition of amorphous silicon layer 15.
 The size of the resulting very-large grain silicon is controlled by silicon
 nucleation sites 13, amorphous layer 15 and the annealing temperature
 used. The average size of the large grain silicon that can be obtained
 directly relates to the distance between individual nucleation sites. As
 taught previously, the desired distance between silicon nucleation sites
 13 is between 0.1 to 0.5 microns (1000 angstroms to 5000 angstroms). Thus,
 the resulting large silicon grain will be between the range of 0.1 to 0.5
 microns, an optimum size grain for intrinsic polycrystalline silicon films
 that may be used to form various devices for a semiconductor assembly,
 namely a thin film transistor.
 A second exemplary implementation of the present invention is depicted in
 FIGS. 2A-2C. Referring to FIG. 2A, HSG silicon 22 is deposited on
 insulation layer 21, which resides on substrate 20. HSG silicon 22 can be
 deposited by creating silicon nucleation sites at a temperature of
 550.degree. C. to 650.degree. C., using a silicon-based gas (such as
 SiH.sub.4, SiH.sub.6, etc.) in combination with an inert gas (such as
 N.sub.2, He.sub.2, etc.). The silicon nucleation is allowed to continue
 until HSG silicon, having a grain size of approximately 500 angstroms to
 1000 angstroms is obtained. Other methods to form HSG silicon, such as HSG
 formation methods taught in U.S. Pat. No. 5,418,180, U.S. and U.S. Pat.
 No. 5,721,171, assigned to the assignee of the present application, and
 are hereby incorporated by reference as if set forth in their entirety.
 Though HSG silicon 22 appears uniform in size and in distribution, (in the
 cross-section of FIG. 2A) the representation of the HSG silicon in FIG. 2A
 is not intended to indicate that the resulting HSG silicon will
 necessarily result in such a pattern or size. The actual HSG silicon 22
 may vary in size and be distributed in a more random fashion than as
 depicted. However, to gain the desired large grain silicon of the present
 invention, it is desired that HSG silicon 22 be approximately 500
 angstroms to 1000 angstroms and be separated from one another, at each
 grain center, by approximately 0.1 micron to 0.5 microns, as taught in the
 first embodiment of the present invention.
 Referring to FIG. 2B, an amorphous silicon layer 23 is deposited directly
 on HSG silicon 22. Amorphous silicon layer 23 will provide the catalyst to
 form the very-large grain silicon of the present invention. Next,
 amorphous silicon layer 23 is subjected to an annealing step at a
 temperature from 550.degree. C. to 580.degree. C. to convert silicon layer
 23 into very-large grain silicon 24, as shown in FIG. 2C. It is preferred
 that this annealing step is performed insitu after the deposition of
 amorphous silicon layer 23.
 The size of the resulting very-large grain silicon is controlled by the
 size and spacing of HSG silicon 24, amorphous layer 23 and the annealing
 temperature employed. The desired distance between the centers of HSG
 silicon 22 is between 0.1 to 0.5 microns. Thus the resulting large silicon
 grain will be within the range of 0.1 to 0.5 microns across. To obtain the
 desired layer thickness and grain size, deposition conditions are the same
 as taught in the first exemplary implementation of the present invention.
 Either of the above exemplary implementations of the present invention can
 be used to fabricate the thin film transistor (TFT) as depicted in FIG. 3.
 Referring to FIG. 3, gate oxide 32 and metal gate 33 are formed and
 patterned on very-large grain silicon layer 31. Next, the very-large grain
 intrinsic silicon layer 31 is conductively doped to form conductive active
 regions 31A on opposing sides of gate oxide 32, while leaving an intrinsic
 silicon portion 31B underlying gate oxide 32 that will function as the
 channel region to the completed TFT. Conductive regions 31A form source
 and drain regions, intrinsic portion 31B forms a channel region, gate
 oxide 32 forms a gate insulation layer and metal gate 33 forms a
 conductive gate which function collectively as a thin film field effect
 transistor. The intrinsic nature of silicon layer 31 will effectively
 operate as a channel region without any light conductive doping prior to
 the formation of the transistor. However, light conductive doping of
 intrinsic layer 31 prior to forming the gate oxide may be conducted if so
 desired to obtain certain transistor operating characteristics.
 Source and drain regions 31A are available for making connections to other
 structures required by a given process, such as a process to form dynamic
 random access memories, static random access memories, or any
 semiconductor device that could implement the TFT of the present
 invention. The semiconductor device is then completed in accordance with
 fabrication processes known to those skilled in the art.
 It is to be understood that although the present invention has been
 described with reference to several preferred embodiments, various
 modifications, known to those skilled in the art, such as utilizing the
 disclosed methods to form programmable floating gate devices, may be made
 to the process steps presented herein without departing from the invention
 as recited in the several claims appended hereto.