Via stack fault detection

A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack.

BACKGROUND

The memory industry is under constant pressure to reduce component size. One way that is being used to reduce component size is to fabricate memory devices as a three-dimensional (3D) memory device. This type of memory device can be achieved by forming a stack of memory cells vertically on a substrate, stacking a plurality of interconnected memory dies vertically within a single integrated circuit package, or some combination of these methods.

Multiple stacked memory dies in a memory package can be coupled (e.g., electrically connected) using vertical connectors, such as through-silicon vias (TSV) or other 3D conductive structures. Vias extend (at least partially) through a thickness of one or more of the dies and can be aligned when the dies are stacked, thus providing electrical communication among the dies in the stack. Such vias are often formed of a conductive material, such as aluminum or copper.

Once the integrated circuit dies are stacked and connected through the vias, it can be difficult to determine the location of a fault in the via stack. There are resulting needs for determining via stack faults.

DETAILED DESCRIPTION

A through-silicon via (TSV) is a vertical electrical connection passing at least partially through an integrated circuit wafer or die. These connections are referred to in the art as TSVs even though the die may comprise some material other than silicon (e.g., germanium). TSVs can be used to create three-dimensional (3D) packages of integrated circuits that can result in higher density integrated circuit packages with shorter, faster connections. The terms TSVs and vias can refer to any type of vertical connector that results in a connection between a plurality of dies.

The subsequent disclosure refers to a via stack. This can be defined as a respective via, from each die of a plurality of dies, being coupled together (e.g., die-to-die interconnect) in a series string of vias. The via stack can be either vertical, as shown inFIGS. 1 and 2, or horizontal.

FIG. 1illustrates a cross-sectional view of an apparatus including an integrated circuit die stack incorporating vias. This figure is for purposes of illustration only as the subsequently described embodiments do not require the use of solder bumps nor that the plurality of dies be stacked vertically. For example, the method ofFIG. 3can be used in detecting a fault in a connection between a plurality of horizontally coupled dies.

Once the plurality of dies has been connected through the vias, the individual vias of each die, as well as the connection itself, can become inaccessible. Thus, if the die connection process results in a via connection that is shorted to another connection, an open connection, or a connection that includes some foreign matter (e.g., an oxide) that reduces the conductivity of that connection, it can be difficult to access the individual connections to determine where the fault lies.

FIG. 1shows a plurality of dies101-104(e.g., wafers) that are stacked vertically. A respective via111-114of each die101-104can be coupled to an adjacent die through a die-to-die interconnect122-124(e.g., solder bumps). An external connection121can be provided to access the via stack100.

Each of the plurality of dies101-104can include one or more circuits. For example, one die101might include circuits for a memory controller while the other dies102-104can include memory circuits such as memory cells (e.g., DRAM, Flash). In such an embodiment, the via stack100can be used to connect the memory controller circuitry to the memory cells.

Each of the dies101-104can include a respective receiver circuit131-134. The respective receiver circuit131-134is coupled to its respective via111-114for that particular die101-104. The respective receiver circuit131-134for each die101-104can include receiver circuitry (e.g., buffers, amplifiers, logic) for coupling the die stack to the circuitry on the respective die101-104. The respective receiver circuit131-134can also include circuitry to be used for identification, addressing, and control functions, of each die101-104, as used in the subsequently described via stack fault detection method.

As described subsequently, the embodiment ofFIG. 1uses an external connection121(e.g., solder bump) to the via stack100in order to supply a voltage to the via stack100as well as measure a resulting current. However, as seen inFIG. 2, the via stack fault detection method can operate without this external connection121.

Each of the receivers131-134of their respective dies101-104includes a selectable reference voltage circuit (e.g., circuit ground) as described subsequently with reference toFIG. 3. In operation, when a particular die/receiver is selected, its selectable reference voltage circuit can be enabled to be connect the die's respective via to circuit ground, thus grounding the via stack100up to that particular die in the stack. Any voltage now applied to the external connection121can cause a current to flow to ground through particular ones of the dies101-104up to the selected die. By measuring the resulting current, a resistance can be calculated and compared to an expected resistance. Any variation from the expected resistance can be used to detect a fault in the via stack100. Operation of the selectable reference voltage circuit and the resulting via stack fault detection is described subsequently with reference toFIGS. 3 and 4.

FIG. 2illustrates a cross-sectional diagram of another apparatus of an integrated circuit die stack incorporating vias but without an external connection to the via stack200. This embodiment includes a plurality of dies201-204, each with a respective via211-214. The vias211-214are coupled to the respective via211-214of an adjacent die201-214through a die-to-die interconnect222-224(e.g., solder bump).

The embodiment ofFIG. 2includes a via211in DIE1201that does not have an external connection. Such a via211can connect various circuit levels within the die201that can be coupled to the adjacent die202and the remaining via stack200through the die-to-die interconnect222.

As described subsequently, the embodiment ofFIG. 2uses an internal connection to the via stack200in order to supply the voltage to the via stack200as well as measure a resulting current. The internal connection can be supplied by circuitry in the receiver231of DIE1201that is coupled to the DIE1via211.

Each of the receivers231-234of their respective dies201-204includes a selectable reference voltage circuit (e.g., circuit ground) as described subsequently with reference toFIG. 3. In operation, when a particular die/receiver is selected, its reference voltage circuit can be enabled in order to couple the die's respective via to circuit ground. Another die, having a switchably coupled supply voltage from an internal connection, can apply a supply voltage to the via stack and cause a current to flow to ground through particular ones of the dies201-204up to the selected die. By measuring the resulting current, a resistance can be calculated and compared to an expected resistance. Any variation from the expected resistance can be used to detect a fault in the via stack200. Operation of the selectable reference voltage circuit and the resulting via stack fault detection is described subsequently with reference toFIGS. 3 and 4.

Both of the embodiments ofFIG. 1andFIG. 2can operate in substantially the same way, as described in the method illustrated inFIG. 4. The use of either an internal connection or an external connection to apply the supply voltage does not affect the method for applying the voltage to the via stack100,200, the detection of the via stack fault, or the resulting measurements.

FIG. 3illustrates a block diagram of an embodiment of the receiver131-134ofFIG. 1and the receiver231-234ofFIG. 2. This figure is for purposes of illustration only since other circuits can provide the same receiver functionality as well as the same identification, addressing, and/or control functionality as the illustrated block diagram. For example, one or more of the receivers can use a direct chip select signal without an identification circuit301. Thus, only an active chip select signal can select a respective die.

The various dies of the above embodiments can include memory circuitry and/or other circuits that can be substantially identical. For example, the receivers131-134,231-234of each die can be substantially identical on two or more of the dies. Any memory circuits can have the same memory architecture including memory addressing and share common command, address, and/or data buses. These buses can be part of a via.

In order for an external controller circuit (not shown) to target a specific memory unit or other circuitry in the stacks of dies, an active chip select signal can be used. The active chip select signal can cause circuits on a specific die to process incoming commands, addresses, and/or data provided on common command, address, and/or data buses. Substantially simultaneously with the active chip select signal, the other dies are provided inactive chip select signals that cause those specific dies to ignore the incoming commands, addresses, and/or data.

Another embodiment can use an address decoder on each die in order to decode an incoming address. Each die can have a unique assigned address so that the circuitry on that particular die becomes active when the address for that particular die is received (e.g., valid address). The other dies, each having different respective addresses (e.g., invalid addresses), would have inactive circuitry.

Using the chip select scheme, the addressing scheme, or some other die selection scheme, the receiver131-134,231-234on each die can be selected individually while the other receivers on the other dies will be inactive (i.e., deselected). Thus, the die identification circuit301can include a chip select receiving circuit, if the received control signal is a chip select signal, or an address decoder, if the received control signal is an address. The die identification circuit301can then generate one or more enable signals (e.g., EN1, EN2) that can be used by both the die circuitry (e.g., memory circuitry) and/or the respective die receiver blocks as described subsequently. The enable signals (e.g., EN1, EN2) are active when the particular respective die receiver is being accessed and inactive when the particular respective die receiver is not being accessed (e.g., another receiver is being accessed).

The receiver can further include receiver circuitry303that can be used to control and/or process any signals received from the via stack. For example, the receiver circuitry303can include buffers, amplifiers, and/or switches (e.g., transistors) for buffering, amplifying, and/or switching on/off, respectively, received signals from the via. The output of the receiver circuitry303is coupled to the die circuitry (e.g., memory cells, controller).

The receiver can further include a selectable reference voltage circuit305(e.g., selectable ground circuit) switchably coupled to its respective via300. When enabled by an active control signal, EN2, the selectable reference voltage circuit can pull the via300to the reference voltage (e.g., ground). The selectable reference voltage circuit305can be a transistor whose control gate is coupled to the EN2signal. In operation, an enable voltage on the control gate of the transistor can couple the via300to ground. Since the via300is part of the via stack100,200, the via stack100,200up to the selected die is coupled to ground.

The receiver can further include a supply voltage enable circuit307. The supply voltage enable circuit307can be used in the apparatus ofFIG. 2when no external connection is available to the stack of dies or it is not desirable to apply the supply voltage to an available external connection. Thus, the supply voltage enable circuit307can provide a supply voltage to the via300and, thus, to the via stack. The supply voltage enable circuit307can also include circuitry to determine a resulting current once a reference voltage enable circuit, of a selected receiver, has been selected to the reference voltage (e.g., ground). The supply voltage enable circuit307can include a transistor having a source coupled to the supply voltage VCC, a drain coupled to the via300, and a control gate coupled to the enable signal EN1. In operation, an active supply voltage enable signal, EN1, can be applied to the supply voltage enable circuit307to enable the transistor that couples the supply voltage VCCto the via300. Since the via300is coupled to the via stack100,200, the via stack100,200is coupled to the supply voltage.

The die selected to have its respective via coupled to ground is different than the die having its respective via coupled to the supply voltage. This would preclude the same die having its via coupled to both ground and the supply voltage simultaneously. In one embodiment, the lowest die in a stack of dies is the die to which the supply voltage can be coupled to its respective via.

The illustrated via300can include one of the vias ofFIG. 1 or 2111-114,211-214. This via300is one via in the via stack100,200of the illustrated embodiments.

FIG. 4illustrates a flowchart of an embodiment of a method for via stack fault detection. The method includes selecting one of a plurality of dies401. As previously described, selecting one of the plurality of dies can be accomplished with an active chip select signal while the unselected dies receive an inactive chip select signal. The selecting can also be accomplished by addressing the die. The selected die now forms one end of a subset of the plurality of dies (e.g., dies under test). The other end of the subset of the plurality of dies is the die comprising the connection to the supply voltage.

The respective receiver for the selected die can be enabled403. Enabling the receiver may be accomplished with the same signal(s) for selecting the die or a separate, active receiver enable signal can be received by the receiver.

A signal is sent to the selected die to cause the reference voltage to be connected to the respective via of the selected die (e.g., short the via to ground)405. The supply voltage is then applied to an end of the via stack407that is opposite the via stack end comprising the via shorted to ground. This can be accomplished through either the external connection or using an internal circuit to apply the supply voltage as described previously. In both cases, the supply voltage can be considered to be switchably coupled to the via stack.

The resulting current can be measured409and the resistance of the via stack, up to the selected die, can then be calculated411. One skilled in the art knows that R=V/I.

The calculated resistance can then be compared to an expected resistance in order to determine if a fault exists in the via stack413. The expected resistances can be determined by an estimation process of multiplying a resistance of one via by the number of vias in the via stack. The expected resistances can also be determined during the die fabrication process by measuring the different resistances of various quantities of stack dies. Other embodiments can determine the expected resistances in other ways.

If the calculated resistance approximately equals the expected resistance415, there is no fault in the via stack419. If the calculated resistance does not equal the expected resistance415, a fault has been found in the via stack417. For example, if the calculated resistance is infinite, an open connection exists in the via stack. If the calculated resistance is relatively low, a shorted connection exists in the via stack. The above process can be repeated using a subset of the tested dies in order to narrow down which die via or which die-to-die interconnect caused the fault.

In another embodiment, instead of calculating the resistance, the measured current can be used to determine if a fault exists in the via stack. For example, the measured current can be compared to a known good current. If the current is too low or non-existent, a fault may have been detected. For example, no current flow would be evidence of an open connection in the via stack. Low current flow would be evidence of a bad connection in the via stack. The expected measured current can be determined in substantially the same manner as the expected resistance.

As an example of operation, referring to the apparatus ofFIG. 1and method ofFIG. 4, if DIE3has been selected by an active chip select signal or an address, when the reference voltage circuit305of the receiver133is enabled, a path to ground now exists from the external connection121through DIE1101, DIE2102, and DIE3103. DIE4104, being above the selected DIE3103, will not be coupled to ground. Thus, the current from the external connection121through DIE1101, DIE2102, and DIE3103will test the die-to-die interconnects122,123and the vias111-113but not the die-to-die interconnect124between DIE3103and DIE4104. A similar process can be used with an internal connection to supply voltage in DIE1.

If a resistance is calculated that does not approximately equal the expected resistance, the process can be repeated but DIE2102can then be selected and the receiver132of that die102enabled such that the reference voltage circuit of that particular receiver couples the via112to ground. The supply voltage is applied and the current measured. If the resistance is still not what is expected, then the die-to-die interconnect122between DIE1101and DIE2102is defective or one of the first via111or the second via112is defective. If the resistance from the repeated process now approximately equals the expected resistance, it has been determined that the die-to-die interconnect123between DIE2102and DIE3103is defective or the via113of DIE3103is defective.

As used herein, an apparatus may refer to, for example, circuitry, an integrated circuit die, a memory device, a memory array, or a system including such a circuit, die, device or array.

CONCLUSION

One or more embodiments of the method and apparatus for detecting a via stack fault can determine if a via stack includes shorted connection, an open connection, or a bad solder joint by measuring a resulting current from an applied supply voltage. Thus, even connections with no external access can be tested with the described embodiments.