Semiconductor device and method of fabrication

A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2008-123674 filed in Japan on May 9, 2008, and Patent Application No. 2009-029623 filed in Japan on Feb. 12, 2009, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a semiconductor device including a plurality of semiconductor chips within the same package.

In recent years, as electronic apparatuses that have more functions and are smaller in size have been developed, semiconductor devices used therein have also been caused to be more multifunctional and thinner. The development of a semiconductor device including a plurality of semiconductor chips within the same package has been required. To achieve such a purpose, there is a conventional known semiconductor device having a structure in which a plurality of semiconductor chips are provided on the same die pad, or a structure in which a plurality of die pads are provided within the same package, and further, a plurality of semiconductor chips are provided on the respective die pads.

Hereinafter, a structure of a conventional semiconductor device, specifically, a Quad Flat Package (QFP package) having a plurality of die pads within the same package, will be described with reference toFIGS. 10A and 10Band11A to11E.

FIGS. 10A and 10Bare cross-sectional views of a structure of a QFP package as a conventional semiconductor device.

In the conventional QFP package ofFIGS. 10A and 10B, die pads101and102are formed within the same package. The die pads101and102have a Point Support Die pad (PSD) structure. A semiconductor chip104is electrically connected via an electrically conductive resin103to the die pad101. A semiconductor chip105is electrically connected via the electrically conductive resin103to the die pad102. Electrodes106on the semiconductor chips104and105are electrically connected via gold wires109to inner leads108of a lead frame107that is a part of the package. The semiconductor chips104and105are also electrically connected to each other via gold wires109so that they can exchange information. The resultant structure is sealed with a sealing resin, which forms an outer shape of the semiconductor device.

As can be seen fromFIGS. 10A and 10B, in the conventional QFP package having the structure described above, the die pads101and102are positioned at different heights, but not at the same height. Thus, in a PSD structure in which semiconductor chips provided on die pads have larger sizes than those of the respective die pads, the arrangement of the die pads at different heights allows portions of semiconductor chips extending off the respective upper and lower die pads to three-dimensionally overlap each other, as shown inFIG. 10B. Therefore, an area occupied by all of the semiconductor chips within the package is reduced, so that the package can be reduced in size.

Next, a method for fabricating a conventional semiconductor device (QFP package) will be described.

Initially, as shown inFIG. 11A, an electrically conductive resin103is applied onto die pads101and102.

Next, as shown inFIG. 11B, semiconductor chips105and106are mounted onto the die pads101and102, respectively, with the electrically conductive resin103being interposed therebetween. When the semiconductor chips105and106have regions overlapping each other, the semiconductor chips105and106will be damaged if the semiconductor chips105and106contact each other. Therefore, in order to prevent from the semiconductor chips105and106from contacting each other, the semiconductor chips105and106need to be carefully isolated from each other in a region where the semiconductor chips105and106three-dimensionally overlap each other. After the semiconductor chips105and106are mounted, the electrically conductive resin103is cured in a curing furnace (not shown).

Next, as shown inFIG. 11C, gold wires109connecting a lead frame107and the semiconductor chips104and105and gold wire109connecting the semiconductor chips104and105are provided by performing a wire bonding step. During wire bonding between the semiconductor chips104and105, it is necessary to hold the semiconductor chips104and105in a manner that prevents the semiconductor chips104and105from contacting each other.

Next, as shown inFIG. 11D, a sealing step is performed by a known technique using a sealing mold and a sealing resin114.

Next, as shown inFIG. 11E, a step of working the lead frame107is performed. Packages are isolated from each other along the lead frame107. A shape of an external connection lead111of the lead frame107is changed. Thus, a semiconductor device is completed.

As described above, a semiconductor chip is mounted in a resin package, so that the semiconductor chip is allowed to function while electrical connection thereof is protected from external environments (the above description is based on Japanese Unexamined Patent Application Publication No. 2005-347428).

Also, Japanese Unexamined Patent Application Publication No. 2008-28006 discloses a semiconductor device that includes separate die pads and has excellent heat dissipating capability. In this semiconductor device, a common metal plate for heat dissipation is provided for a plurality of die pads, and the heat dissipating metal plate is exposed from a sealing resin. Note that the die pads are provided on the same plane while sharing the heat dissipating metal plate, so that a chip having a larger size than that of a die pad cannot be connected to the die pad, for example.

SUMMARY

The aforementioned semiconductor device has a multi-layered structure in which semiconductor chips three-dimensionally overlap each other, so that the package has a large thickness. Therefore, the semiconductor device has a large height when mounted. Moreover, when two or more semiconductor chips are mounted, an influence of heat generated form each semiconductor chip needs to be taken into consideration. When a semiconductor chip having a large increase in temperature and a semiconductor chip having a small increase in temperature are mounted within the same package, it is necessary to efficiently dissipate heat generated during an operation of the semiconductor chips to the outside. Therefore, it is necessary to achieve a semiconductor device having a structure that reduces the height of layered semiconductor chips and the influence of heat generated from the semiconductor chips.

However, in the arrangement of die pads or the multi-layered structure of semiconductor chips in the aforementioned conventional semiconductor device, there is space particularly in a vertical direction between the semiconductor chips. Therefore, the thickness of a package is increased, resulting in an outer shape that is not suitable for high-density packaging. Moreover, such a structure does not allow a heat dissipating structure to mount a semiconductor chip generating a large amount of heat and a semiconductor chip generating a small amount of heat. Therefore, an abnormal operation of the semiconductor device is likely to occur due to heat.

In view of the problems described above, an object of the present disclosure is to provide a semiconductor device having a structure that allows a plurality of semiconductor chips to be mounted within the same package without increasing the thickness of the package, and a method of fabrication thereof.

Also, a semiconductor device is preferably provided that has a structure that allows a plurality of semiconductor chips that have different power consumptions and heat power densities and are provided on a plurality of die pads electrically and thermally isolated from each other, to be mounted within the same package without increasing the thickness of the package. A method of fabrication thereof is preferably provided.

Specifically, the following example means is provided.

A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.

The second resin material refers to a material that prevents heat generated by the first semiconductor chip from transferring to the second semiconductor chip, or heat generated by the second semiconductor chip from transferring to the first semiconductor chip, i.e., a resin material having an adiabatic effect. For example, the second resin material may include a synthetic resin containing a phenol resin, a polyethylene resin, a polypropylene resin or the like as a major component thereof. The second resin material thus defined is equivalent to a thermal insulator as set forth in the appended claims and the specification.

In the semiconductor device, the first and second die pads are preferably electrically isolated from each other. The first and second die pads are preferably provided at positions different from each other in a vertical direction.

In the semiconductor device, one of the first and second die pads is preferably grounded.

In the semiconductor device, a thermal conductivity of the second resin material is lower than a thermal conductivity of the first resin material.

In the semiconductor device, the lower surface of the first die pad is preferably exposed from the sealing resin.

In the semiconductor device, the first semiconductor chip preferably has a high heat generation circuit region having a relatively high amount of heat generated during a circuit operation and a low heat generation circuit region having a relatively low amount of heat generated during the circuit operation. There is preferably space between a region contacting the second resin material of the first semiconductor chip, and the high heat generation circuit region.

In the semiconductor device, a length of the space is preferably larger than or equal to a thickness of the first semiconductor chip.

A method for fabricating a semiconductor device including a plurality of semiconductor chips, includes the steps of (a) providing a first die pad and a second die pad electrically isolated from each other, (b) mounting a first semiconductor chip on an upper surface of the first die pad, and (c) mounting the second semiconductor chip on the second die pad in a manner that contacts a portion of a lower surface of the second semiconductor chip to an upper surface of the second die pad, and a portion extending off the second die pad of the lower surface of the second semiconductor chip to an upper surface of the first semiconductor chip via a thermal insulator.

In the method, the step (c) preferably includes forming the thermal insulator on a portion of the upper surface of the first semiconductor chip before mounting the second semiconductor chip.

According to the semiconductor device and a method of fabrication thereof, a plurality of semiconductor chips can be highly densely mounted within the same package. Moreover, die pads are electrically and thermally isolated from each other. Therefore, even if semiconductor chips have different power consumptions or amounts of generated heat, the semiconductor chips can be less affected by each other. Therefore, it is possible to provide a semiconductor device having stable quality with low cost.

DETAILED DESCRIPTION

Hereinafter, the technical idea of the present disclosure will be described in detail with reference to the accompanying drawings. Various modifications and additions can be made to embodiments disclosed herein without departing the spirit and scope of the present disclosure by those skilled in the art after understanding the present disclosure. Also, a plurality of embodiments described below can be combined in any manner as long as the combination still falls within the spirit and scope of the present disclosure.

First Embodiment

Hereinafter, a first example semiconductor device will be described.

FIGS. 1A to 1Care diagrams showing a structure of the first example semiconductor device.FIG. 1Ais a cross-sectional view schematically showing an internal structure of the semiconductor device.FIG. 1Bis a plan view schematically showing a lead frame of the semiconductor device.FIG. 1Cis a plan view schematically showing an internal structure of the semiconductor device as viewed from the top.

As shown inFIG. 1A, this semiconductor device has die pads1and2. The die pads1and2have a difference in level in a direction perpendicular to a surface thereof on which a semiconductor chip is mounted. In other words, the die pads1and2are arranged and positioned at different heights in a vertical direction. A semiconductor chip4is mounted on the die pad1positioned at the lower height in the package of the semiconductor device with an electrically conductive resin3being interposed therebetween. In other words, a lower surface of the semiconductor chip4is electrically connected to the die pad1. A semiconductor chip5is provided on the die pad2positioned above the die pad1with an electrically conductive resin3being interposed therebetween. A circuit formation surface of the semiconductor chip4is connected via a thermal insulator12to a lower surface of the semiconductor chip5. In other words, a portion of the lower surface of the semiconductor chip5is electrically connected to the die pad2, while another portion of the lower surface of the semiconductor chip5that is not connected to the die pad2is connected via the thermal insulator12to the upper surface of the semiconductor chip4.

Some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5. The other electrodes6on the semiconductor chip4and the other electrodes6on the semiconductor chip5are connected via respective gold wires9to respective inner leads8. The resultant structure is enclosed and sealed with a sealing resin14to form a package, from which external connection leads11are extended to the outside.

As used herein, the thermal insulator12refers to a material that prevents heat generated by the semiconductor chip4from transferring via the thermal insulator12to the semiconductor chip5or heat generated by the semiconductor chip5from transferring via the thermal insulator12to the semiconductor chip4as described above, i.e., a resin material having an adiabatic effect. Moreover, the thermal insulator12is preferably a material that is different from a resin material (described below) for the sealing resin14and has a lower thermal conductivity than that of the sealing resin14. A commonly used epoxy resin as a major component of the sealing resin14has a thermal conductivity of 0.2 W/m·K, and therefore, the thermal insulator12preferably includes a material having a lower thermal conductivity than that of the epoxy resin. For example, the thermal insulator12may include a synthetic resin containing a phenol resin, a polyethylene resin, a polypropylene resin or the like as a major component thereof.

Also, as shown inFIG. 1B, in this semiconductor device, the semiconductor chips4and5contact each other while being layered. As described above, some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5, and the other electrodes6on the semiconductor chip4and the other electrodes6on the semiconductor chip5are connected via respective gold wires9to respective inner leads8. In particular, when the die pads1and2are connected to the ground (GND), GND terminals of the semiconductor chips4and5connected to the die pads1and2are connected via gold wires9to inner leads8that are electrically connected via suspender leads10to the die pads1and2.

Next, as shown inFIG. 1C, in this semiconductor device, the die pads1and2share no suspender leads10in a lead frame7. Therefore, the die pads1and2are electrically and thermally isolated from each other. A portion of the suspender leads10supporting the die pads1and2are linked to the corresponding inner leads8. As a result, when it is desired that the die pads1and2be connected to GND, the inner leads8linked to the suspender leads10are connected to GND.

As described above, according to the structure of this semiconductor device, a plurality of semiconductor chips having different power consumptions or heat power densities can be mounted on a plurality of respective die pads that are electrically and thermally isolated from each other, within the same package, without increasing the thickness of the package. Moreover, such a structure allows a heat dissipating structure to mount a semiconductor chip generating a large amount of heat and a semiconductor chip generating a small amount of heat.

Variation of First Embodiment

FIG. 2shows a structure of a variation of the first example semiconductor device.

As shown inFIG. 2, in this semiconductor device, the die pad1is exposed from the package of the semiconductor device. Specifically, the die pad1is exposed at a portion corresponding to the lowest one of steps of the lead frame7. Note that the other parts of this semiconductor device are similar to the corresponding parts ofFIGS. 1A to 1Cand will not be described.

The structure ofFIG. 2is required, particularly when a semiconductor chip has a high heat power density and therefore heat dissipation by the package itself is not enough to operate the semiconductor chip. In this case, the exposed surface of the die pad1is connected to a mounting substrate for the semiconductor device using solder so as to forcedly dissipate heat. Specifically, the heat dissipating capability of a semiconductor device that has a power consumption of more than 15 W needs to be increased, though the amount of heat generated in a semiconductor chip varies depending on the packaging density, the chip size, the power consumption, ambient temperature during operation, or the like. Therefore, a semiconductor device having a structure in which a die pad is exposed is useful. A semiconductor device having the structure ofFIG. 2is particularly useful when a memory, and a semiconductor element having a power consumption of more than 15 W are mounted within the same package.

Second Embodiment

Hereinafter, a second example semiconductor device will be described. Note that this second example semiconductor device includes three die pads.

FIGS. 3A to 3Care diagrams showing a structure of the second example semiconductor device.FIG. 3Ais a cross-sectional view schematically showing an internal structure of the semiconductor device.FIG. 3Bis a plan view schematically showing a lead frame of the semiconductor device.FIG. 3Cis a plan view schematically showing an internal structure of the semiconductor device as viewed from the top.

As shown inFIG. 3A, the semiconductor device includes die pads1,2and15. The die pads1,2and15have differences in level in a direction perpendicular to a surface thereof on which a semiconductor chip is mounted. In other words, the die pads1,2and15are arranged and positioned at different heights in a vertical direction. A semiconductor chip4is mounted on the die pad1that is provided at the lowest position in the package of the semiconductor device with an electrically conductive resin3being interposed therebetween. A semiconductor chip5is mounted on the die pad2provided above the die pad1with an electrically conductive resin3being interposed therebetween. A semiconductor chip16is mounted on the die pad15provided above the die pad2with an electrically conductive resin3being interposed therebetween. Moreover, a circuit formation surface of the semiconductor chip4is connected to a lower surface of the semiconductor chip5via a thermal insulator12. A circuit formation surface of the semiconductor chip5is connected to a lower surface of the semiconductor chip16via a thermal insulator12. Specifically, a portion of the lower surface of the semiconductor chip5is electrically connected to the die pad2, while another portion of the lower surface of the semiconductor chip5that is not connected to the die pad2is connected via the thermal insulator12to the upper surface of the semiconductor chip4. Similarly, a portion of the lower surface of the semiconductor chip16is electrically connected to the die pad15, while another portion of the lower surface of the semiconductor chip16that is not connected to the die pad15is connected via the thermal insulator12to the upper surface of the semiconductor chip5.

Some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5. Some electrodes6on the semiconductor chip5are electrically connected via respective gold wires9to some respective electrode6on the semiconductor chip16. The other electrodes6on the semiconductor chip4, the other electrodes6on the semiconductor chip5, and the other electrodes6on the semiconductor chip16are electrically connected via respective gold wires9to respective inner leads8. The resultant structure is enclosed and sealed with a sealing resin14to form a package, from which external connection leads11are extended to the outside.

As described above, the thermal insulator12as used herein refers to a material that prevents heat generated by the semiconductor chip4from transferring via the thermal insulator12to the semiconductor chip5, heat generated by the semiconductor chip5from transferring via the thermal insulator12to the semiconductor chip4or16, or heat generated by the semiconductor chip16from transferring via the thermal insulator12to the semiconductor chip5, i.e., a resin material having an adiabatic effect. Moreover, the thermal insulator12is preferably a material that is different from a resin material (described below) for the sealing resin14and has a lower thermal conductivity than that of the sealing resin14. A commonly used epoxy resin as a major component of the sealing resin14has a thermal conductivity of 0.2 W/m·K, and therefore, the thermal insulator12preferably includes a material having a lower thermal conductivity than that of the epoxy resin. For example, the thermal insulator12may include a synthetic resin containing a phenol resin, a polyethylene resin, a polypropylene resin or the like as a major component thereof.

Although it has been assumed above that the number of semiconductor chips mounted within the same package is three, more than three semiconductor chips may be mounted within the same package. This can be similarly achieved by increasing the number of layers (steps) in the aforementioned multi-layered (staircase-like) structure.

Also, as shown inFIG. 3B, in this semiconductor device, the semiconductor chips4,5and16contact each other while being layered. As described above, some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5, and some electrodes6on the semiconductor chip5are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip16. The other electrodes6on the semiconductor chip4, the other electrode6on the semiconductor chip5, and the other electrodes6on the semiconductor chip16are electrically connected via respective gold wires9to respective inner leads8.

Next, as shown inFIG. 3C, in this semiconductor device, the die pads1,2and15share no suspender leads10in a lead frame7. Therefore, the die pads1,2and15are electrically and thermally isolated from each other. A portion of the suspender leads10supporting the die pads1,2and15are linked to the corresponding inner leads8. As a result, when it is desired that the die pads1,2and15be connected to GND, the inner leads8linked to the suspender leads10are connected to GND.

As described above, according to the structure of this semiconductor device, a plurality of semiconductor chips having different power consumptions or heat power densities can be mounted on a plurality of respective die pads that are electrically and thermally isolated from each other, within the same package, without increasing the thickness of the package. Moreover, such a structure allows a heat dissipating structure to mount a semiconductor chip generating a large amount of heat and a semiconductor chip generating a small amount of heat.

Variation of Second Embodiment

FIG. 4shows a structure of a variation of the second example semiconductor device.

As shown inFIG. 4, in this semiconductor device, the die pad1is exposed from the package of the semiconductor device. Specifically, the die pad1is exposed at a portion corresponding to the lowest one of steps of the lead frame7. Note that the other parts of this semiconductor device are similar to the corresponding parts ofFIGS. 3A to 3Cand will not be described. The structure of this variation has advantages similar to those which have been described using the structure ofFIG. 2.

Third Embodiment

Hereinafter, a third example semiconductor device will be described. Note that the third example semiconductor device has three die pads, two of which are positioned at the same height.

FIGS. 5A to 5Care diagrams showing a structure of the third example semiconductor device.FIG. 5Ais a cross-sectional view schematically showing an internal structure of the semiconductor device.FIG. 5Bis a plan view schematically showing a lead frame of the semiconductor device.FIG. 5Cis a plan view schematically showing an internal structure of the semiconductor device as viewed from the top.

As shown inFIG. 5A, this semiconductor device has die pads1,2and15. The die pads1and15are arranged and positioned at the same height. The semiconductor chips4and16are mounted on the die pads1and15provided at the lower position in the package of the semiconductor device with electrically conductive resins3being interposed therebetween, respectively. A semiconductor chip5is mounted on the die pad2provided above the die pads1and15with an electrically conductive resin3being interposed therebetween. Circuit formation surfaces of the semiconductor chips4and16are connected via respective thermal insulators12to a lower surface of the semiconductor chip5. Specifically, a middle portion of the lower surface of the semiconductor chip5is electrically connected to the die pad2, while peripheral portions of the lower surface of the semiconductor chip5that are not connected to the die pad2are connected via the thermal insulators12to upper surfaces of the semiconductor chips4and16.

Some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5. Some electrodes6on the semiconductor chip5are electrically connected via respective gold wires9to some respective electrodes6of the semiconductor chip16. The other electrodes6on the semiconductor chip4, the other electrode6on the semiconductor chip5, and the other electrodes6on the semiconductor chip16are electrically connected via respective gold wires9to respective inner leads8. The resultant structure is enclosed and sealed with a sealing resin14to form a package, from which external connection leads11are extended to the outside. The thermal insulator12is made of a material which has been described in the second embodiment. Although it has been assumed above that the number of semiconductor chips mounted within the same package is three, more than three semiconductor chips may be mounted within the same package. This can be similarly achieved by providing a structure in which some die pads are arranged at the same height as described above.

Also, as shown inFIG. 5B, in this semiconductor device, the semiconductor chips4,5and16contact each other while being layered. As described above, some electrodes6on the semiconductor chip4are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip5, and some electrodes6on the semiconductor chip5are electrically connected via respective gold wires9to some respective electrodes6on the semiconductor chip16. The other electrodes6on the semiconductor chip4, the other electrode6on the semiconductor chip5, and the other electrodes6on the semiconductor chip16are electrically connected via respective gold wires9to respective inner leads8.

Also, as shown inFIG. 5C, in this semiconductor device, the die pads1,2and15share no suspender leads10in a lead frame7. Therefore, the die pads1,2and15are electrically and thermally isolated from each other. A portion of the suspender leads10supporting the die pads1,2and15are linked to the corresponding inner leads8. As a result, when it is desired that the die pads1,2and15be connected to GND, the inner leads8linked to the suspender leads10are connected to GND.

As described above, according to the structure of this semiconductor device, a plurality of semiconductor chips having different power consumptions or heat power densities can be mounted on a plurality of respective die pads that are electrically and thermally isolated from each other, within the same package, without increasing the thickness of the package. Moreover, such a structure allows a heat dissipating structure to mount a semiconductor chip generating a large amount of heat and a semiconductor chip generating a small amount of heat. Also, although the structure ofFIGS. 3A to 3Chas a thickness corresponding to the sum of the heights of three semiconductor chips, the structure ofFIGS. 5A to 5Chas a thickness corresponding to the sum of the heights of two semiconductor chips. Therefore, the thickness of the semiconductor device ofFIGS. 5A to 5Ccan be reduced as compared to the structure ofFIGS. 3A to 3C.

Variation of Third Embodiment

FIG. 6shows a structure of a variation of the third example semiconductor device.

As shown inFIG. 6, in this semiconductor device, the die pads1and15are exposed from the package of the semiconductor device. Specifically, the die pads1and15are exposed at a portion corresponding to the lowest one of steps of the lead frame7. Note that the other parts of this semiconductor device are similar to the corresponding parts ofFIGS. 5A to 5Cand will not be described. The structure of this variation has advantages similar to those which have been described using the structure ofFIG. 2. Moreover, although the structure ofFIG. 4has a thickness corresponding to the sum of the heights of three semiconductor chips, the structure ofFIG. 6has a thickness corresponding to the sum of the heights of two semiconductor chips. Therefore, the thickness of the semiconductor device ofFIG. 6can be reduced as compared to the structure ofFIG. 4.

Fourth Embodiment

Hereinafter, a structure of a fourth example semiconductor device will be described. Note that a positional relationship between contact regions of semiconductor chips in a circuit configuration of the semiconductor chips when heat power densities are distributed in a semiconductor chip, will be described. This embodiment is applicable to all of the embodiments above.

FIG. 7Ashows a two-dimensional arrangement of chips in this semiconductor device.FIG. 7Bshows a cross-sectional arrangement of the chips in this semiconductor device, schematically showing how heat transfers.

As shown inFIG. 7A, when there is a high heat generation circuit area17having a high heat power density of a circuit configured in a semiconductor chip4, a distance a between a semiconductor chip5and the high heat generation circuit area17, and a thickness t of the semiconductor chip4need to satisfy a relationship a>t.

Here, the relationship a>t will be described with reference toFIG. 7B.

A time that it takes for heat to transfer from the high heat generation area17to a lower surface the semiconductor chip4is sR=t/σ, where σ represents a heat transfer rate in the semiconductor chip. A time that it takes for heat to transfer from the high heat generation area17to the semiconductor chip5is sC=a/σ. If a>t, then sR<sC. In other words, the time that it takes for heat to transfer from the high heat generation area17to the lower surface of the semiconductor chip4is shorter than the time that it takes for heat to transfer from the high heat generation area17to the semiconductor chip5.

In this case, if the lower surface of the semiconductor chip4is connected to a die pad1, is exposed from a sealing resin14as in the variation of each embodiment above, and is attached to a mounting substrate with solder, heat dissipated from the high heat generation area17is allowed to transfer to the die pad1having higher heat dissipating capability through the shorter transfer path, which makes it difficult for heat to transfer to the semiconductor chip5.

Fifth Embodiment

Hereinafter, a method for fabricating a fifth example semiconductor device will be described. The fifth example semiconductor device is assumed to have the structure ofFIG. 2, for example.

FIGS. 8A to 8Dand9A to9D are cross-sectional views showing the method for fabricating the fifth example semiconductor device in the order in which steps thereof are performed.

Initially, as shown inFIG. 8A, a lead frame7having two die pads1and2that have a difference in level in a direction perpendicular to a main surface of the die pad on which a semiconductor chip is to be mounted (i.e., the die pads1and2are positioned at different height in a vertical direction), is placed on a lead frame holding plate18having a shape fitting the desired heights of the die pads1and2. Next, an electrically conductive resin3is applied onto the semiconductor chip mounting surfaces of the die pads1and2. In this step, an electrically conductive paste is applied onto both of the die pads1and2. The electrically conductive paste may be an Ag paste containing Ag particles.

Next, as shown inFIG. 8B, a semiconductor chip4having electrodes6on an upper surface thereof is mounted on the die pad1provided at the lower position. Specifically, the semiconductor chip4suction-attached to a collet19is mounted onto the die pad1. Note that semiconductor chips are mounted onto die pads in order of die pad height, lowest first (the lowest die pad1first).

Next, as shown inFIG. 8C, a thermal insulator12is formed in a region where a circuit formation surface of the semiconductor chip4and a semiconductor chip5described below contact each other. Note that the thermal insulator12is similar to that which has been described above with reference toFIG. 2.

Next, as shown inFIG. 8D, the semiconductor chip5suction-attached to the collet19is mounted onto the die pad2while a lower surface of the semiconductor chip5is attached to the thermal insulator12on the semiconductor chip4. As a result, a portion of the lower surface of the semiconductor chip5is electrically connected to the die pad2while another portion of the lower surface of the semiconductor chip5that is not connected to the die pad2is connected via the thermal insulator12to the upper surface of the semiconductor chip4(seeFIG. 9A).

Next, as shown inFIG. 9A, the lead frame7on which the semiconductor chips4and5are mounted is placed in a curing furnace20, followed by heating. As a result, the heating cures an adhesive layer of the electrically conductive resin3and the thermal insulator12. Note that the heating is preferably performed under conditions that prevent a void from remaining in the electrically conductive resin3.

Next, as shown inFIG. 9B, the lead frame7on which the semiconductor chips4and5are mounted is fixed onto a wire bonding stage21, and gold wires9are formed by wire bonding using a capillary22. Wire bonding is performed between the semiconductor chip4and the semiconductor chip5prior to between the semiconductor chips4and5and the lead frame7.

Next, as shown inFIG. 9C, a sealing resin14is injected into the resultant structure using a sealing mold similar to that of the conventional art (sealing step). Here, the die pad1is exposed from the package as shown inFIG. 2.

Next, as shown inFIG. 9D, a working step similar to that of the conventional art is performed. In an assembly step, it is important to cause a shape of a jig for holding the lead frame7having die pads with semiconductor chip mounting surfaces having different heights in the semiconductor chip mounting step or the wire bonding step, to correspond to the difference between the heights.

As described above, according to this semiconductor device fabricating method, a plurality of semiconductor chips having different power consumptions or heat power densities can be mounted on a plurality of respective die pads that are electrically and thermally isolated from each other, within the same package, without increasing the thickness of the package. Moreover, such a structure allows a heat dissipating structure to mount a semiconductor chip generating a large amount of heat and a semiconductor chip generating a small amount of heat.

Although a method for fabricating a semiconductor device having the structure ofFIG. 2has been described above as an example, a method for fabricating semiconductor devices that have the structures ofFIGS. 1 and 3to6and exhibit the aforementioned effect can be contemplated based on this embodiment. For example, when there are three ore more die pads, an electrically conductive resin may be applied onto all of the die pads, semiconductor chips and thermal insulators12may be alternately mounted (e.g., in order of the semiconductor chip4, the thermal insulator12, the semiconductor chip5, the thermal insulator12, and the semiconductor chip6). Moreover, the thermal insulator12may be previously formed on the circuit formation surface of a semiconductor chip when the semiconductor chip is still of a wafer, instead of being formed after the semiconductor chip is mounted on a die pad.

The technique of the present disclosure is useful for a multifunctional semiconductor device, specifically a semiconductor device including a plurality of semiconductor chips within the same package and a method of fabrication thereof.