Display device

A display device including: a lower substrate having a display area and a peripheral area; a plurality of lower electrodes disposed in the display area and on the lower substrate; a pixel defining layer covering a portion of each of the lower electrodes; a light emitting layer disposed on the lower electrodes and the pixel defining layer; an upper electrode disposed on the light emitting layer; a plurality of optical filters disposed on the upper electrode and spaced apart from each other; a lower light blocking layer disposed between the optical filters, and having a plurality of openings; an upper substrate disposed on the lower light blocking layer to oppose the lower substrate; and an alignment structure disposed in the peripheral area of the lower substrate and the upper substrate, and including a material identical to a material of the pixel defining layer and the lower light blocking layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2019-0093206 filed on Jul. 31, 2019 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present invention relate generally to a display device. More particularly, exemplary embodiments of the present invention relate to a display device including an optical filter and a color filter.

DISCUSSION OF THE RELATED ART

Flat panel display devices are used as display devices for replacing a cathode ray tube display device due to being relatively lightweight and thin. Examples of flat panel display devices include a liquid crystal display device and an organic light emitting diode display device.

Recently, a display device including a quantum dot layer and a color filter has been under development. Generally, the display device may include a lower substrate and an upper substrate. Further, in a general manufacturing process of the display device, semiconductor elements, lower electrodes, a light emitting layer, an upper electrode, and the like may be formed on a top surface of the lower substrate, and the quantum dot layer and the color filter may be formed on a bottom surface of the upper substrate. Next, after the top surface of the lower substrate and the bottom surface of the upper substrate are arranged to face each other, the lower substrate and the upper substrate may be coupled to each other by a sealing member, thereby manufacturing the display device.

SUMMARY

According to an exemplary embodiment of the present invention, a display device including: a lower substrate having a display area and a peripheral area at least partially surrounding the display area; a plurality of lower electrodes disposed in the display area and on the lower substrate; a pixel defining layer configured to cover a portion of each of the lower electrodes; a light emitting layer disposed on the lower electrodes and the pixel defining layer; an upper electrode disposed on the light emitting layer; a plurality of optical filters disposed on the upper electrode and spaced apart from each other; a lower light blocking layer disposed between the optical filters, and having a plurality of openings; an upper substrate disposed on the lower light blocking layer to oppose the lower substrate; and an alignment structure disposed in the peripheral area of the lower substrate and the upper substrate, and including a material identical to a material of the pixel defining layer and the lower light blocking layer.

In an exemplary embodiment of the present invention, the lower electrodes, the optical filters, and the openings of the lower light blocking layer overlap each other.

In an exemplary embodiment of the present invention, the lower light blocking layer overlaps the pixel defining layer.

In an exemplary embodiment of the present invention, the alignment structure includes: a first alignment pattern disposed on a bottom surface of the upper substrate; and a second alignment pattern disposed on a top surface of the lower substrate.

In an exemplary embodiment of the present invention, the first alignment pattern and the lower light blocking layer include a same material, and the second alignment pattern and the pixel defining layer include a same material.

In an exemplary embodiment of the present invention, the first alignment pattern includes: a reference pattern; and outer peripheral patterns spaced apart from the reference pattern while surrounding the reference pattern.

In an exemplary embodiment of the present invention, the outer peripheral patterns are spaced apart from each other.

In an exemplary embodiment of the present invention, each of the outer peripheral patterns is spaced apart from the reference pattern at a same interval.

In an exemplary embodiment of the present invention, the second alignment pattern includes a first pattern disposed between the reference pattern and the outer peripheral patterns, wherein the first pattern has a rectangular shape including an opening, and wherein the opening of the first pattern overlaps the reference pattern.

In an exemplary embodiment of the present invention, the second alignment pattern includes a first pattern disposed between the reference pattern and the outer peripheral patterns, wherein the first pattern has a rectangular shape including an opening, and wherein the first pattern surrounds the reference pattern without overlapping the reference pattern and the outer peripheral patterns.

In an exemplary embodiment of the present invention, the second alignment pattern includes: a first pattern disposed between the reference pattern and the outer peripheral patterns, wherein the first pattern has a rectangular shape including an opening; and a second pattern disposed between the first pattern and the lower substrate to overlap the reference pattern, the outer peripheral pattern, and the first pattern.

In an exemplary embodiment of the present invention, the second pattern includes a metal material.

In an exemplary embodiment of the present invention, the display device further includes a plurality of color filters disposed between the lower substrate and the upper substrate, wherein the color filters overlap the optical filters, respectively.

In an exemplary embodiment of the present invention, the display device further includes: a first protective insulating layer disposed between the optical filters and the color filters; and a second protective insulating layer disposed between the lower light blocking layer and the optical filters, wherein the first protective insulating layer and the second protective insulating layer make contact with each other between the optical filters.

In an exemplary embodiment of the present invention, the color filters include: a first color filter disposed on a bottom surface of the upper substrate to transmit blue light, and having a plurality of first openings and a plurality of second openings; second color filters respectively disposed in the first openings on the bottom surface of the upper substrate to transmit red light; and third color filters respectively disposed in the second openings on the bottom surface of the upper substrate to transmit green light.

In an exemplary embodiment of the present invention, the display device further includes an upper light blocking layer disposed between the first color filter and the lower light blocking layer, and having a plurality of openings, wherein the openings of the upper light blocking layer overlap the openings of the lower light blocking layer.

In an exemplary embodiment of the present invention, the optical filters include: a first quantum dot pattern disposed on the second color filters to convert the blue light into the red light; a second quantum dot pattern disposed on the third color filters to convert the blue light into the green light; and a scattering pattern disposed on the first color filter to transmit the blue light.

In an exemplary embodiment of the present invention, the first color filter includes an opening area and a light transmission area, the first and second openings are located in the opening area, and the scattering pattern overlaps the light transmission area.

In an exemplary embodiment of the present invention, the display device further includes: a thin film encapsulation structure disposed in the display area between the upper electrode and the lower light blocking layer; and a sealing member surrounding the display area in the peripheral area between the lower substrate and the upper substrate.

In an exemplary embodiment of the present invention, the light emitting layer is configured to emit blue light, and the light emitting layer is integrally formed in the display area on the lower substrate.

According to an exemplary embodiment of the present invention, a display device includes: a lower substrate having a first area and a second area at least partially surrounding the first area; a plurality of lower electrodes disposed in the first area and on the lower substrate; a pixel defining layer disposed on a portion of each of the lower electrodes; a light emitting layer disposed on the lower electrodes and the pixel defining layer; an upper electrode disposed on the light emitting layer; a plurality of optical filters disposed on the upper electrode and spaced apart from each other; a lower light blocking layer disposed between the optical filters, and having a plurality of openings; an upper substrate opposing the lower substrate; and an alignment structure disposed in the second area of the lower substrate and the upper substrate, and including a first alignment pattern and a second alignment pattern, wherein the first alignment pattern is disposed on a lower surface of the upper substrate, and the second alignment pattern is disposed on an upper surface of the lower substrate.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, display devices and a method of manufacturing a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, same or similar reference numerals may refer to the same or similar elements, and thus repetitive descriptions may be omitted.

FIG. 1is a plan view showing a display device according to an exemplary embodiment of the present invention,FIG. 2is a plan view showing a first color filter included in the display device ofFIG. 1, andFIG. 3is a sectional view taken along line I-I′ ofFIG. 2.

Referring toFIGS. 1, 2, and 3, a display device100may include a lower substrate110, a first semiconductor element250_1, a second semiconductor element2502, a third semiconductor element250_3, a gate insulating layer150, an insulating interlayer190, a planarization layer270, a first lower electrode290_1, a second lower electrode290_2, a third lower electrode290_3, a light emitting layer330, an upper electrode340, a thin film encapsulation structure450, a first protective insulating layer490, a second protective insulating layer495, a plurality of optical filters530, an intermediate layer497, a plurality of color filters510, an upper light blocking layer420, a lower light blocking layer430, a sealing member390, an upper substrate410, etc.

In this case, the first lower electrode290_1, the light emitting layer330, and the upper electrode340form a first sub-pixel structure. In addition, the second lower electrode290_2, the light emitting layer330, and the upper electrode340form a second sub-pixel structure. Further, the third lower electrode290_3, the light emitting layer330, and the upper electrode340form a third sub-pixel structure. The first semiconductor element250_1may include a first active layer130_1, a first gate electrode170_1, a first source electrode210_1, and a first drain electrode230_1. In addition, the second semiconductor element250_2may include a second active layer130_2, a second gate electrode170_2, a second source electrode210_2, and a second drain electrode230_2, and the third semiconductor element250_3may include a third active layer130_3, a third gate electrode170_3, a third source electrode210_3, and a third drain electrode230_3. In addition, the thin film encapsulation structure450may include a first thin film encapsulation layer451, a second thin film encapsulation layer452, and a third thin film encapsulation layer453. In addition, the optical filters530may include a first quantum dot pattern531, a scattering pattern532, and a second quantum dot pattern533. Further, the color filters510may include a first color filter513, a second color filter511, and a third color filter512.

As shown inFIG. 1, the display device100may include a display area10and a peripheral area20at least partially surrounding the display area10. In this case, the display area10may include a plurality of sub-pixel areas30. The sub-pixel areas30may be arranged over the display area10in the form of a matrix.

One of the first to third sub-pixel structures may be disposed in each of the sub-pixel areas30, and the display device100may display an image through the first to third sub-pixel structures. The sealing member390and an alignment structure400which will be described with reference toFIGS. 4 and 5may be disposed in the peripheral area20, and the peripheral area20may correspond to a non-display area. For example, a plurality of transistors, a plurality of capacitors, a plurality of signal wires (e.g., gate signal wires, data signal wires, high power supply voltage wires, light emission signal wires, initialization signal wires, etc.), and the like may be additionally disposed in the display area10, and a plurality of signal wires, a gate driver, a data driver, and the like may be additionally disposed in the peripheral area20.

Although the alignment structure400has been described as being disposed in region ‘A’ ofFIG. 1, a position of the alignment structure400is not limited thereto. For example, the alignment structure400may be disposed in a portion of the peripheral area20. In an exemplary embodiment of the present invention, the alignment structure400may be disposed in the display area10while being adjacent to the sealing member390.

In addition, although the display device100has been described as including one alignment structure400, the configuration of the present invention is not limited thereto. For example, the display device100may include at least two alignment structures.

As shown inFIG. 2, the first color filter513may be disposed in the display area10. The first color filter513may include an opening area11and a light transmission area12. In addition, the first color filter513may have a plurality of first openings513aand a plurality of second openings513b. In this case, the first openings513aand the second openings513bmay be located in the opening area11. For example, the second openings513bmay be spaced apart from the first openings513ain a first direction D1parallel to a top surface of the display device100, respectively. The first openings513amay be spaced apart from each other in a second direction D2orthogonal to the first direction D1, and the second openings513bmay also be spaced apart from each other in the second direction D2. In other words, the first openings513aand the second openings513bmay be parallel to each other. The first openings513aand the second openings513bdisposed in one opening area11may be repeatedly arranged along the first direction D1. In other words, the sub-pixel areas30located in the opening area11may overlap the first openings513aand the second openings513b. For example, the first openings513aand the first sub-pixel structure may overlap each other, and the second openings513band the second sub-pixel structure may overlap each other. Furthermore, no opening may be formed in the light transmission area12. The sub-pixel areas30located in the light transmission area12may overlap the third sub-pixel structure, and a portion overlapping the sub-pixel areas30located in the light transmission area12may function as the first color filter513.

Although each of the display area10, the peripheral area20, and the sub-pixel area30of the present invention has been described as having a rectangular shape when viewed in a plan view, the shape is not limited thereto. For example, each of the display area10, the peripheral area20, and the sub-pixel area30may have a triangular shape, a rhombic shape, a polygonal shape, a circular shape, or an elliptical shape when viewed in a plan view.

Referring again toFIG. 3, the lower substrate110including a transparent or opaque material may be provided. The lower substrate110may include, for example, a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda lime glass substrate, a non-alkali glass substrate, etc. As described above, the display device100may include the display area10including the sub-pixel areas30and the peripheral area20surrounding the display area10. Since the display device100includes the display area10and the peripheral area20, the lower substrate110may also be divided into the display area10and the peripheral area20.

In an exemplary embodiment of the present invention, the lower substrate110may be formed of a transparent resin substrate having flexibility. Examples of the transparent resin substrate that may be used as the lower substrate110include a polyimide substrate. In this case, the polyimide substrate may have a laminated structure including a first polyimide layer, a barrier film layer, a second polyimide layer, etc.

A buffer layer may be disposed in the display area10and on the lower substrate110. The buffer layer may be disposed over the lower substrate110. The buffer layer may prevent metal atoms and/or impurities from diffusing from the lower substrate110to the semiconductor element and the sub-pixel structure, and may control a heat transfer rate during a crystallization process for forming the active layer to obtain a substantially uniform active layer. In addition, when a surface of the lower substrate110is not uniform, the buffer layer may serve to increase flatness of the surface of the lower substrate110. Depending on a type of the lower substrate110, at least two buffer layers may be provided on the lower substrate110, or the buffer layer may not be provided. However, the present invention is not limited thereto; for example, one buffer layer may be provided on the lower substrate110. For example, the buffer layer may include an organic material or an inorganic material.

In addition, a metal layer may be disposed between the lower substrate110and the buffer layer. In an exemplary embodiment of the present invention, when the lower substrate110includes a polyimide substrate, the metal layer may be disposed between the first polyimide layer and the barrier film layer or between the barrier film layer and the second polyimide layer. The metal layer may function as, for example, a gate signal line, a data signal line, a high power supply voltage line, a light emission signal line, and an initialization signal line. In addition, the metal layer may function as a back gate of each of the first to third semiconductor elements250_1,250_2, and250_3. The metal layer may include, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

The first to third active layers130_1,130_2, and130_3may be spaced apart from each other in the display area10on the lower substrate110. For example, each of the first to third active layers130_1,130_2, and130_3may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or poly silicon semiconductor), an organic semiconductor, or the like, and may include a source region and a drain region.

The gate insulating layer150may be disposed on the first to third active layers130_1,130_2, and130_3. The gate insulating layer150may cover the first to third active layers130_1,130_2, and130_3in the display area10on the lower substrate110, and may be disposed over the lower substrate110. In an exemplary embodiment of the present invention, the gate insulating layer150may be disposed in the peripheral area20and on the lower substrate110.

For example, the gate insulating layer150may sufficiently cover the first to third active layers130_1,130_2, and130_3on the lower substrate110, and may have a substantially flat top surface without creating a step around the first to third active layers130_1,130_2, and130_3. In an exemplary embodiment of the present invention, the gate insulating layer150may be disposed along a profile of the first to third active layers130_1,130_2, and130_3with a substantially uniform thickness to cover the first to third active layers130_1,130_2, and130_3on the lower substrate110. The gate insulating layer150may include, for example, a silicon compound, metal oxide, etc. For example, the gate insulating layer150may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. In an exemplary embodiment of the present invention, the gate insulating layer150may be a multilayer structure including a plurality of insulating layers or may be a single layer structure. For example, the insulating layers may have mutually different thicknesses or may include mutually different materials.

The first to third gate electrodes170_1,170_2, and170_3may be spaced apart from each other on the gate insulating layer150. For example, the first gate electrode170_1may be disposed at a portion of the gate insulating layer150under which the first active layer130_1is located, the second gate electrode170_2may be disposed at a portion of the gate insulating layer150under which the second active layer130_2is located, and the third gate electrode170_3may be disposed at a portion of the gate insulating layer150under which the third active layer130_3is located. Each of the first to third gate electrodes170_1,170_2, and170_3may include, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. For example, each of the first to third gate electrodes170_1,170_2, and170_3may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an aluminum-containing alloy, aluminum nitride (AlNx), a silver-containing alloy, tungsten nitride (WNx), a copper-containing alloy, a molybdenum-containing alloy, titanium nitride (TiNx), chromium nitride (CrNx), tantalum nitride (TaNx), strontium ruthenium oxide (SrRuxOy), zinc oxide (ZnOx), indium tin oxide (ITO), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In an exemplary embodiment of the present invention, each of the first to third gate electrodes170_1,170_2, and170_3may be a multilayer structure including a plurality of metal layers or may be a single layer structure. For example, the metal layers may have mutually different thicknesses or may include mutually different materials.

The insulating interlayer190may be disposed on the first to third gate electrodes170_1,170_2, and170_3. The insulating interlayer190may cover the first to third gate electrodes170_1,170_2, and170_3disposed on the gate insulating layer150in the display area10, and may be disposed over the gate insulating layer150. In an exemplary embodiment of the present invention, the insulating interlayer190may be disposed in the peripheral area20and on the lower substrate110.

For example, the insulating interlayer190may sufficiently cover the first to third gate electrodes170_1,170_2, and170_3disposed on the gate insulating layer150, and may have a substantially flat top surface without creating a step around the first to third gate electrodes170_1,170_2, and170_3. In an exemplary embodiment of the present invention, the insulating interlayer190may be disposed along a profile of the first to third gate electrodes170_1,170_2, and170_3with a substantially uniform thickness to cover the first to third gate electrodes170_1,170_2, and170_3on the gate insulating layer150. The insulating interlayer190may include, for example, a silicon compound, metal oxide, etc. In an exemplary embodiment of the present invention, the insulating interlayer190may be a multilayer structure including a plurality of insulating layers or may be a single layer structure. For example, the insulating layers may have mutually different thicknesses or may include mutually different materials.

The first source electrode210_1, the first drain electrode230_1, the second source electrode210_2, the second drain electrode230_2, and the third source electrode210_3, and the third drain electrode230_3may be spaced apart from each other in the display area10and on the insulating interlayer190. For example, the first source electrode210_1may be connected to the source region of the first active layer130_1through a contact hole formed by removing first portions of the gate insulating layer150and the insulating interlayer190, and the first drain electrode230_1may be connected to the drain region of the first active layer130_1through a contact hole formed by removing second portions of the gate insulating layer150and the insulating interlayer190. In addition, the second source electrode210_2may be connected to the source region of the second active layer130_2through a contact hole formed by removing third portions of the gate insulating layer150and the insulating interlayer190, and the second drain electrode230_2may be connected to the drain region of the second active layer130_2through a contact hole formed by removing fourth portions of the gate insulating layer150and the insulating interlayer190. Furthermore, the third source electrode210_3may be connected to the source region of the third active layer130_3through a contact hole formed by removing fifth portions of the gate insulating layer150and the insulating interlayer190, and the third drain electrode230_3may be connected to the drain region of the third active layer130_3through a contact hole formed by removing sixth portions of the gate insulating layer150and the insulating interlayer190. Each of the first to third source electrodes210_1,210_2, and210_3and the first to third drain electrodes230_1,230_2, and230_3may include, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an exemplary embodiment of the present invention, each of the first to third source electrodes210_1,210_2, and210_3and the first to third drain electrodes230_1,230_2, and230_3may be a multilayer structure including a plurality of metal layers or may be a single layer structure. For example, the metal layers may have mutually different thicknesses or may include mutually different materials.

Accordingly, the first semiconductor element250_1including the first active layer130_1, the first gate electrode170_1, the first source electrode210_1, and the first drain electrode230_1may be provided. In addition, the second semiconductor element250_2including the second active layer130_2, the second gate electrode170_2, the second source electrode210_2, and the second drain electrode230_2may be provided. Further, the third semiconductor element250_3including the third active layer130_3, the third gate electrode170_3, the third source electrode210_3, and the third drain electrode230_3may be provided.

Although the display device100has been described as including three transistors (e.g. the first to third semiconductor elements250_1,250_2, and250_3), the configuration of the present invention is not limited thereto. For example, the display device100may include a plurality of transistors and a plurality of capacitors.

In addition, although each of the first to third semiconductor elements250_1,250_2, and250_3has been described as having a top gate structure, the configuration of the present invention is not limited thereto. For example, each of the first to third semiconductor elements250_1,250_2, and250_3may have a bottom gate structure and/or a double gate structure.

Furthermore, although each of the first to third semiconductor elements250_1,250_2, and250_3has been described as not including the gate insulating layer150and the insulating interlayer190, the present invention is limited thereto. For example, each of the first to third semiconductor elements250_1,250_2, and250_3may include the gate insulating layer150and the insulating interlayer190.

The planarization layer270may be disposed in the display area10and on the insulating interlayer190and the first to third semiconductor elements250_1,250_2, and250_3, and may not be disposed in the peripheral area20. For example, the planarization layer270may have a relatively thick thickness to sufficiently cover the first to third source electrodes210_1,210_2, and210_3and the first to third drain electrodes230_1,230_2, and230_3disposed on the insulating interlayer190. In this case, the planarization layer270may have a substantially flat top surface. To implement such a flat top surface of the planarization layer270, a platinization process may be additionally performed on the planarization layer270. The planarization layer270may include, for example, an organic material, an inorganic material, or the like. In an exemplary embodiment of the present invention, the planarization layer270may include an organic material.

The first to third lower electrodes290_1,290_2, and290_3may be spaced apart from each other in the display area10and on the planarization layer270. For example, the first lower electrode290_1may be disposed on a first portion of the planarization layer270. In addition, the second lower electrode290_2may be disposed on a second portion of the planarization layer270, and the third lower electrode290_3may be disposed on a third portion of the planarization layer270. In this case, the third portion of the planarization layer270may be spaced apart from the first portion, and the second portion of the planarization layer270may be located between the first portion and the third portion. In other words, the first portion may overlap the first opening513a, the second portion may overlap the second opening513b, and the third portion may overlap the sub-pixel area30located in the light transmission area12.

The first to third lower electrodes290_1,290_2, and290_3may be respectively connected to the first to third drain electrodes230_1,230_2, and230_3by passing through the planarization layer270, respectively. In other words, the first to third lower electrodes290_1,290_2, and290_3may be electrically connected to the first to third semiconductor elements250_1,250_2, and250_3, respectively. Each of the first to third lower electrodes290_1,290_2, and290_3may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In an exemplary embodiment of the present invention, each of the first to third lower electrodes290_1,290_2, and290_3may have a multilayer structure including a plurality of metal layers or may be a single layer structure. For example, the metal layers may have mutually different thicknesses or may include mutually different materials.

The pixel defining layer310may be disposed in the display area10and on a portion of each of the first to third lower electrodes290_1,290_2, and290_3and the planarization layer270, and may not be disposed in the peripheral area20. The pixel defining layer310may cover both sides (e.g., an outer peripheral portion) of each of the first to third lower electrodes290_1,290_2, and290_3, and may allow a portion of a top surface of each of the first to third lower electrodes290_1,290_2, and290_3to be exposed. The pixel defining layer310may be formed of an organic material or an inorganic material. In an exemplary embodiment of the present invention, the pixel defining layer310may include an organic material. For example, the pixel defining layer310may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, an epoxy-based resin, etc.

The light emitting layer330may be disposed in the display area10and on the pixel defining layer310and the top surface of each of the first to third lower electrodes290_1,290_2, and290_3exposed by the pixel defining layer310. In other words, the light emitting layer330may be continuously arranged in the display area10and on the lower substrate110, and may be integrally formed in the display area10. In an exemplary embodiment of the present invention, the light emitting layer330may be formed by using a light emitting material for emitting blue light. In addition, the light emitting layer330may be formed by laminating a plurality of light emitting materials for emitting different color lights such as red light, green light, and blue light to emit white light as a whole.

The upper electrode340may be disposed in the display area10and on the pixel defining layer310and the light emitting layer330. The upper electrode340may include, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In an exemplary embodiment of the present invention, the upper electrode340may have a multilayer structure including a plurality of metal layers or may be a single layer structure. For example, the metal layers may have mutually different thicknesses or may include mutually different materials.

Accordingly, the first sub-pixel structure including the first lower electrode290_1, the light emitting layer330, and the upper electrode340may be provided. In addition, the second sub-pixel structure including the second lower electrode290_2, the light emitting layer330, and the upper electrode340may be provided, and the third sub-pixel structure including the third lower electrode290_3, the light emitting layer330, and the upper electrode340may be provided.

The first thin film encapsulation layer451may be disposed on the upper electrode340. The first thin film encapsulation layer451may be disposed along a profile of the upper electrode340with a substantially uniform thickness to cover the upper electrode340. In an exemplary embodiment of the present invention, the first thin film encapsulation layer451may be disposed in the peripheral area20and on the lower substrate110. The first thin film encapsulation layer451may prevent the first to third sub-pixel structures from being deteriorated due to penetration of moisture, oxygen, or the like. In addition, the first thin film encapsulation layer451may also function to protect the first to third sub-pixel structures from an external impact. The first thin film encapsulation layer451may include inorganic materials having flexibility.

The second thin film encapsulation layer452may be disposed on the first thin film encapsulation layer451. The second thin film encapsulation layer452may increase flatness of the display device100and protect the first to third sub-pixel structures. The second thin film encapsulation layer452may include organic materials having flexibility.

The third thin film encapsulation layer453may be disposed on the second thin film encapsulation layer452. The third thin film encapsulation layer453may be disposed along a profile of the second thin film encapsulation layer452with a substantially uniform thickness to cover the second thin film encapsulation layer452. In an exemplary embodiment of the present invention, the third thin film encapsulation layer453may be disposed in the peripheral area20and on the lower substrate110. The third thin film encapsulation layer453may prevent the first to third sub-pixel structures from being deteriorated due to the penetration of moisture, oxygen, or the like together with the first thin film encapsulation layer451. In addition, the third thin film encapsulation layer453may also function to protect the first to third sub-pixel structures from an external impact together with the first thin film encapsulation layer451and the second thin film encapsulation layer452. The third thin film encapsulation layer453may include inorganic materials having flexibility.

Accordingly, the thin film encapsulation structure450including the first thin film encapsulation layer451, the second thin film encapsulation layer452, and the third thin film encapsulation layer453may be disposed between the lower light blocking layer430and the upper electrode340. In an exemplary embodiment of the present invention, the thin film encapsulation structure450may have a five-layer structure formed by laminating first to fifth thin film encapsulation layers or a seven-layer structure formed by laminating first to seventh thin film encapsulation layers.

The upper substrate410may be disposed on the thin film encapsulation structure450. The upper substrate410may oppose (or, e.g., face) the lower substrate110. The upper substrate410and the lower substrate110may include substantially the same material. For example, the upper substrate410may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, etc.

The first color filter513may be disposed in the display area10and on the upper substrate410. For example, the first color filter513may be disposed on a bottom surface of the upper substrate410. As described above, the first color filter513may have first openings513aand second openings513bin the display area10. In an exemplary embodiment of the present invention, the first color filter513may transmit blue light, and may be a color filter having a blue color.

The upper light blocking layer420may be disposed on a bottom surface of the first color filter513. In other words, the upper light blocking layer420may be disposed between the first color filter513and the lower light blocking layer430. The upper light blocking layer420may include a plurality of openings. For example, the upper light blocking layer420may have a plate shape including a plurality of openings. The openings may correspond to the sub-pixel areas30, respectively. In addition, the openings of the upper light blocking layer420located in the opening area11of the first color filter513may overlap the first openings513aand the second openings513b, and the openings of the upper light blocking layer420located in the light transmission area12of the first color filter513may overlap the first color filter513serving as a color filter.

The upper light blocking layer420may block or absorb light incident from an outside. The upper light blocking layer420may include an organic material such as a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, or an epoxy-based resin. In addition, the upper light blocking layer420may be substantially opaque. For example, the upper light blocking layer420may further include a light blocking material to absorb the light. The light blocking material may include, for example, carbon black, titanium nitride oxide, titanium black, phenylene black, aniline black, cyanine black, nigrosine acid black, a black resin, and the like. In an exemplary embodiment of the present invention, the upper light blocking layer420may not be disposed on the bottom surface of the first color filter513.

The second color filter511may be disposed in the first opening513aof the first color filter513and the opening of the upper light blocking layer420that is overlapping the first opening513a. In addition, the second color filter511may be disposed on the bottom surface of the upper substrate410. In addition, a portion of the second color filter511may be disposed on a portion of a bottom surface of the upper light blocking layer420. In tan exemplary embodiment of the present invention, the second color filter511may transmit red light, and may be a color filter having a red color.

The third color filter512may be disposed in the second opening513bof the first color filter513and the opening of the upper light blocking layer420that is overlapping the second opening513b. In addition, the third color filter512may be disposed on the bottom surface of the upper substrate410. In addition, a portion of the third color filter512may be disposed on a portion of the bottom surface of the upper light blocking layer420, and may make contact with or overlap the second color filter511on the bottom surface of the upper light blocking layer420. In an exemplary embodiment of the present invention, the third color filter512may transmit green light, and may be a green color filter.

Accordingly, the color filters510including the first color filter513, the second color filter511, and the third color filter512may be provided. The color filters510may include a photosensitive resin and a color photoresist.

Although the color filters510of the present invention have been described as including a green color filter, a blue color filter, and a red color filter, the configuration of the present invention is not limited thereto. For example, the color filters510may include a yellow color filter pattern, a cyan color filter pattern, and a magenta color filter pattern.

In addition, although the red color filter, the green color filter, and the blue color filter of the present invention have been described as being sequentially arranged, the configuration of the present invention is not limited thereto. For example, the arrangement of the color filters may be changed.

The first protective insulating layer490may be disposed on the color filters510and the upper light blocking layer420. For example, the first protective insulating layer490may be disposed under the color filters510and the upper light blocking layer420. The first protective insulating layer490may cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410. For example, the first protective insulating layer490may be disposed along a profile of the color filters510and the upper light blocking layer420with a substantially uniform thickness to cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410. In an exemplary embodiment of the present invention, the first protective insulating layer490may sufficiently cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410, and may have a substantially flat top surface without creating a step around the color filters510and the upper light blocking layer420. The first protective insulating layer490may include an inorganic material or an organic material. In an exemplary embodiment of the present invention, the first protective insulating layer490may have a multilayer structure including a plurality of insulating layers or may be a single layer structure. For example, the insulating layers may have mutually different thicknesses or may include mutually different materials.

The optical filters530may be disposed on the bottom surface of the first protective insulating layer490to overlap the color filters510. The optical filters530may include a first quantum dot pattern531for converting blue light into red light, a second quantum dot pattern533for converting the blue light into green light, and a scattering pattern532for transmitting the blue light.

The first quantum dot pattern531may be disposed under the second color filter511to overlap the second color filter511, the second quantum dot pattern533may be disposed under the third color filter512to overlap the third color filter512, and the scattering pattern532may be disposed under the first color filter513to overlap the first color filter513(or the light transmission area12). In other words, the first quantum dot pattern531may be disposed on the first sub-pixel structure, the second quantum dot pattern533may be disposed on the second sub-pixel structure, and the scattering pattern532may be disposed on the third sub-pixel structure. In an exemplary embodiment of the present invention, the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532may be spaced apart from each other, and may be disposed on the same layer. The first quantum dot pattern531may include a plurality of quantum dots for absorbing the blue light and emitting the red light, the second quantum dot pattern533may include a plurality of quantum dots for absorbing the blue light and emitting the green light, and the scattering pattern532may include a scattering material for emitting the blue light as it is.

Even if the quantum dots included in the first and second quantum dot patterns531and532include the same material, an emission wavelength may vary according to a size of the quantum dot. For example, as the size of the quantum dot becomes smaller, light having a shorter wavelength may be emitted. Therefore, light within a desired visible light range may be emitted by controlling the sizes of the quantum dots included in the first and second quantum dot patterns531and532.

In an exemplary embodiment of the present invention, the quantum dots included in the first quantum dot pattern531and the second quantum dot pattern533may be formed of the same material, and the sizes of the quantum dots included in the first quantum dot pattern531may be larger than the sizes of the quantum dots included in the second quantum dot pattern533.

The scattering pattern532may include, for example, TiO, ZrO, AlO3, In2O3, ZnO, SnO2, Sb2O3, ITO, etc. However, the material of the scattering pattern532is not limited thereto, and may vary as long as the material allows the blue light to be scattered without being converted.

Although the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532of the present invention have been described as being sequentially arranged, the configuration of the present invention is not limited thereto. For example, the arrangement of the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532may be changed.

Accordingly, the optical filters530including the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532may be provided.

The second protective insulating layer495may be disposed on the optical filters530and the first protective insulating layer490. For example, the second protective insulating layer495may be disposed under the optical filters530and the first protective insulating layer490. The second protective insulating layer495may cover the optical filters530on a bottom surface of the first protective insulating layer490. In an exemplary embodiment of the present invention, the second protective insulating layer495may make contact with the first protective insulating layer490at a space between the optical filters530. For example, the second protective insulating layer495may be disposed along a profile of the optical filters530with a substantially uniform thickness to cover the optical filters530on the bottom surface of the first protective insulating layer490. In an exemplary embodiment of the present invention, the second protective insulating layer495may cover the optical filters530on the bottom surface of the first protective insulating layer490, and may have a substantially flat top surface without creating a step around the optical filters530. The second protective insulating layer495may include an inorganic material or an organic material. In an exemplary embodiment of the present invention, the second protective insulating layer495may have a multilayer structure including a plurality of insulating layers or may be a single layer structure. For example, the insulating layers may have mutually different thicknesses or may include mutually different materials.

The lower light blocking layer430may be disposed on the second protective insulating layer495. For example, the lower light blocking layer430may be disposed on a bottom surface of the second protective insulating layer495. The lower light blocking layer430may be disposed at the space formed between the optical filters530on the bottom surface of the second protective insulating layer495. The lower light blocking layer430may include a plurality of openings. For example, the lower light blocking layer430may have a plate shape including a plurality of openings.

The openings of the lower light blocking layer430may correspond to the openings of the upper light blocking layer420and the sub-pixel areas30, respectively. In addition, the openings of the lower light blocking layer430located in the opening area11of the first color filter513may overlap the first openings513aand the second openings513b, and the openings of the lower light blocking layer430located in the light transmission area12of the first color filter513may overlap the first color filter513functioning as a color filter. In an exemplary embodiment of the present invention, the openings of the lower light blocking layer430, the first to third lower electrodes290_1,290_2, and290_3, and the optical filters530may respectively overlap each other. For example, the openings of the lower light blocking layer430, the first to third lower electrodes290_1,290_2, and290_3, and the first quantum dot pattern531, the second quantum dot pattern533and the scattering pattern532of the optical filter530may respectively overlap each other. In addition, the lower light blocking layer430and the upper light blocking layer420may overlap the pixel defining layer310.

The lower light blocking layer430may prevent a color mixture phenomenon that may occur in adjacent optical filters530. For example, when the lower light blocking layer430is not formed, a portion of light incident on the second quantum dot pattern533may be incident on the first quantum dot pattern531, and the remaining portion of the light may be incident on the scattering pattern532. In this case, the color mixture phenomenon may occur. In an exemplary embodiment of the present invention, the lower light blocking layer430may block or absorb the light incident from the outside, and may reflect the light emitted from the light emitting layer330. The lower light blocking layer430and the upper light blocking layer420may include substantially the same material. For example, the lower light blocking layer430may include an organic material and a light blocking material.

The intermediate layer497may be disposed on the lower light blocking layer430and the second protective insulating layer495. The intermediate layer497may be disposed under the lower light blocking layer430and the second protective insulating layer495. The intermediate layer497may be disposed on the bottom surface of the second protective insulating layer495to cover the lower light blocking layer430. For example, the intermediate layer497may have a relatively thick thickness to sufficiently cover the lower light blocking layer430on the bottom surface of the second protective insulating layer495. In other words, the intermediate layer497may be disposed on the thin film encapsulation structure450. The intermediate layer497may include an organic material, an inorganic material, or the like.

The sealing member390may be disposed in the peripheral area20between the lower substrate110and the upper substrate410. For example, the sealing member390may at least partially surround the display area10. For example, the sealing member390may have a trapezoidal shape. However, the present invention is not limited thereto; for example, the sealing member390may have a rectangular shape. In addition, the sealing member390may make contact with the bottom surface of the upper substrate410and the top surface of the lower substrate110. In an exemplary embodiment of the present invention, at least one insulating layer (e.g., the gate insulating layer150, the insulating interlayer190, and the first thin film encapsulation layer451, and the third thin film encapsulation layer453, etc.) may be interposed between the bottom surface of the sealing member390and the top surface of the lower substrate110.

In an exemplary embodiment of the present invention, the sealing member390may include a non-conductive material. For example, the sealing member390may include a frit, etc. In addition, the sealing member390may further include a photocurable material. For example, the sealing member390may include a mixture of an organic material and a photocurable material, and the sealing member390may be obtained by irradiating and curing the mixture with ultraviolet (UV) light, laser light, visible light, etc. The photocurable material included in the sealing member390may include an epoxy acrylate-based resin, a polyester acrylate-based resin, a urethane acrylate-based resin, a polybutadiene acrylate-based resin, a silicone acrylate-based resin, an alkyl acrylate-based resin, etc.

For example, the laser light may be irradiated to the mixture of the organic material and the photocurable material. As the laser light is irradiated, the mixture may be changed from a solid state to a liquid state, and the mixture in the liquid state may be cured back to the solid state after a predetermined time. According to a state change of the mixture, the upper substrate410may be sealed and coupled to the lower substrate110.

Although the sealing member390has been described as having a trapezoidal shape in which the top surface has a smaller width than the bottom surface, the configuration of the present invention is not limited thereto. For example, the sealing member390may have an inverted trapezoidal shape in which the top surface has a larger width than the bottom surface, a rectangular shape, a square shape, etc.

Although the display device100of the present invention has been described as being an organic light emitting diode display device, the configuration of the present invention is not limited thereto. In an exemplary embodiment of the present invention, the display device100may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), and an electrophoretic image display device (EPD). For example, the upper substrate410on which the optical filters530, the color filters510, and the like are disposed may be used as an upper substrate of each of the LCD, the FED, the PDP, and the EPD.

FIG. 4is a sectional view taken along line II-II′ ofFIG. 2, andFIG. 5is a partially enlarged plan view showing region ‘A’ ofFIG. 1. For example, II-II′ line ofFIG. 2may cross region ‘A’ ofFIG. 1in the first direction D1. In other words,FIG. 4may correspond to a sectional view taken along line II-II′ ofFIG. 5.

Referring toFIGS. 3, 4, and 5, the display device100may further include an alignment structure400. In this case, the alignment structure400may include a first alignment pattern and a second alignment pattern. In addition, the first alignment pattern may include a reference pattern435, a first outer peripheral pattern431, a second outer peripheral pattern432, a third outer peripheral pattern433, and a fourth outer peripheral pattern434. Further, the second alignment pattern may include a first pattern311.

The alignment structure400may be disposed in the peripheral area20of the lower substrate110and the upper substrate410, and may contain the same material as a material forming the pixel defining layer310and the lower light blocking layer430. The first alignment pattern may be disposed in the peripheral area20and on the bottom surface of the upper substrate410, and the second alignment pattern may be disposed in the peripheral area20and on the top surface of the lower substrate110. In this case, the first alignment pattern may contain the same material as the lower light blocking layer430, and the second alignment pattern may include the same material as the pixel defining layer310.

The reference pattern435may be disposed in a first portion of the peripheral area20and on the bottom surface of the upper substrate410. In other words, the reference pattern435may be located at a central portion of the alignment structure400. For example, the reference pattern435may have a rectangular shape having first to fourth corners when viewed in a plan view. However, the present invention is not limited thereto. For example, the reference pattern435may have a polygonal shape.

In the plan view of the display device100, the first to fourth outer peripheral patterns431,432,433, and434may be spaced apart from the reference pattern435, and may surround the reference pattern435. In this case, each of the first to fourth outer peripheral patterns431,432,433, and434may be spaced apart from each other at equidistance. In addition, each of the first to fourth outer peripheral patterns431,432,433, and434may be spaced apart from the reference pattern435at the same interval. Furthermore, the first outer peripheral pattern431may face the second outer peripheral pattern432, and the third outer peripheral pattern433may face the fourth outer peripheral pattern434.

For example, the first outer peripheral pattern431may be spaced apart from the first corner of the reference pattern435by a first distance. For example, the first outer peripheral pattern431may have a triangular shape when viewed in a plan view, and a first side of the triangle may face the first corner. For example, the first side of the triangle facing the first corner may be oblique.

The second outer peripheral pattern432may be spaced apart from the second corner of the reference pattern435by the first distance. For example, the second outer peripheral pattern432may have a triangular shape when viewed in a plan view, and an oblique side of the triangle may face the second corner.

The third outer peripheral pattern433may be spaced apart from the third corner of the reference pattern435by the first distance. For example, the third outer peripheral pattern433may have a triangular shape when viewed in a plan view, and an oblique side of the triangle may face the third corner.

The fourth outer peripheral pattern434may be spaced apart from the fourth corner of the reference pattern435by the first distance. For example, the fourth outer peripheral pattern434may have a triangular shape when viewed in a plan view, and an oblique side of the triangle may face the fourth corner.

In the plan view of the display device100, the first pattern311may be disposed between the reference pattern435and the first to fourth outer peripheral patterns431,432,433, and434. The first pattern311may have a rectangular shape including an opening when viewed in a plan view. However, the present invention is not limited thereto; for example, the first pattern311may have a circular shape or a polygonal shape. For example, the reference pattern435may be located in the opening. The first pattern311may surround the reference pattern435, and may not overlap the reference pattern435and the first to fourth outer peripheral patterns431,432,433, and434. In an exemplary embodiment of the present invention, the reference pattern435may be spaced apart from an inner side surface of the first pattern311(e.g., an outer side of the opening). For example, the reference pattern435may be equidistant from each inner side surface of the first pattern311. In addition, an outer side surface of the first pattern311may have first to fourth corners, and the first to fourth outer peripheral patterns431,432,433, and434may be spaced apart from the first to fourth corners at the same interval.

For example, the oblique side of the first outer peripheral pattern431may be spaced apart from the first corner of the outer side surface of the first pattern311by a second distance to face the first corner of the outer side surface of the first pattern311. The oblique side of the second outer peripheral pattern432may be spaced apart from the second corner of the outer side surface of the first pattern311by the second distance to face the second corner of the outer side surface of the first pattern311. The oblique side of the third outer peripheral pattern433may be spaced apart from the third corner of the outer side surface of the first pattern311by the second distance to face the third corner of the outer side surface of the first pattern311. The oblique side of the fourth outer peripheral pattern434may be spaced apart from the fourth corner of the outer side surface of the first pattern311by the second distance to face the fourth corner of the outer side surface of the first pattern311.

In an exemplary embodiment of the present invention, an imaginary straight line may pass through the first corner of the reference pattern435, the first corner of the outer side surface of the first pattern311, a corner facing the oblique side of the first outer peripheral pattern431, the second corner of the reference pattern435, the second corner of the outer side surface of the first pattern311, and a corner facing the oblique side of the second outer peripheral pattern432. In addition, an imaginary straight line may pass through the third corner of the reference pattern435, the third corner of the outer side surface of the first pattern311, a corner facing the oblique side of the third outer peripheral pattern433, the fourth corner of the reference pattern435, the fourth corner of the outer side surface of the first pattern311, and a corner facing the oblique side of the fourth outer peripheral pattern434.

Accordingly, the alignment structure400including the reference pattern435, the first to fourth outer peripheral patterns431,432,433, and434, and the first pattern311may be provided.

For example, in a process of bonding an upper substrate to a lower substrate through a sealing member during a process of manufacturing a conventional display device, a lower light blocking layer and a pixel defining layer has to be accurately aligned (or, e.g., arranged to overlap) and bonded to prevent image quality dispersion due to process variation. The conventional display device may include a first alignment pattern and a second alignment pattern. The first alignment pattern may be disposed on the bottom surface of the upper substrate, and the second alignment pattern may be disposed on the top surface of the lower substrate. The first alignment pattern may contain the same material as an upper light blocking layer, and the second alignment pattern may contain the same material as the metal layer disposed between the lower substrate and a buffer layer. In other words, the conventional display device uses the upper light blocking layer, which may be a black matrix formed on the upper substrate, as the first alignment pattern, and uses the metal layer, which is a metal formed on the lower substrate, as the second alignment pattern. When the alignment patterns are formed by using the upper light blocking layer and the metal layer, and the upper substrate and the lower substrate are bonded to each other by using the alignment patterns, the lower light blocking layer and the pixel defining layer may not be accurately aligned due to the process variation. Thus, a dispersion angle of light emitted through the color filters of the conventional display device may be slightly changed, and the image quality of the conventional display device may be reduced.

The display device100according to an exemplary embodiment of the present invention may include a first alignment pattern containing the same material as the lower light blocking layer430and a second alignment pattern containing the same material as the pixel defining layer310. In other words, the alignment structure400may be formed by using the lower light blocking layer430and the pixel defining layer310. When the upper substrate410and the lower substrate110are bonded to each other by using the alignment structure400, even if process variation occurs, the lower light blocking layer430and the pixel defining layer310may be aligned in a relatively accurate manner. Accordingly, a defective rate of the display device100may be reduced.

FIGS. 6 and 7are views showing a display device according to an exemplary embodiment of the present invention. A display device500illustrated inFIGS. 6 and 7may have a configuration substantially identical or similar to the configuration of the display device100described with reference toFIGS. 1 to 5except for an alignment structure401. InFIGS. 6 and 7, redundant descriptions of components substantially identical or similar to the components described with reference toFIGS. 1 to 5may be omitted. For example,FIG. 6may correspond to a sectional view of the display device500taken along line11-Ir ofFIG. 2, andFIG. 7may correspond to a partially enlarged plan view of the display device500in which region ‘A’ ofFIG. 1is enlarged.

Referring toFIGS. 3, 6, and 7, the display device500may include a lower substrate110, a first semiconductor element250_1, a second semiconductor element250_2, a third semiconductor element250_3, a gate insulating layer150, an insulating interlayer190, a planarization layer270, a first lower electrode290_1, a second lower electrode290_2, a third lower electrode290_3, a light emitting layer330, an upper electrode340, a thin film encapsulation structure450, a first protective insulating layer490, a second protective insulating layer495, a plurality of optical filters530, an intermediate layer497, a plurality of color filters510, an upper light blocking layer420, a lower light blocking layer430, a sealing member390, an upper substrate410, alignment structure401, etc. In this case, the alignment structure401may include a first alignment pattern and a second alignment pattern. In addition, the first alignment pattern may include a reference pattern435, a first outer peripheral pattern431, a second outer peripheral pattern432, a third outer peripheral pattern433, and a fourth outer peripheral pattern434. Further, the second alignment pattern may include a first pattern311and a second pattern171.

The alignment structure401may be disposed in the peripheral area20of the lower substrate110and the upper substrate410, and may contain the same material as a material forming the pixel defining layer310and the lower light blocking layer430, and a metal material. The first alignment pattern may be disposed in the peripheral area20on the bottom surface of the upper substrate410, and the second alignment pattern may be disposed in the peripheral area20on the top surface of the lower substrate110. In this case, the first alignment pattern may contain the same material as the lower light blocking layer430. In addition, the second alignment pattern may include the same material as the pixel defining layer310, the metal layer disposed between the lower substrate110and the buffer layer, and the same material as one of the first to third gate electrodes170_1,170_2, and170_3, the first to third source electrodes210_1,210_2, and210_3, the first to third drain electrodes230_1,230_2, and230_3, and/or the first to third lower electrodes290_1,290_2, and290_3.

As shown inFIG. 6, the second pattern171may be disposed between the first pattern311and the lower substrate110. As shown inFIG. 7, the second pattern171may overlap the reference pattern435, the first to fourth outer peripheral patterns431,432,433, and434, and the first pattern311.

In the plan view of the display device500, the second pattern171may have a rectangular shape when viewed in a plan view, and may extend beyond the first to fourth outer peripheral patterns431,432,433, and434. For example, the second pattern171may extend beyond the outer peripheries of the first to fourth outer peripheral patterns431,432,433, and434.

Accordingly, the alignment structure401including the reference pattern435, the first to fourth outer peripheral patterns431,432,433, and434, the first pattern311, and the second pattern171may be provided.

In the process of bonding the upper substrate410to the lower substrate110through the sealing member390, the bonding process may proceed while checking the alignment structure401through a camera. When the upper substrate410and the lower substrate110are bonded to each other by using the alignment structure401, the camera may recognize the alignment structure401in a relatively easy manner due to the second pattern171.

Since the display device500according to an exemplary embodiment of the present invention includes the alignment structure401including the reference pattern435, the first to fourth outer peripheral patterns431,432,433, and434, the first pattern311, and the second pattern171, a recognition rate of the camera may be increased in the bonding process.

FIGS. 8 and 9are views showing a display device according to an exemplary embodiment of the present invention. A display device600illustrated inFIGS. 6 and 7may have a configuration substantially identical or similar to the configuration of the display device100described with reference toFIGS. 1 to 5except for an alignment structure402. InFIGS. 8 and 9, redundant descriptions of components substantially identical or similar to the components described with reference toFIGS. 1 to 5may be omitted. For example,FIG. 8may correspond to a sectional view of the display device600taken along line ofFIG. 2, andFIG. 9may correspond to a partially enlarged plan view of the display device600in which region ‘A’ ofFIG. 1is enlarged.

Referring toFIGS. 3, 8, and 9, the display device600may include a lower substrate110, a first semiconductor element250_1, a second semiconductor element250_2, a third semiconductor element250_3, a gate insulating layer150, an insulating interlayer190, a planarization layer270, a first lower electrode290_1, a second lower electrode290_2, a third lower electrode290_3, a light emitting layer330, an upper electrode340, a thin film encapsulation structure450, a first protective insulating layer490, a second protective insulating layer495, a plurality of optical filters530, an intermediate layer497, a plurality of color filters510, an upper light blocking layer420, a lower light blocking layer430, a sealing member390, an upper substrate410, alignment structure402, etc. In this case, the alignment structure402may include a first alignment pattern and a second alignment pattern. In addition, the first alignment pattern may include a reference pattern435, a first outer peripheral pattern431, a second outer peripheral pattern432, a third outer peripheral pattern433, and a fourth outer peripheral pattern434. The second alignment pattern may include a first pattern311.

When compared with the first alignment pattern and the second alignment pattern of the alignment structure400inFIGS. 4 and 5, the first alignment pattern of the alignment structure402inFIGS. 8 and 9may be the same as the first alignment pattern of the alignment structure400, and a shape of the first pattern311of the second alignment pattern of the alignment structure402may be different from the shape of the first pattern311of the second alignment pattern of the alignment structure400. For example, the first pattern311of the alignment structure400may have a smaller width in the first direction D1than that of the first pattern311of the alignment structure402. In addition, the first pattern311of the alignment structure402may overlap the first to fourth outer peripheral patterns431-434and the reference pattern435. Further, the first pattern311of the alignment structure402may include an opening surrounding the reference pattern435.

FIGS. 10 and 11are views showing a display device according to an exemplary embodiment of the present invention. A display device700illustrated inFIGS. 10 and 11may have a configuration substantially identical or similar to the configuration of the display device500described with reference toFIGS. 6 and 7except for an alignment structure403. InFIGS. 10 and 11, redundant descriptions of components substantially identical or similar to the components described with reference toFIGS. 6 and 7may be omitted. For example,FIG. 10may correspond to a sectional view of the display device700taken along line II-II′ ofFIG. 2, andFIG. 11may correspond to a partially enlarged plan view of the display device700in which region ‘A’ ofFIG. 1is enlarged.

Referring toFIGS. 3, 10, and 11, the display device700may include a lower substrate110, a first semiconductor element250_1, a second semiconductor element250_2, a third semiconductor element250_3, a gate insulating layer150, an insulating interlayer190, a planarization layer270, a first lower electrode290_1, a second lower electrode290_2, a third lower electrode290_3, a light emitting layer330, an upper electrode340, a thin film encapsulation structure450, a first protective insulating layer490, a second protective insulating layer495, a plurality of optical filters530, an intermediate layer497, a plurality of color filters510, an upper light blocking layer420, a lower light blocking layer430, a sealing member390, an upper substrate410, alignment structure403, etc. In this case, the alignment structure403may include a first alignment pattern and a second alignment pattern. In addition, the first alignment pattern may include a reference pattern435, a first outer peripheral pattern431, a second outer peripheral pattern432, a third outer peripheral pattern433, and a fourth outer peripheral pattern434. The second alignment pattern may include a first pattern311and a second pattern171.

When compared with the first alignment pattern and the second alignment pattern of the alignment structure401inFIGS. 6 and 7, the first alignment pattern of the alignment structure403inFIGS. 10 and 11may be the same as the first alignment pattern of the alignment structure401, and a shape of the first pattern311of the second alignment pattern of the alignment structure403may be different from the shape of the first pattern311of the second alignment pattern of the alignment structure401. For example, the first pattern311of the alignment structure401may have a smaller width in the first direction D1than that of the first pattern311of the alignment structure403. In addition, the first pattern311of the alignment structure403may overlap the first to fourth outer peripheral patterns431-434and the reference pattern435while disposed on the second pattern171.

FIGS. 12 to 23are sectional views showing a method of manufacturing a display device according to an exemplary embodiment of the present invention.

Referring toFIGS. 12 and 13, a lower substrate110including a transparent or opaque material may be provided. The lower substrate110may be divided into the display area10and the peripheral area20. The lower substrate110may be formed by using, for example, a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, etc.

In an exemplary embodiment of the present invention, the lower substrate110may be formed of a transparent resin substrate having flexibility. Examples of the transparent resin substrate that may be used as the lower substrate110include a polyimide substrate. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may have a configuration in which the first polyimide layer, the barrier film layer, and the second polyimide layer are sequentially stacked on a rigid glass substrate. In the method of manufacturing the display device, after an insulating layer (e.g., the buffer layer) may be formed on the second polyimide layer of the polyimide substrate, an upper structure (e.g., the semiconductor elements, the sub-pixel structures, etc.) may be formed on the insulating layer. After the upper structure is formed, the rigid glass substrate may be removed. In other words, since the polyimide substrate is thin and flexible, it may be difficult to directly form the upper structure on the polyimide substrate. In this regard, after the upper structure is formed by using the rigid glass substrate, the glass substrate is removed, so that the polyimide substrate may be used as the lower substrate110.

The buffer layer may be formed in the display area10on the lower substrate110. The buffer layer may be formed over the lower substrate110. Depending on a type of the lower substrate110, at least two buffer layers may be provided on the lower substrate110, or the buffer layer may not be provided. For example, the buffer layer may be formed by using an organic material or an inorganic material.

The metal layer may be formed between the lower substrate110and the buffer layer. In an exemplary embodiment of the present invention, when the lower substrate110includes a polyimide substrate, the metal layer may be formed between the first polyimide layer and the barrier film layer or between the barrier film layer and the second polyimide layer. The metal layer may be formed by using, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

The first to third active layers130_1,130_2, and130_3may be spaced apart from each other in the display area10on the lower substrate110. Each of the first to third active layers130_1,130_2, and130_3may be formed by using, for example, an oxide semiconductor, an inorganic semiconductor, an organic semiconductor, or the like, and may include a source region and a drain region. In other words, the first to third active layers130_1,130_2, and130_3may be simultaneously formed by using the same material.

The gate insulating layer150may be formed on the first to third active layers130_1,130_2, and130_3. The gate insulating layer150may cover the first to third active layers130_1,130_2, and130_3in the display area10on the lower substrate110, and may be formed over the lower substrate110. In an exemplary embodiment of the present invention, the gate insulating layer150may be formed in the peripheral area20and on the lower substrate110.

For example, the gate insulating layer150may sufficiently cover the first to third active layers130_1,130_2, and130_3on the lower substrate110, and may have a substantially flat top surface without creating a step around the first to third active layers130_1,130_2, and130_3. In an exemplary embodiment of the present invention, the gate insulating layer150may be formed along a profile of the first to third active layers130_1,130_2, and130_3with a substantially uniform thickness to cover the first to third active layers130_1,1302, and130_3and may be formed on the lower substrate110. The gate insulating layer150may be formed by using a silicon compound, metal oxide, etc. For example, the gate insulating layer150may include SiOx, SiOxNy, SiOxCy, SiCxNy, AlOx, AlNx, TaOx, HfOx, ZrOx, TiOx, etc.

The first to third gate electrodes170_1,170_2, and170_3may be spaced apart from each other on the gate insulating layer150. For example, the first gate electrode170_1may be formed at a portion of the gate insulating layer150under which the first active layer130_1is located, the second gate electrode170_2may be formed at a portion of the gate insulating layer150under which the second active layer130_2is located, and the third gate electrode170_3may be formed at a portion of the gate insulating layer150under which the third active layer130_3is located. Each of the first to third gate electrodes170_1,170_2, and170_3may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. For example, each of the first to third gate electrodes170_1,170_2, and170_3may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum-containing alloy, AlNx, a silver-containing alloy, WNx, a copper-containing alloy, a molybdenum-containing alloy, TiNx, CrNx, TaNx, SrRuxOy, ZnOx, ITO, SnOx, InOx, GaOx, IZO, etc. These may be used alone or in combination with each other.

As shown inFIG. 13, the second pattern171may be formed in the peripheral area20and on the lower substrate110. In an exemplary embodiment of the present invention, the second pattern171may be simultaneously formed with the first to third gate electrodes170_1,170_2, and170_3by using the same material as the first to third gate electrodes170_1,170_2, and170_3.

Referring toFIGS. 14 and 15, the insulating interlayer190may be formed on the first to third gate electrodes170_1,170_2, and170_3. The insulating interlayer190may cover the first to third gate electrodes170_1,170_2, and170_3in the display area10and on the gate insulating layer150, and may be formed over the gate insulating layer150. In an exemplary embodiment of the present invention, the insulating interlayer190may be formed in the peripheral area20and on the lower substrate110.

For example, the insulating interlayer190may sufficiently cover the first to third gate electrodes170_1,170_2, and170_3on the gate insulating layer150, and may have a substantially flat top surface without creating a step around the first to third gate electrodes170_1,170_2, and170_3. In an exemplary embodiment of the present invention, the insulating interlayer190may be formed along a profile of the first to third gate electrodes170_1,170_2, and170_3with a substantially uniform thickness to cover the first to third gate electrodes170_1,170_2, and170_3on the gate insulating layer150. The insulating interlayer190may be formed by using, for example, a silicon compound, metal oxide, etc.

The first source electrode210_1, the first drain electrode230_1, the second source electrode210_2, the second drain electrode230_2, and the third source electrode210_3, and the third drain electrode230_3may be spaced apart from each other in the display area10on the insulating interlayer190. For example, the first source electrode210_1may be connected to the source region of the first active layer130_1through a contact hole formed by removing first portions of the gate insulating layer150and the insulating interlayer190, and the first drain electrode230_1may be connected to the drain region of the first active layer130_1through a contact hole formed by removing second portions of the gate insulating layer150and the insulating interlayer190. In addition, the second source electrode210_2may be connected to the source region of the second active layer130_2through a contact hole formed by removing third portions of the gate insulating layer150and the insulating interlayer190, and the second drain electrode230_2may be connected to the drain region of the second active layer130_2through a contact hole formed by removing fourth portions of the gate insulating layer150and the insulating interlayer190. Furthermore, the third source electrode210_3may be connected to the source region of the third active layer130_3through a contact hole formed by removing fifth portions of the gate insulating layer150and the insulating interlayer190, and the third drain electrode230_3may be connected to the drain region of the third active layer130_3through a contact hole formed by removing sixth portions of the gate insulating layer150and the insulating interlayer190. Each of the first to third source electrodes210_1,210_2, and210_3and the first to third drain electrodes230_1,230_2, and230_3may be formed by using, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other words, the first to third source electrodes210_1,210_2, and210_3and the first to third drain electrodes230_1,230_2, and230_3may be simultaneously formed by using the same material.

Accordingly, the first semiconductor element250_1including the first active layer130_1, the first gate electrode170_1, the first source electrode210_1, and the first drain electrode230_1may be formed, the second semiconductor element250_2including the second active layer130_2, the second gate electrode170_2, the second source electrode210_2, and the second drain electrode230_2may be formed, and the third semiconductor element250_3including the third active layer130_3, the third gate electrode170_3, the third source electrode210_3, and the third drain electrode230_3may be formed.

The planarization layer270may be formed in the display area10and on the insulating interlayer190and the first to third semiconductor elements250_1,250_2, and250_3, and may not be formed in the peripheral area20. For example, the planarization layer270may have a relatively thick thickness to sufficiently cover the first to third source electrodes210_1,210_2, and2103and the first to third drain electrodes230_1,230_2, and230_3on the insulating interlayer190. In this case, the planarization layer270may have a substantially flat top surface. To implement such a flat top surface of the planarization layer270, a planarization process may be additionally performed on the planarization layer270. The planarization layer270may be formed by using an organic material.

The first to third lower electrodes290_1,290_2, and2903may be spaced apart from each other in the display area10on the planarization layer270. The first to third lower electrodes290_1,290_2, and290_3may be connected to the first to third drain electrodes230_1,230_2, and230_3by passing through the planarization layer270, respectively. Each of the first to third lower electrodes290_1,290_2, and290_3may be formed by using, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In other words, the first to third lower electrodes290_1,290_2, and290_3may be simultaneously formed by using the same material.

The pixel defining layer310may be formed in the display area10and on a portion of each of the first to third lower electrodes290_1,290_2, and290_3and the planarization layer270, and may not be formed in the peripheral area20. The pixel defining layer310may cover both sides of each of the first to third lower electrodes290_1,290_2, and290_3, and may allow a portion of a top surface of each of the first to third lower electrodes290_1,290_2, and290_3to be exposed. The pixel defining layer310may be formed by using an organic material.

As shown inFIG. 15, the first pattern311may be formed on the second pattern171. In an exemplary embodiment of the present invention, the first pattern311may be simultaneously formed with the pixel defining layer310by using the same material as the pixel defining layer310.

Referring toFIG. 16, the light emitting layer330may be formed in the display area10and on the top surface of each of the first to third lower electrodes290_1,290_2, and290_3exposed by the pixel defining layer310. In other words, the light emitting layer330may be continuously (or, e.g., integrally) formed in the display area10on the lower substrate110. In an exemplary embodiment of the present invention, the light emitting layer330may be formed by using a light emitting material for emitting blue light. In addition, the light emitting layer330may be formed by laminating a plurality of light emitting materials for emitting different color lights such as red light, green light, and blue light to emit white light as a whole.

The upper electrode340may be formed in the display area10and on the pixel defining layer310and the light emitting layer330. The upper electrode340may be formed by using, for example, a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

Accordingly, the first sub-pixel structure including the first lower electrode290_1, the light emitting layer330, and the upper electrode340may be formed, the second sub-pixel structure including the second lower electrode290_2, the light emitting layer330, and the upper electrode340may be formed, and the third sub-pixel structure including the third lower electrode290_3, the light emitting layer330, and the upper electrode340may be formed.

The first thin film encapsulation layer451may be formed on the upper electrode340. The first thin film encapsulation layer451may be formed along a profile of the upper electrode340with a substantially uniform thickness to cover the upper electrode340. The first thin film encapsulation layer451may be formed by using inorganic materials having flexibility.

The second thin film encapsulation layer452may be formed on the first thin film encapsulation layer451. The second thin film encapsulation layer452may include organic materials having flexibility.

The third thin film encapsulation layer453may be formed on the second thin film encapsulation layer452. The third thin film encapsulation layer453may be formed along a profile of the second thin film encapsulation layer452with a substantially uniform thickness to cover the second thin film encapsulation layer452. The third thin film encapsulation layer453may be formed by using inorganic materials having flexibility.

Accordingly, the thin film encapsulation structure450including the first thin film encapsulation layer451, the second thin film encapsulation layer452, and the third thin film encapsulation layer453may be formed.

Referring toFIG. 17, the upper substrate410may be provided. The upper substrate410and the lower substrate110may include substantially the same material. For example, the upper substrate410may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, etc.

The first color filter513may be formed in the display area10and on a bottom surface of the upper substrate410. The first color filter513may have first openings513aand second openings513bin the display area10. In an exemplary embodiment of the present invention, the first color filter513may transmit blue light, and may be a color filter having a blue color. As shown inFIG. 2, the first color filter513may include an opening area11and a light transmission area12. The first openings513aand the second openings513bmay be located in the opening area11. No opening may be formed in the light transmission area12. The sub-pixel areas30located in the light transmission area12may overlap the third sub-pixel structure, and a portion overlapping the sub-pixel areas30located in the light transmission area12may function as the first color filter513.

The upper light blocking layer420may be formed on a bottom surface of the first color filter513. The upper light blocking layer420may include a plurality of openings. For example, the upper light blocking layer420may have a plate shape including a plurality of openings. The openings of the upper light blocking layer420located in the opening area11of the first color filter513may overlap the first openings513aand the second openings513b, and the openings of the upper light blocking layer420located in the light transmission area12of the first color filter513may overlap the first color filter513serving as a color filter.

The upper light blocking layer420may block or absorb light incident from an outside. The upper light blocking layer420may be formed by using an organic material such as a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, or an epoxy-based resin. In addition, the upper light blocking layer420may be substantially opaque. For example, the upper light blocking layer420may further include a light blocking material to absorb the light. The light blocking material may include carbon black, titanium nitride oxide, titanium black, phenylene black, aniline black, cyanine black, nigrosine acid black, a black resin, and the like. In an exemplary embodiment of the present invention, the upper light blocking layer420may not be formed on the bottom surface of the first color filter513.

Referring toFIG. 18, the second color filter511may be formed in the first opening513aof the first color filter513and the opening of the upper light blocking layer420on the bottom surface of the upper substrate410. In addition, a portion of the second color filter511may be formed on a portion of a bottom surface of the upper light blocking layer420. In an exemplary embodiment of the present invention, the second color filter511may transmit red light, and may be a color filter having a red color.

The third color filter512may be formed in the second opening513bof the first color filter513and the opening of the upper light blocking layer420on the bottom surface of the upper substrate410. In addition, a portion of the third color filter512may be formed on a portion of the bottom surface of the upper light blocking layer420, and may make contact with or overlap the second color filter511on the bottom surface of the upper light blocking layer420. In an exemplary embodiment of the present invention, the third color filter512may transmit green light, and may be a green color filter.

Accordingly, the color filters510including the first color filter513, the second color filter511, and the third color filter512may be formed. The color filters510may be formed by using a photosensitive resin and a color photoresist.

Referring toFIG. 19, the first protective insulating layer490may be formed under the color filters510and the upper light blocking layer420. The first protective insulating layer490may cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410. For example, the first protective insulating layer490may be formed along a profile of the color filters510and the upper light blocking layer420with a substantially uniform thickness to cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410. In an exemplary embodiment of the present invention, the first protective insulating layer490may sufficiently cover the color filters510and the upper light blocking layer420on the bottom surface of the upper substrate410, and may have a substantially flat top surface without creating a step around the color filters510and the upper light blocking layer420. The first protective insulating layer490may be formed by using an inorganic material or an organic material.

The optical filters530may be formed on the bottom surface of the first protective insulating layer490to overlap the color filters510. The optical filters530may include a first quantum dot pattern531for converting blue light into red light, a second quantum dot pattern533for converting the blue light into green light, and a scattering pattern532for transmitting the blue light.

The first quantum dot pattern531may be formed under the second color filter511to overlap the second color filter511, the second quantum dot pattern533may be formed under the third color filter512to overlap the third color filter512, and the scattering pattern532may be formed under the first color filter513to overlap the first color filter513. In an exemplary embodiment of the present invention, the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532may be spaced apart from each other, and may be disposed on the same layer. The first quantum dot pattern531may include a plurality of quantum dots for absorbing the blue light and emitting the red light, the second quantum dot pattern533may include a plurality of quantum dots for absorbing the blue light and emitting the green light, and the scattering pattern532may include a scattering material for emitting the blue light as it is.

For example, the quantum dots included in the first quantum dot pattern531and the second quantum dot pattern533may be formed by using one of nanocrystals including a silicon-based nanocrystal, a group II-VI compound-based semiconductor nanocrystal, a group III-V compound-based semiconductor nanocrystal, a group IV-VI compound-based semiconductor nanocrystal, and mixtures thereof.

Even if the quantum dots included in the first and second quantum dot patterns531and532include the same material, an emission wavelength may vary according to a size of the quantum dot. For example, as the size of the quantum dot becomes smaller, light having a shorter wavelength may be emitted. Therefore, light within a desired visible light range may be emitted by controlling the sizes of the quantum dots included in the first and second quantum dot patterns531and532.

The scattering pattern532may be formed by using TiO, ZrO, AlO3, In2O3, ZnO, SnO2, Sb2O3, ITO, etc. However, the material of the scattering pattern532is not limited thereto, and may vary as long as the material allows the blue light to be scattered without being converted.

Accordingly, the optical filters530including the first quantum dot pattern531, the second quantum dot pattern533, and the scattering pattern532may be formed.

Referring toFIGS. 20 and 21, the second protective insulating layer495may be formed under the optical filters530and the first protective insulating layer490. The second protective insulating layer495may cover the optical filters530on a bottom surface of the first protective insulating layer490. In an exemplary embodiment of the present invention, the second protective insulating layer495may make contact with the first protective insulating layer490at a space between the optical filters530. For example, the second protective insulating layer495may be formed along a profile of the optical filters530with a substantially uniform thickness to cover the optical filters530on the bottom surface of the first protective insulating layer490. In an exemplary embodiment of the present invention, the second protective insulating layer495may sufficiently cover the optical filters530on the bottom surface of the first protective insulating layer490, and may have a substantially flat top surface without creating a step around the optical filters530. The second protective insulating layer495may be formed by using an inorganic material or an organic material.

The lower light blocking layer430may be formed on a bottom surface of the second protective insulating layer495. The lower light blocking layer430may be formed at the space between the optical filters530on the bottom surface of the second protective insulating layer495. The lower light blocking layer430may include a plurality of openings. For example, the lower light blocking layer430may have a plate shape including a plurality of openings.

The openings of the lower light blocking layer430may correspond to the openings of the upper light blocking layer420and the sub-pixel areas30, respectively. In addition, the openings of the lower light blocking layer430located in the opening area11of the first color filter513may overlap the first openings513aand the second openings513b, and the openings of the lower light blocking layer430located in the light transmission area12of the first color filter513may overlap the first color filter513functioning as a color filter.

The lower light blocking layer430may prevent a color mixture phenomenon that may occur in adjacent optical filters530. For example, when the lower light blocking layer430is not formed, a portion of light incident on the second quantum dot pattern533may be incident on the first quantum dot pattern531, and the remaining portion of the light may be incident on the scattering pattern532. In this case, the color mixture phenomenon may occur. In an exemplary embodiment of the present invention, the lower light blocking layer430may block or absorb the light incident from the outside, and may reflect the light emitted from the light emitting layer330.

The lower light blocking layer430and the upper light blocking layer420may include substantially the same material. For example, the lower light blocking layer430may be formed by using an organic material and a light blocking material.

As shown inFIG. 21, first to fourth outer peripheral patterns431,432,433, and434and a reference pattern435may be formed in the peripheral area20on the bottom surface of the upper substrate410. In an exemplary embodiment of the present invention, the lower light blocking layer430, the first to fourth outer peripheral patterns431,432,433, and434, and the reference pattern435may be simultaneously formed by using the same material.

Accordingly, the alignment structure401including the first to fourth outer peripheral patterns431,432,433,434, the reference pattern435, the first pattern311, and the second pattern171may be formed.

Referring toFIGS. 22 and 23, the intermediate layer497may be formed under the lower light blocking layer430and the second protective insulating layer495. The intermediate layer497may be formed on the bottom surface of the second protective insulating layer495to cover the lower light blocking layer430. For example, the intermediate layer497may have a relatively thick thickness to sufficiently cover the lower light blocking layer430on the bottom surface of the second protective insulating layer495. The intermediate layer497may be formed by using, for example, an organic material, an inorganic material, or the like.

The sealing member390may be disposed in the peripheral area20on the lower substrate110. The sealing member390may have, for example, a trapezoidal shape. In an exemplary embodiment of the present invention, the sealing member390may be formed in the peripheral area20and on the upper substrate410. In this case, the sealing member390may have an inverted trapezoidal shape. The sealing member390may be formed by using a non-conductive material. For example, the sealing member390may include a frit, etc. In addition, the sealing member390may further include a photocurable material. For example, the sealing member390may include a mixture of an organic material and a photocurable material. The photocurable material included in the sealing member390may include an epoxy acrylate-based resin, a polyester acrylate-based resin, a urethane acrylate-based resin, a polybutadiene acrylate-based resin, a silicone acrylate-based resin, an alkyl acrylate-based resin, etc.

After the sealing member390is formed, the bottom surface of the upper substrate410may make contact with the sealing member390by using the alignment structure401.

Next, ultraviolet light, laser light, visible light, or the like may be irradiated onto the sealing member390. For example, the laser light may be irradiated to the sealing member390. As the laser light is irradiated, the mixture may be changed from a solid state to a liquid state, and the mixture in the liquid state may be cured back to the solid state after a predetermined time. According to a state change of the mixture, the upper substrate410may be sealed and coupled to the lower substrate110.

The present invention may be applied to various electronic devices including a display device. For example, the present invention may be applied to vehicle-display device, a ship-display device, an aircraft-display device, portable communication devices, display devices for display or for information transfer, a medical-display device, etc.