Thin Film Transistor and Manufacturing Method, Memory and Manufacturing Method, and Electronic Device

A thin-film transistor (TFT) includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate.

TECHNICAL FIELD

This disclosure relates to the field of memory technologies, and in particular, to a thin-film transistor and a manufacturing method, a memory and a manufacturing method, and an electronic device.

BACKGROUND

A thin-film transistor (TFT) has advantages of a low leakage current, a low growth temperature, and a high mobility, and therefore the thin-film transistor has been widely used in various devices such as a memory.

A structure of a TFT is shown inFIG.1. The TFT10includes a semiconductor layer (or an active layer)102disposed on a substrate101, a source103and a drain104that are disposed on the semiconductor layer102and in contact with the semiconductor layer102, a gate insulation layer105disposed on the semiconductor layer102, and a gate106disposed on the gate insulation layer105.

Because the semiconductor layer102of the TFT10is spread along a plane parallel to the gate106, and the source103and the drain104are located at a same layer, a size of the TFT10is relatively large, and area utilization is low. In addition, because the source electrode103and the drain electrode104are located at the same layer, a short circuit easily occurs during routing of a signal line electrically connected to the source electrode103and a signal line electrically connected to the drain electrode104, which is not conducive to routing and increases process difficulty.

SUMMARY

Embodiments of this disclosure provide a TFT and a manufacturing method, a memory and a manufacturing method, and an electronic device, to reduce a size of the TFT, improve area utilization, and reduce routing difficulty.

To achieve the foregoing objectives, this disclosure uses the following technical solutions.

According to a first aspect, a TFT is provided. The TFT includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are electrically connected to the semiconductor layer respectively.

Compared with the conventional technology, the semiconductor layer is disposed along a plane parallel to the gate (the gate in the conventional technology is equivalent to the gate base in this embodiment of this disclosure), and the second electrode and the first electrode are disposed at a same layer. In this embodiment, the semiconductor layer is disposed along the side surface of the gate body, the first electrode is located at the bottom portion, the second electrode is located between the first electrode and the gate base, and the first electrode and the second electrode are electrically connected to the semiconductor layer respectively. Therefore, the TFT provided in this embodiment has a relatively small size on a plane parallel to the gate base. Therefore, in this embodiment, the size of the TFT is reduced, and area utilization is improved. In addition, because the second electrode and the first electrode of the TFT are located at different layers, a short circuit occurring during routing of a signal line electrically connected to the second electrode and a signal line electrically connected to the first electrode may be avoided, thereby reducing process difficulty.

In a possible implementation, the second electrode is disposed close to the gate base. This can avoid that the first electrode and the second electrode are directly conducted when the first electrode and the second electrode are manufactured.

In a possible implementation, a boundary of a projection of the gate body on the gate base is located within a boundary of the gate base. In this case, the gate body is disposed in a middle region of the gate base.

In a possible implementation, a boundary of a projection of the gate body on the gate base partially overlaps a boundary of the gate base. In this case, the gate body is disposed in an edge region of the gate base.

In a possible implementation, the gate body is of a hollow structure, and an outer boundary of a projection of the gate body on the gate base overlaps a boundary of the gate base. Because the gate body is of a hollow structure, the second dielectric layer, the semiconductor layer, the second electrode, and the first dielectric layer may be disposed in the hollow structure.

In a possible implementation, the semiconductor layer further includes an extension portion extending along a surface of the gate base. In this way, an area of the semiconductor layer may be increased, thereby increasing an electrical connection area between the semiconductor layer and the second electrode, and improving a switching rate of the TFT.

In a possible implementation, the semiconductor layer further includes an extension portion located between the gate body and the first electrode. In this way, an area of the semiconductor layer may be increased, thereby increasing an electrical connection area between the semiconductor layer and the first electrode, and improving a switching rate of the TFT.

In a possible implementation, the semiconductor layer is disposed around the entire side surface of the gate body. In this way, an area of the semiconductor layer may be increased, and a switching rate of the TFT is improved.

In a possible implementation, the semiconductor layer surrounds an entire side surface of the gate body.

In a possible implementation, the second electrode is disposed on a side of the semiconductor layer that is away from the second dielectric layer.

In a possible implementation, the second electrode is disposed between the semiconductor layer and the second dielectric layer.

In a possible implementation, a material of the second dielectric layer is a ferroelectric material, and the TFT further includes a third dielectric layer disposed between the semiconductor layer and the second dielectric layer. The gate, the second dielectric layer, and the third dielectric layer may form a composite gate structure. By using the composite gate structure, the TFT may implement performance of a negative capacitance transistor, and a gate control capability of the TFT may be improved by using the negative capacitance. When the TFT is used in a memory, performance of the memory may be improved.

In a possible implementation, the TFT further includes a first conductive layer disposed between the second dielectric layer and the third dielectric layer. A composite gate structure including the gate, the second dielectric layer, the first conductive layer, and the third dielectric layer may enable the TFT to implement performance of a negative capacitance transistor, and a gate control capability of the TFT may be improved by using the negative capacitance. When the TFT is used in a memory, performance of the memory may be improved.

In a possible implementation, the TFT further includes a fourth dielectric layer disposed between the second electrode and the semiconductor layer, and/or a fifth dielectric layer disposed between the first electrode and the semiconductor layer. The fourth dielectric layer is disposed between the second electrode and the semiconductor layer, so as to avoid a problem of diffusion of the second electrode in a contact region with the semiconductor layer, and reduce a Fermi level pinning problem of contact between the second electrode and the semiconductor layer. The fifth dielectric layer is disposed between the first electrode and the semiconductor layer, so as to avoid a problem of diffusion of the first electrode in a contact region with the semiconductor layer, and reduce a Fermi level pinning problem of contact between the first electrode and the semiconductor layer.

In a possible implementation, thicknesses of both the fourth dielectric layer and the fifth dielectric layer range from 0.1 nanometers (nm) to 2 nm. This can ensure that when a voltage is provided on the gate, the second electrode and the first electrode can be conducted through the semiconductor layer, and performance of the TFT is not affected.

In a possible implementation, the TFT further includes a modulation gate electrode disposed between the first electrode and the second electrode, the modulation gate electrode is disposed on a side of the semiconductor layer that is away from the gate body, and the modulation gate electrode is surrounded by the first dielectric layer, so that the modulation gate electrode is spaced from the first electrode, the second electrode, and the semiconductor layer. A threshold voltage of the TFT may be adjusted by using the modulation gate electrode.

In a possible implementation, the first electrode is a drain, and the second electrode is a source, or the first electrode is a source, and the second electrode is a drain.

According to a second aspect, a memory is provided. The memory includes at least one layer of storage array disposed on a substrate, where each layer of storage array includes a plurality of storage cells, write word lines, write bit lines, read word lines, and read bit lines that are distributed in an array, the storage cell includes a second TFT and a first TFT that are stacked, a gate of the second TFT is electrically connected to the write word line, and a second electrode is electrically connected to the write bit line, and a second electrode and a first electrode of the first TFT are electrically connected to the read word line and the read bit line respectively. The second TFT and the first TFT are the foregoing TFTs. A first electrode of the second TFT is close to a gate of the first TFT, and the first electrode of the second TFT is electrically connected to the gate of the first TFT. Because the second TFT and the first TFT in the memory are the foregoing TFTs, and the second TFT and the first TFT have the same technical effects as those in the foregoing embodiments, details are not described herein again.

In a possible implementation, the storage cell further includes a connection electrode disposed between the first TFT and the second TFT, and the gate of the first TFT is electrically connected to the first electrode of the second TFT by using the connection electrode.

In a possible implementation, gates of second TFTs in a plurality of storage cells that are sequentially arranged in each layer of storage array along a first direction are electrically connected to a same write word line, and second electrodes of second TFTs in a plurality of storage cells that are sequentially arranged in each layer of storage array along a second direction are electrically connected to a same write bit line, where the first direction intersects with the second direction. In each layer of storage array, the gates of the second TFTs in the plurality of storage cells that are sequentially arranged along the first direction are electrically connected to a same write word line, and the second electrodes of the second TFTs in the plurality of storage cells that are sequentially arranged along the second direction are electrically connected to a same write bit line. Therefore, in a write operation process, a first switch signal may be provided to the plurality of write word lines row by row, so that the plurality of rows of second TFTs are turned on row by row. In a case that the first switch signal is provided to a write word line of a current row, logical information is simultaneously written, by using a plurality of write bit lines, to a plurality of storage cells that are electrically connected to the write word line of the current row, so that the logical information may be written to the storage cells row by row, thereby implementing quick writing of the plurality of storage cells in the storage array.

In a possible implementation, second electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the first direction are electrically connected to a same read bit line, and first electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the second direction are electrically connected to a same read word line, second electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the first direction are electrically connected to a same read word line, and first electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the second direction are electrically connected to a same read bit line, second electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the second direction are electrically connected to a same read bit line, and first electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the first direction are electrically connected to a same read word line, or second electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the second direction are electrically connected to a same read word line, and first electrodes of first TFTs in the plurality of storage cells that are sequentially arranged in each layer of storage array along the first direction are electrically connected to a same read bit line, where the first direction intersects with the second direction. In a read operation process, a third level signal may be provided to the plurality of read word lines row by row. In a case that the third level signal is provided to a read word line of a current row, a current on each read bit line is detected. In this way, logical information stored in a plurality of storage cells that are electrically connected to the read word line of the current row can be read simultaneously, so that the logical information stored in the storage cells can be read row by row, thereby implementing quick reading of the plurality of storage cells in the storage array.

In a possible implementation, the first direction and the second direction are orthogonal.

In a possible implementation, the first TFT further includes a first modulation gate electrode disposed between the first electrode and the second electrode, the first modulation gate electrode is disposed on a side of the semiconductor layer that is away from the gate body, and the first modulation gate electrode is surrounded by a first dielectric layer of the first TFT, so as to be spaced from the second electrode, the first electrode, and the semiconductor layer, and first modulation gate electrodes of a plurality of first TFTs located at a same layer are electrically connected together, and/or the second TFT further includes a second modulation gate electrode disposed between the first electrode and the second electrode, the second modulation gate electrode is disposed on a side of the semiconductor layer that is away from the gate body, and the second modulation gate electrode is surrounded by a first dielectric layer of the second TFT, so as to be spaced from the second electrode, the first electrode, and the semiconductor layer, and second modulation gate electrodes of a plurality of second TFTs located at a same layer are electrically connected together. The first TFT includes the first modulation gate electrode, so that a threshold voltage of the first TFT may be adjusted by using the first modulation gate electrode. In addition, first modulation gate electrodes of a plurality of first TFTs are electrically connected together, so that joint modulation of the plurality of first TFTs may be implemented. The second TFT includes the second modulation gate electrode, so that a threshold voltage of the second TFT may be adjusted by using the second modulation gate electrode. In addition, second modulation gate electrodes of a plurality of second TFTs are electrically connected together, so that joint modulation of the plurality of second TFTs may be implemented. Based on this, storage performance of the memory can be adjusted more flexibly.

In a possible implementation, the memory further includes an integrated circuit, and the storage array is disposed on the integrated circuit. In this case, the memory is an on-chip memory.

In a possible implementation, the storage cell is electrically connected to the integrated circuit. In this way, the storage cell may be controlled by using the integrated circuit.

According to a third aspect, an electronic device is provided. The electronic device includes a circuit board and a memory electrically connected to the circuit board, and the memory is the foregoing memory. The electronic device has a same technical effect as that in the foregoing embodiments, and details are not described herein again.

According to a fourth aspect, a TFT manufacturing method is provided. The TFT manufacturing method includes forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, where the first electrode, the first dielectric layer, and the second electrode are sequentially stacked, the first dielectric layer separates the first electrode from the second electrode, the semiconductor layer is formed on a side surface of the first dielectric layer, and the second electrode and the first electrode are both electrically connected to the semiconductor layer, and sequentially forming a second dielectric layer and a gate, where the gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion, and the second dielectric layer separates the gate from the semiconductor layer, the first electrode, and the second electrode. The TFT manufacturing method has a same technical effect as that in the foregoing embodiments, and details are not described herein again.

In a possible implementation, the first electrode is formed as a drain, and the second electrode is formed as a source, or the first electrode is formed as a source, and the second electrode is formed as a drain.

In a possible implementation, forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes sequentially forming a first conductive thin film, a first dielectric thin film, and a second conductive thin film that are stacked on the substrate, patterning the first conductive thin film, the first dielectric thin film, and the second conductive thin film to form the first electrode, the first dielectric layer, and the second electrode that are stacked sequentially, and forming the semiconductor layer on the side surface of the first dielectric layer and a side surface of the second electrode.

In a possible implementation, forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes first, forming a first conductive thin film and a third dielectric thin film that are sequentially stacked on the substrate, then, forming a modulation gate electrode on the third dielectric thin film, then, forming a fourth dielectric thin film, where the fourth dielectric thin film surrounds the modulation gate electrode, then, forming a second conductive thin film on the fourth dielectric thin film, next, patterning the first conductive thin film to form the first electrode, patterning the fourth dielectric thin film and the third dielectric thin film to form the first dielectric layer, and patterning the second conductive thin film to form the second electrode, and forming the semiconductor layer on the side surface of the first dielectric layer and a side surface of the second electrode. A threshold voltage of the TFT may be adjusted by using the modulation gate electrode.

In a possible implementation, forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes forming a first conductive thin film and a first dielectric thin film that are sequentially stacked on the substrate, then, patterning the first conductive thin film and the first dielectric thin film to form the first electrode and the first dielectric layer that are sequentially stacked, forming the semiconductor layer on the side surface of the first dielectric layer, and forming the second electrode on the first dielectric layer.

In a possible implementation, a material of the second dielectric layer is a ferroelectric material, and after the semiconductor layer is formed and before the second dielectric layer is formed, the manufacturing method further includes forming a third dielectric layer, where the third dielectric layer is formed on the side surface of the first dielectric layer. The third dielectric layer has a same technical effect as that in the foregoing embodiments, and details are not described herein again.

In a possible implementation, after the third dielectric layer is formed and before the second dielectric layer is formed, the manufacturing method further includes forming a first conductive layer, where the first conductive layer is formed on the side surface of the first dielectric layer. The first conductive layer has a same technical effect as that in the foregoing embodiments, and details are not described herein again.

In a possible implementation, after the first electrode is formed and before the semiconductor layer is formed, the manufacturing method further includes forming a fifth dielectric layer, where the fifth dielectric layer is in contact with the first electrode and the semiconductor layer respectively. In this way, a problem of diffusion of the first electrode in a contact region with the semiconductor layer may be avoided, and a Fermi level pinning problem of contact between the first electrode and the semiconductor layer may be reduced.

In a possible implementation, after the second electrode is formed and before the semiconductor layer is formed, or after the semiconductor layer is formed and before the second electrode is formed, the manufacturing method further includes forming a fourth dielectric layer, where the fourth dielectric layer is in contact with the second electrode and the semiconductor layer respectively. In this way, a problem of diffusion of the second electrode in a contact region with the semiconductor layer may be avoided, and a Fermi level pinning problem of contact between the second electrode and the semiconductor layer may be reduced.

According to a fifth aspect, a memory manufacturing method is provided. The memory manufacturing method includes forming at least one layer of storage array on a substrate. A method for manufacturing any layer of storage array includes forming, on the substrate, a plurality of first signal lines arranged in parallel, forming, on the plurality of first signal lines, a plurality of first TFTs distributed in an array and a plurality of second signal lines arranged in parallel, where the first TFT is manufactured by using the foregoing TFT manufacturing method, a first electrode of the first TFT is electrically connected to the first signal line, and a second electrode of the first TFT is electrically connected to the second signal line, and the first signal line is one of a read bit line and a read word line, and the second signal line is the other of the read bit line and the read word line, forming, on the first TFTs, a plurality of second TFTs distributed in an array and a plurality of write bit lines arranged in parallel, where a second electrode of the second TFT is electrically connected to the write bit line, the second TFT is manufactured by using the foregoing TFT manufacturing method, one second TFT corresponds to one first TFT, and a first electrode of the second TFT is electrically connected to a gate of the corresponding first TFT, and forming, on the second TFTs, a plurality of write word lines arranged in parallel, where a gate of the second TFT is electrically connected to the write word line. Both the first TFT and the second TFT in the memory are manufactured by using the foregoing TFT manufacturing method, so that sizes of the first TFT and the second TFT in the manufactured memory are relatively small, thereby improving area utilization.

In a possible implementation, after forming, on the plurality of first signal lines, a plurality of first TFTs distributed in an array and a plurality of second signal lines arranged in parallel, and before the forming, on the first TFTs, a plurality of second TFTs distributed in an array and a plurality of write bit lines arranged in parallel, the manufacturing method of any layer of storage array further includes forming a plurality of connection electrodes distributed in an array, where a gate of the first TFT is electrically connected to a first electrode of the corresponding second TFT by using the connection electrode.

REFERENCE NUMERALS

DESCRIPTION OF EMBODIMENTS

The following describes the technical solutions in embodiments of this disclosure with reference to the accompanying drawings in embodiments of this disclosure. It is clear that the described embodiments are merely some rather than all of embodiments of this disclosure.

The following terms “first”, “second” and the like are merely intended for ease of description, and shall not be understood as an indication or implication of relative importance or implicit indication of a quantity of indicated technical features. Therefore, a feature limited by “first”, “second”, or the like may explicitly or implicitly include one or more of the features. In the descriptions of this disclosure, unless otherwise stated, “a plurality of” means two or more than two.

In embodiments of this disclosure, unless otherwise clearly specified and limited, the term “connection” should be understood in a broad sense. For example, the “connection” may be a fixed connection, a detachable connection, or an integral connection, or may be a direct connection, or may be an indirect connection through an intermediate medium. In addition, the term “electrical connection” may be a direct electrical connection, or may be an indirect electrical connection through an intermediate medium. In addition, the term “coupling” may indicate that two or more components are in direct physical contact or electrical contact, or may indicate that two or more components are not in direct contact with each other, but are electrically connected or interact with each other through an intermediate medium.

In embodiments of this disclosure, the word “example” or “for example” or the like is used to represent giving an example, an illustration, or a description. Any embodiment or design solution described as an “example” or “for example” in embodiments of this disclosure should not be explained as being more preferred or having more advantages than another embodiment or design solution. Exactly, use of the word “example”, “for example” or the like is intended to present a relative concept in a specific manner.

In embodiments of this disclosure, the term “and/or” describes an association relationship between associated objects and may indicate that three relationships exist. For example, A and/or B may indicate the following cases: only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. The character “/” generally indicates an “or” relationship between the associated objects.

In embodiments of this disclosure, descriptions about the accompanying drawings are descriptions based on directions shown in the accompanying drawings. When the directions shown in the accompanying drawings change, corresponding descriptions also change accordingly.

With the continuous development of integrated circuit technologies, a quantity of transistors disposed on a chip per unit area in an electronic product such as a computer or a mobile phone continuously increases, so that performance of the electronic product is continuously optimized. On one hand, an amount of data that can be operated by a processor on the chip in a unit time continuously increases, and on the other hand, a storage density of a memory on the chip also continuously increases, thereby meeting people's requirements for data processing in the information era. However, because a logical unit in the processor and a storage cell in the memory are different in structures and techniques, performance improvement degrees of the processor and the memory are different. Further, the storage density and a read/write speed of the memory cannot keep up with an operation speed of the processor, and a “storage wall” appears, which finally limits overall performance improvement of the electronic product.

To resolve the foregoing problem, various types of memories emerge. In various types of memories, a gain cell memory is widely used, and a main target application scenario of the gain cell memory is a high-speed and high-density memory. A gain cell memory of a 2T0C structure can implement a nanosecond-level read/write speed and a millisecond-level storage time. The storage time refers to a time for keeping information stored in the memory, that is, a time from a time when the information is written to a time when the information is correctly read. However, a storage time of the gain cell memory of the 2T0C structure is relatively short, the gain cell memory of the 2T0C structure needs to be continuously refreshed in an actual application. This causes relatively large dynamic power consumption.

Based on the foregoing description, to improve keeping duration of the memory of the 2T0C structure and resolve a problem that power consumption of the gain cell memory of the 2T0C structure is relatively large, the gain cell memory of the 2T0C structure may be prepared based on a TFT. On one hand, an advantage of an ultra-low leakage current of the TFT may be used, so that a keeping time of the memory of the 2T0C structure is greatly increased, and dynamic power consumption is reduced, and on the other hand, an advantage of a low temperature of a TFT manufacturing process may be used, so as to implement three-dimensional (3D) memory integration, and improve a storage density.

Refer toFIG.2A,FIG.2Ais a schematic diagram of a structure of a storage cell in a memory of a 2T0C structure. The storage cell includes a first TFT Tr0and a second TFT Tr1. A gate of the second TFT Tr1is electrically connected to a write word line WWL, a source of the second TFT Tr1is electrically connected to a write bit line WBL, a drain of the second TFT Tr1is electrically connected to a gate of the first TFT Tr0, a source of the first TFT Tr0is electrically connected to a read word line RWL, and a drain of the first TFT Tr0is electrically connected to a read bit line RBL.

FIG.2BandFIG.2Care respectively schematic diagrams of structures of a first TFT Tr0and a second TFT Tr1in a storage cell of a TFT-based memory of a 2T0C structure. Refer toFIG.2BandFIG.2C, both the first TFT Tr0and the second TFT Tr1include a semiconductor layer102disposed on a substrate101, a source103and a drain104that are disposed on the semiconductor layer102and in contact with the semiconductor layer102, a gate insulation layer105disposed on the semiconductor layer102, and a gate106disposed on the gate insulation layer105. In addition, an interlayer dielectric layer107inFIG.2BandFIG.2Cis configured to space different conductive film layers, and a signal line is electrically connected to a corresponding electrode by using a via. For example, a read word line RWL is electrically connected to the source103of the first TFT Tr0by using a via.

However, because the semiconductor layers102in the first TFT Tr0and the second TFT Tr1shown inFIG.2BandFIG.2Care both spread along a plane parallel to the gate106, and the source103and the drain104are disposed at a same layer. In this way, sizes of the first TFT Tr0and the second TFT Tr1are relatively large, and area utilization of the first TFT Tr0and the second TFT Tr1is low. In addition, because the source103and the drain104are located at a same layer, a short circuit easily occurs on a signal line electrically connected to the source electrode103and a signal line electrically connected to the drain electrode104, which is not conducive to routing and increases process difficulty.

To resolve the foregoing problem, an embodiment of this disclosure provides a memory. The memory may be used in an electronic device. The electronic device may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, an in-vehicle device, a smart home device, and/or a smart city device, and a specific type of the electronic device is not limited in embodiments of this disclosure.

FIG.3is a schematic diagram of a structure of an electronic device. The electronic device100may include a processor110, an external memory interface120, an internal memory121, a Universal Serial Bus (USB) interface130, a charging management module140, a power management module141, a battery142, an antenna1, an antenna2, a mobile communication module150, a wireless communication module160, an audio module170, a sensor module180, a button190, a motor191, an indicator192, a camera193, a display screen194, and a subscriber identity module (SIM) card interface195.

It may be understood that the structure shown in this embodiment of this disclosure does not constitute a specific limitation on the electronic device100. In some other embodiments of this disclosure, the electronic device100may include more or fewer components than those shown in the figure, or some components may be combined, or some components may be split, or different component deployments may be used. The components shown in the figure may be implemented by hardware, software, or a combination of software and hardware.

The controller may generate an operation control signal based on an instruction operation code and a time sequence signal, to complete control of instruction reading and instruction execution.

In some embodiments, the processor110may include one or more interfaces. The interface may include an Inter-Integrated Circuit (I2C) interface, an I2C Sound (I2S) interface, a pulse-code modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a SIM interface, and/or a USB interface.

The I2C interface is a two-way synchronization serial bus, and includes a serial data line (SDL) and a serial clock line (SCL). The I2S interface may be configured to perform audio communication.

The PCM interface may also be configured to perform audio communication, and sample, quantize, and code an analog signal.

The UART interface is a universal serial data bus, and is configured to perform asynchronous communication. The bus may be a two-way communication bus. The UART interface converts to-be-transmitted data between serial communication and parallel communication.

The MIPI interface may be configured to connect the processor110to a peripheral component such as the display screen194or the camera193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), and the like.

The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or a data signal. The GPIO interface may alternatively be configured as an I2C interface, an I2S interface, a UART interface, or an MIPI interface.

The USB interface130is an interface that conforms to a USB standard specification, and may be a Mini USB interface, a Micro USB interface, or a USB Type-C interface. The USB interface130may be configured to connect to a charger to charge the electronic device100, or may be configured to transmit data between the electronic device100and a peripheral device, or may be configured to connect to a headset, to play audio by using the headset.

The charging management module140is configured to receive a charging input from a charger. The charger may be a wireless charger or a wired charger.

A wireless communication function of the electronic device100may be implemented by using the antenna1, the antenna2, the mobile communication module150, the wireless communication module160, the modem processor, and the baseband processor.

The mobile communication module150may provide a wireless communication solution that includes second generation (2G)/third generation (3G)/fourth generation (4G)/fifth generation (5G) and that is applied to the electronic device100. The mobile communication module150may include at least one filter, a switch, a power amplifier, and a low-noise amplifier (LNA). The mobile communication module150may receive an electromagnetic wave through the antenna1, perform processing such as filtering or amplification on the received electromagnetic wave, and transmit the electromagnetic wave to the modem processor for demodulation. The mobile communication module150may further amplify a signal modulated by the modem processor, and convert the signal into an electromagnetic wave for radiation through the antenna1.

The wireless communication module160may provide a wireless communication solution that is applied to the electronic device100, and that includes a wireless local area network (WLAN) (for example, a WI-FI network), BLUETOOTH (BT), a global navigation satellite system (GNSS), frequency modulation (FM), a near-field communication (NFC) technology, or an infrared (IR) technology. The wireless communication module160may be one or more components integrating at least one communication processor module. The wireless communication module160receives an electromagnetic wave through the antenna2, performs frequency modulation and filtering processing on an electromagnetic wave signal, and sends a processed signal to the processor110. The wireless communication module160may further receive a to-be-sent signal from the processor110, perform frequency modulation and amplification on the signal, and convert the signal into an electromagnetic wave for radiation through the antenna2.

In some embodiments, the antenna1of the electronic device100is electrically connected to the mobile communication module150, and the antenna2is electrically connected to the wireless communication module160, so that the electronic device100can communicate with a network and another device by using a wireless communication technology. The wireless communication technology may include a Global System for Mobile Communications (GSM), a General Packet Radio Service (GPRS), and code-division multiple access (CDMA).

The electronic device100may implement a display function through the GPU, the display screen194, and the application processor. The GPU is a microprocessor for image processing, and is connected to the display screen194and the application processor. The GPU is configured to perform mathematical and geometric computation and render an image. The processor110may include one or more GPUs, which execute program instructions to generate or change display information.

The display screen194is configured to display an image or a video. In some embodiments, the electronic device100may include one or N display screens194, where N is a positive integer greater than 1.

The electronic device100may implement a photographing function through the ISP, the camera193, the video codec, the GPU, the display screen194, and the application processor.

The ISP is configured to process data fed back by the camera193.

The camera193is configured to capture a static image or a video. In some embodiments, the electronic device100may include one or N cameras193, where N is a positive integer greater than 1.

The external memory interface120may be configured to connect to an external storage card, for example, a Micro Secure Digital (SD) card, to extend a storage capability of the electronic device100. The external storage card communicates with the processor110through the external memory interface120, to implement a data storage function. For example, files such as music and videos are stored in the external storage card.

The internal memory121may be configured to store computer-executable program code. The executable program code includes instructions. The internal memory121may include a program storage region and a data storage region. The program storage region may store an operating system and an application program required by at least one function (for example, a sound playback function or an image display function). The data storage region may store data (such as audio data and an address book) created during use of the electronic device100. In addition, the internal memory121may include a high-speed random-access memory (RAM), or may include a non-volatile memory, for example, at least one magnetic disk storage device, a flash memory device, or a Universal Flash Storage (UFS). The processor110runs the instructions stored in the internal memory121and/or the instructions stored in the memory disposed in the processor, to perform various function applications and data processing of the electronic device100.

The electronic device100may implement an audio function by using the audio module170and the application processor, for example, music playback and recording.

The audio module170is configured to convert digital audio information into an analog audio signal for output, and is also configured to convert an analog audio input into a digital audio signal. The audio module170may be further configured to code and decode an audio signal.

The motor191may generate a vibration prompt. The motor191may be configured to provide an incoming call vibration prompt and a touch vibration feedback.

The SIM card interface195is configured to connect to a SIM card. The SIM card may be inserted into the SIM card interface195or removed from the SIM card interface195, to implement contact with or separation from the electronic device100. The electronic device100may support one or N SIM card interfaces, where N is a positive integer greater than 1.

Based on this, the electronic device100may further include a circuit board, for example, a printed circuit board (PCB). The processor110and the internal memory121may be disposed on the circuit board, and the processor110and the internal memory121are electrically connected to the circuit board.

The memory provided in this embodiment of this disclosure may be used as the internal memory121in the electronic device100, or may be used as the memory in the processor110of the electronic device100.

The memory provided in this embodiment of this disclosure may be an off-chip memory, or may be an on-chip memory (or an embedded memory).

In addition, the memory provided in this embodiment of this disclosure may be a memory prepared based on a back end of line (BEOL) process.

Refer toFIG.4, the memory200includes at least one layer of storage array201disposed on a substrate101.FIG.4is a schematic diagram by using an example in which the memory200includes two layers of storage arrays201. In a case that the memory200includes a plurality of layers of storage arrays201, as shown inFIG.4, the storage arrays201may be sequentially stacked along a vertical direction.

In addition, in a case that the memory200includes a plurality of layers of storage arrays201, the memory200may also be referred to as a three-dimensional integrated memory.

In addition, a quantity of layers of the storage arrays201may be stacked as required. A larger quantity of layers of the stacked storage arrays201indicates a higher storage density of the memory200.

In a case that the memory200includes a plurality of layers of storage arrays201, in some embodiments, refer toFIG.4, the memory200further includes a sixth dielectric layer202disposed between two adjacent layers of storage arrays201, and the two adjacent layers of storage arrays201are separated by using the sixth dielectric layer202.

A material of the sixth dielectric layer202may be one or more of an insulation material such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), yttrium trioxide (Y2O3), and silicon nitride (Si3N4).

The sixth dielectric layer202may be a single-layer structure, or may be a multi-layer stacked structure. In addition, a material of the single-layer structure and a material of each layer in the multi-layer stacked structure may be one or more of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

Refer toFIG.5andFIG.6A, each layer of storage array201includes a plurality of storage cells201A, write word lines WWLs, write bit lines WBLs, read word lines RWLs, and read bit lines RBLs that are distributed in an array.

Refer toFIG.6A,FIG.6B,FIG.6C,FIG.6D, andFIG.6E, the storage cell201A includes a first TFT Tr0and a second TFT Tr1that are stacked.

The first TFT Tr0includes a gate106a, and the gate106aincludes a gate base1061alocated at a top portion and a gate body1062aextending from the gate base1061ato a bottom portion. The first TFT Tr0further includes a first electrode109a, a second electrode108a, a first dielectric layer113a, a second dielectric layer112a, and a semiconductor layer102a. The first electrode109ais located at the bottom portion, and the second electrode108ais located between the first electrode109aand the gate base1061a. The first dielectric layer113ais disposed between the second electrode108aand the first electrode109a, and the first dielectric layer113ais configured to separate the first electrode109afrom the second electrode108a. The semiconductor layer102ais disposed along a side surface of the gate body1062a, and the second dielectric layer112aseparates the semiconductor layer102afrom the gate106a. The first electrode109aand the second electrode108aare electrically connected to the semiconductor layer102arespectively.

As shown inFIG.6A,FIG.6B,FIG.6C, andFIG.6D, the second dielectric layer112acovers a surface of the gate base1061aand a surface of the gate body1062a. Further, the second dielectric layer112asurrounds an outer side of the gate body1062aon the first electrode109a, the semiconductor layer102asurrounds an outer side of the second dielectric layer112a, and the second electrode108ais disposed on an outer side of the semiconductor layer102aand is electrically connected to the semiconductor layer102a. The second electrode108ais on the first electrode109aand is separated by the first dielectric layer113a, and the first electrode109ais electrically connected to the semiconductor layer102a.

The second TFT Tr1includes a gate106b, and the gate106bincludes a gate base1061blocated at a top portion and a gate body1062bextending from the gate base1061bto a bottom portion. The second TFT Tr1further includes a first electrode109b, a second electrode108b, a first dielectric layer113b, a second dielectric layer112b, and a semiconductor layer102b. The first electrode109bis located at the bottom portion, and the second electrode108bis located between the first electrode109aand the gate base1061a. The first dielectric layer113bis disposed between the second electrode108band the first electrode109b, and the first dielectric layer113bis configured to separate the first electrode109bfrom the second electrode108b. The second dielectric layer112bcovers a surface of the gate base106lb and a surface of the gate body1062b. The semiconductor layer102bis disposed along a side surface of the gate body1062b, and the second dielectric layer112bseparates the semiconductor layer102bfrom the gate106b. The first electrode109band the second electrode108bare electrically connected to the semiconductor layer102brespectively.

As shown inFIG.6A,FIG.6B,FIG.6C, andFIG.6D, the second dielectric layer112bsurrounds an outer side of the gate body1062bon the first electrode109b, the semiconductor layer102bsurrounds an outer side of the second dielectric layer112b, and the second electrode108bis disposed on an outer side the semiconductor layer102band is electrically connected to the semiconductor layer102b. The second electrode108bis on the first electrode109band is separated by the first dielectric layer113b, and the first electrode109bis electrically connected to the semiconductor layer102b.

The gate106b(G) of the second TFT Tr1is electrically connected to a write word line WWL, and the second electrode108bis electrically connected to a write bit line WBL. The first electrode109aand the second electrode108aof the first TFT Tr0are electrically connected to a read word line RWL and a read bit line RBL respectively. The first electrode109bof the second TFT Tr1is close to the gate106aof the first TFT Tr0, and the first electrode109bof the second TFT Tr1is electrically connected to the gate106aof the first TFT Tr0.

FIG.6Bis a schematic cross-sectional view along a first direction X inFIG.6A,FIG.6Cis a schematic cross-sectional view along a second direction Y inFIG.6A,FIG.6Dis a schematic cross-sectional view along a direction AA inFIG.6BorFIG.6C, andFIG.6Eis another schematic cross-sectional view along a direction AA inFIG.6BorFIG.6C.

It may be understood that the memory200provided in this embodiment of this disclosure is a memory of a gain cell structure based on a 2T0C structure.

In some embodiments, the first electrode109bof the second TFT Tr1is in direct contact with the gate106aof the first TFT Tr0. In some other embodiments, refer toFIG.6A,FIG.6B, andFIG.6C, both the first electrode109bof the second TFT Tr1and the gate106aof the first TFT Tr0are in contact with a connection electrode111, and the first electrode109bof the second TFT Tr1is electrically connected to the gate106aof the first TFT Tr0by using the connection electrode111.

It should be noted that the second TFT Tr1is a write transistor, and the first TFT Tr0is a read transistor.

Structures of the second TFT Tr1and the first TFT Tr0may be the same or may be different. It should be understood that, in some embodiments, a projection of the second TFT Tr1on the substrate overlaps a projection of the first TFT Tr0on the substrate.

It should be understood that the write word line WWL may be manufactured synchronously with the gate106bof the second TFT Tr1, and the write bit line WBL may be manufactured synchronously with the second electrode108bof the second TFT Tr1.

The second electrode108aof the first TFT Tr0may be electrically connected to the read word line RWL, and the first electrode109amay be electrically connected to the read bit line RBL. In this case, the second electrode108aof the first TFT Tr0and the read word line RWL may be synchronously manufactured, and the first electrode109aof the first TFT Tr0and the read bit line RBL may be synchronously manufactured. Alternatively, the second electrode108aof the first TFT Tr0may be electrically connected to the read bit line RBL, and the first electrode109amay be electrically connected to the read word line RWL. In this case, the second electrode108aof the first TFT Tr0and the read bit line RBL may be synchronously manufactured, and the first electrode109aof the first TFT Tr0and the read word line RWL may be synchronously manufactured.

In this embodiment of this disclosure, for the first TFT Tr0, the second electrode108amay be a source (S)103, and the first electrode109amay be a drain (D)104, or the second electrode108amay be a drain104, and the first electrode109amay be a source103. For the second TFT Tr1, the second electrode108bmay be a source103, and the first electrode109bmay be a drain104, or the second electrode108bmay be a drain104, and the first electrode109bmay be a source103.

In addition, both the first TFT Tr0and the second TFT Tr1may be N-type transistors or may be P-type transistors. Certainly, one of the first TFT Tr0and the second TFT Tr1may be an N-type transistor, and the other may be a P-type transistor.

In some embodiments, a plurality of first TFTs Tr0included in each layer of storage array201may be synchronously manufactured, and/or a plurality of second TFTs Tr1included in each layer of storage array201may be synchronously manufactured.

Refer toFIG.5, the following describes a write operation process and a read operation process of the memory200by using one storage cell201A as an example.

Write operation process: In a write operation process, voltages on the read word line RWL and the read bit line RBL are0, and the first TFT Tr0does not work, and the write word line WWL provides a first switch signal, and the first switch signal controls the second TFT Tr1to be turned on. When first logical information is written, and the first logical information is, for example, “0”, the write bit line WBL provides a first level signal, and the first level signal is written into a node N by using the second TFT Tr1, where the first level signal may control the first TFT Tr0to be turned on. When second logical information is written, and the second logical information is, for example, “1”, the write bit line WBL provides a second level signal, and the second level signal is written into the node N by using the second TFT Tr1, where the second level signal may control the first TFT Tr0to be turned off.

It should be understood that, after the write operation is completed, voltages on the read word line RWL and the read bit line RBL are 0, and the first TFT Tr0does not work, and the write word line WWL provides a second switch signal, and the second switch signal controls the second TFT Tr1to be turned off. In this case, a potential stored by the node N is not affected by an external environment.

Read operation process: The write word line WWL provides the second switch signal, and the second switch signal controls the second TFT Tr1to be turned off, and the read word line RWL provides a third level signal, and logical information stored in the storage cell201A is determined based on a current on the read bit line RBL. When the node N stores the first level signal, because the first level signal may control the first TFT Tr0to be turned on, when the read word line RWL provides the third level signal, the read word line RWL charges the read bit line RBL by using the first TFT Tr0, and the voltage on the read bit line RBL increases. In this way, when it is detected that the current on the read bit line RBL is relatively large, the logical information “0” stored in the storage cell201A may be read. When the node N stores the second level signal, because the second level signal may control the first TFT Tr0to be turned off, when the read word line RWL provides the third level signal, the read word line RWL does not charge the read bit line RBL by using the first TFT Tr0, and the read bit line RBL maintains a 0 V voltage. In this way, when it is detected that the current on the read bit line RBL is relatively small, the logical information “1” stored in the storage cell201A may be read.

For a plurality of second TFTs Tr1, in some embodiments, refer toFIG.5,FIG.6A, andFIG.6B, gates106bof second TFTs Tr1in a plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the first direction X are electrically connected to a same write word line WWL, and refer toFIG.5,FIG.6A, andFIG.6C, second electrodes108bof second TFTs Tr1in a plurality of storage cells201A that are sequentially arranged in each layer of storage array201A along the second direction Y are electrically connected to a same write bit line WBL, where the first direction X intersects with the second direction Y.

In some examples, the first direction X and the second direction Y are orthogonal. For ease of description, the following uses an example in which the first direction X is a row direction and the second direction Y is a column direction.

In each layer of storage array201, the gates106bof the second TFTs Tr1in the plurality of storage cells201A that are sequentially arranged along the first direction X are electrically connected to a same write word line WWL, and the second electrodes108bof the second TFTs Tr1in the plurality of storage cells201A that are sequentially arranged along the second direction Y are electrically connected to a same write bit line WBL. Therefore, in the write operation process, the first switch signal may be provided to the plurality of write word lines WWL row by row, so that the plurality of rows of second TFTs Tr1are turned on row by row. In a case that the first switch signal is provided to a write word line WWL of a current row, logical information is simultaneously written, by using a plurality of write bit lines WBL, to a plurality of storage cells201A that are electrically connected to the write word line WWL of the current row, so that the logical information may be written to the storage cells201A row by row, thereby implementing quick writing of the plurality of storage cells201A in the storage array201.

For example, a plurality of first TFTs Tr0may be connected in the following four manners. In a case that the first electrode109aof the first TFT Tr0is electrically connected to the read bit line RBL, and the second electrode108ais electrically connected to the read word line RWL, the following first manner or second manner may be used.

First manner: Refer toFIG.5,FIG.6A, andFIG.6B, second electrodes108aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the first direction X are electrically connected to a same read word line RWL, and refer toFIG.5,FIG.6A, andFIG.6C, first electrodes109aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the second direction Y are electrically connected to a same read bit line RBL, where the first direction X intersects with the second direction Y.

In each layer of storage array201, the second electrodes108aof the first TFTs Tr0in the plurality of storage cells201A that are sequentially along the first direction X are electrically connected to a same read word line RWL, and the first electrodes109aof the first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged along the second direction Y are electrically connected to a same read bit line RBL. Therefore, in the read operation process, the third level signal may be provided to the plurality of read word lines RWL row by row. In a case that the third level signal is provided to a read word line RWL of a current row, a current on each read bit line RBL is detected. In this way, logical information stored in a plurality of storage cells201A that are electrically connected to the read word line RWL of the current row can be simultaneously read, so that the logical information stored in the storage cells201A can be read row by row, thereby implementing quick reading of the plurality of storage cells201A in the storage array201.

Second manner: Second electrodes108aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the second direction Y are electrically connected to a same read word line RWL, and first electrodes109aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the first direction X are electrically connected to a same read bit line RBL, where the first direction X intersects with the second direction Y.

In a case that the first electrode109aof the first TFT Tr0is electrically connected to the read word line RWL, and the second electrode108ais electrically connected to the read bit line RBL, the following third manner or fourth manner may be used.

Third manner: Second electrodes108aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the first direction X are electrically connected to a same read bit line RWL, and first electrodes109aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the second direction Y are electrically connected to a same read word line RWL, where the first direction X intersects with the second direction Y.

Fourth manner: Second electrodes108aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the second direction Y are electrically connected to a same read bit line RWL, and first electrodes109aof first TFTs Tr0in the plurality of storage cells201A that are sequentially arranged in each layer of storage array201along the first direction X are electrically connected to a same read word line RWL, where the first direction X intersects with the second direction Y.

It should be noted that the second manner, the third manner, and the fourth manner have a same technical effect as the first manner. For details, refer to the foregoing description of the technical effect of the first manner. Details are not described herein again.

Based on the foregoing descriptions, for each layer of storage array201, a quantity of storage cells201A along the first direction X and/or the second direction Y may be increased, to implement a larger-scale storage array.

Refer toFIG.7, in some embodiments, the memory200further includes an integrated circuit203, and the storage array201is disposed on the integrated circuit203. In this case, the memory200is an on-chip memory. In this case, the substrate in the memory200is the integrated circuit203.

A substrate of the integrated circuit203may be a silicon substrate, that is, the integrated circuit203may be an integrated circuit on a silicon substrate.

In addition, the integrated circuit203may be a control circuit of the storage array201, or may be another functional circuit.

It should be noted that, because a process temperature of manufacturing a TFT is relatively low, the storage array201may be integrated into a back end of line of the integrated circuit203. In addition, stacking of a plurality of layers of storage arrays201may be implemented on the integrated circuit203, so as to implement3D system integration.

In some examples, the storage cell201A in the storage array201may be electrically connected to the integrated circuit203. For example, the storage cell201A in the storage array201may be connected to the lower integrated circuit203by using an interconnection line.

An embodiment of this disclosure further provides a TFT10. The TFT may be used as the foregoing first TFT Tr0, or may be used as the foregoing second TFT Tr1.

A structure of the TFT10is described in detail below.

Refer toFIG.8A,FIG.8B, andFIG.8C, the TFT10includes a gate106, a first electrode109, a second electrode108, a first dielectric layer113, a second dielectric layer112, and a semiconductor layer102.

The gate106includes a gate base1061located at a top portion and a gate body1062extending from the gate base1061to a bottom portion. The first electrode109is located at the bottom portion. The second electrode108is located between the first electrode109and the gate base1061. The first dielectric layer113is disposed between the second electrode108and the first electrode109, and the first dielectric layer113is configured to separate the first electrode109from the second electrode108. The second dielectric layer112covers a surface of the gate base1061and a surface of the gate body1062. The semiconductor layer102is disposed along a side surface of the gate body1062, and the second dielectric layer112separates the semiconductor layer102from the gate106. The first electrode109and the second electrode108are electrically connected to the semiconductor layer102respectively.

FIG.8Bis a schematic cross-sectional view along a direction BB inFIG.8A, andFIG.8Cis another schematic cross-sectional view along a direction BB inFIG.8A.

As shown inFIG.8AandFIG.8B, the second dielectric layer112surrounds an outer side of the gate body1062on the first electrode109, the semiconductor layer102surrounds an outer side of the second dielectric layer112, and the second electrode108is disposed on an outer side the semiconductor layer102and is electrically connected to the semiconductor layer102. The second electrode108is on the first electrode109and is separated by the first dielectric layer113, and the first electrode109is electrically connected to the semiconductor layer102.

It should be noted that the gate body1062includes a surface in contact with the gate base1061, a surface away from the gate base1061, and a side surface. The surface in contact with the gate base1061and the surface away from the gate base1061are disposed opposite to each other.

In some embodiments, the gate body1062and the gate base1061are integrally formed. In some other embodiments, the gate body1062and the gate base1061are separately manufactured.

In some examples, the gate body1062is disposed perpendicular to the gate base1061.

The first electrode109forms ohmic contact with the semiconductor layer102, and the second electrode108forms ohmic contact with the semiconductor layer102. In addition, that the first electrode109is electrically connected to the semiconductor layer102may be that the first electrode109is in direct contact with the semiconductor layer102, or may be that the first electrode109is not in direct contact with the semiconductor layer102, but is electrically connected to the semiconductor layer102by using another medium. Similarly, that the second electrode108is electrically connected to the semiconductor layer102may be that the second electrode108is in direct contact with the semiconductor layer102, or may be that the second electrode108is not in direct contact with the semiconductor layer102, but is electrically connected to the semiconductor layer102by using another medium.

It should be noted that the first electrode109in the TFT10may be a drain, and the second electrode108may be a source, or the first electrode109in the TFT10may be a source, and the second electrode108may be a drain.

In addition, the TFT10may be an N-type transistor or may be a P-type transistor.

In addition, because the second dielectric layer112covers the surface of the gate base1061and the surface of the gate body1062, as shown inFIG.8A, the second dielectric layer112includes a first dielectric part1121and a second dielectric part1122, where the first dielectric part1121covers the surface of the gate base1061, and the second dielectric part1122covers the surface of the gate body1062.

Based on this, in some embodiments, the first dielectric part1121and the second dielectric part1122are synchronously manufactured. In some other embodiments, the first dielectric part1121and the second dielectric part1122may be separately manufactured.

Considering that if a distance between the first electrode109and the second electrode108is too short, there may be a risk that the first electrode109and the second electrode108are directly conducted when the first electrode109and the second electrode108are manufactured. To avoid direct conduction of the first electrode109and the second electrode108, in some embodiments, the second electrode108is disposed close to the gate base1061.

It should be understood that materials of the gate106, the first electrode109, and the second electrode108are all conductive materials, for example, metal materials. Further, the materials of the gate106, the first electrode109, and the second electrode108may be one or more of conductive materials such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (In—Ti—O or ITO), aluminum (Al), copper (Cu), ruthenium (Ru), and argentum (Ag).

For the material of the first dielectric layer113and the material of the second dielectric layer112, refer to the material of the sixth dielectric layer202. Details are not described herein again. In addition, the first dielectric layer113and the second dielectric layer112each may be a single-layer structure, or may be a multi-layer stacked structure.

A material of the semiconductor layer102may be one or more of semiconductor materials such as silicon (Si), polysilicon (poly-Si or p-Si), amorphous silicon (amorphous-Si or a-Si), indium gallium zinc oxide (In—Ga—Zn—O or IGZO) poly-compound, zinc oxide (ZnO), ITO, titanium dioxide (TiO2), and molybdenum disulfide (MoS2).

An embodiment of this disclosure provides a TFT10. The gate106of the TFT10includes the gate base1061located at the top portion and the gate body1062extending from the gate base1061to the bottom portion. The semiconductor layer102is disposed along the side of the gate body1062, the first electrode109is located at the bottom portion, the second electrode108is located between the first electrode109and the gate base1061, and the first electrode109and the second electrode108are electrically connected to the semiconductor layer102respectively. In the conventional technology, the semiconductor layer102is disposed along a plane parallel to the gate106(the gate106in the conventional technology is equivalent to the gate base1061in this embodiment of this disclosure), and the second electrode108and the first electrode109are disposed at a same layer, so that a size of the TFT10provided in this embodiment of this disclosure is relatively small on the plane parallel to the gate base1061. Therefore, in this embodiment of this disclosure, a size of the TFT10is reduced, and area utilization is improved. In addition, because the second electrode108and the first electrode109of the TFT10in this embodiment of this disclosure are located at different layers, a short circuit occurring during routing of a signal line electrically connected to the second electrode108and a signal line electrically connected to the first electrode109may be avoided, thereby reducing process difficulty.

When structures of the first TFT Tr0and the second TFT Tr1in the memory200are the foregoing TFT10, sizes of the first TFT Tr0and the second TFT Tr1in the memory200can be reduced, and area utilization can be improved.

For a structure of the gate106, the following three implementations may be used as examples.

First implementation: As shown inFIG.8A,FIG.9,FIG.10, andFIG.11, a boundary of a projection of the gate body1062on the gate base1061is located within a boundary of the gate base1061, that is, the gate body1062is disposed in a middle region of the gate base1061.

Second implementation: As shown inFIG.12AandFIG.12C, a boundary of a projection of the gate body1062on the gate base1061partially overlaps a boundary of the gate base1061, that is, the gate body1062is disposed in an edge region of the gate base1061.

Third implementation: As shown inFIG.12B, the gate body1062is of a hollow structure, and an outer boundary of a projection of the gate body1062on the gate base1061overlaps a boundary of the gate base1061.

It should be understood that, because the gate body1062is of a hollow structure, the projection of the gate body1062on the gate base1061includes two boundaries: an outer boundary and an inner boundary. A boundary close to a center of the gate base1061is referred to as an inner boundary, and a boundary away from the center of the gate base10161is referred to as an outer boundary.

In addition, because the gate body1062is of a hollow structure, and the outer boundary of the projection of the gate body1062on the gate base1061overlaps the boundary of the gate base1061, at least a part of a region of the second dielectric layer112is located in the hollow structure, at least a part of a region of the semiconductor layer102is located in the hollow structure, the second electrode108is located in the hollow structure, and at least a part of a region of the first dielectric layer113is located in the hollow structure.

In a case that the gate body1062is of a hollow structure, the gate106regulates and controls a current in the semiconductor layer102from the outer side of the semiconductor layer102.

For a structure of the semiconductor layer102, the following four implementations may be used as examples.

First implementation: As shown inFIG.8A, the semiconductor layer102is disposed only along the side surface of the gate body1062.

As shown inFIG.8A, the semiconductor layer102surrounds only the side surface of the gate body1062and is disposed on the first electrode109.

The second electrode108and the first electrode109are electrically connected to or in end contact with the semiconductor layer102.

Second implementation: As shown inFIG.12C, the semiconductor layer102is disposed along the side surface of the gate body1062, and the semiconductor layer102further includes an extension portion extending along the surface of the gate base1061. The second dielectric layer112separates the semiconductor layer102from the gate106. In addition, as shown inFIG.12C, the semiconductor layer102is disposed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and covers a top surface of the second electrode108.

In some examples, as shown inFIG.12C, the semiconductor layer102is further disposed on a side surface of the first electrode109.

Third implementation: As shown inFIG.9, the semiconductor layer102is disposed along the side surface of the gate body1062, and the semiconductor layer102extends from the side surface of the gate body1062to a side of the gate body1062that is away from the gate base1061, that is, is located between the gate body1062and the first electrode109. That is, the semiconductor layer102further includes an extension portion located between the gate body1062and the first electrode109. In addition, as shown inFIG.9, the semiconductor layer102covers a side surface of the second dielectric layer112and a surface of the bottom portion.

In some examples, as shown inFIG.9, the semiconductor layer102is disposed on the first electrode109.

Fourth implementation: As shown inFIG.10,FIG.11,FIG.12A, andFIG.12B, the semiconductor layer102is disposed along the side surface of the gate body1062, and the semiconductor layer102further includes an extension portion extending along the surface of the gate base1061and an extension portion located between the gate body1062and the first electrode109. In this case, the semiconductor layer102is in a “Z” shape. In other words, as shown in FIG.10,FIG.12A, andFIG.12B, the semiconductor layer102covers a side surface, a bottom surface, and a top surface of the second dielectric layer112. Alternatively, as shown inFIG.11, the semiconductor layer102covers a side surface and a bottom surface of the second dielectric layer112, and further covers a bottom surface of the second electrode108.

In some examples, as shown inFIG.10,FIG.11,FIG.12A, andFIG.12B, the semiconductor layer102is disposed on the first electrode109.

In some embodiments, as shown inFIG.8B, the semiconductor layer102is disposed around the entire side surface of the gate body1062. In this case, the semiconductor layer102may surround the entire side surface of the gate body1062, or the semiconductor layer102may surround a part of the side surface of the gate body1062.

Because the semiconductor layer102is disposed around the entire side surface of the gate body1062, an area of the semiconductor layer102may be increased, and carrier mobility may be improved.

For the second electrode108, in some embodiments, as shown inFIG.8A,FIG.9,FIG.10,FIG.12A, andFIG.12B, the second electrode108is disposed on a side of the semiconductor layer102that is away from the second dielectric layer112.

It should be understood that, in a case that the semiconductor layer102further includes an extension portion extending along the surface of the gate base1061, when the second electrode108is disposed on the side of the semiconductor layer102that is away from the second dielectric layer112, as shown inFIG.10,FIG.12A, andFIG.12B, the second electrode108is not in contact with the second dielectric layer112, and the second electrode108and the second dielectric layer112are separated by the semiconductor layer102. In a case that the semiconductor layer102is disposed along the side surface of the gate body1062and the semiconductor layer102does not include an extension portion extending along the surface of the gate base1061, as shown inFIG.8AandFIG.9, when the second electrode108is disposed on the side of the semiconductor layer102that is away from the second dielectric layer112, the second electrode108is in contact with the second dielectric layer112.

In some other embodiments, as shown inFIG.11, the second electrode108may be disposed on a side of the semiconductor layer102that is close to the second dielectric layer112. In this case, the second electrode108is located between the second dielectric layer112and the semiconductor layer102.

In addition, the second electrode108may be disposed around the entire side surface of the gate body1062, or the second electrode108may be disposed around the side surface of the gate body1062, but is not the entire side surface.

For the first electrode109, the first electrode109is located at the bottom portion, that is, the first electrode109is disposed on a side of the second electrode108that is away from the gate base1061. In some embodiments, as shown inFIG.8A,FIG.9,FIG.10,FIG.11,FIG.12A, andFIG.12B, the first electrode109is disposed on a side of the gate body1062that is away from the gate base1061. In this case, the semiconductor layer102is disposed on the first electrode109. In some other embodiments, as shown inFIG.12C, the first electrode109is disposed on the side surface of the gate body1062. In this case, the semiconductor layer102may also extend along a side surface of the first electrode109.

In some embodiments, as shown inFIG.13, the TFT10further includes a fourth dielectric layer114disposed between the second electrode108and the semiconductor layer102, and/or a fifth dielectric layer115disposed between the first electrode109and the semiconductor layer102.

For a material of the fourth dielectric layer114and a material of the fifth dielectric layer115, refer to the material of the sixth dielectric layer202. Details are not described herein again. In addition, the fourth dielectric layer114and the fifth dielectric layer115each may be a single-layer structure, or may be a multi-layer stacked structure.

It should be noted that the fourth dielectric layer114is disposed between the second electrode108and the semiconductor layer102, and the second electrode108may or may not be in contact with the semiconductor layer102. The fifth dielectric layer115is disposed between the first electrode109and the semiconductor layer102, and the first electrode109may or may not be in contact with the semiconductor layer102.

To ensure that the first electrode109and the second electrode108can be conducted by using the semiconductor layer102when a voltage is provided on the gate106, in some embodiments, thicknesses of both the fourth dielectric layer114and the fifth dielectric layer115range from 0.1 nm to 2 nm.

Because the thicknesses of the fourth dielectric layer114and the fifth dielectric layer115are relatively small, and the thicknesses range from 0.1 nm to 2 nm, even if the fourth dielectric layer114is disposed between the second electrode108and the semiconductor layer102, and/or the fifth dielectric layer115is disposed between the first electrode109and the semiconductor layer102, when a voltage is provided on the gate106, the first electrode109and the second electrode108can still be conducted by using the semiconductor layer102, and performance of the TFT10is not affected. In addition, the fourth dielectric layer114is disposed between the second electrode108and the semiconductor layer102, so as to avoid a problem of diffusion of the second electrode108in a contact region with the semiconductor layer102, and reduce a Fermi level pinning problem of contact between the second electrode108and the semiconductor layer102. The fifth dielectric layer115is disposed between the first electrode109and the semiconductor layer102, so as to avoid a problem of diffusion of the first electrode109in a contact region with the semiconductor layer102, and reduce a Fermi level pinning problem of contact between the first electrode109and the semiconductor layer102.

In some embodiments, a material of the second dielectric layer112is a ferroelectric material. In this case, as shown inFIG.14, the TFT10further includes a third dielectric layer116disposed between the semiconductor layer102and the second dielectric layer112.

For a material of the third dielectric layer116, refer to the material of the sixth dielectric layer202. Details are not described herein again. In addition, the third dielectric layer116may be a single-layer structure, or may be a multi-layer stacked structure.

It may be understood that, when the material of the second dielectric layer112is a ferroelectric material, the gate106, the second dielectric layer112, and the third dielectric layer116form a composite gate structure. By using the composite gate structure, the TFT10may implement performance of a negative capacitance transistor, and a gate control capability of the TFT10may be improved by using the negative capacitance. When the TFT10is used in the memory200, performance of the memory200may be improved.

It should be noted that in this embodiment of this disclosure, materials of the first dielectric layer113, the second dielectric layer112, the third dielectric layer116, the fourth dielectric layer114, and the fifth dielectric layer115may be the same or may be different.

Based on this, when the material of the second dielectric layer112is a ferroelectric material, and the TFT10includes the third dielectric layer116, as shown inFIG.15, the TFT10further includes a first conductive layer117disposed between the second dielectric layer112and the third dielectric layer116.

For a material of the first conductive layer117, refer to the materials of the gate106, the first electrode109, and the second electrode108. Details are not described herein again.

A composite gate structure including the gate106, the second dielectric layer112, the first conductive layer117, and the third dielectric layer116may enable the TFT10to implement performance of a negative capacitance transistor, and a gate control capability of the TFT10may be improved by using the negative capacitance. When the TFT10is used in the memory200, performance of the memory200may be improved.

In some embodiments, as shown inFIG.16, the TFT10further includes a modulation gate electrode118disposed between the first electrode109and the second electrode108, and the modulation gate electrode118is surrounded by the first dielectric layer113.

For a material of the modulation gate electrode118, refer to the materials of the gate106, the first electrode109, and the second electrode108. Details are not described herein again.

It should be noted that, the modulation gate electrode118is surrounded by the first dielectric layer113, so that the modulation gate electrode118is spaced from the first electrode109, the second electrode108, and the semiconductor layer102. That is, the modulation gate electrode118is electrically isolated from the first electrode109, the second electrode108, and the semiconductor layer102by using the first dielectric layer113.

In this embodiment of this disclosure, because the TFT10includes the modulation gate electrode118, a threshold voltage of the TFT10may be adjusted by using the modulation gate electrode118.

In a case that the TFT10is used as the first TFT Tr0and the second TFT Tr1in the memory200, as shown inFIG.17A,FIG.17B, andFIG.17C, in the memory200, the first TFT Tr0further includes a first modulation gate electrode118adisposed between the first electrode109aand the second electrode108a, the first modulation gate electrode118ais disposed on a side of the semiconductor layer102athat is away from the gate body1062a, and the first modulation gate electrode118ais surrounded by the first dielectric layer113a, so that the first modulation gate electrode118ais spaced from the first electrode109a, the second electrode108a, and the semiconductor layer102a, and first modulation gate electrodes118aof a plurality of first TFTs Tr0located at a same layer are electrically connected together, and/or the second TFT Tr1further includes a second modulation gate electrode118bdisposed between the first electrode109band the second electrode108b, the second modulation gate electrode118bis disposed on a side of the semiconductor layer102bthat is away from the gate body1062b, and the second modulation gate electrode118bis surrounded by the first dielectric layer113b, so that the second modulation gate electrode118bis spaced from the first electrode109b, the second electrode108b, and the semiconductor layer102b, and second modulation gate electrodes118bof a plurality of second TFTs Tr1located at a same layer are electrically connected together.

It should be noted thatFIG.17BandFIG.17Care both schematic cross-sectional views along a direction CC inFIG.17A.

The first modulation gate electrodes118aof the plurality of first TFTs Tr0located at the same layer may be electrically connected together. That is, all the first modulation gate electrodes118aof the plurality of first TFTs Tr0located at the same layer may be electrically connected together, or some first modulation gate electrodes118aof the first modulation gate electrodes118aof the plurality of first TFTs Tr0located at the same layer may be electrically connected together. Similarly, the second modulation gate electrodes118bof the plurality of second TFTs Tr1located at the same layer may be electrically connected together. That is, the second modulation gate electrodes118bof the plurality of second TFTs Tr1located at the same layer may be electrically connected together, or some second modulation gate electrodes118bof the second modulation gate electrodes118bof the plurality of second TFTs Tr1located at the same layer may be electrically connected together.

For example, as shown inFIG.17B, the first modulation gate electrodes118ain the four first TFTs Tr0located at the same layer are electrically connected together. In this way, joint modulation of the four storage cells201A may be implemented.

It should be noted that, in an actual application, a quantity of jointly modulated storage cells201A may be selected as required.

For a material of the first modulation gate electrode118aand a material of the second modulation gate electrode118b, refer to the materials of the gate106, the first electrode109, and the second electrode108. Details are not described herein again.

The first TFT Tr0includes the first modulation gate electrode118a, so that a threshold voltage of the first TFT Tr0may be adjusted by using the first modulation gate electrode118a. The second TFT Tr1includes the second modulation gate electrode118b, so that a threshold voltage of the second TFT Tr1may be adjusted by using the second modulation gate electrode118b. Based on this, storage performance of the memory200can be adjusted more flexibly. For example, for the first TFT Tr0, a relatively low potential may be set for the first modulation gate electrode118a, so that leakage currents of the first electrode109aand the second electrode108aof the first TFT Tr0are reduced, thereby implementing a longer storage and maintenance time. In addition, a relatively high potential may be set for the second modulation gate electrode118bin the second TFT Tr1, so that an overall current of the second TFT Tr1is increased, thereby improving a data reading speed.

An embodiment of this disclosure further provides a TFT10manufacturing method, and the method may be used to manufacture the foregoing TFT10. Refer toFIG.18, the TFT10manufacturing method includes the following steps:

S10. Form a first electrode109, a first dielectric layer113, a second electrode108, and a semiconductor layer102on a substrate. The first electrode109, the first dielectric layer113, and the second electrode108are sequentially stacked, the first dielectric layer113separates the first electrode109from the second electrode108, the semiconductor layer102is formed on a side surface of the first dielectric layer113, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

It should be noted that a sequence of forming the first electrode109, the first dielectric layer113, the second electrode108, and the semiconductor layer102is not limited.

Both the first electrode109and the second electrode108may be in direct contact with the semiconductor layer102, or the first electrode109and the second electrode108may be in contact with the semiconductor layer102through another dielectric layer respectively.

For materials of the first electrode109, the first dielectric layer113, the second electrode108, and the semiconductor layer102, refer to the foregoing embodiments. Details are not described herein again.

In addition, the first dielectric layer113includes a surface close to the second electrode108, a surface close to the first electrode109, and a side surface. The surface close to the second electrode108and the surface close to the first electrode109are disposed opposite to each other.

Based on this, the first electrode109may be formed as a drain, and the second electrode108may be formed as a source, or the first electrode109may be formed as a source, and the second electrode1081may be formed as a drain.

S11. Form a second dielectric layer112and a gate106sequentially, where the gate106includes a gate base1061located at a top portion and a gate body1062extending from the gate base1061to a bottom portion, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a material of the second dielectric layer112, refer to the foregoing embodiments. Details are not described herein again.

In addition, for a material of the gate106, refer to the foregoing embodiments. Details are not described herein again.

It should be noted that the gate base1061and the gate body1062may be formed simultaneously, or the gate base1061and the gate body1062may be formed respectively.

Based on the foregoing description, in this embodiment of this disclosure, when the TFT10is manufactured, steps S10and S11may be performed sequentially, or steps S11and S10may be performed sequentially.

An embodiment of this disclosure provides a TFT10manufacturing method. Because the TFT10manufacturing method provided in this embodiment of this disclosure has a same technical effect as the foregoing TFT10, refer to the foregoing description. Details are not described herein again.

The following describes a specific implementation of the TFT10manufacturing method by using examples.

For example, manufacturing a TFT10shown inFIG.8Aincludes the following steps:

S100. As shown inFIG.19, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

The first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080may be sequentially formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

S101. As shown inFIG.19, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

The first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080may be patterned by using dry etching or wet etching.

In addition, the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080may be etched separately, or the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080may be etched simultaneously.

S102. As shown inFIG.19, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall of the groove structure, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side wall of the groove, a semiconductor thin film formed on another part such as a bottom portion of the groove, a top surface of the second electrode108, and an outer side of the groove is etched, so as to form the semiconductor layer102.

The epitaxial growth method includes, for example, chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and other processes.

S103. As shown inFIG.19, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102, the second electrode108, and the first electrode109.

It should be noted that step S103may be implemented in two manners. In a first manner, the second dielectric layer112may be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer112is an entire layer, and covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113. In a second manner, a seventh dielectric thin film may be first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113, and then the seventh dielectric thin film is etched. In addition to a part formed on the side surface and the bottom portion of the groove, the top surface of the second electrode108, and a top surface of the semiconductor layer102, other seventh dielectric thin films are all etched, so as to form the second dielectric layer112. The first manner is not shown in the accompanying drawing.

S104. As shown inFIG.19, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

A process of forming the gate106may be forming a conductive thin film, and etching the conductive thin film to form the gate106.

For example, manufacturing a TFT10shown inFIG.9includes the following steps:

S110. As shown inFIG.20, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S110, refer to the foregoing step S100. Details are not described herein again.

S111. As shown inFIG.20, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

For a specific implementation process of step S111, refer to the foregoing step S101. Details are not described herein again.

S112. As shown inFIG.20, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first dielectric layer113and the side surface of the second electrode108to a surface of a side of the first electrode109that is close to the second electrode108, that is, a top surface of the first electrode109, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side wall and the bottom portion of the groove, a semiconductor thin film formed on another part such as a top surface of the second electrode108and an outer side of the groove is etched, so as to form the semiconductor layer102.

S113. As shown inFIG.20, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102and the second electrode108.

For a specific implementation process of step S113, refer to the foregoing step S103. Details are not described herein again.

S114. As shown inFIG.20, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S114, refer to the foregoing step S104. Details are not described herein again.

For example, manufacturing a TFT10shown inFIG.10includes the following steps:

S120. As shown inFIG.21, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S120, refer to the foregoing step S100. Details are not described herein again.

S121. As shown inFIG.21, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

For a specific implementation process of step S121, refer to the foregoing step S101. Details are not described herein again.

S122. As shown inFIG.21, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, and a surface of a side of the second electrode108that is away from the first electrode109, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first dielectric layer113and the side surface of the second electrode108to the surface of the side of the second electrode108that is away from the first electrode109(that is, a top surface of the second electrode108) and a surface of a side of the first electrode109that is close to the second electrode108(that is, a top surface of the first electrode109), and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side wall and the bottom portion of the groove, and the top surface of the second electrode108, a semiconductor thin film formed on an outer side of the groove is etched, so as to form the semiconductor layer102.

S123. As shown inFIG.21, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

For a specific implementation process of step S123, refer to the foregoing step S103. Details are not described herein again.

S124. As shown inFIG.21, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S124, refer to the foregoing step S104. Details are not described herein again.

It should be noted that a difference between Embodiment 1, Embodiment 2, and Embodiment 3 lies in a structure of the formed semiconductor layer102.

For example, manufacturing a TFT10shown inFIG.13includes the following steps:

S130. As shown inFIG.22, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S130, refer to the foregoing step S100. Details are not described herein again.

S131. As shown inFIG.22, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

For a specific implementation process of step S131, refer to the foregoing step S101. Details are not described herein again.

S132. As shown inFIG.22, form a fifth dielectric layer115at a bottom portion of the groove structure, that is, form the fifth dielectric layer115on a top surface of the first electrode109, where the fifth dielectric layer115is in contact with the first electrode109.

A process of forming the fifth dielectric layer115may be forming a fifth dielectric thin film, and etching the fifth dielectric thin film to form the fifth dielectric layer115.

S133. As shown inFIG.22, form a fourth dielectric layer114on a side of the second electrode108that is away from the first electrode109, that is, form the fourth dielectric layer114on a top surface of the second electrode108, where the fourth dielectric layer114is in contact with the second electrode108.

A process of forming the fourth dielectric layer114may be forming a sixth dielectric thin film, and then etching the sixth dielectric thin film to form the fourth dielectric layer114.

It should be noted that step S132and step S133may be performed step by step. In this case, step S132may be performed first and then step S133is performed, or step S133may be performed first and then step S132is performed. Step S132and step S133may alternatively be synchronously performed, that is, the fourth dielectric layer114and the fifth dielectric layer115are formed simultaneously.

S134. As shown inFIG.22, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, and a surface of a side of the fourth dielectric layer114that is away from the second electrode108, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113, a side surface of the second electrode108, and a side surface of the fourth dielectric layer114, and the semiconductor layer102further extends from the side surface of the first dielectric layer113, the side surface of the second electrode108, and the side surface of the fourth dielectric layer114to the surface of the side of the fourth dielectric layer114that is away from the second electrode108(that is, a top surface of the fourth dielectric layer114) and a surface of a side of the fifth dielectric layer115that is away from the first electrode109(that is, a top surface of the fifth dielectric layer115), and the semiconductor layer102is in contact with both the fourth dielectric layer114and the fifth dielectric layer115, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the fourth dielectric layer114, the fifth dielectric layer115, the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side wall and the bottom portion of the groove, and the top surface of the fourth dielectric layer114, a semiconductor thin film formed on an outer side of the groove is etched, so as to form the semiconductor layer102.

S135. As shown inFIG.22, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

For a specific implementation process of step S135, refer to the foregoing step S103. Details are not described herein again.

S136. As shown inFIG.22, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113, the side surface of the second electrode108, and the side surface of the fourth dielectric layer114, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S136, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, compared with Embodiment 3, step S132and step S133are added in Embodiment 4.

In Embodiment 4, both step S132and step S133are performed. In some embodiments, one of step S132and step S133may alternatively be performed.

In addition, in Embodiment 4, a structure of the semiconductor layer102formed in step S134is the same as a structure of the semiconductor layer102formed in Embodiment 3. In some embodiments, a structure of the semiconductor layer102formed in step S134may also be the same as a structure of the semiconductor layer102formed in Embodiment 1 or Embodiment 2.

For example, manufacturing a TFT10shown inFIG.14includes the following steps:

S140. As shown inFIG.23, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S140, refer to the foregoing step S100. Details are not described herein again.

S141. As shown inFIG.23, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

For a specific implementation process of step S141, refer to the foregoing step S101. Details are not described herein again.

S142. As shown inFIG.23, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first dielectric layer113and the side surface of the second electrode108to a surface of a side of the first electrode109that is close to the second electrode108, that is, a top surface of the first electrode109, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

For a specific implementation process of step S142, refer to the foregoing step S112. Details are not described herein again.

S143. As shown inFIG.23, form a third dielectric layer116, where the third dielectric layer116is formed on the side wall and the bottom portion of the groove structure.

It should be noted that step S143may be implemented in two manners. In a first manner, the third dielectric layer116may be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the third dielectric layer116is an entire layer, and covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113. In a second manner, an eighth dielectric thin film may be first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the eighth dielectric thin film covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113, and then the eighth dielectric thin film is etched. In addition to a part formed on the side surface and the bottom portion of the groove, other eighth dielectric thin films are all etched, so as to form the third dielectric layer116.

S144. As shown inFIG.23, form a second dielectric layer112, where the second dielectric layer112covers the third dielectric layer116, the semiconductor layer102, and the second electrode108, and a material of the second dielectric layer112is a ferroelectric material.

For a specific implementation process of step S144, refer to the foregoing step S103. Details are not described herein again.

S145. As shown inFIG.23, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S145, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, compared with Embodiment 2, step S143is added in Embodiment 5.

In addition, in Embodiment 5, a structure of the semiconductor layer102formed in step S142is the same as a structure of the semiconductor layer102formed in Embodiment 2. In some embodiments, a structure of the semiconductor layer102formed in step S142may also be the same as a structure of the semiconductor layer102formed in Embodiment 1 or Embodiment 3.

For example, manufacturing a TFT10shown inFIG.15includes the following steps:

S150. As shown inFIG.24, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S150, refer to the foregoing step S100. Details are not described herein again.

S151. As shown inFIG.24, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where the first electrode109, the first dielectric layer113, and the second electrode108form a groove structure.

For a specific implementation process of step S151, refer to the foregoing step S101. Details are not described herein again.

S152. As shown inFIG.24, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first dielectric layer113and the side surface of the second electrode108to a surface of a side of the first electrode109that is close to the second electrode108, that is, a top surface of the first electrode1109, and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

For a specific implementation process of step S152, refer to the foregoing step S112. Details are not described herein again.

S153. As shown inFIG.24, form a third dielectric layer116, where the third dielectric layer116is formed on the side wall and the bottom portion of the groove structure.

For a specific implementation process of step S153, refer to the foregoing step S143. Details are not described herein again.

S154. As shown inFIG.24, form a first conductive layer117, where the first conductive layer117is formed on the side wall and the bottom portion of the groove structure.

A fourth conductive thin film may be first formed, where the fourth conductive thin film covers exposed surfaces of the third dielectric layer116, the semiconductor layer102, the second electrode108, the first dielectric layer113, and the first electrode109, and then the fourth conductive thin film is etched. In addition to a part formed on the side surface and the bottom portion of the groove, other fourth conductive thin films are etched, so as to form the first conductive layer117.

S155. As shown inFIG.24, form a second dielectric layer112, where the second dielectric layer112covers the first conductive layer117, the second dielectric layer116, the semiconductor layer102, and the second electrode108, and a material of the second dielectric layer112is a ferroelectric material.

For a specific implementation process of step S155, refer to the foregoing step S103. Details are not described herein again.

S156. As shown inFIG.24, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S156, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, compared with Embodiment 5, step S154is added in Embodiment 6.

For example, manufacturing a TFT10shown inFIG.12Bincludes the following steps:

S160. As shown inFIG.25, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S160, refer to the foregoing step S100. Details are not described herein again.

S161. As shown inFIG.25, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where boundaries of projections of the first dielectric layer113and the second electrode108on the first electrode109are located within a boundary of the first electrode109, that is, the first dielectric layer113and the second electrode108are located in a middle region of the first electrode109.

For a specific implementation process of step S161, refer to the foregoing step S101. Details are not described herein again.

S162. As shown inFIG.25, form a semiconductor layer102, where the semiconductor layer102covers exposed surfaces of the second electrode108and the first dielectric layer113and a top surface of the first electrode109, that is, the semiconductor layer102covers a top surface and a side surface of the second electrode108, a side surface of the first dielectric layer113, and the top surface of the first electrode109.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the top surface and the side surface of the second electrode108, the side surface of the first dielectric layer113, and the top surface of the first electrode109, a semiconductor thin film formed on another part is etched, so as to form the semiconductor layer102.

S163. As shown inFIG.25, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

For a specific implementation process of step S163, refer to the foregoing step S103. Details are not described herein again.

S164. As shown inFIG.25, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062is disposed around the entire side surfaces of the first dielectric layer113and the second electrode108, that is, the gate body1062is of a hollow structure, the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S164, refer to the foregoing step S104. Details are not described herein again.

For example, manufacturing a TFT shown inFIG.12Aincludes the following steps.

S170. As shown inFIG.26, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S170, refer to the foregoing step S100. Details are not described herein again.

S171. As shown inFIG.26, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where boundaries of projections of the first dielectric layer113and the second electrode108on the first electrode109partially overlap a boundary of the first electrode109, that is, the first dielectric layer113and the second electrode108are located in an edge region of the first electrode109.

For a specific implementation process of step S171, refer to the foregoing step S101. Details are not described herein again.

S172. As shown inFIG.26, form a semiconductor layer102, where the semiconductor layer102is formed on a side surface of the second electrode108and a side surface of the first dielectric layer113, and the semiconductor layer102further extends from the side surface of the second electrode108and the side surface of the first dielectric layer113to a top surface of the second electrode108and a top surface of the first electrode109.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side surface of the second electrode108and the side surface of the first dielectric layer113, the top surface of the second electrode108, and the top surface of the first electrode109, a semiconductor thin film formed on another part is etched, so as to form the semiconductor layer102.

S173. As shown inFIG.26, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

It should be noted that step S173may be implemented in two manners. In a first manner, the second dielectric layer112may be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer112is an entire layer, and covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113. In a second manner, a seventh dielectric thin film may be first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113, and then the seventh dielectric thin film is etched. In addition to a seventh dielectric thin film formed on a surface of a side of the semiconductor layer102that is away from the first electrode109, a seventh dielectric thin film formed on another place is etched, so as to form the second dielectric layer112. The first manner is not shown in the accompanying drawing.

S174. As shown inFIG.26, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S174, refer to the foregoing step S104. Details are not described herein again.

For example, manufacturing a TFT shown inFIG.12Cincludes the following steps:

S180. As shown inFIG.27, sequentially form a first conductive thin film1090, a first dielectric thin film1130, and a second conductive thin film1080that are stacked on a substrate101.

For a specific implementation process of step S180, refer to the foregoing step S100. Details are not described herein again.

S181. As shown inFIG.27, pattern the first conductive thin film1090, the first dielectric thin film1130, and the second conductive thin film1080to form a first electrode109, a first dielectric layer113, and a second electrode108that are sequentially stacked, where boundaries of projections of the first dielectric layer113and the second electrode108on the first electrode109overlap a boundary of the first electrode109.

For a specific implementation process of step S181, refer to the foregoing step S101. Details are not described herein again.

S182. As shown inFIG.27, form a semiconductor layer102, where the semiconductor layer102is formed on a side surface of the first electrode109, a side surface of the first dielectric layer113, and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first electrode109, the side surface of the first dielectric layer113, and the side surface of the second electrode108to a surface of a side of the second electrode108that is away from the first electrode109, that is, a top surface of the second electrode108. A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109, the first dielectric layer113, and the second electrode108, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the left side surface of the first electrode109, the left side surface of the first dielectric layer113, the left side surface of the second electrode108, and the top surface of the second electrode108, a semiconductor thin film formed on another part is etched, so as to form the semiconductor layer102.

S183. As shown inFIG.27, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

It should be noted that step S183may be implemented in two manners. In a first manner, the second dielectric layer112may be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer112is an entire layer, and covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113. In a second manner, a seventh dielectric thin film may be first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113, and then the seventh dielectric thin film is etched. In addition to a seventh dielectric thin film formed on a side surface and a top surface of the semiconductor layer102, a seventh dielectric thin film formed on another place is etched, so as to form the second dielectric layer112. The first manner is not shown in the accompanying drawing.

S184. As shown inFIG.27, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S184, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, a difference between Embodiment 7, Embodiment 8, and Embodiment 9 and the foregoing other embodiments lies in that structures of the formed first electrode109, first dielectric layer113, and second electrode108that are stacked are different.

For example, manufacturing a TFT10shown inFIG.16includes the following steps:

S190. As shown inFIG.28, form a first conductive thin film1090and a third dielectric thin film1131that are sequentially stacked on a substrate101.

For a specific implementation process of step S190, refer to the foregoing step S100. Details are not described herein again.

S191. As shown inFIG.28, form a modulation gate electrode118on the third dielectric thin film1131.

A specific process of forming the modulation gate electrode118may be forming a fifth conductive thin film, and patterning the fifth conductive thin film to form the modulation gate electrode118.

S192. As shown inFIG.28, form a fourth dielectric thin film1132on the modulation gate electrode118, where the fourth dielectric thin film1132covers the modulation gate electrode118.

The fourth dielectric thin film1132may be formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

S193. As shown inFIG.28, perform grinding processing on the fourth dielectric thin film1132.

Grinding processing may be performed on the fourth dielectric thin film1132by using a chemical mechanical polishing technology.

It should be noted that step S193is an optional step. For example, in some embodiments, step S193may be omitted.

S194. As shown inFIG.28, form a second conductive thin film1080on the fourth dielectric thin film1132.

The second conductive thin film1080may be formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, and electroplating.

S195. As shown inFIG.28, pattern the second conductive thin film1080to form a second electrode108, pattern the fourth dielectric thin film1132and the third dielectric thin film1131to form a first dielectric layer113, and pattern the first conductive thin film1090to form a first electrode109, where the second electrode108, the first dielectric layer113, and the first electrode109form a groove structure, and the first dielectric layer113surrounds the modulation gate electrode118, so that the modulation gate electrode118is spaced from the second electrode108and the first electrode109.

For a specific implementation process of step S195, refer to the foregoing step S101. Details are not described herein again.

S196. As shown inFIG.28, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, and a surface of a side of the second electrode108that is away from the first electrode109, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113and a side surface of the second electrode108, and the semiconductor layer102further extends from the side surface of the first dielectric layer113and the side surface of the second electrode108to the surface of the side of the second electrode108that is away from the first electrode109(that is, a top surface of the second electrode108) and a surface of a side of the first electrode109that is close to the second electrode108(that is, a top surface of the first electrode109), and both the first electrode109and the second electrode108are electrically connected to the semiconductor layer102.

For a specific implementation process of step S196, refer to the foregoing step S122. Details are not described herein again.

S197. As shown inFIG.28, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102.

For a specific implementation process of step S197, refer to the foregoing step S103. Details are not described herein again.

S198. As shown inFIG.28, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and the side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S198, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, a difference between Embodiment 10 and the foregoing other embodiments mainly lies in that step S191is added in Embodiment 10.

For example, manufacturing a TFT10shown inFIG.11includes the following steps:

S200. As shown inFIG.29, form a first conductive thin film1090and a first dielectric thin film1130that are sequentially stacked on a substrate101.

For a specific implementation process of step S200, refer to the foregoing step S100. Details are not described herein again.

S201. As shown inFIG.29, pattern the first conductive thin film1090and the first dielectric thin film1130to form a first electrode109and a first dielectric layer113that are sequentially stacked, where the first dielectric layer113and the first electrode109form a groove structure.

For a specific implementation process of step S201, refer to the foregoing step S101. Details are not described herein again.

S202. As shown inFIG.29, form a semiconductor layer102, where the semiconductor layer102is formed on a side wall and a bottom portion of the groove structure, and a surface of a side of the first dielectric layer113that is away from the first electrode109, that is, the semiconductor layer102is formed on a side surface of the first dielectric layer113, and the semiconductor layer102further extends from the side surface of the first dielectric layer113to a surface of a side of the first electrode109that is close to the first dielectric layer113(that is, a top surface of the first electrode109) and the surface of the side of the first dielectric layer113that is away from the first electrode109(that is, a top surface of the first dielectric layer113), and the first electrode109is electrically connected to the semiconductor layer102.

A semiconductor thin film may be first formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer, and covers exposed surfaces of the first electrode109and the first dielectric layer113, and then the semiconductor thin film is etched. In addition to a semiconductor thin film formed on the side wall and the bottom portion of the groove, and the top surface of the first dielectric layer113, a semiconductor thin film formed on an outer side of the groove is etched, so as to form the semiconductor layer102.

S203. As shown inFIG.29, form a second electrode108, where the second electrode108is located on the side of the first dielectric layer113that is away from the first electrode109, that is, the second electrode108is located on the top surface of the first dielectric layer113.

A process of forming the second electrode108may be forming a second conductive thin film, and etching the second conductive thin film to form the second electrode108.

S204. As shown inFIG.29, form a second dielectric layer112, where the second dielectric layer112covers the semiconductor layer102and the second electrode108.

It should be noted that step S204may be implemented in two manners. In a first manner, the second dielectric layer112may be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer112is an entire layer, and covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113. In a second manner, a seventh dielectric thin film may be first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers exposed surfaces of the semiconductor layer102, the second electrode108, the first electrode109, and the first dielectric layer113, and then the seventh dielectric thin film is etched. In addition to a part formed on the side surface and the bottom portion of the groove, and a top surface and a side surface of the second electrode108, other seventh dielectric thin films are all etched, so as to form the second dielectric layer112. The first manner is not shown in the accompanying drawing.

S205. As shown inFIG.29, form a gate106, where the gate106includes a gate base1061and a gate body1062extending from the gate base1061, the gate body1062extends into the groove structure, that is, the gate body1062extends along the side surface of the first dielectric layer113and a side surface of the second electrode108, and the gate base1061is formed on a side of the gate body1062that is away from the first electrode109, and the second dielectric layer112separates the gate106from the semiconductor layer102, the first electrode109, and the second electrode108.

For a specific implementation process of step S205, refer to the foregoing step S104. Details are not described herein again.

It should be noted that, a difference between Embodiment 11 and the foregoing other embodiments mainly lies in that a sequence of forming the semiconductor layer102and the second electrode108in Embodiment 11 is different from that in the foregoing other embodiments.

It should be understood that the TFT10provided in embodiments of this disclosure may be manufactured by using the foregoing TFT10manufacturing method, or may be manufactured by using another manufacturing method. This is not limited herein.

An embodiment of this disclosure further provides a memory manufacturing method, including forming at least one layer of storage array201on a substrate101.

For example, as shown inFIG.30, manufacturing any layer of storage array201shown inFIG.4includes the following steps:

S300. Form, on a substrate101, a plurality of first signal lines arranged in parallel.

S301. Form, on the plurality of first signal lines, a plurality of first TFTs Tr0distributed in an array and a plurality of second signal lines arranged in parallel, where a first electrode109aof the first TFT Tr0is electrically connected to the first signal line, and a second electrode108aof the first TFT Tr0is electrically connected to the second signal line, and the first signal line is one of a read bit line RBL and a read word line RWL, and the second signal line is the other of the read bit line RBL and the read word line RWL. The first TFT Tr0may be manufactured by using the TFT10manufacturing method provided in any one of the foregoing embodiments. It may be understood that the plurality of first TFTs Tr0distributed in an array herein may be synchronously formed.

It should be noted that the first signal line may be a read bit line RBL, and the second signal line may be a read word line RWL. In this case, the first electrode109aof the first TFT Tr0is electrically connected to the read bit line RBL, and the second electrode108ais electrically connected to the read word line RWL. Alternatively, the first signal line may be a read word line RWL, and the second signal line is a read bit line RBL. In this case, the first electrode109aof the first TFT Tr0is electrically connected to the read word line RWL, and the second electrode108ais electrically connected to the read bit line RBL.

It may be understood that, in some embodiments, the first electrode109amay be synchronously formed with the first signal line, and the second electrode108amay be synchronously formed with the second signal line.

S302. Form a plurality of connection electrodes111distributed in an array, where a gate106aof one first TFT Tr0is electrically connected to one connection electrode111.

It should be noted that step S302is an optional step. For example, in some embodiments, step S302may also be omitted.

A sixth conductive thin film may be first formed, and then the sixth conductive thin film is etched, to form the plurality of connection electrodes111.

S303. Form, on the first TFTs Tr0, a plurality of second TFTs Tr1distributed in an array and a plurality of write bit lines WBLs arranged in parallel, where a second electrode108bof the second TFT Tr1is electrically connected to the write bit line WBL. One second TFT Tr1corresponds to one first TFT Tr0, and a first electrode109bof the second TFT Tr1is electrically connected to a gate106aof the corresponding first TFT Tr0. The second TFT Tr1may be manufactured by using the TFT10manufacturing method provided in any one of the foregoing embodiments. It may be understood that the plurality of second TFTs Tr1distributed in an array herein may be synchronously formed.

It should be noted that, when the manufacturing method of any layer of storage array201includes step S302, the first electrode109bof the second TFT Tr1is electrically connected to the gate106aof the corresponding first TFT Tr0by using the connection electrode111.

In some embodiments, the second electrode108bof the second TFT Tr1may be synchronously formed with the write bit line WBL.

S304. Form a plurality of write word lines WWLs arranged in parallel on the second TFTs Tr1, where a gate106bof the second TFT Tr1is electrically connected to the write word line WWL.

In some embodiments, the write word line WWL may be synchronously formed with the gate106bof the second TFT Tr1.

Based on the foregoing description, when the memory200includes a plurality of layers of storage arrays201disposed on the substrate101, when the memory200is manufactured, steps S300to5304may be repeated to form the plurality of layers of storage arrays201.

In addition, after a first layer of storage array201is manufactured, and before a second layer of storage array201is formed, the sixth dielectric layer202may be first formed. In this case, the sixth dielectric layer202is used as a substrate of the second layer of storage array201. Similarly, before a third layer of storage array201, a fourth layer of storage array201, and the like are manufactured, the sixth dielectric layer202may also be formed first. The foregoing descriptions are merely specific implementations of this disclosure, but are not intended to limit the protection scope of this disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this disclosure shall fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to the protection scope of the claims.