Memory module data object processing systems and methods

The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.

BACKGROUND

The present disclosure generally relates to memory devices and, more particularly, to memory modules (e.g., sub-systems) implemented with dedicated processing circuitry, as well as memory devices.

Generally, a computing system includes processing circuitry (e.g., one or more processors) and memory devices (e.g., chips or integrated circuits). Often, one or more memory devices may be implemented on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request and a memory module may retrieve corresponding data from its memory devices. In some instances, the retrieved data may include instructions executable by the processing circuitry to perform an operation and/or data to be input to the operation. Additionally, in some instances, data output (e.g., resulting) from the operation may be stored in memory, for example, to enable subsequent retrieval.

In any case, at least in some instances, multiple operations may be targeted for performance by the processing circuitry, for example, over the same or overlapping time periods. As such, processing power (e.g., capabilities) of the processing circuitry may be allocated (e.g., shared or divided) between performance of the various operations. Even as processing power continues to increase, at least in some instances, centralizing processing in the main processing circuitry of a computing system may limit operational efficiency of the computing system, for example, with respect to latency of operation performance.

DETAILED DESCRIPTION

Generally, hardware of a computing system includes processing circuitry and memory, for example, implemented using one or more processors and/or one or more memory devices (e.g., chips or integrated circuits). During operation of the computing system, the processing circuitry may perform various operations (e.g., tasks) by executing corresponding instructions, for example, based on a user input to determine output data by performing operations on input data. To facilitate operation of the computing system, data accessible to the processing circuitry may be stored in a memory device, such that the memory device stores the input data, the output data, data indicating the executable instructions, or any combination thereof.

In some instances, multiple memory devices may be implemented on a memory module, thereby enabling the memory devices to be communicatively coupled to the processing circuitry as a unit. For example, a dual in-line memory module (DIMM) may include a printed circuit board (PCB) and multiple memory devices. In particular, the memory devices may each be disposed on a flat or planar (e.g., front or back) surface of the printed circuit board and selectively coupled to data (e.g., external) pins formed along an (e.g., bottom) edge of the printed circuit board.

In any case, computing system hardware utilization by a single user generally varies over time. Thus, in some instances, hardware resources to be used by multiple users may be centralized and shared to facilitate reducing implementation associated cost, for example, by reducing total component count, reducing total physical footprint (e.g., size), and/or improving scalability compared to multiple discrete computing systems. In some embodiments, the hardware resources may be centralized in one or more remote (e.g., host) computing devices that include host (e.g., main) processing circuitry and host memory modules.

Additionally, in some embodiments, one or more client devices may be communicatively coupled to the remote computing devices via a communication network. In other words, the communication network may enable data communication therebetween and, thus, the client devices to utilize hardware resources provided in the remote computing devices. For example, when a client device receives a user input, the client device may communicate the user input to a remote computing device via the communication network. Based at least in part on the user input, host processing circuitry in the remote computing device may perform one or more operations by executing corresponding instructions, for example, retrieved from a host memory module. Additionally, results of the one or more operations may be communicated back to the client device via the communication network, for example, to enable presentation to a user via display of a graphical user interface (GUI) at the client device.

When multiple client devices are communicatively coupled to the remote computing devices, each client device may utilize hardware resources provided by the remote computing devices in a similar manner. In fact, at least in some instances, this may result in the host processing circuitry being requested to perform multiple different operations, for example, over the same and/or overlapping time periods (e.g., clock cycles). As such, total processing power of the host processing circuitry may be allocated (e.g., divided) between the various operations. At least in some instances, this may result in the remote computing devices allocating less of the host circuitry processing power to an operation than would otherwise be allocated, thereby increasing likelihood of the host processing circuitry limiting operational efficiency (e.g., latency or duration between user input and result return) of the computing system.

Accordingly, to facilitate improving operational efficiency of computing systems, the present disclosure provides tools and techniques for implementing and/or operating memory modules, which, in addition to memory devices, include dedicated (e.g., memory) processing circuitry. In some embodiments, a memory module may include memory processing circuitry in its memory controller. However, beyond merely controlling data access (e.g., storage and/or retrieval), the memory processing circuitry may be implemented to perform data processing operations, for example, which would otherwise be performed by host processing circuitry. For example, the memory processing circuitry may pre-process data being retrieved to the host processing circuitry and/or post-process data received from the host processing circuitry for storage, thereby enabling processing performed by the host processing circuitry to be reduced and, thus, freeing the host processing circuitry for other tasks.

To facilitate processing by memory processing circuitry, related data may be grouped into data blocks, for example, based at least in part on processing interrelationships. As an illustrative example, image data corresponding with video content may be grouped as a first data block. As a further example, data used to provide a client device a virtual machine may be grouped as a second data block. In a similar manner, other types of related data may be additionally or alternatively be grouped into data blocks.

Since data processing is generally data dependent, to facilitate processing by memory processing circuitry, data may be stored as a data object, which, in addition to a data block, includes metadata that provides context for the data block. In some embodiments, a data object may include tag metadata that indicates type and/or other identifying parameters of data included in its data block. For example, a first data object may include first tag metadata, which indicates that its (e.g., first) data block includes image data and/or that its data block corresponds with specific video content. Additionally or alternatively, a second data object may include second tag metadata, which indicates that its (e.g., second) data block includes virtual machine data and/or that its data block corresponds with a specific client device. Furthermore, in some embodiments, a data object may include validity metadata, for example, which may be indicative of whether its data block is valid or contains errors. Metadata may thus include tag metadata and validity metadata, which may be referred to as a first portion and a second portion of the metadata, respectively.

In some embodiments, data objects may be determined (e.g., generated) by processing circuitry, for example, included in host processing circuitry, memory processing circuitry, or both. In any case, to facilitate generating a data object, the processing circuitry may analyze data to group related data into a data block and determine context of the data block, which may be indicated via metadata. To generate the corresponding data object, the metadata and the data block may be associated or grouped together, for example, by concatenating the metadata in front of the data block to facilitate storage as a unit.

As described above, storing data as data objects may facilitate improving operational efficiency of a computing system by enabling a memory module implemented in the computing system to perform data processing operations, for example, to offload processing performed by host processing circuitry. In particular, memory processing circuitry implemented in the memory module may access (e.g., receive, read, or retrieve) a data object, which includes a data block and metadata. Based at least in part on the metadata, the memory processing circuitry may determine context of the data block and perform data processing operations accordingly.

In some embodiments, memory processing circuitry may access data objects and perform corresponding data processing operations based at least in part on communication with host processing circuitry. For example, when a memory access request is received from host processing circuitry, a memory module may retrieve data identified by the memory access request (e.g., via a virtual memory address) from its memory devices. When the retrieved data is a data object, memory processing circuitry in the memory module may read metadata included in the data object and, in some embodiments, pre-process the associated data block accordingly. For example, when the metadata indicates that the data block includes image data, the memory processing circuitry may decode (e.g., decompress) the image data before outputting the data object to the host processing circuitry.

On the other hand, when data for storage is received from host processing circuitry, a memory module may determine whether the data is a data object. In some embodiments, memory processing circuitry in the memory module may determine whether data is a data object based at least in part on whether metadata is included and/or what metadata is included, for example, by reading a specific bit position expected to be allocated for metadata in data objects. In any case, when the received data is a data object, the memory module may read the metadata included in the data object and, in some embodiments, post-process the associated data block accordingly. For example, when the metadata indicates that the data block includes image data, the memory processing circuitry may encode (e.g., compress) the image data before storing the data object in a memory device.

In other words, in some embodiments, memory processing circuitry in a memory module may automatically perform data processing (e.g., pre-processing and/or post-processing) operations during communication with host processing circuitry. In fact, this may enable the host processing circuitry to operate agnostic to processing performed by the memory module, for example, by communicating in the same manner regardless of whether the memory modules include memory processing circuitry. Moreover, by automatically encoding before storage and decoding before output, the memory processing circuitry may facilitate improving data storage efficiency provided by the memory module, for example, without increasing processing performed by the host processing circuitry.

In some embodiments, memory processing circuitry may perform data processing operations based on explicit instructions received from host processing circuitry. In fact, in some embodiments, formatting data in data objects may enable the host processing circuitry to instruct the memory processing circuitry using higher level instructions. For example, instead of specifying its associated memory address, the host processing circuitry may instruct a memory module to return virtual machine data corresponding with a particular client device. By searching tag metadata included in stored data objects, the memory processing circuitry may identify the requested data object, which includes virtual machine data corresponding with the particular client device, for output back to the host processing circuitry.

In fact, in some embodiments, implementing memory processing circuitry in a memory module to perform data search operations may facilitate further improving operational efficiency, for example, by leveraging internal data communication efficiency. Often, compared with external data communication (e.g., between memory module and host processing circuitry), internal data communication (e.g., between memory device and memory processing circuitry) provides faster data communication speed and/or utilizes less electrical power, for example, due to shorter data communication distances, fewer clock synchronizations, and/or higher internal data communication bandwidth. Additionally, data search operations generally involve retrieving data from memory devices and parsing the retrieved data to identify data that meets (e.g., satisfies) one or more search criteria (e.g., rules). As such, performing data search operations and/or other data intensive operations via the memory processing circuitry may facilitate improving operational efficiency by reducing the amount of external data communication, for example, between the memory module and the host processing circuitry.

Moreover, in some embodiments, memory processing circuitry implemented in a memory module may autonomously perform data processing operations, for example, without receiving a trigger (e.g., instruction) from host processing circuitry. In fact, in some embodiments, the memory processing circuitry may opportunistically perform data processing operations, for example, while the host processing circuitry is performing other tasks. As an illustrative example, based at least in part on validity metadata included in a data object, the memory processing circuitry may periodically detect whether an error occurs in a corresponding data block.

To facilitate improving operational reliability, in some embodiments, a computing system may store redundant copies of data. Thus, when an error is detected, the memory processing circuitry may identify a redundant data object via its tag metadata and correct the error using the redundant data object, for example, by overwriting at least erroneous (e.g., invalid) portions of the data object with corresponding portions of the redundant data object. In fact, at least in some instances, detecting and correcting data errors in this manner may facilitate improving data storage efficiency, for example, by enabling a reduction in number of redundant copies stored since errors may be detected via validity metadata and a redundant copy may be identified via tag metadata. Moreover, in some embodiments, error detection and/or error correction may be additionally or alternatively performed using a dedicated (e.g., separate) service processor, for example, to enable error detection and/or error correction when the computing system has otherwise lost power or is otherwise faulty.

In other words, as will be described in more detail below, implementing and/or operating computing systems in accordance with the techniques described in the present disclosure may provide various technical benefits, such as improved operational reliability. Additionally, the techniques described in the present disclosure may facilitate improving data storage efficiency of computing systems, for example, by facilitating storage of encoded (e.g., compressed) data and/or enabling a reduction in number of redundant copies stored. Moreover, the techniques described in the present disclosure may facilitate improving operational efficiency of computing systems, for example, by enabling processing performed by and/or communication with host processing circuitry to be reduced.

To help illustrate, an example of a computing system10, which includes one or more remote computing devices11, is shown inFIG. 1. As in the depicted embodiment, the remote computing devices11may be communicatively coupled to one or more client device12via a communication network14. It should be appreciated that the depicted embodiment is merely intended to be illustrative and not limiting. For example, in other embodiments, the remote computing devices11may be communicatively coupled to a single client device12or more than two client devices12.

In any case, the communication network14may enable data communication between the client devices12and the remote computing devices11. In some embodiments, the client devices12may be physically remote (e.g., separate) from the remote computing devices11, for example, such that the remote computing devices11are located at a centralized data center. Thus, in some embodiments the communication network14may be a wide area network (WAN), such as the Internet, or it may be or include a local area network (LAN) or wireless LAN (WLAN). In any case, to facilitate communication via the communication network14, the remote computing devices11and the client devices12may each include a network interface16.

In addition to the network interface16, a client device12may include input devices18and/or an electronic display20, which enable a user to interact with the client device12. For example, the input devices18may receive user inputs and, thus, may include buttons, keyboards, mice, trackpads, and/or the like. Additionally or alternatively, the electronic display20may include touch sensing components that receive user inputs by detecting occurrence and/or position of an object touching its screen (e.g., surface of the electronic display20). In addition to enabling user inputs, the electronic display20may facilitate providing visual representations of information by displaying a graphical user interface (GUI) of an operating system, an application interface, text, a still image, video content, or the like.

As described above, the communication network14may enable data communication between the remote computing devices11and one or more client devices12. In other words, the communication network14may enable user inputs to be communicated from a client device12to a remote computing device11. Additionally or alternatively, the communication network14may enable results of operations performed by the remote computing device11based on the user inputs to be communicated back to the client device12, for example, as image data to be displayed on its electronic display20.

In fact, in some embodiments, data communication provided by the communication network14may be leveraged to enable centralizing hardware available to multiple users, for example, such that hardware at client devices12may be reduced. As an illustrative example, the remote computing devices11may provide data storage for multiple different client devices12, thereby enabling data storage (e.g., memory) provided locally at the client devices12to be reduced. Additionally or alternatively, the remote computing devices11may provide processing for multiple different client device12, thereby enabling processing power provided locally at the client devices12to be reduced.

Thus, in addition to the network interface16, the remote computing devices11may include host processing circuitry22and one or more memory modules24(e.g., sub-systems) communicatively coupled via a system bus25. In some embodiments, the host processing circuitry22and/or the memory modules24may be implemented across multiple remote computing devices11, for example, such that a first remote computing device11includes a portion of the host processing circuitry22and the first memory module24A while an Mth remote computing device11includes another portion of the host processing circuitry22and the Mth memory module24M. Additionally or alternatively, the host processing circuitry22and the memory modules24may be implemented in a single remote computing device11.

In any case, the host processing circuitry22may execute instructions to perform corresponding operations, for example, indicated by user inputs received from a client device12. Thus, the host processing circuitry22may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. In some embodiments, the host processing circuitry22may additionally perform operations based on circuit connections formed (e.g., programmed) in the host processing circuitry22. Thus, in such embodiments, the host processing circuitry22may additionally include one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or both. The host processing circuitry22may be or include a system on a chip (SoC).

Additionally, a memory module24may provide data storage accessible to the host processing circuitry22. For example, a memory module24may store data received from a client device12, data resulting from an operation performed by the host processing circuitry22, data to be input to the operation, instructions executable by the host processing circuitry22to perform the operation, or any combination thereof. To facilitate providing data storage, a memory module24may include one or more memory devices26(e.g., chips or integrated circuits). In other words, the memory devices26may each be a tangible, non-transitory, computer-readable medium that stores data accessible to the host processing circuitry22.

To facilitate improving operational reliability, in some embodiments, the remote computing devices11may include a service processor27communicatively coupled to one or more memory modules24via a service bus28. In other words, in such embodiments, data stored in memory devices26of a memory module24may be accessible to the service processor27, for example, which may enable the service processor27to perform error detection operations and/or error correction operations. Moreover, as in the depicted embodiment, the service processor27may be separate (e.g., distinct) from the host processing circuitry22and the service bus28may be separate (e.g., distinct) from the system bus25, for example, to enable the service processor27to access stored data even when the remote computing devices11have otherwise lost power and/or are otherwise faulty.

In any case, as described above, the remote computing devices11may access a memory module24during operation, for example, to write (e.g., store) data to its memory devices26and/or to read (e.g., retrieve) stored data from its memory devices26. Accordingly, at least in some instances, operational efficiency of the remote computing devices11and, thus, the computing system10may be dependent on memory access efficiency (e.g., read latency and/or write latency). To facilitate improving memory access efficiency, in some embodiments, a memory module24may control data storage in its memory devices26, for example, via a memory controller.

To help illustrate, an example of a memory module24, which includes a memory controller30and one or more memory devices26, is shown inFIG. 2. In some embodiments, the memory controller30may operate based on circuit connections formed (e.g., programmed) in the memory controller30. Thus, in such embodiments, the memory controller30may include one or more application specific integrated circuits (ASICs), one or more field programmable logic arrays (FPGAs), or both.

As described above, in some embodiments, memory modules24may be communicatively coupled to host processing circuitry22via a system bus25and/or to a service processor27via a service bus28. To facilitate communication via a data bus (e.g., system bus25and/or service bus28), the memory module24may include a bus interface36. For example, the bus interface36may include data pins (e.g., contacts) formed along an (e.g., bottom) edge of a printed circuit board (PCB). Additionally, the memory module24may be implemented by disposing each of the memory devices26on a flat or planar (e.g., front and/or back) surface of the printed circuit board. Thus, in some embodiments, the memory module24may be a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or the like.

Additionally, in some embodiments, the bus interface36may include logic that enables the memory module24to communicate via a communication protocol implemented on a data bus (e.g., system bus25and/or service bus28). For example, the bus interface36may control timing of data output from the memory module24to the data bus and/or interpret data input to the memory module24from the data bus in accordance with the communication protocol. Thus, in some embodiments, the bus interface36may be a double data rate fourth-generation (DDR4) interface, a double data rate fifth-generation (DDR5) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile dual in-line memory module (e.g., NVDIMM-P) interface, or the like.

To facilitate providing data storage, the memory devices26on the memory module24may be implemented as volatile memory, non-volatile memory, or both. In other words, in some embodiments, the memory devices26may include one or more volatile memory devices, such a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, or both. Additionally or alternatively, the memory devices26may include one or more non-volatile memory devices, such as a flash (e.g., NAND) memory device, a phase-change (e.g., 3D XPoint™) memory device, a ferroelectric random access memory (FeRAM) device, or any combination thereof.

In any case, as described above, the memory controller30may control data storage in the memory devices26implemented on the memory module24. For example, the memory controller30may control storage location (e.g., which memory device26and/or physical memory address) of data in the memory module24. Additionally, the memory controller30may retrieve requested data from its storage location, for example, based at least in part on a virtual memory address received from host processing circuitry22and a memory address map that associated the virtual memory address with a corresponding physical memory address. Thus, as in the depicted embodiment, the memory controller30may be coupled between the bus interface36and the memory devices26via one or more internal buses37, for example, implemented via conductive traces formed on the printed circuit board.

To facilitate improving operational efficiency, a memory module24may include memory processing circuitry38implemented to perform data processing operations, for example, which may otherwise be performed by host processing circuitry22. As in the depicted embodiment, the memory processing circuitry38may be implemented in the memory controller30, thereby resulting in the memory controller30controlling data storage as well as performing data processing operations. However, it should be appreciated that the depicted embodiment is merely intended to be illustrative and not limiting. In particular, in other embodiments, a memory module24may be implemented with memory processing circuitry38separate (e.g., distinct) from its memory controller30, for example, implemented via one or more dedicated application specific integrated circuits (ASICs), one or more dedicated field programmable logic arrays (FPGAs), or both.

In any case, to facilitate performing data processing operations using memory processing circuitry38, data may be formatted as data objects40. In some embodiments, different data objects40may include different types of data. For example, a first data object40A may include image data corresponding with video content while a Kth data object40K includes virtual machine data. Additionally or alternatively, different data objects40may include data corresponding with different entities. For example, the first data object40A may include image data corresponding with first video content while the Kth data object40K includes image data corresponding with second (e.g., different) video content. As a further example, the first data object40A may include virtual machine data corresponding with a first client device12while the Kth data object40K includes virtual machine data corresponding with a second (e.g., different) client device12. Since data processing is generally data dependent, in addition to data, data objects40may indicate context of the data to facilitate processing using memory processing circuitry, for example, instead of using host processing circuitry22.

To help illustrate, an example of a data object40is shown inFIG. 3. As in the depicted embodiment, a data object40may include metadata42concatenated in front of or prepended to a data block44. It should be appreciated that the depicted embodiment is merely intended to be illustrative and not limiting. For example, in other embodiments, the data block44may be concatenated in front of the metadata42or otherwise associated. For example, metadata42may be appended to or multiplexed with (e.g., interleaved with data of) data block44. Additionally or alternatively, the data object40may include other types of metadata42.

In any case, in some embodiments, a data block44may include related data, for example, that is expected to be processed together. As an illustrative example, the data block44may include the image data corresponding with specific video content. As a further example, the data block44may include virtual machine data corresponding with a specific client device12. Other types of related data may similarly be grouped into data blocks44.

To facilitate processing of a data block44using memory processing circuitry38, corresponding metadata42may indicate context of the data block44. In some embodiments, the metadata42may include validity metadata42A, which is indicative of validity of the data block44. For example, the validity metadata42A may include a validity bit, which indicates that the data block44is valid when set (e.g., “1” bit) and invalid when not set (e.g., “0” bit). Additionally or alternatively, the validity metadata42A may facilitate detecting whether the data block44is valid and/or correcting the data block44when invalid. For example, the validity metadata42A may include one or more error checking codes, such as an inversion bit, a poison bit, a parity bit, an error-detecting code (EDC), an error-correcting code (ECC), a Bose-Chaudhuri-Hocquenghem (BCH) code, a message authentication code (MAC), a cyclic redundancy check (CRC) code, or any combination thereof. In other words, metadata42included in a data object40may enable processing circuitry, such as memory processing circuitry38and/or a service processor27, to determine validity of its associated data block44.

Additionally, in some embodiments, the metadata42may include tag metadata42B, which indicates identifying parameters of the data block44. For example, the tag metadata42B may indicate that the data block44includes image data and/or that data block44corresponds with specific video content. Additionally or alternatively, the tag metadata42B may indicate that the data block44is virtual machine data and/or that the data block44corresponds with a specific client device12. In other words, metadata42included in a data object40may enable processing circuitry, such as memory processing circuitry38and/or a service processor27, to identify data included in its associated data block44. In fact, in some embodiments, tag metadata42B may facilitate correcting a data object40indicated as invalid by its validity metadata42A, for example, by enabling a redundant data object40to be identified. Metadata may thus include multiple portions, which may be referred to a first portion and a second portion.

An example of a process46for generating a data object40is described inFIG. 4. Generally, the process46includes analyzing data (process block48), grouping related data into a data block (process block50), determining metadata based on context of the data block (process block52), and associating the metadata and the data block as a data object (process block54). In some embodiments, the process46may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as host processing circuitry22and/or memory processing circuitry38. Additionally or alternatively, the process46may be implemented at least in part based on circuit connections formed in the processing circuitry (e.g., host processing circuitry22and/or memory processing circuitry38).

Accordingly, in some embodiments, processing circuitry (e.g., host processing circuitry22and/or memory processing circuitry38) may analyze data to be stored in a memory module24(process block48). For example, the processing circuitry may analyze the data to determine processing interrelationships. Thus, based at least in part on its analysis, the processing circuitry may group related data into a data block44(process block50). For example, the processing circuitry may group data expected to be processed together into a data block44.

Additionally, based at least in part on its analysis of data included in the data block44, the processing circuitry may determine context of the data block44, which may be indicated using metadata42(process block52). For example, the processing circuitry may analyze the data block44to determine identifying parameters, such as type of data included in the data block44and/or entity associated with the data block44, and indicate the identifying parameters via tag metadata42B. Additionally or alternatively, the processing circuitry may analyze the data block44by performing one or more cryptographic hash operations (e.g., functions) on the data block44to determine corresponding error checking codes, such as a BCH code and/or a CRC code, and indicate the error checking codes via validity metadata42A.

To produce a corresponding data object40, the processing circuitry may associate the metadata42and the data block44(process block54). In some embodiments, the processing circuitry may associate the metadata42and the data block44by concatenating the metadata42with the data block44. To facilitate identifying the metadata42from the data block44, in some embodiments, different data blocks44may be formatted such that each includes specific bit positions reserved for metadata42, for example, even when they include different types of metadata42and/or different types of data blocks44.

In any case, after the data object40is produced, the processing circuitry may output the data object40for storage in a memory device26implemented on the memory module24. For example, when produced by host processing circuitry22, the host processing circuitry22may communicate the data object40to the memory module24via the system bus25and the memory module24may store the data object40in one or more of its memory devices26. When produced by memory processing circuitry38, a memory controller30of the memory module24may output the data object40via the internal bus37for storage in one or more of the memory devices26. In any case, as described above, storing data as data blocks44in a memory module24may enable the memory module24to perform data processing operations via its memory processing circuitry38, which, at least in some instances, may facilitate improving operational efficiency of computing systems10.

To help illustrate, an example of a process56for operating a memory module24is described inFIG. 5. Generally, the process56includes identifying a data object (process block58), determining context of a data block included in the data object based on metadata (process block60), and performing a data processing operation on the data block based on its context (process block62). In some embodiments, the process56may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as a memory controller30and/or memory processing circuitry38. Additionally or alternatively, the process56may be implemented at least in part based on circuit connections formed in a memory controller30and/or memory processing circuitry38.

Accordingly, in some embodiments, a memory controller30implemented in a memory module24may identify a data object40, for example, from data stored in the memory module24, data retrieved from a memory device26implemented in the memory module24, and/or data received from host processing circuitry22for storage in the memory module24(process block58). In other words, when it receives data (e.g., for storage and/or from a memory device26), the memory controller30may determine whether the data includes one or more data objects40. Additionally or alternatively, the memory controller30may search data stored in the memory module24to identify one or more data objects40.

In some embodiments, the memory controller30distinguishes a data object40from data generally based at least in part on whether metadata42is included. To facilitate identifying metadata42, in some embodiments, specific bit positions (e.g.,256most significant bits) may be reserved for metadata42in each data object40. Accordingly, in such embodiments, the memory controller30may parse the specific bit positions in a section of data to determine whether metadata42is included and, thus, whether the section of data is formatted as a data object40.

Additionally or alternatively, the memory controller30may receive an indication (e.g., control signal) of whether specific data is included in a data object40. For example, when the host processing circuitry22outputs data for storage, the host processing circuitry22may output a control signal along with the data that indicates whether the data is included in a data object40. Similarly, when host processing circuitry22requests access to stored data, the host processing circuitry22may output a control signal along with the memory access request that indicates whether the requested data is included in a data object40.

In any case, when a data object40is identified, the memory controller30may determine context of data included in a data block44of the data object40based at least in part on associated metadata42(process block60). As described above, metadata42associated with a data block44in a data object40may indicate context of data included in the data block44and, in some embodiments, may be indicated at specific bit positions in the data object40. To facilitate properly interpreting the metadata42, in some embodiments, specific bit positions in the metadata42may be reserved (e.g., allocated) for specific types of metadata42.

For example, in the metadata42, bit position 0 to bit position N may be reserved for tag metadata42B and bit position N+1 to the most significant bit position may be reserved for validity metadata42A. Moreover, the bit positions reserved for tag metadata42B may further divided between tag metadata42B that indicates type of data included in a corresponding data block44and tag metadata42B that indicates entity associated with the corresponding data block44. Additionally or alternatively, the bit positions reserved for validity metadata42A may be further divided between different types of error checking codes. In any case, by parsing the corresponding reserved bit positions in the data object40, the memory controller30may determine what metadata42is included and, thus, context (e.g., identifying parameters and/or error checking codes) of the data block44.

Based at least in part on its context, memory processing circuitry38implemented in the memory module24may perform data processing operations on the data block44(process block62). For example, based at least in part on validity metadata42A, the memory processing circuitry38may detect and/or correct errors occurring in the data block44. Additionally, based at least in part on tag metadata42B, one or more data objects40that each includes a targeted type of data may be identified, thereby enabling the memory processing circuitry38to perform a data search operation on the identified data objects40. Furthermore, based at least in part on tag metadata42B that indicates type of data included in the data block44, the memory processing circuitry38may pre-process data before output to the host processing circuitry22and/or post-process data received from the host processing circuitry22for storage, which may facilitate freeing the host processing circuitry22for other tasks.

In this manner, the memory processing circuitry38is able to perform data dependent processing, which, at least in some instances, may facilitate improving operational efficiency, operational reliability, and/or data storage efficiency of computing systems10. Since data processing is generally data dependent, the specific data processing operations performed by memory processing circuitry38may vary based on data included in data objects40. Moreover, as described above, the techniques described in the present disclosure may be applied to various different types of data, for example, ranging from virtual machine data to image data corresponding with video content. To help illustrate the wide applicability, example use cases enabled by the techniques present herein are described inFIGS. 6-9.

In particular, an example of a process64for operating a memory module24to post-process data is described inFIG. 6. Generally, the process64includes receiving a data object from host processing circuitry (process block66), determining that the data block includes image data based on metadata (process block68), compressing the data block (process block70), and storing the metadata and compressed data block in a memory device (process block72). In some embodiments, the process64may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as a memory controller30and/or memory processing circuitry38. Additionally or alternatively, the process64may be implemented at least in part based on circuit connections formed in a memory controller30and/or memory processing circuitry38.

Accordingly, in some embodiments, a memory controller30that controls data storage in a memory module24may receive via a system bus25a data object40for storage in the memory module24, for example, from host processing circuitry22and/or a network interface16(process block66). As described above, a data object40may include a data block44and metadata42, which indicates context (e.g., type of data) of the data block44. Thus, based at least in part on its metadata42, the memory controller30may determine whether the received data block44includes image data.

To facilitate improving storage efficiency while enabling the host processing circuitry22to process decoded (e.g., de-compressed) image data, memory processing circuitry38implemented in the memory module24may perform a data compression (e.g., encoding) operation on the data block44(process block70) before the memory controller30stores the data object40in one or more memory devices26of the memory module24(process block72). In some embodiments, the memory processing circuitry38may prediction encode the image data included in the data block44using inter-prediction techniques and/or intra-prediction techniques, for example, in accordance with Advanced Video Coding (AVC) and/or High Efficiency Video Coding (HEVC). Additionally or alternatively, the memory processing circuitry38may entropy encode the image data included in the data block44, for example, using context-adaptive binary arithmetic coding (CABAC) and/or context-adaptive variable-length coding (CAVLC). In any case, by compressing its image data, size of the compressed data block44may be reduced, for example, compared to the received (e.g., un-compressed) data block44.

In this manner, memory processing circuitry38implemented in a memory module24may post-process data by performing data processing (e.g., encoding or compression) operations on the data before storage, which, at least in some instances, may facilitate offloading processing performed by host processing circuitry22and, thus, improving operational efficiency of a corresponding computing system10. To facilitate subsequent retrieval, in some embodiments, the memory controller30may update a memory address mapping with the physical memory address at which the data object40is stored, for example, such that the physical memory address is associated with a virtual memory address referenced by host processing circuitry22. Additionally, in some embodiments, the memory controller30may update data access parameters (e.g., a write time parameter, a last accessed parameter, and/or an access count parameter) associated with the data object40. As will be described in more detail below, data access parameters may be analyzed to predict when a data object40will be subsequently requested, thereby enabling memory processing circuitry38to preemptively pre-process the data object40, which, at least in some instances, may facilitate further improving operational efficiency of the corresponding computing system10.

To help illustrate, an example of a process74for operating a memory module24to pre-process data is described inFIG. 7. Generally, the process74includes retrieving a data object from a memory device (process block76), determining that a data block includes image data based on metadata (process block78), de-compressing the data block (process block80), and outputting the metadata and de-compressed data block to host processing circuitry (process block82). In some embodiments, the process74may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as a memory controller30and/or memory processing circuitry38. Additionally or alternatively, the process74may be implemented at least in part based on circuit connections formed in a memory controller30and/or memory processing circuitry38.

Accordingly, in some embodiments, a memory controller30may retrieve a data object40from a memory device26implemented on a memory module24(process block76). In some embodiments, the memory controller30may retrieve the data object40from the memory device26when the memory module24receives a memory access request, for example, from host processing circuitry22and/or a network interface16that identifies the data object40via its virtual memory address. In such embodiments, the memory controller30may determine actual storage location of the target data object40in the memory module24, for example, using a memory address mapping that associates the virtual memory address to its physical memory address.

Additionally or alternatively, the memory controller30may preemptively retrieve the data object40, for example, before access to the data object40is actually requested. Since data access patterns are often somewhat repetitive (e.g., cyclical), in some embodiments, the memory controller30may analyze data access parameters corresponding with one or more data blocks44to determine previous data access patterns and predict future data access patterns based at least in part on the previous data access patterns, for example, using machine learning techniques. In this manner, the memory controller30may predict when the data object40will actually be requested and retrieve the data object40at least a processing duration beforehand. Since data processing is generally data dependent and duration used to perform different data processing operations may vary, in some embodiments, the memory controller30may predictively set the processing duration based on various factors, such as processing duration of previously performed data processing operations, size of the predicted data block44, type of data indicated by corresponding metadata42as being included in the predicted data block44, and/or the like.

In any case, as described above, a data object40may include a data block44and metadata42, which indicates context (e.g., type of data) of the data block44. Thus, based at least in part on its metadata42, the memory controller30may determine whether the retrieved data block44includes image data. As described above, in some embodiments, image data may be compressed before storage to facilitate improving data storage efficiency provided by a memory module24. However, host processing circuitry22may be expected to process de-compressed image data.

Thus, to facilitate improving storage efficiency while enabling the host processing circuitry22to process decoded (e.g., de-compressed) image data, the memory processing circuitry38may perform a data de-compression (e.g., decoding) operation on the data block44(process block80) before the memory controller30outputs the data object40. Generally, data de-compression operations may be the opposite (e.g. inverse or reverse) of data compression operations. In other words, in some embodiments, the memory processing circuitry38may entropy decode the image data included in the data block44, for example, using CABAC decoding and/or CAVLC decoding. Additionally or alternatively, the memory processing circuitry38may decode (e.g., reconstruct) the image data included in the data block44by reversing the inter-prediction techniques and/or intra-prediction techniques, for example, in accordance with Advanced Video Coding (AVC) and/or High Efficiency Video Coding (HEVC). In any case, after the data object is actually requested and its data block44is de-compressed, the memory module24output the data object40via a system bus25, for example, to the host processing circuitry22and/or the network interface16to enable further processing without first performing a de-compression (e.g., decoding) process.

In this manner, memory processing circuitry38implemented in a memory module24may pre-process data by performing data processing (e.g., decoding and/or de-compression) operations on the data before output, which, at least in some instances, may facilitate offloading processing performed by host processing circuitry22and, thus, improving operational efficiency of a corresponding computing system10. In addition to offloading (e.g., reducing) processing performed by host processing circuitry22, the techniques of the present disclosure may facilitate improving operational efficiency by leveraging data communication efficiency provided by internal buses37implemented on a memory module24. In particular, data communication efficiency (e.g., power consumption, speed, and/or bandwidth) provided by an internal bus37is generally better than data communication efficiency provided by an external bus, such as a system bus25coupled between the memory module24and the host processing circuitry22. Thus, reducing data communication on the system bus25may facilitate improving operational efficiency—particularly for data intensive operations.

To help illustrate, an example of a process84for operating a memory module24to perform a data intensive (e.g., search) operation is described inFIG. 8. Generally, the process84includes identifying targeted data objects based on metadata (process block86), performing a data search operation on the targeted data objects (process block88), and providing search results to host processing circuitry (process block90). In some embodiments, the process84may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as a memory controller30and/or memory processing circuitry38. Additionally or alternatively, the process84may be implemented at least in part based on circuit connections formed in a memory controller30and/or memory processing circuitry38.

Accordingly, in some embodiments, a memory controller30implemented on a memory module24may identify one or more data objects40targeted for a data search operation based at least in part on corresponding metadata42(process block86). In some embodiments, the data search operation may be initiated based on an explicit instruction received from host processing circuitry22, for example, when the host processing circuitry22receives a corresponding user input that requests performance of one or more data processing operations including the data search operation. Additionally or alternatively, the memory module24may autonomously initiate the data search operation, for example, based at least in part on a prediction that performance of the data search operation will subsequently be requested.

As described above, in some embodiments, a memory controller30may analyze data access parameters to determine previous data access patterns and predict future operation accordingly, for example, using machine learning techniques. In this manner, the memory controller30may predict when performance of the data search operation and/or results of the data search will subsequently be requested and autonomously initiate the data search operation at least a processing (e.g., expected search) duration beforehand. Since search duration is generally dependent on amount of data searched (e.g., non-deterministic), in some embodiments, the memory controller30may predictively set the processing duration based on various factors, such as search duration of previously performed data search operations, certainty that the data search operation will actually be requested, amount of data stored in the memory module24, number of data objects40stored in the memory module24, size of each data object40, and/or the like.

In any case, data targeted for identification by a data search operation often occurs within a specific one or more types of data. For example, the result of a data search operation targeting a picture is generally found in image data. Additionally, the result of a data search operation targeting an executable instruction is generally found at least in virtual machine data.

Since search duration is generally dependent on amount of data searched, in some embodiments, the memory controller30may facilitate improving search efficiency by narrowing the data search operation to one or more types of data in which targeted data is expected to be found. As described above, in some embodiments, metadata42included in a data object40may indicate type of data included in a corresponding data block44. Thus, by parsing metadata42of data objects40stored in memory devices26, the memory controller30may identify and, thus, retrieve one or more data objects40that each includes at least one of the targeted types of data, for example, into an internal buffer of the memory controller30.

Memory processing circuitry38may then perform the data search operation by searching the data objects40targeted by the data search operation (process block88). In some embodiments, the memory processing circuitry38search for the targeted data by parsing the data block44of each of the targeted data objects40. In particular, to facilitate identifying the targeted data, the memory processing circuitry38may search the data block44based at least in part on one or more search criteria (e.g., rules) associated with the data search operation.

After actually requested, the memory controller30may output results of the data search operation via a system bus25, for example, to host processing circuitry22and/or a network interface16(process block90). When targeted data is actually found, the results of the data search operation may identify and/or include one or more data objects40, which each includes the targeted data object. On the other hand, when the targeted data is not found, the results of the data search operation may indicate that the targeted data object is not stored in the memory module24and/or that allotted search duration has expired before the targeted data could be found. In any case, size of the data search operation results is generally less than total size of the targeted data objects40—let alone total size of all the data objects40stored in the memory module24.

In other words, although the same data objects40may be retrieved from the memory devices26and, thus, communicated via internal buses37regardless of where a data search operation is performed, using memory processing circuitry38to perform the data search operation may facilitate reducing number of data objects40output via an external bus, such as a system bus25. In this manner, performing data search operations and/or other data intensive operations using memory processing circuitry38implemented in a memory module24may facilitate reducing amount of external communication, which, at least in some instances, may facilitate leveraging communication efficiency provided by its internal buses37to improve operational efficiency of a corresponding computing system10. In addition to improving operational efficiency, the techniques described in the present disclosure may facilitate improving operational reliability of computing systems10.

To help illustrate, an example of a process92for operating a computing system10is described inFIG. 9. Generally, the process92includes detecting an error in a data object based on metadata (process block94), identifying a redundant data object based on metadata (process block96), and correcting the erroneous data object (process block98). In some embodiments, the process92may be implemented at least in part based on circuit connections formed in memory processing circuitry38. Additionally or alternatively, the process92may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as a memory device26, using processing circuitry, such as memory processing circuitry38and/or a service processor27.

Accordingly, in some embodiments, processing circuitry (e.g., memory processing circuitry38and/or a service processor27) may detect whether an error has occurred in a data object40based at least in part on its metadata42(process block94). In some embodiments, memory processing circuitry38implemented in a memory module24may autonomously initiate the error detecting process. For example, the memory processing circuitry38may opportunistically initiate the error detecting process when the memory processing circuitry38predicts that the memory module24will not receive requests within a threshold duration. Additionally or alternatively, the error detecting process may be initiated externally. For example, a service processor27may initiate the error detecting process when it detects that at least a portion of a corresponding computing system10has lost power and/or is otherwise faulty.

In any case, as described above, metadata42of a data object40may include validity metadata42A, which is indicative of whether a corresponding data block44is valid (e.g., does not contain errors). For example, when the validity metadata42A includes a validity bit, the processing circuitry may determine that the data block44is valid when the validity bit is set (e.g., a “1”) and invalid when the validity bit is not set (e.g., “0” bit). Additionally or alternatively, when the validity metadata42A includes an error checking code, the processing circuitry may perform a cryptographic hash operation on the data block44and determine whether the data block44is valid based at least in part on whether the result of the cryptographic has operation matches the error checking code.

When an invalid data object40is detected, the processing circuitry may identify a redundant data object40based at least in part on metadata42of the invalid data object40and/or metadata42of the redundant data object40(process block96). As described above, metadata42of a data object40may include tag metadata42B that indicates identifying parameters of a corresponding data block44. Thus, in some embodiments, the processing circuitry may identify a data object40as the redundant data object40when its tag metadata42B indicates the same identifying parameters as the tag metadata42B of the invalid data object40, for example, such that both include the same type of data and are associated with the same entity. Additionally or alternatively, metadata42included in a data object40may explicitly indicate a corresponding redundant data object40.

In any case, when an invalid data object40is detected, the processing circuitry may correct the invalid data object40(process block98). To correct an error, in some embodiments, the processing circuitry may perform an error correcting process on the invalid data object40and/or the redundant data object40, for example, based at least in part on an error-correcting code (ECC) included in metadata42. Additionally or alternatively, when the processing circuitry determines that the redundant data object40is valid (e.g., based on its validity metadata42A), the processing circuitry may correct the error by overwriting at least the data block44of the invalid data object40with the data block44of the redundant data object40. In any case, by correcting errors in this manner, likelihood of a memory module24outputting an invalid data object40may be reduced, which, at least in some instances, may facilitate improving operational reliability of a corresponding computing system10.

By implementing and/or operating a memory module in accordance with the techniques described herein, a memory module may perform data processing operations that facilitate offloading (e.g., reducing) processing performed by main (e.g., host) processing circuitry of a computing system. For example, dedicated (e.g., memory) processing circuitry implemented in a memory module may pre-process data before output to the main processing circuitry and/or post-process data received from the main processing circuitry before storage in a memory device of the memory module. With this understanding, the technical effects of the present disclosure include improving operational efficiency, operational reliability, and/or data storage efficiency provided by memory modules and, thus, computing systems in which the memory modules are implemented.