Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing

A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.

TECHNICAL FIELD

The present invention relates to a bidirectional nonvolatile memory cell having a charge trapping layer in a trench, and an array of such cells, and a method of manufacturing, and more particularly, wherein the cell can store multi-bits.

BACKGROUND OF THE INVENTION

Nonvolatile memory cells having a charge trapping layer to store charges is well known in the art. See for example, U.S. Pat. No. 6,940,125 assigned to the present assignee, whose disclosure is incorporated by reference in its entirety herein. Bi-directional cells made from trenches in a substrate are also well known in the art. See U.S. Pat. Nos. 6,940,125 6,861,315 and 6,936,883. Finally, the use of silicon nanocrystals (Si-nc) embedded in SiN as a charge trapping layer is also well known in the art. See Choi S., et al. “High Density Silicon Nanocrystal Embedded in SiN Prepared by Low Energy (<500 eV) SiH4plasma Immersion Ion Implantation for Non-volatile Memory Applications” IEDM August, 2005.

It is an object of the present invention to provide a bi-directional non-volatile memory cell (as well as an array and a method of making the array) using a charge trapping layer to store multi-bits in each cell.

SUMMARY OF THE INVENTION

Accordingly, in the present invention, a non-volatile memory cell comprises a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface. A first trench is in the substrate extending in a first direction. The first trench has a sidewall and a bottom. A first region of a second conductivity type is in the bottom of the first trench. A second trench is in the substrate extending in the first direction parallel to and spaced apart from the first trench by a section along the planar surface. The second trench also has a sidewall and a bottom. A second region of the second conductivity type is in the bottom of the second trench. A channel region connects the first and second regions for the conduction of charges. The channel region has three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; and a third portion along the section between the first and second trenches, near the planar surface. A first charge trapping layer is spaced apart from the first portion of the channel region and is for trapping charges. A second charge trapping layer is spaced apart from the second portion of the channel region and is for trapping charges. A dielectric layer is spaced apart from the third portion of the channel region. A first control gate is in the first trench extending in the first direction, capacitively coupled to the first charge trapping layer and to the first region. A second control gate is in the second trench extending in the first direction, capacitively coupled to the second charge trapping layer and to the second region. A third control gate is coupled to the dielectric layer for controlling the conduction of charges in the third portion of the channel region.

The present invention also relates to an array of the foregoing described nonvolatile memory cells. Finally, the present invention relates to a method of manufacturing an array of nonvolatile memory cells.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1, there is shown a cross-sectional view of a first embodiment of a nonvolatile memory cell10of the present invention.

The cell10comprises a substantially single crystalline semiconductor substrate12, having a planar surface14. The substrate12is of a first conductivity type, such as P type. A first trench16and a second trench18are formed in the substrate12with each of the trenches16and18being formed substantially perpendicular to the surface14. The trench16has a first sidewall20a, and a second sidewall20band a bottom22. The trench18has a first sidewall24aand a second sidewall24band a bottom26. A region30of a second conductivity type, such as N, is at the bottom22of the first trench16. A region32of the second conductivity type, such as N, is at the bottom26of the second trench18. A channel connects the region30to the region32, and consists of three parts: along the second sidewall20bof the first trench16, along the planar surface14separating the first trench16from the second trench18, and along the first sidewall24aof the second trench18.

Along the first sidewall20a, the second sidewall20bof the first trench16and along the first sidewall24aand the second sidewall24bof the second trench18is a charge trapping layer50(shown inFIGS. 4O-1). As is well known, the charge trapping layer50can be made from Si-nc in SiN or silicon nitride (SiN) or nanocrystal. The charge trapping layer50is separated and insulated from the substrate12by a bottom insulator52, such as silicon oxide (shown inFIGS. 4O-1). Within each of the first trench16and the second trench18is a control gate40and42, respectively. The control gates40and42are insulated from the charge trapping layer50by a top insulator54. In addition, the control gates40and42are insulated from the regions30and32, along the bottom of each of the first and second trenches16and18. The control gates40and42are formed such that the top portion thereof, exceeds the top of the planar surface14by an amount shown as60. An insulating layer70is formed across the top surface14and the top level of the control gates40and42. A top gate80is on the insulating layer70.

In the operation of the cell10, to erase the cell10, there are two possible modes of operation. In a first mode of operation, charges trapped in the charge trapping layer50tunnel by the mechanism of Fowler-Nordheim tunneling through the top insulator54to the control gates40and42respectively. As an example, this can occur by applying the following voltages: 0 volts to the regions30and32and to the top gate80. A high positive voltage on the order of +8 to +12 volts is applied to the control gates40and42. Negative charges trapped in the charge trapping layer50are attracted by the positive voltages from the control gates40and42and tunnel through Fowler-Nordheim tunneling, through the top insulator54into the control gates40and42. In a second mode of operation, charges trapped in the charge trapping layer50tunnel by the mechanism of Fowler-Nordheim tunneling through the lower insulator52to the substrate12. As an example, this can occur by applying the following voltages: 0 volts to the regions30and32and to the top gate80. A high negative voltage on the order of −8 to −12 volts is applied to the control gates40and42. Negative charges trapped in the charge trapping layer50are repelled by the negative voltages from the control gates40and42and tunnel through Fowler-Nordheim tunneling, through the lower insulator52into the substrate12.

To program the cell10, there are a number possible modes of operation. In a first mode, which is by source side injection and is useful for high speed programming, the following voltages are applied. A positive voltage of +1.5 to 3.0 volts is applied to the top gate80, sufficient to turn on the second channel region under the planar surface14between the trenches16and18. The following voltages are applied to the second regions30and32respectively, 0 volts, and +5 volts, sufficient to turn on the channel region. A positive voltage of +2 volts is applied to the control gate40, sufficient to turn on the channel region along the sidewall20b, and +5 volts is applied to the control gate42. As the channel region is turned on, electrons traverse the channel region from the second region30along the first sidewall20balong the surface14between the trenches16and18, and are then attracted by the positive voltage +5 from the control gate42, and by the fact that they have high energy from the large positive voltage (+5v) applied to the second region32. This causes the electrons in the channel near the top surface14to be injected onto the charge trapping layer50. Thus, in this mode, the portion of the charge trapping layer50near the surface14is programmed.

In a second mode of programming, which is by channel hot electron injection, the same voltages as the first mode are applied except the voltage to the second region32is reduced to +2 volts. In this second mode, by the time the electrons reach the channel region, near the top surface14, they do not have sufficient acceleration (caused by the lower attractive force of the voltage applied to the second region32) to be injected onto the charge trapping layer50. Instead, the electrons continue to traverse along the sidewall24aand as they near the second region32, they have sufficient acceleration to be injected onto the charge trapping layer50, near the second region32. Thus, in this mode, the portion of the charge trapping layer50near the bottom of the trench is programmed.

In yet another mode of programming, which is by channel hot electron injection near the top surface14, the following voltages are applied: 0 volts is applied to the second region32, +2 volts is applied to the second region30, +3 volts is applied to the control gate40, +6 volts is applied to the control gate42, and +1.5 to 3.0 volts is applied to the top gate80. Electrons traverse the channel region from the second region32to the second region30, along the sidewall24a. As the electrons near the top surface14of the substrate12, the strong attractive force of the +6 volts on the control gate42, as opposed to the weaker attractive force of +3 volts on the control gate40causes the electrons to be injected onto the charge trapping layer50along the sidewall24anear the top planar surface14.

In this manner, it is possible to program two bits for the charge trapping layer50along the sidewall of each trench, for a total of 4 bits per cell.

In yet another mode of programming, the following voltages can be applied. +4 volts to the second region30and +2 volts to the second region32. +5 volts to the top gate80. +5 volts to the control gate40. −8 volts to the control gate42. In this mode, which is a low power mode of operation, because a negative voltage is applied to the control gate42, the channel would not turn on. However, if +5 volts is applied to the top gate80, and +5 volts is applied to the control gate40approximately +4 volts would be transferred from the left portion of the trench16to the right corner of the top planar surface14, near trench18. Since control gate42is supplied with −8 volts, approximately +12 volts differential exists between the substrate12and the control gate42causing Fowler-Nordheim tunneling of electrons from the trapping layer50to the substrate12.

To read, the cell10, it depends on whether the cell10is programmed with one (1) bit in the charge trapping layer50along each of the sidewalls20band24aor two (2) bits along each of the sidewalls20band24a. Assume that the cell10is programmed with only 2 bits in total, i.e. one bit in the charge trapping layer along each of the sidewalls20band24a. Then the following voltages are applied: +1.5-3.0 volts on the top gate80, +2-3 volts on the control gate40, 0 volts on the control gate42, +2-3v. on the second region30, and 0V on the second region32. Because there is 0 volts applied to the control gate42, whether the channel along that trench18is turned on or not is controlled by the trapping layer50along the sidewall24a. The electron flow detected at the second region32is determinative of the charges trapped in the charge trapping layer50along the sidewall24a. Another read method would be to force a read current, e.g. 100 nA at the second region32while a voltage, such as +2-3 volts is upplied at the first region, and then detect the read voltage Vr, at the second region32. To read the charge trapping layer50along the sidewall20bof the cell10, the voltages are reversed.

In the event two bits are programmed in the charge trapping layer50along each of the sidewalls of the cell10, then two read operations are necessary to detect the charges trapped near the top (near the planar surface14) and the bottom (near the second region) of the charge trapping layer along each of the sidewalls. Thus, four read operations are necessary to read the cell10in total. In a first read operation, the following voltages are applied: +1.5-3.0 volts applied to the top gate80, +2 volts applied to the second region30, 0 volts applied to the second region32, +2 volts applied to the control gate40, and 0 volts applied to the control gate42. The channel is turned on; the voltage on the control gate40is sufficient to turn on the channel region irrespective of the charges trapped in its associated charge trapping layer50. Electrons traverse the channel from the second region32to the second region30. The amount of electron flow detected at the second region30is determined primarily by the charges trapped in the trapping layer50along the sidewall24a, near the bottom of the trench or near the second region32. The charges trapped along the sidewall24ain the trapping layer50near the top surface14in the trench18are shielded by the depletion region created by the +2 volts applied to the control gate40to the top right hand corner of the planar surface14and the trench18.

A second read operation is then performed. The voltages applied in the second read operation is as follows: +1.5-3.0 volts applied to the top gate80, +2 volts applied to the second region32, 0 volts applied to the second region30, +2 volts applied to the control gate40, and 0 volts applied to the control gate42. The channel is turned on; the voltage on the control gate40is sufficient to turn on the channel region irrespective of the charges trapped in its associated charge trapping layer50. Electrons traverse the channel from the second region30to the second region32. The amount of electron flow detected at the second region32is determined by the charges trapped in the trapping layer50along the sidewall24a. However, because a positive voltage is applied to the second region32, a depletion region is formed about the second region32which shields the threshold voltage caused by the electrons trapped in the charging layer50near the bottom of the trench18or near the second region32. Thus, in this second read, the electron flow detected is primarily caused by the electrons trapped in the trapping layer50near the planar surface14along the sidewall24a. For the third and fourth read operations, the voltages are the same as that for the first and second read operations, except the voltages applied to the control gates40and42and second regions30and32are reversed, thereby determining the state of charge trapping in the trapping layer50near the bottom for the trench16along the sidewall20b, and near the top of the trench16near the planar surface14.

Referring toFIG. 2there is shown a schematic cross sectional view of another memory cell110of the present invention. The memory cell110is similar to the memory cell10, except the height of the control gate40/42in each of the trenches16/18is such that the top of the control gate40/42does not protrude above the planar surface14. As a result, the insulating layer70on the trenches16/18may be “flat”. Because of this flat topology, a simpler process may be used to manufacture the cell110or an array of such cells110. However, because the trenches16/18do not “protrude” above the planar surface14, the height of the control gates40/42of the memory cell110is less than the height of the control gates40/42of the memory cell10. As a result, the cell cannot store a bit in the trapping layer50near the top planar surface14; thereby providing for only the storage of two bits per cell110. In addition, programming of the cell110can occur only through the mechanism of source side injection or channel hot electron injection.

Referring toFIG. 3there is shown a schematic diagram of a memory array90comprising of an array of either memory cells10or110of the present invention. The plurality of memory cells10or110are laid out in a plurality of rows and columns, as indicated. It should be noted that the term “row” and “column” are just for reference, and may be interchangeably used. For cells10or110that are arranged in the same row, e.g. row M, cells to one side share a common second region32, a common control gate42(in a common trench18), and cells to another side share a common second region30, and a common control gate30(in a common trench16). In addition, the top gate80(shown as WLn) extends and connects to each of the cells in the same row. For cells that are arranged in the same column, e.g. column K, the cells share a common control gate30/32and a common trench16/18, and a common second region30/32. The second regions are shown as “lbln”. As will be shown, the array90is made such that there is no isolation, such as STI, between adjacent rows of memory cells10or110. Thus, the array90is an STI free memory array which reduces defect density.

Referring toFIGS. 4A-1and4A-2there is shown a sequence of steps to make the array90of memory cells10or110of the present invention.FIGS. 4A-1through4AH-1show the sequence of steps to make the memory array portion of the present invention, whereasFIGS. 4A-2through4AH-2show the sequence of steps to make the peripheral circuits for the memory array portion of the present invention.

An exemplary mask sequence for the manufacturing of the array90is as follows:

In the first step of the method of the present invention, a layer of pad oxide120of approximately 110 angstroms, is grown in the substrate12. It should be noted that the dimensions disclosed herein are examples only and that other dimensions can be used depending on the lithographic node used. A layer of polysilicon120of approximately 200 angstroms is then formed on the layer110. A layer of Silicon nitride140of approximately 1400 angstroms is then formed on the layer of polysilicon130. A layer of TEOS deposited silicon dioxide150of approximately 300 angstroms is then formed on the layer140. Finally, a layer of SiON160of approximately 480 angstroms is then formed on the layer150. The layers120,130,140,150and160can be formed by conventional means.

In the next step, shown inFIG. 4B, a photoresist layer170is then applied on the SiON160. A masking step is performed in the peripheral portion of the array90, as shown inFIGS. 4B-2, creating an opening in the peripheral portion.

In the next step, the opening in the peripheral portion of the array90is used to etch through the layers:160,150,140,130and120and into the substrate12, as shown inFIG. 4C-2. The photoresist170is then removed.

The opening in the periphery is then extended into the substrate12forming a trench of approximately 2000-3000 angstroms deep. The layer160of SiON is removed. The resultant structure is shown inFIG. 4D.

An oxide dip (DHF dip) is performed on the structure The resultant structure is shown inFIG. 4E.

A layer of sacrificial oxide is deposited on the structure shown inFIG. 4E, followed by an oxide dip (DHF dip) step. This is followed by a HDP (High Density Plasma) deposition of silicon nitride layer. The resultant structure is then subject to a CMP etch with a selectivity of SiN to silicon oxide. Thus, when the silicon oxide in the trench in the periphery is detected, the CMP stops. The resultant structure is shown inFIG. 4F.

A partial oxide etch is performed on the structure shown inFIG. 4Fto reduce the height of the oxide in the trench (which forms the STI) in the periphery of the array90. The resultant structure is shown inFIG. 4G.

The layer of silicon nitride140is then removed by H3PO4. The layer of polysilicon130is removed by APM (Ammonium Peroxide Mixture) or dilute HF. The resultant structure is shown inFIG. 4H.

An ion implant process is then performed in the array portion of the memory device10. This implant is on the order of 1E11 to 1E14 cm−2and is for the purpose of preventing punch through. The resultant structure is shown inFIG. 4I.

Silicon nitride180is then deposited on the structure shown inFIG. 4I, after the photoresist is removed. The silicon nitride180deposited is on the order of 500 angstroms. A layer of TEOS oxide190of approximately 800 angstroms is then deposited on the layer180of silicon nitride180. The resultant structure is shown inFIG. 4J.

Photoresist is then applied on the structure shown inFIG. 4J. A masking operation is performed, and portions of the photoresist are exposed and opened, forming a plurality of spaced apart substantially parallel openings that would form trenches in the column direction. Through these openings, the layer of TEOS oxide190, the silicon nitride180and the pad oxide are removed. The photoresist is then removed. The resultant structure is shown inFIG. 4K.

Through the opening, the substrate12is etched to a depth of approximately 500 angstroms, with undercut. As a result of the undercut, the “trench” formed is curvilinearly shaped. The resultant structure is shown inFIG. 4L.

Implant of Boron11with a large angle is then performed on the structure shown inFIG. 4L. The resultant structure is shown inFIG. 4M.

The structure shown inFIG. 4Mis subject to a HF dip process to remove the TEOS oxide180. The resultant structure is shown inFIG. 4N.

A layer of oxide52of approximately 30 angstroms is then deposited on the structure shown inFIG. 4N. The charge trapping layer50is then formed on the oxide layer52. This can be done by deposition of nanocrystals through CVD. Alternatively, the charge trapping layer50can be a silicon rich nitride (SRN) layer, formed by the deposition of SiH4/NH3. A Silicon rich nitride charge trapping layer50is preferable because the control gate40/42can then be made out of polysilicon or metal. Finally, the charge trapping layer50can also be made from silicon nitride. Thereafter another insulating layer54can be formed on the charge trapping layer50. The layer54can be silicon oxide or it can be a composite layer of ONO (silicon oxide/silicon nitride/silicon oxide), of approximately 60 angstroms. The resultant structure is shown inFIG. 40.

The structure shown inFIG. 40is then subject to an implant step of Arsenic or phosphorus on the order of 1E12 to 1E14 cm−2to form the second regions30/32at the bottom of the trenches16/18. Of course the implant dose and species would depend on the process node. The resultant structure is shown inFIG. 4P.

Polysilicon is then deposited everywhere filling the trenches16/18to form the control gates40/42. The polysilicon40/42is subject to in-situ doping to render it conductive. The doping is at 1.5E20, 600 angstroms. The resultant structure is shown inFIG. 4Q.

The structure shown inFIG. 4Qis then subject to a poly etch step. The top of the control gate40/42can be etched such that it is above the planar surface14of the substrate12by the amount60as shown in the first embodiment as shown inFIG. 1, or the etch can proceed such that the top of the control gate40/42is beneath the top planar surface14of the control gate40/42, as in the second embodiment shown inFIG. 2. The resultant structure is shown inFIG. 4R.

The structure shown inFIG. 4Ris then subject to a HDP oxide deposition, whereby silicon dioxide is deposited everywhere. Within each trench, the silicon dioxide is deposited on top of the polysilicon, which forms the control gates40/42. The resultant structure is shown inFIG. 4S.

The structure shown inFIG. 4Sis then subjected to a blanket oxide etch, whereby the silicon dioxide is etched back until the silicon nitride layer180is reached. The resultant structure is shown inFIG. 4T.

The layer of silicon nitride180is then subject to an anisotropic etch until nitride spacers are formed adjacent to each “stack” consisting of silicon dioxide on polysilicon which is in the trench. The resultant structure is shown inFIG. 4U.

Implant to prevent punch through is then made. This can be Boron species at an implant dose of 1E10 to 1E12 cm2. Of course such species and dosage depend on the process node. This is done by applying a photoresist to the peripheral region, while implant is done in the memory region. After the implant step, the photoresist is removed. The resultant structure is shown inFIG. 4V.

The nitride spacers are then removed by either a wet or dry etch so long as it is selective with respect to silicon dioxide. A sacrificial layer of silicon dioxide is deposited. The layer of sacrificial silicon dioxide is etched. The deposition and removal of the sacrificial silicon dioxide causes some silicon dioxide to remain along the sidewall. As a result, the deposition of silicon dioxide by HTO in the step that results in the structure shown inFIG. 4Wresults in additional silicon dioxide being formed in the circled corner area200. The resultant structure is shown inFIG. 4W.

A layer of approximately 150 angstroms of silicon dioxide is then deposited by HTO on the structure shown inFIG. 4W. This forms the gate oxide layer for the top gate80. The resultant structure is shown inFIG. 4X.

Polysilicon is then deposited on the structure shown inFIG. 4Xforming the top gate80. The resultant structure is shown inFIG. 4Y.

The structure is then subject to a lithographic etch using Photoresist and the like to etch the top gate80. The resultant structure is shown inFIG. 4Z.

From the foregoing it can be seen that a high capacity non-volatile memory cell, and array, using trapping charge layer to store charges is disclosed. Further, a method of manufacturing the array is also disclosed. Finally various methods of programming such cell/array in which multi-bits can be stored in a single cell are also disclosed.