Adaptable sense circuitry and method for read-only memory

Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

BACKGROUND

Field

This disclosure relates generally to read-only memory (ROM), and more specifically, to a system and method for sensing data in a ROM.

Related Art

Read-only memories (ROM) are widely used in various computational and data processing systems. With the advancements in semiconductor fabrication processes, higher density and higher performing ROMs are possible. ROMs are generally configured in many sizes and aspect ratios based on the applications associated with the computational and data processing systems. However, significant challenges exist in trying to maintain consistent performance between large ROM arrays and small ROM arrays over a myriad of environmental conditions and system requirements.

DETAILED DESCRIPTION

Generally, there is provided, an apparatus and method for sensing and operating a read-only memory (ROM). Because ROM array sizes and operating conditions may vary widely over a broad range of applications, an adaptable keeper circuit scheme is coupled with a single-ended sense amplifier to deliver optimum performance. Dummy sensing schemes are provided which allow for generation of control signals to adjust sense amplifier keeper circuits. The dummy sensing schemes can correspond to best case and worse case bit line leakage scenarios, for example. By utilizing the control signals generated from the dummy sensing schemes, keeper transistors can be activated to increase keeper strength in sense amplifiers circuits to sense data stored in the ROM.

FIG. 1illustrates, in block diagram form, an exemplary data processing system100according to an embodiment of the present disclosure. In some embodiments, data processing system100may be characterized as a system-on-a-chip (SoC). System100includes system bus102, processor104, memory106, other peripherals108, and ROM110. Processor104, memory106, other peripherals108, and ROM110are each bidirectionally coupled to system bus102by way of respective communication buses.

System bus102can be any type of bus for communicating any type of information such as address, data, instructions, clocks, and control. System bus102provides a communication backbone for communications among the processor104, memory106, other peripherals108, and ROM110.

Processor104may be any type of processor, including circuits for processing, computing, etc., such as a microprocessor (MPU), microcontroller (MCU), digital signal processor (DSP), or other type of processing core. Processing system100may include multiple processors like processor104. Processor104is configured to execute sets of instructions in order to carry out designated tasks.

Memory106may include any type of volatile or non-volatile memory array cells, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash, etc. Processing system100may include multiple memories like memory106or a combination of different memories. For example, processing system100may include a flash memory in addition to memory106.

Other peripherals108of processing system100may include any number of other circuits and functional hardware blocks such as accelerators, timers, counters, communications, interfaces, analog-to-digital converters, digital-to-analog converters, PLLs, and the like for example. Other peripherals108are each bidirectionally coupled to system bus102by way of respective communication buses.

ROM110may be any type of read-only non-volatile memory such as mask programmable memory, one-time programmable memory, fuse programmable memory, and the like. ROM110may be configured in any size and topography suitable for processing system100. ROM110may be characterized as a boot ROM. In some embodiments. ROM110may include look-up table data or other data that would not need to be changed for the life of processing system100.

FIG. 2illustrates, in block diagram form, a more detailed representation of ROM110inFIG. 1according to an embodiment of the present disclosure. ROM110includes control unit202, row decoder204, column decoder206, memory array208, sense amplifiers210, dummy array212, and dummy sense amplifiers214. The control unit202of ROM110is coupled to system bus102by way of a communication bus. The communication bus generally includes address, data, clocks, and control signals for communicating with processor104for example. The control unit is coupled to provide address information to row decoder204and column decoder206. The control unit202is coupled to receive and latch data from sense amplifiers210. The control unit202is also coupled to receive one or more flags from dummy sense amplifiers214. Such flags may be provided to processing system100by way of control unit202.

Memory array includes a plurality of read-only non-volatile memory cells arranged in rows and columns. Row decoder204is coupled to memory array208and based on provided address information, activates a desired word line to read one or more memory cells of the memory array208. Column decoder206is coupled between memory array208and sense amplifiers210and based on provided address information, selects desired columns or bit lines to read the one or more memory cells of the memory array208. For example, memory array208may include 256 columns, and column decoder206may be configured to select a subset of 16 columns to couple to sense amplifiers210for reading memory cells of the memory array208. As used herein, the terms bit line and column may be used interchangeably, and the terms word line and row may be used interchangeably.

Sense amplifiers210are coupled to column decoder206and include circuitry to sense voltage on each selected bit line such that the sensed voltage level determines the value of data stored in memory cells. In this embodiment, the circuitry of sense amplifiers210is arranged in single-ended sense amp configuration. Data sensed in sense amplifiers210is provided to control unit202where the data is latched.

Dummy array212includes one or more dummy bit lines formed similarly to the bit lines of memory array208. In this embodiment, dummy array212is located adjacent to memory array208such that dummy array212and memory array208can be formed in one contiguous array, having a common column pitch, memory cell structure, and the like for example. The one or more dummy bit lines may be configured to represent a pre-determined capacitive load, leakage, or other topological or electrical characteristic. For example, a dummy bit line configured to represent a best case leakage scenario may include a bit line in the dummy array212having only one memory cell coupled to the bit line.

Dummy sense amplifiers214are coupled to dummy array212and include circuitry to sense voltage on each of the one or more dummy bit lines such that the sensed voltage level determines the value of data stored in memory cells. Dummy data sensed in dummy sense amplifiers214is provided to keeper circuitry in sense amplifiers210. Because the dummy bit lines can be configured to represent best case, worst case, or boundary performance cases, whether data is correctly sensed from such dummy bit lines can be useful to self-adjust keeper circuitry in the sense amplifiers210. Dummy sense amplifiers214also include circuitry to generate one or more flags which are provided to the control unit202. The one or more flags provide an indication that one or more dummy sensed data did not produce an expected result. In some embodiments, the one or more flags provide an indication that one or more dummy sensed data produced an expected result.

FIG. 3illustrates, in schematic form, a more detailed representation of sense amplifier block210and dummy sense amplifier block214depicted inFIG. 2according to an embodiment of the present disclosure. The schematic ofFIG. 3includes dummy sense amplifier circuits DSA1-4(302-308), associated dummy logic circuitry formed with logic gates314-322, sense amplifier circuits SA1-N (310,312) and respective drivers (324,326) having output signals SO1-N, where N is the number of sense amplifier circuits to sense data stored in memory array208. In this embodiment, circuit blocks302-312are instances or copies of sense amplifier circuitry400ofFIG. 4described below. Because dummy sense amplifier circuit blocks and sense amplifier circuit blocks (302-312) are substantially the same, these blocks can be readily instantiated with memory compiler tools, for example.

FIG. 4illustrates, in schematic form, simplified sense amplifier circuitry400in accordance with an embodiment of the present disclosure. Sense amplifier circuitry400includes exemplary sense amplifier circuit412and keeper circuit414formed by P-channel transistors402-410. Sense amplifier circuitry400further includes an input labeled IN coupled to an input of sense amplifier circuit412and to a bit line of memory array208or dummy array212. Inputs labeled A-D are coupled to control electrodes of keeper transistors of keeper circuit414and are coupled to receive control or configuration signals. An output of sense amplifier circuitry400labeled OUT is coupled to the output of sense amplifier circuit412.

Sense amplifier circuit412may be any suitable inverting or non-inverting single-ended sense amplifier circuit suitable for sensing data stored in a ROM array. In this embodiment, sense amplifier circuit412is depicted as an inverter having an input coupled to the input labeled IN and an output coupled to the output labeled OUT of sense amplifier circuitry400.

The keeper circuit414is coupled to sense amplifier circuit412to offset logic level degradation due to leakage current of a bit line coupled at the IN input. Transistors of the keeper circuit414are typically characterized as weak transistors. However, the keeper circuit must be strong enough to sustain a logic high level at the sense amplifier circuit input despite bit line leakage currents, and at the same time must be weak enough to allow an accessed bit to pull down the bit line without excessive timing or current drain penalties. In this embodiment, the keeper circuit414includes a first transistor410having a first current electrode coupled to the input of sense amplifier circuit412labeled IN and a control electrode coupled to the output of the sense amplifier circuit412labeled OUT. Series coupled transistors are coupled between transistor410and a first voltage source such as VDD. In this embodiment, VDD is characterized as a voltage source having a nominal voltage sufficient for normal operation of ROM110. The series coupled transistors include a second transistor404having a first current electrode coupled to a second current electrode of the first transistor410and a control electrode coupled to an input labeled B, and a third transistor402having a first current electrode coupled to the second current electrode of the second transistor404, a control electrode coupled to an input labeled A and a second current electrode coupled to the first voltage source (VDD for example).

The keeper circuit414further includes a fourth transistor408coupled in parallel with transistor404, and a fifth transistor406coupled in parallel with transistor402. The fourth transistor408includes a first current electrode coupled to the first current electrode of the second transistor404, a second current electrode coupled to the second current electrode of the second transistor404, and a control electrode coupled to an input labeled D. The fifth transistor406includes a first current electrode coupled to the first current electrode of the third transistor402, a second current electrode coupled to the first voltage source, and a control electrode coupled to an input labeled C. Transistors406and408of keeper circuit414are configured each in parallel with respective transistors402and404such that the keeper strength can be adjusted by activating (turning on) or deactivating (turning off) transistors406and408.

The term keeper strength as used herein, is generally referred to as a characteristic associated with how effectively the keeper circuit414can source current to offset bit line leakage current while sustaining an appropriate logic level voltage on the input of sense amplifier circuit412. For example, when transistors of the keeper circuit are configured or adjusted to have an increased current carry capacity, the keeper strength is increased and thereby more capable of offsetting leakage current and sustaining the appropriate logic level.

In alternative embodiments, keeper circuit414may include any suitable arrangement of transistors such that the keeper strength can be adjusted based on control or configuration signals. For example, an alternative keeper circuit may include a first transistor having a first current electrode coupled to an input of a sense amplifier circuit and a control electrode coupled to an output of the sense amplifier circuit, and a second transistor may be coupled in series between a voltage source such as VDD and the first transistor. The second transistor may include a first current electrode coupled to a second current electrode of the first transistor, a second current electrode coupled to the voltage source, and a control electrode coupled to a first control signal. One or more keeper adjust transistor may be coupled in parallel with the second transistor. For example, a first keeper adjust transistor may include a first current electrode coupled to the first current electrode of the second transistor, a second current electrode coupled to the second current electrode of the second transistor, and a control electrode coupled to a first keeper adjust signal. Similarly, a second keeper adjust transistor may be coupled in parallel with the second transistor, and include a control electrode coupled to a second keeper adjust signal, and so on.

In the embodiment depicted inFIG. 3, dummy sense amplifier circuits DSA1-4are coupled to respective dummy bit lines DBL1-4at the inputs labeled IN and are coupled to provide respective dummy sense amplifier output signals DSAO1-4at the outputs labeled OUT. The DSAO1-4signals are used to form keeper adjust signals DSAO12and DSAO34provided to respective inputs C and D of sense amplifier circuits SA1-N. Dummy bit lines DBL1-4may be configured in any manner having any number of dummy bit cells coupled to DBL1-4. In this embodiment, dummy bit lines DBL1and DBL3are configured to represent a worse case bit line leakage scenario, and dummy bit lines DBL2and DBL4are configured to represent a best case bit line leakage scenario. For example, a dummy bit line representing a worse case leakage scenario for a memory array having 256 word lines may have 256 dummy bit cells coupled to the dummy bit line. While one dummy bit cell is programmed as a logic “1” and turned on, remaining dummy bit cells of the dummy bit line are programmed as a logic “0” and turn off. In contrast, DBL2and DBL4are each configured to have only one of the dummy bit cells programmed as a logic “0” and turned on, while the remaining dummy bit cells coupled to DBL2and DBL4are programmed as a logic “1” and turned off.

Inputs labeled A-D of dummy sense amplifier circuits DSA1-4are coupled to control electrodes of keeper transistors of keeper circuit414and are coupled to receive control or configuration signals. In this embodiment, inputs A and B of each dummy sense amplifier circuit DSA1-4are coupled to a second voltage source such as VSS or ground such that corresponding keeper transistors402and404are turned on or conducting during normal operation of ROM110. Inputs C and D of each dummy sense amplifier circuit DSA1-4are each coupled to the first voltage source (VDD) or the second voltage source such (ground) such that corresponding keeper transistors (406and408) are configured to provide a predetermined keeper strength during normal operation of ROM110. In this embodiment, inputs C and D of dummy sense amplifier circuits DSA1and DSA4are each coupled to the first voltage source (VDD) such that corresponding keeper transistors406and408are turned off or non-conducting during normal operation of ROM110. Inputs C and D of dummy sense amplifier circuit DSA2are configured such that corresponding keeper transistor406is turned off and transistor408is turned on, and inputs C and D of dummy sense amplifier circuit DSA3are configured such that corresponding keeper transistor406is turned on and transistor408is turned off during normal operation of ROM110. In some embodiments, inputs A-D of dummy sense amplifier circuits DSA1-4may be coupled to one or more control or configuration signals which can provide a logic low voltage level such that a corresponding keeper transistor (402-408) can be turned on or conducting during normal operation of ROM110, and turned off when the corresponding control or configuration signal provides a logic high voltage level.

Dummy sense amplifier output signals DSAO1-4are combined with dummy logic circuitry formed with logic gates314-322. NAND gate314includes a first input coupled to receive the DSAO1signal, a second input coupled to receive the DSAO2signal, and an output providing a first keeper adjust signal labeled DSAO12to the C inputs of sense amplifier circuits SA1-N. NAND gate316includes a first input coupled to receive the DSAO3signal, a second input coupled to receive the DSAO4signal, and an output providing a second keeper adjust signal labeled DSAO34to the D inputs of sense amplifier circuits SA1-N. An input of inverter318is coupled to receive dummy sense amplifier output signal DSAO2, a first input of NAND gate320is coupled to receive the DSAO4signal, and a second input of NAND gate320is coupled to receive the inverse of the DSAO2signal provided at the output of inverter318. An output signal of NAND gate320is provided to an input of inverter322and an output signal labeled FLAG is provided at the output of inverter322.

Still referring toFIG. 3, sense amplifier circuits SA1-N are coupled to respective memory array (208) bit lines BL1-N at the inputs labeled IN, where N is the number of sense amplifier circuits to sense data stored in memory array (208). Outputs labeled OUT of sense amplifier circuits SA1-N are coupled to drivers324and326to provide respective sense amplifier output signals SO1-N. Inputs labeled A-D of sense amplifier circuits SA1-N are coupled to control electrodes of keeper transistors of keeper circuit414and are coupled to receive control or configuration signals. In this embodiment, inputs A and B of each sense amplifier circuit SA1-N are coupled to a second voltage source such as VSS or ground such that corresponding keeper transistors402and404are turned on or conducting during normal operation of ROM110. In some embodiments, inputs A and B of sense amplifier circuits SA1-N may be coupled to a control or configuration signal which can provide a logic low voltage level such that corresponding keeper transistor402and404can be turned on or conducting during normal operation of ROM110, and turned off when the corresponding control or configuration signal provides a logic high voltage level. Inputs C and D of each sense amplifier circuit SA1-N are each coupled to receive first and second keeper adjust signals labeled DSAO12and DSAO34respectively such that corresponding keeper adjust transistors (406and408) are turned on and off to adjust the keeper strength of the keeper circuit414during normal operation of ROM110.

In operation, dummy sense amplifier circuits DSA1-4are configured with a predetermined keeper circuit arrangement and a predetermined number of memory cells coupled to dummy bit lines DBL1-4. As conditions change such as the size of ROM arrays, temperature, voltage, and the like, outputs of the dummy sense amplifier circuit can dynamically respond and provide corresponding outputs signals DSAO1-4. These DSAO1-4signals are combined to generate keeper adjust signals which are provided to sense amplifier circuits SA1-N, thereby adaptably changing the characteristics of the sense amplifier circuits SA1-N. For example, if a dummy sense amplifier circuit detects that its keeper circuit cannot keep up with coupled dummy bit line leakage current, a corresponding output signal can be provided to the sense amplifier circuits such that the keeper strength is increased accordingly. Another aspect of operation includes DSAO2and DSAO4signals combined with circuitry to generate the FLAG output signal. For example, a dummy sense amplifier circuit may be configured to determine an out-of-operating-range indication whereby none of the keeper adjust transistors cannot put the sense amplifier circuits into correct functionality operating range. The out-of-operating-range indication can be provided as a flag to the data processing system100notifying the system that ROM110is currently unusable or not within normal operating condition, and allowing the system to go into a safe or corrective state.

Generally, there is provided, a read-only memory (ROM) including a first bit line; a first dummy bit line; a first dummy sense amplifier coupled to the first dummy bit line, the first dummy sense amplifier providing a first output signal; a first sense amplifier coupled to the first bit line; and a first keeper circuit coupled to the first bit line and the first sense amplifier, the first keeper circuit configured to increase keeper strength based on the first output signal. The first dummy bit line may be configured having only one dummy memory cell coupled to the first dummy bit line. The ROM may further include a flag generation circuit to provide a flag signal indicative that the ROM is no longer in a normal operating condition, the flag signal based on the first output signal. The first keeper circuit may further include a first transistor having a first current electrode coupled to the first bit line and a control electrode coupled to an output of the first sense amplifier; a second transistor having a first current electrode coupled to a second current electrode of the first transistor, and a control electrode coupled to a first voltage source; and a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second current electrode of the second transistor, and a control electrode coupled to receive the first output signal. The first keeper circuit may further include a fourth transistor having a first current electrode coupled to a second current electrode of the second transistor, a second current electrode coupled to a second voltage source, and a control electrode coupled to the first voltage source; and a fifth transistor having a first current electrode coupled to the second current electrode of the third transistor, a second current electrode coupled to the second voltage source, and a control electrode coupled to receive a second output signal from a second dummy sense amplifier. The ROM may further include a first dummy keeper circuit coupled to the first dummy bit line and to the first dummy sense amplifier. The ROM may further include a second dummy bit line; a second dummy sense amplifier coupled to the second dummy bit line, the second dummy sense amplifier providing a second output signal; and a second dummy keeper circuit coupled to the second dummy bit line and to the second dummy sense amplifier; wherein the first keeper circuit is configured to increase keeper strength based on the first output signal and the second output signal. The second dummy bit line may be configured having a plurality of memory cells coupled to the second dummy bit line. The first dummy sense amplifier and keeper circuit, the second dummy sense amplifier and keeper circuit, and the first sense amplifier and keeper circuit may be substantially similar to each other.

In another embodiment, there is provided, a read-only memory (ROM) including a first bit line; a first dummy bit line; a first dummy sense amplifier having an input coupled to the first dummy bit line and an output; a first sense amplifier having an input coupled to the first bit line and an output; a first keeper transistor having a first current electrode coupled to the first bit line and a control electrode coupled to the first sense amplifier output; and a second keeper transistor having a first current electrode coupled to a second current electrode of the first keeper transistor, and a control electrode coupled to the output of the first dummy sense amplifier. The first keeper circuit may further include a third keeper transistor having a first current electrode coupled to the first current electrode of the second keeper transistor, a second current electrode coupled to a second current electrode of the second keeper transistor, and a control electrode coupled to a first configuration signal. The first keeper circuit may further include a fourth keeper transistor having a first current electrode coupled to a second current electrode of the second keeper transistor, a second current electrode coupled to a first voltage source, and a control electrode coupled to the first configuration signal; and a fifth keeper transistor having a first current electrode coupled to the second current electrode of the third keeper transistor, a second current electrode coupled to the first voltage source, and a control electrode coupled to receive a second output signal from a second dummy sense amplifier. The first configuration signal may provide a logic low level during normal operation of the ROM. The ROM may further include a first dummy keeper circuit coupled to the first dummy bit line and to the first dummy sense amplifier, and a second dummy keeper circuit coupled to a second dummy bit line and to the second dummy sense amplifier. The first dummy bit line may be configured having only one dummy memory cell coupled to the first dummy bit line. The ROM may further include a flag generation circuit to provide a flag signal indicative that the ROM is no longer in a normal operating condition, an input of the flag generation circuit coupled to the output of the first dummy sense amplifier.

In yet another embodiment, there is provided, a method for operating a read-only memory (ROM) including sensing a dummy bit line with a dummy sense amplifier circuit coupled to the dummy bit line to generate an dummy sensed output signal; and based on the dummy sensed output signal, adjusting a keeper strength of a keeper circuit coupled to a sense amplifier circuit, the sense amplifier circuit capable of sensing data stored in the ROM. The method may further include based on the dummy sensed output signal, generating a flag signal indicative that the ROM is no longer in a normal operating condition. The method may further include a dummy keeper circuit coupled to the dummy sense amplifier, and wherein circuitry forming the dummy sense amplifier and keeper circuit may be substantially the same as circuitry forming the sense amplifier circuit and keeper circuit. The adjusting a keeper strength of a keeper circuit may include increasing the keeper strength of the keeper circuit.

Therefore, by now it can be appreciated that there has been provided, an apparatus and method for sensing and operating a read-only memory (ROM). Because ROM array sizes and operating conditions may vary widely over a broad range of applications, an adaptable keeper circuit scheme is coupled with a single-ended sense amplifier to deliver optimum performance. Dummy sensing schemes are provided which allow for generation of control signals to adjust sense amplifier keeper circuits. The dummy sensing schemes can correspond to best case and worse case bit line leakage scenarios, for example. By utilizing the control signals generated from the dummy sensing schemes, keeper transistors can be activated to increase keeper strength in sense amplifiers circuits to sense data stored in the ROM.

Also for example, in one embodiment, the illustrated elements of data processing system100are circuitry located on a single integrated circuit or within a same device. Alternatively, data processing system100may include any number of separate integrated circuits or separate devices interconnected with each other.