Method for low power boot for microcontroller

A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

BACKGROUND OF THE INVENTION

The present invention is directed to microcontrollers and, more particularly, to a method of resetting and booting a microcontroller in low power mode.

Power critical applications, such as in medical devices, metering devices, and the like, do not often include power sources capable of generating high currents. Thus, a microcontroller unit (MCU) in the device must ration the current among all resources requiring power consumption. Reset and boot cycles for the MCU can present a problem with power consumption. For example, the MCU in a device may require 16-18 milliAmperes (mA) of current while the existing power source can budget no more than 7 mA.

The main contributors to power drain during reset and boot sequences of the MCU are the flash memory, the system-on-chip (SoC) logic and the number of peripherals that are active following the reset sequence, and the use of a high frequency clock source during the boot sequence.

It is desirable to provide an MCU and a method of resetting and booting the MCU that requires less power and could therefore be used in current limited applications.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings, wherein the same reference numerals are used to designate the same components throughout the several figures, there is shown inFIG. 1a microcontroller unit (MCU)10having at least one central processing unit (CPU) core12. In one preferred embodiment, the core12may be a 32-bit CORTEX-M0+ processor commercially available from ARM Holdings in Cambridge, UK. The core12reads and executes most, if not all, of the instructions stored or sent to the MCU10for operation of the MCU10or the device in which the MCU10is contained. The core12is further configured to execute a boot code following a reset sequence. The boot code contains the necessary instructions for initializing the MCU10for operation following the reset sequence.

The core12is preferably coupled to a flash memory14configured to store device options or similar data for use by the MCU10. In the embodiment shown inFIG. 1, the flash memory14includes 128 kB of non-volatile memory space. Although a flash memory14is used in the MCU10, other memory types may also be used, such as EEPROM or the like.

The flash memory14includes an internal clock16that the flash memory14utilizes for execution of its tasks. Ordinarily, the internal clock16would also be utilized during resetting and boot sequences of the MCU10for calibration and initialization of the flash memory14. In preferred embodiments of the MCU10, the internal clock16operates at about 25 MHz.

The flash memory14further includes a non-volatile option register18which stores data or information that is fetched by the flash memory14during or shortly after the reset sequence of the MCU10. The fetched information includes data used during the boot sequence, for example, by the core12or the like.

The core12is also preferably coupled to a system mode controller (SMC)20, which establishes an operating mode of the MCU10. For example, the SMC20may place the MCU10into a “RUN” mode, which is preferably the ordinary operating mode where the core12is fully functional and the distribution of voltage by a power management controller (PMC)22is fully regulated. A low voltage detector (LVD) circuit24is provided in the PMC22as protection against drops in voltage levels across the MCU10. The SMC20may also place the MCU10into a “wait” mode, where the core12is in a sleep state, reducing power, but peripheral modules26continue to function and are clocked. The SMC20may further place the MCU10into a “stop” mode, where the core12is in a sleep state and all peripheral modules26are optionally stopped. Preferably, the power is still sufficient to maintain the LVD24protection.

As will be described in further detail below, the SMC20also preferably is able to place the MCU10into a “very low power run” (VLPR) mode, wherein the clock frequencies of the core12and the flash memory14are restricted, and the PMC22operates to provide only enough power to run the MCU10at the reduced frequencies. The LVD24is preferably not operational in the VLPR mode. Peripheral modules26may be used as needed, but also run at reduced frequencies. Other operational modes for distribution and conservation of power may also be used.

The MCU10further includes a clock generator28having an internal reference clock30. The internal reference clock30preferably oscillates in the range of 2-4 MHz. The internal reference clock30outputs an output clock signal OUTCLK that may be adjusted for use by various components of the MCU10. For example, the output clock signal OUTCLK from the internal reference clock30may be received by dividers25, which may generate a core clock signal CORECLK used by the core12and an external flash clock signal FLSHCLK received by the flash memory14. In particular, the external flash clock signal FLSHCLK preferably has a frequency of about 1 MHz, and may be used by the flash memory14during the VLPR mode of operation of the MCU10.

The clock generator28may have additional internal reference clocks (not shown) operating at various frequencies as needed for operation of the MCU10. The clock generator28further preferably includes at least a frequency lock loop (FLL)32and a phase lock loop (PLL)34for control of output signals from the clock generator28that may be used by the core12, the flash memory14, or the like. In preferred embodiments, the clock generator28includes the above-described 2-4 MHz internal reference clock30and a further reference clock (not shown) coupled to the FLL32and PLL34. In the VLPR mode, it is preferred that the FLL32and PLL34are bypassed.

The MCU10further includes a boot mode selection logic circuit36which outputs a boot mode selection signal BMSS to at least the SMC20and the flash memory14. The boot mode selection signal BMSS designates whether the MCU10is to boot in the RUN mode or the VLPR mode. Thus, upon a reset and boot operation, the SMC20and the flash memory14perform various functions depending on the designation made by the boot mode selection signal BMSS.

For example, the boot mode selection signal BMSS is output during the reset sequence, and the SMC20therefore enters the VLPR mode or the RUN mode in response. It is preferred that regardless of the mode entered, the 2-4 MHz signal from the internal reference clock30of the clock generator28is selected as the default clock source. By selecting a slow clock source and bypassing the FLL32and PLL34, a significant reduction in power can be achieved.

When the boot mode selection signal BMSS designates the VLPR mode, the flash memory14bypasses and disables its internal clock16prior to calibration. Thus, the flash memory14calibrates itself, fetches information from the non-volatile options register18, and initializes using the external flash clock signal FLSHCLK, preferably at about 1 MHz. This contrasts greatly with the power required during the normal boot operation, wherein the flash memory14performs all of these functions using its internal clock16operating at about 25 MHz.

When the boot mode selection signal BMSS designates the RUN mode, however, the flash memory14calibrates and fetches the information from the non-volatile option register18using its internal clock16. In order to gain the benefit of power savings while booting in the RUN mode, it is preferred that the information fetched from the non-volatile option register18include a bypass bit. When the flash memory14reads the bypass bit out of the non-volatile option register18, the flash memory14is configured to disable and bypass the internal clock16and utilize the external flash clock signal FLSHCLK for the remaining initialization functions of the flash memory14during the reset and boot sequence.

It is preferred that one of the VLPR mode or the RUN mode be set as the default boot mode for the MCU10such that each reset and boot sequence is performed under the default mode for power saving. Further preferably, the MCU10will reset and boot in the RUN mode as a default, since debugger access is not available in the VLPR mode. However, it may be necessary to allow a user to override the default mode depending on the prevailing conditions of use. The override may be provided in any number of ways.

For example, the boot mode selection logic circuit36may be coupled to a battery-backed up real time clock (RTC) circuit38of the MCU10. The RTC circuit38may store an override bit that, depending on the value, may cause the boot mode selection logic circuit36to alter the boot mode selection signal BMSS to designate the boot mode which is different than the set default boot mode. Since the RTC circuit38is powered by a separate dedicated battery power supply, loss of power to the MCU10will not effect the override bit stored in the RTC circuit38.

FIG. 2shows an exemplary configuration for the boot mode selection logic circuit36. An XOR gate40receives as inputs a default boot mode signal from an unbonded pad or option plug42of the MCU10and the override bit from the RTC circuit38. The result of the XOR gate40is fed through additional OR gates44,46and a flip-flop48to form the eventual boot mode selection signal BMSS. Essentially, the override bit from the RTC circuit38simply inverts the default option on the next MCU10system reset. If the override bit is not set or gets cleared, the default boot option returns on the next reset.

It is preferred that the override bit is only cleared by a power-on-reset of the RTC circuit38, and is not affected by the system reset of the MCU10, as a result of the RTC circuit38being powered by a back-up battery (not shown). On a power-on-reset of the RTC circuit38, the override bit may be cleared and the boot mode selection signal BMSS may return to the default setting on the next system reset. The override bit can also be stored in locations other than the RTC circuit38for reading out by the boot mode selection logic circuit36.

An alternative override method includes storing an override bit in the flash memory14. When the core12reads the boot code, it will also read the override bit out of the flash memory14and, when the override bit is set to a value indicating override, the core12will instruct the SMC20to enter the boot mode which is different from the default boot mode. A limitation on this method is that the default boot mode is used until the boot code is executed. For example, the MCU10will boot in the VLPR mode until the boot code is executed and the core12instructs the SMC20to enter the RUN mode, whereafter the remainder of the boot sequence will occur in the RUN mode.

Other methods for overriding the default boot mode of the MCU10may be used as well.

Other components of the MCU10are also affected by the boot mode selection signal BMSS designation. For example, in the VLPR mode, the SMC20instructs the PMC22to fully regulate the voltage until initialization of the flash memory14is completed. Thereafter, the SMC20instructs the PMC22to only loosely regulate the voltage (i.e., strict adherence to a set voltage is not required). It is preferred in the RUN mode that no change to the operation of the PMC22is made.

In addition, most, and preferably all, of the peripheral modules26are disabled during reset, particularly in the VLPR mode. This can be achieved by, for example, gating internal clocks26aof the peripheral modules26during and/or after the reset sequence. For peripheral modules26that rely on an external clock signal, such as BUSCLK received from the dividers25, the external peripheral clock signal BUSCLK would also be gated during and/or after reset. Still further, the FLL32and the PLL34are disabled during and/or after the reset sequence, ensuring that none of the components of the MCU10is utilizing a clock in excess of the output clock signal OUTCLK of the 2-4 MHz internal reference clock30of the clock generator28during the boot sequence.

Embodiments of the present invention achieve a lowest possible current consumption during a boot in either the VLPR or the RUN modes, while balancing the need for booting of the MCU10to occur within a reasonable time period. The techniques described herein minimize current spikes during the boot sequence of the core12and naturally fits with battery operating MCUs10. Boot selection is also performed without a dedicated MCU10pin, and does not require a hardware change to be set.

FIG. 3is a plot of current levels during a reset and boot sequence of an MCU10in the RUN mode using an internal reference clock30at 2 MHz.FIG. 4is an enlargement of the plot ofFIG. 3in the first 200 ms. As can be seen from these plots, the peak generated current level during the reset and boot sequence was between 3 and 3.5 mA, with the duration of the sequence falling between 1 and 1.5 mA.

FIG. 5is a plot of current levels during a reset and boot sequence of an MCU10in the VLPR mode, again using an internal reference clock30at 2 MHz.FIG. 6is an enlargement of the plot ofFIG. 3in the first 200 ms. As can be seen from these plots, the peak generated current level during the reset and boot sequence in the VLPR mode was between 3 and 3.5 mA, with a drop down below 0.5 mA, and with the duration of the sequence falling between 0.5 and 1 mA. It should be noted that the initial peak currents are due to the charging of internal capacitances in the MCU10and will be generated during initial power-up of the device irrespective of the boot mode selected, although a low power mode exit followed by a reset does not require charging of internal capacitances and hence no peak is visible.

These values in either mode are much lower than the values described in prior art systems, where current levels could reach near 20 mA during the reset and boot sequences.

Those skilled in the art will also recognize that the term “coupled” can mean direct or indirect coupling between elements for communication of data or other signals. For example, a component may be coupled to another through one or mode additional components such as switches, a BUS, or the like. Moreover, components may be combined into a single functional unit rather than being separate components connected by a wire, trace, or the like.