Semiconductor memory device and information processing apparatus

A semiconductor memory device includes an address decoder to decode an address specifying pseudo-multiport cells in memory blocks, a first word line driver to output a word line selection signal selecting one of word lines of one of the pseudo-multiport cells based on a row address in the address, and a second word line driver having an output part to output the word line selection signal into one of a pair of the word lines of the pseudo-multiport cell, and a NOR logic part to output NOR of the word line selection signal and a read/write selection signal into the other one of the pair of the word lines, the read/write selection signal selecting writing or reading operations. The second word line driver activates the pair of the word lines for writing data, and activates one of the pair of the word lines for reading data.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-207267, filed on Sep. 20, 2012, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor memory device and an information processing apparatus.

BACKGROUND

There is known in the related art a multiport memory including a read port, a write port, a memory cell array having a plurality of memory cells disposed in an array, and a read/write control circuit. Such a multiport memory generally includes a sub word controller configured to activate a sub word line for selecting a write port memory cell when a write enable signal and a chip enable signal are both valid.

When the related art multiport memory is operated as a single port memory, of a pair of word lines, both word lines are activated when data are retrieved. Hence, power consumption may be increased in this multiport memory case compared to a case where a single port memory fabricated for a single port operation is operated for retrieving data.

Thus, it may be desirable to provide a semiconductor memory device capable of exhibiting reduced electrical power consumption.

RELATED ART DOCUMENTS

Patent Document

SUMMARY

According to an aspect of the embodiments, there is provided a semiconductor memory device that includes a plurality of memory blocks including a plurality of pseudo-multiport cells; an address decoder configured to decode an address specifying one of the pseudo-multiport cells included in the memory blocks; a first word line driver configured to output a word line selection signal selecting one of word lines of the one of the pseudo-multiport cells included in the memory blocks based on a row address included in the address output from the address decoder; and a second word line driver having an output part configured to output the word line selection signal into a first one of a pair of the word lines of the one of the pseudo-multiport cells included in the memory blocks, and a NOR logic part configured to output a result of NOR of the word line selection signal and a read/write selection signal into a second one of the pair of the word lines, the read/write selection signal selecting one of a writing operation to write data into the one of the pseudo-multiport cells or a reading operation to read data from the one of the pseudo-multiport cells, wherein the second word line driver activates the pair of the word lines for writing data into the one of the pseudo-multiport cells, and activates the first one of the pair of the word lines for reading data from the one of the pseudo-multiport cells.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments will be described with reference to the accompanying drawings. Specifically, a description is given of a semiconductor device and an information processing apparatus to which embodiments are applied.

Initially, a comparative example of a semiconductor memory device is illustrated prior to illustration of the semiconductor memory device of the embodiments.

Comparative Example

FIG. 1is a schematic diagram illustrating a structure of a single port bit cell for use in a static random access memory (SRAM), andFIG. 2is a diagram illustrating a detailed structure of the bit cell ofFIG. 1.

As illustrated inFIG. 1, a bit cell10includes a pair of inverters11and12, and n-type metal oxide semiconductor (NMOS) transistors13and14.

The inverters11and12are mutually connected such that the inverters11and12form a loop. Respective gates of the NMOS transistors13and14are connected to a word line WL. A drain of the NMOS transistor13is connected to a positive bit line BL whereas a drain of the NMOS transistor14is connected to a negative bit line BLB (BL bar).

Further, respective sources of the NMOS transistors13and14are connected to connectors N1and N2of the inverters11and12.

As illustrated inFIG. 2, the inverter11is a complementary metal oxide semiconductor (CMOS) inverter including a p-type metal oxide semiconductor (PMOS) transistor11A and an n-type metal oxide semiconductor (NMOS) transistors11B. Likewise, the inverter12is a complementary metal oxide semiconductor (CMOS) inverter including a p-type metal oxide semiconductor (PMOS) transistor12A and an n-type metal oxide semiconductor (NMOS) transistors12B. Specifically, the bit cell10illustrated inFIGS. 1 and 2includes six MOS transistors.

Input/output terminals of the MOS transistors11A and11B intersect input/output terminals of the MOS transistors12A and12B such that the bit cell10is implemented as a latch circuit including the inverters11and12.

The connector N1between the drains of the MOS transistors11A and11B inFIG. 2corresponds to the connector N1illustrated inFIG. 1, which serves as a storage node N1. Further, the connector N2between the drains of the MOS transistors12A and12B inFIG. 2corresponds to the connector N2illustrated inFIG. 2, which serves as a storage node N2.

Data are retrieved from, or written into the storage nodes N1and N2by causing the storage nodes N1and N2to store complementary data of “1”, “0”, or “0”, “1”, and selecting the bit cell10by driving the word line WL and the pair of the bit lines BL and BLB.

For retrieving data, when the word line WL is driven by switching the pair of bit lines BL and BLB into a high (H) level, one of the bit lines BL and BLB is switched to a low (L) level by a corresponding one of the storage nodes N1and N2, thereby outputting data as retrieved (read) data.

On the other hand, for writing data, the word line WL is driven by switching one of the bit lines BL and BLB to a high (H) level and the other one of bit lines BL and BLB to a low (L) level, thereby writing data into the storage nodes N1and N2.

In the bit cell10illustrated inFIGS. 1 and 2is a six-transistor bit cell. This type of the bit cell is not capable of retrieving and writing data simultaneously so that retrieving data and writing data are performed in different cycles.

The respective two inverters11and12inFIG. 3are identical to the inverters11and12included in the single port bit cell10illustrated inFIG. 1. Each of the inverters11and12includes two transistors (seeFIG. 2). Hence, those parts that are the same are designated by the same reference numerals, and a description thereof will be omitted.

The multiport bit cell20includes three word lines, namely, two write word lines WWLA and WWLB, and one read word line RWL. The multiport bit cell20further includes two pairs of bit lines (i.e., four bit lines), namely, a positive write bit line WBL, a negative write bit line WBLB (WBL bar), a positive read bit line RBL, and a negative read bit line RBLB (RBLB bar).

Respective gates of the NMOS transistors13and14are connected to the read word line RWL. A drain of the NMOS transistor13is connected to the read bit line RBL, and a source of the NMOS transistor13is connected to the storage node N2. Likewise, a drain of the NMOS transistor14is connected to the read bit line RBLB, and a source of the NMOS transistor14is connected to the storage node N1.

A gate of the NMOS transistors21is connected to the write word line WWLA. A drain of the NMOS transistor21is connected to the write bit line WBL, and a source of the NMOS transistor21is connected to a drain of the NMOS transistor22. Likewise, the drain of the NMOS transistor22is connected to the source of the transistor21, a source of the NMOS transistor22is grounded, and a gate of the NMOS transistor22is connected to the storage node N2.

A gate of the NMOS transistors23is connected to the write word line WWLB. A drain of the NMOS transistor23is connected to the write bit line WBLB, and a source of the NMOS transistor23is connected to a drain of the NMOS transistor24.

Likewise, the drain of the NMOS transistor24is connected to the source of the transistor23, a source of the NMOS transistor24is grounded, and a gate of the NMOS transistor24is connected to the storage node N1.

To retrieve data, the bit cell20is selected by driving the read word line RWL, and the read bit lines RBL and RBLB.

To write data, the bit cell20is selected by driving the write word lines WWLA and WWLB, and the write bit lines WBL and WBLB.

The bit cell20includes the transistors13and14used for retrieving data, and the transistors21,22,23and24for writing data. Since the bit cell20uses different word lines and bit lines for retrieving data and writing data, retrieving (reading) and writing operations may be performed simultaneously.

FIG. 4is a diagram illustrating a pseudo-multiport bit cell30.

As illustrated inFIG. 4, in the bit cell30, a gate of the NMOS transistor13connected to the bit line BL is connected to a word line WLA_L, and a gate of the NMOS transistor14connected to the bit line BLB is connected to a word line WLB_L.

Other parts of the configuration of the bit cell30are similar to those of the configuration of the bit cell10illustrated inFIG. 1.

In the bit cell30, for retrieving data, a pair of the bit lines BL and BLB is selected while the pair of the word lines WLA_L and WLB_L is switched to the H level to retrieve data from the storage nodes N1and N2of the bit cell30.

Further, for writing data, the bit lines BL and BLB are selected while the word lines WLA_L and WLB_L are switched to the H level to write data into the storage nodes N1and N2of the bit cell30.

Thus, the pseudo-multiport bit cell30is capable of writing data in the storage nodes N1and N2while simultaneously retrieving two sets of data retained in the storage nodes N1and N2. The pseudo-multiport bit cell30may construct a so-called 2 read-1 write (2R1W) type SRAM.

Next, a description is given of an SRAM40including a comparative example of the pseudo-multiport bit cell30with reference toFIG. 5.

FIG. 5is a diagram illustrating the SRAM40including the comparative example of the pseudo-multiport bit cell30.

The SRAM40includes sub arrays41and42, a word line driver43, and a final word line driver44as main components.

The sub arrays41and42include a plurality of the pseudo-multiport bit cells30. For convenience of illustration, inFIG. 5, word lines WLA_L and WLB_L are illustrated inside the sub array41, and word lines WLA_R and WLB_R are illustrated inside the sub array42.

The word lines WLA_L and WLB_L illustrated inside the sub array41correspond to the word lines WLA_L and WLB_L illustrated inFIG. 4. Suffixes “_L” of the word lines WLA_L and WLB_L indicate that the sub array41resides on the left hand side of the final word line driver44inFIG. 5.

Further, the word lines WLA_R and WLB_R illustrated inside the sub array42are a pair of word lines similar to the word lines WLA_L and WLB_L illustrated inFIG. 4. Since the sub array42resides on the right hand side of the final word line driver44, the word lines illustrated inside the sub array42are provided with a suffix “_R”.

Thus, inFIG. 5, the word lines WLA_L and WLB_L are illustrated in the sub array41, and the word lines WLA_R and WLB_R are illustrated in the sub array42.

However, in practice, there is a plurality of pairs of the word lines WLA_L and WLB_L inside the sub array41, such that a plurality of pseudo-multiport bit cells30is disposed in a row direction (i.e., a vertical direction inFIG. 5). Likewise, there is a plurality of pairs of the word lines WLA_R and WLB_R inside the sub array42, such that a plurality of pseudo-multiport bit cells30is disposed in the row direction (i.e., the vertical direction inFIG. 5).

Further, though not illustrated inFIG. 5, a plurality of pairs of bit lines is disposed inside the sub arrays41and42, and the pairs of the bit lines are connected to the pseudo-multiport bit cells30. Note that illustration of drivers to drive the bit lines or the like are omitted fromFIG. 5.

As described above, each of the sub arrays41and42includes the plurality of the pseudo-multiport bit cells30disposed in a matrix.

The word line driver43is disposed adjacent to the sub array41. The word line driver43includes NAND logic parts43A and43B. The NAND logic part43A is supplied with a word line selection signal WLA and an enable signal ENA_A. The NAND logic part43B is supplied with a word line selection signal WLB and an enable signal ENA_B.

FIG. 5illustrates a pair of A word lines (WLA_L/WLA_R) and B word lines (WLB_L/WLB_R). However, in practice, there is a plurality of the pairs of the A word lines (WLA_L/WLA_R) and the B word lines (WLB_L/WLB_R) corresponding to the bit cells30disposed in a matrix as described above.

Accordingly, in practice, there are plural of the NAND logic parts43A and43B disposed corresponding to the plurality of the pairs of the A word lines (WLA_L/WLA_R) and B word lines (WLB_L/WLB_R).

The word line selection signal WLA is a selection signal for selecting a specific word line WLA_L of the plural word lines WLA_L and a specific word line WLA_R of the plural word lines WLA_R. The enable signal ENA_A is an enabling signal for activating the word lines WLA_L and WLA_R.

The word lines WLA_L and WLA_R are activated and switched to a high (H) level when the word line selection signal WLA and the enable signal ENA_A supplied to the NAND logic part43A are both at a high (H) level.

The word line selection signal WLB is a selection signal for selecting a specific word line WLB_L of the plural word lines WLB_L and a specific word line WLB_R of the plural word lines WLB_R. The enable signal ENA_B is an enabling signal for activating the word lines WLB_L and WLB_R.

The word lines WLB_L and WLB_R are activated and switched to a high (H) level when the word line selection signal WLB and the enable signal ENA_B supplied to the NAND logic part43B are both at a high (H) level.

The final word line driver44is disposed between the sub arrays41and42. The final word line driver44includes inverters44AL,44AR,44BL, and44BR.

Respective input terminals of the inverters44AL and44AR are connected to an output terminal of the NAND logic part43A of the word line driver43. An output terminal of the inverter44AL is connected to the word line WLA_L of the sub array41, and an output terminal of the inverter44AR is connected to the word line WLA_R of the sub array42.

The inverters44AL and44AR are configured to invert a selection signal XWLA output from the NAND logic part43A, and output the inverted selection signal XWLA to the respective word lines WLA_L and WLA_R. The selection signal XWLA is a signal obtained by inverting a word line selection signal WLA.

Hence, when the enable signal ENA_A is at a high (H) level, the selection signal WLA is equal to output signals of the inverters44AL and44AR. That is, the word lines WLA_L and WLA_R receive a signal having a signal level equal to that of the selection signal WLA.

Respective input terminals of the inverters44BL and44BR are connected to an output terminal of the NAND logic part43B of the word line driver43. An output terminal of the inverter44BL is connected to the word line WLB_L of the sub array41, and an output terminal of the inverter44BR is connected to the word line WLB_R of the sub array42.

The inverters44AL and44AR are configured to invert a selection signal XWLB output from the NAND logic part43B, and output the inverted selection signal XWLB to the respective word lines WLB_L and WLB_R. The selection signal XWLB is an inverted signal of the word line selection signal WLB, that is, a signal obtained by inverting a word line selection signal WLB.

Hence, when the enable signal ENA_B is at a high (H) level, the selection signal WLB is equal to output signals of the inverters44BL and44BR. That is, the word lines WLB_L and WLB_R receive a signal having a signal level equal to that of the selection signal WLB.

As described above, the word line driver43may need to individually control two word lines WLA_L and WLB_L to operate the pseudo-multiport bit cells30(seeFIG. 4) included in the sub array41as a multiport for retrieving and writing data.

Similarly, the word line driver43may need to individually control two word lines WLA_R and WLB_R to operate the pseudo-multiport bit cells (seeFIG. 4) included in the sub array42as a multiport for retrieving and writing data.

Thus, the word line driver43may need to individually control the A word line (WLA_L/WLB_L) and the B word line (WLA_R/WLB_R) to operate the pseudo-multiport bit cells30(seeFIG. 4) included in the sub arrays41and42as a multiport for retrieving and writing data.

Next, a description is given of an SRAM50operating the pseudo-multiport bit cells30(seeFIG. 4) as a single port bit cell with reference toFIG. 6.

FIG. 6is a diagram illustrating the SRAM50including the comparative example of the pseudo-multiport bit cell30.

The SRAM50includes sub arrays51and52, a word line driver53, and a final word line driver54as main components.

The sub arrays51and52include a plurality of the pseudo-multiport bit cells30(seeFIG. 4) disposed in a matrix in a manner similar to the sub arrays41and42of the SRAM40illustrated inFIG. 5. However, the sub arrays51and52differ from the sub arrays41and42in that each of the pseudo-multiport bit cells30included in the sub arrays51and52is operated as a single port bit cell.

Note that, though not illustrated inFIG. 6, a plurality of pairs of bit lines is disposed inside the sub arrays51and52, and the pairs of the bit lines are connected to the pseudo-multiport bit cells30. Note that illustration of drivers to drive the bit lines or the like is omitted fromFIG. 6.

Note that the operation as a single port bit cell indicates that data are retrieved by utilizing one of the word lines of the pair. For example, when the multiport bit cell is utilized as a single port bit cell, a part of the multiport bit cell fabricated in a large scale integrated circuit (LSI) may be operated as a single port bit cell.

When the part of the multiport bit cell is operated as a single port bit cell, it may be possible to reduce fabrication cost of memory or the like formed of the LSI, cancel out fabrication variability in the bit cells operating as the multiport bit cells and the bit cells operating as the single port bit cells, and improve the operating properties.

Accordingly, in the following, a case where the pseudo-multiport bit cell30is operated as a single port bit cell is examined.

In order to operate each of the pseudo-multiport bit cells30as a single port bit cell, the A word line (WLA_L/WLA_R) and the B word line (WLB_L/WLB_R) in the sub arrays51and52are activated by common control signals.

The word line driver53is disposed adjacent to the sub array51and includes a NAND logic part53A. The NAND logic part53A is supplied with a word line selection signal WLA and an enable signal ENA_A. The word line selection signal WLA and the enable signal ENA_A are the control signals similar to the word line selection signal WLA and the enable signal ENA_A of the SRAM40illustrated inFIG. 5.

FIG. 6illustrates one of each of the A word lines WLA_L and WLA_R; however, in practice, there is a plurality of A word lines WLA_L and WLA_R corresponding to the bit cells30disposed in a matrix. Accordingly, in practice, there is a plurality of the NAND logic parts53A disposed corresponding to the A word lines WLA_L and WLA_R.

An output terminal of the NAND logic part53A is connected to input terminals of inverters54AL,54AR,54BL, and54BR of the final word line driver54disposed between the sub arrays51and52.

The final word line driver54includes the inverters54AL,54AR,54BL, and54BR. Respective input terminals of the inverters54AL,54AR,54BL, and54BR are connected to the output terminal of the NAND logic part53A of the word line driver53.

Hence, the inverters54AL,54AR,54BL, and54BR are supplied with a selection signal XWLA as a common control signal from the NAND logic part53A of the word line driver53. This is because each of the pseudo-multiport bit cells30(seeFIG. 4) included in the SRAM50is operated as a single port bit cell.

In the SRAM50illustrated inFIG. 6, since each of the pseudo-multiport bit cells30is driven as single port memory, driving signals input into the A word lines (WLA_L/WLA_R) and the B word lines (WLB_L/WLB_R) form respective operating waveforms illustrated inFIG. 7.

FIG. 7is a timing chart illustrating operations of the SRAM50. InFIG. 7, the A word lines (WLA_L/WLA_R) are represented by WLA_L/R, and the B word lines (WLB_L/WLB_R) are represented by WLB_L/R.

The driving signals input into the A word lines (WLA_L/R) and the B word lines (WLB_L/R) are inverted selection signals XWLA. The inverted selection signals XWLA are obtained by inverting the selection signals XWLA output by the NAND logic part53A of the word line driver53by inverters54AL,54AR,54BL, and54BR.

That is, the driving signals input into the A word lines (WLA_L/R) and the B word lines (WLB_L/R) are signals reflecting a high (H)/low (L) level of the word line selection signal WLA while the enable signal ENA_A input into the NAND logic part53A maintaining a high (H) level as illustrated inFIG. 7.

Note that when data are written into the SRAM50(WRITE operating time), data may need to be written into both the storage nodes N1and N2of the bit cell30illustrated inFIG. 4.

Hence, when data are written into the SRAM (WRITE operating time), the A word lines (WLA_L/R) and the B word lines (WLB_L/R) both need to be activated.

On the other hand, when data are retrieved from the SRAM50(READ operating time), data may need to be retrieved from any one of the storage nodes N1and N2of the bit cell30illustrated inFIG. 4; that is, it is not necessary to retrieve data from both the storage nodes N1and N2. This is because the data retained in the bit cell30may be detectable by retrieving the data of one of the storage nodes N1and N2.

Hence, when data are retrieved from the SRAM50(READ operating time), it is sufficient to activate one of the A word lines (WLA_L/R) and the B word lines (WLB_L/R). Hence, when the A word lines (WLA_L/R) are activated to retrieve data from the SRAM50, the B word lines (WLB_L/R) need not be activated, for example.

However, in the comparative example of the SRAM50inFIG. 6, the B word lines (WLB_L/R) are activated as indicated by an oval broken line inFIG. 7when data are retrieved (READ operating time). This may require fundamentally unnecessary extra electrical power consumption.

To prevent unnecessary extra electrical power consumption, it is necessary to configure a circuit such that both the A word lines (WLA_L/R) and the B word lines (WLB_L/R) are activated when data are written, whereas one of the A word lines (WLA_L/R) and the B word lines (WLB_L/R) is activated when data are retrieved.

In the following, a circuit in which any one of the A word lines (WLA_L/R) and the B word lines (WLB_L/R) is activated when data are retrieved is examined with reference toFIG. 8.

FIG. 8is a diagram illustrating a comparative example of an SRAM60.

The SRAM60includes sub arrays51and52, a word line driver53, and a final word line driver64as main components. The SRAM60includes a configuration in which the final word line drive54of the SRAM50illustrated inFIG. 6is modified.

Hence, the sub arrays51and52, and the word line driver53are similar to those of the SRAM50illustrated inFIG. 6, and duplicated description will thus be omitted.

Note that illustration of the bit lines and drivers to drive the bit lines or the like disposed inside the sub arrays51and52are omitted fromFIG. 8in a manner similar to the illustration inFIG. 6.

The final word line driver64includes the inverters54AL and54AR, and NOR logic parts64L and64R. The configurations of the inverters54AL and54AR are similar to those of the inverters54AL and54AR of the final word line driver54illustrated inFIG. 6.

The final word line driver64receives a switching signal R/W input from an inverter65. The inverter65is included in a local control block (not illustrated inFIG. 6) of the SRAM60, and is configured to output the switching signal R/W obtained by inverting a write enable signal.

In this case, a low (L) level of the write enable signal enables write (WRITE) operations whereas a high (H) level of the write enable signal disenables write (WRITE) operations. That is, the H level of the write enable signal is a signal level at which read (READ) operations are enabled.

The switching signal R/W is at L level when the write enable signal is at L level whereas the switching signal R/W is at H level when the write enable signal is at H level. As an example, the L level of the switching signal R/W is defined as a signal level when the write (WRITE) operations are performed whereas the H level of the switching signal R/W is defined as a signal level when the read (READ) operations are performed.

First input terminals (see upper input terminals inFIG. 8) of the NOR logic parts64L and64R are connected to the output terminal of the NAND logic part53A of the word line driver53. Second input terminals (see lower input terminals inFIG. 8) of the NOR logic parts64L and64R are connected to the output terminal of the inverter65.

In the following, a description is given of operations of the SRAM60.

FIG. 9is a timing chart illustrating the operations of the SRAM60.

When the write (WRITE) operations are performed, the switching signal R/W output by the inverter65is at L level, and the output signals of the NOR logic parts64L and64R are at a signal level identical to those of the inverters54AL and54AR.

Hence, when the write (WRITE) operations are performed, the driving signal reflecting the signal level of the word line selection signal WLA is supplied to both the A word lines (WLA_L/R) and the B word lines (WLB_L/R), as illustrated inFIG. 9.

On the other hand, when the read (READ) operations are performed, the switching signal R/W output by the inverter65is at H level, and the output signals of the NOR logic parts64L and64R are retained at L level regardless of a signal level of the selection signal XWLA.

Hence, when the read (READ) operations are performed, the driving signal reflecting the signal level of the word line selection signal WLA is supplied to the A word lines (WLA_L/R), as illustrated inFIG. 9. At the same time, the driving signal supplied to the B word lines (WLB_L/R) is retained at L level, as illustrated inFIG. 9. That is, the B word lines (WLB_L/R) will not be activated when the read (READ) operations are performed.

Hence, since the B word lines (WLB_L/R) need not be activated when the read (READ) operations are performed, fundamentally unnecessary extra electrical power consumption will not be required for driving each of the pseudo-multiport bit cells30as single port memory as indicated by the oval broken line inFIG. 7.

Note that the final word line driver64of the SRAM60illustrated inFIG. 8includes the NOR logic parts64L and64R.

In general, when an inverter is fabricated with a large scale integrated circuit (LSI), a NOR circuit needs to have a size (an area) twice or more the size (the area) of the inverter. Hence, the electrical power consumption increases approximately in proportion to the size (the area) of the NOR circuit.

Further, in order for the two NOR logic parts64L and64R to output the driving signal having a signal level sufficient for the B word lines (WLB_L/R), the inverter65needs to have a size (an area) approximately around eight times of the NOR logic parts64L and64R. Hence, the electrical power consumption increases approximately in proportion to the size (the area) of the inverter65.

As described above, in the SRAM60illustrated inFIG. 8, even if the B word lines are not activated to perform the read (READ) operations, the electrical power consumption in the final word line driver64increases. Hence, the electrical power consumption will not be reduced as a total.

Accordingly, the electrical power consumption will not be reduced when the comparative examples of the SRAMs50and60including the pseudo-multiport bit cells30are operated as a single port memory.

The multiport bit cell30is operated as a single port memory. Hence, when a part of the multiport bit cells fabricated in a large scale integrated circuit (LSI) is operated as a single port bit cell, cost of the memory or the like may be reduced. In addition, it may be possible to cancel out fabrication variability in the bit cells operating as the multiport bit cells and the bit cells operating as the single port bit cells, and improve the operating properties.

Thus, it may be desirable to provide a semiconductor memory device capable of exhibiting reduced electrical power consumption.

Embodiment

FIG. 10is a diagram illustrating an information processing apparatus including a semiconductor memory device of an embodiment.

In the following, a description will be given of an embodiment in which an information processing apparatus serves as a server80.

As illustrated inFIG. 10, the server80includes a large scale integrated circuit (LSI)81, a main storage device82, and auxiliary storage device83. An interval between the LSI81and the main storage device82, and an interval between the main storage device82and the auxiliary device93may, for example, be connected by designated buses, respectively.

The LSI81includes a processor core91, a level 1 (L1, primary) instruction cache92, a L1 data cache93, a level 2 (L2, secondary) cache94, and a memory controller95.

The processor core91may, for example, be a central processing unit (CPU) core serving as an arithmetic processing unit configured to perform arithmetic processing of the server80as information processing apparatus. Note that the processor core91, the L1 instruction cache92, and the L1 data cache91may be integrated as a CPU. There may be two or more processor cores91. In this case, each of the processor cores91is connected one L1 instruction cache92and one L1 data cache93.

The L1 instruction cache92is a primary cache configured to temporarily store programs necessary for arithmetic processing of the processor core91. The L1 instruction cache92may, for example, be formed of an SRAM.

The L1 data cache93is a primary data cache configured to temporarily store data necessary for the arithmetic processing of the processor core91, or data generated as a result of the arithmetic processing. In this embodiment, a description will be given of a case in which an SRAM serving as the semiconductor memory device of the embodiment is applied to the L1 data cache93. Note that details of the structure of the embodiment will be described later.

The L2 cache94is a cache close to a main storage device92and located at a level lower than the L1 instruction cache92and the L1 data cache93in the memory hierarchical structure. The L2 cache94typically includes a processing speed lower than those of the L1 instruction cache92and the L1 data cache93; however, the L2 cache includes a large capacity. The L2 instruction cache94may, for example, be formed of an SRAM.

The memory controller95is a control device configured to perform control when the LSI performs data read operations or data write operations between the LSI and the main storage device82. The memory controller95may be formed of an LSI.

The main storage device82may, for example, be a dynamic random access memory (DRAM) and a read only memory (ROM), and the auxiliary storage device93may, for example, be a hard disk.

Note that the server80may include a data input/output interface configured to perform communications with external apparatuses.

FIG. 11is a diagram illustrating an SRAM100of an embodiment.FIG. 11illustrates not a physical arrangement of the SRAM100, but is a block diagram illustrating a connecting relationship of the components of the SRAM100.

The SRAM100of the embodiment is an example of the semiconductor memory device. The SRAM100may, for example, be used as the L1 data cache93illustrated inFIG. 10.

The SRAM100includes a sub array110, an address decoder120, a row selector130A, a sub array selector130B, and a column selector130C.

The SRAM100further includes a word line driver (WL driver)140, a final word line driver (final WL driver)150, and a global selector (global-R/W select)160.

The SRAM100further includes a local controller (local-R/W select & WL control)170, a local block (local-R/W block)180, and a global block (global-R/W block)190.

The sub array110includes a plurality of the pseudo-multiport bit cells30disposed in a matrix. The pseudo-multiport bit cell30is an example of a pseudo-multiport cell.

The sub array110is an example of a memory block. The bit cell30is similar to the respective bit cells30of the comparative examples of the SRAMs50and60, and includes a circuit configuration illustrated inFIG. 4. Hence, the description of the circuit configuration of the bit cell30will be omitted.

FIG. 11illustrated six bit cells30disposed at three columns in a column direction (i.e., in a horizontal direction inFIG. 11) and two rows in a row direction (in a vertical direction inFIG. 11). However, in practice, the sub array110includes further more bit cells30disposed in the column direction and in the row direction.

The sub array110includes two pairs of word lines WLA00 and WLB00, and WLA01 and WLB01; and three pairs of bit lines BL00 and BLB00, BL01 and BLB01, and BL02 and BLB02.

However, as described above, since the sub array110includes further more bit cells30, the sub array110includes further more word lines and bit lines.

Note that in the following description, the A word lines WLA00 and WLA01 and the B word lines WLB00 and WLB01 may be illustrated separately.

The connecting relationships between the bit cells30, the word lines WLA00, WLB00, WLA01, WLB01, and the bit lines BL00, BLB00, BL01, BLB01, BL02, BLB02 are similar to the connecting relationships between the bit cell30, the word line WLA_L and WLB_L, and bit lines BL and BLB illustrated inFIG. 4.

The address decoder120is supplied with an input address included in a read instruction and a write instruction. Output terminals of the address decoder120are connected to input terminals of the row selector130A, the sub array selector130B, and the column selector130C, respectively, via the signal lines101A,101B, and101C indicated by arrows.

The input address is supplied to the address decoder120from the processor core111of the server80including the SRAM100(seeFIG. 10as reference). The input address includes a row address for specifying a row, a sub array address for specifying a sub array, and a column address for specifying a column address.

The address decoder120decodes a row address, a sub array address, and a column address included in the input address to generate row selection data, sub array selection data, and column selection data.

The address decoder120outputs the row selection data, the sub array selection data, and the column selection data to a row selector130A, a sub array selector130B, a column selector130C, respectively.

An input terminal of the row selector130A is connected to the address decoder120via a signal line101A indicated by an arrow, and an output terminal of the row selector130A is connected to a word line driver140via a signal line102A indicated by an arrow.

The row selector130A is configured to transmit the row selection data from the address decoder120to the word line driver140. Note that the row selector130A may include a decoding function to decode a part of the input address associated with the row selection data.

An input terminal of the sub array selector130B is connected to the address decoder120via a signal line101B indicated by an arrow, and an output terminal of the sub array selector130B is connected to the word line driver140and a local controller170via signal lines102B and102C indicated by arrows.

The sub array selector130B is configured to transmit the sub array selection data from the address decoder120to the word line driver140and the local controller170. The sub array selector130B is an example of a block selector to select a sub array110A serving as an example of a memory block.

Note that the sub array selector130B may include a decoding function to decode a part of the input address associated with the sub array selection data.

An input terminal of the column selector130C is connected to the address decoder120via a signal line101C indicated by an arrow, and an output terminal of the column selector130C is connected to a local block180via a signal line102D indicated by an arrow.

The column selector130C is configured to transmit the column selection data from the address decoder120to the local controller170. Note that the column selector130C may include a decoding function to decode a part of the input address associated with the column selection data.

The word line driver (WL driver)140may be an example of the first word line driver. An input terminal of the word line driver140is connected to the row selector130A and the sub array selector130B via signal lines102A and102B indicated by arrows, respectively. An output terminal of the word line driver140is connected to a final word line driver150via a signal line103A indicated by an arrow.

The word line driver140is configured to generate a word line selection signal WLA based on the row selection data input from the row selector130A and the sub array selection data input from the sub array selector130B. The word line driver140inputs the word line selection signal WLA into the final word line driver150.

The final word line driver (final WL driver)150is configured to select a row (i.e., selects a word line) based on the word line selection signal WLA input from the word line driver140and the switching signal R/W input from the local controller170.

The global selector (global-R/W select)160is configured to receive a write enable signal WE from the processor core111(seeFIG. 10) of the server80including the SRAM100.

An output terminal of the global selector160is connected to the local controller170via a signal line104indicated by an arrow. Note that inFIG. 11, only one local controller170is illustrated; however, in practice, there are two or more local controllers170. The global selector160is configured to distribute the write enable signal WE to the plural local controllers170.

An input terminal of the local controller (local-R/W select & WL control)170is connected to respective output terminals of the sub array selector130B and the global selector160via the signal lines102B and104indicated by arrows, respectively. An output terminal of the local controller170is connected to the final word line driver150and the local block180via the signal lines103B and105indicated by arrows, respectively.

The local controller170is configured to generate a switching signal R/W based on the write enable selection data input from the sub array selector130B and the write enable signal WE input from the global selector160. The local controller170outputs the switching signal R/W into the final word line driver150.

Further, the local controller170is configured to generate read/write control signals based on the write enable signal WE input from the global selector160. The local controller170is configured to output the read/write control signals to the local block180via the signal line105indicated by an arrow.

Note that the local controller170is an example of a controller.

An input terminal of the local block (local-R/W block)180is connected to the column selector130and the local controller170via the signal lines102D and105indicated by arrows, respectively. Further, a data input terminal of the local block180is connected to a global block190via a global bit line191, and a data output terminal of the local block180is connected to the global block190via a global bit line192.

Further, the local block180is connected to the bit cells30of the sub array110via the bit lines BL00, BLB00, BL01, BLB01, BL02, and BLB02.

The local block180is configured to retrieve data from or write data into the bit cells30of the sub array110based on the column selection data input from the column selector130C and the read/write control signals input from the local controller170.

The global block (global-R/W block)190is configured to perform data communications between the local block180, and the processor core91of the server80(seeFIG. 10) and the L2 cache94.

In the following, a description is given of a physical arrangement and a connecting relationship of the SRAM100with reference toFIG. 12.

FIG. 12is a first diagram illustrating the physical arrangement of the SRAM100of an embodiment. Note that inFIG. 12, the elements similar to those illustrated inFIG. 11are designated by the same reference numerals, and their descriptions will thus be omitted.

FIG. 12illustrates a physical arrangement and connecting relationship of the sub arrays110A,110B, the word line driver140, and the final word line driver150of the SRAM100.

The configurations of the sub arrays110A and110B are similar to that of the sub array110illustrated inFIG. 11. InFIG. 12, only two sub arrays110A and110B are illustrated; however, in practice, there are further more sub arrays inside the SRAM100.

The word line driver140includes a NAND logic part140A. The NAND logic part140A is supplied with a word line selection signal WLA and an enable signal ENA_A. The word line selection signal WLA is a selection signal for selecting a specific word line WLA_L of the plural word lines WLA_L and a specific word line WLA_R of the plural word lines WLA_R. The enable signal ENA_A is an enabling signal for activating the word lines WLA_L and WLA_R.

Note that the word lines WLA_L and WLB_L correspond to the word lines WLA00 and WLA01 illustrated inFIG. 11.

The final word line driver150includes the inverters151AL and151AR, a NOR logic part152, and inverters153,154L, and154R. The word line driver (WL driver)150may be an example of the second word line driver.

Input terminals of the inverter151AL and151AR and one of input terminals of the NOR logic part152(input terminal on a left hand side inFIG. 12) are connected to an output terminal of the NAND logic part140A of the word line driver140.

Respective output terminals of the inverters151AL and151AR are connected to word lines WLA_L and WLA_R of the sub arrays110A and110B.

Note that the inverters151AL and151AR are examples of output parts configured to output the word line selection signal WLA to one (A word line) of the pair of the word lines (A word line and B word line) of the bit cells30included in the sub arrays110A and110B.

A first input terminal of the NOR logic part152(input terminal on a left hand side inFIG. 12) is connected to an output terminal of the NAND logic part140A of the word line driver140, and a second input terminal (input terminal on a right hand side inFIG. 12) of the NOR logic part152is connected to an output terminal of the inverter170A.

Note that the NOR logic part152is an example of a NOR logic part configured to output a result of NOR (i.e., negation of logical OR) of the word line selection signal WLA and the switching signal R/W to the other one (B word line) of the pair of the word lines (i.e., the pair of A word line and B word line).

The inverter170A is included in the local controller170illustrated inFIG. 11, and configured to output the switching signal R/W to a second input terminal of the NOR logic part152. Note that the connecting relationship on the input side of the inverter140A will be described later.

The switching signal R/W is an example of a read/write selection signal configured to write into or retrieve from the bit cells30.

An output terminal of the NOR logic part152is connected to an input terminal of the inverter153.

An output terminal of the inverter153is connected to input terminals of the inverters154L and154R. Output terminals of the inverters154L and154R are connected to the word lines WLB_L and WLB_R of the sub arrays110A and110B, respectively.

Note that the word lines WLB_L and WLB_L correspond to the word lines WLB00 and WLB01 illustrated inFIG. 11.

Next, a description is given of a physical arrangement and a connecting relationship of the sub array110, the row selector130A, the sub array selector130B, the column selector130C, the word line driver140, the final word line driver150, the local controller170, and the local block180of the SRAM100.

FIG. 13is a second diagram illustrating the physical arrangement of the SRAM100of an embodiment. Note that inFIG. 13, the elements similar to those illustrated inFIGS. 11 and 12are designated by the same reference numerals, and their descriptions will thus be omitted.

FIG. 13illustrates the sub arrays110A,110B,110C,110D, the selector130, the word line drivers140A,140B, and the final word line drivers150A, and150B.

FIG. 13further illustrates the local controller170, and local blocks180A and180B.

FIG. 14illustrates configurations of the four sub arrays110A,110B,110C, and110D, each of which is similar to that of the sub array110illustrated inFIG. 11. In this case, 16 sub arrays (sub array 0 to sub array 15) are disposed in a vertical direction inFIG. 13. The sub arrays110C and110A correspond to the 15thsub array (i.e., sub array 14), and the 16thsub array (i.e., sub array 15). Likewise, the sub arrays110D and110B correspond to the 15thsub array (i.e., sub array 14), and the 16thsub array (i.e., sub array 15).

Note that the sub arrays110A and110B correspond to the sub arrays110A and110B illustrated inFIG. 12.

The selector130represents the row selector130A, the sub array selector130B, and the column selector130C as one block. The row selector130A, the sub array selector130B, and the column selector130C may be implemented as one block inside the actual LSI.

Note that in this example, the row selector130A, the sub array selector130B, and the column selector130C are represented by one selector130(one block). However, the row selector130A, the sub array selector130B, and the column selector130C may alternatively be implemented as separate blocks, or may be incorporated into the address decoder120illustrated inFIG. 11.

FIG. 13illustrates, of the components of the selector130, the inverters131A,131B,132A,132B,133A, and133B. The inverters131A,131B,132A,132B,133A, and133B are included in the sub array selector130B illustrated inFIG. 11.

The inverters131A and131B are supplied with sub array selection data (sub array select 14, 15) from the address decoder120illustrated inFIG. 11. An output terminal of the inverter131A is connected to input terminals of the inverters132A and133A, and an output terminal of131B is connected to input terminals of the inverters132B and133B.

An output terminal of the inverter132A is connected to a first input terminal (an upper input terminal inFIG. 13) of the NAND logic part171A of the local controller170. Likewise, an output terminal of the inverter132B is connected to a first input terminal (an upper input terminal inFIG. 13) of the NAND logic part171B of the local controller170.

The inverters133A and133B are, in practice, connected to a local controller (i.e., the local controller similar to the local controller170illustrated inFIG. 13) residing on a left hand side of the selector130inFIG. 13.

The configurations of the word line drivers140A and140B are similar to that of the word line driver140illustrated inFIG. 11.FIG. 13illustrates two word line drivers140A and140B.

Note that the word line drivers140A corresponds to the word line driver140illustrated inFIG. 12.

The configurations of the final word line drivers150A and150B are similar to that of the final word line driver150illustrated inFIG. 11. The final word line driver150A of the two final word line drivers150A and150B corresponds to the final word line driver150illustrated inFIG. 12.

The local controller170includes inverters170A1,170A2, NAND logic parts171A,171B, and inverters172,173,174and175.

Respective input terminals of the inverters170A1and170A2are connected to the output terminals of the NAND logic parts171A and171B, respectively. An output terminal of the inverter170A1is connected to a second input terminal (an input terminal on the left hand side inFIG. 12) of the NOR logic part152of the final word line driver150A. The inverter170A1corresponds to the inverter170A illustrated inFIG. 12.

Likewise, an output terminal of the inverter170A2is connected to a second input terminal of the NOR logic part of the final word line driver150B.

The inverters170A1and170A2are configured to output the switching signal R/W to the second input terminal of the NOR logic part152of the final word line drivers150A and150B.

First input terminals (upper input terminals inFIG. 13) of the NAND logic parts171A and171B are connected to output terminals of the inverter132A and132B of the selector130, respectively. Second input terminals (lower input terminals inFIG. 13) of the NAND logic parts171A and171B are both connected to an output terminal of the inverter174.

Note that a combination of the inverter170A1and the NAND logic part171A and a combination of the inverter170A2and the NAND logic part171B each are examples of an AND logic part.

The inverter172is supplied with the write enable signal WE distributed inside the global selector160illustrated inFIG. 11. An output terminal of the inverter172is connected to input terminals of the inverters172and174.

An input terminal of the inverter173is connected to an output terminal of the inverters172, and an output terminal of the inverter173is connected to the local block180A. The inverter173is configured to output a READ signal of the read/write control signals to the local block180A.

An input terminal of the inverter174is connected to an output terminal of the inverter172, and an output terminal of the inverter174is connected to second input terminals (lower input terminals inFIG. 13) of the NAND logic parts171A and171B.

An input terminal of the inverter175is connected to an output terminal of the inverters174, and an output terminal of the inverter175is connected to the local block180A. The inverter175is configured to output a WRITE signal of the read/write control signals to the local block180A.

Note thatFIG. 13illustrates a circuit configuration of a part in which the READ signal and the WRITE signal are respectively output to the inverters173and175of the local controller170for convenience of illustration. However, the local controller170is also configured to output the READ signal and the WRITE signal of the read/write control signals to the local block180B.

The configurations of the local blocks180A and180B are similar to that of the local block180illustrated inFIG. 11. Of the local blocks180A and180B, the local block180A corresponds to the local block180illustrated inFIG. 11.

Next, a description will be given, with reference toFIG. 14, of a configuration of the SRAM100including the address decoder120, the global selector16, and the global block190illustrated inFIG. 11.

FIG. 14is a third diagram illustrating the SRAM100of an embodiment. Note that inFIG. 14, the elements similar to those illustrated inFIGS. 11 to 13are designated by the same reference numerals, and their descriptions will thus be omitted.

FIG. 14illustrates the sub arrays110A,110B,110C,110D, the address decoder120, the selector130, the word line drivers140A,140B, and the final word line drivers150A, and150B.

FIG. 14further illustrates the global selector160, the local controller170, the local blocks180A and180B, and the local blocks190A and190B.

The configurations of the sub arrays110A,110B,110C, and110D are similar to those of the sub arrays110A,110B,110C, and110D illustrated inFIG. 13. InFIG. 14, the word lines WLA_L, WLA_R, WLB_L, and WLB_R are typically illustrated for the sub arrays110A and110B in a manner similar toFIG. 12.

The address decoder120decodes a row address, a sub array address, and a column address included in the input address to generate row selection data, sub array selection data, and column selection data. InFIG. 14, the sub array selection data (sub array select) alone is illustrated. The sub array selection data are an example of data represented by the memory block selection signal.

Only the inverters131A,131B,132A,132B,133A, and133B are illustrated for the selector130inFIG. 14, and the inverters131B,132B, and133B illustrated inFIG. 13are omitted inFIG. 14.

The configurations of the word line drivers140A and140B are similar to those of the word line drivers140A and140B illustrated inFIG. 13; however, the word line driver140A is illustrated in a size the same as the size of the word line driver140illustrated inFIG. 11.

The configurations of the final word line drivers150A and150B are similar to those of the final word line drivers150A and150B illustrated inFIG. 13. InFIG. 14, the internal circuits (i.e., the inverters151AL and151AR, a NOR logic part152, and inverters153,154L, and154R) are illustrated for the final word line driver150A in a manner similar to the final word line driver150illustrated inFIG. 11.

The global selector160is disposed between the global blocks190A and190B. The global selector160includes inverters161,162A, and162B.

The inverter161is supplied with the write enable signal WE transmitted from the processor core111(seeFIG. 10) of the server80including the SRAM100. An output terminal of the inverter161is connected to input terminals of the inverters162A and162B.

An input terminal of the inverter162A is connected to an output terminal of the inverters161, and an output terminal of the inverter162A is connected to an input terminal of the inverter172of the local controller170.

The write enable signal WE supplied to the inverter161is distributed to the inverters162A and162B at an output side of the inverter161, and the write enable signal WE distributed to the inverters162A and162B is output from the global selector160.

An output signal of the inverter162has a phase the same as the write enable signal WE, and hence, the inverter172of the local controller170is supplied with the write enable signal WE distributed inside the global selector160.

The configuration of the local controller170is similar to that of the local controller170illustrated inFIG. 13; however, inFIG. 14, only the inverter170A1, and the NAND logic part171A, and the inverters172,173,174and175are illustrated, and the inverter170A2, and the NAND logic part171B illustrated inFIG. 13are omitted fromFIG. 14.

The configurations of the local blocks180A and180B are similar to those of the local blocks180A and180B illustrated inFIG. 13.

The configurations of the local blocks180A and180B are similar to that of the local block190illustrated inFIG. 11. The global blocks190A and190B are disposed one on each side of the global selector160.

The global block190is configured to perform data communications between the local block180A, and the processor core91of the server80(seeFIG. 10) and the L2 cache94. Likewise, the global block190B is configured to perform data communications between the local block180B, and the processor core91of the server80(seeFIG. 10) and the L2 cache94.

Next, a description is given of data writing and reading operations in the SRAM100of an embodiment.

When data are written (WRITE) into the SRAM100, the L level write enable signal WE is supplied to the inverter161of the global selector160. Hence, the write enable signals WE distributed by the global selector160are switched to L level.

When the L level write enable signal WE is supplied to the inverter172of the local controller170, the READ signal of the read/write control signals output by the inverter173is switched to L level whereas the WRITE signal of the read/write control signals output by the inverter175is switched to H level.

At this time, since the output signal of the inverter174is at L level, an input signal of the second input terminal (an input terminal on the right hand side inFIG. 13) of the NAND logic part171A is switched to L level. Further, at this time, since the sub arrays110A and110B are selected, the sub array selection data (sub array select 15) input to the selector130from the address decoder120are at H level.

Hence, the output signal of the NAND logic part171A is switched to H level. This is because the NAND logic part171A operates a NAND of the sub array selection data (sub array select 15) and the output of the inverter174based on the write enable signal WE.

As a result, the switching signal R/W output from the inverter170A1of the local controller170is switched to L level.

The L level switching signal R/W output from the inverter170A1of the local controller170is supplied to a second input terminal (an input terminal on the right hand side inFIG. 14) of the NOR logic part152of the final word line driver150.

When the L level switching signal R/W is supplied to the input terminal (the input terminal on the right hand side inFIG. 14) of the NOR arithmetic unit152, the output signal of the NOR logic part152is switched to an inverted signal level of the signal level of the selection signal XWLA input to the first input terminal (the input terminal on the left hand side inFIG. 14) of the NOR logic part152.

Note that the signal level of the selection signal XWLA is an inverted signal level of the signal level of the word line selection signal WLA. Hence, when data are written (WRITE) into the SRAM100, a signal level of the output signal of the NOR logic part152is equal to a signal level of the word line selection signal WLA. That is, the signal level of the output signal of the NOR logic part15is switched between the H level and L level according to the signal level of the word line selection signal WLA.

The output signal of the NOR logic part152inverted twice, first at the inverter153and then at the inverters154L and154R, and the inverted signals are output to the word lines WLB_L and WLB_R. That is, the word lines WLB_L and WLB_R are supplied with the control signals having a signal level equal to that of the word line selection signal WLA.

As a result, to write the data into the SRAM100(to perform data writing (WRITE) operations), the word lines WLB_L and WLB_R are activated when the word line selection signal WLA is at H level, and deactivated when the word line selection signals WLA is at L level.

Note that the word lines WLA_L and WLA_R are supplied with the inverted selection signals XWLA output from the inverters151AL and151AR. Hence, the word lines WLA_L and WLA_R are activated when the word line selection signal WLA is at H level, and deactivated when the word line selection signal WLA is at L level.

As described above, to write the data into the SRAM100(to perform data writing (WRITE) operations), the word lines WLA_L, WLA_R, WLB_L and WLB_R are activated when the word line selection signals WLA are at H level.

Hence, data may be written into the storage nodes N1and N2(seeFIG. 4) of the pseudo-multiport bit cell30.

Next, a description is given of data reading operations in the SRAM100.

When data are retrieved (READ) from the SRAM100, the H level write enable signal WE is supplied to the inverter161of the global selector160. Hence, the write enable signals WE distributed by the global selector160are switched to H level.

When the H level write enable signal WE is supplied to the inverter172of the local controller170, the READ signal of the read/write control signals output by the inverter173is switched to H level whereas the WRITE signal of the read/write control signals output by the inverter175is switched to L level.

At this time, since the output signal of the inverter174is at H level, an input signal of the second input terminal (an input terminal on the right hand side inFIG. 13) of the NAND logic part171A is switched to H level. Further, at this time, since the sub arrays110A and110B are selected, the sub array selection data (sub array select 15) input to the selector130from the address decoder120are at H level.

Hence, the output signal of the NAND logic part171A is switched to L level. As a result, the switching signal R/W output from the inverter170A1of the local controller170is switched to H level.

The H level switching signal R/W output from the inverter170A1of the local controller170is supplied to the second input terminal (the input terminal on the right hand side inFIG. 14) of the NOR logic part152of the final word line driver150.

When the H level switching signal R/W is supplied to the input terminal (the input terminal on the right hand side inFIG. 14) of the NOR arithmetic unit152, the output signal of the NOR logic part152is switched L level regardless of the signal level of the selection signal XWLA input to the first input terminal (the input terminal on the left hand side inFIG. 14) of the NOR logic part152.

The output signal of the NOR logic part152inverted twice, first at the inverter153and then at the inverters154L and154R, and the inverted signals are output to the word lines WLB_L and WLB_R. That is, the word lines WLB_L and WLB_R constantly receive the L level control signals.

As a result, when data are retrieved (READ) from the SRAM100, the word lines WLB_L and WLB_R are constantly retained at L level and deactivated.

Note that the word lines WLB_L and WLB_R are supplied with the inverted selection signals XWLA output from the inverters151AL and151AR. Hence, the word lines WLA_L and WLA_R are activated when the word line selection signal WLA is at the H level, and deactivated when the word line selection signal WLA is at the L level.

As described above, to read the data into the SRAM100(to perform data reading (READ) operations), the word lines WLA_L and WLA_R are activated when the word line selection signal WLA is at H level. Further, at this moment, the word lines WLB_L and WLB_R are constantly retained at L level, and deactivated.

Hence, data retained in the storage nodes N1and N2(seeFIG. 4) of the pseudo-multiport bit cell30may be retrieved.

As described above, data may be written into the storage nodes N1and N2(seeFIG. 4) of the pseudo-multiport bit cell30by activating the A word lines (WLA_L/R) and the B word lines (WLB_L/R).

On the other hand, data retained in the storage node N2(seeFIG. 4) of the pseudo-multiport bit cell30may be retrieved by activating the A word lines (WLA_L/R) without activating the B word lines (WLB_L/R).

That is, the SRAM100having the pseudo-multiport bit cells30is operated as single port memory.

The aforementioned data writing (WRITE) operations and reading (READ) operations in the SRAM100are similar to the data writing (WRITE) operations and reading (READ) operations (see FIG.9) of the comparative example of SRAM60(seeFIG. 8).

Further, the SRAM100of the embodiment may be able to reduce electrical power consumption according to the following reasons.

The final word line driver150A has a configuration of the comparative example of the SRAM50illustrated inFIG. 6to which the NOR logic part152and the inverter153are added.

Note that the final word line driver150A includes the inverter153at an output side of the NOR logic part152. Further, the inverters154L and154R are connected to the output side of the inverter153.

When the inverters154L and154R are connected to the output side of the inverter153, the size of the inverter153may be reduced by one-fourth of a total size of the inverters154L and154R due to a so-called Fan Out of Four (FO4) effect.

In addition, the size of the NOR logic part152may be reduced by one-fourth of the inverter153by connecting the inverter153to the output side of the NOR logic part152.

Further, there are 16 pairs of the A word lines (WLA_L/R) and B word lines (WLB_L/R) in each of the sub arrays110A and110B. That is, there are 16 NOR logic parts152in each of the final word line drivers150A. A common (one) inverter170A1is connected to the second input terminals (e.g., the input terminal on the right hand side inFIG. 14) of the 16 NOR logic parts152.

Hence, the size of the inverter170A1may be reduced by one-fourth of the size of the 16 NAND logic parts170A1due to the so-called FO4 effect.

In addition, the inverter170A1is connected to an output side of the inverter171. Hence, the size of the inverter171may be reduced by one-fourth of the size of the inverter170A1due to the FO4 effect.

For example, the size of each of the inverters151AL,151AR,154L, and154R is determined as “8”. Since the inverter153supplies the control signals to the inverters154L and154R, it is sufficient that the size of the inverter153is “4” (=(“8”+“8”)/4), and the size of the NOR logic part152is “1”, due to the FO4 effect.

Further, in this case, there are 16 NOR logic parts152having the size of “1”, and the size of the inverter170A1is one-fourth of a total size of 16 NOR logic parts152. Thus, the size of the inverter170A1is “4”.

Further, the size of the inverter171A is one-fourth of the size of the inverter170A1, so the size of the inverter171A is “1”.

Note that the sizes of the NOR logic parts64L and64R of the final word line driver64of the SRAM60illustrated inFIG. 8are both “8”. Hence, it may be necessary that the size of the inverter65illustrated inFIG. 8is “64”.

As described above, in the SRAM100of the embodiment, the NOR logic part152and the inverter153of the final word driver150A may be reduced in size. Hence, the final word driver150A of the SRAM100may be able to reduce electrical power consumption compared to electrical power consumed by the final word line driver64of the comparative example of the SRAM60illustrated inFIG. 8. Note that the final word line driver150B may be able to reduce electrical power consumption in a manner similar to the electrical power consumption reduced by the final word line driver150A.

In addition, the size (i.e., “4”) of the inverter170A1of the local controller170is 1/16 of the size (i.e., “64”) of the inverter65in the SRAM60illustrated inFIG. 8. Hence, the electrical power consumption may further be reduced due to the reduction in size of the inverter171A1.

As described above, it may be possible to reduce the electrical power consumption while the SRAM100having the pseudo-multiport bit cells30is operated as single port memory.

Further, in the SRAM100of the embodiment, the A word lines (WLA_L/R) is activated via the inverters151AL and151AR of the final word line driver150A to retrieve data. In the comparative example of the SRAM50illustrated inFIG. 6and the comparative example of the SRAM60, the data are retrieved in a manner similar to the SRAM100of the embodiment as described above. Hence, the speed of retrieving (reading) the data is similar to those of the comparative examples of the SRAMs50and60illustrated inFIGS. 6 and 8, respectively.

On the other hand, in the SRAM100of the embodiment, the B word lines (WLB_L/R) is activated via the NOR logic part152, the inverters151AL and151AR of the final word line driver150A to write data.

This indicates that the B word lines (WLB_L/R) is delayed by the NOR logic part152and the inverter153, compared to the SRAM50illustrated inFIG. 6.

However, in the SRAMs that generally exhibit higher data reading/writing speeds, the data writing speed does not become much interfered with compared to the data reading speed.

Accordingly, an adverse effect on the data writing speed due to the SRAM having the NOR logic part152and the inverter153may be minimum, thereby little affecting the reading/writing operations.

Further, the SRAM100having the pseudo-multiport bit cells30may be able to reduce electrical power consumption while being operated as single port memory.

Hence, memory fabrication cost may be reduced by forming memory for performing multiport operations and the SRAM100capable of being operated as a single port.

In addition, it may be possible to cancel out fabrication variability in the bit cells operating as the multiport bit cells and the bit cells operating as the single port bit cells, and improve the operating properties.

According to the embodiments, it may be possible to provide the semiconductor memory device capable of exhibiting reduced power consumption and the information processing apparatus having such a semiconductor memory device.