Memory system and operating method thereof

A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2016-0108092, filed on Aug. 25, 2016, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a memory system and, more particularly, to a memory system which processes data to a memory device and an operation method thereof.

2. Description of the Related Art

Recently, the paradigm of the computer environment is changed into a ubiquitous computing environment which allows users to get an access to a computer system anywhere and anytime. For this reason use of portable electronic devices, such as mobile phones, digital cameras laptop computers and the like, is surging. Portable electronic devices generally employ a memory system using a memory device for storing data, i.e., is a data storage device. A data storage device may be used as a main memory device or an auxiliary memory device of a portable electronic device.

A data storage device using a memory device has excellent stability and durability because the data storage device does not include a mechanical driving unit. Also, the data storage device using a memory device is advantageous in that it may access data quickly and consume a small amount of power. Non-limiting examples of the data storage device having these advantages include a Universal Serial Bus (USB) memory device, a memory card with various interfaces, a Solid-State Drive (SSD) and so forth.

With the development of technology, high density/high capacity memory devices have been developed which employ an increased number of word lines (WL). When all word lines in a memory device are not filled with data, for example, when parts of word lines have no data programmed therein, the distribution characteristic of memory cells in the memory device may be changed and may distort a read bias.

SUMMARY

Various embodiments are directed to a memory system capable of grouping word lines of a memory device into a plurality of groups and adjusting a read bias depending on the amount (or ratio) of data programmed in each of the word line groups, and an operating method thereof.

In an embodiment a memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.

In an embodiment, a memory system may include: a memory device; and a controller coupled to the memory device, and suitable for enabling a flag cell read operation for an open block of the memory device during a read mode. The memory device may include: a memory cell array comprising a plurality of search regions, wherein each of the search regions comprises a plurality of group regions, and each of the group regions comprises a flag cell indicating whether program is completed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for checking that a flag cell read operation is enabled when a read command is received, generating the voltage control signal for an adjusted read bias voltage based on flag cell information of the corresponding search region among the plurality of search regions when the flag cell read operation is enabled, and controlling a read operation for the memory cell array based on the adjusted read bias voltage.

In an embodiment, there is provided an operating method of a memory device which includes a memory cell array including a plurality of search regions, wherein each of the search regions comprises a plurality of group regions and each of the group regions comprises a flag cell indicating whether the corresponding group region is programmed. The operating method may include: receiving a read command; adjusting a read bias voltage of a corresponding search region, based on flag cell information of the group regions of the search region; and controlling a read operation for the memory cell array based on the read bias voltage.

In an embodiment, an operating method of a memory system may include: checking block information during a read mode, enabling a flag cell read operation for an open block of a memory device, and generating a read command; generating a read bias voltage which is adjusted based on flag cell information of a corresponding search region of a memory cell array, when the read command is generated and the flag cell read operation is enabled, and controlling a read operation for the memory cell array based on the read bias voltage. The memory cell array may include a plurality of search regions each of the search regions may include a plurality of group regions, and each of the group regions may include a flag cell indicating whether program is completed.

DETAILED DESCRIPTION

It is noted that the drawings are simplified schematic and as such are not necessarily drawn to scale. In some instances, various parts of the drawings may have been exaggerated in order to more clearly illustrate certain features of the illustrated embodiments.

It is further noted that in the following description, specific details are set forth for facilitating the understanding of the present invention, however, the present invention may be practiced without some of these specific details. Also, it is noted, that well-known structures and/or processes may have only been described briefly or not described at all to avoid obscuring the present disclosure with unnecessary well known details.

It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, an element (also referred to as a feature) described in connection with one embodiment may be used singly or in combination with other elements of another embodiment, unless specifically indicated otherwise.

Hereafter, various embodiments will be described below in more detail with reference to the accompanying drawings.

FIG. 1illustrates a data processing system100including a memory system, according to an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may also include a host102operatively coupled to the memory system110.

The host102may be any suitable electronic device. The host102may be or include, for example, a portable electronic device such as a mobile phone, an MP3 player and a laptop computer or a non-portable electronic device such as a desktop computer, a game player, a television (TV) and a projector.

The memory system110may operate in response to a request from the host102. For example, the memory system110may store data provided by the host102and the memory system110may also provide stored data to the host102. Data which are stored in the memory system may be accessed by the host102. The memory system110may be used as a main memory or an auxiliary memory of the host102. The memory system110may be implemented with any one of various storage devices, according to the protocol of a host interface to be coupled electrically with the host102. The memory system110may be implemented with any one of various storage devices such as, for example, a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro-MMC a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like.

The memory system110may include a memory device150and a controller130. The memory device150may store data which may be accessed by the host102. The controller130may control data exchange between the memory device150and the host102. For example, under the control of the controller130, data received from the host102may be stored in the memory device150and stored data in the memory device150may be read and transmitted to the host102.

The controller130an the memory device150may be integrated into one semiconductor device. For instance, the controller130and the memory device150may be integrated into one semiconductor device to form a solid state drive (SSD). When the memory system110is used as an SSD, the operation speed of the host102that is electrically coupled with the memory system110may be significantly increased.

The controller130and the memory device150may be integrated into one semiconductor device to form a memory card, such as, for example, a Personal Computer Memory Card International Association (PCMCIA) card, a compact flash (CF) card, a smart media card (SMC), a memory stick, a multimedia card (MMC), an RS-MMC, a micro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD, an SDHC, and a universal flash storage (UFS) device.

In another instance, the memory system110may be or may be included in a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage for a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices for a home network, one of various electronic devices for a computer network, one of various electronic devices for a telematics network, an RFID device, or one of various component elements for a computing system.

The memory device150may retain stored data even when power is blocked, store the data provided from the host102during a write operation, and provide stored data to the host102during a read operation. The memory device150may include a plurality of memory blocks152,154and156. Each of the memory blocks152,154and156may include a plurality of pages. Each of the pages may include a plurality of memory cells which are electrically coupled to a word line (WL). The memory cells may be single bit cells or multi-bit cells. The memory cells may be arranged in a two or three dimensional stacked structure. The memory device150may be a nonvolatile memory device, for example, a flash memory. The flash memory may have a three-dimensional (3D) stack structure. An exemplary configuration of the memory device150and an exemplary three-dimensional (3D) stack structure of the memory device150will be described later in detail with reference toFIGS. 2 to 4.

The controller130of the memory system110may control the memory device150in response to a request from the host102. The controller130may provide the data read from the memory device150, to the host102, and store the data provided from the host102into the memory device150. To this end, the controller130may control the overall operations of the memory device150including operations such as read, write program, and erase operations.

For example, the controller130may include a host interface (I/F) unit132, a processor134, an error correction code (ECC) unit138, a power management unit (PMU)140, a NAND flash controller (NFC)142, and a memory144.

The host interface unit132may process commands and data provided from the host102, and may communicate with the host102through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-e), serial attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), and integrated drive electronics (IDE).

The ECC unit138may detect and correct errors in the data read from the memory device150during the read operation. The ECC unit138may not correct error bits when the number of the error bits is greater than a threshold number of correctable error bits, and may output an error correction fail signal indicating failure in correcting the error bits.

The ECC unit138may perform an error correction operation based on any suitable method including a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC unit138may include all circuits, systems or devices for the error correction operation.

The PMU140may provide and manage power for the controller130, that is, power for the component elements included in the controller130.

The NFC142may serve as a memory interface between the controller130and the memory device150to allow the controller130to control the memory device150in response to a request from the host102. The NFC142may generate control signals for the memory device150and process data under the control of the processor134when the memory device150is a flash memory and, in particular, when the memory device150is a NAND flash memory. It is noted that a different memory interface may be employed depending upon the type of memory device employed.

The memory144may serve as a working memory of the memory system110and the controller130. The memory144may store data for driving the memory system110and the controller130. The controller130may control the memory device150in response to a request from the host102. For example, the controller130may provide data read from the memory device150to the host102and store the data provided from the host102in the memory device150. When the controller130controls an operation of the memory device150such as, for example, a read, write, program and erase operation, the memory144may store data which are used by the controller130and the memory device150for the operation.

The memory144may be implemented with a volatile memory such as, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above the memory144may store data used by the host102and the memory device150for an operation including a read and a write operation. For storing the data, the memory144may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like.

The processor134may control the general operations of the memory system110, and a write operation or a read operation for the memory device150, in response to a write request or a read request received from the host102, respectively. For example, the processor134may drive firmware, which is referred to as a flash translation layer (FTL), to control the general operations of the memory system110. The processor134may be implemented, for example, with a microprocessor or a central processing unit (CPU).

A management unit (not shown) may be included in the processor134for performing bad block management of the memory device150. The management unit may find bad memory blocks included in the memory device150, which are in unsatisfactory condition for further use, and perform bad block management on the bad memory blocks. When the memory device150is a flash memory, for example, a NAND flash memory, a program failure may occur during a program operation, due to characteristics of a NAND logic function. During the bad block management, the data of the program-failed memory block or the bad memory block may be programmed into a new memory block. Bad blocks due to program fails may seriously deteriorate the utilization efficiency of a 3D stack structure memory device150and the reliability of the memory system100, and thus reliable bad block management is typically employed. Bad block management is well known in the art and hence it will not be described herein in any further detail.

FIG. 2is a diagram illustrating an exemplary configuration of the memory device150shown inFIG. 1.

Referring toFIG. 2, the memory device150may include a plurality of memory blocks. For example, the memory device150may include a zeroth memory block (BLOCK0)210, a first memory block (BLOCK1)220, a second memory block (BLOCK2)230and an N−1thmemory block (BLOCKN−1)240. Each of the memory blocks210to240may include a plurality of pages, for example, 2Mnumber of pages (2MPAGES). Each of the pages may include a plurality of memory cells which are electrically coupled to a word line.

Also, the memory device150may include a plurality of memory blocks, as single level cell (SLC) memory blocks and/or multi-level cell (MLC) memory blocks, according to the number of bits which may be stored or expressed in each memory cell. The SLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing 1-bit data. The MLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing multi-bit data, for example, plurality-bit data. An MLC memory block including a plurality of pages which are implemented with memory cells that are each capable of storing 3-bit data may also be referred to as a triple level cell (TLC) memory block.

Each of the memory blocks210to240may store the data provided from the host102during a write operation, and provide the stored data to the host102during a read operation.

FIG. 3is a diagram illustrating a memory device150including the memory block shown inFIG. 2. For example,FIG. 3shows a detailed configuration of a single memory block330of the memory device150and circuits310and320related thereto.

Referring toFIG. 3, the memory block330may include a plurality of cell strings340which are electrically coupled to a plurality of corresponding bit lines BL0to BLm−1, respectively. The cell string340of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cell transistors MC0to MCn−1 may be electrically coupled in series between the select transistors SST and DST. The respective memory cells MC0to MCn−1 may be configured by multi-level cells (MLC) each of which stores data information of a plurality of bits. For reference, inFIG. 3, ‘DSL’ denotes a drain select line (i.e., a string select line), ‘SSL’ denotes a source select line (i.e., a ground select line), and ‘CSL’ denotes a common source line.

WhileFIG. 3shows, as an example, the memory block330which is configured by NAND flash memory cells, it is to be noted that the memory block330of the memory device300is not limited to NAND flash memory. For example, the memory block330may also be realized by a NOR flash memory, a hybrid flash memory in which at least two kinds of memory cells are combined, or a one-NAND flash memory in which a controller is built in a memory chip. The operational characteristics of a semiconductor device may be applied to not only a flash memory device in which a charge storing layer is configured by conductive floating gates but also a charge trap flash (CTF) in which a charge storing layer is configured by a dielectric layer.

A voltage supply block310of the memory device300may provide word line voltages, for example, a program voltage, a read voltage and a pass voltage, to be supplied to respective word lines according to an operation mode and voltages to be supplied to bulks, for example, well regions, where the memory cells are formed. The voltage supply block310may perform a voltage generating operation under the control of a control circuit (not shown). The voltage supply block310may generate a plurality of variable read voltages to generate a plurality of read data, select one of the memory blocks or sectors of a memory cell array under the control of the control circuit, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and unselected word lines.

A read/write circuit320of the memory device300may be controlled by the control circuit, and may serve as a sense amplifier or a write driver according to an operation mode. During a verification/normal read operation, the read/write circuit320may serve as a sense amplifier for reading data from the memory cell array. Also, during a program operation, the read/write circuit320may serve as a write driver which drives bit lines according to data to be stored in the memory cell array. The read/write circuit320may receive data to be written in the memory cell array, from a buffer (not shown), during the program operation, and may drive the bit lines according to the inputted data. To this end, the read/write circuit320may include a plurality of page buffers (PBs)322,324and326respectively corresponding to columns (or bit lines) or pairs of columns (or pairs of bit lines), and a plurality of latches (not shown) may be included in each of the page buffers322,324and326.

The memory device150may be realized as a 2-dimensional or 3-dimensional memory device. For example, as shown inFIG. 4, in the case here the memory device150is realized as a 3-dimensional nonvolatile memory device, the memory device150may include a plurality of memory blocks BLK0to BLKN−1.

FIG. 4is a diagram illustrating the memory blocks BLK0to BLKN−1 of the memory device150shown inFIG. 3, realized as a 3-dimensional structure (or a vertical structure). For example, the respective memory blocks BLK0to BLKN−1 may be realized as a 3-dimensional structure by including a structure which extends in first to third directions (for example, the x-axis direction the y-axis direction and the z-axis direction).

The respective memory blocks BLK0to BLKN−1 may include a plurality of NAND strings extending in the second direction. The plurality of NAND strings may be provided in the first direction and the third direction. Each NAND string may be electrically coupled to a bit line, at least one drain select line, at least one source select line, a plurality of word lines, at least one dummy word line, and a common source line. Namely, the respective memory blocks BLK0to BLKN−1 may be electrically coupled to a plurality of bit lines, a plurality of drain select lines, a plurality of source select lines, a plurality of word lines, a plurality of dummy word lines, and a plurality of common source lines.

FIG. 5is a diagram illustrating the configuration of a memory system, in accordance with an embodiment of the present invention.

Referring toFIG. 5, the memory system may include a memory device500operatively coupled to a controller590. The memory device500may include a memory controller510, a voltage generator520, a row decoder530, a memory cell array540, a column decoder550and a program/read circuit560.

In an embodiment, the controller590may serve as a controller of an electronic device hosting the memory device. The electronic device may be any suitable electronic device. The electronic device may be or include one or more of a smart phone, tablet PC, mobile phone, video phone, E-book reader, desktop PC, laptop PC, netbook computer, workstation, server, Personal Data Assistant (PDA), Portable Multimedia Player (PMP), PM3 player, medical device, camera and wearable device.

In accordance with an embodiment, the controller590may include a Solid State Drive (SSD) coupled to a host device. The host device may be or include any suitable electronic device. In an embodiment, the controller590and the memory device500may be an SSD operatively coupled to a suitable electronic device. The SSD may be coupled permanently or removably to the electronic device.

The memory cell array540of the memory device500include a plurality of memory cells arranged at the respective intersections of a plurality of word lines WL and a plurality of bit lines BL. The memory device500may receive an address ADDR with a command CMD, the address ADDR indicating a memory cell to be accessed. The address ADDR may include information which the memory controller510may employ for generating a row address X_ADDR for selecting a word line WL of the memory cell array540and a column address Y_ADDR for selecting a bit line BL of the memory cell array540.

The memory cell array540may include a plurality of search regions each including plurality group regions, and each of the group regions may have a flag cell allocated thereto, the flag cell indicating whether or not the corresponding group region is completely programmed. In an embodiment, the memory device500may adjust a read bias voltage for each of the search regions. That is, the search region may correspond to a unit region by which a read bias of the memory device500can be adjusted. In an embodiment, the search region may correspond to a block. Each search region (for example each block) may include a plurality of group regions of which each is set by grouping a plurality of word lines included in the search region. A flag cell for each group region may be allocated to a specific position of the group region. In an embodiment, a group region may have a larger area than a page, and the flag cell of the group region may be allocated to the last word line of the group region. The flag cell of the group region may be set (or programmed) when the group region is completely programmed. In the following descriptions, the phrases setting, programming or writing of the flag cell will be used as having the same meaning. Furthermore resetting and erasing of the flag cell will be used as having the same meaning.

The row decoder530may be coupled to the memory cell array540through the word lines WL, and select one or more of the word lines WL in response to a row address X_ADDR received from the memory controller510. The column decoder550may be coupled to the memory cell array540through the bit lines BL, and select one or more of the bit lines BL in response to a column address Y_ADDR received from the memory controller510.

The program/read circuit560may program or write data DATA inputted from outside (e.g., the controller590) to the memory cell array540or sense data programmed in the memory cell array540and output the sensed data to the controller590, according to control of the memory controller510. Furthermore, the program/read circuit560may provide a program or read result to the memory controller510. For example, during a program operation, the program/read circuit560may perform a verification operation to detect a result of the program operation, and provide the verification result (for example, pass/fail (P/F) signal) to the memory controller510. Furthermore, when a flag cell read operation is enabled during a read operation, the program/read circuit560may read flag cell information of the memory cell array540and provide the read information to the memory controller510.

The program/read circuit560may include a program circuit and a read circuit. The program circuit may be coupled to a bit line BL selected through the column decoder550, and perform a program operation (or write operation) by providing a program pulse to a selected memory cell of the memory cell array540. The read circuit of the program/read circuit560may be coupled to a bit line BL selected through the column decoder550, sense the level of a selected memory cell of the memory cell array540, and read (or output) data stored in the selected memory cell. The read circuit of the program/read circuit560may output data read in the read mode to the outside of the memory device500, for example the controller590.

In an embodiment, the read circuit of the program/read circuit560may read the flag cell information of the memory cell array540. When a read command is received from the controller590in a state where the flag cell read operation is enabled, the memory controller510may read the flag cell information through the read circuit of the program/read circuit560. The flag cell information read from the program/read circuit560may be provided to the memory controller510and/or the controller590.

The voltage generator520may generate various types of voltages for performing operations, such as program, read and erase operations on the memory cell array540, based on a voltage control signal provided by the memory controller510. Furthermore, the voltage generator520may generate driving voltages (or bias voltages) for driving the plurality of word lines WL and bit lines BL. For example, the driving voltages may include a set program voltage, a reset voltage, a read voltage and a cutoff voltage.

In an embodiment, the voltage generator520may generate and supply a read bias voltage having a corresponding level based on a voltage control signal of the memory controller510in the read mode. The voltage generator520may generate and supply a read bias voltage for a closed block or open block, under control of the memory controller510. In order to supply a read bias voltage for an open block, the voltage generator520may generate a read bias voltage which is adjusted based on the number of programmed group regions in the open block (i.e., the amount of data programmed in the block), under control of the memory controller510.

The memory controller510may output control signals for programming data to the memory cell array540or for reading data from the memory cell array540, based on a command CMD, an address ADDR and a control signal CTRL which are received from the controller590. The control signals outputted from the memory controller510may be provided to the voltage generator520, the row decoder530, the column decoder550and the program/read circuit560. The memory controller510may control various operations in the memory device500.

For example, the memory controller510may generate operation control signals based on the command CMD and the control signal CTRL, and provide the generated operation control signals to the program/read circuit560. Furthermore, the memory controller510may provide a row address X_ADDR to the row decoder530, and provide a column address Y_ADDR to the column decoder550. The memory controller510may generate the voltage control signal based on the command CMD, the control signal CTRL and the P/F signal received from the read circuit of the program/read circuit560. For example, the voltage control signal may include a signal indicating the operation mode of the memory device500and a signal for controlling the voltage levels of various voltages generated by the voltage generator520. The memory controller510may provide the generated voltage control signal to the voltage generator520.

In an embodiment, when a flag cell read enable signal is received from the controller590, the memory controller510may read flag cell information of the memory cell array540. When a read command is received in a state where the flag cell read operation is enabled, the memory controller510may control the row decoder530and the column decoder550to designate a flag cell position in the memory cell array540, and read flag cell information through the read circuit of the program/read circuit560. The memory controller510may analyze the flag cell information outputted from the read circuit of the program/read circuit560, and recognize a cell distribution of the memory cell array540, for example, a distribution of programmed memory cells. The memory controller510may generate a voltage control signal for adjusting a read bias voltage according to the recognition result for the cell distribution, and provide the generated voltage control signal to the voltage generator520. The voltage generator520may adjust the read bias voltage based on the received voltage control signal. Thus, the memory controller510may control a read operation of the memory cell array540, based on the adjusted read bias voltage.

According to the recent trend, the number of word lines WL included in each block of a memory device (for example, a nonvolatile memory device or flash memory) is increasing. In this case, when all word lines WL included in the block are not filled, the distribution characteristic of a memory cell in the memory device may change and may distort a read bias. For example, in the case of an open block of which the cell distribution is changed, an offset of relative read throughput (RRT) which is set based on a closed block may not be harmonized with the open block.

In an embodiment, the memory system can internally change the read bias according to a distribution which is distorted depending on how much a block is filled. Thus, the memory system may set an optimized read bias regardless of the state (e.g., program state) of the block. For example, one block may be divided into a plurality of groups, and the read bias may be changed based on the number of programmed groups in a block to be read during a read operation. Under the supposition that the number of the plurality of groups is greater than four and a first read bias voltage is supplied to a closed block, the memory system may supply a second read bias when four groups are programmed in the block to be read, supply a third bias voltage when three groups are programmed, supply a fourth read bias voltage when two groups are programmed, and supply a fifth read bias voltage when one group is programmed. At this time, the first read bias voltage may have the highest level, and the fifth read bias voltage may have the lowest level.

In an embodiment, the memory system may supply a read bias voltage based on the state of a block (for example, closed block or open blocky during a read operation. For example, the memory system may supply a preset read bias voltage to a closed block, and supply to an open block a read bias voltage having a different level from the closed block. For example, the read bias voltage of the open block may have a lower level than the read bias voltage of the closed block.

In accordance with an embodiment, the memory system may supply one read bias voltage or a plurality of read bias voltages to an open block. For example, the memory system may supply a first read bias voltage to the closed block, and supply a second read bias voltage to the open block, the second read bias voltage having a lower level than the first read bias voltage. Furthermore, the memory system may divide the open block into one or more groups, and supply the read bias voltage to the groups. For example, under the supposition that the first read bias voltage is supplied to the closed block, the memory system may supply the second read bias voltage when three or four groups are programmed in a block to be read, and supply the third read bias voltage when one or two groups are programmed.

In an embodiment, the memory system may divide the word lines of the memory device500into group regions. Depending on how much each of the group regions is filled, the memory system may adjust the read bias for the memory device500, thereby stabilizing a read operation.

FIGS. 6A and 66are diagrams illustrating the architecture of the memory device, in accordance with an embodiment.

Referring toFIG. 6A, the memory cell array540of the memory device500inFIG. 5may include a plurality of dies, each of the dies may include a plurality of planes plane0to plane x as indicated by610inFIG. 6A, and each of the planes may include a plurality of blocks block0to block y as indicated by620inFIG. 6A. Each of the blocks may Include a plurality of pages. The block may be set to a unit region by which programmed data can be erased, and the page may be set to a unit region by which data can be programmed and read.

The block may include a plurality of groups group0to group n as indicated by630inFIG. 6A. Each of the groups may be set to a larger area than the page. As illustrated inFIG. 6B, each of the groups may include a flag cell capable of indicating whether the corresponding group is programmed.FIG. 6Billustrates an example in which one block640is divided into five groups including group0650to group4654. In each of the groups group0to group4, the flag cell may be applied to a preset position of the corresponding group. As illustrated inFIG. 66, the flag cell may be allocated to the last word line of the corresponding group. For example, the flag cell Flag0660may be allocated to the last word line of the group0650, the flag cell Flag1661may be allocated to the last word line of the group1651, the flag cell Flag2662may be allocated to the last word line of the group2652the flag cell Flag3663may be allocated to the last word line of the group3653, and the flag cell Flag4664may be allocated to the last word line of the group4654. In various embodiments, a block may be set to a search region, and the search region may be set to a unit region by which a read bias level can be adjusted.

The memory device500including the memory cell array illustrated inFIGS. 6A and 6Bcan adjust a read bias voltage for itself, or adjust a read bias voltage according to control of the controller590.

In an embodiment, when a program command is received from the controller590ofFIG. 5, the memory device500may program data to the respective groups of the block. When a group is completely programmed, the memory device500may set the flag cell of the group. For example, the memory device500may allocate the flag cell to the last word line of each group, and program the flag cell when the last word line is programmed. During a read operation, the memory device500may read all pieces of flag cell information after a currently read word line WL, and determine how many groups are programmed in the corresponding block (i.e., currently read block). Then, the memory device500may internally adjust the read bias voltage of the block, based on the determination result, and read memory cell information of a block corresponding to a read request, using the adjusted read bias voltage.

In an embodiment, the memory device500may include a flag cell read enable bit, and may set the flag cell read enable bit when the setting of the flag cell read enable bit is requested by the controller590. When a read command is inputted in a state where the flag cell read enable bit is set, the memory device500may read the flag cell information of each group and check the program state of the corresponding block. Then, according to the checked program state, the memory device500may adjust the read bias voltage in order to read data of the corresponding block. When the memory device500internally changes the read bias voltage, the read bias voltage can be adjusted without changing the algorithm of a solution product (for example, SSD).

In an embodiment, the controller590may adjust the read bias voltage of the memory device500. The controller590may recognize information related to an open block. When a read request for an open block is received, the controller590may control the memory device500to enable the flag cell read operation. Then, the memory device500may internally adjust the read bias based on the flag cell information. The controller590may control the memory device500to maintain the flag cell read enable state, until a read request for a closed block is made. When a read request for the closed block is made, the controller590may control the memory device500to disable the flag cell read operation.

FIG. 7is a flowchart illustrating an operation of the memory system, in accordance with an embodiment of the present invention.

Referring toFIG. 7, when it is determined at step711that the current mode is the program mode, the memory system may program data to a group region of the memory device at step713. When the group region is completely programmed during the program operation, the memory system may program (i.e., set) the flag cell of the group region at step715.

The memory system may adjust the read bias voltage of the memory device500based on the flag cell information in the read mode. When recognizing the read mode at step721, the memory system may read the flag cell information of the group regions in the block at step723, adjust a read bias voltage of a block to be read based on the read flag cell information at step725, and read data of the corresponding block using the adjusted read bias voltage at step727.

Depending on the amount (or state) of data written to a block of the memory device500, the positions of cells may be changed. Thus, the read bias level may also be changed. For example, when the read bias voltage which is set based on the closed block is applied to an open block where data are partially written, a read fail may occur. The memory system in accordance with an embodiment may check the size (or amount) of data programmed in a block of the memory device500, and adjust the read bias voltage of the corresponding block based on the checked size (or amount) of data programmed.

In an embodiment the memory system may divide the plurality of word lines included in the block into N groups, and set a flag cell only to one word line representative of each group (for example, the last word line of each group), the flag cell indicating the program state of the corresponding group. The representative word line in each of the word line groups may have an erase state at the initial stage. When data are programmed to the representative word line, information indicating that the corresponding group was completely programmed may be programmed to the flag cell of the group. When reading an open block, the memory system may first read the flag cell information (or values) of the representative word lines of the respective word line groups, and set a read bias voltage of the corresponding block based on the read flag cell information. For example, when performing a read operation on the open block, the memory system may adjust the read bias voltage in response to the position of a group checked as a group whose flag cell value corresponds to an erase state.

In accordance with an embodiment, the controller590of the memory system inFIG. 5may check an open block in an open block list in the program mode, and control the memory device500to program data to a group of the open block of the memory cell array540. At this time, when the data are completely programmed to the group, the memory device500may program the flag cell of the corresponding group. For example when the last word line of the group is completely programmed, the memory device500may program the flag cell allocated to the last word line of the corresponding group. When all of the groups of the block are completely programmed by repeating the above-described operation, that is, when the last group of the block is completely programmed, the controller590may set the corresponding block to a closed block, and then select an open block in the open block list in order to perform a program operation.

In accordance with an embodiment, the memory device500of the memory system may check the program states of the groups by reading the flag cells of the block in the flag cell read enable state, and generate the voltage control signal for controlling the read bias voltage based on the flag cell information. The voltage generator520of the memory device500may generate a read bias voltage for reading data of the corresponding block according to the voltage control signal.

In accordance with an embodiment, the controller200of the memory system may determine whether the corresponding block is an open block, in the read mode. When the corresponding block is an open block, the controller200may enable the flag cell read operation of the memory device500, and control the memory device500to adjust the read bias voltage based on the flag cell information.

In an embodiment, the memory system may adjust and supply a read bias voltage based on whether a bock is a closed block or an open block. The memory system may supply a fixed read bias voltage to the closed block. The memory system may supply to the open block an adjusted read bias voltage which is adjusted according to the program state of data. The open block may include a block where data program is not completed. In accordance with an embodiment, the memory system may supply a fixed read bias voltage having a first voltage level to the closed block, and supply a read bias voltage having a second voltage level to the open block, the second voltage level being lower than the first voltage level. In accordance with an embodiment, the memory system may variably adjust the second voltage supplied to the open block, depending on the amount of data programmed in the block. The memory system may check the flag cell information of the open block, and adjust the read bias voltage of the open block based on the number of programmed flag cells (or the number of erased flag cells).

In an embodiment the memory system may generate a flag cell read command for controlling the memory device500to set a read bias voltage by analyzing flag cell information, during a read operation. The flag cell read command may include a command for controlling a read operation for the flag cells allocated to specific positions of the corresponding block. In accordance with an embodiment, the controller590may recognize region information of the groups in each of the blocks, and recognize the position information of the flag cells allocated to the respective groups. In this case, the controller590may search an open block and check the address of the block to be scanned by SP0. Then, the controller590may check the address information of the flag cells allocated to the open block, and transmit the address information with a read command to the memory device500. In accordance with an embodiment, the memory device may recognize the address information of the flag cells allocated to the group regions of the respective blocks. In this case, when receiving the address information of an open block and the flag cell read command, the memory device500may read information of the flag cells allocated to the corresponding open block, and transmit the read information to the controller590.

FIG. 8is a flowchart illustrating a program operation of a memory system, in accordance with an embodiment of the present invention.

Referring toFIG. 8, the memory system may perform a program operation in a program mode at step811. When the program mode is requested, the memory system may check an open block in the open block list, divide the open block into a plurality of groups (e.g., n groups) and select at least one group of the open block to which data are to be programmed, at step813. The memory system may program data to the selected group of the open block at step815. When the selected group is completely programmed, the memory system may recognize the completion of the program for the selected group at step817, and hence, may program the flag cell of the group at step819. For example, when data are programmed to the last word line of the selected group, the memory system may set the flag cell allocated to the last word line of the selected group. After the flag cell is programmed, the memory system may check whether the selected group is the last group of the block, at step821. When the selected group is not the last group, the memory system may proceed to step S823to set the next group, and then return to step S815to program data in the next group.

When the selected group is the last group at step821, the memory system may proceed to step S813to select the next open block, divide the open block into n groups, and then perform a data program operation. When an end of the program operation is requested while data are being programmed, the memory system may recognize the request and end the program operation, at step825.

FIG. 9is a flowchart illustrating a read operation in the memory system, in accordance with an embodiment of the present invention. For example,FIG. 9illustrates an operation in which the memory device of the memory system internally adjusts a read bias.

Referring toFIG. 9, when a read command is received from the controller at step911, the memory device may check whether the flag cell read operation is enabled, at step913. At this time, when the flag cell read operation is disabled, the memory device may recognize the state at step913and perform a data read operation using a default read bias voltage at step931. For example, the state in which the flag cell read operation is disabled may indicate a read operation for a closed block. The default read bias voltage may include a voltage that is set when reading data of a closed block.

When the flag cell read operation is enabled, the memory device may read the flag cells of the groups of the block at step915, and adjust the read bias voltage based on the read flag cell information, at step917. At this time, the memory device may adjust the read bias voltage to a voltage that is proportional to the number of programmed cells. Alternatively, the memory device may adjust the read bias voltage to a preset voltage for example, a read bias voltage that is set when reading data of an open block. After adjusting the read bias voltage, the memory device may check whether an end of the read mode is requested, for example, whether a cancellation of the read command is requested, at step921. When an end of the read mode is not requested, the memory device may proceed to step S913to perform a read operation. On the other hand, when an end of the read mode is requested, the memory device may recognize the request at step921, and end the read operation.

In accordance with an embodiment, the memory device may adjust the read bias voltage itself. In this case, the word lines of the respective blocks included in the memory cell array of the memory device may be divided into n groups, and a flag cell may be allocated to the last word line of each group. When a group is completely programmed, the memory device may program the flag cell of the corresponding group. Then, when a read command is received from the controller, the memory device may read all of the flag cells after the currently read word line, and check how many groups are programmed in the currently read block, based on the information of the read flag cells. The memory device may adjust the read bias voltage of the current block based on the program state of the current block (for example, the number of programmed groups in the block). Furthermore, the memory device may read data of a block corresponding to a read request, using the adjusted read bias voltage.

Before performing a read operation, the memory device may set whether to read flag cell. For example, the memory device may include a flag cell read enable bit. When the flag cell read enable bit is set, the memory device may enable a flag cell read operation, and when the flag cell read enable bit is reset, the memory device may disable the flag cell read operation.

FIGS. 10A and 10Bare diagrams illustrating an operation of adjusting a read bias voltage through the operation ofFIG. 9.

FIG. 10Aillustrates an example in which a block640is divided into five groups Group01010to Group41014and the flag cells1020to1022of the first to third groups Group01010to Group21012are programmed. That is, the third and fourth groups Group31013and Group41014among the five groups may not be programmed, and the flag cells1023and1024of the third and fourth groups among the five flag cells1020,1021,1022,1023and1024may not be programmed.

Referring toFIG. 10B, when a read command is received (for example, when a read operation is performed in a state where the flag read enable bit is set), the memory device may read the flag cell of the groups of the block while performing steps1051to1057. In the case ofFIG. 10A, the memory device may recognize a state in which the flag cells1020to1022are programmed and the flag cell1023is not programmed. That is, the memory device may read flag cells from the point of time that a programmed flag cell is first recognized to the point, of time that a flag cell which is not programmed (i.e., erased flag cell) is recognized. The memory device may adjust the read bias voltage to a value corresponding to the group of the programmed last flag cell (the flag cell1022of the third group1012inFIG. 10A) at step1059. The memory device may perform a data read operation using the adjusted read bias voltage at step1061.

FIG. 11is a flowchart illustrating a read operation of the memory system in accordance with the various embodiments. For example,FIG. 11illustrates an operation in which the controller of the memory system controls a read bias adjusting operation.

Referring toFIG. 11, when a read operation of the memory device in a read mode is requested at step1111, the controller may check whether a block corresponding to the read request is an open block, at step1113. When the corresponding block is a closed block, the controller may transmit a flag cell read disable command to the memory device at step1123, and control the memory device to perform a read operation on the closed block at step1119. When the flag cell read disable command is received from the controller, the memory device may not perform a read operation for flag cell information, but perform a read operation on the memory cell array using the default read bias voltage.

On the other hand, when the block is an open block, the controller may recognize the open block at step1113, transmit a flag cell read enable command to the memory device at step1115, and control the memory device to adjust the read bias voltage at step1117. Then, the controller may control the memory device to perform a read operation using the adjusted read bias voltage at step1119. When the flag cell read enable command is received from the controller, the memory device may read the flag cells, and adjust the read bias voltage based on the read flag cell information. Then, the memory device may perform a read operation on the memory cell array using the adjusted read bias voltage.

When the read operation of the corresponding block is completed the controller may recognize the completion of the read operation, and check whether an end of the read mode is requested, at step1121. When an end of the read mode is requested, the controller may end the read operation of the memory device. On the other hand, when an end of the read mode is not requested, the controller may proceed to step1113to check the state of the next block.

The controller of the memory system may recognize block information on an open block. When a read request for the open block is recognized in the read mode, the controller may control the memory device to enable the flag cell read operation. Then, the memory device may internally adjust the read bias voltage to perform a read operation. Then, when the read operation of the open block is ended, the controller may transmit the flag cell read disable command to the memory device. That is, when the read operation for the open block is ended, the controller may control the memory device based on a read operation of a closed block.

In accordance with another embodiment, the controller may read flag cell information through the memory device and adjust the read bias voltage of the memory device. When a read operation of the memory device is requested, the controller may check whether a block corresponding to the read request is an open block. When the corresponding block is a closed block, the controller may transmit the flag cell read disable command to the memory device, and control the memory device to perform a read operation of the closed block. On the other hand, when the corresponding block is an open block, the controller may transmit the flag cell read enable command to the memory device, and request information of the flag cell of the open block from the memory device. Then, the memory device may sequentially read the flag cells of the open block, and transmit the read information of the flag cells to the controller. When receiving the flag cell information, the controller may set a read bias voltage based on the received flag cell information. After setting the read bias voltage, the controller may transmit voltage control information of the set read bias voltage to the memory device. Then, the memory device may perform a read operation on the memory cell array using the adjusted read bias voltage.

In the memory system in accordance with various embodiments, the plurality of word ides may be divided into N groups, and a flag cell may be allocated to one word line representative of each group (for example, the last word line of each group), the flag cell indicating the program state of the corresponding group. For example, when a group is completely programmed, the memory system may set the flag cell allocated to the corresponding group. When an open block is read, the memory system may first check information (or values) of the flag cell of the representative word lines of the plurality of word line groups. Then, the memory system may adjust a read bias voltage based on the checked flag cell information. For example the memory system may adjust the read bias voltage in response to the position of a word line group of which the representative word line has a flag cell value corresponding to an erase state in the corresponding block, and read the data of the block using the adjust read bias voltage.

Hereinbelow, detailed descriptions will be made with reference toFIGS. 12 to 17, for a data processing system and electronic appliances to which the memory system110including the memory device150and the controller130described above with reference toFIGS. 1 to 11, according to the embodiment, is applied.

FIG. 12is a diagram illustrating a data processing system including the memory system according to the embodiment. For example,FIG. 12illustrates a memory card system6100to which the memory system according to an embodiment is applied.

Referring toFIG. 12, the memory card system6100may include a memory controller6120, a memory device6130, and a connector6110.

In detail, the memory controller6120may be connected with the memory device6130and may access the memory device6130. In some embodiments, the memory device6130may be implemented with a nonvolatile memory (NVM). For example, the memory controller6120may control read, write, erase and background operations for the memory device6130. The memory controller6120may provide an interface between the memory device6130and a host (not shown), and may drive a firmware for controlling the memory device6130. For example, the memory controller6120may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6130may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

Therefore, the memory controller6120may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface and an error correction unit as shown inFIG. 1.

The memory controller6120may communicate with an external device (for example, the host102described above with reference toFIG. 1), through the connector6110. For example, as described above with reference toFIG. 1, the memory controller6120may be configured to communicate with the external device through at least one of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCI-e), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), wireless-fidelity (WI-FI) and Bluetooth. Accordingly, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances for example, a mobile electronic appliance.

The memory device6130may be implemented with a nonvolatile memory (NVM). For example, the memory device6130may be implemented with one of various nonvolatile memory devices such as an electrically erasable and programmable ROM (EPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (STT-MRAM).

The memory controller6120and the memory device6130may be integrated into a single semiconductor device. For example, the memory controller6120and the memory device6130may construct a solid state driver (SSD) by being integrated into a single semiconductor device. The memory controller6120and the memory device6130may construct a memory card such as a PC card (e.g., Personal Computer Memory Card International Association (PCMCIA)) a compact flash card (CF) a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro and eMMC), an SD card (e.g., SD, miniSD microSD and SDHC) and a universal flash storage (UFS).

FIG. 13is a diagram schematically illustrating another example of a data processing system6200including a memory system according to an embodiment of the present invention.

Referring toFIG. 13, the data processing system6200may include a memory device6230which may be implemented with at least one nonvolatile memory (NW) and a memory controller6220for controlling the memory device6230. The data processing system6200may be a storage medium such as a memory card (e.g., CF, SD and microSD), as described above with reference toFIG. 1. The memory device6230may correspond to the memory device150in the memory system110described above with reference toFIG. 1, and the memory controller6220may correspond to the controller130in the memory system110described above with reference toFIG. 1.

The memory controller6220may control the operations, including the read, write and erase operations for the memory device6230in response to requests received from a host6210. The memory controller6220may include at least one of a central processing unit (CPU)6221, a random access memory (RAM) as a buffer memory6222, an error correction code (ECC) circuit6223, a host interface6224, and an NVM interface as a memory interface6225, all coupled via an internal bus.

The CPU6221may control the operations for the memory device6230such as read, write, file system management, bad page management, and so forth. The RAM6222may operate according to control of the CPU6221, and may be used as a work memory, a buffer memory, a cache memory, or the like. In the case where the RAM6222is used as a work memory, data processed by the CPU6221is temporarily stored in the RAM6222. In the case where the RAM6222is used as a buffer memory, the RAM6222is used to buffer data to be transmitted from the host6210to the memory device6230or from the memory device6230to the host6210. In the case where the RAM6222is used as a cache memory, the RAM6222may be used to enable the memory device6230with a low speed to operate at a high speed.

The ECC circuit6223may correspond to the ECC unit138of the controller130described above with reference toFIG. 1. As described above with reference toFIG. 1, the ECC circuit6223may generate an error correction code (ECC) for correcting a fail bit or an error bit in the data received from the memory device6230. The ECC circuit6223may perform error correction encoding for data to be provided to the memory device6230, and may generate data added with parity bits. The parity bits may be stored in the memory device6230. The ECC circuit6223may perform error correction decoding for data outputted from the memory device6230. At this time the ECC circuit6223may correct errors by using the parity bits. For example, as described above with reference toFIG. 1, the ECC circuit6223may correct errors by using one of various coded modulations such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocguenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM) and a Block coded modulation (BCM).

The memory controller6220may transmit and receive data to and from the host6210through the host interface6224, and transmit and receive data to and from the memory device6230through the NVM interface6225. The host interface6224may be connected with the host6210through at least one of various interface protocols such as a parallel advanced technology attachment (PATA) bus, a serial advanced technology attachment (SATA) bus, a small computer system interface (SCSI), a universal serial bus (USB), a peripheral component interconnection express (PCI-e) or a NAND interface. Further, as a wireless communication function or a mobile communication protocol such as wireless fidelity (WI-FI) or long term evolution (LTE) is implemented, the memory controller6220may transmit and receive data by being connected with an external device such as the host6210or another external device other than the host6210. For example, as the memory controller6220is configured to communicate with an external device through at least one among various communication protocols, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances, for example a mobile electronic appliance.

FIG. 14is a diagram illustrating another example of a data processing system including a memory system according to an embodiment of the invention. For example, inFIG. 14, a solid state drive (SSD)6300employing a memory system is shown.

Referring toFIG. 14, the SSD6300may include a memory device6340which may include a plurality of nonvolatile memories NVM, and a controller6320. The controller6320may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6340may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

In detail, the controller6320may be connected with the memory device6340through a plurality of channels CH1, CH2, CH3, . . . and CHi. The controller6320may include a processor6321, a buffer memory6325, an error correction code (ECC) circuit6322, a host interface6324, and a nonvolatile memory (NVM) interface as a memory interface6326coupled via an internal bus.

The buffer memory6325may temporarily store data received from a host6310or data received from a plurality of nonvolatile memories NVMs included in the memory device6340, or temporarily store metadata of the plurality of nonvolatile memories NVMs. For example, the metadata may include map data including mapping tables. The buffer memory6325may be implemented with a volatile memory such as, but not limited to, a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) SDRAM, a low power double data rate (LPDDR) SDRAM and a graphic random access memory (GRAM) or a nonvolatile memory such as, but not limited to, a ferroelectric random access memory (FRAM), a resistive random access memory (ReRAM), a spin-transfer torque magnetic random access memory (STT-MRAM) and a phase change random access memory (PRAM). While it is illustrated inFIG. 10, for the sake of convenience in explanation, that the buffer memory6325is disposed inside the controller6320, it is to be noted that the buffer memory6325may be disposed outside the controller6320.

The ECC circuit6322may calculate error correction code values of data to be programmed in the memory device6340in a program operation, perform an error correction operation for data read from the memory device6340, based on the error correction code values, in a read operation, and perform an error correction operation for data recovered from the memory device6340in a recovery operation for failed data.

The host interface6324may provide an interface function with respect to an external device such as the host6310. The nonvolatile memory interface6326may provide an interface function with respect to the memory device6340which is connected through the plurality of channels CH1, CH2, CH3, . . . and CHi.

As a plurality of SSDs6300to each of which the memory system110described above with reference toFIG. 1is applied are used, a data processing system such as a redundant array of independent disks (RAID) system may be implemented. In the RAID system, the plurality of SSDs6300and an RAID controller for controlling the plurality of SSDs6300may be included. In the case of performing a program operation by receiving a write command from the host6310, the RAID controller may select at least one memory system (for example at least one SSD6300) in response to the RAID level information of the write command received from the host6310, among a plurality of RAID levels (for example, the plurality of SSDs6300) and may output data corresponding to the write command, to the selected SSD6300. In the case of performing a read operation by receiving a read command from the host6310, the RAID controller may select at least one memory system (for example, at least one SSD6300) in response to the RAID level information of the write command received from the host6310, among the plurality of RAID levels (for example, the plurality of SSDs6300), and may provide data outputted from the selected SSD6300, to the host6310.

FIG. 15is a diagram illustrating another example of a data processing system including the memory system according to an embodiment of the present invention. For example, inFIG. 15, an embedded multimedia card (eMMC)6400employing a memory system is shown.

Referring toFIG. 15, the eMMC6400may include a memory device6440which is implemented with at least one NAND flash memory, and a controller6430. The controller6430may correspond to the controller130in the memory system110described above with reference toFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110described above with reference toFIG. 1.

The controller6430may be connected with the memory device6440through a plurality of channels. The controller6430may include a core6432, a host interface6431, and a memory interface such as a NAND interface6433.

The core6432may control the operations of the eMMC6400. The host interface6431may provide an interface function between the controller6430and a host6410. The NAND interface6433may provide an interface function between the memory device6440and the controller6430. For example, the host interface6431may be a parallel interface such as an MMC interface, as described above with reference toFIG. 1, or a serial interface such as an ultra-high speed class 1 (UHS-I)/UHS class 2 (UHS-II) and a universal flash storage (UFS) interface.

FIG. 16is a diagram illustrating another example of a data processing system including a memory system according to an embodiment of the present invention. For example,FIG. 16is a drawing schematically illustrating a universal flash storage (UFS) to which the memory system according to the embodiment is applied.

Referring toFIG. 16, the UFS system6500may include a UFS host6510, a plurality of UFS devices6520and6530, an embedded UFS device6540, and a removable UFS card6550. The UFS host6510may be an application processor of wired/wireless electronic appliances, for example, a mobile electronic appliance.

The UFS host6510, the UFS devices6520and6530, the embedded UFS device6540and the removable UFS card6550may respectively communicate with external devices such as wired/wireless electronic appliances (for example, a mobile electronic appliance), through a UFS protocol. The UFS devices6520and6530, the embedded UFS device6540and the removable UFS card6550may be implemented with the memory system110described above with reference toFIG. 1, for example, as the memory card system6100described above with reference toFIG. 8. The embedded UFS device6540and the removable UFS card6550may communicate through another protocol other than the UFS protocol. For example, the embedded UFS device6540and the removable UFS card6550may communicate through various card protocols such as, but not limited to, USB flash drives (UFDs), multimedia card (MMC), secure digital (SD), mini SD and Micro SD.

FIG. 17is a diagram illustrating another example of a data processing system including the memory system according to an embodiment of the present invention. For example, inFIG. 17, a user system6600employing the memory system is shown.

Referring toFIG. 17, the user system6600may include a user interface6610, a memory module6620, an application processor6630, a network module6640, and a storage module6650.

The application processor6630may drive components included in the user system6600and an operating system (OS). For example, the application processor6630may include controllers for controlling the components included in the user system6600, interfaces, graphics engines, and so on. The application processor6630may be provided by a system-on-chip (SoC).

The memory module6620may operate as a main memory, a working memory, a buffer memory or a cache memory of the user system6600. The memory module6620may include a volatile random access memory such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a low power double data rate (LPDDR) SDRAM, an LPDDR2 SDRAM and an LPDDR3 SDRAM or a nonvolatile random access memory such as a phase change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM) and a ferroelectric random access memory (FRAM). For example, the application processor6630and the memory module6620may be mounted by being packaged on the basis of a package-on-package (POP).

The network module6640may communicate with external devices. For example, the network module6640may support not only wired communications but also various wireless communications such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), and so on, and may thereby communicate with wired/wireless electronic appliances, for example, a mobile electronic appliance. Accordingly, the memory system and the data processing system according to the embodiment may be applied to wired/wireless electronic appliances. The network module6640may be included in the application processor6630.

The storage module6650may store data such as data received from the application processor6530, and transmit data stored therein, to the application processor6530. The storage module6650may be implemented by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash memory, a NOR flash memory and a 3-dimensional NAND flash memory. The storage module6650may be provided as a removable storage medium such as a memory card of the user system6600and an external drive. For example, the storage module6650may correspond to the memory system110described above with reference toFIG. 1, and may be implemented with the SSD, eMMC and UFS described above with reference toFIGS. 14 to 16.

In the case where the memory system110described above with reference toFIG. 1is applied to the mobile electronic appliance of the user system6600according to an embodiment, the application processor6630may control the operations of the mobile electronic appliance, and the network module6640as a communication module may control wired/wireless communication with an external device, as described above. The user interface6610as the display/touch module of the mobile electronic appliance displays data processed by the application processor6630or supports input of data from a touch panel.

In accordance with the various embodiments, the memory system and the operating method thereof can set the read bias voltage level which is optimized in the memory device depending on the data storage states of the plurality of memory blocks, thereby minimizing an occurrence of read fails. Furthermore, the controller for controlling the memory device may search for a block of the memory device in the read mode, and control the memory device to read data of the block using the optimized read bias voltage, when the block is an open block.