Storage device and method of operating the same for processing a trim request of host

The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0129578, filed on Oct. 7, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

Field of Invention

The present disclosure relates to an electronic device, and more particularly, to a storage device and a method of operating the same.

Description of Related Art

A storage device is a device that stores data under control of a host device such as a computer or a smartphone. A storage device may include a memory device storing data and a memory controller controlling the memory device. The memory device may be classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device may be a device that stores data only when power is supplied and loses the stored data when the power supply is cut off. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

The nonvolatile memory device is a device that does not lose data even though power is cut off. The nonvolatile memory device includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, and the like.

SUMMARY

An embodiment of the present disclosure provides a storage device having an improved trim processing operation speed and a method of operating the same.

According to an embodiment of the present disclosure, a storage device includes a memory device including a plurality of pages, a buffer memory configured to store address mapping information including a mapping relationship between a plurality of logical addresses provided from a host and a plurality of physical addresses corresponding to the plurality of pages, first trim bitmap information including trim information of a plurality of first logical address groups each including a first number of logical addresses that are at least two logical addresses of the plurality of logical addresses, and second trim bitmap information including trim information of a plurality of second logical address groups each including a second number of logical addresses greater than the first number of the plurality of logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

According to an embodiment of the present disclosure, a method of operating a storage device including a memory device including a plurality of pages, a buffer memory, and a memory controller that controls the memory device and the buffer memory includes generating address mapping information including a mapping relationship between a plurality of logical addresses provided from a host and a plurality of physical addresses corresponding to the plurality of pages, generating first trim bitmap information including trim information of a plurality of first logical address groups each including a first number of logical addresses that are at least two logical addresses of the plurality of logical addresses, generating second trim bitmap information including trim information of a plurality of second logical address groups each including a second number of logical addresses greater than the first number of the plurality of logical addresses, receiving a trim request from the host, changing trim information of a trim-requested second logical address group including trim-requested logical addresses from the host among the plurality of second logical address groups to a trim state in the second trim bitmap information, changing trim information of trim-requested first logical address groups each including some of the trim-requested logical addresses among the plurality of first logical address groups to the trim state in the first trim bitmap information, based on the changed trim information of the trim-requested second logical address group in the second trim bitmap information, and changing mapping information of the trim-requested logical addresses among the plurality of logical addresses in the address mapping information, based on the changed trim information of the trim-requested first logical address groups in the first trim bitmap information.

According to an embodiment of the present disclosure, a storage device includes a buffer memory configured to buffer entry values each representing a state of a logical address unmapped from or mapped to a physical address, first bit values each representing the states of a first number of ones among the logical addresses, and second bit values each representing the states of a second number of ones among the logical addresses, the second number being greater than the first number, and a controller configured to change one or more among the first bit values to reflect the change of the first bit values into the entry values in response to an unmap request for target logical addresses, a number of which is between the first and second numbers, and change one or more among the second bit values to reflect the change of the second bit values into the entry values in response to the unmap request for the target logical addresses, a number of which is greater than the second number.

The controller may output a response for the unmap request upon changing the first or second bit values.

The controller may change entry values corresponding the target logical addresses to an unmap state, based on the change of the first bit values or the change of the second bit values.

According to the present technology, a storage device having an improved trim processing operation speed and a method of operating the same are provided.

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments which are disclosed in the present specification or application are illustrated only to describe the embodiments according to the present disclosure. The embodiments according to the present disclosure may be carried out in various forms and the descriptions are not limited to the embodiments described in the present specification or application.

FIG.1is a diagram illustrating a storage device according to an embodiment of the present disclosure.

Referring toFIG.1, the storage device50may include a memory device100and a memory controller200that controls an operation of the memory device. The storage device50may be a device that stores data under control of a host400such as a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC, or an in-vehicle infotainment system.

The storage device50may be manufactured as one of various types of storage devices according to a host interface that is a communication method with the host400. For example, the storage device50may be configured as any one of various types of storage devices such as an SSD, a multimedia card in a form of an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card in a form of an SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

The storage device50may be manufactured as any one of various types of packages. For example, the storage device50may be manufactured as any one of various types of package types, such as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The memory device100may store data. The memory device100operates under control of the memory controller200. The memory device100may include a memory cell array (not shown) including a plurality of memory cells that store data.

Each of the memory cells may be configured as a single level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) capable of storing four data bits

The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, the page may be a unit for storing data in the memory device100or reading data stored in the memory device100. The memory block may be a unit for erasing data.

The memory device100is configured to receive a command CMD and an address ADDR from the memory controller200and access an area selected by the address in the memory cell array. The memory device100may perform an operation instructed by the command CMD on the area selected by the address ADDR. For example, the memory device100may perform a write operation (program operation), a read operation, and an erase operation. During the program operation, the memory device100may program data in the area selected by the address ADDR. During the read operation, the memory device100may read data from the area selected by the address ADDR. During the erase operation, the memory device100may erase data stored in the area selected by the address ADDR.

The memory controller200may control an overall operation of the storage device50.

When power is applied to the storage device50, the memory controller200may execute firmware (FW). When the memory device100is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host400, and the memory controller200may include a flash translation layer (FTL) that controls communication between the host400and the memory device100, and a flash interface layer (FIL) that controls communication with the memory device100.

In an embodiment, the memory controller200may receive data and a logical block address (LBA) from the host400and may convert the LBA into a physical block address (PBA) indicating an address of memory cells in which data included in the memory device100is to be stored. In the present specification, the LBA and a “logic address” or a “logical address” may be used as having the same meaning. In the present specification, the PBA and a “physical address” may be used as having the same meaning.

The memory controller200may control the memory device100to perform the program operation, the read operation, or the erase operation according to a request of the host400. During the program operation, the memory controller200may provide a write command, the PBA, and data to the memory device100. During the read operation, the memory controller200may provide a read command and the PBA to the memory device100. During the erase operation, the memory controller200may provide an erase command and the PBA to the memory device100.

In an embodiment, the memory controller200may generate a command, an address, and data independently regardless of the request from the host400and transmit the command, the address, and the data to the memory device100. For example, the memory controller200may provide the command, the address, and the data to the memory device100, for performing a read operation and a program operation accompanying wear leveling, read reclaim, garbage collection, and the like.

In an embodiment, the memory controller200may control at least two or more memory devices100. In this case, the memory controller200may control the memory devices100according to an interleaving method to improve operation performance. The interleaving method may be a method of controlling operations for at least two memory devices100to overlap with each other.

The host400may communicate with the storage device50using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high speed interchip (HSIC), a small computer system interface (SCSI), a peripheral component interconnection (PCI), a PCI express (PCIe), a nonvolatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multi-media card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

The memory controller200may control the buffer memory300to temporarily store data to be stored in the memory device100according to a request of the host400. The data stored in the buffer memory300may be stored in a pre-allocated area (not shown) in the buffer memory300according to a logical address.

A program unit is defined as a size of data to be programmed into the memory device100at a time during a program operation. A size of data provided to the storage device50from the host400at a time may be different from the program unit. Therefore, the memory controller200may store data received according to the program request of the host400in the buffer memory300. Thereafter, when data stored in the buffer memory300becomes a size of the program unit, the memory controller200may control the buffer memory300and the memory device100to program the data of the program unit into the memory device100.

The buffer memory300may be a volatile memory device. Therefore, when power is cut off, the data stored in the buffer memory300may not be maintained.

Referring toFIG.1, the buffer memory300is included in the storage device50and is positioned outside the memory controller200. However, in various embodiments, the buffer memory300may be positioned inside the memory controller200.

FIG.2is a diagram illustrating address mapping information301and trim bitmap information302according to an embodiment of the present disclosure.

Referring toFIG.2, the buffer memory300may store the address mapping information301and the trim bitmap information302.

The address mapping information301may include a mapping relationship between a plurality of logical addresses provided from the host400and a plurality of physical addresses corresponding to a plurality of pages included in the memory device100. In an embodiment, the address mapping information301may include a state of each of the plurality of logical addresses unmapped from or mapped to a physical address.

In an embodiment, the address mapping information301may be stored in the memory device100. The memory controller200may read some of the address mapping information301and store the some of the address mapping information301in the buffer memory300.

InFIG.2, the address mapping information301includes a mapping relationship between first to thirty-second logical addresses LA1to LA32and physical addresses PA, but is not limited thereto. According to an embodiment, the number of logical addresses included in the address mapping information301may vary.

The trim bitmap information302may include trim information of the plurality of logical addresses LA1to LA32included in the address mapping information301. At this time, the trim information may include one of a map state or a trim state, i.e., an unmap state. In an embodiment, the map state may indicate information that a specific logical address is mapped to a specific physical address. In an embodiment, the trim state may indicate information that a specific logical address is unmapped from a physical address.

In an embodiment, the trim bitmap information302may include a plurality of bits indicating the trim information of the plurality of logical addresses. For example, when a specific bit included in the trim bitmap information302is set to 0, a logical address corresponding to the specific bit may be in the map state. As another example, when a specific bit included in the trim bitmap information302is set to 1, a logical address corresponding to the specific bit may be in the trim state.

In an embodiment, the trim bitmap information302may change the trim information of the plurality of logical addresses through a memset function. For example, when an unset operation is performed on a specific bit included in the trim bitmap information302, trim information of a logical address corresponding to the corresponding bit may be changed to the map state. As another example, when a set operation is performed on a specific bit included in the trim bitmap information302, trim information of a logical address corresponding to the corresponding bit may be changed to the trim state.

In an embodiment, the trim bitmap information302may include trim information of logical address groups each including at least two or more logical addresses among the plurality of logical addresses LA1to LA32provided from the host400. Specifically, the plurality of bits included in the trim bitmap information302may indicate the trim information of the plurality of logical address groups, respectively. For example, a bit of first trim information Trim1included in the trim bitmap information302may indicate trim information of a group of the first to fourth logical addresses LA1to LA4. In addition, a bit of second trim information Trim2included in the trim bitmap information302may indicate trim information of a group of the fifth to eighth logical addresses LA5to LA8. In addition, a bit of third trim information Trim3included in the trim bitmap information302may indicate trim information of a group of the ninth to twelfth logical addresses LA9to LA12. In addition, a bit of fourth trim information Trim4included in the trim bitmap information302may indicate trim information of a group of the thirteenth to sixteenth logical addresses LA13to LA16. In addition, a bit of eighth trim information Trim8included in the trim bitmap information302may indicate trim information of a group of the twenty-ninth to thirty-second logical addresses LA29to LA32.

InFIG.2, one bit included in the trim bitmap information302indicates trim information for four logical addresses, but it is not limited thereto. According to an embodiment, the number of logical addresses corresponding to one bit included in the trim bitmap information302may vary.

In an embodiment, when receiving a trim request from the host400, the memory controller200may change the map state of the trim-requested logical addresses in the trim bitmap information302. In an embodiment, the trim request may be referred to as an unmap request. For example, when the memory controller200receives a trim request for the ninth to sixteenth logical addresses LA9to LA16from the host400, the memory controller200may change the third trim information Trim3and the fourth trim information Trim4each including some of the trim-requested logical addresses LA9to LA16to the trim state in the trim bitmap information302. Thereafter, the memory controller200may provide a response signal as a response to the trim request to the host400. In addition, the memory controller200may change the mapping information of the ninth to sixteenth logical addresses LA9to LA16to the trim state T in the address mapping information301based on the third trim information Trim3and the fourth trim information Trim4of the trim bitmap information302during an internal operation such as the read operation and the program operation. Thereafter, the memory controller200may change the third trim information Trim3and the fourth trim information Trim4to the map state.

Accordingly, the storage device50may reduce a time required to update the address mapping information301according to the trim request of the host400by updating the address mapping information301during the internal operation using the trim bitmap information302.

As the number of logical addresses corresponding to one bit (i.e., a piece of the trim information) included in the trim bitmap information302decreases, a time for reflecting the trim information of the trim bitmap information302to the address mapping information301is decreased, but a time required to change the trim information of the trim bitmap information302is increased. Conversely, as the number of logical addresses corresponding to one bit included in the trim bitmap information302increases, the time required to change the trim information of the trim bitmap information302is decreased, but the time for reflecting the trim information of the trim bitmap information302to the address mapping information301is increased.

Therefore, according to an embodiment of the present disclosure, the time required to update the address mapping information301according to the trim request of the host400may be reduced, by changing the address mapping information301based on different trim bitmap information respectively representing trim states of groups each comprising different numbers of logical addresses.

FIG.3is a diagram illustrating a different trim bitmap information according to an embodiment of the present disclosure.

Referring toFIG.3, the buffer memory300may store address mapping information301, first trim bitmap information303, and second trim bitmap information304. At this time, the address mapping information301may indicate the address mapping information301ofFIG.2.

InFIG.3, the address mapping information301includes a mapping relationship between first to thirty-second logical addresses LA1to LA32and physical addresses PA, but is not limited thereto. According to an embodiment, the number of logical addresses included in the address mapping information301may vary.

The first trim bitmap information303and the second trim bitmap information304may include trim information of the plurality of logical addresses LA1to LA32included in the address mapping information301.

In an embodiment, each of the first trim bitmap information303and the second trim bitmap information304may include trim information of logical address groups including at least two or more logical addresses among the plurality of logical addresses LA1to LA32provided from the host400. Specifically, a plurality of bits included in each of the first trim bitmap information303and the second trim bitmap information304may respectively indicate the trim information of a plurality of logical address groups.

In an embodiment, the first trim bitmap information303may include trim information of a plurality of first logical address groups each including a first number of logical addresses that are at least two or more logical addresses of the plurality of logical addresses. At this time, the first number may indicate the number of logical addresses corresponding to one bit (i.e., a piece of the trim information) included in the first trim bitmap information303.

For example, the first trim bitmap information303may include trim information of logical address groups each including four logical addresses. First trim information Trim1included in the first trim bitmap information303may indicate trim information of the first to fourth logical addresses LA1to LA4. In addition, second trim information Trim2included in the first trim bitmap information303may indicate trim information of the fifth to eighth logical addresses LA5to LA8. In addition, third trim information Trim3included in the first trim bitmap information303may indicate trim information of the ninth to twelfth logical addresses LA9to LA12. In addition, fourth trim information Trim4included in the first trim bitmap information303may indicate trim information of the thirteenth to sixteenth logical addresses LA13to LA16. In addition, eighth trim information Trim8included in the first trim bitmap information303may indicate trim information of the twenty-ninth to thirty-second logical addresses LA29to LA32.

InFIG.3, one bit (i.e., a piece of the trim information) included in the first trim bitmap information303indicates trim information for four logical addresses, but it is not limited thereto. According to an embodiment, the number of logical addresses corresponding to one bit included in the first trim bitmap information303may vary.

In an embodiment, the second trim bitmap information304may include trim information of a plurality of second logical address groups each including a second number of logical addresses greater than the first number of the plurality of logical addresses. At this time, the second number may indicate the number of logical addresses corresponding to one bit (i.e., a piece of trim information) included in the second trim bitmap information304. In an embodiment, the second number may be an integer multiple of the first number.

For example, the second trim bitmap information304may include trim information of logical address groups each including eight logical addresses. An a-th trim information Trim a included in the second trim bitmap information304may indicate trim information of the first to eighth logical addresses LA1to LA8. In addition, a b-th trim information Trim b included in the second trim bitmap information304may indicate trim information of the ninth to sixteenth logical addresses LA9to LA16. That is, the number of logical addresses corresponding to one bit (i.e., a piece of the trim information) included in the second trim bitmap information304may be greater than the number of logical addresses corresponding to one bit included in the first trim bitmap information303.

In the above-described example, the second number is twice the first number, but it is not limited thereto, and a multiple difference between the second number and the first number may vary according to an embodiment.

In an embodiment, each of the plurality of second logical address groups may correspond to at least two or more first logical address groups among the plurality of first logical address groups. For example, the logical addresses LA1to LA8corresponding to the a-th trim information Trim a included in the second trim bitmap information304may correspond to the logical addresses LA1to LA8corresponding to the first trim information Trim1and the second trim information Trim2included in the first trim bitmap information303. In addition, the logical addresses LA9to LA16corresponding to the b-th trim information Trim b included in the second trim bitmap information304may correspond to the logical addresses LA9to LA16corresponding to the third trim information Trim3and the fourth trim information Trim4included in the first trim bitmap information303. That is, each of the plurality of bits (i.e., the trim information) included in the second trim bitmap information304may correspond to at least two or more bits among the plurality of bits included in the first trim bitmap information303.

In an embodiment, the memory controller200may change the map state of the trim-requested logical addresses in one of the address mapping information301, the first trim bitmap information303, or the second trim bitmap information304based on the number of logical addresses that are trim-requested from the host400. For example, when receiving the trim request from the host400, the memory controller200may determine one of the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304based on the number of logical addresses that are trim-requested from the host400. Thereafter, the memory controller200may change the map state of the logical addresses in the determined one of the address mapping information301, the first trim bitmap information303, or the second trim bitmap information304.

In an embodiment, the memory controller200may provide the response signal for a response to the trim request to the host400after changing the map state of the trim-requested logical addresses in the determined one of the address mapping information301, the first trim bitmap information303, or the second trim bitmap information304.

In an embodiment, when the map state of the trim-requested logical addresses is changed in one of the first trim bitmap information303and the second trim bitmap information304, the memory controller200may change the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301based on the first trim bitmap information303or the second trim bitmap information304, after providing the response signal to the host400.

For example, the memory controller200may change the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301based on the first trim bitmap information303or the second trim bitmap information304during the internal operation such as the read operation and the program operation. Thereafter, the memory controller200may change the trim information corresponding to the trim-requested logical addresses to the map state in the first trim bitmap information303or the second trim bitmap information304.

FIG.4is a diagram illustrating an example in which the map state is changed in the address mapping information301according to an embodiment of the present disclosure.

InFIG.4, the buffer memory300may store address mapping information301, first trim bitmap information303, and second trim bitmap information304. At this time, the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304may indicate the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304ofFIG.3, respectively. In addition, it is assumed that the first number is four and the second number is eight.

In an embodiment, when the number of trim-requested logical addresses is less than the first number, the memory controller200may change the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301.

Referring toFIG.4, the memory controller200receives the trim request for the ninth logical address LA9and the tenth logical address LA10from the host400.

Since the number of trim-requested logical addresses LA9and LA10is less than four, i.e., the first number, the memory controller200may change the mapping information of the trim-requested logical addresses LA9and LA10to the trim state T in the address mapping information301. Thereafter, the memory controller200may provide the response signal for a response to the trim request to the host400.

FIGS.5A and5Bare diagrams illustrating an example in which a map state is changed in the address mapping information301using the first trim bitmap information303according to an embodiment of the present disclosure.

Specifically,FIG.5Ais a diagram illustrating an example in which the first trim bitmap information303is updated according to the trim request from the host400, andFIG.5Bis a diagram illustrating an example in which the map state is changed in the address mapping information301using the updated first trim bitmap information303.

InFIGS.5A and5B, the buffer memory300may store address mapping information301, first trim bitmap information303, and second trim bitmap information304. At this time, the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304may indicate the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304ofFIG.3, respectively. In addition, it is assumed that the first number is four and the second number is eight.

In an embodiment, when the number of trim-requested logical addresses is equal to or greater than the first number and less than the second number, the memory controller200may change trim information of the trim requested first logical address group including the trim-requested logical addresses among the plurality of first logical address groups in the first trim bitmap information303.

Referring toFIG.5A, the memory controller200receives the trim request for the ninth to twelfth logical addresses LA9to LA12from the host400.

Since the number of trim-requested logical addresses LA9to LA12is four, i.e., equal to the first number, the memory controller200may change the third trim information Trim3on the logical address group including the trim-requested logical addresses LA9to LA12to a trim state1in the first trim bitmap information303. Thereafter, the memory controller200may provide the response signal for a response to the trim request to the host400.

In an embodiment, the memory controller200may change the mapping information of the trim-requested logical addresses among the plurality of logical addresses to the trim state in the address mapping information301, based on the trim information of the trim-requested first logical address group stored in the first trim bitmap information303.

In addition, in an embodiment, the memory controller200may change the trim information of the trim-requested first logical address group to the map state in the first trim bitmap information303after changing the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301.

Referring toFIG.5B, the memory controller200may change the mapping information of the logical addresses LA9to LA12corresponding to the third trim information Trim3to the trim state T in the address mapping information301based on the third trim information Trim3stored in the first trim bitmap information303. Thereafter, the memory controller200may change the third trim information Trim3to a map state0.

FIGS.6A to6Care diagrams illustrating an example in which a map state is changed in the address mapping information301using the second trim bitmap information304according to an embodiment of the present disclosure.

Specifically,FIG.6Ais a diagram illustrating an example in the second trim bitmap information304is updated according to the trim request from the host400,FIG.6Bis a diagram illustrating an example in which the first trim bitmap information303is updated based on the updated second trim bitmap information304, andFIG.6Cis a diagram illustrating an example in which the map state is changed in the address mapping information301using the updated first trim bitmap information303.

InFIGS.6A to6C, the buffer memory300may store address mapping information301, first trim bitmap information303, and second trim bitmap information304. At this time, the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304may indicate the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304ofFIG.3, respectively. In addition, it is assumed that the first number is four and the second number is eight.

In an embodiment, when the number of trim-requested logical addresses is equal to or greater than the second number, the memory controller200may change trim information of the trim requested second logical address group including the trim-requested logical addresses among the plurality of second logical address groups in the second trim bitmap information304.

Referring toFIG.6A, the memory controller200receives the trim request for the ninth to sixteenth logical addresses LA9to LA16from the host400.

Since the number of trim-requested logical addresses LA9to LA16is eight, i.e., equal to the second number, the memory controller200may change the b-th trim information Trim b indicating the trim information on the logical address group including the trim-requested logical addresses LA9to LA16to the trim state1in the second trim bitmap information304. Thereafter, the memory controller200may provide the response signal for a response to the trim request to the host400.

In an embodiment, the memory controller200may change the trim information of the trim-requested first logical address groups each including some of the trim-requested logical addresses among the plurality of first logical address groups to the trim state in the first trim bitmap information303, based on the trim information of the trim-requested second logical address group stored in the second trim bitmap information304.

In addition, in an embodiment, the memory controller200may change the trim information of the trim-requested second logical address group to the map state in the second trim bitmap information304after changing the trim information of the trim-requested first logical address groups to the trim state in the first trim bitmap information303.

Referring toFIG.6B, the memory controller200may change the third trim information Trim3and the fourth trim information Trim4indicating the trim information on the logical address groups each including some of the logical addresses LA9to LA16corresponding to the b-th trim information Trim b to the trim state1in the first trim bitmap information303based on the b-th trim information Trim b stored in the second trim bitmap information304. Thereafter, the memory controller200may change the b-th trim information Trim b to the map state0.

In an embodiment, the memory controller200may change the mapping information of the trim-requested logical addresses among the plurality of logical addresses to the trim state in the address mapping information301, based on the trim information of the trim-requested first logical address groups stored in the first trim bitmap information303.

In addition, in an embodiment, the memory controller200may change the trim information of the trim-requested first logical address groups to the map state in the first trim bitmap information303after changing the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301.

Referring toFIG.6C, the memory controller200may change the mapping information of the logical addresses LA9to LA16corresponding to the third trim information Trim3and the fourth trim information Trim4to the trim state T in the address mapping information301based on the third trim information Trim3and the fourth trim information Trim4stored in the first trim bitmap information303. Thereafter, the memory controller200may change the third trim information Trim3and the fourth trim information Trim4to the map state0.

According to an embodiment of the present disclosure, the trim state by the trim request may be reflected in an order of the second trim bitmap information304, the first trim bitmap information303, and the address mapping information301. Therefore, an operation speed of the storage device50may be improved, thereby improving quality of service (QoS) of the storage device50.

FIG.7is a diagram illustrating an example in which the first trim bitmap information303and the second trim bitmap information304are stored in the memory device100according to an embodiment of the present disclosure.

InFIG.7, the buffer memory300may store address mapping information301, first trim bitmap information303, and second trim bitmap information304. At this time, the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304may indicate the address mapping information301, the first trim bitmap information303, and the second trim bitmap information304ofFIG.3, respectively. In addition, it is assumed that the first number is four and the second number is eight.

In an embodiment, the memory controller200may control the memory device100to store the trim information of each of the plurality of second logical address groups and the trim information of the first logical address groups corresponding to each of the plurality of second logical address groups in the same memory area in the memory device100. At this time, the memory area may include a memory cell, a page, a memory block, and the like.

Referring toFIG.7, the memory controller200may read trim bitmap information (trim bitmap) from the memory device100and provide the trim bitmap information (trim bitmap) to the buffer memory300. At this time, the trim bitmap information (trim bitmap) may include the first trim bitmap information303and the second trim bitmap information304.

In addition, the memory controller200may read updated trim bitmap information (updated trim bitmap) from the buffer memory300and provide the updated trim bitmap information (updated trim bitmap) to the memory device100. At this time, the memory device100may store the a-th trim information Trim a and the b-th trim information Trim b including the trim information on the corresponding logical addresses in the same memory area101together with the first to fourth trim information Trim1to Trim4. In addition, the memory device100may store a c-th trim information Trim c and a d-th trim information Trim d including the trim information on the corresponding logical addresses in the same memory area102together with the fifth to eighth trim information Trim5to Trim8.

Although not shown inFIG.7, the memory device100may store the address mapping information301.

According to an embodiment of the present disclosure, the trim information on the same logical addresses is stored in the same memory area in the memory device100. Therefore, consistency between the trim information may be maintained to increase accuracy of the trim information.

FIG.8is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.

The method shown inFIG.8may be performed by the storage device50shown inFIG.1.

Referring toFIG.8, in operation S801, the storage device50may generate the address mapping information including the mapping relationship between the plurality of logical addresses provided from the host400and the plurality of physical addresses corresponding to the plurality of pages.

In operation S803, the storage device50may generate the first trim bitmap information303including the trim information of the plurality of first logical address groups each including the first number of logical addresses that are at least two or more logical addresses of the plurality of logical addresses.

In operation S805, the storage device50may generate the second trim bitmap information304including the trim information of the plurality of second logical address groups each including the second number of logical addresses greater than the first number of the plurality of logical addresses. At this time, the second number may be an integer multiple of the first number.

In operation S807, the storage device50may receive the trim request from the host400.

In operation S809, the storage device50may determine whether the number of trim-requested logical addresses is less than the first number.

As a result of the determination in operation S809, when the number of trim-requested logical addresses is less than the first number, in operation S811, the storage device50may change the map state of the trim-requested logical addresses in the address mapping information301.

As a result of the determination in operation S809, when the number of trim-requested logical addresses is equal to or greater than the first number, in operation S813, the storage device50may determine whether the number of trim-requested logical addresses is less than the second number.

As a result of the determination in operation S813, when the number of trim-requested logical addresses is less than the second number, in operation S815, the storage device50may change the map state of the trim-requested logical addresses in the first trim bitmap information303.

As a result of the determination in operation S813, when the number of trim-requested logical addresses is equal to or greater than the second number, in operation S817, the storage device50may change the map state of the trim-requested logical addresses in the second trim bitmap information304.

FIG.9is a flowchart illustrating a method of changing the map state in the address mapping information301according to an embodiment of the present disclosure.

The method shown inFIG.9may be performed by the storage device50shown inFIG.1.

FIG.9illustrates a method of operating the storage device50when the number of logical addresses requested to be trimmed from the host400is less than the first number.

Referring toFIG.9, in operation S901, the storage device50may change the mapping information of the trim-requested logical addresses to the trim state in the address mapping information301.

In operation S903, the storage device50may provide the response signal for the trim request to the host400.

FIG.10is a flowchart illustrating a method of changing the map state in the address mapping information301using the first trim bitmap information303according to an embodiment of the present disclosure.

The method shown inFIG.10may be performed by the storage device50shown inFIG.1.

FIG.10illustrates a method of operating the storage device50when the number of logical addresses requested to be trimmed from the host400is equal to or greater than the first number and less than the second number.

Referring toFIG.10, in operation S1001, the storage device50may change the trim information of the trim-requested first logical address group including the trim-requested logical addresses among the plurality of first logical address groups to the trim state in the first trim bitmap information303.

In operation S1003, the storage device50may provide the response signal for the trim request to the host400.

In operation S1005, the storage device50may change the mapping information of the trim-requested logical addresses among the plurality of logical addresses to the trim state in the address mapping information301, based on the trim information of the trim-requested first logical address group stored in the first trim bitmap information303.

In operation S1007, the storage device50may change the trim information of the trim-requested first logical address group to the map state in the first trim bitmap information303.

FIG.11is a flowchart illustrating a method of changing the map state in address mapping information301using the second trim bitmap information304according to an embodiment of the present disclosure.

The method shown inFIG.11may be performed by the storage device50shown inFIG.1.

FIG.11illustrates a method of operating the storage device50when the number of logical addresses requested to be trimmed from the host400is equal to or greater than the second number.

Referring toFIG.11, in operation S1101, the storage device50may change the trim information of the trim-requested second logical address group including the trim-requested logical addresses among the plurality of second logical address groups to the trim state in the second trim bitmap information304.

Referring toFIG.11, in operation S1103, the storage device50may provide the response signal for the trim request to the host400.

Referring toFIG.11, in operation S1105, the storage device50may change the trim information of the trim-requested first logical address groups each including some of the trim-requested logical addresses among the plurality of first logical address groups to the trim state in the first trim bitmap information303, based on the trim information of the trim-requested second logical address group stored in the second trim bitmap information304.

Referring toFIG.11, in operation S1107, the storage device50may change the trim information of the trim-requested second logical address group to the map state in the second trim bitmap information304.

Referring toFIG.11, in operation S1109, the storage device50may change the mapping information of the trim-requested logical addresses among the plurality of logical addresses to the trim state in the address mapping information301, based on the trim information of the trim-requested first logical address groups stored in the first trim bitmap information303.

Referring toFIG.11, in operation S1111, the storage device50may change the trim information of the trim-requested first logical address groups to the map state in the first trim bitmap information303.

FIG.12is a diagram illustrating the memory device ofFIG.1.

Referring toFIG.12, the memory device100may include a memory cell array110, a voltage generator120, an address decoder130, an input/output circuit140, and a control logic150.

The memory cell array110includes a plurality of memory blocks BLK1to BLKi. The plurality of memory blocks BLK1to BLKi are connected to the address decoder130through row lines RL. The plurality of memory blocks BLK1to BLKi may be connected to the input/output circuit140through column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

Each of the plurality of memory blocks BLK1to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as one physical page. That is, the memory cell array110may include a plurality of physical pages. Each of the memory cells of the memory device100may be configured as a single level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quad level cell (QLC) capable of storing four data bits.

In an embodiment, the voltage generator120, the address decoder130, and the input/output circuit140may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array110under control of the control logic150. The peripheral circuit may drive the memory cell array110to perform the program operation, the read operation, and the erase operation.

The voltage generator120is configured to generate a plurality of operation voltages Vop using an external power voltage supplied to the memory device100. The voltage generator120operates in response to the control of the control logic150.

In an embodiment, the voltage generator120may generate an internal power voltage by regulating the external power voltage. The internal power voltage generated by the voltage generator120is used as an operation voltage of the memory device100.

In an embodiment, the voltage generator120may generate the plurality of operation voltages using an external power voltage or an internal power voltage. The voltage generator120may be configured to generate various voltages required in the memory device100. For example, the voltage generator120may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selected read voltages, and a plurality of unselected read voltages.

The voltage generator120may include a plurality of pumping capacitors that receive the internal power voltage to generate the plurality of operation voltages having various voltage levels, and may generate the plurality of operation voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic150.

The generated plurality of operation voltages may be supplied to the memory cell array110by the address decoder130.

The address decoder130is connected to the memory cell array110through the row lines RL. The address decoder130is configured to operate in response to the control of the control logic150. The address decoder130may receive an address ADDR from the control logic150. The address decoder130may decode a block address among the received addresses ADDR. The address decoder130selects at least one memory block among the memory blocks BLK1to BLKi according to the decoded block address. The address decoder130may decode a row address among the received addresses ADDR. The address decoder130may select at least one word line among word lines of a selected memory block according to the decoded row address. In an embodiment, the address decoder130may decode a column address among the received addresses ADDR. The address decoder130may connect the input/output circuit140and the memory cell array110to each other according to the decoded column address.

According to an embodiment of the present disclosure, during the read operation, the address decoder130may apply a read voltage to a selected word line and a read pass voltage of a level higher than that of the read voltage to unselected word lines.

For example, the address decoder130may include components such as a row decoder, a column decoder, and an address buffer.

The input/output circuit140may include a plurality of page buffers. The plurality of page buffers may be connected to the memory cell array110through the bit lines. During the program operation, data may be stored in selected memory cells according to data stored in the plurality of page buffers.

During the read operation, the data stored in the selected memory cells may be sensed through the bit lines, and the sensed data may be stored in the page buffers.

The control logic150may control the address decoder130, the voltage generator120, and the input/output circuit140. The control logic150may operate in response to the command CMD transmitted from an external device. The control logic150may generate various signals in response to the command CMD and the address ADDR to control the peripheral circuits.

FIG.13is a diagram illustrating a configuration of one of the memory blocks ofFIG.12.

The memory block BLKi is one memory block BLKi among the memory blocks BLK1to BLKi ofFIG.12.

Referring toFIG.13, a plurality of word lines arranged in parallel with each other may be connected between a first select line and a second select line. Here, the first select line may be the source select line SSL, and the second select line may be the drain select line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1to BLm and a common source line CSL. The bit lines BL1to BLm may be connected to the strings ST, respectively, and the common source line CSL may be commonly connected to the strings ST. Since the strings ST may be configured to be identical to each other, a string ST connected to the first bit line BL1is specifically described, as an example.

The string ST may include a source select transistor SST, a plurality of memory cells MC1to MC16, and a drain select transistor DST connected in series between the common source line CSL and the first bit line BL1. One string ST may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include more than the number of the memory cells MC1to MC16shown in the figure.

A source of the source select transistor SST may be connected to the common source line CSL and a drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1to MC16may be connected in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in the different strings ST may be connected to the source select line SSL, gates of the drain select transistors DST may be connected to the drain select line DSL, and gates of the memory cells MC1to MC16may be connected to the plurality of word lines WL1to WL16. A group of the memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a page PG. Therefore, the memory block BLKi may include the pages PG of the number of the word lines WL1to WL16.

One memory cell may store one bit of data. This is commonly called a single level cell (SLC). In this case, one physical page PG may store one logical page (LPG) data. The one logical page (LPG) data may include data bits having the same number as cells included in one physical page PG.

The one memory cell may store two or more bits of data. In this case, one physical page PG may store two or more logical page (LPG) data.

FIG.14is a diagram illustrating the memory controller ofFIG.1.

Referring toFIGS.1and14, the memory controller200may include a processor220, a RAM230, an error correction circuit240, a ROM260, a host interface270, and a flash interface280.

The processor220may control an overall operation of the memory controller200. The RAM230may be used as a buffer memory, a cache memory, an operation memory, and the like of the memory controller200.

The error correction circuit240may perform error correction. The error correction circuit240may perform an error correction encoding (ECC encoding) based on data to be written to the memory device100through the flash interface280. The error correction encoded data may be transferred to the memory device100through the flash interface280. The error correction circuit240may perform error correction decoding (ECC decoding) on data received from the memory device100through the flash interface280. For example, the error correction circuit240may be included in the flash interface280as a component of the flash interface280.

The ROM260may store various pieces of information required for the memory controller200to operate in a firmware form.

The memory controller200may communicate with an external device (for example, the host400, an application processor, and the like) through the host interface270.

The memory controller200may communicate with the memory device100through the flash interface280. The memory controller200may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device100through the flash interface280and receive data DATA. For example, the flash interface280may include a NAND interface.

FIG.15is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure.

Referring toFIG.15, the memory card system2000includes a memory controller2100, a memory device2200, and a connector2300.

The memory controller2100is connected to the memory device2200. The memory controller2100is configured to access the memory device2200. For example, the memory controller2100may be configured to control read, write, erase, and background operations of the memory device2200. The memory controller2100is configured to provide an interface between the memory device2200and a host. The memory controller2100is configured to drive firmware for controlling the memory device2200. The memory controller2100may be implemented identically to the memory controller200described with reference toFIG.1. The memory device2200may be implemented identically to the memory device100described with reference toFIG.1.

For example, the memory controller2100may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector circuit.

The memory controller2100may communicate with an external device through the connector2300. The memory controller2100may communicate with an external device (for example, the host) according to a specific communication standard. For example, the memory controller2100is configured to communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe. For example, the connector2300may be defined by at least one of the various communication standards described above.

The memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card. For example, the memory controller2100and the memory device2200may be integrated into one semiconductor device to configure a memory card such as a PC card (personal computer memory card international association (PCMCIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a universal flash storage (UFS).

FIG.16is a block diagram illustrating a solid state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure.

Referring toFIG.16, the SSD system3000includes a host3100and an SSD3200. The SSD3200exchanges a signal with the host3100through a signal connector3001and receives power through a power connector3002. The SSD3200includes an SSD controller3210, a plurality of nonvolatile memories3221to322n, an auxiliary power supply3230, and a buffer memory3240.

According to an embodiment of the present disclosure, the SSD controller3210may perform the function of the memory controller200described with reference toFIG.1.

The SSD controller3210may control the plurality of nonvolatile memories3221to322nin response to the signal received from the host3100. For example, the signal may be signals based on an interface between the host3100and the SSD3200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), a PCI express (PCI-E), an advanced technology attachment (ATA), a serial-ATA, a parallel-ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and an NVMe.

The auxiliary power supply3230is connected to the host3100through the power connector3002. The auxiliary power supply3230may receive the power from the host3100and may be charged with the power. The auxiliary power supply3230may provide power to the SSD3200when power supply from the host3100is not smooth. For example, the auxiliary power supply3230may be positioned in the SSD3200or may be positioned outside the SSD3200. For example, the auxiliary power supply3230may be positioned on a main board and may provide auxiliary power to the SSD3200.

The buffer memory3240operates as a buffer memory of the SSD3200. For example, the buffer memory3240may temporarily store data received from the host3100or data received from the plurality of nonvolatile memories3221to322n, or may temporarily store metadata (for example, a mapping table) of the nonvolatile memories3221to322n. The buffer memory3240may include a volatile memory such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, and a GRAM, or a nonvolatile memory such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM.

According to an embodiment of the present disclosure, the buffer memory3240may perform a function of the buffer memory300described with reference toFIG.1.

FIG.17is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the present disclosure.

The application processor4100may drive components, an operating system (OS), a user program, or the like included in the user system4000. For example, the application processor4100may include controllers, interfaces, graphics engines, and the like that control the components included in the user system4000. The application processor4100may be provided as a system-on-chip (SoC).

The memory module4200may operate as a main memory, an operation memory, a buffer memory, or a cache memory of the user system4000. The memory module4200may include a volatile random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDARM, an LPDDR2 SDRAM, and an LPDDR3 SDRAM, or a nonvolatile random access memory, such as a PRAM, a ReRAM, an MRAM, and an FRAM. For example, the application processor4100and memory module4200may be packaged based on a package on package (POP) and be provided as one semiconductor package.

The network module4300may communicate with external devices. For example, the network module4300may support wireless communication such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module4300may be included in the application processor4100.

The storage module4400may store data. For example, the storage module4400may store data received from the application processor4100. Alternatively, the storage module4400may transmit data stored in the storage module4400to the application processor4100. For example, the storage module4400may be implemented with a nonvolatile semiconductor memory element such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, and a three-dimensional NAND flash. For example, the storage module4400may be provided as a removable storage device (removable drive), such as a memory card, and an external drive of the user system4000.

For example, the storage module4400may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate identically to the memory device100described with reference toFIG.1. The storage module4400may operate identically to the storage device50described with reference toFIG.1.