LAYOUT STRUCTURE OF MEMORY CELL ARRAY FOR NON-VOLATILE MEMORY

A layout structure of a memory cell array for a non-volatile memory is provided. The memory cell array includes plural memory cells. Each memory cell includes a capacitor, an erase gate element, a select transistor, a floating gate transistor and a switch transistor. Moreover, plural wells are formed in a semiconductor substrate, and a floating gate is formed over the semiconductor substrate. The locations of the well regions and the shape of the floating gate are specially designed. Moreover, the plural memory cells with at least two shapes are constructed on the semiconductor substrate. Consequently, the layout area of the layout structure of the memory cell array can be effectively reduced.

FIELD OF THE INVENTION

The present invention relates to a memory cell of a non-volatile memory, and more particularly to a layout structure of a memory cell array for a non-volatile memory in order to reduce the size of the non-volatile memory.

BACKGROUND OF THE INVENTION

FIG.1Ais a schematic top view illustrating a memory cell of a conventional non-volatile memory.FIG.1Bis a schematic equivalent circuit diagram illustrating the memory cell of the conventional non-volatile memory as shown inFIG.1A. The memory cell is disclosed in U.S. Pat. No. 11,164,880 B2.

As shown inFIG.1A, a semiconductor substrate comprises a p-type well region PW, a first n-type well region NW1and a second n-type well region NW2. The first n-type well region NW1and the second n-type well region NW2are formed in two sides of the p-type well region PW. A first gate G1and a second gate G2are located over the p-type well region PW. A floating gate FG is located over the p-type well region PW, the first n-type well region NW1and the second n-type well region NW2. Moreover, each of the floating gate FG, the first gate G1and the second gate G2is made of polysilicon.

After a p-type ion implantation process is performed, a first p-type doped region17and a second p-type doped region18are formed in the second n-type well region NW2. After an n-type ion implantation process is performed, a first n-type doped region11, a second n-type doped region12, a third n-type doped region13and a fourth n-type doped region14are formed in the p-type well region PW.

A conductor line SL (i.e., a source line) is connected with the first n-type doped region11. A conductor line BL (i.e., a bit line) is connected with the fourth n-type doped region14. A conductor line EL (i.e., an erase line) is connected with the first p-type doped region17and the second p-type doped region18. A conductor line CL (i.e., a coupling line) is connected with the first n-type well region NW1. A conductor line (e.g., a select line) SGL is connected with the first gate G1. A conductor line WL (i.e., a word line) is connected with the second gate G2.

As shown inFIG.1A, the floating gate FG is extended to the first n-type well region NW1. Moreover, the floating gate FG and the first n-type well region NW1are collaboratively formed as a capacitor C1. That is, a first terminal of the capacitor C1is connected with the floating gate FG, and a second terminal of the capacitor C1is connected with the coupling line CL.

The floating gate FG is also extended to the second n-type well region NW2. The floating gate FG, the second n-type well region NW2, the first p-type doped region17and the second p-type doped region18are collaboratively formed as a p-type transistor Mp. That is, the gate terminal of the p-type transistor Mp is connected with the floating gate FG, and the drain terminal and the source terminal of the p-type transistor Mp are connected with the erase line EL. The p-type transistor Mp may be regarded as an erase gate element, and the floating gate FG, the second n-type well region NW2, the first p-type doped region17and the second p-type doped region18construct an electron ejecting path.

The first n-type doped region11, the second n-type doped region12, the third n-type doped region13and the fourth n-type doped region14are formed in the p-type well region PW. The first gate G1spans the surface between the first n-type doped region11and the second n-type doped region12. The floating gate FG spans the surface between the second n-type doped region12and the third n-type doped region13. The second gate G2spans the surface between the third n-type doped region13and the fourth n-type doped region14. In other words, three n-type transistors are constructed in the p-type well region PW. The three n-type transistors include a first n-type transistor Ms, a second n-type transistor Mf and a third n-type transistor Msw.

The first n-type transistor Ms is a select transistor. The gate terminal G1of the first n-type transistor Ms is connected with the select line SGL. The first n-type doped region11is connected with the source line SL. The second n-type doped region12is shared by the first n-type transistor Ms and the second n-type transistor Mf.

The second n-type transistor Mf is a floating gate transistor. The gate terminal FG of the second n-type transistor Mf is a floating gate. The third n-type doped region13is shared by the second n-type transistor Mf and the third n-type transistor Msw.

The third n-type transistor Msw is a switch transistor. The second gate G2of the third n-type transistor Msw is connected with the word line WL. The fourth n-type doped region14is connected with the bit line BL.

Please refer to the memory cell100as shown inFIG.1B. The gate terminal of the select transistor Ms is connected with the select line SGL. The first source/drain terminal of the select transistor Ms is connected with the source line SL. The first source/drain terminal of the floating gate transistor Mf is connected with the second source/drain terminal of the select transistor Ms. The gate terminal of the switch transistor Msw is connected with the word line WL. The first source/drain terminal of the switch transistor Msw is connected with the second source/drain terminal of the floating gate transistor Mf. The second source/drain terminal of the switch transistor Msw is connected with the bit line BL. The capacitor C1is connected between the floating gate FG and the coupling line CL. The gate terminal of the p-type transistor Mp is connected with the floating gate FG. The first source/drain terminal and the second source/drain terminal of the p-type transistor Mp are connected with the erase line EL.

Generally, a non-volatile memory comprises a memory cell array, and the memory cell array is composed of plural memory cells. In other words, plural memory cells are constructed on a semiconductor substrate. After the layout structure of the memory cell array is specially designed, the layout area of the non-volatile memory can be effectively reduced.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a layout structure of a memory cell array for a non-volatile memory. The layout structure includes a first first-type well region, a second first-type region, a first second-type well region, a second second-type well region, a first gate, a second gate, a first floating gate, a first first-type doped region, a second first-type doped region, a third first-type doped region, a fourth first-type doped region, a first second-type doped region, a first contact terminal a second contact terminal. The second first-type well region is arranged between the first second-type well region and the second second-type well region. The first second-type well region is arranged between the first first-type well region and the second first-type well region. The first gate, the second gate and the first floating gate are formed on a surface of the second second-type well region. The first floating gate is extended from the second second-type well region to the first first-type well region through the second first-type well region and the first second-type well region. The first first-type doped region, the second first-type doped region, the third first-type doped region and the fourth first-type doped region are formed in the surface of the second second-type well region. The first gate spans a surface between the first first-type doped region and the second first-type doped region. The first floating gate spans a surface between the second first-type doped region and the third first-type doped region. The second gate spans a surface between the third first-type doped region and the fourth first-type doped region. The first second-type doped region is formed in the first first-type well region. The first second-type doped region is located beside the first floating gate. The first contact terminal is formed on the first second-type doped region and connected with an erase line. The second contact terminal formed on the second first-type well region and connected with a coupling line.

Another embodiment of the present invention provides a layout structure of a memory cell array for a non-volatile memory. The layout structure includes a first first-type well region, a second first-type region, a first second-type well region, a second second-type well region, a third second-type well region, a first gate, a second gate, a first floating gate, a first first-type doped region, a second first-type doped region, a third first-type doped region, a fourth first-type doped region, a first second-type doped region, a first contact terminal and a second contact terminal. The second first-type well region is arranged between the first second-type well region and the second second-type well region. The first second-type well region is arranged between the first first-type well region and the second first-type well region. The first first-type well region is arranged between the first second-type well region and the third second-type well region. The first gate, the second gate and the first floating gate are formed on a surface of the third second-type well region. The first floating gate is extended from the third second-type well region to the second first-type well region through the first first-type well region and the first second-type well region. The first first-type doped region, the second first-type doped region, the third first-type doped region and the fourth first-type doped region are formed in a surface of the third second-type well region. The first gate spans a surface between the first first-type doped region and the second first-type doped region. A first floating gate spans a surface between the second first-type doped region and the third first-type doped region. The second gate spans a surface between the third first-type doped region and the fourth first-type doped region. The first second-type doped region is formed in the first first-type well region. The first second-type doped region is located beside the first floating gate. The first contact terminal is formed on the first second-type doped region and connected with an erase line. The second contact terminal is formed on the second first-type well region and connected with a coupling line.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS.2A and2Bschematically illustrates a layout structure of a memory cell array according to a first embodiment of the present invention.

As shown inFIG.2A, plural p-type well regions PW1, PW2and plural n-type well regions NW1, NW2, NM3are formed under the surface of a semiconductor substrate. The p-type well regions PW1, PW2and the n-type well regions NW1, NW2, NM3are arranged alternately. In addition, 12 memory cells cell1˜cell12are constructed on the p-type well regions PW1, PW2and the n-type well regions NW1, NW2, NM3. The odd-numbered memory cells cell1, cell3, cell5, cell7, cell9and cell11are constructed on the n-type well regions NW1, NW2and the p-type well region PW1. The even-number memory cells cell2, cell4, cell6, cell8, cell10and cell12are constructed on the n-type well regions NW2, NW3and the p-type well region PW2. The n-type well region NW2is shared by all of the memory cells cell1˜cell12. The structures of the memory cells cell1˜cell12are similar. For succinctness, only the structure of the memory cell cell1will be described as follows.

Please refer toFIG.2Aagain. In the memory cell cell1, the n-type well regions NW1and NW2are respectively located beside two opposite sides of the p-type well region PW1. A first gate G1and a second gate G2are formed over the p-type well region PW1to cover the p-type well region PW1. In addition, a floating gate FG is formed over the p-type well region PW1and the n-type well regions NW1, NW2to cover the p-type well region PW1and the n-type well regions NW1, NW2. Each of the floating gate FG, the first gate G1and the second gate G2comprises a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate. The polysilicon layer is formed over the gate dielectric layer.

Then, a p-type doped region28is formed in the n-type well region NW1. In addition, four n-type doped regions21,22,23and24are formed in the p-type well region PW1. A contact terminal is formed on the n-type doped region21and connected with a source line SL. A contact terminal is formed on the n-type doped region24and connected with a bit line BL. A contact terminal is formed on the p-type doped region28and connected with an erase line EL. A contact terminal is formed on the n-type well region NW2and connected with a coupling line CL. A contact terminal is formed on the first gate G1and connected with a select line SGL. A contact terminal is formed on the second gate G2and connected with a word line WL.

As shown inFIG.2A, the floating gate FG is extended to the n-type well region NW2. In addition, the floating gate FG and the n-type well region NW2are collaboratively formed as a capacitor. That is, a first terminal of the capacitor is connected with the floating gate FG, and a second terminal of the capacitor is connected with the coupling line CL.

The floating gate FG is also extended to the n-type well region NW1. In addition, the floating gate FG, the n-type well region NW1and the p-type doped region28are collaboratively formed as a p-type transistor. That is, the gate terminal of the p-type transistor is connected with the floating gate FG, and the drain terminal and the source terminal of the p-type transistor are connected with the erase line EL. The p-type transistor may be regarded as an erase gate element, and the floating gate FG, the n-type well region NW1, and the p-type doped region28construct an electron ejecting path of ejecting electrons.

The first gate G1spans the surface between the n-type doped region21and the n-type doped region22. The floating gate FG spans the surface between the n-type doped region22and the n-type doped region23. The second gate G2spans the surface between the n-type doped region23and the n-type doped region24. In other words, a first n-type transistor, a second n-type transistor and a third n-type transistor are constructed in the p-type well region PW1. The first n-type transistor comprises the first gate G1, the n-type doped region21and the n-type doped region22. The second n-type transistor comprises the floating gate FG, the n-type doped region22and the n-type doped region23. The third n-type transistor comprises the second gate G2, the n-type doped region23and the n-type doped region24.

The first n-type transistor is a select transistor. The first gate G1of the first n-type transistor is connected with the select line SGL. The n-type doped region21is connected with the source line SL.

The second n-type transistor is a floating gate transistor. The gate terminal FG of the second n-type transistor is a floating gate.

The third n-type transistor is a switch transistor. The second gate G2of the third n-type transistor is connected with the word line WL. The n-type doped region24is connected with the bit line BL.

By appropriately connecting the word line WL, the bit line BL, the select line SGL, the coupling line CL and the erase line EL, a memory cell array can be formed. The equivalent circuit of the memory cells cell1in the first embodiment is similar to the equivalent circuit of the memory cell shown inFIG.1B, and not redundantly described herein.

The zoom-out layout structure of the memory cell array is shown inFIG.2B. As shown inFIG.2B, a non-volatile memory comprises plural pages, and each page comprises plural memory cells. In addition, plural p-type well regions PW1˜PW5and plural n-type well regions NW1˜NM6are alternately arranged and formed under the surface of the semiconductor substrate. The memory cells in the first page Page1are constructed on the n-type well regions NW1˜NM3and the p-type well regions PW1˜PW2. The memory cells in the second page Page2are constructed on the n-type well regions NW4˜NM6and the p-type well regions PW4˜PW5. The p-type well region PW3is arranged between the n-type well region NW3of the first page Page1and the n-type well region NW4of the second page Page2and served as a spacing well region.

In the memory cell array of the first embodiment, each page is defined by three n-type well regions and two p-type well regions, and one spacing p-type well region is arranged between every two adjacent pages. Consequently, the layout structure of the memory cell array in the non-volatile memory has a larger layout area.

In some other embodiments, the locations of the well regions and the shape of the floating gate are specially designed. Consequently, the layout area of the layout structure of the memory cell array can be reduced.

FIGS.3A and3Bschematically illustrates a layout structure of a memory cell array according to a second embodiment of the present invention. As shown inFIG.3A, plural p-type well regions PW1, PW2and plural n-type well regions NW1, NW2are formed under the surface of a semiconductor substrate. The p-type well regions PW1, PW2and the n-type well regions NW1, NW2are arranged alternately. The n-type well region NW2is arranged between the p-type well regions PW1and PW2. The p-type well region PW1is arranged between the n-type well regions NW1and NW2. In addition, 6 memory cells cell1˜cell6are constructed on the p-type well regions PW1, PW2and the n-type well regions NW1, NW2. The structures of the memory cells cell1, cell4and cell5are similar, and the structures of the memory cells cell2, cell3and cell6are similar. For succinctness, only the structure of the memory cell cell1and the structure of the memory cell cell2will be described as follows.

Please refer toFIG.3Aagain. In the memory cell cell1, a first gate G1and a second gate G2are formed over the p-type well region PW2to cover the p-type well region PW2. In addition, a first floating gate FG1is formed over the p-type well regions PW1, PW2and the n-type well regions NW1, NW2to cover the p-type well regions PW1, PW2and the n-type well regions NW1, NW2.

In the memory cell cell2, a third gate G3and a fourth gate G4are formed over the p-type well region PW1to cover the p-type well region PW1. In addition, a second floating gate FG2is formed over the p-type well regions PW1, PW2and the n-type well regions NW1, NW2to cover the p-type well regions PW1, PW2and the n-type well regions NW1, NW2. Each of the first floating gate FG1, the second floating gate FG2, the first gate G1, the second gate G2, the third gate G3and the fourth gate G4comprises a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate. The polysilicon layer is formed over the gate dielectric layer.

Then, a p-type doped region38is formed in the n-type well region NW1. In addition, four n-type doped regions31,32,33and34are formed in the p-type well region PW2, and four n-type doped regions41,42,43and44are formed in the p-type well region PW1. A contact terminal is formed on the n-type doped region31and connected with a source line SL1. A contact terminal is formed on the n-type doped region34and connected with a bit line BL1. A contact terminal is formed on the n-type doped region41and connected with a source line SL2. A contact terminal is formed on the n-type doped region44and connected with a bit line BL2. A contact terminal is formed on the p-type doped region38and connected with an erase line EL. A contact terminal is formed on the n-type well region NW2and connected with a coupling line CL. A contact terminal is formed on the first gate G1and connected with a select line SGL1. A contact terminal is formed on the second gate G2and connected with a word line WL1. A contact terminal is formed on the third gate G3and connected with a select line SGL2. A contact terminal is formed on the fourth gate G4and connected with a word line WL2.

As shown inFIG.3A, the first floating gate FG1is extended from the p-type well region PW2to the n-type well region NW1through the n-type well region NW2and the p-type well region PW1. In addition, the first floating gate FG1and the n-type well region NW2are collaboratively formed as a capacitor. That is, a first terminal of the capacitor is connected with the first floating gate FG1, and a second terminal of the capacitor is connected with the coupling line CL. The first floating gate FG1is also extended to the n-type well region NW1and located beside the p-type doped region38. In addition, the first floating gate FG1, the n-type well region NW1and the p-type doped region38are collaboratively formed as a p-type transistor. That is, the gate terminal of the p-type transistor is connected with the first floating gate FG1, and the drain terminal and the source terminal of the p-type transistor are connected with the erase line EL. The p-type transistor may be regarded as an erase gate element, and the first floating gate FG1, the n-type well region NW1and the p-type doped region38construct an electron ejecting path of the memory cell Cell1. That is, the electrons of the memory cell Cell1can be ejected from the first floating gate FG1to the erase line EL.

The second floating gate FG2comprises two branches. The first branch of the second floating gate FG2is extended from the p-type well region PW1to the n-type well region NW2and the p-type well region PW2. The second branch of the second floating gate FG2is extended from the p-type well region PW1to the n-type well region NW1. In addition, the second branch of the second floating gate FG2is located beside the p-type doped region38. The second floating gate FG2and the n-type well region NW2are collaboratively formed as a capacitor. That is, a first terminal of the capacitor is connected with the second floating gate FG2, and a second terminal of the capacitor is connected with the coupling line CL. Moreover, the second floating gate FG2, the n-type well region NW1and the p-type doped region38are collaboratively formed as a p-type transistor. That is, the gate terminal of the p-type transistor is connected with the second floating gate FG2, and the drain terminal and the source terminal of the p-type transistor are connected with the erase line EL. The second floating gate FG2, the n-type well region NW1, and the p-type doped region38construct an electron ejecting path of the memory cell Cell2. That is, the electrons of the memory cell Cell2can be ejected from the second floating gate FG2to the erase line EL.

In the memory cell Cell1, the first gate G1spans the surface between the n-type doped region31and the n-type doped region32. The first floating gate FG1spans the surface between the n-type doped region32and the n-type doped region33. The second gate G2spans the surface between the n-type doped region33and the n-type doped region34. In other words, a first n-type transistor, a second n-type transistor and a third n-type transistor are constructed in the p-type well region PW2. The first n-type transistor comprises the first gate G1, the n-type doped region31and the n-type doped region32. The second n-type transistor comprises the first floating gate FG1, the n-type doped region32and the n-type doped region33. The third n-type transistor comprises the second gate G2, the n-type doped region33and the n-type doped region34.

The first n-type transistor is a select transistor. The first gate G1of the first n-type transistor is connected with the select line SGL1. The n-type doped region31is connected with the source line SL1. The second n-type transistor is a floating gate transistor. The third n-type transistor is a switch transistor. The second gate G2of the third n-type transistor is connected with the word line WL1. The n-type doped region34is connected with the bit line BL1.

In the memory cell Cell2, the third gate G3spans the surface between the n-type doped region41and the n-type doped region42. The second floating gate FG2spans the surface between the n-type doped region42and the n-type doped region43. The fourth gate G4spans the surface between the n-type doped region43and the n-type doped region44. In other words, a fourth n-type transistor, a fifth n-type transistor and a sixth n-type transistor are constructed in the p-type well region PW1. The fourth n-type transistor comprises the third gate G3, the n-type doped region41and the n-type doped region42. The fifth n-type transistor comprises the second floating gate FG2, the n-type doped region42and the n-type doped region43. The sixth n-type transistor comprises the fourth gate G4, the n-type doped region43and the n-type doped region44.

The fourth n-type transistor is a select transistor. The third gate G3of the fourth n-type transistor is connected with the select line SGL2. The n-type doped region41is connected with the source line SL2. The fifth n-type transistor is a floating gate transistor. The sixth n-type transistor is a switch transistor. The fourth gate G4of the sixth n-type transistor is connected with the word line WL2. The n-type doped region44is connected with the bit line BL2.

By appropriately connecting the word lines WL1, WL2, the bit lines BL1, BL2, the select lines SGL1, SGL2, the coupling line CL and the erase line EL, a memory cell array can be formed.

The equivalent circuit of each of the memory cells Cell1and the memory cell Cell2in the second embodiment is similar to the equivalent circuit of the memory cell shown inFIG.1B, and not redundantly described herein.

The zoom-out layout structure of the memory cell array is shown inFIG.3B. As shown inFIG.3B, a non-volatile memory comprises plural pages, and each page comprises plural memory cells. In addition, plural p-type well regions PW1˜PW4and plural n-type well regions NW1˜NM4are alternately arranged and formed under the surface of the semiconductor substrate. The memory cells in the first page Page1are constructed on the n-type well regions NW1, NM2and the p-type well regions PW1, PW2. The memory cells in the second page Page2are constructed on the n-type well regions NW3, NM4and the p-type well regions PW3, PW4.

In comparison with the layout structure of the memory cell array of the first embodiment, each page in the layout structure of the memory cell array of the second embodiment is defined by two n-type well regions and two p-type well regions. Moreover, there is no spacing well between every two adjacent pages. Consequently, the layout structure of the memory cell array of the second embodiment has the smaller layout area.

FIGS.4A and4Bschematically illustrates a layout structure of a memory cell array according to a third embodiment of the present invention. As shown inFIG.4A, plural p-type well regions PW1, PW2, PW3and plural n-type well regions NW1, NW2are formed under the surface of a semiconductor substrate. The p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2are arranged alternately. The n-type well region NW2is arranged between the p-type well regions PW1and PW2. The p-type well region PW1is arranged between the n-type well regions NW1and NW2. The n-type well region NW1is arranged between the p-type well regions PW1and PW3. In addition, 6 memory cells cell1˜cell6are constructed on the p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2. The structures of the memory cells cell1, cell4and cells are similar, and the structures of the memory cells cell2, cell3and cells are similar. For succinctness, only the structure of the memory cell cell1and the structure of the memory cell cell2will be described as follows.

Please refer toFIG.4Aagain. In the memory cell cell1, a first gate G1and a second gate G2are formed over the p-type well region PW2to cover the p-type well region PW2. In addition, a first floating gate FG1is formed over the p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2to cover the p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2.

In the memory cell cell2, a third gate G3and a fourth gate G4are formed over the p-type well region PW3to cover the p-type well region PW3. In addition, a second floating gate FG2is formed over the p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2to cover the p-type well regions PW1, PW2, PW3and the n-type well regions NW1, NW2. Each of the first floating gate FG1, the second floating gate FG2, the first gate G1, the second gate G2, the third gate G3and the fourth gate G4comprises a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate. The polysilicon layer is formed over the gate dielectric layer.

Then, a p-type doped region58is formed in the n-type well region NW1. In addition, four n-type doped regions51,52,53and54are formed in the p-type well region PW2, and four n-type doped regions61,62,63and64are formed in the p-type well region PW3. A contact terminal is formed on the n-type doped region51and connected with a source line SL1. A contact terminal is formed on the n-type doped region54and connected with a bit line BL1. A contact terminal is formed on the n-type doped region61and connected with a source line SL2. A contact terminal is formed on the n-type doped region64and connected with a bit line BL2. A contact terminal is formed on the p-type doped region58and connected with an erase line EL. A contact terminal is formed on the n-type well region NW2and connected with a coupling line CL. A contact terminal is formed on the first gate G1and connected with a select line SGL1. A contact terminal is formed on the second gate G2and connected with a word line WL1. A contact terminal is formed on the third gate G3and connected with a select line SGL2. A contact terminal is formed on the fourth gate G4and connected with a word line WL2.

As shown inFIG.4A, the first floating gate FG1is extended from the p-type well region PW2to the p-type well region PW3through the n-type well region NW2, the p-type well region PW1and the n-type well region NW1. In addition, the first floating gate FG1and the n-type well region NW2are collaboratively formed as a capacitor. That is, a first terminal of the capacitor is connected with the first floating gate FG1, and a second terminal of the capacitor is connected with the coupling line CL. The first floating gate FG1is also extended to the n-type well region NW1and located beside the p-type doped region58. In addition, the first floating gate FG1, the n-type well region NW1and the p-type doped region58are collaboratively formed as a p-type transistor. That is, the gate terminal of the p-type transistor is connected with the first floating gate FG1, and the drain terminal and the source terminal of the p-type transistor are connected with the erase line EL. The p-type transistor may be regarded as an erase gate element, and the first floating gate FG1, the n-type well region NW1and the p-type doped region58construct an electron ejecting path of the memory cell Cell1. That is, the electrons of the memory cell Cell1can be ejected from the first floating gate FG1to the erase line EL.

The second floating gate FG2is extended from the p-type well region PW3to the p-type well region PW2through the n-type well region NW1, the p-type well region PW1and the n-type well region NW2. The second floating gate FG2and the n-type well region NW2are collaboratively formed as a capacitor. That is, a first terminal of the capacitor is connected with the second floating gate FG2, and a second terminal of the capacitor is connected with the coupling line CL. In addition, the second floating gate FG2is located beside the p-type doped region58. Moreover, the second floating gate FG2, the n-type well region NW1and the p-type doped region58are collaboratively formed as a p-type transistor. That is, the gate terminal of the p-type transistor is connected with the second floating gate FG2, and the drain terminal and the source terminal of the p-type transistor are connected with the erase line EL. The second floating gate FG2, the n-type well region NW1, and the p-type doped region58construct an electron ejecting path of the memory cell Cell2. That is, the electrons of the memory cell Cell2can be ejected from the second floating gate FG2to the erase line EL.

In the memory cell Cell1, the first gate G1spans the surface between the n-type doped region51and the n-type doped region52. The first floating gate FG1spans the surface between the n-type doped region52and the n-type doped region53. The second gate G2spans the surface between the n-type doped region53and the n-type doped region54. In other words, a first n-type transistor, a second n-type transistor and a third n-type transistor are constructed in the p-type well region PW2. The first n-type transistor comprises the first gate G1, the n-type doped region51and the n-type doped region52. The second n-type transistor comprises the first floating gate FG1, the n-type doped region52and the n-type doped region53. The third n-type transistor comprises the second gate G2, the n-type doped region53and the n-type doped region54.

The first n-type transistor is a select transistor. The first gate G1of the first n-type transistor is connected with the select line SGL1. The n-type doped region51is connected with the source line SL1. The second n-type transistor is a floating gate transistor. The third n-type transistor is a switch transistor. The second gate G2of the third n-type transistor is connected with the word line WL1. The n-type doped region54is connected with the bit line BL1.

In the memory cell Cell2, the third gate Gs spans the surface between the n-type doped region61and the n-type doped region62. The second floating gate FG2spans the surface between the n-type doped region62and the n-type doped region63. The fourth gate G4spans the surface between the n-type doped region63and the n-type doped region64. In other words, a fourth n-type transistor, a fifth n-type transistor and a sixth n-type transistor are constructed in the p-type well region PW3. The fourth n-type transistor comprises the third gate G3, the n-type doped region61and the n-type doped region62. The fifth n-type transistor comprises the second floating gate FG2, the n-type doped region62and the n-type doped region63. The sixth n-type transistor comprises the fourth gate G4, the n-type doped region63and the n-type doped region64.

The fourth n-type transistor is a select transistor. The third gate G3of the fourth n-type transistor is connected with the select line SGL2. The n-type doped region61is connected with the source line SL2. The fifth n-type transistor is a floating gate transistor. The sixth n-type transistor is a switch transistor. The fourth gate G4of the sixth n-type transistor is connected with the word line WL2. The n-type doped region64is connected with the bit line BL2.

By appropriately connecting the word lines WL1, WL2, the bit lines BL1, BL2, the select lines SGL1, SGL2, the coupling line CL and the erase line EL, a memory cell array can be formed.

The equivalent circuit of each of the memory cell Cell1and the memory cell Cell2in the third embodiment is similar to the equivalent circuit of the memory cell shown inFIG.1B, and not redundantly described herein.

The zoom-out layout structure of the memory cell array is shown inFIG.4B. As shown inFIG.4B, a non-volatile memory comprises plural pages, and each page comprises plural memory cells. In addition, plural p-type well regions PW1˜PW5and plural n-type well regions NW1˜NM4are alternately arranged and formed under the surface of the semiconductor substrate. The memory cells in the first page Page1are constructed on the n-type well regions NW1, NM2and the p-type well regions PW1, PW2, PW3. The memory cells in the second page Page2are constructed on the n-type well regions NW3, NM4and the p-type well regions PW2, PW4, PW5. That is, the p-type well region PW2is shared by the two pages.

In comparison with the layout structure of the memory cell array of the first embodiment, each page in the layout structure of the memory cell array of the third embodiment is defined by two n-type well regions and three p-type well regions. Moreover, the p-type well region PW2is shared by the two pages. Consequently, in the non-volatile memory, the layout structure of the memory cell array of the third embodiment has the smaller layout area.

The layout structure of the second embodiment and the third embodiment may be properly modified.FIG.5schematically illustrates a variant example of the layout structure of the memory cell array according to the second embodiment. In comparison with the second embodiment, the floating gates of the memory cells Cell2, Cell3, Cell6are not extended to the p-type well region PW2. In addition, at least one doped region is formed in the n-type well region NW2. The doped region is connected with the coupling line CL. As shown inFIG.5, an n-type doped region47and a p-type doped region48are formed in the n-type well region NW2. The n-type doped region47and the p-type doped region48are located beside all of the floating gates. A contact terminal is formed on the n-type doped region47and connected with the coupling line CL. A contact terminal is formed on the p-type doped region48and connected with the coupling line CL. Consequently, a capacitor is formed between the coupling line CL and the floating gate, and the capacitor has a higher coupling ratio. It is noted that the layout structure may be further modified. For example, in another variant example, only a single n-type doped region or a single p-type doped region is formed in the n-type well region NW2.

FIG.6schematically illustrates a variant example of the layout structure of the memory cell array according to the third embodiment. In comparison with the third embodiment, the floating gates of the memory cells Cell2, Cell3, Cell6are not extended to the p-type well region PW2. Similarly, the floating gate of the memory cells Cell1, Cell4, Cell5are not extended to the p-type well region PW3. Similarly, at least one doped region is formed in the n-type well region NW2. The doped region is connected with the coupling line CL. As shown inFIG.6, an n-type doped region66, a p-type doped region67and another n-type doped region68are formed in the n-type well region NW2. The n-type doped region66, the p-type doped region67and the n-type doped region68are located beside all of the floating gates. A contact terminal is formed on the n-type doped region66and connected with the coupling line CL. A contact terminal is formed on the p-type doped region67and connected with the coupling line CL. A contact terminal is formed on the n-type doped region68and connected with the coupling line CL. Under this circumstance, a capacitor is formed between the coupling line CL and the floating gate, and the capacitor has a higher coupling ratio. It is noted that the layout structure may be further modified. For example, in another variant example, only a single n-type doped region or a single p-type doped region is formed in the n-type well region NW2.

Of course, the layout structure of the memory cell array as shown inFIG.5may be further modified. For example, in a variant example, the three doped regions66,67and68shown inFIG.6are formed in n-type well region NW2. Similarly, the layout structure of the memory cell array as shown inFIG.6may be further modified. For example, in a variant example, the two doped regions47and48shown inFIG.5are formed in the n-type well region NW2.

In the second embodiment and the third embodiment, all of the memory cells Cell1˜Cell6are connected with the same coupling line CL and the same erase line EL. It is noted that the connecting relationships between the word lines WL1, WL2, the bit lines BL1, BL2, the source lines SL1, SL2and the select lines SGL1, SGL2are not restricted. For example, in an embodiment of the memory cell array, the source lines SL1and SL2are connected with each other, the word lines WL1and WL2are connected with each other, the select lines SGL1and SGL2are connected with each other, and the bit lines BL1and BL2are not connected with each other. In another embodiment of the memory cell array, the source lines SL1and SL2are connected with each other, the bit lines BL1and BL2are connected with each other, the word lines WL1, and WL2are not connected with each other, and the select lines SGL1and SGL2are not connected with each other. In another embodiment of the memory cell array, the connecting relationships between the word lines WL1, WL2, the bit lines BL1, BL2, the source lines SL1, SL2and the select lines SGL1, SGL2are distinguished.

In the above embodiments, the memory cell comprises three n-type transistors, a capacitor and a p-type transistor. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the n-doped region and the p-type doped region are replaced by each other, and the n-type well region and the p-type well region are replaced by each other. Consequently, the modified memory cell comprises three p-type transistors, a capacitor and an n-type transistor.

From the above descriptions, the present invention provides a layout structure of a memory cell array for a non-volatile memory. In the layout structure, plural well regions are formed in the semiconductor substrate, and the shapes of the floating gates are specially designed. Consequently, the layout area of the layout structure of the memory cell array can be effectively reduced.