Semiconductor memory device having selectable transfer modes

A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a terminal combining an input terminal for address and an input/output terminal for data.

2. Description of Related Art

A semiconductor device is mounted to a cellular phone or the like. In a cellular phone or the like, data is transferred between a semiconductor memory device (hereinafter referred to as a memory) and other functional circuits such as CPU (Central Processing Unit). In recent years, the data transfer efficiency is desired to improve. One of the methods for the improvement in data transfer efficiency is to increase the number of buses connecting between the memory and CPU etc. This method increases the amount of data that can be transferred in one access by increasing the number of buses. On the other hand, in mobile devices such as a cellular phone provided with a memory, a package of a semiconductor device is desired to be miniaturized. An increase in the number of buses increases the number of pins formed in a memory. The increase in the number of pins is detrimental to the miniaturization of a memory.

Therefore, Japanese Unexamined Patent Application Publication No. 11-328971 (Choi) discloses to use the same pins for inputting/outputting a data signal and inputting an address signal.

The technique set forth by Choi discloses to input/output data through a pin for inputting addresses by inputting a particular control signal. However, the technique only discloses that a memory disclosed by Choi inputs/outputs data through a pin for address. Control of addresses for inputting and input of command to the memory are not taken into consideration for the memory disclosed by Choi. Moreover, Choi only discloses to switch an input of an address pin for an asynchronous memory.

On the other hand, there are memories in recent years that have a burst mode as in a synchronous DRAM (Dynamic Random Access Memory). In the burst mode, a memory carries out a specific operation when accessing the memory with different burst length or inputting a command to the memory.

When using an address terminal for inputting/outputting data in an asynchronous memory as the one disclosed by Choi, detailed access operations and command inputs to an address as in a SDRAM are not possible. On the other hand, in order to transfer a huge amount of data at a time, there has been a case where the number of pins for data input/output terminal is limited by an address terminal and a terminal for command input in a SDRAM or the like.

The present inventor has recognized that in the semiconductor memory device disclosed by Choi, if sharing a pin used for data input/output with an address pin, addresses and commands cannot be input through the address pin, thereby reducing the data transfer efficiency.

SUMMARY

In one embodiment, a semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address pin according to the transfer mode.

This configuration enables a semiconductor memory device which inputs various commands to support mass transfer.

The semiconductor memory device according to the present invention improves data transfer efficiency, keeps the number of pins to the minimum and miniaturizes the semiconductor memory device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereafter, this embodiment is described in detail with reference to the drawings. A semiconductor memory device (hereinafter referred to as a memory) of this embodiment has at least two operational modes. One of the operational modes (first transfer mode) supports sequential transfers in which a large amount of continuous data is input/output at once. The other mode (second transfer mode) is a random transfer operational mode in which a small amount of discrete data is input/output at random. The memory of this embodiment uses pins for inputting addresses as data input/output pins in the mode for transferring a large amount of data and operates in ×32 mode. In the operational mode for transferring data at random, only data input/output pins are used and operates in ×16 mode.

The block diagram of a SDRAM according to this embodiment is shown inFIG. 1. As shown inFIG. 1, a memory1of the SDRAM according to this embodiment includes a switching circuit (Add/IO and CMD/IO switching circuit)2, an address buffer3, an input/output buffer4, a memory array5, a control circuit6, a mode setting circuit (Mode Register Set: hereinafter referred to as a MRS control circuit)7, a data control unit8, a clock control unit9, a standby control unit10, an address latch circuit11, a row decoder12, a column decoder13and a sense amplifier14and a latch circuit15.

The switching circuit2is a circuit for switching a connection destination of pins for address input according to an output of the mode setting circuit7. In this embodiment, the switching circuit switches the case when an address pin is connected with the address buffer3and the case when an address pin is connected with a memory cell through the input/output buffer. The address buffer3outputs an address signal provided through the switching circuit2and the control circuit6when an address is input to the address pin. The input/output buffer4is a buffer circuit for inputting/outputting data with outside the memory. The memory array5has a plurality of memory cells arranged in a matrix to store data.

The control circuit6controls operation of the memory of this embodiment according to a command input through the switching circuit2. The control circuit6lets the MRS circuit7hold that it is a mass transfer when a command indicating of mass transfer is provided and also lets the MRS circuit7hold that it is a random transfer when a command indicating of random transfer is provided.

The MRS circuit7is a register for holding the operational mode of the memory and outputs a signal which controls operation of the memory according to the operational mode held there. The data control unit8is a circuit for selecting whether to output data in 32 bits output of ×32 mode or 16 bits output of ×16 mode. The clock control unit9outputs a control signal that synchronizes with a clock signal which is input externally to operate the memory. The standby control unit10stops operation of the memory when the memory is in standby status to be in a standby mode.

The address latch circuit11temporarily holds an address signal output by the address buffer3. The row decoder12decodes a row address from the address signal held in the address latch circuit11and selects any row of the memory array. The column decoder13decodes the address signal held in the address latch circuit and selects any column of the memory array.

The sense amplifier14amplifies a value read from a memory cell in the memory array5. The latch circuit15temporarily holds read-out data or write-in data.

Moreover, the memory1of this embodiment includes several kinds of pins. In this embodiment, these pins correspond to a plurality of address pins ADQ1to ADQ16in which address data or a data signal is input/output according to the operational mode of the memory, a plurality of data pins DQ1to DQ16in which data is input/output, a mode specification pin CMD_E in which a mode specification signal is input and a command pin CMD for inputting various commands to the memory. These pins are connected to the switching circuit2in the memory1. In an actual memory formed of a semiconductor integrated circuit, there are pins for clock input, power supply input and data mask or the like other than these pins, however they are omitted here.

Operation of the memory1of the present invention formed as described above is explained hereinafter. As mentioned above, the memory1of this embodiment has the mode for transferring a large amount of data (hereinafter referred to as a mass transfer mode) and the mode to transfer a small amount data at random (hereinafter referred to as a random transfer mode).

In the mass transfer mode, a command indicating of the mass transfer mode is input externally to the memory1through the command pin CMD. The command indicating of the mass transfer mode is input to the control circuit2through the switching circuit2. The control circuit6lets the MRS circuit7hold that is the mass transfer mode according to the transfer mode indicated by the provided command. The MRS circuit7outputs a signal indicating of the mass transfer mode to the data control unit8and the switching circuit2if set to the mass transfer mode.

In the case of the mass transfer mode, the data control unit8is set to ×32 mode and inputs/outputs data which is input/output from/to the memory to/from the latch circuit15in ×32 mode.

The switching circuit2treats the address pins ADQ1to ADQ16as data pins when receiving a signal indicating of the mass transfer mode. That is, a signal input and output to the address pins ADQ1to ADQ16is exchanged through the input/output buffer4, the latch circuit15and the data control unit8, as with the signal input to the data pins DQ1to DQ16.

On the other hand, in the random transfer mode, a command indicating of the random transfer mode is input externally to the memory1through the command pin CMD. The signal indicating of the random transfer mode is input to the control circuit6through the switching circuit2. The control circuit6lets the MRS circuit7hold that it is the random transfer mode according to the signal provided. The MRS circuit7outputs a signal indicating of the random transfer mode to the data control unit8and the switching circuit2if set to the random transfer mode.

In the case of the random transfer mode, the data control unit8is set to ×16 mode and inputs/outputs data which is input/output from/to the memory to/from the latch circuit15in ×16 mode.

When receiving the signal indicating of the random transfer mode, the switching circuit2inputs the signal provided to the address pins ADQ1to ADQ16into the address buffer3as data indicating an address of the memory. In the random transfer mode, the memory1accesses a memory cell according to an address through the address buffer3and the address latch circuit11.

With such configuration, by setting to the mass transfer mode when transferring a large amount of data, it is possible to transfer a large amount of data in ×32 mode using the address pins ADQ1to ADQ16without using complicated commands.

On the other hand, if an access to a memory becomes complicated, a complicated command using a part of the address pins ADQ can be input as a SDRAM. In the random transfer mode, it is possible to input/output in ×16 mode as a SDRAM while enabling a more detailed access to the memory1.

Operation of this embodiment according to the present invention is explained hereinafter with reference to a more detailed example. Here, a memory having a configuration of 512M×32 bit is explained as an example.

The pin configuration at the time of the mass data transfer mode is shown inFIG. 2. In the pin configuration shown inFIG. 2, the abovementioned pins operating as address pins and data pins are indicated as ADQ[00] to ADQ[23] and the data pins are indicated as DQ[24] to DQ[30]. Moreover, the mode specification pin CMD_E which supports the transfer mode is equivalent to a command enable CMD_E. The example shown inFIG. 2illustrates a data mask pin B which inputs a signal for masking input/output data in accordance with the actual operation of the memory1, a data strobe pin DQS which inputs a signal for adjusting an input/output timing of data, a clock signal input pin CLK and #CLK, a pin CDQ operating for command input and data input/output of a SDRAM and a chip enable pin CE.

In the case of a memory device of a related art that is able to operate as a SDRAM with 512×32 bit configuration, the number of necessary pins is; 22 address pins, 32 data pins, 1 clock pin and 9 command pins. The memory device of a related art requires at least 32 data pins to output in ×32 mode. Thus the 512M×32 bit memory device requires at least 64 pins.

On the other hand, in this embodiment, after letting the MRS circuit hold that it is the mass transfer mode through the command pin, by providing a signal of a specified level (for example L level) to the mode specification pin, the switching circuit2switches input/output of the address pin to data input/output. Therefore, with 32 pins combining the address pins and data pins, it is possible to output in ×32 mode.

Accordingly, it becomes possible to input and output data in ×32 mode with 43 pins as shown inFIG. 2. The command that can be input to the memory in this case are shown inFIG. 3. The timing chart of an access to the memory is shown inFIG. 4.

As shown inFIG. 3, when using in the mass transfer mode, the number of commands that can be input to the memory1is smaller than the SDRAM with 512M×32 bit configuration. However, in case of inputting/outputting a large amount of continuous data, a first address to be read out may be input once before inputting/outputting data as shown inFIG. 4, and then after that, it is possible to transfer data at high speed in ×32 mode.

FIG. 5shows the pin configuration of the random transfer mode. The control circuit6lets the MRS circuit hold the value when the command indicating of the random transfer mode is input and the switching circuit2switches an input to each pin as shown inFIG. 5. The commands that can be used in this random transfer mode are shown inFIG. 6. If set to the random transfer mode as shown inFIG. 6, it becomes possible to access to a memory cell by bank. Therefore, as shown inFIG. 7, a command and an address are input to access the memory according to the input address and then data is input/output.

As described above, in this embodiment, by providing a mode for inputting/outputting data through the address pins and enabling to use the address pins for inputting/outputting addresses and data in response to a command input externally, it is possible to perform a mass transfer without increasing the number of pins in the memory. As shown inFIG. 8, in the memory of 512M×32 bit, for example, 22 pins can be reduced. Moreover, in the mode to use the address pin as an address pin for its original use, as with a SDRAM of a related art, it is possible to perform detailed accesses using various commands.

Although it is explained in detail according to the embodiment of the present invention, the present invention is not limited to the above embodiment but various modifications can be made. For example, the pin configurations shown inFIGS. 2 to 7can be changed as appropriate according to the specification and the capacity of the target memory device. Moreover, in more detailed explanation, a mode is set by a command for specifying the mode and the address pins in the switching circuit are switched to the data pins by the mode specification pin. However the switching circuit may change the address pins to pins for inputting/outputting data by an output of the MRS circuit and the mode specification pin is not necessarily required. Furthermore, as long as it is the configuration for switching the address pins to the pins for data input/output by the mode specification pin, a predetermined value is held in the MRS circuit by the mode specification pin, and the mode is not necessarily specified by a command input.