Pixel unit and method for manufacturing the same

A method for manufacturing a pixel unit includes the following steps. A channel layer is formed. A first pattern layer is formed above the channel layer and includes a scan line and a gate electrode. A second pattern layer is formed above the first pattern layer and includes a data line and a source electrode, where the source electrode is electrically connected to the channel layer. A third pattern layer is formed above the second pattern layer and includes a drain electrode and an auxiliary electrode, where the drain electrode is electrically connected to the channel layer. The auxiliary electrode is electrically connected to the scan line through a first contact hole.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to and the benefit of, pursuant to 35 U.S.C. § 119(a), patent application Ser. No. 10/611,0571 filed in Taiwan on Mar. 29, 2017. The disclosure of the above application is incorporated herein in its entirety by reference.

FIELD

The present invention relates to a pixel unit and a method for manufacturing the same.

BACKGROUND

Liquid crystal displays to which thin film transistors (TFTs) are applied have been widely used in various consumptive electronic products. A thin film transistor-type liquid crystal display is mainly constituted by a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. Multiple thin film transistors arranged in an array and pixel electrodes each configured in correspondence to each thin film transistor are disposed on the thin film transistor array substrate to constitute pixel structures.

However, in response to various consumptive demands, sizes of liquid crystal displays to which thin film transistors are applied already have a lot of variations, and applications thereof from small sizes to large sizes all have been gradually developed. When a display with a large size is applied, and is designed to have high resolution, a design rule of a pixel structure process seems to be tougher. In view of this, as the design rule becomes tougher, when there is an unexpected situation in the process, display quality of the display will be affected.

SUMMARY

An implementation manner of the present invention provides a method for manufacturing a pixel unit, where in a process of manufacturing the pixel unit, a step of forming a data line is prior to a step of forming a conductor electrically connected to a channel layer and a scan line, and at least one step of forming an insulation layer is between the two steps, so that the data line can be prevented from being connected to a conductor inside a second contact hole and causing a short-circuit. Therefore, the performed process may have a broader design rule and have a better yield, so as to prevent display quality of a device to which the pixel unit is applied from being affected.

An implementation manner of the present invention provides a method for manufacturing a pixel unit, including the following steps: forming a channel layer; forming a first pattern layer above the channel layer, the first pattern layer including a scan line and a gate electrode; forming a second pattern layer above the first pattern layer, the second pattern layer including a data line and a source electrode, where the source electrode is electrically connected to the channel layer; and forming a third pattern layer above the second pattern layer, the third pattern layer including a drain electrode and an auxiliary electrode, where the drain electrode is electrically connected to the channel layer, and the auxiliary electrode is electrically connected to the scan line through a first contact hole.

In some implementation manners, the method for manufacturing a pixel unit further includes: forming a first electrode and a second electrode above the third pattern layer.

In some implementation manners, the method for manufacturing a pixel unit further includes: forming a planarization layer above the third pattern layer, and forming a second contact hole in the planarization layer, where the first electrode is located above the planarization layer, and is electrically connected to the drain electrode through the second contact hole.

In some implementation manners, one part of the auxiliary electrode is located inside the first contact hole, and when being observed along a horizontal direction, the data line does not overlap with the other part of the auxiliary electrode.

In some implementation manners, the drain electrode is electrically connected to the channel layer through a third contact hole, and one part of the drain electrode is located inside the third contact hole, where when being observed along another horizontal direction, the data line does not overlap with the other part of the drain electrode.

In some implementation manners, the method for manufacturing a pixel unit further includes: forming an insulation layer, where the step of forming the insulation layer is posterior to the step of forming the second pattern layer, and is prior to the step of forming the third pattern layer, and the first contact hole at least passes through the insulation layer.

An implementation manner of the present invention provides a pixel unit, disposed on a substrate and including: a channel layer, a first insulation layer, a first pattern layer, a second pattern layer, a third insulation layer, and a third pattern layer. The channel layer is disposed on the substrate. The first insulation layer covers the channel layer. The first pattern layer is disposed on the first insulation layer and includes a scan line and a gate electrode, where a vertical projection of the gate electrode onto the substrate at least partially overlaps with a vertical projection of the channel layer onto the substrate. The second insulation layer is disposed on the first insulation layer and covers the first pattern layer, where the first insulation layer and the second insulation layer share a first contact hole. The second pattern layer is disposed on the second insulation layer and includes a data line and a source electrode, where the source electrode is electrically connected to the channel layer through the first contact hole. The third insulation layer is disposed on the second insulation layer and covers the second pattern layer, where the second insulation layer and the third insulation layer share a second contact hole, and the first insulation layer, the second insulation layer, and the third insulation layer share a third contact hole. The third pattern layer is disposed on the third insulation layer and includes a drain electrode and an auxiliary electrode, where the auxiliary electrode is electrically connected to the scan line through the second contact hole, and the drain electrode is electrically connected to the channel layer through the third contact hole.

In some implementation manners, when being observed along a first horizontal direction, one part of the data line does not overlap with the auxiliary electrode.

In some implementation manners, one part of the drain electrode is located inside the third contact hole, and when being observed along a second horizontal direction, the data line does not overlap with the other part of the drain electrode.

In some implementation manners, one part of the auxiliary electrode is located inside the second contact hole, and when being observed along a first horizontal direction, the data line does not overlap with the other part of the auxiliary electrode.

In some implementation manners, the pixel unit further includes a planarization layer, a first electrode, a passivation layer, and a second electrode. The planarization layer covers the third pattern layer and includes a fourth contact hole. The first electrode is disposed on the planarization layer and is electrically connected to the drain electrode through the fourth contact hole. The passivation layer covers the first electrode. The second electrode is disposed on the planarization layer and is electrically isolated from the first electrode by means of the passivation layer.

DETAILED DESCRIPTION

A plurality of implementation manners of the present invention is disclosed below with reference to the accompanying drawings. For clear description, many details in practice will be described together in the following description. However, it should be understood that these details in practice should not be used to limit the present invention. That is, in some implementation manners of the present invention, these details in practice are not essential. In addition, to simplify the accompanying drawings, some conventional structures and elements are shown in a simple schematic manner in the accompanying drawings.

Herein, it may be understood that words, such as first, second, and third, are used to describe various elements, components, regions, or layers. However, these elements, components, regions, or layers should not be limited by these terms. These words are only used for distinguishing between single elements, components, regions, or layers. Therefore, a first element, component, region, or layer hereinafter may also be referred to as a second element, component, region, or layer without departing from the concept of the present invention.

In the implementation manners and the claims, unless an article in the present disclosure is particularly defined, the words “a” and “the” may generally refer to a single form or a plural form. It should be further understood that when “include”, “comprise”, “have”, and similar terms used in the present disclosure clearly indicate a feature, a region, an integer, a step, an operation, an element, and/or a component that is recorded in the present disclosure, but do not exclude one or more other features, regions, integers, steps, operations, elements, components and/or groups thereof.

When it is said that an element is “connected” or “coupled” to another element, the element may be directly connected to or coupled to the another element, or an additional element may exist between the element and the another element. In contrast, when an element is “directly connected” or “directly coupled” to another element, no additional element exists between the element and the another element.

The term “approximately”, “about” or “nearly” used herein should usually mean that an error of a value is within 20 percent of a given value or range, or preferably within 10 percent, or more preferably within 5 percent. Unless specifically indicated, a value maintained herein is considered as an approximate value, that is, an error or a range as indicated by the term “approximately”, “about” or “nearly”.

Each procedure of a method for manufacturing a pixel unit according to an embodiment of the present invention is described below. Referring toFIG. 1A,FIG. 1B, andFIG. 1C,FIG. 1Ais a schematic top view of forming a channel layer and a first pattern layer114according to some implementation manners of the present disclosure,FIG. 1Bis a schematic sectional view along line1B-1B′ inFIG. 1A, andFIG. 1Cis a schematic sectional view along line1C-1C′ inFIG. 1A. At this manufacturing stage, channel layers110a,110b, and110care first formed on a substrate102, the channel layers110a,110b, and110ccorrespond to three sequentially arranged pixels, and the channel layer110bis located between the channel layer110aand the channel layer110c. Shapes, size and/or orientations of the channel layer110aand the channel layer110cmay be the same. InFIG. 1A, opening directions of the channel layer110aand the channel layer110care, for example, the same. An opening direction of the channel layer110bis different from the opening direction of the channel layer110a. In an example in whichFIG. 1Ais viewed from the front, an opening of the channel layer110afaces toward the bottom, and an opening of the channel layer110bfaces toward an upper right corner, so that the opening direction of the channel layer110band the opening direction of the channel layer110aform an obtuse angle. A first insulation layer112is formed on the channel layers110a,110b, and110cand covers the channel layers110a,110b, and110c. Subsequently, the first pattern layer114is disposed on the first insulation layer112, and includes a scan line116and gate electrodes118a,118b, and118c. The scan line116may extend along a first direction D1. A vertical projection of the gate electrode118of the first pattern layer114onto the substrate102may at least partially overlap with a vertical projection of the channel layer110aonto the substrate102. That is, when the channel layer110aand the first pattern layer114are viewed from the top in a direction perpendicular to the substrate102, an overlapped part between the first pattern layer114and the channel layer110amay be considered as the gate electrode118aof the first pattern layer114. Similarly, an overlapped part between the first pattern layer114and the channel layer110bmay be considered as the gate electrode118bof the first pattern layer114, and an overlapped part between the first pattern layer114and the channel layer110cmay be considered as the gate electrode118cof the first pattern layer114. In this implementation manner, the channel layer110acorresponds to two gate electrodes118a, that is, a dual-gate electrode structure. The channel layers110band110chave similar situations, and details are not described herein again.

Referring toFIG. 2A,FIG. 2B, andFIG. 2C,FIG. 2Ais a schematic top view of forming a second pattern layer122according to some implementation manners of the present disclosure,FIG. 2Bis a schematic sectional view along line2B-2B′ inFIG. 2A, andFIG. 2Cis a schematic sectional view along line2C-2C′ inFIG. 2A. At this manufacturing stage, a second insulation layer120is formed on a first insulation layer112and covers a first pattern layer114, and subsequently, one part of the first insulation layer112and one part of the second insulation layer120are removed, so that the first insulation layer112and the second insulation layer120share first contact holes T1a, T1b, and T1c. After the first contact holes T1a, T1b, and T1care formed, parts of channel layers110a,110b, and110cmay be respectively exposed through the first contact holes T1a, T1b, and T1c. Subsequently, the second pattern layer122is further formed above the channel layers110a,110b, and110c, the first pattern layer114, and the second insulation layer120. The second pattern layer122may be isolated from the first pattern layer114by means of the second insulation layer120.

The second pattern layer122includes data lines124a,124b, and124cand source electrodes126a,126b, and126c. The data lines124a,124b, and124cmay respectively extend along a second direction D2, the data lines124a,124b, and124cmay be sequentially arranged along a first direction D1, and the second direction D2is substantially orthogonal to the first direction D1. That is, an extending direction of scan lines116a,116b, and116cand an extending direction of the data lines124a,124b, and124care substantially orthogonal to each other, so as to define pixel regions. A vertical projection of one part of the source electrode126aonto the substrate102may at least partially overlap with a vertical projection of the channel layer110aonto the substrate102, and this part of the source electrode126amay be filled into the first contact hole T1ato be electrically connected to the channel layer110athrough the first contact hole T1a. A vertical projection of one part of the source electrode126bonto the substrate102may at least partially overlap with a vertical projection of the channel layer110bonto the substrate102, and this part of the source electrode126bmay be filled into the first contact hole T1bto be electrically connected to the channel layer110bthrough the first contact hole T1b. A vertical projection of one part of the source electrode126conto the substrate102may at least partially overlap with a vertical projection of the channel layer110conto the substrate102, and this part of the source electrode126cmay be filled into the first contact hole T1cto be electrically connected to the channel layer110cthrough the first contact hole T1c.

Referring toFIG. 3A,FIG. 3B, andFIG. 3C,FIG. 3Ais a schematic top view of forming a second contact hole T2band third contact holes T3a, T3b, and T3caccording to some implementation manners of the present disclosure,FIG. 3Bis a schematic sectional view along line3B-3B′ inFIG. 3A, andFIG. 3Cis a schematic sectional view along line3C-3C′ inFIG. 3A. At this manufacturing stage, a third insulation layer128is formed on a second insulation layer120and covers a second pattern layer122. The thickness of the third insulation layer128is, for example, greater than or equal to 2000 Å, and the material of the third insulation layer128is, for example, silicon oxide. Subsequently, one part of a first insulation layer112, one part of the second insulation layer120, and one part of the third insulation layer128are removed, so that the second insulation layer120and the third insulation layer128share the second contact hole T2b, and the first insulation layer112, the second insulation layer120, and the third insulation layer128share the third contact holes T3a, T3b, and T3c. After the second contact hole T2band the third contact holes T3a, T3b, and T3care formed, some scan lines116may be exposed through the second contact hole T2b, and parts of channel layers110a,110b, and110cmay be respectively exposed through the third contact holes T3a, T3b, and T3c.

Referring toFIG. 4A,FIG. 4B, andFIG. 4C,FIG. 4Ais a schematic top view of forming a third pattern layer130according to some implementation manners of the present disclosure,FIG. 4Bis a schematic sectional view along line4B-4B′ inFIG. 4A, andFIG. 4Cis a schematic sectional view along line4C-4C′ inFIG. 4A. At this manufacturing stage, the third pattern layer130is formed on a third insulation layer128, and the third pattern layer130includes an auxiliary electrode132and drain electrodes134a,134b, and134c. As shown inFIG. 4C, one part of the auxiliary electrode132is located inside a second contact hole T2b, so that the auxiliary electrode132is electrically connected to a scan line116through the second contact hole T2b. The drain electrode134ais electrically connected to a channel layer110athrough a third contact hole T3a, the drain electrode134bis electrically connected to a channel layer110bthrough a third contact hole T3b, and the drain electrode134cis electrically connected to a channel layer110cthrough a third contact hole T3c.

Because a step of forming a third insulation layer128is posterior to a step of forming a second pattern layer122and is prior to a step of forming a third pattern layer130, the second pattern layer122and the third pattern layer130may be considered to be formed on different planes. That is, when being observed along a horizontal direction, parts of data lines124a,124b, and124cdo not overlap with the auxiliary electrode132. For example, when being observed at position O1in first horizontal direction inFIG. 4A, the data line124adoes not overlap with the auxiliary electrode132, the data line124bdoes not overlap with the auxiliary electrode132, and the data line124cdoes not overlap with the auxiliary electrode132. That is, the data lines124a,124b, and124cand the auxiliary electrode132are not on a same horizontal plane. When being observed at position O2in second horizontal direction inFIG. 4A, although the data line124aoverlaps with one part of the drain electrode134a, the data line124adoes not overlap with the other part of the drain electrode134a. That is, one part of the drain electrode134athat is located above the third insulation layer128and the data line124aare not located on a same horizontal plane. Similarly, the data line124band the drain electrode134b, and the data line124cand the drain electrode134chave the foregoing correspondence. Details are not described herein again.

By means of the configuration, a yield of a formed structure may be improved. For example, as shown in4A, when the formed structure is viewed in a direction perpendicular to a substrate102, because the second pattern layer122and the third pattern layer130may be considered to be formed on different horizontal planes, a short-circuit due to an etching issue between the data line124aand the drain electrode134a, between the data line124band the drain electrode134b, and between the data line124cand the drain electrode134cmay be prevented. For example, a short-circuit due to respective connections between the data lines124a,124b, and124cand conductors inside the third contact holes T3a, T3b, and T3cmay be prevented. Similarly, a short-circuit due to a connection between the data line124band a conductor inside the second contact hole T2bmay also be prevented, and a short-circuit due to an etching issue between the data line124band the auxiliary electrode132may also be prevented. Therefore, by means of the foregoing manufacturing sequence, the performed process may have a broader design rule, and would not be limited by an etching step. On the other hand, because a short-circuit caused due to etching issue is prevented, even if the foregoing process is applied to a panel with a large size designed to have high resolution, the performed process may still have a specific yield, so as to prevent display quality from being affected.

In addition, after the third pattern layer130is formed, the auxiliary electrode132of the third pattern layer130and the scan line116are configured to be connected in parallel to each other. By means of the parallel connection configuration, the auxiliary electrode132may reduce impedance of the scan line116, so as to reduce resistance-capacitance product values (RC values) of the scan line116and the gate electrode118(referring toFIG. 1A). For example, when the material of the scan line116includes molybdenum, the material of the auxiliary electrode132may include aluminum, copper, titanium, or molybdenum, so as to reduce the impedance of the scan line116by means of the parallel connection configuration.

Referring toFIG. 5A,FIG. 5B, andFIG. 5C,FIG. 5Ais a schematic top view of forming a first electrode according to some implementation manners of the present disclosure,FIG. 5Bis a schematic sectional view along line5B-5B′ inFIG. 5A, andFIG. 5Cis a schematic sectional view along line5C-5C′ inFIG. 5A. At this manufacturing stage, a planarization layer136may be first formed on a third insulation layer128, and covers an auxiliary electrode132and drain electrodes134a,134b, and134cof a third pattern layer130. Subsequently, one part of the planarization layer136is removed, so that the planarization layer136has fourth contact holes T4a, T4b, and T4c. After the fourth contact holes T4a, T4b, and T4care formed, first parts of the drain electrodes134a,134b, and134cmay be respectively exposed through the fourth contact holes T4a, T4b, and T4c. First electrodes138a,138b, and138care formed on the planarization layer136. A vertical projection of the first electrode138aonto a substrate102may at least partially overlap with a vertical projection of the drain electrode134aonto the substrate102, and one part of the first electrode138amay be filled into the fourth contact hole T4a, so as to be electrically connected to the drain electrode134athrough the fourth contact hole T4a. A vertical projection of the first electrode138bonto the substrate102may at least partially overlap with a vertical projection of the drain electrode134bonto the substrate102, and one part of the first electrode138bmay be filled into the fourth contact hole T4b, so as to be electrically connected to the drain electrode134bthrough the fourth contact hole T4b. A vertical projection of the first electrode138conto the substrate102may at least partially overlap with a vertical projection of the drain electrode134conto the substrate102, and one part of the first electrode138cmay be filled into the fourth contact hole T4c, so as to be electrically connected to the drain electrode134cthrough the fourth contact hole T4c.

Referring toFIG. 6A,FIG. 6B, andFIG. 6C,FIG. 6Ais a schematic top view of forming a second electrode according to some implementation manners of the present disclosure,FIG. 6Bis a schematic sectional view along line6B-6B′ inFIG. 6A, and FIG.6C is a schematic sectional view along line6C-6C′ inFIG. 6A. At this manufacturing stage, a passivation layer140may be first formed on a planarization layer136and covers first electrodes138aand138b. The thickness of the passivation layer140is, for example, 1000 Å, and the material of the passivation layer140is, for example, silicon nitride. Subsequently, the second electrode142may be formed on the passivation layer140, and is isolated from the first electrodes138aand138bby means of the passivation layer140. The second electrode142has openings144a,144b, and144c, and when the second electrode142is viewed in a direction perpendicular to the substrate102, the openings144a,144b, and144crespectively fall within corresponding pixel regions, and the openings144a,144b, and144crespectively overlap with first electrodes138a,138b, and138c.

In a combination of the first electrodes138a,138b, and138cand the second electrode142, one of them may serve as a pixel electrode, and the other one may serve as a common electrode, for controlling alignment of liquid crystal molecules (not shown) by means of an electric field therebetween. After the second electrode142is formed, a combination of structures of layers on the substrate102may serve as a pixel unit, and a combination of the substrate102and the pixel unit may be considered as an array substrate.

In conclusion, a method for manufacturing a pixel unit is provided. In a process of manufacturing the pixel unit, a step of forming a data line is prior to a step of forming a conductor electrically connected to a channel layer and a scan line, and at least one step of forming an insulation layer is between the two steps, so that a short-circuit due to a connection between the data line and a conductor inside a contact hole can be prevented. Therefore, the performed process may have a broader design rule and have a better yield. On the other hand, an auxiliary electrode connected in parallel to a scan line may be formed, and by means of the auxiliary electrode, impedance of the scan line may be reduced, so as to reduce an RC value of a gate electrode.

Although the present invention is disclosed as above by using multiple implementation manners, these implementation manners are not used to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, and therefore the protection scope of the present invention should be as defined by the appended claims.