SEMICONDUCTOR PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING SEMICONDUCTOR PROCESSING APPARATUS

A method of manufacturing a semiconductor device includes: performing a first semiconductor process on a semiconductor wafer including a front side and a back side opposing the front side; loading the semiconductor wafer into a semiconductor processing apparatus including a support, a spraying apparatus, and a warpage measuring apparatus, wherein the semiconductor wafer is supported by the support, wherein the spraying apparatus is disposed below the semiconductor wafer, and the warpage measuring apparatus is an apparatus configured to measure warpage of the semiconductor wafer; forming a warpage compensation pattern on the back side of the semiconductor wafer using the spraying apparatus until a warpage measurement value of the semiconductor wafer is within a predetermined range, while measuring warpage of the semiconductor wafer using the warpage measuring apparatus; and unloading, from the semiconductor processing apparatus, the semiconductor wafer on which the warpage compensation pattern is formed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0022349 filed on Feb. 20, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor processing apparatus and a method of manufacturing a semiconductor device using the same.

DISCUSSION OF THE RELATED ART

In accordance with a high degree of integration of semiconductor devices, semiconductor devices, including three-dimensionally arranged memory cells, have been under development. In semiconductor devices including three-dimensionally arranged memory cells, the three-dimensionally arranged memory cells are formed, and then warpage of a semiconductor wafer may be intensified, which may result in defects in a subsequent semiconductor process.

SUMMARY

According to some example embodiments of the present inventive concept, a method of manufacturing a semiconductor device includes: performing a first semiconductor process on a semiconductor wafer, wherein the semiconductor wafer on which the first semiconductor process has been performed has a front side, on which an integrated circuit is formed, and a back side opposing the front side; loading the semiconductor wafer, on which the first semiconductor process has been performed, into a semiconductor processing apparatus including a support, a spraying apparatus, and a warpage measuring apparatus, wherein the semiconductor wafer is supported by the support, wherein the back side of the semiconductor wafer is positioned to face in a downward direction, wherein the spraying apparatus is disposed below the semiconductor wafer that is supported by the support, and the warpage measuring apparatus is an apparatus configured to measure warpage of the semiconductor wafer that is supported by the support; forming a warpage compensation pattern on the back side of the semiconductor wafer using the spraying apparatus until a warpage measurement value of the semiconductor wafer, which is measured by the warpage measuring apparatus, is within a predetermined range, while measuring warpage of the semiconductor wafer using the warpage measuring apparatus; and unloading, from the semiconductor processing apparatus, the semiconductor wafer on which the warpage compensation pattern is formed.

According to some example embodiments of the present inventive concept, a method of manufacturing a semiconductor device includes: performing a semiconductor process on a semiconductor wafer, wherein the semiconductor wafer on which the semiconductor process has been performed has a front side, on which an integrated circuit is formed, and a back side opposing the front side; loading the semiconductor wafer, on which the semiconductor process has been performed, into a semiconductor processing apparatus including a support, a warpage measuring apparatus, and a spraying apparatus, wherein the semiconductor wafer is supported by the support, wherein the back side of the semiconductor wafer is positioned to face in a downward direction, and wherein the spraying apparatus is disposed below the semiconductor wafer that is supported by the support; measuring warpage of the semiconductor wafer that is supported by the support by using the warpage measuring apparatus; forming a first warpage compensation pattern on the back side of the semiconductor wafer by spraying a warpage compensation material in a liquid phase onto the back side of the semiconductor wafer by using the spraying apparatus; measuring warpage of the semiconductor wafer on which the first warpage compensation pattern is formed by using the warpage measuring apparatus; and unloading, from the semiconductor processing apparatus, the semiconductor wafer on which the first warpage compensation pattern is formed, when a warpage measurement value of the semiconductor wafer on which the first warpage compensation pattern is formed, which is measured by the warpage measuring apparatus, is within a predetermined range.

According to some example embodiments of the present inventive concept, a semiconductor processing apparatus includes: a support configured to support a semiconductor wafer having a front side, on which an integrated circuit is formed, and a back side opposing the front side, wherein an edge region of the back side of the semiconductor wafer is disposed on the support; a spraying apparatus disposed below the semiconductor wafer that is supported by the support, wherein the spraying apparatus is configured to spray a warpage compensation material in a liquid phase toward a first region, among a plurality of regions of the back side of the semiconductor wafer; a warpage measuring apparatus configured to measure warpage of the semiconductor wafer that is supported by the support; and a controller configured to move the spraying apparatus to form a warpage compensation pattern reducing warpage of the semiconductor wafer, and to control spraying, from the spraying apparatus, of the warpage compensation material toward the first region, according to a warpage measurement value of the semiconductor wafer measured by the warpage measuring apparatus.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, for example, terms such as “upper portion,” “intermediate portion,” and “lower portion” may be replaced with other terms, for example, “first,” “second,” and “third” to describe elements of the specification. Terms such as “first,” “second,” and “third” may be used to describe different elements, but the elements are not limited by the terms, and a “first element” may be referred to as a “second element.”

First,FIGS.1A,1B, and1Cillustrate a semiconductor processing apparatus and a semiconductor device manufacturing method using the same according to an example embodiment of the present inventive concept. InFIGS.1A,1B, and1C,FIG.1Ais a schematic process flowchart illustrating a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept.FIG.1Bis a schematic diagram illustrating an example of a semiconductor processing apparatus according to an example embodiment of the present inventive concept, andFIG.1Cis a schematic plan view illustrating a back side of a semiconductor wafer to describe a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept.

Referring toFIGS.1A,1B, and1C, a first semiconductor process may be performed on a semiconductor wafer WF (S10). The semiconductor wafer WF on which the first semiconductor process has been performed may be a wafer in which warpage may occur. For example, the semiconductor wafer WF on which the first semiconductor process has been performed may be in a state in which nonlinear warpage may occur.

A back side of the semiconductor wafer WF may have a plurality of regions B_1, B_2, B_3, and B_4. The back side of the semiconductor wafer WF may further have an edge region WF_E and a central region WF_C that is between the plurality of regions B_1, B_2, B_3, and B_4.

The back side of the semiconductor wafer WF may further have intermediate regions WF_I disposed between the plurality of regions B_1, B_2, B_3, and B_4such that the plurality of regions B_1, B_2, B_3, and B_4are spaced apart from each other, between the edge region WF_E and the central region WF_C.

The plurality of regions B_1, B_2, B_3, and B_4may include a first region B_1, a second region B_2, a third region B_3, and a fourth region B_4. The semiconductor wafer WF may have a reference region WF_N such as a notch, a flat zone, a groove, an indentation or the like. The plurality of regions B_1, B_2, B_3, and B_4may be divided using the reference region WF_N as a reference.

The semiconductor wafer WF may be loaded into a semiconductor processing apparatus1a(S20).

The semiconductor processing apparatus1amay include a support20, a spraying apparatus36, and a warpage measuring apparatus33within a processing chamber10.

The semiconductor processing apparatus1amay further include a curing apparatus39within the processing chamber10.

The semiconductor processing apparatus1amay further include a controller50.

The support20may support the semiconductor wafer WF.

In an example, the support20may be in contact with the edge region WF_E of the back side of the semiconductor wafer WF, and may support the edge region WF_E of the semiconductor wafer WF.

In an example, the support20may include a central support portion extending up to a central region WF_C between the plurality of regions B_1, B_2, B_3, and B_4from an edge support portion of the support20supporting the edge region WF_E of the back side of the semiconductor wafer WF. InFIG.1C, a region indicated by WF_E may be supported by an edge support portion of the support20, and regions indicated WF_I and WF_C may be supported by a central support portion of the support20.

In an example, the warpage measuring apparatus33may be disposed on a level lower than that of the semiconductor wafer WF supported by the support20.

In an example, the warpage measuring apparatus33may be a measuring apparatus using optics, but example embodiments of the present inventive concept are not limited thereto.

The spraying apparatus36may be disposed below the semiconductor wafer WF supported by the support20. The spraying apparatus36may be a dispenser.

Warpage of the semiconductor wafer WF may be measured (S30). The warpage of the semiconductor wafer WF, supported by the support20, may be measured by using the warpage measuring apparatus33.

A warpage compensation pattern BCP may be formed on the back side of the semiconductor wafer WF (S40). According to a warpage measurement value of the semiconductor wafer WF measured by the warpage measuring apparatus33, a warpage compensation material may be sprayed onto the back side of the semiconductor wafer WF, supported by the support20, using the spraying apparatus36to form a warpage compensation pattern on the back side of the semiconductor wafer WF.

The warpage of the semiconductor wafer WF may be measured (S50). Here, the semiconductor wafer WF may be a semiconductor wafer on which the warpage compensation pattern is formed.

It may be determined whether the warpage measurement value is within an allowable range (S60). When the warpage measurement value is not within the allowable range, an operation (S40) of forming the warpage compensation pattern on the back side of the semiconductor wafer WF and an operation (S50) of measuring the warpage of the semiconductor wafer WF may be repeatedly performed until the warpage measurement value is within the allowable range.

A warpage compensation pattern that is initially formed on the back side of the semiconductor wafer WF may be defined as a first warpage compensation pattern. When the warpage measurement value is not within the allowable range after the first warpage compensation pattern is formed, a warpage compensation pattern may be continuously formed on the back side of the semiconductor wafer WF until the measurement value is within an allowable range. For example, additional warpage compensation patterns may be formed on the back side of the semiconductor wafer WF.

When the warpage measurement value is within the allowable range, the semiconductor wafer WF may be unloaded from the semiconductor processing apparatus1a(S70). A second semiconductor process may be performed on the semiconductor wafer WF on which the warpage compensation pattern is formed (S80).

In an example embodiment of the present inventive concept, while the warpage of the semiconductor wafer WF is measured using the warpage measuring apparatus33, the warpage compensation pattern may be formed on the back side BS of the semiconductor wafer WF by using the spraying apparatus36until the warpage measurement value of the semiconductor wafer WF, measured by the warpage measuring apparatus33, is within the allowable range.

The warpage compensation material, sprayed onto the back side BS of the semiconductor wafer WF supported by the support20by using the spraying apparatus36, may be sprayed in a liquid phase.

The warpage compensation material may include, for example, polyimide or a polyimide-based material.

The warpage compensation material may include, for example, a spin-on-hardmask (SOH) material.

The warpage compensation material may include, for example, a photo-imageable dielectric (PID) material.

The warpage compensation material may be sprayed onto the back side BS of the semiconductor wafer WF in a liquid phase.

The warpage compensation material, sprayed onto the back side BS of the semiconductor wafer WF, may be adhered to the back side BS of the semiconductor wafer WF and may be then cured. For example, the warpage compensation material, sprayed onto the back side BS of the semiconductor wafer WF, may be cured by the curing apparatus39on the back side BS of the semiconductor wafer WF, and thus may be formed as the warpage compensation pattern that is in contact with the back side BS of the semiconductor wafer WF to reduce the warpage of the semiconductor wafer WF.

The spraying apparatus36may be configured to three-dimensionally move along an X-axis, a Y-axis, and a Z-axis of an X-Y-Z coordinate system, to spray the warpage compensation material onto the back side BS of the semiconductor wafer WF supported by the support20.

In an example, the warpage measuring apparatus33may be configured to move together with the spraying apparatus36. For example, the warpage measuring apparatus33and the spraying apparatus36may be attached or connected to each other and may be connected to a track on which the warpage measuring apparatus33and the spraying apparatus36may move; however, the present inventive concept is not limited thereto.

In an example, the curing apparatus39may be configured to move together with the spraying apparatus36. For example, the curing apparatus39and the spraying apparatus36may be attached or connected to each other and may be connected to a track on which the curing apparatus39and the spraying apparatus36may move; however, the present inventive concept is not limited thereto.

In an example, the curing apparatus39may be a UV curing apparatus or an infrared curing apparatus, but example embodiments of the present inventive concept are not limited thereto.

In an example, the semiconductor processing apparatus1amay further include a base30simultaneously moving the warpage measuring apparatus33, the spraying apparatus36, and the curing apparatus39. For example, the base30may be on a track or rail on which the base30may move. The warpage measuring apparatus33, the spraying apparatus36, the curing apparatus39, and the base30may be included in a module27.

In an example, the module27may be disposed in plurality. For example, the module27may include a first module27aand a second module27b.

Each of the first and second modules27aand27bmay include the spraying apparatus36. Accordingly, a plurality of spraying apparatuses, for example, first and second spraying apparatuses36, may be disposed below the semiconductor wafer WF that is supported by the support20. The first and second spraying apparatuses36may spray the warpage spraying material onto different regions, among the plurality of regions B_1, B_2, B_3, and B_4of the back side BS of the semiconductor wafer WF.

The first spraying apparatus36of the first module27amay spray the warpage compensation material onto the first region B_1of the back side BS of the semiconductor wafer WF from below the first region B_1of the back side BS of the semiconductor wafer WF. The second spraying apparatus36of the second module27bmay spray the warpage compensation material onto the third region B_3of the back side BS of the semiconductor wafer WF from below the third region B_3of the back side of the semiconductor wafer WF. The warpage compensation pattern may include a first warpage compensation pattern, which is formed by the first spraying apparatus36of the first module27a, and a second warpage compensation pattern, which is formed by the second spraying apparatus36of the second module27b.

According to the warpage measurement value of the semiconductor wafer WF measured by the warpage measuring apparatus33, the controller50may be configured to move the spraying apparatus36along an X-axis, a Y-axis, and a Z-axis of an X-Y-Z coordinate system to form a warpage compensation pattern that reduces the warpage of the semiconductor wafer WF, and to control spraying of the warpage compensating material toward one region, among the plurality of regions B_1, B_2, B_3, and B_4of the back side BS of the semiconductor wafer WF.

The first and second modules27aand27bmay be independently moved and may be independently controlled, by the controller50.

The warpage measuring apparatus33may be disposed on a level lower than that of the semiconductor wafer WF that is supported by the support20, but example embodiments of the present inventive concept are not limited thereto. Hereinafter, referring toFIG.2, a warpage measuring apparatus33′, disposed above the semiconductor wafer WF that is supported by the support20, will be described.FIG.2is a schematic diagram illustrating a modification of a semiconductor processing apparatus according to an example embodiment of the present inventive concept.

Referring toFIG.2, the warpage measuring apparatus (33inFIG.1B), disposed on a level lower than that of the semiconductor wafer WF that is supported by the support20described with reference toFIG.1, may be replaced with the warpage measuring apparatus33′, disposed above the semiconductor wafer WF. Accordingly, the module27inFIG.1Bmay be replaced with a module27′ in which the warpage measuring apparatus (33inFIG.1B) is omitted. The module27′ may include first and second modules27a′ and27b′, which are independently moved and independently controlled, and each of the first and second modules27a′ and27b′ may include a base30′, corresponding to the base30, and a spraying apparatus36′, corresponding to the spraying apparatus36. Each of the first and second modules27a′ and27b′ may further include a curing apparatus39′, corresponding to the curing apparatus39.

Next, with reference toFIG.3, an example of the semiconductor wafer WF described above will be described.FIG.3is a schematic cross-sectional view illustrating a cross-sectional structure of a semiconductor wafer according to an example embodiment of the present inventive concept.

Referring toFIG.3, a semiconductor wafer WFa according to an example embodiment of the present inventive concept may include a substrate SUB and an integrated circuit region ICR on the substrate SUB. The semiconductor wafer WFa may have a front side FS on which the integrated circuit region ICR is formed and a back side BS opposing the front side FS.

The integrated circuit region ICR may include a plurality of memory cell array regions MCA on the substrate SUB, and an insulating structure INS covering the plurality of memory cell array regions MCA on the substrate SUB.

Each of the plurality of memory cell array regions MCA may include gate electrodes GE, vertically stacked and spaced apart from each other, and vertical channel structures CH passing through the gate electrodes GE. Each of the plurality of memory cell array regions MCA may include three-dimensionally arranged memory cells.

By the operation (S40) of forming the warpage compensation pattern on the back side BS of the semiconductor wafer (WF inFIG.1B) described with reference toFIG.1A, the warpage compensation pattern BCP, described with reference toFIG.1A, may be formed on the back side BS of the semiconductor wafer WFa. Accordingly, the semiconductor wafer WFa may include the warpage compensation pattern BCP.

The semiconductor wafer WFa may have an edge region WF_E and a central region WF_C, as described with reference toFIG.1C.

InFIG.3, a direction of DI may refer to a direction extending away from the edge region WF_E and toward an inner region of the semiconductor wafer WFa.

The warpage compensation pattern BCP may include a first-side warpage compensation pattern BCPa1and a second-side warpage compensation pattern BCPa2, that are spaced apart from each other.

The warpage compensation pattern BCP may be disposed between the edge region WF_E and the central region WF_C.

Next, with reference toFIG.4, an example of the warpage compensation pattern BCP described above will be described.FIG.4is a plan view illustrating a back side of a semiconductor wafer WFb, including a warpage compensation pattern, formed by a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept.

Referring toFIG.4together withFIGS.1A,1B,1C, and3, the first-side warpage compensation pattern BCPa1inFIG.3may be formed as a first-side warpage compensation pattern BCPb1including first and second warpage compensation patterns CP1aaand CP2baformed in the first region B_1, and the second-side warpage compensation pattern BCPa2inFIG.3may be formed as a second-side warpage compensation pattern BCPb2including first and second warpage compensation patterns CP1aband CP2bbformed in the third region B_3.

In some example embodiments of the present inventive concept, the terms “first-side warpage compensation pattern” and “second-side warpage compensation pattern” may be used to distinguish warpage compensation patterns formed in different regions, among the plurality of regions B_1, B_2, B_3, and B_4of the back side of the semiconductor wafer WF.

An example of a method of forming the first and second warpage compensation patterns CP1aaand CP2baof the first-side warpage compensation pattern BCPb1and/or the first and second warpage compensation patterns CP1aband CP2bbof the second-side warpage compensation pattern BCPb2will be described with reference toFIGS.5A and5B.FIG.5Ais a schematic plan view illustrating a first warpage compensation pattern formed first, among the warpage compensation patterns BCP, andFIG.5Bis a schematic plan view illustrating a second warpage compensation pattern formed later, among the warpage compensation patterns BCP.

Referring toFIGS.5A and5Btogether withFIGS.1A,1B,1C,3, and4, according to a warpage measurement value of the semiconductor wafer WF measured by the warpage measuring apparatus33, a warpage compensation material may be sprayed onto the back side of the semiconductor wafer WF that is supported by the support20by using the spraying apparatus36to form a warpage compensation pattern CP1acon the back side BS of the semiconductor wafer WF.

Warpage of the semiconductor wafer WF on which the first warpage compensation pattern CP1acis formed may be measured.

When the warpage measurement value of the semiconductor wafer WF on which the first warpage compensation pattern CP1acis formed is outside of an allowable range, according to the warpage measurement value of the semiconductor wafer WF on which the first warpage compensation pattern CP1acis formed, which is measured by the warpage measuring apparatus33, the warpage compensation material may be sprayed onto the back side BS of the semiconductor wafer WF by using the spraying apparatus36to form a second warpage compensation pattern CP2bcon the back side BS of the semiconductor wafer WF.

Accordingly, a warpage compensation pattern BCPc, including the first and second warpage compensation patterns CP1acand CP2bc, may be formed on the back side BS of the semiconductor wafer WF.

In some example embodiments of the present inventive concept, the terms “first warpage compensation pattern” and “second warpage compensation pattern” refer to may refer to elements included in a warpage compensation pattern formed in one region, among the plurality of regions B_1, B_2, B_3, and B_4of the back side BS of the semiconductor wafer WF.

In some example embodiments of the present inventive concept, in one region among the plurality of regions B_1, B_2, B_3, and B_4of the back side BS of the semiconductor wafer WF, the term “first warpage compensation pattern” may refer to a warpage compensation pattern formed first, and the term “second warpage compensation pattern” may refer to a warpage compensation pattern formed later.

In an example, the first warpage compensation pattern CP1acmay include line portions extending in the direction of D1(e.g., a first direction) from the edge region WF_E to the central region WF_C.

In an example, the second warpage compensation pattern CP2bcmay include line portions extending in the direction of D1.

In an example, the line portions of the second warpage compensation pattern CP2bcmay be disposed between the line portions of the first warpage compensation pattern CP1ac. For example, the second warpage compensation pattern CP2bcand the first warpage compensation pattern CP1acmay be alternately arranged.

In an example, the line portions of the second warpage compensation pattern CP2bcand the line portions of the first warpage compensation pattern CP1acmay have the same width as each other, but example embodiments of the present inventive concept are not limited thereto. Hereinafter, various modifications of the line portions of the second warpage compensation pattern CP2bcand the line portions of the first warpage compensation pattern CP1acwill be described with reference toFIGS.6,7,8, and9.

FIGS.6,7,8, and9are plan views illustrating various modifications of the warpage compensation pattern BCP described above, respectively.

According to an example embodiment of the present inventive concept, referring toFIG.6, a warpage compensation pattern BCPd may include a first warpage compensation pattern CP1adhaving line portions and a second warpage compensation pattern CP2bdhaving line portions. A width of at least one of the line portions of the second warpage compensation pattern CP2bdmay be narrower than a width of at least one of the line portions of the first warpage compensation pattern CP1ad.

According to an example embodiment of the present inventive concept, referring toFIG.7, a warpage compensation pattern BCPe may include a first warpage compensation pattern CP1aehaving line portions CP1ae1and CP1ae2and a second warpage compensation pattern CP2behaving line portions. The line portions CP1ae1and CP1ae2of the first warpage compensation pattern CP1aemay include first line portions CP1ae1having a first width and second line portions CP1ae2having a second width narrower than the first width. The first line portions CP1ae1may be disposed between the second line portions CP1ae2.

According to an example embodiment of the present inventive concept, referring toFIG.8, a warpage compensation pattern BCPf may include a first warpage compensation pattern CP1afhaving line portions CP1af1and CP1af2and a second warpage compensation pattern CP2bfhaving line portions. The line portions CP1af1and CP1af2of the first warpage compensation pattern CP1afmay include first line portions CP1af1having a first width and second line portions CP1af2having a second width wider than the first width. The first line portions CP1af1may be disposed between the second line portions CP1af2.

According to an example embodiment of the present inventive concept, referring toFIG.9, the warpage compensation pattern BCPg may include a first warpage compensation pattern CP1ag, which includes line portions CP1ag1and CP1ag2, and a second warpage compensation pattern CP2bghaving line portions. The line portions CP1ag1and CP1ag2of the first warpage compensation pattern CP1agmay include first line portions CP1ag1, each of which has portions CPag1aaand CP2bg1abwith different widths from each other, and second line portions CP1ag2, each of which has a constant width.

Each of the first warpage compensation pattern CP1ag1may include a first portion CP2bg1ab, which has a first width, and a second portion CP1ag1aa, which has a second width wider than the first width.

To effectively reduce the warpage of the semiconductor wafer, the first portion CP2bg1abmay be disposed to be closer to the edge region WF_E than the second portion CP1ag1aa.

The warpage compensation pattern BCP described above with reference toFIGS.3,4,5A,5B,6,7, and9may include line portions extending in the direction of D1, but example embodiments of the present inventive concept are not limited thereto. Hereinafter, an example of a compensation pattern including line portions extending in a direction of D2, which is substantially perpendicular to the direction of D1, will be described with reference toFIGS.10,11, and12.FIG.10is a plan view illustrating a back side of a semiconductor wafer WFc including a warpage compensation pattern formed by a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept.

Referring toFIG.10together withFIGS.1A,1B,1C, and3, the first-side warpage compensation pattern BCPa1inFIG.3may be formed as a first-side warpage compensation pattern BCPh, including first and second warpage compensation patterns CP1ahand CP2bh, formed in the second region B_2, and the second-side warpage compensation pattern BCPa2inFIG.3may be formed as a second-side warpage compensation pattern BCPi, including first and second warpage compensation patterns CP1aiand CP2bi, formed in the fourth region B_4.

In some example embodiments of the present inventive concept, the terms “first-side warpage compensation pattern” and “second-side warpage compensation pattern” may be used to distinguish warpage compensation patterns from each other that are formed in different regions, among the plurality of regions B_1, B_2, B_3, and B_4of the back side of the semiconductor wafer WF.

An example of a method of forming the first and second warpage compensation patterns CP1ahand CP2bhof the first-side warpage compensation pattern BCPh and/or the first and second warpage compensation patterns CP1aiand CP2biof the second-side warpage compensation pattern BCPi will be described with reference toFIGS.10and11.FIG.11is a schematic plan view illustrating a first warpage compensation pattern formed first, among the warpage compensation patterns BCP, andFIG.12is a schematic plan view illustrating a second warpage compensation pattern formed after the first warpage compensation pattern, among the warpage compensation patterns BCP.

Referring toFIGS.11and12together withFIGS.1A,1B,1C,3, and10, according to a warpage measurement value of the semiconductor wafer WF measured by the warpage measuring apparatus33, a warpage compensation material may be sprayed onto the back side BS of the semiconductor wafer WF, which is supported by the support20, by using the spraying apparatus36in the second direction D2to form a first warpage compensation pattern CP1ajon the back side BS of the semiconductor wafer WF. Warpage of the semiconductor wafer WF on which the first warpage compensation pattern CP1ajis formed may be measured. When the warpage measurement value of the semiconductor wafer WF on which the first warpage compensation pattern CP1ajis formed is outside of an allowable range, according to the warpage measurement value of the semiconductor wafer WF on which the first warpage compensation pattern CP1ajis formed, the warpage compensation material may be sprayed onto the back side BS of the semiconductor wafer WF by using the spraying apparatus36in the second direction D2to form a second warpage compensation pattern CP2bjon the back side BS of the semiconductor wafer WF.

Accordingly, a warpage compensation pattern BCPj, including the first and second warpage compensation patterns CP1ajand CP2bj, may be formed on the back side BS of the semiconductor wafer WF.

In an example, the first warpage compensation pattern CP1ajmay include line portions extending in the direction of D2(e.g., a second direction).

In an example, the second warpage compensation pattern CP2bjmay include line portions extending in the direction of D2.

In an example, the line portions of the second warpage compensation pattern CP2bjmay be disposed between the line portions of the first warpage compensation pattern CP1aj. For example, the line portions of the second warpage compensation pattern CP2bjmay be alternately arranged with the line portions of the first warpage compensation pattern CP1aj.

In an example, the line portions of the second warpage compensation pattern CP2bjand the line portions of the first warpage compensation pattern CP1ajmay have the same width as each other, but example embodiments of the present inventive concept are not limited thereto. Hereinafter, various modifications of the warpage compensation pattern BCPj will be described with reference toFIGS.13and14, respectively.FIGS.13and14are plan views illustrating various modifications of the warpage compensation pattern BCP described above, respectively.

According to an embodiment of the present inventive concept, referring toFIG.13, a warpage compensation pattern BCPk may include a first warpage compensation pattern CP1ak, which has line portions CP1aka and CP1akb extending in the second direction D2, and a second warpage compensation pattern CP2bk, which has line portions extending in the second direction D2. The line portions CP1aka and CP1akb of the first warpage compensation pattern CP1akmay include first line portions CP1aka, which has a first width, and second line portions CP1akb, which has a second width narrower than the first width. The first line portions CP1aka may be disposed between the second line portions CP1akb. A length of at least one of the first line portions CP1aka may be longer than a length of at least one of the second line portions CP1akb.

According to an example embodiment of the present inventive concept, referring toFIG.14, a warpage compensation pattern BCPl may include a first warpage compensation pattern CP1al, which has line portions CP1alaand CP1albextending in the second direction D2, and a second warpage compensation pattern CP2bl, which has line portions extending in the second direction D2. The line portions CP1alaand CP1albof the first warpage compensation pattern CP1almay include first line portions CP1ala, which has a first width, and second line portions CP1alb, which has a second width narrower than the first width. The first line portions CP1alamay be disposed between the second line portions CP1alb. A length of at least one of the first line portions CP1alamay be shorter than a length of at least one of the second line portions CP1alb.

Among the warpage compensation patterns BCP formed according to the example embodiments described above with reference toFIGS.1A to14, a warpage compensation pattern according to some example embodiments of the present inventive concept may include line portions having the same width as each other or line portions having different widths from each other. Among the warpage compensation patterns BCP formed according to the example embodiments described above with reference toFIGS.1A to14, at least one of line portions of the warpage compensation pattern according to some example embodiments may have regions having different widths from each other. Thus, the warpage compensation pattern BCP formed according to the example embodiments described above with reference toFIGS.1A to14may include line portions having the same width as each other, line portions having different widths from each other, or line portions having different width regions from each other.

The warpage compensation pattern BCP formed according to the example

embodiments described above with reference toFIGS.1A to14may have substantially the same thickness as each other, but the example embodiments of the present inventive concept are not limited thereto. Hereinafter, with reference toFIGS.15,16,17,18, and19, various thickness modifications of the warpage compensation pattern BCP formed according to the example embodiments described above with reference toFIGS.1A to14will be described.FIGS.15,16,17,18and19are cross-sectional views illustrating a semiconductor wafer including the warpage compensation pattern BCP.

According to an example embodiment of the present inventive concept, referring toFIG.15, the first and second warpage compensation patterns BCPa1and BCPa2, formed on the back side BS of the semiconductor wafer WFa described with reference toFIG.3, may be modified into first and second warpage compensation patterns BCPt1dand BCPt2d, illustrated in

FIG.15. Each of the first and second warpage compensation patterns BCPt1dand BCPt2dmay have a linear shape extending in the direction of D1. At least one of the first and second warpage compensation patterns BCPt1dand BCPt2dmay include portions having different thicknesses from each other.

The first warpage compensation pattern BCPt1dmay include a first thickness portion Ta, a second thickness portion Tb, and a third thickness portion Tc, sequentially arranged in the direction of D1. The first thickness portion Ta may be larger than the second thickness portion Tb, and the second thickness portion Tb may be larger than the third thickness portion Tc. The second warpage compensation pattern BCPt2dmay include a first thickness portion Ta′, a second thickness portion Tb′, and a third thickness portion Tc′, sequentially arranged in the direction of D1. The first thickness portion Ta′ may be larger than the second thickness portion Tb′, and the second thickness portion Tb′ may be larger than the third thickness portion Tc′. Accordingly, a semiconductor wafer WFd, including the first and second warpage compensation patterns BCPt1dand BCPt2d, may be provided.

According to an example embodiment of the present inventive concept, referring toFIG.16, the first and second warpage compensation patterns BCPa1and BCPa2, formed on the back side BS of the semiconductor wafer WFa described with reference toFIG.3, may be modified into first and second warpage compensation patterns BCPt1eand BCPt2e, illustrated inFIG.16. Each of the first and second warpage compensation patterns BCPt1eand BCPt2emay have a linear shape extending in the direction of D1. The first warpage compensation pattern BCPt1emay include a third thickness portion Tc, a second thickness portion Tb, and a first thickness portion Ta, sequentially arranged in the direction of D1. The first thickness portion Ta may be greater than the second thickness portion Tb, and the second thickness portion Tb may be greater than the third thickness portion Tc. The second warpage compensation pattern BCPt2emay include a third thickness portion Tc′, a second thickness portion Tb′, and a first thickness portion Ta′, sequentially arranged in the direction of D1. The first thickness portion Ta′ may be larger than the second thickness portion Tb′, and the second thickness portion Tb′ may be larger than the third thickness portion Tc′. Accordingly, a semiconductor wafer WFde, including the first and second warpage compensation patterns BCPt1eand BCPt2e, may be provided.

According to an example embodiment of the present inventive concept, referring toFIG.17, the first and second warpage compensation patterns BCPa1and BCPa2, formed on the back side BS of the semiconductor wafer WFa described with reference toFIG.3, may be modified into first and second warpage compensation patterns BCPt1fand BCPt2f, illustrated inFIG.17. Each of the first and second warpage compensation patterns BCPt1fand BCPt2fmay include portions spaced apart from each other in the direction of DI. Accordingly, a semiconductor wafer WFf, including the first and second warpage compensation patterns BCPt1fand BCPt2f, may be provided.

According to an example embodiment of the present inventive concept, referring toFIG.18, the first and second warpage compensation patterns BCPa1and BCPa2, described with reference toFIG.17, may be modified into first and second warpage compensation patterns BCPt1gand BCPt2g, illustrated inFIG.18. In each of the first and second warpage compensation patterns BCPt1gand BCPt2g, at least some of portions, spaced apart from each other in the direction of D1, may have different thicknesses from each other. For example, in each of the first and second warpage compensation patterns BCPt1gand BCPt2g, portions, which are spaced apart from each other in the direction of D1, may have smaller thickness in a region close to the central region WF_C, and may have a larger thickness in a region far away from the central region WF_C. For example, the portions of the first and second warpage compensation patterns BCPt1gand BCPt2gthat are closest to the central region WF_C have a thickness that is smaller than the thickness of the portions of the first and second warpage compensation patterns BCPt1gand BCPt2gthat are farthest from the central region WF_C. For example, the thicknesses of the portions of the first and second warpage compensation patterns BCPt1gand BCPt2gmay decrease as the central region WF_C is approached. Accordingly, a semiconductor wafer WFg, including the first and second warpage compensation patterns BCPt1gand BCPt2g, may be provided.

According to an example embodiment of the present inventive concept, referring toFIG.19, the first and second warpage compensation patterns BCPa1and BCPa2, described with reference toFIG.17, may be modified into first and second warpage compensation patterns BCPt1hand BCPt2h, illustrated inFIG.19. In each of the first and second warpage compensation patterns BCPt1hand BCPt2h, portions, spaced apart from each other in the direction of D1, have a larger thickness in a region close to the central region WF_C, and may have a smaller thickness in a region far away from the central region WF_C. For example, each of the first and second warpage compensation patterns BCPt1hand BCPt2hmay include first thickness portions Ta and Ta′, second thickness portions Tb and Tb′, and the third thickness portions Tc and Tc′, sequentially arranged in the direction of D1. The third thickness portions Tc and Tc′ may be thicker than the second thickness portions Tb and Tb′, and the second thickness portions Tb and Tb′ may be thicker than the first thickness portions Ta and Ta′.

A semiconductor wafer WF, according to an example embodiment of the present inventive concept, before forming the various types of warpage compensation patterns BCP described above with reference toFIGS.3to20will be described with reference toFIG.20.FIG.20is a schematic cross-sectional view illustrating a cross-sectional structure of a semiconductor wafer according to an example embodiment of the present inventive concept.

Referring toFIG.20, a semiconductor wafer WFi may include the substrate SUB and the integrated circuit region ICR on the substrate SUB, which may substantially the same as those described above with reference toFIG.3.

The semiconductor wafer WFi may further include a back side reinforcement pattern CP_L below the substrate SUB.

The back side reinforcement pattern CP_L may be formed of an insulating material. For example, the back side reinforcement pattern CP_L may be formed of silicon oxide. For example, the back side reinforcement pattern CP_L may include tetraethoxysilane oxide (TEOS). The back side reinforcement pattern CP_L may have grooves CP_Lo. The grooves CP_Lo may be opening in a downward direction. A back side BS of the semiconductor wafer WFi may be a lower surface of the back side reinforcement pattern CP_L.

The semiconductor wafer WFi may be a semiconductor wafer before the warpage compensation pattern is formed thereon. For example, the semiconductor wafer WFi may be a semiconductor wafer in a state in which the first semiconductor process in operation S10described with reference toFIG.1Ais performed.

Next, an example in which the warpage compensation pattern BCP described above is formed on the semiconductor wafer WFi inFIG.20will be described with reference to each ofFIGS.21and22.FIG.21is a cross-sectional view illustrating a semiconductor wafer WFj obtained by forming, on the semiconductor wafer WFi inFIG.20, the warpage compensation pattern BCP, which has a linear shape extending in the direction of D1, among the above-described example embodiments.FIG.22is a cross-sectional view illustrating a semiconductor wafer WFk obtained by forming, on the semiconductor wafer WFi inFIG.20, the warpage compensation pattern BCP, which includes portions spaced apart from each other in the direction of D1, among the above-described example embodiments.

In an example, referring toFIGS.20and21, the semiconductor wafer WFj may be formed on the back side BS of the semiconductor wafer WFi inFIG.20, and may include a warpage compensation pattern BCP, having a linear shape extending in the direction of D1, among the above-described example embodiments.

The warpage compensation pattern BCP may include first and second warpage compensation patterns BCPt1jand BCPt2jrespectively extending in the direction of D1. At least a portion of the first and second warpage compensation patterns BCPt1jand BCPt2jmay cover the lower surface of the back side reinforcement pattern CP_L while filling at least a portion of the grooves CP_Lo of the back side reinforcement pattern CP_L.

In an example, referring toFIGS.20and22, the semiconductor wafer WFk may be formed on the back side BS of the semiconductor wafer WFi inFIG.20, and may include a warpage compensation pattern BCP, having portions spaced apart from each other in the direction of D1, among the above-described example embodiments. The warpage compensation pattern BCP may include first and second warpage compensation patterns BCPt1kand BCPt2k, which respectively include portions spaced apart from each other in the direction of D1. At least a portion of the first and second warpage compensation patterns BCPt1kand BCPt2kmay cover the lower surface of the back side reinforcement pattern CP_L while filling at least a portion of the grooves CP_Lo of the back side reinforcement pattern CP_L.

A method of manufacturing a semiconductor device using a semiconductor wafer including the warpage compensation pattern BCP described above, and a semiconductor device manufactured by the method will be described with reference toFIGS.23,24, and25.FIG.23is a process flowchart illustrating a method of manufacturing a semiconductor device using a semiconductor wafer including the warpage compensation pattern BCP described above, according to an example embodiment of the present inventive concept.FIG.24is a schematic perspective view illustrating a semiconductor device manufactured by a method of manufacturing a semiconductor device using a semiconductor wafer including the warpage compensation pattern BCP, according to an example embodiment of the present inventive concept.FIG.25is a schematic partially enlarged cross-sectional view illustrating a bonding region between a lower semiconductor chip and an upper semiconductor chip of the semiconductor device ofFIG.24, according to an example embodiment of the present inventive concept.

Referring toFIGS.23,24, and25, a first semiconductor wafer, having a warpage compensation pattern, may be formed (S110). The warpage compensation pattern may be a warpage compensation pattern BCP according to one of the above-described example embodiments. For example, the first semiconductor wafer may be the semiconductor wafer (WFa inFIG.3) illustrated inFIG.3or the semiconductor wafer WFk illustrated inFIG.22, but the example embodiments of the present inventive concept are not limited thereto. The first semiconductor wafer may be a memory semiconductor wafer including memory cell array regions MCA. Each of the memory cell array regions MCA may include three-dimensionally arranged memory cells.

A second semiconductor wafer may be formed (S120). The second semiconductor wafer may be, for example, a logic semiconductor wafer including a peripheral circuit region PC.

In an example, the second semiconductor wafer may include the warpage compensation pattern BCP according to one of the above-described example embodiments.

In an example, the second semiconductor wafer might not include the warpage compensation pattern BCP according to one of the above-described example embodiments.

The first semiconductor wafer and the second semiconductor wafer may be bonded to each other (S130). Bonding the first semiconductor wafer and the second semiconductor wafer to each other may include performing an inter-metal bonding process.

A semiconductor package may be formed by performing a packaging process (S140). The packaging process may include a back grinding process of reducing a thickness of each of the first and second semiconductor wafers that are bonded to each other and a cutting process of separating the first and second semiconductor wafers that are bonded to each other into a plurality of semiconductor chips. During the packaging process, the warpage compensation pattern BCP may be removed. The plurality of semiconductor chips may be formed into a semiconductor package. Thus, the semiconductor device100, in the form of a semiconductor package, may be formed.

The semiconductor device100may include a lower semiconductor chip150and an upper semiconductor chip110that is disposed on the lower semiconductor chip150. The upper semiconductor chip110may include a plurality of memory cell array regions MCA. The memory cell array regions MCA may be the memory cell array regions MCA inFIG.3. The memory cell array regions MCA may include three-dimensionally arranged memory cells.

The lower semiconductor chip150may include a peripheral circuit region PC capable of operating the memory cell array regions MCA. For example, the peripheral circuit region PC may be used to operate the memory cell array regions MCA.

In a bonding region between the lower semiconductor chip150and the upper semiconductor chip110, the lower semiconductor chip150may include a lower bonding pad155, a lower connection via160disposed below the lower bonding pad155, a lower interconnection structure165disposed below the lower connection via160, and a lower insulating structure170covering the lower bonding pad155, the lower connection via160, and the lower interconnection structure165. An upper surface of the lower insulating structure170may be substantially coplanar with an upper surface of the lower bonding pad155.

In a bonding region between the lower semiconductor chip150and the upper semiconductor chip110, the upper semiconductor chip110may include an upper bonding pad115, an upper connection via1120disposed on the upper bonding pad115, an upper interconnection structure125disposed on the upper connection via120, and an upper insulating structure130covering the upper bonding pad115, the upper connection via120, and the upper interconnection structure125. A lower surface of the upper insulating structure130may be substantially coplanar with a lower surface of the upper bonding pad115.

The upper insulating structure130and the lower insulating structure170may be bonded to each other while being in contact with each other. The upper bonding pad115and the lower bonding pad155may be bonded to each other while being in contact with each other. The upper bonding pad115and the lower bonding pad155may include the same metal material as each other, for example, copper (Cu).

In an example embodiment of the present inventive concept, in an operation (S130) of bonding the first semiconductor wafer and the second semiconductor wafer to each other, the first semiconductor wafer including three-dimensionally arranged memory cells may be a semiconductor wafer having warpage reduced by the warpage compensation pattern BCP, such that the upper bonding pad115and the lower bonding pad155may be bonded to each other without defects.

According to some example embodiments of the present inventive concept, a method of forming a warpage compensation pattern on a back side of a semiconductor wafer while measuring warpage of the semiconductor wafer may be provided. The warpage compensation pattern may be formed by spraying a warpage compensation material onto the back side of the semiconductor wafer in a liquid phase. The warpage compensation pattern may be formed on at least a portion of the back side of the semiconductor wafer.

According to some example embodiments of the present inventive concept, to form the warpage compensation pattern on the back side of the semiconductor wafer, a semiconductor processing apparatus, including a spraying apparatus spraying a warpage spraying material in a liquid phase, a warpage measuring apparatus measuring warpage of the semiconductor wafer, and a controller, may be provided.

The warpage compensation pattern, formed by the semiconductor processing apparatus and the method using the semiconductor processing apparatus, may reduce warpage of the semiconductor wafer, thereby reducing defects in a semiconductor process.