Multiplexer for SDFQ having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same

A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

BACKGROUND

The integrated circuit (IC) industry produces a variety of analog and digital semiconductor devices to address issues in different areas. Developments in semiconductor process technology nodes have progressively reduced component sizes and tightened spacing resulting in progressively increased transistor density. ICs progressively become smaller.

Flip-flops (latches) are used as data storage elements. In some circumstances, a flip-flop stores a single bit (binary digit) of data. In some circumstances, a flip-flop (latch) is used for storage of a state and represents a basic storage element of sequential logic in electronics, e.g., shift registers.

One type of flip-flop is a delay (D) flip-flop (FF). A D FF is a digital electronic circuit that delays the change of state of its output signal (Q) until the next rising or falling edge of a clock timing input signal occurs. The D FF is a modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R inputs from being at the same logic level.

A type of D FF is a scan D FF (SDFQ) which is used, e.g., to implement design for testing (DFT). An SDFQ is a D flip-flop that includes a multiplexer to controllably select between an input D during normal operation and a scan input during scan/test operation. Scan flip-flops, e.g., SDFQs, are used for device testing.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus is otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are likewise interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from a library thereof and are used as components in a layout diagram representing a circuit.

In some embodiments, transistors of a scan group in a multiplexer of an SDFQ are configured to have two sizes, namely a smaller channel size for transistors in a scan group and a larger size for transistors in a data group. In terms of signal propagation delay, the scan group creates a choke (discussed below) as compared to the data group which is discriminating in the effect upon operation of the multiplexer. In particular, the smaller channel size of the sized transistors in the scan group creates a choke which achieves relatively slower signal propagation through the scan group during scan/test operation as compared to signal propagation through the data group during non-scan/test operation, and thus avoids a race condition (discussed below).

In some embodiments, a semiconductor device includes a cell region including active regions (ARs) that extend in a first direction (e.g., parallel to the X-axis) and have components of corresponding transistors formed therein. A first subregion of the cell region includes a first active region in which are formed components of first positive-channel metal oxide semiconductor (PMOS) transistors and a second active region in which are formed components of first negative-channel metal oxide semiconductor (NMOS) transistors. Transistors having components of each of the first and second active regions have a first channel configuration with a first channel size. A second subregion in the cell region includes a third active region in which are formed components of second PMOS transistors and a fourth active region in which are formed components of second NMOS transistors. Transistors based in each of the third active regions and the fourth active regions have a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

The transistors of the cell region are arranged to function as an active circuit, e.g., a scan insertion D flip-flop (SDFQ). The SDFQ includes a multiplexer and a D flip-flop. In some embodiments, the SDFQ is connected to combinational logic. During normal operation, i.e., during non-scan/test operation, the multiplexer selects a data input signal that is generated by the combinational logic. During scan/test operation, however, the multiplexer selects a scan input signal. The multiplexer includes transistors arranged in a data group that select the data input signal and transistors arranged in a scan group that select the scan input signal. The transistors in the data group have components formed in the first and second active regions and so have the first channel configuration, i.e., have the larger channel size. The transistors in the scan group have components formed in the third and fourth active regions and so have the second channel configuration, i.e., have the smaller channel size. As a result, the signal propagation delay of the transistors in the scan group is increased when compared to the signal propagation delay of the transistors in the data group. In terms of when a signal reaches an internal node common to the transistors of the scan group and the data group, the increase in the propagation delay of the transistors in the scan group during test/scan operation emulates the propagation delay of the combinational logic plus the propagation delay of the transistors in the data group during non-test/scan operation, which avoids a race condition (discussed below).

In some embodiments, configuring the transistors of the scan group to have the smaller channel size is referred to as configuring the scan group to be a choke (discussed below). According to another approach (discussed below), a counterpart SDFQ includes a counterpart multiplexer, the counterpart multiplexer including transistors that would be counterparts of the transistors in the scan group (counterpart scan transistors), transistors that would be counterparts of the transistors in the data group (counterpart data transistors), and transistors that would be counterparts of the transistors in the delay group (counterpart delay transistors). According to the other approach, all of the counterpart scan transistors and all of the counterpart data transistors are configured to have a larger channel size whereas all of the counterpart delay transistors are configured to have a smaller channel size, i.e., to be a choke. As such, the other approach creates a choke that indiscriminately affects operation of the multiplexer during both scan/test operation and during non-scan/test operation, and thus the other approach fails to avoid the race condition (discussed below). By contrast, configuring the transistors of the scan group to have the smaller channel size as in some embodiments of the present application creates a choke which is discriminating in the effect upon operation of the multiplexer, i.e., creates a choke which achieves relatively slower signal propagation through the scan group during scan/test operation as compared to signal propagation through the data group during non-scan/test operation, and thus avoids the race condition.

Relevant terminology includes the following. When data input to a sequential logic circuit, e.g., an SDFQ, changes state, propagation delay refers to a finite amount of time needed by the logic gates to perform the operations on changed input data. A condition of valid operation is that the interval between clock pulses must be long enough so that all the logic gates have time to respond to the changes in the input data and have their corresponding outputs settle to stable logic values before the next clock pulse occurs. In general, when the condition is met, the circuit is stable and reliable.

Setup time is the minimum time that a signal must be stable before the clock rising edge. When the setup time is too brief, there is a risk that a logical state of the signal will be misinterpreted. More particularly, when the setup time is too brief, there is a risk that the signal will not settle into a first range of voltages which clearly represents a logical zero or a third range of voltages which clearly represents a logical one, but instead will remain in an intermediate second range of voltages which does not clearly represent either a logical zero or a logical one, resulting in the possibility of an incorrect interpretation of the logical state of the signal will be entered into a register, i.e., latched. Setup-slack is the difference in time between when the signal becomes valid and the setup time. In other words, when the setup-slack is positive, then the signal becomes valid sooner than required by the setup time. A setup-slack violation is a type of violation in which the setup-slack is negative such that the signal becomes valid after the point in time required by the setup time. In general, though a large positive setup-slack avoids signal-state misinterpretation, nevertheless a large positive setup-slack is undesirable because a significant portion of the large positive setup-slack represents delay that could be avoided. Accordingly, in general, the setup-slack is targeted for a near zero, positive number.

Hold time is the shortest time that a signal must be stable after the clock rising edge. When the hold time is not met, there is a risk that an incorrect interpretation of the logical state of the signal will be entered into a register, i.e., latched. Hold-slack is the difference in time between when the signal becomes valid and the hold time. In other words, when hold-slack is positive, then the signal remains valid longer than required by the hold time. A hold-slack violation is a type of slack violation in which the hold-slack is negative such that the signal remains valid too briefly, i.e., the signal remains valid for a shorter amount of time than is required by hold time. In general, though a large positive hold-slack avoids signal-state misinterpretation, nevertheless a large positive hold-slack is undesirable because a significant portion of the large positive hold-slack represents delay that could be avoided. Accordingly, in general, the hold-slack is targeted for a near zero, positive number.

FIG.1is a block diagram of semiconductor device100, in accordance with some embodiments.

Semiconductor device100is includes a semiconductor substrate101and active regions (ARs)124P,124N,126P,126N. Semiconductor device100further includes a cell region102. Cell region102includes active regions (ARs)124P,124N,126P,126N that extend in a first direction, e.g., parallel to the X-axis. InFIG.1, cell region102includes two subregions125L and125S. Within cell region102, subregions125L,125S are aligned with respect to the X-axis but are displaced relative to a second direction (e.g., parallel to the Y-axis) perpendicular to the first direction. Components of transistors, e.g., source/drain (S/D) regions and corresponding channels, or the like, are formed correspondingly in ARs124P,124N,126P,126N.

AR124P in subregion125L is doped with a first conductivity-type dopant such that the transistors corresponding to AR124P are field-effect transistors (FETs), and more particularly, positive-channel metal oxide semiconductor (PMOS) FETs (PFETs). The transistors corresponding to AR124P have a first channel configuration. In some embodiments, transistors corresponding to AR124P are planar transistors and the first channel configuration is defined by a first height relative to the Y-axis. In some embodiments, transistors corresponding to AR124P are fin-type field effect transistors (fin-FETs) and the first channel configuration is defined by a first number of fins, where the first number is X and X is a positive integer. In some fin-FET embodiments, a maximum height of AR124P or any AR, is proportional to a maximum number fins. In either case, the transistors in AR124P have a first channel configuration of a first channel size.

AR124N in subregion125L is doped with a second conductivity-type dopant such that the transistors corresponding to AR124N are negative-channel metal oxide semiconductor (NMOS) FETs (NFETs). The transistors corresponding to AR124N also have the first channel configuration. In some embodiments, transistors corresponding to AR124N are planar transistors and the first channel configuration is defined by the first height. In some embodiments, transistors corresponding to AR124N are fin-FETs and the first channel configuration is defined by the number X of fins. In either case, the transistors in AR124N have the first channel configuration of the first channel size.

AR126P in subregion125S is doped with the first conductivity-type dopant such that the transistors corresponding to AR126P are PMOS transistors. The transistors corresponding to AR126P have a second channel configuration. In some embodiments, transistors corresponding to AR126P are planar transistors and the second channel configuration is defined by a second height, wherein the second height is less than the first height. In some embodiments, transistors corresponding to AR126P are fin-FETs and the second channel configuration is defined by a second number of fins, where the second number is Y, Y is a positive integer, and Y<X. In either case, the transistors in AR126P have a second channel configuration of a second channel size. The second channel size is smaller than the first channel size.

AR126N in subregion125S is doped with the second conductivity-type dopant such that the transistors corresponding to AR126N are NMOS transistors. The transistors corresponding to AR126N also have the second channel configuration. In some embodiments, transistors corresponding to AR126N are planar transistors and the second channel configuration is defined by the second height. In some embodiments, transistors corresponding to AR126N are fin-FETs and the second channel configuration is defined by the number Y of fins. In either case, the transistors of AR126N have the second channel configuration of the second channel size.

InFIG.1, relative to the Y-axis, the size of ARs124P and124N included in subregion125L are larger than the sizes of ARs126P and126N included in subregion125S. Accordingly, in some embodiments and relative to the Y-axis, the suffix uppercase letter L in the reference number125L indicates relatively larger/taller ARs whereas the suffix uppercase letter S in reference number125S indicates relatively smaller/shorter ARs.

The transistors formed with ARs126P,126N have a smaller channel size and therefore a greater propagation delay. This allows scan transistors in a multiplexer to emulate the propagation delay of combinational logic, as explained in further detail below.

FIG.2Ais a block diagram of a semiconductor device200, in accordance with some embodiments.

Semiconductor device200includes a flip-flop FF1and a flip-flop FF2. Each of flip-flops FF1, FF2is a scan insertion D flip-flop (SDFQ). Each of flip-flops FF1, FF2includes a data terminal DT, and a scan input terminal SIT and an output signal terminal QT. Each of flip-flops FF1, FF2also includes a sense enable terminal SEI and a clock terminal CPI. Data input signals D1and D2are received correspondingly by flip-flops FF1, FF2at data terminal DT. A scan input signal SI is received by each of flip-flops FF1, FF2at scan input terminal SIT. A scan enable signal SE is received by each of flip-flops FF1, FF2at scan enable terminal SEI. A clock signal CLK is received by each of the flip-flops FF1, FF2at clock terminal CPI. Output signals Q1and Q2are generated correspondingly by flip-flops FF1, FF2at output signal terminal QT.

The operation of flip-flops FF1, FF2is coordinated by clock signal CLK. During normal, i.e., non-scan/test, operation, the scan enable signal SE is in a deactivated state so that scan input signal SI is not selected but rather data signal D is selected by flip-flops FF1, FF2. During an oscillation of clock signal CLK (assuming proper functioning of FF1), the bit value of data input signal D1at data terminal DT of flip-flop FF1is transferred from data terminal DT of flip-flop FF1to output terminal QT of flip-flop FF1as the bit value of output signal Q1. Also, output signal Q1of flip-flop FF1is received by combinational logic201as an input. Assuming proper functioning of combination logic201, the output of combination logic201is received by FF2as data input signal D2at data terminal DT of flip-flop FF2. By the end of the clock cycle (assuming proper functioning of FF2), output signal Q2at output terminal QT of flip-flop FF2corresponds to the output of combinational logic201.

However, during scan/test operation, scan enable signal SE is in an activated state so that scan input signal SI is selected and data signals D1and D2are ignored by corresponding flip-flops, FF1, FF2. During an oscillation of clock signal CLK (assuming proper functioning of FF1), the bit value of scan input signal SI at scan input terminal SIT of flip-flop FF1is transferred from scan input terminal SIT of flip-flop FF1to output terminal QT of flip-flop FF1as the bit value of output signal Q1. Also, output signal Q1of flip-flop FF1bypasses combinational logic201and is directly input into scan input terminal SIT of flip-flop FF2. By the end of the clock cycle (assuming proper functioning of FF2), output signal Q2of flip-flop FF2corresponds to scan input signal SI directly input from output terminal QT of flip-flop FF1.

InFIG.2A, if not taken into consideration, the bypassing of combinational logic201during scan/test operation otherwise is susceptible to a race condition (or race hazard) with respect to scan input signal SI of flip-flop FF2. More particularly, the synchronization of the bit values through flip-flops FF1, FF2is configured based on a propagation delay of combinational logic201. Because combinational logic201is bypassed during scan/test operation, there is a risk that the bit value of scan input signal SI reaches an internal node in flip-flop FF2too soon, i.e., is not held for a sufficient amount of time which represents a hold-time violation. To avoid the race condition, components within flip-flop FF2are configured to emulate the propagation delay otherwise introduced by combinational logic201during scan/test operation. SQFQ embodiments SDFQ disclosed herein are formed in a cell region, such as the cell region102shown inFIG.1, are configured to avoid the hold-time violation during scan/test operation (as discussed below).

FIG.2Bis a layout diagram of a cell region202, in accordance with some embodiments.

Cell region202is formed as part of a semiconductor substrate203. Semiconductor substrate203is an example of semiconductor substrate101inFIG.1. In some embodiments, cell region202ofFIG.2Bis an example of cell region102of semiconductor device100. Section lines3A-3A′ and3B-3B′ relate cell region202to the cross-sections of correspondingFIGS.3A-3B(discussed below).

In general, a layout diagram represents a semiconductor device. Shapes in the layout diagram represent corresponding components in the semiconductor device. The layout diagram per se is a top view. Shapes in the layout diagram are two-dimensional relative to, e.g., the X-axis and the Y-axis, whereas the semiconductor device being represented is three-dimensional. Typically, relative to the Z-axis, the semiconductor device is organized as a stack of layers in which are located corresponding structures, i.e., to which belong corresponding structures. Accordingly, each shape in the layout diagram represents, more particularly, a component in a corresponding layer of the corresponding semiconductor device. Typically, the layout diagram represents relative depth, i.e., position relative to the Z-axis, of shapes and thus layers by superimposing a second shape on a first shape so that the second shape at least partially overlaps the first shape. For simplicity of discussion, i.e., as a discussion-expedient, some elements in the layout diagram ofFIG.2Bare referred to as if they are counterpart structures in a corresponding semiconductor device rather than patterns/shapes per se.

Layout diagrams vary in terms of the amount of detail represented. In some circumstances, selected layers of a layout diagram are combined/abstracted into a single layer, e.g., for purposes of simplification. Alternatively, and/or additionally, in some circumstances, not all layers of the corresponding semiconductor device are represented, i.e., selected layers of the layout diagram are omitted, e.g., for simplicity of illustration.FIG.2Bis an example of a layout diagram in which selected layers have been omitted, as discussed below.

InFIG.2B, cell region202includes ARs224P,224N,226P,226N. ARs224P,224N,226P,226N are rectangular and have corresponding long axes that extend in the first direction, e.g., parallel to the X-axis. Corresponding short axes of ARs224P,224N,226P,226N extend in the second direction, e.g., parallel to the Y-axis. AR224P corresponds with AR124P inFIG.1. AR224N corresponds with AR124N inFIG.1. AR226P corresponds with AR126P inFIG.1. AR226N corresponds with AR126N inFIG.1.

InFIG.2B, relative to the Y-axis, a distance or size is alternately referred to as a height. A perimeter enclosing ARs224P,224N,226P,226N is rectangular; hence, cell region202is rectangular. Relative to the Y-axis, a height of cell region202is T2(discussed below). Relative to the X-axis, a width of cell region202is W1(discussed below).

Cell region202is separated into two subregions225L,225S. Subregion225L corresponds with subregion125L inFIG.1. Subregion225S corresponds with subregion125S inFIG.1. Subregion225L and subregion225S are aligned with respect to the X-axis but are displaced with respect to the Y-axis. Subregion225L and subregion225S are adjacent and abut one another along line M, which is parallel to the X-axis. InFIG.2B, a line M is the midline of cell region202with respect to the Y-axis. InFIG.2B, each of subregion225L and subregion225S has a height of T1. In some embodiments, line M is not the midline, and subregions225L and225S have different heights. Both subregion225L and subregion225S have a width of W1. Each of ARs224P,224N has a height of H1. Each of ARs226P,226N has a height of H2, where H1>H2. Heights H1and H2are determined by design rules of the corresponding semiconductor process technology node.

The boundaries of cell region202are defined by lines, a line L (i.e., left boundary L that is parallel to the Y-axis), a line R (i.e., right boundary R that is parallel to the Y-axis), a line T (i.e., top boundary T that is parallel to the X-axis), and a line B (i.e., bottom boundary B that is parallel to the X-axis). The boundaries of subregion225L are defined by the top boundary T and the midline M with respect to the Y-axis and the left boundary L and the right boundary R with respect to the X-axis. The boundaries of subregion225S are defined by the midline M and the bottom boundary B with respect to the Y-axis and the left bound L and the right boundary R with respect to the X-axis. The left edge of each of ARs224P,224N,226P,226N are aligned and are colinear with the left boundary L. The right edge of each of ARs224P,224N,226P,226N are aligned and are colinear with the right boundary R.

InFIG.2B, relative to the Y-axis, ARs224P,224N are spaced apart with a corresponding gap. In particular, a height of subregion225L includes: a gap G0between the top boundary T and the top edge of AR224P, where gap G0has a height H0; AR224P which has a height of H1; a gap G3between a bottom edge of AR224P and the top edge of AR224N, where gap G3has a height H3; AR224N which has a height of H1, and a gap G0′ between the bottom edge of AR224N and the midline M, where gap G0′ has a height of H0. InFIG.2B, the height of subregion225L is2H0+2H1+H3=T1.

InFIG.2B, relative to the Y-axis, ARs226P,226N are spaced apart with a corresponding gap. In particular, a height of subregion225S includes: a gap G5between the midline M and the top edge of AR226P, where gap G5has a height of H5; AR226P which has a height of H2; a gap G4between a bottom edge of AR226P and the top edge of AR226N, where gap G4has a height of H4; AR226N which has a height of H2; and a gap G5′between the bottom edge of AR226N and the bottom boundary B, where gap G5′ has a height of H5. InFIG.2B, the height of subregion225S is2H5+2H1+H4=T1.

InFIG.2B, each of heights of ARs224P,224N,226P,226N, and each of the gaps G0, G0′, G3, G5, G5′, G4adjacent to ARs224P,224N,226P,226N are determined according to design rules of the corresponding semiconductor process technology node. In some embodiments, other heights (whether symmetric or asymmetric) are used in subregions225L,225S.

In some embodiments, conductors (not explicitly shown) that have long axis that extend parallel to the X-axis are positioned in gaps G0, G0′, G3, G5, G5′, G4. Conductors are configured to receive reference voltages, such as VDD (e.g., power source voltage), VSS (e.g., ground). With regards to a conductor positioned in gaps G0′or G5that has a long axis parallel to the X-axis and a short axis parallel to the Y-axis, in some embodiments, midline of the short axis of such a conductor is aligned with the midline M. In some embodiments, the midline of the short axis of such a conductor is not aligned with the midline M so that a greater portion of the conductor is in subregion225S than in225L or vice versa.

InFIG.2B, cell region202is arranged into two rows that extend parallel to the X-axis, each row having a height T1. Height T2of cell region202is T2=2*T1. In some embodiments, a minimal height of a single-height cell (not shown) is T1. Accordingly, in such embodiments, cell region202is referred to as a double height cell because height T2is double the height of a single-height cell.

InFIG.2B, cell region202further includes gates209(not all of which are labeled for simplicity of illustration). Long axes of gates209extend parallel the Y-axis. Components of transistors, e.g., source/drain (S/D) regions and corresponding channels, or the like, are formed correspondingly in ARs224P,224N,226P,226N. Additional components of the transistors of cell region202include corresponding portions of gates209. In some embodiments, a given S/D region is formed by doping a given portion of an AR224P,224N,226P,226N that is between corresponding instances of gate209or that is adjacent to a corresponding instance of gate209, the given portion being doped with an appropriate conductivity-type dopant.

Cell region202further includes cut-gate (CG) shapes/patterns210. Long axes of cut patterns210extend substantially parallel to the X-axis. In general, where a given gate underlies a given CG shape such that a portion of the given gate is overlapped by the given CG shape, the given CG shape is used to indicate that the overlapped portion of the given gate will be removed during fabrication of a corresponding semiconductor device. A width between each of gates209is equal to a width W2.

In some embodiments, the transistors of cell region202are FETs. In some embodiments, ARs224P,226P are doped with a first conductivity-type dopant, and ARs224N,226N are doped with a second conductivity-type dopant.

RegardingFIG.2B, in some embodiments that are configured according to complementary metal oxide semiconductor (CMOS) technology, e.g.,FIGS.3A-3B,4B-4F,5B-5C, or the like, the following is true: ARs224P,226P are doped with a first conductivity-type dopant such that the transistors corresponding to ARs224P,226P are PFETs; ARs224N,226N are doped with a second conductivity-type dopant such that the transistors corresponding to ARs224N,226N are NFETs; and ARs224P,226P are formed in corresponding N-wells (seeFIGS.3A-3B).

In some embodiments, the transistors of cell region202have a fin-FET architecture (FIGS.3A-3B). In some embodiments, the transistors of cell region202have a planar-transistor architecture. In some embodiments, the transistors of cell region202have an architecture other than the fin-FET architecture or the planar-transistor architecture.

The channels of transistors in each of ARs224P,224N have a first channel-size. The first channel-size is proportional at least in part to height H1. The channels of transistors in each of ARs224P,224N have the first channel-size. In some embodiments which use the fin-FET architecture, the first channel-size is at least in part proportional to the number of fins intersected by a corresponding portion of a given one of gates209. In some embodiments, the number of fins in ARs224P,224N is a positive integer number X. The channels of transistors in each of ARs226P,226N have a second channel-size, where the second channel size is smaller than the first channel-size. The second channel-size is proportional at least in part to height H2. The channels of transistors in each of ARs226P,226N have the second channel-size. In some embodiments which use the fin-FET architecture, the second channel-size is at least in part proportional to the number of fins intersected by a corresponding portion of a given one of gates209. In some embodiments, the number of fins in ARs226P,226N is a positive integer number Y, where Y<X.

Transistors with the second channel-size have a greater propagation delay than the transistors with the first channel-size. In some embodiments, transistors with the second channel-size have a propagation delay that emulates the propagation delay of the combinational logic201in a processor stage.

InFIG.2B, the transistors of cell region202are arranged to function as an active circuit. In some embodiments, the active circuit is a scan insertion D flip-flop (SDFQ) (FIGS.4A,4B). The number of gates209shown inFIG.2B, and therefore the corresponding number of transistors, has been reduced for simplicity of illustration. As a practical matter, the active circuit defined by the transistors of cell region202determines the number of transistors to be included in cell region202, and thus the number of gates209to be included in cell region202.

InFIG.2B, one instance of gate209has been replaced by an insulating dummy gate (IDG)211. In some embodiments, an IDG is a dielectric structure that includes one or more dielectric materials and functions as an electrical isolation structure. Accordingly, an IDG is not a structure that is electrically conductive and thus does not function, e.g., as an active gate of a transistor. An IDG includes one or more dielectric materials and functions as an electrical isolation structure. In some embodiments, an IDG is based on a gate as a precursor. In some embodiments, a dummy gate includes a conductor, a gate-insulator layer, (optionally) one or more spacers, or the like. In some embodiments, an IDG is formed by first forming a gate, e.g., a dummy gate, sacrificing/removing (e.g., etching) the conductor of the gate to form a trench, (optionally) removing a portion of a substrate that previously had been under the conductor to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resultant electrical isolation structure, i.e., the IDG, are similar to the dimensions of the dummy gate which was sacrificed, or the combination of the gate which was sacrificed and the removed portion of the substrate. In some embodiments, an IDG is a dielectric feature that includes one or more dielectric materials (e.g., oxide, nitride, oxynitride, or other suitable materials), and functions as an isolation feature. In some embodiments, an IDG is a continuous polysilicon on oxide diffusion (OD) edge structure and is referred to as a CPODE structure.

FIGS.3A-3Bare corresponding cross sectional views of a cell region that is included in a semiconductor device, in accordance with some embodiments.

In particular,FIGS.3A-3Bare cross sectional views of a cell region202of a semiconductor device based on cell region202ofFIG.2Bin a circumstance of CMOS technology in which cell region202includes N-wells312(1) and312(2).FIGS.3A-3Bcorrespond to section lines3A-3A′ and3B-3B′ ofFIG.2B.FIG.3Acorresponds to a fin-FET architecture where X=3 and Y=2.FIG.3Bcorresponds to a fin-FET architecture where X=2 and Y=1. In other embodiments, X is greater than 3 and Y is greater than 2 as long as X>Y.

Each ofFIGS.3A-3Bincludes: a P-type substrate302; N-wells312(1) and312(2) formed in substrate302; P-type fins317formed partially in corresponding N-wells312(1)-312(2) relative to the Z-axis; N-type fins318formed partially in substrate302relative to the Z-axis; fin-insulator319formed against fins317and318; and a gate insulating layer320formed on fins317and318, and on exposed upper surfaces of N-wells312(1)-312(2), fin-insulator319and substrate302; and gate309. H1is greater inFIG.3Athan H1inFIG.3B. H2is greater inFIG.3Athan H2inFIG.3B.

In some embodiments, P-type substrate302includes silicon, silicon germanium (SiGe), gallium arsenic, or other suitable semiconductor materials. ARs224P,224N,226P,226N are formed in or over P-type substrate302, using one or more masks corresponding to one or more active regions in the layout diagrams described herein. The gate insulating layer320is deposited over P-type substrate302. Example materials of the gate insulating layer320include, but are not limited to, a high-k dielectric layer, an interfacial layer, and/or combinations thereof. In some embodiments, the gate dielectric material layer is deposited over the substrate by atomic layer deposition (ALD) or other suitable techniques. A gate electrode layer is deposited over the gate dielectric material layer. Example materials of the gate electrode layer include, but are not limited to, polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and/or other suitable conductive materials.

InFIG.3AandFIG.3B, in subregion225L, fins318are the left-most fins with respect to the Y-axis, and fins317are to the right of fins318. InFIG.3AandFIG.3B, in subregion225S, fins318are the left-most fins with respect to the Y-axis, and fins317are to the right of fins318. In other embodiments, fins317are the left most fins with respect to the Y-axis in subregion225L. In some embodiments, in each of subregions225L and225S, fins317are to the left of fins318.

FIG.4Ais a schematic circuit diagram, in accordance with some embodiments.

More particularly,FIG.4Ais a schematic circuit diagram of a scan D FF (SDFQ)430. SDFQ430is an example of how the transistors ofFIGS.1,2,3A-3Bor the like are arranged to function as an active circuit.

FIG.4Ais a transmission-gate-based design (discussed below). SDFQ430is an edge-triggered arrangement that is triggered on a rising edge (positive edge) of a clock signal. Variations of SDFQ430are triggered on the falling edge (negative edge) of the clock signal. Other variations of SDFQ430are double edge-triggered, i.e., are trigged by both the rising edge (positive edge) and falling edge (negative edge) of the clock signal.

InFIG.4A, SDFQ430includes a multiplexer432, a D flip-flop434, a scan buffer444and a clock buffer446.

InFIG.4A, scan buffer444receives a Scan/Test Enable (SE) signal that selects between normal, i.e., non-scan/test, operation relative to data signal D or scan/test operation relative to a Scan Input (SI) signal. Scan buffer444includes a non-sleepy (NS) inverter450(4), the latter including series-connected PFET P41and NFET N41. An NS inverter, e.g.,450(4) is a counterpart to a sleepy inverter, e.g.,448(1) (discussed below). Hereinafter, transistors whose reference alphanumeric is prefixed with the uppercase letter P, e.g., P41, are PFETs, and transistors whose reference alphanumeric is prefixed with the uppercase letter N, e.g., N41, are NFETs.

In NS inverter450(4), transistor P41is connected between a node having a first reference voltage, e.g., VDD, and a node nd41. Transistor N41is connected between node nd41and a node having a second reference voltage, e.g., VSS. The gate terminals of each of transistors P41and N41are connected together and are configured to receive signal SE. Node nd41has a signal seb which is the inversion of signal SE.

InFIG.4A, clock buffer446includes a pair of NS inverters450(5) and450(6). NS inverter450(5) includes series-connected transistors P31and N31. Transistor P31is connected between a node having voltage VDD and a node nd31. Transistor N31is connected between node nd31and a node having voltage VSS. The gate terminals of each of transistors P31and N31are connected together and are configured to receive a clock signal CP. Node nd31represents an output node of NS inverter450(5) and has a clock signal clkb which represents the inversion of clock signal CP.

In clock buffer446, NS inverter450(6) includes series-connected transistors P32and N32. Transistor P32is connected between a node having voltage VDD and a node nd32. Transistor N32is connected between node nd32and a node having voltage VSS. The gate terminals of each of transistors P32and N32are connected together and to node nd31, and thus are configured to receive clock signal clkb. Node nd32represents an output node of NS inverter450(6) and has a clock signal clkbb which represents the inversion of clock signal clkb.

InFIG.4A, multiplexer432includes transistors P11-P15and N11-N15. Transistor P11is connected between a node having voltage VDD and a node nd11. The gate terminal of transistor P11receives signal SI. Transistor P12is connected between node nd11and a node nd13. The gate terminal of transistor P12receives signal seb. Transistor P13is connected between a node having voltage VDD and a node nd12. The gate terminal of transistor P13receives input signal D. Transistor P14is connected between node nd12and node nd13. The gate terminal of transistor P14receives signal SE. Transistor P15is connected between node nd13and a node nd14which has signal m1_ax. The gate terminal of transistor P15receives signal clkbb. Transistor N11is connected between node nd14and a node nd15. The gate terminal of transistor N11receives signal clkb. Transistor N12is connected between node nd15and a node nd16. The gate terminal of transistor N12receives signal SE. Transistor N13is connected between node nd16and a node having voltage VSS. The gate terminal of transistor N13receives signal SI. Transistor N14is connected between node nd15and a node nd17. The gate terminal of transistor N14receives signal seb. Transistor N15is connected between node nd17and a node having voltage VSS. The gate terminal of transistor N15receives input signal D.

In multiplexer432, transistors P11, P12, N12, N13define a group of scan transistors SC1(scan group SC1) of multiplexer432. Scan group SC1is used for selecting the data input signal D. In some embodiments, components of transistors P11, P12are in AR126P ofFIG.1, AR226P ofFIGS.2B and3A-3B, or the like. In some embodiments, components of transistors N12, N13are in AR126N ofFIG.1, AR226N ofFIGS.2B and3A-3B, or the like.

Transistors P13, P14, N14, N15define a group of data transistors DAT1(data group DAT1) of multiplexer432. Data group DAT1is used for selecting the scan input signal SI. In some embodiments, components of transistors P13, P14are in AR124P ofFIG.1, AR224P ofFIGS.2B and3A-3B, or the like. In some embodiments, components of transistors N14, N15are in AR124N ofFIG.1, AR224N ofFIGS.2B and3A-3B, or the like.

Transistors P15, N11define a group of delay transistors DEL1(delay group DEL1) of multiplexer432. Delay group DEL1is used for delaying the propagation of the selected input, namely either SI or D, through multiplexer432. In some embodiments, transistor P15is formed with AR124P ofFIG.1, AR224P ofFIGS.2B and3A-3B, or the like. In some embodiments, transistor N11is formed with AR124N ofFIG.1, AR224N ofFIGS.2B and3A-3B, or the like.

Because the transistors of scan group SC1of multiplexer432are formed in ARs126P,226P with the smaller channel size as compared to the transistors of data group DAT1, the scan transistors of scan group SC1have a greater propagation delay as compared to the transistors of data group DAT1. In terms of when a signal reaches internal node nd14, the greater propagation delay of the transistors of scan group SC1is similar or equal to the propagation delay of combinational logic201(FIG.2A) plus the propagation delay of the transistors in delay group DAT1.

InFIG.4A, D flip-flop434includes a primary latch436, an internal buffer441, a secondary latch438and an output buffer442.

Primary latch436includes an NS inverter450(1) and a sleepy inverter448(1). NS inverter450(1) includes transistors P21and N21. Transistor P21is connected between a node having voltage VDD and a node nd21. Transistor N21is located node nd21and a node having voltage VSS. The gate terminals of transistors P21and N21are connected together and to node nd14, and thus are configured to receive signal m1_ax. As such, signal m1_axrepresents the input signal of D flip-flop434. Node nd21represents an output node of NS inverter450(1) and has a signal m1_bwhich represents the inversion of signal m1_ax.

In primary latch436, sleepy inverter448(1) includes transistors P22-P23and N22-N23. Transistor P22is connected between a node having voltage VDD and a node nd22. Transistor P23is connected between node nd22and node nd14. The gate terminal of transistor P23receives signal clkb. Transistor N22is connected between node nd14and a node nd23. The gate terminal of transistor N22receives signal clkbb. In some embodiments, the gate terminal of transistor N22receives signal CP instead of signal clkbb. Transistor N23is connected between node nd23and a node having voltage VSS. The gate terminal of transistor N22receives signal clkbb. Sleepy inverter448(1) can be put into a sleep mode due to transistors P23and N22. The gate terminals of transistors P22and N23are connected together and to node nd21. Accordingly, sleepy inverter448(1) feeds-back an inverted version of signal m1_b(from node nd21) to node nd14.

InFIG.4A, internal buffer441includes a transmission gate440, the latter including transistors P24and N24. The inclusion of transmission gate440in SDFQ430is referred to as a transmission-gate-based design. Transistors P24and N24are connected in parallel between node nd21and a node nd24. The gate terminal of transistor P24receives signal clkb. The gate terminal of transistor N24receives signal clkbb. Node nd24has a signal s1_a.

In D flip-flop434, secondary latch438includes an NS inverter450(2) and a sleepy inverter448(2). NS inverter450(2) includes transistors P25and N25. Transistor P25is connected between a node having voltage VDD and a node nd25. Transistor N25is connected between node nd25and a node having voltage VSS. The gate terminals of transistors P25and N25are connected together and to node nd24, and thus are configured to receive signal s1_a. Node nd25represents an output node of NS inverter450(2) and has a signal s1_bxwhich represents the inversion of signal s1_a.

In secondary latch438, sleepy inverter448(2) includes transistors P26-P27and N26-N27. Transistor P26is connected between a node having voltage VDD and a node nd26. Transistor P27is connected between node nd26and node nd24. The gate terminal of transistor P27receives signal clkbb. Transistor N26is connected between node nd24and a node nd27. Transistor N27is connected between node nd27and a node having voltage VSS. The gate terminal of transistor N26receives signal clkb. Sleepy inverter448(2) can be put into a sleep mode due to transistors P27and N26. The gate terminals of transistors P26and N27are connected together and to node nd25. Accordingly, sleepy inverter448(2) feeds-back an inverted version of signal s1_bx(from node nd25) to node nd24.

In D flip-flop434, output buffer442includes an NS inverter450(3), the latter including transistors P28and N28. Transistor P28is connected between a node having voltage VDD and a node nd26. Transistor N28is connected between node nd28and a node having voltage VSS. The gate terminals of transistors P28and N28are connected together and to node nd25, and thus are configured to receive signal s1_bx. Node nd26represents an output node of NS inverter450(3), and thus of D flip-flop434. Furthermore, node nd26also represents the output node of SDFQ400. Node464has signal Q which represents the inversion of signal s1_bx.

FIG.4Aassumes that SDFQ430is triggered on the rising edge (positive edge) of clock signal CP. Variations to make SDFQ430be triggered on the falling edge (negative edge) of a clock signal include the following. Instead of receiving clock signal CP, the gate terminals of each of transistors P31and N31are configured to receive a clock signal CPN, where CPN is an inverted version of clock signal CP. Instead of receiving signal clkbb, the gate terminal of transistor P15receives signal clkb. Instead of receiving signal clkb, the gate terminal of transistor N11receives signal clkbb. Instead of receiving signal clkb, the gate terminal of transistor P23receives signal clkbb. In some embodiments, the gate terminal of transistor P23receives signal CPN instead of signal clkbb. Instead of receiving signal clkbb, the gate terminal of transistor N22receives signal clkb. Instead of receiving signal clkb, the gate terminal of transistor P24receives signal clkbb. Instead of receiving signal clkbb, the gate terminal of transistor N24receives signal clkb. Instead of receiving signal clkbb, the gate terminal of transistor P27receives signal clkb. Instead of receiving signal clkb, the gate terminal of transistor N26receives signal clkbb.

InFIG.4A, D flip-flop434is a transmission-gate-based design because internal buffer441thereof includes transmission gate440. In some embodiments, D flip-flop434is a stack-gate-based design (not shown). More particularly, whereas internal buffer441ofFIG.4Aincludes transmission gate440, a stack-gate-based version of D flip-flop434includes a version of internal buffer441which is stack-gate-based. In some embodiments, the stack-gate-based version of internal buffer441includes a sleepy inverter (not shown) in place of transmission gate440, where a sleepy inverter is an example of a stack-gate-based device. Like transmission gate440, the output of the alternative sleepy inverter is connected to node nd24. In contrast to transmission gate440, the input of the alternative sleepy inverter is not connected to node nd21but instead is connected to node nd14.

FIGS.4B-4Fare corresponding layout diagrams402B-402F, in accordance with some embodiments.

Each of layout diagrams402B-402F is an example of layout diagram of cell region202ofFIG.2B.FIGS.4B-4Finclude different arrangements of the transistors of SDFQ430ofFIG.4Ain cell region202ofFIG.2B. Gates209and cut patterns210are not included inFIG.4B-4Ffor simplicity of illustration.

TABLE 1Component from FIG. 4ASection450(5) NS Inverter of Clock Buffer 446A450(6) NS Inverter of Clock Buffer 446B450(4) NS Inverter of 444 Scan BufferCDAT1 Data Transistors of 432 MultiplexerDSC1 Scan Transistors of 432 MultiplexerEDEL1 Delay Transistors of 432 MultiplexerF1448(1) Sleepy Inverter of Primary Latch 436F2450(1) NS Inverter of Primary LatchG440 Transmission Gate of 441 Internal BufferHA1448(2) Sleepy Inverter of 438 Secondary LatchHA2450(2) NS Inverter of 438 Secondary LatchI450(3) NS Inverter of 442 Output BufferJ

Also shown inFIG.4B-4Fare gapping sections. A gapping section does not include any of the PMOS or NMOS transistors of SDFQ430shown inFIG.4A. The gapping section includes 1) includes passive components of SDFQ430that are not shown in4A, 2) active or passive components of other semiconductor devices that are not part of SDFQ430, 3) dummy components, and/or 4) a spacing section with neither active, passive, or dummy components. Gapping sections are identified with the letter “X” followed by a number to specifically identify the gapping section. It should be noted that when a gapping section is between pair of any two of sections A, B, C, D, E, F1, F2, G, HA1HA2, I, J then the pair is considered adjacent to one another with respect to SDFQ430but is not abutting with respect to each other. Relative to the X-axis, gapping sections having different sizes/dimensions due to space-packing considerations which depend upon the sequence of sections in subregion225L and the sequence of sections in subregion225S.

In each ofFIGS.4B-4C, The PMOS transistors having components in sections A, C, D, F1, F2, G, and J of subregion225L are formed in AR224P.

The NMOS transistors having components in sections A, C, D, F1, F2, G, and J of subregion225L are formed in AR224N.

The PMOS transistors having components in sections B, E, HAL HA2, and I of subregion225S are formed in AR226P.

The NMOS transistors having components in sections B, E, HAL HA2, and I, of subregion225S are formed in AR226N.

InFIG.4B, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:A:X1:G:J. InFIG.4C, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:G:X1:A:J. InFIG.4C, sections A and G are reversed in position as compared to the positions of sections A and G inFIG.4B, i.e., G is positioned before A in the left to right sequence inFIG.4Cversus section A being positioned before G in the left-to-right sequence inFIG.4B. Accordingly, inFIG.4C, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:G:X1:A:J.

In each ofFIGS.4B-4C, the left-to-right sequence of the adjacent and abutting sections in subregion225S is E:HA2:HA1:X2:B:I:X3.

In each ofFIGS.4D-4E, section J is in subregion225S as compared to section J being in subregion225L in each ofFIGS.4B-4C.

Accordingly, the PMOS transistors having components in sections A, C, D, F1, F2, and G of subregion225L are formed in AR224P.

The NMOS transistors having components in sections A, C, D, F1, F2, and G of subregion225L are formed in AR224N.

The PMOS transistors having components in sections B, E, HAL HA2, I, and J of subregion225S are formed in AR226P.

The NMOS transistors having components in sections B, E, HAL HA2, I, and J of subregion225S are formed in AR226N.

InFIG.4D, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:A:X4:G:X5. InFIG.4E, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:G:X4:A:X5. InFIG.4D, sections A and G are reversed in position as compared to the positions of sections A and G inFIG.4E, i.e., A is positioned before G in the left to right sequence inFIG.4Dversus section G being positioned before A in the left-to-right sequence inFIG.4E. Accordingly, inFIG.4E, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:G:X4:A:X5.

In each ofFIGS.4D-4E, the left-to-right sequence of the adjacent and abutting sections in subregion225S is E:HA2:HA1:X6:B:J:I:X7.

InFIG.4F, the left-to-right sequence of the adjacent and abutting sections in subregion225L is C:D:F1:F2:G:X8:I:J:X9. InFIG.4F, the left-to-right sequence of adjacent and abutting sections in subregion225S is E:HA2:HA1:X10:B:A:X1. Thus, unlike the embodiments inFIGS.4B-4E, both sections I, J are in subregion225L ofFIG.4F. Also, unlike the embodiments inFIGS.4B-4E, section A is in subregion225S ofFIG.4F.

In some embodiments, subregions225L and subregion225S are configured as shown inFIG.3Awith respect to layout diagrams402B-402F ofFIGS.4B-4F. In some embodiments, subregions225L and subregion225S are configured as shown inFIG.3Bwith respect to layout diagrams402B-402F ofFIGS.4B-4F.

It is to be recalled thatFIGS.4B-4Fare example arrangements of the transistors of SDFQ434ofFIG.4A, where SDFQ434includes the transistors of scan group SC1, data group DAT1and delay group DEL1of multiplexer432, and that SDFQ434ofFIG.4Ais an example of FF2ofFIG.2A. According to another approach similar toFIG.2A, the counterpart to FF2ofFIG.2Ais an SDFQ that includes transistors having a larger channel size and transistors having a smaller channel size, and the SDFQ includes a multiplexer. Regarding the transistors in the multiplexer according to the other approach, all of the transistors that would be counterparts of the transistors in scan group SC1and data group DAT1have the larger channel size, and all of the transistors that would be counterparts of the transistors in delay group DEL1have the smaller channel size. Nevertheless, the other approach does not avoid the race condition. By contrast, some embodiments (e.g.,FIGS.4B-4F) of the present application advantageously avoid the race condition because the transistors of scan group SC1have the smaller channel size (as discussed above) whereas the transistors of data group DAT1have the larger channel size (as discussed above).

The race condition concerns the amount of time that a signal on node nd14is held valid. According to the other approach, the bypass of the combinational logic results in the hold time of the signal SI being shorter than the hold time of the signal D, i.e., the falling edge of the signal SI races ahead of the falling edge of the signal D (the latter during non-scan/test operation), which causes improper latching of the signal SI by the D FF during scan/test operation. By contrast, some embodiments (e.g.,FIGS.4B-4F) of the present application advantageously avoid the race condition because the transistors of scan group SC1have the smaller channel size (as discussed above) and thereby provide a choke whereas the transistors of data group DAT1have the larger channel size (as discussed above), with a result that the hold time of the signal SI during scan-test operation is substantially the same as the hold time of the signal D during non-scan/test operation, i.e., the falling edge of the signal SI during scan/test operation does not race ahead of the falling edge of the signal D during non-scan/test operation.

In other words, there is a minimum amount of time that the signal SI has to be held in order for primary latch436to validly input the bit value of the signal SI at node nd21. If the bit value of the signal SI is not held for the minimum amount of time, then the bit value of the signal SI is not registered at node nd21. By making the scan group SC1of transistors smaller, i.e., by creating a choke, a signal propagation delay is introduced which ensures that the bit value of the signal SI is held long enough at input node nd14for primary latch436to register the bit value of the signal SI at node nd21.

In some embodiments, configuring the transistors of scan group SC1to have the smaller channel size is referred to as configuring scan group SC1to be a choke. Here, the term choke is not being used in the traditional sense associated with inductors and the blocking/choking of higher frequency signals while passing lower frequency signals. Rather, here, the term choke is being used in manner more like the term choke (or choke valve) is used in the context of a carburetor in an internal combustion engine carburation, wherein the choke (when engaged) reduces the volume of air reaching the carburetor. More particularly, here, the term choke is being used in the sense of representing a relatively slower propagation path as compared to otherwise configuring the transistors of scan group SC1to having the larger channel size. As noted, the other approach configures all of the transistors in the multiplexer that would be counterparts of the transistors in delay group DEL1to have the smaller channel size, i.e., to be a choke. As such, the other approach creates a choke that indiscriminately affects operation of the multiplexer during both scan/test operation and during non-scan/test operation, and thus the other approach fails to avoid the race condition. By contrast, configuring the transistors of scan group SC1to have the smaller channel size as in some embodiments of the present application creates a choke which is discriminating in the effect upon operation of the multiplexer, i.e., creates a choke which achieves relatively slower propagation during scan/test operation than is achieved during non-scan/test operation, and thus avoids the race condition.

FIG.5Ais a schematic circuit diagram, in accordance with some embodiments.

More particularly,FIG.5Ais a schematic circuit diagram of an SDFQ530. SDFQ530is an example of how the transistors ofFIGS.1,2,3A-3Bor the like are arranged to function as an active circuit.

FIG.5Ais a transmission-gate-based design. SDFQ530is an edge-triggered arrangement that is triggered on a rising edge (positive edge) of a clock signal. Variations of SDFQ530are triggered on the falling edge (negative edge) of the clock signal. Other variations of SDFQ530are double edge-triggered, i.e., are trigged by both the rising edge (positive edge) and falling edge (negative edge) of the clock signal.

InFIG.5A, SDFQ530includes a multiplexer532, D flip-flop434, scan buffer444, clock buffer446. D flip-flop434, scan buffer444and clock buffer446are the same as in SDFQ430described above with respect toFIG.4AAccordingly, the discussion of D flip-flop434, scan buffer444and clock buffer446is not repeated for the sake of brevity. Rather, discussion of SDFQ530will focus on multiplexer532which is an alternative to multiplexer432ofFIG.4A.

InFIG.5A, multiplexer532includes transistors P51-P56and N51-N56. Transistor P51is connected between a node having voltage VDD and a node nd51. The gate terminal of transistor P51receives scan input signal SI. Transistor P52is connected between node nd51and a node nd53. The gate terminal of transistor P52receives signal seb. Transistor P53is connected between a node having voltage VDD and the node nd52. The gate terminal of transistor P53receives data input signal D. Transistor P54is connected between node nd52and node nd53. The gate terminal of transistor P54receives signal SE. Transistor P55is connected between a node having voltage VDD and the node nd56. Transistor P55has a gate terminal that is connected to node nd53. Transistor P56is connected between node nd56and internal node nd14, the latter having signal m1_ax. The gate terminal of transistor P15receives signal clkbb.

Transistor N51is connected between node nd53and a node nd54. The gate terminal of transistor N51receives signal SE. Transistor N52is connected between node nd54and a node having voltage VSS. The gate terminal of transistor N52receives signal SI. Transistor N53is connected between node nd53and a node nd55. The gate terminal of transistor N53receives signal seb. Transistor N54is connected between node nd55and a node having voltage VSS. The gate terminal of transistor N54receives data input signal D. Transistor N55is connected between internal node nd14and a node nd57. The gate terminal of transistor N55receives signal clkb. Transistor N56is connected between internal node nd57and a node having a voltage VSS. The gate terminal of transistors N56is connected to node nd53.

In multiplexer532, transistors P53, P54, N53, N54define a group of data transistors DAT2(data group DAT2) of multiplexer532. Data group DAT2is used for selecting the data input signal D. In some embodiments, components of transistors P53, P54are in AR124P ofFIG.1, AR224P ofFIGS.2Band3A-3B, or the like. In some embodiments, components of transistors N53, N54are in AR124N ofFIG.1, AR224N ofFIGS.2B and3A-3B, or the like.

Transistors P51, P52, N51, N52define a group of scan transistors SC2(scan group SC2) of multiplexer532. Scan group SC2is used for selecting the scan input signal SI. In some embodiments, components of transistors P51, P52are in AR126P ofFIG.1, AR226P ofFIGS.2B and3A-3B, or the like. In some embodiments, components of transistors N51, N52are in AR126N ofFIG.1, AR226N ofFIGS.2B and3A-3B, or the like.

Transistors P55, P56, N56, N55define a group of delay transistors DEL2(delay group DEL2) of multiplexer532. Delay group DEL2is used for delaying the propagation of the selected input, namely either SI or D, through multiplexer532. The transistors of delay group DEL2are configured as a sleepy inverter. In some embodiments, components of transistors P55, P56are in AR124P ofFIG.1, AR224P ofFIGS.2B and3A-3B, or the like. In some embodiments, components of transistors N55, N56are in AR124N ofFIG.1, AR224N ofFIGS.2B and3A-3B, or the like.

Because the transistors of scan group SC2of multiplexer532are formed in ARs126P,226P with the smaller channel size as compared to the transistors of data group DAT2, the transistors of scan group SC2have a greater propagation delay as compared to the transistors of delay group DAT2. In terms of when a signal reaches internal node nd14, the greater propagation delay of the transistors in scan group SC2is similar or equal to the propagation delay of combinational logic201(FIG.2A) plus the propagation delay the transistors in data group DAT2.

FIGS.5B-5Care corresponding layout diagrams502B-502C, in accordance with some embodiments.

Each of layout diagrams502B-502C is an example of layout diagram of cell region202ofFIG.2B.FIGS.5B-5Cinclude different arrangements of the transistors of SDFQ530ofFIG.5Ain cell region202ofFIG.2B. Gates209and cut patterns210are not included inFIG.5B-5Cfor simplicity of illustration.

TABLE 2Component from FIG. 5ASection450(5) NS Inverter of Clock Buffer 446A450(6) NS Inverter of Clock Buffer 446B450(4) NS Inverter of 444 Scan BufferCDAT2 Data Transistors of 532 MultiplexerDSC2 Scan Transistors of 532 MultiplexerEDEL2 Delay Transistors of 532 MultiplexerF1448(1) Sleepy Inverter of Primary Latch 436F2450(1) NS Inverter of Primary Latch 436G440 Transmission Gate of 441 Internal BufferHA1448(2) Sleepy Inverter of 438 Secondary LatchHA2450(2) NS Inverter of 438 Secondary LatchI450(3) NS Inverter of 442 Output BufferJ

Also shown inFIG.5B-5Care gapping sections. A gapping section does not include any of the PMOS or NMOS transistors of SDFQ530shown inFIG.5A. The gapping section includes 1) includes passive components of SDFQ530that are not shown in5A, 2) active or passive components of other semiconductor devices that are not part of SDFQ530, 3) dummy components, and/or 4) a spacing section with neither active, passive, or dummy components. Gapping sections are identified with the letter “X” followed by a number to specifically identify the gapping section. It should be noted that when a gapping section is between pair of any two of sections A, B, C, D, E, F1, F2, G, HAL HA2, I, J, then the pair is considered adjacent to one another with respect to the SDFQ530but is not abutting with respect to each other. Relative to the X-axis, gapping sections having different sizes/dimensions due to space-packing considerations which depend upon the sequence of sections in subregion225L and the sequence of sections in subregion225S.

In each ofFIGS.5B-5C, the PMOS transistors having components in sections A, C, D, F1, F2, and G of subregion225L are formed in AR224P.

The NMOS transistors having components in sections A, C, D, F1, F2, and G of subregion225L are formed in AR224N.

The PMOS transistors having components in sections B, E, HAL HA2, I, and J of subregion225S are formed in AR226P.

The NMOS transistors having components in sections B, E, HAL HA2, I, and J of subregion225S are formed in AR226N.

InFIG.5B, the left-to-right sequence of the adjacent and abutting sections in subregion225L is D:C:X20:G:F1:F2:A. InFIG.5B, the left-to-right sequence of adjacent and abutting sections in subregion225S is E:J:X21:LHA2:HA1:X22:B.

InFIG.5C, the left-to-right sequence of the adjacent and abutting sections in subregion225L is D:C:X20:A:F1:F2:G. InFIG.5C, the left-to-right sequence of adjacent and abutting sections in subregion225S is E:J:X21:B:HA2:HA1:X22:I. InFIG.5C, sections A and G of subregion225L are reversed in position as compared to the positions of sections A and G of subregion225L inFIG.5B, i.e., A is positioned before G in the left to right sequence inFIG.5Cversus section G being positioned before A inFIG.5B. InFIG.5C, sections B and I of subregion225S are reversed in position as compared to the positions of sections B and I of subregion225S inFIG.5B, i.e., B is positioned before I in the left to right sequence inFIG.5Cversus section I being positioned before B in the left to right sequence inFIG.5B.

In some embodiments, subregions225L and subregion225S are configured as shown inFIG.3Awith respect to layout diagrams502B-502C ofFIGS.5B-5C. In some embodiments, subregions225L and subregion225S are configured as shown inFIG.3Bwith respect to layout diagrams502B-502C ofFIGS.5B-5C.

It is to be recalled thatFIGS.5B-5Care example arrangements of the transistors of SDFQ534ofFIG.5A, where SDFQ534includes the transistors of scan group SC2, data group DAT2and delay group DEL2of multiplexer532, and that SDFQ534ofFIG.5Ais an example of FF2ofFIG.2A. According to another approach similar toFIG.2A, the counterpart to FF2ofFIG.2Ais an SDFQ that includes transistors having a larger channel size and transistors having a smaller channel size, and the SDFQ includes a multiplexer. Regarding the transistors in the multiplexer according to the other approach, all of the transistors that would be counterparts of the transistors in scan group SC2and data group DAT2have the larger channel size, and all of the transistors that would be counterparts of the transistors in delay group DEL2have the smaller channel size. Nevertheless, the other approach does not avoid the race condition. By contrast, some embodiments (e.g.,FIGS.5B-5C) of the present application advantageously avoid the race condition because the transistors of scan group SC2have the smaller channel size (as discussed above) whereas the transistors of data group DAT2have the larger channel size (as discussed above).

In some embodiments, configuring the transistors of scan group SC2to have the smaller channel size is referred to as configuring scan group SC2to be a choke, where use herein of the term choke is discussed above. As noted, the other approach configures all of the transistors in the multiplexer that would be counterparts of the transistors in delay group DEL2to have the smaller channel size, i.e., to be a choke. As such, the other approach creates a choke that indiscriminately affects operation of the multiplexer during both scan/test operation and during non-scan/test operation, and thus the other approach fails to avoid the race condition. By contrast, configuring the transistors of scan group SC2to have the smaller channel size as in some embodiments of the present application creates a choke which is discriminating in the effect upon operation of the multiplexer, i.e., creates a choke which achieves relatively slower propagation during scan/test operation than is achieved during non-scan/test operation, and thus avoids the race condition.

FIG.6Ais a flow diagram600A of a method of manufacturing a semiconductor device, in accordance with some embodiments.

The method of flowchart600A is implementable, for example, using EDA system700(FIG.7, discussed below) and an IC manufacturing system800(FIG.8, discussed below), in accordance with some embodiments. Examples of a semiconductor device which can be manufactured according to the method of flowchart600A include semiconductor devices ofFIGS.1,3A-3B,4A-4F and5A-5C, semiconductor device200inFIG.2A, semiconductor devices based on the layout diagram of cell region202ofFIG.2B, or the like.

InFIG.6A, the method of flowchart600A includes blocks602-604. At block602, a layout diagram is generated which, among other things, includes one or more of layout diagrams disclosed herein, or the like. Block602is implementable, for example, using EDA system700(FIG.7, discussed below), in accordance with some embodiments. From block602, flow proceeds to block604.

At block604, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (b) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated. See discussion below of IC manufacturing system800inFIG.8below.

FIG.6Bis a method600B of fabricating a semiconductor device, in accordance with some embodiments.

Method600B includes blocks606-614. Method600B is an example of block602inFIG.6A. InFIG.6B, flow begins at block606.

At block606, a substrate is formed. Examples of the substrate include substrates101inFIG.1,203inFIG.2B,302ofFIGS.3A-3B, or the like. From block606, flow then proceeds to block608.

At block608, active regions (ARs) are formed including doping corresponding areas of the substrate resulting in the ARs extending a first direction; a first subregion of the substrate including first and second ones of the active regions (first and second active regions); the first active region having a first conductivity-type dopant, the second active region having a second conductivity type dopant; each of the first and second active regions having a first height with respect to a second direction, the second direction being perpendicular to the first direction; a second subregion of the substrate including third and fourth ones of the active regions (third and fourth active regions); the third active region having the first conductivity-type dopant; the fourth active region having the second conductivity-type dopant; and each of the third and fourth active regions having a second height with respect to the second direction, the second height being smaller than the first height. Examples of active regions (ARs) in the cell region include ARs124P,124N,126P,126N inFIG.1, ARs224P,224N,226P,226N inFIG.2B, or the like. The ARs extend in a first direction. From block608, flow then proceeds to block610.

Regarding block608, an example of the first direction is a direction parallel to the X-axis, e.g., as inFIG.1andFIG.2B, or the like. Examples of the first subregion include125L inFIG.1,225LinFIGS.2B,3A-3B,4B-4E,5B-5C, or the like. Examples of the first and second active regions in the first subregion include ARs124P and124N in subregion125L inFIG.1, ARs224P and224N in subregion225L inFIG.2B, or the like. Examples of the first AR being doped with a first conductivity-type dopant include AR124P inFIG.1and AR224P inFIG.2B, each of which is doped with a P-type dopant according to PFET technology, or the like. Examples of the second AR being doped with a second conductivity type dopant include AR124N inFIG.1and AR224N inFIG.2B, each of which is doped with an N-type dopant according to NFET technology. An example of the first height with respect to the second direction (e.g., the Y-axis) for the first and second active regions is height H1inFIGS.2B,3A-3B, or the like.

Further regarding block608, a second subregion in the cell region includes the third and fourth active regions. Examples of the second subregion include125S inFIG.1,225SinFIGS.2B,3A-3B,4B-4E,5B-5C, or the like. Examples of the third and fourth active regions in the second subregion include ARs126P and126N in subregion125S inFIG.1, ARs226P and226N in subregion225S inFIG.2B, or the like. Examples of the third AR being doped with the first conductivity-type dopant include AR126P inFIG.1and AR226P inFIG.2B, each of which is doped with the P-type dopant according to PFET technology, or the like. Examples of the fourth AR being doped with the second conductivity type dopant include AR126N inFIG.1and AR226N inFIG.2B, each of which is doped with an N-type dopant according to NFET technology. An example of the second height with respect to the second direction (e.g., the Y-axis) for the third and fourth active regions is height H2inFIGS.2B,3A-3B, or the like. From block608, flow proceeds to block610.

At block610, source/drain (S/D) regions are formed in the ARs including doping corresponding first areas of the ARs, the S/D regions representing first transistor-components, the forming S/D regions resulting in: second areas of the active regions which are between the corresponding S/D regions are channel regions representing second transistor components; ones of channel regions in the first and second active regions having a first channel size; and ones of channel regions in the third and fourth active regions having a second channel size, the second channel size being smaller than first channel size.

Regarding block610, examples of S/D regions include portions of the ARs224P,224N,226P,226N to the left and right of gates209inFIG.2B, or the like. Examples of the channel regions include fins317,318inFIGS.3A-3B, or the like. The channel regions of the first active region and the second active region have a first channel size. Examples of the channel regions with the first channel size include fins317,318of224P,224N inFIGS.3A-3B, or the like. The channel regions of the third active region and the fourth ARs have a second channel size that is smaller than the first channel size. Examples of the channel regions with the second channel size include fins317,318of226P,226N inFIGS.3A-3B, or the like. From block610, flow then proceeds to block612.

At block612, gate lines are formed over corresponding channel regions, wherein the gate lines represent third transistor components. Examples of the gate lines include gates209inFIG.2B, or the like. From flow612, flow then proceeds to block614.

At block614, the forming of ARs, the forming of S/D regions, and the forming of gate lines result in transistors that are interconnectable to form a scan insertion D flip flop (SDFQ) which includes a multiplexer serially connected at an internal node to a D flip-flop (FF). A subset of ones of the transistors that define the multiplexer include: ones of transistors having first and second transistor-components which are in the first and second ARs and which represent data transistors for selecting a data input signal; and ones of transistors having first and second transistor-components which are in the third and fourth ARs and which represent scan transistors for selecting a scan input signal. Examples of the SDFQ include SDFQ430inFIG.4A, SDFQ530inFIG.5A, or the like. An example of the D FF is D FF434inFIGS.4A and5A, or the like. Examples of the internal node include internal node nd14inFIGS.4A, and5A, or the like. Examples of the multiplexer include multiplexer432inFIG.4A, multiplexer532inFIG.5A, or the like. Examples of the data transistors include the transistors in data group DAT1inFIG.4A, the transistors in data group DAT2inFIG.4B, or the like. Examples of the scan transistors include the transistors in scan group SC1inFIG.4A, the transistors scan group SC2inFIG.5A, or the like.

FIG.7is a block diagram of an electronic design automation (EDA) system700in accordance with some embodiments.

In some embodiments, EDA system700includes an APR system. In some embodiments, EDA system700is a general purpose computing device including a hardware processor702and a non-transitory, computer-readable storage medium704. Storage medium704, amongst other things, is encoded with, i.e., stores, computer program code706, i.e., a set of executable instructions. Execution of instructions706by hardware processor702represents (at least in part) an EDA tool which implements a portion or all of, e.g., the methods ofFIGS.6A,6B, and7, in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Storage medium704, amongst other things, stores layout diagram of cell region202inFIG.2B, layout diagrams402B-402F inFIGS.4B-4F, layout diagrams502B-502C inFIGS.5A-5B, and other layout diagrams of the like within the scope of the present disclosure.

Processor702is electrically coupled to computer-readable storage medium704via a bus708. Processor702is further electrically coupled to an I/O interface710by bus708. A network interface712is further electrically connected to processor702via bus708. Network interface712is connected to a network714, so that processor702and computer-readable storage medium704are capable of connecting to external elements via network714. Processor702is configured to execute computer program code706encoded in computer-readable storage medium704in order to cause system700to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor702is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, storage medium704stores computer program code706configured to cause system700(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium704further stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium704stores library720of standard cells including such standard cells as disclosed herein, one or more circuit diagrams709including such circuit diagrams as disclosed herein, and one or more layout diagrams711including such layout diagrams as disclosed herein.

EDA system700further includes network interface712coupled to processor702. Network interface712allows system700to communicate with network714, to which one or more other computer systems are connected. Network interface712includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems700.

System700is configured to receive information through I/O interface710. The information received through I/O interface710includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor702. The information is transferred to processor702via bus708. EDA system700is configured to receive information related to a UI through I/O interface710. The information is stored in computer-readable medium704as user interface (UI)718.

FIG.8is a block diagram of an integrated circuit (IC) manufacturing system800, and an IC manufacturing flow associated therewith, in accordance with some embodiments.

After block602ofFIG.6A, based on the layout, the IC manufacturing system800implements block604wherein at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit is fabricated using manufacturing system800. In some embodiments, blocks606-614are implemented by the IC manufacturing system800in order to perform block604.

InFIG.8, IC manufacturing system800includes entities, such as a design house820, a mask house830, and an IC manufacturer/fabricator (“fab”)840, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device860. The entities in system800are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and supplies services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house820, mask house830, and IC fab840is owned by a single larger company. In some embodiments, two or more of design house820, mask house830, and IC fab840coexist in a common facility and use common resources.

Design house (or design team)820generates an IC design layout822. IC design layout822includes various geometrical patterns designed for an IC device860. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device860to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout822includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house820implements a proper design procedure to form IC design layout822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout822is presented in one or more data files having information of the geometrical patterns. For example, IC design layout822is expressed in a GDSII file format or DFII file format.

Mask house830includes data preparation832and mask fabrication834. Mask house830uses IC design layout822to manufacture one or more masks to be used for fabricating the various layers of IC device860according to IC design layout822. Mask house830performs mask data preparation832, where IC design layout822is translated into a representative data file (“RDF”). Mask data preparation832supplies the RDF to mask fabrication834. Mask fabrication834includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation832to comply with particular characteristics of the mask writer and/or requirements of IC fab840. InFIG.8, mask data preparation832, mask fabrication834, and mask835are illustrated as separate elements. In some embodiments, mask data preparation832and mask fabrication834are collectively referred to as mask data preparation.

In some embodiments, mask data preparation832includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication834, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation832includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab840to fabricate IC device860. LPC simulates this processing based on IC design layout822to fabricate a simulated manufactured device, such as IC device860. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been fabricated by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout822.

The above description of mask data preparation832has been simplified for the purposes of clarity. In some embodiments, data preparation832includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout822during data preparation832may be executed in a variety of different orders.

After mask data preparation832and during mask fabrication834, a mask835or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The masks are formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication834is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab840uses the mask (or masks) fabricated by mask house830to fabricate IC device860using fabrication tools852. Thus, IC fab840at least indirectly uses IC design layout822to fabricate IC device860. In some embodiments, a semiconductor wafer843is fabricated by IC fab840using the mask (or masks) to form IC device860. Semiconductor wafer843includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer843further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

In some embodiments, a semiconductor device, includes: a cell region including active regions that extend in a first direction and having components of transistors formed therein; the transistors of the cell region being arranged to function as a scan insertion D flip flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF); and the transistors including: data transistors of the multiplexer for selecting a data input signal, the data transistors having a first channel configuration with a first channel size; and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size, the second channel size being smaller than the first channel size. In some embodiments, the active regions include corresponding fins that extend in the first direction; the transistors of the cell region are fin-type field effect transistors (fin-FETs); the first channel size of the data transistors is proportional to a first number of fins included therein; the second channel size of the scan transistors is proportional to a second number of fins included therein; and the second number of fins is fewer than the first number of fins. In some embodiments, the active regions including first active regions and second active regions; the cell region includes a first subregion and a second subregion; the first subregion includes the first active regions; the second subregion includes the second active regions; each of the first active regions have a first height relative to a second direction, the second direction being perpendicular to the first direction; each of the second active regions have a second height relative to the first direction, the second height being less than the first height; the data transistors are formed in the first active regions such that the first channel size of the data transistors is represented by the first height; the scan transistors are formed in the second active regions such that the second channel size of the data transistors is represented by the second channel height. In some embodiments, the first subregion and the second subregion are aligned relative to the first direction and displaced relative to the second direction. In some embodiments, the semiconductor device further includes: combinational logic that generates the data input signal; and wherein: a first propagation delay is defined as a propagation delay of the combinational logic plus a propagation delay of the data input signal through the multiplexer; a second propagation delay is defined as a propagation delay of the scan input signal through the multiplexer; and the second channel size of the scan transistors is sufficiently smaller than the first channel size of the data transistors such that the second propagation delay is approximately equal to the first propagation delay. In some embodiments, the transistors further include delay transistors of the multiplexer; and the delay transistors have the first channel configuration with the first channel size. In some embodiments, the scan transistors include a first positive-channel metal-oxide semiconductor field effect (PMOS) transistor, a second PMOS transistor, a first negative-channel metal-oxide semiconductor field effect (NMOS) transistor, and a second NMOS transistor; the data transistors include a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the delay transistors include a fifth PMOS transistor and a fifth NMOS transistor; the first PMOS transistor and the second PMOS transistor are serially connected between a first node and a second node; the third PMOS transistor and the fourth PMOS transistor are serially connected between a third node and the second node; the fifth PMOS transistor is connected between the second node and the internal node; the fifth NMOS transistor is connected between the internal node and a fourth node; the first NMOS transistor and the second NMOS transistor are serially connected between the fourth node and a fifth node; the third NMOS transistor and the fourth NMOS transistor are serially connected between the fourth node and a sixth node. In some embodiments, the first node is configured to receive a first reference voltage; gates of the first PMOS and second NMOS transistors are configured to receive the scan input signal; gates of the second PMOS and third NMOS transistors are configured to receive an inverted scan-enable signal; gates of the fourth PMOS and first NMOS transistors are configured to receive a non-inverted scan-enable signal; the third node is configured to receive the first reference voltage; gates of the third PMOS and fourth NMOS transistors are configured to receive the data input signal; a gate of the fifth PMOS transistor is configured to receive an non-inverted clock signal; the fifth node is configured to receive a second reference voltage, wherein the second reference voltage is lower than the first reference voltage; a gate of the fifth NMOS transistor is configured to receive an inverted clock signal; and the sixth node is configured to receive the second reference voltage. In some embodiments, the scan transistors include a first positive-channel metal-oxide semiconductor field effect transistor (PMOS), a second PMOS, a first negative-channel metal-oxide semiconductor field effect transistor (NMOS), and a second NMOS; the data transistors include a third PMOS, a fourth PMOS, a third NMOS, and a fourth NMOS; the delay transistors include a fifth PMOS, a sixth PMOS, and a fifth NMOS, and a sixth NMOS; the first PMOS and the second PMOS are serially connected between a first node and a second node; the third PMOS and the fourth PMOS are serially connected between a third node and the second node; the fifth PMOS and the sixth PMOS are serially connected between a fourth node and the internal node; the first NMOS and the second NMOS are serially connected between the second node and a fifth node; the third NMOS and the fourth NMOS are serially connected between the second node and a sixth node; and the fifth NMOS and the sixth NMOS are serially connected between the internal node and a seventh node. In some embodiments, the first node, the third node, and the fourth node are configured to receive a first reference voltage; the fifth node, the sixth node, and the seventh node are configured to receive a second reference voltage, wherein the second reference voltage is lower than the first reference voltage; a gate of the first PMOS is configured to receive the scan input signal; a gate of the second PMOS is configured to receive an inverted scan-enable signal; a gate of the first NMOS is configured to receive a non-inverted scan-enable signal; a gate of the second NMOS is configured to receive the scan input signal; a gate of the third PMOS is configured to receive the data input signal; a gate of the fourth PMOS is configured to receive the non-inverted scan-enable signal; a gate of the third NMOS is configured to receive the data input signal; a gate of the fourth NMOS is configured to receive the non-inverted scan-enable signal; a gate of the fifth PMOS is connected to the second node; a gate of the sixth PMOS is configured to receive a non-inverted clock signal; a gate of the fifth NMOS is configured to receive an inverted clock signal; and a gate of the sixth NMOS is connected to the second node.

In some embodiments, a semiconductor device, includes: a cell region including first, second, third and fourth active regions that extend in a first direction and correspondingly having components of first transistors, second transistors, third transistors and fourth transistors formed therein; the active regions being rectangular; the cell region including a first subregion, the first subregion including the first and second active regions; the first active region being doped with a first conductivity-type dopant; the second active region being doped with a second conductivity-type dopant; the first active region and the second active region having a first height with respect to a second direction, the second direction being perpendicular to the first direction; the cell region further including a second subregion, the second subregion including the third and fourth active regions; the third active region being doped with the first conductivity-type; the fourth active region is of the second conductivity-type dopant; the third active region and the fourth active region having a second height with respect to the second direction, the second height being smaller than the first height; and the transistors of the cell region being arranged to function as a scan insertion D flip flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF); the multiplexer including: corresponding ones of the first transistors and the second transistors as data transistors for selecting a data input signal; and corresponding ones of the third transistors and the fourth transistors as scan transistors for selecting a scan input signal. In some embodiments, the D flip-flop includes: a primary latch that includes a first sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the first sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter; the SDFQ further includes: a clock buffer that includes a second non-sleepy inverter, a third subset of the first transistors and the second transistors being configured as the second non-sleepy inverter; the D flip-flop further includes: an output buffer, a fourth subset of the first transistors and the second transistors being configured as the output buffer; the first sleepy inverter is adjacent to the second non-sleepy inverter; and the first non-sleepy inverter is adjacent to the output buffer. In some embodiments, the D flip-flop includes: a primary latch that includes a sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter; a clock buffer that includes a second non-sleepy inverter, a third subset of the first transistors and the second transistors being configured as the second non-sleepy inverter; an output buffer, a fourth subset of the first transistors and the second transistors being configured as the output buffer; the sleepy inverter is adjacent to the first non-sleepy inverter; and the second non-sleepy inverter is adjacent to the output buffer. In some embodiments, the D flip-flop includes: a primary latch that includes a sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter; a clock buffer that includes a second non-sleepy inverter, a third subset of the first transistors and the second transistors being configured as the second non-sleepy inverter; an output buffer, a first subset of the third transistors and the fourth transistors being configured as the output buffer; the sleepy inverter is adjacent to the second non-sleepy inverter; and the second non-sleepy inverter is positioned between the sleepy inverter and the first non-sleepy inverter. In some embodiments, the D flip-flop includes: a primary latch that includes a sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter; a clock buffer that includes a second non-sleepy inverter, a third subset of the first transistors and the second transistors being configured as the second non-sleepy inverter; an output buffer, a first subset of the third transistors and the fourth transistors being configured as the output buffer; the sleepy inverter is adjacent to the first non-sleepy inverter; and the first non-sleepy inverter is positioned between the sleepy inverter and the second non-sleepy inverter. In some embodiments, the D flip-flop includes: a primary latch that includes a sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter; a clock buffer that includes a second non-sleepy inverter, a first subset of the third transistors and the fourth transistors being configured as the second non-sleepy inverter; an output buffer, a third subset of the first transistors and the second transistors being configured as the output buffer; the sleepy inverter is adjacent to the first non-sleepy inverter; and the first non-sleepy inverter is positioned between the sleepy inverter and the output buffer. In some embodiments, the D flip-flop includes: a primary latch that includes a first sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the first sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter, the first transistors and the second transistors including delay transistors of the multiplexer; a secondary latch that includes a second sleepy inverter and a second non-sleepy inverter, a first subset of the third transistors and the fourth transistors that being configured as the second sleepy inverter and a second subset of the third transistors and the fourth transistors being configured as the second non-sleepy inverter; a clock buffer that includes a third non-sleepy inverter and a fourth non-sleepy inverter connected in series, a third subset of the first transistors and the second transistors being configured as the third non-sleepy inverter and a third subset of the third transistors and the fourth transistors being configured as the fourth non-sleepy inverter; an internal buffer coupled between the primary latch and the secondary latch, wherein a fourth subset of the third transistors and the fourth transistors being configured as the internal buffer; the first non-sleepy inverter is adjacent to the delay transistors, the delay transistors are adjacent to the first sleepy inverter, and the first sleepy inverter is adjacent to the third non-sleepy inverter; and the second non-sleepy inverter is adjacent to the second non-sleepy inverter, the second non-sleepy inverter is adjacent to transmission gate, and the internal buffer is adjacent to the fourth non-sleepy inverter. In some embodiments, the D flip-flop includes: a primary latch that includes a first sleepy inverter and a first non-sleepy inverter, a first subset of the first transistors and the second transistors being configured as the first sleepy inverter and a second subset of the first transistors and the second transistors being configured as the first non-sleepy inverter, the first transistors and the second transistors including delay transistors of the multiplexer; a secondary latch that includes a second sleepy inverter and a second non-sleepy inverter, a first subset of the third transistors and the fourth transistors being configured as the second sleepy inverter and a second subset of the third transistors and the fourth transistors are configured as the second non-sleepy inverter; a clock buffer that includes a third non-sleepy inverter and a fourth non-sleepy inverter connected in series, a third subset of the first transistors and the second transistors being configured as the third non-sleepy inverter and a third subset of the third transistors and the fourth transistors being configured as the fourth non-sleepy inverter; an internal buffer coupled between the primary latch and the secondary latch, wherein a fourth subset of the third transistors and the fourth transistors being configured as the internal buffer; the third non-sleepy inverter is adjacent to the delay transistors, the delay transistors are adjacent to the first sleepy inverter, and the first sleepy inverter is adjacent to the first non-sleepy inverter; and the fourth non-sleepy inverter is adjacent to the second non-sleepy inverter, the second non-sleepy inverter is adjacent to transmission gate, and the internal buffer is adjacent to the second non-sleepy inverter.

In some embodiments, a method of forming a semiconductor device, the method includes: forming a substrate; forming active regions (ARs) in the substrate including doping corresponding areas of the substrate resulting in the active regions extending in a first direction, a first subregion of the substrate including first and second ones of the active regions (first and second active regions), the first active region having a first conductivity-type dopant, the second active region having a second conductivity-type dopant, each of the first and second active regions having a first height with respect to a second direction, the second direction being perpendicular to the first direction, a second subregion of the substrate including third and fourth ones of the active regions (third and fourth active regions), the third active region having the first conductivity-type, the fourth active region having the second conductivity-type dopant; and each of the third and fourth active regions having a second height with respect to the second direction, the second height being smaller than the first height; forming source/drain (S/D) regions in the ARs including doping corresponding first areas of the active regions, the S/D regions representing first transistor-components, the forming S/D regions resulting in second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components, ones of the channel regions in the first and second active regions having a first channel size, and ones of the channel regions in the third and fourth active regions a second channel size, the second channel size being smaller than the first channel size; and forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and the forming active regions, the forming S/D regions and the forming gate lines further resulting in transistors which are configured to define a scan insertion D flip flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF), a subset of ones of the transistors that define the multiplexer including ones of the transistors having first and second transistor-components which are in the first and second active regions and which represent data transistors for selecting a data input signal, and ones of the transistors having first and second transistor-components which are in the third and fourth active regions and which represent scan transistors for selecting a scan input signal.

In some embodiments, the forming active regions further results in the first subregion and the second subregion being aligned relative to the first direction and displaced relative to the second direction.