Reduced precision vector processing

Methods, systems, and devices are described for wired communication. In one aspect, a method includes selecting a gain scalar based at least in part on a constellation point distance associated with a constellation mapper for a line and a tone. The method also includes applying the gain scalar to a tone data output signal of a vector processor.

BACKGROUND

Field of the Disclosure

The present disclosure, for example, relates to data communications, and more particularly, to techniques for reduced precision vector processing in wired communication systems, such as but not limited to digital subscriber line (DSL) systems.

Description of Related Art

DSL communications, like other wired communications, suffer from various forms of interference, including but not limited to crosstalk. Vectored DSL systems can be used to mitigate interference and increase the data throughput. For vector processing, signals need to be transported from a modem physical layer (PHY) to a vector processor unit. Lossless (or near lossless) transportation of the data associated with these signals may require large bandwidth. Also, a multiplier width of the vector processor unit can depend on a bitwidth of the signals to be input into the vector processor unit. Generally, reducing the bitwidth of the signals representation introduces quantization noise. Also, in some scenarios, such as but not limited to nonlinear precoding, the signals may have a very high dynamic range and number of bits required for representation of such signals increases accordingly. In situations where only lower precision (e.g., reduced or shorter bitwidth) vector processing resources are available, the use of lower precision vector processor units may introduce significant quantization to signals with high dynamic range.

SUMMARY

The present description discloses techniques for reducing the bit precision requirement of signals that are input to a vector processor. The techniques enable the lossless (or near lossless) transportation of signals with reduced bandwidth at the vector processing interface. The reduced precision incoming signals also results in a corresponding reduction in the bitwidth of vector multipliers in the vector processor. According to these techniques, aspects of vectored DSL systems can be applied to implement, or utilize the existing, reduced bit precision vector processing resources. Aspects of the present disclosure include techniques for partitioning the gain of incoming signals such that computations associated with vector processing can be simplified.

In some examples, a signal is represented as a combination of two reduced precision signals, and the two reduced precision signals are processed in parallel by vector processing resources of a vector processor. Such examples that process two reduced precision signals include the case of nonlinear precoding (NLP). In NLP cases, the input to the vector processing interface can be represented as a combination of two signal streams. The bit precision requirement of both signal streams can be reduced. In some implementations, the two signal stream are parallel processed by the same or similar vector processing resources of the vector processor. In this manner, the results of the vector processor from each of the signal streams are combined to obtain the desired output signal.

Additionally, according to the techniques described herein, the bit precision requirement of vector processing resources is minimized while introducing almost no quantization noise. As such, when spare vector processing resources are made available by efficiency gains due to the reduced bit precision requirement, the resources can be used in parallel to process signals with higher dynamic range.

A method for wired communication is described. The message includes selecting a gain scalar based at least in part on a constellation point distance associated with a constellation mapper for a line and a tone. The gain scalar is then applied to a tone data output signal of a vector processor.

A wired communication device is described. The wired communication device includes a constellation mapper, a vector processor, a gain selector, and at least one gain component. The gain selector is to select a gain scalar based at least in part on a constellation point distance associated with the constellation mapper for a line and a tone, and the at least one gain component is to apply the gain scalar to a tone data output signal of the vector processor.

Another wired communication device includes means for selecting a gain scalar based at least in part on a constellation point distance associated with a constellation mapper for a line and a tone, and means for applying the gain scalar to a tone data output signal of a vector processor.

A non-transitory computer-readable medium storing code for wireless communication is described. The code of the non-transitory computer-readable medium includes computer-readable code that, when executed, causes a device to select a gain scalar based at least in part on a constellation point distance associated with a constellation mapper for a line and a tone; and apply the gain scalar to a tone data output signal of a vector processor.

Regarding the above-described method, wired communication devices, and non-transitory computer-readable medium, a gain vector can be selected based at least in part on the gain scalar, and the gain vector can be applied to a normalized tone data output signal vector of the constellation mapper. The gain vector can be selected based at least in part on an integer multiplier component, for example using one or more of: a rounding operation, a ceiling operation, an exponent of a rounding operation of a log value, and an exponent of a ceiling operation of a log value.

A remaining gain vector can be determined based at least in part on the gain scalar, and the remaining gain vector can be applied to a precoder of the vector processor. In some cases, a constellation point of the constellation mapper is represented with integer values.

A nonlinear part gain scalar can be selected based at least in part on a modulo size associated with the constellation mapper for the line and the tone, and the nonlinear part gain scalar can be applied to a nonlinear adjustments output signal of the vector processor. The vector processor can include a first vector processing component for processing an intermediate tone data signal vector and a second vector processing unit for processing an intermediate nonlinear adjustments signal vector. The nonlinear part gain vector can be selected based at least in part on the nonlinear part gain scalar, and the nonlinear part gain vector can be applied to a normalized nonlinear adjustments output signal vector of a nonlinear precoding processor. The sum of the gain-applied tone data output signal and the nonlinear part gain-applied nonlinear adjustments nonlinear adjustments output signal can then be summed.

A remaining gain vector can be determined based at least in part on the gain scalar, and a remaining nonlinear part gain vector can be determined based at least in part on the nonlinear part gain scalar. In some cases, the remaining gain vector is applied to a precoder of a first vector processing component of the vector processor for processing an intermediate tone data signal vector, and the remaining nonlinear part gain vector is applied to a precoder of a second vector processing component of the vector processor for processing an intermediate nonlinear adjustments signal vector. The gain scalar and the nonlinear part gain scalar can be selected such that the remaining gain vector and the remaining nonlinear part gain vector are the same, and the remaining gain vector can be applied to a precoder of the vector processor. The remaining nonlinear part gain vector can be applied to the precoder of the vector processor at a different time than the remaining gain vector.

In some accordance with some aspects, the above-described method, wired communication devices, and non-transitory computer-readable medium are implemented in DSL communication systems and devices.

DETAILED DESCRIPTION

According to aspects of the present disclosure, a gain selector of a line card (e.g., a line card of a DSL access multiplexer (DSLAM)) selects a gain scalar based at least in part on a constellation point distance associated with the constellation mapper for a line and a tone. The gain selector also selects a gain vector based at least in part on the gain scalar. A gain component of the line card applies the gain vector to a normalized signal vector of the constellation mapper. The gain component also applies the gain scalar to an output signal of a vector processor (e.g., a vectoring card of a DSLAM). In this regard, gain partitioning techniques allow the signals to be mapped on an integer grid representation for reduced precision representation. The partitioned gains are redistributed to enable the desired computational benefits of the vector processor. These and additional aspects of the present disclosure reduce the bit precision requirement of signals that are input to the vector processor. As such, lossless (or near lossless) transportation of signals (e.g., tone data signals) with reduced bandwidth at the vector processing interface.

In the absence of crosstalk, the existing copper telephone infrastructure can in theory be utilized to carry from tens to hundreds of megabits per second over distances up to approximately 5,000 feet using discrete multitone (DMT) digital subscriber line (DSL) modem technology. DMT modems divide the available bandwidth into many sub-carriers that are synchronized and independently modulated with digital quadrature amplitude modulation (QAM) data to form an aggregate communication channel between the network and subscriber. DMT-based DSL systems typically use Frequency Division Multiplexing (FDM) and assign particular sub-carriers to either downstream (that is, from network/CO to subscriber/user) or upstream (from subscriber/user to network/CO) directions. This FDM strategy limits near end crosstalk (NEXT). DMT systems are typically very robust in the presence of radio frequency interference (RFI) and other types of frequency-selective noise (or interference) or channel dispersion, because each sub-carrier can be independently modulated with an appropriate amount of data and power in order to meet the system requirements and the desired bit error rate.

Aspects of the present disclosure reduce the bit precision requirement of signals (e.g., tone data in a digital QAM data format) to reduce the required vector processing resources and optimize vectored DMT systems (e.g., DMT-based DSL systems and like systems). In this manner, by reducing the number of bits to represent a signal, nonlinear adjustments signals can be processed in a parallel using extra or freed vector processing resource. Similar techniques with the same (or lesser) bit precision by partitioning gain (e.g., gain scalars and gain vectors) as used with respect to the signal can be applied in processing the nonlinear adjustments signal by partitioning vector processing resource or components. Consequently, a lossless (or near lossless) signal that includes nonlinear adjustments can be transported with reduced bit precision and bandwidth by reusing the extra or freed vector processing resources.

It is to be appreciated that, while the present disclosure describes the techniques for reducing the bit precision requirement of signals in the context of vectored DMT systems, aspects of the present disclosure are equally applicable to other communication systems. For example, aspects of the present disclosure apply to various wired communication technologies including, but not limited to, FDM and orthogonal frequency division multiplexing (OFDM) systems associated with coaxial cable communications, power line communications, Ethernet communications, and other wired communication systems where appropriate. Additionally, aspects of the present disclosure can apply to wireless communication systems, for example, where QAM-based schemes are utilized. As such, the scope of the present disclosure is not limited to the specific examples provided with respect to vectored DMT systems.

Referring first toFIG. 1, a block diagram illustrates an example of a vector processing architecture100for use in vectored DMT or OFDM system (such as, but not limited to, a vectored DMT-based DSL system), in accordance with various aspects of the present disclosure. The vector processing architecture100includes a constellation mapper110, a vector processor120, and an output signal source130.

For vectored DMT systems in the downstream, the signals (e.g., tone data) need to be transported from the output of constellation mapper110to vector processor120. The downstream signals are then processed by the vector processor120. Reducing the number of bits to represent the signals can reduce the bandwidth requirement and, consequently, the number of bits required for the vector processing operation. InFIG. 1, the block diagram of the vectored DMT system is illustrated for one tone (e.g. frequency). For tone q of the t-th DMT symbol, define:

x′⁡[q,t]=[x1′⁡[q,t]⋮xN′⁡[q,t]]
to be the mapper output, one corresponding to each line in the vector group.

Gain⁢[q]=[Gain1⁡[q]⋮GainN⁡[q]]
to be the transmit gains corresponding to each line.

Outputs of the constellation mapper110are normalized to the unit energy. In other words, elements of x′[q, t] are scaled by transmit gains before being processed by the vector processor120. The dynamic range of the constellation mapper output signal vector x′[q, t] and Gain decides the precision required for signal vector x[q, t]. Signal vector x[q, t] is input to the vector processor120and the output of the vector processor120is expressed as:
y[q,t]=VP(x[q,t],q)=P*x[q,t]
y[q,t]=P[q]*diag(Gain[q])*x′[q,t],
where diag(Gain[q]) is diagonal matrix with diagonal elements from vector Gain[q]. Output signal vector y[q, t] is available at output signal source130.

The constellation points (i.e., the signals of vector x′[q, t]) are selected from a grid of an integer multiple of half the distance between constellation points. The distance between constellation points depends on the bits loading of the tone. Utilizing this structure of the constellation mapper output and splitting the transmit Gain vector suitably (e.g., so that a part of it could be applied to the precoder), the required precision for x[q, t] can be reduced considerably.

FIG. 2illustrates an example of a reduced precision vector processing architecture200that supports reduced precision vector processing in accordance with various aspects of the present disclosure. The reduced precision vector processing architecture200includes a constellation mapper110-a, a gain splitter215, a vector processor120-a, and an output signal source130-a. The example reduced precision vector processing architecture200shown inFIG. 2is illustrated with respect to constellation mapper110-a, vector processor120-a, and output signal source130-a, which are respective examples of similar devices ofFIG. 1.

In accordance with some aspects, 2di[q] is defined to be the constellation point distance for the constellation mapper110-1of line i for the q th tone. Gain splitter215selects scalar gain α[q] such that

0<α⁡[q]<min1≤i≤N⁢(2⁢⁢di⁡[q])
and gain vector

Xi=I⁡(di⁡[q]α⁡[q])*1di⁡[q]
where I(•) represents an integer multiplier as a function of

Some of the possible examples for function I(•) include a rounding operation, a ceiling operation, an exponent of a rounding operation of a log value, and an exponent of a ceiling operation of a log value. For example, the function I(•) can be

Gain splitter215applies the gain vector

χ⁡[q]=[χ1⁡[q]⋮χN⁡[q]]
to the output of constellation mapper110-a. The resulting vector (e.g., an intermediate vector in the transportation process) can be expressed as

The value of scalar gain α[q] is selected such that the performance impact (if any) due to the change in the precoder from P[q] to P[q]*G[q], is minimal. The value of scalar gain α[q] can be used to tradeoff between Gi[q]/Gaini[q] and precision requirement of xi[q, t]. The smaller value of scalar gain α[q] will lead Gi[q]/Gaini[q] ratio closer to unity. One example of the possible values of scalar gain α[q] is

Output signal vector y[q, t], after applying the scalar gain α[q], is available at output signal source130.

FIG. 3illustrates an example of a constellation map300that supports reduced precision vector processing in accordance with various aspects of the present disclosure. Constellation map300includes examples of 2, 4, and 6 bit constellation patterns. However, aspects of the reduced precision vector processing techniques are not limited to these example constellation patterns and may apply to other constellation patterns of QAM schemes (e.g., 128-QAM and 256-QAM) and other discrete structure signaling concepts.

With reference toFIG. 2, in one example, three lines in the system utilizing reduced precision vector processing architecture200are loaded with 2, 4, and 6 bits of information on a given tone. The output of the constellation mapper110-ais normalized to unit energy. As shown inFIG. 3, the constellation points of constellation map300are fractional complex numbers. Examples of constellation point distances for the three lines are shown inFIG. 3and include 2-bit constellation point distance302as 2d1, 4-bit constellation point distance304as 2d2, and 6-bit constellation point distance306as 2d3.

All of the lines can be assumed to have unity transmit Gain to applied to the signals of the respective lines. Using the reduced precision vector processing techniques described herein, the various constellation points of constellation map300can be represented by integers with little to no loss of information. An example of reduced precision, integer plotted constellation map400is shown inFIG. 4.

In one example ofFIG. 4, only 4 bits per dimension (e.g., real and imaginary axis, totaling 8 bits for complex numbers) are required to represent the reduced precision tone data in a lossless manner. For example, if the max bit loading on a tone is m bits, then with the reduced precision vector processing techniques described herein, output signals with reduced precision of the constellation mapper110-acan be represented with

FIG. 5illustrates an example of a parallel-computation, reduced-precision vector processing architecture500for NLP cases that supports parallel computation and reduced precision vector processing in accordance with various aspects of the present disclosure. The parallel-computation, reduced-precision vector processing architecture500includes a constellation mapper110-b, an NLP processor, a first gain splitter215-a, a second gain splitter215-b, a vector processor120-b, and an output signal source130-b. The example parallel-computation, reduced-precision vector processing architecture300shown inFIG. 5is illustrated with respect to constellation mapper110-b, first gain splitter215-a, second gain splitter215-b, vector processor120-b, and output signal source130-b, which are respective examples of similar devices ofFIGS. 1 and 2.

In case of NLP, a nonlinear adjustments signal s[q, t] is added to the tone data signal before vector processing so that the output of the vector processor120-bdoes not violate the specified power level. The nonlinear adjustments signals si[q, t] are generated using a modulo operation. The modulo size is a number larger than size of the constellation map from which xi[q, t] are generated. The precision requirement for x[q, t] is the same as described in the previous examples described with respect toFIG. 2. In some examples, the reduced precision vector processing techniques described herein can be validly applied to the combined signal x[q, t]+s[q, t] with appropriate choice of the nonlinear adjustments signal s[q, t]. In these examples, the nonlinear adjustments signal s[q, t] can be selected such that the nonlinear adjustments signal can be represented in the form of integer multiples of the constellation point distance.

However, because the integer multiple values for si[q, t] are typically larger (e.g., larger than constellation map sizes of the signal x[q, t], the constellation mapper110-bwould be required encode extra bits. If the extra bits for tone data signal are not provisioned, a parallel computation using extra vector processing resource of vector processor120-bwith similar (or lesser) precision can be performed using similar approach for the nonlinear adjustments signal s[q, t]. According to some examples, the output signal vector y[q, t] using vector processing (VP) resources is represented as follows:
y[q,t]=VP(x[q,t]+s[q,t],q)=VP(x[q,t],q)+VP(s[q,t],q)
y[q,t]=P[q]x[q,t]+P[q]s[q,t]
y[q,t]=P[q]*diag(Gain[q])*x′[q,t]+P[q]*diag(Gain[q])s′[q,t],
where diag(Gain[q]) is diagonal matrix with diagonal elements from vector Gain[q]. The nonlinear adjustments signals si[q, t] can also be treated in the same manner as xi[q, t] except that, in such cases, the distance between the constellation points is replaced by the size of the modulo operation (e.g., using an approximation of a constellation map size). In this manner, the nonlinear adjustments signals si[q, t] can be viewed as another signal coming from constellation mapper110-bsuch that the nonlinear adjustments signals si[q, t] has a larger distance between constellation points of a constellation map.

The tone data signal x[q, t], remaining gain vector G[q], gain vector χ[q], and scalar gain α[q] for the first vector processing component of vector processor120-bare same as described in the above example with respect toFIG. 2. The nonlinear processed part of the nonlinear adjustments signal s[q, t] is an integer multiple of the modulo sizes. In these nonlinear processed part examples, unity gain may be similarly applied as with tone data signal x[q, t]. Modulo sizes are signed integers including zeros, and can be similarly represented as discussed with respect to constellation maps herein. For example, selecting nonlinear part gain scalar β[q]=1.2344, results in a nonlinear part gain vector γ[q]=[0.7071 0.7906 0.8101] while remaining nonlinear part gain vector Ψ[q]=[1.1456 1.0247 1.0000]. In this regard, scalar gain scalar gain α[q] (shown as 0.1543 inFIG. 4) can be different from nonlinear part gain scalar β[q], which is related to shift values.

According to some aspect, parallel processing is used to partition the various gains such that remaining gain vector G[q] and remaining nonlinear part gain vector Ψ[q] are the same (e.g., by suitably choice of scalar gain α[q] and the modulo size for tone q, Md[q]). In these case, the same vector processing resources of vector processor120-bcan be reused by operating the vector processor120-cat higher speeds.

It is to be appreciated that, with some modifications (as would be apparent to a skilled person given the benefit of the present disclosure), the reduced precision vector processing techniques described herein can be applied to upstream signals, for example, by splitting the incoming signals as combination of a course grid and a small difference signal (e.g., as represented with respect to the course grid).

Additionally, the techniques for reducing the bit precision requirement of signals are applicable for any signals having discrete structure characteristics. For example, while the output signals of constellation mapper110-bform a discrete grid with respect to a complex number plane, the present disclosure is not limited in this manner. In some examples, when signals do not have a discrete structure (or the signals are a combination of signals each having discrete grid), such signals could be divided into multiple streams of structured signals and a low dynamic difference signal for reduced precision representation. The multiple streams of reduced precision signals can be processed in parallel and then combined to get the desired output signal. In cases involving NLP processing or preprocessing, the incoming signal can be viewed as a combination or summation of two signals having different discrete structures. In this regard, similar vector processing components of vector processor120-ccan be used for parallel processing of signals with little additional processing and/or associated components.

FIG. 6Ashows a block diagram600-aof an example of a vectoring data communication architecture including line card601and vectoring card651that supports reduced precision vector processing in accordance with various aspects of the present disclosure, and with respect toFIGS. 1-5. Line card601and vectoring card651operate as part of a vectored DMT-based DSL system (e.g., as cards of a DSLAM). It is to be understood that, in some implementations, the component and functions of line card601and vectoring card651can be included on a single card, circuit board, or the like.

The line card601includes a processor605, a memory610, one or more transceivers or interfaces620, a constellation mapper110-c, a gain selector625, and a gain component630. The processor605, memory610, transceiver(s)/interface(s)620, constellation mapper110-c, gain selector625, and gain component630are communicatively coupled with a bus645, which enables communication between these components.

The processor605is an intelligent hardware device, such as a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), etc. The processor605processes information received through the transceiver(s)/interface(s)620and information to be sent to the transceiver(s)/interface(s)620for transmission to other cards or devices. The transceiver(s)/interface(s)620are communicatively coupled to vectoring card651via communication link650. In some implementations, communication link650is an optical interconnect.

The memory610stores computer-readable, computer-executable software (SW) code615containing instructions that, when executed, cause the processor605or another one of the components of line card601to perform various functions described herein, for example, selecting a gain scalar based at least in part on a constellation point distance and a tone and applying the gain scalar to a tone data output signal.

The constellation mapper110-c, gain selector625, and gain component630implement the features described with reference toFIGS. 1-5, as further explained below in the example methods disclosed herein. In some implementations, gain selector625and gain component630can include multiple gain selectors and gain components, and can be incorporated in one or more of the gain splitters215described and illustrated inFIGS. 2 and 5.

The vectoring card651includes a processor655, a memory660, one or more transceivers or interfaces670, a vector processor120-c, and a summer525-a. The processor655, memory660, transceiver(s)/interface(s)670, vector processor120-c, and summer525-aare communicatively coupled with a bus695, which enables communication between these components.

The processor655is an intelligent hardware device, such as a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), etc. The processor655processes information received through the transceiver(s)/interface(s)670and information to be sent to the transceiver(s)/interface(s)670for transmission to other cards or devices. The transceiver(s)/interface(s)670are communicatively coupled to line card601via communication link650.

The memory660stores computer-readable, computer-executable software (SW) code665containing instructions that, when executed, cause the processor655or another one of the components of line card601(e.g., vector processor120-c) to perform various functions described herein, for example, the vector processor120-ccan comprise a first vector processing component for processing an intermediate tone data signal vector and a second vector processing component for processing an intermediate nonlinear adjustments signal vector.

The vector processor120-cand summer525-aimplement the features described with reference toFIGS. 1-5, as further explained below in the example methods disclosed herein. Vector processor120-ccan include multiple vector processing units or components that may perform a same function in combination and/or perform one or more different functions.

In accordance with some aspects of the disclosure, vector processing can be performed such that two or more signal streams are input to vector processor120-c. In this regard, vector processor120-ccan be converted such that portions thereof can support various vector processing tasks or functions. For example, a 48×48p G.fast compliant 106 MHz vector processor can be converted to a 24×24p G.fast 212 MHz with NLP whereby a first vector processing module is configured a 24×24p as a 0-106 MHz linear precoder, a second vector processing module is configured a 24×24p as a 106-212 MHz linear precoder, a third vector processing module is unused as nonlinear precoding may be unnecessary for 0-106 MHz, and a fourth vector processing module is configured a 24×24p NLP preprocessor for the second vector processing module. In this manner, some of the vector processing components of vector processor120-ccan be enhanced and used to support NLP implementations.

Again,FIG. 6Ashows only one possible implementation of a device executing the features ofFIGS. 1-5. While the components ofFIG. 6Aare shown as discrete hardware blocks (e.g., ASICs, field programmable gate arrays (FPGAs), semi-custom integrated circuits, etc.) for purposes of clarity, it will be understood that each of the components may also be implemented by multiple hardware blocks adapted to execute some or all of the applicable features in hardware. Alternatively, features of two or more of the components ofFIG. 6Amay be implemented by a single, consolidated hardware block. For example, a single transceiver620chip may implement the processor605, constellation mapper110-c, gain selector625, and gain component630.

In still other examples, the features of each component may be implemented, in whole or in part, with instructions embodied in a memory, formatted to be executed by one or more general or application-specific processors. For example,FIG. 6Bshows a block diagram600-bof another example of a vectoring data communication architecture that supports reduced precision vector processing. Line card601-ais configured such that the features of the constellation mapper110-d, gain selector625-a, and gain component630-aare implemented as computer-readable code stored on memory610-aand executed by one or more processors605-a. Similarly, vectoring card651-ais configured such that the features of the vector processor120-dand summer525-bare implemented as computer-readable code stored on memory660-aand executed by one or more processors655-a. Other combinations of hardware/software may be used to perform the features of one or more of the components ofFIGS. 6A and 6B.

FIG. 7shows a flow chart that illustrates one example of a method700for reduced precision vector processing in accordance with various aspects of the present disclosure. Method700may be performed by any of the components discussed in the present disclosure, but for clarity method700will be described from the perspective of line card601and vectoring card651ofFIG. 6A. It is to be understood that method700is just one example of techniques for reducing the bit precision requirement of the signals input to the vector processor120-c, thereby enabling the lossless (or near lossless) transportation of signals with reduced bandwidth at the vector processing interface. The operations of the method700may be rearranged, performed by other devices and component thereof, and/or otherwise modified such that other implementations are possible.

Broadly speaking, method700illustrates a procedure by which the bit precision requirement of signals (e.g., tone data signals) is reduced. While the bit precision is reduced, the techniques described in method700enable lossless (or near lossless) transportation of the signals that are input to the vector processor120-c. To this end, method700includes techniques for partitioning the gain of the signals that are input to vector processor120-c. Method700relates to the reduced precision vector processing architecture example provided inFIG. 2and discussed herein.

At block705, gain selector625of line card601selects a gain scalar (e.g., α[q]). The gain scalar is selected based at least in part on a constellation point distance associated with constellation mapper110-cfor a particular line and a particular tone. Additionally, gain selector625selects a gain vector (e.g., χ[q]). The gain vector is selected based at least in part on the gain scalar.

In one option, at block710, gain selector625selects the gain vector based at least in part on an integer multiplier component. For example, the integer multiplier component of the gain vector can based on a function the constellation point distance and the gain scalar. In some examples, the integer multiplier component can be based at least in part on a rounding operation, a ceiling operation, an exponent of a rounding operation of a log value, or an exponent of a ceiling operation of a log value.

At block715, gain component630of the line card601applies the gain vector to a normalized tone data output signal vector (e.g., x′[q, t]) of the constellation mapper110-c. At block720, constellation mapper110-crepresents a constellation point with integer values. Thus, by applying the gain vector to the constellation mapper output, the real axis and imaginary axis of a constellation point can be expressed as integer values.

At block725, according to one option, gain selector625determines a remaining gain vector (e.g., G[q]) based at least in part on the gain scalar. According to one option, at block730, gain component630applies the remaining gain vector to a precoder of the vector processor120-cof the vectoring card651. In some implementations, the gain component630provides the remaining gain vector to the vector processor120-cand the remaining gain vector is applied to the precoder by the vector processor120-cor another component of vectoring card651. Additionally, in this option, the precoder can be a linear precoder.

At block735, gain component630applies the gain scalar to a tone data output signal (e.g., y′[q, t]) of the vector processor120-c. Similarly as discussed above, in some implementations, the gain component630provides the gain scalar to the vector processor120-cand the gain scalar is applied to the tone data output signals by the vector processor120-cor another component of vectoring card651. In this manner, a lossless (or near lossless) tone data output signal (e.g., y[q, t]) can be transported with reduced bit precision and bandwidth.

FIG. 8shows a flow chart that illustrates one example of a method800for reduced precision vector processing associated with NLP cases in accordance with various aspects of the present disclosure. Method800may be performed by any of the components discussed in the present disclosure, but for clarity method800will be described from the perspective of line card601and vectoring card651ofFIG. 6A. It is to be understood that method800is just one example of techniques for reducing the bit precision requirement of the signals input to the vector processor120-c, thereby enabling the lossless (or near lossless) transportation of signals with reduced bandwidth at the vector processing interface. The operations of the method800may be rearranged, performed by other devices and component thereof, and/or otherwise modified such that other implementations are possible.

Broadly speaking, method800illustrates a procedure by which the bit precision requirement of signals (e.g., tone data signals) is reduced in the complex case where NLP is employed. While the bit precision is reduced, the techniques described in method800enable lossless (or near lossless) transportation of the signals that are input to the vector processor120-c. To this end, method800includes techniques for partitioning the gain of the signals that are input to vector processor120-c. Method800relates to the reduced precision vector processing architecture example provided inFIG. 5and discussed herein. Additionally, aspects of method800can include parallel computation and processing of signals and is thus illustrated in such a parallel manner. However, the parallel nature of the blocks ofFIG. 8is not necessarily indicative of timing or order of the execution of the processes described in these blocks.

At block802, gain selector625of line card601selects a gain scalar. The gain scalar is selected based at least in part on a constellation point distance associated with constellation mapper110-cfor a particular line and a particular tone. Additionally, gain selector625selects a gain vector (e.g., χ[q]), which is selected based at least in part on the gain scalar.

At block804, gain selector625selects a nonlinear part gain scalar (e.g., β[q]). The nonlinear part gain scalar is selected based at least in part on a modulo size associated with the constellation mapper for the line and the tone. Additionally, gain selector625selects a nonlinear part gain vector (e.g., γ[q]) based at least in part on the nonlinear part gain scalar. In this regard, the nonlinear part gain scalar and the nonlinear part gain vector are associated with a nonlinear adjustments signal (e.g., s[q, t]). Moreover, gain selector625that selects the nonlinear part gain scalar and the nonlinear part gain vector can be a similar, but different gain selector of line card601than the gain selector625that selects the gain scalar and the gain vector at block802.

In one option, at block806, gain selector625selects the gain scalar and the nonlinear part gain scalar such that a remaining gain vector and a remaining nonlinear part gain vector (discussed with respect to block822and block824, respectively) are the same. In this manner, certain computations for the tone data signal and the nonlinear adjustment signal can be performed using the same vector resources of the vector processor120-c, for example, by operating the vector processor120-cat a higher speed such that vector resources can switch between parallel and related computations. However, it is understood that the operations of block806are not necessary in implementations where vector processing resources of the vector processor120-care not to be shared or reused for the signal streams associated with the tone data signal and the nonlinear adjustment signal.

At block812, gain component630of the line card601applies the gain vector to a normalized tone data output signal vector (e.g., x′[q, t]) of the constellation mapper110-c. Additionally, as discussed inFIG. 7, constellation mapper110-ccan represent a constellation point with integer values by applying the gain vector to the constellation mapper output. At block814, gain component630applies the nonlinear part gain vector to a normalized nonlinear adjustments signal vector (e.g., s′[q, t]).

At block822, according to one option, gain selector625determines a remaining gain vector (e.g., G[q]) based at least in part on the gain scalar. At block824, according to one option, gain selector625also determines a remaining nonlinear part gain vector (e.g., Ψ[q]) based at least in part on the nonlinear part gain scalar.

According to one option, at block832, gain component630applies the remaining gain vector to a precoder of the vector processor120-cof the vectoring card651. In some implementations, the gain component630provides the remaining gain vector to the vector processor120-cand the remaining gain vector is applied to the precoder by the vector processor120-cor another component of vectoring card651.

According to one option, at block834, gain component630applies the remaining nonlinear part gain vector to a precoder of the vector processor120-cof the vectoring card651. In some implementations, the gain component630provides the remaining nonlinear part gain vector to the vector processor120-cand the remaining nonlinear part gain vector is applied to the precoder by the vector processor120-cor another component of vectoring card651.

At block836, according to one option, the remaining gain vector and the remaining nonlinear part gain vector may be applied using different vector processing resources or components. In this option, the remaining gain vector is applied to a precoder of a first vector processing component of the vector processor110-c. The first vector processing component is used for processing an intermediate tone data signal vector (e.g., z[q, t]). The remaining nonlinear part gain vector is applied to a precoder of a second vector processing component of the vector processor110-c, different from the first vector processing component. The second vector processing component is used for processing an intermediate nonlinear adjustments signal vector (e.g., u[q, t]). In this manner, two simultaneous signal streams are configured through the vector processor interface as input to vector processor120-c.

At block838, according to one option, the remaining gain vector and the remaining nonlinear part gain vector may be applied using the same vector processor resources or components. In this option, the remaining gain vector is applied to a precoder of the vector processor120-c. For example, one or more resources or components of the vector processor120-care used for processing an intermediate tone data signal vector (e.g., z[q, t]) during a first time period. The remaining nonlinear part gain vector is applied to the precoder of the vector processor110-c. During a second time period different from the first time period, the same one or more resources or components of the vector processor120-care used for processing an intermediate nonlinear adjustments signal vector (e.g., u[q, t]). Thus, the two signal streams associated with the tone data signal and the nonlinear adjustments signal are effectively configured as one signal stream through the vector processor interface as input to vector processor120-cin a time-division manner.

As noted with respect to block806, when the remaining gain vector and the remaining nonlinear part gain vector are the same, computations for the tone data signal and the nonlinear adjustment signal associated with applying the remaining gain vector and remaining nonlinear part gain vector can be performed using the same vector resources or components of the vector processor120-c. In these cases, the vector processor120-cis operated at a higher speed such that vector resources can switch between parallel and related computations during the first time period and the second time period described with respect to block838.

At block842, gain component630applies the gain scalar to a tone data output signal (e.g., y′[q, t]) of the vector processor120-c. In some implementations, the gain component630provides the gain scalar to the vector processor120-cand the gain scalar is applied to the tone data output signal by the vector processor120-cor another component of vectoring card651. At block844, gain component630applies the nonlinear part gain scalar to a nonlinear adjustments output signal (e.g., v[q, t]) of vector processor120-c. In some implementations, the gain component630provides the nonlinear part gain scalar to the vector processor120-cand the nonlinear part gain scalar is applied to the nonlinear adjustments output signal by the vector processor120-cor another component of vectoring card651.

At block850, summer525-aof vectoring card651sums the gain-applied tone data output signal and the nonlinear part gain-applied nonlinear adjustments output signal. In this manner, by reducing the number of bits to represent the tone data signal, the nonlinear adjustments signal can be processed in parallel (e.g., by employing concurrent or alternating computations techniques) using extra or freed vector processing resource of the vector processor120-c. Similar techniques with the same (or lesser) bit precision as used with respect to the tone data signal can be applied in processing the nonlinear adjustments signal by partitioning vector processing resource or components. Accordingly, a lossless (or near lossless) tone data signal (e.g., y[q, t]) that includes nonlinear adjustments can be transported with reduced bit precision and bandwidth by reusing the extra or freed vector processing resources.

Information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.