Method for fabricating semiconductor layer having textured surface and method for fabricating solar cell

The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority from Taiwan Patent Application Serial No. 101105045, filed on Feb. 16, 2012, the entirety of which is incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to a method for fabricating a semiconductor layer having a textured surface and method for fabricating a solar cell.

BACKGROUND

In order to reduce the production costs of solar cells, thin wafer technology has been developed. Currently, a thin wafer is formed by cutting the wafer. However, thin wafers are easily broken during the cutting process. The thin wafer is then assembled into the cell, and it is a challenge to avoid the thin wafer from becoming damaged during the assembly process.

Additionally, because the surfaces of the thin wafer are smooth, the thin wafer having a textured surface is formed by dry etching process, not by wet etching process. Therefore, there is a need to develop a thin wafer having a textured surface for usage in solar cell.

SUMMARY

The disclosure provides a method for fabricating a semiconductor layer having a textured surface, comprising: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.

The disclosure also provides a method for fabricating a solar cell, comprising: (a-2) providing a textured substrate; (b-2) forming at least one silicon layer on the textured substrate; (c-2) forming a metal layer on the silicon layer; (d-2) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the silicon layer is separated from the textured substrate by the thermal process to obtain the silicon layer having the metal layer and a textured surface; (e-2) forming an anti-reflection layer on the silicon layer having a textured surface; and (f-2) forming an electrode layer on the anti-reflection layer.

DETAILED DESCRIPTION

The following description is of the embodiments of carrying out the disclosure This description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims.

Referring toFIG. 1A-1F, the disclosure provides a method for fabricating a semiconductor layer having a textured surface The method comprises steps (a)-(d).

Firstly, referring toFIG. 1A, a textured substrate102is provided. The substrate102comprises heat resistance materials. The substrate102comprises sapphire, quartz, silicon carbide (SiC) or oxide crystalline. The patterns of the textured substrate102may be regular or irregular patterns, such as pyramid, inverted pyramid or porous etc . . .

In one embodiment, the sapphire is used as the textured substrate102, and a textured sapphire substrate is obtained by a patterned process (lithography process).

Referring toFIG. 1B, the method continues in step (b), wherein at least one semiconductor layer104is formed on the textured substrate102. The semiconductor layer104comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium nitride (InN), indium phosphide (InP) or combinations thereof. The silicon comprises multi-crystalline silicon, single crystalline silicon or micro-crystalline silicon.

Note that the semiconductor layer104may be a single layer or multi-layers which may be adjusted by those skilled in the art according to the actual application.

The semiconductor layer104is formed by a chemical vapor deposition method (CVD), physical vapor deposition method (PVD) or molecular beam epitaxy (MBE).

Additionally, before step (c), the method further comprises performing a doping step to the semiconductor layer104.

In one embodiment, a P-type silicon is formed by doping with a P-type dopant. The P-type dopant comprises boron (B), aluminum (Al), geranium (Ge) indium (In), etc . . .

In another embodiment, an N-type silicon is formed by doping with an N-type dopant. The N-type dopant comprises phosphorus (P), arsenic (As), antimony (Sb), etc . . .

Referring toFIG. 1C, the method continues in step (c), wherein a metal layer106is formed on the semiconductor layer104. The metal layer106comprises gold, aluminum, silver or combinations thereof.

The metal layer106is formed by a coating method, printing method, electroplating method or physical vapor deposition method (PVD).

Referring toFIG. 1D, the method continues in step (d), wherein a thermal process is conducted on the textured substrate102, the semiconductor layer104and the metal layer106, wherein the semiconductor layer104is separated from the textured substrate102by the thermal process to obtain the semiconductor layer104ahaving the metal layer106and a textured surface.

The thermal process in an embodiment is conducted at a temperature of about 200-1000° C., and in another embodiment about 250-550° C. The thermal process in an embodiment is conducted for about 10-60 minutes, and in another embodiment about 15-30 minutes.

Referring toFIG. 1E, the method continues in step (e), wherein the semiconductor layer104ahaving a textured surface is formed on the metal layer106, in one embodiment, the semiconductor layer104ahaving textured surface has a thickness of about 1-100 μm, and in another embodiment the semiconductor layer104ahaving textured surface has a thickness of about 2-50 μm.

Note that the metal layer106and the semiconductor layer104are bonded tightly by the thermal process. A deformation stress is produced in the metal layer106due to the difference of thermal expansion coefficients between the metal layer106and the textured substrate102. Thus, the semiconductor layer104is separated from the textured substrate102by the thermal process and the semiconductor layer104ahaving a thin and textured surface is obtained.

Furthermore, referring toFIG. 2A-2G, the disclosure provides a method for fabricating a solar cell. The method comprises step (a-2)-(f-2).

Firstly, a textured substrate202is provided .The material of the textured substrate202is the same as that of the textured substrate102, and thus is omitted.

Referring toFIG. 2B, the method continues in step (b-2), wherein at least one first silicon layer204is formed on the textured substrate202. The silicon layer204comprises multi-crystalline silicon, single crystalline silicon or micro-crystalline silicon.

In one embodiment, a single first silicon layer204may be formed, and the first silicon layer204may be a doped silicon layer, such as a P-type or N-type silicon layer. The P-type silicon layer is formed by doping boron (B), aluminum (Al), geranium (Ge), indium (In), etc . . . The N-type silicon layer is formed by doping phosphorus (P), arsenic (As), antimony (Sb), etc . . .

Referring toFIG. 2C(optional), a second silicon layer may be formed. The second silicon layer206of a different doped type is formed on the first silicon layer204. For example, a P-type first silicon layer204is firstly formed, and then a second, N-type silicon layer206is formed on the P-type first silicon layer204.

Note that althoughFIG. 2B-2Cshows two silicon layers, multi-layers may also be formed by those skilled in the art according to the actual application.

Referring toFIG. 2D, the method continues in step (c-2), wherein a metal layer208is formed on the first silicon layer204and the second silicon layer206. If the second silicon layer206is not formed (FIG. 2Cis not performed), the metal layer208is only formed on the first silicon layer204. The material and fabrication method of the metal layer208are described above, and thus are omitted.

Referring toFIG. 2E, the method continues in step (d-2), wherein a thermal process is conducted on the textured substrate202, the first silicon layer204and second silicon layer206, and the metal layer208, wherein the first silicon layer204and the second silicon layer206is separated from the textured substrate202by the thermal process to obtain a first silicon layer204ahaving the metal layer208and a textured surface.

The thermal process is conducted at a temperature of about 200-1000° C., and in another embodiment the thermal process is conducted at a temperature of about 250-600° C. The thermal process in an embodiment is conducted for about 10-60 minutes, and in another embodiment, the thermal process is conducted for about 15-30 minutes

Then, referringFIG. 2F, the method continues in step (e-2), wherein an anti-reflection layer (ARC)210is formed on the first silicon layer204ahaving a textured surface. The anti-reflection layer (ARC)210is a dielectric material which comprises silicon nitride (SiN), silicon dioxide (SiO2), titanium dioxide (TiO2) or tantalum oxide (Ta2O5). The anti-reflection layer (ARC)210is formed by plasma enhanced chemical vapor deposition, (PECVD), low pressure chemical vapor deposition (LPCVD), ink jet printing or coating method.

Referring toFIG. 2G, the method continues in step (f-2), wherein an electrode layer212is formed on the anti-reflection layer (ARC)210. The electrode layer212comprises aluminum, silver or combinations thereof. Thus, a thin solar cell20having a thickness of about 1-100 μm and in another embodiment having a thickness of about 2-50 μm is obtained. The electrode layer212is formed by a coating method, printing method, electroplating method or physical vapor deposition method (PVD).

In addition to being used in the solar-cell field, the method for fabricating a semiconductor layer having a textured surface of the disclosure may be used in other semiconductor fabrication processes.

EXAMPLE

Firstly, a textured sapphire substrate was providedFIG. 3shows a scanning electron microscopy (SEM) image of the textured substrate. As shown inFIG. 3, the textured sapphire substrate had regular patterns.

Then, a conductive silver glue (Dupont PV-159) was coated on the micro-crystalline silicon layer. Next, the textured sapphire substrate was put in an oven about at 600° C. for 30 minutes, and the micro-crystalline silicon layer was separated from the textured substrate by the thermal process. Thus, the conductive silver glue having a thin and textured silicon layer having a thickness of about 1-100 μm, and in another embodiment having a thickness of about 2-50 μm.FIG. 4shows a scanning electron microscopy (SEM) image of the silicon layer having a textured surface.

The experimental condition of Example 2 was the same as that of Example 1, except that a different type of conductive silver glue (Dupont PV-412) was coated on the micro-crystalline silicon layer. Then, the textured sapphire substrate was put in an oven at 250° C. for 10 minutes, and the micro-crystalline silicon layer was separated from the textured sapphire substrate by the thermal process. Thus, the conductive silver glue has a thin and textured silicon layer having a thickness of about 1-100 μm, and in another embodiment having a thickness of about 2-50 μm.

Fabricating the Solar Cell

A silicon nitride anti-reflection layer was coated on the thin and textured silicon layer of Example 1. Then, a silver layer was formed on the silicon nitride anti-reflection layer by an electroplating method. Thus, a solar cell was obtained The conductive silver glue was used as a back contact, and the silver layer was used as a front contact.

A 3 μm micro-crystalline silicon layer was formed on the textured sapphire substrate by plasma enhanced chemical vapor deposition (PECVD) (the experimental conditions was the same as Example 1).

Then, a conductive silver glue (Dupont PV-412) was coated on the Ge0.1Si0.9alloy layer. Next, the textured sapphire substrate was put in an oven about at 250° C. for 10 minutes, and the two-layered semiconductor layer (the first layer is a micro-crystalline silicon layer and the second layer is a Ge0.1Si0.9alloy layer) was separated from the textured sapphire substrate by the thermal process. Thus, the conductive silver glue having a textured semiconductor layer.

The experimental condition of Example 5 was the same as that of Example 1, except that the germanium (Ge) multi-crystalline silicon was formed by a solution growth method. A 100 μm germanium multi-crystalline silicon layer was formed on the sapphire substrate about at a temperature of 950° C. and a pressure of 760 torr.

Then, a conductive silver glue (Dupont PV-159) was coated on the germanium multi-crystalline silicon layer. Next, the textured sapphire substrate was put in an oven about at 550° C. for 30 minutes, and the germanium multi-crystalline silicon layer was separated from the textured sapphire substrate by the thermal process. Thus, the conductive silver glue having a textured silicon layer.