Semiconductor integrated circuit and method of manufacturing the same

Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.

This application is based on Japanese patent application No. 2005-349011, the content of which is incorporated hereinto by reference.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same.

2. Related Art

An example of semiconductor integrated circuits so far developed can be found in Japanese Laid-open patent publication No. 2004-55954. In the semiconductor integrated circuit according to this document, a capacitor is provided as a fill-cell capacitance in a region where a functional cell (logic gate cell) is not located.

Generally, the capacitor in the semiconductor integrated circuit is often constituted of a field effect transistor (hereinafter, FET). Specifically, electrically connecting the source terminal and drain terminal of the FET as shown inFIG. 5enables utilizing the gate electrode, the gate insulating layer and the channel region of the FET as the upper electrode, the capacitance insulating layer and the lower electrode capacitor of the capacitor, respectively. Here, the FET inFIG. 5is provided between a power source (VDD) and a ground (GND), so as to act as a decoupling capacitance.

Also, Japanese Laid-open patent publication No. 2001-44283 discloses a semiconductor integrated circuit including a fill-cell in which a fill-cell resistance is provided.

In the capacitor constituted of the FET, however, the path from the channel region (lower electrode) to the source/drain region has a high electrical resistance. This path is where a charge flowing into and out of the lower electrode runs through. The high electrical resistance in this path, therefore, leads to degradation in frequency response of the capacitor.

From the viewpoint of improving the frequency response, reducing the length of the gate electrode (gate length) would be a solution. In this case, however, the electrode area of the capacitor is inevitably reduced, which incurs another problem that the capacitance value is decreased.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a semiconductor integrated circuit comprising a semiconductor substrate, a field effect transistor, and a capacitor; wherein the field effect transistor includes a first impurity diffusion layer of a first conductive type provided in the semiconductor substrate and acting as a source/drain region, a first impurity-implanted region of a second conductive type provided in the semiconductor substrate and adjacent to the first impurity diffusion layer, and acting as a channel region, a gate insulating layer provided on the first impurity-implanted region in the semiconductor substrate, and a gate electrode provided on the gate insulating layer; and the capacitor includes a second impurity diffusion layer of the first or the second conductive type provided in the semiconductor substrate, a second impurity-implanted region of the same conductive type as the second impurity diffusion layer, provided in the semiconductor substrate and adjacent to the second impurity diffusion layer, and acting as a lower electrode, a capacitance insulating layer provided on the second impurity-implanted region of the semiconductor substrate, and an upper electrode provided on the capacitance insulating layer. Here, the first conductive type and the second conductive type are mutually opposite conductive types, and one is N-type and the other is P-type.

In the semiconductor integrated circuit thus constructed, the conductive type of the second impurity diffusion layer and that of the second impurity-implanted region acting as the lower electrode are the same. Under such configuration, electrical resistance of a path from the second impurity-implanted region to the second impurity diffusion layer is smaller, compared with the case where the conductive type is different. Consequently, the capacitor attains superior frequency response.

According to the present invention, there is also provided a method of manufacturing a semiconductor integrated circuit including a semiconductor substrate, a field effect transistor and a capacitor, comprising forming a first impurity diffusion layer of a first conductive type in the semiconductor substrate, thus constituting a source/drain region; forming a first impurity-implanted region of a second conductive type in the semiconductor substrate and adjacent to the first impurity diffusion layer, thus constituting a channel region; forming a gate insulating layer on the first impurity-implanted region in the semiconductor substrate; forming a gate electrode on the gate insulating layer; forming a second impurity diffusion layer of the first or the second conductive type in the semiconductor substrate; forming a second impurity-implanted region of the same conductive type as the second impurity diffusion layer, in the semiconductor substrate and adjacent to the second impurity diffusion layer, thus constituting a lower electrode; forming a capacitance insulating layer on the second impurity-implanted region of the semiconductor substrate, and forming an upper electrode on the capacitance insulating layer.

By the method thus arranged, the second impurity diffusion layer and the second impurity-implanted region of the same conductive type are provided. Because of such arrangement, electrical resistance of a path from the second impurity-implanted region to the second impurity diffusion layer is smaller, compared with the case where the conductive type is different. Consequently, the capacitor attains superior frequency response.

Thus, the present invention provides a semiconductor integrated circuit including a capacitor that offers excellent frequency response performance, and a method of manufacturing such semiconductor integrated circuit.

DETAILED DESCRIPTION

Hereunder, exemplary embodiments of a semiconductor integrated circuit and a method of manufacturing the same according to the present invention will be described in details, referring to the accompanying drawings. In the drawings, same constituents are given the same numerals, and the description thereof will not be repeated.

First Embodiment

FIG. 1is a cross-sectional view showing the semiconductor integrated circuit according to a first embodiment of the present invention. The semiconductor integrated circuit1includes a semiconductor substrate90, an N-type FET10, a P-type FET20, and capacitors30,40. The semiconductor substrate90is, for example, a silicon substrate.

The N-type FET10includes N-type impurity diffusion layers12,13, a P-type impurity-implanted region14, a gate insulating layer15, and a gate electrode16. The N-type impurity diffusion layers12,13are provided in the semiconductor substrate90, and serve as the source/drain region of the N-type FET10. Out of the N-type impurity diffusion layers12,13, the N-type impurity diffusion layer13corresponds to a Lightly Doped Drain (hereinafter, LDD) region. In the semiconductor substrate90, the P-type impurity-implanted region14is provided adjacent to the N-type impurity diffusion layer13. The P-type impurity-implanted region14serves as the channel region of the N-type FET10. The N-type impurity diffusion layers12,13and the P-type impurity-implanted region14are located in a P-type well region11in the semiconductor substrate90.

On the P-type impurity-implanted region14in the semiconductor substrate90, the gate insulating layer15is provided. On the gate insulating layer15, the gate electrode16is provided. The gate insulating layer15and the gate electrode16are constituted of, for instance, silicon oxide and polysilicon respectively. Further on a lateral face of the gate electrode16, a sidewall18is provided.

The P-type FET20includes P-type impurity diffusion layers22,23, an N-type impurity-implanted region24, a gate insulating layer25, and a gate electrode26. The P-type impurity diffusion layers22,23are provided in the semiconductor substrate90, and serve as the source/drain region of the P-type FET20. Out of the P-type impurity diffusion layers22,23, the P-type impurity diffusion layer23corresponds to a LDD region. In the semiconductor substrate90, an N-type impurity-implanted region24is provided adjacent to the P-type impurity diffusion layer23. The N-type impurity-implanted region24serves as the channel region of the P-type FET20. The P-type impurity diffusion layers22,23and the N-type impurity-implanted region24are located in an N-type well region21in the semiconductor substrate90.

On the N-type impurity-implanted region24in the semiconductor substrate90, the gate insulating layer25is provided. On the gate insulating layer25, the gate electrode26is provided. The gate insulating layer25and the gate electrode26are constituted of the same material as the gate insulating layer15and the gate electrode16. Further on a lateral face of the gate electrode26, a sidewall28is provided.

The capacitor30includes N-type impurity diffusion layers32,33, an N-type impurity-implanted region34, a capacitance insulating layer35, and an upper electrode36. The N-type impurity diffusion layers32,33are located in the semiconductor substrate90. The N-type impurity diffusion layers32,33constitute a path for a charge flowing into the N-type impurity-implanted region34(or flowing out of the N-type impurity-implanted region34). In this embodiment, the N-type impurity diffusion layer32and the N-type impurity diffusion layer33have generally the same impurity concentration profile as the N-type impurity diffusion layer12and the N-type impurity diffusion layer13of the N-type FET10, respectively.

In the semiconductor substrate90, the N-type impurity-implanted region34is provided adjacent to the N-type impurity diffusion layer33. The N-type impurity-implanted region34serves as the lower electrode of the capacitor30. Also, the conductive type of the N-type impurity-implanted region34is the same as that of the N-type impurity diffusion layers32,33. In this embodiment, the N-type impurity-implanted region34has generally the same impurity concentration profile as the N-type impurity-implanted region24of the P-type FET20. The N-type impurity diffusion layers32,33and the N-type impurity-implanted region34are located in a P-type well region31in the semiconductor substrate90. Here, the P-type well region31may be integrally formed with the P-type well region11.

On the N-type impurity-implanted region34in the semiconductor substrate90, the capacitance insulating layer35is provided. On the capacitance insulating layer35, the upper electrode36is provided. The capacitance insulating layer35is constituted of the same material as the gate insulating layers15,25. Also, the capacitance insulating layer35has generally the same thickness as the gate insulating layers15,25. Likewise, the upper electrode36is constituted of the same material as the gate electrodes16,26. Also, the upper electrode36has generally the same thickness as the gate electrodes16,26. Further, on a lateral face of the upper electrode36, a sidewall38is provided.

The capacitor40includes P-type impurity diffusion layers42,43, a P-type impurity-implanted region44, a capacitance insulating layer45, and an upper electrode46. The P-type impurity diffusion layers42,43are located in the semiconductor substrate90. The P-type impurity diffusion layers42,43constitute a path for a charge flowing into the P-type impurity-implanted region44(or flowing out of the P-type impurity-implanted region44). In this embodiment, the P-type impurity diffusion layer42and the P-type impurity diffusion layer43have generally the same impurity concentration profile as the P-type impurity diffusion layer22and the P-type impurity diffusion layer23of the P-type FET20, respectively.

In the semiconductor substrate90, the P-type impurity-implanted region44is provided adjacent to the P-type impurity diffusion layer43. The P-type impurity-implanted region44serves as the lower electrode of the capacitor40. Also, the conductive type of the P-type impurity-implanted region44is the same as that of the P-type impurity diffusion layers42,43. In this embodiment, the P-type impurity-implanted region44has generally the same impurity concentration profile as the P-type impurity-implanted region14of the N-type FET10. The P-type impurity diffusion layers42,43and the P-type impurity-implanted region44are located in an N-type well region41in the semiconductor substrate90. Here, the N-type well region41may be integrally formed with the N-type well region21.

On the P-type impurity-implanted region44in the semiconductor substrate90, the capacitance insulating layer45is provided. On the capacitance insulating layer45, the upper electrode46is provided. The capacitance insulating layer45is constituted of the same material as the gate insulating layers15,25. Also, the capacitance insulating layer45has generally the same thickness as the gate insulating layers15,25. Likewise, the upper electrode46is constituted of the same material as the gate electrodes16,26. Also, the upper electrode46has generally the same thickness as the gate electrodes16,26. Further, on a lateral face of the upper electrode46, a sidewall48is provided.

It should be noted that although the N-type impurity diffusion layers32,33are provided on both sides of the N-type impurity-implanted region34in the capacitor30, the N-type impurity diffusion layers32,33on one of the sides are electrically connected to the N-type impurity diffusion layers32,33on the other side, via an interconnect or the like not shown inFIG. 1. This is also the case with the P-type impurity diffusion layers42,43in the capacitor40.

The N-type FET10, the P-type FET20, the capacitor30and the capacitor40are isolated from one another by an isolation region92. The isolation region92is a Shallow Trench Isolation (STI) region, for example.

The N-type FET10, the P-type FET20, the capacitor30and the capacitor40are, for example, formed in a fill-cell.FIG. 2is a plan view showing the fill-cell. The fill-cell50includes functional cells52and capacitance fill-cells54. The capacitance fill-cells54are located so as to fill in a region in the fill-cell50where the functional cells52are not provided. Here, the N-type FET10and the P-type FET20may be employed as the FETs constituting the functional cells52, and the capacitor30and the capacitor40may be employed as the fill-cell capacitance constituting the capacitance fill-cell54.

Also, in the fill-cell50, an N-type well region56and a P-type well region57are respectively disposed so as to extend along the alignment direction of the functional cells52(and the capacitance fill-cells54), i.e. in a left and right direction inFIG. 2. Accordingly, the N-type well region56and the P-type well region57are shared by all the functional cells52and the capacitance fill-cells54inFIG. 2. Likewise, a power source interconnect portion58and a ground interconnect portion59are also disposed so as to extend along the alignment direction, and thus shared by all the functional cells52and the capacitance fill-cells54inFIG. 2.

The capacitor30may be employed as a decoupling capacitance provided between the power source and the ground. In this case, a power source potential is applied to the upper electrode36, and a ground potential is applied to the N-type impurity-implanted region34via the N-type impurity diffusion layers32,33. Likewise, the capacitor40may also be employed as a decoupling capacitance provided between the power source and the ground. In this case, the ground potential is applied to the upper electrode46, and the power source potential is applied to the P-type impurity-implanted region44via the P-type impurity diffusion layers42,43. Alternatively, the capacitors30,40may be utilized as a variable capacitance. In this case, changing the potential to be applied to the upper electrodes36,46allows controlling the capacitance to a desired value.

The following passages describe a manufacturing method of the semiconductor integrated circuit1, as an embodiment of the method of manufacturing a semiconductor integrated circuit according to the present invention. The manufacturing method according to this embodiment is for manufacturing the semiconductor integrated circuit1including the semiconductor substrate90, the N-type FET10, the P-type FET20, and the capacitors30,40, and includes the following steps (a) to (h).

(c) forming the gate insulating layer15and the gate insulating layer25, respectively on the P-type impurity-implanted region14and the N-type impurity-implanted region24in the semiconductor substrate90;

(d) forming the gate electrode16and the gate electrode26on the gate insulating layer15and the gate insulating layer25respectively;

(g) forming the capacitance insulating layer35and the capacitance insulating layer45respectively on the N-type impurity-implanted region34and the P-type impurity-implanted region44in the semiconductor substrate90; and

(h) forming the upper electrode36and the upper electrode46on the capacitance insulating layer35and the capacitance insulating layer45, respectively.

In this embodiment, the N-type impurity diffusion layer32and the N-type impurity diffusion layer33are formed with the N-type impurity diffusion layer12and the N-type impurity diffusion layer13respectively, at a time. Likewise, the P-type impurity diffusion layer42and the P-type impurity diffusion layer43are formed with the P-type impurity diffusion layer22and the P-type impurity diffusion layer23respectively, at a time. Also, the N-type impurity-implanted region34is formed with the N-type impurity-implanted region24at a time. Likewise, the P-type impurity-implanted region44is formed with the P-type impurity-implanted region14at a time. Further, the gate insulating layer15, the gate insulating layer25, the capacitance insulating layer35, and the capacitance insulating layer45are formed at a time. The gate electrode16, the gate electrode26, the upper electrode36and the upper electrode46are also formed at a time. Likewise, the P-type well region31and the N-type well region41are formed with the P-type well region11and the N-type well region21respectively, at a time.

In other words, the capacitor30shares the process of forming the N-type impurity-implanted region34with the P-type FET20, and the remaining processes with the N-type FET10. Likewise, the capacitor40shares the process of forming the P-type impurity-implanted region44with the N-type FET10, and the remaining processes with the P-type FET20.

The foregoing embodiment offers the following advantageous effects. In this embodiment, the conductive type of the N-type impurity diffusion layers32,33and that of the N-type impurity-implanted region34are the same. Because of such configuration, electrical resistance of a path from the N-type impurity-implanted region34to the N-type impurity diffusion layers32,33is smaller, compared with the case where the conductive type is different. Consequently, the capacitor30attains superior frequency response. Likewise, since the P-type impurity diffusion layers42,43and the P-type impurity-implanted region44are of the same conductive type, the capacitor40attains superior frequency response. Thus, according to the foregoing embodiment, the semiconductor integrated circuit1attains the capacitors30,40which offer excellent frequency response performance, and the method of manufacturing such semiconductor integrated circuit is also achieved.

Also, in the capacitor30the N-type impurity-implanted region34serves as the lower electrode. Such configuration allows forming the N-type impurity-implanted region34with the N-type impurity-implanted region24of the P-type FET20at a time. Accordingly, the capacitor30which provides excellent frequency response performance can be obtained without any increase in number of manufacturing steps. In this embodiment actually, the N-type impurity-implanted region24and the N-type impurity-implanted region34are formed at a time, and hence these regions have generally the same impurity concentration profile.

Likewise, in the capacitor40also, the P-type impurity-implanted region44serves as the lower electrode. Such configuration allows forming the P-type impurity-implanted region44with the P-type impurity-implanted region14of the N-type FET10at a time. Accordingly, the capacitor40which provides excellent frequency response performance can be obtained without any increase in number of manufacturing steps. In this embodiment actually, the P-type impurity-implanted region14and the P-type impurity-implanted region44are formed at a time, and hence these regions have generally the same impurity concentration profile.

The capacitance insulating layers35,45are formed with the gate insulating layer15,25at a time. As a result, the capacitance insulating layers35,45are constituted of the identical material to that of the gate insulating layers15,25, and have generally the same thickness as the gate insulating layers15,25. Such arrangement suppresses an increase in number of manufacturing steps of the capacitors30,40.

The upper electrodes36,46are formed with the gate electrodes16,26at a time. As a result, the upper electrodes36,46are constituted of the identical material to that of the gate electrodes16,26, and have generally the same thickness as the gate electrodes16,26. Such arrangement suppresses an increase in number of manufacturing steps of the capacitors30,40.

Employing the capacitors30,40as a decoupling capacitance allows effectively reducing an Electromagnetic Interference (EMI) noise. Recently, the issue of the Electro Magnetic Compatibility (EMC) has come to be focused on even in designing a system or apparatus, and a printed circuit board. Accordingly, remedies against the EMI are becoming more important in semiconductor integrated circuits such as an LSI. Further, the decoupling capacitance is effective as a remedy against a power source noise (IR-drop) in a chip, not only against the EMI noise.

Especially, employing the capacitors30,40as a fill-cell capacitance enables efficiently utilizing the space on the semiconductor substrate90, thereby facilitating suppressing the EMI noise without incurring an increase in footprint of the chip.

Second Embodiment

FIG. 3is a cross-sectional view showing a semiconductor integrated circuit according to a second embodiment of the present invention. The semiconductor integrated circuit2includes a semiconductor substrate90, an N-type FET10, a P-type FET20, and capacitors60,70. Among these constituents, the semiconductor substrate90, the N-type FET10and the P-type FET20are constructed as described referring toFIG. 1.

The capacitor60includes N-type impurity diffusion layers62,63, an N-type impurity-implanted region64, a capacitance insulating layer65, and an upper electrode66. The N-type impurity diffusion layers62,63are located in the semiconductor substrate-90. The N-type impurity diffusion layers62,63constitute a path for a charge flowing into the N-type impurity-implanted region64(or flowing out of the N-type impurity-implanted region64). In this embodiment, the N-type impurity diffusion layer62and the N-type impurity diffusion layer63have generally the same impurity concentration profile as the N-type impurity diffusion layer12and the N-type impurity diffusion layer13of the N-type FET10, respectively.

In the semiconductor substrate90, the N-type impurity-implanted region64is provided adjacent to the N-type impurity diffusion layer63. The N-type impurity-implanted region64serves as the lower electrode of the capacitor60. Also, the conductive type of the N-type impurity-implanted region64is the same as that of the N-type impurity diffusion layers62,63. In this embodiment, the N-type impurity-implanted region64has generally the same impurity concentration profile as the N-type impurity-implanted region24of the P-type FET20. The N-type impurity diffusion layers62,63and the N-type impurity-implanted region64are located in an N-type well region61in the semiconductor substrate90. Here, the N-type well region61may be integrally formed with an N-type well region21.

On the N-type impurity-implanted region64in the semiconductor substrate90, the capacitance insulating layer65is provided. On the capacitance insulating layer65, the upper electrode66is provided. The capacitance insulating layer65is constituted of the same material as the gate insulating layers15,25. Also, the capacitance insulating layer65has generally the same thickness as the gate insulating layers15,25. Likewise, the upper electrode66is constituted of the same material as the gate electrodes16,26. Also, the upper electrode66has generally the same thickness as the gate electrodes16,26. Further, on a lateral face of the upper electrode66, a sidewall68is provided.

The capacitor70includes P-type impurity diffusion layers72,73, a P-type impurity-implanted region74, a capacitance insulating layer75, and an upper electrode76. The P-type impurity diffusion layers72,73are located in the semiconductor substrate90. The P-type impurity diffusion layers72,73constitute a path for a charge flowing into the P-type impurity-implanted region74(or flowing out of the P-type impurity-implanted region74). In this embodiment, the P-type impurity diffusion layer72and the P-type impurity diffusion layer73have generally the same impurity concentration profile as the P-type impurity diffusion layer22and the P-type impurity diffusion layer23of the P-type FET20, respectively.

In the semiconductor substrate90, the P-type impurity-implanted region74is provided adjacent to the P-type impurity diffusion layer73. The P-type impurity-implanted region74serves as the lower electrode of the capacitor70. Also, the conductive type of the P-type impurity-implanted region74is the same as that of the P-type impurity diffusion layers72,73. In this embodiment, the P-type impurity-implanted region74has generally the same impurity concentration profile as the P-type impurity-implanted region14of the N-type FET10. The P-type impurity diffusion layers72,73and the P-type impurity-implanted region74are located in a P-type well region71in the semiconductor substrate90. Here, the P-type well region71may be integrally formed with the P-type well region11.

On the P-type impurity-implanted region74in the semiconductor substrate90, the capacitance insulating layer75is provided. On the capacitance insulating layer75, the upper electrode76is provided. The capacitance insulating layer75is constituted of the same material as the gate insulating layers15,25. Also, the capacitance insulating layer75has generally the same thickness as the gate insulating layers15,25. Likewise, the upper electrode76is constituted of the same material as the gate electrodes16,26. Also, the upper electrode76has generally the same thickness as the gate electrodes16,26. Further, on a lateral face of the upper electrode76, a sidewall78is provided.

Although the N-type impurity diffusion layers62,63are provided on both sides of the N-type impurity-implanted region64in the capacitor60, the N-type impurity diffusion layers62,63on one of the sides are electrically connected to the N-type impurity diffusion layers62,63on the other side, via an interconnect or the like not shown inFIG. 3. This is also the case with the P-type impurity diffusion layers72,73in the capacitor70. The N-type FET10, the P-type FET20, the capacitor60and the capacitor70are isolated from one another by an isolation region92.

The semiconductor integrated circuit2thus constructed may be manufactured through similar processes to those for the semiconductor integrated circuit1shown inFIG. 1. In other words, the capacitor60may share the process of forming the N-type impurity diffusion layers62,63with the N-type FET10, and the remaining processes with the P-type FET20. Likewise, the capacitor70may share the process of forming the P-type impurity diffusion layers72,73with the P-type FET20, and the remaining processes with the N-type FET10.

The foregoing embodiment offers the following advantageous effects. In this embodiment, the conductive type of the N-type impurity diffusion layers62,63and that of the N-type impurity-implanted region64are the same. Because of such configuration, electrical resistance of a path from the N-type impurity-implanted region64to the N-type impurity diffusion layers62,63is smaller, compared with the case where the conductive type is different. Consequently, the capacitor60attains superior frequency response. Likewise, since the P-type impurity diffusion layers72,73and the P-type impurity-implanted region74are of the same conductive type, the capacitor70attains superior frequency response. Thus, according to the foregoing embodiment, the semiconductor integrated circuit2attains the capacitors60,70which offer excellent frequency response performance, and the method of manufacturing such semiconductor integrated circuit is also achieved.

Also, in the capacitor60, the N-type impurity diffusion layers62,63can be formed with the N-type impurity diffusion layer12,13of the N-type FET10at a time. Accordingly, the capacitor60which provides excellent frequency response performance can be obtained without any increase in number of manufacturing steps. In this embodiment actually, the N-type impurity diffusion layer12and the N-type impurity diffusion layer62are formed at a time, and hence these regions have generally the same impurity concentration profile. The N-type impurity diffusion layer13and the N-type impurity diffusion layer63are also formed at a time, and hence these layers have generally the same impurity concentration profile.

Likewise, in the capacitor70also, the P-type impurity diffusion layers72,73can be formed with the P-type impurity diffusion layers22,23of the P-type FET20at a time. Accordingly, the capacitor70which provides excellent frequency response performance can be obtained without any increase in number of manufacturing steps. In this embodiment actually, the P-type impurity diffusion layer22and the P-type impurity diffusion layer72are formed at a time, and hence these regions have generally the same impurity concentration profile. The P-type impurity diffusion layer23and the P-type impurity diffusion layer73are also formed at a time, and hence these layers have generally the same impurity concentration profile.

Further, in this embodiment, the conductive type of the N-type well region61is the same as that of the N-type impurity diffusion layers62,63and the N-type impurity-implanted region64. Because of such configuration, the electrical resistance of the path from the N-type impurity-implanted region64to the N-type impurity diffusion layers62,63becomes still smaller. Likewise, since the P-type impurity diffusion layers72,73and the P-type impurity-implanted region74are of the same conductive type, the electrical resistance of the path from the P-type impurity-implanted region74to the P-type impurity diffusion layers72,73becomes still smaller.

The semiconductor integrated circuit and the method of manufacturing the same according to the present invention are not limited to the foregoing embodiments, but various modifications may be made. To cite a few examples, although the embodiments describe the integrated circuits including two types of capacitors, just one type of capacitor may be provided. More specifically, the semiconductor integrated circuit1shown inFIG. 1may include only either of the capacitor30or the capacitor40. Likewise, the semiconductor integrated circuit2shown inFIG. 3may include only either of the capacitor60or the capacitor70.

Also, although in the capacitor30the conductive type of the N-type impurity diffusion layer33is assumed to be the same as that of the N-type impurity diffusion layer32according to the embodiments, the conductive type of the N-type impurity diffusion layer33may be opposite to that of the N-type impurity diffusion layer32(and the N-type impurity-implanted region34), as long as the N-type impurity diffusion layer32and the N-type impurity-implanted region34are of the same conductive type. This also applies to the capacitors40,60,70.

Further, although in the capacitor30the N-type impurity diffusion layers32,33are provided on both sides of the N-type impurity-implanted region34according to the embodiments, the N-type impurity diffusion layers32,33may only be provided on either side of the N-type impurity-implanted region34as shown inFIG. 4. This also applies to the capacitors40,60,70.