Systems, apparatuses, and methods for implementing a fastpath microcode sequencer are disclosed. A processor includes at least an instruction decode unit and first and second microcode units. For each received instruction, the instruction decode unit forwards the instruction to the first microcode unit if the instruction satisfies at least a first condition. In one implementation, the first condition is the instruction being classified as a frequently executed instruction. If a received instruction satisfies at least a second condition, the instruction decode unit forwards the received instruction to a second microcode unit. In one implementation, the first microcode unit is a smaller, faster structure than the second microcode unit. In one implementation, the second condition is the instruction being classified as an infrequently executed instruction. In other implementations, the instruction decode unit forwards the instruction to another microcode unit responsive to determining the instruction satisfies one or more other conditions.

BACKGROUND

Description of the Related Art

Processors typically rely on microcode sequencers to decode complex instructions into a series of simplified operations (or “ops”). As used herein, the term “microcode” is defined as a plurality of ops. It is noted that ops can also be referred to as micro-ops (or μops). Ops are typically fetched from a microcode storage unit, which is implemented in some processors as a large read-only memory (ROM) or random-access memory (RAM). In some processors, an instruction decode unit generates an initial address from a fetched instruction, and the initial address serves as an entry point into the microcode storage unit. Ops can be followed by an address of the next op or an indication that the last op has been reached if the op is the end of the microcode sequence for the fetched instruction.

To implement instructions requiring more than just a few ops, processors use sequences of ops that are read from the microcode storage unit. This access is relatively slow and introduces stall cycles into the processor pipeline. Accordingly, techniques to reduce the performance impact of slow microcode sequence access times are desired.

DETAILED DESCRIPTION OF IMPLEMENTATIONS

Various systems, apparatuses, and methods for implementing a fastpath microcode sequencer are disclosed herein. A system includes one or more processors coupled to one or more memories. Each processor includes a processor pipeline with a plurality of pipeline stages for fetching, processing, and executing instructions. Instructions are fetched and then conveyed to an instruction decode unit. For each received instruction, the instruction decode unit forwards the instruction to a first microcode unit responsive to determining the instruction satisfies at least a first condition. In one implementation, the first condition is the instruction being classified as a frequently executed instruction. If a received instruction satisfies at least a second condition, the instruction decode unit forwards the received instruction to a second microcode unit. In one implementation, the second condition is the instruction being classified as an infrequently executed instruction. In one implementation, the first microcode unit is a smaller, faster structure than the second microcode unit. In other implementations, the instruction decode unit forwards the instruction to another microcode unit responsive to determining the instruction satisfies one or more other conditions.

In another implementation, the instruction decode unit forwards a received instruction to the first microcode unit responsive to determining the instruction satisfies at least the first condition and a third condition. In one implementation, the third condition is the instruction mapping to a number of ops which is less than a threshold. Also, in another implementation, the instruction decode unit forwards a received instruction to the second microcode unit responsive to determining the instruction satisfies at least the second condition and a fourth condition. In one implementation, the fourth condition is the instruction mapping to a number of ops which is greater than or equal to the threshold.

Referring now toFIG. 1, a block diagram of one implementation of a computing system100is shown. In one implementation, computing system100includes at least processors105A-N, input/output (I/O) interfaces120, bus125, memory controller(s)130, network interface135, and memory device(s)140. In other implementations, computing system100includes other components and/or computing system100is arranged differently. Processors105A-N are representative of any number of processors which are included in system100.

In one implementation, processor105A is a general purpose processor, such as a central processing unit (CPU). In one implementation, processor105N is a data parallel processor with a highly parallel architecture. Data parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and so forth. In some implementations, processors105A-N include multiple data parallel processors.

Memory controller(s)130are representative of any number and type of memory controllers accessible by processors105A-N and I/O devices (not shown) coupled to I/O interfaces120. Memory controller(s)130are coupled to any number and type of memory devices(s)140. Memory device(s)140are representative of any number and type of memory devices. For example, the type of memory in memory device(s)140includes Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), NAND Flash memory, NOR flash memory, Ferroelectric Random Access Memory (FeRAM), or others.

I/O interfaces120are representative of any number and type of I/O interfaces (e.g., peripheral component interconnect (PCI) bus, PCI-Extended (PCI-X), PCIE (PCI Express) bus, gigabit Ethernet (GBE) bus, universal serial bus (USB)). Various types of peripheral devices (not shown) are coupled to I/O interfaces120. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth. Network interface135is used to receive and send network messages across a network.

In various implementations, computing system100is a computer, laptop, mobile device, game console, server, streaming device, wearable device, or any of various other types of computing systems or devices. It is noted that the number of components of computing system100varies from implementation to implementation. For example, in other implementations, there are more or fewer of each component than the number shown inFIG. 1. It is also noted that in other implementations, computing system100includes other components not shown inFIG. 1. Additionally, in other implementations, computing system100is structured in other ways than shown inFIG. 1.

Turning now toFIG. 2, a block diagram of one implementation of a processor pipeline200is shown. In various implementations, processors105A-N (ofFIG. 1) include one or more instantiations of processor pipeline200. In one implementation, processor pipeline200includes at least fetch unit210, decode unit215, dispatch unit220, queues225A-N, and execution units230A-N. It should be understood that processor pipeline200also includes other components (e.g., branch prediction unit, instruction cache) which are not shown to avoid obscuring the figure. In other implementations, processor pipeline200is structured in other suitable manners.

In one implementation, fetch unit210fetches instructions of a program stream from memory and/or an instruction cache, and fetch unit210conveys the fetched instructions to instruction decode unit215. Instruction decode unit215conveys fetched instructions to one of multiple microcode units where stored microcode sequences are retrieved for the fetched instructions. Each stored microcode sequence includes a plurality of instruction operations (or ops for short). It is noted that ops are also referred to as micro-ops or μops. Generally, an instruction operation is an operation that the hardware included in execution units230A-N is capable of executing. In various implementations, each instruction translates to one or more ops which, when executed, result in the performance of the operations defined for that instruction according to the instruction set architecture. Any type of instruction set architecture is employed by processor pipeline200.

In various implementations, multi-level microcode unit218includes multiple separate microcode units. In one implementation, multi-level microcode unit218includes two separate microcode units. In this implementation, multi-level microcode unit218includes a fast, small microcode unit which stores microcode sequences for frequently executed instructions. Additionally, in this implementation, multi-level microcode unit218includes a slow, large microcode unit (as compared to the fast, small microcode unit) which stores microcode sequences for infrequently executed instructions. In another implementation, multi-level microcode unit218includes three separate microcode units. In other implementations, multi-level microcode unit218includes other numbers of microcode units.

The ops from instruction decode unit215are provided to dispatch unit220, and dispatch unit assigns the ops to queues225A-N. As shown in processor pipeline200, each queue225A-N is coupled to a corresponding execution unit230A-N. However, in other implementations, one or more queues225A-N are coupled to multiple execution units230A-N. When the dependencies are resolved and the ops are ready to execute, pickers (not shown) will pick the ops out of queues225A-N to execute on the execution units230A-N.

Referring now toFIG. 3, a block diagram of one implementation of a portion of a processor pipeline300is shown. In one implementation, the portion of processor pipeline300is included within processor pipeline200. A fetch unit (not shown) fetches instructions from a cache and/or memory, and then the fetched operations are provided to instruction decode unit310. For each instruction, instruction decode unit310decides whether to forward the instruction on path315A or path315B depending on whether one or more conditions are met as discussed in greater detail below. Path315A connects to first microcode unit320while path315B connects to second microcode unit325. In one implementation, first microcode unit320is a smaller structure than second microcode unit325. Additionally, in one implementation, accesses to microcode in first microcode unit320are performed with less latency than accesses to microcode in second microcode unit325. The lower latency is achieved due to a shorter path315A as compared to path315B and/or due to faster logic for accessing the stored microcode sequences.

If instruction decode unit310conveys an instruction on path315A, the microcode sequence for this instruction is retrieved from a memory structure within first microcode unit320and conveyed to dispatch unit330. The microcode sequence includes one or more ops which are executable by one or more execution units to perform the operation(s) defined for that instruction. If instruction decode unit310conveys an instruction on path315B, the microcode sequence for this instruction is retrieved from a memory structure within second microcode unit325and conveyed to dispatch unit330. The ops of the microcode sequence are then dispatched by dispatch unit330to subsequent stages (not shown) of processor pipeline300.

Turning now toFIG. 4, a block diagram of one implementation of a multi-path microcode sequencer is shown. Sequencer400includes instruction decode unit405which receives instructions from an instruction stream. For each received instruction, instruction decode unit405determines on which path to send the instruction depending on which microcode sequencing unit should be used to generate microcode for the instruction. In one implementation, there are three paths for generating microcode for instructions of the instruction stream. In other implementations, there are other numbers of paths, such as four, five, six, and so on, for generating microcode for instructions of the instruction stream.

When instruction decode unit405determines that an instruction is able to be decoded by simple instruction decode unit440, then instruction decode unit405conveys the instruction on path408A to simple instruction decode unit440. Simple instruction decode unit440then decodes the instruction and generates microcode which is conveyed to a first input of multiplexer (or mux)445.

For frequently encountered instructions that do not map to simple microcode sequences, the microcode for these frequently encountered instructions is stored in small microcode structure435. In one implementation, small microcode structure435is implemented as a table. In another implementation, small microcode structure435is implemented using read-only memory (ROM). In other implementations, small microcode structure435is implemented using other types of memory structures. When instruction decode unit405determines that the instruction maps to microcode stored in small microcode structure435, instruction decode unit405generates the start address for the microcode sequence and conveys the start address on path408B to simple sequencing logic unit430. Simple sequencing logic unit430accesses small microcode structure435to retrieve the microcode corresponding to the instruction. Small microcode structure435also stores sequencing information which is fed back to simple sequencing logic unit430and used to generate subsequent addresses into small microcode structure435. When the entirety of the microcode sequence is retrieved, small microcode structure435conveys the microcode to a second input of mux445.

When instruction decode unit405determines that an instruction is a complex instruction and/or is an infrequently encountered instruction, instruction decode unit405generates and conveys the start address for the microcode sequence of the instruction on path408C to complex sequencing logic unit415. In one implementation, there is a delay410associated with sending the instruction on path408C to complex sequencing logic unit. Complex sequencing logic unit415conveys the start address for the microcode sequence to large microcode ROM420. It should be understood that in other implementations, large microcode ROM420is implemented using other types of structures. Large microcode ROM420feeds back sequencing information to complex sequencing logic unit415. The microcode sequence is conveyed from large microcode ROM420to a third input of mux445. In one implementation, there is a delay425associated with conveying the microcode sequence on the path from large microcode ROM420to mux445. Depending on which path408A-C the instruction traversed, mux445will pass the microcode sequence from the appropriate input through to the output of mux445. The output of mux445is coupled to subsequent pipeline stages (not shown).

Referring now toFIG. 5, one implementation of a method500for implementing a fastpath microcode sequencer is shown. For purposes of discussion, the steps in this implementation and those ofFIG. 6-8are shown in sequential order. However, it is noted that in various implementations of the described methods, one or more of the elements described are performed concurrently, in a different order than shown, or are omitted entirely. Other additional elements are also performed as desired. Any of the various systems or apparatuses described herein are configured to implement method500.

An instruction decode unit receives an instruction (block505). In one implementation, the instruction decode unit receives the instruction from an instruction fetch unit. In some implementations, the instruction decode unit receives multiple instructions from the instruction fetch unit per clock cycle. Next, the instruction decode unit determines if the instruction satisfies one or more conditions (block510).

Then, the instruction decode unit forwards the instruction to a first microcode unit responsive to determining that the instruction satisfies at least a first condition (block515). In one implementation, the first condition is the instruction being classified as a frequently executed instruction. In one implementation, the instruction decode unit dynamically determines whether the instruction is classified as a frequently executed instruction while in another implementation, the classification of the instruction as a frequently executed instruction is predetermined. In one implementation, an instruction is classified as a frequently executed instruction if the instruction is executed more than a threshold number of times in a given period of time. In another implementation, the instruction decode unit forwards the instruction to a first microcode unit responsive to determining that the instruction satisfies at least the first condition and responsive to determining that the instruction maps to a number of ops which is less than a threshold.

Alternatively, the instruction decode unit forwards the instruction to a second microcode unit responsive to determining that the instruction satisfies at least a second condition (block520). In one implementation, the second condition is the instruction being classified as an infrequently executed instruction. In one implementation, an instruction is classified as an infrequently executed instruction if the instruction is executed less than or equal to the threshold number of times in a given period of time. In one implementation, the first microcode unit is a smaller, faster structure than the second microcode unit. It is noted that in some implementations, instruction decode unit is coupled to other numbers of microcode units, and the instruction decode unit forwards the instruction to another microcode unit based on the instruction satisfying one or more other conditions. It is noted that in one implementation, method500is performed for each instruction received by the instruction decode unit.

Turning now toFIG. 6, another implementation of a method600for implementing a fastpath microcode sequencer is shown. An instruction decode unit receives an instruction (block605). Next, the instruction decode unit determines if the instruction satisfies one or more conditions (block610). Then, the instruction decode unit forwards the instruction to a first microcode unit responsive to determining that the instruction satisfies at least first and second conditions (block615). In one implementation, the first condition is the instruction being classified as a frequently executed instruction and the second condition is the instruction mapping to a number of ops which is less than a threshold. In other implementations, the first and second conditions are other types of conditions.

Alternatively, the instruction decode unit forwards the instruction to a second microcode unit responsive to determining that the instruction satisfies at least third and fourth conditions (block620). In one implementation, the third condition is the instruction being classified as an infrequently executed instruction and the fourth condition is the instruction mapping to a number of ops which is greater than or equal to the threshold. In other implementations, the third and fourth conditions are other types of conditions.

In one implementation, the first microcode unit is a smaller, faster structure than the second microcode unit. It is noted that in some implementations, the instruction decode unit is coupled to other numbers of microcode units, and the instruction decode unit forwards the instruction to another microcode unit based on the instruction satisfying one or more other conditions. It is noted that in one implementation, method600is performed for each instruction received by the instruction decode unit.

Referring now toFIG. 7, one implementation of a method700for implementing a multi-path microcode generation unit is shown. An instruction decode unit receives an instruction of a fetched instruction stream from a fetch unit (block705). The instruction decode unit determines which type of microcode generation technique to use when generating microcode for the instruction (block710). If the instruction decode unit determines that a first type of microcode generation technique should be used to generate microcode for the instruction (conditional block715, “first” leg), then the instruction decode unit sends the instruction on a first path to a simple decode structure (block720). In one implementation, the first type of microcode generation technique is used for instructions which map to simple microcode sequences. In one implementation, a “simple microcode sequence” is defined as a microcode sequence of one or two ops.

If the instruction decode unit determines that a second type of microcode generation technique should be used to generate microcode for the instruction (conditional block715, “second” leg), then the instruction decode unit sends the instruction on a second path to a relatively small, fast microcode structure (block725). In one implementation, the relatively small, fast microcode structure is implemented using a table. In one implementation, the second type of microcode generation technique is used for frequently executed instructions which map to microcode sequences of medium complexity. In one implementation, a “microcode sequence of medium complexity” is defined as a microcode sequence which maps to a given number of ops when the given number is greater than a first threshold but less than a second threshold. The values of the first and second thresholds vary according to the implementation.

Otherwise, if the instruction decode unit determines that a third type of microcode generation technique should be used to generate microcode for the instruction (conditional block715, “third” leg), then the instruction decode unit sends the instruction on a third path to a relatively large, slow microcode structure (block730). In one implementation, the relatively large, slow microcode structure is implemented using a ROM. In one implementation, sending the instruction on the third path results in a longer delay than sending the instruction on the second path. After blocks720,725, and730, microcode is retrieved from the corresponding structure on the selected path (block735). Then, the retrieved microcode is inserted into the decoded instruction sequence (block740). After block740, method700ends. It is noted that in one implementation, method700is performed for each instruction received by the instruction decode unit.

Turning now toFIG. 8, one implementation of a method800for determining which microcode sequences to store in a fastpath microcode structure is shown. A computing system identifies frequently executed instructions of a given program (block805). In one implementation, the identification of the frequently executed instructions is predetermined based on an analysis of the given program. In another implementation, the identification of the frequently executed instructions is performed dynamically in real-time as the program instructions are being executed. Next, microcode sequences of the frequently executed instructions are stored in a fastpath microcode structure (block810). The other instructions not identified as frequently executed instructions are stored in a microcode structure which is larger than and has a slower access time than the fastpath microcode structure (block815). After block815, method800ends. It is noted that in one implementation, when the identification of frequently executed instructions is performed dynamically, method800is performed on a periodic basis.

In various implementations, program instructions of a software application are used to implement the methods and/or mechanisms described herein. For example, program instructions executable by a general or special purpose processor are contemplated. In various implementations, such program instructions are represented by a high level programming language. In other implementations, the program instructions are compiled from a high level programming language to a binary, intermediate, or other form. Alternatively, program instructions are written that describe the behavior or design of hardware. Such program instructions are represented by a high-level programming language, such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. In various implementations, the program instructions are stored on any of a variety of non-transitory computer readable storage mediums. The storage medium is accessible by a computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute program instructions.

It should be emphasized that the above-described implementations are only non-limiting examples of implementations. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.