Liquid crystal display device

A display device is provided. The display device comprises a plurality of data lines extending in a first direction. The display device also comprises a plurality of gate lines. The plurality of gate lines comprises a first gate line, a second gate line and a third gate line extending in a second direction different than the first direction to form a matrix with the plurality of data lines. The first gate line and the second gate line are separated from each other and are arranged in a same row of the matrix. The display device further comprises a first gate connector line and a second gate connector line, respectively, electrically connecting the first gate line and the second gate line to one or two gate drivers. The first gate connector line and the second gate connector line extend in the first direction.

FIELD OF THE PRESENT DISCLOSURE

The present disclosure relates to a liquid crystal display device, and more particularly to a liquid crystal display device with a void in a display region thereof.

BACKGROUND

A liquid crystal display device is constituted to have a display panel with a pair of glass substrates that are arranged to face each other in an opposed manner with a liquid crystal layer being sandwiched therebetween. The display panel has a display region in which a plurality of gate lines extend in a first direction (usually horizontal scanning direction) and are arranged parallel to each other, and a plurality of data lines extend in a second direction (usually vertical scanning direction) and are arranged parallel to each other, such that the plurality of data lines crosses the plurality of gate lines and define pixels therebetween. The display panel further includes pixel electrodes and common electrodes which are formed in each of the pixels on one of the sides of the liquid crystal layer with respect to the said glass substrates. Each of the pixel electrodes is driven by a corresponding thin film transistor (TFT) disposed in the vicinity of the pixel electrode at respective crossing portions of the gate lines and the data lines. Typically, such gate lines and data lines are required to be continuous lines in order to conduct corresponding signal therein to respective TFTs.

Some manufacturers are trying to implement the liquid crystal display devices with voids formed in the display region thereof. For example, the liquid crystal display devices are being implemented in watches, such as smart watches, for displaying relevant information in addition to time. In such implementation of a liquid crystal display device, it may become necessary to form a hole or the like in order to attach one or more indicators, such as various hands like a second-hand, a minute-hand and an hour-hand, which are used to indicate time in a watch. Such void, created due to the formed hole, may obstruct path of the gate lines and the data lines in the display region.

US Patent Publication Number 20080225216A1 proposes a solution to overcome the problem of forming the gate lines and the data lines in the display region with a void. The publication discloses an active matrix circuit substrate which includes: a substrate having an avoidance portion provided in a predetermined region; a plurality of pixel electrodes provided on the substrate; a driving circuit that is provided on the substrate and drives the a plurality of pixel electrodes; a plurality of wiring lines which are provided on the substrate and include a plurality of power lines electrically connected to the driving circuit and a part of which has a detour portion that makes a detour to avoid the avoidance portion; and a connecting portion which is provided in the periphery of the avoidance portion on the substrate and which is connected to the power lines such that the plurality of power lines are packed.

The proposed solution requires detouring of the gate lines and the data lines in the display region around any hole or the like that may be formed therein. Generally, in a liquid crystal display device, the gate lines are wider than the data lines in order to carry the required signals therein. Thus, it may be feasible to detour the data lines; however, detouring of the gate lines may be difficult and expensive to achieve without deteriorating the quality of image produced by the liquid crystal display device.

Furthermore, the display panel also has a non-display region on an outer side of the display region. On the glass substrates of the display panel, gate drivers and data drivers are arranged in the non-display region for applying signals to the gate lines and the data lines to drive the TFTs associated therewith. In such arrangement of the drivers, the non-display region is necessary at a peripheral edge portion of the display panel. It is to be noted that in the liquid crystal display device, the non-display region of the display panel is covered with a front frame (bezel) or the like. Conventionally, an effort has been made to reduce the size of the non-display region in order to thin the bezel.

The present invention has been made in view of such considerations, and it is an object of the present invention to provide a liquid crystal display device which can be implemented for applications requiring a void or the like to be formed in the display region thereof while also reducing the size of the non-display region therein.

SUMMARY

In an aspect, a display device is disclosed. The display device comprises a plurality of data lines extending in a first direction. The display device also comprises a plurality of gate lines. The plurality of gate lines comprises a first gate line, a second gate line and a third gate line extending in a second direction different than the first direction to form a matrix with the plurality of data lines. The first gate line and the second gate line are separated from each other and are arranged in a same row of the matrix. The display device further comprises a first gate connector line and a second gate connector line, respectively, electrically connecting the first gate line and the second gate line to one or two gate drivers. The first gate connector line and the second gate connector line extend in the first direction.

In one or more embodiments, the plurality of data lines extends in a display region of the display device. The plurality of data lead lines electrically connects the plurality of data lines to one or more data drivers arranged in a non-display region of the display device.

In one or more embodiments, the plurality of gate lines and each of the first gate connector line and the second gate connector line extend in the display region. Each of the first gate connector line and the second gate connector line are electrically connected to the one or two gate drivers, arranged in the non-display region, via one or more first gate lead lines.

In one or more embodiments, the display device further comprises a third gate connector line extending in the first direction and electrically connecting the third gate line to the one or more gate drivers, arranged in the non-display region, via one or more second gate lead lines.

In one or more embodiments, each of the one or more first gate lead lines branches into a first gate lead branch line and a second gate lead branch line. The first gate lead branch line is connected to the first gate connector line and the second gate lead branch line is connected to the second gate connector line.

In one or more embodiments, the first gate lead branch line comprises a first portion and a second portion. The first portion overlaps, at least partially, the one or more second gate lead lines in plan view.

In one or more embodiments, the first portion is arranged in a same layer as the plurality of data lines.

In one or more embodiments, the second portion is arranged in a same layer as the plurality of gate lines.

In one or more embodiments, the second gate lead branch line is arranged in a same layer as the plurality of gate lines.

In one or more embodiments, the first gate line and the second gate line are separated at a void in a display region of the display device.

In one or more embodiments, the third gate line is longer than a combination of the first gate line and the second gate line.

In one or more embodiments, the first direction and the second direction are orthogonal to each other.

In one or more embodiments, the one or two gate drivers comprise a first gate driver and a second gate driver. The first gate connector line connects the first gate line to the first gate driver and the second gate connector line connects the second gate line to the second gate driver.

In one or more embodiments, the one or two gate drivers comprise a single gate driver configured to send pulses to the first gate line and the second gate line simultaneously.

In one or more embodiments, each of the first gate line and the second gate line comprises at least one contact point formed therein. The first gate connector line and the second gate connector line are, respectively, connected to the first gate line and the second gate line at the corresponding at least one contact point.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure is not limited to these specific details.

Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not for other embodiments.

A display device of each exemplary embodiment described below includes a display panel that display images, a driving circuit with one or more data drivers and one or more gate drivers that drive the display panel, a timing controller that control the driving circuit, an image processor that performs image processing on an input video signal input and outputs image data to the timing controller, and a backlight that irradiates the display panel with light from a rear surface side thereof. The display device is further provided with a void formed in the display panel. Examples of the display device include, but not limited to, a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, and an electrophoresis display (EPD).

FIG. 1illustrates a schematic configuration of a display device (generally referenced by the numeral100), in accordance with one or more embodiments of the present disclosure. As illustrated inFIG. 1, the display device100includes a display panel102. The display panel102includes a driving circuit104disposed in a non-display region106, bordering a display region108, in the display panel102. The driving circuit104may be arranged proximal to any one of an upper edge108a, a lower edge108b, a left edge108cand a right edge108d, of the display region108in the display panel102. In the present embodiments, the driving circuit104is shown to be arranged proximal to the upper edge108aof the display region108. In addition, the display device100includes a timing controller110that controls the driving circuit104, and an image processor112that outputs image data to the timing controller110. The image processor112receives input video signals data SINtransmitted from an external system (not illustrated), performs known image processing on the input video signal data SIN, and outputs image signal data SOUTto the timing controller110. The image processor112may also output a control signal (not shown inFIG. 1), such as a synchronizing signal, to the timing controller110. In the display device100, the display panel102displays an image in the display region108thereof according to the image signal data SOUT.

FIGS. 2, 6, 8 and 9illustrate plan views of the display panel102according to various exemplary embodiments of the present disclosure. As illustrated, the display panel102includes a plurality of data lines (generally referenced by the numeral114) and a plurality of gate lines (generally referenced by the numeral116) formed in the display region108. The plurality of data lines114and the plurality of gate lines116may be formed of Aluminum (Al) or Copper (Cu); however, it may be contemplated that other metals with high melting point, such as Chromium (Cr), Molybdenum (Mo), Tungsten (W), Titanium (Ti), Tantalum (Ta) or an alloy of two or more kinds of these metals, or a lamination film of two or more kinds of these metals or alloys, may be used without any limitations. As shown, the plurality of data lines114generally extend in a first direction (referenced as ‘X’ axis) and the plurality of gate lines116generally extend in a second direction (referenced as ‘Y’ axis). Further, as shown, the plurality of data lines114are disposed parallel to each other in the second direction ‘Y’ by a same interval, and the plurality of gate lines116are disposed parallel to each other in the first direction ‘X’ by a same interval. As may be seen, the first direction ‘X’ and the second direction ‘Y’ are different from each other, or specifically orthogonal to each other, with the first direction ‘X’ generally extends along vertical scanning direction and the second direction ‘Y’ generally extends along horizontal scanning direction. Thereby, the plurality of data lines114and the plurality of gate lines116form a matrix in the display region108of the display panel102.

In the exemplary embodiments of the present disclosure, the display region108is provided with a void (referred by the numeral118). By “provided” herein means that the void118may be formed by cutting, piercing, molding, etching, or any other known process in a glass substrate (not shown) of the display panel102. The void118may, generally, be in the form of a hole or empty space in which no data lines (from the plurality of data lines114) and no gate lines (from the plurality of gate lines116) are arranged. Although inFIG. 2, the void118has been shown to be located close to the lower edge108bof the display region108, in other examples, the void118may be located at other location in the display region108; for example, as shown inFIGS. 6, 8 and 9of the accompanying drawings but not limited thereto. Further, inFIG. 2, the void118has been shown to have a generally rectangular or square shape; however, it will be clear that the void118may have any other shape; for example, as shown inFIGS. 6, 8 and 9of the accompanying drawings but not limited thereto.

In the present embodiments, the plurality of gate lines116include a first gate line120, a second gate line122and a third gate line124extending in the second direction ‘Y’. Herein, the first gate line120and the second gate line122are separated from each other and are arranged in a same row of the matrix in the display region108of the display panel102. Specifically, the first gate line120and the second gate line122are separated at the void118in the display region108. It may be seen that the first gate line120and the second gate line122may be equidistant from the upper edge108aas well as the lower edge108bof the display region108in the display panel102. Further, the third gate line124is, generally, a continuous line extending along an entire horizontal length between the left edge108cand the right edge108dof the display region108. Herein, the third gate line124is longer than a combination of the first gate line120and the second gate line122. The third gate line124may be located, generally, above or below the void118. In some embodiments, as illustrated inFIG. 2, one or more data lines of the plurality of data lines114which may encounter the void118while extending along the first direction ‘X’ may deviate from the first direction ‘X’ and extend around the void118, while generally still be extending in the first direction ‘X’.

It may be understood that although some of the present embodiments have been described in reference to a single first gate line (such as, the first gate line120), a single second gate line (such as, the second gate line122) and a single third gate line (such as, the third gate line124), the display panel102would typically have plurality of such lines120,122,124therein, and hereinafter any reference to a single line may be applied to multiple corresponding lines without any limitations. Also, it may be contemplated that in a conventional display panel with continuous gate lines, one or more gate lines of the plurality of gate lines could possibly encounter the void (such as, the void118) while extending along the second direction (such as, the second direction ‘Y’), while other gate lines may not do so. It may be appreciated that in the present embodiments, the first gate line120and the second gate line122which are separated at the void118may generally correspond to such one or more gate lines of the plurality of gate lines encountering the void, while the third gate lines124in the display device100may correspond to the said other gate lines.

In the illustrated embodiments, the driving circuit104is shown to be located above the upper edge108aof the display region108, in the non-display region106of the display panel102in plan view. The driving circuit104includes one or more data drivers126for providing signals to the plurality of data lines114and one or more gate drivers128for providing signals to the plurality of gate lines116. In order for the first gate line120, the second gate line122and the third gate line124to be connected to the driving circuit104, the display device100of the present disclosure includes a first gate connector line130and a second gate connector line132, respectively, electrically connecting the first gate line120and the second gate line122to one or two of the gate drivers128, and a third gate connector line134electrically connecting the third gate line124to the gate drivers128in the driving circuit104. In the present embodiments, the first gate connector line130, the second gate connector line132and the third gate connector line134extend in the first direction ‘X’, adjacent and parallel to the plurality of data lines114in the display region108. In one or more examples, the first gate connector line130, the second gate connector line132and the third gate connector line134are formed of the same material as used for forming the plurality of gate lines116. It may be understood that the driving circuit104can be located below the bottom edge108bof the display region108, in the non-display region106of the display panel102in plan view without affecting the scope of the present disclosure.

As illustrated, each of the first gate line120and the second gate line122comprises at least one contact point, such as contact point136formed therein. The first gate connector line130and the second gate connector line132are, respectively, connected to the first gate line120and the second gate line122at the corresponding contact point136therein. In one or more examples, with the display panel108having multiple first gate lines (like, the first gate line120) and multiple second gate lines (like, the second gate line122), the corresponding first gate connector lines130and the corresponding second gate connector lines132are arranged such that the contact points136may, generally, be disposed along one or more sloping lines (as may be seen fromFIG. 2). Further, the third gate line124includes at least one contact point, such as contact point138formed therein, and the third gate connector line134is connected to the third gate line124at the corresponding contact point138therein. In one or more examples, with the display panel108having multiple third gate lines (like, the third gate line124), the corresponding third gate connector lines134are arranged such that the contact points138may, generally, be disposed along one or more sloping lines. In some examples, one or more of the third gate line124may have two contact points138formed therein, corresponding to two number of gate lines, namely the first gate line120and the second gate line122, located below thereof in the display region108of the display panel102in plan view.

It may be appreciated that the plurality of data lines114and each of the first gate line120, the second gate line122and the third gate line124may terminate at or close to the upper edge108aof the display region108, while the driving circuit104is arranged in the non-display region106at a distance from the upper edge108a. In the present embodiments, the display device100includes lead lines (generally referred by the numeral140) which extend from the driving circuit104, in the non-display region106, to the upper edge108aof the display region108or beyond thereof. In particular, the lead lines140include a plurality of data lead lines142electrically connecting the plurality of data lines114to the one or more data drivers126. Further, the lead lines140include a plurality of first gate lead lines144electrically connecting the first gate connector line130and the second gate connector line132to the one or more gate drivers128, and one or more second gate lead lines146electrically connecting the third gate connector line134to the one or more gate drivers128. In one or more examples, the data lead lines142are formed of the same material as used for forming the plurality of data lines114. Further, in one or more examples, the first gate lead lines144and the second gate lead lines146are formed of the same material as used for forming the plurality of gate lines116. It may be contemplated by a person skilled in the art that during operation of the display device100, at least in some examples, the first gate line120and the second gate line122are provided with signals, generally, at a same instant of time so as to complete one horizontal scan for corresponding row of the matrix in the display region108. Further, it may be appreciated a number of the first gate lead lines144is equal to a number of the first gate lines120(which, in turn, is generally equal to a number of the second gate lines122), and a number of the second gate lead lines146is equal to a number of the third gate lines124.

FIGS. 3 and 4illustrate cross-section views of a TFT substrate of the display panel102taken along lines I-I′ and II-II′ respectively ofFIG. 2, andFIG. 5illustrates cross-section view of the display panel102taken along line III-III′ ofFIG. 2, according to one or more exemplary embodiments of the present disclosure. As illustrated, the display panel102includes a glass substrate147which may be a sheet of transparent glass material or the like. An insulating layer148is disposed on the glass substrate147. Further, a passivation layer150is disposed on the insulating layer148, an organic insulating layer152is disposed on the passivation layer150, and an another passivation layer154is disposed on the organic insulating layer152. Such configuration and arrangement of layers in a display panel of a liquid crystal display device is well known in the art and thus has not been described herein. It may be appreciated that the display panel102may include more or less number of said layers, or different types of said layers, without departing from the scope of the present disclosure.

As illustrated inFIG. 3, the cross-section area along the line I-I′ has the data lines114and the gate connector lines (including the first gate connector line130and the third gate connector line134) formed next thereto. It may be understood that although only the first gate connector line130and the third gate connector line134are visible inFIG. 3, the second gate connector line132may also have similar arrangement with respect to its corresponding data line114. As further seen fromFIG. 2, the data lines114and the gate connector lines (such as, the first gate connector line130, as shown) are disposed parallel to each other along the first direction ‘X’ in the display panel102. As shown inFIG. 3, the data lines114and the gate connector lines (such as, the gate connector lines130and134) are arranged between the insulating layer148and the passivation layer150of the display panel102. Also, the cross-section area along the line I-I′ has a common electrode156formed on top of the organic insulating layer152and in contact with the another passivation layer154. Further, pixel electrodes158and an alignment layer (not shown) are formed on top of the another passivation layer154in the cross-section area along the line I-I′ of the display panel102. As illustrated inFIG. 4, the cross-section area along the line II-II′ has one of the gate connector lines (herein, the third gate connector line134) disposed in contact with one of the plurality of gate lines116(herein, the third gate line124). As shown, the third gate connector line134may be formed directly above the third gate line124to provide the electrical connection therebetween via a through hole formed in the insulating layer148. Further, as illustrated inFIG. 5, the cross-section area along the line III-III′ (in the non-display region106) has the lead lines (including the data lead lines142, and the first gate lead lines144and the second gate lead lines146). As shown, the data lead lines142are arranged between the insulating layer148and the passivation layer150(similar to the corresponding plurality of data lines114), and the gate lead lines144and146are arranged between the glass substrate147and the insulating layer148(similar to the corresponding plurality of gate lines116). It may be understood that the left-to-right arrangement of various elements discussed above is exemplary only and shall not be construed as limiting to the present disclosure.

Referring back to illustrated embodiment ofFIG. 2, the driving circuit104includes two gate drivers, namely a first gate driver128aand a second gate driver128bsuch that the first gate connector line130is connected to the first gate driver128aand the second gate connector line132is connected to the second gate driver128b, and thereby the first gate connector line130electrically connects the first gate line120to the first gate driver128aand the second gate connector line132electrically connects the second gate line122to the second gate driver128b. In one or more examples, the first gate driver128aand the second gate driver128bmay be in sync with each other so as to provide generally simultaneous gate signals to the first gate line120and the second gate line122. It may be seen that in the embodiment ofFIG. 2, the first gate lead lines144are not interfering with the second gate lead lines146. In an alternative example, the two gate drivers128aand128bmay be replaced by a single driver with same number of terminals as combined number of terminals in the two gate drivers128aand128bwithout affecting the scope of the present embodiment.

Referring now toFIG. 6, a plan view of the display panel102is illustrated according to another exemplary embodiment of the present disclosure. Herein, the driving circuit104includes a single gate driver128cconfigured to send gate pulses to the first gate line120and the second gate line122simultaneously. In such embodiments, each of the one or more first gate lead lines144branches into a first gate lead branch line160and a second gate lead branch line162such that the first gate lead branch line160is connected to the first gate connector line130and the second gate lead branch line162is connected to the second gate connector line132. It may be understood that the first gate lead branch line160and the second gate lead branch line162may carry the same gate signal simultaneously generated from the gate driver128cfor the first gate line120(via the first gate connector line130) and the second gate line122(via the second gate connector line132).

As may be seen fromFIG. 6, one or more of the first gate lead lines144, or in particular the first gate lead branch lines160of the first gate lead lines144may overlap with the second gate lead lines146in plan view of the non-display region106. Specifically, a portion of the first gate lead branch line160may overlap with the second gate lead lines146, while rest portion of the first gate lead branch line160may not overlap with the second gate lead lines146(but may overlap with the data lead lines142). In an embodiment, each of the first gate lead branch line160includes a first portion160aand a second portion160bwith the first portion160aoverlapping, at least partially, the one or more second gate lead lines146in plan view, and the first portion160abeing arranged in a same layer as the plurality of data lines114and the second portion160bbeing arranged in a same layer as the plurality of gate lines116. Further, the second gate lead branch line162is arranged in a same layer as the plurality of gate lines116, similar to the second portion160bof the first gate lead branch line160.

FIG. 7illustrates a cross-section view of the display panel102taken along line IV-IV′ ofFIG. 6, according to one or more exemplary embodiments of the present disclosure. Generally, the cross-section of the display panel102, as shown inFIG. 7, has the same layers as in the cross-sections of the display panel102as shown inFIGS. 3-5. InFIG. 6, the line IV-IV′ is shown to pass through the non-display region106along a section where only one of the first gate lead line144has branched into the corresponding first gate lead branch line160and the second gate lead branch line162, for the sake of simplicity. As shown inFIG. 7, the data lead lines142are arranged between the insulating layer148and the passivation layer150of the display panel102ofFIG. 6, similar to the data lead lines142of the display panel102ofFIG. 2. Further, as shown, the first gate lead lines144and the second gate lead lines146are, generally, disposed between the insulating layer148and the passivation layer150; however, it is to be noted that for one of the first gate lead line144that has branched into the corresponding first gate lead branch line160and the second gate lead branch line162along the line IV-IV′, the first portion160aof that first gate lead branch line160and the second lead branch line162are electrically connected to each other via a through hole164formed in the insulating layer148.

It may be seen fromFIGS. 6-7in combination and contemplated that the first portion160aof the first gate lead branch line160electrically connects with the insulating layer148so as to avoid contact with the second gate lead lines146already present in a path thereof. It may be understood that an area in which the first portion160aof the first gate lead branch line160may be formed on the insulating layer148may not have any data lead lines (such as, the data lead lines142) formed thereon. Once the region where the first gate lead branch lines160are susceptible to intersect with the second gate lead lines146is traversed, the second portion160bof is formed in the same layer as gate lead lines144,146. The second portion160bof the first gate lead branch line160connects with the first portion160aof the first gate lead branch line160via an another through hole165(similar to the through hole164). This way the first gate lead branch line160mitigate the risk of possible short-circuiting with the second gate lead lines146in the display panel102.

FIGS. 8-9illustrate plan views of the display panel102according to other exemplary embodiments of the present disclosure. It may be seen that the display panel102ofFIG. 8, generally, corresponds to the display panel102ofFIG. 2, with the primary difference being in the shape of the void118. It may be understood that the embodiments of the display panel102as described with reference toFIG. 2may generally be applied to the display panel102ofFIG. 8, and thus have not been described herein again for the brevity of the present disclosure. Further, it may be seen that the display panel102ofFIG. 9, generally, corresponds to the display panel102ofFIG. 6, with the primary difference being in the shape of the void118. It may be understood that the embodiments of the display panel102as described with reference toFIG. 6may generally be applied to the display panel102ofFIG. 9, and thus have not been described herein again for the brevity of the present disclosure.

Although the present disclosure has been described in reference to the gate lines (such as, the first gate lines120and the second gate lines122) being separated around the void (such as, the void118); in other embodiments (not shown), the data lines encountering the void may be separated in addition to the gate lines, or independently of the gate lines (i.e. whether the gate lines are separated or not). In such case, the data drivers (such as, the data drivers126) may be arranged on either one of the left edge108cand the right edge108dof the display panel102, and data connector lines (akin to gate connector lines130and132) may be formed extending in the second direction ‘Y’ to connect the separated data lines to the data drivers. Such configurations may be contemplated by a person skilled in the art and thus have not been described herein for the brevity of the present disclosure.

The display device100of the present disclosure provides a configuration to arrange the gate lines (and/or the data lines) for a display panel with a void without the need of detouring the gate lines (and/or the data lines) which is generally very difficult and expensive to achieve. In addition, the display device100provides an added advantage of arranging the driving circuit104with all the drivers (including the gate drivers and the data drivers) therein along one of the edges (such as, the upper edge108a) of the display panel102, thus providing an opportunity to eliminate the frame needed to cover any drivers, like gate drivers, that may otherwise have been located along the left edge108cand/or the right edge108d. This results in reduced overall bezels of the display device100which is desirable.

The foregoing descriptions of specific embodiments of the present disclosure have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiment was chosen and described in order to best explain the principles of the present disclosure and its practical application, to thereby enable others skilled in the art to best utilize the present disclosure and various embodiments with various modifications as are suited to the particular use contemplated.