Memory programming method, memory control circuit unit and memory storage device

A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 104105289, filed on Feb. 16, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Technology Field

The present relates to a memory programming method and more particularly, to a memory programming method, a memory control circuit unit and a memory storage device for a rewritable non-volatile memory module.

2. Description of Related Art

Along with the widespread of digital cameras, cell phones, and MP3 players in recently years, the consumers' demand to storage media has increased drastically. Because a rewritable non-volatile memory is capable of providing features such as data non-volatility, low power consumption, small volume, and non-mechanical structure, high reading and writing speed, the rewritable non-volatile memory has become the most adaptable memory applied in a portable electronic product, e.g., a notebook computer. Therefore, the flash memory industry has become a very popular part of the electronic industry in recent years.

Generally, a flash memory may be programmed to change a storage state of memory cells in the flash memory to write data. However, programming the memory cells in the flash memory by using the traditional method for programming the flash memory may result in overly increased threshold voltage distribution range of part of the memory cells whose storage state already meet the storage state of the write data (which is also referred to as part of the memory cells being over-programmed), and durability of the over-programmed memory cells may be reduced, and further the overall lifespan of the flash memory may be shortened.

SUMMARY

Accordingly, the present invention is directed to a memory programming method, a memory storage device and a memory control circuit unit capable of grouping a plurality of memory cells into a plurality of programming groups to apply an adaptive program voltage to the memory cells in each programming group, so as to effectively prevent the memory cells from being over-programmed and extend the lifespan of the memory storage device.

According to an exemplary embodiment of the present invention, a memory programming method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of memory cells. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into a plurality of programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. Therein, the first program voltage and the second program voltage are different.

According to another exemplary embodiment of the present invention, a memory storage device including a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit is provided. The rewritable non-volatile memory module includes a plurality of memory cells. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to transmit a first write command sequence. The first write command sequence is configured to instruct to perform a first programming process on the memory cells according to write data. The memory control circuit unit is further configured to obtain a first programming result of the first programming process and group the memory cells into a plurality of programming groups according to the first programming result. The memory control circuit unit is further configured to transmit a second write command sequence. The second write command sequence is configured to instruct to perform a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. Therein, the first program voltage and the second program voltage are different.

According to another exemplary embodiment of the present invention, a memory control circuit unit configured to control a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of memory cells. The memory control circuit unit includes a host interface, a memory interface and a memory management circuit. The host interface is coupled to host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is configured to transmit a first write command sequence. The first write command sequence is configured to instruct to perform a first programming process on the memory cells according to write data. The memory management circuit is further configured to obtain a first programming result of the first programming process and group the memory cells into a plurality of programming groups according to the first programming result. The memory management circuit is further configured to transmit a second write command sequence. The second write command sequence is configured to instruct to perform a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. Therein, the first program voltage and the second program voltage are different.

To sum up, the memory programming method, the memory control circuit unit and the memory storage device provided by the present invention may facilitate in adjusting the program voltage applied to the memory cells according to the threshold voltage distribution (or a writing speed) of the memory cells to prevent the memory cells from being over-programmed, so as to extend the lifespan of the memory storage device. Meanwhile, the threshold voltage distribution range of the programmed memory cells can be accordingly narrowed, so as to reduce error bits occurring in the stored data.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a schematic diagram illustrating a flash memory element according to an exemplary embodiment of the present invention.

With reference toFIG. 1, in the present exemplary embodiment, a flash memory element1(also referred to as a memory cell) includes a charge-trapping layer2for storing electrons, a control gate3for applying a voltage, a tunnel oxide layer4, an interpoly dielectric layer5, and a substrate6. When it is intended to write data into the flash memory element1, electrons may be injected into the charge-trapping layer2by applying a program voltage (also referred to as a program voltage), so as to change a voltage of the flash memory element1. In the exemplary embodiments below, the voltage of the flash memory element1is also referred to as a threshold voltage of the flash memory element1. The threshold voltage may be configured to indicate a data storage state of the flash memory element1. Accordingly, a digital-level state (i.e., a storage state) of the flash memory element1is defined, so as to store data. Here, the process of injecting the electrons into the charge-trapping layer2is referred to as a programming process. By contrast, when it is intended to remove the stored data, an erase voltage is applied, so as to remove the injected electrons from the charge-trapping layer2, and thereby the flash memory element1is restored back to the state before programming.

FIG. 2is a schematic diagram of programming memory cells according to an exemplary embodiment of the present invention.

With reference toFIG. 2, in the present exemplary embodiment, the programming operation of the memory cells is performed by using an incremental-step-pulse programming (ISPP) model and by pulse writing and applying a verification threshold voltage. Particularly, when data is about to be programmed to memory cells, an initial program voltage Viand a program voltage pulse time ΔT are set. When the data is programmed to the memory cells, the set program voltage Viand the set program voltage pulse time ΔT are used to program the memory cells. A verification voltage Vverifymay be configured to verify the memory cells to determine whether the memory cells is in an accurate storage state. If the memory cells is not yet programmed to be in the accurate storage state, the currently applied program voltage is added with an ISPP adjustment value ΔV as a new program voltage (e.g., Vr1, Vr2inFIG. 2) and the memory cell is programmed again according to the new program voltage and the program voltage pulse time ΔT. If the memory cells is programmed to be in the accurate storage state, it represents that the data is accurately written into the memory cells.

FIG. 3is a schematic graph illustrating a threshold voltage distribution of a plurality of memory cells in a programming operation according to an exemplary embodiment of the present invention.

With reference to bothFIG. 2andFIG. 3, it is assumed that a plurality of memory cells is programmed to be in a storage state with a storage bit of “0”. A threshold voltage distribution of the memory cells before being programmed is presented by a solid line D1(which is also referred to as a threshold voltage distribution D1) illustrated inFIG. 3, and an initial storage state of the memory cells is “1”. Additionally, it is assumed that the memory cells are programmed by using the ISPP model ofFIG. 2. When the memory cells are programmed by using the initial program voltage Vi, the threshold voltage distribution of the memory cells is presented by a dotted line D2(which is also referred to as a threshold voltage distribution D2) illustrated inFIG. 3. Then, the verification voltage Vverifyis used to verify the memory cells to determine whether the memory cells are all in the accurate storage state (i.e., the storage bit is “0”). Here, since the memory cells are not in the storage state with the storage bit of “0”, the currently applied initial program voltage Viis added with the ISPP adjustment value ΔV as a new program voltage Vr1, and the memory cells are programmed again according to the new program voltage Vr1and a program voltage pulse time ΔT. A threshold voltage distribution of the memory cells which are re-programmed by using the program voltage Vr1is presented by using a dotted line D3(which is also referred to as a threshold voltage distribution D3) illustrate inFIG. 3. In this way, when a threshold voltage distribution of the memory cells programmed by using the program voltage Vr2is presented by a solid line D4(which is also referred to as a threshold voltage distribution D4) illustrated inFIG. 3, and the memory cells are all in the accurate storage state (i.e., the storage bit is “0”), the programming operation of writing the data including the bit of “0” to the memory cells is completed.

However, the above programming of the memory cells by using the ISPP model may result in the threshold voltage distribution of the memory cells being overly increased. For instance, with reference toFIG. 2andFIG. 3, a width of the threshold voltage distribution D1of the memory cells is smaller than a width of threshold voltage distribution D4of the memory cells. Such phenomenon appears because each memory cell has different characteristics, but is applied with the same program voltage, such that difference among the ranges of the threshold voltages of the memory cells dramatically becomes wider.

Moreover, as described above, programming the memory cells by using the normal ISPP model may also result in the memory cells being over-programmed. For instance, in the exemplary embodiment ofFIG. 3, when the memory cells performed with the programming operation have the threshold voltage distribution D3, programming the memory cells having the threshold voltage distribution D3by applying the same program voltage Vr2cause some memory cells among the memory cells whose threshold voltages exceed the verification voltage Vverifykeep to be applied with the program voltage (this process may be referred to as over-programming). The over-programmed memory cells having threshold voltages higher than the verification voltage Vverify, but being applied with the program voltage Vr2may have threshold voltages of higher levels. In other words, as described above, the programming operation is performed overly on the over-programmed memory cells because the program voltage is continuously applied. The over-programming causes unnecessary wear to the memory cells, increases degradation of the memory cells and thereby shortens the lifespan of the memory storage device.

Accordingly, in a memory programming method, and a memory control circuit unit and a memory storage device using the method provided in the below exemplary embodiments, a threshold voltage distribution status of a plurality of memory cells in the flash memory are identified, and the memory cells are grouped into a plurality of programming groups according to the threshold voltage distribution status of the memory cells, such that each programming group is applied with a corresponding program voltage. In this way, the memory cells may be effectively prevented from being over-programmed to extend the lifespan of the memory storage device.

Generally, a memory storage device (i.e., a memory storage system) includes a rewritable non-volatile memory module and a controller (i.e., a memory control circuit unit). The memory storage device is usually used with a host system, such that the host system can write data into or read data from the memory storage device.

FIG. 4is a schematic diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention.FIG. 5is a schematic diagram illustrating a computer, an input/output (I/O) device and a memory storage device according to an exemplary embodiment of the present invention.

With reference toFIG. 4, a host system11typically includes a computer12and an input/output (I/O) device13. The computer12includes a microprocessor122, a random access memory (RAM)124, a system bus126and a data transmission interface128. The I/O device13includes a mouse21, a keyboard22, a display23and a printer24illustrated inFIG. 5. It may be understood that the I/O device13is not limited to the devices illustrated inFIG. 5, and the I/O device13may further include other devices.

In an exemplary embodiment, the memory storage device10is coupled to other devices of the host system11through the data transmission interface128. Through the operation of the microprocessor122, the RAM124and the I/O device13, data can be written into or read from the memory storage device10. For instance, the memory storage device10may be a rewritable non-volatile memory storage device, such as a flash drive25, a memory card26or a solid state drive (SSD)27illustrated inFIG. 5.

FIG. 6is a schematic diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention.

Generally speaking, the host system11may be any system operated with the memory storage device10to store data. Even though the host system11is described as a computer system in the present exemplary embodiment, the host system11, in another exemplary embodiment, may be a digital camera, a video camera, a communication device, an audio player, or a video player. For instance, in case the host system is a digital camera (video camera)31, the non-volatile memory storage device is a secure digital (SD) card32, a multi media card (MMC) card33, a memory stick (MS)34, a compact flash (CF) card35or an embedded storage device36(illustrated inFIG. 6). The embedded storage device36may include an embedded MMC (eMMC). It may be mentioned that the eMMC is directly coupled to the substrate of the host system.

FIG. 7is a schematic block diagram of the memory storage device depicted inFIG. 4.

With reference toFIG. 7, the memory storage device10includes a connection interface unit102, a memory control circuit unit104and a rewritable non-volatile memory module106.

In the present exemplary embodiment, the connection interface unit102complies with the serial advanced technology attachment (SATA) standard. However, the present invention is not limited thereto, and the connection interface unit402may also comply with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the peripheral component interconnect express (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the memory stick (MS) interface standard, the multi-media card (MMC) interface standard, the Embedded Multimedia Card (eMMC) interface standard, the Universal Flash Storage (UFS) interface standard, the compact flash (CF) interface standard, the integrated device electronics (IDE) standard, or other suitable standards. The connection interface unit102may be package with the memory control circuit unit104in one chip or laid outside a chip having the memory control circuit unit104.

The memory control circuit unit104is configured to execute a plurality of logic gates or control commands which are implemented in a hardware form or in a firmware form and perform operations such as data writing, reading or erasing in the rewritable non-volatile memory module106according to the command of the host system11.

The rewritable non-volatile memory module106is coupled to the memory control circuit unit404and configured to store data written by the host system11. The rewritable non-volatile memory module106may be a single level cell (SLC) NAND flash memory module, a multi level cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing data of 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing data of 3 bits in one memory cell), other flash memory modules, or other memory modules having the same characteristics.

FIG. 8is a schematic block diagram illustrating a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

With reference toFIG. 8, the rewritable non-volatile memory module106includes a memory cell array2202, a word line control circuit2204, a bit line control circuit2206, a column decoder2208, a data input/output (I/O) buffer2210, and a control circuit2212.

FIG. 9is a schematic diagram illustrating a memory cell array according to an exemplary embodiment of the present invention.

With reference toFIG. 8andFIG. 9, the memory cell array2202includes a plurality of select gate drain (SGD) transistors912and a plurality of select gate source (SGS) transistors914disposed on a plurality of substrates, a plurality of bit lines904, a plurality of word lines906, a plurality of source lines connected with the memory cells902and a plurality of memory cells902for storing data (as illustrated inFIG. 9). The memory cells902are disposed on the cross points of the bit lines904and the word lines906in an array. When a write command or a read command is received from the memory control circuit unit104, the control circuit2212controls the word line control circuit2204, the bit line control circuit2206, the column decoder2208, and the data I/O buffer2210to write data into the memory cell array2202or read data from the memory cell array2202. The word line control circuit2204is configured to control the voltage applied to the word lines906, the bit line control circuit2206is configured to control the voltage applied to the bit lines904, the column decoder2208selects the corresponding bit line according to the decoding column address in the command, and the data I/O buffer2210is configured to store the data temporarily.

As described above, the memory cells of the rewritable non-volatile memory module106are programmed, by using a variety of program voltages, to a variety of storage states to accurately store bit values of write data. Specifically, each memory cell in the memory cell array2202has a plurality of storage states, and the storage states are distinguished by a plurality of read voltages.

FIG. 10is a schematic graph of a threshold voltage distribution corresponding to the write data stored in the memory cell array according to an exemplary embodiment of the present invention.

With reference toFIG. 10, taking an MLC NAND flash memory as an example, the threshold voltage in each memory cell may be categorized into 4 storage states according to a default threshold voltage VA, a default threshold voltage VB, and a default threshold voltage VC, and the storage states respectively represent storage bits, “11”, “10”, “00” and “01”. Thus, in the present exemplary embodiment, each memory cell may store data of 2 bits. It may be understood that the threshold voltages and the storage states corresponding thereto illustrated inFIG. 10are merely examples. In another exemplary embodiment, the corresponding relationship between the threshold voltages and the storage states may have an arrangement as “11”, “10”, “01” and “00” along with the increase in the threshold voltages. Alternatively, in another exemplary embodiment, the corresponding relationship between the threshold voltages and the storage states may also be set according to actual usage, which is not limited to the above.

In the example that each memory cells may store data of 2 bits, the memory cells on the same word line form two physical programming units (i.e., a lower physical programming unit and an upper physical programming unit). Additionally, a plurality of physical programming units in the memory cell array2202forms a physical erasing unit, and a physical erasing unit is the smallest unit for erasing. Namely, each physical erasing unit includes the least number of memory cells to be erased altogether.

The data write (i.e., program) process of the memory cell array2202includes applying a voltage (e.g., a gate voltage) to a certain terminal. For example, a program voltage (i.e., write voltage) may be controlled to change the electron volume in a charge-trapping layer in the gate, so that the conduction state of the channel of a memory cell is changed to present the different storage states. For instance, when the data of the lower physical programming unit is “1”, and the data of the upper physical programming unit is “1”, the control circuit2212controls the word line control circuit2204to not change the program voltage in the memory cell, so as to keep the storage state of the memory cell as “11”. When the data of the lower physical programming unit is “1”, and the data of the upper physical programming unit is “0”, the control circuit2212controls the word line control circuit2204to change the program voltage in the memory cell such that the storage state of the memory cell is changed to “10”. When the data of the lower physical programming unit is “0”, and the data of the upper physical programming unit is “0”, the control circuit2212controls the word line control circuit2204to change the program voltage in the memory cell such that the storage state of the memory cell is changed to “00”. When the data of the lower physical programming unit is “0”, and the data of the upper physical programming unit is also 1, the control circuit2212controls the word line control circuit2204to change the program voltage in the memory cell such that the storage state of the memory cell is changed to “01”.

Similarly, in an example that each memory cell is used to store data of 1 bit, (e.g., in an LC NAND flash memory module), the memory cells on the same word line form one physical programming unit. The storage state of the unprogrammed memory cells is “1”. To write data “1” into a memory cell, the control circuit2212controls the word line control circuit2204to keep the storage state of the memory cell as “1”. In contrast, to write data “0”, the control circuit2212controls the word line control circuit2204to change the program voltage in the memory cell such that the storage state of the memory cell is changed to “0”. Namely, the memory cell is programmed to be the memory cell with the storage bit of “0” through the programming operation.

In order to conveniently describe the memory programming method used in the present invention, it is assumed that each memory cell in the rewritable non-volatile memory module106can store 1 bit, and the memory control circuit unit104is intended to store write data (whose bit values are all “0”) into a plurality of unprogrammed memory cells in the rewritable non-volatile memory module106whose storage states are all “1”.

FIG. 11is a schematic diagram of grouping the memory cells according to an exemplary embodiment of the present invention.

With reference toFIG. 11, in the present exemplary embodiment, the memory control circuit unit104instructs the rewritable non-volatile memory module106to use one or more program voltages to perform a programming process (also referred to as a first programming process) on a plurality of memory cells (also referred to as target memory cells) according to write data (whose bit values are all “0”) to be stored and obtains a programming result (also referred to as a first programming result). For instance, a threshold voltage distribution of the target memory cells before being programmed is presented by a dotted line D5(i.e., a threshold voltage distribution D5) illustrated inFIG. 11and a storage state thereof is “1”. After the first programming process is performed, the threshold voltage distribution of the target memory cells is changed to be presented by a solid line D6(i.e., a threshold voltage distribution D6) illustrated inFIG. 11. In other words, the process of changing the threshold voltage distribution of the target memory cells from one distribution to another distribution may be referred to as a programming process. Additionally, in the present exemplary embodiment, the first programming process refers to an initialization process in the ISPP model, and a program voltage used in the first programming process is the initial program voltage (e.g., the initial program voltage Viillustrated inFIG. 2). However, in another exemplary embodiment, the first programming process may also refer to any programming process in the ISPP model, and the number of the program voltages used in each programming process is not limited.

In the present exemplary embodiment, the memory control circuit unit104transmit a verification instruction to the rewritable non-volatile memory module106. The verification instruction is configured to instruct the rewritable non-volatile memory module106to apply the verification voltage Vverifyto the target memory cells to determine whether the storage states of the target memory cells are all in the storage state (which is also referred to as the accurate storage state) corresponding to the write data. If the storage states of the target memory cells are all in the accurate storage state corresponding to the write data, the memory control circuit unit104determines that the programming result of the previously performed programming process meets a predetermined programming result. If the storage states of target memory cells are not all in the accurate storage state corresponding to the write data, the memory control circuit unit104determines that the programming result of the previously performed programming process does not meet the predetermined programming result. Additionally, the voltage level of the verification voltage Vverifymay be determined by the memory control circuit unit104or by the rewritable non-volatile memory module106(e.g., the control circuit2212) itself.

Referring toFIG. 11, since the threshold voltage distribution D6of the target memory cells on which the first programming process performs is smaller than the verification voltage Vverify, the storage states of the target memory cells read by applying the verification voltage Vverifyare all “1”, which does not meet the write data with all “0”. Accordingly, the memory control circuit unit104determines that the first programming result of the target memory cells does not meet the predetermined programming result.

In the present exemplary embodiment, if determining that the first programming result of the target memory cells does not meet the predetermined programming result, the memory control circuit unit104groups the target memory cells into a plurality of programming groups and then applies different program voltages to different programming groups in a subsequent programming process (also referred to as a second programming process), so as to try to program the target memory cells to the accurate storage state corresponding to the write data.

In the present exemplary embodiment, the memory control circuit unit104transmits an instruction (i.e., grouping instruction) to the rewritable non-volatile memory module106, in which the grouping instruction is configured to instruct the rewritable non-volatile memory module106to provide N different grouping voltages to the target memory cells to obtain storage state information of the target memory cells. For instance, after receiving the grouping instruction, the rewritable non-volatile memory module106(e.g., the control circuit2212) apply one or more grouping voltages to the target memory cells according to the grouping instruction, in which N may be 1 to 4, or any positive integer. Therein, the storage state information of the target memory cells may indicate the threshold voltage distributions of the target memory cells. For instance, according to the storage state information of a certain target memory cell, the memory control circuit unit104may obtain a threshold voltage distribution status of the target memory cell. Taking the exemplary embodiment illustrated inFIG. 11as an example, memory control circuit unit104instructs to group the target memory cells by using 4 grouping voltages VG1to VG4. Therein, the grouping voltages VG1to VG4fall within a range included in the threshold voltage distribution of the target memory cells. The grouping voltages VG1to VG4may be sequentially applied to the target memory cells according to levels thereof (e.g., from the smallest to the largest) or other rule. Additionally, the level of each of the grouping voltages VG1to VG4may be determined by the memory control circuit unit104or the rewritable non-volatile memory module106(e.g., the control circuit2212).

With reference toFIG. 11, after instructing the rewritable non-volatile memory module106to apply the grouping voltage VG1to the target memory cells, the memory control circuit unit104may obtain storage states of the target memory cells corresponding to the grouping voltage VG1. For instance, the memory control circuit unit104may obtain the target memory cells with the storage state “0” corresponding to the grouping voltage VG1and the target memory cells with the storage state “1” corresponding to the grouping voltage VG1. For instance, the memory control circuit unit104may identify that the target memory cells with the storage states “0” as the target memory cells having threshold voltages greater than the grouping voltage VG1and identify that the target memory cells with the storage state “1” as the target memory cells having threshold voltages smaller than the grouping voltage VG1. Likewise, after applying the grouping voltages VG2to VG4to the target memory cells, the memory control circuit unit104may further obtain the storage states of the target memory cells corresponding to the grouping voltages VG2to VG4, so as to group the target memory cells into programming groups A1to E1.

In the exemplary embodiment illustrated inFIG. 11, threshold voltage distribution ranges of the programming groups A1to E1are different. Additionally, a threshold voltage of a memory cell in the programming groups A1is smaller than a threshold voltage of a memory cell in the programming group B1; the threshold voltage of the memory cell in the programming group B1is smaller than a threshold voltage of a memory cell in the programming group C1; the threshold voltage of the memory cell in the programming group C1is smaller than a threshold voltage of a memory cell in the programming group D1; the threshold voltage of the memory cells in the programming group D1is smaller than a threshold voltage of a memory cell in the programming group E1.

It is to be mentioned that in the exemplary embodiments above, the memory control circuit unit104instructs to group the target memory cells by using 4 grouping voltages and thus, obtains5programming groups. However, in another exemplary embodiment, different numbers of the grouping voltages result in different numbers of grouped programming groups. For instance, if only one grouping voltage is used to group the target memory cells, the target memory cells may be grouped into only two programming groups, and so on, likewise.

FIG. 12is a schematic diagram of determining the programming groups according to an exemplary embodiment of the present invention.

With reference toFIG. 11andFIG. 12, it is assumed that the target memory cells includes memory cells Cell1to Cell5. A level of a voltage (or threshold voltage) of the memory cell Cell1is VC1, a level of a voltage (or threshold voltage) of the memory cell Cell2is VC2, a level of a voltage (or threshold voltage) of the memory cell Cell3is VC3, a level of a voltage (or threshold voltage) of the memory cell Cell4is VC4, and a level of a voltage (or threshold voltage) of the memory cell Cell5is VC5. After the grouping voltages VG1to VG4are applied to the target memory cells, the memory control circuit unit104may obtain, for example, a storage state ((“1”, “1”, “1”, “1”) in sequence) of the memory cell Cell1corresponding to the grouping voltages VG1to VG4, a storage state ((“0”, “1”, “1”, “1”) in sequence) of the memory cell Cell2corresponding to the grouping voltages VG1to VG4, a storage states ((“0”, “0”, “1”, “1”) in sequence) of the memory cell Cell3corresponding to the grouping voltages VG1to VG4, a storage states ((“0”, “0”, “0”, “1”) in sequence) of the memory cell Cell4corresponding to the grouping voltages VG1to VG4, and a storage states ((“0”, “0”, “0”, “0”) in sequence) of the memory cell Cell5corresponding to the grouping voltages VG1to VG4. The memory cell Cell1is grouped to the programming group A1according to the storage state of the memory cell Cell1corresponding to the grouping voltages VG1to VG4; the memory cell Cell2is grouped to the programming group B1according to the storage state of the memory cell Cell2corresponding to the grouping voltages VG1to VG4; the memory cell Cell3is grouped to the programming group C1according to the storage state of the memory cell Cell3corresponding to the grouping voltages VG1to VG4; the memory cell Cell4is grouped to the programming group D1according to the storage state of the memory cell Cell4corresponding to the grouping voltages VG1to VG4; and the memory cell Cell5is grouped to the programming group E1according to the storage state of the memory cell Cell5corresponding to the grouping voltages VG1to VG4.

The memory control circuit unit104may perform the above grouping operation through a look-up table. For instance, the storage state of the memory cell Cell1corresponding to the grouping voltages VG1to VG4is input to a look-up table to obtain that the memory cell Cell1belongs to the programming group A1. Alternatively, the memory control circuit unit104may also calculate a number of “0” or “1” in a storage state of a certain target memory cell in response to the grouping voltages VG1to VG4and then determine the programming group that the target memory cell belongs to. For instance, the storage state (“1”, “1”, “1”, “1”) of the memory cell Cell1in response to the grouping voltages VG1to VG4does not have any “0”, and thus, the memory control circuit unit104may group the memory cell Cell1into the programming group A1.

Referring toFIG. 11, according to the programming groups A1to E1, a programming speed of the memory cells in the programming group E1in response to the first programming process is the highest, while a programming speed of the memory cells in the programming group A1is the lowest. The programming speed of the memory cells in the programming group E1is higher than a programming speed of the memory cells in the programming group D1, the programming speed of the memory cells in the programming group D1is higher than a programming speed of the memory cells in the programming group C1, and so on. Thus, in the subsequent programming process (i.e., the second programming process), if a program voltage with a lower level is applied to the memory cells of a programming group with a higher writing speed, and another program voltage with a higher level is applied to the memory cells of another programming group with a higher speed, the threshold voltage distribution ranges of the target memory cells after the second programming process may be more concentrated. Moreover, in another exemplary embodiment, the threshold voltage distribution ranges of the programmed target memory cells may also be narrowed by means of adjusting the program voltage pulse time or other parameters related to the ISPP model.

In an exemplary embodiment, the memory control circuit unit104may record grouping information with respect to each memory cell being grouped each time or the last time. Thereby, when the memory cells are programmed afterwards, the grouping information may be directly used for grouping the memory cells to speed up the grouping operation.

As described above, after grouping the target memory cells into the plurality of programming groups, the memory control circuit unit104may instruct to apply different program voltages to different programming groups according to the grouped programming groups. The memory programming method of the present invention will be described with reference toFIG. 13toFIG. 18hereinafter. It may be noted that inFIG. 13toFIG. 18, dotted bars are used to present the program voltages, a slashed bar is used to present the verification voltage, and blank bars are used to present the grouping voltages.

FIG. 13throughFIG. 16are schematic graphs of a memory programming operation according to an exemplary embodiment of the present invention.

With reference toFIG. 13, it is assumed that in the first programming process, the memory control circuit unit104instructs the rewritable non-volatile memory module106to program the target memory cells by using the initial program voltage Vi. Then, the rewritable non-volatile memory module106applies the verification voltage Vverifyto the target memory cells, and the memory control circuit unit104determines whether the first programming result of the first programming process meets a predetermined programming result. For instance, the memory control circuit unit104may determine whether all the storage states of the target memory cells are in the accurate storage state corresponding to the write data. If all the storage states of the target memory cells are not in the accurate storage state corresponding to the write data, the memory control circuit unit104instructs the rewritable non-volatile memory module106to group the target memory cells by using the grouping voltages VG1to VG4. It may be noted that the grouping voltages VG1to VG4has different voltage levels. For instance, the grouping voltage VG1may be smaller than the grouping voltage VG2, the grouping voltage VG2may be smaller than the grouping voltage VG3, and the grouping voltage VG3may be smaller than the grouping voltage VG4.

With reference to bothFIG. 11andFIG. 14, it is assumed that the memory control circuit unit104instructs to program the target memory cells into programming groups A1to E1by using the grouping voltages VG1to VG4, the memory control circuit unit104instructs the rewritable non-volatile memory module106to perform the second programming process on the target memory cells by using a plurality of write voltages (also referred to as program voltages) respectively corresponding to the programming groups A1to E1. For instance, in the second programming process, the rewritable non-volatile memory module106may apply a program voltage VA1to the target memory cells in the programming group A1, apply a program voltage VB1to the target memory cells in the programming group B1, apply a program voltage VC1to the target memory cells in the programming group C1, apply a program voltage VD1to the target memory cells in the programming group D1, and apply a program voltage VE1to the target memory cells in the programming group E1. However, in another exemplary embodiment, the first programming process and the second programming process may also refer to any two continuous or discontinuous programming processes in the ISPP model, which is not limited to the above.

It may be noted that in the present exemplary embodiment, the memory control circuit unit104instructs the rewritable non-volatile memory module106to apply the program voltages VA1to VE1with different voltage levels by looking up in a look-up table according to the threshold voltage distribution of each of the programming groups A1to E1. According to looking-up result, the memory control circuit unit104instructs the rewritable non-volatile memory module106to apply a high-level program voltage to the target memory cells in the programming groups with a lower threshold voltage distribution. For instance, the threshold voltages of the target memory cells in the programming group E1is greater than the threshold voltages of the target memory cells in the programming group D1, and thus, the program voltage VE1applied to the programming group E1is smaller than the program voltage VD1applied to the programming group D1. Likewise, the program voltage VD1applied to the programming group D1is smaller than the program voltage VC1applied to the programming group C1, the program voltage VC1applied to the programming group C1is smaller than the program voltage VB1applied to the programming group B1, and the program voltage VB1applied to the programming group B1is smaller than the program voltage VA1applied to the programming group A1. In addition, the program voltages used in the second programming process is greater than the program voltages used in the first programming process. For instance, referring toFIG. 14, the program voltage VE1is greater than the initial program voltage Vi. Additionally, in another exemplary embodiment, the program voltages VA1to VE1may also be obtained by modifying the previously applied program voltages in previous programming process according to the threshold voltage distribution of each of the programming groups A1to E1.

With reference toFIG. 15, after performing the second programming process on the target memory cells, the rewritable non-volatile memory module106applies the verification voltage Vverifyto the target memory cells, and the memory control circuit unit104determines whether a programming result (also referred to as a second programming result) of the second programming process meets the predetermined programming result corresponding to the write data. If the second programming result does not meet the predetermined programming result, the memory control circuit unit104continues to perform another grouping operation on the target memory cells. For instance, the memory control circuit unit104may instruct the rewritable non-volatile memory module106to apply grouping voltages VG5to VG8to the target memory cells to re-group the target memory cells. It may be noted that after the second programming process is performed on the target memory cells, the threshold voltages of the target memory cells are increased, and thus, the grouping voltages VG5to VG8are correspondingly increased. For instance, a voltage level of the grouping voltage VG5is greater than a voltage level of the grouping voltage VG1; the voltage level of the grouping voltage VG6is greater than a voltage level of the grouping voltage VG2; the voltage level of the grouping voltage VGAis greater than a voltage level of the grouping voltage VG3; and the voltage level of the grouping voltage VG8is greater than a voltage level of the grouping voltage VG4. Details with respect to how to group the target memory cells has been described above and will not be repeated. In addition, the number of the grouping voltages VG5to VG8may also be more or fewer, which is not limited in the present invention.

With reference toFIG. 16, it is assumed that the target memory cells are grouped into the programming groups A2to E2according to the grouping voltages VG5to VG8. The threshold voltages of the target memory cells in the programming group E2are greater than the threshold voltages of the target memory cells in the programming group D2; the threshold voltages of the target memory cells in the programming group D2are greater than the threshold voltages of the target memory cells in the programming group C2; the threshold voltages of the target memory cells in the programming group C2are greater than the threshold voltages of the target memory cells in the programming group B2; and the threshold voltages of the target memory cells in the programming group B2are greater than the threshold voltages of the target memory cells in the programming group A2. The memory control circuit unit104instructs the rewritable non-volatile memory module106to apply program voltages VA2to VE2respectively to the programming groups A2to E2. Therein, the program voltage VA2is applied to the programming group A2, the program voltage VB2is applied to the programming group B2, and so on. A voltage level of each of the program voltage VA2to VE2may be obtained by looking up in a look-up table according to the threshold voltage distribution of each of the programming groups A2to E2. Alternatively, the voltage level of each of the program voltage VA2to VE2may also be obtained by modifying the program voltage VA1to VE1according to the threshold voltage distribution of each of the programming groups A2to E2, which is not limited in the present invention. Additionally, in the present exemplary embodiment, the program voltage VE2is higher than the program voltage VE1; the program voltage VD2is higher than the program voltage VD1; the program voltage VC2is higher than the program voltage VC1; the program voltage VB2is higher than the program voltage VB1; and the program voltage VA2is higher than the program voltage VA1.

It is to be mentioned that the present invention is not intent to limit the number and the time points to perform the grouping operation during a plurality of programming processes of the same write data. For instance, in an exemplary embodiment, before each programming process is performed, the grouping operation is performed. Alternatively, the memory control circuit unit104may also perform the grouping operation directly on the unprogrammed target memory cells (i.e., the memory cells in an erasing state). Thereafter, the memory control circuit unit104may perform all the subsequent programming process based on the grouping result or re-perform a grouping operation before any certain programming processes.

FIG. 17Ais a schematic graph of grouping the memory cells according to another exemplary embodiment of the present invention.FIG. 17Bis a schematic graph of a memory programming operation according to another exemplary embodiment of the present invention.

With reference toFIGS. 17A and 17B, it is assumed that the threshold voltage distribution of the target memory cells in the erasing state is threshold voltage distribution D5′. Before performing a programming process on the target memory cells, the memory control circuit unit104may instruct to set grouping voltages VG1′ to VG4′ according to the threshold voltage distribution D5′ and apply the grouping voltages VG1′ to VG4′ to the target memory cells for grouping. Alternatively, the memory control circuit unit104may also group the target memory cells in the erasing state according to historical grouping information of the target memory cells. For instance, the memory control circuit unit104may group the target memory cells into programming groups A1′ to E1′. Then, the memory control circuit unit104may instruct the rewritable non-volatile memory module106to apply corresponding program voltages VA1′ to VE1′ to the programming groups A1′ to E1′. For instance, after the program voltages VA1′ to VE1′ are applied, the threshold voltage distribution of the target memory cells may become threshold voltage distribution D6′. Then, the memory control circuit unit104determines whether the storage states of the target memory cells are in the accurate storage state corresponding to the write data according to the verification voltage Vverify. Since voltage levels of the target memory cells in the threshold voltage distribution D6′ are all smaller than the verification voltage Vverify, the memory control circuit unit104determines that the storage states of the target memory cells are not in the accurate storage state corresponding to the write data and continue to perform a subsequent programming process on the target memory cells. In the present exemplary embodiment, before performing the subsequent programming process, the memory control circuit unit104re-groups the target memory cells. For instance, the memory control circuit unit104may instruct to apply grouping voltages VG5′ to VG8′ to the target memory cells to group the target memory cells into programming groups A2′ to E2′. Thereby, in the subsequent programming process, the memory control circuit unit104may instruct the rewritable non-volatile memory module106to apply corresponding program voltages VA2′ to VE2′ to program the target memory cells according to the programming groups A2′ to E2′. Details with respect to how to perform the grouping operation and to group the memory cells by using the corresponding program voltages has been described above and will not be repeated.

It is to be mentioned that in the exemplary embodiment illustrated inFIG. 17B, the initial programming process for programming the target memory cells in the erasing state uses the plurality of program voltages VA1′ to VE1′. However, in another exemplary embodiment illustrated inFIG. 17B, even though the target memory cells are grouped, the initial programming process for programming the target memory cells in the erasing state may use only one initial program voltage, e.g., one of the program voltages VA1′ to VE1′ or any one adaptive program voltage. Additionally, in an exemplary embodiment, the memory control circuit unit104only groups the target memory cells according to the programming result of the initial program voltage after performing the initial programming process, and the grouping result may be continuously used until the target memory cells are programmed to be in the accurate storage state. Alternatively, the memory control circuit unit104may re-perform a grouping operation before any programming process after the initial programming process. Additionally, in another exemplary embodiment, the memory control circuit unit104may stop performing any other grouping operation after the number of performing the grouping operation on the target memory cells reaches a maximum number of grouping and perform one or more subsequent programming processes according to programming groups obtained in the last grouping operation. For instance, if it is assumed that the maximum number of grouping is 2, then after performing the grouping operation on the target memory cells for twice, the memory control circuit unit104performs the subsequent programming processes directly according to the programming groups obtained in the second grouping operation.

FIG. 18is a schematic graph of a memory programming operation according to another exemplary embodiment of the present invention.

With reference toFIG. 18, it is assumed that the memory control circuit unit104respectively performs the grouping operation for twice before two programming processes after the initial programming process. After the memory control circuit unit104instructs to apply the program voltages VA2to VE2to the target memory cells, if the memory control circuit unit104determines that the storage states of the target memory cells are not all in the accurate storage state and the number of the grouping operations reach the maximum number of grouping (e.g., twice), then the memory control circuit unit104no longer groups the target memory cells in the subsequent programming process for writing the same data. For instance, in the next programming process, the memory control circuit unit104respectively applies the program voltages VA3to VE3to the target memory cells in the programming groups A2to E2directly according to the programming groups A2to E2obtained by the second grouping operation.

FIG. 19is a schematic block diagram illustrating a memory control circuit unit according to another exemplary embodiment of the present invention.

With reference toFIG. 19, the memory control circuit unit104includes a memory management circuit202, a host interface204, a memory interface206, buffer memory208, an error detecting and correcting (ECC) circuit210and a power management circuit212.

The memory management circuit202is configured to control the overall operation of the memory control circuit unit104. Specifically, the memory management circuit202has a plurality of control commands. When the memory storage device10is in operation, the control commands are executed to perform operations such as data writing, reading and erasing operations.

In the present exemplary embodiment, the control commands of the memory management circuit202are implemented in the form of firmware. For instance, the memory management circuit202has a microprocessor unit (not shown) and a read-only memory (not shown), and the control commands are burnt into the read-only memory. When the memory storage device10is in operation, the control commands are executed by the microprocessor to perform the operations such as data writing, reading and erasing operations. The aforementioned description with respect to the operations of the memory control circuit unit104may be applied to the memory management circuit202.

In another exemplary embodiment, the control commands of the memory management circuit202may also be stored in a form of programming codes in a specific area of the rewritable non-volatile memory module106(e.g., the system area specifically designated for storing the system data). Besides, the memory management circuit202has a microprocessor (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory stores boot codes, and when the memory control circuit unit104is enabled, the microprocessor unit first executes the boot codes to load the control instructions stored in the rewritable non-volatile memory module106to the random access memory of the memory management circuit202. Afterwards, the microprocessor unit executes the control commands for various data operations such as data writing, reading and erasing operations.

In another exemplary embodiment, the control commands of the memory management circuit202may also be implemented in the hardware form. For instance, the memory management circuit202includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit, and the data processing circuit are electrically connected to the microcontroller. Therein, the memory cell management circuit is configured to manage physical erasing units of the rewritable non-volatile memory module106; the memory writing circuit is configured to issue a write command (i.e., a write command sequence) to the rewritable non-volatile memory module106to write data into the rewritable non-volatile memory module106; the memory reading circuit is configured to is configured to issue a read instruction (i.e., a read instruction sequence) to the rewritable non-volatile memory module106to read data from the rewritable non-volatile memory module106; the memory erasing circuit is configured to issue an erase instruction to the rewritable non-volatile memory module106to erase data from the rewritable non-volatile memory module106; and the data processing circuit is configured to process data to be written into the rewritable non-volatile memory module106and data to be read from the rewritable non-volatile memory module106. Each of the write command sequence, the read instruction sequence and erase instruction may include one or a plurality of program codes or instructions.

The host interface204is coupled to the memory management circuit202and configured to receive and identify the commands and data transmitted by the host system11. In other words, the commands and data from the host system11are transmitted to the memory management circuit202through the host interface204. In the present exemplary embodiment, the host interface204complies with the SATA standard. However, it be understood that the present invention is not limited thereto, and the host interface204may also comply with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the MS standard, the MMC standard, the CF standard, the IDE standard or other suitable data transmission standard.

The memory interface206is coupled to memory management circuit202and configured to access the rewritable non-volatile memory module106. Namely, data to be written into the rewritable non-volatile memory module106is converted to a format acceptable for the rewritable non-volatile memory module106by the memory interface206. Specifically, if the memory management circuit202is about to access the rewritable non-volatile memory module106, the memory interface206transmits a corresponding instruction sequence. The instruction sequence may include one or a plurality of signals, or data on a bus. For instance, a read instruction sequence may contain information, such as a read identification code, a memory address, and so on.

The buffer memory208is coupled to memory management circuit202and configured to temporarily store the data and instructions from the host system1000or data from the rewritable non-volatile memory module106. The memory control circuit unit404configures to temporarily store the data from the host system11or the data from the rewritable non-volatile memory module106in the buffer memory208, such that the data are organized to be in a predetermined unit size or a transmission unit size and written into the rewritable non-volatile memory module106or transmitted back to the host system11. In addition, the buffer memory208may also temporarily store system management data used by the memory control circuit unit104, such as a file allocation table or a logical-physical unit mapping table.

The ECC circuit210is coupled to the memory management circuit202and configured to perform an error checking and correcting (ECC) procedure to ensure accuracy of data. Specifically, when the memory management circuit202receives a write command from the host system11, the ECC circuit210may generate a corresponding error correcting code (ECC code) and/or error detecting code (EDC) for data corresponding to the write command. The memory management circuit202may write the data corresponding to the writing command and the corresponding ECC code into the rewritable non-volatile memory module106. Thereafter, when the memory management circuit202reads the data from the rewritable non-volatile memory module106, the corresponding ECC code and/or EDC are also read, and the ECC circuit210performs the ECC procedure on the read data according to the ECC code and/or the EDC.

The power management circuit212is coupled to the memory management circuit202and configured to control a power source of the memory storage device10.

It is to be mentioned that in an exemplary embodiment, a specific program voltage may be applied to a specific programming group through the control of software or firmware. Alternatively, in another exemplary embodiment, the program voltages applied to different programming groups may be controlled through hardware switches. For instance, if the program voltages applied to different programming groups are controlled by hardware switches, one or more control switches or resisters may be disposed on voltage supply paths for supplying the programming voltages. Each control switch or resister is configured to conduct on a voltage supply path for the memory cells belonging to the same programming group. Through conducting on or switching voltage supply paths coupled to different memory cells, the memory cells belonging to different programming groups may be selectively programmed. Taking the exemplary embodiment illustrated inFIG. 14for example, if it is assumed that the programming group A1is to be programmed by using the program voltage VA1, the voltage supply path coupled to the target memory cells belonging to the programming group A1is conducted on, and the voltage supply path coupled to the target memory cells not belonging to the programming group A1is cut off. Thereby, the program voltage VA1is only provided to the target memory cells belonging to the programming group A1for programming through the conducted-on voltage supply path. When the program voltage VB1is to be used to program the programming group B1, only the voltage supply path coupled to the target memory cells belonging to the programming group B1is conducted on to program the programming group B1, and so on, likewise.

FIG. 20is a flowchart illustrating a memory programming method according to an exemplary embodiment of the present invention.

With reference toFIG. 20, in step S2001, the memory control circuit unit104(or the memory management circuit202) performs a first programming process of a plurality of memory cells according to write data and obtains a first programming result of the first programming process. In step S2003, the memory control circuit unit104(or the memory management circuit202) instructs to group the memory cells into a plurality of programming groups according to the first programming result. In step S2005, the memory control circuit unit104(or the memory management circuit202) instructs to perform a second programming process on the memory cells according to the write data. The second programming process includes programming a first programming group among the programming groups by using a first program voltage and programming a second programming group among the programming groups by using a second program voltage. Therein, the first program voltage and the second program voltage are different.

FIG. 21is a schematic graph illustrating a threshold voltage distribution of the programmed memory cells according to an exemplary embodiment of the present invention.

With reference toFIG. 15andFIG. 21, it is assumed that the memory control circuit unit104instruct to program a plurality of memory cells according to write data having data bits of “0”, and then after a first programming process is performed by using the initial program voltage Vi, a threshold voltage distribution of the memory cells is changed from the threshold voltage distribution D1to the threshold voltage distribution D2. Before the second programming process, the memory control circuit unit104instructs to group the memory cells by using the grouping voltages VG1to VG4, and after the memory cells are grouped, the second programming process is performed by using the corresponding program voltages VA1to VE1according to the programming groups A1to E1that the memory cells belong to. After the second programming process is performed, the threshold voltage distribution of the memory cells are changed from the threshold voltage distribution D2to a threshold voltage distribution D7. In this way, after other programming processes are performed, the threshold voltage distribution of the memory cells is changed from the threshold voltage distribution D7to a threshold voltage distribution D8. Then, since the threshold voltages of the memory cells are higher than the verification voltage Vverify, it represents that the storage states of the memory cells are all programmed as “0”.

According to bothFIG. 3andFIG. 21, in the memory programming method of the present invention, the threshold voltage distribution range of the memory cells may be effectively narrowed in the process of programming the memory cells. Namely, the threshold voltage distribution of the memory cells may be concentrated. Additionally, the highest threshold voltage in the threshold voltage distribution D8of the memory cells inFIG. 21may be smaller than the highest threshold voltage in the threshold voltage distribution D4of the memory cells inFIG. 3.

To summarize, in the memory programming method, the memory control circuit unit and the memory storage device provided by the present invention, the memory cells can be grouped, and the program voltages applied to different groups can be correspondingly adjusted according to the threshold voltage distribution (or the write speed) of the memory cells, so as to enhance the accuracy of programming the memory cells and extend the lifespan of the memory storage device. Moreover, the range of the threshold voltage distribution of the programmed memory cells can be narrowed, so as to reduce the possibility of error occurring in the data stored in the memory storage device.

The previously described exemplary embodiments of the present invention have the advantages aforementioned, wherein the advantages aforementioned not required in all versions of the invention.