Method for fabricating single diffusion break structure directly under a gate line

A method for fabricating semiconductor device includes the steps of: forming a first active region and a second active region extending along a first direction on a substrate; forming a first single diffusion break (SDB) structure extending along a second direction between the first active region and the second active region; and forming a first gate line extending along the second direction intersecting the first active region and the second active region. Preferably, the first SDB structure is directly under the first gate line between the first active region and the second active region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating semiconductor device, and more particularly to a method for forming single diffusion break (SDB) structure directly under a gate line.

2. Description of the Prior Art

With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.

In current FinFET fabrication, after shallow trench isolation (STI) is formed around the fin-shaped structure part of the fin-shaped structure and part of the STI could be removed to form a trench, and insulating material is deposited into the trench to form single diffusion break (SDB) structure or isolation structure. However, the integration of the SDB structure and metal gate fabrication still remains numerous problems. Hence how to improve the current FinFET fabrication and structure has become an important task in this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a first active region and a second active region extending along a first direction on a substrate; forming a first single diffusion break (SDB) structure extending along a second direction between the first active region and the second active region; and forming a first gate line extending along the second direction intersecting the first active region and the second active region. Preferably, the first SDB structure is directly under the first gate line between the first active region and the second active region.

According to another aspect of the present invention, a semiconductor device includes: a first active region and a second active region extending along a first direction on a substrate; a first single diffusion break (SDB) structure extending along a second direction between the first active region and the second active region; and a first gate line extending along the second direction intersecting the first active region and the second active region. Preferably, the first SDB structure is directly under the first gate line between the first active region and the second active region.

DETAILED DESCRIPTION

Referring toFIGS. 1-3, in whichFIG. 1is a top view illustrating a semiconductor device according to an embodiment of the present invention,FIG. 2illustrates a cross-sectional view ofFIG. 1along the sectional line AA′, andFIG. 3illustrates a cross-sectional view ofFIG. 1along the sectional line BB′. As shown inFIGS. 1-3, a substrate12such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, and at least an active region such as active regions14,16,18extending along a first direction (such as X-direction) are defined on the substrate12. Next, a plurality of fin-shaped structures20are formed on each of the active regions14,16,18on the substrate12and a shallow trench isolation (STI)22is formed around the fin-shaped structures20. It should be noted that even though four fin-shaped structures20are disposed on each of the active regions14,16,18on the substrate12in this embodiment, it would also be desirable to adjust the number of fin-shaped structures20depending on the demand of the product, which is also within the scope of the present invention.

Preferably, the fin-shaped structures20of this embodiment could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained. It should be noted that some of the fin-shaped structures not removed completely could be remained on the active regions14,16,18to form bumps24after the fin cut process, in which the top surface of the bumps24is significantly lower than the top surface of the fin-shaped structures20within the active regions14,16,18but slightly higher than the top surface of the substrate12.

Alternatively, the fin-shaped structures20could also be obtained by first forming a patterned mask (not shown) on the substrate,12, and through an etching process, the pattern of the patterned mask is transferred to the substrate12to form the fin-shaped structures20. Moreover, the formation of the fin-shaped structures20could also be accomplished by first forming a patterned hard mask (not shown) on the substrate12, and a semiconductor layer composed of silicon germanium is grown from the substrate12through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures20. These approaches for forming fin-shaped structure are all within the scope of the present invention.

Next, a shallow trench isolation (STI)22is formed around the fin-shaped structures20or surrounding the active regions14,16,18as shown inFIG. 1. In this embodiment, the formation of the STI22could be accomplished by conducting a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate12and covering the fin-shaped structures20entirely. Next, a chemical mechanical polishing (CMP) process along with etching process are conducted to remove part of the silicon oxide layer so that the top surface of the remaining silicon oxide is slightly lower than the top surface of the fin-shaped structures20for forming the STI22. Preferably, the fin-shaped structures20disposed on the active regions14,16,18are disposed to protrude above the STI22while the STI22covers the bumps24entirely.

Next, a plurality of single diffusion break (SDB) structures are formed on the substrate12. For instance, SDB structures26,28are formed on two ends of the active region14, SDB structures30,32are formed adjacent to the active region14, SDB structures34,36,38are formed in the active region16, SDB structures42,44are formed in the active region18, and a SDB structures40is formed extending from the active region16to the active region18.

In this embodiment, the formation of the SDB structures26,28,30,32,34,36,38,40,42,44could be accomplished by first conducting a photo-etching process along a second direction (such as Y-direction) to remove part of the fin-shaped structures20and part of the STI22within the active regions14,16,18to form trenches (not shown) also extending along the Y-direction, and then depositing a dielectric material into the trenches to form SDB structures. It should be noted that even though an additional etching process is conducted to divide the fin-shaped structures20to form SDB structures26,28,30,32,34,36,38,40,42,44after the STI22is formed in this embodiment, according to another embodiment of the present invention, it would also be desirable to conduct the aforementioned etching process to form trenches used for defining the SDB structures26,28,30,32,34,36,38,40,42,44, and then deposit a dielectric material into the trenches and around the fin-shaped structures20to form SDB structures26,28,30,32,34,36,38,40,42,44and the STI22at the same time. In other words, the SDB structures26,28,30,32,34,36,38,40,42,44could be formed either after the formation of STI22is completed or at the same time with the STI22, which are all within the scope of the present invention.

Preferably, the SDB structures26,28,30,32,34,36,38,40,42,44in this embodiment and the STI22could be made of same material or different while both the SDB structures26,28,30,32,34,36,38,40,42,44and the STI22could be selected from the group consisting of silicon oxide and silicon nitride. For instance, even though the STI22is preferably made of silicon oxide while the SDB structures26,28,30,32,34,36,38,40,42,44are made of silicon nitride in this embodiment, according to another embodiment of the present invention, both the STI22and the SDB structures26,28,30,32,34,36,38,40,42,44could all be made of silicon oxide, which is also within the scope of the present invention.

Next, gate lines46,48,50,52,54,56,58,60,62,64,66,68,70or gate structures are formed on the fin-shaped structures20intersecting the active regions14,16,18and the STI22. In this embodiment, the formation of the gate lines46,48,50,52,54,56,58,60,62,64,66,68,70could be accomplished by a gate first process, a high-k first approach from a gate last process, or a high-k last approach from the gate late process. For instance, a gate dielectric layer72or interfacial layer, a gate material layer74made of polysilicon, and a selective hard mask could be formed sequentially on the substrate12, and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer74and part of the gate dielectric layer72through single or multiple etching processes. After stripping the patterned resist, gate lines46,48,50,52,54,56,58,60,62,64,66,68,70each composed of a patterned gate dielectric layer72and a patterned material layer74are formed on the fin-shaped structure20and the STI22.

As shown inFIG. 1, the gate lines46,48,50,52,54,56,58,60,62,64,66,68,70are extending along the same second direction (such as Y-direction) as the SDB structures26,28,30,32,34,36,38,40,42,44and intersecting the active regions14,16,18and the fin-shaped structures20, in which each of the SDB structures26,28,30,32,34,36,38,40,42,44are disposed directly under each of the gate lines46,48,50,52,54,56,58,60,62,64,66,68,70respectively. For instance, the SDB structures26is directly under the gate line48, the SDB structures32,42are directly under the gate line50, the SDB structure34is directly under the gate line56, the SDB structures28,36,44are directly under the gate line60, the SDB structures30,38are directly under the gate line64, and the SDB structure40is directly under the gate line68.

In this embodiment, dummy isolation structures76could also be disposed in the STI22outside the active regions14,16,18, the fin-shaped structures20, and the gate lines46,48,50,52,54,56,58,60,62,64,66,68,70. Preferably, no gate lines are disposed on top of the dummy isolation structures76, the dummy isolation structures76and the SDB structures26,28,30,32,34,36,38,40,42,44are formed through the same step, and the dummy isolation structure76and the STI22are preferably made of different material. For instance, the STI22in this embodiment is made of silicon oxide while the dummy isolation structures76are made of silicon nitride.

Preferably, the SDB structure30is disposed directly under the gate line64while not intersecting any of the active regions and fin-shaped structures30, the SDB structure38is disposed directly under the same gate line64while intersecting the active region16and the fin-shaped structures20, and the SDB structure40is extending from one edge of the active region16to another edge of the active region18while disposed directly under the gate line68and intersecting the active regions16,18and the fin-shaped structures20. In other words, the SDB structure40is disposed directly under the gate line68intersecting the active region16, directly under the gate line68between the active region16and the active region18, and directly under the gate line68intersecting the active region18.

As shown inFIGS. 2-3, the top surface of the SDB structures26,28,30,32,34,36,38,40,42,44is even with the top surface of the STI22while the bottom surface of the SDB structures26,28,30,32,34,36,38,40,42,44and the STI22could have different profile and/or different depths depending on whether the SDB structures26,28,30,32,34,36,38,40,42,44intersect the fin-shaped structures20. For instance, as shown inFIG. 2, since the SDB structure30does not intersect any of the active regions14,16,18or fin-shaped structures20, the bottom surface of the SDB structure30is substantially planar and slightly lower than the bottom surface of the adjacent STI22. The bottom surface of the SDB structure38on the other hand reveals a jagged pattern or bumps since the profile of the fin-shaped structures20was etched downward during the aforementioned etching process. It should also be noted that even though the bottom of the SDB structure30is even with the bottom of the SDB structure38in this embodiment, the bottom of the SDB structure30could also be slightly lower than or higher than the bottom surface of the SDB structure38, which is also within the scope of the present invention.

Next, MOS transistor fabrication process could be conducted by forming spacers adjacent to the gate lines46,48,50,52,54,56,58,60,62,64,66,68,70, forming source/drain regions and/or epitaxial layers in the fin-shaped structures20adjacent to two sides of the spacers, and selectively forming a salicide (not shown) on the surface of the source/drain regions and/or epitaxial layers. Since the fabrication of MOS transistors is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.