CHIP-SUBSTRATE COMPOSITE SEMICONDUCTOR DEVICE

A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

TECHNICAL FIELD

This disclosure relates generally to the field of semiconductor devices, and in particular to the field of high-voltage semiconductor transistor chips.

BACKGROUND

Packaging of high-voltage (HV) semiconductor chips involves a number of specific problems. Electrode geometries, their spacing and positions must be determined with respect to the HV requirements. For example, the HV edge of the chip is very sensitive to electric field degradation, and any change in the vicinity of the HV edge may adversely affect the edge termination of the chip. For example, there must be a relatively large distance between the semiconductor chip edge and a low-voltage (LV) terminal element (e.g., source terminal element, gate terminal element, sense terminal element) that crosses the chip edge to allow lateral exit of field lines between the chip edge and the LV terminal element. It is also difficult to provide protection against ion or moisture diffusion into the semiconductor chip at the chip edge.

Further aspects aim at cost efficient manufacturing processes and customer benefits in view of product versatileness and package design.

SUMMARY

According to an aspect of the disclosure a semiconductor device comprises a high-voltage semiconductor transistor chip comprising a front side and a backside. A LV load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further comprises a dielectric inorganic substrate comprising a first side and a second side opposite the first side. A pattern of first metal structures is running through the dielectric inorganic substrate, wherein the pattern of first metal structures is connected to the LV load electrode. At least one second metal structure is running through the dielectric inorganic substrate, wherein the second metal structure is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

DETAILED DESCRIPTION

As used in this specification, the terms “electrically connected” or “connected” or similar terms are not meant to mean that the elements are directly contacted together; intervening elements may be provided between the “electrically connected” or “connected” elements, respectively. However, in accordance with the disclosure, the above-mentioned and similar terms may, optionally, also have the specific meaning that the elements are directly contacted together, i.e. that no intervening elements are provided between the “electrically connected” or “connected” elements, respectively.

Further, the words “over” or “beneath” with regard to a part, element or material layer formed or located “over” or “beneath” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “directly on” or “directly under”, e.g. in direct contact with, the implied surface. The word “over” or “beneath” used with regard to a part, element or material layer formed or located “over” or “beneath” a surface may, however, either be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “indirectly on” or “indirectly under” the implied surface, with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer.

FIG.1illustrates a schematic cross-sectional view of an exemplary semiconductor device100. The semiconductor device100includes a semiconductor transistor chip110. The semiconductor transistor chip110is a HV semiconductor transistor chip that operates at a supply voltage (e.g. drain voltage) equal to or higher than, e.g., 100 V, 200 V, 300 V, 400 V, 500 V, 600 V, 700 V, 800 V, 900 V, or 1000 V. In particular, the semiconductor transistor chip110may operate at a supply voltage in a range between 300 V and 800 V.

The semiconductor transistor chip110has a front side110A and a backside110B. A LV load electrode120and a control electrode130are disposed on the front side110A of the semiconductor transistor chip110. A HV load electrode (not shown) is disposed either on the front side110A or on the backside110B of the semiconductor transistor chip110.

The semiconductor transistor chip110includes an integrated power device such as, e.g., a power transistor. For instance, the semiconductor transistor chip110may be configured as including one or more MISFETs (Metal Insulator Semiconductor Field Effect Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), HEMTs (High Electron Mobility Transistors) or bipolar transistors. The semiconductor transistor chip110may be a vertical transistor device.

A dielectric inorganic substrate150is attached to the front side110A of the semiconductor transistor chip110. More specifically, the front side110A of the semiconductor transistor chip110is attached to a first surface150A of the dielectric inorganic substrate150by, e.g., a wafer bond connection (not shown). The front side110A of the semiconductor transistor chip110may be completely covered by the dielectric inorganic substrate150. In particular, the dielectric inorganic substrate150may be a glass substrate and the wafer bond connection may, e.g., be a glass frit connection.

The dielectric inorganic substrate150comprises a pattern of first metal structures160. The first metal structures160may be accommodated in recesses of the dielectric inorganic substrate150. The first metal structures160run through the dielectric inorganic substrate150, wherein the pattern of first metal structures160is connected to the LV load electrode120. The LV load electrode120may, e.g., be the source electrode or the emitter electrode of the semiconductor transistor chip110.

The dielectric inorganic substrate150further comprises at least one second metal structure170running through the dielectric inorganic substrate150. The second metal structure170is connected to the control electrode130. The control electrode130may, e.g., form the gate electrode of the semiconductor transistor chip110.

The first and second metal structures160,170may be formed of plated metal pillars. To this end, before the dielectric inorganic substrate150is bonded to the wafer from which the semiconductor transistor chip110is later singulated, recesses or through holes are formed in the dielectric inorganic substrate150. The first and second metal structures160,170may then be formed in the recesses or through holes of the dielectric inorganic substrate150by metal plating as will be described in greater detail further below.

The dielectric inorganic substrate150may be a glass substrate or a semiconductor substrate. If the metal structures160,170are required to be electrically insulated from each other, glass or an intrinsic semiconductor substrate material or a semiconductor substrate having recesses with insulated side walls could be used. Recesses with insulated side walls may, e.g., be formed by applying an insulating layer (e.g. a silicon oxide layer or a silicon nitride layer) to the side walls of the recesses in which the first and second metal structures160,170are accommodated.

As will be described in more detail further below, the dielectric inorganic substrate150may optionally comprise or be composed of a plurality of stacked dielectric inorganic substrate layers150_1,150_2, . . . .

The semiconductor device100may be referred to as a composite chip or substrate-semiconductor hetero-structure. Such composite chip may be diced out of a composite wafer which may comprise a semiconductor wafer and a dielectric inorganic substrate wafer bonded together by a wafer bond connection.

Such composite chips offer a number of advantages, especially for designing and/or packaging HV transistor chips.

First, by integrating the permanent dielectric inorganic substrate150together with the semiconductor transistor chip110in a package, the dielectric inorganic substrate150may be used as an ‘adaptor’ that can be appropriately structured and metallized to make the composite chip directly solderable to a package-internal terminal structure or package-external circuitry such as, e.g., a leadframe or an application board or other internal or external terminal structures of a given geometry.

For example, the first metal structures160may end in a substrate metallization120M representing the LV load electrode120of the semiconductor device (composite chip)100and extending on a second surface150B of the dielectric inorganic substrate150. Accordingly, the one or more second metal structures170may end in a substrate metallization130M which represents the control electrode130of the semiconductor device (composite chip)100. As the substrate metallizations120M and130M are spaced apart from the semiconductor transistor chip110by the dielectric inorganic substrate150, constrains in terms of their geometries are substantially relaxed. For this and other reasons, the geometries of the LV substrate metallizations120M,130M may be changed with regard to the geometries of the LV load electrode120and the control electrode130, respectively.

In other words, the dielectric inorganic substrate150may e.g. be useful as a ‘chip electrode layout adaptor’ between the semiconductor transistor chip110and a terminal geometry provided internal (e.g. by a leadframe) or external (e.g. by an application board) of a HV semiconductor package which includes the semiconductor device100. This allows direct bonding of the ‘adapted’ chip front side electrodes (namely the substrate metallizations120M,130M) to a terminal structure (e.g. leadframe) without requiring changes in chip processing when the terminal structure geometry (e.g. leadframe design) is modified. Further, such ‘chip electrode layout adaptor’ may be useful if already available chip types are to be packaged in a package using a given terminal structure geometry (e.g. leadframe geometry).

As a second aspect, the implementation of the dielectric inorganic substrate150allows to process very thin semiconductor wafers when being supported by the dielectric inorganic substrate wafer. Therefore, HV semiconductor transistor chips110with advanced electrical and thermal properties may be used.

Third, in the case of HV semiconductor transistor chips110, there needs to be a relatively large spacing between the front side110A of the semiconductor transistor chip110and a LV connection element (e.g. LV load electrode connection element or control electrode connection element) that extends laterally across a chip edge110E of the semiconductor transistor chip110. This spacing is required because the chip edge110E of HV transistor chips110is typically at a rapidly changing HV potential.FIG.1illustrates a HV load electrode ring140R extending adjacent to the edge110E of the semiconductor transistor chip110, wherein the HV load electrode ring140R is held on the potential of the HV load electrode (not shown). The HV load electrode may, e.g., be the drain or collector electrode of the semiconductor transistor chip110.

For example, while the voltage fluctuations at the LV load electrode120and the control electrode130of the semiconductor transistor chip110are, e.g., between 0.1-3 V at the low voltage load electrode and, e.g., between 0-20 V at the control electrode, the voltage fluctuations at the edge110E of the semiconductor transistor chip110are between 0 V and e.g. 300 to 800 V or even 1000 V with a frequency of typically several 100 kHz. The relatively large spacing between the front side110A of the semiconductor transistor chip110and LV connecting elements (e.g. package terminals or a leadframe or conductor traces of an application board) extending across the edge110E of the semiconductor transistor chip110allow the field lines to escape laterally between the LV connecting elements (not shown) and the chip edge110E.

This distance is created by designing the dielectric inorganic substrate150with a sufficient thickness TS. Thus, the dielectric inorganic substrate150acts as an ‘extension’ to allow field lines to exit laterally between LV terminal elements and the HV chip edge110E. For example, the dielectric inorganic substrate150may have a thickness TS which may be equal to or greater than or less than 50 μm or 100 μm or 200 μm or 300 μm or 400 μm. While for SiC or other high bandgap semiconductor materials, a thickness TS of 50 μm may, e.g., be sufficient, Si semiconductor transistor chips110advantageously may use a dielectric inorganic substrate150of a thickness TS of equal to or greater than 100 μm.

The second surface150B of the dielectric inorganic substrate150may be (highly) planar. The second surface150B of the dielectric inorganic substrate150may be parallel with the backside110B of the semiconductor transistor chip110.

As apparent fromFIGS.2A and2B, the first metal structures160may be arranged in a densely packed array in the dielectric inorganic substrate150. Differently put, the dielectric inorganic substrate150may form a matrix for the pattern or array of first metal structures160. The percentage in volume of metal within the pattern or array of the first metal structures160in the dielectric inorganic substrate150may be high, e.g. equal to or greater than, e.g., 40% or 50% or 60% or 70% or 80%.

The pattern of first metal structures160may, e.g., be a regular array. A pitch of the pattern of first metal structures160may, e.g., be equal to or greater than or less than 15 μm or 17.5 μm or 20 μm or 22.5 μm or 25 μm or 27.5 μm or 30 μm. A distance between adjacent first metal structures160may, e.g., be equal to or greater than or less than 50 μm or 30 μm or 10 μm or 5 μm or 4 μm or 3 μm or 2 μm. The lateral dimension(s) of each first metal structure160may, e.g., be equal to or greater than or less than 12.5 μm or 15 μm or 17.5 μm or 20 μm or 22.5 μm or 25 μm or 27.5 μm. A a ratio of a distance between adjacent first metal structures160and a lateral dimension (e.g. diameter) of a first metal structure160may be equal to or less than 5 or 3 or 2 or 1.

Referring toFIG.2A, the dielectric inorganic substrate150may, e.g., have a polygonal, in particular rectangular shape.

By virtue of the dielectric inorganic substrate150, the semiconductor device100may have advanced heat dissipation properties. Heat dissipation in semiconductor devices100relies, inter alia, on the electrical interconnect between the semiconductor transistor chip110and a terminal structure (e.g. leadframe or application board or conductor traces of an application board, etc.) on which the semiconductor transistor chip110is mounted. Here, this electrical interconnect includes or is composed of the pattern of first metal structures160in the dielectric inorganic substrate150.

The pattern of first metal structures160can be optimized in terms of thermal conductivity and/or heat capacity. The more densely the first metal structures160are packed in the dielectric inorganic substrate150, the better the heat conductivity and the thermal capacity of the dielectric inorganic substrate150. Further, enhancing the thickness TS of the dielectric inorganic structure150increases the thermal capacity thereof, because more metal is held available in the dielectric inorganic structure150for transient heat absorption.

The second metal structure(s)170may be implemented the same way as described above for the first metal structures160, and reiteration is avoided for the sake of brevity. However, as the second metal structure(s)170connect(s) to a low current control electrode, it is also possible that only a single second metal structure (i.e. a single metal pillar connecting between the control electrode130and the substrate metallization130M of the control electrode) is sufficient.

Returning toFIG.2B, the first metal structures160may, e.g., have a polygonal (square, hexagonal, etc.) or rounded cross-section. A square cross-section shape is exemplarily shown inFIG.2B. A hexagonal cross-sectional shape may be beneficial as it provides for a particular high area packing density of metal in the dielectric inorganic structure150.

Each first metal structure160may be linear and/or have an axially symmetric cross-sectional shape. Furthermore, each first metal structure160may have a substantially constant cross-sectional shape along its extension through the dielectric inorganic substrate150. Variable-cross sectional shapes along the longitudinal extension such as, e.g., tapering shapes or bulges or thickenings are also possible.

Moreover, the pattern does not need to be designed as a regular array. Rather, the pattern may be composed of a plurality of different patterns or (e.g. regular) arrays. Such different patterns (e.g. sub-patterns) or arrays (e.g. sub-arrays) may distinguish from each other e.g. in terms of pitch and/or cross-sectional shape of the first metal structures160.

Generally, the dielectric inorganic substrate150offers a variety of approaches to become geometry and/or process independent from the semiconductor wafer. In particular, it is possible to relocate structures which are normally realized in or on the semiconductor transistor chip110partially or completely out of the semiconductor transistor chip110into or onto the dielectric inorganic substrate150. This makes it possible to provide the necessary area for a control pad on the second surface150B of the dielectric inorganic substrate150to fulfill all bond wire rules for a respective package. On the other hand, the area of the control electrode130on the semiconductor transistor chip110can be made very small, because it is not connected by a package terminal such as, e.g., a bond wire. This allows the area consumption of the control electrode130to be reduced in line with the shrinking semiconductor area of semiconductor devices100from generation to generation, thereby reducing the chip cost.

FIG.3Aillustrates an exemplary semiconductor device300. A control pad formed by the substrate metallization130M is disposed on the second surface150B of the dielectric inorganic substrate150. An area of the control pad (metallization130M) may be greater than an area of the control electrode130by, e.g., at least a factor 3 or 5 or 10 or 50 or 100. For example, the control electrode130may have an area with lateral dimensions between, e.g., 5 and 50 μm, in particular between 10 and 25 μm, which is sufficient for electrical bonding to a second metal structure170. On the other hand, the control pad (metallization130M) may have, for example, an area of 500 μm×500 μm sufficient for, e.g., wire bonding.

Hence, the area of the control electrode130on the semiconductor transistor chip110may be reduced to the area of a single second metal structure170(e.g. Cu pillar). Furthermore, it is possible that no separate control electrode (e.g. gate electrode) is required on the semiconductor transistor chip110, but a control electrode ring or a control electrode finger (e.g. gate ring or gate finger, seeFIGS.4A-4E) is used as a control electrode contact. In this case, the control electrode130, shown inFIGS.3A and3B, can even be omitted and would be replaced by a contact to the control electrode ring or control electrode finger. The advantage is a significantly reduced chip area for high impedance semiconductor devices300.

Differently put, the control electrode area on the semiconductor transistor chip110may be substantially smaller (or even zero) than on the top of the composite chip (semiconductor device300). Besides the better connectivity of the semiconductor device300and the possibility of reducing the chip size (see alsoFIG.3B), this approach may also be beneficial in that different packages may be serviced by combining with different control pad layouts (metallization130M layouts) without having to adjust the electrode layout on the semiconductor transistor chip110. This provides for chip cost advantages and reduction of the manufacturing complexity.

Another example of the semiconductor device300is shownFIG.3B. Here, the reduced area of the control electrode130is exploited to place the control pad (metallization130M) closer to the edge110E of the semiconductor transistor chip110than inFIG.3A(see arrow). In particular, the outer edge of the control pad (metallization130M) may be closer to the edge110E of the semiconductor transistor chip110than the outer edge of the control electrode130. Likewise, this may allow to reduce the overall size of the semiconductor transistor chip110, since the control pad (metallization130M) on the upper side of the dielectric inorganic substrate150can extend further into the chip edge region than would be possible directly on the semiconductor chip due to the greater distance (thickness TS) to the front side110A of the semiconductor transistor chip110. For example, as shown inFIG.3B, it is possible to overlap the control pad (metallization130M) with the HV load electrode ring140R.

Further, as shown for example inFIGS.1,3A and3B, the control electrode130may optionally be electrically connected to control electrode field plates326. The control electrode field plates326are vertical metal structures extending into the dielectric inorganic substrate150. The control electrode field plates326may be electrically connected to the substrate metallization130M and may form blind hole metal structures which do not extend through the dielectric inorganic substrate150. For example, as shown inFIG.3B, it is possible to overlap the control electrode field plates326with the HV load electrode ring140R.

Moreover, it is also possible to contact different chip areas directly to provide further pads at the second surface150B of the dielectric inorganic substrate150for, e.g. further control pads (gate pads), connections for a split gate or a temperature sensor etc.

FIGS.4A to4Eillustrate examples of an exemplary semiconductor device400. In semiconductor device400, the dielectric inorganic substrate150is used to improve chip area efficiency by rewiring a control electrode ring (so-called gate ring) and/or a control electrode finger (so-called gate finger) within the dielectric inorganic substrate150.

As known in the art, lateral gate structures such as gate rings (which surround the active area of the semiconductor transistor chip110) and gate fingers (which extend into the active area of the semiconductor transistor chip110) may be used to ensure a high performance (e.g. a high switching speed) of the semiconductor transistor chip110. Such lateral control electrode elements need to have a minimum width sufficient for avoiding electro-migration due to the relatively high gate current as well as a reduction of the distributed gate resistance. For low RDS(on)), the area consumption of such lateral gate structures is relatively high, e.g. about 10-100 μm in width for a gate ring and about 25-150 μm in width for gate fingers.

The dielectric inorganic substrate150allows to transform such lateral gate structures into vertical gate structures which are partly or completely located in the dielectric inorganic substrate150. Thereby, the chip area can be reduced since only the minimum electrically required width of such structures on the semiconductor transistor chip110needs to be maintained (while current can be outsourced into the vertical gate structures).

Referring toFIGS.4A and4B, the dielectric inorganic substrate150includes a control electrode ring (gate ring)430which surrounds an active area of the semiconductor transistor chip110in a vertical projection. At least a part of the control electrode ring430is embedded in the dielectric inorganic substrate150.

More specifically, the dielectric inorganic substrate150may be provided with one or more fourth metal structures432, which are connected to a control electrode chip ring434provided in the semiconductor transistor chip110. The control electrode chip ring434may be designed in the conventional way, however with a significantly smaller width since the electro-migration and the resistance of the ‘composite’ control electrode ring430are reduced by the fourth metal structure(s)432embedded in the dielectric inorganic substrate150. Differently stated, the fourth metal structure(s)432provide(s) for an additional wiring level for the control electrode ring430and thus improve(s) the electrical behavior of the control electrode ring430and, as a result, of the performance of the semiconductor transistor chip110. As shown in the enlarged section ofFIG.4B, the fourth metal structures432laterally connect to each other and/or are formed as a continuous ring trench.

The additional vertical structure provided by the fourth metal structure(s)432may not extend up to the second surface150B of the dielectric inorganic substrate150. As will be described further below, this may either be achieved by composing the dielectric inorganic substrate150of multiple dielectric inorganic substrate layers150_1,150_2, . . . with only the lower dielectric inorganic substrate layer(s)150_1be provided with the fourth metal structure(s)432, or by using recesses for the fourth metal structures432having a narrower opening so that the recesses (e.g. holes or trenches etc.) become less deep in the structuring process. That way, the fourth metal structures432may be fabricated only in a lower area of the dielectric inorganic substrate150.

In the example shown inFIGS.4A and4Bthe control electrode ring430surrounds the LV load electrode120and the control electrode130.FIG.4Cillustrates a semiconductor device400in which the control electrode ring430surrounds the LV load electrode120but not the control electrode130. Apart from this, features of the semiconductor device400ofFIG.4Cmay be similar or identical to the features of the semiconductor device400ofFIGS.4A and4Band reference is made to the above description to avoid reiteration.

FIGS.4D and4Eillustrate a further example of a semiconductor device400which is provided with at least one control electrode finger431. The control electrode finger431extends into an active area of the semiconductor transistor chip110in a vertical projection. Further, the control electrode finger431is electrically connected to the control electrode ring430.

As apparent fromFIGS.4D and4E, the control electrode finger431is (at least partly) embedded in the dielectric inorganic substrate150. More specifically, the control electrode finger431may include a fifth metal structure433and a control electrode chip finger435. The control electrode chip finger435corresponds to a conventional control electrode finger, while the fifth metal structure433provided in the dielectric inorganic substrate150electrically connects to the control electrode chip finger435and thereby provides for the vertical extension of the control electrode finger431.

Rewiring the control electrode chip finger435into the dielectric inorganic substrate150provides for the same advantages and improvements as rewiring the control electrode chip ring434into the dielectric inorganic substrate150as mentioned above, and reference is made to the above description to avoid reiteration.

As mentioned before, the degradation of the electrical field at the HV edge110E of the semiconductor transistor chip110is often a limiting factor in HV semiconductor transistor chips (e.g. IGBTs, MOSFETs, etc.).FIGS.5A-5Billustrate an example of a semiconductor device500in which the dielectric inorganic substrate150is used to rewire the chip-based HV load electrode ring140R into the dielectric inorganic substrate150.

More specifically, the semiconductor device500may include a HV load electrode ring540extending adjacent to the edge110E of the semiconductor transistor chip110. The HV load electrode ring540is partly or completely embedded in the dielectric inorganic substrate150. More specifically, the HV load electrode ring540may include a sixth metal structure542electrically connected to the chip-based HV load electrode ring140R or to any other HV load electrode contact provided in the semiconductor transistor chip110near the edge110E.

In other words, the chip-based HV load electrode ring140R can be partly or completely outsourced into the dielectric inorganic substrate150. The HV load electrode ring540is typically not exposed at the second surface150B of the dielectric inorganic substrate150, i.e. the dielectric inorganic substrate150covers the HV potential (e.g. drain potential).

HV electrode fingers (so-called drain fingers—not shown) can extend inward from the HV load electrode ring540into the active area of the semiconductor transistor chip110for a better HV load electrode contact.

Further, the HV load electrode ring540may include electrically floating rings544embedded in the dielectric inorganic substrate150. For the same reasons as explained above, the electrically floating rings544may be arranged with a small pitch of only a few or a few tens of micrometers. They are effective means of preventing ion penetration into the active area of the semiconductor transistor chip110and thus build a long-term drift stable edge110E of the semiconductor transistor chip110. If realized in the semiconductor transistor chip110, they would, however, unduly widen the chip edge region and therefore increase the semiconductor area consumption.

Hence, the dielectric inorganic substrate150allows to redesign the chip edge110E which is critical in terms of field degradation and ion penetration by the addition of vertical structures (sixth metal structure(s)542and/or electrically floating rings544) to improve electrical behavior, long term drift stability and semiconductor area consumption of the semiconductor device500.

It is to be note that the rings544need not be electrically floating, but may alternatively be controlled by one or more electrical potentials tapped, for example, from the semiconductor transistor chip110.

Referring toFIGS.5C to5D, an example of a semiconductor device500is provided with HV load electrode field plates. The HV electrode field plates include seventh metal structures546extending in a vertical direction in the dielectric inorganic substrate150. The seventh metal structures546may be electrically connected by a horizontal interconnect structure548which is electrically connected e.g. via the sixth metal structure542to HV potential. Similar as the electrically floating rings544, the seventh metal structures546(HV field plates) are advantageous to reduce the metallic openings at the chip edge110E and thus provide a drift-stable edge termination and reduce ion diffusion through the dielectric inorganic substrate150.

As known in the art, the spacing between the chip-based HV load electrode ring140R and a LV electrode (e.g. gate electrode, source/emitter electrode, sense electrode), here exemplified by the LV load electrode120, must be at least 35-45 μm. The rewiring functionality offered by the dielectric inorganic substrate150allows to reduce this spacing D as shown inFIG.5C. To this end, the LV load electrode120(or any other LV electrode) may be connected to LV field plates526which, in this example, are electrically interconnected via the LV load electrode substrate metallization120M.

As shown inFIG.5D, this approach may even allow for a negative spacing D, i.e. an overlap between the horizontal interconnect structure548of the HV load electrode field plates and an interconnect structure (e.g., the substrate metallization120M) of an LV structure equipped with, for example, LV field plates526.

FIGS.6A and6Dillustrate an example of a semiconductor device600which includes a barrier layer610disposed on the first surface150A of the dielectric inorganic substrate150. Optionally, an imide layer620for preconditioning the wafer surface may be used in this and, e.g., all other embodiments. The barrier layer610provides protection against ion diffusion or the penetration of moisture from the dielectric inorganic substrate150to the active area of the semiconductor transistor chip110. The barrier layer610may, e.g., comprise or be a nitride barrier layer. The barrier layer610may have a thickness of 100 nm or thicker and may reach a maximum thickness of, e.g., one or several μm.

Such barrier layers (in particular nitride barrier layers) often can not be deposited on the semiconductor wafer if the wafer has already been metallized, since too high temperatures are required for deposition. With the dielectric inorganic substrate150disclosed herein, it is possible to deposit such barrier layer610on the dielectric inorganic substrate150before it is metal-plated and bonded to the semiconductor wafer, from which the composite chips (semiconductor devices600) are later diced.

FIGS.6B and6Cillustrate stages of a process of manufacturing the barrier layer610on the first surface150A of the dielectric inorganic substrate150. Initially, the first surface of the dielectric inorganic substrate150is covered by the barrier layer610. Later, the dielectric inorganic substrate150is recessed (e.g. as described further below) and the first metal structures160and, e.g. some or all of the further metal structures described herein (e.g. the sixth metal structures542) are formed in the recesses. The barrier layer610is then partially removed to expose the first metal structures160at the first surface150A of the dielectric inorganic substrate150. Other metal structures such as, e.g., the sixth fifth metal structures542may also be exposed at the first surface150A of the dielectric inorganic substrate150.

The barrier layer610may also be produced on the dielectric inorganic substrate150by a CVD (chemical vapor deposition) process. It is to be noted that it may not be possible to apply a CVD process on the semiconductor wafer (there, only sputtering techniques may be usable to deposit the barrier layer610). The CVD process allows to deposit a denser and thus higher quality barrier layer610compared to barrier layers sputtered onto the wafer surface.

Hence, the dielectric inorganic substrate150allows to use higher deposition temperatures and modified manufacturing processes for forming barrier layers610with improved barrier performance.

The barrier layer610may, e.g., be arranged between HV and LV regions, e.g. between a HV load electrode640(e.g. drain electrode) and/or a HV load electrode ring140R and a LV voltage electrode such as, e.g. load electrode120and/or the control electrode130and/or a sense electrode of the semiconductor transistor chip110. A HV load electrode metallization640M may be provided on the dielectric inorganic substrate150and connected to the HV load electrode640.

Further, the barrier layer610may surround the semiconductor transistor chip110as a closed ring outside or adjacent or partially overlapping the active area.

FIG.7illustrates a semiconductor device700in which the distance to the semiconductor transistor chip110, created by the dielectric inorganic substrate150, is used to place an electrical component710in a low inductive manner over the semiconductor transistor chip110. The electrical component710may be a discrete passive or active electrical component. In particular, the electrical component710may be a capacitor, a resistor, an inductor or, as an example of an active component, a diode, e.g. a Zener diode.

The electrical component710may be mounted on the second surface150B of the dielectric inorganic substrate150. The electrical component710may be soldered or otherwise affixed directly to metallizations on the second surface150B of the dielectric inorganic substrate150. By using the dielectric inorganic substrate150, not only the required distance between the semiconductor transistor chip110and the electrical component710can be guaranteed but also rewiring can be made due to the additional wiring level provided by the second surface150B of the dielectric inorganic substrate150. Differently stated, due to the distance to the front side110A of the semiconductor transistor chip110, any electrical components710can be mounted on the dielectric inorganic substrate150without affecting the electrical field over the semiconductor transistor chip110and, in particular, at the edge110E of the semiconductor transistor chip110and without reducing the long-term stability of the semiconductor device700. In particular, no bond wires or other non-optimal connections to the semiconductor transistor chip110are required, and in addition, inductive or capacitive parasitics caused by bond wires or such other non-optimal connections are avoided.

The electrical component710may be electrically connected between a variety of different electrical contacts provided at the second surface150B of the dielectric inorganic substrate150. For example, the electrical component710may be electrically connected between a HV metal pad740disposed on the second surface150B of the dielectric inorganic substrate150and the substrate metallization130M connected via the at least one second metal structure170to the control electrode130. The HV metal pad740may be electrically connected to the HV load electrode ring140R or to the HV load electrode (not shown inFIG.7).

Other possibilities are to connect the electrical component710between the LV load electrode120and the control electrode130. This can be done by electrically connecting (e.g. direct soldering or otherwise affixing) the electrical component710between the substrate metallization120M of the LV load electrode120and the substrate metallization130M of the control electrode130. The respective electrical connections through the dielectric inorganic substrate150are then provided by the pattern of first metal structures160and the at least one second metal structure170. In this and other cases the electrical component710may, in particular, be a Zener diode. The capacitance of the diode is then used for improving the performance of the semiconductor transistor chip110.

Generally, the electrical component710may be connected between any two of all pads provided at the second surface150B of the dielectric inorganic substrate150, in particular between a LV load electrode pad (metallization120M), a LV control electrode pad (metallization130M), a LV control electrode ring pad, a HV load electrode pad and a HV load electrode ring pad740.

Referring toFIG.8, the dielectric inorganic substrate150may also be used to provide for an additional voltage tap on the semiconductor device800. The additional voltage tap may be implemented by a third metal structure820running through the dielectric inorganic substrate150. The third metal structure820may connect an intermediate voltage region850at the semiconductor transistor chip110to an intermediate voltage pad850M disposed on the second surface150B of the dielectric inorganic substrate150.

For example, one of the electrically floating (drain) rings544can be plated through the wafer to form the third metal structure820. The third metal structure820can touch down on a very small (e.g. p-doped) conductive region on the semiconductor transistor chip110. The conductive region can be very small, e.g.1one or a few square μm in size. The through-hole plating can also be very thin, for example a few μm. The pad850M of the intermediate voltage tap is then located far away from the front side110A of the semiconductor chip110and thus outside the region where it would influence the HV field.

The intermediate voltage region850may be located at a certain distance from the HV load electrode ring140R and thus from the edge110E of semiconductor transistor chip110. The distance between the HV load electrode ring140R and the tapped intermediate voltage region850determines the intermediate voltage. Differently stated, the offset of the intermediate voltage to HV (e.g. drain voltage) results from the positioning of the intermediate voltage tap, i.e. its position between the drain ring at the chip edge (i.e. the HV load electrode ring140R) and the source area (i.e. the LV load electrode120). For example the intermediate voltage can be equal to or less than or greater than 150 V or 50 V or 30 V or 20 V below the HV of the semiconductor transistor chip110.

An intermediate voltage tap is usually not feasible on a chip, since no contactable contact surfaces can be placed on the semiconductor transistor chip110near the edge110E, as such contact surfaces would disturb the HV field too much. It would be conceivable to pull out such an intermediate voltage with a line on the chip, but then the HV load electrode ring140R would have to be redesigned. Differently stated, the dielectric inorganic substrate150provides the possibility to tap a desired intermediate voltage region850at the front side110A of the semiconductor transistor chip110and to pull the appropriate intermediate voltage out upwards without changing field lines above the semiconductor transistor chip110in particular at the edge termination or requiring chip redesign for obtaining such intermediate voltage.

The intermediate voltage available at the intermediate voltage pad850can be used directly or can be supported against LV or HV by means of an electrical component710such as, e.g., a Zener diode connected between the intermediate voltage pad850and an LV metallization (e.g.120M or130M) or a HV metallization (e.g.740). That means that the intermediate voltage tap can be combined with the concept of soldering active or passive components710onto the dielectric inorganic substrate150(e.g. between the intermediate tap and source or intermediate tap and gate).

The intermediate voltage pad850is not a power pad. For example, it can be a sense pad and/or it can be a pad which provides a voltage to switch a follower transistor. For example, a transistor connected in series can be controlled ON or OFF by such a tapped voltage set, e.g., 20 V or 30 V below the HV load electrode (e.g. drain) voltage. At present, it is to our knowledge not practicable to tap such a voltage from a HV semiconductor transistor chip, i.e., such control of a follower transistor as disclosed herein is currently not known.

As mentioned before, in all semiconductor devices100,300-800the dielectric inorganic substrate150may comprise or be composed of a single layer dielectric inorganic substrate or a plurality of stacked dielectric inorganic substrate layers150_1,150_2,150_3. In the latter case, each dielectric inorganic substrate layer150_1,150_2,150_3may be constructed the same way as described for the dielectric inorganic substrate150. Implementing the dielectric inorganic substrate150by a multi-layer structure, as shown inFIG.9, may facilitate the process of manufacturing thick dielectric inorganic substrates150, since recess formation and metal plating can be carried out more conveniently with thinner structures, namely the layers150_1,150_2and150_3. For instance, if a thickness TS of 300 μm is desired, each of these processes needs only to be carried out on a dielectric inorganic substrate layer150_1,150_2,150_3of, e.g., a thickness of 50 μm or 100 μm.

The dielectric inorganic substrate layers150_1,150_2,150_3including, e.g., the first and second metal structures160,170may be pre-fabricated and then aligned and bonded together to form the dielectric inorganic substrate150. As noted before, layer bonding may be done on wafer-level, e.g. by using a glass frit connection between adjacent dielectric inorganic substrate layers150_1,150_2and150_3.

Further, this technique of stacking a plurality of dielectric inorganic substrate layers150_1,150_2,150_3allows to form blind hole metal structures960which do not extend through the dielectric inorganic substrate150but end in the dielectric inorganic substrate150at a dielectric inorganic substrate layer150_1,150_2adjacent to the dielectric inorganic substrate layer150_2,150_3which is provided with the blind hole metal structure960. As described before, such blind hole metal structures960can, e.g., be used as field plates (e.g. source field plates526, drain ring field plates546, floating rings544, etc.) which allow to appropriately effect the electrical field above the semiconductor transistor chip110. Due to the layer-by-layer arrangement of the dielectric inorganic substrate150, no true blind holes need to be fabricated to realize such blind hole metal structures960terminating in the dielectric inorganic substrate150.

All ring structures described herein may be closed rings. The metal structures of all ring structures and fingers described herein may laterally contact to each other (see e.g. detail ofFIG.4B) and/or may be implemented as continuous trenches to allow a lateral current flow through the ring structure or the finger, respectively, in the dielectric inorganic substrate150.

FIGS.10A-10Lillustrate exemplary stages of a process of manufacturing a semiconductor device100,300-800in accordance with the disclosure.

Referring toFIG.10A, a dielectric inorganic substrate wafer1050is provided. The dielectric inorganic substrate wafer1050may, e.g., have a thickness of 400 to 700 μm. The dielectric inorganic substrate wafer1050may, e.g., be a glass wafer or a semiconductor wafer.FIGS.1000A-Lillustrate only a portion of the dielectric inorganic substrate wafer1050which comprises, e.g., one semiconductor chip110, seeFIG.10L.

FIG.10Billustrates the formation of recesses1020in a first surface1050A of the dielectric inorganic substrate wafer1050. The recesses1020may be formed by etching. The dimensions (lateral dimensions, depths) of the recesses1020may correspond to the dimensions described above for the first metal structures160.

According toFIG.10B, the dielectric inorganic substrate wafer1050may include (per chip) a first pattern PAT1of recesses1020and a second pattern PAT2of the recesses1020. As shown on the right hand side ofFIG.10Bwhich illustrates a top view on a chip portion of the dielectric inorganic substrate wafer1050, the area of PAT1may, e.g., be substantially greater than the area of PAT2. Further, as mentioned before, the parameters (pitch, distance, shape, . . . ) of the recesses1020in PAT1and in PAT2may be different from each other or may be the same.

In one embodiment, only the first pattern PAT1is formed as a pattern of recesses, while the second pattern PAT2is replaced by another type of through connection such as, e.g., a single hole serving as a through connection for, e.g., the control electrode130of the semiconductor transistor chip110.

Some of the recesses1020formed in the dielectric inorganic substrate wafer1050may have a depth which is smaller than the target thickness of the dielectric inorganic substrate wafer1050(i.e. TS ofFIG.1), while other recesses1020have a depth greater than the target thickness of the dielectric inorganic substrate wafer1050.

Referring toFIG.10C, a liner1012may optionally be deposited over the first surface1050A of the dielectric inorganic substrate wafer1050. The liner1012may, e.g., be an electrically conductive seed layer.

Referring toFIG.10D, a protective layer1014may be applied over the top surface of the dielectric inorganic substrate wafer1050and, e.g., over the liner1012. The protective layer1014may be applied using a self-aligned process. That is, the protective layer1014may only be applied over parts of the first surface1050A of the dielectric inorganic substrate wafer1050which are not recessed. The protective layer1014may, e.g., be applied by a rolling and/or printing process and may, e.g., completely cover the liner1012at non-recessed parts of the first surface1050A of the dielectric inorganic substrate wafer1050.FIG.10Eshows the protective layer1014applied over the top surface of the dielectric inorganic substrate wafer1050.

It is to be noted that the processes of liner1012deposition and/or protective layer1014deposition as shown inFIGS.10C and10Dare optional processes, since metal plating, as described in the following, can also be carried out without liner1012and/or protective layer1014deposition.

Referring toFIG.10F, metal is plated to fill the recesses1020. As a result, the first metal structures160are formed. The first metal structures160may completely fill the recesses1020. Further, the second metal structures170may be formed.

The first metal structures160may protrude a small distance over the first surface1050A of the dielectric inorganic substrate wafer1050. Metal plating can be carried out by electro-chemical deposition (ECD). For instance, copper or a copper alloy may be used as a plating metal, but other metals known in the art to be suitable for package interconnects can also be used. The same may hold true for the second metal structure(s)170.

Referring toFIG.10H, a bonding material1080may be applied on the dielectric inorganic substrate wafer1050. The bonding material1080may be applied on areas of the dielectric inorganic substrate wafer1050which correspond to inactive areas of a semiconductor wafer1010(seeFIG.10I).

The bonding material1080may e.g. comprise or be glass glue (e.g. glass frit) or a resin or any other material suitable to permanently bond the dielectric inorganic substrate wafer1050to the semiconductor wafer1010(seeFIG.10I).

Referring toFIG.10I, the front side of a semiconductor wafer1010is combined with the dielectric inorganic substrate wafer1050to form a composite wafer1000. During this process the plurality of patterns of first metal structures160is placed opposite the plurality of LV load electrodes120on the semiconductor wafer1010. Again, it is to be noted thatFIG.10Ionly shows a partial view of the dielectric inorganic substrate wafer1050and the semiconductor wafer1010which substantially corresponds to one semiconductor transistor chip110in the semiconductor wafer1010. Hence, the first pattern PAT1of first metal structures160and the second pattern PAT2of second metal structures170may form sub-patterns corresponding to two electrodes120,130of a single semiconductor transistor chip110of the semiconductor wafer1010.

The process of combining the semiconductor wafer1010and the dielectric inorganic substrate wafer1050as shown inFIG.10Imay be carried out by using optical alignment through the dielectric inorganic substrate wafer1050(e.g. so-called through-glass alignment or through-semiconductor alignment). That is, an optical alignment processes may be carried out by viewing through the dielectric inorganic substrate wafer1050to recognize the position of the semiconductor wafer1010relative to the position of the dielectric inorganic substrate wafer1050so as to combine the semiconductor wafer1010and the dielectric inorganic substrate wafer1050in proper alignment.

The bonding material1080may have also been applied to the semiconductor wafer1010rather than to the dielectric inorganic substrate wafer1050.

FIG.10Jillustrates the process of bonding the semiconductor wafer1010to the dielectric inorganic substrate wafer1050with the front side1010A of the semiconductor wafer1010facing the dielectric inorganic substrate wafer1050. This process may concurrently connect the plurality of patterns of first metal structures160on the dielectric inorganic substrate wafer1050to the plurality of LV load electrodes120on the semiconductor wafer1010. The process may be carried out by applying heat and pressure to the composite wafer1000.

By virtue of this process the bonding1080material fixedly secures the semiconductor wafer1010to the dielectric inorganic substrate wafer1050. Further, by this or another process, the first metal structures160may be electrically and mechanically fixedly connected to the LV load electrodes120. The connections may be solder-free, i.e. no solder material may be used for establishing the electrical, mechanical and thermal connection between the LV load electrodes120and the first metal structures160. By way of example, the connection may be created by the formation of an eutectic phase between the metal of the LV load electrodes120and the metal of the first metal structures160. The same may hold true for the connection of the second metal structures170to the control electrodes130.

Referring toFIGS.10K and10L, the dielectric inorganic substrate wafer1050may be thinned from a second surface1050B (seeFIG.10J) opposite the first surface1050A to expose the metal of at least a part or of all of the metal structures160in the recesses1020.

More specifically, thinning may, e.g., be carried out in a multi-stage process. For instance, as shown inFIG.10K, thinning may comprise grinding the dielectric inorganic substrate wafer1050down to a thickness which is only slightly larger than the depth of the recesses1020. For instance, grinding may stop at a distance of equal to or less than 20 μm or 15 μm or 10 μm over the bottom of the recesses1020.

The first metal structures160or at least a part of them may then be exposed by etching the dielectric inorganic substrate wafer1050down to the thickness TS (seeFIG.1). Etching may be carried out by wet or dry chemical etching. Etching may be continued until the first metal structures160(or at least some of them) and e.g. also the second metal structures170protrude a small distance such as, e.g., a few μm over the bottom surface of the thinned dielectric inorganic substrate wafer1050. The bottom surface of the thinned dielectric inorganic substrate wafer1050may correspond to the second surface150B of the dielectric inorganic substrate150as shown inFIG.1.

In the following, the back-end-of-line (BEOL) processes of chip packaging may be carried out on the composite wafer1000shown inFIG.10L. In this context, the composite wafer1000is separated along dicing lines L into composite chips corresponding to semiconductor devices100. Separating the composite wafer1000into composite chips may be carried out by any suitable dicing methods, e.g. mechanical sawing, laser dicing and/or etching. As a result, the high voltage semiconductor transistor chip110and the dielectric inorganic substrate150may have aligned cutting edges.

The following examples pertain to further aspects of the disclosure:

Example 1 is a semiconductor device comprises a high voltage semiconductor transistor chip comprising a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further comprises a dielectric inorganic substrate comprising a first side and a second side opposite the first side. A pattern of first metal structures is running through the dielectric inorganic substrate, wherein the pattern of first metal structures is connected to the low-voltage load electrode. At least one second metal structure is running through the dielectric inorganic substrate, wherein the second metal structure is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

In Example 2, the subject matter of Example 1 can optionally include wherein the dielectric inorganic substrate comprises a control pad disposed on the second side of the dielectric inorganic substrate, the second metal structure connecting the control pad, wherein the control pad has an area which is greater than an area of the control electrode by at least a factor 3 and/or an edge of the control pad is closer to an edge of the semiconductor transistor chip than an edge of the control electrode.

In Example 3, the subject matter of Example 1 or 2 can optionally include wherein the dielectric inorganic substrate comprises a control electrode ring surrounding an active area of the semiconductor transistor chip in a vertical projection, wherein the control electrode ring is embedded in the dielectric inorganic substrate.

In Example 4, the subject matter of any of the preceding Examples can optionally include wherein the dielectric inorganic substrate comprises at least one control electrode finger extending into an active area of the semiconductor transistor chip in a vertical projection, wherein the control electrode finger is embedded in the dielectric inorganic substrate.

In Example 5, the subject matter of any of the preceding Examples can optionally include a high voltage load electrode ring extending adjacent to an edge of the semiconductor transistor chip, wherein the high voltage load electrode ring is partly or completely embedded in the dielectric inorganic substrate.

In Example 6, the subject matter of Example 5 can optionally include wherein the high voltage load electrode ring comprises electrically floating rings embedded in the dielectric inorganic substrate.

In Example 7, the subject matter of Example 5 or 6 can optionally include high voltage load electrode field plates embedded in the dielectric inorganic substrate, wherein the high voltage load electrode field plates are vertical metal structures electrically connected to the high voltage load electrode ring.

In Example 8, the subject matter of any of the preceding Examples can optionally include low-voltage load electrode field plates, wherein the low-voltage load electrode field plates are vertical metal structures electrically connected to the low-voltage load electrode.

In Example 9, the subject matter of any of the preceding Examples can optionally include control electrode field plates, wherein the control electrode field plates are vertical metal structures electrically connected to the control electrode.

In Example 10, the subject matter of any of the preceding Examples can optionally include a barrier layer disposed on the first side the dielectric inorganic substrate.

In Example 11, the subject matter of Example 10 can optionally include wherein the barrier layer is arranged between a high voltage load electrode or a high voltage load electrode ring disposed on the front side of the semiconductor transistor chip and the low-voltage load electrode or the control electrode of the semiconductor transistor chip.

In Example 12, the subject matter of any of the preceding Examples can optionally include an active or passive electrical component mounted on the second side of the dielectric inorganic substrate.

In Example 13, the subject matter of Example 12 can optionally include wherein the electrical component is electrically connected between the pattern of first metal structures and the at least one second metal structure or between a high voltage metal pad disposed on the second side of the dielectric inorganic substrate and the at least one second metal structure.

In Example 14, the subject matter of any of the preceding Examples can optionally include a third metal structure running through the dielectric inorganic substrate, wherein the third metal structure is connected to an intermediate voltage region on the front side of the semiconductor transistor chip, the intermediate voltage region being located near an edge of the semiconductor transistor chip, and to an intermediate voltage pad disposed on the second side of the dielectric inorganic substrate.

In Example 15, the subject matter of any of the preceding Examples can optionally include wherein the dielectric inorganic substrate is a glass substrate.

In Example 16, the subject matter of any of the preceding Examples can optionally include wherein the front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate by a wafer bond connection, in particular a glass frit connection.

In Example 17, the subject matter of any of the preceding Examples can optionally include wherein the first metal structures and/or the at least one second metal structure are plated metal pillars.

In Example 18, the subject matter of any of the preceding Examples can optionally include wherein the dielectric inorganic substrate comprises a plurality of stacked dielectric inorganic substrate layers.