Memory arrays with bonded and shared logic circuitry

An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

BACKGROUND

Flash memory, such as NAND flash memory, is a nonvolatile storage medium. A flash memory array generally is coupled to logic circuits that facilitate operations of the memory array. The logic circuits have components such as word line drivers, bit line drivers, and sense amplifiers for the memory array. The logic circuits, for example, include complementary metal-oxide-semiconductor (CMOS) logic. Often times, thermal cycles of the process for formation of the memory array adversely affect the logic circuits. As will be appreciated in light of this disclosure and explained in turn, there exists a number of non-trivial issues associated with decreasing complexity, power consumption, and/or cost (e.g., cost per bit of memory) of the logic circuits, as well as avoiding the adverse effects of thermal cycles of the memory array processing on the logic circuits.

DETAILED DESCRIPTION

An integrated memory structure is disclosed herein, which includes multiple memory arrays, such as flash memory arrays, sharing a common logic circuitry. In some embodiments, the shared logic circuitry is interposed between a first memory array and a second memory array. In an example, the first memory array and the second memory array are processed and formed separately from the logic circuitry. Subsequent to formation of the memory arrays and the logic circuitry, the logic circuitry is bonded to the first memory array and the second memory array. Thus, in an example, the integrated memory structure includes a first die comprising the first memory array, a second die comprising the second memory array, and a third die comprising the logic circuitry, where the third die is between the first and second dies, and the third die is bonded to each of the first and second dies.

In an example, a first layer is deposited on a surface of the logic circuitry that is to be bonded with the memory array, and a second layer is deposited on a surface of the memory array that is to be bonded with the logic circuitry. Each of the first and second layer comprises, for example, an oxide material (such as silicon dioxide), a nitride material (such as silicon nitride), an oxynitride material (such as silicon oxynitride), and/or the like. The first and second layers are cleaned and polished, pre-bonded with one another, and annealed at an elevated temperature, thereby bonding the first and second layers to form a bonding interface layer. Thus, in the integrated memory structure, the logic circuit and the memory array are separated by the bonding interface layer. As discussed, the bonding interface layer comprises silicon dioxide, silicon nitride, silicon oxynitride, or other suitable electrically-insulating bonding material. Although the thickness of the bonding interface layer can vary, in some embodiments it has a thickness in the range of 3000 angstroms to 10 microns. Thus, in the integrated memory structure that includes logic circuitry between, and bonded to, two memory arrays, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

In some examples, the bonding between the logic circuitry and a memory array may be formed using fusion bonding or hybrid bonding. As will be discussed in further detail in turn, in fusion bonding, the bonding process is between the first and second layers (and not between any conductive material such as metal). For example, in fusion bonding (which is also referred to as direct bonding), no conductive structure (e.g., vias including metal) extends through the first and second layers, while these layers are being bonded to form the bonding interface layer. After the bonding is completed, via holes are formed extending through the bonding interface layer and are filled with metal, thereby forming interconnect structures between the logic circuitry and the memory array through the bonding interface layer. Because the vias are formed through the bonding interface layer subsequent to the first and second layers being bonded, sections of an interconnect structure extending through the bonding interface layer do not have any misalignment or offset (no unlanded portions), as will be discussed in further detail in turn.

In contrast to fusion bonding and as will be discussed in further detail in turn, in hybrid bonding, the bonding process is between the first and second layers and also between conductive structures within the first layer and conductive structures within the second layer. For example, in hybrid bonding, conductive structure (e.g., a via including metal) extends through each of the first and second layers, prior to these layers being bonded to form the bonding interface layer. For example, a first interconnect structure extends through the first layer and is exposed through, and flush with, a surface of the first layer; and a second interconnect structure extends through the second layer and is exposed through, and flush with, a surface of the second layer (e.g., prior to the bonding process). During the bonding process, surfaces of the first layer and the second layers bond to form a bonding interface layer, along with a bonding or contact of the first interconnect structure and the second interconnect structure. In an example, due to unintentional practical considerations of the bonding process, the memory array and the logic circuitry may not be perfectly aligned during the bonding process, and hence, the first interconnect structure and the second interconnect structure may not be perfectly aligned while being bonded. Accordingly, sections of a combined interconnect structure formed through the bonding or contact of the first and second interconnect structures, which extend through the bonding interface layer, may have some misalignment or offset, as will be discussed in further detail in turn.

Bonding the logic circuitry with two memory arrays and sharing the logic circuitry among the two memory arrays have several advantages. For example, sharing the logic circuitry among the memory arrays reduces complexity and/or power consumption of the logic circuitry. For example, a single shared voltage divider block of the logic circuitry can be used for both the memory arrays. Sharing the logic circuitry among the memory arrays also reduces cost of the logic circuitry per bit of memory. Thus, the cost of the logic circuitry is amortized across two memory arrays, thereby resulting in cost savings. Also, due to the use of the bonding process between the logic circuitry and the memory arrays, it is possible to separate the logic circuitry processing from the memory array processing, so that the logic circuitry is not affected by the thermal cycles of the process of memory array formation. Also, forming the memory arrays and the logic circuitry independently and separately reduces overall cycle time to manufacture the integrated memory structure.

Instead of bonding the logic circuitry with each of the two memory arrays according to some embodiments, in another example embodiment, the logic circuitry can be bonded with a single memory array. For example, the memory array and the logic circuitry are formed separately and then bonded (e.g., using fusion bonding or hybrid bonding). Thus, formation of the logic circuitry is separate from formation of the memory array, so that the logic circuitry is not affected by thermal cycles of the process of memory array formation.

In an example embodiment, instead of bonding the logic circuitry with each of two memory arrays, the logic circuitry is formed to be integrated with a first memory array (e.g., instead of bonding separately formed logic circuitry and the first memory array, a combined structure is formed that includes both the logic circuitry and the first memory array). After the combination of the first memory array and the logic circuitry is formed, the combination is then bonded with a second memory array. In the final memory structure, the logic circuitry is interposed between the first and second memory arrays. A bonding interface layer is between the logic circuitry and the second memory array (in other words, the combination of the first memory array and the logic circuitry is bonded with the second memory array). However, no such bonding interface layer is present between the logic circuitry and the first memory array. This alternate forming process still allows the logic circuitry to be shared among the first and second memory arrays, thereby reducing complexity, power consumption, and/or a cost per bit of the logic circuitry, as previously discussed herein.

As discussed herein, terms referencing direction, such as upward, downward, vertical, horizontal, left, right, front, back, etc., are used for convenience to describe embodiments of integrated circuits having a base or substrate extending in a horizontal plane. Embodiments of the present disclosure are not limited by these directional references and it is contemplated that integrated circuits and device structures in accordance with the present disclosure can be used in any orientation.

Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same Elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer.

Note that, as used herein, the expression “X includes at least one of A or B” refers to an X that may include, for example, just A only, just B only, or both A and B. To this end, an X that includes at least one of A or B is not to be understood as an X that requires each of A and B, unless expressly so stated. For instance, the expression “X includes A and B” refers to an X that expressly includes both A and B. Moreover, this is true for any number of items greater than two, where “at least one of” those items are included in X. For example, as used herein, the expression “X includes at least one of A, B, or C” refers to an X that may include just A only, just B only, just C only, only A and B (and not C), only A and C (and not B), only B and C (and not A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. To this end, an X that includes at least one of A, B, or C is not to be understood as an X that requires each of A, B, and C, unless expressly so stated. For instance, the expression “X includes A, B, and C” refers to an X that expressly includes each of A, B, and C. Likewise, the expression “X included in at least one of A or B” refers to an X that may be included, for example, in just A only, in just B only, or in both A and B. The above discussion with respect to “X includes at least one of A or B” equally applies here, as will be appreciated.

Elements referred to herein with a common reference label followed by a particular number or alphabet may be collectively referred to by the reference label alone. For example, inFIG. 1discussed herein later, memory arrays104a,104bmay be collectively and generally referred to as memory arrays104in plural, and memory array104in singular.

Architectures

FIG. 1illustrates a cross-sectional view of an integrated memory structure100(also referred to as a structure100) comprising a first memory array (also referred to as an “array”)104a, a second memory array104b, and logic circuitry108, wherein a first bonding interface layer110ais between the first array104aand the logic circuitry108, and a second bonding interface layer110bis between the second array104band the logic circuitry108, in accordance with some embodiments.

In an example, each of the arrays104a,104bcomprises any appropriate three-dimensional (3D) memory array, such as a floating gate flash memory array, a charge-trap (e.g., replacement gate) flash memory array, a phase-change memory array, a resistive memory array, an ovonic memory array, a ferroelectric transistor random access memory (FeTRAM) array, a nanowire memory array, or any other 3D memory array. In one example, each of the memory arrays104a,104bis a stacked NAND flash memory array, which stacks multiple floating gate or charge-trap flash memory cells in a vertical stack wired in a NAND (not AND) fashion. In another example, the 3D memory arrays104a,104binclude NOR (not OR) storage cells.

The array104acomprises word lines (WLs)114a, and the array104bcomprises WLs114b. Although three WLs are illustrated for each of the arrays104, the arrays can have any appropriate number of WLs.

Three example logic components118of the logic circuitry108are symbolically illustrated inFIG. 1. Examples of logic components118include, but are not limited to, address decoders, state machines, buffers, word line drivers, bit line drivers, sense amplifiers, voltage dividers, charge pumps, digital logic blocks, logic gates, switches, inverters, adders, multipliers, etc. In an example, one or more of the logic components118include complementary metal-oxide-semiconductor (CMOS) logic. In an example, the logic circuitry108may also be referred to as “CMOS logic,” “CMOS circuitry,” and/or the like, due to presence of CMOS circuits within the logic circuitry108. In an example, the logic circuitry108includes high voltage logic components (e.g., components and/or transistors that operate at a relatively high voltage, such as in the range of 5 V to 30 V) and/or low voltage logic components (e.g., components and/or transistors that operate at a relatively low voltage, such as in the range of 0.9 V to 5 V).

The structure100is symbolically illustrated in high level inFIG. 1, without illustrating various internal components within the arrays104a,104band the logic circuitry108—further detail of the arrays104a,104band the logic circuitry108will be discussed in turn.

As will be discussed in further detail in turn, the array104a, the array104b, and the logic circuitry108are formed and processed separately. Subsequently, the array104aand the logic circuitry108are bonded (e.g., using wafer to wafer bonding, die to die bonding, wafer to die bonding, or die to wafer bonding), thereby forming the bonding interface layer110a. Thus, in an example, bonding the array104aand the logic circuitry108is accomplished by bonding the wafers together that include these components, and then dicing the wafers (e.g., wafer to wafer bonding). In another example, bonding the array104aand the logic circuitry108is accomplished by bonding a die comprising the array104aand a die comprising the logic circuitry108(e.g., die to die bonding). In yet another example, bonding the array104aand the logic circuitry108is accomplished by bonding a wafer comprising the array104aand a die comprising the logic circuitry108, and then dicing the wafer (e.g., wafer to die bonding). In yet another example, bonding the array104aand the logic circuitry108is accomplished by bonding a wafer comprising the logic circuitry108and a die comprising the array104a, and then dicing the wafer (e.g., wafer to die bonding). Similarly, the array104band the logic circuitry108are bonded (e.g., using wafer to wafer bonding, die to die bonding, wafer to die bonding, or die to wafer bonding), thereby forming the bonding interface layer110b. Thus, each of the bonding interface layers110a,110bare remnant of the bonding process between the logic circuitry108and the corresponding array104.

In an example embodiment, the bonding between the logic circuitry108and the arrays104are performed at a relatively later part of the process used in forming the structure100. For example, as will be discussed in further detail in turn, the logic circuitry108is processed and formed independent of, and separate from, the processing and forming of the arrays104. That is, the logic circuitry108and the arrays104are processed and formed prior to the bonding between the logic circuitry108and the arrays104. Subsequently, the logic circuitry108and the arrays104are bonded (e.g., thereby forming the bonding interface layers110).

In some embodiments, interconnect structures electrically coupling the logic circuitry108and the arrays104are formed after the bonding process (e.g., in case fusion bonding is employed, as will be discussed in turn), while in some other embodiments, at least part of the interconnect structures are formed prior to the bonding process (e.g., in case hybrid bonding is employed, as will be discussed in turn).

In an example, the logic circuitry108is shared among the arrays104a,104b. For example, at least some of the logic components118are shared and used for both the arrays104a,104b.

Bonding the logic circuitry408with the two arrays104a,104b, and sharing the logic circuitry108among the two arrays104a,104bhave several advantages. For example, as discussed previously, sharing the logic circuitry108among the arrays104a,104breduces complexity and/or power consumption of the logic circuitry108. For example, a single shared voltage divider block can be used for both the arrays104a,104b. Sharing the logic circuitry108among the arrays104a,104balso reduces cost of the logic circuitry108(e.g., cost of the logic circuitry per bit of memory). Thus, the cost of the logic circuitry108is amortized across two memory arrays, thereby resulting in cost savings. Also, due to the use of the bonding process between the logic circuitry108and the arrays104, it is possible to separate the logic circuitry processing from the array processing, so that the logic circuitry108is not affected by the thermal cycles of the process of memory array formation. Also, forming the arrays104and the logic circuitry108independently and separately reduces overall cycle time to manufacture the structure100.

FIGS. 2A-2Cillustrate an example process of bonding, using a fusion bonding process, a memory array204and logic circuitry208, thereby forming a bonding interface layer210, in accordance with some embodiments. In an example, the memory array204ofFIGS. 2A-2Ccan be any of the memory arrays104a,104bofFIG. 1(or any other memory array discussed herein), the logic circuitry208ofFIGS. 2A-2Ccan be the logic circuitry108ofFIG. 1(or any other logic circuitry discussed herein), and the bonding interface layer210ofFIGS. 2A-2Ccan be any of the bonding interface layers110a,110bofFIG. 1(or any other bonding interface layer discussed herein).

Referring toFIG. 2A, the array204and the logic circuitry208are formed separately. In some embodiments, one or both the array204and the logic circuitry208may be in a wafer level, i.e., on a corresponding wafer, while they are being bonded. In some other embodiments, one or both the array204and the logic circuitry208may be in a die level (i.e., singulated and separated in individual dies), while they are being bonded.

The array204has a layer211aon a bottom surface of the array204that is to be bonded to the logic circuitry208, and the logic circuitry208has a layer211bon a top surface of the logic circuitry that is to be bonded to the array204. That is, the layers211a,211bare to be bonded. The layers211a,211bwill be discussed in further detail later. The arrows203inFIG. 2Asymbolically indicate that the array204and the logic circuitry208are to be bonded.

As illustrated inFIG. 2A, no interconnect structure comprising conductive material (e.g., such as metal) extends through the layers211a,211b. For example,FIG. 2Aillustrates an example interconnect structure219that extends from a logic component218to the layer211b, but the interconnect structure219does not extend through the layer211b. Thus, a surface201bof the layer211b(e.g., which faces away from the logic circuitry208) does not have any metal or other conductive material protruding through the layer211b. Similarly, a surface201aof the layer211a(e.g., which faces away from the array204) does not have any metal or other conductive material protruding through the layer211a.

FIG. 2Billustrates a combined structure where the array204and logic circuitry208have bonded, to form the bonding interface layer210. The bonding between the array204and logic circuitry208is performed using fusion bonding (also referred to as direct bonding). In fusion bonding, the smooth surfaces201aand201bof the layers211a,211b, respectively, are first polished, smoothed, and/or cleaned (e.g., made free of any impurity). Then the layers211a,211bare pre-bonded, e.g., at room temperature. Subsequently, the layers211a,211bare annealed, e.g., at elevated temperature, such that the layers211a,211bbond to form the bonding interface layer210. In another example, any other appropriate type of process flow may be employed for the fusion bonding process.

In an example, each of the layers211a,211b,210comprises silicon and oxygen. For example, the bonding interface layer210is Silicon dioxide (SiO2). In an example, each of the layers211a,211b,210comprises silicon and nitrogen. For example, the bonding interface layer210is Silicon Nitride (Si3N4). In another example, any other appropriate material, that are employed for fusion or direct bonding, may be used for the bonding interface layer210.

In an example, a thickness of the bonding interface layer210is within a range of about 3000 angstroms to 10 microns. The thickness of the bonding interface layer210can be based on the material used for the bonding interface layer210, a size of the surfaces201of the layers211, a level of purity or cleanliness of the surfaces201prior to bonding, desired degree of electrical isolation between the logic circuitry208and memory array204, and/or desired degree of structural integrity.

In an example, during the bonding process, the layers211a,211bare bonded to form the single bonding interface layer210, where the individual layers211a,211bare not separately discernable in the bonding interface layer210. In another example, the individual layers211a,211bare separately discernable in the bonding interface layer210. For instance, there may be a visible seam between layers211a,211b.

In an example, in the fusion bonding process, prior to the bonding, no metal or other conductive material extends through the layer211aon the surface201a, and no metal or other conductive material extends through the layer211bon the surface201b. That is, the fusion bonding ofFIGS. 2A-2Bis between the layers211aand211b, without any bonding or attachment between two conductive materials (in contrast, a hybrid bonding process involves bonding between conductive materials, as will be discussed in turn).

Referring now toFIG. 2C, a plurality of interconnect structures are formed through the bonding interface layer210, and a single example interconnect structure220is illustrated inFIG. 2C. The interconnect structure220is formed using deep via etch, such that a through hole via is formed through the array204and the bonding interface layer210, and the via is filled with conductive material such as metal. The interconnect structure220can be coupled to the interconnect structure219ofFIG. 2B, e.g., to form a continuous interconnect structure between the array204and the logic circuitry208.

FIG. 2Cfurther illustrates a magnified view of a section205, which comprises a section of the bonding interface layer210and the interconnect structure220. For example, in the magnified view, an imaginary line AA′ passes through the bonding interface layer210, and divides the bonding interface layer210in the layers211aand211b. The interconnect structure220passes through the line AA′. Also illustrated is a side221of the interconnect structure220. Because the interconnect structure220is formed after the bonding process, there is no discontinuity, offset or misalignment in the side221of the interconnect structure220, in the section of the interconnect structure220passing the line AA′. As will be discussed herein in turn, if, for example, hybrid bonding is employed instead of fusion bonding, then a side of the interconnect layer may have some discontinuity or misalignment.

FIGS. 3A-3Billustrate an example process of bonding, using hybrid bonding process, a memory array304and logic circuitry308, thereby forming a bonding interface layer310, in accordance with some embodiments. In an example, the memory array304ofFIGS. 3A-3Bcan be any of the memory arrays104a,104bofFIG. 1(or any other memory array discussed herein), the logic circuitry308ofFIGS. 3A-3Bcan be the logic circuitry108ofFIG. 1(or any other logic circuitry discussed herein), and the bonding interface layer310ofFIGS. 3A-3Bcan be any of the bonding interface layers110a,110bofFIG. 1(or any other bonding interface layer discussed herein).

Referring toFIG. 3A, the array304and the logic circuitry308are formed separately. In some embodiments, one or both the array304and the logic circuitry308may be in a wafer level, i.e., part of a corresponding wafer; while in some other embodiments, one or both the array304and the logic circuitry308may be in a die level (i.e., singulated and separated in individual dies).

The array304has a layer311aon a bottom surface of the array304that is to be bonded to the logic circuitry308, and the logic circuitry308has a layer311bon a top surface of the logic circuitry that is to be bonded to the array304a. That is, the layers311a,311bare to be bonded. The layers311a,311bmay be similar to the layers211a,211bdiscussed with respect toFIGS. 2A-2C. The arrows303inFIG. 3Asymbolically indicate that the array304and the logic circuitry308are to be bonded.

In an example, a plurality of interconnect structures comprising conductive material (e.g., such as metal) extend through the layers311a, and311b. For example,FIG. 3Aillustrates an example interconnect structure319acomprising conductive material (e.g., such as metal) extends through the layer311a; and an interconnect structure319bcomprising conductive material (e.g., such as metal) extends through the layer311b. Thus, a surface301aof the layer311a(e.g., which faces away from the array304) has a plurality of metal or other conductive materials exposed through the layer311a(such as the tip of the interconnect structure319abeing exposed through the surface301a). The tip of the interconnect structure319ais flush or co-planar with the surface301aof the layer311a, as illustrated. In an example, the layer311ais polished or cleaned, to make the tip of the interconnect structure319aflush or co-planar with the surface301aof the layer311a.

Similarly, a surface301bof the layer311b(e.g., which faces away from the logic circuitry208) has a plurality of metal or other conductive materials exposed through the layer311b(such as the tip of the interconnect structure319bprotruding or exposed through the surface301b).

FIG. 3Billustrates a combined structure where the array304and logic circuitry308have bonded, to form the bonding interface layer310. The bonding between the array304and logic circuitry308is performed using hybrid bonding. As previously discussed with respect toFIGS. 2A-2C, in fusion bonding, the bonding is between the two layers211a,211b, without any bonding between metals or other conductive material exposed through the bonding surfaces of these two layers. In contrast, in hybrid bonding, the layers311a,311bare bonded, along with attachment or contact between corresponding conductive materials exposed through the bonding surfaces of these two layers. For example, in the hybrid bonding ofFIG. 3B, the layers311a,311bare bonded, along with attachment, bonding or contact between conductive materials of the tips of the interconnect structures319a,319brespectively exposed through the bonding surfaces of the layers311a,311b. Thus, the interconnect structures319a,319bare in contact inFIG. 3B, thereby forming a combined interconnect structure320.

Similar to fusion bonding, in the hybrid bonding, the smooth surfaces301aand301bof the layers311a,311b, respectively, and the exposed tips of the interconnect structures319a,319bare polished, smoothed, and/or cleaned (e.g., made free of any impurity). Then the layers311a,311bare pre-bonded, e.g., at room temperature. Subsequently, the layers311a,311bare annealed, e.g., at elevated temperature, such that the layers311a,311bbond to form the bonding interface layer310. In another example, any other appropriate process flow may be employed for the hybrid bonding process.

In an example, the layers311a,311b,310may be similar to those discussed with respect toFIGS. 2A-2C. For example, each of the layers311a,311b,310comprises silicon and oxygen, e.g., comprises Silicon dioxide (SiO2). In an example, each of the layers311a,311b,310comprises silicon and nitrogen, e.g., comprises Silicon Nitride (Si3N4). In another example, any other appropriate material, generally used for hybrid bonding, may be used for the bonding interface layer310. In an example, a thickness of the bonding interface layer310is within a range of about 3000 angstrom to 1 micron.

In an example, during the bonding process, the layers311a,311bare bonded to form the single bonding interface layer310, where the individual layers311a,311bare not separately discernable in the bonding interface layer310. In another example, the individual layers311a,311bare separately discernable in the bonding interface layer310.

FIG. 3Bfurther illustrates a magnified view of a section305, which comprises a section of the bonding interface layer310and the interconnect structure320. For example, in the magnified view, an imaginary line AA′ passes through the bonding interface layer310, and divides the bonding interface layer310into the layers311aand311b. The interconnect structure320passes through the line AA′. Also illustrated is a side321of the interconnect structure320. The interconnect structure320comprises the interconnect structures319a,319b. Ideally, if the array304and the logic circuitry308are perfectly aligned during the bonding process, the interconnect structures319a,319bwould also be perfectly aligned. However, due to unintentional practical considerations of the bonding process, the array304and the logic circuitry308may not be perfectly aligned during the bonding process, and hence, the interconnect structures319a,319bmay also not be perfectly aligned in the interconnect structure320. For example, the magnified view of the section305shows misalignment or offset between two sections of the interconnect structure320passing through the bonding interface layer310, as illustrated inFIG. 3B. The misalignment or offset may inherently be an unintended consequence of hybrid bonding process. As discussed with respect toFIG. 2C, no such misalignment or offset will be present if the fusion bonding is employed instead.

In an example, as illustrated inFIG. 3B, sections of the interconnect structure320passing through the bonding interface layer310are misaligned, and hence, sections of the misaligned interconnect structure320are exposed (e.g., a section of a bottom surface of the interconnect structure319ais not coupled to a top surface of the interconnect structure319b). Accordingly, in an example, the bonding interface layer310includes a diffusion barrier for the exposed sections of the interconnect structure320. In such an example, the bonding interface layer310comprises Silicon (Si), Carbon (C), Nitrogen (N), and/or Oxygen (O) (e.g., a Si—C—N—O system), e.g., in addition to, or instead of, the examples of material for the bonding interface layer310provided herein previously. That is, the bonding interface layer210includes dielectric with composition mixture of silicon, carbon, nitrogen, and/or oxygen, which is used to enable good bonding, as well as to form a diffusion barrier to the misaligned (and hence exposed) metal (e.g., copper) of the interconnect structure320.

InFIGS. 3A-3B, the metal to metal bonding is a via-to-via bonding. However, hybrid bonding can involve via-to-line bonding as well.FIG. 3Cillustrates an example process of bonding, using hybrid bonding process, a memory array304and logic circuitry308, thereby forming a bonding interface layer310, where the hybrid bonding involves a via-to-line bonding, in accordance with some embodiments. For example, the interconnect structure319aincludes a via comprising conductive material through the layer311a, and the interconnect structure319bincludes a conductive line (e.g., metal line) through the layer311b, and the conductive materials of the via and the lines are bonded during the hybrid bonding process.

FIG. 4illustrates a cross-sectional view of an integrated memory structure (also referred to as a structure400) comprising a first memory array404a, a second memory array404b, and logic circuitry408between the first and second memory arrays, wherein the logic circuitry408is separated from the first and second memory arrays by way of first and second bonding interface layers410a,410b, respectively, in accordance with some embodiments. In an example, the arrays404a,404band the logic circuitry408ofFIG. 4respectively correspond to the arrays104a,104band the logic circuitry108ofFIG. 1. Similarly, the bonding interface layers410a,410brespectively correspond to the bonding interface layers110a,110bofFIG. 1.

In an example, the bonding interface layer410ais formed via fusion bonding (e.g., as discussed with respect toFIGS. 2A-2C) of the array404aand the logic circuitry408, and the bonding interface layer410bis formed via fusion bonding of the array404band the logic circuitry408. In an example, the bonding interface layers410a,410bare similar to the bonding interface layer210ofFIGS. 2A-2C. For example, the bonding interface layers410a,410bcomprise oxide material such as Silicon dioxide (SiO2), nitride material such as Silicon Nitride (Si3N4), etc., although any other appropriate material that are used for bonding two wafer level components may also be used. In an example, a thickness of each of the bonding interface layers410is within a range of about 3000 angstrom to 1 micron.

Details of the memory arrays404a,404bare discussed herein below. However, such details are merely examples, and any appropriate modification of the internal structures of the arrays404a,404bmay be appreciated by those skilled in the art.

The memory array404bis formed on a substrate479. The substrate479, in an example, is a wafer on which multiple such arrays are formed. In an example, the bonding process is performed while the array404bis still on the wafer, i.e., prior to dicing of the wafer. In another example, the bonding process is performed after the dicing of the wafer.

In an example, the array404aincludes memory cells, such as NAND flash memory cells, formed at memory pillars456a. The array404afurther includes conductive access lines to enable access to the memory cells, such as bitlines464a, e.g., which are coming out of the page inFIG. 4(e.g., perpendicular to a plane of the paper), wordlines (WL)420a, select gate source (SGS)452a, and select gate drain (SGD)460a. The wordlines420aare staggered or arranged in a stair-case like pattern. The array404afurther includes current common source (SRC, also referred to as a source plate)455a, located underneath the memory pillars456a.

The array404afurther includes WL connection terminals457a, each WL connection terminal457acoupled to a corresponding WL420a, e.g., via interconnect structures459a. The array404afurther includes SDG connection terminals461a, each SGD connection terminal459acoupled to a corresponding SGD460a, e.g., via interconnect structures459a. The array404acomprises a plurality of metallization levels407acomprising metals, which electrically couple various components within the array404a.

In an example embodiment, the structure400is accessed from a top surface403aof the array404a. For example, the array404acomprises a plurality of interconnect structures407acomprising one or more metallization levels. Interconnect terminals402(although merely one is illustrated inFIG. 4) are coupled to the surface of the array404a, e.g., for connecting the structure400to external components.

In an example, one or more interconnect structures411pass through the array404aand the bonding interface layer410a, e.g., to electrically couple to the logic circuitry408and/or the array404b. The interconnect structures411can be used to transmit signals to and/or from the logic circuitry408and/or the array404b.

In an example, the array404bhas a structure that is at least in part similar to the structure of the array404a. For example, the array404bincludes memory cells, such as NAND flash memory cells, formed at memory pillars456b. The array404bfurther includes conductive access lines to enable access to the memory cells, such as bitlines464b, WL420b, SGS452b, and SGD460b. The array404bfurther includes SRC455b, located underneath the memory pillars456b.

The array404bfurther includes WL connection terminals457b, each WL connection terminal457bcoupled to a corresponding WL420b, e.g., via interconnect structures459b. The array404bfurther includes SDG connection terminals461bcoupled to a corresponding SGD460b, e.g., via interconnect structures459b.

In an example embodiment, various interconnect structures413pass through the array404aand the bonding interface layer410b, and these interconnect structures413transmit access lines signals to and/or from the logic circuitry408and/or the array404b. For example, interconnect structures413atransmit SGD signals to and/or from SGD460bof the array404b(although merely two such interconnect structures413aare illustrated inFIG. 4). Similarly, interconnect structures413btransmit wordline signals to and/or from WLs420bof the array404b. Similarly, interconnect structures413ctransmit SGS signals to and/or from SGS452bof the array404b. Interconnect structure413dtransmits SRC signals to and/or from SRC455bof the array404b. Interconnect structure413etransmits bitline signals to and/or from bitlines464bof the array404b. Thus, at least the interconnect structures411,413extend through the bonding interface layer410a.

In an example embodiment, the logic circuitry408includes various logic circuits, generally illustrated as logic components418a,418b,418c. As discussed with respect toFIG. 1, examples of logic components418include, but are not limited to, address decoders, state machines, buffers, word line drivers, bit line drivers, sense amplifiers, voltage dividers, charge pumps, digital logic blocks, etc. In an example, one or more of the logic components418include CMOS logic. In an example, the logic circuitry408include high voltage logic components (e.g., components and/or transistors that operate at a relatively high voltage, such as in the range of 5 V to 30 V) and/or low voltage logic components (e.g., components and/or transistors that operate at a relatively low voltage, such as in the range of 0.9 V to 5 V). For example, the logic circuitry408includes n-channel metal-oxide semiconductor field-effect transistors (MOSFET), p-channel MOSFETs, or both.

Various interconnect structures415couple the logic circuitry408to the array404b. For example, the interconnect structures415extend through the bonding interface layer410b, thereby coupling the logic circuitry408and the array404b.

Also illustrated inFIG. 4is a magnified view of a section425, where the section425includes a section of the bonding interface layer410aand an interconnect structure413extending through the bonding interface layer410a. As discussed with respect toFIGS. 2A-2C, the interconnect structure413extending through the bonding interface layer410adoes not have any discontinuity, offset or misalignment, e.g., as the array404aand the logic circuitry408are bonded using fusion bonding in an example.

Also illustrated inFIG. 4is a magnified view of a section427, where the section427includes a section of the bonding interface layer410band an interconnect structure415extending through the bonding interface layer410b. As discussed with respect toFIGS. 2A-2C, the interconnect structure415extending through the bonding interface layer410bdoes not have any discontinuity, offset or misalignment, e.g., as the array404band the logic circuitry408are bonded using fusion bonding in an example.

In an example embodiment and as previously discussed herein, the bonding interface layer410aseparates the array404aand the logic circuitry408. For example, the structure400has a left sidewall403mand an opposing right sidewall403n(although “left” and “right” are merely for purposes of ease of identification, and not limiting), and the bonding interface layer410aextends from the left sidewall403mto the right sidewall403n. Similarly, the structure400has a front wall and an opposing back wall (e.g., which are not visible and not labelled inFIG. 4, and which are perpendicular to the left and right sidewalls), and the bonding interface layer410aextends from the front and back walls. That is, the structure400has a top surface and a bottom surface, and a plurality of walls or surfaces extending between the top and bottom surfaces—the bonding interface layer410adivides the structure in its entirety such that the bonding interface layer410aextends to each of the plurality of walls or surfaces. Similarly, the bonding interface layer410balso divides the structure400in its entirety such that the bonding interface layer410bextends to each of the plurality of walls or surfaces. In an example, a first die includes the array404a, a second dies includes the logic circuitry408, and a third die includes the array404b, where the three dies are bonded using the bonding interface layers410a,410b, as discussed herein.

FIGS. 5A, 5B, 5C, 5D, 5E, and 5Fcollectively illustrate a method for forming a memory structure (such as the memory structure400ofFIG. 4) comprising a first memory array (e.g., memory array404a), a second memory array (e.g., memory array404b), and logic circuitry (e.g., logic circuitry408) interposed between the first and second memory arrays, wherein a first bonding interface layer (e.g., bonding interface layer410a) is between the first memory array and the logic circuitry, and a second bonding interface layer (e.g., bonding interface layer410b) is between the second memory array and the logic circuitry, in accordance with some embodiments.

Referring toFIG. 5A, illustrated is the memory array404bformed on the substrate479. The substrate479, in an example, is a wafer on which the array404bis formed. The array404also comprises a layer501aon a surface that is to be bonded with the logic circuitry408, where the layer501amay be similar to the layer211aofFIG. 2A.

Also illustrated inFIG. 5Ais the logic circuitry408formed on a support substrate502. The substrate502, in an example, is a wafer on which the logic circuitry408is formed, e.g., if the logic circuitry408is still on a wafer while bonding with the array404b. In another example, the substrate502is a substrate of a die comprising the logic circuitry408, e.g., if the die comprising the logic circuitry408is to be bonded with the array404b. The logic circuitry408also comprises a layer501bon a surface that is to be bonded with the array404b, where the layer501bmay be similar to the layer211bofFIG. 2A.

Referring now toFIG. 5B, the logic circuitry408is bonded with the array404b, e.g., as discussed with respect toFIG. 2B. For example, the layers501a,501bare bonded to form the bonding interface layer410b. A height of the logic circuitry408is H1, as illustrated. The support substrate502is then de-bonded from the logic circuitry408.

Referring now toFIG. 5C, various conductive structures or interconnect structures513,415, etc. are formed in the logic circuitry408. Some of the conductive structures comprises conductive material (such as metal) deposited within vias that extend through the bonding interface layer410b, such as conductive structures415. For example, as the interconnect structures415are formed after formation of the bonding interface layer410b, there are no offset or misalignment in the interconnect structures415, as illustrated in the magnified view of the section427.

The logic circuitry408comprises a surface515that is opposite to the surface of the logic circuitry408to which the array404bis bonded (e.g., the surface515was attached to the support substrate502inFIG. 5A). Some of the interconnect structures have ends adjacent to, or exposed through, the surface515of the logic circuitry408. In an example embodiment, the interconnect structures415,513are formed by accessing the logic circuitry408through the surface515. In an example embodiment, various metallization levels, vias, interconnect structures are formed within the logic circuitry408, resulting in an increase of a height of the logic circuitry408. For example, inFIGS. 5A-5B, the height of the logic circuitry408is H1, whereas after formation of the interconnect structures the height increases to H2inFIG. 5C.

Referring now toFIG. 5D, layer510cis formed on the surface515of the logic circuitry408, where the layer510cis similar to the layers211ofFIG. 2A. Also illustrated inFIG. 5Dis the array404a, with a layer501dformed on a surface that is to be bonded to the logic circuitry408. The array404amay be supported by a support substrate552, which may be a wafer for example (e.g., if the wafer supporting the array404ahas not been diced yet).

The layer510dis similar to the layers211ofFIG. 2A. A height of the array404ais H3, as illustrated inFIG. 5D. Note that for purposes of illustrative clarity, some of the components of the array404a, which are labelled inFIG. 4, are not labelled inFIG. 5D(or in some of the subsequent figures).

Referring now toFIG. 5E, the logic circuitry408is bonded with the array404a, e.g., as discussed with respect toFIG. 2B, and the support substrate552is de-bonded from the array404a. For example, the layers501c,501dare bonded to form the bonding interface layer410a.

Referring now toFIG. 5F, interconnect structures411,413are formed in the array404a, e.g., using deep via etch. For example, deep through hole vias are formed that extends through the array404aand the bonding interface layer410a, and are filled with conductive material, such as metal, to form the interconnect structures411,413. In an example, such a through hole via is formed over a corresponding interconnect structure513of the logic circuitry408(e.g., where the interconnect structure513is formed inFIG. 5C), such that the conductive material within the via and the interconnect structure513, in combination, form the interconnect structure413.

Furthermore, various metallization levels, various terminals (e.g., such as WL connection terminals457a, SDG connection terminals461a, etc.), etc. are formed near a top of the array404a, e.g., which extends a height of the array404a. For example, the array404ainFIG. 5Fhas a height H4that is greater than the height H3of the array404ainFIG. 5E. That is, at least a section of the array404ais formed after the array404ais bonded with the logic circuitry408. The resultant structure400ofFIG. 5Fis similar to the structure400ofFIG. 4.

Thus, inFIGS. 4 and 5A-5E, the array404band the logic circuitry408of the structure400are bonded using fusion bonding, and the logic circuitry408and the array404aare also bonded using fusion bonding. Thus, interconnect structures extending through a bonding interface layer410is formed after the corresponding components are bonded. However, in another example embodiment, one or both the bonding in the structure400may be hybrid bonding (e.g., as discussed with respect toFIGS. 3A-3E). In such embodiments, the interconnect structures are pre-formed through the layers501a,501band/or layers501c,501d, and the hybrid bonding bonds the corresponding interconnect structures.

FIG. 6illustrates a cross-sectional view of a memory structure600(also referred to as a structure600) comprising a memory array604and logic circuitry608, wherein a bonding interface layer610is interposed between the memory array604and the logic circuitry608, in accordance with some embodiments.

In an example, the memory array604ofFIG. 6is at least in part similar to the memory array404aofFIG. 4, and accordingly, similar components in the two memory arrays are labelled using similar labels, and also individual components within the memory array604ofFIG. 6are not discussed in detail. In an example, the logic circuitry608ofFIG. 6is at least in part similar to the logic circuitry408ofFIG. 4, and accordingly, similar components in the two logic circuitries are labelled using similar labels, and also individual components within the logic circuitry608ofFIG. 6are not discussed in detail.

InFIG. 4, the logic circuitry408was interposed between two arrays404a,404b. In contrast, the logic circuitry608ofFIG. 6is bonded to a single array604. In an example, the bonding between the logic circuitry608and the array604is performed using fusion bonding, thereby forming the bonding interface610(e.g., which is similar to the bonding interfaces410ofFIG. 4). The logic circuitry408is formed on a substrate679.

FIGS. 7A, 7B, and 7Ccollectively illustrate a method for forming a memory structure (such as the memory structure600ofFIG. 6) comprising a memory array (e.g., memory array604) and logic circuitry (e.g., logic circuitry608ofFIG. 6), wherein a bonding interface layer (e.g., bonding interface layer610) is between the memory array and the logic circuitry, in accordance with some embodiments.

Referring toFIG. 7A, illustrated is the logic circuitry608on a substrate679. A layer501b, similar to the layers211ofFIG. 2A, is deposited on the logic circuitry608. Also illustrated is the array604, which may be similar to the array404aofFIG. 5D. The logic circuitry408and the array604are not yet bonded inFIG. 7A.

Referring now toFIG. 7B, the array604is bonded with the logic circuitry608using fusion bonding, as discussed with respect toFIG. 5E. Accordingly, the bonding interface layer610is formed due to the bonding of the layers501a,501b.

Referring now toFIG. 7C, interconnect structures411,413are formed in the array604, e.g., using deep via etch, as discussed with respect toFIG. 5E. Furthermore, various metallization levels, various terminals (e.g., such as WL connection terminals457a, SDG connection terminals461a, etc.), etc. are formed near a top of the array604, e.g., which extends a height of the array604. For example, the array604inFIG. 7Chas a height H4that is greater than the height H3of the array604inFIG. 7B, e.g., as discussed with respect toFIG. 5E. The resultant structure ofFIG. 7Cis the structure600ofFIG. 6.

FIG. 8illustrates a cross-sectional view of a memory structure800(also referred to as a structure800) comprising a first memory array804a, a second memory array804b, and logic circuitry808, wherein a bonding interface layer810is interposed between the second memory array804band the logic circuitry608, without any such bonding interface layer between the first memory array804aand the logic circuitry808, in accordance with some embodiments.

In an example, the memory arrays804a,804bofFIG. 8are at least in part similar to the memory arrays404a,404b, respectively, ofFIG. 4, and accordingly, similar components within the memory arrays in the two figures are labelled using similar labels, and also individual components within the memory arrays804a,804bofFIG. 8are not discussed in detail. In an example, the logic circuitry808ofFIG. 8is at least in part similar to the logic circuitry408ofFIG. 4, and accordingly, similar components in the two logic circuitries are labelled using similar labels, and also individual components within the logic circuitry808ofFIG. 8are not discussed in detail.

In an example embodiment, the logic circuitry808ofFIG. 8is at least in part formed along with the formation of the memory array804a. That is, the logic circuitry808is bot bonded with the memory array804a—rather, the logic circuitry808is formed in situ with the memory array804a, as will be discussed herein in further detail in turn. Thus, the array804aand the logic circuitry808are in a single die, whereas the array804bis in a different die.

In an example embodiment, the combination of the memory array804aand the logic circuitry808is bonded to the memory array804b, via the bonding interface layer810. The bonding interface layer810is at least in part similar to the bonding interface layers410ofFIG. 4.

As will be discussed herein in further detail in turn, a layer815is between the bonding interface layer810and the logic circuitry808. In an example, the bonding interface layer810substantially extends from the sidewall403nto the sidewall403m, and the layer815also substantially extends from the sidewall403nto the sidewall403m. For example, the layer815substantially covers (e.g., covers more than 90%, or more than 95%, or more than 99%) a bottom surface of the logic circuitry808, and the bonding interface layer810substantially covers a bottom surface of the layer815. In an example, the layer815comprises silicon, e.g., crystalline silicon. In an example, the layer815is remnant of a wafer or substrate on which the combination of the array804aand the logic circuitry808are formed, as will be discussed in further detail in turn.

FIGS. 9A, 9B, 9C, and 9Dcollectively illustrate a method for forming a memory structure (such as the memory structure800ofFIG. 8) comprising a first memory array (e.g., array804a), a second memory array (e.g., array804b), and logic circuitry (e.g., logic circuitry808), wherein a bonding interface layer (e.g., bonding interface layer810) is interposed between the second memory array and the logic circuitry, without any such bonding interface layer between the first memory array and the logic circuitry, in accordance with some embodiments.

Referring toFIG. 9A, illustrated is a combination of the array804aand the logic circuitry808formed on a wafer915, such as a silicon wafer.

Referring now toFIG. 9B, a temporary carrier wafer919is attached to a top surface of the combination of the array804aand the logic circuitry808(e.g., where an opposite bottom surface of the combination of the array804aand the logic circuitry808has the wafer915attached thereon). Subsequently, the wafer915is polished or otherwise thinned, to decrease a height of the wafer915, thereby forming the layer815. For example, inFIG. 9A, the original height of the wafer915is Hw1, and the wafer915is thinned such that a height of the layer815inFIG. 9Bis Hw2, where Hw2is less than Hw1. In an example, the height Hw2of the layer815is in the range of 7 microns to 10 microns.

Referring now toFIG. 9C, layer901ais deposited on a bottom surface of the layer815. Also, illustrated inFIG. 9Cis the array804b, with layer901bdeposited on a top surface of the array804b. The layers901a,901bare similar to the layers501ofFIG. 5A.

After deposition of the layer901a(and before the bonding process), vias are formed through the layers901a,815, and filled with conductive material such as metal, to form interconnection structures915athrough the layers901a,815. The combination of the array804aand the logic circuitry808is accessed from the bottom surface (e.g., from the exposed surface of the layer901a) while forming the vias for the interconnection structures915a.

Similarly, after deposition of the layer901b, vias are formed through the layer901b, and filled with conductive material such as metal, to form interconnection structures915bthrough the layer901b. The array804bis accessed from the top surface (e.g., from the exposed surface of the layer901a) while forming the vias for the interconnection structures915b.

Thus, each of the layers901aand901bhave openings through which tips of the corresponding interconnect structures915a,915bare exposed (e.g., similar to that discussed with respect toFIGS. 3A-3B). For example, the conductive material of the tips of the interconnect structures915aexposed through the layer901aand the bottom surface of the layer901aare flush or co-planar. For example, the bottom surface of the layer901ais polished, to that tips of the interconnect structures915aexposed through the layer901aand the bottom surface of the layer901aare flush or coplanar. Similarly, the conductive material of the tips of the interconnect structures915bexposed through the layer901aand the bottom surface of the layer901aare flush or at the same level, i.e., coplanar.

Referring now toFIG. 9D, the layers901aand901bare bonded to form the bonding interface layer810. During the bonding process, two corresponding interconnect structures915a,915bare also bonded or otherwise come in contact, to form a common interconnect structure415. Thus, the bonding is between the layers901a,901b, as well as between corresponding ones of the interconnect structures915a,915b—accordingly, as discussed with respect toFIGS. 3A-3B, the bonding ofFIG. 9Dis a hybrid bonding. As also discussed with respect toFIGS. 3A-3B, there is a misalignment or offset in two sections of the interconnect structure415inFIG. 9D, which is illustrated in a magnified view of a section427. AlthoughFIG. 9Dillustrates multiple via-to-via bonding through the layer810(e.g., as discussed with respect toFIGS. 3A-3B), there may be via-to-line bonding as well through the layer810(e.g., as discussed with respect toFIG. 3C). The resultant structure ofFIG. 9Dis the structure800ofFIG. 8.

FIG. 10illustrates an example computing system implemented with integrated memory structures disclosed herein, in accordance with one or more embodiments of the present disclosure. As can be seen, the computing system2000houses a motherboard2002. The motherboard2002may include a number of components, including, but not limited to, a processor2004and at least one communication chip2006, each of which can be physically and electrically coupled to the motherboard2002, or otherwise integrated therein. As will be appreciated, the motherboard2002may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system2000, etc.

Any memory, such as any flash memory (e.g., a 3D NAND flash memory), included in computing system2000may include one or more memory arrays bonded with logic circuitry, as discussed herein. In an example, the logic circuitry is interposed between, and shared among, two memory arrays, as discussed herein.

The processor2004of the computing system2000includes an integrated circuit die packaged within the processor2004. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip2006also may include an integrated circuit die packaged within the communication chip2006. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor2004(e.g., where functionality of any chips2006is integrated into processor2004, rather than having separate communication chips). Further note that processor2004may be a chip set having such wireless capability. In short, any number of processor2004and/or communication chips2006can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

FURTHER EXAMPLE EMBODIMENTS

Numerous variations and configurations will be apparent in light of this disclosure and the following examples.

Example 1. An integrated circuit memory comprising: a memory array comprising a plurality of memory cells; a logic circuitry; and a layer comprising silicon and having a thickness of at least 3000 angstrom, the layer between the memory array and the logic circuitry.

Example 2. The integrated circuit memory of example 1, wherein: the memory array comprises a first sidewall and an opposing second sidewall; and the layer extends from the first sidewall to the second sidewall.

Example 3. The integrated circuit memory of any of examples 1-2, wherein the layer further comprises at least one of oxygen or nitrogen.

Example 4. The integrated circuit memory of any of examples 1-3, wherein the logic circuitry comprises one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and/or a digital logic block.

Example 5. The integrated circuit memory of any of examples 1-4, wherein the logic circuitry comprises: a first one or more transistors that operate at a first voltage in the range of 5 volts (V) to 30 V; and a second one or more transistors that operate at a second voltage in the range of 0.9 V to 5 V.

Example 6. The integrated circuit memory of any of examples 1-5, wherein the logic circuitry comprises complementary metal-oxide-semiconductor (CMOS) logic.

Example 7. The integrated circuit memory of any of examples 1-6, wherein the memory array is included in a first die that is bonded to a second die comprising the logic circuitry.

Example 8. The integrated circuit memory of example 7, wherein the layer is a bonding interface layer between the first die and the second die.

Example 9. The integrated circuit memory of any of examples 1-8, wherein the memory array is a first memory array, the layer is a first layer, the integrated circuit memory further comprising: a second memory array, wherein the logic circuitry is between the first and second memory arrays; and a second layer comprising silicon and having a thickness of at least 3000 angstrom, the second layer between the second memory array and the logic circuitry.

Example 10. The integrated circuit memory of example 9, wherein: the first memory array is included in a first die that is bonded to a second die comprising the logic circuitry; the second memory array is included in a third die that is bonded to the second die; the first layer is a first bonding interface layer between the first die and the second die; the second layer is a second bonding interface layer between the third die and the second die; and one or more logic components of the logic circuitry is shared by the first and second memory arrays.

Example 11. The integrated circuit memory of any of examples 1-10, wherein the memory array is a first memory array, the integrated circuit memory further comprising a second memory array, wherein: the first memory array and the logic circuitry are included in a first die; the second memory array is included in a second die that is bonded to the first die; the layer is a bonding interface layer between the first die and the second die; and the logic circuitry is between the first and second memory arrays and one or more logic components of the logic circuitry is shared by the first and second memory arrays.

Example 12. The integrated circuit memory of any of examples 1-8, wherein the layer is a first layer, the integrated circuit memory further comprising: a second layer in direct contact with the first layer, the second layer comprising silicon, the second layer compositionally different from the first layer.

Example 13. The integrated circuit memory of example 12, further comprising: an interconnect structure extending through the first layer and the second layer, wherein the interconnect structure has a first portion that extends through the second layer and a first section of the first layer, and a second portion that extends through a second section of the first layer, and wherein the first portion of the interconnect structure is offset with respect to the second portion of the interconnect structure.

Example 14. The integrated circuit memory of any of examples 12-13, wherein: a length and a width of the first layer is substantially similar to a length and width, respectively, of the second layer.

Example 15. The integrated circuit memory of any of examples 12-13, wherein: the memory array comprises a first sidewall and an opposing second sidewall; and each of the first layer and the second layer extends from the first sidewall to the second sidewall.

Example 16. The integrated circuit memory of any of examples 12-13, wherein: the second layer has a thickness in the range of 7 microns to 10 microns.

Example 17. The integrated circuit memory of any of examples 1-16, wherein the memory array is flash memory array.

Example 18. The integrated circuit memory of any of examples 1-17, wherein the memory array is three-dimensional (3D) NAND flash memory array.

Example 19. A motherboard, wherein the integrated circuit memory of any of examples 1-18 is attached to the motherboard.

Example 20. A computing system comprising the integrated circuit memory of any of examples 1-19.

Example 21. An integrated circuit memory comprising: a first die including a first memory array; a second die including a second memory array; a third die including logic circuitry comprising a plurality of logic components, the third die between the first and second dies; a first bonding interface that bonds the first die to the third die; and a second bonding interface that bonds the second die to the third die.

Example 22. The integrated circuit memory of example 21, wherein: at least one of the first and second bonding interfaces comprises silicon and oxygen, and has a thickness of at least 3000 angstrom.

Example 23. The integrated circuit memory of any of examples 21-22, wherein: at least one of the first and second bonding interfaces comprises silicon and nitrogen, and has a thickness of at least 3000 angstrom.

Example 24. The integrated circuit memory of any of examples 21-23, wherein: the first die has a first surface facing a second surface of the third die; and the first bonding interface is on substantially an entirety of the first surface of the first die.

Example 25. The integrated circuit memory of any of examples 21-24, wherein: the first bonding interface is on substantially an entirety of the second surface of the third die.

Example 26. The integrated circuit memory of any of examples 21-25, wherein the plurality of logic components includes one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, and/or a digital logic block.

Example 27. The integrated circuit memory of any of examples 21-26, wherein the plurality of logic components includes: a first one or more transistors that operate at a first voltage in the range of 5 volts (V) to 30 V; and a second one or more transistors that operate at a second voltage in the range of 0.9 V to 5 V.

Example 28. The integrated circuit memory of any of examples 21-27, wherein the first and second memory arrays are three-dimensional (3D) flash memory arrays and the logic components include complementary metal oxide semiconductor (CMOS) logic components.

Example 29. The integrated circuit memory of any of examples 21-28, wherein the first and second memory arrays are three-dimensional (3D) NAND flash memory arrays.

Example 30. A motherboard, wherein the integrated circuit memory of any of examples 21-29 is attached to the motherboard.

Example 31. A computing system comprising the integrated circuit memory of any of examples 21-30.

Example 32. An integrated circuit memory comprising: a first die including a first memory array and logic circuitry; a second die including a second memory array; and a bonding interface that bonds the first die to the second die, wherein the logic circuitry is between the first and second memory arrays, wherein one or more logic components of the logic circuitry is shared by the first and second memory arrays.

Example 33. The integrated circuit memory of example 32, wherein the first and second memory arrays are three-dimensional (3D) NAND flash memory arrays.

Example 34. A motherboard, wherein the integrated circuit memory of any of examples 32-33 is attached to the motherboard.

Example 35. A computing system comprising the integrated circuit memory of any of examples 32-34.

Example 36. A method to form an integrated flash memory structure, the method comprising: forming a memory array having a first layer on a surface of the memory array; forming a logic circuitry having a second layer on a surface of the logic circuitry; and bonding the memory array and the logic circuitry using the first layer and the second layer.

Example 37. The method of example 36, further comprising: subsequent to bonding the memory array and the logic circuitry, forming a via through a bonding interface that is formed between the memory array and the logic circuitry; and depositing metal material within the via.

Example 38. The method of example 36, further comprising: prior to bonding the memory array and the logic circuitry, forming a first conductive structure that extends through the first layer and a second conductive structure that extends through the second layer, wherein subsequent to bonding the memory array and the logic circuitry, the first conductive structure and the second conductive structure are bonded to form an integrated conductive structure.

Example 39. The method of example 38, wherein within the integrated conductive structure, the first conductive structure is misaligned with respect to the second conductive structure.

Example 40. The method of example 39, wherein the first conductive structure is one of a first via comprising conductive material or a first conductive line, and the second conductive structure is one of a second via comprising conductive material or a second conductive line.

Example 41. The method of any of examples 38-40, wherein: prior to bonding the memory array and the logic circuitry, the first conductive structure is exposed through a first surface of the first layer that is to be bonded with the second layer, and a tip of the first conductive structure is flush with the first surface; and prior to bonding the memory array and the logic circuitry, the second conductive structure is exposed through a second surface of the second layer that is to be bonded with the first layer, and a tip of the second conductive structure is flush with the second surface.

Example 42. The method of any of examples 36-41, wherein the memory array is a first memory array, the method further comprising: forming a second memory array having a third layer on a surface of the second memory array; forming a fourth layer on another surface of the logic circuitry; and bonding the second memory array and the logic circuitry using the third layer and the fourth layer.

Example 43. The method of example 42, wherein the logic circuitry is between the first and second memory arrays.

Example 44. The method of example 36, wherein: the memory array is a first memory array; bonding the first memory array and the logic circuitry comprises bonding the first layer and the second layer to form a bonding interface layer; forming the logic circuitry comprises forming the logic circuitry along with forming a second memory array, such that no bonding interface layer is between the logic circuitry and the second memory array; and bonding the first memory array and the logic circuitry comprises bonding the first memory array with a combination of the logic circuitry and the second memory array.

The foregoing detailed description has been presented for illustration. It is not intended to be exhaustive or to limit the disclosure to the precise form described. Many modifications and variations are possible in light of this disclosure. Therefore it is intended that the scope of this application be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.