THREE-DIMENSIONAL MEMORY DEVICES INCLUDING SELF-ALIGNED SOURCE-CHANNEL JUNCTIONS AND METHODS FOR FORMING THE SAME

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor source cap structure which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel, and a source layer contacting at least a first end surface segment of the semiconductor source cap structure.

FIELD

The present disclosure relates generally to the field of semiconductor devices, and particularly to three-dimensional memory devices including self-aligned source-channel junctions and methods for forming the same.

BACKGROUND

SUMMARY

According to an aspect of the present disclosure, a semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor source cap structure which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel, and a source layer contacting at least a first end surface segment of the semiconductor source cap structure.

According to another aspect of the present disclosure, a method of forming a semiconductor structure comprises: forming a source-side spacer layer over a carrier substrate; forming an alternating stack of insulating layers and spacer material layers over the source-side spacer layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming a memory opening through the alternating stack and the source-side spacer layer; forming a memory film at a peripheral portion of the memory opening; forming a source cap structure at a bottom portion of the memory film; forming a vertical semiconductor channel on a top surface of the source cap structure and on an inner sidewall of the memory film; removing the carrier substrate; and forming a source layer on an exposed bottom surface segment of the source cap structure.

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to a three-dimensional memory device containing self-aligned channel cap structures and methods for forming the same, the various aspects of which are described below. Embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include three-dimensional memory devices comprising a plurality of memory strings.

Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that may be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded throughout, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that may independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many a number of external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations may be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within a same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that may be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that may be selected for programming. A page is also the smallest unit that may be selected to a read operation.

Referring toFIG.1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated. The first exemplary structure comprises a carrier substrate9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate9may comprise a commercially available silicon wafer. Alternatively, the carrier substrate9may comprise any material that may be removed selective the materials of insulating layers and dielectric material portions to be subsequently formed. In case the carrier substrate9comprise silicon (e.g., a single crystal silicon wafer), at least a top surface portion of the carrier substrate9may be doped with boron to act as an etch stop and to prevent collateral etching during a subsequent etching step. As used herein, an etch process etches a first material selective to a second material if the etch rate of the etch process for the first material is at least three times the etch rate for the second material. The atomic concentration of boron in at least the boron-doped portion of the carrier substrate9(or in the entire carrier substrate) may be at least 1×1019/cm3, such as in a range from 5×1019/cm3to 2×1021/cm3, such as from 1×1020/cm3to 1×1021/cm3, although lesser and greater thicknesses may also be employed.

A backside stopper layer12can be formed on the top surface of the carrier substrate9. The backside stopper layer12comprises an insulating material, such as silicon oxide, and may have a thickness in a range from 10 nm to 200 nm, such as from 20 nm to 100 nm, although lesser and greater thicknesses may also be employed. The backside stopper layer12may be deposited on the carrier substrate9by chemical vapor deposition, atomic layer deposition or sputtering. Alternatively, if the carrier substrate9comprises a silicon substrate, then the backside stopper layer12may be formed by oxidizing an upper surface of the carrier substrate9.

A source-side spacer layer14can be formed over the backside stopper layer12. The source-side spacer layer14has a uniform thickness, which may be in range from 50 nm to 1,000 nm, such as from 100 nm to 500 nm, although lesser and greater thicknesses may also be employed. The source-side spacer layer14may comprise a semiconductor material, a conductive material, or an insulating material. Generally, the source-side spacer layer14comprises a material that is different from the materials of an alternating stack of insulating layers and spacer material layers (such as sacrificial material layers) to be subsequently formed. Further, the source-side spacer layer14comprises a material providing a greater etch resistance than the materials of the alternating stack during an anisotropic etch process to be subsequently employed to form openings through the alternating stack.

In one embodiment, the source-side spacer layer14comprises and/or consists essentially of a semiconductor material, which may be an elemental semiconductor material such as silicon (e.g., polysilicon) or germanium, or a compound semiconductor material such as silicon-germanium or a III-V compound semiconductor material. In one embodiment, vertical semiconductor channels to be subsequently formed comprises dopants of a first conductivity type (which may be p-type or n-type), and the source-side spacer layer14comprises doped semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type. In one embodiment, the atomic concentration of electrical dopants of the second conductivity type in the source-side spacer layer14may in a range from 1×1016/cm3to 1×1020/cm3, such as from 1×1018/cm3to 5×1019/cm3.

The first exemplary structure comprises a memory array region100in which a three-dimensional array of memory elements is subsequently formed, and a contact region300in which layer contact via structures are formed, which contact word lines embodied as electrically conductive layers.

Referring toFIG.2, a first alternating stack of insulating layers32and spacer material layers can be formed over the carrier substrate9. The spacer material layers may be formed as sacrificial material layers42. In case a second alternating stack of additional insulating layers and additional spacer material layers is subsequently formed over the first alternating stack to form a multi-tier structure, the first alternating stack is referred to as a first-tier alternating stack, and the second alternating stack is referred to as a second-tier alternating stack. In this case, the insulating layers32within the first-tier alternating stack are herein referred to as first insulating layers132, and spacer material layers (such as the sacrificial material layers42) within the first-tier alternating stack are herein referred to as first spacer material layers (such as first sacrificial material layers142). In one embodiment, the first spacer material layers may comprise first sacrificial material layers142. In this case, a first-tier alternating stack (132,142) of first insulating layers132and first sacrificial material layers142can be formed over the source-side spacer layer14.

The first insulating layers132comprise an insulating material such as undoped silicate glass or a doped silicate glass, and the first sacrificial material layers142comprise a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the first insulating layers132may comprise silicon oxide layers, and the first sacrificial material layers142may comprise silicon nitride layers. The first-tier alternating stack (132,142) may comprise multiple repetitions of a unit layer stack including a first insulating layer132and a first sacrificial material layer142. The total number of repetitions of the unit layer stack within the first-tier alternating stack (132,142) may be, for example, in a range from 8 to 1,024, such as from 32 to 256, although lesser and greater number of repetitions may also be employed.

Each of the first insulating layers132may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each of the first sacrificial material layers142may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. The first exemplary structure comprises a memory array region100in which a three-dimensional array of memory elements is to be subsequently formed, and a contact region300in which layer contact via structures contacting word lines are to be subsequently formed.

While an embodiment is described in which the first spacer material layers are formed as first sacrificial material layers142, the first spacer material layers may be formed as first electrically conductive layers in an alternative embodiment. In this case, processing steps performed to replace the first sacrificial material layers142with first electrically conductive layers may be omitted. Generally, spacer material layers of the present disclosure may be formed as, or may be subsequently replaced with, electrically conductive layers.

The first stepped surfaces of the first-tier alternating stack (132,142) continuously extend from a bottommost layer within the first-tier alternating stack (132,142) to a topmost layer within the first-tier alternating stack (132,142).

A first stepped dielectric material portion165(i.e., an insulating fill material portion) can be formed in the first stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost layer of the first-tier alternating stack (132,142), for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the first stepped cavity constitutes the first stepped dielectric material portion165. As used herein, a “stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases or decreases stepwise as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the first stepped dielectric material portion165, the silicon oxide of the first stepped dielectric material portion165may, or may not, be doped with dopants such as B, P, and/or F.

Referring toFIG.4, a first etch mask layer (such as a photoresist layer) can be formed over the first-tier alternating stack (132,142), and can be lithographically patterned to form openings therein. A first anisotropic etch process can be performed to transfer the pattern of the openings in the first etch mask layer through the first stepped dielectric material portion165, the first-tier alternating stack (132,142), and the source-side spacer layer14. The first anisotropic etch process may comprise a first etch step having a first anisotropic etch chemistry that etches the materials of the first stepped dielectric material portion165and the first-tier alternating stack (132,142) while forming vertical or substantially vertical sidewalls. The first anisotropic etch chemistry may be selective to the material of the source-side spacer layer14, i.e., may etch the materials of the first stepped dielectric material portion165and the first-tier alternating stack (132,142) at a significantly higher etch rate than the material of the source-side spacer layer14. The source-side spacer layer14may be employed as an etch stop structure for the first etch step of the first anisotropic etch process.

Further, the first anisotropic etch process may comprise a second etch step having a second anisotropic etch chemistry that etches the material of the source-side spacer layer14while forming tapered sidewalls around voids formed by removal of the material of the source-side spacer layer14. In one embodiment, the backside stopper layer12may be employed as an etch stop layer for the second etch step of the first anisotropic etch process.

First-tier memory openings149can be formed through the first-tier alternating stack (132,142) and the source-side spacer layer14in the memory array region100, and first-tier support openings119can be formed through the first stepped dielectric material portion165, the first-tier alternating stack (132,142), and the source-side spacer layer14in the contact region300. Each of the first-tier memory openings149and the first-tier support openings119can have a respective bottom surface that is formed on the top surface of the backside stopper layer12or slightly below the top surface of the backside stopper layer12. The first-tier memory openings149and the first-tier support openings119may have a diameter in a range from 40 nm too 400 nm, such as from 80 nm to 200 nm, although lesser and greater thicknesses may be employed. The first etch mask layer can be removed, for example, by ashing after the first anisotropic etch process.

In one embodiment, each of the first-tier memory openings149and the first-tier support openings119may comprise a respective top cavity portion having a cylindrical shape, and a respective bottom cavity portion having a shape of an inverted cone or an inverted conical frustum. As used herein, an inverted cone refers to a cone having an apex at a bottommost point. As used herein, an inverted conical frustum refers to a conical frustum having a variable lateral extent that increases with a vertical distance upward. An inverted conical frustum can be derived from an inverted cone by removing a bottommost portion of the inverted cone. Each bottom cavity portion of the first-tier memory openings149and the first-tier support openings119comprises a respective tapered conical sidewall TCS. The taper angle of the tapered conical sidewalls TCS relative to the vertical direction may be in a range from 3 degrees to 30 degrees, such as from 5 degrees to 15 degrees, although lesser and greater angles may also be employed. Thus, the source-side spacer layer14comprises openings that are defined by the tapered conical sidewalls TCS. The lateral extent of each opening in the source-side spacer layer14increases with a vertical distance from a horizontal plane including an interface between the source-side spacer layer14and the backside stopper layer12toward the first-tier alternating stack (132,142).

Referring toFIG.5, a sacrificial fill material, such as a carbon-based material (e.g., amorphous carbon, diamond-like carbon, or a doped carbon material), a high etch-rate dielectric material (e.g., borosilicate glass or organosilicate glass), or a polymer material, can be deposited in the first-tier memory openings149and in the first-tier support openings119by a conformal deposition process. Excess portions of the sacrificial fill material can be removed from above the top surface of the first-tier alternating stack (132,142), for example, by a recess etch process. Each remaining portion of the sacrificial fill material that fills a respective first-tier memory opening149constitutes a sacrificial memory opening fill structure148. Each remaining portion of the sacrificial fill material that fills a respective first-tier support opening119constitutes a sacrificial support opening fill structure118. In one embodiment, each of the sacrificial memory opening fill structures148and the sacrificial support opening fill structures118comprises a respective upper cylindrical portion and a respective lower portion having a shape of an inverted cone or an inverted conical frustum.

Referring toFIG.6, a second-tier alternating stack (232,242) of second insulating layers232and second spacer material layers may be formed above the first-tier alternating stack (132,142) and the first stepped dielectric material portion165. The second insulating layers232can be additional insulating layers32having a same material composition and a same thickness range as the first insulating layers132. The second spacer material layers can be additional spacer material layers having a same material composition and a same thickness range as the first spacer material layers in the first-tier alternating stack (132,142). In one embodiment, the second spacer material layers may comprise second sacrificial material layers242. In this case, the second sacrificial material layers242can be additional sacrificial material layers42having a same material composition and a same thickness range as the first sacrificial material layers142. The first insulating layers132and the second insulating layers232are collectively referred to as insulating layers32. The first sacrificial material layers142and the second sacrificial material layers242are collectively referred to as sacrificial material layers42.

The second-tier alternating stack (232,242) may comprise multiple repetitions of a unit layer stack including a second insulating layer232and a second sacrificial material layer242. The total number of repetitions of the unit layer stack within the second-tier alternating stack (232,242) may be, for example, in a range from 8 to 1,024, such as from 32 to 256, although lesser and greater number of repetitions may also be employed. Each of the second insulating layers232may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each of the second sacrificial material layers242may have a thickness in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed.

While an embodiment is described in which the second spacer material layers are formed as second sacrificial material layers242, the second spacer material layers may be formed as second electrically conductive layers in an alternative embodiment. In this case, processing steps performed to replace the second sacrificial material layers242with second electrically conductive layers may be omitted. Generally, spacer material layers of the present disclosure may be formed as, or may be subsequently replaced with, electrically conductive layers.

Optional stepped surfaces are formed in the contact region300by patterning the second-tier alternating stack (232,242). The stepped surfaces of the second-tier alternating stack (232,242) may be laterally offset toward the memory array region100relative to the stepped surfaces of the first-tier alternating stack (132,142) in a plan view. A second stepped cavity is formed within the volume from which portions of the second-tier alternating stack (232,242) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces. The second stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the second stepped cavity changes in steps as a function of the vertical distance from the top surface of the carrier substrate9. In one embodiment, the second stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type.

The stepped surfaces of the second-tier alternating stack (232,242) continuously extend from a bottommost layer within the second-tier alternating stack (232,242) to a topmost layer within the second-tier alternating stack (232,242).

A second stepped dielectric material portion265(i.e., an insulating fill material portion) can be formed in the second stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost layer of the second-tier alternating stack (232,242), for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the second stepped cavity constitutes the second stepped dielectric material portion265. If silicon oxide is employed for the second stepped dielectric material portion265, the silicon oxide of the second stepped dielectric material portion265may, or may not, be doped with dopants such as B, P, and/or F. The combination of the first stepped dielectric material portion165and the second stepped dielectric material portion265may be collectively referred to as a stepped dielectric material portion65.

Referring toFIG.7, a second etch mask layer (such as a photoresist layer) can be formed over the second-tier alternating stack (232,242), and can be lithographically patterned to form openings therein. The pattern of the openings in the second etch mask layer may be the same as the pattern of the sacrificial opening fill structures (148,118). A second anisotropic etch process can be performed to transfer the pattern of the openings in the second etch mask layer through the second stepped dielectric material portion265and the second-tier alternating stack (232,242). Second-tier memory openings249can be formed through the second-tier alternating stack (232,242) directly on a top surface of a respective sacrificial memory opening fill structure148in the memory array region100. Second-tier support openings219can be formed through the second stepped dielectric material portion165and the second-tier alternating stack (232,242) directly on a top surface of a respective sacrificial support opening fill structure118in the contact region300.

Each of the second-tier memory openings249and the second-tier support openings219may have about the same diameter as the diameter of a respective underlying sacrificial opening fill structure (148,118). Ideally, the second-tier memory openings249have a 100% areal overlap with the sacrificial memory opening fill structures148, and the second-tier support openings219have a 100% areal overlap with the sacrificial support opening fill structures118. In practice, a finite lithographic overlay error between the pattern of the opening in the second etch mask layer and the first etch mask layer may reduce the percentage of the areal overlap to a range between 50% and 100%. The second etch mask layer can be removed, for example, by ashing after the second anisotropic etch process.

Referring toFIGS.8A and8B, the sacrificial memory opening fill structures148and the sacrificial support opening fill structures118may be removed selective to the materials of the second-tier alternating stack (232,242), the first-tier alternating stack (132,142), the stepped dielectric material portion65, the source-side spacer layer14, and the backside stopper layer12. In an illustrative example, if the sacrificial memory opening fill structures148and the sacrificial support opening fill structures118comprise a carbon-based material, an ashing process may be performed to remove the sacrificial memory opening fill structures148and the sacrificial support opening fill structures118. Inter-tier memory openings49(which are also referred to as memory openings49) can be formed through the second-tier alternating stack (232,242), the first-tier alternating stack (132,142), the source-side spacer layer14, and the backside stopper layer12, and optionally into an upper portion of the carrier substrate9. Inter-tier support openings19(which are also referred to as support openings19) can be formed through the stepped dielectric material portion65, at least through the first-tier alternating stack (132,142) and optionally through the second-tier alternating stack (232,242), and through the source-side spacer layer14and the backside stopper layer12, and optionally into an upper portion of the carrier substrate9.

In summary, a source-side spacer layer14can be formed over a carrier substrate9, and at least one alternating stack of insulating layers32and spacer material layers (such as sacrificial material layers42) may be formed over the source-side spacer layer14in the first exemplary structure. The spacer material layers are formed as, or are subsequently replaced with (if formed as sacrificial material layers42), electrically conductive layers. Memory openings49can be formed through the alternating stack (32,42) in the memory array region100. The alternating stack (32,42) may comprise a single-tier structure including a single stepped dielectric material portion, or may comprise a multi-tier structure including a first-tier alternating stack (132,142) and a first stepped dielectric material portion165as a first-tier structure, and a second-tier alternating stack (232,242) and a second stepped dielectric material portion265as a second-tier structure, and optionally including additional tier structures (not shown) that are formed above the second-tier structure.

Each of the memory openings49can vertically extend at least to a top surface of the backside stopper layer12. In one embodiment, bottom surfaces of the memory openings49may be formed on a top surface of the backside stopper layer12. Each cluster of memory openings49may comprise a plurality of rows of memory openings49. Each row of memory openings49may comprise a plurality of memory openings49that are arranged along the first horizontal direction hd1with a uniform pitch. The rows of memory openings49may be laterally spaced among one another along the second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd2. In one embodiment, each cluster of memory openings49may be formed as a two-dimensional periodic array of memory openings49. The memory openings49may have a diameter in a range from 60 nm too 400 nm, such as from 120 nm to 300 nm, although lesser and greater thicknesses may be employed. In the alternative embodiment, the support openings19are formed at the same time as the memory openings49using the same patterned photoresist layer. In one embodiment, each of the memory openings49and support openings19may comprise a bottom cavity portion having a shape of an inverted cone or an inverted conical frustum.

FIGS.9A-9Gare sequential vertical cross-sectional views of a memory opening49during formation of a memory opening fill structure58in the first exemplary structure according to the first embodiment of the present disclosure. A similar structural change may occur in every other memory opening49and in each of the support openings19during the processing steps ofFIGS.9A-9G.

Referring toFIG.9A, a memory opening49is illustrated after the processing steps ofFIGS.8A and8B. The memory opening49comprises a cylindrical cavity portion that vertically extends through the at least one alternating stack {(132,142), (232,242)}, and a bottom cavity portion having a shape of an inverted cone or an inverted conical frustum and laterally surrounded by a tapered conical sidewall TCS.

Referring toFIG.9B, a memory film50including a memory material layer54can be conformally deposited. In an illustrative example, the memory film50may comprise an optional blocking dielectric layer52, the memory material layer54, and an optional dielectric liner56. The memory material layer54includes a memory material, i.e., a material that can store data bits therein. The memory material layer54may comprise a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in the electrical resistivity, ferroelectric polarization, or any other measurable physical property. In case the memory material layer54comprises a charge storage material, the optional dielectric liner56may comprise a tunneling dielectric layer. The memory film50is formed on exposed surfaces of the memory openings49.

Referring toFIG.9C, a conformal semiconductor deposition process can be performed to deposit a doped semiconductor fill material in each memory opening49and in each support opening19to form a conformal doped semiconductor layer16L. The doped semiconductor fill material has a doping of a second conductivity type, which is the opposite of the first conductivity type of vertical semiconductor channels to be subsequently formed. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. For example, the conformal doped semiconductor layer16L may comprise n-type, phosphorus doped polysilicon or amorphous silicon. The atomic concentration of dopants of the second conductivity type in the doped semiconductor fill material may be in a range form 1.0×1014/cm3to 1.0×1021/cm3, such as from 1.0×1016/cm3to 1.0×1020/cm3, although lesser and greater atomic concentrations may also be employed.

The thickness of the conformal doped semiconductor layer16L may be greater than one half of the diameter of at least a bottom of the cavity portion having the shape of the inverted cone or an inverted conical frustum, and less than one half of the diameter of each memory opening49and may be less than one half of the diameter of each support opening19at the levels of the alternating stack (32,42). In this case, a cavity may be present within each memory opening49and within each support opening19at the levels of the alternating stack (32,42), while at least the bottom of the cavity portion having the shape of the inverted cone or an inverted conical frustum is completely filled with the conformal doped semiconductor layer16L.

Referring toFIG.9D, an isotropic etch back process may be performed to isotropically recess the conformal doped semiconductor layer16L. All portions of the conformal doped semiconductor layer16L can be removed except bottommost portions of the conformal doped semiconductor layer16L located at bottom portions of conical or frustum-shaped bottom portions of the memory openings49and the support openings19. Removal of the material of the conformal doped semiconductor layer16L is isotropic during the isotropic etch back process, and thus, remaining portions of the conformal doped semiconductor layer16L comprise bottommost tip portions of the conformal doped semiconductor layer16L at a respective bottom portion of the memory openings49and the support openings19. Remaining portions of the conformal doped semiconductor layer16L in the memory openings49after the isotropic etch back process function as topmost capping portions of a source structure, and are hereafter referred to source cap structures16. The source cap structures16is located inside of and is surrounded by the memory film50.

In summary, the source cap structures16may be formed by conformally depositing and isotropically etching a doped semiconductor material, and each remaining portion of the doped semiconductor material comprises a source cap structure16. Each source cap structure16comprises a tapered annular surface that contact a respective memory film50, and may comprise a first end surface segment ESS1that contacts an underlying portion of the respective memory film50. In one embodiment, each source cap structure16may comprise a second end surface segment ESS2, which is a concave surface segment that is exposed to an overlying void in a respective memory opening49or in a respective support opening19. In one embodiment, the second end surface segments ESS2of the source cap structures16may be located entirely between a first horizontal plane HP1including the first horizontal surface (such as a top surface) of the source-side spacer layer14and a second horizontal plane HP2including a second horizontal surface (such as a bottom surface) of the source-side spacer layer14.

Referring toFIG.9E, a semiconductor channel material layer60L can be deposited on the memory film50and each of the second end surface segments ESS2of the source cap structures16by performing a conformal deposition process. In one embodiment, the semiconductor channel material layer60L may be doped with dopants of the first conductivity type, which is the opposite of the second conductivity type. The atomic concentration of dopants of the first conductivity type in the semiconductor channel material layer60L may be in a range from 1.0×1012/cm3to 3.0×1017/cm3, such as from 1.0×1014/cm3to 3.0×1016/cm3, although lesser and greater atomic concentrations may also be employed. The thickness of the semiconductor channel material layer60L may be in a range from 3 nm to 60 nm, such as from 6 nm to 30 nm, although lesser and greater thicknesses may also be employed. In one embodiment, each bottom portion of the semiconductor channel material layer60L located within a respective memory opening49may comprise a convex surface that contacts the concave surface segment ESS2of a respective source cap structure16. A p-n junction can be formed at each interface between the semiconductor channel material layer60L and the source cap structures16.

Referring toFIG.9F, a dielectric core layer comprising a dielectric fill material, such as silicon oxide, can be deposited in remaining volumes of the memory openings49. The dielectric core layer can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at, or about, the horizontal plane including the bottom surface of a topmost insulating layers32. Each remaining portion of the dielectric core layer constitutes a dielectric core62.

Referring toFIG.9G, a doped semiconductor material having a doping of the second conductivity type can be deposited within each recessed region above the dielectric cores62. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material having a doping of the second conductivity type, a horizontally-extending portion of the semiconductor channel material layer60L, and a horizontally-extending potion of the memory film50can be removed from above the horizontal plane including the top surface of the topmost layer of the alternating stack (32,42), for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel material layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60. Each drain region63has a doping of the second conductivity type, and is located at a top end of the vertical semiconductor channel60that is located at an opposite side of a bottom end that contacts the source cap structure16.

Each contiguous combination of a memory film50and a vertical semiconductor channel60constitutes a memory stack structure55. The set of all material portions that fills a memory opening49constitutes a memory opening fill structure58. The set of all material portions that fills a support opening19constitutes a support pillar structure. Each memory opening fill structure58can be located in a memory opening49, and can comprise a memory film50, a vertical semiconductor channel60, a source cap structure16, a dielectric core62, and a drain region63.

In summary, a memory opening49vertically extends through the alternating stack (32,42) and through the source-side spacer layer14. Within each memory opening49, a memory film50is formed at a peripheral portion of the memory opening49, a source cap structure16is formed at a bottom portion of the inner sidewall of the memory film50, and a vertical semiconductor channel60is formed on a top surface of the source cap structure16and on an inner sidewall of the memory film50. In each memory opening fill structure58, the vertical semiconductor channel60comprises dopants of a first conductivity type at a first atomic concentration, and the source cap structure16comprises dopants of a second conductivity type that is an opposite of the first conductivity type at a second atomic concentration that is higher than the first atomic concentration.

Referring toFIGS.10A and10B, the first exemplary structure is illustrated after formation of memory opening fill structures58within the memory openings49and formation of the support pillar structures20in the support openings19. Each of the support pillar structures20may have a same set of materials as a memory opening fill structure58. Alternatively, the support pillar structures20may include only an insulating material, such as silicon oxide. In this alternative embodiment, the support openings19are filled with silicon oxide before or after forming the memory opening fill structures58.

Referring toFIGS.11A and11B, a dielectric material, such as undoped silicate glass (i.e., silicon oxide) or a doped silicate glass can be deposited over the alternating stack (32,42) to form a contact-level dielectric layer80. The thickness of the contact-level dielectric layer80may be in a range from 100 nm to 600 nm, such as from 200 nm to 400 nm, although lesser and greater thicknesses may also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer80, and can be lithographically patterned to form elongated openings that laterally extend along the first horizontal direction hd1between neighboring clusters of memory opening fill structures58. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer80, the alternating stack (32,42), and the stepped dielectric material portion65, and at least to a top surface of the carrier substrate9. Lateral isolation trenches79laterally extending along the first horizontal direction hd1can be formed through the alternating stack (32,42), the stepped dielectric material portion65, and the contact-level dielectric layer80. Each of the lateral isolation trenches79may comprise a respective pair of lengthwise sidewalls that are parallel to the first horizontal direction hd1and vertically extend from the carrier substrate9to the top surface of the contact-level dielectric layer80. A surface of the carrier substrate9can be physically exposed underneath each lateral isolation trench79. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIG.12, an etchant that selectively etches the material of the sacrificial material layers42with respect to the material of the insulating layers32, the source-side spacer layer14, and the carrier substrate9can be introduced into the lateral isolation trenches79, for example, employing an isotropic etch process. Lateral recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the sacrificial material layers42can be selective to the materials of the insulating layers32, the stepped dielectric material portion65, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the stepped dielectric material portion65can include silicon oxide.

Each lateral recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess43can be greater than the height of the lateral recess43. A plurality of lateral recesses43can be formed in the volumes from which the second material of the sacrificial material layers42is removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the lateral recesses43. The lateral recesses43comprise first lateral recesses143that are formed in volumes from which the first sacrificial material layers142are removed, and further comprise second lateral recesses243that are formed in volumes from which the second sacrificial material layers242are removed.

Each of the plurality of lateral recesses43can extend substantially parallel to the top surface of the carrier substrate9. A lateral recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each lateral recess43can have a uniform height throughout.

Referring toFIG.13, an outer blocking dielectric layer (not expressly illustrated inFIG.13) can be optionally formed. The outer blocking dielectric layer, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the lateral recesses43. In case the blocking dielectric layer52is present within each memory opening, the outer blocking dielectric layer is optional. In case the blocking dielectric layer52is omitted, the outer blocking dielectric layer is present.

At least one conductive material can be deposited in the lateral recesses43by providing at least one reactant gas into the lateral recesses43through the lateral isolation trenches79. A metallic barrier layer can be deposited in the lateral recesses43. The metallic barrier layer includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer can include a conductive metallic nitride material such as TiN, TaN, WN, MoN or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer can consist essentially of a conductive metal nitride such as TiN.

A metal fill material is deposited in the plurality of lateral recesses43, on the sidewalls of the at least one the lateral isolation trench79, and over the top surface of the contact-level dielectric layer80to form a metallic fill material layer. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating layers32and the memory stack structures55by the metallic barrier layer, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.

A plurality of electrically conductive layers46can be formed in the plurality of lateral recesses43, and a continuous metallic material layer can be formed on the sidewalls of each lateral isolation trench79and over the contact-level dielectric layer80. The electrically conductive layers46comprise first electrically conducive layers146that are formed in the volumes of the first lateral recesses143and replace the first sacrificial material layers142, and further comprise second electrically conductive layers246that are formed in the volumes of the second lateral recesses243and replace the second sacrificial material layers242. Each electrically conductive layer46includes a portion of the metallic barrier layer and a portion of the metallic fill material layer that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous metallic material layer includes a continuous portion of the metallic barrier layer and a continuous portion of the metallic fill material layer that are located in the lateral isolation trenches79or above the contact-level dielectric layer80.

The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each lateral isolation trench79and from above the contact-level dielectric layer80by performing an isotropic etch process that etches the at least one conductive material of the continuous electrically conductive material layer. Each remaining portion of the deposited metallic material in the lateral recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46. Generally, the electrically conductive layers46can be formed by providing a metallic precursor gas into the lateral isolation trenches79and into the lateral recesses43.

At least one uppermost electrically conductive layer46may comprise a respective drain-side select gate electrode. At least one bottommost electrically conductive layer46may comprise a respective source-side select gate electrode. The remaining electrically conductive layers46may comprise word lines. Each word line functions as a common control gate electrode for the plurality of vertical NAND strings (e.g., memory opening fill structures58).

Referring toFIGS.14A and14B, a dielectric fill material, such as silicon oxide can be deposited in the lateral isolation trenches79. Excess portions of the dielectric fill material can be removed from above the contact-level dielectric layer80. Each remaining portion of the dielectric fill material that fills a respective one of the lateral isolation trenches79constitutes a lateral isolation trench fill structure76, which may be a dielectric wall structure. In an alternative embodiment, an insulating spacer having a tubular configuration can be formed in peripheral portions of each of the lateral isolation trenches79, and a through-stack conductive via structure may be formed within a respective one of the insulating spacers. In this case, each lateral isolation trench fill structure76may comprise a combination of a through-stack conductive via structure and an insulating spacer that laterally surrounds the through-stack conductive via structure.

Contact via structures (88,86) can be formed through the contact-level dielectric layer80, and optionally through the stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact-level dielectric layer80on each drain region63. Layer contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer80, and through the stepped dielectric material portion65.

Referring toFIG.15, additional dielectric material layers and additional metal interconnect structures can be formed over the contact-level dielectric layer80. The additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and/or at least one additional line-and-via-level dielectric layer. The additional metal interconnect structures may comprise metal via structures, metal line structures, and/or integrated metal line-and-via structures. The additional dielectric material layers that are formed above the contact-level dielectric layer80are herein referred to as memory-side dielectric material layers960. The additional metal interconnect structures are collectively referred to as memory-side dielectric material layers960. The memory-side dielectric material layers960comprise a bit-line-level dielectric material layer embedding bit lines, which are a subset of the memory-side metal interconnect structures980.

Metal bonding pads, which are herein referred to as memory-side bonding pads988, may be formed at the topmost level of the memory-side dielectric material layers960. The memory-side bonding pads988may be electrically connected to the memory-side metal interconnect structures980and various nodes of the three-dimensional memory array including the electrically conductive layers46and the memory opening fill structures58. A memory die900can thus be provided.

The memory-side dielectric material layers960are formed over the alternating stacks (32,46). The memory-side metal interconnect structures980are embedded in the memory-side dielectric material layers960. The memory-side bonding pads988can be embedded within the memory-side dielectric material layers960, and specifically, within the topmost layer among the memory-side dielectric material layers960. The memory-side bonding pads988can be electrically connected to the memory-side metal interconnect structures980.

In one embodiment, the memory die900may comprise: a three-dimensional memory array comprising an alternating stack (32,46) of insulating layers32and electrically conductive layers46, a two-dimensional array of memory openings49vertically extending through the alternating stack (32,46), and a two-dimensional array of memory opening fill structures58located in the two-dimensional array of memory openings49and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel60; and a two-dimensional array of contact via structures (such as the drain contact via structures88) overlying the three-dimensional memory array and electrically connected to a respective one of the vertical semiconductor channels60.

Referring toFIG.16, a logic die700can be provided. The logic die700includes a logic-side substrate709, a peripheral circuit720located on the logic-side substrate709and comprising logic-side semiconductor devices (such as field effect transistors), logic-side metal interconnect structures780embedded within logic-side dielectric material layers760, and logic-side bonding pads778. The peripheral circuit720can be configured to control operation of the memory array within the memory die900. Specifically, the peripheral circuit720can be configured to drive various electrical components within the memory array including, but not limited to, the electrically conductive layers46, the drain regions63, and a source contact structure to be subsequently formed. The peripheral circuit720can be configured to control operation of the vertical stack of memory elements in the memory array in the memory die900.

Referring toFIG.17, the logic die700can be attached to the memory die900, for example, by bonding the logic-side bonding pads788to the memory-side bonding pads988at a bonding interface. The bonding between the memory die900and the logic die700may be performed employing a wafer-to-wafer bonding process in which a two-dimensional array of memory dies900is bonded to a two-dimensional array of logic dies700, by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads788within each logic die700can be bonded to the memory-side bonding pads988within a respective memory die900.

Referring toFIG.18, the carrier substrate9can be removed, for example, by grinding, polishing, cleaving, an isotropic etch process, and/or an anisotropic etch process. The backside stopper layer12may be employed as a stopping structure during a terminal processing step that is employed to remove the carrier substrate9. For example, if the carrier substrate9comprises silicon, the backside of the carrier substrate9can be thinned by performing at least one process step that removes a predominant portion of the carrier substrate9from the backside, and a terminal processing step that may include a wet etch process employing KOH, which can etch the silicon of a remaining portion of the carrier substrate9selective to the material of the backside stopper layer12(which may include a dielectric material, such as silicon oxide).

Referring toFIGS.19A and19B, the backside stopper layer12and end portions of the memory films50can be removed by performing a sequence of etch processes. The optional outer blocking dielectric layers44are expressly shown inFIG.19B.

In an illustrative example, a first etch process that etches the material of the backside stopper layer12can be performed. If the backside stopper layer12comprises silicon oxide, a wet etch process employing dilute hydrofluoric acid can be employed as the first etch process to remove the backside stopper layer12selective to the material of the source-side spacer layer14(which may comprise a semiconductor material, such as polysilicon). If the blocking dielectric layers52comprise silicon oxide, end portions of the blocking dielectric layers52that are proximal to the backside stopper layer12may be collaterally removed during the first etch process.

Subsequently, a second etch process can be performed to remove end portions of the memory material layers54selective to the material of the dielectric liner56and the source-side spacer layer14. If the memory material layers54comprise silicon nitride, a wet etch process employing hot phosphoric acid or a mixture of dilute hydrofluoric acid and ethylene glycol can be employed as the second etch process to remove end portions of the memory material layers54that are exposed to voids in the openings in the source-side spacer layer14.

Further, a third etch process can be performed to remove end portions of the dielectric liners56selective to the material of source cap structures16and the source-side spacer layer14. If the dielectric liners56comprise silicon oxide and/or silicon oxynitride, a wet etch process employing dilute hydrofluoric acid or another suitable etchant solution can be employed as the third etch process to remove end portions of the dielectric liners56that are exposed to voids in the openings in the source-side spacer layer14.

A first end surface segment ESS1of each source cap structure16can be physically exposed after the sequence of etch processes. Each source cap structure16may comprise a second end surface segment ESS2that contacts a convex end surface of a vertical semiconductor channel60. Each source cap structure16may comprise an annular conical surface segment ACSS which comprises a first tapered annular area ACSS1that is physically exposed to a void in a respective opening in the source-side spacer layer14, and a second tapered annular area ACSS2in contact with a memory film50.

Referring toFIGS.20A and20B, a source layer18can be formed by depositing at least one electrically conductive material within the voids of the openings in the source-side spacer layer14and on the physically exposed planar backside surface of the source-side spacer layer14. The source layer18may comprise a stack of an optional metallic barrier material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a high-electrical-conductivity metal material (such as Cu, Mo, W, Ti, Ta, Co, Ru, etc.).

If the support pillar structures comprise a semiconductor material, then a photoresist layer (not shown) can be applied over the source layer18and can be lithographically patterned to cover the areas of the memory opening fill structures58in the memory array region100without covering the areas of the support pillar structures20in the contact region300. Unmasked portions of the material of the source layer18can be removed by performing an etch process. The semiconductor material in the support pillar structures20can be electrically isolated from the source layer18. Alternatively, if the support pillar structures20only include an insulating material, then source layer18patterning step may be omitted or modified.

Referring toFIG.21, a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure illustrated inFIG.1by increasing the thickness of the backside stopper layer12. Specifically, the thickness of the backside stopper layer12can be selected to be greater than twice the thickness of a memory film50to be subsequently formed. For example, the thickness of the backside stopper layer12may be in a range from 30 nm to 300 nm, such as from 60 nm to 150 nm, although lesser and greater thicknesses may also be employed. The source-side spacer layer14can be formed on the top surface of the backside stopper layer12.

A photoresist layer (not shown) can be applied over the top surface of the source-side spacer layer14, and can be lithographically patterned to form an array of openings having a same pattern as the array of first-tier memory openings149illustrated inFIG.4. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the source-side spacer layer14and the backside stopper layer12. The carrier substrate9may be employed as a stopper structure for the anisotropic etch process. An array of discrete source-level openings349can be formed through the source-side spacer layer14and the backside stopper layer12. The discrete source-level openings349may have cylindrical sidewalls that vertically extend through the source-side spacer layer14and the backside stopper layer12.

Referring toFIG.22, an isotropic etch process, such as a wet etch process, may be performed, which etches the material of the backside stopper layer12selective to the materials of the source-side spacer layer14and the carrier substrate9. For example, if the source-side spacer layer14and the carrier substrate9comprise semiconductor materials, such as silicon, and if the backside stopper layer12comprises silicon oxide, a wet etch process employing dilute hydrofluoric acid can be performed to laterally recess the backside stopper layer12selective to the source-side spacer layer14and the backside stopper layer12.

The lateral etch distance of the isotropic etch process is less than one half of a nearest neighbor spacing among the discrete source-level openings349to prevent merging of the discrete source-level openings349. Further, the lateral etch distance of the isotropic etch process may be greater than the thickness of memory films50to be subsequently formed. In one embodiment, the lateral etch distance of the isotropic etch process may be in a range from 15 nm to 100 nm, such as from 30 nm to 60 nm, although lesser and greater thicknesses may also be employed. Each volume of a void formed by lateral recessing of the backside stopper layer12constitutes an annular recess cavity13. Generally, an annular recess cavity13can be formed around each discrete source-level opening349at the level of the backside stopper layer12.

Referring toFIG.23, a sacrificial fill material can be deposited in the discrete source-level openings349. The sacrificial fill material may comprise a carbon-based material (e.g., amorphous carbon, diamond-like carbon, or a doped carbon material), a high etch-rate dielectric material (e.g., borosilicate glass or organosilicate glass), or a polymer material. Excess portions of the sacrificial fill material can be removed from above a horizontal plane including the top surface of the source-side spacer layer14, for example, by a recess etch process. Each remaining portion of the sacrificial fill material filling a respective discrete source-level opening349constitutes a sacrificial pedestal structure348. Each sacrificial pedestal structure348may comprise an upper cylindrical portion located at the level of the source-side spacer layer14and a lower cylindrical portion located at the level of the backside stopper layer12. A two-dimensional array of sacrificial pedestal structures348can be formed.

Referring toFIG.24, the processing steps described with reference toFIGS.2and3can be performed to form a first-tier alternating stack (132,142) of first insulating layers132and first sacrificial material layers142, first stepped surfaces, and a first stepped dielectric material portion165.

Referring toFIG.25, the processing steps described with reference toFIG.4can be performed with a modification in the anisotropic etch process to form first-tier memory openings149and first-tier support openings119. Specifically, the anisotropic etch process can be modified to etch through unmasked portions of the first-tier alternating stack (132,142) without etching the materials of the source-side spacer layer14or the sacrificial pedestal structures348.

Referring toFIG.26, the processing steps described with reference toFIG.5can be performed to form sacrificial memory opening fill structures148in the first-tier memory openings149and to form sacrificial support opening fill structures118in the first-tier support openings119.

Referring toFIG.27, the processing steps described with reference toFIG.6can be performed to form a second-tier alternating stack (232,242) of second insulating layers232and second spacer material layers (such as second sacrificial material layers242), second stepped surfaces, and a second stepped dielectric material portion265.

Referring toFIG.28, the processing steps described with reference toFIG.7can be performed to form second-tier memory openings249through the second-tier alternating stack (232,242) directly on a top surface of a respective sacrificial memory opening fill structure148, and to form second-tier support openings219through the second stepped dielectric material portion165and the second-tier alternating stack (232,242) directly on a top surface of a respective sacrificial support opening fill structure118.

Referring toFIG.29A, a masking layer (not shown) may be formed over the second-tier memory openings249. The sacrificial support opening fill structures118, may be removed selective to the materials of the second-tier alternating stack (232,242), the first-tier alternating stack (132,142), the stepped dielectric material portion65, the source-side spacer layer14, the backside stopper layer12, and the carrier substrate9. In an illustrative example, if the sacrificial support opening fill structures118, comprise a carbon-based material, an ashing process may be performed to remove the sacrificial support opening fill structures118. Inter-tier support openings19(which are also referred to as support openings19) can be formed through the stepped dielectric material portion65, at least through the first-tier alternating stack (132,142), and optionally through the second-tier alternating stack (232,242).

The support openings19are then filled with an insulating material, such as silicon oxide. The insulating material is then planarized to leave dielectric support pillar structures20filling the support openings. The dielectric support structures20consist of an insulating material, such as silicon oxide. The masking layer is then removed by selective etching.

Referring toFIG.29B, the sacrificial memory opening fill structures148and the sacrificial pedestal structures348may be removed selective to the materials of the support pillar structures20, the second-tier alternating stack (232,242), the first-tier alternating stack (132,142), the stepped dielectric material portion65, the source-side spacer layer14, the backside stopper layer12, and the carrier substrate9. In an illustrative example, if the sacrificial memory opening fill structures148and the sacrificial pedestal structures348comprise a carbon-based material, an ashing process may be performed to remove the sacrificial memory opening fill structures148and the sacrificial pedestal structures348. Inter-tier memory openings49(which are also referred to as memory openings49) can be formed through the second-tier alternating stack (232,242), the first-tier alternating stack (132,142), the source-side spacer layer14, and the backside stopper layer12.

FIGS.30A-30Gare sequential vertical cross-sectional views of a memory opening49during formation of a memory opening fill structure58in the second exemplary structure according to the second embodiment of the present disclosure.

Referring toFIG.30A, a memory opening49in the second exemplary structure is illustrated, which comprises the annular recess cavity13located at the level of the backside stopper layer12. The annular recess cavity13is formed around each memory opening49at the level of the backside stopper layer12by removal of the sacrificial pedestal structure348.

Referring toFIG.30B, the processing steps described with reference toFIG.9Bcan be performed to form a memory film50within at peripheral portions of the memory openings49, and over the topmost surface of the alternating stack {(132,142), (232,242)}.

Referring toFIG.30C, the processing steps described with reference toFIG.9Ccan be performed to form a conformal doped semiconductor layer16L including a doped semiconductor fill material. The doped semiconductor fill material has a doping of a second conductivity type, which is the opposite of the first conductivity type of vertical semiconductor channels to be subsequently formed. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of dopants of the second conductivity type in the doped semiconductor fill material may be in a range form 1.0×1014/cm3to 1.0×1021/cm3, such as from 1.0×1016/cm3to 1.0×1020/cm3, although lesser and greater atomic concentrations may also be employed. The thickness of the conformal doped semiconductor layer16L may be less than one half of the diameter of each memory opening49, and may be greater than one half of the difference between the thickness of the backside stopper layer12and twice the thickness of the memory film50. The entire volume of each annular recess cavity13may be filled with materials of the memory film50and the conformal doped semiconductor layer16L. A cylindrical cavity may be present within each memory opening49.

Referring toFIG.30D, an etch back process can be performed to remove portions of the conformal doped semiconductor layer16L outside the annular recess cavities13, such as portions which overlie the horizontal plane including the top surface of the backside stopper layer12or are not masked by the combination of the alternating stack {(132,142), (232,242)} and vertically-extending portions of the memory film50that are laterally surrounded by the alternating stack {(132,142), (232,242)}. Each remaining portion of the conformal doped semiconductor layer16L having a respective annular shape and underlies the source-side spacer layer14constitutes an annular semiconductor ring116. Each annular semiconductor ring116may be formed inside a respective annular recess cavity13defined by a respective portion of the memory film50that underlies the source-side spacer layer14. Each annular semiconductor ring116may have an inner cylindrical surface that is vertically coincident with an inner cylindrical sidewall of a vertically-extending portion of the memory film50.

Referring toFIG.30E, a selective semiconductor deposition process can be performed to grow a doped semiconductor material having a doping of the second conductivity type from physically exposed cylindrical surfaces of the annular semiconductor rings116while suppressing growth of the doped semiconductor material from physically exposed dielectric surfaces such as the physically exposed surfaces of the memory film50, i.e., from the physically exposed surfaces of the dielectric liner56(which may be a tunneling dielectric layer). A selective deposition process refers to a deposition process in which a material is grown from a first-type surface while deposition of the material from a second-type surface is suppressed. A selective semiconductor deposition process refers to a deposition process in which a semiconductor material is grown from a first-type surface such as a physically exposed semiconductor surface while deposition of the semiconductor material from a second-type surface such as an insulating surface is suppressed.

The selective semiconductor deposition process forms the source cap structure16on an inner sidewall of each annular semiconductor ring116. The duration of the selective semiconductor deposition process can be selected such that growth surfaces of the semiconductor material of the source cap structure16merge at a center portion to form a center seam CS. In one embodiment, the vertical extent of each center seam CS may be greater than the height of each annular semiconductor ring116.

According to an aspect of the present disclosure, the selective semiconductor deposition process may be performed with in-situ doping with dopants of the second conductivity type. The atomic concentration of dopants of the second conductivity type in the source cap structures16may be in a range from 5.0×1018/cm3to 2.0×1021/cm3, such as from 1.0×1020/cm3to 1.0×1021/cm3, although lesser and greater atomic concentrations may also be employed. In an illustrative example, if the vertical semiconductor channels to be subsequently formed are doped with p-type dopants (such as boron), the source cap structures16are doped with n-type dopants (such as phosphorus). The source cap structures16form p-n junctions with respect to vertical semiconductor channels to be subsequently formed, and thus, function as components of source structures. Control of the duration of the selective semiconductor deposition process allows control of the location of the top surfaces of the source cap structures16, and thus, allows control of the height of the p-n junctions to be subsequently formed.

In one embodiment, each source cap structure16may comprise a center seam CS that vertically extends from a center of a top surface thereof to a center of a bottom surface thereof. In one embodiment, each source cap structure16comprises a contoured top surface having a periphery that is raised above a center point of the contoured top surface. In one embodiment, the contoured top surface of each source cap structure16comprises convex surface, while the bottom surface of each source cap structure16is flat. In one embodiment, the geometrical center GC of each source cap structure16can be located at a point within a center seam CS of the source cap structure16. As used herein, a geometrical center of an object is the location of the center of gravity of a hypothetical object that occupies the same volume as the object and having a uniform density throughout.

Each source cap structure16may comprise a cylindrical surface segment CSS that continuously extends from a first end surface segment ESS1contacting a top surface of a horizontally-extending portion of the memory film50to a second end surface segment ESS2that is physically exposed to a cavity located within a respective memory opening49. In one embodiment, a first (i.e., lower) cylindrical area of the cylindrical surface segment CSS of each source cap structure16may contact a respective annular semiconductor ring116. A second (i.e., upper) cylindrical area of the cylindrical surface segment CSS of each source cap structure16may contact a cylindrical surface segment of an inner sidewall of the memory film50.

The first end surface segment ESS1is adjoined to a first periphery of the cylindrical surface segment CSS. The second end surface segment ESS2is adjoined to a second periphery of the cylindrical surface segment CSS. In one embodiment, the second end surface segment ESS2comprises a convex surface segment having a lowest point that is adjoined to a topmost point of the central seam CS. In one embodiment, each source cap structure16has a variable thickness that varies along a radial direction from a vertical axis passing through the geometrical center GC of the source cap structure16. In one embodiment, each source cap structure16comprises a central seam CS that vertically extends from the first end surface segment ESS1to a second end surface segment ESS2that is adjoined to a second periphery of the cylindrical surface segment.

Referring toFIG.30F, a semiconductor channel material layer60L can be deposited on the memory film50and each of the source cap structures16by performing a conformal deposition process. In one embodiment, the semiconductor channel material layer60L may be doped with dopants of the first conductivity type, which is the opposite of the second conductivity type. The atomic concentration of dopants of the first conductivity type in the semiconductor channel material layer60L may be in a range from 1.0×1012/cm3to 3.0×1017/cm3, such as from 1.0×1014/cm3to 3.0×1016/cm3, although lesser and greater atomic concentrations may also be employed. The thickness of the semiconductor channel material layer60L may be in a range from 3 nm to 60 nm, such as from 6 nm to 30 nm, although lesser and greater thicknesses may also be employed. In one embodiment, each portion of the semiconductor channel material layer60L located within a respective memory opening49may comprise a contoured bottom surface which is a concave surface that contacts the convex surface of the source cap structure16. A p-n junction can be formed at each interface between the semiconductor channel material layer60L and each of the source cap structures16.

A dielectric core layer comprising a dielectric fill material, such as silicon oxide, can be deposited in remaining volumes of the memory openings49. The dielectric core layer can be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at, or about, the horizontal plane including the bottom surface of a topmost insulating layers32. Each remaining portion of the dielectric core layer constitutes a dielectric core62.

Referring toFIG.30G, a doped semiconductor material having a doping of the second conductivity type can be deposited within each recessed region above the dielectric cores62. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material having a doping of the second conductivity type, a horizontally-extending portion of the semiconductor channel material layer60L, and a horizontally-extending potion of the memory film50can be removed from above the horizontal plane including the top surface of the topmost layer of the alternating stack (32,42), for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel material layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60.

Each contiguous combination of a memory film50and a vertical semiconductor channel60constitutes a memory stack structure55. The set of all material portions that fills a contiguous combination of a memory opening49constitutes a memory opening fill structure58. Each memory opening fill structure58can be located in a memory opening49, and can comprise an annular semiconductor ring116, a source cap structure16, a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63. In one embodiment, each source cap structure16comprises a second end surface segment ESS2having a convex surface segment that contacts a concave surface segment of a vertical semiconductor channel60.

Referring toFIGS.31A and31B, the second exemplary structure is illustrated after formation of memory opening fill structures58within the memory openings49and formation of the support pillar structures20in the support openings19. Each of the support pillar structures20may comprise a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63. The support pillar structures20may be free of any semiconductor material having a doping of the second conductivity type and may consist essentially of an insulating material.

Referring toFIGS.32A and32B, a dielectric material, such as undoped silicate glass (i.e., silicon oxide) or a doped silicate glass can be deposited over the alternating stack (32,42) to form a contact-level dielectric layer80. The thickness of the contact-level dielectric layer80may be in a range from 100 nm to 600 nm, such as from 200 nm to 400 nm, although lesser and greater thicknesses may also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer80, and can be lithographically patterned to form elongated openings that laterally extend along the first horizontal direction hd1between neighboring clusters of memory opening fill structures58. An anisotropic etch process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer80, the alternating stack (32,42), and the stepped dielectric material portion65, and at least to a top surface of the carrier substrate9. Lateral isolation trenches79laterally extending along the first horizontal direction hd1can be formed through the alternating stack (32,42), the stepped dielectric material portion65, and the contact-level dielectric layer80. Each of the lateral isolation trenches79may comprise a respective pair of lengthwise sidewalls that are parallel to the first horizontal direction hd1and vertically extend from the carrier substrate9to the top surface of the contact-level dielectric layer80. A surface of the carrier substrate9can be physically exposed underneath each lateral isolation trench79. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIG.33, the step described above with respect toFIG.12is performed to form the lateral recesses43. Specifically, an etchant that selectively etches the material of the sacrificial material layers42with respect to the material of the insulating layers32, the source-side spacer layer14, and the carrier substrate9can be introduced into the lateral isolation trenches79, for example, employing an isotropic etch process. Lateral recesses43are formed in volumes from which the sacrificial material layers42are removed.

Referring toFIG.34, an outer blocking dielectric layer (not expressly illustrated inFIG.34) can be optionally formed, as described above with respect toFIG.13. The electrically conductive layers46are then formed in the lateral recesses43, as described above with respect toFIG.13. At least one uppermost electrically conductive layer46may comprise a respective drain-side select gate electrode. At least one bottommost electrically conductive layer46may comprise a respective source-side select gate electrode. The remaining electrically conductive layers46may comprise word lines. Each word line functions as a common control gate electrode for the plurality of vertical NAND strings (e.g., memory opening fill structures58).

Referring toFIGS.35A and35B, the steps described above with respect toFIGS.14A and14Bare performed to form the lateral isolation trench fill structure76in the lateral isolation trenches79and to form the contact via structures (88,86).

Referring toFIG.36, the steps described above with respect toFIG.15are performed to form the memory-side dielectric material layers960, memory-side metal interconnect structures980and the memory-side bonding pads988,

Referring toFIG.37, the logic die700can be attached to the memory die900, for example, by bonding the logic-side bonding pads788to the memory-side bonding pads988at a bonding interface, as described with reference toFIG.17. The logic die700in the second exemplary structure may be the same as the logic die700described with reference toFIG.16.

Referring toFIG.38, the carrier substrate9can be removed, for example, by grinding, polishing, cleaving, an isotropic etch process, and/or an anisotropic etch process, as described above with reference toFIG.18.

Referring toFIGS.39A and39B, the backside stopper layer12and end portions of the memory films50can be removed by performing a sequence of etch processes, as described above with respect toFIGS.19A and19B.

In an illustrative example, a first etch process that etches the material of the backside stopper layer12can be performed. If the backside stopper layer12comprises silicon oxide, a wet etch process employing dilute hydrofluoric acid can be employed as the first etch process to remove the backside stopper layer12selective to the material of the source-side spacer layer14(which may comprise a semiconductor material such as polysilicon) and selective to the material of the memory material layer54. If the blocking dielectric layers52comprise silicon oxide, portions of the blocking dielectric layers52that are not masked by the annular semiconductor rings116may be collaterally removed during the first etch process.

Subsequently, a second etch process can be performed to remove portions of the memory material layers54that are not masked by the annular semiconductor rings116selective to the material of the dielectric liner56and the source-side spacer layer14. If the memory material layers54comprise silicon nitride, a wet etch process employing hot phosphoric acid or a mixture of dilute hydrofluoric acid and ethylene glycol can be employed as the second etch process to remove end portions of the memory material layers54that are exposed to voids in the openings in the source-side spacer layer14.

Further, a third etch process can be performed to remove portions of the dielectric liners56that are not masked by the annular semiconductor rings116selective to the material of the annular semiconductor rings116, the source cap structures16, and the source-side spacer layer14. If the dielectric liners56comprise silicon oxide and/or silicon oxynitride, a wet etch process employing dilute hydrofluoric acid or another suitable etchant solution can be employed as the third etch process to remove end portions of the dielectric liners56that are not masked by the annular semiconductor rings116.

A first end surface segment ESS1of each source cap structure16can be physically exposed after the sequence of etch processes. Each source cap structure16may comprise a first end surface segment ESS1that is physically exposed. Each annular semiconductor ring116may comprise a respective annular surface and a respective cylindrical surface that are exposed. Each memory film50in a memory opening fill structure58may comprise a respective annular portion that is interposed between the source-side spacer layer14and the annular semiconductor ring116. Generally, the first end surface segment ESS1of each source cap structure16, an edge portion of each memory film50, and a backside surface of the source-side spacer layer14can be physically exposed upon removal of the backside stopper layer12and end portions of the memory films50.

Referring toFIGS.40A and40B, a source layer18can be formed by depositing at least one metallic material on the physically exposed planar backside surface of the source-side spacer layer14and on the physically exposed surfaces of the annular semiconductor rings116and the source cap structure16. The source layer18may comprise a stack of an optional metallic barrier material (such as TIN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a high-electrical-conductivity metal material (such as Cu, Mo, W, Ti, Ta, Co, Ru, etc.). The source layer18can be formed on a bottom surface of the source-side spacer layer14and on exposed cylindrical sidewalls of remaining portions of the memory films50after removal of the physically exposed portion of the memory film50. The source layer18contacts the first end surface segment ESS1of each source cap structure16and the annular semiconductor ring116.

In one embodiment, the entirety of the second end surface segment ESS2of each source cap structure16may be located between a first horizontal plane HP1including a first horizontal surface (such as a top surface) of the source-side spacer layer14and a second horizontal plane HP2including a second horizontal surface (such as a bottom surface) of the source-side spacer layer14. Generally, the location of the p-n junction between a source cap structure16and a vertical semiconductor channel60may be adjusted as need.FIG.40Cillustrates a configuration in which at least a portion of the second end surface segment ESS2of each source cap structure16is more distal from the horizontal plane (such as the second horizontal plane HP2) including an interface between the source-side spacer layer14and the source layer18than the alternating stack {(132,146), (232,246)} is from the horizontal plane.FIG.40Dillustrates a configuration in which the second end surface segment ESS2of each source cap structure16is more proximal to the horizontal plane (such as the second horizontal plane HP2) including an interface between the source-side spacer layer14and the source layer18than in the configuration illustrated inFIG.40B.

The embodiments of the present disclosure include a semiconductor structure which comprises: an alternating stack {(132,146), (232,246)} of insulating layers (132,232) and electrically conductive layers (146,246); a memory opening49vertically extending through the alternating stack {(132,146), (232,246)}; a memory opening fill structure58located in the memory opening49and comprising a memory film50, a vertical semiconductor channel60, and a semiconductor source cap structure16which is at least partially laterally surrounded by the memory film50and which contacts the vertical semiconductor channel60, and a source layer18contacting at least a first end surface segment ESS1of the source cap structure16.

In some embodiments, the semiconductor structure further comprises a source-side spacer layer14located between the source layer18and the alternating stack {(132,146), (232,246)}. The memory opening49also vertically extends through the source-side spacer layer14; and the semiconductor source cap structure16is laterally surrounded by the source-side spacer layer14. The vertical semiconductor channel60has a doping of a first conductivity type; The source-side spacer layer14comprises a semiconductor material layer; the semiconductor source cap structure16comprises a semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type; a first end of the vertical semiconductor channel60contacts the semiconductor source cap structure16; and the memory opening fill structure58further comprises a drain region63having a doping of the second conductivity type and contacting a second end of the vertical semiconductor channel60opposite to the first end.

In the first embodiment, the semiconductor source cap structure16further comprises an annular conical surface segment ACSS adjoined to the first end surface segment ESS1; and the annular conical surface segment ACSS is laterally surrounded by the memory film50and by the source-side spacer layer14.

In the first embodiment, the annular conical surface segment ACSS comprises: a first tapered annular area in contact with the source layer18; and a second tapered annular area in contact with the memory film50. In the first embodiment, the semiconductor source cap structure16comprises a second end surface segment ESS2that contacts a convex end surface of the vertical semiconductor channel60. In the first embodiment, the second end surface segment ESS2comprises a convex surface segment located entirely between a first horizontal plane HP1including a first horizontal surface of the source-side spacer layer14and a second horizontal plane HP2including a second horizontal surface of the source-side spacer layer14.

In the first embodiment, the source-side spacer layer14comprises an opening having a tapered conical sidewall TCS; and the tapered conical sidewall TCS comprises a first tapered conical surface segment that contacts a conical surface segment of the source layer18. In the first embodiment, a lateral extent of the opening in the source-side spacer layer14increases with a vertical distance from a horizontal plane including an interface between the source-side spacer layer14and the source layer18toward the alternating stack {(132,146), (232,246)}. In the first embodiment, the tapered conical sidewall TCS comprises a second tapered conical surface segment that contacts a conical surface segment of an outer sidewall of the memory film50.

In the second embodiment, the semiconductor source cap structure16further comprises a cylindrical surface segment CSS. The first end surface segment ESS1is adjoined to a first periphery of the cylindrical surface segment CSS.

In the second embodiment, the semiconductor structure further comprises an annular semiconductor ring116having an inner cylindrical surface that contacts a first cylindrical area of the cylindrical surface segment of the semiconductor source cap structure16. In the second embodiment, a second cylindrical area of the cylindrical surface segment of the source cap structure16contacts a cylindrical surface segment of an inner sidewall of the memory film50. In the second embodiment, the memory film50comprises an annular plate portion that is interposed between the source-side spacer layer14and the annular semiconductor ring116.

In the second embodiment, the semiconductor source cap structure16further comprises second end surface segment ESS2that is adjoined to a second periphery of the cylindrical surface segment; and the second end surface segment ESS2comprises a convex surface segment that contacts a concave surface segment of the vertical semiconductor channel60. In the second embodiment, the semiconductor source cap structure16has a variable thickness that varies along a radial direction from a vertical axis passing through a geometrical center GC of the semiconductor source cap structure16; and the semiconductor source cap structure16comprises a central seam CS that vertically extends from the first end surface segment ESS1to a second end surface segment ESS2that is adjoined to a second periphery of the cylindrical surface segment.

The various embodiments of the present disclosure may be employed to provide a high quality Ohmic electrical contact between a source layer18and source cap structure16. Further, the various embodiments of the present disclosure may be employed to provide enhanced control over locations of p-n junctions by adjusting locations of a second end surface segment ESS2of each source cap structure16relative to that of the vertical semiconductor channel60.

Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Whenever two or more elements are listed as alternatives in a same paragraph of in different paragraphs, a Markush group including a listing of the two or more elements is also impliedly disclosed. Whenever the auxiliary verb “can” is employed in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device can provide an equivalent result. As such, the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. If publications, patent applications, and/or patents are cited herein, each of such documents is incorporated herein by reference in their entirety.