Power and area efficient receiver equalization architecture with relaxed DFE timing constraint

An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

TECHNICAL FIELD

Embodiments of the present invention relate generally to methods and apparatuses for receiving data. More particularly, embodiments of the invention relate to receiving data and determining values of the received data at a power and area efficient receiver equalizer with relaxed Decision Feedback Equalizer (DFE) timing constraint.

BACKGROUND ART

In serial data communication, the channel through which information is transmitted (e.g., chip-to-chip or backplane interconnects,) imposes a limit on the bandwidth capacity, or rate at which information may pass through the channel. One significant limitation on achievable bandwidth is known as inter-symbol interference (ISI), which occurs when a portion of a signal representative of one bit of information interferes with a different portion of the signal representative of a different bit of information.

To overcome bandwidth limited chip-to-chip and backplane interconnects at high data rates, conventional high-speed transceivers implement a combination of a Decision Feedback Equalizer (DFE) on the Receiver (RX) side as well as a Feed Forward Equalization (FFE) on the Transmitter (TX) side. Although RX DFE has advantages such as not amplifying noise, it has a very strict timing constraint of one unit interval (UI) for the feedback path. Given the current transceiver data rates, one UI can be as small as 35.7 pico seconds (ps), which is very difficult to meet, even for cutting edge manufacturing processes.

For example,FIG. 1Aillustrates a conventional architecture of a quarter-rate equalizer100comprising DFE samplers031-034for sampling/determining the value of an incoming signal based on the current integration performed by main taps011-014and DFE taps021-024. The DFE taps021-024are constrained to integrate the current of signals from various DFE samplers031-034within one UI from when the sampler inputs become available.

A few techniques have been adopted in the industry to mitigate this timing constraint. For example, time-interleaving techniques such as half-rate or quarter-rate architecture can relax the DFE timing constraint for the second DFE tap and onward, but the DFE first tap timing constraint remains at one UI. Although loop unrolling can eliminate the analog settling time from the one UI timing constraint, loop unrolling adds incurs additional hardware resources, and also results in more power dissipation.

Recent transceiver designs use FFE in the TX side to equalize part of the channel losses. There are several drawbacks of putting FFE on the TX side. The first significant impact is related to the limit on the amplitude of the transmitted signal on the TX side. This limitation on the amplitude implies that, when equalization is used, the total energy sent from the TX to the far end receiver (RX) is reduced.

Conventional architectures implement back-channel communication between the RX and TX as a way to tune the TX FFE coefficients following the RX requests. Back-channel communication costs extra hardware. Additionally, it can be difficult to find a combined optimal solution for FFE and DFE, given a long feedback latency of the back-channel, as well as the limited resolution of the far-end TX. Moreover, after channel attenuation and reflection, TX FFE becomes less effective as compared to directly applying FFE in the far end RX. Given these and other disadvantages, putting FFE on the RX side is becoming more popular.

The impact of pre-cursor ISI on receiver performance becomes significant for interconnects operating at 10 Gbps and above. The higher the link speed, the higher the potential impact of the pre cursor ISI on the recovered eye diagram. An eye diagram is generated by superimposing a stream of pulses of “0's” and “1's.” Ideally, an eye diagram has a rectangular shape because the “0's” and “1's” pulses have perfect edges (i.e., zero rise and fall time). Due to ISI, the received pulses become imperfect, and the resulting diagram looks more like an “eye.” As ISI increases, the eye diagram looks more and more like a closed/narrower eye. Received signals having a closed-eye characteristic are less effective in driving the FFE filter, resulting in an equalizer having little benefit.

Unlike DFE, which can only equalize post cursors of impulse response, FFE is able to equalize pre cursors as well. Conventional architectures of RX FFE require analog elements (such as inductors and capacitors) in order to create a one UI distance between taps. These analog elements typically occupy a large area and are difficult to integrate into a System-on-Chip (SOC). Furthermore, at very high speeds, the insertion loss is significant, leading to a closed eye diagram at the receiver pads even, after a Continuous Time Linear Equalizer (CTLE) has been applied to the input signal.

More recently, some equalizers implement FFE filters by feed forwarding the input signal held at the SNH directly to the current integration logic. Such conventional architectures also result in a closed eye at the receiver at high data rates because the insertion loss is significant at high speeds. For example, the quarter-rate equalizer101ofFIG. 1Bconsists of pre/post cursor taps131-134for integrating the current of the outputs of sample and hold (SNH)121-124. As used herein, current integration refers to the process of summing/adding current onto a capacitive load. As illustrated, SNH121-124outputs are based on un-equalized outputs of SNH101-104. Thus, the performance of pre/post cursor taps131-134is reduced because they integrate based on un-equalized signals, resulting in a closed eye at the receiver at high data rates.

DETAILED DESCRIPTION

In accordance with an embodiment of the present invention, an input signal is received by a receiver. In order to recover the signal, i.e., compensate for channel impairments, the signal is processed by an equalizer. In one embodiment, the equalizer includes four (4) branches. The four branches enable the equalizer to process the signal in a time-interleaving manner, thus, allowing the equalizer to operate at one-quarter of the data rate. Each branch includes a current integration summer (summer), for integrating the current corresponding to the input signal onto load capacitances. In order to optimize and improve performance of the equalizer, various FFE taps are fed with a signal that has been fully equalized, which makes FFE taps behave very similarly to DFE taps, resulting in a more accurate integration, and thus a more accurate determination of whether the incoming signal is a “0” or “1.” In one embodiment, post cursor tap1, post cursor tap2and pre cursor tap1are implemented by FFE, eliminating the one UI timing constraint in conventional DFE implementation. The clocking structure of the branches are designed such that the DFE timing constraint for DFE tap3and up is relaxed to at least two UIs.

Throughout the description, a receiver equalization architecture is described based on the conventional quarter rate with current integration summer. However, it will be appreciated that the equalizer of the present invention is not so limited, and the techniques described herein are equally applicable to other architectures, e.g., 1/16th, ⅛th, half-rate, full-rate, etc.

Throughout the description, references are made to the figures, in which like numerals represent the same or similar elements. The figures and description of the present specification reference pairs of signals that are identical except for their polarities. Polarities are identified by a “p” or “n” identifier. For example, Vin_p is the same signal as Vin_n, except that Vin_p has the positive polarity while Vin_n has the negative polarity. At times, the description and Figures may refer to such signals without the added identifier. In such instances, it will be understood that the reference is made with respect both polarities collectively. Thus, for example, a reference to Vin shall mean that both Vin_p and Vin_n are being referred to.

FIG. 2is a block diagram illustrating an embodiment of a high-speed communications system200. System200includes a transmitter205for transmitting differentially encoded signals Vin_p220and Vin_n221, which may be collectively referred to as Vin, over a communication channel. System200further includes receiver210for receiving Vin from transmitter205. Receiver210includes equalizer215. In one embodiment, equalizer215includes four branches (illustrated as branch0,90,180, and270) that time-interleave the processing of incoming Vin signal. Alternatively, equalizer215may include more or less than four branches. As used herein, time-interleaving refers to each of the branches processing one bit (e.g., determine the value of an incoming Vin signal,) while the other branches process the subsequent bits represented by Vin during the subsequent intervals. By way of example, a stream of four bits may be represented by Vin arriving at receiver210in the order {1, 0, 1, 1}. Depending on the current phase of the clocks, branch0of equalizer215may process the first bit (“1”), branch90processes the second bit (“0”), branch180processes the third bit (“1”), and branch270processes the fourth bit (“1”). By time-interleaving, equalizer215is able to process the incoming signals at a lower clock frequency than the data rate (e.g., a quarter of the data rate when the receiver includes four branches).

FIGS. 3A-3Dillustrate one embodiment of equalizer215.FIG. 3Aillustrates branch0of equalizer215having current integration summer320receiving input clocks snhclk0_p, snhclk0_n, snhclk90_p, snhclk90_n, snhclk180_p, snhclk180_n, snhclk270_p, and snhclk270_n (collectively illustrated as “snhclk0/90/180/270_p/n”). Branch0further includes DFE sampler304clocked by sampler_clk0_p, and DFE samplers308and312, both clocked by sampler_clk0_n. In one embodiment, the clocks have frequencies and duty cycles relative to each other as illustrated inFIG. 4. For example, snhclk90_p rises as snhclk0_p falls; shnclk180_p rises as snhclk90_p falls; snhclk270_p rises snhclk180_p falls; and snhclk0_p rises snhclk270_p falls. It should also be noted that snhclk0_n, snhclk90_n, snhclk180_n, and snhclk270_n have similar timing relationship, except that they have opposite polarities to snhclk0_p, snhclk90_p, snhclk180_p, and snhclk270_p, respectively. It should also be further noted that sampler_clk0_p, sampler_clk90_p, sampler_clk180_p, and sampler_clk270_p have the same frequency as clocks snhclk0_p, snhclk90_p, snhclk180_p, and snhclk270_p, respectively; the difference between these clocks lies in their duty cycles (e.g., “snhclk” clocks have 25% duty cycles while “sampler_clk” clocks have 50% duty cycles). Additionally, it should be noted that sampler_clk0_n, sampler_clk90_n, sampler_clk180_n, and sampler_clk270_n have the same frequency as sampler_clk0_p, sampler_clk90_p, sampler_clk180_p, and sampler_clk270_p, except that they have opposite polarities. For example, sampler_clk0_p has the opposite polarity as sampler_clk0_n. Throughout the description, references are made to “UI” (Unit interval between two adjacent incoming bits). In one embodiment, an UI is the time period when one of the “snhclk” clocks (e.g., snhclk0_p, snhclk90_p, etc.) is HIGH.

In one embodiment, summer320includes current integration taps, such as those shown inFIG. 5, for integrating the current corresponding to Vin_p and Vin_n onto load capacitances C1and C2, respectively. For example, when a “1” is received, load capacitance C1will be charged to a higher voltage than the voltage in load capacitance C2during each of the integration periods. On the other hand, if an input “0” is received, load capacitance C2will be charged to higher voltage than the voltage in load capacitance C1during each of the integration periods. In one embodiment, the input signals Vin_p/n have been equalized by a continuous time linear equalizer (CTLE), not shown inFIG. 3A. Summer320integrates the current corresponding to signals that have been FFE and/or DFE equalized by another branch (e.g., out_p/n90of branch90, out_p/n180of branch180, and out_p/n270of branch270).

As illustrated inFIG. 3A, summer320includes differential output nodes out_p0and out_n0communicatively coupled to load capacitances C1and C2, respectively. These differential nodes out_p/n0are fully equalized by summer320by the time they are used by another branch. As used herein, “fully equalized” refers to all taps within a summer having completed their current integration process. Output nodes out_p/n0are received by DFE sampler304, which makes a determination of whether Vinis a “0” or a “1” based on the difference between the voltages of equalized signals out_p0and out_n0. For example, if the difference between out_p0and out_n0is positive, DFE sampler304determines that the incoming signal is a “1,” and drives a “1” to its output node D-4. On the other hand, if the difference results in a negative value, DFE sampler304determines that the incoming signal is a “0” and drives a “0” to its output node D-4. Branch0further includes DFE sampler308which drives its output D-8based on the received D-4value. In one embodiment, branch0also includes DFE sampler312for driving its output node D-12based on received D-8signal. According to one embodiment, DFE samplers304may be implemented as Sense-Amplifier Flip-Flop (SAFF),308, and312may be implemented as conventional flip-flops, which are clocked by sampler_clk0_p, sampler_clk0_n, and sampler_clk0_n, respectively. For example, DFE sampler304may be clocked by sampler_clk0_p, and DFE sampler308and312may be clocked by sampler_clk0_n.

According to one embodiment, the integration (i.e., summation) of current onto load capacitances C1and C2is accomplished in stages, each stage corresponding to one UI, i.e., a period of time when one of input clocks snhclk0/90/180/270_p is HIGH. Conventional equalizers implement FFE filters by feed forwarding the input signal Vin held at the sample and hold (“SNH”) directly to the current integration logic. Such conventional architectures result in a closed eye at the receiver at high data rates because the insertion loss is quite significant at high speeds. Unlike conventional equalizers, summer320implements an FFE filter that compensates for ISI by integrating signals that have been equalized, resulting in wider eye openings as compared to architectures which utilize signals directly from the SNH. For example, summer320performs integration of signals that have been equalized by the various DFE and FFE taps of the branches. Details of which FFE and DFE equalized signals are integrated during a particular UI shall become apparent through the discussion below.

FIGS. 3B-3Dare block diagrams illustrating one embodiment of branch90,180, and270of equalizer215, respectively. These three branches implement current integration summer and DFE sampler logic similar to those described herein with respect toFIG. 3A. Examples of which taps are enabled for integration during which stage (i.e., UI) are described in further detail below.

FIG. 5is a block diagram illustrating an embodiment of equalizer215, including the various taps of summers320-323. For example, summer320includes a main tap501, pre cursor tap502, post cursor1tap503, post cursor2tap504, and various DFE taps505-507. In one embodiment, each tap includes sample and hold (SHN) logic (not shown) that samples and holds the signal to be integrated. In such an embodiment, the signal is started to be sampled one UI prior to the UI in which the signal is integrated. For example, main tap501may include SNH logic for sampling Vin_p/n during the period when snhclk0_p is HIGH (“1”), which is one UI prior to when snhclk90_p is HIGH; SNH logic then holds the sampled signal when snhclk0_p is LOW, which is integrated by main tap501during the UI when snhclk90_p is HIGH.FIG. 4illustrates the timing relationship between the clocks.

As described above, the integration current corresponding to a signal occurs over several, e.g., four stages (UIs). Each stage/UI corresponds to the enabling of one or more of the taps illustrated inFIG. 5. According to one aspect of the invention, a tap is enabled by an input clock, e.g., when the clock is “1.” Furthermore, each tap integrates the current of a different input signal, e.g., the integrated signal may be the incoming signal Vin_p/n, or an equalized signal from another branch (e.g., output signals out_p/n0, out_p/n90, out_p/n180, and/or out_p/n270), and/or a DFE sampled signal from one of the branches. As illustrated, main tap501integrates the current corresponding to Vin_p/n onto load capacitances C1/C2, respectively, during the UI when snhclk90_p is HIGH; pre cursor tap502integrates the current corresponding to out_p/n90(equalized output from branch90) during the UI when snhclk270_p is HIGH; post cursor1tap503integrates the current corresponding to out_p/n270(equalized output from branch270) during the UI when snhclk270_p is HIGH; post cursor2tap504integrates the current corresponding to out_p/n180(equalized output from branch180) during the UI when snhclk180_p is HIGH; DFE taps505integrates the current corresponding to D-1, D-5, and D-9(from branch270), and D-3(from branch90) during the UI when snhclk270_p is HIGH; DFE taps506integrates the current corresponding to D-2, D-6, and D-10(from branch180), and D-4(from branch0) during the UI when snhclk180_p is HIGH; and DFE taps507integrates the current corresponding to D-7and D-11(from branch90), and D-8and D-12(from branch0), during the UI when snhclk90_p is HIGH. In one embodiment, each of DFE taps505-507correspond to four DFE taps because each is responsible for integrating current corresponding to four input DFE sampled signals.

Pre cursor tap502integrates the current of an equalized signal out_p/n90, which results in a wider eye opening than conventional architectures, where the conventional pre cursor tap typically integrates the current corresponding to an output of the SNH of a main tap from another branch. For example, a pre cursor tap of a conventional equalizer (such as pre/post cursor tap131ofFIG. 1B) may integrate the current corresponding to the SNH output of a main tap (such as SNH102ofFIG. 1B).

Post cursor1tap503integrates the current corresponding to equalized signal out_p/n270, which results in a wider eye than conventional architectures. In a conventional equalizer architecture, a post cursor2tap typically integrates the SNH output of a pre cursor tap. The same advantages of integrating equalized signals can be said of the remaining pre and post cursor taps. The taps of summers321-323integrate the current of signals during the UIs as illustrated inFIG. 5using similar methods as discussed herein with respect to summer320.

FIGS. 6A-6Gare block diagrams illustrating the various taps of summer320(branch0) as illustrated inFIG. 5. For example,FIG. 6Aillustrates one embodiment of main tap501. Main tap501includes transistors which are enabled when snhclk0_p is HIGH, resulting in the resetting/discharging of load capacitors C1and C2to Ground. In one embodiment, main tap501includes SNH605that tracks Vin_p/n (i.e., passes Vin_p/n from source to drain of Q1/Q2, respectively) when clock snhclk0_p is HIGH. When snhclk0_p switches LOW, the signals Vin_p/n are latched at the SNH output nodes (gates of Q3and Q4, respectively), and will not be affected by further transitions by Vin_p/n. The output of SNH605determines the gate voltage of Q3/Q4. The gate voltage of Q3/Q4regulate the amount of current (acting as differential pair) charging capacitance C1and C2. For example, if the incoming differential Vin is positive (i.e., Vin_p>Vin_n), the current flowing through the drain of Q4(charging capacitance C1) is larger than the current flowing though the drain of Q3(charging capacitance C2), resulting in a positive differential output voltage (i.e., Out_p0−Out_n0>=0). Otherwise, if Vin is negative (i.e., Vin_p<Vin_n), the current flowing through the drain of Q4(charging capacitance C1) is smaller than the current flowing though the drain of Q3(charging capacitance C2), resulting in a negative differential output voltage (i.e., Out_p0−Out_n0<0). As illustrated, main tap501integrates the current corresponding to Vin_p/n onto load capacitances C1/C2when snhclk90_p is HIGH.

FIG. 6Bis a block diagram illustrating an embodiment of pre cursor1tap502. Pre cursor1tap502includes SNH606which tracks equalized signals out_p/n90when snhclk270_n is HIGH, and latches them when snhclk270_n switches LOW. As illustrated, pre cursor tap502integrates out_p/n90latched by SNH606when snhclk270_p is HIGH.

FIGS. 6C-6Gillustrate one embodiment of the remaining taps of summer320. These taps integrate the signals illustrated in a manner similar to the description of FIGS.6A-6B. For the sake of brevity, we will not discuss them here. It is worth clarifying, however, that each of the DFE taps505-507may be implemented as multiple taps. For example, althoughFIG. 6Eonly illustrates one tap, in embodiments in which four DFE sampled signals are integrated, four taps may be implemented to integrate each DFE sampled signal. Thus, as illustrated inFIG. 6E, the four taps shall integrate the DFE sampled signals D-1p/n, D-3p/n, D-5p/n, and D-9p/n, respectively. Alternatively, the number of DFE sampled signals that are integrated may be different. For example, DFE tap505may, in some embodiments, integrate only DFE sampled signal D-1p/n.

FIGS. 7A-7Gillustrate one embodiment of the taps of summer321(branch90),FIGS. 8A-8Gillustrate one embodiment of the taps of summer322(branch180), andFIGS. 9A-9Gillustrate one embodiment of the taps of summer323(branch270). These taps integrate the current onto load capacitances C3-C8in a similar manner to the taps described above herein with respect toFIGS. 6A-6G. There are differences, however, with respect to which signals are being integrated and during which UI.FIGS. 4 and 5illustrate which signals are integrated by the various taps, and during which UI they are integrated.

FIG. 10is a timing diagram illustrating exemplary clocking of summer320(branch0). Reference to “D-x ready” means that equalized data D-x is ready for integration. “D-x” refers to the various outputs of DFE samplers illustrated inFIGS. 3A-3D. The row on which “D-x ready” appears denotes the branch from which D-x is coming. The column on which “D-x ready” appears denotes the time when D-x is ready to be integrated. Thus, for example, “D-4ready” appears on row snhclk0_p (second row), which means that D-4is provided by a DFE sampler of branch0. The appearance of “D-4ready” in the column T0means that D-4is ready to be integrated during T0(the first UI) in the sequence. InFIG. 10, “∫tap” means that the respective tap is enabled for integration. The row on which “∫tap” appears denotes the branch that provides the equalized signal to be integrated. The column on which “∫tap” appears denotes the UI during which the integration is performed. Thus, for example, “∫D-4” appearing on row snhclk0means branch0provides the signal D-4to be integrated by DFE tap506. The fact that “∫D-4” appears in column T2means that the integration of D-4(by DFE tap506) occurs during T2(the third UI in the sequence).FIG. 10illustrates differential pairs as a single ended signal for clarity. For example, “D-4ready” means that both D-4p and D-4n are ready. And, “∫D-4” means that D-4p and D-4n are integrated.

As discussed above, conventional equalizers have a DFE timing constraint of one UI, i.e., the signal sampled by data sampler must be feedback to DFE taps within one UI period. Sampled signals are available only one UI prior to being integrated. In systems operating at high data rates, this may not be sufficient time for integration. As illustrated inFIG. 10, the integrating timing of the embodiments described herein is designed such that for DFE tap3and above, the sampled signals are ready, i.e., fed back to the summer, at least two UI periods before the corresponding taps of the summer integrate them This integration timing reduces the DFE timing constraint for DFE tap3and above to at least two UIs. For post cursor1, post cursor2and pre-cursor, FFEs with fully equalized signal are used as input to eliminate the one UI timing constraint.

During T0(i.e., the first UI), snhclk0_p clock rises from LOW to HIGH. At the rising edge of snhclk0_p, branch0samplers (e.g., DFE samplers304308and312) make a decision on whether the incoming signal Vin is either a “1” or “0,” based on the final integration value from previous integration period. For example, DFE sampler304determines if out_0is a “0” or “1” and latches the corresponding value onto D-4at the rising edge of sampler_clk0_p. Thus, as illustrated inFIG. 10, D-4is ready at T0. At the falling edge of snhclk0_p, the second and third sampler of branch0(e.g. DFE sampler308and312) latch the corresponding values onto D-8and D-12respectively. Thus, as illustrated inFIG. 10, D-8/D-12is ready at T-2. After out_0is latched onto D-4at the rising edge of sampler_clk0_p, the load capacitances C1and C2are discharged to Ground by main tap501during the first UI, getting them ready for the current round of integrations. While snhclk0_p clock is HIGH, SNH605of main tap501tracks the input signal Vin.

During T1(i.e., the second UI), when snhclk0_p switches LOW, SNH605latches Vin, and integration by the main tap501of the current corresponding to input signal Vin starts for a duration of one UI. Put differently, main tap501starts integrating the current corresponding to Vin during the UI when snhclk90_p is HIGH, which is one UI delayed from snhclk0_p. This is denoted inFIG. 10as “∫Vin.” During the same UI when snhclk90_p is HIGH, D-7, D-8, D-11, and D-12(outputs of DFE samplers307,308,311, and312, respectively) are integrated by DFE taps507. This is denoted inFIG. 10as “∫D-7,” “∫D-8,” “∫D-11,” and “∫D-12,” respectively.

As illustrated inFIG. 10, the DFE tap timing constraint is at least two UIs for DFE tap3and above, unlike conventional equalization architectures which have a strict one UI timing constraint. For example, D-7is ready for integration at T-1, but it is not integrated until T1, which is two UIs later. Thus,FIG. 10illustrates a clocking structure that relaxes the DFE tap timing constraint to at least two UIs, which is easy to meet even for very high speed data rate (such as OIF CEI 28 Gbps or 802.3bj 25 Gbps).

During T2(the third UI), all taps within branch180complete their current integration process. The final value of branch180(i.e., out_180) is a signal that is fully equalized by the CTLE, FFE, and DFE taps521-527. In one embodiment, out_180is integrated by post cursor2tap504during the third UI (when snhclk180_p is HIGH). This is denoted inFIG. 10as “∫D-2/Post Cursor2.”

During the same third UI, DFE sampled signals D-4, D-6, and D-10are integrated by DFE taps506(denoted inFIG. 10as “∫D-4,” “∫D-6,” and “∫D-10”). Again, these equalized signals are ready for integration at least two UIs earlier. For example, D-4is ready at T0, which is two UIs earlier then when it is integrated at T2. It should be noted, however, that the integration of D-2does not have this relaxed timing constraint. For example, D-2is ready for integration at T2, the same UI that it is integrated. At high data rates, this timing constraint may not be met. Thus, in one embodiment, the integration of D-2is disabled at high data rates. For lower data rates, D-2integration may be enabled since the UI period is much larger. The selective integration of D-2is denoted inFIG. 10as “∫D-2/Post Cursor2” to clarify that at high data rates, only integration of out_180by post cursor2tap504is performed because signal out_180is the analog equivalent of D-2.

During T3(the fourth UI), all integrations are done at branch270. The final value of branch270(i.e., out_270) is a signal that is fully equalized by the CTLE, FFE, and DFE taps531-537. In one embodiment, out_270is integrated by post cursor1tap503(of branch 0) during the fourth UI (when snhclk270_p is HIGH). This is denoted inFIG. 10as “∫D1/Post Cursor1.”

During the same fourth UI, DFE sampled signals D-3, D-5, and D-9are integrated by DFE taps505(denoted inFIG. 10as “∫D-3,” “∫D-5,” and “∫D-9”). Again, these equalized signals are ready for integration at least two UIs earlier. For example, D-3is ready at T1, which is two UIs earlier then when it is integrated at T3. It should be noted, however, that the integration of D-1does not have this relaxed timing constraint. For example, D-1is ready for integration at T3, the same UI that it is integrated. At high data rates, this timing constraint may not be met. Thus, in one embodiment, the integration of D-1is disabled at high data rates. For lower data rates, D-1integration may be enabled since the UI period is much larger. The selective integration of D-1is denoted inFIG. 10as “∫D-1/Post Cursor1” to clarify that at high data rates, only integration of out_270by post cursor1tap503is performed, because out_270is the analog equivalent of D-1.

During the same fourth UI (T3), equalized signal out_90is integrated by pre cursor tap502(as denoted by “∫Pre Cursor.”) During T3, the integration by branch90(i.e., on Out_p/n90) has not been completed because only main tap511and DFE taps517have completed their current integration process. Pre cursor tap512, post cursor1tap513, post cursor2tap514, DFE taps515, and DFE taps516have not completed their integration yet. Pre cursor tap502, however, is the only FFE tap in branch0which does not use fully equalized data (i.e., from Out_p/n90). Out_0is equalized during T3, and latched by DFE sampler304during T4, marking the beginning of another equalization sequence.

FIG. 10illustrates one embodiment of the clocking of branch0. The clocking of branch0is not limited to the illustrated sequence with respect to which taps are enabled for integration during a particular UI. Nor is the clocking of branch0limited to the illustrated signals that are integrated by the particular taps that are enabled during each UI. Additionally, the clocking of branch0may be extended to operate in sequences other than four UIs.

FIG. 11is a flow diagram illustrating a method1100for determining a value of a received data signal. For example, method1100may be performed by branch0of equalizer215, such as DFE samplers304,308,312, and summer320. At block1105, a first DFE sampler (e.g., DFE sampler304) latches an equalized output (e.g., out_p/n0) of the summer. At block1110, a second DFE sampler (e.g., DFE sampler308) latches an output of the first DFE sampler (e.g., DFE sampler304). At block1115, a third DFE sampler (e.g., DFE sampler312) latches an output of the second DFE sampler (e.g., DFE sampler308). At block1120, a summer (e.g., summer320) integrates the output of the DFE samplers (e.g., DFE samplers304,308, and312), the received signal, and equalized outputs from one ore more other branches (e.g., out_p/n90, out_p/n180, and out_p/n270).

Throughout the description, metal oxide semiconductor field effect transistors (MOSFETs, also commonly known simply as MOS) are illustrated as the building blocks of various logic. The logic blocks, however, are not so limited. For example, the logic blocks may be implemented using bipolar junction transistors (BJTs), or a combination of MOS and BJT transistors, commonly known as BiCMOS technology.

A receiver equalizer includes a plurality of branches for equalizing a received signal. The first branch comprises a first decision feedback equalizer (DFE) sampler coupled to a summer for latching an equalized output of the summer. In one embodiment, the first branch of the equalizer includes a second DFE sampler coupled to the first DFE sampler for latching an output of the first DFE sampler. In one embodiment, the first branch includes a third DFE sampler coupled to the second DFE sampler for latching an output of the second DFE sampler. The summer is coupled to the first, second, and third DFE sampler of the first branch for integrating the output of said DFE samplers, the received signal, and equalized outputs from other branches. The integrating occurs over a plurality of unit intervals (UIs).

The summer comprises a main tap for integrating the received signal during a second UI. The summer further comprises a first DFE tap for integrating the output of the second DFE sampler of the first branch during the second UI. In one embodiment, the summer comprises a second DFE tap for integrating the output of the third DFE sampler of the first branch during the second UI. In one embodiment, the summer further comprises a third DFE tap for integrating an output of a second DFE sampler of a second branch during the second UI. In one embodiment, the summer comprises a fourth DFE tap for integrating an output of a third DFE sampler of the second branch during the second UI.

The summer comprises a second post cursor tap for integrating an equalized output from a third branch during a third UI. The summer further comprises a fifth DFE tap for integrating the output of the first DFE sampler of the first branch during the third UI. In one embodiment, the summer comprises a sixth DFE tap for integrating an output of a first DFE sampler of the third branch during the third UI. In one embodiment, the summer further comprises a seventh DFE tap for integrating an output of a second DFE sampler of the third branch during the third UI. In one aspect of the invention, the summer comprises an eighth DFE tap for integrating an output of a third DFE sampler of the third branch during the third UI.

The summer comprises a pre cursor tap for integrating an equalized output from the second branch during a fourth UI. The summer comprises a first post cursor tap for integrating an equalized output from a fourth branch during the fourth UI. The summer further comprises a ninth DFE tap for integrating the output of a first DFE sampler of the second branch during the fourth UI. In one embodiment, the summer comprises a tenth DFE tap for integrating an output of a first DFE sampler of the fourth branch during the fourth UI. In one embodiment, the summer comprises an eleventh DFE tap for integrating an output of a second DFE sampler of the fourth branch during the fourth UI. In one aspect of the invention, the summer comprises a twelfth DFE tap for integrating an output of a third DFE sampler of the fourth branch during the fourth UI.

Various embodiments and aspects of the inventions have been described with reference to the drawings. The description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions.

The techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices. Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer-readable media, such as non-transitory computer-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer-readable transmission media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals).