Liquid crystal display

A liquid crystal display includes a substrate, first and second pixels neighboring in a row direction, third and fourth pixels respectively neighboring the first and second pixel in a column direction, wherein the pixels are formed on the substrate, first and second data lines formed on the substrate that transmit a data voltage, and a voltage line disposed between the first and second data lines. The pixels respectively include a first switching element connected to the first or second data line, a second switching element connected to the voltage line, a first pixel electrode connected to the first switching element, and a second pixel electrode connected to the second switching element. A position of the first pixel electrode with respect to the second pixel electrode of the first pixel is opposite to a position of the first pixel electrode with respect to the second pixel electrode of the second pixel.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2010-0020137 filed in the Korean Intellectual Property Office on Mar. 5, 2010, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display.

(b) Description of the Related Art

Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. An LCD includes a pair of panels provided with field-generating electrodes, such as pixel electrodes and a common electrode, and a liquid crystal (LC) layer interposed between the two panels. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer that determines the orientations of LC molecules therein to adjust polarization of incident light.

An LCD also includes switching elements connected to the respective pixel electrodes, and a plurality of signal lines such as gate lines and data lines for controlling the switching elements and thereby applying voltages to the pixel electrodes.

The liquid crystal display receives an input image signal from an external graphics controller, the input image signal contains luminance information of each pixel PX, and the luminance is represented by gray levels of varying intensity. Each pixel is supplied with the data voltage corresponding to the desired luminance information. The data voltage applied to the pixel appears as a pixel voltage according to a difference between a reference voltage such as a common voltage and the data voltage, and each pixel displays luminance representing a gray of the image signal according to the pixel voltage. Here, the range of the pixel voltage that is applicable to the liquid crystal display is determined according to a driver.

The driver of the liquid crystal display may be mounted on the display panel in a form of a plurality of integrated circuit (IC) chips, or may be installed on a flexible circuit film and attached to the display panel, but the use of IC chips involves a high percentage of the manufacturing cost of the liquid crystal display.

SUMMARY OF THE INVENTION

A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate, a first pixel and a second pixel that neighbor each other in a row direction, a third pixel and a fourth pixel respectively neighboring the first pixel and the second pixel in a column direction, wherein the first to fourth pixels are formed on the first substrate, a first data line and a second data line formed on the first substrate and respectively transmitting a data voltage, and a first voltage line disposed between the first data line and the second data line. The first pixel, the second pixel, the third pixel, and the fourth pixel respectively include a first switching element connected to either the first data line or the second data line, a second switching element connected to the first voltage line, a first pixel electrode connected to the first switching element, and a second pixel electrode connected to the second switching element. A position of the first pixel electrode with respect to the second pixel electrode of the first pixel is opposite to a position of the first pixel electrode with respect to the second pixel electrode of the second pixel.

The first pixel electrode and the second pixel electrode may respectively include a plurality of branches, and the branches of the first pixel electrode and the branches of the second pixel electrode may be alternately interposed with each other.

A branch arrangement sequence of the first pixel electrode and of the second pixel electrode in the first pixel may be opposite to a branch arrangement sequence of the first pixel electrode and the second pixel electrode in the third pixel.

The branches of the first pixel electrode and the branches of the second pixel electrode may be periodically curved with a zigzag shape.

The first data line, the second data line, and the first voltage line, may be periodically curved with a zigzag shape according to the first pixel electrode and the second pixel electrode.

The first voltage line may be supplied with two different voltages alternately by frame.

The liquid crystal display may further include a second voltage line extending parallel to the first voltage line, wherein the second voltage line may be supplied with a different voltage from the first voltage line.

The liquid crystal display may further include a first common voltage line disposed on an edge portion of the first substrate and intersecting the first and second data lines, wherein the first voltage line may be connected to the first common voltage line, thereby receiving a voltage.

The liquid crystal display may further include a second common voltage line disposed on an edge portion of the first substrate and intersecting the first and second data lines, wherein the second voltage line may be connected to the second common voltage line, thereby receiving a voltage.

The liquid crystal display may further include a data driver respectively applying a data voltage to the first data line and the second data line, wherein the first voltage line and the second voltage line respectively receive a voltage from the data driver.

The liquid crystal display may further include a second substrate facing the first substrate and a liquid crystal layer interposed between the first substrate and the second substrate. The liquid crystal layer has positive dielectric anisotropy, and may be in a vertical alignment mode in the absence of an electric field.

DESCRIPTION OF SYMBOLS

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

In the drawings, the thickness of layers, films, panels, regions, etc., can be exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference toFIG. 1andFIG. 2.

FIG. 1is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, andFIG. 2is an equivalent circuit diagram showing a structure of a liquid crystal display and one-pixel according to an exemplary embodiment of the present invention.

Referring toFIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly300, a gate driver400, a data driver500, a gray voltage generator800, and a signal controller600.

The liquid crystal panel assembly300includes a plurality of signal lines (not shown) and a plurality of pixels PX connected thereto and arranged in an approximate matrix. Meanwhile, referring toFIG. 2, in a view of the structure, the liquid crystal panel assembly300includes lower and upper panels100and200facing each other, and a liquid crystal layer3therebetween.

The plurality of signal lines includes gate lines and data lines.

Referring toFIG. 2, each pixel PX includes a liquid crystal capacitor Clc, a first storage capacitor Csta, and a second storage capacitor Cstb.

The liquid crystal capacitor Clc includes the first pixel electrode PEa and a second pixel electrode PEb of the lower panel100as two terminals, and the liquid crystal layer3between the first and the second pixel electrodes PEa and PEb functions as a dielectric material. The first pixel electrode PEa and the second pixel electrode PEb may be connected to the signal lines through a separate switching element (not shown). The liquid crystal layer3has dielectric anisotropy and may be in a vertical alignment mode, in which the liquid crystal molecules of the liquid crystal layer3have their long axes aligned vertical to surfaces of the two panels100and200in the absence of an electric field.

The first and second pixel electrodes PEa and PEb of the pixel electrode PE may be formed from different layers, or from the same layer.

The first storage capacitor Csta and the second storage capacitor Cstb serving as assistants to the liquid crystal capacitor Clc may be respectively formed by overlapping separate electrodes (not shown) provided on the lower panel100with the first and second pixel electrodes PEa and PEb via an insulator interposed therebetween. The first and second storage capacitors Csta and Cstb may be omitted if necessary.

In addition, to realize a color display, each pixel PX uniquely displays one of primary colors (spatial division), or each pixel PX temporally and alternately displays one of the primary colors (temporal division). Then, the primary colors are spatially or temporally synthesized, and thus a desired color is recognized. An example of the primary colors may be red, green, and blue. One example of the spatial division is represented inFIG. 2, where each pixel PX is provided with a color filter (CF) for one of the primary colors on the region of the upper panel200corresponding to the first and second pixel electrodes PEa and PEb. Alternatively, the color filter CF may be formed on or below the first and second pixel electrodes PEa and PEb of the lower panel100.

Referring again toFIG. 1, the gray voltage generator800generates all gray level voltages or a predetermined number, of gray level voltages (or reference gray level voltages) related to transmittance of the pixels PX.

The gate driver400is connected to the gate lines of the liquid crystal panel assembly300, and applies a gate signal configured by a combination of a gate-on voltage Von and a gate-off voltage Voff to the gate lines.

The data driver500is connected to the data lines of the liquid crystal panel assembly300, and selects a gray level voltage from the gray voltage generator800and applies the selected gray level voltage to the data line as the data voltage. However, in a case in which the gray voltage generator800provides a limited number of reference gray level voltages instead of all of the gray level voltages, the data driver500generates a desired data voltage by dividing the reference gray level voltages.

The signal controller600controls the gate driver400and the data driver500.

Next, a method of driving a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference toFIG. 3as well asFIG. 1andFIG. 2.

FIG. 3is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.FIG. 3shows the lower and upper panels100and200facing each other, the liquid crystal layer3therebetween, the first and second pixel electrodes PEa and PEb, and the liquid crystal molecules31.

Referring toFIG. 1, the signal controller600receives input image signals R, G, and B and input control signals for controlling the input image signals from an external graphics controller (not shown). The input image signals R, G, and B contain a luminance value of the respective pixels PX, and the luminance value can have one of a predetermined number of gray values, for example 1024=210, 256=28, or 64=26. The input control signals include vertical synchronization signals Vsync, horizontal synchronization signals Hsync, main clock signals MCLK, and data enable signals DE.

The signal controller600, based on the received input image signals R, G, and B and the input control signals, processes the input image signals R, G, and B in accordance with the operating conditions of the liquid crystal panel assembly300, and generates gate control signals CONT1, data control signals CONT2, and digital image signals DAT. Then, the signal controller600transmits the gate control signals CONT1to the gate driver400, while transmitting the data control signals CONT2and the processed image signals DAT to the data driver500.

Depending upon the data control signals CONT2from the signal controller600, the data driver500receives the digital image signals DAT for one row of pixels PX, and selects gray voltages corresponding to the respective digital image signals DAT, followed by converting the digital image signals DAT into analog data voltages Vd and applying them to the corresponding data lines.

Upon receipt of the gate control signals CONT1from the signal controller600, the gate driver400applies gate-on voltages Von to the gate lines to turn on the switching elements connected to the gate lines. Thus, the data voltage Vd applied to the data line is applied to the pixel electrode PE through the turned-on switching element. Here, only one of the first pixel electrode PEa and the second pixel electrode PEb may be supplied with the data voltage, and the other may be supplied with a predetermined voltage or may be periodically supplied with two voltages that oscillate.

The difference between the two data voltages applied to the first and second pixel electrodes PEa and PEb is expressed as a charged voltage of the liquid crystal capacitors Clc, i.e., a pixel voltage.

If a potential difference is generated between two terminals of the liquid crystal capacitor Clc, as shown inFIG. 4, an electric field parallel to the surface of the display panel100and200is formed on the liquid crystal layer3between the first and second pixel electrodes PEa and PEb, as shown inFIG. 3. When the liquid crystal molecules31have a positive dielectric anisotropy, the liquid crystal molecules31arrange themselves such that the long axes thereof are aligned parallel to the direction of the electric field, and the degree of inclination changes according to the magnitude of the pixel voltage. This liquid crystal layer3is referred to as an electrically-induced optical compensation (EOC) mode liquid crystal layer. Also, the polarization of light passing through the liquid crystal layer3is changed according to the inclination degree of the liquid crystal molecules31. The change of the polarization appears as a change of transmittance of light by the polarizer, and accordingly, the pixel PX displays the luminance representing the gray value of the image signal DAT.

By repeating such a process by one horizontal period (also referred to as “1H”, equal to one period of the horizontal synchronization signal (Hsync) and the data enable signal DE), the gate-on signal Von is sequentially applied to all the gate lines and the data voltages are applied to all the pixels PX to display an image of one frame.

Next, a structure to apply a voltage to a pixel of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference toFIG. 4andFIG. 5as well asFIG. 1toFIG. 3.

FIG. 4andFIG. 5are equivalent circuit diagrams of two pixels in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring toFIG. 4, the liquid crystal display according to the present exemplary embodiment includes signal lines including a gate line Gi, a storage electrode line SL, neighboring data lines Dj and D(j+1), and a voltage line VL disposed between two data lines Dj and D(j+1), and pixels PXnand PXn+1connected thereto.

The gate line Gi transmits the gate signal, and the storage electrode line SL transmits a predetermined voltage such as a common voltage Vcom. The gate line Gi and the storage electrode line SL may be parallel to each other.

The data lines Dj and D(j+1) transmit the data voltage Vd from the data driver500.

The voltage line VL is supplied with a predetermined voltage or is periodically supplied with two voltages that oscillate. For example, the voltage line VL may be periodically supplied with a lowest voltage and a highest voltage that are available to the liquid crystal display, and the oscillation period of the voltage may be one frame. The voltage line VL may receive the predetermined voltage or the two oscillating voltages from the data driver500, via the data lines Dj and D(j+1). If the voltage from the data driver500is supplied to the voltage line VL, it may be useful for synchronizing the signal.

Each pixel PXn and PX(n+1) includes a first switching element Qa, a second switching element Qb, the liquid crystal capacitor Clc, the first storage capacitor Csta, and the second storage capacitor Cstb.

The first and second switching elements Qa and Qb may be three terminal elements such as a thin film transistor provided in the lower panel100. The first switching element Qa of each pixel PXn and PX(n+1) includes a control terminal connected to the gate line Gi, an input terminal connected either to the data lines Dj or D(j+1), and an output terminal connected to the liquid crystal capacitor Clc and the first storage capacitor Csta. The second switching element Qb of each pixel PXn and PX(n+1), includes a control terminal connected to the gate line Gi, an input terminal connected to the voltage line VL, and an output terminal connected to the liquid crystal capacitor Clc and the second storage capacitor Cstb. The second switching elements Qb of two neighboring pixels PXn and PX(n+1) are connected to the same voltage line VL.

The description of the liquid crystal capacitor Clc and the first and the second storage capacitors Csta and Cstb is the same as the description ofFIG. 2such that it is omitted. However, in the exemplary embodiment shown inFIG. 4, the first and second storage capacitors Csta and Cstb are formed by respectively overlapping the first pixel electrode PEa and the second pixel electrode PEb, with the storage electrode line SL, via the insulator interposed therebetween.

In the exemplary embodiment shown inFIG. 5, instead of one voltage line VL, a first voltage line VL1and a second voltage line VL2are disposed between two neighboring pixels PXn and PX(n+1) such that the second switching element Qb of the pixels PXn and PX(n+1) are respectively connected to the first voltage line VL1and the second voltage line VL2. The first and second voltage lines VL1and VL2may be supplied with one predetermined voltage, or may be periodically supplied with two oscillating voltages. Alternatively, the first voltage line VL1and the second voltage line VL2may be periodically supplied with the different voltages that oscillate for the frame. As described above, the voltages may be the lowest voltage and the highest voltage available to the liquid crystal display.

Next, an operation of the liquid crystal display shown inFIG. 4will be described with reference toFIG. 6andFIG. 7.

FIG. 6andFIG. 7depict a charging voltage of a liquid crystal capacitor and a data voltage applied to a data line of four neighboring pixels in two sequential frames when an available lowest voltage is 0V and an available highest voltage is 15V in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring toFIG. 6andFIG. 7, one voltage line VL is disposed between two neighboring pixels, and two pixels PX are commonly connected to the voltage line VL. The voltage line VL is periodically supplied with the highest driving voltage (e.g., 15V) and the lowest driving voltage (e.g., 0V) by frame, and two neighboring voltage lines VL are supplied with different voltages. That is, if the voltage line VL is supplied with 0V in one frame as shown inFIG. 6, the voltage line VL is supplied with 15V in the next frame as shown inFIG. 7, and the neighboring voltage lines VL is supplied with the reverse voltage.

The data voltages applied to the data lines Dj, D(j+1), D(j+2), and D(j+3) may be the highest driving voltage, the lowest driving voltage, or voltages therebetween.

First, referring toFIG. 6, when the left voltage line VL is supplied with 0V and the right voltage line VL is supplied with 15V, the target charging voltage of the first pixel is 15V, such that the first data line Dj is supplied with the data voltage of 15V, and the target charging voltage of the second pixel is 10V such that the second data line D(j+1) is supplied with 10V. The target charging voltage of the third pixel is 10V such that the third data line D(j+2) is supplied with 5V, and the target charging voltage of the fourth pixel is 14V such that the fourth data line D(j+3) is supplied with 1V. Here, the two left pixels are supplied with a data voltage having a positive polarity and two right pixels are supplied with a data voltage of a negative polarity with respect to the voltage of the voltage line VL such that it is possible to drive by column inversion, and thereby improve display characteristics.

In the next frame, as shown inFIG. 7, the left voltage line VL is supplied with 15V, and the right voltage line VL is supplied with 0V. The target charging voltage of the first pixel is 15V such that the first data line Dj is supplied with the data voltage of 0V, and the target charging voltage of the second pixel is 1.0V such that the second data line D(j+1) is supplied with 5V. The target charging voltage of the third pixel is 10V such that the third data line D(j+2) is supplied with 10V, and the target charging voltage of the fourth pixel is 14V such that the fourth data line D(j+3) is supplied with 14V. Here, two left pixels are supplied with a data voltage having a negative polarity and two right pixels are supplied with a data voltage having a positive polarity with respect to the voltage of the voltage line VL such that it is possible to drive by column inversion, and since the opposite polarity was applied to the previous frame, driving by frame inversion is realized.

In the exemplary embodiments ofFIG. 6andFIG. 7, the values of the target charging voltage of the pixel and the voltage applied to the voltage line VL are exemplary, and may vary according to the liquid crystal display.

In the present exemplary embodiment, the voltage line VL that is shared by two pixels is disposed between two neighboring pixels, such that the number of data lines may be reduced, the aperture ratio and the transmittance of the liquid crystal display may be increased, and the number of data drivers may be reduced. Therefore, the manufacturing cost of the liquid crystal display may be reduced.

Also, two pixel electrodes of one pixel PX are supplied with voltages having different polarities with respect to the common voltage Vcom that is substantially between the highest driving voltage and the lowest driving voltage, such that the driving voltage may be increased, the response speed of the liquid crystal molecule may be increased, and the transmittance of the liquid crystal display may be increased.

Next, an inversion driving method of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference toFIG. 8.

FIG. 8is an equivalent circuit diagram of four pixels of a liquid crystal display according to an exemplary embodiment of the present invention,

Referring toFIG. 8, a circuit of four pixels PX1, PX2, PX3, and PX4that neighbor each other in the row direction and the column direction is Shown. The connection relationship of two pixels PX1and PX2that neighbor in the row direction is the same as that of the exemplary embodiment shown inFIG. 4such that the detailed description thereof is omitted.

However, the connection relationship of the liquid crystal capacitor Clc, and the first and second switching elements Qa and Qb of two pixels PX3and PX4, is different from that of the pixels PX1and PX2. Referring to the left terminal of the liquid crystal capacitor Clc as the first terminal and the right terminal as the second terminal, the first switching element Qa of the pixels PX1and PX2are connected to the first terminal of the liquid crystal capacitor Clc, the second switching element Qb is connected to the second terminal of the liquid crystal capacitor Clc. On the other hand, the first switching element Qa of the pixels PX3and PX4is connected to the second terminal of the liquid crystal capacitor Clc, and the second switching element Qb thereof is connected to the first terminal of the liquid crystal capacitor Clc.

Thus, although the voltage line VL is supplied with the same voltage during one frame, row inversion driving is possible.

Next, the pixel structure and liquid crystal display arrangement shown inFIG. 8will be described with reference toFIG. 9toFIG. 1.3.

FIG. 9is a layout view of four pixels of a liquid crystal display according to an exemplary embodiment of the present invention, andFIG. 10is a cross-sectional view of the liquid crystal display ofFIG. 9taken along the line X-X.

Referring toFIG. 9andFIG. 10, a liquid crystal display according to an exemplary embodiment of the present invention includes lower and upper display panels100and200facing each other, and a liquid crystal layer3interposed between the two panels100and200.

First, the lower display panel100will be described in detail.

A plurality of gate conductors including a plurality of gate lines121, and a plurality of storage electrode lines131are formed on an insulation substrate110.

The gate lines121transmit gate signals and extend in a transverse direction, and each gate line121includes a plurality of pairs of first and second gate electrodes124aand124b.

The storage electrode line131receives a predetermined voltage such as a common voltage Vcom, and extends in the transverse direction. Each storage electrode line131may be disposed above a neighboring gate line121, and may include a downward protrusion.

A gate insulating layer140that may be made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors121and131.

A plurality of first semiconductor stripes (not shown) and a plurality of second semiconductor stripes (not shown) respectively disposed between pairs of first semiconductor stripes are formed on the gate insulating layer140, and they may be made of hydrogenated amorphous silicon or polysilicon. The first semiconductor stripe includes protrusions154aprotruding on the left or right side to be disposed on the first gate electrode124a, and the second semiconductor stripe includes protrusions154bprotruding on both of the right and left sides to be disposed on the second gate electrodes124b.

Ohmic contacts163aand165aare formed on the first and the second semiconductor stripes. The ohmic contacts163aand165amay be made of a material such as n+hydrogenated a-Si that is heavily doped with an n-type impurity such as phosphorus, or of a silicide. The ohmic contacts163aand165aare separated from each other on the first and second gate electrodes124aand124b.

A data conductor including a plurality of pairs of data lines171, a plurality of voltage lines178, and a plurality of pairs of first and second drain electrodes175aand175bare formed on the ohmic contacts163aand165aand the gate insulating layer140.

The data line171transmits the data signal and extends substantially in the longitudinal direction. As shown inFIG. 9, the data line171may be periodically curved with a zigzag shape, and there may be a plurality of curves. The acute angle between the oblique edge of the data line171and the gate line121may be about 45 degrees. The data line171includes a first source electrode173aextending toward the first gate electrodes124aand124b.

The voltage line178is disposed between the pair of data lines171, and transmits a predetermined voltage, or alternatively, transmits two voltages that periodically oscillate. The voltage line178extends in the longitudinal direction like the data line171, as shown inFIG. 9, may be curved parallel to the data line171with the zigzag shape. The acute angle between the oblique edge of the voltage line178and the gate line121may be about 45 degrees. The voltage line178includes second source electrodes173bextending in both sides toward the second gate electrodes124b. The first source electrode173aand the second source electrode173bface each other with mirror symmetry.

The first drain electrode175aincludes a bar-shaped end portion and a first extension177ahaving a wide area, and the second drain electrode175bincludes a bar-shaped end portion and a second extension177bhaving a wide area. The bar-shaped end portions of the first and second drain electrodes175aand175bare respectively opposite to the first and second source electrodes173aand173bwith respect to the first and second gate electrodes124aand124b, and are partially enclosed by the first and second source electrodes173aand173b. Most of the first and second expansions177aand177boverlap the storage electrode line131.

The first and second gate electrodes124aand124b, the first and second source electrodes173aand173h, and the first and second drain electrodes175aand175brespectively constitute the first and second thin film transistors Qa and Qb together with the first and second semiconductors154aand154b. Channels of the first and second thin film transistors Qa and Qb are respectively formed in the first and second semiconductors154aand154bbetween the first and second source electrodes173aand173band the first and second drain electrodes175aand175b.

The protrusions154aand154bof the semiconductor have a portion that is exposed without being covered by the first and second source electrodes173aand173band the first and second drain electrodes175aand175b.

A passivation layer180made of an inorganic insulator or an organic insulator is formed on the data conductors173a,173b,175a, and175b, and the exposed protrusions154aand154bof the semiconductors.

The passivation layer180has a plurality of contact holes185aand185bexposing portions of the first and second extensions177aand177b.

A plurality of pairs of first and second pixel electrodes191aand191bthat may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective metal such as aluminum, silver, chromium, or alloys thereof, are formed on the passivation layer180.

As shown inFIG. 9, the first and second pixel electrodes191aand191binclude a plurality of branches that are interposed between each other with a substantially uniform gap, and the plurality of branches are substantially parallel to the data lines171and the voltage line178. The plurality of branches may be curved with the zigzag shape like the data line171and the voltage line178as shown inFIG. 9, and may form an acute angle of about 45 degrees with the gate line121. The branches of the first pixel electrode191aand the second pixel electrode191bare alternately disposed, thereby forming a pectinate pattern.

The first and second pixel electrodes191aand191bare respectively physically and electrically connected to the first and second drain electrodes175aand175bthrough the contact holes185aand185b. The first and second pixel electrodes191aand191brespectively receive data voltages from the first and second drain electrodes175aand175b. The first and second pixel electrodes191aand191balong with the liquid crystal layer3form the liquid crystal capacitor Clc which maintains the applied voltage after the first and second thin film transistors Qa and Qb are turned off.

The first and second expansions177aand177bof the first and second drain electrodes175aand175bthat are connected to the first and second pixel electrodes191aand191boverlap the storage electrode line131via the gate insulating layer140, thereby respectively forming the first and second storage capacitors Csta and Cstb that enhance the voltage maintaining capacity of the liquid crystal capacitor Clc.

Referring toFIG. 8andFIG. 9, for the pixels PX1and PX3, or PX2and PX4neighbor each other in the column direction, the sequence in which the branches of the first and second pixel electrodes191aand191bare positioned in the region where light is transmitted is different. That is, the branches of the second pixel electrode191bof the pixels PX1and PX2disposed in the upper row form the outer boundary of the pixels PX1and PX2, and are disposed ahead of the first pixel electrode191a. On the other hand, the branches of the first pixel electrode191aform the outer boundary of the pixels PX3and PX4in disposed in the lower row, and are disposed ahead of the second pixel electrode191b. As described above, the arrangement sequence of the branches of the first pixel electrode191aand the second pixel electrode191bof the pixels neighboring in the column direction are reversed, and as a result, as shown inFIG. 8, row inversion driving may be realized with respect to the voltage line178supplied with a voltage that oscillates by frame.

Next, referring to the upper panel200, light blocking member220and a plurality of color filters230are formed on an insulation substrate210. The light blocking member220blocks light leakage between the first and second pixel electrodes191aand191b. The color filter230is primarily disposed in the region enclosed by the light blocking member220, and may extend along the columns of the first and second pixel electrodes191aand191b.

An overcoat250is formed on the color filter230and the light blocking member220. The overcoat250may be made of an (organic) insulating material, and protects the color filters230and provides a flat surface. The overcoat250may be omitted.

Vertical alignment layers (not shown) may be formed on the inner surface of the display panels100and200.

Polarizers (not shown) may be provided on the outer surface of the display panels100and200.

If the first and second pixel electrodes191aand191bare supplied with voltages through the data line171and the voltage line178, an electric field approximately parallel to the surface of the display panels100and200is formed. Thus, the liquid crystal molecules of the liquid crystal layer3that are initially aligned perpendicular to the surfaces of the display panels100and200rearrange themselves in response to the electric field such that the long axes thereof are inclined parallel to the direction of the electric field, and the polarization degree of the light incident to the liquid crystal layer3varies according to the inclination degree of the liquid crystal molecules. The change of polarization appears as a change of transmittance by the polarizer, by which the liquid crystal display displays the images.

In the present exemplary embodiment, the first and second pixel electrodes191aand191bcurve with a zigzag shape to vary the inclination direction of the liquid crystal molecules, and thereby improve the viewing angle. In addition, the exemplary embodiment ofFIG. 9may also incorporate characteristics and effects of the exemplary embodiments described above.

FIG. 11,FIG. 1.2, andFIG. 13are layout views of a plurality of pixels of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring toFIG. 11, the pixels shown inFIG. 9are consecutively disposed in a row direction. That is, the two pixels PX1and PX2are alternately disposed in the upper row of the pixel, and the two pixels PX3and PX4are alternately disposed in the lower row of the pixel. On the other hand, the two neighboring voltage lines178are supplied with different voltages, for example 0V and 15V. As described above, as shown inFIG. 6andFIG. 7, the polarities of the data voltages applied to the neighbor pixel pair PX1and PX2in each pixel row are reversed, to realize column inversion. Also, the voltage applied to each voltage line178may oscillate by frame, to realize frame inversion as described regardingFIG. 6andFIG. 7.

Next, referring toFIG. 12, a pair of pixels PX1and PX2, and a pair of pixels PX3and PX4are alternately disposed in one pixel row. That is, a pair of pixels including the pixels PX1and PX2neighbor the pair of pixels including the pixels PX3and PX4. Pixels PX3and PX4have first and second pixel electrodes191aand191bwhose branch arrangement is reversed with respect to the branch arrangement of the first and second pixel electrodes191aand191bof the pixels PX1and PX2. Here, two neighboring voltage lines178may be supplied with the same voltage, for example 0V and 15V. Although the voltage line178between the pixel pair PX1and PX2and the voltage line178between the pixel pair PX3and PX4neighboring in the row direction are supplied with the same voltage, the branch arrangements of the first and second pixel electrodes191aand191bof the two pixel pairs are reversed with respect to each other, to realize column inversion.

Next,FIG. 13shows another arrangement of the pixels PX1, PX2, PX3, and PX4, each having first and second pixel electrodes191cand191d, according to an embodiment of the invention. In this exemplary embodiment, the number of the branches of each of the pixel electrodes191cand191dis reduced by two with respect to the number of branches of the first and second pixel electrodes191aand191bof the exemplary embodiment ofFIG. 11andFIG. 1.2. The voltage lines178are alternately supplied with the highest driving voltage (e.g., 15V) and the lowest driving voltage (e.g., 0V) in the row direction. The pixels R, G, and B representing red (R), green (G), and blue (B) are alternately disposed in the row direction, and, as shown inFIG. 9, pixels PX1and PX3, and PX2and PX4, for which the branch arrangement of the first and second pixel electrodes191cand191dare reversed, are disposed as neighbors in the column direction.

When the pixels PX1, PX2, PX3, and PX4are disposed like this, and the pixels representing the red (R), the green (G), and the blue (B) are grouped into one pixel group, the polarities of the pixel groups neighboring in the row direction are different and the polarities of the pixel groups neighboring in the column direction are also different, thereby realizing dot inversion.

Next, a structure for supplying a voltage to an edge portion of the liquid crystal display, particularly the voltage line178, will be described with reference toFIG. 14andFIG. 15, as well asFIG. 1.

FIG. 14is a layout view of an edge portion of a liquid crystal display according to an exemplary embodiment of the present invention, andFIG. 15is a cross-sectional view of the liquid crystal display ofFIG. 14taken along the line XV-XV.

The liquid crystal display whose cross-sectional edge portion is shown inFIG. 14andFIG. 15is similar to the liquid crystal display according to the exemplary embodiment shown inFIG. 9andFIG. 10.

Referring to the lower panel100, a first common voltage line137aand a second common voltage line137bare formed on the insulation substrate110. Referring toFIG. 1andFIG. 14, the first and second common voltage lines137aand137bextend in the row direction between the pixels PX300and the data driver500, and are both insulated from and cross the data line171. The first common voltage line137aand the second common voltage line137bmay transmit two different voltages, for example the highest driving voltage and the lowest driving voltage. Also, the voltages of the first and second common voltage lines137aand137bmay change by frame, and may oscillate.

A gate insulating layer140is formed on the first and the second common voltage line137aand137b. The gate insulating layer140includes a plurality of substantially uniformly arranged contact holes145athat expose a portion of the first common voltage line137a, and a plurality of substantially uniformly arranged contact holes145bthat expose a portion of the second common voltage line137b.

A voltage line178is disposed on the gate insulating layer140, and a semiconductor (not shown) having the same plane shape as the voltage line178may be formed between the gate insulating layer140and the voltage line178. Since the description thereof is the same as that of the above exemplary embodiment, it is omitted.

The voltage line178is alternately connected to the first common voltage line137aand the second common voltage line137bthrough the contact holes145aand the contact holes145bin a row direction, thereby receiving the voltage.

Alternatively, one of the first and second common voltage lines137aand137bmay be omitted, and in this case, all of the voltage lines178may be connected to one common voltage line. Also, the first and second common voltage lines137aand137bmay be formed from different layers than that of the present exemplary embodiment, for example, may be formed from the same layer as the data line171. In this case, the contact holes145aand145bof the gate insulating layer140are unnecessary, and the voltage line178may be directly connected to the first and second common voltage lines137aand137b.

A passivation layer180is formed on the voltage line178and the gate insulating layer140.

According to an exemplary embodiment of the present invention, a pixel voltage range capable of being used in the liquid crystal display may be increased without replacing the data driver, thereby increasing the transmittance. Also, the manufacturing cost of the driver may be reduced, and the aperture ratio of the display panel may be improved.

Also, according to an exemplary embodiment of the present invention, row inversion, column inversion, or dot inversion driving may be realized without inversion driving in the data driver.

While embodiments of this invention have been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that embodiments of the invention are not limited to the disclosed exemplary embodiments, but, on the contrary, are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.