Semiconductor package and manufacturing method thereof

A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.

CROSS-REFERENCE TO THE RELATED APPLICATIONS

This application is based upon and claims priority to Korean Patent Application No. 10-2019-0116092, filed on Sep. 20, 2019; the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof.

BACKGROUND

In general, semiconductor packages are manufactured by performing a semiconductor packaging process on semiconductor chips manufactured by performing various semiconductor processes on a wafer. Recently, in order to reduce the manufacturing costs of the semiconductor packages, a wafer-level packaging technique is proposed in which the semiconductor packaging process is performed at a wafer level, and a wafer-level semiconductor package subjected to the semiconductor packaging process is individualized into individual units.

Meanwhile, as illustrated inFIG. 1, the semiconductor package is mounted on a board through external connection terminals protruding from an outside of the semiconductor package.

However, the semiconductor package may be exposed to physical impact or the like during operation or during manufacturing or may be exposed to various shocks such as thermal shock or the like that may be applied due to heat generation and cooling.

Further, when heat generated during operation is accumulated, problems such as operation failures, malfunctions, or the like may occur, and electromagnetic interference (EMI) generated during operation may cause nearby devices to malfunction.

SUMMARY

The present disclosure is directed to providing a semiconductor package having a structure resistant to physical impact, thermal shock, or the like and a manufacturing method thereof.

The present disclosure is also directed to providing a semiconductor package capable of dissipating heat and shielding electromagnetic interference (EMI) and a manufacturing method thereof.

It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

According to an aspect of the present disclosure, there is provided a semiconductor package including a chip having a contact pad provided on one surface thereof, a buffer layer formed on one surface of the chip, one or more wiring patterns which are disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip, and a mold layer which is formed to surround a side surface of the chip, formed to be higher than a corner of one surface of the chip, and formed up to the other surface of the wiring pattern.

The semiconductor package may further include an insulating layer formed on an outside of the buffer layer so as to cover the buffer layer and the wiring pattern.

The insulating layer and the mold layer may be formed of materials having coefficients of thermal expansion whose difference is in a range of 0 to 25 ppm/° C.

The insulating layer and the mold layer may be in direct contact with each other in at least some sections.

The semiconductor package may further include an external connection terminal configured to transmit an electrical signal to an external device, an external pad provided on the insulating layer and having the external connection terminal disposed thereon, and a conductive via formed between the external pad and the wiring pattern.

A height of the insulating layer may be in a range of 10 to 50 μm.

The conductive via may have a height corresponding to 0 to 95% of a height of the insulating layer.

Each of the insulating layer and the mold layer may be formed of a non-photosensitive material.

Each of the insulating layer and the mold layer may include a filler, and a diameter of the filler may be less than or equal to ¼ times a thickness of the insulating layer.

The insulating layer and the mold layer may be drilled by a laser, and each of a portion of the insulating layer and a portion of the mold layer, which are drilled by the laser, may be formed to have an inclined side surface so that an inner diameter thereof is gradually decreased toward an inside thereof.

An object to be exposed, which is exposed by being drilled, may be over-etched by the laser, and a range in which the object to be exposed is over-etched may be between 0.01% and 30% of a thickness of the object to be exposed.

The semiconductor package may include the mold layer formed to surround the other surface and the side surface of the chip.

The semiconductor package may include a metal shielding layer formed on the other surface of the chip, which is a surface opposite to one surface of the chip, and the other surface of the mold layer.

The semiconductor package may include a metal shielding layer of a metal material formed to surround the other surface and a side surface of the mold layer, and a side surface of the insulating layer.

An oxide passivation layer may be formed on the wiring pattern.

The semiconductor package may further include an embedded ground portion, which is formed inside the mold layer, and includes one side electrically connected to a ground electrode among the plurality of wiring patterns and the other side electrically connected to the metal shielding layer.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor package, and the method includes a first carrier attaching operation of forming a buffer layer on one surface of a chip, on which a contact pad is formed, and attaching the buffer layer of the chip to a first carrier, a mold layer forming operation of forming a mold layer so as to surround the other side surface and a side surface of the chip to which the first carrier is attached, and a side surface of the buffer layer, a second carrier attaching operation of turning over the chip on which the mold layer is formed and attaching the other surface of the chip to a second carrier, a disposing operation of disposing one or more wiring patterns, which are electrically connected to the contact pad of the chip and extended to an outside of the chip, on one surface of the buffer layer, an insulating layer forming operation of forming an insulating layer on one side of the wiring pattern, an exposing operation of removing a portion of the insulating layer so that a portion of the wiring pattern is exposed, and a build-up operation of disposing an external pad and an external connection terminal in the exposed wiring pattern.

The exposing operation may be an operation of exposing the wiring pattern by removing a portion of the insulating layer through a polishing operation.

The exposing operation may be an operation of exposing the wiring pattern by drilling a portion of the insulating layer through a laser.

In the first carrier attaching operation, an embedded ground portion extending in one side direction and the other side direction may be further disposed on the first carrier, and the method may further include a grinding operation, which is performed before the second carrier attaching operation, of grinding the other surface of the mold layer formed in the mold layer forming operation until the other surface of the chip and the other end of the embedded ground portion are exposed so that the other surface of the mold layer is coplanar with the other surface of the chip and the other end of the embedded ground portion, and a metal shielding layer disposing operation of disposing a metal shielding layer to be in contact with the other surface of each of the chip and the mold layer and the other end of the embedded ground portion.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the exemplary embodiments for specifically realizing the objects of the present disclosure will be described with reference to the accompanying drawings. In describing the present embodiments, the same designations and reference numerals are used for the same components, and additional descriptions thereof will be omitted.

As illustrated inFIG. 2, a semiconductor package100according to one embodiment of the present disclosure may include a chip110, a buffer layer130, wiring patterns140, an insulating layer150, an external pad160, an external connection terminal170, and a mold layer180.

The chip110may include various types of one or a plurality of individual devices as a semiconductor device. For example, the plurality of individual devices may include microelectronic devices, complementary metal-oxide semiconductor (CMOS) transistors, metal-oxide semiconductor field effect transistors (MOSFETs), system large scale integration (LSI) devices, optoelectronic devices such as CMOS imaging sensors (CISs), microelectromechanical systems (MEMS), bulk acoustic wave (BAW) filter devices, active devices, passive devices, and the like, but the present disclosure is not limited thereto.

The chip110may be a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static RAM (SRAM), or a nonvolatile memory semiconductor chip such as a phase-change RANI (PRAM), a magneto-resistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM), but the present disclosure is not limited thereto.

The chip110may be a logic chip. For example, the logic chip may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP), but the present disclosure is not limited thereto.

InFIG. 2, the chip110is illustrated as being a single semiconductor device chip but is not limited thereto and may include a plurality of semiconductor devices, and the plurality of semiconductor devices may be semiconductor devices of the same type or different types.

In addition, the semiconductor package100may be a system-in-package (SiP) in which different types of semiconductor device chips are electrically connected to each other to operate as a single system.

A contact pad120may be formed on one surface of the chip110. InFIG. 2, a surface facing an upper side may be one surface, and a surface facing a lower side opposite to the upper side may be the other surface. In the following descriptions, a surface or an end in a direction in which the contact pad120is formed on the chip110is referred to as one surface or one end, and a surface or an end in a direction opposite to one surface or one end is referred to as the other surface or the other end.

The contact pad120may perform a role of a passage through which the chip110is electrically connected to various types of individual devices formed on the chip110and may transmit input or output signals of the chip110. The contact pad120may be made of a non-resistive metal such as aluminum or copper, but the present disclosure is not limited thereto. In addition, it is illustrated in the drawing that there are two contact pads120, but the present disclosure is not limited to the number of contact pads120.

The buffer layer130may be formed on one surface of the chip110, may be formed of a non-conductive material to prevent an unnecessary electrical short circuit, and may protect one surface of the chip110.

The wiring pattern140may be disposed on the buffer layer130, may be formed of a conductive material to be electrically connected to the contact pad120of the chip, and may be formed to extend to an outside of the chip110in a lateral direction.

Since the wiring pattern140may be formed of a conductive material to be electrically connected to the contact pad120, a path through which the chip is electrically connected to an external device or a substrate may be formed.

The wiring pattern140may be disposed on an upper side of the buffer layer130and may extend toward a side surface of the chip110and may be electrically connected to the contact pad by forming a notch protruding toward the contact pad at a point corresponding to the contact pad120of the chip110and being in contact with the contact pad while passing through the buffer layer. The wiring pattern may be made of tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof, and the present disclosure is not limited thereto as the material of the wiring pattern140.

The insulating layer150may be formed on an outside of the buffer layer130and may be formed to cover the buffer layer130and the wiring pattern140.

Accordingly, the wiring pattern140may be covered by the buffer layer130and the insulating layer150and thus may be protected from physical or chemical damage.

The buffer layer130and the insulating layer150may be made of an insulating polymer, an epoxy, a silicon oxide film, a silicon nitride film, an insulating polymer, or a combination thereof. Alternatively, the buffer layer130and the insulating layer150may each be made of a non-photosensitive material or a photosensitive material. For example, the insulating polymer may include general-purpose polymers such as polymethyl methacrylate (PMMA), polystyrene (PS), polybenzoxazole (PBO), and the like, acrylic-based polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinylalcohol-based polymers, polymer derivatives having a phenol-based group, or a combination thereof.

Further, the buffer layer130and the insulating layer150may be made of different materials. For example, one of the buffer layer130and the insulating layer150may be made of a non-photosensitive material, for example, non-photosensitive polyimide, and the other one thereof may be made of a photosensitive material such as photosensitive polyimide. Alternatively, the buffer layer130and the insulating layer150may be made of the same material.

Of course, the material of each of the buffer layer130and the insulating layer150is not limited to those described above and may include more various materials.

Further, a height (thickness) of the insulating layer150may be in a range of 10 to 50 μm and, preferably, may be 30 μm±3 μm.

The external pad160may be provided on the insulating layer150and may function as a pad on which the external connection terminal170is disposed. The external pad160may be electrically connected to the wiring pattern140and may be electrically connected to the contact pad120of the chip through the wiring pattern140.

To this end, the external pad160may form a wetting layer having an excellent wettability to allow the external connection terminal170to be properly adhered thereto.

For example, the external pad160may be an under bump metal (UBM) layer and may include a metal material such as Cu, Al, chromium (Cr), W, Ni, Ti, gold (Au), silver (Ag), or a combination thereof having excellent conductivity, but the present disclosure is not limited thereto.

Alternatively, as illustrated on a right side ofFIG. 2, a conductive via142may be formed between the external pad160and the wiring pattern140. The conductive via142may be provided to electrically connect the external pad160to the wiring pattern140. In addition, the conductive via142may be formed of a single layer or may also be formed of a plurality of layers made of different materials.

By providing the conductive via142as described above, the insulating layer150may be formed to have a greater thickness. That is, since the conductive via142is provided between the external pad160and the wiring pattern140, it is possible to electrically connect the external pad160to the wiring pattern140even when the insulating layer150is formed to have a greater thickness so that difficulty in electrically connecting the external pad160to the wiring pattern140may be eliminated. Accordingly, since the insulating layer150may be formed to be thicker, the effect of protecting the chip110may be increased, thereby improving reliability.

For example, the conductive via142may be formed to have a height corresponding to a range of 0 to 95% of the height (thickness) of the insulating layer150. As one example, the height of the conductive via142may be in a range of 10 to 47 μm and may preferably be in a range of 24±5 μm.

The external connection terminal170is a terminal which transmits an electrical signal from the semiconductor package100to an external device such as a substrate and may be collapsed and bonded on the external pad160. The external connection terminal170may be electrically connected to the chip through the wiring pattern140and may electrically connect the semiconductor package100to an external device (e.g., a board or the like).

That is, the external connection terminal170may be a connection terminal for mounting the semiconductor package100on a board such as a printed circuit board, which is an external device.

The external connection terminal170may include a solder bump and may include tin (Sn), Au, Ag, Ni, indium (In), bismuth (Bi), antimony (Sb), Cu, zinc (Zn), lead (Pb), or a combination thereof, but the present disclosure is not limited thereto. In addition, the solder bump may be formed in a ball shape but may be formed in various shapes such as, but not limited to, a cylinder, a polygonal column, a polyhedron, or the like.

Meanwhile, the mold layer180may be formed to surround the other surface and the side surface of the chip110and a side surface of the buffer layer130. The mold layer180may be formed up to a lower side surface of the wiring pattern140and may be formed to be in contact with the insulating layer150to protect the chip, the buffer layer130, and the wiring pattern140.

That is, the mold layer180may be formed to be higher than one surface of the chip110and may be formed to be at the same height as the buffer layer130so as to be coplanar with the buffer layer130. Accordingly, corner portions of the chip110are surrounded and covered by the mold layer180and the buffer layer130, and thus the chip110may be protected by the load and impact applied from the outside, thereby enhancing impact resistance.

Accordingly, the side surface of each of the chip110and the buffer layer130and the wiring pattern is surrounded by the mold layer180, thereby protecting the chip110, the buffer layer130, and the wiring pattern140from physical or chemical damage.

The mold layer180may be formed of an epoxy of a non-conductive material but is not necessarily limited thereto and may be formed of various materials such as an insulating polymer.

For example, the mold layer180may be formed of the same material or a material having the same physical properties as the insulating layer150. At this point, the same physical properties may mean the same coefficient of thermal expansion. Accordingly, since coefficients of thermal expansion (CTE) of the mold layer180and the insulating layer150are the same, the semiconductor package100is prevented from being bent or distorted due to heat generated by the chip110. Of course, the mold layer180and the insulating layer150may be formed of materials having coefficients of thermal expansion whose difference is in a range of 0 to 25 ppm/° C.

In addition, the insulating layer150and the mold layer180may be in direct contact with each other in at least some sections. Here, the insulating layer150and the mold layer180have the same physical properties and thus may have better mutual adhesion than a case when the insulating layer150and the mold layer180have materials of different physical properties. In this case, as illustrated inFIG. 2, the wiring pattern140is disposed between the insulating layer150and the mold layer180, and since the insulating layer150and the mold layer180are firmly adhered to upper and lower sides of the wiring pattern140, respectively, the wiring pattern140may also be firmly fixed.

Meanwhile, generally, photosensitive materials tend to have poor wettability or adhesion with metal materials, and non-photosensitive materials tend to have excellent wettability or adhesion with metal materials. Accordingly, when the insulating layer150and the mold layer180are formed of a non-photosensitive material, the insulating layer150and the mold layer180may have excellent adhesion with the wiring pattern140that is a metal material, and thus the wiring pattern140may be more reliably fixed.

Meanwhile, as necessary, the buffer layer130may not be disposed, and the wiring pattern140may be disposed directly on one surface of the chip110. Alternatively, the buffer layer130may be formed to have a thickness greater than that of the mold layer180. In this case, the wiring pattern may be formed on one surface of the chip in a shape bent upward.

Here, the non-photosensitive material for forming the insulating layer150and the mold layer180may have fillers mixed therein for various reasons, and the filler mixed in the insulating layer150and the filler included in the mold layer180may be the same type or different types. In addition, filler particles mixed in the insulating layer150and filler particles included in the mold layer180may have the same size and diameter or may have different sizes and diameters. Of course, as described above, distortion may occur due to the difference in thermal deformation when the difference in physical properties of the insulating layer150and the mold layer180is great, and thus, in order to lower the difference in physical properties, the fillers may be blended such that the difference between the size and diameter of the filler mixed in the insulating layer150and the size and diameter of the filler included in the mold layer180is not great. In this case, the filler mixed in the insulating layer150and the filler included in the mold layer180may have the same diameter or different diameters.

The filler is a particle having a diameter less than the thickness of the corresponding insulating layer and may increase CTE of the corresponding insulating layer, thereby improving effective CTE of each of the insulating layer150and the mold layer180. That is, the filler may be a material having a CTE greater than a CTE of a main insulating material constituting the corresponding insulating layer. For example, the filler may have a diameter of less than or equal to about ¼ of a thickness of the corresponding insulating layer and may have a diameter in a range of about 0.1 to 10 μm, but the present disclosure is not limited thereto. Preferably, the filler may have a diameter of 5 μm or less. However, when the filler has a diameter greater than the corresponding limitation, the filler may cause a surface of the corresponding insulating layer to have a plurality of recessed structures that are too uneven, and thus properties such as surface adhesion of the corresponding insulating layer may be degraded. For example, the filler may include silica (SiO2) or the like, but the present disclosure is not limited thereto.

Meanwhile, in order to electrically connect the external pad160to the external connection terminal170, a portion of the insulating layer150covered on an upper side of the wiring pattern140needs to be etched to expose the wiring pattern140. In general, when the insulating layer150is formed of a photosensitive material, the insulating layer150may be formed by an etching method using a photoresist or the like. However, when the insulating layer150is formed of a non-photosensitive material, the insulating layer150may be physically cut out and polished or drilled or may be drilled using a laser or the like.

In this case, as illustrated inFIG. 3, in the case of drilling using a laser, a side surface154of a drilled portion152may be formed to be inclined such that a width of the drilled portion152becomes narrower inward.

Accordingly, the insulating layer150made of a non-photosensitive material is etched by being irradiated with a laser to expose the wiring pattern140which is an object to be exposed.

Here, the object to be exposed refers to an object exposed to the outside through etching, polishing, or drilling and may be the wiring pattern140, the chip110, or the like that is buried in the insulating layer150or the mold layer180. In addition, other components buried in the insulating layer150or the mold layer180may also be the object to be exposed that needs to be exposed through drilling, polishing, or the like as necessary.

In addition, in the case of drilling using a laser, a portion of the wiring pattern140, which is the object to be exposed that needs to be exposed, may also be drilled to form an over-etched region144.

The over-etched region144is formed in the object to be exposed because, when drilling is performed with the laser, residue may remain on a surface of the object to be exposed if drilling is performed up to an interface region of the object to be exposed. Thus, when the over-etched region144is formed by etching slightly further than the interface of the object to be exposed, the concern of remaining residue may be excluded.

A range (a depth d) in which the over-etched region144thus formed is over-etched may be between 0.01% and 30% of a thickness D of the object to be exposed. Of course, such a range may be adjusted as necessary. In the present embodiment, the depth at which the over-etched region144is over-etched is illustrated as being 2 to 3 μm, but the present disclosure is not limited thereto.

Hereinafter, a semiconductor package200according to a second embodiment of the present disclosure will be described.

As illustrated inFIG. 4, the semiconductor package200according to the present embodiment may include a chip210, a buffer layer230, wiring patterns240, an insulating layer250, an external pad260, an external connection terminal270, a mold layer280, and a metal heat dissipating pad290.

The chip210, the buffer layer230, the wiring patterns240, the insulating layer250, the external pad260, and the external connection terminal270are substantially identical or similar to the chip110, the buffer layer130, the wiring patterns140, the insulating layer150, the external pad160, and the external connection terminal170of the first embodiment described above, and thus detailed descriptions thereof will be omitted.

Meanwhile, the above-described mold layer180according to the first embodiment is formed to surround the other surface and the side surface of the chip110and the side surface of the buffer layer130, but the mold layer280of the present embodiment may have a portion corresponding to the other surface of the chip210that is open.

In addition, the metal heat dissipating pad290may be provided to be in contact with the other surface of the chip210. Further, the metal heat dissipating pad290may be formed to be exposed to an outside of the other surface of the mold layer280.

As a result, by providing the metal heat dissipating pad290, heat generated from the chip110may be conducted to the metal heat dissipating pad290and dissipated to the outside.

The above-described metal heat dissipating pad290may be formed of a material having excellent thermal conductivity, such as aluminum, copper, stainless steel, or the like, and any material with excellent thermal conductivity may be applicable to the metal heat dissipating pad290even though the material is not necessarily metal.

Hereinafter, a semiconductor package300according to a third embodiment of the present disclosure will be described.

As illustrated inFIG. 5, the semiconductor package300according to the present embodiment may include a chip310, a buffer layer330, wiring patterns340, an external connection terminal370, and a mold layer380.

The chip310, the buffer layer330, and the mold layer380are substantially similar or identical to the chip110, the buffer layer130, and the mold layer180of the first embodiment described above, and thus detailed descriptions thereof will be omitted.

Meanwhile, in the semiconductor package100of the first embodiment described above, the insulating layer150is provided to cover the wiring pattern140, but in the semiconductor package300of the present embodiment, instead of the insulating layer150, an oxide passivation layer350may be formed on a surface of the wiring pattern340.

Since the oxide passivation layer350is formed on the surface of the wiring pattern340, the wiring pattern340may be protected from being corroded or the like even when the insulating layer150is not formed.

In addition, since the insulating layer150is not formed, the external pad160is not necessarily required, and it is also possible that the external connection terminal370is directly formed on the wiring pattern340.

Further, since the oxide passivation layer350is formed on the surface of the wiring pattern340, a separate passivation layer for protecting the surface of the wiring pattern340does not need to be formed, and thus the wiring pattern may have a smaller thickness.

Further, in order to form the robust oxide passivation layer350, a roughening process for increasing surface roughness of the wiring pattern340may be performed before the oxide passivation layer350is formed.

Hereinafter, a semiconductor package400according to a fourth embodiment of the present disclosure will be described.

As illustrated inFIG. 6, the semiconductor package400according to the present embodiment may include a chip410, a buffer layer430, wiring patterns440, an insulating layer450, an external pad460, an external connection terminal470, a mold layer480, and a shield layer490.

Here, the chip410, the buffer layer430, the insulating layer450, the external pad460, and the external connection terminal470are substantially similar or identical to the chip110, the buffer layer130, the insulating layer150, the external pad160, and the external connection terminal170of the first embodiment described above, and thus detailed descriptions thereof will be omitted.

Meanwhile, the above-described mold layer180according to the first embodiment is formed to surround the other surface and the side surface of the chip110and the side surface of the buffer layer130, but the mold layer480of the present embodiment may be formed to have a portion corresponding to the other surface of the chip410that is open and to surround a side surface of each of the chip410and the buffer layer430. In addition, the other surface of the mold layer480may be formed to be coplanar with the other surface of the chip410.

In addition, the shield layer490may be formed of a metal material having thermal conductivity, electrical conductivity, and electromagnetic interference (EMI) shielding properties and may be formed to surround the other surface and a side surface of the mold layer480and a side surface of the insulating layer450. At this point, the shield layer490may be provided to be in contact with the other surface of the chip410.

In addition, a wiring pattern442, among the plurality of wiring patterns440provided in the chip410, in charge of grounding may extend longer to a lateral surface and may be electrically connected to the shield layer490by being in contact therewith and thus achieve grounding.

Accordingly, the shield layer490may perform a role of a heat sink configured to dissipate heat generated from the chip410to the outside and may perform a function of shielding EMI generated from the chip410or introduced from the outside as well as a grounding function.

Further, the outside of the semiconductor package400may be finished with a metal material so that the semiconductor package400may be more effectively protected from physical impact and chemical impact.

The shield layer490may be formed of a metal material such as aluminum, copper, stainless steel, and the like having excellent heat dissipation properties, but the present disclosure is not limited thereto, and any material having excellent thermal conductivity and EMI shielding properties may be applicable to the shield layer490.

Hereinafter, a semiconductor package500according to a fifth embodiment of the present disclosure will be described.

As illustrated inFIG. 7, the semiconductor package500according to the present embodiment may include a chip510, a buffer layer530, wiring patterns540, an insulating layer550, an external pad560, an external connection terminal570, a mold layer580, an embedded ground portion595, and a metal shielding layer590.

The chip510, the buffer layer530, the wiring patterns540, the insulating layer550, the external pad560, and the external connection terminal570are substantially identical or similar to the chip110, the buffer layer130, the wiring patterns140, the insulating layer150, the external pad160, and the external connection terminal170of the first embodiment described above, and thus detailed descriptions thereof will be omitted.

Meanwhile, the above-described mold layer180according to the first embodiment is formed to surround the other surface and the side surface of the chip110and the side surface of the buffer layer130, but the mold layer580of the present embodiment may be formed to have a portion corresponding to the other surface of the chip510that is open and to surround a side surface of each of the chip510and the buffer layer530. In addition, the other surface of the mold layer580may be formed to be coplanar with the other surface of the chip510.

The embedded ground portion595may be formed inside the mold layer580.

The embedded ground portion595may be formed inside the mold layer580, and one side of the embedded ground portion595may be electrically connected to the wiring pattern540in charge of grounding among the plurality of wiring patterns540and the other side thereof may extend toward the other surface of the mold layer580.

The embedded ground portion595may be formed as one embedded ground portion or may be formed as a plurality.

Meanwhile, the other end of the embedded ground portion595described above may extend toward the other surface of the mold layer580to be coplanar with the other surface of the mold layer580.

In addition, the metal shielding layer590may be provided. The metal shielding layer590may be formed to be in contact with the other surface of the chip510and the other end of the embedded ground portion595.

Accordingly, the metal shielding layer590may perform a role of a heat sink configured to dissipate heat generated from the chip510to the outside and may perform a function of shielding EMI generated from the chip510and EMI introduced from the outside as well as a grounding function.

In addition, a package-on-package (POP) structure may be formed by being stacked with other semiconductor packages through the metal shielding layer.

Hereinafter, a method of manufacturing the above-described semiconductor package100according to the first embodiment of the present disclosure will be described with reference toFIGS. 8 to 18.

As illustrated inFIG. 8, the method of manufacturing the semiconductor package according to the present embodiment may include a first carrier attaching operation (S110), a mold layer forming operation (S120), a second carrier attaching operation (S130), a disposing operation (S140), an insulating layer forming operation (S150), an exposing operation (S160), and a build-up operation (S170).

The first carrier attaching operation (S110) is an operation of forming a buffer layer130on one surface of a chip110, as illustrated inFIGS. 9A and 9B, and turning the chip110over such that the buffer layer130faces downward and then attaching the buffer layer130on a first carrier50as illustrated inFIGS. 10A and 10B.

Here, after the buffer layer130is formed, a back-grinding process may be performed on the other surface of the chip110.

As illustrated inFIG. 10A, the first carrier50may be formed as a flat plate, and an adhesive surface52, to which a structure such as the chip110may be temporarily attached, may be formed on the first carrier50.

In the present operation, as illustrated inFIG. 10B, the chip110may be disposed to be in contact with an upper surface of the first carrier50in a state in which the buffer layer130faces the first carrier50. The buffer layer130may also be adhered to the adhesive surface52of the first carrier50so that the position thereof may be temporarily fixed.

As illustrated inFIG. 11, the mold layer forming operation (S120) is an operation of forming a mold layer180on an upper side of the chip110disposed above the first carrier50. As the mold layer forming operation (S120) is performed, the other surface of the chip110may be buried in the mold layer180.

As illustrated inFIG. 12, the second carrier attaching operation (S130) is an operation of turning over the chip110on which the mold layer180is formed and attaching the other surface of the chip110to a second carrier60. At this point, the first carrier50may be removed, and the second carrier60may be disposed on the other surface of the mold layer180to support the other surface of the mold layer180.

The second carrier60may also be formed as a flat plate, and an adhesive surface62, to which a structure such as the mold layer180may be temporarily attached, may be formed on an upper surface of the second carrier60.

In addition, the disposing operation (S140) may be performed as illustrated inFIG. 13. In the disposing operation (S140), one or more wiring patterns140, which are electrically connected to the contact pad120of the chip110and extend to an outside of the chip110, may be disposed on one surface of the buffer layer130.

Here, a conductive via142may be formed on one surface of the wiring pattern140. The conductive via142may be formed so that an external pad to be described below and the wiring pattern140are electrically connected to each other. Of course, the conductive via142may be formed or may not be formed as necessary.

In addition, the insulating layer forming operation (S150) is an operation of forming an insulating layer150on one side of the wiring pattern140as illustrated inFIG. 14.

After the insulating layer150is formed, the exposing operation (S160) may be performed as illustrated inFIG. 15. The exposing operation (S160) is an operation of removing a portion of the insulating layer150so that a portion of the wiring pattern140buried in the insulating layer150or a portion of the conductive via142is exposed. As illustrated inFIG. 15, the exposing operation (S160) may be performed through a mechanical polishing or etching operation (S162) so that the wiring pattern140or the conductive via142is exposed.

Meanwhile, the exposing operation (S160) may be performed through a drilling operation using a laser (S164).

That is, as illustrated inFIG. 16, after the insulating layer forming operation (S150) of forming the insulating layer150on one side of the wiring pattern140is performed, a drilled portion152exposing the wiring pattern140may be formed by drilling a portion of the insulating layer150using a laser as illustrated inFIG. 17. In general, the use of a laser allows more freedom in drilling depth compared to mechanical polishing, and thus it may not be necessary to form a separate conductive via142. Of course, the present disclosure is not limited thereto, and laser drilling may be performed while forming the conductive via142. In addition, deep drilling is enabled by using the laser so that the insulating layer150may be formed to be thicker, and accordingly, a portion protecting the chip110may be thicker, thereby improving durability and reliability.

After the exposing operation (S160), as illustrated inFIG. 18, the build-up operation (S170) of disposing an external pad160and an external connection terminal170on the exposed wiring pattern140may be performed.

Hereinafter, a method of manufacturing the above-described semiconductor package500according to the fifth embodiment of the present disclosure will be described with reference toFIGS. 19 to 24.

As illustrated inFIG. 19, the method of manufacturing the semiconductor package according to the present embodiment may include a first carrier attaching operation (S210), a mold layer forming operation (S220), a grinding operation (S225), a second carrier attaching operation (S230), a disposing operation (S240), an insulating layer forming operation (S250), an exposing operation (S260), a build-up operation (S270), and a metal shielding layer disposing operation (S280).

The first carrier attaching operation (S210) is an operation of forming a buffer layer530on one surface of a chip510, as illustrated inFIGS. 9A and 9B, and turning the chip510over such that the buffer layer530faces downward and then attaching the buffer layer530on a first carrier50as illustrated inFIGS. 20A and 20B.

Here, after the buffer layer530is formed, a back-grinding process may be performed on the other surface of the chip510.

As illustrated inFIG. 20A, the first carrier50may be formed as a flat plate, and an adhesive surface52, to which a structure such as the chip510may be temporarily attached, may be formed on the first carrier50.

In the first carrier attaching operation (S210), an embedded ground portion595may be formed on an upper side surface of the first carrier50as illustrated inFIG. 20A. The first carrier50may be formed as a flat plate, and an adhesive surface52, to which a structure such as the embedded ground portion595may be temporarily attached, may be formed on an upper surface of the first carrier50. The embedded ground portion595may be formed on the upper side surface of the first carrier50.

Further, as illustrated inFIG. 20B, the chip510may be disposed to be in contact with the adhesive surface52of the first carrier50in a state in which the buffer layer530faces the first carrier50. The buffer layer530may also be adhered to the adhesive surface52of the first carrier50so that the position thereof may be temporarily fixed.

As illustrated inFIG. 21, the mold layer forming operation (S220) is an operation of forming a mold layer580on an upper side and a side surface of each of the chip510and the embedded ground portion595that are disposed above the first carrier50. While the mold layer forming operation (S220) is being performed, the other surface of each of the chip510and the embedded ground portion595may be buried in the mold layer580.

In addition, the grinding operation (S225) may be performed. In the grinding operation (S225), as illustrated inFIG. 22, the other surface of the mold layer580may be ground and polished so that the other surface of the chip510or the other end of the embedded ground portion595is exposed.

Here, in the grinding operation (S225) of the present embodiment, the other surface of the mold layer580may be polished such that the other surface of the mold layer580is coplanar with the other surface of the chip510and the other end of the embedded ground portion595.

As illustrated inFIG. 23, the second carrier attaching operation (S230) is an operation of turning over the chip510and the embedded ground portion595, on which the mold layer580is formed, and attaching the other surface of each of the chip510and the embedded ground portion595to a second carrier60. At this point, the first carrier50may be removed, and the second carrier60may be disposed on the other surface of the mold layer580to support the other surface of the mold layer580and the other end of the embedded ground portion595.

The second carrier60may also be formed as a flat plate, and an adhesive surface62, to which a structure such as the mold layer580may be temporarily attached, may be formed on an upper surface of the second carrier60.

In addition, the insulating layer forming operation (S250), the exposing operation (S260), and the build-up operation (S270) may be performed. The insulating layer forming operation (S250), the exposing operation (S260), and the build-up operation (S270) are substantially similar to the insulating layer forming operation (S150), the exposing operation (S160), and the build-up operation (S170), which are described above in the manufacturing method of the first embodiment, and thus detailed descriptions thereof will be omitted. An insulating layer550, an external pad560, and an external connection terminal570may be disposed through the insulating layer forming operation (S250), the exposing operation (S260), and the build-up operation (S270).

In addition, the metal shielding layer disposing operation (S280) is performed to provide a metal shielding layer590on the other surface of the mold layer580, on which the grinding operation is performed, as illustrated inFIG. 24. At this point, since the other surface of the mold layer580is coplanar with the other surface of the chip510and the other end of the embedded ground portion595, the metal shielding layer590may also be planar.

Here, the metal shielding layer590may be provided to be in contact with the other surface of each of the chip510and the mold layer580and the other end of the embedded ground portion595. Thus, heat may be rapidly discharged since the metal shielding layer590is in contact with the chip510, and a ground line may be formed since the metal shielding layer590is in contact with the other end of the embedded ground portion595.

Hereinafter, a semiconductor package600according to a sixth embodiment of the present disclosure will be described.

As illustrated inFIGS. 25 and 26, the semiconductor package600according to the present embodiment may include a chip610, a buffer layer630, wiring patterns640, an insulating layer650, an external pad660, an external connection terminal670, a mold layer680, an embedded ground portion695, and a metal shielding layer690, and these components may be substantially similar to the chip510, the buffer layer530, the wiring patterns540, the insulating layer550, the external pad560, the external connection terminal570, the mold layer580, the embedded ground portion595, and the metal shielding layer590of the fifth embodiment described above.

However, in the above-described embodiment, the other surface of the mold layer580, the other surface of the chip510, and the other end of the embedded ground portion595are polished in the grinding operation (S225) to be coplanar with each other, and the metal shielding layer590is also planar, but according to the present embodiment, the other surface of the mold layer680, the other surface of the chip610, and the other end of the embedded ground portion695are not coplanar with each other, and the metal shielding layer690is also not planar and may be formed in a shape that is bent several times.

In the above-described embodiment, the other surface of the mold layer580, the other surface of the chip, and the other end of the embedded ground portion595are ground to be coplanar with each other, but in the present embodiment, as illustrated inFIG. 25, portions of the other surface of the mold layer680corresponding to the chip and the embedded ground portion695may be drilled so that the other surface of the chip610and the other end of the embedded ground portion695are exposed.

In this case, a laser may be used as a drilling means. However, the present disclosure is not limited thereto, and drilling may be performed using other known drilling means.

Here, the drilled portion is formed in a tapered shape such that a width thereof is gradually increased in a direction toward the other surface of the mold layer680and gradually decreased in a direction toward an inside of the mold layer680.

Accordingly, the other surface of the mold layer680, the other surface of the chip610, and the other surface of the embedded ground portion695may not be coplanar with each other and may form steps with different heights, and the other surface of the chip610and the other surface of the embedded ground portion695may be located further inward than the other surface of the mold layer680.

At this point, the other surface of the embedded ground portion695, which is an object to be exposed by being drilled and exposed by a laser, may be over-etched as described above and may be over-etched in a range (depth) of 2 to 3 μm. Of course, the over-etching may be deeper or thinner than this range.

Accordingly, the metal shielding layer690provided on the other surface of the mold layer680may have a shape that is bent several times rather than a flat surface. That is, portions corresponding to the other surface of the chip610and the other end of the embedded ground portion695, which are formed so as to form steps with the mold layer680, may be formed by being bent several times to be in contact with the other surface of the chip610and the other end of the embedded ground portion695. When the metal shielding layer690has a shape that is bent several times, a surface area thereof may increase, which may be more advantageous for heat dissipation.

Hereinafter, a semiconductor package700according to a seventh embodiment of the present disclosure will be described.

As illustrated inFIG. 27, the semiconductor package700according to the present embodiment may include a chip710, a buffer layer730, wiring patterns740, an insulating layer750, an external pad760, an external connection terminal770, a mold layer780, an embedded ground portion795, and a metal shielding layer790, and these components may be substantially similar to the chip610, the buffer layer630, the wiring patterns640, the insulating layer650, the external pad660, the external connection terminal670, the mold layer680, the embedded ground portion695, and the metal shielding layer690of the sixth embodiment described above.

However, in the above-described embodiment, portions of the other surface of the mold layer680corresponding to the chip610and the embedded ground portion695are drilled, but in the present embodiment, a portion of the other surface of the mold layer780corresponding to the chip710may be subjected to a polishing operation to be coplanar with the other surface of the mold layer780, and a portion of the other surface of the mold layer780corresponding to the embedded ground portion795may be drilled using a laser and thus the drilling may be performed only on the corresponding portion.

That is, when the other end of the embedded ground portion795is located inside the mold layer780more than the other surface of the chip710, the other surface of the mold layer780may be ground to expose the other surface of the chip710. At this point, the other surface of the mold layer780may be coplanar with the other surface of the chip710.

Afterward, the portion of the other surface of the mold layer780corresponding to the embedded ground portion795is drilled by performing a laser drilling process or the like to expose the other end of the embedded ground portion795.

In addition, the metal shielding layer790may be provided on the other surface of the mold layer780, in which the grinding operation has been performed.

At this point, the other surface of the mold layer780and the other surface of the chip710may be coplanar with each other, and the other end of the embedded ground portion795may be located further inward than the other surface of the mold layer780.

Accordingly, in the metal shielding layer790, a portion in contact with the other surface of the mold layer780may be coplanar with a portion in contact with the other surface of the chip710, and a portion in contact with the embedded ground portion795may be stepped.

Hereinafter, a semiconductor package800according to an eighth embodiment of the present disclosure will be described.

As illustrated inFIG. 28, the semiconductor package800according to the present embodiment may include a chip810, a buffer layer830, wiring patterns840, an insulating layer850, an external pad860, an external connection terminal870, a mold layer880, an embedded ground portion895, and a metal shielding layer890, and these components may be substantially similar to the chip710, the buffer layer730, the wiring patterns740, the insulating layer750, the external pad760, the external connection terminal770, the mold layer780, the embedded ground portion795, and the metal shielding layer790of the seventh embodiment described above.

However, in the above-described embodiment, the metal shielding layer790is formed to be bent several times to be in contact with the other surface of the chip710or the other end of the embedded ground portion795, which is formed to be stepped from the other surface of the mold layer780, but in the present embodiment, a portion of the metal shielding layer890corresponding to the other surface of the chip810or the other end of the embedded ground portion895, which is formed to be stepped from the other surface of the mold layer880, may be formed to be thicker, and the other surface of the metal shielding layer890may be formed to be planar.

A semiconductor package and a manufacturing method thereof have the following effects.

First, a mold layer is formed on a circumference of a chip so that it is possible to provide a semiconductor package having a structure resistant to external impact, thermal shock, or the like.

Second, a metal heat dissipating pad, a shield layer of a metal material, or a metal shielding layer is provided on the other surface of the chip or the mold layer to dissipate heat generated during operation so that thermal stability can be improved, and the metal shielding layer capable of shielding electromagnetic interference (EMI) is provided so that operation stability can also be improved.

Third, an insulating layer and the mold layer surrounding one surface and the other surface of the chip are formed of materials having the same physical properties so that distortion due to thermal deformation caused by heat generated from the chip can be minimized.

Fourth, wiring patterns are provided between the insulating layer and the mold layer that are formed of the same physical properties and the same material to provide excellent adhesion between the insulating layer and the mold layer so that a fixing force of the wiring patterns can be improved.

Fifth, the materials of the insulating layer and the mold layer include a non-photosensitive material having excellent adhesion to metal so that a fixing force for fixing the wiring patterns disposed between the insulating layer and the mold layer can be improved.

Sixth, in drilling the insulating layer and the mold layer made of a non-photosensitive material using a laser, an over-etched region, in which a portion of an object to be exposed is also etched, is formed to reduce the possibility of foreign substances remaining on a surface of the object to be exposed so that the possibility of electrical contact failure can be minimized.

It should be noted that advantageous effects of the present disclosure are not limited to the above-described effects, and other effects that are not described herein will be apparent to those skilled in the art from the following descriptions.

The exemplary embodiments of the present disclosure have been examined as described above, and it will be clear to those skilled in the art that the present disclosure will be realized into a different specific form without departing from the spirit or scope of the present disclosure other than the above-described embodiments. Accordingly, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation, and the present disclosure is not limited to the above description and may also be changed within the scope of the appended claims and all equivalents falling within the scope.