Apparatus for buffered transmission of data

An apparatus with a data input, a data output, a first buffer, a second buffer, and control logic is disclosed. The control logic is equipped to route data packets that are received through the data input to the first buffer or the second buffer and to flag them as valid or invalid, and to provide data packets that are to be output through the data output from the first buffer or the second buffer, equipped to provide a data packet that is to be output through the data output from the first buffer when the data packet is being written into the first buffer at the time of a start of the readout, to provide it from the second buffer when the data packet is being written into the second buffer at the time of a start of the readout.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an apparatus for the buffered transmission of data. In particular, the present invention relates to an apparatus with two data buffers (hereinafter referred to as buffers) and with control logic that controls write and read accesses to the buffers

Description of the Background Art

Apparatuses for buffered transmission of data that have three buffers are known from the prior art. Said apparatuses keep one buffer available for writing data and one buffer for reading out data, while the third buffer serves for transmission of data between the ports.

SUMMARY OF THE INVENTION

The invention improves on the prior art inasmuch as the apparatuses and method according to the invention allow a transmission between a transmitter and a receiver in which only two buffers are required, wherein the transmitter can nevertheless write data into the apparatus at any time.

An apparatus according to an exemplary embodiment of the invention includes a data input, a data output, a first buffer, a second buffer, and control logic, wherein the control logic is equipped to route data packets that are received through the data input to the first buffer or the second buffer and to flag them as valid or invalid, and to provide data packets that are to be output through the data output from the first buffer or the second buffer, wherein the control logic is furthermore equipped to provide a data packet that is to be output through the data output from the first buffer when the data packet is being written into the first buffer at the time of a start of the readout, to provide the data packet from the second buffer when the data packet is being written into the second buffer at the time of the start of the readout, and to provide the data packet from the buffer that has the newest valid data packet when no data packet is being written into the buffers at the start of the readout.

Here, the term “data input” as used in the description and the claims can be understood to mean, in particular, a communication connection through which data can be transmitted to the apparatus. The communication connection can be, e.g., an electrically conductive connection by means of which current and/or voltage levels representing data can be supplied to the apparatus. Furthermore, the term “data output” as used in the description and the claims can be understood to mean, in particular, a communication connection through which the data can be output by the apparatus. The communication connection can be, e.g., an electrically conductive connection by means of which current and/or voltage levels representing data can be output by the apparatus.

In addition, the term “buffer” as used in the description and the claims can be understood to mean, in particular, a memory element (component) or an addressable region in a memory element (component). This means that a distinction between buffers can relate both to a logical distinction, e.g. with regard to addressable regions in a memory element (component, e.g., “DP-RAM Page 1, DP-RAM Page 2”), and to a distinction with regard to the memory elements (components) involved. Furthermore, the term “control logic” as used in the description and the claims can be understood to mean, in particular, a circuit that is equipped to control the apparatus, and in particular to choose the buffer from which a data packet is to be provided and the buffer into which a data packet is to be written, starting from an analysis of the state of the apparatus or of the read and/or write requests (“read/write requests”) made to the apparatus.

In addition, the term “data packet” as used in the description and the claims can be understood to mean, in particular, binary coded information items that are transmitted/received in a block, wherein the information items typically share a context. Moreover, a data packet often has a defined structure that makes it possible to assign a binary coded information item to a corresponding section of the data packet. Moreover, the phrase “start of the readout” as used in the description and the claims can be understood to mean, in particular, a point in time immediately before the output of a first bit of a data packet to be provided.

The phrase “immediately before” can be understood here to mean that the point in time is nonetheless sufficiently in advance of the output that the apparatus is able to make decisions with respect to the buffer from which the data packet is to be provided. Consequently, the point in time can be calculated, for example, by subtracting the time required by the control logic for deciding which buffer is to provide the data packet from the point in time when a first bit is actually output.

In addition, the terms “valid” and “invalid” as used in the description and the claims relate, in particular, to the correctness of data packets (or to the correctness of the data packet content). An incorrect data packet is, for example, a data packet in which a write error has occurred during writing into the buffer (and that consequently deviates in an erroneous way from an appropriate data packet in form and/or in content), or a data packet that was written correctly into the buffer but contains incorrect information (on account of a previous error).

An apparatus according to the invention thus allows a continuous flow of data from the transmitter (data source) to the receiver (data consumer) in that data packets are written into the two buffers and are provided from the two buffers in alternation.

The apparatus can be used, e.g., as a 2-buffer FIFO in automation engineering, where it can be implemented in a transceiver. The transceiver can be used, for example, for forwarding process data from a field bus to a local bus (e.g., in a bus coupler or a bus controller). The process data can be written into the 2-buffer FIFO in the form of data packets/data blocks (fixed length). In this case, the control logic can monitor that the data exactly correspond to a previously configured data block length.

Once the data have been written into the FIFO, the data can be flagged as “valid” or as “invalid” by the transmitter. Moreover, the transmitter can declare the data invalid even during the writing process. With a “valid” signal, in contrast, the transmitter can communicate that the provided data are valid. In the event of an error, the receiver can, moreover, be supplied with data from the other buffer in order to obtain the last valid data. It is possible, furthermore, to provide a data packet while the data packet is being written into the buffer.

Preferably, the control logic is equipped to flag a data packet as invalid if, while the data packet is being provided from one of the buffers, writing of a data packet into one of the buffers is begun.

As a result, it is possible to ensure, for example, that the newest data packet at the time is always provided, wherein the data packet can be available or an availability can be imminent.

Preferably, the control logic is equipped to flag a data packet as invalid if, while a data packet is being provided from a buffer, a part of the data packet that is still to be read out is overwritten.

Consequently, errors can be detected that arise when the write operation takes place faster than the read operation.

Preferably, the control logic is equipped to generate a read error signal when a data packet is read out that is flagged as invalid during or after the writing of the data packet.

Consequently, the transmission of data packets that are invalid or no longer current can be avoided. The read error signal thus indicates whether a data packet currently being read out is valid or not.

Preferably, the control logic is equipped to provide the data packet that is to be output through the data output from the buffer that was last written if no data packet is being written into the address areas at the start of the readout and the data packet written into the last-written buffer is flagged as valid.

Consequently, it is ensured that the most current (valid) data packet is always transmitted to the receiver.

The control logic can be equipped to continue providing the same newest valid data packet until a newer valid data packet is available.

The last valid data can thus be output (or read out) multiple times until newer valid data are written into the FIFO. As a result, it is possible to ensure that the receiver can be continuously supplied with data that are valid (in the error-free case).

The control logic can be equipped to generate an overflow signal when a valid data packet is overwritten without having been read out.

The control logic can be equipped to generate an underflow signal when a valid data packet is read out more than once.

The apparatus can be integrated into a system (e.g., an automation system) that has a transmitter (e.g., a sensor) and a receiver (e.g., a central control unit) in order to provide a continuous flow of data packets transmitted in a buffered manner from the transmitter.

The transmitter can be equipped to read back a data packet from the buffer that has the newest valid data packet and to write it into the apparatus again when the transmitter has no valid data packet that is more current, but is equipped to write a data packet into the apparatus at specific points in time.

A method according to the invention for transmission of data packets from a transmitter to a receiver by means of an apparatus having a first buffer and a second buffer and control logic comprises a writing of data packets into the first buffer or the second buffer and a flagging of the data packets as valid or invalid, and a readout of a data packet from the first buffer when the data packet is being written into the first buffer at the time of a start of the readout, and a readout of the data packet from the second buffer when the data packet is being written into the second buffer at the time of a start of the readout, and a readout of the data packet from the buffer that has the newest valid data packet when no data packet is being written into the buffers at the start of the readout.

The method additionally can include a generation of a read error signal if, while a data packet is being read out from one of the buffers, writing of a data packet into one of the buffers is begun.

The method additionally can include a generation of a read error signal if a data packet is read out that is flagged as invalid during or after the writing of the data packet.

The method additionally can include a generation of an overflow signal if a valid data packet is overwritten without having been read out.

The method additionally can include a generation of an underflow signal if a valid data packet is read out more than once.

The method additionally can include a generation of an empty signal if no buffer has a valid data packet.

The method additionally can include a readback by the transmitter of a data packet and a repeated writing of the read-back data packet into a buffer when the transmitter has no valid data packet that is more current, but is equipped to write a data packet into the apparatus at specific points in time.

DETAILED DESCRIPTION

An.FIG.1shows an apparatus10according to the invention in accordance with an exemplary embodiment. The apparatus10includes a data input12and a data output14. The apparatus10is connected to a transmitter16(data producer) through the data input12. At regular intervals, the transmitter16generates data packets that are to be transmitted to a receiver18(data consumer). The receiver18is connected to the data output14of the apparatus10, and requests data packets at regular intervals or reads data packets out from the apparatus10at regular intervals.

The apparatus10additionally includes a first buffer20, a second buffer22, and control logic24. The control logic24is equipped to route data packets that are received through the data input12to the first buffer20or the second buffer22. For this purpose, the control logic24can establish a data connection between the data input12and the first buffer20or a data connection between the data input12and the second buffer22by means of a first changeover switch26. Consequently, data packets received through the data input12are written into the first buffer20or into the second buffer22as a function of the setting of the first changeover switch26.

The control logic24is furthermore equipped to flag data packets written into the first buffer20or second buffer22as valid or as invalid. The flagging of a data packet as valid or invalid can be based on a signal of the transmitter16, for example when the transmitter16signals that a data packet is erroneous. For this purpose, the transmitter16can be connected to the control logic24through a first control line28, and the control logic24can, during the writing of a data packet or after the completion of the writing of the data packet, indicate whether the data packet or the written part of the data packet is valid or invalid. The transmitter16, moreover, can notify the control logic24through the first control line28of a write access to the apparatus10or indicate a completion of a write access.

The control logic24is additionally equipped to provide data packets that are to be output through the data output from the first buffer20or the second buffer22. For this purpose, the control logic24can establish a data connection between the first buffer20and the data output14or a data connection between the second buffer22and the data output14by means of a second changeover switch30. Consequently, data packets output through the data output14are read out from the first buffer20or from the second buffer22as a function of the setting of the second changeover switch30. Moreover, the same data packet can be provided repeatedly in succession as long as no newer (valid) data packet is being written into the apparatus10.

The receiver18can be connected to the control logic24through a second control line32. As a result, the control logic24can indicate to the receiver18during readout of a data packet or after the completion of readout of the data packet whether the data packet or the part of the data packet that has been read out is valid or invalid. Moreover, the receiver18can notify the control logic24through the second control line32of a read access to the apparatus10or indicate a completion of a read access. The control logic24can furthermore track which buffer20,22has been written with a valid data packet and how old the data packets stored in the buffers20,22are.

FIG.2illustrates a state of the apparatus10shown inFIG.1in which neither write nor read accesses are taking place. Here, the first buffer20contains a first data packet and the second buffer22contains a second data packet. The control logic24determines which of the data packets is valid. If only one of the data packets is valid, the apparatus10provides this data packet to the receiver18. If both data packets are valid, the apparatus10provides the newer of the two valid data packets (i.e., the data packet with the newer time stamp t1>t0) to the receiver18. If both data packets were to be invalid, this would be signaled to the receiver18or neither of the two data packets would be provided to the receiver18.

If, as shown inFIG.3, a request is made by the receiver18and if no new data packet is being written into the apparatus10at the time of the readout, the apparatus10provides the newest valid data packet (i.e., the data packet with the newer time stamp t1>t0) to the receiver18. In contrast, if a data packet that has a newer time stamp t2>t1is being written into the apparatus10at the time of the request by the receiver18, as shown inFIG.4, then this packet is provided to the receiver18. The provision can be aborted if the data packet written into the first buffer20is flagged as invalid. The data packet written into the first buffer20can be flagged as invalid, moreover, if the receiver18in reading out a data packet gets ahead of the transmitter16in writing the data packet and as a result the risk exists that an inconsistent data packet will be provided to the receiver18.

The control logic24is thus equipped to provide a data packet, which is to be output through the data output14, from the first buffer20when the data packet is being written into the first buffer20at the time of a start of the readout, and to provide the data packet from the second buffer22when the data packet is being written into the second buffer22at the time of the start of the readout. If no data packet is being written into the buffers20,22at the start of the readout, the data packet is provided from the buffer20,22that has the newest valid data packet.

If, while the newest valid data packet is being read out from the second buffer22(as inFIG.3) or from the first buffer20(as inFIG.4), a newer (valid) data packet is being written into the other respective buffer20,22, the read-out data packet can be flagged as invalid. If the read-out data packet is flagged as invalid, the readout operation can be aborted and the receiver18can (immediately or at a next readout time) read out the (now newest) data packet from the other respective buffer20,22. Alternatively, the receiver18can continue the readout operation and discard the read-out data packet.

Instead of flagging a (stale) data packet as invalid, the control logic24can also flag the data packet as stale, by which means the receiver18can be informed that the data packet is valid but stale. The receiver18can then abort the readout of the data packet now flagged as stale and (immediately or at a next readout time) read out the (newer) data packet from the other respective buffer20,22. Instead of aborting the readout, the receiver18can also read out in its entirety a data packet that is flagged (as invalid and/or stale) and discard the read-out data packet or forward it flagged as invalid. This can be advisable when, for example, an aborting of the readout would generate a read error that would have to be overcome by clearing the buffers20,22.

As shown inFIG.5, a data packet can be read back from a buffer20,22by the transmitter16. For example, the transmitter16can extract an information item from the read-back data packet and transmit this information item in a data packet that is to be written to the apparatus10(or replace an information item in the data packet with the extracted information item). In this way, an information item (e.g., a value such as a measured value) can be kept constant in a series of data packets (e.g., on request, for example “hold-last-value”). The readback in this case can take place during a readout of the buffer20,22as well as when no data packet is being read out of the buffer20,22. Moreover, it is possible, as shown inFIG.6, for the transmitter16to read back a data packet from one buffer20,22while the transmitter16is writing a data packet into the other buffer20,22. During the readback, moreover, an arbitrary buffer20,22(preferably the one written with the newest valid data packet) can be read out by the receiver18.

FIG.7illustrates an exemplary sequence of write and read accesses in the apparatus10. After a data packet has been written into one of the buffers20,22by the transmitter16, the receiver18begins readout of the data packet. Since the data packet was flagged as valid by the transmitter16, the apparatus10indicates to the receiver18at the time the readout is started (and beyond) that the read-out data packet is valid.

FIG.8illustrates an exemplary sequence of write and read accesses in which a data packet written into a buffer20,22is flagged as invalid (during or after the completion of the write operation). Since a valid data packet, which was provided, is present in the apparatus10, however, the validity signal can remain at “valid.”

FIG.9illustrates an exemplary sequence of write and read accesses in which a valid data packet is repeatedly read out until the transmitter16provides a newer valid data packet. Because a valid data packet that can be provided is present in the apparatus10at all times here as well, the validity signal can remain at “valid.”

FIG.10illustrates an exemplary sequence of write and read accesses in which the receiver18misses the opportunity to pick up a data packet. Since the most current valid data packet is always provided to the receiver18, the missed data packet is no longer delivered to the receiver and is lost.

FIG.11illustrates an exemplary sequence of write and read accesses in which write and read accesses overlap, reducing the transmission latency. If a data packet is flagged as invalid by the transmitter16, the receiver18can abort the readout of the data packet or, as shown inFIG.11, continue the readout and discard the read-out data packet. For this purpose, the receiver18can continuously evaluate the validity signal and discard a data packet if the validity signal indicates an invalid data packet during the readout of the data packet.

FIG.12illustrates an exemplary sequence of write and read accesses in which a write operation commences during a read operation. As a result of the commencing of the write operation during the read operation, the validity signal is set to “invalid” so that the receiver18aborts the readout operation or discards the read-out data packet.

FIG.13illustrates an exemplary sequence of write and read accesses that differs from the sequence shown inFIG.12in that the data packet is flagged as invalid by the transmitter16. As a result, the first data packet is read out again in the following read operation.

FIG.14illustrates an exemplary sequence of write and read accesses in which a write and a read access are started in the same clock cycle. In this case, the validity signal is set to “invalid” so that the receiver18aborts the readout operation or discards the read-out data packet.

FIG.15illustrates an exemplary sequence of write and read accesses in which a write access proceeds more slowly than a read access taking place in parallel (directed at the same data packet) so that the receiver18“gets ahead of” the transmitter16in the buffer access. In consequence, the validity signal is set to “invalid” so that the receiver18aborts the readout operation or discards the read-out data packet.

FIG.16illustrates an exemplary sequence of write and read accesses in which a read access proceeds more slowly than a write access taking place in parallel so that the transmitter16begins to write a new data packet while the receiver is still reading out an older data packet, so that the latter is now stale. In consequence, the validity signal is set to “invalid” so that the receiver18aborts the readout operation, discards the read-out data packet, or forwards it flagged as stale.

FIG.17illustrates an exemplary sequence of write and read accesses that differs from the sequence shown inFIG.16in that the data packet is flagged as invalid by the transmitter16. As a result, the first data packet is read out again in the following read operation.

FIG.18illustrates an exemplary sequence of write and read accesses in which a read access to empty buffers20,22takes place. Because the validity signal is set to “invalid,” the receiver18recognizes that the read-out data packet is to be discarded. After a first data packet has been written into a buffer20,22by the transmitter16, the apparatus10signals that it is no longer empty and a valid data packet can be provided.

FIG.19illustrates an exemplary sequence of write and read accesses that differs from the sequence shown inFIG.18in that the first data packet is flagged as invalid by the transmitter16. Therefore, the validity signal is set to “invalid” so that the receiver18aborts the readout operation or discards the read-out data packet.

FIG.20illustrates an exemplary sequence of write and read accesses that triggers an overflow signal. Here, a valid data packet is being written into a buffer20,22before a valid data packet written beforehand into the apparatus10has been read out. As indicated inFIG.20, the overflow can be signaled to the transmitter16and the receiver18at different times, for example to the transmitter16at the start of writing the valid data packet and to the receiver18during reading of the valid data packet.

FIG.21illustrates an exemplary sequence of write and read accesses that differs from the sequence shown inFIG.20in that the receiver18attempts to read out the data packet, but the readout attempt fails. In this case, no overflow signal is triggered, even though the data packet cannot be read out successfully.

FIG.22illustrates an exemplary sequence of write and read accesses that differs from the sequence shown inFIG.20in that a data packet is written into the apparatus, but this packet is flagged as invalid so that the skipped read access does not cause overwriting of a validly written data packet.

FIG.23illustrates an exemplary sequence of write and read accesses that triggers an underflow signal. Here, the same valid data packet is read out twice. As illustrated inFIG.24, the underflow signal is also triggered when the second readout of the same valid data packet is aborted or the formerly valid data packet is flagged as stale, and hence invalid, during the readout.

FIG.25illustrates a flowchart of a method for transmission of data packets from the transmitter16to the receiver18. In step34here, as explained in detail above, data packets are written into the buffers20,22and flagged as valid or invalid. At the time of the readout of a data packet, if the data packet is being written into one of the buffers20,22, then the data packet is read out of that buffer20,22in step36or38. However, if no data packet is being written into one of the buffers20,22at the time of the readout, then the data packet is read out of the buffer20,22that has the newest valid data packet. As a result, the transmitter16can write data into the apparatus10at any time and the receiver18can read data out of the apparatus10at any time.