Voltage boosting power supply circuit for monitoring charging voltage with predetermined voltage to detect boosted voltage, and boosted voltage control method

A power supply circuit of the present invention includes a voltage boosting capacitor, a first switch, a second switch, an addition comparison circuit, and a control circuit. The first switch charges the voltage boosting capacitor by applying a first voltage thereto. The second switch connects a second voltage serially to the voltage boosting capacitor that is already charged, thereby boosting the voltage therein. The addition comparison circuit adds up the voltage of the voltage boosting capacitor and the second voltage and compares the comparison result, with a predetermined threshold value. The control circuit controls the on/off state of the first switch according to the comparison result of the addition comparison circuit.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a voltage boosting power supply circuit and a boosted voltage control method, more particularly to a charge pump voltage boosting power supply circuit that employs a capacitor, as well as a boosted voltage control method.

2. Related Art

A charge pump power supply circuit is incorporated in each liquid crystal display panel driving IC (Integrated Circuit) employed for portable phones. This power supply circuit generates a panel driving voltage used for driving a liquid crystal display panel from a voltage (supply voltage) supplied from a battery or the like and supplies the generated voltage to the object driving IC. Many manufacturers are involved in portable phone markets and manufacturing various types of portable phones. Under such circumstances, such display panel driving ICs are required to have general-purpose properties and generate a predetermined driving voltage from any of various types of supply voltages without changing their settings.

Furthermore, such display panel driving ICs are also required to be reduced more in size to cope with liquid crystal display panels that are becoming narrower in frame width. And now that the picture quality is improved more and more due to an increase in the number of color tones, influences of the power supply circuit output voltage quality on picture quality cannot be ignored. This is why there has been a need of such a compact and high performance power supply circuit, that is, a compact power supply circuit that can prevent voltage falling to be caused by a load current. Consequently, chip sized and low voltage transistors favorable in performance have been used for those power supply circuits. The low voltage transistor has smaller on-resistance than the high voltage transistor when the same channel width is employed for both of the transistors. The use of such low voltage transistors, therefore, makes it possible to configure a low resistance switch smaller in size than a circuit that uses high voltage transistors.

Such a charge pump power supply circuit that generates a driving voltage from a supply voltage is disclosed in, for example, Japanese Patent Laid-Open Application No. 2005-20922. As shown inFIG. 1, this charge pump power supply circuit includes a voltage boosting circuit790, a control circuit780, a comparator773, and a smoothing capacitor799. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit790includes transistors (switches)791to794and a voltage boosting capacitor797. Each of the transistors791and793is a switch for applying a supply voltage VDC to the voltage boosting capacitor797, thereby charging the capacitor797. The transistor792is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor797that is already charged, thereby boosting the voltage of the capacitor797. The transistor794is a switch for supplying a boosted voltage to the load circuit as a boosted output VDC2.

The comparator773compares the charging voltage of the voltage boosting capacitor797with a reference voltage VR and outputs the comparison result to the control circuit780. The control circuit780includes an AND circuit781, a NAND circuit782, and a NOT circuit783. The control circuit780controls the on/off state of each of the transistors791to794of the voltage boosting circuit790.

The output of the voltage boosting circuit790is smoothed by the smoothing capacitor799and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the AND circuit781, the NAND circuit782, and the NOT circuit783of the control circuit780, etc.

Next, there will be described the operation of this power supply circuit. A voltage Va of a node a is compared with the reference voltage VR in the comparator773. The node a is connected to a terminal away far from the GND of the voltage boosting capacitor797, the drain terminal of the transistor793, and the source terminal of the transistor794respectively. The output of the comparator773becomes high when the voltage Va of the node a is lower than the reference voltage VR (Va<VR) and low when the voltage Va of the node a is higher than the reference voltage VR (Va≦VR).

When the level of the voltage boosting clock CLK is low, the gate level of each of the transistors792and794becomes high, so that those transistors are turned off. At this time, if the output level of the comparator773becomes high due to Va<VR, the level of the two inputs of the AND circuit781also becomes high. Consequently, the transistor791is turned on and the level of the two inputs of the NAND circuit782become high. Consequently, the transistor793is also turned on. At this time, the voltage Va of the node a is equal to the charging voltage VC of the voltage boosting capacitor797. Thus the supply voltage VDC is applied to the voltage boosting capacitor797, thereby the voltage boosting capacitor797is charged. In other words, while the level of the voltage boosting clock CLK is low and Va<VR is assumed, the voltage boosting capacitor797is kept charged in that period.

If the output level of the comparator773becomes low due to Va≧VR, that is, VC≦VR while the level of the voltage boosting clock CLK is low, the output of the AND781becomes low. As a result, the transistor791is turned off and the output level of the AND782becomes high, thereby the transistor793is also turned off. Consequently, the charging of the voltage boosting capacitor797stops. At this time, the voltage boosting capacitor797keeps the charging voltage as is without charging and discharging. The voltage boosting capacitor797is charged until the charging voltage VC becomes equal to the reference voltage VR.

When the level of the voltage boosting clock CLK is high, the level of the gates of the transistors792and794becomes low, so that those transistors792and794are turned on. At this time, the output level of the AND781becomes low, so that the transistor791is turned off and the output level of the NAND782becomes high, thereby the transistor793is turned off. Consequently, the connecting node between the voltage boosting capacitor797and the transistor791is applied the supply voltage VDC through the transistor792and the voltage Va of the node a is boosted to a value (VDC+VC) that is a sum of the supply voltage VDC and the charging voltage VC of the voltage boosting capacitor797. This boosted voltage is supplied to the smoothing capacitor799through the transistor794that is turned on, thereby the voltage VDC2=(VDC+VC) is supplied to the load circuit as an initial value. Consequently, while the level of the voltage boosting clock CLK is high, it is assumed as a boosted voltage output period.

In the above power supply circuit, the charging voltage VC can be set with reference to the reference voltage VR in such a way and the voltage VC never exceeds the reference voltage VR. However, as shown in the case of the output voltage VDC2=(VDC+VC) just after a boosted voltage output period is set, the output voltage VDC2is affected by a fluctuation of the supply voltage VDC. For example, when the supply voltage VDC is 3 volts, the reference voltage VR is set so as to obtain output voltage VDC2=5 volts. In an ideal case, the relationship between the supply voltage VDC and the output voltage VDC2becomes as shown inFIG. 2. When the supply voltage VDC is 3 volts, the output voltage VDC2is 5 volts. And if the reference voltage VDC falls, the output voltage VDC2also falls, resulting in insufficient voltage. On the other hand, if the supply voltage VDC rises, the output voltage VDC2also rises, thereby the element breakdown voltage might be exceeded. In other words, in the above power supply circuit, in order to keep the output voltage VDC2constantly, the reference voltage VR should be varied in accordance with the supply voltage VDC.

FIG. 3shows a circuit diagram of a charge pump power supply circuit disclosed in Japanese Patent Laid-Open Application No. 2005-278383. This power supply circuit includes a voltage boosting circuit890, a comparison circuit870, a control circuit880, and a smoothing capacitor899. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit890includes transistors (switches)891to894and a voltage boosting capacitor897. The transistors891and893are switches for applying a supply voltage VDC to the voltage boosting capacitor897, thereby charging the capacitor897. The transistor892is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor897that is already charged, thereby boosting the voltage of the capacitor897. The transistor894is a switch for supplying the boosted voltage to the load circuit as a boosted voltage output VDC2.

The comparison circuit870includes a comparator873and resistance elements871and872. Each of the resistance elements871and872divides the output voltage VDC2of the voltage boosting circuit890to generate a comparison voltage VCMP. The comparator873compares the comparison voltage VCMP with the reference voltage VR and outputs the comparison result VCTL to the control circuit880. The control circuit880includes a level shift circuit883, a NAND circuit881, and a NOT circuit882. The control circuit880controls the on/off state of each of the transistors891to894of the voltage boosting circuit890according to the comparison result VCTL output from the comparison circuit870and the voltage boosting clock CLK.

The output of the voltage boosting circuit890is smoothed by the smoothing capacitor899and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the NAND circuit881, the NOT circuit882, the level shift circuit883of the control circuit880, etc.

Next, there will be described the operation of this power supply circuit with reference toFIGS. 4A to 4D. When the level of the voltage boosting clock CLK is low (FIG. 4A), the output level of the NAND circuit881becomes high and the transistors891and893are turned on while the transistors892and894are turned off. Consequently, the supply voltage VDC is applied to the voltage boosting capacitor897, which is thus charged until the charging voltage VC becomes equal to the supply voltage VDC (FIG. 4B).

While the level of the voltage boosting clock CLK is high (FIG. 4A), if the level of the comparison result VCTL is high, the output of the NOT circuit882becomes high (FIG. 4D). And because the output voltage VDC2is discharged until it goes lower than the predetermined voltage V2(FIG. 4D), the output level of the comparison circuit870is high and the output level of the NAND circuit881is low. Consequently, the transistors891and893are turned off while the transistors892and894are turned on. In other words, the supply voltage VDC is applied to the connecting node between the voltage boosting capacitor897and the transistor891through the transistor892, thereby the voltage VC− of the connecting node is assumed as a voltage VDC as shown inFIG. 4C. Consequently, the voltage of the connecting node between the voltage boosting capacitor897and the transistor893is boosted by the same voltage as the supply voltage VDC. If the voltage of the voltage boosting capacitor897is assumed as VC, the voltage VC+ of the connecting node between the voltage boosting capacitor897and the transistor893becomes VDC+VC (FIG. 4B). The connecting node between the voltage boosting capacitor897and the transistor893is connected to the smoothing capacitor899through the transistor894and the voltage VDC2=(VDC+VC) is supplied to the connecting node. And because the charging voltage VC is kept charged until it becomes equal to the supply voltage VDC, the output voltage VDC2becomes double the voltage VDC instantaneously (FIG. 4D).

The comparator873compares the comparison voltage VCMP with the reference voltage VR. The VCMP is obtained by dividing the output voltage VDC2through any of the resistance elements871and872. The output level of the comparator873becomes high when the comparison voltage VCMP is lower than the reference voltage VR (VCMP<VR) and becomes low when the comparison voltage VCMP is higher than the reference voltage VR (VCMP≦VR). When the output level of the comparison circuit870is high, the output level of the NAND circuit881of the control circuit880becomes low, thereby the voltage boosting circuit890keeps discharging. If the output level of the comparison circuit870becomes low, the output level of the NAND circuit881becomes high, thereby the voltage boosting circuit890stops discharging.

When the state of the voltage boosting circuit890is switched from charging to discharging, the output voltage VDC2becomes double the VDC. Thus the output level of the comparison circuit870becomes low and the state of the voltage boosting circuit890is switched from discharging to charging. Consequently, the smoothing capacitor899is discharged and the output voltage VDC2falls gradually in accordance with the power consumption of the load circuit. If the comparison voltage VCMP obtained by dividing the output voltage VDC2becomes lower than the reference voltage VR, the output level of the comparison circuit870becomes high and the state of the voltage boosting circuit890is switched to discharging.

In this power supply circuit, the output voltage VDC2is controlled so that the comparison voltage VCMP obtained by dividing the VDC2is equalized to the reference voltage VR as described above. Consequently, this power supply circuit can keep the output voltage VDC2at a predetermined voltage V2without changing its setting regardless of the changes of the supply voltage VDC. However, the voltage boosting capacitor897is charged up to the supply voltage VDC during the charging period, so that the output voltage VDC2, as shown inFIG. 4D), goes over the predetermined voltage V2just after discharging and becomes about double the supply voltage VDC. In other words, an element to which the output voltage VDC2is supplied should be set at a high breakdown voltage so as to withstand the instantaneous output voltage VDC2. Rising of this instantaneous output voltage VDC2causes random noise generation. The output voltage VDC2, as shown inFIG. 5, is assumed as a power supply of a source driver and such noise affects the output of the source driver. And the fluctuation of the source driver causes horizontal stripes to appear on the screen, resulting in degradation of the display quality if the source driver output is not synchronized with the panel display frequency.

As described above, in a conventional power supply circuit, obtaining a predetermined output voltage from any of wide ranged supply voltages has been confronted with various problems. For example, it has been required to change settings in accordance with the supply voltage, noise is generated, and the element breakdown voltage is exceeded.

Under such circumstances, it is an exemplary feature of the present invention to provide a power supply circuit capable of obtaining a predetermined output voltage from any of wide ranged supply voltages without changing the settings.

SUMMARY OF THE DISCLOSURE

According to one exemplary aspect of the present invention, the voltage boosting power supply circuit includes a voltage boosting capacitor, a first switch, a second switch, an addition comparison circuit, and a control circuit. The first switch applies a first voltage to the voltage boosting capacitor, thereby charging the capacitor. The second switch connects a second voltage serially to the voltage boosting capacitor that is already charged, thereby boosting the voltage of the capacitor. The addition comparison circuit adds up the voltage of the voltage boosting capacitor that is being charged and the second voltage, then compares the addition result with a predetermined threshold value. The control circuit controls the on/off state of the first switch according to the comparison result of the addition comparison circuit. The first and second voltages may be the same voltage.

According to another exemplary aspect of the present invention, the boosted voltage control method includes a charging step, a voltage boosting step, an addition step, a comparison step, and a control step. In the charging step, a first voltage is applied to the voltage boosting capacitor to charge the capacitor. In the voltage boosting step, a second voltage is connected serially to the voltage boosting capacitor that is already charged to boost the voltage of the capacitor. In the addition step, the voltage of the voltage boosting capacitor that is being charged is added to the second voltage and the addition result is output. In the comparison step, the addition result is compared with a predetermined threshold value and the comparison result is output. And in the control step, charging of the voltage boosting capacitor stops according to the comparison result.

According to still another exemplary aspect of the present invention, the voltage boosting power supply circuit includes a voltage boosting capacitor, a first switch, a second switch, an addition comparison circuit, and a control circuit. The first switch applies a first voltage to the voltage boosting capacitor, thereby charging the capacitor. The second switch connects a second voltage serially to the voltage boosting capacitor that is already charged, thereby boosting the voltage of the capacitor. The addition comparison circuit adds up the voltage of the voltage boosting capacitor that is being charged and the second voltage, then compares the addition result with a predetermined threshold value. The control circuit controls the on/off state of the first switch according to the comparison result of the addition comparison circuit. The first and second voltages may be the same voltage.

According to still another exemplary aspect of the present invention, the boosted voltage control method includes a charging step, a voltage boosting step, an addition step, a comparison step, and a control step. In the charging step, a first voltage is applied to the voltage boosting capacitor through a resistance element to charge the capacitor. In the voltage boosting step, a second voltage is connected serially to the voltage boosting capacitor that is already charged to boost the voltage of the capacitor. In the addition step, the voltage of the voltage boosting capacitor that is being charged is added to the second voltage and the addition result is output. In the comparison step, the addition result is compared with a predetermined threshold value and the comparison result is output. And in the control step, charging of the voltage boosting capacitor stops according to the comparison result.

As described above, according to the present invention, it is possible to provide a power supply circuit capable of obtaining a predetermined output voltage from any of wide ranged supply voltages without changing the settings.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 6is a block diagram for showing a configuration of a liquid crystal display apparatus in an exemplary embodiment of the present invention. The liquid crystal display apparatus900includes a liquid crystal display panel901, a data side driving circuit.902, a scanning side driving circuit903, a power supply circuit904, and a display control circuit905.

The liquid crystal display panel901includes a plurality of data lines disposed horizontally and extended vertically, as well as a plurality of scanning lines907disposed vertically and extended horizontally. A pixel is formed at a cross point of a data line906and a scanning line907. Each pixel, in a single color as shown inFIG. 6, includes a TFT (Thin Film Transistor)908, a pixel capacity909, and a liquid crystal element910. The gate of the TFT908is connected to the scanning line907and the source (drain) thereof is connected to the data line906. The drain (source) of the TFT908is connected to the pixel capacity909and the liquid crystal element910respectively and the other ends of the pixel capacity909and the liquid crystal element910are connected to a common electrode COM respectively. The liquid crystal element910is a capacitive element. In this embodiment, it is premised that the combination of a pixel capacity909and a liquid crystal element910is referred to as a panel capacity. In the case of a multicolor liquid crystal display panel, each pixel is a set of R, G, and B dots and each dot includes a TFT908, a pixel capacity909, and a liquid crystal element910. The operations are basically the same among liquid crystal display panels.

The data side driving circuit902outputs an analog signal voltage (gradation voltage) generated in accordance with a digital image signal (hereinafter, to be referred to as data) to drive the data lines906. The scanning side driving circuit903outputs a TFT908selection/non-selection voltage to drive the scanning lines907. The power supply circuit904supplies a voltage to the data side driving circuit902for outputting the analog signal voltage and the scanning side driving circuit903for outputting the selection/non-selection voltage. The display control circuit905generates timing signals for driving the data lines906and the scanning lines907, as well as timing signals for controlling the voltage boosting of the power supply circuit904to control the scanning side driving circuit903, the data side driving circuit902, and the power supply circuit904. The display control circuit905supplies a display clock signal DCCLK to the power supply circuit904as a timing signal.

Next, there will be described a power supply circuit in a first embodiment with reference toFIG. 7. The power supply circuit, as shown inFIG. 7, includes a voltage boosting circuit10, an addition circuit60, a comparison circuit70, a control circuit80, a transfer gate40, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit10includes transistors11to14, and a voltage boosting capacitor21. The transistors11and13are switches for charging the voltage boosting capacitor21with a supply voltage VDC. The transistor12is a switch for connecting a supply voltage VDC serially to the voltage boosting capacitor21, thereby boosting the voltage of the capacitor21that is already charged. The transistor14is a switch for discharging the charge from the voltage boosting capacitor21with the boosted voltage. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40is a switch for extracting the voltage VC from the voltage boosting capacitor21that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61,62,64, and65. The addition circuit60adds up the voltage VC of the voltage boosting capacitor21extracted through the transfer gate40and the supply voltage VDC. The addition circuit60then outputs the addition result to the comparison circuit70. The comparison circuit70includes a comparator78, and resistance elements71and72. The comparison circuit70compares the output voltage of the addition circuit60with the reference voltage VREF and outputs the comparison result to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and a NOT circuit83and controls the on/off state of each transistor (switch) and the transfer gate40of the voltage boosting circuit10according to the comparison result of the comparison circuit70.

The output of the voltage boosting circuit10is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the NAND circuit81, the level shift circuit82, and the NOT circuit83of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this first embodiment with reference toFIGS. 8A to 8E.

The voltage boosting clock DCCLK is a clock signal synchronized with a display clock of the display device as shown inFIG. 8A. The power supply circuit operation is synchronized with this voltage boosting clock DCCLK.

When the level of the output VCTL of the comparison circuit70is high (FIG. 8B) and the level of the voltage boosting clock DCCLK is low, the state is assumed as shown on the left end inFIGS. 8A to 8E. And because the output level of the NOT circuit83is high and the output level of the NAND circuit81is low, the transistors11and13are turned on while the transistors12and14are turned off. Consequently, the voltage boosting capacitor21is supplied the supply voltage VDC through the transistors11and13, thereby charging is started for the capacitor21. As shown inFIG. 8C, the voltage VC+ of the connecting node between the voltage boosting capacitor21and the transistor13rises when this charging starts.

At this time, the transfer gate40is turned on and enables the voltage boosting capacitor21that is being charged to output its voltage VC to the addition circuit60. The addition circuit60adds the voltage VC that is charged and rises to the supply voltage VDC. In other words, the addition result comes to correspond to the voltage VC+ assumed when charging of the voltage boosting capacitor21starts. If the resistance value is equal between the resistance elements61and62and the resistance values of the resistance elements64and65are defined as R64and R65respectively, the output voltage VADD of the addition circuit60will be calculated as follows.
VADD=(1+R65/R64)·(VDC+VC)/2  (1)

The output voltage VADD of this addition circuit60is inputted to the comparison circuit70. In the comparison circuit70, the output voltage VADD is divided by each of the resistance elements71and72and the comparison circuit78compares each divided voltage VCMP with the reference voltage VREF. If the resistance values of the resistance elements71and72are defined as R71and R72respectively, the voltage VCMP will be calculated as follows.
VCMP=VADD·R72/(R71+R72)  (2)

The output level of the comparator78becomes high at VCMP<VREF and low at VCMP≧VREF. In other words, the comparison circuit70outputs a high level signal to the control circuit80as the comparison result VCTL when the charging voltage VC of the voltage boosting capacitor21is lower than a predetermined voltage V1. If the charging voltage exceeds the predetermined voltage V1as a result of charging, the output level of the comparison circuit70becomes low.

The control circuit80makes a level shift of the comparison result VCTL of the comparison circuit70through the level shift circuit82and outputs the result to the NAND circuit81. Because the output level of the NOT circuit83is high, the output level of the NAND circuit81becomes low when the level of the comparison result VCTL is high, thereby the transistor13is turned on. When the transistor13is turned on and the voltage boosting capacitor21is further charged, the level of the comparison result VCTL becomes low and the NAND circuit81outputs a high level signal to turn off the transistor13. Consequently, if the charging voltage VC of the voltage boosting capacitor21goes over the predetermined voltage V1, the transistor13is turned off and charging of the voltage boosting capacitor21stops. In such a way, when the level of the voltage boosting clock DCCLK is low, the voltage boosting circuit10is charged, thereby the voltage boosting capacitor21is charged up to the predetermined voltage V1.

When the level of the voltage boosting clock DCCLK becomes high, the output level of the NOT circuit83becomes low, thereby the output level of the NAND circuit81becomes high. Consequently, the transistors11and13are turned off while the transistors12and14are turned on. Then, the supply voltage VDC is supplied to the connecting node between the voltage boosting capacitor21and the transistor11through the transistor12. Consequently, the voltage V− of the connecting node between the voltage boosting capacitor21and the transistor11is boosted to the voltage VDC in a moment as shown inFIG. 8D. As a result, the voltage VC+ of the node connected to the transistor13is boosted to the voltage V2from the voltage V1as shown inFIG. 8C. At the same time, the connecting node between the voltage boosting capacitor21and the transistor13is connected to the smoothing capacitor90through the transistor14, thereby the smoothing capacitor90is charged. In other words, the voltage VDC2=(VC+VDC) is supplied to the load circuit through the smoothing capacitor90.

Because the voltage boosting circuit10supplies a voltage to the load circuit while charging the smoothing capacitor90, the output voltage VDC2begins falling before it rises to the voltage V2as shown inFIG. 8E. At this time, the transfer gate40is turned off while the addition circuit60keeps the same state. Thus the charge in the voltage boosting capacitor21is moved to the smoothing capacitor90and the load circuit, so that the output voltage VDC2falls gradually. The voltage boosting capacitor21is discharged and its voltage VC falls gradually as shown inFIG. 8C. In such a way, when the voltage boosting clock DCCLK is on the high level, the voltage boosting circuit is discharged.

As described above, while the power supply circuit is operating, in order to enable the initial voltage of the output voltage VDC2to reach a desired voltage value V2, the voltage boosting capacitor21should be charged until the voltage VC reaches the voltage value V1in a charging period. At this time, it is just required that the capacitor21is charged up to the voltage VC so as to satisfy VDC+VC=V2and the comparison circuit70stops charging of the voltage boosting capacitor21. In other words, it is just required to satisfy VCMP=VREF here. Those operations are substituted for the formulas (1) and (2) described above as follows.
(1+R65/R64)·V2/2=VREF·(R71+R72)/R72  (3)

In order to satisfy the formula (3), the R64, R65, R71, and R72are set, thereby the voltage boosting capacitor21is charged up to the voltage V1so as to enable the initial output voltage VDC2to reach the desired voltage value V2. For example, if R64=R65and R71=R72are assumed, V2=2. VREF is assumed and the output voltage is set double the reference voltage. Consequently, at this time, it is just required to set the reference voltage VREF at ½ of the desired voltage value V2. And the voltage VC of the voltage boosting capacitor21is never charged over the desired voltage value V2when the charging starts. And because a sum of the charging voltage VC and the supply voltage VDC that are added up in the addition circuit60is to be compared, the charging voltage VC of the voltage boosting capacitor21never exceeds the predetermined voltage value V2upon starting the discharging even when the supply voltage VDC changes.

FIG. 9shows another configuration of each of the addition circuit60and the comparison circuit70. A charging voltage VC and a supply voltage VDC are connected to the input of the operation amplifier (comparator) through the resistance elements, thereby the addition circuit60and the comparison circuit70are united into one. In principle, even such a circuit can operate, but a combination of the addition circuit60and the comparison circuit70as shown inFIG. 7is more preferable.

As described above, the charging voltage VC of the voltage boosting capacitor21is adjusted to satisfy VC+VDC=V2with use of the addition circuit60, the comparison circuit70, and the control circuit80. Consequently, although the charging voltage VC is varied by power consumption, the output voltage VDC2is kept constantly (V2) regardless of the changes of the supply voltage VDC. For example, in the power supply circuit in which the supply voltage VDC is set at 3.0 volts and the output voltage VDC2is set at 5.0 volts, the relationship between supply voltage VDC and output voltage VDC2becomes as shown inFIG. 10.

This is why the power supply circuit can use any of wide ranged supply voltages (from low to high voltages) without changing its settings. And because the target voltage value V2of the output voltage VDC2is set under the element breakdown voltage, the element breakdown voltage is never exceeded. Furthermore, because the supply voltage VDC is connected to the voltage boosting capacitor21during a charging period, the discharging cycle is synchronized with the display clock as shown inFIG. 8E. No noise is thus generated in boosted voltage outputs and no horizontal stripes appear on the screen. Therefore, the display quality is prevented from degradation.

FIG. 11shows a circuit diagram of a power supply circuit in a second embodiment of the present invention. This power supply circuit includes a voltage boosting circuit100, an addition circuit60, a comparison circuit70, a control circuit180, transfer gates140and240, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit100includes a first voltage boosting circuit that includes transistors111to114and a voltage boosting capacitor121, as well as a second voltage boosting circuit that includes transistors211to214and a voltage boosting capacitor221. The first and second voltage boosting circuits are the same in both configuration and operation as the voltage boosting circuit10described in the first embodiment.

In the first voltage boosting circuit, the transistor111and113are switches for charging the voltage boosting capacitor121with a supply voltage VDC. The transistors112and114are switches for boosting the charge in the voltage boosting capacitor121with the supply voltage VDC, then discharging the charge, thereby supplying an output voltage VDC2to the smoothing capacitor90. The transfer gate140includes two transistors and a NOT circuit. The transfer gate140functions as a switch for extracting the voltage VC1from the voltage boosting capacitor121that is being charged.

In the second voltage boosting circuit, the transistor211and213are switches for charging the voltage boosting capacitor221with the supply voltage VDC. The transistors212and214are switches for boosting the charge in the voltage boosting capacitor221with the supply voltage VDC, then discharging the charge, thereby supplying the output voltage VDC2to the smoothing capacitor90. The transfer gate240includes two transistors and a NOT circuit. The transfer gate240functions as a switch for extracting the voltage VC2from the voltage boosting capacitor221that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65. While the transfer gate140is turned on, the addition circuit60adds up the voltage of the voltage boosting capacitor121extracted through the transfer gate140and the supply voltage VDC and outputs the addition result. While the transfer gate240is on, the addition circuit60adds up the voltage of the voltage boosting capacitor221extracted through the transfer gate240and the supply voltage VDC and outputs the addition result. The comparison circuit70includes a comparator78and resistance elements71and72. The comparison circuit70compares the output voltage of the addition circuit with a reference voltage VREF and outputs the comparison result to the control circuit180.

The control circuit180includes NAND circuits181and281, level shift circuits182and282, AND circuits186and286, and NOT circuits183and283. The control circuit180controls the on/off state of each of the transistors (switches) and the transfer gates140and240of the voltage boosting circuit100. The AND circuits186and286, as well as the NOT circuit187, synchronously with the voltage boosting clock DCCLK, controls so that the first and second voltage boosting circuits repeat charging period and voltage boosting period alternately and outputs the comparison result between charging periods to the corresponding NAND circuits181and281, respectively.

The output of the voltage boosting circuit100is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the NAND circuits181and281, the level shift circuits182and282, the NOT circuit183of the control circuit180, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this second embodiment.

At first, the output level of the comparison circuit70is assumed to be high. And, when the level of the voltage boosting clock DCCLK is low, the NOT circuit183outputs a high level signal, thereby the transistor111is turned on and the transistors112and114are turned off. Then, the output level of the NOT circuit187becomes high, so that the AND circuit186outputs a high level signal and the NAND circuit181outputs a low level signal, thereby the transistor113is turned on. Consequently, the voltage VC+ of the connecting node between the voltage boosting capacitor21and the transistor13rises at the start of a charging period.

At this time, the transfer gate140is on and outputs the voltage VC1of the voltage boosting capacitor21that is being charged to the addition circuit60. At this time, the transfer gate240is off and the addition circuit60adds the voltage VC1that is charged and risen to the supply voltage VDC. Thus the addition result comes to correspond to the voltage VC+ when the voltage boosting capacitor121begins discharging.

The addition result of the addition circuit60is inputted to the comparison circuit70. In the comparison circuit70, each of the resistance elements divides the addition result and the comparator78compares each divided voltage VCMP with a reference voltage VREF. The comparison circuit70outputs a high level signal to the control circuit80as the comparison result when the charging voltage of the voltage boosting capacitor121is lower than the predetermined voltage value V1. When the charging voltage exceeds the predetermined voltage value V1as a result of charging, the comparison circuit70outputs a low level signal.

When the level of the comparison result becomes low, the AND circuit186of the control circuit180outputs a low level signal. The output of the AND circuit is subjected to a level shift in the level shift circuit182and the result is inputted to the NAND circuit181. The NAND circuit181outputs a high level signal, thereby the transistor113is turned off. Consequently, when the charging voltage VC1of the voltage boosting capacitor121exceeds the predetermined voltage V1, the transistor113is turned off, thereby the charging of the voltage boosting capacitor181stops.

On the other hand, in the voltage boosting circuit, the level of the voltage boosting clock CDCLK is low, so that the NAND circuit281outputs a high level signal. Thus the transistors211and213are turned off and the transistors212and214are turned on. Consequently, the supply voltage VDC is supplied to the connection node between the voltage boosting capacitor221and the transistor211through the transistor212while the connecting node between the voltage boosting capacitor221and the transistor213is connected to the smoothing capacitor90through the transistor214and supplies the output voltage VDC2. In other words, the second voltage boosting circuit is discharged while the level of the voltage boosting clock DCCLK is low.

When the level of the voltage boosting clock CDCLK is high, the NOT circuit183outputs a low level signal and the NAND circuit181outputs a high level signal. In the first voltage boosting circuit, therefore, the transistors111and113are turned off and the transistors112and114are turned on. At this time, the supply voltage VDC is supplied to the connecting node between the voltage boosting capacitor121and the transistor111through the transistor112while the connecting node between the voltage boosting capacitor221and the transistor is connected to the smoothing capacitor90through the transistor114and supplies the output voltage VDC2. In other words, the first voltage boosting circuit is switched to discharging.

On the other hand, in the second voltage boosting circuit, while the comparison circuit70outputs a high level signal and the AND circuit286also outputs a high level signal and the NAND circuit281outputs a low level signal. Thus the transistors211and213are turned on and the transistors212and214are turned off. Consequently, the voltage boosting capacitor221is charged with the supply voltage VDC. At this time, the transfer gate is on, so that the voltage VC2of the voltage boosting capacitor221is supplied to the addition circuit60through the transfer gate240. Furthermore, because the transfer gate140is off, the addition circuit60adds up the voltage VC2of the voltage boosting capacitor221and the supply voltage VDC. Each of the resistance elements71and72divides the output voltage of the addition circuit60, then the comparison circuit70compares each divided voltage VCMP with the reference voltage VREF.

The comparison circuit70outputs a high level signal as the comparison result when the level of the voltage VC2of the voltage boosting capacitor221is lower than the predetermined voltage V1and outputs a low level signal when the voltage VC2exceeds the predetermined voltage. When the comparison circuit70outputs a low level signal, the AND circuit of the control circuit180outputs a low level signal and the NAND circuit281thereof outputs a high level signal respectively. Consequently, the transistor213is turned off, thereby the charging of the voltage boosting capacitor221stops.

In such a way, the first voltage boosting circuit assumes a period during which the level of the voltage boosting clock DCLK is low as a charging period and a period during which the level of the voltage boosting clock DCCLK is high as a boosted voltage output period. The second voltage boosting circuit assumes a period during which the level of the voltage boosting clock DCCLK is high as a charging period and a period during which the level of the voltage boosting clock DCCLK is low as a boosted voltage output period. Consequently, the voltage boosting circuit100operates so that the first and second voltage boosting circuits compensate each other, thereby the boosted output voltage VDC2falls less with respect to the load current (high power supply performance) in the voltage boosting circuit100.

Because the voltage of the voltage boosting capacitor121or221that is being charged is added to the supply voltage VDC and according to the addition result, the transistor113or213is turned on/off, the output voltage VDC2never exceeds the element breakdown voltage. Furthermore, the power supply circuit can use any of wide ranged supply voltages (from low to high voltages) without changing its settings. Furthermore, because the discharging cycle is synchronized with the voltage boosting clock DCCLK, no noise is generated in the boosted output voltage and no horizontal stripes appears on the screen. Thus the display quality is prevented from degradation.

FIG. 12shows a circuit diagram of a power supply circuit in a third embodiment. This power supply circuit includes a voltage boosting circuit20, an addition circuit60, a comparison circuit70, a control circuit80, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit20includes transistors11to17and voltage boosting capacitors21and22. The transistor11and13are switches for applying the supply voltage VDC to the voltage boosting capacitor21, thereby charging the capacitor21. The transistors12is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor21, thereby boosting the charge in the capacitor21. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40functions as a switch for extracting the voltage VC1from the voltage boosting capacitor21that is being charged. The transistors15and16are switches for applying the supply voltage VDC to the voltage boosting capacitor22, thereby charging the capacitor22. The transistor14is a switch for boosting the charge in the voltage boosting capacitor22with the voltage VC1of the voltage boosting capacitor21of which voltage is already boosted by the transistor12. The transistor17is a switch for discharging the charge from the voltage boosting capacitor22, thereby supplying the output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the voltage VC2from the voltage boosting capacitor22that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65. The addition circuit adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage DC2of the voltage boosting capacitor22, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72. The comparison circuit70compares the output voltage of the addition circuit60with a reference voltage VREF and outputs the comparison result to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and a NOT circuit83. The control circuit80controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit20according to the voltage boosting clock DCCLK and the comparison result of the comparison circuit70.

The output of the voltage boosting circuit20is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the NAND circuits81, the level shift circuits82, the NOT circuit83of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this third embodiment.

At first, the level of the output VCTL of the comparison circuit70is assumed to be high. Then, when the level of the voltage boosting clock DCCLK becomes low, the NOT circuit83outputs a high level signal and the NAND circuit81outputs a low level signal, thereby the transistors11,13,15, and16are turned on and the transistors12,14, and17are turned off. Consequently, the voltage boosting capacitor21is supplied the voltage VDC through the transistors11and13while the voltage boosting capacitor22is supplied the voltage VDC through the transistors15and16, thereby those voltage boosting capacities21and22are charged respectively.

At this time, the transfer gates40and41are on and outputs the voltages VC1and VC2of the voltage boosting capacitors21and22that are being charged to the addition circuit60. At this time, the addition circuit60adds up the charging voltage VC1of the voltage boosting capacitor21, the charging voltage VC2of the voltage boosting capacitor22, and the supply voltage VDC, then outputs the output voltage VADD to the comparison circuit70. If the resistance value is equal among the resistance elements61to63and the resistance values of the resistance elements64and65are defined as R64and R65respectively, the output voltage VADD of the addition circuit60is calculated as follows.
VADD=(1+R65/R64)·(VC1+VC2+VDC)/3  (4)

In the comparison circuit70, each of the resistance elements71and72divides the voltage VADD and the comparator78compares each divided voltage VCMP with a reference voltage VREF. If the resistance values of the resistance elements71and72are defined as R71and R72respectively here, so that the voltage VCMP is calculated as follows.
VCMP=VADD·R72/(R71+R72)  (5)

Consequently, the comparator78outputs a high level signal at VCMP<VREF and outputs a low level signal at VCMP≧VREF. When the comparator78outputs a high level signal, the NAND circuit81of the control circuit80outputs a low level signal, thereby the voltage boosting circuit20is charged. While the comparator78outputs a low level signal, the NAND circuit81outputs a high level signal, thereby the transistors13and16are turned off and the charging of the voltage boosting capacitors21and22stop.

When the level of the voltage boosting clock DCCLK becomes high, the output level of the NOT circuit83becomes low and the output level of the NAND circuit81becomes high, thereby the transistors11,13,15, and16are turned off while the transistors12,14, and17are turned on. Consequently, the supply voltage VDC and the voltage boosting capacitors C21and C22are connected to each another serially, thereby a voltage VDC+VC1+VC2is applied to the smoothing capacitor90. In other words, the output voltage VDC2becomes a voltage VDC+VC1+VC2.

If the voltage value of a desired boosted output voltage VDC2is assumed as V3, it is just required to satisfy VCMP=VREF here at VDC+VC1+VC2=V3, so that those items are substituted in the formulas (4) and (5) as follows.
(1+R65/R64)·V3/3=VREF·(R71+R72)/R72  (6)

R64, R65, R71, and R72are selected so as to satisfy the formula (6), thereby the charging voltages VC1and VC2are adjusted so as to satisfy the output voltage VDC2=V3.

In such a way, the power supply circuit in this third embodiment uses two voltage boosting capacitors and can generate a boosted output voltage that is three times the supply voltage VDC in maximum. Even the power supply circuit can obtain the same effect as that in the first embodiment by adding the voltages VC1and VC2charged into the voltage boosting capacitors21and22at the time of charging to the supply voltage VDC and controlling the on/off state of each of the transistors13and16in accordance with the addition result.

Furthermore, even upon increasing the voltage boosting power by adding another voltage boosting capacitor to the power supply circuit, the same effect can be obtained by adding up the charging voltages of all the voltage boosting capacitors that are being charged and controlling the on/off state of each switch for supplying a voltage for charging each voltage boosting capacitor according to the addition result.

FIG. 13shows a circuit diagram of a power supply circuit in a fourth embodiment. This power supply circuit includes a voltage boosting circuit30, an addition circuit60, a comparison circuit70, a control circuit80, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit30includes transistors11to18and voltage boosting capacitors21and23. The transistor11,13, and18are switches for connecting the voltage boosting capacitors21and22serially and applying the supply voltage VDC to those capacitors21and22, thereby charging them21and22. The transistor12is a switch for boosting the charge in the voltage boosting capacitor21by connecting the supply voltage VDC serially to the capacitor21. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40functions as a switch for extracting the voltage VC1from the voltage boosting capacitor21. The transistors15and16are switches for charging voltage boosting capacitor22by applying the supply voltage VDC thereto. The transistor14is a switch for boosting the charge in the voltage boosting capacitor22with the charging voltage VC1of the voltage boosting capacitor21and the supply voltage VDC. The transistor17is a switch for discharging the voltage boosting capacitor22, thereby supplying the output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the voltage VC2from the voltage boosting capacitor22that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65. The addition circuit60adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage VC2of the voltage boosting capacitor22extracted through the transfer gate41, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72. The comparison circuit70compares the output voltage of the addition circuit60with a reference voltage VREF and outputs the comparison result to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and NOT circuits83and84. The control circuit80controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit30according to the voltage boosting clock DCCLK and the comparison result of the comparison circuit70.

The output of the voltage boosting circuit30is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed output voltage VDC2is also supplied to the NAND circuits81, the level shift circuits82, the NOT circuits83and84of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this fourth embodiment.

At first, the output level of the comparison circuit70is assumed to be high. Then, when the level of the voltage boosting clock DCCLK is low, the NOT circuit83outputs a high level signal and the NAND circuit81outputs a low level signal, thereby the transistors11,13,15,16, and18are turned on and the transistors12,14, and17are turned off. Consequently, the voltage boosting capacitors21and23that are connected to each other serially through the transistor13are supplied the voltage VDC through the transistors11and18, thereby those capacitors21and23are charged respectively. The voltage boosting capacitors21and23are charged up to a voltage of ½ of the supply voltage VDC respectively. The voltage boosting capacitor22is supplied the supply voltage VDC through the transistors15and16and charged up to the VDC.

At this time, the transfer gates40and41are on and outputs the voltages VC1and VC2of the voltage boosting capacitors21and22that are being charged to the addition circuit60. At this time, the addition circuit60adds up the charging voltage VC1of the voltage boosting capacitor21, the charging voltage VC2of the voltage boosting capacitor22, and the supply voltage VDC, then outputs the output voltage VADD to the comparison circuit70. In the comparison circuit70, each of the resistance elements71and72divides the output voltage VADD and the comparator68compares each divided voltage VADD with a reference voltage VREF and outputs the comparison result to the control circuit80. As described in the third embodiment, the control circuit80controls the on/off state of each of the transistors16and 16 according to the comparison result and adjust the charging voltages VC1and VC2so that the output voltage VDC2becomes a desired voltage.

When the level of the voltage boosting clock DCCLK is high, the voltage boosting capacitors21and22are connected to each other serially through the transistor14and supply a voltage (supply voltage VDC+charging voltages VC1and VC2) to the smoothing capacitor90through the transistor17.

In such a way, the power supply circuit in this fourth embodiment uses three voltage boosting capacitors to generate a boosted output voltage that is 2.5 times the supply voltage VDC in maximum. Even this power supply circuit can obtain the same effect as each of those described above by adding up the voltages charged into the voltage boosting capacitors21and22at the time of charging and the supply voltage VDC and controlling the on/off states of the transistors16and18in accordance with the addition result.

Furthermore, there will be described a power supply circuit in a fifth embodiment with reference toFIG. 14. The power supply circuit in this fifth embodiment includes, as shown inFIG. 14, a voltage boosting circuit10, an addition circuit60, a comparison circuit70, a control circuit80, a transfer gate40, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown). The voltage boosting circuit10, the comparison circuit70, the control circuit80, and the transfer gate40are the same as those in the first embodiment. The addition circuit60includes an operation amplifier68and resistance elements61to65and adds up the charging voltage VC of the voltage boosting capacitor21, the supply voltage VDC, and the output voltage VDC2of the voltage boosting circuit10.

If the resistance values of the resistance elements61to65are defined as R61to R65and R61=R62=R63is satisfied here, then the output VADD of the addition circuit60can be calculated as follows.
VADD=(1+R65/R64)×(VC+VDC+VDC2)/3  (7)

The comparison circuit70obtains a comparison voltage VCMP by dividing the output VADD of the addition circuit60through each of the resistance elements71and72. If the resistance values of the resistance elements71and72are defined as R71and R72respectively, the comparison voltage VCMP can be calculated as follows.
VCMP=VADD×R72/(R71+R72)  (8)

Consequently, the comparison circuit70outputs a high level signal at VCMP<VREF and outputs a low level signal at VCMP≧VREF. When the comparison circuit70outputs a high level signal, the NAND circuit81of the control circuit80outputs a low level signal, thereby the charging is continued. When the comparison circuit70outputs a low level signal, the NAND circuit81of the control circuit80outputs a high level signal, thereby the transistor13is turned off and charging of the voltage capacitor21stops.

When the level of voltage boosting clock DCCLK is high, the transistors11and13are turned off and the transistors12and14are turned on. Thus the voltage VC+VDC=VDC2is supplied to the smoothing capacitor90. If the desired boosted output voltage value is defined as V2and the difference from the output voltage VDC2(a deficiency of VDC2) is assumed to be ΔV(=V2−VDC2), the following equality is satisfied.
V2+ΔV=VC+VDC(9)

Consequently, the ΔV can be compensated. If an adjustment is made on this condition so as to satisfy VCMP=VREF, therefore, the desired voltage V2is obtained. And the following calculation is possible with the formulas (7) to (9).
(1+R65/R64)×2×V2/3=VREF×(R71+R72)/R72  (10)

Consequently, by selecting R71, R72, R64, and R65so as to satisfy the formula (10), the charging voltage VC of the voltage boosting capacitor21is adjusted so as to satisfy VDC2=V2.

In the first to fourth embodiments, a voltage to be charged in each voltage boosting capacitor is decided free from influences of the boosted output voltage VDC2. In this fifth embodiment, however, because the output voltage VDC2is added up during a charging period, the voltage boosting capacitor21is kept charged until the charging voltage VC rises to compensate the falling of the output voltage VDC2as shown in the formula (9). Consequently, the output voltage VDC2is kept at a voltage nearer to the desired voltage value V2.FIG. 15shows a relationship between the load current and the boosted output voltage.FIG. 15Adenotes the property of the power supply circuit shown inFIG. 14andFIG. 15Bdenotes the property of the power supply circuit shown inFIG. 7. It would be understood from those facts that the power supply circuit in this fifth embodiment can prevent lowering of the boosted output voltage to be caused by a load current more effectively and the power supply is assumed as a voltage boosting circuit with higher performance.

As described above, in the case of the charge pump voltage boosting power supply circuit, the voltage of each voltage boosting capacitor is monitored while it is being charged and the on/off state of each switch is controlled according to the voltage. The power supply circuit can thus generate a predetermined output voltage that never exceeds the element breakdown voltage in a wide range of supply voltages (from low to high voltages). Furthermore, because switches are controlled only in the charging period, no random noise is superposed on the boosted output voltage. Consequently, it is possible to eliminate horizontal stripes that otherwise might appear on the display screen due to the noise. And because the boosted output voltage is also monitored, this fifth embodiment can realize a voltage boosting circuit that can prevent falling of the boosted output voltage that might occur due to a load current, thereby realizing high current supply performance.

In order to realize such high performance, it will be effective to reduce the on-resistance of each transistor in each voltage boosting circuit. In this case, a large current comes to flow in each transistor at the start of charging in the subject voltage boosting capacitor. In other words, as shown inFIG. 16A, a current IVDC flows from the power supply (voltage VDC) into the voltage boosting circuit10, so that the power supply voltage supplied to the voltage boosting circuit10and the source driver920, as well as the ground voltage come to be varied due to the influence of the resistance of the power supply line. Furthermore, as shown inFIG. 16B, because the supply voltage is varied in such a way, the output of a bias generation circuit included in the source driver902is also varied and the variation affects the output of the source driver20.

For example, the voltage in the voltage boosting circuit10varies as shown inFIGS. 17A to 17F.FIG. 17Ashows a ground voltage in the circuit of the source driver920,FIG. 17Bshows a power supply voltage VDC in the circuit of the source driver920, andFIG. 17Cshows a current IVDC flowing into the voltage boosting circuit10. As shown clearly in those figures, the voltages and current are varied significantly synchronously with the voltage boosting clock DCCLK (FIG. 17F).FIG. 17Dshows a voltage VC+ of the power supply side node of the voltage boosting capacitor andFIG. 17Eshows a voltage VC− of the ground side node thereof. As shown clearly in those figures, a large current (IVDC) flows in the voltage boosting capacitor at the start of charging. In such a way, if the supply voltage VDC and the ground voltage VSS are varied significantly, the variation causes the output of the source driver920to be varied and the image quality to be degraded with unnecessary horizontal stripes to be displayed on the screen. Such causes of the image quality degradation must be eliminated.

FIG. 18shows a circuit diagram of a power supply circuit in a sixth embodiment. This power supply circuit includes a voltage boosting circuit30, an addition circuit60, a comparison circuit70, a control circuit80, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown). This power supply circuit is almost the same in configuration as that in the fourth embodiment. There is only a difference between those embodiments; resistance elements are added newly to the voltage boosting circuit30in this sixth embodiment. The voltage boosting circuit30inserts a resistance element33between a transistor18and the voltage boosting capacitor23and another resistance element32between a transistor16and a voltage boosting capacitor22.

Consequently, the voltage boosting circuit30comes to include transistors11to18, voltage boosting capacitors21to23, and resistance elements32to33. The transistors11,13, and18are switches for connecting the voltage boosting capacitors21and23to each other serially and charging those capacitors21and23with a supply voltage VDC. The resistance element33connected between the transistor18and the voltage boosting capacitor23limits the current flow for charging the voltage boosting capacitors21and23. The transistor12is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor21to boost the charge therein. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40is a switch for extracting the voltage VC1from the voltage boosting capacitor21that is being charged. The transistors15and16are switches for charging the voltage boosting capacitor22by applying the supply voltage VDC thereto. The resistance element32connected between the transistor16and the voltage boosting capacitor22limits the current flow for charging the voltage boosting capacitor22. The transistor14is a switch for connecting the voltage boosting capacitor22serially to the voltage boosting capacitor21so as to boost the charge in the voltage boosting capacitor22with the charging voltage VC1of the voltage boosting capacitor21and the supply voltage VDC. The transistor17is a switch for discharging the charge from the voltage boosting capacitor22and supplying an output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the VDC2from the voltage boosting capacitor22that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65and adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage VC2of the voltage boosting capacitor22extracted through the transfer gate41, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72and compares the output voltage of the addition circuit60with a reference voltage VREF. The comparison result is output to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and NOT circuits83and84. The control circuit80controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit30according to the voltage boosting clock DCCLK and the comparison result of the comparison circuit70.

The output of the voltage boosting circuit30is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed voltage VDC2is also supplied to the NAND circuit81, the level shift circuit82, and the NOT circuits83and84of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this sixth embodiment.

At first, the output level of the comparison circuit70is assumed to be high. Then, when the level of the voltage boosting clock DCCLK is low, the NOT circuit83outputs a high level signal and the NAND circuit81outputs a low level signal, thereby the transistors11,13,15,16, and18are turned on and the transistors12,14, and17are turned off. Consequently, the voltage boosting capacitors21and23that are connected to each other serially through the transistor13are supplied the voltage VDC through the transistors11and18and the resistance element33, thereby the capacitors21and23are charged respectively. The voltage boosting capacitors21and23are charged up to a voltage of ½ of the supply voltage VDC respectively. At this time, the resistance element33limits the current for charging the voltage boosting capacitors21and23. The voltage boosting capacitor22is supplied the supply voltage VDC through the transistors15and16and the resistance element33to be charged up to the VDC. At this time, the resistance element32limits the current for charging the voltage boosting capacitor22. Here, while the resistance elements32and33are described as independent elements, the on-resistance of the transistors16and18may be used instead of those elements32and33. In other words, it is possible to use the transistors16and18instead of the resistance elements32and33to adjust their on-resistance to flow a predetermined current.

At this time, the transfer gates40and41are on and outputs the voltages VC1and VC2of the voltage boosting capacitors21and22that are being charged respectively to the addition circuit60. The addition circuit60then adds up the charging voltage VC1of the voltage boosting capacitor21, the charging voltage VC2of the voltage boosting capacitor22, and the supply voltage VDC and outputs the output voltage VADD to the comparison circuit70. In the comparison circuit70, the resistance elements71and72function to divide the output voltage VADD respectively and the comparison circuit70compares each divided voltage VADD with a reference voltage VREF and outputs the comparison result to the control circuit80. As described in the third embodiment, the control circuit80controls the on/off state of each of the transistors16and18according to the comparison result and adjust the charging voltages VC1and VC2so that the output voltage VDC2becomes a desired voltage.

When the level of the voltage boosting clock DCCLK is high, the voltage boosting capacitors21and22are connected to each other serially through the transistor14, thereby a voltage (supply voltage VDC+charging voltages VC1and VC2) is supplied to the smoothing capacitor90through the transistor17.

In such a way, the power supply circuit described in the fourth embodiment are provided with the resistance elements32and33for limiting the supply current IVDC for charging respectively in this sixth embodiment. Consequently, as shown inFIGS. 19A to 19E, the change of the current (FIG. 19B) is eased upon charging the voltage boosting capacitors21to23and the variation of the supply voltage VDC is suppressed (FIG. 19A). Here, the power supply circuit is described on the basis of that in the fourth embodiment, the variation of the supply voltage VDC can also be suppressed similarly in the power supply circuits in other embodiments.

FIG. 20shows a circuit diagram of a power supply circuit in a seventh exemplary embodiment. This power supply circuit includes a voltage boosting circuit30, an addition circuit60, a comparison circuit70, a control circuit80, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown). This power supply circuit is almost the same in configuration as that in the fourth exemplary embodiment. There is only a difference between those embodiments; a resistance element is added newly to the voltage boosting circuit30in this seventh embodiment. The voltage boosting circuit30inserts the resistance element96between the transistor18/16and the supply voltage VDC.

Consequently, the voltage boosting circuit30comes to include transistors11to18, voltage boosting capacitors21to23, and a resistance element96. The transistors11,13, and18are switches for connecting the voltage boosting capacitors21and23to each other serially and apply a supply voltage VDC to those capacitors21and23through the resistance element96, thereby charging those capacitors21and23. The transistor12is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor21to boost the charge therein. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40is a switch for extracting the voltage VC1from the voltage boosting capacitor21that is being charged. The transistors15and16are switches for charging the voltage boosting capacitor22by applying the supply voltage VDC thereto through the resistance element96. The resistance element96limits the current flow for charging the voltage boosting capacitors21to23. The transistor14is a switch for connecting the voltage boosting capacitor22serially to the voltage boosting capacitor21so as to boost the charge in the voltage boosting capacitor22with the charging voltage VC1of the voltage boosting capacitor21and with the supply voltage VDC. The transistor17is a switch for discharging the charge from the voltage boosting capacitor22and supplying an output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the VDC2from the voltage boosting capacitor22that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65and adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage VC2of the voltage boosting capacitor22extracted through the transfer gate41, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72and compares the output voltage of the addition circuit60with a reference voltage VREF. The comparison result is output to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and NOT circuits83and84. The control circuit80controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit30according to the voltage boosting clock DCCLK and the comparison result of the comparison circuit70.

The output of the voltage boosting circuit30is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed voltage VDC2is also supplied to the NAND circuit81, the level shift circuit82, and the NOT circuits83and84of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this seventh embodiment.

At first, the output level of the comparison circuit70is assumed to be high. Then, when the level of the voltage boosting clock DCCLK is low, the NOT circuit83outputs a high level signal and the NAND circuit81outputs a low level signal, thereby the transistors11,13,15,16, and18are turned on and the transistors12,14, and17are turned off. Consequently, the voltage boosting capacitors21and23that are connected to each other serially through the transistor13are supplied the voltage VDC through the transistors11and18and the resistance element96, thereby the capacitors21and23are charged. At this time, the voltage boosting capacitors21and23are charged up to a voltage of ½ of the supply voltage VDC respectively. The resistance element96limits the current flow for charging the voltage boosting capacitors21and23. The voltage boosting capacitor22is supplied the supply voltage VDC through the transistors15and16and the resistance element96, thereby the capacitor22is charged up to the VDC. At this time, the resistance element96limits the current flow for charging the voltage boosting capacitor22, thereby the variation of the supply voltage VDC that might occur due to the charging current at the start of charging is suppressed.

At this time, the transfer gates40and41are on and outputs the voltages VC1and VC2of the voltage boosting capacitors21and22that are being charged respectively to the addition circuit60. The addition circuit60then adds up the charging voltage VC1of the voltage boosting capacitor21, the charging voltage VC2of the voltage boosting capacitor22, and the supply voltage VDC and outputs the output voltage VADD to the comparison circuit70. In the comparison circuit70, the resistance elements71and72function to divide the output voltage VADD respectively and the comparison circuit70compares each divided voltage VADD with the reference voltage VREF and outputs the comparison result to the control circuit80. As described in the third embodiment, the control circuit80also controls the on/off state of each of the transistors16and18according to the comparison result and adjust the charging voltages VC1and VC2so that the output voltage VDC2reaches a desired voltage.

When the level of the voltage boosting clock DCCLK is high, the voltage boosting capacitors21and22are connected to each other serially through the transistor14, thereby a voltage (supply voltage VDC+charging voltages VC1and VC2) is supplied to the smoothing capacitor90through the transistor17.

The liquid crystal display driver IC940that employs this power supply circuit, as shown inFIG. 21, is mounted on a glass substrate950. A power is supplied to the liquid crystal display driver IC940through a flexible printed circuits960. A power supply line962provided on the flexible printed circuits960is connected to power lines952and953provided on the glass substrate950at junctions955and956. The liquid crystal display driver IC940includes a bump942and the driver IC940is connected to the power lines952and953provided on the glass substrate950through the bump942. Consequently, the connection resistance related to a power supply is determined by the number of bumps942, the width of the power line952/953provided on the glass substrate950, and the connection resistance of the junction955/956.

In other words, as shown inFIG. 21, because the lines on the glass substrate950are classified into the power line952and the power line953, the resistance value can be changed. When the power line952is extremely thick and the number of bumps942increases, the resistance value can be set almost at zero. On the other hand, the width of the line953and the number of bumps942are adjusted so as to obtain a resistance value equivalent to that of the resistance element96. Consequently, a power is supplied to the transistor12through the power line952while the resistance is almost zero and a power comes to be supplied to the transistors16and18through the power line953at a resistance value equivalent to that of the resistance element96. In such a way, the line resistor can be used instead of the resistance element96. In other words, the number of resistance elements can also be reduced by utilizing the packaging properties. Here, although the description has been made on the basis of the power supply circuit in the fourth embodiment, the reduction of the number of resistance elements, etc. described here may be achieved similarly for the circuits in other embodiments.

FIG. 22shows a circuit diagram of a power supply circuit in an eighth exemplary embodiment. This power supply circuit includes a voltage boosting circuit50, an addition circuit60, a comparison circuit170, a control circuit380, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown). This power supply circuit differs in configuration from that described in the fourth embodiment; in this eighth embodiment, transistors36and38are connected to each other in parallel to the transistors16and18for charging the voltage boosting capacitors21to23provided in the voltage boosting circuit30and a comparison circuit170is newly added to control the operations of those transistors36and38and a gate circuit is added to the control circuit380.

The voltage boosting circuit50includes transistors11to18, as well as36and38and voltage boosting capacitors21to23. The transistors16and36are connected to each other in parallel while the transistors18and38are connected in parallel. The transistors11,13, and18/38are switches for connecting the voltage boosting capacitors21and23to each other serially and charge those capacitors21and23by applying a supply voltage VDC thereto. The transistor12is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor21to boost the charge therein. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40is a switch for extracting the voltage VC1from the voltage boosting capacitor21that is being charged. The transistors15and16/36are switches for charging the voltage boosting capacitor22by applying the supply voltage VDC thereto. The transistor14is a switch for connecting the voltage boosting capacitor22serially to the voltage boosting capacitor21, thereby boosting the charge in the capacitor22with the charging voltage VC1of the voltage boosting capacitor21and the supply voltage VDC. The transistor17is a switch for discharging the charge from the voltage boosting capacitor22and supplying an output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the VDC2from the voltage boosting capacitor22that is being charged.

The addition circuit60includes an operation amplifier68and resistance elements61to65and adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage VC2of the voltage boosting capacitor22extracted through the transfer gate41, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72and compares the output voltage of the addition circuit60with a reference voltage VREF. The comparison result VCTL is output to the control circuit380. The comparison circuit170includes a comparator178, as well as resistance elements171and172and compares the supply voltage VDC with the reference voltage VREF. The comparison result VCTL2is output to the control circuit380. The supply voltage compared in the comparison circuit170should preferably be free from the influence of the voltage drop to be caused by a charging current and the comparison should preferably be made for a voltage around the input end of the supply voltage VDC in this power supply circuit.

The control circuit380includes NAND circuits81and88, level shift circuits82and86, and NOT circuits83,84, and87. The control circuit380controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit50according to the voltage boosting clock DCCLK and the comparison result of the comparison circuit70/170. The output VCTL2of the comparison circuit170drives the NAND circuits81and88exclusively. In other words, the output VCTL2validates the NAND81when the supply voltage VDC is lower than the predetermined voltage and validates the NAND circuit88when the supply voltage VDC is higher than the predetermined voltage. When the NAND circuit81is validated, the transistors18and16are turned on. When the NAND circuit88is validated, the transistors38and36are turned on. If the on-resistance of the transistors38and36is set larger than the on-resistance of the transistors18and16, the charging current can be limited when the transistors38and36are turned on.

The output of the voltage boosting circuit50is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed voltage VDC2is also supplied to the NAND circuits81and88, the level shift circuits82and86, and the NOT circuits83,84, and87of the control circuit380, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in this eighth embodiment.

In the comparison circuit170, the comparator178compares a voltage obtained by dividing the supply voltage VDC through each of the resistance elements171and172with a reference voltage VREF and outputs the comparison result VCTL2. In other words, the comparison result VCTL2, which denotes whether the supply voltage VDC is higher or lower than the predetermined voltage, is output to the control circuit380through the level shift circuit86. Here, the comparison result VCTL2denotes the low level when the supply voltage VDC is higher than the predetermined voltage and the comparison result VCTL2denotes the high level when the supply voltage VDC is lower than the predetermined voltage.

On the other hand, in the control circuit380, each of the NAND circuits81and88works exclusively as a selection circuit that receives the comparison result VCTL2as a selection signal. Consequently, when the comparison result VCTL2denotes the high level, the NAND circuit81side circuit is validated. When the supply voltage VDC denotes the low level, the NAND circuit88side circuit is validated. When the comparison result VCTL2denotes the high level, that is, when the supply voltage VDC is lower than the predetermined voltage, the NAND circuit81is validated to drive the transistors18and16, thereby this power supply circuit works as described in the fourth embodiment. And when the comparison result VCTL2denotes the low level, that is, when the supply voltage VDC is higher than the predetermined voltage, the NAND circuit88is validated to drive the transistors38and36instead of the transistors18and16. In this case, the route for connecting the supply voltage VDC upon charging the voltage boosting capacitors21to23is switched, thereby the resistance value is switched.

In other words, when the supply voltage VDC is higher than the predetermined voltage and the level of the voltage for charging the voltage boosting capacitors21to23is high, the transistors38and36having a large on-resistance respectively are driven, thereby the charging current of the voltage boosting capacitors21to23is limited. Consequently, it is avoided that the current flow in the subject voltage boosting circuit changes abruptly. The supply voltage VDC is thus prevented from significant changes. When the supply voltage VDC is lower than the predetermined voltage and the level of the voltage for charging the voltage boosting capacitors21to23is low, the transistors18and16having a small on-resistance respectively are driven and the charging current is not limited. Consequently, when the charging current at the start of charging is comparatively less, no current limitation is made and the performance is not degraded.

As described above, the power supply circuit in this embodiment includes newly added charging switches (transistors); this is different in configuration from the power supply circuit in the fourth embodiment. Each of the switches has on-resistance to be switched in accordance with the level of the supply voltage VDC. In the power supply circuit configured in such a way, a high on-resistance switch (transistor36/38) is selected for a high supply voltage VDC that might cause a fluctuation due to a charging current at the start of charging, thereby the charging current is suppressed while a low on-resistance switch (transistor16/18) is selected for a low supply voltage VDC that will not cause any fluctuation, since the charging current at the start of charging is small, thereby the charging performance is assured.

FIG. 23shows a circuit diagram of a power supply circuit in a ninth exemplary embodiment. This power supply circuit includes a voltage boosting circuit30, an addition circuit60, a comparison circuit70, a control circuit80, transfer gates40and41, and a smoothing capacitor90. The power supply circuit supplies an output voltage VDC2to a load circuit (not shown).

The voltage boosting circuit30includes transistors11to18, as well as voltage boosting capacitors21to23. The transistors11,13, and18are switches for connecting the voltage boosting capacitors21and23to each other serially, thereby charging those capacitors21and23by applying a supply voltage VDC thereto. The transistor12is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor21, thereby boosting the charge therein. The transfer gate40includes two transistors and a NOT circuit. The transfer gate40is a switch for extracting the voltage VC1from the voltage boosting capacitor21that is being charged. The transistors15and16are switches for charging the voltage boosting capacitor22by applying the supply voltage VDC thereto. The transistor14is a switch for connecting the voltage boosting capacitor21serially to the voltage boosting capacitor22, thereby boosting the charge in the voltage boosting capacitor22with the charging voltage VC1of the voltage boosting capacitor21and the supply voltage VDC. The transistor17is a switch for discharging the charge from the voltage boosting capacitor22and supplying an output voltage VDC2to the smoothing capacitor90. The transfer gate41includes two transistors and a NOT circuit and functions as a switch for extracting the VDC2from the voltage boosting capacitor22that is being charged. The sources of the transistors11and15are not connected to a common line VSS in a circuit for supplying a ground voltage GND, but connected directly to an independent line VSC, away from the common line VSS, for supplying the ground voltage GND. In other words, the ground voltage of the voltage boosting circuit30is separated from the ground voltage of the common line VSS and connected to the ground voltage of the independent line VSC. Consequently, the ground voltage VSS of each of the comparison circuit70, the addition circuit60, and the control circuit80is not affected from the current flowing in the voltage boosting circuit30, thereby the ground voltage VSS is stabilized.

The addition circuit60includes an operation amplifier68and resistance elements61to65and adds up the voltage VC1of the voltage boosting capacitor21extracted through the transfer gate40, the voltage VC2of the voltage boosting capacitor22extracted through the transfer gate41, and the supply voltage VDC. The comparison circuit70includes a comparator78and resistance elements71and72and compares the output voltage of the addition circuit60with a reference voltage VREF. The comparison result is output to the control circuit80. The control circuit80includes a NAND circuit81, a level shift circuit82, and NOT circuits83and84. The control circuit80controls the on/off state of each of the transistors (switches) and the transfer gates40and41of the voltage boosting circuit30according to the voltage boosting clock DCCLK and the comparison results of the comparison circuit70.

The output of the voltage boosting circuit30is smoothed by the smoothing capacitor90and the result is supplied to the load circuit. The smoothed voltage VDC2is also supplied to the NAND circuit81, the level shift circuit82, and the NOT circuits83and84of the control circuit80, as well as the operation amplifier68of the addition circuit60, etc.

Next, there will be described the operation of the power supply circuit in the ninth exemplary embodiment. The operation of each part in the power supply circuit is the same as that in the power supply circuit in the fourth embodiment.

At first, the output level of the comparison circuit70is assumed to be high. Then, when the level of the voltage boosting clock DCCLK is low, the NOT circuit83outputs a high level signal and the NAND circuit81outputs a low level signal, thereby the transistors11,13,15,16, and18are turned on and the transistors12,14, and17are turned off. Consequently, the voltage boosting capacitors21and23connected to each other serially through the transistor13are supplied a supply voltage VDC through the transistors11and18to be charged respectively. The voltage boosting capacitors21and23are charged up to a voltage of ½ of the supply voltage VDC respectively. At this time, the charging current flows to the ground voltage GND through the independent line VSC from the source of the transistor11. The voltage boosting capacitor22is supplied the supply voltage VDC through the transistors15and16to be charged up to the VDC. At this time, the charging current flows from the source of the transistor15to the ground voltage GND through the independent line VSC.

At this time, the transfer gates40and41are on and outputs the voltages VC1and VC2of the voltage boosting capacitors21and22that are being charged respectively to the addition circuit60. The addition circuit60then adds up the charging voltage VC1of the voltage boosting capacitor21, the charging voltage VC2of the voltage boosting capacitor22, and the supply voltage VDC and outputs the output voltage VADD to the comparison circuit70. In the comparison circuit70, each of the resistance elements71and72divides the output voltage VADD and the comparison circuit70compares each divided voltage VADD with the reference voltage VREF and outputs the comparison result to the control circuit80. As described in the third embodiment, the control circuit80also controls the on/off state of each of the transistors16and18according to the comparison result and adjusts the charging voltages VC1and VC2so that the output voltage VDC2reaches a desired voltage.

When the level of the voltage boosting clock DCCLK is high, the voltage boosting capacitors21and22are connected to each other serially through the transistor14, thereby a voltage (supply voltage VDC+charging voltages VC1and VC2) is supplied to the smoothing capacitor90through the transistor17.

In such a way, the charging current flows from the sources of the transistors11and15to the independent line VSC upon charging the voltage boosting capacitors21to23. Therefore, as shown inFIGS. 24A to 24C, no fluctuation occurs in the voltage of the common line VSS while the fluctuation might otherwise occurs due to a charging current. In other words, in this embodiment, the sources of the switches (transistors11and15) provided in the charging route are separated from the common line VSS and connected to the independent line VSC, thereby the voltage of the common line VSS is prevented from fluctuation that might otherwise occur due to a charging current and the display quality of the liquid crystal display apparatus is prevented from degradation.

As described above, if high performance is required, then a predetermined resistance element is inserted only at the voltage supply side of the subject charging switch, thereby minimizing the lowering of the performance while the charging current is limited. Otherwise, switching is made between a low on-resistance switch and a high on-resistance switch in accordance with the level of the supply voltage VDC, thereby limiting the charging current in accordance with the level of the supply voltage VDC. If the charging current is limited in such a way, it is possible to suppress the fluctuation of the supply voltage VDC that might otherwise occur due to a charging current at the start of charging. Consequently, the display quality can be prevented from degradation such as horizontal stripes to appear on the screen. Furthermore, the source of each switch (transistor) at the low potential side of the charging channel capacitor is separated from the common line VSS and connected to the independent line VSC in the subject circuit, thereby it is possible to eliminate the fluctuation of the voltage in the common line VSS, which might otherwise occur due to a charging current in the subject circuit. Thus the display quality is prevented from degradation such as horizontal stripes to appear on the screen. The present invention is not limited only to the embodiment described above; it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention.