Low voltage current and voltage generator

A bandgap reference circuit which is operable in low supply conditions is described. Such a circuit includes a second amplifier and a resistor at the output of a bandgap reference cell to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1 and Q2 with currents of different forms.

FIELD OF THE INVENTION

The invention relates to bandgap voltage references and particularly to bandgap voltage circuits operable in low supply voltage environments.

BACKGROUND

Bandgap voltage references and temperature dependent or temperature independent bias current generators are widely used in integrated circuits and have application in both bipolar and CMOS processes. Ultimately it will be understood that any bandgap based voltage or current generator provides for a combination of a Proportional To Absolute Temperature (PTAT) signal with a Complementary To Absolute Temperature (CTAT) signal. In bandgap voltage reference a base-emitter voltage of a bipolar transistor (which is CTAT) is added to a PTAT voltage generated from a base-emitter voltage difference of at least two bipolar transistors operating at different collector current density. In constant current generators or in current mode bandgap voltage generators two currents, one of the form of a PTAT current and one of the form of a CTAT current, are combined to generate a desired output current or voltage. In the design of such circuits operation at low power supply is desired.

An example of a known low voltage bandgap voltage reference implemented in CMOS process is presented inFIG. 1. It includes three substrate bipolar transistors, Q1, Q2, Q3four PMOS transistors, M1, M2, M3, M4, two NMOS transistors, M5, M6, one amplifier, A, and two resistors, R1, R2. The amplifier A effects a forcing of the common gate of M1to M4such that its two inputs have substantially the same voltage which is the base-emitter voltage of bipolar transistor operating at lower current density, Q2. As the bipolar transistors coupled to each of the two input terminals of the amplifier are operable at different current densities, abase emitter voltage difference ΔVbe is generated. This base-emitter voltage difference ΔVbe between the bipolar transistors Q1and Q2is reflected across R1which is coupled between the non-inverting terminal of the amplifier and Q1. The base emitter voltage of Q1provides a base emitter voltage Vbe. Thus, the reference voltage at the output node Vrefis a combination of the ΔVbe across R1and the Vbe of Q1. The circuit ofFIG. 1implemented in a typical submicron CMOS process can operate at a supply voltage of less than 1.5V. It can generate both a voltage reference and PTAT current reference.

Another example of a known prior art circuit configured to generate a constant current or with a predetermined temperature output voltage or current is presented inFIG. 2. The circuit ofFIG. 2is based on two bipolar transistors; a first QP1, operating with high current density, and the second, QP2, operating with low current density. Their base-emitter voltage difference ΔVbe, which is a signal of the form of a proportional to absolute temperature PTAT signal, is reflected across a resistor R3coupled between QP2and the inverting terminal of the operational amplifier, A1. As the amplifier A1operably controls its two inputs to be at substantially the same voltage level and similarly to the circuit ofFIG. 1, the input to the amplifier A1has a voltage level corresponding to the base-emitter voltage Vbe of the bipolar transistor QP1operating with higher base-emitter voltage. This has a form of a complementary to absolute temperature, CTAT, signal. The drains of the two PMOS transistors MP2, MP3are each coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier A1. Each PMOS transistor MP2and MP3have substantially identical aspect ratios W/L and have their gates coupled to ground which results in the drains currents being PTAT in nature. A second amplifier A2is provided having its inverting terminal coupled to the non-inverting terminal of the first amplifier A1. A feedback path from the second amplifier A2is coupled to each of the MOS devices MP2, MP3and forms a common summing node “f”. At the summing node “f” three currents are summed together, two PTAT currents, from MP2and MP3,respectively, and one CTAT current, as the second amplifier A2operably forces the base-emitter voltage across a resistor R4via MOS device MP6, provided at the output of the amplifier A2. As a result the current via PMOS transistor MP1has a temperature dependence relating to the mixture of PTAT and CTAT currents. While the circuit ofFIG. 1operates at a lower supply voltage to the circuit ofFIG. 2, it suffers in that it can generate only PTAT currents. The circuit ofFIG. 2is operable to generate a current with desired temperature behaviour but requires a larger supply voltage compared to the circuit ofFIG. 1as the PMOS transistor MP1forms a cascoded arrangement with each of PMOS transistors MP2and MP3. Similarly, MP4and MP5are in a cascoded arrangement. It will be appreciated by those skilled in the art that transistors in a cascoded arrangement requires a high biasing voltage than an uncascoded arrangement.

There is therefore a need for a circuit that can operate in lower voltage supply environments but yet has a desired temperature behaviour.

SUMMARY

Accordingly the invention provides a bandgap reference circuit which is operable in low supply conditions. Such a circuit includes a second amplifier and a resistor at the output of a bandgap reference cell to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1and Q2with currents of different forms.

These and other features will be better understood with reference to the following drawings which will assist in an understanding of the teaching of the invention but which are not intended to be limiting in any fashion.

DETAILED DESCRIPTION OF THE DRAWINGS

Exemplary implementations of circuits provided in accordance with the teaching of the invention are now described with reference toFIGS. 3 to 5. Such circuits are adapted to generate an output current with desired temperature behaviour, and are also operable at low supply current.

A first example of such a circuit is presented inFIG. 3. Such a circuit includes a first amplifier A1having an inverting terminal, a non-inverting terminal and an output terminal. Coupled to each of the two input terminals of the amplifier A1are first Q1and second Q2bipolar transistors which are operable at different current densities such that a difference in base emitter voltages ΔVbe between each of the first and second transistors is generated across a resistor R1provided to the non-inverting input leg of the amplifier. This voltage difference has a proportional to absolute temperature PTAT form. The output from the amplifier which drives M1and M2forces PTAT drain currents for each of M1and M2.

The first transistor Q1which is operable at the lower current density is coupled via the resistor R1to the non-inverting input of the amplifier whereas the second transistor Q2, operable at the higher current density, is coupled directly to the inverting input of the amplifier. The voltage at the input to the amplifier is therefore related to the base emitter voltage Vbe of this second transistor Q1and has a complementary to absolute temperature CTAT form.

A second amplifier A2also having an inverting terminal, a non-inverting terminal and an output terminal is provided, the non-inverting terminal being coupled to the non-inverting terminal of the first amplifier A1. As a result the CTAT voltage Vbe at the input to the first amplifier A1is reflected at the inputs of the second amplifier A2.

The inverting input of the second amplifier is coupled with the output of the first amplifier via the MOS devices MI and M2. The two MOS devices M1, M2are desirably provided having the same aspect ratio W/L. Two degeneration resistors R3, R4are also provided and are coupled between the sources of the two MOS devices M1, M2and ground respectively. Each of the degeneration resistors R3, R4are desirably provided having the same value. This will be understood as representing a preferred but not essential arrangement in that by scaling the MOS devices M1, M2and their associated resistors R3, R4to one another different scaled currents could be generated. The drains of the two MOS devices M1, M2are coupled to each of the non-inverting and inverting inputs to the amplifier respectively.

The inverting input of the second amplifier A2is also coupled via a first mirror arrangement provided by MOS devices M5, M4, M3to the inputs to the first amplifier A1. The drain of the MOS device M5is coupled to the inverting input of the second amplifier A2and also to the drain of the second MOS device M2. It is also coupled to ground via a load resistor R2. It will be understood that assuming the MOS devices M1and M2have the same aspect ratio and the degeneration resistors R3and R4have the same value then the amplifier A1forces the base-emitter voltage difference ΔVbe between Q1and Q2across resistor R1. As a result the drain currents of M1and M2are PTAT currents. All input voltages of A1and A2have substantially the same voltage level, which is base-emitter voltage Vbe of Q2such that the voltage developed across R2is the Vbe voltage which results in a CTAT current flowing through the load resistor R2. A summing node, I Sum, is therefore provided where this CTAT current which flows through R2is summed with the PTAT current provided at the drain of M2. In this way the summed current at the summing node is derived from the CTAT and PTAT voltages.

A second mirroring arrangement is effected by coupling the gate of MOS device M5to the gate of MOS device M6, which again is desirably provided having the same aspect ratio. As a consequence the drain current of M6is substantially identical to the drain current of M5which is equal to the current at the summing node. The drain current of M6therefore is a constant current made up of a PTAT current and a CTAT current which flows through the load across which a constant voltage, V Sum, is developed. The voltage reference, and the originating current reference, can be scaled by scaling the relative values of the first and second resistors R1and R2.

As M3, M4, M5and M6have the same gate-source voltage they will provide substantially identical drain currents. In this way although they are detailed as being first and second current mirrors, they provide the same mirroring of the current from the drain of M5which is equal to the summed current. Depending on the resistor ratio of R2/R1, the drain currents of M3to M6can be provided as constant currents or with desired temperature behaviour. Assuming that the output is a constant current it will be understood that a constant current is provided at each of the drains of M3, M4, M5, M6with the result that the first and second bipolar transistors Q1and Q2are biased with a constant current substantially equal to the summed current. It will be understood that the biasing of the first and second bipolar transistors Q1and Q2with a constant current provides for no compensation for second order temperature curvature effects but a modification to the circuit ofFIG. 3to provide for such correction will be discussed later.

It will be understood that the value of the constant current/voltage nodes ofFIG. 3are not directly related to the value of the base emitter voltage of the first bipolar Q1.FIG. 4shows a modification of the circuitry ofFIG. 3which can generate simultaneously a voltage, Vref which is based on the base emitter voltage value of a bipolar, and an output current with a predetermined temperature behaviour.

Referring now toFIG. 4, similarly to that described with reference toFIG. 3, the drain currents of MOS devices M1and M2are operating with PTAT currents. However whereas in the circuit ofFIG. 3, the load resistor R2was coupled to the drain of M2so as to provide a CTAT current which was summed with the PTAT current provided by M2to generate the constant current at the summing node, in this arrangement ofFIG. 4an additional sub-circuit is provided and the summing node is provided as part of that sub-circuit. In this way the drain of MOS device M5is biased with a PTAT form derived from the drain current of MOS device M2such that a corresponding PTAT current is mirrored by MOS devices M3, M4and M5to bias the first and second bipolar transistors Q1and Q2. A load resistor R5across which a PTAT voltage is developed resulting from the drain current of M3is provided in the non-inverting leg between the drain of MOS device M3and the first bipolar Q1. A voltage reference node between R5and the drain M2provides an output voltage whereby the PTAT voltage developed across R5is summed with a CTAT voltage provided by the base emitter voltage Vbe of the bipolar device Q1to generate the voltage reference.

As was mentioned above, whereas in the circuit ofFIG. 3, the current at the summing node was directly mirrored using the current mirror of MOS devices M5, M6, in this circuit ofFIG. 4, an additional sub-circuit is provided. The sub-circuit consists of a NMOS transistor, M8, two PMOS transistors, M6, M7, one amplifier, A3, and two resistors, R2, R6. The non-inverting input of the third amplifier A3is coupled to the drain of MOS device M1and the non-inverting input of the second amplifier A2. Whereas in the circuitry ofFIG. 3the drain of the MOS device M2was coupled to the second resistor R2, the drain of the MOS device M5and the inverting input of the second amplifier A2such that the summing node was at the drain of the second MOS device M2, in this arrangement the additional MOS device M8, which is at the same gate potential as M2and M1, is coupled at its drain to the inverting input of amplifier A3and across load device R2to ground. The summing node ISum, has therefore been transferred across to the common node of the drain of MOS device M8, the inverting input of the third amplifier A3, the drain of MOS device M6and the resistor R2. Similarly to that described with reference toFIG. 3, a CTAT voltage ΔVbe is developed across the resistor R2derived from Q1which result in a CTAT current flowing through R2which sums with the PTAT current at the summing node resulting in a constant current which is mirrored by M6and M7. Thus the drain current of M7is a constant current, the summed current, which is reflected across the load to develop a reference voltage VSum. The temperature dependence of the current injected from M7into the load corresponds to the resistor ratio R2/R1.

It will be appreciated that in the arrangement ofFIG. 3, the first and second bipolar transistors were biased with a constant current whereas inFIG. 4they are both biased with a PTAT current. The reference voltage provided by the circuit ofFIG. 4at the output node Vref has a typical second order non-linear voltage error of the form TlogT. This second order effect is commonly called a curvature error. This error can be minimised if the two bipolar transistors, Q1, Q2are biased differently, Q1with PTAT current and Q2with constant current.FIG. 5shows how by providing currents of this form it is possible to generate a “curvature” corrected voltage reference and a temperature independent output current. In the circuit modification ofFIG. 5, the gate of MOS device M3is coupled directly to the output of the second amplifier A2, whereas the gate of MOS device M4is coupled to the output of the third amplifier A3. In this way the drain current of M4is of the form of a constant current, derived from the constant current summing node, whereas the drain of M3has a PTAT form derived from the drain current of MOS device M2. By biasing each of the first and second bipolar transistors Q1, and Q2with current of a different form, a second order curvature correction is effected.

It will be understood that what has been described herein are exemplary arrangement of circuits that are operable in a bandgap configuration and can be used in environments with low supply voltages as there is no need to provide transistors in a cascoded arrangement. Such circuits may provide for simultaneous generation of temperature independent voltage and temperature independent current references. By providing a resistor at the output node of an amplifier it is possible to compensate for base emitter variations in the transistor providing the bandgap voltage cell CTAT component and this compensation can be achieved irrespective of the resistor's temperature coefficient. Such circuits may be configured to provide bias currents to each of the first and second bipolar transistors Q1and Q2as to compensate for second order curvature effects that are inherent in any bandgap cell.

It will be understood that what has been described herein are exemplary embodiments of circuits which, by providing a second amplifier and a resistor at the output of a bandgap reference cell it is possible to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1and Q2with currents of different forms. While the present invention has been described with reference to exemplary arrangements and circuits it will be understood that it is not intended to limit the teaching of the present invention to such arrangements as modifications can be made without departing from the spirit and scope of the present invention. In this way it will be understood that the invention is to be limited only insofar as is deemed necessary in the light of the appended claims.

It will be understood that the use of the term “coupled” is intended to mean that the two devices are configured to be in electric communication with one another. This may be achieved by a direct link between the two devices or may be via one or more intermediary electrical devices.

Similarly the words comprises/comprising when used in the specification are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more additional features, integers, steps, components or groups thereof.