Multiplier pipelining optimization with a postponed estimation correction

One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

FIELD

The present disclosure relates to multiplier pipelining optimization, in particular to, multiplier pipelining optimization with a postponed estimation correction.

BACKGROUND

Cryptography may be utilized to protect data from unwanted access, for authentication, to generate digital signatures, etc. Current cryptographic techniques rely on intensive mathematical operations. For example, a number of public key cryptographic standards (e.g., RSA (Rivest-Shamir-Adleman), Diffie-Hellman, ElGamal, DSA (Digital Signature Algorithm), etc.) are based, at least in part, on modular exponentiation of large numbers. A binary representation of the large numbers may include on the order of thousands, e.g., 1024, 2048, 4096, 8192, etc., or more bits. Modular exponentiation involves raising a first number (base) to some power (exponent) and reducing it with respect to a third number (modulus). A reduction (i.e., modular reduction) result corresponds to a remainder left when the base raised to the exponent is divided by the modulus. Mathematically, modular exponentiation can be expressed as gemod M where g is the base, e is the exponent and M is the modulus. Computationally, modular exponentiation includes squaring followed by a reduction and/or multiplying followed by a reduction. Such operations are performed repeatedly in cryptography. Thus, even a relatively small performance increase in a single modular reduction operation can have a significant effect over the relatively large number of modular reduction operations associated with modular exponentiation of large numbers.

DETAILED DESCRIPTION

Modular exponentiation for large numbers may be performed by a square-and-multiply technique. Whether to square an operand or square and multiply the operand depends on a value of the exponent. For each square and multiply operation there is a reduction stage to reduce the square/multiplication result modulo the modulus. The reduction stage thus reduces the size (e.g., in bits) of the square/multiplication result to the size of the operand(s) used as input to the square/multiply operation.

One technique for performing modular multiplication and squaring of relatively large numbers includes a combination of “schoolbook” multiplication and a Barrett reduction technique. Schoolbook multiplication generally includes multiplying a multiplicand by each digit of a multiplier to produce a respective intermediate result then shifting and adding the intermediate results to produce a final result. Barrett reduction progresses from left to right, using a quotient estimation to subtract a suitable multiple of the modulus. For example, for N and M, two integers with 2n and n bits, respectively, N may be reduced with respect to modulus M by determining a remainder of a division N/M. Modular exponentiation may then be performed via a sequence of multiply and square operations, each followed by a reduction. Thus, at any given point during exponentiation, there are two operands, A and B (where A=B for a square operation), that have size of n bits and a product is generated, N=AB that has size 2n bits. N may then be reduced as R=N mod M, where R is an n-bit integer.

Barrett reduction typically includes two n-bit multiplications and an n-bit subtraction. Modified Barrett reduction is a modification of Barrett reduction configured to reduce sizes of the multiplications to fewer than n bits. The modification is termed “folding”. Similar to unmodified Barrett reduction, a principle of the reduction method is to efficiently determine an estimate of a quotient q≈N/M followed by a subtraction R=N−qM.

Modified Barrett Reduction includes determining two constants, m prime (m′) and mu (μ), in advance (i.e., precomputing m′ and μ). The values of m′ and μ remain unchanged for the reduce operations (as long as the modulus m does not change). Determining m′ and μ in advance avoids determining them during the reduction stages. In other words, precomputing allows m′ and μ to be determined once and used a plurality of times. m′ and μ may be determined as:
m′=21.5tmodm
and

μ=⌊21.5⁢tm⌋
where m is the modulus, t is a number of bits in the modulus m and the brackets in m correspond to “floor” which corresponds to a largest integer less than a result of the operations included in the bracket.

Modified Barrett Reduction includes three reduction stages configured to reduce a square/multiply result. In other words, the three reduction stages follow a square stage or a multiply stage and if both a square and a multiply are performed, a sequence is square—reduce—multiply—reduce. As used herein, multiply stage corresponds to a square stage or a multiply stage. Thus, a multiply stage may be configured to multiply or square. As further used herein, a multiply result corresponds to a square result or a multiply result. In a first reduction stage, reduction stage 1, high order digits (e.g., bits) of the multiply result are folded to yield a reduced value a′ (i.e., reduction stage 1 result) as:

a′=a⁢⁢mod⁢⁢21.5⁢t+m′⁢⌊a21.5⁢t⌋≡a⁢⁢mod⁢⁢m
where a is the multiply result and a′ is the reduction stage 1 result. Folding is configured to decrease a size (e.g., number of bits, digits) of operands multiplied in a Barrett Reduction to reduce computational intensity and to thus improve performance. For example, a number of bits in the multiply result a is reduced from 2t to 1.5t by folding. In a second reduction stage, reduction stage2, an estimate of s (s=floor(a/m)) may be determined as:

s=⌊a′2t⌋*μ
s corresponds to an estimate of quotient q. In a third reduction stage, reduction stage 3, an estimate is subtracted from a′, the reduction stage 1 result to produce a value which is at least close to a final result as:

a′⁢mod⁢⁢m≡a′-⌊⌊a′2t⌋*μ2t⌋*m=a′-⌊s2t⌋*m
In some situations, there may be additional subtractions of the modulus to achieve the final result, i.e., a remainder less than the modulus m.

In addition to multiplication in the multiply stage, the reduction stages themselves include multiplications. For example, reduction stage 1 includes determining a product of m′ and floor (a/21.5t). In another example, reduction stage 2 includes determining a product of μ and floor (a′/2t). In another example, reduction stage 3 includes determining a product of m and floor(s/2t).

Thus, a modified Barrett reduction may be performed in three stages. A multiply result of the multiply stage is input to the first reduction stage and a result of a prior reduction stage is an input to a respective subsequent reduction stage. Thus, each reduction stage depends on a previous result. For example, the first reduction stage is configured to receive a multiply result a from the multiply stage. In another example, the second reduction stage is configured to receive a′, a result of the first reduction stage. In another example, the third reduction stage is configured to receive s, a result of the second reduction stage.

A Modified Barrett Reduction may be performed many times in the determination of a modular exponentiation result. A multiplier (e.g., multiplier circuitry) may be used to perform at least some of the multiplications associated with modular exponentiation. Performance may be enhanced by pipelining operations of the multiplier to achieve at least some parallelism. Performance may be further enhanced by ensuring that the multiplier pipeline has minimal or no gaps in operations. In other words, performance may be further enhanced by ensuring that, once a modular exponentiation has started, the multiplier is fully utilized and thus not idle waiting for a prior result.

Generally, this disclosure relates to a multiplier pipelining optimization with a postponed estimation correction. The optimization is configured to be applied to reduction stages one and two of a modified Barrett reduction. The methods and systems are configured to initiate multiplication operations associated with reduction stage 2 prior to completion of operations associated with reduction stage 1. Initiating multiplication operations associated with reduction stage2prior or completion of operations associated with reduction stage 1 is configured to ensure that a multiplier is fully utilized, i.e., that there are no gaps in the pipeline between reduction stages.

Initiating reduction stage 2 prior to completion of reduction stage 1 may not capture a carry propagation that affects the reduction stage 1 result and thus the reduction stage 2 result. Occurrence of a carry propagation is configured to trigger a correction of the result of reduction stage 2, i.e., a postponed estimation correction based, at least in part, on the carry propagation. The postponed estimation correction may be implemented by adding μ at a selected offset to the result of reduction stage 2 and, thus, the carry propagation may be accommodated. Such a correction may have little or no detrimental effect on a performance improvement associated with fully utilizing the multiplier since a likelihood of occurrence of a carry propagation is extremely small. The method and system may be configured to reorder operations associated with reduction stage 1 to reduce a likelihood of a carry propagation occurring in reduction stage1.

FIG. 1illustrates a system block diagram of a system100consistent with several embodiments of the present disclosure. System100may correspond to and/or be included in a computing device, including, but not limited to, a server, a workstation computer, a desktop computer, a laptop computer, a tablet computer (e.g., iPad®, GalaxyTab® and the like), an ultraportable computer, an ultramobile computer, a netbook computer and/or a subnotebook computer, a mobile telephone including, but not limited to, a smart phone, (e.g., iPhone®, Android®-based phone, Blackberry®, Symbian®-based phone, Palm®-based phone, etc.), etc.

System100includes a processor102, memory104, communication logic106, a multiplier110, a plurality of registers112, modular exponentiation (ME) logic114, a parameter store116and optimizer logic118. Processor102is configured to perform operations associated with system100. Processor102may include one or more processing unit(s). Memory104includes any type of memory technology, as described herein. Communication logic106is configured to provide communication of commands and/or data to and/or from system100. Such commands and/or data may be encrypted.

Registers112are configured to hold one or more parameters and/or operands related to modular exponentiation, as described herein. Parameter store116is configured to store precomputed parameters, e.g., m′ and μ. ME logic114is configured to manage operations associated with modular exponentiation, as described herein.

Multiplier110is configured to multiply a plurality of operands and to provide a result. For example, multiplier110may receive at least one operand from registers112and provide a result to registers112. In another example, multiplier110may receive a parameter from parameter store116. ME logic114may control provision of operands and/or parameters to multiplier110and may be configured to capture one or more results from multiplier112.

Multiplier110has a bit width, w. The multiplier bit width corresponds to a size of operand element that the multiplier110can multiply. For example, multiplier110bit width may be 512 bits. Continuing with this example, multiplier110may receive two operand elements, each with a bit width of 512, and may produce a product (i.e., multiply result) of 1024 bits. In another example, multiplier bit width may be greater than or less than 512 bits. An operand may include one or more operand elements that together form the operand. For example, a bit width of an operand may be 2048, 4096, 8192, etc. Thus, a 2048-bit width operand may correspond to four multiplier bit widths.

Operations of multiplier110may be pipelined. Pipelining is configured to enhance performance by facilitating parallel operations of a component, e.g., multiplier110. Pipelining may have an associated pipeline depth that corresponds to a number of operations that may be performed in parallel at given point in time. For example, multiplier110pipeline depth may be 3. In other examples, the pipeline depth associated with multiplier110may be more or less than 3.

Optimizer logic118is configured to manage optimization of modular exponentiation operations. Optimizer logic118may be configured to reorder operations of multiplier110. For example, optimizer logic118may be configured to initiate a first reduction stage to operate on an operand and to initiate a second reduction stage prior to completion of the first reduction stage, as described herein. In another example, optimizer logic118may be configured to reorder provision of a plurality of operand elements to multiplier110. The reordering is configured to reduce a likelihood that a carry propagation will occur. Optimizer logic118may be configured to determine whether a carry propagation has occurred during reduction stage 1 related to the result of reduction stage2. Optimizer logic118may be further configured to detect the carry bit(s) and perform a postponed estimate correction in reduction stage 2 if the carry propagation has occurred. The postponed estimate correction may include adding μ at a selected offset to the result (i.e., estimate s) of reduction stage2to correct the estimate, as described herein.

FIG. 2illustrates an example pipeline200consistent with various embodiments of the present disclosure. Example pipeline200corresponds to pipeline with depth three. Pipeline depth is related to a number of parallel operations that may be performed by a component, e.g., multiplier110, that is executing the operations of the pipeline. Thus, example pipeline200includes three sequences202a,202b,202c, of pipelined operations.

Example pipeline200illustrates order of operations of two stages, R1 and R2, where a result of the first stage R1 is an input to the second stage R2. In other words, R2 relies on completion of the operations associated with R1 in order to perform its operations. For example, stage R1 may correspond to a first reduction stage of a modified Barrett reduction and stage R2 may correspond to a second reduction stage of the modified Barrett reduction, as described herein. Each stage R1, R2 includes a plurality of operations R1n-5, R1n-4, R1n-3, R1n-2, R1n-1and R1nand R21, R22, R23, R24, R25and R26, respectively, that are distributed across the pipeline200. For example, the first pipe202aincludes operations R1n-5, R1n-2, R21and R24, the second pipe202bincludes operations R1n-4, R1n-1, R22and R25and the third pipe202cincludes operations R1n-3, R1n, R23and R26.

Time is increasing from left to right inFIG. 2. Thus, R1ncorresponds to a last operation of stage R1 that completes at time206and R21corresponds to a first operation of stage R2 that starts at time204. Time210is a difference between stage R1 completion time206and stage R2 initiation time204and represents an overlap between stage R1 and R2. Typically, when a second stage depends on a result from a first stage, no overlap is allowed, and initiation of operations of stage R2 may be delayed until stage R1 completion time206. Such a delay may then result in a gap in pipeline200when the component executing the pipeline, e.g., multiplier110, may be idle and thus underutilized. Performance may then be less than optimal.

FIG. 3Aillustrates an example multiplier pipeline300of depth three consistent with one embodiment of the present disclosure.FIG. 3Billustrates an operational flow diagram350related toFIG. 3A.FIGS. 3A and 3Bmay be best understood when considered together.

Multiplier pipeline300and operational flow diagram350illustrate reduction stage 1 (i.e., determination of a′ based on a and m′) and reduction stage 2 (i.e., determination of estimate s based on a′ and μ) of a modified Barrett reduction, as described herein. In this example, a bit width, i.e., size, of operand a is 2*t and t=4*w, where w is the bit width of a multiplier, e.g., multiplier110ofFIG. 1, configured to perform multiplication operations. In general, t is greater than w and t=4*w is one non-limiting example. Pipeline300illustrates an order of operations and operational flow diagram350illustrates details of the operations and results. Pipeline300and operational flow diagram350further illustrate one example of a multiplier pipelining optimization with a postponed estimation correction consistent with the present disclosure.

Turning toFIG. 3A, example multiplier pipeline300has a depth of three, i.e., pipes302,304,306. Pipelines of greater and lesser depths may be utilized consistent with the present disclosure. Each pipe302,304,306includes a plurality of respective operations and each operation generally includes a multiplication. Operations310(i.e., MU1+*R5+) and312(i.e., MU0*R4) are associated with reduction stage 2 and are configured to be initiated prior to completion of reduction stage 1. Operations314(i.e., R7*M′0) and316(i.e., R6*M′1) are associated with reduction stage 1. Operation316and/or operation318may not be complete when operations310and/or312are initiated. In this example, reduction stage 1 completes when operation318(i.e., R6*M′0) completes. Pipeline300illustrates a multiplier pipelining optimization configured to eliminate gaps and associated multiplier idle time between reduction stage 1 and reduction stage 2.

Turning toFIG. 3B, operational flow diagram350illustrates operations356,316and318associated with reduction stage 1 and operations374associated with reduction stage 2. Operation358acorresponds to reduction stage 2 operation358band is initiated prior to completion of reduction stage 1. Operations358a,358bcorrespond to operation310ofFIG. 3A. Similarly, operations362acorresponds to reduction stage 2 operation362band is initiated prior to completion of reduction stage 1. Operations362a,362bcorrespond to operation312ofFIG. 3A. In other words, operations358aand358b, illustrated as two operations in operational flow diagram350are actually one reduction stage 2 operation that is initiated prior to completion of reduction stage 1 and whose result is utilized in reduction stage 2. Similarly, operations362aand362bare actually one reduction stage 2 operation that is initiated prior to completion of reduction stage 1 and whose result is utilized in reduction stage 2.

Inputs to reduction stage 1 are a multiply result (i.e., a)352and constant parameter m′354. Thus, multiply result352is an output of a multiply stage. An output of reduction stage 1 (R5:R0 result370) corresponds to a′, i.e., folded a. A bit width of a′ is less than the bit width of a. R0 through R7 of multiply result352may be included in registers112. R0 through R7 of multiply result352correspond to operand elements. R7 of multiply result352corresponds to a most significant operand element of multiply result352and R0 of multiply result352corresponds to a least significant operand element of multiply result352. The bit width of each of R0 through R7 of multiply result352corresponds to a multiplier, e.g., multiplier110, bit width w. M′3, M′2, M′1 and M′0 are elements of parameter m′. M′3, M′2, M′1 and M′0 each have a bit width w. In this example350, left-right position corresponds to bit position in an operand and/or parameter and top to bottom is related to order of operations. Particular order of operations is illustrated by pipeline300.

Example350illustrates determination of a′ based on a352and μ354, using folding and schoolbook multiplication, as described herein. Example350further illustrates determination of estimate s based on a′ and μ as described herein. Initially, R7 and R6 of multiply result352correspond to floor(a/21.5t). Initially, R5:R0 of multiply result352correspond to R5:R0 result370and hold a mod 21.5t. During operations356,316and318, R5:R0 result370holds an intermediate result and at the completion of reduction stage 1, R5:R0 result370holds the reduction stage 1 result. At the completion of reduction stage 1, i.e., operations356,316and318, R5:R0370hold reduction stage 1 result a′. Each plus sign, e.g., plus signs361,365, indicates an addition operation of the value to the right of the respective plus sign. Additions are accumulated in R5:R0 intermediate result370. A multiplier, e.g., multiplier110, may then be configured to multiply R7 and R6 by M′3, M′2, M′1 and M′0. The multiplication results of operations356,316and318may be added to appropriate operand elements R5 through R0 of intermediate result370to yield reduction stage 1 result. Result370includes six elements of bit width w and (possibly) a carry bit371since a carry may occur as a result of an addition operation.

Operations358a,358b,362a,362band374are configured to determine an estimate s, as described herein. At the completion of reduction stage 1, R5 and R4 of result370, reduction stage 1 result, correspond to floor(a′/2t). MU1 and MU0 are elements of constant parameter μ. Thus, operations358a,358b,362a,362band374illustrate R4:5+*MU0:1+. The plus signs with MU1 and R5 indicate a possibility of a carry in those operands. A result, i.e., estimate s376, may then correspond to R4:5+*MU0:1+.

Thus, examples300,350illustrate determination of a′ (the result of reduction stage 1) and the estimate s (the result of reduction stage 2). The multiplication operations may be pipelined in multiplier110, as described herein.

Turning now toFIG. 3A, in a conventional pipelined multiplication, operation310may not be initiated until operation318has completed. In other words, reduction stage 2 may not be initiated until reduction stage 1 has completed. Such a configuration results in gaps in the pipeline300after operations316,314and318, multiplier underutilization and thus may have less than optimal performance. In an optimized multiplier pipeline with a postponed estimation correction, consistent with the present disclosure, such gaps may be eliminated and performance may be improved by initiating operations310,312prior to completion of reduction stage 1.

Operation312(i.e., MU0*R4), that corresponds to operations362a,362b, includes operand element R4 of result370. Operation310(i.e., MU1+*R5+), that corresponds to operations358a,358b, includes operand element R5 of result370. When operations310and312are initiated, prior to completion of reduction stage 1, R4 and R5 of result370may contain temporary (i.e., not yet final) respective values. For example, operation316(i.e., R6*M′1) that completes after operation310is initiated may affect R5 of result370via a carry propagation from operand element R2 of result370as a result of addition361. Since operation310includes multiplying R5+ by MU1+ and operation310is initiated prior to completion of operation316, such a carry propagation may not be captured in operation310. In other words, the temporary value of R5, that may not include the propagated carry, is used in operation310. Operation316may further affect R4 of result370via a carry from addition361. However, operation316is configured to complete prior to initiation of operation312that includes R4 of result370, thus, R4 may contain its associated final value that includes the propagated carry, if any.

Similarly, operation318(i.e., R6*M′0) may affect R4 of result370via a carry propagation from addition365. Since operation312includes multiplying R4 by MU0 and operation312is initiated prior to completion of operation318, such a carry propagation may not be captured in operation312. In other words, the temporary value of R4 of result370, that may not include the propagated carry, if any, is used in operation312.

Propagating carry(ies) associated with addition(s)361and/or365that may affect R5 and/or R4 of result370may be detected during and/or after reduction stage 1 by, e.g., optimizer logic118. The reduction stage 2 result376may then be corrected based, at least in part, on the detected propagated carry(ies). For example, if a carry propagates to R5 in reduction stage 1, estimate376may be corrected by adding μ (i.e., MU1:MU0) left shifted by element width w (i.e., μ<<w) to reduction stage 2 result376. In another example, if a carry propagates to R4 in reduction stage 1, estimate376may be corrected by adding μ to reduction stage 2 result376. In other words, propagated carry(ies) not accounted for in the temporary value(s) of R4 and/or R5 of result370may be accounted for (i.e., corrected) during reduction stage 2. Thus, optimizer logic118may be configured to perform postponed estimation correction of estimate s after a completion of reduction stage 1 and prior to a completion of reduction stage 2 in response to detecting propagate carry(ies) in reduction stage 2.

It may be appreciated that a likelihood (i.e., probability) that a carry will propagate into R4 or R5 is 2−2w. The likelihood that a carry will propagate into R4 or R5 is vanishingly small (but is not impossible). Thus, frequency of correcting for a carry propagation is similarly extremely small so that such correction has little or no effect on performance. The likelihood that a carry will propagate into higher order operand elements may be affected by an order of operations in reduction stage 1. Schoolbook multiplication may often be performed from right to left (i.e., least significant operand element to most significant operand element) but may also proceed left to right (most significant operand element to least significant operand element). The likelihood of carry propagation into higher order elements may be reduced by proceeding left to right and determining relatively more significant intermediate results that include the most significant operand element prior to determining relatively less significant intermediate results that include the least significant operand element.

Reduction stage 1 operations of example350may be configured to proceed from right to left by executing operations356,316and318from the bottom up. Reduction stage 1 operations of example350may be ordered from the top down corresponding to left to right schoolbook multiplication. Reordering the reduction stage 1 to correspond to left to right schoolbook multiplication is configured to reduce a likelihood of carry propagation into R5 and/or R4 of result370, as described herein.

Thus, performance related to modular reduction may be improved by eliminating gaps in a multiplier pipeline and reordering operations to reduce the likelihood of a carry propagation. For example, for a pipeline of depth three and assuming that each multiplier of width w consumes three time units for each multiplication, performance may be improved by about 12.5%.

FIG. 4is a flowchart400of multiplier pipelining optimization operations according to one embodiment of the present disclosure. The operations may be performed, for example, by computing system100, in particular, optimizer logic118, multiplier110and/or ME logic114ofFIG. 1.

Operations of this embodiment may begin with receiving a modulus402. A first constant, m′, may be determined at operation404. A second constant μ may be determined at operation406. For example, the first constant m′ and second constant μ may be related to a modified Barrett reduction, as described herein. Operation408includes receiving an operand. The operand may be related to a modular exponentiation. For example, the operand may correspond to a multiply result. A first reduction stage (reduction stage 1) may be initiated at operation410. A second reduction stage (reduction stage 2) may be initiated at operation412. The first reduction stage may complete at operation414.

Whether a carry propagation has occurred may be determined at operation416. For example, a carry propagation may correspond to a carry from a lower order intermediate result element. If a carry propagation has not occurred, the second reduction stage may complete at operation418. If a carry propagation has occurred, a postponed estimate correction may be performed at operation420and program flow may proceed to operation418. Operations416and420may be performed before or after operation414. A result may be output at operation422. For example, the result may correspond to a reduction stage2result, i.e., estimate s. Program flow may then proceed to operation410.

Thus, an estimate related to a modified Barrett reduction may be determined and multiplier operation may be optimized.

While the flowchart ofFIG. 4illustrate operations according various embodiments, it is to be understood that not all of the operations depicted inFIG. 4are necessary for other embodiments. In addition, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted inFIG. 4, and/or other operations described herein may be combined in a manner not specifically shown in any of the drawings, and such embodiments may include less or more operations than are illustrated inFIG. 4. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.

Memory104may include one or more of the following types of memory: semiconductor firmware memory, programmable memory, non-volatile memory, read only memory, electrically programmable memory, random access memory, flash memory, magnetic disk memory, and/or optical disk memory. Either additionally or alternatively system memory may include other and/or later-developed types of computer-readable memory.

Embodiments of the operations described herein may be implemented in a computer-readable storage device having stored thereon instructions that when executed by one or more processors perform the methods. The processor may include, for example, a processing unit and/or programmable circuitry. The storage device may include a machine readable storage device including any type of tangible, non-transitory storage device, for example, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, magnetic or optical cards, or any type of storage devices suitable for storing electronic instructions.

“Circuitry”, as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The logic may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smart phones, etc.

In some embodiments, a hardware description language (HDL) may be used to specify circuit and/or logic implementation(s) for the various logic and/or circuitry described herein. For example, in one embodiment the hardware description language may comply or be compatible with a very high speed integrated circuits (VHSIC) hardware description language (VHDL) that may enable semiconductor fabrication of one or more circuits and/or logic described herein. The VHDL may comply or be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008 and/or other versions of the IEEE VHDL standards and/or other hardware description standards.

Generally, this disclosure relates to a multiplier pipelining optimization with a postponed estimation correction. The optimization is configured to be applied to reduction stages one and two of a modified Barrett reduction. The methods and systems are configured to initiate multiplication operations associated with reduction stage 2 prior to completion of operations associated with reduction stage 1. Initiating multiplication operations associated with reduction stage2prior or completion of operations associated with reduction stage 1 is configured to ensure that a multiplier is fully utilized, i.e., that there are no gaps in the pipeline between reduction stages.

Initiating reduction stage 2 prior to completion of reduction stage 1 may not capture a carry propagation that affects the reduction stage 1 result and thus the reduction stage 2 result. Occurrence of a carry propagation is configured to trigger a correction of the result of reduction stage 2, i.e., a postponed estimation correction based, at least in part, on the carry propagation. The postponed estimation correction may be implemented by adding μ at a selected offset to the result of reduction stage 2 and, thus, the carry propagation may be accommodated. Such a correction may have little or no detrimental effect on a performance improvement associated with fully utilizing the multiplier since a likelihood of occurrence of a carry propagation is extremely small. The method and system may be configured to reorder operations associated with reduction stage 1 to reduce a likelihood of a carry propagation occurring in reduction stage1.

EXAMPLES

Examples of the present disclosure include subject material such as a method, means for performing acts of the method, a device, or of an apparatus or system related to a multiplier pipelining optimization with a postponed estimation correction, as discussed below.

According to this example there is provided a system. The system includes a register; a multiplier; and optimizer logic. The register is to store an operand. The optimizer logic is to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

This example includes the elements of example 1, wherein the optimizer logic is further to perform a postponed estimate correction of a result of the second reduction stage if the carry propagation has occurred.

This example includes the elements of example 1, wherein the optimizer logic is further to reorder provision of a plurality of elements of the operand to the multiplier, the reordering to reduce a likelihood that the carry propagation will occur.

This example includes the elements according to any one of examples 1 through 3, wherein the multiplier is to perform a plurality of pipelined multiplications of a plurality of elements of the operand.

This example includes the elements according to any one of examples 1 through 3, further including modular exponentiation (ME) logic and a parameter store, the ME logic to precompute a first constant m′ and a second constant μ and to store the first constant and second constant in the parameter store.

This example includes the elements according to any one of examples 1 through 3, wherein the operand is related to modular exponentiation.

This example includes the elements according to any one of examples 1 through 3, wherein the first reduction stage and the second reduction stage are related to a modified Barrett reduction.

This example includes the elements according to any one of examples 1 through 3, wherein a bit width of the multiplier is less than a number of bits in the operand.

This example includes the elements according to any one of examples 1 through 3, wherein the second reduction stage overlaps the first reduction stage.

This example includes the elements according to any one of examples 1 through 3, wherein the multiplier is to operate as a pipeline to perform a plurality of operations in parallel.

This example includes the elements according to any one of examples 1 through 3, wherein a bit width of the operand is in the range of 512 to 8192 bits.

This example includes the elements according to any one of examples 1 through 3, wherein the optimizer logic is further to provide a result of the first reduction stage to the second reduction stage.

This example includes the elements of example 12, wherein the optimizer logic is further to provide the result of the first reduction stage to the second reduction stage after a completion of the first reduction stage.

According to this example there is provided a method. The method includes initiating, by optimizer logic, a first reduction stage to operate on an operand; initiating, by the optimizer logic, a second reduction stage prior to completion of the first reduction stage; and determining, by the optimizer logic, whether a carry propagation has occurred.

This example includes the elements of example 14, and further includes performing, by the optimizer logic, a postponed estimate correction of a result of the second reduction stage if the carry propagation has occurred.

This example includes the elements of example 14, and further includes reordering, by the optimizer logic, provision of a plurality of elements of the operand to a multiplier, the reordering to reduce a likelihood that the carry propagation will occur.

This example includes the elements of example 14, and further includes performing, by a multiplier, a plurality of pipelined multiplications of a plurality of elements of the operand.

This example includes the elements of example 14, and further includes precomputing, by modular exponentiation (ME) logic, a first constant m′ and a second constant μ; and storing, by the ME logic, the first constant and second constant in a parameter store.

This example includes the elements of example 14, wherein the operand is related to modular exponentiation.

This example includes the elements of example 14, wherein the first reduction stage and the second reduction stage are related to a modified Barrett reduction.

This example includes the elements of example 14, wherein a bit width of a multiplier is less than a number of bits in the operand.

This example includes the elements of example 14, wherein the second reduction stage overlaps the first reduction stage.

This example includes the elements of example 14, and further includes operating, by a multiplier, as a pipeline to perform a plurality of operations in parallel.

This example includes the elements of example 14, wherein a bit width of the operand is in the range of 512 to 8192.

This example includes the elements of example 14, and further includes providing, by the optimizer logic, a result of the first reduction stage to the second reduction stage.

This example includes the elements of example 25, wherein the result of the first reduction stage is provided to the second reduction stage after a completion of the first reduction stage.

According to this example there is provided a device. The device includes a computer readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations including initiating a first reduction stage to operate on an operand; initiating a second reduction stage prior to completion of the first reduction stage; and determining whether a carry propagation has occurred.

This example includes the elements of example 27, wherein the instructions that when executed by one or more processors results in the following additional operations including performing a postponed estimate correction of a result of the second reduction stage if the carry propagation has occurred.

This example includes the elements of example 27, wherein the instructions that when executed by one or more processors results in the following additional operations including reordering provision of a plurality of elements of the operand to a multiplier, the reordering to reduce a likelihood that the carry propagation will occur.

This example includes the elements according to any one of examples 27 through 29, wherein the instructions that when executed by one or more processors results in the following additional operations including performing a plurality of pipelined multiplications of a plurality of elements of the operand.

This example includes the elements according to any one of examples 27 through 29, wherein the instructions that when executed by one or more processors results in the following additional operations including precomputing a first constant m′ and a second constant μ; and storing the first constant and second constant in a parameter store.

This example includes the elements according to any one of examples 27 through 29, wherein the operand is related to modular exponentiation.

This example includes the elements according to any one of examples 27 through 29, wherein the first reduction stage and the second reduction stage are related to a modified Barrett reduction.

This example includes the elements according to any one of examples 27 through 29, wherein a bit width of a multiplier is less than a number of bits in the operand.

This example includes the elements according to any one of examples 27 through 29, wherein the second reduction stage overlaps the first reduction stage.

This example includes the elements according to any one of examples 27 through 29, wherein the instructions that when executed by one or more processors results in the following additional operations including operating as a pipeline to perform a plurality of operations in parallel.

This example includes the elements according to any one of examples 27 through 29, wherein a bit width of the operand is in the range of 512 to 8192.

This example includes the elements according to any one of examples 27 through 29, wherein the instructions that when executed by one or more processors results in the following additional operations including providing a result of the first reduction stage to the second reduction stage.

This example includes the elements of example 38, wherein the result of the first reduction stage is provided to the second reduction stage after a completion of the first reduction stage.

According to this example there is provided a device. The device includes means for initiating, by optimizer logic, a first reduction stage to operate on an operand; means for initiating, by the optimizer logic, a second reduction stage prior to completion of the first reduction stage; and means for determining, by the optimizer logic, whether a carry propagation has occurred.

This example includes the elements of example 40, and further includes means for performing, by the optimizer logic, a postponed estimate correction of a result of the second reduction stage if the carry propagation has occurred.

This example includes the elements of example 40, and further includes means for reordering, by the optimizer logic, provision of a plurality of elements of the operand to a multiplier, the reordering to reduce a likelihood that the carry propagation will occur.

This example includes the elements according to any one of examples 40 through 42, and further includes means for performing, by a multiplier, a plurality of pipelined multiplications of a plurality of elements of the operand.

This example includes the elements according to any one of examples 40 through 42, and further includes means for precomputing, by modular exponentiation (ME) logic, a first constant m′ and a second constant μ; and means for storing, by the ME logic, the first constant and second constant in a parameter store.

This example includes the elements according to any one of examples 40 through 42, wherein the operand is related to modular exponentiation.

This example includes the elements according to any one of examples 40 through 42, wherein the first reduction stage and the second reduction stage are related to a modified Barrett reduction.

This example includes the elements according to any one of examples 40 through 42, wherein a bit width of a multiplier is less than a number of bits in the operand.

This example includes the elements according to any one of examples 40 through 42, wherein the second reduction stage overlaps the first reduction stage.

This example includes the elements according to any one of examples 40 through 42, and further includes means for operating, by a multiplier, as a pipeline to perform a plurality of operations in parallel.

This example includes the elements according to any one of examples 40 through 42, wherein a bit width of the operand is in the range of 512 to 8192.

This example includes the elements according to any one of examples 40 through 42, and further includes means for providing, by the optimizer logic, a result of the first reduction stage to the second reduction stage.

This example includes the elements of example 51, wherein the result of the first reduction stage is provided to the second reduction stage after a completion of the first reduction stage.

According to this example there is a computer readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations including the method according to any one of examples 14 to 26.

Another example of the present disclosure is a system including at least one device arranged to perform the method of any one of examples 14 to 26.

Another example of the present disclosure is a device including means to perform the method of any one of examples 14 to 26.