Power supply apparatus and error detecting method for power supply apparatus

A power supply apparatus includes a trans circuit configured to convert an input voltage into an output voltage by adjusting switching of the input voltage; an output voltage detector configured to detect the output voltage; a compensator configured to generate a control value controlling a duty ratio of the switching such that a value of the detected output voltage coincides with a target value for the output voltage; an input voltage detector configured to detect the input voltage; an estimator configured to estimate an allowed range of the control value in accordance with the target value and a value of the detected input voltage; and an adjuster configured to adjust the control value so as to stop the switching when the control value falls outside the allowed range.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2016-002270, filed on Jan. 8, 2016, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a power supply apparatus and an error detecting method for a power supply apparatus.

BACKGROUND

In a related structure, the output voltage of a power supply apparatus including a switching element may be controlled by changing a duty ratio of switching of the switching element in the power supply apparatus. In another related structure, the output voltage of a direct current to direct current converting device including a switching element may be controlled by changing a duty ratio of switching of the switching element in the direct current to direct current converting device.

Related art is disclosed in Japanese Laid-open Patent Publication No. 06-351244 and Japanese Laid-open Patent Publication No. 2003-92880.

SUMMARY

According to an aspect of the embodiment, a power supply apparatus includes a trans circuit configured to convert an input voltage into an output voltage by adjusting switching of the input voltage; an output voltage detector configured to detect the output voltage; a compensator configured to generate a control value controlling a duty ratio of the switching such that a value of the detected output voltage coincides with a target value for the output voltage; an input voltage detector configured to detect the input voltage; an estimator configured to estimate an allowed range of the control value in accordance with the target value and a value of the detected input voltage; and an adjuster configured to adjust the control value so as to stop the switching when the control value falls outside the allowed range.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a block diagram illustrating an example of configuration of a power supply apparatus that generates an output voltage from an input voltage by switching of a switching element. A power supply apparatus100includes a switching circuit5, a detecting circuit4, a target voltage setting unit1, an error arithmetic unit2, and a compensator3. The switching circuit5includes a switching element5a. The switching circuit5converts an input voltage Vin into an output voltage Vout by the switching of the switching element5a. The detecting circuit4detects the output voltage Vout output from the switching circuit5, and outputs the detected value of the output voltage Vout. The target voltage setting unit1sets a target value Vref for the output voltage Vout. The error arithmetic unit2calculates an error between the target value Vref set by the target voltage setting unit1and the output value of the output voltage Vout which output value is output from the detecting circuit4. The compensator3controls the duty ratio of the switching of the switching element5aso as to make the error zero.

In the power supply apparatus100as inFIG. 1, when a disconnection has occurred between the switching circuit5and the detecting circuit4, the output value of the detecting circuit4becomes zero (see timing t2inFIG. 2, for example), and therefore it may be determined that an abnormality due to the disconnection has occurred in the power supply apparatus100.FIG. 2is a diagram illustrating an example of changes in an output value of a detecting circuit. The detecting circuit may be the detecting circuit4illustrated inFIG. 1. However, when a degradation abnormality occurs in the power supply apparatus100, the gain of the detecting circuit4changes, and thus the output value of the detecting circuit4also changes. Therefore, when the output value of the detecting circuit4is changed to a value other than zero (see timing t1inFIG. 2, for example), it is difficult to determine whether the output value of the detecting circuit4is changed due to a variation in the output voltage Vout or is changed due to a degradation abnormality of the power supply apparatus100. As a result, the power supply apparatus100may continue operating in the state of the degradation abnormality.

It is accordingly an object of the present disclosure to protect a power supply apparatus from continuing operating in the state of a degradation abnormality.

FIG. 3is a block diagram illustrating an example of configuration of a power supply apparatus according to one embodiment. A power supply apparatus101is an example of a switching power supply that generates a direct-current output voltage Vout from a direct-current input voltage Vin by the switching of a switching element50awithin a switching circuit50. The power supply apparatus101, for example, includes the switching circuit50, an output voltage detector40, a target voltage setting unit10, an error arithmetic unit20, a compensator30, an input voltage detector60, an estimator70, an abnormality determining unit80, and an adjustor90.

The switching circuit50is an example of a trans converter that includes the switching element50aand which converts the input voltage Vin input to the switching circuit50into the output voltage Vout by the switching of the switching element50a. The switching circuit50subjects the direct-current input voltage Vin to voltage conversion, and outputs the direct-current output voltage Vout after the voltage conversion. The switching circuit50may be a step-down trans converter that steps down the input voltage Vin and which outputs the output voltage Vout after the step-down, or may be a step-up trans converter that steps up the input voltage Vin and which outputs the output voltage Vout after the step-up. Concrete examples of the switching element50ainclude a bipolar transistor, a field-effect transistor, and the like.

The output voltage detector40is an example of a detecting unit that detects the output voltage Vout output from the switching circuit50and which outputs the detected value of the output voltage Vout. The output voltage detector40detects the voltage value of the output voltage Vout, and outputs an output voltage detected value corresponding to the detected voltage value. The output voltage detector40, for example, includes a photocoupler detecting the output voltage Vout, and outputs the detected value of the output voltage Vout according to the output value of the photocoupler.

The target voltage setting unit10is an example of a setting unit that sets a target value Vref for the output voltage Vout. The target value Vref is, for example, set to a fixed reference value in advance.

The error arithmetic unit20calculates an error E between the target value Vref set by the target voltage setting unit10and the detected value of the output voltage Vout which detected value is output from the output voltage detector40. The error arithmetic unit20, for example, calculates the error E by subtracting the detected value of the output voltage Vout from the target value Vref.

The compensator30is an example of a compensator that generates a duty ratio control value Dr controlling a duty ratio D of the switching circuit50such that the detected value of the output voltage Vout which detected value is output from the output voltage detector40coincides with the target value Vref set by the target voltage setting unit10. For example, the compensator30generates the duty ratio control value Dr controlling the duty ratio D of the switching circuit50such that the error E becomes zero. The duty ratio D of the switching circuit50represents the duty ratio of the switching of the switching element50ain the switching circuit50.

The input voltage detector60is an example of a detecting unit that detects the input voltage Vin input to the switching circuit50, and which outputs the detected value of the input voltage Vin. The input voltage detector60detects the voltage value of the input voltage Vin, and outputs an input voltage detected value corresponding to the detected voltage value.

The estimator70is an example of an estimator that estimates a normal range Dx of the duty ratio control value Dr from the target value Vref set by the target voltage setting unit10and the detected value of the input voltage Vin which detected value is output from the input voltage detector60. The normal range Dx is an example of an allowed range of the duty ratio control value Dr.

The estimator70, for example, includes a duty ratio estimating unit71and a range estimating unit72. The duty ratio estimating unit71is an example of a representative value estimating unit that estimates a representative value De of the duty ratio control value Dr from the target value Vref set by the target voltage setting unit10and the detected value of the input voltage Vin which detected value is output from the input voltage detector60.

The duty ratio estimating unit71, for example, estimates the representative value De based on a representative value estimating rule for estimating the representative value De from the target value Vref set by the target voltage setting unit10and the detected value of the input voltage Vin which detected value is output from the input voltage detector60. The representative value estimating rule defines correspondence relation between the target value Vref, the detected value of the input voltage Vin, and the representative value De. The representative value estimating rule may be defined in advance by an estimation arithmetic expression, or may be defined in advance by a table (map). Respective concrete examples of the estimation arithmetic expression and the table (map) for estimating the representative value De will be described later. The estimation of the representative value De by the duty ratio estimating unit71based on the table may reduce a processing load on a CPU114(seeFIG. 11; details will be described later) when the CPU114functions as the duty ratio estimating unit71, for example.

The range estimating unit72estimates the normal range Dx from the representative value De of the duty ratio control value Dr. The representative value De is included in the normal range Dx. The range estimating unit72, for example, includes an upper limit setting unit that sets an upper limit value Dmax of the normal range Dx to a value larger than the representative value De and a lower limit setting unit that sets a lower limit value Dmin of the normal range Dx to a value smaller than the representative value De. The normal range Dx is determined by setting the upper limit value Dmax and the lower limit value Dmin. For example, the upper limit setting unit sets the upper limit value Dmax to a value obtained by increasing the representative value De by a given amount of increase, and the lower limit setting unit sets the lower limit value Dmin to a value obtained by decreasing the representative value De by a given amount of decrease.

The upper limit setting unit of the range estimating unit72, for example, estimates the upper limit value Dmax from the representative value De based on an upper limit value estimating rule defining correspondence relation between the representative value De and the upper limit value Dmax. The lower limit setting unit of the range estimating unit72, for example, estimates the lower limit value Dmin from the representative value De based on a lower limit value estimating rule defining correspondence relation between the representative value De and the lower limit value Dmin. The upper limit value estimating rule and the lower limit value estimating rule may be defined in advance by estimation arithmetic expressions, or may be defined in advance by tables (maps). Respective concrete examples of the estimation arithmetic expressions and the tables (maps) for estimating the upper limit value Dmax and the lower limit value Dmin will be described later. The estimation of the upper limit value Dmax by the upper limit setting unit of the range estimating unit72based on the table may reduce a processing load on the CPU114when the CPU114functions as the upper limit setting unit of the range estimating unit72, for example. Similarly, the estimation of the lower limit value Dmin by the lower limit setting unit of the range estimating unit72based on the table may reduce a processing load on the CPU114when the CPU114functions as the lower limit setting unit of the range estimating unit72, for example.

Alternatively, rather than estimating the representative value De from the target value Vref and the detected value of the input voltage Vin and estimating the normal range Dx from the estimated representative value De, the estimator70may estimate the normal range Dx without estimating the representative value De. For example, the estimator70estimates the normal range Dx based on an upper and lower limit estimating rule for estimating the upper and lower limit values of the normal range Dx from the target value Vref set by the target voltage setting unit10and the detected value of the input voltage Vin which detected value is output from the input voltage detector60. The upper and lower limit estimating rule includes an upper limit estimating rule defining correspondence relation between the target value Vref, the detected value of the input voltage Vin, and the upper limit value Dmax of the normal range Dx and a lower limit estimating rule defining correspondence relation between the target value Vref, the detected value of the input voltage Vin, and the lower limit value Dmin of the normal range Dx. The upper limit estimating rule and the lower limit estimating rule may be defined in advance by estimation arithmetic expressions, or may be defined in advance by tables (maps). The estimation of the upper limit value Dmax and the lower limit value Dmin by the estimator70based on the tables may reduce a processing load on the CPU114when the CPU114functions as the estimator70, for example.

The abnormality determining unit80is an example of a determining unit that determines whether or not the duty ratio control value Dr generated by the compensator30has fallen outside the normal range Dx estimated by the estimator70. When the abnormality determining unit80determines that the duty ratio control value Dr generated by the compensator30has fallen outside the normal range Dx, the abnormality determining unit80determines that a degradation abnormality has occurred in the power supply apparatus101. When the abnormality determining unit80determines that the duty ratio control value Dr generated by the compensator30has not fallen outside the normal range Dx (is within the normal range Dx), on the other hand, the abnormality determining unit80determines that no degradation abnormality has occurred in the power supply apparatus101.

The adjustor90is an example of an adjustor that adjusts the duty ratio control value Dr according to a result of determination of the abnormality determining unit80. The adjustment of the duty ratio control value Dr by the adjustor90according to the determination result of the abnormality determining unit80may reflect the determination result of the abnormality determining unit80in the duty ratio control value Dr.

Description will next be made of operation of the power supply apparatus101when a degradation abnormality occurs in the power supply apparatus101. A degradation abnormality of the power supply apparatus101represents a change in output characteristics of at least one of the compensator30, the switching circuit50, and the output voltage detector40due to a degradation. Factors in a degradation abnormality of the power supply apparatus101include, for example, a degradation in the photocoupler included in the output voltage detector40and a degradation in characteristics of an amplifying unit included in at least one of the compensator30, the switching circuit50, and the output voltage detector40.

When a degradation abnormality occurs in the power supply apparatus101, a gain K of the output voltage detector40changes, and therefore the detected value of the output voltage Vout which detected value is output from the output voltage detector40also changes. Relation between the output voltage Vout and the target value Vref in the case of the power supply apparatus101is expressed by the following equation.

G(s) denotes a gain of the compensator30, P(s) denotes a gain of the switching circuit50, and s denotes a Laplace operator. For example, when the gain K of the output voltage detector40changes due to the occurrence of a degradation abnormality in the power supply apparatus101, the output voltage Vout also changes.

FIG. 4is a timing diagram illustrating an example of operation of a power supply apparatus when a degradation abnormality occurs in the power supply apparatus. The power supply apparatus may be the power supply apparatus101illustrated inFIG. 3.

When at least one of the compensator30, the switching circuit50, and the output voltage detector40is degraded, the gain K of the output voltage detector40changes.FIG. 4illustrates a case where the gain K is decreased.

With the decrease in the gain K, the detected value of the output voltage Vout which detected value is output from the output voltage detector40decreases, and therefore the error E increases. With the increase in the error E, the compensator30raises the duty ratio control value Dr. When the abnormality determining unit80determines that the duty ratio control value Dr has exceeded the upper limit value Dmax of the normal range Dx, the abnormality determining unit80determines that a degradation abnormality has occurred in the power supply apparatus101. The abnormality determining unit80, for example, changes the level of a determination result signal R indicating a result of the determination of whether or not the duty ratio control value Dr has fallen outside the normal range Dx from an inactive level (for example, a high level) to an active level (for example, a low level). The determination result signal R at the inactive level indicates that the duty ratio control value Dr is within the normal range Dx. The determination result signal R at the active level indicates that the duty ratio control value Dr is outside the normal range Dx.

When the abnormality determining unit80determines that the duty ratio control value Dr has exceeded the upper limit value Dmax of the normal range Dx, the adjustor90adjusts the duty ratio control value Dr so as to stop the switching of the switching circuit50. For example, when the adjustor90detects the determination result signal R at the active level, the adjustor90lowers the duty ratio control value Dr to zero as illustrated inFIG. 4by multiplying the duty ratio control value Dr by zero. The voltage value of the output voltage Vout output from the switching circuit50is thereby lowered toward zero.

When the abnormality determining unit80determines that the duty ratio control value Dr has exceeded the upper limit value Dmax of the normal range Dx, the adjustor90may notify the outside of the power supply apparatus101(for example, a user and/or a given apparatus) that a degradation abnormality has occurred in the power supply apparatus101.

Hence, even when a degradation abnormality that decreases the gain K occurs in the power supply apparatus101, the output voltage Vout may be protected from continuing rising because the duty ratio control value Dr is limited with the upper limit value Dmax as an upper limit. The power supply apparatus101may therefore be protected from continuing operating in the state of the degradation abnormality. In addition, a load to which the output voltage Vout is applied (load supplied with a direct-current power from the switching circuit50) may be protected from being damaged by an excessive rise in the output voltage Vout.

When the gain K is increased due to a degradation in at least one of the compensator30, the switching circuit50, and the output voltage detector40, on the other hand, the detected value of the output voltage Vout which detected value is output from the output voltage detector40rises. When the detected value of the output voltage Vout rises, the error E decreases. With the decrease in the error E, the compensator30lowers the duty ratio control value Dr. When the abnormality determining unit80determines that the duty ratio control value Dr has become less than the lower limit value Dmin of the normal range Dx, the abnormality determining unit80determines that a degradation abnormality has occurred in the power supply apparatus101. When the abnormality determining unit80determines that a degradation abnormality has occurred in the power supply apparatus101, the abnormality determining unit80changes the level of the determination result signal R from the inactive level to the active level.

When the abnormality determining unit80determines that the duty ratio control value Dr has become less than the lower limit value Dmin of the normal range Dx, the adjustor90adjusts the duty ratio control value Dr so as to stop the switching of the switching circuit50. For example, when the adjustor90detects the determination result signal R at the active level, the adjustor90lowers the duty ratio control value Dr to zero as illustrated inFIG. 4by multiplying the duty ratio control value Dr by zero. The voltage value of the output voltage Vout output from the switching circuit50is thereby lowered toward zero.

When the abnormality determining unit80determines that the duty ratio control value Dr has become less than the lower limit value Dmin of the normal range Dx, the adjustor90may notify the outside of the power supply apparatus101(for example, a user and/or a given apparatus) that a degradation abnormality has occurred in the power supply apparatus101.

Hence, even in the case where a degradation abnormality that increases the gain K occurs in the power supply apparatus101, the duty ratio control value Dr is forcibly lowered to zero when the duty ratio control value Dr is lowered to the lower limit value Dmin. The power supply apparatus101may thereby be protected from continuing operating in a state in which a degradation abnormality that increases the gain K continues.

Description will next be made of an example of a method of detecting an abnormality in the power supply apparatus101. The method of detecting an abnormality in the power supply apparatus101is realized by processing steps illustrated inFIGS. 5 to 7.

FIG. 5is a flowchart illustrating an example of operation of a duty ratio estimating unit. The duty ratio estimating unit may be the duty ratio estimating unit71illustrated inFIG. 3. The duty ratio estimating unit71periodically repeats a series of processing (processing from a “start” to an “end”) illustrated inFIG. 5.

In step S11, the duty ratio estimating unit71obtains the target value Vref from the target voltage setting unit10, and obtains the detected value of the input voltage Vin from the input voltage detector60. In step S13, the duty ratio estimating unit71estimates the representative value De of the duty ratio control value Dr from the target value Vref and the detected value of the input voltage Vin that are obtained in step S11.

FIG. 6is a flowchart illustrating an example of operation of a range estimating unit and an abnormality determining unit. The range estimating unit and the abnormality determining unit may be the range estimating unit72and the abnormality determining unit80illustrated inFIG. 3. A series of processing (processing from a “start” to an “end”) illustrated inFIG. 6is periodically repeated. The processing from step S21to step S25is performed by the range estimating unit72. The processing from step S27to step S33is performed by the abnormality determining unit80.

In step S21, the range estimating unit72obtains the representative value De (estimated duty ratio) of the duty ratio control value Dr from the duty ratio estimating unit71.

In step S23, the range estimating unit72sets a value larger than the representative value De obtained in step S21as the upper limit value Dmax of the normal range Dx. The range estimating unit72, for example, calculates the upper limit value Dmax (upper limit duty ratio) by multiplying the representative value De by a given coefficient KU larger than one. An example of the coefficient KU will be described later.

In step S25, the range estimating unit72sets a value smaller than the representative value De obtained in step S21as the lower limit value Dmin of the normal range Dx. The range estimating unit72, for example, calculates the lower limit value Dmin (lower limit duty ratio) by multiplying the representative value De by a given coefficient KL larger than zero and smaller than one. An example of the coefficient KL will be described later. The order of step S25and step S23may be interchanged.

In step S27, the abnormality determining unit80determines whether or not the duty ratio control value Dr obtained from the compensator30is larger than the upper limit value Dmax. When the abnormality determining unit80determines that the duty ratio control value Dr is larger than the upper limit value Dmax (Yes in step S27), the abnormality determining unit80sets the level of the determination result signal R to a low level (=0) in step S31. When the duty ratio control value Dr is equal to or less than the upper limit value Dmax (No in step S27), on the other hand, the abnormality determining unit80performs the processing of step S29.

In step S29, the abnormality determining unit80determines whether or not the duty ratio control value Dr obtained from the compensator30is smaller than the lower limit value Dmin. When the abnormality determining unit80determines that the duty ratio control value Dr is smaller than the lower limit value Dmin (Yes in step S29), the abnormality determining unit80sets the level of the determination result signal R to the low level (=0) in step S31. When the duty ratio control value Dr is equal to or more than the lower limit value Dmin (No in step S29), on the other hand, the abnormality determining unit80performs the processing of step S33. In step S33, the abnormality determining unit80sets the level of the determination result signal R to a high level (=1).

Incidentally, the order of step S27and step S29may be interchanged.

FIG. 7is a flowchart illustrating an example of operation of an adjustor. The adjustor may be the adjustor90illustrated inFIG. 3. The adjustor90periodically repeats a series of processing (processing from a “start” to an “end”) illustrated inFIG. 7.

In step S41, the adjustor90obtains the determination result signal R from the abnormality determining unit80. In step S43, the adjustor90adjusts the duty ratio control value Dr according to the logic level of the determination result signal R obtained in step S41.

In step S43, when the level of the determination result signal R is the high level, the adjustor90does not adjust the duty ratio control value Dr by multiplying the duty ratio control value Dr obtained from the compensator30by one. When the level of the determination result signal R is the low level, on the other hand, the adjustor90adjusts the duty ratio control value Dr to zero by multiplying the duty ratio control value Dr obtained from the compensator30by zero. For example, when the duty ratio control value Dr obtained from the compensator30is within the normal range Dx, the value of the duty ratio control value Dr obtained from the compensator30is maintained. When the duty ratio control value Dr obtained from the compensator30is outside the normal range Dx, on the other hand, the value of the duty ratio control value Dr obtained from the compensator30becomes zero, so that the value of the duty ratio control value Dr input to the switching circuit50also becomes zero.

Hence, the above-described abnormality detecting method may determine whether or not a degradation abnormality has occurred in the power supply apparatus101by determining whether or not the duty ratio control value Dr has fallen outside the normal range Dx.

Incidentally, a cycle of the series of processing illustrated in each ofFIG. 5,FIG. 6, andFIG. 7is equal to or more than a cycle in which the compensator30generates the duty ratio control value Dr. This is because the duty ratio D changes only in a shorter time than a cycle of response of the compensator30.

Here, for example, let Vref be the target value for the output voltage Vout, let De be the representative value of the duty ratio control value Dr, let Dmax be the upper limit value of the normal range Dx, let Dmin be the lower limit value of the normal range Dx, let Vmax be a specified upper limit value of the output voltage Vout, and let Vmin be a specified lower limit value of the output voltage Vout. In this case, the range estimating unit72may calculate the upper limit value Dmax and the lower limit value Dmin according to:
Dmax=De×(Vmax/Vref)
Dmin=De×(Vmin/Vref).

FIG. 8is a timing diagram illustrating an example of changes in output voltage Vout and output current Iout of a switching circuit. The switching circuit may be the switching circuit50illustrated inFIG. 3. The specified upper limit value Vmax is a maximum value to which the output voltage Vout is allowed to vary. The specified upper limit value Vmax is specified in specifications that the load to which the output voltage Vout is applied requests from the power supply apparatus101. The specified lower limit value Vmin is a minimum value to which the output voltage Vout is allowed to vary. The specified lower limit value Vmin is specified in the specifications that the load to which the output voltage Vout is applied requests from the power supply apparatus101.

The load side requests that the power supply apparatus101keep the output voltage Vout equal to or more than the specified lower limit value Vmin even when the output current Tout is raised due to a sharp increase in a load current flowing from the switching circuit50to the load. Similarly, the load side requests that the power supply apparatus101keep the output voltage Vout equal to or less than the specified upper limit value Vmax even when the output current Tout is decreased due to a sharp decrease in the load current flowing from the switching circuit50to the load.

For example, setting the upper limit value Dmax of the normal range Dx to a value corresponding to the specified upper limit value Vmax enables the abnormality determining unit80to determine that a degradation abnormality that decreases the gain K has occurred in the power supply apparatus101when the output voltage Vout has exceeded the specified upper limit value Vmax. Similarly, setting the lower limit value Dmin of the normal range Dx to a value corresponding to the specified lower limit value Vmin enables the abnormality determining unit80to determine that a degradation abnormality that increases the gain K has occurred in the power supply apparatus101when the output voltage Vout has become less than the specified lower limit value Vmin.

“Dmax=De×(Vmax/Vref)” is an example of an estimation arithmetic expression (an example of the upper limit value estimating rule) for estimating the upper limit value Dmax from the representative value De, the specified upper limit value Vmax, and the target value Vref. “Dmin=De×(Vmin/Vref)” is an example of an estimation arithmetic expression (an example of the lower limit value estimating rule) for estimating the lower limit value Dmin from the representative value De, the specified lower limit value Vmin, and the target value Vref. (Vmax/Vref) is an example of the coefficient KU. (Vmin/Vref) is an example of the coefficient KL.

Alternatively, the range estimating unit72may estimate the upper limit value Dmax according to an upper limit value estimating table defining correspondence relation between the representative value De and the upper limit value Dmax, for example. The upper limit value estimating table is, for example, obtained by calculating the upper limit value Dmax corresponding to each representative value De according to “Dmax=De×(Vmax/Vref)” in advance. The upper limit value estimating table obtained by calculating the upper limit value Dmax corresponding to each representative value De in advance is stored in a read only memory (ROM)116or an auxiliary storage device117(seeFIG. 11; details will be described later) in advance, for example.

Similarly, the range estimating unit72may estimate the lower limit value Dmin according to a lower limit value estimating table defining correspondence relation between the representative value De and the lower limit value Dmin, for example. The lower limit value estimating table is, for example, obtained by calculating the lower limit value Dmin corresponding to each representative value De according to “Dmin=De×(Vmin/Vref)” in advance. The lower limit value estimating table obtained by calculating the lower limit value Dmin corresponding to each representative value De in advance is stored in the ROM116or the auxiliary storage device117in advance, for example.

FIG. 9is a diagram illustrating an example of configuration of a power supply apparatus in a case where degradation abnormality determination for the power supply apparatus is implemented by an analog circuit. A power supply apparatus102is one concrete example of the power supply apparatus101inFIG. 3. The power supply apparatus102, for example, includes a switching circuit51and a control circuit120. The control circuit120, for example, includes a voltage detecting circuit42, a target voltage generating circuit12, an operational amplifier22, an analog compensator32, an input voltage detecting circuit63, an estimator70, an abnormality determining unit80, and a switch92.

The switching circuit51is an example of the switching circuit50inFIG. 3. The switching circuit51is an example of a well-known forward converter including a pair of input terminals150, a pair of output terminals158, a switching element152, a transformer153, capacitors151and157, diodes154and155, and an inductor156. The switching circuit51converts an input voltage Vin input from a direct-current input power supply121to the pair of input terminals150on the primary side of the transformer153into an output voltage Vout to be output from the pair of output terminals158on the secondary side of the transformer153. The switching circuit51converts the input voltage Vin into the output voltage Vout by the switching of the switching element152coupled to a primary side coil of the transformer153. The output voltage Vout is applied to a load122via the pair of output terminals158.

The voltage detecting circuit42is an example of the output voltage detector40inFIG. 3. The voltage detecting circuit42outputs an analog detection voltage Vo by subjecting the output voltage Vout to resistance voltage division, for example.

The target voltage generating circuit12is an example of the target voltage setting unit10inFIG. 3. The target voltage generating circuit12generates a fixed target voltage as an example of the target value Vref. The operational amplifier22is an example of the error arithmetic unit20inFIG. 3. The operational amplifier22outputs an error voltage Ve. The analog compensator32is an example of the compensator30inFIG. 3. The analog compensator32generates a duty ratio control voltage Vr. The duty ratio control voltage Vr is an example of the duty ratio control value Dr. The duty ratio control voltage Vr controls a duty ratio D such that the error voltage Ve becomes zero.

FIG. 10is a diagram illustrating an example of configuration of an analog compensator. The analog compensator may be the analog compensator32illustrated inFIG. 9. The analog compensator32includes a filter circuit formed by an operational amplifier134. The analog compensator32is a well-known circuit including the operational amplifier134, a reference voltage source138, resistances131,133, and135, and capacitors132,136, and137. The analog compensator32outputs the duty ratio control voltage Vr corresponding to the error voltage Ve.

InFIG. 9, the input voltage detecting circuit63is an example of the input voltage detector60inFIG. 3. The input voltage detecting circuit63outputs an analog detected input voltage by subjecting the input voltage Vin to resistance voltage division.

The estimator70, for example, includes an analog divider75and an analog range calculating unit76. The analog divider75is an example of the duty ratio estimating unit71. The analog range calculating unit76is an example of the range estimating unit72.

In the case where the switching circuit51is the forward converter illustrated inFIG. 9, the following holds:
Vout=Vin×D

where D is the duty ratio. Hence, the analog divider75calculates the representative value De of the duty ratio control value Dr based on
D=Vout/Vin.

“D=Vout/Vin” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

The analog range calculating unit76includes an upper limit analog multiplier76aand a lower limit analog multiplier76b. The upper limit analog multiplier76ais an example of the upper limit setting unit that sets a value larger than the representative value De as the upper limit value Dmax of the normal range Dx. The upper limit analog multiplier76acalculates the upper limit value Dmax of the normal range Dx by multiplying the representative value De by the coefficient KU, for example. The lower limit analog multiplier76bis an example of the lower limit setting unit that sets a value smaller than the representative value De as the lower limit value Dmin of the normal range Dx. The lower limit analog multiplier76bcalculates the lower limit value Dmin of the normal range Dx by multiplying the representative value De by the coefficient KL, for example.

The abnormality determining unit80, for example, includes a window comparator84. The window comparator84includes an upper limit comparator84aand a lower limit comparator84b. In the present embodiment, the window comparator84outputs zero when the duty ratio control voltage Vr is higher than the upper limit value Dmax or when the duty ratio control voltage Vr is lower than the lower limit value Dmin, and the window comparator84outputs one when the duty ratio control voltage Vr is equal to or higher than the lower limit value Dmin and is equal to or lower than the upper limit value Dmax.

The switch92is an example of the adjustor90inFIG. 3. The switch92adjusts the duty ratio control voltage Vr according to the output value of the window comparator84. The switch92is off when the output value of the window comparator84is zero. The switch92is on when the output value of the window comparator84is one.

The control circuit120, for example, includes a PWM signal generating circuit119, a gate driver112, and an overvoltage protecting circuit113. PWM is an abbreviation of pulse width modulation. The PWM signal generating circuit119outputs a PWM signal according to the duty ratio control voltage Vr output from the switch92. The gate driver112switches the switching element152according to the PWM signal. The gate driver112turns off the switching element152when the overvoltage protecting circuit113detects that the analog detection voltage Vo is equal to or more than a given overvoltage threshold value.

FIG. 11is a diagram illustrating an example of configuration of a power supply apparatus in a case where degradation abnormality determination for the power supply apparatus is implemented by software. A power supply apparatus103is one concrete example of the power supply apparatus101ofFIG. 3. The power supply apparatus103, for example, includes a switching circuit51, a voltage detecting circuit42, an overvoltage protecting circuit113, a gate driver112, and a microcomputer110.

The microcomputer110, for example, includes a PWM module111, an analog-to-digital (AD) converter41, an AD converter62, a CPU114as an example of a processor, a random access memory (RAM)115, a ROM116, and an auxiliary storage device117. The auxiliary storage device117may be provided outside the microcomputer110. In the present example, the CPU114, the RAM115, and the ROM116are coupled to each other by a bus118. However, the microcomputer110is not limited to the configuration in which the CPU114, the RAM115, and the ROM116are coupled to each other by the bus118. The ROM116stores a program executed by the CPU114, various kinds of data, and the like.

FIG. 12is a block diagram illustrating a plurality of functions implemented by a CPU. The CPU may be the CPU114illustrated inFIG. 11. The CPU114functions as a target voltage setting unit10, an error arithmetic unit21, a compensator31, an input voltage obtaining unit61, an estimator70, an abnormality determining unit80, and a multiplying unit91by executing the program stored in the ROM116.

InFIG. 11, the voltage detecting circuit42and the AD converter41are an example of the output voltage detector40inFIG. 3. The voltage detecting circuit42, for example, outputs an analog detection voltage Vo by subjecting an output voltage Vout to resistance voltage division. The AD converter41converts the analog detection voltage Vo into a digital output voltage detected value, and outputs the digital output voltage detected value.

InFIG. 12, the target voltage setting unit10, for example, sets a target value Vref for the output voltage Vout to a fixed reference value stored in the ROM116in advance. The error arithmetic unit21is an example of the error arithmetic unit20inFIG. 3. The error arithmetic unit21calculates an error E. The compensator31is an example of the compensator30inFIG. 3. The compensator31generates a duty ratio control value Dr controlling the duty ratio D of the switching circuit51such that the error E becomes zero.

InFIG. 11andFIG. 12, the AD converter62and the input voltage obtaining unit61are an example of the input voltage detector60inFIG. 3. The AD converter62converts an analog input voltage Vin into a digital input voltage Vin. The input voltage obtaining unit61obtains the digital input voltage Vin.

InFIG. 12, the estimator70, for example, includes a dividing unit73and a range calculating unit74. The dividing unit73is an example of the duty ratio estimating unit71. The range calculating unit74is an example of the range estimating unit72.

In the case where the switching circuit51is the forward converter illustrated inFIG. 11, the following holds:
Vout=Vin×D

where D is the duty ratio. Hence, the dividing unit73calculates the representative value De of the duty ratio control value Dr based on
D=Vout/Vin

“D=Vout/Vin” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

The range calculating unit74includes an upper limit calculating unit74aand a lower limit calculating unit74b. The upper limit calculating unit74ais an example of the upper limit setting unit that sets a value larger than the representative value De as the upper limit value Dmax of the normal range Dx. The upper limit calculating unit74acalculates the upper limit value Dmax of the normal range Dx by multiplying the representative value De by the coefficient KU, for example. The lower limit calculating unit74bis an example of the lower limit setting unit that sets a value smaller than the representative value De as the lower limit value Dmin of the normal range Dx. The lower limit calculating unit74bcalculates the lower limit value Dmin of the normal range Dx by multiplying the representative value De by the coefficient KL, for example.

The abnormality determining unit80, for example, includes an upper limit comparing unit81, a lower limit comparing unit82, and a multiplying unit83. In the present embodiment, the upper limit comparing unit81compares the upper limit value Dmax and the duty ratio control value Dr with each other to determine magnitude relation between the upper limit value Dmax and the duty ratio control value Dr, and outputs zero when the duty ratio control value Dr is larger than the upper limit value Dmax and outputs one when the duty ratio control value Dr is equal to or less than the upper limit value Dmax. In the present embodiment, the lower limit comparing unit82compares the lower limit value Dmin and the duty ratio control value Dr with each other to determine magnitude relation between the lower limit value Dmin and the duty ratio control value Dr, and outputs zero when the duty ratio control value Dr is smaller than the lower limit value Dmin and outputs one when the duty ratio control value Dr is equal to or more than the lower limit value Dmin. The multiplying unit83outputs a product of the output value of the upper limit comparing unit81and the output value of the lower limit comparing unit82.

The multiplying unit91is an example of the adjustor90inFIG. 3. The multiplying unit91adjusts the duty ratio control value Dr by multiplying the duty ratio control value Dr by the output value of the multiplying unit83.

InFIG. 11, the PWM module111outputs a PWM signal according to the duty ratio control value Dr output from the multiplying unit91. The gate driver112switches the switching element152according to the PWM signal. The gate driver112turns off the switching element152when the overvoltage protecting circuit113detects that the analog detection voltage Vo is equal to or more than a given overvoltage threshold value.

FIG. 13is a diagram illustrating an example of configuration of a switching circuit. A switching circuit52is an example of the switching circuit50inFIG. 3. The switching circuit52is an example of a well-known step-down converter including a switching element251, a capacitor254, a diode252, and an inductor253.

In the case where the switching circuit52is the step-down converter illustrated inFIG. 13, the following holds:
Vout=Vin×D

where D is the duty ratio. Hence, the duty ratio estimating unit71inFIG. 3calculates the representative value De of the duty ratio control value Dr based on
D=Vout/Vin.

“D=Vout/Vin” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

FIG. 14is a diagram illustrating an example of configuration of a switching circuit. A switching circuit53is an example of the switching circuit50inFIG. 3. The switching circuit53is an example of a well-known step-up converter including a switching element352, a capacitor354, a diode353, and an inductor351.

In the case where the switching circuit53is the step-up converter illustrated inFIG. 14, the following holds:
Vout=Vin/(1−D)

where D is the duty ratio. Hence, the duty ratio estimating unit71inFIG. 3calculates the representative value De of the duty ratio control value Dr based on
D=1−(Vin/Vout).

“D=1−(Vin/Vout)” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

FIG. 15is a diagram illustrating an example of configuration of a switching circuit. A switching circuit54is an example of the switching circuit50inFIG. 3. The switching circuit54is an example of a well-known step-up/step-down converter including a switching element451, a capacitor454, a diode453, and an inductor452.

In the case where the switching circuit54is the step-up/step-down converter illustrated inFIG. 15, the following holds:
Vout=−Vin(D/(1−D))

where D is the duty ratio. Hence, the duty ratio estimating unit71inFIG. 3calculates the representative value De of the duty ratio control value Dr based on
D=−Vout/(Vin −Vout).

“D=−Vout/(Vin−Vout)” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

FIG. 16is a diagram illustrating an example of configuration of a switching circuit. A switching circuit55is an example of the switching circuit50inFIG. 3. The switching circuit55is an example of a well-known flyback converter including a switching element551, a capacitor557, a diode556, and a transformer552. The transformer552includes an exciting coil553, a primary side coil554, and a secondary side coil555.

In the case where the switching circuit55is the flyback converter illustrated inFIG. 16, the following holds:
Vout=Vin×(D/(1−D))×(N2/N1)

where D is the duty ratio, N1 is the number of turns of the primary side coil554, and N2 is the number of turns of the secondary side coil555. Hence, when N1 and N2 are equal to each other, for example, the duty ratio estimating unit71inFIG. 3calculates the representative value De of the duty ratio control value Dr based on
D=−Vout/(Vin −Vout).

“D=−Vout/(Vin−Vout)” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

FIG. 17is a diagram illustrating an example of configuration of a switching circuit. A switching circuit56is an example of the switching circuit50inFIG. 3. The switching circuit56is an example of a well-known forward converter including a switching element651, a capacitor660, diodes652,657, and658, an inductor659, and a transformer661. The transformer661includes an exciting coil653, primary side coils654and655, and a secondary side coil656.

In the case where the switching circuit56is the forward converter illustrated inFIG. 17, the following holds:
Vout=Vin×D×(N2/N1)

where D is the duty ratio, N1 is the number of turns of the primary side coils654and655combined, N2 is the number of turns of the secondary side coil656. Hence, when N1 and N2 are equal to each other, for example, the duty ratio estimating unit71inFIG. 3calculates the representative value De of the duty ratio control value Dr based on
D=Vout/Vin.

“D=Vout/Vin” is an example of an estimation arithmetic expression for estimating the representative value De from the target value Vref and the detected value of the input voltage Vin.

A power supply apparatus, a program for detecting an abnormality in the power supply apparatus, and a method for detecting an abnormality in the power supply apparatus have been described above based on the embodiments. However, the present disclosure is not limited to the foregoing embodiments. Various modifications and improvements such as combination with a part or the whole of another embodiment, replacement, and the like may be made within the scope of the present disclosure.