Skew cancellation for source synchronous clock and data signals

The skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled. For programmable skew cancellation, a skew value corresponding to the amount of the skew is determined and programmed into a data storage device. Sampling clock signals of the same frequency but different phases are generated from the clock signal, and one of the sampling clock signals having the desired phase is selected depending on the programmed skew value. Alternatively, for automatic skew cancellation, a phase locked loop compares the received data signal to one of the sampling clock signals to determine the skew value for selecting the sampling clock signal having the desired phase. Stable bit values of the data signal are then sampled with the selected sampling clock signal.

TECHNICAL FIELD

This invention relates generally to source synchronous data communications, and more particularly, to a method and system for canceling/calibrating for skew between clock and data signals that are source synchronous.

BACKGROUND

FIG. 1shows a conventional source synchronous communications system100for data communications between a first low speed data processor102and a second low speed data processor104. A plurality of high speed data channels including a first high speed data channel106, a second high speed data channel108, and so on, up to an Nth high speed data channel110, are coupled between a source synchronous transmitter112and a source synchronous receiver114.

The data processors102and104are “low speed” in that they generate V-bits of parallel data bits at a frequency that is V-times lower than the frequency of serial data transmission through the “high speed” data channels106,108, and110. The source synchronous transmitter112serializes the parallel V-bits for serial data transmission through the data channels106,108, and110. Thus, the source synchronous transmitter112is comprised of a respective transmitter serializer for each of the high speed data channels106,108, and110.

A first transmitter serializer116receives a first parallel V-bits from the first low speed data processor102and serializes such V-bits to generate serial data bits SDOUT1transmitted via the first high speed data channel106. Similarly, a second transmitter serializer118receives a second parallel V-bits from the first low speed data processor102and serializes such V-bits to generate serial data bits SDOUT2transmitted via the second high speed data channel108. In addition, an Nth transmitter serializer120receives an Nth parallel V-bits from the first low speed data processor102and serializes such V-bits to generate serial data bits SDOUTN transmitted via the Nth high speed data channel110.

A transmitter PLL (phase locked loop)122receives a transmit clock signal, from the first low speed data processor102, that is synchronized with each of the V-bits generated for the transmitter serializers116,118, and120. For example, each of the V-bits is generated for the transmitter serializers116,118, and120for every clock cycle of the transmit clock signal from the first low speed data processor102. The transmitter PLL122generates a high speed transmit clock signal (HSTCLK) with a frequency that is V-times the frequency of the transmit clock signal from the first low speed data processor102.

Each of the transmitter serializers116,118, and120uses HSTCLK from the transmitter PLL122to generate the serial data bits SDOUT1, SDOUT2, and SDOUTN from the respective parallel V-bits. In addition, each of the high speed data channels106,108, and110transmits the serial data bits SDOUT1, SDOUT2, and SDOUTN at the higher frequency of HSTCLK.

The transmitter PLL122also generates a transmitted clock signal (CLKOUT) that is transmitted via a clock data channel124. CLKOUT has the lower frequency of the transmit clock signal from the data processor102and is synchronized with the serial data bits SDOUT1, SDOUT2, and SDOUTN. For example, V-bits of the serial data bits SDOUT1, SDOUT2, and SDOUTN may be generated every cycle of CLKOUT. Thus, the transmitted data bits SDOUT1, SDOUT2, and SDOUTN and the transmitted clock signal CLKOUT are termed “source synchronous”. In addition, the high speed data channels106,108, and110and the synchronized clock signal CLKOUT comprise a “source synchronous link group”.

A plurality of receiver deserializers comprise the source synchronous receiver114including a first receiver deserializer126, a second receiver deserializer128, and so on, up to an Nth receiver deserializer130. In addition, a receiver PLL (phase locked loop)132receives a received clock signal CLKIN which is the transmitted clock signal CLKOUT transmitted via the clock data channel124. The receiver PLL132generates a high frequency sampling clock signal SCLK to be used by each of the receiver deserializers126,128, and130for sampling a respective received data signal. The frequency of SCLK is V-times the frequency of the received clock signal CLKIN.

Received serial bits data signals SDIN1, SDIN2, and SDINN are the transmitted serial data bits SDOUT1, SDOUT2, and SDOUTN, respectively, transmitted via the high speed data channels106,108, and110, respectively. The first receiver deserializer126samples the first received serial bits data signal SDIN1using SCLK to generate a parallel V-bits data signal for the second low speed data processor104. Similarly, the second receiver deserializer128samples the second received serial bits data signal SDIN2using SCLK to generate a parallel V-bits data signal for the second low speed data processor104. In addition, the third receiver deserializer130samples the Nth received serial bits data signal SDINN using SCLK to generate a parallel V-bits data signal for the second low speed data processor104.

The receiver PLL132also generates a parallel data clock signal that is the low speed received clock signal CLKIN delayed by a predetermined time period. The parallel data clock signal is synchronized with the parallel V-bits generated by the receiver deserializers126,128, and130and is used by the second low speed data processor104for processing such parallel V-bits from the receiver deserializers126,128, and130.

FIG. 2shows the components within the transmitter PLL122and within one of the transmitter serializers116,118, or120, such as the Nth transmitter serializer120for example. The transmitter serializer120is comprised of a parallel to serial shift register134, and the transmitter PLL122is comprised of a xV frequency multiplier136and a 1/V frequency divider138.FIG. 3shows a timing diagram during operation of the transmitter serializer120and the transmitter PLL122ofFIG. 2.

Referring toFIGS. 2 and 3, a symbol comprised of the parallel V-bits, TD<1:V>140 inFIG. 3and the low frequency transmit clock signal142are generated by the first low speed data processor102. The shift register134uses an edge of the transmit clock signal142for loading in the symbol of the parallel V-bits. For example, an Nth symbol of the parallel V-bits140is loaded into the shift register at a rising edge144of a cycle152of the transmit clock signal142.

The xV frequency multiplier136generates HSTCLK146inFIG. 3by multiplying the frequency of the transmit clock signal142by V-times. In addition, the 1/V frequency divider generates CLKOUT148inFIG. 3by dividing the frequency of HSTCLK146by V-times. Thus, the frequency of CLKOUT148is substantially same as the frequency of the transmit clock signal142.

In addition, the shift register134uses HSTCLK146to shift out the bits within the shift register134as the serial data bits SDOUT150. For example, referring toFIGS. 2 and 3, each serial bit of SDOUT150is shifted out at each rising edge of HSTCLK146. The symbol of V-bits shifted out as serial data bits is synchronized to an edge of the transmit clock signal142and thus of CLKOUT148. For example inFIG. 3, the Nth symbol of V-bits is generated as the serial data bits SDOUT150after two cycles of HSTCLK146(i.e., with two bits of delay) after the rising edge144of the transmit clock142or of CLKOUT148. Such a delay is typically to account for the sample and hold time during loading of the Nth symbol of V-bits into the shift register134at the rising edge144. Nevertheless, the serial data output signal SDOUT150is synchronized with the transmitted clock signal CLKOUT148.

Such a parallel to serial shift register134, xV frequency multiplier136, and 1/V frequency divider138are each individually known to one of ordinary skill in the art of electronics. In addition, each of the transmitter serializers116,118, and120has a respective parallel to serial shift register similar to the shift register134ofFIG. 2that each uses the one HSTCLK from the transmitter PLL122for generating the respective serial data bits SDOUT1, SDOUT2, and SDOUTN.

FIG. 4shows the components within the receiver PLL132and within one of the receiver deserializers126,128, and130such as the Nth receiver deserializer130for example. The receiver deserializer130is comprised of a serial to parallel shift register162, and the receiver PLL132is comprised of a xV frequency multiplier164and a re-timer166.FIG. 5shows a timing diagram during operation of the receiver deserializer130and the receiver PLL132ofFIG. 4.

Referring toFIGS. 4 and 5, the xV frequency multiplier164generates SCLK174by multiplying the frequency of CLKIN172by V-times. In addition, the shift register162uses SCLK174to sample in and shift SDIN176at every rising edge of SCLK174. The re-timer166generates the parallel data clock signal178by delaying CLKIN172a predetermined time period using SCLK174.

The shift register162also uses the parallel data clock signal178for shifting out a symbol of parallel V-bits RD<1:V>180, at every rising edge of the parallel data clock signal178. The re-timer166determines the timing of the rising edge of the parallel data clock signal178to ensure that the V-bits of a symbol are stabilized within the shift register162before being shifted out to the second low speed data processor104. For example, a symbol of V-bits as sampled by the shift register162is two-bits delayed from a rising edge of CLKIN, and the re-timer is designed for such a known delay. At any rate, the received serial bits data signal SDIN176and the received clock signal CLKIN172are synchronized such that CLKIN172is used for defining the symbol boundaries of the V-bits.

Such a serial to parallel shift register162, xV frequency multiplier164, and re-timer166are each individually known to one of ordinary skill in the art of electronics. In addition, each of the receiver deserializers126,128, and130has a respective serial to parallel shift register similar to the shift register162ofFIG. 4that each uses the one SCLK from the receiver PLL132for sampling the respective received serial bits data signal SDIN1, SDIN2, or SDINN.

Referring toFIGS. 1,5, and6, the received clock signal CLKIN172and the received serial bits data signal SDIN176are transmitted via different data channels. Each of such different data paths is likely to have different delays such that CLKIN172and SDIN176are skewed. Referring toFIGS. 5 and 6, SCLK174is generated from CLKIN172with a rising edge of CLKIN172being aligned to a falling edge of SCLK174. In that case, each rising edge of SCLK174is used for sampling SDIN176.

FIG. 6illustrates an ideal SDIN182that is not skewed with respect to the received clock signal CLKIN172. The ideal SDIN182has a stable bit time184during which the bit value does not change within a total bit time186. On the other hand, the value of SDIN182jitters within the bit time186out-side of the stable bit time184(as indicated by the cross-hatching inFIG. 6) and may change in bit-value with such jitter. The stable bit time184is typically about 50% of the total bit time186.

For the ideal SDIN182, the rising edge of SCLK174occurs substantially at the center of the stable bit time184such that a valid bit value is sampled.FIG. 6also illustrates a skewed SDIN188that is skewed from CLKIN172by a skew time period190. With such a skewed SDIN188, the rising edge of SCLK174occurs during jitter of the skewed SDIN188such that the sampled bit value may not be valid.

Nevertheless, referring toFIG. 1, since the received clock signal CLKIN and the received serial bits data signal SDIN are transmitted via different data channels, such skew between such signals is likely to occur. For example, assume that SDIN is transmitted at 1 Gbps (giga-bits per second) such that each bit time is 1000 ps (pico-seconds) and such that the stable bit time184is 500 ps. In addition, assume that the serial to parallel shift register162requires a set-up and hold time of 100 ps for sampling the bit value. In that case, a skew of +/−200 ps may be tolerated by the source synchronous receiver114of the prior art. However, each of the data channels106,108,110, and124, which are typically comprised of PC board traces, connectors, termination resistors, and/or cables, may contribute more than the tolerated skew such as even a skew of over 30 ns (nano-seconds).

Thus, a mechanism is desired for accounting for the skew between the received clock signal CLKIN and the received serial bits data signal SDIN for sampling valid data bits of SDIN.

SUMMARY

Accordingly, in a general aspect of the present invention, the skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled.

In one example embodiment, programmable skew cancellation is performed when the amount of the skew is less than a predetermined percentage of the bit time of the received data signal. In such programmable skew cancellation, a skew value corresponding to the amount of the skew is programmed into a data storage device. A sampling clock signal is generated from the received clock signal, and the phase of the sampling clock signal is selected depending on the programmed skew value. The received data signal is then sampled with this sampling clock signal.

In another embodiment of the present invention, automatic skew calibration is performed when the amount of the skew is equal to or greater than the predetermined percentage of the bit time of the received data signal. In such automatic skew calibration, a source synchronous transmitter serializer transmits a sync pattern of data bits during a training time period for the received data signal. A clock recovery phase locked loop uses such a sync pattern of the received data signal to determine a phase of the sampling clock signal that is used for sampling the received data signal.

In addition, skew cancellation or calibration is performed within a respective receiver deserializer for each of a plurality of data channels for canceling a respective skew with respect to the received clock signal of a corresponding received data signal transmitted via each of the plurality of data channels. Because each of the receiver deserializers accounts for such respective skew, the skew tolerance through each of the plurality of data channels is loosened for easier design of the data channels.

These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, and16refer to elements having similar structure and function.

DETAILED DESCRIPTION

Referring toFIG. 7, a source synchronous receiver deserializer200according to an aspect of the present invention includes a serial to parallel shift register202for inputting a received serial bits data signal SDIN. In addition, the receiver deserializer200also includes components for generating a sampling clock signal SCLKNEWand a parallel data clock signal from a received clock signal CLKIN.

For generating the sampling clock signal SCLKNEW, a data storage device204stores three data bits SELECT<0:2> programmed into the data storage device204. A decoder206decodes the three data bits SELECT<0:2> to generate multiplexer control signals S<1:8>. A clock circuit, such as a xV frequency clock synthesizer208, inputs CLKIN and generates a plurality of high speed sampling clock signals HSCLK<1:8>,222,224,226,228,230,232,234, and236illustrated in the timing diagram ofFIG. 8for example.

A multiplexer210receives HSCLK<1:8> from the clock synthesizer208and selects one of them as SCLKNEW, depending on the control signals S<1:8> from the decoder206. For example, referring toFIG. 8, each of the eight sampling clock signals HSCLK<1:8> are successively phase shifted from each other by 45°. Given SDIN238inFIG. 8, the sixth HSCLK6232is desired as SCLKNEW242having the rising edges centered about a stable bit time240of each cycle of SDIN238.

SCLKOLD244inFIG. 8is the SCLK signal generated by the xV frequency multiplier164ofFIG. 4from the received clock signal CLKIN. It is shown for comparison to SCLKNEW. Because of the skew between CLKIN and SDIN238, the rising edges of SCLKOLD244occur during jitter of SDIN238outside of the stable bit time240. Thus, data bits sampled by SCLKOLD244would not be valid. The phase shift246between SCLKOLD244and SCLKNEW242indicates the amount of skew between CLKIN and SDIN238.

FIG. 9shows the timing diagram during operation of the receiver deserializer200ofFIG. 7. Referring toFIGS. 7,8, and9, SCLKNEW242is generated from the multiplexer210as the sixth HSCLK6232. Thus, the falling edge of SCLKNEW242is phase shifted from the rising edge of the CLKIN252by the skew time period246inFIGS. 8 and 9. The rising edges of SCLKNEW242are used for sampling SDIN238(shown inFIG. 9without the jitter regions for clarity of illustration).

Referring toFIGS. 7 and 9, the source synchronous receiver deserializer200includes a delay circuit213for generating the parallel data clock signal254from CLKIN252and SCLKNEW242. In one embodiment of the present invention, the parallel data clock signal254is CLKIN252delayed by a predetermined number of cycles258of SCLKNEW242. An edge of the parallel data clock signal254, such as the rising edge inFIG. 9, is used by the serial to parallel shift register202to shift out a symbol of V-bits RD<1:V>256 to the second low speed data processor104. Such a delay258between CLKIN252and the parallel data clock signal254ensures that the V-bits of a symbol are stabilized within the serial to parallel shift register202before being shifted out to the second low speed data processor104.

In this manner, for programmable skew cancellation, the amount of skew246between CLKIN252and SDIN238is first determined. Mechanisms for determining such an amount of skew246are known to one of ordinary skill in the art of source synchronous data communication. For example, during calibration of a source synchronous communications system600ofFIG. 15using the receiver deserializer200, the amount of skew246between CLKIN252and SDIN238is determined using signal measuring equipment such as an oscilloscope coupled at the inputs to a source synchronous receiver602.

Then, the three bits SELECT<0:2> are programmed into the data storage device204to indicate such an amount of the skew246. The data storage device204may be part of a PLD (programmable logic device) that is programmed to store the amount of the skew246during calibration of the source synchronous communications system600ofFIG. 15using the receiver deserializer200. The programmed three bits SELECT<0:2> determine the phase of SCLKNEW242from the multiplexer210such that the rising edges of SCLKNEW242occur within the stable bit time period of SDIN238.

In one embodiment of the present invention, the programmed three bits SELECT<0:2> determine which of HSCLK<1:8> 222, 224, 226, 228, 230, 232, 234, and 236 ofFIG. 8is selected as SCLKNEW242. However, more bits indicating the amount of the skew246may be programmed for selecting from more numerous high speed clock signals generated by the clock synthesizer208. Mechanisms for programming the bits SELECT<0:2> into the data storage device204are known to one of ordinary skill in the art of electronics. In addition, implementation of each of the components202,204,206,208,210, and213, individually, is known to one of ordinary skill in the art of electronics.

Referring toFIGS. 6 and 7, the programmable skew cancellation with the source synchronous receiver deserializer200ofFIG. 7is useful when the amount of the skew190is less than a predetermined percentage of the total bit time186. For example, assume that the stable bit time184is 50% of the total bit time186, and that the serial to parallel shift register202requires 10% of the total bit time for sample and hold during sampling a bit value of SDIN. In that case, the programmable skew cancellation with the source synchronous receiver deserializer200ofFIG. 7is useful when the amount of the skew190is less than +/−40% (which is 50% minus X % that is the sample and hold time percentage for the shift register202) of the total bit time186.

A positive skew percentage means the rising edges of SCLKOLD174lead the centers of the stable bit time periods184by that percentage of the total bit time186, and a negative skew percentage means the rising edges of the SCLKOLD174lag the centers of the stable bit time periods184by that percentage of the total bit time186. Referring toFIG. 8, one of the plurality of sampling clock signals HSCLK<1:8>,222,224,226,228,230,232,234, and236can cancel the skew between CLKIN and SDIN when the amount of the skew246is less than the predetermined percentage (which is 50% minus the sample and hold time percentage of the shift register202) of the total bit time186.

If the amount of the skew246is greater than such a predetermined percentage of the total bit time186, then the source synchronous receiver deserializer300ofFIG. 10is used for automatic skew calibration according to another embodiment of the present invention. The receiver deserializer300includes a serial to parallel shift register302for sampling SDIN into parallel V-bits data. The receiver deserializer300also includes components for generating a sampling clock signal SCLKNEWand a parallel data clock signal from CLKIN. The receiver deserializer300also includes a calibration enable logic310and a 1/V frequency divider312.

For generating SCLKNEW, a clock recovery PLL (phase locked loop)304uses SDIN for generating multiplexer control signals S<1:8> sent to a multiplexer306. A clock circuit, such as xV frequency clock synthesizer308, inputs CLKIN and generates a plurality of high speed sampling clock signals HSCLK<1:8> (such as222,224,226,228,230,232,234, and236ofFIG. 8for example).

The multiplexer306inputs the plurality of sampling clock signals HSCLK<1:8> and selects one of them as SCLKNEW, depending on the control signals S<1:8> from the clock recovery PLL304. The clock recovery PLL304compares the current phase of SCLKNEWand the phase of SDIN and adjusts the control signals S<1:8> until SCLKNEWand SDIN are “in-phase”. Referring toFIG. 8for example, SCLKNEWand SDIN are considered “in-phase” when a rising edge of SCLKNEWoccurs at the center of the stable bit time period240.

FIG. 11shows a timing diagram during operation of the source synchronous receiver deserializer300ofFIG. 10. Referring toFIGS. 10 and 11, the clock recovery PLL304and the multiplexer306operate to generate SCLKNEW320that is “in-phase” with SDIN322, during an initial training period324. Referring toFIGS. 10 and 11, a transmitter serializer314generates SDOUT that is transmitted via a high speed data channel316to the source synchronous deserializer receiver300. At power up, the transmitter serializer314generates sync patterns for SDOUT (and thus for SDIN). For example, the sync pattern is comprised of a repeating pattern of bytes, such as with each byte having a pattern of four low bits followed by four high bits (i.e., “00001111”)

In addition, for invoking automatic skew calibration during the initial training period320, the calibration enable logic310asserts a CAL control signal326at a first time point328. When the clock recovery PLL receives the asserted CAL control signal326, the clock recovery PLL304and the multiplexer306operate to adjust the phase of SCLKNEW320until SCLKNEW320is “in-phase” with SDIN322. For example, when the rising edges of SCLKNEW320lead the centers of the stable bit time periods of SDIN, the clock recovery PLL adjusts the control signals S<1:8> such that the multiplexer306selects another one of the high speed sampling clock signals HSCLK<1:8> having a lower phase shift.

On the other hand, when the rising edges of SCLKNEW320lag the centers of the stable bit time periods of SDIN, the clock recovery PLL adjusts the control signals S<1:8> such that the multiplexer306selects another one of the high speed sampling clock signals HSCLK<1:8> having a higher phase shift. After such adjustments, when the rising edges of SCLKNEWsubstantially coincide with the centers of the stable bit time periods of SDIN, the clock recovery PLL locks into that SCLKNEWand asserts a LOCK control signal330at a second time point332. The LOCK control signal330was initially de-asserted when the clock recovery PLL304was enabled with the asserted CAL control signal326at the first time point328.

Referring toFIGS. 10 and 11, the 1/V frequency divider312divides the frequency of SCLKNEWto generate the parallel data clock signal having the lower frequency. In addition, the serial to parallel shift register302samples the SDIN322at every rising edge of SCLKNEW320and shifts out V-bits of parallel data RD<1:V>334at every rising edge of the parallel data clock signal. After the LOCK control signal330is asserted at time point332, the sync pattern begins to appear in the V-bits of parallel data RD<1:V>334output by the serial to parallel shift register302.

After the LOCK control signal330is asserted at time point332, the calibration enable logic de-asserts the CAL control signal to disable the clock recovery PLL304from further adjusting the phase of SCLKNEW. Once SCLKNEWis considered to be “in-phase” with SDIN, the phase of SCLKNEWis locked for subsequent operation of the source synchronous receiver deserializer300. The length of the training period324when the transmitter serializer314transmits the sync pattern for SDIN is designed to sufficiently surround the time period when the CAL control signal326is asserted. After the training period324, the transmitter serializer314transmits the real serial data to be processed by the receiving low speed data processor104.

In this manner, automatic skew calibration is performed when the transmitter serializer314generates the sync pattern for SDIN during the training period324and when the CAL control signal326is asserted. With such automatic skew calibration, the clock recovery PLL304and the multiplexer306adjust the phase of SCLKNEWuntil the phase of SCLKNEWis substantially “in-phase” with SDIN. Implementation of each of the components302,304,306,308,310,312,314, and316inFIG. 10, individually, is known to one of ordinary skill in the art of electronics.

In an alternative embodiment of the present invention, components of a CDR (clock data recovery) receiver deserializer may be configured for performing the programmable skew cancellation of the components ofFIG. 7and the automatic skew calibration of the components ofFIG. 10.FIG. 12shows the prior art components of a CDR receiver deserializer400including a clock recovery PLL (phase locked loop)402that inputs SDIN for generating a recovered serial clock signal (SCLK) from SDIN. SCLK is input by a 1/V frequency divider404and a serial-to-parallel shift register406. The serial-to-parallel shift register406samples SDIN at every rising edge of SCLK.

The 1/V frequency divider404generates a recovered parallel clock signal (RPCLK) having a cycle for every “V” cycles of SCLK. The recovered parallel clock signal (RPCLK) is input by the serial-to-parallel shift register406to generate a recovered parallel data output (RPDO) comprised of V-bits of SDIN at a rising edge of RPCLK. A SYNC detect logic408asserts a VRS (diVider ReSet) signal (i.e., a parallel clock enabling signal) for determining the timing of the rising edge of every cycle of RPCLK such that SDIN is properly partitioned to generate each of the V-bits of RPDO. The SYNC detect logic408inputs SDIN and asserts the VRS signal at the occurrence of a sync pattern within SDIN. Such a CDR receiver deserializer400and such operations and components402,404,406, and408of the CDR receiver deserializer400are known to one of ordinary skill in the art of CDR SERDES (serializer/deserializer) transceivers.

FIG. 13shows the components of the clock recovery PLL402ofFIG. 12including a phase detector410, a digital filter412, and a phase selector414for generating SCLK from SDIN. The phase selector410inputs the high speed sampling clock signals HSCLK<1:8> from a xV frequency clock synthesizer416and selects one of them as the recovered serial clock signal (SCLK). The phase selector414selects one of the clock signals HSCLK<1:8> as SCLK depending on FWD and BWD control signals from the digital filter412. The phase detector410compares the phases of SDIN and SCLK and generates the FWD and BWD, control signals to adjust the phase of SCLK until the phase of SCLK becomes substantially “in phase” with the phase of SDIN. Such a clock recovery PLL402and such operations and components410,412, and414of the clock recovery PLL402are known to one of ordinary skill in the art of CDR SERDES (serializer/deserializer) transceivers.

Referring toFIGS. 12,13, and14, the components of the CDR receiver deserializer400ofFIG. 12are configured to form a source synchronous receiver deserializer500ofFIG. 14with programmable skew cancellation and automatic skew calibration, according to another embodiment of the present invention. Referring toFIGS. 7,10,12, and14, elements having the same reference number refer to elements having similar structure and function. ComparingFIGS. 10,12, and14, the clock recovery PLL304ofFIG. 10is implemented with the clock recovery PLL402ofFIG. 12. In addition, the multiplexer306ofFIG. 14may be part of the phase selector414that is also a part of the clock recovery PLL402. Furthermore, a first mode multiplexer502and a second mode multiplexer504are added.

FIG. 15shows a source synchronous communications system600of an embodiment of the present invention using the receiver deserializer500ofFIG. 14. Referring toFIGS. 1 and 15, elements having the same reference number refer to elements having similar structure and function. ComparingFIGS. 1 and 15, the receiver PLL132ofFIG. 1is no longer used in the source synchronous receiver602ofFIG. 6. In addition, each of the receiver deserializers126,128, and130ofFIG. 1are replaced with a corresponding receiver deserializer604,606, and608, respectively, that are each substantially similar to the receiver deserializer500ofFIG. 14.

FIG. 16shows a flow-chart of steps during operation of the receiver deserializer500ofFIG. 14as each of the receiver deserializers604,606, and608inFIG. 15. The receiver deserializer500inputs CLKIN from the clock data channel124and a respective SDIN from a respective one of the high speed data channels106,108, and110. Referring toFIGS. 14 and 16, an amount of skew between such SDIN and CLKIN is determined (step702ofFIG. 16).

Mechanisms for determining such an amount of skew is known to one of ordinary skill in the art of SERDES (serializer/deserializer) transceivers. For example, during calibration of a source synchronous communications system600ofFIG. 15using the receiver deserializer200, the amount of skew246between CLKIN252and SDIN238is determined using signal measuring equipment such as an oscilloscope coupled at the inputs to a source synchronous receiver602.

Then, a decision is made as to whether such an amount of skew is less than a predetermined percentage of the total bit time of SDIN (step704ofFIG. 16). As already discussed in reference toFIG. 6, the predetermined percentage is determined as plus or minus (50% minus the X % of the total bit time for sample and hold during sampling a bit value of SDIN by the shift register406).

Referring toFIGS. 14 and 16, if the amount of the skew between SDIN and CLKIN is less than the predetermined percentage of the total bit time, an AUTO control signal is de-asserted for performing programmed skew cancellation (step706ofFIG. 16). On the other hand, if the amount of the skew is equal to or greater than the predetermined percentage of the total bit time, the AUTO control signal is asserted for performing automatic skew calibration (step708ofFIG. 16).

Referring toFIG. 14, when the AUTO control signal is de-asserted for performing programmed skew cancellation, the first mode multiplexer502selects the control signals S′<1:8> from the decoder206for determining the phase of SCLKNEWfrom the multiplexer306(step710ofFIG. 16). In addition, in that case, the second mode multiplexer504selects the output of the delay circuit213for generating the parallel data clock signal (step712ofFIG. 16). Such a mode of operation for performing programmed skew cancellation is labeled as “SS_RX” (for regular source synchronous receiver) in the inputs of the multiplexers502and504.

On the other hand, when the AUTO control signal is asserted for performing automatic skew calibration, the first mode multiplexer502selects the control signals S″<1:8> from the clock recovery PLL402for determining the phase of SCLKNEWfrom the multiplexer306(step714ofFIG. 16). Furthermore, in that case, the second mode multiplexer504selects the output of the 1/V frequency divider404for generating the parallel data clock signal (step716ofFIG. 16). Such a mode of operation for performing automatic skew calibration is labeled as “SS_CDRX” (for source synchronous CDR receiver) in the inputs of the multiplexers502and504.

In this manner, components of a CDR receiver deserializer are configured to form the source synchronous receiver deserializer500ofFIG. 14with capability to provide programmable skew cancellation and automatic skew calibration. Referring toFIG. 15, each of the source synchronous receiver deserializers604,606, and608implemented similarly as the receiver deserializer500ofFIG. 14inputs CLKIN and provides separate skew cancellation or calibration depending on the respective amount of skew between the respective SDIN and the one CLKIN by generating a separate respective SCLKNEWfor each of the high speed data channels106,108, and110. Because each of the receiver deserializers604,606, and608accounts for such respective amount of skew, the skew tolerance through each of the plurality of data channels106,108, and110is loosened for easier design of such data channels.

In contrast referring toFIG. 1, all of the prior art receiver deserializers126,128, and130share the same sampling clock signal SCLK from the receiver PLL132. Thus, the prior art source synchronous receiver114cannot eliminate the deleterious effects from variable amounts of skew between the respective SDIN and the one CLKIN for each of the multiple data channels106,108, and110.

It will be understood by those of skill in the art that the foregoing description is only exemplary of the invention and is not intended to limit its application to the structure and operation described herein. For example, the present invention may be practiced with more numerous controls signals for finer adjustment of the phase of SCLKNEW. In addition, the logical states described and illustrated herein are by way of example only, and the present invention may be practiced with other logical states as would be apparent to one of ordinary skill in the art of electronics from the description herein. Furthermore, many of the components illustrated and described herein for an example embodiment of the present invention may be alternatively implemented in hardware or software and in discrete or integrated circuits.

Additionally, the term “asserted” associated with a signal herein refers to changing the logical state of a signal from the logical low state to a logical high state, and the term “de-asserted” associated with a signal herein refers to changing the logical state of a signal from the logical high state to a logical low state. However, the term “asserted” and “de-asserted” associated with a signal may be inter-changed herein depending on the direction of change of the signal as such a direction of change of the signals may be reversed with use of inverters.

The present invention is limited only as defined in the following claims and equivalents thereof.