Insulated-gate semiconductor device

Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

This invention claims priority from Japanese Patent Application Number JP 2006-265386 filed on Sep. 28, 2006, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an insulated-gate semiconductor device, and particularly to an insulated-gate semiconductor device in which an operation region is sufficiently secured, and in which a high reverse breakdown voltage is maintained.

2. Description of the Related Art

In a conventional insulated-gate semiconductor device, a transistor cell is not disposed below a gate pad electrode. This technology is described, for instance, in Japanese Patent Application Publication No. 2002-368218 (FIG. 6 to FIG. 8).

Meanwhile, a protection diode is disposed below the gate pad electrode in some cases, and a number of pn junctions are connected to each other in series in the protection diode, for example. Moreover, a diffusion region of high-concentration impurities is sometimes formed in a substrate below the gate pad electrode in order to secure a reverse breakdown voltage between a drain and a source.

FIGS. 11A and 11Bshow one example of an n channel MOSFET as the conventional insulated-gate semiconductor device, in which a p+ type impurity region is formed below the gate pad electrode.

FIG. 11Ais a plan view of the MOSFET. Note that, interlayer insulating films on the surface of the substrate are omitted inFIG. 11A. Metal electrode layers (a source electrode47, a gate pad electrode48and a gate wiring48a) are indicated by the dashed lines.

Gate electrodes43are formed into a stripe shape on the surface of a semiconductor substrate31with gate oxide films41interposed therebetween. The gate electrodes43are formed by patterning polysilicon which has been deposited and then doped with impurities to reduce the resistance. Source regions45are formed in the surface of the substrate31along the gate electrodes43. The source regions45are formed along the gate electrodes43, and have a stripe shape.

The source electrode47is formed on an operation region51where transistor cells are disposed. The gate pad electrode48is disposed on one edge of a chip. The gate wiring48a, which is connected to the gate pad electrode48, is formed around the chip.

FIG. 11Bis a cross-sectional view taken along the line f-f inFIG. 11A.

The semiconductor substrate31is provided with a drain region by stacking an n+ type silicon semiconductor substrate31awith an n− type epitaxial layer31bor the like. Multiple p type channel regions34are formed into a stripe shape in the surface of the semiconductor substrate31. The multiple gate electrodes43are disposed in the stripe shape on the surface of the semiconductor substrate31on sides of the channel regions34while the gate insulating films41are interposed between the gate electrodes43and the semiconductor substrate31. The n+ type source regions45are formed in the surface of the channel region34which is adjacent to the gate electrodes43. The top of the gate electrode43is covered with the interlayer insulating film46, and the source electrode47is formed thereon. The source electrode47is in contact with the source regions45. The region surrounded by the gate electrodes43serves as the single transistor cell. A large number of these cells are disposed to form the operation region51.

The gate pad electrode48is formed above the n- type semiconductor layer31boutside the operation region51. The gate pad electrode48is connected to the gate electrodes43in the operation region51through a gate leading electrode43a. Moreover, a protection diode43dformed by doping impurities in polysilicon is disposed below the gate pad electrode48. The p+ type impurity region49is formed in the same pattern as that of the protection diode43d.

When the reverse voltage is applied between the source and the drain, depletion layers are spread from in pn junctions between the channel regions34and the n− type semiconductor layers31bover the operation region51, thereby securing the reverse breakdown voltage between the source and the drain. Meanwhile, the protection diode43dis formed on the one edge of the chip, and transistor cells (channel regions34) are not disposed in the substrate surface below the protection diode43d. For this reason, the p+ type impurity region49is formed in the substrate surface below the protection diode43d. For example, if the pn junction is ended at the end portion of the operation region51, the curvature of the depletion layer spreading at this region is increased, resulting in a problem that the reverse breakdown voltage between the source and the drain is deteriorated due to the electric field concentration. However, by forming the p+ type impurity region49, the spreading of the depletion layer at the end portion of the operation region51can be moderately extended to the one edge of the chip. In other words, the curvature at the end of the operation region51is decreased, allowing the electric field concentration to be mitigated. Thus, it is possible to secure a predetermined reverse breakdown voltage between the source and the drain.

The protection diode43dis made into a rectangular shape by patterning the polysilicon as shown inFIGS. 11Aand B, for example. In the protection diode43d, a number of pn junctions are formed in concentric circles as shown by the chain lines. Specifically, in the conventional art, the protection diode43dhaving a large area is patterned below the entire lower surface of the gate pad electrode48so as to overlap the gate pad electrode48. Accordingly, the p+ type impurity region49having the large area needs to be disposed from the outside of the operation region51where the transistor cells are not disposed to the one edge of the chip.

FIG. 12AandFIG. 12Bare diagrams for describing the p+ type impurity region49.FIG. 12Ashows a perspective view of the p+ type impurity region49at the circle portion inFIG. 11Aas viewed from the operation region51where the transistor cells (MOSFET) are disposed.FIG. 12Bshows a plan view of another pattern of the p+ type impurity region49, while omitting the interlayer insulating films on the surface, and indicating the metal electrode layers with the dashed lines.

The p+ type impurity region49is a diffusion region, and has the curvature of a spherical shape (FIG. 12A) at the end portion (the junction surface with the n− type epitaxial layer31b) indicated by the circle inFIG. 11A. Here, suppose a case where a higher (for example, several hundreds V) reverse breakdown voltage is needed between the drain and the source in the pattern shown inFIG. 11. In this case, even if the p+ type impurity region49is disposed, high electric field is concentrated at the end portion (indicated by the arrows inFIG. 12A) having the curvature of the spherical shape. Accordingly, it is impossible to obtain a desired reverse breakdown voltage between the drain and the source.

Moreover, in order to reduce the on-resistance of the device, the specific resistance in the n− type epitaxial layer31bneeds to be reduced, for example. In such a case, the pattern of the p+ type impurity region49shown inFIG. 11leads to decrease in the reverse breakdown voltage between the source and the drain.

In other words, when the property required for the operation region51is changed, the pattern of the p+ type impurity region49needs to be modified, besides the operation region51, in order to obtain a predetermined reverse breakdown voltage between the source and the drain.

Specifically, by decreasing the curvature of the spherical shape, it is possible to secure a sufficient reverse breakdown voltage between the drain and the source. More specifically, as shown inFIG. 12B, by decreasing the curvature at corners of the p+ type impurity region49in the plane pattern, it is possible to decrease the curvature of the spherical shape shown inFIG. 12A, and accordingly to secure a predetermined reverse breakdown voltage.

Nevertheless, when the protection diode43dis patterned below the gate pad electrode48so as to be substantially overlapped with the gate pad electrode48, the p+ type impurity region49needs to be formed so as to cover the substrate surface below the protection diode43d. Specifically, in a case where a sufficient reverse breakdown voltage between the drain and the source must be secured, the forming the p+ type impurity region49in the same pattern as that of the protection diode43dinevitably causes the curvature at the corners of the p+ type impurity region49to be small. Accordingly, in the pattern shown inFIG. 12, some of the transistor cells adjacent to the gate pad electrode48cannot be disposed. This produces a problem of making it inevitable not only to regulate (or modify the design of) the p+ type impurity region49, but also to reduce the operation region (area for disposing the transistor cells).

SUMMARY OF THE INVENTION

The invention provides an insulated-gate semiconductor device that includes a semiconductor substrate of a first general conductivity type, a plurality of gate electrodes formed on or in a surface portion of the semiconductor substrate in a form of stripes running in a first direction, a plurality of channel regions of a second general conductivity type formed in the surface portion in a form of stripes running in the first direction, a first insulating film formed between each of the gate electrodes and a corresponding channel region, a plurality of source regions of the first general conductivity type formed in the channel regions in a form of stripes running in the first direction, a gate pad electrode formed on the surface portion so that portions of the channel regions are disposed under the gate pad electrode, a plurality of pn junction diodes formed on or in the surface portion so as to be under the gate pad electrode and extend in the first direction; and a second insulating film formed on each of the gate electrodes, on the pn junction diodes and on the portions of the channel regions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Description will be given specifically of embodiments according to the present invention by exemplifying an n channel MOSFET as an insulated-gate semiconductor device with reference toFIG. 1toFIG. 10.

FIG. 1toFIG. 7show the first embodiment of the present invention.

FIG. 1AandFIG. 1Bare plan views showing a chip on the MOSFET according to the first embodiment of the present invention.FIG. 1Ais the plan view showing metal electrode layers (a source electrode, a gate pad electrode and a gate wiring) by the dashed lines, omitting interlayer insulating films.FIG. 1Bis the plan view showing a pattern of the source electrode, the gate pad electrode and the gate wiring.

MOSFETs100according to the present invention mainly include an n type semiconductor substrate1, channel regions4, first insulating films11, gate electrodes13, source regions15, body regions14, second insulating films16, a gate pad electrode18, a source electrode17, and a protection diode12d.

As shown inFIG. 1A, the gate electrodes13are formed in a stripe shape on the surface of the n type semiconductor substrate1with gate oxide films which is the first insulating films (unillustrated here) interposed therebetween. The gate electrodes13are formed by patterning polysilicon which has been deposited and then doped with impurities to reduce the resistance.

The channel regions4are p type impurity regions formed in the surface of the n type semiconductor substrate1into a stripe shape along the gate electrodes13.

The source regions15are n+ impurity regions formed in the surface of the channel regions4along the gate electrodes13. Each of the body regions14is a p+ type impurity region formed along the gate electrodes13, and between the adjacent source regions15in the surface of the channel region4, so as to stabilize the electric potential of the substrate.

It is noted that conductivity types such as p+, p and p− belong in one general conductivity type and conductivity types such as n+, n and n− belong in another general conductivity type.

The source regions15and the channel region4(body region14), which are surrounded by the gate electrodes13, form a transistor cell of the MOSFET with a stripe shape. A large number of the transistor cells are disposed to form an operation region21of the MOSFETs100. The transistor cells are disposed up to one edge of the chip. All the gate electrodes13are connected to a gate leading electrode13awhich surrounds the outer periphery of the operation region21, and which is disposed on the surface of the n type semiconductor substrate1with the gate oxide film interposed therebetween. The gate leading electrode13a is also polysilicon doped with impurities to reduce the resistance as in the case of the gate electrode13.

The gate pad electrode18is disposed along one side of the chip. Note that, althoughFIG. 1shows an example of the gate pad electrode18disposed near the center of the one side of the chip, the gate pad electrode18may be disposed at a corner of the chip. The gate pad electrode18is a metal electrode layer formed above the n+ type semiconductor substrate1with the interlayer insulating films which is the second insulating films (unillustrated here) interposed therebetween. Moreover, a gate wiring18ais formed on the n type semiconductor substrate surrounding the outer periphery of the operation region21via the interlayer insulating films, and connected to the gate pad electrode18. The gate wiring18aand the gate pad electrode18are made of the same metal electrode layer. The gate wiring18ais in contact with the gate leading electrode13a, and thereby the gate voltage is applied to the gate electrode13of each transistor cell.

The gate leading electrode13ais formed in the same ring shaped pattern as that of the gate wiring18a, and thus these shapes substantially superpose with each other. A p+ type impurity region29is formed in the surface of the n type semiconductor substrate1below the gate leading electrode13ain a ring shaped pattern as being substantially superposed with the gate leading electrode13a. The p+ type impurity region29surrounding the outer periphery of the chip is connected to the channel regions4with the stripe shape, and applied with the same source potential as the channel regions4are. As a result, the curvature of a depletion layer at the outer periphery of the chip is decreased.

The gate pad electrode18is not in contact with the channel regions4and the body regions14therebelow. Additionally, no source region15is disposed in the channel regions4below the gate pad electrode18.

Guard rings22which are diffusion region are disposed in the surface of the n type semiconductor substrate1around the gate leading electrode13aas necessary. The guard rings22are, for example, p type impurity regions to which any electric potential is applied.

The source electrode17is formed adjacent to and surrounds the gate pad electrode18as shown inFIG. 1B. The source electrode17is made of the same metal electrode layer as that of the gate pad electrode18, covers a large area of the operation region21, and thereby electrically connects to each transistor cell.

The transistor cells according to this embodiment are stripe-shaped. Accordingly, the transistor cells in an X area shown inFIG. 1Aare also applied with a predetermined electric potential by the source electrode17(seeFIG. 1B), and performs the transistor operation while the potential is fixed.

It should be noted, however, that each of the source regions15and the gate electrodes13in the transistor cells in the X region is divided on both side of the gate pad electrode18. In other words, the source regions15and the gate electrodes13are not disposed below the gate pad electrode18. Specifically, the body regions14and the source regions15are disposed in the surfaces of the channel regions4at the operation region21below the source electrode17, and thus the channel regions4are not exposed in the plan view ofFIG. 1A. On the other hand, below the gate pad electrode18, the channels4(and the body regions14) are exposed.

Accordingly, when predetermined electric potentials (a gate potential and a source potential) are applied to the gate electrodes13and the channel regions4with the stripe shapes, only the transistor cells below the source electrode17perform the transistor operation. Meanwhile, since some of the channel regions4are extended below the gate pad electrode18also, the source potential is applied thereto.

The protection diode12dwith a stripe shape is formed below the gate pad electrode18. Detailed description of the protection diode12dwill be given later.

The protection diode12dis formed in the same pattern as that of the gate electrode13. However, the protection diode12dis set apart from the gate electrodes13disposed in the extending direction of the protection diode12din predetermined distances.

FIG. 2andFIG. 3show cross-sectional views of the MOSFET according to this embodiment.FIG. 2is the cross-sectional view taken along the line a-a inFIG. 1A.FIG. 3is the cross-sectional view taken along the line b-b inFIG. 1A.

In the n type semiconductor substrate1, a drain region is formed by stacking an n+ type silicon semiconductor substrate1awith an n− type semiconductor layer1b, for example. The n-type semiconductor layer1bis, for example, an epitaxial layer. The multiple channel regions4are formed in the surface of the n− type semiconductor layer1binto the stripe shape.

The source regions15, which are n+ type impurity regions, as well as the body region14, which is a p+ type impurity region, are formed in the surface of the channel region4below the source electrode17. The gate electrode13made of the polysilicon is disposed in the stripe shape on the substrate surface between the adjacent channel regions4with the gate oxide films between the substrate and the gate electrode13. The source regions15are formed on both sides of the gate electrodes13so as to be partially superposed with the corresponding gate electrodes13. The body region14is disposed in the surface of the channel region4between the adjacent source regions15.

Specifically, the channel region4, the source regions15and the body region14are disposed in the stripe shapes on both sides of and along the gate electrodes13with the stripe shape.

The interlayer insulating film16made of a BPSG (Boron Phosphorus Silicate Glass) film or the like is formed on the top surface and side surfaces of the gate electrode13. Thus, the periphery of the gate electrode13is covered with the gate insulating film11and the interlayer insulating film16.

The source electrode17is formed by patterning the metal electrode layer into a predetermined shape on the interlayer insulating films16(seeFIG. 1B).

As shown inFIG. 2, contact holes CH are formed in the interlayer insulating films16below the source electrode17. The source electrode17is in contact with the source regions15and the body regions14(channel regions4) via the contact holes CH.

The protection diode12d, the body regions14, the channel regions4, gate oxide films11, the interlayer insulating films16and the gate leading electrode13aare disposed below the gate pad electrode18. Herein, the protection diode12dincludes the two pn junction diodes12aand12bwith stripe shape. The gate pad electrode18is in contact with the gate leading electrode13avia the contact holes CH formed in the interlayer insulating film16. Moreover, the gate pad electrode18applies the gate potential to one end of each protection diode12dvia the contact hole CH formed in the interlayer insulating film16therebelow.

As described above, no source region15is disposed in the channel regions4below the gate pad electrode18, and then no transistor cell is formed below the gate pad electrode18. Meanwhile, the body regions14and the channel regions4below the gate pad electrode18are connected to the source electrode17(FIG. 1A), and then the source potential is applied thereto.

As shown inFIG. 3, the gate electrode13, the channel region4and the source region15with the stripe shapes are formed below the source electrode17surrounding the gate pad electrode18in the X region, and thereby a transistor cell is formed.

The channel regions4and the body regions14in the X region are up to below the gate pad electrode18. In this embodiment, the region where the channel regions4are disposed inFIG. 2andFIG. 3is the operation region21.

As shown inFIG. 2andFIG. 3, the source potential is applied to the channel regions4below the gate pad electrode18as in the case of the channel regions4of the transistor cell. Moreover, the channel regions4(and also the body regions14) below the gate pad electrode18are formed in the same pattern as that of the operation region21. The channel regions4(and also the body regions14) in the operation region21are formed in a condition where the breakdown voltage required for the MOSFET is secured. Thus, the reverse breakdown voltage between the drain and the source equal to that of the operation region21is secured even in the channel regions4below the gate pad electrode18.

For this reason, the channel region4with the stripe shape makes it possible to secure the reverse breakdown voltage between the drain and the source below the gate pad electrode18. Thus, the conventional p+ type impurity region with a large area is no longer necessary.

In other words, it suffices to form the p+ type impurity region29according to this embodiment only at the outer periphery of the chip where no channel region4is disposed. It is only necessary that the p+ type impurity region29be formed in the pattern of being substantially superposed with the gate leading electrode13awith the ring shape, and thereby a width Wa of the p+ type impurity region29is greatly reduced as compared to that of the conventional impurity region.

Specifically, the width Wa of the p+ type impurity region29is larger than a width Wb of the channel region4, and for example 50 μm in a case where the breakdown voltage is approximately 600V. In the conventional art (FIG. 11) where the impurity region is formed in the entire surface below the protection diode43d, a width Wc of the p+ type impurity region49is, for example, 400 μm. Thus, the width Wa is reduced to approximately ⅛ of that of the conventional impurity region.

Conventionally, the protection diode43dwith the concentric-circular shape and the p+ type impurity region49having a large area superposed therewith are disposed below the gate pad electrode48. When the breakdown voltage required for the operation region51is changed, the pattern of the p+ type impurity region49(curvature at the corners) also needed to be modified appropriately.

In the meanwhile, according to this embodiment, by forming the channel regions4(body regions14) with the same design rule (size and impurity concentration) as that of the operation region21below the gate pad electrode18, the reverse breakdown voltage between the drain and the source equal to the breakdown voltage required for the operation region21is secured below the gate pad electrode18.

Moreover, when the breakdown voltage in the operation region21is modified, a predetermined breakdown voltage is secured below the gate pad electrode18also by modifying the setting value of the channel regions4in the operation region21. In other words, as the setting value in the operation region21is modified, a predetermined reverse breakdown voltage between the drain and the source is secured below the gate pad electrode18.

The p+ type impurity region29surrounds the outer periphery of the chip where no channel region4is disposed, and connected to the channel regions4with the stripe shape (FIG.1A). Accordingly, the p+ type impurity region29and the channel regions4have the same electric potential (the source potential). Thus, when the reverse voltage is applied between the source and the drain, the curvature of the depletion layer is decreased at the outer periphery of the chip where no channel region4is disposed, and thereby the electric field concentration is suppressed.

The guard rings22, which are the diffusion regions of the p+ type impurities, are disposed at the outer periphery of the p+ type impurity region29as necessary. No electric potential is applied to the guard rings22, and thereby the electric field concentration which occurs between the source and the drain around the p+ type impurity region29is mitigated.

Furthermore, a drain electrode20is formed on the back surface of the n type semiconductor layer1where the drain electrode20comes into contact with the n+ type semiconductor substrate1a.

Incidentally, the channel regions4with the stripe shape below the gate pad electrode18are formed by self-alignment using the polysilicon with the stripe shape as a mask. That is, in this embodiment, the polysilicon which serves as the mask below the gate pad electrode18remains. And unlike that of the operation region21, the polysilicon does not function as the gate electrode13.

For this reason, p type semiconductor regions12pandntype semiconductor regions12nare formed in the polysilicon serving as the mask for forming the channel regions4. One end of the polysilicon is connected to the gate pad electrode18, and the other end is connected to the source electrode17, and thereby the protection diode12dis formed.

Hereinafter, description will be given of the protection diode12dwith reference toFIG. 4toFIG. 7.

FIG. 4toFIG. 6are diagrams for describing the protection diode12daccording to this embodiment.FIG. 4is the schematic plan view for describing the protection diode12d.FIG. 5is the enlarged plan view ofFIG. 4.FIG. 6Ais the cross-sectional view taken along the line c-c inFIG. 5.FIG. 6Bis the equivalent circuit diagram of the protection diode12d.

Note that, inFIG. 4andFIG. 5, configurations other than that of the protection diode12dare schematically shown. InFIG. 5, the interlayer insulating films are omitted, and the source electrode17and the gate pad electrode18are indicated by the dashed lines.

As shown inFIG. 4andFIG. 5, for example, four pn junction diodes121to124are disposed below the gate pad electrode18.

Hereinafter, description will be given of the pn junction diode121. The configurations of the other pn junction diodes122to124are the same as that of the pn junction diode121.

The pn junction diode121is formed as follows. Firstly, the p type semiconductor regions12pand the n type semiconductor regions12nare alternately disposed adjacent to one another by implanting ions of p type and n type impurities, or by the deposition (PBF (Poly Boron Film) and POCl3), into the polysilicon serving as the mask for forming the channel regions4. Accordingly, pn junctions are formed. Then, on one end (for example, the n type impurity region12n) is connected to the gate pad electrode18, and the other end (for example, another n type impurity region12n) is connected to the source electrode17.

The pn junction diodes121and122are connected to each other in parallel while sharing the gate pad electrode18. Each one end of the pn junction diodes121and122, which is an end opposite to the connection portion interposed therebetween, is connected to the source electrode17. Thus, the pn junction12awith a stripe shape is formed. Specifically, the pn junction diode12ais formed as follows. Firstly, the polysilicon is patterned at the same time as the gate electrode13is patterned which is disposed in the extending direction of the pn junction diode12a. Then, the pn junction diode12ais formed by being divided from the gate electrode13in a predetermined separation distance. As a result, the pn junction diode12ahas the same width as that of the gate electrode13.

Similarly, the pn junction diode12bis formed in a stripe shape by connecting the pn junction diodes123and124to each other in parallel.

Moreover, each of the pn junction diodes12aand12bwith the stripe shapes is connected to each other in parallel by being connected both ends to the gate pad electrode18and the source electrode17, respectively. In other words, according to this embodiment, the four pn junction diodes121to124are connected in parallel, and thereby the protection diode12dbetween the gate and the source of the MOSFET is formed. Note that the gate oxide films11and the n− type semiconductor layer1bare disposed immediately below the protection diode12das shown inFIG. 2.

Further description will be given with reference toFIG. 6.

As shown inFIG. 6AandFIG. 2, the periphery of the pn junction diode121is covered with the interlayer insulating film16, and then the one end thereof (the p type semiconductor region12por the n type semiconductor region12n) is connected to the gate pad electrode18via the contact holes CH formed in the interlayer insulating film16. The other end (another p type semiconductor region12por another n type semiconductor region12n) is connected to the source electrode17.

Accordingly, as shown inFIG. 6B, the pn junction diodes121to124are connected in parallel, and thereby the single protection diode12dis formed. The protection diode12dis connected between a source terminal S and a gate terminal G of the MOSFET having the source terminal S, the gate terminal G and a drain terminal D.

Note that the number of series connections of the pn junctions in the pn junction diodes121to124, the number of the pn junction diodes12aand12bwith the stripe shapes, as well as the contact positions with the gate pad electrode18and the source electrode17have been exemplified, and these settings are appropriately selected in accordance with the breakdown voltage.

For example, by shifting the positions of the contact holes CH for the gate pad electrode18in the protection diode12dshown inFIG. 5, the breakdown voltage is easily modified. In such a case, the pn junction diodes121to124need to have the same configurations (the same number of pn junctions). Thus, for one line of the stripe-shaped pn junction diode12a, the two contact holes CH are formed below the gate pad electrode18.

FIG. 7shows the conventional protection diode43dshown inFIG. 11. Generally, in the protection diode43d, the pn junctions are connected in series in the concentric circles.

The pn junction diode121according to this embodiment corresponds to the portion indicated by the dashed line and the hatching inFIG. 7. In the protection diode43dforming the pn junctions in the concentric circles, the area within the innermost periphery of the pn junction is the smallest. By this area, the current capacity of the reverse current is determined, that is, the breakdown voltage of the protection diode43dis determined. Additionally, by series-connecting the multiple pn junctions having a predetermined breakdown voltage in the concentric circles, the breakdown voltage which is sufficient to protect the MOSFET between the gate and the source is secured.

According to this embodiment, the pn junction diodes121to124having the same configurations are connected in parallel. In other words, if a pn junction area S2in the pn junction diode121is the same as a pn junction area S1within the innermost periphery of the protection diode43din the concentric circles inFIG. 7, the protection diode12dobtains the same breakdown voltage as that of the protection diode43dwith the concentric-circular shape.

The pn junction diodes12aand12bwith the stripe shapes are formed in the same pattern as that of the gate electrode13. In other words, for example, the ten pn junction diodes12aand12bwith the stripe shapes can actually be disposed below the gate pad electrode18. Accordingly, by connecting these diodes in parallel, the pn junction area S2having the same breakdown voltage as the pn junction area S1within the innermost periphery of the protection diode with the concentric-circular shape is sufficiently secured.

Furthermore, by series-connecting the same number of the pn junctions in the pn junction diode121as that of the series connections of the pn junctions in the protection diode43dwith the concentric-circular shape, the same breakdown voltage as that of the protection diode43with the concentric-circular shape is obtained.

Suppose a case where lengths Lp and Ln of the corresponding p type semiconductor region12pandntype semiconductor region12naccording to this embodiment are respectively the same as lengths Lp′ and Ln′ in the protection diode43dwith the concentric-circular shape. In this case, when the numbers of the series connections of the pn junctions are the same between the pn junction diode121and the protection diode43d, the diameter of the protection diode43dwith the concentric-circular shape is the same as the length of the single pn junction diode12awith the stripe shape.

Accordingly, the area occupied by the protection diode12daccording to this embodiment is made smaller than that of the protection diode43dwith the concentric-circular shape.

As described above, according to this embodiment, the breakdown voltage of the protection diode12dis determined by the number of the series connections of the pn junctions in the pn junction diode121(positions of the contact holes CH for the source electrode17and the gate pad electrode18).

Still furthermore, the current capacity of the protection diode12dis determined by the number of the parallel connections (four in this embodiment) in the pn junction diode121.

For this reason, the number of the series connections of the pn junctions (position of the contact hole CH for each electrode) and the number of the parallel connections are appropriately selected in accordance with the property of the protection diode12d.

FIG. 8toFIG. 10shows the second embodiment according to the present invention.FIG. 8is a partially enlarged view for describing transistor cells. The transistor cell according to the second embodiment has a trench structure, and the other configurations are the same as those inFIG. 1. For this reason, a chip of a MOSFETs100is referred to the plan view ofFIG. 1, and description for the same constituents is omitted.

FIG. 8is a plan view of metal electrode layers indicated by the dashed lines, and in which interlayer insulating films are omitted.FIG. 9is a cross-sectional view taken along the line d-d inFIG. 8.FIG. 10is a cross-sectional view taken along the line e-e inFIG. 8.

The first embodiment is so-called the MOSFET in which the gate electrodes are in the planar structure with the vertical current paths. Meanwhile, the second embodiment is the MOSFET in a trench structure.

As shown inFIG. 8, trenches7are formed in a stripe shape in a plane pattern of an n type semiconductor substrate1. In the plane pattern, gate electrodes13, channel regions4, source regions15and body regions14are all formed in stripe shapes along the trenches7.

In this case also, the transistor cells are stripe-shaped. The channel regions4and body regions14which are connected to the transistor cells are formed below a gate pad electrode18. The patterns of a source electrode17and a gate wiring18aare the same as those according to the first embodiment.

As shown inFIG. 9, the trenches7penetrate through the channel regions4, and have the depth reaching an n− type semiconductor layer1b. In this case, the channel regions4are continuously formed in the surface of the n type semiconductor substrate1. The inner wall of the trench7is covered with a gate oxide film11, and the trench7is filled with a polysilicon filling.

Below the source electrode17, the resistance in the polysilicon in the trench7is to be reduced, and then the gate electrode13is formed. The n+ type source regions15are formed in the surface of the channel region4which is adjacent to the trenches7. The p+ type body region14is formed between the adjacent source regions15in the surface of the channel region4.

The interlayer insulating films16are formed, covering the gate electrodes13. The source electrode17is in contact with the source regions15and the body regions14(the channel region4) via contact holes CH formed in the interlayer insulating films16.

The trenches7, the polysilicon, the body regions14and the channel regions4are disposed in the n type semiconductor substrate1below the gate pad electrode18, but the gate pad electrode18is never in contact with the channel regions4.

The gate pad electrode18is in contact with a gate leading electrode13aabove a p+ type impurity region29via the contact holes CH formed in the interlayer insulating films16.

The transistor cells in an X region is in contact with the source electrode17which surrounds the gate pad electrode18, and which is adjacent thereto. Accordingly, the electric potential of these electrodes are fixed, and thereby the transistor operation is performed.

Moreover, the channel regions4below the gate pad electrode18are fixed to the source potential. The reverse breakdown voltage between the drain and the source equal to that of an operation region21is secured.

Pn junction diodes12aand12bwith stripe shapes, with which polysilicon are buried in the trenches, are disposed below the gate pad electrode18. One of each pn junction diodes12aand12bis connected to the gate pad electrode18, and the other end is connected to the source region17, and thereby a protection diode12dbetween the gate and the source is formed.

According to the second embodiment, the insulating film11is formed in the trench7. However, the description thereof is omitted, since the schematic plan view showing the connection between the protection diode12dand each electrode is the same asFIG. 4andFIG. 5.

The polysilicon are buried in the trenches7with the stripe shape in the flat pattern. In the X region, the polysilicon and the gate electrodes13formed in the extending direction of the polysilicon are insulated by dividing the trenches7.

As in the plane patterns inFIG. 4andFIG. 5, n type semiconductor regions12nandptype semiconductor regions12pare alternately disposed adjacent to one another in the polysilicon in the trench7. Then, the implantation and/or the deposition of impurities are performed so as to form pn junctions.

Accordingly, four pn junction diodes121to124which are connected to the source electrode17and the gate pad electrode18at both ends, are connected to one another in parallel, and thereby the single protection diode12dis formed. The protection diode12dis connected between the source and the gate of the MOSFET.

According to the second embodiment, the gate electrode13has the trench structure. Thus, the number of the transistor cells disposed in the operation region21is increased as compared to the first embodiment, resulting in the increase of the cell density.

Additionally, the embodiments according to the present invention have been described by use of the n channel MOSFET. However, the same effect is obtained in a p channel MOSFET in which the conductivity type is made opposite to those embodiments, or an IGBT (Insulated Gate Bipolar Transistor) in which a p type (n type) substrate is disposed below an n+ (p+) type semiconductor substrate of a MOSFET, as well.

According to the present invention, provided is the MOSFET in which a high reverse breakdown voltage between the drain and the source is secured without reducing the area of the operation region. Specifically, the transistor cells are formed in the stripe shape. Some of the channel regions are disposed below the gate pad electrode, and thereby the source potential is applied to the channel regions. The channel regions below the gate pad electrode are formed in the same pattern as that of the operation region of the MOSFET. Thus, the reverse breakdown voltage between the drain and the source equal to that of the operation region is secured even below the gate pad electrode.

For this reason, even when the reverse breakdown voltage between the drain and the source is modified, a predetermined breakdown voltage is secured without modifying the pattern (curvature at the corner) of the p+ type impurity region which was necessity conventionally. For example, when higher breakdown voltage is secured, conventionally there has been a problem that the operation region (the number of the areas for disposing the transistor cells) has to be reduced in accordance with the modification of the pattern of the p+ type impurity region. In contrast, according to the present embodiments, the reverse breakdown voltage between the drain and the source is secured in the channel regions below the gate pad electrode, instead of the conventional p+ type impurity region having a large area. In addition, the area for the operation region is secured as that of the conventional operation region.

Moreover, the pn junction diode with the stripe shape is formed below the gate pad electrode. The gate potential is applied to the one end of the pn junction diode, and the source potential is applied to the other end of the pn junction diode. According to the present embodiments, the polysilicon is disposed in the stripe shape below the gate pad electrode. Utilizing this structure, the protection diode is disposed below the gate pad electrode.

Furthermore, the breakdown voltage of the protection diode can be arbitrarily set by appropriately selecting the positions of the contact holes for the gate pad electrode, the source electrode, and the pn junction diodes with the stripe shape.