Semiconductor device

A semiconductor device includes first and second electrode, a semiconductor part therebetween, and first and second control electrode. The first control electrode is provided in a first trench between the first electrode and the semiconductor part. The second control electrode is provided in a second trench between the second electrode and the semiconductor part. The semiconductor part includes first, third, fifth and sixth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The sixth layer is provided between the first layer and the second electrode. The second electrode is electrically connected to the first layer via a first-conductivity-region including the sixth layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-017859, filed on Feb. 5, 2020; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments relate to a semiconductor device.

BACKGROUND

It is desirable to reduce the switching loss of a power control semiconductor device.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode; a second electrode facing the first electrode; a semiconductor part provided between the first electrode and the second electrode; a first control electrode disposed between the first electrode and the semiconductor part inside a first trench provided in the semiconductor part, the first control electrode being electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the first electrode by a second insulating film; and a second control electrode disposed between the second electrode and the semiconductor part inside a second trench provided in the semiconductor part, the second control electrode being electrically insulated from the semiconductor part by a third insulating film and electrically insulated from the second electrode by a fourth insulating film. The semiconductor part includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, and a sixth semiconductor layer of the first conductivity type. The first semiconductor layer extending between the first electrode and the second electrode. The first and second trenches extend in the first semiconductor layer. The second semiconductor layer is provided between the first semiconductor layer and the first electrode, the second semiconductor layer facing the first control electrode via the first insulating film and being electrically connected to the first electrode. The third semiconductor layer is selectively provided between the second semiconductor layer and the first electrode, the third semiconductor layer contacting the first insulating film and being electrically connected to the first electrode. The fourth semiconductor layer is provided between the first semiconductor layer and the second electrode, the fourth semiconductor layer facing the second control electrode via the third insulating film and being electrically connected to the second electrode. The fifth semiconductor layer is selectively provided between the fourth semiconductor layer and the second electrode, the fifth semiconductor layer contacting the third insulating film and being electrically connected to the second electrode. The sixth semiconductor layer is selectively provided between the first semiconductor layer and the second electrode, the second electrode being connected to the first semiconductor layer via a first-conductivity-type region including the sixth semiconductor layer.

Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic and conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

The arrangements and the configurations of the portions are described using an X-axis, a Y-axis, and a Z-axis shown in each drawing. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other and respectively refer to an X-direction, a Y-direction, and a Z-direction. There are cases where the Z-direction is described as upward, and the reverse direction is described as downward.

First Embodiment

FIG. 1is a schematic cross section showing a semiconductor device1according to a first embodiment. The semiconductor device1is a so-called reverse-conducting IGBT

The semiconductor device1includes a semiconductor part10, a first electrode20, a second electrode30, a first control electrode40, and a second control electrode50.

The first electrode20and the second electrode30face each other, and the semiconductor part10is provided between the first electrode20and the second electrode30. The first electrode20is, for example, an emitter electrode, and the second electrode30is, for example, a collector electrode.

The semiconductor part10is, for example, silicon. The first electrode20and the second electrode30are, for example, metal layers including aluminum (Al).

The first control electrode40is provided between the semiconductor part10and the first electrode20. The first control electrode40is disposed inside a first trench GT1provided in the semiconductor part10. The first control electrode40is electrically insulated from the semiconductor part10by a first insulating film43. Also, the first control electrode40is electrically insulated from the first electrode20by a second insulating film45.

The second control electrode50is provided between the semiconductor part10and the second electrode30. The second control electrode50is disposed inside a second trench GT2provided in the semiconductor part10. The second control electrode50is electrically insulated from the semiconductor part10by a third insulating film53. Also, the second control electrode50is electrically insulated from the second electrode30by a fourth insulating film55.

The first control electrode40is, for example, a gate electrode at the emitter side. The second control electrode50is a gate electrode at the collector side. The first control electrode40and the second control electrode are, for example, conductive polysilicon.

The semiconductor part10includes a first semiconductor layer11of a first conductivity type, a second semiconductor layer13of a second conductivity type, a third semiconductor layer15of the first conductivity type, a fourth semiconductor layer21of the second conductivity type, a fifth semiconductor layer23of the first conductivity type, a sixth semiconductor layer25of the first conductivity type, and a seventh semiconductor layer27of the first conductivity type. Hereinbelow, the first conductivity type is described as an n-type, and the second conductivity type is described as a p-type.

The first semiconductor layer11extends between the first electrode20and the second electrode30, and the first trench GT1and the second trench GT2extend in the first semiconductor layer11. The first semiconductor layer11is, for example, an n-type base layer.

The second semiconductor layer13is provided between the first semiconductor layer11and the first electrode20and faces the first control electrode40via the first insulating film43. The second semiconductor layer13is electrically connected to the first electrode20. The second semiconductor layer13is, for example, a p-type base layer.

The third semiconductor layer15is selectively provided between the second semiconductor layer13and the first electrode20. The third semiconductor layer15contacts the first insulating film43and is electrically connected to the first electrode20. The third semiconductor layer15is, for example, an n-type emitter layer.

The fourth semiconductor layer21is provided between the first semiconductor layer11and the second electrode30and faces the second control electrode50via the third insulating film53. The fourth semiconductor layer21is electrically connected to the second electrode. The fourth semiconductor layer21is, for example, a p-type collector layer.

The fifth semiconductor layer23is selectively provided between the fourth semiconductor layer21and the second electrode30. The fifth semiconductor layer23contacts the third insulating film53and is electrically connected to the second electrode30. The fifth semiconductor layer23is, for example, an n-type collector layer.

The sixth semiconductor layer25is selectively provided between the first semiconductor layer11and the second electrode30. The second electrode30is connected to the first semiconductor layer11via a first-conductivity-type region NR including the sixth semiconductor layer25. The sixth semiconductor layer25is, for example, an n-type cathode layer.

The seventh semiconductor layer27is provided between the first semiconductor layer11and the fourth semiconductor layer21. The seventh semiconductor layer27includes a first-conductivity-type impurity with a higher concentration than the first-conductivity-type impurity of the first semiconductor layer11. The seventh semiconductor layer is, for example, an n-type buffer layer. The fifth semiconductor layer23includes a first-conductivity-type impurity with a higher concentration than the first-conductivity-type impurity of the seventh semiconductor layer27.

The seventh semiconductor layer27is provided also between the first semiconductor layer11and the sixth semiconductor layer25. The sixth semiconductor layer25includes a first-conductivity-type impurity with a higher concentration than the first-conductivity-type impurity of the seventh semiconductor layer27and is electrically connected to the second electrode30. In the example, the first-conductivity-type region NR includes the sixth semiconductor layer25and the seventh semiconductor layer27.

As shown inFIG. 1, multiple first control electrodes40are provided between the semiconductor part10and the first electrode20. Also, multiple second control electrodes50are provided between the semiconductor part10and the second electrode30.

The sixth semiconductor layer25is provided between two adjacent second control electrodes50of the multiple second control electrodes50. The sixth semiconductor layer25faces the two adjacent second control electrodes50via the third insulating film53.

For example, a distance WG1between the adjacent first control electrodes40may be the same as or different from a distance WG2between the adjacent second control electrodes50. A distance WG3between the second control electrodes50where the sixth semiconductor layer25is provided may be different from the distance WG2between the other adjacent second control electrodes50.

FIG. 2is a time chart showing a method for controlling the semiconductor device1according to the first embodiment. For example, a power converter (not illustrated) such as an inverter or the like is configured using multiple semiconductor devices1.FIG. 2shows the method for controlling a control voltages VGEand VBGCwhen the semiconductor device1is operated in the diode mode in such a power converter.

When operating in the diode mode, the potential of the first electrode20is controlled to be greater than the potential of the second electrode30. The potentials of the first and second electrodes20and30are reversed at a time tOFFat which the semiconductor device1is caused to transition from the diode mode to the IGBT mode.

The control voltage VGEis applied between the first electrode20and the first control electrode40. For example, the control voltage VGEis a positive voltage when the potential of the first control electrode40is greater than the potential of the first electrode20.

The control voltage VBGCis applied between the second electrode30and the second control electrode50. For example, the control voltage VBGCis a positive voltage when the potential of the second control electrode50is greater than the potential of the second electrode30.

As shown inFIG. 2, the control voltage VGEis maintained at negative 15 V from a start timing (not illustrated) of the diode mode until a time t1. The control voltage VGEis increased to positive 15 V at the time t1, is maintained at positive 15 V until a time t2, and subsequently is reduced to negative 15 V at the time t2. The period between the time t2and the time tOFFis a so-called dead time set to avoid a short-circuit of the power conversion circuit.

On the other hand, the control voltage VBGCis maintained at positive 15 V from the start timing (not illustrated) of the diode mode until the time t1. The control voltage VBGCis reduced to negative 15 V at the time t1, is maintained at negative 15 V until the time t2, and subsequently is increased to positive 15 V at the time t2.

FIGS. 3A and 3Bare schematic cross-sectional views showing the method for controlling the semiconductor device1according to the first embodiment.FIGS. 3A and 3Bshow the flow of the charge in the semiconductor device1corresponding to the control process of the control voltages VGEand VBGCshown inFIG. 2.

FIG. 3Ashows the flow of the charge in the period from the start of the diode mode to the time t1. The p-n junction between the first semiconductor layer11and the second semiconductor layer13is forward-biased, and holes are injected from the second semiconductor layer13into the first semiconductor layer11. On the other hand, the p-n junction between the fourth semiconductor layer21and the seventh semiconductor layer27is reverse biased; therefore, electrons are injected from the electrode30into the first semiconductor layer11via the first-conductivity-type region NR, i.e., the sixth semiconductor layer25and the seventh semiconductor layer27.

A first-conductivity-type inversion layer NIV1is induced at the interface between the fourth semiconductor layer21and the third insulating film53by the control voltage VBGC, e.g., positive 15 V applied to the second control electrode50. Therefore, electrons are injected from the electrode30into the first semiconductor layer11via the fifth semiconductor layer23, the first-conductivity-type inversion layer NIV1, and the seventh semiconductor layer27. Thereby, in the period from the start timing of the diode mode to the time t1, the densities of the electrons and holes in the first semiconductor layer11can be increased, and the on-resistance can be reduced.

FIG. 3Bshows the flow of the charge in the period from the time t1to the time t2. In the period from the time t1to the time t2, the control voltage VBGC, e.g., negative 15 V is applied to the second control electrode50; and the first-conductivity-type inversion layer NIV1in the fourth semiconductor layer21disappears. Therefore, the electron injection into the first semiconductor layer11via the inversion layer NIV is stopped, and the electron injection from the second electrode30into the first semiconductor layer11occurs only along the path via the sixth semiconductor layer25and the seventh semiconductor layer27. As a result, the electron injection from the second electrode30into the first semiconductor layer11is reduced, and the hole injection from the second semiconductor layer13into the first semiconductor layer11is reduced.

Also, the control voltage VGE, e.g., positive 15 V is applied to the first control electrode40, and a first-conductivity-type inversion layer NIV2is induced at the interface between the second semiconductor layer13and the first insulating film43. The electrons in the first semiconductor layer11are ejected to the first electrode20via the first-conductivity-type inversion layer NIV2and the third semiconductor layer15.

The fourth semiconductor layer21includes, for example, a second-conductivity-type impurity with substantially the same concentration as the second-conductivity-type impurity of the second semiconductor layer13. The threshold voltage of the first control electrode40is substantially equal to the threshold voltage of the second control electrode50, and the first-conductivity-type inversion layers NIV2and NIV1are induced respectively by the control voltages VGEand VBGCof positive 15 V.

By performing such a control of the first and second control electrodes40and50in the semiconductor device1, the densities of the electrons and holes in the first semiconductor layer11in the period t1to t2directly before the transition from the diode mode to the IGBT mode can be reduced. Thereby, the ejection time of the electrons and holes in the first semiconductor layer11in the recovery period from the diode mode, i.e., the time necessary to deplete the first semiconductor layer11, can be reduced, and the recovery loss can be reduced.

FIG. 4is a schematic cross section showing a semiconductor device2according to a modification of the first embodiment.

In the semiconductor device2, the seventh semiconductor layer27is not provided between the first semiconductor layer11and the sixth semiconductor layer25.

The seventh semiconductor layer27is provided to prevent the depletion region induced in the first semiconductor layer11from reaching the fourth semiconductor layer21of the second conductivity type. Therefore, the seventh semiconductor layer27may not be disposed in the first-conductivity-type region NR in which the sixth semiconductor layer25of the first conductivity type is provided.

In the semiconductor device2as well, the recovery loss in the diode operation can be reduced by the control voltages VGEand VBGCshown inFIG. 2.

FIGS. 5A and 5Bare schematic views showing a semiconductor device3according to another modification of the first embodiment.FIG. 5Ais a cross-sectional view of the semiconductor device3.FIG. 5Bis a time chart showing a method for controlling the semiconductor device3.

In the semiconductor part10of the semiconductor device3as shown inFIG. 5A, the fourth semiconductor layer21faces a second control electrode50avia the third insulating film53. The sixth semiconductor layer25faces a second control electrode50bvia another third insulating film53.

The fourth semiconductor layer21and the sixth semiconductor layer25are provided between the adjacent second control electrodes50aand50b. The sixth semiconductor layer25is positioned between the fourth semiconductor layer21and the second control electrode50b.

The semiconductor part10further includes an eighth semiconductor layer29of the first conductivity type provided between the sixth semiconductor layer25and the second electrode30. The eighth semiconductor layer29contacts another third insulating film53and is electrically connected to the second electrode30. The eighth semiconductor layer29includes a first-conductivity-type impurity with a higher concentration than the first-conductivity-type impurity of the sixth semiconductor layer25. The first-conductivity-type region NR includes the sixth semiconductor layer25, the seventh semiconductor layer27, and the eighth semiconductor layer29.

As shown inFIG. 5B, the control voltage VGEis maintained at negative 15 V from the start timing (not illustrated) of the diode mode until the time t1. The control voltage VGEis increased to positive 15 V at the time t1, is maintained at positive 15 V until the time t2, and subsequently is reduced to negative 15 V at the time t2.

On the other hand, the control voltage VBGCis maintained at positive 15 V from the start timing (not illustrated) of the diode mode until the time t1. For example, the control voltage VBGCis reduced to 0 V at the time t1, is maintained at 0 V until the time t2, and subsequently is increased to positive 15 V at the time t2.

FIGS. 6A and 6Bare schematic views showing the method for controlling the semiconductor device3according to the other modification of the first embodiment.FIGS. 6Aand6B show the flow of the charge in the semiconductor device3corresponding to the control processes due to the control voltages VGEand VBGCshown inFIG. 5B.

FIG. 6Ashows the flow of the charge in the period from the start of the diode mode to the time t1. The p-n junction between the first semiconductor layer11and the second semiconductor layer13is forward-biased, and holes are injected from the second semiconductor layer13into the first semiconductor layer11. The first-conductivity-type inversion layer NIV1is induced at the interface between the fourth semiconductor layer21and the third insulating film53by the control voltage VBGC, e.g., positive 15 V applied to the second control electrode50. A first-conductivity-type charge accumulation layer NAC is induced at the interface between the sixth semiconductor layer25and the third insulating film53. Therefore, electrons are injected into the first semiconductor layer11from the electrode30through a path via the fifth semiconductor layer23, the first-conductivity-type inversion layer NIV1, and the seventh semiconductor layer27and a path via the eighth semiconductor layer29, the first-conductivity-type charge accumulation layer NAC, and the seventh semiconductor layer27. As a result, in the period from the start of the diode mode to the time t1, the densities of the electrons and holes in the first semiconductor layer11can be increased, and the on-resistance can be reduced.

FIG. 6Bshows the flow of the charge in the period from the time t1to the time t2. In the period from the time t1to the time t2, the control voltage VBGCapplied between the second control electrode50and the electrode30is, for example, 0 V. Therefore, the first-conductivity-type inversion layer NIV1that is induced between the fourth semiconductor layer21and the third insulating film53disappears. As a result, the electron injection from the second electrode30into the first semiconductor layer11occurs only through the path via the eighth semiconductor layer29, the sixth semiconductor layer25, and the seventh semiconductor layer27; and the electron injection from the second electrode30into the first semiconductor layer11is reduced. Accordingly, the hole injection from the second semiconductor layer13into the first semiconductor layer11also is reduced.

On the other hand, the control voltage VGE, e.g., positive 15 V is applied to the first control electrode40; and the first-conductivity-type inversion layer NIV2is induced at the interface between the second semiconductor layer13and the first insulating film43. The electrons in the first semiconductor layer11are ejected to the first electrode20via the first-conductivity-type inversion layer NIV2and the third semiconductor layer15.

In the semiconductor device3, the densities of the electrons and holes in the first semiconductor layer11in the period t1to t2directly before the transition from the diode mode to the IGBT mode can be reduced by the control voltages VGEand VBGCshown inFIG. 5B. Thereby, the ejection time of the electrons and holes of the first semiconductor layer11in the recovery period from the diode mode can be reduced, and the recovery loss can be reduced.

FIG. 7is a schematic cross-sectional view showing another method for controlling the semiconductor device3according to the other modification of the first embodiment.FIG. 7shows the flow of the charge when the semiconductor device3is operated in the IGBT mode.

In the IGBT mode, the potential of the second electrode30is maintained to be greater than the potential of the first electrode20. Also, the control voltage VBGC, e.g., negative 15 V is applied between the second electrode30and the second control electrode50. Therefore, a second-conductivity-type charge accumulation layer PIV is induced between the sixth semiconductor layer25and the second control electrode50.

An on/off-control of the collector current flowing from the second electrode30toward the first electrode20is performed by applying the control voltage VGE, e.g., positive 15 V or negative 15 V between the first electrode20and the first control electrode40.

As shown inFIG. 7, the first-conductivity-type inversion layer NIV2is induced between the second semiconductor layer13and the first control electrode40. Therefore, electrons are injected from the first electrode20into the first semiconductor layer11via the third semiconductor layer15and the first-conductivity-type inversion layer NIV2.

Accordingly, holes are injected from the fourth semiconductor layer21into the first semiconductor layer11via the seventh semiconductor layer27. Also, the ejection of electrons from the first semiconductor layer11to the second electrode30is suppressed by the second-conductivity-type charge accumulation layer PIV induced between the sixth semiconductor layer25and the second control electrode50. Thereby, the densities of the electrons and holes in the first semiconductor layer11are increased, and the on-resistance is reduced. It is favorable for the entire sixth semiconductor layer25to be inverted to the second conductivity type to cause this effect to be more pronounced when a negative control voltage VBGCis applied between the second electrode30and the second control electrode50.

Second Embodiment

FIGS. 8A and 8Bare schematic views showing a semiconductor device4according to a second embodiment.FIG. 8Ais a cross-sectional view of the semiconductor device4.FIG. 8Bis a time chart showing a method for controlling the semiconductor device4.

As shown inFIG. 8A, the semiconductor part10of the semiconductor device4includes a ninth semiconductor layer33of the second conductivity type selectively provided between the first semiconductor layer11and the second electrode30. In other words, the semiconductor device4includes a portion where the fourth semiconductor layer21is provided between the adjacent second control electrodes50, and another portion where the ninth semiconductor layer33is provided between the adjacent second control electrodes50. The semiconductor part10further includes the fifth semiconductor layer23provided between the ninth semiconductor layer33and the second electrode30.

The ninth semiconductor layer33faces at least one of the mutually-adjacent second control electrodes50via the third insulating film53. In the example, the ninth semiconductor layer33faces both of the mutually-adjacent second control electrodes50via the third insulating film53. The ninth semiconductor layer33includes a second-conductivity-type impurity with a lower concentration than the second-conductivity-type impurity of the fourth semiconductor layer21.

As shown inFIG. 8B, the control voltage VGEis maintained at negative 15 V from the start timing (not illustrated) of the diode mode until the time t1. The control voltage VGEis increased to positive 15 V at the time t1, is maintained at positive 15 V until the time t2, and subsequently is reduced to negative 15 V at the time t2.

On the other hand, the control voltage VBGCis maintained at positive 15 V from the start timing (not illustrated) of the diode mode until the time t1. For example, the control voltage VBGCis reduced to positive 5 V at the time t1, is maintained at positive 5 V until the time t2, and subsequently is increased to positive 15 V at the time t2.

FIGS. 9A and 9Bare schematic views showing the method for controlling the semiconductor device4according to the other modification of the first embodiment.FIGS. 9A and 9Bshow the flow of the charge in the semiconductor device4corresponding to the control processes due to the control voltages VGEand VBGCshown inFIG. 8B.

FIG. 9Ashows the flow of the charge in the period from the start of the diode mode to the time t1. The p-n junction between the first semiconductor layer11and the second semiconductor layer13is forward-biased, and holes are injected from the second semiconductor layer13into the first semiconductor layer11. The first-conductivity-type inversion layer NIV1is induced at the interface between the fourth semiconductor layer21and the third insulating film53by the control voltage VBGCof positive 15 V applied to the second control electrode50. Also, a first-conductivity-type inversion layer NIV3is induced at the interface between the ninth semiconductor layer33and the third insulating film53.

Electrons are injected from the electrode30into the first semiconductor layer11through a path via the fifth semiconductor layer23, the first-conductivity-type inversion layer NIV1, and the seventh semiconductor layer27and a path via the fifth semiconductor layer23, the first-conductivity-type inversion layer NIV3, and the seventh semiconductor layer27. As a result, the densities of the electrons and holes in the first semiconductor layer11in the period from the start of the diode mode to the time t1can be increased, and the on-resistance can be reduced.

FIG. 9Bshows the flow of the charge in the period from the time t1to the time t2. The control voltage VBGCthat is applied between the second control electrode50and the electrode30is positive 5 V in the period from the time t1to the time t2. In the example, the threshold voltage for inducing the first-conductivity-type inversion layer NIV2at the interface between the fourth semiconductor layer21and the third insulating film53is greater than positive 5 V. On the other hand, the threshold voltage for inducing the first-conductivity-type inversion layer NIV3at the interface between the ninth semiconductor layer33and the other third insulating film53is less than positive 5 V.

Therefore, by lowering the control voltage VBGCbetween the second electrode30and the second control electrode50to positive 5 V, the first-conductivity-type inversion layer NIV1disappears, and the first-conductivity-type inversion layer NIV3is maintained. As a result, the electron injection from the second electrode30into the first semiconductor layer11occurs only through the path via the first-conductivity-type inversion layer NIV3, and the electron injection from the second electrode into the first semiconductor layer11is reduced. Accordingly, the holes that are injected from the second semiconductor layer13into the first semiconductor layer11also are reduced.

The control voltage VGEof positive 15 V is applied to the first control electrode40; and the first-conductivity-type inversion layer NIV2is induced at the interface between the second semiconductor layer13and the first insulating film43. Therefore, the electrons in the first semiconductor layer11are ejected to the first electrode20via the first-conductivity-type inversion layer NIV2and the third semiconductor layer15.

In the semiconductor device4, the densities of the electrons and holes in the first semiconductor layer11in the period t1to t2directly before the transition from the diode mode to the IGBT mode can be reduced by the control of the carriers by the control voltages VGEand VBGCshown inFIG. 8B. Thereby, the ejection time of the electrons and holes of the first semiconductor layer11in the recovery period from the diode mode can be reduced, and the recovery loss can be reduced.

FIGS. 10A and 10Bare schematic cross-sectional views showing semiconductor devices5and6according to modifications of the second embodiment.

In the semiconductor part10of the semiconductor device5shown inFIG. 10A, the fourth semiconductor layer21faces the second control electrode50avia the third insulating film53. The ninth semiconductor layer33faces the second control electrode50bvia another third insulating film53.

The fourth semiconductor layer21and the ninth semiconductor layer33are provided between the adjacent second control electrodes50aand50b. The ninth semiconductor layer33is positioned between the fourth semiconductor layer21and the second control electrode50b.

In the example as well, the densities of the electrons and holes in the first semiconductor layer11in the period t1to t2directly before the transition from the diode mode to the IGBT mode can be reduced by performing the carrier control by the control voltages VGEand VBGCshown inFIG. 8B; and the recovery loss in the recovery period from the diode mode can be reduced.

In the semiconductor device6shown inFIG. 10B, the semiconductor part10further includes a tenth semiconductor layer35of the first conductivity type provided between the first semiconductor layer11and the second semiconductor layer13. The tenth semiconductor layer35includes a first-conductivity-type impurity with a higher concentration than the first impurity of the first semiconductor layer11. Also, the tenth semiconductor layer35includes the first-conductivity-type impurity with a lower concentration than the first-conductivity-type impurity of the third semiconductor layer15. The tenth semiconductor layer35is, for example, an n-type barrier layer.

By providing the tenth semiconductor layer35in the example, the potential barrier to the holes moving from the first semiconductor layer11toward the second semiconductor layer13can be increased. Thereby, the movement of the holes from the first semiconductor layer11toward the second semiconductor layer13can be suppressed, and the densities of the electrons and holes in the first semiconductor layer11can be increased. In other words, the tenth semiconductor layer35is effective for reducing the on-resistance by increasing the densities of the electrons and holes in the first semiconductor layer11in both the diode mode and the IGBT mode. The tenth semiconductor layer35is not limited to the example; for example, the tenth semiconductor layer35also is applicable to the semiconductor devices1to5.