Integrated circuit device

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0166965, filed on Dec. 2, 2020 in the Korean Intellectual Property Office, and entitled: “Integrated Circuit Device,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to an integrated circuit device.

2. Description of the Related Art

As the size of an integrated circuit device decreases, the integration density of field-effect transistors on a substrate may be increased. A horizontal nanosheet field-effect transistor (hNSFET) including a plurality of horizontal nanosheets stacked on one layout region has been considered.

SUMMARY

The embodiments may be realized by providing an integrated circuit device including a substrate including a first device region and a second device region; a first fin active region extending in a first horizontal direction on the first device region; a second fin active region extending in the first horizontal direction on the second device region; an isolation film covering opposite side walls of each of the first fin active region and the second fin active region; a plurality of gate cut insulating patterns on the isolation film on the first device region and the second device region; a gate line extending on the first fin active region and the second fin active region in a second horizontal direction that crosses the first horizontal direction, the gate line having a length in the second horizontal direction limited by the plurality of gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the first fin active region and the second fin active region and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom surface to the top surface.

The embodiments may be realized by providing an integrated circuit device including a substrate including a first device region and a second device region separated from the first device region; a first fin active region extending in a first horizontal direction on the first device region; a second fin active region extending in the first horizontal direction on the second device region; an isolation film covering opposite side walls of each of the first fin active region and the second fin active region; a gate line extending on the first device region and the second device region in a second horizontal direction that crosses the first horizontal direction; a first nanosheet stack facing a first fin top of the first fin active region at a position separated from the first fin top in a vertical direction, the first nanosheet stack including at least one first nanosheet surrounded by the gate line; a second nanosheet stack facing a second fin top of the second fin active region at a position separated from the second fin top in the vertical direction, the second nanosheet stack including at least one second nanosheet surrounded by the gate line; and an inter-region insulating pattern on the isolation film between the first fin active region and the second fin active region and partially penetrating the gate line in the vertical direction, wherein the inter-region insulating pattern has a bottom surface contacting the isolation film, a top surface contacting the gate line, and a side wall linearly extending from the bottom surface to the top surface.

The embodiments may be realized by providing an integrated circuit device including a substrate including an N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel MOS (PMOS) transistor region separated from the NMOS transistor region; a first fin active region extending in a first horizontal direction on the NMOS transistor region; a second fin active region extending in the first horizontal direction on the PMOS transistor region; an isolation film covering opposite side walls of each of the first fin active region and the second fin active region; a plurality of gate cut insulating patterns on the isolation film on the NMOS transistor region and the PMOS transistor region and having a first height in a vertical direction; a gate line extending on the NMOS transistor region and the PMOS transistor region in a second horizontal direction that crosses the first horizontal direction; a first nanosheet stack on the first fin active region and including at least one first nanosheet surrounded by the gate line; a second nanosheet stack on the second fin active region and including at least one second nanosheet surrounded by the gate line; and an inter-region insulating pattern between the NMOS transistor region and the PMOS transistor region, partially penetrating the gate line in the vertical direction, and having a second height in the vertical direction that is less than the first height, wherein the inter-region insulating pattern has a bottom surface contacting the isolation film, a top surface contacting the gate line, and a side wall linearly extending from the bottom surface to the top surface.

DETAILED DESCRIPTION

FIG.1is a plane layout diagram of partial configurations of an integrated circuit device100, according to embodiments.FIG.2Ais a cross-sectional view of a partial configuration of a cross-section taken along line X1-X1′ inFIG.1;FIG.2Bis a cross-sectional view showing a partial configuration of a cross-section taken along line X2-X2′ inFIG.1; andFIG.2Cis a cross-sectional view of a partial configuration of a cross-section taken along line Y1-Y1′ inFIG.1.

Referring toFIG.1andFIGS.2A through2C, the integrated circuit device100may include a substrate102, which includes a first device region AR1and a second device region AR2, and a plurality of fin active regions F1and F2, which respectively protrude from the first and second device regions AR1and AR2of the substrate102in a vertical direction (a Z direction). The fin active regions F1and F2may extend to be parallel with each other in a first horizontal direction (an X direction). The fin active regions F1and F2may include a first fin active region F1, which protrudes from the first device region AR1of the substrate102in the vertical direction, and a second fin active region F2, which protrudes from the second device region AR2of the substrate102in the vertical direction. In an implementation, as illustrated inFIG.1, one first fin active region F1may be on the first device region AR1and one second fin active region F2may be on the second device region AR2, or a plurality of fin active regions may be arranged on each of the first and second device regions AR1and AR2.

The substrate102may include a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. Each of the terms “SiGe”, “SiC”, “GaAs”, “InAs”, “InGaAs”, and “InP” used herein indicates a material composed of elements included in each term and is not a chemical equation representing stoichiometric relationships. The substrate102may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

An isolation film112, which covers both, e.g., opposite) side walls of each of the first and second fin active regions F1and F2, may be in the substrate102. The isolation film112may include an oxide film, a nitride film, or a combination thereof. The first fin active region F1may protrude upwardly through the isolation film112in a fin shape on the first device region AR1, and the second fin active region F2may protrude upwardly through the isolation film112in a fin shape on the second device region AR2.

A plurality of gate lines160may extend lengthwise on the first and second fin active regions F1and F2in a second horizontal direction (a Y direction) that crosses the first horizontal direction. Each of a plurality of nanosheet stacks NSS may be above or on a fin top FT of one of the first and second fin active regions F1and F2at an intersection between a corresponding one of the first and second fin active regions F1and F2and one of the gate lines160. Each of the nanosheet stacks NSS may face the fin top FT of a corresponding one of the first and second fin active regions F1and F2at a position separated in the vertical direction from the corresponding one of the first and second fin active regions F1and F2. The term “nanosheet” used herein refers to a conductive structure having a cross-section that is substantially perpendicular to a direction in which electric current flows. It will be understood that the nanosheet may include a nanowire.

Each of the nanosheet stacks NSS may include a plurality of nanosheets, which overlap each other above the fin top FT of a corresponding one of the first and second fin active regions F1and F2in the vertical direction. The nanosheets may respectively have different vertical distances (e.g., Z-direction distances) from the fin top FT. The nanosheets may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, which are sequentially stacked on the fin top FT of each of the first and second fin active regions F1and F2.

The numbers of nanosheet stacks NSS and gate lines160, which are arranged on one fin active region, e.g., the first fin active region F1or the second fin active region F2, may be a suitable number. In an implementation, one or more nanosheet stacks NSS and one or more gate lines160may be arranged on one fin active region, e.g., the first fin active region F1or the second fin active region F2.

In an implementation, as illustrated inFIGS.2A through2C, each of the nanosheet stacks NSS may include three nanosheets, e.g., the first, second, and third nanosheets N1, N2, and N3. In an implementation, the number of nanosheets included in each nanosheet stack NSS may be a suitable number. In an implementation, each of the nanosheet stacks NSS may include one nanosheet, two nanosheets, or at least four nanosheets. Each of the first, second, and third nanosheets N1, N2, and N3may have a channel region. In an implementation, each of the first, second, and third nanosheets N1, N2, and N3may have a thickness (e.g., in the Z direction) of about 4 nm to about 6 nm. In an implementation, the thickness of each of the first, second, and third nanosheets N1, N2, and N3refers to a size in the vertical direction (the Z direction). In an implementation, the first, second, and third nanosheets N1, N2, and N3may have substantially the same thickness as one another in the vertical direction. In an implementation, at least some of the first, second, and third nanosheets N1, N2, and N3may have different thicknesses from each other in the vertical direction.

In an implementation, as shown inFIGS.2A and2B, the first, second, and third nanosheets N1, N2, and N3of one nanosheet stack NSS may have the same size as one another in the first horizontal direction. In an implementation, at least some of the first, second, and third nanosheets N1, N2, and N3of one nanosheet stack NSS may have different sizes from each other in the first horizontal direction. In an implementation, the length (in the first horizontal direction) of each of the first and second nanosheets N1and N2, which are relatively close or proximate to the fin top FT, may be less than the length (in the first horizontal direction) of the third nanosheet N3, which is farthest from or distal to the fin top FT.

A plurality of first recesses R1may be in a top surface of the first fin active region F1on the first device region AR1, and a plurality of second recesses R2may be in a top surface of the second fin active region F2on the second device region AR2. In an implementation, as illustrated inFIGS.2A and2B, the level of the bottommost surface of each of the first recesses R1and the second recesses R2may be lower than the level of the fin top FT of each of the first and second fin active regions F1and F2. In an implementation, the level of the bottommost surface of each of the first recesses R1and the second recesses R2may be the same as or similar to the level of the fin top FT of each of the first and second fin active regions F1and F2.

A plurality of first source/drain regions SD1may be on the first recesses R1on the first device region AR1, and a plurality of second source/drain regions SD2may be on the second recesses R2on the second device region AR2.

The gate lines160may extend lengthwise on the first and second fin active regions F1and F2and the isolation film112in the second horizontal direction (the Y direction) on the first and second device regions AR1and AR2. The gate lines160may be on the first and second fin active regions F1and F2and may cover the nanosheet stacks NSS and may surround each of the first, second, and third nanosheets N1, N2, and N3. A plurality of transistors, e.g., N-channel metal-oxide semiconductor (NMOS) transistors TR1and P-channel MOS (PMOS) transistors TR2, may be on the substrate102at intersections between the first and second fin active regions F1and F2and the gate lines160. In an implementation, the first device region AR1may correspond to an NMOS transistor region, and the second device region AR2may correspond to a PMOS transistor region. The NMOS transistors TR1may be at the intersections between the first fin active region F1and the gate lines160on the first device region AR1, and the PMOS transistors TR2may be at the intersections between the second fin active region F2and the gate lines160on the second device region AR2.

Each of the gate lines160may include a main gate portion160M and a plurality of sub gate portions160S. The main gate portion160M may extend lengthwise in the second horizontal direction (the Y direction) to cover the top surface of a nanosheet stack NSS. The sub gate portions160S may be integrally connected to the main gate portion160M and respectively between the third nanosheet N3and the second nanosheet N2, between the second nanosheet N2and the first nanosheet N1, and between the first nanosheet N1and the first or second fin active region F1or F2.

Each of the gate lines160may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may include TiN or TaN. The metal carbide may include TiAlC.

A plurality of gate cut insulating patterns and an inter-region insulating pattern150C may be on the isolation film112on the substrate102.

The gate cut insulating patterns may include a first gate cut insulating pattern150A on the first device region AR1and a second gate cut insulating pattern150B on the second device region AR2. The inter-region insulating pattern150C may be at a boundary between the first device region AR1and the second device region AR2.

Each of the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C may extend lengthwise in the first horizontal direction (the X direction) to cross the gate lines160.

A height HA of the first gate cut insulating pattern150A in the vertical direction (the Z direction) may be the same as or similar to a height HB of the second gate cut insulating pattern150B in the vertical direction (the Z direction). A level of a topmost surface of each of the first and second gate cut insulating patterns150A and150B may be the same as or similar to the level of a topmost surface of the gate lines160(e.g., the surfaces may be coplanar). A pair of gate lines160, which are respectively adjacent to both sides of one of the first and second gate cut insulating patterns150A and150B in the second horizontal direction (the Y direction), may not be connected, and may be separated from each other.

A height HC of the inter-region insulating pattern150C in the vertical direction (the Z direction) may be less than the heights HA and HB of the respective first and second gate cut insulating patterns150A and150B.

Some gate lines160that are arranged in a line in the second horizontal direction (the Y direction) may be separated from one another by the first and second gate cut insulating patterns150A and150B. At least one gate line160among the gate lines160may have a length limited in the second horizontal direction (the Y direction) by the first and second gate cut insulating patterns150A and150B and may extend lengthwise in the second horizontal direction (the Y direction) on the first and second device regions AR1and AR2.

The inter-region insulating pattern150C may only partially penetrate the gate line160in the vertical direction (the Z direction). The gate line160may have a structure, in which only a lower portion is partially cut by the inter-region insulating pattern150C on the isolation film112between the first fin active region F1and the second fin active region F2. The gate line160may include a gate connecting portion GCP covering or on the inter-region insulating pattern150C. A portion of the gate line160on the first device region AR1may be integrally connected to a portion of the gate line160on the second device region AR2through the gate connecting portion GCP. The inter-region insulating pattern150C may have a bottom surface, which is in contact (e.g., direct contact) with the isolation film112and closest or proximate to the substrate102, a top surface, which is in contact (e.g., direct contact) with the gate line160and farthest from or distal to the substrate102, and side walls linearly extending from the bottom surface to the top surface. The top surface of the inter-region insulating pattern150C may be in contact (e.g., direct contact) with the gate line160.

In the vertical direction (the Z direction), the length of the gate connecting portion GCP may be less than the length (in the vertical direction) of the inter-region insulating pattern150C. In an implementation, in the vertical direction (the Z direction), the length of the gate connecting portion GCP may be greater than or equal to the length of the inter-region insulating pattern150C.

In an implementation, each of the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C may include a nitrogen-containing insulating film. In an implementation, each of the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C may include a silicon nitride film.

In an implementation, as shown inFIG.2C, in the second horizontal direction (the Y direction), a shortest (e.g., lateral) distance D11between the inter-region insulating pattern150C and the first fin active region F1may be the same as or similar to a shortest (e.g., lateral) distance D12between the inter-region insulating pattern150C and the second fin active region F2. In an implementation, a relative position of the inter-region insulating pattern150C between the first and second fin active regions F1and F2may be determined, taking into account the performance of the NMOS transistor TR1on the first device region AR1and the performance of the PMOS transistor TR2on the second device region AR2.

The level of the topmost surface of the inter-region insulating pattern150C may be lower than the level of the topmost surface of each of the first and second gate cut insulating patterns150A and150B. In an implementation, the level of the topmost surface of the inter-region insulating pattern150C may be lower than or equal to the level of the topmost surface of the nanosheet stacks NSS. In an implementation, the level of the topmost surface of the inter-region insulating pattern150C may be lower than the level of the topmost surface of each of the first and second gate cut insulating patterns150A and150B and higher than the level of the topmost surface of the nanosheet stacks NSS. In the specification, the term “level” refers to a height from the top surface of the substrate102in the vertical direction (the Z direction or a −Z direction).

A gate dielectric film152may be between the first, second, and third nanosheets N1, N2, and N3of each nanosheet stack NSS and the gate line160. The gate dielectric film152may include portions covering the surfaces of the first, second, and third nanosheets N1, N2, and N3; portions covering the side walls of the main gate portion160M; and portions covering the sidewalls of the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C.

In an implementation, the gate dielectric film152may include a stack structure of an interface film and a high-k dielectric film. The interface film may include a low-k dielectric film, e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof, having a permittivity of about 9 or less. In an implementation, the interface film may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than a silicon oxide film. In an implementation, the high-k dielectric film may have a dielectric constant of about 10 to about 25. In an implementation, the high-k dielectric film may include hafnium oxide.

In an implementation, the first, second, and third nanosheets N1, N2, and N3may respectively include semiconductor layers including the same element. In an implementation, each of the first, second, and third nanosheets N1, N2, and N3may include an Si layer. On the first device region AR1, the first, second, and third nanosheets N1, N2, and N3may be doped with a dopant of the same conductivity type as the first source/drain region SD1. On the second device region AR2, the first, second, and third nanosheets N1, N2, and N3may be doped with a dopant of the same conductivity type as the second source/drain region SD2. In an implementation, the first, second, and third nanosheets N1, N2, and N3on the first device region AR1may include an Si layer doped with an n-type dopant, and the first, second, and third nanosheets N1, N2, and N3on the second device region AR2may include an Si layer doped with a p-type dopant.

Both (e.g., opposite) side walls of each gate line160on the first and second fin active regions F1and F2and the isolation film112may be covered with a plurality of outer insulating spacers118. The outer insulating spacers118may be on the top surface of the nanosheet stacks NSS to cover both (e.g., opposite) side walls of the main gate portion160M. Each of the outer insulating spacers118may be separated from the gate line160with the gate dielectric film152between each outer insulating spacer118and the gate line160. The outer insulating spacers118may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. Each of the terms “SiCN” “SiBN”, “SiON”, “SiOCN”, “SiBCN”, and “SiOC” used herein indicates a material composed of elements included in each term and is not a chemical equation representing stoichiometric relationships.

As shown inFIG.2A, on the first device region AR1, a plurality of inner insulating spacers120may be between the third nanosheet N3and the second nanosheet N2, between the second nanosheet N2and the first nanosheet N1, between the first nanosheet N1and the first fin active region F1, and between the sub gate portions160S and the first source/drain region SD1. Each of opposite side walls of each of the sub gate portions160S on the first device region AR1may be covered with an inner insulating spacer120with the gate dielectric film152between the side wall of each sub gate portion160S and the inner insulating spacer120. On the first device region AR1, each of the sub gate portions160S may be separated from the first source/drain region SD1with the gate dielectric film152and the inner insulating spacer120between each sub gate portion160S and the first source/drain region SD1. Each of the inner insulating spacers120may be in contact (e.g., direct contact) with the first source/drain region SD1. At least some of the inner insulating spacers120may overlap any one of the outer insulating spacers118in the vertical direction (the Z direction). The inner insulating spacers120may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The inner insulating spacers120may further include an air gap. In an implementation, the inner insulating spacers120may include the same material as the outer insulating spacers118. In an implementation, the outer insulating spacers118may include a different material than the inner insulating spacers120.

On the first device region AR1, each of a plurality of first source/drain regions SD1may face each of the sub gate portions160S with an inner insulating spacer120between each first source/drain region SD1and each sub gate portion160S in the first horizontal direction (the X direction). The first source/drain regions SD1may not include any portion that is in contact with the gate dielectric film152.

In an implementation, as shown inFIG.2B, on the second device region AR2, each of both (e.g., opposite) side walls of each of the sub gate portions160S between the third nanosheet N3and the second nanosheet N2, between the second nanosheet N2and the first nanosheet N1, and between the first nanosheet N1and the second fin active region F2may be separated from a second source/drain region SD2with the gate dielectric film152between each side wall of each sub gate portion160S and the second source/drain region SD2. The gate dielectric film152may include a portion that is in contact (e.g., direct contact) with the second source/drain region SD2. Each of a plurality of second source/drain regions SD2may face the nanosheet stack NSS and the sub gate portions160S in the first horizontal direction (the X direction).

In an implementation, the gate lines160may have a structure, in which a metal nitride film, a metal film, a conductive capping film, and a gap-fill metal film are sequentially stacked. The metal nitride film and the metal film may include Ti, Ta, W, Ru, Nb, Mo, or Hf. The gap-fill metal film may include a W film or an Al film. Each of the gate lines160may include a work function metal film. The work function metal film may include a metal, e.g., Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. In an implementation, each of the gate lines160may include a stack structure of TiAlC/TiN/W, TiN/TaN/TiAlC/TiN/W, or TiN/TaN/TiN/TiAlC/TiN/W.

In an implementation, as shown inFIGS.2A through2C, the gate line160and the gate dielectric film152(covering the side walls of the gate line160) may be covered with a capping insulating pattern164. The capping insulating pattern164may include a silicon nitride film.

On the first device region AR1, the main gate portion160M of the gate line160may be separated from a first source/drain region SD1with an outer insulating spacer118between the main gate portion160M and the first source/drain region SD1. On the second device region AR2, the main gate portion160M of the gate line160may be separated from a second source/drain region SD2with an outer insulating spacer118between the main gate portion160M and the second source/drain region SD2.

In an implementation, the first device region AR1may correspond to an NMOS transistor region, and the second device region AR2may correspond to a PMOS transistor region. In this case, a plurality of first source/drain regions SD1on the first device region AR1may include an Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant, and a plurality of second source/drain regions SD2on the second device region AR2may include a SiGe layer doped with a p-type dopant. The n-type dopant may include, e.g., phosphorus (P), arsenic (As), or antimony (Sb). The p-type dopant may include, e.g., boron (B) or gallium (Ga).

In an implementation, the first source/drain regions SD1on the first device region AR1may have a different shape and size than the second source/drain regions SD2on the second device region AR2. In an implementation, a plurality of first and second source/drain regions SD1and SD2having various shapes and sizes may be on the first and second device regions AR1and AR2.

In an implementation, as shown inFIGS.2A and2B, the first and second source/drain regions SD1and SD2may be covered with an insulating liner142. The insulating liner142may conformally cover the outer insulating spacer118and the surface of each of the first and second source/drain regions SD1and SD2. The insulating liner142may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or a combination thereof.

On the first and second device regions AR1and AR2, the insulating liner142may be covered with an intergate insulating film144. The intergate insulating film144may include a silicon nitride film, a silicon oxide film, SiON, SiOCN, or a combination thereof. A plurality of capping insulating patterns164and the intergate insulating film144between each of the capping insulating patterns164may be covered with an insulating structure190. The insulating structure190may include an etch stop film190A and an interlayer insulating film190B. The etch stop film190A may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film190B may include an oxide film, a nitride film, an ultra low-k (ULK) film having an ultra low dielectric constant k of about 2.2 to about 2.4, or a combination thereof. In an implementation, the interlayer insulating film190B may include a tetraethylorthosilicate (TEOS) film, a high density plasma (HDP) film, a boro-phospho-silicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof.

In an implementation, as shown inFIGS.2A and2B, on the first and second device regions AR1and AR2, a plurality of source/drain contacts174and a plurality of source/drain via contacts192may be on the first and second source/drain regions SD1and SD2. The first and second source/drain regions SD1and SD2may be connected to a conductive line thereabove through the source/drain contacts174and the source/drain via contacts192.

A metal silicide film172may be between each of the first and second source/drain regions SD1and SD2and a source/drain contact174. In an implementation, the metal silicide film172may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. In an implementation, the metal silicide film172may include titanium silicide. The source/drain contact174may pass through the intergate insulating film144and the insulating liner142in the vertical direction (the Z direction) and may be in contact (e.g., direct contact) with the metal silicide film172. Each of the source/drain via contacts192may pass through the insulating structure190in the vertical direction (the Z direction) and may be in contact (e.g., direct contact) with the source/drain contact174.

Each of the source/drain contacts174may include a conductive barrier film174A and a metal plug174B. Each of the source/drain via contacts192may include a conductive barrier film192A and a metal plug192B. The conductive barrier films174A and192A may include Ti, Ta, TiN, TaN, or a combination thereof, and the metal plugs174B and192B may include W, Co, Cu, Ru, Mn, or a combination thereof. In an implementation, a side wall of each of the source/drain contacts174and the source/drain via contacts192may be surrounded by a contact insulating spacer. The contact insulating spacer may include SiCN, SiOCN, silicon nitride (SiN), or a combination.

A gate contact may be on a top of each of the gate lines160. Each of the gate lines160may be connected to a conductive line thereabove through the gate contact. The gate contact may have a structure similar to that of each of the source/drain contacts174and the source/drain via contacts192.

The integrated circuit device100illustrated inFIG.1andFIGS.2A through2Cmay include the inter-region insulating pattern150C on the isolation film112between the first device region AR1and the second device region AR2. The inter-region insulating pattern150C may help remove or reduce the probability of occurrence of defective processes during the manufacture of the integrated circuit device100and may contribute to the enhancement of the performance and reliability of the NMOS transistor TR1on the first device region AR1and the PMOS transistor TR2on the second device region AR2.

FIG.3is a cross-sectional view of an integrated circuit device100A according to some embodiments.FIG.3illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1.

Referring toFIG.3, the integrated circuit device100A may have substantially the same configuration as the integrated circuit device100described with reference toFIG.1andFIGS.2A through2C. The integrated circuit device100A may include a plurality of gate lines160A. The gate lines160A may have substantially the same configuration as the gate lines160described with reference toFIG.1andFIGS.2A through2C. In an implementation, the gate lines160A may have different stack structures between the first device region AR1and the second device region AR2.

Each of the gate lines160A may have a stack structure, and may include at least two layers selected from a first work function metal film ML1, a second work function metal film ML2, and a gap-fill metal film ML3. In an implementation, the first work function metal film ML1may include a TiN film. The second work function metal film ML2may include a combination of a first TiN film, a TiAlC film, and a second TiN film. The gap-fill metal film ML3may include W, Al, or a combination thereof.

On a portion of the second device region AR2, a gate line160A may include the first work function metal film ML1contacting (e.g., directly contacting) the gate dielectric film152and the second work function metal film ML2contacting (e.g., directly contacting) the first work function metal film ML1. On another portion of the second device region AR2, a gate line160A may include the first work function metal film ML1contacting (e.g., directly contacting) the gate dielectric film152, the second work function metal film ML2contacting (e.g., directly contacting) the first work function metal film ML1, and the gap-fill metal film ML3contacting (e.g., directly contacting) the second work function metal film ML2.

The gate line160A on the first device region AR1may not include the first work function metal film ML1. In an implementation, the gate line160A on the first device region AR1may include the second work function metal film ML2contacting (e.g., directly contacting) the gate dielectric film152and the gap-fill metal film ML3contacting (e.g., directly contacting) the second work function metal film ML2.

The inter-region insulating pattern150C between the first device region AR1and the second device region AR2may have a flat top surface TA. The flat top surface TA of the inter-region insulating pattern150C may be covered with the gap-fill metal film ML3. Similarly to the description of the gate connecting portion GCP that has been given with reference toFIG.2C, a portion of the gate line160A on the first device region AR1may be integrally connected to a portion of the gate line160A in the second device region AR2through the gap-fill metal film ML3that covers the flat top surface TA of the inter-region insulating pattern150C.

In an implementation, the gap-fill metal film ML3that covers the flat top surface TA of the inter-region insulating pattern150C may include a single metal film. In an implementation, the gap-fill metal film ML3that covers the flat top surface TA of the inter-region insulating pattern150C may include a W film or an Al film.

FIG.4is a cross-sectional view of an integrated circuit device100B according to some embodiments.FIG.4illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1.

Referring toFIG.4, the integrated circuit device100B may have substantially the same configuration as the integrated circuit device100A described with reference toFIG.3. The inter-region insulating pattern150C of the integrated circuit device100B may have a non-linear or non-planar top surface TB (e.g., the top surface TB may not be flat). The integrated circuit device100B may include a gate line160B, which includes the gap-fill metal film ML3covering the non-planar top surface TB of the inter-region insulating pattern150C. A portion of the gap-fill metal film ML3of the gate line160B may be in contact (e.g., direct contact) with the non-planar top surface TB and have a non-planar surface corresponding to (e.g., complementary to) the non-planar top surface TB. The detailed configuration of the gate line160B may be substantially the same as that of the gate line160A described with reference toFIG.3.

Similarly to the description of the gate connecting portion GCP that has been given with reference toFIG.2C, a portion of the gate line160B on the first device region AR1may be integrally connected to a portion of the gate line160B on the second device region AR2through the portion of the gap-fill metal film ML3that covers the non-planar top surface TB of the inter-region insulating pattern150C.

FIG.5is a cross-sectional view of an integrated circuit device200according to some embodiments.FIG.5illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1.

Referring toFIG.5, the integrated circuit device200may have substantially the same configuration as the integrated circuit device100described with reference toFIG.1andFIGS.2A through2C. In an implementation, the integrated circuit device200may include a gate line260, which extends lengthwise on the first device region AR1and the second device region AR2in the second horizontal direction (the Y direction), and an inter-region insulating pattern250C on the isolation film112between the first device region AR1and the second device region AR2.

Similarly to the description of the gate line160that has been given with reference toFIG.1andFIGS.2A through2C, the gate line260may include the main gate portion160M and the sub gate portions160S and may have a length limited or defined in the second horizontal direction (the Y direction) by the first and second gate cut insulating patterns150A and150B. The gate line260may have a structure, in which only a lower portion is partially cut by the inter-region insulating pattern250C on the isolation film112. The gate line260may include a gate connecting portion GCP2covering or on the top surface of the inter-region insulating pattern250C. A portion of the gate line260on the first device region AR1may be integrally connected to a portion of the gate line260on the second device region AR2through the gate connecting portion GCP2.

The inter-region insulating pattern250C may have substantially the same configuration as the inter-region insulating pattern150C described with reference toFIG.1andFIGS.2A through2C. In an implementation, the inter-region insulating pattern250C may be closer to the first fin active region F1of the first device region AR1than to the second fin active region F2of the second device region AR2. In the second horizontal direction (the Y direction), a shortest (e.g., lateral) distance D21between the inter-region insulating pattern250C and the first fin active region F1may be less than a shortest (e.g., lateral) distance D22between the inter-region insulating pattern250C and the second fin active region F2. In an implementation, a volume of a portion of the gate line260between the nanosheet stack NSS on the first device region AR1and the inter-region insulating pattern250C may be less than a volume of a portion of the gate line260between the nanosheet stack NSS on the second device region AR2and the inter-region insulating pattern250C. The detailed configuration of the gate line260may be substantially the same as that of the gate line160described with reference toFIG.1andFIGS.2A through2C.

In an implementation, the gate line260may have different stack structures between or on the first device region AR1and the second device region AR2. In an implementation, similarly to the description of the gate line160A that has been given with reference toFIG.3, the gate line260on the first device region AR1may include the second work function metal film ML2contacting the gate dielectric film152and the gap-fill metal film ML3contacting the second work function metal film ML2. On a portion of the second device region AR2, the gate line260may include the first work function metal film ML1contacting the gate dielectric film152and the second work function metal film ML2contacting the first work function metal film ML1. On another portion of the second device region AR2, the gate line260may include the first work function metal film ML1contacting the gate dielectric film152, the second work function metal film ML2contacting the first work function metal film ML1, and the gap-fill metal film ML3contacting the second work function metal film ML2. The detailed configurations of the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3have been described above with reference toFIG.3.

FIG.6is a cross-sectional view of an integrated circuit device300according to some embodiments.FIG.6illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1.

Referring toFIG.6, the integrated circuit device300may have substantially the same configuration as the integrated circuit device100described with reference toFIG.1andFIGS.2A through2C. In an implementation, the integrated circuit device300may include a gate line360, which extends lengthwise on the first device region AR1and the second device region AR2in the second horizontal direction (the Y direction), and an inter-region insulating pattern350C on the isolation film112between the first device region AR1and the second device region AR2.

Similarly to the description of the gate line160that has been given with reference toFIG.1andFIGS.2A through2C, the gate line360may include the main gate portion160M and the sub gate portions160S and may have a length limited in the second horizontal direction (the Y direction) by the first and second gate cut insulating patterns150A and150B. The gate line360may have a structure, in which only a lower portion is partially cut by the inter-region insulating pattern350C on the isolation film112. The gate line360may include a gate connecting portion GCP3covering the top surface of the inter-region insulating pattern350C. A portion of the gate line360on the first device region AR1may be integrally connected to a portion of the gate line360on the second device region AR2through the gate connecting portion GCP3.

The inter-region insulating pattern350C may have substantially the same configuration as the inter-region insulating pattern150C described with reference toFIG.1andFIGS.2A through2C. In an implementation, the inter-region insulating pattern350C may be closer to the second fin active region F2on the second device region AR2than to the first fin active region F1on the first device region AR1. In the second horizontal direction (the Y direction), a shortest (e.g., lateral) distance D31between the inter-region insulating pattern350C and the first fin active region F1may be greater than a shortest (e.g., lateral) distance D32between the inter-region insulating pattern350C and the second fin active region F2. In an implementation, the volume of a portion of the gate line360between the nanosheet stack NSS on the first device region AR1and the inter-region insulating pattern350C may be greater than the volume of a portion of the gate line360between the nanosheet stack NSS on the second device region AR2and the inter-region insulating pattern350C. The detailed configuration of the gate line360is substantially the same as that of the gate line160described with reference toFIG.1andFIGS.2A through2C.

In an implementation, the gate line360may have different stack structures between or on the first device region AR1and the second device region AR2. In an implementation, similarly to the description of the gate line160A that has been given with reference toFIG.3, the gate line360on the first device region AR1may include the second work function metal film ML2contacting the gate dielectric film152and the gap-fill metal film ML3contacting the second work function metal film ML2. On a portion of the second device region AR2, the gate line360may include the first work function metal film ML1contacting the gate dielectric film152and the second work function metal film ML2contacting the first work function metal film ML1. On another portion of the second device region AR2, the gate line360may include the first work function metal film ML1contacting the gate dielectric film152, the second work function metal film ML2contacting the first work function metal film ML1, and the gap-fill metal film ML3contacting the second work function metal film ML2. The detailed configurations of the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3have been described above with reference toFIG.3.

FIG.7is a cross-sectional view of an integrated circuit device400according to some embodiments.FIG.7illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1.

Referring toFIG.7, the integrated circuit device400may have substantially the same configuration as the integrated circuit device100described with reference toFIG.1andFIGS.2A through2C. In an implementation, the integrated circuit device400may include a gate line460, which extends lengthwise on the first device region AR1and the second device region AR2in the second horizontal direction (the Y direction), and an inter-region insulating pattern450C on the isolation film112between the first device region AR1and the second device region AR2. A height H4C of the inter-region insulating pattern450C in the vertical direction (the Z direction) may be less than each of the heights HA and HB of the respective first and second gate cut insulating patterns150A and150B in the vertical direction (the Z direction).

Similarly to the description of the gate line160that has been given with reference toFIG.1andFIGS.2A through2C, the gate line460may include the main gate portion160M and the sub gate portions160S and may have a length limited in the second horizontal direction (the Y direction) by the first and second gate cut insulating patterns150A and150B. The gate line460may have a structure, in which only a lower portion is partially cut by the inter-region insulating pattern450C on the isolation film112. The gate line460may include a gate connecting portion GCP4covering the top surface of the inter-region insulating pattern450C. A portion of the gate line460on the first device region AR1may be integrally connected to a portion of the gate line460on the second device region AR2through the gate connecting portion GCP4.

A length or height of the gate connecting portion GCP4may be greater than the length or height of the inter-region insulating pattern450C in the vertical direction (the Z direction). In an implementation, a level of the topmost surface of the inter-region insulating pattern450C may be lower than a level of the topmost surface of the nanosheet stack NSS. In an implementation, at least one of the first, second, and third nanosheets N1, N2, and N3of the nanosheet stack NSS may be at a higher level than the topmost surface of the inter-region insulating pattern450C.

The detailed configuration of the gate line460is substantially the same as that of the gate line160described with reference toFIG.1andFIGS.2A through2C. In an implementation, the gate line460may have different stack structures between or on the first device region AR1and the second device region AR2. In an implementation, similarly to the description of the gate line160A that has been given with reference toFIG.3, the gate line460on the first device region AR1may include the second work function metal film ML2contacting the gate dielectric film152and the gap-fill metal film ML3contacting the second work function metal film ML2. On a portion of the second device region AR2, the gate line460may include the first work function metal film ML1contacting the gate dielectric film152and the second work function metal film ML2contacting the first work function metal film ML1. On another portion of the second device region AR2, the gate line460may include the first work function metal film ML1contacting the gate dielectric film152, the second work function metal film ML2contacting the first work function metal film ML1, and the gap-fill metal film ML3contacting the second work function metal film ML2. The detailed configurations of the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3have been described above with reference toFIG.3.

FIG.8is a plane layout diagram of partial configurations of an integrated circuit device500, according to embodiments.FIG.9is a cross-sectional view showing a partial configuration of a cross-section taken along line Y1-Y1′ inFIG.8.

Referring toFIGS.8and9, the integrated circuit device500may have substantially the same configuration as the integrated circuit device100described with reference toFIG.1andFIGS.2A through2C. In an implementation, the integrated circuit device500may include a plurality of gate lines560on the first and second fin active regions AR1and F2on the first and second device regions AR1and AR2and an inter-region insulating pattern550C on the isolation film112between the first device region AR1and the second device region AR2. A height H5C of the inter-region insulating pattern550C in the vertical direction (the Z direction) may be the same as or similar to each of the heights HA and HB of the respective first and second gate cut insulating patterns150A and150B in the vertical direction (the Z direction). The inter-region insulating pattern550C may include a silicon nitride film.

Similarly to the description of the gate line160that has been given with reference toFIG.1andFIGS.2A through2C, each of the gate lines560may include the main gate portion160M and the sub gate portions160S. In an implementation, the length of a gate line560on the first device region AR1in the second horizontal direction (the Y direction) may be limited by the first gate cut insulating pattern150A and the inter-region insulating pattern550C. The length of a gate line560on the second device region AR2in the second horizontal direction (the Y direction) may be limited by the second gate cut insulating pattern150B and the inter-region insulating pattern550C.

Among the gate lines560, a pair of gate lines560, which are respectively on the first device region AR1and the second device region AR2and arranged in a line (e.g., aligned) in the second horizontal direction (the Y direction), may be separated from each other in the second horizontal direction (the Y direction) with the inter-region insulating pattern550C therebetween. The pair of gate lines560may not include a portion that covers the top surface of the inter-region insulating pattern550C. In an implementation, the level of the topmost surface of the inter-region insulating pattern550C may be the same as or similar to the level of the topmost surface of each gate line560.

The detailed configuration of the gate line560is substantially the same as that of the gate line160described with reference toFIG.1andFIGS.2A through2C.

In the integrated circuit device500, a pair of gate lines560, which are arranged in a line in the second horizontal direction (the Y direction) and separated from each other with the inter-region insulating pattern550C therebetween in the second horizontal direction (the Y direction), may be electrically connected to each other. For this configuration, the integrated circuit device500may include a pair of gate contacts582respectively connected to the gate lines560and a conductive line586connected to the gate contacts582. The gate lines560may be electrically connected to each other through the gate contacts582and the conductive line586.

Each of the gate contacts582may include a conductive barrier film582A and a metal plug582B. The conductive barrier film582A may include Ti, Ta, TiN, TaN, or a combination thereof, and the metal plug582B may include W, Co, Cu, Ru, Mn, or a combination thereof. The conductive line586may include Ti, Ta, TiN, TaN, W, Co, Cu, Ru, Mn, or a combination thereof. In an implementation, the material and shape of each of the gate contacts582and the conductive line586may be variously changed or modified.

FIG.10is a cross-sectional view of an integrated circuit device500A according to some embodiments.FIG.10illustrates a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.8.

Referring toFIG.10, the integrated circuit device500A may have substantially the same configuration as the integrated circuit device500described with reference toFIGS.8and9. In an implementation, the integrated circuit device500A may include a plurality of gate lines560A. The gate lines560A may have substantially the same configuration as the gate lines560described with reference toFIGS.8and9. In an implementation, gate lines560A on the first device region AR1may have a different stack structure than gate lines560A on the second device region AR2.

Each of the gate lines560A may have a stack structure, and may include at least two layers selected from a first work function metal film ML1, a second work function metal film ML2, and a gap-fill metal film ML3. A gate line560A on the first device region AR1may not include the first work function metal film ML1. In an implementation, the gate line560A on the first device region AR1may include the second work function metal film ML2contacting the gate dielectric film152and the gap-fill metal film ML3contacting the second work function metal film ML2. Some gate lines560A on the second device region AR2may include the first work function metal film ML1contacting the gate dielectric film152and the second work function metal film ML2contacting the first work function metal film ML1. Other gate lines560A on the second device region AR2may include the first work function metal film ML1contacting the gate dielectric film152, the second work function metal film ML2contacting the first work function metal film ML1, and the gap-fill metal film ML3contacting the second work function metal film ML2. The detailed configurations of the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3have been described above with reference toFIG.3.

Each of the integrated circuit devices100,100A,100B,200,300,400,500, and500A described with reference toFIGS.1through10includes the inter-region insulating pattern150C,250C,350C,450C, or550C on the isolation film112between the first device region AR1and the second device region AR2. Each of the inter-region insulating patterns150C,250C,350C,450C, and550C may help remove or reduce the probability of occurrence of defective processes during the manufacture of the integrated circuit device100,100A,100B,200,300,400,500, or500A and may contribute to the enhancement of the performance and reliability of the NMOS transistor TR1in the first device region AR1and the PMOS transistor TR2in the second device region AR2.

FIGS.11A through25are cross-sectional views of stages in a method of manufacturing an integrated circuit device, according to embodiments, in whichFIGS.11A,12A, . . . , and17A show a partial configuration of a portion corresponding to the cross-section taken along the line X1-X1′ inFIG.1,FIGS.11B,12B, . . . , and17B show a partial configuration of a portion corresponding to the cross-section taken along the line X2-X2′ inFIG.1, andFIGS.11C,12C, . . . , and17C andFIGS.18through25show a partial configuration of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.1. Example methods of manufacturing the integrated circuit devices100and100B illustrated inFIGS.1through3will be described with reference toFIGS.11A through25below. InFIGS.1through3andFIGS.11A through25, like reference numerals denote like elements, and detailed descriptions thereof may be omitted.

Referring toFIGS.11A through11C, a plurality of sacrificial semiconductor layers104and a plurality of nanosheet semiconductor layers NS may be alternately stacked on the substrate102. Thereafter, the first fin active region F1and the second fin active region F2, which protrude above the substrate102in the vertical direction (the Z direction) and extend in the first horizontal direction (the X direction) to be parallel with each other, by partially etching each of the sacrificial semiconductor layers104, the nanosheet semiconductor layers NS, and the substrate102; and the isolation film112, which covers both side walls of a lower portion of each of the first and second fin active regions F1and F2, may be formed. The level of the top surface of the isolation film112may be the same as or similar to the level of the fin top FT of each of the first and second fin active regions F1and F2.

A stack structure of the sacrificial semiconductor layers104and the nanosheet semiconductor layers NS may remain on the fin top FT of each of the first fin active region F1on the first device region AR1and the second fin active region F2on the second device region AR2.

The sacrificial semiconductor layers104may include a semiconductor material having a different etch selectivity than a semiconductor material of the nanosheet semiconductor layers NS. In an implementation, the nanosheet semiconductor layers NS may include an Si layer, and the sacrificial semiconductor layers104may include an SiGe layer. In an implementation, the sacrificial semiconductor layers104may have a constant Ge content. The SiGe layer of the sacrificial semiconductor layers104may have a constant Ge content of about 5 at % to about 60 at %, e.g., about 10 at % to about 40 at %. The Ge content of the SiGe layer of the sacrificial semiconductor layers104may be variously changed as desired.

Referring toFIGS.12A through12C, a plurality of dummy gate structures DGS and outer insulating spacers118respectively covering opposite side walls of each of the dummy gate structures DGS may be formed on the stack structure of the sacrificial semiconductor layers104and the nanosheet semiconductor layers NS. The dummy gate structures DGS may continuously extend lengthwise in the second horizontal direction (the Y direction) at positions corresponding to the gate lines160illustrated inFIG.1.

Each of the dummy gate structures DGS may have a structure, in which an oxide film D112, a dummy gate layer D114, and a capping layer D116are sequentially stacked. In an implementation, the dummy gate layer D114may include a polysilicon film, and the capping layer D116may include a silicon nitride film.

Thereafter, a first mask pattern MP1having a first opening MH1exposing the first device region AR1may be formed on the resultant structure including a dummy gate structure DGS and the outer insulating spacers118. A plurality of nanosheet stacks NSS may be formed from the nanosheet semiconductor layers NS on the first device region AR1by partially removing each of the sacrificial semiconductor layers104and the nanosheet semiconductor layers NS using the dummy gate structure DGS and the outer insulating spacers118as etch masks on the first device region AR1in the state where the second device region AR2is covered with the first mask pattern MP1. Each of the nanosheet stacks NSS may include the first, second, and third nanosheets N1, N2, and N3. A plurality of first recesses R1may be formed in an upper portion of the first fin active region F1by etching some portions of the first fin active region F1, which are exposed among the nanosheet stacks NSS on the first device region AR1. To form the first recesses R1, the first fin active region F1may be etched using dry etching, wet etching, or a combination thereof.

Thereafter, a plurality of indents104D may be formed among the first, second, and third nanosheets N1, N2, and N3and the first fin active region F1by selectively removing portions of the sacrificial semiconductor layers104exposed by the first recesses R1at opposite sides of each nanosheet stack NSS, and a plurality of inner insulating spacers120filling the indents104D may be formed. The indents104D may be formed by selectively etching the portions of the sacrificial semiconductor layers104using a difference in etch selectivity between the sacrificial semiconductor layers104and the first, second, and third nanosheets N1, N2, and N3. The inner insulating spacers120may be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation, or a combination thereof.

Thereafter, a plurality of first source/drain regions SD1may be formed on the first fin active region F1at opposite sides of each of the nanosheet stacks NSS. The first source/drain regions SD1may be formed by epitaxially growing a semiconductor material from a surface of the first fin active region F1exposed at the bottoms of the first recesses R1and the side walls of the first, second, and third nanosheets N1, N2, and N3. In an implementation, the first source/drain regions SD1may be formed by performing low-pressure CVD (LPCVD), selective epitaxial growth (SEG), or cyclic deposition and etching (CDE) using source materials including an elemental semiconductor precursor. In an implementation, the first source/drain regions SD1may include an Si layer doped with an n-type dopant. Silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), or the like may be used as an Si source to form the first source/drain regions SD1. The n-type dopant may include P, As, or Sb.

Referring toFIGS.13A through13C, after the first mask pattern MP1is removed from the resultant structure ofFIGS.12A through12C, a second mask pattern MP2having a second opening MH2exposing the second device region AR2may be formed. A plurality of nanosheet stacks NSS may be formed from the nanosheet semiconductor layers NS on the second device region AR2by partially removing each of the sacrificial semiconductor layers104and the nanosheet semiconductor layers NS using the dummy gate structure DGS and the outer insulating spacers118as etch masks in the second device region AR2in the state where the first device region AR1is covered with the second mask pattern MP2. Each of the nanosheet stacks NSS may include the first, second, and third nanosheets N1, N2, and N3.

A plurality of second recesses R2may be formed in an upper portion of the second fin active region F2by etching the second fin active region F2exposed among the nanosheet stacks NSS on the second device region AR2. A method of forming the second recesses R2is the same as the method of forming the first recesses R1, which has been described with reference toFIGS.12A through12C.

Thereafter, a plurality of second source/drain regions SD2may be formed on the second fin active region F2at opposite sides of each of the nanosheet stacks NSS. Similarly to the description of the first source/drain regions SD1, which has been given with reference toFIGS.12A through12C, the second source/drain regions SD2may be formed by epitaxially growing a semiconductor material from a surface of the second fin active region F2exposed at the bottoms of the second recesses R2and the side walls of the first, second, and third nanosheets N1, N2, and N3. In an implementation, the second source/drain regions SD2may include an SiGe layer doped with a p-type dopant. An Si source and a Ge source may be used to form the second source/drain regions SD2. Silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), or the like may be used as the Si source. Germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H10), dichlorogermane (Ge2H2Cl2), or the like may be used as the Ge source. The p-type dopant may include B or Ga.

Referring toFIGS.14A through14C, after the second mask pattern MP2is removed from the resultant structure ofFIGS.13A through13C, the insulating liner142, which covers the surface of each of the first and second source/drain regions SD1and SD2and the surface of each of the outer insulating spacers118, may be formed, and the intergate insulating film144may be formed on the insulating liner142. Thereafter, the top surface of the dummy gate layer D114may be exposed by removing the capping layer D116and planarizing the outer insulating spacers118, the insulating liner142, and the intergate insulating film144.

Thereafter, a third mask pattern MP3, which covers the dummy gate layer D114, the insulating liner142, and the intergate insulating film144, may be formed. The third mask pattern MP3may have a plurality of third openings MH3, each of which exposes a portion of the dummy gate layer D114and a portion of each of the outer insulating spacers118, the insulating liner142, and the intergate insulating film144, which are adjacent to exposed portion of the dummy gate layer D114. The respective positions of the third openings MH3of the third mask pattern MP3may respectively correspond to the respective positions of the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C inFIG.1.

The isolation film112may be exposed by the third openings MH3by selectively performing anisotropic etching on a portion of the dummy gate layer D114exposed by the third openings MH3and etching the oxide film D112, which is exposed by the third openings MH3as a result of etching the portion of the dummy gate layer D114. As a result, a plurality of gate cut spaces CTS respectively communicating with the third openings MH3may be formed in the dummy gate layer D114.

Referring toFIGS.15A through15C, after the third mask pattern MP3is removed from the resultant structure ofFIGS.14A through14C, a plurality of gate cut insulating films150respectively filling the gate cut spaces CTS may be formed, and an upper portion of a gate cut insulating film150on the boundary between the first device region AR1and the second device region AR2may be substituted by a sacrificial film SCT. Each of the gate cut insulating films150and the sacrificial film SCT may include a material, which has an etch selectivity with respect to a material of the dummy gate layer D114. In an implementation, when the dummy gate layer D114includes a polysilicon film, the gate cut insulating films150may include silicon nitride and the sacrificial film SCT may include silicon oxide.

Thereafter, a plurality of gate spaces GS may be formed on the nanosheet stacks NSS by removing the dummy gate layer D114and the oxide film D112below the dummy gate layer D114. The lengths of the gate spaces GS in the second horizontal direction (the Y direction) may be limited by the gate cut insulating films150and the sacrificial film SCT.

Referring toFIGS.16A through16C, the sacrificial semiconductor layers104remaining on each of the first and second fin active regions F1and F2may be removed from the resultant structure ofFIGS.15A through15Cthrough a gate space GS above a nanosheet stack NSS such that the gate space GS may extend to spaces among the first, second, and third nanosheets N1, N2, and N3and the fin top FT.

In an implementation, to selectively remove the sacrificial semiconductor layers104, a difference in etch selectivity between the sacrificial semiconductor layers104and the first, second, and third nanosheets N1, N2, and N3may be used. To selectively remove the sacrificial semiconductor layers104, a liquid or gas etchant may be used. In an implementation, to selectively remove the sacrificial semiconductor layers104, a CH3COOH etchant, e.g., an etchant including a mixture of CH3COOH, HNO3, and HF or a mixture of CH3COOH, H2O2, and HF, may be used.

Referring toFIGS.17A through17C, the gate dielectric film152, which covers the exposed surfaces of the first, second, and third nanosheets N1, N2, and N3and the first and second fin active regions F1and F2in the resultant structure ofFIGS.16A through16C, may be formed. The gate dielectric film152may conformally cover the surfaces of the outer insulating spacers118, the gate cut insulating films150, and the sacrificial film SCT, which are exposed by the gate spaces GS.

Referring toFIG.18, the first work function metal film ML1, which covers the exposed surfaces in the resultant structure ofFIGS.17A through17C, may be formed. The first work function metal film ML1may fill the spaces among the first, second, and third nanosheets N1, N2, and N3and the respective fin tops FT of the first and second fin active regions F1and F2in the first and second device regions AR1and AR2.

Referring toFIG.19, a fourth mask pattern MP4, which covers the second device region AR2and exposes the first device region AR1in the resultant structure ofFIG.18, may be formed, and the gate dielectric film152on the first device region AR1may be exposed by selectively removing the first work function metal film ML1exposed in the first device region AR1around the fourth mask pattern MP4.

In an implementation, to selectively remove the first work function metal film ML1exposed on the first device region AR1, wet etching may be performed. Because the stack structure of a gate cut insulating film150and the sacrificial film SCT is on the isolation film112between the first device region AR1and the second device region AR2, wet etching may be performed for a sufficient time to completely remove even portions of the first work function metal film ML1, which fill the spaces among the first, second, and third nanosheets N1, N2, and N3and the fin top FT of the first fin active region F1, during a process of removing the first work function metal film ML1from the first device region AR1. During the wet etching, the first work function metal film ML1and structures around the first work function metal film ML1on the second device region AR2may be protected by the fourth mask pattern MP4and the stack structure of the gate cut insulating film150and the sacrificial film SCT on the isolation film112between the first device region AR1and the second device region AR2against an etching atmosphere.

After the first work function metal film ML1is removed from the first device region AR1, the gate space GS among the first, second, and third nanosheets N1, N2, and N3and the fin top FT may be empty on the first device region AR1.

Referring toFIG.20, after the fourth mask pattern MP4is removed from the resultant structure ofFIG.19, the second work function metal film ML2, which covers surfaces exposed by the gate spaces GS in the first and second device regions AR1and AR2, may be formed. The second work function metal film ML2in a gate space GS on the first device region AR1may be in contact with the gate dielectric film152. The second work function metal film ML2in a gate space GS on the second device region AR2may be in contact with the first work function metal film ML1.

Referring toFIG.21, a fifth mask pattern MP5covering the resultant structure ofFIG.20may be formed. The fifth mask pattern MP5may have an opening MH5at a position corresponding to the sacrificial film SCT. In an implementation, the fifth mask pattern MP5may include a carbon-containing film including a spin-on hardmask (SOH) material. The carbon-containing film may include an organic compound having a relatively high carbon content of about 85 wt % to about 99 wt % based on the total weight thereof. The organic compound may include a hydrocarbon compound including an aromatic ring or a derivative of the hydrocarbon compound.

The top surface of the sacrificial film SCT may be exposed by partially removing each of the second work function metal film ML2, the first work function metal film ML1, and the gate dielectric film152, which are exposed by the opening MH5.

Referring toFIG.22, the top surface of the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2may be exposed by the opening MH5by removing the sacrificial film SCT from the resultant structure ofFIG.21. Wet etching, dry etching, or a combination thereof may be used to remove the sacrificial film SCT.

Referring toFIG.23, the gate dielectric film152, the second work function metal film ML2, and first work function metal film ML1, which are around the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2, may be lowered by partially removing the gate dielectric film152, the second work function metal film ML2, and first work function metal film ML1, which are exposed by the opening MH5, from the resultant structure ofFIG.22. Wet etching, dry etching, or a combination thereof may be used to partially remove the gate dielectric film152, the second work function metal film ML2, and first work function metal film ML1.

Referring toFIG.24, after the fifth mask pattern MP5is removed from the resultant structure ofFIG.23, the gap-fill metal film ML3filling the remaining portions of the gate spaces GS on the first and second device regions AR1and AR2may be formed and then planarized such that the topmost surfaces of a plurality of gate cut insulating films150are exposed. As a result, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3may fill only the gate spaces GS (seeFIG.17C) and a space above the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2.

Referring toFIG.25, the first work function metal film ML1, the second work function metal film ML2, the gap-fill metal film ML3, and the gate cut insulating films150may be lowered by partially removing the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3, which fill the gate spaces GS (seeFIG.17C), and the gate cut insulating films150from the top surface of the resultant structure ofFIG.24. At this time, the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2may be protected by the gap-fill metal film ML3and thus not be changed in height. As a result, the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern150C may be obtained from the gate cut insulating films150.

Thereafter, a capping insulating pattern164may be formed on the first work function metal film ML1, the second work function metal film ML2, the gap-fill metal film ML3, and the first and second gate cut insulating patterns150A and150B to fill the remaining region of the gate spaces GS (seeFIG.17C).

In an implementation, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3in the resultant structure ofFIG.25may form the gate lines160of the integrated circuit device100illustrated inFIGS.2A through2C. In an implementation, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3in the resultant structure ofFIG.25may form the gate lines160A of the integrated circuit device100A illustrated inFIG.3.

Thereafter, as shown inFIGS.2A and2B, the source/drain contacts174, which pass through the intergate insulating film144and the insulating liner142and are connected to the first source/drain regions SD1on the first device region AR1and the second source/drain regions SD2on the second device region AR2, and the metal silicide film172between the first and second source/drain regions SD1and SD2and the source/drain contacts174, may be formed. As shown inFIGS.2A through2C, the insulating structure190, which covers the top surface of the resultant structure including the metal silicide film172and the source/drain contacts174, may be formed, and the source/drain via contacts192, each of which passes through the insulating structure190and is connected to a source/drain contact174, may be formed. In an implementation, a process of forming a plurality of gate contacts, each of which passes through the capping insulating pattern164and is connected to a gate line160, and a plurality of gate via contacts, each of which passes through the insulating structure190and is connected to a gate contact, may be further performed.

It is understood that the integrated circuit devices100B,200,300,400,500, and500A described with reference toFIGS.4through10and other various integrated circuit devices having similar structures thereto may be manufactured by making various modifications and changes in the descriptions given with reference toFIGS.11A through25.

In an implementation, to manufacture the integrated circuit device100B ofFIG.4, the inter-region insulating pattern150C obtained from the gate cut insulating film150in the boundary between the first device region AR1and the second device region AR2may be formed to have the non-planar top surface TB by controlling an etching atmosphere in each of the process of removing the sacrificial film SCT, as described above with reference toFIG.22, and the process of partially removing the gate dielectric film152, the second work function metal film ML2, and first work function metal film ML1, which are exposed by the opening MH5, as described above with reference toFIG.23.

To manufacture the integrated circuit device200ofFIG.5or the integrated circuit device300ofFIG.6, the position of a third opening MH3corresponding to the boundary between the first device region AR1and the second device region AR2among the third openings MH3of the third mask pattern MP3may be changed when the third mask pattern MP3is formed as described above with reference toFIGS.14A through14C.

In an implementation, when the third mask pattern MP3is formed as described above with reference toFIGS.14A through14C, the third mask pattern MP3may be formed such that the position of the third opening MH3corresponding to the boundary between the first device region AR1and the second device region AR2is closer to the first fin active region F1on the first device region AR1than to the second fin active region F2on the second device region AR2, and then the subsequent processes described with reference toFIGS.14A through25may be performed so that the integrated circuit device200ofFIG.5may be manufactured.

In an implementation, when the third mask pattern MP3is formed as described above with reference toFIGS.14A through14C, the third mask pattern MP3may be formed such that the position of the third opening MH3corresponding to the boundary between the first device region AR1and the second device region AR2is closer to the second fin active region F2on the second device region AR2than to the first fin active region F1on the first device region AR1, and then the subsequent processes described with reference toFIGS.14A through25may be performed so that the integrated circuit device300ofFIG.6may be manufactured.

To manufacture the integrated circuit device400ofFIG.7, the length of the sacrificial film SCT in the vertical direction (the Z direction) may be made greater than that shown inFIG.15Cin the process of substituting the upper portion of the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2with the sacrificial film SCT, as described above with reference toFIGS.15A through15C, such that the level of the contact surface between the sacrificial film SCT and the gate cut insulating film150therebelow is lower than that shown inFIG.15C. Thereafter, the integrated circuit device400ofFIG.7may be manufactured by performing the subsequent processes described with reference toFIGS.16A through25.

FIG.26is a cross-sectional view of a stage in a method of manufacturing an integrated circuit device, according to some embodiments. Another example method of manufacturing the integrated circuit devices100and100B illustrated inFIGS.1through3will be described with reference toFIG.26.

Referring toFIG.26, after the top surface of the sacrificial film SCT is exposed by the opening MH5of the fifth mask pattern MP5by performing the processes described with reference toFIGS.11A through21, the sacrificial film SCT may be removed through the opening MH5using the method described with reference toFIG.22.

Thereafter, a side wall of each of the second work function metal film ML2and the first work function metal film ML1may be exposed by the opening MH5by partially removing the gate dielectric film152, which is exposed by the opening MH5, using a method similar to that described with reference toFIG.23. In an implementation, differently from the description given with reference toFIG.23, the process of partially removing the second work function metal film ML2and the first work function metal film ML1through the opening MH5may be omitted.

Thereafter, the topmost surfaces of a plurality of gate cut insulating films150may be exposed by removing the fifth mask pattern MP5, forming the gap-fill metal film ML3filling the remaining portions of the gate spaces GS on the first and second device regions AR1and AR2, and planarizing the resultant structure, using a method similar to that described with reference toFIG.24. As a result, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3may remain in only the gate spaces GS (seeFIG.17C) and the space above the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2. Thereafter, the integrated circuit device100illustrated inFIGS.2A through2Cor the integrated circuit device100A illustrated inFIG.3may be manufactured by performing the processes described with reference toFIG.25.

FIGS.27A through27Fare cross-sectional views of stages in a method of manufacturing an integrated circuit device, according to some embodiments.FIGS.27A through27Fillustrate partial configurations of a portion corresponding to the cross-section taken along the line Y1-Y1′ inFIG.8. Example methods of manufacturing the integrated circuit devices500and500B illustrated inFIGS.8through10will be described with reference toFIGS.27A through27Fbelow. InFIGS.1through10andFIGS.27A through27F, like reference numerals denote like elements, and detailed descriptions thereof may be omitted.

Referring toFIG.27A, the processes described with reference toFIGS.11A through15Cmay be performed. In an implementation, the process of substituting the upper portion of the gate cut insulating film150at the boundary between the first device region AR1and the second device region AR2with the sacrificial film SCT may be omitted from the processes described with reference toFIGS.15A through15C. As a result, a plurality of gate cut insulating films150above the substrate102may have equal or similar heights in the vertical direction (the Z direction) to one another.

Referring toFIG.27B, a gate space GS may be extended to spaces among the first, second, and third nanosheets N1, N2, and N3and the fin top FT by removing the sacrificial semiconductor layers104remaining on each of the first and second fin active regions F1and F2from the resultant structure ofFIG.27A, and the gate dielectric film152, which covers the exposed surfaces of the first, second, and third nanosheets N1, N2, and N3and the first and second fin active regions F1and F2, may be formed, using a method similar to that described with reference toFIGS.16A through17C.

Referring toFIG.27C, the first work function metal film ML1, which covers the exposed surfaces on the first and second device regions AR1and AR1of the resultant structure ofFIG.27B, may be formed, and the gate dielectric film152on the first device region AR1may be exposed by selectively removing the first work function metal film ML1from only the first device region AR1, using a method similar to that described with reference toFIGS.18and19.

To selectively remove the first work function metal film ML1exposed on the first device region AR1, wet etching may be performed. In an implementation, because a gate cut insulating film150is on the isolation film112between the first device region AR1and the second device region AR2, wet etching may be performed for a sufficient time to completely remove even portions of the first work function metal film ML1, which fill the spaces among the first, second, and third nanosheets N1, N2, and N3and the fin top FT of the first fin active region F1, during the process of removing the first work function metal film ML1from the first device region AR1. During the wet etching, the first work function metal film ML1and structures around the first work function metal film ML1on the second device region AR2may be protected by the fourth mask pattern MP4and the gate cut insulating film150on the isolation film112between the first device region AR1and the second device region AR2against an etching atmosphere.

Referring toFIG.27D, the second work function metal film ML2, which covers surfaces exposed by the gate spaces GS in the resultant structure ofFIG.27C, may be formed using a method similar to that described with reference toFIG.20.

Referring toFIG.27E, the topmost surfaces of a plurality of gate cut insulating films150may be exposed by forming the gap-fill metal film ML3filling the remaining portions of the gate spaces GS on the first and second device regions AR1and AR2of the resultant structure ofFIG.27Dand planarizing the resultant structure, using a method similar to that described with reference toFIG.24.

Referring toFIG.27F, the first work function metal film ML1, the second work function metal film ML2, the gap-fill metal film ML3, and the gate cut insulating films150may be lowered by partially removing the first work function metal film ML1, the second work function metal film ML2, the gap-fill metal film ML3, and the gate cut insulating films150from the top surface of the resultant structure ofFIG.27E, using a method similar to that described with reference toFIG.25. As a result, the first and second gate cut insulating patterns150A and150B and the inter-region insulating pattern550C may be obtained from the gate cut insulating films150. Thereafter, the capping insulating pattern164, which covers the first work function metal film ML1, the second work function metal film ML2, the gap-fill metal film ML3, the first and second gate cut insulating patterns150A and150B, and the inter-region insulating pattern550C, may be formed.

In an implementation, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3in the resultant structure ofFIG.27Fmay form the gate lines560of the integrated circuit device500illustrated inFIGS.8and9. In an implementation, the first work function metal film ML1, the second work function metal film ML2, and the gap-fill metal film ML3in the resultant structure ofFIG.27Fmay form the gate lines560A of the integrated circuit device500A illustrated inFIG.10.

Thereafter, the integrated circuit device500illustrated inFIGS.8and9or the integrated circuit device500A illustrated inFIG.10may be manufactured by forming the insulating structure190on the capping insulating pattern164, forming a pair of gate contacts582to pass through the insulating structure190and the capping insulating pattern164and to be respectively connected to a pair of gate lines560(seeFIG.9) or560A (seeFIG.10) respectively on the first and second device regions AR1and AR2, and forming the conductive line586on the insulating structure190to be connected to the gate contacts582, as shown inFIGS.9and10.

By way of summation and review, with the increase in the integration density of semiconductor devices and the decrease in the size thereof, a structure for increasing the performance and reliability of an NSFET may be considered.

One or more embodiments may provide an integrated circuit device including a field-effect transistor.

One or more embodiments may provide a method in which a wet etch time may be increased as much as it is desired during the process of opening either the NMOS region or the PMOS region and removing a metal.

One or more embodiments may provide a method in which a wet etch time may be increased as much as it is desired during the process of opening either the NMOS region or the PMOS region and removing a metal.

One or more embodiments may provide a device in which a side wall of the isolation structure, which is formed at the boundary between the NMOS region and the PMOS region, may be linearly or planarly extended in a vertical direction without a stepped portion. In addition, to enhance the performance of the NMOS and PMOS transistors, the isolation structure may be closer to one region between the NMOS region and the PMOS region. The height of the isolation structure may be lower than the height of the topmost surface of a nanosheet.

One or more embodiments may provide an integrated circuit device for removing the probability of occurrence of defective processes during the manufacture of the integrated circuit device and providing the stable performance and enhanced reliability of a nanosheet field-effect transistor.