Electronic device and method of manufacturing same

An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device. The first interconnection pattern and the second interconnection pattern are connected through a through electrode provided through the adhesive layer and the second sealing resin.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based upon and claims the benefit of priority of Japanese Patent Application No. 2009-091956, filed on Apr. 6, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to electronic devices and methods of manufacturing the same. In particular, the present invention relates to an electronic device including a first semiconductor device and a second semiconductor device electrically connected to the first semiconductor device, where the first semiconductor device includes a first electronic component and a first multilayer interconnection structure electrically connected to the first electronic component and the second semiconductor device includes a second electronic component and a second multilayer interconnection structure electrically connected to the second electronic component.

2. Description of the Related Art

FIG. 1is a cross-sectional view of a conventional electronic device200.

Referring toFIG. 1, the conventional electronic device200includes a first semiconductor device201, a second semiconductor device202, and internal connection terminals203. The first semiconductor device201includes a wiring board211(a first multilayer interconnection structure), a first electronic component212, underfill resin213, and external connection terminals214.

The wiring board211is a plate-shaped multilayer interconnection structure. The wiring board211includes stacked insulating layers216and217; interconnection patterns219,228, and229; pads221; solder resist layers222and226; and external connection pads223and224. The insulating layer216is provided on an upper surface217A of the insulating layer217.

The interconnection patterns219and the pads221are provided on an upper surface216A of the insulating layer216. The interconnection patterns219include pad parts232and233, which are not covered with the solder resist layer222and are exposed. The pads221are not covered with the solder resist layer222and are exposed.

The solder resist layer222is provided on the upper surface216A of the insulating layer216. The external connection pads223and224are provided on a lower surface217B of the insulating layer217. The lower surfaces of the external connection pads223and224are not covered with the solder resist layer226and are exposed.

The solder resist layer226is provided on the lower surface217B of the insulating layer217. The interconnection patterns228and229are provided inside the stacked insulating layers216and217. The interconnection patterns228are connected to the corresponding pad parts233and external connection pads223. The interconnection patterns229are connected to the corresponding pads221and external connection pads224.

The first electronic component212is placed between the first semiconductor device201and the second semiconductor device202. The first electronic component212includes electrode pads236. The electrode pads236are electrically connected to the corresponding pad parts232through bumps237(for example, solder bumps).

The underfill resin213is provided to fill in the gap between the first electronic component212and the wiring board211. The external connection terminals214are provided on the lower surfaces of the corresponding external connection pads223and224.

The second semiconductor device202is provided over the first semiconductor device201. The second semiconductor device202includes a wiring board241(a second multilayer interconnection structure), a second electronic component243, and molded resin246. The wiring board241has a plate shape, and includes pads251,252and254. The pads251face the pad parts233, and are electrically connected to the pad parts233through the corresponding internal connection terminals203. The pads252face the pads221, and are electrically connected to the pads221through the corresponding internal connection terminals203. The pads254are electrically connected to the pads251or the pads252.

The second electronic component243is bonded onto the wiring board241, and is electrically connected to the pads254through metal wires244. The molded resin246is provided on the wiring board241. The molded resin246seals the metal wires244and the second electronic component243.

The diameter (height) of the internal connection terminals203is determined so that the first electronic component212and the second semiconductor device202are out of contact with each other. The internal connection terminals203may have a height of, for example, 200 μm. (See, for example, Japanese Laid-Open Patent Application No. 6-13541.)

SUMMARY OF THE INVENTION

According to one aspect of the present invention, an electronic device includes a first semiconductor device including a first electronic component having a first surface and a second surface facing away from each other, the first surface having a first electrode pad provided thereon; a first sealing resin having a first surface and a second surface facing away from each other, the first sealing resin sealing side surfaces of the first electronic component so that the first surface and the second surface of the first electronic component are exposed at the first surface and the second surface, respectively, of the first sealing resin; and a first multilayer interconnection structure including a plurality of insulating layers and a first interconnection pattern, the insulating layers being stacked to cover the first surface of the first electronic component and the first surface of the first sealing resin, the first interconnection pattern being directly connected to the first electrode pad; and a second semiconductor device including a second electronic component having a first surface and a second surface facing away from each other, the first surface having a second electrode pad provided thereon; a second sealing resin having a first surface and a second surface facing away from each other, the second sealing resin sealing side surfaces of the second electronic component so that the first surface and the second surface of the second electronic component are exposed at the first surface and the second surface, respectively, of the second sealing resin; and a second multilayer interconnection structure including a plurality of insulating layers and a second interconnection pattern, the insulating layers being stacked to cover the first surface of the second electronic component and the first surface of the second sealing resin, the second interconnection pattern being directly connected to the second electrode pad, wherein the first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device, and the first interconnection pattern and the second interconnection pattern are connected through a through electrode provided through the adhesive layer and the second sealing resin.

According to one aspect of the present invention, a method of manufacturing an electronic device includes: forming a first semiconductor device including a first electronic component having a first surface and a second surface facing away from each other, the first surface having a first electrode pad provided thereon; a first sealing resin having a first surface and a second surface facing away from each other, the first sealing resin being provided to seal side surfaces of the first electronic component so that the first surface and the second surface of the first electronic component are exposed at the first surface and the second surface, respectively, of the first sealing resin; and a first multilayer interconnection structure including a plurality of insulating layers and a first interconnection pattern, the insulating layers being stacked to cover the first surface of the first electronic component and the first surface of the first sealing resin, the first interconnection pattern being directly connected to the first electrode pad; and forming a second semiconductor device, which includes preparing a second electronic component having a first surface and a second surface facing away from each other, the first surface having a second electrode pad provided thereon, and forming a second sealing resin having a first surface and a second surface facing away from each other, the second sealing resin sealing side surfaces of the second electronic component so that the first surface and the second surface of the second electronic component are exposed at the first surface and the second surface, respectively, of the second sealing resin; stacking the second sealing resin on the first multilayer interconnection structure with an adhesive layer being interposed between the second surface of the second sealing resin and the first multilayer interconnection structure; forming a through electrode through the second sealing resin and the adhesive layer, the through electrode being connected to the first interconnection pattern; and forming a second multilayer interconnection structure including a plurality of insulating layers and a second interconnection pattern, the insulating layers being stacked to cover the first surface of the second electronic component and the first surface of the second sealing resin, the second interconnection pattern being directly connected to the second electrode pad.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to the above-described conventional electronic device200ofFIG. 1, the first electronic component212provided on the upper surface side of the wiring board211and the wiring board211are electrically connected through the bumps237. Accordingly, there is a problem in that the electronic device200as well as the first semiconductor device201is large in size in the directions of its thickness.

Further, according to the conventional electronic device200, the height (diameter) of the internal connection terminals203that electrically connect the first semiconductor device201and the second semiconductor device202needs to be larger than the sum of the height of the first electronic component212and the height of the bumps237. Therefore, there is a problem in that the electronic device200is large in size in the directions of its thickness.

Furthermore, according to the conventional electronic device200, there is also the problem of a decrease in the reliability of the electrical connection between the first semiconductor device201and the second semiconductor device if solder balls are used as the internal connection terminals203.

The problem of increases in the sizes of the first semiconductor device201and the electronic device200in their thickness directions also occurs in the case of connecting the first electronic component212and the wiring board211by wire bonding.

According to one aspect of the present invention, there are provided an electronic device that is reduced in size in its thickness directions with increased reliability of the electrical connection between a first semiconductor device and a second semiconductor device and a method of manufacturing such an electronic device.

A description is given, with reference to the accompanying drawings, of embodiments of the present invention.

[a] First Embodiment

FIGS. 2A and 2Bare cross-sectional views of an electronic device10according to a first embodiment of the present invention.

Referring toFIGS. 2A and 2B, the electronic device10according to the first embodiment includes a first semiconductor device11and a second semiconductor device12.

Referring toFIG. 2A, the first semiconductor device11includes first electronic components15and16; sealing resin18; through electrodes21,22, and23; and a first multilayer interconnection structure25.

The first electronic component15has a thin plate shape and may be, for example, 200 μm to 300 μm in thickness. The first electronic component15includes a first electrode pad31having a connection surface31A; a first electrode pad32having a connection surface32A; an electrode pad formation surface15A on which the first electrode pads31and32are formed; and a rear surface15B on the side opposite to (facing away from) the electrode pad formation surface15A.

The first electronic component16has a thin plate shape and may be, for example, 200 μm to 300 μm in thickness. The first electronic component16includes a first electrode pad33having a connection surface33A; a first electrode pad34having a connection surface34A; an electrode pad formation surface16A on which the first electrode pads33and34are formed; and a rear surface16B on the side opposite to (facing away from) the electrode pad formation surface16A.

The first electronic components15and16may be, for example, semiconductor chips. By way of example, the first electronic components15and16may be semiconductor chips for CPUs (Central Processing Units); one of the first electronic components15and16may be a semiconductor chip for a CPU and the other one of the first electronic components15and16may be a semiconductor chip for a memory; or one of the first electronic components15and16may be a semiconductor chip for a CPU and the other one of the first electronic components15and16may be a semiconductor chip for a GPU (Graphics Processing Unit).

The sealing resin18is provided around the first electronic components15and16to seal the side surfaces of the first electronic components15and16. The sealing resin18is substantially equal in thickness to the first electronic components15and16. The sealing resin18may be, for example, 200 μm to 300 μm in thickness.

The sealing resin18has a surface18A and a multilayer interconnection structure formation surface18B on the side opposite to (facing away from) the surface18A. The rear surfaces15B and16B of the first electronic components15and16, respectively, are exposed at the surface18A of the sealing resin18. The surface18A of the sealing resin18is substantially level with the rear surfaces15B and16B of the first electronic components15and16. As a result, the surface18A of the sealing resin18and the rear surfaces15B and16B of the first electronic components15and16are in substantially the same plane (that is, substantially form a single surface).

By thus configuring the sealing resin18, sealing the side surfaces of the first electronic components15and16, so that the surface18A is substantially level with the rear surfaces15B and16B of the first electronic components15and16, it is possible to seal the side surfaces of the first electronic components15and16without an increase in the size of the first semiconductor device11in its thickness directions (vertical directions inFIG. 2A).

The electrode pad formation surfaces15A and16A of the first electronic components15and16and the first electrode pads31through34are exposed at the multilayer interconnection structure formation surface18B of the sealing resin18. The multilayer interconnection structure formation surface18B is substantially level with the electrode pad formation surfaces15A and16A. The first multilayer interconnection structure25is formed on the multilayer interconnection structure formation surface18B.

Through holes36,37, and38are formed in the sealing resin18. The through holes36through38are formed through part of the sealing resin18around the first electronic components15and16. The through holes36through38may be, for example, 200 μm in diameter.

The sealing resin18may be, for example, molded resin, whose material may be, for example, epoxy resin.

The through electrode21is provided in the through hole36. The through electrode21has an end surface21A in the same plane as the rear surfaces15B and16B of the first electronic components15and16and the surface18A of the sealing resin18. The end surface21A of the through electrode21serves as, for example, a connection surface for mounting another electronic component (not graphically illustrated).

An end part of the through electrode21on which another end surface21B is formed projects from the multilayer interconnection structure formation surface18B. The end surface21B of the through electrode21is in the same plane as the connection surfaces31A,32A,33A, and34A of the first electrode pads31,32,33, and34, respectively.

The through electrode21having the above-described configuration may be formed by, for example, plating. Examples of the material of the through electrode21include Cu.

The through electrode22is provided in the through hole37. The through electrode22has an end surface22A in the same plane as the rear surfaces15B and16B of the first electronic components15and16and the surface18A of the sealing resin18. The end surface22A of the through electrode22serves as, for example, a connection surface for mounting another electronic component (not graphically illustrated).

An end part of the through electrode22on which another end surface22B is formed projects from the multilayer interconnection structure formation surface18B. The end surface22B of the through electrode22is in the same plane as the connection surfaces31A,32A,33A, and34A of the first electrode pads31,32,33, and34, respectively.

The through electrodes22having the above-described configuration may be formed by, for example, plating. Examples of the material of the through electrode22include Cu.

The through electrodes23are provided in the corresponding through holes38. The through electrodes23have respective end surfaces23A in the same plane as the rear surfaces15B and16B of the first electronic components15and16and the surface18A of the sealing resin18. The end surfaces22A of the through electrodes23serve as, for example, connection surfaces for mounting another electronic component (not graphically illustrated).

End parts of the through electrodes23on which respective other end surfaces23B are formed project from the multilayer interconnection structure formation surface18B. The end surfaces23B of the through electrodes23are in the same plane as the connection surfaces31A,32A,33A, and34A of the first electrode pads31,32,33, and34, respectively.

The through electrodes23having the above-described configuration may be formed by, for example, plating. Examples of the material of the through electrodes23include Cu.

As described above, the end surfaces21A,22A, and23A of the through electrodes21,22, and23, respectively, are placed in the same plane as the rear surfaces15B and16B of the first electronic components15and16and the surface18A of the sealing resin18. As a result, the first semiconductor device11has a flat surface on the side opposite to the surface facing toward the second semiconductor device12.

The first multilayer interconnection structure25includes a layered body41, external connection pads43,44,45,46, and47serving as first pads, and interconnection patterns51,52,53, and54serving as first interconnection patterns.

The layered body41includes a stack of multiple insulating layers56,57, and58. The insulating layer56is provided on the electrode pad formation surfaces15A and16A of the first electronic components15and16, the multilayer interconnection structure formation surface18B of the sealing resin18, the parts of the through electrodes21through23projecting from the multilayer interconnection structure formation surface18B, and the first electrode pads31through34. The insulating layer56may be, for example, an insulating resin layer (such as an epoxy resin layer). The insulating layer56may be, for example, 5 μm to 30 μm in thickness.

The insulating layer56has a surface56A in contact with the sealing resin18and a surface56B facing away from (on the side opposite to) the surface56A. The surface56A corresponds to a first surface of the layered body41. The insulating layer57is provided on the surface56B of the insulating layer56. The insulating layer57may be, for example, an insulating resin layer (such as an epoxy resin layer). The insulating layer57may be, for example, 5 μm to 30 μm in thickness.

The insulating layer57has a surface57A in contact with the insulating layer56and a surface57B facing away from (on the side opposite to) the surface57A. The insulating layer58is provided on the surface57B of the insulating layer57. The insulating layer58may be, for example, an insulating resin layer (such as an epoxy resin layer). The insulating layer58may be, for example, 5 μm to 30 μm in thickness.

The insulating layer58has a surface58A in contact with the insulating layer57and a surface58B facing away from (on the side opposite to) the surface58A. The surface58B corresponds to a second surface of the layered body41. The external connection pads43through47are provided on the surface58B of the insulating layer58. The external connection pads43through47have respective connection surfaces43A,44A,45A,46A, and47A. The connection surfaces43A through47A are electrically connected to the second semiconductor device12.

The interconnection patterns51through54are provided inside the layered body41. The interconnection pattern51includes vias61,62,64, and66and interconnects63and65. The via61is provided through part of the insulating layer56facing the through electrode21. The via61has a connection surface61A. The connection surface61A is connected to the end surface21B of the through electrode21. As a result, the interconnection pattern51is electrically connected to the through electrode21.

The via62is provided through part of the insulating layer56facing the connection surface31A of the first electrode pad31. The via62is directly connected to (or in direct contact with) the connection surface31A of the first electrode pad31. As a result, the interconnection pattern51is electrically connected to the first electronic component15.

The interconnect63is provided on the surface56B of the insulating layer56. The interconnect63forms a unitary structure with the end parts of the vias61and62positioned on the surface56B side in the insulating layer56. Thereby, the interconnect63electrically connects the first electronic component15and the through electrode21.

The via64is provided through part of the insulating layer57facing the interconnect63. As a result, the via64is connected to the interconnect63.

The interconnect65is provided on the surface57B of the insulating layer57. The interconnect65forms a unitary structure with the end part of the via64positioned on the surface57B side in the insulating layer57. As a result, the interconnect65is electrically connected to the via64.

The via66is provided through part of the insulating layer58between the interconnect65and the external connection pad44. As a result, the via66is connected to the interconnect65. The via66has a connection surface66A. The connection surface66A is connected to the external connection pad44.

Thereby, the interconnection pattern51electrically connects the first electronic component15, the through electrode21, and the external connection pad44. The end part of the via66positioned on the surface58B side in the insulating layer58forms a unitary structure with the external connection pad44. Examples of the material of the interconnection pattern51include Cu.

The interconnection pattern52includes vias68,69,72,74, and75and interconnects71and73. The via68is provided through part of the insulating layer56facing the connection surface32A of the first electrode pad32. The via68is directly connected to (or in direct contact with) the connection surface32A of the first electrode pad32. As a result, the interconnection pattern52is electrically connected to the first electronic component15.

The via69is provided through part of the insulating layer56facing the connection surface33A of the first electrode pad33. The via69is directly connected to (or in direct contact with) the connection surface33A of the first electrode pad33. As a result, the interconnection pattern52is electrically connected to the first electronic component16.

The interconnect71is provided on the surface56B of the insulating layer56. The interconnect71forms a unitary structure with the end parts of the vias68and69positioned on the surface56B side in the insulating layer56. Thereby, the interconnect71electrically connects the first electronic components15and16.

The via72is provided through part of the insulating layer57facing the interconnect71. As a result, the via72is connected to the interconnect71.

The interconnect73is provided on the surface57B of the insulating layer57. The interconnect73forms a unitary structure with the end part of the via72positioned on the surface57B side in the insulating layer57. As a result, the interconnect73is electrically connected to the via72.

The via74is provided through part of the insulating layer58between the interconnect73and the external connection pad45. As a result, the via74is connected to the interconnect73. The via74has a connection surface74A. The connection surface74A is connected to the external connection pad45. As a result, the external connection pad45is electrically connected to the first electronic components15and16. The end part of the via74positioned on the surface58B side in the insulating layer58forms a unitary structure with the external connection pad45.

The via75is provided through part of the insulating layer58between the interconnect73and the external connection pad46. As a result, the via75is connected to the interconnect73. The via75has a connection surface75A. The connection surface75A is connected to the external connection pad46. As a result, the external connection pad46is electrically connected to the first electronic components15and16. The end part of the via75positioned on the surface58B side in the insulating layer58forms a unitary structure with the external connection pad46. The interconnection pattern52is electrically connected to the first electronic components15and16and the external connection pads45and46. Examples of the material of the interconnection pattern52include Cu.

The interconnection pattern53includes vias77,78,81, and83and interconnects79and82. The via77is provided through part of the insulating layer56facing the through electrode22. The via77has a connection surface77A. The connection surface77A is connected to the end surface22B of the through electrode22. As a result, the interconnection pattern53is electrically connected to the through electrode22.

The via78is provided through part of the insulating layer56facing the connection surface34A of the first electrode pad34. The via78is directly connected to (or in direct contact with) the connection surface34A of the first electrode pad34. As a result, the interconnection pattern53is electrically connected to the first electronic component16.

The interconnect79is provided on the surface56B of the insulating layer56. The interconnect79forms a unitary structure with the end parts of the vias77and78positioned on the surface56B side in the insulating layer56. Thereby, the interconnect79electrically connects the first electronic component16and the through electrode22.

The via81is provided through part of the insulating layer57facing the interconnect79. As a result, the via81is connected to the interconnect79.

The interconnect82is provided on the surface57B of the insulating layer57. The interconnect82forms a unitary structure with the end part of the via81positioned on the surface57B side in the insulating layer57. As a result, the interconnect82is electrically connected to the via81.

The via83is provided through part of the insulating layer58between the interconnect82and the external connection pad47. As a result, the via83is connected to the interconnect82. The via83has a connection surface83A. The connection surface83A is connected to the external connection pad47. Thereby, the interconnection pattern53electrically connects the first electronic component15, the through electrode22, and the external connection pad47. The end part of the via83positioned on the surface58B side in the insulating layer58forms a unitary structure with the external connection pad47. Examples of the material of the interconnection pattern53include Cu.

Directly connecting the first electrode pads31through34of the first electronic components15and16with the interconnection patterns51through53as described above eliminates the necessity of bumps for electrically connecting the first electronic components15and16and the first multilayer interconnection structure25. As a result, the first semiconductor device11is reduced in size in its thickness directions.

The interconnection patterns54have vias85,87, and89and interconnects86and88. The vias85are provided through parts of the insulating layer56facing the through electrodes23. The vias85have respective connection surfaces85A. The connection surfaces85A are connected to the end surfaces23B of the corresponding through electrodes23. As a result, the interconnection patterns54are electrically connected to the corresponding through electrodes23.

The interconnects86are provided on the surface56B of the insulating layer56. The interconnects86form respective unitary structures with the end parts of the corresponding vias85positioned on the surface56B side in the insulating layer56. As a result, the interconnects86are electrically connected to the corresponding vias85.

The vias87are provided through parts of the insulating layer57facing the interconnects86. As a result, the vias87are connected to the corresponding interconnects86.

The interconnects88are provided on the surface57B of the insulating layer57. The interconnects88form respective unitary structures with the end parts of the corresponding vias87positioned on the surface57B side in the insulating layer57. As a result, the interconnects88are electrically connected to the corresponding vias87.

The vias89are provided through parts of the insulating layer58between the corresponding interconnects88and external connection pads43. As a result, the vias89are connected to the corresponding interconnects88. The vias89have respective connection surfaces89A. The connection surfaces89A are connected to the corresponding external connection pads43. Thereby, the interconnection patterns54electrically connect the through electrodes23and the corresponding external connection pads43. The end parts of the vias89positioned on the surface58B side in the insulating layer58form respective unitary structures with the corresponding external pads43. Examples of the material of the interconnection patterns54include Cu.

The first multilayer interconnection structure25having the above-described configuration is smaller in thickness than the first electronic components15and16and the sealing resin18. The first multilayer interconnection structure25may be, for example, 100 μm in thickness.

According to the first semiconductor device11having the above-described configuration, the first electrode pads31through34of the first electronic components15and16and the interconnection patterns51through53are directly connected to eliminate the necessity of bumps for electrically connecting the first electronic components15and16and the first multilayer interconnection structure25. As a result, the first semiconductor device11is reduced in size in its thickness directions.

Referring toFIG. 2Bas well asFIG. 2A, the second semiconductor device12includes an adhesive layer94, second electronic components95and96, sealing resin98, through holes101,102,103,104, and105, through electrodes111,112,113,114, and115, and a second multilayer interconnection structure117.

The adhesive layer94has a surface94A and an electronic component placement surface94B facing away from (on the side opposite to) the surface94A. The adhesive layer is provided so as to cover the surface58B of the insulating layer58of the first semiconductor device11and the external connection pads43through47provided on the surface58B. As a result, the surface94A of the adhesive layer94is in contact with the surface58B of the insulating layer58.

For example, an epoxy resin film may be used for the adhesive layer94. In this case, the adhesive layer94may be, for example, 50 μm in thickness.

The second electronic component95has a thin plate shape and may be, for example, 200 μm to 300 μm in thickness. The second electronic component95includes a second electrode pad121having a connection surface121A; a second electrode pad122having a connection surface122A; an electrode pad formation surface95A on which the second electrode pads121and122are formed; and a rear surface95B on the side opposite to (facing away from) the electrode pad formation surface95A. The rear surface95B of the second electronic component95is bonded to the electronic component placement surface94B of the adhesive layer94.

The second electronic component96has a thin plate shape and is substantially equal in thickness to the second electronic component95. The second electronic component96may be, for example, 200 μm to 300 μm in thickness. The second electronic component96includes a second electrode pad123having a connection surface123A; a second electrode pad124having a connection surface124A; an electrode pad formation surface96A on which the second electrode pads123and124are formed; and a rear surface965on the side opposite to (facing away from) the electrode pad formation surface96A. The rear surface96B of the second electronic component96is bonded to the electronic component placement surface94B of the adhesive layer94.

The second electronic components95and96may be, for example, semiconductor chips. By way of example, the second electronic components95and96may be semiconductor chips for CPUs (Central Processing Units); one of the second electronic components95and96may be a semiconductor chip for a CPU and the other one of the first electronic components95and96may be a semiconductor chip for a memory; or one of the first electronic components95and96may be a semiconductor chip for a CPU and the other one of the first electronic components95and96may be a semiconductor chip for a GPU (Graphics Processing Unit).

The sealing resin98is provided on the electronic component placement surface94B and around the second electronic components95and96to seal the side surfaces of the second electronic components95and96. The sealing resin98is substantially equal in thickness to the second electronic components95and96. The sealing resin98may be, for example, 200 μm to 300 μm in thickness.

The sealing resin98has a surface98A and a multilayer interconnection structure formation surface98B on the side opposite to (facing away from) the surface98A. The rear surfaces95B and96B of the second electronic components95and96, respectively, are exposed at the surface98A of the sealing resin98. The surface98A of the sealing resin98is substantially level with the rear surfaces95B and96B of the second electronic components95and96. As a result, the surface98A of the sealing resin98and the rear surfaces95B and96B of the second electronic components95and96are in substantially the same plane (that is, substantially form a single surface).

By thus configuring the sealing resin98, sealing the side surfaces of the second electronic components95and96, so that the surface98A is substantially level with the rear surfaces95B and96B of the second electronic components95and96, it is possible to seal the side surfaces of the second electronic components95and96without an increase in the size of the second semiconductor device12in its thickness directions (vertical directions inFIG. 2B).

The electrode pad formation surfaces95A and96A of the second electronic components95and96and the second electrode pads121through124are exposed at the multilayer interconnection structure formation surface98B of the sealing resin98. The multilayer interconnection structure formation surface98B is substantially level with the electrode pad formation surfaces95A and96A.

The sealing resin98may be, for example, molded resin, whose material may be, for example, epoxy resin.

The through hole101is formed through part of the adhesive layer94and part of the sealing resin98which parts face the external connection pad45of the semiconductor device11, so as to expose the connection surface45A of the external connection pad45.

The through hole102is formed through part of the adhesive layer94and part of the sealing resin98which parts face the external connection pad46of the first semiconductor device11, so as to expose the connection surface46A of the external connection pad46.

The through hole103is formed through part of the adhesive layer94and part of the sealing resin98which parts face the external connection pad44of the semiconductor device11, so as to expose the connection surface44A of the external connection pad44.

The through hole104is formed through part of the adhesive layer94and part of the sealing resin98which parts face the external connection pad47of the first semiconductor device11, so as to expose the connection surface47A of the external connection pad47.

The through holes105are formed through parts of the adhesive layer94and parts of the sealing resin98which parts face the external connection pads43of the first semiconductor device11, so as to expose the connection surfaces43A of the external connection pad43.

The through holes101through105configured as described above may be, for example, 200 μm in diameter.

The through electrode111is provided in the through hole101. The through electrode111has an end surface111A connected to the connection surface45A of the external connection pad45of the first semiconductor device11. As a result, the through electrode111is electrically connected to the first semiconductor device11.

The through electrode111has another end surface111B in substantially the same plane as the electrode pad formation surfaces95A and96A of the second electronic components95and96and the multilayer interconnection structure formation surface98A of the sealing resin98. The end surface111B of the through electrode111is electrically connected to the second multilayer interconnection structure117.

The through electrode112is provided in the through hole102. The through electrode112has an end surface112A connected to the connection surface46A of the external connection pad46of the first semiconductor device11. As a result, the through electrode112is electrically connected to the first semiconductor device11.

The through electrode112has another end surface112B in substantially the same plane as the electrode pad formation surfaces95A and96A of the second electronic components95and96and the multilayer interconnection structure formation surface98A of the sealing resin98. The end surface112B of the through electrode112is electrically connected to the second multilayer interconnection structure117.

The through electrode113is provided in the through hole103. The through electrode113has an end surface113A connected to the connection surface44A of the external connection pad44of the first semiconductor device11. As a result, the through electrode113is electrically connected to the first semiconductor device11.

The through electrode113has another end surface113B in substantially the same plane as the electrode pad formation surfaces95A and96A of the second electronic components95and96and the multilayer interconnection structure formation surface98A of the sealing resin98. The end surface113B of the through electrode113is electrically connected to the second multilayer interconnection structure117.

The through electrode114is provided in the through hole104. The through electrode114has an end surface114A connected to the connection surface47A of the external connection pad47of the first semiconductor device11. As a result, the through electrode114is electrically connected to the first semiconductor device11.

The through electrode114has another end surface114B in substantially the same plane as the electrode pad formation surfaces95A and96A of the second electronic components95and96and the multilayer interconnection structure formation surface98A of the sealing resin98. The end surface114B of the through electrode114is electrically connected to the second multilayer interconnection structure117.

The through electrodes115are provided in the corresponding through holes105. The through electrodes115have respective end surfaces115A connected to the connection surfaces43A of the corresponding external connection pads43of the first semiconductor device11. As a result, the through electrodes115are electrically connected to the first semiconductor device11.

The through electrodes115have respective other end surfaces115B in substantially the same plane as the electrode pad formation surfaces95A and96A of the second electronic components95and96and the multilayer interconnection structure formation surface98A of the sealing resin98. The end surfaces115B of the through electrodes115are electrically connected to the second multilayer interconnection structure117.

The through electrodes111through115configured as described above may be, for example, 200 μm in diameter. The through electrodes111through115may be, for example, 240 μm in height (vertical size). The through electrodes111through115may be formed by, for example, plating. Examples of the material of the through electrodes111through115include Cu.

The second multilayer interconnection structure117has substantially the same configuration as the first multilayer interconnection structure25of the first semiconductor device11except for additionally having a solder resist layer128on the configuration of the first multilayer interconnection structure25. That is, the second multilayer interconnection structure117includes the layered body41, which includes the insulating layers56,57, and58, and the solder resist layer128.

The second multilayer interconnection structure117is provided on the second electrode pads121through124and on the electrode pad formation surfaces95A and96A, the multilayer interconnection structure surface98B, and the end surfaces111B,112B,113B,114B, and115B of the through electrodes111through115, which are in the same plane.

The connection surfaces43A,44A,45A,46A, and47A of the external connection pads43through47(second pads) of the second multilayer interconnection structure117are to be connected to external connection terminals (not graphically illustrated) connected to a mounting board (not graphically illustrated) such as a motherboard when the electronic device10is mounted on the mounting board.

Here, a description is given of the connections of the interconnection patterns51through54(second interconnection patterns) of the second multilayer interconnection structure117.

The interconnection pattern51is directly connected to (or in direct contact with) the connection surface121A of the second electrode pad121. As a result, the interconnection pattern51is electrically connected to the second electronic component95. The interconnection pattern51has multiple connection surfaces61A. The connection surfaces61A of the interconnection pattern51are connected to the end surfaces111B and113B of the through electrodes111and113, respectively. As a result, the interconnection pattern51is electrically connected to the first semiconductor device11through the through electrodes111and113. The connection surface66A of the interconnection pattern51is connected to the external connection pad44. The interconnection pattern51electrically connects the external connection pad44, the second electronic component95, and the through electrodes111and113.

The interconnection pattern52is directly connected to (or in direct contact with) the connection surfaces122A and123A of the second electrode pads122and123, respectively. As a result, the interconnection pattern52is electrically connected to the second electronic components95and96. The connection surface74A of the interconnection pattern52is connected to the external connection pad45. The connection surface75A of the interconnection pattern52is connected to the external connection pad46. The interconnection pattern52electrically connects the external connection pads45and46and the second electronic components95and96.

The interconnection pattern53is directly connected to (or in direct contact with) the connection surface124A of the second electrode pad124. As a result, the interconnection pattern53is electrically connected to the second electronic component96. The interconnection pattern53has multiple connection surfaces77A. The connection surfaces77A of the interconnection pattern53are connected to the end surfaces112B and114B of the through electrodes112and114, respectively. As a result, the interconnection pattern53is electrically connected to the first semiconductor device11through the through electrodes112and114. The connection surface83A of the interconnection pattern53is connected to the external connection pad47. The interconnection pattern53electrically connects the external connection pad47, the second electronic component96, and the through electrodes112and114.

The connection surfaces85A of the interconnection patterns54are connected to the end surfaces115B of the corresponding through electrodes115. As a result, the interconnection patterns54are electrically connected to the first semiconductor device11through the through electrodes115. The connection surfaces89A of the interconnection patterns54are connected to the corresponding external connection pads43. The interconnection patterns54electrically connect the external connection pads43and the through electrodes115.

Directly connecting the second electrode pads121through124of the second electronic components95and96with the interconnection patterns51through53(second interconnection patterns) as described above eliminates the necessity of bumps for electrically connecting the second electronic components95and96and the second multilayer interconnection structure117. As a result, the second semiconductor device12is reduced in size in its thickness directions.

Further, the surface of the first semiconductor device11on the side on which the external connection pads43through47are formed is bonded to the adhesive layer94of the second semiconductor device12so that the external connection pads43, the external connection pads44and45, and the external connection pads46and47of the first semiconductor device11face the connection surfaces85A, the connection surfaces61A, and the connection surfaces77A, respectively, of the second semiconductor device12. Further, the through electrodes115, the through electrodes113and111, and the through electrodes112and114are provided through the parts of the adhesive layer94and the parts of the sealing resin98between the external connection pads43and the connection surfaces85A, the external connection pads44and45and the connection surfaces61A, and the external connection pads46and47and the connection surfaces77A, respectively, to be connected to the external connection pads43and the connection surfaces85A, the external connection pads44and45and the connection surfaces61A, and the external connection pads46and47and the connection surfaces77A, respectively. This makes it possible to electrically connect the first semiconductor device11and the second semiconductor device12without using internal connection terminals (such as solder balls) (that is, without providing a gap for providing internal connection terminals large [for example, 300 μm] in diameter between the first semiconductor device11and the second semiconductor device12). Accordingly, the electronic device10is reduced in size in its thickness directions (vertical directions inFIGS. 2A and 2B).

Further, compared with the case of electrically connecting the first semiconductor device11and the second semiconductor device12using internal connection terminals (such as solder balls), it is possible to increase the reliability of the electrical connection between the first semiconductor device11and the second semiconductor device12by electrically connecting the first semiconductor device11and the second semiconductor device12through the through electrodes111through115.

In addition, the electronic device10is formed by stacking the first semiconductor device11, which includes the first multilayer interconnection structure25having the interconnection patterns51through53directly connected to the first electrode pads31through34of the first electronic components15and16, and the second semiconductor device12, which includes the second multilayer interconnection structure117having the interconnection patterns51through53directly connected to the second electrode pads121through124of the second electronic components95and96. Accordingly, the electronic device10is reduced in size in its thickness directions.

The solder resist layer128is provided on the surface58B of the insulating layer58of the second multilayer interconnection structure117so as to expose the connection surfaces43A,44A,45A,46A, and47A of the external connection pads43through47of the second multilayer interconnection structure117.

The second multilayer interconnection structure117configured as described above is smaller in thickness than the second electronic components95and96and the sealing resin98. The second multilayer interconnection structure117may be, for example, 100 μm in thickness.

According to the electronic device10of this embodiment, the surface of the first semiconductor device11on the side on which the external connection pads43through47are formed is bonded to the adhesive layer94of the second semiconductor device12so that the external connection pads43, the external connection pads44and45, and the external connection pads46and47of the first semiconductor device11face the connection surfaces85A, the connection surfaces61A, and the connection surfaces77A, respectively, of the second semiconductor device12. Further, the through electrodes115, the through electrodes113and111, and the through electrodes112and114are provided through the parts of the adhesive layer94and the parts of the sealing resin98between the external connection pads43and the connection surfaces85A, the external connection pads44and45and the connection surfaces61A, and the external connection pads46and47and the connection surfaces77A, respectively, to be connected to the external connection pads43and the connection surfaces85A, the external connection pads44and45and the connection surfaces61A, and the external connection pads46and47and the connection surfaces77A, respectively. This makes it possible to electrically connect the first semiconductor device11and the second semiconductor device12without using internal connection terminals (such as solder balls). Accordingly, the electronic device10is reduced in size in its thickness directions.

Further, compared with the case of electrically connecting the first semiconductor device11and the second semiconductor device12using internal connection terminals (such as solder balls), it is possible to increase the reliability of the electrical connection between the first semiconductor device11and the second semiconductor device12by electrically connecting the first semiconductor device11and the second semiconductor device12through the through electrodes111through115.

In addition, the electronic device10is formed by stacking the first semiconductor device11, which includes the first multilayer interconnection structure25having the interconnection patterns51through53directly connected to the first electrode pads31through34of the first electronic components15and16, and the second semiconductor device12, which includes the second multilayer interconnection structure117having the interconnection patterns51through53directly connected to the second electrode pads121through124of the second electronic components95and96. Accordingly, the electronic device10is reduced in size in its thickness directions.

FIGS. 3A through 3Uare diagrams illustrating a process for manufacturing an electronic device according to the first embodiment of the present invention. InFIGS. 3A through 3U, the same elements as those of the electronic device10of the first embodiment are referred to by the same reference numerals.

A description is given, with reference toFIGS. 3A through 3U, of a method of manufacturing the electronic device10of the first embodiment.

First, in the process illustrated inFIG. 3A, an adhesive agent132is formed (provided) on a surface131A of a support body131. Examples of the support body131include a glass substrate, a silicon substrate, and a metal plate (such as a Cu plate). The support body131may be, for example, 300 μm to 600 μm in thickness. Examples of the adhesive agent132include an adhesive polyimide resin tape (for example, 1 μm to 20 μm in thickness).

Next, in the process illustrated inFIG. 3B, the first electronic components15and16are bonded onto the support body131so that the connection surfaces31A,32A,33A, and34A of the first electrode pads31through34come into contact with the surface131A of the support body131and the electrode pad formation surfaces15A and16A of the first electronic components15and16are covered with the adhesive agent132.

At this stage, the first electronic components15and16do not have a thin plate shape (that is, not thinned). The first electronic components15and16at this stage, which are not thinned, are easier to handle than the first electronic components15and16shaped into thin plates. Accordingly, it is possible to bond the first electronic components15and16to predetermined positions on the support body131with accuracy. The first electronic components15and16at this stage, that is, before being subjected to thinning, may be, for example, 700 μm in thickness.

The first electronic components15and16may be, for example, semiconductor chips. By way of example, the first electronic components15and16may be semiconductor chips for CPUs (Central Processing Units); one of the first electronic components15and16may be a semiconductor chip for a CPU and the other one of the first electronic components15and16may be a semiconductor chip for a memory; or one of the first electronic components15and16may be a semiconductor chip for a CPU and the other one of the first electronic components15and16may be a semiconductor chip for a GPU (Graphics Processing Unit).

Next, in the process illustrated inFIG. 3C, the sealing resin18is formed (provided) on a surface132A of the adhesive agent132, which surface132A is on the side opposite to the surface of the adhesive agent132in contact with the support body131, so as to seal parts of the side surfaces of the first electronic components15and16.

The sealing resin18may be, for example, molded resin, which may be formed of, for example, epoxy resin. The sealing resin18may be formed by transfer molding. The sealing resin18is formed to have its upper surface positioned higher than the rear surfaces15B and16B of the first electronic components15and16after a thinning process. At this stage, the sealing resin18may be, for example, 300 μm in thickness.

Next, in the process illustrated inFIG. 3D, the first electronic components15and16and the sealing resin18are ground from the upper surface side of the structure illustrated inFIG. 3C(the side of the rear surfaces15B and16B of the first electronic components15and16) (using, for example, a backside grinder), thereby thinning the first electronic components15and16so that the rear surfaces15B and16B of the thinned first electronic components15and16and the surface18A of the ground sealing resin18are in the same plane.

As a result, the structure illustrated inFIG. 3Dhas a flat upper surface. The first electronic components15and16(parts of the first electronic components15and16on the adhesive agent132) after thinning may be, for example, 200 μm in thickness. In this case, the sealing resin18after grinding may be, for example, 200 μm in thickness.

Next, in the process illustrated inFIG. 3E, the through holes36through38are formed through the sealing resin18and the adhesive agent132from the surface18A side of the sealing resin18.

The through holes36through38are formed by exposing parts of the sealing resin18and the adhesive agent corresponding to (regions) where the through holes36through38are to be formed to laser light, for example. The through holes36through38are formed to expose the surface131A of the support body131. The through holes36through38may be, for example, 200 μm in diameter.

Next, in the process illustrated inFIG. 3F, the through electrode21, the through electrode22, and the through electrodes23are simultaneously formed to fill in the through hole36, the through hole37, and the through holes38, respectively. As a result, the end surfaces21B,22B, and23B of the through electrodes21through23are formed in the same plane as the connection surfaces31A,32A,33A, and34A of the first electrode pads31through34.

At this point, the through electrodes21through23are formed so as to have their respective end surfaces21A,22A, and23A positioned in the same plane as the rear surfaces15B and16B of the first electronic components15and16and the surface18A of the sealing resin18. The through electrodes21through23may be formed by, for example, plating or printing.

In the case of using printing, a Cu layer may be formed on the surface131A of the support body131(such as, a silicon substrate or a glass substrate) by sputtering. The Cu layer serves as a power feeding layer in the case of a silicon substrate or a glass substrate. Thereafter, the Cu layer is fed with electricity to cause a plate film to be deposited and grow to fill in the through holes36through38. Thereby, the through electrodes21through23are formed. Examples of the material of the through electrodes21through23include Cu.

In the case of using a metal plate (such as a Cu plate) as the support body131, the support body131serves as a power feeding layer. Accordingly, there is no need to form the above-described Cu layer. The through electrodes21through23may be, for example, 200 μm in diameter.

After formation of the through electrodes21through23, a protection layer (such as a Ni/Au layered film of alternate layers of Ni-plating and Au-plating) may be provided on the end surfaces21A,22A, and23A of the through electrodes21through23.

Next, in the process illustrated inFIG. 3G, the adhesive agent132and the support body131are removed from the first electronic components15and16and the sealing resin18in which the through electrodes21through23are formed as illustrated inFIG. 3F.

For example, the support body131is mechanically separated from the first electronic components15and16and the sealing resin18in which the through electrodes21through23are formed as illustrated inFIG. 3F, thereby removing the support body131and the adhesive agent132together. As a result, the through electrodes21through23and the first electrode pads31through34project relative to the multilayer interconnection structure formation surface18B of the sealing resin18by the thickness of the adhesive agent132. However, such projecting to some extent does not cause a problem in the manufacturing process. Further, the end surfaces21B,22B, and23B of the through electrodes21through23and the connection surfaces31A,32A,33A, and34A of the first electrode pads31through34are not in completely the same plane as the multilayer interconnection structure formation surface18B of the sealing resin18.

Next, in the process illustrated inFIG. 3H, the insulating layer56having openings133,134,135,136,137,138, and139is formed on the multilayer interconnection structure formation surface18B of the sealing resin18, the first electrode pads31through34, the electrode pad formation surfaces15A and16A of the first electronic components15and16, and the end surfaces21B,22B, and23B of the through electrodes21through23.

For example, the insulating layer56is formed by sticking an insulating resin film (such as an epoxy resin film) serving as the base material of the insulating layer56to the lower surface of the structure illustrated inFIG. 3Gand thereafter performing laser processing on parts of the insulating resin film corresponding to the openings133through139. The insulating layer56may be, for example, 5 μm to 30 μm in thickness.

The openings133are formed so as to expose the end surfaces23B of the through electrodes23. The opening134is formed so as to expose the end surface21B of the through electrode21. The opening135is formed so as to expose the connection surface31A of the first electrode pad31. The opening136is formed so as to expose the connection surface32A of the first electrode pad32. The opening137is formed so as to expose the connection surface33A of the first electrode pad33. The opening138is formed so as to expose the connection surface34A of the first electrode pad34. The opening139is formed so as to expose the end surface22B of the through electrode22.

Next, in the process illustrated inFIG. 3I, the vias61,62,68,69,77,78, and85are formed in the openings134,135,136,137,139,138, and133, respectively, and the interconnects63,71,79, and86are formed on the surface56B of the insulating layer56at the same time.

The via61is formed in the opening134so that the connection surface61A connects to the end surface218of the through electrode21. The via62is formed in the opening135so as to connect to the connection surface31A of the first electrode pad31. The via68is formed in the opening136so as to connect to the connection surface32A of the first electrode pad32. The via69is formed in the opening137so as to connect to the connection surface33A of the first electrode pad33. The via77is formed in the opening139so that the connection surface77A connects to the end surface22B of the through electrode22. The via78is formed in the opening138so as to connect to the connection surface34A of the first electrode pad34. The vies85are formed in the corresponding openings133so that the connection surfaces85A connect to the end surfaces23B of the corresponding through electrodes23.

The interconnect63is formed on the surface56B of the insulating layer56as part of a unitary structure with the vies61and62. The interconnect71is formed on the surface56B of the insulating layer56as part of a unitary structure with the vias68and69. The interconnect79is formed on the surface56B of the insulating layer56as part of a unitary structure with the vias77and78. The interconnects86are formed on the surface56B of the insulating layer56as parts of respective unitary structures with the corresponding vias85.

As a result, the first electrode pads31and32of the first electronic component15are directly connected to (or in direct contact with) the vias62and68, respectively, and the first electrode pads33and34of the first electronic component16are directly connected to (or in direct contact with) the vias69and78, respectively.

By thus connecting the first electrode pads31through34of the first electronic components15and16directly to the vias62,68,69, and78, it is possible to electrically connect the first electronic components15and16and the first multilayer interconnection structure25without using bumps or metal wires. Accordingly, the first semiconductor device11is reduced in size in its thickness directions.

The vias61,62,68,69,77,78, and85and the interconnects63,71,79, and86may be formed by, for example, a semi-additive process. Examples of the material of the vias61,62,68,69,77,78, and85and the interconnects63,71,79, and86include Cu.

Next, in the process illustrated inFIG. 3J, the insulating layer57having openings141,142,143, and144is formed on the surface56B of the insulating layer56by performing the same processing as in the above-described process illustrated inFIG. 3H.

The openings141are formed so as to expose parts of the corresponding interconnects86. The opening142is formed so as to expose part of the interconnect63. The opening143is formed so as to expose part of the interconnect71. The opening144is formed so as to expose part of the interconnect79. Examples of the material of the insulating layer57include an epoxy resin film. The insulating layer57may be, for example, 5 μm to 30 μm in thickness.

Next, the vias64,72,81, and87are formed in the openings142,143,144, and141, respectively, and the interconnects65,73,82, and88are formed on the surface57B of the insulating layer57at the same time by performing the same processing as in the above-described process illustrated inFIG. 3I.

The via64is formed in the opening142so as to connect to the interconnect63. The via72is formed in the opening143so as to connect to the interconnect71. The via81is formed in the opening144so as to connect to the interconnect79. The vias87are formed in the corresponding openings141so as to connect to the corresponding interconnects86.

The interconnect65is formed on the surface57B of the insulating layer57as part of a unitary structure with the via64. The interconnect73is formed on the surface57B of the insulating layer57as part of a unitary structure with the via72. The interconnect82is formed on the surface57B of the insulating layer57as part of a unitary structure with the via81. The interconnects88are formed on the surface57B of the insulating layer57as parts of respective unitary structures with the corresponding vias87.

The vias64,72,81, and87and the interconnects65,73,82, and88may be formed by, for example, a semi-additive process. Examples of the material of the vias64,72,81, and87and the interconnects65,73,82, and88include Cu.

Next, in the process illustrated inFIG. 3K, the insulating layer58having openings145,146,147,148, and149is formed on the surface57B of the insulating layer57by performing the same processing as in the above-described process illustrated inFIG. 3H.

The openings145are formed so as to expose parts of the corresponding interconnects88. The opening146is formed so as to expose part of the interconnect65. The opening147is formed so as to expose part of the interconnect73. The opening148is formed so as to expose part of the interconnect73. The opening149is formed so as to expose part of the interconnect82. Examples of the material of the insulating layer58include an epoxy resin film. The insulating layer58may be, for example, 5 μm to 30 μm in thickness.

Next, the vias66,74,75,83, and89are formed in the openings146,147,148,149, and145, respectively, and the external connection pads43through47are formed on the surface58B of the insulating layer58at the same time by performing the same processing as in the above-described process illustrated inFIG. 3I. As a result, the interconnection patterns51through54and the first multilayer interconnection structure25are formed, and the first semiconductor device11including the interconnection patterns51through54and the first multilayer interconnection structure25is manufactured. The processes illustrated inFIGS. 3A through 3Kmay be referred to as a first semiconductor device forming step.

The via66is formed in the opening146so as to connect to the interconnect65. The via74is formed in the opening147so as to connect to the interconnect73. The via75is formed in the opening148so as to connect to the interconnect73. The via83is formed in the opening149so as to connect to the interconnect82. The vias89are formed in the corresponding openings145so as to connect to the corresponding interconnects88.

The external connection pads43are formed on the surface58B of the insulating layer58as parts of respective unitary structures with (the connection surfaces89A of) the corresponding vias89. The external connection pad44is formed on the surface58B of the insulating layer58as part of a unitary structure with (the connection surface66A) of the via66. The external connection pad45is formed on the surface58B of the insulating layer58as part of a unitary structure with (the connection surface74A) of the via74. The external connection pad46is formed on the surface58B of the insulating layer58as part of a unitary structure with (the connection surface75A) of the via75. The external connection pad47is formed on the surface58B of the insulating layer58as part of a unitary structure with (the connection surface83A) of the via83.

The vias66,74,75,83, and89and the external connection pads43through47may be formed by, for example, a semi-additive process. Examples of the material of the vias66,74,75,83, and89and the external connection pads43through47include Cu.

Next, in the process illustrated inFIG. 3L, the first semiconductor device11illustrated inFIG. 3Kis turned upside down.

Next, in the process illustrated inFIG. 3M, the second electronic components95and96are prepared. The second electronic component95includes the second electrode pads121and122having their respective connection surfaces121A and122A, the electrode pad formation surface95A on which the second electrode pads121and122are formed, and the rear surface95B. The second electronic component96includes the second electrode pads123and124having their respective connection surfaces123A and124A, the electrode pad formation surface96A on which the second electrode pads123and124are formed, and the rear surface96B. Thereafter, the electronic component placement surface94B of the adhesive layer94and the rear surfaces95B and96B of the second electronic components95and96are bonded. (This process may be referred to as a second electronic component bonding process.)

Examples of the adhesive layer94include an epoxy resin film. In this case, the adhesive layer94may be, for example, 50 μm in thickness.

The second electronic components95and96have a thin plate shape and may be, for example, 200 μm in thickness. The second electronic components95and96may be, for example, semiconductor chips. By way of example, the second electronic components95and96may be semiconductor chips for CPUs (Central Processing Units); one of the second electronic components95and96may be a semiconductor chip for a CPU and the other one of the first electronic components95and96may be a semiconductor chip for a memory; or one of the first electronic components95and96may be a semiconductor chip for a CPU and the other one of the first electronic components95and96may be a semiconductor chip for a GPU (Graphics Processing Unit).

Next, in the process illustrated inFIG. 3N, the sealing resin98is formed on the electronic component placement surface94B of the adhesive layer94. (This process may be referred to as a sealing resin forming process.) The sealing resin98has the multilayer interconnection structure formation surface985that exposes the second electrode pads121through124and the electrode pad formation surfaces95A and96A, and seals the side surfaces of the second electronic components95and96.

The sealing resin98may be, for example, molded resin, whose material may be, for example, epoxy resin. The sealing resin98may be formed by transfer molding. The sealing resin98may be, for example, 200 μm in thickness.

Next, in the process illustrated inFIG. 3O, the structure illustrated inFIG. 3Nis stuck onto the first semiconductor device11illustrated inFIG. 3L, so that the surface94A of the adhesive layer94provided in the structure illustrated inFIG. 3Ncovers the surface58A of the insulating layer58and the external connection pads43through47of the first semiconductor device11. (This process may be referred to as an adhesive layer sticking process.)

Next, in the process illustrated inFIG. 3P, the through holes101through105are formed through parts of the adhesive layer94and the sealing resin98which parts face the connection surfaces45A,46A,44A,47A, and43A of the external connection pads45,46,44,47, and43, respectively.

The through hole101is formed so as to expose the connection surface45A. The through hole102is formed so as to expose the connection surface46A. The through hole103is formed so as to expose the connection surface44A. The through hole104is formed so as to expose the connection surface47A. The through holes105are formed so as to expose the corresponding connection surfaces43A.

The through holes101through105may be formed by performing laser processing on parts of the adhesive layer94and the sealing resin98which parts correspond to (regions) where the through holes101through105are to be formed. The through holes101through105may be, for example, 200 μm in diameter.

Next, in the process illustrated inFIG. 3Q, the through electrodes111through115are formed to fill in the through holes101through105, respectively, by the same technique as in the above-described process illustrated inFIG. 3F. Examples of the material of the through electrodes111through115include Cu.

The through electrode111is formed in the through hole101so as to have the end surface111A connected to the connection surface45A and to have the end surface111B in substantially the same plane as the electrode pad formation surfaces95A and96A and the surface98B of the sealing resin98.

The through electrode112is formed in the through hole102so as to have the end surface112A connected to the connection surface46A and to have the end surface112B in substantially the same plane as the electrode pad formation surfaces95A and96A and the surface98B of the sealing resin98.

The through electrode113is formed in the through hole103so as to have the end surface113A connected to the connection surface44A and to have the end surface113B in substantially the same plane as the electrode pad formation surfaces95A and96A and the surface98B of the sealing resin98.

The through electrode114is formed in the through hole104so as to have the end surface114A connected to the connection surface47A and to have the end surface114B in substantially the same plane as the electrode pad formation surfaces95A and96A and the surface98B of the sealing resin98.

The through electrodes115are formed in the corresponding through holes105so as to have the end surfaces115A connected to the corresponding connection surfaces43A and to have the end surfaces115B in substantially the same plane as the electrode pad formation surfaces95A and96A and the surface98B of the sealing resin98.

Next, in the process illustrated inFIG. 3R, the insulating layer56having openings151,152,153,154,155,156,157,158, and159is formed on the multilayer interconnection structure formation surface98B and on the end surfaces111B,112B,113B,114B, and115B of the through electrodes111through115, the electrode pad formation surfaces95A and96A of the second electronic components95and96, and the second electrode pads121through124, which are exposed at the multilayer interconnection structure formation surface98B (that is, not covered with the sealing resin98), by the same technique as in the above-described process illustrated inFIG. 3H. Examples of the insulating layer56include an insulating resin film (such as an epoxy resin film). The insulating layer56may be, for example, 5 μm to 30 μm in thickness.

The openings151are formed so as to expose the end surfaces115B of the corresponding through electrodes115. The opening152is formed so as to expose the end surface113B of the through electrode113. The opening153is formed so as to expose the end surface111B of the through electrode111. The opening154is formed so as to expose the connection surface121A of the second electrode pad121. The opening155is formed so as to expose the connection surface122A of the second electrode pad122. The opening156is formed so as to expose the connection surface123A of the second electrode pad123. The opening157is formed so as to expose the connection surface124A of the second electrode pad124. The opening158is formed so as to expose the end surface112B of the through electrode112. The opening159is formed so as to expose the end surface114B of the through electrode114.

Next, in the process illustrated inFIG. 3S, the vias61,62,68,69,77,78, and85are formed in the openings152and153,154,155,156,158and159,157, and151, respectively, and the interconnects63,71,79, and86are formed on the surface56B of the insulating layer56at the same time by the same technique as in the above-described process illustrated inFIG. 3I.

The vias61are formed in the openings152and153so that the connection surfaces61A connect to the end surfaces111B and113B of the through electrode111and113, respectively. The via62is formed in the opening154so as to connect to the connection surface121A of the second electrode pad121. The via68is formed in the opening155so as to connect to the connection surface122A of the second electrode pad122. The via69is formed in the opening156so as to connect to the connection surface123A of the second electrode pad123. The vias77are formed in the openings158and159so that the connection surfaces77A connect to the end surfaces112B and114B of the through electrodes112and114, respectively. The via78is formed in the opening157so as to connect to the connection surface124A of the second electrode pad124. The vias85are formed in the corresponding openings151so that the connection surfaces85A connect to the end surfaces115B of the corresponding through electrodes115.

The interconnect63is formed on the surface56B of the insulating layer56as part of a unitary structure with the vias61and62. The interconnect71is formed on the surface56B of the insulating layer56as part of a unitary structure with the vias68and69. The interconnect79is formed on the surface56B of the insulating layer56as part of a unitary structure with the vias77and78. The interconnects86are formed on the surface56B of the insulating layer56as parts of respective unitary structures with the corresponding vias85.

As a result, the second electrode pads121and122of the second electronic component95are directly connected to (or in direct contact with) the vias62and68, respectively, and the second electrode pads123and124of the second electronic component96are directly connected to (or in direct contact with) the vias69and78, respectively.

By thus connecting the second electrode pads121through124of the second electronic components95and96directly to the vias62,68,69, and78, it is possible to electrically connect the second electronic components95and96and the second multilayer interconnection structure117without using bumps or metal wires. Accordingly, the second semiconductor device12is reduced in size in its thickness directions.

Next, in the process illustrated inFIG. 3T, the insulating layer57, the vias64,72,81, and87, and the interconnects73,82,86, and65; and the insulating layer58, the vias66,74,75,83, and89, and the external connection pads43through47are successively formed by the same techniques as in the above-described processes illustrated inFIGS. 3J and 3K.

As a result, the interconnection pattern51connected to the external connection pad44, the second electronic component95, and the through electrodes111and113; the interconnection pattern52connected to the external connection pads45and46and the second electronic components95and96; the interconnection pattern53connected to the external connection pad47, the second electronic component96, and the through electrodes112and114; and the interconnection patterns54connected to the corresponding external connection pads43and through electrodes115are formed.

The insulating layers57and58may be, for example, insulating resin films (such as epoxy resin films). The insulating layers57and58may be, for example, 5 μm to 30 μm in thickness. Examples of the materials of the vias64,72,81,87,66,74,75,83, and89, the interconnects73,82,86, and65, and the external connection pads43through47include Cu.

Next, in the process illustrated inFIG. 3U, the solder resist layer128is formed on the surface58B of the insulating layer58of the structure illustrated inFIG. 3Tso as to expose the connection surfaces43A,44A,45A,46A, and47A of the external connection pads43through47, and the resulting structure is turned upside down.

As a result, the second semiconductor device12is formed on the lower surface side of the first semiconductor device11, so that the electronic device10having the first semiconductor device11and the second semiconductor device12according to the first embodiment is manufactured. The processes illustrated inFIGS. 3M through 3Umay be referred to as a second semiconductor device forming step.

According to the electronic device10of this embodiment, the second semiconductor device12having the second electronic components95and96directly connected to the interconnection patterns51through53provided in the second multilayer interconnection structure117is formed on the first semiconductor device11having the first electronic components15and16directly connected to the interconnection patterns51through53provided in the first multilayer interconnection structure25, and the first semiconductor device11is electrically connected to the second multilayer interconnection structure117and the second electronic components95and96through the through electrodes111through115provided in the second semiconductor device12. This eliminates the need for bumps or metal wires for electrically connecting the interconnection patterns51through53and the first and the second electronic components15,16,95, and96; internal connection terminals for electrically connecting the first semiconductor device11and the second semiconductor device12; and a gap for providing such internal connection terminals. Accordingly, the electronic device10is reduced in size in its thickness directions.

Further, compared with the case of electrically connecting the first semiconductor device11and the second semiconductor device12using internal connection terminals (such as solder balls), it is possible to increase the reliability of the electrical connection between the first semiconductor device11and the second semiconductor device12by electrically connecting the first semiconductor device11and the second semiconductor device12through the through electrodes111through115.

This embodiment is described, taking the electronic device10as an example, where the first semiconductor device11including the through electrodes21through23and the sealing resin18and the second semiconductor device12including the through electrodes111through115and the sealing resin98are stacked. Here, as an alternative configuration, the first semiconductor device11provided in the electronic device10may be replaced with, for example, a common electronic-component-containing board (for example, a board having an electronic component such as a semiconductor chip built in a multilayer interconnection structure).

[b] Second Embodiment

FIG. 4is a cross-sectional view of an electronic device170according to a second embodiment of the present invention. InFIG. 4, the same elements as those of the electronic device10of the first embodiment are referred to by the same reference numerals.

Referring toFIG. 4, the electronic device170of the second embodiment has the same configuration as the electronic device10of the first embodiment except that the electronic device170further includes a third semiconductor device171in addition to the configuration of the electronic device10.

The third semiconductor device171is interposed between the first semiconductor device11and the second semiconductor device12. The third semiconductor device171is equal in configuration to the second semiconductor device12without the solder resist layer128.

The through electrodes111through115of the third semiconductor device171are connected to the external connection pads43through47of the first semiconductor device11. As a result, the third semiconductor device171is electrically connected to the first semiconductor device11.

The external connection pads43through47of the third semiconductor device171are connected to the through electrodes111through115of the second semiconductor device12. As a result, the third semiconductor device171is electrically connected to the second semiconductor device12. Further, the first semiconductor device11is electrically connected to the second semiconductor device12through the third semiconductor device171.

Thus, the electronic device may be configured by stacking two or more semiconductor devices. The electronic device170of the second embodiment having the above-described configuration produces the same effects as the electronic device10of the first embodiment.

The electronic device170of this embodiment produces the same effects as the electronic device10of the first embodiment. Further, the electronic device170of the second embodiment may be manufactured by executing the processes of the processes ofFIGS. 3A through 3Tdescribed in the first embodiment, thereafter executing the processes of the processes ofFIGS. 3M through 3Tdescribed in the first embodiment, and thereafter executing the process ofFIG. 3Udescribed in the first embodiment.

This embodiment is described, taking the electronic device170as an example, where the first semiconductor device11including the through electrodes21through23and the sealing resin18, the third semiconductor device including the through electrodes111through115and the sealing resin98, and the second semiconductor device12including the through electrodes111through115and the sealing resin98are stacked. Here, as an alternative configuration, the first semiconductor device11provided in the electronic device170may be replaced with, for example, a common electronic-component-containing board (for example, a board having an electronic component such as a semiconductor chip built in a multilayer interconnection structure).

Further, two or more third semiconductor devices171may be interposed between the first semiconductor device11and the second semiconductor device12.

According to one aspect of the present invention, a gap is eliminated between a first semiconductor device and a second semiconductor device, and a pad (one of the elements of the first semiconductor device) and an interconnection pattern (one of the elements of the second semiconductor device) are electrically connected via a through electrode. This makes it possible to reduce the size of the electronic device in its thickness directions.

Further, according to one aspect of the present invention, an interconnection pattern and an electrode pad of an electronic component are directly connected in a first semiconductor device, and an interconnection pattern and an electrode pad of a second electronic component are directly connected in a second semiconductor device. This reduces the size of the first electronic component and the second electronic component in their thickness directions, so that it is possible to reduce the size of the electronic device in its thickness directions.

Further, according to one aspect of the present invention, a first semiconductor device and a second semiconductor device are electrically connected via a through electrode. This increases the reliability of the electrical connection between the first semiconductor device and the second semiconductor device compared with the case of electrically connecting the first semiconductor device and the second semiconductor device using internal connection terminals (such as solder balls).

Further, according to one aspect of the present invention, a second semiconductor device having a second electronic component directly connected to a second interconnection pattern provided in a second multilayer interconnection structure is formed on a first semiconductor device having a first electronic component directly connected to a first interconnection pattern provided in a first multilayer interconnection structure, and the first semiconductor device is electrically connected to the second multilayer interconnection structure and the second electronic component via a through electrode provided in the second semiconductor device. This eliminates the need for: bumps or metal wires for electrically connecting the first and the second interconnection pattern and the first and the second electronic component; internal connection terminals for electrically connecting the first semiconductor device and the second semiconductor device; and a gap for providing such internal connection terminals. Accordingly, it is possible to reduce the size of the electronic device in its thickness directions.

Further, compared with the case of electrically connecting the first semiconductor device and the second semiconductor device using internal connection terminals (such as solder balls), it is possible to increase the reliability of the electrical connection between the first semiconductor device and the second semiconductor device by electrically connecting the first semiconductor device and the second semiconductor device via the through electrode.

Thus, according to one aspect of the present invention, it is possible to reduce the size of an electronic device in its thickness directions, and to increase the reliability of the electrical connection between a first semiconductor device and a second semiconductor device.