Semiconductor device

A semiconductor device is provided, including: a semiconductor substrate having an active area and an edge termination region; an upper electrode; an insulating film provided between the semiconductor substrate and the upper electrode and having a contact hole; a first conductivity-type drift region; a second conductivity-type base region; a second conductivity-type well region; and a second conductivity-type extension region formed extending in a direction toward the well region from the base region and separated from the upper electrode by the insulating film, wherein a sum of a first distance from an end portion of the contact hole closer to the well region to an end portion of the extension region closer to the well region and a second distance from the end portion of the extension region closer to the well region to the well region is smaller than a thickness of the semiconductor substrate in the active area.

The contents of the following Japanese patent applications are incorporated herein by reference:NO. 2017-026875 filed on Feb. 16, 2017, andNO. 2017-240871 filed on Dec. 15, 2017

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

For semiconductor devices such as a diode of FWD (Free Wheeling Diode) connected in parallel with a power device such as an insulated gate bipolar transistor (IGBT), a structure is conventionally known in which a p-type region is extended to the outside of a contact portion for an anode electrode on the upper surface of the semiconductor substrate (see Patent Document 1, for example).

Patent Document 1: Japanese Patent Application Publication No. 2013-179342

Semiconductor devices preferably have a high reverse recovery withstand capability.

SUMMARY

An aspect of the present invention provides a semiconductor device including a semiconductor substrate having formed therein an active area in which main current flows and an edge termination region to relax electric field. The semiconductor device may include an upper electrode provided above the semiconductor substrate. The semiconductor device may include an insulating film which is provided between the semiconductor substrate and the upper electrode, and has formed therein a contact hole. The semiconductor device may include a first conductivity-type drift region formed inside the semiconductor substrate. The semiconductor device may include a second conductivity-type base region which is formed on an upper-surface side of the semiconductor substrate in the active area, and is connected to the upper electrode through the contact hole. The semiconductor device may include a second conductivity-type well region which is formed on an upper-surface side of the semiconductor substrate in the edge termination region, and is separated from the upper electrode. The semiconductor device may include a second conductivity-type extension region which is formed extending in a direction toward the well region from the base region on an upper-surface side of the semiconductor substrate, and is separated from the upper electrode by the insulating film. In a plane parallel to the upper surface of the semiconductor substrate, a sum of a first distance from an end portion of the contact hole closer to the well region to an end portion of the extension region closer to the well region and a second distance from the end portion of the extension region closer to the well region to the well region may be smaller than a thickness of the semiconductor substrate in the active area.

The sum of the first distance and the second distance may be greater than 50 μm. The sum of the first distance and the second distance may be smaller than 100 μm.

A doping concentration NAof the extension region may satisfy the following formula:

wherein Jrate is a rated current density (A/cm2), q is an elementary charge (C), and vsat_Pis a saturation velocity of holes (cm/sec). A doping concentration of the extension region may be 5.0×1016/cm3or more and 3.0×1017/cm3or less.

A depth of the extension region may be same as a depth of the well region. A doping concentration of the extension region may be same as a doping concentration of the well region.

The semiconductor device may include a first conductivity-type cathode region which is provided between the drift region and a lower surface of the semiconductor substrate inside the semiconductor substrate, and has a higher doping concentration than the drift region. An end portion of the cathode region closer to the edge termination region may be arranged closer to the active area than the well region. The end portion of the cathode region closer to the edge termination region may be arranged closer to the active area than the end portion of the extension region closer to the well region. The end portion of the cathode region closer to the edge termination region may be arranged closer to the active area than the end portion of the contact hole closer to the well region. At a corner portion of the semiconductor substrate, a radius of curvature of an end portion of the contact hole in top view may be greater than a radius of curvature of an end portion of the extension region in top view.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as an “upper” side, and the other side is referred to as a “lower” side. One of two principal surfaces of a substrate, a layer or some other member is referred to as an upper surface, and the other surface is referred to as a lower surface. The “upper” and “lower” directions are not limited to the gravitational direction or directions when the semiconductor device is implemented. In this specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis and Z-axis. In this specification, the X-Y plane is defined as a plane parallel to the upper surface of a semiconductor substrate, and Z-axis is defined to be along a depth direction perpendicular to the upper surface of the semiconductor substrate.

An example where a first conductivity type is n-type and a second conductivity type is p-type is shown in each example embodiment, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the conductivity types of a substrate, a layer, a region and the like in each example embodiment will each be oppositely polarized.

FIG. 1is a cross-sectional view showing an example of a semiconductor device100according to an embodiment of the present invention.FIG. 1shows a cross section taken in a direction perpendicular to the upper surface of a semiconductor substrate10in which the semiconductor device100is formed.

The semiconductor device100includes a semiconductor substrate10. The semiconductor substrate10is a substrate formed of a semiconductor material such as silicon, silicon carbide and gallium nitride. At least part of the semiconductor substrate10may be formed by bulk wafer or epitaxial growth or the like. The semiconductor substrate10includes an (n−)-type drift region18.

In the semiconductor substrate10, an (n+)-type cathode region24having a higher doping concentration than the drift region18is formed between the drift region18and the lower surface of the semiconductor substrate10. The cathode region24is exposed on the lower surface of the semiconductor substrate10. The cathode region24may be formed over the entire lower surface of the semiconductor substrate10, or may be formed in a partial region thereof.

An (n+)-type buffer region20having a higher doping concentration than the drift region18may be formed between the drift region18and the cathode region24. The buffer region20may function as a field stop region to prevent a depletion layer, spreading from the base region14, from reaching the same depth as the cathode region24. The base region14functions as an anode region of a diode.

An upper electrode52is formed above the upper surface of the semiconductor substrate10. The upper electrode52functions as an anode electrode. A lower electrode54is formed on the lower surface of the semiconductor substrate10. The lower electrode54functions as a cathode electrode. The upper electrode52and the lower electrode54are formed of one or more metal materials such as aluminum, copper and tungsten. In this specification, from among the principal surfaces of the semiconductor substrate10, a surface on which the upper electrode52is formed is referred to as an upper surface, and a surface on which the lower electrode54is formed is referred to as a lower surface.

An insulating film26is formed between the upper surface of the semiconductor substrate10and the upper electrode52. The insulating film26may include one or more of an oxide film, a nitride film and silicate glass. A contact hole56penetrating the insulating film26is formed in the insulating film26. The upper electrode52is also formed inside the contact hole56. The upper electrode52is connected to the upper surface of the semiconductor substrate10through the contact hole56.

An active area70, an extension section80and an edge termination region90are formed in the semiconductor substrate10. The active area70is a region in which main current of the semiconductor device100flows. The main current refers to current which flows between the upper electrode52and the lower electrode54, for example. At least a partial region of the active area70operates as a diode such as an FWD. A transistor such as an IGBT may further be formed in the active area70.

A (p+)-type base region14is formed in the upper surface of the semiconductor substrate10in the active area70. The base region14is exposed on the upper surface of the semiconductor substrate10. The base region14is electrically connected to the upper electrode52through the contact hole56.

The edge termination region90is formed closer to the edge of the semiconductor substrate10than the active area70. The edge termination region90relaxes electric field concentration at the end portion of the active area70. On the upper surface of the semiconductor substrate10, the edge termination region90is formed to surround the active area70. The edge termination region90includes one or more (p+)-type well regions94inside the semiconductor substrate10. Each well region94may be exposed on the upper surface of the semiconductor substrate10.

Each well region94may be provided to surround the active area70in a plane parallel to the upper surface of the semiconductor substrate10. The well region94may function as a guard ring to extend the depletion layer, extending from the active area70, to the vicinity of the edge of the semiconductor substrate10in a direction parallel to the upper surface of the semiconductor substrate10.

The well region94is separated from the upper electrode52. The well region94of the present example is not electrically connected to the upper electrode52. The upper surface of the well region94of the present example is covered by the insulating film26.

The edge termination region90may further include one or more metal films92formed above the semiconductor substrate10. The metal film92may be formed of the same material as the upper electrode52. The metal film92may be provided for each well region94. The metal film92is provided to cover the well region94. The metal film92may function as a field plate. The metal film92may be connected to the well region94through a contact hole formed in the insulating film26. The metal film92is provided being separated from the upper electrode52.

The edge termination region90may further include a (p+)-type or (n+)-type channel stopper96at the end portion of the semiconductor substrate10. The insulating film26may be provided on the upper surface of the channel stopper96. The channel stopper96may be connected to the metal film92.

The extension section80is provided between the active area70and the edge termination region90. The extension section80may be provided between an end portion60of the contact hole56closer to the well region94in the active area70and the edge termination region90. In an example, on the upper surface of the semiconductor substrate10, the extension section80may be provided to surround the active area70. InFIG. 1, an end portion of the active area70at which a diode is formed, the extension section80and the edge termination region90are shown.

In this specification, the end portion60of the contact hole56closer to the edge termination region90(an outermost perimeter end of the surface at which the upper electrode52and the surface layer of the front surface of the semiconductor substrate10are in contact) is regarded as the boundary between the active area70and the extension section80. The extension section80includes a (p+)-type extension region30formed extending from the base region14in a direction toward the well region94inside the semiconductor substrate10. The extension region30is separated from the upper electrode52by the insulating film26. The extension region30of the present example is exposed on the upper surface of the semiconductor substrate10. The upper surface of the extension region30is covered by the insulating film26. The upper electrode52may be provided above the extension region30with intervention of the insulating film26.

The extension region30functions as a high-resistance region during operation of the semiconductor device100. By providing the extension region30, implantation of holes from the upper electrode52into the edge termination region90during operation of the semiconductor device100can be suppressed. The concentration of excessive amounts of holes and electrons to be stored in the edge termination region90is reduced, and therefore current which flows from the edge termination region90toward the active area70during reverse recovery operation of the semiconductor device100can be reduced. Thus, current crowding during reverse recovery operation can be mitigated.

When a large hole current flows in the extension region30during reverse recovery operation of the semiconductor device100, the hole concentration p is increased, and thereby the electric charge of acceptors (−NA, where NAis the acceptor concentration) in the extension region30and the electric charge of holes (+p) are cancelled. As a result, the absolute value of the space charge density (|p−NA|) in the extension region30is decreased, so that the space charge becomes near neutral. Thus, the extension region30may become unable to function as a (p+)-type region. In this case, the depletion layer is terminated at the upper surface of the extension section80during reverse recovery of the semiconductor device100, so that electric fields may concentrate at the vicinity of the extension section80.

In the present example, the distance from the end portion60of the contact hole56closer to the well region94to an end portion62of the extension region30closer to the well region94in a plane parallel to the upper surface of the semiconductor substrate10is referred to as a first distance L1. The first distance L1corresponds to the length of the extension region30. Also, the distance from the end portion62of the extension region30closer to the well region94to an end portion64of the well region94closer to the extension region30in a plane parallel to the upper surface of the semiconductor substrate10is referred to as a second distance L2. The distance L1and the distance L2refer to the respective shortest distances. The distance L1and the distance L2may be distances on the same straight line. If a plurality of well regions94are provided, one of the well regions94that is closest to the extension region30is associated with the second distance L2.

In the semiconductor device100, the sum of the first distance L1and the second distance L2is smaller than a thickness Wt of the semiconductor substrate10. In this manner, even if acceptors in the extension region30and holes are cancelled during reverse recovery operation, the depletion layer can be extended from the active area70to the edge termination region90. Accordingly, the reverse recovery withstand capability can be improved. The thickness Wt of the semiconductor substrate10may adopt the average thickness of the edge termination region90. The position of the end portion62of the extension region30may be regarded as the boundary position between the extension section80and the edge termination region90.

FIG. 2illustrates reverse recovery operation of the semiconductor device in the case where the sum of the first distance L1and the second distance L2, L1+L2, is sufficiently greater than the thickness Wt of the semiconductor substrate10. During reverse recovery of the semiconductor device, a large amount of holes are implanted from the edge termination region90to the end portion of the extension region30. As a result, acceptors at the end portion of the extension region30are cancelled by holes, so that the absolute value of the space charge density is decreased and the substantial function of acceptors is depressed. If the concentration of implanted holes is increased, the end portion of the extension region30becomes unable to function as a (p+)-type region. For example, if the concentration of holes implanted into the extension region30is large, a partial region of the extension region30may function as being inverted into an n-type region or a neutral region.

In particular, at the end portion62of the extension region30distanced from the end portion60of the contact hole56, holes are concentratedly implanted from the edge termination region90, and it takes time to extract the implanted holes. Thus, as indicated by dotted line inFIG. 2, the extension region30that can function as a (p+)-type region is temporarily shortened.

FIG. 3shows an example of spread of the depletion layer in the example ofFIG. 2. When the extension region30that can function as a (p+)-type region is shortened as shown inFIG. 2, the distance between the extension region30and the adjacent well region94increases. Thus, the depletion layer102may be contracted toward the active area70or terminated at the upper surface of the semiconductor substrate10between the extension region30and the well region94. In this case, electric fields concentrate between the extension region30and the well region94, and the withstand capability of the semiconductor device is lowered.

FIG. 4illustrates reverse recovery operation of the semiconductor device100in the case where the sum of the first distance L1and the second distance L2, L1+L2, is smaller than the thickness Wt of the semiconductor substrate10. In a manner similar to the example ofFIG. 2, holes are implanted from the edge termination region90into the extension region30during reverse recovery of the semiconductor device100. As a result, the substantial length of the extension region30is temporarily shortened.

FIG. 5shows an example of spread of the depletion layer in the example ofFIG. 4. In the present example, the sum of the first distance L1and the second distance L2, L1+L2, is sufficiently small. By making L1+L2small, a depletion layer102spreading from the base region14and a depletion layer102formed around the well region94adjacent to the base region14can be closely connected to each other even if the substantial length of the extension region30is decreased. In this manner, termination of the depletion layer102between the extension region30and the well region94can be suppressed.

For example, in the vicinity of the upper electrode52, holes implanted into the extension region30can be extracted relatively quickly. Thus, the extension region30can function as a (p+)-type region at least in the vicinity of the upper electrode52. Accordingly, by making the distance L1+L2from the end portion60of the contact hole56to the well region94sufficiently small, exposure of the depletion layer102on the upper surface of the substrate can be suppressed so as to suppress lowering of the withstand capability of the semiconductor device100even if part of the extension region30temporarily becomes unable to function as a (p+)-type region.

Specifically, lowering of the withstand capability of the semiconductor device100can be suppressed by making the distance L1+L2smaller than the thickness Wt of the semiconductor substrate10. The distance L1+L2may be 90% or less, or 80% or less of the thickness Wt of the semiconductor substrate10. The distance L2may be 5 μm or less. Also, the distance L2may be 80% or more and 120% or less of the average interval between well regions94.

The thickness Wt of the semiconductor substrate10varies with the rated voltage of the semiconductor device100. In an example, for the semiconductor device100with a rated voltage of 600 V, the thickness Wt of the semiconductor substrate10is approximately 60 μm. The thickness of the semiconductor substrate10increases as the rated voltage increases. The distance L1+L2may be smaller than 100 μm, may be smaller than 90 μm, or may be smaller than 80 μm.

Note that, if the distance L1+L2is excessively short, the length of the extension region30is restricted, and therefore the effect of suppressing implantation of holes into the edge termination region90may be decreased. The distance L1+L2may be 50% or more, or 70% or more of the thickness Wt of the semiconductor substrate10. Also, the distance L1+L2may be greater than 50 μm, may be greater than 60 μm, or may be greater than 70 μm.

Also, the distance L1is preferably greater than the distance L2. For example, the distance L1may be 5 times or more, ten times or more, or twenty times or more the distance L2. In this manner, the extension region30can be formed to have a sufficient length, so as to improve the effect of suppressing hole implantation into the edge termination region90.

Also, a length L3by which the upper electrode52extends from the end portion60of the contact hole56in a direction toward the well region94on the insulating film26may be 50% or more, or 70% or more of the length L1of the extension region30. By extending the upper electrode52toward the well region94, termination of the depletion layer102between the extension region30and the well region94can be suppressed even if the extension region30is substantially shortened. The length L3may be smaller than the value obtained by subtracting L3from L1+L2.

Also, the doping concentration (acceptor concentration NAin the present example) of the extension region30may be in a range of the following formula. The acceptor concentration NAof the extension region30may be a peak value in the extension region30. Note that Jrate is the rated current density (A/cm2), q is the elementary charge (=1.6e−19(C)), and vsat_Pis the saturation velocity of holes (approximately 7×106to 1×107(cm/sec) in the case of silicon for example, and in an example, 7×106(cm/sec)). In an example, a semiconductor device with a rated voltage of 600 V has a rated current density of approximately 500 A/cm2, and the rated current density decreases as the rated voltage increases. The value of Jrate×30/q·vsat_Pin the following formula is a concentration index of the acceptor concentration of the extension region30. As the density of holes that flow from the edge termination region90toward the extension section80is approximately ten times the rated current density, the concentration index is the value obtained by multiplying its approximate calculation, Jrate×10/q·Vsat_P, by three as a withstand capability margin. Thus, the acceptor concentration NAof the extension region30may be in a range of the following formula with respect to the concentration index:

If the doping concentration of the extension region30is excessively low, the resistance value of the extension region30is increased. In this case, during reverse recovery operation of the semiconductor device100, holes from the edge termination region90concentrate at the end portion60of the contact hole56without passing through the extension region30. Thus, the withstand capability of the semiconductor device100is lowered.

If the doping concentration of the extension region30is excessively high, the resistance value of the extension region30is lowered. In this case, implantation of carriers into the edge termination region90during operation of the semiconductor device100can not be suppressed. Thus, a large amount of holes flow from the edge termination region90toward the active area70during reverse recovery operation of the semiconductor device100, and the reverse recovery withstand capability of the semiconductor device100is lowered.

In contrast, by appropriately setting the doping concentration of the extension region30, holes can be extracted through the extension region30during reverse recovery operation of the semiconductor device100, and implantation of carriers into the edge termination region90during operation of the semiconductor device100can be suppressed. Thus, the withstand capability of the semiconductor device100can be improved.

Note that inversion of the extension region30as described above can be suppressed by increasing the doping concentration of the extension region30. Thus, the value of Jrate×30/q·vsat_Pin the formula may be greater than 1, may be greater than 2, or may be greater than 5.

FIG. 6shows the relationship between the length L1(μm) of the extension region30and the reverse recovery withstand capability Pmax of the semiconductor device100. In the present example, p-type impurities were implanted into the extension region30with a concentration of 1.3×1013/cm2. The example ofFIG. 6shows the characteristics under the condition that the depletion layer is not terminated at the extension section80.

As shown inFIG. 6, the reverse recovery withstand capability Pmax is maximized at 150 (kW) or more when the length L1of the extension region30is in a range of greater than 50 μm and smaller than 100 μm. If the length L1of the extension region30is smaller than 50 μm, the resistance value of the extension region30is increased, and the effect of suppressing hole implantation into the edge termination region90is decreased. Thus, the reverse recovery withstand capability Pmax is lowered. Also, if the length L1of the extension region30is greater than 100 μm, the resistance value of the extension region30is lowered, and current concentrates at the end portion60of the contact hole56during reverse recovery. Thus, the reverse recovery withstand capability Pmax is lowered.

FIG. 7shows the relationship between the concentration (/cm2) of impurities implanted into the extension region30and the reverse recovery withstand capability Pmax of the semiconductor device100. In the present example, the length L1of the extension region30is set to 50 μm. The example ofFIG. 7shows the characteristics under the condition that the depletion layer is not terminated at the extension section80.

As shown inFIG. 7, the reverse recovery withstand capability Pmax is maximized at 150 (kW) or more when the implantation concentration is in a range of 1.3×1013/cm2or more and 6.0×1013/cm2or less. Note that the doping concentration of the extension region30corresponding to the above-mentioned implantation concentration is 5×1016/cm3or more and 3×1017/cm3or less.

If the concentration of impurities implanted into the extension region30is smaller than 1.3×1013/cm2, the resistance value of the extension region30is increased, and the effect of suppressing hole implantation into the edge termination region90is decreased. Also, if the concentration of impurities implanted into the extension region30is greater than 6.0×1013/cm2, the resistance value of the extension region30is lowered, and current concentrates at the end portion60of the contact hole56during reverse recovery. Thus, the reverse recovery withstand capability Pmax is lowered.

Inversion of the extension region30can be suppressed by increasing the doping concentration of the extension region30. Thus, the doping concentration of the extension region30may be made as high as possible unless the resistance value of the extension region30is excessively decreased. The doping concentration of the extension region30may be 7×1016/cm3or more, or may be 1×1017/cm3or more. In this case, the upper limit value of the doping concentration of the extension region30may be 3×1017or less.

FIG. 8is an enlarged view of the vicinity of the extension region30and the well region94. The depth of the lower end of the extension region30and the depth of the well region94, as measured from the upper surface of the semiconductor substrate10, are respectively referred to as D1and D2. The depth D1of the lower end of the extension region30may be the same as the depth D2of the well region94. Note that the depths may be regarded to be the same if the error is within 10%.

Also, the doping concentrations of the extension region30and the well region94may be the same. Note that the doping concentrations may be regarded to be the same if the error is within 10%. The peak value of the doping concentration of each region may be regarded as its doping concentration.

By setting the depths and doping concentrations of the extension region30and the well region94to be the same, it becomes easy to form the extension region30and the well region94in the same process. Thus, the fabrication cost can be reduced. Also, masks for implanting impurities into the extension region30and the well region94can be formed in the same process. Because of this, the alignment error of the mask for the extension region30and the alignment error of the mask for the well region94are not added. Accordingly, the distance margin between the mask for the extension region30and the mask for the well region94can be made small. Thus, the distance L1+L2can be easily made small.

FIG. 9is another example of an enlarged view of the vicinity of the extension region30and the well region94. In the present example, an end portion31of the extension region30opposing the well region94has the same doping concentration and depth as the well region94. A region of the extension region30adjacent to the base region14may have the same doping concentration and depth as the base region14.

FIG. 10Ais a cross-sectional view showing another example of the semiconductor device100. The semiconductor device100of the present example has a different structure of the cathode region24from the semiconductor device100in any aspect described inFIG. 1toFIG. 9. Other structures may be the same as the semiconductor device100in any aspect described with reference toFIG. 1toFIG. 9.

The cathode region24of the present example is selectively formed on the lower-surface side of the semiconductor substrate10. More specifically, the cathode region24is not formed in at least a partial region of the edge termination region90. Note that the cathode region24is formed in at least a partial region of the active area70.

In the present example, the position of an end portion of the cathode region24closer to the edge termination region90in a direction from the active area70toward the edge termination region90is referred to as Xn. If cathode regions24are discretely provided, the position of an end portion the cathode region24closest to the edge termination region90is referred to as Xn.

The position Xn of the end portion of the cathode region24closer to the edge termination region90may be arranged closer to the active area70than a position Xa of the end portion of the well region94closer to the active area70. That is, the cathode region24may not be provided at a position overlapping with the well region94and in a region closer to the end portion of the semiconductor substrate10than the well region94. In this manner, implantation of carriers into the edge termination region90during operation of the semiconductor device100can be suppressed. Thus, the reverse recovery withstand capability of the semiconductor device100can be improved.

The position Xn of the end portion of the cathode region24closer to the edge termination region90may be arranged closer to the active area70than a position Xb of the end portion62of the extension region30closer to the well region94. That is, the cathode region24may not be formed in the edge termination region90. In this manner, implantation of carriers into the edge termination region90can be further suppressed.

The position Xn of the end portion of the cathode region24closer to the edge termination region90may be arranged closer to the active area70than a position Xd of the end portion of the upper electrode52closer to the edge termination region90. Also, it may be arranged closer to the active area70than a position Xc of the end portion of the contact hole56closer to the well region94. That is, the cathode region24may not be formed in the edge termination region90and the extension section80. In this manner, implantation of carriers into the edge termination region90can be further suppressed.

Also, a (p+)-type high-concentration region25which covers part of the upper surface of the cathode region24may be further provided inside the semiconductor substrate10. The high-concentration region25is a floating region which does not contact the lower electrode54. At least part of the high-concentration region25may be formed below the extension region30, and may be formed at the end portion of the active area70. With such a configuration, implantation of carriers into the edge termination region90can be further suppressed.

In the present example, it is effective particularly in the case where the concentration of the base region14is relatively low. Specifically, given a minimum integral of concentration nCof the base region14at which the depletion layer spreading from the p-n junction between the base region14and the drift region18does not punch through to the upper electrode52in the depth direction (direction from the upper surface toward the lower surface), the integral of concentration nAof the base region14may be nCor more and less than thirty times nC, or further, less than ten times nC.

In order for the depletion layer not to punch through to the upper electrode52, the integral of concentration nAof the base region14is to be equal to or greater than the integral of concentration nC. The integral of concentration nCis represented as nC=Ec×(ε0εr/q), wherein Ecis the critical electric field strength at which avalanche breakdown occurs, ε0is the dielectric constant of vacuum, εris the relative dielectric constant of semiconductor, and q is the elementary charge. For example, in the case of silicon, the critical electric field strength Ecis 1.6×105to 2.4×105(V/cm) depending on the donor concentration of the drift region18, and therefore the integral of concentration nCis approximately 1.1×1012to 1.6×1012(/cm2). On the other hand, in order for the reverse recovery characteristics of the diode to be of soft recovery, it is necessary to reduce implantation of minority carriers (holes in the present example), and therefore it is desired to reduce the integral of concentration nAof the base region14to be as small as possible. In order for that, the integral of concentration nAof the base region14may be nCor more (1.6×1012(/cm2) or more) and less than thirty times nC(less than 4.8×1013(/cm2)), or further, less than ten times nC(less than 1.6×1013(/cm2)), as described above. In view of the above, the peak concentration of the base region14may be 1.0×1016(/cm3) or more and 5.4×1017(/cm3) or less, depending on the junction depth. Otherwise, it may be in a range as previously described above. If the base region14has such a low concentration, the extension region30which is formed with the same concentration and depth as the base region14has a further significantly improved reverse recovery withstand capability by virtue of the configuration in the present example.

If the base region14has such as low concentration, the base region14may be formed to have substantially the same junction depth in a region where the upper electrode52and the front surface of the semiconductor substrate10are in contact, in order to prevent punch-through of the depletion layer to the anode electrode. The word “substantially” means, for example, that the junction depth may have a distribution of within 10% in view of the fact that roughness is present in the front surface of the semiconductor substrate10in a region where the active area70is formed. Also, for example, if a plurality of trenches are formed in a region where the upper electrode52and the front surface of the semiconductor substrate10are in contact, the junction depth of the base region14may have a distribution of within 10% inside mesa regions sandwiched by the trenches. Furthermore, the junction depth of the base region14may have a distribution of within 10% among a plurality of mesa regions. In other words, the base region14may be formed with a substantially uniform junction depth in a region where the upper electrode52and the front surface of the semiconductor substrate10are in contact. In this manner, punch-through of the upper electrode52to the depletion layer to increase leakage current can be suppressed.

FIG. 10Bis a cross-sectional view showing another example of the semiconductor device100. The semiconductor device100of the present example further includes a high-concentration region66in addition to the structure of semiconductor device100described with reference toFIG. 10A. WhileFIG. 10Ashows the semiconductor device100in which the buffer region20is in contact with the lower electrode54,FIG. 10Bshows the semiconductor device100in which the high-concentration region66is provided between the buffer region20and the lower electrode54.

The high-concentration region66of the present example is of (p+)-type. The doping concentration of the high-concentration region66may be the same as the doping concentration of the high-concentration region25. The high-concentration region66may be provided at the same depth position as the cathode region24. By providing the high-concentration region66, implantation of carriers into the edge termination region90can be further suppressed.

FIG. 11shows an overview of the structure of the upper surface of the semiconductor device100. The semiconductor device100includes a semiconductor substrate10. Note that, pads provided on the upper surface of the semiconductor substrate10are omitted inFIG. 11. In this specification, the end portion of the outer perimeter of the semiconductor substrate10in top view is referred to as an outer perimeter end150. The top view refers to the view as seen in parallel with the Z-axis from the upper-surface side of the semiconductor substrate10.

The semiconductor device100includes an active area70and an edge termination region90. As described above, a diode is provided in the active area70. A transistor may further be provided in the active area70. The active area70can be regarded as a region where the upper electrode52is provided in top view of the semiconductor substrate10, and a region sandwiched by regions where the upper electrode52is provided.

The edge termination region90is provided between the active area70and the outer perimeter end150of the semiconductor substrate10on the upper surface of the semiconductor substrate10. An extension region30is provided between the edge termination region90and the active area70. The edge termination region90and the extension region30may be arranged in an annular manner to surround the active area70on the upper surface of the semiconductor substrate10. The edge termination region90of the present example is arranged along the outer perimeter end150of the semiconductor substrate10. The edge termination region90and the extension region30are formed in a curved line at corner portions110of the semiconductor substrate10in top view.

FIG. 12shows the upper surface of a corner portion110. InFIG. 12, a cross section120of the structure which corresponds to the corner portion110and is provided on the upper-surface side of the semiconductor substrate10is shown together. In the present example, at the corner portion110, the radius of curvature of an end portion60of the contact hole56in top view is greater than the radius of curvature of an end portion62of the extension region30in top view. The end portion60and the end portion62are end portions closer to the outer perimeter end150of the semiconductor substrate10from among the end portions of the contact hole56and the extension region30.

Carriers stored in the drift region18and the like flow toward the active area70during reverse recovery of the diode. Carriers in the vicinity of the corner portion110concentratedly flow into the contact hole56at the corner portion110, so that the reverse recovery withstand capability of the corner portion110is lowered. In contrast, by increasing the radius of curvature of the contact hole56, the length of the contact hole56at the corner portion110in top view can be increased. Thus, the current density of the end portion of the contact hole56per unit length can be reduced, so that the reverse recovery withstand capability can be improved.

InFIG. 12, an end portion122of the contact hole56in the case where it has the same radius of curvature as the end portion62of the extension region30is indicated by dashed line. The length of the curved region of the end portion of the contact hole56can be increased by further increasing its radius of curvature as of the end portion60. Current is likely to concentrate at the curved region of the end portion of the contact hole56, and therefore the current concentration can be mitigated by making the curved portion longer.

An arc center O1′ of the end portion60of the contact hole56is arranged to be off toward the inside of the semiconductor substrate10relative to an arc center O1of the imaginary end portion122. A region where the edge termination region90is formed in a straight line in top view is referred to as a linear portion111. A length L1′ of the extension region30in the corner portion110may be greater than a length L1of the extension region30in the linear portion111. The length L1′ of the extension region30in the corner portion110may adopt the maximum length of the extension region30in the corner portion110. The length of the extension region30is a length in a direction orthogonal to the end portion60in top view. The length L1′ may be 1.1 times or more, 1.2 times or more, or 1.5 times or more the length L1.

Also, the distance between the extension region30and the well region94in the corner portion110is referred to as L2′. The distance L2′ may adopt the maximum distance between the extension region30and the well region94in the corner portion110. The distance is a distance in a direction orthogonal to the end portion62in top view. The sum of the length L1′ and the distance L2′ in the corner portion110may be greater than the sum of the length L1and the distance L2in the linear portion111.

At the corner portion110, the radius of curvature of the end portion60of the contact hole56may be greater than the radius of curvature of an end portion123of the upper electrode52. The end portion123of the upper electrode52is an end portion closer to the outer perimeter end150of the semiconductor substrate10. At the corner portion110, the radius of curvature of the end portion60of the contact hole56may be greater than the radius of curvature of the end portion64of the well region94. The end portion64of the well region94is the end portion of the well region94that is closest to the active area70, end portion which is closer to the active area70.

The positive space charge density of the extension region30may be smaller in the corner portion110than in the linear portion111. By increasing the radius of curvature of the contact hole56at the corner portion110, the acceptor concentration of the corner portion110can be saved, so that exposure of the depletion layer102on the upper surface of the substrate is suppressed so as to suppress lowering of the withstand capability of the semiconductor device100even if part of the extension region30temporarily becomes unable to function as a (p+)-type region.

FIG. 13shows an overview of the structure of the upper surface of a semiconductor device200according to another example embodiment. The semiconductor device200is different from the semiconductor device100in that it includes a transistor region72and a diode region82in the active area70. Also, the semiconductor device200includes a gate pad116, a gate runner48and a gate metal layer50. Other structures may be the same as the semiconductor device100.

The transistor region72includes a transistor such as an IGBT. The diode region82is arranged alternately with the transistor region72in a predetermined X-axis direction on the upper surface of the semiconductor substrate10. In this specification, the X-axis direction may be referred to as an array direction.

In each diode region82, an (n+)-type cathode region24is provided in a region contacting the lower surface of the semiconductor substrate10. In the semiconductor device200of the present example, a region which is in contact with the lower surface of the semiconductor substrate10and is not in the cathode region is a (p+)-type collector region.

The diode region82is a region where the cathode region24is projected in the Z-axis direction. The transistor region72is a region where the collector region is formed on the lower surface of the semiconductor substrate10and a unit structure including an (n+)-type emitter region is periodically formed on the upper surface of the semiconductor substrate10. The boundary between the diode region82and the transistor region72in the X-axis direction is the boundary between the cathode region24and the collector region. In this specification, the diode region82also includes a region which is extended from the region where the cathode region24is projected in the Z-axis direction and reaches the end portion of the active area70in the Y-axis direction (indicated by the dashed line extended from the solid line of the cathode region24in the Y-axis direction inFIG. 13).

The transistor region72may be provided at both ends of the active area70in the X-axis direction. The active area70may be divided in the Y-axis direction by the gate runner48. The transistor region72and the diode region82are arranged alternately in the X-axis direction in each divided region of the active area70.

The gate metal layer50is provided between the edge termination region90and the active area70on the upper surface of the semiconductor substrate10. Although an interlayer insulating film is provided between the gate metal layer50and the semiconductor substrate10, it is omitted inFIG. 13.

The gate metal layer50may be provided to surround the active area70in top view of the semiconductor substrate10. The gate metal layer50is electrically connected to the gate pad116provided outside the active area70. The gate pad116may be arranged between the gate metal layer50and the active area70. A pad electrically connected to the upper electrode52may be provided between the gate metal layer50and the active area70.

The gate metal layer50may be formed of aluminum or an aluminum-silicon alloy. The gate metal layer50is electrically connected to the transistor region72, and supplies a gate voltage to the transistor region72.

The gate runner48is electrically connected to the gate metal layer50, and extends to above the active area70. At least one gate runner48may be provided to traverse the active area70in the X-axis direction. The gate runner48supplies a gate voltage to the transistor region72. The gate runner48may be formed of a semiconductor material such as polysilicon doped with impurities, or may be formed of metal. The gate runner48is formed above or inside the semiconductor substrate10, and the semiconductor substrate10and the gate runner48are insulated from each other by an insulating film.

FIG. 14is an enlarged view of the vicinity of a region130inFIG. 13. The semiconductor device200of the present example includes a gate trench portion43, a dummy trench portion33, an extension region30, an (n+)-type emitter region12, a (p−)-type base region14and a (p+)-type contact region15, which are provided inside the semiconductor substrate10and are exposed on the upper surface of the semiconductor substrate10. In this specification, the gate trench portion43or the dummy trench portion33may be simply referred to as a trench portion. Also, the semiconductor device200of the present example includes an upper electrode52, a gate metal layer50and a metal film92, which are provided above the upper surface of the semiconductor substrate10. The metal film92, the upper electrode52and the gate metal layer50are provided being separated from each other.

The edge termination region90is arranged outside (in the positive Y-axis direction) the gate metal layer50. The edge termination region90may include one or more metal films92as described above. Also, although the well region94is provided inside the semiconductor substrate10below the metal film92, it is omitted inFIG. 14. The metal film92and the well region94are provided in an annular manner to surround the active area70outside the gate metal layer50.

Although an insulating film26is formed between the upper surface of the semiconductor substrate10and each of the metal film92, the upper electrode52and the gate metal layer50, it is omitted inFIG. 14. In the insulating film26of the present example, a contact hole56is formed to penetrate the insulating film26.

The upper electrode52contacts the emitter region12, the contact region15and the base region14on the upper surface of the semiconductor substrate10through the contact hole56. Also, the upper electrode52is connected to a dummy conductive portion in the dummy trench portion33through the contact hole56. A connection portion36formed of a conductive material such as polysilicon doped with impurities may be provided between the upper electrode52and the dummy conductive portion. An insulating film such as an oxide film is formed between the connection portion36and the upper surface of the semiconductor substrate10.

The gate metal layer50contacts the gate runner48through the contact hole56. At the end portion of the active area70, the gate metal layer50and the gate trench portion43may be connected without intervention of the gate runner48.

The gate runner48is formed of polysilicon doped with impurities or the like. The gate runner48is connected to a gate conductive portion in the gate trench portion43at the upper surface of the semiconductor substrate10. The gate runner48is not connected to the dummy conductive portion in the dummy trench portion33. The gate runner48of the present example is formed from below the contact hole56to an edge portion41of the gate trench portion43.

An insulating film such as an oxide film is formed between the gate runner48and the upper surface of the semiconductor substrate10. At the edge portion41of the gate trench portion43, the gate conductive portion is exposed on the upper surface of the semiconductor substrate10. A contact hole to connect the gate conductive portion and the gate runner48is provided in the insulating film above the gate conductive portion. Note that, although the upper electrode52and the gate runner48do not overlap with each other in plan view inFIG. 14, the upper electrode52and the gate runner48may overlap with each other. In this case, an insulating film is provided between the upper electrode52and the gate runner48.

The upper electrode52and the gate metal layer50are formed of a metal-containing material. For example, at least a partial region of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may include a barrier metal formed of titanium, a titanium compound or the like as an underlayer of a region formed of aluminum or the like, and may include a plug formed of tungsten or the like in the contact hole.

One or more gate trench portions43and one or more dummy trench portions33are arrayed at predetermined intervals along a predetermined array direction (the X-axis direction in the present example) on the upper surface of the semiconductor substrate10. In the transistor region72of the present example, one or more gate trench portions43and one or more dummy trench portions33are formed alternately along the array direction.

A gate trench portion43of the present example may have two linear portions39extending in a straight line along the longitudinal direction perpendicular to the array direction (the Y-axis direction in the present example) and an edge portion41to connect the two linear portions39. At least part of the edge portion41is preferably formed in a curved line on the upper surface of the semiconductor substrate10. The edge portion41connects the end portions of the two linear portions39of the gate trench portion43to each other, the end portions being ends of their linear shapes along the longitudinal direction. Thereby, electric field concentration at the end portions of the linear portions39can be relaxed. In this specification, each linear portion39of the gate trench portion43may be regarded as one gate trench portion43.

At least one dummy trench portion33is provided between linear portions39of the gate trench portion43. Each dummy trench portion33may have linear portions29and an edge portion35in a manner similar to the gate trench portion43. In another example, the dummy trench portion33may have a linear portion29and no edge portion35. In the example shown inFIG. 14, two linear portions29of the dummy trench portion33are arranged between two linear portions39of the gate trench portion43in the transistor region72.

In the diode region82, a plurality of dummy trench portions33are arranged along the X-axis direction on the upper surface of the semiconductor substrate10. The shape of a dummy trench portion33in the X-Y plane in the diode region82may be similar to a dummy trench portion33provided in the transistor region72.

The edge portion35and the linear portions29of a dummy trench portion33have shapes similar to the edge portion41and the linear portions39of a gate trench portion43. A dummy trench portion33provided in the diode region82and a linear-shaped dummy trench portion33provided in the transistor region72may have the same length in the Y-axis direction.

The upper electrode52is formed above the gate trench portion43, the dummy trench portion33, the extension region30, the emitter region12, the base region14and the contact region15. The extension region30and one of the longitudinal-direction ends of the contact hole56, one which is closer to the position where the gate metal layer50is provided, are provided being distanced from each other in the X-Y plane. The diffusion depth of the extension region30may be greater than the depths of the gate trench portion43and the dummy trench portion33. Partial regions of the gate trench portion43and the dummy trench portion33closer to the gate metal layer50are formed in the extension region30. The bottom portion of the edge portion41of the gate trench portion43in the Z-axis direction and the bottom portion of the edge portion35of the dummy trench portion33in the Z-axis direction may be covered by the extension region30.

One or more mesa portions61sandwiched by trench portions are provided in each of the transistor region72and the diode region82. A mesa portion61refers to a region of the semiconductor substrate10that is sandwiched by trench portions and is closer to the upper surface than the deepest bottom portion of the trench portions.

A base region14is formed in a mesa portion61sandwiched by trench portions. The base region14is a second conductivity-type ((p−)-type) region having a lower doping concentration than the extension region30.

A second conductivity-type contact region15having a higher doping concentration than the base region14is formed on the upper surface of the base region14in the mesa portion61. The contact region15of the present example is of (p+)-type. On the upper surface of the semiconductor substrate10, the extension region30may be formed being distanced, in a direction toward the gate metal layer50, from one of contact regions15that is arranged at the outermost end in the Y-axis direction. The base region14is exposed on the upper surface of the semiconductor substrate10between the extension region30and the contact region15.

In the transistor region72, a first conductivity-type emitter region12having a higher doping concentration than the drift region formed inside the semiconductor substrate10is selectively formed on the upper surface of a mesa portion61-1. The emitter region12of the present example is of (n+)-type. In the base region14adjacent to the emitter region12in the depth direction of the semiconductor substrate10(negative Z-axis direction), a portion contacting the gate trench portion43functions as a channel portion. When an ON voltage is applied to the gate trench portion43, a channel which is an inversion layer of electrons is formed at a portion adjacent to the gate trench portion43in the base region14provided between the emitter region12and the drift region in the Z-axis direction. The channel formed in the base region14allows carriers to flow between the emitter region12and the drift region.

In the present example, base regions14-eare arranged at both end portions of each mesa portion61in the Y-axis direction. In the present example, on the upper surface of each mesa portion61, a region adjacent to a base region14-eon the center side of the mesa portion61is the contact region15. Also, a region contacting a base region14-eon the opposite side to the contact region15is the extension region30.

In a mesa portion61-1in the transistor region72of the present example, the contact region15and the emitter region12are arranged alternately along the Y-axis direction in a region sandwiched by base regions14-eat both ends in the Y-axis direction. Each of the contact region15and the emitter region12is formed from one of adjacent trench portions to the other trench portion.

In one or more mesa portions61-2provided at the boundary with the diode region82from among the mesa portions61in the transistor region72, a contact region15having a larger area than a contact region15in a mesa portion61-1is provided. The emitter region12may not be provided in a mesa portion61-2. In a mesa portion61-2of the present example, a contact region15is provided in the entire region sandwiched by base regions14-e.

In each mesa portion61-1in the transistor region72of the present example, a contact hole56is formed above the regions of contact regions15and emitter regions12. In a mesa portion61-2, a contact hole56is formed above the contact region15. In each mesa portion61, the contact hole56is not formed in regions corresponding to the base regions14-eand the extension region30. The contact holes56of the respective mesa portions61in the transistor region72may have the same length in the Y-axis direction.

In the diode region82, an (n+)-type cathode region24is formed in a region in contact with the lower surface of the semiconductor substrate10. InFIG. 14, a region where the cathode region24is formed is indicated by dashed line. A (p+)-type collector region may be formed in a region where the cathode region24is not formed in a region in contact with the lower surface of the semiconductor substrate10.

The transistor region72may be a region where mesa portions61having formed therein the contact region15and the emitter region12and trench portions adjacent to the mesa portions61are provided in a region overlapping with the collector region in the Z-axis direction. However, in a mesa portion61-2at the boundary with the diode region82, a contact region15may be provided instead of the emitter region12.

A base region14is arranged on the upper surface of a mesa portion61-3in the diode region82. However, a contact region15may be provided in a region adjacent to a base region14-e. The contact hole56is terminated above the contact region15. Note that, while the diode region82includes five mesa portions61-3and seven dummy trench portions33sandwiching the mesa portions61-3in the example ofFIG. 14, the number of mesa portions61-3and the number of dummy trench portions33in the diode region82are not so limited. A greater number of mesa portions61-3and dummy trench portions33may be provided in the diode region82.

FIG. 15shows an example of a cross section taken along A-A inFIG. 13. The cross section taken along A-A is an X-Z cross section including a transistor region72and the edge termination region90. The structure of the edge termination region90is the same as the structure of the edge termination region90in any aspect described with reference toFIG. 1toFIG. 10B. However, in at least part of a region contacting the lower surface of the semiconductor substrate10in the edge termination region90, a cathode region24may be provided instead of the collector region22.

The transistor region72includes, in the cross section, the semiconductor substrate10, the insulating film26, the upper electrode52and the lower electrode54. The insulating film26is formed to cover at least part of the upper surface of the semiconductor substrate10. Through holes such as a contact hole56are formed in the insulating film26. The contact hole56exposes the upper surface of the semiconductor substrate10.

The upper electrode52is formed on the upper surfaces of the semiconductor substrate10and the insulating film26. The upper electrode52is also formed inside the contact hole56, and contacts the upper surface of the semiconductor substrate10exposed by the contact hole56. The lower electrode54is formed on the lower surface of the semiconductor substrate10. The lower electrode54may contact the entire lower surface of the semiconductor substrate10.

In the transistor region72, a (p−)-type base region14is formed in the semiconductor substrate10on its upper-surface side. An (n−)-type drift region18is arranged below the base region14inside the semiconductor substrate10. Each trench portion is provided from the upper surface of the semiconductor substrate10to penetrate the base region14and reach the drift region18.

In the cross section, in each mesa portion61-1of the transistor region72, an (n+)-type emitter region12and a (p−)-type base region14are arranged in this order from the upper-surface side of the semiconductor substrate10. Note that, in an X-Z cross section passing through a contact region15in the transistor region72, a contact region15is provided in each mesa portion61-1of the transistor region72instead of an emitter region12. The contact region15may function as a latch-up suppression layer to suppress latch-up.

In the transistor region72, a (p+)-type collector region22is provided in a region adjacent to the lower surface of the semiconductor substrate10. In the semiconductor substrate10of the present example, an (n+)-type buffer region20is provided between the drift region18and the collector region22and between the drift region18and the cathode region24. The doping concentration of the buffer region20is higher than the doping concentration of the drift region18. The buffer region20may function as a field stop layer to prevent a depletion layer, spreading from the lower-surface side of the base region14, from reaching the (p+)-type collector region22and the (n+)-type cathode region24.

One or more gate trench portions43and one or more dummy trench portions33are formed in the semiconductor substrate10on its upper-surface side. Each trench portion extends from the upper surface of the semiconductor substrate10, penetrates the base region14and reaches the drift region18. In a region where an emitter region12or a contact region15is provided, each trench portion also penetrates the region and reaches the drift region18. That a trench portion penetrates a doping region does not necessarily mean that fabrication is performed in the order of forming a doping region and subsequently forming a trench portion. That a trench portion penetrates a doping region also means that trench portions are formed and subsequently a doping region is formed between the trench portions.

A gate trench portion43includes a gate trench, a gate insulating film42and a gate conductive portion44, which are formed in the semiconductor substrate10on its upper-surface side. The gate insulating film42is formed to cover the inner wall of the gate trench. The gate insulating film42may be formed by oxidizing or nitriding the semiconductor material of the inner wall of the gate trench. The gate conductive portion44is formed inside the gate trench on an inner side relative to the gate insulating film42. That is, the gate insulating film42insulates the gate conductive portion44and the semiconductor substrate10from each other. The gate conductive portion44is formed of a conductive material such as polysilicon.

The gate conductive portion44at least includes a region opposing an adjacent base region14with intervention of the gate insulating film42in the depth direction. In the cross section, the gate trench portion43is covered by the insulating film26on the upper surface of the semiconductor substrate10. When a predetermined voltage is applied to the gate conductive portion44, a channel as an inversion layer of electrons is formed in the interfacial surface layer of the base region14in contact with the gate trench.

In the cross section, a dummy trench portion33may have the same structure as a gate trench portion43. A dummy trench portion33has a dummy trench, a dummy insulating film32and a dummy conductive portion34, which are formed in the semiconductor substrate10on its upper-surface side. The dummy insulating film32is formed to cover the inner wall of the dummy trench. The dummy conductive portion34is formed inside the dummy trench and formed on an inner side relative to the dummy insulating film32. The dummy insulating film32insulates the dummy conductive portion34and the semiconductor substrate10from each other. The dummy conductive portion34may be formed of the same material as the gate conductive portion44. For example, the dummy conductive portion34is formed of a conductive material such as polysilicon. The dummy conductive portion34may have the same length as the gate conductive portion44in the depth direction. In the cross section, the dummy trench portion33is covered by the insulating film26on the upper surface of the semiconductor substrate10. Note that the bottom portions of the dummy trench portion33and the gate trench portion43may have a shape of a curved surface (a curved line in the cross section) that is downwardly convex.

An extension region30may be provided at the end portion of the transistor region72closer to the extension section80. The extension region30is formed to a greater depth than the base region14. The extension region30of the present example is formed to a greater depth than each trench portion. At least one trench portion in the transistor region72may be formed in the extension region30.

A contact hole56to connect the extension region30and the upper electrode52is provided in the insulating film26in the transistor region72. The contact hole56may extend in a straight line in the Y-axis direction. In the X-axis direction, the distance between the end portion60of the contact hole56provided closest to the extension section80and the end portion62of the extension region30is equivalent to the first distance L1.

A gate metal layer50, an insulating film26, a gate runner48and an extension region30are provided in the extension section80. The gate metal layer50is provided above the upper surface of the semiconductor substrate10. The insulating film26is provided between the gate metal layer50and the semiconductor substrate10.

The gate runner48is provided between the gate metal layer50and the semiconductor substrate10. The insulating film26is provided between the gate runner48and the gate metal layer50and between the gate runner48and the semiconductor substrate10. The gate runner48and the gate metal layer50are connected to each other through a contact hole56provided in the insulating film26. The gate metal layer50may be formed inside the contact hole56.

The extension region30is provided below the gate metal layer50and the gate runner48. In the X-axis direction, the range in which the extension region30is provided is preferably wider than the range in which the gate metal layer50and the gate runner48are provided.

In the present example as well, the sum of the first distance L1and the second distance L2may be smaller than the thickness Wt of the semiconductor substrate10. In this manner, even if acceptors and holes in the extension region30are cancelled during reverse recovery operation, the depletion layer can be extended from the active area70to the edge termination region90. Accordingly, the reverse recovery withstand capability can be improved. Note that the first distance L1and the second distance L2shown inFIG. 15may satisfy the same condition as the first distance L1and the second distance L2as described with reference toFIG. 1toFIG. 10B.

FIG. 16shows an example of a cross section taken along B-B inFIG. 13. The cross section taken along B-B is a Y-Z cross section including a diode region82and the edge termination region90. The cross section passes through the contact hole56in the diode region82. The structure of the edge termination region90is the same as the structure of the edge termination region90in any aspect described with reference toFIG. 1toFIG. 10B.

The diode region82has a structure similar to the active area70as described with reference toFIG. 1toFIG. 10B. However, in the example ofFIG. 16, the base region14is formed to a shallower position than the extension region30.

In the extension section80of the present example, a gate metal layer50and a gate runner48are provided in addition to the structure of the extension section80shown inFIG. 1. In the Y-axis direction, the distance between the end portion60of the contact hole56of the diode region82and the end portion62of the extension region30is referred to as a first distance L10. In the Y-axis direction, the distance between the end portion62of the extension region30and the end portion64of the well region94is referred to as a second distance L20. The sum of the first distance L10and the second distance L20may be smaller than the thickness Wt of the semiconductor substrate10. In this manner, even if acceptors and holes in the extension region30are cancelled during reverse recovery operation, the depletion layer can be extended from the active area70to the edge termination region90. Accordingly, the reverse recovery withstand capability can be improved. Note that the first distance L10and the second distance L20shown inFIG. 16may satisfy the same condition as the first distance L1and the second distance L2as described with reference toFIG. 1toFIG. 10B.

Also, in the Y-axis direction, the distance between an end portion67of the cathode region24and the end portion60of the contact hole56is referred to as L30. The distance L30may be smaller than the distance L10. Also, the distance between an end portion63of the upper electrode52in the X-axis direction and the end portion60of the contact hole56as shown inFIG. 15is referred to as L4, and the distance between an end portion63of the upper electrode52in the Y-axis direction and the end portion60of the contact hole56as shown inFIG. 16is referred to as L40. The distance L40may be greater than the distance L4. Note that, also in a Y-Z cross section passing through a contact hole56in the transistor region72, distances such as the first distance L10and the second distance L20may satisfy the same conditions of the distances described with reference toFIG. 16.

FIG. 17shows another example of a corner portion110. The corner portion110of the present example includes a plurality of trench portions such as a dummy trench portion33and contact holes56arranged between the trench portions, in the active area70.

In the Y-axis direction, a line connecting the tips of the respective trench portions is referred to as a curved line128, and a line connecting the tips of the contact holes56is referred to as a curved line126. The radius of curvature of the curved line126may be greater than the radius of curvature of the curved line128. By increasing the radius of curvature of the curved line126for the contact holes56, current concentration at the end portions of the contact holes56at the corner portion110can be mitigated. The radius of curvature of the curved line126may be greater than the radius of curvature of an end portion65of the gate metal layer50closer to the active area70.

The positive space charge density of the base region14in a mesa portion61sandwiched by trench portions may be smaller in the corner portion110than in the linear portion111. As above, the acceptor concentration of the base region14at the corner portion110is saved by increasing the length from the end portion of a trench to the end portion of the contact hole56at the corner portion110. In this manner, even if part of the base region14temporarily becomes unable to function as a (p+)-type region, exposure of the depletion layer102on the upper surface of the substrate can be suppressed so as to suppress lowering of the withstand capability of the semiconductor device100.