Interface layer between dual polycrystalline silicon layers

A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices and, more particularly, to fabricating an interface layer between dual polycrystalline silicon layers in semiconductor devices.

BACKGROUND ART

Dual polycrystalline silicon layers may be formed adjacent one another in various different types of semiconductor devices, including, for example, certain types of non-volatile memory devices. As shown inFIG. 1, formation of dual polycrystalline silicon layers typically involves the deposition of a first polycrystalline silicon layer110on an underlying layer105and then optional processing (not shown) of layer110to form various device structures (e.g., gates, etc.). Layer110may then be cleaned in an attempt to remove oxides and impurities, followed by an optional anneal at a high temperature to attempt to further remove oxides on layer110. A second polycrystalline silicon layer115may then be deposited over layer110. The cleaning and annealing processes, however, may not remove all oxides and impurities at the surface of layer110, and residual oxide clusters120may be present on the surface of layer110prior to deposition of layer115, thus, causing an imperfect interface130between polycrystalline silicon layers110and115.

In the case wherein layer110is processed to produce a gate structure prior to formation of the second polycrystalline silicon layer, dopants for the gate are typically implanted into the top of the gate (i.e., into the upper surface of layer110). In some circumstances, the dopants may cluster125at the surface of layer110, thus, creating an undesirable depletion region at the interface130between layers110and115.

DISCLOSURE OF THE INVENTION

According to an aspect of the invention, a method may include forming a first layer of polycrystalline silicon and cleaning a surface of the first layer. The method may further include forming an interface layer over the surface of the first layer, where the interface layer comprises a metal or alloy that can react with a silicon to form a silicide. The method may also include forming a second layer of polycrystalline silicon over the interface layer.

According to another aspect of the invention, a method of forming an interface between dual polycrystalline silicon layers may include forming a first layer of polycrystalline silicon. The method may further include forming a metal interface layer on the first layer of polycrystalline silicon and forming a second layer of polycrystalline silicon on the metal interface layer.

According to a further aspect of the invention, a structure for interfacing dual polycrystalline silicon layers may include a first layer of polycrystalline silicon having a first surface. The structure may further include a metal interface layer formed on the first surface of the first layer of polycrystalline silicon, the metal interface layer having a second surface and having a thickness ranging from about 10 Å to about 500 Å. The structure may also include a second layer of polycrystalline silicon formed on the second surface of the interface layer.

Other advantages and features of the invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.

BEST MODE FOR CARRYING OUT THE INVENTION

Consistent with aspects of the invention, an interface layer may be formed between dual polycrystalline silicon layers when fabricating one or more semiconductor devices. The interface layer may include titanium, cobalt or nickel and, via a thermal cycling process, may be reacted with the polycrystalline silicon layers to produce silicide regions between the interface layer and each polycrystalline silicon layer. The interface layer, thus, provides an improved bond between the dual polycrystalline silicon layers that further has an improved electrical contact as compared to existing polysilicon-to-polysilicon interfacing techniques.

FIG. 2illustrates a cross-section of a first polycrystalline silicon layer205formed over an underlying layer210according to an exemplary embodiment of the invention. Underlying layer210may include any type of layer used in various semiconductor devices, such as a layer of dielectric material, a metal layer, or a layer of semiconducting material. Polycrystalline silicon layer205may be formed, for example, using existing deposition processes. The thickness of polycrystalline silicon layer205may range, for example, from about 100 Å to about 3,000 Å. Layer205may, optionally, be processed, as appropriate, to fabricate necessary structures for the eventual semiconductor device. In one implementation, for example, such processing may include implanting dopants into layer205to form a gate structure. Surface215of layer205may then be cleaned using existing oxide and/or impurity removal cleaning processes. In one implementation, cleaning of surface215of layer205may include a wet clean process using hydrofluoric acid (HF).

As shown inFIG. 3, an interface layer305may be formed on polycrystalline silicon layer205. Interface layer305may include any type of metal or alloy that can react with silicon to form a silicide. For example, interface layer305may include titanium (Ti), cobalt (Co) or nickel (Ni), the above metals combined with other materials (e.g., CoRe, etc.), or alloys of the above metals. Interface layer305may be formed using, for example, existing deposition processes, though other layer formation processes may be used. The thickness of interface layer305may range, for example, from about 10 Å to about 500 Å.

A second polycrystalline silicon layer405may be formed on interface layer305, as shown inFIG. 4. Layer405may be formed, for example, using existing deposition processes. The thickness of polycrystalline silicon layer405may range, for example, from about 100 Å to about 3,000 Å.

As shown inFIG. 5, subsequent to formation of layer405, layers205,305and405may be subjected to a thermal cycle510such that interface layer305reacts with polycrystalline silicon layers205and405. The thermal cycle may range from a low temperature of about 300 degrees Celsius to a high temperature of about 900 degrees Celsius over a period of time ranging from about 1 second to about 12 hours. The thermal cycle510may be inherently produced as a by-product of subsequent device fabrication processes, or may be a specifically implemented step for the purpose of reacting interface layer305with layers205and405. Subjecting layers205,305and405to the thermal cycle may cause the polycrystalline silicon in layers205and405to react with the material of interface layer305to form silicide regions505between interface layer305and each of layers205and405. For example, if interface layer305includes titanium, thermal cycling produces silicide regions505that include titanium silicide (TiSi). If interface layer305includes cobalt, thermal cycling produces silicide regions505that include cobalt silicide (CoSi). If interface layer305includes nickel, thermal cycling produces silicide regions505that include nickel silicide (NiSi). Silicide regions505may be formed to a thickness ranging from about 50 Å to about 1,000 Å. Layers205and405bond well to interface layer305and silicide regions505, thus, providing an improved interface between dual polycrystalline silicon layers205and405that has a good electrical contact.

An interface layer between dual polycrystalline silicon layers, as described above with respect toFIGS. 2-5, may be used in any type of semiconductor device where it is desired to interface a first polycrystalline silicon layer with a second polycrystalline silicon layer.FIGS. 6A and 6Bdepict one exemplary implementation in which the interface layer of the present invention is used in an array of silicon-oxide-nitride-oxide-silicon (SONOS) type memory cells600. As shown inFIGS. 6A and 6B, an array of memory cells600may include an oxide-nitride-oxide (ONO) stack605formed over, for example, a substrate610. Gate structures205, formed from a layer of polycrystalline silicon, may be formed at intervals over the ONO stack605. A source region620and a drain region625may be formed underneath respective sides of a corresponding gate structure205, with a channel region630being disposed between each source620and drain625region. Dielectric mesas615may be formed between gate structures205to insulate the gate structures205from one another. A layer305, formed as described above with respect toFIGS. 2-5, may be formed over each gate structure205as an interface to a second layer405of polycrystalline silicon formed over each gate structure205. The second layer405of polycrystalline silicon may form multiple wordlines for the memory array.

Substrate610, consistent with one aspect, may include a crystal silicon wafer. In other implementations, substrate610may include a gallium arsenide layer, a silicon-on-insulator structure, a silicon-germanium layer, or other conventional materials used to form a semiconductor substrate. A bottom oxide of ONO stack605layer may be formed on substrate610. The bottom oxide layer may be formed on substrate610using, for example, existing deposition processes, such as a chemical vapor deposition (CVD) process. The bottom oxide layer may include oxide materials, such as, for example, silicon oxide, or silicon oxynitride. The thickness of the bottom oxide layer may range, for example, from about 35 Å to about 70 Å.

A charge storage layer of ONO stack605may be formed on the bottom oxide layer using, for example, existing deposition processes, such as conventional CVD processes. In one exemplary embodiment, the charge storage layer may include a nitride charge storage layer, such as, for example, silicon nitride. In other embodiments, the charge storage layer may include other known dielectric materials such as, for example, high dielectric constant (high K) dielectric materials, that may be used to store a charge. The thickness of the charge storage layer may range, for example, from about 40 Å to about 100 Å.

A top oxide layer of ONO stack605may be formed on the charge storage layer using, for example, existing deposition processes, such as conventional CVD processes. The top oxide layer may include oxide materials, such as, for example, silicon oxide, or silicon oxynitride. The thickness of the top oxide layer may range, for example, from about 30 Å to about 60 Å.

A layer of gate material may be formed on the top oxide layer of ONO stack605using existing deposition processes. The layer of gate material may include, for example, polycrystalline silicon. The thickness of the layer may range, for example, from about 1000 Å to about 2000 Å. The layer of gate material may be etched, using existing photolithographic and etching processes to form gate structures205.

A source region620and a drain region625may then be formed in substrate610adjacent each gate structure. Each source region620and drain region625may be implanted with n-type or p-type impurities based on particular end device requirements. The particular implantation dosages and energy used to implant the impurities is not described herein in order not to unduly obscure the thrust of the invention. One of ordinary skill in the art, however, would be able to optimize the formation of each source region620and drain region625based on the particular end device requirements. Formation of each source region620and drain region625creates a channel region630in substrate610between each source region620and drain region625.

An interface layer305, formed as described above with respect toFIGS. 2-5, may be formed over each gate structure205as an interface to a second layer405of polycrystalline silicon formed over each gate structure205. The second layer405of polycrystalline silicon may form multiple wordlines for the memory array.

In each memory cell ofFIGS. 6A and 6B, during programming, electrical charge is transferred from substrate610to the nitride layer in the ONO stack605. Voltages are applied to the gate205and drain620creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel630. As the electrons move along the channel630, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer of ONO stack605and become trapped in the nitride layer of ONO stack605. Electrons are trapped near drain region625because the electric fields are the strongest near drain region625. Reversing the potentials applied to the source region620and drain region625causes electrons to travel along the channel in the opposite direction and be injected into the nitride layer near source region620. Because the nitride is not electrically conductive, the charge introduced into the nitride layer of ONO stack605tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous nitride layer.

In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the invention. However, implementations consistent with the invention can be practiced without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the invention. In practicing the invention, conventional photolithographic, etching and deposition techniques may be employed, and hence, the details of such techniques have not been set forth herein in detail.

The foregoing description of embodiments of the invention provides illustration and description, but is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. For example, while series of acts have been described above, the order of the acts may vary in other implementations consistent with the invention.

Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the above disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein. No element, act, or instruction used in the description of the application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used. The scope of the invention is defined by the following claims and their equivalents.