Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer

One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

BACKGROUND

1. Field of the Invention

The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer.

2. Related Art

Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.

Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.

A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.

Some processor designers have proposed entering a “scout mode” during processor stall conditions. In this scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed 19 Dec. 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue and the rename unit, and also achieves memory-level parallelism. However, it suffers from the disadvantage of having to re-compute any computational operations that are performed while in scout mode.

Hence, what is needed is a method and an apparatus for hiding memory latency without the above-described drawbacks of existing processor designs.

SUMMARY

One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

In a variation on this embodiment, deferring the store involves inserting the store into a deferred queue, which contains deferred instructions in program order.

In a variation on this embodiment, after a store is deferred into the deferred queue during execute-ahead mode, if a load is subsequently encountered, the system prefetches a cache line for the load, and defers execution of the load to prevent a possible read-after-write (RAW) hazard.

In a variation on this embodiment, while executing the instruction and subsequent instructions in an execute-ahead mode, the store buffer is gated so that stores that enter the store buffer during execute-ahead mode remain in the store buffer until the processor leaves the execute-ahead mode.

In a variation on this embodiment, upon encountering a load during the execute-ahead mode, the system determines if a load buffer is full. If so, the system: prefetches a cache line for the load; defers execution of the load; and marks a destination register for the load to indicate that the value in the destination register is subject to an unresolved data dependency.

In a variation on this embodiment, if a non-data-dependent stall condition is encountered in normal execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the non-data-dependent stall condition. Next, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. When the non-data-dependent stall condition that caused the processor to move out of normal execution mode is finally resolved, the system uses the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.

In a variation on this embodiment, if a non-data-dependent stall condition that is not a load buffer full condition or a store buffer full condition is encountered in execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. When the unresolved data dependency or the non-data-dependent stall condition that originally caused the processor to move out of normal execution mode is finally resolved, the system uses the checkpoint to resume execution in normal execution mode from the instruction that originally encountered the stall condition.

In a variation on this embodiment, if the unresolved data dependency is resolved during execute-ahead mode, the system executes deferred instructions in a deferred mode. If all deferred instructions are executed during the deferred mode, the system returns to the normal execution mode to resume normal program execution from the point where the execute-ahead mode left off.

In a variation on this embodiment, executing deferred instructions in the deferred mode involves: issuing deferred instructions for execution in program order; deferring execution of deferred instructions that still cannot be executed because of unresolved data dependencies; and executing other deferred instructions that able to be executed in program order. If some deferred instructions are deferred again, the system returns to execute-ahead mode at the point where execute-ahead mode left off.

In a variation on this embodiment, executing instructions involves keeping track of data dependencies to facilitate determining if a given instruction is subject to an unresolved data dependency. This can involve maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data dependency.

In a variation on this embodiment, the unresolved data dependency can include: a use of an operand that has not returned from a preceding load miss; a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss; a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and a use of an operand that depends on another operand that is subject to an unresolved data dependency.

In a variation on this embodiment, if the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

In a variation on this embodiment, while executing deferred instructions in the deferred mode, if a deferred store is encountered, and the store buffer now has capacity because one or more stores that entered to store buffer prior to execute-ahead mode have left the store buffer, the system enters the deferred store into the store buffer instead of deferring the deferred store again. If no stores remain in the deferred queue, subsequent loads and stores are no longer forcefully deferred.

DETAILED DESCRIPTION

Processor

FIG. 1illustrates the design of a processor100in accordance with an embodiment of the present invention. Processor100can generally include any type of processor, including, but not limited to, a microprocessor, a mainframe computer, a digital signal processor, a personal organizer, a device controller and a computational engine within an appliance. As is illustrated inFIG. 1, processor100includes instruction cache102, fetch unit104, decode unit106, instruction buffer108, deferred queue112, grouping logic110, main memory124, arithmetic logic unit (ALU)114, ALU116, branch pipe118and floating point unit120.

During operation, fetch unit104retrieves instructions to be executed from instruction cache102, and feeds these instructions into decode unit106. Decode unit106forwards the instructions to be executed into instruction buffer108, which is organized as a FIFO buffer. Instruction buffer108feeds instructions in program order into grouping logic110, which groups instructions together and sends them to execution units, including memory pipe122(for accessing memory124), ALU114, ALU116, branch pipe118(which resolves conditional branch computations), and floating point unit120.

If an instruction cannot be executed due to an unresolved data dependency, such as an operand that has not returned from a load operation, the system defers execution of the instruction and moves the instruction into deferred queue112. Note that like instruction buffer108, deferred queue112is also organized as a FIFO buffer.

When the data dependency is eventually resolved, instructions from deferred queue112are executed in program order with respect to other deferred instructions, but not with respect to other previously executed non-deferred instructions. This process is described in more detail below with reference toFIG. 5.

Buffers

FIG. 2illustrates various buffers within processor100in accordance with an embodiment of the present invention. These buffers include load buffer201, store buffer202and prefetch buffer203, which are well-known structures in existing processors. Also illustrated inFIG. 2is a deferred queue112(fromFIG. 1) and Level 2 (L2) cache204.

Load buffer201, store buffer202and prefetch buffer203hold entries for load, store and prefetch instructions that are waiting to access slower portions of the memory hierarchy, such as L2 cache204and possibly main memory124.

The present invention exploits the instruction storage capacity of the deferred queue112to increase the effective size of load buffer201and store buffer202. This is accomplished as follows. If load buffer201or store buffer202becomes full, additional loads or stores get deferred into deferred queue112as is described below with reference toFIGS. 3-9. All of this is accomplished without violating data flow dependencies.

Note that processor100needs to track when the load or store buffers are full. This can be done in several ways. For example, a credit mechanism can be employed in which credits are decremented upon issuing a load or store and the respective credit is returned when the load or store completes. Alternately, the load/store unit of processor100can signal the issue unit of processor100when it receives a load or store that would overflow one of its buffers. Regardless, the issue unit knows that the load or store could not be issued and so defers its execution by placing it into deferred queue112.

Keeping Track of Dependencies

The present invention keeps track of data dependencies in order to determine if an instruction is subject to an unresolved data dependency. In one embodiment of the present invention, this involves maintaining state information for each register, which indicates whether or not a value in the register depends on an unresolved data dependency. For example,FIG. 3illustrates a register file302in accordance with an embodiment of the present invention. Each register in register file302is associated with a “not-there” bit, which keeps track of whether a valid operand value is contained in the register, or if the operand cannot be produced because of an unresolved data dependency. For example, if a register is waiting for an operand to return from a load operation, the corresponding not-there bit is set to indicate that the desired operand value is not present in the register.

When a subsequent instruction references a source operand value that is marked as not-there, and generates a result that is stored in a destination register, the system marks the destination register as not-there to indicate that the value in the destination register also depends on the unresolved data-dependency. This can be accomplished by marking the not-there bit of the destination register with the “OR” of the not-there bits for source registers of the instruction.

Structures for Keeping Track of Stores

FIG. 4Aillustrates a store-in-DQ indicator402in accordance with an embodiment of the present invention. Store-in-DQ indicator402is set whenever a store is deferred into deferred queue112, and is cleared when all deferred stores are removed from deferred queue112.

In another embodiment of the present invention, instead of maintaining a single store-in-DQ indicator402, the system maintains a stores-in-DQ counter404and a stores-during-execute-ahead-mode counter406as is illustrated inFIG. 4B. Stores-in-DQ counter404keeps track of the number of stores in deferred queue112, and hence, is a generalization of the store-in-DQ indicator402. In contrast, stores-during-execute-ahead-mode counter406enables the system to determine if the number of stores that are deferred during execute-ahead mode exceed the capacity of the store buffer, and if so to immediately enter scout mode as is described in more detail below with reference toFIG. 8.

State Diagram

FIG. 5presents a state diagram which includes execute-ahead mode504and the scout mode508in accordance with an embodiment of the present invention. The system starts in normal execution mode502, wherein instructions are executed in program order as they are issued from instruction buffer108(seeFIG. 1).

Next, if an unresolved data dependency arises during execution of an instruction, the system moves to execute-ahead mode504. An unresolved data dependency can include: a use of an operand that has not returned from a preceding load miss; a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss; a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and a use of an operand that depends on another operand that is subject to an unresolved data dependency.

While moving to execute-ahead mode504, the system generates a checkpoint that can be used, if necessary, to return execution of the process to the point where the unresolved data dependency was encountered; this point is referred to as the “launch point.” (Generating the checkpoint involves saving the precise architectural state of processor100to facilitate subsequent recovery from exceptions that arise during execute-ahead mode504or deferred mode506.) The system also “defers” execution of the instruction that encountered the unresolved data dependency by storing the instruction in deferred queue112.

While operating in execute-ahead mode504, the system continues to execute instructions in program order as they are received from instruction buffer108, and any instructions that cannot execute because of an unresolved data dependency are deferred into deferred queue112.

During execute-ahead mode504, if an unresolved data dependency is finally resolved, the system moves into deferred mode506, wherein the system attempts to execute instructions from deferred queue112in program order. Note that the system attempts to execute these instructions in program order with respect to other deferred instructions in deferred queue112, but not with respect to other previously executed non-deferred instructions (and not with respect to deferred instructions executed in previous passes through deferred queue112). During this process, the system defers execution of deferred instructions that still cannot be executed because of unresolved data dependencies by placing these again-deferred instruction back into deferred queue112. On the other hand, the system executes other instructions that can be executed in program order with respect to each other.

After the system completes a pass through deferred queue112, if deferred queue112is empty, the system moves back into normal execution mode502. This may involve committing changes made during execute-ahead mode504and deferred mode506to the architectural state of processor100, if such changes have not been already committed. It can also involve throwing away the checkpoint generated when the system moved into execute-ahead mode504.

On the other hand, if deferred queue112is not empty after the system completes a pass through deferred queue112, the system returns to execute-ahead mode504to execute instructions from instruction buffer108from the point where the execute-ahead mode504left off.

If a non-data dependent stall condition (except for a load buffer full or store buffer full condition) arises while the system is in normal execution mode502or in execute-ahead mode504, the system moves into scout mode508. (This non-data-dependent stall condition can include: a memory barrier operation; or a deferred queue full condition.) In scout mode508, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of processor100.

Scout mode508is described in more detail in a pending U.S. patent application entitled, “Generating Prefetches by Speculatively Executing Code Through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay, having Ser. No. 10/741,944, and filing date 19 Dec. 2003, which is hereby incorporated by reference to describe implementation details of scout mode508.

Unfortunately, computational operations performed during scout mode508need to be recomputed again, which can require a large amount of computational work.

When the original “launch point” stall condition is finally resolved, the system moves back into normal execution mode502, and, in doing so, uses the previously generated checkpoint to resume execution from the launch point instruction that encountered the launch point stall condition. The launch point stall condition is the stall condition that originally caused the system to move out of normal execution mode502. For example, the launch point stall condition can be the data-dependent stall condition that caused the system to move from normal execution mode502to execute-ahead mode504, before moving to scout mode508. Alternatively, the launch point stall condition can be the non-data-dependent stall condition that caused the system to move directly from normal execution mode502to scout mode508.

Handling a Store in Execute-Ahead Mode

FIG. 6presents a flow chart illustrating how a store is handled during execute-ahead mode504in accordance with an embodiment of the present invention. When a store is encountered during execute-ahead mode504, the system checks store-in-DQ indicator402to determine whether there exists a deferred store in the deferred queue112(step604). If so, a subsequent load cannot perform a CAM lookup on deferred queue112, because unlike store buffer202, deferred queue112lacks the circuitry to perform a CAM lookup. Hence, in order to avoid a potential read-after-write (RAW) hazard, the system defers subsequent loads.

Moreover, because of this deferral of younger loads, it is desirable for the first deferred store to enter store buffer202before a younger store. It is also preferable to keep the space in store buffer202free, so that upon entering deferred mode506the first such deferred store will enter store buffer202. Hence, instead of executing a subsequent store that follows the first deferred store, the system defers the subsequent store by prefetching the subsequent store (step608) and inserting the subsequent store into deferred queue112(step610).

Note that store-in-DQ indicator402cannot be immediately cleared if a store should complete and free up an entry in the store buffer. Once a store is deferred because of lack of space in store buffer202, all younger loads in program order must be deferred. Thus, store-in-DQ indicator402remains set until processor100enters deferred mode506. At this point the store-in-DQ indicator402is cleared. If store buffer202is still full, the store that was originally deferred will be deferred again, and system will again set store-in-DQ indicator402.

On the other hand, if there no longer exists a deferred store in deferred queue112at step604, the system determines if store buffer202is full (step606). If so, the system defers the store by prefetching the store (step608) and inserting the store into deferred queue112(step610). The system also sets store-in-DQ indicator402(if it is not already set), or alternatively increments stores-in-DQ counter404. Otherwise, if store buffer202is not full, the system processes the store normally in execute-ahead mode504, which involves placing the store into store buffer202(step612).

Handling a Load in Execute-Ahead Mode

FIG. 7presents a flow chart illustrating how a load is handled during execute-ahead mode504in accordance with an embodiment of the present invention. When a load is encountered during execute-ahead mode504, the system checks store-in-DQ indicator402to determine whether there exists a deferred store in the deferred queue112(step704). If so, in order to avoid a potential RAW hazard, the system defers the load by prefetching the load (step708) and inserting the load into deferred queue112(step710).

On the other hand, if there does not exist a deferred store in deferred queue112at step704, the system determines if load buffer201is full (step706). If so, the system defers the load by prefetching the load (step708) and inserting the load into deferred queue112(step710). Otherwise, if the load buffer is not full, the system processes the load normally in execute-ahead mode504, which involves placing the load into load buffer201(step712).

Note that when a load is deferred, its destination register is marked as “not-there.” Furthermore, note that the previously-described mechanism for propagating not-there bits works naturally to avoid RAW hazards.

Entering Scout Mode Directly

FIG. 8presents a flow chart illustrating how the system directly enters scout mode508when the number of stores encountered during execute-ahead mode504exceeds the capacity of store buffer202in accordance with an embodiment of the present invention. During execute-ahead mode504, the system increments stores-during-execute-ahead-mode counter406for every store the system encounters (step802). The system then determines if stores-during-execute-ahead-mode counter406exceeds the capacity of store buffer202(step804).

If so, store buffer202will eventually fill with stores encountered during execute-ahead mode504. Note that these stores will never leave store buffer202because store buffer202is gated during execute-ahead mode504. Furthermore, at least one additional store will remain in deferred queue112. This additional store will never leave deferred queue112because there will never be space for it is store buffer202. Hence, execute-ahead mode504will never complete successfully, and deferred queue112will eventually fill up with instructions, which will cause the system to enter scout mode508. Instead of waiting for deferred queue112to fill up, one embodiment of the present invention immediately enters scout mode508because the system will eventually have to enter scout mode508anyway (step806). Note that the system does not have to always enter scout mode508at this point, but can instead decide heuristically whether to stall issue or to immediately enter scout mode508.

Otherwise, if stores-during-execute-ahead-mode counter406does not exceed the capacity of store buffer202, the system returns to step802to resume normal operation in execute-ahead mode504.

Keeping Track of Stores in the Deferred Queue

FIG. 9presents a flow chart illustrating how stores-in-DQ counter404can be used to keep track of the number of stores in deferred queue112in accordance with an embodiment of the present invention. For each store that is deferred during execute-ahead mode504, the system increments stores-in-DQ counter404(step902).

While retrying deferred stores in deferred mode506, if a deferred store can be placed in store buffer202(for example, because there is space in store buffer202, or because a preceding deferred store has completed), the system executes the store in deferred mode506. This involves placing the store into store buffer202and decrementing stores-in-DQ counter404(step904).

If stores-in-DQ counter404reaches zero, no stores remain in deferred queue112. Consequently, subsequent loads and stores do not have to be forcefully deferred into deferred queue112(step906).