Data encoding and packet sharing in a parallel communication interface

An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.

BACKGROUND

Technical Field

Embodiments described herein are related to systems-on-a-chip (SOCs) and, more particularly, to parallel communication interfaces.

Description of the Related Art

System-on-a-chip (SOC) integrated circuits (ICs) generally include one or more processors that serve as central processing units (CPUs) for a system, along with various other components such a memory controllers and peripheral components. Additional components, including one or more additional ICs, can be included with a particular SOC IC to form a given device. For example, an SOC may include any suitable combination of one or more general-purpose processors, a graphics processors, an audio processor, security and/or cryptography circuits, networking circuits (e.g., one or more circuits supporting ethernet, universal serial bus (USB), peripheral component interconnect express (PCIe)), memory controllers, display controllers, and the like.

To communicate among the processors, memory controllers, peripherals, and other components (collectively referred to as “agents”), the SOC may include a bus circuit capable of transferring data packets with a particular number of bits in parallel. Such a bus circuit may include a variety of interfaces, buffers, and/or other circuits to perform data packet transfers between two or more agents. By transferring data packets with 32, 64, 128, or more bits in parallel, data may be transferred between agents in a sufficient amount of time for a given application. To increase bandwidth for transferring data, some SOCs may include a plurality of bus circuits. For example, one bus circuit may be used for a plurality of general-purpose processors to exchange data with each other and one or more memory controllers. Another bus circuit may be used for transferring graphics information between a graphics processor, a display interface, and a camera circuit. In addition, a third bus circuit may be included for exchanging data between agents that have low priority information to exchange, such as a file being saved from a volatile memory to a non-volatile memory. A number and size of bus circuits on a given SOC may be based, at least partially, on die area and/or power supply considerations.

SUMMARY

In an embodiment, an apparatus includes an interface circuit, including a plurality of segments, and an encoder circuit. The interface circuit may be configured to send individual bits of a data packet in parallel via the plurality of segments, and to send an idle value via the plurality of segments when no data packet is available to send. The idle value may correspond to a particular bit sequence per segment, and may be configured to cause a corresponding segment in a receiving apparatus to be idle. The encoder circuit may be configured to receive a particular data packet having a plurality of bits arranged in an original order. In response to a determination that a group of the plurality of bits have a same value as the idle value for a subset of the plurality of segments, the encoder circuit may be configured to replace at least a portion of the group of bits with a mask value to generate a modified data packet. The mask value may indicate, to a receiving apparatus independent of control signals external to the particular data packet, how to recreate the particular data packet with the bits arranged in the original order. The encoder circuit may be configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.

In a further embodiment, to replace the at least a portion of the group of bits with the mask value, the encoder circuit may be configured to include the mask value within a particular segment of the plurality of segments. In an embodiment, the encoder circuit may by further configured to modify values of one or more of the group of bits for the subset of segments.

In one embodiment, to include the mask value in the particular segment, the encoder circuit may be further configured to shift one or more bits of the plurality of bits from the particular segment into a different segment and insert the mask value into a particular set of bit positions vacated by the shifted bits. In an example, to include the mask value in the particular segment, the encoder circuit may be further configured to set a particular bit of the particular segment to a value that indicates that the mask value is included in the particular segment.

In a further example, to send the idle value, the interface circuit may be configured to send the idle value in a particular set of segments of the plurality of segments. In an example, the apparatus may further include a plurality of networks, and a first and a second group of the plurality of segments may be coupled, respectively, to a first and a second network of the plurality of networks.

While embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims.

DETAILED DESCRIPTION OF EMBODIMENTS

As described above, a given integrated circuit (IC) design may include one or more bus circuits to enable communication between a plurality of agents. As used herein, an “agent” refers to a functional circuit that is capable of initiating or being a destination for a transaction on a bus circuit. Accordingly, general-purpose processors, graphics processors, network interfaces, memory controllers, and other similar circuits may be referred to as agents. In some cases, a data exchange between two agents across one of the bus circuits (also referred to as a “transaction”), may have a particular priority. For example, in a user computer device (e.g., desktop/laptop computer, smartphone, tablet, and the like), launching an application initiated by a user may be treated with a high priority, as any delays could be noticed by the user and generate a sense of low performance in the user's opinion if the delays are longer than expected. In contrast, a background process that is synchronizing user data with an online account may occur without the user's knowledge, and therefore, be treated with a lower priority than the launch of the user's application.

To manage the variety of data transactions between the various agents, a plurality of bus circuits may be implemented, with particular bus circuits prioritized for particular types of transactions. Bus circuits, however, consume both die area and power on an IC. As such, SOC designers may balance performance of the SOC agents with limitations on die area and/or power budgets. Accordingly, SOC designers may desire a bus circuit design that increases an amount of data that can be transferred in relation to the die area and/or power that the bus circuit consumes. One technique for reducing a die area of a bus circuit, as well as for reducing power consumption, is to reduce a number of control signals associated with the bus circuit for a given number of bits that can be transferred in parallel. A reduced number of physical wires may result in less die area used for a given number of bits that can be transferred in parallel. Fewer control signals may also reduce power consumption by reducing a number of signals switching for a given transaction.

Reducing a number of control signals, however, may pose several challenges. For example, another technique for reducing power consumption of a bus circuit includes sending an indication to one or more agents on a bus circuit to enter an idle state. The idle state may indicate that no transaction is currently in progress, allowing bus interface circuits receiving the idle indication to place associated circuits of the interface into a reduced power state. To avoid utilizing an additional wire for a control signal to indicate the idle state, a particular value may be reserved for the data wires of the bus circuit to indicate the idle state, referred to herein as an “idle value.” For example, a value of all logic high bits or all logic low bits may be used as the idle value. A bus interface circuit detecting the idle value may ignore the bus circuit until a different value is detected, e.g., disable a clock signal to circuits that sample values on the bus circuit.

While such a value may reduce power consumption of a bus circuit and/or agents coupled to the bus circuit without increasing a number of control signals, an issue arises when a transaction includes a valid data value that coincidently equals the idle value. A transaction includes one or more data packets being transferred across a bus circuit from a source agent that initiates the transaction to a destination agent that is to receive the transaction. A “data packet” or simply “packet” as used herein, refers to a group of bits that are sent over the bus in parallel within a given bus cycle. For example, to send a transaction that includes 1000 bytes of data across a bus circuit that supports data packets of 128 bits (sixteen bytes) requires at least 63 data packets. If one of these data packets happens to correspond to the idle value, then an indication needs to be provided to the destination agent to avoid having the destination agent incorrectly interpret the valid data packet as an idle value.

Further complicating the issue, bus interface circuits, in some embodiments, may be implemented using a plurality of segment circuits (or simply “segments”), in which each segment includes components for transferring a number of bits. A set of segments may be used together to transfer a single data packet in parallel. For example, a 128-bit bus interface circuit may be implemented using four 32-bit segments. Although operating in parallel, each segment may operate independently from the other segments. In such embodiments, an idle value may be implemented per segment, rather than across an entire data packet, thereby increasing a possibility of a given data packet including a coincidental idle value for at least one segment.

To address such an issue, techniques are contemplated that include encoding a data packet before sending the data packet across a bus circuit. Such an encoding technique may include sending a data packet to an encoder circuit prior to transmission across the bus circuit. The encoder circuit may determine if the received data packets includes a value that could be misinterpreted as an idle value by one or more segments of the bus circuit. If such a case is detected, then a mask value is generated and used to replace at least a portion of the data packet. This mask value may be used by a destination agent to decode the encoded data packet to reconstruct the original data packet. For example, a mask value may be generated in which a particular bit of the mask value indicates whether a corresponding segment of an encoded data packet holds a valid value that can be misinterpreted as an idle value.

By encoding the mask value into the data packet, the idle value may still be utilized without an addition of a number of control signals to each segment of an interface. Avoiding an increase in a number of control signals may save power and/or die area of an IC in comparison to an IC in which additional control signals are added.

FIG.1illustrates a block diagram of one embodiment of a system that encodes a data packet before sending the data packet via an interface circuit. As illustrated, system100includes encoder circuit101and interface circuit110. Interface circuit110further includes a plurality of segments127a-127h(collectively segments127). In some embodiments, system100is implemented as an integrated circuit (IC). Encoder circuit101and interface circuit110may be coupled to one or more agents on the IC via a bus circuit. Interface circuit110may, in some embodiments, be further coupled to a different IC via a plurality of pins.

As shown, interface circuit110, including segments127, is configured to send individual bits of a data packet in parallel via segments127. For example, a source agent may initiate a transaction, including one or more data packets, to be sent to a destination agent. To send a given data packet of the transaction, the source agent sends the data packet to interface circuit110, which in turn, sends the data packet to the destination agent. In various embodiments, the data packet may be sent to additional circuits, including, for example, bus switches and/or other interface circuits on the way to the destination agent. In some embodiments, interface circuit110may be coupled to a different interface circuit on a different IC.

Interface circuit110, as illustrated, is further configured to send an idle value via segments127when no data packet is available to send. The idle value corresponds to a particular bit sequence per segment, and is configured to cause a corresponding segment in a receiving apparatus to be idle, also referred to as an idle state. The idle value may be utilized to reduce power consumption in the receiving apparatus when no data packets are being transferred. The idle value may indicate to the receiving apparatus that no data is currently being sent, thereby preventing the receiving apparatus from wasting resources by processing invalid data. In some embodiments, the receiving apparatus may remain active, but ignore any received data packets corresponding to the idle value. In other embodiments, the receiving apparatus may take actions to reduce power consumption during an idle state. For example, the idle state may prevent one or more signals (e.g., a clock signal and/or other control signals) of a corresponding segment that is associated with the destination agent from transitioning. Reducing a number of signal transitions may reduce a dynamic power consumed by the corresponding segments.

In some cases, however, a data packet may include a value, that when aligned to segments127, results in one or more of segments127asserting an idle value. In such cases, the value sent by the one or more segments127is intended to be interpreted as a valid data value, and not as an idle value. In some embodiments, an additional control signal may be added to indicate to a receiving segment when an idle value is being sent versus other valid information. With a segmented interface, such as interface circuit110, a control signal may be required for each segment127, which may increase a die size and or power consumption of system100. In a system with few segments, the additional control signals may be acceptable. In other systems, tens, hundreds, or even more segments may be included in a given interface circuit. The additional die area and/or power consumption from the needed control signals may not be acceptable.

To address the idle value issue without adding an undesirable number of control signals, system100includes encoder circuit101. As illustrated, encoder circuit101is configured to receive data packet120having a plurality of bits arranged in bit order140, from least significant bit144to most significant bit142. Data packet120includes a plurality of portions122a-122h(collectively portions122), wherein each portion aligns to a respective one of segments127.

In response to a determination that a group of the plurality of bits have a same value as the idle value for a subset of segments127, encoder circuit101is further configured to replace at least one of portions122of the group of bits with mask value125to generate modified data packet130. In the example ofFIG.1, portion122dcorresponds to the idle value. In other examples, more than one portion122may correspond to the idle value.

Mask value125indicates, to a receiving apparatus independent of control signals external to data packet120, how to recreate data packet120with the bits arranged in bit order140. For example, encoder circuit101may generate mask value125with at least one bit corresponding to a respective one of portions122. The at least one bit is given a first value if the respective portion includes the idle value, and a different value if the idle value is not included. Additionally, encoder circuit101is further configured to set a particular bit of mask value125to a value that indicates that mask value125is included in the modified data packet130. For example, eight portions are depicted inFIG.1for data packet120. Each of portions122may include nine bits. Mask value125may, therefore use eight bits of mask value125to indicate which of segments127include portions122of modified data packet130that correspond to the idle value, and use the ninth bit to indicate that the value placed in segment127ais a mask value and not part of the original data packet120.

To replace the at least a portion of the group of bits with mask value125, encoder circuit101is further configured to include mask value125within a particular segment of segments127. As shown, encoder circuit101replaces the least significant portion, portion122a, with mask value125to generate modified data packet130. Mask value125will be sent via segment127a. In addition, to include mask value125in segment127a, encoder circuit101is further configured to shift one or more bits of the plurality of bits from segment127ainto a different segment and insert mask value125into a particular set of bit positions vacated by the shifted bits. For example, portions122a-122cinclude valid data that does not correspond to the idle value. Accordingly, portions122a-122care shifted in modified data packet130to an adjacent portion in a next higher order of significance. Since portion122dincludes the idle value, portion122dis removed from modified data packet130. Portions122a-122c, therefore, are sent via segments127b-127d, respectively.

After modified data packet130is generated, encoder circuit101is further configured to send modified data packet130to the receiving apparatus via segments127of interface circuit110. In some embodiments, segments127may be implemented as multiple instances of a single circuit design. As such, each segment may have a respective power and/or clock signal for performing the transfer of modified data packet130. While data packets are described as being transferred via interface circuit110in parallel, the individual operation of each of segments127may result in portions122not being perfectly aligned. Accordingly, as used herein, “parallel” is used to indicate operations that are performed in a substantially overlapping manner. Beginnings and/or endings of two or more parallel operations may not, however, align exactly.

It is noted that system100, as illustrated inFIG.1, is merely an example. The illustration ofFIG.1has been simplified to highlight features relevant to this disclosure. Various embodiments may include different configurations of the circuit elements. For example, interface circuit110is shown with eight segments127. In other embodiments, any suitable number of segments may be included. Mask value125is shown to replace a least significant one of portions122. In other embodiments, a most significant portion or any other particular one of portions122may be replaced by mask value125.

FIG.1illustrates an encoding operation of a data packet before being sent to a receiving apparatus. The receiving apparatus may include a corresponding decoder circuit to reconstruct an original data packet. One example of a decoder circuit is shown inFIG.2.

Moving toFIG.2, a block diagram of an embodiment of a system that receives a data packet via an interface circuit and then restores the data packet to an original state is shown. As illustrated, system200includes decoder circuit201and interface circuit210. Interface circuit210further includes a set of segments227a-227h(collectively segments227). In a similar manner as described above for system100ofFIG.1, system200may, in some embodiments, be implemented as an integrated circuit (IC), and decoder circuit201and interface circuit210may be coupled to one or more agents on the IC via a bus circuit. Interface circuit210may, in some embodiments, be further coupled to a different IC via a plurality of pins. For example, interface circuit210may be implemented on a first IC and coupled to interface circuit110implemented on a second IC via a plurality of conductive paths.

As illustrated, interface circuit210is configured to receive an encoded data packet via segments227. For example, segments227may be aligned with and coupled to segments127ofFIG.1. Respective portions of the received data packet may be held in ones of segments227. Decoder circuit201is configured to access segments227, and extract mask value125from the received data packet. For example, decoder circuit201may be configured to determine whether a particular one of segments227, e.g., segment227aas illustrated, includes a mask value or includes a portion of the received data packet. In some embodiments, a portion of segment227amay be used to indicate presence of a mask value, such as a most or least significant bit of segment227a. The extracted mask value125is stored in register230in decoder circuit201, as shown.

After extracting mask value125, decoder circuit201is further configured to replace, in the received data packet, mask value125with restoration value244that corresponds to the idle value. Since mask value125is included in segment227ato indicate that at least one portion of the received data packet included an idle value, the idle value is used as restoration value244to restore the data packet to its original state. As illustrated, the portion of the received data packet that included mask value125is replaced by adding restoration value244. Restoration value244, however, may not be placed in a same position as mask value125. Rather, decoder circuit201is further configured to reconstruct, using mask value125, data packet120to include restoration value244.

In the example ofFIG.2, decoder circuit201uses mask value125to determine that segments227b-227dinclude, respectively, portions122a-122cof data packet120. Accordingly, decoder circuit201shifts portions122a-122creceived in segments227b-227dinto the three least significant positions of the reconstructed data packet120. The remaining segments227e-227hinclude portions122e-122h, which are received in their proper positions for reconstructed data packet120. Portion122d, therefore, is determined (using mask value125) to be missing from the received data packet in segments227, and decoder circuit201places restoration value244in a position corresponding to portion122d.

It is noted that the embodiment ofFIG.2is one example. In other embodiments, a different combination of elements may be included. For example, a different number of segments may be included instead of eight. AlthoughFIG.2depicts9pins included in each segment227, in other embodiments, any suitable number of pins may be included per segment. Mask value125is shown to be received in a least significant one of segments227. In other embodiments, a most significant segment or any other particular one of segments227may include mask value125.

In the description ofFIGS.1and2, a single portion of a data packet is depicted as including an idle value. In various cases, a given data packet may include no idle values or multiple idle values. In some cases, an actual idle value may be sent to indicate an idle state. Various examples of packets are shown inFIG.3.

Turning toFIG.3, three examples of packets received by a decoder circuit are shown. As illustrated, examples300a-300cillustrate behavior of decoder circuit201ofFIG.2after receiving various forms of packets. Example300adepicts decoder circuit201receiving idle packet320a. Example300bshows decoder circuit201receiving data packet320b, which does not include a mask value. Example300cshows decoder circuit201receiving data packet320cwhich includes mask value325, as well as several portions that originally included idle values.

As illustrated, example300aincludes decoder circuit201receiving (from interface circuit110via interface circuit210, for example) idle packet320a. To send idle packet320a, interface circuit110is configured to send idle value321a-321gin a particular set of segments127a-127h. In the example, the idle value is ‘00000000’ and is sent via all eight of segments127ofFIG.1. In other embodiments, however, the idle value may be set to any predetermined value and may be sent via a subset of segments127. For example, the idle value may be ‘010101010’ and may be sent to half of segments127, such as segments127a,127c,127e, and127g. In such an embodiment, segments127b,127d,127f, and127hmay determine whether to enter an idle state based on a respective one of segments127a,127c,127e, and127g.

Idle packet320a, as shown, is sent decoder circuit201, which may then enter a static or reduced activity state. For example, one or more clock signals may be gated to reduce a number of signal transitions occurring within decoder circuit201. Interface circuit210may also enter a reduced activity state in response to detecting idle packet320a. In some embodiments, interface circuit210may not send idle packet320ato decoder circuit201, and decoder circuit201instead enters a reduced activity state in response to the reduced activity of interface circuit210. In response to receiving a data packet with a non-idle value, then interface circuit210and decoder circuit201return to full operational states.

In example300b, decoder circuit201receives data packet320bfrom interface circuit110via interface circuit210. Data packet320bincludes portions322a-322h(collectively portions322). Since none of portions322have values that correspond to the idle value (e.g., ‘00000000’ in the current examples), a mask value is not generated for data packet320band all portions may be sent by interface circuit110to interface circuit210without changes to any values. Accordingly, decoder circuit201generates decoded data packet330bwith the same values as data packet320bas received via interface circuit210.

In example300c, decoder circuit201receives a data packet that includes a mask value. Similar to the other two examples, decoder circuit201receives, from interface circuit110via interface circuit210, data packet320cthat includes portions323a-323h(collectively portions323). In various embodiments, the mask value may be placed in any suitable portion of the data packet. In the illustrated example, mask value325is placed in a least significant portion344of data packet320c.

Since mask value325is included within data packet320cin a position that, in many cases, includes information other than a mask value, an indication is used to alert decoder circuit201that a mask value is included rather than other information. To include mask value325in a particular segment (corresponding, in example300c, to the least significant portion344), encoder circuit101ofFIG.1is further configured to set a particular bit of the particular segment to a value that indicates that mask value325is included in the particular segment. In mask value325, the most significant bit (underlined and in bold) is used as this indication. When this bit is set to ‘1’ as it is for mask value325, then the value in the least significant portion of a received data packet is a mask value. If it is set to ‘0’ as it is for portion322ain example300b, the value in the least significant portion of a received data packet may be treated as data.

Decoder circuit201is further configured to identify the inclusion of mask value325using a portion of a received value from the particular one of a set of segments of interface circuit210. As described for the examples ofFIG.3, the particular one of the segments is the least significant one and the portion of the value in this segment is the most significant bit. The inclusion of mask value325is indicated by the value of ‘1’ in the most significant bit of the value received via segment227aof interface circuit210.

To encode data packet320c, encoder circuit101is further configured to modify values for a subset of segments127that would otherwise send values that correspond to the idle value. In response to a determination that more than one of a plurality of values have a same value as the idle value, encoder circuit101is configured to replace the values that are the same as the idle value with a particular value that is different than the idle value. As shown inFIG.3, the idle value is ‘000000000’ and the particular value is ‘111111111.’ In other embodiments, the idle value and/or the particular value may be any other suitable values.

To reconstruct the original data packet, decoder circuit201is further configured to identify, using mask value325, ones of segments227that include the particular value; and replace the particular value with the idle value. Decoder circuit201generates decoded data packet330cby identifying, based on mask value325, which portions of the decoded data packet330bshould be set to the idle value. The most significant bit of mask value325is the indication that the portion should be treated as a mask value. The remaining eight bits are used to indicate which portions of decoded data packet330bshould be set to the idle value, with the most significant bit of the eight bits corresponding to the most significant portion, and so forth to the least significant bit corresponding to the least significant portion. A bit value of ‘0’ indicates the value of the corresponding portion is included in data packet320c, while a bit value of ‘1’ indicates the corresponding portion should be set to the idle value. The third, fifth, and sixth bits of mask value325(counting from the least significant bit) are set to one, indicating that portions323c,323eand323fare to be changed from the particular value (‘111111111’) in data packet320cto the idle value (‘000000000’) in decoded data packet330c.

It is noted that, in example300c, the least significant portion of decoded data packet330cthat includes the idle value, e.g., portion323c, is replaced in data packet320cby encoder circuit101before the encoded data packet is sent. Since mask value325is placed into the least significant portion, portions323aand323b, which include valid information, are shifted into the next higher significance portions and portion323cis removed from data packet320c. Since portions323eand323fare not removed, their values are replaced with the particular value. This prevents any one of segments127of interface circuit110from sending an idle value to the corresponding segments227in interface circuit210. Otherwise, if an individual one of segments227were to receive the idle value, that particular segment might enter an idle state and thereby fail to receive the respective portion of data packet320c.

It is noted that the examples ofFIG.3are merely for demonstrating disclosed concepts. The examples are limited to showing data packets and a decoder circuit to clearly illustrate the described techniques. In the illustrated examples, the most significant bit of the least significant portion of a data packet is used as an indication of a mask value. In other embodiments, however, any suitable bit of any suitable portion

FIGS.1and2describe respective embodiments of an encoder circuit and a decoder circuit, as well as their associated interface circuits. Encoder and decoder circuits may be used together in various embodiments.FIG.4illustrates an embodiment of a system that includes an encoder circuit and a decoder circuit that are coupled via their respective interface circuits.

Proceeding toFIG.4, a block diagram of an embodiment of a system that includes two integrated circuits coupled via a physical connection between respective interface circuits is shown. In the illustrated embodiment, system400includes integrated circuits405aand405bcoupled via physical connection440. Integrated circuit405aincludes transmitter circuit450and networks460a-460c(collectively networks460). Similarly, integrated circuit405bincludes receiver circuit455and networks470a-470c(collectively networks470). Transmitter circuit450includes encoder circuits401aand401band interface circuit410. Receiver circuit455includes decoder circuits403aand403b, and interface circuit412. Interface circuits410and412include respectively, segments427a-427h(collectively segments427) and segments429a-429h(collectively segments429).

In some embodiments, dies for integrated circuits405aand405bare configured as a single system400in which the existence of multiple semiconductor dies is transparent to software executing on the single system. Networks460on integrated circuit405aand networks470on integrated circuit405bmay be coupled to a variety of agents on the respective die. These agents (not illustrated) may include, as disclosed above, any suitable combination of general-purpose processors, graphics, processors, memory controllers, and the like. Different types of agents may be coupled to one or more of the different networks. For example, networks460aand460bmay be coupled to a processor complex that includes a plurality of processor circuits, while network460cis coupled to one or more memory controllers. Networks470aand470bmay be coupled to a similar processor complex on integrated circuit405band network470ccoupled to a similar one or more memory controllers. In some embodiments, integrated circuit405aand405bmay correspond to different instances of a same integrated circuit design.

For example, software executing on a processor circuit (not shown) in integrated circuit405amay be coupled to one or more of networks460and, using a coupled network460, initiate transactions that include sending one or more data packets, including, e.g., data packet425a, to a functional circuit (not shown) included in integrated circuit405b. Data packet425a, without explicit commands from the software executing on the processor, may be encoded via encoder circuit401b, sent via interface circuit410to interface circuit412in integrated circuit405bwhere it is then decoded by decoder circuit403band forwarded on to the destination functional circuit using network470c.

Techniques such as are utilized in system400may allow a scalable system solution that is scalable from a single integrated circuit to multiple integrated circuits coupled via their respective interface circuits. This scalable solution may enable reuse of software with few, if any, changes across systems with varying numbers of integrated circuits.

To enable communication across the integrated circuit dies, integrated circuit405a, as shown, includes transmitter circuit450, which further includes a first set of segments427. In a similar manner as described above for segments127, segments427(as well as segments429) may be implemented as multiple instances of a single circuit design that is used as a building block for creating an interface circuit with a number of pins that is a multiple of the number of pins in a single one of segments427or429. Use of such building blocks for creating an interface circuit may reduce a design complexity as well as create an interface with pins that have similar characteristics across the entire interface circuit. Although only eight segments are shown in each of interface circuits410and412, other embodiments may have tens or hundreds of segments. In an interface circuit with a number of pins in the hundreds or even thousands, similar characteristics across the interface may make it easier for designers to manage the timing of signals in the various segments.

As disclosed above, integrated circuits405aand405beach include a plurality of networks460and470, respectively. Groups of segments427are coupled, respectively, to groups of networks460. As shown, segments427g-427hare assigned to network460a, segments427e-427fare assigned to network460b, and segments427a-427dare assigned to network460c. It is noted that segment427amay not be fully utilized by network460c. In some embodiments, the excess pins of segment427amay be used by a different network. In other embodiments, the excess pins may be left unused or otherwise utilized for other functions, such as providing a clock signal, power signal, and/or ground reference signal. Groups of segments429are assigned to respective groups networks470in a similar manner.

As illustrated, transmitter circuit450is configured to, in response to a determination that no data packet is available to send, send an idle value. This idle value corresponds to a particular value per segment427, e.g., all logic low or all logic high values. A given segment of segments429is configured to enter an idle state in response to receiving the idle value from a corresponding one of segments427. Since the idle state is, in the current embodiment, implemented per each segment, techniques such as previously described are utilized to avoid inadvertently sending an idle value on a given segment427when a bit sequence in a received data packet happens to be the same as the idle value.

Transmitter circuit450, as shown, is further configured to receive a particular data packet (e.g., data packet420a) that includes a plurality of values associated with respective ones of segments427. At least one value of the plurality of values, has a same value as the idle value. Data packet420ais received by encoder circuit401afrom a combination of network460aand460b. In various embodiments, a given data packet may be received from one or more networks. Data packet420ais depicted as having four portions, each portion aligning with a respective one of segments427e-427hof the plurality of segments427. As stated, one or more of these portions have a value that is the same as an idle value. Data packet420a, however, includes information other than idle values and the presence of an idle value aligning with one or more of segments427e-427his a random occurrence and not intended to trigger an idle state in a corresponding one or more of segments429e-429h. For example, an idle value in segment427gmay cause segment429gto enter the idle state.

In order to avoid triggering an idle state in segment429g, transmitter circuit450is further configured to replace a value associated with a particular one of segments427e-427hwith a mask value to generate an encoded data packet. In various embodiments, a particular one of the set of segments aligned with a given data packet is used to store and transmit the mask value that identifies which ones of the set of segments originally held an idle value. Continuing the example from the prior paragraph, segment427ghas the idle value while the other three segments have non-idle values. In the current example, segment427eis used to hold the mask value. Any of the other three segments may be used in other embodiments. Accordingly, encoder circuit401ais configured to generate a mask value that indicates that segment427goriginally held a value corresponding to the idle value. Encoder circuit401ais further configured to use a portion of the mask value to indicate the inclusion of the mask value in segment427e, and to then place the generated mask value into segment427e. To generate an encoded data packet in segments427e-427h, the non-idle values of data packet420athat aligned to segments427eand427fare shifted into segments427fand427g, respectively. The idle value that originally aligned to segment427gis removed, having been replaced by the mask value now in segment427e. Transmitter circuit450is further configured to send the encoded data packet via segments427e-427h.

As depicted, receiver circuit455, including a second set of segments429aligned with and coupled to segments427, is configured to receive the encoded data packet via segments429e-429h. Segments427are coupled to respective ones of segments429via physical connections440. In various embodiments, physical connections between integrated circuit405aand405bmay be implemented using solder bumps on bonding pads of interface circuits410and412, using an interposer device between the dies of integrated circuits405aand405b, abutting integrated circuits405aand405balong one edge of the respective dies and using bond wires as physical connections440, or using other suitable methods.

After receiving the encoded data packet from transmitter circuit450, receiver circuit455, as shown, is further configured to extract the mask value from the received data packet. Decoder circuit403ais configured to detect the indication in the value received from segment427eand held in segment429ethat determines whether the portion of the received value is a mask value or information associated with the original data packet420a. Since segment427eholds the mask value, the portion indicates the presence of the mask value and decoder circuit403aextracts the value, for example, placing the value into a register, memory location, or other form of latching circuit.

As illustrated, receiver circuit455is further configured to replace, in the received data packet420b, the mask value with a restoration value that corresponds to the idle value, and to reconstruct, using the mask value, data packet420b, including the restoration value. Decoder circuit403ais further configured to use a restoration value, equal to the idle value, to replace the extracted mask value. Decoder circuit403afurther uses the mask value to identify that data packet420bshould have the restoration value in the portion that is aligned to segment429g. Decoder circuit403aplaces the restoration value in this identified position of data packet420band shifts the values received in segments429fand429gover into the portions aligned with segments429eand429f, respectively. Data packet420b, accordingly, is reconstructed to match data packet420aand segment429gis prevented from entering an idle state despite the inclusion of an idle value in the original data packet420a.

Although communication is shown as being transmitted by integrated circuit405aand received by integrated circuit405b, in some embodiments, integrated circuit405bincludes one or more transmitter circuits and integrated circuit405aincludes one or more receiver circuits, thereby enabling communication back and forth between the two integrated circuits. Additionally, other embodiments may include more than two integrated circuits coupled via respective interface circuits by a plurality of physical connections.

It is noted thatFIG.4is merely one example of the disclosed concepts. Although two integrated circuits are shown, any suitable number may be included in other embodiments. The number of illustrated elements are limited for clarity. In other embodiments, any suitable number of each of the various elements may be included. For example, eight segments in total are illustrated for each interface circuit. In other embodiments, any suitable number of segments may be included, as well as any suitable number of pins per segment.

The circuits and techniques described above in regards toFIGS.1-4may be utilized to encode and decode data packets for transmission across an interface circuit. Two methods associated with encoding and decoding data packets are described below in regards toFIGS.5and6.

Proceeding now toFIG.5, a flow diagram for an embodiment of a method for encoding a data packet that includes an idle value is shown. Method500may be performed by a system that includes an encoder circuit and an interface circuit with a plurality of segments, such as systems100and400inFIGS.1and4. Referring collectively toFIGS.4and5, method500begins in block510.

At block510, method500includes receiving, by encoder circuit401b, data packet425ahaving a plurality of bits arranged in an original order for sending via interface circuit410that includes a plurality of segments427. As illustrated, data packet425ais received by encoder circuit401bfrom network460c. Network460cmay by coupled to one or more agents in integrated circuit405a, one of which sources a transaction that includes sending data packet425ato a destination agent on integrated circuit405b. Data packet425ais sent via interface circuit410which is coupled to interface circuit412of integrated circuit405bby physical connections440. From interface circuit412, the data packet is sent via network470cto the destination agent. Interface circuits410and412are each implemented using a plurality of segments427and429, respectively.

Method500, at block520, further includes determining, by encoder circuit401b, that a group of the plurality of bits corresponds to an idle value for a subset of the plurality of segments429. As shown inFIG.4, segments427are coupled, via physical connections440, to respective ones of segments429. When no data packet is available for sending, by interface circuit410, an idle value may be generated by the segments427that causes the respective segment429to enter the idle state as described above. In the current embodiment, the idle state is implemented per segment. If segment427hsends the idle value while segments427e-427gsend other valid information, then segment429henters the idle state while segments429e-429greceive the information from their respective segments427. This segmented implementation allows segments427e-427hto assert idle values when encoder circuit401adoes not have a data packet to send, while segments427a-427dmay be sending data packet425a.

Accordingly, to ensure data packet425is sent and received without unintentionally causing one of segments429a-429dto enter the idle state, method500includes determining values of portions of data packet425that align with ones of segments427a-427d. Determined values of these portions that are the same as the idle value are identified. For the example ofFIG.5, portions data packet425athat are aligned with segments427band427dare identified as being the same as the idle value.

At block530, the method further includes self-encoding, by encoder circuit401b, data packet425aby replacing at least a portion of the group of bits with a mask value that indicates, to decoder circuit403b, how to decode the self-encoded data packet. As illustrated, replacing the at least a portion of the group of bits with the mask value includes replacing bits of segment427bwith the mask value. For data packet425a, however, the mask value is sent in a particular one of segments427a-427d, in this example, segment427a. Accordingly, replacing the idle value associated with segment427bincludes shifting the bits of segment427ainto segment427b, and placing the mask value in segment427a. Placing the mask value in segment427aincludes setting one or more bits of the segment427a(e.g., the most or least significant bit) to a value that indicates that the mask value is included in segment427a. As previously described, the most significant bit of segment427amay be set to a logic high value to indicate that the mask value is included.

In addition, removing idle values from data packet425aincludes replacing bits of segment427dwith a predetermined value that is different than the idle value. Since the value of the portion of data packet425athat aligns with segment427dis also equal to the idle value, this value is replaced with the particular value, e.g., the complement of the idle value, to prevent the sending of an unintended idle value to segment429d. The mask value placed into segment427aincludes indications that data packet425aincludes idle values in the portions aligned with segments427band427d. Segments427a-427dnow hold a self-encoded version of data packet425a. As used herein, “self-encoded” refers to a data packet, including a given number of bits, that is encoded to include one or more control signals without increasing the number of bits of the data packet and without loss of information included in the unencoded version of the data packet.

Method500also includes, at block540, sending, by interface circuit410using segments427a-427d, the self-encoded data packet to decoder circuit403b. After encoder circuit401bgenerates the self-encoded version of data packet425a, the self-encoded data packet is sent via segments427a-427dto corresponding ones of segments429a-429d. Segments427band427d, which, in the original version of data packet425awere aligned with portions that corresponded to the idle value, now transmit non-idle values that are received by segments429aband429d, respectively, without triggering an idle state.

In some embodiments, method500may end in block540, or in other embodiments, may repeat in response to new data to be exchanged between encoder circuit401band decoder circuit403b. It is noted that the method ofFIG.5is merely an example for encoding a data packet that includes an idle value.

Turning now toFIG.6, a flow diagram for an embodiment of a method for decoding a received data packet that includes a mask value is illustrated. In a similar manner as for method500above, method600may be performed by a system that includes an decoder circuit and an interface circuit with a plurality of segments, such as systems200and400inFIGS.2and4. Method600may be performed in response to a performance of method500. Referring collectively toFIGS.4and6, method600begins in block610after block540of method500is performed.

Method600, at block610, includes receiving, by decoder circuit403b, the self-encoded data packet. As illustrated, the self-encoded version of data packet425ais received via segments429a-429dof interface circuit412. As described above in regards toFIG.5, the received self-encoded data packet includes a mask value in segment429a.

At block620, method600also includes extracting, by decoder circuit403b, the mask value from the received data packet. As described above, encoder circuit401bincludes an indication that the value sent via segment427aand received via segment429aincludes a mask value that identifies ones of the segments that should have values corresponding to the idle value, but instead hold non-idle values to avoid triggering unintentional idle states. In some embodiments, the mask value is read from segment429aand then stored into a register or memory location, such as register230inFIG.2. Decoder circuit403bidentifies the inclusion of the mask value by detecting a portion of bits set to a particular value, e.g., the most significant bit of segment429amay be a logic high value.

Method600further includes, at block630, replacing, by decoder circuit403b, the mask value in data packet425bwith a restoration value that corresponds to the idle value. Since the mask value was not a part of the original data packet425a, decoder circuit replaces the mask value with the restoration value. Since encoder circuit401bremoves idle values from self-encoded data packets, decoder circuit403bis configured to use the idle value as a restoration value.

At block640, method600further includes reconstructing, by decoder circuit403busing the mask value, data packet425b. Using the mask value, decoder circuit403bidentifies that segments429band429dshould have the restoration value rather than the values they hold. In addition, decoder circuit403buses the mask value to determine that the value held in segment429bhas been shifted and should be shifted back to align with segment429a. After shifting the value in segment429bto the least significant portion of data packet425b, the restoration value is placed into the portions of data packet425bthat align with segments429band429d. Data packet425bis now decoded and has a same value as original data packet425a. Method600may end after performing the operations of block640, or may repeat if another self-encoded data packet is ready to be received.

Use of such encoding and decoding techniques as described in methods500and600, as well as the remainder of this disclosure, may enable use of idling techniques between two or more interfaces without increasing a number of signals between the two interfaces. By self-encoding data packets, additional control information (e.g., a mask value) may be added to the data packets when applicable to identify information that may otherwise create an unintentional reaction (e.g., an idle state).

It is noted that the method ofFIG.6is merely an example for decoding self-encoded data packets. Method600may be performed by any instances of the integrated circuits disclosed inFIGS.1-4. Variations of the disclosed methods are contemplated, including combinations of operations of methods500and600, such as performing the methods in series.

FIGS.1-6illustrate apparatus and methods for a system that includes encoding and decoding data packets sent between two or more interface circuits. Any embodiment of the disclosed systems may be included in one or more of a variety of computer systems, such as a desktop computer, laptop computer, smartphone, tablet, wearable device, and the like. In some embodiments, the circuits described above (e.g., integrated circuits405aand405b) may be implemented on one or more systems-on-chip (SoCs) or other type of integrated circuits. A block diagram illustrating an embodiment of computer system700is illustrated inFIG.7. Computer system700may, in some embodiments, include any disclosed embodiment of systems100,200, and400. Integrated circuits405aand405b, in some embodiments, may each correspond to one instance, or to respective portions, of computer system700.

In the illustrated embodiment, the system700includes at least one instance of a system on chip (SoC)706which may include multiple types of processing circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a communication fabric, and interfaces to memories and input/output devices. In some embodiments, one or more processors in SoC706includes multiple execution lanes and an instruction issue queue. In various embodiments, SoC706is coupled to external memory702, peripherals704, and power supply708. In an embodiment, SoC706may be implemented using a combination of integrated circuits405aand405bcoupled together by physical connections440to operate as a single SoC.

A power supply708is also provided which supplies the supply voltages to SoC706as well as one or more supply voltages to the memory702and/or the peripherals704. In various embodiments, power supply708represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoC706is included (and more than one external memory702is included as well).

The peripherals704include any desired circuitry, depending on the type of system700. For example, in one embodiment, peripherals704includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals704also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals704include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.

As illustrated, system700is shown to have application in a wide range of areas. For example, system700may be utilized as part of the chips, circuitry, components, etc., of a desktop computer710, laptop computer720, tablet computer730, cellular or mobile phone740, or television750(or set-top box coupled to a television). Also illustrated is a smartwatch and health monitoring device760. In some embodiments, the smartwatch may include a variety of general-purpose computing related functions. For example, the smartwatch may provide access to email, cellphone service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health related functionality. For example, a health monitoring device may monitor a user's vital signs, track proximity of a user to other users for the purpose of epidemiological social distancing, contact tracing, provide communication to an emergency service in the event of a health crisis, and so on. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring related functions. Other wearable devices770are contemplated as well, such as devices worn around the neck, devices attached to hats or other headgear, devices that are implantable in the human body, eyeglasses designed to provide an augmented and/or virtual reality experience, and so on.

System700may further be used as part of a cloud-based service(s)780. For example, the previously mentioned devices, and/or other devices, may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Also illustrated inFIG.7is the application of system700to various modes of transportation790. For example, system700may be used in the control and/or entertainment systems of aircraft, trains, buses, cars for hire, private automobiles, waterborne vessels from private boats to cruise liners, scooters (for rent or owned), and so on. In various cases, system700may be used to provide automated guidance (e.g., self-driving vehicles), general systems control, and otherwise.

It is noted that the wide variety of potential applications for system700may include a variety of performance, cost, and power consumption requirements. Accordingly, a scalable solution enabling use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be beneficial. These and many other embodiments are possible and are contemplated. It is noted that the devices and applications illustrated inFIG.7are illustrative only and are not intended to be limiting. Other devices are possible and are contemplated.

As disclosed in regards toFIG.7, computer system700may include two or more integrated circuits coupled together and included within a personal computer, smart phone, tablet computer, or other type of computing device. A process for designing and producing an integrated circuit using design information is presented below inFIG.8.

FIG.8is a block diagram illustrating an example of a non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. The embodiment ofFIG.8may be utilized in a process to design and manufacture integrated circuits, such as, for example, integrated circuits405aand405bas shown inFIG.4. In the illustrated embodiment, semiconductor fabrication system820is configured to process the design information815stored on non-transitory computer-readable storage medium810and fabricate integrated circuit830(e.g., integrated circuits405aand405b) based on the design information815.

Design information815may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information815may be usable by semiconductor fabrication system820to fabricate at least a portion of integrated circuit830. The format of design information815may be recognized by at least one semiconductor fabrication system, such as semiconductor fabrication system820, for example. In some embodiments, design information815may include a netlist that specifies elements of a cell library, as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit830may also be included in design information815. Such cell libraries may include information indicative of device or transistor level netlists, mask design data, characterization data, and the like, of cells included in the cell library.

Integrated circuit830may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information815may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (gdsii), or any other suitable format.

In various embodiments, integrated circuit830is configured to operate according to a circuit design specified by design information815, which may include performing any of the functionality described herein. For example, integrated circuit830may include any of various elements shown or described herein. Further, integrated circuit830may be configured to perform various functions described herein in conjunction with other components. Further, the functionality described herein may be performed by multiple connected integrated circuits, such as integrated circuits405aand405binFIG.4.

The present disclosure includes references to “embodiments,” which are non-limiting implementations of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments will necessarily manifest any or all of the potential advantages described herein.

Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

For example, while the appended dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated, including the following: Claim3(could depend from any of claims1-2); claim4(any preceding claim); claim5(claim4), etc. Where appropriate, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) suggest corresponding claims of another statutory type (e.g., method).

References to the singular forms such “a,” “an,” and “the” are intended to mean “one or more” unless the context clearly dictates otherwise. Reference to “an item” in a claim thus does not preclude additional instances of the item.

When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.

Various “labels” may proceed nouns in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third” when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.

The hardware circuits may include any combination of combinatorial logic circuitry, clocked storage devices such as flops, registers, latches, etc., finite state machines, memory such as static random access memory or embedded dynamic random access memory, custom designed circuitry, analog circuitry, programmable logic arrays, etc. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.”

In an embodiment, hardware circuits in accordance with this disclosure may be implemented by coding the description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that may be transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and may further include other circuit elements (e.g. passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function. This unprogrammed FPGA may be “configurable to” perform that function, however.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.