Non-volatile memory with reduced program speed variation

A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.

BACKGROUND

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery).

As memory structures increase in density, it becomes more challenging to maintain the integrity of the data being stored.

DETAILED DESCRIPTION

In order to reduce errors, a memory system is proposed that programs different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer. For example, a plurality of non-volatile memory cells include a first group of memory cells at a first range of one or more distances from to one or more edges of the word line layer and a second group of memory cells at a second range of one or more distances from to one or more edges of the word line layer. The second range of distances are greater than the first range of distances. A control circuit is configured to program the first group of memory cells using a first target level for a first data state and program the second group of memory cells using a second target level for the first data state. The first target level is higher in voltage than the second target level such that on completion of programming the first group of memory cells are in a first threshold voltage distribution and the second group of memory cells are in a second threshold voltage distribution that is lower in voltage than the first threshold voltage distribution. The above example mentioned a first target level and a second target level, both for a first data state. Other embodiments can use a first set of target levels and a second set of target level, both for a set of data states, where the first set of target levels are higher in voltage than corresponding target levels of the second set of target levels.

FIGS. 1-4Fdescribe one set of examples of a memory system that can be used to implement the technology proposed herein.FIG. 1is a functional block diagram of an example memory device. The components depicted inFIG. 1are electrical circuits. Memory device100includes one or more memory die108. Each memory die108includes a three dimensional memory structure126of memory cells (such as, for example, a 3D array of memory cells), control circuitry110, and read/write circuits128. In other embodiments, a two dimensional array of memory cells can be used. Memory structure126is addressable by word lines via a row decoder124and by bit lines via a column decoder132. The read/write circuits128include multiple sense blocks150including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells (connected to the same word line) to be read or programmed in parallel. In some systems, a controller122is included in the same memory device100as the one or more memory die108. However, in other systems, the controller can be separated from the memory die108. In some embodiments controller122will be on a different die than memory die108. In some embodiments, one controller122will communicate with multiple memory die108. In other embodiments, each memory die108has its own controller. Commands and data are transferred between the host140and controller122via a data bus120, and between controller122and the one or more memory die108via lines118. In one embodiment, memory die108includes a set of input and/or output (I/O) pins that connect to lines118.

Memory structure126may comprise one or more arrays of memory cells including a 3D array. The memory structure may comprise a monolithic three dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate. In one embodiment, memory structure126implements three dimensional NAND flash memory. Other embodiments include two dimensional NAND flash memory, two dimensional NOR flash memory, ReRAM cross-point memories, magnetoresistive memory (e.g., MRAM), phase change memory (e.g., PCRAM), and others.

Control circuitry110cooperates with the read/write circuits128to perform memory operations (e.g., erase, program, read, and others) on memory structure126, and includes a state machine112, an on-chip address decoder114, a power control module116and a temperature detection circuit116. The state machine112provides die-level control of memory operations, such as programming different memory cells to different final targets for a common data state based on distance to an edge of a word line layer. Temperature detection circuit113(which is an example of a memory temperature sensor on memory die108) is configured to detect temperature at the memory die108, and can be any suitable temperature detection circuit known in the art. In one embodiment, state machine112is programmable by the software. In other embodiments, state machine112does not use software and is completely implemented in hardware (e.g., electrical circuits). In one embodiment, control circuitry110includes registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.

The on-chip address decoder114provides an address interface between addresses used by host140or controller122to the hardware address used by the decoders124and132. Power control module116controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word line layers (discussed below) in a 3D configuration, select transistors (e.g., SGS and SGD transistors, described below) and source lines. Power control module116may include charge pumps for creating voltages. The sense blocks include bit line drivers. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

Any one or any combination of control circuitry110, state machine112, decoders114/124/132, temperature detection circuit113, power control module116, sense blocks150, read/write circuits128, and/or controller122can be considered a control circuit that performs the functions described herein.

The (on-chip or off-chip) controller122(which in one embodiment is an electrical circuit) may comprise one or more processors122c, ROM122a, RAM122b, Memory Interface122dand a system temperature sensor122e, all of which are interconnected. One or more processors122cis one example of a control circuit. Other embodiments can use state machines or other custom circuits designed to perform one or more functions. The storage devices (ROM122a, RAM122b) comprises code such as a set of instructions, and the processor122cis operable to execute the set of instructions to provide the functionality described below related to programming different memory cells to different final targets for a common data state based on distance to an edge of a word line layer. Alternatively or additionally, processor122ccan access code from a storage device in the memory structure, such as a reserved area of memory cells connected to one or more word lines. Memory interface122d, in communication with ROM122a, RAM122band processor122c, is an electrical circuit (electrical interface) that provides an electrical interface between controller122and one or more memory die108. For example, memory interface122dcan change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. Processor122ccan issue commands to control circuitry110(or any other component of memory die108) via Memory Interface122d.

Multiple memory elements in memory structure126may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND flash memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected memory cells and select gate transistors.

A NAND flash memory array may be configured so that the array is composed of multiple NAND strings of which a NAND string is composed of multiple memory cells sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory cells may be otherwise configured.

The memory cells may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations, or in structures not considered arrays.

By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form vertical NAND strings that traverse across multiple horizontal levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

The interface between controller122and non-volatile memory die108may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, memory system100may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system100may be part of an embedded memory system. For example, the flash memory may be embedded within the host. In other example, memory system100can be in the form of a solid state drive (SSD) drive.

In some embodiments, non-volatile memory system100includes a single channel between controller122and non-volatile memory die108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the controller and the memory die, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if a single channel is shown in the drawings.

As depicted inFIG. 3, controller112includes a front end module208that interfaces with a host, a back end module210that interfaces with the one or more non-volatile memory die108, and various other modules that perform functions which will now be described in detail.

The components of controller122depicted inFIG. 3may take the form of a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro) processor or processing circuitry that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. For example, each module may include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or in addition, each module may include software stored in a processor readable device (e.g., memory) to program a processor for controller122to perform the functions described herein. The architecture depicted inFIG. 2is one example implementation that may (or may not) use the components of controller122depicted inFIG. 1(i.e. RAM, ROM, processor, interface).

Referring again to modules of the controller122, a buffer manager/bus control214manages buffers in random access memory (RAM)216and controls the internal bus arbitration of controller122. A read only memory (ROM)218stores system boot code. Although illustrated inFIG. 2as located separately from the controller122, in other embodiments one or both of the RAM216and ROM218may be located within the controller. In yet other embodiments, portions of RAM and ROM may be located both within the controller122and outside the controller. Further, in some implementations, the controller122, RAM216, and ROM218may be located on separate semiconductor die.

Front end module208includes a host interface220and a physical layer interface (PHY)222that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface220can depend on the type of memory being used. Examples of host interfaces220include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface220typically facilitates transfer for data, control signals, and timing signals.

Back end module210includes an error correction code (ECC) engine224that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer226generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die108. A RAID (Redundant Array of Independent Dies) module228manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the non-volatile memory system100. In some cases, the RAID module228may be a part of the ECC engine224. Note that the RAID parity may be added as an extra die or dies as implied by the common name, but it may also be added within the existing die, e.g. as an extra plane, or extra block, or extra WLs within a block. A memory interface230provides the command sequences to non-volatile memory die108and receives status information from non-volatile memory die108. In one embodiment, memory interface230may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer232controls the overall operation of back end module210.

One embodiment includes a programming manager236, which can be used to manage (in conjunction with the circuits on the memory die) the programming of memory cells closer to an edge of the word line layer and memory cells further from the edge of the word line layer to a first data state representing first data such that the memory cells closer to the edge of the word line layer are programmed to a first final threshold voltage distribution using a first final verify level and the memory cells further from the edge of the word line layer are programmed to a second final threshold voltage distribution using a second verify level, where the second verify level is lower than the first verify level and the second final threshold voltage distribution is lower in voltage than the first threshold voltage distribution. For example, in one embodiment, programming manager236may perform and/or manage the processes ofFIGS. 7A, 12, 14 and 15, described below. More details of programming manager236are also provided below with respect to those figures. Programming manager236can be an electrical circuit, a set of one or more software modules, or a combination of a circuit and software.

Additional components of system100illustrated inFIG. 2include media management layer238, which performs wear leveling of memory cells of non-volatile memory die108. System100also includes other discrete components240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller122. In alternative embodiments, one or more of the physical layer interface222, RAID module228, media management layer238and buffer management/bus controller214are optional components that are not necessary in the controller122.

The Flash Translation Layer (FTL) or Media Management Layer (MML)238may be integrated as part of the flash management that may handle flash errors and interfacing with the host. In particular, MML may be a module in flash management and may be responsible for the internals of NAND management. In particular, the MML238may include an algorithm in the memory device firmware which translates writes from the host into writes to the flash memory126of die108. The MML238may be needed because: 1) the flash memory may have limited endurance; 2) the flash memory126may only be written in multiples of pages; and/or 3) the flash memory126may not be written unless it is erased as a block. The MML238understands these potential limitations of the flash memory126which may not be visible to the host. Accordingly, the MML238attempts to translate the writes from host into writes into the flash memory126. As described below, erratic bits may be identified and recorded using the MML238. This recording of erratic bits can be used for evaluating the health of blocks and/or word lines (the memory cells on the word lines).

Controller122may interface with one or more memory dies108. In one embodiment, controller122and multiple memory dies (together comprising non-volatile storage system100) implement a solid state drive (SSD), which can emulate, replace or be used instead of a hard disk drive inside a host, as a NAS device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not be made to work as a hard drive.

Some embodiments of a non-volatile storage system will include one memory die108connected to one controller122. However, other embodiments may include multiple memory die108in communication with one or more controllers122. In one example, the multiple memory die can be grouped into a set of memory packages. Each memory package includes one or more memory die in communication with controller122. In one embodiment, a memory package includes a printed circuit board (or similar structure) with one or more memory die mounted thereon. In some embodiments, a memory package can include molding material to encase the memory dies of the memory package. In some embodiments, controller122is physically separate from any of the memory packages.

FIG. 3is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory structure126, which includes a plurality memory cells. For example,FIG. 3shows a portion of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-216 alternating dielectric layers and conductive layers, for example, 96 data word line layers, 8 select layers, 4 dummy word line layers and 108 dielectric layers. More or less than 108-216 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four “fingers” by local interconnects LI (isolation areas).FIG. 3only shows two fingers and two local interconnects LI. Below and the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that inFIG. 3, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory structure126is provided below with respect toFIG. 4A-4F.

FIG. 4Ais a block diagram explaining one example organization of memory structure126, which is divided into two planes302and304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, for two plane memory, the block IDs are usually such that even blocks belong to one plane and odd blocks belong to another plane; therefore, plane302includes block 0, 2, 4, 6, . . . and plane304includes blocks 1, 3, 5, 7, . . . . In on embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure126to enable the signaling and selection circuits.

FIGS. 4B-4Fdepict an example 3D NAND structure.FIG. 4Bis a block diagram depicting a top view of a portion of one block from memory structure126. The portion of the block depicted inFIG. 4Bcorresponds to portion306in block 2 ofFIG. 4A. As can be seen fromFIG. 4B, the block depicted inFIG. 4Bextends in the direction of332. In one embodiment, the memory array will have 60 layers. Other embodiments have less than or more than 60 layers. However,FIG. 4Bonly shows the top layer.

FIG. 4Bdepicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors and multiple memory cells. In one embodiment, each vertical column implements a NAND string and, therefore, can be referred to as a memory column. A memory column can implement other types of memory in addition to NAND.FIG. 4Bdepicts vertical columns422,432,442and452. Vertical column422implements NAND string482. Vertical column432implements NAND string484. Vertical column442implements NAND string486. Vertical column452implements NAND string488. More details of the vertical columns are provided below. Since the block depicted inFIG. 4Bextends in the direction of arrow330and in the direction of arrow332, the block includes more vertical columns than depicted inFIG. 4B

FIG. 4Balso depicts a set of bit lines415, including bit lines411,412,413,414, . . .419.FIG. 4Bshows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line. For example, bit line414is connected to vertical columns422,432,442and452.

The block depicted inFIG. 4Bincludes a set of isolation areas402,404,406,408and410that serve to divide each layer of the block into four regions; for example, the top layer depicted inFIG. 4Bis divided into regions420,430,440and450, which are referred to as fingers. In the layers of the block that implement memory cells, the four regions are referred to as word line fingers that are separated by the isolation areas (also serving as local interconnects). In one embodiment, the word line fingers on a common level of a block connect together at the end of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line only connects to one vertical column in each of regions420,430,440and450. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block. In one embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together); therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

Isolation areas402,404,406,408and410also connect the various layers to a source line below the vertical columns In one embodiment, isolation areas402,404,406,408and410are filled with a layer of SiO2(blocking) and a layer of poly-silicon (source line connection).

AlthoughFIG. 4Bshows each region having four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.

FIG. 4Balso shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG. 4Cdepicts a portion of an embodiment of three dimensional memory structure126showing a cross-sectional view along line AA ofFIG. 4B. This cross sectional view cuts through vertical columns432and434and region430(seeFIG. 4B). The structure ofFIG. 4Cincludes four drain side select layers SGD0, SGD1, SGD2and SGD3; four source side select layers SGS0, SGS1, SGS2and SGS3; four dummy word line layers DD0, DD1, DS0and DS1; and forty eight data word line layers WLL0-WLL47for connecting to data memory cells. Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than four dummy word line layers, and more or less than forty eight word line layers (e.g., 96 word line layers). Vertical columns432and434are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each vertical column comprises a NAND string. For example, vertical column432comprises NAND string484. Below the vertical columns and the layers listed below is substrate101, an insulating film454on the substrate, and source line SL. The NAND string of vertical column432has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement withFIG. 4B,FIG. 4Cshow vertical column432connected to Bit Line414via connector415. Isolation areas404and406are also depicted.

For ease of reference, drain side select layers SGD0, SGD1, SGD2and SGD3; source side select layers SGS0, SGS1, SGS2and SGS3; dummy word line layers DD0, DD1, DS0and DS1; and word line layers WLL0-WLL47collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL59. For example, dielectric layers DL49is above word line layer WLL43and below word line layer WLL44. In one embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layer WLL0-WLL47connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0and DS1connect to dummy memory cells. A dummy memory cell does not store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. Drain side select layers SGD0, SGD1, SGD2and SGD3are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, SGS2and SGS3are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 4Ddepicts a logical representation of the conductive layers (SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, SGS2, SGS3, DD0, DD1, DS0, DS1, and WLL0-WLL47) for the block that is partially depicted inFIG. 4C. As mentioned above with respect toFIG. 4B, in one embodiment isolation areas402,404,406,408and410break up each conductive layers into four regions or fingers. For example, word line layer WLL31is divided into regions460,462,464and466. For word line layers (WLL0-WLL31), the regions are referred to as word line fingers; for example, word line layer WLL46is divided into word line fingers460,462,464and466. In one embodiment, the four word line fingers on a same level are connected together. In another embodiment, each word line finger operates as a separate word line.

Drain side select gate layer SGD0(the top layer) is also divided into regions420,430,440and450, also known as fingers or select line fingers. In one embodiment, the four select line fingers on a same level are connected together. In another embodiment, each select line finger operates as a separate word line.

FIG. 4Edepicts a cross sectional view of region429ofFIG. 4Cthat includes a portion of vertical column432. In one embodiment, the vertical columns are round and include four layers; however, in other embodiments more or less than four layers can be included and other shapes can be used. In one embodiment, vertical column432includes an inner core layer470that is made of a dielectric, such as SiO2. Other materials can also be used. Surrounding inner core470is polysilicon channel471. Materials other than polysilicon can also be used. Note that it is the channel471that connects to the bit line. Surrounding channel471is a tunneling dielectric472. In one embodiment, tunneling dielectric472has an ONO structure. Surrounding tunneling dielectric472is charge trapping layer473, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 4Edepicts dielectric layers DLL49, DLL50, DLL51, DLL52and DLL53, as well as word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each of the word line layers includes a word line region476surrounded by an aluminum oxide layer477, which is surrounded by a blocking oxide (SiO2) layer478. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel471, tunneling dielectric472, charge trapping layer473, blocking oxide layer478, aluminum oxide layer477and word line region476. For example, word line layer WLL47and a portion of vertical column432comprise a memory cell MC1. Word line layer WLL46and a portion of vertical column432comprise a memory cell MC2. Word line layer WLL45and a portion of vertical column432comprise a memory cell MC3. Word line layer WLL44and a portion of vertical column432comprise a memory cell MC4. Word line layer WLL43and a portion of vertical column432comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer473which is associated with the memory cell. These electrons are drawn into the charge trapping layer473from the channel471, through the tunneling dielectric472, in response to an appropriate voltage on word line region476. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

FIG. 4Fshows physical word lines WLL0-WLL47running across the entire block. The structure ofFIG. 4Gcorresponds to portion306in Block 2 ofFIGS. 4A-F, including bit lines411,412,413,414, . . .419. Within the block, each bit line connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2and SGD3are used to determine which of the four NAND strings connect to the associated bit line. The block can also be thought of as divided into four sub-blocks SB0, SB1, SB2and SB3. Sub-block SB0corresponds to those vertical NAND strings controlled by SGD0and SGS0, sub-block SB1corresponds to those vertical NAND strings controlled by SGD1and SGS1, sub-block SB2corresponds to those vertical NAND strings controlled by SGD2and SGS2, and sub-block SB3corresponds to those vertical NAND strings controlled by SGD3and SGS3.

Although the example memory system ofFIGS. 4-4Fis a three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein. For example, floating gate memories (e.g., NAND-type and NOR-type flash memory ReRAM memories, magnetoresistive memory (e.g., MRAM), and phase change memory (e.g., PCRAM) can also be used.

Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a spin valve and is the simplest structure for an MRAM bit. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.

Phase change memory (PCRAM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave.

The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.FIG. 5illustrates example threshold voltage distributions for the memory cell array when each memory cell stores three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell).FIG. 5shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S0represents memory cells that are erased. The other seven threshold voltage distributions (data states) S1-S17represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected.

FIG. 5also shows seven read reference voltages, Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., S0, S1, S2, S3, . . . ) a memory cell is in.

FIG. 5also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. When programming memory cells to data state S1, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv1. When programming memory cells to data state S2, the system will test whether the memory cells have threshold voltages greater than or equal to Vv2. When programming memory cells to data state S3, the system will determine whether memory cells have their threshold voltage greater than or equal to Vv3. When programming memory cells to data state S4, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv4. When programming memory cells to data state S5, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv5. When programming memory cells to data state S6, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv6. When programming memory cells to data state S7, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv7.

In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S0directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0to data state S1, other memory cells are being programmed from data state S0to data state S2and/or from data state S0to data state S3, and so on. The arrows ofFIG. 6represent the full sequence programming. The technology described herein can also be used with other types of programming in addition to full sequence programming (including, but not limited to, multiple stage/phase programming). In some embodiments, data states S1-S7can overlap, with controller122relying on ECC to identify the correct data being stored.

FIG. 6is a table describing one example of an assignment of data values to data states. In the table ofFIG. 6, S0—111. S1=110, S2=200, S3=000, S4=010, S5=011, S6=001 and S7=101. Other encodings of data can also be used. No particular data encoding is required by the technology disclosed herein.

In one embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state S0, the erased state. In the embodiment ofFIG. 6, all bits stored in a memory cell are 1 when the memory cells is erased (e.g., in data state S0).

FIG. 7Ais a flowchart describing one embodiment of a process for programming that is performed by controller122. In some embodiments, rather than have a dedicated controller, the host can perform the functions of the controller. In step702, controller122sends instructions to one or more memory die108to program data. In step704, controller122sends one or more addresses to one or more memory die108. The one or more logical addresses indicate where to program the data. In step706, controller122sends the data to be programmed to the one or more memory die108. In step708, controller122receives a result of the programming from the one or more memory die108. Example results include that the data was programmed successfully, an indication that the programming operation failed, and indication that the data was programmed but at a different location, or other result. In step710, in response to the result received in step708, controller122updates the system information that it maintains. In one embodiment, the system maintains tables of data that indicate status information for each block. This information may include a mapping of logical addresses to physical addresses, which blocks/word lines are open/closed (or partially opened/closed), which blocks/word lines are bad, etc.

In some embodiments, before step702, controller122would receive host data and an instruction to program from the host, and the controller would run the ECC engine224to create code words from the host data, as known in the art and described in more detail below. These code words are the data transmitted in step706. controller can also scramble the data to achieve wear leveling with respect to the memory cells.

FIG. 7Bis a flowchart describing one embodiment of a process for programming. The process ofFIG. 7Bis performed by the memory die in response to the steps ofFIG. 7A(i.e., in response to the instructions, data and addresses from controller122). In one example embodiment, the process ofFIG. 7Bis performed on memory die108using the one or more control circuits discussed above, at the direction of state machine112. The process ofFIG. 7Bcan also be used to implement the full sequence programming discussed above. Additionally, the process ofFIG. 7Bcan be used to implement each phase of a multi-phase programming process.

Typically, the program voltage applied to the control gates (via a selected word line) during a program operation is applied as a series of program pulses. Between programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step770ofFIG. 7B, the programming voltage (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine112is initialized at1. In step772, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, the group of memory cells being programmed concurrently are all connected to the same word line (the selected word line). The unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes known in the art. If a memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to inhibit programming In step772, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently. That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they have been locked out from programming.

In step774, the appropriate memory cells are verified using the appropriate set of verify reference voltages to perform one or more verify operations. In one embodiment, the verification process is performed by applying the testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage.

In step776, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step778. If, in776, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step780.

In step780, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine, the controller, or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step782, it is determined whether the count from step780is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed memory cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step778. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, step780will count the number of failed cells for each sector, each target data state or other unit, and those counts will individually or collectively be compared to a threshold in step782.

In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during a read process to allow for future errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.

If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step784and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 12, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step788. This is one example of a program fault. If the program counter PC is less than the program limit value PL, then the process continues at step786during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.5 volts). After step786, the process loops back to step772and another program pulse is applied to the selected word line so that another iteration (steps772-786) of the programming process ofFIG. 7Bis performed.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, ofFIG. 5) or verify operation (e.g. see verify reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7ofFIG. 5) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

In some embodiments, controller122receives a request from the host (or a client, user, etc.) to program host data (data received from the host) into the memory system. In some embodiments, controller122arranges the host data to be programmed into units of data. For example, controller122can arrange the host data into pages, word line units, blocks, jumbo blocks, or other units. For purposes of this document, a block is a physical grouping of memory cells. In one example, a block is a unit of erase. However, in other examples a block need not be a unit of erase. In one example, a block comprises a set of memory cells connected by uninterrupted word lines such as a set of NAND strings connected to a common set of word lines. Other physical arrangement can also be used.

Step772ofFIG. 7Bincludes applying a program voltage pulse on the selected word line. Step774ofFIG. 7Bincludes verification, which in some embodiments comprises applying the verify reference voltages on the selected word line. As steps772and774are part of an iterative loop, the program voltage is applied as a series of voltage pulses that step up in magnitude. Between voltage pulses, verify reference voltages are applied. This is depicted inFIG. 7C, which shows program voltage pulses792,794and796, applied during three successive iterations of step772. Between program voltage pulses792,794and796, the system tests the memory cells to determine whether threshold voltages of the memory cells are greater than the respective verify reference voltages by applying the verify references voltages as verify pulses.

Looking back atFIG. 4B, the memory structure is depicted with four rows of memory holes between isolation areas402,404,406,408and410. In some embodiments, when memory cells are further scaled down, one approach is to reduce the number of isolation areas which are used to separate sub-blocks or increase the number of memory holes without increasing the number of isolation areas. The isolation areas are also used to let in etchant to etch away silicon nitride (SiN) layers inside the multiple oxide/nitride layer stack and replace them with tungsten layers which will be used as word line layers. That is when the memory stack is first fabricated, alternating layers of dielectric material (oxide) and silicon nitride are deposited or otherwise laid down. Then the memory holes are created through the alternating layers of oxide/nitride. Various materials that make up the memory holes are then added, as depicted inFIG. 4E. Then the isolation areas are carved into the stack. Subsequently, an etchant is inserted via the insolation areas in order to etch out the silicon nitride. Once the silicon nitride is removed, tungsten is used to replace the silicon nitride. This tungsten will become the word line layers.

If the number of isolation areas is reduced as compared t the number of memory holds, it means more memory holes will exist between every two neighboring isolation areas. This also means larger areas of silicon nitride need to be etched away and replaced by tungsten between every two neighboring isolation areas and, therefore, the silicon nitride etching process will take a longer time. Since the silicon nitride layers surrounding the outer memory holes (memory holes which are closer to the isolation areas) will be etched earlier by the etchant (typically hot phosphoric acid) coming in from vertically etched through isolation areas, while the silicon nitride layers surrounding the inner memory holes (memory holes which are closer to the isolation areas) will be etched later, the dielectric layers (SiO2layers) inside the outer memory holes will be exposed to the etchant for a longer time. Due to this exposure difference, the SiO2layers of the outer memory holes will be etched away more than that of the inner memory holes. This will cause thinner dielectric layer thickness inside the outer memory holes which leads to faster memory cell programming and erasing. It will also lead to comparatively thicker dielectric layer thickness for the inner memory holes which leads to slower memory programming and erase speeds.

FIG. 8shows a portion of a block which includes isolation areas802,804and806. Between neighboring isolation areas are eight rows of memory holes. For example, between isolation area802and isolation area804is word line finger810having eight rows of memory holes. Row of memory holes820and row of memory holes826are outer memory holes. Row of memory holes822and row of memory holes824are inner memory holes. Arrows842and844depict the direction of the etchant discussed above as it moves from its respective isolation area (802and804) toward the inner memory holes of rows822and824. As discussed above, the memory holes of rows820and826will be etched earlier and longer. Therefore, dielectric layers of the memory holes of rows820and826will be thinner than the dielectric areas of rows of memory holes822and824. For example, blocking dielectric478(seeFIG. 4E) will be thinner for the memory cells of memory holes in rows820and826, as compared to the memory cells of memory holes in rows822and824. In some cases, the inner word line dielectric layers (e.g., DL0, DL1, DL2, . . . ) will also be thinner.

Because of the thinner blocking dielectrics, memory cells of rows820and826will be faster programming memory cells. Due to the thicker blocking dielectrics, the memory cells of rows822and824will be slower programming memory cells. A faster programming memory cell is a memory cell that changes threshold voltage faster than a slower memory cell under the same programming conditions. Conversely, a slower memory cell is a memory cell that changes its threshold voltage slower than a faster memory cell under the same programming conditions.

FIG. 8also shows word line finger812between isolation area804and isolation area806. Word line finger812includes eight rows of memory holes including outer memory holes of rows828and834and inner memory holes of rows830and832. Arrows846and848show the direction of the etchant from the isolation areas into the inner memory holes. As discussed above, the memory cells in the outer memory holes will have thinner blocking dielectrics than inner memory holes, therefore, the memory cells in the outer memory holes of rows828and834will be faster programming memory cells while the memory cells of inner memory holes of rows830and832will have thicker blocking dielectrics and be slower programming memory cells.

Memory holes (also known an memory columns) can be grouped together to form groups based on their distance from the nearest isolation areas. In this way, memory cells program speed difference within the same group can be significantly reduced. However, a program speed difference between memory cells in different groups (within the same block) may still remain. Since all groups are connected to the same word line layer in one block (e.g., four word line fingers in a word line layer), a group with slower programming memory cells needs a higher final program voltage (higher magnitude voltage in last iteration of step772ofFIG. 7B) to complete programming. This higher final program voltage may cause extra program disturb for erased memory cells (data state S0) in the groups of memory cells having faster programming memory cells. Because of this, the memory cell program speed difference in the various groups may have a negative impact for program disturb.

As discussed above, memory holes can be grouped together to form groups based on their distance from the nearest isolation areas. Alternatively said, memory holes can be grouped together to form groups based on their distance from the edge of the word line layers. This is depicted inFIG. 9which shows a portion of a block, including word line layer810between isolation area802and isolation area804. Between the isolation areas802and804are eight rows of memory holes divided into two groups based on distance to the isolation areas802/804(also known as distance to the edge922or edge920of the word line layer810). For example, a first group includes outer memory holes (and memory cells) closer to edge922or closer to edge920of the word line810. A second group includes memory holes (and memory cells) that are further from edge920and edge922of word line layer810.

The first group of memory holes and memory cells includes multiple adjacent rows of memory holes/memory cells between a pair of isolation areas1002/1004. The second group of memory cells includes two or more adjacent rows of memory holes/memory cells between pairs of isolation areas. In some embodiments, memory holes can also be referred to as memory columns. More specifically, memory columns include all the materials described above with respect toFIG. 4E.

FIG. 10shows a portion of a block which includes word line layer1000between isolation layers1002and1004. The portion of the block depicted inFIG. 10includes four rows of memory holes between isolation areas1002/1004. The memory holes are divided into a first group representing memory holes (and memory cells) closer to edges1020and1022of word line layer1000and a second group of memory holes (and memory cells) further from edges1020and1022of word line layer1000.

FIG. 11depicts a portion of a block which includes word line layer1100between isolation areas1120/1122. The portion of the block depicted inFIG. 11includes sixteen rows of memory holes between isolation areas1120and1122divided into four groups. The first group includes two rows of memory holes closest to edge of1122of word line layer1100and two memory holes closer to edge1120of word line layer1100. The second group includes two rows of memory holes that are third and fourth from the edge1120of word line layer1100and rows of memory holes that are third and fourth from edge1122of word line layer1100. The third group includes memory holes that are fifth and sixth from edge1120of word line layer100and two rows of memory holes that are fifth and sixth from edge1122of word line layer1100. The fourth group includes four rows of memory holes that are furthest from edges1120and1122. Therefore, embodiments ofFIGS. 9-11divide the rows of memory holes into groups based on distance from the edges of the word line layers.

When grouping rows of memory holes into groups within the same sub-block, rows of memory cells with similar programming speeds are placed into the same groups. In this way, memory cells on the same word line within the same group will have similar program speed. However, program speed differences for memory cells in different groups can be large, and this difference can cause program disturb for erased memory cells in the various groups that have faster programming speeds. To overcome this problem, that is to minimize variations in program speed and reduce program disturb, it is proposed that different verify reference voltages be used during the programming for different groups of memory cells. Memory cells in groups of faster programming memory cells will have the verified reference voltages set higher. Memory cells in groups of slower programming memory cells will have the verify reference voltages set lower.

In some memory systems, the programming include first programming memory cell to an intermediate verify voltage and then programming the memory cells to a final target (or final target level). Sometimes the intermediate voltage is called an offset voltage. The proposal discussed above in which different memory cells are programmed with different verified reference voltages based on whether they are in groups of fast programming memory cells closer to the isolation areas of slower programming memory cells further from the isolation areas pertains to changing the final target (final target level). The final target (final target levels) are adjusted. The faster programming memory cells and slower programming memory cells (e.g., the multiple groups) will complete programming on the same program pulse. In this way, slower programming memory cells will not cause program disturb on faster programming memory cells. Overall programming disturb inside a block will be improved as a result.

This proposal is described at a high level with respect toFIG. 12, which is a flow chart describing one embodiment of a process for programming In step1202ofFIG. 12, data is received to be stored in the nonvolatile memory. In step1204, the memory system will program different memory cells to different final targets for a common data state based on distance to one or more edge of the word line layer. The different final targets are verified reference voltages as discussed above. The common data state can be any one of data states S0-S7, discussed above. One example implementation of step1204includes applying programming to a plurality of nonvolatile memory cells connected to a word line layer (step1204a) and verifying the program of the nonvolatile memory cells by testing different memory cells being programmed to the common data state for different final target levels based on the distance to one or more edge of the word line layer (step1204b).

In some embodiments, an entire set of verified reference voltages are customized for each group of memory holes. In other embodiments, only verified reference voltages for a subset of one or more data states are adjusted.

As a result of this proposed use of different final target levels for different groups of memory cells, each group of memory cells will be programmed to slightly different threshold voltage distributions for the same data states. This is depicted inFIG. 13A, which applies to an embodiment that stores three bits of data per memory cell and has its memory holes within a sub block divided into two groups (seeFIGS. 9 and 10). That is, the groups of memory holes or groups of memory cells comprise a first group of memory cells at a first range of one or more distances from one or more edges of the word line layer and a second group of memory cells that are at a second range of one or more distances from the one or more edges edge of the word line layer. There is a range of distances because, as seen in some of the figures described above, multiple rows of memory cells can be in a common group. The second range of distances, in this example, are greater than the first range of distances. The control circuit is configured to program the first group of memory cells using the first set of target levels for first set of data states and program the second group of memory cells, at a separate time from the first group, using a second set of target levels for the same set of data states. The first set of target levels are each higher in voltage than corresponding target levels of the second set of target levels such that on completion of programming, the first group of memory cells are in a first set of threshold voltage distributions1302ofFIG. 13Aand the second group of memory cells are in a second set of threshold voltage distributions1304that are each at a lower voltage than the corresponding threshold voltage distributions in the first set of voltage distribution1302. For example, S1of distributions1304begins at a lower voltage than S1of distributions1302. That is because the final target level (verify reference voltage) used to program memory cells of the first group to S1was Vv1and the final target level (verify reference voltage) used to program memory cells of the second group to S1was Vv1-4. Since the second set of memory cells being programmed to distributions1304use lower verify levels each of the corresponding data states start at a lower voltage level. In the above discussion, the first set of target levels includes Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. The second set of target levels includes Vv1-Δ, Vv2-Δ, Vv3-Δ, Vv4-Δ, Vv5-Δ, Vv6-Δ, and Vv7-Δ.

FIG. 13Bshows threshold distributions for a system that includes four groups of memory holes/cells between isolation areas, which is depicted graphically inFIG. 11. In the embodiment ofFIGS. 11 and 13B, the first group of memory cells are programmed to the common data states using a first set of target levels, the second group of memory cells are programmed to the common data states using a second set of target levels, the third group of memory cells are programmed to the common data states using a third set of target levels, and the fourth group of memory cells are programmed to the common data states using a fourth set of target levels. The first set of target levels includes Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. The second set of target levels includes Vv1-Δ1, Vv2-Δ1, Vv3-Δ1, Vv4-Δ1, Vv5-Δ1, Vv6-Δ1, and Vv7-Δ1. The third set of target levels includes Vv1-Δ2, Vv2-Δ2, Vv3-Δ2, Vv4-Δ2, Vv5-Δ2, Vv6-Δ2, and Vv7-Δ2. The fourth set of target levels includes Vv1-Δ3, Vv2-Δ3, Vv3-Δ3, Vv4-Δ3, Vv5-Δ3, Vv6-Δ3, and Vv7-Δ3. As a result of programming the first group of memory cells using the first set of target levels, the memory cells are programmed to threshold voltage distributions1320. The result of programming the second group of memory cells using the second set of target levels results in memory cells being programmed to threshold voltage distributions1322. The result of programming the memory cells of the third group using the third set of target levels is the memory cells being programmed to threshold voltage distributions1324. The result of programming the memory cells of the fourth group of memory cells using the fourth set of target levels is the memory cells being programmed to threshold voltage distributions1326.

Threshold voltage distributions1326that are each at a lower voltage than the corresponding threshold voltage distributions in threshold voltage distributions1324. Threshold voltage distributions1324that are each at a lower voltage than the corresponding threshold voltage distributions in threshold voltage distributions1322. Threshold voltage distributions1322that are each at a lower voltage than the corresponding threshold voltage distributions in threshold voltage distributions1320.

In one embodiment, Δ or Δ1 can be 0.1 v, 0.2 v, or another small amount of voltage. In some embodiments, Δ2 is an offset that is greater than Δ1 by 0.1 v, 0.2 v, or some other small voltage. In one embodiment, Δ3 is an offset that is greater than Δ2 by 0.1 v, 0.2 v, or some other small voltage. Thus, applying the process ofFIG. 12to the memory cells or the memory holes depicted inFIG. 9 or 10result in the threshold voltage distributions1302and1304ofFIG. 13A. Performing the process ofFIG. 12on memory cells of the memory holes depicted inFIG. 11results in threshold distributions1320,1322,1324and1326ofFIG. 13B.

FIG. 14is a flow chart describing more details of one example implementation of the process ofFIG. 12. The process ofFIG. 14is used to program data for the plurality of memory cells connected to a common word line. In step1402, data is received. That data is to be stored in memory cells connected to one word line. In one example, the word line is connected to four sub-blocks, as described above. In step1404, the system programs data to be stored in a first sub block. In step1406, the system programs data to be stored in a second sub block. In step1408, the system programs data to be stored in a third sub block. In step1410, the system programs data to be stored in a fourth sub block. In one embodiment the four sub-blocks of step1404-1410correspond to the four sub-blocks SB0, SB1, SB2and SB3described above.

FIG. 15is a flow chart describing one example implementation of programming data to be stored in a sub-block. That is, the process ofFIG. 15can be used to implement any of steps1404,1406,1408and1410. The process ofFIG. 15applies to an embodiment which divides the memory holes/memory cells of a sub block into four groups such as depicted inFIG. 11. The first group of memory cells are at a first range of one or more distances from one or more edges of the word line layer. The second group of memory cells are at a second range of one or more distances from one or more edges of the word line layer. The third group of memory cells are at a third range of one or more distances from one or more edges of the word line layer. The fourth group of memory cells are at a fourth range of one or more distances from one or more edges of the word line layer. The process ofFIG. 15can be adapted for embodiments that use more or less than four groups.

In step1502ofFIG. 15, the system programs the first group of memory cells using a first set of target levels for a set data states, while inhibiting the other groups of memory cells from being programmed. Step1502includes performing the process ofFIG. 7B. In step1504, the system programs the second group of memory cells using a second set of target levels for the set of data states while inhibiting the other groups of memory cells from programming. Step1504includes performing the process ofFIG. 7B. In step1506, the system programs the third group of memory cells using a third set of target levels for the set of data states while inhibiting the other groups of memory cells from programming. Step1506includes performing the process ofFIG. 7B. In step1508, the system programs the fourth group of memory cells using a fourth set of target levels for the set of data states while inhibiting the other groups of memory cells from programming. Step1508includes performing the process ofFIG. 7B.

FIG. 16is a table which depicts the first set of target levels for the first group, the second set of target levels for the second group, the third set of target levels for the third group and the fourth set of target levels for the fourth group. Each of the target levels ofFIG. 16correspond to the final target levels and threshold voltage distributions depicted inFIG. 13B. In one embodiment, each of steps1502-1508complete programming for the different memory cells on the same number of programming voltage pulses.

The above discussion ofFIG. 15includes using different sets of target levels for each group. Each set of target levels includes separate final target levels for each data state. In some embodiments, the variation in target levels between groups can be implemented for a subset of data states (one data state, two data states, . . . ).

The discussion above includes a means for programming memory cells closer to one or more edges of the word line layer and memory cells further from one or more edges of the word line layer to a first data state representing first data such that the memory cells closer to an edge of the word line layer are programmed to a first final threshold voltage distribution using a first final verified level and memory cells further from the edges of the word line layer are programmed to a second final threshold voltage distribution using a second verified level. In this embodiment, the second verified level is lower than the first verified level and the second threshold voltage distribution is lower in voltage than the first threshold voltage distribution. The means for programming can include the various circuits depicted inFIG. 1. In some embodiments, the means for programming can also include the circuits depicted inFIG. 2. These circuits use the processes ofFIG. 7A, 7BandFIG. 12to perform the programming. Additionally,FIGS. 14 and 15provide example implementations ofFIG. 12.

One embodiment includes a non-volatile storage apparatus comprising a memory structure comprising a word line layer and a plurality of non-volatile memory cells, and a control circuit connected to the memory structure. The control circuit is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.

In one example implementation, the memory structure is a monolithic three dimensional memory structure that further comprises a plurality of dielectric layers, a plurality of memory columns and plurality of isolation areas, the word line layers are arranged alternatingly with the plurality of dielectric layers forming a stack, the memory columns extend vertically through at least a portion of the stack, the non-volatile memory cells include portions of the memory columns, edges of the word line layers are adjacent to the isolation areas, memory cells closer to the isolation areas are faster programming memory cells, and memory cells further from the isolation areas are slower programming memory cells.

One embodiment includes a non-volatile storage apparatus comprising a first word line layer, a plurality of non-volatile memory cells comprising a first group of memory cells at a first range of one or more distances from one or more edges of the first word line layer and a second group of memory cells at a second range of one or more distances from the one or more edges of the first word line layer (the second range of distances are greater than the first range of distances), and a control circuit in communication with the memory cells and the first word line layer. The control circuit is configured to program the first group of memory cells using a first target level for a first data state. The control circuit is configured to program the second group of memory cells using a second target level for the first data state. The first target level is higher in voltage than the second target level such that on completion of programming the first group of memory cells are in a first threshold voltage distribution and the second group of memory cells are in a second threshold voltage distribution that is lower in voltage than the first threshold voltage distribution.

One embodiment includes a method for programming non-volatile memory comprising applying programming to a plurality of non-volatile memory cells connected to a word line layer and verifying the programming of the non-volatile memory cells by testing different memory cells being programmed to a common data state for different final target levels based on distance to one or more edges of the word line layer.

One embodiment includes a non-volatile storage apparatus comprising a word line layer; a plurality of non-volatile memory cells; and means for programming memory cells closer to one or more edges of the word line layer and memory cells further from the one or more edges of the word line layer to a first data state representing first data such that the memory cells closer to an edge of the word line layer are programmed to a first final threshold voltage distribution using a first final verify level and the memory cells further from the one or more edges of the word line layer are programmed to a second final threshold voltage distribution using a second verify level. The second verify level is lower than the first verify level. The second final threshold voltage distribution is lower in voltage than the first threshold voltage distribution.