Scan flip-flop, method thereof and devices having the same

A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2012-0027387 filed on Mar. 16, 2012, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to a scan flip-flop, and more particularly, to a high-speed low-power scan flip-flop, an operating method thereof and data processing devices having the same.

2. Description of the Related Art

To design a high speed operation chip, designing a high speed flip-flop may be required. A related-art master-slave flip-flop is widely used due to its small size and low power consumption. However, using the master-slave flip-flop in the high-speed operating chip reaches a limit due to data-to-output latency. To improve the limit of the master-slave flip-flop, a pulse flip-flop or a semi-dynamic flip-flop is developed. However, a yield of a chip using the pulse flip-flop or the semi-dynamic flip-flop is not good because of unstable characteristics of a pulse, and it is not easy to integrate the pulse-flip-flop or the semi-dynamic flip-flop on the chip because of a long hold time.

SUMMARY

One or more exemplary embodiments provide an operating method of a scan flip-flop which performs a normal operation latching a data input and a scan operation latching a scan input, the method including, when the scan flip-flop performs the scan operation, determining an intermediate node voltage, which is a voltage at an intermediate node of the scan flip-flop, based on a clock signal, the scan input and data of a latch input node, determining the data based on the clock signal and the intermediate node voltage, and latching the data based on the clock signal.

The determining the intermediate node voltage may include: keeping an intermediate node voltage at a first phase of the clock signal to an intermediate node voltage when the clock signal transits; and determining an intermediate node voltage at a second phase of the clock signal to be synchronized with the scan input. The first phase and the second phase have opposite signal levels.

An overlap section of the clock signal and the intermediate node voltage may correspond to a half-cycle of the clock signal.

The determining data may include: sourcing a supply voltage to the latch input node based on the clock signal and the intermediate node voltage; and sinking a voltage of the latch input node to a ground based on the clock signal, the intermediate node voltage and the data input during the normal operation, and sinking the voltage of the latch input node to the ground based on the clock signal and the intermediate node voltage during the scan operation.

One or more exemplary embodiment provide a scan flip-flop which performs a normal operation latching a data input and a scan operation latching a scan input, including a first circuit, a second circuit and a latch.

The first circuit may determine an intermediate node voltage based on a clock signal, one of the data input and the scan input, and data of a latch input node.

The second circuit may determine the data based on the clock signal, the intermediate node voltage and the data input during the normal operation, and determines the data based on the clock signal and the intermediate node voltage during the scan operation. The latch may latch the data based on the clock signal.

When the scan flip-flop performs the scan operation, the first circuit may keep an intermediate node voltage at a first phase of the clock signal to an intermediate node voltage when the clock signal transits, determines an intermediate node voltage at a second phase of the clock signal to be synchronized with the scan input. The first phase and the second phase may have opposite signal levels. The second circuit may include a sourcing circuit and a sinking circuit.

The sourcing circuit may source a supply voltage to the latch input node based on the clock signal and the intermediate node voltage. The sinking circuit may sink a voltage of the latch input node to a ground based on the clock signal, the intermediate node voltage and the data input during the normal operation, and sink the voltage of the latch input node to the ground based on the clock signal and the intermediate node voltage during the scan operation.

According to an aspect of an exemplary embodiment, the first circuit may include a sourcing circuit which includes a first sub-sourcing circuit controlling a connection between a power node and the intermediate node in response to the clock signal and the scan input, and a second sub-sourcing circuit controlling the connection between the power node and the intermediate node in response to the data.

According to an aspect of another exemplary embodiment, the first circuit may include a first connection circuit controlling a connection between the intermediate node and a ground node based on the scan input and the data, and a second connection circuit controlling the connection between the intermediate node and the ground node based on a logical combination signal of a scan enable signal and the data input, the data, and the clock signal.

According to an aspect of still another exemplary embodiment, the first circuit may include a first connection circuit controlling a connection between the intermediate node and a ground node in response to the scan input and the data, and a second connection circuit controlling the connection between the first connection circuit and the ground node in response to a logical combination signal of a scan enable signal and the data input, and the clock signal.

According to an aspect of still another exemplary embodiment, the first circuit may include a first connection circuit controlling a connection between the intermediate node and a ground node in response to the scan input and the data, and a second connection circuit controlling connection between the intermediate node and the first connection circuit in response to a logical combination signal of a scan enable signal and the data input, and the clock signal.

The scan flip-flop may further include a logic circuit, which generates the scan input by performing a logical operation on a scan enable signal indicating the normal operation and the scan operation and scan data. The data input may be a parallel data including one-bit or more.

According to an aspect of still another exemplary embodiment, the first circuit may include a first keeper circuit for discharging the data based on the clock signal and the data, and a second keeper circuit for discharging the intermediate node voltage based on the clock signal and the intermediate node voltage.

According to an aspect of still another exemplary embodiment, the first circuit may include a keeper circuit for discharging the data through the second circuit based on the clock signal, the data and the intermediate node voltage.

One or more exemplary embodiments provide another scan flip-flop performing a normal operation latching a data input and a scan operation latching a scan input, including a first circuit, a second circuit, a latch and a reset circuit.

The first circuit may determine an intermediate node voltage based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit may determine the data based on the clock signal, the intermediate node voltage and the data input during the normal operation, and determines the data based on the clock signal and the intermediate node voltage during the scan operation. The latch may latch the data based on the clock signal.

The reset circuit may pull down the intermediate node voltage to a ground in response to an indication signal indicating a reset operation.

According to an exemplary embodiment, there is provided a data processing device which may include a data source outputting at least one of a scan data and a data input, and a scan flip-flop which may perform a scan operation latching a scan input related to the scan data and a normal operation latching the data input.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

A scan input of the inventive concepts means a signal generated according to a logical combination of a scan data SIN and a scan enable signal SE, or the scan data SIN itself.

FIG. 1is a schematic block diagram of a scan flip-flop according to an example embodiment. Referring toFIG. 1, a scan flip-flop10may include a first circuit20, a second circuit30, and a latch40.

The scan flip-flop10may perform selectively a normal operation, e.g., latching a data input DIN, and a scan operation, e.g., latching a scan data SIN, based on a level of a scan enable signal SE. According to an exemplary embodiment, the data input DIN may be a parallel data including one-bit or more. For example, when the level of the scan enable signal SE is a first level, e.g., a low level or a logic 0, the scan flip-flop10may perform a normal operation. In addition, when the level of the scan enable signal SE is a second level, e.g., a high level or a logic 1, the scan flip-flop10may perform a scan operation.

Hereinafter, for convenience of explanation, the first level is referred to as “L-level” and the second level is referred to as “H-level”.

The first circuit20may determine an intermediate node voltage (or a voltage level VFB) of an intermediate node based on a clock signal CK, one of a scan data SIN and a data input DIN, and data VZZ of a latch input node.

The second circuit30may determine the data VZZ of the latch input node based on the clock signal CK, the intermediate node voltage VFB of the intermediate node and the data input DIN during a normal operation. In addition, the second circuit30may determine the data VZZ of the latch input node based on the clock signal CK and the intermediate node voltage VFB of the intermediate node during a scan operation.

The latch40may latch the data VZZ of the latch input node based on the clock signal CK, e.g., a rising edge. For example, the latch40includes an input terminal IN receiving the data VZZ output from the latch input node, a control terminal CK_IN receiving the clock signal CK, and an output terminal OUT outputting an output data Q. According to an exemplary embodiment, the latch40may output the output data Q through the output terminal OUT and output an inverted output data QB through an inverted output terminal OUTB.

Here, the data VZZ may mean L-level or H-level determined based on a voltage level of the latch input node.

FIG. 2is a circuit diagram depicting an exemplary embodiment of the scan flip-flop illustrated inFIG. 1.

A scan flip-flop10-1according to an exemplary embodiment of the scan flip-flop10ofFIG. 1includes a first circuit20-1, a second circuit30-1and the latch40.

Each circuit20-1,30-1and40may be modified or changed variously as illustrated inFIGS. 7 to 33.

The first circuit20-1includes a first logic circuit20a, a first sourcing circuit20b, a first connection circuit CC1, a second connection circuit CC2, a first keeper circuit KC1, a second keeper circuit KC2and a second logic circuit G0.

The first logic circuit20agenerates a scan input INC by performing a logical combination on a scan data SIN and a scan enable signal SE.

For convenience of explanation,FIG. 2illustrates the first logic circuit20aincluding a NAND gate G3and an inverter G4; however, a structure of the first logic circuit20amay be changed variously according to exemplary embodiments.

The first logic circuit20amay mask the scan data SIN according to a level of the scan enable signal SE. For example, when the scan enable signal SE is at L-level, i.e., during a normal operation, the first logic circuit20amay block transmission of the scan data SIN. Here, an output signal INC of the first logic circuit20a, e.g., a scan input, may be at L-level.

When the scan enable signal SE is at H-level, i.e., during a scan operation, the first logic circuit20amay transmit the scan data SIN to the first circuit20-1as the scan input INC. Accordingly, without considering a delay and element characteristics of the first logic circuit20a, the scan data SIN and the scan input INC may be an identical signal during a scan operation.

During a normal operation to be explained referring toFIG. 3, a first sourcing circuit20bmay source a supply voltage Vdd to the intermediate node FB according to the clock signal CK and data VZZ of a latch input node ZZ. In addition, during a scan operation to be explained referring toFIG. 5, the first sourcing circuit20bmay source the supply voltage Vdd to the intermediate node FB according to the clock signal CK, the data VZZ of the latch input node ZZ and the scan input INC.

The first sourcing circuit20bincludes a first sub sourcing circuit P10and P11and a second sub sourcing circuit P12. The first sub sourcing circuit P10and P11controls connection of a power node and the intermediate node FB according to a level of the scan input INC and a level of the clock signal CK. Here, the ‘power node’ means a node for supplying a supply voltage Vdd.

A second sub sourcing circuit P12controls connection of the power node and the intermediate node FB according to the data VZZ of the latch input node ZZ. Each sub sourcing circuit may perform a function of a switching circuit or a pull-up circuit.

The first connection circuit CC1may control connection between the intermediate FB and a ground (or a ‘ground node’ connected to the ground) according to the scan input INC and the data VZZ of the latch input node ZZ. The first connection circuit CC1includes a transistor N10gated based on the scan input INC and the transistor N11gated based on the data VZZ of the latch input node ZZ.

The second connection circuit CC2controls connection between the first connection circuit CC1and the ground node based on an output signal B of the second logic circuit G0and the clock signal CK. The second connection circuit CC2includes a transistor N12gated according to the output signal B of the second logic circuit G0and a transistor N13gated according to the clock signal CK.

As illustrated inFIGS. 11 to 19, connections and a structure of each connection circuit CC1and CC2may be changed variously.

The first keeper circuit KC1may retain or maintain a voltage (or the data VZZ) of the latch input node ZZ which is discharged to the ground. For example, the first keeper circuit KC1includes an inverter G1and an NMOS transistor N21. When the clock signal CK is at H-level and the data VZZ of the latch input node ZZ is at L-level, the first keeper circuit KC1may keep the data VZZ of the latch input node ZZ at L-level, e.g., the ground.

As illustrated inFIGS. 7 to 9, connections and a structure of the first keeper circuit KC1may be changed variously.

The second keeper circuit KC2may retain a voltage of an intermediate node FB which is discharged to the ground. For example, the second keeper circuit KC2includes an inverter G2and an NMOS transistor N22. When the clock signal CK is at H-level and the voltage of the intermediate node FB is at L-level, the second keeper circuit KC2may keep the voltage of the intermediate node FB at L-level.

As illustrated inFIGS. 14 and 16, connections and a structure of the second keeper circuit KC2may be changed variously.

A second logic circuit G0performs a logical combination on the scan enable signal SE and the data input DIN, and generates an output signal B in accordance with a logical combination result. For example, the second logic circuit G0may be embodied in a NOR gate.

As illustrated inFIGS. 29 and 30, connections and a structure of the second logic circuit G0may be changed variously.

The second circuit30-1includes a second sourcing circuit30aand a sinking circuit30b. The second sourcing circuit30amay source the supply voltage Vdd to the latch input node ZZ based on the clock signal CK and the voltage of the intermediate node FB. The second sourcing circuit30aincludes a first sub sourcing circuit P0and a second sub sourcing circuit P1.

The first sub sourcing circuit P0may source the supply voltage Vdd to the latch input node ZZ in response to the level of the clock signal CK. The second sub sourcing circuit P1may source the supply voltage Vdd to the latch input node ZZ in response to the voltage of the intermediate node FB. According to an exemplary embodiment, the first sub sourcing circuit P0and the second sub sourcing circuit P1may be connected in parallel.

During a normal operation, the sinking circuit30bmay control sinking of the data VZZ of the latch input node ZZ to the ground based on the clock signal CK, the voltage of the intermediate node FB and the data input DIN. During a scan operation, the sinking circuit30bmay control sinking of the data VZZ of the latch input node ZZ to the ground based on the clock signal CK and the voltage of the intermediate node FB.

As illustrated inFIGS. 20 to 24, connections and a structure of the sinking circuit30bmay be changed variously. According to an exemplary embodiment, a PMOS transistor which is expressed as ‘P’ in the exemplary embodiments may be replaced with an NMOS transistor, and an NMOS transistor which is expressed as ‘N’ may be replaced with a PMOS transistor.

A sourcing circuit may be called a pull-up circuit or a connection circuit. In addition, a sinking circuit may be called a pull-down circuit or a connection circuit.

FIG. 3depicts a connection relation of elements in a normal operation of the scan flip-flop illustrated inFIG. 2, andFIG. 4is a timing diagram of input/output signals in the normal operation of the scan flip-flop illustrated inFIG. 3.

A normal operation of the scan flip-flop10is explained in detail referring toFIGS. 1 to 4. Each circuit20-2and30-2illustrated inFIG. 3illustrates a connection relation of elements (or components) included in each circuit20-1and30-1ofFIG. 2which performs the normal operation.

Hereafter, it is assumed that a ‘first phase’ is one of L level and H-level, particularly H-level, and a ‘second phase’ is the other of L-level and H-level, more particularly the L-level.

At a time point Tl, when the clock signal CK is at L-level and each of the scan enable signal SE and the data input DIN is at L-level, each transistor N0, N1, N2, N10and N13is turned off and each transistor P0, P10, P11and N12is turned on. Accordingly, each of data VZZ of the latch input node ZZ and the intermediate node voltage VFB of the intermediate node FB has H-level. Here, the latch40is assumed to output an output data Q having L-level.

At a time point T2, although the data input DIN is at H-level, each transistor N2and N13keeps an off state. Thus, each of the data VZZ and the intermediate node voltage FB keeps H-level and the latch40keeps the output data Q having L-level.

At a time point T3, when the data input DIN is at H-level, and the clock signal CK transits from L-level to H-level, each transistor N1, N2, and N3is turned on. Accordingly, the data VZZ transits from H-level to L-level.

At a time point T4, the data VZZ retains at L-level by the first keeper circuit KC1. Here, although glitch occurs in the data input DIN, the intermediate node voltage VFB retains H-level regardless of the glitch.

Since the data VZZ retains L-level, a transistor P12is turned ON and the transistor N11is turned OFF. Accordingly, the intermediate node voltage VFB retains H-level.

The latch40latches the data VZZ having L-level in response to a rising edge of the clock signal CK, and outputs an output data Q having H-level.

The latch40is illustrated to output an output data Q having the same phase as the data input DIN in response to a rising edge of the clock signal CK; however, it may output an output data having the same phase as the data input DIN or an inverted output data having an opposite phase in response to one of a rising edge and a falling edge of the clock signal CK according to an exemplary embodiment.

At a time point T5, for example, when the data input DIN retains H-level and the clock signal CK is at L-level, the transistor P0is turned on and the transistor N2is turned off. The Data VZZ transits to H-level by the transistor P0. An intermediate node voltage VFB retains H-level by each transistor P10and P11.

At a time point T6, when the clock signal CK transits from L-level to H-level, the transistor N2is turned on and the data VZZ transits to L-level. The intermediate node voltage VFB retains at H-level by the transistor P12. Here, the data VZZ having L-level retains L-level by the first keeper circuit KC1.

The latch40outputs an output data Q having H-level based on the data VZZ having L-level and a rising edge of the clock signal CK.

At a time point T7, when the data input DIN is at H-level and the clock signal CK is at L-level, the transistor P0is turned on and the transistor N2is turned off. The Data VZZ transits to H-level by the transistor P0. The intermediate node voltage VFB retains H-level by each transistor P10and P11. At a time point T8, when the data input DIN transits to L-level while the clock signal CK retains L-level, the transistor N1is turned off and the data ZZ and the intermediate node voltage VFB retain H-level.

At a time point T9, when the clock signal CK transits from L-level to H-level, the transistor N1retains an OFF state and the data VZZ retains H-level. However, each transistor N11, N12, and N13is turned on, so that the intermediate node voltage VFB transits to L-level. As the transistor P1is turned on, the data VZZ retains H-level.

The latch40latches the data VZZ having H-level based on a rising edge of the clock signal CK and outputs an output data Q having L-level.

At a time point T10, the intermediate node voltage VFB having L-level retains L-level by the second keeper circuit KC2. Although glitch occurs in the data input DIN, the intermediate node voltage VFB retains L-level by the second keeper circuit KC2regardless of the glitch. At a time point T11, when the clock signal CK is L-level, the intermediate node voltage VFB transits to H-level by each transistor P10and P11. When the data input DIN retains L-level, the transistor N1retains an OFF state. Thus, the data VZZ is not discharged and retains the H-level.

At a time point T12, each transistor N11, N12and N13is turned on, so that the intermediate node voltage VFB is discharged to L-level.

FIG. 5depicts a connection relation of elements in a scan operation of the scan flip-flop illustrated inFIG. 2, andFIG. 6is a timing diagram of input/output signals in the scan operation illustrated inFIG. 5. A scan operation of the scan flip-flop10is explained in detail referring to FIGS.1,2,5and6. During the scan operation, the scan data SIN and the scan input INC are substantially the same signals.

Each circuit20-3and30-3illustrated inFIG. 5illustrates a connection relation of elements included in each circuit20-1and30-1ofFIG. 2which performs the scan operation.

At a time point Ta, when the clock signal CK is at L-level and the scan input INC, i.e., the scan data SIN, is at H-level, each transistor N2, N13and P10is turned off and each transistor P0and N10is turned on. Since the data VZZ of the latch input node ZZ is at H-level, so that the transistor N11is turned on. Accordingly, the intermediate node voltage VFB of the intermediate node FB becomes L-level. Accordingly, the transistor N3is turned off and a transistor P1is turned on. Here, it is assumed that the latch40outputs an output data Q having L-level.

At a time point Tb, when the scan data SIN is at L-level, a transistor N10is turned off and a transistor P10is turned on. The intermediate node voltage VFB transits to H-level by each transistor P10and P11. Accordingly, the transistor N3is turned on and the transistor P1is turned off. Here, the data VZZ retains H-level according to the clock signal CK having L-level.

At a time point Tc, when the clock signal CK transits from L-level to H-level, each transistor P0and P11is turned off and each transistor N2and N13is turned on. Accordingly, the data VZZ transits from H-level to L-level. The data VZZ retains L-level by the first keeper circuit KC1.

The latch40latches the data VZZ having L-level based on a rising edge of the clock signal CK, and outputs an output data Q having H-level. As described above, the latch40may output an output data Q having a phase that is contrary to the scan data SIN but identical to the data VZZ.

At a time point Td, since each transistor N10and P11retains an off state even though glitch occurs in the scan data SIN, the glitch may not affect the intermediate node voltage VFB. At a time point Te, i.e., when the clock signal CK is at L-level, the transistor P0is turned on and the transistor N2is turned off. The data VZZ transits to H-level by the transistor P0.

In response to the clock signal CK having L-level, the transistor N13is turned off and the transistor P11is turned on. The intermediate node voltage VFB retains H-level by each transistor P10and P11. However, when the scan input SIN transits from L-level to H-level by glitch, the transistor P10is turned off and the transistor N10is turned on.

When the transistor N10is turned on by glitch while the transistor N11retains an on state, the intermediate node voltage VFB is discharged to a ground through the transistors N10and N11. That is, when the clock signal CK is at L-level, glitch included in the scan data SIN affects the intermediate node voltage VFB.

When the clock signal is at H-level, e.g., at a time point Td, the intermediate node voltage VFB is not synchronized with the scan data SIN; however, the intermediate node voltage VFB is synchronized with the scan data SIN when the clock signal CK is at L-level, e.g., at a time point Te. Here, synchronization includes a case when each phase of two signals is identical or contrary to each other.

At a time point Tf, when the clock signal CK transits from L-level to H-level, the data VZZ transits to L-level through each transistor N2and N3. The data VZZ retains L-level by the first keeper circuit KC1. The intermediate node voltage VFB retains H-level by the transistor P12. The latch40latches the data VZZ having L-level in response to a rising edge of the clock signal CK and outputs an output data Q having H-level.

An operation of a scan flip-flop10-3at a time point Tg is the same as an operation of the scan flip-flop10-3at a time point Td. When the clock signal CK is at L-level and the scan data SIN is at L-level at a time point Th, the transistor P0is turned on and the transistor N2is turned off. The data VZZ transits to H-level by the transistor P0. The intermediate node voltage VFB retains H-level by each transistor P10and P11. However, between a time point Th and a time point Ti, when the scan data SIN transits from L-level to H-level while the clock signal CK retains L-level, the transistor P10is turned off and the transistor N10is turned on.

Each transistor N10and N11is turned on, so that the intermediate node voltage VFB is discharged from H-level to L-level. Accordingly, the transistor N3is turned off and the transistor P1is turned on, so that the data VZZ retains H-level.

At a time point Tj, since the transistor N3retains an off state when the clock signal CK transits from L-level to H-level, the data VZZ retains H-level. However, each transistor N10, N11and N13is turned on, so that the intermediate node voltage VFB is discharged to L-level. Here, the second keeper circuit KC2keeps the intermediate node voltage at L-level.

The second latch40latches the data VZZ having H-level in response to a rising edge of the clock signal CK and outputs an output data Q having L-level.

At a time point Tk, the intermediate node voltage VFB retains L-level by the second keeper circuit KC2even though glitch occurs in the scan data SIN. At a time point T1, when the clock signal CK is at L-level, the data VZZ retains H-level by the transistor P0. Here, the intermediate node voltage VFB retains L-level by each transistor N10and N1and the second keeper circuit KC2. However, when the scan data SIN transits from H-level to L-level because of glitch, the transistor N10is turned off and the transistor P10is turned on. Since each transistor P10and P11is turned on, a supply voltage Vdd is supplied to the intermediate node FB. Accordingly, the intermediate node voltage VFB is changed due to glitch included in the scan data SIN.

As described above, the intermediate node voltage VFB is not synchronized with the scan data SIN when the clock signal CK is at H-level, e.g., at a time point Tk, but the intermediate node voltage VFB is synchronized with the scan data SIN when the clock signal CK is at L-level, e.g., at a time point Tl. Here, each phase of two signals SIN and VFB is contrary to each other; however, glitch of the scan data SIN affects the intermediate node voltage VFB.

At a time point Tm, when the clock signal CK transits from L-level to H-level, the data VZZ retains H-level by the transistor P1and the intermediate node voltage VFB retains L-level by the transistors N10and N11.

The latch40latches the data VZZ having H-level in response to a rising edge of the clock signal CK and outputs an output data Q having L-level.

As illustrated inFIG. 6, a result of performing an AND operation on the clock signal CK and the intermediate node voltage VFB, e.g., an overlap section, corresponds to a half cycle of the clock signal CK.

FIGS. 7 to 25are circuit diagrams depicting other exemplary embodiments of the scan flip-flop illustrated inFIG. 1. Except for a part marked in a bold line, a structure and an operation of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure and operations of each scan flip-flop10-4to10-22illustrated inFIGS. 7 to 25.

For convenience of explanation, no latch is illustrated in the scan flip-flops10-4to10-22illustrated inFIGS. 7 to 25. However, a latch input node ZZ is connected to an input terminal IN of the latch40and a clock signal CK is supplied to a control terminal.

The first keeper circuit KC1illustrated inFIG. 7includes an inverter G1and an NMOS transistor N21. Referring toFIGS. 2,3and7, a first logic circuit20amay output a scan input INC having L-level based on a scan enable signal INB (=SE) having L-level during a normal operation. In addition, the first logic circuit20amay output a scan input INC having the same phase as the scan data SIN based on the scan enable signal INB (=SE) having H-level during a scan operation.

The first logic circuit20aincludes all logic circuits which may output the scan input INC having L-level or the scan input INC having the same phase as the scan data SIN according to a level of the scan enable signal INB (=SE).

An NMOS transistor N21ofFIG. 7is gated in response to an output signal of the inverter G1, and connected between a latch input node ZZ and a first node ND1. The first node ND1is a common node of transistors N12and N13.

A first keeper circuit KC1-1illustrated inFIG. 8includes the inverter G1and the NMOS transistor N21. The NMOS transistor N21is gated in response to an output signal of the inverter G1and connected between the latch input node ZZ and a second node ND2. Referring toFIGS. 2 and 8, the second node ND2is a common node of transistors N0, N1and N2.

Referring toFIGS. 2 and 8, the first keeper circuit KC1-1may discharge the data VZZ through the second circuit30-1.

A first keeper circuit KC1-2illustrated inFIG. 9includes the inverter G1and the NMOS transistor N21. The NMOS transistor N21is gated in response to an output signal of the inverter G1and connected between the latch input node ZZ and a third node ND3. Referring toFIGS. 2 and 9, the third node ND3is a common node of transistors N2and N3.

Referring toFIGS. 2 and 9, the first keeper circuit KC1-2may discharge the data VZZ through the second circuit30-1.

FIG. 10is a circuit diagram depicting another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIG. 2, the scan input INC is supplied to the transistor P10of the first sourcing circuit20band the clock signal CK is supplied to the transistor P11of the first sourcing circuit20b. However, the scan input INC ofFIG. 10is supplied to a transistor P11′ of a sourcing circuit20b-1and a clock signal CK is supplied to a transistor P10′ of the first sourcing circuit20b-1.

FIG. 11is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 11, a first connection circuit CC1-1ofFIG. 11controls connection between the intermediate node FB and the ground node based on the scan input INC and the data VZZ of the latch input node ZZ.

The first connection circuit CC1-1includes transistors N10and N11′ connected in series between the intermediate node FB and the ground node. The data VZZ is supplied to a gate of a transistor N11′, and the scan input INC is supplied to a gate of a transistor N10.

A second connection circuit CC2-1controls connection between the intermediate node FB and the ground node based on the data VZZ, an output signal of a second logic circuit G0and the clock signal CK. The second connection circuit CC2-1includes transistors N11to N13connected in series between the intermediate node FB and the ground node. The data VZZ is supplied to a gate of a transistor N11, an output signal of the second logic circuit G0is supplied to a gate of a transistor N12, and the clock signal CK is supplied to a gate of a transistor N13.

FIG. 12is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 12, a first connection circuit CC1-2ofFIG. 12controls connection between the intermediate node FB and the ground node based on a scan input INC and data VZZ of the latch input node ZZ.

The first connection circuit CC1-2includes transistors N10and N31connected in series between the intermediate node FB and the ground node. The scan input INC is supplied to a gate of a transistor N10and the data VZZ is supplied to a gate of a transistor N31.

A second connection circuit CC2-2controls connection between the intermediate node FB and the ground node based on the data VZZ, an output signal of the second logic circuit G0and the clock signal CK. The second connection circuit CC2-2includes transistors N11to N13connected in series between the intermediate node FB and the ground node. The data VZZ is supplied to a gate of the transistor N11, an output signal of the second logic circuit G0is supplied to a gate of the transistor N12, and the clock signal CK is supplied to a gate of the transistor N13.

FIG. 13is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 13, a first connection circuit CC1-3ofFIG. 13controls connection between the intermediate node FB and the ground node based on the scan input INC and the data VZZ of the latch input node ZZ.

The first connection circuit CC1-3includes transistors N31and N10connected in series between the intermediate node FB and the ground node. The data VZZ is supplied to a gate of a transistor N31and the scan input INC is supplied to a gate of a transistor N10.

A second connection circuit CC2-3controls connection between the intermediate node FB and the ground node based on an output signal of the second logic circuit G0, the data VZZ and the clock signal CK. The second connection circuit CC2-3includes transistors N11to N13connected in series between the intermediate node FB and the ground node. An output signal of the second logic circuit G0is supplied to a gate of the transistor N11, the data VZZ is supplied to a gate of the transistor N12, and the clock signal CK is supplied to a gate of the transistor N13.

FIG. 14is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 13 and 14, except for connection of a second keeper circuit KC2-1, a structure of a scan flip-flop10-10ofFIG. 13is substantially the same as a structure of a scan flip-flop10-11ofFIG. 14. A transistor N22ofFIG. 13is connected between a common node of transistors N12and N13and the intermediate node FB. However, the transistor N22ofFIG. 14is connected between a common node of transistors N11and N12and the intermediate node.

FIG. 15is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 14and15, except for connection of a second connection circuit CC2-4and connection of the first keeper circuit KC1-1, the scan flip-flop10-11ofFIG. 14has substantially the same structure as a scan flip-flop10-12ofFIG. 15.

The second connection circuit CC2-4ofFIG. 15controls connection between the intermediate node FB and the ground node based on an output signal of the second logic circuit G0, a clock signal CK and data VZZ.

The second connection circuit CC2-4includes transistors N11to N13connected in series between the intermediate node FB and the ground node. An output signal of the second logic circuit G0is supplied to a gate of a transistor N11, the clock signal CK is supplied to a gate of a transistor N12, and the data VZZ is supplied to a gate of a transistor N13.

The first keeper circuit KC1-1is connected between the latch input node ZZ and the second node ND2. A transistor N22of the second keeper circuit KC2-1is connected between a common node of transistors N11and N12and the intermediate node FB.

FIG. 16is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 15 and 16, except for connection of a second keeper circuit KC2, a structure of the scan flip-flop10-12ofFIG. 15is equal to a structure of a scan flip-flop10-13ofFIG. 16.

A transistor N22of a second keeper circuit KC2-1ofFIG. 15is connected between a common node of transistors N11and N12and the intermediate node FB. However, a transistor N22of the second keeper circuit KC2ofFIG. 16is connected between a common node of transistors N12and N13and the intermediate node FB.

FIG. 17is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 16 and 17, except for connection of a first connection circuit CC1-4and connection of a second connection circuit CC2-5, a structure of the scan flip-flop10-13ofFIG. 16is the same as a structure of a scan flip-flop10-14ofFIG. 17.

The first connection circuit CC1-4ofFIG. 17controls connection between the intermediate node FB and the ground node based on the scan input INC and the data VZZ.

The first connection circuit CC1-4includes transistors N10and N13connected in series between the intermediate node FB and the ground node. The scan input INC is supplied to a gate of a transistor N10, and the data VZZ is supplied to a gate of a transistor N13.

The second connection circuit CC2-5controls connection between the intermediate node FB and the first connection circuit CC1-4based on an output signal of the second logic circuit G0and a clock signal CK. The second connection circuit CC2-5includes transistors N11and N12connected in series between the intermediate node FB and the first connection circuit CC1-4. An output signal of the second logic circuit G0is supplied to a gate of a transistor N11, and the clock signal CK is supplied to a gate of a transistor N12.

FIG. 18is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 17 and 18, except for connection of a second keeper circuit KC2-1, a structure of the scan flip-flop10-14ofFIG. 17is the same as a structure of a scan flip-flop10-15ofFIG. 18. A transistor N22of a second keeper circuit KC2ofFIG. 17is connected between a common node of transistors N12and N13and the intermediate node FB. However, a transistor N22of the second keeper circuit KC2-1ofFIG. 18is connected between a common node of transistors N11and N12and the intermediate node FB.

FIG. 19is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 17 and 19, except for connection of a second connection circuit CC2-6, a structure of the scan flip-flop10-14ofFIG. 17is the same as a structure of a scan flip-flop10-16ofFIG. 19. An output signal of the second logic circuit G0is supplied to a gate of the transistor N11, and a clock signal CK is supplied to a gate of the transistor N12inFIG. 17. However, the clock signal CK is supplied to a gate of the transistor N11, and an output signal of the second logic circuit G0is supplied to a gate of the transistor N12inFIG. 19.

FIG. 20is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 20, except for connection of the sinking circuit30b-1, a structure of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure of a scan flip-flop10-17ofFIG. 20.

The clock signal CK is supplied to a gate of the transistor N2, and the intermediate node FB is connected to a gate of each transistor P1and N3inFIG. 2. However, the clock signal CK is supplied to a gate of a transistor N3and the intermediate node FB is connected to a gate of each transistor P1and N2inFIG. 20.

FIG. 21is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 21, except for connection of a sinking circuit30b-2, a structure of the scan flip-flop10-1ofFIG. 2is the same as a structure of a scan flip-flop10-18ofFIG. 21.

InFIG. 2, the clock signal CK is supplied to a gate of the transistor N2, and the intermediate node FB is connected to a gate of each transistor P1and N3. However, the clock signal CK is supplied to a gate of a transistor N41, and the intermediate node FB is connected to a gate of each transistor P1and N3inFIG. 21.

FIG. 22is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 21 and 22, except for connection of a sinking circuit30b-3, a structure of the scan flip-flop10-18ofFIG. 21is the same as a structure of a scan flip-flop10-19ofFIG. 22.

InFIG. 21, the clock signal CK is supplied to a gate of the transistor N41, and the intermediate node FB is connected to a gate of each transistor P1and N3. However, the clock signal CK is supplied to a gate of a transistor N3and the intermediate node FB is connected to a gate of each transistor P1and N41inFIG. 22.

FIG. 23is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 23, except for connection of a sinking circuit30b-4, a structure of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure of a scan flip-flop10-20ofFIG. 23.

InFIG. 2, the clock signal CK is supplied to a gate of the transistor N2, and the intermediate node FB is connected to a gate of each transistor P1and N3. However, the clock signal CK is supplied to a gate of a transistor N41, and the intermediate node FB is connected to a gate of each transistor P1and N42inFIG. 23.

FIG. 24is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 24, except for connection of a sinking circuit30b-5, a structure of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure of a scan flip-flop10-21ofFIG. 24.

InFIG. 2, the clock signal CK is supplied to a gate of the transistor N2, and the intermediate node FB is connected to a gate of each transistor P1and N3. However, the clock signal CK is supplied to a gate of a transistor N42and the intermediate node FB is connected to a gate of each transistor P1and N41inFIG. 24.

FIG. 25is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 25, except for a transmission path of a scan enable signal SE and a transmission path of scan data SIN, a structure of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure of a scan flip-flop10-22ofFIG. 25.

The scan flip-flop10-22ofFIG. 25does not include a logic circuit which may perform a logical combination on the scan enable signal SE and the scan data SIN. However, the scan data SIN may be also called a scan input in this case.

The scan enable signal SE is supplied to a gate of each transistor N0, P51, and N51and a second logic circuit G0, the scan data SIN is directly supplied to a gate of each transistor P10and N10.

A transistor P51is connected between a power node and a transistor P11. A transistor N51is connected between a common node of transistors N11and N12and a transistor N10.

Each transistor N0and N51is turned off and a transistor P51is turned on during a normal operation, i.e., when a scan enable signal SE is at L-level, so that a structure of the scan flip-flop10-22ofFIG. 25becomes substantially equal to a structure of the scan flip-flop10-2ofFIG. 3. During a scan operation, i.e., when the scan enable signal SE is at H-level, each transistor P51and N12becomes turned off and a transistor N0is turned on, so that a structure of the scan flip-flop10-22ofFIG. 25becomes substantially equal to a structure of the scan flip-flop10-3ofFIG. 5.

FIG. 26Ais a schematic block diagram of the scan flip-flop according to another exemplary embodiment of the inventive concepts. Referring toFIG. 26A, a scan flip-flop10′ which may perform a reset function may include a first circuit20′, a second circuit30and a latch40.

The scan flip-flop10′ may perform a normal operation or a scan operation according to a level of the scan enable signal SE. The scan flip-flop10′ may also perform the reset operation based on an indication signal R or RN indicating a reset operation.

For example, the scan flip-flop10′ may perform a normal operation or a scan operation in response to a reset signal R having L-level. However, the scan flip-flop10′ may perform a reset operation in response to a reset signal R having H-level.

During the reset operation, a voltage of the intermediate node is at L-level, so that a transistor P1is turned on. Accordingly, the data VZZ becomes at H-level, and the latch40may output an output data Q having L-level through an output terminal OUT in response to a rising edge of the clock signal CK. According to an exemplary embodiment, the latch40may output an inverted output data QB having H-level through an inverted output terminal OUTB in response to a rising edge of the clock signal CK.

The reset signal R or an inverted reset signal RN supplied to the first circuit20′ may perform a function of an indication signal indicating a reset operation of the scan flip-flop10′.

FIG. 26Bis a circuit diagram depicting an exemplary embodiment of the scan flip-flop illustrated inFIG. 26A. Referring toFIGS. 2 and 26B, except for a reset circuit RC and a first keeper circuit KC1-3, a structure of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure of a scan flip-flop10-23ofFIG. 26B.

A reset circuit RC includes a transistor P61connected between the first sourcing circuit20band the intermediate node FB, and a transistor N61connected between the intermediate node FB and the ground node. A reset signal R is supplied to a gate of each transistor P61and N61.

The first keeper circuit KC1-3includes a transistor N62connected between a common node of transistors N12and N13and a transistor N21. An inverted reset signal RN is supplied to a gate of a transistor N62. For example, when an inverted reset signal RN having H-level is input to the first circuit20′, an inverter INV1outputs a reset signal R having L-level. Accordingly, each transistor P61and N62is turned on, so that a structure of the scan flip-flop10-23ofFIG. 26Bbecomes substantially equal to a structure of the scan flip-flop10-1ofFIG. 2.

On the contrary, when an inverted reset signal RN having L-level is input to the first circuit20′, the inverter INV1outputs a reset signal R having H-level. Accordingly, a transistor N61is turned on, so that a voltage of the intermediate node FB transits to L-level and the data VZZ of the latch input node ZZ transits to H-level.

FIG. 27is a circuit diagram depicting another exemplary embodiment of the scan flip-flop illustrated inFIG. 26A. While an inverted reset signal RN is input to the first circuit20′ inFIG. 26B, a reset signal R is input to the first circuit20′ inFIG. 27. An operation of the scan flip-flop10-23ofFIG. 26Bis substantially the same as an operation of a scan flip-flop10-24ofFIG. 27.

FIG. 28is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 26A. Referring toFIGS. 25 and 28, except for a reset circuit RC, a first keeper circuit KC1-3and an inverter INV3, a structure and an operation of the scan flip-flop10-22ofFIG. 25is substantially the same as a structure and an operation of a scan flip-flop10-25ofFIG. 28.

FIG. 29is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 29, except for a sourcing circuit30b-6and a second logic circuit G0′, a structure and an operation of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure and an operation of a scan flip-flop10-26ofFIG. 29.

A sourcing circuit30b-6includes transistors N1, NB and NC receiving a data input DIN. Transistors N1, NB and NC connected in parallel perform a function of an OR gate. Here, a transistor N1is gated according to a first bit A of the data input DIN, a transistor NB is gated according to a second bit B of the data input DIN, and a transistor NC is gated according to a third bit C of the data input DIN. In addition, the second logic circuit G0′ performs a NOR operation on a scan enable signal SE and each bit A, B and C.

FIG. 30is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 30, except for a sourcing circuit30b-7, the second logic circuit G0′ and a third logic circuit G5, a structure and an operation of the scan flip-flop10-1ofFIG. 2is substantially the same as a structure and an operation of a scan flip-flop10-27ofFIG. 30.

The sourcing circuit30b-7includes transistors N1and NB′ receiving the data input DIN. Transistors N1and NB′ connected in series perform a function of an AND gate. Here, the transistor N1is gated according to a first bit A of the data input DIN, and the transistor NB′ is gated according to a second bit B of the data input DIN.

A third logic circuit G5performs an AND operation on each bit A and B. The second logic circuit G0performs a NOR operation on a scan enable signal SE and an output signal of the third logic circuit G5.

FIG. 31is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 2 and 31, a latch40-1according to an exemplary embodiment of the latch40ofFIG. 2includes transistors P81, P82, P83, N81, N82and N83and an inverter G6. PMOS transistors P81, P82and P83perform a function of a sourcing circuit or a pull-up circuit. NMOS transistors N81, N82and N83perform a function of a sinking circuit or a pull-down circuit.

For example, referring to a time point T3ofFIG. 4, a time point T6ofFIG. 4, a time point Tc ofFIG. 6or a time point Tf ofFIG. 6, when the data VZZ is at L-level at a rising edge of the clock signal CK, each transistor P81, P82and N81is turned on and each transistor N82, N83and P83is turned off. Accordingly, the latch40-1outputs an output data Q having H-level.

In addition, referring to a time point T9ofFIG. 4or a time point Tj ofFIG. 6, when the data VZZ are at H-level at a rising edge of the clock signal CK, each transistor P81, P82and P83is turned off and each transistor N81, N82and N83is turned on. Accordingly, the latch40-1outputs an output data Q having L-level.

FIG. 32is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 1. Referring toFIGS. 31 and 32, except for an inverter G7, a structure and an operation of a latch40-2ofFIG. 32is substantially the same as a structure and an operation of the latch40-1ofFIG. 31. That is, the inverter G7outputs an inverted output data QB having a phase contrary to a phase of an output data.

FIG. 33is a circuit diagram depicting still another exemplary embodiment of the scan flip-flop illustrated inFIG. 26A. Referring toFIGS. 26B and 33, except for a latch40-3, the scan flip-flop10-23ofFIG. 26Bis substantially the same as a scan flip-flop10-30ofFIG. 33.

In addition, except for that the inverter G6of the latch40-1ofFIG. 31is changed to a NAND gate G8of the latch40-3ofFIG. 33, a structure of the latch40-1ofFIG. 31is substantially the same as a structure of the latch40-3ofFIG. 33.

Since the intermediate node FB is pulled down to a ground and the transistor P1is turned on by the reset circuit RC when the reset signal R is at H-level, i.e., when the scan flip-flop10-30is reset, the data VZZ has H-level. Since the inverted reset signal RN is at L-level, the NAND gate G8outputs a signal having H-level. Accordingly, a transistor N82is turned on in response to the data VZZ having the H-level, and a transistor N83is turned on in response to an output signal of the NAND gate G8having the H-level. Accordingly, an output signal Q transits to an initial state, e.g., L-level, regardless of a level of the clock signal CK.

Each latch40-1,40-2or40-3is an exemplary embodiment of the latch40ofFIG. 1or the latch40ofFIG. 26A.

FIG. 34is a block diagram depicting an exemplary embodiment of a data processing device including the scan flip-flop illustrated inFIG. 1or26A.

A data processing device50illustrated inFIG. 34includes a plurality of scan flip-flops10a,10b, . . . ,10c. Each of the plurality of scan flip-flops10a,10b, . . . ,10cmay be embodied in the scan flip-flop10ofFIG. 1. In addition, each of the plurality of scan flip-flops10a,10b, . . . ,10cillustrated inFIG. 34may be replaced with the scan flip-flop10′ including a reset function illustrated inFIG. 26A.

A first scan flip-flop10aincludes a first terminal D receiving a data input DIN and a second terminal SI receiving a scan data SIN. Additionally, each scan flip-flop10b, . . . ,10cincludes a terminal D receiving an output data Q and a terminal SI receiving an inverted output data QB.

For convenience of explanation,FIG. 34illustrates an exemplary embodiment where the output data Q is input to the terminal D and the inverted output data QB is input to the terminal SI directly; however, the output data Q may be input to the terminal SI and the inverted output data QB may be directly input to the terminal D according to an exemplary embodiment.

Moreover, the output data Q may be input to one of the terminal D and the terminal SI after being processed by a first logic network (not shown) according to an exemplary embodiment, and the inverted output data QB may be input to the other of the terminal D and the terminal SI after being processed by a second logic network (not shown). The first logic network and the second logic network may be the same logic networks or different logic networks.

Here, a logic network may mean a combinational logic circuit.

The data processing device50may be embodied in an integrated circuit (IC), a system on chip (SoC), a central processing unit (CPU) or a processor.

FIG. 35is a block diagram depicting another exemplary embodiment of the data processing device including the scan flip-flop illustrated inFIG. 1or26A. A data processing device100may be embodied in an IC or a SoC including a plurality of scan flip-flops10. As described above, the scan flip-flop10may be replaced with a san flip-flop10′ having a reset function.

Each of the plurality of scan flip-flops10may perform a data communication with a logic circuit120according to a clock signal CK. According to an exemplary embodiment, the logic circuit120may be embodied in a synchronous circuit or an asynchronous circuit. The logic circuit120may process a data input DIN or a scan data SIN, and output an output data Data-Out corresponding to a process result.

FIG. 36is a block diagram depicting still another exemplary embodiment of the data processing device including the scan flip-flop illustrated inFIG. 1or26A.

Referring toFIG. 36, a data processing device200may be embodied in a personal computer (PC) or a data server.

The data processing device200includes a processor100, a power source210, a storage device220, a memory230, input/output ports240, an expansion card250, a network device260and a display270. According to an exemplary embodiment, the data processing device200may further include a camera module280.

The processor100means the data processing device illustrated inFIG. 35, which is embodied in an IC or an SoC. The processor100may be a multi-core processor. The processor100may control at least one of elements100and210to280.

The power source210may supply an operation voltage to at least one of the elements100and210to280. The storage device220may be embodied in a hard disk drive (HDD) or a solid state drive (SSD).

The memory230may be embodied in a volatile memory or a non-volatile memory. According to an exemplary embodiment, a memory controller which may control a data access operation on the memory230, e.g., a read operation, a write operation (or a program operation) or an erase operation, may be integrated or embedded in the processor100. According to another exemplary embodiment, the memory controller may be embodied between the processor100and the memory230.

The input/output ports240mean ports which may transmit data to the data storage device200or transmit data output from the data storage device200to an external device. For example, the input/output ports240may be a port for connecting a pointing device like a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

The expansion card250may be embodied in a secure digital (SD) card or a multi-media card (MMC). According to an exemplary embodiment, the expansion card250may be a subscriber identification module (SIM) card or a universal subscriber identity module (USIM) card.

The network device260means a device which may connect the data storage device200with a wire network or a wireless network.

The display270may display data output from the storage device220, the memory230, the input/output ports240, the expansion card250or the network device260.

The camera module280means a module which may convert an optical image into an electrical image. Accordingly, an electrical image output from the camera module280may be stored in the storage device220, the memory230or the expansion card250. Additionally, an electrical image output from the camera module280may be displayed through the display220.

FIG. 37is a block diagram depicting still another exemplary embodiment of the data processing device including the scan flip-flop illustrated inFIG. 1or26A. Referring toFIG. 37, a data processing device300may be embodied in a laptop computer.

FIG. 38is a block diagram depicting still another exemplary embodiment of the data processing device including the scan flip-flop illustrated inFIG. 1or26A.

A data processing device400may be embodied in a portable device. The portable device400may be embodied in a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, or an e-book.

FIG. 39is a flowchart for explaining the scan operation of the scan flip-flop illustrated inFIG. 1. An operating method of the scan flip-flop10or10′ which performs the normal operation latching the data input DIN and the scan operation latching the scan input INC related to the scan data SIN is explained in detail referring toFIGS. 1 to 39.

When the scan flip-flop10or10′ performs the scan operation, the intermediate node voltage VFB of the intermediate node FB is determined based on the clock signal CK, the scan input INC (or the scan data SIN) and the data VZZ of the latch input node ZZ (S110).

Referring to the time point Td or Tk ofFIG. 6, when the clock signal CK is at H-level, the intermediate node voltage VFB retains the intermediate voltage VFB which is immediately before the clock signal CK transits to H-level at Td or Tk, respectively. Referring to the time point Te ofFIG. 6or the time point Tl ofFIG. 6, when the clock signal CK is at L-level, the intermediate node voltage VFB is determined by a voltage synchronized with the scan input INC or the scan data SIN.

The Data VZZ is determined based on the clock signal CK and the intermediate node voltage VFB (S120). The supply voltage Vdd is sourced to the latch input node ZZ based on the clock signal CK and the intermediate node voltage VFB. Accordingly, the data VZZ is determined.

During the normal operation, the voltage of the latch input node ZZ is sunk to the ground based on the clock signal CK, the intermediate node voltage VFB and the data input DIN. In addition, the voltage of the latch input node ZZ is sunk to the ground based on the clock signal CK and the intermediate node voltage VFB during the scan operation. Accordingly, the data VZZ is determined to be at L-level or H-level according to an operation of the second circuit30. The latch40latches the data VZZ based on the clock signal CK (S130).

A scan flip-flop according to an exemplary embodiment of the inventive concepts may operate with high speed and low power.