STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION

A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

DETAILED DESCRIPTION

Disclosed is an architecture for magnetic RAM (MRAM) devices and methods of integration with standard semiconductor circuit back-end-of-line (BEOL) fabrication processes. In one embodiment, the MTJ and method of forming disclosed pertain to conventional MRAM. In another embodiment, a spin-torque-transfer (STT) MRAM is disclosed.

FIG. 1shows an exemplary wireless communication system100in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration,FIG. 1shows three remote units120,130, and150and two base stations140. It will be recognized that conventional wireless communication systems may have many more remote units and base stations. Remote units120,130, and150include MRAM and/or STT MRAM memory devices125A,125B and125C, which are embodiments of the disclosure as discussed further below.FIG. 1shows forward link signals180from the base stations110and the remote units120,130, and150and reverse link signals190from the remote units120,130, and150to base stations140.

InFIG. 1, the remote unit120is shown as a mobile telephone, the remote unit130is shown as a portable computer, and the remote unit150is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, navigation devices (such as GPS enabled devices), set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. AlthoughFIG. 1illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. The disclosed device may be suitably employed in any device which includes MRAM devices.

FIG. 2is a block diagram illustrating a design workstation used for circuit, layout, and logic design of the disclosed semiconductor integrated circuit. A design workstation200includes a hard disk201containing operating system software, support files, and design software such as CADENCE or ORCAD. The design workstation200also includes a display202to facilitate design of a circuit design210. The circuit design210may be the memory circuit as disclosed above. A storage medium204is provided for tangibly storing the circuit design210. The circuit design210may be stored on the storage medium204in a file format such as GDSII or GERBER. The storage medium204may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation200includes a drive apparatus203for accepting input from or writing output to the storage medium204.

Data recorded on the storage medium204may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium204facilitates the design of the circuit design210by decreasing the number of processes for designing semiconductor ICs.

To illustrate fabrication issues in conventional MTJ structures,FIG. 3shows an implementation of an MTJ device300as may be conventionally fabricated. A metal interconnect301is formed in a via in an interlevel dielectric layer, ILD302as part of a back end of line (BEOL) process flow. The ILD302separates a magnetic tunnel junction, MTJ303, for example, from a switching device, such as a transistor.

A dielectric barrier layer304is disposed on the ILD302with a via305formed corresponding to the location of the metal interconnect301. The various layers of dielectric barriers may be formed, for example, of metal oxides, metal carbides, or metal nitrides. For example, the barrier materials may be SiOx, SiC, SiN. The choice may be made based, for example, on the requirement to be susceptible to or resistant to various etchants. The via305corresponding to the location of the metal interconnect301is formed using a first mask. A metallization to form a first electrode306may be disposed in the via305to contact the metal interconnect301.

A stack of layers forming the MTJ303are deposited on the first electrode306. The stack of layers includes a reference layer307(which may be a fixed layer and antiferro-magnet layer, not shown individually), a tunnel barrier layer308, and a free layer309. A second electrode310is provided on the free layer309. The MTJ303and second electrode310will be collectively referred to as the MTJ stack. A second (“stack”) mask and a series of etches create the MTJ stack as shown inFIG. 3. A dielectric passivation barrier layer311encapsulates the MTJ303stack, after which a planarization may be applied to level the dielectric passivation barrier layer311and expose the second electrode310.

A third metallization layer to form a third electrode312may be disposed over the planarized dielectric passivation barrier layer311, making electrical contact with the second electrode310. Metallizations to form the first, second and third electrodes306,310and312may be selected from various metals, including refractory-metals such as tantalum (Ta). Tantalum is commonly applied to the standard BEOL due to its desirable characteristics as a diffusion barrier.

A dielectric barrier layer313is disposed over the third electrode312. A third mask is then applied to pattern and define the lateral extent of the dielectric barrier layer313, the third electrode312, the dielectric passivation barrier layer311, and the first electrode306, as shown inFIG. 3.

Additional processes may include standard back-end-of-line (BEOL) processes. For example, a further dielectric layer (as a passivation or an ILD layer)314may be deposited on the dielectric barrier layer313and the dielectric barrier layer304. A via is formed in the dielectric barrier layer313and the dielectric layer314. The via is filled with a metal to provide a metal interconnect315to contact the third electrode312, as shown inFIG. 3.

Several problems may occur with the prior art structure described above with respect toFIG. 3. The first mask needs to be critically aligned with the metal interconnect301to insure the first electrode306contacts the metal interconnect301. The stack mask—to define the MTJ stack also needs to be critically aligned, to avoid placement of the MTJ stack near the metal interconnect301and the corresponding via305(formed by the first mask), and to insure proper definition and registration of the layers of the MTJ stack. A succession of critical dimension alignments from one mask to the next may exceed tolerances and have an adverse effect on yield, and thus cost,

Furthermore, the dielectric barrier layer304may be comparable to or thicker than the first electrode306. Thus, step coverage of the first electrode306may not be satisfactory due to topographical variation in the vicinity near the via305. In other words, electrical contact between the first electrode306and the metal interconnect301may be inadequate. Therefore, fabrication of the MTJ stack close to the edges of the via305should be avoided to assure that all layers of the MTJ303are uniform in thickness and flat when deposited. Otherwise the quality and reliability of the MTJ303may be adversely compromised. It may occur that some layers of the MTJ303are on the order of 1 nm, such as the barrier layer308, which is fragile and quite sensitive to topography. Increasing the lateral separation between the MTJ303and the via305to isolate the MTJ303from the topography of the via305and to ensure flatness may, however, undesirably require more substrate space. Equally important, the additional current path distance through the first electrode306from the MTJ303to the metal interconnect301will increase contact resistance, due at least to sheet resistivity of the first electrode306.

In spin torque transfer (STT) MRAM the magnetization of the free layer309is directly modulated in write mode by electrical current flowing through the junction, i.e., between the reference layer307and the free layer309by tunneling through the barrier layer308. Depending on how electrons flow, State 0 or State 1 may be written because the electron current is spin polarized, which sets the free layer polarization. As with conventional MRAM the electrical current of the device junction is determined in read mode by determining the electron tunneling resistance through the barrier layer308between two magnetic layers the reference layer307and the free layer309, whose relative polarizations may be parallel or anti-parallel

FIG. 4illustrates an MTJ device400according to one embodiment of the disclosure. In this embodiment (as described in more detail below) only one mask defines critical selected nano-scale features of the MTJ structure, but the mask alignment is not a critical dimension. The remaining masks and associated processes benefit from relaxed critical dimension requirements. The process is integration compatible with a semiconductor back-end-of-line (BEOL) process flow. Furthermore, cell scaling to smaller MTJ size may result in faster switching speed, higher drive current densities, lower absolute current and power, improved stability of the MTJ reference stack layers, and reduced stray magnetic field effects. The MTJ device400is implemented in STT MRAM although it may alternatively be applicable for conventional MRAM.

In one embodiment of the disclosure, the MTJ fabrication portion of the entire device fabrication process (i.e., including both front-end-of-line (FEOL) and back-end-of-line (BEOL) processes) is structured to allow inclusion of a process flow for formation of at least a nano-scale portion of the MTJ device (including at least a second electrode layer410, a free layer409, and a tunnel barrier layer408, described in detail below). This portion of the additional process flow uses only one mask that is critical as to feature size. The one mask is not sensitive to placement alignment. A second portion of the additional process flow uses two masks that contain larger structural elements of the MTJ device (i.e., the reference layer407(which may be a fixed antiferromagnet layer and a synthetic antiferromagnet (SAF) layer, not shown individually), a first electrode406, and a third electrode412, also described in detail below), where the mask alignment is relatively non-critical. Thus, a method of integrating an MRAM MTJ into the BEOL process flow for fabrication of integrated circuitry is provided where one device size critical dimension mask and two additional masks where placement alignment is relatively non-critical are employed.

A first mask opens a first contact via (also referred to as a seed opening)405in a dielectric barrier layer404to expose a metal interconnect401in a sub-layer, where the contact via opening may be substantially larger than the metal interconnect401. The mask allows for the large contact via opening to provide a large planar area to easily position the smaller MTJ structure in subsequent fabrication processes, thereby relaxing critical alignment registration, and improving the uniformity and stability of the to be deposited reference magnetization layer407. A first electrode406, larger than the contact via405, is formed with another mask (also referred to as the “third” mask), thus insuring overlap and contact with the metal interconnect401and to circuitry previously formed, i.e., beneath the MTJ device400, and overlapping the surrounding rim of the contact via405(formed by the dielectric barrier layer404) without requiring critical mask alignment.

The reference layer407may he patterned using the same mask as used to form the first electrode406. The reference layer407and first electrode406are larger than the nano-scale portion of the MTJ. The larger reference layer407and contact via area ensure greater stability of the fixed magnetic reference field over the lifetime of the device, and places the fringing fields at the edges of the reference layer407farther from the free layer409of the nano-scale portion of the MTJ to reduce the stray field effect.

Two advantages accrue: alignment of the first electrode406to connect to the metal interconnect401is thus a non-critical alignment, and placement of the nano-scale MTJ portion on the reference layer407is non-critical, provided the nano-scale MTJ portion is placed away from any topographical feature, such as the edge associated with the overlap of the reference layer/first electrode407/406near the rim of the barrier layer contact via405. When the metal interconnect formation process require planarization, the nano-scale MTJ portion may be positioned to avoid this area as well.

The nano-scale portion of the MTJ includes a tunnel barrier layer408and a free layer409, referred to as a “stack.” The stack may further include a second electrode410in contact with the free layer409, opposite the tunnel barrier layer408. The stack is patterned and etched using a second mask. In another embodiment, the tunnel barrier layer408is formed using the third mask, thereby making the tunnel barrier layer408substantially the same in surface area and shape as the reference layer407and the first electrode406.

A third electrode412may be patterned with the same third mask used for patterning the reference layer407and the first electrode406, which is again a non-critical alignment.

The contact via405is formed in the dielectric barrier404, and is defined by a first mask pattern. The contact via405is larger than the via305formed in the conventional structure shown inFIG. 3. The first electrode406is formed over a first interlayer dielectric (ILD)402, the dielectric barrier404, and the metal interconnect401, overlapping the edge of the large contact via405. That is, the first electrode406overlaps the rim of the dielectric barrier404that forms the boundary of the contact via405. Positioning the contact via405over the metal interconnect401is not sensitive to location with respect to the metal interconnect401, in contrast to the example of the via305and metal interconnect301shown inFIG. 3. Therefore, placement accuracy of the first mask to form the contact via405is not a critical dimension, improving the reliability and yield of this process.

The various layers of dielectric barriers included in the structure, such as the dielectric barrier404, may be formed, for example, of metal oxides, metal carbides, or metal nitrides. For example, the barrier materials may be SiOx, SiC, SiN. The choice may be made based on the desirability of being susceptible to or resisting various etchants.

The reference layer407is deposited aver the metallization from which the first electrode406is formed before any patterning occurs. Additionally, the tunnel barrier layer408, free layer409, and (optionally) a metal layer for the second electrode410may be formed over the reference layer407, successively. The layers408,409,410may be patterned in a single process with a second mask, and the layers successively etched appropriately to form the MTJ “stack.” Whereas the dimensions of the stack may be nano-scale, and have a critical dimension, placement of the mask is not a critical dimension. Provided the area of the contact via405has been chosen to be appropriately large, the stack can be formed within and away from the stepped edges of the first electrode406and the reference layer407at the rim of via contact via405. The stack may also be positioned over the location of the metal interconnect401if dishing in the metal interconnect401is not significant.

As an example of dimensions appropriate for an exemplary STT MRAM MTJ, for 65 nm and 45 nm technology nodes, the metal interconnect401may be on the order of 70 nm. The first electrode406and reference layer407my have dimensions where the planar portion defined by the via contact via405are at least 70 mm. The cell size of the MRAM may be affected by the size of the first electrode406or the third electrode412. Therefore, the contact via405may be larger than the via305. The critical dimension registration is further relaxed, as long as conductive contact exists between the first electrode406and the metal interconnect401.

The MTJ device400includes a second (local) dielectric passivation barrier layer411to isolate the stack, and a third electrode layer412. The third mask, which is non-critical in alignment and is larger than the contact via405, patterns the MTJ structure from the third electrode layer412down to the first electrode406. The MTJ device400also includes a global dielectric passivation barrier layer416to encapsulate the layers previously formed and etched. The global dielectric passivation barrier layer416inhibits contaminant penetration into (or from) the critical layers of the junction, including the electrodes406,410,412, the fixed reference layer407, the free layer409, and the tunnel barrier layer408.

The MTJ device400is completed with subsequent processes that may substantially be a BEOL process flow, e.g., to planarize the structure and provide electrical connectivity to other circuitry, with, for example a metal interconnect415. It may be appreciated that metal interconnects401and415may be applied as source and bit lines.

FIG. 5illustrates an exemplary process500for forming of the MTJ device400according to one embodiment. Process1is the point at which the method of forming the MTJ device400is inserted into the standard BEOL process flow, and process8is the point at which the conventional BEOL process flow continues.

Process1: A substrate comprising the ILD402with a through hole via containing the metal interconnect401, is over coated with the first dielectric passivation barrier layer404. A first mask pattern opens the contact via405of a selected size, at least overlapping and larger than the metal interconnect401. Then the substrate is over-coated with a succession of layers: an electrode layer metallization for the first electrode406, the magnetization reference layer407, the tunnel barrier layer408, the free layer409, and a second metallization layer for the second electrode410.

Process2: A second mask pattern (“stack” mask), defines the critical (or nano scale) portion of the MTJ device. In one embodiment, the size of the critical portion is smaller than the contact via405. In this embodiment, the second electrode410, the free layer409and the tunnel barrier layer408are patterned based upon the second mask. As only a few layers are etched and a relatively thinner portion of the MTJ is processed, this etching process is easier to control, e.g., with respect to undercutting, over-etching etc., and the process is inherently self-aligned. In this embodiment, the tunnel barrier layer408is patterned with the second mask pattern. In another embodiment (not shown), the tunnel barrier layer408is patterned with a third mask pattern, as described in Process6. The second mask may be configured to pattern the critical portion in the shape of an ellipse to enhance the polarization alignment/anti-alignment between the free layer409and the magnetization reference layer407in the two polarization states. In one embodiment, a portion of the reference layer407is etched during the second mask process. For example all or a portion of the SAF layer may be etched. If all of the synthetic antiferromagnet (SAF) layer is etched, a small portion of the fixed antiferromagnet layer may also be etched.

Process3: After the critical portion of MTJ device400is defined, the second dielectric passivation barrier layer411is deposited to insulate and encapsulate the critical portion. The second dielectric passivation barrier layer411may commonly be silicon nitride, silicon oxide or another dielectric material. It can be the same material as the dielectric passivation barrier layer404, or another insulating material, depending on characteristics of other fabrication processes.

Process4: The deposited second dielectric passivation barrier411surface is planarized to expose the second electrode410.

Process5: Because the dimensions of the second electrode410may be small, i.e., nano-scale, an additional metallization is deposited on the surface of the substrate to be later patterned to form the third electrode412. The third electrode412contacts the second electrode410.

Process6: A third mask process patterns a cell of the MTJ device400, from the third electrode412down to the first electrode406, and including the second dielectric passivation barrier411. A series of material selective etches may be applied to provide the net cell shape (as determined by the third mask) from the third electrode412vertically down to, but not including, the dielectric barrier layer404. AlthoughFIG. 4shows the same mask process for patterning the third electrode412, a different mask may be optionally used to form a third electrode with a different shape and size, if desired.

Process7: A global dielectric passivation barrier layer416is then deposited over the entire exposed surface, to further “cap” the structure formed in Process6. The global dielectric passivation barrier layer416can be the same material as the dielectric barrier layer404, or it can be different. Exemplary materials include silicon carbide, silicon nitride, silicon oxide, and a combination thereof.

Process8: A second interlayer dielectric (ILD)414is deposited over the global dielectric passivation barrier layer416and planarized, if deposited with an over-burden, to expose a portion of the passivation barrier layer416directly over the nano scale MTJ structure. The planarized ILD414may serve as a substrate upon which to build additional levels of device functionality within the BEOL process flow. The same mask (i.e., the second mask) used to pattern the MTJ stack, or another mask, may optionally be used to pattern a contact via in the dielectric passivation barrier layer416formed in Process7. Alternatively, another BEOL specified mask may be used. The contact via permits formation of the metal interconnect415. The mask registration is not critical, and need not be placed directly over the MTJ stack. However, contact resistance my be reduced by such direct placement.

It may be appreciated that the structure and method disclosed are “manufacture friendly,” in that only one of the three masks is used to define critical dimension elements. Moreover, alignment registration of the three masks is not a critical dimension requirement. In addition, it becomes easier to control the polarization of the free layer during memory operation because of a much larger reference layer, which provides a more uniform fixed magnetization field.

A further advantage is improved scalability: fabrication of smaller MTJ structures for the critical free layer portion permits higher drive current density (with lower absolute current) resulting in faster switching, while stability is improved by the larger reference layer.

A still further advantage is the improved yield, because the method is less susceptible to process induced defects and damage that may otherwise occur where critical dimension registration among a greater number of masks is required.