Semiconductor device having jumper pattern

According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor device.

DISCUSSION OF RELATED ART

Logic cells of a semiconductor device are provided as part of a standard-cell library to design a semiconductor integrated circuit structure for performing a particular function. The logic cells may be optimized to particular requirements and are pre-designed in various manners. The pre-designed logic cells are called standard cells. Such standard cells are used in designing semiconductor circuits.

In using standard cells, there is a limitation in a design rule. As integrated semiconductor devices shrink in size, a critical dimension of the design rule decreases, and a minimum distance between patterns is required to prevent electrical short between internal patterns. To secure the minimum distance, it is necessary to meet requirements including critical dimension uniformity, a line edge roughness (LER) of a pattern, and so on.

SUMMARY

According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.

According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. A first active fin and a second active fin are spaced apart from each other in a first direction. Each of the first active fin and the second active fin extends in the first direction. A third active fin is spaced apart from the first active fin in a second direction crossing the first direction. A trench is disposed between the first active fin and the second active fin. A field insulation layer is disposed in the trench. A jumper pattern is disposed on the first active fin, the third active fin and the field insulation layer. The jumper pattern connects electrically the first active fin and the third active fin.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the inventive concept will be described below in detail with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness of layers and regions may be exaggerated for clarity. It will also be understood that when an element is referred to as being “on” another element or substrate, it may be directly on the other element or substrate, or intervening layers may also be present. It will also be understood that when an element is referred to as being “coupled to” or “connected to” another element, it may be directly coupled to or connected to the other element, or intervening elements may also be present. Like reference numerals may refer to the like elements throughout the specification and drawings.

As a semiconductor integrated circuit design is becoming complicated, a semi-custom design, which is a computer-based automatic design, is widely used. A semi-custom design refers to a method for developing a desired circuit by preparing a plurality of standard basic circuits in advance and automatically designing logic cells thereof using a computer. An exemplary semi-custom design is a design using a standard cell.

In a standard cell method, a complicated logic circuit formed by combining basic circuits is optimally designed and is pre-registered as a standard cell in the database of a computer. In a case of designing a semiconductor integrated circuit, a desired circuit may be implemented by combining various standard cells registered in the database. The respective standard cells have a constant cell height and appropriate standard cells are arranged in multiple columns, thereby designing an integrated circuit.

As an integration level of semiconductor integrated circuits is increases, shrinkage of a standard cell size is required. In general, the shrinkage of the standard cell size can be achieved by reducing sizes of transistors included in each standard cell. However, if the sizes of transistors included in each standard cell are uniformly reduced, desired functions may not be implemented. In general, since only the lowest level metal is used in the standard cell, the complexity in designing the lowest level metal may increase, resulting in an increase in the standard cell size.

If the standard cell layout according to the present inventive concept is employed, routing congestion of a plurality of metal wires may be avoided while reducing the standard cell size. For example, in the metal wire design, a space on a diffusion preventing region positioned in a lower layer is used, thereby increasing space utilization efficiency in the metal wire design. In addition, capacitance is lowered by reducing use of a back-end-of-line (BEOL) interconnector, thereby reducing power consumption and a gate delay.

FIG. 1is an exemplary layout view of a semiconductor chip including standard cells, andFIG. 2is a circuit view of a single standard cell.

Referring toFIG. 1, a semiconductor chip SC may include a standard cell region5and an input/output cell region6. The semiconductor chip SC may include a plurality of standard cells5ain the standard cell region5. The semiconductor chip SC may include a pad in the input/output cell region6to receive/output a signal from/to the outside. The input/output cell region6may be formed around the standard cell region5.

The plurality of standard cells5amay be arranged in a matrix type in the standard cell region5. A system on chip (SOC) may use a standard cell library, and a central processing unit (CPU), a random access memory (RAM), a first-in first-out (FIFO), a small computer system interface (SCSI), sea of gate (SOG), or the like, may be formed in the standard cell region5.

An exemplary circuit formed in the standard cell5awill now be described with reference toFIG. 2. For example,FIG. 2illustrates a partial circuit of a buffer formed in the standard cell5a. The partial circuit may include an output port and a driver. The output port may include, for example, a first CMOS inverter C1including a first PMOS transistor PT1and a first NMOS transistor NT1. The driver may include, for example, a second CMOS inverter C2including a second PMOS transistor PT2and a second NMOS transistor NT2, and a third CMOS inverter C3including a third PMOS transistor PT3and a third NMOS transistor NT3.

An output of the second CMOS inverter C2including the second PMOS transistor PT2and the second NMOS transistor NT2may be applied to the first NMOS transistor NT1as an input, and an output of the third CMOS inverter C3including the third PMOS transistor PT3and the third NMOS transistor NT3may be applied to the first PMOS transistor PT1as an input.

In the circuit shown inFIG. 2, if a high-level signal is input to the third CMOS inverter C3and the second CMOS inverter C2, a high-level signal is also output from the first CMOS inverter C1disposed at the output port. If a low-level signal is input to the third CMOS inverter C3and the second CMOS inverter C2, a low-level signal is also output from the first CMOS inverter C1disposed at the output port.

If a low-level signal is input to the third CMOS inverter C3and a high-level signal is input to the second CMOS inverter C2, the first CMOS inverter C1is put into a floating state. For example, the first CMOS inverter C1is put into a high-impedance state.

FIG. 3is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept, andFIG. 4is a cross-sectional view taken along line A1-A2ofFIG. 3.

Referring toFIGS. 3 and 4, the semiconductor device1may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, and first to fifth contacts211to215.

Here, the third gate line31and the fourth gate line41may be dummy gate lines, a diffusion preventing region may be disposed between the third gate line31and the fourth gate line41, and a field insulation layer110may be formed in the diffusion preventing region.

As shown, the plurality of active regions ACT11, ACT12, ACT21, and ACT22may be arranged in a matrix type, but aspects of the present inventive concept are not limited thereto. For example, the first active region ACT11and the second active region ACT12may be alternately arranged in a first direction X1. Alternatively, the first active region ACT11and the third active region ACT21may be alternately arranged in a second Y1. The field insulation layer110may be formed between the first active region ACT11and the second active region ACT12and between the third active region ACT21and the fourth active region ACT22to define active regions.

One or more fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42may be arranged in the plurality of active regions ACT11, ACT12, ACT21, and ACT22. For example, the plurality of fins F1, F12, and F13may be arranged in the first active region ACT11, the plurality of fins F2, F21, and F22may be arranged in the second active region ACT12, the plurality of fins F3, F31, and F32may be arranged in the third active region ACT21, and the plurality of fins F4, F41, and F42may be arranged in the fourth active region ACT22.

Some fins, (for example, F1and F2) may be arranged to be spaced apart at a first distance d1in a lengthwise direction (in the second direction Y1inFIG. 3). Some fins (for example, F1, F12, and F13) may be arranged to be spaced apart at a second distance d2in a widthwise direction (in the first direction X1inFIG. 3).

For example, the second distance d2between adjacent active regions (for example, between ACT11and ACT21or between ACT12and ACT22) may be greater than the first distance d1between the first fin F1and the second fin F2, which are adjacent with each other in the lengthwise direction active region (for example, in the first direction Y1).

The plurality of gate lines11,21,31,41,51, and61may extend lengthwise in the first direction X1. As described above, the third gate line31and the fourth gate line41as dummy gate lines may extend lengthwise in the first direction X1.

Referring toFIG. 3, the plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42may extend lengthwise in the second direction Y1. The fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42may be some portions of the substrate101or may include an epitaxial layer grown from the substrate101. InFIG. 3, two fins F1and F2are arranged to be spaced apart from each other in the lengthwise direction. The present inventive concept is not limited thereto.

Referring toFIG. 4, a deep trench DT may be formed between the fin12and the fin21, and the inside of the deep trench DT may be filled by the field insulation layer110to form a diffusion preventing region. The field insulation layer110may be formed on the substrate101, filling the deep trench DT and contacting an end surface of each of the plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42.

Referring back toFIG. 3, the field insulation layer110may extend lengthwise in the first direction X1. The field insulation layer110may be an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. Unlike inFIG. 4, the field insulation layer110may be formed on only a portion of the trench DT.

The plurality of gate lines11,21,31,41,51, and61may be formed to intersect the corresponding fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42on the fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42. For example, the first to third gate lines11,21, and31may be formed on the first fin F1and the fourth to sixth gate lines41,51, and61may be formed on the second fin F2.

The third gate line31may be formed on the corresponding field insulation layer110. In addition, the fourth gate line41may be formed on the corresponding field insulation layer110. The third gate line31may be formed on the fin F1, crossing the fin F1. The fourth gate line41may be formed on the fin F2, crossing the fin F2. As described above, a structure formed between adjacent fins (for example, between F1and F2), including the field insulation layer110and two dummy gate lines formed thereon (that is, the third gate line31and the fourth gate line41), may be referred to as a double diffusion break.

Referring back toFIG. 4, each gate line (for example, the gate line31) may include metal layers MG1and MG2. As shown, the third gate line31may include two or more metal layers MG1and MG2stacked one on another. The first metal layer MG1may control a work function of a transistor and the second metal layer MG2may fill a space formed by the first metal layer MG1. The first metal layer MG1may include, for example, at least one of TiN, TaN, TiC, and TaC. In addition, the second metal layer MG2may include, for example, W or Al. The third gate line31may be formed by, for example, a replacement process or a gate last process, but aspects of the present inventive concept are not limited thereto.

The dummy gate lines (for example, the third gate line31and the fourth gate line41) may have structures similar to those of other gate lines11,21,51, and61. For example, the gate lines11,21,51, and61may also include two or more metal layers MG1and MG2stacked one on another, like the dummy gate lines (for example, the third gate line31and the fourth gate line41). For example, the first metal layer MG1may control a work function of a transistor and the second metal layer MG2may fill a space formed by the first metal layer MG1.

A gate insulation layer345may be formed between the fin F12and each of the metal layers MG1and MG2. The gate insulation layer345may include a high-k dielectric material having a higher dielectric constant than a silicon oxide layer. For example, the gate insulation layer345may include, for example, HfO2, ZrO2or Ta2O5.

Sources/drains161may be disposed between two adjacent gate lines, or may be disposed between a gate line (e.g.,21) and the dummy gate line (e.g.,31).

The sources/drains161may be an elevated sources/drain protruding above a top surface of the fin F12.

In addition, the sources/drains161may be formed to partly overlap a spacer351.

If the semiconductor device1ofFIG. 4is a P-type metal-oxide-semiconductor (PMOS) transistor, the sources/drains161may include a compressive stress material. For example, the compressive stress may include a material (for example, SiGe) having a larger lattice constant than Si. The compressive stress material may increase the mobility of carriers of a channel region by applying compressive stress to the fin F12.

If the semiconductor device1ofFIG. 4is an N type metal-oxide-semiconductor (NMOS) transistor, the sources/drains161may include the same material as the substrate101or a tensile stress material. For example, if the substrate101includes Si, the sources/drains161may include Si or a material (for example, SiC) having a smaller lattice constant than Si.

In an exemplary embodiment, the sources/drains161may be formed by doping impurity into the fin F12.

The spacer351may include at least one of a nitride layer and an oxynitride layer. The spacer351may insulate the metal layers MG1and the MG2and the sources/drains161from each other.

The substrate101may be, for example, a semiconductor substrate. The substrate101may include at least one of silicon, strained Si, silicon alloy, silicon carbide (SiC), silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium, germanium alloy, gallium arsenide (GaAs), indium arsenide (InAs), III-V semiconductor and II-VI semiconductor, a combination thereof, and a stacked layer thereof. In addition, the substrate101may be an organic plastic substrate. The following description will be made on the assumption that the substrate100includes silicon.

The substrate101may be of a P type or an N type. In some exemplary embodiments of the present inventive concept, an insulating substrate may be used as the substrate101. For example, a silicon on insulator (SOI) substrate may be used as the substrate101. In this case, the semiconductor device1may operate faster than a semiconductor device formed on a silicon substrate.

The gate pickup region GPR may be formed between the first active region ACT11and the third active region ACT21and between the second active region ACT12and the fourth active region ACT22. The gate pickup region GPR may extend in the second direction Y1, for example. A gate pickup insulation layer and a gate pickup electrode may be additionally formed in the gate pickup region GPR. The gate pickup insulation layer may include silicon oxide. In addition, the gate pickup electrode may include a conductive material, such as doped polysilicon. For example, the gate pickup insulation layer may also be formed to surround bottom and side surfaces of the gate pickup electrode. In an exemplary embodiment, the gate pickup insulation layer may surround completely bottom and side surfaces of the gate pickup electrode.

The first jumper pattern201may be disposed to intersect a top portion of the third gate line31, overlapping the first active region ACT11and the field insulation layer110. For example, the first jumper pattern201may be an interconnect pattern formed on the fin F1and the fin F12, connecting the fin F1and the fin F12to each other.

Referring toFIG. 4, the first juniper pattern201may be formed on the field insulation layer110to cover the third gate line31. A first interlevel insulation layer IL1may be formed between the first jumper pattern201and the sources/drains161. In addition, a second interlevel insulation layer IL2may be formed on the first interlevel insulation layer IL1.

The first interlevel insulation layer IL1and the second interlevel insulation layer IL2may be used to electrically insulate the sources/drains161from the first jumper pattern201. The first interlevel insulation layer IL1and the second interlevel insulation layer IL2may be formed using silicon oxide, such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), or high density plasma-CVD (HDP-CVD). A top surface of the first interlevel insulation layer IL1and a top surface of the third gate line31may be coplanar with each other.

The first to fifth contacts211to215may be used to electrically connect a plurality of fins. For example, the first contact211may be used to electrically connect the fins F1, F12, and F13to each other, the second contact212may be used to electrically connect the fins F21and F22to each other, the third contact213may be used to electrically connect the fins F2and F21to each other, the fourth contact214may be used to electrically connect the fins F3and F31, and the fifth contact215may be used to electrically connect the fins F4and F41.

The first jumper pattern201may be connected to additional via contacts or metal wires to provide various signal routing paths for designing a standard cell structure. Accordingly, design complexity of the metal wires, cell capacitance may be lowered, or power consumption may be reduced.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present inventive concept will be described.

FIG. 5is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor device1ofFIGS. 3 and 4will be omitted.

The first jumper pattern201may be connected to additional via contacts or metal wires to provide a variety of signal routing paths for designing a semiconductor device using a standard cell structure. Accordingly, design complexity of the metal wires, cell capacitance may be lowered, or power consumption can be reduced.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present inventive concept will be described.

Referring toFIG. 5, the semiconductor device2may include a first jumper pattern201including a first contact pattern202, a second contact pattern203, and a first bridge pattern204, and a blocking pattern120may be formed between the first bridge pattern204and the third gate line31.

The first contact pattern202and the second contact pattern203may vertically pass through a first interlevel insulation layer IL1and a second interlevel insulation layer IL2to be in contact with a source/drain161adjacent to a side portion of the third gate line31. The first contact pattern202and the second contact pattern203may further include a barrier layer. The barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (TiW) or other barrier metals.

A contact electrode may be formed on the barrier layer, and the contact electrode may include titanium (Ti), titanium nitride (TiN), an aluminum compound, a tungsten compound, tungsten (W), copper (Cu) or other metals. The first contact pattern202and the second contact pattern203may include the barrier layer and the contact electrode.

The first bridge pattern204may electrically connect the first contact pattern202and the second contact pattern203. In an exemplary embodiment, the first bridge pattern204may include a barrier layer and a contact electrode. As described above, the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium tungsten (TiW) or other barrier metal, and the contact electrode may include titanium (Ti), titanium nitride (TiN), an aluminum compound, a tungsten compound, tungsten (W), copper (Cu) or other metals.

The first bridge pattern204may be in direct contact with a blocking pattern120. The lowest surface of the first bridge pattern204may have a width greater than that of the blocking pattern120to be in contact with the contact patterns202and203.

The blocking pattern120may include a conductive material. For example, the blocking pattern120may include metal having higher resistance than the second metal layer. MG2. The blocking pattern120may include tungsten silicide (WSi), titanium nitride (TiN), tantalum nitride (TaN), titanium silicide nitride (TiSiN), or tantalum silicide nitride (TaSiN).

FIG. 6is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor devicesFIGS. 4 and 5will be omitted.

Referring toFIG. 6, the semiconductor device3may include a second jumper pattern205which is in contact with a blocking pattern120, a source/drain161and the field insulation layer110. In this case, a top surface and sidewalls of the blocking pattern120may be surrounded by the jumper pattern205.

For example, the first contact pattern202, the second contact pattern203and the first bridge pattern204ofFIG. 5may be integrally formed into the second jumper pattern205. The second jumper pattern205is formed to intersect a top portion of the third gate line31, and the blocking pattern120may be formed between the second jumper pattern205and the third gate line31.

FIG. 7is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor devices ofFIGS. 4, 5 and 6will be omitted.

Referring toFIG. 7, the semiconductor device4may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, first to sixth contacts211to216, and a second bridge pattern311.

The second bridge pattern311may electrically connect the fourth contact214and the sixth contact216. The fourth contact214, the sixth contact216, and the second bridge pattern311may form an U-shaped connection.

The fourth contact214may electrically connect the fin F31and the fin F32to each other, and the sixth contact216may be formed on the field insulation layer110. The fourth contact214and the sixth contact216may include titanium (Ti), titanium nitride (TiN), an aluminum compound, a tungsten compound, tungsten (W), copper (Cu) or other metals. In an exemplary embodiment, metal wires may be formed on the second bridge pattern311through a via contact to provide a signal routing path.

FIG. 8is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient explanation, descriptions of substantially the same content as that of the semiconductor devices ofFIGS. 4 to 7will be omitted.

Referring toFIG. 8, the semiconductor device5may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, first to fifth contacts211to215, a first connection pattern217, and a first gate fin312.

The first connection pattern217is a conductive pattern formed only on the field insulation layer110without overlapping the first to fourth active regions ACT11, ACT12, ACT21, and ACT22. The first connection pattern217may electrically connect the first jumper pattern201and the first gate fin312.

The first gate fin312may be formed in the gate pickup region GPR and may intersect the third to fifth gate lines31,41, and51. The first gate fin312may be used to pick up the fifth gate line51, and a via contact and a metal wire may be formed on the fifth gate line51to be used in designing a standard cell.

FIG. 9is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor devices1-5ofFIGS. 4-8will be omitted.

Referring toFIG. 9, the semiconductor device6may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, first to fifth contacts211to215, a first gate fin312, a first via contact411, and a first metal wire M1.

The first gate fin312may be formed in the gate pickup region GPR and may intersect the third to fifth gate lines31,41, and51. The first gate fin312may be used to pick up the fifth gate line51. A first via contact411may be formed on a region where the first gate fin312overlaps the field insulation layer110, and a first metal wire M1may be formed on the first via contact411. Using connection structures including the first metal wire M1, the first via contact411and the first gate fin312, the fifth gate line51is connected electrically to the201.

FIG. 10is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, the description of substantially the same content as that of the semiconductor devices1to6ofFIGS. 4 to 9will be given.

Referring toFIG. 10, the semiconductor device7may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, first to fifth contacts211to215, a seventh contact218, an eighth contact219, and a third bridge pattern313.

The seventh contact218may be formed in the first active region ACT11and may electrically connect the fin F1and the fin F12. The eighth contact219may be formed in the field insulation layer110and may be formed to be adjacent with the seventh contact218. The seventh contact218and the eighth contact219may include titanium (Ti), titanium nitride (TiN), an aluminum compound, a tungsten compound, tungsten (W), copper (Cu) or other metals. The third bridge pattern313may electrically connect the seventh contact218and the eighth contact219. Metal wires may formed on the third bridge pattern313through a via contact to provide a signal routing path.

FIG. 11is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor devices1to7ofFIGS. 4 to 10will be omitted.

Referring toFIG. 11, the semiconductor device8may a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, first to fifth contacts211to215, a ninth contact220, a second via contact221, a third via contact222, and a fourth bridge pattern314.

The fourth contact214may be formed in the third active region ACT21and may electrically connect the fin F3and the fin F31. The ninth contact220may be formed in the field insulation layer110and may be formed to be adjacent with the fourth contact214. The fourth contact214and the ninth contact220may include titanium (Ti), titanium nitride (TiN), an aluminum compound, a tungsten compound, tungsten (W), copper (Cu) or other metals.

The fourth bridge pattern314may electrically connect the fourth contact214and the ninth contact220, and the fourth bridge pattern314and the fourth contact214may be electrically connected through the second via contact221. In addition, the fourth bridge pattern314may be electrically connected to the ninth contact220through the third via contact222.

FIG. 12is a layout view of a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenient description, descriptions of substantially the same content as that of the semiconductor devices1to8ofFIGS. 4 to 11will be given.

Referring toFIG. 12, the semiconductor device9may include a substrate101, a first active region ACT11, a second active region ACT12, a third active region ACT21, a fourth active region ACT22, a gate pickup region GPR, first to sixth gate lines11,21,31,41,51, and61, a plurality of fins F1to F4, F12, F13, F21, F22, F31, F32, F41, and F42, a first jumper pattern201, first to fifth contacts211to215, a ninth contact220, a second via contact221, a third via contact222, a fourth bridge pattern314, and a second metal wire M11.

The second metal wire M11may be formed only on the field insulation layer110, overlapping only the field insulation layer110. The second metal wire M11is electrically connected to the fourth bridge pattern314, thereby providing a signal routing path.

FIG. 13is a view of a semiconductor device according to an exemplary embodiment of the present inventive concept andFIG. 14is a view of a semiconductor device according to an exemplary embodiment of the present inventive concept. Hereinafter, descriptions of the same content as that in the previous exemplary embodiments will be omitted, and the following description will focus on differences between the present and previous embodiments.

First, referring toFIG. 13, the semiconductor device10may include a logic region1410and a static random access memory (SRAM) forming region1420. A first transistor1411may be disposed in the logic region1410and a second transistor1421may be disposed in the SRAM forming region1420.

In an exemplary embodiment of the present inventive concept, the first transistor1411and the second transistor1421may have different conductivity types. Alternatively, the first transistor1411and the second transistor1421may have the same conductivity type. The semiconductor device10may include the semiconductor devices1to9according to an exemplary embodiment of the present inventive concept.

Next, referring toFIG. 14, the semiconductor device11may include a logic region1410, and third and fourth transistors1412and1422, which are different from each other, may be disposed in the logic region1410. Although not shown, third and fourth transistors1412and1422, which are different from each other, may be disposed in an SRAM forming region as well.

In an exemplary embodiment of the present inventive concept, the third transistor1412and the fourth transistor1422may have different conductivity types. Alternatively, the third transistor1412and the fourth transistor1422may have the same conductivity type. The semiconductor device11may include the semiconductor devices1to9according to an exemplary embodiment of the present inventive concept.

Referring back toFIG. 13, the logic region1410and the SRAM forming region1420are illustrated, but aspects of the present inventive concept are not limited thereto. For example, the present inventive concept may also be applied to the logic region1410and a region where other types of memories are formed. For example, the semiconductor device10may include a dynamic random access memory (DRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), or a phase-change memory (PRAM).

FIG. 15is a block diagram of a system-on-a-chip (SoC) system including a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 15, the SoC system1000may include an application processor1001and a DRAM1060.

The application processor1001may include a central processing unit (CPU)1010, a multimedia system1020, a multilevel interconnect bus1030, a memory system1040, and a peripheral circuit1050.

The CPU1010may perform arithmetic operations necessary for operating the SoC system1000. In an exemplary embodiment of the present inventive concept, the CPU1010may include a multi-core environment including two or more cores.

The multimedia system1020may be used in performing a variety of multimedia functions in the SoC system1000. The multimedia system1020may include a three-dimensional (3D) engine module, a video codec, a display system, a camera system, and a post-processor.

The multilevel interconnect bus1030may be used in performing data communication among the CPU1010, the multimedia system1020, the memory system1040, and the peripheral circuit1050. In an exemplary embodiment of the present inventive concept, the multilevel interconnect bus1030may have a multi-layered structure. For example, the bus1030may include a multi-layer advanced high-performance bus (AHB), or a multi-layer advanced eXtensible interface (AXI), but aspects of the present inventive concept are not limited thereto.

The memory system1040may provide environments necessary for high-speed operation by connecting the AP1001to an external memory (for example, the DRAM1060). In an exemplary embodiment of the present inventive concept, the memory system1040may include a separate controller (for example, a DRAM controller) for controlling the external memory (for example, the DRAM1060).

The peripheral circuit1050may provide environments necessary for connecting the SoC system1000to an external device (for example, a main board). Accordingly, the peripheral circuit1050may include various kinds of interfaces enabling the external device connected to the SoC system1000to be compatibly used.

The DRAM1060may function as a working memory required to operate the AP1001. In an exemplary embodiment of the present inventive concept, as illustrated, the DRAM1060may be disposed outside the AP1001. For example, the DRAM1060may be packaged with the AP1001in the form of a package on package (PoP).

At least one of components of the SoC system1000may employ a semiconductor device according to an exemplary embodiment of the present inventive concept.

Next, an electronic system including semiconductor devices according to an exemplary embodiment of the present inventive concept will be described with reference toFIG. 16.

FIG. 16is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring toFIG. 16, the electronic system1100may include a controller1110, an input/output device (I/O)1120, a memory device1130, an interface1140and a bus1150.

The controller1110, the I/O1120, the memory device1130, and/or the interface1140may be connected to each other through the bus1150. The bus1150corresponds to a path through which data moves.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements having functions similar to those of these elements. The I/O1120may include a key pad, a key board, a display device, and so on. The memory device1130may store data and/or commands. The interface1140may perform functions of transmitting data to a communication network or receiving data from the communication network. The interface1140may be wired or wireless. For example, the interface1140may include an antenna or a wired/wireless transceiver, and so on.

Although not illustrated, the electronic system1100may further include high-speed DRAM and/or SRAM as the working memory for the operation of the controller1110. Here, a semiconductor device according to an exemplary embodiment of the present inventive concept may be employed as the working memory. In addition, a semiconductor device according to an exemplary embodiment of the present inventive concept may be provided in the memory device1130or may be provided in the controller1110or the I/O1120.

The electronic system1100may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic device for transmitting and/or receiving information in a wireless environment.

FIGS. 17 to 19show electronic devices including a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG. 17shows a tablet PC (1200),FIG. 18shows a notebook computer (1300), andFIG. 19shows a smart phone (1400). At least one of the semiconductor devices1to9according to some exemplary embodiments of the present inventive concept may be employed to a tablet PC1200, a notebook computer1300, a smart phone1400, and the like.

Aspects of the present inventive concept are not limited thereto. For example, the electronic devices may be implemented as a computer, an ultra mobile personal computer (UMPC), a work station, a net-book, a personal digital assistant (PDA), a portable computer, a wireless phone, a mobile phone, an e-book, a portable multimedia player (PMP), a potable game console, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, or the like.